From 96dc62d8dc0db58005011009b4f5fbf6838c926d Mon Sep 17 00:00:00 2001 From: woody Date: Wed, 24 Dec 2025 17:21:08 +0900 Subject: [PATCH] add IPL --- .../Mobis/Gen4_ICUMX_Loader/.gitignore | 2 + IPL/Customer/Mobis/Gen4_ICUMX_Loader/Makefile | 667 ++ .../Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_s4.c | 2468 +++++++ .../Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4h.c | 4084 ++++++++++++ .../Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4m.c | 3552 ++++++++++ .../Mobis/Gen4_ICUMX_Loader/common/crc32.c | 0 .../Mobis/Gen4_ICUMX_Loader/common/log/log.c | 100 + .../Mobis/Gen4_ICUMX_Loader/common/log/scif.c | 625 ++ .../common/scmt_checkpoint.c | 126 + .../common/timer/micro_wait.c | 109 + .../Gen4_ICUMX_Loader/common/timer/scmt.c | 108 + .../Mobis/Gen4_ICUMX_Loader/cpu_on/cpu_on.c | 237 + IPL/Customer/Mobis/Gen4_ICUMX_Loader/dos.mk | 734 ++ IPL/Customer/Mobis/Gen4_ICUMX_Loader/env.ini | 7 + .../Gen4_ICUMX_Loader/image_load/android_ab.c | 309 + .../Gen4_ICUMX_Loader/image_load/image_load.c | 535 ++ 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| 141 + .../tools/sw_min_ver_tbl/tfmv_ver_tbl.ld | 60 + IPL/Customer/Mobis/V4H_Cx_Loader/Makefile | 593 ++ .../Mobis/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4h.c | 323 + .../Mobis/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4m.c | 318 + .../V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4h.c | 3434 ++++++++++ .../V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4m.c | 3020 +++++++++ .../Mobis/V4H_Cx_Loader/common/crc32.c | 273 + .../Mobis/V4H_Cx_Loader/common/log/log.c | 264 + .../Mobis/V4H_Cx_Loader/common/log/scif.c | 172 + .../V4H_Cx_Loader/common/scmt_checkpoint.c | 0 .../Mobis/V4H_Cx_Loader/common/string.c | 84 + .../common/timer/generic_timer.c | 177 + .../Mobis/V4H_Cx_Loader/common/timer/scmt.c | 0 .../Mobis/V4H_Cx_Loader/cpu_on/cpu_on.c | 304 + .../V4H_Cx_Loader/image_load/android_ab.c | 336 + .../V4H_Cx_Loader/image_load/image_load.c | 494 ++ .../V4H_Cx_Loader/include/access_protection.h | 37 + .../Mobis/V4H_Cx_Loader/include/android_ab.h | 51 + .../include/android_bootloader_message.h | 256 + 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| 108 + .../renesas/rcar/drivers/iic_dvfs/iic_dvfs.c | 402 ++ .../renesas/rcar/drivers/iic_dvfs/iic_dvfs.h | 45 + .../plat/renesas/rcar/drivers/io/io_memdrv.c | 236 + .../plat/renesas/rcar/drivers/io/io_rcar.c | 620 ++ .../rcar/drivers/memdrv/rcar_console.S | 98 + .../renesas/rcar/drivers/memdrv/rcar_printf.c | 169 + .../renesas/rcar/drivers/memdrv/rcar_printf.h | 43 + .../renesas/rcar/drivers/pwrc/rcar_pwrc.c | 286 + .../renesas/rcar/drivers/pwrc/rcar_pwrc.h | 79 + .../renesas/rcar/drivers/rpc/rpc_driver.c | 84 + .../plat/renesas/rcar/drivers/scif/scif.S | 323 + .../renesas/rcar/drivers/timer/bl2_swdt.c | 201 + .../plat/renesas/rcar/include/avs_driver.h | 44 + .../renesas/rcar/include/bl2_axi_register.h | 272 + .../plat/renesas/rcar/include/bl2_cpg_init.h | 38 + .../renesas/rcar/include/bl2_cpg_register.h | 135 + .../renesas/rcar/include/bl2_dma_register.h | 67 + .../plat/renesas/rcar/include/bl2_int_error.h | 41 + .../renesas/rcar/include/bl2_lifec_register.h | 305 + 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+ .../rcar/qos/H3/ES10/qos_init_h3_es10.c | 409 ++ .../rcar/qos/H3/ES10/qos_init_h3_es10.h | 37 + .../rcar/qos/H3/WS11/qos_init_h3_ws11.c | 593 ++ .../rcar/qos/H3/WS11/qos_init_h3_ws11.h | 37 + .../renesas/rcar/qos/M3/qos_init_m3_es10.c | 601 ++ .../renesas/rcar/qos/M3/qos_init_m3_es10.h | 37 + .../Dummy_BL33/plat/renesas/rcar/qos/qos.mk | 54 + .../plat/renesas/rcar/qos/qos_init.c | 130 + .../plat/renesas/rcar/qos/qos_init.h | 37 + .../Dummy_BL33/plat/renesas/rcar/rcar_def.h | 279 + .../plat/renesas/rcar/rcar_io_storage.c | 442 ++ .../Dummy_BL33/plat/renesas/rcar/rcar_pm.c | 388 ++ .../plat/renesas/rcar/rcar_private.h | 172 + .../plat/renesas/rcar/rcar_topology.c | 223 + .../plat/renesas/rcar/rcar_version.h | 42 + IPL/SDK/v3m/src/Dummy_BL33/readme.md | 162 + .../Dummy_BL33/services/spd/opteed/opteed.mk | 39 + .../services/spd/opteed/opteed_common.c | 128 + .../services/spd/opteed/opteed_helpers.S | 103 + .../services/spd/opteed/opteed_main.c | 443 ++ .../services/spd/opteed/opteed_pm.c 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.../V4H_Cx_Loader/include/emmc_registers.h | 174 + .../v4h/src/V4H_Cx_Loader/include/emmc_std.h | 312 + IPL/SDK/v4h/src/V4H_Cx_Loader/include/gic.h | 417 ++ .../V4H_Cx_Loader/include/hscif_register.h | 61 + .../src/V4H_Cx_Loader/include/image_load.h | 243 + .../V4H_Cx_Loader/include/image_load_emmc.h | 113 + .../src/V4H_Cx_Loader/include/inline_asm.h | 55 + .../v4h/src/V4H_Cx_Loader/include/interrupt.h | 56 + .../src/V4H_Cx_Loader/include/ip_control.h | 51 + .../src/V4H_Cx_Loader/include/loader_main.h | 85 + .../include/loader_main_common.h | 43 + .../V4H_Cx_Loader/include/loader_mmu_table.h | 80 + IPL/SDK/v4h/src/V4H_Cx_Loader/include/log.h | 98 + .../v4h/src/V4H_Cx_Loader/include/mem_io.h | 104 + IPL/SDK/v4h/src/V4H_Cx_Loader/include/qos.h | 33 + .../V4H_Cx_Loader/include/ram_protection.h | 150 + .../v4h/src/V4H_Cx_Loader/include/rcar_def.h | 66 + .../src/V4H_Cx_Loader/include/rcar_register.h | 157 + .../src/V4H_Cx_Loader/include/rst_register.h | 65 + .../v4h/src/V4H_Cx_Loader/include/rtvram.h | 35 + .../V4H_Cx_Loader/include/rtvram_register.h | 92 + IPL/SDK/v4h/src/V4H_Cx_Loader/include/scif.h | 51 + .../src/V4H_Cx_Loader/include/scif_register.h | 60 + .../src/V4H_Cx_Loader/include/secure_boot.h | 60 + .../v4h/src/V4H_Cx_Loader/include/string.h | 51 + IPL/SDK/v4h/src/V4H_Cx_Loader/include/swdt.h | 105 + IPL/SDK/v4h/src/V4H_Cx_Loader/include/timer.h | 51 + IPL/SDK/v4h/src/V4H_Cx_Loader/include/types.h | 70 + .../src/V4H_Cx_Loader/ip/ddr/boot_init_dram.h | 36 + IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/ddr.mk | 12 + .../src/V4H_Cx_Loader/ip/ddr/dram_sub_func.c | 36 + .../src/V4H_Cx_Loader/ip/ddr/dram_sub_func.h | 33 + .../ip/ddr/v4h/lpddr5/boot_init_dram.c | 4613 +++++++++++++ .../ip/ddr/v4h/lpddr5/boot_init_dram_config.c | 194 + .../ip/ddr/v4h/lpddr5/boot_init_dram_config.h | 236 + .../ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h | 203 + .../ip/ddr/v4h/lpddr5/ddr_regdef.h | 269 + .../ip/ddr/v4h/lpddr5/ecc_enable_v4h.c | 183 + .../ip/ddr/v4h/lpddr5/ecc_enable_v4h.h | 111 + .../ip/ddr/v4h/lpddr5/ecm_enable_v4h.c | 260 + .../ip/ddr/v4h/lpddr5/ecm_enable_v4h.h | 42 + .../ip/ddr/v4h/lpddr5/init_dram_tbl_v4h_lp5.h | 1753 +++++ .../ip/ddr/v4m/lpddr5/boot_init_dram.c | 4542 +++++++++++++ .../ip/ddr/v4m/lpddr5/boot_init_dram_config.c | 240 + .../ip/ddr/v4m/lpddr5/boot_init_dram_config.h | 156 + .../ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h | 165 + .../ip/ddr/v4m/lpddr5/ddr_regdef.h | 390 ++ .../ip/ddr/v4m/lpddr5/ecc_enable_v4m.c | 171 + .../ip/ddr/v4m/lpddr5/ecc_enable_v4m.h | 116 + .../ip/ddr/v4m/lpddr5/ecm_enable_v4m.c | 265 + .../ip/ddr/v4m/lpddr5/ecm_enable_v4m.h | 47 + .../ip/ddr/v4m/lpddr5/init_dram_tbl_v4m_lp5.h | 1654 +++++ .../v4h/src/V4H_Cx_Loader/ip/emmc/emmc_boot.c | 95 + .../v4h/src/V4H_Cx_Loader/ip/emmc/emmc_cmd.c | 622 ++ .../v4h/src/V4H_Cx_Loader/ip/emmc/emmc_init.c | 320 + .../V4H_Cx_Loader/ip/emmc/emmc_interrupt.c | 239 + .../src/V4H_Cx_Loader/ip/emmc/emmc_mount.c | 1592 +++++ .../V4H_Cx_Loader/ip/emmc/emmc_multiboot.c | 94 + .../v4h/src/V4H_Cx_Loader/ip/emmc/emmc_read.c | 216 + .../src/V4H_Cx_Loader/ip/emmc/emmc_utility.c | 305 + IPL/SDK/v4h/src/V4H_Cx_Loader/ip/interrupt.c | 102 + IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ip_control.c | 89 + IPL/SDK/v4h/src/V4H_Cx_Loader/ip/qos/qos.c | 553 ++ .../v4h/src/V4H_Cx_Loader/ip/rtvram/rtvram.c | 81 + IPL/SDK/v4h/src/V4H_Cx_Loader/ip/swdt/swdt.c | 123 + .../v4h/src/V4H_Cx_Loader/loader/asm_macros.S | 55 + .../V4H_Cx_Loader/loader/loader_exceptions.S | 207 + .../src/V4H_Cx_Loader/loader/loader_main.c | 479 ++ .../V4H_Cx_Loader/loader/loader_main_common.c | 244 + .../V4H_Cx_Loader/loader/loader_mmu_table.c | 1086 +++ .../v4h/src/V4H_Cx_Loader/loader/loader_s4.S | 336 + .../v4h/src/V4H_Cx_Loader/loader/loader_s4.ld | 140 + .../v4h/src/V4H_Cx_Loader/loader/loader_v4h.S | 381 ++ .../src/V4H_Cx_Loader/loader/loader_v4h.ld | 137 + .../v4h/src/V4H_Cx_Loader/loader/loader_v4m.S | 375 ++ .../src/V4H_Cx_Loader/loader/loader_v4m.ld | 129 + IPL/SDK/v4h/src/V4H_Cx_Loader/loader/stack.S | 48 + .../protect/region_id/region_id.c | 439 ++ .../src/V4H_Cx_Loader/secure/secure_boot.c | 507 ++ 2302 files changed, 455822 insertions(+) create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/.gitignore create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/Makefile create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_s4.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4h.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4m.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/crc32.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/log/log.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/log/scif.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/scmt_checkpoint.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/timer/micro_wait.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/timer/scmt.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/cpu_on/cpu_on.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/dos.mk create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/env.ini create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/android_ab.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/image_load.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/image_load_emmc.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/image_load_flash.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/access_protection.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/android_ab.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/android_bootloader_message.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ap_system_core_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/avs.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/axmm_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/bit.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cnf_tbl.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpg.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpg_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpu.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpu_on.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/crc.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/dma.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/dma_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_boot.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_config.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_def.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_hal.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_multiboot.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_registers.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_std.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/fcpr.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/fcpr_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/gpio.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/hscif_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/i2c.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/i2c_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/image_load.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/image_load_emmc.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/image_load_flash.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/inline_asm.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/intc.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/intc_id.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ip_control.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/loader_main.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/loader_main_common.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/log.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mcu_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mem_io.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mfis.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mfis_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/micro_wait.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/pfc.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/pfc_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/qos.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ram_def.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ram_protection.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rcar_def.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/remap.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/remap_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rom_api.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rpc.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rpc_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rpcqspidrv.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rst_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rtsram_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rtvram.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rtvram_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/san.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scif.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scif_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt_checkpoint.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt_config.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/spiflash2drv.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/sysc.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/types.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/vect_set.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/wdt.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/wdt_register.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/intc/intc.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/intc/vect_set.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/intc/vecttbl.S create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/avs/avs.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/cpg/cpg.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/boot_init_dram.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/ddr.mk create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_regdef.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ddr_regdef.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/init_dram_tbl_s4.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/dma/dma.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_boot.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_cmd.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_init.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_interrupt.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_mount.c create mode 100644 IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_multiboot.c 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IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ddr_regdef.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/init_dram_tbl_s4.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/dma/dma.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_boot.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_cmd.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_init.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_interrupt.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_mount.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_multiboot.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_read.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_utility.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/fcpr/fcpr.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/i2c/i2c.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ip_control.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/mfis/mfis.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/qos/qos.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/rpc/rpc.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/rtvram/rtvram.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/sysc/sysc.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/wdt/wdt.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/icumx_loader.ld create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/icumx_loader_v4m.ld create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader.S create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_common.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_s4.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_v4h.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_v4m.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/codesram_ecc.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/codesram_ecc.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/loader_main_mcu.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/loader_main_mcu.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/sdmac.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/sdmac.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/sdmac_register.h create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/protect/ram_protection.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/protect/region_id.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/protect/stack_protect.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/remap/remap.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/rom_api/rom_api.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/s4/sa9.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/s4/sa9.ld create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/sa0.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/sa0.ld create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4h/sa9.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4h/sa9.ld create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4m/sa9.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4m/sa9.ld create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/ntfmv_ver_tbl.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/ntfmv_ver_tbl.ld create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/tfmv_ver_tbl.c create mode 100644 IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/tfmv_ver_tbl.ld create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/Makefile create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4h.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4m.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4h.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4m.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/common/log/log.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/common/log/scif.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/common/string.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/common/timer/generic_timer.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/cpu_on/cpu_on.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/image_load/image_load.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/access_protection.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/axmm_register.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/cnf_tbl.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/cpu_on.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_boot.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_config.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_def.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_hal.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_multiboot.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_registers.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_std.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/gic.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/hscif_register.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/image_load.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/image_load_emmc.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/inline_asm.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/interrupt.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/ip_control.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/loader_main.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/loader_main_common.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/loader_mmu_table.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/log.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/mem_io.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/qos.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/ram_protection.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/rcar_def.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/rcar_register.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/rst_register.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/rtvram.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/rtvram_register.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/scif.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/scif_register.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/secure_boot.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/string.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/swdt.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/timer.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/include/types.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/boot_init_dram.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/ddr.mk create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/dram_sub_func.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/dram_sub_func.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ddr_regdef.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/init_dram_tbl_v4h_lp5.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ddr_regdef.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/init_dram_tbl_v4m_lp5.h create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_boot.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_cmd.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_init.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_interrupt.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_mount.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_multiboot.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_read.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_utility.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/interrupt.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ip_control.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/qos/qos.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/rtvram/rtvram.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/ip/swdt/swdt.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/loader/asm_macros.S create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_exceptions.S create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_main.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_main_common.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_mmu_table.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_s4.S create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_s4.ld create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4h.S create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4h.ld create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4m.S create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4m.ld create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/loader/stack.S create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/protect/region_id/region_id.c create mode 100644 IPL/SDK/v4h/src/V4H_Cx_Loader/secure/secure_boot.c diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/.gitignore b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/.gitignore new file mode 100644 index 0000000..3a0c7df --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/.gitignore @@ -0,0 +1,2 @@ +build +obj.bat diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/Makefile b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/Makefile new file mode 100644 index 0000000..d863000 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/Makefile @@ -0,0 +1,667 @@ +#/******************************************************************************* +# * DISCLAIMER +# * This software is supplied by Renesas Electronics Corporation and is only +# * intended for use with Renesas products. No other uses are authorized. This +# * software is owned by Renesas Electronics Corporation and is protected under +# * all applicable laws, including copyright laws. +# * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +# * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +# * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +# * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +# * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +# * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +# * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +# * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +# * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +# * Renesas reserves the right, without notice, to make changes to this software +# * and to discontinue the availability of this software. By using this software, +# * you agree to the additional terms and conditions found by accessing the +# * following link: +# * http://www.renesas.com/disclaimer +# * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved. +# *******************************************************************************/ +# +# ******************************************************************************* +# * DESCRIPTION : makefile for Loader +# ****************************************************************************** + +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +INCLUDE_DIR = -Iinclude \ + -Iip/ddr + +OUTDIR := build + +# LSI setting common define +RCAR_S4 := 0 +RCAR_V4H := 1 +RCAR_V4M := 2 +$(eval $(call add_define,RCAR_S4)) +$(eval $(call add_define,RCAR_V4H)) +$(eval $(call add_define,RCAR_V4M)) +ifneq ("$(FORCE_115200)", "") +$(eval $(call add_define,FORCE_115200)) +endif + +#/* Select LSI("S4" or "V4H" or "V4M" )******************************** +ifeq ("$(LSI)", "") +LSI = S4 +endif + +ifeq (${LSI},S4) + RCAR_LSI:=${RCAR_S4} + DIR_NAME_SA9 = s4 + OBJ_FILE += loader/loader_main_s4.o \ + cnf_tbl/cnf_tbl_s4.o \ + ip/qos/qos.o \ + ip/rtvram/rtvram.o \ + ip/ddr/s4/lpddr4x/ecc_enable_s4.o + INCLUDE_DIR += -Imcu + include ip/ddr/ddr.mk +else ifeq (${LSI},V4H) + RCAR_LSI:=${RCAR_V4H} + DIR_NAME_SA9 = v4h + OBJ_FILE += loader/loader_main_v4h.o \ + ip/fcpr/fcpr.o \ + cnf_tbl/cnf_tbl_v4h.o \ + ip/ddr/v4h/lpddr5/ecc_enable_v4h.o \ + ip/ddr/v4h/lpddr5/ecm_enable_v4h.o +else ifeq (${LSI},V4M) + RCAR_LSI:=${RCAR_V4M} + DIR_NAME_SA9 = v4m + OBJ_FILE += loader/loader_main_v4m.o \ + ip/fcpr/fcpr.o \ + cnf_tbl/cnf_tbl_v4m.o \ + ip/sysc/sysc.o \ + ip/avs/avs.o \ + ip/i2c/i2c.o \ + ip/ddr/v4m/lpddr5/ecc_enable_v4m.o \ + ip/ddr/v4m/lpddr5/ecm_enable_v4m.o +else + $(error "Error: ${LSI} is not supported.") +endif +$(eval $(call add_define,RCAR_LSI)) + +# +# timing measurement +# +ifeq ("$(MEASURE_TIME)", "") + MEASURE_TIME = 0 +else + $(eval $(call add_define,MEASURE_TIME)) + #Set log level to Error, so we dont waste time with unnecessary prints + ifndef LOG_LEVEL + LOG_LEVEL := 1 + endif + OBJ_FILE += common/scmt_checkpoint.o \ + common/timer/scmt.o +endif +ifeq ("$(MEASURE_TIME_NOPRINT)", "") + MEASURE_TIME_NOPRINT = 0 +else + $(eval $(call add_define,MEASURE_TIME_NOPRINT)) +endif + +################################################### + +#output file name +FILE_NAME = icumx_loader +FILE_NAME_SA0 = bootparam_sa0 +FILE_NAME_SA9 = cert_header_sa9 +FILE_NAME_TFMV_TBL = tfmv_ver_tbl +FILE_NAME_NTFMV_TBL = ntfmv_ver_tbl + +OUTPUT_FILE = $(FILE_NAME).elf +OUTPUT_FILE_SA0 = $(FILE_NAME_SA0).elf +OUTPUT_FILE_SA9 = $(FILE_NAME_SA9).elf +OUTPUT_FILE_TFMV_TBL = $(FILE_NAME_TFMV_TBL).elf +OUTPUT_FILE_NTFMV_TBL = $(FILE_NAME_NTFMV_TBL).elf + +#object file name +OBJ_FILE += cpu_on/cpu_on.o \ + common/log/log.o \ + common/log/scif.o \ + common/timer/micro_wait.o \ + image_load/image_load.o \ + intc/intc.o \ + intc/vecttbl.o \ + intc/vect_set.o \ + ip/ip_control.o \ + ip/cpg/cpg.o \ + ip/emmc/emmc_boot.o \ + ip/wdt/wdt.o \ + loader/loader.o \ + loader/loader_main_common.o \ + protect/ram_protection.o \ + protect/region_id.o \ + protect/stack_protect.o \ + remap/remap.o \ + rom_api/rom_api.o + +OBJ_FILE_SA0 = tools/dummy_create/sa0.o +OBJ_FILE_SA9 = tools/dummy_create/$(DIR_NAME_SA9)/sa9.o +OBJ_FILE_TFMV_TBL = tools/sw_min_ver_tbl/tfmv_ver_tbl.o +OBJ_FILE_NTFMV_TBL = tools/sw_min_ver_tbl/ntfmv_ver_tbl.o + +#linker script name +ifeq (${LSI},V4M) + MEMORY_DEF = loader/icumx_loader_v4m.ld +else + MEMORY_DEF = loader/icumx_loader.ld +endif + +MEMORY_DEF_SA0 = tools/dummy_create/sa0.ld +MEMORY_DEF_SA9 = tools/dummy_create/$(DIR_NAME_SA9)/sa9.ld +MEMORY_DEF_TFMV_TBL = tools/sw_min_ver_tbl/tfmv_ver_tbl.ld +MEMORY_DEF_NTFMV_TBL = tools/sw_min_ver_tbl/ntfmv_ver_tbl.ld + +################################################### + +# Debug build +DEBUG:=0 + +# Process DEBUG flag +$(eval $(call assert_boolean,DEBUG)) +$(eval $(call add_define,DEBUG)) +ifeq (${DEBUG},0) + $(eval $(call add_define,NDEBUG)) +CFLAGS += -Onone +else +ASFLAGS += -G -dwarf2 +CFLAGS += -G -dwarf2 -Odebug +endif + +# MISRA Option +#------ MISRA ------ +ifndef MISRA +MISRA := MANDATORY +endif +ifeq ("$(MISRA)", "DISABLE") + MISRA_OPTION = DISABLE +else ifeq ("$(MISRA)", "FULL") + MISRA_OPTION = FULL +else ifeq ("$(MISRA)", "MANDATORY") + MISRA_OPTION = MANDATORY +else ifeq ("$(MISRA)", "REQUIRED") + MISRA_OPTION = REQUIRED +endif +CFLAGS_MISRA_FULL = \ + --misra_adv=warn \ + --misra_req=warn \ + --misra_mand=warn \ + --no_misra_runtime \ + --misra_2012=all,-R1.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later +CFLAGS_MISRA_REQUIRED = \ + --misra_adv=silent \ + --misra_req=warn \ + --misra_mand=warn \ + --no_misra_runtime \ + --misra_2012=all,-R1.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later +CFLAGS_MISRA_MANDATORY = \ + --misra_adv=silent \ + --misra_req=silent \ + --misra_mand=warn \ + --no_misra_runtime \ + --misra_2012=all,-R1.1,-R3.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later + # MISRA 2012 Rule 3.1 is confirmed with static analysis +ifeq ("$(MISRA_OPTION)", "FULL") +CFLAGS += $(CFLAGS_MISRA_FULL) +else ifeq ("$(MISRA)", "REQUIRED") +CFLAGS += $(CFLAGS_MISRA_REQUIRED) +else ifeq ("$(MISRA)", "MANDATORY") +CFLAGS += $(CFLAGS_MISRA_MANDATORY) +endif + +# Process LOG_LEVEL +ifndef LOG_LEVEL +LOG_LEVEL := 2 +endif +$(eval $(call add_define,LOG_LEVEL)) +ifeq (${LOG_LEVEL},0) + LDFLAGS += -nostdlib +endif + +# Process SET_FCPR_PARAM flag +# 0:Disable, 1:Enable (Support V4H / V4M Linux OS) +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef SET_FCPR_PARAM + SET_FCPR_PARAM := 0 + $(eval $(call add_define,SET_FCPR_PARAM)) + else + ifeq (${SET_FCPR_PARAM},0) + $(eval $(call add_define,SET_FCPR_PARAM)) + else ifeq (${SET_FCPR_PARAM},1) + $(eval $(call add_define,SET_FCPR_PARAM)) + else + $(error "Error:SET_FCPR_PARAM=${SET_FCPR_PARAM} is not supported.") + endif + endif +else + SET_FCPR_PARAM := 0 + $(eval $(call add_define,SET_FCPR_PARAM)) +endif + +# Process BOOT_MCU flag (S4 only) +# 0:None, 1:G4MH, 2:Reserved, 3:G4MH+ICUMH +ifeq (${LSI},S4) + ifndef BOOT_MCU + BOOT_MCU :=3 + $(eval $(call add_define,BOOT_MCU)) + else + ifeq (${BOOT_MCU},0) + $(eval $(call add_define,BOOT_MCU)) + else ifeq (${BOOT_MCU},1) + $(eval $(call add_define,BOOT_MCU)) + else ifeq (${BOOT_MCU},2) + $(eval $(call add_define,BOOT_MCU)) + else ifeq (${BOOT_MCU},3) + $(eval $(call add_define,BOOT_MCU)) + else + $(error "Error:BOOT_MCU=${BOOT_MCU} is not supported.") + endif + endif +else + BOOT_MCU :=0 + $(eval $(call add_define,BOOT_MCU)) +endif + +ifneq (${BOOT_MCU},0) +OBJ_FILE += mcu/cpu_on_for_mcu.o \ + mcu/sdmac.o \ + mcu/loader_main_mcu.o \ + mcu/image_load_for_mcu.o \ + mcu/codesram_ecc.o +endif + +# Process RTVRAM_EXTEND flag +ifeq (${LSI},S4) + ifndef RTVRAM_EXTEND + RTVRAM_EXTEND := 1 + $(eval $(call add_define,RTVRAM_EXTEND)) + else + ifeq (${RTVRAM_EXTEND},0) + $(eval $(call add_define,RTVRAM_EXTEND)) + else ifeq (${RTVRAM_EXTEND},1) + $(eval $(call add_define,RTVRAM_EXTEND)) + else + $(error "Error:RTVRAM_EXTEND=${RTVRAM_EXTEND} is not supported.") + endif + endif +endif + +# Process QSPI_DDR_MODE flag +# 0:SDR, 1:DDR +ifndef QSPI_DDR_MODE +QSPI_DDR_MODE := 0 +$(eval $(call add_define,QSPI_DDR_MODE)) +else + ifeq (${QSPI_DDR_MODE},0) + $(eval $(call add_define,QSPI_DDR_MODE)) + else ifeq (${QSPI_DDR_MODE},1) + $(eval $(call add_define,QSPI_DDR_MODE)) + else + $(error "Error:QSPI_DDR_MODE=${QSPI_DDR_MODE} is not supported.") + endif +endif + +# RCAR_QSPI_DDR_DUMMY_CYCLE +ifndef RCAR_QSPI_DDR_DUMMY_CYCLE +RCAR_QSPI_DDR_DUMMY_CYCLE := 9 +endif +$(eval $(call add_define,RCAR_QSPI_DDR_DUMMY_CYCLE)) + +# Process RCAR_SA9_TYPE flag +# 0:Flash, 1:eMMC +ifeq (${LSI},S4) + ifndef RCAR_SA9_TYPE + RCAR_SA9_TYPE := 0 + $(eval $(call add_define,RCAR_SA9_TYPE)) + else + ifeq (${RCAR_SA9_TYPE},0) + $(eval $(call add_define,RCAR_SA9_TYPE)) + else ifeq (${RCAR_SA9_TYPE},1) + $(eval $(call add_define,RCAR_SA9_TYPE)) + else + $(error "Error:RCAR_SA9_TYPE=${RCAR_SA9_TYPE} is not supported.") + endif + endif +else ifeq ($(filter ${LSI},V4H V4M),${LSI}) + RCAR_SA9_TYPE := 0 + $(eval $(call add_define,RCAR_SA9_TYPE)) +endif + + +ifeq (${RCAR_SA9_TYPE},1) +OBJ_FILE += image_load/image_load_emmc.o \ + ip/emmc/emmc_cmd.o \ + ip/emmc/emmc_init.o \ + ip/emmc/emmc_interrupt.o \ + ip/emmc/emmc_mount.o \ + ip/emmc/emmc_multiboot.o \ + ip/emmc/emmc_read.o \ + ip/emmc/emmc_utility.o +else ifeq (${RCAR_SA9_TYPE},0) +OBJ_FILE += image_load/image_load_flash.o \ + ip/dma/dma.o \ + ip/rpc/rpc.o \ + ip/mfis/mfis.o +endif + +# Process CA_LOAD_TYPE flag +# 0:CA Loader 1:BL31 (or Secure Monitor) +ifeq (${LSI},S4) + ifndef CA_LOAD_TYPE + CA_LOAD_TYPE := 0 + $(eval $(call add_define,CA_LOAD_TYPE)) + else + ifeq (${CA_LOAD_TYPE},0) + $(eval $(call add_define,CA_LOAD_TYPE)) + else ifeq (${CA_LOAD_TYPE},1) + $(eval $(call add_define,CA_LOAD_TYPE)) + else + $(error "Error:CA_LOAD_TYPE=${CA_LOAD_TYPE} is not supported.") + endif + endif +else ifeq ($(filter ${LSI},V4H V4M),${LSI}) + CA_LOAD_TYPE := 0 + $(eval $(call add_define,CA_LOAD_TYPE)) +endif + +ifeq (${RCAR_SA9_TYPE},1) + ifeq (${CA_LOAD_TYPE},0) + $(error "Error:RCAR_SA9_TYPE=1 and CA_LOAD_TYPE=0 is not supported.") + endif +endif + +# Process MCU_SECURE_BOOT flag (S4 only) +ifndef MCU_SECURE_BOOT + MCU_SECURE_BOOT := 0 + $(eval $(call add_define,MCU_SECURE_BOOT)) +else + ifeq (${MCU_SECURE_BOOT},0) + $(eval $(call add_define,MCU_SECURE_BOOT)) + else ifeq (${MCU_SECURE_BOOT},1) + ifeq (${BOOT_MCU},0) + $(error "Error:MCU_SECURE_BOOT=${MCU_SECURE_BOOT} and BOOT_MCU=${BOOT_MCU} is not supported.") + else + $(eval $(call add_define,MCU_SECURE_BOOT)) + endif + else + $(error "Error:MCU_SECURE_BOOT=${MCU_SECURE_BOOT} is not supported.") + endif +endif + +# Process SW_VERSION_CHECK flag +# 0:Disable 1:Enable +ifndef SW_VERSION_CHECK +SW_VERSION_CHECK := 0 +$(eval $(call add_define,SW_VERSION_CHECK)) +else + ifeq (${SW_VERSION_CHECK},0) + $(eval $(call add_define,SW_VERSION_CHECK)) + else ifeq (${SW_VERSION_CHECK},1) + $(eval $(call add_define,SW_VERSION_CHECK)) + else + $(error "Error:SW_VERSION_CHECK=${SW_VERSION_CHECK} is not supported.") + endif +endif + +# Process access protection flag +# 0:Disable 1:Enable +ifndef ACC_PROT_ENABLE +ACC_PROT_ENABLE := 0 +$(eval $(call add_define,ACC_PROT_ENABLE)) +else + ifeq (${ACC_PROT_ENABLE},0) + $(eval $(call add_define,ACC_PROT_ENABLE)) + else ifeq (${ACC_PROT_ENABLE},1) + $(eval $(call add_define,ACC_PROT_ENABLE)) + else + $(error "Error:ACC_PROT_ENABLE=${ACC_PROT_ENABLE} is not supported.") + endif +endif + +ifeq (${MCU_SECURE_BOOT},1) +include mcu_secureboot/mcu_secureboot.mk +endif + +# Process ADD_HOTPLUG_MAGIC flag +ifndef ADD_HOTPLUG_MAGIC + ADD_HOTPLUG_MAGIC := 0 + $(eval $(call add_define,ADD_HOTPLUG_MAGIC)) +else + ifeq (${ADD_HOTPLUG_MAGIC},0) + $(eval $(call add_define,ADD_HOTPLUG_MAGIC)) + else ifeq (${ADD_HOTPLUG_MAGIC},1) + $(eval $(call add_define,ADD_HOTPLUG_MAGIC)) + else + $(error "Error:ADD_HOTPLUG_MAGIC=${ADD_HOTPLUG_MAGIC} is not supported.") + endif +endif + +# Process STACK_PROTECT flag +ifndef STACK_PROTECT + STACK_PROTECT := 0 + $(eval $(call add_define,STACK_PROTECT)) +else + ifeq (${STACK_PROTECT},0) + $(eval $(call add_define,STACK_PROTECT)) + else ifeq (${STACK_PROTECT},1) + $(eval $(call add_define,STACK_PROTECT)) + CFLAGS += -stack_protector + else + $(error "Error:STACK_PROTECT=${STACK_PROTECT} is not supported.") + endif +endif + +# Process RTOS_LOAD_NUM flag +# 1:RTOS#0 only 3:RTOS#0,#1,#2 +ifndef RTOS_LOAD_NUM + RTOS_LOAD_NUM := 1 + $(eval $(call add_define,RTOS_LOAD_NUM)) +else + ifeq (${RTOS_LOAD_NUM},1) + $(eval $(call add_define,RTOS_LOAD_NUM)) + else ifeq (${RTOS_LOAD_NUM},3) + $(eval $(call add_define,RTOS_LOAD_NUM)) + else + $(error "Error:RTOS_LOAD_NUM=${RTOS_LOAD_NUM} is not supported.") + endif +endif + +# Process OPTEE_LOAD_ENABLE flag +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef OPTEE_LOAD_ENABLE + OPTEE_LOAD_ENABLE := 1 + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else + ifeq (${OPTEE_LOAD_ENABLE},0) + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else ifeq (${OPTEE_LOAD_ENABLE},1) + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else + $(error "Error:OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.") + endif + endif +endif + +################################################### +# pass SecureMonitor parametor +################################################### +# Process SET_CA_PARAM flag +ifeq (${LSI},S4) + ifndef SET_CA_PARAM + SET_CA_PARAM := 1 + $(eval $(call add_define,SET_CA_PARAM)) + else + ifeq (${SET_CA_PARAM},0) + $(eval $(call add_define,SET_CA_PARAM)) + else ifeq (${SET_CA_PARAM},1) + $(eval $(call add_define,SET_CA_PARAM)) + else + $(error "Error:SET_CA_PARAM=${SET_CA_PARAM} is not supported.") + endif + endif +endif + +# Process ECM_ENABLE +ifndef ECM_ENABLE + ECM_ENABLE:= 0 + $(eval $(call add_define,ECM_ENABLE)) +else + ifeq (${ECM_ENABLE},0) + $(eval $(call add_define,ECM_ENABLE)) + else ifeq (${ECM_ENABLE},1) + $(eval $(call add_define,ECM_ENABLE)) + else + $(error "Error: ECM_ENABLE=${ECM_ENABLE} is not supported.") + endif +endif + +# Process ECM_ERROR_ENABLE flag +ifndef ECM_ERROR_ENABLE + ECM_ERROR_ENABLE := 1 + $(eval $(call add_define,ECM_ERROR_ENABLE)) +else + ifeq (${ECM_ERROR_ENABLE},0) + $(eval $(call add_define,ECM_ERROR_ENABLE)) + else ifeq (${ECM_ERROR_ENABLE},1) + $(eval $(call add_define,ECM_ERROR_ENABLE)) + else + $(error "Error:ECM_ERROR_ENABLE=${ECM_ERROR_ENABLE} is not supported.") + endif +endif + + +# Process DBSC HUNGUP WA +ifndef WA_OTLINT5579 + WA_OTLINT5579:= 1 +endif +$(eval $(call add_define,WA_OTLINT5579)) + +################################################### + +OUTDIR_REL := $(OUTDIR)/release +OUTDIR_OBJ := $(OUTDIR)/obj + +OBJ_FILE := $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o) +OBJ_FILE_SA0 := $(OBJ_FILE_SA0:%.o=$(OUTDIR_OBJ)/%.o) +OBJ_FILE_SA9 := $(OBJ_FILE_SA9:%.o=$(OUTDIR_OBJ)/%.o) +OBJ_FILE_TFMV_TBL := $(OBJ_FILE_TFMV_TBL:%.o=$(OUTDIR_OBJ)/%.o) +OBJ_FILE_NTFMV_TBL := $(OBJ_FILE_NTFMV_TBL:%.o=$(OUTDIR_OBJ)/%.o) + +CC = cxrh850 +AS = cxrh850 +LD = cxrh850 +OC = gsrec +OD = gdump + +ASFLAGS += -asm="-preprocess_assembly_files" \ + -asm="-nostartfiles" \ + -D__ASSEMBLY \ + $(INCLUDE_DIR) $(DEFINES) + +CFLAGS += -nostartfiles \ + -c99 \ + $(INCLUDE_DIR) $(DEFINES) \ + --ghstd=last \ + -Wundef \ + --diag_error=193 \ + --prototype_errors +# --ghstd=last : Enable Green Hills Standard Mode +# -Wundef : Output warning if there are any undefined symbols +# --diag_error=193 : Error if zero is applied to undefined symbol +# --prototype_errors : Error if there are no any prototype declaration + +ifeq (${LOG_LEVEL},0) +# There are no any additional options +else +CFLAGS += --diag_suppress=1932 # There is warning that format string parameter in sprintf is not constant +endif + +LDFLAGS += -nostartfiles -Mu + +BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__ + +################################################### +.SUFFIXES : .s .c .o + +################################################### +# command + +.PHONY: all +all: $(OUTPUT_FILE) $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA9) $(OUTPUT_FILE_TFMV_TBL) $(OUTPUT_FILE_NTFMV_TBL) + +################################################### +# Linker +################################################### +$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE) + @echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' > $(OUTDIR_OBJ)/build_message.c + @$(CC) $(CFLAGS) -o $(OUTDIR_OBJ)/build_message.o -c $(OUTDIR_OBJ)/build_message.c + + @$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \ + -T $(MEMORY_DEF) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE) \ + $(LDFLAGS) \ + -map=$(OUTDIR_REL)/$(FILE_NAME).map + + @$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).srec + @$(OD) -full -ysec $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE) -o $(OUTDIR_REL)/$(OUTPUT_FILE:%.elf=%.bin) + +$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0) + @$(LD) $(OBJ_FILE_SA0) \ + -T $(MEMORY_DEF_SA0) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) \ + -map=$(OUTDIR_REL)/$(FILE_NAME_SA0).map \ + -nostdlib + + @$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) > $(OUTDIR_REL)/$(FILE_NAME_SA0).srec + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0:%.elf=%.bin) + +$(OUTPUT_FILE_SA9) : $(MEMORY_DEF_SA9) $(OBJ_FILE_SA9) + @$(LD) $(OBJ_FILE_SA9) \ + -T $(MEMORY_DEF_SA9) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) \ + -map=$(OUTDIR_REL)/$(FILE_NAME_SA9).map \ + -nostdlib + + @$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) > $(OUTDIR_REL)/$(FILE_NAME_SA9).srec + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA9:%.elf=%.bin) + +$(OUTPUT_FILE_TFMV_TBL) : $(MEMORY_DEF_TFMV_TBL) $(OBJ_FILE_TFMV_TBL) + @$(LD) $(OBJ_FILE_TFMV_TBL) \ + -T $(MEMORY_DEF_TFMV_TBL) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL) \ + -map=$(OUTDIR_REL)/$(FILE_NAME_TFMV_TBL).map \ + -nostdlib + + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL) -o $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL:%.elf=%.bin) + +$(OUTPUT_FILE_NTFMV_TBL) : $(MEMORY_DEF_NTFMV_TBL) $(OBJ_FILE_NTFMV_TBL) + @$(LD) $(OBJ_FILE_NTFMV_TBL) \ + -T $(MEMORY_DEF_NTFMV_TBL) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL) \ + -map=$(OUTDIR_REL)/$(FILE_NAME_NTFMV_TBL).map \ + -nostdlib + + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL) -o $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL:%.elf=%.bin) + +################################################### +# Compile +################################################### + +$(OUTDIR_OBJ)/%.o:%.c + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + @$(CC) $(CFLAGS) -o $@ -c $< + +$(OUTDIR_OBJ)/%.o:%.S + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + @$(AS) $(ASFLAGS) -o $@ -c $< + + +.PHONY: clean +clean: + @rm -rf $(OUTDIR) diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_s4.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_s4.c new file mode 100644 index 0000000..2d38556 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_s4.c @@ -0,0 +1,2468 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table + ******************************************************************************/ +/****************************************************************************** + * @file cnf_tbl.c + * - Version : 0.02 + * @brief Configuration table for S4. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 23.05.2022 0.02 Integration of S4 and V4H + * Renamed from conf_tbl.c to cnf_tbl_s4.c. + * : 23.01.2023 0.03 Update the set value of Region ID. + * Add the RAM access protection + * setting value tables. + *****************************************************************************/ + +#include +#include +#include +#include +#include + +#define RTDMA_EN (0x00000002U) +#define SYSDMA_EN (0x0000BFC4U) + +#pragma ghs section rodata=".qosbw_tbl" +const QOS_SETTING_TABLE g_qosbw_tbl[] = { + [0] = {0x000C04020000FFFFULL, 0x00100000031FFC01ULL}, + [1] = {0x000C04080000FFFFULL, 0x00100000031FFC01ULL}, + [2] = {0x000C08100000FFFFULL, 0x00100000031FFC01ULL}, + [3] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [4] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [5] = {0x000C04020000FFFFULL, 0x00100000031FFC01ULL}, + [6] = {0x000C04080000FFFFULL, 0x00100000031FFC01ULL}, + [7] = {0x000C08100000FFFFULL, 0x00200000031FFC01ULL}, + [8] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [9] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [10] = {0x000C04020000FFFFULL, 0x00100000031FFC01ULL}, + [11] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [12] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [13] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [14] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [15] = {0x000C04020000FFFFULL, 0x00100000031FFC01ULL}, + [16] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [17] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [18] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [19] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [20] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [21] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [22] = {0x000C04280000FFFFULL, 0x00100000031FFC01ULL}, + [23] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [24] = {0x000C08280000FFFFULL, 0x00100000031FFC01ULL}, + [25] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [26] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [27] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [28] = {0x000C14280000FFFFULL, 0x00100000031FFC01ULL}, + [29] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [30] = {0x001008280000FFFFULL, 0x00100000031FFC01ULL}, + [31] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [32] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [33] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [34] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [35] = {0x000C04020000FFFFULL, 0x00100000031FFC01ULL}, + [36] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [37] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [38] = {0x001404100000FFFFULL, 0x00100000031FFC01ULL}, + [39] = {0x001404100000FFFFULL, 0x00100000031FFC01ULL}, + [40] = {0x000C1C6F0000FFFFULL, 0x00100000031FFC01ULL}, + [41] = {0x000C103F0000FFFFULL, 0x00100000031FFC01ULL}, + [42] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [43] = {0x000C144F0000FFFFULL, 0x00100000031FFC01ULL}, + [44] = {0x001408200000FFFFULL, 0x00100000031FFC01ULL}, + [45] = {0x0014185F0000FFFFULL, 0x00100000031FFC01ULL}, + [46] = {0x000C0C300000FFFFULL, 0x00100000031FFC01ULL}, + [47] = {0x000C1C6F0000FFFFULL, 0x00100000031FFC01ULL} +}; + + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".qoswt_tbl" +const QOS_SETTING_TABLE g_qoswt_tbl[] = { + [0] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [1] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [2] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [3] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [4] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [5] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [6] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [7] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [8] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [9] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [10] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [11] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [12] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [13] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [14] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [15] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [16] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [17] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [18] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [19] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [20] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [21] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [22] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [23] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [24] = {0x000C08280000FFF0ULL, 0x0000000000000000ULL}, + [25] = {0x000C00000000FFF0ULL, 0x0000000000000000ULL}, + [26] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [27] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [28] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [29] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [30] = {0x001008280000C010ULL, 0x0000000000000000ULL}, + [31] = {0x000C00000000C010ULL, 0x0000000000000000ULL}, + [32] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [33] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [34] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [35] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [36] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [37] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [38] = {0x001404100000FFF0ULL, 0x0000000000000000ULL}, + [39] = {0x001404100000C010ULL, 0x0000000000000000ULL}, + [40] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [41] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [42] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [43] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [44] = {0x0014000000000000ULL, 0x0000000000000000ULL}, + [45] = {0x0014000000000000ULL, 0x0000000000000000ULL}, + [46] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [47] = {0x000C000000000000ULL, 0x0000000000000000ULL} +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + + +#pragma ghs section rodata=".rgid_m_tbl" +const REGION_ID_SETTING_TABLE g_rgid_m_tbl[] = { + [0] = {0xFCF81000U, 0x00000002U}, /* RGIDM_MODID[0]:PCI0 */ + [1] = {0xFCF81020U, 0x00000002U}, /* RGIDM_MODID[1]:PCI1 */ + [2] = {0xFCF81024U, 0x00000002U}, /* RGIDM_MODID[2]:PCI2 */ + [3] = {0xFCF81034U, 0x00000002U}, /* RGIDM_MODID[3]:PCI3 */ + [4] = {0xFCF81038U, 0x00000002U}, /* RGIDM_MODID[4]:RSW2 */ + [5] = {0xFCF8103CU, 0x00000001U}, /* RGIDM_MODID[5]:RSW2SEC */ + [6] = {0xFCF81044U, 0x00000002U}, /* RGIDM_MODID[6]:UFS */ + [7] = {0xFDC21004U, 0x00000000U}, /* RGIDM_MODID[7]:CR0 */ + [8] = {0xFDC2100CU, 0x00000000U}, /* RGIDM_MODID[8]:ICUMX */ + [9] = {0xFDC21010U, 0x00000000U}, /* RGIDM_MODID[9]:ICUMX */ + [10] = {0xFDC21014U, 0x00000000U}, /* RGIDM_MODID[10]:ICUMX */ + [11] = {0xFD441018U, 0x00000001U}, /* RGIDM_MODID[11]:CR52SS */ + [12] = {0xFD44101CU, 0x00000003U}, /* RGIDM_MODID[12]:CSD */ + [13] = {0xFD441024U, 0x00000002U}, /* RGIDM_MODID[13]:INTAP0 */ + [14] = {0xFD441068U, 0x00000005U}, /* RGIDM_MODID[14]:ControlDomain0 */ + [15] = {0xFD44106CU, 0x00000005U}, /* RGIDM_MODID[15]:ControlDomain1 */ + [16] = {0xFD4410A0U, 0x00000005U}, /* RGIDM_MODID[16]:ControlDomain2 */ + [17] = {0xFD4410ACU, 0x00000005U}, /* RGIDM_MODID[17]:ControlDomain3 */ + [18] = {0xFD4410B0U, 0x00000005U}, /* RGIDM_MODID[18]:ControlDomain4 */ + [19] = {0xFD4410B4U, 0x00000005U}, /* RGIDM_MODID[19]:ControlDomain5 */ + [20] = {0xFD4410B8U, 0x00000005U}, /* RGIDM_MODID[20]:ControlDomain6 */ + [21] = {0xFD4410BCU, 0x00000005U}, /* RGIDM_MODID[21]:ControlDomain7 */ + [22] = {0xFD4410C0U, 0x00000005U}, /* RGIDM_MODID[22]:ControlDomain8 */ + [23] = {0xFD4410C4U, 0x00000005U}, /* RGIDM_MODID[23]:ControlDomain9 */ + [24] = {0xFD441078U, 0x00000005U}, /* RGIDM_MODID[24]:ControlDomain10 */ + [25] = {0xFD44107CU, 0x00000005U}, /* RGIDM_MODID[25]:ControlDomain11 */ + [26] = {0xFD441080U, 0x00000005U}, /* RGIDM_MODID[26]:ControlDomain12 */ + [27] = {0xFD441084U, 0x00000004U}, /* RGIDM_MODID[27]:ControlDomain13 */ + [28] = {0xFD441088U, 0x00000004U}, /* RGIDM_MODID[28]:ControlDomain14 */ + [29] = {0xFD44108CU, 0x00000005U}, /* RGIDM_MODID[29]:ControlDomain15 */ + [30] = {0xFD441090U, 0x00000005U}, /* RGIDM_MODID[30]:ControlDomain16 */ + [31] = {0xFD441094U, 0x00000005U}, /* RGIDM_MODID[31]:ControlDomain17 */ + [32] = {0xFD441098U, 0x00000005U}, /* RGIDM_MODID[32]:ControlDomain18 */ + [33] = {0xFD44109CU, 0x00000005U}, /* RGIDM_MODID[33]:ControlDomain19 */ + [34] = {0xFD4410A4U, 0x00000005U}, /* RGIDM_MODID[34]:ControlDomain20 */ + [35] = {0xFD4410A8U, 0x00000003U}, /* RGIDM_MODID[35]:ControlDomain21 */ + [36] = {0xFF861018U, 0x00000002U}, /* RGIDM_MODID[36]:FBABUSTOP0 */ + [37] = {0xFF86101CU, 0x00000002U}, /* RGIDM_MODID[37]:FBABUSTOP1 */ + [38] = {0xFCB51020U, 0x00000002U}, /* RGIDM_MODID[38]:SDHI0 */ + [39] = {0xFF811000U, 0x00000002U}, /* RGIDM_MODID[39]:AXMM2AXSTM */ + [40] = {0xFF811004U, 0x00000003U}, /* RGIDM_MODID[40]:CSDE0 */ + [41] = {0xFF811008U, 0x00000003U}, /* RGIDM_MODID[41]:CSDE1 */ + [42] = {0xFDDBF500U, 0x0000000EU}, /* RGIDM_MODID[42]:VRAM_R */ + [43] = {0xFDDBF504U, 0x0000000EU}, /* RGIDM_MODID[43]:VRAM_W */ + +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_r_tbl" +const REGION_ID_SETTING_TABLE g_rgid_r_tbl[] = { + [0] = {0xFD482000U, 0x0000002EU}, /* RGIDR_MODID[0]:ARMGC0 */ + [1] = {0xFD482004U, 0x0000002EU}, /* RGIDR_MODID[1]:ARMGC1 */ + [2] = {0xFD482008U, 0x00000000U}, /* RGIDR_MODID[2]:ARMGC2 */ + [3] = {0xFD48200CU, 0x0000003FU}, /* RGIDR_MODID[3]:ARRT00 */ + /* After setting */ /* RGIDR_MODID[4]:ARRT01 */ + /* After setting */ /* RGIDR_MODID[5]:ARRT02 */ + [4] = {0xFD482018U, 0x0000003FU}, /* RGIDR_MODID[6]:ARRT03 */ + [5] = {0xFD48201CU, 0x0000003FU}, /* RGIDR_MODID[7]:ARRT04 */ + [6] = {0xFD482020U, 0x0000003FU}, /* RGIDR_MODID[8]:ARRT05 */ + [7] = {0xFD482024U, 0x0000003FU}, /* RGIDR_MODID[9]:ARRT06 */ + [8] = {0xFD482028U, 0x0000003FU}, /* RGIDR_MODID[10]:ARRT07 */ + [9] = {0xFD48202CU, 0x00000000U}, /* RGIDR_MODID[11]:ARRT08 */ + [10] = {0xFD482030U, 0x00000011U}, /* RGIDR_MODID[12]:LIFEC0 */ + [11] = {0xFD482034U, 0x00000026U}, /* RGIDR_MODID[13]:SWDT */ + [12] = {0xFD482038U, 0x0000003FU}, /* RGIDR_MODID[14]:TMU0 */ + [13] = {0xFD48203CU, 0x00000026U}, /* RGIDR_MODID[15]:WDT */ + [14] = {0xFD482040U, 0x00000026U}, /* RGIDR_MODID[16]:WWDT0 */ + [15] = {0xFD482044U, 0x00000026U}, /* RGIDR_MODID[17]:WWDT1 */ + [16] = {0xFD482048U, 0x00000026U}, /* RGIDR_MODID[18]:WWDT2 */ + [17] = {0xFD48204CU, 0x00000026U}, /* RGIDR_MODID[19]:WWDT3 */ + [18] = {0xFD482050U, 0x00000026U}, /* RGIDR_MODID[20]:WWDT4 */ + [19] = {0xFD482054U, 0x00000026U}, /* RGIDR_MODID[21]:WWDT5 */ + [20] = {0xFD482058U, 0x00000026U}, /* RGIDR_MODID[22]:WWDT6 */ + [21] = {0xFD48205CU, 0x00000026U}, /* RGIDR_MODID[23]:WWDT7 */ + [22] = {0xFD482060U, 0x00000026U}, /* RGIDR_MODID[24]:WWDT8 */ + [23] = {0xFD482064U, 0x00000026U}, /* RGIDR_MODID[25]:WWDT9 */ + [24] = {0xFD482068U, 0x0000003FU}, /* RGIDR_MODID[26]:ECMRT3 */ + [25] = {0xFDA02000U, 0x0000002EU}, /* RGIDR_MODID[27]:ADVFSC */ + [26] = {0xFDA02004U, 0x0000003FU}, /* RGIDR_MODID[28]:APMU0 */ + [27] = {0xFDA02008U, 0x00000002U}, /* RGIDR_MODID[29]:APMU1 */ + [28] = {0xFDA0200CU, 0x00000000U}, /* RGIDR_MODID[30]:APMU10 */ + [29] = {0xFDA02010U, 0x00000000U}, /* RGIDR_MODID[31]:APMU11 */ + [30] = {0xFDA02014U, 0x00000000U}, /* RGIDR_MODID[32]:APMU12 */ + [31] = {0xFDA02018U, 0x00000000U}, /* RGIDR_MODID[33]:APMU13 */ + [32] = {0xFDA0201CU, 0x00000000U}, /* RGIDR_MODID[34]:APMU14 */ + [33] = {0xFDA02020U, 0x00000000U}, /* RGIDR_MODID[35]:APMU15 */ + [34] = {0xFDA02024U, 0x00000004U}, /* RGIDR_MODID[36]:APMU2 */ + [35] = {0xFDA02028U, 0x00000004U}, /* RGIDR_MODID[37]:APMU3 */ + [36] = {0xFDA0202CU, 0x00000000U}, /* RGIDR_MODID[38]:APMU4 */ + [37] = {0xFDA02030U, 0x00000000U}, /* RGIDR_MODID[39]:APMU5 */ + [38] = {0xFDA02034U, 0x00000000U}, /* RGIDR_MODID[40]:APMU6 */ + [39] = {0xFDA02038U, 0x00000000U}, /* RGIDR_MODID[41]:APMU7 */ + [40] = {0xFDA0203CU, 0x00000000U}, /* RGIDR_MODID[42]:APMU8 */ + [41] = {0xFDA02040U, 0x00000000U}, /* RGIDR_MODID[43]:APMU9 */ + [42] = {0xFDA02044U, 0x0000003FU}, /* RGIDR_MODID[44]:ARS00 */ + /* After setting */ /* RGIDR_MODID[45]:ARS01 */ + /* After setting */ /* RGIDR_MODID[46]:ARS02 */ + [43] = {0xFDA02050U, 0x0000003FU}, /* RGIDR_MODID[47]:ARS03 */ + [44] = {0xFDA02054U, 0x0000003FU}, /* RGIDR_MODID[48]:ARS04 */ + [45] = {0xFDA02058U, 0x0000003FU}, /* RGIDR_MODID[49]:ARS05 */ + [46] = {0xFDA0205CU, 0x0000003FU}, /* RGIDR_MODID[50]:ARS06 */ + [47] = {0xFDA02060U, 0x0000003FU}, /* RGIDR_MODID[51]:ARS07 */ + [48] = {0xFDA02064U, 0x00000000U}, /* RGIDR_MODID[52]:ARS08 */ + [49] = {0xFDA02068U, 0x0000002EU}, /* RGIDR_MODID[53]:CMT0 */ + [50] = {0xFDA0206CU, 0x0000002EU}, /* RGIDR_MODID[54]:CMT1 */ + [51] = {0xFDA02070U, 0x0000002EU}, /* RGIDR_MODID[55]:CMT2 */ + [52] = {0xFDA02074U, 0x0000002EU}, /* RGIDR_MODID[56]:CMT3 */ + [53] = {0xFDA02078U, 0x0000002AU}, /* RGIDR_MODID[57]:CKM */ + [54] = {0xFDA0207CU, 0x0000002EU}, /* RGIDR_MODID[58]:DBE */ + [55] = {0xFDA02080U, 0x0000002EU}, /* RGIDR_MODID[59]:IRQC */ + [56] = {0xFDA02084U, 0x0000003BU}, /* RGIDR_MODID[60]:ECMPS0 */ + [57] = {0xFDA0209CU, 0x0000002EU}, /* RGIDR_MODID[61]:SCMT */ + [58] = {0xFDA020A8U, 0x0000002EU}, /* RGIDR_MODID[62]:TSC1 */ + [59] = {0xFDA020ACU, 0x0000002EU}, /* RGIDR_MODID[63]:TSC2 */ + [60] = {0xFDA020B0U, 0x0000002EU}, /* RGIDR_MODID[64]:TSC3 */ + [61] = {0xFDA020B4U, 0x0000002EU}, /* RGIDR_MODID[65]:TSC4 */ + [62] = {0xFDA020B8U, 0x00000026U}, /* RGIDR_MODID[66]:UCMT */ + [63] = {0xFDA02100U, 0x0000003FU}, /* RGIDR_MODID[67]:CPG0 */ + [64] = {0xFDA02104U, 0x0000002AU}, /* RGIDR_MODID[68]:CPG1 */ + [65] = {0xFDA02108U, 0x0000000CU}, /* RGIDR_MODID[69]:CPG2 */ + [66] = {0xFDA0210CU, 0x0000000CU}, /* RGIDR_MODID[70]:CPG3 */ + [67] = {0xFDA02110U, 0x0000003FU}, /* RGIDR_MODID[71]:PFC00 */ + [68] = {0xFDA02114U, 0x0000002AU}, /* RGIDR_MODID[72]:PFC01 */ + [69] = {0xFDA02118U, 0x0000000CU}, /* RGIDR_MODID[73]:PFC02 */ + [70] = {0xFDA0211CU, 0x0000000CU}, /* RGIDR_MODID[74]:PFC03 */ + [71] = {0xFDA02150U, 0x0000003FU}, /* RGIDR_MODID[75]:PFCS0 */ + [72] = {0xFDA02154U, 0x0000002AU}, /* RGIDR_MODID[76]:PFCS1 */ + [73] = {0xFDA02158U, 0x0000000CU}, /* RGIDR_MODID[77]:PFCS2 */ + [74] = {0xFDA0215CU, 0x0000000CU}, /* RGIDR_MODID[78]:PFCS3 */ + [75] = {0xFDA02160U, 0x0000003FU}, /* RGIDR_MODID[79]:RESET0 */ + [76] = {0xFDA02164U, 0x0000002AU}, /* RGIDR_MODID[80]:RESET1 */ + [77] = {0xFDA02168U, 0x0000000CU}, /* RGIDR_MODID[81]:RESET2 */ + [78] = {0xFDA0216CU, 0x0000000CU}, /* RGIDR_MODID[82]:RESET3 */ + [79] = {0xFDA02170U, 0x0000003FU}, /* RGIDR_MODID[83]:SYS0 */ + [80] = {0xFDA02174U, 0x0000002AU}, /* RGIDR_MODID[84]:SYS1 */ + [81] = {0xFDA02178U, 0x0000000CU}, /* RGIDR_MODID[85]:SYS2 */ + [82] = {0xFDA0217CU, 0x0000000CU}, /* RGIDR_MODID[86]:SYS3 */ + [83] = {0xFCB62000U, 0x0000002EU}, /* RGIDR_MODID[87]:DMAMSI0 */ + [84] = {0xFCB62004U, 0x0000002EU}, /* RGIDR_MODID[88]:DMAMSI1 */ + [85] = {0xFCB62008U, 0x0000002EU}, /* RGIDR_MODID[89]:DMAMSI2 */ + [86] = {0xFCB6200CU, 0x0000002EU}, /* RGIDR_MODID[90]:DMAMSI3 */ + [87] = {0xFCB62018U, 0x0000003BU}, /* RGIDR_MODID[91]:ECMSP3 */ + [88] = {0xFCB62024U, 0x0000003FU}, /* RGIDR_MODID[92]:ARSP30 */ + /* After setting */ /* RGIDR_MODID[93]:ARSP31 */ + /* After setting */ /* RGIDR_MODID[94]:ARSP32 */ + [89] = {0xFCB62030U, 0x0000003FU}, /* RGIDR_MODID[95]:ARSP33 */ + [90] = {0xFCB62034U, 0x0000003FU}, /* RGIDR_MODID[96]:ARSP34 */ + [91] = {0xFCB62038U, 0x0000003FU}, /* RGIDR_MODID[97]:ARSP35 */ + [92] = {0xFCB6203CU, 0x0000003FU}, /* RGIDR_MODID[98]:ARSP36 */ + [93] = {0xFCB62040U, 0x0000003FU}, /* RGIDR_MODID[99]:ARSP37 */ + [94] = {0xFCB62044U, 0x00000000U}, /* RGIDR_MODID[100]:ARSP38 */ + [95] = {0xFCB62048U, 0x0000002EU}, /* RGIDR_MODID[101]:MSI0 */ + [96] = {0xFCB6204CU, 0x0000002EU}, /* RGIDR_MODID[102]:MSI1 */ + [97] = {0xFCB62050U, 0x0000002EU}, /* RGIDR_MODID[103]:MSI2 */ + [98] = {0xFCB62054U, 0x0000002EU}, /* RGIDR_MODID[104]:MSI3 */ + [99] = {0xFCB92000U, 0x0000003FU}, /* RGIDR_MODID[105]:ARSP40 */ + /* After setting */ /* RGIDR_MODID[106]:ARSP41 */ + /* After setting */ /* RGIDR_MODID[107]:ARSP42 */ + [100] = {0xFCB9200CU, 0x0000003FU}, /* RGIDR_MODID[108]:ARSP43 */ + [101] = {0xFCB92010U, 0x0000003FU}, /* RGIDR_MODID[109]:ARSP44 */ + [102] = {0xFCB92014U, 0x0000003FU}, /* RGIDR_MODID[110]:ARSP45 */ + [103] = {0xFCB92018U, 0x0000003FU}, /* RGIDR_MODID[111]:ARSP46 */ + [104] = {0xFCB9201CU, 0x0000003FU}, /* RGIDR_MODID[112]:ARSP47 */ + [105] = {0xFCB92020U, 0x00000000U}, /* RGIDR_MODID[113]:ARSP48 */ + [106] = {0xFCB92024U, 0x0000003FU}, /* RGIDR_MODID[114]:DMAHSCIF0 */ + [107] = {0xFCB92028U, 0x0000003FU}, /* RGIDR_MODID[115]:DMAHSCIF1 */ + [108] = {0xFCB9202CU, 0x0000003FU}, /* RGIDR_MODID[116]:DMAHSCIF2 */ + [109] = {0xFCB92030U, 0x0000003FU}, /* RGIDR_MODID[117]:DMAHSCIF3 */ + [110] = {0xFCB92034U, 0x0000003FU}, /* RGIDR_MODID[118]:DMASCIF0 */ + [111] = {0xFCB92038U, 0x0000003FU}, /* RGIDR_MODID[119]:DMASCIF1 */ + [112] = {0xFCB9203CU, 0x0000003FU}, /* RGIDR_MODID[120]:DMASCIF3 */ + [113] = {0xFCB92040U, 0x0000003FU}, /* RGIDR_MODID[121]:DMASCIF4 */ + [114] = {0xFCB92044U, 0x0000003BU}, /* RGIDR_MODID[122]:ECMSP4 */ + [115] = {0xFCB92048U, 0x0000003FU}, /* RGIDR_MODID[123]:HSCIF0 */ + [116] = {0xFCB9204CU, 0x0000003FU}, /* RGIDR_MODID[124]:HSCIF1 */ + [117] = {0xFCB92050U, 0x0000003FU}, /* RGIDR_MODID[125]:HSCIF2 */ + [118] = {0xFCB92054U, 0x0000003FU}, /* RGIDR_MODID[126]:HSCIF3 */ + [119] = {0xFCB92058U, 0x0000003FU}, /* RGIDR_MODID[127]:SCIF0 */ + [120] = {0xFCB9205CU, 0x0000003FU}, /* RGIDR_MODID[128]:SCIF1 */ + [121] = {0xFCB92060U, 0x0000003FU}, /* RGIDR_MODID[129]:SCIF3 */ + [122] = {0xFCB92064U, 0x0000003FU}, /* RGIDR_MODID[130]:SCIF4 */ + [123] = {0xFCB92068U, 0x0000003FU}, /* RGIDR_MODID[131]:TMU1 */ + [124] = {0xFCB9206CU, 0x0000003FU}, /* RGIDR_MODID[132]:TMU2 */ + [125] = {0xFCB92070U, 0x0000003FU}, /* RGIDR_MODID[133]:TMU3 */ + [126] = {0xFCB92074U, 0x0000003FU}, /* RGIDR_MODID[134]:TMU4 */ + [127] = {0xFCF82000U, 0x0000002AU}, /* RGIDR_MODID[135]:CKMHSC */ + [128] = {0xFCF82004U, 0x0000000CU}, /* RGIDR_MODID[136]:AXIPCI001 */ + [129] = {0xFCF82008U, 0x0000000CU}, /* RGIDR_MODID[137]:AXIPCI002 */ + [130] = {0xFCF8200CU, 0x0000000CU}, /* RGIDR_MODID[138]:AXIPCI003 */ + [131] = {0xFCF82010U, 0x0000002EU}, /* RGIDR_MODID[139]:ETHPHY */ + [132] = {0xFCF82014U, 0x0000000CU}, /* RGIDR_MODID[140]:AXIPCI005 */ + [133] = {0xFCF82018U, 0x0000000CU}, /* RGIDR_MODID[141]:AXIPCI006 */ + [134] = {0xFCF8201CU, 0x0000000CU}, /* RGIDR_MODID[142]:AXIPCI007 */ + [135] = {0xFCF82020U, 0x0000000CU}, /* RGIDR_MODID[143]:AXIPCI008 */ + [136] = {0xFCF82024U, 0x0000000CU}, /* RGIDR_MODID[144]:AXIPCI009 */ + [137] = {0xFCF82028U, 0x0000000CU}, /* RGIDR_MODID[145]:AXIPCI010 */ + [138] = {0xFCF8202CU, 0x0000000CU}, /* RGIDR_MODID[146]:AXIPCI011 */ + [139] = {0xFCF82030U, 0x0000000CU}, /* RGIDR_MODID[147]:AXIPCI012 */ + [140] = {0xFCF82034U, 0x0000000CU}, /* RGIDR_MODID[148]:AXIPCI013 */ + [141] = {0xFCF82038U, 0x0000000CU}, /* RGIDR_MODID[149]:AXIPCI014 */ + [142] = {0xFCF8203CU, 0x0000000CU}, /* RGIDR_MODID[150]:AXIPCI015 */ + [143] = {0xFCF82040U, 0x0000000CU}, /* RGIDR_MODID[151]:AXIPCI100 */ + [144] = {0xFCF82044U, 0x0000000CU}, /* RGIDR_MODID[152]:AXIPCI101 */ + [145] = {0xFCF82048U, 0x0000000CU}, /* RGIDR_MODID[153]:AXIPCI102 */ + [146] = {0xFCF8204CU, 0x0000000CU}, /* RGIDR_MODID[154]:AXIPCI103 */ + [147] = {0xFCF82050U, 0x0000000CU}, /* RGIDR_MODID[155]:AXIPCI104 */ + [148] = {0xFCF82054U, 0x0000000CU}, /* RGIDR_MODID[156]:AXIPCI105 */ + [149] = {0xFCF82058U, 0x0000000CU}, /* RGIDR_MODID[157]:AXIPCI106 */ + [150] = {0xFCF8205CU, 0x0000000CU}, /* RGIDR_MODID[158]:AXIPCI107 */ + [151] = {0xFCF82060U, 0x0000000CU}, /* RGIDR_MODID[159]:AXIPCI108 */ + [152] = {0xFCF82064U, 0x0000000CU}, /* RGIDR_MODID[160]:AXIPCI109 */ + [153] = {0xFCF82068U, 0x0000000CU}, /* RGIDR_MODID[161]:AXIPCI110 */ + [154] = {0xFCF8206CU, 0x0000000CU}, /* RGIDR_MODID[162]:AXIPCI111 */ + [155] = {0xFCF82070U, 0x0000000CU}, /* RGIDR_MODID[163]:AXIPCI112 */ + [156] = {0xFCF82074U, 0x0000000CU}, /* RGIDR_MODID[164]:AXIPCI113 */ + [157] = {0xFCF82078U, 0x0000000CU}, /* RGIDR_MODID[165]:AXIPCI114 */ + [158] = {0xFCF8207CU, 0x0000000CU}, /* RGIDR_MODID[166]:AXIPCI115 */ + [159] = {0xFCF82080U, 0x0000002EU}, /* RGIDR_MODID[167]:ETHPHYRAM */ + [160] = {0xFCF82088U, 0x0000000CU}, /* RGIDR_MODID[168]:IPMMUHC00 */ + [161] = {0xFCF8208CU, 0x0000002EU}, /* RGIDR_MODID[169]:RSW200 */ + [162] = {0xFCF82090U, 0x0000002EU}, /* RGIDR_MODID[170]:RSW201 */ + [163] = {0xFCF82094U, 0x0000002EU}, /* RGIDR_MODID[171]:RSW210 */ + [164] = {0xFCF82098U, 0x0000002EU}, /* RGIDR_MODID[172]:RSW211 */ + [165] = {0xFCF8209CU, 0x0000002EU}, /* RGIDR_MODID[173]:RSW202 */ + [166] = {0xFCF820A0U, 0x0000002EU}, /* RGIDR_MODID[174]:RSW203 */ + [167] = {0xFCF820A4U, 0x0000002EU}, /* RGIDR_MODID[175]:RSW204 */ + [168] = {0xFCF820A8U, 0x0000002EU}, /* RGIDR_MODID[176]:RSW205 */ + [169] = {0xFCF820ACU, 0x0000002EU}, /* RGIDR_MODID[177]:RSW206 */ + [170] = {0xFCF820B0U, 0x0000002EU}, /* RGIDR_MODID[178]:RSW207 */ + [171] = {0xFCF820B4U, 0x0000002EU}, /* RGIDR_MODID[179]:RSW208 */ + [172] = {0xFCF820B8U, 0x0000002EU}, /* RGIDR_MODID[180]:RSW209 */ + [173] = {0xFCF820BCU, 0x0000002EU}, /* RGIDR_MODID[181]:RSW2RAM */ + [174] = {0xFCF820C0U, 0x0000002AU}, /* RGIDR_MODID[182]:RSW2SEC00 */ + [175] = {0xFCF820C4U, 0x0000002AU}, /* RGIDR_MODID[183]:RSW2SEC01 */ + [176] = {0xFCF820C8U, 0x0000002AU}, /* RGIDR_MODID[184]:RSW2SEC10 */ + [177] = {0xFCF820CCU, 0x0000002AU}, /* RGIDR_MODID[185]:RSW2SEC11 */ + [178] = {0xFCF820D0U, 0x0000002AU}, /* RGIDR_MODID[186]:RSW2SEC02 */ + [179] = {0xFCF820D4U, 0x0000002AU}, /* RGIDR_MODID[187]:RSW2SEC03 */ + [180] = {0xFCF820D8U, 0x0000002AU}, /* RGIDR_MODID[188]:RSW2SEC04 */ + [181] = {0xFCF820DCU, 0x0000002AU}, /* RGIDR_MODID[189]:RSW2SEC05 */ + [182] = {0xFCF820E0U, 0x0000002AU}, /* RGIDR_MODID[190]:RSW2SEC06 */ + [183] = {0xFCF820E4U, 0x0000002AU}, /* RGIDR_MODID[191]:RSW2SEC07 */ + [184] = {0xFCF820E8U, 0x0000002AU}, /* RGIDR_MODID[192]:RSW2SEC08 */ + [185] = {0xFCF820ECU, 0x0000002AU}, /* RGIDR_MODID[193]:RSW2SEC09 */ + [186] = {0xFCF820F4U, 0x0000000CU}, /* RGIDR_MODID[194]:AXIPCI000 */ + [187] = {0xFCF820F8U, 0x0000000CU}, /* RGIDR_MODID[195]:AXIPCI004 */ + [188] = {0xFCF820FCU, 0x0000000CU}, /* RGIDR_MODID[196]:IPMMUHC01 */ + [189] = {0xFCF8210CU, 0x0000000CU}, /* RGIDR_MODID[197]:IPMMUHC10 */ + [190] = {0xFCF82110U, 0x0000000CU}, /* RGIDR_MODID[198]:IPMMUHC11 */ + [191] = {0xFCF82114U, 0x0000000CU}, /* RGIDR_MODID[199]:IPMMUHC12 */ + [192] = {0xFCF82118U, 0x0000000CU}, /* RGIDR_MODID[200]:IPMMUHC13 */ + [193] = {0xFCF8211CU, 0x0000000CU}, /* RGIDR_MODID[201]:PPHY0 */ + [194] = {0xFCF82120U, 0x0000000CU}, /* RGIDR_MODID[202]:PPHY1 */ + [195] = {0xFCF82124U, 0x0000000CU}, /* RGIDR_MODID[203]:IPMMUHC14 */ + [196] = {0xFCF82128U, 0x0000000CU}, /* RGIDR_MODID[204]:IPMMUHC15 */ + [197] = {0xFCF8212CU, 0x0000002EU}, /* RGIDR_MODID[205]:FBAHSC */ + [198] = {0xFCF82130U, 0x0000000CU}, /* RGIDR_MODID[206]:IPMMUHC02 */ + [199] = {0xFCF82134U, 0x0000003FU}, /* RGIDR_MODID[207]:AXIUFSS */ + [200] = {0xFCF82138U, 0x0000003BU}, /* RGIDR_MODID[208]:ECMHSC */ + [201] = {0xFCF8213CU, 0x0000003FU}, /* RGIDR_MODID[209]:ARHC0 */ + /* After setting */ /* RGIDR_MODID[210]:ARHC1 */ + /* After setting */ /* RGIDR_MODID[211]:ARHC2 */ + [202] = {0xFCF82148U, 0x0000003FU}, /* RGIDR_MODID[212]:ARHC3 */ + [203] = {0xFCF8214CU, 0x0000003FU}, /* RGIDR_MODID[213]:ARHC4 */ + [204] = {0xFCF82150U, 0x0000003FU}, /* RGIDR_MODID[214]:ARHC5 */ + [205] = {0xFCF82154U, 0x0000003FU}, /* RGIDR_MODID[215]:ARHC6 */ + [206] = {0xFCF82158U, 0x0000003FU}, /* RGIDR_MODID[216]:ARHC7 */ + [207] = {0xFCF8215CU, 0x00000000U}, /* RGIDR_MODID[217]:ARHC8 */ + [208] = {0xFCF82160U, 0x0000000CU}, /* RGIDR_MODID[218]:IPMMUHC03 */ + [209] = {0xFCF82164U, 0x0000000CU}, /* RGIDR_MODID[219]:IPMMUHC04 */ + [210] = {0xFCF82168U, 0x0000000CU}, /* RGIDR_MODID[220]:IPMMUHC05 */ + [211] = {0xFCF8216CU, 0x0000000CU}, /* RGIDR_MODID[221]:IPMMUHC06 */ + [212] = {0xFCF82170U, 0x0000000CU}, /* RGIDR_MODID[222]:IPMMUHC07 */ + [213] = {0xFCF82174U, 0x0000000CU}, /* RGIDR_MODID[223]:IPMMUHC08 */ + [214] = {0xFCF82178U, 0x0000000CU}, /* RGIDR_MODID[224]:IPMMUHC09 */ + [215] = {0xFDC22000U, 0x0000003FU}, /* RGIDR_MODID[225]:ARRC0 */ + /* After setting */ /* RGIDR_MODID[226]:ARRC1 */ + /* After setting */ /* RGIDR_MODID[227]:ARRC2 */ + [216] = {0xFDC2200CU, 0x0000003FU}, /* RGIDR_MODID[228]:ARRC3 */ + [217] = {0xFDC22010U, 0x0000003FU}, /* RGIDR_MODID[229]:ARRC4 */ + [218] = {0xFDC22014U, 0x0000003FU}, /* RGIDR_MODID[230]:ARRC5 */ + [219] = {0xFDC22018U, 0x0000003FU}, /* RGIDR_MODID[231]:ARRC6 */ + [220] = {0xFDC2201CU, 0x0000003FU}, /* RGIDR_MODID[232]:ARRC7 */ + [221] = {0xFDC22020U, 0x00000000U}, /* RGIDR_MODID[233]:ARRC8 */ + [222] = {0xFDC22024U, 0x00000019U}, /* RGIDR_MODID[234]:CR0 */ + [223] = {0xFDC22028U, 0x0000003FU}, /* RGIDR_MODID[235]:ICUMX */ + [224] = {0xFDC2202CU, 0x0000003BU}, /* RGIDR_MODID[236]:ECMRC */ + [225] = {0xFD432000U, 0x0000002EU}, /* RGIDR_MODID[237]:DMAWCRC0 */ + [226] = {0xFD432004U, 0x0000002EU}, /* RGIDR_MODID[238]:DMAWCRC1 */ + [227] = {0xFD432008U, 0x0000002EU}, /* RGIDR_MODID[239]:DMAWCRC2 */ + [228] = {0xFD43200CU, 0x0000002EU}, /* RGIDR_MODID[240]:DMAWCRC3 */ + [229] = {0xFD432010U, 0x0000000CU}, /* RGIDR_MODID[241]:DMATSIP0 */ + [230] = {0xFD432014U, 0x0000000CU}, /* RGIDR_MODID[242]:DMATSIP1 */ + [231] = {0xFD432018U, 0x0000000CU}, /* RGIDR_MODID[243]:DMATSIP2 */ + [232] = {0xFD442000U, 0x0000003FU}, /* RGIDR_MODID[244]:ARMREG00 */ + [233] = {0xFD442004U, 0x0000000CU}, /* RGIDR_MODID[245]:ARMREG01 */ + [234] = {0xFD442008U, 0x00000000U}, /* RGIDR_MODID[246]:ARMREG10 */ + [235] = {0xFD44200CU, 0x00000000U}, /* RGIDR_MODID[247]:ARMREG11 */ + [236] = {0xFD442010U, 0x0000002AU}, /* RGIDR_MODID[248]:ARMREG12 */ + [237] = {0xFD442014U, 0x0000003FU}, /* RGIDR_MODID[249]:ARMREG13 */ + [238] = {0xFD442018U, 0x0000002AU}, /* RGIDR_MODID[250]:ARMREG14 */ + [239] = {0xFD44201CU, 0x00000022U}, /* RGIDR_MODID[251]:AXICR52SS */ + [240] = {0xFD442020U, 0x0000002EU}, /* RGIDR_MODID[252]:AXICSD0 */ + [241] = {0xFD442024U, 0x0000002EU}, /* RGIDR_MODID[253]:AXIINTAP0 */ + [242] = {0xFD442028U, 0x0000002EU}, /* RGIDR_MODID[254]:AXIINTAP1 */ + [243] = {0xFD44202CU, 0x00000019U}, /* RGIDR_MODID[255]:AXISECROM */ + [244] = {0xFD442030U, 0x0000003FU}, /* RGIDR_MODID[256]:AXISYSRAM0 */ + [245] = {0xFD442034U, 0x0000003FU}, /* RGIDR_MODID[257]:AXISYSRAM1 */ + [246] = {0xFD442038U, 0x00000000U}, /* RGIDR_MODID[258]:ARGREG15 */ + [247] = {0xFD44203CU, 0x00000000U}, /* RGIDR_MODID[259]:ARMREG2 */ + [248] = {0xFD442040U, 0x00000000U}, /* RGIDR_MODID[260]:ARMREG3 */ + [249] = {0xFD442044U, 0x00000000U}, /* RGIDR_MODID[261]:ARMREG4 */ + [250] = {0xFD442048U, 0x0000003FU}, /* RGIDR_MODID[262]:ARMREG5 */ + [251] = {0xFD44204CU, 0x0000002AU}, /* RGIDR_MODID[263]:ARMREG6 */ + [252] = {0xFD442050U, 0x00000000U}, /* RGIDR_MODID[264]:ARMREG7 */ + [253] = {0xFD442054U, 0x0000000CU}, /* RGIDR_MODID[265]:ARMREG8 */ + [254] = {0xFD442058U, 0x0000000CU}, /* RGIDR_MODID[266]:ARMREG9 */ + [255] = {0xFD44205CU, 0x0000003FU}, /* RGIDR_MODID[267]:ARRD0 */ + /* After setting */ /* RGIDR_MODID[268]:ARRD1 */ + /* After setting */ /* RGIDR_MODID[269]:ARRD2 */ + [256] = {0xFD442068U, 0x0000003FU}, /* RGIDR_MODID[270]:ARRD3 */ + [257] = {0xFD44206CU, 0x0000003FU}, /* RGIDR_MODID[271]:ARRD4 */ + [258] = {0xFD442070U, 0x0000003FU}, /* RGIDR_MODID[272]:ARRD5 */ + [259] = {0xFD442074U, 0x0000003FU}, /* RGIDR_MODID[273]:ARRD6 */ + [260] = {0xFD442078U, 0x0000003FU}, /* RGIDR_MODID[274]:ARRD7 */ + [261] = {0xFD44207CU, 0x00000000U}, /* RGIDR_MODID[275]:ARRD8 */ + [262] = {0xFD442080U, 0x0000003FU}, /* RGIDR_MODID[276]:ARRT0 */ + /* After setting */ /* RGIDR_MODID[277]:ARRT1 */ + /* After setting */ /* RGIDR_MODID[278]:ARRT2 */ + [263] = {0xFD44208CU, 0x0000003FU}, /* RGIDR_MODID[279]:ARRT3 */ + [264] = {0xFD442090U, 0x0000003FU}, /* RGIDR_MODID[280]:ARRT4 */ + [265] = {0xFD442094U, 0x0000003FU}, /* RGIDR_MODID[281]:ARRT5 */ + [266] = {0xFD442098U, 0x0000003FU}, /* RGIDR_MODID[282]:ARRT6 */ + [267] = {0xFD44209CU, 0x0000003FU}, /* RGIDR_MODID[283]:ARRT7 */ + [268] = {0xFD4420A0U, 0x00000000U}, /* RGIDR_MODID[284]:ARRT8 */ + [269] = {0xFD4420A4U, 0x0000002AU}, /* RGIDR_MODID[285]:CKMRT */ + [270] = {0xFD4420A8U, 0x0000002EU}, /* RGIDR_MODID[286]:CRC0 */ + [271] = {0xFD4420ACU, 0x0000002EU}, /* RGIDR_MODID[287]:CRC1 */ + [272] = {0xFD4420B0U, 0x0000002EU}, /* RGIDR_MODID[288]:CRC2 */ + [273] = {0xFD4420B4U, 0x0000002EU}, /* RGIDR_MODID[289]:CRC3 */ + [274] = {0xFD4420B8U, 0x0000002EU}, /* RGIDR_MODID[290]:CSD */ + [275] = {0xFD4420BCU, 0x0000003BU}, /* RGIDR_MODID[291]:ECM */ + [276] = {0xFD4420C0U, 0x0000003BU}, /* RGIDR_MODID[292]:ECMRT */ + [277] = {0xFD4420C4U, 0x0000002EU}, /* RGIDR_MODID[293]:FBACR52 */ + [278] = {0xFD4420C8U, 0x0000002EU}, /* RGIDR_MODID[294]:FBART */ + [279] = {0xFD4420CCU, 0x0000002EU}, /* RGIDR_MODID[295]:INTTP */ + [280] = {0xFD4420D0U, 0x0000000CU}, /* RGIDR_MODID[296]:IPMMURT000 */ + [281] = {0xFD4420D4U, 0x0000000CU}, /* RGIDR_MODID[297]:IPMMURT100 */ + [282] = {0xFD4420D8U, 0x0000002EU}, /* RGIDR_MODID[298]:KCRC4 */ + [283] = {0xFD4420DCU, 0x0000002EU}, /* RGIDR_MODID[299]:KCRC5 */ + [284] = {0xFD4420E0U, 0x0000002EU}, /* RGIDR_MODID[300]:KCRC6 */ + [285] = {0xFD4420E4U, 0x0000002EU}, /* RGIDR_MODID[301]:KCRC7 */ + [286] = {0xFD4420E8U, 0x0000003FU}, /* RGIDR_MODID[302]:MFI00 */ + [287] = {0xFD4420ECU, 0x0000002EU}, /* RGIDR_MODID[303]:MFI01 */ + [288] = {0xFD4420F0U, 0x0000002EU}, /* RGIDR_MODID[304]:MFI10 */ + [289] = {0xFD4420F4U, 0x0000002EU}, /* RGIDR_MODID[305]:MFI02 */ + [290] = {0xFD4420F8U, 0x0000002EU}, /* RGIDR_MODID[306]:MFI03 */ + [291] = {0xFD4420FCU, 0x0000002EU}, /* RGIDR_MODID[307]:MFI04 */ + [292] = {0xFD442100U, 0x00000000U}, /* RGIDR_MODID[308]:MFI05 */ + [293] = {0xFD442104U, 0x00000000U}, /* RGIDR_MODID[309]:MFI06 */ + [294] = {0xFD442108U, 0x00000000U}, /* RGIDR_MODID[310]:MFI07 */ + [295] = {0xFD44210CU, 0x00000000U}, /* RGIDR_MODID[311]:MFI08 */ + [296] = {0xFD442110U, 0x0000002EU}, /* RGIDR_MODID[312]:MFI09 */ + [297] = {0xFD442114U, 0x0000003FU}, /* RGIDR_MODID[313]:MFI15 */ + [298] = {0xFD442118U, 0x0000002AU}, /* RGIDR_MODID[314]:CKMCR52 */ + [299] = {0xFD44211CU, 0x0000003BU}, /* RGIDR_MODID[315]:RTDM0P */ + [300] = {0xFD442120U, 0x0000003BU}, /* RGIDR_MODID[316]:ECMRD */ + [301] = {0xFD442124U, 0x0000003BU}, /* RGIDR_MODID[317]:RTDM1P */ + [302] = {0xFD44212CU, 0x0000003BU}, /* RGIDR_MODID[318]:RTDM2P */ + [303] = {0xFD442130U, 0x0000003BU}, /* RGIDR_MODID[319]:SYSRAM10 */ + [304] = {0xFD442134U, 0x0000003BU}, /* RGIDR_MODID[320]:RTDM3P */ + [305] = {0xFD442138U, 0x00000003U}, /* RGIDR_MODID[321]:SYSRAM00 */ + [306] = {0xFD44213CU, 0x0000002EU}, /* RGIDR_MODID[322]:TSIPL0 */ + [307] = {0xFD442140U, 0x0000002EU}, /* RGIDR_MODID[323]:TSIPL1 */ + [308] = {0xFD442144U, 0x0000002EU}, /* RGIDR_MODID[324]:TSIPL2 */ + [309] = {0xFD442148U, 0x0000002EU}, /* RGIDR_MODID[325]:TSIPL3 */ + [310] = {0xFD44214CU, 0x0000002EU}, /* RGIDR_MODID[326]:TSIPL4 */ + [311] = {0xFD442150U, 0x0000002EU}, /* RGIDR_MODID[327]:TSIPL5 */ + [312] = {0xFD442154U, 0x0000002EU}, /* RGIDR_MODID[328]:TSIPL6 */ + [313] = {0xFD442158U, 0x0000002EU}, /* RGIDR_MODID[329]:TSIPL7 */ + [314] = {0xFD44215CU, 0x0000002EU}, /* RGIDR_MODID[330]:WCRC0 */ + [315] = {0xFD442160U, 0x0000002EU}, /* RGIDR_MODID[331]:WCRC1 */ + [316] = {0xFD442164U, 0x0000002EU}, /* RGIDR_MODID[332]:WCRC2 */ + [317] = {0xFD442168U, 0x0000002EU}, /* RGIDR_MODID[333]:WCRC3 */ + [318] = {0xFD442174U, 0x0000000CU}, /* RGIDR_MODID[334]:TSIP0 */ + [319] = {0xFD442178U, 0x0000000CU}, /* RGIDR_MODID[335]:TSIP1 */ + [320] = {0xFD44217CU, 0x0000000CU}, /* RGIDR_MODID[336]:TSIP2 */ + [321] = {0xFD442180U, 0x0000002EU}, /* RGIDR_MODID[337]:MFI11 */ + [322] = {0xFD442184U, 0x00000000U}, /* RGIDR_MODID[338]:MFI12 */ + [323] = {0xFD442188U, 0x00000000U}, /* RGIDR_MODID[339]:MFI13 */ + [324] = {0xFD44218CU, 0x00000000U}, /* RGIDR_MODID[340]:MFI14 */ + [325] = {0xFD442190U, 0x0000000CU}, /* RGIDR_MODID[341]:IPMMURT001 */ + [326] = {0xFD442194U, 0x0000000CU}, /* RGIDR_MODID[342]:IPMMURT010 */ + [327] = {0xFD442198U, 0x0000000CU}, /* RGIDR_MODID[343]:IPMMURT011 */ + [328] = {0xFD44219CU, 0x0000000CU}, /* RGIDR_MODID[344]:IPMMURT012 */ + [329] = {0xFD4421A0U, 0x0000000CU}, /* RGIDR_MODID[345]:IPMMURT013 */ + [330] = {0xFD4421A4U, 0x0000000CU}, /* RGIDR_MODID[346]:IPMMURT014 */ + [331] = {0xFD4421A8U, 0x0000000CU}, /* RGIDR_MODID[347]:IPMMURT015 */ + [332] = {0xFD4421ACU, 0x0000000CU}, /* RGIDR_MODID[348]:IPMMURT002 */ + [333] = {0xFD4421B0U, 0x0000000CU}, /* RGIDR_MODID[349]:IPMMURT003 */ + [334] = {0xFD4421B4U, 0x0000000CU}, /* RGIDR_MODID[350]:IPMMURT004 */ + [335] = {0xFD4421B8U, 0x0000000CU}, /* RGIDR_MODID[351]:IPMMURT005 */ + [336] = {0xFD4421BCU, 0x0000000CU}, /* RGIDR_MODID[352]:IPMMURT006 */ + [337] = {0xFD4421C0U, 0x0000000CU}, /* RGIDR_MODID[353]:IPMMURT007 */ + [338] = {0xFD4421C4U, 0x0000000CU}, /* RGIDR_MODID[354]:IPMMURT008 */ + [339] = {0xFD4421C8U, 0x0000000CU}, /* RGIDR_MODID[355]:IPMMURT009 */ + [340] = {0xFD4421CCU, 0x0000000CU}, /* RGIDR_MODID[356]:IPMMURT101 */ + [341] = {0xFD4421D0U, 0x0000000CU}, /* RGIDR_MODID[357]:IPMMURT110 */ + [342] = {0xFD4421D4U, 0x0000000CU}, /* RGIDR_MODID[358]:IPMMURT111 */ + [343] = {0xFD4421D8U, 0x0000000CU}, /* RGIDR_MODID[359]:IPMMURT112 */ + [344] = {0xFD4421DCU, 0x0000000CU}, /* RGIDR_MODID[360]:IPMMURT113 */ + [345] = {0xFD4421E0U, 0x0000000CU}, /* RGIDR_MODID[361]:IPMMURT114 */ + [346] = {0xFD4421E4U, 0x0000000CU}, /* RGIDR_MODID[362]:IPMMURT115 */ + [347] = {0xFD4421E8U, 0x0000000CU}, /* RGIDR_MODID[363]:IPMMURT102 */ + [348] = {0xFD4421ECU, 0x0000000CU}, /* RGIDR_MODID[364]:IPMMURT103 */ + [349] = {0xFD4421F0U, 0x0000000CU}, /* RGIDR_MODID[365]:IPMMURT104 */ + [350] = {0xFD4421F4U, 0x0000000CU}, /* RGIDR_MODID[366]:IPMMURT105 */ + [351] = {0xFD4421F8U, 0x0000000CU}, /* RGIDR_MODID[367]:IPMMURT106 */ + [352] = {0xFD4421FCU, 0x0000000CU}, /* RGIDR_MODID[368]:IPMMURT107 */ + [353] = {0xFD442200U, 0x0000003BU}, /* RGIDR_MODID[369]:RTDM000 */ + [354] = {0xFD442204U, 0x0000003BU}, /* RGIDR_MODID[370]:RTDM001 */ + [355] = {0xFD442208U, 0x0000003BU}, /* RGIDR_MODID[371]:RTDM010 */ + [356] = {0xFD44220CU, 0x0000003BU}, /* RGIDR_MODID[372]:RTDM011 */ + [357] = {0xFD442210U, 0x0000003BU}, /* RGIDR_MODID[373]:RTDM012 */ + [358] = {0xFD442214U, 0x0000003BU}, /* RGIDR_MODID[374]:RTDM013 */ + [359] = {0xFD442218U, 0x0000003BU}, /* RGIDR_MODID[375]:RTDM014 */ + [360] = {0xFD44221CU, 0x0000003BU}, /* RGIDR_MODID[376]:RTDM015 */ + [361] = {0xFD442220U, 0x0000003BU}, /* RGIDR_MODID[377]:RTDM002 */ + [362] = {0xFD442224U, 0x0000003BU}, /* RGIDR_MODID[378]:RTDM003 */ + [363] = {0xFD442228U, 0x0000003BU}, /* RGIDR_MODID[379]:RTDM004 */ + [364] = {0xFD44222CU, 0x0000003BU}, /* RGIDR_MODID[380]:RTDM005 */ + [365] = {0xFD442230U, 0x0000003BU}, /* RGIDR_MODID[381]:RTDM006 */ + [366] = {0xFD442234U, 0x0000003BU}, /* RGIDR_MODID[382]:RTDM007 */ + [367] = {0xFD442238U, 0x0000003BU}, /* RGIDR_MODID[383]:RTDM008 */ + [368] = {0xFD44223CU, 0x0000003BU}, /* RGIDR_MODID[384]:RTDM009 */ + [369] = {0xFD442240U, 0x0000003BU}, /* RGIDR_MODID[385]:RTDM100 */ + [370] = {0xFD442244U, 0x0000003BU}, /* RGIDR_MODID[386]:RTDM101 */ + [371] = {0xFD442248U, 0x0000003BU}, /* RGIDR_MODID[387]:RTDM110 */ + [372] = {0xFD44224CU, 0x0000003BU}, /* RGIDR_MODID[388]:RTDM111 */ + [373] = {0xFD442250U, 0x0000003BU}, /* RGIDR_MODID[389]:RTDM112 */ + [374] = {0xFD442254U, 0x0000003BU}, /* RGIDR_MODID[390]:RTDM113 */ + [375] = {0xFD442258U, 0x0000003BU}, /* RGIDR_MODID[391]:RTDM114 */ + [376] = {0xFD44225CU, 0x0000003BU}, /* RGIDR_MODID[392]:RTDM115 */ + [377] = {0xFD442260U, 0x0000003BU}, /* RGIDR_MODID[393]:RTDM102 */ + [378] = {0xFD442264U, 0x0000003BU}, /* RGIDR_MODID[394]:RTDM103 */ + [379] = {0xFD442268U, 0x0000003BU}, /* RGIDR_MODID[395]:RTDM104 */ + [380] = {0xFD44226CU, 0x0000003BU}, /* RGIDR_MODID[396]:RTDM105 */ + [381] = {0xFD442270U, 0x0000003BU}, /* RGIDR_MODID[397]:RTDM106 */ + [382] = {0xFD442274U, 0x0000003BU}, /* RGIDR_MODID[398]:RTDM107 */ + [383] = {0xFD442278U, 0x0000003BU}, /* RGIDR_MODID[399]:RTDM108 */ + [384] = {0xFD44227CU, 0x0000003BU}, /* RGIDR_MODID[400]:RTDM109 */ + [385] = {0xFD442280U, 0x0000003BU}, /* RGIDR_MODID[401]:RTDM200 */ + [386] = {0xFD442284U, 0x0000003BU}, /* RGIDR_MODID[402]:RTDM201 */ + [387] = {0xFD442288U, 0x0000003BU}, /* RGIDR_MODID[403]:RTDM210 */ + [388] = {0xFD44228CU, 0x0000003BU}, /* RGIDR_MODID[404]:RTDM211 */ + [389] = {0xFD442290U, 0x0000003BU}, /* RGIDR_MODID[405]:RTDM212 */ + [390] = {0xFD442294U, 0x0000003BU}, /* RGIDR_MODID[406]:RTDM213 */ + [391] = {0xFD442298U, 0x0000003BU}, /* RGIDR_MODID[407]:RTDM214 */ + [392] = {0xFD44229CU, 0x0000003BU}, /* RGIDR_MODID[408]:RTDM215 */ + [393] = {0xFD4422A0U, 0x0000003BU}, /* RGIDR_MODID[409]:RTDM202 */ + [394] = {0xFD4422A4U, 0x0000003BU}, /* RGIDR_MODID[410]:RTDM203 */ + [395] = {0xFD4422A8U, 0x0000003BU}, /* RGIDR_MODID[411]:RTDM204 */ + [396] = {0xFD4422ACU, 0x0000003BU}, /* RGIDR_MODID[412]:RTDM205 */ + [397] = {0xFD4422B0U, 0x0000003BU}, /* RGIDR_MODID[413]:RTDM206 */ + [398] = {0xFD4422B4U, 0x0000003BU}, /* RGIDR_MODID[414]:RTDM207 */ + [399] = {0xFD4422B8U, 0x0000003BU}, /* RGIDR_MODID[415]:RTDM208 */ + [400] = {0xFD4422BCU, 0x0000003BU}, /* RGIDR_MODID[416]:RTDM209 */ + [401] = {0xFD4422C0U, 0x0000003BU}, /* RGIDR_MODID[417]:RTDM300 */ + [402] = {0xFD4422C4U, 0x0000003BU}, /* RGIDR_MODID[418]:RTDM301 */ + [403] = {0xFD4422C8U, 0x0000003BU}, /* RGIDR_MODID[419]:RTDM310 */ + [404] = {0xFD4422CCU, 0x0000003BU}, /* RGIDR_MODID[420]:RTDM311 */ + [405] = {0xFD4422D0U, 0x0000003BU}, /* RGIDR_MODID[421]:RTDM312 */ + [406] = {0xFD4422D4U, 0x0000003BU}, /* RGIDR_MODID[422]:RTDM313 */ + [407] = {0xFD4422D8U, 0x0000003BU}, /* RGIDR_MODID[423]:RTDM314 */ + [408] = {0xFD4422DCU, 0x0000003BU}, /* RGIDR_MODID[424]:RTDM315 */ + [409] = {0xFD4422E0U, 0x0000003BU}, /* RGIDR_MODID[425]:RTDM302 */ + [410] = {0xFD4422E4U, 0x0000003BU}, /* RGIDR_MODID[426]:RTDM303 */ + [411] = {0xFD4422E8U, 0x0000003BU}, /* RGIDR_MODID[427]:RTDM304 */ + [412] = {0xFD4422ECU, 0x0000003BU}, /* RGIDR_MODID[428]:RTDM305 */ + [413] = {0xFD4422F0U, 0x0000003BU}, /* RGIDR_MODID[429]:RTDM306 */ + [414] = {0xFD4422F4U, 0x0000003BU}, /* RGIDR_MODID[430]:RTDM307 */ + [415] = {0xFD4422F8U, 0x0000003BU}, /* RGIDR_MODID[431]:RTDM308 */ + [416] = {0xFD4422FCU, 0x0000003BU}, /* RGIDR_MODID[432]:RTDM309 */ + [417] = {0xFD442300U, 0x0000000CU}, /* RGIDR_MODID[433]:IPMMURT108 */ + [418] = {0xFD442304U, 0x0000000CU}, /* RGIDR_MODID[434]:IPMMURT109 */ + [419] = {0xFD442308U, 0x00000011U}, /* RGIDR_MODID[435]:SYSRAM01 */ + [420] = {0xFD44230CU, 0x0000003BU}, /* RGIDR_MODID[436]:SYSRAM02 */ + [421] = {0xFD442310U, 0x00000011U}, /* RGIDR_MODID[437]:SYSRAM03 */ + [422] = {0xFD442314U, 0x00000011U}, /* RGIDR_MODID[438]:SYSRAM04 */ + [423] = {0xFD442318U, 0x00000011U}, /* RGIDR_MODID[439]:SYSRAM05 */ + [424] = {0xFD44231CU, 0x00000011U}, /* RGIDR_MODID[440]:SYSRAM06 */ + [425] = {0xFD442320U, 0x00000000U}, /* RGIDR_MODID[441]:SYSRAM07 */ + [426] = {0xFD442324U, 0x0000003BU}, /* RGIDR_MODID[442]:SYSRAM11 */ + [427] = {0xFD442328U, 0x0000003BU}, /* RGIDR_MODID[443]:SYSRAM12 */ + [428] = {0xFD44232CU, 0x0000003BU}, /* RGIDR_MODID[444]:SYSRAM13 */ + [429] = {0xFD442330U, 0x0000003BU}, /* RGIDR_MODID[445]:SYSRAM14 */ + [430] = {0xFD442334U, 0x0000003BU}, /* RGIDR_MODID[446]:SYSRAM15 */ + [431] = {0xFD442338U, 0x0000003BU}, /* RGIDR_MODID[447]:SYSRAM16 */ + [432] = {0xFD44233CU, 0x00000000U}, /* RGIDR_MODID[448]:SYSRAM17 */ + [433] = {0xFD442360U, 0x00000022U}, /* RGIDR_MODID[449]:BKBUF */ + [434] = {0xFD44236CU, 0x0000003FU}, /* RGIDR_MODID[450]:MCU */ + [435] = {0xFF862000U, 0x0000003FU}, /* RGIDR_MODID[451]:ARSC0 */ + /* After setting */ /* RGIDR_MODID[452]:ARSC1 */ + /* After setting */ /* RGIDR_MODID[453]:ARSC2 */ + [436] = {0xFF86200CU, 0x0000003FU}, /* RGIDR_MODID[454]:ARSC3 */ + [437] = {0xFF862010U, 0x0000003FU}, /* RGIDR_MODID[455]:ARSC4 */ + [438] = {0xFF862014U, 0x0000003FU}, /* RGIDR_MODID[456]:ARSC5 */ + [439] = {0xFF862018U, 0x0000003FU}, /* RGIDR_MODID[457]:ARSC6 */ + [440] = {0xFF86201CU, 0x0000003FU}, /* RGIDR_MODID[458]:ARSC7 */ + [441] = {0xFF862020U, 0x00000000U}, /* RGIDR_MODID[459]:ARSC8 */ + [442] = {0xFF862024U, 0x0000003FU}, /* RGIDR_MODID[460]:ARSTM0 */ + /* After setting */ /* RGIDR_MODID[461]:ARSTM1 */ + [443] = {0xFF862030U, 0x0000002EU}, /* RGIDR_MODID[462]:AXIFBABUSTOP0 */ + [444] = {0xFF862034U, 0x0000002EU}, /* RGIDR_MODID[463]:AXIFBABUSTOP1 */ + /* After setting */ /* RGIDR_MODID[464]:ARSTM2 */ + [445] = {0xFF86203CU, 0x0000003FU}, /* RGIDR_MODID[465]:ARSTM3 */ + [446] = {0xFF862040U, 0x0000003FU}, /* RGIDR_MODID[466]:ARSTM4 */ + [447] = {0xFF862044U, 0x0000003FU}, /* RGIDR_MODID[467]:ARSTM5 */ + [448] = {0xFF862048U, 0x0000003FU}, /* RGIDR_MODID[468]:ARSTM6 */ + [449] = {0xFF86204CU, 0x0000003FU}, /* RGIDR_MODID[469]:ARSTM7 */ + [450] = {0xFF862050U, 0x00000000U}, /* RGIDR_MODID[470]:ARSTM8 */ + [451] = {0xFF862054U, 0x0000003BU}, /* RGIDR_MODID[471]:ECMTOP */ + [452] = {0xFF862058U, 0x0000002EU}, /* RGIDR_MODID[472]:FBA */ + [453] = {0xFF86205CU, 0x0000002EU}, /* RGIDR_MODID[473]:FBC */ + [454] = {0xFF862060U, 0x0000000CU}, /* RGIDR_MODID[474]:AXICCI00 */ + [455] = {0xFF862064U, 0x0000000CU}, /* RGIDR_MODID[475]:AXICCI01 */ + [456] = {0xFF862068U, 0x0000000CU}, /* RGIDR_MODID[476]:AXICCI10 */ + [457] = {0xFF86206CU, 0x0000000CU}, /* RGIDR_MODID[477]:AXICCI11 */ + [458] = {0xFF862070U, 0x0000000CU}, /* RGIDR_MODID[478]:AXICCI12 */ + [459] = {0xFF862074U, 0x0000000CU}, /* RGIDR_MODID[479]:AXICCI13 */ + [460] = {0xFF862078U, 0x0000000CU}, /* RGIDR_MODID[480]:AXICCI14 */ + [461] = {0xFF86207CU, 0x0000000CU}, /* RGIDR_MODID[481]:AXICCI15 */ + [462] = {0xFF862080U, 0x0000000CU}, /* RGIDR_MODID[482]:AXICCI2 */ + [463] = {0xFF862084U, 0x0000000CU}, /* RGIDR_MODID[483]:AXICCI3 */ + [464] = {0xFF862088U, 0x0000000CU}, /* RGIDR_MODID[484]:AXICCI4 */ + [465] = {0xFF86208CU, 0x0000000CU}, /* RGIDR_MODID[485]:AXICCI5 */ + [466] = {0xFF862090U, 0x0000000CU}, /* RGIDR_MODID[486]:AXICCI6 */ + [467] = {0xFF862094U, 0x0000000CU}, /* RGIDR_MODID[487]:AXICCI7 */ + [468] = {0xFF862098U, 0x0000000CU}, /* RGIDR_MODID[488]:AXICCI8 */ + [469] = {0xFF86209CU, 0x0000003FU}, /* RGIDR_MODID[489]:AXICCI9 */ + [470] = {0xFF8620A0U, 0x0000003FU}, /* RGIDR_MODID[490]:ECMSTM */ + [471] = {0xFCB82014U, 0x0000002EU}, /* RGIDR_MODID[491]:DMAI2C0 */ + [472] = {0xFCB82018U, 0x0000002EU}, /* RGIDR_MODID[492]:DMAI2C1 */ + [473] = {0xFCB8201CU, 0x0000002EU}, /* RGIDR_MODID[493]:DMAI2C2 */ + [474] = {0xFCB82020U, 0x0000002EU}, /* RGIDR_MODID[494]:DMAI2C3 */ + [475] = {0xFCB82024U, 0x0000002EU}, /* RGIDR_MODID[495]:DMAI2C4 */ + [476] = {0xFCB82028U, 0x0000002EU}, /* RGIDR_MODID[496]:DMAI2C5 */ + [477] = {0xFDDC2000U, 0x00000000U}, /* RGIDR_MODID[497]:ARMM */ + /* After setting */ /* RGIDR_MODID[498]:AXIARNMM */ + [478] = {0xFDDC2008U, 0x0000003FU}, /* RGIDR_MODID[499]:ARSM0 */ + /* After setting */ /* RGIDR_MODID[500]:ARSM1 */ + /* After setting */ /* RGIDR_MODID[501]:ARSM2 */ + [479] = {0xFDDC2014U, 0x0000003FU}, /* RGIDR_MODID[502]:AXIQOS0 */ + [480] = {0xFDDC2018U, 0x0000003FU}, /* RGIDR_MODID[503]:AXIQOS1 */ + [481] = {0xFDDC201CU, 0x0000003FU}, /* RGIDR_MODID[504]:AXIQOS2 */ + [482] = {0xFDDC2020U, 0x0000003FU}, /* RGIDR_MODID[505]:AXIQOS3 */ + [483] = {0xFDDC2024U, 0x0000003FU}, /* RGIDR_MODID[506]:AXIQOS4 */ + [484] = {0xFDDC2030U, 0x0000003FU}, /* RGIDR_MODID[507]:AXIQOS5 */ + [485] = {0xFDDC2034U, 0x0000003FU}, /* RGIDR_MODID[508]:ARSM3 */ + [486] = {0xFDDC2038U, 0x0000003FU}, /* RGIDR_MODID[509]:ARSM4 */ + [487] = {0xFDDC203CU, 0x0000003FU}, /* RGIDR_MODID[510]:ARSM5 */ + [488] = {0xFDDC2040U, 0x0000003FU}, /* RGIDR_MODID[511]:ARSM6 */ + [489] = {0xFDDC2044U, 0x0000003FU}, /* RGIDR_MODID[512]:ARSM7 */ + [490] = {0xFDDC2048U, 0x00000000U}, /* RGIDR_MODID[513]:ARSM8 */ + [491] = {0xFDDC204CU, 0x0000003FU}, /* RGIDR_MODID[514]:AXMM0 */ + [492] = {0xFDDC2050U, 0x0000003FU}, /* RGIDR_MODID[515]:AXMM1 */ + [493] = {0xFDDC2054U, 0x00000000U}, /* RGIDR_MODID[516]:AXMMPMON */ + [494] = {0xFDDC2058U, 0x0000002AU}, /* RGIDR_MODID[517]:CKMMM */ + [495] = {0xFDDC205CU, 0x0000003BU}, /* RGIDR_MODID[518]:ECMMM */ + [496] = {0xFDDC2068U, 0x0000002EU}, /* RGIDR_MODID[519]:FBAMM */ + [497] = {0xFDDC206CU, 0x0000000CU}, /* RGIDR_MODID[520]:IPMMUMM00 */ + [498] = {0xFDDC2070U, 0x0000003FU}, /* RGIDR_MODID[521]:DBS00 */ + [499] = {0xFDDC2074U, 0x0000002AU}, /* RGIDR_MODID[522]:DBS01 */ + [500] = {0xFDDC2080U, 0x0000003FU}, /* RGIDR_MODID[523]:AXCIDBS */ + [501] = {0xFDDC209CU, 0x0000000CU}, /* RGIDR_MODID[524]:IPMMUMM01 */ + [502] = {0xFDDC20A0U, 0x0000000CU}, /* RGIDR_MODID[525]:IPMMUMM10 */ + [503] = {0xFDDC20A4U, 0x0000000CU}, /* RGIDR_MODID[526]:IPMMUMM11 */ + [504] = {0xFDDC20A8U, 0x0000000CU}, /* RGIDR_MODID[527]:IPMMUMM12 */ + [505] = {0xFDDC20ACU, 0x0000000CU}, /* RGIDR_MODID[528]:IPMMUMM13 */ + [506] = {0xFDDC20B0U, 0x0000000CU}, /* RGIDR_MODID[529]:IPMMUMM14 */ + [507] = {0xFDDC20B4U, 0x0000000CU}, /* RGIDR_MODID[530]:IPMMUMM15 */ + [508] = {0xFDDC20B8U, 0x0000000CU}, /* RGIDR_MODID[531]:IPMMUMM02 */ + [509] = {0xFDDC20BCU, 0x0000000CU}, /* RGIDR_MODID[532]:IPMMUMM03 */ + [510] = {0xFDDC20C0U, 0x0000000CU}, /* RGIDR_MODID[533]:IPMMUMM04 */ + [511] = {0xFDDC20C4U, 0x0000000CU}, /* RGIDR_MODID[534]:IPMMUMM05 */ + [512] = {0xFDDC20C8U, 0x0000000CU}, /* RGIDR_MODID[535]:IPMMUMM06 */ + [513] = {0xFDDC20CCU, 0x0000000CU}, /* RGIDR_MODID[536]:IPMMUMM07 */ + [514] = {0xFDDC20D0U, 0x0000000CU}, /* RGIDR_MODID[537]:IPMMUMM08 */ + [515] = {0xFDDC20D4U, 0x0000000CU}, /* RGIDR_MODID[538]:IPMMUMM09 */ + [516] = {0xFCB52000U, 0x0000003FU}, /* RGIDR_MODID[539]:ARSD00 */ + /* After setting */ /* RGIDR_MODID[540]:ARSD01 */ + /* After setting */ /* RGIDR_MODID[541]:ARSD02 */ + [517] = {0xFCB5200CU, 0x0000003FU}, /* RGIDR_MODID[542]:ARSD03 */ + [518] = {0xFCB52010U, 0x0000003FU}, /* RGIDR_MODID[543]:ARSD04 */ + [519] = {0xFCB52014U, 0x0000003FU}, /* RGIDR_MODID[544]:ARSD05 */ + [520] = {0xFCB52018U, 0x0000003FU}, /* RGIDR_MODID[545]:ARSD06 */ + [521] = {0xFCB52028U, 0x0000003FU}, /* RGIDR_MODID[546]:AXIRPC */ + [522] = {0xFCB5202CU, 0x0000003FU}, /* RGIDR_MODID[547]:AXISDHI0 */ + [523] = {0xFCB52030U, 0x0000003FU}, /* RGIDR_MODID[548]:ARSD07 */ + [524] = {0xFCB52034U, 0x00000000U}, /* RGIDR_MODID[549]:ARSD07 */ + [525] = {0xFCB52038U, 0x0000003FU}, /* RGIDR_MODID[550]:ARSP00 */ + /* After setting */ /* RGIDR_MODID[551]:ARSP01 */ + /* After setting */ /* RGIDR_MODID[552]:ARSP02 */ + [526] = {0xFCB52044U, 0x0000003FU}, /* RGIDR_MODID[553]:ARSP03 */ + [527] = {0xFCB52048U, 0x0000003FU}, /* RGIDR_MODID[554]:ARSP04 */ + [528] = {0xFCB5204CU, 0x0000003FU}, /* RGIDR_MODID[555]:ARSP05 */ + [529] = {0xFCB52050U, 0x0000003FU}, /* RGIDR_MODID[556]:ARSP06 */ + [530] = {0xFCB52054U, 0x00000022U}, /* RGIDR_MODID[557]:ARSP07 */ + [531] = {0xFCB52058U, 0x00000000U}, /* RGIDR_MODID[558]:ARSP08 */ + [532] = {0xFCB5205CU, 0x0000000CU}, /* RGIDR_MODID[559]:IPMMUDS001 */ + [533] = {0xFCB52060U, 0x0000002AU}, /* RGIDR_MODID[560]:CKMPER0 */ + [534] = {0xFCB52064U, 0x0000003BU}, /* RGIDR_MODID[561]:ECMPER0 */ + [535] = {0xFCB52068U, 0x0000002EU}, /* RGIDR_MODID[562]:FBAPER0 */ + [536] = {0xFCB5206CU, 0x0000002EU}, /* RGIDR_MODID[563]:FSO0 */ + [537] = {0xFCB52070U, 0x0000002EU}, /* RGIDR_MODID[564]:FSO1 */ + [538] = {0xFCB52074U, 0x0000002EU}, /* RGIDR_MODID[565]:FSO10 */ + [539] = {0xFCB52078U, 0x0000002EU}, /* RGIDR_MODID[566]:FSO2 */ + [540] = {0xFCB5207CU, 0x0000002EU}, /* RGIDR_MODID[567]:FSO3 */ + [541] = {0xFCB52080U, 0x0000002EU}, /* RGIDR_MODID[568]:FSO4 */ + [542] = {0xFCB52084U, 0x0000002EU}, /* RGIDR_MODID[569]:FSO5 */ + [543] = {0xFCB52088U, 0x0000002EU}, /* RGIDR_MODID[570]:FSO6 */ + [544] = {0xFCB5208CU, 0x0000002EU}, /* RGIDR_MODID[571]:FSO7 */ + [545] = {0xFCB52090U, 0x0000002EU}, /* RGIDR_MODID[572]:FSO8 */ + [546] = {0xFCB52094U, 0x0000002EU}, /* RGIDR_MODID[573]:FSO9 */ + [547] = {0xFCB5209CU, 0x0000003BU}, /* RGIDR_MODID[574]:ECMSD0 */ + [548] = {0xFCB520A0U, 0x0000000CU}, /* RGIDR_MODID[575]:IPMMUDS010 */ + [549] = {0xFCB520A4U, 0x0000000CU}, /* RGIDR_MODID[576]:IPMMUDS011 */ + [550] = {0xFCB520A8U, 0x0000002EU}, /* RGIDR_MODID[577]:I2C0 */ + [551] = {0xFCB520ACU, 0x0000002EU}, /* RGIDR_MODID[578]:I2C1 */ + [552] = {0xFCB520B0U, 0x0000002EU}, /* RGIDR_MODID[579]:I2C2 */ + [553] = {0xFCB520B4U, 0x0000002EU}, /* RGIDR_MODID[580]:I2C3 */ + [554] = {0xFCB520B8U, 0x0000002EU}, /* RGIDR_MODID[581]:I2C4 */ + [555] = {0xFCB520BCU, 0x0000002EU}, /* RGIDR_MODID[582]:I2C5 */ + [556] = {0xFCB520C0U, 0x0000000CU}, /* RGIDR_MODID[583]:IPMMUDS012 */ + [557] = {0xFCB520C8U, 0x0000000CU}, /* RGIDR_MODID[584]:IPMMUDS000 */ + [558] = {0xFCB520CCU, 0x0000000CU}, /* RGIDR_MODID[585]:IPMMUDS013 */ + [559] = {0xFCB520D0U, 0x0000000CU}, /* RGIDR_MODID[586]:IPMMUDS014 */ + [560] = {0xFCB520D4U, 0x0000000CU}, /* RGIDR_MODID[587]:IPMMUDS015 */ + [561] = {0xFCB520D8U, 0x0000000CU}, /* RGIDR_MODID[588]:IPMMUDS002 */ + [562] = {0xFCB520DCU, 0x0000000CU}, /* RGIDR_MODID[589]:IPMMUDS003 */ + [563] = {0xFCB520E0U, 0x0000000CU}, /* RGIDR_MODID[590]:IPMMUDS004 */ + [564] = {0xFCB520E4U, 0x0000000CU}, /* RGIDR_MODID[591]:IPMMUDS005 */ + [565] = {0xFCB520ECU, 0x0000000CU}, /* RGIDR_MODID[592]:IPMMUDS006 */ + [566] = {0xFCB520F0U, 0x0000000CU}, /* RGIDR_MODID[593]:IPMMUDS007 */ + [567] = {0xFCB520F4U, 0x0000000CU}, /* RGIDR_MODID[594]:SYDM1P */ + [568] = {0xFCB520F8U, 0x0000000CU}, /* RGIDR_MODID[595]:IPMMUDS008 */ + [569] = {0xFCB520FCU, 0x0000000CU}, /* RGIDR_MODID[596]:SYDM2P */ + [570] = {0xFCB52100U, 0x0000000CU}, /* RGIDR_MODID[597]:IPMMUDS009 */ + [571] = {0xFCB52240U, 0x0000000CU}, /* RGIDR_MODID[598]:SYDM100 */ + [572] = {0xFCB52244U, 0x0000000CU}, /* RGIDR_MODID[599]:SYDM101 */ + [573] = {0xFCB52248U, 0x0000000CU}, /* RGIDR_MODID[600]:SYDM110 */ + [574] = {0xFCB5224CU, 0x0000000CU}, /* RGIDR_MODID[601]:SYDM111 */ + [575] = {0xFCB52250U, 0x0000000CU}, /* RGIDR_MODID[602]:SYDM112 */ + [576] = {0xFCB52254U, 0x0000000CU}, /* RGIDR_MODID[603]:SYDM113 */ + [577] = {0xFCB52258U, 0x0000000CU}, /* RGIDR_MODID[604]:SYDM114 */ + [578] = {0xFCB5225CU, 0x0000000CU}, /* RGIDR_MODID[605]:SYDM115 */ + [579] = {0xFCB52260U, 0x0000000CU}, /* RGIDR_MODID[606]:SYDM102 */ + [580] = {0xFCB52264U, 0x0000000CU}, /* RGIDR_MODID[607]:SYDM103 */ + [581] = {0xFCB52268U, 0x0000000CU}, /* RGIDR_MODID[608]:SYDM104 */ + [582] = {0xFCB5226CU, 0x0000000CU}, /* RGIDR_MODID[609]:SYDM105 */ + [583] = {0xFCB52270U, 0x0000000CU}, /* RGIDR_MODID[610]:SYDM106 */ + [584] = {0xFCB52274U, 0x0000000CU}, /* RGIDR_MODID[611]:SYDM107 */ + [585] = {0xFCB52278U, 0x0000000CU}, /* RGIDR_MODID[612]:SYDM108 */ + [586] = {0xFCB5227CU, 0x0000000CU}, /* RGIDR_MODID[613]:SYDM109 */ + [587] = {0xFCB52280U, 0x0000000CU}, /* RGIDR_MODID[614]:SYDM200 */ + [588] = {0xFCB52284U, 0x0000000CU}, /* RGIDR_MODID[615]:SYDM201 */ + [589] = {0xFCB52288U, 0x0000000CU}, /* RGIDR_MODID[616]:SYDM210 */ + [590] = {0xFCB5228CU, 0x0000000CU}, /* RGIDR_MODID[617]:SYDM211 */ + [591] = {0xFCB52290U, 0x0000000CU}, /* RGIDR_MODID[618]:SYDM212 */ + [592] = {0xFCB52294U, 0x0000000CU}, /* RGIDR_MODID[619]:SYDM213 */ + [593] = {0xFCB52298U, 0x0000000CU}, /* RGIDR_MODID[620]:SYDM214 */ + [594] = {0xFCB5229CU, 0x0000000CU}, /* RGIDR_MODID[621]:SYDM215 */ + [595] = {0xFCB522A0U, 0x0000000CU}, /* RGIDR_MODID[622]:SYDM202 */ + [596] = {0xFCB522A4U, 0x0000000CU}, /* RGIDR_MODID[623]:SYDM203 */ + [597] = {0xFCB522A8U, 0x0000000CU}, /* RGIDR_MODID[624]:SYDM204 */ + [598] = {0xFCB522ACU, 0x0000000CU}, /* RGIDR_MODID[625]:SYDM205 */ + [599] = {0xFCB522B0U, 0x0000000CU}, /* RGIDR_MODID[626]:SYDM206 */ + [600] = {0xFCB522B4U, 0x0000000CU}, /* RGIDR_MODID[627]:SYDM207 */ + [601] = {0xFCB522B8U, 0x0000000CU}, /* RGIDR_MODID[628]:SYDM208 */ + [602] = {0xFCB522BCU, 0x0000000CU}, /* RGIDR_MODID[629]:SYDM209 */ + [604] = {0xFDDB9660U, 0x0000003FU}, /* RGIDR_MODID[630]:ARCC */ + [603] = {0xFDDB9674U, 0x0000003FU}, /* RGIDR_MODID[631]:ARRTRAM */ + [605] = {0xFCB52024U, 0x00000000U}, /* RGIDR_MODID[632]:RSV0 */ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_w_tbl" +const REGION_ID_SETTING_TABLE g_rgid_w_tbl[] = { + [0] = {0xFD482400U, 0x0000002EU}, /* RGIDW_MODID[0]:ARMGC0 */ + [1] = {0xFD482404U, 0x0000002EU}, /* RGIDW_MODID[1]:ARMGC1 */ + [2] = {0xFD482408U, 0x00000000U}, /* RGIDW_MODID[2]:ARMGC2 */ + [3] = {0xFD48240CU, 0x00000022U}, /* RGIDW_MODID[3]:ARRT00 */ + /* After setting */ /* RGIDW_MODID[4]:ARRT01 */ + /* After setting */ /* RGIDW_MODID[5]:ARRT02 */ + [4] = {0xFD482418U, 0x00000011U}, /* RGIDW_MODID[6]:ARRT03 */ + [5] = {0xFD48241CU, 0x00000022U}, /* RGIDW_MODID[7]:ARRT04 */ + [6] = {0xFD482420U, 0x00000011U}, /* RGIDW_MODID[8]:ARRT05 */ + [7] = {0xFD482424U, 0x00000022U}, /* RGIDW_MODID[9]:ARRT06 */ + [8] = {0xFD482428U, 0x00000022U}, /* RGIDW_MODID[10]:ARRT07 */ + [9] = {0xFD48242CU, 0x00000000U}, /* RGIDW_MODID[11]:ARRT08 */ + [10] = {0xFD482430U, 0x00000011U}, /* RGIDW_MODID[12]:LIFEC0 */ + [11] = {0xFD482434U, 0x00000026U}, /* RGIDW_MODID[13]:SWDT */ + [12] = {0xFD482438U, 0x0000003FU}, /* RGIDW_MODID[14]:TMU0 */ + [13] = {0xFD48243CU, 0x00000026U}, /* RGIDW_MODID[15]:WDT */ + [14] = {0xFD482440U, 0x00000026U}, /* RGIDW_MODID[16]:WWDT0 */ + [15] = {0xFD482444U, 0x00000026U}, /* RGIDW_MODID[17]:WWDT1 */ + [16] = {0xFD482448U, 0x00000026U}, /* RGIDW_MODID[18]:WWDT2 */ + [17] = {0xFD48244CU, 0x00000026U}, /* RGIDW_MODID[19]:WWDT3 */ + [18] = {0xFD482450U, 0x00000026U}, /* RGIDW_MODID[20]:WWDT4 */ + [19] = {0xFD482454U, 0x00000026U}, /* RGIDW_MODID[21]:WWDT5 */ + [20] = {0xFD482458U, 0x00000026U}, /* RGIDW_MODID[22]:WWDT6 */ + [21] = {0xFD48245CU, 0x00000026U}, /* RGIDW_MODID[23]:WWDT7 */ + [22] = {0xFD482460U, 0x00000026U}, /* RGIDW_MODID[24]:WWDT8 */ + [23] = {0xFD482464U, 0x00000026U}, /* RGIDW_MODID[25]:WWDT9 */ + [24] = {0xFD482468U, 0x0000003FU}, /* RGIDW_MODID[26]:ECMRT3 */ + [25] = {0xFDA02400U, 0x00000026U}, /* RGIDW_MODID[27]:ADVFSC */ + [26] = {0xFDA02404U, 0x0000003FU}, /* RGIDW_MODID[28]:APMU0 */ + [27] = {0xFDA02408U, 0x00000002U}, /* RGIDW_MODID[29]:APMU1 */ + [28] = {0xFDA0240CU, 0x00000000U}, /* RGIDW_MODID[30]:APMU10 */ + [29] = {0xFDA02410U, 0x00000000U}, /* RGIDW_MODID[31]:APMU11 */ + [30] = {0xFDA02414U, 0x00000000U}, /* RGIDW_MODID[32]:APMU12 */ + [31] = {0xFDA02418U, 0x00000000U}, /* RGIDW_MODID[33]:APMU13 */ + [32] = {0xFDA0241CU, 0x00000000U}, /* RGIDW_MODID[34]:APMU14 */ + [33] = {0xFDA02420U, 0x00000000U}, /* RGIDW_MODID[35]:APMU15 */ + [34] = {0xFDA02424U, 0x00000004U}, /* RGIDW_MODID[36]:APMU2 */ + [35] = {0xFDA02428U, 0x00000004U}, /* RGIDW_MODID[37]:APMU3 */ + [36] = {0xFDA0242CU, 0x00000000U}, /* RGIDW_MODID[38]:APMU4 */ + [37] = {0xFDA02430U, 0x00000000U}, /* RGIDW_MODID[39]:APMU5 */ + [38] = {0xFDA02434U, 0x00000000U}, /* RGIDW_MODID[40]:APMU6 */ + [39] = {0xFDA02438U, 0x00000000U}, /* RGIDW_MODID[41]:APMU7 */ + [40] = {0xFDA0243CU, 0x00000000U}, /* RGIDW_MODID[42]:APMU8 */ + [41] = {0xFDA02440U, 0x00000000U}, /* RGIDW_MODID[43]:APMU9 */ + [42] = {0xFDA02444U, 0x00000022U}, /* RGIDW_MODID[44]:ARS00 */ + /* After setting */ /* RGIDW_MODID[45]:ARS01 */ + /* After setting */ /* RGIDW_MODID[46]:ARS02 */ + [43] = {0xFDA02450U, 0x00000011U}, /* RGIDW_MODID[47]:ARS03 */ + [44] = {0xFDA02454U, 0x00000022U}, /* RGIDW_MODID[48]:ARS04 */ + [45] = {0xFDA02458U, 0x00000011U}, /* RGIDW_MODID[49]:ARS05 */ + [46] = {0xFDA0245CU, 0x00000022U}, /* RGIDW_MODID[50]:ARS06 */ + [47] = {0xFDA02460U, 0x00000022U}, /* RGIDW_MODID[51]:ARS07 */ + [48] = {0xFDA02464U, 0x00000000U}, /* RGIDW_MODID[52]:ARS08 */ + [49] = {0xFDA02468U, 0x0000002EU}, /* RGIDW_MODID[53]:CMT0 */ + [50] = {0xFDA0246CU, 0x0000002EU}, /* RGIDW_MODID[54]:CMT1 */ + [51] = {0xFDA02470U, 0x0000002EU}, /* RGIDW_MODID[55]:CMT2 */ + [52] = {0xFDA02474U, 0x0000002EU}, /* RGIDW_MODID[56]:CMT3 */ + [53] = {0xFDA02478U, 0x0000002AU}, /* RGIDW_MODID[57]:CKM */ + [54] = {0xFDA0247CU, 0x0000002EU}, /* RGIDW_MODID[58]:DBE */ + [55] = {0xFDA02480U, 0x0000002EU}, /* RGIDW_MODID[59]:IRQC */ + [56] = {0xFDA02484U, 0x0000003BU}, /* RGIDW_MODID[60]:ECMPS0 */ + [57] = {0xFDA0249CU, 0x0000002EU}, /* RGIDW_MODID[61]:SCMT */ + [58] = {0xFDA024A8U, 0x0000002EU}, /* RGIDW_MODID[62]:TSC1 */ + [59] = {0xFDA024ACU, 0x0000002EU}, /* RGIDW_MODID[63]:TSC2 */ + [60] = {0xFDA024B0U, 0x0000002EU}, /* RGIDW_MODID[64]:TSC3 */ + [61] = {0xFDA024B4U, 0x0000002EU}, /* RGIDW_MODID[65]:TSC4 */ + [62] = {0xFDA024B8U, 0x00000026U}, /* RGIDW_MODID[66]:UCMT */ + [63] = {0xFDA02500U, 0x0000003FU}, /* RGIDW_MODID[67]:CPG0 */ + [64] = {0xFDA02504U, 0x0000002AU}, /* RGIDW_MODID[68]:CPG1 */ + [65] = {0xFDA02508U, 0x0000000CU}, /* RGIDW_MODID[69]:CPG2 */ + [66] = {0xFDA0250CU, 0x0000000CU}, /* RGIDW_MODID[70]:CPG3 */ + [67] = {0xFDA02510U, 0x0000003FU}, /* RGIDW_MODID[71]:PFC00 */ + [68] = {0xFDA02514U, 0x0000002AU}, /* RGIDW_MODID[72]:PFC01 */ + [69] = {0xFDA02518U, 0x0000000CU}, /* RGIDW_MODID[73]:PFC02 */ + [70] = {0xFDA0251CU, 0x0000000CU}, /* RGIDW_MODID[74]:PFC03 */ + [71] = {0xFDA02550U, 0x0000003FU}, /* RGIDW_MODID[75]:PFCS0 */ + [72] = {0xFDA02554U, 0x0000002AU}, /* RGIDW_MODID[76]:PFCS1 */ + [73] = {0xFDA02558U, 0x0000000CU}, /* RGIDW_MODID[77]:PFCS2 */ + [74] = {0xFDA0255CU, 0x0000000CU}, /* RGIDW_MODID[78]:PFCS3 */ + [75] = {0xFDA02560U, 0x0000003FU}, /* RGIDW_MODID[79]:RESET0 */ + [76] = {0xFDA02564U, 0x0000002AU}, /* RGIDW_MODID[80]:RESET1 */ + [77] = {0xFDA02568U, 0x0000000CU}, /* RGIDW_MODID[81]:RESET2 */ + [78] = {0xFDA0256CU, 0x0000000CU}, /* RGIDW_MODID[82]:RESET3 */ + [79] = {0xFDA02570U, 0x0000003FU}, /* RGIDW_MODID[83]:SYS0 */ + [80] = {0xFDA02574U, 0x0000002AU}, /* RGIDW_MODID[84]:SYS1 */ + [81] = {0xFDA02578U, 0x0000000CU}, /* RGIDW_MODID[85]:SYS2 */ + [82] = {0xFDA0257CU, 0x0000000CU}, /* RGIDW_MODID[86]:SYS3 */ + [83] = {0xFCB62400U, 0x0000002EU}, /* RGIDW_MODID[87]:DMAMSI0 */ + [84] = {0xFCB62404U, 0x0000002EU}, /* RGIDW_MODID[88]:DMAMSI1 */ + [85] = {0xFCB62408U, 0x0000002EU}, /* RGIDW_MODID[89]:DMAMSI2 */ + [86] = {0xFCB6240CU, 0x0000002EU}, /* RGIDW_MODID[90]:DMAMSI3 */ + [87] = {0xFCB62418U, 0x0000003BU}, /* RGIDW_MODID[91]:ECMSP3 */ + [88] = {0xFCB62424U, 0x00000022U}, /* RGIDW_MODID[92]:ARSP30 */ + /* After setting */ /* RGIDW_MODID[93]:ARSP31 */ + /* After setting */ /* RGIDW_MODID[94]:ARSP32 */ + [89] = {0xFCB62430U, 0x00000011U}, /* RGIDW_MODID[95]:ARSP33 */ + [90] = {0xFCB62434U, 0x00000022U}, /* RGIDW_MODID[96]:ARSP34 */ + [91] = {0xFCB62438U, 0x00000011U}, /* RGIDW_MODID[97]:ARSP35 */ + [92] = {0xFCB6243CU, 0x00000022U}, /* RGIDW_MODID[98]:ARSP36 */ + [93] = {0xFCB62440U, 0x00000022U}, /* RGIDW_MODID[99]:ARSP37 */ + [94] = {0xFCB62444U, 0x00000000U}, /* RGIDW_MODID[100]:ARSP38 */ + [95] = {0xFCB62448U, 0x0000002EU}, /* RGIDW_MODID[101]:MSI0 */ + [96] = {0xFCB6244CU, 0x0000002EU}, /* RGIDW_MODID[102]:MSI1 */ + [97] = {0xFCB62450U, 0x0000002EU}, /* RGIDW_MODID[103]:MSI2 */ + [98] = {0xFCB62454U, 0x0000002EU}, /* RGIDW_MODID[104]:MSI3 */ + [99] = {0xFCB92400U, 0x00000022U}, /* RGIDW_MODID[105]:ARSP40 */ + /* After setting */ /* RGIDW_MODID[106]:ARSP41 */ + /* After setting */ /* RGIDW_MODID[107]:ARSP42 */ + [100] = {0xFCB9240CU, 0x00000011U}, /* RGIDW_MODID[108]:ARSP43 */ + [101] = {0xFCB92410U, 0x00000022U}, /* RGIDW_MODID[109]:ARSP44 */ + [102] = {0xFCB92414U, 0x00000011U}, /* RGIDW_MODID[110]:ARSP45 */ + [103] = {0xFCB92418U, 0x00000022U}, /* RGIDW_MODID[111]:ARSP46 */ + [104] = {0xFCB9241CU, 0x00000022U}, /* RGIDW_MODID[112]:ARSP47 */ + [105] = {0xFCB92420U, 0x00000000U}, /* RGIDW_MODID[113]:ARSP48 */ + [106] = {0xFCB92424U, 0x0000003FU}, /* RGIDW_MODID[114]:DMAHSCIF0 */ + [107] = {0xFCB92428U, 0x0000003FU}, /* RGIDW_MODID[115]:DMAHSCIF1 */ + [108] = {0xFCB9242CU, 0x0000003FU}, /* RGIDW_MODID[116]:DMAHSCIF2 */ + [109] = {0xFCB92430U, 0x0000003FU}, /* RGIDW_MODID[117]:DMAHSCIF3 */ + [110] = {0xFCB92434U, 0x0000003FU}, /* RGIDW_MODID[118]:DMASCIF0 */ + [111] = {0xFCB92438U, 0x0000003FU}, /* RGIDW_MODID[119]:DMASCIF1 */ + [112] = {0xFCB9243CU, 0x0000003FU}, /* RGIDW_MODID[120]:DMASCIF3 */ + [113] = {0xFCB92440U, 0x0000003FU}, /* RGIDW_MODID[121]:DMASCIF4 */ + [114] = {0xFCB92444U, 0x0000003BU}, /* RGIDW_MODID[122]:ECMSP4 */ + [115] = {0xFCB92448U, 0x0000003FU}, /* RGIDW_MODID[123]:HSCIF0 */ + [116] = {0xFCB9244CU, 0x0000003FU}, /* RGIDW_MODID[124]:HSCIF1 */ + [117] = {0xFCB92450U, 0x0000003FU}, /* RGIDW_MODID[125]:HSCIF2 */ + [118] = {0xFCB92454U, 0x0000003FU}, /* RGIDW_MODID[126]:HSCIF3 */ + [119] = {0xFCB92458U, 0x0000003FU}, /* RGIDW_MODID[127]:SCIF0 */ + [120] = {0xFCB9245CU, 0x0000003FU}, /* RGIDW_MODID[128]:SCIF1 */ + [121] = {0xFCB92460U, 0x0000003FU}, /* RGIDW_MODID[129]:SCIF3 */ + [122] = {0xFCB92464U, 0x0000003FU}, /* RGIDW_MODID[130]:SCIF4 */ + [123] = {0xFCB92468U, 0x0000003FU}, /* RGIDW_MODID[131]:TMU1 */ + [124] = {0xFCB9246CU, 0x0000003FU}, /* RGIDW_MODID[132]:TMU2 */ + [125] = {0xFCB92470U, 0x0000003FU}, /* RGIDW_MODID[133]:TMU3 */ + [126] = {0xFCB92474U, 0x0000003FU}, /* RGIDW_MODID[134]:TMU4 */ + [127] = {0xFCF82400U, 0x0000002AU}, /* RGIDW_MODID[135]:CKMHSC */ + [128] = {0xFCF82404U, 0x0000000CU}, /* RGIDW_MODID[136]:AXIPCI001 */ + [129] = {0xFCF82408U, 0x0000000CU}, /* RGIDW_MODID[137]:AXIPCI002 */ + [130] = {0xFCF8240CU, 0x0000000CU}, /* RGIDW_MODID[138]:AXIPCI003 */ + [131] = {0xFCF82410U, 0x0000002EU}, /* RGIDW_MODID[139]:ETHPHY */ + [132] = {0xFCF82414U, 0x0000000CU}, /* RGIDW_MODID[140]:AXIPCI005 */ + [133] = {0xFCF82418U, 0x0000000CU}, /* RGIDW_MODID[141]:AXIPCI006 */ + [134] = {0xFCF8241CU, 0x0000000CU}, /* RGIDW_MODID[142]:AXIPCI007 */ + [135] = {0xFCF82420U, 0x0000000CU}, /* RGIDW_MODID[143]:AXIPCI008 */ + [136] = {0xFCF82424U, 0x0000000CU}, /* RGIDW_MODID[144]:AXIPCI009 */ + [137] = {0xFCF82428U, 0x0000000CU}, /* RGIDW_MODID[145]:AXIPCI010 */ + [138] = {0xFCF8242CU, 0x0000000CU}, /* RGIDW_MODID[146]:AXIPCI011 */ + [139] = {0xFCF82430U, 0x0000000CU}, /* RGIDW_MODID[147]:AXIPCI012 */ + [140] = {0xFCF82434U, 0x0000000CU}, /* RGIDW_MODID[148]:AXIPCI013 */ + [141] = {0xFCF82438U, 0x0000000CU}, /* RGIDW_MODID[149]:AXIPCI014 */ + [142] = {0xFCF8243CU, 0x0000000CU}, /* RGIDW_MODID[150]:AXIPCI015 */ + [143] = {0xFCF82440U, 0x0000000CU}, /* RGIDW_MODID[151]:AXIPCI100 */ + [144] = {0xFCF82444U, 0x0000000CU}, /* RGIDW_MODID[152]:AXIPCI101 */ + [145] = {0xFCF82448U, 0x0000000CU}, /* RGIDW_MODID[153]:AXIPCI102 */ + [146] = {0xFCF8244CU, 0x0000000CU}, /* RGIDW_MODID[154]:AXIPCI103 */ + [147] = {0xFCF82450U, 0x0000000CU}, /* RGIDW_MODID[155]:AXIPCI104 */ + [148] = {0xFCF82454U, 0x0000000CU}, /* RGIDW_MODID[156]:AXIPCI105 */ + [149] = {0xFCF82458U, 0x0000000CU}, /* RGIDW_MODID[157]:AXIPCI106 */ + [150] = {0xFCF8245CU, 0x0000000CU}, /* RGIDW_MODID[158]:AXIPCI107 */ + [151] = {0xFCF82460U, 0x0000000CU}, /* RGIDW_MODID[159]:AXIPCI108 */ + [152] = {0xFCF82464U, 0x0000000CU}, /* RGIDW_MODID[160]:AXIPCI109 */ + [153] = {0xFCF82468U, 0x0000000CU}, /* RGIDW_MODID[161]:AXIPCI110 */ + [154] = {0xFCF8246CU, 0x0000000CU}, /* RGIDW_MODID[162]:AXIPCI111 */ + [155] = {0xFCF82470U, 0x0000000CU}, /* RGIDW_MODID[163]:AXIPCI112 */ + [156] = {0xFCF82474U, 0x0000000CU}, /* RGIDW_MODID[164]:AXIPCI113 */ + [157] = {0xFCF82478U, 0x0000000CU}, /* RGIDW_MODID[165]:AXIPCI114 */ + [158] = {0xFCF8247CU, 0x0000000CU}, /* RGIDW_MODID[166]:AXIPCI115 */ + [159] = {0xFCF82480U, 0x0000002EU}, /* RGIDW_MODID[167]:ETHPHYRAM */ + [160] = {0xFCF82488U, 0x0000000CU}, /* RGIDW_MODID[168]:IPMMUHC00 */ + [161] = {0xFCF8248CU, 0x0000002EU}, /* RGIDW_MODID[169]:RSW200 */ + [162] = {0xFCF82490U, 0x0000002EU}, /* RGIDW_MODID[170]:RSW201 */ + [163] = {0xFCF82494U, 0x0000002EU}, /* RGIDW_MODID[171]:RSW210 */ + [164] = {0xFCF82498U, 0x0000002EU}, /* RGIDW_MODID[172]:RSW211 */ + [165] = {0xFCF8249CU, 0x0000002EU}, /* RGIDW_MODID[173]:RSW202 */ + [166] = {0xFCF824A0U, 0x0000002EU}, /* RGIDW_MODID[174]:RSW203 */ + [167] = {0xFCF824A4U, 0x0000002EU}, /* RGIDW_MODID[175]:RSW204 */ + [168] = {0xFCF824A8U, 0x0000002EU}, /* RGIDW_MODID[176]:RSW205 */ + [169] = {0xFCF824ACU, 0x0000002EU}, /* RGIDW_MODID[177]:RSW206 */ + [170] = {0xFCF824B0U, 0x0000002EU}, /* RGIDW_MODID[178]:RSW207 */ + [171] = {0xFCF824B4U, 0x0000002EU}, /* RGIDW_MODID[179]:RSW208 */ + [172] = {0xFCF824B8U, 0x0000002EU}, /* RGIDW_MODID[180]:RSW209 */ + [173] = {0xFCF824BCU, 0x0000002EU}, /* RGIDW_MODID[181]:RSW2RAM */ + [174] = {0xFCF824C0U, 0x0000002AU}, /* RGIDW_MODID[182]:RSW2SEC00 */ + [175] = {0xFCF824C4U, 0x0000002AU}, /* RGIDW_MODID[183]:RSW2SEC01 */ + [176] = {0xFCF824C8U, 0x0000002AU}, /* RGIDW_MODID[184]:RSW2SEC10 */ + [177] = {0xFCF824CCU, 0x0000002AU}, /* RGIDW_MODID[185]:RSW2SEC11 */ + [178] = {0xFCF824D0U, 0x0000002AU}, /* RGIDW_MODID[186]:RSW2SEC02 */ + [179] = {0xFCF824D4U, 0x0000002AU}, /* RGIDW_MODID[187]:RSW2SEC03 */ + [180] = {0xFCF824D8U, 0x0000002AU}, /* RGIDW_MODID[188]:RSW2SEC04 */ + [181] = {0xFCF824DCU, 0x0000002AU}, /* RGIDW_MODID[189]:RSW2SEC05 */ + [182] = {0xFCF824E0U, 0x0000002AU}, /* RGIDW_MODID[190]:RSW2SEC06 */ + [183] = {0xFCF824E4U, 0x0000002AU}, /* RGIDW_MODID[191]:RSW2SEC07 */ + [184] = {0xFCF824E8U, 0x0000002AU}, /* RGIDW_MODID[192]:RSW2SEC08 */ + [185] = {0xFCF824ECU, 0x0000002AU}, /* RGIDW_MODID[193]:RSW2SEC09 */ + [186] = {0xFCF824F4U, 0x0000000CU}, /* RGIDW_MODID[194]:AXIPCI000 */ + [187] = {0xFCF824F8U, 0x0000000CU}, /* RGIDW_MODID[195]:AXIPCI004 */ + [188] = {0xFCF824FCU, 0x0000000CU}, /* RGIDW_MODID[196]:IPMMUHC01 */ + [189] = {0xFCF8250CU, 0x0000000CU}, /* RGIDW_MODID[197]:IPMMUHC10 */ + [190] = {0xFCF82510U, 0x0000000CU}, /* RGIDW_MODID[198]:IPMMUHC11 */ + [191] = {0xFCF82514U, 0x0000000CU}, /* RGIDW_MODID[199]:IPMMUHC12 */ + [192] = {0xFCF82518U, 0x0000000CU}, /* RGIDW_MODID[200]:IPMMUHC13 */ + [193] = {0xFCF8251CU, 0x0000000CU}, /* RGIDW_MODID[201]:PPHY0 */ + [194] = {0xFCF82520U, 0x0000000CU}, /* RGIDW_MODID[202]:PPHY1 */ + [195] = {0xFCF82524U, 0x0000000CU}, /* RGIDW_MODID[203]:IPMMUHC14 */ + [196] = {0xFCF82528U, 0x0000000CU}, /* RGIDW_MODID[204]:IPMMUHC15 */ + [197] = {0xFCF8252CU, 0x0000002EU}, /* RGIDW_MODID[205]:FBAHSC */ + [198] = {0xFCF82530U, 0x0000000CU}, /* RGIDW_MODID[206]:IPMMUHC02 */ + [199] = {0xFCF82534U, 0x0000003FU}, /* RGIDW_MODID[207]:AXIUFSS */ + [200] = {0xFCF82538U, 0x0000003BU}, /* RGIDW_MODID[208]:ECMHSC */ + [201] = {0xFCF8253CU, 0x00000022U}, /* RGIDW_MODID[209]:ARHC0 */ + /* After setting */ /* RGIDW_MODID[210]:ARHC1 */ + /* After setting */ /* RGIDW_MODID[211]:ARHC2 */ + [202] = {0xFCF82548U, 0x00000011U}, /* RGIDW_MODID[212]:ARHC3 */ + [203] = {0xFCF8254CU, 0x00000022U}, /* RGIDW_MODID[213]:ARHC4 */ + [204] = {0xFCF82550U, 0x00000011U}, /* RGIDW_MODID[214]:ARHC5 */ + [205] = {0xFCF82554U, 0x00000022U}, /* RGIDW_MODID[215]:ARHC6 */ + [206] = {0xFCF82558U, 0x00000022U}, /* RGIDW_MODID[216]:ARHC7 */ + [207] = {0xFCF8255CU, 0x00000000U}, /* RGIDW_MODID[217]:ARHC8 */ + [208] = {0xFCF82560U, 0x0000000CU}, /* RGIDW_MODID[218]:IPMMUHC03 */ + [209] = {0xFCF82564U, 0x0000000CU}, /* RGIDW_MODID[219]:IPMMUHC04 */ + [210] = {0xFCF82568U, 0x0000000CU}, /* RGIDW_MODID[220]:IPMMUHC05 */ + [211] = {0xFCF8256CU, 0x0000000CU}, /* RGIDW_MODID[221]:IPMMUHC06 */ + [212] = {0xFCF82570U, 0x0000000CU}, /* RGIDW_MODID[222]:IPMMUHC07 */ + [213] = {0xFCF82574U, 0x0000000CU}, /* RGIDW_MODID[223]:IPMMUHC08 */ + [214] = {0xFCF82578U, 0x0000000CU}, /* RGIDW_MODID[224]:IPMMUHC09 */ + [215] = {0xFDC22400U, 0x00000022U}, /* RGIDW_MODID[225]:ARRC0 */ + [216] = {0xFDC22404U, 0x00000000U}, /* RGIDW_MODID[226]:ARRC1 */ + /* After setting */ /* RGIDW_MODID[227]:ARRC2 */ + /* After setting */ /* RGIDW_MODID[228]:ARRC3 */ + [217] = {0xFDC22410U, 0x00000022U}, /* RGIDW_MODID[229]:ARRC4 */ + [218] = {0xFDC22414U, 0x00000011U}, /* RGIDW_MODID[230]:ARRC5 */ + [219] = {0xFDC22418U, 0x00000022U}, /* RGIDW_MODID[231]:ARRC6 */ + [220] = {0xFDC2241CU, 0x00000022U}, /* RGIDW_MODID[232]:ARRC7 */ + [221] = {0xFDC22420U, 0x00000000U}, /* RGIDW_MODID[233]:ARRC8 */ + [222] = {0xFDC22424U, 0x00000019U}, /* RGIDW_MODID[234]:CR0 */ + [223] = {0xFDC22428U, 0x0000003FU}, /* RGIDW_MODID[235]:ICUMX */ + [224] = {0xFDC2242CU, 0x0000003BU}, /* RGIDW_MODID[236]:ECMRC */ + [225] = {0xFD432400U, 0x0000002EU}, /* RGIDW_MODID[237]:DMAWCRC0 */ + [226] = {0xFD432404U, 0x0000002EU}, /* RGIDW_MODID[238]:DMAWCRC1 */ + [227] = {0xFD432408U, 0x0000002EU}, /* RGIDW_MODID[239]:DMAWCRC2 */ + [228] = {0xFD43240CU, 0x0000002EU}, /* RGIDW_MODID[240]:DMAWCRC3 */ + [229] = {0xFD432410U, 0x0000000CU}, /* RGIDW_MODID[241]:DMATSIP0 */ + [230] = {0xFD432414U, 0x0000000CU}, /* RGIDW_MODID[242]:DMATSIP1 */ + [231] = {0xFD432418U, 0x0000000CU}, /* RGIDW_MODID[243]:DMATSIP2 */ + [232] = {0xFD442400U, 0x0000003FU}, /* RGIDW_MODID[244]:ARMREG00 */ + [233] = {0xFD442404U, 0x0000000CU}, /* RGIDW_MODID[245]:ARMREG01 */ + [234] = {0xFD442408U, 0x00000000U}, /* RGIDW_MODID[246]:ARMREG10 */ + [235] = {0xFD44240CU, 0x00000000U}, /* RGIDW_MODID[247]:ARMREG11 */ + [236] = {0xFD442410U, 0x0000002AU}, /* RGIDW_MODID[248]:ARMREG12 */ + [237] = {0xFD442414U, 0x0000003FU}, /* RGIDW_MODID[249]:ARMREG13 */ + [238] = {0xFD442418U, 0x0000002AU}, /* RGIDW_MODID[250]:ARMREG14 */ + [239] = {0xFD44241CU, 0x00000033U}, /* RGIDW_MODID[251]:AXICR52SS */ + [240] = {0xFD442420U, 0x0000002EU}, /* RGIDW_MODID[252]:AXICSD0 */ + [241] = {0xFD442424U, 0x0000002EU}, /* RGIDW_MODID[253]:AXIINTAP0 */ + [242] = {0xFD442428U, 0x0000002EU}, /* RGIDW_MODID[254]:AXIINTAP1 */ + [243] = {0xFD44242CU, 0x00000019U}, /* RGIDW_MODID[255]:AXISECROM */ + [244] = {0xFD442430U, 0x0000003FU}, /* RGIDW_MODID[256]:AXISYSRAM0 */ + [245] = {0xFD442434U, 0x0000003FU}, /* RGIDW_MODID[257]:AXISYSRAM1 */ + [246] = {0xFD442438U, 0x00000000U}, /* RGIDW_MODID[258]:ARGREG15 */ + [247] = {0xFD44243CU, 0x00000000U}, /* RGIDW_MODID[259]:ARMREG2 */ + [248] = {0xFD442440U, 0x00000000U}, /* RGIDW_MODID[260]:ARMREG3 */ + [249] = {0xFD442444U, 0x00000000U}, /* RGIDW_MODID[261]:ARMREG4 */ + [250] = {0xFD442448U, 0x0000003FU}, /* RGIDW_MODID[262]:ARMREG5 */ + [251] = {0xFD44244CU, 0x0000002AU}, /* RGIDW_MODID[263]:ARMREG6 */ + [252] = {0xFD442450U, 0x00000000U}, /* RGIDW_MODID[264]:ARMREG7 */ + [253] = {0xFD442454U, 0x0000000CU}, /* RGIDW_MODID[265]:ARMREG8 */ + [254] = {0xFD442458U, 0x0000000CU}, /* RGIDW_MODID[266]:ARMREG9 */ + [255] = {0xFD44245CU, 0x00000022U}, /* RGIDW_MODID[267]:ARRD0 */ + /* After setting */ /* RGIDW_MODID[268]:ARRD1 */ + /* After setting */ /* RGIDW_MODID[269]:ARRD2 */ + [256] = {0xFD442468U, 0x00000011U}, /* RGIDW_MODID[270]:ARRD3 */ + [257] = {0xFD44246CU, 0x00000022U}, /* RGIDW_MODID[271]:ARRD4 */ + [258] = {0xFD442470U, 0x00000011U}, /* RGIDW_MODID[272]:ARRD5 */ + [259] = {0xFD442474U, 0x00000022U}, /* RGIDW_MODID[273]:ARRD6 */ + [260] = {0xFD442478U, 0x00000022U}, /* RGIDW_MODID[274]:ARRD7 */ + [261] = {0xFD44247CU, 0x00000000U}, /* RGIDW_MODID[275]:ARRD8 */ + [262] = {0xFD442480U, 0x00000022U}, /* RGIDW_MODID[276]:ARRT0 */ + /* After setting */ /* RGIDW_MODID[277]:ARRT1 */ + /* After setting */ /* RGIDW_MODID[278]:ARRT2 */ + [263] = {0xFD44248CU, 0x00000011U}, /* RGIDW_MODID[279]:ARRT3 */ + [264] = {0xFD442490U, 0x00000022U}, /* RGIDW_MODID[280]:ARRT4 */ + [265] = {0xFD442494U, 0x00000011U}, /* RGIDW_MODID[281]:ARRT5 */ + [266] = {0xFD442498U, 0x00000022U}, /* RGIDW_MODID[282]:ARRT6 */ + [267] = {0xFD44249CU, 0x00000022U}, /* RGIDW_MODID[283]:ARRT7 */ + [268] = {0xFD4424A0U, 0x00000000U}, /* RGIDW_MODID[284]:ARRT8 */ + [269] = {0xFD4424A4U, 0x0000002AU}, /* RGIDW_MODID[285]:CKMRT */ + [270] = {0xFD4424A8U, 0x0000002EU}, /* RGIDW_MODID[286]:CRC0 */ + [271] = {0xFD4424ACU, 0x0000002EU}, /* RGIDW_MODID[287]:CRC1 */ + [272] = {0xFD4424B0U, 0x0000002EU}, /* RGIDW_MODID[288]:CRC2 */ + [273] = {0xFD4424B4U, 0x0000002EU}, /* RGIDW_MODID[289]:CRC3 */ + [274] = {0xFD4424B8U, 0x0000002EU}, /* RGIDW_MODID[290]:CSD */ + [275] = {0xFD4424BCU, 0x0000003BU}, /* RGIDW_MODID[291]:ECM */ + [276] = {0xFD4424C0U, 0x0000003BU}, /* RGIDW_MODID[292]:ECMRT */ + [277] = {0xFD4424C4U, 0x0000002EU}, /* RGIDW_MODID[293]:FBACR52 */ + [278] = {0xFD4424C8U, 0x0000002EU}, /* RGIDW_MODID[294]:FBART */ + [279] = {0xFD4424CCU, 0x0000002EU}, /* RGIDW_MODID[295]:INTTP */ + [280] = {0xFD4424D0U, 0x0000000CU}, /* RGIDW_MODID[296]:IPMMURT000 */ + [281] = {0xFD4424D4U, 0x0000000CU}, /* RGIDW_MODID[297]:IPMMURT100 */ + [282] = {0xFD4424D8U, 0x0000002EU}, /* RGIDW_MODID[298]:KCRC4 */ + [283] = {0xFD4424DCU, 0x0000002EU}, /* RGIDW_MODID[299]:KCRC5 */ + [284] = {0xFD4424E0U, 0x0000002EU}, /* RGIDW_MODID[300]:KCRC6 */ + [285] = {0xFD4424E4U, 0x0000002EU}, /* RGIDW_MODID[301]:KCRC7 */ + [286] = {0xFD4424E8U, 0x0000003FU}, /* RGIDW_MODID[302]:MFI00 */ + [287] = {0xFD4424ECU, 0x0000002EU}, /* RGIDW_MODID[303]:MFI01 */ + [288] = {0xFD4424F0U, 0x0000002EU}, /* RGIDW_MODID[304]:MFI10 */ + [289] = {0xFD4424F4U, 0x0000002EU}, /* RGIDW_MODID[305]:MFI02 */ + [290] = {0xFD4424F8U, 0x0000002EU}, /* RGIDW_MODID[306]:MFI03 */ + [291] = {0xFD4424FCU, 0x0000002EU}, /* RGIDW_MODID[307]:MFI04 */ + [292] = {0xFD442500U, 0x00000000U}, /* RGIDW_MODID[308]:MFI05 */ + [293] = {0xFD442504U, 0x00000000U}, /* RGIDW_MODID[309]:MFI06 */ + [294] = {0xFD442508U, 0x00000000U}, /* RGIDW_MODID[310]:MFI07 */ + [295] = {0xFD44250CU, 0x00000000U}, /* RGIDW_MODID[311]:MFI08 */ + [296] = {0xFD442510U, 0x0000002EU}, /* RGIDW_MODID[312]:MFI09 */ + [297] = {0xFD442514U, 0x0000003FU}, /* RGIDW_MODID[313]:MFI15 */ + [298] = {0xFD442518U, 0x0000002AU}, /* RGIDW_MODID[314]:CKMCR52 */ + [299] = {0xFD44251CU, 0x0000003BU}, /* RGIDW_MODID[315]:RTDM0P */ + [300] = {0xFD442520U, 0x0000003BU}, /* RGIDW_MODID[316]:ECMRD */ + [301] = {0xFD442524U, 0x0000003BU}, /* RGIDW_MODID[317]:RTDM1P */ + [302] = {0xFD44252CU, 0x0000003BU}, /* RGIDW_MODID[318]:RTDM2P */ + [303] = {0xFD442530U, 0x0000003BU}, /* RGIDW_MODID[319]:SYSRAM10 */ + [304] = {0xFD442534U, 0x0000003BU}, /* RGIDW_MODID[320]:RTDM3P */ + [305] = {0xFD442538U, 0x00000003U}, /* RGIDW_MODID[321]:SYSRAM00 */ + [306] = {0xFD44253CU, 0x0000002EU}, /* RGIDW_MODID[322]:TSIPL0 */ + [307] = {0xFD442540U, 0x0000002EU}, /* RGIDW_MODID[323]:TSIPL1 */ + [308] = {0xFD442544U, 0x0000002EU}, /* RGIDW_MODID[324]:TSIPL2 */ + [309] = {0xFD442548U, 0x0000002EU}, /* RGIDW_MODID[325]:TSIPL3 */ + [310] = {0xFD44254CU, 0x0000002EU}, /* RGIDW_MODID[326]:TSIPL4 */ + [311] = {0xFD442550U, 0x0000002EU}, /* RGIDW_MODID[327]:TSIPL5 */ + [312] = {0xFD442554U, 0x0000002EU}, /* RGIDW_MODID[328]:TSIPL6 */ + [313] = {0xFD442558U, 0x0000002EU}, /* RGIDW_MODID[329]:TSIPL7 */ + [314] = {0xFD44255CU, 0x0000002EU}, /* RGIDW_MODID[330]:WCRC0 */ + [315] = {0xFD442560U, 0x0000002EU}, /* RGIDW_MODID[331]:WCRC1 */ + [316] = {0xFD442564U, 0x0000002EU}, /* RGIDW_MODID[332]:WCRC2 */ + [317] = {0xFD442568U, 0x0000002EU}, /* RGIDW_MODID[333]:WCRC3 */ + [318] = {0xFD442574U, 0x0000000CU}, /* RGIDW_MODID[334]:TSIP0 */ + [319] = {0xFD442578U, 0x0000000CU}, /* RGIDW_MODID[335]:TSIP1 */ + [320] = {0xFD44257CU, 0x0000000CU}, /* RGIDW_MODID[336]:TSIP2 */ + [321] = {0xFD442580U, 0x0000002EU}, /* RGIDW_MODID[337]:MFI11 */ + [322] = {0xFD442584U, 0x00000000U}, /* RGIDW_MODID[338]:MFI12 */ + [323] = {0xFD442588U, 0x00000000U}, /* RGIDW_MODID[339]:MFI13 */ + [324] = {0xFD44258CU, 0x00000000U}, /* RGIDW_MODID[340]:MFI14 */ + [325] = {0xFD442590U, 0x0000000CU}, /* RGIDW_MODID[341]:IPMMURT001 */ + [326] = {0xFD442594U, 0x0000000CU}, /* RGIDW_MODID[342]:IPMMURT010 */ + [327] = {0xFD442598U, 0x0000000CU}, /* RGIDW_MODID[343]:IPMMURT011 */ + [328] = {0xFD44259CU, 0x0000000CU}, /* RGIDW_MODID[344]:IPMMURT012 */ + [329] = {0xFD4425A0U, 0x0000000CU}, /* RGIDW_MODID[345]:IPMMURT013 */ + [330] = {0xFD4425A4U, 0x0000000CU}, /* RGIDW_MODID[346]:IPMMURT014 */ + [331] = {0xFD4425A8U, 0x0000000CU}, /* RGIDW_MODID[347]:IPMMURT015 */ + [332] = {0xFD4425ACU, 0x0000000CU}, /* RGIDW_MODID[348]:IPMMURT002 */ + [333] = {0xFD4425B0U, 0x0000000CU}, /* RGIDW_MODID[349]:IPMMURT003 */ + [334] = {0xFD4425B4U, 0x0000000CU}, /* RGIDW_MODID[350]:IPMMURT004 */ + [335] = {0xFD4425B8U, 0x0000000CU}, /* RGIDW_MODID[351]:IPMMURT005 */ + [336] = {0xFD4425BCU, 0x0000000CU}, /* RGIDW_MODID[352]:IPMMURT006 */ + [337] = {0xFD4425C0U, 0x0000000CU}, /* RGIDW_MODID[353]:IPMMURT007 */ + [338] = {0xFD4425C4U, 0x0000000CU}, /* RGIDW_MODID[354]:IPMMURT008 */ + [339] = {0xFD4425C8U, 0x0000000CU}, /* RGIDW_MODID[355]:IPMMURT009 */ + [340] = {0xFD4425CCU, 0x0000000CU}, /* RGIDW_MODID[356]:IPMMURT101 */ + [341] = {0xFD4425D0U, 0x0000000CU}, /* RGIDW_MODID[357]:IPMMURT110 */ + [342] = {0xFD4425D4U, 0x0000000CU}, /* RGIDW_MODID[358]:IPMMURT111 */ + [343] = {0xFD4425D8U, 0x0000000CU}, /* RGIDW_MODID[359]:IPMMURT112 */ + [344] = {0xFD4425DCU, 0x0000000CU}, /* RGIDW_MODID[360]:IPMMURT113 */ + [345] = {0xFD4425E0U, 0x0000000CU}, /* RGIDW_MODID[361]:IPMMURT114 */ + [346] = {0xFD4425E4U, 0x0000000CU}, /* RGIDW_MODID[362]:IPMMURT115 */ + [347] = {0xFD4425E8U, 0x0000000CU}, /* RGIDW_MODID[363]:IPMMURT102 */ + [348] = {0xFD4425ECU, 0x0000000CU}, /* RGIDW_MODID[364]:IPMMURT103 */ + [349] = {0xFD4425F0U, 0x0000000CU}, /* RGIDW_MODID[365]:IPMMURT104 */ + [350] = {0xFD4425F4U, 0x0000000CU}, /* RGIDW_MODID[366]:IPMMURT105 */ + [351] = {0xFD4425F8U, 0x0000000CU}, /* RGIDW_MODID[367]:IPMMURT106 */ + [352] = {0xFD4425FCU, 0x0000000CU}, /* RGIDW_MODID[368]:IPMMURT107 */ + [353] = {0xFD442600U, 0x0000003BU}, /* RGIDW_MODID[369]:RTDM000 */ + [354] = {0xFD442604U, 0x0000003BU}, /* RGIDW_MODID[370]:RTDM001 */ + [355] = {0xFD442608U, 0x0000003BU}, /* RGIDW_MODID[371]:RTDM010 */ + [356] = {0xFD44260CU, 0x0000003BU}, /* RGIDW_MODID[372]:RTDM011 */ + [357] = {0xFD442610U, 0x0000003BU}, /* RGIDW_MODID[373]:RTDM012 */ + [358] = {0xFD442614U, 0x0000003BU}, /* RGIDW_MODID[374]:RTDM013 */ + [359] = {0xFD442618U, 0x0000003BU}, /* RGIDW_MODID[375]:RTDM014 */ + [360] = {0xFD44261CU, 0x0000003BU}, /* RGIDW_MODID[376]:RTDM015 */ + [361] = {0xFD442620U, 0x0000003BU}, /* RGIDW_MODID[377]:RTDM002 */ + [362] = {0xFD442624U, 0x0000003BU}, /* RGIDW_MODID[378]:RTDM003 */ + [363] = {0xFD442628U, 0x0000003BU}, /* RGIDW_MODID[379]:RTDM004 */ + [364] = {0xFD44262CU, 0x0000003BU}, /* RGIDW_MODID[380]:RTDM005 */ + [365] = {0xFD442630U, 0x0000003BU}, /* RGIDW_MODID[381]:RTDM006 */ + [366] = {0xFD442634U, 0x0000003BU}, /* RGIDW_MODID[382]:RTDM007 */ + [367] = {0xFD442638U, 0x0000003BU}, /* RGIDW_MODID[383]:RTDM008 */ + [368] = {0xFD44263CU, 0x0000003BU}, /* RGIDW_MODID[384]:RTDM009 */ + [369] = {0xFD442640U, 0x0000003BU}, /* RGIDW_MODID[385]:RTDM100 */ + [370] = {0xFD442644U, 0x0000003BU}, /* RGIDW_MODID[386]:RTDM101 */ + [371] = {0xFD442648U, 0x0000003BU}, /* RGIDW_MODID[387]:RTDM110 */ + [372] = {0xFD44264CU, 0x0000003BU}, /* RGIDW_MODID[388]:RTDM111 */ + [373] = {0xFD442650U, 0x0000003BU}, /* RGIDW_MODID[389]:RTDM112 */ + [374] = {0xFD442654U, 0x0000003BU}, /* RGIDW_MODID[390]:RTDM113 */ + [375] = {0xFD442658U, 0x0000003BU}, /* RGIDW_MODID[391]:RTDM114 */ + [376] = {0xFD44265CU, 0x0000003BU}, /* RGIDW_MODID[392]:RTDM115 */ + [377] = {0xFD442660U, 0x0000003BU}, /* RGIDW_MODID[393]:RTDM102 */ + [378] = {0xFD442664U, 0x0000003BU}, /* RGIDW_MODID[394]:RTDM103 */ + [379] = {0xFD442668U, 0x0000003BU}, /* RGIDW_MODID[395]:RTDM104 */ + [380] = {0xFD44266CU, 0x0000003BU}, /* RGIDW_MODID[396]:RTDM105 */ + [381] = {0xFD442670U, 0x0000003BU}, /* RGIDW_MODID[397]:RTDM106 */ + [382] = {0xFD442674U, 0x0000003BU}, /* RGIDW_MODID[398]:RTDM107 */ + [383] = {0xFD442678U, 0x0000003BU}, /* RGIDW_MODID[399]:RTDM108 */ + [384] = {0xFD44267CU, 0x0000003BU}, /* RGIDW_MODID[400]:RTDM109 */ + [385] = {0xFD442680U, 0x0000003BU}, /* RGIDW_MODID[401]:RTDM200 */ + [386] = {0xFD442684U, 0x0000003BU}, /* RGIDW_MODID[402]:RTDM201 */ + [387] = {0xFD442688U, 0x0000003BU}, /* RGIDW_MODID[403]:RTDM210 */ + [388] = {0xFD44268CU, 0x0000003BU}, /* RGIDW_MODID[404]:RTDM211 */ + [389] = {0xFD442690U, 0x0000003BU}, /* RGIDW_MODID[405]:RTDM212 */ + [390] = {0xFD442694U, 0x0000003BU}, /* RGIDW_MODID[406]:RTDM213 */ + [391] = {0xFD442698U, 0x0000003BU}, /* RGIDW_MODID[407]:RTDM214 */ + [392] = {0xFD44269CU, 0x0000003BU}, /* RGIDW_MODID[408]:RTDM215 */ + [393] = {0xFD4426A0U, 0x0000003BU}, /* RGIDW_MODID[409]:RTDM202 */ + [394] = {0xFD4426A4U, 0x0000003BU}, /* RGIDW_MODID[410]:RTDM203 */ + [395] = {0xFD4426A8U, 0x0000003BU}, /* RGIDW_MODID[411]:RTDM204 */ + [396] = {0xFD4426ACU, 0x0000003BU}, /* RGIDW_MODID[412]:RTDM205 */ + [397] = {0xFD4426B0U, 0x0000003BU}, /* RGIDW_MODID[413]:RTDM206 */ + [398] = {0xFD4426B4U, 0x0000003BU}, /* RGIDW_MODID[414]:RTDM207 */ + [399] = {0xFD4426B8U, 0x0000003BU}, /* RGIDW_MODID[415]:RTDM208 */ + [400] = {0xFD4426BCU, 0x0000003BU}, /* RGIDW_MODID[416]:RTDM209 */ + [401] = {0xFD4426C0U, 0x0000003BU}, /* RGIDW_MODID[417]:RTDM300 */ + [402] = {0xFD4426C4U, 0x0000003BU}, /* RGIDW_MODID[418]:RTDM301 */ + [403] = {0xFD4426C8U, 0x0000003BU}, /* RGIDW_MODID[419]:RTDM310 */ + [404] = {0xFD4426CCU, 0x0000003BU}, /* RGIDW_MODID[420]:RTDM311 */ + [405] = {0xFD4426D0U, 0x0000003BU}, /* RGIDW_MODID[421]:RTDM312 */ + [406] = {0xFD4426D4U, 0x0000003BU}, /* RGIDW_MODID[422]:RTDM313 */ + [407] = {0xFD4426D8U, 0x0000003BU}, /* RGIDW_MODID[423]:RTDM314 */ + [408] = {0xFD4426DCU, 0x0000003BU}, /* RGIDW_MODID[424]:RTDM315 */ + [409] = {0xFD4426E0U, 0x0000003BU}, /* RGIDW_MODID[425]:RTDM302 */ + [410] = {0xFD4426E4U, 0x0000003BU}, /* RGIDW_MODID[426]:RTDM303 */ + [411] = {0xFD4426E8U, 0x0000003BU}, /* RGIDW_MODID[427]:RTDM304 */ + [412] = {0xFD4426ECU, 0x0000003BU}, /* RGIDW_MODID[428]:RTDM305 */ + [413] = {0xFD4426F0U, 0x0000003BU}, /* RGIDW_MODID[429]:RTDM306 */ + [414] = {0xFD4426F4U, 0x0000003BU}, /* RGIDW_MODID[430]:RTDM307 */ + [415] = {0xFD4426F8U, 0x0000003BU}, /* RGIDW_MODID[431]:RTDM308 */ + [416] = {0xFD4426FCU, 0x0000003BU}, /* RGIDW_MODID[432]:RTDM309 */ + [417] = {0xFD442700U, 0x0000000CU}, /* RGIDW_MODID[433]:IPMMURT108 */ + [418] = {0xFD442704U, 0x0000000CU}, /* RGIDW_MODID[434]:IPMMURT109 */ + [419] = {0xFD442708U, 0x00000011U}, /* RGIDW_MODID[435]:SYSRAM01 */ + [420] = {0xFD44270CU, 0x0000003BU}, /* RGIDW_MODID[436]:SYSRAM02 */ + [421] = {0xFD442710U, 0x00000011U}, /* RGIDW_MODID[437]:SYSRAM03 */ + [422] = {0xFD442714U, 0x00000011U}, /* RGIDW_MODID[438]:SYSRAM04 */ + [423] = {0xFD442718U, 0x00000011U}, /* RGIDW_MODID[439]:SYSRAM05 */ + [424] = {0xFD44271CU, 0x00000011U}, /* RGIDW_MODID[440]:SYSRAM06 */ + [425] = {0xFD442720U, 0x00000000U}, /* RGIDW_MODID[441]:SYSRAM07 */ + [426] = {0xFD442724U, 0x0000003BU}, /* RGIDW_MODID[442]:SYSRAM11 */ + [427] = {0xFD442728U, 0x0000002AU}, /* RGIDW_MODID[443]:SYSRAM12 */ + [428] = {0xFD44272CU, 0x0000003BU}, /* RGIDW_MODID[444]:SYSRAM13 */ + [429] = {0xFD442730U, 0x0000003BU}, /* RGIDW_MODID[445]:SYSRAM14 */ + [430] = {0xFD442734U, 0x0000003BU}, /* RGIDW_MODID[446]:SYSRAM15 */ + [431] = {0xFD442738U, 0x0000003BU}, /* RGIDW_MODID[447]:SYSRAM16 */ + [432] = {0xFD44273CU, 0x00000000U}, /* RGIDW_MODID[448]:SYSRAM17 */ + [433] = {0xFD442760U, 0x00000022U}, /* RGIDW_MODID[449]:BKBUF */ + [434] = {0xFD44276CU, 0x0000003FU}, /* RGIDW_MODID[450]:MCU */ + [435] = {0xFF862400U, 0x00000022U}, /* RGIDW_MODID[451]:ARSC0 */ + /* After setting */ /* RGIDW_MODID[452]:ARSC1 */ + /* After setting */ /* RGIDW_MODID[453]:ARSC2 */ + [436] = {0xFF86240CU, 0x00000011U}, /* RGIDW_MODID[454]:ARSC3 */ + [437] = {0xFF862410U, 0x00000022U}, /* RGIDW_MODID[455]:ARSC4 */ + [438] = {0xFF862414U, 0x00000011U}, /* RGIDW_MODID[456]:ARSC5 */ + [439] = {0xFF862418U, 0x00000022U}, /* RGIDW_MODID[457]:ARSC6 */ + [440] = {0xFF86241CU, 0x00000022U}, /* RGIDW_MODID[458]:ARSC7 */ + [441] = {0xFF862420U, 0x00000000U}, /* RGIDW_MODID[459]:ARSC8 */ + [442] = {0xFF862424U, 0x00000022U}, /* RGIDW_MODID[460]:ARSTM0 */ + /* After setting */ /* RGIDW_MODID[461]:ARSTM1 */ + [443] = {0xFF862430U, 0x0000002EU}, /* RGIDW_MODID[462]:AXIFBABUSTOP0 */ + [444] = {0xFF862434U, 0x0000002EU}, /* RGIDW_MODID[463]:AXIFBABUSTOP1 */ + /* After setting */ /* RGIDW_MODID[464]:ARSTM2 */ + [445] = {0xFF86243CU, 0x00000011U}, /* RGIDW_MODID[465]:ARSTM3 */ + [446] = {0xFF862440U, 0x00000022U}, /* RGIDW_MODID[466]:ARSTM4 */ + [447] = {0xFF862444U, 0x00000011U}, /* RGIDW_MODID[467]:ARSTM5 */ + [448] = {0xFF862448U, 0x00000022U}, /* RGIDW_MODID[468]:ARSTM6 */ + [449] = {0xFF86244CU, 0x00000022U}, /* RGIDW_MODID[469]:ARSTM7 */ + [450] = {0xFF862450U, 0x00000000U}, /* RGIDW_MODID[470]:ARSTM8 */ + [451] = {0xFF862454U, 0x0000003BU}, /* RGIDW_MODID[471]:ECMTOP */ + [452] = {0xFF862458U, 0x0000002EU}, /* RGIDW_MODID[472]:FBA */ + [453] = {0xFF86245CU, 0x0000002EU}, /* RGIDW_MODID[473]:FBC */ + [454] = {0xFF862460U, 0x0000000CU}, /* RGIDW_MODID[474]:AXICCI00 */ + [455] = {0xFF862464U, 0x0000000CU}, /* RGIDW_MODID[475]:AXICCI01 */ + [456] = {0xFF862468U, 0x0000000CU}, /* RGIDW_MODID[476]:AXICCI10 */ + [457] = {0xFF86246CU, 0x0000000CU}, /* RGIDW_MODID[477]:AXICCI11 */ + [458] = {0xFF862470U, 0x0000000CU}, /* RGIDW_MODID[478]:AXICCI12 */ + [459] = {0xFF862474U, 0x0000000CU}, /* RGIDW_MODID[479]:AXICCI13 */ + [460] = {0xFF862478U, 0x0000000CU}, /* RGIDW_MODID[480]:AXICCI14 */ + [461] = {0xFF86247CU, 0x0000000CU}, /* RGIDW_MODID[481]:AXICCI15 */ + [462] = {0xFF862480U, 0x0000000CU}, /* RGIDW_MODID[482]:AXICCI2 */ + [463] = {0xFF862484U, 0x0000000CU}, /* RGIDW_MODID[483]:AXICCI3 */ + [464] = {0xFF862488U, 0x0000000CU}, /* RGIDW_MODID[484]:AXICCI4 */ + [465] = {0xFF86248CU, 0x0000000CU}, /* RGIDW_MODID[485]:AXICCI5 */ + [466] = {0xFF862490U, 0x0000000CU}, /* RGIDW_MODID[486]:AXICCI6 */ + [467] = {0xFF862494U, 0x0000000CU}, /* RGIDW_MODID[487]:AXICCI7 */ + [468] = {0xFF862498U, 0x0000000CU}, /* RGIDW_MODID[488]:AXICCI8 */ + [469] = {0xFF86249CU, 0x0000003BU}, /* RGIDW_MODID[489]:AXICCI9 */ + [470] = {0xFF8624A0U, 0x0000003FU}, /* RGIDW_MODID[490]:ECMSTM */ + [471] = {0xFCB82414U, 0x0000002EU}, /* RGIDW_MODID[491]:DMAI2C0 */ + [472] = {0xFCB82418U, 0x0000002EU}, /* RGIDW_MODID[492]:DMAI2C1 */ + [473] = {0xFCB8241CU, 0x0000002EU}, /* RGIDW_MODID[493]:DMAI2C2 */ + [474] = {0xFCB82420U, 0x0000002EU}, /* RGIDW_MODID[494]:DMAI2C3 */ + [475] = {0xFCB82424U, 0x0000002EU}, /* RGIDW_MODID[495]:DMAI2C4 */ + [476] = {0xFCB82428U, 0x0000002EU}, /* RGIDW_MODID[496]:DMAI2C5 */ + [477] = {0xFDDC2400U, 0x00000000U}, /* RGIDW_MODID[497]:ARMM */ + /* After setting */ /* RGIDW_MODID[498]:AXIARNMM */ + [478] = {0xFDDC2408U, 0x00000022U}, /* RGIDW_MODID[499]:ARSM0 */ + /* After setting */ /* RGIDW_MODID[500]:ARSM1 */ + /* After setting */ /* RGIDW_MODID[501]:ARSM2 */ + [479] = {0xFDDC2414U, 0x0000003FU}, /* RGIDW_MODID[502]:AXIQOS0 */ + [480] = {0xFDDC2418U, 0x0000003FU}, /* RGIDW_MODID[503]:AXIQOS1 */ + [481] = {0xFDDC241CU, 0x0000003FU}, /* RGIDW_MODID[504]:AXIQOS2 */ + [482] = {0xFDDC2420U, 0x0000003FU}, /* RGIDW_MODID[505]:AXIQOS3 */ + [483] = {0xFDDC2424U, 0x0000003FU}, /* RGIDW_MODID[506]:AXIQOS4 */ + [484] = {0xFDDC2430U, 0x0000003FU}, /* RGIDW_MODID[507]:AXIQOS5 */ + [485] = {0xFDDC2434U, 0x00000011U}, /* RGIDW_MODID[508]:ARSM3 */ + [486] = {0xFDDC2438U, 0x00000022U}, /* RGIDW_MODID[509]:ARSM4 */ + [487] = {0xFDDC243CU, 0x00000011U}, /* RGIDW_MODID[510]:ARSM5 */ + [488] = {0xFDDC2440U, 0x00000022U}, /* RGIDW_MODID[511]:ARSM6 */ + [489] = {0xFDDC2444U, 0x00000022U}, /* RGIDW_MODID[512]:ARSM7 */ + [490] = {0xFDDC2448U, 0x00000000U}, /* RGIDW_MODID[513]:ARSM8 */ + [491] = {0xFDDC244CU, 0x0000003FU}, /* RGIDW_MODID[514]:AXMM0 */ + [492] = {0xFDDC2450U, 0x0000003FU}, /* RGIDW_MODID[515]:AXMM1 */ + [493] = {0xFDDC2454U, 0x00000000U}, /* RGIDW_MODID[516]:AXMMPMON */ + [494] = {0xFDDC2458U, 0x0000002AU}, /* RGIDW_MODID[517]:CKMMM */ + [495] = {0xFDDC245CU, 0x0000003BU}, /* RGIDW_MODID[518]:ECMMM */ + [496] = {0xFDDC2468U, 0x0000002EU}, /* RGIDW_MODID[519]:FBAMM */ + [497] = {0xFDDC246CU, 0x0000000CU}, /* RGIDW_MODID[520]:IPMMUMM00 */ + [498] = {0xFDDC2470U, 0x0000003FU}, /* RGIDW_MODID[521]:DBS00 */ + [499] = {0xFDDC2474U, 0x0000002AU}, /* RGIDW_MODID[522]:DBS01 */ + [500] = {0xFDDC2480U, 0x0000003FU}, /* RGIDW_MODID[523]:AXCIDBS */ + [501] = {0xFDDC249CU, 0x0000000CU}, /* RGIDW_MODID[524]:IPMMUMM01 */ + [502] = {0xFDDC24A0U, 0x0000000CU}, /* RGIDW_MODID[525]:IPMMUMM10 */ + [503] = {0xFDDC24A4U, 0x0000000CU}, /* RGIDW_MODID[526]:IPMMUMM11 */ + [504] = {0xFDDC24A8U, 0x0000000CU}, /* RGIDW_MODID[527]:IPMMUMM12 */ + [505] = {0xFDDC24ACU, 0x0000000CU}, /* RGIDW_MODID[528]:IPMMUMM13 */ + [506] = {0xFDDC24B0U, 0x0000000CU}, /* RGIDW_MODID[529]:IPMMUMM14 */ + [507] = {0xFDDC24B4U, 0x0000000CU}, /* RGIDW_MODID[530]:IPMMUMM15 */ + [508] = {0xFDDC24B8U, 0x0000000CU}, /* RGIDW_MODID[531]:IPMMUMM02 */ + [509] = {0xFDDC24BCU, 0x0000000CU}, /* RGIDW_MODID[532]:IPMMUMM03 */ + [510] = {0xFDDC24C0U, 0x0000000CU}, /* RGIDW_MODID[533]:IPMMUMM04 */ + [511] = {0xFDDC24C4U, 0x0000000CU}, /* RGIDW_MODID[534]:IPMMUMM05 */ + [512] = {0xFDDC24C8U, 0x0000000CU}, /* RGIDW_MODID[535]:IPMMUMM06 */ + [513] = {0xFDDC24CCU, 0x0000000CU}, /* RGIDW_MODID[536]:IPMMUMM07 */ + [514] = {0xFDDC24D0U, 0x0000000CU}, /* RGIDW_MODID[537]:IPMMUMM08 */ + [515] = {0xFDDC24D4U, 0x0000000CU}, /* RGIDW_MODID[538]:IPMMUMM09 */ + [516] = {0xFCB52400U, 0x00000022U}, /* RGIDW_MODID[539]:ARSD00 */ + /* After setting */ /* RGIDW_MODID[540]:ARSD01 */ + /* After setting */ /* RGIDW_MODID[541]:ARSD02 */ + [517] = {0xFCB5240CU, 0x00000011U}, /* RGIDW_MODID[542]:ARSD03 */ + [518] = {0xFCB52410U, 0x00000022U}, /* RGIDW_MODID[543]:ARSD04 */ + [519] = {0xFCB52414U, 0x00000011U}, /* RGIDW_MODID[544]:ARSD05 */ + [520] = {0xFCB52418U, 0x00000022U}, /* RGIDW_MODID[545]:ARSD06 */ + [521] = {0xFCB52428U, 0x0000003FU}, /* RGIDW_MODID[546]:AXIRPC */ + [522] = {0xFCB5242CU, 0x0000003FU}, /* RGIDW_MODID[547]:AXISDHI0 */ + [523] = {0xFCB52430U, 0x00000022U}, /* RGIDW_MODID[548]:ARSD07 */ + [524] = {0xFCB52434U, 0x00000000U}, /* RGIDW_MODID[549]:ARSD07 */ + [525] = {0xFCB52438U, 0x00000022U}, /* RGIDW_MODID[550]:ARSP00 */ + /* After setting */ /* RGIDW_MODID[551]:ARSP01 */ + /* After setting */ /* RGIDW_MODID[552]:ARSP02 */ + [526] = {0xFCB52444U, 0x00000011U}, /* RGIDW_MODID[553]:ARSP03 */ + [527] = {0xFCB52448U, 0x00000022U}, /* RGIDW_MODID[554]:ARSP04 */ + [528] = {0xFCB5244CU, 0x00000011U}, /* RGIDW_MODID[555]:ARSP05 */ + [529] = {0xFCB52450U, 0x00000022U}, /* RGIDW_MODID[556]:ARSP06 */ + [530] = {0xFCB52454U, 0x00000022U}, /* RGIDW_MODID[557]:ARSP07 */ + [531] = {0xFCB52458U, 0x00000000U}, /* RGIDW_MODID[558]:ARSP08 */ + [532] = {0xFCB5245CU, 0x0000000CU}, /* RGIDW_MODID[559]:IPMMUDS001 */ + [533] = {0xFCB52460U, 0x0000002AU}, /* RGIDW_MODID[560]:CKMPER0 */ + [534] = {0xFCB52464U, 0x0000003BU}, /* RGIDW_MODID[561]:ECMPER0 */ + [535] = {0xFCB52468U, 0x0000002EU}, /* RGIDW_MODID[562]:FBAPER0 */ + [536] = {0xFCB5246CU, 0x0000002EU}, /* RGIDW_MODID[563]:FSO0 */ + [537] = {0xFCB52470U, 0x0000002EU}, /* RGIDW_MODID[564]:FSO1 */ + [538] = {0xFCB52474U, 0x0000002EU}, /* RGIDW_MODID[565]:FSO10 */ + [539] = {0xFCB52478U, 0x0000002EU}, /* RGIDW_MODID[566]:FSO2 */ + [540] = {0xFCB5247CU, 0x0000002EU}, /* RGIDW_MODID[567]:FSO3 */ + [541] = {0xFCB52480U, 0x0000002EU}, /* RGIDW_MODID[568]:FSO4 */ + [542] = {0xFCB52484U, 0x0000002EU}, /* RGIDW_MODID[569]:FSO5 */ + [543] = {0xFCB52488U, 0x0000002EU}, /* RGIDW_MODID[570]:FSO6 */ + [544] = {0xFCB5248CU, 0x0000002EU}, /* RGIDW_MODID[571]:FSO7 */ + [545] = {0xFCB52490U, 0x0000002EU}, /* RGIDW_MODID[572]:FSO8 */ + [546] = {0xFCB52494U, 0x0000002EU}, /* RGIDW_MODID[573]:FSO9 */ + [547] = {0xFCB5249CU, 0x0000003BU}, /* RGIDW_MODID[574]:ECMSD0 */ + [548] = {0xFCB524A0U, 0x0000000CU}, /* RGIDW_MODID[575]:IPMMUDS010 */ + [549] = {0xFCB524A4U, 0x0000000CU}, /* RGIDW_MODID[576]:IPMMUDS011 */ + [550] = {0xFCB524A8U, 0x0000002EU}, /* RGIDW_MODID[577]:I2C0 */ + [551] = {0xFCB524ACU, 0x0000002EU}, /* RGIDW_MODID[578]:I2C1 */ + [552] = {0xFCB524B0U, 0x0000002EU}, /* RGIDW_MODID[579]:I2C2 */ + [553] = {0xFCB524B4U, 0x0000002EU}, /* RGIDW_MODID[580]:I2C3 */ + [554] = {0xFCB524B8U, 0x0000002EU}, /* RGIDW_MODID[581]:I2C4 */ + [555] = {0xFCB524BCU, 0x0000002EU}, /* RGIDW_MODID[582]:I2C5 */ + [556] = {0xFCB524C0U, 0x0000000CU}, /* RGIDW_MODID[583]:IPMMUDS012 */ + [557] = {0xFCB524C8U, 0x0000000CU}, /* RGIDW_MODID[584]:IPMMUDS000 */ + [558] = {0xFCB524CCU, 0x0000000CU}, /* RGIDW_MODID[585]:IPMMUDS013 */ + [559] = {0xFCB524D0U, 0x0000000CU}, /* RGIDW_MODID[586]:IPMMUDS014 */ + [560] = {0xFCB524D4U, 0x0000000CU}, /* RGIDW_MODID[587]:IPMMUDS015 */ + [561] = {0xFCB524D8U, 0x0000000CU}, /* RGIDW_MODID[588]:IPMMUDS002 */ + [562] = {0xFCB524DCU, 0x0000000CU}, /* RGIDW_MODID[589]:IPMMUDS003 */ + [563] = {0xFCB524E0U, 0x0000000CU}, /* RGIDW_MODID[590]:IPMMUDS004 */ + [564] = {0xFCB524E4U, 0x0000000CU}, /* RGIDW_MODID[591]:IPMMUDS005 */ + [565] = {0xFCB524ECU, 0x0000000CU}, /* RGIDW_MODID[592]:IPMMUDS006 */ + [566] = {0xFCB524F0U, 0x0000000CU}, /* RGIDW_MODID[593]:IPMMUDS007 */ + [567] = {0xFCB524F4U, 0x0000000CU}, /* RGIDW_MODID[594]:SYDM1P */ + [568] = {0xFCB524F8U, 0x0000000CU}, /* RGIDW_MODID[595]:IPMMUDS008 */ + [569] = {0xFCB524FCU, 0x0000000CU}, /* RGIDW_MODID[596]:SYDM2P */ + [570] = {0xFCB52500U, 0x0000000CU}, /* RGIDW_MODID[597]:IPMMUDS009 */ + [571] = {0xFCB52640U, 0x0000000CU}, /* RGIDW_MODID[598]:SYDM100 */ + [572] = {0xFCB52644U, 0x0000000CU}, /* RGIDW_MODID[599]:SYDM101 */ + [573] = {0xFCB52648U, 0x0000000CU}, /* RGIDW_MODID[600]:SYDM110 */ + [574] = {0xFCB5264CU, 0x0000000CU}, /* RGIDW_MODID[601]:SYDM111 */ + [575] = {0xFCB52650U, 0x0000000CU}, /* RGIDW_MODID[602]:SYDM112 */ + [576] = {0xFCB52654U, 0x0000000CU}, /* RGIDW_MODID[603]:SYDM113 */ + [577] = {0xFCB52658U, 0x0000000CU}, /* RGIDW_MODID[604]:SYDM114 */ + [578] = {0xFCB5265CU, 0x0000000CU}, /* RGIDW_MODID[605]:SYDM115 */ + [579] = {0xFCB52660U, 0x0000000CU}, /* RGIDW_MODID[606]:SYDM102 */ + [580] = {0xFCB52664U, 0x0000000CU}, /* RGIDW_MODID[607]:SYDM103 */ + [581] = {0xFCB52668U, 0x0000000CU}, /* RGIDW_MODID[608]:SYDM104 */ + [582] = {0xFCB5266CU, 0x0000000CU}, /* RGIDW_MODID[609]:SYDM105 */ + [583] = {0xFCB52670U, 0x0000000CU}, /* RGIDW_MODID[610]:SYDM106 */ + [584] = {0xFCB52674U, 0x0000000CU}, /* RGIDW_MODID[611]:SYDM107 */ + [585] = {0xFCB52678U, 0x0000000CU}, /* RGIDW_MODID[612]:SYDM108 */ + [586] = {0xFCB5267CU, 0x0000000CU}, /* RGIDW_MODID[613]:SYDM109 */ + [587] = {0xFCB52680U, 0x0000000CU}, /* RGIDW_MODID[614]:SYDM200 */ + [588] = {0xFCB52684U, 0x0000000CU}, /* RGIDW_MODID[615]:SYDM201 */ + [589] = {0xFCB52688U, 0x0000000CU}, /* RGIDW_MODID[616]:SYDM210 */ + [590] = {0xFCB5268CU, 0x0000000CU}, /* RGIDW_MODID[617]:SYDM211 */ + [591] = {0xFCB52690U, 0x0000000CU}, /* RGIDW_MODID[618]:SYDM212 */ + [592] = {0xFCB52694U, 0x0000000CU}, /* RGIDW_MODID[619]:SYDM213 */ + [593] = {0xFCB52698U, 0x0000000CU}, /* RGIDW_MODID[620]:SYDM214 */ + [594] = {0xFCB5269CU, 0x0000000CU}, /* RGIDW_MODID[621]:SYDM215 */ + [595] = {0xFCB526A0U, 0x0000000CU}, /* RGIDW_MODID[622]:SYDM202 */ + [596] = {0xFCB526A4U, 0x0000000CU}, /* RGIDW_MODID[623]:SYDM203 */ + [597] = {0xFCB526A8U, 0x0000000CU}, /* RGIDW_MODID[624]:SYDM204 */ + [598] = {0xFCB526ACU, 0x0000000CU}, /* RGIDW_MODID[625]:SYDM205 */ + [599] = {0xFCB526B0U, 0x0000000CU}, /* RGIDW_MODID[626]:SYDM206 */ + [600] = {0xFCB526B4U, 0x0000000CU}, /* RGIDW_MODID[627]:SYDM207 */ + [601] = {0xFCB526B8U, 0x0000000CU}, /* RGIDW_MODID[628]:SYDM208 */ + [602] = {0xFCB526BCU, 0x0000000CU}, /* RGIDW_MODID[629]:SYDM209 */ + [604] = {0xFDDB969CU, 0x00000000U}, /* RGIDW_MODID[630]:ARCC */ + [603] = {0xFDDB96B0U, 0x00000000U}, /* RGIDW_MODID[631]:ARRTRAM */ + [605] = {0xFCB52424U, 0x00000000U}, /* RGIDW_MODID[632]:RSV0 */ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_sec_tbl" +const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[] = { + [0] = {0xFD483400U, 0x00000000U}, /* RGIDSEC_MODID[0]:ARMGC0 */ + [1] = {0xFD483404U, 0x00000002U}, /* RGIDSEC_MODID[1]:ARMGC1 */ + [2] = {0xFD483408U, 0x00000002U}, /* RGIDSEC_MODID[2]:ARMGC2 */ + [3] = {0xFD48340CU, 0x00000002U}, /* RGIDSEC_MODID[3]:ARRT00 */ + [4] = {0xFD483410U, 0x00000002U}, /* RGIDSEC_MODID[4]:ARRT01 */ + [5] = {0xFD483414U, 0x00000002U}, /* RGIDSEC_MODID[5]:ARRT02 */ + [6] = {0xFD483418U, 0x00000002U}, /* RGIDSEC_MODID[6]:ARRT03 */ + [7] = {0xFD48341CU, 0x00000002U}, /* RGIDSEC_MODID[7]:ARRT04 */ + [8] = {0xFD483420U, 0x00000002U}, /* RGIDSEC_MODID[8]:ARRT05 */ + [9] = {0xFD483424U, 0x00000002U}, /* RGIDSEC_MODID[9]:ARRT06 */ + [10] = {0xFD483428U, 0x00000002U}, /* RGIDSEC_MODID[10]:ARRT07 */ + [11] = {0xFD48342CU, 0x00000002U}, /* RGIDSEC_MODID[11]:ARRT08 */ + [12] = {0xFD483430U, 0x00000000U}, /* RGIDSEC_MODID[12]:LIFEC0 */ + [13] = {0xFD483434U, 0x00000002U}, /* RGIDSEC_MODID[13]:SWDT */ + [14] = {0xFD483438U, 0x00000002U}, /* RGIDSEC_MODID[14]:TMU0 */ + [15] = {0xFD48343CU, 0x00000002U}, /* RGIDSEC_MODID[15]:WDT */ + [16] = {0xFD483440U, 0x00000002U}, /* RGIDSEC_MODID[16]:WWDT0 */ + [17] = {0xFD483444U, 0x00000002U}, /* RGIDSEC_MODID[17]:WWDT1 */ + [18] = {0xFD483448U, 0x00000002U}, /* RGIDSEC_MODID[18]:WWDT2 */ + [19] = {0xFD48344CU, 0x00000002U}, /* RGIDSEC_MODID[19]:WWDT3 */ + [20] = {0xFD483450U, 0x00000002U}, /* RGIDSEC_MODID[20]:WWDT4 */ + [21] = {0xFD483454U, 0x00000002U}, /* RGIDSEC_MODID[21]:WWDT5 */ + [22] = {0xFD483458U, 0x00000002U}, /* RGIDSEC_MODID[22]:WWDT6 */ + [23] = {0xFD48345CU, 0x00000002U}, /* RGIDSEC_MODID[23]:WWDT7 */ + [24] = {0xFD483460U, 0x00000002U}, /* RGIDSEC_MODID[24]:WWDT8 */ + [25] = {0xFD483464U, 0x00000002U}, /* RGIDSEC_MODID[25]:WWDT9 */ + [26] = {0xFD483468U, 0x00000002U}, /* RGIDSEC_MODID[26]:ECMRT3 */ + [27] = {0xFDA03400U, 0x00000002U}, /* RGIDSEC_MODID[27]:ADVFSC */ + [28] = {0xFDA03404U, 0x00000002U}, /* RGIDSEC_MODID[28]:APMU0 */ + [29] = {0xFDA03408U, 0x00000002U}, /* RGIDSEC_MODID[29]:APMU1 */ + [30] = {0xFDA0340CU, 0x00000002U}, /* RGIDSEC_MODID[30]:APMU10 */ + [31] = {0xFDA03410U, 0x00000002U}, /* RGIDSEC_MODID[31]:APMU11 */ + [32] = {0xFDA03414U, 0x00000002U}, /* RGIDSEC_MODID[32]:APMU12 */ + [33] = {0xFDA03418U, 0x00000002U}, /* RGIDSEC_MODID[33]:APMU13 */ + [34] = {0xFDA0341CU, 0x00000002U}, /* RGIDSEC_MODID[34]:APMU14 */ + [35] = {0xFDA03420U, 0x00000002U}, /* RGIDSEC_MODID[35]:APMU15 */ + [36] = {0xFDA03424U, 0x00000002U}, /* RGIDSEC_MODID[36]:APMU2 */ + [37] = {0xFDA03428U, 0x00000002U}, /* RGIDSEC_MODID[37]:APMU3 */ + [38] = {0xFDA0342CU, 0x00000002U}, /* RGIDSEC_MODID[38]:APMU4 */ + [39] = {0xFDA03430U, 0x00000002U}, /* RGIDSEC_MODID[39]:APMU5 */ + [40] = {0xFDA03434U, 0x00000002U}, /* RGIDSEC_MODID[40]:APMU6 */ + [41] = {0xFDA03438U, 0x00000002U}, /* RGIDSEC_MODID[41]:APMU7 */ + [42] = {0xFDA0343CU, 0x00000002U}, /* RGIDSEC_MODID[42]:APMU8 */ + [43] = {0xFDA03440U, 0x00000002U}, /* RGIDSEC_MODID[43]:APMU9 */ + [44] = {0xFDA03444U, 0x00000002U}, /* RGIDSEC_MODID[44]:ARS00 */ + [45] = {0xFDA03448U, 0x00000002U}, /* RGIDSEC_MODID[45]:ARS01 */ + [46] = {0xFDA0344CU, 0x00000002U}, /* RGIDSEC_MODID[46]:ARS02 */ + [47] = {0xFDA03450U, 0x00000002U}, /* RGIDSEC_MODID[47]:ARS03 */ + [48] = {0xFDA03454U, 0x00000002U}, /* RGIDSEC_MODID[48]:ARS04 */ + [49] = {0xFDA03458U, 0x00000002U}, /* RGIDSEC_MODID[49]:ARS05 */ + [50] = {0xFDA0345CU, 0x00000002U}, /* RGIDSEC_MODID[50]:ARS06 */ + [51] = {0xFDA03460U, 0x00000002U}, /* RGIDSEC_MODID[51]:ARS07 */ + [52] = {0xFDA03464U, 0x00000002U}, /* RGIDSEC_MODID[52]:ARS08 */ + [53] = {0xFDA03468U, 0x00000002U}, /* RGIDSEC_MODID[53]:CMT0 */ + [54] = {0xFDA0346CU, 0x00000002U}, /* RGIDSEC_MODID[54]:CMT1 */ + [55] = {0xFDA03470U, 0x00000002U}, /* RGIDSEC_MODID[55]:CMT2 */ + [56] = {0xFDA03474U, 0x00000002U}, /* RGIDSEC_MODID[56]:CMT3 */ + [57] = {0xFDA03478U, 0x00000002U}, /* RGIDSEC_MODID[57]:CKM */ + [58] = {0xFDA0347CU, 0x00000002U}, /* RGIDSEC_MODID[58]:DBE */ + [59] = {0xFDA03480U, 0x00000002U}, /* RGIDSEC_MODID[59]:IRQC */ + [60] = {0xFDA03484U, 0x00000002U}, /* RGIDSEC_MODID[60]:ECMPS0 */ + [61] = {0xFDA0349CU, 0x00000002U}, /* RGIDSEC_MODID[61]:SCMT */ + [62] = {0xFDA034A8U, 0x00000002U}, /* RGIDSEC_MODID[62]:TSC1 */ + [63] = {0xFDA034ACU, 0x00000002U}, /* RGIDSEC_MODID[63]:TSC2 */ + [64] = {0xFDA034B0U, 0x00000002U}, /* RGIDSEC_MODID[64]:TSC3 */ + [65] = {0xFDA034B4U, 0x00000002U}, /* RGIDSEC_MODID[65]:TSC4 */ + [66] = {0xFDA034B8U, 0x00000002U}, /* RGIDSEC_MODID[66]:UCMT */ + [67] = {0xFDA03500U, 0x00000002U}, /* RGIDSEC_MODID[67]:CPG0 */ + [68] = {0xFDA03504U, 0x00000002U}, /* RGIDSEC_MODID[68]:CPG1 */ + [69] = {0xFDA03508U, 0x00000002U}, /* RGIDSEC_MODID[69]:CPG2 */ + [70] = {0xFDA0350CU, 0x00000002U}, /* RGIDSEC_MODID[70]:CPG3 */ + [71] = {0xFDA03510U, 0x00000002U}, /* RGIDSEC_MODID[71]:PFC00 */ + [72] = {0xFDA03514U, 0x00000002U}, /* RGIDSEC_MODID[72]:PFC01 */ + [73] = {0xFDA03518U, 0x00000002U}, /* RGIDSEC_MODID[73]:PFC02 */ + [74] = {0xFDA0351CU, 0x00000002U}, /* RGIDSEC_MODID[74]:PFC03 */ + [75] = {0xFDA03550U, 0x00000002U}, /* RGIDSEC_MODID[75]:PFCS0 */ + [76] = {0xFDA03554U, 0x00000002U}, /* RGIDSEC_MODID[76]:PFCS1 */ + [77] = {0xFDA03558U, 0x00000002U}, /* RGIDSEC_MODID[77]:PFCS2 */ + [78] = {0xFDA0355CU, 0x00000002U}, /* RGIDSEC_MODID[78]:PFCS3 */ + [79] = {0xFDA03560U, 0x00000002U}, /* RGIDSEC_MODID[79]:RESET0 */ + [80] = {0xFDA03564U, 0x00000002U}, /* RGIDSEC_MODID[80]:RESET1 */ + [81] = {0xFDA03568U, 0x00000002U}, /* RGIDSEC_MODID[81]:RESET2 */ + [82] = {0xFDA0356CU, 0x00000002U}, /* RGIDSEC_MODID[82]:RESET3 */ + [83] = {0xFDA03570U, 0x00000002U}, /* RGIDSEC_MODID[83]:SYS0 */ + [84] = {0xFDA03574U, 0x00000002U}, /* RGIDSEC_MODID[84]:SYS1 */ + [85] = {0xFDA03578U, 0x00000002U}, /* RGIDSEC_MODID[85]:SYS2 */ + [86] = {0xFDA0357CU, 0x00000002U}, /* RGIDSEC_MODID[86]:SYS3 */ + [87] = {0xFCB63400U, 0x00000002U}, /* RGIDSEC_MODID[87]:DMAMSI0 */ + [88] = {0xFCB63404U, 0x00000002U}, /* RGIDSEC_MODID[88]:DMAMSI1 */ + [89] = {0xFCB63408U, 0x00000002U}, /* RGIDSEC_MODID[89]:DMAMSI2 */ + [90] = {0xFCB6340CU, 0x00000002U}, /* RGIDSEC_MODID[90]:DMAMSI3 */ + [91] = {0xFCB63418U, 0x00000002U}, /* RGIDSEC_MODID[91]:ECMSP3 */ + [92] = {0xFCB63424U, 0x00000002U}, /* RGIDSEC_MODID[92]:ARSP30 */ + [93] = {0xFCB63428U, 0x00000002U}, /* RGIDSEC_MODID[93]:ARSP31 */ + [94] = {0xFCB6342CU, 0x00000002U}, /* RGIDSEC_MODID[94]:ARSP32 */ + [95] = {0xFCB63430U, 0x00000002U}, /* RGIDSEC_MODID[95]:ARSP33 */ + [96] = {0xFCB63434U, 0x00000002U}, /* RGIDSEC_MODID[96]:ARSP34 */ + [97] = {0xFCB63438U, 0x00000002U}, /* RGIDSEC_MODID[97]:ARSP35 */ + [98] = {0xFCB6343CU, 0x00000002U}, /* RGIDSEC_MODID[98]:ARSP36 */ + [99] = {0xFCB63440U, 0x00000002U}, /* RGIDSEC_MODID[99]:ARSP37 */ + [100] = {0xFCB63444U, 0x00000002U}, /* RGIDSEC_MODID[100]:ARSP38 */ + [101] = {0xFCB63448U, 0x00000002U}, /* RGIDSEC_MODID[101]:MSI0 */ + [102] = {0xFCB6344CU, 0x00000002U}, /* RGIDSEC_MODID[102]:MSI1 */ + [103] = {0xFCB63450U, 0x00000002U}, /* RGIDSEC_MODID[103]:MSI2 */ + [104] = {0xFCB63454U, 0x00000002U}, /* RGIDSEC_MODID[104]:MSI3 */ + [105] = {0xFCB93400U, 0x00000002U}, /* RGIDSEC_MODID[105]:ARSP40 */ + [106] = {0xFCB93404U, 0x00000002U}, /* RGIDSEC_MODID[106]:ARSP41 */ + [107] = {0xFCB93408U, 0x00000002U}, /* RGIDSEC_MODID[107]:ARSP42 */ + [108] = {0xFCB9340CU, 0x00000002U}, /* RGIDSEC_MODID[108]:ARSP43 */ + [109] = {0xFCB93410U, 0x00000002U}, /* RGIDSEC_MODID[109]:ARSP44 */ + [110] = {0xFCB93414U, 0x00000002U}, /* RGIDSEC_MODID[110]:ARSP45 */ + [111] = {0xFCB93418U, 0x00000002U}, /* RGIDSEC_MODID[111]:ARSP46 */ + [112] = {0xFCB9341CU, 0x00000002U}, /* RGIDSEC_MODID[112]:ARSP47 */ + [113] = {0xFCB93420U, 0x00000002U}, /* RGIDSEC_MODID[113]:ARSP48 */ + [114] = {0xFCB93424U, 0x00000002U}, /* RGIDSEC_MODID[114]:DMAHSCIF0 */ + [115] = {0xFCB93428U, 0x00000002U}, /* RGIDSEC_MODID[115]:DMAHSCIF1 */ + [116] = {0xFCB9342CU, 0x00000002U}, /* RGIDSEC_MODID[116]:DMAHSCIF2 */ + [117] = {0xFCB93430U, 0x00000002U}, /* RGIDSEC_MODID[117]:DMAHSCIF3 */ + [118] = {0xFCB93434U, 0x00000002U}, /* RGIDSEC_MODID[118]:DMASCIF0 */ + [119] = {0xFCB93438U, 0x00000002U}, /* RGIDSEC_MODID[119]:DMASCIF1 */ + [120] = {0xFCB9343CU, 0x00000002U}, /* RGIDSEC_MODID[120]:DMASCIF3 */ + [121] = {0xFCB93440U, 0x00000002U}, /* RGIDSEC_MODID[121]:DMASCIF4 */ + [122] = {0xFCB93444U, 0x00000002U}, /* RGIDSEC_MODID[122]:ECMSP4 */ + [123] = {0xFCB93448U, 0x00000002U}, /* RGIDSEC_MODID[123]:HSCIF0 */ + [124] = {0xFCB9344CU, 0x00000002U}, /* RGIDSEC_MODID[124]:HSCIF1 */ + [125] = {0xFCB93450U, 0x00000002U}, /* RGIDSEC_MODID[125]:HSCIF2 */ + [126] = {0xFCB93454U, 0x00000002U}, /* RGIDSEC_MODID[126]:HSCIF3 */ + [127] = {0xFCB93458U, 0x00000002U}, /* RGIDSEC_MODID[127]:SCIF0 */ + [128] = {0xFCB9345CU, 0x00000002U}, /* RGIDSEC_MODID[128]:SCIF1 */ + [129] = {0xFCB93460U, 0x00000002U}, /* RGIDSEC_MODID[129]:SCIF3 */ + [130] = {0xFCB93464U, 0x00000002U}, /* RGIDSEC_MODID[130]:SCIF4 */ + [131] = {0xFCB93468U, 0x00000002U}, /* RGIDSEC_MODID[131]:TMU1 */ + [132] = {0xFCB9346CU, 0x00000002U}, /* RGIDSEC_MODID[132]:TMU2 */ + [133] = {0xFCB93470U, 0x00000002U}, /* RGIDSEC_MODID[133]:TMU3 */ + [134] = {0xFCB93474U, 0x00000002U}, /* RGIDSEC_MODID[134]:TMU4 */ + [135] = {0xFCF83400U, 0x00000002U}, /* RGIDSEC_MODID[135]:CKMHSC */ + [136] = {0xFCF83404U, 0x00000002U}, /* RGIDSEC_MODID[136]:AXIPCI001 */ + [137] = {0xFCF83408U, 0x00000002U}, /* RGIDSEC_MODID[137]:AXIPCI002 */ + [138] = {0xFCF8340CU, 0x00000002U}, /* RGIDSEC_MODID[138]:AXIPCI003 */ + [139] = {0xFCF83410U, 0x00000002U}, /* RGIDSEC_MODID[139]:ETHPHY */ + [140] = {0xFCF83414U, 0x00000002U}, /* RGIDSEC_MODID[140]:AXIPCI005 */ + [141] = {0xFCF83418U, 0x00000002U}, /* RGIDSEC_MODID[141]:AXIPCI006 */ + [142] = {0xFCF8341CU, 0x00000002U}, /* RGIDSEC_MODID[142]:AXIPCI007 */ + [143] = {0xFCF83420U, 0x00000002U}, /* RGIDSEC_MODID[143]:AXIPCI008 */ + [144] = {0xFCF83424U, 0x00000002U}, /* RGIDSEC_MODID[144]:AXIPCI009 */ + [145] = {0xFCF83428U, 0x00000002U}, /* RGIDSEC_MODID[145]:AXIPCI010 */ + [146] = {0xFCF8342CU, 0x00000002U}, /* RGIDSEC_MODID[146]:AXIPCI011 */ + [147] = {0xFCF83430U, 0x00000002U}, /* RGIDSEC_MODID[147]:AXIPCI012 */ + [148] = {0xFCF83434U, 0x00000002U}, /* RGIDSEC_MODID[148]:AXIPCI013 */ + [149] = {0xFCF83438U, 0x00000002U}, /* RGIDSEC_MODID[149]:AXIPCI014 */ + [150] = {0xFCF8343CU, 0x00000002U}, /* RGIDSEC_MODID[150]:AXIPCI015 */ + [151] = {0xFCF83440U, 0x00000002U}, /* RGIDSEC_MODID[151]:AXIPCI100 */ + [152] = {0xFCF83444U, 0x00000002U}, /* RGIDSEC_MODID[152]:AXIPCI101 */ + [153] = {0xFCF83448U, 0x00000002U}, /* RGIDSEC_MODID[153]:AXIPCI102 */ + [154] = {0xFCF8344CU, 0x00000002U}, /* RGIDSEC_MODID[154]:AXIPCI103 */ + [155] = {0xFCF83450U, 0x00000002U}, /* RGIDSEC_MODID[155]:AXIPCI104 */ + [156] = {0xFCF83454U, 0x00000002U}, /* RGIDSEC_MODID[156]:AXIPCI105 */ + [157] = {0xFCF83458U, 0x00000002U}, /* RGIDSEC_MODID[157]:AXIPCI106 */ + [158] = {0xFCF8345CU, 0x00000002U}, /* RGIDSEC_MODID[158]:AXIPCI107 */ + [159] = {0xFCF83460U, 0x00000002U}, /* RGIDSEC_MODID[159]:AXIPCI108 */ + [160] = {0xFCF83464U, 0x00000002U}, /* RGIDSEC_MODID[160]:AXIPCI109 */ + [161] = {0xFCF83468U, 0x00000002U}, /* RGIDSEC_MODID[161]:AXIPCI110 */ + [162] = {0xFCF8346CU, 0x00000002U}, /* RGIDSEC_MODID[162]:AXIPCI111 */ + [163] = {0xFCF83470U, 0x00000002U}, /* RGIDSEC_MODID[163]:AXIPCI112 */ + [164] = {0xFCF83474U, 0x00000002U}, /* RGIDSEC_MODID[164]:AXIPCI113 */ + [165] = {0xFCF83478U, 0x00000002U}, /* RGIDSEC_MODID[165]:AXIPCI114 */ + [166] = {0xFCF8347CU, 0x00000002U}, /* RGIDSEC_MODID[166]:AXIPCI115 */ + [167] = {0xFCF83480U, 0x00000002U}, /* RGIDSEC_MODID[167]:ETHPHYRAM */ + [168] = {0xFCF83488U, 0x00000002U}, /* RGIDSEC_MODID[168]:IPMMUHC00 */ + [169] = {0xFCF8348CU, 0x00000002U}, /* RGIDSEC_MODID[169]:RSW200 */ + [170] = {0xFCF83490U, 0x00000002U}, /* RGIDSEC_MODID[170]:RSW201 */ + [171] = {0xFCF83494U, 0x00000002U}, /* RGIDSEC_MODID[171]:RSW210 */ + [172] = {0xFCF83498U, 0x00000002U}, /* RGIDSEC_MODID[172]:RSW211 */ + [173] = {0xFCF8349CU, 0x00000002U}, /* RGIDSEC_MODID[173]:RSW202 */ + [174] = {0xFCF834A0U, 0x00000002U}, /* RGIDSEC_MODID[174]:RSW203 */ + [175] = {0xFCF834A4U, 0x00000002U}, /* RGIDSEC_MODID[175]:RSW204 */ + [176] = {0xFCF834A8U, 0x00000002U}, /* RGIDSEC_MODID[176]:RSW205 */ + [177] = {0xFCF834ACU, 0x00000002U}, /* RGIDSEC_MODID[177]:RSW206 */ + [178] = {0xFCF834B0U, 0x00000002U}, /* RGIDSEC_MODID[178]:RSW207 */ + [179] = {0xFCF834B4U, 0x00000002U}, /* RGIDSEC_MODID[179]:RSW208 */ + [180] = {0xFCF834B8U, 0x00000002U}, /* RGIDSEC_MODID[180]:RSW209 */ + [181] = {0xFCF834BCU, 0x00000002U}, /* RGIDSEC_MODID[181]:RSW2RAM */ + [182] = {0xFCF834C0U, 0x00000002U}, /* RGIDSEC_MODID[182]:RSW2SEC00 */ + [183] = {0xFCF834C4U, 0x00000002U}, /* RGIDSEC_MODID[183]:RSW2SEC01 */ + [184] = {0xFCF834C8U, 0x00000002U}, /* RGIDSEC_MODID[184]:RSW2SEC10 */ + [185] = {0xFCF834CCU, 0x00000002U}, /* RGIDSEC_MODID[185]:RSW2SEC11 */ + [186] = {0xFCF834D0U, 0x00000002U}, /* RGIDSEC_MODID[186]:RSW2SEC02 */ + [187] = {0xFCF834D4U, 0x00000002U}, /* RGIDSEC_MODID[187]:RSW2SEC03 */ + [188] = {0xFCF834D8U, 0x00000002U}, /* RGIDSEC_MODID[188]:RSW2SEC04 */ + [189] = {0xFCF834DCU, 0x00000002U}, /* RGIDSEC_MODID[189]:RSW2SEC05 */ + [190] = {0xFCF834E0U, 0x00000002U}, /* RGIDSEC_MODID[190]:RSW2SEC06 */ + [191] = {0xFCF834E4U, 0x00000002U}, /* RGIDSEC_MODID[191]:RSW2SEC07 */ + [192] = {0xFCF834E8U, 0x00000002U}, /* RGIDSEC_MODID[192]:RSW2SEC08 */ + [193] = {0xFCF834ECU, 0x00000002U}, /* RGIDSEC_MODID[193]:RSW2SEC09 */ + [194] = {0xFCF834F4U, 0x00000002U}, /* RGIDSEC_MODID[194]:AXIPCI000 */ + [195] = {0xFCF834F8U, 0x00000002U}, /* RGIDSEC_MODID[195]:AXIPCI004 */ + [196] = {0xFCF834FCU, 0x00000002U}, /* RGIDSEC_MODID[196]:IPMMUHC01 */ + [197] = {0xFCF8350CU, 0x00000002U}, /* RGIDSEC_MODID[197]:IPMMUHC10 */ + [198] = {0xFCF83510U, 0x00000002U}, /* RGIDSEC_MODID[198]:IPMMUHC11 */ + [199] = {0xFCF83514U, 0x00000002U}, /* RGIDSEC_MODID[199]:IPMMUHC12 */ + [200] = {0xFCF83518U, 0x00000002U}, /* RGIDSEC_MODID[200]:IPMMUHC13 */ + [201] = {0xFCF8351CU, 0x00000002U}, /* RGIDSEC_MODID[201]:PPHY0 */ + [202] = {0xFCF83520U, 0x00000002U}, /* RGIDSEC_MODID[202]:PPHY1 */ + [203] = {0xFCF83524U, 0x00000002U}, /* RGIDSEC_MODID[203]:IPMMUHC14 */ + [204] = {0xFCF83528U, 0x00000002U}, /* RGIDSEC_MODID[204]:IPMMUHC15 */ + [205] = {0xFCF8352CU, 0x00000002U}, /* RGIDSEC_MODID[205]:FBAHSC */ + [206] = {0xFCF83530U, 0x00000002U}, /* RGIDSEC_MODID[206]:IPMMUHC02 */ + [207] = {0xFCF83534U, 0x00000002U}, /* RGIDSEC_MODID[207]:AXIUFSS */ + [208] = {0xFCF83538U, 0x00000002U}, /* RGIDSEC_MODID[208]:ECMHSC */ + [209] = {0xFCF8353CU, 0x00000002U}, /* RGIDSEC_MODID[209]:ARHC0 */ + [210] = {0xFCF83540U, 0x00000002U}, /* RGIDSEC_MODID[210]:ARHC1 */ + [211] = {0xFCF83544U, 0x00000002U}, /* RGIDSEC_MODID[211]:ARHC2 */ + [212] = {0xFCF83548U, 0x00000002U}, /* RGIDSEC_MODID[212]:ARHC3 */ + [213] = {0xFCF8354CU, 0x00000002U}, /* RGIDSEC_MODID[213]:ARHC4 */ + [214] = {0xFCF83550U, 0x00000002U}, /* RGIDSEC_MODID[214]:ARHC5 */ + [215] = {0xFCF83554U, 0x00000002U}, /* RGIDSEC_MODID[215]:ARHC6 */ + [216] = {0xFCF83558U, 0x00000002U}, /* RGIDSEC_MODID[216]:ARHC7 */ + [217] = {0xFCF8355CU, 0x00000002U}, /* RGIDSEC_MODID[217]:ARHC8 */ + [218] = {0xFCF83560U, 0x00000002U}, /* RGIDSEC_MODID[218]:IPMMUHC03 */ + [219] = {0xFCF83564U, 0x00000002U}, /* RGIDSEC_MODID[219]:IPMMUHC04 */ + [220] = {0xFCF83568U, 0x00000002U}, /* RGIDSEC_MODID[220]:IPMMUHC05 */ + [221] = {0xFCF8356CU, 0x00000002U}, /* RGIDSEC_MODID[221]:IPMMUHC06 */ + [222] = {0xFCF83570U, 0x00000002U}, /* RGIDSEC_MODID[222]:IPMMUHC07 */ + [223] = {0xFCF83574U, 0x00000002U}, /* RGIDSEC_MODID[223]:IPMMUHC08 */ + [224] = {0xFCF83578U, 0x00000002U}, /* RGIDSEC_MODID[224]:IPMMUHC09 */ + [225] = {0xFDC23400U, 0x00000002U}, /* RGIDSEC_MODID[225]:ARRC0 */ + [226] = {0xFDC23404U, 0x00000002U}, /* RGIDSEC_MODID[226]:ARRC1 */ + [227] = {0xFDC23408U, 0x00000002U}, /* RGIDSEC_MODID[227]:ARRC2 */ + [228] = {0xFDC2340CU, 0x00000002U}, /* RGIDSEC_MODID[228]:ARRC3 */ + [229] = {0xFDC23410U, 0x00000002U}, /* RGIDSEC_MODID[229]:ARRC4 */ + [230] = {0xFDC23414U, 0x00000002U}, /* RGIDSEC_MODID[230]:ARRC5 */ + [231] = {0xFDC23418U, 0x00000002U}, /* RGIDSEC_MODID[231]:ARRC6 */ + [232] = {0xFDC2341CU, 0x00000002U}, /* RGIDSEC_MODID[232]:ARRC7 */ + [233] = {0xFDC23420U, 0x00000002U}, /* RGIDSEC_MODID[233]:ARRC8 */ + [234] = {0xFDC23424U, 0x00000000U}, /* RGIDSEC_MODID[234]:CR0 */ + [235] = {0xFDC23428U, 0x00000002U}, /* RGIDSEC_MODID[235]:ICUMX */ + [236] = {0xFDC2342CU, 0x00000002U}, /* RGIDSEC_MODID[236]:ECMRC */ + [237] = {0xFD433400U, 0x00000002U}, /* RGIDSEC_MODID[237]:DMAWCRC0 */ + [238] = {0xFD433404U, 0x00000002U}, /* RGIDSEC_MODID[238]:DMAWCRC1 */ + [239] = {0xFD433408U, 0x00000002U}, /* RGIDSEC_MODID[239]:DMAWCRC2 */ + [240] = {0xFD43340CU, 0x00000002U}, /* RGIDSEC_MODID[240]:DMAWCRC3 */ + [241] = {0xFD433410U, 0x00000002U}, /* RGIDSEC_MODID[241]:DMATSIP0 */ + [242] = {0xFD433414U, 0x00000002U}, /* RGIDSEC_MODID[242]:DMATSIP1 */ + [243] = {0xFD433418U, 0x00000002U}, /* RGIDSEC_MODID[243]:DMATSIP2 */ + [244] = {0xFD443400U, 0x00000002U}, /* RGIDSEC_MODID[244]:ARMREG00 */ + [245] = {0xFD443404U, 0x00000002U}, /* RGIDSEC_MODID[245]:ARMREG01 */ + [246] = {0xFD443408U, 0x00000002U}, /* RGIDSEC_MODID[246]:ARMREG10 */ + [247] = {0xFD44340CU, 0x00000002U}, /* RGIDSEC_MODID[247]:ARMREG11 */ + [248] = {0xFD443410U, 0x00000002U}, /* RGIDSEC_MODID[248]:ARMREG12 */ + [249] = {0xFD443414U, 0x00000000U}, /* RGIDSEC_MODID[249]:ARMREG13 */ + [250] = {0xFD443418U, 0x00000000U}, /* RGIDSEC_MODID[250]:ARMREG14 */ + [251] = {0xFD44341CU, 0x00000002U}, /* RGIDSEC_MODID[251]:AXICR52SS */ + [252] = {0xFD443420U, 0x00000002U}, /* RGIDSEC_MODID[252]:AXICSD0 */ + [253] = {0xFD443424U, 0x00000002U}, /* RGIDSEC_MODID[253]:AXIINTAP0 */ + [254] = {0xFD443428U, 0x00000002U}, /* RGIDSEC_MODID[254]:AXIINTAP1 */ + [255] = {0xFD44342CU, 0x00000002U}, /* RGIDSEC_MODID[255]:AXISECROM */ + [256] = {0xFD443430U, 0x00000002U}, /* RGIDSEC_MODID[256]:AXISYSRAM0 */ + [257] = {0xFD443434U, 0x00000002U}, /* RGIDSEC_MODID[257]:AXISYSRAM1 */ + [258] = {0xFD443438U, 0x00000002U}, /* RGIDSEC_MODID[258]:ARGREG15 */ + [259] = {0xFD44343CU, 0x00000002U}, /* RGIDSEC_MODID[259]:ARMREG2 */ + [260] = {0xFD443440U, 0x00000002U}, /* RGIDSEC_MODID[260]:ARMREG3 */ + [261] = {0xFD443444U, 0x00000002U}, /* RGIDSEC_MODID[261]:ARMREG4 */ + [262] = {0xFD443448U, 0x00000002U}, /* RGIDSEC_MODID[262]:ARMREG5 */ + [263] = {0xFD44344CU, 0x00000002U}, /* RGIDSEC_MODID[263]:ARMREG6 */ + [264] = {0xFD443450U, 0x00000002U}, /* RGIDSEC_MODID[264]:ARMREG7 */ + [265] = {0xFD443454U, 0x00000000U}, /* RGIDSEC_MODID[265]:ARMREG8 */ + [266] = {0xFD443458U, 0x00000000U}, /* RGIDSEC_MODID[266]:ARMREG9 */ + [267] = {0xFD44345CU, 0x00000002U}, /* RGIDSEC_MODID[267]:ARRD0 */ + [268] = {0xFD443460U, 0x00000002U}, /* RGIDSEC_MODID[268]:ARRD1 */ + [269] = {0xFD443464U, 0x00000002U}, /* RGIDSEC_MODID[269]:ARRD2 */ + [270] = {0xFD443468U, 0x00000002U}, /* RGIDSEC_MODID[270]:ARRD3 */ + [271] = {0xFD44346CU, 0x00000002U}, /* RGIDSEC_MODID[271]:ARRD4 */ + [272] = {0xFD443470U, 0x00000002U}, /* RGIDSEC_MODID[272]:ARRD5 */ + [273] = {0xFD443474U, 0x00000002U}, /* RGIDSEC_MODID[273]:ARRD6 */ + [274] = {0xFD443478U, 0x00000002U}, /* RGIDSEC_MODID[274]:ARRD7 */ + [275] = {0xFD44347CU, 0x00000002U}, /* RGIDSEC_MODID[275]:ARRD8 */ + [276] = {0xFD443480U, 0x00000002U}, /* RGIDSEC_MODID[276]:ARRT0 */ + [277] = {0xFD443484U, 0x00000002U}, /* RGIDSEC_MODID[277]:ARRT1 */ + [278] = {0xFD443488U, 0x00000002U}, /* RGIDSEC_MODID[278]:ARRT2 */ + [279] = {0xFD44348CU, 0x00000002U}, /* RGIDSEC_MODID[279]:ARRT3 */ + [280] = {0xFD443490U, 0x00000002U}, /* RGIDSEC_MODID[280]:ARRT4 */ + [281] = {0xFD443494U, 0x00000002U}, /* RGIDSEC_MODID[281]:ARRT5 */ + [282] = {0xFD443498U, 0x00000002U}, /* RGIDSEC_MODID[282]:ARRT6 */ + [283] = {0xFD44349CU, 0x00000002U}, /* RGIDSEC_MODID[283]:ARRT7 */ + [284] = {0xFD4434A0U, 0x00000002U}, /* RGIDSEC_MODID[284]:ARRT8 */ + [285] = {0xFD4434A4U, 0x00000002U}, /* RGIDSEC_MODID[285]:CKMRT */ + [286] = {0xFD4434A8U, 0x00000002U}, /* RGIDSEC_MODID[286]:CRC0 */ + [287] = {0xFD4434ACU, 0x00000002U}, /* RGIDSEC_MODID[287]:CRC1 */ + [288] = {0xFD4434B0U, 0x00000002U}, /* RGIDSEC_MODID[288]:CRC2 */ + [289] = {0xFD4434B4U, 0x00000002U}, /* RGIDSEC_MODID[289]:CRC3 */ + [290] = {0xFD4434B8U, 0x00000002U}, /* RGIDSEC_MODID[290]:CSD */ + [291] = {0xFD4434BCU, 0x00000002U}, /* RGIDSEC_MODID[291]:ECM */ + [292] = {0xFD4434C0U, 0x00000002U}, /* RGIDSEC_MODID[292]:ECMRT */ + [293] = {0xFD4434C4U, 0x00000002U}, /* RGIDSEC_MODID[293]:FBACR52 */ + [294] = {0xFD4434C8U, 0x00000002U}, /* RGIDSEC_MODID[294]:FBART */ + [295] = {0xFD4434CCU, 0x00000002U}, /* RGIDSEC_MODID[295]:INTTP */ + [296] = {0xFD4434D0U, 0x00000002U}, /* RGIDSEC_MODID[296]:IPMMURT000 */ + [297] = {0xFD4434D4U, 0x00000002U}, /* RGIDSEC_MODID[297]:IPMMURT100 */ + [298] = {0xFD4434D8U, 0x00000002U}, /* RGIDSEC_MODID[298]:KCRC4 */ + [299] = {0xFD4434DCU, 0x00000002U}, /* RGIDSEC_MODID[299]:KCRC5 */ + [300] = {0xFD4434E0U, 0x00000002U}, /* RGIDSEC_MODID[300]:KCRC6 */ + [301] = {0xFD4434E4U, 0x00000002U}, /* RGIDSEC_MODID[301]:KCRC7 */ + [302] = {0xFD4434E8U, 0x00000002U}, /* RGIDSEC_MODID[302]:MFI00 */ + [303] = {0xFD4434ECU, 0x00000002U}, /* RGIDSEC_MODID[303]:MFI01 */ + [304] = {0xFD4434F0U, 0x00000002U}, /* RGIDSEC_MODID[304]:MFI10 */ + [305] = {0xFD4434F4U, 0x00000002U}, /* RGIDSEC_MODID[305]:MFI02 */ + [306] = {0xFD4434F8U, 0x00000002U}, /* RGIDSEC_MODID[306]:MFI03 */ + [307] = {0xFD4434FCU, 0x00000002U}, /* RGIDSEC_MODID[307]:MFI04 */ + [308] = {0xFD443500U, 0x00000002U}, /* RGIDSEC_MODID[308]:MFI05 */ + [309] = {0xFD443504U, 0x00000002U}, /* RGIDSEC_MODID[309]:MFI06 */ + [310] = {0xFD443508U, 0x00000002U}, /* RGIDSEC_MODID[310]:MFI07 */ + [311] = {0xFD44350CU, 0x00000002U}, /* RGIDSEC_MODID[311]:MFI08 */ + [312] = {0xFD443510U, 0x00000002U}, /* RGIDSEC_MODID[312]:MFI09 */ + [313] = {0xFD443514U, 0x00000002U}, /* RGIDSEC_MODID[313]:MFI15 */ + [314] = {0xFD443518U, 0x00000002U}, /* RGIDSEC_MODID[314]:CKMCR52 */ + [315] = {0xFD44351CU, 0x00000002U}, /* RGIDSEC_MODID[315]:RTDM0P */ + [316] = {0xFD443520U, 0x00000002U}, /* RGIDSEC_MODID[316]:ECMRD */ + [317] = {0xFD443524U, 0x00000002U}, /* RGIDSEC_MODID[317]:RTDM1P */ + [318] = {0xFD44352CU, 0x00000002U}, /* RGIDSEC_MODID[318]:RTDM2P */ + [319] = {0xFD443530U, 0x00000002U}, /* RGIDSEC_MODID[319]:SYSRAM10 */ + [320] = {0xFD443534U, 0x00000002U}, /* RGIDSEC_MODID[320]:RTDM3P */ + [321] = {0xFD443538U, 0x00000000U}, /* RGIDSEC_MODID[321]:SYSRAM00 */ + [322] = {0xFD44353CU, 0x00000002U}, /* RGIDSEC_MODID[322]:TSIPL0 */ + [323] = {0xFD443540U, 0x00000002U}, /* RGIDSEC_MODID[323]:TSIPL1 */ + [324] = {0xFD443544U, 0x00000002U}, /* RGIDSEC_MODID[324]:TSIPL2 */ + [325] = {0xFD443548U, 0x00000002U}, /* RGIDSEC_MODID[325]:TSIPL3 */ + [326] = {0xFD44354CU, 0x00000002U}, /* RGIDSEC_MODID[326]:TSIPL4 */ + [327] = {0xFD443550U, 0x00000002U}, /* RGIDSEC_MODID[327]:TSIPL5 */ + [328] = {0xFD443554U, 0x00000002U}, /* RGIDSEC_MODID[328]:TSIPL6 */ + [329] = {0xFD443558U, 0x00000002U}, /* RGIDSEC_MODID[329]:TSIPL7 */ + [330] = {0xFD44355CU, 0x00000002U}, /* RGIDSEC_MODID[330]:WCRC0 */ + [331] = {0xFD443560U, 0x00000002U}, /* RGIDSEC_MODID[331]:WCRC1 */ + [332] = {0xFD443564U, 0x00000002U}, /* RGIDSEC_MODID[332]:WCRC2 */ + [333] = {0xFD443568U, 0x00000002U}, /* RGIDSEC_MODID[333]:WCRC3 */ + [334] = {0xFD443574U, 0x00000002U}, /* RGIDSEC_MODID[334]:TSIP0 */ + [335] = {0xFD443578U, 0x00000002U}, /* RGIDSEC_MODID[335]:TSIP1 */ + [336] = {0xFD44357CU, 0x00000002U}, /* RGIDSEC_MODID[336]:TSIP2 */ + [337] = {0xFD443580U, 0x00000002U}, /* RGIDSEC_MODID[337]:MFI11 */ + [338] = {0xFD443584U, 0x00000002U}, /* RGIDSEC_MODID[338]:MFI12 */ + [339] = {0xFD443588U, 0x00000002U}, /* RGIDSEC_MODID[339]:MFI13 */ + [340] = {0xFD44358CU, 0x00000002U}, /* RGIDSEC_MODID[340]:MFI14 */ + [341] = {0xFD443590U, 0x00000002U}, /* RGIDSEC_MODID[341]:IPMMURT001 */ + [342] = {0xFD443594U, 0x00000002U}, /* RGIDSEC_MODID[342]:IPMMURT010 */ + [343] = {0xFD443598U, 0x00000002U}, /* RGIDSEC_MODID[343]:IPMMURT011 */ + [344] = {0xFD44359CU, 0x00000002U}, /* RGIDSEC_MODID[344]:IPMMURT012 */ + [345] = {0xFD4435A0U, 0x00000002U}, /* RGIDSEC_MODID[345]:IPMMURT013 */ + [346] = {0xFD4435A4U, 0x00000002U}, /* RGIDSEC_MODID[346]:IPMMURT014 */ + [347] = {0xFD4435A8U, 0x00000002U}, /* RGIDSEC_MODID[347]:IPMMURT015 */ + [348] = {0xFD4435ACU, 0x00000002U}, /* RGIDSEC_MODID[348]:IPMMURT002 */ + [349] = {0xFD4435B0U, 0x00000002U}, /* RGIDSEC_MODID[349]:IPMMURT003 */ + [350] = {0xFD4435B4U, 0x00000002U}, /* RGIDSEC_MODID[350]:IPMMURT004 */ + [351] = {0xFD4435B8U, 0x00000002U}, /* RGIDSEC_MODID[351]:IPMMURT005 */ + [352] = {0xFD4435BCU, 0x00000002U}, /* RGIDSEC_MODID[352]:IPMMURT006 */ + [353] = {0xFD4435C0U, 0x00000002U}, /* RGIDSEC_MODID[353]:IPMMURT007 */ + [354] = {0xFD4435C4U, 0x00000002U}, /* RGIDSEC_MODID[354]:IPMMURT008 */ + [355] = {0xFD4435C8U, 0x00000002U}, /* RGIDSEC_MODID[355]:IPMMURT009 */ + [356] = {0xFD4435CCU, 0x00000002U}, /* RGIDSEC_MODID[356]:IPMMURT101 */ + [357] = {0xFD4435D0U, 0x00000002U}, /* RGIDSEC_MODID[357]:IPMMURT110 */ + [358] = {0xFD4435D4U, 0x00000002U}, /* RGIDSEC_MODID[358]:IPMMURT111 */ + [359] = {0xFD4435D8U, 0x00000002U}, /* RGIDSEC_MODID[359]:IPMMURT112 */ + [360] = {0xFD4435DCU, 0x00000002U}, /* RGIDSEC_MODID[360]:IPMMURT113 */ + [361] = {0xFD4435E0U, 0x00000002U}, /* RGIDSEC_MODID[361]:IPMMURT114 */ + [362] = {0xFD4435E4U, 0x00000002U}, /* RGIDSEC_MODID[362]:IPMMURT115 */ + [363] = {0xFD4435E8U, 0x00000002U}, /* RGIDSEC_MODID[363]:IPMMURT102 */ + [364] = {0xFD4435ECU, 0x00000002U}, /* RGIDSEC_MODID[364]:IPMMURT103 */ + [365] = {0xFD4435F0U, 0x00000002U}, /* RGIDSEC_MODID[365]:IPMMURT104 */ + [366] = {0xFD4435F4U, 0x00000002U}, /* RGIDSEC_MODID[366]:IPMMURT105 */ + [367] = {0xFD4435F8U, 0x00000002U}, /* RGIDSEC_MODID[367]:IPMMURT106 */ + [368] = {0xFD4435FCU, 0x00000002U}, /* RGIDSEC_MODID[368]:IPMMURT107 */ + [369] = {0xFD443600U, 0x00000002U}, /* RGIDSEC_MODID[369]:RTDM000 */ + [370] = {0xFD443604U, 0x00000002U}, /* RGIDSEC_MODID[370]:RTDM001 */ + [371] = {0xFD443608U, 0x00000002U}, /* RGIDSEC_MODID[371]:RTDM010 */ + [372] = {0xFD44360CU, 0x00000002U}, /* RGIDSEC_MODID[372]:RTDM011 */ + [373] = {0xFD443610U, 0x00000002U}, /* RGIDSEC_MODID[373]:RTDM012 */ + [374] = {0xFD443614U, 0x00000002U}, /* RGIDSEC_MODID[374]:RTDM013 */ + [375] = {0xFD443618U, 0x00000002U}, /* RGIDSEC_MODID[375]:RTDM014 */ + [376] = {0xFD44361CU, 0x00000002U}, /* RGIDSEC_MODID[376]:RTDM015 */ + [377] = {0xFD443620U, 0x00000002U}, /* RGIDSEC_MODID[377]:RTDM002 */ + [378] = {0xFD443624U, 0x00000002U}, /* RGIDSEC_MODID[378]:RTDM003 */ + [379] = {0xFD443628U, 0x00000002U}, /* RGIDSEC_MODID[379]:RTDM004 */ + [380] = {0xFD44362CU, 0x00000002U}, /* RGIDSEC_MODID[380]:RTDM005 */ + [381] = {0xFD443630U, 0x00000002U}, /* RGIDSEC_MODID[381]:RTDM006 */ + [382] = {0xFD443634U, 0x00000002U}, /* RGIDSEC_MODID[382]:RTDM007 */ + [383] = {0xFD443638U, 0x00000002U}, /* RGIDSEC_MODID[383]:RTDM008 */ + [384] = {0xFD44363CU, 0x00000002U}, /* RGIDSEC_MODID[384]:RTDM009 */ + [385] = {0xFD443640U, 0x00000002U}, /* RGIDSEC_MODID[385]:RTDM100 */ + [386] = {0xFD443644U, 0x00000002U}, /* RGIDSEC_MODID[386]:RTDM101 */ + [387] = {0xFD443648U, 0x00000002U}, /* RGIDSEC_MODID[387]:RTDM110 */ + [388] = {0xFD44364CU, 0x00000002U}, /* RGIDSEC_MODID[388]:RTDM111 */ + [389] = {0xFD443650U, 0x00000002U}, /* RGIDSEC_MODID[389]:RTDM112 */ + [390] = {0xFD443654U, 0x00000002U}, /* RGIDSEC_MODID[390]:RTDM113 */ + [391] = {0xFD443658U, 0x00000002U}, /* RGIDSEC_MODID[391]:RTDM114 */ + [392] = {0xFD44365CU, 0x00000002U}, /* RGIDSEC_MODID[392]:RTDM115 */ + [393] = {0xFD443660U, 0x00000002U}, /* RGIDSEC_MODID[393]:RTDM102 */ + [394] = {0xFD443664U, 0x00000002U}, /* RGIDSEC_MODID[394]:RTDM103 */ + [395] = {0xFD443668U, 0x00000002U}, /* RGIDSEC_MODID[395]:RTDM104 */ + [396] = {0xFD44366CU, 0x00000002U}, /* RGIDSEC_MODID[396]:RTDM105 */ + [397] = {0xFD443670U, 0x00000002U}, /* RGIDSEC_MODID[397]:RTDM106 */ + [398] = {0xFD443674U, 0x00000002U}, /* RGIDSEC_MODID[398]:RTDM107 */ + [399] = {0xFD443678U, 0x00000002U}, /* RGIDSEC_MODID[399]:RTDM108 */ + [400] = {0xFD44367CU, 0x00000002U}, /* RGIDSEC_MODID[400]:RTDM109 */ + [401] = {0xFD443680U, 0x00000002U}, /* RGIDSEC_MODID[401]:RTDM200 */ + [402] = {0xFD443684U, 0x00000002U}, /* RGIDSEC_MODID[402]:RTDM201 */ + [403] = {0xFD443688U, 0x00000002U}, /* RGIDSEC_MODID[403]:RTDM210 */ + [404] = {0xFD44368CU, 0x00000002U}, /* RGIDSEC_MODID[404]:RTDM211 */ + [405] = {0xFD443690U, 0x00000002U}, /* RGIDSEC_MODID[405]:RTDM212 */ + [406] = {0xFD443694U, 0x00000002U}, /* RGIDSEC_MODID[406]:RTDM213 */ + [407] = {0xFD443698U, 0x00000002U}, /* RGIDSEC_MODID[407]:RTDM214 */ + [408] = {0xFD44369CU, 0x00000002U}, /* RGIDSEC_MODID[408]:RTDM215 */ + [409] = {0xFD4436A0U, 0x00000002U}, /* RGIDSEC_MODID[409]:RTDM202 */ + [410] = {0xFD4436A4U, 0x00000002U}, /* RGIDSEC_MODID[410]:RTDM203 */ + [411] = {0xFD4436A8U, 0x00000002U}, /* RGIDSEC_MODID[411]:RTDM204 */ + [412] = {0xFD4436ACU, 0x00000002U}, /* RGIDSEC_MODID[412]:RTDM205 */ + [413] = {0xFD4436B0U, 0x00000002U}, /* RGIDSEC_MODID[413]:RTDM206 */ + [414] = {0xFD4436B4U, 0x00000002U}, /* RGIDSEC_MODID[414]:RTDM207 */ + [415] = {0xFD4436B8U, 0x00000002U}, /* RGIDSEC_MODID[415]:RTDM208 */ + [416] = {0xFD4436BCU, 0x00000002U}, /* RGIDSEC_MODID[416]:RTDM209 */ + [417] = {0xFD4436C0U, 0x00000002U}, /* RGIDSEC_MODID[417]:RTDM300 */ + [418] = {0xFD4436C4U, 0x00000002U}, /* RGIDSEC_MODID[418]:RTDM301 */ + [419] = {0xFD4436C8U, 0x00000002U}, /* RGIDSEC_MODID[419]:RTDM310 */ + [420] = {0xFD4436CCU, 0x00000002U}, /* RGIDSEC_MODID[420]:RTDM311 */ + [421] = {0xFD4436D0U, 0x00000002U}, /* RGIDSEC_MODID[421]:RTDM312 */ + [422] = {0xFD4436D4U, 0x00000002U}, /* RGIDSEC_MODID[422]:RTDM313 */ + [423] = {0xFD4436D8U, 0x00000002U}, /* RGIDSEC_MODID[423]:RTDM314 */ + [424] = {0xFD4436DCU, 0x00000002U}, /* RGIDSEC_MODID[424]:RTDM315 */ + [425] = {0xFD4436E0U, 0x00000002U}, /* RGIDSEC_MODID[425]:RTDM302 */ + [426] = {0xFD4436E4U, 0x00000002U}, /* RGIDSEC_MODID[426]:RTDM303 */ + [427] = {0xFD4436E8U, 0x00000002U}, /* RGIDSEC_MODID[427]:RTDM304 */ + [428] = {0xFD4436ECU, 0x00000002U}, /* RGIDSEC_MODID[428]:RTDM305 */ + [429] = {0xFD4436F0U, 0x00000002U}, /* RGIDSEC_MODID[429]:RTDM306 */ + [430] = {0xFD4436F4U, 0x00000002U}, /* RGIDSEC_MODID[430]:RTDM307 */ + [431] = {0xFD4436F8U, 0x00000002U}, /* RGIDSEC_MODID[431]:RTDM308 */ + [432] = {0xFD4436FCU, 0x00000002U}, /* RGIDSEC_MODID[432]:RTDM309 */ + [433] = {0xFD443700U, 0x00000002U}, /* RGIDSEC_MODID[433]:IPMMURT108 */ + [434] = {0xFD443704U, 0x00000002U}, /* RGIDSEC_MODID[434]:IPMMURT109 */ + [435] = {0xFD443708U, 0x00000000U}, /* RGIDSEC_MODID[435]:SYSRAM01 */ + [436] = {0xFD44370CU, 0x00000002U}, /* RGIDSEC_MODID[436]:SYSRAM02 */ + [437] = {0xFD443710U, 0x00000000U}, /* RGIDSEC_MODID[437]:SYSRAM03 */ + [438] = {0xFD443714U, 0x00000000U}, /* RGIDSEC_MODID[438]:SYSRAM04 */ + [439] = {0xFD443718U, 0x00000000U}, /* RGIDSEC_MODID[439]:SYSRAM05 */ + [440] = {0xFD44371CU, 0x00000000U}, /* RGIDSEC_MODID[440]:SYSRAM06 */ + [441] = {0xFD443720U, 0x00000002U}, /* RGIDSEC_MODID[441]:SYSRAM07 */ + [442] = {0xFD443724U, 0x00000002U}, /* RGIDSEC_MODID[442]:SYSRAM11 */ + [443] = {0xFD443728U, 0x00000002U}, /* RGIDSEC_MODID[443]:SYSRAM12 */ + [444] = {0xFD44372CU, 0x00000002U}, /* RGIDSEC_MODID[444]:SYSRAM13 */ + [445] = {0xFD443730U, 0x00000002U}, /* RGIDSEC_MODID[445]:SYSRAM14 */ + [446] = {0xFD443734U, 0x00000002U}, /* RGIDSEC_MODID[446]:SYSRAM15 */ + [447] = {0xFD443738U, 0x00000002U}, /* RGIDSEC_MODID[447]:SYSRAM16 */ + [448] = {0xFD44373CU, 0x00000002U}, /* RGIDSEC_MODID[448]:SYSRAM17 */ + [449] = {0xFD443760U, 0x00000002U}, /* RGIDSEC_MODID[449]:BKBUF */ + [450] = {0xFD44376CU, 0x00000002U}, /* RGIDSEC_MODID[450]:MCU */ + [451] = {0xFF863400U, 0x00000002U}, /* RGIDSEC_MODID[451]:ARSC0 */ + [452] = {0xFF863404U, 0x00000002U}, /* RGIDSEC_MODID[452]:ARSC1 */ + [453] = {0xFF863408U, 0x00000002U}, /* RGIDSEC_MODID[453]:ARSC2 */ + [454] = {0xFF86340CU, 0x00000002U}, /* RGIDSEC_MODID[454]:ARSC3 */ + [455] = {0xFF863410U, 0x00000002U}, /* RGIDSEC_MODID[455]:ARSC4 */ + [456] = {0xFF863414U, 0x00000002U}, /* RGIDSEC_MODID[456]:ARSC5 */ + [457] = {0xFF863418U, 0x00000002U}, /* RGIDSEC_MODID[457]:ARSC6 */ + [458] = {0xFF86341CU, 0x00000002U}, /* RGIDSEC_MODID[458]:ARSC7 */ + [459] = {0xFF863420U, 0x00000002U}, /* RGIDSEC_MODID[459]:ARSC8 */ + [460] = {0xFF863424U, 0x00000002U}, /* RGIDSEC_MODID[460]:ARSTM0 */ + [461] = {0xFF863428U, 0x00000002U}, /* RGIDSEC_MODID[461]:ARSTM1 */ + [462] = {0xFF863430U, 0x00000002U}, /* RGIDSEC_MODID[462]:AXIFBABUSTOP0 */ + [463] = {0xFF863434U, 0x00000002U}, /* RGIDSEC_MODID[463]:AXIFBABUSTOP1 */ + [464] = {0xFF863438U, 0x00000002U}, /* RGIDSEC_MODID[464]:ARSTM2 */ + [465] = {0xFF86343CU, 0x00000002U}, /* RGIDSEC_MODID[465]:ARSTM3 */ + [466] = {0xFF863440U, 0x00000002U}, /* RGIDSEC_MODID[466]:ARSTM4 */ + [467] = {0xFF863444U, 0x00000002U}, /* RGIDSEC_MODID[467]:ARSTM5 */ + [468] = {0xFF863448U, 0x00000002U}, /* RGIDSEC_MODID[468]:ARSTM6 */ + [469] = {0xFF86344CU, 0x00000002U}, /* RGIDSEC_MODID[469]:ARSTM7 */ + [470] = {0xFF863450U, 0x00000002U}, /* RGIDSEC_MODID[470]:ARSTM8 */ + [471] = {0xFF863454U, 0x00000002U}, /* RGIDSEC_MODID[471]:ECMTOP */ + [472] = {0xFF863458U, 0x00000002U}, /* RGIDSEC_MODID[472]:FBA */ + [473] = {0xFF86345CU, 0x00000002U}, /* RGIDSEC_MODID[473]:FBC */ + [474] = {0xFF863460U, 0x00000002U}, /* RGIDSEC_MODID[474]:AXICCI00 */ + [475] = {0xFF863464U, 0x00000002U}, /* RGIDSEC_MODID[475]:AXICCI01 */ + [476] = {0xFF863468U, 0x00000002U}, /* RGIDSEC_MODID[476]:AXICCI10 */ + [477] = {0xFF86346CU, 0x00000002U}, /* RGIDSEC_MODID[477]:AXICCI11 */ + [478] = {0xFF863470U, 0x00000002U}, /* RGIDSEC_MODID[478]:AXICCI12 */ + [479] = {0xFF863474U, 0x00000002U}, /* RGIDSEC_MODID[479]:AXICCI13 */ + [480] = {0xFF863478U, 0x00000002U}, /* RGIDSEC_MODID[480]:AXICCI14 */ + [481] = {0xFF86347CU, 0x00000002U}, /* RGIDSEC_MODID[481]:AXICCI15 */ + [482] = {0xFF863480U, 0x00000002U}, /* RGIDSEC_MODID[482]:AXICCI2 */ + [483] = {0xFF863484U, 0x00000002U}, /* RGIDSEC_MODID[483]:AXICCI3 */ + [484] = {0xFF863488U, 0x00000002U}, /* RGIDSEC_MODID[484]:AXICCI4 */ + [485] = {0xFF86348CU, 0x00000002U}, /* RGIDSEC_MODID[485]:AXICCI5 */ + [486] = {0xFF863490U, 0x00000002U}, /* RGIDSEC_MODID[486]:AXICCI6 */ + [487] = {0xFF863494U, 0x00000002U}, /* RGIDSEC_MODID[487]:AXICCI7 */ + [488] = {0xFF863498U, 0x00000002U}, /* RGIDSEC_MODID[488]:AXICCI8 */ + [489] = {0xFF86349CU, 0x00000002U}, /* RGIDSEC_MODID[489]:AXICCI9 */ + [490] = {0xFF8634A0U, 0x00000002U}, /* RGIDSEC_MODID[490]:ECMSTM */ + [491] = {0xFCB83414U, 0x00000002U}, /* RGIDSEC_MODID[491]:DMAI2C0 */ + [492] = {0xFCB83418U, 0x00000002U}, /* RGIDSEC_MODID[492]:DMAI2C1 */ + [493] = {0xFCB8341CU, 0x00000002U}, /* RGIDSEC_MODID[493]:DMAI2C2 */ + [494] = {0xFCB83420U, 0x00000002U}, /* RGIDSEC_MODID[494]:DMAI2C3 */ + [495] = {0xFCB83424U, 0x00000002U}, /* RGIDSEC_MODID[495]:DMAI2C4 */ + [496] = {0xFCB83428U, 0x00000002U}, /* RGIDSEC_MODID[496]:DMAI2C5 */ + [497] = {0xFDDC3400U, 0x00000002U}, /* RGIDSEC_MODID[497]:ARMM */ + [498] = {0xFDDC3404U, 0x00000002U}, /* RGIDSEC_MODID[498]:AXIARNMM */ + [499] = {0xFDDC3408U, 0x00000002U}, /* RGIDSEC_MODID[499]:ARSM0 */ + [500] = {0xFDDC340CU, 0x00000002U}, /* RGIDSEC_MODID[500]:ARSM1 */ + [501] = {0xFDDC3410U, 0x00000002U}, /* RGIDSEC_MODID[501]:ARSM2 */ + [502] = {0xFDDC3414U, 0x00000002U}, /* RGIDSEC_MODID[502]:AXIQOS0 */ + [503] = {0xFDDC3418U, 0x00000002U}, /* RGIDSEC_MODID[503]:AXIQOS1 */ + [504] = {0xFDDC341CU, 0x00000002U}, /* RGIDSEC_MODID[504]:AXIQOS2 */ + [505] = {0xFDDC3420U, 0x00000002U}, /* RGIDSEC_MODID[505]:AXIQOS3 */ + [506] = {0xFDDC3424U, 0x00000002U}, /* RGIDSEC_MODID[506]:AXIQOS4 */ + [507] = {0xFDDC3430U, 0x00000002U}, /* RGIDSEC_MODID[507]:AXIQOS5 */ + [508] = {0xFDDC3434U, 0x00000002U}, /* RGIDSEC_MODID[508]:ARSM3 */ + [509] = {0xFDDC3438U, 0x00000002U}, /* RGIDSEC_MODID[509]:ARSM4 */ + [510] = {0xFDDC343CU, 0x00000002U}, /* RGIDSEC_MODID[510]:ARSM5 */ + [511] = {0xFDDC3440U, 0x00000002U}, /* RGIDSEC_MODID[511]:ARSM6 */ + [512] = {0xFDDC3444U, 0x00000002U}, /* RGIDSEC_MODID[512]:ARSM7 */ + [513] = {0xFDDC3448U, 0x00000002U}, /* RGIDSEC_MODID[513]:ARSM8 */ + [514] = {0xFDDC344CU, 0x00000000U}, /* RGIDSEC_MODID[514]:AXMM0 */ + [515] = {0xFDDC3450U, 0x00000000U}, /* RGIDSEC_MODID[515]:AXMM1 */ + [516] = {0xFDDC3454U, 0x00000002U}, /* RGIDSEC_MODID[516]:AXMMPMON */ + [517] = {0xFDDC3458U, 0x00000002U}, /* RGIDSEC_MODID[517]:CKMMM */ + [518] = {0xFDDC345CU, 0x00000002U}, /* RGIDSEC_MODID[518]:ECMMM */ + [519] = {0xFDDC3468U, 0x00000002U}, /* RGIDSEC_MODID[519]:FBAMM */ + [520] = {0xFDDC346CU, 0x00000002U}, /* RGIDSEC_MODID[520]:IPMMUMM00 */ + [521] = {0xFDDC3470U, 0x00000002U}, /* RGIDSEC_MODID[521]:DBS00 */ + [522] = {0xFDDC3474U, 0x00000002U}, /* RGIDSEC_MODID[522]:DBS01 */ + [523] = {0xFDDC3480U, 0x00000002U}, /* RGIDSEC_MODID[523]:AXCIDBS */ + [524] = {0xFDDC349CU, 0x00000002U}, /* RGIDSEC_MODID[524]:IPMMUMM01 */ + [525] = {0xFDDC34A0U, 0x00000002U}, /* RGIDSEC_MODID[525]:IPMMUMM10 */ + [526] = {0xFDDC34A4U, 0x00000002U}, /* RGIDSEC_MODID[526]:IPMMUMM11 */ + [527] = {0xFDDC34A8U, 0x00000002U}, /* RGIDSEC_MODID[527]:IPMMUMM12 */ + [528] = {0xFDDC34ACU, 0x00000002U}, /* RGIDSEC_MODID[528]:IPMMUMM13 */ + [529] = {0xFDDC34B0U, 0x00000002U}, /* RGIDSEC_MODID[529]:IPMMUMM14 */ + [530] = {0xFDDC34B4U, 0x00000002U}, /* RGIDSEC_MODID[530]:IPMMUMM15 */ + [531] = {0xFDDC34B8U, 0x00000002U}, /* RGIDSEC_MODID[531]:IPMMUMM02 */ + [532] = {0xFDDC34BCU, 0x00000002U}, /* RGIDSEC_MODID[532]:IPMMUMM03 */ + [533] = {0xFDDC34C0U, 0x00000002U}, /* RGIDSEC_MODID[533]:IPMMUMM04 */ + [534] = {0xFDDC34C4U, 0x00000002U}, /* RGIDSEC_MODID[534]:IPMMUMM05 */ + [535] = {0xFDDC34C8U, 0x00000002U}, /* RGIDSEC_MODID[535]:IPMMUMM06 */ + [536] = {0xFDDC34CCU, 0x00000002U}, /* RGIDSEC_MODID[536]:IPMMUMM07 */ + [537] = {0xFDDC34D0U, 0x00000002U}, /* RGIDSEC_MODID[537]:IPMMUMM08 */ + [538] = {0xFDDC34D4U, 0x00000002U}, /* RGIDSEC_MODID[538]:IPMMUMM09 */ + [539] = {0xFCB53400U, 0x00000002U}, /* RGIDSEC_MODID[539]:ARSD00 */ + [540] = {0xFCB53404U, 0x00000002U}, /* RGIDSEC_MODID[540]:ARSD01 */ + [541] = {0xFCB53408U, 0x00000002U}, /* RGIDSEC_MODID[541]:ARSD02 */ + [542] = {0xFCB5340CU, 0x00000002U}, /* RGIDSEC_MODID[542]:ARSD03 */ + [543] = {0xFCB53410U, 0x00000002U}, /* RGIDSEC_MODID[543]:ARSD04 */ + [544] = {0xFCB53414U, 0x00000002U}, /* RGIDSEC_MODID[544]:ARSD05 */ + [545] = {0xFCB53418U, 0x00000002U}, /* RGIDSEC_MODID[545]:ARSD06 */ + [546] = {0xFCB53428U, 0x00000002U}, /* RGIDSEC_MODID[546]:AXIRPC */ + [547] = {0xFCB5342CU, 0x00000002U}, /* RGIDSEC_MODID[547]:AXISDHI0 */ + [548] = {0xFCB53430U, 0x00000002U}, /* RGIDSEC_MODID[548]:ARSD07 */ + [549] = {0xFCB53434U, 0x00000002U}, /* RGIDSEC_MODID[549]:ARSD07 */ + [550] = {0xFCB53438U, 0x00000002U}, /* RGIDSEC_MODID[550]:ARSP00 */ + [551] = {0xFCB5343CU, 0x00000002U}, /* RGIDSEC_MODID[551]:ARSP01 */ + [552] = {0xFCB53440U, 0x00000002U}, /* RGIDSEC_MODID[552]:ARSP02 */ + [553] = {0xFCB53444U, 0x00000002U}, /* RGIDSEC_MODID[553]:ARSP03 */ + [554] = {0xFCB53448U, 0x00000002U}, /* RGIDSEC_MODID[554]:ARSP04 */ + [555] = {0xFCB5344CU, 0x00000002U}, /* RGIDSEC_MODID[555]:ARSP05 */ + [556] = {0xFCB53450U, 0x00000002U}, /* RGIDSEC_MODID[556]:ARSP06 */ + [557] = {0xFCB53454U, 0x00000002U}, /* RGIDSEC_MODID[557]:ARSP07 */ + [558] = {0xFCB53458U, 0x00000002U}, /* RGIDSEC_MODID[558]:ARSP08 */ + [559] = {0xFCB5345CU, 0x00000002U}, /* RGIDSEC_MODID[559]:IPMMUDS001 */ + [560] = {0xFCB53460U, 0x00000002U}, /* RGIDSEC_MODID[560]:CKMPER0 */ + [561] = {0xFCB53464U, 0x00000002U}, /* RGIDSEC_MODID[561]:ECMPER0 */ + [562] = {0xFCB53468U, 0x00000002U}, /* RGIDSEC_MODID[562]:FBAPER0 */ + [563] = {0xFCB5346CU, 0x00000002U}, /* RGIDSEC_MODID[563]:FSO0 */ + [564] = {0xFCB53470U, 0x00000002U}, /* RGIDSEC_MODID[564]:FSO1 */ + [565] = {0xFCB53474U, 0x00000002U}, /* RGIDSEC_MODID[565]:FSO10 */ + [566] = {0xFCB53478U, 0x00000002U}, /* RGIDSEC_MODID[566]:FSO2 */ + [567] = {0xFCB5347CU, 0x00000002U}, /* RGIDSEC_MODID[567]:FSO3 */ + [568] = {0xFCB53480U, 0x00000002U}, /* RGIDSEC_MODID[568]:FSO4 */ + [569] = {0xFCB53484U, 0x00000002U}, /* RGIDSEC_MODID[569]:FSO5 */ + [570] = {0xFCB53488U, 0x00000002U}, /* RGIDSEC_MODID[570]:FSO6 */ + [571] = {0xFCB5348CU, 0x00000002U}, /* RGIDSEC_MODID[571]:FSO7 */ + [572] = {0xFCB53490U, 0x00000002U}, /* RGIDSEC_MODID[572]:FSO8 */ + [573] = {0xFCB53494U, 0x00000002U}, /* RGIDSEC_MODID[573]:FSO9 */ + [574] = {0xFCB5349CU, 0x00000002U}, /* RGIDSEC_MODID[574]:ECMSD0 */ + [575] = {0xFCB534A0U, 0x00000002U}, /* RGIDSEC_MODID[575]:IPMMUDS010 */ + [576] = {0xFCB534A4U, 0x00000002U}, /* RGIDSEC_MODID[576]:IPMMUDS011 */ + [577] = {0xFCB534A8U, 0x00000002U}, /* RGIDSEC_MODID[577]:I2C0 */ + [578] = {0xFCB534ACU, 0x00000002U}, /* RGIDSEC_MODID[578]:I2C1 */ + [579] = {0xFCB534B0U, 0x00000002U}, /* RGIDSEC_MODID[579]:I2C2 */ + [580] = {0xFCB534B4U, 0x00000002U}, /* RGIDSEC_MODID[580]:I2C3 */ + [581] = {0xFCB534B8U, 0x00000002U}, /* RGIDSEC_MODID[581]:I2C4 */ + [582] = {0xFCB534BCU, 0x00000002U}, /* RGIDSEC_MODID[582]:I2C5 */ + [583] = {0xFCB534C0U, 0x00000002U}, /* RGIDSEC_MODID[583]:IPMMUDS012 */ + [584] = {0xFCB534C8U, 0x00000002U}, /* RGIDSEC_MODID[584]:IPMMUDS000 */ + [585] = {0xFCB534CCU, 0x00000002U}, /* RGIDSEC_MODID[585]:IPMMUDS013 */ + [586] = {0xFCB534D0U, 0x00000002U}, /* RGIDSEC_MODID[586]:IPMMUDS014 */ + [587] = {0xFCB534D4U, 0x00000002U}, /* RGIDSEC_MODID[587]:IPMMUDS015 */ + [588] = {0xFCB534D8U, 0x00000002U}, /* RGIDSEC_MODID[588]:IPMMUDS002 */ + [589] = {0xFCB534DCU, 0x00000002U}, /* RGIDSEC_MODID[589]:IPMMUDS003 */ + [590] = {0xFCB534E0U, 0x00000002U}, /* RGIDSEC_MODID[590]:IPMMUDS004 */ + [591] = {0xFCB534E4U, 0x00000002U}, /* RGIDSEC_MODID[591]:IPMMUDS005 */ + [592] = {0xFCB534ECU, 0x00000002U}, /* RGIDSEC_MODID[592]:IPMMUDS006 */ + [593] = {0xFCB534F0U, 0x00000002U}, /* RGIDSEC_MODID[593]:IPMMUDS007 */ + [594] = {0xFCB534F4U, 0x00000002U}, /* RGIDSEC_MODID[594]:SYDM1P */ + [595] = {0xFCB534F8U, 0x00000002U}, /* RGIDSEC_MODID[595]:IPMMUDS008 */ + [596] = {0xFCB534FCU, 0x00000002U}, /* RGIDSEC_MODID[596]:SYDM2P */ + [597] = {0xFCB53500U, 0x00000002U}, /* RGIDSEC_MODID[597]:IPMMUDS009 */ + [598] = {0xFCB53640U, 0x00000002U}, /* RGIDSEC_MODID[598]:SYDM100 */ + [599] = {0xFCB53644U, 0x00000002U}, /* RGIDSEC_MODID[599]:SYDM101 */ + [600] = {0xFCB53648U, 0x00000002U}, /* RGIDSEC_MODID[600]:SYDM110 */ + [601] = {0xFCB5364CU, 0x00000002U}, /* RGIDSEC_MODID[601]:SYDM111 */ + [602] = {0xFCB53650U, 0x00000002U}, /* RGIDSEC_MODID[602]:SYDM112 */ + [603] = {0xFCB53654U, 0x00000002U}, /* RGIDSEC_MODID[603]:SYDM113 */ + [604] = {0xFCB53658U, 0x00000002U}, /* RGIDSEC_MODID[604]:SYDM114 */ + [605] = {0xFCB5365CU, 0x00000002U}, /* RGIDSEC_MODID[605]:SYDM115 */ + [606] = {0xFCB53660U, 0x00000002U}, /* RGIDSEC_MODID[606]:SYDM102 */ + [607] = {0xFCB53664U, 0x00000002U}, /* RGIDSEC_MODID[607]:SYDM103 */ + [608] = {0xFCB53668U, 0x00000002U}, /* RGIDSEC_MODID[608]:SYDM104 */ + [609] = {0xFCB5366CU, 0x00000002U}, /* RGIDSEC_MODID[609]:SYDM105 */ + [610] = {0xFCB53670U, 0x00000002U}, /* RGIDSEC_MODID[610]:SYDM106 */ + [611] = {0xFCB53674U, 0x00000002U}, /* RGIDSEC_MODID[611]:SYDM107 */ + [612] = {0xFCB53678U, 0x00000002U}, /* RGIDSEC_MODID[612]:SYDM108 */ + [613] = {0xFCB5367CU, 0x00000002U}, /* RGIDSEC_MODID[613]:SYDM109 */ + [614] = {0xFCB53680U, 0x00000002U}, /* RGIDSEC_MODID[614]:SYDM200 */ + [615] = {0xFCB53684U, 0x00000002U}, /* RGIDSEC_MODID[615]:SYDM201 */ + [616] = {0xFCB53688U, 0x00000002U}, /* RGIDSEC_MODID[616]:SYDM210 */ + [617] = {0xFCB5368CU, 0x00000002U}, /* RGIDSEC_MODID[617]:SYDM211 */ + [618] = {0xFCB53690U, 0x00000002U}, /* RGIDSEC_MODID[618]:SYDM212 */ + [619] = {0xFCB53694U, 0x00000002U}, /* RGIDSEC_MODID[619]:SYDM213 */ + [620] = {0xFCB53698U, 0x00000002U}, /* RGIDSEC_MODID[620]:SYDM214 */ + [621] = {0xFCB5369CU, 0x00000002U}, /* RGIDSEC_MODID[621]:SYDM215 */ + [622] = {0xFCB536A0U, 0x00000002U}, /* RGIDSEC_MODID[622]:SYDM202 */ + [623] = {0xFCB536A4U, 0x00000002U}, /* RGIDSEC_MODID[623]:SYDM203 */ + [624] = {0xFCB536A8U, 0x00000002U}, /* RGIDSEC_MODID[624]:SYDM204 */ + [625] = {0xFCB536ACU, 0x00000002U}, /* RGIDSEC_MODID[625]:SYDM205 */ + [626] = {0xFCB536B0U, 0x00000002U}, /* RGIDSEC_MODID[626]:SYDM206 */ + [627] = {0xFCB536B4U, 0x00000002U}, /* RGIDSEC_MODID[627]:SYDM207 */ + [628] = {0xFCB536B8U, 0x00000002U}, /* RGIDSEC_MODID[628]:SYDM208 */ + [629] = {0xFCB536BCU, 0x00000002U}, /* RGIDSEC_MODID[629]:SYDM209 */ + [631] = {0xFDDB9624U, 0x00000001U}, /* RGIDSEC_MODID[630]:ARCC */ + [630] = {0xFDDB9638U, 0x00000001U}, /* RGIDSEC_MODID[631]:ARRTRAM */ + [632] = {0xFCB53424U, 0x00000002U}, /* RGIDSEC_MODID[632]:RSV0 */ +}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +/* T.B.D. */ +#pragma ghs section rodata=".rgid_axi_tbl" +const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[] = { + [0] = {0xFD482010U, 0x0000003FU}, /* RGIDR_MODID[4]:ARRT01 */ + [1] = {0xFD482014U, 0x0000003FU}, /* RGIDR_MODID[5]:ARRT02 */ + [2] = {0xFDA02048U, 0x0000003FU}, /* RGIDR_MODID[45]:ARS01 */ + [3] = {0xFDA0204CU, 0x0000003FU}, /* RGIDR_MODID[46]:ARS02 */ + [4] = {0xFCB62028U, 0x0000003FU}, /* RGIDR_MODID[93]:ARSP31 */ + [5] = {0xFCB6202CU, 0x0000003FU}, /* RGIDR_MODID[94]:ARSP32 */ + [6] = {0xFCB92004U, 0x0000003FU}, /* RGIDR_MODID[106]:ARSP41 */ + [7] = {0xFCB92008U, 0x0000003FU}, /* RGIDR_MODID[107]:ARSP42 */ + [8] = {0xFCF82140U, 0x0000003FU}, /* RGIDR_MODID[210]:ARHC1 */ + [9] = {0xFCF82144U, 0x0000003FU}, /* RGIDR_MODID[211]:ARHC2 */ + [10] = {0xFDC22004U, 0x0000003FU}, /* RGIDR_MODID[226]:ARRC1 */ + [11] = {0xFDC22008U, 0x0000003FU}, /* RGIDR_MODID[227]:ARRC2 */ + [12] = {0xFD442060U, 0x0000003FU}, /* RGIDR_MODID[268]:ARRD1 */ + [13] = {0xFD442064U, 0x0000003FU}, /* RGIDR_MODID[269]:ARRD2 */ + [14] = {0xFD442084U, 0x0000003FU}, /* RGIDR_MODID[277]:ARRT1 */ + [15] = {0xFD442088U, 0x0000003FU}, /* RGIDR_MODID[278]:ARRT2 */ + [18] = {0xFF862004U, 0x0000003FU}, /* RGIDR_MODID[452]:ARSC1 */ + [19] = {0xFF862008U, 0x0000003FU}, /* RGIDR_MODID[453]:ARSC2 */ + [16] = {0xFF862028U, 0x0000003FU}, /* RGIDR_MODID[461]:ARSTM1 */ + [17] = {0xFF862038U, 0x0000003FU}, /* RGIDR_MODID[464]:ARSTM2 */ + [20] = {0xFDDC2004U, 0x0000003FU}, /* RGIDR_MODID[498]:AXIARNMM */ + [21] = {0xFDDC200CU, 0x0000003FU}, /* RGIDR_MODID[500]:ARSM1 */ + [22] = {0xFDDC2010U, 0x0000003FU}, /* RGIDR_MODID[501]:ARSM2 */ + [23] = {0xFCB52004U, 0x0000003FU}, /* RGIDR_MODID[540]:ARSD01 */ + [24] = {0xFCB52008U, 0x0000003FU}, /* RGIDR_MODID[541]:ARSD02 */ + [25] = {0xFCB5203CU, 0x0000003FU}, /* RGIDR_MODID[551]:ARSP01 */ + [26] = {0xFCB52040U, 0x0000003FU}, /* RGIDR_MODID[552]:ARSP02 */ + [27] = {0xFD482410U, 0x00000000U}, /* RGIDW_MODID[4]:ARRT01 */ + [28] = {0xFD482414U, 0x00000000U}, /* RGIDW_MODID[5]:ARRT02 */ + [29] = {0xFDA02448U, 0x00000000U}, /* RGIDW_MODID[45]:ARS01 */ + [30] = {0xFDA0244CU, 0x00000000U}, /* RGIDW_MODID[46]:ARS02 */ + [31] = {0xFCB62428U, 0x00000000U}, /* RGIDW_MODID[93]:ARSP31 */ + [32] = {0xFCB6242CU, 0x00000000U}, /* RGIDW_MODID[94]:ARSP32 */ + [33] = {0xFCB92404U, 0x00000000U}, /* RGIDW_MODID[106]:ARSP41 */ + [34] = {0xFCB92408U, 0x00000000U}, /* RGIDW_MODID[107]:ARSP42 */ + [35] = {0xFCF82540U, 0x00000000U}, /* RGIDW_MODID[210]:ARHC1 */ + [36] = {0xFCF82544U, 0x00000000U}, /* RGIDW_MODID[211]:ARHC2 */ + [37] = {0xFDC22404U, 0x00000000U}, /* RGIDW_MODID[226]:ARRC1 */ + [38] = {0xFDC22408U, 0x00000011U}, /* RGIDW_MODID[227]:ARRC2 */ + [39] = {0xFD442460U, 0x00000000U}, /* RGIDW_MODID[268]:ARRD1 */ + [40] = {0xFD442464U, 0x00000000U}, /* RGIDW_MODID[269]:ARRD2 */ + [41] = {0xFD442484U, 0x00000000U}, /* RGIDW_MODID[277]:ARRT1 */ + [42] = {0xFD442488U, 0x00000000U}, /* RGIDW_MODID[278]:ARRT2 */ + [45] = {0xFF862404U, 0x00000000U}, /* RGIDW_MODID[452]:ARSC1 */ + [46] = {0xFF862408U, 0x00000000U}, /* RGIDW_MODID[453]:ARSC2 */ + [43] = {0xFF862428U, 0x00000000U}, /* RGIDW_MODID[461]:ARSTM1 */ + [44] = {0xFF862438U, 0x00000000U}, /* RGIDW_MODID[464]:ARSTM2 */ + [47] = {0xFDDC2404U, 0x00000000U}, /* RGIDW_MODID[498]:AXIARNMM */ + [48] = {0xFDDC240CU, 0x00000000U}, /* RGIDW_MODID[500]:ARSM1 */ + [49] = {0xFDDC2410U, 0x00000000U}, /* RGIDW_MODID[501]:ARSM2 */ + [50] = {0xFCB52404U, 0x00000000U}, /* RGIDW_MODID[540]:ARSD01 */ + [51] = {0xFCB52408U, 0x00000000U}, /* RGIDW_MODID[541]:ARSD02 */ + [52] = {0xFCB5243CU, 0x00000000U}, /* RGIDW_MODID[551]:ARSP01 */ + [53] = {0xFCB52440U, 0x00000000U}, /* RGIDW_MODID[552]:ARSP02 */ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +const uint32_t g_rgid_rtdma_setting_value[RTDMA_MODULE_MAX][RTDMA_CH_MAX][2U] = { + {/* Module0 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, + {/* Module1 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, + {/* Module2 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, + {/* Module3 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + } +}; + +const uint32_t g_rgid_sysdma_setting_value[SYSDMA_MODULE_MAX][SYSDMA_CH_MAX][2U] = { + {/* Module0 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {SYSDMA_EN, RGID_2}, /* CH0 */ + [1] = {SYSDMA_EN, RGID_2}, /* CH1 */ + [2] = {SYSDMA_EN, RGID_2}, /* CH2 */ + [3] = {SYSDMA_EN, RGID_2}, /* CH3 */ + [4] = {SYSDMA_EN, RGID_2}, /* CH4 */ + [5] = {SYSDMA_EN, RGID_2}, /* CH5 */ + [6] = {SYSDMA_EN, RGID_2}, /* CH6 */ + [7] = {SYSDMA_EN, RGID_2}, /* CH7 */ + [8] = {SYSDMA_EN, RGID_2}, /* CH8 */ + [9] = {SYSDMA_EN, RGID_2}, /* CH9 */ + [10] = {SYSDMA_EN, RGID_2}, /* CH10 */ + [11] = {SYSDMA_EN, RGID_2}, /* CH11 */ + [12] = {SYSDMA_EN, RGID_2}, /* CH12 */ + [13] = {SYSDMA_EN, RGID_2}, /* CH13 */ + [14] = {SYSDMA_EN, RGID_2}, /* CH14 */ + [15] = {SYSDMA_EN, RGID_2} /* CH15 */ + }, + {/* Module1 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {SYSDMA_EN, RGID_2}, /* CH0 */ + [1] = {SYSDMA_EN, RGID_2}, /* CH1 */ + [2] = {SYSDMA_EN, RGID_2}, /* CH2 */ + [3] = {SYSDMA_EN, RGID_2}, /* CH3 */ + [4] = {SYSDMA_EN, RGID_2}, /* CH4 */ + [5] = {SYSDMA_EN, RGID_2}, /* CH5 */ + [6] = {SYSDMA_EN, RGID_2}, /* CH6 */ + [7] = {SYSDMA_EN, RGID_2}, /* CH7 */ + [8] = {SYSDMA_EN, RGID_2}, /* CH8 */ + [9] = {SYSDMA_EN, RGID_2}, /* CH9 */ + [10] = {SYSDMA_EN, RGID_2}, /* CH10 */ + [11] = {SYSDMA_EN, RGID_2}, /* CH11 */ + [12] = {SYSDMA_EN, RGID_2}, /* CH12 */ + [13] = {SYSDMA_EN, RGID_2}, /* CH13 */ + [14] = {SYSDMA_EN, RGID_2}, /* CH14 */ + [15] = {SYSDMA_EN, RGID_2} /* CH15 */ + }, +}; + +/* When V4H, this table is used as RT-VRAM0. */ +const RTRAM_PROTECTION_STRUCTUR g_rtsram_protection_table[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTSRAM_ICUMX_IPL_AREA] = {NOT_USED_VALUE, {0x0000FFCAU, 0x0000FFEEU}}, /* not used for address value */ + [RTSRAM_ICUMX_FW_AREA] = {0xEB240000U, {0x0004FFEEU, 0x0004FFEEU}}, + [2] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [3] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* this table is temporary setting for RT-VRAM protection */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table_1[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM_BLANK_AREA] = {NOT_USED_VALUE, {0x0000FFF8U, 0x0000FFF8U}}, /* not used for address value */ + [RTVRAM_EXTEND_CACHE_AREA] = {0xE2010000U, {0x0000BFF8U, 0x0000BFF8U}}, + [RTVRAM_RTOS_AREA] = {0xE2100000U, {0x0000FFD9U, 0x0000FFD9U}}, + [3] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* this table is finaly setting for RT-VRAM protection */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table_2[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM_BLANK_AREA] = {NOT_USED_VALUE, {0x0000FFF8U, 0x0000FFF8U}}, /* not used for address value */ + [RTVRAM_EXTEND_CACHE_AREA] = {0xE2010000U, {0x0000BFFFU, 0x0000BFFFU}}, + [RTVRAM_RTOS_AREA] = {0xE2100000U, {0x0000FFD9U, 0x0000FFD9U}}, + [3] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX] = { + /* access Secure */ + /* address R | W R|W */ + [SYSTEM_RAM_ALL] = {NOT_USED_VALUE, {0xFFD0FFD0U, 0x00000000U}}, /* not used for address value */ + [1] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [2] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [3] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX] = { + /* access secure */ + /* address R | W R|W */ + [RTVRAM_EXTEND_AREA] = {NOT_USED_VALUE, {0xBFFFBFFFU, 0x00000000U}}, /* not used for address value */ + [SDRAM_BLANK_AREA] = {0x0401C00000U, {0xFFC0FFC0U, 0x00000000U}}, + [SDRAM_PROTECT_AREA] = {0x0406400000U, {0xFFC8FFC8U, 0x00000000U}}, + [SDRAM_PUBLIC_AREA] = {0x0407E00000U, {0xFFC0FFC0U, 0x00000000U}}, + [4] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [16] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [17] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [18] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [19] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [20] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [21] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [22] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [23] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [24] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [25] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [26] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [27] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [28] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [29] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [30] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [31] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [32] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [33] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [34] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [35] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [36] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [37] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [38] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [39] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [40] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [41] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [42] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [43] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [44] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [45] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [46] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [47] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [48] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [49] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [50] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [51] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [52] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [53] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [54] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [55] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [56] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [57] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [58] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [59] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [60] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [61] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [62] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [63] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4h.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4h.c new file mode 100644 index 0000000..6aa72f0 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4h.c @@ -0,0 +1,4084 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table + ******************************************************************************/ +/****************************************************************************** + * @file cnf_tbl.c + * - Version : 0.11 + * @brief Configuration table for V4H. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 23.05.2022 0.02 Integration of S4 and V4H + * Renamed from conf_tbl.c to cnf_tbl_v4h.c. + * : 22.11.2022 0.03 Removed QoS configuration table + * : 13.11.2023 0.04 Added setting table for CCI MPU GID register. + * : 11.01.2024 0.05 Updated writing privilege to System RAM. + * Fixed setting value of read/write permissions + * for RT-VRAM1 area2. + * Update Region ID settings. + * The divided areas of SDRAM have been changed. + * : 11.07.2024 0.06 Updated AXI timeout setting value. + * Removed FDT_PAP in g_fdt_tbl. + * : 29.08.2024 0.07 Updated Region ID and RAM protection setting + * for QNX. + * : 05.12.2024 0.08 Update RAM protection settings for ICCOM + * memory area (SDRAM Area5). + * Update Region ID settings for VSPD and VSPX. + * Update Region ID settings for IPMMU. + * : 16.12.2024 0.09 Updated Region ID setting. + * Updated Region ID setting and RAM protection + * setting for booting CR52 3 cores. + * Updated AXI timeout setting value. + * Added IMP Region ID table. + * Added IPMMU Region ID table. + * : 17.03.2025 0.10 Updated AXI timeout setting value. + * : 26.05.2025 0.11 Updated RAM protection settings for + * protection area. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#define RTDMA_EN (0x00000002U) +#define SYSDMA_EN (0x00003FF4U) + +#pragma ghs section rodata=".qosbw_tbl" +/* not used for V4H */ +const QOS_SETTING_TABLE g_qosbw_tbl[] = {0}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".qoswt_tbl" +/* not used for V4H */ +const QOS_SETTING_TABLE g_qoswt_tbl[] = {0}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_m_tbl" +const REGION_ID_SETTING_TABLE g_rgid_m_tbl[] = { + [0] = {0xFCF81000U, 0x00000002U}, /* RGIDM_MODID[0]:PCI0 */ + [1] = {0xFCF81020U, 0x00000002U}, /* RGIDM_MODID[1]:PCI1 */ + [2] = {0xFCF81024U, 0x00000002U}, /* RGIDM_MODID[2]:PCI2 */ + [3] = {0xFCF81034U, 0x00000002U}, /* RGIDM_MODID[3]:PCI3 */ + [4] = {0xFCF81010U, 0x00000002U}, /* RGIDM_MODID[4]:AVB0 */ + [5] = {0xFCF81014U, 0x00000001U}, /* RGIDM_MODID[5]:AVB1 */ + [6] = {0xFCF81018U, 0x00000001U}, /* RGIDM_MODID[6]:AVB2 */ + [7] = {0xFCF81040U, 0x00000002U}, /* RGIDM_MODID[7]:TSN */ + [8] = {0xFDC21004U, 0x00000000U}, /* RGIDM_MODID[8]:CR0 */ + [9] = {0xFDC2100CU, 0x00000000U}, /* RGIDM_MODID[9]:DCLS_ICUMX */ + [10] = {0xFDC21010U, 0x00000000U}, /* RGIDM_MODID[10]:ICUMX */ + [11] = {0xFDC21014U, 0x00000000U}, /* RGIDM_MODID[11]:SDMAC_ICUMX */ + [12] = {0xFD441018U, 0x00000001U}, /* RGIDM_MODID[12]:CR52SS0 */ + [13] = {0xFD44105CU, 0x00000001U}, /* RGIDM_MODID[13]:CR52SS1 */ + [14] = {0xFD441060U, 0x00000006U}, /* RGIDM_MODID[14]:CR52SS2 */ + [15] = {0xFD44101CU, 0x00000003U}, /* RGIDM_MODID[15]:CSD */ + [16] = {0xFD441024U, 0x00000002U}, /* RGIDM_MODID[16]:INTAP0 */ + [17] = {0xFC861018U, 0x00000002U}, /* RGIDM_MODID[17]:FBABUSTOP0 */ + [18] = {0xFC86101CU, 0x00000002U}, /* RGIDM_MODID[18]:FBABUSTOP1 */ + [19] = {0xFCB51020U, 0x00000002U}, /* RGIDM_MODID[19]:SDHI0 */ + [20] = {0xFCB51010U, 0x00000001U}, /* RGIDM_MODID[20]:FRAY */ + [21] = {0xFCB51014U, 0x00000002U}, /* RGIDM_MODID[21]:IPC */ + [22] = {0xFC811000U, 0x00000002U}, /* RGIDM_MODID[22]:AXMM2AXSTM */ + [23] = {0xFC811004U, 0x00000003U}, /* RGIDM_MODID[23]:CSDE0 */ + [24] = {0xFC811008U, 0x00000003U}, /* RGIDM_MODID[24]:CSDE1 */ + [25] = {0xFC881004U, 0x00000002U}, /* RGIDM_MODID[25]:FBABUSIR0 */ + [26] = {0xFC881008U, 0x00000002U}, /* RGIDM_MODID[26]:FBABUSIR1 */ + [27] = {0xFC88100CU, 0x00000002U}, /* RGIDM_MODID[27]:FBABUSIR2 */ + [28] = {0xFC881010U, 0x00000002U}, /* RGIDM_MODID[28]:FBABUSIR3 */ + [29] = {0xFC881014U, 0x00000002U}, /* RGIDM_MODID[29]:FBABUSIR4 */ + [30] = {0xFC011014U, 0x00000002U}, /* RGIDM_MODID[30]:RGX0 */ + [31] = {0xFC681004U, 0x00000002U}, /* RGIDM_MODID[31]:FBABUSVC */ + [32] = {0xFC681008U, 0x00000005U}, /* RGIDM_MODID[32]:FCPCS */ + [33] = {0xFC681010U, 0x00000002U}, /* RGIDM_MODID[33]:IMR00 */ + [34] = {0xFC681014U, 0x00000002U}, /* RGIDM_MODID[34]:IMR01 */ + [35] = {0xFC681024U, 0x00000002U}, /* RGIDM_MODID[35]:IMR10 */ + [36] = {0xFC681028U, 0x00000002U}, /* RGIDM_MODID[36]:IMR11 */ + [37] = {0xFC68100CU, 0x00000002U}, /* RGIDM_MODID[37]:IMR20 */ + [38] = {0xFC681018U, 0x00000002U}, /* RGIDM_MODID[38]:IMR21 */ + [39] = {0xFC681040U, 0x00000002U}, /* RGIDM_MODID[39]:IMS0 */ + [40] = {0xFC681044U, 0x00000002U}, /* RGIDM_MODID[40]:IMS1 */ + [41] = {0xFC681048U, 0x00000005U}, /* RGIDM_MODID[41]:IV1ES */ + [42] = {0xFEBE1000U, 0x00000002U}, /* RGIDM_MODID[42]:DSITLINK0 */ + [43] = {0xFEBE1004U, 0x00000002U}, /* RGIDM_MODID[43]:DSTLINK1 */ + [44] = {0xFEBE1008U, 0x00000002U}, /* RGIDM_MODID[44]:FBABUSVIO */ + [45] = {0xFEBE1014U, 0x00000002U}, /* RGIDM_MODID[45]:FCPVD0 */ + [46] = {0xFEBE1018U, 0x00000002U}, /* RGIDM_MODID[46]:FCPVD1 */ + [47] = {0xFEBE101CU, 0x00000002U}, /* RGIDM_MODID[47]:FCPVX0 */ + [48] = {0xFEBE1020U, 0x00000002U}, /* RGIDM_MODID[48]:FCPVX1 */ + [49] = {0xFEBF1020U, 0x00000002U}, /* RGIDM_MODID[49]:ISP00 */ + [50] = {0xFEBF1024U, 0x00000002U}, /* RGIDM_MODID[50]:ISP01 */ + [51] = {0xFEBF1000U, 0x00000002U}, /* RGIDM_MODID[51]:ISP02 */ + [52] = {0xFEBF1004U, 0x00000002U}, /* RGIDM_MODID[52]:ISP03 */ + [53] = {0xFEBF1008U, 0x00000002U}, /* RGIDM_MODID[53]:ISP04 */ + [54] = {0xFEBF1028U, 0x00000002U}, /* RGIDM_MODID[54]:ISP10 */ + [55] = {0xFEBF102CU, 0x00000002U}, /* RGIDM_MODID[55]:ISP11 */ + [56] = {0xFEBF1044U, 0x00000002U}, /* RGIDM_MODID[56]:ISP12 */ + [57] = {0xFEBF104CU, 0x00000002U}, /* RGIDM_MODID[57]:ISP13 */ + [58] = {0xFEBF1050U, 0x00000002U}, /* RGIDM_MODID[58]:ISP14 */ + [59] = {0xFEBF1010U, 0x00000002U}, /* RGIDM_MODID[59]:VIN0 */ + [60] = {0xFEBF1014U, 0x00000002U}, /* RGIDM_MODID[60]:VIN1 */ + [61] = {0xFC311004U, 0x00000002U}, /* RGIDM_MODID[61]:FBABUSVIP0 */ + [62] = {0xFC311010U, 0x00000002U}, /* RGIDM_MODID[62]:SMPO */ + [63] = {0xFC311018U, 0x00000002U}, /* RGIDM_MODID[63]:SMPS */ + [64] = {0xFC31101CU, 0x00000002U}, /* RGIDM_MODID[64]:UMFL */ + [65] = {0xFC341018U, 0x00000002U}, /* RGIDM_MODID[65]:PAP */ + [66] = {0xFC341028U, 0x00000002U}, /* RGIDM_MODID[66]:FBABUSVIP1 */ + [67] = {0xFC401000U, 0x00000002U}, /* RGIDM_MODID[67]:DSP00 */ + [68] = {0xFC401004U, 0x00000002U}, /* RGIDM_MODID[68]:DSP01 */ + [69] = {0xFC401008U, 0x00000002U}, /* RGIDM_MODID[69]:DSP10 */ + [70] = {0xFC40100CU, 0x00000002U}, /* RGIDM_MODID[70]:DSP11 */ + [71] = {0xFC401010U, 0x00000002U}, /* RGIDM_MODID[71]:DSP20 */ + [72] = {0xFC401014U, 0x00000002U}, /* RGIDM_MODID[72]:DSP21 */ + [73] = {0xFC401018U, 0x00000002U}, /* RGIDM_MODID[73]:DSP30 */ + [74] = {0xFC40101CU, 0x00000002U}, /* RGIDM_MODID[74]:DSP31 */ + [75] = {0xFDDBF500U, 0x0000000EU}, /* RGIDM_MODID[75]:VRAM_R */ + [76] = {0xFDDBF504U, 0x0000000EU}, /* RGIDM_MODID[76]:VRAM_W */ +}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_r_tbl" +const REGION_ID_SETTING_TABLE g_rgid_r_tbl[] = { + [0] = {0xFD482000U, 0x0000000FU}, /* RGIDR_MODID[0]:ARMGC0*/ + [1] = {0xFD482004U, 0x0000000FU}, /* RGIDR_MODID[1]:ARMGC1*/ + [2] = {0xFD482008U, 0x00000000U}, /* RGIDR_MODID[2]:ARMGC2*/ + [3] = {0xFD48200CU, 0x0000000FU}, /* RGIDR_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDR_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDR_MODID[5]:ARRT02*/ + [4] = {0xFD482018U, 0x0000000FU}, /* RGIDR_MODID[6]:ARRT03*/ + [5] = {0xFD48201CU, 0x0000000FU}, /* RGIDR_MODID[7]:ARRT04*/ + [6] = {0xFD482020U, 0x0000000FU}, /* RGIDR_MODID[8]:ARRT05*/ + [7] = {0xFD482024U, 0x0000000FU}, /* RGIDR_MODID[9]:ARRT06*/ + [8] = {0xFD482028U, 0x0000000FU}, /* RGIDR_MODID[10]:ARRT07*/ + [9] = {0xFD48202CU, 0x00000000U}, /* RGIDR_MODID[11]:ARRT08*/ + [10] = {0xFD482030U, 0x00000001U}, /* RGIDR_MODID[12]:LIFEC0*/ + [11] = {0xFD482034U, 0x0000000EU}, /* RGIDR_MODID[13]:SWDT*/ + [12] = {0xFD482038U, 0x0000006EU}, /* RGIDR_MODID[14]:TMU0*/ + [13] = {0xFD48203CU, 0x0000000EU}, /* RGIDR_MODID[15]:WDT*/ + [14] = {0xFD482040U, 0x0000000EU}, /* RGIDR_MODID[16]:WWDT0*/ + [15] = {0xFD482044U, 0x0000000EU}, /* RGIDR_MODID[17]:WWDT1*/ + [16] = {0xFD482048U, 0x0000000EU}, /* RGIDR_MODID[18]:WWDT2*/ + [17] = {0xFD48204CU, 0x0000000EU}, /* RGIDR_MODID[19]:WWDT3*/ + [18] = {0xFD482050U, 0x0000000EU}, /* RGIDR_MODID[20]:WWDT4*/ + [19] = {0xFD482054U, 0x0000000EU}, /* RGIDR_MODID[21]:WWDT5*/ + [20] = {0xFD482058U, 0x0000000EU}, /* RGIDR_MODID[22]:WWDT6*/ + [21] = {0xFD482068U, 0x0000000FU}, /* RGIDR_MODID[23]:ECMRT3*/ + [22] = {0xFDA02000U, 0x0000000EU}, /* RGIDR_MODID[24]:ADVFSC*/ + [23] = {0xFDA02004U, 0x0000000FU}, /* RGIDR_MODID[25]:APMU0*/ + [24] = {0xFDA02008U, 0x00000002U}, /* RGIDR_MODID[26]:APMU1*/ + [25] = {0xFDA0200CU, 0x00000000U}, /* RGIDR_MODID[27]:APMU10*/ + [26] = {0xFDA02010U, 0x00000000U}, /* RGIDR_MODID[28]:APMU11*/ + [27] = {0xFDA02014U, 0x00000000U}, /* RGIDR_MODID[29]:APMU12*/ + [28] = {0xFDA02018U, 0x00000000U}, /* RGIDR_MODID[30]:APMU13*/ + [29] = {0xFDA0201CU, 0x00000000U}, /* RGIDR_MODID[31]:APMU14*/ + [30] = {0xFDA02020U, 0x00000000U}, /* RGIDR_MODID[32]:APMU15*/ + [31] = {0xFDA02024U, 0x00000004U}, /* RGIDR_MODID[33]:APMU2*/ + [32] = {0xFDA02028U, 0x00000004U}, /* RGIDR_MODID[34]:APMU3*/ + [33] = {0xFDA0202CU, 0x00000000U}, /* RGIDR_MODID[35]:APMU4*/ + [34] = {0xFDA02030U, 0x00000000U}, /* RGIDR_MODID[36]:APMU5*/ + [35] = {0xFDA02034U, 0x00000000U}, /* RGIDR_MODID[37]:APMU6*/ + [36] = {0xFDA02038U, 0x00000000U}, /* RGIDR_MODID[38]:APMU7*/ + [37] = {0xFDA0203CU, 0x00000000U}, /* RGIDR_MODID[39]:APMU8*/ + [38] = {0xFDA02040U, 0x00000000U}, /* RGIDR_MODID[40]:APMU9*/ + [39] = {0xFDA02044U, 0x0000000FU}, /* RGIDR_MODID[41]:ARS00*/ + /* After setting */ /* RGIDR_MODID[42]:ARS01*/ + /* After setting */ /* RGIDR_MODID[43]:ARS02*/ + [40] = {0xFDA02050U, 0x0000000FU}, /* RGIDR_MODID[44]:ARS03*/ + [41] = {0xFDA02054U, 0x0000000FU}, /* RGIDR_MODID[45]:ARS04*/ + [42] = {0xFDA02058U, 0x0000000FU}, /* RGIDR_MODID[46]:ARS05*/ + [43] = {0xFDA0205CU, 0x0000000FU}, /* RGIDR_MODID[47]:ARS06*/ + [44] = {0xFDA02060U, 0x0000000FU}, /* RGIDR_MODID[48]:ARS07*/ + [45] = {0xFDA02064U, 0x00000000U}, /* RGIDR_MODID[49]:ARS08*/ + [46] = {0xFDA02068U, 0x0000000EU}, /* RGIDR_MODID[50]:CMT0*/ + [47] = {0xFDA0206CU, 0x0000000EU}, /* RGIDR_MODID[51]:CMT1*/ + [48] = {0xFDA02070U, 0x0000000EU}, /* RGIDR_MODID[52]:CMT2*/ + [49] = {0xFDA02074U, 0x0000000EU}, /* RGIDR_MODID[53]:CMT3*/ + [50] = {0xFDA02078U, 0x0000000AU}, /* RGIDR_MODID[54]:CKM*/ + [51] = {0xFDA0207CU, 0x0000000EU}, /* RGIDR_MODID[55]:DBE*/ + [52] = {0xFDA02080U, 0x0000000EU}, /* RGIDR_MODID[56]:IRQC*/ + [53] = {0xFDA02084U, 0x0000000FU}, /* RGIDR_MODID[57]:ECMPS0*/ + [54] = {0xFDA02088U, 0x0000000BU}, /* RGIDR_MODID[58]:OTP0*/ + [55] = {0xFDA0208CU, 0x0000000FU}, /* RGIDR_MODID[59]:OTP1*/ + [56] = {0xFDA0209CU, 0x0000000EU}, /* RGIDR_MODID[60]:SCMT*/ + [57] = {0xFDA020A8U, 0x0000004EU}, /* RGIDR_MODID[61]:TSC1*/ + [58] = {0xFDA020ACU, 0x0000004EU}, /* RGIDR_MODID[62]:TSC2*/ + [59] = {0xFDA020B0U, 0x0000004EU}, /* RGIDR_MODID[63]:TSC3*/ + [60] = {0xFDA020B4U, 0x0000004EU}, /* RGIDR_MODID[64]:TSC4*/ + [61] = {0xFDA020B8U, 0x00000006U}, /* RGIDR_MODID[65]:UCMT*/ + [62] = {0xFDA02100U, 0x0000006FU}, /* RGIDR_MODID[66]:CPG0*/ + [63] = {0xFDA02104U, 0x0000000AU}, /* RGIDR_MODID[67]:CPG1*/ + [64] = {0xFDA02108U, 0x0000004EU}, /* RGIDR_MODID[68]:CPG2*/ + [65] = {0xFDA0210CU, 0x00000028U}, /* RGIDR_MODID[69]:CPG3*/ + [66] = {0xFDA02110U, 0x0000006FU}, /* RGIDR_MODID[70]:PFC00*/ + [67] = {0xFDA02114U, 0x0000000AU}, /* RGIDR_MODID[71]:PFC01*/ + [68] = {0xFDA02118U, 0x0000004EU}, /* RGIDR_MODID[72]:PFC02*/ + [69] = {0xFDA0211CU, 0x00000028U}, /* RGIDR_MODID[73]:PFC03*/ + [70] = {0xFDA02120U, 0x0000006FU}, /* RGIDR_MODID[74]:PFC10*/ + [71] = {0xFDA02124U, 0x0000000AU}, /* RGIDR_MODID[75]:PFC11*/ + [72] = {0xFDA02128U, 0x0000004EU}, /* RGIDR_MODID[76]:PFC12*/ + [73] = {0xFDA0212CU, 0x00000028U}, /* RGIDR_MODID[77]:PFC13*/ + [74] = {0xFDA02130U, 0x0000006FU}, /* RGIDR_MODID[78]:PFC20*/ + [75] = {0xFDA02134U, 0x0000000AU}, /* RGIDR_MODID[79]:PFC21*/ + [76] = {0xFDA02138U, 0x0000004EU}, /* RGIDR_MODID[80]:PFC22*/ + [77] = {0xFDA0213CU, 0x00000028U}, /* RGIDR_MODID[81]:PFC23*/ + [78] = {0xFDA02140U, 0x0000006FU}, /* RGIDR_MODID[82]:PFC30*/ + [79] = {0xFDA02144U, 0x0000000AU}, /* RGIDR_MODID[83]:PFC31*/ + [80] = {0xFDA02148U, 0x0000004EU}, /* RGIDR_MODID[84]:PFC32*/ + [81] = {0xFDA0214CU, 0x00000028U}, /* RGIDR_MODID[85]:PFC33*/ + [82] = {0xFDA02150U, 0x0000006FU}, /* RGIDR_MODID[86]:PFCS0*/ + [83] = {0xFDA02154U, 0x0000000AU}, /* RGIDR_MODID[87]:PFCS1*/ + [84] = {0xFDA02158U, 0x0000004EU}, /* RGIDR_MODID[88]:PFCS2*/ + [85] = {0xFDA0215CU, 0x00000028U}, /* RGIDR_MODID[89]:PFCS3*/ + [86] = {0xFDA02160U, 0x0000006FU}, /* RGIDR_MODID[90]:RESET0*/ + [87] = {0xFDA02164U, 0x0000000AU}, /* RGIDR_MODID[91]:RESET1*/ + [88] = {0xFDA02168U, 0x0000004EU}, /* RGIDR_MODID[92]:RESET2*/ + [89] = {0xFDA0216CU, 0x00000028U}, /* RGIDR_MODID[93]:RESET3*/ + [90] = {0xFDA02170U, 0x0000006FU}, /* RGIDR_MODID[94]:SYS0*/ + [91] = {0xFDA02174U, 0x0000000AU}, /* RGIDR_MODID[95]:SYS1*/ + [92] = {0xFDA02178U, 0x0000004EU}, /* RGIDR_MODID[96]:SYS2*/ + [93] = {0xFDA0217CU, 0x00000028U}, /* RGIDR_MODID[97]:SYS3*/ + [94] = {0xFCB62000U, 0x0000000EU}, /* RGIDR_MODID[98]:DMAMSI0*/ + [95] = {0xFCB62004U, 0x0000000EU}, /* RGIDR_MODID[99]:DMAMSI1*/ + [96] = {0xFCB62008U, 0x0000000EU}, /* RGIDR_MODID[100]:DMAMSI2*/ + [97] = {0xFCB6200CU, 0x0000000EU}, /* RGIDR_MODID[101]:DMAMSI3*/ + [98] = {0xFCB62010U, 0x0000000EU}, /* RGIDR_MODID[102]:DMAMSI4*/ + [99] = {0xFCB62014U, 0x0000000EU}, /* RGIDR_MODID[103]:DMAMSI5*/ + [100] = {0xFCB62018U, 0x0000000FU}, /* RGIDR_MODID[104]:ECMSP3*/ + [101] = {0xFCB62024U, 0x0000000FU}, /* RGIDR_MODID[105]:ARSP30*/ + /* After setting */ /* RGIDR_MODID[106]:ARSP31*/ + /* After setting */ /* RGIDR_MODID[107]:ARSP32*/ + [102] = {0xFCB62030U, 0x0000000FU}, /* RGIDR_MODID[108]:ARSP33*/ + [103] = {0xFCB62034U, 0x0000000FU}, /* RGIDR_MODID[109]:ARSP34*/ + [104] = {0xFCB62038U, 0x0000000FU}, /* RGIDR_MODID[110]:ARSP35*/ + [105] = {0xFCB6203CU, 0x0000000FU}, /* RGIDR_MODID[111]:ARSP36*/ + [106] = {0xFCB62040U, 0x0000000FU}, /* RGIDR_MODID[112]:ARSP37*/ + [107] = {0xFCB62044U, 0x00000000U}, /* RGIDR_MODID[113]:ARSP38*/ + [108] = {0xFCB62048U, 0x0000000EU}, /* RGIDR_MODID[114]:MSI0*/ + [109] = {0xFCB6204CU, 0x0000000EU}, /* RGIDR_MODID[115]:MSI1*/ + [110] = {0xFCB62050U, 0x0000000EU}, /* RGIDR_MODID[116]:MSI2*/ + [111] = {0xFCB62054U, 0x0000000EU}, /* RGIDR_MODID[117]:MSI3*/ + [112] = {0xFCB62058U, 0x0000000EU}, /* RGIDR_MODID[118]:MSI4*/ + [113] = {0xFCB6205CU, 0x0000000EU}, /* RGIDR_MODID[119]:MSI5*/ + [114] = {0xFCB92000U, 0x0000000FU}, /* RGIDR_MODID[120]:ARSP40*/ + /* After setting */ /* RGIDR_MODID[121]:ARSP41*/ + /* After setting */ /* RGIDR_MODID[122]:ARSP42*/ + [115] = {0xFCB9200CU, 0x0000000FU}, /* RGIDR_MODID[123]:ARSP43*/ + [116] = {0xFCB92010U, 0x0000000FU}, /* RGIDR_MODID[124]:ARSP44*/ + [117] = {0xFCB92014U, 0x0000000FU}, /* RGIDR_MODID[125]:ARSP45*/ + [118] = {0xFCB92018U, 0x0000000FU}, /* RGIDR_MODID[126]:ARSP46*/ + [119] = {0xFCB9201CU, 0x0000000FU}, /* RGIDR_MODID[127]:ARSP47*/ + [120] = {0xFCB92020U, 0x00000000U}, /* RGIDR_MODID[128]:ARSP48*/ + [121] = {0xFCB92024U, 0x0000004FU}, /* RGIDR_MODID[129]:DMAHSCIF0*/ + [122] = {0xFCB92028U, 0x0000004FU}, /* RGIDR_MODID[130]:DMAHSCIF1*/ + [123] = {0xFCB9202CU, 0x0000004FU}, /* RGIDR_MODID[131]:DMAHSCIF2*/ + [124] = {0xFCB92030U, 0x0000004FU}, /* RGIDR_MODID[132]:DMAHSCIF3*/ + [125] = {0xFCB92034U, 0x0000004FU}, /* RGIDR_MODID[133]:DMASCIF0*/ + [126] = {0xFCB92038U, 0x0000004FU}, /* RGIDR_MODID[134]:DMASCIF1*/ + [127] = {0xFCB9203CU, 0x0000004FU}, /* RGIDR_MODID[135]:DMASCIF3*/ + [128] = {0xFCB92040U, 0x0000004FU}, /* RGIDR_MODID[136]:DMASCIF4*/ + [129] = {0xFCB92044U, 0x0000000FU}, /* RGIDR_MODID[137]:ECMSP4*/ + [130] = {0xFCB92048U, 0x0000004FU}, /* RGIDR_MODID[138]:HSCIF0*/ + [131] = {0xFCB9204CU, 0x0000004FU}, /* RGIDR_MODID[139]:HSCIF1*/ + [132] = {0xFCB92050U, 0x0000004FU}, /* RGIDR_MODID[140]:HSCIF2*/ + [133] = {0xFCB92054U, 0x0000004FU}, /* RGIDR_MODID[141]:HSCIF3*/ + [134] = {0xFCB92058U, 0x0000004FU}, /* RGIDR_MODID[142]:SCIF0*/ + [135] = {0xFCB9205CU, 0x0000004FU}, /* RGIDR_MODID[143]:SCIF1*/ + [136] = {0xFCB92060U, 0x0000004FU}, /* RGIDR_MODID[144]:SCIF3*/ + [137] = {0xFCB92064U, 0x0000004FU}, /* RGIDR_MODID[145]:SCIF4*/ + [138] = {0xFCB92068U, 0x0000006EU}, /* RGIDR_MODID[146]:TMU1*/ + [139] = {0xFCB9206CU, 0x0000006EU}, /* RGIDR_MODID[147]:TMU2*/ + [140] = {0xFCB92070U, 0x0000006EU}, /* RGIDR_MODID[148]:TMU3*/ + [141] = {0xFCB92074U, 0x0000006EU}, /* RGIDR_MODID[149]:TMU4*/ + [142] = {0xFCB92078U, 0x0000004AU}, /* RGIDR_MODID[150]:CANFD*/ + [143] = {0xFCB9207CU, 0x0000004AU}, /* RGIDR_MODID[151]:DMACANFD*/ + [144] = {0xFCB92080U, 0x00000002U}, /* RGIDR_MODID[152]:DMATPU0*/ + [145] = {0xFCB92084U, 0x00000002U}, /* RGIDR_MODID[153]:PWM0*/ + [146] = {0xFCB92088U, 0x00000002U}, /* RGIDR_MODID[154]:PWM1*/ + [147] = {0xFCB9208CU, 0x00000002U}, /* RGIDR_MODID[155]:PWM2*/ + [148] = {0xFCB92090U, 0x00000002U}, /* RGIDR_MODID[156]:PWM3*/ + [149] = {0xFCB92094U, 0x00000002U}, /* RGIDR_MODID[157]:PWM4*/ + [150] = {0xFCB92098U, 0x00000002U}, /* RGIDR_MODID[158]:PWM5*/ + [151] = {0xFCB9209CU, 0x00000002U}, /* RGIDR_MODID[159]:PWM6*/ + [152] = {0xFCB920A0U, 0x00000002U}, /* RGIDR_MODID[160]:PWM7*/ + [153] = {0xFCB920A4U, 0x00000002U}, /* RGIDR_MODID[161]:PWM8*/ + [154] = {0xFCB920A8U, 0x00000002U}, /* RGIDR_MODID[162]:PWM9*/ + [155] = {0xFCB920ACU, 0x00000002U}, /* RGIDR_MODID[163]:TPU0*/ + [156] = {0xFC672000U, 0x0000002FU}, /* RGIDR_MODID[164]:ARVC10*/ + /* After setting */ /* RGIDR_MODID[165]:ARVC11*/ + /* After setting */ /* RGIDR_MODID[166]:ARVC12*/ + [157] = {0xFC67200CU, 0x0000002FU}, /* RGIDR_MODID[167]:ARVC13*/ + [158] = {0xFC672010U, 0x0000002FU}, /* RGIDR_MODID[168]:ARVC14*/ + [159] = {0xFC672014U, 0x0000002FU}, /* RGIDR_MODID[169]:ARVC15*/ + [160] = {0xFC672018U, 0x0000002FU}, /* RGIDR_MODID[170]:ARVC16*/ + [161] = {0xFC67201CU, 0x0000002FU}, /* RGIDR_MODID[171]:ARVC17*/ + [162] = {0xFC672020U, 0x00000000U}, /* RGIDR_MODID[172]:ARVC18*/ + [163] = {0xFC672024U, 0x0000000FU}, /* RGIDR_MODID[173]:ECMVC1*/ + [164] = {0xFC672028U, 0x00000028U}, /* RGIDR_MODID[174]:FCPCS*/ + [165] = {0xFC67202CU, 0x00000028U}, /* RGIDR_MODID[175]:VCP4LC*/ + [166] = {0xFC672030U, 0x00000028U}, /* RGIDR_MODID[176]:VCP4LV*/ + [167] = {0xFEBD2000U, 0x0000000FU}, /* RGIDR_MODID[177]:ARVI40*/ + /* After setting */ /* RGIDR_MODID[178]:ARVI41*/ + /* After setting */ /* RGIDR_MODID[179]:ARVI42*/ + [168] = {0xFEBD200CU, 0x0000000FU}, /* RGIDR_MODID[180]:ARVI43*/ + [169] = {0xFEBD2010U, 0x0000000FU}, /* RGIDR_MODID[181]:ARVI44*/ + [170] = {0xFEBD2014U, 0x0000000FU}, /* RGIDR_MODID[182]:ARVI45*/ + [171] = {0xFEBD2018U, 0x0000000FU}, /* RGIDR_MODID[183]:ARVI46*/ + [172] = {0xFEBD201CU, 0x0000000FU}, /* RGIDR_MODID[184]:ARVI47*/ + [173] = {0xFEBD2020U, 0x00000000U}, /* RGIDR_MODID[185]:ARVI48*/ + [174] = {0xFEBD2024U, 0x0000000FU}, /* RGIDR_MODID[186]:DIS0*/ + [175] = {0xFEBD202CU, 0x0000000FU}, /* RGIDR_MODID[187]:DSC*/ + [176] = {0xFEBD2030U, 0x0000000FU}, /* RGIDR_MODID[188]:ECMVIO2*/ + [177] = {0xFEBD2034U, 0x0000000FU}, /* RGIDR_MODID[189]:FCPVD0*/ + [178] = {0xFEBD2038U, 0x0000000FU}, /* RGIDR_MODID[190]:FCPVD1*/ + [179] = {0xFEBD203CU, 0x0000004EU}, /* RGIDR_MODID[191]:VSPD0*/ + [180] = {0xFEBD2040U, 0x0000004EU}, /* RGIDR_MODID[192]:VSPD1*/ + [181] = {0xFCF82000U, 0x0000000AU}, /* RGIDR_MODID[193]:CKMHSC*/ + [182] = {0xFCF82004U, 0x0000000CU}, /* RGIDR_MODID[194]:AXIPCI001*/ + [183] = {0xFCF82008U, 0x0000000CU}, /* RGIDR_MODID[195]:AXIPCI002*/ + [184] = {0xFCF8200CU, 0x0000000CU}, /* RGIDR_MODID[196]:AXIPCI003*/ + [185] = {0xFCF82014U, 0x0000000CU}, /* RGIDR_MODID[197]:AXIPCI005*/ + [186] = {0xFCF82018U, 0x0000000CU}, /* RGIDR_MODID[198]:AXIPCI006*/ + [187] = {0xFCF8201CU, 0x0000000CU}, /* RGIDR_MODID[199]:AXIPCI007*/ + [188] = {0xFCF82020U, 0x0000000CU}, /* RGIDR_MODID[200]:AXIPCI008*/ + [189] = {0xFCF82024U, 0x0000000CU}, /* RGIDR_MODID[201]:AXIPCI009*/ + [190] = {0xFCF82028U, 0x0000000CU}, /* RGIDR_MODID[202]:AXIPCI010*/ + [191] = {0xFCF8202CU, 0x0000000CU}, /* RGIDR_MODID[203]:AXIPCI011*/ + [192] = {0xFCF82030U, 0x0000000CU}, /* RGIDR_MODID[204]:AXIPCI012*/ + [193] = {0xFCF82034U, 0x0000000CU}, /* RGIDR_MODID[205]:AXIPCI013*/ + [194] = {0xFCF82038U, 0x0000000CU}, /* RGIDR_MODID[206]:AXIPCI014*/ + [195] = {0xFCF8203CU, 0x0000000CU}, /* RGIDR_MODID[207]:AXIPCI015*/ + [196] = {0xFCF82040U, 0x0000000CU}, /* RGIDR_MODID[208]:AXIPCI100*/ + [197] = {0xFCF82044U, 0x0000000CU}, /* RGIDR_MODID[209]:AXIPCI101*/ + [198] = {0xFCF82048U, 0x0000000CU}, /* RGIDR_MODID[210]:AXIPCI102*/ + [199] = {0xFCF8204CU, 0x0000000CU}, /* RGIDR_MODID[211]:AXIPCI103*/ + [200] = {0xFCF82050U, 0x0000000CU}, /* RGIDR_MODID[212]:AXIPCI104*/ + [201] = {0xFCF82054U, 0x0000000CU}, /* RGIDR_MODID[213]:AXIPCI105*/ + [202] = {0xFCF82058U, 0x0000000CU}, /* RGIDR_MODID[214]:AXIPCI106*/ + [203] = {0xFCF8205CU, 0x0000000CU}, /* RGIDR_MODID[215]:AXIPCI107*/ + [204] = {0xFCF82060U, 0x0000000CU}, /* RGIDR_MODID[216]:AXIPCI108*/ + [205] = {0xFCF82064U, 0x0000000CU}, /* RGIDR_MODID[217]:AXIPCI109*/ + [206] = {0xFCF82068U, 0x0000000CU}, /* RGIDR_MODID[218]:AXIPCI110*/ + [207] = {0xFCF8206CU, 0x0000000CU}, /* RGIDR_MODID[219]:AXIPCI111*/ + [208] = {0xFCF82070U, 0x0000000CU}, /* RGIDR_MODID[220]:AXIPCI112*/ + [209] = {0xFCF82074U, 0x0000000CU}, /* RGIDR_MODID[221]:AXIPCI113*/ + [210] = {0xFCF82078U, 0x0000000CU}, /* RGIDR_MODID[222]:AXIPCI114*/ + [211] = {0xFCF8207CU, 0x0000000CU}, /* RGIDR_MODID[223]:AXIPCI115*/ + [212] = {0xFCF82084U, 0x0000000EU}, /* RGIDR_MODID[224]:GPTP*/ + [213] = {0xFCF82088U, 0x0000004EU}, /* RGIDR_MODID[225]:IPMMUHC00*/ + [214] = {0xFCF820F0U, 0x0000000EU}, /* RGIDR_MODID[226]:TSN0*/ + [215] = {0xFCF820F4U, 0x0000000CU}, /* RGIDR_MODID[227]:AXIPCI000*/ + [216] = {0xFCF820F8U, 0x0000000CU}, /* RGIDR_MODID[228]:AXIPCI004*/ + [217] = {0xFCF820FCU, 0x0000004EU}, /* RGIDR_MODID[229]:IPMMUHC01*/ + [218] = {0xFCF82100U, 0x0000004EU}, /* RGIDR_MODID[230]:AVB0*/ + [219] = {0xFCF82104U, 0x0000004EU}, /* RGIDR_MODID[231]:AVB1*/ + [220] = {0xFCF82108U, 0x0000004EU}, /* RGIDR_MODID[232]:AVB2*/ + [221] = {0xFCF8210CU, 0x0000004EU}, /* RGIDR_MODID[233]:IPMMUHC10*/ + [222] = {0xFCF82110U, 0x0000004EU}, /* RGIDR_MODID[234]:IPMMUHC11*/ + [223] = {0xFCF82114U, 0x0000004EU}, /* RGIDR_MODID[235]:IPMMUHC12*/ + [224] = {0xFCF82118U, 0x0000004EU}, /* RGIDR_MODID[236]:IPMMUHC13*/ + [225] = {0xFCF8211CU, 0x0000000CU}, /* RGIDR_MODID[237]:PPHY0*/ + [226] = {0xFCF82120U, 0x0000000CU}, /* RGIDR_MODID[238]:PPHY1*/ + [227] = {0xFCF82124U, 0x0000004EU}, /* RGIDR_MODID[239]:IPMMUHC14*/ + [228] = {0xFCF82128U, 0x0000004EU}, /* RGIDR_MODID[240]:IPMMUHC15*/ + [229] = {0xFCF8212CU, 0x0000000EU}, /* RGIDR_MODID[241]:FBAHSC*/ + [230] = {0xFCF82130U, 0x0000004EU}, /* RGIDR_MODID[242]:IPMMUHC02*/ + [231] = {0xFCF82138U, 0x0000000FU}, /* RGIDR_MODID[243]:ECMHSC*/ + [232] = {0xFCF8213CU, 0x0000000FU}, /* RGIDR_MODID[244]:ARHC0*/ + /* After setting */ /* RGIDR_MODID[245]:ARHC1*/ + /* After setting */ /* RGIDR_MODID[246]:ARHC2*/ + [233] = {0xFCF82148U, 0x0000000FU}, /* RGIDR_MODID[247]:ARHC3*/ + [234] = {0xFCF8214CU, 0x0000000FU}, /* RGIDR_MODID[248]:ARHC4*/ + [235] = {0xFCF82150U, 0x0000000FU}, /* RGIDR_MODID[249]:ARHC5*/ + [236] = {0xFCF82154U, 0x0000000FU}, /* RGIDR_MODID[250]:ARHC6*/ + [237] = {0xFCF82158U, 0x0000000FU}, /* RGIDR_MODID[251]:ARHC7*/ + [238] = {0xFCF8215CU, 0x00000000U}, /* RGIDR_MODID[252]:ARHC8*/ + [239] = {0xFCF82160U, 0x0000004EU}, /* RGIDR_MODID[253]:IPMMUHC03*/ + [240] = {0xFCF82164U, 0x0000004EU}, /* RGIDR_MODID[254]:IPMMUHC04*/ + [241] = {0xFCF82168U, 0x0000004EU}, /* RGIDR_MODID[255]:IPMMUHC05*/ + [242] = {0xFCF8216CU, 0x0000004EU}, /* RGIDR_MODID[256]:IPMMUHC06*/ + [243] = {0xFCF82170U, 0x0000004EU}, /* RGIDR_MODID[257]:IPMMUHC07*/ + [244] = {0xFCF82174U, 0x0000004EU}, /* RGIDR_MODID[258]:IPMMUHC08*/ + [245] = {0xFCF82178U, 0x0000004EU}, /* RGIDR_MODID[259]:IPMMUHC09*/ + [246] = {0xFC882000U, 0x0000000FU}, /* RGIDR_MODID[260]:ARIMP00*/ + /* After setting */ /* RGIDR_MODID[261]:ARIMP01*/ + /* After setting */ /* RGIDR_MODID[262]:ARIMP02*/ + [247] = {0xFC88200CU, 0x0000000FU}, /* RGIDR_MODID[263]:ARIMP03*/ + [248] = {0xFC882010U, 0x0000000FU}, /* RGIDR_MODID[264]:ARIMP04*/ + [249] = {0xFC882014U, 0x0000004EU}, /* RGIDR_MODID[265]:AXIFBABUSIR0*/ + [250] = {0xFC882018U, 0x0000004EU}, /* RGIDR_MODID[266]:AXIFBABUSIR1*/ + [251] = {0xFC88201CU, 0x0000004EU}, /* RGIDR_MODID[267]:AXIFBABUSIR2*/ + [252] = {0xFC882020U, 0x0000004EU}, /* RGIDR_MODID[268]:AXIFBABUSIR3*/ + [253] = {0xFC882024U, 0x0000004EU}, /* RGIDR_MODID[269]:AXIFBABUSIR4*/ + [254] = {0xFC882028U, 0x0000004EU}, /* RGIDR_MODID[270]:AXIIMP0*/ + [255] = {0xFC88202CU, 0x0000004EU}, /* RGIDR_MODID[271]:CKMCNR*/ + [256] = {0xFC882030U, 0x0000004EU}, /* RGIDR_MODID[272]:CKMDSP*/ + [257] = {0xFC882034U, 0x0000000FU}, /* RGIDR_MODID[273]:ARIMP05*/ + [258] = {0xFC882038U, 0x0000000FU}, /* RGIDR_MODID[274]:ARIMP06*/ + [259] = {0xFC88203CU, 0x0000000FU}, /* RGIDR_MODID[275]:ARIMP07*/ + [260] = {0xFC882040U, 0x00000000U}, /* RGIDR_MODID[276]:ARIMP08*/ + [261] = {0xFC882044U, 0x0000004EU}, /* RGIDR_MODID[277]:CKMIR*/ + [262] = {0xFC882048U, 0x0000000FU}, /* RGIDR_MODID[278]:ECMIR*/ + [263] = {0xFC88204CU, 0x0000000FU}, /* RGIDR_MODID[279]:DSPPS*/ + [264] = {0xFC882050U, 0x0000004EU}, /* RGIDR_MODID[280]:IPMMUIR1*/ + [265] = {0xFC882054U, 0x0000004EU}, /* RGIDR_MODID[281]:IPMMUIR0*/ + [266] = {0xFC882058U, 0x0000004EU}, /* RGIDR_MODID[282]:IPMMUIR10*/ + [267] = {0xFC88205CU, 0x0000004EU}, /* RGIDR_MODID[283]:IPMMUIR11*/ + [268] = {0xFC882060U, 0x0000004EU}, /* RGIDR_MODID[284]:IPMMUIR12*/ + [269] = {0xFC882064U, 0x0000004EU}, /* RGIDR_MODID[285]:IPMMUIR13*/ + [270] = {0xFC882068U, 0x0000004EU}, /* RGIDR_MODID[286]:IPMMUIR14*/ + [271] = {0xFC88206CU, 0x0000004EU}, /* RGIDR_MODID[287]:IPMMUIR15*/ + [272] = {0xFC882070U, 0x0000004EU}, /* RGIDR_MODID[288]:IPMMUIR2*/ + [273] = {0xFC882074U, 0x0000004EU}, /* RGIDR_MODID[289]:IPMMUIR3*/ + [274] = {0xFC882078U, 0x0000004EU}, /* RGIDR_MODID[290]:IPMMUIR4*/ + [275] = {0xFC88207CU, 0x0000004EU}, /* RGIDR_MODID[291]:IPMMUIR5*/ + [276] = {0xFC882080U, 0x0000004EU}, /* RGIDR_MODID[292]:IPMMUIR6*/ + [277] = {0xFC882084U, 0x0000004EU}, /* RGIDR_MODID[293]:IPMMUIR7*/ + [278] = {0xFC882088U, 0x0000004EU}, /* RGIDR_MODID[294]:IPMMUIR8*/ + [279] = {0xFC88208CU, 0x0000004EU}, /* RGIDR_MODID[295]:IPMMUIR9*/ + [280] = {0xFC012000U, 0x0000000FU}, /* RGIDR_MODID[296]:ARPV0*/ + /* After setting */ /* RGIDR_MODID[297]:ARPV1*/ + [281] = {0xFC012008U, 0x0000002CU}, /* RGIDR_MODID[298]:AXIRGXS*/ + /* After setting */ /* RGIDR_MODID[299]:ARPV2*/ + [282] = {0xFC012010U, 0x0000000FU}, /* RGIDR_MODID[300]:ARPV3*/ + [283] = {0xFC012014U, 0x0000000FU}, /* RGIDR_MODID[301]:ARPV4*/ + [284] = {0xFC012018U, 0x0000000FU}, /* RGIDR_MODID[302]:ARPV5*/ + [285] = {0xFC01201CU, 0x0000000FU}, /* RGIDR_MODID[303]:ARPV6*/ + [286] = {0xFC012020U, 0x0000000FU}, /* RGIDR_MODID[304]:ARPV7*/ + [287] = {0xFC012024U, 0x00000000U}, /* RGIDR_MODID[305]:ARPV8*/ + [288] = {0xFC012028U, 0x0000000AU}, /* RGIDR_MODID[306]:CKM3DG*/ + [289] = {0xFC01202CU, 0x0000000FU}, /* RGIDR_MODID[307]:ECM3DG*/ + [290] = {0xFC012030U, 0x0000000EU}, /* RGIDR_MODID[308]:FBAPVC*/ + [291] = {0xFC012034U, 0x0000000EU}, /* RGIDR_MODID[309]:FBAPVD0*/ + [292] = {0xFC012038U, 0x0000000EU}, /* RGIDR_MODID[310]:FBAPVD1*/ + [293] = {0xFC01203CU, 0x0000000EU}, /* RGIDR_MODID[311]:FBAPVD2*/ + [294] = {0xFC012040U, 0x0000000EU}, /* RGIDR_MODID[312]:FBAPVE*/ + [295] = {0xFC012044U, 0x0000004EU}, /* RGIDR_MODID[313]:IPMMUPV000*/ + [296] = {0xFC012048U, 0x0000004EU}, /* RGIDR_MODID[314]:IPMMUPV001*/ + [297] = {0xFC01204CU, 0x0000004EU}, /* RGIDR_MODID[315]:IPMMUPV010*/ + [298] = {0xFC012050U, 0x0000004EU}, /* RGIDR_MODID[316]:IPMMUPV011*/ + [299] = {0xFC012054U, 0x0000004EU}, /* RGIDR_MODID[317]:IPMMUPV012*/ + [300] = {0xFC012058U, 0x0000004EU}, /* RGIDR_MODID[318]:IPMMUPV013*/ + [301] = {0xFC01205CU, 0x0000004EU}, /* RGIDR_MODID[319]:IPMMUPV014*/ + [302] = {0xFC012060U, 0x0000004EU}, /* RGIDR_MODID[320]:IPMMUPV015*/ + [303] = {0xFC012064U, 0x0000004EU}, /* RGIDR_MODID[321]:IPMMUPV002*/ + [304] = {0xFC012068U, 0x0000004EU}, /* RGIDR_MODID[322]:IPMMUPV003*/ + [305] = {0xFC01206CU, 0x0000004EU}, /* RGIDR_MODID[323]:IPMMUPV004*/ + [306] = {0xFC012070U, 0x0000004EU}, /* RGIDR_MODID[324]:IPMMUPV005*/ + [307] = {0xFC012074U, 0x0000004EU}, /* RGIDR_MODID[325]:IPMMUPV006*/ + [308] = {0xFC012078U, 0x0000004EU}, /* RGIDR_MODID[326]:IPMMUPV007*/ + [309] = {0xFC01207CU, 0x0000004EU}, /* RGIDR_MODID[327]:IPMMUPV008*/ + [310] = {0xFC012080U, 0x0000004EU}, /* RGIDR_MODID[328]:IPMMUPV009*/ + [311] = {0xFDC22000U, 0x0000000FU}, /* RGIDR_MODID[329]:ARRC0*/ + /* After setting */ /* RGIDR_MODID[330]:ARRC1*/ + /* After setting */ /* RGIDR_MODID[331]:ARRC2*/ + [312] = {0xFDC2200CU, 0x0000000FU}, /* RGIDR_MODID[332]:ARRC3*/ + [313] = {0xFDC22010U, 0x0000000FU}, /* RGIDR_MODID[333]:ARRC4*/ + [314] = {0xFDC22014U, 0x0000000FU}, /* RGIDR_MODID[334]:ARRC5*/ + [315] = {0xFDC22018U, 0x0000000FU}, /* RGIDR_MODID[335]:ARRC6*/ + [316] = {0xFDC2201CU, 0x0000000FU}, /* RGIDR_MODID[336]:ARRC7*/ + [317] = {0xFDC22020U, 0x00000000U}, /* RGIDR_MODID[337]:ARRC8*/ + [318] = {0xFDC22024U, 0x00000009U}, /* RGIDR_MODID[338]:CR0*/ + [319] = {0xFDC22028U, 0x0000004FU}, /* RGIDR_MODID[339]:ICUMX*/ + [320] = {0xFDC2202CU, 0x0000000FU}, /* RGIDR_MODID[340]:ECMRC*/ + [321] = {0xFD432000U, 0x0000004EU}, /* RGIDR_MODID[341]:DMAWCRC0*/ + [322] = {0xFD432004U, 0x0000004EU}, /* RGIDR_MODID[342]:DMAWCRC1*/ + [323] = {0xFD432008U, 0x0000004EU}, /* RGIDR_MODID[343]:DMAWCRC2*/ + [324] = {0xFD43200CU, 0x0000004EU}, /* RGIDR_MODID[344]:DMAWCRC3*/ + [325] = {0xFD442000U, 0x0000000FU}, /* RGIDR_MODID[345]:ARMREG00*/ + [326] = {0xFD442004U, 0x0000000DU}, /* RGIDR_MODID[346]:ARMREG01*/ + [327] = {0xFD442008U, 0x00000000U}, /* RGIDR_MODID[347]:ARMREG10*/ + [328] = {0xFD44200CU, 0x00000000U}, /* RGIDR_MODID[348]:ARMREG11*/ + [329] = {0xFD442010U, 0x0000000BU}, /* RGIDR_MODID[349]:ARMREG12*/ + [330] = {0xFD442014U, 0x0000000FU}, /* RGIDR_MODID[350]:ARMREG13*/ + [331] = {0xFD442018U, 0x0000000BU}, /* RGIDR_MODID[351]:ARMREG14*/ + [332] = {0xFD44201CU, 0x00000002U}, /* RGIDR_MODID[352]:AXICR52SS0*/ + [333] = {0xFD442020U, 0x0000000EU}, /* RGIDR_MODID[353]:AXICSD0*/ + [334] = {0xFD442024U, 0x0000000EU}, /* RGIDR_MODID[354]:AXIINTAP0*/ + [335] = {0xFD442028U, 0x00000000U}, /* RGIDR_MODID[355]:AXIINTAP1*/ + [336] = {0xFD44202CU, 0x00000009U}, /* RGIDR_MODID[356]:AXISECROM*/ + [337] = {0xFD442030U, 0x0000000FU}, /* RGIDR_MODID[357]:AXISYSRAM0*/ + [338] = {0xFD442034U, 0x0000004FU}, /* RGIDR_MODID[358]:AXISYSRAM1*/ + [339] = {0xFD442038U, 0x00000000U}, /* RGIDR_MODID[359]:ARGREG15*/ + [340] = {0xFD44203CU, 0x00000000U}, /* RGIDR_MODID[360]:ARMREG2*/ + [341] = {0xFD442040U, 0x00000000U}, /* RGIDR_MODID[361]:ARMREG3*/ + [342] = {0xFD442044U, 0x00000000U}, /* RGIDR_MODID[362]:ARMREG4*/ + [343] = {0xFD442048U, 0x0000000FU}, /* RGIDR_MODID[363]:ARMREG5*/ + [344] = {0xFD44204CU, 0x0000000FU}, /* RGIDR_MODID[364]:ARMREG6*/ + [345] = {0xFD442050U, 0x00000000U}, /* RGIDR_MODID[365]:ARMREG7*/ + [346] = {0xFD442054U, 0x0000000DU}, /* RGIDR_MODID[366]:ARMREG8*/ + [347] = {0xFD442058U, 0x0000000DU}, /* RGIDR_MODID[367]:ARMREG9*/ + [348] = {0xFD44205CU, 0x0000000FU}, /* RGIDR_MODID[368]:ARRD0*/ + /* After setting */ /* RGIDR_MODID[369]:ARRD1*/ + /* After setting */ /* RGIDR_MODID[370]:ARRD2*/ + [349] = {0xFD442068U, 0x0000000FU}, /* RGIDR_MODID[371]:ARRD3*/ + [350] = {0xFD44206CU, 0x0000000FU}, /* RGIDR_MODID[372]:ARRD4*/ + [351] = {0xFD442070U, 0x0000000FU}, /* RGIDR_MODID[373]:ARRD5*/ + [352] = {0xFD442074U, 0x0000000FU}, /* RGIDR_MODID[374]:ARRD6*/ + [353] = {0xFD442078U, 0x0000000FU}, /* RGIDR_MODID[375]:ARRD7*/ + [354] = {0xFD44207CU, 0x00000000U}, /* RGIDR_MODID[376]:ARRD8*/ + [355] = {0xFD442080U, 0x0000000FU}, /* RGIDR_MODID[377]:ARRT0*/ + /* After setting */ /* RGIDR_MODID[378]:ARRT1*/ + /* After setting */ /* RGIDR_MODID[379]:ARRT2*/ + [356] = {0xFD44208CU, 0x0000000FU}, /* RGIDR_MODID[380]:ARRT3*/ + [357] = {0xFD442090U, 0x0000000FU}, /* RGIDR_MODID[381]:ARRT4*/ + [358] = {0xFD442094U, 0x0000000FU}, /* RGIDR_MODID[382]:ARRT5*/ + [359] = {0xFD442098U, 0x0000000FU}, /* RGIDR_MODID[383]:ARRT6*/ + [360] = {0xFD44209CU, 0x0000000FU}, /* RGIDR_MODID[384]:ARRT7*/ + [361] = {0xFD4420A0U, 0x00000000U}, /* RGIDR_MODID[385]:ARRT8*/ + [362] = {0xFD4420A4U, 0x0000000AU}, /* RGIDR_MODID[386]:CKMRT*/ + [363] = {0xFD4420A8U, 0x0000004EU}, /* RGIDR_MODID[387]:CRC0*/ + [364] = {0xFD4420ACU, 0x0000004EU}, /* RGIDR_MODID[388]:CRC1*/ + [365] = {0xFD4420B0U, 0x0000004EU}, /* RGIDR_MODID[389]:CRC2*/ + [366] = {0xFD4420B4U, 0x0000004EU}, /* RGIDR_MODID[390]:CRC3*/ + [367] = {0xFD4420B8U, 0x0000000EU}, /* RGIDR_MODID[391]:CSD*/ + [368] = {0xFD4420BCU, 0x0000000FU}, /* RGIDR_MODID[392]:ECM*/ + [369] = {0xFD4420C0U, 0x0000000FU}, /* RGIDR_MODID[393]:ECMRT*/ + [370] = {0xFD4420C4U, 0x0000000EU}, /* RGIDR_MODID[394]:FBACR52*/ + [371] = {0xFD4420C8U, 0x0000000EU}, /* RGIDR_MODID[395]:FBART*/ + [372] = {0xFD4420CCU, 0x0000000EU}, /* RGIDR_MODID[396]:INTTP*/ + [373] = {0xFD4420D0U, 0x0000004EU}, /* RGIDR_MODID[397]:IPMMURT000*/ + [374] = {0xFD4420D4U, 0x0000004EU}, /* RGIDR_MODID[398]:IPMMURT100*/ + [375] = {0xFD4420D8U, 0x0000004EU}, /* RGIDR_MODID[399]:KCRC4*/ + [376] = {0xFD4420DCU, 0x0000004EU}, /* RGIDR_MODID[400]:KCRC5*/ + [377] = {0xFD4420E0U, 0x0000004EU}, /* RGIDR_MODID[401]:KCRC6*/ + [378] = {0xFD4420E4U, 0x0000004EU}, /* RGIDR_MODID[402]:KCRC7*/ + [379] = {0xFD4420E8U, 0x0000004FU}, /* RGIDR_MODID[403]:MFI00*/ + [380] = {0xFD4420ECU, 0x0000004EU}, /* RGIDR_MODID[404]:MFI01*/ + [381] = {0xFD4420F0U, 0x0000004EU}, /* RGIDR_MODID[405]:MFI10*/ + [382] = {0xFD4420F4U, 0x0000004EU}, /* RGIDR_MODID[406]:MFI02*/ + [383] = {0xFD4420F8U, 0x0000004EU}, /* RGIDR_MODID[407]:MFI03*/ + [384] = {0xFD4420FCU, 0x0000004EU}, /* RGIDR_MODID[408]:MFI04*/ + [385] = {0xFD442100U, 0x00000000U}, /* RGIDR_MODID[409]:MFI05*/ + [386] = {0xFD442104U, 0x00000000U}, /* RGIDR_MODID[410]:MFI06*/ + [387] = {0xFD442108U, 0x00000000U}, /* RGIDR_MODID[411]:MFI07*/ + [388] = {0xFD44210CU, 0x00000000U}, /* RGIDR_MODID[412]:MFI08*/ + [389] = {0xFD442110U, 0x0000004EU}, /* RGIDR_MODID[413]:MFI09*/ + [390] = {0xFD442114U, 0x0000004FU}, /* RGIDR_MODID[414]:MFI15*/ + [391] = {0xFD442118U, 0x0000000AU}, /* RGIDR_MODID[415]:CKMCR52*/ + [392] = {0xFD44211CU, 0x0000004BU}, /* RGIDR_MODID[416]:RTDM0P*/ + [393] = {0xFD442120U, 0x0000000FU}, /* RGIDR_MODID[417]:ECMRD*/ + [394] = {0xFD442124U, 0x0000004BU}, /* RGIDR_MODID[418]:RTDM1P*/ + [395] = {0xFD44212CU, 0x0000004BU}, /* RGIDR_MODID[419]:RTDM2P*/ + [396] = {0xFD442130U, 0x0000000BU}, /* RGIDR_MODID[420]:SYSRAM10*/ + [397] = {0xFD442134U, 0x0000004BU}, /* RGIDR_MODID[421]:RTDM3P*/ + [398] = {0xFD442138U, 0x00000003U}, /* RGIDR_MODID[422]:SYSRAM00*/ + [399] = {0xFD44213CU, 0x0000004EU}, /* RGIDR_MODID[423]:TSIPL0*/ + [400] = {0xFD442140U, 0x0000004EU}, /* RGIDR_MODID[424]:TSIPL1*/ + [401] = {0xFD442144U, 0x0000004EU}, /* RGIDR_MODID[425]:TSIPL2*/ + [402] = {0xFD442148U, 0x0000004EU}, /* RGIDR_MODID[426]:TSIPL3*/ + [403] = {0xFD44214CU, 0x0000004EU}, /* RGIDR_MODID[427]:TSIPL4*/ + [404] = {0xFD442150U, 0x0000004EU}, /* RGIDR_MODID[428]:TSIPL5*/ + [405] = {0xFD442154U, 0x0000004EU}, /* RGIDR_MODID[429]:TSIPL6*/ + [406] = {0xFD442158U, 0x0000004EU}, /* RGIDR_MODID[430]:TSIPL7*/ + [407] = {0xFD44215CU, 0x0000004EU}, /* RGIDR_MODID[431]:WCRC0*/ + [408] = {0xFD442160U, 0x0000004EU}, /* RGIDR_MODID[432]:WCRC1*/ + [409] = {0xFD442164U, 0x0000004EU}, /* RGIDR_MODID[433]:WCRC2*/ + [410] = {0xFD442168U, 0x0000004EU}, /* RGIDR_MODID[434]:WCRC3*/ + [411] = {0xFD442180U, 0x0000004EU}, /* RGIDR_MODID[435]:MFI11*/ + [412] = {0xFD442184U, 0x00000000U}, /* RGIDR_MODID[436]:MFI12*/ + [413] = {0xFD442188U, 0x00000000U}, /* RGIDR_MODID[437]:MFI13*/ + [414] = {0xFD44218CU, 0x00000000U}, /* RGIDR_MODID[438]:MFI14*/ + [415] = {0xFD442190U, 0x0000004EU}, /* RGIDR_MODID[439]:IPMMURT001*/ + [416] = {0xFD442194U, 0x0000004EU}, /* RGIDR_MODID[440]:IPMMURT010*/ + [417] = {0xFD442198U, 0x0000004EU}, /* RGIDR_MODID[441]:IPMMURT011*/ + [418] = {0xFD44219CU, 0x0000004EU}, /* RGIDR_MODID[442]:IPMMURT012*/ + [419] = {0xFD4421A0U, 0x0000004EU}, /* RGIDR_MODID[443]:IPMMURT013*/ + [420] = {0xFD4421A4U, 0x0000004EU}, /* RGIDR_MODID[444]:IPMMURT014*/ + [421] = {0xFD4421A8U, 0x0000004EU}, /* RGIDR_MODID[445]:IPMMURT015*/ + [422] = {0xFD4421ACU, 0x0000004EU}, /* RGIDR_MODID[446]:IPMMURT002*/ + [423] = {0xFD4421B0U, 0x0000004EU}, /* RGIDR_MODID[447]:IPMMURT003*/ + [424] = {0xFD4421B4U, 0x0000004EU}, /* RGIDR_MODID[448]:IPMMURT004*/ + [425] = {0xFD4421B8U, 0x0000004EU}, /* RGIDR_MODID[449]:IPMMURT005*/ + [426] = {0xFD4421BCU, 0x0000004EU}, /* RGIDR_MODID[450]:IPMMURT006*/ + [427] = {0xFD4421C0U, 0x0000004EU}, /* RGIDR_MODID[451]:IPMMURT007*/ + [428] = {0xFD4421C4U, 0x0000004EU}, /* RGIDR_MODID[452]:IPMMURT008*/ + [429] = {0xFD4421C8U, 0x0000004EU}, /* RGIDR_MODID[453]:IPMMURT009*/ + [430] = {0xFD4421CCU, 0x0000004EU}, /* RGIDR_MODID[454]:IPKMURT101*/ + [431] = {0xFD4421D0U, 0x0000004EU}, /* RGIDR_MODID[455]:IPMMURT110*/ + [432] = {0xFD4421D4U, 0x0000004EU}, /* RGIDR_MODID[456]:IPMMURT111*/ + [433] = {0xFD4421D8U, 0x0000004EU}, /* RGIDR_MODID[457]:IPMMURT112*/ + [434] = {0xFD4421DCU, 0x0000004EU}, /* RGIDR_MODID[458]:IPMMURT113*/ + [435] = {0xFD4421E0U, 0x0000004EU}, /* RGIDR_MODID[459]:IPMMURT114*/ + [436] = {0xFD4421E4U, 0x0000004EU}, /* RGIDR_MODID[460]:IPMMURT115*/ + [437] = {0xFD4421E8U, 0x0000004EU}, /* RGIDR_MODID[461]:IPMMURT102*/ + [438] = {0xFD4421ECU, 0x0000004EU}, /* RGIDR_MODID[462]:IPMMURT103*/ + [439] = {0xFD4421F0U, 0x0000004EU}, /* RGIDR_MODID[463]:IPMMURT104*/ + [440] = {0xFD4421F4U, 0x0000004EU}, /* RGIDR_MODID[464]:IPMMURT105*/ + [441] = {0xFD4421F8U, 0x0000004EU}, /* RGIDR_MODID[465]:IPMMURT106*/ + [442] = {0xFD4421FCU, 0x0000004EU}, /* RGIDR_MODID[466]:IPMMURT107*/ + [443] = {0xFD442200U, 0x0000004BU}, /* RGIDR_MODID[467]:RTDM000*/ + [444] = {0xFD442204U, 0x0000004BU}, /* RGIDR_MODID[468]:RTDM001*/ + [445] = {0xFD442208U, 0x0000004BU}, /* RGIDR_MODID[469]:RTDM010*/ + [446] = {0xFD44220CU, 0x0000004BU}, /* RGIDR_MODID[470]:RTDM011*/ + [447] = {0xFD442210U, 0x0000004BU}, /* RGIDR_MODID[471]:RTDM012*/ + [448] = {0xFD442214U, 0x0000004BU}, /* RGIDR_MODID[472]:RTDM013*/ + [449] = {0xFD442218U, 0x0000004BU}, /* RGIDR_MODID[473]:RTDM014*/ + [450] = {0xFD44221CU, 0x0000004BU}, /* RGIDR_MODID[474]:RTDM015*/ + [451] = {0xFD442220U, 0x0000004BU}, /* RGIDR_MODID[475]:RTDM002*/ + [452] = {0xFD442224U, 0x0000004BU}, /* RGIDR_MODID[476]:RTDM003*/ + [453] = {0xFD442228U, 0x0000004BU}, /* RGIDR_MODID[477]:RTDM004*/ + [454] = {0xFD44222CU, 0x0000004BU}, /* RGIDR_MODID[478]:RTDM005*/ + [455] = {0xFD442230U, 0x0000004BU}, /* RGIDR_MODID[479]:RTDM006*/ + [456] = {0xFD442234U, 0x0000004BU}, /* RGIDR_MODID[480]:RTDM007*/ + [457] = {0xFD442238U, 0x0000004BU}, /* RGIDR_MODID[481]:RTDM008*/ + [458] = {0xFD44223CU, 0x0000004BU}, /* RGIDR_MODID[482]:RTDM009*/ + [459] = {0xFD442240U, 0x0000004BU}, /* RGIDR_MODID[483]:RTDM100*/ + [460] = {0xFD442244U, 0x0000004BU}, /* RGIDR_MODID[484]:RTDM101*/ + [461] = {0xFD442248U, 0x0000004BU}, /* RGIDR_MODID[485]:RTDM110*/ + [462] = {0xFD44224CU, 0x0000004BU}, /* RGIDR_MODID[486]:RTDM111*/ + [463] = {0xFD442250U, 0x0000004BU}, /* RGIDR_MODID[487]:RTDM112*/ + [464] = {0xFD442254U, 0x0000004BU}, /* RGIDR_MODID[488]:RTDM113*/ + [465] = {0xFD442258U, 0x0000004BU}, /* RGIDR_MODID[489]:RTDM114*/ + [466] = {0xFD44225CU, 0x0000004BU}, /* RGIDR_MODID[490]:RTDM115*/ + [467] = {0xFD442260U, 0x0000004BU}, /* RGIDR_MODID[491]:RTDM102*/ + [468] = {0xFD442264U, 0x0000004BU}, /* RGIDR_MODID[492]:RTDM103*/ + [469] = {0xFD442268U, 0x0000004BU}, /* RGIDR_MODID[493]:RTDM104*/ + [470] = {0xFD44226CU, 0x0000004BU}, /* RGIDR_MODID[494]:RTDM105*/ + [471] = {0xFD442270U, 0x0000004BU}, /* RGIDR_MODID[495]:RTDM106*/ + [472] = {0xFD442274U, 0x0000004BU}, /* RGIDR_MODID[496]:RTDM107*/ + [473] = {0xFD442278U, 0x0000004BU}, /* RGIDR_MODID[497]:RTDM108*/ + [474] = {0xFD44227CU, 0x0000004BU}, /* RGIDR_MODID[498]:RTDM109*/ + [475] = {0xFD442280U, 0x0000004BU}, /* RGIDR_MODID[499]:RTDM200*/ + [476] = {0xFD442284U, 0x0000004BU}, /* RGIDR_MODID[500]:RTDM201*/ + [477] = {0xFD442288U, 0x0000004BU}, /* RGIDR_MODID[501]:RTDM210*/ + [478] = {0xFD44228CU, 0x0000004BU}, /* RGIDR_MODID[502]:RTDM211*/ + [479] = {0xFD442290U, 0x0000004BU}, /* RGIDR_MODID[503]:RTDM212*/ + [480] = {0xFD442294U, 0x0000004BU}, /* RGIDR_MODID[504]:RTDM213*/ + [481] = {0xFD442298U, 0x0000004BU}, /* RGIDR_MODID[505]:RTDM214*/ + [482] = {0xFD44229CU, 0x0000004BU}, /* RGIDR_MODID[506]:RTDM215*/ + [483] = {0xFD4422A0U, 0x0000004BU}, /* RGIDR_MODID[507]:RTDM202*/ + [484] = {0xFD4422A4U, 0x0000004BU}, /* RGIDR_MODID[508]:RTDM203*/ + [485] = {0xFD4422A8U, 0x0000004BU}, /* RGIDR_MODID[509]:RTDM204*/ + [486] = {0xFD4422ACU, 0x0000004BU}, /* RGIDR_MODID[510]:RTDM205*/ + [487] = {0xFD4422B0U, 0x0000004BU}, /* RGIDR_MODID[511]:RTDM206*/ + [488] = {0xFD4422B4U, 0x0000004BU}, /* RGIDR_MODID[512]:RTDM207*/ + [489] = {0xFD4422B8U, 0x0000004BU}, /* RGIDR_MODID[513]:RTDM208*/ + [490] = {0xFD4422BCU, 0x0000004BU}, /* RGIDR_MODID[514]:RTDM209*/ + [491] = {0xFD4422C0U, 0x0000004BU}, /* RGIDR_MODID[515]:RTDM300*/ + [492] = {0xFD4422C4U, 0x0000004BU}, /* RGIDR_MODID[516]:RTDM301*/ + [493] = {0xFD4422C8U, 0x0000004BU}, /* RGIDR_MODID[517]:RTDM310*/ + [494] = {0xFD4422CCU, 0x0000004BU}, /* RGIDR_MODID[518]:RTDM311*/ + [495] = {0xFD4422D0U, 0x0000004BU}, /* RGIDR_MODID[519]:RTDM312*/ + [496] = {0xFD4422D4U, 0x0000004BU}, /* RGIDR_MODID[520]:RTDM313*/ + [497] = {0xFD4422D8U, 0x0000004BU}, /* RGIDR_MODID[521]:RTDM314*/ + [498] = {0xFD4422DCU, 0x0000004BU}, /* RGIDR_MODID[522]:RTDM315*/ + [499] = {0xFD4422E0U, 0x0000004BU}, /* RGIDR_MODID[523]:RTDM302*/ + [500] = {0xFD4422E4U, 0x0000004BU}, /* RGIDR_MODID[524]:RTDM303*/ + [501] = {0xFD4422E8U, 0x0000004BU}, /* RGIDR_MODID[525]:RTDM304*/ + [502] = {0xFD4422ECU, 0x0000004BU}, /* RGIDR_MODID[526]:RTDM305*/ + [503] = {0xFD4422F0U, 0x0000004BU}, /* RGIDR_MODID[527]:RTDM306*/ + [504] = {0xFD4422F4U, 0x0000004BU}, /* RGIDR_MODID[528]:RTDM307*/ + [505] = {0xFD4422F8U, 0x0000004BU}, /* RGIDR_MODID[529]:RTDM308*/ + [506] = {0xFD4422FCU, 0x0000004BU}, /* RGIDR_MODID[530]:RTDM309*/ + [507] = {0xFD442300U, 0x0000004EU}, /* RGIDR_MODID[531]:IPMMURT108*/ + [508] = {0xFD442304U, 0x0000004EU}, /* RGIDR_MODID[532]:IPMMURT109*/ + [509] = {0xFD442308U, 0x00000001U}, /* RGIDR_MODID[533]:SYSRAM01*/ + [510] = {0xFD44230CU, 0x0000000BU}, /* RGIDR_MODID[534]:SYSRAM02*/ + [511] = {0xFD442310U, 0x00000001U}, /* RGIDR_MODID[535]:SYSRAM03*/ + [512] = {0xFD442314U, 0x00000001U}, /* RGIDR_MODID[536]:SYSRAM04*/ + [513] = {0xFD442318U, 0x00000001U}, /* RGIDR_MODID[537]:SYSRAM05*/ + [514] = {0xFD44231CU, 0x00000001U}, /* RGIDR_MODID[538]:SYSRAM06*/ + [515] = {0xFD442320U, 0x00000000U}, /* RGIDR_MODID[539]:SYSRAM07*/ + [516] = {0xFD442324U, 0x0000000BU}, /* RGIDR_MODID[540]:SYSRAM11*/ + [517] = {0xFD442328U, 0x0000000BU}, /* RGIDR_MODID[541]:SYSRAM12*/ + [518] = {0xFD44232CU, 0x0000000BU}, /* RGIDR_MODID[542]:SYSRAM13*/ + [519] = {0xFD442330U, 0x0000000BU}, /* RGIDR_MODID[543]:SYSRAM14*/ + [520] = {0xFD442334U, 0x0000000BU}, /* RGIDR_MODID[544]:SYSRAM15*/ + [521] = {0xFD442338U, 0x0000000BU}, /* RGIDR_MODID[545]:SYSRAM16*/ + [522] = {0xFD44233CU, 0x00000000U}, /* RGIDR_MODID[546]:SYSRAM17*/ + [523] = {0xFD442360U, 0x00000002U}, /* RGIDR_MODID[547]:BKBUF*/ + [524] = {0xFD442364U, 0x00000002U}, /* RGIDR_MODID[548]:AXICR52SS1*/ + [525] = {0xFD442368U, 0x00000002U}, /* RGIDR_MODID[549]:AXICR52SS2*/ + [526] = {0xFC862000U, 0x0000000FU}, /* RGIDR_MODID[550]:ARSC0*/ + /* After setting */ /* RGIDR_MODID[551]:ARSC1*/ + /* After setting */ /* RGIDR_MODID[552]:ARSC2*/ + [527] = {0xFC86200CU, 0x0000000FU}, /* RGIDR_MODID[553]:ARSC3*/ + [528] = {0xFC862010U, 0x0000000FU}, /* RGIDR_MODID[554]:ARSC4*/ + [529] = {0xFC862014U, 0x0000000FU}, /* RGIDR_MODID[555]:ARSC5*/ + [530] = {0xFC862018U, 0x0000000FU}, /* RGIDR_MODID[556]:ARSC6*/ + [531] = {0xFC86201CU, 0x0000000FU}, /* RGIDR_MODID[557]:ARSC7*/ + [532] = {0xFC862020U, 0x00000000U}, /* RGIDR_MODID[558]:ARSC8*/ + [533] = {0xFC862024U, 0x0000000FU}, /* RGIDR_MODID[559]:ARSTM0*/ + /* After setting */ /* RGIDR_MODID[560]:ARSTM1*/ + [534] = {0xFC86202CU, 0x0000000EU}, /* RGIDR_MODID[561]:CSD1S*/ + [535] = {0xFC862030U, 0x0000000EU}, /* RGIDR_MODID[562]:AXIFBABUSTOP0*/ + [536] = {0xFC862034U, 0x0000000EU}, /* RGIDR_MODID[563]:AXIFBABUSTOP1*/ + /* After setting */ /* RGIDR_MODID[564]:ARSTM2*/ + [537] = {0xFC86203CU, 0x0000000FU}, /* RGIDR_MODID[565]:ARSTM3*/ + [538] = {0xFC862040U, 0x0000000FU}, /* RGIDR_MODID[566]:ARSTM4*/ + [539] = {0xFC862044U, 0x0000000FU}, /* RGIDR_MODID[567]:ARSTM5*/ + [540] = {0xFC862048U, 0x0000000FU}, /* RGIDR_MODID[568]:ARSTM6*/ + [541] = {0xFC86204CU, 0x0000000FU}, /* RGIDR_MODID[569]:ARSTM7*/ + [542] = {0xFC862050U, 0x00000000U}, /* RGIDR_MODID[570]:ARSTM8*/ + [543] = {0xFC862054U, 0x0000000FU}, /* RGIDR_MODID[571]:ECMTOP*/ + [544] = {0xFC862058U, 0x0000000EU}, /* RGIDR_MODID[572]:FBA*/ + [545] = {0xFC86205CU, 0x0000000EU}, /* RGIDR_MODID[573]:FBC*/ + [546] = {0xFC862060U, 0x0000000CU}, /* RGIDR_MODID[574]:AXICCI00*/ + [547] = {0xFC862064U, 0x0000000CU}, /* RGIDR_MODID[575]:AXICCI01*/ + [548] = {0xFC862068U, 0x0000000CU}, /* RGIDR_MODID[576]:AXICCI10*/ + [549] = {0xFC86206CU, 0x0000000CU}, /* RGIDR_MODID[577]:AXICCI11*/ + [550] = {0xFC862070U, 0x0000000CU}, /* RGIDR_MODID[578]:AXICCI12*/ + [551] = {0xFC862074U, 0x0000000CU}, /* RGIDR_MODID[579]:AXICCI13*/ + [552] = {0xFC862078U, 0x0000000CU}, /* RGIDR_MODID[580]:AXICCI14*/ + [553] = {0xFC86207CU, 0x0000000CU}, /* RGIDR_MODID[581]:AXICCI15*/ + [554] = {0xFC862080U, 0x0000000CU}, /* RGIDR_MODID[582]:AXICCI2*/ + [555] = {0xFC862084U, 0x0000000CU}, /* RGIDR_MODID[583]:AXICCI3*/ + [556] = {0xFC862088U, 0x0000000CU}, /* RGIDR_MODID[584]:AXICCI4*/ + [557] = {0xFC86208CU, 0x0000000CU}, /* RGIDR_MODID[585]:AXICCI5*/ + [558] = {0xFC862090U, 0x0000000CU}, /* RGIDR_MODID[586]:AXICCI6*/ + [559] = {0xFC862094U, 0x0000000CU}, /* RGIDR_MODID[587]:AXICCI7*/ + [560] = {0xFC862098U, 0x0000000CU}, /* RGIDR_MODID[588]:AXICCI8*/ + [561] = {0xFC86209CU, 0x0000000FU}, /* RGIDR_MODID[589]:AXICCI9*/ + [562] = {0xFC8620A0U, 0x0000000FU}, /* RGIDR_MODID[590]:ECMSTM*/ + [563] = {0xFCB82000U, 0x0000002CU}, /* RGIDR_MODID[591]:DMASSI00*/ + [564] = {0xFCB82004U, 0x0000002CU}, /* RGIDR_MODID[592]:DMASSI01*/ + [565] = {0xFCB82008U, 0x0000002CU}, /* RGIDR_MODID[593]:DMASSI02*/ + [566] = {0xFCB8200CU, 0x0000002CU}, /* RGIDR_MODID[594]:DMASSI03*/ + [567] = {0xFCB82010U, 0x0000002CU}, /* RGIDR_MODID[595]:DMASSI04*/ + [568] = {0xFCB82014U, 0x0000004EU}, /* RGIDR_MODID[596]:DMAI2C0*/ + [569] = {0xFCB82018U, 0x0000004EU}, /* RGIDR_MODID[597]:DMAI2C1*/ + [570] = {0xFCB8201CU, 0x0000004EU}, /* RGIDR_MODID[598]:DMAI2C2*/ + [571] = {0xFCB82020U, 0x0000004EU}, /* RGIDR_MODID[599]:DMAI2C3*/ + [572] = {0xFCB82024U, 0x0000004EU}, /* RGIDR_MODID[600]:DMAI2C4*/ + [573] = {0xFCB82028U, 0x0000004EU}, /* RGIDR_MODID[601]:DMAI2C5*/ + [574] = {0xFCB8202CU, 0x0000002CU}, /* RGIDR_MODID[602]:DMASSI05*/ + [575] = {0xFCB82030U, 0x0000002CU}, /* RGIDR_MODID[603]:DMASSI06*/ + [576] = {0xFCB82034U, 0x0000002CU}, /* RGIDR_MODID[604]:DMASSI07*/ + [577] = {0xFDDC2000U, 0x00000007U}, /* RGIDR_MODID[605]:ARMM*/ + /* After setting */ /* RGIDR_MODID[606]:AXIARNMM*/ + [578] = {0xFDDC2008U, 0x0000000FU}, /* RGIDR_MODID[607]:ARSM0*/ + /* After setting */ /* RGIDR_MODID[608]:ARSM1*/ + /* After setting */ /* RGIDR_MODID[609]:ARSM2*/ + [579] = {0xFDDC2014U, 0x0000000FU}, /* RGIDR_MODID[610]:AXIQOS0*/ + [580] = {0xFDDC2018U, 0x0000000FU}, /* RGIDR_MODID[611]:AXIQOS1*/ + [581] = {0xFDDC201CU, 0x0000000FU}, /* RGIDR_MODID[612]:AXIQOS2*/ + [582] = {0xFDDC2020U, 0x0000000FU}, /* RGIDR_MODID[613]:AXIQOS3*/ + [583] = {0xFDDC2024U, 0x0000000FU}, /* RGIDR_MODID[614]:AXIQOS4*/ + [584] = {0xFDDC2028U, 0x0000000FU}, /* RGIDR_MODID[615]:AXIQOS5*/ + [585] = {0xFDDC202CU, 0x0000000FU}, /* RGIDR_MODID[616]:AXIQOS6*/ + [586] = {0xFDDC2030U, 0x0000000FU}, /* RGIDR_MODID[617]:AXIQOS7*/ + [587] = {0xFDDC2034U, 0x0000000FU}, /* RGIDR_MODID[618]:ARSM3*/ + [588] = {0xFDDC2038U, 0x0000000FU}, /* RGIDR_MODID[619]:ARSM4*/ + [589] = {0xFDDC203CU, 0x0000000FU}, /* RGIDR_MODID[620]:ARSM5*/ + [590] = {0xFDDC2040U, 0x0000000FU}, /* RGIDR_MODID[621]:ARSM6*/ + [591] = {0xFDDC2044U, 0x0000000FU}, /* RGIDR_MODID[622]:ARSM7*/ + [592] = {0xFDDC2048U, 0x00000000U}, /* RGIDR_MODID[623]:ARSM8*/ + [593] = {0xFDDC204CU, 0x0000000BU}, /* RGIDR_MODID[624]:AXMM0*/ + [594] = {0xFDDC2050U, 0x0000000BU}, /* RGIDR_MODID[625]:AXMM1*/ + [595] = {0xFDDC2054U, 0x00000000U}, /* RGIDR_MODID[626]:AXMMPMON*/ + [596] = {0xFDDC2058U, 0x0000000AU}, /* RGIDR_MODID[627]:CKMMM*/ + [597] = {0xFDDC205CU, 0x0000000FU}, /* RGIDR_MODID[628]:ECMMM*/ + [598] = {0xFDDC2060U, 0x0000000EU}, /* RGIDR_MODID[629]:FBADBSC0*/ + [599] = {0xFDDC2064U, 0x0000000EU}, /* RGIDR_MODID[630]:FBADBSC1*/ + [600] = {0xFDDC2068U, 0x0000000EU}, /* RGIDR_MODID[631]:FBAMM*/ + [601] = {0xFDDC206CU, 0x0000004EU}, /* RGIDR_MODID[632]:IPMMUMM00*/ + [602] = {0xFDDC2070U, 0x0000000FU}, /* RGIDR_MODID[633]:DBS0A0*/ + [603] = {0xFDDC2074U, 0x0000000AU}, /* RGIDR_MODID[634]:DBS0A1*/ + [604] = {0xFDDC2078U, 0x0000000FU}, /* RGIDR_MODID[635]:DBS1A0*/ + [605] = {0xFDDC207CU, 0x0000000AU}, /* RGIDR_MODID[636]:DBS1A1*/ + [606] = {0xFDDC2080U, 0x0000000FU}, /* RGIDR_MODID[637]:AXCIDBS*/ + [607] = {0xFDDC2084U, 0x00000009U}, /* RGIDR_MODID[638]:FCPRC*/ + [608] = {0xFDDC2088U, 0x0000000FU}, /* RGIDR_MODID[639]:DBS0D0*/ + [609] = {0xFDDC208CU, 0x0000000AU}, /* RGIDR_MODID[640]:DBS0D1*/ + [610] = {0xFDDC2090U, 0x0000000FU}, /* RGIDR_MODID[641]:DBS1D0*/ + [611] = {0xFDDC2094U, 0x0000000AU}, /* RGIDR_MODID[642]:DBS1D1*/ + [612] = {0xFDDC2098U, 0x0000000EU}, /* RGIDR_MODID[643]:FBADDR*/ + [613] = {0xFDDC209CU, 0x0000004EU}, /* RGIDR_MODID[644]:IPMMUMM01*/ + [614] = {0xFDDC20A0U, 0x0000004EU}, /* RGIDR_MODID[645]:IPMMUMM10*/ + [615] = {0xFDDC20A4U, 0x0000004EU}, /* RGIDR_MODID[646]:IPMMUMM11*/ + [616] = {0xFDDC20A8U, 0x0000004EU}, /* RGIDR_MODID[647]:IPMMUMM12*/ + [617] = {0xFDDC20ACU, 0x0000004EU}, /* RGIDR_MODID[648]:IPMMUMM13*/ + [618] = {0xFDDC20B0U, 0x0000004EU}, /* RGIDR_MODID[649]:IPMMUMM14*/ + [619] = {0xFDDC20B4U, 0x0000004EU}, /* RGIDR_MODID[650]:IPMMUMM15*/ + [620] = {0xFDDC20B8U, 0x0000004EU}, /* RGIDR_MODID[651]:IPMMUMM02*/ + [621] = {0xFDDC20BCU, 0x0000004EU}, /* RGIDR_MODID[652]:IPMMUMM03*/ + [622] = {0xFDDC20C0U, 0x0000004EU}, /* RGIDR_MODID[653]:IPMMUMM04*/ + [623] = {0xFDDC20C4U, 0x0000004EU}, /* RGIDR_MODID[654]:IPMMUMM05*/ + [624] = {0xFDDC20C8U, 0x0000004EU}, /* RGIDR_MODID[655]:IPMMUMM06*/ + [625] = {0xFDDC20CCU, 0x0000004EU}, /* RGIDR_MODID[656]:IPMMUMM07*/ + [626] = {0xFDDC20D0U, 0x0000004EU}, /* RGIDR_MODID[657]:IPMMUMM08*/ + [627] = {0xFDDC20D4U, 0x0000004EU}, /* RGIDR_MODID[658]:IPMMUMM09*/ + [628] = {0xFC802000U, 0x0000000FU}, /* RGIDR_MODID[659]:ARSN0*/ + /* After setting */ /* RGIDR_MODID[660]:ARSN1*/ + /* After setting */ /* RGIDR_MODID[661]:ARSN2*/ + [629] = {0xFC80200CU, 0x0000000FU}, /* RGIDR_MODID[662]:ARSN3*/ + [630] = {0xFC802010U, 0x0000000FU}, /* RGIDR_MODID[663]:ARSN4*/ + [631] = {0xFC802014U, 0x0000000FU}, /* RGIDR_MODID[664]:ARSN5*/ + [632] = {0xFC802018U, 0x0000000FU}, /* RGIDR_MODID[665]:ARSN6*/ + [633] = {0xFC80201CU, 0x00000007U}, /* RGIDR_MODID[666]:ARSN7*/ + [634] = {0xFC802020U, 0x00000000U}, /* RGIDR_MODID[667]:ARSN8*/ + [635] = {0xFC802024U, 0x0000000FU}, /* RGIDR_MODID[668]:ECMTOP3*/ + [636] = {0xFCB52000U, 0x0000000FU}, /* RGIDR_MODID[669]:ARSD00*/ + /* After setting */ /* RGIDR_MODID[670]:ARSD01*/ + /* After setting */ /* RGIDR_MODID[671]:ARSD02*/ + [637] = {0xFCB5200CU, 0x0000000FU}, /* RGIDR_MODID[672]:ARSD03*/ + [638] = {0xFCB52010U, 0x0000000FU}, /* RGIDR_MODID[673]:ARSD04*/ + [639] = {0xFCB52014U, 0x0000000FU}, /* RGIDR_MODID[674]:ARSD05*/ + [640] = {0xFCB52018U, 0x0000000FU}, /* RGIDR_MODID[675]:ARSD06*/ + [641] = {0xFCB5201CU, 0x0000004AU}, /* RGIDR_MODID[676]:AXIFRAY*/ + [642] = {0xFCB52020U, 0x0000000FU}, /* RGIDR_MODID[677]:AXIIPC*/ + [643] = {0xFCB52028U, 0x0000004FU}, /* RGIDR_MODID[678]:AXIRPC*/ + [644] = {0xFCB5202CU, 0x0000000FU}, /* RGIDR_MODID[679]:AXISDHI0*/ + [645] = {0xFCB52030U, 0x0000000FU}, /* RGIDR_MODID[680]:ARSD07*/ + [646] = {0xFCB52034U, 0x00000000U}, /* RGIDR_MODID[681]:ARSD08*/ + [647] = {0xFCB52038U, 0x0000000FU}, /* RGIDR_MODID[682]:ARSP00*/ + /* After setting */ /* RGIDR_MODID[683]:ARSP01*/ + /* After setting */ /* RGIDR_MODID[684]:ARSP02*/ + [648] = {0xFCB52044U, 0x0000000FU}, /* RGIDR_MODID[685]:ARSP03*/ + [649] = {0xFCB52048U, 0x0000000FU}, /* RGIDR_MODID[686]:ARSP04*/ + [650] = {0xFCB5204CU, 0x0000000FU}, /* RGIDR_MODID[687]:ARSP05*/ + [651] = {0xFCB52050U, 0x0000000FU}, /* RGIDR_MODID[688]:ARSP06*/ + [652] = {0xFCB52054U, 0x00000007U}, /* RGIDR_MODID[689]:ARSP07*/ + [653] = {0xFCB52058U, 0x00000000U}, /* RGIDR_MODID[690]:ARSP08*/ + [654] = {0xFCB5205CU, 0x0000004EU}, /* RGIDR_MODID[691]:IPMMUDS001*/ + [655] = {0xFCB52060U, 0x0000000AU}, /* RGIDR_MODID[692]:CKMPER0*/ + [656] = {0xFCB52064U, 0x0000000FU}, /* RGIDR_MODID[693]:ECMPER0*/ + [657] = {0xFCB52068U, 0x0000000EU}, /* RGIDR_MODID[694]:FBAPER0*/ + [658] = {0xFCB5206CU, 0x0000004EU}, /* RGIDR_MODID[695]:FSO0*/ + [659] = {0xFCB52070U, 0x0000004EU}, /* RGIDR_MODID[696]:FSO1*/ + [660] = {0xFCB52074U, 0x0000004EU}, /* RGIDR_MODID[697]:FSO10*/ + [661] = {0xFCB52078U, 0x0000004EU}, /* RGIDR_MODID[698]:FSO2*/ + [662] = {0xFCB5207CU, 0x0000004EU}, /* RGIDR_MODID[699]:FSO3*/ + [663] = {0xFCB52080U, 0x0000004EU}, /* RGIDR_MODID[700]:FSO4*/ + [664] = {0xFCB52084U, 0x0000004EU}, /* RGIDR_MODID[701]:FSO5*/ + [665] = {0xFCB52088U, 0x0000004EU}, /* RGIDR_MODID[702]:FSO6*/ + [666] = {0xFCB5208CU, 0x0000004EU}, /* RGIDR_MODID[703]:FSO7*/ + [667] = {0xFCB52090U, 0x0000004EU}, /* RGIDR_MODID[704]:FSO8*/ + [668] = {0xFCB52094U, 0x0000004EU}, /* RGIDR_MODID[705]:FSO9*/ + [669] = {0xFCB52098U, 0x0000002CU}, /* RGIDR_MODID[706]:ADG*/ + [670] = {0xFCB5209CU, 0x0000000FU}, /* RGIDR_MODID[707]:ECMSD0*/ + [671] = {0xFCB520A0U, 0x0000004EU}, /* RGIDR_MODID[708]:IPMMUDS010*/ + [672] = {0xFCB520A4U, 0x0000004EU}, /* RGIDR_MODID[709]:IPMMUDS011*/ + [673] = {0xFCB520A8U, 0x0000004EU}, /* RGIDR_MODID[710]:I2C0*/ + [674] = {0xFCB520ACU, 0x0000004EU}, /* RGIDR_MODID[711]:I2C1*/ + [675] = {0xFCB520B0U, 0x0000004EU}, /* RGIDR_MODID[712]:I2C2*/ + [676] = {0xFCB520B4U, 0x0000004EU}, /* RGIDR_MODID[713]:I2C3*/ + [677] = {0xFCB520B8U, 0x0000004EU}, /* RGIDR_MODID[714]:I2C4*/ + [678] = {0xFCB520BCU, 0x0000004EU}, /* RGIDR_MODID[715]:I2C5*/ + [679] = {0xFCB520C0U, 0x0000004EU}, /* RGIDR_MODID[716]:IPMMUDS012*/ + [680] = {0xFCB520C4U, 0x0000000FU}, /* RGIDR_MODID[717]:IPC*/ + [681] = {0xFCB520C8U, 0x0000004EU}, /* RGIDR_MODID[718]:IPMMUDS000*/ + [682] = {0xFCB520CCU, 0x0000004EU}, /* RGIDR_MODID[719]:IPMMUDS013*/ + [683] = {0xFCB520D0U, 0x0000004EU}, /* RGIDR_MODID[720]:IPMMUDS014*/ + [684] = {0xFCB520D4U, 0x0000004EU}, /* RGIDR_MODID[721]:IPMMUDS015*/ + [685] = {0xFCB520D8U, 0x0000004EU}, /* RGIDR_MODID[722]:IPMMUDS002*/ + [686] = {0xFCB520DCU, 0x0000004EU}, /* RGIDR_MODID[723]:IPMMUDS003*/ + [687] = {0xFCB520E0U, 0x0000004EU}, /* RGIDR_MODID[724]:IPMMUDS004*/ + [688] = {0xFCB520E4U, 0x0000004EU}, /* RGIDR_MODID[725]:IPMMUDS005*/ + [689] = {0xFCB520E8U, 0x0000002CU}, /* RGIDR_MODID[726]:SSI*/ + [690] = {0xFCB520ECU, 0x0000004EU}, /* RGIDR_MODID[727]:IPMMUDS006*/ + [691] = {0xFCB520F0U, 0x0000004EU}, /* RGIDR_MODID[728]:IPMMUDS007*/ + [692] = {0xFCB520F4U, 0x0000000CU}, /* RGIDR_MODID[729]:SYDM1P*/ + [693] = {0xFCB520F8U, 0x0000004EU}, /* RGIDR_MODID[730]:IPMMUDS008*/ + [694] = {0xFCB520FCU, 0x0000000CU}, /* RGIDR_MODID[731]:SYDM2P*/ + [695] = {0xFCB52100U, 0x0000004EU}, /* RGIDR_MODID[732]:IPMMUDS009*/ + [696] = {0xFCB52240U, 0x0000000CU}, /* RGIDR_MODID[733]:SYDM100*/ + [697] = {0xFCB52244U, 0x0000000CU}, /* RGIDR_MODID[734]:SYDM101*/ + [698] = {0xFCB52248U, 0x0000000CU}, /* RGIDR_MODID[735]:SYDM110*/ + [699] = {0xFCB5224CU, 0x0000000CU}, /* RGIDR_MODID[736]:SYDM111*/ + [700] = {0xFCB52250U, 0x0000000CU}, /* RGIDR_MODID[737]:SYDM112*/ + [701] = {0xFCB52254U, 0x0000000CU}, /* RGIDR_MODID[738]:SYDM113*/ + [702] = {0xFCB52258U, 0x0000000CU}, /* RGIDR_MODID[739]:SYDM114*/ + [703] = {0xFCB5225CU, 0x0000000CU}, /* RGIDR_MODID[740]:SYDM115*/ + [704] = {0xFCB52260U, 0x0000000CU}, /* RGIDR_MODID[741]:SYDM102*/ + [705] = {0xFCB52264U, 0x0000000CU}, /* RGIDR_MODID[742]:SYDM103*/ + [706] = {0xFCB52268U, 0x0000000CU}, /* RGIDR_MODID[743]:SYDM104*/ + [707] = {0xFCB5226CU, 0x0000000CU}, /* RGIDR_MODID[744]:SYDM105*/ + [708] = {0xFCB52270U, 0x0000000CU}, /* RGIDR_MODID[745]:SYDM106*/ + [709] = {0xFCB52274U, 0x0000000CU}, /* RGIDR_MODID[746]:SYDM107*/ + [710] = {0xFCB52278U, 0x0000000CU}, /* RGIDR_MODID[747]:SYDM108*/ + [711] = {0xFCB5227CU, 0x0000000CU}, /* RGIDR_MODID[748]:SYDM109*/ + [712] = {0xFCB52280U, 0x0000000CU}, /* RGIDR_MODID[749]:SYDM200*/ + [713] = {0xFCB52284U, 0x0000000CU}, /* RGIDR_MODID[750]:SYDM201*/ + [714] = {0xFCB52288U, 0x0000000CU}, /* RGIDR_MODID[751]:SYDM210*/ + [715] = {0xFCB5228CU, 0x0000000CU}, /* RGIDR_MODID[752]:SYDM211*/ + [716] = {0xFCB52290U, 0x0000000CU}, /* RGIDR_MODID[753]:SYDM212*/ + [717] = {0xFCB52294U, 0x0000000CU}, /* RGIDR_MODID[754]:SYDM213*/ + [718] = {0xFCB52298U, 0x0000000CU}, /* RGIDR_MODID[755]:SYDM214*/ + [719] = {0xFCB5229CU, 0x0000000CU}, /* RGIDR_MODID[756]:SYDM215*/ + [720] = {0xFCB522A0U, 0x0000000CU}, /* RGIDR_MODID[757]:SYDM202*/ + [721] = {0xFCB522A4U, 0x0000000CU}, /* RGIDR_MODID[758]:SYDM203*/ + [722] = {0xFCB522A8U, 0x0000000CU}, /* RGIDR_MODID[759]:SYDM204*/ + [723] = {0xFCB522ACU, 0x0000000CU}, /* RGIDR_MODID[760]:SYDM205*/ + [724] = {0xFCB522B0U, 0x0000000CU}, /* RGIDR_MODID[761]:SYDM206*/ + [725] = {0xFCB522B4U, 0x0000000CU}, /* RGIDR_MODID[762]:SYDM207*/ + [726] = {0xFCB522B8U, 0x0000000CU}, /* RGIDR_MODID[763]:SYDM208*/ + [727] = {0xFCB522BCU, 0x0000000CU}, /* RGIDR_MODID[764]:SYDM209*/ + [728] = {0xFC682000U, 0x0000000FU}, /* RGIDR_MODID[765]:ARVC0*/ + /* After setting */ /* RGIDR_MODID[766]:ARVC1*/ + /* After setting */ /* RGIDR_MODID[767]:ARVC2*/ + [729] = {0xFC68200CU, 0x0000000FU}, /* RGIDR_MODID[768]:ARVC3*/ + [730] = {0xFC682010U, 0x0000000EU}, /* RGIDR_MODID[769]:AXIFBABUSVC*/ + [731] = {0xFC682014U, 0x0000000FU}, /* RGIDR_MODID[770]:ARVC4*/ + [732] = {0xFC682018U, 0x0000000FU}, /* RGIDR_MODID[771]:ARVC5*/ + [733] = {0xFC68201CU, 0x0000000FU}, /* RGIDR_MODID[772]:ARVC6*/ + [734] = {0xFC682020U, 0x0000000FU}, /* RGIDR_MODID[773]:ARVC7*/ + [735] = {0xFC682024U, 0x00000000U}, /* RGIDR_MODID[774]:ARVC8*/ + [736] = {0xFC682028U, 0x0000000AU}, /* RGIDR_MODID[775]:CKMVC*/ + [737] = {0xFC68202CU, 0x0000000FU}, /* RGIDR_MODID[776]:ECMVC0*/ + [738] = {0xFC682030U, 0x0000004EU}, /* RGIDR_MODID[777]:IMR2*/ + [739] = {0xFC682034U, 0x0000004EU}, /* RGIDR_MODID[778]:IMR0*/ + [740] = {0xFC682038U, 0x0000004EU}, /* RGIDR_MODID[779]:IMR1*/ + [741] = {0xFC68203CU, 0x0000004EU}, /* RGIDR_MODID[780]:IPMMUVC01*/ + [742] = {0xFC682040U, 0x0000004EU}, /* RGIDR_MODID[781]:IPMMUVC10*/ + [743] = {0xFC682044U, 0x0000000CU}, /* RGIDR_MODID[782]:IMS0*/ + [744] = {0xFC682048U, 0x0000000CU}, /* RGIDR_MODID[783]:IMS1*/ + [745] = {0xFC68204CU, 0x0000004EU}, /* RGIDR_MODID[784]:IPMMUVC00*/ + [746] = {0xFC682050U, 0x0000004EU}, /* RGIDR_MODID[785]:IPMMUVC11*/ + [747] = {0xFC682054U, 0x0000004EU}, /* RGIDR_MODID[786]:IPMMUVC12*/ + [748] = {0xFC682058U, 0x0000004EU}, /* RGIDR_MODID[787]:IPMMUVC13*/ + [749] = {0xFC68205CU, 0x0000004EU}, /* RGIDR_MODID[788]:IPMMUVC14*/ + [750] = {0xFC682060U, 0x0000004EU}, /* RGIDR_MODID[789]:IPMMUVC15*/ + [751] = {0xFC682064U, 0x0000004EU}, /* RGIDR_MODID[790]:IPMMUVC02*/ + [752] = {0xFC682068U, 0x0000004EU}, /* RGIDR_MODID[791]:IPMMUVC03*/ + [753] = {0xFC68206CU, 0x0000004EU}, /* RGIDR_MODID[792]:IPMMUVC04*/ + [754] = {0xFC682070U, 0x0000004EU}, /* RGIDR_MODID[793]:IPMMUVC05*/ + [755] = {0xFC682074U, 0x0000004EU}, /* RGIDR_MODID[794]:IPMMUVC06*/ + [756] = {0xFC682078U, 0x0000004EU}, /* RGIDR_MODID[795]:IPMMUVC07*/ + [757] = {0xFC68207CU, 0x0000004EU}, /* RGIDR_MODID[796]:IPMMUVC08*/ + [758] = {0xFC682080U, 0x0000004EU}, /* RGIDR_MODID[797]:IPMMUVC09*/ + [759] = {0xFC682084U, 0x00000028U}, /* RGIDR_MODID[798]:IV1ES*/ + [760] = {0xFEBE2000U, 0x0000004EU}, /* RGIDR_MODID[799]:CSITOP0*/ + [761] = {0xFEBE2004U, 0x0000000FU}, /* RGIDR_MODID[800]:ARVI10*/ + /* After setting */ /* RGIDR_MODID[801]:ARVI11*/ + /* After setting */ /* RGIDR_MODID[802]:ARVI12*/ + [762] = {0xFEBE2010U, 0x0000000FU}, /* RGIDR_MODID[803]:ARVI13*/ + [763] = {0xFEBE2014U, 0x0000000FU}, /* RGIDR_MODID[804]:ARVI14*/ + [764] = {0xFEBE2018U, 0x0000000FU}, /* RGIDR_MODID[805]:ARVI15*/ + [765] = {0xFEBE201CU, 0x0000000FU}, /* RGIDR_MODID[806]:ARVI16*/ + [766] = {0xFEBE2020U, 0x0000000FU}, /* RGIDR_MODID[807]:ARVI17*/ + [767] = {0xFEBE2024U, 0x00000000U}, /* RGIDR_MODID[808]:ARVI18*/ + [768] = {0xFEBE2028U, 0x0000000AU}, /* RGIDR_MODID[809]:CKMVIO*/ + [769] = {0xFEBE202CU, 0x0000004EU}, /* RGIDR_MODID[810]:CSITOP1*/ + [770] = {0xFEBE2034U, 0x0000004EU}, /* RGIDR_MODID[811]:DSITLINK0*/ + [771] = {0xFEBE2038U, 0x0000004EU}, /* RGIDR_MODID[812]:DSITLINK1*/ + [772] = {0xFEBE203CU, 0x0000000FU}, /* RGIDR_MODID[813]:ECMVIO1*/ + [773] = {0xFEBE2044U, 0x0000004EU}, /* RGIDR_MODID[814]:IPMMUVI001*/ + [774] = {0xFEBE2048U, 0x0000000CU}, /* RGIDR_MODID[815]:FCPVX0*/ + [775] = {0xFEBE204CU, 0x0000000CU}, /* RGIDR_MODID[816]:FCPVX1*/ + [776] = {0xFEBE2058U, 0x0000004EU}, /* RGIDR_MODID[817]:IPMMUVI000*/ + [777] = {0xFEBE205CU, 0x0000004EU}, /* RGIDR_MODID[818]:IPMMUVI100*/ + [778] = {0xFEBE2060U, 0x0000004EU}, /* RGIDR_MODID[819]:IPMMUVI010*/ + [779] = {0xFEBE2064U, 0x0000004EU}, /* RGIDR_MODID[820]:IPMMUVI011*/ + [780] = {0xFEBE2068U, 0x0000004EU}, /* RGIDR_MODID[821]:VSPX0*/ + [781] = {0xFEBE206CU, 0x0000004EU}, /* RGIDR_MODID[822]:VSPX1*/ + [782] = {0xFEBE2078U, 0x0000004EU}, /* RGIDR_MODID[823]:IPMMUVI012*/ + [783] = {0xFEBE207CU, 0x0000004EU}, /* RGIDR_MODID[824]:IPMMUVI013*/ + [784] = {0xFEBE2080U, 0x0000004EU}, /* RGIDR_MODID[825]:IPMMUVI014*/ + [785] = {0xFEBE2084U, 0x0000004EU}, /* RGIDR_MODID[826]:IPMMUVI015*/ + [786] = {0xFEBE2088U, 0x0000004EU}, /* RGIDR_MODID[827]:IPMMUVI002*/ + [787] = {0xFEBE208CU, 0x0000004EU}, /* RGIDR_MODID[828]:IPMMUVI003*/ + [788] = {0xFEBE2090U, 0x0000004EU}, /* RGIDR_MODID[829]:IPMMUVI004*/ + [789] = {0xFEBE2094U, 0x0000004EU}, /* RGIDR_MODID[830]:IPMMUVI005*/ + [790] = {0xFEBE2098U, 0x0000004EU}, /* RGIDR_MODID[831]:IPMMUVI006*/ + [791] = {0xFEBE209CU, 0x0000004EU}, /* RGIDR_MODID[832]:IPMMUVI007*/ + [792] = {0xFEBE20A0U, 0x0000004EU}, /* RGIDR_MODID[833]:IPMMUVI008*/ + [793] = {0xFEBE20A4U, 0x0000004EU}, /* RGIDR_MODID[834]:IPMMUVI009*/ + [794] = {0xFEBE20A8U, 0x0000004EU}, /* RGIDR_MODID[835]:IPMMUVI101*/ + [795] = {0xFEBE20ACU, 0x0000004EU}, /* RGIDR_MODID[836]:IPMMUVI110*/ + [796] = {0xFEBE20B0U, 0x0000004EU}, /* RGIDR_MODID[837]:IPMMUVI111*/ + [797] = {0xFEBE20B4U, 0x0000004EU}, /* RGIDR_MODID[838]:IPMMUVI112*/ + [798] = {0xFEBE20B8U, 0x0000004EU}, /* RGIDR_MODID[839]:IPMMUVI113*/ + [799] = {0xFEBE20BCU, 0x0000004EU}, /* RGIDR_MODID[840]:IPMMUVI114*/ + [800] = {0xFEBE20C0U, 0x0000004EU}, /* RGIDR_MODID[841]:IPMMUVI115*/ + [801] = {0xFEBE20C4U, 0x0000004EU}, /* RGIDR_MODID[842]:IPMMUVI102*/ + [802] = {0xFEBE20C8U, 0x0000004EU}, /* RGIDR_MODID[843]:IPMMUVI103*/ + [803] = {0xFEBE20CCU, 0x0000004EU}, /* RGIDR_MODID[844]:IPMMUVI104*/ + [804] = {0xFEBE20D0U, 0x0000004EU}, /* RGIDR_MODID[845]:IPMMUVI105*/ + [805] = {0xFEBE20D4U, 0x0000004EU}, /* RGIDR_MODID[846]:IPMMUVI106*/ + [806] = {0xFEBE20D8U, 0x0000004EU}, /* RGIDR_MODID[847]:IPMMUVI107*/ + [807] = {0xFEBE20DCU, 0x0000004EU}, /* RGIDR_MODID[848]:IPMMUVI108*/ + [808] = {0xFEBE20E0U, 0x0000004EU}, /* RGIDR_MODID[849]:IPMMUVI109*/ + [809] = {0xFEBE2104U, 0x0000000EU}, /* RGIDR_MODID[850]:AXIFBABUSVIO*/ + [810] = {0xFEBF2000U, 0x0000000FU}, /* RGIDR_MODID[851]:ARVI0*/ + /* After setting */ /* RGIDR_MODID[852]:ARVI1*/ + /* After setting */ /* RGIDR_MODID[853]:ARVI2*/ + [811] = {0xFEBF200CU, 0x0000000FU}, /* RGIDR_MODID[854]:ARVI3*/ + [812] = {0xFEBF2010U, 0x0000000FU}, /* RGIDR_MODID[855]:ARVI4*/ + [813] = {0xFEBF2014U, 0x0000000FU}, /* RGIDR_MODID[856]:ARVI5*/ + [814] = {0xFEBF2018U, 0x0000000FU}, /* RGIDR_MODID[857]:ARVI6*/ + [815] = {0xFEBF201CU, 0x0000000FU}, /* RGIDR_MODID[858]:ARVI7*/ + [816] = {0xFEBF2020U, 0x00000000U}, /* RGIDR_MODID[859]:ARVI8*/ + [817] = {0xFEBF2024U, 0x0000000FU}, /* RGIDR_MODID[860]:ECMVIO0*/ + [818] = {0xFEBF2028U, 0x0000004EU}, /* RGIDR_MODID[861]:ISP0*/ + [819] = {0xFEBF202CU, 0x0000004EU}, /* RGIDR_MODID[862]:ISP0CORE*/ + [820] = {0xFEBF2030U, 0x0000004EU}, /* RGIDR_MODID[863]:ISP1*/ + [821] = {0xFEBF2034U, 0x0000004EU}, /* RGIDR_MODID[864]:ISP1CORE*/ + [822] = {0xFEBF2054U, 0x0000004EU}, /* RGIDR_MODID[865]:VIN00*/ + [823] = {0xFEBF2058U, 0x0000004EU}, /* RGIDR_MODID[866]:VIN01*/ + [824] = {0xFEBF205CU, 0x0000004EU}, /* RGIDR_MODID[867]:VIN02*/ + [825] = {0xFEBF2060U, 0x0000004EU}, /* RGIDR_MODID[868]:VIN03*/ + [826] = {0xFEBF2064U, 0x0000004EU}, /* RGIDR_MODID[869]:VIN04*/ + [827] = {0xFEBF2068U, 0x0000004EU}, /* RGIDR_MODID[870]:VIN05*/ + [828] = {0xFEBF206CU, 0x0000004EU}, /* RGIDR_MODID[871]:VIN06*/ + [829] = {0xFEBF2070U, 0x0000004EU}, /* RGIDR_MODID[872]:VIN07*/ + [830] = {0xFEBF2074U, 0x0000004EU}, /* RGIDR_MODID[873]:VIN10*/ + [831] = {0xFEBF2078U, 0x0000004EU}, /* RGIDR_MODID[874]:VIN11*/ + [832] = {0xFEBF207CU, 0x0000004EU}, /* RGIDR_MODID[875]:VIN12*/ + [833] = {0xFEBF2080U, 0x0000004EU}, /* RGIDR_MODID[876]:VIN13*/ + [834] = {0xFEBF2084U, 0x0000004EU}, /* RGIDR_MODID[877]:VIN14*/ + [835] = {0xFEBF2088U, 0x0000004EU}, /* RGIDR_MODID[878]:VIN15*/ + [836] = {0xFEBF208CU, 0x0000004EU}, /* RGIDR_MODID[879]:VIN16*/ + [837] = {0xFEBF2090U, 0x0000004EU}, /* RGIDR_MODID[880]:VIN17*/ + [838] = {0xFC312000U, 0x0000000FU}, /* RGIDR_MODID[881]:ARVIP00*/ + /* After setting */ /* RGIDR_MODID[882]:ARVIP01*/ + /* After setting */ /* RGIDR_MODID[883]:ARVIP02*/ + [839] = {0xFC31200CU, 0x0000000FU}, /* RGIDR_MODID[884]:ARVIP03*/ + [840] = {0xFC312010U, 0x0000000EU}, /* RGIDR_MODID[885]:AXIFBABUSVIP0*/ + [841] = {0xFC312014U, 0x0000000FU}, /* RGIDR_MODID[886]:ARVIP04*/ + [842] = {0xFC312018U, 0x0000000FU}, /* RGIDR_MODID[887]:ARVIP05*/ + [843] = {0xFC31201CU, 0x0000000FU}, /* RGIDR_MODID[888]:ARVIP06*/ + [844] = {0xFC312020U, 0x00000007U}, /* RGIDR_MODID[889]:ARVIP07*/ + [845] = {0xFC312024U, 0x00000000U}, /* RGIDR_MODID[890]:ARVIP08*/ + [846] = {0xFC312028U, 0x0000000AU}, /* RGIDR_MODID[891]:CKMVIP*/ + [847] = {0xFC31202CU, 0x0000000FU}, /* RGIDR_MODID[892]:ECMVIP0*/ + [848] = {0xFC312030U, 0x0000004EU}, /* RGIDR_MODID[893]:IPMMUVIP000*/ + [849] = {0xFC312038U, 0x0000004EU}, /* RGIDR_MODID[894]:SMPO0*/ + [850] = {0xFC31203CU, 0x0000004EU}, /* RGIDR_MODID[895]:SMPS0*/ + [851] = {0xFC312040U, 0x0000000CU}, /* RGIDR_MODID[896]:UMFL0*/ + [852] = {0xFC312044U, 0x0000004EU}, /* RGIDR_MODID[897]:IPMMUVIP001*/ + [853] = {0xFC312048U, 0x0000004EU}, /* RGIDR_MODID[898]:IPMMUVIP010*/ + [854] = {0xFC31204CU, 0x0000004EU}, /* RGIDR_MODID[899]:IPMMUVIP011*/ + [855] = {0xFC312050U, 0x0000004EU}, /* RGIDR_MODID[900]:UMFL0M_W*/ + [856] = {0xFC312054U, 0x0000004EU}, /* RGIDR_MODID[901]:IPMMUVIP012*/ + [857] = {0xFC312058U, 0x0000004EU}, /* RGIDR_MODID[902]:IPMMUVIP013*/ + [858] = {0xFC31205CU, 0x0000004EU}, /* RGIDR_MODID[903]:IPMMUVIP014*/ + [859] = {0xFC312060U, 0x0000004EU}, /* RGIDR_MODID[904]:IPMMUVIP015*/ + [860] = {0xFC312064U, 0x0000004EU}, /* RGIDR_MODID[905]:IPMMUVIP002*/ + [861] = {0xFC312068U, 0x0000004EU}, /* RGIDR_MODID[906]:IPMMUVIP003*/ + [862] = {0xFC31206CU, 0x0000004EU}, /* RGIDR_MODID[907]:IPMMUVIP004*/ + [863] = {0xFC312070U, 0x0000004EU}, /* RGIDR_MODID[908]:IPMMUVIP005*/ + [864] = {0xFC312074U, 0x0000004EU}, /* RGIDR_MODID[909]:IPMMUVIP006*/ + [865] = {0xFC312078U, 0x0000004EU}, /* RGIDR_MODID[910]:IPMMUVIP007*/ + [866] = {0xFC31207CU, 0x0000004EU}, /* RGIDR_MODID[911]:IPMMUVIP008*/ + [867] = {0xFC312080U, 0x0000004EU}, /* RGIDR_MODID[912]:IPMMUVIP009*/ + [868] = {0xFC342000U, 0x0000000FU}, /* RGIDR_MODID[913]:ARVIP10*/ + /* After setting */ /* RGIDR_MODID[914]:ARVIP11*/ + /* After setting */ /* RGIDR_MODID[915]:ARVIP12*/ + [869] = {0xFC34200CU, 0x0000000FU}, /* RGIDR_MODID[916]:ARVIP13*/ + [870] = {0xFC342010U, 0x0000000EU}, /* RGIDR_MODID[917]:AXIFBABUSVIP1*/ + [871] = {0xFC342014U, 0x0000000FU}, /* RGIDR_MODID[918]:ARVIIP14*/ + [872] = {0xFC342018U, 0x0000000FU}, /* RGIDR_MODID[919]:ARVIIP15*/ + [873] = {0xFC34201CU, 0x0000000FU}, /* RGIDR_MODID[920]:ARVIIP16*/ + [874] = {0xFC342020U, 0x0000000FU}, /* RGIDR_MODID[921]:ARVIIP17*/ + [875] = {0xFC342024U, 0x00000000U}, /* RGIDR_MODID[922]:ARVIIP18*/ + [876] = {0xFC342038U, 0x0000000FU}, /* RGIDR_MODID[923]:ECMVIP1*/ + [877] = {0xFC34203CU, 0x0000004EU}, /* RGIDR_MODID[924]:IPMMUVIP101*/ + [878] = {0xFC342040U, 0x0000004EU}, /* RGIDR_MODID[925]:IPMMUVIP100*/ + [879] = {0xFC342044U, 0x0000004EU}, /* RGIDR_MODID[926]:IPMMUVIP110*/ + [880] = {0xFC342048U, 0x0000004EU}, /* RGIDR_MODID[927]:IPMMUVIP111*/ + [881] = {0xFC34204CU, 0x0000004EU}, /* RGIDR_MODID[928]:IPMMUVIP112*/ + [882] = {0xFC342050U, 0x0000004EU}, /* RGIDR_MODID[929]:IPMMUVIP113*/ + [883] = {0xFC342054U, 0x0000004EU}, /* RGIDR_MODID[930]:IPMMUVIP114*/ + [884] = {0xFC342058U, 0x0000004EU}, /* RGIDR_MODID[931]:IPMMUVIP115*/ + [885] = {0xFC34205CU, 0x0000004EU}, /* RGIDR_MODID[932]:IPMMUVIP102*/ + [886] = {0xFC342060U, 0x0000004EU}, /* RGIDR_MODID[933]:IPMMUVIP103*/ + [887] = {0xFC342064U, 0x0000004EU}, /* RGIDR_MODID[934]:IPMMUVIP104*/ + [888] = {0xFC342068U, 0x0000004EU}, /* RGIDR_MODID[935]:IPMMUVIP105*/ + [889] = {0xFC34206CU, 0x0000004EU}, /* RGIDR_MODID[936]:IPMMUVIP106*/ + [890] = {0xFC342070U, 0x0000004EU}, /* RGIDR_MODID[937]:IPMMUVIP107*/ + [891] = {0xFC342074U, 0x0000004EU}, /* RGIDR_MODID[938]:IPMMUVIP108*/ + [892] = {0xFC342078U, 0x0000004EU}, /* RGIDR_MODID[939]:IPMMUVIP109*/ + [893] = {0xFC342118U, 0x00000004U}, /* RGIDR_MODID[940]:PAP*/ + [894] = {0xFC402000U, 0x0000000FU}, /* RGIDR_MODID[941]:ARDSP0*/ + /* After setting */ /* RGIDR_MODID[942]:ARDSP1*/ + /* After setting */ /* RGIDR_MODID[943]:ARDSP2*/ + [895] = {0xFC40200CU, 0x0000000FU}, /* RGIDR_MODID[944]:ARDSP3*/ + [896] = {0xFC402010U, 0x0000000FU}, /* RGIDR_MODID[945]:ARDSP4*/ + [897] = {0xFC402014U, 0x0000000FU}, /* RGIDR_MODID[946]:ARDSP5*/ + [898] = {0xFC402018U, 0x0000000FU}, /* RGIDR_MODID[947]:ARDSP6*/ + [899] = {0xFC40201CU, 0x0000000FU}, /* RGIDR_MODID[948]:ARDSP7*/ + [900] = {0xFC402020U, 0x0000000FU}, /* RGIDR_MODID[949]:ECMDSP*/ + [901] = {0xFC402024U, 0x0000000CU}, /* RGIDR_MODID[950]:AXIDSP0*/ + [902] = {0xFC402028U, 0x0000000CU}, /* RGIDR_MODID[951]:AXIDSP1*/ + [903] = {0xFC40202CU, 0x0000000CU}, /* RGIDR_MODID[952]:AXIDSP2*/ + [904] = {0xFC402030U, 0x0000000CU}, /* RGIDR_MODID[953]:AXIDSP3*/ + [906] = {0xFDDB9660U, 0x0000000FU}, /* RGIDR_MODID[954]:ARCC*/ + [905] = {0xFDDB9674U, 0x0000000FU}, /* RGIDR_MODID[955]:ARRTRAM*/ + [907] = {0xFCB52024U, 0x00000000U}, /* RGIDR_MODID[956]:RSV0*/ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_w_tbl" +const REGION_ID_SETTING_TABLE g_rgid_w_tbl[] = { + [0] = {0xFD482400U, 0x0000000EU}, /* RGIDW_MODID[0]:ARMGC0*/ + [1] = {0xFD482404U, 0x0000000EU}, /* RGIDW_MODID[1]:ARMGC1*/ + [2] = {0xFD482408U, 0x00000000U}, /* RGIDW_MODID[2]:ARMGC2*/ + [3] = {0xFD48240CU, 0x00000002U}, /* RGIDW_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDW_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDW_MODID[5]:ARRT02*/ + [4] = {0xFD482418U, 0x00000001U}, /* RGIDW_MODID[6]:ARRT03*/ + [5] = {0xFD48241CU, 0x00000002U}, /* RGIDW_MODID[7]:ARRT04*/ + [6] = {0xFD482420U, 0x00000001U}, /* RGIDW_MODID[8]:ARRT05*/ + [7] = {0xFD482424U, 0x00000002U}, /* RGIDW_MODID[9]:ARRT06*/ + [8] = {0xFD482428U, 0x00000002U}, /* RGIDW_MODID[10]:ARRT07*/ + [9] = {0xFD48242CU, 0x00000000U}, /* RGIDW_MODID[11]:ARRT08*/ + [10] = {0xFD482430U, 0x00000001U}, /* RGIDW_MODID[12]:LIFEC0*/ + [11] = {0xFD482434U, 0x0000000EU}, /* RGIDW_MODID[13]:SWDT*/ + [12] = {0xFD482438U, 0x0000006EU}, /* RGIDW_MODID[14]:TMU0*/ + [13] = {0xFD48243CU, 0x0000000EU}, /* RGIDW_MODID[15]:WDT*/ + [14] = {0xFD482440U, 0x0000000EU}, /* RGIDW_MODID[16]:WWDT0*/ + [15] = {0xFD482444U, 0x0000000EU}, /* RGIDW_MODID[17]:WWDT1*/ + [16] = {0xFD482448U, 0x0000000EU}, /* RGIDW_MODID[18]:WWDT2*/ + [17] = {0xFD48244CU, 0x0000000EU}, /* RGIDW_MODID[19]:WWDT3*/ + [18] = {0xFD482450U, 0x0000000EU}, /* RGIDW_MODID[20]:WWDT4*/ + [19] = {0xFD482454U, 0x0000000EU}, /* RGIDW_MODID[21]:WWDT5*/ + [20] = {0xFD482458U, 0x0000000EU}, /* RGIDW_MODID[22]:WWDT6*/ + [21] = {0xFD482468U, 0x0000000AU}, /* RGIDW_MODID[23]:ECMRT3*/ + [22] = {0xFDA02400U, 0x00000006U}, /* RGIDW_MODID[24]:ADVFSC*/ + [23] = {0xFDA02404U, 0x0000000FU}, /* RGIDW_MODID[25]:APMU0*/ + [24] = {0xFDA02408U, 0x00000002U}, /* RGIDW_MODID[26]:APMU1*/ + [25] = {0xFDA0240CU, 0x00000000U}, /* RGIDW_MODID[27]:APMU10*/ + [26] = {0xFDA02410U, 0x00000000U}, /* RGIDW_MODID[28]:APMU11*/ + [27] = {0xFDA02414U, 0x00000000U}, /* RGIDW_MODID[29]:APMU12*/ + [28] = {0xFDA02418U, 0x00000000U}, /* RGIDW_MODID[30]:APMU13*/ + [29] = {0xFDA0241CU, 0x00000000U}, /* RGIDW_MODID[31]:APMU14*/ + [30] = {0xFDA02420U, 0x00000000U}, /* RGIDW_MODID[32]:APMU15*/ + [31] = {0xFDA02424U, 0x00000004U}, /* RGIDW_MODID[33]:APMU2*/ + [32] = {0xFDA02428U, 0x00000004U}, /* RGIDW_MODID[34]:APMU3*/ + [33] = {0xFDA0242CU, 0x00000000U}, /* RGIDW_MODID[35]:APMU4*/ + [34] = {0xFDA02430U, 0x00000000U}, /* RGIDW_MODID[36]:APMU5*/ + [35] = {0xFDA02434U, 0x00000000U}, /* RGIDW_MODID[37]:APMU6*/ + [36] = {0xFDA02438U, 0x00000000U}, /* RGIDW_MODID[38]:APMU7*/ + [37] = {0xFDA0243CU, 0x00000000U}, /* RGIDW_MODID[39]:APMU8*/ + [38] = {0xFDA02440U, 0x00000000U}, /* RGIDW_MODID[40]:APMU9*/ + [39] = {0xFDA02444U, 0x00000002U}, /* RGIDW_MODID[41]:ARS00*/ + /* After setting */ /* RGIDW_MODID[42]:ARS01*/ + /* After setting */ /* RGIDW_MODID[43]:ARS02*/ + [40] = {0xFDA02450U, 0x00000001U}, /* RGIDW_MODID[44]:ARS03*/ + [41] = {0xFDA02454U, 0x00000002U}, /* RGIDW_MODID[45]:ARS04*/ + [42] = {0xFDA02458U, 0x00000001U}, /* RGIDW_MODID[46]:ARS05*/ + [43] = {0xFDA0245CU, 0x00000002U}, /* RGIDW_MODID[47]:ARS06*/ + [44] = {0xFDA02460U, 0x00000002U}, /* RGIDW_MODID[48]:ARS07*/ + [45] = {0xFDA02464U, 0x00000000U}, /* RGIDW_MODID[49]:ARS08*/ + [46] = {0xFDA02468U, 0x0000000EU}, /* RGIDW_MODID[50]:CMT0*/ + [47] = {0xFDA0246CU, 0x0000000EU}, /* RGIDW_MODID[51]:CMT1*/ + [48] = {0xFDA02470U, 0x0000000EU}, /* RGIDW_MODID[52]:CMT2*/ + [49] = {0xFDA02474U, 0x0000000EU}, /* RGIDW_MODID[53]:CMT3*/ + [50] = {0xFDA02478U, 0x0000000AU}, /* RGIDW_MODID[54]:CKM*/ + [51] = {0xFDA0247CU, 0x0000000EU}, /* RGIDW_MODID[55]:DBE*/ + [52] = {0xFDA02480U, 0x0000000EU}, /* RGIDW_MODID[56]:IRQC*/ + [53] = {0xFDA02484U, 0x0000000AU}, /* RGIDW_MODID[57]:ECMPS0*/ + [54] = {0xFDA02488U, 0x0000000BU}, /* RGIDW_MODID[58]:OTP0*/ + [55] = {0xFDA0248CU, 0x0000000FU}, /* RGIDW_MODID[59]:OTP1*/ + [56] = {0xFDA0249CU, 0x0000000EU}, /* RGIDW_MODID[60]:SCMT*/ + [57] = {0xFDA024A8U, 0x0000004AU}, /* RGIDW_MODID[61]:TSC1*/ + [58] = {0xFDA024ACU, 0x0000004AU}, /* RGIDW_MODID[62]:TSC2*/ + [59] = {0xFDA024B0U, 0x0000004AU}, /* RGIDW_MODID[63]:TSC3*/ + [60] = {0xFDA024B4U, 0x0000004AU}, /* RGIDW_MODID[64]:TSC4*/ + [61] = {0xFDA024B8U, 0x00000006U}, /* RGIDW_MODID[65]:UCMT*/ + [62] = {0xFDA02500U, 0x0000006FU}, /* RGIDW_MODID[66]:CPG0*/ + [63] = {0xFDA02504U, 0x0000000AU}, /* RGIDW_MODID[67]:CPG1*/ + [64] = {0xFDA02508U, 0x0000004EU}, /* RGIDW_MODID[68]:CPG2*/ + [65] = {0xFDA0250CU, 0x00000028U}, /* RGIDW_MODID[69]:CPG3*/ + [66] = {0xFDA02510U, 0x0000006FU}, /* RGIDW_MODID[70]:PFC00*/ + [67] = {0xFDA02514U, 0x0000000AU}, /* RGIDW_MODID[71]:PFC01*/ + [68] = {0xFDA02518U, 0x0000004EU}, /* RGIDW_MODID[72]:PFC02*/ + [69] = {0xFDA0251CU, 0x00000028U}, /* RGIDW_MODID[73]:PFC03*/ + [70] = {0xFDA02520U, 0x0000006FU}, /* RGIDW_MODID[74]:PFC10*/ + [71] = {0xFDA02524U, 0x0000000AU}, /* RGIDW_MODID[75]:PFC11*/ + [72] = {0xFDA02528U, 0x0000004EU}, /* RGIDW_MODID[76]:PFC12*/ + [73] = {0xFDA0252CU, 0x00000028U}, /* RGIDW_MODID[77]:PFC13*/ + [74] = {0xFDA02530U, 0x0000006FU}, /* RGIDW_MODID[78]:PFC20*/ + [75] = {0xFDA02534U, 0x0000000AU}, /* RGIDW_MODID[79]:PFC21*/ + [76] = {0xFDA02538U, 0x0000004EU}, /* RGIDW_MODID[80]:PFC22*/ + [77] = {0xFDA0253CU, 0x00000028U}, /* RGIDW_MODID[81]:PFC23*/ + [78] = {0xFDA02540U, 0x0000006FU}, /* RGIDW_MODID[82]:PFC30*/ + [79] = {0xFDA02544U, 0x0000000AU}, /* RGIDW_MODID[83]:PFC31*/ + [80] = {0xFDA02548U, 0x0000004EU}, /* RGIDW_MODID[84]:PFC32*/ + [81] = {0xFDA0254CU, 0x00000028U}, /* RGIDW_MODID[85]:PFC33*/ + [82] = {0xFDA02550U, 0x0000006FU}, /* RGIDW_MODID[86]:PFCS0*/ + [83] = {0xFDA02554U, 0x0000000AU}, /* RGIDW_MODID[87]:PFCS1*/ + [84] = {0xFDA02558U, 0x0000004EU}, /* RGIDW_MODID[88]:PFCS2*/ + [85] = {0xFDA0255CU, 0x00000028U}, /* RGIDW_MODID[89]:PFCS3*/ + [86] = {0xFDA02560U, 0x0000006FU}, /* RGIDW_MODID[90]:RESET0*/ + [87] = {0xFDA02564U, 0x0000000AU}, /* RGIDW_MODID[91]:RESET1*/ + [88] = {0xFDA02568U, 0x0000004EU}, /* RGIDW_MODID[92]:RESET2*/ + [89] = {0xFDA0256CU, 0x00000028U}, /* RGIDW_MODID[93]:RESET3*/ + [90] = {0xFDA02570U, 0x0000006FU}, /* RGIDW_MODID[94]:SYS0*/ + [91] = {0xFDA02574U, 0x0000000AU}, /* RGIDW_MODID[95]:SYS1*/ + [92] = {0xFDA02578U, 0x0000004EU}, /* RGIDW_MODID[96]:SYS2*/ + [93] = {0xFDA0257CU, 0x00000028U}, /* RGIDW_MODID[97]:SYS3*/ + [94] = {0xFCB62400U, 0x0000000EU}, /* RGIDW_MODID[98]:DMAMSI0*/ + [95] = {0xFCB62404U, 0x0000000EU}, /* RGIDW_MODID[99]:DMAMSI1*/ + [96] = {0xFCB62408U, 0x0000000EU}, /* RGIDW_MODID[100]:DMAMSI2*/ + [97] = {0xFCB6240CU, 0x0000000EU}, /* RGIDW_MODID[101]:DMAMSI3*/ + [98] = {0xFCB62410U, 0x0000000EU}, /* RGIDW_MODID[102]:DMAMSI4*/ + [99] = {0xFCB62414U, 0x0000000EU}, /* RGIDW_MODID[103]:DMAMSI5*/ + [100] = {0xFCB62418U, 0x0000000AU}, /* RGIDW_MODID[104]:ECMSP3*/ + [101] = {0xFCB62424U, 0x00000002U}, /* RGIDW_MODID[105]:ARSP30*/ + /* After setting */ /* RGIDW_MODID[106]:ARSP31*/ + /* After setting */ /* RGIDW_MODID[107]:ARSP32*/ + [102] = {0xFCB62430U, 0x00000001U}, /* RGIDW_MODID[108]:ARSP33*/ + [103] = {0xFCB62434U, 0x00000002U}, /* RGIDW_MODID[109]:ARSP34*/ + [104] = {0xFCB62438U, 0x00000001U}, /* RGIDW_MODID[110]:ARSP35*/ + [105] = {0xFCB6243CU, 0x00000002U}, /* RGIDW_MODID[111]:ARSP36*/ + [106] = {0xFCB62440U, 0x00000002U}, /* RGIDW_MODID[112]:ARSP37*/ + [107] = {0xFCB62444U, 0x00000000U}, /* RGIDW_MODID[113]:ARSP38*/ + [108] = {0xFCB62448U, 0x0000000EU}, /* RGIDW_MODID[114]:MSI0*/ + [109] = {0xFCB6244CU, 0x0000000EU}, /* RGIDW_MODID[115]:MSI1*/ + [110] = {0xFCB62450U, 0x0000000EU}, /* RGIDW_MODID[116]:MSI2*/ + [111] = {0xFCB62454U, 0x0000000EU}, /* RGIDW_MODID[117]:MSI3*/ + [112] = {0xFCB62458U, 0x0000000EU}, /* RGIDW_MODID[118]:MSI4*/ + [113] = {0xFCB6245CU, 0x0000000EU}, /* RGIDW_MODID[119]:MSI5*/ + [114] = {0xFCB92400U, 0x00000002U}, /* RGIDW_MODID[120]:ARSP40*/ + /* After setting */ /* RGIDW_MODID[121]:ARSP41*/ + /* After setting */ /* RGIDW_MODID[122]:ARSP42*/ + [115] = {0xFCB9240CU, 0x00000001U}, /* RGIDW_MODID[123]:ARSP43*/ + [116] = {0xFCB92410U, 0x00000002U}, /* RGIDW_MODID[124]:ARSP44*/ + [117] = {0xFCB92414U, 0x00000001U}, /* RGIDW_MODID[125]:ARSP45*/ + [118] = {0xFCB92418U, 0x00000002U}, /* RGIDW_MODID[126]:ARSP46*/ + [119] = {0xFCB9241CU, 0x00000002U}, /* RGIDW_MODID[127]:ARSP47*/ + [120] = {0xFCB92420U, 0x00000000U}, /* RGIDW_MODID[128]:ARSP48*/ + [121] = {0xFCB92424U, 0x0000004FU}, /* RGIDW_MODID[129]:DMAHSCIF0*/ + [122] = {0xFCB92428U, 0x0000004FU}, /* RGIDW_MODID[130]:DMAHSCIF1*/ + [123] = {0xFCB9242CU, 0x0000004FU}, /* RGIDW_MODID[131]:DMAHSCIF2*/ + [124] = {0xFCB92430U, 0x0000004FU}, /* RGIDW_MODID[132]:DMAHSCIF3*/ + [125] = {0xFCB92434U, 0x0000004FU}, /* RGIDW_MODID[133]:DMASCIF0*/ + [126] = {0xFCB92438U, 0x0000004FU}, /* RGIDW_MODID[134]:DMASCIF1*/ + [127] = {0xFCB9243CU, 0x0000004FU}, /* RGIDW_MODID[135]:DMASCIF3*/ + [128] = {0xFCB92440U, 0x0000004FU}, /* RGIDW_MODID[136]:DMASCIF4*/ + [129] = {0xFCB92444U, 0x0000000AU}, /* RGIDW_MODID[137]:ECMSP4*/ + [130] = {0xFCB92448U, 0x0000004FU}, /* RGIDW_MODID[138]:HSCIF0*/ + [131] = {0xFCB9244CU, 0x0000004FU}, /* RGIDW_MODID[139]:HSCIF1*/ + [132] = {0xFCB92450U, 0x0000004FU}, /* RGIDW_MODID[140]:HSCIF2*/ + [133] = {0xFCB92454U, 0x0000004FU}, /* RGIDW_MODID[141]:HSCIF3*/ + [134] = {0xFCB92458U, 0x0000004FU}, /* RGIDW_MODID[142]:SCIF0*/ + [135] = {0xFCB9245CU, 0x0000004FU}, /* RGIDW_MODID[143]:SCIF1*/ + [136] = {0xFCB92460U, 0x0000004FU}, /* RGIDW_MODID[144]:SCIF3*/ + [137] = {0xFCB92464U, 0x0000004FU}, /* RGIDW_MODID[145]:SCIF4*/ + [138] = {0xFCB92468U, 0x0000006EU}, /* RGIDW_MODID[146]:TMU1*/ + [139] = {0xFCB9246CU, 0x0000006EU}, /* RGIDW_MODID[147]:TMU2*/ + [140] = {0xFCB92470U, 0x0000006EU}, /* RGIDW_MODID[148]:TMU3*/ + [141] = {0xFCB92474U, 0x0000006EU}, /* RGIDW_MODID[149]:TMU4*/ + [142] = {0xFCB92478U, 0x0000004AU}, /* RGIDW_MODID[150]:CANFD*/ + [143] = {0xFCB9247CU, 0x0000004AU}, /* RGIDW_MODID[151]:DMACANFD*/ + [144] = {0xFCB92480U, 0x00000002U}, /* RGIDW_MODID[152]:DMATPU0*/ + [145] = {0xFCB92484U, 0x00000002U}, /* RGIDW_MODID[153]:PWM0*/ + [146] = {0xFCB92488U, 0x00000002U}, /* RGIDW_MODID[154]:PWM1*/ + [147] = {0xFCB9248CU, 0x00000002U}, /* RGIDW_MODID[155]:PWM2*/ + [148] = {0xFCB92490U, 0x00000002U}, /* RGIDW_MODID[156]:PWM3*/ + [149] = {0xFCB92494U, 0x00000002U}, /* RGIDW_MODID[157]:PWM4*/ + [150] = {0xFCB92498U, 0x00000002U}, /* RGIDW_MODID[158]:PWM5*/ + [151] = {0xFCB9249CU, 0x00000002U}, /* RGIDW_MODID[159]:PWM6*/ + [152] = {0xFCB924A0U, 0x00000002U}, /* RGIDW_MODID[160]:PWM7*/ + [153] = {0xFCB924A4U, 0x00000002U}, /* RGIDW_MODID[161]:PWM8*/ + [154] = {0xFCB924A8U, 0x00000002U}, /* RGIDW_MODID[162]:PWM9*/ + [155] = {0xFCB924ACU, 0x00000002U}, /* RGIDW_MODID[163]:TPU0*/ + [156] = {0xFC672400U, 0x00000002U}, /* RGIDW_MODID[164]:ARVC10*/ + /* After setting */ /* RGIDW_MODID[165]:ARVC11*/ + /* After setting */ /* RGIDW_MODID[166]:ARVC12*/ + [157] = {0xFC67240CU, 0x00000001U}, /* RGIDW_MODID[167]:ARVC13*/ + [158] = {0xFC672410U, 0x00000002U}, /* RGIDW_MODID[168]:ARVC14*/ + [159] = {0xFC672414U, 0x00000001U}, /* RGIDW_MODID[169]:ARVC15*/ + [160] = {0xFC672418U, 0x00000002U}, /* RGIDW_MODID[170]:ARVC16*/ + [161] = {0xFC67241CU, 0x00000002U}, /* RGIDW_MODID[171]:ARVC17*/ + [162] = {0xFC672420U, 0x00000000U}, /* RGIDW_MODID[172]:ARVC18*/ + [163] = {0xFC672424U, 0x0000000AU}, /* RGIDW_MODID[173]:ECMVC1*/ + [164] = {0xFC672428U, 0x00000028U}, /* RGIDW_MODID[174]:FCPCS*/ + [165] = {0xFC67242CU, 0x00000028U}, /* RGIDW_MODID[175]:VCP4LC*/ + [166] = {0xFC672430U, 0x00000028U}, /* RGIDW_MODID[176]:VCP4LV*/ + [167] = {0xFEBD2400U, 0x00000002U}, /* RGIDW_MODID[177]:ARVI40*/ + /* After setting */ /* RGIDW_MODID[178]:ARVI41*/ + /* After setting */ /* RGIDW_MODID[179]:ARVI42*/ + [168] = {0xFEBD240CU, 0x00000001U}, /* RGIDW_MODID[180]:ARVI43*/ + [169] = {0xFEBD2410U, 0x00000002U}, /* RGIDW_MODID[181]:ARVI44*/ + [170] = {0xFEBD2414U, 0x00000001U}, /* RGIDW_MODID[182]:ARVI45*/ + [171] = {0xFEBD2418U, 0x00000002U}, /* RGIDW_MODID[183]:ARVI46*/ + [172] = {0xFEBD241CU, 0x00000002U}, /* RGIDW_MODID[184]:ARVI47*/ + [173] = {0xFEBD2420U, 0x00000000U}, /* RGIDW_MODID[185]:ARVI48*/ + [174] = {0xFEBD2424U, 0x0000000FU}, /* RGIDW_MODID[186]:DIS0*/ + [175] = {0xFEBD242CU, 0x0000000FU}, /* RGIDW_MODID[187]:DSC*/ + [176] = {0xFEBD2430U, 0x0000000EU}, /* RGIDW_MODID[188]:ECMVIO2*/ + [177] = {0xFEBD2434U, 0x0000000FU}, /* RGIDW_MODID[189]:FCPVD0*/ + [178] = {0xFEBD2438U, 0x0000000FU}, /* RGIDW_MODID[190]:FCPVD1*/ + [179] = {0xFEBD243CU, 0x0000004EU}, /* RGIDW_MODID[191]:VSPD0*/ + [180] = {0xFEBD2440U, 0x0000004EU}, /* RGIDW_MODID[192]:VSPD1*/ + [181] = {0xFCF82400U, 0x0000000AU}, /* RGIDW_MODID[193]:CKMHSC*/ + [182] = {0xFCF82404U, 0x0000000CU}, /* RGIDW_MODID[194]:AXIPCI001*/ + [183] = {0xFCF82408U, 0x0000000CU}, /* RGIDW_MODID[195]:AXIPCI002*/ + [184] = {0xFCF8240CU, 0x0000000CU}, /* RGIDW_MODID[196]:AXIPCI003*/ + [185] = {0xFCF82414U, 0x0000000CU}, /* RGIDW_MODID[197]:AXIPCI005*/ + [186] = {0xFCF82418U, 0x0000000CU}, /* RGIDW_MODID[198]:AXIPCI006*/ + [187] = {0xFCF8241CU, 0x0000000CU}, /* RGIDW_MODID[199]:AXIPCI007*/ + [188] = {0xFCF82420U, 0x0000000CU}, /* RGIDW_MODID[200]:AXIPCI008*/ + [189] = {0xFCF82424U, 0x0000000CU}, /* RGIDW_MODID[201]:AXIPCI009*/ + [190] = {0xFCF82428U, 0x0000000CU}, /* RGIDW_MODID[202]:AXIPCI010*/ + [191] = {0xFCF8242CU, 0x0000000CU}, /* RGIDW_MODID[203]:AXIPCI011*/ + [192] = {0xFCF82430U, 0x0000000CU}, /* RGIDW_MODID[204]:AXIPCI012*/ + [193] = {0xFCF82434U, 0x0000000CU}, /* RGIDW_MODID[205]:AXIPCI013*/ + [194] = {0xFCF82438U, 0x0000000CU}, /* RGIDW_MODID[206]:AXIPCI014*/ + [195] = {0xFCF8243CU, 0x0000000CU}, /* RGIDW_MODID[207]:AXIPCI015*/ + [196] = {0xFCF82440U, 0x0000000CU}, /* RGIDW_MODID[208]:AXIPCI100*/ + [197] = {0xFCF82444U, 0x0000000CU}, /* RGIDW_MODID[209]:AXIPCI101*/ + [198] = {0xFCF82448U, 0x0000000CU}, /* RGIDW_MODID[210]:AXIPCI102*/ + [199] = {0xFCF8244CU, 0x0000000CU}, /* RGIDW_MODID[211]:AXIPCI103*/ + [200] = {0xFCF82450U, 0x0000000CU}, /* RGIDW_MODID[212]:AXIPCI104*/ + [201] = {0xFCF82454U, 0x0000000CU}, /* RGIDW_MODID[213]:AXIPCI105*/ + [202] = {0xFCF82458U, 0x0000000CU}, /* RGIDW_MODID[214]:AXIPCI106*/ + [203] = {0xFCF8245CU, 0x0000000CU}, /* RGIDW_MODID[215]:AXIPCI107*/ + [204] = {0xFCF82460U, 0x0000000CU}, /* RGIDW_MODID[216]:AXIPCI108*/ + [205] = {0xFCF82464U, 0x0000000CU}, /* RGIDW_MODID[217]:AXIPCI109*/ + [206] = {0xFCF82468U, 0x0000000CU}, /* RGIDW_MODID[218]:AXIPCI110*/ + [207] = {0xFCF8246CU, 0x0000000CU}, /* RGIDW_MODID[219]:AXIPCI111*/ + [208] = {0xFCF82470U, 0x0000000CU}, /* RGIDW_MODID[220]:AXIPCI112*/ + [209] = {0xFCF82474U, 0x0000000CU}, /* RGIDW_MODID[221]:AXIPCI113*/ + [210] = {0xFCF82478U, 0x0000000CU}, /* RGIDW_MODID[222]:AXIPCI114*/ + [211] = {0xFCF8247CU, 0x0000000CU}, /* RGIDW_MODID[223]:AXIPCI115*/ + [212] = {0xFCF82484U, 0x0000000EU}, /* RGIDW_MODID[224]:GPTP*/ + [213] = {0xFCF82488U, 0x0000004EU}, /* RGIDW_MODID[225]:IPMMUHC00*/ + [214] = {0xFCF824F0U, 0x0000000EU}, /* RGIDW_MODID[226]:TSN0*/ + [215] = {0xFCF824F4U, 0x0000000CU}, /* RGIDW_MODID[227]:AXIPCI000*/ + [216] = {0xFCF824F8U, 0x0000000CU}, /* RGIDW_MODID[228]:AXIPCI004*/ + [217] = {0xFCF824FCU, 0x0000004EU}, /* RGIDW_MODID[229]:IPMMUHC01*/ + [218] = {0xFCF82500U, 0x0000004EU}, /* RGIDW_MODID[230]:AVB0*/ + [219] = {0xFCF82504U, 0x0000004EU}, /* RGIDW_MODID[231]:AVB1*/ + [220] = {0xFCF82508U, 0x0000004EU}, /* RGIDW_MODID[232]:AVB2*/ + [221] = {0xFCF8250CU, 0x0000004EU}, /* RGIDW_MODID[233]:IPMMUHC10*/ + [222] = {0xFCF82510U, 0x0000004EU}, /* RGIDW_MODID[234]:IPMMUHC11*/ + [223] = {0xFCF82514U, 0x0000004EU}, /* RGIDW_MODID[235]:IPMMUHC12*/ + [224] = {0xFCF82518U, 0x0000004EU}, /* RGIDW_MODID[236]:IPMMUHC13*/ + [225] = {0xFCF8251CU, 0x0000000CU}, /* RGIDW_MODID[237]:PPHY0*/ + [226] = {0xFCF82520U, 0x0000000CU}, /* RGIDW_MODID[238]:PPHY1*/ + [227] = {0xFCF82524U, 0x0000004EU}, /* RGIDW_MODID[239]:IPMMUHC14*/ + [228] = {0xFCF82528U, 0x0000004EU}, /* RGIDW_MODID[240]:IPMMUHC15*/ + [229] = {0xFCF8252CU, 0x0000000EU}, /* RGIDW_MODID[241]:FBAHSC*/ + [230] = {0xFCF82530U, 0x0000004EU}, /* RGIDW_MODID[242]:IPMMUHC02*/ + [231] = {0xFCF82538U, 0x0000000AU}, /* RGIDW_MODID[243]:ECMHSC*/ + [232] = {0xFCF8253CU, 0x00000002U}, /* RGIDW_MODID[244]:ARHC0*/ + /* After setting */ /* RGIDW_MODID[245]:ARHC1*/ + /* After setting */ /* RGIDW_MODID[246]:ARHC2*/ + [233] = {0xFCF82548U, 0x00000001U}, /* RGIDW_MODID[247]:ARHC3*/ + [234] = {0xFCF8254CU, 0x00000002U}, /* RGIDW_MODID[248]:ARHC4*/ + [235] = {0xFCF82550U, 0x00000001U}, /* RGIDW_MODID[249]:ARHC5*/ + [236] = {0xFCF82554U, 0x00000002U}, /* RGIDW_MODID[250]:ARHC6*/ + [237] = {0xFCF82558U, 0x00000002U}, /* RGIDW_MODID[251]:ARHC7*/ + [238] = {0xFCF8255CU, 0x00000000U}, /* RGIDW_MODID[252]:ARHC8*/ + [239] = {0xFCF82560U, 0x0000004EU}, /* RGIDW_MODID[253]:IPMMUHC03*/ + [240] = {0xFCF82564U, 0x0000004EU}, /* RGIDW_MODID[254]:IPMMUHC04*/ + [241] = {0xFCF82568U, 0x0000004EU}, /* RGIDW_MODID[255]:IPMMUHC05*/ + [242] = {0xFCF8256CU, 0x0000004EU}, /* RGIDW_MODID[256]:IPMMUHC06*/ + [243] = {0xFCF82570U, 0x0000004EU}, /* RGIDW_MODID[257]:IPMMUHC07*/ + [244] = {0xFCF82574U, 0x0000004EU}, /* RGIDW_MODID[258]:IPMMUHC08*/ + [245] = {0xFCF82578U, 0x0000004EU}, /* RGIDW_MODID[259]:IPMMUHC09*/ + [246] = {0xFC882400U, 0x00000002U}, /* RGIDW_MODID[260]:ARIMP00*/ + /* After setting */ /* RGIDW_MODID[261]:ARIMP01*/ + /* After setting */ /* RGIDW_MODID[262]:ARIMP02*/ + [247] = {0xFC88240CU, 0x00000001U}, /* RGIDW_MODID[263]:ARIMP03*/ + [248] = {0xFC882410U, 0x00000002U}, /* RGIDW_MODID[264]:ARIMP04*/ + [249] = {0xFC882414U, 0x0000004EU}, /* RGIDW_MODID[265]:AXIFBABUSIR0*/ + [250] = {0xFC882418U, 0x0000004EU}, /* RGIDW_MODID[266]:AXIFBABUSIR1*/ + [251] = {0xFC88241CU, 0x0000004EU}, /* RGIDW_MODID[267]:AXIFBABUSIR2*/ + [252] = {0xFC882420U, 0x0000004EU}, /* RGIDW_MODID[268]:AXIFBABUSIR3*/ + [253] = {0xFC882424U, 0x0000004EU}, /* RGIDW_MODID[269]:AXIFBABUSIR4*/ + [254] = {0xFC882428U, 0x0000004EU}, /* RGIDW_MODID[270]:AXIIMP0*/ + [255] = {0xFC88242CU, 0x0000004EU}, /* RGIDW_MODID[271]:CKMCNR*/ + [256] = {0xFC882430U, 0x0000004EU}, /* RGIDW_MODID[272]:CKMDSP*/ + [257] = {0xFC882434U, 0x00000001U}, /* RGIDW_MODID[273]:ARIMP05*/ + [258] = {0xFC882438U, 0x00000002U}, /* RGIDW_MODID[274]:ARIMP06*/ + [259] = {0xFC88243CU, 0x00000002U}, /* RGIDW_MODID[275]:ARIMP07*/ + [260] = {0xFC882440U, 0x00000000U}, /* RGIDW_MODID[276]:ARIMP08*/ + [261] = {0xFC882444U, 0x0000004EU}, /* RGIDW_MODID[277]:CKMIR*/ + [262] = {0xFC882448U, 0x0000000AU}, /* RGIDW_MODID[278]:ECMIR*/ + [263] = {0xFC88244CU, 0x0000000FU}, /* RGIDW_MODID[279]:DSPPS*/ + [264] = {0xFC882450U, 0x0000004EU}, /* RGIDW_MODID[280]:IPMMUIR1*/ + [265] = {0xFC882454U, 0x0000004EU}, /* RGIDW_MODID[281]:IPMMUIR0*/ + [266] = {0xFC882458U, 0x0000004EU}, /* RGIDW_MODID[282]:IPMMUIR10*/ + [267] = {0xFC88245CU, 0x0000004EU}, /* RGIDW_MODID[283]:IPMMUIR11*/ + [268] = {0xFC882460U, 0x0000004EU}, /* RGIDW_MODID[284]:IPMMUIR12*/ + [269] = {0xFC882464U, 0x0000004EU}, /* RGIDW_MODID[285]:IPMMUIR13*/ + [270] = {0xFC882468U, 0x0000004EU}, /* RGIDW_MODID[286]:IPMMUIR14*/ + [271] = {0xFC88246CU, 0x0000004EU}, /* RGIDW_MODID[287]:IPMMUIR15*/ + [272] = {0xFC882470U, 0x0000004EU}, /* RGIDW_MODID[288]:IPMMUIR2*/ + [273] = {0xFC882474U, 0x0000004EU}, /* RGIDW_MODID[289]:IPMMUIR3*/ + [274] = {0xFC882478U, 0x0000004EU}, /* RGIDW_MODID[290]:IPMMUIR4*/ + [275] = {0xFC88247CU, 0x0000004EU}, /* RGIDW_MODID[291]:IPMMUIR5*/ + [276] = {0xFC882480U, 0x0000004EU}, /* RGIDW_MODID[292]:IPMMUIR6*/ + [277] = {0xFC882484U, 0x0000004EU}, /* RGIDW_MODID[293]:IPMMUIR7*/ + [278] = {0xFC882488U, 0x0000004EU}, /* RGIDW_MODID[294]:IPMMUIR8*/ + [279] = {0xFC88248CU, 0x0000004EU}, /* RGIDW_MODID[295]:IPMMUIR9*/ + [280] = {0xFC012400U, 0x00000002U}, /* RGIDW_MODID[296]:ARPV0*/ + /* After setting */ /* RGIDW_MODID[297]:ARPV1*/ + [281] = {0xFC012408U, 0x0000002CU}, /* RGIDW_MODID[298]:AXIRGXS*/ + /* After setting */ /* RGIDW_MODID[299]:ARPV2*/ + [282] = {0xFC012410U, 0x00000001U}, /* RGIDW_MODID[300]:ARPV3*/ + [283] = {0xFC012414U, 0x00000002U}, /* RGIDW_MODID[301]:ARPV4*/ + [284] = {0xFC012418U, 0x00000001U}, /* RGIDW_MODID[302]:ARPV5*/ + [285] = {0xFC01241CU, 0x00000002U}, /* RGIDW_MODID[303]:ARPV6*/ + [286] = {0xFC012420U, 0x00000002U}, /* RGIDW_MODID[304]:ARPV7*/ + [287] = {0xFC012424U, 0x00000000U}, /* RGIDW_MODID[305]:ARPV8*/ + [288] = {0xFC012428U, 0x0000000AU}, /* RGIDW_MODID[306]:CKM3DG*/ + [289] = {0xFC01242CU, 0x0000000AU}, /* RGIDW_MODID[307]:ECM3DG*/ + [290] = {0xFC012430U, 0x0000000EU}, /* RGIDW_MODID[308]:FBAPVC*/ + [291] = {0xFC012434U, 0x0000000EU}, /* RGIDW_MODID[309]:FBAPVD0*/ + [292] = {0xFC012438U, 0x0000000EU}, /* RGIDW_MODID[310]:FBAPVD1*/ + [293] = {0xFC01243CU, 0x0000000EU}, /* RGIDW_MODID[311]:FBAPVD2*/ + [294] = {0xFC012440U, 0x0000000EU}, /* RGIDW_MODID[312]:FBAPVE*/ + [295] = {0xFC012444U, 0x0000004EU}, /* RGIDW_MODID[313]:IPMMUPV000*/ + [296] = {0xFC012448U, 0x0000004EU}, /* RGIDW_MODID[314]:IPMMUPV001*/ + [297] = {0xFC01244CU, 0x0000004EU}, /* RGIDW_MODID[315]:IPMMUPV010*/ + [298] = {0xFC012450U, 0x0000004EU}, /* RGIDW_MODID[316]:IPMMUPV011*/ + [299] = {0xFC012454U, 0x0000004EU}, /* RGIDW_MODID[317]:IPMMUPV012*/ + [300] = {0xFC012458U, 0x0000004EU}, /* RGIDW_MODID[318]:IPMMUPV013*/ + [301] = {0xFC01245CU, 0x0000004EU}, /* RGIDW_MODID[319]:IPMMUPV014*/ + [302] = {0xFC012460U, 0x0000004EU}, /* RGIDW_MODID[320]:IPMMUPV015*/ + [303] = {0xFC012464U, 0x0000004EU}, /* RGIDW_MODID[321]:IPMMUPV002*/ + [304] = {0xFC012468U, 0x0000004EU}, /* RGIDW_MODID[322]:IPMMUPV003*/ + [305] = {0xFC01246CU, 0x0000004EU}, /* RGIDW_MODID[323]:IPMMUPV004*/ + [306] = {0xFC012470U, 0x0000004EU}, /* RGIDW_MODID[324]:IPMMUPV005*/ + [307] = {0xFC012474U, 0x0000004EU}, /* RGIDW_MODID[325]:IPMMUPV006*/ + [308] = {0xFC012478U, 0x0000004EU}, /* RGIDW_MODID[326]:IPMMUPV007*/ + [309] = {0xFC01247CU, 0x0000004EU}, /* RGIDW_MODID[327]:IPMMUPV008*/ + [310] = {0xFC012480U, 0x0000004EU}, /* RGIDW_MODID[328]:IPMMUPV009*/ + [311] = {0xFDC22400U, 0x00000002U}, /* RGIDW_MODID[329]:ARRC0*/ + /* After setting */ /* RGIDW_MODID[330]:ARRC1*/ + /* After setting */ /* RGIDW_MODID[331]:ARRC2*/ + [312] = {0xFDC2240CU, 0x00000001U}, /* RGIDW_MODID[332]:ARRC3*/ + [313] = {0xFDC22410U, 0x00000002U}, /* RGIDW_MODID[333]:ARRC4*/ + [314] = {0xFDC22414U, 0x00000001U}, /* RGIDW_MODID[334]:ARRC5*/ + [315] = {0xFDC22418U, 0x00000002U}, /* RGIDW_MODID[335]:ARRC6*/ + [316] = {0xFDC2241CU, 0x00000002U}, /* RGIDW_MODID[336]:ARRC7*/ + [317] = {0xFDC22420U, 0x00000000U}, /* RGIDW_MODID[337]:ARRC8*/ + [318] = {0xFDC22424U, 0x00000009U}, /* RGIDW_MODID[338]:CR0*/ + [319] = {0xFDC22428U, 0x0000004FU}, /* RGIDW_MODID[339]:ICUMX*/ + [320] = {0xFDC2242CU, 0x0000000AU}, /* RGIDW_MODID[340]:ECMRC*/ + [321] = {0xFD432400U, 0x0000004EU}, /* RGIDW_MODID[341]:DMAWCRC0*/ + [322] = {0xFD432404U, 0x0000004EU}, /* RGIDW_MODID[342]:DMAWCRC1*/ + [323] = {0xFD432408U, 0x0000004EU}, /* RGIDW_MODID[343]:DMAWCRC2*/ + [324] = {0xFD43240CU, 0x0000004EU}, /* RGIDW_MODID[344]:DMAWCRC3*/ + [325] = {0xFD442400U, 0x0000000FU}, /* RGIDW_MODID[345]:ARMREG00*/ + [326] = {0xFD442404U, 0x0000000CU}, /* RGIDW_MODID[346]:ARMREG01*/ + [327] = {0xFD442408U, 0x00000000U}, /* RGIDW_MODID[347]:ARMREG10*/ + [328] = {0xFD44240CU, 0x00000000U}, /* RGIDW_MODID[348]:ARMREG11*/ + [329] = {0xFD442410U, 0x0000000AU}, /* RGIDW_MODID[349]:ARMREG12*/ + [330] = {0xFD442414U, 0x0000000FU}, /* RGIDW_MODID[350]:ARMREG13*/ + [331] = {0xFD442418U, 0x0000000AU}, /* RGIDW_MODID[351]:ARMREG14*/ + [332] = {0xFD44241CU, 0x00000003U}, /* RGIDW_MODID[352]:AXICR52SS0*/ + [333] = {0xFD442420U, 0x0000000EU}, /* RGIDW_MODID[353]:AXICSD0*/ + [334] = {0xFD442424U, 0x0000000EU}, /* RGIDW_MODID[354]:AXIINTAP0*/ + [335] = {0xFD442428U, 0x00000000U}, /* RGIDW_MODID[355]:AXIINTAP1*/ + [336] = {0xFD442430U, 0x0000000FU}, /* RGIDW_MODID[356]:AXISYSRAM0*/ + [337] = {0xFD442434U, 0x0000004FU}, /* RGIDW_MODID[357]:AXISYSRAM1*/ + [338] = {0xFD442438U, 0x00000000U}, /* RGIDW_MODID[358]:ARGREG15*/ + [339] = {0xFD44243CU, 0x00000000U}, /* RGIDW_MODID[359]:ARMREG2*/ + [340] = {0xFD442440U, 0x00000000U}, /* RGIDW_MODID[360]:ARMREG3*/ + [341] = {0xFD442444U, 0x00000000U}, /* RGIDW_MODID[361]:ARMREG4*/ + [342] = {0xFD442448U, 0x0000000FU}, /* RGIDW_MODID[362]:ARMREG5*/ + [343] = {0xFD44244CU, 0x0000000AU}, /* RGIDW_MODID[363]:ARMREG6*/ + [344] = {0xFD442450U, 0x00000000U}, /* RGIDW_MODID[364]:ARMREG7*/ + [345] = {0xFD442454U, 0x0000000CU}, /* RGIDW_MODID[365]:ARMREG8*/ + [346] = {0xFD442458U, 0x0000000CU}, /* RGIDW_MODID[366]:ARMREG9*/ + [347] = {0xFD44245CU, 0x00000002U}, /* RGIDW_MODID[367]:ARRD0*/ + /* After setting */ /* RGIDW_MODID[368]:ARRD1*/ + /* After setting */ /* RGIDW_MODID[369]:ARRD2*/ + [348] = {0xFD442468U, 0x00000001U}, /* RGIDW_MODID[370]:ARRD3*/ + [349] = {0xFD44246CU, 0x00000002U}, /* RGIDW_MODID[371]:ARRD4*/ + [350] = {0xFD442470U, 0x00000001U}, /* RGIDW_MODID[372]:ARRD5*/ + [351] = {0xFD442474U, 0x00000002U}, /* RGIDW_MODID[373]:ARRD6*/ + [352] = {0xFD442478U, 0x00000002U}, /* RGIDW_MODID[374]:ARRD7*/ + [353] = {0xFD44247CU, 0x00000000U}, /* RGIDW_MODID[375]:ARRD8*/ + [354] = {0xFD442480U, 0x00000002U}, /* RGIDW_MODID[376]:ARRT0*/ + /* After setting */ /* RGIDW_MODID[377]:ARRT1*/ + /* After setting */ /* RGIDW_MODID[378]:ARRT2*/ + [355] = {0xFD44248CU, 0x00000001U}, /* RGIDW_MODID[379]:ARRT3*/ + [356] = {0xFD442490U, 0x00000002U}, /* RGIDW_MODID[380]:ARRT4*/ + [357] = {0xFD442494U, 0x00000001U}, /* RGIDW_MODID[381]:ARRT5*/ + [358] = {0xFD442498U, 0x00000002U}, /* RGIDW_MODID[382]:ARRT6*/ + [359] = {0xFD44249CU, 0x00000002U}, /* RGIDW_MODID[383]:ARRT7*/ + [360] = {0xFD4424A0U, 0x00000000U}, /* RGIDW_MODID[384]:ARRT8*/ + [361] = {0xFD4424A4U, 0x0000000AU}, /* RGIDW_MODID[385]:CKMRT*/ + [362] = {0xFD4424A8U, 0x0000004EU}, /* RGIDW_MODID[386]:CRC0*/ + [363] = {0xFD4424ACU, 0x0000004EU}, /* RGIDW_MODID[387]:CRC1*/ + [364] = {0xFD4424B0U, 0x0000004EU}, /* RGIDW_MODID[388]:CRC2*/ + [365] = {0xFD4424B4U, 0x0000004EU}, /* RGIDW_MODID[389]:CRC3*/ + [366] = {0xFD4424B8U, 0x0000000EU}, /* RGIDW_MODID[390]:CSD*/ + [367] = {0xFD4424BCU, 0x0000000EU}, /* RGIDW_MODID[391]:ECM*/ + [368] = {0xFD4424C0U, 0x0000000AU}, /* RGIDW_MODID[392]:ECMRT*/ + [369] = {0xFD4424C4U, 0x0000000EU}, /* RGIDW_MODID[393]:FBACR52*/ + [370] = {0xFD4424C8U, 0x0000000EU}, /* RGIDW_MODID[394]:FBART*/ + [371] = {0xFD4424CCU, 0x0000000EU}, /* RGIDW_MODID[395]:INTTP*/ + [372] = {0xFD4424D0U, 0x0000004EU}, /* RGIDW_MODID[396]:IPMMURT000*/ + [373] = {0xFD4424D4U, 0x0000004EU}, /* RGIDW_MODID[397]:IPMMURT100*/ + [374] = {0xFD4424D8U, 0x0000004EU}, /* RGIDW_MODID[398]:KCRC4*/ + [375] = {0xFD4424DCU, 0x0000004EU}, /* RGIDW_MODID[399]:KCRC5*/ + [376] = {0xFD4424E0U, 0x0000004EU}, /* RGIDW_MODID[400]:KCRC6*/ + [377] = {0xFD4424E4U, 0x0000004EU}, /* RGIDW_MODID[401]:KCRC7*/ + [378] = {0xFD4424E8U, 0x0000004FU}, /* RGIDW_MODID[402]:MFI00*/ + [379] = {0xFD4424ECU, 0x0000004EU}, /* RGIDW_MODID[403]:MFI01*/ + [380] = {0xFD4424F0U, 0x0000004EU}, /* RGIDW_MODID[404]:MFI10*/ + [381] = {0xFD4424F4U, 0x0000004EU}, /* RGIDW_MODID[405]:MFI02*/ + [382] = {0xFD4424F8U, 0x0000004EU}, /* RGIDW_MODID[406]:MFI03*/ + [383] = {0xFD4424FCU, 0x0000004EU}, /* RGIDW_MODID[407]:MFI04*/ + [384] = {0xFD442500U, 0x00000000U}, /* RGIDW_MODID[408]:MFI05*/ + [385] = {0xFD442504U, 0x00000000U}, /* RGIDW_MODID[409]:MFI06*/ + [386] = {0xFD442508U, 0x00000000U}, /* RGIDW_MODID[410]:MFI07*/ + [387] = {0xFD44250CU, 0x00000000U}, /* RGIDW_MODID[411]:MFI08*/ + [388] = {0xFD442510U, 0x0000004EU}, /* RGIDW_MODID[412]:MFI09*/ + [389] = {0xFD442514U, 0x0000004FU}, /* RGIDW_MODID[413]:MFI15*/ + [390] = {0xFD442518U, 0x0000000AU}, /* RGIDW_MODID[414]:CKMCR52*/ + [391] = {0xFD44251CU, 0x0000004BU}, /* RGIDW_MODID[415]:RTDM0P*/ + [392] = {0xFD442520U, 0x0000000AU}, /* RGIDW_MODID[416]:ECMRD*/ + [393] = {0xFD442524U, 0x0000004BU}, /* RGIDW_MODID[417]:RTDM1P*/ + [394] = {0xFD44252CU, 0x0000004BU}, /* RGIDW_MODID[418]:RTDM2P*/ + [395] = {0xFD442530U, 0x0000000BU}, /* RGIDW_MODID[419]:SYSRAM10*/ + [396] = {0xFD442534U, 0x0000004BU}, /* RGIDW_MODID[420]:RTDM3P*/ + [397] = {0xFD442538U, 0x00000001U}, /* RGIDW_MODID[421]:SYSRAM00*/ + [398] = {0xFD44253CU, 0x0000004EU}, /* RGIDW_MODID[422]:TSIPL0*/ + [399] = {0xFD442540U, 0x0000004EU}, /* RGIDW_MODID[423]:TSIPL1*/ + [400] = {0xFD442544U, 0x0000004EU}, /* RGIDW_MODID[424]:TSIPL2*/ + [401] = {0xFD442548U, 0x0000004EU}, /* RGIDW_MODID[425]:TSIPL3*/ + [402] = {0xFD44254CU, 0x0000004EU}, /* RGIDW_MODID[426]:TSIPL4*/ + [403] = {0xFD442550U, 0x0000004EU}, /* RGIDW_MODID[427]:TSIPL5*/ + [404] = {0xFD442554U, 0x0000004EU}, /* RGIDW_MODID[428]:TSIPL6*/ + [405] = {0xFD442558U, 0x0000004EU}, /* RGIDW_MODID[429]:TSIPL7*/ + [406] = {0xFD44255CU, 0x0000004EU}, /* RGIDW_MODID[430]:WCRC0*/ + [407] = {0xFD442560U, 0x0000004EU}, /* RGIDW_MODID[431]:WCRC1*/ + [408] = {0xFD442564U, 0x0000004EU}, /* RGIDW_MODID[432]:WCRC2*/ + [409] = {0xFD442568U, 0x0000004EU}, /* RGIDW_MODID[433]:WCRC3*/ + [410] = {0xFD442580U, 0x0000004EU}, /* RGIDW_MODID[434]:MFI11*/ + [411] = {0xFD442584U, 0x00000000U}, /* RGIDW_MODID[435]:MFI12*/ + [412] = {0xFD442588U, 0x00000000U}, /* RGIDW_MODID[436]:MFI13*/ + [413] = {0xFD44258CU, 0x00000000U}, /* RGIDW_MODID[437]:MFI14*/ + [414] = {0xFD442590U, 0x0000004EU}, /* RGIDW_MODID[438]:IPMMURT001*/ + [415] = {0xFD442594U, 0x0000004EU}, /* RGIDW_MODID[439]:IPMMURT010*/ + [416] = {0xFD442598U, 0x0000004EU}, /* RGIDW_MODID[440]:IPMMURT011*/ + [417] = {0xFD44259CU, 0x0000004EU}, /* RGIDW_MODID[441]:IPMMURT012*/ + [418] = {0xFD4425A0U, 0x0000004EU}, /* RGIDW_MODID[442]:IPMMURT013*/ + [419] = {0xFD4425A4U, 0x0000004EU}, /* RGIDW_MODID[443]:IPMMURT014*/ + [420] = {0xFD4425A8U, 0x0000004EU}, /* RGIDW_MODID[444]:IPMMURT015*/ + [421] = {0xFD4425ACU, 0x0000004EU}, /* RGIDW_MODID[445]:IPMMURT002*/ + [422] = {0xFD4425B0U, 0x0000004EU}, /* RGIDW_MODID[446]:IPMMURT003*/ + [423] = {0xFD4425B4U, 0x0000004EU}, /* RGIDW_MODID[447]:IPMMURT004*/ + [424] = {0xFD4425B8U, 0x0000004EU}, /* RGIDW_MODID[448]:IPMMURT005*/ + [425] = {0xFD4425BCU, 0x0000004EU}, /* RGIDW_MODID[449]:IPMMURT006*/ + [426] = {0xFD4425C0U, 0x0000004EU}, /* RGIDW_MODID[450]:IPMMURT007*/ + [427] = {0xFD4425C4U, 0x0000004EU}, /* RGIDW_MODID[451]:IPMMURT008*/ + [428] = {0xFD4425C8U, 0x0000004EU}, /* RGIDW_MODID[452]:IPMMURT009*/ + [429] = {0xFD4425CCU, 0x0000004EU}, /* RGIDW_MODID[453]:IPKMURT101*/ + [430] = {0xFD4425D0U, 0x0000004EU}, /* RGIDW_MODID[454]:IPMMURT110*/ + [431] = {0xFD4425D4U, 0x0000004EU}, /* RGIDW_MODID[455]:IPMMURT111*/ + [432] = {0xFD4425D8U, 0x0000004EU}, /* RGIDW_MODID[456]:IPMMURT112*/ + [433] = {0xFD4425DCU, 0x0000004EU}, /* RGIDW_MODID[457]:IPMMURT113*/ + [434] = {0xFD4425E0U, 0x0000004EU}, /* RGIDW_MODID[458]:IPMMURT114*/ + [435] = {0xFD4425E4U, 0x0000004EU}, /* RGIDW_MODID[459]:IPMMURT115*/ + [436] = {0xFD4425E8U, 0x0000004EU}, /* RGIDW_MODID[460]:IPMMURT102*/ + [437] = {0xFD4425ECU, 0x0000004EU}, /* RGIDW_MODID[461]:IPMMURT103*/ + [438] = {0xFD4425F0U, 0x0000004EU}, /* RGIDW_MODID[462]:IPMMURT104*/ + [439] = {0xFD4425F4U, 0x0000004EU}, /* RGIDW_MODID[463]:IPMMURT105*/ + [440] = {0xFD4425F8U, 0x0000004EU}, /* RGIDW_MODID[464]:IPMMURT106*/ + [441] = {0xFD4425FCU, 0x0000004EU}, /* RGIDW_MODID[465]:IPMMURT107*/ + [442] = {0xFD442600U, 0x0000004BU}, /* RGIDW_MODID[466]:RTDM000*/ + [443] = {0xFD442604U, 0x0000004BU}, /* RGIDW_MODID[467]:RTDM001*/ + [444] = {0xFD442608U, 0x0000004BU}, /* RGIDW_MODID[468]:RTDM010*/ + [445] = {0xFD44260CU, 0x0000004BU}, /* RGIDW_MODID[469]:RTDM011*/ + [446] = {0xFD442610U, 0x0000004BU}, /* RGIDW_MODID[470]:RTDM012*/ + [447] = {0xFD442614U, 0x0000004BU}, /* RGIDW_MODID[471]:RTDM013*/ + [448] = {0xFD442618U, 0x0000004BU}, /* RGIDW_MODID[472]:RTDM014*/ + [449] = {0xFD44261CU, 0x0000004BU}, /* RGIDW_MODID[473]:RTDM015*/ + [450] = {0xFD442620U, 0x0000004BU}, /* RGIDW_MODID[474]:RTDM002*/ + [451] = {0xFD442624U, 0x0000004BU}, /* RGIDW_MODID[475]:RTDM003*/ + [452] = {0xFD442628U, 0x0000004BU}, /* RGIDW_MODID[476]:RTDM004*/ + [453] = {0xFD44262CU, 0x0000004BU}, /* RGIDW_MODID[477]:RTDM005*/ + [454] = {0xFD442630U, 0x0000004BU}, /* RGIDW_MODID[478]:RTDM006*/ + [455] = {0xFD442634U, 0x0000004BU}, /* RGIDW_MODID[479]:RTDM007*/ + [456] = {0xFD442638U, 0x0000004BU}, /* RGIDW_MODID[480]:RTDM008*/ + [457] = {0xFD44263CU, 0x0000004BU}, /* RGIDW_MODID[481]:RTDM009*/ + [458] = {0xFD442640U, 0x0000004BU}, /* RGIDW_MODID[482]:RTDM100*/ + [459] = {0xFD442644U, 0x0000004BU}, /* RGIDW_MODID[483]:RTDM101*/ + [460] = {0xFD442648U, 0x0000004BU}, /* RGIDW_MODID[484]:RTDM110*/ + [461] = {0xFD44264CU, 0x0000004BU}, /* RGIDW_MODID[485]:RTDM111*/ + [462] = {0xFD442650U, 0x0000004BU}, /* RGIDW_MODID[486]:RTDM112*/ + [463] = {0xFD442654U, 0x0000004BU}, /* RGIDW_MODID[487]:RTDM113*/ + [464] = {0xFD442658U, 0x0000004BU}, /* RGIDW_MODID[488]:RTDM114*/ + [465] = {0xFD44265CU, 0x0000004BU}, /* RGIDW_MODID[489]:RTDM115*/ + [466] = {0xFD442660U, 0x0000004BU}, /* RGIDW_MODID[490]:RTDM102*/ + [467] = {0xFD442664U, 0x0000004BU}, /* RGIDW_MODID[491]:RTDM103*/ + [468] = {0xFD442668U, 0x0000004BU}, /* RGIDW_MODID[492]:RTDM104*/ + [469] = {0xFD44266CU, 0x0000004BU}, /* RGIDW_MODID[493]:RTDM105*/ + [470] = {0xFD442670U, 0x0000004BU}, /* RGIDW_MODID[494]:RTDM106*/ + [471] = {0xFD442674U, 0x0000004BU}, /* RGIDW_MODID[495]:RTDM107*/ + [472] = {0xFD442678U, 0x0000004BU}, /* RGIDW_MODID[496]:RTDM108*/ + [473] = {0xFD44267CU, 0x0000004BU}, /* RGIDW_MODID[497]:RTDM109*/ + [474] = {0xFD442680U, 0x0000004BU}, /* RGIDW_MODID[498]:RTDM200*/ + [475] = {0xFD442684U, 0x0000004BU}, /* RGIDW_MODID[499]:RTDM201*/ + [476] = {0xFD442688U, 0x0000004BU}, /* RGIDW_MODID[500]:RTDM210*/ + [477] = {0xFD44268CU, 0x0000004BU}, /* RGIDW_MODID[501]:RTDM211*/ + [478] = {0xFD442690U, 0x0000004BU}, /* RGIDW_MODID[502]:RTDM212*/ + [479] = {0xFD442694U, 0x0000004BU}, /* RGIDW_MODID[503]:RTDM213*/ + [480] = {0xFD442698U, 0x0000004BU}, /* RGIDW_MODID[504]:RTDM214*/ + [481] = {0xFD44269CU, 0x0000004BU}, /* RGIDW_MODID[505]:RTDM215*/ + [482] = {0xFD4426A0U, 0x0000004BU}, /* RGIDW_MODID[506]:RTDM202*/ + [483] = {0xFD4426A4U, 0x0000004BU}, /* RGIDW_MODID[507]:RTDM203*/ + [484] = {0xFD4426A8U, 0x0000004BU}, /* RGIDW_MODID[508]:RTDM204*/ + [485] = {0xFD4426ACU, 0x0000004BU}, /* RGIDW_MODID[509]:RTDM205*/ + [486] = {0xFD4426B0U, 0x0000004BU}, /* RGIDW_MODID[510]:RTDM206*/ + [487] = {0xFD4426B4U, 0x0000004BU}, /* RGIDW_MODID[511]:RTDM207*/ + [488] = {0xFD4426B8U, 0x0000004BU}, /* RGIDW_MODID[512]:RTDM208*/ + [489] = {0xFD4426BCU, 0x0000004BU}, /* RGIDW_MODID[513]:RTDM209*/ + [490] = {0xFD4426C0U, 0x0000004BU}, /* RGIDW_MODID[514]:RTDM300*/ + [491] = {0xFD4426C4U, 0x0000004BU}, /* RGIDW_MODID[515]:RTDM301*/ + [492] = {0xFD4426C8U, 0x0000004BU}, /* RGIDW_MODID[516]:RTDM310*/ + [493] = {0xFD4426CCU, 0x0000004BU}, /* RGIDW_MODID[517]:RTDM311*/ + [494] = {0xFD4426D0U, 0x0000004BU}, /* RGIDW_MODID[518]:RTDM312*/ + [495] = {0xFD4426D4U, 0x0000004BU}, /* RGIDW_MODID[519]:RTDM313*/ + [496] = {0xFD4426D8U, 0x0000004BU}, /* RGIDW_MODID[520]:RTDM314*/ + [497] = {0xFD4426DCU, 0x0000004BU}, /* RGIDW_MODID[521]:RTDM315*/ + [498] = {0xFD4426E0U, 0x0000004BU}, /* RGIDW_MODID[522]:RTDM302*/ + [499] = {0xFD4426E4U, 0x0000004BU}, /* RGIDW_MODID[523]:RTDM303*/ + [500] = {0xFD4426E8U, 0x0000004BU}, /* RGIDW_MODID[524]:RTDM304*/ + [501] = {0xFD4426ECU, 0x0000004BU}, /* RGIDW_MODID[525]:RTDM305*/ + [502] = {0xFD4426F0U, 0x0000004BU}, /* RGIDW_MODID[526]:RTDM306*/ + [503] = {0xFD4426F4U, 0x0000004BU}, /* RGIDW_MODID[527]:RTDM307*/ + [504] = {0xFD4426F8U, 0x0000004BU}, /* RGIDW_MODID[528]:RTDM308*/ + [505] = {0xFD4426FCU, 0x0000004BU}, /* RGIDW_MODID[529]:RTDM309*/ + [506] = {0xFD442700U, 0x0000004EU}, /* RGIDW_MODID[530]:IPMMURT108*/ + [507] = {0xFD442704U, 0x0000004EU}, /* RGIDW_MODID[531]:IPMMURT109*/ + [508] = {0xFD442708U, 0x00000001U}, /* RGIDW_MODID[532]:SYSRAM01*/ + [509] = {0xFD44270CU, 0x0000000BU}, /* RGIDW_MODID[533]:SYSRAM02*/ + [510] = {0xFD442710U, 0x00000001U}, /* RGIDW_MODID[534]:SYSRAM03*/ + [511] = {0xFD442714U, 0x00000001U}, /* RGIDW_MODID[535]:SYSRAM04*/ + [512] = {0xFD442718U, 0x00000001U}, /* RGIDW_MODID[536]:SYSRAM05*/ + [513] = {0xFD44271CU, 0x00000001U}, /* RGIDW_MODID[537]:SYSRAM06*/ + [514] = {0xFD442720U, 0x00000000U}, /* RGIDW_MODID[538]:SYSRAM07*/ + [515] = {0xFD442724U, 0x0000000BU}, /* RGIDW_MODID[539]:SYSRAM11*/ + [516] = {0xFD442728U, 0x0000000AU}, /* RGIDW_MODID[540]:SYSRAM12*/ + [517] = {0xFD44272CU, 0x0000000BU}, /* RGIDW_MODID[541]:SYSRAM13*/ + [518] = {0xFD442730U, 0x0000000BU}, /* RGIDW_MODID[542]:SYSRAM14*/ + [519] = {0xFD442734U, 0x0000000BU}, /* RGIDW_MODID[543]:SYSRAM15*/ + [520] = {0xFD442738U, 0x0000000BU}, /* RGIDW_MODID[544]:SYSRAM16*/ + [521] = {0xFD44273CU, 0x00000000U}, /* RGIDW_MODID[545]:SYSRAM17*/ + [522] = {0xFD442760U, 0x00000002U}, /* RGIDW_MODID[546]:BKBUF*/ + [523] = {0xFD442764U, 0x00000003U}, /* RGIDW_MODID[547]:AXICR52SS1*/ + [524] = {0xFD442768U, 0x00000003U}, /* RGIDW_MODID[548]:AXICR52SS2*/ + [525] = {0xFC862400U, 0x00000002U}, /* RGIDW_MODID[549]:ARSC0*/ + /* After setting */ /* RGIDW_MODID[550]:ARSC1*/ + /* After setting */ /* RGIDW_MODID[551]:ARSC2*/ + [526] = {0xFC86240CU, 0x00000001U}, /* RGIDW_MODID[552]:ARSC3*/ + [527] = {0xFC862410U, 0x00000002U}, /* RGIDW_MODID[553]:ARSC4*/ + [528] = {0xFC862414U, 0x00000001U}, /* RGIDW_MODID[554]:ARSC5*/ + [529] = {0xFC862418U, 0x00000002U}, /* RGIDW_MODID[555]:ARSC6*/ + [530] = {0xFC86241CU, 0x00000002U}, /* RGIDW_MODID[556]:ARSC7*/ + [531] = {0xFC862420U, 0x00000000U}, /* RGIDW_MODID[557]:ARSC8*/ + [532] = {0xFC862424U, 0x00000002U}, /* RGIDW_MODID[558]:ARSTM0*/ + /* After setting */ /* RGIDW_MODID[559]:ARSTM1*/ + [533] = {0xFC86242CU, 0x0000000EU}, /* RGIDW_MODID[560]:CSD1S*/ + [534] = {0xFC862430U, 0x0000000EU}, /* RGIDW_MODID[561]:AXIFBABUSTOP0*/ + [535] = {0xFC862434U, 0x0000000EU}, /* RGIDW_MODID[562]:AXIFBABUSTOP1*/ + /* After setting */ /* RGIDW_MODID[563]:ARSTM2*/ + [536] = {0xFC86243CU, 0x00000001U}, /* RGIDW_MODID[564]:ARSTM3*/ + [537] = {0xFC862440U, 0x00000002U}, /* RGIDW_MODID[565]:ARSTM4*/ + [538] = {0xFC862444U, 0x00000001U}, /* RGIDW_MODID[566]:ARSTM5*/ + [539] = {0xFC862448U, 0x00000002U}, /* RGIDW_MODID[567]:ARSTM6*/ + [540] = {0xFC86244CU, 0x00000002U}, /* RGIDW_MODID[568]:ARSTM7*/ + [541] = {0xFC862450U, 0x00000000U}, /* RGIDW_MODID[569]:ARSTM8*/ + [542] = {0xFC862454U, 0x0000000AU}, /* RGIDW_MODID[570]:ECMTOP*/ + [543] = {0xFC862458U, 0x0000000EU}, /* RGIDW_MODID[571]:FBA*/ + [544] = {0xFC86245CU, 0x0000000EU}, /* RGIDW_MODID[572]:FBC*/ + [545] = {0xFC862460U, 0x0000000CU}, /* RGIDW_MODID[573]:AXICCI00*/ + [546] = {0xFC862464U, 0x0000000EU}, /* RGIDW_MODID[574]:AXICCI01*/ + [547] = {0xFC862468U, 0x0000000CU}, /* RGIDW_MODID[575]:AXICCI10*/ + [548] = {0xFC86246CU, 0x0000000CU}, /* RGIDW_MODID[576]:AXICCI11*/ + [549] = {0xFC862470U, 0x0000000CU}, /* RGIDW_MODID[577]:AXICCI12*/ + [550] = {0xFC862474U, 0x0000000CU}, /* RGIDW_MODID[578]:AXICCI13*/ + [551] = {0xFC862478U, 0x0000000CU}, /* RGIDW_MODID[579]:AXICCI14*/ + [552] = {0xFC86247CU, 0x0000000CU}, /* RGIDW_MODID[580]:AXICCI15*/ + [553] = {0xFC862480U, 0x0000000EU}, /* RGIDW_MODID[581]:AXICCI2*/ + [554] = {0xFC862484U, 0x0000000CU}, /* RGIDW_MODID[582]:AXICCI3*/ + [555] = {0xFC862488U, 0x0000000CU}, /* RGIDW_MODID[583]:AXICCI4*/ + [556] = {0xFC86248CU, 0x0000000CU}, /* RGIDW_MODID[584]:AXICCI5*/ + [557] = {0xFC862490U, 0x0000000CU}, /* RGIDW_MODID[585]:AXICCI6*/ + [558] = {0xFC862494U, 0x0000000CU}, /* RGIDW_MODID[586]:AXICCI7*/ + [559] = {0xFC862498U, 0x0000000CU}, /* RGIDW_MODID[587]:AXICCI8*/ + [560] = {0xFC86249CU, 0x00000009U}, /* RGIDW_MODID[588]:AXICCI9*/ + [561] = {0xFC8624A0U, 0x0000000AU}, /* RGIDW_MODID[589]:ECMSTM*/ + [562] = {0xFCB82400U, 0x0000002CU}, /* RGIDW_MODID[590]:DMASSI00*/ + [563] = {0xFCB82404U, 0x0000002CU}, /* RGIDW_MODID[591]:DMASSI01*/ + [564] = {0xFCB82408U, 0x0000002CU}, /* RGIDW_MODID[592]:DMASSI02*/ + [565] = {0xFCB8240CU, 0x0000002CU}, /* RGIDW_MODID[593]:DMASSI03*/ + [566] = {0xFCB82410U, 0x0000002CU}, /* RGIDW_MODID[594]:DMASSI04*/ + [567] = {0xFCB82414U, 0x0000004EU}, /* RGIDW_MODID[595]:DMAI2C0*/ + [568] = {0xFCB82418U, 0x0000004EU}, /* RGIDW_MODID[596]:DMAI2C1*/ + [569] = {0xFCB8241CU, 0x0000004EU}, /* RGIDW_MODID[597]:DMAI2C2*/ + [570] = {0xFCB82420U, 0x0000004EU}, /* RGIDW_MODID[598]:DMAI2C3*/ + [571] = {0xFCB82424U, 0x0000004EU}, /* RGIDW_MODID[599]:DMAI2C4*/ + [572] = {0xFCB82428U, 0x0000004EU}, /* RGIDW_MODID[600]:DMAI2C5*/ + [573] = {0xFCB8242CU, 0x0000002CU}, /* RGIDW_MODID[601]:DMASSI05*/ + [574] = {0xFCB82430U, 0x0000002CU}, /* RGIDW_MODID[602]:DMASSI06*/ + [575] = {0xFCB82434U, 0x0000002CU}, /* RGIDW_MODID[603]:DMASSI07*/ + [576] = {0xFDDC2400U, 0x00000002U}, /* RGIDW_MODID[604]:ARMM*/ + /* After setting */ /* RGIDW_MODID[605]:AXIARNMM*/ + [577] = {0xFDDC2408U, 0x00000002U}, /* RGIDW_MODID[606]:ARSM0*/ + /* After setting */ /* RGIDW_MODID[607]:ARSM1*/ + /* After setting */ /* RGIDW_MODID[608]:ARSM2*/ + [578] = {0xFDDC2414U, 0x0000000FU}, /* RGIDW_MODID[609]:AXIQOS0*/ + [579] = {0xFDDC2418U, 0x0000000FU}, /* RGIDW_MODID[610]:AXIQOS1*/ + [580] = {0xFDDC241CU, 0x0000000FU}, /* RGIDW_MODID[611]:AXIQOS2*/ + [581] = {0xFDDC2420U, 0x0000000FU}, /* RGIDW_MODID[612]:AXIQOS3*/ + [582] = {0xFDDC2424U, 0x0000000FU}, /* RGIDW_MODID[613]:AXIQOS4*/ + [583] = {0xFDDC2428U, 0x0000000FU}, /* RGIDW_MODID[614]:AXIQOS5*/ + [584] = {0xFDDC242CU, 0x0000000FU}, /* RGIDW_MODID[615]:AXIQOS6*/ + [585] = {0xFDDC2430U, 0x0000000FU}, /* RGIDW_MODID[616]:AXIQOS7*/ + [586] = {0xFDDC2434U, 0x00000001U}, /* RGIDW_MODID[617]:ARSM3*/ + [587] = {0xFDDC2438U, 0x00000002U}, /* RGIDW_MODID[618]:ARSM4*/ + [588] = {0xFDDC243CU, 0x00000001U}, /* RGIDW_MODID[619]:ARSM5*/ + [589] = {0xFDDC2440U, 0x00000002U}, /* RGIDW_MODID[620]:ARSM6*/ + [590] = {0xFDDC2444U, 0x00000002U}, /* RGIDW_MODID[621]:ARSM7*/ + [591] = {0xFDDC2448U, 0x00000000U}, /* RGIDW_MODID[622]:ARSM8*/ + [592] = {0xFDDC244CU, 0x0000000BU}, /* RGIDW_MODID[623]:AXMM0*/ + [593] = {0xFDDC2450U, 0x0000000BU}, /* RGIDW_MODID[624]:AXMM1*/ + [594] = {0xFDDC2454U, 0x00000000U}, /* RGIDW_MODID[625]:AXMMPMON*/ + [595] = {0xFDDC2458U, 0x0000000AU}, /* RGIDW_MODID[626]:CKMMM*/ + [596] = {0xFDDC245CU, 0x0000000AU}, /* RGIDW_MODID[627]:ECMMM*/ + [597] = {0xFDDC2460U, 0x0000000EU}, /* RGIDW_MODID[628]:FBADBSC0*/ + [598] = {0xFDDC2464U, 0x0000000EU}, /* RGIDW_MODID[629]:FBADBSC1*/ + [599] = {0xFDDC2468U, 0x0000000EU}, /* RGIDW_MODID[630]:FBAMM*/ + [600] = {0xFDDC246CU, 0x0000004EU}, /* RGIDW_MODID[631]:IPMMUMM00*/ + [601] = {0xFDDC2470U, 0x0000000FU}, /* RGIDW_MODID[632]:DBS0A0*/ + [602] = {0xFDDC2474U, 0x0000000AU}, /* RGIDW_MODID[633]:DBS0A1*/ + [603] = {0xFDDC2478U, 0x0000000FU}, /* RGIDW_MODID[634]:DBS1A0*/ + [604] = {0xFDDC247CU, 0x0000000AU}, /* RGIDW_MODID[635]:DBS1A1*/ + [605] = {0xFDDC2480U, 0x0000000FU}, /* RGIDW_MODID[636]:AXCIDBS*/ + [606] = {0xFDDC2484U, 0x00000009U}, /* RGIDW_MODID[637]:FCPRC*/ + [607] = {0xFDDC2488U, 0x0000000FU}, /* RGIDW_MODID[638]:DBS0D0*/ + [608] = {0xFDDC248CU, 0x0000000AU}, /* RGIDW_MODID[639]:DBS0D1*/ + [609] = {0xFDDC2490U, 0x0000000FU}, /* RGIDW_MODID[640]:DBS1D0*/ + [610] = {0xFDDC2494U, 0x0000000AU}, /* RGIDW_MODID[641]:DBS1D1*/ + [611] = {0xFDDC2498U, 0x0000000EU}, /* RGIDW_MODID[642]:FBADDR*/ + [612] = {0xFDDC249CU, 0x0000004EU}, /* RGIDW_MODID[643]:IPMMUMM01*/ + [613] = {0xFDDC24A0U, 0x0000004EU}, /* RGIDW_MODID[644]:IPMMUMM10*/ + [614] = {0xFDDC24A4U, 0x0000004EU}, /* RGIDW_MODID[645]:IPMMUMM11*/ + [615] = {0xFDDC24A8U, 0x0000004EU}, /* RGIDW_MODID[646]:IPMMUMM12*/ + [616] = {0xFDDC24ACU, 0x0000004EU}, /* RGIDW_MODID[647]:IPMMUMM13*/ + [617] = {0xFDDC24B0U, 0x0000004EU}, /* RGIDW_MODID[648]:IPMMUMM14*/ + [618] = {0xFDDC24B4U, 0x0000004EU}, /* RGIDW_MODID[649]:IPMMUMM15*/ + [619] = {0xFDDC24B8U, 0x0000004EU}, /* RGIDW_MODID[650]:IPMMUMM02*/ + [620] = {0xFDDC24BCU, 0x0000004EU}, /* RGIDW_MODID[651]:IPMMUMM03*/ + [621] = {0xFDDC24C0U, 0x0000004EU}, /* RGIDW_MODID[652]:IPMMUMM04*/ + [622] = {0xFDDC24C4U, 0x0000004EU}, /* RGIDW_MODID[653]:IPMMUMM05*/ + [623] = {0xFDDC24C8U, 0x0000004EU}, /* RGIDW_MODID[654]:IPMMUMM06*/ + [624] = {0xFDDC24CCU, 0x0000004EU}, /* RGIDW_MODID[655]:IPMMUMM07*/ + [625] = {0xFDDC24D0U, 0x0000004EU}, /* RGIDW_MODID[656]:IPMMUMM08*/ + [626] = {0xFDDC24D4U, 0x0000004EU}, /* RGIDW_MODID[657]:IPMMUMM09*/ + [627] = {0xFC802400U, 0x00000002U}, /* RGIDW_MODID[658]:ARSN0*/ + /* After setting */ /* RGIDW_MODID[659]:ARSN1*/ + /* After setting */ /* RGIDW_MODID[660]:ARSN2*/ + [628] = {0xFC80240CU, 0x00000001U}, /* RGIDW_MODID[661]:ARSN3*/ + [629] = {0xFC802410U, 0x00000002U}, /* RGIDW_MODID[662]:ARSN4*/ + [630] = {0xFC802414U, 0x00000001U}, /* RGIDW_MODID[663]:ARSN5*/ + [631] = {0xFC802418U, 0x00000002U}, /* RGIDW_MODID[664]:ARSN6*/ + [632] = {0xFC80241CU, 0x00000002U}, /* RGIDW_MODID[665]:ARSN7*/ + [633] = {0xFC802420U, 0x00000000U}, /* RGIDW_MODID[666]:ARSN8*/ + [634] = {0xFC802424U, 0x0000000AU}, /* RGIDW_MODID[667]:ECMTOP3*/ + [635] = {0xFCB52400U, 0x00000002U}, /* RGIDW_MODID[668]:ARSD00*/ + /* After setting */ /* RGIDW_MODID[669]:ARSD01*/ + /* After setting */ /* RGIDW_MODID[670]:ARSD02*/ + [636] = {0xFCB5240CU, 0x00000001U}, /* RGIDW_MODID[671]:ARSD03*/ + [637] = {0xFCB52410U, 0x00000002U}, /* RGIDW_MODID[672]:ARSD04*/ + [638] = {0xFCB52414U, 0x00000001U}, /* RGIDW_MODID[673]:ARSD05*/ + [639] = {0xFCB52418U, 0x00000002U}, /* RGIDW_MODID[674]:ARSD06*/ + [640] = {0xFCB5241CU, 0x0000004AU}, /* RGIDW_MODID[675]:AXIFRAY*/ + [641] = {0xFCB52420U, 0x0000000FU}, /* RGIDW_MODID[676]:AXIIPC*/ + [642] = {0xFCB52428U, 0x0000004FU}, /* RGIDW_MODID[677]:AXIRPC*/ + [643] = {0xFCB5242CU, 0x0000000FU}, /* RGIDW_MODID[678]:AXISDHI0*/ + [644] = {0xFCB52430U, 0x00000002U}, /* RGIDW_MODID[679]:ARSD07*/ + [645] = {0xFCB52434U, 0x00000000U}, /* RGIDW_MODID[680]:ARSD08*/ + [646] = {0xFCB52438U, 0x00000002U}, /* RGIDW_MODID[681]:ARSP00*/ + /* After setting */ /* RGIDW_MODID[682]:ARSP01*/ + /* After setting */ /* RGIDW_MODID[683]:ARSP02*/ + [647] = {0xFCB52444U, 0x00000001U}, /* RGIDW_MODID[684]:ARSP03*/ + [648] = {0xFCB52448U, 0x00000002U}, /* RGIDW_MODID[685]:ARSP04*/ + [649] = {0xFCB5244CU, 0x00000001U}, /* RGIDW_MODID[686]:ARSP05*/ + [650] = {0xFCB52450U, 0x00000002U}, /* RGIDW_MODID[687]:ARSP06*/ + [651] = {0xFCB52454U, 0x00000002U}, /* RGIDW_MODID[688]:ARSP07*/ + [652] = {0xFCB52458U, 0x00000000U}, /* RGIDW_MODID[689]:ARSP08*/ + [653] = {0xFCB5245CU, 0x0000004EU}, /* RGIDW_MODID[690]:IPMMUDS001*/ + [654] = {0xFCB52460U, 0x0000000AU}, /* RGIDW_MODID[691]:CKMPER0*/ + [655] = {0xFCB52464U, 0x0000000AU}, /* RGIDW_MODID[692]:ECMPER0*/ + [656] = {0xFCB52468U, 0x0000000EU}, /* RGIDW_MODID[693]:FBAPER0*/ + [657] = {0xFCB5246CU, 0x0000004EU}, /* RGIDW_MODID[694]:FSO0*/ + [658] = {0xFCB52470U, 0x0000004EU}, /* RGIDW_MODID[695]:FSO1*/ + [659] = {0xFCB52474U, 0x0000004EU}, /* RGIDW_MODID[696]:FSO10*/ + [660] = {0xFCB52478U, 0x0000004EU}, /* RGIDW_MODID[697]:FSO2*/ + [661] = {0xFCB5247CU, 0x0000004EU}, /* RGIDW_MODID[698]:FSO3*/ + [662] = {0xFCB52480U, 0x0000004EU}, /* RGIDW_MODID[699]:FSO4*/ + [663] = {0xFCB52484U, 0x0000004EU}, /* RGIDW_MODID[700]:FSO5*/ + [664] = {0xFCB52488U, 0x0000004EU}, /* RGIDW_MODID[701]:FSO6*/ + [665] = {0xFCB5248CU, 0x0000004EU}, /* RGIDW_MODID[702]:FSO7*/ + [666] = {0xFCB52490U, 0x0000004EU}, /* RGIDW_MODID[703]:FSO8*/ + [667] = {0xFCB52494U, 0x0000004EU}, /* RGIDW_MODID[704]:FSO9*/ + [668] = {0xFCB52498U, 0x0000002CU}, /* RGIDW_MODID[705]:ADG*/ + [669] = {0xFCB5249CU, 0x0000000AU}, /* RGIDW_MODID[706]:ECMSD0*/ + [670] = {0xFCB524A0U, 0x0000004EU}, /* RGIDW_MODID[707]:IPMMUDS010*/ + [671] = {0xFCB524A4U, 0x0000004EU}, /* RGIDW_MODID[708]:IPMMUDS011*/ + [672] = {0xFCB524A8U, 0x0000004EU}, /* RGIDW_MODID[709]:I2C0*/ + [673] = {0xFCB524ACU, 0x0000004EU}, /* RGIDW_MODID[710]:I2C1*/ + [674] = {0xFCB524B0U, 0x0000004EU}, /* RGIDW_MODID[711]:I2C2*/ + [675] = {0xFCB524B4U, 0x0000004EU}, /* RGIDW_MODID[712]:I2C3*/ + [676] = {0xFCB524B8U, 0x0000004EU}, /* RGIDW_MODID[713]:I2C4*/ + [677] = {0xFCB524BCU, 0x0000004EU}, /* RGIDW_MODID[714]:I2C5*/ + [678] = {0xFCB524C0U, 0x0000004EU}, /* RGIDW_MODID[715]:IPMMUDS012*/ + [679] = {0xFCB524C4U, 0x0000000FU}, /* RGIDW_MODID[716]:IPC*/ + [680] = {0xFCB524C8U, 0x0000004EU}, /* RGIDW_MODID[717]:IPMMUDS000*/ + [681] = {0xFCB524CCU, 0x0000004EU}, /* RGIDW_MODID[718]:IPMMUDS013*/ + [682] = {0xFCB524D0U, 0x0000004EU}, /* RGIDW_MODID[719]:IPMMUDS014*/ + [683] = {0xFCB524D4U, 0x0000004EU}, /* RGIDW_MODID[720]:IPMMUDS015*/ + [684] = {0xFCB524D8U, 0x0000004EU}, /* RGIDW_MODID[721]:IPMMUDS002*/ + [685] = {0xFCB524DCU, 0x0000004EU}, /* RGIDW_MODID[722]:IPMMUDS003*/ + [686] = {0xFCB524E0U, 0x0000004EU}, /* RGIDW_MODID[723]:IPMMUDS004*/ + [687] = {0xFCB524E4U, 0x0000004EU}, /* RGIDW_MODID[724]:IPMMUDS005*/ + [688] = {0xFCB524E8U, 0x0000002CU}, /* RGIDW_MODID[725]:SSI*/ + [689] = {0xFCB524ECU, 0x0000004EU}, /* RGIDW_MODID[726]:IPMMUDS006*/ + [690] = {0xFCB524F0U, 0x0000004EU}, /* RGIDW_MODID[727]:IPMMUDS007*/ + [691] = {0xFCB524F4U, 0x0000000CU}, /* RGIDW_MODID[728]:SYDM1P*/ + [692] = {0xFCB524F8U, 0x0000004EU}, /* RGIDW_MODID[729]:IPMMUDS008*/ + [693] = {0xFCB524FCU, 0x0000000CU}, /* RGIDW_MODID[730]:SYDM2P*/ + [694] = {0xFCB52500U, 0x0000004EU}, /* RGIDW_MODID[731]:IPMMUDS009*/ + [695] = {0xFCB52640U, 0x0000000CU}, /* RGIDW_MODID[732]:SYDM100*/ + [696] = {0xFCB52644U, 0x0000000CU}, /* RGIDW_MODID[733]:SYDM101*/ + [697] = {0xFCB52648U, 0x0000000CU}, /* RGIDW_MODID[734]:SYDM110*/ + [698] = {0xFCB5264CU, 0x0000000CU}, /* RGIDW_MODID[735]:SYDM111*/ + [699] = {0xFCB52650U, 0x0000000CU}, /* RGIDW_MODID[736]:SYDM112*/ + [700] = {0xFCB52654U, 0x0000000CU}, /* RGIDW_MODID[737]:SYDM113*/ + [701] = {0xFCB52658U, 0x0000000CU}, /* RGIDW_MODID[738]:SYDM114*/ + [702] = {0xFCB5265CU, 0x0000000CU}, /* RGIDW_MODID[739]:SYDM115*/ + [703] = {0xFCB52660U, 0x0000000CU}, /* RGIDW_MODID[740]:SYDM102*/ + [704] = {0xFCB52664U, 0x0000000CU}, /* RGIDW_MODID[741]:SYDM103*/ + [705] = {0xFCB52668U, 0x0000000CU}, /* RGIDW_MODID[742]:SYDM104*/ + [706] = {0xFCB5266CU, 0x0000000CU}, /* RGIDW_MODID[743]:SYDM105*/ + [707] = {0xFCB52670U, 0x0000000CU}, /* RGIDW_MODID[744]:SYDM106*/ + [708] = {0xFCB52674U, 0x0000000CU}, /* RGIDW_MODID[745]:SYDM107*/ + [709] = {0xFCB52678U, 0x0000000CU}, /* RGIDW_MODID[746]:SYDM108*/ + [710] = {0xFCB5267CU, 0x0000000CU}, /* RGIDW_MODID[747]:SYDM109*/ + [711] = {0xFCB52680U, 0x0000000CU}, /* RGIDW_MODID[748]:SYDM200*/ + [712] = {0xFCB52684U, 0x0000000CU}, /* RGIDW_MODID[749]:SYDM201*/ + [713] = {0xFCB52688U, 0x0000000CU}, /* RGIDW_MODID[750]:SYDM210*/ + [714] = {0xFCB5268CU, 0x0000000CU}, /* RGIDW_MODID[751]:SYDM211*/ + [715] = {0xFCB52690U, 0x0000000CU}, /* RGIDW_MODID[752]:SYDM212*/ + [716] = {0xFCB52694U, 0x0000000CU}, /* RGIDW_MODID[753]:SYDM213*/ + [717] = {0xFCB52698U, 0x0000000CU}, /* RGIDW_MODID[754]:SYDM214*/ + [718] = {0xFCB5269CU, 0x0000000CU}, /* RGIDW_MODID[755]:SYDM215*/ + [719] = {0xFCB526A0U, 0x0000000CU}, /* RGIDW_MODID[756]:SYDM202*/ + [720] = {0xFCB526A4U, 0x0000000CU}, /* RGIDW_MODID[757]:SYDM203*/ + [721] = {0xFCB526A8U, 0x0000000CU}, /* RGIDW_MODID[758]:SYDM204*/ + [722] = {0xFCB526ACU, 0x0000000CU}, /* RGIDW_MODID[759]:SYDM205*/ + [723] = {0xFCB526B0U, 0x0000000CU}, /* RGIDW_MODID[760]:SYDM206*/ + [724] = {0xFCB526B4U, 0x0000000CU}, /* RGIDW_MODID[761]:SYDM207*/ + [725] = {0xFCB526B8U, 0x0000000CU}, /* RGIDW_MODID[762]:SYDM208*/ + [726] = {0xFCB526BCU, 0x0000000CU}, /* RGIDW_MODID[763]:SYDM209*/ + [727] = {0xFC682400U, 0x00000002U}, /* RGIDW_MODID[764]:ARVC0*/ + /* After setting */ /* RGIDW_MODID[765]:ARVC1*/ + /* After setting */ /* RGIDW_MODID[766]:ARVC2*/ + [728] = {0xFC68240CU, 0x00000001U}, /* RGIDW_MODID[767]:ARVC3*/ + [729] = {0xFC682410U, 0x0000000EU}, /* RGIDW_MODID[768]:AXIFBABUSVC*/ + [730] = {0xFC682414U, 0x00000002U}, /* RGIDW_MODID[769]:ARVC4*/ + [731] = {0xFC682418U, 0x00000001U}, /* RGIDW_MODID[770]:ARVC5*/ + [732] = {0xFC68241CU, 0x00000002U}, /* RGIDW_MODID[771]:ARVC6*/ + [733] = {0xFC682420U, 0x00000002U}, /* RGIDW_MODID[772]:ARVC7*/ + [734] = {0xFC682424U, 0x00000000U}, /* RGIDW_MODID[773]:ARVC8*/ + [735] = {0xFC682428U, 0x0000000AU}, /* RGIDW_MODID[774]:CKMVC*/ + [736] = {0xFC68242CU, 0x0000000AU}, /* RGIDW_MODID[775]:ECMVC0*/ + [737] = {0xFC682430U, 0x0000004EU}, /* RGIDW_MODID[776]:IMR2*/ + [738] = {0xFC682434U, 0x0000004EU}, /* RGIDW_MODID[777]:IMR0*/ + [739] = {0xFC682438U, 0x0000004EU}, /* RGIDW_MODID[778]:IMR1*/ + [740] = {0xFC68243CU, 0x0000004EU}, /* RGIDW_MODID[779]:IPMMUVC01*/ + [741] = {0xFC682440U, 0x0000004EU}, /* RGIDW_MODID[780]:IPMMUVC10*/ + [742] = {0xFC682444U, 0x0000000CU}, /* RGIDW_MODID[781]:IMS0*/ + [743] = {0xFC682448U, 0x0000000CU}, /* RGIDW_MODID[782]:IMS1*/ + [744] = {0xFC68244CU, 0x0000004EU}, /* RGIDW_MODID[783]:IPMMUVC00*/ + [745] = {0xFC682450U, 0x0000004EU}, /* RGIDW_MODID[784]:IPMMUVC11*/ + [746] = {0xFC682454U, 0x0000004EU}, /* RGIDW_MODID[785]:IPMMUVC12*/ + [747] = {0xFC682458U, 0x0000004EU}, /* RGIDW_MODID[786]:IPMMUVC13*/ + [748] = {0xFC68245CU, 0x0000004EU}, /* RGIDW_MODID[787]:IPMMUVC14*/ + [749] = {0xFC682460U, 0x0000004EU}, /* RGIDW_MODID[788]:IPMMUVC15*/ + [750] = {0xFC682464U, 0x0000004EU}, /* RGIDW_MODID[789]:IPMMUVC02*/ + [751] = {0xFC682468U, 0x0000004EU}, /* RGIDW_MODID[790]:IPMMUVC03*/ + [752] = {0xFC68246CU, 0x0000004EU}, /* RGIDW_MODID[791]:IPMMUVC04*/ + [753] = {0xFC682470U, 0x0000004EU}, /* RGIDW_MODID[792]:IPMMUVC05*/ + [754] = {0xFC682474U, 0x0000004EU}, /* RGIDW_MODID[793]:IPMMUVC06*/ + [755] = {0xFC682478U, 0x0000004EU}, /* RGIDW_MODID[794]:IPMMUVC07*/ + [756] = {0xFC68247CU, 0x0000004EU}, /* RGIDW_MODID[795]:IPMMUVC08*/ + [757] = {0xFC682480U, 0x0000004EU}, /* RGIDW_MODID[796]:IPMMUVC09*/ + [758] = {0xFC682484U, 0x00000028U}, /* RGIDW_MODID[797]:IV1ES*/ + [759] = {0xFEBE2400U, 0x0000004EU}, /* RGIDW_MODID[798]:CSITOP0*/ + [760] = {0xFEBE2404U, 0x00000002U}, /* RGIDW_MODID[799]:ARVI10*/ + /* After setting */ /* RGIDW_MODID[800]:ARVI11*/ + /* After setting */ /* RGIDW_MODID[801]:ARVI12*/ + [761] = {0xFEBE2410U, 0x00000001U}, /* RGIDW_MODID[802]:ARVI13*/ + [762] = {0xFEBE2414U, 0x00000002U}, /* RGIDW_MODID[803]:ARVI14*/ + [763] = {0xFEBE2418U, 0x00000001U}, /* RGIDW_MODID[804]:ARVI15*/ + [764] = {0xFEBE241CU, 0x00000002U}, /* RGIDW_MODID[805]:ARVI16*/ + [765] = {0xFEBE2420U, 0x00000002U}, /* RGIDW_MODID[806]:ARVI17*/ + [766] = {0xFEBE2424U, 0x00000000U}, /* RGIDW_MODID[807]:ARVI18*/ + [767] = {0xFEBE2428U, 0x0000000AU}, /* RGIDW_MODID[808]:CKMVIO*/ + [768] = {0xFEBE242CU, 0x0000004EU}, /* RGIDW_MODID[809]:CSITOP1*/ + [769] = {0xFEBE2434U, 0x0000004EU}, /* RGIDW_MODID[810]:DSITLINK0*/ + [770] = {0xFEBE2438U, 0x0000004EU}, /* RGIDW_MODID[811]:DSITLINK1*/ + [771] = {0xFEBE243CU, 0x0000000AU}, /* RGIDW_MODID[812]:ECMVIO1*/ + [772] = {0xFEBE2444U, 0x0000004EU}, /* RGIDW_MODID[813]:IPMMUVI001*/ + [773] = {0xFEBE2448U, 0x0000000CU}, /* RGIDW_MODID[814]:FCPVX0*/ + [774] = {0xFEBE244CU, 0x0000000CU}, /* RGIDW_MODID[815]:FCPVX1*/ + [775] = {0xFEBE2458U, 0x0000004EU}, /* RGIDW_MODID[816]:IPMMUVI000*/ + [776] = {0xFEBE245CU, 0x0000004EU}, /* RGIDW_MODID[817]:IPMMUVI100*/ + [777] = {0xFEBE2460U, 0x0000004EU}, /* RGIDW_MODID[818]:IPMMUVI010*/ + [778] = {0xFEBE2464U, 0x0000004EU}, /* RGIDW_MODID[819]:IPMMUVI011*/ + [779] = {0xFEBE2468U, 0x0000004EU}, /* RGIDW_MODID[820]:VSPX0*/ + [780] = {0xFEBE246CU, 0x0000004EU}, /* RGIDW_MODID[821]:VSPX1*/ + [781] = {0xFEBE2478U, 0x0000004EU}, /* RGIDW_MODID[822]:IPMMUVI012*/ + [782] = {0xFEBE247CU, 0x0000004EU}, /* RGIDW_MODID[823]:IPMMUVI013*/ + [783] = {0xFEBE2480U, 0x0000004EU}, /* RGIDW_MODID[824]:IPMMUVI014*/ + [784] = {0xFEBE2484U, 0x0000004EU}, /* RGIDW_MODID[825]:IPMMUVI015*/ + [785] = {0xFEBE2488U, 0x0000004EU}, /* RGIDW_MODID[826]:IPMMUVI002*/ + [786] = {0xFEBE248CU, 0x0000004EU}, /* RGIDW_MODID[827]:IPMMUVI003*/ + [787] = {0xFEBE2490U, 0x0000004EU}, /* RGIDW_MODID[828]:IPMMUVI004*/ + [788] = {0xFEBE2494U, 0x0000004EU}, /* RGIDW_MODID[829]:IPMMUVI005*/ + [789] = {0xFEBE2498U, 0x0000004EU}, /* RGIDW_MODID[830]:IPMMUVI006*/ + [790] = {0xFEBE249CU, 0x0000004EU}, /* RGIDW_MODID[831]:IPMMUVI007*/ + [791] = {0xFEBE24A0U, 0x0000004EU}, /* RGIDW_MODID[832]:IPMMUVI008*/ + [792] = {0xFEBE24A4U, 0x0000004EU}, /* RGIDW_MODID[833]:IPMMUVI009*/ + [793] = {0xFEBE24A8U, 0x0000004EU}, /* RGIDW_MODID[834]:IPMMUVI101*/ + [794] = {0xFEBE24ACU, 0x0000004EU}, /* RGIDW_MODID[835]:IPMMUVI110*/ + [795] = {0xFEBE24B0U, 0x0000004EU}, /* RGIDW_MODID[836]:IPMMUVI111*/ + [796] = {0xFEBE24B4U, 0x0000004EU}, /* RGIDW_MODID[837]:IPMMUVI112*/ + [797] = {0xFEBE24B8U, 0x0000004EU}, /* RGIDW_MODID[838]:IPMMUVI113*/ + [798] = {0xFEBE24BCU, 0x0000004EU}, /* RGIDW_MODID[839]:IPMMUVI114*/ + [799] = {0xFEBE24C0U, 0x0000004EU}, /* RGIDW_MODID[840]:IPMMUVI115*/ + [800] = {0xFEBE24C4U, 0x0000004EU}, /* RGIDW_MODID[841]:IPMMUVI102*/ + [801] = {0xFEBE24C8U, 0x0000004EU}, /* RGIDW_MODID[842]:IPMMUVI103*/ + [802] = {0xFEBE24CCU, 0x0000004EU}, /* RGIDW_MODID[843]:IPMMUVI104*/ + [803] = {0xFEBE24D0U, 0x0000004EU}, /* RGIDW_MODID[844]:IPMMUVI105*/ + [804] = {0xFEBE24D4U, 0x0000004EU}, /* RGIDW_MODID[845]:IPMMUVI106*/ + [805] = {0xFEBE24D8U, 0x0000004EU}, /* RGIDW_MODID[846]:IPMMUVI107*/ + [806] = {0xFEBE24DCU, 0x0000004EU}, /* RGIDW_MODID[847]:IPMMUVI108*/ + [807] = {0xFEBE24E0U, 0x0000004EU}, /* RGIDW_MODID[848]:IPMMUVI109*/ + [808] = {0xFEBE2504U, 0x0000000EU}, /* RGIDW_MODID[849]:AXIFBABUSVIO*/ + [809] = {0xFEBF2400U, 0x00000002U}, /* RGIDW_MODID[850]:ARVI0*/ + /* After setting */ /* RGIDW_MODID[851]:ARVI1*/ + /* After setting */ /* RGIDW_MODID[852]:ARVI2*/ + [810] = {0xFEBF240CU, 0x00000001U}, /* RGIDW_MODID[853]:ARVI3*/ + [811] = {0xFEBF2410U, 0x00000002U}, /* RGIDW_MODID[854]:ARVI4*/ + [812] = {0xFEBF2414U, 0x00000001U}, /* RGIDW_MODID[855]:ARVI5*/ + [813] = {0xFEBF2418U, 0x00000002U}, /* RGIDW_MODID[856]:ARVI6*/ + [814] = {0xFEBF241CU, 0x00000002U}, /* RGIDW_MODID[857]:ARVI7*/ + [815] = {0xFEBF2420U, 0x00000000U}, /* RGIDW_MODID[858]:ARVI8*/ + [816] = {0xFEBF2424U, 0x0000000AU}, /* RGIDW_MODID[859]:ECMVIO0*/ + [817] = {0xFEBF2428U, 0x0000004EU}, /* RGIDW_MODID[860]:ISP0*/ + [818] = {0xFEBF242CU, 0x0000004EU}, /* RGIDW_MODID[861]:ISP0CORE*/ + [819] = {0xFEBF2430U, 0x0000004EU}, /* RGIDW_MODID[862]:ISP1*/ + [820] = {0xFEBF2434U, 0x0000004EU}, /* RGIDW_MODID[863]:ISP1CORE*/ + [821] = {0xFEBF2454U, 0x0000004EU}, /* RGIDW_MODID[864]:VIN00*/ + [822] = {0xFEBF2458U, 0x0000004EU}, /* RGIDW_MODID[865]:VIN01*/ + [823] = {0xFEBF245CU, 0x0000004EU}, /* RGIDW_MODID[866]:VIN02*/ + [824] = {0xFEBF2460U, 0x0000004EU}, /* RGIDW_MODID[867]:VIN03*/ + [825] = {0xFEBF2464U, 0x0000004EU}, /* RGIDW_MODID[868]:VIN04*/ + [826] = {0xFEBF2468U, 0x0000004EU}, /* RGIDW_MODID[869]:VIN05*/ + [827] = {0xFEBF246CU, 0x0000004EU}, /* RGIDW_MODID[870]:VIN06*/ + [828] = {0xFEBF2470U, 0x0000004EU}, /* RGIDW_MODID[871]:VIN07*/ + [829] = {0xFEBF2474U, 0x0000004EU}, /* RGIDW_MODID[872]:VIN10*/ + [830] = {0xFEBF2478U, 0x0000004EU}, /* RGIDW_MODID[873]:VIN11*/ + [831] = {0xFEBF247CU, 0x0000004EU}, /* RGIDW_MODID[874]:VIN12*/ + [832] = {0xFEBF2480U, 0x0000004EU}, /* RGIDW_MODID[875]:VIN13*/ + [833] = {0xFEBF2484U, 0x0000004EU}, /* RGIDW_MODID[876]:VIN14*/ + [834] = {0xFEBF2488U, 0x0000004EU}, /* RGIDW_MODID[877]:VIN15*/ + [835] = {0xFEBF248CU, 0x0000004EU}, /* RGIDW_MODID[878]:VIN16*/ + [836] = {0xFEBF2490U, 0x0000004EU}, /* RGIDW_MODID[879]:VIN17*/ + [837] = {0xFC312400U, 0x00000002U}, /* RGIDW_MODID[880]:ARVIP00*/ + /* After setting */ /* RGIDW_MODID[881]:ARVIP01*/ + /* After setting */ /* RGIDW_MODID[882]:ARVIP02*/ + [838] = {0xFC31240CU, 0x00000001U}, /* RGIDW_MODID[883]:ARVIP03*/ + [839] = {0xFC312410U, 0x0000000EU}, /* RGIDW_MODID[884]:AXIFBABUSVIP0*/ + [840] = {0xFC312414U, 0x00000002U}, /* RGIDW_MODID[885]:ARVIP04*/ + [841] = {0xFC312418U, 0x00000001U}, /* RGIDW_MODID[886]:ARVIP05*/ + [842] = {0xFC31241CU, 0x00000002U}, /* RGIDW_MODID[887]:ARVIP06*/ + [843] = {0xFC312420U, 0x00000002U}, /* RGIDW_MODID[888]:ARVIP07*/ + [844] = {0xFC312424U, 0x00000000U}, /* RGIDW_MODID[889]:ARVIP08*/ + [845] = {0xFC312428U, 0x0000000AU}, /* RGIDW_MODID[890]:CKMVIP*/ + [846] = {0xFC31242CU, 0x0000000AU}, /* RGIDW_MODID[891]:ECMVIP0*/ + [847] = {0xFC312430U, 0x0000004EU}, /* RGIDW_MODID[892]:IPMMUVIP000*/ + [848] = {0xFC312438U, 0x0000004EU}, /* RGIDW_MODID[893]:SMPO0*/ + [849] = {0xFC31243CU, 0x0000004EU}, /* RGIDW_MODID[894]:SMPS0*/ + [850] = {0xFC312440U, 0x0000000CU}, /* RGIDW_MODID[895]:UMFL0*/ + [851] = {0xFC312444U, 0x0000004EU}, /* RGIDW_MODID[896]:IPMMUVIP001*/ + [852] = {0xFC312448U, 0x0000004EU}, /* RGIDW_MODID[897]:IPMMUVIP010*/ + [853] = {0xFC31244CU, 0x0000004EU}, /* RGIDW_MODID[898]:IPMMUVIP011*/ + [854] = {0xFC312450U, 0x0000004EU}, /* RGIDW_MODID[899]:UMFL0M_W*/ + [855] = {0xFC312454U, 0x0000004EU}, /* RGIDW_MODID[900]:IPMMUVIP012*/ + [856] = {0xFC312458U, 0x0000004EU}, /* RGIDW_MODID[901]:IPMMUVIP013*/ + [857] = {0xFC31245CU, 0x0000004EU}, /* RGIDW_MODID[902]:IPMMUVIP014*/ + [858] = {0xFC312460U, 0x0000004EU}, /* RGIDW_MODID[903]:IPMMUVIP015*/ + [859] = {0xFC312464U, 0x0000004EU}, /* RGIDW_MODID[904]:IPMMUVIP002*/ + [860] = {0xFC312468U, 0x0000004EU}, /* RGIDW_MODID[905]:IPMMUVIP003*/ + [861] = {0xFC31246CU, 0x0000004EU}, /* RGIDW_MODID[906]:IPMMUVIP004*/ + [862] = {0xFC312470U, 0x0000004EU}, /* RGIDW_MODID[907]:IPMMUVIP005*/ + [863] = {0xFC312474U, 0x0000004EU}, /* RGIDW_MODID[908]:IPMMUVIP006*/ + [864] = {0xFC312478U, 0x0000004EU}, /* RGIDW_MODID[909]:IPMMUVIP007*/ + [865] = {0xFC31247CU, 0x0000004EU}, /* RGIDW_MODID[910]:IPMMUVIP008*/ + [866] = {0xFC312480U, 0x0000004EU}, /* RGIDW_MODID[911]:IPMMUVIP009*/ + [867] = {0xFC342400U, 0x00000002U}, /* RGIDW_MODID[912]:ARVIP10*/ + /* After setting */ /* RGIDW_MODID[913]:ARVIP11*/ + /* After setting */ /* RGIDW_MODID[914]:ARVIP12*/ + [868] = {0xFC34240CU, 0x00000001U}, /* RGIDW_MODID[915]:ARVIP13*/ + [869] = {0xFC342410U, 0x0000000EU}, /* RGIDW_MODID[916]:AXIFBABUSVIP1*/ + [870] = {0xFC342414U, 0x00000002U}, /* RGIDW_MODID[917]:ARVIIP14*/ + [871] = {0xFC342418U, 0x00000001U}, /* RGIDW_MODID[918]:ARVIIP15*/ + [872] = {0xFC34241CU, 0x00000002U}, /* RGIDW_MODID[919]:ARVIIP16*/ + [873] = {0xFC342420U, 0x00000002U}, /* RGIDW_MODID[920]:ARVIIP17*/ + [874] = {0xFC342424U, 0x00000000U}, /* RGIDW_MODID[921]:ARVIIP18*/ + [875] = {0xFC342438U, 0x0000000AU}, /* RGIDW_MODID[922]:ECMVIP1*/ + [876] = {0xFC34243CU, 0x0000004EU}, /* RGIDW_MODID[923]:IPMMUVIP101*/ + [877] = {0xFC342440U, 0x0000004EU}, /* RGIDW_MODID[924]:IPMMUVIP100*/ + [878] = {0xFC342444U, 0x0000004EU}, /* RGIDW_MODID[925]:IPMMUVIP110*/ + [879] = {0xFC342448U, 0x0000004EU}, /* RGIDW_MODID[926]:IPMMUVIP111*/ + [880] = {0xFC34244CU, 0x0000004EU}, /* RGIDW_MODID[927]:IPMMUVIP112*/ + [881] = {0xFC342450U, 0x0000004EU}, /* RGIDW_MODID[928]:IPMMUVIP113*/ + [882] = {0xFC342454U, 0x0000004EU}, /* RGIDW_MODID[929]:IPMMUVIP114*/ + [883] = {0xFC342458U, 0x0000004EU}, /* RGIDW_MODID[930]:IPMMUVIP115*/ + [884] = {0xFC34245CU, 0x0000004EU}, /* RGIDW_MODID[931]:IPMMUVIP102*/ + [885] = {0xFC342460U, 0x0000004EU}, /* RGIDW_MODID[932]:IPMMUVIP103*/ + [886] = {0xFC342464U, 0x0000004EU}, /* RGIDW_MODID[933]:IPMMUVIP104*/ + [887] = {0xFC342468U, 0x0000004EU}, /* RGIDW_MODID[934]:IPMMUVIP105*/ + [888] = {0xFC34246CU, 0x0000004EU}, /* RGIDW_MODID[935]:IPMMUVIP106*/ + [889] = {0xFC342470U, 0x0000004EU}, /* RGIDW_MODID[936]:IPMMUVIP107*/ + [890] = {0xFC342474U, 0x0000004EU}, /* RGIDW_MODID[937]:IPMMUVIP108*/ + [891] = {0xFC342478U, 0x0000004EU}, /* RGIDW_MODID[938]:IPMMUVIP109*/ + [892] = {0xFC342518U, 0x00000004U}, /* RGIDW_MODID[939]:PAP*/ + [893] = {0xFC402400U, 0x00000002U}, /* RGIDW_MODID[940]:ARDSP0*/ + /* After setting */ /* RGIDW_MODID[941]:ARDSP1*/ + /* After setting */ /* RGIDW_MODID[942]:ARDSP2*/ + [894] = {0xFC40240CU, 0x00000001U}, /* RGIDW_MODID[943]:ARDSP3*/ + [895] = {0xFC402410U, 0x00000002U}, /* RGIDW_MODID[944]:ARDSP4*/ + [896] = {0xFC402414U, 0x00000001U}, /* RGIDW_MODID[945]:ARDSP5*/ + [897] = {0xFC402418U, 0x00000002U}, /* RGIDW_MODID[946]:ARDSP6*/ + [898] = {0xFC40241CU, 0x00000002U}, /* RGIDW_MODID[947]:ARDSP7*/ + [899] = {0xFC402420U, 0x0000000AU}, /* RGIDW_MODID[948]:ECMDSP*/ + [900] = {0xFC402424U, 0x0000000CU}, /* RGIDW_MODID[949]:AXIDSP0*/ + [901] = {0xFC402428U, 0x0000000CU}, /* RGIDW_MODID[950]:AXIDSP1*/ + [902] = {0xFC40242CU, 0x0000000CU}, /* RGIDW_MODID[951]:AXIDSP2*/ + [903] = {0xFC402430U, 0x0000000CU}, /* RGIDW_MODID[952]:AXIDSP3*/ + [905] = {0xFDDB969CU, 0x00000000U}, /* RGIDW_MODID[953]:ARCC*/ + [904] = {0xFDDB96B0U, 0x00000000U}, /* RGIDW_MODID[954]:ARRTRAM*/ + [906] = {0xFCB52424U, 0x00000000U}, /* RGIDW_MODID[955]:RSV0*/ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_sec_tbl" +const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[] = { + [0] = {0xFD483400U, 0x00000000U}, /* SEC_MODID[0]:ARMGC0*/ + [1] = {0xFD483404U, 0x00000002U}, /* SEC_MODID[1]:ARMGC1*/ + [2] = {0xFD483408U, 0x00000002U}, /* SEC_MODID[2]:ARMGC2*/ + [3] = {0xFD48340CU, 0x00000002U}, /* SEC_MODID[3]:ARRT00*/ + [4] = {0xFD483410U, 0x00000002U}, /* SEC_MODID[4]:ARRT01*/ + [5] = {0xFD483414U, 0x00000002U}, /* SEC_MODID[5]:ARRT02*/ + [6] = {0xFD483418U, 0x00000002U}, /* SEC_MODID[6]:ARRT03*/ + [7] = {0xFD48341CU, 0x00000002U}, /* SEC_MODID[7]:ARRT04*/ + [8] = {0xFD483420U, 0x00000002U}, /* SEC_MODID[8]:ARRT05*/ + [9] = {0xFD483424U, 0x00000002U}, /* SEC_MODID[9]:ARRT06*/ + [10] = {0xFD483428U, 0x00000002U}, /* SEC_MODID[10]:ARRT07*/ + [11] = {0xFD48342CU, 0x00000002U}, /* SEC_MODID[11]:ARRT08*/ + [12] = {0xFD483430U, 0x00000000U}, /* SEC_MODID[12]:LIFEC0*/ + [13] = {0xFD483434U, 0x00000002U}, /* SEC_MODID[13]:SWDT*/ + [14] = {0xFD483438U, 0x00000002U}, /* SEC_MODID[14]:TMU0*/ + [15] = {0xFD48343CU, 0x00000002U}, /* SEC_MODID[15]:WDT*/ + [16] = {0xFD483440U, 0x00000002U}, /* SEC_MODID[16]:WWDT0*/ + [17] = {0xFD483444U, 0x00000002U}, /* SEC_MODID[17]:WWDT1*/ + [18] = {0xFD483448U, 0x00000002U}, /* SEC_MODID[18]:WWDT2*/ + [19] = {0xFD48344CU, 0x00000002U}, /* SEC_MODID[19]:WWDT3*/ + [20] = {0xFD483450U, 0x00000002U}, /* SEC_MODID[20]:WWDT4*/ + [21] = {0xFD483454U, 0x00000002U}, /* SEC_MODID[21]:WWDT5*/ + [22] = {0xFD483458U, 0x00000002U}, /* SEC_MODID[22]:WWDT6*/ + [23] = {0xFD483468U, 0x00000002U}, /* SEC_MODID[23]:ECMRT3*/ + [24] = {0xFDA03400U, 0x00000002U}, /* SEC_MODID[24]:ADVFSC*/ + [25] = {0xFDA03404U, 0x00000002U}, /* SEC_MODID[25]:APMU0*/ + [26] = {0xFDA03408U, 0x00000002U}, /* SEC_MODID[26]:APMU1*/ + [27] = {0xFDA0340CU, 0x00000002U}, /* SEC_MODID[27]:APMU10*/ + [28] = {0xFDA03410U, 0x00000002U}, /* SEC_MODID[28]:APMU11*/ + [29] = {0xFDA03414U, 0x00000002U}, /* SEC_MODID[29]:APMU12*/ + [30] = {0xFDA03418U, 0x00000002U}, /* SEC_MODID[30]:APMU13*/ + [31] = {0xFDA0341CU, 0x00000002U}, /* SEC_MODID[31]:APMU14*/ + [32] = {0xFDA03420U, 0x00000002U}, /* SEC_MODID[32]:APMU15*/ + [33] = {0xFDA03424U, 0x00000002U}, /* SEC_MODID[33]:APMU2*/ + [34] = {0xFDA03428U, 0x00000002U}, /* SEC_MODID[34]:APMU3*/ + [35] = {0xFDA0342CU, 0x00000002U}, /* SEC_MODID[35]:APMU4*/ + [36] = {0xFDA03430U, 0x00000002U}, /* SEC_MODID[36]:APMU5*/ + [37] = {0xFDA03434U, 0x00000002U}, /* SEC_MODID[37]:APMU6*/ + [38] = {0xFDA03438U, 0x00000002U}, /* SEC_MODID[38]:APMU7*/ + [39] = {0xFDA0343CU, 0x00000002U}, /* SEC_MODID[39]:APMU8*/ + [40] = {0xFDA03440U, 0x00000002U}, /* SEC_MODID[40]:APMU9*/ + [41] = {0xFDA03444U, 0x00000002U}, /* SEC_MODID[41]:ARS00*/ + [42] = {0xFDA03448U, 0x00000002U}, /* SEC_MODID[42]:ARS01*/ + [43] = {0xFDA0344CU, 0x00000002U}, /* SEC_MODID[43]:ARS02*/ + [44] = {0xFDA03450U, 0x00000002U}, /* SEC_MODID[44]:ARS03*/ + [45] = {0xFDA03454U, 0x00000002U}, /* SEC_MODID[45]:ARS04*/ + [46] = {0xFDA03458U, 0x00000002U}, /* SEC_MODID[46]:ARS05*/ + [47] = {0xFDA0345CU, 0x00000002U}, /* SEC_MODID[47]:ARS06*/ + [48] = {0xFDA03460U, 0x00000002U}, /* SEC_MODID[48]:ARS07*/ + [49] = {0xFDA03464U, 0x00000002U}, /* SEC_MODID[49]:ARS08*/ + [50] = {0xFDA03468U, 0x00000002U}, /* SEC_MODID[50]:CMT0*/ + [51] = {0xFDA0346CU, 0x00000002U}, /* SEC_MODID[51]:CMT1*/ + [52] = {0xFDA03470U, 0x00000002U}, /* SEC_MODID[52]:CMT2*/ + [53] = {0xFDA03474U, 0x00000002U}, /* SEC_MODID[53]:CMT3*/ + [54] = {0xFDA03478U, 0x00000002U}, /* SEC_MODID[54]:CKM*/ + [55] = {0xFDA0347CU, 0x00000002U}, /* SEC_MODID[55]:DBE*/ + [56] = {0xFDA03480U, 0x00000002U}, /* SEC_MODID[56]:IRQC*/ + [57] = {0xFDA03484U, 0x00000002U}, /* SEC_MODID[57]:ECMPS0*/ + [58] = {0xFDA03488U, 0x00000002U}, /* SEC_MODID[58]:OTP0*/ + [59] = {0xFDA0348CU, 0x00000002U}, /* SEC_MODID[59]:OTP1*/ + [60] = {0xFDA0349CU, 0x00000002U}, /* SEC_MODID[60]:SCMT*/ + [61] = {0xFDA034A8U, 0x00000002U}, /* SEC_MODID[61]:TSC1*/ + [62] = {0xFDA034ACU, 0x00000002U}, /* SEC_MODID[62]:TSC2*/ + [63] = {0xFDA034B0U, 0x00000002U}, /* SEC_MODID[63]:TSC3*/ + [64] = {0xFDA034B4U, 0x00000002U}, /* SEC_MODID[64]:TSC4*/ + [65] = {0xFDA034B8U, 0x00000002U}, /* SEC_MODID[65]:UCMT*/ + [66] = {0xFDA03500U, 0x00000002U}, /* SEC_MODID[66]:CPG0*/ + [67] = {0xFDA03504U, 0x00000002U}, /* SEC_MODID[67]:CPG1*/ + [68] = {0xFDA03508U, 0x00000002U}, /* SEC_MODID[68]:CPG2*/ + [69] = {0xFDA0350CU, 0x00000002U}, /* SEC_MODID[69]:CPG3*/ + [70] = {0xFDA03510U, 0x00000002U}, /* SEC_MODID[70]:PFC00*/ + [71] = {0xFDA03514U, 0x00000002U}, /* SEC_MODID[71]:PFC01*/ + [72] = {0xFDA03518U, 0x00000002U}, /* SEC_MODID[72]:PFC02*/ + [73] = {0xFDA0351CU, 0x00000002U}, /* SEC_MODID[73]:PFC03*/ + [74] = {0xFDA03520U, 0x00000002U}, /* SEC_MODID[74]:PFC10*/ + [75] = {0xFDA03524U, 0x00000002U}, /* SEC_MODID[75]:PFC11*/ + [76] = {0xFDA03528U, 0x00000002U}, /* SEC_MODID[76]:PFC12*/ + [77] = {0xFDA0352CU, 0x00000002U}, /* SEC_MODID[77]:PFC13*/ + [78] = {0xFDA03530U, 0x00000002U}, /* SEC_MODID[78]:PFC20*/ + [79] = {0xFDA03534U, 0x00000002U}, /* SEC_MODID[79]:PFC21*/ + [80] = {0xFDA03538U, 0x00000002U}, /* SEC_MODID[80]:PFC22*/ + [81] = {0xFDA0353CU, 0x00000002U}, /* SEC_MODID[81]:PFC23*/ + [82] = {0xFDA03540U, 0x00000002U}, /* SEC_MODID[82]:PFC30*/ + [83] = {0xFDA03544U, 0x00000002U}, /* SEC_MODID[83]:PFC31*/ + [84] = {0xFDA03548U, 0x00000002U}, /* SEC_MODID[84]:PFC32*/ + [85] = {0xFDA0354CU, 0x00000002U}, /* SEC_MODID[85]:PFC33*/ + [86] = {0xFDA03550U, 0x00000002U}, /* SEC_MODID[86]:PFCS0*/ + [87] = {0xFDA03554U, 0x00000002U}, /* SEC_MODID[87]:PFCS1*/ + [88] = {0xFDA03558U, 0x00000002U}, /* SEC_MODID[88]:PFCS2*/ + [89] = {0xFDA0355CU, 0x00000002U}, /* SEC_MODID[89]:PFCS3*/ + [90] = {0xFDA03560U, 0x00000002U}, /* SEC_MODID[90]:RESET0*/ + [91] = {0xFDA03564U, 0x00000002U}, /* SEC_MODID[91]:RESET1*/ + [92] = {0xFDA03568U, 0x00000002U}, /* SEC_MODID[92]:RESET2*/ + [93] = {0xFDA0356CU, 0x00000002U}, /* SEC_MODID[93]:RESET3*/ + [94] = {0xFDA03570U, 0x00000002U}, /* SEC_MODID[94]:SYS0*/ + [95] = {0xFDA03574U, 0x00000002U}, /* SEC_MODID[95]:SYS1*/ + [96] = {0xFDA03578U, 0x00000002U}, /* SEC_MODID[96]:SYS2*/ + [97] = {0xFDA0357CU, 0x00000002U}, /* SEC_MODID[97]:SYS3*/ + [98] = {0xFCB63400U, 0x00000002U}, /* SEC_MODID[98]:DMAMSI0*/ + [99] = {0xFCB63404U, 0x00000002U}, /* SEC_MODID[99]:DMAMSI1*/ + [100] = {0xFCB63408U, 0x00000002U}, /* SEC_MODID[100]:DMAMSI2*/ + [101] = {0xFCB6340CU, 0x00000002U}, /* SEC_MODID[101]:DMAMSI3*/ + [102] = {0xFCB63410U, 0x00000002U}, /* SEC_MODID[102]:DMAMSI4*/ + [103] = {0xFCB63414U, 0x00000002U}, /* SEC_MODID[103]:DMAMSI5*/ + [104] = {0xFCB63418U, 0x00000002U}, /* SEC_MODID[104]:ECMSP3*/ + [105] = {0xFCB63424U, 0x00000002U}, /* SEC_MODID[105]:ARSP30*/ + [106] = {0xFCB63428U, 0x00000002U}, /* SEC_MODID[106]:ARSP31*/ + [107] = {0xFCB6342CU, 0x00000002U}, /* SEC_MODID[107]:ARSP32*/ + [108] = {0xFCB63430U, 0x00000002U}, /* SEC_MODID[108]:ARSP33*/ + [109] = {0xFCB63434U, 0x00000002U}, /* SEC_MODID[109]:ARSP34*/ + [110] = {0xFCB63438U, 0x00000002U}, /* SEC_MODID[110]:ARSP35*/ + [111] = {0xFCB6343CU, 0x00000002U}, /* SEC_MODID[111]:ARSP36*/ + [112] = {0xFCB63440U, 0x00000002U}, /* SEC_MODID[112]:ARSP37*/ + [113] = {0xFCB63444U, 0x00000002U}, /* SEC_MODID[113]:ARSP38*/ + [114] = {0xFCB63448U, 0x00000002U}, /* SEC_MODID[114]:MSI0*/ + [115] = {0xFCB6344CU, 0x00000002U}, /* SEC_MODID[115]:MSI1*/ + [116] = {0xFCB63450U, 0x00000002U}, /* SEC_MODID[116]:MSI2*/ + [117] = {0xFCB63454U, 0x00000002U}, /* SEC_MODID[117]:MSI3*/ + [118] = {0xFCB63458U, 0x00000002U}, /* SEC_MODID[118]:MSI4*/ + [119] = {0xFCB6345CU, 0x00000002U}, /* SEC_MODID[119]:MSI5*/ + [120] = {0xFCB93400U, 0x00000002U}, /* SEC_MODID[120]:ARSP40*/ + [121] = {0xFCB93404U, 0x00000002U}, /* SEC_MODID[121]:ARSP41*/ + [122] = {0xFCB93408U, 0x00000002U}, /* SEC_MODID[122]:ARSP42*/ + [123] = {0xFCB9340CU, 0x00000002U}, /* SEC_MODID[123]:ARSP43*/ + [124] = {0xFCB93410U, 0x00000002U}, /* SEC_MODID[124]:ARSP44*/ + [125] = {0xFCB93414U, 0x00000002U}, /* SEC_MODID[125]:ARSP45*/ + [126] = {0xFCB93418U, 0x00000002U}, /* SEC_MODID[126]:ARSP46*/ + [127] = {0xFCB9341CU, 0x00000002U}, /* SEC_MODID[127]:ARSP47*/ + [128] = {0xFCB93420U, 0x00000002U}, /* SEC_MODID[128]:ARSP48*/ + [129] = {0xFCB93424U, 0x00000002U}, /* SEC_MODID[129]:DMAHSCIF0*/ + [130] = {0xFCB93428U, 0x00000002U}, /* SEC_MODID[130]:DMAHSCIF1*/ + [131] = {0xFCB9342CU, 0x00000002U}, /* SEC_MODID[131]:DMAHSCIF2*/ + [132] = {0xFCB93430U, 0x00000002U}, /* SEC_MODID[132]:DMAHSCIF3*/ + [133] = {0xFCB93434U, 0x00000002U}, /* SEC_MODID[133]:DMASCIF0*/ + [134] = {0xFCB93438U, 0x00000002U}, /* SEC_MODID[134]:DMASCIF1*/ + [135] = {0xFCB9343CU, 0x00000002U}, /* SEC_MODID[135]:DMASCIF3*/ + [136] = {0xFCB93440U, 0x00000002U}, /* SEC_MODID[136]:DMASCIF4*/ + [137] = {0xFCB93444U, 0x00000002U}, /* SEC_MODID[137]:ECMSP4*/ + [138] = {0xFCB93448U, 0x00000002U}, /* SEC_MODID[138]:HSCIF0*/ + [139] = {0xFCB9344CU, 0x00000002U}, /* SEC_MODID[139]:HSCIF1*/ + [140] = {0xFCB93450U, 0x00000002U}, /* SEC_MODID[140]:HSCIF2*/ + [141] = {0xFCB93454U, 0x00000002U}, /* SEC_MODID[141]:HSCIF3*/ + [142] = {0xFCB93458U, 0x00000002U}, /* SEC_MODID[142]:SCIF0*/ + [143] = {0xFCB9345CU, 0x00000002U}, /* SEC_MODID[143]:SCIF1*/ + [144] = {0xFCB93460U, 0x00000002U}, /* SEC_MODID[144]:SCIF3*/ + [145] = {0xFCB93464U, 0x00000002U}, /* SEC_MODID[145]:SCIF4*/ + [146] = {0xFCB93468U, 0x00000002U}, /* SEC_MODID[146]:TMU1*/ + [147] = {0xFCB9346CU, 0x00000002U}, /* SEC_MODID[147]:TMU2*/ + [148] = {0xFCB93470U, 0x00000002U}, /* SEC_MODID[148]:TMU3*/ + [149] = {0xFCB93474U, 0x00000002U}, /* SEC_MODID[149]:TMU4*/ + [150] = {0xFCB93478U, 0x00000002U}, /* SEC_MODID[150]:CANFD*/ + [151] = {0xFCB9347CU, 0x00000002U}, /* SEC_MODID[151]:DMACANFD*/ + [152] = {0xFCB93480U, 0x00000002U}, /* SEC_MODID[152]:DMATPU0*/ + [153] = {0xFCB93484U, 0x00000002U}, /* SEC_MODID[153]:PWM0*/ + [154] = {0xFCB93488U, 0x00000002U}, /* SEC_MODID[154]:PWM1*/ + [155] = {0xFCB9348CU, 0x00000002U}, /* SEC_MODID[155]:PWM2*/ + [156] = {0xFCB93490U, 0x00000002U}, /* SEC_MODID[156]:PWM3*/ + [157] = {0xFCB93494U, 0x00000002U}, /* SEC_MODID[157]:PWM4*/ + [158] = {0xFCB93498U, 0x00000002U}, /* SEC_MODID[158]:PWM5*/ + [159] = {0xFCB9349CU, 0x00000002U}, /* SEC_MODID[159]:PWM6*/ + [160] = {0xFCB934A0U, 0x00000002U}, /* SEC_MODID[160]:PWM7*/ + [161] = {0xFCB934A4U, 0x00000002U}, /* SEC_MODID[161]:PWM8*/ + [162] = {0xFCB934A8U, 0x00000002U}, /* SEC_MODID[162]:PWM9*/ + [163] = {0xFCB934ACU, 0x00000002U}, /* SEC_MODID[163]:TPU0*/ + [164] = {0xFC673400U, 0x00000002U}, /* SEC_MODID[164]:ARVC10*/ + [165] = {0xFC673404U, 0x00000002U}, /* SEC_MODID[165]:ARVC11*/ + [166] = {0xFC673408U, 0x00000002U}, /* SEC_MODID[166]:ARVC12*/ + [167] = {0xFC67340CU, 0x00000002U}, /* SEC_MODID[167]:ARVC13*/ + [168] = {0xFC673410U, 0x00000002U}, /* SEC_MODID[168]:ARVC14*/ + [169] = {0xFC673414U, 0x00000002U}, /* SEC_MODID[169]:ARVC15*/ + [170] = {0xFC673418U, 0x00000002U}, /* SEC_MODID[170]:ARVC16*/ + [171] = {0xFC67341CU, 0x00000002U}, /* SEC_MODID[171]:ARVC17*/ + [172] = {0xFC673420U, 0x00000002U}, /* SEC_MODID[172]:ARVC18*/ + [173] = {0xFC673424U, 0x00000002U}, /* SEC_MODID[173]:ECMVC1*/ + [174] = {0xFC673428U, 0x00000002U}, /* SEC_MODID[174]:FCPCS*/ + [175] = {0xFC67342CU, 0x00000002U}, /* SEC_MODID[175]:VCP4LC*/ + [176] = {0xFC673430U, 0x00000002U}, /* SEC_MODID[176]:VCP4LV*/ + [177] = {0xFEBD3400U, 0x00000002U}, /* SEC_MODID[177]:ARVI40*/ + [178] = {0xFEBD3404U, 0x00000002U}, /* SEC_MODID[178]:ARVI41*/ + [179] = {0xFEBD3408U, 0x00000002U}, /* SEC_MODID[179]:ARVI42*/ + [180] = {0xFEBD340CU, 0x00000002U}, /* SEC_MODID[180]:ARVI43*/ + [181] = {0xFEBD3410U, 0x00000002U}, /* SEC_MODID[181]:ARVI44*/ + [182] = {0xFEBD3414U, 0x00000002U}, /* SEC_MODID[182]:ARVI45*/ + [183] = {0xFEBD3418U, 0x00000002U}, /* SEC_MODID[183]:ARVI46*/ + [184] = {0xFEBD341CU, 0x00000002U}, /* SEC_MODID[184]:ARVI47*/ + [185] = {0xFEBD3420U, 0x00000002U}, /* SEC_MODID[185]:ARVI48*/ + [186] = {0xFEBD3424U, 0x00000002U}, /* SEC_MODID[186]:DIS0*/ + [187] = {0xFEBD342CU, 0x00000002U}, /* SEC_MODID[187]:DSC*/ + [188] = {0xFEBD3430U, 0x00000002U}, /* SEC_MODID[188]:ECMVIO2*/ + [189] = {0xFEBD3434U, 0x00000002U}, /* SEC_MODID[189]:FCPVD0*/ + [190] = {0xFEBD3438U, 0x00000002U}, /* SEC_MODID[190]:FCPVD1*/ + [191] = {0xFEBD343CU, 0x00000002U}, /* SEC_MODID[191]:VSPD0*/ + [192] = {0xFEBD3440U, 0x00000002U}, /* SEC_MODID[192]:VSPD1*/ + [193] = {0xFCF83400U, 0x00000002U}, /* SEC_MODID[193]:CKMHSC*/ + [194] = {0xFCF83404U, 0x00000002U}, /* SEC_MODID[194]:AXIPCI001*/ + [195] = {0xFCF83408U, 0x00000002U}, /* SEC_MODID[195]:AXIPCI002*/ + [196] = {0xFCF8340CU, 0x00000002U}, /* SEC_MODID[196]:AXIPCI003*/ + [197] = {0xFCF83414U, 0x00000002U}, /* SEC_MODID[197]:AXIPCI005*/ + [198] = {0xFCF83418U, 0x00000002U}, /* SEC_MODID[198]:AXIPCI006*/ + [199] = {0xFCF8341CU, 0x00000002U}, /* SEC_MODID[199]:AXIPCI007*/ + [200] = {0xFCF83420U, 0x00000002U}, /* SEC_MODID[200]:AXIPCI008*/ + [201] = {0xFCF83424U, 0x00000002U}, /* SEC_MODID[201]:AXIPCI009*/ + [202] = {0xFCF83428U, 0x00000002U}, /* SEC_MODID[202]:AXIPCI010*/ + [203] = {0xFCF8342CU, 0x00000002U}, /* SEC_MODID[203]:AXIPCI011*/ + [204] = {0xFCF83430U, 0x00000002U}, /* SEC_MODID[204]:AXIPCI012*/ + [205] = {0xFCF83434U, 0x00000002U}, /* SEC_MODID[205]:AXIPCI013*/ + [206] = {0xFCF83438U, 0x00000002U}, /* SEC_MODID[206]:AXIPCI014*/ + [207] = {0xFCF8343CU, 0x00000002U}, /* SEC_MODID[207]:AXIPCI015*/ + [208] = {0xFCF83440U, 0x00000002U}, /* SEC_MODID[208]:AXIPCI100*/ + [209] = {0xFCF83444U, 0x00000002U}, /* SEC_MODID[209]:AXIPCI101*/ + [210] = {0xFCF83448U, 0x00000002U}, /* SEC_MODID[210]:AXIPCI102*/ + [211] = {0xFCF8344CU, 0x00000002U}, /* SEC_MODID[211]:AXIPCI103*/ + [212] = {0xFCF83450U, 0x00000002U}, /* SEC_MODID[212]:AXIPCI104*/ + [213] = {0xFCF83454U, 0x00000002U}, /* SEC_MODID[213]:AXIPCI105*/ + [214] = {0xFCF83458U, 0x00000002U}, /* SEC_MODID[214]:AXIPCI106*/ + [215] = {0xFCF8345CU, 0x00000002U}, /* SEC_MODID[215]:AXIPCI107*/ + [216] = {0xFCF83460U, 0x00000002U}, /* SEC_MODID[216]:AXIPCI108*/ + [217] = {0xFCF83464U, 0x00000002U}, /* SEC_MODID[217]:AXIPCI109*/ + [218] = {0xFCF83468U, 0x00000002U}, /* SEC_MODID[218]:AXIPCI110*/ + [219] = {0xFCF8346CU, 0x00000002U}, /* SEC_MODID[219]:AXIPCI111*/ + [220] = {0xFCF83470U, 0x00000002U}, /* SEC_MODID[220]:AXIPCI112*/ + [221] = {0xFCF83474U, 0x00000002U}, /* SEC_MODID[221]:AXIPCI113*/ + [222] = {0xFCF83478U, 0x00000002U}, /* SEC_MODID[222]:AXIPCI114*/ + [223] = {0xFCF8347CU, 0x00000002U}, /* SEC_MODID[223]:AXIPCI115*/ + [224] = {0xFCF83484U, 0x00000002U}, /* SEC_MODID[224]:GPTP*/ + [225] = {0xFCF83488U, 0x00000002U}, /* SEC_MODID[225]:IPMMUHC00*/ + [226] = {0xFCF834F0U, 0x00000002U}, /* SEC_MODID[226]:TSN0*/ + [227] = {0xFCF834F4U, 0x00000002U}, /* SEC_MODID[227]:AXIPCI000*/ + [228] = {0xFCF834F8U, 0x00000002U}, /* SEC_MODID[228]:AXIPCI004*/ + [229] = {0xFCF834FCU, 0x00000002U}, /* SEC_MODID[229]:IPMMUHC01*/ + [230] = {0xFCF83500U, 0x00000002U}, /* SEC_MODID[230]:AVB0*/ + [231] = {0xFCF83504U, 0x00000002U}, /* SEC_MODID[231]:AVB1*/ + [232] = {0xFCF83508U, 0x00000002U}, /* SEC_MODID[232]:AVB2*/ + [233] = {0xFCF8350CU, 0x00000002U}, /* SEC_MODID[233]:IPMMUHC10*/ + [234] = {0xFCF83510U, 0x00000002U}, /* SEC_MODID[234]:IPMMUHC11*/ + [235] = {0xFCF83514U, 0x00000002U}, /* SEC_MODID[235]:IPMMUHC12*/ + [236] = {0xFCF83518U, 0x00000002U}, /* SEC_MODID[236]:IPMMUHC13*/ + [237] = {0xFCF8351CU, 0x00000002U}, /* SEC_MODID[237]:PPHY0*/ + [238] = {0xFCF83520U, 0x00000002U}, /* SEC_MODID[238]:PPHY1*/ + [239] = {0xFCF83524U, 0x00000002U}, /* SEC_MODID[239]:IPMMUHC14*/ + [240] = {0xFCF83528U, 0x00000002U}, /* SEC_MODID[240]:IPMMUHC15*/ + [241] = {0xFCF8352CU, 0x00000002U}, /* SEC_MODID[241]:FBAHSC*/ + [242] = {0xFCF83530U, 0x00000002U}, /* SEC_MODID[242]:IPMMUHC02*/ + [243] = {0xFCF83538U, 0x00000002U}, /* SEC_MODID[243]:ECMHSC*/ + [244] = {0xFCF8353CU, 0x00000002U}, /* SEC_MODID[244]:ARHC0*/ + [245] = {0xFCF83540U, 0x00000002U}, /* SEC_MODID[245]:ARHC1*/ + [246] = {0xFCF83544U, 0x00000002U}, /* SEC_MODID[246]:ARHC2*/ + [247] = {0xFCF83548U, 0x00000002U}, /* SEC_MODID[247]:ARHC3*/ + [248] = {0xFCF8354CU, 0x00000002U}, /* SEC_MODID[248]:ARHC4*/ + [249] = {0xFCF83550U, 0x00000002U}, /* SEC_MODID[249]:ARHC5*/ + [250] = {0xFCF83554U, 0x00000002U}, /* SEC_MODID[250]:ARHC6*/ + [251] = {0xFCF83558U, 0x00000002U}, /* SEC_MODID[251]:ARHC7*/ + [252] = {0xFCF8355CU, 0x00000002U}, /* SEC_MODID[252]:ARHC8*/ + [253] = {0xFCF83560U, 0x00000002U}, /* SEC_MODID[253]:IPMMUHC03*/ + [254] = {0xFCF83564U, 0x00000002U}, /* SEC_MODID[254]:IPMMUHC04*/ + [255] = {0xFCF83568U, 0x00000002U}, /* SEC_MODID[255]:IPMMUHC05*/ + [256] = {0xFCF8356CU, 0x00000002U}, /* SEC_MODID[256]:IPMMUHC06*/ + [257] = {0xFCF83570U, 0x00000002U}, /* SEC_MODID[257]:IPMMUHC07*/ + [258] = {0xFCF83574U, 0x00000002U}, /* SEC_MODID[258]:IPMMUHC08*/ + [259] = {0xFCF83578U, 0x00000002U}, /* SEC_MODID[259]:IPMMUHC09*/ + [260] = {0xFC883400U, 0x00000002U}, /* SEC_MODID[260]:ARIMP00*/ + [261] = {0xFC883404U, 0x00000002U}, /* SEC_MODID[261]:ARIMP01*/ + [262] = {0xFC883408U, 0x00000002U}, /* SEC_MODID[262]:ARIMP02*/ + [263] = {0xFC88340CU, 0x00000002U}, /* SEC_MODID[263]:ARIMP03*/ + [264] = {0xFC883410U, 0x00000002U}, /* SEC_MODID[264]:ARIMP04*/ + [265] = {0xFC883414U, 0x00000002U}, /* SEC_MODID[265]:AXIFBABUSIR0*/ + [266] = {0xFC883418U, 0x00000002U}, /* SEC_MODID[266]:AXIFBABUSIR1*/ + [267] = {0xFC88341CU, 0x00000002U}, /* SEC_MODID[267]:AXIFBABUSIR2*/ + [268] = {0xFC883420U, 0x00000002U}, /* SEC_MODID[268]:AXIFBABUSIR3*/ + [269] = {0xFC883424U, 0x00000002U}, /* SEC_MODID[269]:AXIFBABUSIR4*/ + [270] = {0xFC883428U, 0x00000002U}, /* SEC_MODID[270]:AXIIMP0*/ + [271] = {0xFC88342CU, 0x00000002U}, /* SEC_MODID[271]:CKMCNR*/ + [272] = {0xFC883430U, 0x00000002U}, /* SEC_MODID[272]:CKMDSP*/ + [273] = {0xFC883434U, 0x00000002U}, /* SEC_MODID[273]:ARIMP05*/ + [274] = {0xFC883438U, 0x00000002U}, /* SEC_MODID[274]:ARIMP06*/ + [275] = {0xFC88343CU, 0x00000002U}, /* SEC_MODID[275]:ARIMP07*/ + [276] = {0xFC883440U, 0x00000002U}, /* SEC_MODID[276]:ARIMP08*/ + [277] = {0xFC883444U, 0x00000002U}, /* SEC_MODID[277]:CKMIR*/ + [278] = {0xFC883448U, 0x00000002U}, /* SEC_MODID[278]:ECMIR*/ + [279] = {0xFC88344CU, 0x00000002U}, /* SEC_MODID[279]:DSPPS*/ + [280] = {0xFC883450U, 0x00000002U}, /* SEC_MODID[280]:IPMMUIR1*/ + [281] = {0xFC883454U, 0x00000002U}, /* SEC_MODID[281]:IPMMUIR0*/ + [282] = {0xFC883458U, 0x00000002U}, /* SEC_MODID[282]:IPMMUIR10*/ + [283] = {0xFC88345CU, 0x00000002U}, /* SEC_MODID[283]:IPMMUIR11*/ + [284] = {0xFC883460U, 0x00000002U}, /* SEC_MODID[284]:IPMMUIR12*/ + [285] = {0xFC883464U, 0x00000002U}, /* SEC_MODID[285]:IPMMUIR13*/ + [286] = {0xFC883468U, 0x00000002U}, /* SEC_MODID[286]:IPMMUIR14*/ + [287] = {0xFC88346CU, 0x00000002U}, /* SEC_MODID[287]:IPMMUIR15*/ + [288] = {0xFC883470U, 0x00000002U}, /* SEC_MODID[288]:IPMMUIR2*/ + [289] = {0xFC883474U, 0x00000002U}, /* SEC_MODID[289]:IPMMUIR3*/ + [290] = {0xFC883478U, 0x00000002U}, /* SEC_MODID[290]:IPMMUIR4*/ + [291] = {0xFC88347CU, 0x00000002U}, /* SEC_MODID[291]:IPMMUIR5*/ + [292] = {0xFC883480U, 0x00000002U}, /* SEC_MODID[292]:IPMMUIR6*/ + [293] = {0xFC883484U, 0x00000002U}, /* SEC_MODID[293]:IPMMUIR7*/ + [294] = {0xFC883488U, 0x00000002U}, /* SEC_MODID[294]:IPMMUIR8*/ + [295] = {0xFC88348CU, 0x00000002U}, /* SEC_MODID[295]:IPMMUIR9*/ + [296] = {0xFC013400U, 0x00000002U}, /* SEC_MODID[296]:ARPV0*/ + [297] = {0xFC013404U, 0x00000002U}, /* SEC_MODID[297]:ARPV1*/ + [298] = {0xFC013408U, 0x00000002U}, /* SEC_MODID[298]:AXIRGXS*/ + [299] = {0xFC01340CU, 0x00000002U}, /* SEC_MODID[299]:ARPV2*/ + [300] = {0xFC013410U, 0x00000002U}, /* SEC_MODID[300]:ARPV3*/ + [301] = {0xFC013414U, 0x00000002U}, /* SEC_MODID[301]:ARPV4*/ + [302] = {0xFC013418U, 0x00000002U}, /* SEC_MODID[302]:ARPV5*/ + [303] = {0xFC01341CU, 0x00000002U}, /* SEC_MODID[303]:ARPV6*/ + [304] = {0xFC013420U, 0x00000002U}, /* SEC_MODID[304]:ARPV7*/ + [305] = {0xFC013424U, 0x00000002U}, /* SEC_MODID[305]:ARPV8*/ + [306] = {0xFC013428U, 0x00000002U}, /* SEC_MODID[306]:CKM3DG*/ + [307] = {0xFC01342CU, 0x00000002U}, /* SEC_MODID[307]:ECM3DG*/ + [308] = {0xFC013430U, 0x00000002U}, /* SEC_MODID[308]:FBAPVC*/ + [309] = {0xFC013434U, 0x00000002U}, /* SEC_MODID[309]:FBAPVD0*/ + [310] = {0xFC013438U, 0x00000002U}, /* SEC_MODID[310]:FBAPVD1*/ + [311] = {0xFC01343CU, 0x00000002U}, /* SEC_MODID[311]:FBAPVD2*/ + [312] = {0xFC013440U, 0x00000002U}, /* SEC_MODID[312]:FBAPVE*/ + [313] = {0xFC013444U, 0x00000002U}, /* SEC_MODID[313]:IPMMUPV000*/ + [314] = {0xFC013448U, 0x00000002U}, /* SEC_MODID[314]:IPMMUPV001*/ + [315] = {0xFC01344CU, 0x00000002U}, /* SEC_MODID[315]:IPMMUPV010*/ + [316] = {0xFC013450U, 0x00000002U}, /* SEC_MODID[316]:IPMMUPV011*/ + [317] = {0xFC013454U, 0x00000002U}, /* SEC_MODID[317]:IPMMUPV012*/ + [318] = {0xFC013458U, 0x00000002U}, /* SEC_MODID[318]:IPMMUPV013*/ + [319] = {0xFC01345CU, 0x00000002U}, /* SEC_MODID[319]:IPMMUPV014*/ + [320] = {0xFC013460U, 0x00000002U}, /* SEC_MODID[320]:IPMMUPV015*/ + [321] = {0xFC013464U, 0x00000002U}, /* SEC_MODID[321]:IPMMUPV002*/ + [322] = {0xFC013468U, 0x00000002U}, /* SEC_MODID[322]:IPMMUPV003*/ + [323] = {0xFC01346CU, 0x00000002U}, /* SEC_MODID[323]:IPMMUPV004*/ + [324] = {0xFC013470U, 0x00000002U}, /* SEC_MODID[324]:IPMMUPV005*/ + [325] = {0xFC013474U, 0x00000002U}, /* SEC_MODID[325]:IPMMUPV006*/ + [326] = {0xFC013478U, 0x00000002U}, /* SEC_MODID[326]:IPMMUPV007*/ + [327] = {0xFC01347CU, 0x00000002U}, /* SEC_MODID[327]:IPMMUPV008*/ + [328] = {0xFC013480U, 0x00000002U}, /* SEC_MODID[328]:IPMMUPV009*/ + [329] = {0xFDC23400U, 0x00000002U}, /* SEC_MODID[329]:ARRC0*/ + [330] = {0xFDC23404U, 0x00000002U}, /* SEC_MODID[330]:ARRC1*/ + [331] = {0xFDC23408U, 0x00000002U}, /* SEC_MODID[331]:ARRC2*/ + [332] = {0xFDC2340CU, 0x00000002U}, /* SEC_MODID[332]:ARRC3*/ + [333] = {0xFDC23410U, 0x00000002U}, /* SEC_MODID[333]:ARRC4*/ + [334] = {0xFDC23414U, 0x00000002U}, /* SEC_MODID[334]:ARRC5*/ + [335] = {0xFDC23418U, 0x00000002U}, /* SEC_MODID[335]:ARRC6*/ + [336] = {0xFDC2341CU, 0x00000002U}, /* SEC_MODID[336]:ARRC7*/ + [337] = {0xFDC23420U, 0x00000002U}, /* SEC_MODID[337]:ARRC8*/ + [338] = {0xFDC23424U, 0x00000000U}, /* SEC_MODID[338]:CR0*/ + [339] = {0xFDC23428U, 0x00000002U}, /* SEC_MODID[339]:ICUMX*/ + [340] = {0xFDC2342CU, 0x00000002U}, /* SEC_MODID[340]:ECMRC*/ + [341] = {0xFD433400U, 0x00000002U}, /* SEC_MODID[341]:DMAWCRC0*/ + [342] = {0xFD433404U, 0x00000002U}, /* SEC_MODID[342]:DMAWCRC1*/ + [343] = {0xFD433408U, 0x00000002U}, /* SEC_MODID[343]:DMAWCRC2*/ + [344] = {0xFD43340CU, 0x00000002U}, /* SEC_MODID[344]:DMAWCRC3*/ + [345] = {0xFD443400U, 0x00000002U}, /* SEC_MODID[345]:ARMREG00*/ + [346] = {0xFD443404U, 0x00000002U}, /* SEC_MODID[346]:ARMREG01*/ + [347] = {0xFD443408U, 0x00000002U}, /* SEC_MODID[347]:ARMREG10*/ + [348] = {0xFD44340CU, 0x00000002U}, /* SEC_MODID[348]:ARMREG11*/ + [349] = {0xFD443410U, 0x00000002U}, /* SEC_MODID[349]:ARMREG12*/ + [350] = {0xFD443414U, 0x00000000U}, /* SEC_MODID[350]:ARMREG13*/ + [351] = {0xFD443418U, 0x00000000U}, /* SEC_MODID[351]:ARMREG14*/ + [352] = {0xFD44341CU, 0x00000002U}, /* SEC_MODID[352]:AXICR52SS0*/ + [353] = {0xFD443420U, 0x00000002U}, /* SEC_MODID[353]:AXICSD0*/ + [354] = {0xFD443424U, 0x00000002U}, /* SEC_MODID[354]:AXIINTAP0*/ + [355] = {0xFD443428U, 0x00000002U}, /* SEC_MODID[355]:AXIINTAP1*/ + [356] = {0xFD44342CU, 0x00000002U}, /* SEC_MODID[356]:AXISECROM*/ + [357] = {0xFD443430U, 0x00000002U}, /* SEC_MODID[357]:AXISYSRAM0*/ + [358] = {0xFD443434U, 0x00000002U}, /* SEC_MODID[358]:AXISYSRAM1*/ + [359] = {0xFD443438U, 0x00000002U}, /* SEC_MODID[359]:ARGREG15*/ + [360] = {0xFD44343CU, 0x00000002U}, /* SEC_MODID[360]:ARMREG2*/ + [361] = {0xFD443440U, 0x00000002U}, /* SEC_MODID[361]:ARMREG3*/ + [362] = {0xFD443444U, 0x00000002U}, /* SEC_MODID[362]:ARMREG4*/ + [363] = {0xFD443448U, 0x00000002U}, /* SEC_MODID[363]:ARMREG5*/ + [364] = {0xFD44344CU, 0x00000002U}, /* SEC_MODID[364]:ARMREG6*/ + [365] = {0xFD443450U, 0x00000002U}, /* SEC_MODID[365]:ARMREG7*/ + [366] = {0xFD443454U, 0x00000000U}, /* SEC_MODID[366]:ARMREG8*/ + [367] = {0xFD443458U, 0x00000000U}, /* SEC_MODID[367]:ARMREG9*/ + [368] = {0xFD44345CU, 0x00000002U}, /* SEC_MODID[368]:ARRD0*/ + [369] = {0xFD443460U, 0x00000002U}, /* SEC_MODID[369]:ARRD1*/ + [370] = {0xFD443464U, 0x00000002U}, /* SEC_MODID[370]:ARRD2*/ + [371] = {0xFD443468U, 0x00000002U}, /* SEC_MODID[371]:ARRD3*/ + [372] = {0xFD44346CU, 0x00000002U}, /* SEC_MODID[372]:ARRD4*/ + [373] = {0xFD443470U, 0x00000002U}, /* SEC_MODID[373]:ARRD5*/ + [374] = {0xFD443474U, 0x00000002U}, /* SEC_MODID[374]:ARRD6*/ + [375] = {0xFD443478U, 0x00000002U}, /* SEC_MODID[375]:ARRD7*/ + [376] = {0xFD44347CU, 0x00000002U}, /* SEC_MODID[376]:ARRD8*/ + [377] = {0xFD443480U, 0x00000002U}, /* SEC_MODID[377]:ARRT0*/ + [378] = {0xFD443484U, 0x00000002U}, /* SEC_MODID[378]:ARRT1*/ + [379] = {0xFD443488U, 0x00000002U}, /* SEC_MODID[379]:ARRT2*/ + [380] = {0xFD44348CU, 0x00000002U}, /* SEC_MODID[380]:ARRT3*/ + [381] = {0xFD443490U, 0x00000002U}, /* SEC_MODID[381]:ARRT4*/ + [382] = {0xFD443494U, 0x00000002U}, /* SEC_MODID[382]:ARRT5*/ + [383] = {0xFD443498U, 0x00000002U}, /* SEC_MODID[383]:ARRT6*/ + [384] = {0xFD44349CU, 0x00000002U}, /* SEC_MODID[384]:ARRT7*/ + [385] = {0xFD4434A0U, 0x00000002U}, /* SEC_MODID[385]:ARRT8*/ + [386] = {0xFD4434A4U, 0x00000002U}, /* SEC_MODID[386]:CKMRT*/ + [387] = {0xFD4434A8U, 0x00000002U}, /* SEC_MODID[387]:CRC0*/ + [388] = {0xFD4434ACU, 0x00000002U}, /* SEC_MODID[388]:CRC1*/ + [389] = {0xFD4434B0U, 0x00000002U}, /* SEC_MODID[389]:CRC2*/ + [390] = {0xFD4434B4U, 0x00000002U}, /* SEC_MODID[390]:CRC3*/ + [391] = {0xFD4434B8U, 0x00000002U}, /* SEC_MODID[391]:CSD*/ + [392] = {0xFD4434BCU, 0x00000002U}, /* SEC_MODID[392]:ECM*/ + [393] = {0xFD4434C0U, 0x00000002U}, /* SEC_MODID[393]:ECMRT*/ + [394] = {0xFD4434C4U, 0x00000002U}, /* SEC_MODID[394]:FBACR52*/ + [395] = {0xFD4434C8U, 0x00000002U}, /* SEC_MODID[395]:FBART*/ + [396] = {0xFD4434CCU, 0x00000002U}, /* SEC_MODID[396]:INTTP*/ + [397] = {0xFD4434D0U, 0x00000002U}, /* SEC_MODID[397]:IPMMURT000*/ + [398] = {0xFD4434D4U, 0x00000002U}, /* SEC_MODID[398]:IPMMURT100*/ + [399] = {0xFD4434D8U, 0x00000002U}, /* SEC_MODID[399]:KCRC4*/ + [400] = {0xFD4434DCU, 0x00000002U}, /* SEC_MODID[400]:KCRC5*/ + [401] = {0xFD4434E0U, 0x00000002U}, /* SEC_MODID[401]:KCRC6*/ + [402] = {0xFD4434E4U, 0x00000002U}, /* SEC_MODID[402]:KCRC7*/ + [403] = {0xFD4434E8U, 0x00000002U}, /* SEC_MODID[403]:MFI00*/ + [404] = {0xFD4434ECU, 0x00000002U}, /* SEC_MODID[404]:MFI01*/ + [405] = {0xFD4434F0U, 0x00000002U}, /* SEC_MODID[405]:MFI10*/ + [406] = {0xFD4434F4U, 0x00000002U}, /* SEC_MODID[406]:MFI02*/ + [407] = {0xFD4434F8U, 0x00000002U}, /* SEC_MODID[407]:MFI03*/ + [408] = {0xFD4434FCU, 0x00000002U}, /* SEC_MODID[408]:MFI04*/ + [409] = {0xFD443500U, 0x00000002U}, /* SEC_MODID[409]:MFI05*/ + [410] = {0xFD443504U, 0x00000002U}, /* SEC_MODID[410]:MFI06*/ + [411] = {0xFD443508U, 0x00000002U}, /* SEC_MODID[411]:MFI07*/ + [412] = {0xFD44350CU, 0x00000002U}, /* SEC_MODID[412]:MFI08*/ + [413] = {0xFD443510U, 0x00000002U}, /* SEC_MODID[413]:MFI09*/ + [414] = {0xFD443514U, 0x00000002U}, /* SEC_MODID[414]:MFI15*/ + [415] = {0xFD443518U, 0x00000002U}, /* SEC_MODID[415]:CKMCR52*/ + [416] = {0xFD44351CU, 0x00000002U}, /* SEC_MODID[416]:RTDM0P*/ + [417] = {0xFD443520U, 0x00000002U}, /* SEC_MODID[417]:ECMRD*/ + [418] = {0xFD443524U, 0x00000002U}, /* SEC_MODID[418]:RTDM1P*/ + [419] = {0xFD44352CU, 0x00000002U}, /* SEC_MODID[419]:RTDM2P*/ + [420] = {0xFD443530U, 0x00000002U}, /* SEC_MODID[420]:SYSRAM10*/ + [421] = {0xFD443534U, 0x00000002U}, /* SEC_MODID[421]:RTDM3P*/ + [422] = {0xFD443538U, 0x00000000U}, /* SEC_MODID[422]:SYSRAM00*/ + [423] = {0xFD44353CU, 0x00000002U}, /* SEC_MODID[423]:TSIPL0*/ + [424] = {0xFD443540U, 0x00000002U}, /* SEC_MODID[424]:TSIPL1*/ + [425] = {0xFD443544U, 0x00000002U}, /* SEC_MODID[425]:TSIPL2*/ + [426] = {0xFD443548U, 0x00000002U}, /* SEC_MODID[426]:TSIPL3*/ + [427] = {0xFD44354CU, 0x00000002U}, /* SEC_MODID[427]:TSIPL4*/ + [428] = {0xFD443550U, 0x00000002U}, /* SEC_MODID[428]:TSIPL5*/ + [429] = {0xFD443554U, 0x00000002U}, /* SEC_MODID[429]:TSIPL6*/ + [430] = {0xFD443558U, 0x00000002U}, /* SEC_MODID[430]:TSIPL7*/ + [431] = {0xFD44355CU, 0x00000002U}, /* SEC_MODID[431]:WCRC0*/ + [432] = {0xFD443560U, 0x00000002U}, /* SEC_MODID[432]:WCRC1*/ + [433] = {0xFD443564U, 0x00000002U}, /* SEC_MODID[433]:WCRC2*/ + [434] = {0xFD443568U, 0x00000002U}, /* SEC_MODID[434]:WCRC3*/ + [435] = {0xFD443580U, 0x00000002U}, /* SEC_MODID[435]:MFI11*/ + [436] = {0xFD443584U, 0x00000002U}, /* SEC_MODID[436]:MFI12*/ + [437] = {0xFD443588U, 0x00000002U}, /* SEC_MODID[437]:MFI13*/ + [438] = {0xFD44358CU, 0x00000002U}, /* SEC_MODID[438]:MFI14*/ + [439] = {0xFD443590U, 0x00000002U}, /* SEC_MODID[439]:IPMMURT001*/ + [440] = {0xFD443594U, 0x00000002U}, /* SEC_MODID[440]:IPMMURT010*/ + [441] = {0xFD443598U, 0x00000002U}, /* SEC_MODID[441]:IPMMURT011*/ + [442] = {0xFD44359CU, 0x00000002U}, /* SEC_MODID[442]:IPMMURT012*/ + [443] = {0xFD4435A0U, 0x00000002U}, /* SEC_MODID[443]:IPMMURT013*/ + [444] = {0xFD4435A4U, 0x00000002U}, /* SEC_MODID[444]:IPMMURT014*/ + [445] = {0xFD4435A8U, 0x00000002U}, /* SEC_MODID[445]:IPMMURT015*/ + [446] = {0xFD4435ACU, 0x00000002U}, /* SEC_MODID[446]:IPMMURT002*/ + [447] = {0xFD4435B0U, 0x00000002U}, /* SEC_MODID[447]:IPMMURT003*/ + [448] = {0xFD4435B4U, 0x00000002U}, /* SEC_MODID[448]:IPMMURT004*/ + [449] = {0xFD4435B8U, 0x00000002U}, /* SEC_MODID[449]:IPMMURT005*/ + [450] = {0xFD4435BCU, 0x00000002U}, /* SEC_MODID[450]:IPMMURT006*/ + [451] = {0xFD4435C0U, 0x00000002U}, /* SEC_MODID[451]:IPMMURT007*/ + [452] = {0xFD4435C4U, 0x00000002U}, /* SEC_MODID[452]:IPMMURT008*/ + [453] = {0xFD4435C8U, 0x00000002U}, /* SEC_MODID[453]:IPMMURT009*/ + [454] = {0xFD4435CCU, 0x00000002U}, /* SEC_MODID[454]:IPKMURT101*/ + [455] = {0xFD4435D0U, 0x00000002U}, /* SEC_MODID[455]:IPMMURT110*/ + [456] = {0xFD4435D4U, 0x00000002U}, /* SEC_MODID[456]:IPMMURT111*/ + [457] = {0xFD4435D8U, 0x00000002U}, /* SEC_MODID[457]:IPMMURT112*/ + [458] = {0xFD4435DCU, 0x00000002U}, /* SEC_MODID[458]:IPMMURT113*/ + [459] = {0xFD4435E0U, 0x00000002U}, /* SEC_MODID[459]:IPMMURT114*/ + [460] = {0xFD4435E4U, 0x00000002U}, /* SEC_MODID[460]:IPMMURT115*/ + [461] = {0xFD4435E8U, 0x00000002U}, /* SEC_MODID[461]:IPMMURT102*/ + [462] = {0xFD4435ECU, 0x00000002U}, /* SEC_MODID[462]:IPMMURT103*/ + [463] = {0xFD4435F0U, 0x00000002U}, /* SEC_MODID[463]:IPMMURT104*/ + [464] = {0xFD4435F4U, 0x00000002U}, /* SEC_MODID[464]:IPMMURT105*/ + [465] = {0xFD4435F8U, 0x00000002U}, /* SEC_MODID[465]:IPMMURT106*/ + [466] = {0xFD4435FCU, 0x00000002U}, /* SEC_MODID[466]:IPMMURT107*/ + [467] = {0xFD443600U, 0x00000002U}, /* SEC_MODID[467]:RTDM000*/ + [468] = {0xFD443604U, 0x00000002U}, /* SEC_MODID[468]:RTDM001*/ + [469] = {0xFD443608U, 0x00000002U}, /* SEC_MODID[469]:RTDM010*/ + [470] = {0xFD44360CU, 0x00000002U}, /* SEC_MODID[470]:RTDM011*/ + [471] = {0xFD443610U, 0x00000002U}, /* SEC_MODID[471]:RTDM012*/ + [472] = {0xFD443614U, 0x00000002U}, /* SEC_MODID[472]:RTDM013*/ + [473] = {0xFD443618U, 0x00000002U}, /* SEC_MODID[473]:RTDM014*/ + [474] = {0xFD44361CU, 0x00000002U}, /* SEC_MODID[474]:RTDM015*/ + [475] = {0xFD443620U, 0x00000002U}, /* SEC_MODID[475]:RTDM002*/ + [476] = {0xFD443624U, 0x00000002U}, /* SEC_MODID[476]:RTDM003*/ + [477] = {0xFD443628U, 0x00000002U}, /* SEC_MODID[477]:RTDM004*/ + [478] = {0xFD44362CU, 0x00000002U}, /* SEC_MODID[478]:RTDM005*/ + [479] = {0xFD443630U, 0x00000002U}, /* SEC_MODID[479]:RTDM006*/ + [480] = {0xFD443634U, 0x00000002U}, /* SEC_MODID[480]:RTDM007*/ + [481] = {0xFD443638U, 0x00000002U}, /* SEC_MODID[481]:RTDM008*/ + [482] = {0xFD44363CU, 0x00000002U}, /* SEC_MODID[482]:RTDM009*/ + [483] = {0xFD443640U, 0x00000002U}, /* SEC_MODID[483]:RTDM100*/ + [484] = {0xFD443644U, 0x00000002U}, /* SEC_MODID[484]:RTDM101*/ + [485] = {0xFD443648U, 0x00000002U}, /* SEC_MODID[485]:RTDM110*/ + [486] = {0xFD44364CU, 0x00000002U}, /* SEC_MODID[486]:RTDM111*/ + [487] = {0xFD443650U, 0x00000002U}, /* SEC_MODID[487]:RTDM112*/ + [488] = {0xFD443654U, 0x00000002U}, /* SEC_MODID[488]:RTDM113*/ + [489] = {0xFD443658U, 0x00000002U}, /* SEC_MODID[489]:RTDM114*/ + [490] = {0xFD44365CU, 0x00000002U}, /* SEC_MODID[490]:RTDM115*/ + [491] = {0xFD443660U, 0x00000002U}, /* SEC_MODID[491]:RTDM102*/ + [492] = {0xFD443664U, 0x00000002U}, /* SEC_MODID[492]:RTDM103*/ + [493] = {0xFD443668U, 0x00000002U}, /* SEC_MODID[493]:RTDM104*/ + [494] = {0xFD44366CU, 0x00000002U}, /* SEC_MODID[494]:RTDM105*/ + [495] = {0xFD443670U, 0x00000002U}, /* SEC_MODID[495]:RTDM106*/ + [496] = {0xFD443674U, 0x00000002U}, /* SEC_MODID[496]:RTDM107*/ + [497] = {0xFD443678U, 0x00000002U}, /* SEC_MODID[497]:RTDM108*/ + [498] = {0xFD44367CU, 0x00000002U}, /* SEC_MODID[498]:RTDM109*/ + [499] = {0xFD443680U, 0x00000002U}, /* SEC_MODID[499]:RTDM200*/ + [500] = {0xFD443684U, 0x00000002U}, /* SEC_MODID[500]:RTDM201*/ + [501] = {0xFD443688U, 0x00000002U}, /* SEC_MODID[501]:RTDM210*/ + [502] = {0xFD44368CU, 0x00000002U}, /* SEC_MODID[502]:RTDM211*/ + [503] = {0xFD443690U, 0x00000002U}, /* SEC_MODID[503]:RTDM212*/ + [504] = {0xFD443694U, 0x00000002U}, /* SEC_MODID[504]:RTDM213*/ + [505] = {0xFD443698U, 0x00000002U}, /* SEC_MODID[505]:RTDM214*/ + [506] = {0xFD44369CU, 0x00000002U}, /* SEC_MODID[506]:RTDM215*/ + [507] = {0xFD4436A0U, 0x00000002U}, /* SEC_MODID[507]:RTDM202*/ + [508] = {0xFD4436A4U, 0x00000002U}, /* SEC_MODID[508]:RTDM203*/ + [509] = {0xFD4436A8U, 0x00000002U}, /* SEC_MODID[509]:RTDM204*/ + [510] = {0xFD4436ACU, 0x00000002U}, /* SEC_MODID[510]:RTDM205*/ + [511] = {0xFD4436B0U, 0x00000002U}, /* SEC_MODID[511]:RTDM206*/ + [512] = {0xFD4436B4U, 0x00000002U}, /* SEC_MODID[512]:RTDM207*/ + [513] = {0xFD4436B8U, 0x00000002U}, /* SEC_MODID[513]:RTDM208*/ + [514] = {0xFD4436BCU, 0x00000002U}, /* SEC_MODID[514]:RTDM209*/ + [515] = {0xFD4436C0U, 0x00000002U}, /* SEC_MODID[515]:RTDM300*/ + [516] = {0xFD4436C4U, 0x00000002U}, /* SEC_MODID[516]:RTDM301*/ + [517] = {0xFD4436C8U, 0x00000002U}, /* SEC_MODID[517]:RTDM310*/ + [518] = {0xFD4436CCU, 0x00000002U}, /* SEC_MODID[518]:RTDM311*/ + [519] = {0xFD4436D0U, 0x00000002U}, /* SEC_MODID[519]:RTDM312*/ + [520] = {0xFD4436D4U, 0x00000002U}, /* SEC_MODID[520]:RTDM313*/ + [521] = {0xFD4436D8U, 0x00000002U}, /* SEC_MODID[521]:RTDM314*/ + [522] = {0xFD4436DCU, 0x00000002U}, /* SEC_MODID[522]:RTDM315*/ + [523] = {0xFD4436E0U, 0x00000002U}, /* SEC_MODID[523]:RTDM302*/ + [524] = {0xFD4436E4U, 0x00000002U}, /* SEC_MODID[524]:RTDM303*/ + [525] = {0xFD4436E8U, 0x00000002U}, /* SEC_MODID[525]:RTDM304*/ + [526] = {0xFD4436ECU, 0x00000002U}, /* SEC_MODID[526]:RTDM305*/ + [527] = {0xFD4436F0U, 0x00000002U}, /* SEC_MODID[527]:RTDM306*/ + [528] = {0xFD4436F4U, 0x00000002U}, /* SEC_MODID[528]:RTDM307*/ + [529] = {0xFD4436F8U, 0x00000002U}, /* SEC_MODID[529]:RTDM308*/ + [530] = {0xFD4436FCU, 0x00000002U}, /* SEC_MODID[530]:RTDM309*/ + [531] = {0xFD443700U, 0x00000002U}, /* SEC_MODID[531]:IPMMURT108*/ + [532] = {0xFD443704U, 0x00000002U}, /* SEC_MODID[532]:IPMMURT109*/ + [533] = {0xFD443708U, 0x00000000U}, /* SEC_MODID[533]:SYSRAM01*/ + [534] = {0xFD44370CU, 0x00000002U}, /* SEC_MODID[534]:SYSRAM02*/ + [535] = {0xFD443710U, 0x00000000U}, /* SEC_MODID[535]:SYSRAM03*/ + [536] = {0xFD443714U, 0x00000000U}, /* SEC_MODID[536]:SYSRAM04*/ + [537] = {0xFD443718U, 0x00000000U}, /* SEC_MODID[537]:SYSRAM05*/ + [538] = {0xFD44371CU, 0x00000000U}, /* SEC_MODID[538]:SYSRAM06*/ + [539] = {0xFD443720U, 0x00000002U}, /* SEC_MODID[539]:SYSRAM07*/ + [540] = {0xFD443724U, 0x00000002U}, /* SEC_MODID[540]:SYSRAM11*/ + [541] = {0xFD443728U, 0x00000002U}, /* SEC_MODID[541]:SYSRAM12*/ + [542] = {0xFD44372CU, 0x00000002U}, /* SEC_MODID[542]:SYSRAM13*/ + [543] = {0xFD443730U, 0x00000002U}, /* SEC_MODID[543]:SYSRAM14*/ + [544] = {0xFD443734U, 0x00000002U}, /* SEC_MODID[544]:SYSRAM15*/ + [545] = {0xFD443738U, 0x00000002U}, /* SEC_MODID[545]:SYSRAM16*/ + [546] = {0xFD44373CU, 0x00000002U}, /* SEC_MODID[546]:SYSRAM17*/ + [547] = {0xFD443760U, 0x00000002U}, /* SEC_MODID[547]:BKBUF*/ + [548] = {0xFD443764U, 0x00000002U}, /* SEC_MODID[548]:AXICR52SS1*/ + [549] = {0xFD443768U, 0x00000002U}, /* SEC_MODID[549]:AXICR52SS2*/ + [550] = {0xFC863400U, 0x00000002U}, /* SEC_MODID[550]:ARSC0*/ + [551] = {0xFC863404U, 0x00000002U}, /* SEC_MODID[551]:ARSC1*/ + [552] = {0xFC863408U, 0x00000002U}, /* SEC_MODID[552]:ARSC2*/ + [553] = {0xFC86340CU, 0x00000002U}, /* SEC_MODID[553]:ARSC3*/ + [554] = {0xFC863410U, 0x00000002U}, /* SEC_MODID[554]:ARSC4*/ + [555] = {0xFC863414U, 0x00000002U}, /* SEC_MODID[555]:ARSC5*/ + [556] = {0xFC863418U, 0x00000002U}, /* SEC_MODID[556]:ARSC6*/ + [557] = {0xFC86341CU, 0x00000002U}, /* SEC_MODID[557]:ARSC7*/ + [558] = {0xFC863420U, 0x00000002U}, /* SEC_MODID[558]:ARSC8*/ + [559] = {0xFC863424U, 0x00000002U}, /* SEC_MODID[559]:ARSTM0*/ + [560] = {0xFC863428U, 0x00000002U}, /* SEC_MODID[560]:ARSTM1*/ + [561] = {0xFC86342CU, 0x00000002U}, /* SEC_MODID[561]:CSD1S*/ + [562] = {0xFC863430U, 0x00000002U}, /* SEC_MODID[562]:AXIFBABUSTOP0*/ + [563] = {0xFC863434U, 0x00000002U}, /* SEC_MODID[563]:AXIFBABUSTOP1*/ + [564] = {0xFC863438U, 0x00000002U}, /* SEC_MODID[564]:ARSTM2*/ + [565] = {0xFC86343CU, 0x00000002U}, /* SEC_MODID[565]:ARSTM3*/ + [566] = {0xFC863440U, 0x00000002U}, /* SEC_MODID[566]:ARSTM4*/ + [567] = {0xFC863444U, 0x00000002U}, /* SEC_MODID[567]:ARSTM5*/ + [568] = {0xFC863448U, 0x00000002U}, /* SEC_MODID[568]:ARSTM6*/ + [569] = {0xFC86344CU, 0x00000002U}, /* SEC_MODID[569]:ARSTM7*/ + [570] = {0xFC863450U, 0x00000002U}, /* SEC_MODID[570]:ARSTM8*/ + [571] = {0xFC863454U, 0x00000002U}, /* SEC_MODID[571]:ECMTOP*/ + [572] = {0xFC863458U, 0x00000002U}, /* SEC_MODID[572]:FBA*/ + [573] = {0xFC86345CU, 0x00000002U}, /* SEC_MODID[573]:FBC*/ + [574] = {0xFC863460U, 0x00000002U}, /* SEC_MODID[574]:AXICCI00*/ + [575] = {0xFC863464U, 0x00000002U}, /* SEC_MODID[575]:AXICCI01*/ + [576] = {0xFC863468U, 0x00000002U}, /* SEC_MODID[576]:AXICCI10*/ + [577] = {0xFC86346CU, 0x00000002U}, /* SEC_MODID[577]:AXICCI11*/ + [578] = {0xFC863470U, 0x00000002U}, /* SEC_MODID[578]:AXICCI12*/ + [579] = {0xFC863474U, 0x00000002U}, /* SEC_MODID[579]:AXICCI13*/ + [580] = {0xFC863478U, 0x00000002U}, /* SEC_MODID[580]:AXICCI14*/ + [581] = {0xFC86347CU, 0x00000002U}, /* SEC_MODID[581]:AXICCI15*/ + [582] = {0xFC863480U, 0x00000002U}, /* SEC_MODID[582]:AXICCI2*/ + [583] = {0xFC863484U, 0x00000002U}, /* SEC_MODID[583]:AXICCI3*/ + [584] = {0xFC863488U, 0x00000002U}, /* SEC_MODID[584]:AXICCI4*/ + [585] = {0xFC86348CU, 0x00000002U}, /* SEC_MODID[585]:AXICCI5*/ + [586] = {0xFC863490U, 0x00000002U}, /* SEC_MODID[586]:AXICCI6*/ + [587] = {0xFC863494U, 0x00000002U}, /* SEC_MODID[587]:AXICCI7*/ + [588] = {0xFC863498U, 0x00000002U}, /* SEC_MODID[588]:AXICCI8*/ + [589] = {0xFC86349CU, 0x00000002U}, /* SEC_MODID[589]:AXICCI9*/ + [590] = {0xFC8634A0U, 0x00000002U}, /* SEC_MODID[590]:ECMSTM*/ + [591] = {0xFCB83400U, 0x00000002U}, /* SEC_MODID[591]:DMASSI00*/ + [592] = {0xFCB83404U, 0x00000002U}, /* SEC_MODID[592]:DMASSI01*/ + [593] = {0xFCB83408U, 0x00000002U}, /* SEC_MODID[593]:DMASSI02*/ + [594] = {0xFCB8340CU, 0x00000002U}, /* SEC_MODID[594]:DMASSI03*/ + [595] = {0xFCB83410U, 0x00000002U}, /* SEC_MODID[595]:DMASSI04*/ + [596] = {0xFCB83414U, 0x00000002U}, /* SEC_MODID[596]:DMAI2C0*/ + [597] = {0xFCB83418U, 0x00000002U}, /* SEC_MODID[597]:DMAI2C1*/ + [598] = {0xFCB8341CU, 0x00000002U}, /* SEC_MODID[598]:DMAI2C2*/ + [599] = {0xFCB83420U, 0x00000002U}, /* SEC_MODID[599]:DMAI2C3*/ + [600] = {0xFCB83424U, 0x00000002U}, /* SEC_MODID[600]:DMAI2C4*/ + [601] = {0xFCB83428U, 0x00000002U}, /* SEC_MODID[601]:DMAI2C5*/ + [602] = {0xFCB8342CU, 0x00000002U}, /* SEC_MODID[602]:DMASSI05*/ + [603] = {0xFCB83430U, 0x00000002U}, /* SEC_MODID[603]:DMASSI06*/ + [604] = {0xFCB83434U, 0x00000002U}, /* SEC_MODID[604]:DMASSI07*/ + [605] = {0xFDDC3400U, 0x00000002U}, /* SEC_MODID[605]:ARMM*/ + [606] = {0xFDDC3404U, 0x00000002U}, /* SEC_MODID[606]:AXIARNMM*/ + [607] = {0xFDDC3408U, 0x00000002U}, /* SEC_MODID[607]:ARSM0*/ + [608] = {0xFDDC340CU, 0x00000002U}, /* SEC_MODID[608]:ARSM1*/ + [609] = {0xFDDC3410U, 0x00000002U}, /* SEC_MODID[609]:ARSM2*/ + [610] = {0xFDDC3414U, 0x00000002U}, /* SEC_MODID[610]:AXIQOS0*/ + [611] = {0xFDDC3418U, 0x00000002U}, /* SEC_MODID[611]:AXIQOS1*/ + [612] = {0xFDDC341CU, 0x00000002U}, /* SEC_MODID[612]:AXIQOS2*/ + [613] = {0xFDDC3420U, 0x00000002U}, /* SEC_MODID[613]:AXIQOS3*/ + [614] = {0xFDDC3424U, 0x00000002U}, /* SEC_MODID[614]:AXIQOS4*/ + [615] = {0xFDDC3428U, 0x00000002U}, /* SEC_MODID[615]:AXIQOS5*/ + [616] = {0xFDDC342CU, 0x00000002U}, /* SEC_MODID[616]:AXIQOS6*/ + [617] = {0xFDDC3430U, 0x00000002U}, /* SEC_MODID[617]:AXIQOS7*/ + [618] = {0xFDDC3434U, 0x00000002U}, /* SEC_MODID[618]:ARSM3*/ + [619] = {0xFDDC3438U, 0x00000002U}, /* SEC_MODID[619]:ARSM4*/ + [620] = {0xFDDC343CU, 0x00000002U}, /* SEC_MODID[620]:ARSM5*/ + [621] = {0xFDDC3440U, 0x00000002U}, /* SEC_MODID[621]:ARSM6*/ + [622] = {0xFDDC3444U, 0x00000002U}, /* SEC_MODID[622]:ARSM7*/ + [623] = {0xFDDC3448U, 0x00000002U}, /* SEC_MODID[623]:ARSM8*/ + [624] = {0xFDDC344CU, 0x00000000U}, /* SEC_MODID[624]:AXMM0*/ + [625] = {0xFDDC3450U, 0x00000000U}, /* SEC_MODID[625]:AXMM1*/ + [626] = {0xFDDC3454U, 0x00000002U}, /* SEC_MODID[626]:AXMMPMON*/ + [627] = {0xFDDC3458U, 0x00000002U}, /* SEC_MODID[627]:CKMMM*/ + [628] = {0xFDDC345CU, 0x00000002U}, /* SEC_MODID[628]:ECMMM*/ + [629] = {0xFDDC3460U, 0x00000002U}, /* SEC_MODID[629]:FBADBSC0*/ + [630] = {0xFDDC3464U, 0x00000002U}, /* SEC_MODID[630]:FBADBSC1*/ + [631] = {0xFDDC3468U, 0x00000002U}, /* SEC_MODID[631]:FBAMM*/ + [632] = {0xFDDC346CU, 0x00000002U}, /* SEC_MODID[632]:IPMMUMM00*/ + [633] = {0xFDDC3470U, 0x00000002U}, /* SEC_MODID[633]:DBS0A0*/ + [634] = {0xFDDC3474U, 0x00000002U}, /* SEC_MODID[634]:DBS0A1*/ + [635] = {0xFDDC3478U, 0x00000002U}, /* SEC_MODID[635]:DBS1A0*/ + [636] = {0xFDDC347CU, 0x00000002U}, /* SEC_MODID[636]:DBS1A1*/ + [637] = {0xFDDC3480U, 0x00000002U}, /* SEC_MODID[637]:AXCIDBS*/ + [638] = {0xFDDC3484U, 0x00000002U}, /* SEC_MODID[638]:FCPRC*/ + [639] = {0xFDDC3488U, 0x00000002U}, /* SEC_MODID[639]:DBS0D0*/ + [640] = {0xFDDC348CU, 0x00000002U}, /* SEC_MODID[640]:DBS0D1*/ + [641] = {0xFDDC3490U, 0x00000002U}, /* SEC_MODID[641]:DBS1D0*/ + [642] = {0xFDDC3494U, 0x00000002U}, /* SEC_MODID[642]:DBS1D1*/ + [643] = {0xFDDC3498U, 0x00000002U}, /* SEC_MODID[643]:FBADDR*/ + [644] = {0xFDDC349CU, 0x00000002U}, /* SEC_MODID[644]:IPMMUMM01*/ + [645] = {0xFDDC34A0U, 0x00000002U}, /* SEC_MODID[645]:IPMMUMM10*/ + [646] = {0xFDDC34A4U, 0x00000002U}, /* SEC_MODID[646]:IPMMUMM11*/ + [647] = {0xFDDC34A8U, 0x00000002U}, /* SEC_MODID[647]:IPMMUMM12*/ + [648] = {0xFDDC34ACU, 0x00000002U}, /* SEC_MODID[648]:IPMMUMM13*/ + [649] = {0xFDDC34B0U, 0x00000002U}, /* SEC_MODID[649]:IPMMUMM14*/ + [650] = {0xFDDC34B4U, 0x00000002U}, /* SEC_MODID[650]:IPMMUMM15*/ + [651] = {0xFDDC34B8U, 0x00000002U}, /* SEC_MODID[651]:IPMMUMM02*/ + [652] = {0xFDDC34BCU, 0x00000002U}, /* SEC_MODID[652]:IPMMUMM03*/ + [653] = {0xFDDC34C0U, 0x00000002U}, /* SEC_MODID[653]:IPMMUMM04*/ + [654] = {0xFDDC34C4U, 0x00000002U}, /* SEC_MODID[654]:IPMMUMM05*/ + [655] = {0xFDDC34C8U, 0x00000002U}, /* SEC_MODID[655]:IPMMUMM06*/ + [656] = {0xFDDC34CCU, 0x00000002U}, /* SEC_MODID[656]:IPMMUMM07*/ + [657] = {0xFDDC34D0U, 0x00000002U}, /* SEC_MODID[657]:IPMMUMM08*/ + [658] = {0xFDDC34D4U, 0x00000002U}, /* SEC_MODID[658]:IPMMUMM09*/ + [659] = {0xFC803400U, 0x00000002U}, /* SEC_MODID[659]:ARSN0*/ + [660] = {0xFC803404U, 0x00000002U}, /* SEC_MODID[660]:ARSN1*/ + [661] = {0xFC803408U, 0x00000002U}, /* SEC_MODID[661]:ARSN2*/ + [662] = {0xFC80340CU, 0x00000002U}, /* SEC_MODID[662]:ARSN3*/ + [663] = {0xFC803410U, 0x00000002U}, /* SEC_MODID[663]:ARSN4*/ + [664] = {0xFC803414U, 0x00000002U}, /* SEC_MODID[664]:ARSN5*/ + [665] = {0xFC803418U, 0x00000002U}, /* SEC_MODID[665]:ARSN6*/ + [666] = {0xFC80341CU, 0x00000002U}, /* SEC_MODID[666]:ARSN7*/ + [667] = {0xFC803420U, 0x00000002U}, /* SEC_MODID[667]:ARSN8*/ + [668] = {0xFC803424U, 0x00000002U}, /* SEC_MODID[668]:ECMTOP3*/ + [669] = {0xFCB53400U, 0x00000002U}, /* SEC_MODID[669]:ARSD00*/ + [670] = {0xFCB53404U, 0x00000002U}, /* SEC_MODID[670]:ARSD01*/ + [671] = {0xFCB53408U, 0x00000002U}, /* SEC_MODID[671]:ARSD02*/ + [672] = {0xFCB5340CU, 0x00000002U}, /* SEC_MODID[672]:ARSD03*/ + [673] = {0xFCB53410U, 0x00000002U}, /* SEC_MODID[673]:ARSD04*/ + [674] = {0xFCB53414U, 0x00000002U}, /* SEC_MODID[674]:ARSD05*/ + [675] = {0xFCB53418U, 0x00000002U}, /* SEC_MODID[675]:ARSD06*/ + [676] = {0xFCB5341CU, 0x00000002U}, /* SEC_MODID[676]:AXIFRAY*/ + [677] = {0xFCB53420U, 0x00000002U}, /* SEC_MODID[677]:AXIIPC*/ + [678] = {0xFCB53428U, 0x00000002U}, /* SEC_MODID[678]:AXIRPC*/ + [679] = {0xFCB5342CU, 0x00000002U}, /* SEC_MODID[679]:AXISDHI0*/ + [680] = {0xFCB53430U, 0x00000002U}, /* SEC_MODID[680]:ARSD07*/ + [681] = {0xFCB53434U, 0x00000002U}, /* SEC_MODID[681]:ARSD08*/ + [682] = {0xFCB53438U, 0x00000002U}, /* SEC_MODID[682]:ARSP00*/ + [683] = {0xFCB5343CU, 0x00000002U}, /* SEC_MODID[683]:ARSP01*/ + [684] = {0xFCB53440U, 0x00000002U}, /* SEC_MODID[684]:ARSP02*/ + [685] = {0xFCB53444U, 0x00000002U}, /* SEC_MODID[685]:ARSP03*/ + [686] = {0xFCB53448U, 0x00000002U}, /* SEC_MODID[686]:ARSP04*/ + [687] = {0xFCB5344CU, 0x00000002U}, /* SEC_MODID[687]:ARSP05*/ + [688] = {0xFCB53450U, 0x00000002U}, /* SEC_MODID[688]:ARSP06*/ + [689] = {0xFCB53454U, 0x00000002U}, /* SEC_MODID[689]:ARSP07*/ + [690] = {0xFCB53458U, 0x00000002U}, /* SEC_MODID[690]:ARSP08*/ + [691] = {0xFCB5345CU, 0x00000002U}, /* SEC_MODID[691]:IPMMUDS001*/ + [692] = {0xFCB53460U, 0x00000002U}, /* SEC_MODID[692]:CKMPER0*/ + [693] = {0xFCB53464U, 0x00000002U}, /* SEC_MODID[693]:ECMPER0*/ + [694] = {0xFCB53468U, 0x00000002U}, /* SEC_MODID[694]:FBAPER0*/ + [695] = {0xFCB5346CU, 0x00000002U}, /* SEC_MODID[695]:FSO0*/ + [696] = {0xFCB53470U, 0x00000002U}, /* SEC_MODID[696]:FSO1*/ + [697] = {0xFCB53474U, 0x00000002U}, /* SEC_MODID[697]:FSO10*/ + [698] = {0xFCB53478U, 0x00000002U}, /* SEC_MODID[698]:FSO2*/ + [699] = {0xFCB5347CU, 0x00000002U}, /* SEC_MODID[699]:FSO3*/ + [700] = {0xFCB53480U, 0x00000002U}, /* SEC_MODID[700]:FSO4*/ + [701] = {0xFCB53484U, 0x00000002U}, /* SEC_MODID[701]:FSO5*/ + [702] = {0xFCB53488U, 0x00000002U}, /* SEC_MODID[702]:FSO6*/ + [703] = {0xFCB5348CU, 0x00000002U}, /* SEC_MODID[703]:FSO7*/ + [704] = {0xFCB53490U, 0x00000002U}, /* SEC_MODID[704]:FSO8*/ + [705] = {0xFCB53494U, 0x00000002U}, /* SEC_MODID[705]:FSO9*/ + [706] = {0xFCB53498U, 0x00000002U}, /* SEC_MODID[706]:ADG*/ + [707] = {0xFCB5349CU, 0x00000002U}, /* SEC_MODID[707]:ECMSD0*/ + [708] = {0xFCB534A0U, 0x00000002U}, /* SEC_MODID[708]:IPMMUDS010*/ + [709] = {0xFCB534A4U, 0x00000002U}, /* SEC_MODID[709]:IPMMUDS011*/ + [710] = {0xFCB534A8U, 0x00000002U}, /* SEC_MODID[710]:I2C0*/ + [711] = {0xFCB534ACU, 0x00000002U}, /* SEC_MODID[711]:I2C1*/ + [712] = {0xFCB534B0U, 0x00000002U}, /* SEC_MODID[712]:I2C2*/ + [713] = {0xFCB534B4U, 0x00000002U}, /* SEC_MODID[713]:I2C3*/ + [714] = {0xFCB534B8U, 0x00000002U}, /* SEC_MODID[714]:I2C4*/ + [715] = {0xFCB534BCU, 0x00000002U}, /* SEC_MODID[715]:I2C5*/ + [716] = {0xFCB534C0U, 0x00000002U}, /* SEC_MODID[716]:IPMMUDS012*/ + [717] = {0xFCB534C4U, 0x00000002U}, /* SEC_MODID[717]:IPC*/ + [718] = {0xFCB534C8U, 0x00000002U}, /* SEC_MODID[718]:IPMMUDS000*/ + [719] = {0xFCB534CCU, 0x00000002U}, /* SEC_MODID[719]:IPMMUDS013*/ + [720] = {0xFCB534D0U, 0x00000002U}, /* SEC_MODID[720]:IPMMUDS014*/ + [721] = {0xFCB534D4U, 0x00000002U}, /* SEC_MODID[721]:IPMMUDS015*/ + [722] = {0xFCB534D8U, 0x00000002U}, /* SEC_MODID[722]:IPMMUDS002*/ + [723] = {0xFCB534DCU, 0x00000002U}, /* SEC_MODID[723]:IPMMUDS003*/ + [724] = {0xFCB534E0U, 0x00000002U}, /* SEC_MODID[724]:IPMMUDS004*/ + [725] = {0xFCB534E4U, 0x00000002U}, /* SEC_MODID[725]:IPMMUDS005*/ + [726] = {0xFCB534E8U, 0x00000002U}, /* SEC_MODID[726]:SSI*/ + [727] = {0xFCB534ECU, 0x00000002U}, /* SEC_MODID[727]:IPMMUDS006*/ + [728] = {0xFCB534F0U, 0x00000002U}, /* SEC_MODID[728]:IPMMUDS007*/ + [729] = {0xFCB534F4U, 0x00000002U}, /* SEC_MODID[729]:SYDM1P*/ + [730] = {0xFCB534F8U, 0x00000002U}, /* SEC_MODID[730]:IPMMUDS008*/ + [731] = {0xFCB534FCU, 0x00000002U}, /* SEC_MODID[731]:SYDM2P*/ + [732] = {0xFCB53500U, 0x00000002U}, /* SEC_MODID[732]:IPMMUDS009*/ + [733] = {0xFCB53640U, 0x00000002U}, /* SEC_MODID[733]:SYDM100*/ + [734] = {0xFCB53644U, 0x00000002U}, /* SEC_MODID[734]:SYDM101*/ + [735] = {0xFCB53648U, 0x00000002U}, /* SEC_MODID[735]:SYDM110*/ + [736] = {0xFCB5364CU, 0x00000002U}, /* SEC_MODID[736]:SYDM111*/ + [737] = {0xFCB53650U, 0x00000002U}, /* SEC_MODID[737]:SYDM112*/ + [738] = {0xFCB53654U, 0x00000002U}, /* SEC_MODID[738]:SYDM113*/ + [739] = {0xFCB53658U, 0x00000002U}, /* SEC_MODID[739]:SYDM114*/ + [740] = {0xFCB5365CU, 0x00000002U}, /* SEC_MODID[740]:SYDM115*/ + [741] = {0xFCB53660U, 0x00000002U}, /* SEC_MODID[741]:SYDM102*/ + [742] = {0xFCB53664U, 0x00000002U}, /* SEC_MODID[742]:SYDM103*/ + [743] = {0xFCB53668U, 0x00000002U}, /* SEC_MODID[743]:SYDM104*/ + [744] = {0xFCB5366CU, 0x00000002U}, /* SEC_MODID[744]:SYDM105*/ + [745] = {0xFCB53670U, 0x00000002U}, /* SEC_MODID[745]:SYDM106*/ + [746] = {0xFCB53674U, 0x00000002U}, /* SEC_MODID[746]:SYDM107*/ + [747] = {0xFCB53678U, 0x00000002U}, /* SEC_MODID[747]:SYDM108*/ + [748] = {0xFCB5367CU, 0x00000002U}, /* SEC_MODID[748]:SYDM109*/ + [749] = {0xFCB53680U, 0x00000002U}, /* SEC_MODID[749]:SYDM200*/ + [750] = {0xFCB53684U, 0x00000002U}, /* SEC_MODID[750]:SYDM201*/ + [751] = {0xFCB53688U, 0x00000002U}, /* SEC_MODID[751]:SYDM210*/ + [752] = {0xFCB5368CU, 0x00000002U}, /* SEC_MODID[752]:SYDM211*/ + [753] = {0xFCB53690U, 0x00000002U}, /* SEC_MODID[753]:SYDM212*/ + [754] = {0xFCB53694U, 0x00000002U}, /* SEC_MODID[754]:SYDM213*/ + [755] = {0xFCB53698U, 0x00000002U}, /* SEC_MODID[755]:SYDM214*/ + [756] = {0xFCB5369CU, 0x00000002U}, /* SEC_MODID[756]:SYDM215*/ + [757] = {0xFCB536A0U, 0x00000002U}, /* SEC_MODID[757]:SYDM202*/ + [758] = {0xFCB536A4U, 0x00000002U}, /* SEC_MODID[758]:SYDM203*/ + [759] = {0xFCB536A8U, 0x00000002U}, /* SEC_MODID[759]:SYDM204*/ + [760] = {0xFCB536ACU, 0x00000002U}, /* SEC_MODID[760]:SYDM205*/ + [761] = {0xFCB536B0U, 0x00000002U}, /* SEC_MODID[761]:SYDM206*/ + [762] = {0xFCB536B4U, 0x00000002U}, /* SEC_MODID[762]:SYDM207*/ + [763] = {0xFCB536B8U, 0x00000002U}, /* SEC_MODID[763]:SYDM208*/ + [764] = {0xFCB536BCU, 0x00000002U}, /* SEC_MODID[764]:SYDM209*/ + [765] = {0xFC683400U, 0x00000002U}, /* SEC_MODID[765]:ARVC0*/ + [766] = {0xFC683404U, 0x00000002U}, /* SEC_MODID[766]:ARVC1*/ + [767] = {0xFC683408U, 0x00000002U}, /* SEC_MODID[767]:ARVC2*/ + [768] = {0xFC68340CU, 0x00000002U}, /* SEC_MODID[768]:ARVC3*/ + [769] = {0xFC683410U, 0x00000002U}, /* SEC_MODID[769]:AXIFBABUSVC*/ + [770] = {0xFC683414U, 0x00000002U}, /* SEC_MODID[770]:ARVC4*/ + [771] = {0xFC683418U, 0x00000002U}, /* SEC_MODID[771]:ARVC5*/ + [772] = {0xFC68341CU, 0x00000002U}, /* SEC_MODID[772]:ARVC6*/ + [773] = {0xFC683420U, 0x00000002U}, /* SEC_MODID[773]:ARVC7*/ + [774] = {0xFC683424U, 0x00000002U}, /* SEC_MODID[774]:ARVC8*/ + [775] = {0xFC683428U, 0x00000002U}, /* SEC_MODID[775]:CKMVC*/ + [776] = {0xFC68342CU, 0x00000002U}, /* SEC_MODID[776]:ECMVC0*/ + [777] = {0xFC683430U, 0x00000002U}, /* SEC_MODID[777]:IMR2*/ + [778] = {0xFC683434U, 0x00000002U}, /* SEC_MODID[778]:IMR0*/ + [779] = {0xFC683438U, 0x00000002U}, /* SEC_MODID[779]:IMR1*/ + [780] = {0xFC68343CU, 0x00000002U}, /* SEC_MODID[780]:IPMMUVC01*/ + [781] = {0xFC683440U, 0x00000002U}, /* SEC_MODID[781]:IPMMUVC10*/ + [782] = {0xFC683444U, 0x00000002U}, /* SEC_MODID[782]:IMS0*/ + [783] = {0xFC683448U, 0x00000002U}, /* SEC_MODID[783]:IMS1*/ + [784] = {0xFC68344CU, 0x00000002U}, /* SEC_MODID[784]:IPMMUVC00*/ + [785] = {0xFC683450U, 0x00000002U}, /* SEC_MODID[785]:IPMMUVC11*/ + [786] = {0xFC683454U, 0x00000002U}, /* SEC_MODID[786]:IPMMUVC12*/ + [787] = {0xFC683458U, 0x00000002U}, /* SEC_MODID[787]:IPMMUVC13*/ + [788] = {0xFC68345CU, 0x00000002U}, /* SEC_MODID[788]:IPMMUVC14*/ + [789] = {0xFC683460U, 0x00000002U}, /* SEC_MODID[789]:IPMMUVC15*/ + [790] = {0xFC683464U, 0x00000002U}, /* SEC_MODID[790]:IPMMUVC02*/ + [791] = {0xFC683468U, 0x00000002U}, /* SEC_MODID[791]:IPMMUVC03*/ + [792] = {0xFC68346CU, 0x00000002U}, /* SEC_MODID[792]:IPMMUVC04*/ + [793] = {0xFC683470U, 0x00000002U}, /* SEC_MODID[793]:IPMMUVC05*/ + [794] = {0xFC683474U, 0x00000002U}, /* SEC_MODID[794]:IPMMUVC06*/ + [795] = {0xFC683478U, 0x00000002U}, /* SEC_MODID[795]:IPMMUVC07*/ + [796] = {0xFC68347CU, 0x00000002U}, /* SEC_MODID[796]:IPMMUVC08*/ + [797] = {0xFC683480U, 0x00000002U}, /* SEC_MODID[797]:IPMMUVC09*/ + [798] = {0xFC683484U, 0x00000002U}, /* SEC_MODID[798]:IV1ES*/ + [799] = {0xFEBE3400U, 0x00000002U}, /* SEC_MODID[799]:CSITOP0*/ + [800] = {0xFEBE3404U, 0x00000002U}, /* SEC_MODID[800]:ARVI10*/ + [801] = {0xFEBE3408U, 0x00000002U}, /* SEC_MODID[801]:ARVI11*/ + [802] = {0xFEBE340CU, 0x00000002U}, /* SEC_MODID[802]:ARVI12*/ + [803] = {0xFEBE3410U, 0x00000002U}, /* SEC_MODID[803]:ARVI13*/ + [804] = {0xFEBE3414U, 0x00000002U}, /* SEC_MODID[804]:ARVI14*/ + [805] = {0xFEBE3418U, 0x00000002U}, /* SEC_MODID[805]:ARVI15*/ + [806] = {0xFEBE341CU, 0x00000002U}, /* SEC_MODID[806]:ARVI16*/ + [807] = {0xFEBE3420U, 0x00000002U}, /* SEC_MODID[807]:ARVI17*/ + [808] = {0xFEBE3424U, 0x00000002U}, /* SEC_MODID[808]:ARVI18*/ + [809] = {0xFEBE3428U, 0x00000002U}, /* SEC_MODID[809]:CKMVIO*/ + [810] = {0xFEBE342CU, 0x00000002U}, /* SEC_MODID[810]:CSITOP1*/ + [811] = {0xFEBE3434U, 0x00000002U}, /* SEC_MODID[811]:DSITLINK0*/ + [812] = {0xFEBE3438U, 0x00000002U}, /* SEC_MODID[812]:DSITLINK1*/ + [813] = {0xFEBE343CU, 0x00000002U}, /* SEC_MODID[813]:ECMVIO1*/ + [814] = {0xFEBE3444U, 0x00000002U}, /* SEC_MODID[814]:IPMMUVI001*/ + [815] = {0xFEBE3448U, 0x00000002U}, /* SEC_MODID[815]:FCPVX0*/ + [816] = {0xFEBE344CU, 0x00000002U}, /* SEC_MODID[816]:FCPVX1*/ + [817] = {0xFEBE3458U, 0x00000002U}, /* SEC_MODID[817]:IPMMUVI000*/ + [818] = {0xFEBE345CU, 0x00000002U}, /* SEC_MODID[818]:IPMMUVI100*/ + [819] = {0xFEBE3460U, 0x00000002U}, /* SEC_MODID[819]:IPMMUVI010*/ + [820] = {0xFEBE3464U, 0x00000002U}, /* SEC_MODID[820]:IPMMUVI011*/ + [821] = {0xFEBE3468U, 0x00000002U}, /* SEC_MODID[821]:VSPX0*/ + [822] = {0xFEBE346CU, 0x00000002U}, /* SEC_MODID[822]:VSPX1*/ + [823] = {0xFEBE3478U, 0x00000002U}, /* SEC_MODID[823]:IPMMUVI012*/ + [824] = {0xFEBE347CU, 0x00000002U}, /* SEC_MODID[824]:IPMMUVI013*/ + [825] = {0xFEBE3480U, 0x00000002U}, /* SEC_MODID[825]:IPMMUVI014*/ + [826] = {0xFEBE3484U, 0x00000002U}, /* SEC_MODID[826]:IPMMUVI015*/ + [827] = {0xFEBE3488U, 0x00000002U}, /* SEC_MODID[827]:IPMMUVI002*/ + [828] = {0xFEBE348CU, 0x00000002U}, /* SEC_MODID[828]:IPMMUVI003*/ + [829] = {0xFEBE3490U, 0x00000002U}, /* SEC_MODID[829]:IPMMUVI004*/ + [830] = {0xFEBE3494U, 0x00000002U}, /* SEC_MODID[830]:IPMMUVI005*/ + [831] = {0xFEBE3498U, 0x00000002U}, /* SEC_MODID[831]:IPMMUVI006*/ + [832] = {0xFEBE349CU, 0x00000002U}, /* SEC_MODID[832]:IPMMUVI007*/ + [833] = {0xFEBE34A0U, 0x00000002U}, /* SEC_MODID[833]:IPMMUVI008*/ + [834] = {0xFEBE34A4U, 0x00000002U}, /* SEC_MODID[834]:IPMMUVI009*/ + [835] = {0xFEBE34A8U, 0x00000002U}, /* SEC_MODID[835]:IPMMUVI101*/ + [836] = {0xFEBE34ACU, 0x00000002U}, /* SEC_MODID[836]:IPMMUVI110*/ + [837] = {0xFEBE34B0U, 0x00000002U}, /* SEC_MODID[837]:IPMMUVI111*/ + [838] = {0xFEBE34B4U, 0x00000002U}, /* SEC_MODID[838]:IPMMUVI112*/ + [839] = {0xFEBE34B8U, 0x00000002U}, /* SEC_MODID[839]:IPMMUVI113*/ + [840] = {0xFEBE34BCU, 0x00000002U}, /* SEC_MODID[840]:IPMMUVI114*/ + [841] = {0xFEBE34C0U, 0x00000002U}, /* SEC_MODID[841]:IPMMUVI115*/ + [842] = {0xFEBE34C4U, 0x00000002U}, /* SEC_MODID[842]:IPMMUVI102*/ + [843] = {0xFEBE34C8U, 0x00000002U}, /* SEC_MODID[843]:IPMMUVI103*/ + [844] = {0xFEBE34CCU, 0x00000002U}, /* SEC_MODID[844]:IPMMUVI104*/ + [845] = {0xFEBE34D0U, 0x00000002U}, /* SEC_MODID[845]:IPMMUVI105*/ + [846] = {0xFEBE34D4U, 0x00000002U}, /* SEC_MODID[846]:IPMMUVI106*/ + [847] = {0xFEBE34D8U, 0x00000002U}, /* SEC_MODID[847]:IPMMUVI107*/ + [848] = {0xFEBE34DCU, 0x00000002U}, /* SEC_MODID[848]:IPMMUVI108*/ + [849] = {0xFEBE34E0U, 0x00000002U}, /* SEC_MODID[849]:IPMMUVI109*/ + [850] = {0xFEBE3504U, 0x00000002U}, /* SEC_MODID[850]:AXIFBABUSVIO*/ + [851] = {0xFEBF3400U, 0x00000002U}, /* SEC_MODID[851]:ARVI0*/ + [852] = {0xFEBF3404U, 0x00000002U}, /* SEC_MODID[852]:ARVI1*/ + [853] = {0xFEBF3408U, 0x00000002U}, /* SEC_MODID[853]:ARVI2*/ + [854] = {0xFEBF340CU, 0x00000002U}, /* SEC_MODID[854]:ARVI3*/ + [855] = {0xFEBF3410U, 0x00000002U}, /* SEC_MODID[855]:ARVI4*/ + [856] = {0xFEBF3414U, 0x00000002U}, /* SEC_MODID[856]:ARVI5*/ + [857] = {0xFEBF3418U, 0x00000002U}, /* SEC_MODID[857]:ARVI6*/ + [858] = {0xFEBF341CU, 0x00000002U}, /* SEC_MODID[858]:ARVI7*/ + [859] = {0xFEBF3420U, 0x00000002U}, /* SEC_MODID[859]:ARVI8*/ + [860] = {0xFEBF3424U, 0x00000002U}, /* SEC_MODID[860]:ECMVIO0*/ + [861] = {0xFEBF3428U, 0x00000002U}, /* SEC_MODID[861]:ISP0*/ + [862] = {0xFEBF342CU, 0x00000002U}, /* SEC_MODID[862]:ISP0CORE*/ + [863] = {0xFEBF3430U, 0x00000002U}, /* SEC_MODID[863]:ISP1*/ + [864] = {0xFEBF3434U, 0x00000002U}, /* SEC_MODID[864]:ISP1CORE*/ + [865] = {0xFEBF3454U, 0x00000002U}, /* SEC_MODID[865]:VIN00*/ + [866] = {0xFEBF3458U, 0x00000002U}, /* SEC_MODID[866]:VIN01*/ + [867] = {0xFEBF345CU, 0x00000002U}, /* SEC_MODID[867]:VIN02*/ + [868] = {0xFEBF3460U, 0x00000002U}, /* SEC_MODID[868]:VIN03*/ + [869] = {0xFEBF3464U, 0x00000002U}, /* SEC_MODID[869]:VIN04*/ + [870] = {0xFEBF3468U, 0x00000002U}, /* SEC_MODID[870]:VIN05*/ + [871] = {0xFEBF346CU, 0x00000002U}, /* SEC_MODID[871]:VIN06*/ + [872] = {0xFEBF3470U, 0x00000002U}, /* SEC_MODID[872]:VIN07*/ + [873] = {0xFEBF3474U, 0x00000002U}, /* SEC_MODID[873]:VIN10*/ + [874] = {0xFEBF3478U, 0x00000002U}, /* SEC_MODID[874]:VIN11*/ + [875] = {0xFEBF347CU, 0x00000002U}, /* SEC_MODID[875]:VIN12*/ + [876] = {0xFEBF3480U, 0x00000002U}, /* SEC_MODID[876]:VIN13*/ + [877] = {0xFEBF3484U, 0x00000002U}, /* SEC_MODID[877]:VIN14*/ + [878] = {0xFEBF3488U, 0x00000002U}, /* SEC_MODID[878]:VIN15*/ + [879] = {0xFEBF348CU, 0x00000002U}, /* SEC_MODID[879]:VIN16*/ + [880] = {0xFEBF3490U, 0x00000002U}, /* SEC_MODID[880]:VIN17*/ + [881] = {0xFC313400U, 0x00000002U}, /* SEC_MODID[881]:ARVIP00*/ + [882] = {0xFC313404U, 0x00000002U}, /* SEC_MODID[882]:ARVIP01*/ + [883] = {0xFC313408U, 0x00000002U}, /* SEC_MODID[883]:ARVIP02*/ + [884] = {0xFC31340CU, 0x00000002U}, /* SEC_MODID[884]:ARVIP03*/ + [885] = {0xFC313410U, 0x00000002U}, /* SEC_MODID[885]:AXIFBABUSVIP0*/ + [886] = {0xFC313414U, 0x00000002U}, /* SEC_MODID[886]:ARVIP04*/ + [887] = {0xFC313418U, 0x00000002U}, /* SEC_MODID[887]:ARVIP05*/ + [888] = {0xFC31341CU, 0x00000002U}, /* SEC_MODID[888]:ARVIP06*/ + [889] = {0xFC313420U, 0x00000002U}, /* SEC_MODID[889]:ARVIP07*/ + [890] = {0xFC313424U, 0x00000002U}, /* SEC_MODID[890]:ARVIP08*/ + [891] = {0xFC313428U, 0x00000002U}, /* SEC_MODID[891]:CKMVIP*/ + [892] = {0xFC31342CU, 0x00000002U}, /* SEC_MODID[892]:ECMVIP0*/ + [893] = {0xFC313430U, 0x00000002U}, /* SEC_MODID[893]:IPMMUVIP000*/ + [894] = {0xFC313438U, 0x00000002U}, /* SEC_MODID[894]:SMPO0*/ + [895] = {0xFC31343CU, 0x00000002U}, /* SEC_MODID[895]:SMPS0*/ + [896] = {0xFC313440U, 0x00000002U}, /* SEC_MODID[896]:UMFL0*/ + [897] = {0xFC313444U, 0x00000002U}, /* SEC_MODID[897]:IPMMUVIP001*/ + [898] = {0xFC313448U, 0x00000002U}, /* SEC_MODID[898]:IPMMUVIP010*/ + [899] = {0xFC31344CU, 0x00000002U}, /* SEC_MODID[899]:IPMMUVIP011*/ + [900] = {0xFC313450U, 0x00000002U}, /* SEC_MODID[900]:UMFL0M_W*/ + [901] = {0xFC313454U, 0x00000002U}, /* SEC_MODID[901]:IPMMUVIP012*/ + [902] = {0xFC313458U, 0x00000002U}, /* SEC_MODID[902]:IPMMUVIP013*/ + [903] = {0xFC31345CU, 0x00000002U}, /* SEC_MODID[903]:IPMMUVIP014*/ + [904] = {0xFC313460U, 0x00000002U}, /* SEC_MODID[904]:IPMMUVIP015*/ + [905] = {0xFC313464U, 0x00000002U}, /* SEC_MODID[905]:IPMMUVIP002*/ + [906] = {0xFC313468U, 0x00000002U}, /* SEC_MODID[906]:IPMMUVIP003*/ + [907] = {0xFC31346CU, 0x00000002U}, /* SEC_MODID[907]:IPMMUVIP004*/ + [908] = {0xFC313470U, 0x00000002U}, /* SEC_MODID[908]:IPMMUVIP005*/ + [909] = {0xFC313474U, 0x00000002U}, /* SEC_MODID[909]:IPMMUVIP006*/ + [910] = {0xFC313478U, 0x00000002U}, /* SEC_MODID[910]:IPMMUVIP007*/ + [911] = {0xFC31347CU, 0x00000002U}, /* SEC_MODID[911]:IPMMUVIP008*/ + [912] = {0xFC313480U, 0x00000002U}, /* SEC_MODID[912]:IPMMUVIP009*/ + [913] = {0xFC343400U, 0x00000002U}, /* SEC_MODID[913]:ARVIP10*/ + [914] = {0xFC343404U, 0x00000002U}, /* SEC_MODID[914]:ARVIP11*/ + [915] = {0xFC343408U, 0x00000002U}, /* SEC_MODID[915]:ARVIP12*/ + [916] = {0xFC34340CU, 0x00000002U}, /* SEC_MODID[916]:ARVIP13*/ + [917] = {0xFC343410U, 0x00000002U}, /* SEC_MODID[917]:AXIFBABUSVIP1*/ + [918] = {0xFC343414U, 0x00000002U}, /* SEC_MODID[918]:ARVIIP14*/ + [919] = {0xFC343418U, 0x00000002U}, /* SEC_MODID[919]:ARVIIP15*/ + [920] = {0xFC34341CU, 0x00000002U}, /* SEC_MODID[920]:ARVIIP16*/ + [921] = {0xFC343420U, 0x00000002U}, /* SEC_MODID[921]:ARVIIP17*/ + [922] = {0xFC343424U, 0x00000002U}, /* SEC_MODID[922]:ARVIIP18*/ + [923] = {0xFC343438U, 0x00000002U}, /* SEC_MODID[923]:ECMVIP1*/ + [924] = {0xFC34343CU, 0x00000002U}, /* SEC_MODID[924]:IPMMUVIP101*/ + [925] = {0xFC343440U, 0x00000002U}, /* SEC_MODID[925]:IPMMUVIP100*/ + [926] = {0xFC343444U, 0x00000002U}, /* SEC_MODID[926]:IPMMUVIP110*/ + [927] = {0xFC343448U, 0x00000002U}, /* SEC_MODID[927]:IPMMUVIP111*/ + [928] = {0xFC34344CU, 0x00000002U}, /* SEC_MODID[928]:IPMMUVIP112*/ + [929] = {0xFC343450U, 0x00000002U}, /* SEC_MODID[929]:IPMMUVIP113*/ + [930] = {0xFC343454U, 0x00000002U}, /* SEC_MODID[930]:IPMMUVIP114*/ + [931] = {0xFC343458U, 0x00000002U}, /* SEC_MODID[931]:IPMMUVIP115*/ + [932] = {0xFC34345CU, 0x00000002U}, /* SEC_MODID[932]:IPMMUVIP102*/ + [933] = {0xFC343460U, 0x00000002U}, /* SEC_MODID[933]:IPMMUVIP103*/ + [934] = {0xFC343464U, 0x00000002U}, /* SEC_MODID[934]:IPMMUVIP104*/ + [935] = {0xFC343468U, 0x00000002U}, /* SEC_MODID[935]:IPMMUVIP105*/ + [936] = {0xFC34346CU, 0x00000002U}, /* SEC_MODID[936]:IPMMUVIP106*/ + [937] = {0xFC343470U, 0x00000002U}, /* SEC_MODID[937]:IPMMUVIP107*/ + [938] = {0xFC343474U, 0x00000002U}, /* SEC_MODID[938]:IPMMUVIP108*/ + [939] = {0xFC343478U, 0x00000002U}, /* SEC_MODID[939]:IPMMUVIP109*/ + [940] = {0xFC343518U, 0x00000002U}, /* SEC_MODID[940]:PAP*/ + [941] = {0xFC403400U, 0x00000002U}, /* SEC_MODID[941]:ARDSP0*/ + [942] = {0xFC403404U, 0x00000002U}, /* SEC_MODID[942]:ARDSP1*/ + [943] = {0xFC403408U, 0x00000002U}, /* SEC_MODID[943]:ARDSP2*/ + [944] = {0xFC40340CU, 0x00000002U}, /* SEC_MODID[944]:ARDSP3*/ + [945] = {0xFC403410U, 0x00000002U}, /* SEC_MODID[945]:ARDSP4*/ + [946] = {0xFC403414U, 0x00000002U}, /* SEC_MODID[946]:ARDSP5*/ + [947] = {0xFC403418U, 0x00000002U}, /* SEC_MODID[947]:ARDSP6*/ + [948] = {0xFC40341CU, 0x00000002U}, /* SEC_MODID[948]:ARDSP7*/ + [949] = {0xFC403420U, 0x00000002U}, /* SEC_MODID[949]:ECMDSP*/ + [950] = {0xFC403424U, 0x00000002U}, /* SEC_MODID[950]:AXIDSP0*/ + [951] = {0xFC403428U, 0x00000002U}, /* SEC_MODID[951]:AXIDSP1*/ + [952] = {0xFC40342CU, 0x00000002U}, /* SEC_MODID[952]:AXIDSP2*/ + [953] = {0xFC403430U, 0x00000002U}, /* SEC_MODID[953]:AXIDSP3*/ + [955] = {0xFDDB9624U, 0x00000001U}, /* SEC_MODID[954]:ARCC*/ + [954] = {0xFDDB9638U, 0x00000001U}, /* SEC_MODID[955]:ARRTRAM*/ + [956] = {0xFCB53424U, 0x00000002U}, /* SEC_MODID[956]:RSV0*/ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_axi_tbl" +const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[] = { + [0] = {0xFD482010U, 0x0000000FU}, /* RGIDR_MODID[4]:ARRT01*/ + [1] = {0xFD482014U, 0x0000000FU}, /* RGIDR_MODID[5]:ARRT02*/ + [2] = {0xFDA02048U, 0x0000000FU}, /* RGIDR_MODID[42]:ARS01*/ + [3] = {0xFDA0204CU, 0x0000000FU}, /* RGIDR_MODID[43]:ARS02*/ + [4] = {0xFCB62028U, 0x0000000FU}, /* RGIDR_MODID[106]:ARSP31*/ + [5] = {0xFCB6202CU, 0x0000000FU}, /* RGIDR_MODID[107]:ARSP32*/ + [6] = {0xFCB92004U, 0x0000000FU}, /* RGIDR_MODID[121]:ARSP41*/ + [7] = {0xFCB92008U, 0x0000000FU}, /* RGIDR_MODID[122]:ARSP42*/ + [8] = {0xFC672004U, 0x0000002FU}, /* RGIDR_MODID[165]:ARVC11*/ + [9] = {0xFC672008U, 0x0000002FU}, /* RGIDR_MODID[166]:ARVC12*/ + [10] = {0xFEBD2004U, 0x0000000FU}, /* RGIDR_MODID[178]:ARVI41*/ + [11] = {0xFEBD2008U, 0x0000000FU}, /* RGIDR_MODID[179]:ARVI42*/ + [12] = {0xFCF82140U, 0x0000000FU}, /* RGIDR_MODID[245]:ARHC1*/ + [13] = {0xFCF82144U, 0x0000000FU}, /* RGIDR_MODID[246]:ARHC2*/ + [14] = {0xFC882004U, 0x0000000FU}, /* RGIDR_MODID[261]:ARIMP01*/ + [15] = {0xFC882008U, 0x0000000FU}, /* RGIDR_MODID[262]:ARIMP02*/ + [16] = {0xFC012004U, 0x0000000FU}, /* RGIDR_MODID[297]:ARPV1*/ + [17] = {0xFC01200CU, 0x0000000FU}, /* RGIDR_MODID[299]:ARPV2*/ + [18] = {0xFDC22004U, 0x0000000FU}, /* RGIDR_MODID[330]:ARRC1*/ + [19] = {0xFDC22008U, 0x0000000FU}, /* RGIDR_MODID[331]:ARRC2*/ + [20] = {0xFD442060U, 0x0000000FU}, /* RGIDR_MODID[369]:ARRD1*/ + [21] = {0xFD442064U, 0x0000000FU}, /* RGIDR_MODID[370]:ARRD2*/ + [22] = {0xFD442084U, 0x0000000FU}, /* RGIDR_MODID[378]:ARRT1*/ + [23] = {0xFD442088U, 0x0000000FU}, /* RGIDR_MODID[379]:ARRT2*/ + [26] = {0xFC862004U, 0x0000000FU}, /* RGIDR_MODID[551]:ARSC1*/ + [27] = {0xFC862008U, 0x0000000FU}, /* RGIDR_MODID[552]:ARSC2*/ + [24] = {0xFC862028U, 0x0000000FU}, /* RGIDR_MODID[560]:ARSTM1*/ + [25] = {0xFC862038U, 0x0000000FU}, /* RGIDR_MODID[564]:ARSTM2*/ + [28] = {0xFDDC2004U, 0x0000000FU}, /* RGIDR_MODID[606]:AXIARNMM*/ + [29] = {0xFDDC200CU, 0x0000000FU}, /* RGIDR_MODID[608]:ARSM1*/ + [30] = {0xFDDC2010U, 0x0000000FU}, /* RGIDR_MODID[609]:ARSM2*/ + [31] = {0xFC802004U, 0x0000000FU}, /* RGIDR_MODID[660]:ARSN1*/ + [32] = {0xFC802008U, 0x0000000FU}, /* RGIDR_MODID[661]:ARSN2*/ + [33] = {0xFCB52004U, 0x0000000FU}, /* RGIDR_MODID[670]:ARSD01*/ + [34] = {0xFCB52008U, 0x0000000FU}, /* RGIDR_MODID[671]:ARSD02*/ + [35] = {0xFCB5203CU, 0x0000000FU}, /* RGIDR_MODID[683]:ARSP01*/ + [36] = {0xFCB52040U, 0x0000000FU}, /* RGIDR_MODID[684]:ARSP02*/ + [37] = {0xFC682004U, 0x0000000FU}, /* RGIDR_MODID[766]:ARVC1*/ + [38] = {0xFC682008U, 0x0000000FU}, /* RGIDR_MODID[767]:ARVC2*/ + [39] = {0xFEBE2008U, 0x0000000FU}, /* RGIDR_MODID[801]:ARVI11*/ + [40] = {0xFEBE200CU, 0x0000000FU}, /* RGIDR_MODID[802]:ARVI12*/ + [41] = {0xFEBF2004U, 0x0000000FU}, /* RGIDR_MODID[852]:ARVI1*/ + [42] = {0xFEBF2008U, 0x0000000FU}, /* RGIDR_MODID[853]:ARVI2*/ + [43] = {0xFC312004U, 0x0000000FU}, /* RGIDR_MODID[882]:ARVIP01*/ + [44] = {0xFC312008U, 0x0000000FU}, /* RGIDR_MODID[883]:ARVIP02*/ + [45] = {0xFC342004U, 0x0000000FU}, /* RGIDR_MODID[914]:ARVIP11*/ + [46] = {0xFC342008U, 0x0000000FU}, /* RGIDR_MODID[915]:ARVIP12*/ + [47] = {0xFC402004U, 0x0000000FU}, /* RGIDR_MODID[942]:ARDSP1*/ + [48] = {0xFC402008U, 0x0000000FU}, /* RGIDR_MODID[943]:ARDSP2*/ + [49] = {0xFD482410U, 0x00000000U}, /* RGIDW_MODID[4]:ARRT01*/ + [50] = {0xFD482414U, 0x00000000U}, /* RGIDW_MODID[5]:ARRT02*/ + [51] = {0xFDA02448U, 0x00000000U}, /* RGIDW_MODID[42]:ARS01*/ + [52] = {0xFDA0244CU, 0x00000000U}, /* RGIDW_MODID[43]:ARS02*/ + [53] = {0xFCB62428U, 0x00000000U}, /* RGIDW_MODID[106]:ARSP31*/ + [54] = {0xFCB6242CU, 0x00000000U}, /* RGIDW_MODID[107]:ARSP32*/ + [55] = {0xFCB92404U, 0x00000000U}, /* RGIDW_MODID[121]:ARSP41*/ + [56] = {0xFCB92408U, 0x00000000U}, /* RGIDW_MODID[122]:ARSP42*/ + [57] = {0xFC672404U, 0x00000000U}, /* RGIDW_MODID[165]:ARVC11*/ + [58] = {0xFC672408U, 0x00000000U}, /* RGIDW_MODID[166]:ARVC12*/ + [59] = {0xFEBD2404U, 0x00000000U}, /* RGIDW_MODID[178]:ARVI41*/ + [60] = {0xFEBD2408U, 0x00000000U}, /* RGIDW_MODID[179]:ARVI42*/ + [61] = {0xFCF82540U, 0x00000000U}, /* RGIDW_MODID[245]:ARHC1*/ + [62] = {0xFCF82544U, 0x00000000U}, /* RGIDW_MODID[246]:ARHC2*/ + [63] = {0xFC882404U, 0x00000000U}, /* RGIDW_MODID[261]:ARIMP01*/ + [64] = {0xFC882408U, 0x00000000U}, /* RGIDW_MODID[262]:ARIMP02*/ + [65] = {0xFC012404U, 0x00000000U}, /* RGIDW_MODID[297]:ARPV1*/ + [66] = {0xFC01240CU, 0x00000000U}, /* RGIDW_MODID[299]:ARPV2*/ + [67] = {0xFDC22404U, 0x00000000U}, /* RGIDW_MODID[330]:ARRC1*/ + [68] = {0xFDC22408U, 0x00000000U}, /* RGIDW_MODID[331]:ARRC2*/ + [69] = {0xFD442460U, 0x00000000U}, /* RGIDW_MODID[368]:ARRD1*/ + [70] = {0xFD442464U, 0x00000000U}, /* RGIDW_MODID[369]:ARRD2*/ + [71] = {0xFD442484U, 0x00000000U}, /* RGIDW_MODID[377]:ARRT1*/ + [72] = {0xFD442488U, 0x00000000U}, /* RGIDW_MODID[378]:ARRT2*/ + [75] = {0xFC862404U, 0x00000000U}, /* RGIDW_MODID[550]:ARSC1*/ + [76] = {0xFC862408U, 0x00000000U}, /* RGIDW_MODID[551]:ARSC2*/ + [73] = {0xFC862428U, 0x00000000U}, /* RGIDW_MODID[559]:ARSTM1*/ + [74] = {0xFC862438U, 0x00000000U}, /* RGIDW_MODID[563]:ARSTM2*/ + [77] = {0xFDDC2404U, 0x00000000U}, /* RGIDW_MODID[605]:AXIARNMM*/ + [78] = {0xFDDC240CU, 0x00000000U}, /* RGIDW_MODID[607]:ARSM1*/ + [79] = {0xFDDC2410U, 0x00000000U}, /* RGIDW_MODID[608]:ARSM2*/ + [80] = {0xFC802404U, 0x00000000U}, /* RGIDW_MODID[659]:ARSN1*/ + [81] = {0xFC802408U, 0x00000000U}, /* RGIDW_MODID[660]:ARSN2*/ + [82] = {0xFCB52404U, 0x00000000U}, /* RGIDW_MODID[669]:ARSD01*/ + [83] = {0xFCB52408U, 0x00000000U}, /* RGIDW_MODID[670]:ARSD02*/ + [84] = {0xFCB5243CU, 0x00000000U}, /* RGIDW_MODID[682]:ARSP01*/ + [85] = {0xFCB52440U, 0x00000000U}, /* RGIDW_MODID[683]:ARSP02*/ + [86] = {0xFC682404U, 0x00000000U}, /* RGIDW_MODID[765]:ARVC1*/ + [87] = {0xFC682408U, 0x00000000U}, /* RGIDW_MODID[766]:ARVC2*/ + [88] = {0xFEBE2408U, 0x00000000U}, /* RGIDW_MODID[800]:ARVI11*/ + [89] = {0xFEBE240CU, 0x00000000U}, /* RGIDW_MODID[801]:ARVI12*/ + [90] = {0xFEBF2404U, 0x00000000U}, /* RGIDW_MODID[851]:ARVI1*/ + [91] = {0xFEBF2408U, 0x00000000U}, /* RGIDW_MODID[852]:ARVI2*/ + [92] = {0xFC312404U, 0x00000000U}, /* RGIDW_MODID[881]:ARVIP01*/ + [93] = {0xFC312408U, 0x00000000U}, /* RGIDW_MODID[882]:ARVIP02*/ + [94] = {0xFC342404U, 0x00000000U}, /* RGIDW_MODID[913]:ARVIP11*/ + [95] = {0xFC342408U, 0x00000000U}, /* RGIDW_MODID[914]:ARVIP12*/ + [96] = {0xFC402404U, 0x00000000U}, /* RGIDW_MODID[941]:ARDSP1*/ + [97] = {0xFC402408U, 0x00000000U}, /* RGIDW_MODID[942]:ARDSP2*/ +}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_gid_tbl" +const REGION_ID_SETTING_TABLE g_rgid_gid_tbl[] = { + [0] = {0xFC0F0000U, 0x000F0024U}, /* CCI MPU GID register 0 */ + /* Physical address:0xF12F0000, Logical address 0x0xFC0F0000 */ + [1] = {0xFC0F0004U, 0x000F0024U}, /* CCI MPU GID register 1 */ + /* Physical address:0xF12F0004, Logical address 0x0xFC0F0004 */ +}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +const uint32_t g_rgid_rtdma_setting_value[RTDMA_MODULE_MAX][RTDMA_CH_MAX][2U] = { + {/* Module0 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, + {/* Module1 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, + {/* Module2 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, + {/* Module3 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + } +}; + +const uint32_t g_rgid_sysdma_setting_value[SYSDMA_MODULE_MAX][SYSDMA_CH_MAX][2U] = { + {/* Module0 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {SYSDMA_EN, RGID_2}, /* CH0 */ + [1] = {SYSDMA_EN, RGID_2}, /* CH1 */ + [2] = {SYSDMA_EN, RGID_2}, /* CH2 */ + [3] = {SYSDMA_EN, RGID_2}, /* CH3 */ + [4] = {SYSDMA_EN, RGID_2}, /* CH4 */ + [5] = {SYSDMA_EN, RGID_2}, /* CH5 */ + [6] = {SYSDMA_EN, RGID_2}, /* CH6 */ + [7] = {SYSDMA_EN, RGID_2}, /* CH7 */ + [8] = {SYSDMA_EN, RGID_2}, /* CH8 */ + [9] = {SYSDMA_EN, RGID_2}, /* CH9 */ + [10] = {SYSDMA_EN, RGID_2}, /* CH10 */ + [11] = {SYSDMA_EN, RGID_2}, /* CH11 */ + [12] = {SYSDMA_EN, RGID_2}, /* CH12 */ + [13] = {SYSDMA_EN, RGID_2}, /* CH13 */ + [14] = {SYSDMA_EN, RGID_2}, /* CH14 */ + [15] = {SYSDMA_EN, RGID_2} /* CH15 */ + }, + {/* Module1 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {SYSDMA_EN, RGID_2}, /* CH0 */ + [1] = {SYSDMA_EN, RGID_2}, /* CH1 */ + [2] = {SYSDMA_EN, RGID_2}, /* CH2 */ + [3] = {SYSDMA_EN, RGID_2}, /* CH3 */ + [4] = {SYSDMA_EN, RGID_2}, /* CH4 */ + [5] = {SYSDMA_EN, RGID_2}, /* CH5 */ + [6] = {SYSDMA_EN, RGID_2}, /* CH6 */ + [7] = {SYSDMA_EN, RGID_2}, /* CH7 */ + [8] = {SYSDMA_EN, RGID_2}, /* CH8 */ + [9] = {SYSDMA_EN, RGID_2}, /* CH9 */ + [10] = {SYSDMA_EN, RGID_2}, /* CH10 */ + [11] = {SYSDMA_EN, RGID_2}, /* CH11 */ + [12] = {SYSDMA_EN, RGID_2}, /* CH12 */ + [13] = {SYSDMA_EN, RGID_2}, /* CH13 */ + [14] = {SYSDMA_EN, RGID_2}, /* CH14 */ + [15] = {SYSDMA_EN, RGID_2} /* CH15 */ + }, +}; + +/* When V4H, this table is used as RT-VRAM0. */ +/* RAM protection setting for SECDIV[n]D_0 / SECCTRR[m]D_0 / SECCTRW[m]D_0 */ +const RTRAM_PROTECTION_STRUCTUR g_rtsram_protection_table[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTSRAM_ICUMX_IPL_AREA] = {NOT_USED_VALUE, {0x0000FFFCU, 0x0000FFFEU}}, /* not used for address value */ + /* Area0 phys:0xE0000000-0xE003FFFF R:RGID0/1 W:RGID0 */ + [RTSRAM_ICUMX_FW_AREA] = {RTSRAM_AREA1_TOP, {0x0004FFFEU, 0x0004FFFEU}}, /* Area1 phys:0xE0040000-0xE00FFFFF R:RGID0 W:RGID0 */ + [2] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [3] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* this table is finaly setting for RT-VRAM protection */ +/* RAM protection setting for SECDIV[n]D_1 / SECCTRR[m]D_1 / SECCTRW[m]D_1 */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table_1[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM_BLANK_AREA] = {NOT_USED_VALUE, {0x0000FFB6U, 0x0000FFB2U}}, /* not used for address value */ + /* Area0 phys:0xE2000000-0xE200FFFF R:RGID0/3/6 W:RGID0/2/3/6 */ + [RTVRAM_EXTEND_CACHE_AREA] = {RTVRAM_AREA1_TOP, {0x0000BFFFU, 0x0000BFFFU}}, /* Area1 phys:0xE2010000-0xE20FFFFF R:RGID14 W:RGID14 */ + [RTVRAM_RTOS_AREA] = {RTVRAM_AREA2_TOP, {0x0000FFF4U, 0x0000FFF0U}}, /* Area2 phys:0xE2100000-0xE3BFFFFF R:RGID0/1/3 W:RGID0/1/2/3 */ + [3] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for SPTDIVCR[n] / SPTRGNCR[n] / SPTSECCR[n] */ +const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX] = { + /* access Secure */ + /* address R | W R|W */ + [SYSTEM_RAM_CX_2ND_IPL] = {NOT_USED_VALUE, {0xFFD8FFD8U, 0x00000000U}}, /* not used for address value */ + /* Area0 phys:0xE6300000-0xE635DFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [SYSTEM_RAM_SHARED_MEM] = {SYSTEM_RAM_AREA1_TOP, {0xFFD8FFD8U, 0x00000000U}}, /* Area1 phys:0xE635E000-0xE635FFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [2] = {SYSTEM_RAM_AREA2_TOP, {0xFFDAFFDAU, 0x00000000U}}, /* Area2 phys:0xE6360000-0xE63FFFFF R:RGID0/2/5 W:RGID0/2/5 */ + [3] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for DPTDIVCR[n] / DPTRGNCR[n] / DPTSECCR[n] */ +const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX] = { + /* access secure */ + /* address R | W R|W */ + [RTVRAM_EXTEND_AREA] = {NOT_USED_VALUE, {0xBFFFBFFFU, 0x00000000U}}, /* not used for address value */ + /* Area0 phys:0x04_00000000-0x04_01BFFFFF R:RGID14 W:RGID14 */ + [CR_FW_SHARED_AREA] = {DRAM_ADDR_AREA1, {0xFFBCFFBCU, 0x00000000U}}, /* Area1 phys:0x04_01C00000-0x04_01CFFFFF R:RGID0/1/6 W:RGID0/1/6 */ + [SDRAM_BLANK_AREA] = {DRAM_ADDR_AREA2, {0xFF90FF90U, 0x00000000U}}, /* Area2:OPTEE_DISABLE phys:0x04_01D00000-0x04_063FFFFF + * Area2:OPTEE_ENABLE phys:0x04_01D00000-0x04_040FFFFF + * R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFAFFF8U, 0x00000000U}}, /* Area3 phys:0x04_06400000-0x04_0643FFFF R:RGID0/2 W:RGID0/1/2 */ + [SDRAM_PUBLIC_AREA] = {DRAM_ADDR_AREA4, {0xFF90FF90U, 0x00000000U}}, /* Area4 phys:0x04_06440000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA5, {0xFFB9FFB9U, 0x00000000U}}, /* Area5 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA6, {0xFFB0FFB0U, 0x00000000U}}, /* Area6 phys:0x04_08000000-0x04_1DBFFFFF R:RGID0/1/2/3/6 W:RGID0/1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA7, {0xFFB9FFB9U, 0x00000000U}}, /* Area7 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFBDFFBDU, 0x00000000U}}, /* Area8 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFDDFFDDU, 0x00000000U}}, /* Area9 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA11,{0xBF90BF90U, 0x00000000U}}, /* Area11 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA12,{0xFFFFFFFFU, 0x00000000U}}, /* Area12 phys:0x05_00000000-0x05_FFFFFFFF */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFF9FFF9U, 0x00000000U}}, /* Area13 phys:0x06_00000000-0x06_FFFFFFFF R:RGID1/2 W:RGID1/2 */ + [14] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [16] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +#else + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFAFFFAU, 0x00000000U}}, /* Area3 phys:0x04_04100000-0x04_063FFFFF R:RGID0/2 W:RGID0/2 */ + [SDRAM_PROTECT_AREA2]= {DRAM_ADDR_AREA4, {0xFFFAFFF8U, 0x00000000U}}, /* Area4 phys:0x04_06400000-0x04_0643FFFF R:RGID0/2 W:RGID0/1/2 */ + [SDRAM_BLANK_AREA2] = {DRAM_ADDR_AREA5, {0xFF90FF90U, 0x00000000U}}, /* Area5 phys:0x04_06440000-0x04_07DFFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [OPTEE_SHARED_AREA] = {DRAM_ADDR_AREA6, {0xFFFBFFFBU, 0x00000000U}}, /* Area6 phys:0x04_07E00000-0x04_07EFFFFF R:RGID2 W:RGID2 */ + [SDRAM_BLANK_AREA3] = {DRAM_ADDR_AREA7, {0xFF90FF90U, 0x00000000U}}, /* Area7 phys:0x04_07F00000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFB9FFB9U, 0x00000000U}}, /* Area8 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFB0FFB0U, 0x00000000U}}, /* Area9 phys:0x04_08000000-0x04_1DBFFFFF R:RGID0/1/2/3/6 W:RGID0/1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA11,{0xFFBDFFBDU, 0x00000000U}}, /* Area11 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA12,{0xFFDDFFDDU, 0x00000000U}}, /* Area12 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFB9FFB9U, 0x00000000U}}, /* Area13 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA14,{0xBF90BF90U, 0x00000000U}}, /* Area14 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA15,{0xFFFFFFFFU, 0x00000000U}}, /* Area15 phys:0x05_00000000-0x05_FFFFFFFF */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA16,{0xFFF9FFF9U, 0x00000000U}}, /* Area16 phys:0x06_00000000-0x06_FFFFFFFF R:RGID1/2 W:RGID1/2 */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + [17] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [18] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [19] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [20] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [21] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [22] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [23] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [24] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [25] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [26] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [27] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [28] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [29] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [30] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [31] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [32] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [33] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [34] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [35] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [36] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [37] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [38] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [39] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [40] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [41] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [42] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [43] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [44] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [45] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [46] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [47] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [48] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [49] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [50] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [51] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [52] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [53] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [54] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [55] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [56] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [57] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [58] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [59] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [60] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [61] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [62] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [63] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +const CONFIGURATION_SETTING_TABLE g_fdt_tbl[FDT_REG_MAX] = { + [0] = {0xFD480700U, 0x00000002U}, /*FDT_AXRT2APRT0*/ + [1] = {0xFDA00700U, 0x00000002U}, /*FDT_AXSC2APS0*/ + [2] = {0xFCB60700U, 0x00000004U}, /*FDT_AXSP02APSP3*/ + [3] = {0xFCB60704U, 0x00000004U}, /*FDT_AXSD02APSP3*/ + [4] = {0xFCB90700U, 0x00000004U}, /*FDT_AXSD02APSP4*/ + [5] = {0xFCB90704U, 0x00000004U}, /*FDT_AXSP02APSP4*/ + [6] = {0xFC070700U, 0x00000005U}, /*FDT_AXVC2APVC1*/ + [7] = {0xFC9D0700U, 0x00000006U}, /*FDT_AXVI12APVI4*/ + [8] = {0xFCF80700U, 0x00000008U}, /*FDT_PCI00*/ + [9] = {0xFCF80710U, 0x00000005U}, /*FDT_AVB0*/ + [10] = {0xFCF80714U, 0x00000005U}, /*FDT_AVB1*/ + [11] = {0xFCF80718U, 0x00000005U}, /*FDT_AVB2*/ + [12] = {0xFCF80720U, 0x00000008U}, /*FDT_PCI01*/ + [13] = {0xFCF80724U, 0x00000008U}, /*FDT_PCI10*/ + [14] = {0xFCF80728U, 0x00000008U}, /*FDT_AXSTM2AXHC0*/ + [15] = {0xFCF8072CU, 0x00000008U}, /*FDT_AXSTM2AXHC1*/ + [16] = {0xFCF80734U, 0x00000008U}, /*FDT_PCI11*/ + [17] = {0xFCF80740U, 0x00000005U}, /*FDT_TSN0*/ + [18] = {0xFF880704U, 0x0000000BU}, /*FDT_FBABUSIR0*/ + [19] = {0xFF880708U, 0x0000000BU}, /*FDT_FBABUSIR1*/ + [20] = {0xFF88070CU, 0x0000000BU}, /*FDT_FBABUSIR2*/ + [21] = {0xFF880710U, 0x0000000BU}, /*FDT_FBABUSIR3*/ + [22] = {0xFF880714U, 0x0000000BU}, /*FDT_FBABUSIR4*/ + [23] = {0xFF88071CU, 0x0000000BU}, /*FDT_IMP0*/ + [24] = {0xFF880720U, 0x0000000BU}, /*FDT_IMP1*/ + [25] = {0xFF880728U, 0x0000000BU}, /*FDT_DSPD*/ + [26] = {0xFF88072CU, 0x0000000BU}, /*FDT_DSPP*/ + [27] = {0xFC610714U, 0x00000008U}, /*FDT_RGX0*/ + [28] = {0xFDC20204U, 0x00000008U}, /*FDT_AXRT2AXRC*/ + [29] = {0xFDC2020CU, 0x00000008U}, /*FDT_DCLS_ICUMX*/ + [30] = {0xFDC20210U, 0x00000008U}, /*FDT_ICUMX*/ + [31] = {0xFDC20704U, 0x00000008U}, /*FDT_CR0*/ + [32] = {0xFD430700U, 0x00000008U}, /*FDT_PERI_RTDM0*/ + [33] = {0xFD430704U, 0x00000008U}, /*FDT_PERI_RTDM1*/ + [34] = {0xFD430708U, 0x00000008U}, /*FDT_PERI_RTDM2*/ + [35] = {0xFD43070CU, 0x00000008U}, /*FDT_PERI_RTDM3*/ + [36] = {0xFD440700U, 0x00000008U}, /*FDT_AXRC2AXRT*/ + [37] = {0xFD440708U, 0x00000008U}, /*FDT_BUS_RTDM0M*/ + [38] = {0xFD44070CU, 0x00000008U}, /*FDT_BUS_RTDM1M*/ + [39] = {0xFD440710U, 0x00000008U}, /*FDT_BUS_RTDM2M*/ + [40] = {0xFD440714U, 0x00000008U}, /*FDT_BUS_RTDM3M*/ + [41] = {0xFD440718U, 0x00000008U}, /*FDT_CR52SS0*/ + [42] = {0xFD44071CU, 0x00000008U}, /*FDT_CSD*/ + [43] = {0xFD440724U, 0x00000008U}, /*FDT_INTAP0*/ + [44] = {0xFD440728U, 0x00000008U}, /*FDT_MEM_RTDM0*/ + [45] = {0xFD44072CU, 0x00000008U}, /*FDT_MEM_RTDM1*/ + [46] = {0xFD440730U, 0x00000008U}, /*FDT_MEM_RTDM2*/ + [47] = {0xFD440734U, 0x00000008U}, /*FDT_MEM_RTDM3*/ + [48] = {0xFD44075CU, 0x00000008U}, /*FDT_CR52SS1*/ + [49] = {0xFD440760U, 0x00000008U}, /*FDT_CR52SS2*/ + [50] = {0xFF860704U, 0x00000008U}, /*FDT_AXRT2AXSC*/ + [51] = {0xFF860708U, 0x00000008U}, /*FDT_AXSM2AXSC*/ + [52] = {0xFF86070CU, 0x00000008U}, /*FDT_AXSN2AXSC*/ + [53] = {0xFF860714U, 0x00000008U}, /*FDT_CCI*/ + [54] = {0xFF860718U, 0x00000008U}, /*FDT_FBABUSTOP0*/ + [55] = {0xFF86071CU, 0x00000008U}, /*FDT_FBABUSTOP1*/ + [56] = {0xFCB80704U, 0x00000006U}, /*FDT_PERI_SYDM1*/ + [57] = {0xFCB80708U, 0x00000006U}, /*FDT_PERI_SYDM2*/ + [58] = {0xFDDC0700U, 0x00000008U}, /*FDT_AXMM2AXSN*/ + [59] = {0xFF800700U, 0x00000008U}, /*FDT_AXIMP02AXSN*/ + [60] = {0xFF800704U, 0x00000008U}, /*FDT_AXSC2AXSN*/ + [61] = {0xFF800708U, 0x00000008U}, /*FDT_AXSP02AXSN*/ + [62] = {0xFF80070CU, 0x00000008U}, /*FDT_AXHC2AXSN*/ + [63] = {0xFCB50708U, 0x00000006U}, /*FDT_BUS_SYDM1*/ + [64] = {0xFCB5070CU, 0x00000006U}, /*FDT_BUS_SYDM2*/ + [65] = {0xFCB50710U, 0x00000004U}, /*FDT_FRAY*/ + [66] = {0xFCB50714U, 0x00000006U}, /*FDT_IPC*/ + [67] = {0xFCB50718U, 0x00000006U}, /*FDT_MEM_SYDM1*/ + [68] = {0xFCB5071CU, 0x00000006U}, /*FDT_MEM_SYDM2*/ + [69] = {0xFCB50720U, 0x00000006U}, /*FDT_SDHI0*/ + [70] = {0xFF810700U, 0x00000008U}, /*FDT_AXMM2AXSTM*/ + [71] = {0xFF810704U, 0x00000008U}, /*FDT_CSDE0*/ + [72] = {0xFF810708U, 0x00000008U}, /*FDT_CSDE1*/ + [73] = {0xFC080704U, 0x00000006U}, /*FDT_FBABUSVC*/ + [74] = {0xFC080708U, 0x0000000AU}, /*FDT_FCPCS*/ + [75] = {0xFC08070CU, 0x0000000AU}, /*FDT_IMR20*/ + [76] = {0xFC080710U, 0x0000000AU}, /*FDT_IMR00*/ + [77] = {0xFC080714U, 0x0000000AU}, /*FDT_IMR01*/ + [78] = {0xFC080718U, 0x0000000AU}, /*FDT_IMR21*/ + [79] = {0xFC080724U, 0x0000000AU}, /*FDT_IMR10*/ + [80] = {0xFC080728U, 0x0000000AU}, /*FDT_IMR11*/ + [81] = {0xFC080740U, 0x0000000AU}, /*FDT_IMS0*/ + [82] = {0xFC080744U, 0x0000000AU}, /*FDT_IMS1*/ + [83] = {0xFC080748U, 0x0000000AU}, /*FDT_IV1ES*/ + [84] = {0xFC9E0700U, 0x00000005U}, /*FDT_DSITXLINK0*/ + [85] = {0xFC9E0704U, 0x00000005U}, /*FDT_DSITXLINK1*/ + [86] = {0xFC9E0708U, 0x00000008U}, /*FDT_FBABUSVIO*/ + [87] = {0xFC9E0714U, 0x00000008U}, /*FDT_FCPVD0*/ + [88] = {0xFC9E0718U, 0x00000008U}, /*FDT_FCPVD1*/ + [89] = {0xFC9E071CU, 0x00000008U}, /*FDT_FCPVX0*/ + [90] = {0xFC9E0720U, 0x00000008U}, /*FDT_FCPVX1*/ + [91] = {0xFC9F0210U, 0x00000008U}, /*FDT_AXVI12AXVI*/ + [92] = {0xFC9F0700U, 0x0000000EU}, /*FDT_ISP02*/ + [93] = {0xFC9F0704U, 0x0000000EU}, /*FDT_ISP03*/ + [94] = {0xFC9F0708U, 0x0000000EU}, /*FDT_ISP04*/ + [95] = {0xFC9F0710U, 0x0000000EU}, /*FDT_VIN0*/ + [96] = {0xFC9F0714U, 0x0000000EU}, /*FDT_VIN1*/ + [97] = {0xFC9F0720U, 0x0000000EU}, /*FDT_ISP00*/ + [98] = {0xFC9F0724U, 0x0000000EU}, /*FDT_ISP01*/ + [99] = {0xFC9F0728U, 0x0000000EU}, /*FDT_ISP10*/ + [100] = {0xFC9F072CU, 0x0000000EU}, /*FDT_ISP11*/ + [101] = {0xFC9F0744U, 0x0000000EU}, /*FDT_ISP12*/ + [102] = {0xFC9F074CU, 0x0000000EU}, /*FDT_ISP13*/ + [103] = {0xFC9F0750U, 0x0000000EU}, /*FDT_ISP14*/ + [104] = {0xFC310704U, 0x00000006U}, /*FDT_FBABUSVIP0*/ + [105] = {0xFC310710U, 0x0000000BU}, /*FDT_SMPO0*/ + [106] = {0xFC310718U, 0x0000000BU}, /*FDT_SMPS0*/ + [107] = {0xFC31071CU, 0x0000000BU}, /*FDT_UMFL0*/ + [108] = {0xFC340700U, 0x0000000BU}, /*FDT_AXVIP02AXVIP1*/ + [109] = {0xFC340718U, 0x0000000BU}, /*FDT_PAP*/ + [110] = {0xFC340728U, 0x00000006U}, /*FDT_FBABUSVIP1*/ + [111] = {0xFC400200U, 0x0000000BU}, /*FDT_AXIMP02AXDSP*/ + [112] = {0xFC400204U, 0x0000000BU}, /*FDT_DSP00*/ + [113] = {0xFC400208U, 0x0000000BU}, /*FDT_DSP01*/ + [114] = {0xFC40020CU, 0x0000000BU}, /*FDT_DSP10*/ + [115] = {0xFC400210U, 0x0000000BU}, /*FDT_DSP11*/ + [116] = {0xFC400214U, 0x0000000BU}, /*FDT_DSP20*/ + [117] = {0xFC400218U, 0x0000000BU}, /*FDT_DSP21*/ + [118] = {0xFC40021CU, 0x0000000BU}, /*FDT_DSP30*/ + [119] = {0xFC400220U, 0x0000000BU}, /*FDT_DSP31*/ +}; + +const CONFIGURATION_SETTING_TABLE g_inten_tbl[INTEN_REG_MAX] = { + [0] = {0xFF8403C0U, 0x00033E4CU}, /* FIXINTENTOP00 */ + [1] = {0xFDA723C0U, 0x00000003U}, /* FIXINTENTOP10 */ + [2] = {0xFF8483C0U, 0x00000007U}, /* FIXINTENTOP20 */ + [3] = {0xFF8443C0U, 0x000000FFU}, /* FIXINTENTOP30 */ + [4] = {0xFDDFC3C0U, 0x000000FAU}, /* FIXINTENMM0 */ + [5] = {0xFD8003C0U, 0x0DFFEFFFU}, /* FIXINTENRT00 */ + [6] = {0xFD8003C4U, 0x00042000U}, /* FIXINTENRT01 */ + [7] = {0xFD8043C0U, 0x000000FFU}, /* FIXINTENRT10 */ + [8] = {0xFD8083C0U, 0x000000FFU}, /* FIXINTENRT20 */ + [9] = {0xFD80C3C0U, 0x00000003U}, /* FIXINTENRT30 */ + [10] = {0xFCB303C0U, 0x001FDFC0U}, /* FIXINTENPER000 */ + [11] = {0xFCB343C0U, 0x0000000FU}, /* FIXINTENPER010 */ + [12] = {0xFCB383C0U, 0x0000000FU}, /* FIXINTENPER020 */ + [13] = {0xFCB3C3C0U, 0x0000000FU}, /* FIXINTENPER030 */ + [14] = {0xFCE903C0U, 0x638353FBU}, /* FIXINTENHSC0 */ + [15] = {0xFCE903C4U, 0x00000000U}, /* FIXINTENHSC1 */ + [16] = {0xFC8F83C0U, 0xB0006660U}, /* FIXINTENVIO00 */ + [17] = {0xFC8F83C4U, 0x00018001U}, /* FIXINTENVIO01 */ + [18] = {0xFC8F03C0U, 0xF980000FU}, /* FIXINTENVIO10 */ + [19] = {0xFC8F03C4U, 0x00000039U}, /* FIXINTENVIO11 */ + [20] = {0xFC8FC3C0U, 0x00000003U}, /* FIXINTENVIO20 */ + [21] = {0xFC0103C0U, 0x7AF6ABABU}, /* FIXINTENVC00 */ + [22] = {0xFC0183C0U, 0x00000003U}, /* FIXINTENVC10 */ + [23] = {0xFF8E03C0U, 0x03C3E00FU}, /* FIXINTENIR0 */ + [24] = {0xFC2F03C0U, 0x0000026FU}, /* FIXINTENVIP00 */ + [25] = {0xFC2F83C0U, 0x000010E1U}, /* FIXINTENVIP10 */ + [26] = {0xFC6403C0U, 0x00000007U}, /* FIXINTEN3DG0 */ + [27] = {0xFC4803C0U, 0x0003FFFFU}, /* FIXINTENDSP0 */ + [28] = {0xFF840440U, 0xC5400001U}, /* EDCINTENTOP00 */ + [29] = {0xFF840444U, 0x81FDBB0FU}, /* EDCINTENTOP01 */ + [30] = {0xFF840448U, 0x0000000FU}, /* EDCINTENTOP02 */ + [31] = {0xFDA72440U, 0xFFDFFFFFU}, /* EDCINTENTOP10 */ + [32] = {0xFDA72444U, 0x003FBFFFU}, /* EDCINTENTOP11 */ + [33] = {0xFF848440U, 0x00000003U}, /* EDCINTENTOP20 */ + [34] = {0xFF844440U, 0x0000003FU}, /* EDCINTENTOP30 */ + [35] = {0xFDDFC440U, 0xFFFFFFFFU}, /* EDCINTENMM0 */ + [36] = {0xFDDFC444U, 0xFFFFFFFFU}, /* EDCINTENMM1 */ + [37] = {0xFDDFC448U, 0xFFFFFFFFU}, /* EDCINTENMM2 */ + [38] = {0xFDDFC44CU, 0xFFFFFFFFU}, /* EDCINTENMM3 */ + [39] = {0xFDDFC450U, 0x03FFFFFFU}, /* EDCINTENMM4 */ + [40] = {0xFD800440U, 0x3F7F87FFU}, /* EDCINTENRT00 */ + [41] = {0xFD800444U, 0x001DF804U}, /* EDCINTENRT01 */ + [42] = {0xFD800448U, 0xFFFFFC2FU}, /* EDCINTENRT02 */ + [43] = {0xFD80044CU, 0xFEF3FFFFU}, /* EDCINTENRT03 */ + [44] = {0xFD800450U, 0x6DFDDFF7U}, /* EDCINTENRT04 */ + [45] = {0xFD800454U, 0xFFC001FFU}, /* EDCINTENRT05 */ + [46] = {0xFD808440U, 0x00007FFFU}, /* EDCINTENRT20 */ + [47] = {0xFD80C440U, 0xFFFFFFFFU}, /* EDCINTENRT30 */ + [48] = {0xFD80C444U, 0x00000003U}, /* EDCINTENRT31 */ + [49] = {0xFCB30440U, 0x80800000U}, /* EDCINTENPER000 */ + [50] = {0xFCB30444U, 0x0000000EU}, /* EDCINTENPER001 */ + [51] = {0xFCB30448U, 0xFFF81E80U}, /* EDCINTENPER002 */ + [52] = {0xFCB3044CU, 0xFFFF03FFU}, /* EDCINTENPER003 */ + [53] = {0xFCB30450U, 0x87F7BFFEU}, /* EDCINTENPER004 */ + [54] = {0xFCB30454U, 0xEC01003FU}, /* EDCINTENPER005 */ + [55] = {0xFCB30458U, 0x2007FFFFU}, /* EDCINTENPER006 */ + [56] = {0xFCB3045CU, 0x00000180U}, /* EDCINTENPER007 */ + [57] = {0xFCB34440U, 0xFFF7E7EAU}, /* EDCINTENPER010 */ + [58] = {0xFCB34444U, 0x0000000FU}, /* EDCINTENPER011 */ + [59] = {0xFCB38440U, 0xFFFFFFFFU}, /* EDCINTENPER020 */ + [60] = {0xFCB3C440U, 0xFFFFFFFFU}, /* EDCINTENPER030 */ + [61] = {0xFCB3C444U, 0xFFFFFFFFU}, /* EDCINTENPER031 */ + [62] = {0xFCB3C448U, 0x0000FFFFU}, /* EDCINTENPER032 */ + [63] = {0xFCE90440U, 0xFF9FFFFFU}, /* EDCINTENHSC0 */ + [64] = {0xFCE90444U, 0x19067733U}, /* EDCINTENHSC1 */ + [65] = {0xFCE90448U, 0xC190607CU}, /* EDCINTENHSC2 */ + [66] = {0xFCE9044CU, 0xA6F8C631U}, /* EDCINTENHSC3 */ + [67] = {0xFCE90450U, 0x11D31923U}, /* EDCINTENHSC4 */ + [68] = {0xFCE90454U, 0x00000001U}, /* EDCINTENHSC5 */ + [69] = {0xFC8F8440U, 0x00FEFFFFU}, /* EDCINTENVIO00 */ + [70] = {0xFC8F8444U, 0x0FFFFFFFU}, /* EDCINTENVIO01 */ + [71] = {0xFC8F8448U, 0x00000000U}, /* EDCINTENVIO02 */ + [72] = {0xFC8F844CU, 0xCCCCC000U}, /* EDCINTENVIO03 */ + [73] = {0xFC8F8450U, 0x070F0CF0U}, /* EDCINTENVIO04 */ + [74] = {0xFC8F8454U, 0xC0000000U}, /* EDCINTENVIO05 */ + [75] = {0xFC8F8458U, 0x007F2080U}, /* EDCINTENVIO06 */ + [76] = {0xFC8F0440U, 0xCF010300U}, /* EDCINTENVIO10 */ + [77] = {0xFC8F0444U, 0xFFFF0000U}, /* EDCINTENVIO11 */ + [78] = {0xFC8F0448U, 0xFFFF0000U}, /* EDCINTENVIO12 */ + [79] = {0xFC8F044CU, 0xE67CFFCCU}, /* EDCINTENVIO13 */ + [80] = {0xFC8F0450U, 0xC927CF3FU}, /* EDCINTENVIO14 */ + [81] = {0xFC8F0454U, 0x1DE3797FU}, /* EDCINTENVIO15 */ + [82] = {0xFC8F0458U, 0x1F800000U}, /* EDCINTENVIO16 */ + [83] = {0xFC8FC440U, 0x000FDFEFU}, /* EDCINTENVIO20 */ + [84] = {0xFC010440U, 0x0011EC01U}, /* EDCINTENVC00 */ + [85] = {0xFC010444U, 0xF3EFCE30U}, /* EDCINTENVC01 */ + [86] = {0xFC010448U, 0xFFFFFE5BU}, /* EDCINTENVC02 */ + [87] = {0xFC01044CU, 0xFFFFFFFFU}, /* EDCINTENVC03 */ + [88] = {0xFC010450U, 0x0000003FU}, /* EDCINTENVC04 */ + [89] = {0xFC018440U, 0x00000FFFU}, /* EDCINTENVC10 */ + [90] = {0xFF8E0440U, 0x00073FFFU}, /* EDCINTENIR0 */ + [91] = {0xFF8E0444U, 0xF983FFD8U}, /* EDCINTENIR1 */ + [92] = {0xFF8E0448U, 0xFFF3FFFFU}, /* EDCINTENIR2 */ + [93] = {0xFF8E044CU, 0x0F8000FFU}, /* EDCINTENIR3 */ + [94] = {0xFC2F0440U, 0x00000177U}, /* EDCINTENVIP00 */ + [95] = {0xFC2F0444U, 0xF3BE0000U}, /* EDCINTENVIP01 */ + [96] = {0xFC2F0448U, 0x001F7BF8U}, /* EDCINTENVIP02 */ + [97] = {0xFC2F044CU, 0x00000000U}, /* EDCINTENVIP03 */ + [98] = {0xFC2F0450U, 0x18000000U}, /* EDCINTENVIP04 */ + [99] = {0xFC2F0454U, 0x0000FBFBU}, /* EDCINTENVIP05 */ + [100] = {0xFC2F8440U, 0xFFE18430U}, /* EDCINTENVIP10 */ + [101] = {0xFC2F8444U, 0xF87C3FF0U}, /* EDCINTENVIP11 */ + [102] = {0xFC2F8448U, 0x00000007U}, /* EDCINTENVIP12 */ + [103] = {0xFC640440U, 0xFBFC07FFU}, /* EDCINTEN3DG0 */ + [104] = {0xFC640444U, 0x0081FC47U}, /* EDCINTEN3DG1 */ + [105] = {0xFC480440U, 0x03FFFFFFU}, /* EDCINTENDSP0 */ + [106] = {0xFF840680U, 0x000F3F82U}, /* ICISTPINTENTOP00 */ + [107] = {0xFDA72680U, 0x00000003U}, /* ICISTPINTENTOP10 */ + [108] = {0xFF848680U, 0x00000007U}, /* ICISTPINTENTOP20 */ + [109] = {0xFF844680U, 0x000000FFU}, /* ICISTPINTENTOP30 */ + [110] = {0xFDDFC680U, 0x000FFFFFU}, /* ICISTPINTENMM0 */ + [111] = {0xFD800680U, 0x0E007FFFU}, /* ICISTPINTENRT00 */ + [112] = {0xFD804680U, 0x000001FFU}, /* ICISTPINTENRT10 */ + [113] = {0xFD808680U, 0x00000007U}, /* ICISTPINTENRT20 */ + [114] = {0xFD80C680U, 0x00000003U}, /* ICISTPINTENRT30 */ + [115] = {0xFCB30680U, 0x00023FF0U}, /* ICISTPINTENPER000 */ + [116] = {0xFCB34680U, 0x0000000FU}, /* ICISTPINTENPER010 */ + [117] = {0xFCB38680U, 0x00000003U}, /* ICISTPINTENPER020 */ + [118] = {0xFCB3C680U, 0x00000003U}, /* ICISTPINTENPER030 */ + [119] = {0xFCE90680U, 0x000001E7U}, /* ICISTPINTENHSC0 */ + [120] = {0xFC8F8680U, 0x00000013U}, /* ICISTPINTENVIO00 */ + [121] = {0xFC8F0680U, 0x0000003FU}, /* ICISTPINTENVIO10 */ + [122] = {0xFC8FC680U, 0x00000003U}, /* ICISTPINTENVIO20 */ + [123] = {0xFC010680U, 0x0000003FU}, /* ICISTPINTENVC00 */ + [124] = {0xFC018680U, 0x00000003U}, /* ICISTPINTENVC10 */ + [125] = {0xFF8E0680U, 0x0000FFC3U}, /* ICISTPINTENIR0 */ + [126] = {0xFC2F0680U, 0x0000001FU}, /* ICISTPINTENVIP00 */ + [127] = {0xFC2F8680U, 0x0000003FU}, /* ICISTPINTENVIP10 */ + [128] = {0xFC640680U, 0x0000000FU}, /* ICISTPINTEN3DG0 */ + [129] = {0xFC480680U, 0x000000FFU}, /* ICISTPINTENDSP0 */ + [130] = {0xFF840580U, 0x0000003CU}, /* DCLSINTENTOP00 */ + [131] = {0xFDA72580U, 0x00000003U}, /* DCLSINTENTOP10 */ + [132] = {0xFF848580U, 0x00000003U}, /* DCLSINTENTOP20 */ + [133] = {0xFF844580U, 0x00000003U}, /* DCLSINTENTOP30 */ + [134] = {0xFDDFC580U, 0x3FFFFFF7U}, /* DCLSINTENMM0 */ + [135] = {0xFDDFC584U, 0x00000080U}, /* DCLSINTENMM1 */ + [136] = {0xFD800580U, 0x01FFFFFFU}, /* DCLSINTENRT00 */ + [137] = {0xFD800584U, 0x0000003EU}, /* DCLSINTENRT01 */ + [138] = {0xFD808580U, 0x0000003FU}, /* DCLSINTENRT20 */ + [139] = {0xFD80C580U, 0x00000003U}, /* DCLSINTENRT30 */ + [140] = {0xFCB30580U, 0x039FFFC0U}, /* DCLSINTENPER000 */ + [141] = {0xFCB34580U, 0x0000000AU}, /* DCLSINTENPER010 */ + [142] = {0xFCB38580U, 0x0000000FU}, /* DCLSINTENPER020 */ + [143] = {0xFCB3C580U, 0x000000FFU}, /* DCLSINTENPER030 */ + [144] = {0xFCE90580U, 0x1FFFC23FU}, /* DCLSINTENHSC0 */ + [145] = {0xFC8F8580U, 0x7207FF0CU}, /* DCLSINTENVIO00 */ + [146] = {0xFC8F0580U, 0x0DFBC03FU}, /* DCLSINTENVIO10 */ + [147] = {0xFC8FC580U, 0x00000003U}, /* DCLSINTENVIO20 */ + [148] = {0xFC010580U, 0x03FAF7E7U}, /* DCLSINTENVC00 */ + [149] = {0xFC018580U, 0x00000003U}, /* DCLSINTENVC10 */ + [150] = {0xFF8E0580U, 0x0FFF9F60U}, /* DCLSINTENIR0 */ + [151] = {0xFC2F0580U, 0xE00003E7U}, /* DCLSINTENVIP00 */ + [152] = {0xFC2F0584U, 0x0000003FU}, /* DCLSINTENVIP01 */ + [153] = {0xFC2F8580U, 0x00000C3FU}, /* DCLSINTENVIP10 */ + [154] = {0xFC480580U, 0x00000003U}, /* DCLSINTENDSP0 */ + [155] = {0xFF840480U, 0xF99F00F0U}, /* LSCHKINTENTOP00 */ + [156] = {0xFF840484U, 0x0003E67FU}, /* LSCHKINTENTOP01 */ + [157] = {0xFDA72480U, 0x00000003U}, /* LSCHKINTENTOP10 */ + [158] = {0xFF848480U, 0x0000001FU}, /* LSCHKINTENTOP20 */ + [159] = {0xFF844480U, 0x000FFFFFU}, /* LSCHKINTENTOP30 */ + [160] = {0xFDDFC480U, 0xFFFFFFFFU}, /* LSCHKINTENMM0 */ + [161] = {0xFDDFC484U, 0x000003FFU}, /* LSCHKINTENMM1 */ + [162] = {0xFD800480U, 0x7FFFFF7FU}, /* LSCHKINTENRT00 */ + [163] = {0xFD800484U, 0x001FFFFFU}, /* LSCHKINTENRT01 */ + [164] = {0xFD800488U, 0x04C4C000U}, /* LSCHKINTENRT02 */ + [165] = {0xFD804480U, 0x003FC7F8U}, /* LSCHKINTENRT10 */ + [166] = {0xFD808480U, 0x000003FFU}, /* LSCHKINTENRT20 */ + [167] = {0xFD80C480U, 0x00000003U}, /* LSCHKINTENRT30 */ + [168] = {0xFCB30480U, 0xDFFFDF00U}, /* LSCHKINTENPER000 */ + [169] = {0xFCB30484U, 0x00000CFFU}, /* LSCHKINTENPER001 */ + [170] = {0xFCB34480U, 0x000000FFU}, /* LSCHKINTENPER010 */ + [171] = {0xFCB38480U, 0x0000000FU}, /* LSCHKINTENPER020 */ + [172] = {0xFCB3C480U, 0x0000000FU}, /* LSCHKINTENPER030 */ + [173] = {0xFCE90480U, 0x1F863FFFU}, /* LSCHKINTENHSC0 */ + [174] = {0xFCE90484U, 0x00000C3CU}, /* LSCHKINTENHSC1 */ + [175] = {0xFC8F8480U, 0xF99F333FU}, /* LSCHKINTENVIO00 */ + [176] = {0xFC8F8484U, 0x000E0403U}, /* LSCHKINTENVIO01 */ + [177] = {0xFC8F0480U, 0xE0040003U}, /* LSCHKINTENVIO10 */ + [178] = {0xFC8F0484U, 0x0031F3FCU}, /* LSCHKINTENVIO11 */ + [179] = {0xFC8FC480U, 0x00000003U}, /* LSCHKINTENVIO20 */ + [180] = {0xFC010480U, 0x7EF0ABABU}, /* LSCHKINTENVC00 */ + [181] = {0xFC010484U, 0x00000FDFU}, /* LSCHKINTENVC01 */ + [182] = {0xFC018480U, 0x00000003U}, /* LSCHKINTENVC10 */ + [183] = {0xFF8E0480U, 0x403FF00FU}, /* LSCHKINTENIR0 */ + [184] = {0xFF8E0484U, 0x003F3FFFU}, /* LSCHKINTENIR1 */ + [185] = {0xFC2F0480U, 0x000176DFU}, /* LSCHKINTENVIP00 */ + [186] = {0xFC2F0484U, 0x00060000U}, /* LSCHKINTENVIP01 */ + [187] = {0xFC2F8480U, 0x001C3F87U}, /* LSCHKINTENVIP10 */ + [188] = {0xFC640480U, 0x0000063FU}, /* LSCHKINTEN3DG0 */ + [189] = {0xFC480480U, 0x3FFFFFFFU}, /* LSCHKINTENDSP0 */ + [190] = {0xFF840700U, 0x0000001EU}, /* OTHINTENTOP00 */ + [191] = {0xFDDFC700U, 0x008FCFFFU}, /* OTHINTENMM0 */ + [192] = {0xFD800700U, 0x00FFFFF0U}, /* OTHINTENRT00 */ + [193] = {0xFCB30700U, 0x0000003CU}, /* OTHINTENPER000 */ + [194] = {0xFCE90700U, 0x0000003CU}, /* OTHINTENHSC0 */ + [195] = {0xFC8F8700U, 0x00000000U}, /* OTHINTENVIO00 */ + [196] = {0xFC8F0700U, 0x0000007CU}, /* OTHINTENVIO10 */ + [197] = {0xFC010700U, 0x000000F0U}, /* OTHINTENVC00 */ + [198] = {0xFC018700U, 0x00000000U}, /* OTHINTENVC10 */ + [199] = {0xFF8E0700U, 0x000000F0U}, /* OTHINTENIR0 */ + [200] = {0xFC2F0700U, 0x00000FC0U}, /* OTHINTENVIP00 */ + [201] = {0xFC2F8700U, 0x00000000U}, /* OTHINTENVIP10 */ + [202] = {0xFC640700U, 0x00000024U}, /* OTHINTEN3DG0 */ + [203] = {0xFF840400U, 0xC5000071U}, /* ROUINTENTOP00 */ + [204] = {0xFF840404U, 0xC8FFE7CFU}, /* ROUINTENTOP01 */ + [205] = {0xFF840408U, 0x8000F3E7U}, /* ROUINTENTOP02 */ + [206] = {0xFDA72400U, 0xFFFFFFFFU}, /* ROUINTENTOP10 */ + [207] = {0xFDA72404U, 0x003FFFFFU}, /* ROUINTENTOP11 */ + [208] = {0xFF848400U, 0x00000007U}, /* ROUINTENTOP20 */ + [209] = {0xFF844400U, 0x003FFFFFU}, /* ROUINTENTOP30 */ + [210] = {0xFDDFC400U, 0xFFFFFFFFU}, /* ROUINTENMM0 */ + [211] = {0xFDDFC404U, 0xFFFFFFFFU}, /* ROUINTENMM1 */ + [212] = {0xFDDFC408U, 0xFFFFFFFFU}, /* ROUINTENMM2 */ + [213] = {0xFDDFC40CU, 0x01FFFFFFU}, /* ROUINTENMM3 */ + [214] = {0xFD800400U, 0x007F3FEFU}, /* ROUINTENRT00 */ + [215] = {0xFD800404U, 0x40000040U}, /* ROUINTENRT01 */ + [216] = {0xFD800408U, 0x7BFFFBFFU}, /* ROUINTENRT02 */ + [217] = {0xFD80040CU, 0xFFFFFFFFU}, /* ROUINTENRT03 */ + [218] = {0xFD800410U, 0x6C007F87U}, /* ROUINTENRT04 */ + [219] = {0xFD800414U, 0xFFFFFFFFU}, /* ROUINTENRT05 */ + [220] = {0xFD800418U, 0x05FFFFFFU}, /* ROUINTENRT06 */ + [221] = {0xFD804400U, 0x001FFFFFU}, /* ROUINTENRT10 */ + [222] = {0xFD808400U, 0x000003FFU}, /* ROUINTENRT20 */ + [223] = {0xFD80C400U, 0xFFFFFFFFU}, /* ROUINTENRT30 */ + [224] = {0xFD80C404U, 0x00000003U}, /* ROUINTENRT31 */ + [225] = {0xFCB30400U, 0x00800000U}, /* ROUINTENPER000 */ + [226] = {0xFCB30404U, 0x00000000U}, /* ROUINTENPER001 */ + [227] = {0xFCB30408U, 0xFFF81C80U}, /* ROUINTENPER002 */ + [228] = {0xFCB3040CU, 0xC7F1FFFFU}, /* ROUINTENPER003 */ + [229] = {0xFCB30410U, 0x020FFFFFU}, /* ROUINTENPER004 */ + [230] = {0xFCB30414U, 0xFFBDE010U}, /* ROUINTENPER005 */ + [231] = {0xFCB30418U, 0x01003FFFU}, /* ROUINTENPER006 */ + [232] = {0xFCB3041CU, 0x0000005EU}, /* ROUINTENPER007 */ + [233] = {0xFCB34400U, 0xFFF7FF7EU}, /* ROUINTENPER010 */ + [234] = {0xFCB34404U, 0x0000003FU}, /* ROUINTENPER011 */ + [235] = {0xFCB38400U, 0x0FFFFFFFU}, /* ROUINTENPER020 */ + [236] = {0xFCB3C400U, 0xFFFFFFFFU}, /* ROUINTENPER030 */ + [237] = {0xFCB3C404U, 0xFFFFFFFFU}, /* ROUINTENPER031 */ + [238] = {0xFCB3C408U, 0x000000FFU}, /* ROUINTENPER032 */ + [239] = {0xFCE90400U, 0xFFE1D3FFU}, /* ROUINTENHSC0 */ + [240] = {0xFCE90404U, 0x00106001U}, /* ROUINTENHSC1 */ + [241] = {0xFCE90408U, 0xFFFB9906U}, /* ROUINTENHSC2 */ + [242] = {0xFCE9040CU, 0x7C1F07F9U}, /* ROUINTENHSC3 */ + [243] = {0xFCE90410U, 0x00000CFFU}, /* ROUINTENHSC4 */ + [244] = {0xFC8F8400U, 0xDFFFE1FFU}, /* ROUINTENVIO00 */ + [245] = {0xFC8F8404U, 0x00001003U}, /* ROUINTENVIO01 */ + [246] = {0xFC8F8408U, 0xF8000000U}, /* ROUINTENVIO02 */ + [247] = {0xFC8F840CU, 0x1E18007FU}, /* ROUINTENVIO03 */ + [248] = {0xFC8F8410U, 0xE0786200U}, /* ROUINTENVIO04 */ + [249] = {0xFC8F8414U, 0x0000000FU}, /* ROUINTENVIO05 */ + [250] = {0xFC8F8418U, 0xFFFE0002U}, /* ROUINTENVIO06 */ + [251] = {0xFC8F0400U, 0x200007CFU}, /* ROUINTENVIO10 */ + [252] = {0xFC8F0404U, 0xCF3FE1CEU}, /* ROUINTENVIO11 */ + [253] = {0xFC8F0408U, 0x000079E7U}, /* ROUINTENVIO12 */ + [254] = {0xFC8F040CU, 0x00000000U}, /* ROUINTENVIO13 */ + [255] = {0xFC8F0410U, 0x3C000000U}, /* ROUINTENVIO14 */ + [256] = {0xFC8F0414U, 0x0F038000U}, /* ROUINTENVIO15 */ + [257] = {0xFC8F0418U, 0x0000001CU}, /* ROUINTENVIO16 */ + [258] = {0xFC8FC400U, 0x0003F7FBU}, /* ROUINTENVIO20 */ + [259] = {0xFC010400U, 0x40000000U}, /* ROUINTENVC00 */ + [260] = {0xFC010404U, 0x38001860U}, /* ROUINTENVC01 */ + [261] = {0xFC010408U, 0xF9C003BFU}, /* ROUINTENVC02 */ + [262] = {0xFC01040CU, 0xFFFFF3FFU}, /* ROUINTENVC03 */ + [263] = {0xFC010410U, 0x000001FFU}, /* ROUINTENVC04 */ + [264] = {0xFC018400U, 0x000003FFU}, /* ROUINTENVC10 */ + [265] = {0xFF8E0400U, 0x803F1FC1U}, /* ROUINTENIR0 */ + [266] = {0xFF8E0404U, 0x087E821FU}, /* ROUINTENIR1 */ + [267] = {0xFF8E0408U, 0xFFFF0FC2U}, /* ROUINTENIR2 */ + [268] = {0xFF8E040CU, 0x000001FFU}, /* ROUINTENIR3 */ + [269] = {0xFC2F0400U, 0xF00101E1U}, /* ROUINTENVIP00 */ + [270] = {0xFC2F0404U, 0xBC07C007U}, /* ROUINTENVIP01 */ + [271] = {0xFC2F0408U, 0x00EE97E1U}, /* ROUINTENVIP02 */ + [272] = {0xFC2F040CU, 0x00000000U}, /* ROUINTENVIP03 */ + [273] = {0xFC2F0410U, 0x00000000U}, /* ROUINTENVIP04 */ + [274] = {0xFC2F0414U, 0x01F80000U}, /* ROUINTENVIP05 */ + [275] = {0xFC2F8400U, 0x07FFFFFFU}, /* ROUINTENVIP10 */ + [276] = {0xFC2F8404U, 0x3FFFF03FU}, /* ROUINTENVIP11 */ + [277] = {0xFC640400U, 0x03FC03FFU}, /* ROUINTEN3DG0 */ + [278] = {0xFC640404U, 0x000007FFU}, /* ROUINTEN3DG1 */ + [279] = {0xFC480400U, 0xFFFFFFFFU}, /* ROUINTENDSP0 */ + [280] = {0xFF840500U, 0xC0FEEFFFU}, /* RSCHKINTENTOP00 */ + [281] = {0xFF840504U, 0x603F99FFU}, /* RSCHKINTENTOP01 */ + [282] = {0xFF840508U, 0x0001C000U}, /* RSCHKINTENTOP02 */ + [283] = {0xFDA72500U, 0x00000001U}, /* RSCHKINTENTOP10 */ + [284] = {0xFF848500U, 0x0000001FU}, /* RSCHKINTENTOP20 */ + [285] = {0xFF844500U, 0x00003FFFU}, /* RSCHKINTENTOP30 */ + [286] = {0xFDDFC500U, 0xFFFFFFFFU}, /* RSCHKINTENMM0 */ + [287] = {0xFDDFC504U, 0x00000007U}, /* RSCHKINTENMM1 */ + [288] = {0xFD800500U, 0xFFFFFFFFU}, /* RSCHKINTENRT00 */ + [289] = {0xFD800504U, 0xFFFF8001U}, /* RSCHKINTENRT01 */ + [290] = {0xFD800508U, 0x0000FFE3U}, /* RSCHKINTENRT02 */ + [291] = {0xFD804500U, 0x000007FFU}, /* RSCHKINTENRT10 */ + [292] = {0xFD808500U, 0x000000FFU}, /* RSCHKINTENRT20 */ + [293] = {0xFD80C500U, 0x00000001U}, /* RSCHKINTENRT30 */ + [294] = {0xFCB30500U, 0xFFF10F07U}, /* RSCHKINTENPER000 */ + [295] = {0xFCB30504U, 0x000FBCFFU}, /* RSCHKINTENPER001 */ + [296] = {0xFCB34500U, 0x000000FAU}, /* RSCHKINTENPER010 */ + [297] = {0xFCB38500U, 0x00000003U}, /* RSCHKINTENPER020 */ + [298] = {0xFCB3C500U, 0x0000003FU}, /* RSCHKINTENPER030 */ + [299] = {0xFCE90500U, 0xF3F3FFFFU}, /* RSCHKINTENHSC0 */ + [300] = {0xFCE90504U, 0x001FFFFFU}, /* RSCHKINTENHSC1 */ + [301] = {0xFC8F8500U, 0xFFFFC003U}, /* RSCHKINTENVIO00 */ + [302] = {0xFC8F8504U, 0x3801C03FU}, /* RSCHKINTENVIO01 */ + [303] = {0xFC8F0500U, 0xFF7F3FFFU}, /* RSCHKINTENVIO10 */ + [304] = {0xFC8F0504U, 0x041A001EU}, /* RSCHKINTENVIO11 */ + [305] = {0xFC8FC500U, 0x00000007U}, /* RSCHKINTENVIO20 */ + [306] = {0xFC010500U, 0xFEBB6627U}, /* RSCHKINTENVC00 */ + [307] = {0xFC010504U, 0x000007FFU}, /* RSCHKINTENVC01 */ + [308] = {0xFC018500U, 0x00000007U}, /* RSCHKINTENVC10 */ + [309] = {0xFF8E0500U, 0x3FFFFE00U}, /* RSCHKINTENIR0 */ + [310] = {0xFF8E0504U, 0x0000FFFFU}, /* RSCHKINTENIR1 */ + [311] = {0xFC2F0500U, 0x0000FFFFU}, /* RSCHKINTENVIP00 */ + [312] = {0xFC2F0504U, 0x000FF800U}, /* RSCHKINTENVIP01 */ + [313] = {0xFC2F8500U, 0x000FFFFFU}, /* RSCHKINTENVIP10 */ + [314] = {0xFC640500U, 0x000001C7U}, /* RSCHKINTEN3DG0 */ + [315] = {0xFC480500U, 0x0001FFFFU}, /* RSCHKINTENDSP0 */ + [316] = {0xFF840540U, 0x00000003U}, /* TIDINTENTOP00 */ + [317] = {0xFF848540U, 0x00000007U}, /* TIDINTENTOP20 */ + [318] = {0xFDDFC540U, 0x00003FFFU}, /* TIDINTENMM0 */ + [319] = {0xFD800540U, 0x007FFF7FU}, /* TIDINTENRT00 */ + [320] = {0xFD800544U, 0x00000020U}, /* TIDINTENRT01 */ + [321] = {0xFD804540U, 0x000000FFU}, /* TIDINTENRT10 */ + [322] = {0xFD808540U, 0x0000003FU}, /* TIDINTENRT20 */ + [323] = {0xFCB30540U, 0x0003FFF0U}, /* TIDINTENPER000 */ + [324] = {0xFCB34540U, 0x0000000FU}, /* TIDINTENPER010 */ + [325] = {0xFCE90540U, 0x0638367FU}, /* TIDINTENHSC0 */ + [326] = {0xFC8F8540U, 0xFFF0CFC3U}, /* TIDINTENVIO00 */ + [327] = {0xFC8F8544U, 0x00000003U}, /* TIDINTENVIO01 */ + [328] = {0xFC8F0540U, 0x3C000000U}, /* TIDINTENVIO10 */ + [329] = {0xFC8F0544U, 0x0000003FU}, /* TIDINTENVIO11 */ + [330] = {0xFC010540U, 0x3B77EFD0U}, /* TIDINTENVC00 */ + [331] = {0xFF8E0540U, 0x00FC1F60U}, /* TIDINTENIR0 */ + [332] = {0xFC2F0540U, 0x0000036DU}, /* TIDINTENVIP00 */ + [333] = {0xFC2F8540U, 0x00000610U}, /* TIDINTENVIP10 */ + [334] = {0xFC640540U, 0x00000003U}, /* TIDINTEN3DG0 */ + [335] = {0xFC480540U, 0x00000000U}, /* TIDINTENDSP0 */ + [336] = {0xFF840640U, 0x00000001U}, /* SAFERRINTENTOP00 */ + [337] = {0xFDA72640U, 0x00000001U}, /* SAFERRINTENTOP10 */ + [338] = {0xFF848640U, 0x00000000U}, /* SAFERRINTENTOP20 */ + [339] = {0xFF844640U, 0x00000001U}, /* SAFERRINTENTOP30 */ + [340] = {0xFDDFC640U, 0x00000007U}, /* SAFERRINTENMM0 */ + [341] = {0xFD800640U, 0x0000001DU}, /* SAFERRINTENRT00 */ + [342] = {0xFD804640U, 0x00000001U}, /* SAFERRINTENRT10 */ + [343] = {0xFD808640U, 0x00000001U}, /* SAFERRINTENRT20 */ + [344] = {0xFD80C640U, 0x00000001U}, /* SAFERRINTENRT30 */ + [345] = {0xFCB30640U, 0x00000004U}, /* SAFERRINTENPER000 */ + [346] = {0xFCB34640U, 0x00000001U}, /* SAFERRINTENPER010 */ + [347] = {0xFCB38640U, 0x00000001U}, /* SAFERRINTENPER020 */ + [348] = {0xFCB3C640U, 0x00000001U}, /* SAFERRINTENPER030 */ + [349] = {0xFCE90640U, 0x00000001U}, /* SAFERRINTENHSC0 */ + [350] = {0xFC8F8640U, 0x00000001U}, /* SAFERRINTENVIO00 */ + [351] = {0xFC8F0640U, 0x00000002U}, /* SAFERRINTENVIO10 */ + [352] = {0xFC8FC640U, 0x00000001U}, /* SAFERRINTENVIO20 */ + [353] = {0xFC010640U, 0x00000001U}, /* SAFERRINTENVC00 */ + [354] = {0xFC018640U, 0x00000001U}, /* SAFERRINTENVC10 */ + [355] = {0xFF8E0640U, 0x00000001U}, /* SAFERRINTENIR0 */ + [356] = {0xFC2F0640U, 0x00000001U}, /* SAFERRINTENVIP00 */ + [357] = {0xFC2F8640U, 0x00000001U}, /* SAFERRINTENVIP10 */ + [358] = {0xFC640640U, 0x00000001U}, /* SAFERRINTEN3DG0 */ + [359] = {0xFC480640U, 0x00000001U}, /* SAFERRINTENDSP0 */ + [360] = {0xFF8404C0U, 0x0000007BU}, /* WCRCINTENTOP00 */ + [361] = {0xFDDFC4C0U, 0x07FFFFFFU}, /* WCRCINTENMM0 */ + [362] = {0xFD8004C0U, 0x607FFFFBU}, /* WCRCINTENRT00 */ + [363] = {0xFD8004C4U, 0x0000001CU}, /* WCRCINTENRT01 */ + [364] = {0xFD8044C0U, 0x0000078FU}, /* WCRCINTENRT10 */ + [365] = {0xFD8084C0U, 0x00000001U}, /* WCRCINTENRT20 */ + [366] = {0xFCB304C0U, 0x000037FFU}, /* WCRCINTENPER000 */ + [367] = {0xFCB344C0U, 0x00000003U}, /* WCRCINTENPER010 */ + [368] = {0xFCE904C0U, 0x000FC1ECU}, /* WCRCINTENHSC0 */ + [369] = {0xFC8F84C0U, 0x0000FFC3U}, /* WCRCERRINTENVIO00 */ + [370] = {0xFC8F04C0U, 0x001FC40FU}, /* WCRCERRINTENVIO10 */ + [371] = {0xFC0104C0U, 0x00357D7DU}, /* WCRCERRINTENVC00 */ + [372] = {0xFF8E04C0U, 0x3FFF03F0U}, /* WCRCERRINTENIR0 */ + [373] = {0xFC2F04C0U, 0x070030F5U}, /* WCRCERRINTENVIP00 */ + [374] = {0xFC2F84C0U, 0x000000F0U}, /* WCRCERRINTENVIP10 */ + [375] = {0xFC6404C0U, 0x00000063U}, /* WCRCERRINTEN3DG0 */ + [376] = {0xFC4804C0U, 0x3FFF03F0U}, /* WCRCINTENDSP0 */ + [377] = {0xFF840600U, 0x00000001U}, /* SECERRINTENTOP00 */ + [378] = {0xFDA72600U, 0x00000001U}, /* SECERRINTENTOP10 */ + [379] = {0xFF848600U, 0x00000000U}, /* SECERRINTENTOP20 */ + [380] = {0xFF844600U, 0x00000001U}, /* SECERRINTENTOP30 */ + [381] = {0xFDDFC600U, 0x00000007U}, /* SECERRINTENMM0 */ + [382] = {0xFD800600U, 0x0000001DU}, /* SECERRINTENRT00 */ + [383] = {0xFD804600U, 0x00000001U}, /* SECERRINTENRT10 */ + [384] = {0xFD808600U, 0x00000001U}, /* SECERRINTENRT20 */ + [385] = {0xFD80C600U, 0x00000001U}, /* SECERRINTENRT30 */ + [386] = {0xFCB30600U, 0x00000004U}, /* SECERRINTENPER000 */ + [387] = {0xFCB34600U, 0x00000001U}, /* SECERRINTENPER010 */ + [388] = {0xFCB38600U, 0x00000001U}, /* SECERRINTENPER020 */ + [389] = {0xFCB3C600U, 0x00000001U}, /* SECERRINTENPER030 */ + [390] = {0xFCE90600U, 0x00000001U}, /* SECERRINTENHSC0 */ + [391] = {0xFC8F8600U, 0x00000001U}, /* SECERRINTENVIO00 */ + [392] = {0xFC8F0600U, 0x00000002U}, /* SECERRINTENVIO10 */ + [393] = {0xFC8FC600U, 0x00000001U}, /* SECERRINTENVIO20 */ + [394] = {0xFC010600U, 0x00000001U}, /* SECERRINTENVC00 */ + [395] = {0xFC018600U, 0x00000001U}, /* SECERRINTENVC10 */ + [396] = {0xFF8E0600U, 0x00007FFFU}, /* SECERRINTENIR0 */ + [397] = {0xFC2F0600U, 0x00000001U}, /* SECERRINTENVIP00 */ + [398] = {0xFC2F8600U, 0x00000001U}, /* SECERRINTENVIP10 */ + [399] = {0xFC640600U, 0x00000001U}, /* SECERRINTEN3DG0 */ + [400] = {0xFC480600U, 0x00000001U}, /* SECERRINTENDSP0 */ +}; + +const REGION_ID_SETTING_TABLE g_imp_rgid_m_tbl[IMP_MASTER_MAX] = { + [0] = {0xFFA8E270U, 0x00010202U}, /* SPMI BMATTR00 */ + [1] = {0xFFA8E274U, 0x00010202U}, /* SPMI BMATTR01 */ + [2] = {0xFFA8E278U, 0x00010202U}, /* SPMI BMATTR02 */ + [3] = {0xFFA8E27CU, 0x00010202U}, /* SPMI BMATTR03 */ + [4] = {0xFFA8E280U, 0x00010202U}, /* SPMI BMATTR04 */ + [5] = {0xFFA8E284U, 0x00010202U}, /* SPMI BMATTR05 */ + [6] = {0xFFA8E288U, 0x00010202U}, /* SPMI BMATTR06 */ + [7] = {0xFFA8E28CU, 0x00010202U}, /* SPMI BMATTR07 */ + [8] = {0xFFA8E290U, 0x00010202U}, /* SPMI BMATTR08 */ + [9] = {0xFFA8E294U, 0x00010202U}, /* SPMI BMATTR09 */ + [10] = {0xFFA8E298U, 0x00010202U}, /* SPMI BMATTR10 */ + [11] = {0xFFA8E29CU, 0x00010202U}, /* SPMI BMATTRSP0 */ + [12] = {0xFFAB2270U, 0x00010202U}, /* SPMC BMATTR00 */ + [13] = {0xFFAB2274U, 0x00010202U}, /* SPMC BMATTR01 */ + [14] = {0xFFAB2278U, 0x00010202U}, /* SPMC BMATTR02 */ + [15] = {0xFFAB227CU, 0x00010202U}, /* SPMC BMATTR03 */ + [16] = {0xFFAB2280U, 0x00010202U}, /* SPMC BMATTR04 */ + [17] = {0xFFAB2284U, 0x00010202U}, /* SPMC BMATTR05 */ + [18] = {0xFFAB2288U, 0x00010202U}, /* SPMC BMATTR06 */ +}; + +const REGION_ID_SETTING_TABLE g_imp_rgid_s_tbl[IMP_SLAVE_MAX] = { + [0] = {0xFF902100U, 0x004E004FU}, /* IMPSLV RCR0 */ + [1] = {0xFF902108U, 0x004E004FU}, /* IMPSLV RCR2 */ + [2] = {0xFFAB2100U, 0x004E004FU}, /* SPMC RCR0 */ + [3] = {0xFFAB2110U, 0x004E004FU}, /* SPMC RC00 */ + [4] = {0xFFAB2114U, 0x004E004FU}, /* SPMC RC01 */ + [5] = {0xFFAB2118U, 0x004E004FU}, /* SPMC RC02 */ + [6] = {0xFFAB2200U, 0x004E004FU}, /* SPMC RCB0 */ + [7] = {0xFFAB2204U, 0x004E004FU}, /* SPMC RCB1 */ + [8] = {0xFFAB2208U, 0x004E004FU}, /* SPMC RCB2 */ + [9] = {0xFFAB220CU, 0x004E004FU}, /* SPMC RCB3 */ + [10] = {0xFFAB2210U, 0x004E004FU}, /* SPMC RCB4 */ + [11] = {0xFFAB2104U, 0x004E004FU}, /* SPMC RCR1 */ + [12] = {0xFFA8E100U, 0x004E004FU}, /* SPMI RCR0 */ + [13] = {0xFFA8E110U, 0x004E004FU}, /* SPMI RC00 */ + [14] = {0xFFA8E114U, 0x004E004FU}, /* SPMI RC01 */ + [15] = {0xFFA8E118U, 0x004E004FU}, /* SPMI RC02 */ + [16] = {0xFFA8E11CU, 0x004E004FU}, /* SPMI RC03 */ + [17] = {0xFFA8E120U, 0x004E004FU}, /* SPMI RC04 */ + [18] = {0xFFA8E124U, 0x004E004FU}, /* SPMI RC05 */ + [19] = {0xFFA8E128U, 0x004E004FU}, /* SPMI RC06 */ + [20] = {0xFFA8E12CU, 0x004E004FU}, /* SPMI RC07 */ + [21] = {0xFFA8E130U, 0x004E004FU}, /* SPMI RC08 */ + [22] = {0xFFA8E134U, 0x004E004FU}, /* SPMI RC09 */ + [23] = {0xFFA8E138U, 0x004E004FU}, /* SPMI RC10 */ + [24] = {0xFFA8E13CU, 0x004E004FU}, /* SPMI RC11 */ + [25] = {0xFFA8E140U, 0x004E004FU}, /* SPMI RC12 */ + [26] = {0xFFA8E144U, 0x004E004FU}, /* SPMI RC13 */ + [27] = {0xFFA8E200U, 0x004E004FU}, /* SPMI RCB0 */ + [28] = {0xFFA8E204U, 0x004E004FU}, /* SPMI RCB1 */ + [29] = {0xFFA8E208U, 0x004E004FU}, /* SPMI RCB2 */ + [30] = {0xFFA8E20CU, 0x004E004FU}, /* SPMI RCB3 */ + [31] = {0xFFA8E210U, 0x004E004FU}, /* SPMI RCB4 */ + [32] = {0xFFA8E214U, 0x004E004FU}, /* SPMI RCB5 */ + [33] = {0xFFA8E218U, 0x004E004FU}, /* SPMI RCB6 */ + [34] = {0xFFA8E21CU, 0x004E004FU}, /* SPMI RCB7 */ + [35] = {0xFFA8E104U, 0x004E004FU}, /* SPMI RCR1 */ + [36] = {0xFF902110U, 0x004E004FU}, /* IMPSLV RC00 */ + [37] = {0xFF902104U, 0x004E004FU}, /* IMPSLV RCR1 */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX] = { + [0] = {0xFC480570U, 0x00000002U}, /* IMRGID_IPMMU_VI0 */ + [1] = {0xFC4C0570U, 0x00000002U}, /* IMRGID_IPMMU_VI1 */ + [2] = {0xFC3C0570U, 0x00000002U}, /* IMRGID_IPMMU_VC0 */ + [3] = {0xFC380570U, 0x00000002U}, /* IMRGID_IPMMU_IR */ + [4] = {0xFC080570U, 0x00000001U}, /* IMRGID_IPMMU_RT0 */ + [5] = {0xFC0C0570U, 0x00000001U}, /* IMRGID_IPMMU_RT1 */ + [6] = {0xFC300570U, 0x00000001U}, /* IMRGID_IPMMU_DS0 */ + [7] = {0xFC340570U, 0x00000001U}, /* IMRGID_IPMMU_HSC */ + [8] = {0xFC500570U, 0x00000002U}, /* IMRGID_IPMMU_VIP0 */ + [9] = {0xFC540570U, 0x00000002U}, /* IMRGID_IPMMU_VIP1 */ + [10] = {0xFC400570U, 0x00000002U}, /* IMRGID_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX] = { + [0] = {0xFC480578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI0 */ + [1] = {0xFC4C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI1 */ + [2] = {0xFC3C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VC0 */ + [3] = {0xFC380578U, 0x00000001U}, /* IMSECGRP_IPMMU_IR */ + [4] = {0xFC080578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT0 */ + [5] = {0xFC0C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT1 */ + [6] = {0xFC300578U, 0x00000001U}, /* IMSECGRP_IPMMU_DS0 */ + [7] = {0xFC340578U, 0x00000001U}, /* IMSECGRP_IPMMU_HSC */ + [8] = {0xFC500578U, 0x00000001U}, /* IMSECGRP_IPMMU_VIP0 */ + [9] = {0xFC540578U, 0x00000001U}, /* IMSECGRP_IPMMU_VIP1 */ + [10] = {0xFC400578U, 0x00000001U}, /* IMSECGRP_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX] = { + [0] = {0xFC480574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI0 */ + [1] = {0xFC4C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI1 */ + [2] = {0xFC3C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VC0 */ + [3] = {0xFC380574U, 0x00000002U}, /* IMRGIDEN_IPMMU_IR */ + [4] = {0xFC080574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT0 */ + [5] = {0xFC0C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT1 */ + [6] = {0xFC300574U, 0x00000002U}, /* IMRGIDEN_IPMMU_DS0 */ + [7] = {0xFC340574U, 0x00000002U}, /* IMRGIDEN_IPMMU_HSC */ + [8] = {0xFC500574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VIP0 */ + [9] = {0xFC540574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VIP1 */ + [10] = {0xFC400574U, 0x00000002U}, /* IMRGIDEN_IPMMU_3DG */ +}; + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4m.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4m.c new file mode 100644 index 0000000..87abef8 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4m.c @@ -0,0 +1,3552 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table + ******************************************************************************/ +/****************************************************************************** + * @file cnf_tbl_v4m.c + * - Version : 0.12 + * @brief Configuration table for V4M. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + * : 19.09.2023 0.02 Update setting table according to + * HWUM Rev.0.50. + * : 10.10.2023 0.03 Removed unimplemented registers. + * : 13.11.2023 0.04 Added setting table for CCI MPU GID register. + * : 11.01.2024 0.05 Updated writing privilege to System RAM. + * Fixed setting value of read/write permissions + * for RT-VRAM1 area2. + * Update Region ID settings. + * The divided areas of SDRAM have been changed. + * : 17.07.2024 0.06 Removed FDT_PAP in g_fdt_tbl. + * : 11.10.2024 0.07 Updated Region ID and RAM protection setting + * for QNX. + * : 12.11.2024 0.08 Updated AXI timeout setting value. + * : 05.12.2024 0.09 Update RAM protection settings for ICCOM + * memory area (SDRAM Area5). + * Update Region ID settings for VSPD and VSPX. + * Update Region ID settings for IPMMU. + * : 16.12.2024 0.10 Updated Region ID setting. + * Updated Region ID setting and RAM protection + * setting for booting CR52 3 cores. + * Updated AXI timeout setting value. + * Update Region ID settings for ISP ch1. + * Update Region ID settings for PCI1. + * Added IPMMU Region ID table. + * : 17.03.2025 0.11 Updated AXI timeout setting value. + * : 26.05.2025 0.12 Updated RAM protection settings for + * protection area. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#define RTDMA_EN (0x00000002U) +#define SYSDMA_EN (0x00003FF4U) + +#pragma ghs section rodata=".qosbw_tbl" +/* not used for V4M */ +const QOS_SETTING_TABLE g_qosbw_tbl[] = {0}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".qoswt_tbl" +/* not used for V4M */ +const QOS_SETTING_TABLE g_qoswt_tbl[] = {0}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_m_tbl" +const REGION_ID_SETTING_TABLE g_rgid_m_tbl[] = { + [0] = {0xFCF81000U, 0x00000002U}, /* RGIDM_MODID[0]:PCI0 */ + [1] = {0xFCF81020U, 0x00000002U}, /* RGIDM_MODID[1]:PCI1 */ + [2] = {0xFCF81010U, 0x00000002U}, /* RGIDM_MODID[3]:AVB0 */ + [3] = {0xFCF81014U, 0x00000001U}, /* RGIDM_MODID[4]:AVB1 */ + [4] = {0xFCF81018U, 0x00000001U}, /* RGIDM_MODID[5]:AVB2 */ + [5] = {0xFDC2100CU, 0x00000000U}, /* RGIDM_MODID[6]:DCLS_ICUMX */ + [6] = {0xFDC21010U, 0x00000000U}, /* RGIDM_MODID[7]:ICUMX */ + [7] = {0xFDC21014U, 0x00000000U}, /* RGIDM_MODID[8]:SDMAC_ICUMX */ + [8] = {0xFD441018U, 0x00000001U}, /* RGIDM_MODID[9]:CR52SS0 */ + [9] = {0xFD44105CU, 0x00000001U}, /* RGIDM_MODID[10]:CR52SS1 */ + [10] = {0xFD441060U, 0x00000006U}, /* RGIDM_MODID[11]:CR52SS2 */ + [11] = {0xFD44101CU, 0x00000003U}, /* RGIDM_MODID[12]:CSD */ + [12] = {0xFD441024U, 0x00000002U}, /* RGIDM_MODID[13]:INTAP0 */ + [13] = {0xFC861018U, 0x00000002U}, /* RGIDM_MODID[14]:FBABUSTOP0 */ + [14] = {0xFCB51020U, 0x00000002U}, /* RGIDM_MODID[15]:SDHI0 */ + [15] = {0xFCB51010U, 0x00000001U}, /* RGIDM_MODID[16]:FRAY */ + [16] = {0xFC811000U, 0x00000002U}, /* RGIDM_MODID[17]:AXMM2AXSTM */ + [17] = {0xFC811004U, 0x00000003U}, /* RGIDM_MODID[18]:CSDE0 */ + [18] = {0xFC811008U, 0x00000003U}, /* RGIDM_MODID[19]:CSDE1 */ + [19] = {0xFD441020U, 0x00000003U}, /* RGIDM_MODID[20]:CSDE2 */ + [20] = {0xFC881004U, 0x00000002U}, /* RGIDM_MODID[21]:FBABUSIR0 */ + [21] = {0xFC881008U, 0x00000002U}, /* RGIDM_MODID[22]:FBABUSIR1 */ + [22] = {0xFC88100CU, 0x00000002U}, /* RGIDM_MODID[23]:FBABUSIR2 */ + [23] = {0xFC881010U, 0x00000002U}, /* RGIDM_MODID[24]:FBABUSIR3 */ + [24] = {0xFC011014U, 0x00000002U}, /* RGIDM_MODID[25]:RGX0 */ + [25] = {0xFC681004U, 0x00000002U}, /* RGIDM_MODID[26]:FBABUSVC */ + [26] = {0xFC681010U, 0x00000002U}, /* RGIDM_MODID[27]:IMR00 */ + [27] = {0xFC681014U, 0x00000002U}, /* RGIDM_MODID[28]:IMR01 */ + [28] = {0xFC681024U, 0x00000002U}, /* RGIDM_MODID[29]:IMR10 */ + [29] = {0xFC681028U, 0x00000002U}, /* RGIDM_MODID[30]:IMR11 */ + [30] = {0xFC681040U, 0x00000002U}, /* RGIDM_MODID[31]:IMS0 */ + [31] = {0xFC681044U, 0x00000002U}, /* RGIDM_MODID[32]:IMS1 */ + [32] = {0xFC681048U, 0x00000005U}, /* RGIDM_MODID[33]:IV1ES */ + [33] = {0xFEBE1000U, 0x00000002U}, /* RGIDM_MODID[34]:DSITLINK0 */ + [34] = {0xFEBE1008U, 0x00000002U}, /* RGIDM_MODID[36]:FBABUSVIO */ + [35] = {0xFEBE1014U, 0x00000002U}, /* RGIDM_MODID[37]:FCPVD0 */ + [36] = {0xFEBE101CU, 0x00000002U}, /* RGIDM_MODID[38]:FCPVX0 */ + [37] = {0xFEBF1020U, 0x00000002U}, /* RGIDM_MODID[39]:ISP00 */ + [38] = {0xFEBF1024U, 0x00000002U}, /* RGIDM_MODID[40]:ISP01 */ + [39] = {0xFEBF1000U, 0x00000002U}, /* RGIDM_MODID[41]:ISP02 */ + [40] = {0xFEBF1004U, 0x00000002U}, /* RGIDM_MODID[42]:ISP03 */ + [41] = {0xFEBF1008U, 0x00000002U}, /* RGIDM_MODID[43]:ISP04 */ + [42] = {0xFEBF1010U, 0x00000002U}, /* RGIDM_MODID[44]:VIN0 */ + [43] = {0xFEBF1014U, 0x00000002U}, /* RGIDM_MODID[45]:VIN1 */ + [44] = {0xFC311004U, 0x00000002U}, /* RGIDM_MODID[46]:FBABUSVIP0 */ + [45] = {0xFC311010U, 0x00000002U}, /* RGIDM_MODID[47]:SMPO */ + [46] = {0xFC311018U, 0x00000002U}, /* RGIDM_MODID[48]:SMPS */ + [47] = {0xFC31101CU, 0x00000002U}, /* RGIDM_MODID[49]:UMFL */ + [48] = {0xFC881018U, 0x00000002U}, /* RGIDM_MODID[50]:DSP00 */ + [49] = {0xFC881024U, 0x00000002U}, /* RGIDM_MODID[51]:DSP01 */ + [50] = {0xFC881038U, 0x00000002U}, /* RGIDM_MODID[52]:DSP10 */ + [51] = {0xFC881044U, 0x00000002U}, /* RGIDM_MODID[53]:DSP11 */ + [52] = {0xFC881048U, 0x00000002U}, /* RGIDM_MODID[54]:DSP20 */ + [53] = {0xFC88104CU, 0x00000002U}, /* RGIDM_MODID[55]:DSP21 */ + [54] = {0xFC881050U, 0x00000002U}, /* RGIDM_MODID[56]:DSP30 */ + [55] = {0xFC881054U, 0x00000002U}, /* RGIDM_MODID[57]:DSP31 */ + [56] = {0xFC881058U, 0x00000002U}, /* RGIDM_MODID[58]:IMP0R100 */ + [57] = {0xFC88105CU, 0x00000002U}, /* RGIDM_MODID[59]:IMP0R101 */ + [58] = {0xFC881060U, 0x00000002U}, /* RGIDM_MODID[60]:IMP0R102 */ + [59] = {0xFC881064U, 0x00000002U}, /* RGIDM_MODID[61]:IMP0R103 */ + [60] = {0xFC881068U, 0x00000002U}, /* RGIDM_MODID[62]:IMP0R104 */ + [61] = {0xFC88106CU, 0x00000002U}, /* RGIDM_MODID[63]:IMP0R105 */ + [62] = {0xFC881070U, 0x00000002U}, /* RGIDM_MODID[64]:IMP0R106 */ + [63] = {0xFC881074U, 0x00000002U}, /* RGIDM_MODID[65]:IMP0R107 */ + [64] = {0xFC881078U, 0x00000002U}, /* RGIDM_MODID[66]:IMP0R108 */ + [65] = {0xFC88107CU, 0x00000002U}, /* RGIDM_MODID[67]:IMP0R109 */ + [66] = {0xFC881080U, 0x00000002U}, /* RGIDM_MODID[68]:IMP0R200 */ + [67] = {0xFC881084U, 0x00000002U}, /* RGIDM_MODID[69]:IMP0R201 */ + [68] = {0xFC881088U, 0x00000002U}, /* RGIDM_MODID[70]:IMP0R202 */ + [69] = {0xFC88108CU, 0x00000002U}, /* RGIDM_MODID[71]:IMP0W100 */ + [70] = {0xFC881090U, 0x00000002U}, /* RGIDM_MODID[72]:IMP0W101 */ + [71] = {0xFC881094U, 0x00000002U}, /* RGIDM_MODID[73]:IMP0W102 */ + [72] = {0xFC881098U, 0x00000002U}, /* RGIDM_MODID[74]:IMP0W103 */ + [73] = {0xFC88109CU, 0x00000002U}, /* RGIDM_MODID[75]:IMP0W104 */ + [74] = {0xFC8810A0U, 0x00000002U}, /* RGIDM_MODID[76]:IMP0W105 */ + [75] = {0xFC8810A4U, 0x00000002U}, /* RGIDM_MODID[77]:IMP0W106 */ + [76] = {0xFC8810A8U, 0x00000002U}, /* RGIDM_MODID[78]:IMP0W107 */ + [77] = {0xFC8810ACU, 0x00000002U}, /* RGIDM_MODID[79]:IMP0W108 */ + [78] = {0xFC8810B0U, 0x00000002U}, /* RGIDM_MODID[80]:IMP0W109 */ + [79] = {0xFC8810B4U, 0x00000002U}, /* RGIDM_MODID[81]:IMP0W200 */ + [80] = {0xFC8810B8U, 0x00000002U}, /* RGIDM_MODID[82]:IMP0W201 */ + [81] = {0xFC8810BCU, 0x00000002U}, /* RGIDM_MODID[83]:IMP0W202 */ + [82] = {0xFDDBF500U, 0x0000000EU}, /* RGIDM_MODID[84]:VRAM_R */ + [83] = {0xFDDBF504U, 0x0000000EU}, /* RGIDM_MODID[85]:VRAM_W */ + [84] = {0xFC311008U, 0x00000002U}, /* RGIDM_MODID[86]:PAP */ +}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_r_tbl" +const REGION_ID_SETTING_TABLE g_rgid_r_tbl[] = { + [0] = {0xFD482000U, 0x0000000FU}, /* RGIDR_MODID[0]:ARMGC0*/ + [1] = {0xFD482004U, 0x0000000FU}, /* RGIDR_MODID[1]:ARMGC1*/ + [2] = {0xFD482008U, 0x00000000U}, /* RGIDR_MODID[2]:ARMGC2*/ + [3] = {0xFD48200CU, 0x0000000FU}, /* RGIDR_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDR_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDR_MODID[5]:ARRT02*/ + [4] = {0xFD482018U, 0x0000000FU}, /* RGIDR_MODID[6]:ARRT03*/ + [5] = {0xFD48201CU, 0x0000000FU}, /* RGIDR_MODID[7]:ARRT04*/ + [6] = {0xFD482020U, 0x0000000FU}, /* RGIDR_MODID[8]:ARRT05*/ + [7] = {0xFD482024U, 0x0000000FU}, /* RGIDR_MODID[9]:ARRT06*/ + [8] = {0xFD482028U, 0x0000000FU}, /* RGIDR_MODID[10]:ARRT07*/ + [9] = {0xFD48202CU, 0x00000000U}, /* RGIDR_MODID[11]:ARRT08*/ + [10] = {0xFD482030U, 0x00000001U}, /* RGIDR_MODID[12]:LIFEC0*/ + [11] = {0xFD482034U, 0x0000000EU}, /* RGIDR_MODID[13]:SWDT*/ + [12] = {0xFD482038U, 0x0000006EU}, /* RGIDR_MODID[14]:TMU0*/ + [13] = {0xFD48203CU, 0x0000000EU}, /* RGIDR_MODID[15]:WDT*/ + [14] = {0xFD482040U, 0x0000000EU}, /* RGIDR_MODID[16]:WWDT0*/ + [15] = {0xFD482044U, 0x0000000EU}, /* RGIDR_MODID[17]:WWDT1*/ + [16] = {0xFD482048U, 0x0000000EU}, /* RGIDR_MODID[18]:WWDT2*/ + [17] = {0xFD48204CU, 0x0000000EU}, /* RGIDR_MODID[19]:WWDT3*/ + [18] = {0xFD482050U, 0x0000000EU}, /* RGIDR_MODID[20]:WWDT4*/ + [19] = {0xFD482054U, 0x0000000EU}, /* RGIDR_MODID[21]:WWDT5*/ + [20] = {0xFD482058U, 0x0000000EU}, /* RGIDR_MODID[22]:WWDT6*/ + [21] = {0xFD482068U, 0x0000000FU}, /* RGIDR_MODID[23]:ECMRT3*/ + [22] = {0xFDA02004U, 0x0000000FU}, /* RGIDR_MODID[24]:APMU0*/ + [23] = {0xFDA02008U, 0x00000002U}, /* RGIDR_MODID[25]:APMU1*/ + [24] = {0xFDA0200CU, 0x00000000U}, /* RGIDR_MODID[26]:APMU10*/ + [25] = {0xFDA02010U, 0x00000000U}, /* RGIDR_MODID[27]:APMU11*/ + [26] = {0xFDA02014U, 0x00000000U}, /* RGIDR_MODID[28]:APMU12*/ + [27] = {0xFDA02018U, 0x00000000U}, /* RGIDR_MODID[29]:APMU13*/ + [28] = {0xFDA0201CU, 0x00000000U}, /* RGIDR_MODID[30]:APMU14*/ + [29] = {0xFDA02020U, 0x00000000U}, /* RGIDR_MODID[31]:APMU15*/ + [30] = {0xFDA02024U, 0x00000004U}, /* RGIDR_MODID[32]:APMU2*/ + [31] = {0xFDA02028U, 0x00000004U}, /* RGIDR_MODID[33]:APMU3*/ + [32] = {0xFDA0202CU, 0x00000000U}, /* RGIDR_MODID[34]:APMU4*/ + [33] = {0xFDA02030U, 0x00000000U}, /* RGIDR_MODID[35]:APMU5*/ + [34] = {0xFDA02034U, 0x00000000U}, /* RGIDR_MODID[36]:APMU6*/ + [35] = {0xFDA02038U, 0x00000000U}, /* RGIDR_MODID[37]:APMU7*/ + [36] = {0xFDA0203CU, 0x00000000U}, /* RGIDR_MODID[38]:APMU8*/ + [37] = {0xFDA02040U, 0x00000000U}, /* RGIDR_MODID[39]:APMU9*/ + [38] = {0xFDA02044U, 0x0000000FU}, /* RGIDR_MODID[40]:ARS00*/ + /* After setting */ /* RGIDR_MODID[41]:ARS01*/ + /* After setting */ /* RGIDR_MODID[42]:ARS02*/ + [39] = {0xFDA02050U, 0x0000000FU}, /* RGIDR_MODID[43]:ARS03*/ + [40] = {0xFDA02054U, 0x0000000FU}, /* RGIDR_MODID[44]:ARS04*/ + [41] = {0xFDA02058U, 0x0000000FU}, /* RGIDR_MODID[45]:ARS05*/ + [42] = {0xFDA0205CU, 0x0000000FU}, /* RGIDR_MODID[46]:ARS06*/ + [43] = {0xFDA02060U, 0x0000000FU}, /* RGIDR_MODID[47]:ARS07*/ + [44] = {0xFDA02064U, 0x00000000U}, /* RGIDR_MODID[48]:ARS08*/ + [45] = {0xFDA02068U, 0x0000000EU}, /* RGIDR_MODID[49]:CMT0*/ + [46] = {0xFDA0206CU, 0x0000000EU}, /* RGIDR_MODID[50]:CMT1*/ + [47] = {0xFDA02070U, 0x0000000EU}, /* RGIDR_MODID[51]:CMT2*/ + [48] = {0xFDA02074U, 0x0000000EU}, /* RGIDR_MODID[52]:CMT3*/ + [49] = {0xFDA02078U, 0x0000000AU}, /* RGIDR_MODID[53]:CKM*/ + [50] = {0xFDA0207CU, 0x0000000EU}, /* RGIDR_MODID[54]:DBE*/ + [51] = {0xFDA02080U, 0x0000000EU}, /* RGIDR_MODID[55]:IRQC*/ + [52] = {0xFDA02084U, 0x0000000FU}, /* RGIDR_MODID[56]:ECMPS0*/ + [53] = {0xFDA02088U, 0x0000000BU}, /* RGIDR_MODID[57]:OTP0*/ + [54] = {0xFDA0208CU, 0x0000000FU}, /* RGIDR_MODID[58]:OTP1*/ + [55] = {0xFDA0209CU, 0x0000000EU}, /* RGIDR_MODID[59]:SCMT*/ + [56] = {0xFDA020A8U, 0x0000004EU}, /* RGIDR_MODID[60]:TSC1*/ + [57] = {0xFDA020ACU, 0x0000004EU}, /* RGIDR_MODID[61]:TSC2*/ + [58] = {0xFDA020B8U, 0x00000006U}, /* RGIDR_MODID[62]:UCMT*/ + [59] = {0xFDA02100U, 0x0000006FU}, /* RGIDR_MODID[63]:CPG0*/ + [60] = {0xFDA02104U, 0x0000000AU}, /* RGIDR_MODID[64]:CPG1*/ + [61] = {0xFDA02108U, 0x0000004EU}, /* RGIDR_MODID[65]:CPG2*/ + [62] = {0xFDA0210CU, 0x00000028U}, /* RGIDR_MODID[66]:CPG3*/ + [63] = {0xFDA02110U, 0x0000006FU}, /* RGIDR_MODID[67]:PFC00*/ + [64] = {0xFDA02114U, 0x0000000AU}, /* RGIDR_MODID[68]:PFC01*/ + [65] = {0xFDA02118U, 0x0000004EU}, /* RGIDR_MODID[69]:PFC02*/ + [66] = {0xFDA0211CU, 0x00000028U}, /* RGIDR_MODID[70]:PFC03*/ + [67] = {0xFDA02120U, 0x0000006FU}, /* RGIDR_MODID[71]:PFC10*/ + [68] = {0xFDA02124U, 0x0000000AU}, /* RGIDR_MODID[72]:PFC11*/ + [69] = {0xFDA02128U, 0x0000004EU}, /* RGIDR_MODID[73]:PFC12*/ + [70] = {0xFDA0212CU, 0x00000028U}, /* RGIDR_MODID[74]:PFC13*/ + [71] = {0xFDA02130U, 0x0000006FU}, /* RGIDR_MODID[75]:PFC20*/ + [72] = {0xFDA02134U, 0x0000000AU}, /* RGIDR_MODID[76]:PFC21*/ + [73] = {0xFDA02138U, 0x0000004EU}, /* RGIDR_MODID[77]:PFC22*/ + [74] = {0xFDA0213CU, 0x00000028U}, /* RGIDR_MODID[78]:PFC23*/ + [75] = {0xFDA02150U, 0x0000006FU}, /* RGIDR_MODID[79]:PFCS0*/ + [76] = {0xFDA02154U, 0x0000000AU}, /* RGIDR_MODID[80]:PFCS1*/ + [77] = {0xFDA02158U, 0x0000004EU}, /* RGIDR_MODID[81]:PFCS2*/ + [78] = {0xFDA0215CU, 0x00000028U}, /* RGIDR_MODID[82]:PFCS3*/ + [79] = {0xFDA02160U, 0x0000006FU}, /* RGIDR_MODID[83]:RESET0*/ + [80] = {0xFDA02164U, 0x0000000AU}, /* RGIDR_MODID[84]:RESET1*/ + [81] = {0xFDA02168U, 0x0000004EU}, /* RGIDR_MODID[85]:RESET2*/ + [82] = {0xFDA0216CU, 0x00000028U}, /* RGIDR_MODID[86]:RESET3*/ + [83] = {0xFDA02170U, 0x0000006FU}, /* RGIDR_MODID[87]:SYS0*/ + [84] = {0xFDA02174U, 0x0000000AU}, /* RGIDR_MODID[88]:SYS1*/ + [85] = {0xFDA02178U, 0x0000004EU}, /* RGIDR_MODID[89]:SYS2*/ + [86] = {0xFDA0217CU, 0x00000028U}, /* RGIDR_MODID[90]:SYS3*/ + [87] = {0xFCB62000U, 0x0000000EU}, /* RGIDR_MODID[91]:DMAMSI0*/ + [88] = {0xFCB62004U, 0x0000000EU}, /* RGIDR_MODID[92]:DMAMSI1*/ + [89] = {0xFCB62008U, 0x0000000EU}, /* RGIDR_MODID[93]:DMAMSI2*/ + [90] = {0xFCB6200CU, 0x0000000EU}, /* RGIDR_MODID[94]:DMAMSI3*/ + [91] = {0xFCB62010U, 0x0000000EU}, /* RGIDR_MODID[95]:DMAMSI4*/ + [92] = {0xFCB62014U, 0x0000000EU}, /* RGIDR_MODID[96]:DMAMSI5*/ + [93] = {0xFCB62018U, 0x0000000FU}, /* RGIDR_MODID[97]:ECMSP3*/ + [94] = {0xFCB62024U, 0x0000000FU}, /* RGIDR_MODID[98]:ARSP30*/ + /* After setting */ /* RGIDR_MODID[99]:ARSP31*/ + /* After setting */ /* RGIDR_MODID[100]:ARSP32*/ + [95] = {0xFCB62030U, 0x0000000FU}, /* RGIDR_MODID[101]:ARSP33*/ + [96] = {0xFCB62034U, 0x0000000FU}, /* RGIDR_MODID[102]:ARSP34*/ + [97] = {0xFCB62038U, 0x0000000FU}, /* RGIDR_MODID[103]:ARSP35*/ + [98] = {0xFCB6203CU, 0x0000000FU}, /* RGIDR_MODID[104]:ARSP36*/ + [99] = {0xFCB62040U, 0x0000000FU}, /* RGIDR_MODID[105]:ARSP37*/ + [100] = {0xFCB62044U, 0x00000000U}, /* RGIDR_MODID[106]:ARSP38*/ + [101] = {0xFCB62048U, 0x0000000EU}, /* RGIDR_MODID[107]:MSI0*/ + [102] = {0xFCB6204CU, 0x0000000EU}, /* RGIDR_MODID[108]:MSI1*/ + [103] = {0xFCB62050U, 0x0000000EU}, /* RGIDR_MODID[109]:MSI2*/ + [104] = {0xFCB62054U, 0x0000000EU}, /* RGIDR_MODID[110]:MSI3*/ + [105] = {0xFCB62058U, 0x0000000EU}, /* RGIDR_MODID[111]:MSI4*/ + [106] = {0xFCB6205CU, 0x0000000EU}, /* RGIDR_MODID[112]:MSI5*/ + [107] = {0xFCB92000U, 0x0000000FU}, /* RGIDR_MODID[113]:ARSP40*/ + /* After setting */ /* RGIDR_MODID[114]:ARSP41*/ + /* After setting */ /* RGIDR_MODID[115]:ARSP42*/ + [108] = {0xFCB9200CU, 0x0000000FU}, /* RGIDR_MODID[116]:ARSP43*/ + [109] = {0xFCB92010U, 0x0000000FU}, /* RGIDR_MODID[117]:ARSP44*/ + [110] = {0xFCB92014U, 0x0000000FU}, /* RGIDR_MODID[118]:ARSP45*/ + [111] = {0xFCB92018U, 0x0000000FU}, /* RGIDR_MODID[119]:ARSP46*/ + [112] = {0xFCB9201CU, 0x0000000FU}, /* RGIDR_MODID[120]:ARSP47*/ + [113] = {0xFCB92020U, 0x00000000U}, /* RGIDR_MODID[121]:ARSP48*/ + [114] = {0xFCB92024U, 0x0000004FU}, /* RGIDR_MODID[122]:DMAHSCIF0*/ + [115] = {0xFCB92028U, 0x0000004FU}, /* RGIDR_MODID[123]:DMAHSCIF1*/ + [116] = {0xFCB9202CU, 0x0000004FU}, /* RGIDR_MODID[124]:DMAHSCIF2*/ + [117] = {0xFCB92030U, 0x0000004FU}, /* RGIDR_MODID[125]:DMAHSCIF3*/ + [118] = {0xFCB92034U, 0x0000004FU}, /* RGIDR_MODID[126]:DMASCIF0*/ + [119] = {0xFCB92038U, 0x0000004FU}, /* RGIDR_MODID[127]:DMASCIF1*/ + [120] = {0xFCB9203CU, 0x0000004FU}, /* RGIDR_MODID[128]:DMASCIF3*/ + [121] = {0xFCB92040U, 0x0000004FU}, /* RGIDR_MODID[129]:DMASCIF4*/ + [122] = {0xFCB92044U, 0x0000000FU}, /* RGIDR_MODID[130]:ECMSP4*/ + [123] = {0xFCB92048U, 0x0000004FU}, /* RGIDR_MODID[131]:HSCIF0*/ + [124] = {0xFCB9204CU, 0x0000004FU}, /* RGIDR_MODID[132]:HSCIF1*/ + [125] = {0xFCB92050U, 0x0000004FU}, /* RGIDR_MODID[133]:HSCIF2*/ + [126] = {0xFCB92054U, 0x0000004FU}, /* RGIDR_MODID[134]:HSCIF3*/ + [127] = {0xFCB92058U, 0x0000004FU}, /* RGIDR_MODID[135]:SCIF0*/ + [128] = {0xFCB9205CU, 0x0000004FU}, /* RGIDR_MODID[136]:SCIF1*/ + [129] = {0xFCB92060U, 0x0000004FU}, /* RGIDR_MODID[137]:SCIF3*/ + [130] = {0xFCB92064U, 0x0000004FU}, /* RGIDR_MODID[138]:SCIF4*/ + [131] = {0xFCB92068U, 0x0000006EU}, /* RGIDR_MODID[139]:TMU1*/ + [132] = {0xFCB9206CU, 0x0000006EU}, /* RGIDR_MODID[140]:TMU2*/ + [133] = {0xFCB92070U, 0x0000006EU}, /* RGIDR_MODID[141]:TMU3*/ + [134] = {0xFCB92074U, 0x0000006EU}, /* RGIDR_MODID[142]:TMU4*/ + [135] = {0xFCB92078U, 0x0000004AU}, /* RGIDR_MODID[143]:CANFD*/ + [136] = {0xFCB9207CU, 0x0000004AU}, /* RGIDR_MODID[144]:DMACANFD*/ + [137] = {0xFCB92080U, 0x00000002U}, /* RGIDR_MODID[145]:DMATPU0*/ + [138] = {0xFCB92084U, 0x00000002U}, /* RGIDR_MODID[146]:PWM0*/ + [139] = {0xFCB92088U, 0x00000002U}, /* RGIDR_MODID[147]:PWM1*/ + [140] = {0xFCB9208CU, 0x00000002U}, /* RGIDR_MODID[148]:PWM2*/ + [141] = {0xFCB92090U, 0x00000002U}, /* RGIDR_MODID[149]:PWM3*/ + [142] = {0xFCB92094U, 0x00000002U}, /* RGIDR_MODID[150]:PWM4*/ + [143] = {0xFCB920ACU, 0x00000002U}, /* RGIDR_MODID[151]:TPU0*/ + [144] = {0xFEBD2000U, 0x0000000FU}, /* RGIDR_MODID[152]:ARVI40*/ + /* After setting */ /* RGIDR_MODID[153]:ARVI41*/ + /* After setting */ /* RGIDR_MODID[154]:ARVI42*/ + [145] = {0xFEBD200CU, 0x0000000FU}, /* RGIDR_MODID[155]:ARVI43*/ + [146] = {0xFEBD2010U, 0x0000000FU}, /* RGIDR_MODID[156]:ARVI44*/ + [147] = {0xFEBD2014U, 0x0000000FU}, /* RGIDR_MODID[157]:ARVI45*/ + [148] = {0xFEBD2018U, 0x0000000FU}, /* RGIDR_MODID[158]:ARVI46*/ + [149] = {0xFEBD201CU, 0x0000000FU}, /* RGIDR_MODID[159]:ARVI47*/ + [150] = {0xFEBD2020U, 0x00000000U}, /* RGIDR_MODID[160]:ARVI48*/ + [151] = {0xFEBD2024U, 0x0000000FU}, /* RGIDR_MODID[161]:DIS0*/ + [152] = {0xFEBD2030U, 0x0000000FU}, /* RGIDR_MODID[162]:ECMVIO2*/ + [153] = {0xFEBD2034U, 0x0000000FU}, /* RGIDR_MODID[163]:FCPVD0*/ + [154] = {0xFEBD203CU, 0x0000004EU}, /* RGIDR_MODID[164]:VSPD0*/ + [155] = {0xFCF82000U, 0x0000000AU}, /* RGIDR_MODID[165]:CKMHSC*/ + [156] = {0xFCF82004U, 0x0000000CU}, /* RGIDR_MODID[166]:AXIPCI001*/ + [157] = {0xFCF82008U, 0x0000000CU}, /* RGIDR_MODID[167]:AXIPCI002*/ + [158] = {0xFCF8200CU, 0x0000000CU}, /* RGIDR_MODID[168]:AXIPCI003*/ + [159] = {0xFCF82014U, 0x0000000CU}, /* RGIDR_MODID[169]:AXIPCI005*/ + [160] = {0xFCF82018U, 0x0000000CU}, /* RGIDR_MODID[170]:AXIPCI006*/ + [161] = {0xFCF8201CU, 0x0000000CU}, /* RGIDR_MODID[171]:AXIPCI007*/ + [162] = {0xFCF82020U, 0x0000000CU}, /* RGIDR_MODID[172]:AXIPCI008*/ + [163] = {0xFCF82024U, 0x0000000CU}, /* RGIDR_MODID[173]:AXIPCI009*/ + [164] = {0xFCF82028U, 0x0000000CU}, /* RGIDR_MODID[174]:AXIPCI010*/ + [165] = {0xFCF8202CU, 0x0000000CU}, /* RGIDR_MODID[175]:AXIPCI011*/ + [166] = {0xFCF82030U, 0x0000000CU}, /* RGIDR_MODID[176]:AXIPCI012*/ + [167] = {0xFCF82034U, 0x0000000CU}, /* RGIDR_MODID[177]:AXIPCI013*/ + [168] = {0xFCF82038U, 0x0000000CU}, /* RGIDR_MODID[178]:AXIPCI014*/ + [169] = {0xFCF8203CU, 0x0000000CU}, /* RGIDR_MODID[179]:AXIPCI015*/ + [170] = {0xFCF82084U, 0x0000000EU}, /* RGIDR_MODID[180]:GPTP*/ + [171] = {0xFCF82088U, 0x0000004EU}, /* RGIDR_MODID[181]:IPMMUHC00*/ + [172] = {0xFCF820F4U, 0x0000000CU}, /* RGIDR_MODID[182]:AXIPCI000*/ + [173] = {0xFCF820F8U, 0x0000000CU}, /* RGIDR_MODID[183]:AXIPCI004*/ + [174] = {0xFCF820FCU, 0x0000004EU}, /* RGIDR_MODID[184]:IPMMUHC01*/ + [175] = {0xFCF82100U, 0x0000004EU}, /* RGIDR_MODID[185]:AVB0*/ + [176] = {0xFCF82104U, 0x0000004EU}, /* RGIDR_MODID[186]:AVB1*/ + [177] = {0xFCF82108U, 0x0000004EU}, /* RGIDR_MODID[187]:AVB2*/ + [178] = {0xFCF8210CU, 0x0000004EU}, /* RGIDR_MODID[188]:IPMMUHC10*/ + [179] = {0xFCF82110U, 0x0000004EU}, /* RGIDR_MODID[189]:IPMMUHC11*/ + [180] = {0xFCF82114U, 0x0000004EU}, /* RGIDR_MODID[190]:IPMMUHC12*/ + [181] = {0xFCF82118U, 0x0000004EU}, /* RGIDR_MODID[191]:IPMMUHC13*/ + [182] = {0xFCF8211CU, 0x0000000CU}, /* RGIDR_MODID[192]:PPHY0*/ + [183] = {0xFCF82124U, 0x0000004EU}, /* RGIDR_MODID[193]:IPMMUHC14*/ + [184] = {0xFCF82128U, 0x0000004EU}, /* RGIDR_MODID[194]:IPMMUHC15*/ + [185] = {0xFCF8212CU, 0x0000000EU}, /* RGIDR_MODID[195]:FBAHSC*/ + [186] = {0xFCF82130U, 0x0000004EU}, /* RGIDR_MODID[196]:IPMMUHC02*/ + [187] = {0xFCF82138U, 0x0000000FU}, /* RGIDR_MODID[197]:ECMHSC*/ + [188] = {0xFCF8213CU, 0x0000000FU}, /* RGIDR_MODID[198]:ARHC0*/ + /* After setting */ /* RGIDR_MODID[199]:ARHC1*/ + /* After setting */ /* RGIDR_MODID[200]:ARHC2*/ + [189] = {0xFCF82148U, 0x0000000FU}, /* RGIDR_MODID[201]:ARHC3*/ + [190] = {0xFCF8214CU, 0x0000000FU}, /* RGIDR_MODID[202]:ARHC4*/ + [191] = {0xFCF82150U, 0x0000000FU}, /* RGIDR_MODID[203]:ARHC5*/ + [192] = {0xFCF82154U, 0x0000000FU}, /* RGIDR_MODID[204]:ARHC6*/ + [193] = {0xFCF82158U, 0x0000000FU}, /* RGIDR_MODID[205]:ARHC7*/ + [194] = {0xFCF8215CU, 0x00000000U}, /* RGIDR_MODID[206]:ARHC8*/ + [195] = {0xFCF82160U, 0x0000004EU}, /* RGIDR_MODID[207]:IPMMUHC03*/ + [196] = {0xFCF82164U, 0x0000004EU}, /* RGIDR_MODID[208]:IPMMUHC04*/ + [197] = {0xFCF82168U, 0x0000004EU}, /* RGIDR_MODID[209]:IPMMUHC05*/ + [198] = {0xFCF8216CU, 0x0000004EU}, /* RGIDR_MODID[210]:IPMMUHC06*/ + [199] = {0xFCF82170U, 0x0000004EU}, /* RGIDR_MODID[211]:IPMMUHC07*/ + [200] = {0xFCF82174U, 0x0000004EU}, /* RGIDR_MODID[212]:IPMMUHC08*/ + [201] = {0xFCF82178U, 0x0000004EU}, /* RGIDR_MODID[213]:IPMMUHC09*/ + [202] = {0xFC882000U, 0x0000000FU}, /* RGIDR_MODID[214]:ARIMP00*/ + /* After setting */ /* RGIDR_MODID[215]:ARIMP01*/ + /* After setting */ /* RGIDR_MODID[216]:ARIMP02*/ + [203] = {0xFC88200CU, 0x0000000FU}, /* RGIDR_MODID[217]:ARIMP03*/ + [204] = {0xFC882010U, 0x0000000FU}, /* RGIDR_MODID[218]:ARIMP04*/ + [205] = {0xFC882014U, 0x0000004EU}, /* RGIDR_MODID[219]:AXIFBABUSIR0*/ + [206] = {0xFC882018U, 0x0000004EU}, /* RGIDR_MODID[220]:AXIFBABUSIR1*/ + [207] = {0xFC88201CU, 0x0000004EU}, /* RGIDR_MODID[221]:AXIFBABUSIR2*/ + [208] = {0xFC882020U, 0x0000004EU}, /* RGIDR_MODID[222]:AXIFBABUSIR3*/ + [209] = {0xFC882028U, 0x0000004EU}, /* RGIDR_MODID[223]:AXIIMP0*/ + [210] = {0xFC882034U, 0x0000000FU}, /* RGIDR_MODID[224]:ARIMP05*/ + [211] = {0xFC882038U, 0x0000000FU}, /* RGIDR_MODID[225]:ARIMP06*/ + [212] = {0xFC88203CU, 0x0000000FU}, /* RGIDR_MODID[226]:ARIMP07*/ + [213] = {0xFC882040U, 0x00000000U}, /* RGIDR_MODID[227]:ARIMP08*/ + [214] = {0xFC882048U, 0x0000000FU}, /* RGIDR_MODID[228]:ECMIR*/ + [215] = {0xFC88204CU, 0x0000000FU}, /* RGIDR_MODID[229]:DSPPS*/ + [216] = {0xFC882050U, 0x0000004EU}, /* RGIDR_MODID[230]:IPMMUIR1*/ + [217] = {0xFC882054U, 0x0000004EU}, /* RGIDR_MODID[231]:IPMMUIR0*/ + [218] = {0xFC882058U, 0x0000004EU}, /* RGIDR_MODID[232]:IPMMUIR10*/ + [219] = {0xFC88205CU, 0x0000004EU}, /* RGIDR_MODID[233]:IPMMUIR11*/ + [220] = {0xFC882060U, 0x0000004EU}, /* RGIDR_MODID[234]:IPMMUIR12*/ + [221] = {0xFC882064U, 0x0000004EU}, /* RGIDR_MODID[235]:IPMMUIR13*/ + [222] = {0xFC882068U, 0x0000004EU}, /* RGIDR_MODID[236]:IPMMUIR14*/ + [223] = {0xFC88206CU, 0x0000004EU}, /* RGIDR_MODID[237]:IPMMUIR15*/ + [224] = {0xFC882070U, 0x0000004EU}, /* RGIDR_MODID[238]:IPMMUIR2*/ + [225] = {0xFC882074U, 0x0000004EU}, /* RGIDR_MODID[239]:IPMMUIR3*/ + [226] = {0xFC882078U, 0x0000004EU}, /* RGIDR_MODID[240]:IPMMUIR4*/ + [227] = {0xFC88207CU, 0x0000004EU}, /* RGIDR_MODID[241]:IPMMUIR5*/ + [228] = {0xFC882080U, 0x0000004EU}, /* RGIDR_MODID[242]:IPMMUIR6*/ + [229] = {0xFC882084U, 0x0000004EU}, /* RGIDR_MODID[243]:IPMMUIR7*/ + [230] = {0xFC882088U, 0x0000004EU}, /* RGIDR_MODID[244]:IPMMUIR8*/ + [231] = {0xFC88208CU, 0x0000004EU}, /* RGIDR_MODID[245]:IPMMUIR9*/ + [232] = {0xFC012000U, 0x0000000FU}, /* RGIDR_MODID[246]:ARPV0*/ + /* After setting */ /* RGIDR_MODID[247]:ARPV1*/ + [233] = {0xFC012008U, 0x0000002CU}, /* RGIDR_MODID[248]:AXIRGXS*/ + /* After setting */ /* RGIDR_MODID[249]:ARPV2*/ + [234] = {0xFC012010U, 0x0000000FU}, /* RGIDR_MODID[250]:ARPV3*/ + [235] = {0xFC012014U, 0x0000000FU}, /* RGIDR_MODID[251]:ARPV4*/ + [236] = {0xFC012018U, 0x0000000FU}, /* RGIDR_MODID[252]:ARPV5*/ + [237] = {0xFC01201CU, 0x0000000FU}, /* RGIDR_MODID[253]:ARPV6*/ + [238] = {0xFC012020U, 0x0000000FU}, /* RGIDR_MODID[254]:ARPV7*/ + [239] = {0xFC012024U, 0x00000000U}, /* RGIDR_MODID[255]:ARPV8*/ + [240] = {0xFC01202CU, 0x0000000FU}, /* RGIDR_MODID[256]:ECM3DG*/ + [241] = {0xFC012030U, 0x0000000EU}, /* RGIDR_MODID[257]:FBAPVC*/ + [242] = {0xFC012034U, 0x0000000EU}, /* RGIDR_MODID[258]:FBAPVD0*/ + [243] = {0xFC012038U, 0x0000000EU}, /* RGIDR_MODID[259]:FBAPVD1*/ + [244] = {0xFC01203CU, 0x0000000EU}, /* RGIDR_MODID[260]:FBAPVD2*/ + [245] = {0xFC012040U, 0x0000000EU}, /* RGIDR_MODID[261]:FBAPVE*/ + [246] = {0xFC012044U, 0x0000004EU}, /* RGIDR_MODID[262]:IPMMUPV000*/ + [247] = {0xFC012048U, 0x0000004EU}, /* RGIDR_MODID[263]:IPMMUPV001*/ + [248] = {0xFC01204CU, 0x0000004EU}, /* RGIDR_MODID[264]:IPMMUPV010*/ + [249] = {0xFC012050U, 0x0000004EU}, /* RGIDR_MODID[265]:IPMMUPV011*/ + [250] = {0xFC012054U, 0x0000004EU}, /* RGIDR_MODID[266]:IPMMUPV012*/ + [251] = {0xFC012058U, 0x0000004EU}, /* RGIDR_MODID[267]:IPMMUPV013*/ + [252] = {0xFC01205CU, 0x0000004EU}, /* RGIDR_MODID[268]:IPMMUPV014*/ + [253] = {0xFC012060U, 0x0000004EU}, /* RGIDR_MODID[269]:IPMMUPV015*/ + [254] = {0xFC012064U, 0x0000004EU}, /* RGIDR_MODID[270]:IPMMUPV002*/ + [255] = {0xFC012068U, 0x0000004EU}, /* RGIDR_MODID[271]:IPMMUPV003*/ + [256] = {0xFC01206CU, 0x0000004EU}, /* RGIDR_MODID[272]:IPMMUPV004*/ + [257] = {0xFC012070U, 0x0000004EU}, /* RGIDR_MODID[273]:IPMMUPV005*/ + [258] = {0xFC012074U, 0x0000004EU}, /* RGIDR_MODID[274]:IPMMUPV006*/ + [259] = {0xFC012078U, 0x0000004EU}, /* RGIDR_MODID[275]:IPMMUPV007*/ + [260] = {0xFC01207CU, 0x0000004EU}, /* RGIDR_MODID[276]:IPMMUPV008*/ + [261] = {0xFC012080U, 0x0000004EU}, /* RGIDR_MODID[277]:IPMMUPV009*/ + [262] = {0xFDC22000U, 0x0000000FU}, /* RGIDR_MODID[278]:ARRC0*/ + /* After setting */ /* RGIDR_MODID[279]:ARRC1*/ + /* After setting */ /* RGIDR_MODID[280]:ARRC2*/ + [263] = {0xFDC2200CU, 0x0000000FU}, /* RGIDR_MODID[281]:ARRC3*/ + [264] = {0xFDC22010U, 0x0000000FU}, /* RGIDR_MODID[282]:ARRC4*/ + [265] = {0xFDC22014U, 0x0000000FU}, /* RGIDR_MODID[283]:ARRC5*/ + [266] = {0xFDC22018U, 0x0000000FU}, /* RGIDR_MODID[284]:ARRC6*/ + [267] = {0xFDC2201CU, 0x0000000FU}, /* RGIDR_MODID[285]:ARRC7*/ + [268] = {0xFDC22020U, 0x00000000U}, /* RGIDR_MODID[286]:ARRC8*/ + [269] = {0xFDC22028U, 0x0000004FU}, /* RGIDR_MODID[287]:ICUMX*/ + [270] = {0xFDC2202CU, 0x0000000FU}, /* RGIDR_MODID[288]:ECMRC*/ + [271] = {0xFD432000U, 0x0000004EU}, /* RGIDR_MODID[289]:DMAWCRC0*/ + [272] = {0xFD432004U, 0x0000004EU}, /* RGIDR_MODID[290]:DMAWCRC1*/ + [273] = {0xFD432008U, 0x0000004EU}, /* RGIDR_MODID[291]:DMAWCRC2*/ + [274] = {0xFD43200CU, 0x0000004EU}, /* RGIDR_MODID[292]:DMAWCRC3*/ + [275] = {0xFD442000U, 0x0000000FU}, /* RGIDR_MODID[293]:ARMREG00*/ + [276] = {0xFD442004U, 0x0000000DU}, /* RGIDR_MODID[294]:ARMREG01*/ + [277] = {0xFD442008U, 0x00000000U}, /* RGIDR_MODID[295]:ARMREG10*/ + [278] = {0xFD44200CU, 0x00000000U}, /* RGIDR_MODID[296]:ARMREG11*/ + [279] = {0xFD442010U, 0x0000000BU}, /* RGIDR_MODID[297]:ARMREG12*/ + [280] = {0xFD442014U, 0x0000000FU}, /* RGIDR_MODID[298]:ARMREG13*/ + [281] = {0xFD442018U, 0x0000000BU}, /* RGIDR_MODID[299]:ARMREG14*/ + [282] = {0xFD44201CU, 0x00000002U}, /* RGIDR_MODID[300]:AXICR52SS0*/ + [283] = {0xFD442020U, 0x0000000EU}, /* RGIDR_MODID[301]:AXICSD0*/ + [284] = {0xFD442024U, 0x0000000EU}, /* RGIDR_MODID[302]:AXIINTAP0*/ + [285] = {0xFD44202CU, 0x00000009U}, /* RGIDR_MODID[303]:AXISECROM*/ + [286] = {0xFD442030U, 0x0000000FU}, /* RGIDR_MODID[304]:AXISYSRAM0*/ + [287] = {0xFD442034U, 0x0000004FU}, /* RGIDR_MODID[305]:AXISYSRAM1*/ + [288] = {0xFD442038U, 0x00000000U}, /* RGIDR_MODID[306]:ARGREG15*/ + [289] = {0xFD44203CU, 0x00000000U}, /* RGIDR_MODID[307]:ARMREG2*/ + [290] = {0xFD442040U, 0x00000000U}, /* RGIDR_MODID[308]:ARMREG3*/ + [291] = {0xFD442044U, 0x00000000U}, /* RGIDR_MODID[309]:ARMREG4*/ + [292] = {0xFD442048U, 0x0000000FU}, /* RGIDR_MODID[310]:ARMREG5*/ + [293] = {0xFD44204CU, 0x0000000FU}, /* RGIDR_MODID[311]:ARMREG6*/ + [294] = {0xFD442050U, 0x00000000U}, /* RGIDR_MODID[312]:ARMREG7*/ + [295] = {0xFD442054U, 0x0000000DU}, /* RGIDR_MODID[313]:ARMREG8*/ + [296] = {0xFD442058U, 0x0000000DU}, /* RGIDR_MODID[314]:ARMREG9*/ + [297] = {0xFD44205CU, 0x0000000FU}, /* RGIDR_MODID[315]:ARRD0*/ + /* After setting */ /* RGIDR_MODID[316]:ARRD1*/ + /* After setting */ /* RGIDR_MODID[317]:ARRD2*/ + [298] = {0xFD442068U, 0x0000000FU}, /* RGIDR_MODID[318]:ARRD3*/ + [299] = {0xFD44206CU, 0x0000000FU}, /* RGIDR_MODID[319]:ARRD4*/ + [300] = {0xFD442070U, 0x0000000FU}, /* RGIDR_MODID[320]:ARRD5*/ + [301] = {0xFD442074U, 0x0000000FU}, /* RGIDR_MODID[321]:ARRD6*/ + [302] = {0xFD442078U, 0x0000000FU}, /* RGIDR_MODID[322]:ARRD7*/ + [303] = {0xFD44207CU, 0x00000000U}, /* RGIDR_MODID[323]:ARRD8*/ + [304] = {0xFD442080U, 0x0000000FU}, /* RGIDR_MODID[324]:ARRT0*/ + /* After setting */ /* RGIDR_MODID[325]:ARRT1*/ + /* After setting */ /* RGIDR_MODID[326]:ARRT2*/ + [305] = {0xFD44208CU, 0x0000000FU}, /* RGIDR_MODID[327]:ARRT3*/ + [306] = {0xFD442090U, 0x0000000FU}, /* RGIDR_MODID[328]:ARRT4*/ + [307] = {0xFD442094U, 0x0000000FU}, /* RGIDR_MODID[329]:ARRT5*/ + [308] = {0xFD442098U, 0x0000000FU}, /* RGIDR_MODID[330]:ARRT6*/ + [309] = {0xFD44209CU, 0x0000000FU}, /* RGIDR_MODID[331]:ARRT7*/ + [310] = {0xFD4420A0U, 0x00000000U}, /* RGIDR_MODID[332]:ARRT8*/ + [311] = {0xFD4420A4U, 0x0000000AU}, /* RGIDR_MODID[333]:CKMRT*/ + [312] = {0xFD4420A8U, 0x0000004EU}, /* RGIDR_MODID[334]:CRC0*/ + [313] = {0xFD4420ACU, 0x0000004EU}, /* RGIDR_MODID[335]:CRC1*/ + [314] = {0xFD4420B0U, 0x0000004EU}, /* RGIDR_MODID[336]:CRC2*/ + [315] = {0xFD4420B4U, 0x0000004EU}, /* RGIDR_MODID[337]:CRC3*/ + [316] = {0xFD4420B8U, 0x0000000EU}, /* RGIDR_MODID[338]:CSD*/ + [317] = {0xFD4420BCU, 0x0000000FU}, /* RGIDR_MODID[339]:ECM*/ + [318] = {0xFD4420C0U, 0x0000000FU}, /* RGIDR_MODID[340]:ECMRT*/ + [319] = {0xFD4420C4U, 0x0000000EU}, /* RGIDR_MODID[341]:FBACR52*/ + [320] = {0xFD4420C8U, 0x0000000EU}, /* RGIDR_MODID[342]:FBART*/ + [321] = {0xFD4420CCU, 0x0000000EU}, /* RGIDR_MODID[343]:INTTP*/ + [322] = {0xFD4420D0U, 0x0000004EU}, /* RGIDR_MODID[344]:IPMMURT000*/ + [323] = {0xFD4420D4U, 0x0000004EU}, /* RGIDR_MODID[345]:IPMMURT100*/ + [324] = {0xFD4420D8U, 0x0000004EU}, /* RGIDR_MODID[346]:KCRC4*/ + [325] = {0xFD4420DCU, 0x0000004EU}, /* RGIDR_MODID[347]:KCRC5*/ + [326] = {0xFD4420E0U, 0x0000004EU}, /* RGIDR_MODID[348]:KCRC6*/ + [327] = {0xFD4420E4U, 0x0000004EU}, /* RGIDR_MODID[349]:KCRC7*/ + [328] = {0xFD4420E8U, 0x0000004FU}, /* RGIDR_MODID[350]:MFI00*/ + [329] = {0xFD4420ECU, 0x0000004EU}, /* RGIDR_MODID[351]:MFI01*/ + [330] = {0xFD4420F0U, 0x0000004EU}, /* RGIDR_MODID[352]:MFI10*/ + [331] = {0xFD4420F4U, 0x0000004EU}, /* RGIDR_MODID[353]:MFI02*/ + [332] = {0xFD4420F8U, 0x0000004EU}, /* RGIDR_MODID[354]:MFI03*/ + [333] = {0xFD4420FCU, 0x0000004EU}, /* RGIDR_MODID[355]:MFI04*/ + [334] = {0xFD442100U, 0x00000000U}, /* RGIDR_MODID[356]:MFI05*/ + [335] = {0xFD442104U, 0x00000000U}, /* RGIDR_MODID[357]:MFI06*/ + [336] = {0xFD442108U, 0x00000000U}, /* RGIDR_MODID[358]:MFI07*/ + [337] = {0xFD44210CU, 0x00000000U}, /* RGIDR_MODID[359]:MFI08*/ + [338] = {0xFD442110U, 0x0000004EU}, /* RGIDR_MODID[360]:MFI09*/ + [339] = {0xFD442114U, 0x0000004FU}, /* RGIDR_MODID[361]:MFI15*/ + [340] = {0xFD442118U, 0x0000000AU}, /* RGIDR_MODID[362]:CKMCR52*/ + [341] = {0xFD44211CU, 0x0000004BU}, /* RGIDR_MODID[363]:RTDM0P*/ + [342] = {0xFD442120U, 0x0000000FU}, /* RGIDR_MODID[364]:ECMRD*/ + [343] = {0xFD442124U, 0x0000004BU}, /* RGIDR_MODID[365]:RTDM1P*/ + [344] = {0xFD442130U, 0x0000000BU}, /* RGIDR_MODID[366]:SYSRAM10*/ + [345] = {0xFD442138U, 0x00000003U}, /* RGIDR_MODID[367]:SYSRAM00*/ + [346] = {0xFD44213CU, 0x0000004EU}, /* RGIDR_MODID[368]:TSIPL0*/ + [347] = {0xFD442140U, 0x0000004EU}, /* RGIDR_MODID[369]:TSIPL1*/ + [348] = {0xFD442144U, 0x0000004EU}, /* RGIDR_MODID[370]:TSIPL2*/ + [349] = {0xFD442148U, 0x0000004EU}, /* RGIDR_MODID[371]:TSIPL3*/ + [350] = {0xFD44214CU, 0x0000004EU}, /* RGIDR_MODID[372]:TSIPL4*/ + [351] = {0xFD442150U, 0x0000004EU}, /* RGIDR_MODID[373]:TSIPL5*/ + [352] = {0xFD442154U, 0x0000004EU}, /* RGIDR_MODID[374]:TSIPL6*/ + [353] = {0xFD442158U, 0x0000004EU}, /* RGIDR_MODID[375]:TSIPL7*/ + [354] = {0xFD44215CU, 0x0000004EU}, /* RGIDR_MODID[376]:WCRC0*/ + [355] = {0xFD442160U, 0x0000004EU}, /* RGIDR_MODID[377]:WCRC1*/ + [356] = {0xFD442164U, 0x0000004EU}, /* RGIDR_MODID[378]:WCRC2*/ + [357] = {0xFD442168U, 0x0000004EU}, /* RGIDR_MODID[379]:WCRC3*/ + [358] = {0xFD442180U, 0x0000004EU}, /* RGIDR_MODID[380]:MFI11*/ + [359] = {0xFD442184U, 0x00000000U}, /* RGIDR_MODID[381]:MFI12*/ + [360] = {0xFD442188U, 0x00000000U}, /* RGIDR_MODID[382]:MFI13*/ + [361] = {0xFD44218CU, 0x00000000U}, /* RGIDR_MODID[383]:MFI14*/ + [362] = {0xFD442190U, 0x0000004EU}, /* RGIDR_MODID[384]:IPMMURT001*/ + [363] = {0xFD442194U, 0x0000004EU}, /* RGIDR_MODID[385]:IPMMURT010*/ + [364] = {0xFD442198U, 0x0000004EU}, /* RGIDR_MODID[386]:IPMMURT011*/ + [365] = {0xFD44219CU, 0x0000004EU}, /* RGIDR_MODID[387]:IPMMURT012*/ + [366] = {0xFD4421A0U, 0x0000004EU}, /* RGIDR_MODID[388]:IPMMURT013*/ + [367] = {0xFD4421A4U, 0x0000004EU}, /* RGIDR_MODID[389]:IPMMURT014*/ + [368] = {0xFD4421A8U, 0x0000004EU}, /* RGIDR_MODID[390]:IPMMURT015*/ + [369] = {0xFD4421ACU, 0x0000004EU}, /* RGIDR_MODID[391]:IPMMURT002*/ + [370] = {0xFD4421B0U, 0x0000004EU}, /* RGIDR_MODID[392]:IPMMURT003*/ + [371] = {0xFD4421B4U, 0x0000004EU}, /* RGIDR_MODID[393]:IPMMURT004*/ + [372] = {0xFD4421B8U, 0x0000004EU}, /* RGIDR_MODID[394]:IPMMURT005*/ + [373] = {0xFD4421BCU, 0x0000004EU}, /* RGIDR_MODID[395]:IPMMURT006*/ + [374] = {0xFD4421C0U, 0x0000004EU}, /* RGIDR_MODID[396]:IPMMURT007*/ + [375] = {0xFD4421C4U, 0x0000004EU}, /* RGIDR_MODID[397]:IPMMURT008*/ + [376] = {0xFD4421C8U, 0x0000004EU}, /* RGIDR_MODID[398]:IPMMURT009*/ + [377] = {0xFD4421CCU, 0x0000004EU}, /* RGIDR_MODID[399]:IPKMURT101*/ + [378] = {0xFD4421D0U, 0x0000004EU}, /* RGIDR_MODID[400]:IPMMURT110*/ + [379] = {0xFD4421D4U, 0x0000004EU}, /* RGIDR_MODID[401]:IPMMURT111*/ + [380] = {0xFD4421D8U, 0x0000004EU}, /* RGIDR_MODID[402]:IPMMURT112*/ + [381] = {0xFD4421DCU, 0x0000004EU}, /* RGIDR_MODID[403]:IPMMURT113*/ + [382] = {0xFD4421E0U, 0x0000004EU}, /* RGIDR_MODID[404]:IPMMURT114*/ + [383] = {0xFD4421E4U, 0x0000004EU}, /* RGIDR_MODID[405]:IPMMURT115*/ + [384] = {0xFD4421E8U, 0x0000004EU}, /* RGIDR_MODID[406]:IPMMURT102*/ + [385] = {0xFD4421ECU, 0x0000004EU}, /* RGIDR_MODID[407]:IPMMURT103*/ + [386] = {0xFD4421F0U, 0x0000004EU}, /* RGIDR_MODID[408]:IPMMURT104*/ + [387] = {0xFD4421F4U, 0x0000004EU}, /* RGIDR_MODID[409]:IPMMURT105*/ + [388] = {0xFD4421F8U, 0x0000004EU}, /* RGIDR_MODID[410]:IPMMURT106*/ + [389] = {0xFD4421FCU, 0x0000004EU}, /* RGIDR_MODID[411]:IPMMURT107*/ + [390] = {0xFD442200U, 0x0000004BU}, /* RGIDR_MODID[412]:RTDM000*/ + [391] = {0xFD442204U, 0x0000004BU}, /* RGIDR_MODID[413]:RTDM001*/ + [392] = {0xFD442208U, 0x0000004BU}, /* RGIDR_MODID[414]:RTDM010*/ + [393] = {0xFD44220CU, 0x0000004BU}, /* RGIDR_MODID[415]:RTDM011*/ + [394] = {0xFD442210U, 0x0000004BU}, /* RGIDR_MODID[416]:RTDM012*/ + [395] = {0xFD442214U, 0x0000004BU}, /* RGIDR_MODID[417]:RTDM013*/ + [396] = {0xFD442218U, 0x0000004BU}, /* RGIDR_MODID[418]:RTDM014*/ + [397] = {0xFD44221CU, 0x0000004BU}, /* RGIDR_MODID[419]:RTDM015*/ + [398] = {0xFD442220U, 0x0000004BU}, /* RGIDR_MODID[420]:RTDM002*/ + [399] = {0xFD442224U, 0x0000004BU}, /* RGIDR_MODID[421]:RTDM003*/ + [400] = {0xFD442228U, 0x0000004BU}, /* RGIDR_MODID[422]:RTDM004*/ + [401] = {0xFD44222CU, 0x0000004BU}, /* RGIDR_MODID[423]:RTDM005*/ + [402] = {0xFD442230U, 0x0000004BU}, /* RGIDR_MODID[424]:RTDM006*/ + [403] = {0xFD442234U, 0x0000004BU}, /* RGIDR_MODID[425]:RTDM007*/ + [404] = {0xFD442238U, 0x0000004BU}, /* RGIDR_MODID[426]:RTDM008*/ + [405] = {0xFD44223CU, 0x0000004BU}, /* RGIDR_MODID[427]:RTDM009*/ + [406] = {0xFD442240U, 0x0000004BU}, /* RGIDR_MODID[428]:RTDM100*/ + [407] = {0xFD442244U, 0x0000004BU}, /* RGIDR_MODID[429]:RTDM101*/ + [408] = {0xFD442248U, 0x0000004BU}, /* RGIDR_MODID[430]:RTDM110*/ + [409] = {0xFD44224CU, 0x0000004BU}, /* RGIDR_MODID[431]:RTDM111*/ + [410] = {0xFD442250U, 0x0000004BU}, /* RGIDR_MODID[432]:RTDM112*/ + [411] = {0xFD442254U, 0x0000004BU}, /* RGIDR_MODID[433]:RTDM113*/ + [412] = {0xFD442258U, 0x0000004BU}, /* RGIDR_MODID[434]:RTDM114*/ + [413] = {0xFD44225CU, 0x0000004BU}, /* RGIDR_MODID[435]:RTDM115*/ + [414] = {0xFD442260U, 0x0000004BU}, /* RGIDR_MODID[436]:RTDM102*/ + [415] = {0xFD442264U, 0x0000004BU}, /* RGIDR_MODID[437]:RTDM103*/ + [416] = {0xFD442268U, 0x0000004BU}, /* RGIDR_MODID[438]:RTDM104*/ + [417] = {0xFD44226CU, 0x0000004BU}, /* RGIDR_MODID[439]:RTDM105*/ + [418] = {0xFD442270U, 0x0000004BU}, /* RGIDR_MODID[440]:RTDM106*/ + [419] = {0xFD442274U, 0x0000004BU}, /* RGIDR_MODID[441]:RTDM107*/ + [420] = {0xFD442278U, 0x0000004BU}, /* RGIDR_MODID[442]:RTDM108*/ + [421] = {0xFD44227CU, 0x0000004BU}, /* RGIDR_MODID[443]:RTDM109*/ + [422] = {0xFD442300U, 0x0000004EU}, /* RGIDR_MODID[444]:IPMMURT108*/ + [423] = {0xFD442304U, 0x0000004EU}, /* RGIDR_MODID[445]:IPMMURT109*/ + [424] = {0xFD442308U, 0x00000001U}, /* RGIDR_MODID[446]:SYSRAM01*/ + [425] = {0xFD44230CU, 0x0000000BU}, /* RGIDR_MODID[447]:SYSRAM02*/ + [426] = {0xFD442310U, 0x00000001U}, /* RGIDR_MODID[448]:SYSRAM03*/ + [427] = {0xFD442314U, 0x00000001U}, /* RGIDR_MODID[449]:SYSRAM04*/ + [428] = {0xFD442318U, 0x00000001U}, /* RGIDR_MODID[450]:SYSRAM05*/ + [429] = {0xFD44231CU, 0x00000001U}, /* RGIDR_MODID[451]:SYSRAM06*/ + [430] = {0xFD442320U, 0x00000000U}, /* RGIDR_MODID[452]:SYSRAM07*/ + [431] = {0xFD442324U, 0x0000000BU}, /* RGIDR_MODID[453]:SYSRAM11*/ + [432] = {0xFD442328U, 0x0000000BU}, /* RGIDR_MODID[454]:SYSRAM12*/ + [433] = {0xFD44232CU, 0x0000000BU}, /* RGIDR_MODID[455]:SYSRAM13*/ + [434] = {0xFD442330U, 0x0000000BU}, /* RGIDR_MODID[456]:SYSRAM14*/ + [435] = {0xFD442334U, 0x0000000BU}, /* RGIDR_MODID[457]:SYSRAM15*/ + [436] = {0xFD442338U, 0x0000000BU}, /* RGIDR_MODID[458]:SYSRAM16*/ + [437] = {0xFD44233CU, 0x00000000U}, /* RGIDR_MODID[459]:SYSRAM17*/ + [438] = {0xFD442360U, 0x00000002U}, /* RGIDR_MODID[460]:BKBUF*/ + [439] = {0xFD442364U, 0x00000002U}, /* RGIDR_MODID[461]:AXICR52SS1*/ + [440] = {0xFD442368U, 0x00000002U}, /* RGIDR_MODID[462]:AXICR52SS2*/ + [441] = {0xFC862000U, 0x0000000FU}, /* RGIDR_MODID[463]:ARSC0*/ + /* After setting */ /* RGIDR_MODID[464]:ARSC1*/ + /* After setting */ /* RGIDR_MODID[465]:ARSC2*/ + [442] = {0xFC86200CU, 0x0000000FU}, /* RGIDR_MODID[466]:ARSC3*/ + [443] = {0xFC862010U, 0x0000000FU}, /* RGIDR_MODID[467]:ARSC4*/ + [444] = {0xFC862014U, 0x0000000FU}, /* RGIDR_MODID[468]:ARSC5*/ + [445] = {0xFC862018U, 0x0000000FU}, /* RGIDR_MODID[469]:ARSC6*/ + [446] = {0xFC86201CU, 0x0000000FU}, /* RGIDR_MODID[470]:ARSC7*/ + [447] = {0xFC862020U, 0x00000000U}, /* RGIDR_MODID[471]:ARSC8*/ + [448] = {0xFC862024U, 0x0000000FU}, /* RGIDR_MODID[472]:ARSTM0*/ + /* After setting */ /* RGIDR_MODID[473]:ARSTM1*/ + [449] = {0xFC86202CU, 0x0000000EU}, /* RGIDR_MODID[474]:CSD1S*/ + [450] = {0xFC862030U, 0x0000000EU}, /* RGIDR_MODID[475]:AXIFBABUSTOP0*/ + /* After setting */ /* RGIDR_MODID[476]:ARSTM2*/ + [451] = {0xFC86203CU, 0x0000000FU}, /* RGIDR_MODID[477]:ARSTM3*/ + [452] = {0xFC862040U, 0x0000000FU}, /* RGIDR_MODID[478]:ARSTM4*/ + [453] = {0xFC862044U, 0x0000000FU}, /* RGIDR_MODID[479]:ARSTM5*/ + [454] = {0xFC862048U, 0x0000000FU}, /* RGIDR_MODID[480]:ARSTM6*/ + [455] = {0xFC86204CU, 0x0000000FU}, /* RGIDR_MODID[481]:ARSTM7*/ + [456] = {0xFC862050U, 0x00000000U}, /* RGIDR_MODID[482]:ARSTM8*/ + [457] = {0xFC862054U, 0x0000000FU}, /* RGIDR_MODID[483]:ECMTOP*/ + [458] = {0xFC862058U, 0x0000000EU}, /* RGIDR_MODID[484]:FBA*/ + [459] = {0xFC86205CU, 0x0000000EU}, /* RGIDR_MODID[485]:FBC*/ + [460] = {0xFC862034U, 0x0000000CU}, /* RGIDR_MODID[486]:AXICCI00*/ + [461] = {0xFC862060U, 0x0000000CU}, /* RGIDR_MODID[487]:AXICCI01*/ + [462] = {0xFC862064U, 0x0000000CU}, /* RGIDR_MODID[488]:AXICCI10*/ + [463] = {0xFC862068U, 0x0000000CU}, /* RGIDR_MODID[489]:AXICCI11*/ + [464] = {0xFC86206CU, 0x0000000CU}, /* RGIDR_MODID[490]:AXICCI12*/ + [465] = {0xFC862070U, 0x0000000CU}, /* RGIDR_MODID[491]:AXICCI13*/ + [466] = {0xFC862074U, 0x0000000CU}, /* RGIDR_MODID[492]:AXICCI14*/ + [467] = {0xFC862078U, 0x0000000CU}, /* RGIDR_MODID[493]:AXICCI15*/ + [468] = {0xFC86207CU, 0x0000000CU}, /* RGIDR_MODID[494]:AXICCI2*/ + [469] = {0xFC862080U, 0x0000000CU}, /* RGIDR_MODID[495]:AXICCI3*/ + [470] = {0xFC862084U, 0x0000000CU}, /* RGIDR_MODID[496]:AXICCI4*/ + [471] = {0xFC862088U, 0x0000000CU}, /* RGIDR_MODID[497]:AXICCI5*/ + [472] = {0xFC86208CU, 0x0000000CU}, /* RGIDR_MODID[498]:AXICCI6*/ + [473] = {0xFC862090U, 0x0000000CU}, /* RGIDR_MODID[499]:AXICCI7*/ + [474] = {0xFC862094U, 0x0000000CU}, /* RGIDR_MODID[500]:AXICCI8*/ + [475] = {0xFC862098U, 0x0000000FU}, /* RGIDR_MODID[501]:AXICCI9*/ + [476] = {0xFC8620A0U, 0x0000000FU}, /* RGIDR_MODID[502]:ECMSTM*/ + [477] = {0xFCB82000U, 0x0000002CU}, /* RGIDR_MODID[503]:DMASSI00*/ + [478] = {0xFCB82004U, 0x0000002CU}, /* RGIDR_MODID[504]:DMASSI01*/ + [479] = {0xFCB82008U, 0x0000002CU}, /* RGIDR_MODID[505]:DMASSI02*/ + [480] = {0xFCB8200CU, 0x0000002CU}, /* RGIDR_MODID[506]:DMASSI03*/ + [481] = {0xFCB82010U, 0x0000002CU}, /* RGIDR_MODID[507]:DMASSI04*/ + [482] = {0xFCB82014U, 0x0000004EU}, /* RGIDR_MODID[508]:DMAI2C0*/ + [483] = {0xFCB82018U, 0x0000004EU}, /* RGIDR_MODID[509]:DMAI2C1*/ + [484] = {0xFCB8201CU, 0x0000004EU}, /* RGIDR_MODID[510]:DMAI2C2*/ + [485] = {0xFCB82020U, 0x0000004EU}, /* RGIDR_MODID[511]:DMAI2C3*/ + [486] = {0xFCB8202CU, 0x0000002CU}, /* RGIDR_MODID[512]:DMASSI05*/ + [487] = {0xFCB82030U, 0x0000002CU}, /* RGIDR_MODID[513]:DMASSI06*/ + [488] = {0xFCB82034U, 0x0000002CU}, /* RGIDR_MODID[514]:DMASSI07*/ + [489] = {0xFDDC2000U, 0x00000007U}, /* RGIDR_MODID[515]:ARMM*/ + /* After setting */ /* RGIDR_MODID[516]:AXIARNMM*/ + [490] = {0xFDDC2008U, 0x0000000FU}, /* RGIDR_MODID[517]:ARSM0*/ + /* After setting */ /* RGIDR_MODID[518]:ARSM1*/ + /* After setting */ /* RGIDR_MODID[519]:ARSM2*/ + [491] = {0xFDDC2014U, 0x0000000FU}, /* RGIDR_MODID[520]:AXIQOS0*/ + [492] = {0xFDDC2018U, 0x0000000FU}, /* RGIDR_MODID[521]:AXIQOS1*/ + [493] = {0xFDDC201CU, 0x0000000FU}, /* RGIDR_MODID[522]:AXIQOS2*/ + [494] = {0xFDDC2020U, 0x0000000FU}, /* RGIDR_MODID[523]:AXIQOS3*/ + [495] = {0xFDDC2024U, 0x0000000FU}, /* RGIDR_MODID[524]:AXIQOS4*/ + [496] = {0xFDDC2028U, 0x0000000FU}, /* RGIDR_MODID[525]:AXIQOS5*/ + [497] = {0xFDDC2034U, 0x0000000FU}, /* RGIDR_MODID[526]:ARSM3*/ + [498] = {0xFDDC2038U, 0x0000000FU}, /* RGIDR_MODID[527]:ARSM4*/ + [499] = {0xFDDC203CU, 0x0000000FU}, /* RGIDR_MODID[528]:ARSM5*/ + [500] = {0xFDDC2040U, 0x0000000FU}, /* RGIDR_MODID[529]:ARSM6*/ + [501] = {0xFDDC2044U, 0x0000000FU}, /* RGIDR_MODID[530]:ARSM7*/ + [502] = {0xFDDC2048U, 0x00000000U}, /* RGIDR_MODID[531]:ARSM8*/ + [503] = {0xFDDC204CU, 0x0000000BU}, /* RGIDR_MODID[532]:AXMM0*/ + [504] = {0xFDDC2050U, 0x0000000BU}, /* RGIDR_MODID[533]:AXMM1*/ + [505] = {0xFDDC2054U, 0x00000000U}, /* RGIDR_MODID[534]:AXMMPMON*/ + [506] = {0xFDDC2058U, 0x0000000AU}, /* RGIDR_MODID[535]:CKMMM*/ + [507] = {0xFDDC205CU, 0x0000000FU}, /* RGIDR_MODID[536]:ECMMM*/ + [508] = {0xFDDC2060U, 0x0000000EU}, /* RGIDR_MODID[537]:FBADBSC0*/ + [509] = {0xFDDC2068U, 0x0000000EU}, /* RGIDR_MODID[538]:FBAMM*/ + [510] = {0xFDDC206CU, 0x0000004EU}, /* RGIDR_MODID[539]:IPMMUMM00*/ + [511] = {0xFDDC2070U, 0x0000000FU}, /* RGIDR_MODID[540]:DBS0A0*/ + [512] = {0xFDDC2074U, 0x0000000AU}, /* RGIDR_MODID[541]:DBS0A1*/ + [513] = {0xFDDC2084U, 0x00000009U}, /* RGIDR_MODID[542]:FCPRC*/ + [514] = {0xFDDC2088U, 0x0000000FU}, /* RGIDR_MODID[543]:DBS0D0*/ + [515] = {0xFDDC208CU, 0x0000000AU}, /* RGIDR_MODID[544]:DBS0D1*/ + [516] = {0xFDDC2098U, 0x0000000EU}, /* RGIDR_MODID[545]:FBADDR*/ + [517] = {0xFDDC209CU, 0x0000004EU}, /* RGIDR_MODID[546]:IPMMUMM01*/ + [518] = {0xFDDC20A0U, 0x0000004EU}, /* RGIDR_MODID[547]:IPMMUMM10*/ + [519] = {0xFDDC20A4U, 0x0000004EU}, /* RGIDR_MODID[548]:IPMMUMM11*/ + [520] = {0xFDDC20A8U, 0x0000004EU}, /* RGIDR_MODID[549]:IPMMUMM12*/ + [521] = {0xFDDC20ACU, 0x0000004EU}, /* RGIDR_MODID[550]:IPMMUMM13*/ + [522] = {0xFDDC20B0U, 0x0000004EU}, /* RGIDR_MODID[551]:IPMMUMM14*/ + [523] = {0xFDDC20B4U, 0x0000004EU}, /* RGIDR_MODID[552]:IPMMUMM15*/ + [524] = {0xFDDC20B8U, 0x0000004EU}, /* RGIDR_MODID[553]:IPMMUMM02*/ + [525] = {0xFDDC20BCU, 0x0000004EU}, /* RGIDR_MODID[554]:IPMMUMM03*/ + [526] = {0xFDDC20C0U, 0x0000004EU}, /* RGIDR_MODID[555]:IPMMUMM04*/ + [527] = {0xFDDC20C4U, 0x0000004EU}, /* RGIDR_MODID[556]:IPMMUMM05*/ + [528] = {0xFDDC20C8U, 0x0000004EU}, /* RGIDR_MODID[557]:IPMMUMM06*/ + [529] = {0xFDDC20CCU, 0x0000004EU}, /* RGIDR_MODID[558]:IPMMUMM07*/ + [530] = {0xFDDC20D0U, 0x0000004EU}, /* RGIDR_MODID[559]:IPMMUMM08*/ + [531] = {0xFDDC20D4U, 0x0000004EU}, /* RGIDR_MODID[560]:IPMMUMM09*/ + [532] = {0xFC802000U, 0x0000000FU}, /* RGIDR_MODID[561]:ARSN0*/ + /* After setting */ /* RGIDR_MODID[562]:ARSN1*/ + /* After setting */ /* RGIDR_MODID[563]:ARSN2*/ + [533] = {0xFC80200CU, 0x0000000FU}, /* RGIDR_MODID[564]:ARSN3*/ + [534] = {0xFC802010U, 0x0000000FU}, /* RGIDR_MODID[565]:ARSN4*/ + [535] = {0xFC802014U, 0x0000000FU}, /* RGIDR_MODID[566]:ARSN5*/ + [536] = {0xFC802018U, 0x0000000FU}, /* RGIDR_MODID[567]:ARSN6*/ + [537] = {0xFC80201CU, 0x00000007U}, /* RGIDR_MODID[568]:ARSN7*/ + [538] = {0xFC802020U, 0x00000000U}, /* RGIDR_MODID[569]:ARSN8*/ + [539] = {0xFC802024U, 0x0000000FU}, /* RGIDR_MODID[570]:ECMTOP3*/ + [540] = {0xFCB52000U, 0x0000000FU}, /* RGIDR_MODID[571]:ARSD00*/ + /* After setting */ /* RGIDR_MODID[572]:ARSD01*/ + /* After setting */ /* RGIDR_MODID[573]:ARSD02*/ + [541] = {0xFCB5200CU, 0x0000000FU}, /* RGIDR_MODID[574]:ARSD03*/ + [542] = {0xFCB52010U, 0x0000000FU}, /* RGIDR_MODID[575]:ARSD04*/ + [543] = {0xFCB52014U, 0x0000000FU}, /* RGIDR_MODID[576]:ARSD05*/ + [544] = {0xFCB52018U, 0x0000000FU}, /* RGIDR_MODID[577]:ARSD06*/ + [545] = {0xFCB5201CU, 0x0000004AU}, /* RGIDR_MODID[578]:AXIFRAY*/ + [546] = {0xFCB52028U, 0x0000004FU}, /* RGIDR_MODID[579]:AXIRPC*/ + [547] = {0xFCB5202CU, 0x0000000FU}, /* RGIDR_MODID[580]:AXISDHI0*/ + [548] = {0xFCB52030U, 0x0000000FU}, /* RGIDR_MODID[581]:ARSD07*/ + [549] = {0xFCB52034U, 0x00000000U}, /* RGIDR_MODID[582]:ARSD08*/ + [550] = {0xFCB52038U, 0x0000000FU}, /* RGIDR_MODID[583]:ARSP00*/ + /* After setting */ /* RGIDR_MODID[584]:ARSP01*/ + /* After setting */ /* RGIDR_MODID[585]:ARSP02*/ + [551] = {0xFCB52044U, 0x0000000FU}, /* RGIDR_MODID[586]:ARSP03*/ + [552] = {0xFCB52048U, 0x0000000FU}, /* RGIDR_MODID[587]:ARSP04*/ + [553] = {0xFCB5204CU, 0x0000000FU}, /* RGIDR_MODID[588]:ARSP05*/ + [554] = {0xFCB52050U, 0x0000000FU}, /* RGIDR_MODID[589]:ARSP06*/ + [555] = {0xFCB52054U, 0x00000007U}, /* RGIDR_MODID[590]:ARSP07*/ + [556] = {0xFCB52058U, 0x00000000U}, /* RGIDR_MODID[591]:ARSP08*/ + [557] = {0xFCB5205CU, 0x0000004EU}, /* RGIDR_MODID[592]:IPMMUDS001*/ + [558] = {0xFCB52060U, 0x0000000AU}, /* RGIDR_MODID[593]:CKMPER0*/ + [559] = {0xFCB52064U, 0x0000000FU}, /* RGIDR_MODID[594]:ECMPER0*/ + [560] = {0xFCB52068U, 0x0000000EU}, /* RGIDR_MODID[595]:FBAPER0*/ + [561] = {0xFCB5206CU, 0x0000004EU}, /* RGIDR_MODID[596]:FSO0*/ + [562] = {0xFCB52070U, 0x0000004EU}, /* RGIDR_MODID[597]:FSO1*/ + [563] = {0xFCB52074U, 0x0000004EU}, /* RGIDR_MODID[598]:FSO10*/ + [564] = {0xFCB52078U, 0x0000004EU}, /* RGIDR_MODID[599]:FSO2*/ + [565] = {0xFCB5207CU, 0x0000004EU}, /* RGIDR_MODID[600]:FSO3*/ + [566] = {0xFCB52080U, 0x0000004EU}, /* RGIDR_MODID[601]:FSO4*/ + [567] = {0xFCB52084U, 0x0000004EU}, /* RGIDR_MODID[602]:FSO5*/ + [568] = {0xFCB52088U, 0x0000004EU}, /* RGIDR_MODID[603]:FSO6*/ + [569] = {0xFCB5208CU, 0x0000004EU}, /* RGIDR_MODID[604]:FSO7*/ + [570] = {0xFCB52090U, 0x0000004EU}, /* RGIDR_MODID[605]:FSO8*/ + [571] = {0xFCB52094U, 0x0000004EU}, /* RGIDR_MODID[606]:FSO9*/ + [572] = {0xFCB52098U, 0x0000002CU}, /* RGIDR_MODID[607]:ADG*/ + [573] = {0xFCB5209CU, 0x0000000FU}, /* RGIDR_MODID[608]:ECMSD0*/ + [574] = {0xFCB520A0U, 0x0000004EU}, /* RGIDR_MODID[609]:IPMMUDS010*/ + [575] = {0xFCB520A4U, 0x0000004EU}, /* RGIDR_MODID[610]:IPMMUDS011*/ + [576] = {0xFCB520A8U, 0x0000004EU}, /* RGIDR_MODID[611]:I2C0*/ + [577] = {0xFCB520ACU, 0x0000004EU}, /* RGIDR_MODID[612]:I2C1*/ + [578] = {0xFCB520B0U, 0x0000004EU}, /* RGIDR_MODID[613]:I2C2*/ + [579] = {0xFCB520B4U, 0x0000004EU}, /* RGIDR_MODID[614]:I2C3*/ + [580] = {0xFCB520C0U, 0x0000004EU}, /* RGIDR_MODID[615]:IPMMUDS012*/ + [581] = {0xFCB520C8U, 0x0000004EU}, /* RGIDR_MODID[616]:IPMMUDS000*/ + [582] = {0xFCB520CCU, 0x0000004EU}, /* RGIDR_MODID[617]:IPMMUDS013*/ + [583] = {0xFCB520D0U, 0x0000004EU}, /* RGIDR_MODID[618]:IPMMUDS014*/ + [584] = {0xFCB520D4U, 0x0000004EU}, /* RGIDR_MODID[619]:IPMMUDS015*/ + [585] = {0xFCB520D8U, 0x0000004EU}, /* RGIDR_MODID[620]:IPMMUDS002*/ + [586] = {0xFCB520DCU, 0x0000004EU}, /* RGIDR_MODID[621]:IPMMUDS003*/ + [587] = {0xFCB520E0U, 0x0000004EU}, /* RGIDR_MODID[622]:IPMMUDS004*/ + [588] = {0xFCB520E4U, 0x0000004EU}, /* RGIDR_MODID[623]:IPMMUDS005*/ + [589] = {0xFCB520E8U, 0x0000002CU}, /* RGIDR_MODID[624]:SSI*/ + [590] = {0xFCB520ECU, 0x0000004EU}, /* RGIDR_MODID[625]:IPMMUDS006*/ + [591] = {0xFCB520F0U, 0x0000004EU}, /* RGIDR_MODID[626]:IPMMUDS007*/ + [592] = {0xFCB520F4U, 0x0000000CU}, /* RGIDR_MODID[627]:SYDM1P*/ + [593] = {0xFCB520F8U, 0x0000004EU}, /* RGIDR_MODID[628]:IPMMUDS008*/ + [594] = {0xFCB520FCU, 0x0000000CU}, /* RGIDR_MODID[629]:SYDM2P*/ + [595] = {0xFCB52100U, 0x0000004EU}, /* RGIDR_MODID[630]:IPMMUDS009*/ + [596] = {0xFCB52240U, 0x0000000CU}, /* RGIDR_MODID[631]:SYDM100*/ + [597] = {0xFCB52244U, 0x0000000CU}, /* RGIDR_MODID[632]:SYDM101*/ + [598] = {0xFCB52248U, 0x0000000CU}, /* RGIDR_MODID[633]:SYDM110*/ + [599] = {0xFCB5224CU, 0x0000000CU}, /* RGIDR_MODID[634]:SYDM111*/ + [600] = {0xFCB52250U, 0x0000000CU}, /* RGIDR_MODID[635]:SYDM112*/ + [601] = {0xFCB52254U, 0x0000000CU}, /* RGIDR_MODID[636]:SYDM113*/ + [602] = {0xFCB52258U, 0x0000000CU}, /* RGIDR_MODID[637]:SYDM114*/ + [603] = {0xFCB5225CU, 0x0000000CU}, /* RGIDR_MODID[638]:SYDM115*/ + [604] = {0xFCB52260U, 0x0000000CU}, /* RGIDR_MODID[639]:SYDM102*/ + [605] = {0xFCB52264U, 0x0000000CU}, /* RGIDR_MODID[640]:SYDM103*/ + [606] = {0xFCB52268U, 0x0000000CU}, /* RGIDR_MODID[641]:SYDM104*/ + [607] = {0xFCB5226CU, 0x0000000CU}, /* RGIDR_MODID[642]:SYDM105*/ + [608] = {0xFCB52270U, 0x0000000CU}, /* RGIDR_MODID[643]:SYDM106*/ + [609] = {0xFCB52274U, 0x0000000CU}, /* RGIDR_MODID[644]:SYDM107*/ + [610] = {0xFCB52278U, 0x0000000CU}, /* RGIDR_MODID[645]:SYDM108*/ + [611] = {0xFCB5227CU, 0x0000000CU}, /* RGIDR_MODID[646]:SYDM109*/ + [612] = {0xFCB52280U, 0x0000000CU}, /* RGIDR_MODID[647]:SYDM200*/ + [613] = {0xFCB52284U, 0x0000000CU}, /* RGIDR_MODID[648]:SYDM201*/ + [614] = {0xFCB52288U, 0x0000000CU}, /* RGIDR_MODID[649]:SYDM210*/ + [615] = {0xFCB5228CU, 0x0000000CU}, /* RGIDR_MODID[650]:SYDM211*/ + [616] = {0xFCB52290U, 0x0000000CU}, /* RGIDR_MODID[651]:SYDM212*/ + [617] = {0xFCB52294U, 0x0000000CU}, /* RGIDR_MODID[652]:SYDM213*/ + [618] = {0xFCB52298U, 0x0000000CU}, /* RGIDR_MODID[653]:SYDM214*/ + [619] = {0xFCB5229CU, 0x0000000CU}, /* RGIDR_MODID[654]:SYDM215*/ + [620] = {0xFCB522A0U, 0x0000000CU}, /* RGIDR_MODID[655]:SYDM202*/ + [621] = {0xFCB522A4U, 0x0000000CU}, /* RGIDR_MODID[656]:SYDM203*/ + [622] = {0xFCB522A8U, 0x0000000CU}, /* RGIDR_MODID[657]:SYDM204*/ + [623] = {0xFCB522ACU, 0x0000000CU}, /* RGIDR_MODID[658]:SYDM205*/ + [624] = {0xFCB522B0U, 0x0000000CU}, /* RGIDR_MODID[659]:SYDM206*/ + [625] = {0xFCB522B4U, 0x0000000CU}, /* RGIDR_MODID[660]:SYDM207*/ + [626] = {0xFCB522B8U, 0x0000000CU}, /* RGIDR_MODID[661]:SYDM208*/ + [627] = {0xFCB522BCU, 0x0000000CU}, /* RGIDR_MODID[662]:SYDM209*/ + [628] = {0xFC682000U, 0x0000000FU}, /* RGIDR_MODID[663]:ARVC0*/ + /* After setting */ /* RGIDR_MODID[664]:ARVC1*/ + /* After setting */ /* RGIDR_MODID[665]:ARVC2*/ + [629] = {0xFC68200CU, 0x0000000FU}, /* RGIDR_MODID[666]:ARVC3*/ + [630] = {0xFC682010U, 0x0000000EU}, /* RGIDR_MODID[667]:AXIFBABUSVC*/ + [631] = {0xFC682014U, 0x0000000FU}, /* RGIDR_MODID[668]:ARVC4*/ + [632] = {0xFC682018U, 0x0000000FU}, /* RGIDR_MODID[669]:ARVC5*/ + [633] = {0xFC68201CU, 0x0000000FU}, /* RGIDR_MODID[670]:ARVC6*/ + [634] = {0xFC682020U, 0x0000000FU}, /* RGIDR_MODID[671]:ARVC7*/ + [635] = {0xFC682024U, 0x00000000U}, /* RGIDR_MODID[672]:ARVC8*/ + [636] = {0xFC68202CU, 0x0000000FU}, /* RGIDR_MODID[673]:ECMVC0*/ + [637] = {0xFC682034U, 0x0000004EU}, /* RGIDR_MODID[674]:IMR0*/ + [638] = {0xFC682038U, 0x0000004EU}, /* RGIDR_MODID[675]:IMR1*/ + [639] = {0xFC68203CU, 0x0000004EU}, /* RGIDR_MODID[676]:IPMMUVC01*/ + [640] = {0xFC682040U, 0x0000004EU}, /* RGIDR_MODID[677]:IPMMUVC10*/ + [641] = {0xFC682044U, 0x0000000CU}, /* RGIDR_MODID[678]:IMS0*/ + [642] = {0xFC682048U, 0x0000000CU}, /* RGIDR_MODID[679]:IMS1*/ + [643] = {0xFC68204CU, 0x0000004EU}, /* RGIDR_MODID[680]:IPMMUVC00*/ + [644] = {0xFC682050U, 0x0000004EU}, /* RGIDR_MODID[681]:IPMMUVC11*/ + [645] = {0xFC682054U, 0x0000004EU}, /* RGIDR_MODID[682]:IPMMUVC12*/ + [646] = {0xFC682058U, 0x0000004EU}, /* RGIDR_MODID[683]:IPMMUVC13*/ + [647] = {0xFC68205CU, 0x0000004EU}, /* RGIDR_MODID[684]:IPMMUVC14*/ + [648] = {0xFC682060U, 0x0000004EU}, /* RGIDR_MODID[685]:IPMMUVC15*/ + [649] = {0xFC682064U, 0x0000004EU}, /* RGIDR_MODID[686]:IPMMUVC02*/ + [650] = {0xFC682068U, 0x0000004EU}, /* RGIDR_MODID[687]:IPMMUVC03*/ + [651] = {0xFC68206CU, 0x0000004EU}, /* RGIDR_MODID[688]:IPMMUVC04*/ + [652] = {0xFC682070U, 0x0000004EU}, /* RGIDR_MODID[689]:IPMMUVC05*/ + [653] = {0xFC682074U, 0x0000004EU}, /* RGIDR_MODID[690]:IPMMUVC06*/ + [654] = {0xFC682078U, 0x0000004EU}, /* RGIDR_MODID[691]:IPMMUVC07*/ + [655] = {0xFC68207CU, 0x0000004EU}, /* RGIDR_MODID[692]:IPMMUVC08*/ + [656] = {0xFC682080U, 0x0000004EU}, /* RGIDR_MODID[693]:IPMMUVC09*/ + [657] = {0xFC682084U, 0x00000028U}, /* RGIDR_MODID[694]:IV1ES*/ + [658] = {0xFEBE2000U, 0x0000004EU}, /* RGIDR_MODID[695]:CSITOP0*/ + [659] = {0xFEBE2004U, 0x0000000FU}, /* RGIDR_MODID[696]:ARVI10*/ + /* After setting */ /* RGIDR_MODID[697]:ARVI11*/ + /* After setting */ /* RGIDR_MODID[698]:ARVI12*/ + [660] = {0xFEBE2010U, 0x0000000FU}, /* RGIDR_MODID[699]:ARVI13*/ + [661] = {0xFEBE2014U, 0x0000000FU}, /* RGIDR_MODID[700]:ARVI14*/ + [662] = {0xFEBE2018U, 0x0000000FU}, /* RGIDR_MODID[701]:ARVI15*/ + [663] = {0xFEBE201CU, 0x0000000FU}, /* RGIDR_MODID[702]:ARVI16*/ + [664] = {0xFEBE2020U, 0x0000000FU}, /* RGIDR_MODID[703]:ARVI17*/ + [665] = {0xFEBE2024U, 0x00000000U}, /* RGIDR_MODID[704]:ARVI18*/ + [666] = {0xFEBE202CU, 0x0000004EU}, /* RGIDR_MODID[705]:CSITOP1*/ + [667] = {0xFEBE2034U, 0x0000004EU}, /* RGIDR_MODID[706]:DSITLINK0*/ + [668] = {0xFEBE203CU, 0x0000000FU}, /* RGIDR_MODID[707]:ECMVIO1*/ + [669] = {0xFEBE2044U, 0x0000004EU}, /* RGIDR_MODID[708]:IPMMUVI001*/ + [670] = {0xFEBE2048U, 0x0000000CU}, /* RGIDR_MODID[709]:FCPVX0*/ + [671] = {0xFEBE2058U, 0x0000004EU}, /* RGIDR_MODID[710]:IPMMUVI000*/ + [672] = {0xFEBE205CU, 0x0000004EU}, /* RGIDR_MODID[711]:IPMMUVI100*/ + [673] = {0xFEBE2060U, 0x0000004EU}, /* RGIDR_MODID[712]:IPMMUVI010*/ + [674] = {0xFEBE2064U, 0x0000004EU}, /* RGIDR_MODID[713]:IPMMUVI011*/ + [675] = {0xFEBE2068U, 0x0000004EU}, /* RGIDR_MODID[714]:VSPX0*/ + [676] = {0xFEBE2078U, 0x0000004EU}, /* RGIDR_MODID[715]:IPMMUVI012*/ + [677] = {0xFEBE207CU, 0x0000004EU}, /* RGIDR_MODID[716]:IPMMUVI013*/ + [678] = {0xFEBE2080U, 0x0000004EU}, /* RGIDR_MODID[717]:IPMMUVI014*/ + [679] = {0xFEBE2084U, 0x0000004EU}, /* RGIDR_MODID[718]:IPMMUVI015*/ + [680] = {0xFEBE2088U, 0x0000004EU}, /* RGIDR_MODID[719]:IPMMUVI002*/ + [681] = {0xFEBE208CU, 0x0000004EU}, /* RGIDR_MODID[720]:IPMMUVI003*/ + [682] = {0xFEBE2090U, 0x0000004EU}, /* RGIDR_MODID[721]:IPMMUVI004*/ + [683] = {0xFEBE2094U, 0x0000004EU}, /* RGIDR_MODID[722]:IPMMUVI005*/ + [684] = {0xFEBE2098U, 0x0000004EU}, /* RGIDR_MODID[723]:IPMMUVI006*/ + [685] = {0xFEBE209CU, 0x0000004EU}, /* RGIDR_MODID[724]:IPMMUVI007*/ + [686] = {0xFEBE20A0U, 0x0000004EU}, /* RGIDR_MODID[725]:IPMMUVI008*/ + [687] = {0xFEBE20A4U, 0x0000004EU}, /* RGIDR_MODID[726]:IPMMUVI009*/ + [688] = {0xFEBE20A8U, 0x0000004EU}, /* RGIDR_MODID[727]:IPMMUVI101*/ + [689] = {0xFEBE20ACU, 0x0000004EU}, /* RGIDR_MODID[728]:IPMMUVI110*/ + [690] = {0xFEBE20B0U, 0x0000004EU}, /* RGIDR_MODID[729]:IPMMUVI111*/ + [691] = {0xFEBE20B4U, 0x0000004EU}, /* RGIDR_MODID[730]:IPMMUVI112*/ + [692] = {0xFEBE20B8U, 0x0000004EU}, /* RGIDR_MODID[731]:IPMMUVI113*/ + [693] = {0xFEBE20BCU, 0x0000004EU}, /* RGIDR_MODID[732]:IPMMUVI114*/ + [694] = {0xFEBE20C0U, 0x0000004EU}, /* RGIDR_MODID[733]:IPMMUVI115*/ + [695] = {0xFEBE20C4U, 0x0000004EU}, /* RGIDR_MODID[734]:IPMMUVI102*/ + [696] = {0xFEBE20C8U, 0x0000004EU}, /* RGIDR_MODID[735]:IPMMUVI103*/ + [697] = {0xFEBE20CCU, 0x0000004EU}, /* RGIDR_MODID[736]:IPMMUVI104*/ + [698] = {0xFEBE20D0U, 0x0000004EU}, /* RGIDR_MODID[737]:IPMMUVI105*/ + [699] = {0xFEBE20D4U, 0x0000004EU}, /* RGIDR_MODID[738]:IPMMUVI106*/ + [700] = {0xFEBE20D8U, 0x0000004EU}, /* RGIDR_MODID[739]:IPMMUVI107*/ + [701] = {0xFEBE20DCU, 0x0000004EU}, /* RGIDR_MODID[740]:IPMMUVI108*/ + [702] = {0xFEBE20E0U, 0x0000004EU}, /* RGIDR_MODID[741]:IPMMUVI109*/ + [703] = {0xFEBE2104U, 0x0000000EU}, /* RGIDR_MODID[742]:AXIFBABUSVIO*/ + [704] = {0xFEBF2000U, 0x0000000FU}, /* RGIDR_MODID[743]:ARVI0*/ + /* After setting */ /* RGIDR_MODID[744]:ARVI1*/ + /* After setting */ /* RGIDR_MODID[745]:ARVI2*/ + [705] = {0xFEBF200CU, 0x0000000FU}, /* RGIDR_MODID[746]:ARVI3*/ + [706] = {0xFEBF2010U, 0x0000000FU}, /* RGIDR_MODID[747]:ARVI4*/ + [707] = {0xFEBF2014U, 0x0000000FU}, /* RGIDR_MODID[748]:ARVI5*/ + [708] = {0xFEBF2018U, 0x0000000FU}, /* RGIDR_MODID[749]:ARVI6*/ + [709] = {0xFEBF201CU, 0x0000000FU}, /* RGIDR_MODID[750]:ARVI7*/ + [710] = {0xFEBF2020U, 0x00000000U}, /* RGIDR_MODID[751]:ARVI8*/ + [711] = {0xFEBF2024U, 0x0000000FU}, /* RGIDR_MODID[752]:ECMVIO0*/ + [712] = {0xFEBF2028U, 0x0000004EU}, /* RGIDR_MODID[753]:ISP0*/ + [713] = {0xFEBF202CU, 0x0000004EU}, /* RGIDR_MODID[754]:ISP0CORE*/ + [714] = {0xFEBF2030U, 0x0000004EU}, /* RGIDR_MODID[755]:ISP1*/ + [715] = {0xFEBF2054U, 0x0000004EU}, /* RGIDR_MODID[756]:VIN00*/ + [716] = {0xFEBF2058U, 0x0000004EU}, /* RGIDR_MODID[757]:VIN01*/ + [717] = {0xFEBF205CU, 0x0000004EU}, /* RGIDR_MODID[758]:VIN02*/ + [718] = {0xFEBF2060U, 0x0000004EU}, /* RGIDR_MODID[759]:VIN03*/ + [719] = {0xFEBF2064U, 0x0000004EU}, /* RGIDR_MODID[760]:VIN04*/ + [720] = {0xFEBF2068U, 0x0000004EU}, /* RGIDR_MODID[761]:VIN05*/ + [721] = {0xFEBF206CU, 0x0000004EU}, /* RGIDR_MODID[762]:VIN06*/ + [722] = {0xFEBF2070U, 0x0000004EU}, /* RGIDR_MODID[763]:VIN07*/ + [723] = {0xFEBF2074U, 0x0000004EU}, /* RGIDR_MODID[764]:VIN10*/ + [724] = {0xFEBF2078U, 0x0000004EU}, /* RGIDR_MODID[765]:VIN11*/ + [725] = {0xFEBF207CU, 0x0000004EU}, /* RGIDR_MODID[766]:VIN12*/ + [726] = {0xFEBF2080U, 0x0000004EU}, /* RGIDR_MODID[767]:VIN13*/ + [727] = {0xFEBF2084U, 0x0000004EU}, /* RGIDR_MODID[768]:VIN14*/ + [728] = {0xFEBF2088U, 0x0000004EU}, /* RGIDR_MODID[769]:VIN15*/ + [729] = {0xFEBF208CU, 0x0000004EU}, /* RGIDR_MODID[770]:VIN16*/ + [730] = {0xFEBF2090U, 0x0000004EU}, /* RGIDR_MODID[771]:VIN17*/ + [731] = {0xFC312000U, 0x0000000FU}, /* RGIDR_MODID[772]:ARVIP00*/ + /* After setting */ /* RGIDR_MODID[773]:ARVIP01*/ + /* After setting */ /* RGIDR_MODID[774]:ARVIP02*/ + [732] = {0xFC31200CU, 0x0000000FU}, /* RGIDR_MODID[775]:ARVIP03*/ + [733] = {0xFC312010U, 0x0000000EU}, /* RGIDR_MODID[776]:AXIFBABUSVIP0*/ + [734] = {0xFC312014U, 0x0000000FU}, /* RGIDR_MODID[777]:ARVIP04*/ + [735] = {0xFC312018U, 0x0000000FU}, /* RGIDR_MODID[778]:ARVIP05*/ + [736] = {0xFC31201CU, 0x0000000FU}, /* RGIDR_MODID[779]:ARVIP06*/ + [737] = {0xFC312020U, 0x00000007U}, /* RGIDR_MODID[780]:ARVIP07*/ + [738] = {0xFC312024U, 0x00000000U}, /* RGIDR_MODID[781]:ARVIP08*/ + [739] = {0xFC31202CU, 0x0000000FU}, /* RGIDR_MODID[782]:ECMVIP0*/ + [740] = {0xFC312030U, 0x0000004EU}, /* RGIDR_MODID[783]:IPMMUVIP000*/ + [741] = {0xFC312038U, 0x0000004EU}, /* RGIDR_MODID[784]:SMPO0*/ + [742] = {0xFC31203CU, 0x0000004EU}, /* RGIDR_MODID[785]:SMPS0*/ + [743] = {0xFC312040U, 0x0000004EU}, /* RGIDR_MODID[786]:UMFL0*/ + [744] = {0xFC312044U, 0x0000004EU}, /* RGIDR_MODID[787]:IPMMUVIP001*/ + [745] = {0xFC312048U, 0x0000004EU}, /* RGIDR_MODID[788]:IPMMUVIP010*/ + [746] = {0xFC31204CU, 0x0000004EU}, /* RGIDR_MODID[789]:IPMMUVIP011*/ + [747] = {0xFC312050U, 0x0000004EU}, /* RGIDR_MODID[790]:UMFL0M_W*/ + [748] = {0xFC312054U, 0x0000004EU}, /* RGIDR_MODID[791]:IPMMUVIP012*/ + [749] = {0xFC312058U, 0x0000004EU}, /* RGIDR_MODID[792]:IPMMUVIP013*/ + [750] = {0xFC31205CU, 0x0000004EU}, /* RGIDR_MODID[793]:IPMMUVIP014*/ + [751] = {0xFC312060U, 0x0000004EU}, /* RGIDR_MODID[794]:IPMMUVIP015*/ + [752] = {0xFC312064U, 0x0000004EU}, /* RGIDR_MODID[795]:IPMMUVIP002*/ + [753] = {0xFC312068U, 0x0000004EU}, /* RGIDR_MODID[796]:IPMMUVIP003*/ + [754] = {0xFC31206CU, 0x0000004EU}, /* RGIDR_MODID[797]:IPMMUVIP004*/ + [755] = {0xFC312070U, 0x0000004EU}, /* RGIDR_MODID[798]:IPMMUVIP005*/ + [756] = {0xFC312074U, 0x0000004EU}, /* RGIDR_MODID[799]:IPMMUVIP006*/ + [757] = {0xFC312078U, 0x0000004EU}, /* RGIDR_MODID[800]:IPMMUVIP007*/ + [758] = {0xFC31207CU, 0x0000004EU}, /* RGIDR_MODID[801]:IPMMUVIP008*/ + [759] = {0xFC312080U, 0x0000004EU}, /* RGIDR_MODID[802]:IPMMUVIP009*/ + [760] = {0xFC8820A0U, 0x0000000FU}, /* RGIDR_MODID[803]:ARDSP0*/ + /* After setting */ /* RGIDR_MODID[804]:ARDSP1*/ + /* After setting */ /* RGIDR_MODID[805]:ARDSP2*/ + [761] = {0xFC8820ACU, 0x0000000FU}, /* RGIDR_MODID[806]:ARDSP3*/ + [762] = {0xFC8820B0U, 0x0000000FU}, /* RGIDR_MODID[807]:ARDSP4*/ + [763] = {0xFC8820B4U, 0x0000000FU}, /* RGIDR_MODID[808]:ARDSP5*/ + [764] = {0xFC8820B8U, 0x0000000FU}, /* RGIDR_MODID[809]:ARDSP6*/ + [765] = {0xFC8820BCU, 0x0000000FU}, /* RGIDR_MODID[810]:ARDSP7*/ + [766] = {0xFC8820C0U, 0x0000000FU}, /* RGIDR_MODID[811]:ECMDSP*/ + [767] = {0xFC882090U, 0x0000000CU}, /* RGIDR_MODID[812]:AXIDSP0*/ + [768] = {0xFC882094U, 0x0000000CU}, /* RGIDR_MODID[813]:AXIDSP1*/ + [769] = {0xFC882098U, 0x0000000CU}, /* RGIDR_MODID[814]:AXIDSP2*/ + [770] = {0xFC88209CU, 0x0000000CU}, /* RGIDR_MODID[815]:AXIDSP3*/ + [771] = {0xFC8820C4U, 0x0000004EU}, /* RGIDR_MODID[816]:IMPM0100*/ + [772] = {0xFC8820C8U, 0x0000004EU}, /* RGIDR_MODID[817]:IMPM0101*/ + [773] = {0xFC8820CCU, 0x0000004EU}, /* RGIDR_MODID[818]:IMPM0102*/ + [774] = {0xFC8820D0U, 0x0000004EU}, /* RGIDR_MODID[819]:IMPM0103*/ + [775] = {0xFC8820D4U, 0x0000004EU}, /* RGIDR_MODID[820]:IMPM0104*/ + [776] = {0xFC8820D8U, 0x0000004EU}, /* RGIDR_MODID[821]:IMPM0105*/ + [777] = {0xFC8820DCU, 0x0000004EU}, /* RGIDR_MODID[822]:IMPM0106*/ + [778] = {0xFC8820E0U, 0x0000004EU}, /* RGIDR_MODID[823]:IMPM0107*/ + [779] = {0xFC8820E4U, 0x0000004EU}, /* RGIDR_MODID[824]:IMPM0200*/ + [780] = {0xFC8820E8U, 0x0000004EU}, /* RGIDR_MODID[825]:IMPM0201*/ + [781] = {0xFC8820ECU, 0x0000004EU}, /* RGIDR_MODID[826]:IMPS0000*/ + [782] = {0xFC8820F0U, 0x0000004EU}, /* RGIDR_MODID[827]:IMPS0001*/ + [783] = {0xFC8820F4U, 0x0000004EU}, /* RGIDR_MODID[828]:IMPS0002*/ + [784] = {0xFC8820F8U, 0x0000004EU}, /* RGIDR_MODID[829]:IMPS0003*/ + [785] = {0xFC8820FCU, 0x0000004EU}, /* RGIDR_MODID[830]:IMPS0100*/ + [786] = {0xFC882100U, 0x0000004EU}, /* RGIDR_MODID[831]:IMPS0101*/ + [787] = {0xFC882104U, 0x0000004EU}, /* RGIDR_MODID[832]:IMPS0102*/ + [788] = {0xFC882108U, 0x0000004EU}, /* RGIDR_MODID[833]:IMPS0103*/ + [789] = {0xFC88210CU, 0x0000004EU}, /* RGIDR_MODID[834]:IMPS0104*/ + [790] = {0xFC882110U, 0x0000004EU}, /* RGIDR_MODID[835]:IMPS0105*/ + [791] = {0xFC882114U, 0x0000004EU}, /* RGIDR_MODID[836]:IMPS0106*/ + [792] = {0xFC882118U, 0x0000004EU}, /* RGIDR_MODID[837]:IMPS0107*/ + [793] = {0xFC88211CU, 0x0000004EU}, /* RGIDR_MODID[838]:IMPS0108*/ + [794] = {0xFC882120U, 0x0000004EU}, /* RGIDR_MODID[839]:IMPS0109*/ + [795] = {0xFC882124U, 0x0000004EU}, /* RGIDR_MODID[840]:IMPS0110*/ + [796] = {0xFC882128U, 0x0000004EU}, /* RGIDR_MODID[841]:IMPS0111*/ + [797] = {0xFC88212CU, 0x0000004EU}, /* RGIDR_MODID[842]:IMPS0200*/ + [798] = {0xFC882130U, 0x0000004EU}, /* RGIDR_MODID[843]:IMPS0201*/ + [799] = {0xFC882134U, 0x0000004EU}, /* RGIDR_MODID[844]:IMPS0202*/ + [801] = {0xFDDB9660U, 0x0000000FU}, /* RGIDR_MODID[845]:ARCC*/ + [800] = {0xFDDB9674U, 0x0000000FU}, /* RGIDR_MODID[846]:ARRTRAM*/ + [802] = {0xFCB52024U, 0x00000000U}, /* RGIDR_MODID[847]:RSV0*/ + [803] = {0xFC31210CU, 0x00000004U}, /* RGIDR_MODID[848]:PAP*/ + [804] = {0xFEBD2028U, 0x0000000CU}, /* RGIDR_MODID[849]:DOC*/ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_w_tbl" +const REGION_ID_SETTING_TABLE g_rgid_w_tbl[] = { + [0] = {0xFD482400U, 0x0000000EU}, /* RGIDW_MODID[0]:ARMGC0*/ + [1] = {0xFD482404U, 0x0000000EU}, /* RGIDW_MODID[1]:ARMGC1*/ + [2] = {0xFD482408U, 0x00000000U}, /* RGIDW_MODID[2]:ARMGC2*/ + [3] = {0xFD48240CU, 0x00000002U}, /* RGIDW_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDW_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDW_MODID[5]:ARRT02*/ + [4] = {0xFD482418U, 0x00000001U}, /* RGIDW_MODID[6]:ARRT03*/ + [5] = {0xFD48241CU, 0x00000002U}, /* RGIDW_MODID[7]:ARRT04*/ + [6] = {0xFD482420U, 0x00000001U}, /* RGIDW_MODID[8]:ARRT05*/ + [7] = {0xFD482424U, 0x00000002U}, /* RGIDW_MODID[9]:ARRT06*/ + [8] = {0xFD482428U, 0x00000002U}, /* RGIDW_MODID[10]:ARRT07*/ + [9] = {0xFD48242CU, 0x00000000U}, /* RGIDW_MODID[11]:ARRT08*/ + [10] = {0xFD482430U, 0x00000001U}, /* RGIDW_MODID[12]:LIFEC0*/ + [11] = {0xFD482434U, 0x0000000EU}, /* RGIDW_MODID[13]:SWDT*/ + [12] = {0xFD482438U, 0x0000006EU}, /* RGIDW_MODID[14]:TMU0*/ + [13] = {0xFD48243CU, 0x0000000EU}, /* RGIDW_MODID[15]:WDT*/ + [14] = {0xFD482440U, 0x0000000EU}, /* RGIDW_MODID[16]:WWDT0*/ + [15] = {0xFD482444U, 0x0000000EU}, /* RGIDW_MODID[17]:WWDT1*/ + [16] = {0xFD482448U, 0x0000000EU}, /* RGIDW_MODID[18]:WWDT2*/ + [17] = {0xFD48244CU, 0x0000000EU}, /* RGIDW_MODID[19]:WWDT3*/ + [18] = {0xFD482450U, 0x0000000EU}, /* RGIDW_MODID[20]:WWDT4*/ + [19] = {0xFD482454U, 0x0000000EU}, /* RGIDW_MODID[21]:WWDT5*/ + [20] = {0xFD482458U, 0x0000000EU}, /* RGIDW_MODID[22]:WWDT6*/ + [21] = {0xFD482468U, 0x0000000AU}, /* RGIDW_MODID[23]:ECMRT3*/ + [22] = {0xFDA02404U, 0x0000000FU}, /* RGIDW_MODID[24]:APMU0*/ + [23] = {0xFDA02408U, 0x00000002U}, /* RGIDW_MODID[25]:APMU1*/ + [24] = {0xFDA0240CU, 0x00000000U}, /* RGIDW_MODID[26]:APMU10*/ + [25] = {0xFDA02410U, 0x00000000U}, /* RGIDW_MODID[27]:APMU11*/ + [26] = {0xFDA02414U, 0x00000000U}, /* RGIDW_MODID[28]:APMU12*/ + [27] = {0xFDA02418U, 0x00000000U}, /* RGIDW_MODID[29]:APMU13*/ + [28] = {0xFDA0241CU, 0x00000000U}, /* RGIDW_MODID[30]:APMU14*/ + [29] = {0xFDA02420U, 0x00000000U}, /* RGIDW_MODID[31]:APMU15*/ + [30] = {0xFDA02424U, 0x00000004U}, /* RGIDW_MODID[32]:APMU2*/ + [31] = {0xFDA02428U, 0x00000004U}, /* RGIDW_MODID[33]:APMU3*/ + [32] = {0xFDA0242CU, 0x00000000U}, /* RGIDW_MODID[34]:APMU4*/ + [33] = {0xFDA02430U, 0x00000000U}, /* RGIDW_MODID[35]:APMU5*/ + [34] = {0xFDA02434U, 0x00000000U}, /* RGIDW_MODID[36]:APMU6*/ + [35] = {0xFDA02438U, 0x00000000U}, /* RGIDW_MODID[37]:APMU7*/ + [36] = {0xFDA0243CU, 0x00000000U}, /* RGIDW_MODID[38]:APMU8*/ + [37] = {0xFDA02440U, 0x00000000U}, /* RGIDW_MODID[39]:APMU9*/ + [38] = {0xFDA02444U, 0x00000002U}, /* RGIDW_MODID[40]:ARS00*/ + /* After setting */ /* RGIDW_MODID[41]:ARS01*/ + /* After setting */ /* RGIDW_MODID[42]:ARS02*/ + [39] = {0xFDA02450U, 0x00000001U}, /* RGIDW_MODID[43]:ARS03*/ + [40] = {0xFDA02454U, 0x00000002U}, /* RGIDW_MODID[44]:ARS04*/ + [41] = {0xFDA02458U, 0x00000001U}, /* RGIDW_MODID[45]:ARS05*/ + [42] = {0xFDA0245CU, 0x00000002U}, /* RGIDW_MODID[46]:ARS06*/ + [43] = {0xFDA02460U, 0x00000002U}, /* RGIDW_MODID[47]:ARS07*/ + [44] = {0xFDA02464U, 0x00000000U}, /* RGIDW_MODID[48]:ARS08*/ + [45] = {0xFDA02468U, 0x0000000EU}, /* RGIDW_MODID[49]:CMT0*/ + [46] = {0xFDA0246CU, 0x0000000EU}, /* RGIDW_MODID[50]:CMT1*/ + [47] = {0xFDA02470U, 0x0000000EU}, /* RGIDW_MODID[51]:CMT2*/ + [48] = {0xFDA02474U, 0x0000000EU}, /* RGIDW_MODID[52]:CMT3*/ + [49] = {0xFDA02478U, 0x0000000AU}, /* RGIDW_MODID[53]:CKM*/ + [50] = {0xFDA0247CU, 0x0000000EU}, /* RGIDW_MODID[54]:DBE*/ + [51] = {0xFDA02480U, 0x0000000EU}, /* RGIDW_MODID[55]:IRQC*/ + [52] = {0xFDA02484U, 0x0000000AU}, /* RGIDW_MODID[56]:ECMPS0*/ + [53] = {0xFDA02488U, 0x0000000BU}, /* RGIDW_MODID[57]:OTP0*/ + [54] = {0xFDA0248CU, 0x0000000FU}, /* RGIDW_MODID[58]:OTP1*/ + [55] = {0xFDA0249CU, 0x0000000EU}, /* RGIDW_MODID[59]:SCMT*/ + [56] = {0xFDA024A8U, 0x0000004AU}, /* RGIDW_MODID[60]:TSC1*/ + [57] = {0xFDA024ACU, 0x0000004AU}, /* RGIDW_MODID[61]:TSC2*/ + [58] = {0xFDA024B8U, 0x00000006U}, /* RGIDW_MODID[62]:UCMT*/ + [59] = {0xFDA02500U, 0x0000006FU}, /* RGIDW_MODID[63]:CPG0*/ + [60] = {0xFDA02504U, 0x0000000AU}, /* RGIDW_MODID[64]:CPG1*/ + [61] = {0xFDA02508U, 0x0000004EU}, /* RGIDW_MODID[65]:CPG2*/ + [62] = {0xFDA0250CU, 0x00000028U}, /* RGIDW_MODID[66]:CPG3*/ + [63] = {0xFDA02510U, 0x0000006FU}, /* RGIDW_MODID[67]:PFC00*/ + [64] = {0xFDA02514U, 0x0000000AU}, /* RGIDW_MODID[68]:PFC01*/ + [65] = {0xFDA02518U, 0x0000004EU}, /* RGIDW_MODID[69]:PFC02*/ + [66] = {0xFDA0251CU, 0x00000028U}, /* RGIDW_MODID[70]:PFC03*/ + [67] = {0xFDA02520U, 0x0000006FU}, /* RGIDW_MODID[71]:PFC10*/ + [68] = {0xFDA02524U, 0x0000000AU}, /* RGIDW_MODID[72]:PFC11*/ + [69] = {0xFDA02528U, 0x0000004EU}, /* RGIDW_MODID[73]:PFC12*/ + [70] = {0xFDA0252CU, 0x00000028U}, /* RGIDW_MODID[74]:PFC13*/ + [71] = {0xFDA02530U, 0x0000006FU}, /* RGIDW_MODID[75]:PFC20*/ + [72] = {0xFDA02534U, 0x0000000AU}, /* RGIDW_MODID[76]:PFC21*/ + [73] = {0xFDA02538U, 0x0000004EU}, /* RGIDW_MODID[77]:PFC22*/ + [74] = {0xFDA0253CU, 0x00000028U}, /* RGIDW_MODID[78]:PFC23*/ + [75] = {0xFDA02550U, 0x0000006FU}, /* RGIDW_MODID[79]:PFCS0*/ + [76] = {0xFDA02554U, 0x0000000AU}, /* RGIDW_MODID[80]:PFCS1*/ + [77] = {0xFDA02558U, 0x0000004EU}, /* RGIDW_MODID[81]:PFCS2*/ + [78] = {0xFDA0255CU, 0x00000028U}, /* RGIDW_MODID[82]:PFCS3*/ + [79] = {0xFDA02560U, 0x0000006FU}, /* RGIDW_MODID[83]:RESET0*/ + [80] = {0xFDA02564U, 0x0000000AU}, /* RGIDW_MODID[84]:RESET1*/ + [81] = {0xFDA02568U, 0x0000004EU}, /* RGIDW_MODID[85]:RESET2*/ + [82] = {0xFDA0256CU, 0x00000028U}, /* RGIDW_MODID[86]:RESET3*/ + [83] = {0xFDA02570U, 0x0000006FU}, /* RGIDW_MODID[87]:SYS0*/ + [84] = {0xFDA02574U, 0x0000000AU}, /* RGIDW_MODID[88]:SYS1*/ + [85] = {0xFDA02578U, 0x0000004EU}, /* RGIDW_MODID[89]:SYS2*/ + [86] = {0xFDA0257CU, 0x00000028U}, /* RGIDW_MODID[90]:SYS3*/ + [87] = {0xFCB62400U, 0x0000000EU}, /* RGIDW_MODID[91]:DMAMSI0*/ + [88] = {0xFCB62404U, 0x0000000EU}, /* RGIDW_MODID[92]:DMAMSI1*/ + [89] = {0xFCB62408U, 0x0000000EU}, /* RGIDW_MODID[93]:DMAMSI2*/ + [90] = {0xFCB6240CU, 0x0000000EU}, /* RGIDW_MODID[94]:DMAMSI3*/ + [91] = {0xFCB62410U, 0x0000000EU}, /* RGIDW_MODID[95]:DMAMSI4*/ + [92] = {0xFCB62414U, 0x0000000EU}, /* RGIDW_MODID[96]:DMAMSI5*/ + [93] = {0xFCB62418U, 0x0000000AU}, /* RGIDW_MODID[97]:ECMSP3*/ + [94] = {0xFCB62424U, 0x00000002U}, /* RGIDW_MODID[98]:ARSP30*/ + /* After setting */ /* RGIDW_MODID[99]:ARSP31*/ + /* After setting */ /* RGIDW_MODID[100]:ARSP32*/ + [95] = {0xFCB62430U, 0x00000001U}, /* RGIDW_MODID[101]:ARSP33*/ + [96] = {0xFCB62434U, 0x00000002U}, /* RGIDW_MODID[102]:ARSP34*/ + [97] = {0xFCB62438U, 0x00000001U}, /* RGIDW_MODID[103]:ARSP35*/ + [98] = {0xFCB6243CU, 0x00000002U}, /* RGIDW_MODID[104]:ARSP36*/ + [99] = {0xFCB62440U, 0x00000002U}, /* RGIDW_MODID[105]:ARSP37*/ + [100] = {0xFCB62444U, 0x00000000U}, /* RGIDW_MODID[106]:ARSP38*/ + [101] = {0xFCB62448U, 0x0000000EU}, /* RGIDW_MODID[107]:MSI0*/ + [102] = {0xFCB6244CU, 0x0000000EU}, /* RGIDW_MODID[108]:MSI1*/ + [103] = {0xFCB62450U, 0x0000000EU}, /* RGIDW_MODID[109]:MSI2*/ + [104] = {0xFCB62454U, 0x0000000EU}, /* RGIDW_MODID[110]:MSI3*/ + [105] = {0xFCB62458U, 0x0000000EU}, /* RGIDW_MODID[111]:MSI4*/ + [106] = {0xFCB6245CU, 0x0000000EU}, /* RGIDW_MODID[112]:MSI5*/ + [107] = {0xFCB92400U, 0x00000002U}, /* RGIDW_MODID[113]:ARSP40*/ + /* After setting */ /* RGIDW_MODID[114]:ARSP41*/ + /* After setting */ /* RGIDW_MODID[115]:ARSP42*/ + [108] = {0xFCB9240CU, 0x00000001U}, /* RGIDW_MODID[116]:ARSP43*/ + [109] = {0xFCB92410U, 0x00000002U}, /* RGIDW_MODID[117]:ARSP44*/ + [110] = {0xFCB92414U, 0x00000001U}, /* RGIDW_MODID[118]:ARSP45*/ + [111] = {0xFCB92418U, 0x00000002U}, /* RGIDW_MODID[119]:ARSP46*/ + [112] = {0xFCB9241CU, 0x00000002U}, /* RGIDW_MODID[120]:ARSP47*/ + [113] = {0xFCB92420U, 0x00000000U}, /* RGIDW_MODID[121]:ARSP48*/ + [114] = {0xFCB92424U, 0x0000004FU}, /* RGIDW_MODID[122]:DMAHSCIF0*/ + [115] = {0xFCB92428U, 0x0000004FU}, /* RGIDW_MODID[123]:DMAHSCIF1*/ + [116] = {0xFCB9242CU, 0x0000004FU}, /* RGIDW_MODID[124]:DMAHSCIF2*/ + [117] = {0xFCB92430U, 0x0000004FU}, /* RGIDW_MODID[125]:DMAHSCIF3*/ + [118] = {0xFCB92434U, 0x0000004FU}, /* RGIDW_MODID[126]:DMASCIF0*/ + [119] = {0xFCB92438U, 0x0000004FU}, /* RGIDW_MODID[127]:DMASCIF1*/ + [120] = {0xFCB9243CU, 0x0000004FU}, /* RGIDW_MODID[128]:DMASCIF3*/ + [121] = {0xFCB92440U, 0x0000004FU}, /* RGIDW_MODID[129]:DMASCIF4*/ + [122] = {0xFCB92444U, 0x0000000AU}, /* RGIDW_MODID[130]:ECMSP4*/ + [123] = {0xFCB92448U, 0x0000004FU}, /* RGIDW_MODID[131]:HSCIF0*/ + [124] = {0xFCB9244CU, 0x0000004FU}, /* RGIDW_MODID[132]:HSCIF1*/ + [125] = {0xFCB92450U, 0x0000004FU}, /* RGIDW_MODID[133]:HSCIF2*/ + [126] = {0xFCB92454U, 0x0000004FU}, /* RGIDW_MODID[134]:HSCIF3*/ + [127] = {0xFCB92458U, 0x0000004FU}, /* RGIDW_MODID[135]:SCIF0*/ + [128] = {0xFCB9245CU, 0x0000004FU}, /* RGIDW_MODID[136]:SCIF1*/ + [129] = {0xFCB92460U, 0x0000004FU}, /* RGIDW_MODID[137]:SCIF3*/ + [130] = {0xFCB92464U, 0x0000004FU}, /* RGIDW_MODID[138]:SCIF4*/ + [131] = {0xFCB92468U, 0x0000006EU}, /* RGIDW_MODID[139]:TMU1*/ + [132] = {0xFCB9246CU, 0x0000006EU}, /* RGIDW_MODID[140]:TMU2*/ + [133] = {0xFCB92470U, 0x0000006EU}, /* RGIDW_MODID[141]:TMU3*/ + [134] = {0xFCB92474U, 0x0000006EU}, /* RGIDW_MODID[142]:TMU4*/ + [135] = {0xFCB92478U, 0x0000004AU}, /* RGIDW_MODID[143]:CANFD*/ + [136] = {0xFCB9247CU, 0x0000004AU}, /* RGIDW_MODID[144]:DMACANFD*/ + [137] = {0xFCB92480U, 0x00000002U}, /* RGIDW_MODID[145]:DMATPU0*/ + [138] = {0xFCB92484U, 0x00000002U}, /* RGIDW_MODID[146]:PWM0*/ + [139] = {0xFCB92488U, 0x00000002U}, /* RGIDW_MODID[147]:PWM1*/ + [140] = {0xFCB9248CU, 0x00000002U}, /* RGIDW_MODID[148]:PWM2*/ + [141] = {0xFCB92490U, 0x00000002U}, /* RGIDW_MODID[149]:PWM3*/ + [142] = {0xFCB92494U, 0x00000002U}, /* RGIDW_MODID[150]:PWM4*/ + [143] = {0xFCB924ACU, 0x00000002U}, /* RGIDW_MODID[151]:TPU0*/ + [144] = {0xFEBD2400U, 0x00000002U}, /* RGIDW_MODID[152]:ARVI40*/ + /* After setting */ /* RGIDW_MODID[153]:ARVI41*/ + /* After setting */ /* RGIDW_MODID[154]:ARVI42*/ + [145] = {0xFEBD240CU, 0x00000001U}, /* RGIDW_MODID[155]:ARVI43*/ + [146] = {0xFEBD2410U, 0x00000002U}, /* RGIDW_MODID[156]:ARVI44*/ + [147] = {0xFEBD2414U, 0x00000001U}, /* RGIDW_MODID[157]:ARVI45*/ + [148] = {0xFEBD2418U, 0x00000002U}, /* RGIDW_MODID[158]:ARVI46*/ + [149] = {0xFEBD241CU, 0x00000002U}, /* RGIDW_MODID[159]:ARVI47*/ + [150] = {0xFEBD2420U, 0x00000000U}, /* RGIDW_MODID[160]:ARVI48*/ + [151] = {0xFEBD2424U, 0x0000000FU}, /* RGIDW_MODID[161]:DIS0*/ + [152] = {0xFEBD2430U, 0x0000000EU}, /* RGIDW_MODID[162]:ECMVIO2*/ + [153] = {0xFEBD2434U, 0x0000000FU}, /* RGIDW_MODID[163]:FCPVD0*/ + [154] = {0xFEBD243CU, 0x0000004EU}, /* RGIDW_MODID[164]:VSPD0*/ + [155] = {0xFCF82400U, 0x0000000AU}, /* RGIDW_MODID[165]:CKMHSC*/ + [156] = {0xFCF82404U, 0x0000000CU}, /* RGIDW_MODID[166]:AXIPCI001*/ + [157] = {0xFCF82408U, 0x0000000CU}, /* RGIDW_MODID[167]:AXIPCI002*/ + [158] = {0xFCF8240CU, 0x0000000CU}, /* RGIDW_MODID[168]:AXIPCI003*/ + [159] = {0xFCF82414U, 0x0000000CU}, /* RGIDW_MODID[169]:AXIPCI005*/ + [160] = {0xFCF82418U, 0x0000000CU}, /* RGIDW_MODID[170]:AXIPCI006*/ + [161] = {0xFCF8241CU, 0x0000000CU}, /* RGIDW_MODID[171]:AXIPCI007*/ + [162] = {0xFCF82420U, 0x0000000CU}, /* RGIDW_MODID[172]:AXIPCI008*/ + [163] = {0xFCF82424U, 0x0000000CU}, /* RGIDW_MODID[173]:AXIPCI009*/ + [164] = {0xFCF82428U, 0x0000000CU}, /* RGIDW_MODID[174]:AXIPCI010*/ + [165] = {0xFCF8242CU, 0x0000000CU}, /* RGIDW_MODID[175]:AXIPCI011*/ + [166] = {0xFCF82430U, 0x0000000CU}, /* RGIDW_MODID[176]:AXIPCI012*/ + [167] = {0xFCF82434U, 0x0000000CU}, /* RGIDW_MODID[177]:AXIPCI013*/ + [168] = {0xFCF82438U, 0x0000000CU}, /* RGIDW_MODID[178]:AXIPCI014*/ + [169] = {0xFCF8243CU, 0x0000000CU}, /* RGIDW_MODID[179]:AXIPCI015*/ + [170] = {0xFCF82484U, 0x0000000EU}, /* RGIDW_MODID[180]:GPTP*/ + [171] = {0xFCF82488U, 0x0000004EU}, /* RGIDW_MODID[181]:IPMMUHC00*/ + [172] = {0xFCF824F4U, 0x0000000CU}, /* RGIDW_MODID[182]:AXIPCI000*/ + [173] = {0xFCF824F8U, 0x0000000CU}, /* RGIDW_MODID[183]:AXIPCI004*/ + [174] = {0xFCF824FCU, 0x0000004EU}, /* RGIDW_MODID[184]:IPMMUHC01*/ + [175] = {0xFCF82500U, 0x0000004EU}, /* RGIDW_MODID[185]:AVB0*/ + [176] = {0xFCF82504U, 0x0000004EU}, /* RGIDW_MODID[186]:AVB1*/ + [177] = {0xFCF82508U, 0x0000004EU}, /* RGIDW_MODID[187]:AVB2*/ + [178] = {0xFCF8250CU, 0x0000004EU}, /* RGIDW_MODID[188]:IPMMUHC10*/ + [179] = {0xFCF82510U, 0x0000004EU}, /* RGIDW_MODID[189]:IPMMUHC11*/ + [180] = {0xFCF82514U, 0x0000004EU}, /* RGIDW_MODID[190]:IPMMUHC12*/ + [181] = {0xFCF82518U, 0x0000004EU}, /* RGIDW_MODID[191]:IPMMUHC13*/ + [182] = {0xFCF8251CU, 0x0000000CU}, /* RGIDW_MODID[192]:PPHY0*/ + [183] = {0xFCF82524U, 0x0000004EU}, /* RGIDW_MODID[193]:IPMMUHC14*/ + [184] = {0xFCF82528U, 0x0000004EU}, /* RGIDW_MODID[194]:IPMMUHC15*/ + [185] = {0xFCF8252CU, 0x0000000EU}, /* RGIDW_MODID[195]:FBAHSC*/ + [186] = {0xFCF82530U, 0x0000004EU}, /* RGIDW_MODID[196]:IPMMUHC02*/ + [187] = {0xFCF82538U, 0x0000000AU}, /* RGIDW_MODID[197]:ECMHSC*/ + [188] = {0xFCF8253CU, 0x00000002U}, /* RGIDW_MODID[198]:ARHC0*/ + /* After setting */ /* RGIDW_MODID[199]:ARHC1*/ + /* After setting */ /* RGIDW_MODID[200]:ARHC2*/ + [189] = {0xFCF82548U, 0x00000001U}, /* RGIDW_MODID[201]:ARHC3*/ + [190] = {0xFCF8254CU, 0x00000002U}, /* RGIDW_MODID[202]:ARHC4*/ + [191] = {0xFCF82550U, 0x00000001U}, /* RGIDW_MODID[203]:ARHC5*/ + [192] = {0xFCF82554U, 0x00000002U}, /* RGIDW_MODID[204]:ARHC6*/ + [193] = {0xFCF82558U, 0x00000002U}, /* RGIDW_MODID[205]:ARHC7*/ + [194] = {0xFCF8255CU, 0x00000000U}, /* RGIDW_MODID[206]:ARHC8*/ + [195] = {0xFCF82560U, 0x0000004EU}, /* RGIDW_MODID[207]:IPMMUHC03*/ + [196] = {0xFCF82564U, 0x0000004EU}, /* RGIDW_MODID[208]:IPMMUHC04*/ + [197] = {0xFCF82568U, 0x0000004EU}, /* RGIDW_MODID[209]:IPMMUHC05*/ + [198] = {0xFCF8256CU, 0x0000004EU}, /* RGIDW_MODID[210]:IPMMUHC06*/ + [199] = {0xFCF82570U, 0x0000004EU}, /* RGIDW_MODID[211]:IPMMUHC07*/ + [200] = {0xFCF82574U, 0x0000004EU}, /* RGIDW_MODID[212]:IPMMUHC08*/ + [201] = {0xFCF82578U, 0x0000004EU}, /* RGIDW_MODID[213]:IPMMUHC09*/ + [202] = {0xFC882400U, 0x00000002U}, /* RGIDW_MODID[214]:ARIMP00*/ + /* After setting */ /* RGIDW_MODID[215]:ARIMP01*/ + /* After setting */ /* RGIDW_MODID[216]:ARIMP02*/ + [203] = {0xFC88240CU, 0x00000001U}, /* RGIDW_MODID[217]:ARIMP03*/ + [204] = {0xFC882410U, 0x00000002U}, /* RGIDW_MODID[218]:ARIMP04*/ + [205] = {0xFC882414U, 0x0000004EU}, /* RGIDW_MODID[219]:AXIFBABUSIR0*/ + [206] = {0xFC882418U, 0x0000004EU}, /* RGIDW_MODID[220]:AXIFBABUSIR1*/ + [207] = {0xFC88241CU, 0x0000004EU}, /* RGIDW_MODID[221]:AXIFBABUSIR2*/ + [208] = {0xFC882420U, 0x0000004EU}, /* RGIDW_MODID[222]:AXIFBABUSIR3*/ + [209] = {0xFC882428U, 0x0000004EU}, /* RGIDW_MODID[223]:AXIIMP0*/ + [210] = {0xFC882434U, 0x00000001U}, /* RGIDW_MODID[224]:ARIMP05*/ + [211] = {0xFC882438U, 0x00000002U}, /* RGIDW_MODID[225]:ARIMP06*/ + [212] = {0xFC88243CU, 0x00000002U}, /* RGIDW_MODID[226]:ARIMP07*/ + [213] = {0xFC882440U, 0x00000000U}, /* RGIDW_MODID[227]:ARIMP08*/ + [214] = {0xFC882448U, 0x0000000AU}, /* RGIDW_MODID[228]:ECMIR*/ + [215] = {0xFC88244CU, 0x0000000FU}, /* RGIDW_MODID[229]:DSPPS*/ + [216] = {0xFC882450U, 0x0000004EU}, /* RGIDW_MODID[230]:IPMMUIR1*/ + [217] = {0xFC882454U, 0x0000004EU}, /* RGIDW_MODID[231]:IPMMUIR0*/ + [218] = {0xFC882458U, 0x0000004EU}, /* RGIDW_MODID[232]:IPMMUIR10*/ + [219] = {0xFC88245CU, 0x0000004EU}, /* RGIDW_MODID[233]:IPMMUIR11*/ + [220] = {0xFC882460U, 0x0000004EU}, /* RGIDW_MODID[234]:IPMMUIR12*/ + [221] = {0xFC882464U, 0x0000004EU}, /* RGIDW_MODID[235]:IPMMUIR13*/ + [222] = {0xFC882468U, 0x0000004EU}, /* RGIDW_MODID[236]:IPMMUIR14*/ + [223] = {0xFC88246CU, 0x0000004EU}, /* RGIDW_MODID[237]:IPMMUIR15*/ + [224] = {0xFC882470U, 0x0000004EU}, /* RGIDW_MODID[238]:IPMMUIR2*/ + [225] = {0xFC882474U, 0x0000004EU}, /* RGIDW_MODID[239]:IPMMUIR3*/ + [226] = {0xFC882478U, 0x0000004EU}, /* RGIDW_MODID[240]:IPMMUIR4*/ + [227] = {0xFC88247CU, 0x0000004EU}, /* RGIDW_MODID[241]:IPMMUIR5*/ + [228] = {0xFC882480U, 0x0000004EU}, /* RGIDW_MODID[242]:IPMMUIR6*/ + [229] = {0xFC882484U, 0x0000004EU}, /* RGIDW_MODID[243]:IPMMUIR7*/ + [230] = {0xFC882488U, 0x0000004EU}, /* RGIDW_MODID[244]:IPMMUIR8*/ + [231] = {0xFC88248CU, 0x0000004EU}, /* RGIDW_MODID[245]:IPMMUIR9*/ + [232] = {0xFC012400U, 0x00000002U}, /* RGIDW_MODID[246]:ARPV0*/ + /* After setting */ /* RGIDW_MODID[247]:ARPV1*/ + [233] = {0xFC012408U, 0x0000002CU}, /* RGIDW_MODID[248]:AXIRGXS*/ + /* After setting */ /* RGIDW_MODID[249]:ARPV2*/ + [234] = {0xFC012410U, 0x00000001U}, /* RGIDW_MODID[250]:ARPV3*/ + [235] = {0xFC012414U, 0x00000002U}, /* RGIDW_MODID[251]:ARPV4*/ + [236] = {0xFC012418U, 0x00000001U}, /* RGIDW_MODID[252]:ARPV5*/ + [237] = {0xFC01241CU, 0x00000002U}, /* RGIDW_MODID[253]:ARPV6*/ + [238] = {0xFC012420U, 0x00000002U}, /* RGIDW_MODID[254]:ARPV7*/ + [239] = {0xFC012424U, 0x00000000U}, /* RGIDW_MODID[255]:ARPV8*/ + [240] = {0xFC01242CU, 0x0000000AU}, /* RGIDW_MODID[256]:ECM3DG*/ + [241] = {0xFC012430U, 0x0000000EU}, /* RGIDW_MODID[257]:FBAPVC*/ + [242] = {0xFC012434U, 0x0000000EU}, /* RGIDW_MODID[258]:FBAPVD0*/ + [243] = {0xFC012438U, 0x0000000EU}, /* RGIDW_MODID[259]:FBAPVD1*/ + [244] = {0xFC01243CU, 0x0000000EU}, /* RGIDW_MODID[260]:FBAPVD2*/ + [245] = {0xFC012440U, 0x0000000EU}, /* RGIDW_MODID[261]:FBAPVE*/ + [246] = {0xFC012444U, 0x0000004EU}, /* RGIDW_MODID[262]:IPMMUPV000*/ + [247] = {0xFC012448U, 0x0000004EU}, /* RGIDW_MODID[263]:IPMMUPV001*/ + [248] = {0xFC01244CU, 0x0000004EU}, /* RGIDW_MODID[264]:IPMMUPV010*/ + [249] = {0xFC012450U, 0x0000004EU}, /* RGIDW_MODID[265]:IPMMUPV011*/ + [250] = {0xFC012454U, 0x0000004EU}, /* RGIDW_MODID[266]:IPMMUPV012*/ + [251] = {0xFC012458U, 0x0000004EU}, /* RGIDW_MODID[267]:IPMMUPV013*/ + [252] = {0xFC01245CU, 0x0000004EU}, /* RGIDW_MODID[268]:IPMMUPV014*/ + [253] = {0xFC012460U, 0x0000004EU}, /* RGIDW_MODID[269]:IPMMUPV015*/ + [254] = {0xFC012464U, 0x0000004EU}, /* RGIDW_MODID[270]:IPMMUPV002*/ + [255] = {0xFC012468U, 0x0000004EU}, /* RGIDW_MODID[271]:IPMMUPV003*/ + [256] = {0xFC01246CU, 0x0000004EU}, /* RGIDW_MODID[272]:IPMMUPV004*/ + [257] = {0xFC012470U, 0x0000004EU}, /* RGIDW_MODID[273]:IPMMUPV005*/ + [258] = {0xFC012474U, 0x0000004EU}, /* RGIDW_MODID[274]:IPMMUPV006*/ + [259] = {0xFC012478U, 0x0000004EU}, /* RGIDW_MODID[275]:IPMMUPV007*/ + [260] = {0xFC01247CU, 0x0000004EU}, /* RGIDW_MODID[276]:IPMMUPV008*/ + [261] = {0xFC012480U, 0x0000004EU}, /* RGIDW_MODID[277]:IPMMUPV009*/ + [262] = {0xFDC22400U, 0x00000002U}, /* RGIDW_MODID[278]:ARRC0*/ + /* After setting */ /* RGIDW_MODID[279]:ARRC1*/ + /* After setting */ /* RGIDW_MODID[280]:ARRC2*/ + [263] = {0xFDC2240CU, 0x00000001U}, /* RGIDW_MODID[281]:ARRC3*/ + [264] = {0xFDC22410U, 0x00000002U}, /* RGIDW_MODID[282]:ARRC4*/ + [265] = {0xFDC22414U, 0x00000001U}, /* RGIDW_MODID[283]:ARRC5*/ + [266] = {0xFDC22418U, 0x00000002U}, /* RGIDW_MODID[284]:ARRC6*/ + [267] = {0xFDC2241CU, 0x00000002U}, /* RGIDW_MODID[285]:ARRC7*/ + [268] = {0xFDC22420U, 0x00000000U}, /* RGIDW_MODID[286]:ARRC8*/ + [269] = {0xFDC22428U, 0x0000004FU}, /* RGIDW_MODID[287]:ICUMX*/ + [270] = {0xFDC2242CU, 0x0000000AU}, /* RGIDW_MODID[288]:ECMRC*/ + [271] = {0xFD432400U, 0x0000004EU}, /* RGIDW_MODID[289]:DMAWCRC0*/ + [272] = {0xFD432404U, 0x0000004EU}, /* RGIDW_MODID[290]:DMAWCRC1*/ + [273] = {0xFD432408U, 0x0000004EU}, /* RGIDW_MODID[291]:DMAWCRC2*/ + [274] = {0xFD43240CU, 0x0000004EU}, /* RGIDW_MODID[292]:DMAWCRC3*/ + [275] = {0xFD442400U, 0x0000000FU}, /* RGIDW_MODID[293]:ARMREG00*/ + [276] = {0xFD442404U, 0x0000000CU}, /* RGIDW_MODID[294]:ARMREG01*/ + [277] = {0xFD442408U, 0x00000000U}, /* RGIDW_MODID[295]:ARMREG10*/ + [278] = {0xFD44240CU, 0x00000000U}, /* RGIDW_MODID[296]:ARMREG11*/ + [279] = {0xFD442410U, 0x0000000AU}, /* RGIDW_MODID[297]:ARMREG12*/ + [280] = {0xFD442414U, 0x0000000FU}, /* RGIDW_MODID[298]:ARMREG13*/ + [281] = {0xFD442418U, 0x0000000AU}, /* RGIDW_MODID[299]:ARMREG14*/ + [282] = {0xFD44241CU, 0x00000003U}, /* RGIDW_MODID[300]:AXICR52SS0*/ + [283] = {0xFD442420U, 0x0000000EU}, /* RGIDW_MODID[301]:AXICSD0*/ + [284] = {0xFD442424U, 0x0000000EU}, /* RGIDW_MODID[302]:AXIINTAP0*/ + [285] = {0xFD442430U, 0x0000000FU}, /* RGIDW_MODID[303]:AXISYSRAM0*/ + [286] = {0xFD442434U, 0x0000004FU}, /* RGIDW_MODID[304]:AXISYSRAM1*/ + [287] = {0xFD442438U, 0x00000000U}, /* RGIDW_MODID[305]:ARGREG15*/ + [288] = {0xFD44243CU, 0x00000000U}, /* RGIDW_MODID[306]:ARMREG2*/ + [289] = {0xFD442440U, 0x00000000U}, /* RGIDW_MODID[307]:ARMREG3*/ + [290] = {0xFD442444U, 0x00000000U}, /* RGIDW_MODID[308]:ARMREG4*/ + [291] = {0xFD442448U, 0x0000000FU}, /* RGIDW_MODID[309]:ARMREG5*/ + [292] = {0xFD44244CU, 0x0000000AU}, /* RGIDW_MODID[310]:ARMREG6*/ + [293] = {0xFD442450U, 0x00000000U}, /* RGIDW_MODID[311]:ARMREG7*/ + [294] = {0xFD442454U, 0x0000000CU}, /* RGIDW_MODID[312]:ARMREG8*/ + [295] = {0xFD442458U, 0x0000000CU}, /* RGIDW_MODID[313]:ARMREG9*/ + [296] = {0xFD44245CU, 0x00000002U}, /* RGIDW_MODID[314]:ARRD0*/ + /* After setting */ /* RGIDW_MODID[315]:ARRD1*/ + /* After setting */ /* RGIDW_MODID[316]:ARRD2*/ + [297] = {0xFD442468U, 0x00000001U}, /* RGIDW_MODID[317]:ARRD3*/ + [298] = {0xFD44246CU, 0x00000002U}, /* RGIDW_MODID[318]:ARRD4*/ + [299] = {0xFD442470U, 0x00000001U}, /* RGIDW_MODID[319]:ARRD5*/ + [300] = {0xFD442474U, 0x00000002U}, /* RGIDW_MODID[320]:ARRD6*/ + [301] = {0xFD442478U, 0x00000002U}, /* RGIDW_MODID[321]:ARRD7*/ + [302] = {0xFD44247CU, 0x00000000U}, /* RGIDW_MODID[322]:ARRD8*/ + [303] = {0xFD442480U, 0x00000002U}, /* RGIDW_MODID[323]:ARRT0*/ + /* After setting */ /* RGIDW_MODID[324]:ARRT1*/ + /* After setting */ /* RGIDW_MODID[325]:ARRT2*/ + [304] = {0xFD44248CU, 0x00000001U}, /* RGIDW_MODID[326]:ARRT3*/ + [305] = {0xFD442490U, 0x00000002U}, /* RGIDW_MODID[327]:ARRT4*/ + [306] = {0xFD442494U, 0x00000001U}, /* RGIDW_MODID[328]:ARRT5*/ + [307] = {0xFD442498U, 0x00000002U}, /* RGIDW_MODID[329]:ARRT6*/ + [308] = {0xFD44249CU, 0x00000002U}, /* RGIDW_MODID[330]:ARRT7*/ + [309] = {0xFD4424A0U, 0x00000000U}, /* RGIDW_MODID[331]:ARRT8*/ + [310] = {0xFD4424A4U, 0x0000000AU}, /* RGIDW_MODID[332]:CKMRT*/ + [311] = {0xFD4424A8U, 0x0000004EU}, /* RGIDW_MODID[333]:CRC0*/ + [312] = {0xFD4424ACU, 0x0000004EU}, /* RGIDW_MODID[334]:CRC1*/ + [313] = {0xFD4424B0U, 0x0000004EU}, /* RGIDW_MODID[335]:CRC2*/ + [314] = {0xFD4424B4U, 0x0000004EU}, /* RGIDW_MODID[336]:CRC3*/ + [315] = {0xFD4424B8U, 0x0000000EU}, /* RGIDW_MODID[337]:CSD*/ + [316] = {0xFD4424BCU, 0x0000000EU}, /* RGIDW_MODID[338]:ECM*/ + [317] = {0xFD4424C0U, 0x0000000AU}, /* RGIDW_MODID[339]:ECMRT*/ + [318] = {0xFD4424C4U, 0x0000000EU}, /* RGIDW_MODID[340]:FBACR52*/ + [319] = {0xFD4424C8U, 0x0000000EU}, /* RGIDW_MODID[341]:FBART*/ + [320] = {0xFD4424CCU, 0x0000000EU}, /* RGIDW_MODID[342]:INTTP*/ + [321] = {0xFD4424D0U, 0x0000004EU}, /* RGIDW_MODID[343]:IPMMURT000*/ + [322] = {0xFD4424D4U, 0x0000004EU}, /* RGIDW_MODID[344]:IPMMURT100*/ + [323] = {0xFD4424D8U, 0x0000004EU}, /* RGIDW_MODID[345]:KCRC4*/ + [324] = {0xFD4424DCU, 0x0000004EU}, /* RGIDW_MODID[346]:KCRC5*/ + [325] = {0xFD4424E0U, 0x0000004EU}, /* RGIDW_MODID[347]:KCRC6*/ + [326] = {0xFD4424E4U, 0x0000004EU}, /* RGIDW_MODID[348]:KCRC7*/ + [327] = {0xFD4424E8U, 0x0000004FU}, /* RGIDW_MODID[349]:MFI00*/ + [328] = {0xFD4424ECU, 0x0000004EU}, /* RGIDW_MODID[350]:MFI01*/ + [329] = {0xFD4424F0U, 0x0000004EU}, /* RGIDW_MODID[351]:MFI10*/ + [330] = {0xFD4424F4U, 0x0000004EU}, /* RGIDW_MODID[352]:MFI02*/ + [331] = {0xFD4424F8U, 0x0000004EU}, /* RGIDW_MODID[353]:MFI03*/ + [332] = {0xFD4424FCU, 0x0000004EU}, /* RGIDW_MODID[354]:MFI04*/ + [333] = {0xFD442500U, 0x00000000U}, /* RGIDW_MODID[355]:MFI05*/ + [334] = {0xFD442504U, 0x00000000U}, /* RGIDW_MODID[356]:MFI06*/ + [335] = {0xFD442508U, 0x00000000U}, /* RGIDW_MODID[357]:MFI07*/ + [336] = {0xFD44250CU, 0x00000000U}, /* RGIDW_MODID[358]:MFI08*/ + [337] = {0xFD442510U, 0x0000004EU}, /* RGIDW_MODID[359]:MFI09*/ + [338] = {0xFD442514U, 0x0000004FU}, /* RGIDW_MODID[360]:MFI15*/ + [339] = {0xFD442518U, 0x0000000AU}, /* RGIDW_MODID[361]:CKMCR52*/ + [340] = {0xFD44251CU, 0x0000004BU}, /* RGIDW_MODID[362]:RTDM0P*/ + [341] = {0xFD442520U, 0x0000000AU}, /* RGIDW_MODID[363]:ECMRD*/ + [342] = {0xFD442524U, 0x0000004BU}, /* RGIDW_MODID[364]:RTDM1P*/ + [343] = {0xFD442530U, 0x0000000BU}, /* RGIDW_MODID[365]:SYSRAM10*/ + [344] = {0xFD442538U, 0x00000001U}, /* RGIDW_MODID[366]:SYSRAM00*/ + [345] = {0xFD44253CU, 0x0000004EU}, /* RGIDW_MODID[367]:TSIPL0*/ + [346] = {0xFD442540U, 0x0000004EU}, /* RGIDW_MODID[368]:TSIPL1*/ + [347] = {0xFD442544U, 0x0000004EU}, /* RGIDW_MODID[369]:TSIPL2*/ + [348] = {0xFD442548U, 0x0000004EU}, /* RGIDW_MODID[370]:TSIPL3*/ + [349] = {0xFD44254CU, 0x0000004EU}, /* RGIDW_MODID[371]:TSIPL4*/ + [350] = {0xFD442550U, 0x0000004EU}, /* RGIDW_MODID[372]:TSIPL5*/ + [351] = {0xFD442554U, 0x0000004EU}, /* RGIDW_MODID[373]:TSIPL6*/ + [352] = {0xFD442558U, 0x0000004EU}, /* RGIDW_MODID[374]:TSIPL7*/ + [353] = {0xFD44255CU, 0x0000004EU}, /* RGIDW_MODID[375]:WCRC0*/ + [354] = {0xFD442560U, 0x0000004EU}, /* RGIDW_MODID[376]:WCRC1*/ + [355] = {0xFD442564U, 0x0000004EU}, /* RGIDW_MODID[377]:WCRC2*/ + [356] = {0xFD442568U, 0x0000004EU}, /* RGIDW_MODID[378]:WCRC3*/ + [357] = {0xFD442580U, 0x0000004EU}, /* RGIDW_MODID[379]:MFI11*/ + [358] = {0xFD442584U, 0x00000000U}, /* RGIDW_MODID[380]:MFI12*/ + [359] = {0xFD442588U, 0x00000000U}, /* RGIDW_MODID[381]:MFI13*/ + [360] = {0xFD44258CU, 0x00000000U}, /* RGIDW_MODID[382]:MFI14*/ + [361] = {0xFD442590U, 0x0000004EU}, /* RGIDW_MODID[383]:IPMMURT001*/ + [362] = {0xFD442594U, 0x0000004EU}, /* RGIDW_MODID[384]:IPMMURT010*/ + [363] = {0xFD442598U, 0x0000004EU}, /* RGIDW_MODID[385]:IPMMURT011*/ + [364] = {0xFD44259CU, 0x0000004EU}, /* RGIDW_MODID[386]:IPMMURT012*/ + [365] = {0xFD4425A0U, 0x0000004EU}, /* RGIDW_MODID[387]:IPMMURT013*/ + [366] = {0xFD4425A4U, 0x0000004EU}, /* RGIDW_MODID[388]:IPMMURT014*/ + [367] = {0xFD4425A8U, 0x0000004EU}, /* RGIDW_MODID[389]:IPMMURT015*/ + [368] = {0xFD4425ACU, 0x0000004EU}, /* RGIDW_MODID[390]:IPMMURT002*/ + [369] = {0xFD4425B0U, 0x0000004EU}, /* RGIDW_MODID[391]:IPMMURT003*/ + [370] = {0xFD4425B4U, 0x0000004EU}, /* RGIDW_MODID[392]:IPMMURT004*/ + [371] = {0xFD4425B8U, 0x0000004EU}, /* RGIDW_MODID[393]:IPMMURT005*/ + [372] = {0xFD4425BCU, 0x0000004EU}, /* RGIDW_MODID[394]:IPMMURT006*/ + [373] = {0xFD4425C0U, 0x0000004EU}, /* RGIDW_MODID[395]:IPMMURT007*/ + [374] = {0xFD4425C4U, 0x0000004EU}, /* RGIDW_MODID[396]:IPMMURT008*/ + [375] = {0xFD4425C8U, 0x0000004EU}, /* RGIDW_MODID[397]:IPMMURT009*/ + [376] = {0xFD4425CCU, 0x0000004EU}, /* RGIDW_MODID[398]:IPKMURT101*/ + [377] = {0xFD4425D0U, 0x0000004EU}, /* RGIDW_MODID[399]:IPMMURT110*/ + [378] = {0xFD4425D4U, 0x0000004EU}, /* RGIDW_MODID[400]:IPMMURT111*/ + [379] = {0xFD4425D8U, 0x0000004EU}, /* RGIDW_MODID[401]:IPMMURT112*/ + [380] = {0xFD4425DCU, 0x0000004EU}, /* RGIDW_MODID[402]:IPMMURT113*/ + [381] = {0xFD4425E0U, 0x0000004EU}, /* RGIDW_MODID[403]:IPMMURT114*/ + [382] = {0xFD4425E4U, 0x0000004EU}, /* RGIDW_MODID[404]:IPMMURT115*/ + [383] = {0xFD4425E8U, 0x0000004EU}, /* RGIDW_MODID[405]:IPMMURT102*/ + [384] = {0xFD4425ECU, 0x0000004EU}, /* RGIDW_MODID[406]:IPMMURT103*/ + [385] = {0xFD4425F0U, 0x0000004EU}, /* RGIDW_MODID[407]:IPMMURT104*/ + [386] = {0xFD4425F4U, 0x0000004EU}, /* RGIDW_MODID[408]:IPMMURT105*/ + [387] = {0xFD4425F8U, 0x0000004EU}, /* RGIDW_MODID[409]:IPMMURT106*/ + [388] = {0xFD4425FCU, 0x0000004EU}, /* RGIDW_MODID[410]:IPMMURT107*/ + [389] = {0xFD442600U, 0x0000004BU}, /* RGIDW_MODID[411]:RTDM000*/ + [390] = {0xFD442604U, 0x0000004BU}, /* RGIDW_MODID[412]:RTDM001*/ + [391] = {0xFD442608U, 0x0000004BU}, /* RGIDW_MODID[413]:RTDM010*/ + [392] = {0xFD44260CU, 0x0000004BU}, /* RGIDW_MODID[414]:RTDM011*/ + [393] = {0xFD442610U, 0x0000004BU}, /* RGIDW_MODID[415]:RTDM012*/ + [394] = {0xFD442614U, 0x0000004BU}, /* RGIDW_MODID[416]:RTDM013*/ + [395] = {0xFD442618U, 0x0000004BU}, /* RGIDW_MODID[417]:RTDM014*/ + [396] = {0xFD44261CU, 0x0000004BU}, /* RGIDW_MODID[418]:RTDM015*/ + [397] = {0xFD442620U, 0x0000004BU}, /* RGIDW_MODID[419]:RTDM002*/ + [398] = {0xFD442624U, 0x0000004BU}, /* RGIDW_MODID[420]:RTDM003*/ + [399] = {0xFD442628U, 0x0000004BU}, /* RGIDW_MODID[421]:RTDM004*/ + [400] = {0xFD44262CU, 0x0000004BU}, /* RGIDW_MODID[422]:RTDM005*/ + [401] = {0xFD442630U, 0x0000004BU}, /* RGIDW_MODID[423]:RTDM006*/ + [402] = {0xFD442634U, 0x0000004BU}, /* RGIDW_MODID[424]:RTDM007*/ + [403] = {0xFD442638U, 0x0000004BU}, /* RGIDW_MODID[425]:RTDM008*/ + [404] = {0xFD44263CU, 0x0000004BU}, /* RGIDW_MODID[426]:RTDM009*/ + [405] = {0xFD442640U, 0x0000004BU}, /* RGIDW_MODID[427]:RTDM100*/ + [406] = {0xFD442644U, 0x0000004BU}, /* RGIDW_MODID[428]:RTDM101*/ + [407] = {0xFD442648U, 0x0000004BU}, /* RGIDW_MODID[429]:RTDM110*/ + [408] = {0xFD44264CU, 0x0000004BU}, /* RGIDW_MODID[430]:RTDM111*/ + [409] = {0xFD442650U, 0x0000004BU}, /* RGIDW_MODID[431]:RTDM112*/ + [410] = {0xFD442654U, 0x0000004BU}, /* RGIDW_MODID[432]:RTDM113*/ + [411] = {0xFD442658U, 0x0000004BU}, /* RGIDW_MODID[433]:RTDM114*/ + [412] = {0xFD44265CU, 0x0000004BU}, /* RGIDW_MODID[434]:RTDM115*/ + [413] = {0xFD442660U, 0x0000004BU}, /* RGIDW_MODID[435]:RTDM102*/ + [414] = {0xFD442664U, 0x0000004BU}, /* RGIDW_MODID[436]:RTDM103*/ + [415] = {0xFD442668U, 0x0000004BU}, /* RGIDW_MODID[437]:RTDM104*/ + [416] = {0xFD44266CU, 0x0000004BU}, /* RGIDW_MODID[438]:RTDM105*/ + [417] = {0xFD442670U, 0x0000004BU}, /* RGIDW_MODID[439]:RTDM106*/ + [418] = {0xFD442674U, 0x0000004BU}, /* RGIDW_MODID[440]:RTDM107*/ + [419] = {0xFD442678U, 0x0000004BU}, /* RGIDW_MODID[441]:RTDM108*/ + [420] = {0xFD44267CU, 0x0000004BU}, /* RGIDW_MODID[442]:RTDM109*/ + [421] = {0xFD442700U, 0x0000004EU}, /* RGIDW_MODID[443]:IPMMURT108*/ + [422] = {0xFD442704U, 0x0000004EU}, /* RGIDW_MODID[444]:IPMMURT109*/ + [423] = {0xFD442708U, 0x00000001U}, /* RGIDW_MODID[445]:SYSRAM01*/ + [424] = {0xFD44270CU, 0x0000000BU}, /* RGIDW_MODID[446]:SYSRAM02*/ + [425] = {0xFD442710U, 0x00000001U}, /* RGIDW_MODID[447]:SYSRAM03*/ + [426] = {0xFD442714U, 0x00000001U}, /* RGIDW_MODID[448]:SYSRAM04*/ + [427] = {0xFD442718U, 0x00000001U}, /* RGIDW_MODID[449]:SYSRAM05*/ + [428] = {0xFD44271CU, 0x00000001U}, /* RGIDW_MODID[450]:SYSRAM06*/ + [429] = {0xFD442720U, 0x00000000U}, /* RGIDW_MODID[451]:SYSRAM07*/ + [430] = {0xFD442724U, 0x0000000BU}, /* RGIDW_MODID[452]:SYSRAM11*/ + [431] = {0xFD442728U, 0x0000000AU}, /* RGIDW_MODID[453]:SYSRAM12*/ + [432] = {0xFD44272CU, 0x0000000BU}, /* RGIDW_MODID[454]:SYSRAM13*/ + [433] = {0xFD442730U, 0x0000000BU}, /* RGIDW_MODID[455]:SYSRAM14*/ + [434] = {0xFD442734U, 0x0000000BU}, /* RGIDW_MODID[456]:SYSRAM15*/ + [435] = {0xFD442738U, 0x0000000BU}, /* RGIDW_MODID[457]:SYSRAM16*/ + [436] = {0xFD44273CU, 0x00000000U}, /* RGIDW_MODID[458]:SYSRAM17*/ + [437] = {0xFD442760U, 0x00000002U}, /* RGIDW_MODID[459]:BKBUF*/ + [438] = {0xFD442764U, 0x00000003U}, /* RGIDW_MODID[460]:AXICR52SS1*/ + [439] = {0xFD442768U, 0x00000003U}, /* RGIDW_MODID[461]:AXICR52SS2*/ + [440] = {0xFC862400U, 0x00000002U}, /* RGIDW_MODID[462]:ARSC0*/ + /* After setting */ /* RGIDW_MODID[463]:ARSC1*/ + /* After setting */ /* RGIDW_MODID[464]:ARSC2*/ + [441] = {0xFC86240CU, 0x00000001U}, /* RGIDW_MODID[465]:ARSC3*/ + [442] = {0xFC862410U, 0x00000002U}, /* RGIDW_MODID[466]:ARSC4*/ + [443] = {0xFC862414U, 0x00000001U}, /* RGIDW_MODID[467]:ARSC5*/ + [444] = {0xFC862418U, 0x00000002U}, /* RGIDW_MODID[468]:ARSC6*/ + [445] = {0xFC86241CU, 0x00000002U}, /* RGIDW_MODID[469]:ARSC7*/ + [446] = {0xFC862420U, 0x00000000U}, /* RGIDW_MODID[470]:ARSC8*/ + [447] = {0xFC862424U, 0x00000002U}, /* RGIDW_MODID[471]:ARSTM0*/ + /* After setting */ /* RGIDW_MODID[472]:ARSTM1*/ + [448] = {0xFC86242CU, 0x0000000EU}, /* RGIDW_MODID[473]:CSD1S*/ + [449] = {0xFC862430U, 0x0000000EU}, /* RGIDW_MODID[474]:AXIFBABUSTOP0*/ + /* After setting */ /* RGIDW_MODID[475]:ARSTM2*/ + [450] = {0xFC86243CU, 0x00000001U}, /* RGIDW_MODID[476]:ARSTM3*/ + [451] = {0xFC862440U, 0x00000002U}, /* RGIDW_MODID[477]:ARSTM4*/ + [452] = {0xFC862444U, 0x00000001U}, /* RGIDW_MODID[478]:ARSTM5*/ + [453] = {0xFC862448U, 0x00000002U}, /* RGIDW_MODID[479]:ARSTM6*/ + [454] = {0xFC86244CU, 0x00000002U}, /* RGIDW_MODID[480]:ARSTM7*/ + [455] = {0xFC862450U, 0x00000000U}, /* RGIDW_MODID[481]:ARSTM8*/ + [456] = {0xFC862454U, 0x0000000AU}, /* RGIDW_MODID[482]:ECMTOP*/ + [457] = {0xFC862458U, 0x0000000EU}, /* RGIDW_MODID[483]:FBA*/ + [458] = {0xFC86245CU, 0x0000000EU}, /* RGIDW_MODID[484]:FBC*/ + [459] = {0xFC862434U, 0x0000000CU}, /* RGIDW_MODID[485]:AXICCI00*/ + [460] = {0xFC862460U, 0x0000000EU}, /* RGIDW_MODID[486]:AXICCI01*/ + [461] = {0xFC862464U, 0x0000000CU}, /* RGIDW_MODID[487]:AXICCI10*/ + [462] = {0xFC862468U, 0x0000000CU}, /* RGIDW_MODID[488]:AXICCI11*/ + [463] = {0xFC86246CU, 0x0000000CU}, /* RGIDW_MODID[489]:AXICCI12*/ + [464] = {0xFC862470U, 0x0000000CU}, /* RGIDW_MODID[490]:AXICCI13*/ + [465] = {0xFC862474U, 0x0000000CU}, /* RGIDW_MODID[491]:AXICCI14*/ + [466] = {0xFC862478U, 0x0000000CU}, /* RGIDW_MODID[492]:AXICCI15*/ + [467] = {0xFC86247CU, 0x0000000EU}, /* RGIDW_MODID[493]:AXICCI2*/ + [468] = {0xFC862480U, 0x0000000CU}, /* RGIDW_MODID[494]:AXICCI3*/ + [469] = {0xFC862484U, 0x0000000CU}, /* RGIDW_MODID[495]:AXICCI4*/ + [470] = {0xFC862488U, 0x0000000CU}, /* RGIDW_MODID[496]:AXICCI5*/ + [471] = {0xFC86248CU, 0x0000000CU}, /* RGIDW_MODID[497]:AXICCI6*/ + [472] = {0xFC862490U, 0x0000000CU}, /* RGIDW_MODID[498]:AXICCI7*/ + [473] = {0xFC862494U, 0x0000000CU}, /* RGIDW_MODID[499]:AXICCI8*/ + [474] = {0xFC862498U, 0x00000009U}, /* RGIDW_MODID[500]:AXICCI9*/ + [475] = {0xFC8624A0U, 0x0000000AU}, /* RGIDW_MODID[501]:ECMSTM*/ + [476] = {0xFCB82400U, 0x0000002CU}, /* RGIDW_MODID[502]:DMASSI00*/ + [477] = {0xFCB82404U, 0x0000002CU}, /* RGIDW_MODID[503]:DMASSI01*/ + [478] = {0xFCB82408U, 0x0000002CU}, /* RGIDW_MODID[504]:DMASSI02*/ + [479] = {0xFCB8240CU, 0x0000002CU}, /* RGIDW_MODID[505]:DMASSI03*/ + [480] = {0xFCB82410U, 0x0000002CU}, /* RGIDW_MODID[506]:DMASSI04*/ + [481] = {0xFCB82414U, 0x0000004EU}, /* RGIDW_MODID[507]:DMAI2C0*/ + [482] = {0xFCB82418U, 0x0000004EU}, /* RGIDW_MODID[508]:DMAI2C1*/ + [483] = {0xFCB8241CU, 0x0000004EU}, /* RGIDW_MODID[509]:DMAI2C2*/ + [484] = {0xFCB82420U, 0x0000004EU}, /* RGIDW_MODID[510]:DMAI2C3*/ + [485] = {0xFCB8242CU, 0x0000002CU}, /* RGIDW_MODID[511]:DMASSI05*/ + [486] = {0xFCB82430U, 0x0000002CU}, /* RGIDW_MODID[512]:DMASSI06*/ + [487] = {0xFCB82434U, 0x0000002CU}, /* RGIDW_MODID[513]:DMASSI07*/ + [488] = {0xFDDC2400U, 0x00000002U}, /* RGIDW_MODID[514]:ARMM*/ + /* After setting */ /* RGIDW_MODID[515]:AXIARNMM*/ + [489] = {0xFDDC2408U, 0x00000002U}, /* RGIDW_MODID[516]:ARSM0*/ + /* After setting */ /* RGIDW_MODID[517]:ARSM1*/ + /* After setting */ /* RGIDW_MODID[518]:ARSM2*/ + [490] = {0xFDDC2414U, 0x0000000FU}, /* RGIDW_MODID[519]:AXIQOS0*/ + [491] = {0xFDDC2418U, 0x0000000FU}, /* RGIDW_MODID[520]:AXIQOS1*/ + [492] = {0xFDDC241CU, 0x0000000FU}, /* RGIDW_MODID[521]:AXIQOS2*/ + [493] = {0xFDDC2420U, 0x0000000FU}, /* RGIDW_MODID[522]:AXIQOS3*/ + [494] = {0xFDDC2424U, 0x0000000FU}, /* RGIDW_MODID[523]:AXIQOS4*/ + [495] = {0xFDDC2428U, 0x0000000FU}, /* RGIDW_MODID[524]:AXIQOS5*/ + [496] = {0xFDDC2434U, 0x00000001U}, /* RGIDW_MODID[525]:ARSM3*/ + [497] = {0xFDDC2438U, 0x00000002U}, /* RGIDW_MODID[526]:ARSM4*/ + [498] = {0xFDDC243CU, 0x00000001U}, /* RGIDW_MODID[527]:ARSM5*/ + [499] = {0xFDDC2440U, 0x00000002U}, /* RGIDW_MODID[528]:ARSM6*/ + [500] = {0xFDDC2444U, 0x00000002U}, /* RGIDW_MODID[529]:ARSM7*/ + [501] = {0xFDDC2448U, 0x00000000U}, /* RGIDW_MODID[530]:ARSM8*/ + [502] = {0xFDDC244CU, 0x0000000BU}, /* RGIDW_MODID[531]:AXMM0*/ + [503] = {0xFDDC2450U, 0x0000000BU}, /* RGIDW_MODID[532]:AXMM1*/ + [504] = {0xFDDC2454U, 0x00000000U}, /* RGIDW_MODID[533]:AXMMPMON*/ + [505] = {0xFDDC2458U, 0x0000000AU}, /* RGIDW_MODID[534]:CKMMM*/ + [506] = {0xFDDC245CU, 0x0000000AU}, /* RGIDW_MODID[535]:ECMMM*/ + [507] = {0xFDDC2460U, 0x0000000EU}, /* RGIDW_MODID[536]:FBADBSC0*/ + [508] = {0xFDDC2468U, 0x0000000EU}, /* RGIDW_MODID[537]:FBAMM*/ + [509] = {0xFDDC246CU, 0x0000004EU}, /* RGIDW_MODID[538]:IPMMUMM00*/ + [510] = {0xFDDC2470U, 0x0000000FU}, /* RGIDW_MODID[539]:DBS0A0*/ + [511] = {0xFDDC2474U, 0x0000000AU}, /* RGIDW_MODID[540]:DBS0A1*/ + [512] = {0xFDDC2484U, 0x00000009U}, /* RGIDW_MODID[541]:FCPRC*/ + [513] = {0xFDDC2488U, 0x0000000FU}, /* RGIDW_MODID[542]:DBS0D0*/ + [514] = {0xFDDC248CU, 0x0000000AU}, /* RGIDW_MODID[543]:DBS0D1*/ + [515] = {0xFDDC2498U, 0x0000000EU}, /* RGIDW_MODID[544]:FBADDR*/ + [516] = {0xFDDC249CU, 0x0000004EU}, /* RGIDW_MODID[545]:IPMMUMM01*/ + [517] = {0xFDDC24A0U, 0x0000004EU}, /* RGIDW_MODID[546]:IPMMUMM10*/ + [518] = {0xFDDC24A4U, 0x0000004EU}, /* RGIDW_MODID[547]:IPMMUMM11*/ + [519] = {0xFDDC24A8U, 0x0000004EU}, /* RGIDW_MODID[548]:IPMMUMM12*/ + [520] = {0xFDDC24ACU, 0x0000004EU}, /* RGIDW_MODID[549]:IPMMUMM13*/ + [521] = {0xFDDC24B0U, 0x0000004EU}, /* RGIDW_MODID[550]:IPMMUMM14*/ + [522] = {0xFDDC24B4U, 0x0000004EU}, /* RGIDW_MODID[551]:IPMMUMM15*/ + [523] = {0xFDDC24B8U, 0x0000004EU}, /* RGIDW_MODID[552]:IPMMUMM02*/ + [524] = {0xFDDC24BCU, 0x0000004EU}, /* RGIDW_MODID[553]:IPMMUMM03*/ + [525] = {0xFDDC24C0U, 0x0000004EU}, /* RGIDW_MODID[554]:IPMMUMM04*/ + [526] = {0xFDDC24C4U, 0x0000004EU}, /* RGIDW_MODID[555]:IPMMUMM05*/ + [527] = {0xFDDC24C8U, 0x0000004EU}, /* RGIDW_MODID[556]:IPMMUMM06*/ + [528] = {0xFDDC24CCU, 0x0000004EU}, /* RGIDW_MODID[557]:IPMMUMM07*/ + [529] = {0xFDDC24D0U, 0x0000004EU}, /* RGIDW_MODID[558]:IPMMUMM08*/ + [530] = {0xFDDC24D4U, 0x0000004EU}, /* RGIDW_MODID[559]:IPMMUMM09*/ + [531] = {0xFC802400U, 0x00000002U}, /* RGIDW_MODID[560]:ARSN0*/ + /* After setting */ /* RGIDW_MODID[561]:ARSN1*/ + /* After setting */ /* RGIDW_MODID[562]:ARSN2*/ + [532] = {0xFC80240CU, 0x00000001U}, /* RGIDW_MODID[563]:ARSN3*/ + [533] = {0xFC802410U, 0x00000002U}, /* RGIDW_MODID[564]:ARSN4*/ + [534] = {0xFC802414U, 0x00000001U}, /* RGIDW_MODID[565]:ARSN5*/ + [535] = {0xFC802418U, 0x00000002U}, /* RGIDW_MODID[566]:ARSN6*/ + [536] = {0xFC80241CU, 0x00000002U}, /* RGIDW_MODID[567]:ARSN7*/ + [537] = {0xFC802420U, 0x00000000U}, /* RGIDW_MODID[568]:ARSN8*/ + [538] = {0xFC802424U, 0x0000000AU}, /* RGIDW_MODID[569]:ECMTOP3*/ + [539] = {0xFCB52400U, 0x00000002U}, /* RGIDW_MODID[570]:ARSD00*/ + /* After setting */ /* RGIDW_MODID[571]:ARSD01*/ + /* After setting */ /* RGIDW_MODID[572]:ARSD02*/ + [540] = {0xFCB5240CU, 0x00000001U}, /* RGIDW_MODID[573]:ARSD03*/ + [541] = {0xFCB52410U, 0x00000002U}, /* RGIDW_MODID[574]:ARSD04*/ + [542] = {0xFCB52414U, 0x00000001U}, /* RGIDW_MODID[575]:ARSD05*/ + [543] = {0xFCB52418U, 0x00000002U}, /* RGIDW_MODID[576]:ARSD06*/ + [544] = {0xFCB5241CU, 0x0000004AU}, /* RGIDW_MODID[577]:AXIFRAY*/ + [545] = {0xFCB52428U, 0x0000004FU}, /* RGIDW_MODID[578]:AXIRPC*/ + [546] = {0xFCB5242CU, 0x0000000FU}, /* RGIDW_MODID[579]:AXISDHI0*/ + [547] = {0xFCB52430U, 0x00000002U}, /* RGIDW_MODID[580]:ARSD07*/ + [548] = {0xFCB52434U, 0x00000000U}, /* RGIDW_MODID[581]:ARSD08*/ + [549] = {0xFCB52438U, 0x00000002U}, /* RGIDW_MODID[582]:ARSP00*/ + /* After setting */ /* RGIDW_MODID[583]:ARSP01*/ + /* After setting */ /* RGIDW_MODID[584]:ARSP02*/ + [550] = {0xFCB52444U, 0x00000001U}, /* RGIDW_MODID[585]:ARSP03*/ + [551] = {0xFCB52448U, 0x00000002U}, /* RGIDW_MODID[586]:ARSP04*/ + [552] = {0xFCB5244CU, 0x00000001U}, /* RGIDW_MODID[587]:ARSP05*/ + [553] = {0xFCB52450U, 0x00000002U}, /* RGIDW_MODID[588]:ARSP06*/ + [554] = {0xFCB52454U, 0x00000002U}, /* RGIDW_MODID[589]:ARSP07*/ + [555] = {0xFCB52458U, 0x00000000U}, /* RGIDW_MODID[590]:ARSP08*/ + [556] = {0xFCB5245CU, 0x0000004EU}, /* RGIDW_MODID[591]:IPMMUDS001*/ + [557] = {0xFCB52460U, 0x0000000AU}, /* RGIDW_MODID[592]:CKMPER0*/ + [558] = {0xFCB52464U, 0x0000000AU}, /* RGIDW_MODID[593]:ECMPER0*/ + [559] = {0xFCB52468U, 0x0000000EU}, /* RGIDW_MODID[594]:FBAPER0*/ + [560] = {0xFCB5246CU, 0x0000004EU}, /* RGIDW_MODID[595]:FSO0*/ + [561] = {0xFCB52470U, 0x0000004EU}, /* RGIDW_MODID[596]:FSO1*/ + [562] = {0xFCB52474U, 0x0000004EU}, /* RGIDW_MODID[597]:FSO10*/ + [563] = {0xFCB52478U, 0x0000004EU}, /* RGIDW_MODID[598]:FSO2*/ + [564] = {0xFCB5247CU, 0x0000004EU}, /* RGIDW_MODID[599]:FSO3*/ + [565] = {0xFCB52480U, 0x0000004EU}, /* RGIDW_MODID[600]:FSO4*/ + [566] = {0xFCB52484U, 0x0000004EU}, /* RGIDW_MODID[601]:FSO5*/ + [567] = {0xFCB52488U, 0x0000004EU}, /* RGIDW_MODID[602]:FSO6*/ + [568] = {0xFCB5248CU, 0x0000004EU}, /* RGIDW_MODID[603]:FSO7*/ + [569] = {0xFCB52490U, 0x0000004EU}, /* RGIDW_MODID[604]:FSO8*/ + [570] = {0xFCB52494U, 0x0000004EU}, /* RGIDW_MODID[605]:FSO9*/ + [571] = {0xFCB52498U, 0x0000002CU}, /* RGIDW_MODID[606]:ADG*/ + [572] = {0xFCB5249CU, 0x0000000AU}, /* RGIDW_MODID[607]:ECMSD0*/ + [573] = {0xFCB524A0U, 0x0000004EU}, /* RGIDW_MODID[608]:IPMMUDS010*/ + [574] = {0xFCB524A4U, 0x0000004EU}, /* RGIDW_MODID[609]:IPMMUDS011*/ + [575] = {0xFCB524A8U, 0x0000004EU}, /* RGIDW_MODID[610]:I2C0*/ + [576] = {0xFCB524ACU, 0x0000004EU}, /* RGIDW_MODID[611]:I2C1*/ + [577] = {0xFCB524B0U, 0x0000004EU}, /* RGIDW_MODID[612]:I2C2*/ + [578] = {0xFCB524B4U, 0x0000004EU}, /* RGIDW_MODID[613]:I2C3*/ + [579] = {0xFCB524C0U, 0x0000004EU}, /* RGIDW_MODID[614]:IPMMUDS012*/ + [580] = {0xFCB524C8U, 0x0000004EU}, /* RGIDW_MODID[615]:IPMMUDS000*/ + [581] = {0xFCB524CCU, 0x0000004EU}, /* RGIDW_MODID[616]:IPMMUDS013*/ + [582] = {0xFCB524D0U, 0x0000004EU}, /* RGIDW_MODID[617]:IPMMUDS014*/ + [583] = {0xFCB524D4U, 0x0000004EU}, /* RGIDW_MODID[618]:IPMMUDS015*/ + [584] = {0xFCB524D8U, 0x0000004EU}, /* RGIDW_MODID[619]:IPMMUDS002*/ + [585] = {0xFCB524DCU, 0x0000004EU}, /* RGIDW_MODID[620]:IPMMUDS003*/ + [586] = {0xFCB524E0U, 0x0000004EU}, /* RGIDW_MODID[621]:IPMMUDS004*/ + [587] = {0xFCB524E4U, 0x0000004EU}, /* RGIDW_MODID[622]:IPMMUDS005*/ + [588] = {0xFCB524E8U, 0x0000002CU}, /* RGIDW_MODID[623]:SSI*/ + [589] = {0xFCB524ECU, 0x0000004EU}, /* RGIDW_MODID[624]:IPMMUDS006*/ + [590] = {0xFCB524F0U, 0x0000004EU}, /* RGIDW_MODID[625]:IPMMUDS007*/ + [591] = {0xFCB524F4U, 0x0000000CU}, /* RGIDW_MODID[626]:SYDM1P*/ + [592] = {0xFCB524F8U, 0x0000004EU}, /* RGIDW_MODID[627]:IPMMUDS008*/ + [593] = {0xFCB524FCU, 0x0000000CU}, /* RGIDW_MODID[628]:SYDM2P*/ + [594] = {0xFCB52500U, 0x0000004EU}, /* RGIDW_MODID[629]:IPMMUDS009*/ + [595] = {0xFCB52640U, 0x0000000CU}, /* RGIDW_MODID[630]:SYDM100*/ + [596] = {0xFCB52644U, 0x0000000CU}, /* RGIDW_MODID[631]:SYDM101*/ + [597] = {0xFCB52648U, 0x0000000CU}, /* RGIDW_MODID[632]:SYDM110*/ + [598] = {0xFCB5264CU, 0x0000000CU}, /* RGIDW_MODID[633]:SYDM111*/ + [599] = {0xFCB52650U, 0x0000000CU}, /* RGIDW_MODID[634]:SYDM112*/ + [600] = {0xFCB52654U, 0x0000000CU}, /* RGIDW_MODID[635]:SYDM113*/ + [601] = {0xFCB52658U, 0x0000000CU}, /* RGIDW_MODID[636]:SYDM114*/ + [602] = {0xFCB5265CU, 0x0000000CU}, /* RGIDW_MODID[637]:SYDM115*/ + [603] = {0xFCB52660U, 0x0000000CU}, /* RGIDW_MODID[638]:SYDM102*/ + [604] = {0xFCB52664U, 0x0000000CU}, /* RGIDW_MODID[639]:SYDM103*/ + [605] = {0xFCB52668U, 0x0000000CU}, /* RGIDW_MODID[640]:SYDM104*/ + [606] = {0xFCB5266CU, 0x0000000CU}, /* RGIDW_MODID[641]:SYDM105*/ + [607] = {0xFCB52670U, 0x0000000CU}, /* RGIDW_MODID[642]:SYDM106*/ + [608] = {0xFCB52674U, 0x0000000CU}, /* RGIDW_MODID[643]:SYDM107*/ + [609] = {0xFCB52678U, 0x0000000CU}, /* RGIDW_MODID[644]:SYDM108*/ + [610] = {0xFCB5267CU, 0x0000000CU}, /* RGIDW_MODID[645]:SYDM109*/ + [611] = {0xFCB52680U, 0x0000000CU}, /* RGIDW_MODID[646]:SYDM200*/ + [612] = {0xFCB52684U, 0x0000000CU}, /* RGIDW_MODID[647]:SYDM201*/ + [613] = {0xFCB52688U, 0x0000000CU}, /* RGIDW_MODID[648]:SYDM210*/ + [614] = {0xFCB5268CU, 0x0000000CU}, /* RGIDW_MODID[649]:SYDM211*/ + [615] = {0xFCB52690U, 0x0000000CU}, /* RGIDW_MODID[650]:SYDM212*/ + [616] = {0xFCB52694U, 0x0000000CU}, /* RGIDW_MODID[651]:SYDM213*/ + [617] = {0xFCB52698U, 0x0000000CU}, /* RGIDW_MODID[652]:SYDM214*/ + [618] = {0xFCB5269CU, 0x0000000CU}, /* RGIDW_MODID[653]:SYDM215*/ + [619] = {0xFCB526A0U, 0x0000000CU}, /* RGIDW_MODID[654]:SYDM202*/ + [620] = {0xFCB526A4U, 0x0000000CU}, /* RGIDW_MODID[655]:SYDM203*/ + [621] = {0xFCB526A8U, 0x0000000CU}, /* RGIDW_MODID[656]:SYDM204*/ + [622] = {0xFCB526ACU, 0x0000000CU}, /* RGIDW_MODID[657]:SYDM205*/ + [623] = {0xFCB526B0U, 0x0000000CU}, /* RGIDW_MODID[658]:SYDM206*/ + [624] = {0xFCB526B4U, 0x0000000CU}, /* RGIDW_MODID[659]:SYDM207*/ + [625] = {0xFCB526B8U, 0x0000000CU}, /* RGIDW_MODID[660]:SYDM208*/ + [626] = {0xFCB526BCU, 0x0000000CU}, /* RGIDW_MODID[661]:SYDM209*/ + [627] = {0xFC682400U, 0x00000002U}, /* RGIDW_MODID[662]:ARVC0*/ + /* After setting */ /* RGIDW_MODID[663]:ARVC1*/ + /* After setting */ /* RGIDW_MODID[664]:ARVC2*/ + [628] = {0xFC68240CU, 0x00000001U}, /* RGIDW_MODID[665]:ARVC3*/ + [629] = {0xFC682410U, 0x0000000EU}, /* RGIDW_MODID[666]:AXIFBABUSVC*/ + [630] = {0xFC682414U, 0x00000002U}, /* RGIDW_MODID[667]:ARVC4*/ + [631] = {0xFC682418U, 0x00000001U}, /* RGIDW_MODID[668]:ARVC5*/ + [632] = {0xFC68241CU, 0x00000002U}, /* RGIDW_MODID[669]:ARVC6*/ + [633] = {0xFC682420U, 0x00000002U}, /* RGIDW_MODID[670]:ARVC7*/ + [634] = {0xFC682424U, 0x00000000U}, /* RGIDW_MODID[671]:ARVC8*/ + [635] = {0xFC68242CU, 0x0000000AU}, /* RGIDW_MODID[672]:ECMVC0*/ + [636] = {0xFC682434U, 0x0000004EU}, /* RGIDW_MODID[673]:IMR0*/ + [637] = {0xFC682438U, 0x0000004EU}, /* RGIDW_MODID[674]:IMR1*/ + [638] = {0xFC68243CU, 0x0000004EU}, /* RGIDW_MODID[675]:IPMMUVC01*/ + [639] = {0xFC682440U, 0x0000004EU}, /* RGIDW_MODID[676]:IPMMUVC10*/ + [640] = {0xFC682444U, 0x0000000CU}, /* RGIDW_MODID[677]:IMS0*/ + [641] = {0xFC682448U, 0x0000000CU}, /* RGIDW_MODID[678]:IMS1*/ + [642] = {0xFC68244CU, 0x0000004EU}, /* RGIDW_MODID[679]:IPMMUVC00*/ + [643] = {0xFC682450U, 0x0000004EU}, /* RGIDW_MODID[680]:IPMMUVC11*/ + [644] = {0xFC682454U, 0x0000004EU}, /* RGIDW_MODID[681]:IPMMUVC12*/ + [645] = {0xFC682458U, 0x0000004EU}, /* RGIDW_MODID[682]:IPMMUVC13*/ + [646] = {0xFC68245CU, 0x0000004EU}, /* RGIDW_MODID[683]:IPMMUVC14*/ + [647] = {0xFC682460U, 0x0000004EU}, /* RGIDW_MODID[684]:IPMMUVC15*/ + [648] = {0xFC682464U, 0x0000004EU}, /* RGIDW_MODID[685]:IPMMUVC02*/ + [649] = {0xFC682468U, 0x0000004EU}, /* RGIDW_MODID[686]:IPMMUVC03*/ + [650] = {0xFC68246CU, 0x0000004EU}, /* RGIDW_MODID[687]:IPMMUVC04*/ + [651] = {0xFC682470U, 0x0000004EU}, /* RGIDW_MODID[688]:IPMMUVC05*/ + [652] = {0xFC682474U, 0x0000004EU}, /* RGIDW_MODID[689]:IPMMUVC06*/ + [653] = {0xFC682478U, 0x0000004EU}, /* RGIDW_MODID[690]:IPMMUVC07*/ + [654] = {0xFC68247CU, 0x0000004EU}, /* RGIDW_MODID[691]:IPMMUVC08*/ + [655] = {0xFC682480U, 0x0000004EU}, /* RGIDW_MODID[692]:IPMMUVC09*/ + [656] = {0xFC682484U, 0x00000028U}, /* RGIDW_MODID[693]:IV1ES*/ + [657] = {0xFEBE2400U, 0x0000004EU}, /* RGIDW_MODID[694]:CSITOP0*/ + [658] = {0xFEBE2404U, 0x00000002U}, /* RGIDW_MODID[695]:ARVI10*/ + /* After setting */ /* RGIDW_MODID[696]:ARVI11*/ + /* After setting */ /* RGIDW_MODID[697]:ARVI12*/ + [659] = {0xFEBE2410U, 0x00000001U}, /* RGIDW_MODID[698]:ARVI13*/ + [660] = {0xFEBE2414U, 0x00000002U}, /* RGIDW_MODID[699]:ARVI14*/ + [661] = {0xFEBE2418U, 0x00000001U}, /* RGIDW_MODID[700]:ARVI15*/ + [662] = {0xFEBE241CU, 0x00000002U}, /* RGIDW_MODID[701]:ARVI16*/ + [663] = {0xFEBE2420U, 0x00000002U}, /* RGIDW_MODID[702]:ARVI17*/ + [664] = {0xFEBE2424U, 0x00000000U}, /* RGIDW_MODID[703]:ARVI18*/ + [665] = {0xFEBE242CU, 0x0000004EU}, /* RGIDW_MODID[704]:CSITOP1*/ + [666] = {0xFEBE2434U, 0x0000004EU}, /* RGIDW_MODID[705]:DSITLINK0*/ + [667] = {0xFEBE243CU, 0x0000000AU}, /* RGIDW_MODID[706]:ECMVIO1*/ + [668] = {0xFEBE2444U, 0x0000004EU}, /* RGIDW_MODID[707]:IPMMUVI001*/ + [669] = {0xFEBE2448U, 0x0000000CU}, /* RGIDW_MODID[708]:FCPVX0*/ + [670] = {0xFEBE2458U, 0x0000004EU}, /* RGIDW_MODID[709]:IPMMUVI000*/ + [671] = {0xFEBE245CU, 0x0000004EU}, /* RGIDW_MODID[710]:IPMMUVI100*/ + [672] = {0xFEBE2460U, 0x0000004EU}, /* RGIDW_MODID[711]:IPMMUVI010*/ + [673] = {0xFEBE2464U, 0x0000004EU}, /* RGIDW_MODID[712]:IPMMUVI011*/ + [674] = {0xFEBE2468U, 0x0000004EU}, /* RGIDW_MODID[713]:VSPX0*/ + [675] = {0xFEBE2478U, 0x0000004EU}, /* RGIDW_MODID[714]:IPMMUVI012*/ + [676] = {0xFEBE247CU, 0x0000004EU}, /* RGIDW_MODID[715]:IPMMUVI013*/ + [677] = {0xFEBE2480U, 0x0000004EU}, /* RGIDW_MODID[716]:IPMMUVI014*/ + [678] = {0xFEBE2484U, 0x0000004EU}, /* RGIDW_MODID[717]:IPMMUVI015*/ + [679] = {0xFEBE2488U, 0x0000004EU}, /* RGIDW_MODID[718]:IPMMUVI002*/ + [680] = {0xFEBE248CU, 0x0000004EU}, /* RGIDW_MODID[719]:IPMMUVI003*/ + [681] = {0xFEBE2490U, 0x0000004EU}, /* RGIDW_MODID[720]:IPMMUVI004*/ + [682] = {0xFEBE2494U, 0x0000004EU}, /* RGIDW_MODID[721]:IPMMUVI005*/ + [683] = {0xFEBE2498U, 0x0000004EU}, /* RGIDW_MODID[722]:IPMMUVI006*/ + [684] = {0xFEBE249CU, 0x0000004EU}, /* RGIDW_MODID[723]:IPMMUVI007*/ + [685] = {0xFEBE24A0U, 0x0000004EU}, /* RGIDW_MODID[724]:IPMMUVI008*/ + [686] = {0xFEBE24A4U, 0x0000004EU}, /* RGIDW_MODID[725]:IPMMUVI009*/ + [687] = {0xFEBE24A8U, 0x0000004EU}, /* RGIDW_MODID[726]:IPMMUVI101*/ + [688] = {0xFEBE24ACU, 0x0000004EU}, /* RGIDW_MODID[727]:IPMMUVI110*/ + [689] = {0xFEBE24B0U, 0x0000004EU}, /* RGIDW_MODID[728]:IPMMUVI111*/ + [690] = {0xFEBE24B4U, 0x0000004EU}, /* RGIDW_MODID[729]:IPMMUVI112*/ + [691] = {0xFEBE24B8U, 0x0000004EU}, /* RGIDW_MODID[730]:IPMMUVI113*/ + [692] = {0xFEBE24BCU, 0x0000004EU}, /* RGIDW_MODID[731]:IPMMUVI114*/ + [693] = {0xFEBE24C0U, 0x0000004EU}, /* RGIDW_MODID[732]:IPMMUVI115*/ + [694] = {0xFEBE24C4U, 0x0000004EU}, /* RGIDW_MODID[733]:IPMMUVI102*/ + [695] = {0xFEBE24C8U, 0x0000004EU}, /* RGIDW_MODID[734]:IPMMUVI103*/ + [696] = {0xFEBE24CCU, 0x0000004EU}, /* RGIDW_MODID[735]:IPMMUVI104*/ + [697] = {0xFEBE24D0U, 0x0000004EU}, /* RGIDW_MODID[736]:IPMMUVI105*/ + [698] = {0xFEBE24D4U, 0x0000004EU}, /* RGIDW_MODID[737]:IPMMUVI106*/ + [699] = {0xFEBE24D8U, 0x0000004EU}, /* RGIDW_MODID[738]:IPMMUVI107*/ + [700] = {0xFEBE24DCU, 0x0000004EU}, /* RGIDW_MODID[739]:IPMMUVI108*/ + [701] = {0xFEBE24E0U, 0x0000004EU}, /* RGIDW_MODID[740]:IPMMUVI109*/ + [702] = {0xFEBE2504U, 0x0000000EU}, /* RGIDW_MODID[741]:AXIFBABUSVIO*/ + [703] = {0xFEBF2400U, 0x00000002U}, /* RGIDW_MODID[742]:ARVI0*/ + /* After setting */ /* RGIDW_MODID[743]:ARVI1*/ + /* After setting */ /* RGIDW_MODID[744]:ARVI2*/ + [704] = {0xFEBF240CU, 0x00000001U}, /* RGIDW_MODID[745]:ARVI3*/ + [705] = {0xFEBF2410U, 0x00000002U}, /* RGIDW_MODID[746]:ARVI4*/ + [706] = {0xFEBF2414U, 0x00000001U}, /* RGIDW_MODID[747]:ARVI5*/ + [707] = {0xFEBF2418U, 0x00000002U}, /* RGIDW_MODID[748]:ARVI6*/ + [708] = {0xFEBF241CU, 0x00000002U}, /* RGIDW_MODID[749]:ARVI7*/ + [709] = {0xFEBF2420U, 0x00000000U}, /* RGIDW_MODID[750]:ARVI8*/ + [710] = {0xFEBF2424U, 0x0000000AU}, /* RGIDW_MODID[751]:ECMVIO0*/ + [711] = {0xFEBF2428U, 0x0000004EU}, /* RGIDW_MODID[752]:ISP0*/ + [712] = {0xFEBF242CU, 0x0000004EU}, /* RGIDW_MODID[753]:ISP0CORE*/ + [713] = {0xFEBF2430U, 0x0000004EU}, /* RGIDW_MODID[754]:ISP1*/ + [714] = {0xFEBF2454U, 0x0000004EU}, /* RGIDW_MODID[755]:VIN00*/ + [715] = {0xFEBF2458U, 0x0000004EU}, /* RGIDW_MODID[756]:VIN01*/ + [716] = {0xFEBF245CU, 0x0000004EU}, /* RGIDW_MODID[757]:VIN02*/ + [717] = {0xFEBF2460U, 0x0000004EU}, /* RGIDW_MODID[758]:VIN03*/ + [718] = {0xFEBF2464U, 0x0000004EU}, /* RGIDW_MODID[759]:VIN04*/ + [719] = {0xFEBF2468U, 0x0000004EU}, /* RGIDW_MODID[760]:VIN05*/ + [720] = {0xFEBF246CU, 0x0000004EU}, /* RGIDW_MODID[761]:VIN06*/ + [721] = {0xFEBF2470U, 0x0000004EU}, /* RGIDW_MODID[762]:VIN07*/ + [722] = {0xFEBF2474U, 0x0000004EU}, /* RGIDW_MODID[763]:VIN10*/ + [723] = {0xFEBF2478U, 0x0000004EU}, /* RGIDW_MODID[764]:VIN11*/ + [724] = {0xFEBF247CU, 0x0000004EU}, /* RGIDW_MODID[765]:VIN12*/ + [725] = {0xFEBF2480U, 0x0000004EU}, /* RGIDW_MODID[766]:VIN13*/ + [726] = {0xFEBF2484U, 0x0000004EU}, /* RGIDW_MODID[767]:VIN14*/ + [727] = {0xFEBF2488U, 0x0000004EU}, /* RGIDW_MODID[768]:VIN15*/ + [728] = {0xFEBF248CU, 0x0000004EU}, /* RGIDW_MODID[769]:VIN16*/ + [729] = {0xFEBF2490U, 0x0000004EU}, /* RGIDW_MODID[770]:VIN17*/ + [730] = {0xFC312400U, 0x00000002U}, /* RGIDW_MODID[771]:ARVIP00*/ + /* After setting */ /* RGIDW_MODID[772]:ARVIP01*/ + /* After setting */ /* RGIDW_MODID[773]:ARVIP02*/ + [731] = {0xFC31240CU, 0x00000001U}, /* RGIDW_MODID[774]:ARVIP03*/ + [732] = {0xFC312410U, 0x0000000EU}, /* RGIDW_MODID[775]:AXIFBABUSVIP0*/ + [733] = {0xFC312414U, 0x00000002U}, /* RGIDW_MODID[776]:ARVIP04*/ + [734] = {0xFC312418U, 0x00000001U}, /* RGIDW_MODID[777]:ARVIP05*/ + [735] = {0xFC31241CU, 0x00000002U}, /* RGIDW_MODID[778]:ARVIP06*/ + [736] = {0xFC312420U, 0x00000002U}, /* RGIDW_MODID[779]:ARVIP07*/ + [737] = {0xFC312424U, 0x00000000U}, /* RGIDW_MODID[780]:ARVIP08*/ + [738] = {0xFC31242CU, 0x0000000AU}, /* RGIDW_MODID[781]:ECMVIP0*/ + [739] = {0xFC312430U, 0x0000004EU}, /* RGIDW_MODID[782]:IPMMUVIP000*/ + [740] = {0xFC312438U, 0x0000004EU}, /* RGIDW_MODID[783]:SMPO0*/ + [741] = {0xFC31243CU, 0x0000004EU}, /* RGIDW_MODID[784]:SMPS0*/ + [742] = {0xFC312440U, 0x0000004EU}, /* RGIDW_MODID[785]:UMFL0*/ + [743] = {0xFC312444U, 0x0000004EU}, /* RGIDW_MODID[786]:IPMMUVIP001*/ + [744] = {0xFC312448U, 0x0000004EU}, /* RGIDW_MODID[787]:IPMMUVIP010*/ + [745] = {0xFC31244CU, 0x0000004EU}, /* RGIDW_MODID[788]:IPMMUVIP011*/ + [746] = {0xFC312450U, 0x0000004EU}, /* RGIDW_MODID[789]:UMFL0M_W*/ + [747] = {0xFC312454U, 0x0000004EU}, /* RGIDW_MODID[790]:IPMMUVIP012*/ + [748] = {0xFC312458U, 0x0000004EU}, /* RGIDW_MODID[791]:IPMMUVIP013*/ + [749] = {0xFC31245CU, 0x0000004EU}, /* RGIDW_MODID[792]:IPMMUVIP014*/ + [750] = {0xFC312460U, 0x0000004EU}, /* RGIDW_MODID[793]:IPMMUVIP015*/ + [751] = {0xFC312464U, 0x0000004EU}, /* RGIDW_MODID[794]:IPMMUVIP002*/ + [752] = {0xFC312468U, 0x0000004EU}, /* RGIDW_MODID[795]:IPMMUVIP003*/ + [753] = {0xFC31246CU, 0x0000004EU}, /* RGIDW_MODID[796]:IPMMUVIP004*/ + [754] = {0xFC312470U, 0x0000004EU}, /* RGIDW_MODID[797]:IPMMUVIP005*/ + [755] = {0xFC312474U, 0x0000004EU}, /* RGIDW_MODID[798]:IPMMUVIP006*/ + [756] = {0xFC312478U, 0x0000004EU}, /* RGIDW_MODID[799]:IPMMUVIP007*/ + [757] = {0xFC31247CU, 0x0000004EU}, /* RGIDW_MODID[800]:IPMMUVIP008*/ + [758] = {0xFC312480U, 0x0000004EU}, /* RGIDW_MODID[801]:IPMMUVIP009*/ + [759] = {0xFC8824A0U, 0x00000002U}, /* RGIDW_MODID[802]:ARDSP0*/ + /* After setting */ /* RGIDW_MODID[803]:ARDSP1*/ + /* After setting */ /* RGIDW_MODID[804]:ARDSP2*/ + [760] = {0xFC8824ACU, 0x00000001U}, /* RGIDW_MODID[805]:ARDSP3*/ + [761] = {0xFC8824B0U, 0x00000002U}, /* RGIDW_MODID[806]:ARDSP4*/ + [762] = {0xFC8824B4U, 0x00000001U}, /* RGIDW_MODID[807]:ARDSP5*/ + [763] = {0xFC8824B8U, 0x00000002U}, /* RGIDW_MODID[808]:ARDSP6*/ + [764] = {0xFC8824BCU, 0x00000002U}, /* RGIDW_MODID[809]:ARDSP7*/ + [765] = {0xFC8824C0U, 0x0000000AU}, /* RGIDW_MODID[810]:ECMDSP*/ + [766] = {0xFC882490U, 0x0000000CU}, /* RGIDW_MODID[811]:AXIDSP0*/ + [767] = {0xFC882494U, 0x0000000CU}, /* RGIDW_MODID[812]:AXIDSP1*/ + [768] = {0xFC882498U, 0x0000000CU}, /* RGIDW_MODID[813]:AXIDSP2*/ + [769] = {0xFC88249CU, 0x0000000CU}, /* RGIDW_MODID[814]:AXIDSP3*/ + [771] = {0xFDDB969CU, 0x00000000U}, /* RGIDW_MODID[815]:ARCC*/ + [770] = {0xFDDB96B0U, 0x00000000U}, /* RGIDW_MODID[816]:ARRTRAM*/ + [772] = {0xFCB52424U, 0x00000000U}, /* RGIDW_MODID[817]:RSV0*/ + [773] = {0xFC31250CU, 0x00000004U}, /* RGIDW_MODID[818]:PAP*/ + [774] = {0xFC8824C4U, 0x0000004EU}, /* RGIDW_MODID[819]:IMPM0100*/ + [775] = {0xFC8824C8U, 0x0000004EU}, /* RGIDW_MODID[820]:IMPM0101*/ + [776] = {0xFC8824CCU, 0x0000004EU}, /* RGIDW_MODID[821]:IMPM0102*/ + [777] = {0xFC8824D0U, 0x0000004EU}, /* RGIDW_MODID[822]:IMPM0103*/ + [778] = {0xFC8824D4U, 0x0000004EU}, /* RGIDW_MODID[823]:IMPM0104*/ + [779] = {0xFC8824D8U, 0x0000004EU}, /* RGIDW_MODID[824]:IMPM0105*/ + [780] = {0xFC8824DCU, 0x0000004EU}, /* RGIDW_MODID[825]:IMPM0106*/ + [781] = {0xFC8824E0U, 0x0000004EU}, /* RGIDW_MODID[826]:IMPM0107*/ + [782] = {0xFC8824E4U, 0x0000004EU}, /* RGIDW_MODID[827]:IMPM0200*/ + [783] = {0xFC8824E8U, 0x0000004EU}, /* RGIDW_MODID[828]:IMPM0201*/ + [784] = {0xFC8824ECU, 0x0000004EU}, /* RGIDW_MODID[829]:IMPS0000*/ + [785] = {0xFC8824F0U, 0x0000004EU}, /* RGIDW_MODID[830]:IMPS0001*/ + [786] = {0xFC8824F4U, 0x0000004EU}, /* RGIDW_MODID[831]:IMPS0002*/ + [787] = {0xFC8824F8U, 0x0000004EU}, /* RGIDW_MODID[832]:IMPS0003*/ + [788] = {0xFC8824FCU, 0x0000004EU}, /* RGIDW_MODID[833]:IMPS0100*/ + [789] = {0xFC882500U, 0x0000004EU}, /* RGIDW_MODID[834]:IMPS0101*/ + [790] = {0xFC882504U, 0x0000004EU}, /* RGIDW_MODID[835]:IMPS0102*/ + [791] = {0xFC882508U, 0x0000004EU}, /* RGIDW_MODID[836]:IMPS0103*/ + [792] = {0xFC88250CU, 0x0000004EU}, /* RGIDW_MODID[837]:IMPS0104*/ + [793] = {0xFC882510U, 0x0000004EU}, /* RGIDW_MODID[838]:IMPS0105*/ + [794] = {0xFC882514U, 0x0000004EU}, /* RGIDW_MODID[839]:IMPS0106*/ + [795] = {0xFC882518U, 0x0000004EU}, /* RGIDW_MODID[840]:IMPS0107*/ + [796] = {0xFC88251CU, 0x0000004EU}, /* RGIDW_MODID[841]:IMPS0108*/ + [797] = {0xFC882520U, 0x0000004EU}, /* RGIDW_MODID[842]:IMPS0109*/ + [798] = {0xFC882524U, 0x0000004EU}, /* RGIDW_MODID[843]:IMPS0110*/ + [799] = {0xFC882528U, 0x0000004EU}, /* RGIDW_MODID[844]:IMPS0111*/ + [800] = {0xFC88252CU, 0x0000004EU}, /* RGIDW_MODID[845]:IMPS0200*/ + [801] = {0xFC882530U, 0x0000004EU}, /* RGIDW_MODID[846]:IMPS0201*/ + [802] = {0xFC882534U, 0x0000004EU}, /* RGIDW_MODID[847]:IMPS0202*/ + [803] = {0xFEBD2428U, 0x0000000CU}, /* RGIDW_MODID[848]:DOC*/ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_sec_tbl" +const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[] = { + [0] = {0xFD483400U, 0x00000000U}, /* SEC_MODID[0]:ARMGC0*/ + [1] = {0xFD483404U, 0x00000002U}, /* SEC_MODID[1]:ARMGC1*/ + [2] = {0xFD483408U, 0x00000002U}, /* SEC_MODID[2]:ARMGC2*/ + [3] = {0xFD48340CU, 0x00000002U}, /* SEC_MODID[3]:ARRT00*/ + [4] = {0xFD483410U, 0x00000002U}, /* SEC_MODID[4]:ARRT01*/ + [5] = {0xFD483414U, 0x00000002U}, /* SEC_MODID[5]:ARRT02*/ + [6] = {0xFD483418U, 0x00000002U}, /* SEC_MODID[6]:ARRT03*/ + [7] = {0xFD48341CU, 0x00000002U}, /* SEC_MODID[7]:ARRT04*/ + [8] = {0xFD483420U, 0x00000002U}, /* SEC_MODID[8]:ARRT05*/ + [9] = {0xFD483424U, 0x00000002U}, /* SEC_MODID[9]:ARRT06*/ + [10] = {0xFD483428U, 0x00000002U}, /* SEC_MODID[10]:ARRT07*/ + [11] = {0xFD48342CU, 0x00000002U}, /* SEC_MODID[11]:ARRT08*/ + [12] = {0xFD483430U, 0x00000000U}, /* SEC_MODID[12]:LIFEC0*/ + [13] = {0xFD483434U, 0x00000002U}, /* SEC_MODID[13]:SWDT*/ + [14] = {0xFD483438U, 0x00000002U}, /* SEC_MODID[14]:TMU0*/ + [15] = {0xFD48343CU, 0x00000002U}, /* SEC_MODID[15]:WDT*/ + [16] = {0xFD483440U, 0x00000002U}, /* SEC_MODID[16]:WWDT0*/ + [17] = {0xFD483444U, 0x00000002U}, /* SEC_MODID[17]:WWDT1*/ + [18] = {0xFD483448U, 0x00000002U}, /* SEC_MODID[18]:WWDT2*/ + [19] = {0xFD48344CU, 0x00000002U}, /* SEC_MODID[19]:WWDT3*/ + [20] = {0xFD483450U, 0x00000002U}, /* SEC_MODID[20]:WWDT4*/ + [21] = {0xFD483454U, 0x00000002U}, /* SEC_MODID[21]:WWDT5*/ + [22] = {0xFD483458U, 0x00000002U}, /* SEC_MODID[22]:WWDT6*/ + [23] = {0xFD483468U, 0x00000002U}, /* SEC_MODID[23]:ECMRT3*/ + [24] = {0xFDA03404U, 0x00000002U}, /* SEC_MODID[24]:APMU0*/ + [25] = {0xFDA03408U, 0x00000002U}, /* SEC_MODID[25]:APMU1*/ + [26] = {0xFDA0340CU, 0x00000002U}, /* SEC_MODID[26]:APMU10*/ + [27] = {0xFDA03410U, 0x00000002U}, /* SEC_MODID[27]:APMU11*/ + [28] = {0xFDA03414U, 0x00000002U}, /* SEC_MODID[28]:APMU12*/ + [29] = {0xFDA03418U, 0x00000002U}, /* SEC_MODID[29]:APMU13*/ + [30] = {0xFDA0341CU, 0x00000002U}, /* SEC_MODID[30]:APMU14*/ + [31] = {0xFDA03420U, 0x00000002U}, /* SEC_MODID[31]:APMU15*/ + [32] = {0xFDA03424U, 0x00000002U}, /* SEC_MODID[32]:APMU2*/ + [33] = {0xFDA03428U, 0x00000002U}, /* SEC_MODID[33]:APMU3*/ + [34] = {0xFDA0342CU, 0x00000002U}, /* SEC_MODID[34]:APMU4*/ + [35] = {0xFDA03430U, 0x00000002U}, /* SEC_MODID[35]:APMU5*/ + [36] = {0xFDA03434U, 0x00000002U}, /* SEC_MODID[36]:APMU6*/ + [37] = {0xFDA03438U, 0x00000002U}, /* SEC_MODID[37]:APMU7*/ + [38] = {0xFDA0343CU, 0x00000002U}, /* SEC_MODID[38]:APMU8*/ + [39] = {0xFDA03440U, 0x00000002U}, /* SEC_MODID[39]:APMU9*/ + [40] = {0xFDA03444U, 0x00000002U}, /* SEC_MODID[40]:ARS00*/ + [41] = {0xFDA03448U, 0x00000002U}, /* SEC_MODID[41]:ARS01*/ + [42] = {0xFDA0344CU, 0x00000002U}, /* SEC_MODID[42]:ARS02*/ + [43] = {0xFDA03450U, 0x00000002U}, /* SEC_MODID[43]:ARS03*/ + [44] = {0xFDA03454U, 0x00000002U}, /* SEC_MODID[44]:ARS04*/ + [45] = {0xFDA03458U, 0x00000002U}, /* SEC_MODID[45]:ARS05*/ + [46] = {0xFDA0345CU, 0x00000002U}, /* SEC_MODID[46]:ARS06*/ + [47] = {0xFDA03460U, 0x00000002U}, /* SEC_MODID[47]:ARS07*/ + [48] = {0xFDA03464U, 0x00000002U}, /* SEC_MODID[48]:ARS08*/ + [49] = {0xFDA03468U, 0x00000002U}, /* SEC_MODID[49]:CMT0*/ + [50] = {0xFDA0346CU, 0x00000002U}, /* SEC_MODID[50]:CMT1*/ + [51] = {0xFDA03470U, 0x00000002U}, /* SEC_MODID[51]:CMT2*/ + [52] = {0xFDA03474U, 0x00000002U}, /* SEC_MODID[52]:CMT3*/ + [53] = {0xFDA03478U, 0x00000002U}, /* SEC_MODID[53]:CKM*/ + [54] = {0xFDA0347CU, 0x00000002U}, /* SEC_MODID[54]:DBE*/ + [55] = {0xFDA03480U, 0x00000002U}, /* SEC_MODID[55]:IRQC*/ + [56] = {0xFDA03484U, 0x00000002U}, /* SEC_MODID[56]:ECMPS0*/ + [57] = {0xFDA03488U, 0x00000002U}, /* SEC_MODID[57]:OTP0*/ + [58] = {0xFDA0348CU, 0x00000002U}, /* SEC_MODID[58]:OTP1*/ + [59] = {0xFDA0349CU, 0x00000002U}, /* SEC_MODID[59]:SCMT*/ + [60] = {0xFDA034A8U, 0x00000002U}, /* SEC_MODID[60]:TSC1*/ + [61] = {0xFDA034ACU, 0x00000002U}, /* SEC_MODID[61]:TSC2*/ + [62] = {0xFDA034B8U, 0x00000002U}, /* SEC_MODID[62]:UCMT*/ + [63] = {0xFDA03500U, 0x00000002U}, /* SEC_MODID[63]:CPG0*/ + [64] = {0xFDA03504U, 0x00000002U}, /* SEC_MODID[64]:CPG1*/ + [65] = {0xFDA03508U, 0x00000002U}, /* SEC_MODID[65]:CPG2*/ + [66] = {0xFDA0350CU, 0x00000002U}, /* SEC_MODID[66]:CPG3*/ + [67] = {0xFDA03510U, 0x00000002U}, /* SEC_MODID[67]:PFC00*/ + [68] = {0xFDA03514U, 0x00000002U}, /* SEC_MODID[68]:PFC01*/ + [69] = {0xFDA03518U, 0x00000002U}, /* SEC_MODID[69]:PFC02*/ + [70] = {0xFDA0351CU, 0x00000002U}, /* SEC_MODID[70]:PFC03*/ + [71] = {0xFDA03520U, 0x00000002U}, /* SEC_MODID[71]:PFC10*/ + [72] = {0xFDA03524U, 0x00000002U}, /* SEC_MODID[72]:PFC11*/ + [73] = {0xFDA03528U, 0x00000002U}, /* SEC_MODID[73]:PFC12*/ + [74] = {0xFDA0352CU, 0x00000002U}, /* SEC_MODID[74]:PFC13*/ + [75] = {0xFDA03530U, 0x00000002U}, /* SEC_MODID[75]:PFC20*/ + [76] = {0xFDA03534U, 0x00000002U}, /* SEC_MODID[76]:PFC21*/ + [77] = {0xFDA03538U, 0x00000002U}, /* SEC_MODID[77]:PFC22*/ + [78] = {0xFDA0353CU, 0x00000002U}, /* SEC_MODID[78]:PFC23*/ + [79] = {0xFDA03550U, 0x00000002U}, /* SEC_MODID[79]:PFCS0*/ + [80] = {0xFDA03554U, 0x00000002U}, /* SEC_MODID[80]:PFCS1*/ + [81] = {0xFDA03558U, 0x00000002U}, /* SEC_MODID[81]:PFCS2*/ + [82] = {0xFDA0355CU, 0x00000002U}, /* SEC_MODID[82]:PFCS3*/ + [83] = {0xFDA03560U, 0x00000002U}, /* SEC_MODID[83]:RESET0*/ + [84] = {0xFDA03564U, 0x00000002U}, /* SEC_MODID[84]:RESET1*/ + [85] = {0xFDA03568U, 0x00000002U}, /* SEC_MODID[85]:RESET2*/ + [86] = {0xFDA0356CU, 0x00000002U}, /* SEC_MODID[86]:RESET3*/ + [87] = {0xFDA03570U, 0x00000002U}, /* SEC_MODID[87]:SYS0*/ + [88] = {0xFDA03574U, 0x00000002U}, /* SEC_MODID[88]:SYS1*/ + [89] = {0xFDA03578U, 0x00000002U}, /* SEC_MODID[89]:SYS2*/ + [90] = {0xFDA0357CU, 0x00000002U}, /* SEC_MODID[90]:SYS3*/ + [91] = {0xFCB63400U, 0x00000002U}, /* SEC_MODID[91]:DMAMSI0*/ + [92] = {0xFCB63404U, 0x00000002U}, /* SEC_MODID[92]:DMAMSI1*/ + [93] = {0xFCB63408U, 0x00000002U}, /* SEC_MODID[93]:DMAMSI2*/ + [94] = {0xFCB6340CU, 0x00000002U}, /* SEC_MODID[94]:DMAMSI3*/ + [95] = {0xFCB63410U, 0x00000002U}, /* SEC_MODID[95]:DMAMSI4*/ + [96] = {0xFCB63414U, 0x00000002U}, /* SEC_MODID[96]:DMAMSI5*/ + [97] = {0xFCB63418U, 0x00000002U}, /* SEC_MODID[97]:ECMSP3*/ + [98] = {0xFCB63424U, 0x00000002U}, /* SEC_MODID[98]:ARSP30*/ + [99] = {0xFCB63428U, 0x00000002U}, /* SEC_MODID[99]:ARSP31*/ + [100] = {0xFCB6342CU, 0x00000002U}, /* SEC_MODID[100]:ARSP32*/ + [101] = {0xFCB63430U, 0x00000002U}, /* SEC_MODID[101]:ARSP33*/ + [102] = {0xFCB63434U, 0x00000002U}, /* SEC_MODID[102]:ARSP34*/ + [103] = {0xFCB63438U, 0x00000002U}, /* SEC_MODID[103]:ARSP35*/ + [104] = {0xFCB6343CU, 0x00000002U}, /* SEC_MODID[104]:ARSP36*/ + [105] = {0xFCB63440U, 0x00000002U}, /* SEC_MODID[105]:ARSP37*/ + [106] = {0xFCB63444U, 0x00000002U}, /* SEC_MODID[106]:ARSP38*/ + [107] = {0xFCB63448U, 0x00000002U}, /* SEC_MODID[107]:MSI0*/ + [108] = {0xFCB6344CU, 0x00000002U}, /* SEC_MODID[108]:MSI1*/ + [109] = {0xFCB63450U, 0x00000002U}, /* SEC_MODID[109]:MSI2*/ + [110] = {0xFCB63454U, 0x00000002U}, /* SEC_MODID[110]:MSI3*/ + [111] = {0xFCB63458U, 0x00000002U}, /* SEC_MODID[111]:MSI4*/ + [112] = {0xFCB6345CU, 0x00000002U}, /* SEC_MODID[112]:MSI5*/ + [113] = {0xFCB93400U, 0x00000002U}, /* SEC_MODID[113]:ARSP40*/ + [114] = {0xFCB93404U, 0x00000002U}, /* SEC_MODID[114]:ARSP41*/ + [115] = {0xFCB93408U, 0x00000002U}, /* SEC_MODID[115]:ARSP42*/ + [116] = {0xFCB9340CU, 0x00000002U}, /* SEC_MODID[116]:ARSP43*/ + [117] = {0xFCB93410U, 0x00000002U}, /* SEC_MODID[117]:ARSP44*/ + [118] = {0xFCB93414U, 0x00000002U}, /* SEC_MODID[118]:ARSP45*/ + [119] = {0xFCB93418U, 0x00000002U}, /* SEC_MODID[119]:ARSP46*/ + [120] = {0xFCB9341CU, 0x00000002U}, /* SEC_MODID[120]:ARSP47*/ + [121] = {0xFCB93420U, 0x00000002U}, /* SEC_MODID[121]:ARSP48*/ + [122] = {0xFCB93424U, 0x00000002U}, /* SEC_MODID[122]:DMAHSCIF0*/ + [123] = {0xFCB93428U, 0x00000002U}, /* SEC_MODID[123]:DMAHSCIF1*/ + [124] = {0xFCB9342CU, 0x00000002U}, /* SEC_MODID[124]:DMAHSCIF2*/ + [125] = {0xFCB93430U, 0x00000002U}, /* SEC_MODID[125]:DMAHSCIF3*/ + [126] = {0xFCB93434U, 0x00000002U}, /* SEC_MODID[126]:DMASCIF0*/ + [127] = {0xFCB93438U, 0x00000002U}, /* SEC_MODID[127]:DMASCIF1*/ + [128] = {0xFCB9343CU, 0x00000002U}, /* SEC_MODID[128]:DMASCIF3*/ + [129] = {0xFCB93440U, 0x00000002U}, /* SEC_MODID[129]:DMASCIF4*/ + [130] = {0xFCB93444U, 0x00000002U}, /* SEC_MODID[130]:ECMSP4*/ + [131] = {0xFCB93448U, 0x00000002U}, /* SEC_MODID[131]:HSCIF0*/ + [132] = {0xFCB9344CU, 0x00000002U}, /* SEC_MODID[132]:HSCIF1*/ + [133] = {0xFCB93450U, 0x00000002U}, /* SEC_MODID[133]:HSCIF2*/ + [134] = {0xFCB93454U, 0x00000002U}, /* SEC_MODID[134]:HSCIF3*/ + [135] = {0xFCB93458U, 0x00000002U}, /* SEC_MODID[135]:SCIF0*/ + [136] = {0xFCB9345CU, 0x00000002U}, /* SEC_MODID[136]:SCIF1*/ + [137] = {0xFCB93460U, 0x00000002U}, /* SEC_MODID[137]:SCIF3*/ + [138] = {0xFCB93464U, 0x00000002U}, /* SEC_MODID[138]:SCIF4*/ + [139] = {0xFCB93468U, 0x00000002U}, /* SEC_MODID[139]:TMU1*/ + [140] = {0xFCB9346CU, 0x00000002U}, /* SEC_MODID[140]:TMU2*/ + [141] = {0xFCB93470U, 0x00000002U}, /* SEC_MODID[141]:TMU3*/ + [142] = {0xFCB93474U, 0x00000002U}, /* SEC_MODID[142]:TMU4*/ + [143] = {0xFCB93478U, 0x00000002U}, /* SEC_MODID[143]:CANFD*/ + [144] = {0xFCB9347CU, 0x00000002U}, /* SEC_MODID[144]:DMACANFD*/ + [145] = {0xFCB93480U, 0x00000002U}, /* SEC_MODID[145]:DMATPU0*/ + [146] = {0xFCB93484U, 0x00000002U}, /* SEC_MODID[146]:PWM0*/ + [147] = {0xFCB93488U, 0x00000002U}, /* SEC_MODID[147]:PWM1*/ + [148] = {0xFCB9348CU, 0x00000002U}, /* SEC_MODID[148]:PWM2*/ + [149] = {0xFCB93490U, 0x00000002U}, /* SEC_MODID[149]:PWM3*/ + [150] = {0xFCB93494U, 0x00000002U}, /* SEC_MODID[150]:PWM4*/ + [151] = {0xFCB934ACU, 0x00000002U}, /* SEC_MODID[151]:TPU0*/ + [152] = {0xFEBD3400U, 0x00000002U}, /* SEC_MODID[152]:ARVI40*/ + [153] = {0xFEBD3404U, 0x00000002U}, /* SEC_MODID[153]:ARVI41*/ + [154] = {0xFEBD3408U, 0x00000002U}, /* SEC_MODID[154]:ARVI42*/ + [155] = {0xFEBD340CU, 0x00000002U}, /* SEC_MODID[155]:ARVI43*/ + [156] = {0xFEBD3410U, 0x00000002U}, /* SEC_MODID[156]:ARVI44*/ + [157] = {0xFEBD3414U, 0x00000002U}, /* SEC_MODID[157]:ARVI45*/ + [158] = {0xFEBD3418U, 0x00000002U}, /* SEC_MODID[158]:ARVI46*/ + [159] = {0xFEBD341CU, 0x00000002U}, /* SEC_MODID[159]:ARVI47*/ + [160] = {0xFEBD3420U, 0x00000002U}, /* SEC_MODID[160]:ARVI48*/ + [161] = {0xFEBD3424U, 0x00000002U}, /* SEC_MODID[161]:DIS0*/ + [162] = {0xFEBD3430U, 0x00000002U}, /* SEC_MODID[162]:ECMVIO2*/ + [163] = {0xFEBD3434U, 0x00000002U}, /* SEC_MODID[163]:FCPVD0*/ + [164] = {0xFEBD343CU, 0x00000002U}, /* SEC_MODID[164]:VSPD0*/ + [165] = {0xFCF83400U, 0x00000002U}, /* SEC_MODID[165]:CKMHSC*/ + [166] = {0xFCF83404U, 0x00000002U}, /* SEC_MODID[166]:AXIPCI001*/ + [167] = {0xFCF83408U, 0x00000002U}, /* SEC_MODID[167]:AXIPCI002*/ + [168] = {0xFCF8340CU, 0x00000002U}, /* SEC_MODID[168]:AXIPCI003*/ + [169] = {0xFCF83414U, 0x00000002U}, /* SEC_MODID[169]:AXIPCI005*/ + [170] = {0xFCF83418U, 0x00000002U}, /* SEC_MODID[170]:AXIPCI006*/ + [171] = {0xFCF8341CU, 0x00000002U}, /* SEC_MODID[171]:AXIPCI007*/ + [172] = {0xFCF83420U, 0x00000002U}, /* SEC_MODID[172]:AXIPCI008*/ + [173] = {0xFCF83424U, 0x00000002U}, /* SEC_MODID[173]:AXIPCI009*/ + [174] = {0xFCF83428U, 0x00000002U}, /* SEC_MODID[174]:AXIPCI010*/ + [175] = {0xFCF8342CU, 0x00000002U}, /* SEC_MODID[175]:AXIPCI011*/ + [176] = {0xFCF83430U, 0x00000002U}, /* SEC_MODID[176]:AXIPCI012*/ + [177] = {0xFCF83434U, 0x00000002U}, /* SEC_MODID[177]:AXIPCI013*/ + [178] = {0xFCF83438U, 0x00000002U}, /* SEC_MODID[178]:AXIPCI014*/ + [179] = {0xFCF8343CU, 0x00000002U}, /* SEC_MODID[179]:AXIPCI015*/ + [180] = {0xFCF83484U, 0x00000002U}, /* SEC_MODID[180]:GPTP*/ + [181] = {0xFCF83488U, 0x00000002U}, /* SEC_MODID[181]:IPMMUHC00*/ + [182] = {0xFCF834F4U, 0x00000002U}, /* SEC_MODID[182]:AXIPCI000*/ + [183] = {0xFCF834F8U, 0x00000002U}, /* SEC_MODID[183]:AXIPCI004*/ + [184] = {0xFCF834FCU, 0x00000002U}, /* SEC_MODID[184]:IPMMUHC01*/ + [185] = {0xFCF83500U, 0x00000002U}, /* SEC_MODID[185]:AVB0*/ + [186] = {0xFCF83504U, 0x00000002U}, /* SEC_MODID[186]:AVB1*/ + [187] = {0xFCF83508U, 0x00000002U}, /* SEC_MODID[187]:AVB2*/ + [188] = {0xFCF8350CU, 0x00000002U}, /* SEC_MODID[188]:IPMMUHC10*/ + [189] = {0xFCF83510U, 0x00000002U}, /* SEC_MODID[189]:IPMMUHC11*/ + [190] = {0xFCF83514U, 0x00000002U}, /* SEC_MODID[190]:IPMMUHC12*/ + [191] = {0xFCF83518U, 0x00000002U}, /* SEC_MODID[191]:IPMMUHC13*/ + [192] = {0xFCF8351CU, 0x00000002U}, /* SEC_MODID[192]:PPHY0*/ + [193] = {0xFCF83524U, 0x00000002U}, /* SEC_MODID[193]:IPMMUHC14*/ + [194] = {0xFCF83528U, 0x00000002U}, /* SEC_MODID[194]:IPMMUHC15*/ + [195] = {0xFCF8352CU, 0x00000002U}, /* SEC_MODID[195]:FBAHSC*/ + [196] = {0xFCF83530U, 0x00000002U}, /* SEC_MODID[196]:IPMMUHC02*/ + [197] = {0xFCF83538U, 0x00000002U}, /* SEC_MODID[197]:ECMHSC*/ + [198] = {0xFCF8353CU, 0x00000002U}, /* SEC_MODID[198]:ARHC0*/ + [199] = {0xFCF83540U, 0x00000002U}, /* SEC_MODID[199]:ARHC1*/ + [200] = {0xFCF83544U, 0x00000002U}, /* SEC_MODID[200]:ARHC2*/ + [201] = {0xFCF83548U, 0x00000002U}, /* SEC_MODID[201]:ARHC3*/ + [202] = {0xFCF8354CU, 0x00000002U}, /* SEC_MODID[202]:ARHC4*/ + [203] = {0xFCF83550U, 0x00000002U}, /* SEC_MODID[203]:ARHC5*/ + [204] = {0xFCF83554U, 0x00000002U}, /* SEC_MODID[204]:ARHC6*/ + [205] = {0xFCF83558U, 0x00000002U}, /* SEC_MODID[205]:ARHC7*/ + [206] = {0xFCF8355CU, 0x00000002U}, /* SEC_MODID[206]:ARHC8*/ + [207] = {0xFCF83560U, 0x00000002U}, /* SEC_MODID[207]:IPMMUHC03*/ + [208] = {0xFCF83564U, 0x00000002U}, /* SEC_MODID[208]:IPMMUHC04*/ + [209] = {0xFCF83568U, 0x00000002U}, /* SEC_MODID[209]:IPMMUHC05*/ + [210] = {0xFCF8356CU, 0x00000002U}, /* SEC_MODID[210]:IPMMUHC06*/ + [211] = {0xFCF83570U, 0x00000002U}, /* SEC_MODID[211]:IPMMUHC07*/ + [212] = {0xFCF83574U, 0x00000002U}, /* SEC_MODID[212]:IPMMUHC08*/ + [213] = {0xFCF83578U, 0x00000002U}, /* SEC_MODID[213]:IPMMUHC09*/ + [214] = {0xFC883400U, 0x00000002U}, /* SEC_MODID[214]:ARIMP00*/ + [215] = {0xFC883404U, 0x00000002U}, /* SEC_MODID[215]:ARIMP01*/ + [216] = {0xFC883408U, 0x00000002U}, /* SEC_MODID[216]:ARIMP02*/ + [217] = {0xFC88340CU, 0x00000002U}, /* SEC_MODID[217]:ARIMP03*/ + [218] = {0xFC883410U, 0x00000002U}, /* SEC_MODID[218]:ARIMP04*/ + [219] = {0xFC883414U, 0x00000002U}, /* SEC_MODID[219]:AXIFBABUSIR0*/ + [220] = {0xFC883418U, 0x00000002U}, /* SEC_MODID[220]:AXIFBABUSIR1*/ + [221] = {0xFC88341CU, 0x00000002U}, /* SEC_MODID[221]:AXIFBABUSIR2*/ + [222] = {0xFC883420U, 0x00000002U}, /* SEC_MODID[222]:AXIFBABUSIR3*/ + [223] = {0xFC883428U, 0x00000002U}, /* SEC_MODID[223]:AXIIMP0*/ + [224] = {0xFC883434U, 0x00000002U}, /* SEC_MODID[224]:ARIMP05*/ + [225] = {0xFC883438U, 0x00000002U}, /* SEC_MODID[225]:ARIMP06*/ + [226] = {0xFC88343CU, 0x00000002U}, /* SEC_MODID[226]:ARIMP07*/ + [227] = {0xFC883440U, 0x00000002U}, /* SEC_MODID[227]:ARIMP08*/ + [228] = {0xFC883448U, 0x00000002U}, /* SEC_MODID[228]:ECMIR*/ + [229] = {0xFC88344CU, 0x00000002U}, /* SEC_MODID[229]:DSPPS*/ + [230] = {0xFC883450U, 0x00000002U}, /* SEC_MODID[230]:IPMMUIR1*/ + [231] = {0xFC883454U, 0x00000002U}, /* SEC_MODID[231]:IPMMUIR0*/ + [232] = {0xFC883458U, 0x00000002U}, /* SEC_MODID[232]:IPMMUIR10*/ + [233] = {0xFC88345CU, 0x00000002U}, /* SEC_MODID[233]:IPMMUIR11*/ + [234] = {0xFC883460U, 0x00000002U}, /* SEC_MODID[234]:IPMMUIR12*/ + [235] = {0xFC883464U, 0x00000002U}, /* SEC_MODID[235]:IPMMUIR13*/ + [236] = {0xFC883468U, 0x00000002U}, /* SEC_MODID[236]:IPMMUIR14*/ + [237] = {0xFC88346CU, 0x00000002U}, /* SEC_MODID[237]:IPMMUIR15*/ + [238] = {0xFC883470U, 0x00000002U}, /* SEC_MODID[238]:IPMMUIR2*/ + [239] = {0xFC883474U, 0x00000002U}, /* SEC_MODID[239]:IPMMUIR3*/ + [240] = {0xFC883478U, 0x00000002U}, /* SEC_MODID[240]:IPMMUIR4*/ + [241] = {0xFC88347CU, 0x00000002U}, /* SEC_MODID[241]:IPMMUIR5*/ + [242] = {0xFC883480U, 0x00000002U}, /* SEC_MODID[242]:IPMMUIR6*/ + [243] = {0xFC883484U, 0x00000002U}, /* SEC_MODID[243]:IPMMUIR7*/ + [244] = {0xFC883488U, 0x00000002U}, /* SEC_MODID[244]:IPMMUIR8*/ + [245] = {0xFC88348CU, 0x00000002U}, /* SEC_MODID[245]:IPMMUIR9*/ + [246] = {0xFC013400U, 0x00000002U}, /* SEC_MODID[246]:ARPV0*/ + [247] = {0xFC013404U, 0x00000002U}, /* SEC_MODID[247]:ARPV1*/ + [248] = {0xFC013408U, 0x00000002U}, /* SEC_MODID[248]:AXIRGXS*/ + [249] = {0xFC01340CU, 0x00000002U}, /* SEC_MODID[249]:ARPV2*/ + [250] = {0xFC013410U, 0x00000002U}, /* SEC_MODID[250]:ARPV3*/ + [251] = {0xFC013414U, 0x00000002U}, /* SEC_MODID[251]:ARPV4*/ + [252] = {0xFC013418U, 0x00000002U}, /* SEC_MODID[252]:ARPV5*/ + [253] = {0xFC01341CU, 0x00000002U}, /* SEC_MODID[253]:ARPV6*/ + [254] = {0xFC013420U, 0x00000002U}, /* SEC_MODID[254]:ARPV7*/ + [255] = {0xFC013424U, 0x00000002U}, /* SEC_MODID[255]:ARPV8*/ + [256] = {0xFC01342CU, 0x00000002U}, /* SEC_MODID[256]:ECM3DG*/ + [257] = {0xFC013430U, 0x00000002U}, /* SEC_MODID[257]:FBAPVC*/ + [258] = {0xFC013434U, 0x00000002U}, /* SEC_MODID[258]:FBAPVD0*/ + [259] = {0xFC013438U, 0x00000002U}, /* SEC_MODID[259]:FBAPVD1*/ + [260] = {0xFC01343CU, 0x00000002U}, /* SEC_MODID[260]:FBAPVD2*/ + [261] = {0xFC013440U, 0x00000002U}, /* SEC_MODID[261]:FBAPVE*/ + [262] = {0xFC013444U, 0x00000002U}, /* SEC_MODID[262]:IPMMUPV000*/ + [263] = {0xFC013448U, 0x00000002U}, /* SEC_MODID[263]:IPMMUPV001*/ + [264] = {0xFC01344CU, 0x00000002U}, /* SEC_MODID[264]:IPMMUPV010*/ + [265] = {0xFC013450U, 0x00000002U}, /* SEC_MODID[265]:IPMMUPV011*/ + [266] = {0xFC013454U, 0x00000002U}, /* SEC_MODID[266]:IPMMUPV012*/ + [267] = {0xFC013458U, 0x00000002U}, /* SEC_MODID[267]:IPMMUPV013*/ + [268] = {0xFC01345CU, 0x00000002U}, /* SEC_MODID[268]:IPMMUPV014*/ + [269] = {0xFC013460U, 0x00000002U}, /* SEC_MODID[269]:IPMMUPV015*/ + [270] = {0xFC013464U, 0x00000002U}, /* SEC_MODID[270]:IPMMUPV002*/ + [271] = {0xFC013468U, 0x00000002U}, /* SEC_MODID[271]:IPMMUPV003*/ + [272] = {0xFC01346CU, 0x00000002U}, /* SEC_MODID[272]:IPMMUPV004*/ + [273] = {0xFC013470U, 0x00000002U}, /* SEC_MODID[273]:IPMMUPV005*/ + [274] = {0xFC013474U, 0x00000002U}, /* SEC_MODID[274]:IPMMUPV006*/ + [275] = {0xFC013478U, 0x00000002U}, /* SEC_MODID[275]:IPMMUPV007*/ + [276] = {0xFC01347CU, 0x00000002U}, /* SEC_MODID[276]:IPMMUPV008*/ + [277] = {0xFC013480U, 0x00000002U}, /* SEC_MODID[277]:IPMMUPV009*/ + [278] = {0xFDC23400U, 0x00000002U}, /* SEC_MODID[278]:ARRC0*/ + [279] = {0xFDC23404U, 0x00000002U}, /* SEC_MODID[279]:ARRC1*/ + [280] = {0xFDC23408U, 0x00000002U}, /* SEC_MODID[280]:ARRC2*/ + [281] = {0xFDC2340CU, 0x00000002U}, /* SEC_MODID[281]:ARRC3*/ + [282] = {0xFDC23410U, 0x00000002U}, /* SEC_MODID[282]:ARRC4*/ + [283] = {0xFDC23414U, 0x00000002U}, /* SEC_MODID[283]:ARRC5*/ + [284] = {0xFDC23418U, 0x00000002U}, /* SEC_MODID[284]:ARRC6*/ + [285] = {0xFDC2341CU, 0x00000002U}, /* SEC_MODID[285]:ARRC7*/ + [286] = {0xFDC23420U, 0x00000002U}, /* SEC_MODID[286]:ARRC8*/ + [287] = {0xFDC23428U, 0x00000002U}, /* SEC_MODID[287]:ICUMX*/ + [288] = {0xFDC2342CU, 0x00000002U}, /* SEC_MODID[288]:ECMRC*/ + [289] = {0xFD433400U, 0x00000002U}, /* SEC_MODID[289]:DMAWCRC0*/ + [290] = {0xFD433404U, 0x00000002U}, /* SEC_MODID[290]:DMAWCRC1*/ + [291] = {0xFD433408U, 0x00000002U}, /* SEC_MODID[291]:DMAWCRC2*/ + [292] = {0xFD43340CU, 0x00000002U}, /* SEC_MODID[292]:DMAWCRC3*/ + [293] = {0xFD443400U, 0x00000002U}, /* SEC_MODID[293]:ARMREG00*/ + [294] = {0xFD443404U, 0x00000002U}, /* SEC_MODID[294]:ARMREG01*/ + [295] = {0xFD443408U, 0x00000002U}, /* SEC_MODID[295]:ARMREG10*/ + [296] = {0xFD44340CU, 0x00000002U}, /* SEC_MODID[296]:ARMREG11*/ + [297] = {0xFD443410U, 0x00000002U}, /* SEC_MODID[297]:ARMREG12*/ + [298] = {0xFD443414U, 0x00000000U}, /* SEC_MODID[298]:ARMREG13*/ + [299] = {0xFD443418U, 0x00000000U}, /* SEC_MODID[299]:ARMREG14*/ + [300] = {0xFD44341CU, 0x00000002U}, /* SEC_MODID[300]:AXICR52SS0*/ + [301] = {0xFD443420U, 0x00000002U}, /* SEC_MODID[301]:AXICSD0*/ + [302] = {0xFD443424U, 0x00000002U}, /* SEC_MODID[302]:AXIINTAP0*/ + [303] = {0xFD44342CU, 0x00000002U}, /* SEC_MODID[303]:AXISECROM*/ + [304] = {0xFD443430U, 0x00000002U}, /* SEC_MODID[304]:AXISYSRAM0*/ + [305] = {0xFD443434U, 0x00000002U}, /* SEC_MODID[305]:AXISYSRAM1*/ + [306] = {0xFD443438U, 0x00000002U}, /* SEC_MODID[306]:ARGREG15*/ + [307] = {0xFD44343CU, 0x00000002U}, /* SEC_MODID[307]:ARMREG2*/ + [308] = {0xFD443440U, 0x00000002U}, /* SEC_MODID[308]:ARMREG3*/ + [309] = {0xFD443444U, 0x00000002U}, /* SEC_MODID[309]:ARMREG4*/ + [310] = {0xFD443448U, 0x00000002U}, /* SEC_MODID[310]:ARMREG5*/ + [311] = {0xFD44344CU, 0x00000002U}, /* SEC_MODID[311]:ARMREG6*/ + [312] = {0xFD443450U, 0x00000002U}, /* SEC_MODID[312]:ARMREG7*/ + [313] = {0xFD443454U, 0x00000000U}, /* SEC_MODID[313]:ARMREG8*/ + [314] = {0xFD443458U, 0x00000000U}, /* SEC_MODID[314]:ARMREG9*/ + [315] = {0xFD44345CU, 0x00000002U}, /* SEC_MODID[315]:ARRD0*/ + [316] = {0xFD443460U, 0x00000002U}, /* SEC_MODID[316]:ARRD1*/ + [317] = {0xFD443464U, 0x00000002U}, /* SEC_MODID[317]:ARRD2*/ + [318] = {0xFD443468U, 0x00000002U}, /* SEC_MODID[318]:ARRD3*/ + [319] = {0xFD44346CU, 0x00000002U}, /* SEC_MODID[319]:ARRD4*/ + [320] = {0xFD443470U, 0x00000002U}, /* SEC_MODID[320]:ARRD5*/ + [321] = {0xFD443474U, 0x00000002U}, /* SEC_MODID[321]:ARRD6*/ + [322] = {0xFD443478U, 0x00000002U}, /* SEC_MODID[322]:ARRD7*/ + [323] = {0xFD44347CU, 0x00000002U}, /* SEC_MODID[323]:ARRD8*/ + [324] = {0xFD443480U, 0x00000002U}, /* SEC_MODID[324]:ARRT0*/ + [325] = {0xFD443484U, 0x00000002U}, /* SEC_MODID[325]:ARRT1*/ + [326] = {0xFD443488U, 0x00000002U}, /* SEC_MODID[326]:ARRT2*/ + [327] = {0xFD44348CU, 0x00000002U}, /* SEC_MODID[327]:ARRT3*/ + [328] = {0xFD443490U, 0x00000002U}, /* SEC_MODID[328]:ARRT4*/ + [329] = {0xFD443494U, 0x00000002U}, /* SEC_MODID[329]:ARRT5*/ + [330] = {0xFD443498U, 0x00000002U}, /* SEC_MODID[330]:ARRT6*/ + [331] = {0xFD44349CU, 0x00000002U}, /* SEC_MODID[331]:ARRT7*/ + [332] = {0xFD4434A0U, 0x00000002U}, /* SEC_MODID[332]:ARRT8*/ + [333] = {0xFD4434A4U, 0x00000002U}, /* SEC_MODID[333]:CKMRT*/ + [334] = {0xFD4434A8U, 0x00000002U}, /* SEC_MODID[334]:CRC0*/ + [335] = {0xFD4434ACU, 0x00000002U}, /* SEC_MODID[335]:CRC1*/ + [336] = {0xFD4434B0U, 0x00000002U}, /* SEC_MODID[336]:CRC2*/ + [337] = {0xFD4434B4U, 0x00000002U}, /* SEC_MODID[337]:CRC3*/ + [338] = {0xFD4434B8U, 0x00000002U}, /* SEC_MODID[338]:CSD*/ + [339] = {0xFD4434BCU, 0x00000002U}, /* SEC_MODID[339]:ECM*/ + [340] = {0xFD4434C0U, 0x00000002U}, /* SEC_MODID[340]:ECMRT*/ + [341] = {0xFD4434C4U, 0x00000002U}, /* SEC_MODID[341]:FBACR52*/ + [342] = {0xFD4434C8U, 0x00000002U}, /* SEC_MODID[342]:FBART*/ + [343] = {0xFD4434CCU, 0x00000002U}, /* SEC_MODID[343]:INTTP*/ + [344] = {0xFD4434D0U, 0x00000002U}, /* SEC_MODID[344]:IPMMURT000*/ + [345] = {0xFD4434D4U, 0x00000002U}, /* SEC_MODID[345]:IPMMURT100*/ + [346] = {0xFD4434D8U, 0x00000002U}, /* SEC_MODID[346]:KCRC4*/ + [347] = {0xFD4434DCU, 0x00000002U}, /* SEC_MODID[347]:KCRC5*/ + [348] = {0xFD4434E0U, 0x00000002U}, /* SEC_MODID[348]:KCRC6*/ + [349] = {0xFD4434E4U, 0x00000002U}, /* SEC_MODID[349]:KCRC7*/ + [350] = {0xFD4434E8U, 0x00000002U}, /* SEC_MODID[350]:MFI00*/ + [351] = {0xFD4434ECU, 0x00000002U}, /* SEC_MODID[351]:MFI01*/ + [352] = {0xFD4434F0U, 0x00000002U}, /* SEC_MODID[352]:MFI10*/ + [353] = {0xFD4434F4U, 0x00000002U}, /* SEC_MODID[353]:MFI02*/ + [354] = {0xFD4434F8U, 0x00000002U}, /* SEC_MODID[354]:MFI03*/ + [355] = {0xFD4434FCU, 0x00000002U}, /* SEC_MODID[355]:MFI04*/ + [356] = {0xFD443500U, 0x00000002U}, /* SEC_MODID[356]:MFI05*/ + [357] = {0xFD443504U, 0x00000002U}, /* SEC_MODID[357]:MFI06*/ + [358] = {0xFD443508U, 0x00000002U}, /* SEC_MODID[358]:MFI07*/ + [359] = {0xFD44350CU, 0x00000002U}, /* SEC_MODID[359]:MFI08*/ + [360] = {0xFD443510U, 0x00000002U}, /* SEC_MODID[360]:MFI09*/ + [361] = {0xFD443514U, 0x00000002U}, /* SEC_MODID[361]:MFI15*/ + [362] = {0xFD443518U, 0x00000002U}, /* SEC_MODID[362]:CKMCR52*/ + [363] = {0xFD44351CU, 0x00000002U}, /* SEC_MODID[363]:RTDM0P*/ + [364] = {0xFD443520U, 0x00000002U}, /* SEC_MODID[364]:ECMRD*/ + [365] = {0xFD443524U, 0x00000002U}, /* SEC_MODID[365]:RTDM1P*/ + [366] = {0xFD443530U, 0x00000002U}, /* SEC_MODID[366]:SYSRAM10*/ + [367] = {0xFD443538U, 0x00000000U}, /* SEC_MODID[367]:SYSRAM00*/ + [368] = {0xFD44353CU, 0x00000002U}, /* SEC_MODID[368]:TSIPL0*/ + [369] = {0xFD443540U, 0x00000002U}, /* SEC_MODID[369]:TSIPL1*/ + [370] = {0xFD443544U, 0x00000002U}, /* SEC_MODID[370]:TSIPL2*/ + [371] = {0xFD443548U, 0x00000002U}, /* SEC_MODID[371]:TSIPL3*/ + [372] = {0xFD44354CU, 0x00000002U}, /* SEC_MODID[372]:TSIPL4*/ + [373] = {0xFD443550U, 0x00000002U}, /* SEC_MODID[373]:TSIPL5*/ + [374] = {0xFD443554U, 0x00000002U}, /* SEC_MODID[374]:TSIPL6*/ + [375] = {0xFD443558U, 0x00000002U}, /* SEC_MODID[375]:TSIPL7*/ + [376] = {0xFD44355CU, 0x00000002U}, /* SEC_MODID[376]:WCRC0*/ + [377] = {0xFD443560U, 0x00000002U}, /* SEC_MODID[377]:WCRC1*/ + [378] = {0xFD443564U, 0x00000002U}, /* SEC_MODID[378]:WCRC2*/ + [379] = {0xFD443568U, 0x00000002U}, /* SEC_MODID[379]:WCRC3*/ + [380] = {0xFD443580U, 0x00000002U}, /* SEC_MODID[380]:MFI11*/ + [381] = {0xFD443584U, 0x00000002U}, /* SEC_MODID[381]:MFI12*/ + [382] = {0xFD443588U, 0x00000002U}, /* SEC_MODID[382]:MFI13*/ + [383] = {0xFD44358CU, 0x00000002U}, /* SEC_MODID[383]:MFI14*/ + [384] = {0xFD443590U, 0x00000002U}, /* SEC_MODID[384]:IPMMURT001*/ + [385] = {0xFD443594U, 0x00000002U}, /* SEC_MODID[385]:IPMMURT010*/ + [386] = {0xFD443598U, 0x00000002U}, /* SEC_MODID[386]:IPMMURT011*/ + [387] = {0xFD44359CU, 0x00000002U}, /* SEC_MODID[387]:IPMMURT012*/ + [388] = {0xFD4435A0U, 0x00000002U}, /* SEC_MODID[388]:IPMMURT013*/ + [389] = {0xFD4435A4U, 0x00000002U}, /* SEC_MODID[389]:IPMMURT014*/ + [390] = {0xFD4435A8U, 0x00000002U}, /* SEC_MODID[390]:IPMMURT015*/ + [391] = {0xFD4435ACU, 0x00000002U}, /* SEC_MODID[391]:IPMMURT002*/ + [392] = {0xFD4435B0U, 0x00000002U}, /* SEC_MODID[392]:IPMMURT003*/ + [393] = {0xFD4435B4U, 0x00000002U}, /* SEC_MODID[393]:IPMMURT004*/ + [394] = {0xFD4435B8U, 0x00000002U}, /* SEC_MODID[394]:IPMMURT005*/ + [395] = {0xFD4435BCU, 0x00000002U}, /* SEC_MODID[395]:IPMMURT006*/ + [396] = {0xFD4435C0U, 0x00000002U}, /* SEC_MODID[396]:IPMMURT007*/ + [397] = {0xFD4435C4U, 0x00000002U}, /* SEC_MODID[397]:IPMMURT008*/ + [398] = {0xFD4435C8U, 0x00000002U}, /* SEC_MODID[398]:IPMMURT009*/ + [399] = {0xFD4435CCU, 0x00000002U}, /* SEC_MODID[399]:IPKMURT101*/ + [400] = {0xFD4435D0U, 0x00000002U}, /* SEC_MODID[400]:IPMMURT110*/ + [401] = {0xFD4435D4U, 0x00000002U}, /* SEC_MODID[401]:IPMMURT111*/ + [402] = {0xFD4435D8U, 0x00000002U}, /* SEC_MODID[402]:IPMMURT112*/ + [403] = {0xFD4435DCU, 0x00000002U}, /* SEC_MODID[403]:IPMMURT113*/ + [404] = {0xFD4435E0U, 0x00000002U}, /* SEC_MODID[404]:IPMMURT114*/ + [405] = {0xFD4435E4U, 0x00000002U}, /* SEC_MODID[405]:IPMMURT115*/ + [406] = {0xFD4435E8U, 0x00000002U}, /* SEC_MODID[406]:IPMMURT102*/ + [407] = {0xFD4435ECU, 0x00000002U}, /* SEC_MODID[407]:IPMMURT103*/ + [408] = {0xFD4435F0U, 0x00000002U}, /* SEC_MODID[408]:IPMMURT104*/ + [409] = {0xFD4435F4U, 0x00000002U}, /* SEC_MODID[409]:IPMMURT105*/ + [410] = {0xFD4435F8U, 0x00000002U}, /* SEC_MODID[410]:IPMMURT106*/ + [411] = {0xFD4435FCU, 0x00000002U}, /* SEC_MODID[411]:IPMMURT107*/ + [412] = {0xFD443600U, 0x00000002U}, /* SEC_MODID[412]:RTDM000*/ + [413] = {0xFD443604U, 0x00000002U}, /* SEC_MODID[413]:RTDM001*/ + [414] = {0xFD443608U, 0x00000002U}, /* SEC_MODID[414]:RTDM010*/ + [415] = {0xFD44360CU, 0x00000002U}, /* SEC_MODID[415]:RTDM011*/ + [416] = {0xFD443610U, 0x00000002U}, /* SEC_MODID[416]:RTDM012*/ + [417] = {0xFD443614U, 0x00000002U}, /* SEC_MODID[417]:RTDM013*/ + [418] = {0xFD443618U, 0x00000002U}, /* SEC_MODID[418]:RTDM014*/ + [419] = {0xFD44361CU, 0x00000002U}, /* SEC_MODID[419]:RTDM015*/ + [420] = {0xFD443620U, 0x00000002U}, /* SEC_MODID[420]:RTDM002*/ + [421] = {0xFD443624U, 0x00000002U}, /* SEC_MODID[421]:RTDM003*/ + [422] = {0xFD443628U, 0x00000002U}, /* SEC_MODID[422]:RTDM004*/ + [423] = {0xFD44362CU, 0x00000002U}, /* SEC_MODID[423]:RTDM005*/ + [424] = {0xFD443630U, 0x00000002U}, /* SEC_MODID[424]:RTDM006*/ + [425] = {0xFD443634U, 0x00000002U}, /* SEC_MODID[425]:RTDM007*/ + [426] = {0xFD443638U, 0x00000002U}, /* SEC_MODID[426]:RTDM008*/ + [427] = {0xFD44363CU, 0x00000002U}, /* SEC_MODID[427]:RTDM009*/ + [428] = {0xFD443640U, 0x00000002U}, /* SEC_MODID[428]:RTDM100*/ + [429] = {0xFD443644U, 0x00000002U}, /* SEC_MODID[429]:RTDM101*/ + [430] = {0xFD443648U, 0x00000002U}, /* SEC_MODID[430]:RTDM110*/ + [431] = {0xFD44364CU, 0x00000002U}, /* SEC_MODID[431]:RTDM111*/ + [432] = {0xFD443650U, 0x00000002U}, /* SEC_MODID[432]:RTDM112*/ + [433] = {0xFD443654U, 0x00000002U}, /* SEC_MODID[433]:RTDM113*/ + [434] = {0xFD443658U, 0x00000002U}, /* SEC_MODID[434]:RTDM114*/ + [435] = {0xFD44365CU, 0x00000002U}, /* SEC_MODID[435]:RTDM115*/ + [436] = {0xFD443660U, 0x00000002U}, /* SEC_MODID[436]:RTDM102*/ + [437] = {0xFD443664U, 0x00000002U}, /* SEC_MODID[437]:RTDM103*/ + [438] = {0xFD443668U, 0x00000002U}, /* SEC_MODID[438]:RTDM104*/ + [439] = {0xFD44366CU, 0x00000002U}, /* SEC_MODID[439]:RTDM105*/ + [440] = {0xFD443670U, 0x00000002U}, /* SEC_MODID[440]:RTDM106*/ + [441] = {0xFD443674U, 0x00000002U}, /* SEC_MODID[441]:RTDM107*/ + [442] = {0xFD443678U, 0x00000002U}, /* SEC_MODID[442]:RTDM108*/ + [443] = {0xFD44367CU, 0x00000002U}, /* SEC_MODID[443]:RTDM109*/ + [444] = {0xFD443700U, 0x00000002U}, /* SEC_MODID[444]:IPMMURT108*/ + [445] = {0xFD443704U, 0x00000002U}, /* SEC_MODID[445]:IPMMURT109*/ + [446] = {0xFD443708U, 0x00000000U}, /* SEC_MODID[446]:SYSRAM01*/ + [447] = {0xFD44370CU, 0x00000002U}, /* SEC_MODID[447]:SYSRAM02*/ + [448] = {0xFD443710U, 0x00000000U}, /* SEC_MODID[448]:SYSRAM03*/ + [449] = {0xFD443714U, 0x00000000U}, /* SEC_MODID[449]:SYSRAM04*/ + [450] = {0xFD443718U, 0x00000000U}, /* SEC_MODID[450]:SYSRAM05*/ + [451] = {0xFD44371CU, 0x00000000U}, /* SEC_MODID[451]:SYSRAM06*/ + [452] = {0xFD443720U, 0x00000002U}, /* SEC_MODID[452]:SYSRAM07*/ + [453] = {0xFD443724U, 0x00000002U}, /* SEC_MODID[453]:SYSRAM11*/ + [454] = {0xFD443728U, 0x00000002U}, /* SEC_MODID[454]:SYSRAM12*/ + [455] = {0xFD44372CU, 0x00000002U}, /* SEC_MODID[455]:SYSRAM13*/ + [456] = {0xFD443730U, 0x00000002U}, /* SEC_MODID[456]:SYSRAM14*/ + [457] = {0xFD443734U, 0x00000002U}, /* SEC_MODID[457]:SYSRAM15*/ + [458] = {0xFD443738U, 0x00000002U}, /* SEC_MODID[458]:SYSRAM16*/ + [459] = {0xFD44373CU, 0x00000002U}, /* SEC_MODID[459]:SYSRAM17*/ + [460] = {0xFD443760U, 0x00000002U}, /* SEC_MODID[460]:BKBUF*/ + [461] = {0xFD443764U, 0x00000002U}, /* SEC_MODID[461]:AXICR52SS1*/ + [462] = {0xFD443768U, 0x00000002U}, /* SEC_MODID[462]:AXICR52SS2*/ + [463] = {0xFC863400U, 0x00000002U}, /* SEC_MODID[463]:ARSC0*/ + [464] = {0xFC863404U, 0x00000002U}, /* SEC_MODID[464]:ARSC1*/ + [465] = {0xFC863408U, 0x00000002U}, /* SEC_MODID[465]:ARSC2*/ + [466] = {0xFC86340CU, 0x00000002U}, /* SEC_MODID[466]:ARSC3*/ + [467] = {0xFC863410U, 0x00000002U}, /* SEC_MODID[467]:ARSC4*/ + [468] = {0xFC863414U, 0x00000002U}, /* SEC_MODID[468]:ARSC5*/ + [469] = {0xFC863418U, 0x00000002U}, /* SEC_MODID[469]:ARSC6*/ + [470] = {0xFC86341CU, 0x00000002U}, /* SEC_MODID[470]:ARSC7*/ + [471] = {0xFC863420U, 0x00000002U}, /* SEC_MODID[471]:ARSC8*/ + [472] = {0xFC863424U, 0x00000002U}, /* SEC_MODID[472]:ARSTM0*/ + [473] = {0xFC863428U, 0x00000002U}, /* SEC_MODID[473]:ARSTM1*/ + [474] = {0xFC86342CU, 0x00000002U}, /* SEC_MODID[474]:CSD1S*/ + [475] = {0xFC863430U, 0x00000002U}, /* SEC_MODID[475]:AXIFBABUSTOP0*/ + [476] = {0xFC863438U, 0x00000002U}, /* SEC_MODID[476]:ARSTM2*/ + [477] = {0xFC86343CU, 0x00000002U}, /* SEC_MODID[477]:ARSTM3*/ + [478] = {0xFC863440U, 0x00000002U}, /* SEC_MODID[478]:ARSTM4*/ + [479] = {0xFC863444U, 0x00000002U}, /* SEC_MODID[479]:ARSTM5*/ + [480] = {0xFC863448U, 0x00000002U}, /* SEC_MODID[480]:ARSTM6*/ + [481] = {0xFC86344CU, 0x00000002U}, /* SEC_MODID[481]:ARSTM7*/ + [482] = {0xFC863450U, 0x00000002U}, /* SEC_MODID[482]:ARSTM8*/ + [483] = {0xFC863454U, 0x00000002U}, /* SEC_MODID[483]:ECMTOP*/ + [484] = {0xFC863458U, 0x00000002U}, /* SEC_MODID[484]:FBA*/ + [485] = {0xFC86345CU, 0x00000002U}, /* SEC_MODID[485]:FBC*/ + [486] = {0xFC863434U, 0x00000002U}, /* SEC_MODID[486]:AXICCI00*/ + [487] = {0xFC863460U, 0x00000002U}, /* SEC_MODID[487]:AXICCI01*/ + [488] = {0xFC863464U, 0x00000002U}, /* SEC_MODID[488]:AXICCI10*/ + [489] = {0xFC863468U, 0x00000002U}, /* SEC_MODID[489]:AXICCI11*/ + [490] = {0xFC86346CU, 0x00000002U}, /* SEC_MODID[490]:AXICCI12*/ + [491] = {0xFC863470U, 0x00000002U}, /* SEC_MODID[491]:AXICCI13*/ + [492] = {0xFC863474U, 0x00000002U}, /* SEC_MODID[492]:AXICCI14*/ + [493] = {0xFC863478U, 0x00000002U}, /* SEC_MODID[493]:AXICCI15*/ + [494] = {0xFC86347CU, 0x00000002U}, /* SEC_MODID[494]:AXICCI2*/ + [495] = {0xFC863480U, 0x00000002U}, /* SEC_MODID[495]:AXICCI3*/ + [496] = {0xFC863484U, 0x00000002U}, /* SEC_MODID[496]:AXICCI4*/ + [497] = {0xFC863488U, 0x00000002U}, /* SEC_MODID[497]:AXICCI5*/ + [498] = {0xFC86348CU, 0x00000002U}, /* SEC_MODID[498]:AXICCI6*/ + [499] = {0xFC863490U, 0x00000002U}, /* SEC_MODID[499]:AXICCI7*/ + [500] = {0xFC863494U, 0x00000002U}, /* SEC_MODID[500]:AXICCI8*/ + [501] = {0xFC863498U, 0x00000002U}, /* SEC_MODID[501]:AXICCI9*/ + [502] = {0xFC8634A0U, 0x00000002U}, /* SEC_MODID[502]:ECMSTM*/ + [503] = {0xFCB83400U, 0x00000002U}, /* SEC_MODID[503]:DMASSI00*/ + [504] = {0xFCB83404U, 0x00000002U}, /* SEC_MODID[504]:DMASSI01*/ + [505] = {0xFCB83408U, 0x00000002U}, /* SEC_MODID[505]:DMASSI02*/ + [506] = {0xFCB8340CU, 0x00000002U}, /* SEC_MODID[506]:DMASSI03*/ + [507] = {0xFCB83410U, 0x00000002U}, /* SEC_MODID[507]:DMASSI04*/ + [508] = {0xFCB83414U, 0x00000002U}, /* SEC_MODID[508]:DMAI2C0*/ + [509] = {0xFCB83418U, 0x00000002U}, /* SEC_MODID[509]:DMAI2C1*/ + [510] = {0xFCB8341CU, 0x00000002U}, /* SEC_MODID[510]:DMAI2C2*/ + [511] = {0xFCB83420U, 0x00000002U}, /* SEC_MODID[511]:DMAI2C3*/ + [512] = {0xFCB8342CU, 0x00000002U}, /* SEC_MODID[512]:DMASSI05*/ + [513] = {0xFCB83430U, 0x00000002U}, /* SEC_MODID[513]:DMASSI06*/ + [514] = {0xFCB83434U, 0x00000002U}, /* SEC_MODID[514]:DMASSI07*/ + [515] = {0xFDDC3400U, 0x00000002U}, /* SEC_MODID[515]:ARMM*/ + [516] = {0xFDDC3404U, 0x00000002U}, /* SEC_MODID[516]:AXIARNMM*/ + [517] = {0xFDDC3408U, 0x00000002U}, /* SEC_MODID[517]:ARSM0*/ + [518] = {0xFDDC340CU, 0x00000002U}, /* SEC_MODID[518]:ARSM1*/ + [519] = {0xFDDC3410U, 0x00000002U}, /* SEC_MODID[519]:ARSM2*/ + [520] = {0xFDDC3414U, 0x00000002U}, /* SEC_MODID[520]:AXIQOS0*/ + [521] = {0xFDDC3418U, 0x00000002U}, /* SEC_MODID[521]:AXIQOS1*/ + [522] = {0xFDDC341CU, 0x00000002U}, /* SEC_MODID[522]:AXIQOS2*/ + [523] = {0xFDDC3420U, 0x00000002U}, /* SEC_MODID[523]:AXIQOS3*/ + [524] = {0xFDDC3424U, 0x00000002U}, /* SEC_MODID[524]:AXIQOS4*/ + [525] = {0xFDDC3428U, 0x00000002U}, /* SEC_MODID[525]:AXIQOS5*/ + [526] = {0xFDDC3434U, 0x00000002U}, /* SEC_MODID[526]:ARSM3*/ + [527] = {0xFDDC3438U, 0x00000002U}, /* SEC_MODID[527]:ARSM4*/ + [528] = {0xFDDC343CU, 0x00000002U}, /* SEC_MODID[528]:ARSM5*/ + [529] = {0xFDDC3440U, 0x00000002U}, /* SEC_MODID[529]:ARSM6*/ + [530] = {0xFDDC3444U, 0x00000002U}, /* SEC_MODID[530]:ARSM7*/ + [531] = {0xFDDC3448U, 0x00000002U}, /* SEC_MODID[531]:ARSM8*/ + [532] = {0xFDDC344CU, 0x00000000U}, /* SEC_MODID[532]:AXMM0*/ + [533] = {0xFDDC3450U, 0x00000000U}, /* SEC_MODID[533]:AXMM1*/ + [534] = {0xFDDC3454U, 0x00000002U}, /* SEC_MODID[534]:AXMMPMON*/ + [535] = {0xFDDC3458U, 0x00000002U}, /* SEC_MODID[535]:CKMMM*/ + [536] = {0xFDDC345CU, 0x00000002U}, /* SEC_MODID[536]:ECMMM*/ + [537] = {0xFDDC3460U, 0x00000002U}, /* SEC_MODID[537]:FBADBSC0*/ + [538] = {0xFDDC3468U, 0x00000002U}, /* SEC_MODID[538]:FBAMM*/ + [539] = {0xFDDC346CU, 0x00000002U}, /* SEC_MODID[539]:IPMMUMM00*/ + [540] = {0xFDDC3470U, 0x00000002U}, /* SEC_MODID[540]:DBS0A0*/ + [541] = {0xFDDC3474U, 0x00000002U}, /* SEC_MODID[541]:DBS0A1*/ + [542] = {0xFDDC3484U, 0x00000002U}, /* SEC_MODID[542]:FCPRC*/ + [543] = {0xFDDC3488U, 0x00000002U}, /* SEC_MODID[543]:DBS0D0*/ + [544] = {0xFDDC348CU, 0x00000002U}, /* SEC_MODID[544]:DBS0D1*/ + [545] = {0xFDDC3498U, 0x00000002U}, /* SEC_MODID[545]:FBADDR*/ + [546] = {0xFDDC349CU, 0x00000002U}, /* SEC_MODID[546]:IPMMUMM01*/ + [547] = {0xFDDC34A0U, 0x00000002U}, /* SEC_MODID[547]:IPMMUMM10*/ + [548] = {0xFDDC34A4U, 0x00000002U}, /* SEC_MODID[548]:IPMMUMM11*/ + [549] = {0xFDDC34A8U, 0x00000002U}, /* SEC_MODID[549]:IPMMUMM12*/ + [550] = {0xFDDC34ACU, 0x00000002U}, /* SEC_MODID[550]:IPMMUMM13*/ + [551] = {0xFDDC34B0U, 0x00000002U}, /* SEC_MODID[551]:IPMMUMM14*/ + [552] = {0xFDDC34B4U, 0x00000002U}, /* SEC_MODID[552]:IPMMUMM15*/ + [553] = {0xFDDC34B8U, 0x00000002U}, /* SEC_MODID[553]:IPMMUMM02*/ + [554] = {0xFDDC34BCU, 0x00000002U}, /* SEC_MODID[554]:IPMMUMM03*/ + [555] = {0xFDDC34C0U, 0x00000002U}, /* SEC_MODID[555]:IPMMUMM04*/ + [556] = {0xFDDC34C4U, 0x00000002U}, /* SEC_MODID[556]:IPMMUMM05*/ + [557] = {0xFDDC34C8U, 0x00000002U}, /* SEC_MODID[557]:IPMMUMM06*/ + [558] = {0xFDDC34CCU, 0x00000002U}, /* SEC_MODID[558]:IPMMUMM07*/ + [559] = {0xFDDC34D0U, 0x00000002U}, /* SEC_MODID[559]:IPMMUMM08*/ + [560] = {0xFDDC34D4U, 0x00000002U}, /* SEC_MODID[560]:IPMMUMM09*/ + [561] = {0xFC803400U, 0x00000002U}, /* SEC_MODID[561]:ARSN0*/ + [562] = {0xFC803404U, 0x00000002U}, /* SEC_MODID[562]:ARSN1*/ + [563] = {0xFC803408U, 0x00000002U}, /* SEC_MODID[563]:ARSN2*/ + [564] = {0xFC80340CU, 0x00000002U}, /* SEC_MODID[564]:ARSN3*/ + [565] = {0xFC803410U, 0x00000002U}, /* SEC_MODID[565]:ARSN4*/ + [566] = {0xFC803414U, 0x00000002U}, /* SEC_MODID[566]:ARSN5*/ + [567] = {0xFC803418U, 0x00000002U}, /* SEC_MODID[567]:ARSN6*/ + [568] = {0xFC80341CU, 0x00000002U}, /* SEC_MODID[568]:ARSN7*/ + [569] = {0xFC803420U, 0x00000002U}, /* SEC_MODID[569]:ARSN8*/ + [570] = {0xFC803424U, 0x00000002U}, /* SEC_MODID[570]:ECMTOP3*/ + [571] = {0xFCB53400U, 0x00000002U}, /* SEC_MODID[571]:ARSD00*/ + [572] = {0xFCB53404U, 0x00000002U}, /* SEC_MODID[572]:ARSD01*/ + [573] = {0xFCB53408U, 0x00000002U}, /* SEC_MODID[573]:ARSD02*/ + [574] = {0xFCB5340CU, 0x00000002U}, /* SEC_MODID[574]:ARSD03*/ + [575] = {0xFCB53410U, 0x00000002U}, /* SEC_MODID[575]:ARSD04*/ + [576] = {0xFCB53414U, 0x00000002U}, /* SEC_MODID[576]:ARSD05*/ + [577] = {0xFCB53418U, 0x00000002U}, /* SEC_MODID[577]:ARSD06*/ + [578] = {0xFCB5341CU, 0x00000002U}, /* SEC_MODID[578]:AXIFRAY*/ + [579] = {0xFCB53428U, 0x00000002U}, /* SEC_MODID[579]:AXIRPC*/ + [580] = {0xFCB5342CU, 0x00000002U}, /* SEC_MODID[580]:AXISDHI0*/ + [581] = {0xFCB53430U, 0x00000002U}, /* SEC_MODID[581]:ARSD07*/ + [582] = {0xFCB53434U, 0x00000002U}, /* SEC_MODID[582]:ARSD08*/ + [583] = {0xFCB53438U, 0x00000002U}, /* SEC_MODID[583]:ARSP00*/ + [584] = {0xFCB5343CU, 0x00000002U}, /* SEC_MODID[584]:ARSP01*/ + [585] = {0xFCB53440U, 0x00000002U}, /* SEC_MODID[585]:ARSP02*/ + [586] = {0xFCB53444U, 0x00000002U}, /* SEC_MODID[586]:ARSP03*/ + [587] = {0xFCB53448U, 0x00000002U}, /* SEC_MODID[587]:ARSP04*/ + [588] = {0xFCB5344CU, 0x00000002U}, /* SEC_MODID[588]:ARSP05*/ + [589] = {0xFCB53450U, 0x00000002U}, /* SEC_MODID[589]:ARSP06*/ + [590] = {0xFCB53454U, 0x00000002U}, /* SEC_MODID[590]:ARSP07*/ + [591] = {0xFCB53458U, 0x00000002U}, /* SEC_MODID[591]:ARSP08*/ + [592] = {0xFCB5345CU, 0x00000002U}, /* SEC_MODID[592]:IPMMUDS001*/ + [593] = {0xFCB53460U, 0x00000002U}, /* SEC_MODID[593]:CKMPER0*/ + [594] = {0xFCB53464U, 0x00000002U}, /* SEC_MODID[594]:ECMPER0*/ + [595] = {0xFCB53468U, 0x00000002U}, /* SEC_MODID[595]:FBAPER0*/ + [596] = {0xFCB5346CU, 0x00000002U}, /* SEC_MODID[596]:FSO0*/ + [597] = {0xFCB53470U, 0x00000002U}, /* SEC_MODID[597]:FSO1*/ + [598] = {0xFCB53474U, 0x00000002U}, /* SEC_MODID[598]:FSO10*/ + [599] = {0xFCB53478U, 0x00000002U}, /* SEC_MODID[599]:FSO2*/ + [600] = {0xFCB5347CU, 0x00000002U}, /* SEC_MODID[600]:FSO3*/ + [601] = {0xFCB53480U, 0x00000002U}, /* SEC_MODID[601]:FSO4*/ + [602] = {0xFCB53484U, 0x00000002U}, /* SEC_MODID[602]:FSO5*/ + [603] = {0xFCB53488U, 0x00000002U}, /* SEC_MODID[603]:FSO6*/ + [604] = {0xFCB5348CU, 0x00000002U}, /* SEC_MODID[604]:FSO7*/ + [605] = {0xFCB53490U, 0x00000002U}, /* SEC_MODID[605]:FSO8*/ + [606] = {0xFCB53494U, 0x00000002U}, /* SEC_MODID[606]:FSO9*/ + [607] = {0xFCB53498U, 0x00000002U}, /* SEC_MODID[607]:ADG*/ + [608] = {0xFCB5349CU, 0x00000002U}, /* SEC_MODID[608]:ECMSD0*/ + [609] = {0xFCB534A0U, 0x00000002U}, /* SEC_MODID[609]:IPMMUDS010*/ + [610] = {0xFCB534A4U, 0x00000002U}, /* SEC_MODID[610]:IPMMUDS011*/ + [611] = {0xFCB534A8U, 0x00000002U}, /* SEC_MODID[611]:I2C0*/ + [612] = {0xFCB534ACU, 0x00000002U}, /* SEC_MODID[612]:I2C1*/ + [613] = {0xFCB534B0U, 0x00000002U}, /* SEC_MODID[613]:I2C2*/ + [614] = {0xFCB534B4U, 0x00000002U}, /* SEC_MODID[614]:I2C3*/ + [615] = {0xFCB534C0U, 0x00000002U}, /* SEC_MODID[615]:IPMMUDS012*/ + [616] = {0xFCB534C8U, 0x00000002U}, /* SEC_MODID[616]:IPMMUDS000*/ + [617] = {0xFCB534CCU, 0x00000002U}, /* SEC_MODID[617]:IPMMUDS013*/ + [618] = {0xFCB534D0U, 0x00000002U}, /* SEC_MODID[618]:IPMMUDS014*/ + [619] = {0xFCB534D4U, 0x00000002U}, /* SEC_MODID[619]:IPMMUDS015*/ + [620] = {0xFCB534D8U, 0x00000002U}, /* SEC_MODID[620]:IPMMUDS002*/ + [621] = {0xFCB534DCU, 0x00000002U}, /* SEC_MODID[621]:IPMMUDS003*/ + [622] = {0xFCB534E0U, 0x00000002U}, /* SEC_MODID[622]:IPMMUDS004*/ + [623] = {0xFCB534E4U, 0x00000002U}, /* SEC_MODID[623]:IPMMUDS005*/ + [624] = {0xFCB534E8U, 0x00000002U}, /* SEC_MODID[624]:SSI*/ + [625] = {0xFCB534ECU, 0x00000002U}, /* SEC_MODID[625]:IPMMUDS006*/ + [626] = {0xFCB534F0U, 0x00000002U}, /* SEC_MODID[626]:IPMMUDS007*/ + [627] = {0xFCB534F4U, 0x00000002U}, /* SEC_MODID[627]:SYDM1P*/ + [628] = {0xFCB534F8U, 0x00000002U}, /* SEC_MODID[628]:IPMMUDS008*/ + [629] = {0xFCB534FCU, 0x00000002U}, /* SEC_MODID[629]:SYDM2P*/ + [630] = {0xFCB53500U, 0x00000002U}, /* SEC_MODID[630]:IPMMUDS009*/ + [631] = {0xFCB53640U, 0x00000002U}, /* SEC_MODID[631]:SYDM100*/ + [632] = {0xFCB53644U, 0x00000002U}, /* SEC_MODID[632]:SYDM101*/ + [633] = {0xFCB53648U, 0x00000002U}, /* SEC_MODID[633]:SYDM110*/ + [634] = {0xFCB5364CU, 0x00000002U}, /* SEC_MODID[634]:SYDM111*/ + [635] = {0xFCB53650U, 0x00000002U}, /* SEC_MODID[635]:SYDM112*/ + [636] = {0xFCB53654U, 0x00000002U}, /* SEC_MODID[636]:SYDM113*/ + [637] = {0xFCB53658U, 0x00000002U}, /* SEC_MODID[637]:SYDM114*/ + [638] = {0xFCB5365CU, 0x00000002U}, /* SEC_MODID[638]:SYDM115*/ + [639] = {0xFCB53660U, 0x00000002U}, /* SEC_MODID[639]:SYDM102*/ + [640] = {0xFCB53664U, 0x00000002U}, /* SEC_MODID[640]:SYDM103*/ + [641] = {0xFCB53668U, 0x00000002U}, /* SEC_MODID[641]:SYDM104*/ + [642] = {0xFCB5366CU, 0x00000002U}, /* SEC_MODID[642]:SYDM105*/ + [643] = {0xFCB53670U, 0x00000002U}, /* SEC_MODID[643]:SYDM106*/ + [644] = {0xFCB53674U, 0x00000002U}, /* SEC_MODID[644]:SYDM107*/ + [645] = {0xFCB53678U, 0x00000002U}, /* SEC_MODID[645]:SYDM108*/ + [646] = {0xFCB5367CU, 0x00000002U}, /* SEC_MODID[646]:SYDM109*/ + [647] = {0xFCB53680U, 0x00000002U}, /* SEC_MODID[647]:SYDM200*/ + [648] = {0xFCB53684U, 0x00000002U}, /* SEC_MODID[648]:SYDM201*/ + [649] = {0xFCB53688U, 0x00000002U}, /* SEC_MODID[649]:SYDM210*/ + [650] = {0xFCB5368CU, 0x00000002U}, /* SEC_MODID[650]:SYDM211*/ + [651] = {0xFCB53690U, 0x00000002U}, /* SEC_MODID[651]:SYDM212*/ + [652] = {0xFCB53694U, 0x00000002U}, /* SEC_MODID[652]:SYDM213*/ + [653] = {0xFCB53698U, 0x00000002U}, /* SEC_MODID[653]:SYDM214*/ + [654] = {0xFCB5369CU, 0x00000002U}, /* SEC_MODID[654]:SYDM215*/ + [655] = {0xFCB536A0U, 0x00000002U}, /* SEC_MODID[655]:SYDM202*/ + [656] = {0xFCB536A4U, 0x00000002U}, /* SEC_MODID[656]:SYDM203*/ + [657] = {0xFCB536A8U, 0x00000002U}, /* SEC_MODID[657]:SYDM204*/ + [658] = {0xFCB536ACU, 0x00000002U}, /* SEC_MODID[658]:SYDM205*/ + [659] = {0xFCB536B0U, 0x00000002U}, /* SEC_MODID[659]:SYDM206*/ + [660] = {0xFCB536B4U, 0x00000002U}, /* SEC_MODID[660]:SYDM207*/ + [661] = {0xFCB536B8U, 0x00000002U}, /* SEC_MODID[661]:SYDM208*/ + [662] = {0xFCB536BCU, 0x00000002U}, /* SEC_MODID[662]:SYDM209*/ + [663] = {0xFC683400U, 0x00000002U}, /* SEC_MODID[663]:ARVC0*/ + [664] = {0xFC683404U, 0x00000002U}, /* SEC_MODID[664]:ARVC1*/ + [665] = {0xFC683408U, 0x00000002U}, /* SEC_MODID[665]:ARVC2*/ + [666] = {0xFC68340CU, 0x00000002U}, /* SEC_MODID[666]:ARVC3*/ + [667] = {0xFC683410U, 0x00000002U}, /* SEC_MODID[667]:AXIFBABUSVC*/ + [668] = {0xFC683414U, 0x00000002U}, /* SEC_MODID[668]:ARVC4*/ + [669] = {0xFC683418U, 0x00000002U}, /* SEC_MODID[669]:ARVC5*/ + [670] = {0xFC68341CU, 0x00000002U}, /* SEC_MODID[670]:ARVC6*/ + [671] = {0xFC683420U, 0x00000002U}, /* SEC_MODID[671]:ARVC7*/ + [672] = {0xFC683424U, 0x00000002U}, /* SEC_MODID[672]:ARVC8*/ + [673] = {0xFC68342CU, 0x00000002U}, /* SEC_MODID[673]:ECMVC0*/ + [674] = {0xFC683434U, 0x00000002U}, /* SEC_MODID[674]:IMR0*/ + [675] = {0xFC683438U, 0x00000002U}, /* SEC_MODID[675]:IMR1*/ + [676] = {0xFC68343CU, 0x00000002U}, /* SEC_MODID[676]:IPMMUVC01*/ + [677] = {0xFC683440U, 0x00000002U}, /* SEC_MODID[677]:IPMMUVC10*/ + [678] = {0xFC683444U, 0x00000002U}, /* SEC_MODID[678]:IMS0*/ + [679] = {0xFC683448U, 0x00000002U}, /* SEC_MODID[679]:IMS1*/ + [680] = {0xFC68344CU, 0x00000002U}, /* SEC_MODID[680]:IPMMUVC00*/ + [681] = {0xFC683450U, 0x00000002U}, /* SEC_MODID[681]:IPMMUVC11*/ + [682] = {0xFC683454U, 0x00000002U}, /* SEC_MODID[682]:IPMMUVC12*/ + [683] = {0xFC683458U, 0x00000002U}, /* SEC_MODID[683]:IPMMUVC13*/ + [684] = {0xFC68345CU, 0x00000002U}, /* SEC_MODID[684]:IPMMUVC14*/ + [685] = {0xFC683460U, 0x00000002U}, /* SEC_MODID[685]:IPMMUVC15*/ + [686] = {0xFC683464U, 0x00000002U}, /* SEC_MODID[686]:IPMMUVC02*/ + [687] = {0xFC683468U, 0x00000002U}, /* SEC_MODID[687]:IPMMUVC03*/ + [688] = {0xFC68346CU, 0x00000002U}, /* SEC_MODID[688]:IPMMUVC04*/ + [689] = {0xFC683470U, 0x00000002U}, /* SEC_MODID[689]:IPMMUVC05*/ + [690] = {0xFC683474U, 0x00000002U}, /* SEC_MODID[690]:IPMMUVC06*/ + [691] = {0xFC683478U, 0x00000002U}, /* SEC_MODID[691]:IPMMUVC07*/ + [692] = {0xFC68347CU, 0x00000002U}, /* SEC_MODID[692]:IPMMUVC08*/ + [693] = {0xFC683480U, 0x00000002U}, /* SEC_MODID[693]:IPMMUVC09*/ + [694] = {0xFC683484U, 0x00000002U}, /* SEC_MODID[694]:IV1ES*/ + [695] = {0xFEBE3400U, 0x00000002U}, /* SEC_MODID[695]:CSITOP0*/ + [696] = {0xFEBE3404U, 0x00000002U}, /* SEC_MODID[696]:ARVI10*/ + [697] = {0xFEBE3408U, 0x00000002U}, /* SEC_MODID[697]:ARVI11*/ + [698] = {0xFEBE340CU, 0x00000002U}, /* SEC_MODID[698]:ARVI12*/ + [699] = {0xFEBE3410U, 0x00000002U}, /* SEC_MODID[699]:ARVI13*/ + [700] = {0xFEBE3414U, 0x00000002U}, /* SEC_MODID[700]:ARVI14*/ + [701] = {0xFEBE3418U, 0x00000002U}, /* SEC_MODID[701]:ARVI15*/ + [702] = {0xFEBE341CU, 0x00000002U}, /* SEC_MODID[702]:ARVI16*/ + [703] = {0xFEBE3420U, 0x00000002U}, /* SEC_MODID[703]:ARVI17*/ + [704] = {0xFEBE3424U, 0x00000002U}, /* SEC_MODID[704]:ARVI18*/ + [705] = {0xFEBE342CU, 0x00000002U}, /* SEC_MODID[705]:CSITOP1*/ + [706] = {0xFEBE3434U, 0x00000002U}, /* SEC_MODID[706]:DSITLINK0*/ + [707] = {0xFEBE343CU, 0x00000002U}, /* SEC_MODID[707]:ECMVIO1*/ + [708] = {0xFEBE3444U, 0x00000002U}, /* SEC_MODID[708]:IPMMUVI001*/ + [709] = {0xFEBE3448U, 0x00000002U}, /* SEC_MODID[709]:FCPVX0*/ + [710] = {0xFEBE3458U, 0x00000002U}, /* SEC_MODID[710]:IPMMUVI000*/ + [711] = {0xFEBE345CU, 0x00000002U}, /* SEC_MODID[711]:IPMMUVI100*/ + [712] = {0xFEBE3460U, 0x00000002U}, /* SEC_MODID[712]:IPMMUVI010*/ + [713] = {0xFEBE3464U, 0x00000002U}, /* SEC_MODID[713]:IPMMUVI011*/ + [714] = {0xFEBE3468U, 0x00000002U}, /* SEC_MODID[714]:VSPX0*/ + [715] = {0xFEBE3478U, 0x00000002U}, /* SEC_MODID[715]:IPMMUVI012*/ + [716] = {0xFEBE347CU, 0x00000002U}, /* SEC_MODID[716]:IPMMUVI013*/ + [717] = {0xFEBE3480U, 0x00000002U}, /* SEC_MODID[717]:IPMMUVI014*/ + [718] = {0xFEBE3484U, 0x00000002U}, /* SEC_MODID[718]:IPMMUVI015*/ + [719] = {0xFEBE3488U, 0x00000002U}, /* SEC_MODID[719]:IPMMUVI002*/ + [720] = {0xFEBE348CU, 0x00000002U}, /* SEC_MODID[720]:IPMMUVI003*/ + [721] = {0xFEBE3490U, 0x00000002U}, /* SEC_MODID[721]:IPMMUVI004*/ + [722] = {0xFEBE3494U, 0x00000002U}, /* SEC_MODID[722]:IPMMUVI005*/ + [723] = {0xFEBE3498U, 0x00000002U}, /* SEC_MODID[723]:IPMMUVI006*/ + [724] = {0xFEBE349CU, 0x00000002U}, /* SEC_MODID[724]:IPMMUVI007*/ + [725] = {0xFEBE34A0U, 0x00000002U}, /* SEC_MODID[725]:IPMMUVI008*/ + [726] = {0xFEBE34A4U, 0x00000002U}, /* SEC_MODID[726]:IPMMUVI009*/ + [727] = {0xFEBE34A8U, 0x00000002U}, /* SEC_MODID[727]:IPMMUVI101*/ + [728] = {0xFEBE34ACU, 0x00000002U}, /* SEC_MODID[728]:IPMMUVI110*/ + [729] = {0xFEBE34B0U, 0x00000002U}, /* SEC_MODID[729]:IPMMUVI111*/ + [730] = {0xFEBE34B4U, 0x00000002U}, /* SEC_MODID[730]:IPMMUVI112*/ + [731] = {0xFEBE34B8U, 0x00000002U}, /* SEC_MODID[731]:IPMMUVI113*/ + [732] = {0xFEBE34BCU, 0x00000002U}, /* SEC_MODID[732]:IPMMUVI114*/ + [733] = {0xFEBE34C0U, 0x00000002U}, /* SEC_MODID[733]:IPMMUVI115*/ + [734] = {0xFEBE34C4U, 0x00000002U}, /* SEC_MODID[734]:IPMMUVI102*/ + [735] = {0xFEBE34C8U, 0x00000002U}, /* SEC_MODID[735]:IPMMUVI103*/ + [736] = {0xFEBE34CCU, 0x00000002U}, /* SEC_MODID[736]:IPMMUVI104*/ + [737] = {0xFEBE34D0U, 0x00000002U}, /* SEC_MODID[737]:IPMMUVI105*/ + [738] = {0xFEBE34D4U, 0x00000002U}, /* SEC_MODID[738]:IPMMUVI106*/ + [739] = {0xFEBE34D8U, 0x00000002U}, /* SEC_MODID[739]:IPMMUVI107*/ + [740] = {0xFEBE34DCU, 0x00000002U}, /* SEC_MODID[740]:IPMMUVI108*/ + [741] = {0xFEBE34E0U, 0x00000002U}, /* SEC_MODID[741]:IPMMUVI109*/ + [742] = {0xFEBE3504U, 0x00000002U}, /* SEC_MODID[742]:AXIFBABUSVIO*/ + [743] = {0xFEBF3400U, 0x00000002U}, /* SEC_MODID[743]:ARVI0*/ + [744] = {0xFEBF3404U, 0x00000002U}, /* SEC_MODID[744]:ARVI1*/ + [745] = {0xFEBF3408U, 0x00000002U}, /* SEC_MODID[745]:ARVI2*/ + [746] = {0xFEBF340CU, 0x00000002U}, /* SEC_MODID[746]:ARVI3*/ + [747] = {0xFEBF3410U, 0x00000002U}, /* SEC_MODID[747]:ARVI4*/ + [748] = {0xFEBF3414U, 0x00000002U}, /* SEC_MODID[748]:ARVI5*/ + [749] = {0xFEBF3418U, 0x00000002U}, /* SEC_MODID[749]:ARVI6*/ + [750] = {0xFEBF341CU, 0x00000002U}, /* SEC_MODID[750]:ARVI7*/ + [751] = {0xFEBF3420U, 0x00000002U}, /* SEC_MODID[751]:ARVI8*/ + [752] = {0xFEBF3424U, 0x00000002U}, /* SEC_MODID[752]:ECMVIO0*/ + [753] = {0xFEBF3428U, 0x00000002U}, /* SEC_MODID[753]:ISP0*/ + [754] = {0xFEBF342CU, 0x00000002U}, /* SEC_MODID[754]:ISP0CORE*/ + [755] = {0xFEBF3430U, 0x00000002U}, /* SEC_MODID[755]:ISP1*/ + [756] = {0xFEBF3454U, 0x00000002U}, /* SEC_MODID[756]:VIN00*/ + [757] = {0xFEBF3458U, 0x00000002U}, /* SEC_MODID[757]:VIN01*/ + [758] = {0xFEBF345CU, 0x00000002U}, /* SEC_MODID[758]:VIN02*/ + [759] = {0xFEBF3460U, 0x00000002U}, /* SEC_MODID[759]:VIN03*/ + [760] = {0xFEBF3464U, 0x00000002U}, /* SEC_MODID[760]:VIN04*/ + [761] = {0xFEBF3468U, 0x00000002U}, /* SEC_MODID[761]:VIN05*/ + [762] = {0xFEBF346CU, 0x00000002U}, /* SEC_MODID[762]:VIN06*/ + [763] = {0xFEBF3470U, 0x00000002U}, /* SEC_MODID[763]:VIN07*/ + [764] = {0xFEBF3474U, 0x00000002U}, /* SEC_MODID[764]:VIN10*/ + [765] = {0xFEBF3478U, 0x00000002U}, /* SEC_MODID[765]:VIN11*/ + [766] = {0xFEBF347CU, 0x00000002U}, /* SEC_MODID[766]:VIN12*/ + [767] = {0xFEBF3480U, 0x00000002U}, /* SEC_MODID[767]:VIN13*/ + [768] = {0xFEBF3484U, 0x00000002U}, /* SEC_MODID[768]:VIN14*/ + [769] = {0xFEBF3488U, 0x00000002U}, /* SEC_MODID[769]:VIN15*/ + [770] = {0xFEBF348CU, 0x00000002U}, /* SEC_MODID[770]:VIN16*/ + [771] = {0xFEBF3490U, 0x00000002U}, /* SEC_MODID[771]:VIN17*/ + [772] = {0xFC313400U, 0x00000002U}, /* SEC_MODID[772]:ARVIP00*/ + [773] = {0xFC313404U, 0x00000002U}, /* SEC_MODID[773]:ARVIP01*/ + [774] = {0xFC313408U, 0x00000002U}, /* SEC_MODID[774]:ARVIP02*/ + [775] = {0xFC31340CU, 0x00000002U}, /* SEC_MODID[775]:ARVIP03*/ + [776] = {0xFC313410U, 0x00000002U}, /* SEC_MODID[776]:AXIFBABUSVIP0*/ + [777] = {0xFC313414U, 0x00000002U}, /* SEC_MODID[777]:ARVIP04*/ + [778] = {0xFC313418U, 0x00000002U}, /* SEC_MODID[778]:ARVIP05*/ + [779] = {0xFC31341CU, 0x00000002U}, /* SEC_MODID[779]:ARVIP06*/ + [780] = {0xFC313420U, 0x00000002U}, /* SEC_MODID[780]:ARVIP07*/ + [781] = {0xFC313424U, 0x00000002U}, /* SEC_MODID[781]:ARVIP08*/ + [782] = {0xFC31342CU, 0x00000002U}, /* SEC_MODID[782]:ECMVIP0*/ + [783] = {0xFC313430U, 0x00000002U}, /* SEC_MODID[783]:IPMMUVIP000*/ + [784] = {0xFC313438U, 0x00000002U}, /* SEC_MODID[784]:SMPO0*/ + [785] = {0xFC31343CU, 0x00000002U}, /* SEC_MODID[785]:SMPS0*/ + [786] = {0xFC313440U, 0x00000002U}, /* SEC_MODID[786]:UMFL0*/ + [787] = {0xFC313444U, 0x00000002U}, /* SEC_MODID[787]:IPMMUVIP001*/ + [788] = {0xFC313448U, 0x00000002U}, /* SEC_MODID[788]:IPMMUVIP010*/ + [789] = {0xFC31344CU, 0x00000002U}, /* SEC_MODID[789]:IPMMUVIP011*/ + [790] = {0xFC313450U, 0x00000002U}, /* SEC_MODID[790]:UMFL0M_W*/ + [791] = {0xFC313454U, 0x00000002U}, /* SEC_MODID[791]:IPMMUVIP012*/ + [792] = {0xFC313458U, 0x00000002U}, /* SEC_MODID[792]:IPMMUVIP013*/ + [793] = {0xFC31345CU, 0x00000002U}, /* SEC_MODID[793]:IPMMUVIP014*/ + [794] = {0xFC313460U, 0x00000002U}, /* SEC_MODID[794]:IPMMUVIP015*/ + [795] = {0xFC313464U, 0x00000002U}, /* SEC_MODID[795]:IPMMUVIP002*/ + [796] = {0xFC313468U, 0x00000002U}, /* SEC_MODID[796]:IPMMUVIP003*/ + [797] = {0xFC31346CU, 0x00000002U}, /* SEC_MODID[797]:IPMMUVIP004*/ + [798] = {0xFC313470U, 0x00000002U}, /* SEC_MODID[798]:IPMMUVIP005*/ + [799] = {0xFC313474U, 0x00000002U}, /* SEC_MODID[799]:IPMMUVIP006*/ + [800] = {0xFC313478U, 0x00000002U}, /* SEC_MODID[800]:IPMMUVIP007*/ + [801] = {0xFC31347CU, 0x00000002U}, /* SEC_MODID[801]:IPMMUVIP008*/ + [802] = {0xFC313480U, 0x00000002U}, /* SEC_MODID[802]:IPMMUVIP009*/ + [803] = {0xFC8834A0U, 0x00000002U}, /* SEC_MODID[803]:ARDSP0*/ + [804] = {0xFC8834A4U, 0x00000002U}, /* SEC_MODID[804]:ARDSP1*/ + [805] = {0xFC8834A8U, 0x00000002U}, /* SEC_MODID[805]:ARDSP2*/ + [806] = {0xFC8834ACU, 0x00000002U}, /* SEC_MODID[806]:ARDSP3*/ + [807] = {0xFC8834B0U, 0x00000002U}, /* SEC_MODID[807]:ARDSP4*/ + [808] = {0xFC8834B4U, 0x00000002U}, /* SEC_MODID[808]:ARDSP5*/ + [809] = {0xFC8834B8U, 0x00000002U}, /* SEC_MODID[809]:ARDSP6*/ + [810] = {0xFC8834BCU, 0x00000002U}, /* SEC_MODID[810]:ARDSP7*/ + [811] = {0xFC8834C0U, 0x00000002U}, /* SEC_MODID[811]:ECMDSP*/ + [812] = {0xFC883490U, 0x00000002U}, /* SEC_MODID[812]:AXIDSP0*/ + [813] = {0xFC883494U, 0x00000002U}, /* SEC_MODID[813]:AXIDSP1*/ + [814] = {0xFC883498U, 0x00000002U}, /* SEC_MODID[814]:AXIDSP2*/ + [815] = {0xFC88349CU, 0x00000002U}, /* SEC_MODID[815]:AXIDSP3*/ + [816] = {0xFCB53424U, 0x00000002U}, /* SEC_MODID[816]:RSV0*/ + [817] = {0xFC31350CU, 0x00000002U}, /* SEC_MODID[817]:PAP*/ + [818] = {0xFEBD3428U, 0x00000002U}, /* SEC_MODID[818]:DOC*/ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_axi_tbl" +const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[] = { + [0] = {0xFD482010U, 0x0000000FU}, /* RGIDR_MODID[4]:ARRT01*/ + [1] = {0xFD482014U, 0x0000000FU}, /* RGIDR_MODID[5]:ARRT02*/ + [2] = {0xFDA02048U, 0x0000000FU}, /* RGIDR_MODID[41]:ARS01*/ + [3] = {0xFDA0204CU, 0x0000000FU}, /* RGIDR_MODID[42]:ARS02*/ + [4] = {0xFCB62028U, 0x0000000FU}, /* RGIDR_MODID[99]:ARSP31*/ + [5] = {0xFCB6202CU, 0x0000000FU}, /* RGIDR_MODID[100]:ARSP32*/ + [6] = {0xFCB92004U, 0x0000000FU}, /* RGIDR_MODID[114]:ARSP41*/ + [7] = {0xFCB92008U, 0x0000000FU}, /* RGIDR_MODID[115]:ARSP42*/ + [8] = {0xFEBD2004U, 0x0000000FU}, /* RGIDR_MODID[153]:ARVI41*/ + [9] = {0xFEBD2008U, 0x0000000FU}, /* RGIDR_MODID[154]:ARVI42*/ + [10] = {0xFCF82140U, 0x0000000FU}, /* RGIDR_MODID[199]:ARHC1*/ + [11] = {0xFCF82144U, 0x0000000FU}, /* RGIDR_MODID[200]:ARHC2*/ + [12] = {0xFC882004U, 0x0000000FU}, /* RGIDR_MODID[215]:ARIMP01*/ + [13] = {0xFC882008U, 0x0000000FU}, /* RGIDR_MODID[216]:ARIMP02*/ + [14] = {0xFC012004U, 0x0000000FU}, /* RGIDR_MODID[247]:ARPV1*/ + [15] = {0xFC01200CU, 0x0000000FU}, /* RGIDR_MODID[249]:ARPV2*/ + [16] = {0xFDC22004U, 0x0000000FU}, /* RGIDR_MODID[279]:ARRC1*/ + [17] = {0xFDC22008U, 0x0000000FU}, /* RGIDR_MODID[280]:ARRC2*/ + [18] = {0xFD442060U, 0x0000000FU}, /* RGIDR_MODID[316]:ARRD1*/ + [19] = {0xFD442064U, 0x0000000FU}, /* RGIDR_MODID[317]:ARRD2*/ + [20] = {0xFD442084U, 0x0000000FU}, /* RGIDR_MODID[325]:ARRT1*/ + [21] = {0xFD442088U, 0x0000000FU}, /* RGIDR_MODID[326]:ARRT2*/ + [24] = {0xFC862004U, 0x0000000FU}, /* RGIDR_MODID[464]:ARSC1*/ + [25] = {0xFC862008U, 0x0000000FU}, /* RGIDR_MODID[465]:ARSC2*/ + [22] = {0xFC862028U, 0x0000000FU}, /* RGIDR_MODID[473]:ARSTM1*/ + [23] = {0xFC862038U, 0x0000000FU}, /* RGIDR_MODID[476]:ARSTM2*/ + [26] = {0xFDDC2004U, 0x0000000FU}, /* RGIDR_MODID[516]:AXIARNMM*/ + [27] = {0xFDDC200CU, 0x0000000FU}, /* RGIDR_MODID[518]:ARSM1*/ + [28] = {0xFDDC2010U, 0x0000000FU}, /* RGIDR_MODID[519]:ARSM2*/ + [29] = {0xFC802004U, 0x0000000FU}, /* RGIDR_MODID[562]:ARSN1*/ + [30] = {0xFC802008U, 0x0000000FU}, /* RGIDR_MODID[563]:ARSN2*/ + [31] = {0xFCB52004U, 0x0000000FU}, /* RGIDR_MODID[572]:ARSD01*/ + [32] = {0xFCB52008U, 0x0000000FU}, /* RGIDR_MODID[573]:ARSD02*/ + [33] = {0xFCB5203CU, 0x0000000FU}, /* RGIDR_MODID[584]:ARSP01*/ + [34] = {0xFCB52040U, 0x0000000FU}, /* RGIDR_MODID[585]:ARSP02*/ + [35] = {0xFC682004U, 0x0000000FU}, /* RGIDR_MODID[664]:ARVC1*/ + [36] = {0xFC682008U, 0x0000000FU}, /* RGIDR_MODID[665]:ARVC2*/ + [37] = {0xFEBE2008U, 0x0000000FU}, /* RGIDR_MODID[697]:ARVI11*/ + [38] = {0xFEBE200CU, 0x0000000FU}, /* RGIDR_MODID[698]:ARVI12*/ + [39] = {0xFEBF2004U, 0x0000000FU}, /* RGIDR_MODID[744]:ARVI1*/ + [40] = {0xFEBF2008U, 0x0000000FU}, /* RGIDR_MODID[745]:ARVI2*/ + [41] = {0xFC312004U, 0x0000000FU}, /* RGIDR_MODID[772]:ARVIP01*/ + [42] = {0xFC312008U, 0x0000000FU}, /* RGIDR_MODID[773]:ARVIP02*/ + [43] = {0xFC8820A4U, 0x0000000FU}, /* RGIDR_MODID[803]:ARDSP1*/ + [44] = {0xFC8820A8U, 0x0000000FU}, /* RGIDR_MODID[804]:ARDSP2*/ + [45] = {0xFD482410U, 0x00000000U}, /* RGIDW_MODID[4]:ARRT01*/ + [46] = {0xFD482414U, 0x00000000U}, /* RGIDW_MODID[5]:ARRT02*/ + [47] = {0xFDA02448U, 0x00000000U}, /* RGIDW_MODID[41]:ARS01*/ + [48] = {0xFDA0244CU, 0x00000000U}, /* RGIDW_MODID[42]:ARS02*/ + [49] = {0xFCB62428U, 0x00000000U}, /* RGIDW_MODID[99]:ARSP31*/ + [50] = {0xFCB6242CU, 0x00000000U}, /* RGIDW_MODID[100]:ARSP32*/ + [51] = {0xFCB92404U, 0x00000000U}, /* RGIDW_MODID[114]:ARSP41*/ + [52] = {0xFCB92408U, 0x00000000U}, /* RGIDW_MODID[115]:ARSP42*/ + [53] = {0xFEBD2404U, 0x00000000U}, /* RGIDW_MODID[153]:ARVI41*/ + [54] = {0xFEBD2408U, 0x00000000U}, /* RGIDW_MODID[154]:ARVI42*/ + [55] = {0xFCF82540U, 0x00000000U}, /* RGIDW_MODID[199]:ARHC1*/ + [56] = {0xFCF82544U, 0x00000000U}, /* RGIDW_MODID[200]:ARHC2*/ + [57] = {0xFC8824A4U, 0x00000000U}, /* RGIDW_MODID[802]:ARDSP1*/ + [58] = {0xFC8824A8U, 0x00000000U}, /* RGIDW_MODID[803]:ARDSP2*/ + [59] = {0xFC882404U, 0x00000000U}, /* RGIDW_MODID[215]:ARIMP01*/ + [60] = {0xFC882408U, 0x00000000U}, /* RGIDW_MODID[216]:ARIMP02*/ + [61] = {0xFC012404U, 0x00000000U}, /* RGIDW_MODID[247]:ARPV1*/ + [62] = {0xFC01240CU, 0x00000000U}, /* RGIDW_MODID[249]:ARPV2*/ + [63] = {0xFDC22404U, 0x00000000U}, /* RGIDW_MODID[279]:ARRC1*/ + [64] = {0xFDC22408U, 0x00000000U}, /* RGIDW_MODID[280]:ARRC2*/ + [65] = {0xFD442460U, 0x00000000U}, /* RGIDW_MODID[315]:ARRD1*/ + [66] = {0xFD442464U, 0x00000000U}, /* RGIDW_MODID[316]:ARRD2*/ + [67] = {0xFD442484U, 0x00000000U}, /* RGIDW_MODID[324]:ARRT1*/ + [68] = {0xFD442488U, 0x00000000U}, /* RGIDW_MODID[325]:ARRT2*/ + [71] = {0xFC862404U, 0x00000000U}, /* RGIDW_MODID[463]:ARSC1*/ + [72] = {0xFC862408U, 0x00000000U}, /* RGIDW_MODID[464]:ARSC2*/ + [69] = {0xFC862428U, 0x00000000U}, /* RGIDW_MODID[472]:ARSTM1*/ + [70] = {0xFC862438U, 0x00000000U}, /* RGIDW_MODID[475]:ARSTM2*/ + [73] = {0xFDDC2404U, 0x00000000U}, /* RGIDW_MODID[515]:AXIARNMM*/ + [74] = {0xFDDC240CU, 0x00000000U}, /* RGIDW_MODID[517]:ARSM1*/ + [75] = {0xFDDC2410U, 0x00000000U}, /* RGIDW_MODID[518]:ARSM2*/ + [76] = {0xFC802404U, 0x00000000U}, /* RGIDW_MODID[561]:ARSN1*/ + [77] = {0xFC802408U, 0x00000000U}, /* RGIDW_MODID[562]:ARSN2*/ + [78] = {0xFCB52404U, 0x00000000U}, /* RGIDW_MODID[571]:ARSD01*/ + [79] = {0xFCB52408U, 0x00000000U}, /* RGIDW_MODID[572]:ARSD02*/ + [80] = {0xFCB5243CU, 0x00000000U}, /* RGIDW_MODID[583]:ARSP01*/ + [81] = {0xFCB52440U, 0x00000000U}, /* RGIDW_MODID[584]:ARSP02*/ + [82] = {0xFC682404U, 0x00000000U}, /* RGIDW_MODID[663]:ARVC1*/ + [83] = {0xFC682408U, 0x00000000U}, /* RGIDW_MODID[664]:ARVC2*/ + [84] = {0xFEBE2408U, 0x00000000U}, /* RGIDW_MODID[696]:ARVI11*/ + [85] = {0xFEBE240CU, 0x00000000U}, /* RGIDW_MODID[697]:ARVI12*/ + [86] = {0xFEBF2404U, 0x00000000U}, /* RGIDW_MODID[743]:ARVI1*/ + [87] = {0xFEBF2408U, 0x00000000U}, /* RGIDW_MODID[744]:ARVI2*/ + [88] = {0xFC312404U, 0x00000000U}, /* RGIDW_MODID[771]:ARVIP01*/ + [89] = {0xFC312408U, 0x00000000U}, /* RGIDW_MODID[772]:ARVIP02*/ +}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_gid_tbl" +const REGION_ID_SETTING_TABLE g_rgid_gid_tbl[] = { + [0] = {0xFC0F0000U, 0x000F0024U}, /* CCI MPU GID register 0 */ +}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +const uint32_t g_rgid_rtdma_setting_value[RTDMA_MODULE_MAX][RTDMA_CH_MAX][2U] = { + {/* Module0 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, + {/* Module1 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, +}; + +const uint32_t g_rgid_sysdma_setting_value[SYSDMA_MODULE_MAX][SYSDMA_CH_MAX][2U] = { + {/* Module0 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {SYSDMA_EN, RGID_2}, /* CH0 */ + [1] = {SYSDMA_EN, RGID_2}, /* CH1 */ + [2] = {SYSDMA_EN, RGID_2}, /* CH2 */ + [3] = {SYSDMA_EN, RGID_2}, /* CH3 */ + [4] = {SYSDMA_EN, RGID_2}, /* CH4 */ + [5] = {SYSDMA_EN, RGID_2}, /* CH5 */ + [6] = {SYSDMA_EN, RGID_2}, /* CH6 */ + [7] = {SYSDMA_EN, RGID_2}, /* CH7 */ + [8] = {SYSDMA_EN, RGID_2}, /* CH8 */ + [9] = {SYSDMA_EN, RGID_2}, /* CH9 */ + [10] = {SYSDMA_EN, RGID_2}, /* CH10 */ + [11] = {SYSDMA_EN, RGID_2}, /* CH11 */ + [12] = {SYSDMA_EN, RGID_2}, /* CH12 */ + [13] = {SYSDMA_EN, RGID_2}, /* CH13 */ + [14] = {SYSDMA_EN, RGID_2}, /* CH14 */ + [15] = {SYSDMA_EN, RGID_2} /* CH15 */ + }, + {/* Module1 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {SYSDMA_EN, RGID_2}, /* CH0 */ + [1] = {SYSDMA_EN, RGID_2}, /* CH1 */ + [2] = {SYSDMA_EN, RGID_2}, /* CH2 */ + [3] = {SYSDMA_EN, RGID_2}, /* CH3 */ + [4] = {SYSDMA_EN, RGID_2}, /* CH4 */ + [5] = {SYSDMA_EN, RGID_2}, /* CH5 */ + [6] = {SYSDMA_EN, RGID_2}, /* CH6 */ + [7] = {SYSDMA_EN, RGID_2}, /* CH7 */ + [8] = {SYSDMA_EN, RGID_INVALID}, /* reserved */ + [9] = {SYSDMA_EN, RGID_INVALID}, /* reserved */ + [10] = {SYSDMA_EN, RGID_INVALID}, /* reserved */ + [11] = {SYSDMA_EN, RGID_INVALID}, /* reserved */ + [12] = {SYSDMA_EN, RGID_INVALID}, /* reserved */ + [13] = {SYSDMA_EN, RGID_INVALID}, /* reserved */ + [14] = {SYSDMA_EN, RGID_INVALID}, /* reserved */ + [15] = {SYSDMA_EN, RGID_INVALID} /* reserved */ + }, +}; + +/* When V4H, this table is used as RT-VRAM0. */ +/* RAM protection setting for SECDIV[n]D_0 / SECCTRR[m]D_0 / SECCTRW[m]D_0 */ +const RTRAM_PROTECTION_STRUCTUR g_rtsram_protection_table[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTSRAM_ICUMX_IPL_AREA] = {NOT_USED_VALUE, {0x0000FFFCU, 0x0000FFFEU}}, /* not used for address value */ + /* Area0 phys:0xE0000000-0xE003FFFF R:RGID0/1 W:RGID0 */ + [RTSRAM_ICUMX_FW_AREA] = {RTSRAM_AREA1_TOP, {0x0004FFFEU, 0x0004FFFEU}}, /* Area1 phys:0xE0040000-0xE00FFFFF R:RGID0 W:RGID0 */ + [2] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [3] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* this table is finaly setting for RT-VRAM protection */ +/* RAM protection setting for SECDIV[n]D_1 / SECCTRR[m]D_1 / SECCTRW[m]D_1 */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table_1[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM_BLANK_AREA] = {NOT_USED_VALUE, {0x0000FFB6U, 0x0000FFB2U}}, /* not used for address value */ + /* Area0 phys:0xE2000000-0xE200FFFF R:RGID0/3/6 W:RGID0/2/3/6 */ + [RTVRAM_EXTEND_CACHE_AREA] = {RTVRAM_AREA1_TOP, {0x0000BFFFU, 0x0000BFFFU}}, /* Area1 phys:0xE2010000-0xE20FFFFF R:RGID14 W:RGID14 */ + [RTVRAM_RTOS_AREA] = {RTVRAM_AREA2_TOP, {0x0000FFF4U, 0x0000FFF0U}}, /* Area2 phys:0xE2100000-0xE3BFFFFF R:RGID0/1/3 W:RGID0/1/2/3 */ + [3] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for SPTDIVCR[n] / SPTRGNCR[n] / SPTSECCR[n] */ +const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX] = { + /* access Secure */ + /* address R | W R|W */ + [SYSTEM_RAM_CX_2ND_IPL] = {NOT_USED_VALUE, {0xFFD8FFD8U, 0x00000000U}}, /* not used for address value */ + /* Area0 phys:0xE6300000-0xE635DFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [SYSTEM_RAM_SHARED_MEM] = {SYSTEM_RAM_AREA1_TOP, {0xFFD8FFD8U, 0x00000000U}}, /* Area1 phys:0xE635E000-0xE635FFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [2] = {SYSTEM_RAM_AREA2_TOP, {0xFFDAFFDAU, 0x00000000U}}, /* Area2 phys:0xE6360000-0xE63FFFFF R:RGID0/2/5 W:RGID0/2/5 */ + [3] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for DPTDIVCR[n] / DPTRGNCR[n] / DPTSECCR[n] */ +const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX] = { + /* access secure */ + /* address R | W R|W */ + [RTVRAM_EXTEND_AREA] = {NOT_USED_VALUE, {0xBFFFBFFFU, 0x00000000U}}, /* not used for address value */ + /* Area0 phys:0x04_00000000-0x04_01BFFFFF R:RGID14 W:RGID14 */ + [CR_FW_SHARED_AREA] = {DRAM_ADDR_AREA1, {0xFFBCFFBCU, 0x00000000U}}, /* Area1 phys:0x04_01C00000-0x04_01CFFFFF R:RGID0/1/6 W:RGID0/1/6 */ + [SDRAM_BLANK_AREA] = {DRAM_ADDR_AREA2, {0xFF90FF90U, 0x00000000U}}, /* Area2:OPTEE_DISABLE phys:0x04_01D00000-0x04_063FFFFF + * Area2:OPTEE_ENABLE phys:0x04_01D00000-0x04_040FFFFF + * R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFAFFF8U, 0x00000000U}}, /* Area3 phys:0x04_06400000-0x04_0643FFFF R:RGID0/2 W:RGID0/1/2 */ + [SDRAM_PUBLIC_AREA] = {DRAM_ADDR_AREA4, {0xFF90FF90U, 0x00000000U}}, /* Area4 phys:0x04_06440000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA5, {0xFFB9FFB9U, 0x00000000U}}, /* Area5 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA6, {0xFFB0FFB0U, 0x00000000U}}, /* Area6 phys:0x04_08000000-0x04_1DBFFFFF R:RGID0/1/2/3/6 W:RGID0/1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA7, {0xFFB9FFB9U, 0x00000000U}}, /* Area7 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFBDFFBDU, 0x00000000U}}, /* Area8 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFDDFFDDU, 0x00000000U}}, /* Area9 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA11,{0xBF90BF90U, 0x00000000U}}, /* Area11 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA12,{0xFFF9FFF9U, 0x00000000U}}, /* Area12 phys:0x05_00000000-0x05_FFFFFFFF R:RGID1/2 W:RGID1/2 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA13,{0xFFFFFFFFU, 0x00000000U}}, /* Area13 phys:0x06_00000000-0x06_FFFFFFFF */ + [14] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [16] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +#else + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFAFFFAU, 0x00000000U}}, /* Area3 phys:0x04_04100000-0x04_063FFFFF R:RGID0/2 W:RGID0/2 */ + [SDRAM_PROTECT_AREA2]= {DRAM_ADDR_AREA4, {0xFFFAFFF8U, 0x00000000U}}, /* Area4 phys:0x04_06400000-0x04_0643FFFF R:RGID0/2 W:RGID0/1/2 */ + [SDRAM_BLANK_AREA2] = {DRAM_ADDR_AREA5, {0xFF90FF90U, 0x00000000U}}, /* Area5 phys:0x04_06440000-0x04_07DFFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [OPTEE_SHARED_AREA] = {DRAM_ADDR_AREA6, {0xFFFBFFFBU, 0x00000000U}}, /* Area6 phys:0x04_07E00000-0x04_07EFFFFF R:RGID2 W:RGID2 */ + [SDRAM_BLANK_AREA3] = {DRAM_ADDR_AREA7, {0xFF90FF90U, 0x00000000U}}, /* Area7 phys:0x04_07F00000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFB9FFB9U, 0x00000000U}}, /* Area8 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFB0FFB0U, 0x00000000U}}, /* Area9 phys:0x04_08000000-0x04_1DBFFFFF R:RGID0/1/2/3/6 W:RGID0/1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA11,{0xFFBDFFBDU, 0x00000000U}}, /* Area11 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA12,{0xFFDDFFDDU, 0x00000000U}}, /* Area12 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFB9FFB9U, 0x00000000U}}, /* Area13 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA14,{0xBF90BF90U, 0x00000000U}}, /* Area14 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA15,{0xFFF9FFF9U, 0x00000000U}}, /* Area15 phys:0x05_00000000-0x05_FFFFFFFF R:RGID1/2 W:RGID1/2 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA16,{0xFFFFFFFFU, 0x00000000U}}, /* Area16 phys:0x06_00000000-0x06_FFFFFFFF */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + [17] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [18] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [19] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [20] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [21] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [22] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [23] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [24] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [25] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [26] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [27] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [28] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [29] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [30] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [31] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [32] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [33] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [34] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [35] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [36] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [37] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [38] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [39] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [40] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [41] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [42] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [43] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [44] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [45] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [46] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [47] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [48] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [49] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [50] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [51] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [52] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [53] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [54] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [55] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [56] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [57] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [58] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [59] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [60] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [61] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [62] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [63] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +const CONFIGURATION_SETTING_TABLE g_fdt_tbl[FDT_REG_MAX] = { + [0] = {0xFCF80700U, 0x00000008U}, /*FDT_PCI00*/ + [1] = {0xFCF80710U, 0x00000005U}, /*FDT_AVB0*/ + [2] = {0xFCF80714U, 0x00000005U}, /*FDT_AVB1*/ + [3] = {0xFCF80718U, 0x00000005U}, /*FDT_AVB2*/ + [4] = {0xFF880704U, 0x0000000BU}, /*FDT_FBABUSIR0*/ + [5] = {0xFF880708U, 0x0000000BU}, /*FDT_FBABUSIR1*/ + [6] = {0xFF88070CU, 0x0000000BU}, /*FDT_FBABUSIR2*/ + [7] = {0xFF880710U, 0x0000000BU}, /*FDT_FBABUSIR3*/ + [8] = {0xFF88071CU, 0x0000000BU}, /*FDT_IMP0*/ + [9] = {0xFF880720U, 0x0000000BU}, /*FDT_IMP1*/ + [10] = {0xFF880728U, 0x0000000BU}, /*FDT_DSPD*/ + [11] = {0xFF88072CU, 0x0000000BU}, /*FDT_DSPP*/ + [12] = {0xFC610714U, 0x00000008U}, /*FDT_RGX0*/ + [13] = {0xFDC2070CU, 0x00000008U}, /*FDT_DCLS_ICUMX*/ + [14] = {0xFDC20710U, 0x00000008U}, /*FDT_ICUMX*/ + [15] = {0xFD430700U, 0x00000008U}, /*FDT_PERI_RTDM0*/ + [16] = {0xFD430704U, 0x00000008U}, /*FDT_PERI_RTDM1*/ + [17] = {0xFD440708U, 0x00000008U}, /*FDT_BUS_RTDM0M*/ + [18] = {0xFD44070CU, 0x00000008U}, /*FDT_BUS_RTDM1M*/ + [19] = {0xFD440718U, 0x00000008U}, /*FDT_CR52SS0*/ + [20] = {0xFD44071CU, 0x00000008U}, /*FDT_CSD*/ + [21] = {0xFD440724U, 0x00000008U}, /*FDT_INTAP0*/ + [22] = {0xFD440728U, 0x00000008U}, /*FDT_MEM_RTDM0*/ + [23] = {0xFD44072CU, 0x00000008U}, /*FDT_MEM_RTDM1*/ + [24] = {0xFD44075CU, 0x00000008U}, /*FDT_CR52SS1*/ + [25] = {0xFD440760U, 0x00000008U}, /*FDT_CR52SS2*/ + [26] = {0xFF860710U, 0x00000008U}, /*FDT_CCI*/ + [27] = {0xFF860718U, 0x00000008U}, /*FDT_FBABUSTOP0*/ + [28] = {0xFCB80704U, 0x00000006U}, /*FDT_PERI_SYDM1*/ + [29] = {0xFCB80708U, 0x00000006U}, /*FDT_PERI_SYDM2*/ + [30] = {0xFCB50708U, 0x00000006U}, /*FDT_BUS_SYDM1*/ + [31] = {0xFCB5070CU, 0x00000006U}, /*FDT_BUS_SYDM2*/ + [32] = {0xFCB50710U, 0x00000004U}, /*FDT_FRAY*/ + [33] = {0xFCB50718U, 0x00000006U}, /*FDT_MEM_SYDM1*/ + [34] = {0xFCB5071CU, 0x00000006U}, /*FDT_MEM_SYDM2*/ + [35] = {0xFCB50720U, 0x00000006U}, /*FDT_SDHI0*/ + [36] = {0xFF810700U, 0x00000008U}, /*FDT_AXMM2AXSTM*/ + [37] = {0xFF810704U, 0x00000008U}, /*FDT_CSDE0*/ + [38] = {0xFF810708U, 0x00000008U}, /*FDT_CSDE1*/ + [39] = {0xFC080704U, 0x00000006U}, /*FDT_FBABUSVC*/ + [40] = {0xFC080710U, 0x0000000AU}, /*FDT_IMR00*/ + [41] = {0xFC080714U, 0x0000000AU}, /*FDT_IMR01*/ + [42] = {0xFC080724U, 0x0000000AU}, /*FDT_IMR10*/ + [43] = {0xFC080728U, 0x0000000AU}, /*FDT_IMR11*/ + [44] = {0xFC080740U, 0x0000000AU}, /*FDT_IMS0*/ + [45] = {0xFC080744U, 0x0000000AU}, /*FDT_IMS1*/ + [46] = {0xFC080748U, 0x0000000AU}, /*FDT_IV1ES*/ + [47] = {0xFC9E0700U, 0x00000005U}, /*FDT_DSITXLINK0*/ + [48] = {0xFC9E0708U, 0x00000008U}, /*FDT_FBABUSVIO*/ + [49] = {0xFC9E0714U, 0x00000008U}, /*FDT_FCPVD0*/ + [50] = {0xFC9E071CU, 0x00000008U}, /*FDT_FCPVX0*/ + [51] = {0xFC9F0700U, 0x0000000EU}, /*FDT_ISP02*/ + [52] = {0xFC9F0704U, 0x0000000EU}, /*FDT_ISP03*/ + [53] = {0xFC9F0708U, 0x0000000EU}, /*FDT_ISP04*/ + [54] = {0xFC9F0710U, 0x0000000EU}, /*FDT_VIN0*/ + [55] = {0xFC9F0714U, 0x0000000EU}, /*FDT_VIN1*/ + [56] = {0xFC9F0720U, 0x0000000EU}, /*FDT_ISP00*/ + [57] = {0xFC9F0724U, 0x0000000EU}, /*FDT_ISP01*/ + [58] = {0xFC310704U, 0x00000006U}, /*FDT_FBABUSVIP0*/ + [59] = {0xFC310710U, 0x0000000BU}, /*FDT_SMPO0*/ + [60] = {0xFC310718U, 0x0000000BU}, /*FDT_SMPS0*/ + [61] = {0xFC31071CU, 0x0000000BU}, /*FDT_UMFL0*/ + [62] = {0xFC400204U, 0x0000000BU}, /*FDT_DSP00*/ + [63] = {0xFC400208U, 0x0000000BU}, /*FDT_DSP01*/ + [64] = {0xFC40020CU, 0x0000000BU}, /*FDT_DSP10*/ + [65] = {0xFC400210U, 0x0000000BU}, /*FDT_DSP11*/ + [66] = {0xFC400214U, 0x0000000BU}, /*FDT_DSP20*/ + [67] = {0xFC400218U, 0x0000000BU}, /*FDT_DSP21*/ + [68] = {0xFC40021CU, 0x0000000BU}, /*FDT_DSP30*/ + [69] = {0xFC400220U, 0x0000000BU}, /*FDT_DSP31*/ + [70] = {0xFC310708U, 0x0000000BU}, /*FDT_PAP*/ + [71] = {0xFD440720U, 0x00000008U}, /*FDT_CSDE2*/ +}; + +const CONFIGURATION_SETTING_TABLE g_inten_tbl[INTEN_REG_MAX] = { + [0] = {0xFF8403C0U, 0x00001003U}, /*FIXINTENTOP00*/ + [1] = {0xFDA723C0U, 0x00000000U}, /*FIXINTENTOP10*/ + [2] = {0xFF8483C0U, 0x00000007U}, /*FIXINTENTOP20*/ + [3] = {0xFDDFC3C0U, 0x000000F0U}, /*FIXINTENMM0*/ + [4] = {0xFD8003C0U, 0x099F1CF3U}, /*FIXINTENRT00*/ + [5] = {0xFD8003C4U, 0x00042000U}, /*FIXINTENRT01*/ + [6] = {0xFD8043C0U, 0x00000033U}, /*FIXINTENRT10*/ + [7] = {0xFD8083C0U, 0x000000CCU}, /*FIXINTENRT20*/ + [8] = {0xFD80C3C0U, 0x00000000U}, /*FIXINTENRT30*/ + [9] = {0xFCB303C0U, 0x001DDDC0U}, /*FIXINTENPER000*/ + [10] = {0xFCB343C0U, 0x0000000FU}, /*FIXINTENPER010*/ + [11] = {0xFCB383C0U, 0x00000000U}, /*FIXINTENPER020*/ + [12] = {0xFCB3C3C0U, 0x00000000U}, /*FIXINTENPER030*/ + [13] = {0xFCE903C0U, 0x210243F8U}, /*FIXINTENHSC0*/ + [14] = {0xFCE903C4U, 0x00000000U}, /*FIXINTENHSC1*/ + [15] = {0xFC8F83C0U, 0x30004460U}, /*FIXINTENVIO00*/ + [16] = {0xFC8F83C4U, 0x00000000U}, /*FIXINTENVIO01*/ + [17] = {0xFC8F03C0U, 0x5100000DU}, /*FIXINTENVIO10*/ + [18] = {0xFC8F03C4U, 0x00000029U}, /*FIXINTENVIO11*/ + [19] = {0xFC8FC3C0U, 0x00000000U}, /*FIXINTENVIO20*/ + [20] = {0xFC0103C0U, 0x3266A3A3U}, /*FIXINTENVC00*/ + [21] = {0xFF8E03C0U, 0x03C3C00FU}, /*FIXINTENIR0*/ + [22] = {0xFC2F03C0U, 0x0000037FU}, /*FIXINTENVIP00*/ + [23] = {0xFC6403C0U, 0x00000005U}, /*FIXINTEN3DG0*/ + [24] = {0xFC4803C0U, 0x0003FFFFU}, /*FIXINTENDSP0*/ + [25] = {0xFF840440U, 0xC5400003U}, /*EDCINTENTOP00*/ + [26] = {0xFF840444U, 0x81552A0AU}, /*EDCINTENTOP01*/ + [27] = {0xFF840448U, 0x0000000FU}, /*EDCINTENTOP02*/ + [28] = {0xFDA72440U, 0xFCDEFFFDU}, /*EDCINTENTOP10*/ + [29] = {0xFDA72444U, 0x0039BDFFU}, /*EDCINTENTOP11*/ + [30] = {0xFF848440U, 0x00000003U}, /*EDCINTENTOP20*/ + [31] = {0xFF844440U, 0x0000003FU}, /*EDCINTENTOP30*/ + [32] = {0xFDDFC440U, 0xFFFFFFFFU}, /*EDCINTENMM0*/ + [33] = {0xFDDFC444U, 0xFFFFFFFFU}, /*EDCINTENMM1*/ + [34] = {0xFDDFC448U, 0x0FFFFFFFU}, /*EDCINTENMM2*/ + [35] = {0xFDDFC44CU, 0xFFFFFEFFU}, /*EDCINTENMM3*/ + [36] = {0xFDDFC450U, 0x0FFFFFFFU}, /*EDCINTENMM4*/ + [37] = {0xFD800440U, 0x3F77BFFFU}, /*EDCINTENRT00*/ + [38] = {0xFD800444U, 0x001DF804U}, /*EDCINTENRT01*/ + [39] = {0xFD800448U, 0x81FFFFAFU}, /*EDCINTENRT02*/ + [40] = {0xFD80044CU, 0x3EF3FFFFU}, /*EDCINTENRT03*/ + [41] = {0xFD800450U, 0x6DFDDFF7U}, /*EDCINTENRT04*/ + [42] = {0xFD800454U, 0x9FC001FFU}, /*EDCINTENRT05*/ + [43] = {0xFD808440U, 0x00006B73U}, /*EDCINTENRT20*/ + [44] = {0xFD80C440U, 0x7FFC7FFDU}, /*EDCINTENRT30*/ + [45] = {0xFD80C444U, 0x00000000U}, /*EDCINTENRT31*/ + [46] = {0xFCB30440U, 0x80800003U}, /*EDCINTENPER000*/ + [47] = {0xFCB30444U, 0x0000000EU}, /*EDCINTENPER001*/ + [48] = {0xFCB30448U, 0xB7F81E80U}, /*EDCINTENPER002*/ + [49] = {0xFCB3044CU, 0xFF0F03FDU}, /*EDCINTENPER003*/ + [50] = {0xFCB30450U, 0x87E73B7CU}, /*EDCINTENPER004*/ + [51] = {0xFCB30454U, 0xEC010007U}, /*EDCINTENPER005*/ + [52] = {0xFCB30458U, 0x2000FFFFU}, /*EDCINTENPER006*/ + [53] = {0xFCB3045CU, 0x00000180U}, /*EDCINTENPER007*/ + [54] = {0xFCB34440U, 0xFFF1E1E7U}, /*EDCINTENPER010*/ + [55] = {0xFCB34444U, 0x0000000FU}, /*EDCINTENPER011*/ + [56] = {0xFCB38440U, 0xFFFFFFF3U}, /*EDCINTENPER020*/ + [57] = {0xFCB3C440U, 0xFFFFFF0FU}, /*EDCINTENPER030*/ + [58] = {0xFCB3C444U, 0x0FFFFFFFU}, /*EDCINTENPER031*/ + [59] = {0xFCB3C448U, 0x000083FEU}, /*EDCINTENPER032*/ + [60] = {0xFCE90440U, 0xDF7FBFFBU}, /*EDCINTENHSC0*/ + [61] = {0xFCE90444U, 0x10047627U}, /*EDCINTENHSC1*/ + [62] = {0xFCE90448U, 0x81004050U}, /*EDCINTENHSC2*/ + [63] = {0xFCE9044CU, 0xA6F84210U}, /*EDCINTENHSC3*/ + [64] = {0xFCE90450U, 0x00D30901U}, /*EDCINTENHSC4*/ + [65] = {0xFCE90454U, 0x00000001U}, /*EDCINTENHSC5*/ + [66] = {0xFC8F8440U, 0x37FFFFFFU}, /*EDCINTENVIO00*/ + [67] = {0xFC8F8444U, 0x0E3FFC7FU}, /*EDCINTENVIO01*/ + [68] = {0xFC8F8448U, 0x00000000U}, /*EDCINTENVIO02*/ + [69] = {0xFC8F844CU, 0xCCCCC000U}, /*EDCINTENVIO03*/ + [70] = {0xFC8F8450U, 0x070F0CF0U}, /*EDCINTENVIO04*/ + [71] = {0xFC8F8454U, 0xC0000000U}, /*EDCINTENVIO05*/ + [72] = {0xFC8F8458U, 0x001F2080U}, /*EDCINTENVIO06*/ + [73] = {0xFC8F0440U, 0x45010103U}, /*EDCINTENVIO10*/ + [74] = {0xFC8F0444U, 0xFFFF0000U}, /*EDCINTENVIO11*/ + [75] = {0xFC8F0448U, 0xFFFF0000U}, /*EDCINTENVIO12*/ + [76] = {0xFC8F044CU, 0xE234D7CCU}, /*EDCINTENVIO13*/ + [77] = {0xFC8F0450U, 0xC8234D16U}, /*EDCINTENVIO14*/ + [78] = {0xFC8F0454U, 0x1522511FU}, /*EDCINTENVIO15*/ + [79] = {0xFC8F0458U, 0x1F800000U}, /*EDCINTENVIO16*/ + [80] = {0xFC8FC440U, 0x00A68B45U}, /*EDCINTENVIO20*/ + [81] = {0xFC010440U, 0x0010CC07U}, /*EDCINTENVC00*/ + [82] = {0xFC010444U, 0xC3CF0E30U}, /*EDCINTENVC01*/ + [83] = {0xFC010448U, 0xFFFFFC53U}, /*EDCINTENVC02*/ + [84] = {0xFC01044CU, 0x9F773DCFU}, /*EDCINTENVC03*/ + [85] = {0xFC010450U, 0x0000003BU}, /*EDCINTENVC04*/ + [86] = {0xFF8E0440U, 0x0004D1FFU}, /*EDCINTENIR0*/ + [87] = {0xFF8E0444U, 0xC983DF98U}, /*EDCINTENIR1*/ + [88] = {0xFF8E0448U, 0x7BD3FFFFU}, /*EDCINTENIR2*/ + [89] = {0xFF8E044CU, 0x0F0000FFU}, /*EDCINTENIR3*/ + [90] = {0xFC2F0440U, 0x0007FF77U}, /*EDCINTENVIP00*/ + [91] = {0xFC2F0444U, 0xF3BA0000U}, /*EDCINTENVIP01*/ + [92] = {0xFC2F0448U, 0x001F7BE8U}, /*EDCINTENVIP02*/ + [93] = {0xFC2F044CU, 0x00000000U}, /*EDCINTENVIP03*/ + [94] = {0xFC2F0450U, 0x18000000U}, /*EDCINTENVIP04*/ + [95] = {0xFC2F0454U, 0x0000FAFAU}, /*EDCINTENVIP05*/ + [96] = {0xFC640440U, 0xF3FC3F7EU}, /*EDCINTEN3DG0*/ + [97] = {0xFC640444U, 0x0081FC47U}, /*EDCINTEN3DG1*/ + [98] = {0xFC480440U, 0x03FFFFFFU}, /*EDCINTENDSP0*/ + [99] = {0xFF840680U, 0x000F2D8FU}, /*ICISTPINTENTOP00*/ + [100] = {0xFDA72680U, 0x00000003U}, /*ICISTPINTENTOP10*/ + [101] = {0xFF848680U, 0x00000007U}, /*ICISTPINTENTOP20*/ + [102] = {0xFF844680U, 0x000000D7U}, /*ICISTPINTENTOP30*/ + [103] = {0xFDDFC680U, 0x0007EFFFU}, /*ICISTPINTENMM0*/ + [104] = {0xFD800680U, 0x0A007FFFU}, /*ICISTPINTENRT00*/ + [105] = {0xFD804680U, 0x000001E3U}, /*ICISTPINTENRT10*/ + [106] = {0xFD808680U, 0x00000007U}, /*ICISTPINTENRT20*/ + [107] = {0xFD80C680U, 0x00000003U}, /*ICISTPINTENRT30*/ + [108] = {0xFCB30680U, 0x000235F1U}, /*ICISTPINTENPER000*/ + [109] = {0xFCB34680U, 0x0000000FU}, /*ICISTPINTENPER010*/ + [110] = {0xFCB38680U, 0x00000003U}, /*ICISTPINTENPER020*/ + [111] = {0xFCB3C680U, 0x00000003U}, /*ICISTPINTENPER030*/ + [112] = {0xFCE90680U, 0x000000C7U}, /*ICISTPINTENHSC0*/ + [113] = {0xFC8F8680U, 0x00000013U}, /*ICISTPINTENVIO00*/ + [114] = {0xFC8F0680U, 0x0000003FU}, /*ICISTPINTENVIO10*/ + [115] = {0xFC8FC680U, 0x00000003U}, /*ICISTPINTENVIO20*/ + [116] = {0xFC010680U, 0x0000003FU}, /*ICISTPINTENVC00*/ + [117] = {0xFF8E0680U, 0x0000EF47U}, /*ICISTPINTENIR0*/ + [118] = {0xFC2F0680U, 0x00000037U}, /*ICISTPINTENVIP00*/ + [119] = {0xFC640680U, 0x0000000FU}, /*ICISTPINTEN3DG0*/ + [120] = {0xFC480680U, 0x000000FFU}, /*ICISTPINTENDSP0*/ + [121] = {0xFF840580U, 0x00000029U}, /*DCLSINTENTOP00*/ + [122] = {0xFDA72580U, 0x00000001U}, /*DCLSINTENTOP10*/ + [123] = {0xFF848580U, 0x00000003U}, /*DCLSINTENTOP20*/ + [124] = {0xFF844580U, 0x00000003U}, /*DCLSINTENTOP30*/ + [125] = {0xFDDFC580U, 0x3FFFFFF7U}, /*DCLSINTENMM0*/ + [126] = {0xFDDFC584U, 0x00000080U}, /*DCLSINTENMM1*/ + [127] = {0xFD800580U, 0x0FFFE7FFU}, /*DCLSINTENRT00*/ + [128] = {0xFD800584U, 0x00000036U}, /*DCLSINTENRT01*/ + [129] = {0xFD808580U, 0x00000033U}, /*DCLSINTENRT20*/ + [130] = {0xFD80C580U, 0x00000001U}, /*DCLSINTENRT30*/ + [131] = {0xFCB30580U, 0x039E1F43U}, /*DCLSINTENPER000*/ + [132] = {0xFCB34580U, 0x00000007U}, /*DCLSINTENPER010*/ + [133] = {0xFCB38580U, 0x00000003U}, /*DCLSINTENPER020*/ + [134] = {0xFCB3C580U, 0x0000000FU}, /*DCLSINTENPER030*/ + [135] = {0xFCE90580U, 0x0BFF01FAU}, /*DCLSINTENHSC0*/ + [136] = {0xFC8F8580U, 0x5000FC0FU}, /*DCLSINTENVIO00*/ + [137] = {0xFC8F0580U, 0x0C6A80FFU}, /*DCLSINTENVIO10*/ + [138] = {0xFC8FC580U, 0x00000001U}, /*DCLSINTENVIO20*/ + [139] = {0xFC010580U, 0x03F8E79FU}, /*DCLSINTENVC00*/ + [140] = {0xFF8E0580U, 0x0FFD9E63U}, /*DCLSINTENIR0*/ + [141] = {0xFC2F0580U, 0xE0000EF7U}, /*DCLSINTENVIP00*/ + [142] = {0xFC2F0584U, 0x0000003FU}, /*DCLSINTENVIP01*/ + [143] = {0xFC480580U, 0x00000003U}, /*DCLSINTENDSP0*/ + [144] = {0xFF840480U, 0xF986FFFFU}, /*LSCHKINTENTOP00*/ + [145] = {0xFF840484U, 0x0003E61CU}, /*LSCHKINTENTOP01*/ + [146] = {0xFDA72480U, 0x00000003U}, /*LSCHKINTENTOP10*/ + [147] = {0xFF848480U, 0x0000001FU}, /*LSCHKINTENTOP20*/ + [148] = {0xFF844480U, 0x0006B5ADU}, /*LSCHKINTENTOP30*/ + [149] = {0xFDDFC480U, 0xFEFFF7FFU}, /*LSCHKINTENMM0*/ + [150] = {0xFDDFC484U, 0x0000017FU}, /*LSCHKINTENMM1*/ + [151] = {0xFD800480U, 0x4FFF3F4FU}, /*LSCHKINTENRT00*/ + [152] = {0xFD800484U, 0x003FFE7FU}, /*LSCHKINTENRT01*/ + [153] = {0xFD800488U, 0x04C4C000U}, /*LSCHKINTENRT02*/ + [154] = {0xFD804480U, 0x000FC1F8U}, /*LSCHKINTENRT10*/ + [155] = {0xFD808480U, 0x0000037BU}, /*LSCHKINTENRT20*/ + [156] = {0xFD80C480U, 0x00000003U}, /*LSCHKINTENRT30*/ + [157] = {0xFCB30480U, 0x1FAF1F0FU}, /*LSCHKINTENPER000*/ + [158] = {0xFCB30484U, 0x00000CAFU}, /*LSCHKINTENPER001*/ + [159] = {0xFCB34480U, 0x000000FFU}, /*LSCHKINTENPER010*/ + [160] = {0xFCB38480U, 0x0000000FU}, /*LSCHKINTENPER020*/ + [161] = {0xFCB3C480U, 0x0000000FU}, /*LSCHKINTENPER030*/ + [162] = {0xFCE90480U, 0x1E043FCFU}, /*LSCHKINTENHSC0*/ + [163] = {0xFCE90484U, 0x00000418U}, /*LSCHKINTENHSC1*/ + [164] = {0xFC8F8480U, 0x711E2307U}, /*LSCHKINTENVIO00*/ + [165] = {0xFC8F8484U, 0x000E0400U}, /*LSCHKINTENVIO01*/ + [166] = {0xFC8F0480U, 0xA0040003U}, /*LSCHKINTENVIO10*/ + [167] = {0xFC8F0484U, 0x0031B368U}, /*LSCHKINTENVIO11*/ + [168] = {0xFC8FC480U, 0x00000003U}, /*LSCHKINTENVIO20*/ + [169] = {0xFC010480U, 0x7EF0A3A3U}, /*LSCHKINTENVC00*/ + [170] = {0xFC010484U, 0x00000D96U}, /*LSCHKINTENVC01*/ + [171] = {0xFF8E0480U, 0x4033D0FFU}, /*LSCHKINTENIR0*/ + [172] = {0xFF8E0484U, 0x003F33FCU}, /*LSCHKINTENIR1*/ + [173] = {0xFC2F0480U, 0x00057FFFU}, /*LSCHKINTENVIP00*/ + [174] = {0xFC2F0484U, 0x00000000U}, /*LSCHKINTENVIP01*/ + [175] = {0xFC640480U, 0x0000063FU}, /*LSCHKINTEN3DG0*/ + [176] = {0xFC480480U, 0x3FFFFFFFU}, /*LSCHKINTENDSP0*/ + [177] = {0xFF840700U, 0x0000001EU}, /*OTHINTENTOP00*/ + [178] = {0xFDDFC700U, 0x008FCFFFU}, /*OTHINTENMM0*/ + [179] = {0xFD800700U, 0x00FFFFF0U}, /*OTHINTENRT00*/ + [180] = {0xFCB30700U, 0x0000003CU}, /*OTHINTENPER000*/ + [181] = {0xFCE90700U, 0x0000003CU}, /*OTHINTENHSC0*/ + [182] = {0xFC8F8700U, 0x00000000U}, /*OTHINTENVIO00*/ + [183] = {0xFC8F0700U, 0x0000007CU}, /*OTHINTENVIO10*/ + [184] = {0xFC010700U, 0x000000F0U}, /*OTHINTENVC00*/ + [185] = {0xFF8E0700U, 0x000000F0U}, /*OTHINTENIR0*/ + [186] = {0xFC2F0700U, 0x00000FC0U}, /*OTHINTENVIP00*/ + [187] = {0xFC640700U, 0x00000024U}, /*OTHINTEN3DG0*/ + [188] = {0xFF840400U, 0xC5001FFFU}, /*ROUINTENTOP00*/ + [189] = {0xFF840404U, 0xC8B3458FU}, /*ROUINTENTOP01*/ + [190] = {0xFF840408U, 0x8000F3E7U}, /*ROUINTENTOP02*/ + [191] = {0xFDA72400U, 0xFE7F7FFFU}, /*ROUINTENTOP10*/ + [192] = {0xFDA72404U, 0x0039FDFFU}, /*ROUINTENTOP11*/ + [193] = {0xFF848400U, 0x0000007FU}, /*ROUINTENTOP20*/ + [194] = {0xFF844400U, 0x0035F5D7U}, /*ROUINTENTOP30*/ + [195] = {0xFDDFC400U, 0xFBFFFFADU}, /*ROUINTENMM0*/ + [196] = {0xFDDFC404U, 0xFFFFBFEFU}, /*ROUINTENMM1*/ + [197] = {0xFDDFC408U, 0xFFFFF7FEU}, /*ROUINTENMM2*/ + [198] = {0xFDDFC40CU, 0x01FFFFFFU}, /*ROUINTENMM3*/ + [199] = {0xFD800400U, 0x007F403FU}, /*ROUINTENRT00*/ + [200] = {0xFD800404U, 0x40000040U}, /*ROUINTENRT01*/ + [201] = {0xFD800408U, 0x7BFFFFFFU}, /*ROUINTENRT02*/ + [202] = {0xFD80040CU, 0xFFFFE387U}, /*ROUINTENRT03*/ + [203] = {0xFD800410U, 0x68006F87U}, /*ROUINTENRT04*/ + [204] = {0xFD800414U, 0xFFFFFFFEU}, /*ROUINTENRT05*/ + [205] = {0xFD800418U, 0x077E30FFU}, /*ROUINTENRT06*/ + [206] = {0xFD804400U, 0x001E3C78U}, /*ROUINTENRT10*/ + [207] = {0xFD808400U, 0x0000034DU}, /*ROUINTENRT20*/ + [208] = {0xFD80C400U, 0x7FFE3FFFU}, /*ROUINTENRT30*/ + [209] = {0xFD80C404U, 0x00000000U}, /*ROUINTENRT31*/ + [210] = {0xFCB30400U, 0x00800007U}, /*ROUINTENPER000*/ + [211] = {0xFCB30404U, 0x00000000U}, /*ROUINTENPER001*/ + [212] = {0xFCB30408U, 0xFDB01C80U}, /*ROUINTENPER002*/ + [213] = {0xFCB3040CU, 0xC771EFFFU}, /*ROUINTENPER003*/ + [214] = {0xFCB30410U, 0x020FDEE4U}, /*ROUINTENPER004*/ + [215] = {0xFCB30414U, 0xFFBDE010U}, /*ROUINTENPER005*/ + [216] = {0xFCB30418U, 0x010023FFU}, /*ROUINTENPER006*/ + [217] = {0xFCB3041CU, 0x0000005EU}, /*ROUINTENPER007*/ + [218] = {0xFCB34400U, 0xFFF1EF1EU}, /*ROUINTENPER010*/ + [219] = {0xFCB34404U, 0x0000003FU}, /*ROUINTENPER011*/ + [220] = {0xFCB38400U, 0x0FFFFFFFU}, /*ROUINTENPER020*/ + [221] = {0xFCB3C400U, 0xFFFFFFFFU}, /*ROUINTENPER030*/ + [222] = {0xFCB3C404U, 0xFE0FFFFFU}, /*ROUINTENPER031*/ + [223] = {0xFCB3C408U, 0x00000083U}, /*ROUINTENPER032*/ + [224] = {0xFCE90400U, 0xEFE1D3F3U}, /*ROUINTENHSC0*/ + [225] = {0xFCE90404U, 0x00004001U}, /*ROUINTENHSC1*/ + [226] = {0xFCE90408U, 0x0FFB1004U}, /*ROUINTENHSC2*/ + [227] = {0xFCE9040CU, 0x4C010049U}, /*ROUINTENHSC3*/ + [228] = {0xFCE90410U, 0x00000807U}, /*ROUINTENHSC4*/ + [229] = {0xFC8F8400U, 0x7FFFFBE1U}, /*ROUINTENVIO00*/ + [230] = {0xFC8F8404U, 0x00001000U}, /*ROUINTENVIO01*/ + [231] = {0xFC8F8408U, 0xF8000000U}, /*ROUINTENVIO02*/ + [232] = {0xFC8F840CU, 0x18000079U}, /*ROUINTENVIO03*/ + [233] = {0xFC8F8410U, 0x20600000U}, /*ROUINTENVIO04*/ + [234] = {0xFC8F8414U, 0x0000000CU}, /*ROUINTENVIO05*/ + [235] = {0xFC8F8418U, 0xFFFE0002U}, /*ROUINTENVIO06*/ + [236] = {0xFC8F0400U, 0x2000034DU}, /*ROUINTENVIO10*/ + [237] = {0xFC8F0404U, 0x4D15E1C6U}, /*ROUINTENVIO11*/ + [238] = {0xFC8F0408U, 0x000078E3U}, /*ROUINTENVIO12*/ + [239] = {0xFC8F040CU, 0x00000000U}, /*ROUINTENVIO13*/ + [240] = {0xFC8F0410U, 0x3C000000U}, /*ROUINTENVIO14*/ + [241] = {0xFC8F0414U, 0x0E028000U}, /*ROUINTENVIO15*/ + [242] = {0xFC8F0418U, 0x0000001CU}, /*ROUINTENVIO16*/ + [243] = {0xFC8FC400U, 0x002962B1U}, /*ROUINTENVIO20*/ + [244] = {0xFC010400U, 0x00000000U}, /*ROUINTENVC00*/ + [245] = {0xFC010404U, 0x38001860U}, /*ROUINTENVC01*/ + [246] = {0xFC010408U, 0xE1C0033CU}, /*ROUINTENVC02*/ + [247] = {0xFC01040CU, 0x7EFFF3FDU}, /*ROUINTENVC03*/ + [248] = {0xFC010410U, 0x000001F7U}, /*ROUINTENVC04*/ + [249] = {0xFF8E0400U, 0x883CEF3EU}, /*ROUINTENIR0*/ + [250] = {0xFF8E0404U, 0x087C821EU}, /*ROUINTENIR1*/ + [251] = {0xFF8E0408U, 0xFFFD0F42U}, /*ROUINTENIR2*/ + [252] = {0xFF8E040CU, 0x000001B6U}, /*ROUINTENIR3*/ + [253] = {0xFC2F0400U, 0x70010B6EU}, /*ROUINTENVIP00*/ + [254] = {0xFC2F0404U, 0x9C07C003U}, /*ROUINTENVIP01*/ + [255] = {0xFC2F0408U, 0x00EE96E1U}, /*ROUINTENVIP02*/ + [256] = {0xFC2F040CU, 0x00000000U}, /*ROUINTENVIP03*/ + [257] = {0xFC2F0410U, 0x00000000U}, /*ROUINTENVIP04*/ + [258] = {0xFC2F0414U, 0x01500000U}, /*ROUINTENVIP05*/ + [259] = {0xFC640400U, 0x03FC02FEU}, /*ROUINTEN3DG0*/ + [260] = {0xFC640404U, 0x000007FFU}, /*ROUINTEN3DG1*/ + [261] = {0xFC480400U, 0xFFFFFFFFU}, /*ROUINTENDSP0*/ + [262] = {0xFF840500U, 0x3F5FF3FFU}, /*RSCHKINTENTOP00*/ + [263] = {0xFF840504U, 0x603FFE73U}, /*RSCHKINTENTOP01*/ + [264] = {0xFF840508U, 0x0001C000U}, /*RSCHKINTENTOP02*/ + [265] = {0xFDA72500U, 0x00000001U}, /*RSCHKINTENTOP10*/ + [266] = {0xFF848500U, 0x0000001FU}, /*RSCHKINTENTOP20*/ + [267] = {0xFF844500U, 0x00001AD9U}, /*RSCHKINTENTOP30*/ + [268] = {0xFDDFC500U, 0xFFFFFFFFU}, /*RSCHKINTENMM0*/ + [269] = {0xFDDFC504U, 0x00000007U}, /*RSCHKINTENMM1*/ + [270] = {0xFD800500U, 0x7FFFF7FFU}, /*RSCHKINTENRT00*/ + [271] = {0xFD800504U, 0xFAB58006U}, /*RSCHKINTENRT01*/ + [272] = {0xFD800508U, 0x000013A1U}, /*RSCHKINTENRT02*/ + [273] = {0xFD804500U, 0x000007F8U}, /*RSCHKINTENRT10*/ + [274] = {0xFD808500U, 0x000000FDU}, /*RSCHKINTENRT20*/ + [275] = {0xFD80C500U, 0x00000001U}, /*RSCHKINTENRT30*/ + [276] = {0xFCB30500U, 0xF7F10F1FU}, /*RSCHKINTENPER000*/ + [277] = {0xFCB30504U, 0x000FBCFDU}, /*RSCHKINTENPER001*/ + [278] = {0xFCB34500U, 0x000000FAU}, /*RSCHKINTENPER010*/ + [279] = {0xFCB38500U, 0x00000003U}, /*RSCHKINTENPER020*/ + [280] = {0xFCB3C500U, 0x0000003FU}, /*RSCHKINTENPER030*/ + [281] = {0xFCE90500U, 0x93FF7F7FU}, /*RSCHKINTENHSC0*/ + [282] = {0xFCE90504U, 0x001FE067U}, /*RSCHKINTENHSC1*/ + [283] = {0xFC8F8500U, 0xFEFFC003U}, /*RSCHKINTENVIO00*/ + [284] = {0xFC8F8504U, 0x0801C03FU}, /*RSCHKINTENVIO01*/ + [285] = {0xFC8F0500U, 0xDF793FFFU}, /*RSCHKINTENVIO10*/ + [286] = {0xFC8F0504U, 0x041A001EU}, /*RSCHKINTENVIO11*/ + [287] = {0xFC8FC500U, 0x00000004U}, /*RSCHKINTENVIO20*/ + [288] = {0xFC010500U, 0xFEBB663FU}, /*RSCHKINTENVC00*/ + [289] = {0xFC010504U, 0x0000077FU}, /*RSCHKINTENVC01*/ + [290] = {0xFF8E0500U, 0x3E7FEE0FU}, /*RSCHKINTENIR0*/ + [291] = {0xFF8E0504U, 0x0000FFFFU}, /*RSCHKINTENIR1*/ + [292] = {0xFC2F0500U, 0x0003FDF8U}, /*RSCHKINTENVIP00*/ + [293] = {0xFC2F0504U, 0x000FF000U}, /*RSCHKINTENVIP01*/ + [294] = {0xFC640500U, 0x000001DFU}, /*RSCHKINTEN3DG0*/ + [295] = {0xFC480500U, 0x0001FFFFU}, /*RSCHKINTENDSP0*/ + [296] = {0xFF840540U, 0x0000000EU}, /*TIDINTENTOP00*/ + [297] = {0xFF848540U, 0x00000007U}, /*TIDINTENTOP20*/ + [298] = {0xFDDFC540U, 0x00003FFFU}, /*TIDINTENMM0*/ + [299] = {0xFD800540U, 0x0167CC7CU}, /*TIDINTENRT00*/ + [300] = {0xFD800544U, 0x00000020U}, /*TIDINTENRT01*/ + [301] = {0xFD804540U, 0x00000033U}, /*TIDINTENRT10*/ + [302] = {0xFD808540U, 0x00000036U}, /*TIDINTENRT20*/ + [303] = {0xFCB30540U, 0x0003BF70U}, /*TIDINTENPER000*/ + [304] = {0xFCB34540U, 0x0000000FU}, /*TIDINTENPER010*/ + [305] = {0xFCE90540U, 0x0210247BU}, /*TIDINTENHSC0*/ + [306] = {0xFC8F8540U, 0x1CC0C703U}, /*TIDINTENVIO00*/ + [307] = {0xFC8F8544U, 0x00000003U}, /*TIDINTENVIO01*/ + [308] = {0xFC8F0540U, 0x94000000U}, /*TIDINTENVIO10*/ + [309] = {0xFC8F0544U, 0x0000002AU}, /*TIDINTENVIO11*/ + [310] = {0xFC010540U, 0x3366CD90U}, /*TIDINTENVC00*/ + [311] = {0xFF8E0540U, 0x000C1E60U}, /*TIDINTENIR0*/ + [312] = {0xFC2F0540U, 0x000007EDU}, /*TIDINTENVIP00*/ + [313] = {0xFC640540U, 0x00000011U}, /*TIDINTEN3DG0*/ + [314] = {0xFC480540U, 0x00000000U}, /*TIDINTENDSP0*/ + [315] = {0xFF840640U, 0x00000002U}, /*SAFERRINTENTOP00*/ + [316] = {0xFDA72640U, 0x00000001U}, /*SAFERRINTENTOP10*/ + [317] = {0xFF848640U, 0x00000000U}, /*SAFERRINTENTOP20*/ + [318] = {0xFF844640U, 0x00000001U}, /*SAFERRINTENTOP30*/ + [319] = {0xFDDFC640U, 0x00000007U}, /*SAFERRINTENMM0*/ + [320] = {0xFD800640U, 0x0000001DU}, /*SAFERRINTENRT00*/ + [321] = {0xFD804640U, 0x00000001U}, /*SAFERRINTENRT10*/ + [322] = {0xFD808640U, 0x00000001U}, /*SAFERRINTENRT20*/ + [323] = {0xFD80C640U, 0x00000001U}, /*SAFERRINTENRT30*/ + [324] = {0xFCB30640U, 0x00000004U}, /*SAFERRINTENPER000*/ + [325] = {0xFCB34640U, 0x00000001U}, /*SAFERRINTENPER010*/ + [326] = {0xFCB38640U, 0x00000001U}, /*SAFERRINTENPER020*/ + [327] = {0xFCB3C640U, 0x00000001U}, /*SAFERRINTENPER030*/ + [328] = {0xFCE90640U, 0x00000001U}, /*SAFERRINTENHSC0*/ + [329] = {0xFC8F8640U, 0x00000001U}, /*SAFERRINTENVIO00*/ + [330] = {0xFC8F0640U, 0x00000002U}, /*SAFERRINTENVIO10*/ + [331] = {0xFC8FC640U, 0x00000001U}, /*SAFERRINTENVIO20*/ + [332] = {0xFC010640U, 0x00000001U}, /*SAFERRINTENVC00*/ + [333] = {0xFF8E0640U, 0x00000001U}, /*SAFERRINTENIR0*/ + [334] = {0xFC2F0640U, 0x00000001U}, /*SAFERRINTENVIP00*/ + [335] = {0xFC640640U, 0x00000001U}, /*SAFERRINTEN3DG0*/ + [336] = {0xFC480640U, 0x00000001U}, /*SAFERRINTENDSP0*/ + [337] = {0xFF8404C0U, 0x00000192U}, /*WCRCINTENTOP00*/ + [338] = {0xFDDFC4C0U, 0x07FFBDFFU}, /*WCRCINTENMM0*/ + [339] = {0xFD8004C0U, 0x207F3F3BU}, /*WCRCINTENRT00*/ + [340] = {0xFD8004C4U, 0x00000014U}, /*WCRCINTENRT01*/ + [341] = {0xFD8044C0U, 0x00000783U}, /*WCRCINTENRT10*/ + [342] = {0xFD8084C0U, 0x00000000U}, /*WCRCINTENRT20*/ + [343] = {0xFCB304C0U, 0x000027DFU}, /*WCRCINTENPER000*/ + [344] = {0xFCB344C0U, 0x00000003U}, /*WCRCINTENPER010*/ + [345] = {0xFCE904C0U, 0x000041BBU}, /*WCRCINTENHSC0*/ + [346] = {0xFC8F84C0U, 0x0000C703U}, /*WCRCERRINTENVIO00*/ + [347] = {0xFC8F04C0U, 0x0016840FU}, /*WCRCERRINTENVIO10*/ + [348] = {0xFC0104C0U, 0x00347D59U}, /*WCRCERRINTENVC00*/ + [349] = {0xFF8E04C0U, 0x3FFE03D0U}, /*WCRCERRINTENIR0*/ + [350] = {0xFC2F04C0U, 0x070031FDU}, /*WCRCERRINTENVIP00*/ + [351] = {0xFC6404C0U, 0x00000063U}, /*WCRCERRINTEN3DG0*/ + [352] = {0xFC4804C0U, 0x00007FFFU}, /*WCRCINTENDSP0*/ + [353] = {0xFF840600U, 0x00000002U}, /*SECERRINTENTOP00*/ + [354] = {0xFDA72600U, 0x00000001U}, /*SECERRINTENTOP10*/ + [355] = {0xFF848600U, 0x00000000U}, /*SECERRINTENTOP20*/ + [356] = {0xFF844600U, 0x00000001U}, /*SECERRINTENTOP30*/ + [357] = {0xFDDFC600U, 0x00000007U}, /*SECERRINTENMM0*/ + [358] = {0xFD800600U, 0x0000001DU}, /*SECERRINTENRT00*/ + [359] = {0xFD804600U, 0x00000001U}, /*SECERRINTENRT10*/ + [360] = {0xFD808600U, 0x00000001U}, /*SECERRINTENRT20*/ + [361] = {0xFD80C600U, 0x00000001U}, /*SECERRINTENRT30*/ + [362] = {0xFCB30600U, 0x00000004U}, /*SECERRINTENPER000*/ + [363] = {0xFCB34600U, 0x00000001U}, /*SECERRINTENPER010*/ + [364] = {0xFCB38600U, 0x00000001U}, /*SECERRINTENPER020*/ + [365] = {0xFCB3C600U, 0x00000001U}, /*SECERRINTENPER030*/ + [366] = {0xFCE90600U, 0x00000001U}, /*SECERRINTENHSC0*/ + [367] = {0xFC8F8600U, 0x00000001U}, /*SECERRINTENVIO00*/ + [368] = {0xFC8F0600U, 0x00000002U}, /*SECERRINTENVIO10*/ + [369] = {0xFC8FC600U, 0x00000001U}, /*SECERRINTENVIO20*/ + [370] = {0xFC010600U, 0x00000001U}, /*SECERRINTENVC00*/ + [371] = {0xFF8E0600U, 0x00000001U}, /*SECERRINTENIR0*/ + [372] = {0xFC2F0600U, 0x00000001U}, /*SECERRINTENVIP00*/ + [373] = {0xFC640600U, 0x00000001U}, /*SECERRINTEN3DG0*/ + [374] = {0xFC480600U, 0x00000001U}, /*SECERRINTENDSP0*/ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX] = { + [0] = {0xFC480570U, 0x00000002U}, /* IMRGID_IPMMU_VI0 */ + [1] = {0xFC4C0570U, 0x00000002U}, /* IMRGID_IPMMU_VI1 */ + [2] = {0xFC3C0570U, 0x00000002U}, /* IMRGID_IPMMU_VC0 */ + [3] = {0xFC380570U, 0x00000002U}, /* IMRGID_IPMMU_IR */ + [4] = {0xFC080570U, 0x00000001U}, /* IMRGID_IPMMU_RT0 */ + [5] = {0xFC0C0570U, 0x00000001U}, /* IMRGID_IPMMU_RT1 */ + [6] = {0xFC300570U, 0x00000001U}, /* IMRGID_IPMMU_DS0 */ + [7] = {0xFC340570U, 0x00000001U}, /* IMRGID_IPMMU_HSC */ + [8] = {0xFC500570U, 0x00000002U}, /* IMRGID_IPMMU_VIP0 */ + [9] = {0xFC400570U, 0x00000002U}, /* IMRGID_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX] = { + [0] = {0xFC480578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI0 */ + [1] = {0xFC4C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI1 */ + [2] = {0xFC3C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VC0 */ + [3] = {0xFC380578U, 0x00000001U}, /* IMSECGRP_IPMMU_IR */ + [4] = {0xFC080578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT0 */ + [5] = {0xFC0C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT1 */ + [6] = {0xFC300578U, 0x00000001U}, /* IMSECGRP_IPMMU_DS0 */ + [7] = {0xFC340578U, 0x00000001U}, /* IMSECGRP_IPMMU_HSC */ + [8] = {0xFC500578U, 0x00000001U}, /* IMSECGRP_IPMMU_VIP0 */ + [9] = {0xFC400578U, 0x00000001U}, /* IMSECGRP_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX] = { + [0] = {0xFC480574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI0 */ + [1] = {0xFC4C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI1 */ + [2] = {0xFC3C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VC0 */ + [3] = {0xFC380574U, 0x00000002U}, /* IMRGIDEN_IPMMU_IR */ + [4] = {0xFC080574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT0 */ + [5] = {0xFC0C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT1 */ + [6] = {0xFC300574U, 0x00000002U}, /* IMRGIDEN_IPMMU_DS0 */ + [7] = {0xFC340574U, 0x00000002U}, /* IMRGIDEN_IPMMU_HSC */ + [8] = {0xFC500574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VIP0 */ + [9] = {0xFC400574U, 0x00000002U}, /* IMRGIDEN_IPMMU_3DG */ +}; + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/crc32.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/crc32.c new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/log/log.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/log/log.c new file mode 100644 index 0000000..bf46cab --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/log/log.c @@ -0,0 +1,100 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Log driver + ******************************************************************************/ +/****************************************************************************** + * @file log.c + * - Version : 0.03 + * @brief Log driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 06.01.2022 0.02 Static analysis support + * : 04,04,2023 0.03 Fixed to not use the standard input/output + * library when LOG_LEVEL=0. + *****************************************************************************/ + +#include +#include +#include + +#if LOG_LEVEL >= LOG_ERROR +#include + +#define VSPRINTF_OK (0) + +void local_printf(const char *fmt, ...) +{ + va_list ap; + static char s_buffer[1024]; + int32_t num; + uint32_t loop; + + /* Convert all arguments to one string */ + va_start(ap, fmt); + num = vsprintf(s_buffer, fmt, ap); + va_end(ap); + + /* String output */ + if (VSPRINTF_OK <= num) + { + for (loop = 0U; loop < num; loop++) + { + (void)console_putc((uint8_t)s_buffer[loop]); + /* If the outputted character is LF, output CR */ + if (s_buffer[loop] == 0x0A) /* \n */ + { + (void)console_putc((uint8_t)'\r'); + } + } + } + else + { + while(1) + { + /* loop due to error detection. */ + } + } +} +/* End of function local_printf(const char *fmt, ...) */ +#endif + +void panic_printf(const char *str) +{ + const uint8_t *p = (const uint8_t *)str; + + /* Output one character at a time until the data in the argument is null-terminated string. */ + while(*p != (uint8_t)'\0') + { + (void)console_putc(*p); + p++; + } + /* output character is CR and LF */ + (void)console_putc((uint8_t)'\r'); + (void)console_putc((uint8_t)'\n'); +} +/* End of function panic_printf(const char *str) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/log/scif.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/log/scif.c new file mode 100644 index 0000000..b2f285e --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/log/scif.c @@ -0,0 +1,625 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : SCIF driver + ******************************************************************************/ +/****************************************************************************** + * @file scif.c + * - Version : 0.08 + * @brief 1. Initial setting of SCIF. + * 2. Initial setting of HSCIF. + * 3. Log output function. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Modify the timing of MODEMR judgement. + * : 15.10.2021 0.03 Modify register access to read modify write. + * : 03.12.2021 0.04 Fix incorrect configuration process. + * : 06.01.2022 0.05 Static analysis support + * : 23.05.2022 0.06 Integration of S4 and V4H + * : 20.12.2022 0.07 Modify writing bit size to SCBRR register. + * : 21.08.2023 0.08 Add support for V4M. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Define */ +#define SCIF_SCSCR_TE_EN (uint16_t)((uint16_t)1U << 5U) +#define SCIF_SCSCR_RE_EN (uint16_t)((uint16_t)1U << 4U) +#define SCIF_SCSCR_CKE_EXT_CLK (uint16_t)((uint16_t)2U << 0U) +#define SCIF_SCSCR_INIT_DATA (uint16_t)(SCIF_SCSCR_TE_EN | SCIF_SCSCR_RE_EN) +#define SCIF_SCSCR_HW_INIT (uint16_t)(0x0000U) + +#define SCIF_SCFCR_TFRST_EN (uint16_t)((uint16_t)1U << 2U) +#define SCIF_SCFCR_RFRS_EN (uint16_t)((uint16_t)1U << 1U) +#define SCIF_SCFCR_RESET_FIFO (uint16_t)(SCIF_SCFCR_TFRST_EN | SCIF_SCFCR_RFRS_EN) + +#define SCIF_SCFSR_TEND (uint16_t)((uint16_t)1U << 6U) +#define SCIF_SCFSR_TDFE (uint16_t)((uint16_t)1U << 5U) +#define TRANS_END_CHECK (uint16_t)(SCIF_SCFSR_TEND | SCIF_SCFSR_TDFE) +#define SCIF_SCFSR_INIT_DATA (uint16_t)(0x0000U) + +#define SCIF_SCLSR_INIT_DATA (uint16_t)(0x0000U) + +#define SCIF_SCSMR_CHR (uint16_t)((uint16_t)1U << 6U) +#define SCIF_SCSMR_PE (uint16_t)((uint16_t)1U << 5U) +#define SCIF_SCSMR_STOP (uint16_t)((uint16_t)1U << 3U) +#define SCIF_SCSMR_CKS (uint16_t)((uint16_t)3U << 0U) +#define SCIF_SCSMR_INIT_DATA ~((uint16_t)(SCIF_SCSMR_CHR | SCIF_SCSMR_PE | SCIF_SCSMR_STOP | SCIF_SCSMR_CKS)) + +/* Pclk(66MHz)/1, 115.2kbps*/ +/* N = 66/(66/2*115200)*10^4-1 =17=> 0x11 */ +#define SCIF_SCBRR_115200BPS (uint8_t)(0x11U) +/* Pclk(266MHz)/1, 921.6kbps*/ +/* N = 266/(8*2*921600)*10^6-1 =17=> 0x11 */ +#define HSCIF_SCBRR_921600BPS (uint8_t)(0x11U) +/* Pclk(266MHz)/1, 1.8432Mbps*/ +/* N = 266/(8*2*1843200)*10^6-1 =8=> 0x08 */ +#define HSCIF_SCBRR_1843200BPS (uint8_t)(0x08U) + +#define HSCIF_HSSRR_SRE (uint16_t)(1U << 15U) +#define HSCIF_HSSRR_SRCYC (uint16_t)(0x1FU << 0U) +#define HSCIF_HSSRR_SRCYC8 (uint16_t)(7U << 0U) /* Sampling rate 8-1 */ +#define HSCIF_HSSRR_VAL (uint16_t)(HSCIF_HSSRR_SRE | HSCIF_HSSRR_SRCYC8) + +#define HSCIF_DL_DIV1 (uint16_t)(1U << 0U) +#define HSCIF_CKS_CKS (uint16_t)(1U << 15U) +#define HSCIF_CKS_XIN (uint16_t)(1U << 14U) +#define HSCIF_CKS_SC_CLK_EXT ~((uint16_t)(HSCIF_CKS_CKS | HSCIF_CKS_XIN)) + +/* module start setting value */ +#if (RCAR_LSI == RCAR_S4) +#define CPG_MSTPCR_HSCIF (((uint32_t)1U) << 14U) +#define CPG_MSTPCR_SCIF (((uint32_t)1U) << 4U) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define CPG_MSTPCR_HSCIF (((uint32_t)1U) << 14U) +#define CPG_MSTPCR_SCIF (((uint32_t)1U) << 2U) +#endif /* RCAR_LSI == RCAR_S4 */ + +/* Pin function setting value */ +#if (RCAR_LSI == RCAR_S4) +#define GPSR_TX ((uint32_t)1U << 3U) /* HTX0 / TX3 */ +#define GPSR_RX ((uint32_t)1U << 2U) /* HRX0 / RX3 */ +#define IPSR_RX_VAL ((uint32_t)1U << 8U) /* RX3 */ +#define IPSR_TX_VAL ((uint32_t)1U << 12U) /* TX3 */ +#define POC_TX_33V ((uint32_t)1U << 3U) /* HTX0 / TX3 3.3V setting value */ +#define POC_RX_33V ((uint32_t)1U << 2U) /* HRX0 / RX3 3.3V setting value */ +#define IPSR_RX_MASK ((uint32_t)0xFU << 8U) /* IPSR bit[11:8] */ +#define IPSR_TX_MASK ((uint32_t)0xFU << 12U) /* IPSR bit[15:12] */ +#define PFC_GPSR_SCIF_MASK (uint32_t)(0x0000000CU) /* SCIF3/HSCIF0 RX/TX */ +#define PFC_GPSR_SCIF_VAL (uint32_t)(GPSR_TX | GPSR_RX) /* SCIF3/HSCIF0 RX/TX */ +#define PFC_IPSR_SCIF_MASK (uint32_t)(IPSR_RX_MASK | IPSR_TX_MASK) /* Mask value of IPSR (SCIF3/HSCIF0 RX/TX) */ +#define PFC_IPSR_SCIF_VAL (uint32_t)(IPSR_RX_VAL | IPSR_TX_VAL) /* SCIF3 RX/TX */ +#define PFC_IPSR_HSCIF_VAL (uint32_t)(0x00000000U) /* HSCIF0 RX/TX */ +#define PFC_POC_SCIF_MASK (uint32_t)(0x0000000CU) /* SCIF3/HSCIF0 RX/TX */ +#define PFC_POC_SCIF_33V (uint32_t)(POC_TX_33V | POC_RX_33V) /* SCIF3/HSCIF0 RX/TX */ +#define PFC_IPSR_SCIF_EXTCLK_MASK (uint32_t)(0xFU << 0U) /* Mask value of IPSR (External Clock) */ +#define PFC_IPSR_SCIF_EXTCLK_VAL (uint32_t)(0x0U << 0U) /* IPSR (External Clock) */ +#define PFC_GPSR_SCIF_EXTCLK_MASK (uint32_t)(0x00000001U) /* Mask value of IPSR (External Clock) */ +#define PFC_GPSR_SCIF_EXTCLK_VAL (uint32_t)(1U << 0U) /* IPSR (External Clock) */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define GPSR_TX ((uint32_t)1U << 12U) /* HTX0 / TX0 */ +#define GPSR_RX ((uint32_t)1U << 16U) /* HRX0 / RX0 */ +#define IPSR_RX_VAL ((uint32_t)1U << 0U) /* RX0 */ +#define IPSR_TX_VAL ((uint32_t)1U << 16U) /* TX0 */ +#define POC_TX_33V ((uint32_t)1U << 12U) /* HTX0 / TX0 3.3V setting value */ +#define POC_RX_33V ((uint32_t)1U << 16U) /* HRX0 / RX0 3.3V setting value */ +#define POC_TX_18V ((uint32_t)0U << 12U) /* HTX0 / TX0 1.8V setting value */ +#define POC_RX_18V ((uint32_t)0U << 16U) /* HRX0 / RX0 1.8V setting value */ +#define IPSR_RX_MASK ((uint32_t)0xFU << 0U) /* IPSR bit[3:0] */ +#define IPSR_TX_MASK ((uint32_t)0xFU << 16U) /* IPSR bit[19:16] */ +#define PFC_GPSR_SCIF_MASK (uint32_t)(0x00011000U) /* SCIF0/HSCIF0 RX/TX */ +#define PFC_GPSR_SCIF_VAL (uint32_t)(GPSR_TX | GPSR_RX) /* SCIF0/HSCIF0 RX/TX */ +#define PFC_IPSR_SCIF_MASK1 (uint32_t)(IPSR_TX_MASK) /* Mask value of IPSR (SCIF0/HSCIF0 TX) */ +#define PFC_IPSR_SCIF_VAL1 (uint32_t)(IPSR_TX_VAL) /* SCIF0 TX */ +#define PFC_IPSR_SCIF_MASK2 (uint32_t)(IPSR_RX_MASK) /* Mask value of IPSR (SCIF3/HSCIF0 RX) */ +#define PFC_IPSR_SCIF_VAL2 (uint32_t)(IPSR_RX_VAL) /* SCIF0 RX */ +#define PFC_IPSR_HSCIF_VAL1 (uint32_t)(0x00000000U) /* HSCIF0 TX */ +#define PFC_IPSR_HSCIF_VAL2 (uint32_t)(0x00000000U) /* HSCIF0 RX */ +#define PFC_POC_SCIF_MASK (uint32_t)(0x00011000U) /* SCIF0/HSCIF0 RX/TX */ +#define PFC_POC_SCIF_33V (uint32_t)(POC_TX_33V | POC_RX_33V) /* SCIF0/HSCIF0 RX/TX */ +#define PFC_IPSR_SCIF_EXTCLK_MASK (uint32_t)(0xFU << 4U) /* Mask value of IPSR (External Clock) */ +#define PFC_IPSR_SCIF_EXTCLK_VAL (uint32_t)(0x0U << 4U) /* IPSR (External Clock) */ +#define PFC_GPSR_SCIF_EXTCLK_MASK (uint32_t)(0x00020000U) /* Mask value of IPSR (External Clock) */ +#endif /* RCAR_LSI == RCAR_S4 */ + +static void (*rcar_putc)(uint8_t outchar); + +static void scif_module_start(uint32_t modemr); +static void scif_pfc_init(uint32_t modemr); +static void scif_console_init(uint32_t modemr); +static void scif_console_putc(uint8_t outchar); +static void hscif_console_putc(uint8_t outchar); + + +static void scif_module_start(uint32_t modemr) +{ + uint32_t reg; + + if(modemr == MODEMR_SCIF_DLMODE) + { + reg = mem_read32(CPG_MSTPSR7D0); + /* If supply of clock to SCIF0 is stopped */ + if (FALSE != (CPG_MSTPCR_SCIF & reg)) + { + /* Supply of clock to SCIF0 is start */ + reg &= ~(CPG_MSTPCR_SCIF); + cpg_reg_write(CPG_MSTPCR7D0, CPG_MSTPSR7D0, reg); + } + } + else + { + reg = mem_read32(CPG_MSTPSR5D0); + /* If supply of clock to SCIF0 is stopped */ + if (FALSE != (CPG_MSTPCR_HSCIF & reg)) + { + /* Supply of clock to SCIF0 is start */ + reg &= ~(CPG_MSTPCR_HSCIF); + cpg_reg_write(CPG_MSTPCR5D0, CPG_MSTPSR5D0, reg); + } + } +} +/* End of function scif_module_start(void) */ + +static void scif_pfc_init(uint32_t modemr) +{ + uint32_t reg; + +#if (RCAR_LSI == RCAR_S4) + if(modemr == MODEMR_SCIF_DLMODE) + { + /* Set RX / TX of SCIF 0. */ + reg = mem_read32(PFC_IP0SR0_RW); + reg &= (~(PFC_IPSR_SCIF_MASK)); + reg |= PFC_IPSR_SCIF_VAL; + pfc_reg_write(PFC_IP0SR0_RW, reg); + + /* Set Voltage setting of 1.8V. */ + reg = mem_read32(PFC_POC0_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + pfc_reg_write(PFC_POC0_RW, reg); + } + else if(modemr == MODEMR_HSCIF_DLMODE_921600) + { + /* Set HRX / HTX of HSCIF 0. */ + reg = mem_read32(PFC_IP0SR0_RW); + reg &= (~(PFC_IPSR_SCIF_MASK)); + reg |= PFC_IPSR_HSCIF_VAL; + pfc_reg_write(PFC_IP0SR0_RW, reg); + + /* Set Voltage setting of 3.3V. */ + reg = mem_read32(PFC_POC0_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + reg |= PFC_POC_SCIF_33V; + pfc_reg_write(PFC_POC0_RW, reg); + } + else if(modemr == MODEMR_HSCIF_DLMODE_1843200) + { + /* Set HRX / HTX of HSCIF 0. */ + reg = mem_read32(PFC_IP0SR0_RW); + reg &= (~(PFC_IPSR_SCIF_MASK)); + reg |= PFC_IPSR_HSCIF_VAL; + pfc_reg_write(PFC_IP0SR0_RW, reg); + + /* Set Voltage setting of 1.8V. */ + reg = mem_read32(PFC_POC0_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + pfc_reg_write(PFC_POC0_RW, reg); + } + else if(modemr == MODEMR_HSCIF_DLMODE_3000000) + { + /* Set HRX / HTX of HSCIF 0. */ + reg = mem_read32(PFC_IP0SR0_RW); + reg &= (~(PFC_IPSR_SCIF_MASK)); + reg |= PFC_IPSR_HSCIF_VAL; + pfc_reg_write(PFC_IP0SR0_RW, reg); + + /* Set Voltage setting of 1.8V. */ + reg = mem_read32(PFC_POC0_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + pfc_reg_write(PFC_POC0_RW, reg); + + /* Set External Clock. */ + reg = mem_read32(PFC_IP0SR0_RW); + reg &= (~(PFC_IPSR_SCIF_EXTCLK_MASK)); + reg |= PFC_IPSR_SCIF_EXTCLK_VAL; + pfc_reg_write(PFC_IP0SR0_RW, reg); + + reg = mem_read32(PFC_GPSR0_RW); + reg &= (~(PFC_GPSR_SCIF_EXTCLK_MASK)); + reg |= PFC_GPSR_SCIF_EXTCLK_MASK; + pfc_reg_write(PFC_GPSR0_RW, reg); + } + else + { + /* no process */ + } + + reg = mem_read32(PFC_GPSR0_RW); + reg &= (~(PFC_GPSR_SCIF_MASK)); + reg |= PFC_GPSR_SCIF_VAL; + pfc_reg_write(PFC_GPSR0_RW, reg); + +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + if(modemr == MODEMR_SCIF_DLMODE) + { + /* Set TX of SCIF 0. */ + reg = mem_read32(PFC_IP1SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK1)); + reg |= PFC_IPSR_SCIF_VAL1; + pfc_reg_write(PFC_IP1SR1_RW, reg); + + /* Set RX of SCIF 0. */ + reg = mem_read32(PFC_IP2SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK2)); + reg |= PFC_IPSR_SCIF_VAL2; + pfc_reg_write(PFC_IP2SR1_RW, reg); + + /* Set Voltage setting of 1.8V. */ + reg = mem_read32(PFC_POC1_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + pfc_reg_write(PFC_POC1_RW, reg); + } + else if(modemr == MODEMR_HSCIF_DLMODE_921600) + { + /* Set HTX of HSCIF 0. */ + reg = mem_read32(PFC_IP1SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK1)); + reg |= PFC_IPSR_HSCIF_VAL1; + pfc_reg_write(PFC_IP1SR1_RW, reg); + + /* Set HRX of HSCIF 0. */ + reg = mem_read32(PFC_IP2SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK2)); + reg |= PFC_IPSR_HSCIF_VAL2; + pfc_reg_write(PFC_IP2SR1_RW, reg); + + /* Set Voltage setting of 3.3V. */ + reg = mem_read32(PFC_POC1_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + reg |= PFC_POC_SCIF_33V; + pfc_reg_write(PFC_POC1_RW, reg); + } + else if(modemr == MODEMR_HSCIF_DLMODE_1843200) + { + /* Set HTX of HSCIF 0. */ + reg = mem_read32(PFC_IP1SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK1)); + reg |= PFC_IPSR_HSCIF_VAL1; + pfc_reg_write(PFC_IP1SR1_RW, reg); + + /* Set HRX of HSCIF 0. */ + reg = mem_read32(PFC_IP2SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK2)); + reg |= PFC_IPSR_HSCIF_VAL2; + pfc_reg_write(PFC_IP2SR1_RW, reg); + + /* Set Voltage setting of 1.8V. */ + reg = mem_read32(PFC_POC1_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + pfc_reg_write(PFC_POC1_RW, reg); + } + else if(modemr == MODEMR_HSCIF_DLMODE_3000000) + { + /* Set HTX of HSCIF 0. */ + reg = mem_read32(PFC_IP1SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK1)); + reg |= PFC_IPSR_HSCIF_VAL1; + pfc_reg_write(PFC_IP1SR1_RW, reg); + + /* Set HRX of HSCIF 0. */ + reg = mem_read32(PFC_IP2SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK2)); + reg |= PFC_IPSR_HSCIF_VAL2; + pfc_reg_write(PFC_IP2SR1_RW, reg); + + /* Set Voltage setting of 1.8V. */ + reg = mem_read32(PFC_POC1_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + pfc_reg_write(PFC_POC1_RW, reg); + + /* Set External Clock. */ + reg = mem_read32(PFC_IP2SR1_RW); + reg &= (~(PFC_IPSR_SCIF_EXTCLK_MASK)); + reg |= PFC_IPSR_SCIF_EXTCLK_VAL; + pfc_reg_write(PFC_IP2SR1_RW, reg); + + reg = mem_read32(PFC_GPSR1_RW); + reg &= (~(PFC_GPSR_SCIF_EXTCLK_MASK)); + reg |= PFC_GPSR_SCIF_EXTCLK_MASK; + pfc_reg_write(PFC_GPSR1_RW, reg); + } + else + { + /* no process */ + } + + reg = mem_read32(PFC_GPSR1_RW); + reg &= (~(PFC_GPSR_SCIF_MASK)); + reg |= PFC_GPSR_SCIF_VAL; + pfc_reg_write(PFC_GPSR1_RW, reg); +#endif /* RCAR_LSI == RCAR_S4 */ +} +/* End of function scif_pfc_init(void) */ + +static void scif_console_init(uint32_t modemr) +{ + uint16_t reg; + switch(modemr) + { + case MODEMR_HSCIF_DLMODE_3000000: + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + reg = mem_read16(HSCIF_HSFCR); + reg |= SCIF_SCFCR_RESET_FIFO; + mem_write16(HSCIF_HSFCR, reg); + + /* clear ORER bit */ + mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA); + + /* external clock, SC_CLK pin used for output pin */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_CKE_EXT_CLK); + /* 8bit data, no-parity, 1 stop, Po/1 */ + reg = mem_read16(HSCIF_HSSMR); + reg &= SCIF_SCSMR_INIT_DATA; + mem_write16(HSCIF_HSSMR, reg); + + /* 24MHz / (3000000 * 8) = 1 */ + mem_write16(HSCIF_DL, HSCIF_DL_DIV1); + reg = mem_read16(HSCIF_CKS); + reg &= HSCIF_CKS_SC_CLK_EXT; + mem_write16(HSCIF_CKS, reg); + /* Sampling rate 8 */ + reg = mem_read16(HSCIF_HSSRR); + reg &= ~(HSCIF_HSSRR_SRE | HSCIF_HSSRR_SRCYC); + reg |= HSCIF_HSSRR_VAL; + mem_write16(HSCIF_HSSRR, reg); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + reg = mem_read16(HSCIF_HSFCR); + reg &= ~(SCIF_SCFCR_RESET_FIFO); + mem_write16(HSCIF_HSFCR, reg); + /* enable TE, RE; SC_CLK=external */ + reg = mem_read16(HSCIF_HSSCR); + reg |= SCIF_SCSCR_INIT_DATA; + mem_write16(HSCIF_HSSCR, reg); + + /* Set the pointer to a function that outputs one character. */ + rcar_putc = hscif_console_putc; + break; + } + case MODEMR_HSCIF_DLMODE_1843200: + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + reg = mem_read16(HSCIF_HSFCR); + reg |= SCIF_SCFCR_RESET_FIFO; + mem_write16(HSCIF_HSFCR, reg); + + /* clear ORER bit */ + mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA); + + /* internal clock, SC_CLK pin unused for output pin */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* 8bit data, no-parity, 1 stop, Po/1 */ + reg = mem_read16(HSCIF_HSSMR); + reg &= SCIF_SCSMR_INIT_DATA; + mem_write16(HSCIF_HSSMR, reg); + + /* Sampling rate 8 */ + mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL); + /* Baud rate 1843200bps*/ + mem_write8(HSCIF_HSBRR, HSCIF_SCBRR_1843200BPS); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + reg = mem_read16(HSCIF_HSFCR); + reg &= ~(SCIF_SCFCR_RESET_FIFO); + mem_write16(HSCIF_HSFCR, reg); + /* enable TE, RE; SC_CLK=external */ + reg = mem_read16(HSCIF_HSSCR); + reg |= SCIF_SCSCR_INIT_DATA; + mem_write16(HSCIF_HSSCR, reg); + + /* Set the pointer to a function that outputs one character. */ + rcar_putc = hscif_console_putc; + break; + } + case MODEMR_HSCIF_DLMODE_921600: + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + reg = mem_read16(HSCIF_HSFCR); + reg |= SCIF_SCFCR_RESET_FIFO; + mem_write16(HSCIF_HSFCR, reg); + + /* clear ORER bit */ + mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA); + + /* internal clock, SC_CLK pin unused for output pin */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* 8bit data, no-parity, 1 stop, Po/1 */ + reg = mem_read16(HSCIF_HSSMR); + reg &= SCIF_SCSMR_INIT_DATA; + mem_write16(HSCIF_HSSMR, reg); + + /* Sampling rate 8 */ + mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL); + /* Baud rate 921600bps*/ + mem_write8(HSCIF_HSBRR, HSCIF_SCBRR_921600BPS); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + reg = mem_read16(HSCIF_HSFCR); + reg &= ~(SCIF_SCFCR_RESET_FIFO); + mem_write16(HSCIF_HSFCR, reg); + /* enable TE, RE; SC_CLK=external */ + reg = mem_read16(HSCIF_HSSCR); + reg |= SCIF_SCSCR_INIT_DATA; + mem_write16(HSCIF_HSSCR, reg); + + /* Set the pointer to a function that outputs one character. */ + rcar_putc = hscif_console_putc; + break; + } + case MODEMR_SCIF_DLMODE: + default: + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + reg = mem_read16(SCIF_SCFCR); + reg |= SCIF_SCFCR_RESET_FIFO; + mem_write16(SCIF_SCFCR, reg); + + /* clear ORER bit */ + mem_write16(SCIF_SCLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(SCIF_SCFSR, SCIF_SCFSR_INIT_DATA); + + /* internal clock, SC_CLK pin unused for output pin */ + mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT); + /* 8bit data, no-parity, 1 stop, Po/1 */ + reg = mem_read16(SCIF_SCSMR); + reg &= SCIF_SCSMR_INIT_DATA; + mem_write16(SCIF_SCSMR, reg); + + /* Baud rate 115200bps*/ + mem_write8(SCIF_SCBRR, SCIF_SCBRR_115200BPS); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + reg = mem_read16(SCIF_SCFCR); + reg &= ~(SCIF_SCFCR_RESET_FIFO); + mem_write16(SCIF_SCFCR, reg); + /* enable TE, RE; SC_CLK=no output */ + reg = mem_read16(SCIF_SCSCR); + reg |= SCIF_SCSCR_INIT_DATA; + mem_write16(SCIF_SCSCR, reg); + + /* Set the pointer to a function that outputs one character. */ + rcar_putc = scif_console_putc; + break; + } + } +} +/* End of function scif_console_init(void) */ + +#define _MODE31 (BASE_RTSRAM_ADDR + 0x0002FFF0) +#define _MODE_115200 0x00115200 +void scif_init(void) +{ + uint32_t modemr; + +#ifdef FORCE_115200 /* force to serial speed to 115200 bps */ + /* Gen4_ICUMX_loader(0xEB22FFF0) at RT-VRAM */ + modemr = MODEMR_SCIF_DLMODE; + mem_write32(_MODE31, _MODE_115200); +#else + modemr = ((mem_read32(RST_MODEMR0) & RST_MODEMR0_MD31) >> 31U); + modemr |= ((mem_read32(RST_MODEMR1) & RST_MODEMR1_MD32) << 1U); +#endif + scif_module_start(modemr); + scif_pfc_init(modemr); + scif_console_init(modemr); +} +/* End of function scif_init(void) */ + +void console_putc(uint8_t outchar) +{ + rcar_putc(outchar); +} +/* End of function console_putc(void) */ + + +static void scif_console_putc(uint8_t outchar) +{ + uint16_t reg; + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK)) + { + ; + } + + mem_write8(SCIF_SCFTDR, outchar); /* Transfer one character */ + reg = mem_read16(SCIF_SCFSR); + reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */ + mem_write16(SCIF_SCFSR, reg); + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK)) + { + ; + } +} +/* End of function scif_console_putc(uint8_t outchar) */ + +static void hscif_console_putc(uint8_t outchar) +{ + uint16_t reg; + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK)) + { + ; + } + + mem_write8(HSCIF_HSFTDR, outchar); /* Transfer one character */ + reg = mem_read16(HSCIF_HSFSR); + reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */ + mem_write16(HSCIF_HSFSR, reg); + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK)) + { + ; + } +} +/* End of function hscif_console_putc(uint8_t outchar) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/scmt_checkpoint.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/scmt_checkpoint.c new file mode 100644 index 0000000..e802a4a --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/scmt_checkpoint.c @@ -0,0 +1,126 @@ + +#include +#include /* NULL pointer */ +#include + +#include "scmt.h" +#include "scmt_config.h" +#include "scmt_checkpoint.h" + +#if PRINT_INFO + #include /* Access to mode pin register */ + #include /* Access to mode pin register */ +#endif /* PRINT_INFO */ + + +#define xstr(a) str(a) +#define str(a) #a + +/* Structure to hold the log data. */ +typedef struct { + uint32_t counter; /* Value of SCMT counter */ + char * note; /* String is stored as pointer! Pointer must be valid during runtime! */ + uint32_t data; /* Arbitrary data to add to log */ +} checkpoint_t; +checkpoint_t time_checkpoints[TIME_CHECKPOINTS_MAX]; + +/* If SCMT has a start value other than zero, we'll keep two slots free to inform the user about the offset within the print function */ +#if (SCMT_START_VALUE == 0) +uint32_t time_checkpoints_index = 0; +#else +uint32_t time_checkpoints_index = 2; +#endif + +/* Store a checkpoint: Fetch current counter value and store it together with a pointer to a static string as well as arbitrary data */ +void store_time_checkpoint(char * note, uint32_t data) +{ + if (time_checkpoints_index < TIME_CHECKPOINTS_MAX) { + time_checkpoints[time_checkpoints_index].counter = scmt_module_read(); + time_checkpoints[time_checkpoints_index].note = note; + time_checkpoints[time_checkpoints_index].data = data; + } + time_checkpoints_index++; +} + + +#if (0 == (MEASURE_TIME_NOPRINT)) +/* Print checkpoints */ +void print_time_checkpoints(void) +{ + uint32_t i; + + {PRINTFN(MODULE"=================\r\n");} + +#if PRINT_INFO + /* First, provide some information about the environment */ + {PRINTFN(MODULE"MODEMR[1:0]: 0x%x 0x%x\r\n", mem_read32(RST_MODEMR1), mem_read32(RST_MODEMR0) );} + + {PRINTFN(MODULE"Timer: '" xstr(TIMER_FUNC) "'\r\n");} + {PRINTFN(MODULE"- freq: %.3f kHz\r\n", (TIMER_FREQ)/1000.0f);} + {PRINTFN(MODULE"- resolution: 1 tick = %.4f ms\r\n", 1000.0/(TIMER_FREQ));} +#endif /* PRINT_INFO */ + + /* In case of unsufficient storage for checkpoints, inform about it */ + if (time_checkpoints_index >= TIME_CHECKPOINTS_MAX) { + {PRINTFN(MODULE"Internal number of checkpoints exceeded reserved space: %i of %i\r\n", time_checkpoints_index, TIME_CHECKPOINTS_MAX);} + } + + /* In case of non-zero SCMT start value, inform about it */ + #if (SCMT_START_VALUE != 0) + time_checkpoints[0].counter = 0; + time_checkpoints[0].note = "Reset Release!"; + time_checkpoints[1].counter = SCMT_START_VALUE; + time_checkpoints[1].note = "Timer started here with manual offset relative to reset release!"; + #endif + + /* Print log in CSV style */ + {PRINTFN(MODULE"CSV; timer_ticks; total_time[ms]; delta_time[ms]; data; comment\r\n" );} + for (i=0; i0) { + ms_delta = ms - time_checkpoints[i-1].counter*1000.0/(TIMER_FREQ); + } + + // ==> "E:ICUMX:CP: 364; 2.77; 2.77; 0; init_done" + {PRINTFN(MODULE"CP; %u; %f; %f; %u; %s\r\n", time_checkpoints[i].counter, ms, ms_delta, time_checkpoints[i].data, time_checkpoints[i].note );} +#else + {PRINTFN(MODULE"CP; %u; --; --; %u; %s\r\n", time_checkpoints[i].counter, time_checkpoints[i].data, time_checkpoints[i].note );} +#endif + + } + + /* Timer verification. + Sample calculation: + SCIF is running with 921600 Baud. 8N1 => 0.0108 ms / bit. + Sending 20 characters should take 28 timer ticks of SCMT + As SCIF has a 16-stage FIFO, send at least 16 characters before start of measurements */ +#if 0 != TIMER_TEST_VS_BAUD + { + uint32_t start = 0, stop = 0; + const char teststr[] = "ExecutingTimerTestExecutingTimerTestExecutingTimerTest!\r\n"; /* 57 characters */ + const float charrate = (TIMER_TEST_VS_BAUD)/10.0; /* 8N1: 10 cycles per character */ + const float expected_ms = sizeof(teststr)*1000.0/(charrate); + float measured_ms; + + {PRINTFN(MODULE"=================\r\n");} + {PRINTFN(MODULE"FillingFifoForTimerTestFillingFifoForTimerTest - ");} + start = (TIMER_FUNC)(); + {local_printf(teststr);} + stop = (TIMER_FUNC)(); + measured_ms = (stop-start)*1000.0/(TIMER_FREQ); + + {PRINTFN(MODULE"(Printing the test took %5i ticks / %7.2f ms / expected: %7.2f ms - %s)\r\n", stop-start, measured_ms, expected_ms, ((measured_ms/expected_ms < 1.3) && (measured_ms/expected_ms > 0.9))?"OK":"ERROR");} + } +#endif /* TIMER_TEST_VS_BAUD */ + {PRINTFN(MODULE"=================\r\n");} + +} +#else //(MEASURE_TIME_NOPRINT) == 0 +void print_time_checkpoints(void) {} +#endif //(MEASURE_TIME_NOPRINT) == 0 + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/timer/micro_wait.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/timer/micro_wait.c new file mode 100644 index 0000000..8aaaff5 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/timer/micro_wait.c @@ -0,0 +1,109 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Time wait driver + ******************************************************************************/ +/****************************************************************************** + * @file micro_wait.c + * - Version : 0.03 + * @brief Wait of micro second + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 15.10.2021 0.02 modify register access to read modify write. + * : 03.12.2021 0.03 fix incorrect configuration process. + *****************************************************************************/ + +#include +#include +#include + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + +#define INTICUOSTM0 (0xFFFEEA14U) +#define INTCR_RF ((uint16_t)1U << 12U) +#define INTCR_RF_NO_REQ ((uint16_t)0U << 12U) + +#define OSTM0_BASE (0xFFFEE000U) +#define OSTM0CMP (OSTM0_BASE) +#define OSTM0TS (OSTM0_BASE + 0x0014U) +#define OSTM0TT (OSTM0_BASE + 0x0018U) +#define OSTM0CTL (OSTM0_BASE + 0x0020U) + +#define OSTM0TS_TS (uint8_t)(0x01U) /* b0:1: Start */ +#define OSTM0TT_TT (uint8_t)(0x01U) /* b0:1: Stop */ +#define OSTM0CMP_MICRO_VALUE (0x00000190U) /* PCLK=400MHz(400=0x190 = 1us) */ + +#define OSTM0CTL_MD10 (uint8_t)(0x02U) /* b1:1: Free-run compare mode(Start:0 Counting Direction:up) */ + /* b0:0: Interrupts when counting starts are enabled */ + +#define MAX_MICRO_WAIT (10737418U) /* 0xFFFFFFFF / 400 */ + +void micro_wait(uint32_t count_us) +{ + uint32_t val; + uint16_t reg16; + uint8_t reg8; + + if (count_us != 0U) + { + /* When the timer count is an argument that exceeds 0xFFFFFFFF */ + if(MAX_MICRO_WAIT < count_us) + { + count_us = MAX_MICRO_WAIT; + } + val = count_us * OSTM0CMP_MICRO_VALUE; + /* timer start */ + reg8 = mem_read8(OSTM0TT); + reg8 |= OSTM0TT_TT; + mem_write8(OSTM0TT, reg8); + mem_write32(OSTM0CMP, val); + reg8 = mem_read8(OSTM0CTL); + reg8 |= OSTM0CTL_MD10; + mem_write8(OSTM0CTL, reg8); + reg8 = mem_read8(OSTM0TS); + reg8 |= OSTM0TS_TS; + mem_write8(OSTM0TS, reg8); + + while (1) + { + reg16 = mem_read16(INTICUOSTM0); + if ((reg16 & (INTCR_RF)) != INTCR_RF_NO_REQ) + { + /* timer stop */ + reg16 = (reg16 & (uint16_t)(~(INTCR_RF))); + mem_write16(INTICUOSTM0, reg16); + reg8 = mem_read8(OSTM0TT); + reg8 |= OSTM0TT_TT; + mem_write8(OSTM0TT, reg8); + break; + } + } + } +} +/* End of function micro_wait(uint32_t count_us) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/timer/scmt.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/timer/scmt.c new file mode 100644 index 0000000..d0823b3 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/common/timer/scmt.c @@ -0,0 +1,108 @@ + +#include +#include +#include +#include +#include + +#if SCMT_DEBUG + #include +#endif /* SCMT_DEBUG */ + +#if SCMT_TOGGLE_GPIO + #include +void gpio_set(void) +{ + /* V4H: SCL3_V::Pin AK5::GP8_06 + GPIO Group 8 Base: H’E606 8000 + INOUTSELn +0x184 (set pin to output mode) + OUTDTn +0x188 (set pin output value) + */ + pfc_reg_write(PFC_INOUTSEL8_RW, 1<<6); /* Set GP8_06 to output mode */ + pfc_reg_write(PFC_OUTDT8_RW, 1<<6); /* Set GP8_06 to 'high' */ +} +static int gpio_reset_cnt = 3; +void gpio_clear(void) +{ + if (gpio_reset_cnt>0) { + gpio_reset_cnt--; + } + else + { + pfc_reg_write(PFC_OUTDT8_RW, 0); /* Set GP8_06 to 'low' */ + } + +} +#endif /* SCMT_TOGGLE_GPIO */ + +void scmt_module_start(void) +{ + /* For boot time measurement, signal start of SCMT by GPIO pin toggle */ + #if SCMT_TOGGLE_GPIO + gpio_set(); + #endif /* SCMT_TOGGLE_GPIO */ + + /* If you have issues with the code getting stuck or reading zero from the timer, + you can debug the init seqence with SCMT_DEBUG. + Just make sure that printing debug data is already possible. */ + #if SCMT_DEBUG + PRINTFN("SCMT A\n"); + #endif /* SCMT_DEBUG */ + #if SCMT_INIT + mem_write32(SCMT_CMSCNT,(SCMT_START_VALUE)); /* Set counter value to zero */ + #endif /* SCMT_INIT */ + #if SCMT_DEBUG + PRINTFN("SCMT B: SCMT_CMSCNT (0x%x) = 0x%x\n", SCMT_CMSCNT, mem_read32(SCMT_CMSCNT) ); + #endif /* SCMT_DEBUG */ + #if SCMT_INIT + mem_write32(SCMT_CMSCOR,0xffffffff); /* Set compare value to maximum, we use it as 32-bit counter only */ + #endif /* SCMT_INIT */ + #if SCMT_DEBUG + PRINTFN("SCMT C: SCMT_CMSCOR (0x%x) = 0x%x\n", SCMT_CMSCOR, mem_read32(SCMT_CMSCOR) ); + #endif /* SCMT_DEBUG */ + #if SCMT_INIT + while(mem_read16(SCMT_CMSCSR)&(1<<13)); /* Wait for write clearance */ + #endif /* SCMT_INIT */ + #if SCMT_DEBUG + PRINTFN("SCMT D: SCMT_CMSCSR (0x%x) = 0x%x\n", SCMT_CMSCSR, mem_read16(SCMT_CMSCSR) ); + #endif /* SCMT_DEBUG */ + #if SCMT_INIT + mem_write16(SCMT_CMSSTR,1<<5); /* Start counter */ + #endif /* SCMT_INIT */ + #if SCMT_DEBUG + PRINTFN("SCMT E: SCMT_CMSSTR (0x%x) = 0x%x\n", SCMT_CMSSTR, mem_read16(SCMT_CMSSTR) ); + PRINTFN("SCMT F: SCMT_CMSCNT (0x%x) = 0x%x\n", SCMT_CMSCNT, mem_read32(SCMT_CMSCNT) ); + PRINTFN("SCMT G: SCMT_CMSCNT (0x%x) = 0x%x\n", SCMT_CMSCNT, mem_read32(SCMT_CMSCNT) ); + PRINTFN("SCMT H: SCMT_CMSCNT (0x%x) = 0x%x\n", SCMT_CMSCNT, mem_read32(SCMT_CMSCNT) ); + PRINTFN("SCMT I: SCMT_CMSCNT (0x%x) = 0x%x\n", SCMT_CMSCNT, mem_read32(SCMT_CMSCNT) ); + #endif /* SCMT_DEBUG */ +} + +uint32_t scmt_module_read(void) +{ + uint32_t last = 0, current = 0; + + /* For boot time measurement, signal start of SCMT by GPIO pin toggle, reset after some time */ + #if SCMT_TOGGLE_GPIO + gpio_clear(); + #endif /* SCMT_TOGGLE_GPIO */ + + /* From UM: + When CMSCNT is read during the counter operation, the read value may be wrong because of an asynchronous clock between counter and bus-interface. + For exact value, read this register continuously, until same values are read from this register. */ + current = mem_read32(SCMT_CMSCNT); + do { + last = current; + current = mem_read32(SCMT_CMSCNT); + } while (last != current); + return current; +} + +/* NOT SAFE FOR OVERLFOWS */ +void scmt_wait_ticks(uint32_t ticks) +{ + uint32_t start = scmt_module_read(); + uint32_t stop = start + ticks; + + while (stop > scmt_module_read()) { /* NOP */ }; +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/cpu_on/cpu_on.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/cpu_on/cpu_on.c new file mode 100644 index 0000000..203ed14 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/cpu_on/cpu_on.c @@ -0,0 +1,237 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Power management driver + ******************************************************************************/ + /****************************************************************************** + * @file cpu_on.c + * - Version : 0.09 + * @brief Boot process of ARM CPU core. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Modify macro definition name. + * : 08.09.2021 0.03 Removed the reset process of BOOT_CTRL and + * OPBT_CTRL register. + * : 06.01.2022 0.04 Static analysis support + * : 23.05.2022 0.05 Integration of S4 and V4H + * : 21.06.2022 0.06 Remove functions for MCU. + * : 21.08.2023 0.07 Add support for V4M. + * : 17.11.2023 0.08 Move a part of definitions to cpu_on.h. + * : 09.12.2024 0.09 Update OTP_MEM_OTPMONITOR60 register to + * OTP_MEM_OTPMONITOR17 register for V4M. + * And Improve the adj_cr_variant_freq function. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* ARM */ +#define CA_CORE0_WUP_REQ (0x00000001U) +#define CA_CORE0_VLD_RVBARP (0x00000001U) +#define CR_VLD_BARP (0x00000001U << 0U) +#define CR_BAREN_VALID (0x00000001U << 4U) +#define CRRST_BIT (0x00000001U) + +#if (RCAR_LSI == RCAR_V4H) +#define V4H_7_NI_CR (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */ +#define V4H_5_NI_CR (0x41U) /* 1100[MHz] = 50/3[MHz] x (0x41 + 0x1) */ +#define V4H_3_NI_CR (0x35U) /* 900[MHz] = 50/3[MHz] x (0x35 + 0x1) */ +#elif (RCAR_LSI == RCAR_V4M) +#define V4M_7_NI_CR (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */ +#define V4M_5_NI_CR (0x41U) /* 1100[MHz] = 50/3[MHz] x (0x41 + 0x1) */ +#define V4M_3_NI_CR (0x35U) /* 900[MHz] = 50/3[MHz] x (0x35 + 0x1) */ +#define V4M_2_NI_CR (0x35U) /* 900[MHz] = 50/3[MHz] x (0x35 + 0x1) */ +# endif /* RCAR_LSI == RCAR_V4H */ + +#define CPG_PLL6CR0_KICK_BIT (0x80000000U) +#define CPG_PLLECR_PLL6ST_BIT (0x00008000U) + +#define AP_CORE_APSREG_P_CCI500_AUX_ASPRTM (0x00000001U << 1U) + +static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr); + +static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr) +{ + if(RCAR_PWR_TARGET_CR == target) + { + /* CR Boot address set */ + mem_write32(APMU_CRBARP, (uint32_t)(boot_addr | CR_VLD_BARP)); + mem_write32(APMU_CRBARP, (uint32_t)(boot_addr | CR_VLD_BARP | CR_BAREN_VALID)); + } + else if(RCAR_PWR_TARGET_CA == target) + { + /* CA Boot address set */ + mem_write32(APMU_RVBARPLC0, boot_addr | CA_CORE0_VLD_RVBARP); + mem_write32(APMU_RVBARPHC0, 0x00000000U); + } + else + { + /* No Process */ + } +} +/* End of function arm_cpu_set_address(uint32_t target, uint32_t boot_addr) */ + +void arm_cpu_on(uint32_t target, uint32_t boot_addr) +{ + uint32_t res_data; + + if(RCAR_PWR_TARGET_CR == target) + { + /* CR Boot address set. */ + arm_cpu_set_address(target, boot_addr); + + synci(); + + /* CR reset. */ + res_data = mem_read32(APMU_CRRSTCTRL); + res_data &= ~(CRRST_BIT); + mem_write32(APMU_CRRSTCTRL, res_data); + } + else if(RCAR_PWR_TARGET_CA == target) + { + /* CA Boot address set. */ + arm_cpu_set_address(target, boot_addr); + + /* AP-System core initialize */ + res_data = mem_read32(ap_core_get_ap_cluster_n_aux0_addr(0U)); + res_data |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT; + mem_write32(ap_core_get_ap_cluster_n_aux0_addr(0U), res_data); + + res_data = mem_read32(AP_CORE_APSREG_CCI500_AUX); + res_data |= AP_CORE_APSREG_CCI500_AUX_ACTDIS; + mem_write32(AP_CORE_APSREG_CCI500_AUX, res_data); +#if (RCAR_LSI == RCAR_V4H) + res_data = mem_read32(AP_CORE_APSREG_P_CCI500_AUX); + res_data |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM; + mem_write32(AP_CORE_APSREG_P_CCI500_AUX, res_data); +#endif /* RCAR_LSI == RCAR_V4H */ + synci(); + + /* CA core0 wake up sequence. */ + res_data = mem_read32(APMU_PWRCTRLC0); + res_data |= CA_CORE0_WUP_REQ; + mem_write32(APMU_PWRCTRLC0, res_data); + /* Wait until CA core0 wake up sequence finished. */ + do + { + res_data = mem_read32(APMU_PWRCTRLC0); + }while(FALSE != (CA_CORE0_WUP_REQ & res_data)); + } + else + { + /* No Process */ + } +} +/* End of function arm_cpu_on(uint32_t target, uint32_t boot_addr) */ + + +void adj_cr_variant_freq(void) +{ + uint32_t product = mem_read32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK; + uint32_t pll6_freq = mem_read32(CPG_PLL6CR0); + +#if (RCAR_LSI == RCAR_V4H) + /* Set the CPU frequency division ratio according to the type of variant. */ + switch (product) + { + case VARIANT_V4H_7: + /* Default value, do nothing */; + break; + case VARIANT_V4H_5: + pll6_freq = (pll6_freq & ~(0xFFU << 20U)); + pll6_freq = (pll6_freq | (V4H_5_NI_CR << 20U)); + break; + case VARIANT_V4H_3: + pll6_freq = (pll6_freq & ~(0xFFU << 20U)); + pll6_freq = (pll6_freq | (V4H_3_NI_CR << 20U)); + break; + default: + ; /* Do nothing */ + break; + } + + if (VARIANT_V4H_5 == product || VARIANT_V4H_3 == product) + { + /* Write Division value to FRQCRC0 register */ + mem_write32(CPG_CPGWPR, ~(pll6_freq)); + mem_write32(CPG_PLL6CR0, pll6_freq); + + mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT)); + mem_write32(CPG_PLL6CR0, (mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT)); + + while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL6ST_BIT) != CPG_PLLECR_PLL6ST_BIT) + { + ; + } + } +#elif (RCAR_LSI == RCAR_V4M) + /* Set the CPU frequency division ratio according to the type of variant. */ + switch (product) + { + case VARIANT_V4M_7: + /* Default value, do nothing */; + break; + case VARIANT_V4M_5: + pll6_freq = (pll6_freq & ~(0xFFU << 20U)); + pll6_freq = (pll6_freq | (V4M_5_NI_CR << 20U)); + break; + case VARIANT_V4M_3: + pll6_freq = (pll6_freq & ~(0xFFU << 20U)); + pll6_freq = (pll6_freq | (V4M_3_NI_CR << 20U)); + break; + case VARIANT_V4M_2: + pll6_freq = (pll6_freq & ~(0xFFU << 20U)); + pll6_freq = (pll6_freq | (V4M_2_NI_CR << 20U)); + break; + default: + ; /* Do nothing */ + break; + } + + if (VARIANT_V4M_5 == product || VARIANT_V4M_3 == product || VARIANT_V4M_2 == product) + { + /* Write Division value to FRQCRC0 register */ + mem_write32(CPG_CPGWPR, ~(pll6_freq)); + mem_write32(CPG_PLL6CR0, pll6_freq); + + mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT)); + mem_write32(CPG_PLL6CR0, (mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT)); + + while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL6ST_BIT) != CPG_PLLECR_PLL6ST_BIT) + { + ; + } + } +#endif /* RCAR_LSI == RCAR_V4H */ +} +/* End of function adj_cpu_variant_freq(void) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/dos.mk b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/dos.mk new file mode 100644 index 0000000..3eed752 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/dos.mk @@ -0,0 +1,734 @@ +#/******************************************************************************* +# * DISCLAIMER +# * This software is supplied by Renesas Electronics Corporation and is only +# * intended for use with Renesas products. No other uses are authorized. This +# * software is owned by Renesas Electronics Corporation and is protected under +# * all applicable laws, including copyright laws. +# * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +# * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +# * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +# * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +# * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +# * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +# * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +# * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +# * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +# * Renesas reserves the right, without notice, to make changes to this software +# * and to discontinue the availability of this software. By using this software, +# * you agree to the additional terms and conditions found by accessing the +# * following link: +# * http://www.renesas.com/disclaimer +# * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved. +# *******************************************************************************/ +# +# ******************************************************************************* +# * DESCRIPTION : makefile for Loader +# ****************************************************************************** + +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +INCLUDE_DIR = -Iinclude \ + -Iip/ddr + +OUTDIR := build + +# LSI setting common define +RCAR_S4 := 0 +RCAR_V4H := 1 +RCAR_V4M := 2 +$(eval $(call add_define,RCAR_S4)) +$(eval $(call add_define,RCAR_V4H)) +$(eval $(call add_define,RCAR_V4M)) +ifneq ("$(FORCE_115200)", "") +$(eval $(call add_define,FORCE_115200)) +endif + +#/* Select LSI("S4" or "V4H" or "V4M" )******************************** +ifeq ("$(LSI)", "") +LSI = S4 +endif + +ifeq (${LSI},S4) + RCAR_LSI:=${RCAR_S4} + DIR_NAME_SA9 = s4 + OBJ_FILE += loader/loader_main_s4.o \ + cnf_tbl/cnf_tbl_s4.o \ + ip/qos/qos.o \ + ip/rtvram/rtvram.o \ + ip/ddr/s4/lpddr4x/ecc_enable_s4.o + INCLUDE_DIR += -Imcu + include ip/ddr/ddr.mk +else ifeq (${LSI},V4H) + RCAR_LSI:=${RCAR_V4H} + DIR_NAME_SA9 = v4h + OBJ_FILE += loader/loader_main_v4h.o \ + ip/fcpr/fcpr.o \ + cnf_tbl/cnf_tbl_v4h.o \ + common/crc32.o \ + image_load/android_ab.o \ + ip/ddr/v4h/lpddr5/ecc_enable_v4h.o \ + ip/ddr/v4h/lpddr5/ecm_enable_v4h.o +else ifeq (${LSI},V4M) + RCAR_LSI:=${RCAR_V4M} + DIR_NAME_SA9 = v4m + OBJ_FILE += loader/loader_main_v4m.o \ + ip/fcpr/fcpr.o \ + cnf_tbl/cnf_tbl_v4m.o \ + ip/sysc/sysc.o \ + ip/avs/avs.o \ + ip/i2c/i2c.o \ + ip/ddr/v4m/lpddr5/ecc_enable_v4m.o \ + ip/ddr/v4m/lpddr5/ecm_enable_v4m.o +else + $(error "Error: ${LSI} is not supported.") +endif +$(eval $(call add_define,RCAR_LSI)) + +# timing measurement +ifeq ("$(MEASURE_TIME)", "") + MEASURE_TIME = 0 +else + $(eval $(call add_define,MEASURE_TIME)) + # Set log level to Error, so we dont waste time with unnecessary prints + LOG_LEVEL := 1 + OBJ_FILE += common/scmt_checkpoint.o \ + common/timer/scmt.o +endif +ifeq ("$(MEASURE_TIME_NOPRINT)", "") + MEASURE_TIME_NOPRINT = 0 +else + $(eval $(call add_define,MEASURE_TIME_NOPRINT)) +endif + +################################################### + +#output file name +FILE_NAME = icumx_loader +FILE_NAME_SA0 = bootparam_sa0 +FILE_NAME_SA9 = cert_header_sa9 +FILE_NAME_TFMV_TBL = tfmv_ver_tbl +FILE_NAME_NTFMV_TBL = ntfmv_ver_tbl + +OUTPUT_FILE = $(FILE_NAME).elf +OUTPUT_FILE_SA0 = $(FILE_NAME_SA0).elf +OUTPUT_FILE_SA9 = $(FILE_NAME_SA9).elf +OUTPUT_FILE_TFMV_TBL = $(FILE_NAME_TFMV_TBL).elf +OUTPUT_FILE_NTFMV_TBL = $(FILE_NAME_NTFMV_TBL).elf + +#object file name +OBJ_FILE += cpu_on/cpu_on.o \ + common/log/log.o \ + common/log/scif.o \ + common/timer/micro_wait.o \ + image_load/image_load.o \ + intc/intc.o \ + intc/vecttbl.o \ + intc/vect_set.o \ + ip/ip_control.o \ + ip/cpg/cpg.o \ + ip/emmc/emmc_boot.o \ + ip/wdt/wdt.o \ + loader/loader.o \ + loader/loader_main_common.o \ + protect/ram_protection.o \ + protect/region_id.o \ + protect/stack_protect.o \ + remap/remap.o \ + rom_api/rom_api.o + +OBJ_FILE_SA0 = tools/dummy_create/sa0.o +OBJ_FILE_SA9 = tools/dummy_create/$(DIR_NAME_SA9)/sa9.o +OBJ_FILE_TFMV_TBL = tools/sw_min_ver_tbl/tfmv_ver_tbl.o +OBJ_FILE_NTFMV_TBL = tools/sw_min_ver_tbl/ntfmv_ver_tbl.o + +#linker script name +ifeq (${LSI},V4M) + MEMORY_DEF = loader/icumx_loader_v4m.ld +else + MEMORY_DEF = loader/icumx_loader.ld +endif + +MEMORY_DEF_SA0 = tools/dummy_create/sa0.ld +MEMORY_DEF_SA9 = tools/dummy_create/$(DIR_NAME_SA9)/sa9.ld +MEMORY_DEF_TFMV_TBL = tools/sw_min_ver_tbl/tfmv_ver_tbl.ld +MEMORY_DEF_NTFMV_TBL = tools/sw_min_ver_tbl/ntfmv_ver_tbl.ld + +################################################### + +# Debug build +DEBUG:=0 + +# Process DEBUG flag +$(eval $(call assert_boolean,DEBUG)) +$(eval $(call add_define,DEBUG)) +ifeq (${DEBUG},0) + $(eval $(call add_define,NDEBUG)) +CFLAGS += -Onone +else +ASFLAGS += -G -dwarf2 +CFLAGS += -G -dwarf2 -Odebug +endif + +# booting performance check +ifneq ("$(WDT_RESET)", "") +$(eval $(call add_define,WDT_RESET)) +endif + +# Process STRICT_AB_BOOTING flag +ifneq ("$(STRICT_AB_BOOTING)", "") +$(eval $(call add_define,STRICT_AB_BOOTING)) +endif + +# booting performance check +ifeq ("$(BOOT_TIME_CHECK)", "") +BOOT_TIME_CHECK = 0 +endif +$(eval $(call add_define,BOOT_TIME_CHECK)) +OBJ_FILE += ip/gpio/gpio.o + +# MISRA Option +#------ MISRA ------ +ifndef MISRA +MISRA := MANDATORY +endif +ifeq ("$(MISRA)", "DISABLE") + MISRA_OPTION = DISABLE +else ifeq ("$(MISRA)", "FULL") + MISRA_OPTION = FULL +else ifeq ("$(MISRA)", "MANDATORY") + MISRA_OPTION = MANDATORY +else ifeq ("$(MISRA)", "REQUIRED") + MISRA_OPTION = REQUIRED +endif +CFLAGS_MISRA_FULL = \ + --misra_adv=warn \ + --misra_req=warn \ + --misra_mand=warn \ + --no_misra_runtime \ + --misra_2012=all,-R1.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later +CFLAGS_MISRA_REQUIRED = \ + --misra_adv=silent \ + --misra_req=warn \ + --misra_mand=warn \ + --no_misra_runtime \ + --misra_2012=all,-R1.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later +CFLAGS_MISRA_MANDATORY = \ + --misra_adv=silent \ + --misra_req=silent \ + --misra_mand=warn \ + --no_misra_runtime \ + --misra_2012=all,-R1.1,-R3.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later + # MISRA 2012 Rule 3.1 is confirmed with static analysis +ifeq ("$(MISRA_OPTION)", "FULL") +CFLAGS += $(CFLAGS_MISRA_FULL) +else ifeq ("$(MISRA)", "REQUIRED") +CFLAGS += $(CFLAGS_MISRA_REQUIRED) +else ifeq ("$(MISRA)", "MANDATORY") +CFLAGS += $(CFLAGS_MISRA_MANDATORY) +endif + +# Process LOG_LEVEL +ifndef LOG_LEVEL +LOG_LEVEL := 2 +endif +$(eval $(call add_define,LOG_LEVEL)) +ifeq (${LOG_LEVEL},0) + LDFLAGS += -nostdlib +endif + +# Process SET_FCPR_PARAM flag +# 0:Disable, 1:Enable (Support V4H / V4M Linux OS) +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef SET_FCPR_PARAM + SET_FCPR_PARAM := 0 + $(eval $(call add_define,SET_FCPR_PARAM)) + else + ifeq (${SET_FCPR_PARAM},0) + $(eval $(call add_define,SET_FCPR_PARAM)) + else ifeq (${SET_FCPR_PARAM},1) + $(eval $(call add_define,SET_FCPR_PARAM)) + else + $(error "Error:SET_FCPR_PARAM=${SET_FCPR_PARAM} is not supported.") + endif + endif +else + SET_FCPR_PARAM := 0 + $(eval $(call add_define,SET_FCPR_PARAM)) +endif + +# Process BOOT_MCU flag (S4 only) +# 0:None, 1:G4MH, 2:Reserved, 3:G4MH+ICUMH +ifeq (${LSI},S4) + ifndef BOOT_MCU + BOOT_MCU :=3 + $(eval $(call add_define,BOOT_MCU)) + else + ifeq (${BOOT_MCU},0) + $(eval $(call add_define,BOOT_MCU)) + else ifeq (${BOOT_MCU},1) + $(eval $(call add_define,BOOT_MCU)) + else ifeq (${BOOT_MCU},2) + $(eval $(call add_define,BOOT_MCU)) + else ifeq (${BOOT_MCU},3) + $(eval $(call add_define,BOOT_MCU)) + else + $(error "Error:BOOT_MCU=${BOOT_MCU} is not supported.") + endif + endif +else + BOOT_MCU :=0 + $(eval $(call add_define,BOOT_MCU)) +endif + +ifneq (${BOOT_MCU},0) +OBJ_FILE += mcu/cpu_on_for_mcu.o \ + mcu/sdmac.o \ + mcu/loader_main_mcu.o \ + mcu/image_load_for_mcu.o \ + mcu/codesram_ecc.o +endif + +# Process RTVRAM_EXTEND flag +ifeq (${LSI},S4) + ifndef RTVRAM_EXTEND + RTVRAM_EXTEND := 1 + $(eval $(call add_define,RTVRAM_EXTEND)) + else + ifeq (${RTVRAM_EXTEND},0) + $(eval $(call add_define,RTVRAM_EXTEND)) + else ifeq (${RTVRAM_EXTEND},1) + $(eval $(call add_define,RTVRAM_EXTEND)) + else + $(error "Error:RTVRAM_EXTEND=${RTVRAM_EXTEND} is not supported.") + endif + endif +endif + +# Process QSPI_DDR_MODE flag +# 0:SDR, 1:DDR +ifndef QSPI_DDR_MODE +QSPI_DDR_MODE := 0 +$(eval $(call add_define,QSPI_DDR_MODE)) +else + ifeq (${QSPI_DDR_MODE},0) + $(eval $(call add_define,QSPI_DDR_MODE)) + else ifeq (${QSPI_DDR_MODE},1) + $(eval $(call add_define,QSPI_DDR_MODE)) + else + $(error "Error:QSPI_DDR_MODE=${QSPI_DDR_MODE} is not supported.") + endif +endif + +# RCAR_QSPI_DDR_DUMMY_CYCLE +ifndef RCAR_QSPI_DDR_DUMMY_CYCLE +RCAR_QSPI_DDR_DUMMY_CYCLE := 9 +endif +$(eval $(call add_define,RCAR_QSPI_DDR_DUMMY_CYCLE)) + +# Process RCAR_SA9_TYPE flag +# 0:Flash, 1:eMMC +ifeq (${LSI},S4) + ifndef RCAR_SA9_TYPE + RCAR_SA9_TYPE := 0 + $(eval $(call add_define,RCAR_SA9_TYPE)) + else + ifeq (${RCAR_SA9_TYPE},0) + $(eval $(call add_define,RCAR_SA9_TYPE)) + else ifeq (${RCAR_SA9_TYPE},1) + $(eval $(call add_define,RCAR_SA9_TYPE)) + else + $(error "Error:RCAR_SA9_TYPE=${RCAR_SA9_TYPE} is not supported.") + endif + endif +else ifeq ($(filter ${LSI},V4H V4M),${LSI}) + RCAR_SA9_TYPE := 0 + $(eval $(call add_define,RCAR_SA9_TYPE)) +endif + + +ifeq (${RCAR_SA9_TYPE},1) +OBJ_FILE += image_load/image_load_emmc.o \ + ip/emmc/emmc_cmd.o \ + ip/emmc/emmc_init.o \ + ip/emmc/emmc_interrupt.o \ + ip/emmc/emmc_mount.o \ + ip/emmc/emmc_multiboot.o \ + ip/emmc/emmc_read.o \ + ip/emmc/emmc_utility.o +else ifeq (${RCAR_SA9_TYPE},0) +OBJ_FILE += image_load/image_load_flash.o \ + ip/dma/dma.o \ + ip/rpc/rpc.o \ + ip/rpc/qspi_xdr_mode.o \ + ip/rpc/dma2.o \ + ip/rpc/rpcqspidrv.o \ + ip/rpc/spiflash2drv.o \ + ip/mfis/mfis.o +endif + +# Process CA_LOAD_TYPE flag +# 0:CA Loader 1:BL31 (or Secure Monitor) +ifeq (${LSI},S4) + ifndef CA_LOAD_TYPE + CA_LOAD_TYPE := 0 + $(eval $(call add_define,CA_LOAD_TYPE)) + else + ifeq (${CA_LOAD_TYPE},0) + $(eval $(call add_define,CA_LOAD_TYPE)) + else ifeq (${CA_LOAD_TYPE},1) + $(eval $(call add_define,CA_LOAD_TYPE)) + else + $(error "Error:CA_LOAD_TYPE=${CA_LOAD_TYPE} is not supported.") + endif + endif +else ifeq ($(filter ${LSI},V4H V4M),${LSI}) + CA_LOAD_TYPE := 0 + $(eval $(call add_define,CA_LOAD_TYPE)) +endif + +ifeq (${RCAR_SA9_TYPE},1) + ifeq (${CA_LOAD_TYPE},0) + $(error "Error:RCAR_SA9_TYPE=1 and CA_LOAD_TYPE=0 is not supported.") + endif +endif + +# Process MCU_SECURE_BOOT flag (S4 only) +ifndef MCU_SECURE_BOOT + MCU_SECURE_BOOT := 0 + $(eval $(call add_define,MCU_SECURE_BOOT)) +else + ifeq (${MCU_SECURE_BOOT},0) + $(eval $(call add_define,MCU_SECURE_BOOT)) + else ifeq (${MCU_SECURE_BOOT},1) + ifeq (${BOOT_MCU},0) + $(error "Error:MCU_SECURE_BOOT=${MCU_SECURE_BOOT} and BOOT_MCU=${BOOT_MCU} is not supported.") + else + $(eval $(call add_define,MCU_SECURE_BOOT)) + endif + else + $(error "Error:MCU_SECURE_BOOT=${MCU_SECURE_BOOT} is not supported.") + endif +endif + +# Process SW_VERSION_CHECK flag +# 0:Disable 1:Enable +ifndef SW_VERSION_CHECK +SW_VERSION_CHECK := 0 +$(eval $(call add_define,SW_VERSION_CHECK)) +else + ifeq (${SW_VERSION_CHECK},0) + $(eval $(call add_define,SW_VERSION_CHECK)) + else ifeq (${SW_VERSION_CHECK},1) + $(eval $(call add_define,SW_VERSION_CHECK)) + else + $(error "Error:SW_VERSION_CHECK=${SW_VERSION_CHECK} is not supported.") + endif +endif + +# Process access protection flag +# 0:Disable 1:Enable +ifndef ACC_PROT_ENABLE +ACC_PROT_ENABLE := 0 +$(eval $(call add_define,ACC_PROT_ENABLE)) +else + ifeq (${ACC_PROT_ENABLE},0) + $(eval $(call add_define,ACC_PROT_ENABLE)) + else ifeq (${ACC_PROT_ENABLE},1) + $(eval $(call add_define,ACC_PROT_ENABLE)) + else + $(error "Error:ACC_PROT_ENABLE=${ACC_PROT_ENABLE} is not supported.") + endif +endif + +ifeq (${MCU_SECURE_BOOT},1) +include mcu_secureboot/mcu_secureboot.mk +endif + +# Process ADD_HOTPLUG_MAGIC flag +ifndef ADD_HOTPLUG_MAGIC + ADD_HOTPLUG_MAGIC := 0 + $(eval $(call add_define,ADD_HOTPLUG_MAGIC)) +else + ifeq (${ADD_HOTPLUG_MAGIC},0) + $(eval $(call add_define,ADD_HOTPLUG_MAGIC)) + else ifeq (${ADD_HOTPLUG_MAGIC},1) + $(eval $(call add_define,ADD_HOTPLUG_MAGIC)) + else + $(error "Error:ADD_HOTPLUG_MAGIC=${ADD_HOTPLUG_MAGIC} is not supported.") + endif +endif + +# Process STACK_PROTECT flag +ifndef STACK_PROTECT + STACK_PROTECT := 0 + $(eval $(call add_define,STACK_PROTECT)) +else + ifeq (${STACK_PROTECT},0) + $(eval $(call add_define,STACK_PROTECT)) + else ifeq (${STACK_PROTECT},1) + $(eval $(call add_define,STACK_PROTECT)) + CFLAGS += -stack_protector + else + $(error "Error:STACK_PROTECT=${STACK_PROTECT} is not supported.") + endif +endif + +# Process RTOS_LOAD_NUM flag +# 1:RTOS#0 only 3:RTOS#0,#1,#2 +ifndef RTOS_LOAD_NUM + RTOS_LOAD_NUM := 1 + $(eval $(call add_define,RTOS_LOAD_NUM)) +else + ifeq (${RTOS_LOAD_NUM},1) + $(eval $(call add_define,RTOS_LOAD_NUM)) + else ifeq (${RTOS_LOAD_NUM},3) + $(eval $(call add_define,RTOS_LOAD_NUM)) + else + $(error "Error:RTOS_LOAD_NUM=${RTOS_LOAD_NUM} is not supported.") + endif +endif + +# Process OPTEE_LOAD_ENABLE flag +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef OPTEE_LOAD_ENABLE + OPTEE_LOAD_ENABLE := 1 + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else + ifeq (${OPTEE_LOAD_ENABLE},0) + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else ifeq (${OPTEE_LOAD_ENABLE},1) + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else + $(error "Error:OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.") + endif + endif +endif + +# Process BL2_LOAD_ENABLE flag +ifeq (${LSI},V4H) + ifndef BL2_LOAD_ENABLE + BL2_LOAD_ENABLE := 1 + $(eval $(call add_define,BL2_LOAD_ENABLE)) + else + ifeq (${BL2_LOAD_ENABLE},0) + $(eval $(call add_define,BL2_LOAD_ENABLE)) + else ifeq (${BL2_LOAD_ENABLE},1) + $(eval $(call add_define,BL2_LOAD_ENABLE)) + else + $(error "Error:BL2_LOAD_ENABLE=${BL2_LOAD_ENABLE} is not supported.") + endif + endif +endif + +# Process QNX_OS_LOAD_ENABLE flag +ifeq (${LSI},V4H) + ifndef QNX_OS_LOAD_ENABLE + QNX_OS_LOAD_ENABLE := 1 + $(eval $(call add_define,QNX_OS_LOAD_ENABLE)) + else + ifeq (${QNX_OS_LOAD_ENABLE},0) + $(eval $(call add_define,QNX_OS_LOAD_ENABLE)) + else ifeq (${QNX_OS_LOAD_ENABLE},1) + $(eval $(call add_define,QNX_OS_LOAD_ENABLE)) + else + $(error "Error:QNX_OS_LOAD_ENABLE=${QNX_OS_LOAD_ENABLE} is not supported.") + endif + endif +endif + +################################################### +# pass SecureMonitor parametor +################################################### +# Process SET_CA_PARAM flag +ifeq (${LSI},S4) + ifndef SET_CA_PARAM + SET_CA_PARAM := 1 + $(eval $(call add_define,SET_CA_PARAM)) + else + ifeq (${SET_CA_PARAM},0) + $(eval $(call add_define,SET_CA_PARAM)) + else ifeq (${SET_CA_PARAM},1) + $(eval $(call add_define,SET_CA_PARAM)) + else + $(error "Error:SET_CA_PARAM=${SET_CA_PARAM} is not supported.") + endif + endif +endif + +# Process ECM_ENABLE +ifndef ECM_ENABLE + ECM_ENABLE:= 0 + $(eval $(call add_define,ECM_ENABLE)) +else + ifeq (${ECM_ENABLE},0) + $(eval $(call add_define,ECM_ENABLE)) + else ifeq (${ECM_ENABLE},1) + $(eval $(call add_define,ECM_ENABLE)) + else + $(error "Error: ECM_ENABLE=${ECM_ENABLE} is not supported.") + endif +endif + +# Process ECM_ERROR_ENABLE flag +ifndef ECM_ERROR_ENABLE + ECM_ERROR_ENABLE := 1 + $(eval $(call add_define,ECM_ERROR_ENABLE)) +else + ifeq (${ECM_ERROR_ENABLE},0) + $(eval $(call add_define,ECM_ERROR_ENABLE)) + else ifeq (${ECM_ERROR_ENABLE},1) + $(eval $(call add_define,ECM_ERROR_ENABLE)) + else + $(error "Error:ECM_ERROR_ENABLE=${ECM_ERROR_ENABLE} is not supported.") + endif +endif + + +# Process SAN_ENABLE +ifndef SAN_ENABLE + SAN_ENABLE:= 0 + $(eval $(call add_define,SAN_ENABLE)) +else + ifeq (${SAN_ENABLE},0) + $(eval $(call add_define,SAN_ENABLE)) + else ifeq (${SAN_ENABLE},1) + $(eval $(call add_define,SAN_ENABLE)) + OBJ_FILE += \ + ip/san/v4h.o \ + ip/wdt/rwdt.o \ + ip/i2c/i2c5.o + else + $(error "Error: SAN_ENABLE=${SAN_ENABLE} is not supported.") + endif +endif + +# Process DBSC HUNGUP WA +ifndef WA_OTLINT5579 + WA_OTLINT5579:= 1 +endif +$(eval $(call add_define,WA_OTLINT5579)) + +################################################### + +OUTDIR_REL := $(OUTDIR)/release +OUTDIR_OBJ := $(OUTDIR)/obj + +OBJ_FILE := $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o) +OBJ_FILE_SA0 := $(OBJ_FILE_SA0:%.o=$(OUTDIR_OBJ)/%.o) +OBJ_FILE_SA9 := $(OBJ_FILE_SA9:%.o=$(OUTDIR_OBJ)/%.o) +OBJ_FILE_TFMV_TBL := $(OBJ_FILE_TFMV_TBL:%.o=$(OUTDIR_OBJ)/%.o) +OBJ_FILE_NTFMV_TBL := $(OBJ_FILE_NTFMV_TBL:%.o=$(OUTDIR_OBJ)/%.o) + +CC = cxrh850 +AS = cxrh850 +LD = cxrh850 +OC = gsrec +OD = gdump + +ASFLAGS += -asm="-preprocess_assembly_files" \ + -asm="-nostartfiles" \ + -D__ASSEMBLY \ + $(INCLUDE_DIR) $(DEFINES) + +CFLAGS += -nostartfiles \ + -c99 \ + $(INCLUDE_DIR) $(DEFINES) \ + --ghstd=last \ + -Wundef \ + --diag_error=193 \ + --prototype_errors +# --ghstd=last : Enable Green Hills Standard Mode +# -Wundef : Output warning if there are any undefined symbols +# --diag_error=193 : Error if zero is applied to undefined symbol +# --prototype_errors : Error if there are no any prototype declaration + +ifeq (${LOG_LEVEL},0) +# There are no any additional options +else +CFLAGS += --diag_suppress=1932 # There is warning that format string parameter in sprintf is not constant +endif + +LDFLAGS += -nostartfiles -Mu + +BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__ + +################################################### +.SUFFIXES : .s .c .o + +################################################### +# command + +.PHONY: all +all: $(OUTPUT_FILE) $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA9) $(OUTPUT_FILE_TFMV_TBL) $(OUTPUT_FILE_NTFMV_TBL) + +################################################### +# Linker +################################################### +$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE) + @echo const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP); > $(OUTDIR_OBJ)/build_message.c + $(V)$(CC) $(CFLAGS) -o $(OUTDIR_OBJ)/build_message.o -c $(OUTDIR_OBJ)/build_message.c + + $(V)$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \ + -T $(MEMORY_DEF) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE) \ + $(LDFLAGS) \ + -map=$(OUTDIR_REL)/$(FILE_NAME).map + + $(V)$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).srec + $(V)$(OD) -full -ysec $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump + $(V)gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE) -o $(OUTDIR_REL)/$(OUTPUT_FILE:%.elf=%.bin) + +$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0) + $(V)$(LD) $(OBJ_FILE_SA0) \ + -T $(MEMORY_DEF_SA0) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) \ + -map=$(OUTDIR_REL)/$(FILE_NAME_SA0).map \ + -nostdlib + + $(V)$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) > $(OUTDIR_REL)/$(FILE_NAME_SA0).srec + $(V)gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0:%.elf=%.bin) + +$(OUTPUT_FILE_SA9) : $(MEMORY_DEF_SA9) $(OBJ_FILE_SA9) + $(V)$(LD) $(OBJ_FILE_SA9) \ + -T $(MEMORY_DEF_SA9) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) \ + -map=$(OUTDIR_REL)/$(FILE_NAME_SA9).map \ + -nostdlib + + $(V)$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) > $(OUTDIR_REL)/$(FILE_NAME_SA9).srec + $(V)gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA9:%.elf=%.bin) + +$(OUTPUT_FILE_TFMV_TBL) : $(MEMORY_DEF_TFMV_TBL) $(OBJ_FILE_TFMV_TBL) + $(V)$(LD) $(OBJ_FILE_TFMV_TBL) \ + -T $(MEMORY_DEF_TFMV_TBL) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL) \ + -map=$(OUTDIR_REL)/$(FILE_NAME_TFMV_TBL).map \ + -nostdlib + + $(V)gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL) -o $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL:%.elf=%.bin) + +$(OUTPUT_FILE_NTFMV_TBL) : $(MEMORY_DEF_NTFMV_TBL) $(OBJ_FILE_NTFMV_TBL) + $(V)$(LD) $(OBJ_FILE_NTFMV_TBL) \ + -T $(MEMORY_DEF_NTFMV_TBL) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL) \ + -map=$(OUTDIR_REL)/$(FILE_NAME_NTFMV_TBL).map \ + -nostdlib + + $(V)gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL) -o $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL:%.elf=%.bin) + +################################################### +# Compile +################################################### + +$(OUTDIR_OBJ)/%.o:%.c + $(V)$(CC) $(CFLAGS) -o $@ -c $< + +$(OUTDIR_OBJ)/%.o:%.S + $(V)$(AS) $(ASFLAGS) -o $@ -c $< + + +.PHONY: clean +clean: + @rm -rf $(OUTDIR) diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/env.ini b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/env.ini new file mode 100644 index 0000000..dd0a92b --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/env.ini @@ -0,0 +1,7 @@ +_build_param="ECM_ENABLE=1 ECM_ERROR_ENABLE=1 ECC_ENABLE=1 \ +SW_VERSION_CHECK=1 \ +OPTEE_LOAD_ENABLE=1 \ +BL2_LOAD_ENABLE=1 \ +QNX_OS_LOAD_ENABLE=1 \ +STACK_PROTECT=1 \ +" diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/android_ab.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/android_ab.c new file mode 100644 index 0000000..dffa61f --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/android_ab.c @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Copyright (C) 2017 The Android Open Source Project + */ +#include +#include +#include +#include +#include +#ifndef ENODATA +#define ENODATA 61 +#endif +#include + +#include +#include +#include +#include +#include +#include +typedef unsigned long int ulong; +typedef uint32_t u32; +#define typeof(x) __typeof__(x) +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +#define QSPI_MISC_START (FLASH_BASE + 0x00740000U) +#define QSPI_AB_OFFSET (2048) +#define QSPI_AB_CONTROL (QSPI_MISC_START + QSPI_AB_OFFSET) +#define QSPI_AB_SIZE (1024U) + +#include +#undef DISK_BUFFER_ADDR +#define DISK_BUFFER_ADDR (BASE_RTSRAM_ADDR + (0x0002E000U)) // 0xEB22E000U +volatile uint8_t *_disk_buffer = 0; +#undef AB_INFO_FLAG_ADDR +#define AB_INFO_FLAG_ADDR (BASE_RTSRAM_ADDR + (0x0002FFFCU)) // 0xEB22FFFCU +#define TMP_BUFFER_ADDR (BASE_RTSRAM_ADDR + (0x0002D000U)) // 0xEB22D000U + +/** + * Compute the CRC-32 of the bootloader control struct. + * + * Only the bytes up to the crc32_le field are considered for the CRC-32 + * calculation. + * + * @param[in] abc bootloader control block + * + * @return crc32 sum + */ +static uint32_t ab_control_compute_crc(struct bootloader_control *abc) +{ + return crc32(0, (void *)abc, offsetof(typeof(*abc), crc32_le)); +} + +/** + * Initialize bootloader_control to the default value. + * + * It allows us to boot all slots in order from the first one. This value + * should be used when the bootloader message is corrupted, but not when + * a valid message indicates that all slots are unbootable. + * + * @param[in] abc bootloader control block + * + * @return 0 on success and a negative on error + */ +static int ab_control_default(struct bootloader_control *abc) +{ + int i; + const struct slot_metadata metadata = { + .priority = 15, + .tries_remaining = 7, + .successful_boot = 0, + .verity_corrupted = 0, + .reserved = 0 + }; + + if (!abc) + return -EFAULT; + + memcpy(abc->slot_suffix, "a\0\0\0", 4); + abc->magic = BOOT_CTRL_MAGIC; + abc->version = BOOT_CTRL_VERSION; + abc->nb_slot = NUM_SLOTS; + memset(abc->reserved0, 0, sizeof(abc->reserved0)); + for (i = 0; i < abc->nb_slot; ++i) + abc->slot_info[i] = metadata; + + memset(abc->reserved1, 0, sizeof(abc->reserved1)); + abc->crc32_le = ab_control_compute_crc(abc); + + return 0; +} + +/** + * Load the boot_control struct from disk into newly allocated memory. + * + * This function allocates and returns an integer number of disk blocks, + * based on the block size of the passed device to help performing a + * read-modify-write operation on the boot_control struct. + * The boot_control struct offset (2 KiB) must be a multiple of the device + * block size, for simplicity. + * + * @param[out] pointer to pointer to bootloader_control data + * @return 0 on success and a negative on error + */ +static int ab_control_create_from_disk(struct bootloader_control **abc) +{ + uint32_t phys_dst = remap_get_phys_addr(DISK_BUFFER_ADDR); // 0xEB22E000U + uint32_t phys_src = QSPI_AB_CONTROL; + uint32_t size = QSPI_AB_SIZE; + + /* Load content */ + dma_trans_start(phys_dst, phys_src, size); + + /* End loading */ + load_end(); + + *abc = (struct bootloader_control *)_disk_buffer; + return 0; +} + +/** + * Store the loaded boot_control block. + * + * Store back to the same location it was read from with + * ab_control_create_from_misc(). + * + * @return 0 on success and a negative on error + */ +static int ab_control_store(struct bootloader_control *abc) +{ + uint32_t phys_dst = QSPI_AB_CONTROL; + uint32_t phys_src = remap_get_phys_addr((uint32_t)abc); + uint32_t size = sizeof(struct bootloader_control); + + init_rpc_qspi_flash(); + qspi_flash_rw_init(); + NOTICE("we're storing bootloader control block.(%d)\n", size); + + phys_dst -= FLASH_BASE; + + /* Sector Erase */ + sector_erase_qspi_flash(phys_dst, phys_dst + 4096 - 1); + + clear_bp_qspi_flash(); + save_data_with_buf_qspi_flash(phys_src, phys_dst, size); + + /* set read mode, it's slower than before */ + init_rpc_qspi_flash_4fastread_ext_mode(); + return 0; +} + +/** + * Compare two slots. + * + * The function determines slot which is should we boot from among the two. + * + * @param[in] a The first bootable slot metadata + * @param[in] b The second bootable slot metadata + * @return Negative if the slot "a" is better, positive of the slot "b" is + * better or 0 if they are equally good. + */ +static int ab_compare_slots(const struct slot_metadata *a, + const struct slot_metadata *b) +{ + /* Higher priority is better */ + if (a->priority != b->priority) + return b->priority - a->priority; + + /* Higher successful_boot value is better, in case of same priority */ + if (a->successful_boot != b->successful_boot) + return b->successful_boot - a->successful_boot; + + /* Higher tries_remaining is better to ensure round-robin */ + if (a->tries_remaining != b->tries_remaining) + return b->tries_remaining - a->tries_remaining; + + return 0; +} + +int ab_select_slot(void) +{ + struct bootloader_control *abc = NULL; + u32 crc32_le; + int slot, i, ret; + bool store_needed = false; + char slot_suffix[4]; + // uint32_t ab_info_addr = remap_get_phys_addr(AB_INFO_FLAG_ADDR); // 0xEB22FFFCU + + _disk_buffer = (uint8_t *)(DISK_BUFFER_ADDR); // 0xEB22E000U + mem_write32(AB_INFO_FLAG_ADDR, AB_INFO_FLAG_INIT); + ret = ab_control_create_from_disk(&abc); + if (ret < 0) { + /* + * This condition represents an actual problem with the code or + * the board setup, like an invalid partition information. + * Signal a repair mode and do not try to boot from either slot. + */ + return ret; + } + + crc32_le = ab_control_compute_crc(abc); + if (abc->crc32_le != crc32_le) { + ERROR("Invalid CRC-32 (expected %.8x, found %.8x)," + "re-initializing A/B metadata.\n", crc32_le, abc->crc32_le); + + ret = ab_control_default(abc); + if (ret < 0) { + // free(abc); + return -ENODATA; + } + store_needed = true; + } + + if (abc->magic != BOOT_CTRL_MAGIC) { + ERROR("Unknown A/B metadata: %.8x\n", abc->magic); + // free(abc); + return -ENODATA; + } + + if (abc->version > BOOT_CTRL_VERSION) { + ERROR("Unsupported A/B metadata version: %.8x\n", abc->version); + // free(abc); + return -ENODATA; + } + + /* + * At this point a valid boot control metadata is stored in abc, + * followed by other reserved data in the same block. We select a with + * the higher priority slot that + * - is not marked as corrupted and + * - either has tries_remaining > 0 or successful_boot is true. + * If the selected slot has a false successful_boot, we also decrement + * the tries_remaining until it eventually becomes unbootable because + * tries_remaining reaches 0. This mechanism produces a bootloader + * induced rollback, typically right after a failed update. + */ + + /* Safety check: limit the number of slots. */ + if (abc->nb_slot > ARRAY_SIZE(abc->slot_info)) { + abc->nb_slot = ARRAY_SIZE(abc->slot_info); + NOTICE("[%s:%d] abc->nb_slot > ARRAY_SIZE(abc->slot_info)\n", __func__, __LINE__); + store_needed = true; + } + + slot = -1; + for (i = 0; i < abc->nb_slot; ++i) { + if (abc->slot_info[i].verity_corrupted || + !abc->slot_info[i].tries_remaining) { + NOTICE("unbootable slot %d tries: %d, corrupt: %d\n", + i, abc->slot_info[i].tries_remaining, + abc->slot_info[i].verity_corrupted); + continue; + } + NOTICE("bootable slot %d pri: %d, tries: %d, " + "corrupt: %d, successful: %d\n", + i, abc->slot_info[i].priority, + abc->slot_info[i].tries_remaining, + abc->slot_info[i].verity_corrupted, + abc->slot_info[i].successful_boot); + + if (slot < 0 || + ab_compare_slots(&abc->slot_info[i], + &abc->slot_info[slot]) < 0) { + slot = i; + } + } + + if (slot >= 0 && !abc->slot_info[slot].successful_boot) { + ERROR("Attempting slot %d, tries remaining %d\n", + slot, abc->slot_info[slot].tries_remaining); + abc->slot_info[slot].tries_remaining--; + store_needed = true; + } + + if (slot >= 0) { + /* + * Legacy user-space requires this field to be set in the BCB. + * Newer releases load this slot suffix from the command line + * or the device tree. + */ + memset(slot_suffix, 0, sizeof(slot_suffix)); + slot_suffix[0] = BOOT_SLOT_NAME(slot); + if (memcmp(abc->slot_suffix, slot_suffix, sizeof(slot_suffix))) { + NOTICE("slot_suffix is differ(%s:%s)\n", + abc->slot_suffix, slot_suffix); + memcpy(abc->slot_suffix, slot_suffix, sizeof(slot_suffix)); + store_needed = true; + } + } + + if (store_needed) { + abc->crc32_le = ab_control_compute_crc(abc); + ab_control_store(abc); + crc32_le = AB_INFO_FLAG_STORE; + } + else + crc32_le = AB_INFO_FLAG_OK; + // free(abc); + + if (slot == 1) + crc32_le |= AB_INFO_SELECT_2nd; + mem_write32(AB_INFO_FLAG_ADDR, crc32_le); + + if (slot < 0) + return -EINVAL; + + return slot; +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/image_load.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/image_load.c new file mode 100644 index 0000000..9138ab0 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/image_load.c @@ -0,0 +1,535 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file image_load.c + * - Version : 0.14 + * @brief Loading image driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Modify macro definition name. + * : 30.09.2021 0.03 Support of eMMC boot. + * : 15.10.2021 0.04 Fix a problem with overwriting the load area + * information in RTOS. + * modify Error log of check_load_area. + * Modify the process of outputting load + * information of Optionbyte to function. + * : 03.12.2021 0.05 Modify function "check_load_area" to check the + * boundary value of RT-VRAM(for virtual buffer). + * Fixed judgment of the top/end of the + * forwarding destination. + * : 06.01.2022 0.06 Support for two-stage boot of G4MH. + * : 23.05.2022 0.07 Support for updating the memory map. + * : 21.06.2022 0.08 Modify some function's arguments and add + * macros. + * : 05.08.2022 0.09 Add TFMV/NTFMV minimum version table + * information to load_init function. + * : 22.09.2022 0.10 Fix address range check for V4H. + * : 21.08.2023 0.11 Add support for V4M. + * : 15.01.2024 0.12 Add image_id initialization to load_init + * function. + * : 19.12.2024 0.13 Add RTOS#1, RTOS#2 image. + * : 26.05.2025 0.14 Change key cert address of [CA_OPTIONAL_ID+2]. + *****************************************************************************/ + +/* indelude */ +#include +#include +#include +#include +#include +#include +#include + +#if (RCAR_SA9_TYPE == FLASH_BOOT) +#include +#include +#elif (RCAR_SA9_TYPE == EMMC_BOOT) +#include +#include +#include +#endif + +#define KEY_SIZE_FLG_MSK (0x00000003U) +#define KEY_SIZE_4096 (0x00000002U) +#define KEY_SIZE_3072 (0x00000001U) +#define KEY_SIZE_2048 (0x00000000U) +#define WORD_TO_BYTE (4U) +#define ERROR_PARAM (0U) +#define NOT_OVERLAP_FLAG (0U) +#define OVERLAP_FLAG (1U) +#define RAM_RANGE_OK (0U) +#define RAM_RANGE_NG (1U) +#if (BOOT_MCU != 0U) +#define RAM_MAX (5U) +#else +#define RAM_MAX (4U) +#endif /* (BOOT_MCU != 0U) */ + +/* Load Parameter of Secure data */ +#define SRC_ADDR_OF_SECURE_DATA_FOR_ICUMXB (SRC_TOP + 0x00340000U) +#define DST_ADDR_OF_SECURE_DATA_FOR_ICUMXB (0xEB2E0000U) +#if (BOOT_MCU != 0U) +#define SRC_ADDR_OF_SECURE_DATA_FOR_ICUMH (SRC_TOP + 0x00440000U) +/* The destination address of Flash to RAM in the ICUMH Secure data is the top address of RT-VRAM. */ +#endif + +static void get_info_from_cert(uint32_t cert_addr, uint32_t *size, + uint32_t *dest_addr); +static void check_src_addr_range(uint32_t src, uint32_t len, uint32_t src_end); +static void check_dst_addr_range(uint32_t dst, uint32_t len, uint32_t dst_end); +static void check_overlap_images(uint32_t dst, uint32_t len, uint32_t dst_end); + +uint32_t load_content_cert(int slot) +{ + uint32_t load_num; +#if (RCAR_SA9_TYPE == FLASH_BOOT) + load_num = load_content_cert_for_flash(slot); +#elif (RCAR_SA9_TYPE == EMMC_BOOT) + load_num = load_content_cert_for_emmc(); +#else + /* NoProcess */ +#endif + return load_num; +} +/* End of function load_content_cert(void) */ + +void load_image(LOAD_INFO* li) +{ + /* log output of load image for information */ +#if (RCAR_SA9_TYPE == FLASH_BOOT) + load_image_info_print_for_flash(li); +#elif (RCAR_SA9_TYPE == EMMC_BOOT) + load_image_info_print_for_emmc(li); +#endif + /* Check transfer range of image. */ + check_load_area(li); + + /* Image load start. */ + load_start(li); +} +/* End of function load_image(LOAD_INFO* li) */ + +void load_init(LOAD_INFO* li, int slot) +{ + uint32_t loop; + uint32_t buf; + + const char *image_name[MAX_PLACED] = { + [SECURE_FW_ID] = "Secure FW", + [RTOS_ID] = "RTOS", + [CA_PROGRAM_ID] = "Cx IPL", + [ICUMH_PROGRAM_ID] = "ICUMH", + [G4MH_PROGRAM_ID] = "G4MH(1st)", + [G4MH_PROGRAM_ID + 1] = "G4MH(2nd)", + [CA_OPTIONAL_ID] = "CA Program #1", + [CA_OPTIONAL_ID + 1] = "CA Program #2", + [CA_OPTIONAL_ID + 2] = "CA Program #3", + [CA_OPTIONAL_ID + 3] = "CA Program #4", + [CA_OPTIONAL_ID + 4] = "CA Program #5", + [CA_OPTIONAL_ID + 5] = "CA Program #6", + [CA_OPTIONAL_ID + 6] = "CA Program #7", + [CA_OPTIONAL_ID + 7] = "CA Program #8", + [TFMV_MIN_VER_TBL_ID] = "TFMV minimum version table", + [NTFMV_MIN_VER_TBL_ID] = "NTFMV minimum version table", +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + [RTOS1_ID] = "RTOS#1", + [RTOS2_ID] = "RTOS#2" +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + }; + + const uint32_t key_cert[MAX_PLACED] = { + [SECURE_FW_ID] = TFMV_KEY_CERT_ADDR, + [RTOS_ID] = TFMV_KEY_CERT_ADDR, + [CA_PROGRAM_ID] = TFMV_KEY_CERT_ADDR, + [ICUMH_PROGRAM_ID] = TFMV_KEY_CERT_ADDR, + [G4MH_PROGRAM_ID] = TFMV_KEY_CERT_ADDR, + [G4MH_PROGRAM_ID + 1] = TFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID] = TFMV_KEY_CERT_ADDR, /* bl31 */ +#if (RCAR_LSI == RCAR_S4) + [CA_OPTIONAL_ID + 1] = TFMV_KEY_CERT_ADDR, +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + [CA_OPTIONAL_ID + 1] = NTFMV_KEY_CERT_ADDR, /* u-boot */ +#endif +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + [CA_OPTIONAL_ID + 2] = NTFMV_KEY_CERT_ADDR, +#else + [CA_OPTIONAL_ID + 2] = TFMV_KEY_CERT_ADDR, /* tee-os */ +#endif +#if (BL2_LOAD_ENABLE == 0) + [CA_OPTIONAL_ID + 3] = NTFMV_KEY_CERT_ADDR, +#else + [CA_OPTIONAL_ID + 3] = TFMV_KEY_CERT_ADDR, /* ca76-loader */ +#endif + [CA_OPTIONAL_ID + 4] = NTFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID + 5] = NTFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID + 6] = NTFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID + 7] = NTFMV_KEY_CERT_ADDR, + [TFMV_MIN_VER_TBL_ID] = TFMV_KEY_CERT_ADDR, + [NTFMV_MIN_VER_TBL_ID] = NTFMV_KEY_CERT_ADDR, +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + [RTOS1_ID] = TFMV_KEY_CERT_ADDR, + [RTOS2_ID] = TFMV_KEY_CERT_ADDR +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + }; + + /* Set Load info parameter */ + for (loop = 0; loop < MAX_PLACED; loop++) + { + li[loop].name = image_name[loop]; + li[loop].key_cert_addr = key_cert[loop]; + li[loop].cnt_cert_addr = get_logic_cont_cert_addr(loop); + get_info_from_cert(li[loop].cnt_cert_addr, &li[loop].image_size, &li[loop].boot_addr); + buf = get_src_addr_offset_in_cert(loop); + li[loop].src_addr = (SRC_TOP + mem_read32(buf)); +#if (RCAR_SA9_TYPE == FLASH_BOOT) + li[loop].src_addr += (slot * CONTENT_CERT_2nd_OFFSET); +#endif + li[loop].image_id = loop; +#if (RCAR_SA9_TYPE == EMMC_BOOT) + buf = get_part_num_in_cert(loop); + li[loop].part_num = mem_read32(buf); +#endif + } +}/* End of function load_init(LOAD_INFO* li) */ + + +void check_load_area(const LOAD_INFO* li) +{ + uint32_t src; + uint32_t dst; + uint32_t len; + uint32_t src_end; + uint32_t dst_end; + + src = li->src_addr; + dst = li->boot_addr; + len = li->image_size; + + /* Check whether source is overflow. */ + check_overflow(src, len, &src_end, __func__); + + /* Check whether destination is overflow. */ + check_overflow(dst, len, &dst_end, __func__); + + /* Check source address range. */ + check_src_addr_range(src, len, src_end); + + /* Check destination address range. */ + check_dst_addr_range(dst, len, dst_end); + + /* Check whether overlap destination address and images that have been loaded. */ + check_overlap_images(dst, len, dst_end); +} +/* End of function check_load_area(const LOAD_INFO* li) */ + +static void get_info_from_cert(uint32_t cert_addr, uint32_t *size, + uint32_t *dest_addr) +{ + uint32_t val; + uint32_t certInfo1; + uint32_t pSize; + uint32_t pDestL; + + /* Get key length of content certificate. */ + val = mem_read32(cert_addr + CERT_INFO_FLG_OFFSET); + certInfo1 = (val >> KEY_SIZE_BIT_SHIFT) & KEY_SIZE_FLG_MSK; + + /* Get the transfer address and transfer size from + the certificate in accordance with the key length. */ + if (KEY_SIZE_4096 == certInfo1) /* key size = 4096 */ + { + pSize = cert_addr + CERT_INFO_SIZE_OFFSET2; + *size = mem_read32(pSize) * WORD_TO_BYTE; + pDestL = cert_addr + CERT_INFO_DST_OFFSET2; + *dest_addr = mem_read32(pDestL); + } + else if (KEY_SIZE_3072 == certInfo1) /* key size = 3072 */ + { + pSize = cert_addr + CERT_INFO_SIZE_OFFSET1; + *size = mem_read32(pSize) * WORD_TO_BYTE; + pDestL = cert_addr + CERT_INFO_DST_OFFSET1; + *dest_addr = mem_read32(pDestL); + } + else if (KEY_SIZE_2048 == certInfo1) /* key size = 2048 */ + { + pSize = cert_addr + CERT_INFO_SIZE_OFFSET; + *size = mem_read32(pSize) * WORD_TO_BYTE; + pDestL = cert_addr + CERT_INFO_DST_OFFSET; + *dest_addr = mem_read32(pDestL); + } + else + { + *size = ERROR_PARAM; + *dest_addr = ERROR_PARAM; + } +} +/* End of function get_info_from_cert(uint32_t cert_addr, uint32_t *size, uint32_t *dest_addr) */ + +void load_start(const LOAD_INFO* li) +{ +#if (RCAR_SA9_TYPE == FLASH_BOOT) + dma_trans_start(li->boot_addr, li->src_addr, li->image_size); +#elif (RCAR_SA9_TYPE == EMMC_BOOT) + uint32_t rtn_val; + uint32_t sector_count; + uint32_t fraction; + + /* Converted to number of sectors transferred. */ + sector_count = li->image_size >> EMMC_SECTOR_SIZE_SHIFT; + fraction = li->image_size % EMMC_SECTOR_SIZE; + /* Add 1 if there is a fraction */ + if(0U != fraction) + { + sector_count += 1U; + } + + rtn_val = emmc_trans_data(li->part_num, (li->src_addr >> EMMC_SECTOR_SIZE_SHIFT), + li->boot_addr, sector_count); + + if(EMMC_DEV_OK != rtn_val) + { + ERROR("load_start(emmc_trans_data error).\r\n"); + panic; + } +#else + /* NoProcess */ +#endif +}/* End of function load_start(LOAD_INFO* li) */ + +void load_end(void) +{ +#if (RCAR_SA9_TYPE == FLASH_BOOT) + dma_trans_end_check(); +#else + /* NoProcess */ +#endif +}/* End of function load_end(void) */ + +void load_securedata(uint32_t target_id, int slot) +{ + LOAD_INFO tmp_li; + + if(target_id == SECURE_FW_ID) /* When secure data transfer for ICUMXB FW. */ + { + tmp_li.image_size = SECUREDATA_SIZE; + tmp_li.src_addr = SRC_ADDR_OF_SECURE_DATA_FOR_ICUMXB; +#if (RCAR_SA9_TYPE == FLASH_BOOT) + tmp_li.src_addr += (slot * CONTENT_CERT_2nd_OFFSET); +#endif + tmp_li.boot_addr =DST_ADDR_OF_SECURE_DATA_FOR_ICUMXB; +#if (RCAR_SA9_TYPE == EMMC_BOOT) + tmp_li.part_num = EMMC_PARTITION_1; +#endif + } +#if (BOOT_MCU != 0U) + else if(target_id == ICUMH_PROGRAM_ID) /* When secure data transfer for ICUMH FW. */ + { + tmp_li.image_size = SECUREDATA_SIZE; + tmp_li.src_addr = SRC_ADDR_OF_SECURE_DATA_FOR_ICUMH; + tmp_li.boot_addr = RTVRAM_BASE; +#if (RCAR_SA9_TYPE == EMMC_BOOT) + tmp_li.part_num = EMMC_PARTITION_1; +#endif + } +#endif + else + { + ERROR("Failed input parameter.\n"); + panic; + } + + load_start(&tmp_li); +}/* End of function load_securedata(uint32_t target_id) */ + +void check_overflow(uint32_t addr, uint32_t len, uint32_t *end_addr, const char *func_name) +{ + /* Pre confirmation */ + if (addr > (UINT32_MAX - len)) + { + ERROR("1:overflow is occurred in %s.\n", func_name); + ERROR("1:address = 0x%x size = 0x%x\n", addr, len); + panic; + } + else + { + *end_addr = addr + len - 1U; + } + /* Post confirmation */ + if (*end_addr < addr) + { + ERROR("2:overflow is occurred in %s.\n", func_name); + ERROR("2:address = 0x%x size = 0x%x\n", addr, len); + panic; + } +} +/* End of function check_overflow(uint32_t addr, uint32_t len, uint32_t *end_addr, char *func_name) */ + +static void check_src_addr_range(uint32_t src, uint32_t len, uint32_t src_end) +{ + + /* Check image size */ + if (len == 0U) + { + ERROR("image size error\n"); + panic; + } + +#if (RCAR_SA9_TYPE == FLASH_BOOT) + if ((src < SRC_TOP) || (SRC_END < src_end)) +#elif (RCAR_SA9_TYPE == EMMC_BOOT) + if (SRC_END < src_end) +#endif + { + ERROR("check load area (source address)\n"); + ERROR("source address = 0x%x image size = 0x%x\n", src, len); + panic; + } +} +/* End of function check_src_addr_range(uint32_t src, uint32_t len, uint32_t src_end) */ + +static void check_dst_addr_range(uint32_t dst, uint32_t len, uint32_t dst_end) +{ + uint32_t rge_chk_flg; + uint32_t loop; + + /* The memory range of destination. */ + const ADDRESS_RANGE add_list[RAM_MAX] = { + [TARGET_MEM_DRAM] = {DRAM_BASE, DRAM_END}, + [TARGET_MEM_RTSRAM] = {RTSRAM_BASE, RTSRAM_END}, + [TARGET_MEM_RTVRAM] = {RTVRAM_VBUF_TOP, RTVRAM_VBUF_END}, + [TARGET_MEM_SYSRAM] = {SYSRAM_BASE, SYSRAM_END}, +#if (BOOT_MCU != 0U) + [TARGET_MEM_CODESRAM] = {CODESRAM_BASE, CODESRAM_END} +#endif /* (BOOT_MCU != 0U) */ + }; + + /* Check image size */ + if (len == 0U) + { + ERROR("image size error\n"); + panic; + } + + rge_chk_flg = RAM_RANGE_NG; + + for(loop = 0; loop < RAM_MAX; loop++) + { + if (add_list[loop].topadd <= dst) + { + if(dst_end <= add_list[loop].endadd) + { + rge_chk_flg = RAM_RANGE_OK; + break; + } + } + } + + if(rge_chk_flg != RAM_RANGE_OK) + { + ERROR("check load area (destination address)\n"); + ERROR("destination address = 0x%x image size = 0x%x\n", dst, len); + panic; + } +} +/* End of function check_dst_addr_range(uint32_t dst, uint32_t len, uint32_t dst_end) */ + +static void check_overlap_images(uint32_t dst, uint32_t len, uint32_t dst_end) +{ + uint32_t overlap; + uint32_t loop; + + static uint32_t s_num = 1U; + + static ADDRESS_RANGE s_placed_image[MAX_PLACED + 1] = { + [0] = {IPL_TOP, IPL_END}, + [1] = {0U,0U}, + [2] = {0U,0U}, + [3] = {0U,0U}, + [4] = {0U,0U}, + [5] = {0U,0U}, + [6] = {0U,0U}, + [7] = {0U,0U}, + [8] = {0U,0U}, + [9] = {0U,0U}, + [10] = {0U,0U}, + [11] = {0U,0U}, + [12] = {0U,0U}, + [13] = {0U,0U}, + [14] = {0U,0U}, + [15] = {0U,0U}, + [16] = {0U,0U} + }; + + overlap = NOT_OVERLAP_FLAG; + loop = 0U; + do + { + /* check overlap */ + if ((dst >= s_placed_image[loop].topadd) && (dst <= s_placed_image[loop].endadd)) + { + overlap = OVERLAP_FLAG; + } + else if ((dst_end >= s_placed_image[loop].topadd) && (dst_end <= s_placed_image[loop].endadd)) + { + overlap = OVERLAP_FLAG; + } + else if ((dst < s_placed_image[loop].topadd) && (s_placed_image[loop].endadd < dst_end)) + { + overlap = OVERLAP_FLAG; + } + else + { + loop++; + } + } while ((loop < s_num) && (overlap == NOT_OVERLAP_FLAG)); + + /* Check the overlap flag. * + * Parameters are error if overwrite occurred. * + * Otherwise, add parameters of the image to be loaded into Placed_image. */ + if (overlap == NOT_OVERLAP_FLAG) + { + s_placed_image[s_num].topadd = dst; + s_placed_image[s_num].endadd = dst_end; + INFO("[0x%x] topadd = 0x%x endadd = 0x%x\n", s_num, + s_placed_image[s_num].topadd, s_placed_image[s_num].endadd); + s_num++; + } + else + { + ERROR("check load area (overlap)\n"); + ERROR("destination address = 0x%x image size = 0x%x\n", dst, len); + ERROR("overlapped image is [%x]\n", loop); + ERROR("top address = 0x%x end address = 0x%x\n", + s_placed_image[loop].topadd, s_placed_image[loop].endadd); + panic; + } +} +/* End of function check_overlap_images(uint32_t dst, uint32_t len, uint32_t dst_end) */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/image_load_emmc.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/image_load_emmc.c new file mode 100644 index 0000000..45366b7 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/image_load_emmc.c @@ -0,0 +1,145 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load for emmc function + ******************************************************************************/ +/****************************************************************************** + * @file image_load_emmc.c + * - Version : 0.04 + * @brief Image load for emmc function. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 30.09.2021 0.01 First Release + * : 23.05.2022 0.02 Support for updating the memory map. + * : 05.08.2022 0.03 Add load_ver_tbl_cert_for_emmc function. + * : 30.09.2022 0.04 Modify size output in + * load_ver_tbl_cert_for_emmc function. + *****************************************************************************/ + +/* indelude */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void load_ver_tbl_cert_for_emmc(void); + +uint32_t load_content_cert_for_emmc(void) +{ + uint32_t load_num; + uint32_t phys_dst; + uint32_t phys_src; + uint32_t size; + uint32_t part; + + /* source address.(0x00240000/sector:0x1200) */ + phys_src = EMMC_CONTENT_CERT_SECTOR_NUMBER; + /* Get physical address of transfer destination. */ + phys_dst = remap_get_phys_addr(SA9_DEST_ADDR); + /* transfer size(number of secters) */ + size = CONTENT_CERT_INFO_SIZE >> EMMC_SECTOR_SIZE_SHIFT; + /* The partition that contains A. */ + part = (uint32_t)PARTITION_ID_BOOT_1; + + /* Load content cert header */ + (void)emmc_trans_data(part, phys_src, phys_dst, size); + + NOTICE( + "======== content cert info ========\n" + "destination address:0x%08x\n" + "physical destination address:0x%08x\n" + "source address:(p:%d)0x%08x\n" + "size:0x%08x\n", SA9_DEST_ADDR, phys_dst, + PARTITION_ID_BOOT_1, EMMC_CONTENT_CERT_ADDR, CONTENT_CERT_INFO_SIZE); + + load_num = mem_read32(SA9_DEST_ADDR); + + /* Check number of image load. + In case of number of image load is 0, error of transfer parameter. + In case of number of image loads is higher than 8, + the transfer parameter error. */ + if ((load_num == 0U) || (load_num > CA_MAX_IMAGE)) + { + ERROR("Content cert info 'load image num' fault.\n"); + ERROR("load image num = %d\n",load_num); + panic; + } + + /* Increase forwarding address by the size of cert header */ + phys_src += (CONTENT_CERT_INFO_SIZE >> EMMC_SECTOR_SIZE_SHIFT); + phys_dst += CONTENT_CERT_INFO_SIZE; + + /* Transfer size calculation for SA9 * + * TFMV key + NTFMV key + minimum version table + (content cert * number of loads) */ + size = ((KEY_CERT_SIZE * 2U) + MIN_VER_TBL_SIZE + + ((NUM_OF_ALWAYS_LOAD_CERT + load_num) * CONTENT_CERT_SIZE)); + + (void)emmc_trans_data(part, phys_src, phys_dst, size >> EMMC_SECTOR_SIZE_SHIFT); + + NOTICE( + "======== content cert ========\n" + "address:0x%08x size:0x%08x\n", phys_dst, size); + + /* Load content cert of Software minimum version table */ + load_ver_tbl_cert_for_emmc(); + + return load_num; +} +/* End of function load_content_cert_for_emmc(void) */ + +static void load_ver_tbl_cert_for_emmc(void) +{ +#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) + uint32_t phys_dst; + uint32_t phys_src; + uint32_t size; + uint32_t part; + + /* source address.(0x0024D000/sector:0x1268) */ + phys_src = EMMC_VER_TBL_CNT_CERT_SEC_NUM; + /* Get physical address of transfer destination. */ + phys_dst = remap_get_phys_addr(SA9_DEST_ADDR + EMMC_VER_TBL_OFFSET); + /* transfer size(number of secters) */ + size = (CONTENT_CERT_SIZE * 2U) >> EMMC_SECTOR_SIZE_SHIFT; + /* The partition that contains content cert of Software minimum version table. */ + part = (uint32_t)PARTITION_ID_BOOT_1; + + /* Load content cert of Software minimum version table */ + (void)emmc_trans_data(part, phys_src, phys_dst, size); + + NOTICE("======== content cert of SW version table ========\n" + "address:0x%08x size:0x%08x\n", phys_dst, (size << EMMC_SECTOR_SIZE_SHIFT)); + +#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */ +} +/* End of function load_ver_tbl_cert_for_emmc(void) */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/image_load_flash.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/image_load_flash.c new file mode 100644 index 0000000..2fa46bc --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/image_load/image_load_flash.c @@ -0,0 +1,180 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load for Flash function + ******************************************************************************/ +/****************************************************************************** + * @file image_load_flash.c + * - Version : 0.04 + * @brief Image load for Flash function. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 30.09.2021 0.01 First Release + * : 23.05.2022 0.02 Support for updating the memory map. + * : 05.08.2022 0.03 Add load_ver_tbl_cert_for_flash function. + * : 20.12.2024 0.04 Add support for booting CR52 3 cores. + *****************************************************************************/ + +/* indelude */ +#include +#include +#include +#include +#include +#include +#include "image_load.h" + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +static void load_rtos12_cert_for_flash(void); +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +static void load_ver_tbl_cert_for_flash(int slot); + +uint32_t load_content_cert_for_flash(int slot) +{ + uint32_t load_num; + uint32_t phys_dst; + uint32_t phys_src; + uint32_t size; + + /* source address.(0x08240000) */ + phys_src = FLASH_CONTENT_CERT_ADDR + (slot * CONTENT_CERT_2nd_OFFSET); + /* Get physical address of transfer destination. */ + phys_dst = remap_get_phys_addr(SA9_DEST_ADDR); + /* transfer size */ + size = CONTENT_CERT_INFO_SIZE; + /* Load content cert header */ + dma_trans_start(phys_dst, phys_src, size); + + NOTICE( + "======== content cert info ========\n" + "destination address:0x%08x\n" + "physical destination address:0x%08x\n" + "source address:0x%08x\n" + "size:0x%08x\n", SA9_DEST_ADDR, phys_dst, phys_src, size); + + + /* End loading cert header */ + load_end(); + + load_num = mem_read32(SA9_DEST_ADDR); + + + /* Check number of image load. + In case of number of image load is 0, error of transfer parameter. + In case of number of image loads is higher than 8, + the transfer parameter error. */ + if ((load_num == 0U) || (load_num > CA_MAX_IMAGE)) + { + ERROR("Content cert info 'load image num' fault.\n"); + ERROR("load image num = %d\n",load_num); + panic; + } + + /* Increase forwarding address by the size of cert header */ + phys_src += CONTENT_CERT_INFO_SIZE; + phys_dst += CONTENT_CERT_INFO_SIZE; + + /* Transfer size calculation for SA9 * + * TFMV key + NTFMV key + TFMV/NTFMV minimum version table + (content cert * number of loads) */ + size = ((KEY_CERT_SIZE * 2U) + MIN_VER_TBL_SIZE + + ((NUM_OF_ALWAYS_LOAD_CERT + load_num) * CONTENT_CERT_SIZE)); + + /* Load SA9. */ + dma_trans_start(phys_dst, phys_src, size); + + /* End loading content cert */ + load_end(); + + NOTICE("======== content of SA9 ========\n" + "address:0x%08x size:0x%08x\n", phys_dst, size); + + /* Load content cert of Software minimum version table */ + load_ver_tbl_cert_for_flash(slot); + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + /* Load content cert of RTOS#1 and RTOS#2 */ + load_rtos12_cert_for_flash(); +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + + return load_num; +} +/* End of function load_content_cert_for_flash(void) */ + +static void load_ver_tbl_cert_for_flash(int slot) +{ +#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) + uint32_t phys_dst; + uint32_t phys_src; + uint32_t size; + + /* Source address.(0x0824D000) */ + phys_src = FLASH_VER_TBL_CNT_CERT_ADDR + (slot * CONTENT_CERT_2nd_OFFSET); + /* Get physical address of transfer destination. */ + phys_dst = remap_get_phys_addr(SA9_DEST_ADDR + VER_TBL_CNT_CERT_OFFSET); + /* transfer size */ + size = CONTENT_CERT_SIZE * 2U; + + /* Load content cert of Software minimum version table. */ + dma_trans_start(phys_dst, phys_src, size); + + /* End loading content cert */ + load_end(); + + NOTICE("======== content cert of SW version table ========\n" + "address:0x%08x size:0x%08x\n", phys_dst, size); + +#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */ +} +/* End of function load_ver_tbl_cert_for_flash(void) */ + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +static void load_rtos12_cert_for_flash(void) +{ + uint32_t phys_dst; + uint32_t phys_src; + uint32_t size; + + /* Source address.(0x0824E000) */ + phys_src = FLASH_RTOS12_CNT_CERT_ADDR; + /* Get physical address of transfer destination. */ + phys_dst = remap_get_phys_addr(SA9_DEST_ADDR + RTOS12_CNT_CERT_OFFSET); + /* transfer size */ + size = CONTENT_CERT_SIZE * 2U; /* RTOS#1 and RTOS#2 */ + + /* Load content cert of Software minimum version table. */ + dma_trans_start(phys_dst, phys_src, size); + + /* End loading content cert */ + load_end(); + + NOTICE("======== content cert of RTOS#1 and RTOS#2 ========\n" + "address:0x%08x size:0x%08x\n", phys_dst, size); + +} +/* End of function load_rtos12_cert_for_flash(void) */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/access_protection.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/access_protection.h new file mode 100644 index 0000000..9d5f08c --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/access_protection.h @@ -0,0 +1,53 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Access Protection function header + ******************************************************************************/ + +#include + +#ifndef ACCESS_PROTECTION_ID_H__ +#define ACCESS_PROTECTION_ID_H__ + +#define PROTECTION_DISABLE (0U) +#define PROTECTION_ENABLE (1U) + +#define RGID_0 (0U) +#define RGID_1 (1U) +#define RGID_2 (2U) +#define RGID_INVALID (0xFFFFFFFFU) + +#define CPG_PROTECTION (63U) +#define SYSC_PROTECTION (5U) +#define RESET_PROTECTION (29U) +#define WRITE_ENABLE (0xFFFFFFFFU) + +void rgid_protection(void); +void ram_protection(void); +void rgid_protection_final(void); +void ram_protection_final(void); +void set_master_rgid_4_tfr_mod(void); +void icu_remove_write_access(void); + +#endif /* ACCESS_PROTECTION_ID_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/android_ab.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/android_ab.h new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/android_bootloader_message.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/android_bootloader_message.h new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ap_system_core_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ap_system_core_register.h new file mode 100644 index 0000000..01fa5d5 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ap_system_core_register.h @@ -0,0 +1,43 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : AP-System Core register header + ******************************************************************************/ + +#ifndef AP_SYSTEM_CORE_REGISTER_H_ +#define AP_SYSTEM_CORE_REGISTER_H_ + +#include + +#define AP_CORE_BASE (BASE_AP_CORE_ADDR) /* 0xE6280000 */ + +#define AP_CORE_APSREG_CCI500_AUX (AP_CORE_BASE + 0x00009010U) +#define AP_CORE_APSREG_P_CCI500_AUX (AP_CORE_BASE + 0x00029010U) + +static inline uint32_t ap_core_get_ap_cluster_n_aux0_addr(uint32_t num) +{ + return (AP_CORE_BASE + 0x00000010U + (num * 0x1000U)); +} + +#endif /* AP_SYSTEM_CORE_REGISTER_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/avs.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/avs.h new file mode 100644 index 0000000..cc5bfea --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/avs.h @@ -0,0 +1,34 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : AVS driver header + ******************************************************************************/ + +#ifndef AVS_DRIVER_H__ +#define AVS_DRIVER_H__ + +void avs_low_power_mode_setting(void); + +#endif /* AVS_DRIVER_H__ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/axmm_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/axmm_register.h new file mode 100644 index 0000000..8cc39fe --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/axmm_register.h @@ -0,0 +1,82 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : AXMM register header + ******************************************************************************/ + +#ifndef AXMM_REGISTER_H__ +#define AXMM_REGISTER_H__ + +#include +#include + +/* RT-SRAM register base address */ +#define AXMM_BASE (BASE_AXMM_ADDR) + +#define AXMM_DPTDIVCR (AXMM_BASE + 0x6000U) +#define AXMM_DPTRGNCR (AXMM_BASE + 0x6100U) +#define AXMM_DPTSECCR (AXMM_BASE + 0x6200U) +#define AXMM_SPTDIVCR (AXMM_BASE + 0x6300U) +#define AXMM_SPTRGNCR (AXMM_BASE + 0x6400U) +#define AXMM_SPTSECCR (AXMM_BASE + 0x6500U) + + +#define AXMM_DPTDIVCR_DIVADDR_MASK (0x003FFFFFU) +#define AXMM_DPTSECCR_SECGRP_MASK (0x00000F00U) +#define AXMM_DPTSECCR_SECGWP_MASK (0x0000000FU) +#define AXMM_SPTDIVCR_DIVADDR_MASK (0x000FFFFFU) +#define AXMM_SPTSECCR_SECGRP_MASK (0x00000F00U) +#define AXMM_SPTSECCR_SECGWP_MASK (0x0000000FU) + +static inline uint32_t get_dptdivcr_addr(uint32_t num) +{ + return ((AXMM_DPTDIVCR + (num * 4U))); +} + +static inline uint32_t get_dptrgncr_addr(uint32_t num) +{ + return ((AXMM_DPTRGNCR + (num * 4U))); +} + +static inline uint32_t get_dptseccr_addr(uint32_t num) +{ + return ((AXMM_DPTSECCR + (num * 4U))); +} + +static inline uint32_t get_sptdivcr_addr(uint32_t num) +{ + return ((AXMM_SPTDIVCR + (num * 4U))); +} + +static inline uint32_t get_sptrgncr_addr(uint32_t num) +{ + return ((AXMM_SPTRGNCR + (num * 4U))); +} + +static inline uint32_t get_sptseccr_addr(uint32_t num) +{ + return ((AXMM_SPTSECCR + (num * 4U))); +} + +#endif /* AXMM_REGISTER_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/bit.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/bit.h new file mode 100644 index 0000000..6c1b79f --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/bit.h @@ -0,0 +1,77 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2015-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Bit definnition header + ******************************************************************************/ +/****************************************************************************** + * @file bit.h + * - Version : 0.03 + * @brief Bit definnition header + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 16.02.2022 0.01 First Release + * : 08.04.2022 0.02 Add include guard. + * : 09.11.2022 0.03 License notation change. + *****************************************************************************/ + +#ifndef BIT_H_ +#define BIT_H_ + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#endif /* BIT_H_ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cnf_tbl.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cnf_tbl.h new file mode 100644 index 0000000..20cc4f8 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cnf_tbl.h @@ -0,0 +1,160 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table header + ******************************************************************************/ + +#ifndef CNF_TBL_H_ +#define CNF_TBL_H_ + +#include +#include + +typedef struct{ + uint32_t reg_addr; /* register address(for SIC remap) */ + uint32_t value; /* setting value */ +} CONFIGURATION_SETTING_TABLE; + +typedef struct{ + uint64_t fix; + uint64_t be; +} QOS_SETTING_TABLE; + +typedef struct{ + uint32_t addr; /* address of Region ID registers.(for SIC Remap) */ + uint32_t value; /* setting value of Region ID registers. */ +} REGION_ID_SETTING_TABLE; + +typedef struct { + uint32_t rw_val; + uint32_t sec_val; +}RAM_PROTECTION_VALUE_FORMAT; + +typedef struct { + uint32_t read_val; + uint32_t write_val; +}RTRAM_PROTECTION_VALUE_FORMAT; + +typedef struct { + uint32_t addr; + RTRAM_PROTECTION_VALUE_FORMAT setting_value; +}RTRAM_PROTECTION_STRUCTUR; + +typedef struct { + uint32_t addr; + RAM_PROTECTION_VALUE_FORMAT setting_value; +}SYSTEM_RAM_PROTECTION_STRUCTUR; + +typedef struct { + uint64_t addr; + RAM_PROTECTION_VALUE_FORMAT setting_value; +}DRAM_PROTECTION_STRUCTUR; + +#if (RCAR_LSI == RCAR_S4) +#define QOS_TBL_MAX (48U) /* Max setting number of QoS Bank registers. */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define QOS_TBL_MAX (125U) /* Max setting number of QoS Bank registers. */ +#endif /* RCAR_LSI == RCAR_S4 */ + +#if (RCAR_LSI == RCAR_S4) +#define RGID_M_MAX (44U) /* Max number of Region registers. (Master) */ +#define RGID_R_MAX (606U) /* Max number of Region registers. (Read) */ +#define RGID_W_MAX (606U) /* Max number of Region registers. (Write) */ +#define RGID_SEC_MAX (633U) /* Max number of Region registers. (Secure) */ +#define RGID_AXI_MAX (54U) /* Max number of Region registers. (Read/Write for AXI-bus) */ +#elif (RCAR_LSI == RCAR_V4H) +#define RGID_M_MAX (77U) /* Max number of Region registers. (Master) */ +#define RGID_R_MAX (908U) /* Max number of Region registers. (Read) */ +#define RGID_W_MAX (907U) /* Max number of Region registers. (Write) */ +#define RGID_SEC_MAX (957U) /* Max number of Region registers. (Secure) */ +#define RGID_AXI_MAX (98U) /* Max number of Region registers. (Read/Write for AXI-bus) */ +#define RGID_GID_MAX (2U) /* Max number of Region registers. (CCI MPU GID register) */ +#elif (RCAR_LSI == RCAR_V4M) +#define RGID_M_MAX (85U) /* Max number of Region registers. (Master) */ +#define RGID_R_MAX (805U) /* Max number of Region registers. (Read) */ +#define RGID_W_MAX (804U) /* Max number of Region registers. (Write) */ +#define RGID_SEC_MAX (819U) /* Max number of Region registers. (Secure) */ +#define RGID_AXI_MAX (90U) /* Max number of Region registers. (Read/Write for AXI-bus) */ +#define RGID_GID_MAX (1U) /* Max number of Region registers. (CCI MPU GID register) */ +#endif /* (RCAR_LSI == RCAR_S4) */ + +#define RAM_PROTECTION_MAX (16U) /* Max number of RAM Protection registers. (RT-SRAM/RT-VRAM/SystemRAM) */ +#define DRAM_PROTECTION_MAX (64U) /* Max number of RAM Protection registers. (SDRAM) */ + +#if (RCAR_LSI == RCAR_S4) +#define FDT_REG_MAX (102U) +#elif (RCAR_LSI == RCAR_V4H) +#define FDT_REG_MAX (120U) +#elif (RCAR_LSI == RCAR_V4M) +#define FDT_REG_MAX (72U) +#endif +#if (RCAR_LSI == RCAR_V4H) +#define INTEN_REG_MAX (401U) +#elif (RCAR_LSI == RCAR_V4M) +#define INTEN_REG_MAX (375U) +#endif /* (RCAR_LSI == RCAR_V4H) */ + +#if (RCAR_LSI == RCAR_V4H) +#define IMP_MASTER_MAX (19U) +#define IMP_SLAVE_MAX (38U) +#endif /* (RCAR_LSI == RCAR_V4H) */ + +#if (RCAR_LSI == RCAR_V4H) +#define IPMMU_RGID_MAX (11U) +#elif (RCAR_LSI == RCAR_V4M) +#define IPMMU_RGID_MAX (10U) +#endif /* (RCAR_LSI == RCAR_V4H) */ + +extern const QOS_SETTING_TABLE g_qosbw_tbl[QOS_TBL_MAX]; +extern const QOS_SETTING_TABLE g_qoswt_tbl[QOS_TBL_MAX]; + +extern const REGION_ID_SETTING_TABLE g_rgid_m_tbl[RGID_M_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_r_tbl[RGID_R_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_w_tbl[RGID_W_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[RGID_SEC_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[RGID_AXI_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_gid_tbl[RGID_GID_MAX]; +extern const uint32_t g_rgid_rtdma_setting_value[RTDMA_MODULE_MAX][RTDMA_CH_MAX][2U]; +extern const uint32_t g_rgid_sysdma_setting_value[SYSDMA_MODULE_MAX][SYSDMA_CH_MAX][2U]; +extern const RTRAM_PROTECTION_STRUCTUR g_rtsram_protection_table[RAM_PROTECTION_MAX]; +extern const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table_1[RAM_PROTECTION_MAX]; +#if (RCAR_LSI == RCAR_S4) +extern const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table_2[RAM_PROTECTION_MAX]; +#endif +extern const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX]; +extern const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX]; +extern const CONFIGURATION_SETTING_TABLE g_fdt_tbl[FDT_REG_MAX]; +extern const CONFIGURATION_SETTING_TABLE g_inten_tbl[INTEN_REG_MAX]; +#if (RCAR_LSI == RCAR_V4H) +extern const REGION_ID_SETTING_TABLE g_imp_rgid_m_tbl[IMP_MASTER_MAX]; +extern const REGION_ID_SETTING_TABLE g_imp_rgid_s_tbl[IMP_SLAVE_MAX]; +#endif /* (RCAR_LSI == RCAR_V4H) */ +extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX]; +extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX]; +extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX]; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#endif /* CNF_TBL_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpg.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpg.h new file mode 100644 index 0000000..254f41d --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpg.h @@ -0,0 +1,57 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : CPG driver header + ******************************************************************************/ +#ifndef CPG_H_ +#define CPG_H_ + +#include +#include +#include + +#define RPC_CLK_160MHZ (0x00000013U) /* RPCphi = 160MHz RPCD2phi = 80MHZ */ + +/* Prototype */ +void cpg_init(void); + +/* Inline function */ +static inline void cpg_reg_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t data) +{ + mem_write32(CPG_CPGWPR, ~data); + mem_write32(mstpcr, data); + while ((mem_read32(mstpsr) & ~(uint32_t)(data)) != 0U) + { + /* Loop to wait for confirmation that changes to "MSTPCRn" are reflected in "MSTPSRn". */ + } +} + +/* Inline function */ +static inline void apmu_reg_write(uint32_t reg, uint32_t data) +{ + mem_write32(APMU_WPR, ~data); + mem_write32(reg, data); +} + +#endif /* CPG_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpg_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpg_register.h new file mode 100644 index 0000000..690dea2 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpg_register.h @@ -0,0 +1,129 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : CPG register header + ******************************************************************************/ + +#ifndef CPG_REGISTER_H__ +#define CPG_REGISTER_H__ + +#include + +/* CPG base address */ +/* 0xE6150000 */ +#define CPG_BASE (BASE_CPG_ADDR) + +/* Domain Offset Addresses */ +#define D0 (0x4000U * 0U) +#define D1 (0x4000U * 1U) +#define D2 (0x4000U * 2U) +#define D3 (0x4000U * 3U) + +/* CPG write protect */ +#define CPG_CPGWPR (CPG_BASE + 0x0000U + D0) +/* CPG write protect control */ +#define CPG_CPGWPCR (CPG_BASE + 0x0004U + D0) + +/* Module Stop Control register */ +/* Registers of domain 0 */ +#define CPG_MSTPCR5D0 (CPG_BASE + 0x2D14U + D0) /* HSCIF0, I2C3 */ +#define CPG_MSTPCR6 (CPG_BASE + 0x2D18U) /* R/W 32 Domain0 module stop control register 6 */ +#define CPG_MSTPCR7D0 (CPG_BASE + 0x2D1CU + D0) /* SCIF0 */ +#define CPG_MSTPCR28D0 (CPG_BASE + 0x2D70U + D0) /* FCPR */ + +/* Module Stop Status register */ +/* Registers of domain 0 */ +#define CPG_MSTPSR5D0 (CPG_BASE + 0x2E14U + D0) /* HSCIF0, I2C3 */ +#define CPG_MSTPSR6 (CPG_BASE + 0x2E18U) /* R 32 Module stop status register 6 */ +#define CPG_MSTPSR7D0 (CPG_BASE + 0x2E1CU + D0) /* SCIF0 */ +#define CPG_MSTPSR28D0 (CPG_BASE + 0x2E70U + D0) /* FCPR */ + +/* Module standby , Software reset */ +#define CPG_SRCR6 (CPG_BASE + 0x2C18U) /* R/W 32 Software reset register 6 */ +#define CPG_SRCR11 (CPG_BASE + 0x2C2CU) +#define CPG_SRSTCLR6 (CPG_BASE + 0x2C98U) /* W 32 Software reset clearing register 6 */ +#define CPG_SRSTCLR11 (CPG_BASE + 0x2CACU) +#if (RCAR_LSI == RCAR_V4H) +#define CPG_SRCR28 (CPG_BASE + 0x2C70U) +#define CPG_SRCR29 (CPG_BASE + 0x2C74U) +#endif /* RCAR_LSI == RCAR_V4H */ + +#define CPGSRCR_PDR11 (0x00002000U) /* Bit13 */ +#if (RCAR_LSI == RCAR_V4H) +#define CPGSRCR28_VAL (0xCF600000U) +#define CPGSRCR29_VAL (0x007B3D9EU) +#endif /* RCAR_LSI == RCAR_V4H */ + +#define CPG_D1WACRA00 (CPG_BASE + 0x3900U) +#define CPG_D2WACRA00 (CPG_BASE + 0x3A00U) +#define CPG_D3WACRA00 (CPG_BASE + 0x3B00U) + +#define CPG_D1WACR_MSTPCR0 (CPG_BASE + 0x3100U) +#define CPG_D1WACR_RAHSR0 (CPG_BASE + 0x3180U) +#define CPG_D1WACR_SRCR0 (CPG_BASE + 0x3500U) +#define CPG_D1WACR_SRSTCLR0 (CPG_BASE + 0x3580U) + +#define CPG_D2WACR_MSTPCR0 (CPG_BASE + 0x3200U) +#define CPG_D2WACR_RAHSR0 (CPG_BASE + 0x3280U) +#define CPG_D2WACR_SRCR0 (CPG_BASE + 0x3600U) +#define CPG_D2WACR_SRSTCLR0 (CPG_BASE + 0x3680U) + +#define CPG_D3WACR_MSTPCR0 (CPG_BASE + 0x3300U) +#define CPG_D3WACR_RAHSR0 (CPG_BASE + 0x3380U) +#define CPG_D3WACR_SRCR0 (CPG_BASE + 0x3700U) +#define CPG_D3WACR_SRSTCLR0 (CPG_BASE + 0x3780U) + +/* APMU */ +#define APMU_BASE (BASE_APMU_ADDR) +#if (RCAR_LSI == RCAR_S4) +#define CORTEX_R_CORE (0U) /* Target Cortex R52 cores (0 only) */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define CORTEX_R_CORE (1U) /* Target Cortex R52 cores (0 to 2) */ +#endif /* RCAR_LSI == RCAR_S4 */ +#define APMU_WPR (APMU_BASE + 0x0004U) /* Write protection register */ +#define APMU_D0_ACCENR (APMU_BASE + 0x0010U) /* Domain0 Access enable register */ +#define APMU_D1_ACCENR (APMU_BASE + 0x0014U) /* Domain1 Access enable register */ +#define APMU_D2_ACCENR (APMU_BASE + 0x0018U) /* Domain2 Access enable register */ +#define APMU_D3_ACCENR (APMU_BASE + 0x001CU) /* Domain3 Access enable register */ +#define APMU_CRRSTCTRL (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x0304U) /* Cortex-R Reset Control Register */ +#define APMU_CRBAR (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x0334U) /* Cortex-R Boot Address Register */ +#define APMU_CRBARP (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x033CU) /* Cortex-R Boot Address Register Protected */ +#define APMU_PWRCTRLC0 (APMU_BASE + 0x0800U) /* Power Control Register for Core 0 */ +#define APMU_RVBARPLC0 (APMU_BASE + 0x0838U) /* Reset Vector Base Address Register Protected Low for Core 0 */ +#define APMU_RVBARPHC0 (APMU_BASE + 0x083CU) /* Reset Vector Base Address Register Protected High for Core 0 */ + +/* SD-IF */ +#define CPG_SD0CKCR0 (CPG_BASE + 0x0870U) + +/* RPC */ +#define CPG_RPCCKCR (CPG_BASE + 0x0874U) +/* for CPG register setting */ +#define RPCCKCR_RPCFC_MASK (0x1FU) /* Mask for RPCFC bit of CPG_RPCCKCR */ +#define RPCCKCR_RPCFC_160M (0x11U) /* RPC clock 160MHz */ +#define RPCCKCR_RPCFC_80M (0x13U) /* RPC clock 80MHz */ +#define RPCCKCR_RPCFC_40M (0x17U) /* RPC clock 40MHz */ + +#define CPG_PLL6CR0 (CPG_BASE + 0x084CU) +#define CPG_PLLECR (CPG_BASE + 0x0820U) +#endif /* CPG_REGISTER_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpu.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpu.h new file mode 100644 index 0000000..51275cb --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpu.h @@ -0,0 +1,103 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : CPU register access list header + ******************************************************************************/ + + +#ifndef CPU_H_ +#define CPU_H_ + +/* + * Groups + */ + +/* Name Reg, Group Comment */ +#define EIPC 0, 0 /* Status save registers when acknowledging EI level exception SV */ +#define EIPSW 1, 0 /* Status save registers when acknowledging EI level exception SV */ +#define FEPC 2, 0 /* Status save registers when acknowledging FE level exception SV */ +#define FEPSW 3, 0 /* Status save registers when acknowledging FE level exception SV */ +#define PSW 5, 0 /* Program status word Note 1 */ +#define EIIC 13, 0 /* EI level exception cause SV */ +#define FEIC 14, 0 /* FE level exception cause SV */ +#define CTPC 16, 0 /* CALLT execution status save register UM */ +#define CTPSW 17, 0 /* CALLT execution status save register UM */ +#define CTBP 20, 0 /* CALLT base pointer UM */ +#define EIWR 28, 0 /* EI level exception working register SV */ +#define FEWR 29, 0 /* FE level exception working register SV */ +#define BSEL 31, 0 /* (Reserved for backward compatibility with V850E2 series)Note 2 SV */ + +#define MCFG0 0, 1 /* Machine configuration SV */ +#define RBASE 2, 1 /* Reset vector base address SV */ +#define EBASE 3, 1 /* Exception handler vector address SV */ +#define INTBP 4, 1 /* Base address of the interrupt handler table SV */ +#define MCTL 5, 1 /* CPU control SV */ +#define PID 6, 1 /* Processor ID SV */ +#define SCCFG 11, 1 /* SYSCALL operation setting SV */ +#define SCBP 12, 1 /* SYSCALL base pointer SV */ + +#define HTCFG0 0, 2 /* Thread configuration SV */ +#define MEA 6, 2 /* Memory error address SV */ +#define ASID 7, 2 /* Address space ID SV */ +#define MEI 8, 2 /* Memory error information SV */ +#define ISPR 10, 2 /* Priority of interrupt being serviced SV */ +#define PMR 11, 2 /* Interrupt priority masking SV */ +#define ICSR 12, 2 /* Interrupt control status SV */ +#define INTCFG 13, 2 /* Interrupt function setting SV */ + +#define MPM 0, 5 /* Memory protection operation mode setting SV */ +#define MPRC 1, 5 /* MPU region control SV */ +#define MPBRGN 4, 5 /* MPU base region number SV */ +#define MPTRGN 5, 5 /* MPU end region number SV */ +#define MCA 8, 5 /* Memory protection setting check address SV */ +#define MCS 9, 5 /* Memory protection setting check size SV */ +#define MCC 10, 5 /* Memory protection setting check command SV */ +#define MCR 11, 5 /* Memory protection setting check result SV */ + +#define MPLA0 0, 6 /* Protection area minimum address SV */ +#define MPUA0 1, 6 /* Protection area maximum address SV */ +#define MPAT0 2, 6 /* Protection area attribute SV */ +#define MPLA1 4, 6 /* Protection area minimum address SV */ +#define MPUA1 5, 6 /* Protection area maximum address SV */ +#define MPAT1 6, 6 /* Protection area attribute SV */ +#define MPLA2 8, 6 /* Lower address of the protection area SV */ +#define MPUA2 9, 6 /* Protection area maximum address SV */ +#define MPAT2 10, 6 /* Protection area attribute SV */ +#define MPLA3 12, 6 /* Protection area minimum address SV */ +#define MPUA3 13, 6 /* Protection area maximum address SV */ +#define MPAT3 14, 6 /* Protection area attribute SV */ +#define MPLA4 16, 6 /* Protection area minimum address SV */ +#define MPUA4 17, 6 /* Protection area maximum address SV */ +#define MPAT4 18, 6 /* Protection area attribute SV */ +#define MPLA5 20, 6 /* Protection area minimum address SV */ +#define MPUA5 21, 6 /* Protection area maximum address SV */ +#define MPAT5 22, 6 /* Protection area attribute SV */ +#define MPLA6 24, 6 /* Protection area minimum address SV */ +#define MPUA6 25, 6 /* Protection area maximum address SV */ +#define MPAT6 26, 6 /* Protection area attribute SV */ +#define MLUA7 28, 6 /* Protection area minimum address SV */ +#define MPUA7 29, 6 /* Protection area maximum address SV */ +#define MPAT7 30, 6 /* Protection area attribute SV */ + +#endif /* CPU_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpu_on.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpu_on.h new file mode 100644 index 0000000..754113e --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/cpu_on.h @@ -0,0 +1,62 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Power management driver header + ******************************************************************************/ + +#ifndef CPU_ON_H__ +#define CPU_ON_H__ +#include "remap_register.h" + +#define RCAR_PWR_TARGET_CR (0U) +#define RCAR_PWR_TARGET_CA (1U) + +#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 (0x00000001U << 1U) +#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0 (0x00000001U << 0U) +#define AP_CORE_APSREG_CCI500_AUX_ACTDIS (0x00000001U << 0U) +#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT (AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 | AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0) + + +#define OTP_MEM_1_BASE (BASE_OTP_MEM_ADDR) +#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U) +#define OTP_MEM_PRODUCT_MASK (0x000000FFU) + +#if (RCAR_LSI == RCAR_V4H) +#define VARIANT_V4H_7 (0x00U) +#define VARIANT_V4H_5 (0x01U) +#define VARIANT_V4H_3 (0x02U) +#elif (RCAR_LSI == RCAR_V4M) +#define VARIANT_V4M_7 (0x00U) +#define VARIANT_V4M_5 (0x01U) +#define VARIANT_V4M_3 (0x02U) +#define VARIANT_V4M_2 (0x04U) +#endif /* RCAR_LSI == RCAR_V4H */ + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void arm_cpu_on(uint32_t target, uint32_t boot_addr); +void adj_cr_variant_freq(void); + +#endif /* CPU_ON_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/crc.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/crc.h new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/dma.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/dma.h new file mode 100644 index 0000000..82f1b2a --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/dma.h @@ -0,0 +1,57 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : DMA driver header + ******************************************************************************/ + +#ifndef DMA_DRIVER_H__ +#define DMA_DRIVER_H__ + +#include +#include +#include + +/* fraction mask for 64-byte units */ +#define FRACTION_MASK_64_BYTE (0x0000003FU) +#define TRANS_SIZE_64BYTE (0x40U) + +/* Prototype */ +void dma_init(void); +void dma_trans_start(uint32_t dst, uint32_t src, uint32_t len); +void dma_trans_end_check(void); +void dma_release(void); + +/* Inline function */ +/* Check address align when RT-DMAC/SDMAC transfer */ +static inline void dma_address_align_check(uint32_t dst_addr, uint32_t src_addr) +{ + if (((src_addr & FRACTION_MASK_64_BYTE) != 0U) || ((dst_addr & FRACTION_MASK_64_BYTE) != 0U)) + { + /* src_addr or dst_addr are not 64-byte alignment. */ + ERROR("Not 64-byte alignment in DMA transfer\n"); + panic; + } +} + +#endif /* DMA_DRIVER_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/dma_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/dma_register.h new file mode 100644 index 0000000..bd06423 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/dma_register.h @@ -0,0 +1,154 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : DMA register header + ******************************************************************************/ + +#ifndef DMA_REGISTER_H_ +#define DMA_REGISTER_H_ + +#include +#include + +#define DMACH (0U) /* The range of DMA ch is 0-15. */ + +#if ((RCAR_LSI == RCAR_S4) || (RCAR_LSI == RCAR_V4H)) +#define RTDMA_MODULE_MAX (4U) +#define RTDMA_CH_MAX (16U) +#define SYSDMA_MODULE_MAX (2U) +#define SYSDMA_CH_MAX (16U) +#elif (RCAR_LSI == RCAR_V4M) +#define RTDMA_MODULE_MAX (2U) +#define RTDMA_CH_MAX (16U) +#define SYSDMA_MODULE_MAX (2U) +#define SYSDMA_CH_MAX (16U) +#endif + +/* RT-DMA Control */ +#define RTDMACTL_BASE (BASE_RTDMACTL_ADDR) + +#define RTDMA_DMOR (RTDMACTL_BASE + 0x0060U) /* DMA operation register */ + +/* RT-DMAC0(for RPC) */ +#define RTDMA0_BASE (BASE_RTDMA0_ADDR) +#define RTDMA1_BASE (RTDMA0_BASE + 0x00010000U) +#define RTDMA2_BASE (RTDMA0_BASE + 0x00160000U) +#define RTDMA3_BASE (RTDMA0_BASE + 0x00170000U) +/* SYSDMAC */ +#define SYSDMA0_BASE (BASE_DMA_ADDR) +#define SYSDMA1_BASE (SYSDMA0_BASE + 0x00010000U) + +#define RTDMA_DMSEC (RTDMA0_BASE + 0x00B0U) + +#define DMA_REGIONID_MASK (0x0000000FU) + + +static inline uint32_t dma_get_rtdma_sar_addr(uint32_t num) +{ + return (RTDMA0_BASE + 0x0000U + (num * 0x1000U)); +} + +static inline uint32_t dma_get_rtdma_dar_addr(uint32_t num) +{ + return (RTDMA0_BASE + 0x0004U + (num * 0x1000U)); +} + +static inline uint32_t dma_get_rtdma_tcr_addr(uint32_t num) +{ + return (RTDMA0_BASE + 0x0008U + (num * 0x1000U)); +} + +static inline uint32_t dma_get_rtdma_chcr_addr(uint32_t num) +{ + return (RTDMA0_BASE + 0x000CU + (num * 0x1000U)); +} + +static inline uint32_t dma_get_rtdma_module_base_addr(uint32_t module) +{ + uint32_t ret; + + if(module == 0U) + { + ret = RTDMA0_BASE; + } + else if(module == 1U) + { + ret = RTDMA1_BASE; + } +#if ((RCAR_LSI == RCAR_S4) || (RCAR_LSI == RCAR_V4H)) + else if(module ==2U) + { + ret = RTDMA2_BASE; + } + else if(module == 3U) + { + ret = RTDMA3_BASE; + } +#endif /* ((RCAR_LSI == RCAR_S4) || (RCAR_LSI == RCAR_V4H)) */ + else + { + ERROR("Invalid DMA module value!\n"); + panic; + } + return ret; +} + +static inline uint32_t dma_get_rtdma_regionid_addr(uint32_t module, uint32_t ch) +{ + uint32_t base; + base = dma_get_rtdma_module_base_addr(module); + + return (base + 0x0078U + (ch * 0x1000U)); +} + +static inline uint32_t dma_get_sysdma_module_base_addr(uint32_t module) +{ + uint32_t ret; + + if(module == 0U) + { + ret = SYSDMA0_BASE; + } + else if(module == 1U) + { + ret = SYSDMA1_BASE; + } + else + { + ERROR("Invalid DMA module value!\n"); + panic; + } + + return ret; +} + +static inline uint32_t dma_get_sysdma_regionid_addr(uint32_t module, uint32_t ch) +{ + uint32_t base; + base = dma_get_sysdma_module_base_addr(module); + + return (base + 0x0078U + (ch * 0x1000U)); +} + +#endif /* DMAREGISTER_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_boot.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_boot.h new file mode 100644 index 0000000..437c50c --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_boot.h @@ -0,0 +1,41 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC boot header + ******************************************************************************/ + +#ifndef EMMC_BOOT_ +#define EMMC_BOOT_ + +#include + +#define FLASH_BOOT (0U) +#define EMMC_BOOT (1U) + +#define CA_IPL (0U) +#define BL31 (1U) + +void emmc_initialize( void ); + +#endif /* EMMC_BOOT_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_config.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_config.h new file mode 100644 index 0000000..847fe7e --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_config.h @@ -0,0 +1,82 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC Config header + ******************************************************************************/ + +#ifndef EMMC_CONFIG_H__ +#define EMMC_CONFIG_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "cpg_register.h" +#include "pfc_register.h" +#include "cpg.h" +#include "pfc.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* MMC driver config */ +#define EMMC_RCA (1U) /* RCA */ +#define EMMC_RW_DATA_TIMEOUT (0x40U) /* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */ +#define EMMC_CMD_MAX (60U) /* Don't change. */ + +/* etc */ +#define LOADIMAGE_FLAGS_DMA_ENABLE (0x00000001U) + +/* Module stop */ +#define CPG_MSTPCR_SDHI (1U << 6U) + +/* clock */ +#define CPG_SD0CKCR0_STP0HCK (1U << 9U) +#define CPG_SD0CKCR0_SDSRCFC_MASK (7U << 2U) +#define CPG_SD0CKCR0_SDSRCFC_000 (0U << 2U) +#define CPG_SD0CKCR0_SDSRCFC_010 (2U << 2U) +#define CPG_SD0CKCR0_SD0FC_MASK (3U << 0U) +#define CPG_SD0CKCR0_SD0FC_DIV2 (0U << 0U) +#define CPG_SD0CKCR0_SD0FC_DIV4 (1U << 0U) +#define CPG_SD0CKCR0_100MHZ (CPG_SD0CKCR0_STP0HCK | CPG_SD0CKCR0_SDSRCFC_010 | CPG_SD0CKCR0_SD0FC_DIV2) +#define CPG_SD0CKCR0_200MHZ (CPG_SD0CKCR0_STP0HCK | CPG_SD0CKCR0_SDSRCFC_000 | CPG_SD0CKCR0_SD0FC_DIV4) + +#if (RCAR_LSI == RCAR_S4) +#define PFC_POC_MMC_RW (PFC_POC1_RW) +#define PFC_POC_MMC_MASK (0x007FF000U) +#define PFC_POC_MMC_VAL (0x00000000U) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define PFC_POC_MMC_RW (PFC_POC3_RW) +#define PFC_POC_MMC_MASK (0x000007FFU) +#define PFC_POC_MMC_VAL (0x00000000U) +#endif /* RCAR_LSI == RCAR_S4 */ + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* #ifndef EMMC_CONFIG_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_def.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_def.h new file mode 100644 index 0000000..74b2222 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_def.h @@ -0,0 +1,74 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC Define header + ******************************************************************************/ + +#ifndef EMMC_DEF_H__ +#define EMMC_DEF_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_std.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +#define EMMC_DEV_OK (0x525F4F4BU) /* "R_OK" */ +#define EMMC_DEV_ERR (0xFFFFFFFFU) +#define EMMC_DEV_ERR_HW (0x00000004U) +#define EMMC_DEV_ERR_FAULT_INJECTION (0x00000005U) + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ +extern st_mmc_base mmc_drv_obj; + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* eMMC driver API */ +EMMC_ERROR_CODE emmc_init(void); +EMMC_ERROR_CODE emmc_terminate(void); +EMMC_ERROR_CODE emmc_memcard_power(uint32_t mode); +EMMC_ERROR_CODE emmc_mount(void); +EMMC_ERROR_CODE emmc_set_request_mmc_clock(const uint32_t *freq); +EMMC_ERROR_CODE emmc_send_idle_cmd (uint32_t arg); +EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id); +EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, uint32_t feature_flags); +uint32_t emmc_bit_field (const uint8_t *data, uint32_t top, uint32_t bottom); + + +/* interrupt service */ +uint32_t emmc_interrupt(void); + + +/* send command API */ +EMMC_ERROR_CODE emmc_exec_cmd (uint32_t error_mask, uint32_t *response); +void emmc_make_nontrans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg); +void emmc_make_trans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual, + uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode); +EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg); + +/* ********************************* CODE ********************************** */ + +#endif /* #define EMMC_DEF_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_hal.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_hal.h new file mode 100644 index 0000000..1db49a6 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_hal.h @@ -0,0 +1,162 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC HAL driverd header + ******************************************************************************/ + +#ifndef EMMC_HAL_H__ +#define EMMC_HAL_H__ +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +/* Memory card response types */ +#define HAL_MEMCARD_COMMAND_INDEX_MASK (0x0003fU) + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* memory access operation */ +typedef enum +{ + HAL_MEMCARD_READ = 0U, /**< read */ + HAL_MEMCARD_WRITE = 1U /**< write */ +} HAL_MEMCARD_OPERATION; + +/* Type of data width on memorycard bus */ +typedef enum +{ + HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U, + HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U, + HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U +} HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */ + +/* mode of data transfer */ +typedef enum +{ + HAL_MEMCARD_DMA = 0U, + HAL_MEMCARD_NOT_DMA = 1U +} HAL_MEMCARD_DATA_TRANSFER_MODE; + + +/* Memory card response types. */ +typedef enum hal_memcard_response_type +{ + HAL_MEMCARD_RESPONSE_NONE = 0x00000U, + HAL_MEMCARD_RESPONSE_R1 = 0x00100U, + HAL_MEMCARD_RESPONSE_R1b = 0x00200U, + HAL_MEMCARD_RESPONSE_R2 = 0x00300U, + HAL_MEMCARD_RESPONSE_R3 = 0x00400U, + HAL_MEMCARD_RESPONSE_R4 = 0x00500U, + HAL_MEMCARD_RESPONSE_R5 = 0x00600U, + HAL_MEMCARD_RESPONSE_R6 = 0x00700U, + HAL_MEMCARD_RESPONSE_R7 = 0x00800U, + HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U +} HAL_MEMCARD_RESPONSE_TYPE; + + +/* Memory card command types. */ +typedef enum hal_memcard_command_type +{ + HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U, + HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U, + HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U, + HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U, + HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U, + HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U +} HAL_MEMCARD_COMMAND_TYPE; + +/* Type of memory card */ +typedef enum hal_memcard_command_card_type +{ + HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U +} HAL_MEMCARD_COMMAND_CARD_TYPE; + +/* Memory card application command. */ +typedef enum hal_memcard_command_app_norm +{ + HAL_MEMCARD_COMMAND_NORMAL = 0x00000U, + HAL_MEMCARD_COMMAND_APP = 0x20000U, + HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U +} HAL_MEMCARD_COMMAND_APP_NORM; + + +/* Memory card command codes. */ +typedef enum +{ +/* class 0 and class 1 */ + CMD0_GO_IDLE_STATE = 0 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD0 */ + CMD1_SEND_OP_COND = 1 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD1 */ + CMD2_ALL_SEND_CID_MMC = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD2 */ + CMD2_ALL_SEND_CID_SD = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD3_SET_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD3 */ + CMD3_SEND_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R6 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD4_SET_DSR = 4 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD4 */ + CMD5_SLEEP_AWAKE = 5 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD5 */ + CMD6_SWITCH = 6 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD6 */ + CMD6_SWITCH_FUNC = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + ACMD6_SET_BUS_WIDTH = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + CMD7_SELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7 */ + CMD7_SELECT_CARD_PROG = 7 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7(from Disconnected State to Programming State) */ + CMD7_DESELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, + CMD8_SEND_EXT_CSD = 8 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD8 */ + CMD8_SEND_IF_COND = 8 | HAL_MEMCARD_RESPONSE_R7 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD9_SEND_CSD = 9 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD9 */ + CMD10_SEND_CID = 10 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD10 */ + CMD11_READ_DAT_UNTIL_STOP = 11 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD11 */ + CMD12_STOP_TRANSMISSION = 12 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 */ + CMD12_STOP_TRANSMISSION_WRITE = 12 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 R1b : write case */ + CMD13_SEND_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD13 */ + ACMD13_SD_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + CMD14_BUSTEST_R = 14 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD14 */ + CMD15_GO_INACTIVE_STATE = 15 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD15 */ + +/* class 2 */ + CMD16_SET_BLOCKLEN = 16 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD16 */ + CMD17_READ_SINGLE_BLOCK = 17 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD17 */ + CMD18_READ_MULTIPLE_BLOCK = 18 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD18 */ + CMD19_BUS_TEST_W = 19 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD19 */ +/* class 3 */ + CMD20_WRITE_DAT_UNTIL_STOP = 20 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD20 */ + CMD21 = 21, /* CMD21 */ + CMD22 = 22, /* CMD22 */ + ACMD22_SEND_NUM_WR_BLOCKS = 22 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + +/* class 4 */ + CMD23_SET_BLOCK_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL /* CMD23 */ + +} HAL_MEMCARD_COMMAND; + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* EMMC_HAL_H__ */ + +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_multiboot.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_multiboot.h new file mode 100644 index 0000000..35f7680 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_multiboot.h @@ -0,0 +1,44 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC Multi boot header + ******************************************************************************/ + +#ifndef EMMC_MULTIBOOT_H_ +#define EMMC_MULTIBOOT_H_ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + + +/* ************************** FUNCTION PROTOTYPES ************************** */ +uint32_t emmc_trans_data(uint32_t next_bootPartition, uintptr_t sourceSct, uintptr_t targetAd, uint32_t sectorSize); +/* ******************************** END ************************************ */ +#endif /* #ifndef EMMC_MULTIBOOT_H_*/ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_registers.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_registers.h new file mode 100644 index 0000000..e81d9a4 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_registers.h @@ -0,0 +1,146 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC register header + ******************************************************************************/ + +#ifndef EMMC_REGISTERS_H__ +#define EMMC_REGISTERS_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +/* MMC0 channel */ +#define MMC0_SD_BASE (BASE_MMC0_ADDR) /* reg addr is 0xEE140000U */ + +#define SD_CMD (MMC0_SD_BASE + 0x0000U) +#define SD_ARG (MMC0_SD_BASE + 0x0010U) +#define SD_STOP (MMC0_SD_BASE + 0x0020U) +#define SD_SECCNT (MMC0_SD_BASE + 0x0028U) +#define SD_RSP10 (MMC0_SD_BASE + 0x0030U) +#define SD_RSP32 (MMC0_SD_BASE + 0x0040U) +#define SD_RSP54 (MMC0_SD_BASE + 0x0050U) +#define SD_RSP76 (MMC0_SD_BASE + 0x0060U) +#define SD_INFO1 (MMC0_SD_BASE + 0x0070U) +#define SD_INFO2 (MMC0_SD_BASE + 0x0078U) +#define SD_INFO1_MASK (MMC0_SD_BASE + 0x0080U) +#define SD_INFO2_MASK (MMC0_SD_BASE + 0x0088U) +#define SD_CLK_CTRL (MMC0_SD_BASE + 0x0090U) +#define SD_SIZE (MMC0_SD_BASE + 0x0098U) +#define SD_OPTION (MMC0_SD_BASE + 0x00A0U) +#define SD_ERR_STS1 (MMC0_SD_BASE + 0x00B0U) +#define SD_ERR_STS2 (MMC0_SD_BASE + 0x00B8U) +#define SD_BUF0 (MMC0_SD_BASE + 0x00C0U) +#define CC_EXT_MODE (MMC0_SD_BASE + 0x0360U) +#define SOFT_RST (MMC0_SD_BASE + 0x0380U) +#define HOST_MODE (MMC0_SD_BASE + 0x0390U) +#define DM_CM_DTRAN_MODE (MMC0_SD_BASE + 0x0820U) +#define DM_CM_DTRAN_CTRL (MMC0_SD_BASE + 0x0828U) +#define DM_CM_INFO1 (MMC0_SD_BASE + 0x0840U) +#define DM_CM_INFO1_MASK (MMC0_SD_BASE + 0x0848U) +#define DM_CM_INFO2 (MMC0_SD_BASE + 0x0850U) +#define DM_CM_INFO2_MASK (MMC0_SD_BASE + 0x0858U) +#define DM_DTRAN_ADDR (MMC0_SD_BASE + 0x0880U) + + + +/* SD_INFO1 Registers */ +#define SD_INFO1_INFO2 (0x00000004U) /* Access end */ +#define SD_INFO1_INFO0 (0x00000001U) /* Response end */ + +/* SD_INFO2 Registers */ +#define SD_INFO2_CBSY (0x00004000U) /* Command Type Register Busy */ +#define SD_INFO2_BWE (0x00000200U) /* SD_BUF Write Enable */ +#define SD_INFO2_BRE (0x00000100U) /* SD_BUF Read Enable */ +#define SD_INFO2_DAT0 (0x00000080U) /* SDDAT0 */ +#define SD_INFO2_ALL_ERR (0x0000807FU) +#define SD_INFO2_CLEAR (0x00000800U) /* BIT11 The write value should always be 1. HWM_0003 */ + +/* DM_INFO1 Registers */ +#define DM_CM_INFO_DTRANEND0 (0x00010000U) /* DMAC Channel 0 Transfer End */ +#define DM_CM_INFO_DTRANEND1 (0x00020000U) /* DMAC Channel 0 Transfer End */ + +/* SOFT_RST */ +#define SOFT_RST_SDRST (0x00000001U) + +/* SD_CLK_CTRL */ +#define SD_CLK_CTRL_CLKDIV_MASK (0x000000FFU) +#define SD_CLK_WRITE_MASK (0x000003FFU) + +/* SD_OPTION */ +#define SD_OPTION_WIDTH (0x00008000U) +#define SD_OPTION_WIDTH8 (0x00002000U) +#define SD_OPTION_TIMEOUT_CNT_MASK (0x000000F0U) + + +/* MMC Clock Frequency + * 200MHz * 1/x = output clock + */ +#define MMC_400KHZ (512U) /* 200MHz * 1/512 = 390 KHz */ +#define MMC_20MHZ (16U) /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */ +#define MMC_26MHZ (8U) /* 200MHz * 1/8 = 25 MHz High speed mode 26Mhz */ +#define MMC_52MHZ (4U) /* 200MHz * 1/4 = 50 MHz High speed mode 52Mhz */ + + +#define MMC_FREQ_52MHZ (52000000U) +#define MMC_FREQ_26MHZ (26000000U) +#define MMC_FREQ_20MHZ (20000000U) + + +/* MMC Clock DIV */ +#define MMC_SD_CLK_START (0x00000100U) /* CLOCK On */ +#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */ + +/* DM_CM_DTRAN_MODE */ +#define DM_CM_DTRAN_MODE_CH0 (0x00000000U) /* CH0 : downstream */ +#define DM_CM_DTRAN_MODE_CH1 (0x00010000U) /* CH1 : upstream */ +#define DM_CM_DTRAN_MODE_BIT_WIDTH (0x00000030U) + +/* CC_EXT_MODE */ +#define CC_EXT_MODE_DMASDRW_ENABLE (0x00000002U) /* SD_BUF Read/Write DMA Transfer */ +#define CC_EXT_MODE_CLEAR (0x00001010U) /* BIT 12 & 4 always 1. */ + +/* DM_CM_INFO_MASK */ +#define DM_CM_INFO_MASK_CLEAR (0xFFFCFFFEU) +#define DM_CM_INFO_CH0_ENABLE (0x00010001U) +#define DM_CM_INFO_CH1_ENABLE (0x00020001U) + +/* DM_DTRAN_ADDR */ +#define DM_DTRAN_ADDR_WRITE_MASK (0xFFFFFFF8U) + +/*DM_CM_DTRAN_CTRL */ +#define DM_CM_DTRAN_CTRL_START (0x00000001U) + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* EMMC_REGISTERS_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_std.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_std.h new file mode 100644 index 0000000..3057bf7 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/emmc_std.h @@ -0,0 +1,263 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC standard header + ******************************************************************************/ + +#ifndef EMMC_STD_H__ +#define EMMC_STD_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_hal.h" +#include "emmc_registers.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/*CSD register Macros */ +#define EMMC_CSD_SPEC_VARS() (emmc_bit_field(mmc_drv_obj.csd_data, 125,122)) +#define EMMC_CSD_TRAN_SPEED() (emmc_bit_field(mmc_drv_obj.csd_data, 103,96)) + +/* for sector access */ +#define EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */ +#define EMMC_SECTOR_PADD_MASK ((1U << EMMC_SECTOR_SIZE_SHIFT) - 1U) +#define EMMC_SECTOR_SIZE (512U) +#define EMMC_BLOCK_LENGTH (512U) +#define EMMC_BLOCK_LENGTH_DW (128U) + +/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */ +typedef enum +{ + EMMC_ERR = 0U, /**< unknown error */ + EMMC_SUCCESS , /**< OK */ + EMMC_ERR_FROM_DMAC , /**< DMAC allocation error */ + EMMC_ERR_FROM_DMAC_TRANSFER , /**< DMAC transfer error */ + EMMC_ERR_CARD_STATUS_BIT , /**< card status error. Non-masked error bit was set in the card status */ + EMMC_ERR_CMD_TIMEOUT , /**< command timeout error */ + EMMC_ERR_DATA_TIMEOUT , /**< data timeout error */ + EMMC_ERR_CMD_CRC , /**< command CRC error */ + EMMC_ERR_DATA_CRC , /**< data CRC error */ + EMMC_ERR_PARAM , /**< parameter error */ + EMMC_ERR_RESPONSE , /**< response error */ + EMMC_ERR_RESPONSE_BUSY , /**< response busy error */ + EMMC_ERR_TRANSFER , /**< data transfer error */ + EMMC_ERR_READ_SECTOR , /**< read sector error */ + EMMC_ERR_WRITE_SECTOR , /**< write sector error */ + EMMC_ERR_STATE , /**< state error */ + EMMC_ERR_TIMEOUT , /**< timeout error */ + EMMC_ERR_ILLEGAL_CARD , /**< illegal card */ + EMMC_ERR_CARD_BUSY , /**< Busy state */ + EMMC_ERR_CARD_STATE , /**< card state error */ + EMMC_ERR_SET_TRACE , /**< trace information error */ + EMMC_ERR_FROM_TIMER , /**< Timer error */ + EMMC_ERR_FORCE_TERMINATE , /**< Force terminate */ + EMMC_ERR_CARD_POWER , /**< card power fail */ + EMMC_ERR_ERASE_SECTOR , /**< erase sector error */ + EMMC_ERR_INFO2 /**< exec cmd error info2 */ +} EMMC_ERROR_CODE; + +/* Response */ +/** R1 */ +#define EMMC_R1_ERROR_MASK (0xFDBFE080U) /* Type 'E' bit and bit14(must be 0). ignore bit22 */ +#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) /* Ignore bit23 (Not check CRC error) */ +#define EMMC_R1_STATE_MASK (0x00001E00U) /* [12:9] */ +#define EMMC_R1_READY (0x00000100U) /* bit8 */ +#define EMMC_R1_STATE_SHIFT (9U) + +/** R4 */ +#define EMMC_R4_STATUS (0x00008000U) + +/** CSD */ +#define EMMC_TRANSPEED_FREQ_UNIT_MASK (0x07U) /* bit[2:0] */ +#define EMMC_TRANSPEED_MULT_MASK (0x78U) /* bit[6:3] */ +#define EMMC_TRANSPEED_MULT_SHIFT (3U) + +/** OCR */ +#define EMMC_HOST_OCR_VALUE (0x40FF8080U) +#define EMMC_OCR_STATUS_BIT (0x80000000U) /* Card power up status bit */ +#define EMMC_OCR_ACCESS_MODE_MASK (0x60000000U) /* bit[30:29] */ +#define EMMC_OCR_ACCESS_MODE_SECT (0x40000000U) + +/** EXT_CSD */ +#define EMMC_EXT_CSD_CARD_TYPE (196U) +#define EMMC_EXT_CSD_PARTITION_CONFIG (179U) + +#define EMMC_EXT_CSD_CARD_TYPE_26MHZ (0x01U) +#define EMMC_EXT_CSD_CARD_TYPE_52MHZ (0x02U) + +/** SWITCH (CMD6) argument */ +#define EXTCSD_ACCESS_BYTE (0x03000000U) + +#define HS_TIMING_ADD (185U<<16U) /* H'b9 */ +#define HS_TIMING_1 (1U<<8U) + +#define BUS_WIDTH_ADD (183U<<16U) /* H'b7 */ +#define BUS_WIDTH_1 (0U<<8U) + +#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1) /**< H'03b90100 */ + +#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1) /**< H'03b70000 */ +#define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL /**< Partition config = 0x00 */ + +/** for st_mmc_base */ +#define EMMC_MAX_RESPONSE_LENGTH (17U) +#define EMMC_MAX_CID_LENGTH (16U) +#define EMMC_MAX_CSD_LENGTH (16U) +#define EMMC_MAX_EXT_CSD_LENGTH (512U) + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* Partition id */ +typedef enum +{ + PARTITION_ID_USER = 0x0, /**< User Area */ + PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */ + PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */ + PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */ + PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */ + PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */ + PARTITION_ID_GP_3 = 0x6, /**< General Purpose partition 3 */ + PARTITION_ID_GP_4 = 0x7, /**< General Purpose partition 4 */ + PARTITION_ID_MASK = 0x7 /**< [2:0] */ +} EMMC_PARTITION_ID; + +/* card state in R1 response [12:9] */ +typedef enum +{ + EMMC_R1_STATE_IDLE = 0, + EMMC_R1_STATE_READY, + EMMC_R1_STATE_IDENT, + EMMC_R1_STATE_STBY, + EMMC_R1_STATE_TRAN, + EMMC_R1_STATE_DATA, + EMMC_R1_STATE_RCV, + EMMC_R1_STATE_PRG, + EMMC_R1_STATE_DIS, + EMMC_R1_STATE_BTST, + EMMC_R1_STATE_SLEP +} EMMC_R1_STATE; + +typedef enum{ + ESTATE_BEGIN = 0, + ESTATE_ISSUE_CMD, + ESTATE_NON_RESP_CMD, + ESTATE_RCV_RESP, + ESTATE_RCV_RESPONSE_BUSY, + ESTATE_CHECK_RESPONSE_COMPLETE, + ESTATE_DATA_TRANSFER, + ESTATE_DATA_TRANSFER_COMPLETE, + ESTATE_ACCESS_END, + ESTATE_TRANSFER_ERROR, + ESTATE_ERROR, + ESTATE_END +}EMMC_INT_STATE; + +/* eMMC boot driver error information */ +typedef struct +{ + volatile uint32_t info1; /**< SD_INFO1 register value. (hardware dependence) */ + volatile uint32_t info2; /**< SD_INFO2 register value. (hardware dependence) */ + volatile uint32_t status1; /**< SD_ERR_STS1 register value. (hardware dependence) */ + volatile uint32_t status2; /**< SD_ERR_STS2 register value. (hardware dependence) */ + volatile uint32_t dm_info1; /**< DM_CM_INFO1 register value. (hardware dependence) */ + volatile uint32_t dm_info2; /**< DM_CM_INFO2 register value. (hardware dependence) */ +} st_error_info; + + +/* Command information */ +typedef struct +{ + HAL_MEMCARD_COMMAND cmd; /**< Command information */ + uint32_t arg; /**< argument */ + HAL_MEMCARD_OPERATION dir; /**< direction */ + uint32_t hw; /**< H/W dependence. SD_CMD register value. */ +} st_command_info; + + +/* MMC driver base */ +typedef struct +{ + st_error_info error_info; /**< error information */ + st_command_info cmd_info; /**< command information */ + + /* for data transfer */ + uint32_t *buff_address_virtual; /**< Dest or Src buff */ + uint32_t *buff_address_physical; /**< Dest or Src buff */ + HAL_MEMCARD_DATA_WIDTH bus_width; /**< bus width */ + uint32_t trans_size; /**< transfer size for this command */ + uint32_t remain_size; /**< remain size for this command */ + uint32_t response_length; /**< response length for this command */ + + /* clock */ + uint32_t max_freq; /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */ + uint32_t current_freq; /**< current MMC clock[Hz] (the closest frequency supported by HW) */ + + /* state flag */ + uint32_t card_power_enable; /**< True : Power ON */ + uint32_t clock_enable; /**< True : Clock ON */ + uint32_t initialize; /**< True : initialize complete. */ + uint32_t mount; /**< True : mount complete. */ + uint32_t selected; /**< True : selected card. */ + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; /**< 0: DMA, 1:PIO */ + EMMC_R1_STATE current_state; /**< card state */ + volatile uint32_t during_transfer; /**< True : during transfer */ + volatile uint32_t during_dma_transfer; /**< True : during transfer (DMA)*/ + volatile uint32_t dma_error_flag; /**< True : occurred DMAC error */ + volatile uint32_t force_terminate; /**< force terminate flag */ + volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */ + + /* timeout */ + uint32_t data_timeout; /**< read and write data timeout.*/ + + /* interrupt */ + volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */ + volatile uint32_t int_event2; /**< interrupt SD_INFO2 Event */ + volatile uint32_t dm_event1; /**< interrupt DM_CM_INFO1 Event */ + volatile uint32_t dm_event2; /**< interrupt DM_CM_INFO2 Event */ + + /* response */ + uint32_t *response; /**< pointer to buffer for executing command. */ + uint32_t r1_card_status; /**< R1 response data */ + uint32_t r3_ocr; /**< R3 response data */ + uint32_t r4_resp; /**< R4 response data */ + uint32_t r5_resp; /**< R5 response data */ + + /* Card registers (4byte align) */ + uint8_t csd_data[EMMC_MAX_CSD_LENGTH]; /**< CSD */ + uint8_t cid_data[EMMC_MAX_CID_LENGTH]; /**< CID */ + uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH]; /**< EXT_CSD */ + uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH]; /**< other response */ + + /* SDHI base address */ + uintptr_t base_address; +} st_mmc_base; + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +/* ******************************** END ************************************ */ +#endif /* EMMC_STD_H__ */ + /* EMMC_STD_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/fcpr.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/fcpr.h new file mode 100644 index 0000000..0e85a3c --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/fcpr.h @@ -0,0 +1,45 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : FCPR driver header + ******************************************************************************/ + +#ifndef FCPR_H__ +#define FCPR_H__ + +#include + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ +#define FCPR_DISABLE (0U) +#define FCPR_ENABLE (1U) + +#define COMPRESSION_START_ADDR (0x80000000U) +#define COMPRESSION_END_ADDR (0xA2FFFFFFU) +#define COMPRESSION_ENABLE (0x00000001U) + +void fcpr_init(void); + +#endif /* FCPR_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/fcpr_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/fcpr_register.h new file mode 100644 index 0000000..dc2f5ca --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/fcpr_register.h @@ -0,0 +1,46 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : FCPR register header + ******************************************************************************/ + +#ifndef FCPR_REGISTER_H__ +#define FCPR_REGISTER_H__ + +#include + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ +/* CPG base address */ +/* 0xE6785700 */ +#define FCPR_BASE (BASE_FCPR_ADDR) + +/* FCPR */ +#define FCPR_CMP_CTRL (BASE_FCPR_ADDR + 0x0030U) +#define FCPR_CMP_SPACE (BASE_FCPR_ADDR + 0x0080U) +#define FCPR_CMP_STADR (BASE_FCPR_ADDR + 0x0084U) +#define FCPR_CMP_EDADR (BASE_FCPR_ADDR + 0x0088U) + +#endif /* FCPR_REGISTER_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/gpio.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/gpio.h new file mode 100644 index 0000000..e947d35 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/gpio.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2025 Hyundai Mobis Co., Ltd. + * + * The right to copy, distribute, modify, or otherwise make use + * of this software may be licensed only pursuant to the terms + * of an applicable Hyundai Mobis license agreement. + */ + +#ifndef GPIO_H +#define GPIO_H + +void gpio_N1307(int set); +void gpio_N1305(int set); +void gpio_V4H_SERDES_1V8_en(int set); + +#endif /* GPIO_H */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/hscif_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/hscif_register.h new file mode 100644 index 0000000..7b33171 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/hscif_register.h @@ -0,0 +1,49 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : HSCIF register header + ******************************************************************************/ + + +#ifndef HSCIF_REGISTER_H_ +#define HSCIF_REGISTER_H_ + +#include + +/* HSCIF0 base address */ +/* 0xE6540000U */ +#define HSCIF0_BASE (BASE_HSCIF_ADDR) + +#define HSCIF_HSSMR (HSCIF0_BASE + 0x0000U) /* 16 Serial mode register */ +#define HSCIF_HSBRR (HSCIF0_BASE + 0x0004U) /* 8 Bit rate register */ +#define HSCIF_HSSCR (HSCIF0_BASE + 0x0008U) /* 16 Serial control register */ +#define HSCIF_HSFTDR (HSCIF0_BASE + 0x000CU) /* 8 Transmit FIFO data register */ +#define HSCIF_HSFSR (HSCIF0_BASE + 0x0010U) /* 16 Serial status register */ +#define HSCIF_HSFCR (HSCIF0_BASE + 0x0018U) /* 16 FIFO control register */ +#define HSCIF_HSLSR (HSCIF0_BASE + 0x0024U) /* 16 Line status register */ +#define HSCIF_DL (HSCIF0_BASE + 0x0030U) /* 16 Frequency division register */ +#define HSCIF_CKS (HSCIF0_BASE + 0x0034U) /* 16 Clock Select register */ +#define HSCIF_HSSRR (HSCIF0_BASE + 0x0040U) /* 16 Sampling rate register */ + +#endif /* HSCIF_REGISTER_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/i2c.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/i2c.h new file mode 100644 index 0000000..f0d7cae --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/i2c.h @@ -0,0 +1,74 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : I2C driver header + ******************************************************************************/ + +#ifndef I2C_DRIVER_H__ +#define I2C_DRIVER_H__ + +#define FLG_RW (0x00000001U) + +#define I2C_OK (0x00000000U) +#define I2C_NG (0x00000001U) + +#define SET_SCGD (0x00000018U) +#define SET_CDF (0x00000007U) + +#define FLAG_SDBS (1U << 3) + +#define FLAG_MDBS (0x00000080U) +#define FLAG_FSCL (0x00000040U) +#define FLAG_FSDA (0x00000020U) +#define FLAG_MIE (0x00000008U) +#define FLAG_FSB (0x00000002U) +#define FLAG_ESG (0x00000001U) + +#define FLAG_MNR (0x00000040U) +#define FLAG_MAL (0x00000020U) +#define FLAG_MST (0x00000010U) +#define FLAG_MDE (0x00000008U) +#define FLAG_MDT (0x00000004U) +#define FLAG_MDR (0x00000002U) +#define FLAG_MAT (0x00000001U) +#define __INV(x) ((0x7F) & ~(x)) + +#define FLAG_NONE (0U) + +#define ERR_MAX (1U) + +void i2c3_init(void); +void i2c3_write(uint32_t slaveAdd, uint32_t regAdd, uint32_t setData); +void i2c3_read(uint32_t slaveAdd, uint32_t regAdd, uint32_t *revData); +uint32_t i2c3_err_check(uint32_t first, uint32_t second, uint32_t error); +void i2c3_release(void); + +void i2c5_init(void); +void i2c5_write(uint32_t slaveAdd, uint32_t regAdd, uint32_t setData); +void i2c5_read(uint32_t slaveAdd, uint32_t regAdd, uint32_t *revData); +uint32_t i2c5_err_check(uint32_t first, uint32_t second, uint32_t error); +void i2c5_release(void); + +#endif /* I2C_DRIVER_H__ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/i2c_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/i2c_register.h new file mode 100644 index 0000000..56134f2 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/i2c_register.h @@ -0,0 +1,99 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : I2C register header + ******************************************************************************/ + +#ifndef I2C_REGISTER_H__ +#define I2C_REGISTER_H__ + +#include + +/* I2C ch6 base address */ +#define I2C3_BASE (BASE_I2C3_ADDR) /* Physical address:0xE66D0000, Logical address:0xFDCD0000 */ + +/* Slave control register */ +#define I2C3_ICSCR (I2C3_BASE + 0x0000U) +/* Master control register */ +#define I2C3_ICMCR (I2C3_BASE + 0x0004U) +/* Slave status register */ +#define I2C3_ICSSR (I2C3_BASE + 0x0008U) +/* Master status register */ +#define I2C3_ICMSR (I2C3_BASE + 0x000CU) +/* Slave interrupt enable register */ +#define I2C3_ICSIER (I2C3_BASE + 0x0010U) +/* Master interrupt enable register */ +#define I2C3_ICMIER (I2C3_BASE + 0x0014U) +/* Clock control register */ +#define I2C3_ICCCR (I2C3_BASE + 0x0018U) +/* Slave address register */ +#define I2C3_ICSAR (I2C3_BASE + 0x001CU) +/* Master address register */ +#define I2C3_ICMAR (I2C3_BASE + 0x0020U) +/* Recieve data register */ +#define I2C3_ICRXD (I2C3_BASE + 0x0024U) +/* Transmit data register */ +#define I2C3_ICTXD (I2C3_BASE + 0x0024U) +/* Clock control register 2 */ +#define I2C3_ICCCR2 (I2C3_BASE + 0x0028U) + + +/* I2C ch? base address */ +#define I2C5_BASE (BASE_I2C5_ADDR) /* Physical address:0xE66E0000, Logical address:0xFDCE0000 */ + +/* Slave control register */ +#define I2C5_ICSCR (I2C5_BASE + 0x0000U) +/* Master control register */ +#define I2C5_ICMCR (I2C5_BASE + 0x0004U) +/* Slave status register */ +#define I2C5_ICSSR (I2C5_BASE + 0x0008U) +/* Master status register */ +#define I2C5_ICMSR (I2C5_BASE + 0x000CU) +/* Slave interrupt enable register */ +#define I2C5_ICSIER (I2C5_BASE + 0x0010U) +/* Master interrupt enable register */ +#define I2C5_ICMIER (I2C5_BASE + 0x0014U) +/* Clock control register */ +#define I2C5_ICCCR (I2C5_BASE + 0x0018U) +/* Slave address register */ +#define I2C5_ICSAR (I2C5_BASE + 0x001CU) +/* Master address register */ +#define I2C5_ICMAR (I2C5_BASE + 0x0020U) +/* Recieve data register */ +#define I2C5_ICRXD (I2C5_BASE + 0x0024U) +/* Transmit data register */ +#define I2C5_ICTXD (I2C5_BASE + 0x0024U) +/* Clock control register 2 */ +#define I2C5_ICCCR2 (I2C5_BASE + 0x0028U) +/* SCL mask Control register */ +#define I2C5_ICMPR (I2C5_BASE + 0x002CU) +/* SCL high Control register */ +#define I2C5_ICHPR (I2C5_BASE + 0x0030U) +/* SCL low Control register */ +#define I2C5_ICLPR (I2C5_BASE + 0x0034U) +/* First bit setup cycle register */ +#define I2C5_ICFBSCR (I2C5_BASE + 0x0038U) + +#endif /* I2C_REGISTER_H__ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/image_load.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/image_load.h new file mode 100644 index 0000000..8d97917 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/image_load.h @@ -0,0 +1,150 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function header + ******************************************************************************/ + +#ifndef LOAD_IMAGE_H_ +#define LOAD_IMAGE_H_ + +/* define */ +/* For Build Option RTOS_LOAD_NUM */ +#define RTOS_LOAD_NUM_1 (1U) /* RTOS is RTOS#0 only. */ +#define RTOS_LOAD_NUM_3 (3U) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */ + +/* For Build Option OPTEE_LOAD_ENABLE */ +#define OPTEE_DISABLE (0U) /* Load OP-TEE image disable. */ +#define OPTEE_ENABLE (1U) /* Load OP-TEE image enable. */ + +/* ICUMX Loader */ +#define IPL_TOP (0xEB210000U) +#define IPL_SIZE (128U * 1024U) +#define IPL_END ((IPL_TOP +IPL_SIZE) - 1U) + +#define MCU_OFFSET (0x0200U) /* 512byte */ + +/* Certificate logical address */ +extern char __ghsbegin_sa9_load[]; +#define SA9_DEST_ADDR (uintptr_t)(&__ghsbegin_sa9_load[0]) +#define CONTENT_CERT_OFFSET (0x6000U) + +/* key cert address */ +#define TFMV_KEY_CERT_ADDR (SA9_DEST_ADDR + CONTENT_CERT_INFO_SIZE) /* 0xFDE31000 */ +#define NTFMV_KEY_CERT_ADDR (TFMV_KEY_CERT_ADDR + KEY_CERT_SIZE) /* 0xFDE33000 */ + +/* Size of each content contained in SA9. */ +#define KEY_CERT_SIZE (0x00002000U) /* Key cert size(8KiB) */ +#define CONTENT_CERT_INFO_SIZE (0x00001000U) /* Content cert header size(4KiB) */ +#define CONTENT_CERT_SIZE (0x00000800U) /* content cert src size(2KiB) */ +#define MIN_VER_TBL_SIZE (0x00001000U) /* Software minimum version table */ + +/* Load ID */ +#define SECURE_FW_ID (0U) /* 0:Secure Firmware */ +#define RTOS_ID (1U) /* 1:RTOS#0 */ +#define CA_PROGRAM_ID (2U) /* 2:CX 2nd IPL */ +#define ICUMH_PROGRAM_ID (3U) /* 3:ICUMH program */ +#define G4MH_PROGRAM_ID (4U) /* 4:G4MH program(1st) 5:G4MH program(2nd) */ +#define CA_OPTIONAL_ID (6U) /* 6:CA Program#1, 7:CA Program#2 ... 13:CA Program#8 */ +#define TFMV_MIN_VER_TBL_ID (14U) /* 14:TFMV Software minimum version table */ +#define NTFMV_MIN_VER_TBL_ID (15U) /* 15:NTFMV Software minimum version table */ +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RTOS1_ID (16U) /* 16:RTOS#1 */ +#define RTOS2_ID (17U) /* 17:RTOS#2 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* Number of Max loading image */ +#define NUM_OF_ALWAYS_LOAD_CERT (6U) /* Secure FW + RTOS + Cx IPL + ICUMH + (G4MH * 2) */ +#define CA_MAX_IMAGE (8U) /* CA program MAX image num */ + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1) +#define MAX_PLACED (16U) /* IPL (or minimum version table) + Secure FW + RTOS * + * + Cx IPL + (CA program * 8) + ICUMH + G4MH */ +#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define MAX_PLACED (18U) /* IPL (or minimum version table) + Secure FW + RTOS#0 * + * + Cx IPL + (CA program * 8) + ICUMH + G4MH + RTOS#1 + RTOS#2 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_1 */ + +#define TARGET_MEM_DRAM (0U) +#define TARGET_MEM_RTSRAM (1U) +#define TARGET_MEM_RTVRAM (2U) +#define TARGET_MEM_SYSRAM (3U) +#define TARGET_MEM_CODESRAM (4U) + +/* get info from cert address offset */ +#define CERT_INFO_SIZE_OFFSET (0x00000264U) /* Offset Type1 */ +#define CERT_INFO_DST_OFFSET (0x00000154U) /* Offset Type1 */ +#define CERT_INFO_SIZE_OFFSET1 (0x00000364U) /* Offset Type2 */ +#define CERT_INFO_DST_OFFSET1 (0x000001D4U) /* Offset Type2 */ +#define CERT_INFO_SIZE_OFFSET2 (0x00000464U) /* Offset Type2 */ +#define CERT_INFO_DST_OFFSET2 (0x00000254U) /* Offset Type2 */ + +#define FLASH_BOOT (0U) +#define EMMC_BOOT (1U) + +#define CERT_INFO_FLG_OFFSET (0x0000000CU) +#define KEY_SIZE_BIT_SHIFT (21U) + +/* Parameter info of secure data (for ICUM FW) */ +#define SECUREDATA_SIZE (112U * 1024U) /* 112KB */ + +/* struct */ +/* load address range */ +typedef struct { + uint32_t topadd; + uint32_t endadd; +} ADDRESS_RANGE; + +/* load info */ +typedef struct{ + const char *name; /* store load image name */ + uint32_t image_size; /* store image size */ + uint32_t boot_addr; /* store boot address of image */ + uint32_t key_cert_addr; /* store key cert address */ + uint32_t cnt_cert_addr; /* store content cert address */ + uint32_t src_addr; /* store source address */ + uint32_t part_num; /* store eMMC partition number */ + uint32_t image_id; /* store image ID */ +} LOAD_INFO; + +static inline uint32_t get_src_addr_offset_in_cert(uint32_t id) +{ + return (SA9_DEST_ADDR + ((id * 0x10U) + 0x8U)); +} + +static inline uint32_t get_logic_cont_cert_addr(uint32_t num) +{ + return (SA9_DEST_ADDR + CONTENT_CERT_OFFSET + (num * CONTENT_CERT_SIZE)); +} + +/* Prototype */ +uint32_t load_content_cert(int slot); +void load_image(LOAD_INFO* li); +void load_init(LOAD_INFO* li, int slot); +void check_load_area(const LOAD_INFO* li); +void load_start(const LOAD_INFO* li); +void load_end(void); +void check_overflow(uint32_t addr, uint32_t len, uint32_t *end_addr, const char *func_name); +void load_securedata(uint32_t target_id, int slot); +#endif /* LOAD_IMAGE_H_ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/image_load_emmc.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/image_load_emmc.h new file mode 100644 index 0000000..64831f2 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/image_load_emmc.h @@ -0,0 +1,73 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function for eMMC header + ******************************************************************************/ + +#ifndef LOAD_IMAGE_EMMC_H_ +#define LOAD_IMAGE_EMMC_H_ + +#include +#include +#include +#include + +/* define */ +/* eMMC */ +#define EMMC_TOP (0x00000000U) +#define EMMC_BOOT_PART_SIZE (31U * 1024U * 1024U) /* 31MB */ +#define EMMC_END ((EMMC_TOP + EMMC_BOOT_PART_SIZE) - 1U) +#define SRC_TOP (EMMC_TOP) +#define SRC_END (EMMC_END) + +/* For eMMC */ +#define EMMC_SECTOR_SIZE (512U) +#define EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */ +#define EMMC_CONTENT_CERT_ADDR (0x00240000U) +#define EMMC_CONTENT_CERT_SECTOR_NUMBER (EMMC_CONTENT_CERT_ADDR >> EMMC_SECTOR_SIZE_SHIFT) +#define EMMC_PARTITION_1 (1U) +#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) +#define EMMC_VER_TBL_OFFSET (0x0000D000U) +#define EMMC_VER_TBL_CNT_CERT_ADDR (EMMC_CONTENT_CERT_ADDR + EMMC_VER_TBL_OFFSET) +#define EMMC_VER_TBL_CNT_CERT_SEC_NUM (EMMC_VER_TBL_CNT_CERT_ADDR >> EMMC_SECTOR_SIZE_SHIFT) +#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */ + +static inline void load_image_info_print_for_emmc(const LOAD_INFO* li) +{ + NOTICE("======== %s image load info ========\n" + "load address \t= 0x%08x\n" "image size \t= 0x%08x\n" + "source address \t= (p:%d)0x%08x\n", + li->name, li->boot_addr, li->image_size, + li->part_num, li->src_addr); +} + +static inline uint32_t get_part_num_in_cert(uint32_t id) +{ + return (SA9_DEST_ADDR + ((id + 1U) * 0x10U)); +} + +/* Prototype */ +uint32_t load_content_cert_for_emmc(void); +#endif /* LOAD_IMAGE_EMMC_H_ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/image_load_flash.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/image_load_flash.h new file mode 100644 index 0000000..4356999 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/image_load_flash.h @@ -0,0 +1,69 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function for eMMC header + ******************************************************************************/ + +#ifndef LOAD_IMAGE_FLASH_H_ +#define LOAD_IMAGE_FLASH_H_ + +#include +#include +#include +#include + +/* define */ +/* Flash address */ +#define FLASH_BASE (0x08000000U) +#define FLASH_SIZE (0x04000000U) +#define FLASH_END ((FLASH_BASE + FLASH_SIZE) - 1U) +#define SRC_TOP (FLASH_BASE) +#define SRC_END (FLASH_END) + +/* Flash address of content certificate */ +#define CONTENT_CERT_SA (9U) /* Content Cert SA9 */ +#define SA_SIZE (0x00040000U) +#define CONTENT_CERT_2nd_OFFSET (0x00280000U) /* 256KB * 10 */ +#define FLASH_CONTENT_CERT_ADDR (uint32_t)(FLASH_BASE + (SA_SIZE * CONTENT_CERT_SA)) /* FLASH Base + SA9 offset */ +#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) +#define VER_TBL_CNT_CERT_OFFSET (0x0000D000U) +#define FLASH_VER_TBL_CNT_CERT_ADDR (FLASH_CONTENT_CERT_ADDR + VER_TBL_CNT_CERT_OFFSET) /* SA9 top + offset */ +#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */ +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RTOS12_CNT_CERT_OFFSET (0x0000E000U) +#define FLASH_RTOS12_CNT_CERT_ADDR (FLASH_CONTENT_CERT_ADDR + RTOS12_CNT_CERT_OFFSET) /* SA9 top + offset */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +static inline void load_image_info_print_for_flash(const LOAD_INFO* li) +{ + NOTICE("======== %s image load info ========\n" + "load address \t= 0x%08x\n" "image size \t= 0x%08x\n" + "source address \t= 0x%08x\n", + li->name, li->boot_addr, li->image_size, li->src_addr); +} + +/* Prototype */ +uint32_t load_content_cert_for_flash(int slot); +#endif /* LOAD_IMAGE_FLASH_H_ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/inline_asm.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/inline_asm.h new file mode 100644 index 0000000..5f9f38f --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/inline_asm.h @@ -0,0 +1,41 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : inline asm func header + ******************************************************************************/ + +#ifndef INLINE_ASM_H__ +#define INLINE_ASM_H__ + +static inline void syncm(void) +{ + __asm__ __volatile__ ("SYNCM"); +} + +static inline void synci(void) +{ + __asm__ __volatile__ ("SYNCI"); +} + +#endif /* INLINE_ASM_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/intc.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/intc.h new file mode 100644 index 0000000..b783201 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/intc.h @@ -0,0 +1,58 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : window watchdog timer function header + ******************************************************************************/ + +#ifndef INTC_H__ +#define INTC_H__ + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + +#define INTC1_BASE (0xFFFEEA00UL) +#define INTC2_BASE (0xFFFEF000UL) + +typedef void (* INT_HANDLER)(uint32_t int_no, uint32_t arg); + +static inline uint32_t get_icumx_ic_addr(uint32_t id) +{ + uint32_t ret; + if(id < 32U) + { + ret = INTC1_BASE + (0x02U * (id % 32U)); + } + else + { + ret = (INTC2_BASE + 0x40U) + (0x02U * (id % 32U)); + } + return ret; +} + +void intc_set_interrupt(uint32_t int_no, uint32_t level, INT_HANDLER cb); +void intc_disable_interrupt(uint32_t int_no); +void intc_handler(void); + +#endif /* INTC_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/intc_id.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/intc_id.h new file mode 100644 index 0000000..764ab7a --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/intc_id.h @@ -0,0 +1,71 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Interrupt controler ID header + ******************************************************************************/ + +#ifndef INTC_ID_H_ +#define INTC_ID_H_ + +#define ECC_ERR_LRAM (0U) /* ECC Error Detection for Local RAM */ +#define ECC_ERR_CACHE (1U) /* ECC Error Detection for Cache RAM */ +#define EDC_ERR_INT_AXI (2U) /* EDC Error interrupt of AXI */ +#define ECC_ERR_INT_AXIAB (3U) /* ECC Error interrupt of AXIAB */ +#define ECC_ERR_INT_PKCC (4U) /* ECC Error interrupt of PKCC */ +#define CORTEX_INT_REQ_SINGLE_CORE (5U) /* Cortex-R/A interrupt request (single main core) */ +#define CORTEX_INT_REQ_SEL_SINGLE_CORE (6U) /* Cortex-R/A interrupt request (selected single main core) */ +#define COMPLETION_AES (7U) /* Completion of AES encryption or decryption */ + /* ID 8 Reserved */ +#define COMPLETION_RAND_NUMBER (9U) /* Random number generation complete */ +#define OSTIMER0_OVERFLOW (10U) /* OS Timer 0 overflow */ +#define OSTIMER1_OVERFLOW (11U) /* OS Timer 1 overflow */ +#define WDT0_INT (12U) /* Watchdog Timer 0 interrupt (at 75%) */ +#define COMPLETION_PKCC (13U) /* Completion of PKCC operation */ +#define COMPLETION_DMAC_CH5CH6 (14U) /* Interrupt request by transfer completion for channel-5/6 */ +#define INT_REQ_BRESP_RRESP_ERR_AXI (15U) /* Interrupt request by BRESP/RRESP-error for AXI */ + /* ID 16 Reserved */ +#define REQ_SHAA0 (17U) /* Input data request for SHAA0 */ +#define COMPLETION_SHAA0 (18U) /* Completion or suspension of SHAA0 data output */ +#define REQ_CHALLENGE_DATA_FOR_ARM_DEBUG (19U) /* Challenge data request for ARM Debugger */ +#define REQ_RES_COMP_FOR_ARM_DEBUG (20U) /* Response data compare request for ARM Debugger */ +#define REQ_CHALLENGE_DATA_FOR_RH850_DEBUG (21U) /* Challenge data request for RH850 Debugger */ +#define REQ_RES_COMP_FOR_RH850_DEBUG (22U) /* Response data compare request for RH850 Debugger */ +#define REQ_CHALLENGE_DATA_FOR_RH850_DEBUG_R (23U) /* Challenge data request for RH850 Debugger r */ + /* Reserved */ +#define ACC_ERR_MASKROM_RTSRAM (25U) /* Data access error detection of Mask ROM or RTSRAM area */ +#define ACC_ERR_EXCEPT_MASKROM_RTSRAM (26U) /* Data access error detection except Mask ROM and RT-SRAM area */ + /* ID 27 Reserved */ + /* ID 28 Reserved */ +#define RTSRAM_SAFETY_ERR (29U) /* RT-SRAM Error Safety Error Detection */ +#define RTSRAM_SECURE_ERR (30U) /* RT-SRAM Error Secure Error Detection */ +#define RTSRAM_EDC_ERR (31U) /* RT-SRAM Error EDC Error Detection */ +#define RTSRAM_DUPLEX_ERR (32U) /* RT-SRAM Error Duplex circuit Error Detection */ +#define RTSRAM_SYSRAM_2BIT_ERR (33U) /* RT-SRAM Error SYSRAM 2bit Error Detection */ +#define RTSRAM_SYSRAM_1BIT_ERR (34U) /* RT-SRAM Error SYSRAM 1bit Error Detection */ +#define SECROM_SYSRAM_2BIT_ERR (35U) /* Sec ROM Error SYSRAM 2bit Error Detection */ +#define SECROM_SYSRAM_1BIT_ERR (36U) /* Sec ROM Error SYSRAM 1bit Error Detection */ +#define COMPLETION_SECURE_BOOT_ENGINE_CALC (37U) /* Completion of secure boot engine calculation */ + /* ID 38 -- 63 Reserved */ + +#endif /* INTC_ID_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ip_control.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ip_control.h new file mode 100644 index 0000000..aefd1f4 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ip_control.h @@ -0,0 +1,34 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : IP's control header + ******************************************************************************/ +#ifndef IP_CONTROL_H_ +#define IP_CONTROL_H_ + +/* Prototype */ +void ip_init(void); +void ip_release(void); + +#endif /* IP_CONTROL_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/loader_main.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/loader_main.h new file mode 100644 index 0000000..3a250e9 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/loader_main.h @@ -0,0 +1,36 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main header + ******************************************************************************/ + +#ifndef LOADER_MAIN_H_ +#define LOADER_MAIN_H_ + +/* prototype */ +uint32_t loader_main(void); +#if (RCAR_LSI == RCAR_V4H) +void clear_ecm_st_axi(void); +#endif +#endif /* LOAD_MAIN_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/loader_main_common.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/loader_main_common.h new file mode 100644 index 0000000..6b8d8bd --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/loader_main_common.h @@ -0,0 +1,44 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main common header + ******************************************************************************/ + +#ifndef LOADER_MAIN_COMMON_H_ +#define LOADER_MAIN_COMMON_H_ + + +/* define */ +#define IPL_VERSION "1.58.0" + +#define ADD_MAGIC_NUMBER (1U) + +/* Global */ +extern const char build_message[]; + +/* prototype */ +void print_boot_msg(void); +void wa_setting_apmu(void); + +#endif /* LOADER_MAIN_COMMON_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/log.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/log.h new file mode 100644 index 0000000..df767b8 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/log.h @@ -0,0 +1,86 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Log driver header + ******************************************************************************/ + +#ifndef LOG_H__ +#define LOG_H__ + +#include +#include + +#define LOG_NONE (0) +#define LOG_ERROR (1) +#define LOG_NOTICE (2) +#define LOG_WARNING (3) +#define LOG_INFO (4) +#define LOG_VERBOSE (5) + +#if LOG_LEVEL >= LOG_ERROR +#include +#endif + +#if LOG_LEVEL >= LOG_VERBOSE +# define VERBOSE(...) local_printf("V:" __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + +#if LOG_LEVEL >= LOG_INFO +# define INFO(...) local_printf("I:" __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_WARNING +# define WARN(...) local_printf("W:" __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_ERROR +# define ERROR(...) local_printf("E:" __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_NOTICE +# define NOTICE(...) local_printf("N:" __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#define panic \ + do { \ + panic_printf(__func__); \ + while(true){} \ + } while (false) + +#if LOG_LEVEL >= LOG_ERROR +void local_printf(const char *fmt, ...); +#endif +void panic_printf(const char *str); + +#endif /* LOG_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mcu_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mcu_register.h new file mode 100644 index 0000000..bd28444 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mcu_register.h @@ -0,0 +1,125 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MCU register header + ******************************************************************************/ + +#ifndef MCU_REGISTER_H_ +#define MCU_REGISTER_H_ + +#include + +/* The Base is remapped in the IPL, and the address is calculated and accessed + * by adding the offset to the remapped address. */ +#define MCU_BASE (BASE_MCU_ADDR) + +/* SCDS0 (0xD8F00800) */ +#define MCU_ICUM_OPBT0 (MCU_BASE + 0x09C0U) +#define MCU_ICUM_OPBT1 (MCU_BASE + 0x09C4U) +#define MCU_ICUM_OPBT2 (MCU_BASE + 0x09C8U) +#define MCU_ICUM_OPBT4 (MCU_BASE + 0x09D0U) +#define MCU_ICUM_OPBT5 (MCU_BASE + 0x09D4U) +#define MCU_ICUM_OPBT6 (MCU_BASE + 0x09D8U) +#define MCU_ICUM_OPBT7 (MCU_BASE + 0x09DCU) +#define MCU_GREG120 (MCU_BASE + 0x09E0U) + +/* SCDS2 (0xD8F00C00) */ +#define MCU_RESET_VECTOR_PE0 (MCU_BASE + 0x0C00U) +#define MCU_RESET_VECTOR_PE1 (MCU_BASE + 0x0C04U) +#define MCU_OPBT0 (MCU_BASE + 0x0C20U) +#define MCU_OPBT1 (MCU_BASE + 0x0C24U) +#define MCU_OPBT2 (MCU_BASE + 0x0C28U) +#define MCU_OPBT3 (MCU_BASE + 0x0C2CU) +#define MCU_OPBT4 (MCU_BASE + 0x0C30U) +#define MCU_OPBT6 (MCU_BASE + 0x0C38U) +#define MCU_OPBT7 (MCU_BASE + 0x0C3CU) +#define MCU_OPBT8 (MCU_BASE + 0x0C40U) +#define MCU_OPBT9 (MCU_BASE + 0x0C44U) +#define MCU_OPBT96 (MCU_BASE + 0x0CA0U) + +/* MCCR_SELB0 (0xD8F01000) */ +#define MCU_OPBT_STAT (MCU_BASE + 0x1000U) +#define MCU_OPBT_CTRL (MCU_BASE + 0x1004U) +#define MCU_G4MH_BOOT_CTLR (MCU_BASE + 0x1008U) +#define MCU_ICUMH_BOOT_CTLR (MCU_BASE + 0x100CU) +#define MCU_BOOT_STAT (MCU_BASE + 0x1024U) + +/* MCCR_SELB1 (0xD8F02000) */ + +/* HBG (0xD8F12000) */ +#define MCU_HBG_CS0_HBGPROT0 (MCU_BASE + 0x00012000U) +#define MCU_HBG_CS1_HBGPROT0 (MCU_BASE + 0x00012100U) +#define MCU_HBG_CS2_HBGPROT0 (MCU_BASE + 0x00012200U) +#define MCU_HBG_CS3_HBGPROT0 (MCU_BASE + 0x00012300U) +#define MCU_HBG_CS4_HBGPROT0 (MCU_BASE + 0x00012400U) +#define MCU_HBG_CS5_HBGPROT0 (MCU_BASE + 0x00012500U) +#define MCU_HBG_DS_HBGPROT0 (MCU_BASE + 0x00012600U) +#define MCU_HBG_PFS_HBGPROT0 (MCU_BASE + 0x00012700U) +#define MCU_HBG_SOCM_HBGPROT0 (MCU_BASE + 0x00012800U) +#define MCU_HBG_SOCS_HBGPROT0 (MCU_BASE + 0x00012900U) + +/* HBGSLVER (0xD8F19000) */ +#define MCU_HBGSLVER_CS0_HBGKCPROT (MCU_BASE + 0x00019018U) +#define MCU_HBGSLVER_CS1_HBGKCPROT (MCU_BASE + 0x00019118U) +#define MCU_HBGSLVER_CS2_HBGKCPROT (MCU_BASE + 0x00019218U) +#define MCU_HBGSLVER_CS3_HBGKCPROT (MCU_BASE + 0x00019318U) +#define MCU_HBGSLVER_CS4_HBGKCPROT (MCU_BASE + 0x00019418U) +#define MCU_HBGSLVER_CS5_HBGKCPROT (MCU_BASE + 0x00019518U) +#define MCU_HBGSLVER_DS_HBGKCPROT (MCU_BASE + 0x00019618U) +#define MCU_HBGSLVER_PFS_HBGKCPROT (MCU_BASE + 0x00019718U) +#define MCU_HBGSLVER_SOCM_HBGKCPROT (MCU_BASE + 0x00019818U) +#define MCU_HBGSLVER_SOCS_HBGKCPROT (MCU_BASE + 0x00019918U) + +/* PBG (0xD8F01800) */ +#define MCUAXI_PBG_PBGPROT0_0 (MCU_BASE + 0x1800U) +#define MCUAXI_PBG_PBGPROT0_1 (MCU_BASE + 0x1808U) +#define MCUAXI_PBG_PBGPROT0_2 (MCU_BASE + 0x1810U) +#define MCUAXI_PBG_PBGPROT0_3 (MCU_BASE + 0x1818U) +#define MCUAXI_PBG_PBGPROT0_4 (MCU_BASE + 0x1820U) +#define MCUAXI_PBG_PBGPROT0_5 (MCU_BASE + 0x1828U) +#define MCUAXI_PBG_PBGPROT0_6 (MCU_BASE + 0x1830U) +#define MCUAXI_PBG_ERRSLV_PBGKCPROT (MCU_BASE + 0x00018118U) + + +/* CSRM (0xD8F10000) */ +#define MCU_CSRM0ECCCTL (MCU_BASE + 0x00010000U) +#define MCU_CSRM1ECCCTL (MCU_BASE + 0x00010100U) +#define MCU_CSRM2ECCCTL (MCU_BASE + 0x00010200U) +#define MCU_CSRM3ECCCTL (MCU_BASE + 0x00010300U) +#define MCU_CSRM4ECCCTL (MCU_BASE + 0x00010400U) +#define MCU_CSRM5ECCCTL (MCU_BASE + 0x00010500U) +#define MCU_CSRM0APCTL (MCU_BASE + 0x00010050U) +#define MCU_CSRM1APCTL (MCU_BASE + 0x00010150U) +#define MCU_CSRM2APCTL (MCU_BASE + 0x00010250U) +#define MCU_CSRM3APCTL (MCU_BASE + 0x00010350U) +#define MCU_CSRM4APCTL (MCU_BASE + 0x00010450U) +#define MCU_CSRM5APCTL (MCU_BASE + 0x00010550U) +#define MCU_CSRM0CSIFCODE (MCU_BASE + 0x00010080U) +#define MCU_CSRM1CSIFCODE (MCU_BASE + 0x00010180U) +#define MCU_CSRM2CSIFCODE (MCU_BASE + 0x00010280U) +#define MCU_CSRM3CSIFCODE (MCU_BASE + 0x00010380U) +#define MCU_CSRM4CSIFCODE (MCU_BASE + 0x00010480U) +#define MCU_CSRM5CSIFCODE (MCU_BASE + 0x00010580U) + +#endif /* MCU_REGISTER_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mem_io.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mem_io.h new file mode 100644 index 0000000..1ab5cbd --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mem_io.h @@ -0,0 +1,84 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Memory access driver header + ******************************************************************************/ +#ifndef MEM_IO_H_ +#define MEM_IO_H_ + +#include + +static inline void mem_write8(uintptr_t addr, uint8_t data) +{ + *(volatile uint8_t*)addr = data; +} + +static inline uint8_t mem_read8(uintptr_t addr) +{ + return (*(volatile uint8_t*)addr); +} + +static inline void mem_write16(uintptr_t addr, uint16_t data) +{ + *(volatile uint16_t*)addr = data; +} + +static inline uint16_t mem_read16(uintptr_t addr) +{ + return (*(volatile uint16_t*)addr); +} + +static inline void mem_write32(uintptr_t addr, uint32_t data) +{ + *(volatile uint32_t*)addr = data; +} + +static inline uint32_t mem_read32(uintptr_t addr) +{ + return (*(volatile uint32_t*)addr); +} + +static inline void mem_write64(uintptr_t addr, uint64_t data) +{ + *(volatile uint64_t*)addr = data; +} + +static inline uint64_t mem_read64(uintptr_t addr) +{ + return (*(volatile uint64_t*)addr); +} + +static inline void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set) +{ + mem_write32(addr, (mem_read32(addr) & ~clr) | set); +} + +#if defined(__RH850G3K__) +#define mmio_write_32(a,b) mem_write32(a,b) +#define mmio_read_32(a) mem_read32(a) +#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c) +#endif + + +#endif /* MEM_IO_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mfis.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mfis.h new file mode 100644 index 0000000..52ed336 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mfis.h @@ -0,0 +1,39 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MFIS driver header + ******************************************************************************/ + +#ifndef MFIS_H__ +#define MFIS_H__ + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + +void mfis_init(void); +void mfis_lock(void); +void mfis_unlock(void); + +#endif /* MFIS_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mfis_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mfis_register.h new file mode 100644 index 0000000..cd93e2f --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/mfis_register.h @@ -0,0 +1,45 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MFIS register header + ******************************************************************************/ + +#ifndef MFIS_REGISTER_H__ +#define MFIS_REGISTER_H__ + +#include + +/* The Base is remapped in the IPL, and the address is calculated and accessed + * by adding the offset to the remapped address. */ +#define MFIS_BASE (BASE_MFIS_ADDR) + +#define MFISLCKR_ADDRESS (0x0800U) /* MFISLCKR[j] Address 0x724 +(4U*(63U-8U)) */ + +/* Register Definition */ +#define MFIS_LCKR (MFIS_BASE + MFISLCKR_ADDRESS) /* MFIS Lock Register */ +#define MFIS_WPCNTR (MFIS_BASE + 0x0900U) /* Write Protection Control Register */ +#define MFIS_WACNTR (MFIS_BASE + 0x0904U) /* Write Access Control Register */ + + +#endif /* MFIS_REGISTER_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/micro_wait.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/micro_wait.h new file mode 100644 index 0000000..a16a913 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/micro_wait.h @@ -0,0 +1,39 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Time wait driver header + ******************************************************************************/ + +#ifndef MICRO_WAIT_H_ +#define MICRO_WAIT_H_ + +#include + +/* Define */ + +/* Prototype */ +void micro_wait(uint32_t count_us); + + +#endif /* MICRO_WAIT_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/pfc.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/pfc.h new file mode 100644 index 0000000..4c5b970 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/pfc.h @@ -0,0 +1,41 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : PFC driver header + ******************************************************************************/ + +#ifndef PFC_H__ +#define PFC_H__ + +#include +#include +#include + +static inline void pfc_reg_write(uint32_t addr, uint32_t data) +{ + mem_write32(get_pmmr_addr(addr), ~data); + mem_write32(addr, data); +} + +#endif /* PFC_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/pfc_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/pfc_register.h new file mode 100644 index 0000000..6904ffe --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/pfc_register.h @@ -0,0 +1,154 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : PFC register header + ******************************************************************************/ + + +#ifndef PFC_REGISTER_H__ +#define PFC_REGISTER_H__ + +#include +#include + +/* PFC / GPIO base address */ +/* 0xE6050000 */ +#define PFC_BASE (BASE_PFC_ADDR) + +#define PFC_RW_OFFSET (0x0000U) +#define PFC_SET_OFFSET (0x0200U) +#define PFC_CLR_OFFSET (0x0400U) + +#if (RCAR_LSI == RCAR_S4) +#define PFC_MCU_BASE (BASE_PFCMCU_ADDR) + +#define PFC_PORT_GRP0 (0x00000000U) /* Port Group0/4 */ +#define PFC_PORT_GRP1 (0x00000800U) /* Port Group1/5 */ +#define PFC_PORT_GRP2 (0x00001000U) /* Port Group2/6 */ +#define PFC_PORT_GRP3 (0x00001800U) /* Port Group3/7 */ +#define PFC_SYS_GRP (0x00028000U) /* System Group0/1 */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define PFC_PORT_GRP0 (0x00000000U) /* Port Group0 */ +#define PFC_PORT_GRP1 (0x00000800U) /* Port Group1 */ +#define PFC_PORT_GRP2 (0x00008000U) /* Port Group2 */ +#define PFC_PORT_GRP3 (0x00008800U) /* Port Group3 */ +#define PFC_PORT_GRP4 (0x00010000U) /* Port Group4 */ +#define PFC_PORT_GRP5 (0x00010800U) /* Port Group5 */ +#define PFC_PORT_GRP6 (0x00011000U) /* Port Group6 */ +#define PFC_PORT_GRP7 (0x00011800U) /* Port Group7 */ +#if (RCAR_LSI == RCAR_V4H) +#define PFC_PORT_GRP8 (0x00018000U) /* Port Group8 */ +#endif +#define PFC_SYS_GRP (0x00028000U) /* System Group0 */ +#endif + +/* PFC / GPIO registers */ +/* Read/Write registers */ +#define PFC_PORT_GRP_MASK (0xFFFFF800U) + +/* Port Group0 */ +#define PFC_DM1PR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x002CU) +#define PFC_GPSR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0040U) +#define PFC_IP0SR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0060U) +#define PFC_POC0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x00A0U) +/* Port Group1 */ +#define PFC_DM1PR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x002CU) +#define PFC_GPSR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0040U) +#define PFC_IP1SR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0064U) +#define PFC_IP2SR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0068U) +#define PFC_POC1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x00A0U) +/* Port Group2 */ +#define PFC_DM1PR2_RW (PFC_BASE + PFC_PORT_GRP2 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR2_RW (PFC_BASE + PFC_PORT_GRP2 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR2_RW (PFC_BASE + PFC_PORT_GRP2 + PFC_RW_OFFSET + 0x002CU) +/* Port Group3 */ +#define PFC_DM1PR3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x002CU) +#define PFC_POC3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x00A0U) +#define PFC_PUEN3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x00C0U) +/* Port Group4 */ +#define PFC_DM1PR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x002CU) +/* Physical address:0xE6060040, Logical address:0x0xFDA60040 */ +#define PFC_GPSR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0040U) +/* Physical address:0xE6060060, Logical address:0x0xFDA60060 */ +#define PFC_IP0SR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0060U) +/* Physical address:0xE60600C0, Logical address:0x0xFDA600C0 */ +#define PFC_PUEN4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x00C0U) +/* Physical address:0xE6060100, Logical address:0x0xFDA60100 */ +#define PFC_MODSEL4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0100U) +#define PFC_IOINTSEL4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0180U) +#define PFC_INOUTSEL4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0184U) +#define PFC_OUTDT4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0188U) +#define PFC_INDT4_R (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x018CU) +#define PFC_POSNEG4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x01A0U) +#define PFC_OUTDTSEL4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x01C0U) +#define PFC_OUTDTH4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x01C4U) +#define PFC_OUTDTL4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x01C8U) +#define PFC_INEN4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x01D0U) +/* Port Group5 */ +#define PFC_DM1PR5_RW (PFC_BASE + PFC_PORT_GRP5 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR5_RW (PFC_BASE + PFC_PORT_GRP5 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR5_RW (PFC_BASE + PFC_PORT_GRP5 + PFC_RW_OFFSET + 0x002CU) +/* Port Group6 */ +#define PFC_DM1PR6_RW (PFC_BASE + PFC_PORT_GRP6 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR6_RW (PFC_BASE + PFC_PORT_GRP6 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR6_RW (PFC_BASE + PFC_PORT_GRP6 + PFC_RW_OFFSET + 0x002CU) +/* Port Group7 */ +#define PFC_DM1PR7_RW (PFC_BASE + PFC_PORT_GRP7 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR7_RW (PFC_BASE + PFC_PORT_GRP7 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR7_RW (PFC_BASE + PFC_PORT_GRP7 + PFC_RW_OFFSET + 0x002CU) +#if (RCAR_LSI == RCAR_V4H) +/* Port Group8 */ +#define PFC_DM1PR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x002CU) +#define PFC_INOUTSEL8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0184U) +#define PFC_OUTDT8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0188U) +#endif +/* System Group */ +#define PFC_DM1PRSYS_RW (PFC_BASE + PFC_SYS_GRP + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PRSYS_RW (PFC_BASE + PFC_SYS_GRP + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PRSYS_RW (PFC_BASE + PFC_SYS_GRP + PFC_RW_OFFSET + 0x002CU) + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +/* Physical address:0xE6068040 */ +#define PFC_GPSR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0040U) +#define PFC_IP1SR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0064U) +#define PFC_PUEN8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x00C0U) +#define PFC_MODSEL8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0100U) +#endif + +static inline uint32_t get_pmmr_addr(uint32_t addr) +{ + return (addr & PFC_PORT_GRP_MASK); +} + +#endif /* PFC_REGISTER_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/qos.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/qos.h new file mode 100644 index 0000000..2992d65 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/qos.h @@ -0,0 +1,33 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : QoS driver header + ******************************************************************************/ + +#ifndef QOS_INIT_H_ +#define QOS_INIT_H_ + +extern void qos_init(void); + +#endif /* QOS_INIT_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ram_def.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ram_def.h new file mode 100644 index 0000000..5b4dfb2 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ram_def.h @@ -0,0 +1,84 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : R-Car RAM header + ******************************************************************************/ + +#ifndef RAM_DEF_H_ +#define RAM_DEF_H_ + +#include "remap_register.h" + +/* DRAM address */ +#define DRAM_BASE (0x40000000U) +#define DRAM_SIZE (0x80000000U) +#define DRAM_END ((DRAM_BASE + DRAM_SIZE) - 1U) +#define SDRAM_40BIT_ADDR_TOP (0x0400000000ULL) +/* RT-SRAM */ +#define RTSRAM_BASE (0xEB200000U) +#define RTSRAM_SIZE ((1024U - 16U) * 1024U) /* 1MB - 16KB(stack size) */ +#define RTSRAM_END ((RTSRAM_BASE + RTSRAM_SIZE) - 1U) +/* RT-VRAM */ +#define RTVRAM_BASE (0xE2000000U) +#define RTVRAM_SIZE (1024U * 1024U) /* 1MB */ +#define RTVRAM_END ((RTVRAM_BASE + RTVRAM_SIZE) - 1U) +/* RT-VRAM extend mode */ +#define RTVRAM_VBUF_TOP (RTVRAM_BASE + RTVRAM_SIZE) /* 0xE2100000 */ +#define RTVRAM_VBUF_4M (4U) /* 4MB */ +#define RTVRAM_VBUF_8M (8U) /* 8MB */ +#define RTVRAM_VBUF_12M (12U) /* 12MB */ +#define RTVRAM_VBUF_16M (16U) /* 16MB */ +#define RTVRAM_VBUF_20M (20U) /* 20MB */ +#define RTVRAM_VBUF_24M (24U) /* 24MB */ +#define RTVRAM_VBUF_28M (28U) /* 28MB */ +#define RTVRAM_VBUF_SIZE ((RTVRAM_VBUF_28M - 1U) * 1024U * 1024U) /* 3MB to 27MB (The first 1MB is actual RAM.) */ +#define RTVRAM_VBUF_AREA_SIZE (4U * 1024U * 1024U) /* 4MB */ +#define RTVRAM_VBUF_END ((RTVRAM_VBUF_TOP + RTVRAM_VBUF_SIZE) - 1U) + +/* Code SRAM */ +#if (BOOT_MCU != 0U) +#define CODESRAM_BASE (0x10000000U) +#define CODESRAM_SIZE (6U * 1024U * 1024U) /* 6MB */ +#define CODESRAM_END ((CODESRAM_BASE + CODESRAM_SIZE) - 1U) +#endif /* (BOOT_MCU != 0U) */ + +/* System RAM */ +#define SYSRAM_BASE (0xE6300000U) +#if (RCAR_LSI == RCAR_V4H) +#define SYSRAM_SIZE (1024U * 1024U) /* 1MB */ +#else +#define SYSRAM_SIZE (384U * 1024U) /* 384KB */ +#endif +#define SYSRAM_END ((SYSRAM_BASE + SYSRAM_SIZE) - 1U) + +/* Local RAM */ +#define LOCAL_RAM_BASE (0xFEDE0000U) +#define LOCAL_RAM_SIZE (0x00020000U) /* 128KB */ +#define LOCAL_RAM_END ((LOCAL_RAM_BASE + LOCAL_RAM_SIZE) - 1U) + +/* Data-SRAM */ +#define DATA_SRAM_BASE (0xDF200000U) + +#endif /* RAM_DEF_H_ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ram_protection.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ram_protection.h new file mode 100644 index 0000000..287e9d4 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/ram_protection.h @@ -0,0 +1,162 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RAM protection driver header + ******************************************************************************/ +#ifndef RAM_PROTECTION_H_ +#define RAM_PROTECTION_H_ + +#include +#include + +#define RTSRAM_AREA1_TOP (0xE0040000U) +#define RTSRAM_ADDR_END (0xE0100000U) +#if (RCAR_LSI == RCAR_S4) +#define RTSRAM_ADDR_OFFSET_MASK (0x000FF000U) +#else +#define RTSRAM_ADDR_OFFSET_MASK (0xFFFFF000U) +#endif +#define RTVRAM_AREA1_TOP (0xE2010000U) +#define RTVRAM_AREA2_TOP (0xE2100000U) +#define RTVRAM_ADDR_END (0xE3C00000U) +#define RTVRAM_ADDR_MASK (0xFFFFF000U) +#if (RCAR_LSI == RCAR_S4) +#define SYSTEM_RAM_ADDR_END (0xE6360000U) +#else /* (RCAR_LSI == RCAR_S4) */ +/* For V4H/V4M */ +#define SYSTEM_RAM_AREA1_TOP (0xE635E000U) +#define SYSTEM_RAM_AREA2_TOP (0xE6360000U) +#define SYSTEM_RAM_ADDR_END (0xE6400000U) +#endif /* (RCAR_LSI == RCAR_S4) */ +#define SYSTEM_RAM_ADDR_MASK (0xFFFFF000U) +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define DRAM_ADDR_AREA1 (0x0401C00000ULL) +#define DRAM_ADDR_AREA2 (0x0401D00000ULL) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define DRAM_ADDR_AREA3 (0x0406400000ULL) +#define DRAM_ADDR_AREA4 (0x0406440000ULL) +#define DRAM_ADDR_AREA5 (0x0407FC0000ULL) +#define DRAM_ADDR_AREA6 (0x0408000000ULL) +#define DRAM_ADDR_AREA7 (0x041DC00000ULL) +#define DRAM_ADDR_AREA8 (0x0420000000ULL) +#define DRAM_ADDR_AREA9 (0x0440000000ULL) +#define DRAM_ADDR_AREA10 (0x0460000000ULL) +#define DRAM_ADDR_AREA11 (0x0480000000ULL) +#define DRAM_ADDR_AREA12 (0x0500000000ULL) +#define DRAM_ADDR_AREA13 (0x0600000000ULL) +#else +#define DRAM_ADDR_AREA3 (0x0404100000ULL) +#define DRAM_ADDR_AREA4 (0x0406400000ULL) +#define DRAM_ADDR_AREA5 (0x0406440000ULL) +#define DRAM_ADDR_AREA6 (0x0407E00000ULL) +#define DRAM_ADDR_AREA7 (0x0407F00000ULL) +#define DRAM_ADDR_AREA8 (0x0407FC0000ULL) +#define DRAM_ADDR_AREA9 (0x0408000000ULL) +#define DRAM_ADDR_AREA10 (0x041DC00000ULL) +#define DRAM_ADDR_AREA11 (0x0420000000ULL) +#define DRAM_ADDR_AREA12 (0x0440000000ULL) +#define DRAM_ADDR_AREA13 (0x0460000000ULL) +#define DRAM_ADDR_AREA14 (0x0480000000ULL) +#define DRAM_ADDR_AREA15 (0x0500000000ULL) +#define DRAM_ADDR_AREA16 (0x0600000000ULL) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#else +#define DRAM_ADDR_AREA1 (0x0401C00000ULL) +#define DRAM_ADDR_AREA2 (0x0406400000ULL) +#define DRAM_ADDR_AREA3 (0x0406440000ULL) +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ +#define DRAM_ADDR_END (0x0700000000ULL) +#define SDRAM_ADDR_MASK (0x3FFFFF0000ULL) + +#define NOT_USED_VALUE (0x00000000U) + +/* For System RAM protection setting */ +#define REGIONID0_WRITE_PRIVILEGE (0x00000001U) /* bit0 */ + +/* RAM DIVISION AREA ID */ +/* RT-SRAM */ +#define RTSRAM_ICUMX_IPL_AREA (0U) /* 0xE0000000 -- 0xE003FFFF */ +#define RTSRAM_ICUMX_FW_AREA (1U) /* 0xE0040000 -- 0xE00FFFFF */ +/* RT-VRAM */ +#define RTVRAM_BLANK_AREA (0U) /* 0xE2000000 -- 0xE200FFFF */ +#define RTVRAM_EXTEND_CACHE_AREA (1U) /* 0xE2010000 -- 0xE20FFFFF */ +#define RTVRAM_RTOS_AREA (2U) /* 0xE2100000 -- 0xE3BFFFFF */ +/* System RAM */ +#define SYSTEM_RAM_CX_2ND_IPL (0U) /* 0xE6300000 -- 0xE635DFFF */ +#define SYSTEM_RAM_SHARED_MEM (1U) /* 0xE635E000 -- 0xE635FFFF */ +/* SDRAM */ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define RTVRAM_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */ +#define CR_FW_SHARED_AREA (1U) /* 0x04_01C00000 -- 0x04_01CFFFFF */ +#define SDRAM_BLANK_AREA (2U) /* OPTEE_DISABLE:0x04_01D00000 -- 0x04_063FFFFF + * OPTEE_ENABLE :0x04_01D00000 -- 0x04_040FFFFF */ +#define SDRAM_PROTECT_AREA (3U) /* OPTEE_DISABLE:0x04_06400000 -- 0x04_0643FFFF + * OPTEE_ENABLE :0x04_04100000 -- 0x04_0643FFFF */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define SDRAM_PUBLIC_AREA (4U) /* 0x04_06440000 -- 0x04_07FBFFFF */ +#define ICCOM_USED_AREA (5U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */ +#define LINUX_USED_AREA (6U) /* 0x04_08000000 -- 0x04_1DBFFFFF */ +#define CAAREA2_USED_AREA (7U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */ +#define CR52_USED_AREA (8U) /* 0x04_20000000 -- 0x04_3FFFFFFF */ +#define CAAREA3_USED_AREA (9U) /* 0x04_40000000 -- 0x04_5FFFFFFF */ +#define CAAREA2_USED_AREA2 (10U) /* 0x04_60000000 -- 0x04_7FFFFFFF */ +#define CAAREA1_USED_AREA (11U) /* 0x04_80000000 -- 0x04_FFFFFFFF */ +#else +#define SDRAM_PROTECT_AREA2 (4U) /* 0x04_06400000 -- 0x04_0643FFFF */ +#define SDRAM_BLANK_AREA2 (5U) /* 0x04_06440000 -- 0x04_07DFFFFF */ +#define OPTEE_SHARED_AREA (6U) /* 0x04_07E00000 -- 0x04_07EFFFFF */ +#define SDRAM_BLANK_AREA3 (7U) /* 0x04_07F00000 -- 0x04_07FBFFFF */ +#define ICCOM_USED_AREA (8U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */ +#define LINUX_USED_AREA (9U) /* 0x04_08000000 -- 0x04_1DBFFFFF */ +#define CAAREA2_USED_AREA (10U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */ +#define CR52_USED_AREA (11U) /* 0x04_20000000 -- 0x04_3FFFFFFF */ +#define CAAREA3_USED_AREA (12U) /* 0x04_40000000 -- 0x04_5FFFFFFF */ +#define CAAREA2_USED_AREA2 (13U) /* 0x04_60000000 -- 0x04_7FFFFFFF */ +#define CAAREA1_USED_AREA (14U) /* 0x04_80000000 -- 0x04_FFFFFFFF */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#if (RCAR_LSI == RCAR_V4H) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define RESERVERD_AREA (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define CAAREA1_USED_AREA2 (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#else +#define RESERVERD_AREA (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define CAAREA1_USED_AREA2 (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#elif (RCAR_LSI == RCAR_V4M) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define CAAREA1_USED_AREA2 (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define RESERVERD_AREA (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#else +#define CAAREA1_USED_AREA2 (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define RESERVERD_AREA (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#endif /* RCAR_LSI == RCAR_V4H */ +#else +#define RTVRAM_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */ +#define SDRAM_BLANK_AREA (1U) /* 0x04_01C00000 -- 0x04_063FFFFF */ +#define SDRAM_PROTECT_AREA (2U) /* 0x04_06400000 -- 0x04_0643FFFF */ +#define SDRAM_PUBLIC_AREA (3U) /* 0x04_06440000 -- 0x06_FFFFFFFF */ +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +#endif /* RAM_PROTECTION_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rcar_def.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rcar_def.h new file mode 100644 index 0000000..ada224c --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rcar_def.h @@ -0,0 +1,51 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : R-Car common header + ******************************************************************************/ + +#ifndef RCAR_DEF_H_ +#define RCAR_DEF_H_ + +#include "remap_register.h" + +/* Product Register */ +#define PRR (0xFFF00044U) /* PRR register */ +#define PRR_CA_CL3_STATE_MASK (0x80000000U) /* Cortex-A Cluster 3 State */ +#define PRR_PRODUCT_MASK (0x00007F00U) /* Product mask */ +#define PRR_CUT_MASK (0x000000FFU) /* Cut Number bit mask */ +#define PRR_MAJOR_MASK (0x000000F0U) /* Major bit mask */ +#define PRR_MINOR_MASK (0x0000000FU) /* Minor bit mask */ +#define PRR_MAJOR_SHIFT (4U) /* Major bit shift */ +#define PRR_MAJOR_OFFSET (1U) + +#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */ +#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */ +#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */ + +#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */ +#define PRR_PRODUCT_11 (0x00000001U) /* ver 1.1 */ +#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */ +#endif /* RCAR_DEF_H_ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/remap.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/remap.h new file mode 100644 index 0000000..03fb5e6 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/remap.h @@ -0,0 +1,48 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : remap driver header + ******************************************************************************/ +#ifndef REMAP_H_ +#define REMAP_H_ + +#define ICUMX_CTLREG_BASE (0xFFFEE200U) +#define ICUMX_CFREMAP (ICUMX_CTLREG_BASE + 0x4CU) +#define CFREMAP_AREA_SIZE (0x02000000U) + +#include + +typedef struct{ + uint32_t base_addr; /* Base address of Region ID registers. */ + uint32_t rmp_addr; /* Stores the address converted from the Region ID base address to SICREMAP address. */ +} REMAP_TABLE; + +uint32_t remap_get_phys_addr(uint32_t remap_addr); +uint32_t get_cfremap_addr(uint32_t fetch_addr); +uint32_t remap_get_remap_addr(uint32_t phys_addr); +void remap_register(uint32_t addr, uint32_t *remap_addr); +void remap_unregister(uint32_t remap_addr); +void set_sicremap_s4v10(void); +void set_sicremap_fcpr(void); +#endif /* REMAP_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/remap_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/remap_register.h new file mode 100644 index 0000000..49c6c77 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/remap_register.h @@ -0,0 +1,281 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : remap register header + ******************************************************************************/ + +#ifndef REMAP_REGISTER_H_ +#define REMAP_REGISTER_H_ + +#include + +#define REMAP_BASE (0xFF1FC400U) + +#define ICUMX_PROT0PCMD (0xFFFEE090U) +#define ICUMX_PROT0PS (0xFFFEE094U) +#define PROTCMD_START (0xA5U) +#define PROTS0ERR (0x01U) + +#define ICU_REMAP0 (0xFC000000U) + +/* REMAP setting */ +/* Remap ID(0 -- 15) */ +#define ICU_REMAP_NUM_RTRAM (15U) /* RTRAM */ +#define ICU_REMAP_NUM_CC (14U) /* CC63S,AXMM,QoS for S4 / V4H */ +#define ICU_REMAP_NUM_FCPR (14U) /* FCPR for V4M */ +#define ICU_REMAP_NUM_PFC (13U) /* PFC,GPIO,CPGA,RESET */ +#define ICU_REMAP_NUM_ECM (12U) /* ECM,AP-System Core */ +#define ICU_REMAP_NUM_RPC (11U) /* RPC */ +#define ICU_REMAP_NUM_RTDMAC (10U) /* RT-DMAC0,PFC(MCU) */ +#define ICU_REMAP_NUM_SCIF (9U) /* SCIF */ +#define ICU_REMAP_NUM_MMC (8U) /* MMC */ +#define ICU_REMAP_NUM_HSCIF (7U) /* HSCIF */ +#define ICU_REMAP_NUM_DMAC (6U) /* SYS-DMAC0 */ +#define ICU_REMAP_NUM_RGID (5U) /* Region ID */ +#if (RCAR_LSI == RCAR_S4) +#define ICU_REMAP_NUM_MCU (4U) /* MCU */ +#endif + +/* SICREMAP2M15 */ +#define ICU_REMAP_RTSRAM (0xEB200000U) /* RT-SRAM */ +/* SICREMAP2M14 */ +#define ICU_REMAP_CC (0xE6600000U) /* CC63S,AXMM,QoS,FCPR for S4 / V4H */ +/* SICREMAP2M14 */ +#define ICU_REMAP_FCPR (0xE6600000U) /* FCPR for V4M */ +/* SICREMAP2M13 */ +#define ICU_REMAP_PFC (0xE6000000U) /* PFC,GPIO,CPGA,RESET */ +/* SICREMAP2M12 */ +#define ICU_REMAP_ECM (0xE6200000U) /* ECM,AP-System Core */ +/* SICREMAP2M11 */ +#define ICU_REMAP_RPC (0xEE200000U) /* RPC */ +/* SICREMAP2M10 */ +#define ICU_REMAP_RTDMAC (0xFFC00000U) /* RT-DMAC0,PFC(MCU) */ +/* SICREMAP2M9 */ +#if (RCAR_LSI == RCAR_S4) +#define ICU_REMAP_SCIF (0xE6C00000U) /* SCIF3 */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define ICU_REMAP_SCIF (0xE6E00000U) /* SCIF0 */ +#endif /* RCAR_LSI == RCAR_S4 */ +/* SICREMAP2M8 */ +#define ICU_REMAP_MMC (0xEE000000U) /* MMC */ +/* SICREMAP2M7 */ +#define ICU_REMAP_HSCIF (0xE6400000U) /* HSCIF */ +/* SICREMAP2M6 */ +#define ICU_REMAP_DMAC (0xE7200000U) /* SYS-DMAC0 */ +/* SICREMAP2M5 */ +#define ICU_REMAP_RGID (0xE7600000U) /* Region ID */ +#if (RCAR_LSI == RCAR_S4) +/* SICREMAP2M4 */ +#define ICU_REMAP_MCU (0xD8E00000U) /* MCU */ +#endif + +#define ICU_REMAP15_BASE (ICU_REMAP_RTRAM) /* RTRAM */ +#define ICU_REMAP14_BASE (ICU_REMAP_CC) /* CC63S,AXMM,QoS,FCPR */ +#define ICU_REMAP13_BASE (ICU_REMAP_PFC) /* PFC,GPIO,CPGA,RESET */ +#define ICU_REMAP12_BASE (ICU_REMAP_ECM) /* ECM,AP-System Core */ +#define ICU_REMAP11_BASE (ICU_REMAP_RPC) /* RPC */ +#define ICU_REMAP10_BASE (ICU_REMAP_RTDMAC) /* RT-DMAC0 */ +#define ICU_REMAP9_BASE (ICU_REMAP_SCIF) /* SCIF */ +#define ICU_REMAP8_BASE (ICU_REMAP_MMC) /* MMC */ +#define ICU_REMAP7_BASE (ICU_REMAP_HSCIF) /* HSCIF */ +#define ICU_REMAP6_BASE (ICU_REMAP_DMAC) /* SYS-DMAC0 */ +#define ICU_REMAP5_BASE (ICU_REMAP_RGID) /* Region ID */ +#if (RCAR_LSI == RCAR_S4) +#define ICU_REMAP4_BASE (ICU_REMAP_MCU) /* MCU */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define ICU_REMAP4_BASE (0x00000000U) /* Reserved */ +#endif +#define ICU_REMAP3_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP2_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP1_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP0_BASE (0x00000000U) /* Reserved */ + +/* Base address offset of each register after remap */ +/* REMAP15(0xEB200000U) */ +/* RT-SRAM */ +#define ICU_REMAP_OFFSET_RTSRAM (0x00000000U) + +/* REMAP14(0xE6600000U) */ +#define ICU_REMAP_OFFSET_CC63S (0x00000000U) +#define ICU_REMAP_OFFSET_DBSC (0x00190000U) /* (0xE6790000U) */ +#define ICU_REMAP_OFFSET_AXMM (0x00180000U) /* (0xE6780000U) */ +#if (RCAR_LSI == RCAR_S4) +#define ICU_REMAP_OFFSET_CCI (0x001a0000U) /* (0xE67A0000U) */ +#define ICU_REMAP_OFFSET_QOS (0x001e0000U) /* (0xE67E0000U) */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define ICU_REMAP_OFFSET_FCPR (0x00185700U) /* (0xE6785700U) */ + #if (RCAR_LSI == RCAR_V4M) + #define ICU_REMAP_OFFSET_I2C3 (0x000D0000U) /* (0xE66D0000U) */ + #endif /* (RCAR_LSI == RCAR_V4M) */ + #define ICU_REMAP_OFFSET_I2C5 (0x000E0000U) /* (0xE66E0000U) */ +#endif /* (RCAR_LSI == RCAR_S4) */ + +/* REMAP13(0xE6000000U) */ +/* RWDT */ +#define ICU_REMAP_OFFSET_RWDT (0x00020000U) +/* SWDT */ +#define ICU_REMAP_OFFSET_SWDT (0x00030000U) +/* PFC */ +#define ICU_REMAP_OFFSET_PFC (0x00050000U) +/* EFUSE */ +#define ICU_REMAP_OFFSET_EFUSE (0x00078800U) +/* CPGA */ +#define ICU_REMAP_OFFSET_CPGA (0x00150000U) +/* RESET */ +#define ICU_REMAP_OFFSET_RESET (0x00160000U) +/* APMU */ +#define ICU_REMAP_OFFSET_APMU (0x00170000U) +/* SYSC */ +#define ICU_REMAP_OFFSET_SYSC (0x00180000U) +/* OTP */ +#define ICU_REMAP_OFFSET_OTP (0x001BF000U) +#if (RCAR_LSI == RCAR_V4M) +#define ICU_REMAP_OFFSET_AVS (0x000A0000U) /* (0xE60A0000U) */ +#endif /* (RCAR_LSI == RCAR_V4M) */ + +/* REMAP12(0xE6200000U) */ +/* ECM */ +#define ICU_REMAP_OFFSET_MFIS (0x00060000U) +#define ICU_REMAP_OFFSET_SDRAM_ECC (0x00050000U) +#define ICU_REMAP_OFFSET_AP_CORE (0x00080000U) + +/* REMAP11(0xEE200000U) */ +/*RPC*/ +#define ICU_REMAP_OFFSET_RPC (0x00000000U) + +/* REMAP10(0xFFC00000U) */ +/* RT-DMA */ +#define ICU_REMAP_OFFSET_RTDMA0 (0x00010000U) +#define ICU_REMAP_OFFSET_RTDMACTL (0x00160000U) +#define ICU_REMAP_OFFSET_PFCMCU (0x00190000U) + +#if (RCAR_LSI == RCAR_S4) +/* REMAP9(0xE6C00000U) */ +/*SCIF*/ +#define ICU_REMAP_OFFSET_SCIF3 (0x00050000U) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +/* REMAP9(0xE6E00000U) */ +/*SCIF*/ +#define ICU_REMAP_OFFSET_SCIF0 (0x00060000U) +#endif /* RCAR_LSI == RCAR_S4 */ + +/* REMAP8(0xEE000000U) */ +/* SDHI2/MMC0 */ +#define ICU_REMAP_OFFSET_SDHI (0x00140000U) + +/* REMAP7(0xE6400000U) */ +/* HSCIF */ +#define ICU_REMAP_OFFSET_HSCIF0 (0x00140000U) + +/* REMAP6(0xE7200000U) */ +/* SYS-DMAC */ +#define ICU_REMAP_OFFSET_SYSDMAC (0x00100000U) + +/* REMAP5(0xE7600000U) */ +/* Region ID */ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define ICU_REMAP_OFFSET_ICISTP (0x00100000U) +#endif +#define ICU_REMAP_OFFSET_RGID (0x00150000U) + +#if (RCAR_LSI == RCAR_S4) +/* REMAP4(0xD8E00000U) */ +/* MCU */ +#define ICU_REMAP_OFFSET_MCU (0x00100000U) +#endif + +/* REMAP15(0xEB200000U) */ +#define BASE_RTSRAM_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTRAM) + ICU_REMAP_OFFSET_RTSRAM) +/* REMAP14(0xE6600000U) */ +#define BASE_DBSC_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_DBSC) +#define BASE_AXMM_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_AXMM) +#if (RCAR_LSI == RCAR_S4) +#define BASE_CCI_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_CCI) +#define BASE_QOS_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_QOS) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define BASE_FCPR_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_FCPR) + #if (RCAR_LSI == RCAR_V4M) + #define BASE_I2C3_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_I2C3) + #endif /* (RCAR_LSI == RCAR_V4M) */ + #define BASE_I2C5_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_I2C5) +#endif /* (RCAR_LSI == RCAR_S4) */ +/* REMAP13(0xE6000000U) */ +#define BASE_RWDT_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_RWDT) +#define BASE_SWDT_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_SWDT) +#define BASE_EFUSE_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_EFUSE) +#define BASE_PFC_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_PFC) +#define BASE_CPG_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_CPGA) +#define BASE_RESET_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_RESET) +#define BASE_APMU_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_APMU) +#define BASE_SYSC_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_SYSC) +#define BASE_OTP_MEM_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_OTP) +#if (RCAR_LSI == RCAR_V4M) +#define BASE_AVS_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_AVS) +#endif /* (RCAR_LSI == RCAR_V4M) */ +/* REMAP12(0xE6200000U) */ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define BASE_ECM_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM)) +#endif +#define BASE_MFIS_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_MFIS) +#define BASE_ECC_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_SDRAM_ECC) +#define BASE_AP_CORE_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_AP_CORE) +/* REMAP11(0xEE200000U) */ +#define BASE_RPC_ADDR (icu_remap_calc(ICU_REMAP_NUM_RPC) + ICU_REMAP_OFFSET_RPC) +/* REMAP10(0xFFC00000U) */ +#define BASE_RTDMA0_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMA0) +#define BASE_RTDMACTL_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMACTL) +#if (RCAR_LSI == RCAR_S4) +#define BASE_PFCMCU_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_PFCMCU) +#endif +#if (RCAR_LSI == RCAR_S4) +/* REMAP9(0xE6C00000U) */ +#define BASE_SCIF_ADDR (icu_remap_calc(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF3) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +/* REMAP9(0xE6E00000U) */ +#define BASE_SCIF_ADDR (icu_remap_calc(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF0) +#endif /* RCAR_LSI == RCAR_S4 */ +/* REMAP8(0xEE000000U) */ +#define BASE_MMC0_ADDR (icu_remap_calc(ICU_REMAP_NUM_MMC) + ICU_REMAP_OFFSET_SDHI) +/* REMAP7(0xE6400000U) */ +#define BASE_HSCIF_ADDR (icu_remap_calc(ICU_REMAP_NUM_HSCIF) + ICU_REMAP_OFFSET_HSCIF0) +/* REMAP6(0xE7200000U) */ +#define BASE_DMA_ADDR (icu_remap_calc(ICU_REMAP_NUM_DMAC) + ICU_REMAP_OFFSET_SYSDMAC) +/* REMAP5(0xE7600000U) */ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define BASE_ICISTP_ADDR (icu_remap_calc(ICU_REMAP_NUM_RGID) + ICU_REMAP_OFFSET_ICISTP) +#endif +#define BASE_RGID_ADDR (icu_remap_calc(ICU_REMAP_NUM_RGID) + ICU_REMAP_OFFSET_RGID) +#if (RCAR_LSI == RCAR_S4) +/* REMAP4(0xD8E00000U) */ +#define BASE_MCU_ADDR (icu_remap_calc(ICU_REMAP_NUM_MCU) + ICU_REMAP_OFFSET_MCU) +#endif + +/* Calculate the base address of each register after remapping */ +static inline uint32_t icu_remap_calc(uint32_t num) +{ + return (ICU_REMAP0 + (num * 0x00200000U)); +} +/* End of function icu_remap_calc(uint32_t num) */ + +#endif /* REMAP_REGISTER_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rom_api.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rom_api.h new file mode 100644 index 0000000..b87365e --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rom_api.h @@ -0,0 +1,73 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : boot ROM API header + ******************************************************************************/ +#ifndef ROM_API_H__ +#define ROM_API_H__ + +#include +#include + +#define SECURE_BOOT (0x0U) +#define NORMAL_BOOT (0x211883DFU) + +#define ROMAPI_OK (0x00000000U) +#define ROM_ERR_IMG_VERIFIER_NO_ENCRYPT_IMG (0xF100001DU) + +#define LCS_CM (0x00000000U) /* CM */ +#define LCS_DM (0x00000001U) /* DM */ +#define LCS_SD (0x00000003U) /* SD */ +#define LCS_SE (0x00000005U) /* SE */ +#define LCS_FA (0x00000007U) /* FA */ + +/* BOOTROM API address */ +#define ROM_GETLCS (0x01104418U) +#define ROM_SECUREBOOT_VERIFY (0x011044C8U) +#define ROM_SECUREBOOT_DECRYPT (0x011044D0U) +#define ROM_SECUREBOOT_COMPARE (0x011044D8U) + +/* For build option SW_VERSION_CHECK */ +#define OPT_VERSION_CHECK_ENABLE (1U) + +typedef uint32_t (*ROM_SECUREBOOT_VERIFY_API)(uint32_t *pKeyCert, uint32_t *pContentCert); +typedef uint32_t (*ROM_SECUREBOOT_DECRYPT_API)(uint32_t *pContentCert); +typedef uint32_t (*ROM_SECUREBOOT_COMPARE_API)(uint32_t *pContentCert, + uint32_t *hash, + uint32_t hash_size); +typedef uint32_t (*ROM_GETLCS_API)(uint32_t *pLcs, uint32_t lcs_size); + +static inline uint32_t get_load_info_id(const LOAD_INFO *li) +{ + return ((li->cnt_cert_addr - (SA9_DEST_ADDR + CONTENT_CERT_OFFSET)) / CONTENT_CERT_SIZE); +} +/* End of function get_load_info_id(LOAD_INFO *li) */ + +void rom_secureboot(LOAD_INFO* li); +uint32_t call_ROM_GetLcs(uint32_t *pLcs, uint32_t lcs_size); +void sw_version_check(const LOAD_INFO* li); +void auth_min_ver_tbl(LOAD_INFO* li); +void preload_verify_cntcert(const LOAD_INFO* li); + +#endif /* ROM_API_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rpc.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rpc.h new file mode 100644 index 0000000..321bc30 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rpc.h @@ -0,0 +1,74 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RPC driver header + ******************************************************************************/ + +#ifndef RPC_H__ +#define RPC_H__ + +#include +// #include + +/* If user customizes for another vendor's QSPI Flash, set to 1. */ +#define USER_ADDED_QSPI (1U) /* 0:Disable 1:Enable */ + +/* For return value */ +#define QSPI_CMD_INIT_SUCCESS (0x00000000U) +#define QSPI_CMD_INIT_ERROR (0xFFFFFFFFU) +/* Common command for QSPI Flash */ +#define FLASH_CMD_READ_ID (0x9FU) +/* Device ID mask for QSPI Flash */ +#define DEVICE_ID_MASK (0x00FFFFFFU) + +/* QSPI Flash device ID */ +#define DEVID_MT25QU01GB (0x0021BB20U) /* MT25QU01GB for PRK3 rev3 */ +#if USER_ADDED_QSPI == 1 +#define DEVID_XXXXXXXXX (0x003B25C2U) /* MX66U1G45G for PRK3 rev4 */ +#endif /* USER_ADDED_QSPI == 1 */ + +typedef struct { + uint32_t read_fast; + uint32_t sector_erase_4byte_addr; + uint32_t parameter_4kbyte_erase; + uint32_t pp_4byte_addr; + uint32_t read_any_register; + uint32_t read_stts_register; + uint32_t write_enable; + uint32_t read_32bit_addr; + uint32_t ddr_quad_io_read_32bit_addr; +} st_qspi_cmd_tbl_t; + +extern const st_qspi_cmd_tbl_t* gp_qspi_cmd_tbl; +extern uint8_t prk3_rev; + +void rpc_init(void); +void rpc_release(void); +void rpc_end_state_check(void); +void qspi_flash_rw_init(void); +int check_Erase_Fail(uint32_t status); + +void qspi_ddr_transfer_mode(uint32_t command); +void qspi_sdr_transfer_mode(uint32_t command); +#endif /* RPC_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rpc_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rpc_register.h new file mode 100644 index 0000000..8344849 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rpc_register.h @@ -0,0 +1,171 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RPC register header + ******************************************************************************/ + +#ifndef RPC_REGISTER_H_ +#define RPC_REGISTER_H_ + + +#include + +/* RPC base address */ +/* 0xEE200000 */ +#define RPC_BASE (BASE_RPC_ADDR) + +#define RPC_CMNCR (RPC_BASE + 0x0000U) /* Common control register */ +#define RPC_SSLDR (RPC_BASE + 0x0004U) /* R/W */ +#define RPC_DRCR (RPC_BASE + 0x000CU) /* Data read control register */ +#define RPC_DRCMR (RPC_BASE + 0x0010U) /* Data read command setting register */ +#define RPC_DREAR (RPC_BASE + 0x0014U) /* Data read extended address register */ +#define RPC_DRENR (RPC_BASE + 0x001CU) /* Data read enable setting register */ +#define RPC_SMCR (RPC_BASE + 0x0020U) /* Manual mode control register */ +#define RPC_SMCMR (RPC_BASE + 0x0024U) /* Manual mode command setting register */ +#define RPC_SMADR (RPC_BASE + 0x0028U) /* R/W */ +#define RPC_SMOPR (RPC_BASE + 0x002CU) /* R/W */ +#define RPC_SMENR (RPC_BASE + 0x0030U) /* Manual mode enable setting register */ +#define RPC_SMRDR0 (RPC_BASE + 0x0038U) /* Manual mode read data register 0 */ +#define RPC_SMRDR1 (RPC_BASE + 0x003CU) /* R */ +#define RPC_SMWDR0 (RPC_BASE + 0x0040U) /* R/W */ +#define RPC_CMNSR (RPC_BASE + 0x0048U) /* Common status register */ +#define RPC_DRDMCR (RPC_BASE + 0x0058U) /* Data read Dummy Cycle setting register */ +#define RPC_DRDRENR (RPC_BASE + 0x005CU) /* Data read DDR enable register */ +#define RPC_SMDMCR (RPC_BASE + 0x0060U) /* R/W */ +#define RPC_SMDRENR (RPC_BASE + 0x0064U) /* Manual mode DDR enable register */ +#define RPC_PHYCNT (RPC_BASE + 0x007CU) /* PHY control register */ +#define RPC_PHYOFFSET1 (RPC_BASE + 0x0080U) /* PHY Timing Offset Register 1 */ +#define RPC_OFFSET1 RPC_PHYOFFSET1 +#define RPC_PHYINT (RPC_BASE + 0x0088U) /* R/W */ +#define RPC_WRBUF (RPC_BASE + 0x8000U) /* W RPC Write buffer (Access size=4/8/16/32/64Byte) */ +#define RPC_WRBUF_PHYS (0xEE208000) + +/* for RPC register setting */ +#define RPC_PHYCNT_CAL (1U << 31U) +#define RPC_PHYCNT_STRTIM3 (1U << 27U) +#define RPC_PHYCNT_HS (1U << 18U) +#define RPC_PHYCNT_STRTIM2 (1U << 17U) +#define RPC_PHYCNT_STRTIM1 (1U << 16U) +#define RPC_PHYCNT_STRTIM0 (1U << 15U) +#define RPC_PHYCNT_WBUF2 (1U << 4U) +#define RPC_PHYCNT_WBUF (1U << 2U) +#define RPC_PHYCNT_PHYMEM_HYP (3U << 0U) +#define CMNCR_MD_MANUAL (1U << 31U) +#define CMNCR_MOIIO3_HIZ (3U << 22U) +#define CMNCR_MOIIO2_HIZ (3U << 20U) +#define CMNCR_MOIIO1_HIZ (3U << 18U) +#define CMNCR_MOIIO0_HIZ (3U << 16U) +#define CMNCR_IO0FV_HIZ (3U << 8U) +#define CMNCR_BSZ_HYP (1U << 0U) +#define CMNCR_BSZ_MASK (3U << 0U) +#define SSLDR_SLNDL (4U << 8U) +#define DRCR_SSLN (1U << 24U) +#define DRCR_RBURST_32UNITS (0x1FU << 16U) +#define DRCR_RCF (1U << 9U) +#define DRCR_RBE_BURST (1U << 8U) +#define DRCR_SSLE (1U << 0U) +#define DRCMR_S26KS512S (0xA0U << 16U) +#define DRCMR_CMD_MASK (0xFFU << 16U) +#define DRCMR_OCMD_MASK (0xFFU << 0U) +#define DREAR_EAC_26BITS (1U << 0U) +#define DREAR_EAV_MASK (0xFFU << 16U) +#define DREAR_EAC_MASK (7U << 0U) +#define DRENR_CDB_4BITS (2U << 30U) +#define DRENR_OCDB_4BITS (2U << 28U) +#define DRENR_ADB_4BITS (2U << 24U) +#define DRENR_OPDB_4BITS (2U << 20U) +#define DRENR_DRDB_4BITS (2U << 16U) +#define DRENR_DME_EN (1U << 15U) +#define DRENR_CDE_EN (1U << 14U) +#define DRENR_OCDE_EN (1U << 12U) +#define DRENR_ADE_HYPER (4U << 8U) +#define DRENR_ADE_ONE_SERIAL (0xFU << 8U) +#define DRENR_CDB_MASK (3U << 30U) +#define DRENR_OCDB_MASK (3U << 28U) +#define DRENR_ADB_MASK (3U << 24U) +#define DRENR_OPDB_MASK (3U << 20U) +#define DRENR_DRDB_MASK (3U << 16U) +#define DRENR_ADE_MASK (0xFU << 8U) +#define DRENR_OPDE_MASK (0xFU << 4U) +#define SMCR_SSLKP (1U << 8U) +#define SMCR_SPIRE (1U << 2U) +#define SMCR_SPIWE (1U << 1U) +#define SMCR_SPIE (1U << 0U) +#define SMCMR_HYP_READ (0x80U << 16U) +#define SMCMR_HYP_WRITE (0x00U << 16U) +#define SMCMR_CMD_MASK (0xFFU << 16U) +#define SMCMR_OCMD_MASK (0xFFU << 0U) +#define SMOPR_OPD3_MASK (0xFFU << 24U) +#define SMOPR_OPD2_MASK (0xFFU << 16U) +#define SMOPR_OPD1_MASK (0xFFU << 8U) +#define SMOPR_OPD0_MASK (0xFFU << 0U) +#define SMENR_CDB_4BITS (2U << 30U) +#define SMENR_OCDB_4BITS (2U << 28U) +#define SMENR_ADB_4BITS (2U << 24U) +#define SMENR_OPDB_4BITS (2U << 20U) +#define SMENR_SPIDB_4BITS (2U << 16U) +#define SMENR_DME_EN (1U << 15U) +#define SMENR_CDE_EN (1U << 14U) +#define SMENR_OCDE_EN (1U << 12U) +#define SMENR_ADE_HYPER (4U << 8U) +#define SMENR_ADE_SERIAL_31 (0xFU << 8U) +#define SMENR_ADE_SERIAL_23 (7U << 8U) +#define SMENR_SPIDE_HYP_16 (8U << 0U) +#define SMENR_SPIDE_HYP_32 (0xCU << 0U) +#define SMENR_SPIDE_HYP_64 (0xFU << 0U) +#define SMENR_SPIDE_SPI_8 (8U << 0U) +#define SMENR_SPIDE_SPI_16 (0xCU << 0U) +#define SMENR_SPIDE_SPI_32 (0xFU << 0U) +#define SMENR_CDB_MASK (3U << 30U) +#define SMENR_OCDB_MASK (3U << 28U) +#define SMENR_ADB_MASK (3U << 24U) +#define SMENR_OPDB_MASK (3U << 20U) +#define SMENR_SPIDB_MASK (3U << 16U) +#define SMENR_ADE_MASK (0xFU << 8U) +#define SMENR_OPDE_MASK (0xFU << 4U) +#define SMENR_SPIDE_MASK (0xFU << 0U) +#define CMNSR_TEND (0x00000001U) +#define DRDMCR_DMCYC_15 (0xEU << 0U) +#define DRDMCR_DMCYC_8 (7U << 0U) +#define DRDMCR_DMCYC_MASK (0x1FU << 0U) +#define DRDRENR_HYPE_HYPER (5U << 12U) +#define DRDRENR_ADDRE (1U << 8U) +#define DRDRENR_OPDRE (1U << 4U) +#define DRDRENR_DRDRE (1U << 0U) +#define DRDRENR_HYPE_MASK (7U << 12U) +#define SMDMCR_DMCYC_15 (0xEU << 0U) +#define SMDMCR_DMCYC_8 (7U << 0U) +#define SMDMCR_DMCYC_MASK (0x1FU << 0U) +#define SMDRENR_HYPE_HYPER (5U << 12U) +#define SMDRENR_ADDRE (1U << 8U) +#define SMDRENR_OPDRE (1U << 4U) +#define SMDRENR_SPIDRE (1U << 0U) +#define SMDRENR_HYPE_MASK (7U << 12U) +#define PHYOFFSET1_HYPER (0x21511144U) +#define PHYOFFSET1_DMA_QSPI (0x31511144U) +#define PHYOFFSET1_MASK (0xFFFFFFFFU) +#define PHYINT_HYPER (0x07070002U) +#define PHYINT_MASK (0xFFFFFFFFU) + +#endif /* RPC_REGISTER_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rpcqspidrv.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rpcqspidrv.h new file mode 100644 index 0000000..769fda0 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rpcqspidrv.h @@ -0,0 +1,78 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2015-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RPC driver for QSPI Flash header + ******************************************************************************/ +/****************************************************************************** + * @file rpcqspidrv.h + * - Version : 0.03 + * @brief RPC driver for QSPI Flash header + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 16.02.2022 0.01 First Release + * : 01.04.2022 0.02 Add definitions. + * : 09.11.2022 0.03 License notation change. + *****************************************************************************/ + +#ifndef RPCQSPIDRV_H__ +#define RPCQSPIDRV_H__ + +#include +#include + +#define SPI_IOADDRESS_TOP 0x08000000 /* RPC memory space 0x08000000-0x0BFFFFFF = 64MBytes */ +#define RPC_CLK_40M 0x01 +#define RPC_CLK_80M 0x02 +#define RPC_CLK_160M 0x03 + +#define DEVICE_ID_MASK (0x00FFFFFFU) + +#define RPC_WRITE_BUF_SIZE (0x100U) /* 256byte:RPC Write Buffer size */ +#define FLASH_SECTOR_SIZE (0x00010000U) /* Flash 1sector is 64KiB */ +#define FLASH_SECTOR_MASK ((~(FLASH_SECTOR_SIZE-1)) & 0xFFFFFFFFU) + +#define DRCMR_SMCMR_CMD_SHIFT (16U) + +void init_rpc_qspi_flash_4fastread_ext_mode(void); +void init_rpc_qspi_flash(void); +void sector_erase_4byte_qspi_flash(uint32_t sector_addr); +void write_data_4pp_with_buf_qspi_flash(uint32_t addr, uint32_t source_addr); +void read_any_register_qspi_flash(uint32_t addr, unsigned char *readData); /* Add24bit,Data8bit */ +void write_any_register_qspi_flash(uint32_t addr, unsigned char writeData); /* Add24bit,Data8bit */ +void set_rpc_clock_mode(uint32_t mode); +void wait_rpc_tx_end(void); + +void parameter_sector_erase_4kb_qspi_flash(uint32_t sector_addr); +void reset_rpc(void); +void set_rpc_ssl_delay(void); + +void power_on_rpc(void); +uint32_t read_wip_status_register(uint32_t *status); /* for MT25QU01GB */ +uint32_t read_qspi_flash_id(uint32_t *readData); /* for QSPIx1ch */ +uint32_t read_status_qspi_flash(uint32_t *readData); /* for QSPIx1ch */ +void write_command_qspi_flash(uint32_t command); /* for QSPIx1ch */ + +#endif /* RPCQSPIDRV_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rst_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rst_register.h new file mode 100644 index 0000000..91ba5cf --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rst_register.h @@ -0,0 +1,57 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RST register header + ******************************************************************************/ + +#ifndef RST_REGISTER_H_ +#define RST_REGISTER_H_ + +#include + +#define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */ + +#define RST_MODEMR0 (RST_BASE + 0x0000U) /* Mode pin register0 */ +#define RST_MODEMR1 (RST_BASE + 0x0004U) /* Mode pin register1 */ +#define RST_MODEMR0_MD31 (1U << 31U) +#define RST_MODEMR1_MD32 (1U << 0U) + +#define RST_MODEMR0_BOOT_DEV_MASK (0x0000001EU) +#define RST_MODEMR0_BOOT_DEV_HYPERFLASH160 (0x00000004U) +#define RST_MODEMR0_BOOT_DEV_HYPERFLASH80 (0x00000006U) +#define RST_MODEMR0_BOOT_DEV_SERIAL_FLASH40 (0x00000008U) +#define RST_MODEMR0_BOOT_DEV_SERIAL_FLASH (0x0000000CU) +#define RST_MODEMR0_BOOT_DEV_QSPI_FLASH80 (0x0000000EU) +#define RST_MODEMR0_BOOT_DEV_HYPER_XIP160 (0x00000014U) +#define RST_MODEMR0_BOOT_DEV_HYPER_XIP80 (0x00000016U) +#define RST_MODEMR0_BOOT_DEV_EMMC_50X8 (0x0000001AU) +#define RST_WDTRSTCR (RST_BASE + 0x0010U) + +/* SCIF / HSCIF clock speed */ +#define MODEMR_SCIF_DLMODE (0x00000000U) +#define MODEMR_HSCIF_DLMODE_921600 (0x00000001U) +#define MODEMR_HSCIF_DLMODE_1843200 (0x00000002U) +#define MODEMR_HSCIF_DLMODE_3000000 (0x00000003U) + +#endif /* RST_REGISTER_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rtsram_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rtsram_register.h new file mode 100644 index 0000000..5dc6825 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rtsram_register.h @@ -0,0 +1,65 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-SRAM register header + ******************************************************************************/ + +#ifndef RTSRAM_REGISTER_H__ +#define RTSRAM_REGISTER_H__ + +#include + +/* RT-SRAM register base address */ +#define RTSRAM_REG_BASE (0xFFE90000U) + +#define RTSRAM_SECDIVD (RTSRAM_REG_BASE + 0x0000U) +#define RTSRAM_SECCTRRD (RTSRAM_REG_BASE + 0x0040U) +#define RTSRAM_SECCTRWD (RTSRAM_REG_BASE + 0x0340U) + +#if (RCAR_LSI == RCAR_S4) +#define RTSRAM_SECDIVD_DIVADDR_MASK (0x000000FFU) +#else +#define RTSRAM_SECDIVD_DIVADDR_MASK (0x000FFFFFU) +#endif +#define RTSRAM_SECCTRRD_SECGRP_MASK (0x000F0000U) +#define RTSRAM_SECCTRRD_SAFGRP_MASK (0x0000FFFFU) +#define RTSRAM_SECCTRWD_SECGRP_MASK (0x000F0000U) +#define RTSRAM_SECCTRWD_SAFGRP_MASK (0x0000FFFFU) + +static inline uint32_t get_rtsram_secdivd_addr(uint32_t num) +{ + return ((RTSRAM_SECDIVD + (num * 4U))); +} + +static inline uint32_t get_rtsram_secctrrd_addr(uint32_t num) +{ + return ((RTSRAM_SECCTRRD + (num * 4U))); +} + +static inline uint32_t get_rtsram_secctrwd_addr(uint32_t num) +{ + return ((RTSRAM_SECCTRWD + (num * 4U))); +} + +#endif /* RTSRAM_REGISTER_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rtvram.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rtvram.h new file mode 100644 index 0000000..1ee2ecc --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rtvram.h @@ -0,0 +1,35 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-VRAM driver header + ******************************************************************************/ + +#ifndef RTVRAM_H_ +#define RTVRAM_H_ + +#include + +void rtvram_extendmode(void); + +#endif /* RTVRAM_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rtvram_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rtvram_register.h new file mode 100644 index 0000000..42d4a68 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/rtvram_register.h @@ -0,0 +1,70 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-VRAM register header + ******************************************************************************/ + +#ifndef RTVRAM_REGISTER_H__ +#define RTVRAM_REGISTER_H__ + +#include + +/* RT-VRAM register base address */ +#define RTVRAM_REG_BASE (0xFFEC0000U) + +#define RTVRAM_SECDIVD (RTVRAM_REG_BASE + 0x0000U) +#define RTVRAM_SECCTRRD (RTVRAM_REG_BASE + 0x0040U) +#define RTVRAM_SECCTRWD (RTVRAM_REG_BASE + 0x0340U) +#define RTVRAM_EXT_MODE (RTVRAM_REG_BASE + 0x8500U) +#define RTVRAM_VBUF_CFG (RTVRAM_REG_BASE + 0x6504U) +#define RTVRAM_CACHE_FLUSH (RTVRAM_REG_BASE + 0x4530U) +#define RTVRAM_VBUF_BADDR (RTVRAM_REG_BASE + 0xC580U) + +#define RTVRAM_SECDIVD_DIVADDR_MASK (0x000FFFFFU) +#define RTVRAM_SECCTRRD_SECGRP_MASK (0x000F0000U) +#define RTVRAM_SECCTRRD_SAFGRP_MASK (0x0000FFFFU) +#define RTVRAM_SECCTRWD_SECGRP_MASK (0x000F0000U) +#define RTVRAM_SECCTRWD_SAFGRP_MASK (0x0000FFFFU) + +static inline uint32_t get_rtvram_secdivd_addr(uint32_t num) +{ + return ((RTVRAM_SECDIVD + (num * 4U))); +} + +static inline uint32_t get_rtvram_secctrrd_addr(uint32_t num) +{ + return ((RTVRAM_SECCTRRD + (num * 4U))); +} + +static inline uint32_t get_rtvram_secctrwd_addr(uint32_t num) +{ + return ((RTVRAM_SECCTRWD + (num * 4U))); +} + +static inline uint32_t get_vbuf_baddr_addr(uint32_t num) +{ + return ((RTVRAM_VBUF_BADDR + (num * 4U))); +} + +#endif /* RTVRAM_REGISTER_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/san.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/san.h new file mode 100644 index 0000000..542e9a1 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/san.h @@ -0,0 +1,29 @@ +#ifndef SAN_DRIVER_H__ +#define SAN_DRIVER_H__ + +extern void PMIC_SM_27A(void); +extern void PMIC_SM_27B(void); +extern void PMIC_SM_27C(void); +extern void PMIC_SM_27D(void); +extern void check_SoC_Activation(void); +extern void PMIC_SM_12_wdt(void); + +extern void SM_6_3_1(void); +extern void SM_6_3_2(void); +extern void SM_5_3_6(void); +extern void SM_5_1(void); +extern void SM_6_23(void); +extern void SM_4_21(void); +extern void SM_5_1_6(void); +extern void SM_5_2_6(void); +extern void SM_6_2(void); +extern void SM_6_11(void); +extern void SM_6_14_6(void); +extern void SM_6_22(void); +extern void SM_6_24_2(void); +extern void SM_6_24_3(void); +extern void SM_6_29(void); +extern void SM_6_30(void); + +#endif /* SAN_DRIVER_H__ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scif.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scif.h new file mode 100644 index 0000000..9aae4e9 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scif.h @@ -0,0 +1,38 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : SCIF driver header + ******************************************************************************/ + +#ifndef SCIF_H_ +#define SCIF_H_ + +#include +#include + +/* Prototype */ +void scif_init(void); +void console_putc(uint8_t outchar); + +#endif /* SCIF_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scif_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scif_register.h new file mode 100644 index 0000000..f3278c6 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scif_register.h @@ -0,0 +1,47 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : SCIF register header + ******************************************************************************/ + + +#ifndef SCIF_REGISTER_H_ +#define SCIF_REGISTER_H_ + +#include + +/* SCIF base address */ +/* S4:0xE6C50000(CH3), V4H:0xE6E60000(CH0) */ +#define SCIF_BASE (BASE_SCIF_ADDR) + +#define SCIF_SCSMR (SCIF_BASE + 0x0000U) /* 16 Serial mode register */ +#define SCIF_SCBRR (SCIF_BASE + 0x0004U) /* 8 Bit rate register */ +#define SCIF_SCSCR (SCIF_BASE + 0x0008U) /* 16 Serial control register */ +#define SCIF_SCFTDR (SCIF_BASE + 0x000CU) /* 8 Transmit FIFO data register */ +#define SCIF_SCFSR (SCIF_BASE + 0x0010U) /* 16 Serial status register */ +#define SCIF_SCFCR (SCIF_BASE + 0x0018U) /* 16 FIFO control register */ +#define SCIF_SCLSR (SCIF_BASE + 0x0024U) /* 16 Line status register */ +#define SCIF_CKS (SCIF_BASE + 0x0034U) /* 16 Clock Select register */ + +#endif /* SCIF_REGISTER_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt.h new file mode 100644 index 0000000..1cd5896 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt.h @@ -0,0 +1,20 @@ +#ifndef SCMT_H_ +#define SCMT_H_ + +/* This code will also work with SUCMT, just be aware of it using RCLK instead of OSCCLK! */ + +/* Start SCMT timer. + Will set GPIO=HIGH if requested by SCMT_TOGGLE_GPIO */ +void scmt_module_start(void); + +/* Fetch SCMT timer value. + Will set GPIO=LOW again after several calls if requested by SCMT_TOGGLE_GPIO */ +uint32_t scmt_module_read(void); + +/* Wait for a specific number of ticks + - ticks: SCMT timer ticks to wait. Use SCMT_MS2TICKS)(ms) if you want to wait in milliseconds + + NOT SAFE FOR OVERLFOWS: Don't use if expected to run for over 9 hours */ +void scmt_wait_ticks(uint32_t ticks); + +#endif diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt_checkpoint.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt_checkpoint.h new file mode 100644 index 0000000..5ace3f8 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt_checkpoint.h @@ -0,0 +1,26 @@ +#ifndef SCMT_CHECKPOINT_H_ +#define SCMT_CHECKPOINT_H_ + +#include "scmt_config.h" + +#if 1 == (MEASURE_TIME) + +/* Store a checkpoint: + Fetch current counter value and store it together with: + - note: A pointer to a STATIC string. String must still be available when print_time_checkpoints() is called! + - data: Arbitrary data for later analysis (e.g. amount of data transferred) */ +void store_time_checkpoint(char * note, uint32_t data); + +/* Print checkpoints: + Outputs all measurements to serial output. */ +void print_time_checkpoints(void); + +#else +/* If measurement is disabled, still provide empty functions, so user won't need to comment out all function calls. */ + +void store_time_checkpoint(char * note, uint32_t data) {} +void print_time_checkpoints(void) {} + +#endif /* MEASURE_TIME */ + +#endif diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt_config.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt_config.h new file mode 100644 index 0000000..13c76b3 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt_config.h @@ -0,0 +1,80 @@ +#ifndef SCMT_CONFIG_H_ +#define SCMT_CONFIG_H_ + +/* Activate measurement functions. Provide dummy functions otherwise */ +#ifndef MEASURE_TIME +#define MEASURE_TIME (0) +#endif + +/* Replace printing by dummy function. This will keep timer init, but removes impact of printing on system performance */ +#ifndef MEASURE_TIME_NOPRINT +#define MEASURE_TIME_NOPRINT (0) +#endif + +/* Only first IPL should init the timer. + In case of bus access issues, you can check addresses and register values with SCMT_DEBUG. + (Dont forget to add a call to scmt_module_start then and set debug level to NOTICE(2). ) */ +#define SCMT_INIT (1) +#define SCMT_DEBUG (0) + +/* SCMT base address */ +/* V4H:0xE6040000 */ +/* V4H-ICUMX: 0xFC000000 + (13*0x00200000) + 0x00040000 = 0xFDA40000 */ +#define SCMT_BASE (0xFDA40000) + +/* For boot time measurement, you can signal the start of SCMT by GPIO pin toggle */ +/* See code for adaption of toggled pin */ +#define SCMT_TOGGLE_GPIO (1) + +/* SCMT is counting with OSCCLK = 131.57 kHz */ +/* Tick = 7.6 µs*/ +/* Full 32-bit wrap around therefore: 32643 seconds == 9.07 hours */ +/* NOTE: WRAPAROUND HANDLING NOT IMPLEMENTED! */ +#define SCMT_MS2TICKS(ms) ((ms)*131.579) + +/* If the startup time until start of SCMT is known, we can set it as start value of the timer to see absolute time right away */ +//#define SCMT_START_VALUE (0) /* No offset, add offset using your spreadsheet program */ +//#define SCMT_START_VALUE (2750) /* 20.9ms with MODEMR[1:0]: 0x0 0x801105a4 > ICUMX Boot from HyperFlash 160MHz, Unsecure Boot */ +//#define SCMT_START_VALUE (2842) /* 21.6ms with MODEMR[1:0]: 0x0 0x801105a4 > ICUMX Boot from HyperFlash 80MHz, Unsecure Boot */ +//#define SCMT_START_VALUE (2974) /* 22.6ms with MODEMR[1:0]: 0x0 0x801105a8 > ICUMX Boot from SerialFlash 133MHz QuadIO, Unsecure Boot */ +//#define SCMT_START_VALUE (3237) /* 24.6ms with MODEMR[1:0]: 0x0 0x801105a8 > ICUMX Boot from SerialFlash 80MHz QuadIO, Unsecure Boot */ +#define SCMT_START_VALUE (7184) /* 54.6ms with MODEMR[1:0]: 0x0 0x801105a8 > ICUMX Boot from SerialFlash 40MHz, Unsecure Boot */ + +/* Start a little self-test routine to check Timer-Frequency against baudrate */ +/* #define TIMER_TEST_VS_BAUD (921600) */ +#define TIMER_TEST_VS_BAUD (0) + +/* SCMT frequency slightly depends on MD-Pin settings!! See V4H UM Table 8.1.4e Note 5 */ +#define TIMER_FREQ (131578.9) + +/* Module name show in log output */ +#define MODULE "ICUMX:" + +/* Arry size for time checkpoints */ +#define TIME_CHECKPOINTS_MAX (20) + +/* Print additional infos about compiler or MODEMR register */ +#define PRINT_INFO (1) + +/* Calculates milliseconds from timer ticks. May be disabled if compiler is currently not prepared to handle floats */ +#define PRINT_FLOAT (1) + +/* PRINTING + You need to configure a way to hook into the systems print functionality +*/ + +/* Uses the ERROR macro defined by log.h - Works for ICUMX and CR Core */ +#include /* Access to ERROR() print function */ +#define PRINTFN(args...) ERROR(args) + +/* Uses facilities provided by Dummy_CA76 application */ +//#define USE_LOG_PRINTF (1) +//void log_printf(const char *fmt, ...); /* Provided by scmt_checkpoint_log.c */ +//int32_t PutChar(char outChar); /* Provided by devdrv.c */ +//#define PRINTFN(args...) {log_printf(args);} +//#define PUTFN(outChar) PutChar(outChar) + + + + +#endif diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt_register.h new file mode 100644 index 0000000..b310502 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/scmt_register.h @@ -0,0 +1,51 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : SCMT register header + ******************************************************************************/ + + +#ifndef SCMT_REGISTER_H_ +#define SCMT_REGISTER_H_ + +#include "scmt_config.h" + +/* SUCMT base address */ +/* S4-ICUMX: 0xE61D0000 */ +/* S4-G4MH: 0xD61D0000 */ + +/* SCMT base address */ +/* V4H:0xE6040000 */ +/* V4H-ICUMX: 0xFC000000 + (13*0x00200000) + 0x00040000 = 0xFDA40000 */ +/* Defined in scmt_config.h */ +/* #define SCMT_BASE (0xE6040000) */ + +/* ((( ICUMX-SUCMT: 0xFC000000 + (13*0x00200000) + 0x001D0000 = 0xFDBD0000 ))) */ + +#define SCMT_CMSSTR (SCMT_BASE + 0x0000U) /* 16 Compare match timer start register */ +#define SCMT_CMSCSR (SCMT_BASE + 0x0040U) /* 16 Compare match timer control/status register */ +#define SCMT_CMSCNT (SCMT_BASE + 0x0044U) /* 32 Compare match timer counter */ +#define SCMT_CMSCOR (SCMT_BASE + 0x0048U) /* 32 Compare match timer constant register */ + +#endif /* SCMT_REGISTER_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/spiflash2drv.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/spiflash2drv.h new file mode 100644 index 0000000..cbe813b --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/spiflash2drv.h @@ -0,0 +1,54 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2020-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Flash driver for S25FS512S header + ******************************************************************************/ +/****************************************************************************** + * @file spiflash2drv.h + * - Version : 0.04 + * @brief Flash driver for S25FS512S header + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 16.02.2022 0.01 First Release + * : 01.04.2022 0.02 Add definitions. + * : 08.04.2022 0.03 Add include guard. + * : 09.11.2022 0.04 License notation change. + *****************************************************************************/ + +#ifndef SPIFLASH2DRV_H_ +#define SPIFLASH2DRV_H_ + +void fast_rd_qspi_flash(uint32_t sourceSpiAdd, uint32_t destinationAdd, uint32_t byteCount); +void sector_erase_NNNkb_qspi_flash_s25s512s(uint32_t addr); +void parameter_sector_erase_4kb_qspi_flash_s25s512s(uint32_t addr); +void page_program_with_buf_qspi_flash_s25s512s(uint32_t addr, uint32_t source_addr); +void clear_bp_qspi_flash(void); +void save_data_with_buf_qspi_flash(uint32_t srcAdd, uint32_t svFlashAdd, uint32_t svSize); +void sector_erase_qspi_flash(uint32_t EraseStatAdd, uint32_t EraseEndAdd); +void parameter_sector_erase_qspi_flash(uint32_t EraseStatAdd, uint32_t EraseEndAdd); + +#endif /* SPIFLASH2DRV_H_ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/sysc.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/sysc.h new file mode 100644 index 0000000..4dcbd04 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/sysc.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : sysc header + ******************************************************************************/ +/****************************************************************************** + * @file sysc.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.09.2023 0.01 First Release + * : 08.01.2025 0.02 Add write protection register definition. + *****************************************************************************/ +#ifndef SYSC_H_ +#define SYSC_H_ + +#include +#include + +#define BASE_SYSC (BASE_SYSC_ADDR) /* SYSC logical address 0xFDB80000 */ + /* SYSC physical address 0xE6180000 */ +#if (RCAR_LSI == RCAR_V4M) +#define SYSC_SYSCSR (BASE_SYSC + 0x0000U) +#define SYSC_SYSCISCR0 (BASE_SYSC + 0x0810U) +#define SYSC_SYSCIER0 (BASE_SYSC + 0x0820U) +#define SYSC_SYSCIMR0 (BASE_SYSC + 0x0830U) +#define SYSC_PDRONCR31 (BASE_SYSC + 0x1004U + (31U * 64U)) /* Power Domain:C4 */ +#endif /* RCAR_LSI == RCAR_V4M */ +#define SYSC_SYSCD1WACR0 (BASE_SYSC + 0x3020U) +#define SYSC_SYSCD2WACR0 (BASE_SYSC + 0x3040U) +#define SYSC_SYSCD3WACR0 (BASE_SYSC + 0x3060U) + +#if (RCAR_LSI == RCAR_V4M) +#define SYSCIER0_PDR31 (0x80000000U) /* Bit31 */ +#define SYSCIMR0_PDR31 (0x80000000U) /* Bit31 */ +#define SYSCISCR0_PDR31 (0x80000000U) /* Bit31 */ +#define SYSCSR_BUSY1 (0x00000002U) /* Bit1 */ +#define PDRONCR31_PWRON (0x00000001U) /* Bit0 */ +#endif /* RCAR_LSI == RCAR_V4M */ + +/* Prototype */ +#if (RCAR_LSI == RCAR_V4M) +void sysc_c4_power_on(void); +#endif /* RCAR_LSI == RCAR_V4M */ +#endif /* SYSC_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/types.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/types.h new file mode 100644 index 0000000..8a34d4c --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/types.h @@ -0,0 +1,57 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Types Define header + ******************************************************************************/ + + +#ifndef TYPES_H +#define TYPES_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * File Name: types.h + * Contents : Types Define + ****************************************************************************/ +#include +#include + +#ifndef FALSE +#define FALSE (0U) +#endif + +#ifndef TRUE +#define TRUE (1U) +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/vect_set.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/vect_set.h new file mode 100644 index 0000000..b90dbc2 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/vect_set.h @@ -0,0 +1,35 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Set vector table function header + ******************************************************************************/ + +#ifndef VECT_SET_H__ +#define VECT_SET_H__ + +extern char __ghsbegin_EIINTTBL_ICU[]; + +void set_vect_table(void); + +#endif /* VECT_SET_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/wdt.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/wdt.h new file mode 100644 index 0000000..5c6b9c5 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/wdt.h @@ -0,0 +1,38 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : window watchdog timer function header + ******************************************************************************/ + +#ifndef WDT_H__ +#define WDT_H__ + +void wdt_init(void); +void wdt_restart(void); +void wdt_handler(void); + +void rwdt_init(int start); +void swdt_init(int start); + +#endif /* WDT_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/wdt_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/wdt_register.h new file mode 100644 index 0000000..519b246 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/include/wdt_register.h @@ -0,0 +1,46 @@ +/******************************************************************************* + * DESCRIPTION : WDT register header + ******************************************************************************/ + +#ifndef WDT_REGISTER_H__ +#define WDT_REGISTER_H__ + +#include + +/* RWDT base address */ +/* 0xE6020000 */ +#define RWDT_BASE (BASE_RWDT_ADDR) + +/* RWDT counter */ +#define RWDT_RWTCNT (RWDT_BASE + 0x0000U) +#define RWTCNT_UPPER (0x5A5A0000) + +/* RWDT control/status A */ +#define RWDT_RWTCSRA (RWDT_BASE + 0x0004U) + +#define RWTCSRA_UPPER (0xA5A5A500) +#define RWTCSRA_TME ((1U) << 7) +#define RWTCSRA_WRFLG ((1U) << 5) +#define RWTCSRA_WOVF ((1U) << 4) +#define RWTCSRA_WOVF_E ((1U) << 3) +#define RWTCSRA_CKS0 ((0x7U)) + +/* RWDT control/status B */ +#define RWDT_RWTCSRB (RWDT_BASE + 0x0008U) + +#define RWTCSRB_CKS1 ((0x3FU)) + +/* SWDT base address */ +/* 0xE6030000 */ +#define SWDT_BASE (BASE_SWDT_ADDR) + +/* SWDT counter */ +#define SWDT_SWTCNT (SWDT_BASE + 0x0000U) + +/* SWDT control/status A */ +#define SWDT_SWTCSRA (SWDT_BASE + 0x0004U) + +/* SWDT control/status B */ +#define SWDT_SWTCSRB (SWDT_BASE + 0x0008U) + +#endif /* WDT_REGISTER_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/intc/intc.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/intc/intc.c new file mode 100644 index 0000000..aca2576 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/intc/intc.c @@ -0,0 +1,155 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Interrupt controler driver + ******************************************************************************/ +/****************************************************************************** + * @file intc.c + * - Version : 0.02 + * @brief Interrupt controler driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 06.01.2022 0.01 First Release + * : 05,04.2023 0.02 Remove string.h + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +#define INTC_EI_MAX (64U) +#define INTC_EI_ID_MASK (0xFFU) + +#define ICUMX_IC_MK_BIT (0x0080U) /* Interrupt request mask */ +#define ICUMX_IC_TB_BIT (0x0040U) /* Vector table selection system */ +#define ICUMX_IC_PRIORITY_MASK (0x0007U) + +#define INT_FLG_ENABLE (0x10U) +#define INT_FLG_DISABLE (0x00U) + +#define EXCEPTION_SOURCE_CODE_BIT (0x1000U) + + +typedef struct { + INT_HANDLER handler; + uint32_t arg; + uint32_t flg; +} INTC_HDR_TBL; + +static INTC_HDR_TBL s_intc_tbl[INTC_EI_MAX]; + +void intc_set_interrupt(uint32_t int_no, uint32_t level, INT_HANDLER cb) +{ + uint16_t reg; + __DI(); + + /* check Exception Source code */ + if (INTC_EI_MAX <= int_no) + { + ERROR("Undefined Exception Source code error.(0x%x)\n", int_no); + panic; + } + + /* set interrupt handler */ + s_intc_tbl[int_no].handler = cb; + s_intc_tbl[int_no].flg = INT_FLG_ENABLE; + + /* the interrupt enable */ + reg = mem_read16(get_icumx_ic_addr(int_no)); + reg &= (~(ICUMX_IC_MK_BIT) | ICUMX_IC_PRIORITY_MASK); + reg |= (ICUMX_IC_TB_BIT | (level & ICUMX_IC_PRIORITY_MASK)); + mem_write16(get_icumx_ic_addr(int_no), reg); + + __EI(); +} +/* End of function intc_set_interrupt(uint32_t int_no, uint32_t level, INT_HANDLER cb) */ + + +void intc_disable_interrupt(uint32_t int_no) +{ + uint16_t reg; + __DI(); + + /* check Exception Source code */ + if (INTC_EI_MAX <= int_no) + { + ERROR("Undefined Exception Source code error.(0x%x)\n", int_no); + panic; + } + + /* check interrupt enable flag */ + if (INT_FLG_DISABLE == (s_intc_tbl[int_no].flg & INT_FLG_ENABLE)) + { + ERROR("Execption disabled.(0x%x)\n", int_no); + panic; + } + + /* the interrupt disable */ + s_intc_tbl[int_no].flg &= ~INT_FLG_ENABLE; + reg = mem_read16(get_icumx_ic_addr(int_no)); + reg &= ~(ICUMX_IC_TB_BIT); + reg |= ICUMX_IC_MK_BIT; + mem_write16(get_icumx_ic_addr(int_no), reg); + + __EI(); +} +/* End of function intc_disable_interrupt(uint32_t int_no) */ + +#pragma ghs interrupt(nonreentrant) +void intc_handler(void) +{ + uint32_t reg; + uint32_t int_no; + reg = __STSR(EIIC); + + /* check Exception Source code */ + if ((reg & EXCEPTION_SOURCE_CODE_BIT) == 0U) + { + ERROR("Undefined Exception Source code error.(0x%x)\n", reg); + panic; + } + int_no = reg & INTC_EI_ID_MASK; + if (INTC_EI_MAX <= int_no) + { + ERROR("Undefined Exception Source code error.(0x%x)\n", int_no); + panic; + } + + /* check interrupt enable flag */ + if (INT_FLG_DISABLE == (s_intc_tbl[int_no].flg & INT_FLG_ENABLE)) + { + ERROR("Execption disabled.(0x%x)\n", int_no); + panic; + } + + /* execute interrupt handler */ + s_intc_tbl[int_no].handler(int_no, s_intc_tbl[int_no].arg); +} +/* End of function intc_handler(void) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/intc/vect_set.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/intc/vect_set.c new file mode 100644 index 0000000..cb7b7ec --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/intc/vect_set.c @@ -0,0 +1,50 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Set vector table function + ******************************************************************************/ +/****************************************************************************** + * @file vect_set.c + * - Version : 0.01 + * @brief Set vector table function. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 06.01.2022 0.01 First Release + *****************************************************************************/ +#include +#include +#include "intc.h" +#include "vect_set.h" +#include "cpu.h" +#include "rst_register.h" +#include "mem_io.h" + +void set_vect_table(void) +{ + /* set interrupt table */ + __LDSR(INTBP, (uint32_t)&__ghsbegin_EIINTTBL_ICU[0]); +} +/* End of function set_vect_table(void) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/intc/vecttbl.S b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/intc/vecttbl.S new file mode 100644 index 0000000..4128399 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/intc/vecttbl.S @@ -0,0 +1,181 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader vector table + ******************************************************************************/ + + .global code_start + .global intc_handler + + .section ".reset" + .align 512 + .align 16 +_start: + jr32 code_start //RESET + .align 16 + jr32 _Dummy //SYSERR + .align 16 + jr32 _Dummy //HVTRAP + .align 16 + jr32 _Dummy //FETRAP + .align 16 + jr32 _Dummy //TRAP0 + .align 16 + jr32 _Dummy //TRAP1 + .align 16 + jr32 _Dummy //RIE + .align 16 + jr32 _Dummy //FPP/FPI + .align 16 + jr32 _Dummy //UCPOP + .align 16 + jr32 _Dummy //MIP/MDP + .align 16 + jr32 _Dummy //PIE + .align 16 + jr32 _Dummy //Debug + .align 16 + jr32 _Dummy //MAE + .align 16 + jr32 _Dummy //(R.F.U) + .align 16 + jr32 _Dummy //FENMI + .align 16 + jr32 _Dummy //FEINT + .align 16 + jr32 _Dummy //INTn(priority0) + .align 16 + jr32 _Dummy //INTn(priority1) + .align 16 + jr32 _Dummy //INTn(priority2) + .align 16 + jr32 _Dummy //INTn(priority3) + .align 16 + jr32 _Dummy //INTn(priority4) + .align 16 + jr32 _Dummy //INTn(priority5) + .align 16 + jr32 _Dummy //INTn(priority6) + .align 16 + jr32 _Dummy //INTn(priority7) + .align 16 + jr32 _Dummy //INTn(priority8) + .align 16 + jr32 _Dummy //INTn(priority9) + .align 16 + jr32 _Dummy //INTn(priority10) + .align 16 + jr32 _Dummy //INTn(priority11) + .align 16 + jr32 _Dummy //INTn(priority12) + .align 16 + jr32 _Dummy //INTn(priority13) + .align 16 + jr32 _Dummy //INTn(priority14) + .align 16 + jr32 _Dummy //INTn(priority15) + + .section ".EIINTTBL_ICU", const + .align 512 +.offset 0x0000 + .word _intc_handler /* 0 : INTICUECCLRAM */ +.offset 0x0004 + .word _intc_handler /* 1 : INTICUECCCRAM */ +.offset 0x0008 + .word _intc_handler /* 2 : INTICUEDCAXI */ +.offset 0x000C + .word _intc_handler /* 3 : INTICUECCAXIAB */ +.offset 0x0010 + .word _intc_handler /* 4 : INTICUECCPKRAM */ +.offset 0x0014 + .word _intc_handler /* 5 : INTPES */ +.offset 0x0018 + .word _intc_handler /* 6 : INTPE */ +.offset 0x001C + .word _intc_handler /* 7 : INTICUAESD0RD */ +.offset 0x0020 + .word _intc_handler /* 8 : Reserved */ +.offset 0x0024 + .word _intc_handler /* 9 : INTICUTRNGE0 */ +.offset 0x0028 + .word _intc_handler /* 10 : INTICUOSTM0 */ +.offset 0x002C + .word _intc_handler /* 11 : INTICUOSTM1 */ +.offset 0x0030 + .word _intc_handler /* 12 : INTICUWDTA0 */ +.offset 0x0034 + .word _intc_handler /* 13 : INTICUPKCCA0 */ +.offset 0x0038 + .word _intc_handler /* 14 : INTICUDMACA0 */ +.offset 0x003C + .word _intc_handler /* 15 : INTICUDMACA0AXI */ +.offset 0x0040 + .word _intc_handler /* 16 : Reserved */ +.offset 0x0044 + .word _intc_handler /* 17 : INTICUSHAA0IREQ */ +.offset 0x0048 + .word _intc_handler /* 18 : INTICUSHAA0OEND */ +.offset 0x004C + .word _intc_handler /* 19 : INTICUCRCDRQA */ +.offset 0x0050 + .word _intc_handler /* 20 : INTICUCRRDRQA */ +.offset 0x0054 + .word _intc_handler /* 21 : INTICUCRCDRQ1 */ +.offset 0x0058 + .word _intc_handler /* 22 : INTICUCRRDRQ */ +.offset 0x005C + .word _intc_handler /* 23 : INTICUCRCDRQ2 */ +.offset 0x0060 + .word _intc_handler /* 24 : Reserved */ +.offset 0x0064 + .word _intc_handler /* 25 : INTICUERRCFDA */ +.offset 0x0068 + .word _intc_handler /* 26 : INTICUERRDFDA */ +.offset 0x006C + .word _intc_handler /* 27 : Reserved */ +.offset 0x0070 + .word _intc_handler /* 28 : Reserved */ +.offset 0x0074 + .word _intc_handler /* 29 : INTSAFRTRAMERR */ +.offset 0x0078 + .word _intc_handler /* 30 : INTSECRTRAMERR */ +.offset 0x007C + .word _intc_handler /* 31 : INTEDCRTRAMERR */ +.offset 0x0080 + .word _intc_handler /* 32 : INTECCRTRAMCMPE */ +.offset 0x0084 + .word _intc_handler /* 33 : INTECCMRTRAMERR */ +.offset 0x0088 + .word _intc_handler /* 34 : INTECCSRTRAMERR */ +.offset 0x008C + .word _intc_handler /* 35 : INTEDCMSECROMER */ +.offset 0x0090 + .word _intc_handler /* 36 : INTEDCSSECROMER */ +.offset 0x0094 + .word _intc_handler /* 37 : INTSCEGCALEND */ + + .section ".text" + .align 2 +_Dummy: + br _Dummy diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/avs/avs.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/avs/avs.c new file mode 100644 index 0000000..69bc727 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/avs/avs.c @@ -0,0 +1,115 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : AVS driver + ******************************************************************************/ +/****************************************************************************** + * @file avs.c + * - Version : 0.01 + * @brief AVS driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 16.11.2023 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#define AVS_BASE (BASE_AVS_ADDR) /* Physical address:0xE60A0000, Logical address:0xFDAA0000 */ +#define AVS_ADVADJP (AVS_BASE + 0x0080U) +#define ADVADJP_VOLCOND_MASK (0x000001FFU) + +#define VOLCOND_NUM (5U) /* Array number */ +#define VOLCOND_FLAG_4 (4U) +#define VOLCOND_FLAG_2 (2U) + +/* I2C Slave Address */ +#define SLAVE_RW_ADDR (0x000000C8U) + +/* PMIC register Address */ +#define BUCK1_DVS0CFG1 (0x00000072U) +#define BUCK1_DVS0CFG0 (0x00000073U) +#define DVS_CFG_NUM (2U) /* Array number */ + +/* PMIC register setting value */ +#define BUCK1_DVS0CFG1_VOLCOND2 (0x0000009FU) /* Setting value for 0.7575[V] */ +#define BUCK1_DVS0CFG0_VOLCOND2 (0x000000C0U) /* Setting value for 0.7575[V] */ +#define BUCK1_DVS0CFG1_VOLCOND4 (0x0000009AU) /* Setting value for 0.7325[V] */ +#define BUCK1_DVS0CFG0_VOLCOND4 (0x00000080U) /* Setting value for 0.7325[V] */ + +void avs_low_power_mode_setting(void) +{ + uint32_t volcond; + + /* Initialize I2C ch3. */ + i2c3_init(); + + /* Confirm VOLCOND in ADVADJP register. */ + volcond = mem_read32(AVS_ADVADJP); + volcond &= ADVADJP_VOLCOND_MASK; + + NOTICE("Low Power Mode setting(AVS) VOLCOND=%d\n", volcond); + switch (volcond) + { + case VOLCOND_FLAG_2: + { + /* In case of VOLCOND=2, set supply voltage to 0.7575[V]. */ + i2c3_write(SLAVE_RW_ADDR, BUCK1_DVS0CFG1, BUCK1_DVS0CFG1_VOLCOND2); + i2c3_write(SLAVE_RW_ADDR, BUCK1_DVS0CFG0, BUCK1_DVS0CFG0_VOLCOND2); + INFO("VOLCOND=0x%x SET Slave=0x%x Register=0x%x Value=0x%x\n", + volcond, SLAVE_RW_ADDR, BUCK1_DVS0CFG1, BUCK1_DVS0CFG1_VOLCOND2); + INFO("VOLCOND=0x%x SET Slave=0x%x Register=0x%x Value=0x%x\n", + volcond, SLAVE_RW_ADDR, BUCK1_DVS0CFG0, BUCK1_DVS0CFG0_VOLCOND2); + break; + } + case VOLCOND_FLAG_4: + { + /* In case of VOLCOND=4, set supply voltage to 0.7325[V]. */ + i2c3_write(SLAVE_RW_ADDR, BUCK1_DVS0CFG1, BUCK1_DVS0CFG1_VOLCOND4); + i2c3_write(SLAVE_RW_ADDR, BUCK1_DVS0CFG0, BUCK1_DVS0CFG0_VOLCOND4); + INFO("VOLCOND=0x%x SET Slave=0x%x Register=0x%x Value=0x%x\n", + volcond, SLAVE_RW_ADDR, BUCK1_DVS0CFG1, BUCK1_DVS0CFG1_VOLCOND4); + INFO("VOLCOND=0x%x SET Slave=0x%x Register=0x%x Value=0x%x\n", + volcond, SLAVE_RW_ADDR, BUCK1_DVS0CFG0, BUCK1_DVS0CFG0_VOLCOND4); + break; + } + default: + { + /* Other than VOLCOND = 2 or 4, nothing to do. */ + break; + } + } + + /* Release I2C ch3 */ + i2c3_release(); +} +/* End of function avs_low_power_mode_setting(void) */ + + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/cpg/cpg.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/cpg/cpg.c new file mode 100644 index 0000000..0825aba --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/cpg/cpg.c @@ -0,0 +1,83 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : CPG initialize + ******************************************************************************/ + /****************************************************************************** + * @file cpg.c + * - Version : 0.03 + * @brief Initial setting process of CPG. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Move cpg_reg_write function to cpg.h. + * : 27.12.2024 0.03 Add set_srcr function. + *****************************************************************************/ + +#include +#include +#if (RCAR_LSI == RCAR_V4H) +#include +#endif /* RCAR_LSI == RCAR_V4H */ + +/* CPG write protect value */ +#define CPGWPCR_PASSWORD (0xA5A50000U) +#define CPGWPCR_WPE ((uint32_t)1U << 0U) +#define CPGWPCR_WPE_VALID (0U) + +#if (RCAR_LSI == RCAR_V4H) +static void set_srcr(void); +#endif /* RCAR_LSI == RCAR_V4H */ + +void cpg_init(void) +{ + /* Release CPG write protect */ + if((mem_read32(CPG_CPGWPCR) & CPGWPCR_WPE) != CPGWPCR_WPE_VALID) + { + mem_write32(CPG_CPGWPR, ~(uint32_t)(CPGWPCR_PASSWORD)); + mem_write32(CPG_CPGWPCR, CPGWPCR_PASSWORD); + + /* bit in WPE = 0? */ + while ((mem_read32(CPG_CPGWPCR) & CPGWPCR_WPE) != CPGWPCR_WPE_VALID) + { + ; + } + } + +#if (RCAR_LSI == RCAR_V4H) + set_srcr(); +#endif /* RCAR_LSI == RCAR_V4H */ +} +/* End of function cpg_init(void) */ + +#if (RCAR_LSI == RCAR_V4H) +static void set_srcr(void) +{ + mem_write32(CPG_SRCR28, CPGSRCR28_VAL); + mem_write32(CPG_SRCR29, CPGSRCR29_VAL); +} +/* End of function set_srcr(void) */ +#endif /* RCAR_LSI == RCAR_V4H */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/boot_init_dram.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/boot_init_dram.h new file mode 100644 index 0000000..1ab608d --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/boot_init_dram.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation All rights reserved. + */ + +#ifndef __BOOT_INIT_DRAM_ +#define __BOOT_INIT_DRAM_ + +extern int32_t InitDram(void); + +#define INITDRAM_OK (0) +#define INITDRAM_NG (0xffffffff) +#define INITDRAM_ERR_I (0xffffffff) +#define INITDRAM_ERR_O (0xfffffffe) +#define INITDRAM_ERR_T (0xfffffff0) + +#endif /* __BOOT_INIT_DRAM_*/ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/ddr.mk b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/ddr.mk new file mode 100644 index 0000000..b31c2ea --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/ddr.mk @@ -0,0 +1,6 @@ +# +# Copyright (c) 2015-2022, Renesas Electronics Corporation All rights reserved. +# + +OBJ_FILE += ip/ddr/s4/lpddr4x/boot_init_dram.o +OBJ_FILE += ip/ddr/dram_sub_func.o \ No newline at end of file diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.c new file mode 100644 index 0000000..8003434 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2015-2018, Renesas Electronics Corporation All rights reserved. + */ + +#include +#include "dram_sub_func.h" + +void dram_get_boot_status(uint32_t *status) +{ + *status = DRAM_BOOT_STATUS_COLD; +} + +int32_t dram_update_boot_status(uint32_t status) +{ + int32_t ret = 0; + return ret; +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.h new file mode 100644 index 0000000..0afbb35 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation All rights reserved. + */ + +#ifndef DRAM_SUB_FUNC_H_ +#define DRAM_SUB_FUNC_H_ + +#define DRAM_BOOT_STATUS_COLD (0U) +#define DRAM_BOOT_STATUS_WARM (1U) + +#define DRAM_UPDATE_STATUS_ERR (-1) + +void dram_get_boot_status(uint32_t *status); +int32_t dram_update_boot_status(uint32_t status); + +#endif /* DRAM_SUB_FUNC_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram.c new file mode 100644 index 0000000..f4137dc --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram.c @@ -0,0 +1,2243 @@ +/******************************************************************************* + * Copyright (c) 2021-2023 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#else +#include +#include +#endif +#include "ddr_regdef.h" +#include "init_dram_tbl_s4.h" +#include "boot_init_dram_regdef.h" +#include "boot_init_dram.h" +#include "dram_sub_func.h" + +#define DDR_BACKUPMODE +#define FATAL_MSG(x) NOTICE(x) + +/******************************************************************************* + * variables + ******************************************************************************/ +/* +static uint32_t Prr_Product; +static uint32_t Prr_Cut; +*/ +static uint32_t _cnf_BOARDTYPE; +static uint32_t brd_clk; +static uint32_t brd_clkdiv; +static uint32_t brd_clkdiva; +static uint32_t ddr_mbps; +static uint32_t ddr_mbpsdiv; +static uint32_t bus_mbps, bus_mbpsdiv; +static uint32_t ddr_tccd; +static const struct _boardcnf *Boardcnf; +static uint32_t ddr_phyvalid; +static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; +static uint32_t ch_have_this_cs[CS_CNT]; +static uint32_t max_density; +static uint32_t ddr_mul; +static uint32_t ddr_mul_nf; +static uint32_t ddr_mul_low; +static uint32_t ddrtbl_load_num; + +#define DDR_PHY_REGSET_MAX 143 +#define DDR_PI_REGSET_MAX 223 +static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX]; +#ifdef DDR_BACKUPMODE +static uint32_t ddrBackup; +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static uint32_t vch_nxt(uint32_t pos); +static void cpg_write_32(uint32_t a, uint32_t v); +static void pll3_control(uint32_t high); + +static void send_dbcmd(uint32_t cmd); +static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd); +static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata); +static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata); +static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, uint32_t val); +static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef); +static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val); +static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); +static void ddr_setval_ach(uint32_t regdef, uint32_t val); +static void ddr_setval_ach_as(uint32_t regdef, uint32_t val); +static uint32_t ddr_getval(uint32_t ch, uint32_t regdef); +static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size); +static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val); +static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef); +static uint16_t _f_scale(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint16_t cyc); +static void _f_scale_js2(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint16_t *f_js2); +static void ddrtbl_load(void); +static void ddrtbl_load_pi(void); +static void ddr_config(void); +static void dbsc_regset(void); +static void dbsc_regset_post(void); +static uint32_t dfi_init_start(void); +static void ddr_register_set(void); +static void wait_dbpdstat1(uint32_t status); +static uint32_t wait_freqchgreq(uint32_t req_assert); +static void set_freqchgack(uint32_t ack_assert); +static void set_dfifrequency(uint32_t freq); +static uint32_t pll3_freq(uint32_t fsel); +static uint32_t pi_training_go(void); +static void manual_frequency_change(void); +static uint32_t manual_training_wrlvl(void); +static uint32_t manual_training_rdgtlvl(void); +static uint32_t manual_training_rdlvl(void); +static uint32_t manual_training_wdqlvl(void); +static uint32_t ca_vref_training(void); +static uint32_t init_ddr(void); +static uint32_t boardcnf_get_brd_type(void); +static void dbsc_write_32(uintptr_t addr, uint32_t data); + +/******************************************************************************* + * load board configuration + ******************************************************************************/ +#include "boot_init_dram_config.c" + +/******************************************************************************* + * CA Vref Training setting + ******************************************************************************/ +#ifndef DDR_CAVREF_VAL +#define DDR_CAVREF_VAL 0x11 +#endif + +#ifndef DDR_CAVREF_DELTA +#define DDR_CAVREF_DELTA 3 +#endif + +/******************************************************************************* + * macro for channel selection loop + ******************************************************************************/ +static uint32_t vch_nxt(uint32_t pos) +{ + uint32_t posn; + + for (posn = pos; posn < DRAM_CH_CNT; posn++) { + if (ddr_phyvalid & (1U << posn)) { + break; + } + } + return posn; +} + +#define foreach_vch(ch) \ +for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1U)) + +#define foreach_ech(ch) \ +for (ch = 0U; ch < DRAM_CH_CNT; ch++) + +/******************************************************************************* + * Printing functions + ******************************************************************************/ +#define MSG_LF(...) + +/******************************************************************************* + * clock settings, reset control + ******************************************************************************/ +static void cpg_write_32(uint32_t a, uint32_t v) +{ + mmio_write_32(CPG_CPGWPR, ~v); + mmio_write_32(a, v); +} + +static void pll3_control(uint32_t high) +{ + uint32_t dataDIV, dataMUL; + uint32_t ssmode, dataNF; + + if (high) { + /* High frequency mode */ + dataMUL = ddr_mul - 1U; + dataDIV = 0x02U; + dataNF = ddr_mul_nf; + } else { + /* Low frequency mode (25MHz) */ + dataMUL = ddr_mul_low - 1U; /* PLL3VCO = 1600MHz */ + dataDIV = 0x0CU; /* div = 64 */ + dataNF = 0x00U; + } + + ssmode = 0x04U; + dataMUL = (dataMUL << 20) | (ssmode << 16); + dataNF = (dataNF << 20); + + /* PLL3 multiplie set */ + if (((mmio_read_32(CPG_PLL3CR0) & 0x3FFFFF7FU) != dataMUL) || (mmio_read_32(CPG_PLL3CR1) != dataNF) ) { + cpg_write_32(CPG_PLL3CR0, dataMUL); + cpg_write_32(CPG_PLL3CR1, dataNF); + cpg_write_32(CPG_PLL3CR0, mmio_read_32(CPG_PLL3CR0) | CPG_PLL3CR_KICK_BIT); + while ((mmio_read_32(CPG_PLLECR) & CPG_PLLECR_PLL3ST_BIT) != CPG_PLLECR_PLL3ST_BIT); + } + /* PLL3 DIV set(Target value) */ + while ((mmio_read_32(CPG_FRQCRD) & CPG_FRQCRD_KICK_BIT)); + cpg_write_32(CPG_FRQCRD, dataDIV | (mmio_read_32(CPG_FRQCRD) & 0xFFFFFF80U)); + cpg_write_32(CPG_FRQCRD, mmio_read_32(CPG_FRQCRD) | CPG_FRQCRD_KICK_BIT); + while ((mmio_read_32(CPG_FRQCRD) & CPG_FRQCRD_KICK_BIT)); + +} + +/******************************************************************************* + * DDR memory register access + ******************************************************************************/ +static void send_dbcmd(uint32_t cmd) +{ + /* dummy read */ + mmio_read_32(DBSC_DBCMD); + while ((mmio_read_32(DBSC_DBWAIT)) & 0x01U); + + dbsc_write_32((DBSC_DBCMD), cmd); +} + +/******************************************************************************* + * DDRPHY register access (raw) + ******************************************************************************/ +static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd) +{ + uint32_t val; + + val = 0U; + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00004000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x0000C000U)); + + val = mmio_read_32(DBSC_DBPDRGA(phyno)); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd); + + val = mmio_read_32(DBSC_DBPDRGD(phyno)); + (void)val; + + return val; +} + +static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) +{ + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd); + + mmio_write_32(DBSC_DBPDRGD(phyno), regdata); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x00008000U)); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); +} + +static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) +{ + uint32_t ch; + + foreach_vch(ch) { + reg_ddrphy_write(ch, regadd, regdata); + } +} + +/******************************************************************************* + * DDRPHY register access (field modify) + ******************************************************************************/ +static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + + adr = DDR_REGDEF_ADR(_regdef) + 0x100U * slice; + len = DDR_REGDEF_LEN(_regdef); + lsb = DDR_REGDEF_LSB(_regdef); + if (len == 0x20U) { + msk = 0xffffffffU; + } else { + msk = ((1U << len) - 1U) << lsb; + } + + tmp = reg_ddrphy_read(ch, adr); + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + reg_ddrphy_write(ch, adr, tmp); +} + +static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + + adr = DDR_REGDEF_ADR(_regdef) + 0x100U * slice; + len = DDR_REGDEF_LEN(_regdef); + lsb = DDR_REGDEF_LSB(_regdef); + if (len == 0x20U) { + msk = 0xffffffffU; + } else { + msk = ((1U << len) - 1U); + } + + tmp = reg_ddrphy_read(ch, adr); + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) +{ + ddr_setval_s(ch, 0U, regdef, val); +} + +static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val) +{ + uint32_t ch; + + foreach_vch(ch) { + ddr_setval_s(ch, slice, regdef, val); + } +} + +static void ddr_setval_ach(uint32_t regdef, uint32_t val) +{ + ddr_setval_ach_s(0U, regdef, val); +} + +static void ddr_setval_ach_as(uint32_t regdef, uint32_t val) +{ + uint32_t slice; + + for (slice = 0U; slice < SLICE_CNT; slice++) { + ddr_setval_ach_s(slice, regdef, val); + } +} + +static uint32_t ddr_getval(uint32_t ch, uint32_t regdef) +{ + return ddr_getval_s(ch, 0U, regdef); +} + +/******************************************************************************* + * DBSC register access + ******************************************************************************/ +static void dbsc_write_32(uintptr_t addr, uint32_t data) +{ + *((volatile uint32_t*)addr) = data; +} + +/******************************************************************************* + * handling functions for setteing ddrphy value table + ******************************************************************************/ +static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size) +{ + uint32_t i; + + for (i = 0U; i < size; i++) { + to[i] = from[i]; + } +} + +static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000000ffU; + + adr = DDR_REGDEF_ADR(_regdef); + len = DDR_REGDEF_LEN(_regdef); + lsb = DDR_REGDEF_LSB(_regdef); + if (len == 0x20U) { + msk = 0xffffffffU; + } else { + msk = ((1U << len) - 1U) << lsb; + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + tbl[adr & adrmsk] = tmp; +} + +static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000000ffU; + + adr = DDR_REGDEF_ADR(_regdef); + len = DDR_REGDEF_LEN(_regdef); + lsb = DDR_REGDEF_LSB(_regdef); + if (len == 0x20U) { + msk = 0xffffffffU; + } else { + msk = ((1U << len) - 1U); + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +/******************************************************************************* + * functions and parameters for timing setting + ******************************************************************************/ +struct _jedec_spec1 { + uint16_t fx3; + uint8_t RLwoDBI; + uint8_t RLwDBI; + uint8_t WL; + uint8_t nWR; + uint8_t nRTP; + uint8_t ODTLon; + uint8_t MR1; + uint8_t MR2; + uint16_t tRRD; + uint16_t tFAW; +}; + +#define JS1_USABLEC_SPEC_LO 2 +#define JS1_USABLEC_SPEC_HI 7 +#define JS1_FREQ_TBL_NUM 8 +#define JS1_MR1(f) (0x04 | ((f) << 4)) +#define JS1_MR2(f) (0x00 | ((f) << 3) | (f)) + +const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { + { 800, 6, 6, 4, 6 , 8, 0, JS1_MR1(0), JS1_MR2(0)|0x40,10000, 40000 }, /* 533.333Mbps*/ + { 1600, 10, 12, 8, 10 , 8, 0, JS1_MR1(1), JS1_MR2(1)|0x40,10000, 40000 }, /* 1066.666Mbps*/ + { 2400, 14, 16, 12, 16 , 8, 6, JS1_MR1(2), JS1_MR2(2)|0x40,10000, 40000 }, /* 1600.000Mbps*/ + { 3200, 20, 22, 10, 20 , 8, 4, JS1_MR1(3), JS1_MR2(3), 10000, 40000 }, /* 2133.333Mbps*/ + { 4000, 24, 28, 12, 24 ,10, 4, JS1_MR1(4), JS1_MR2(4), 10000, 40000 }, /* 2666.666Mbps*/ + { 4800, 28, 32, 14, 30 ,12, 6, JS1_MR1(5), JS1_MR2(5), 10000, 40000 }, /* 3200.000Mbps*/ + { 5600, 32, 36, 16, 34 ,14, 6, JS1_MR1(6), JS1_MR2(6), 10000, 40000 }, /* 3733.333Mbps*/ + { 6400, 36, 40, 18, 40 ,16, 8, JS1_MR1(7), JS1_MR2(7), 7500, 30000 } /* 4266.666Mbps*/ +}; + +struct _jedec_spec2 { + uint16_t ps; + uint16_t cyc; +}; + +#define JS2_tSR 0 +#define JS2_tXP 1 +#define JS2_tRTP 2 +#define JS2_tRCD 3 +#define JS2_tRPpb 4 +#define JS2_tRPab 5 +#define JS2_tRAS 6 +#define JS2_tWR 7 +#define JS2_tWTR 8 +#define JS2_tRRD 9 +#define JS2_tPPD 10 +#define JS2_tFAW 11 +#define JS2_tDQSCK 12 +#define JS2_tCKEHCMD 13 +#define JS2_tCKELCMD 14 +#define JS2_tCKELPD 15 +#define JS2_tMRR 16 +#define JS2_tMRW 17 +#define JS2_tMRD 18 +#define JS2_tZQCALns 19 +#define JS2_tZQLAT 20 +#define JS2_tIEdly 21 +#define JS2_tODTon_min 22 +#define JS2_TBLCNT 23 + +#define JS2_tRCpb (JS2_TBLCNT) +#define JS2_tRCab (JS2_TBLCNT + 1) +#define JS2_tRFCab (JS2_TBLCNT + 2) +#define JS2_CNT (JS2_TBLCNT + 3) + +#ifndef JS2_DERATE +#define JS2_DERATE 0 +#endif +const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { + { +/*tSR */ { 15000, 3 }, +/*tXP */ { 7500, 3 }, +/*tRTP */ { 7500, 8 }, +/*tRCD */ { 18000, 4 }, +/*tRPpb */ { 18000, 3 }, +/*tRPab */ { 21000, 3 }, +/*tRAS */ { 42000, 3 }, +/*tWR */ { 18000, 4 }, +/*tWTR */ { 10000, 8 }, +/*tRRD */ { 0, 0 }, +/*tPPD */ { 0, 0 }, +/*tFAW */ { 0, 0 }, +/*tDQSCK*/ { 3500, 0 }, +/*tCKEHCMD*/ { 7500, 3 }, +/*tCKELCMD*/ { 7500, 3 }, +/*tCKELPD*/ { 7500, 3 }, +/*tMRR*/ { 0, 8 }, +/*tMRW*/ { 10000, 10 }, +/*tMRD*/ { 14000, 10 }, +/*tZQCALns*/ { 1000, 0 }, +/*tZQLAT*/ { 30000, 10 }, +/*tIEdly*/ { 6000, 0 }, +/*tODTon_min*/ { 1500, 0 } + },{ +/*tSR */ { 15000, 3 }, +/*tXP */ { 7500, 3 }, +/*tRTP */ { 7500, 8 }, +/*tRCD */ { 19875, 4 }, +/*tRPpb */ { 19875, 3 }, +/*tRPab */ { 22875, 3 }, +/*tRAS */ { 43875, 3 }, +/*tWR */ { 18000, 4 }, +/*tWTR */ { 10000, 8 }, +/*tRRD */ { 1875, 0 }, +/*tPPD */ { 0, 0 }, +/*tFAW */ { 0, 0 }, +/*tDQSCK*/ { 3600, 0 }, +/*tCKEHCMD*/ { 7500, 3 }, +/*tCKELCMD*/ { 7500, 3 }, +/*tCKELPD*/ { 7500, 3 }, +/*tMRR*/ { 0, 8 }, +/*tMRW*/ { 10000, 10 }, +/*tMRD*/ { 14000, 10 }, +/*tZQCALns*/ { 1000, 0 }, +/*tZQLAT*/ { 30000, 10 }, +/*tIEdly*/ { 6000, 0 }, +/*tODTon_min*/ { 1500, 0 } + } +}; + +const uint16_t jedec_spec2_tRFC_ab[5] = { +/* 4Gb, 6Gb, 8Gb,12Gb,16Gb (24Gb/32Gb non) */ + 130, 180, 180, 280, 280 +}; + +static uint32_t js1_ind; +static uint16_t js2[JS2_CNT]; +static uint8_t RL; +static uint8_t WL; + +static uint16_t _f_scale(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint16_t cyc) +{ + uint32_t tmp; + uint32_t div; + + tmp = (((uint32_t)(ps) + 9U) / 10U) * f_ddr_mbps; + div = tmp / (200000U * f_ddr_mbpsdiv); + if (tmp != (div * 200000U * f_ddr_mbpsdiv)) { + div = div + 1U; + } + + if (div > cyc) { + cyc = (uint16_t)div; + } + + return cyc; +} + +static void _f_scale_js2(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint16_t *f_js2) +{ + uint32_t i; + + for (i = 0U; i < JS2_TBLCNT; i++) { + f_js2[i] = _f_scale(f_ddr_mbps, f_ddr_mbpsdiv, + (uint32_t)jedec_spec2[JS2_DERATE][i].ps, + jedec_spec2[JS2_DERATE][i].cyc); + } + + f_js2[JS2_tRRD] = _f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(js1[js1_ind].tRRD + jedec_spec2[JS2_DERATE][JS2_tPPD].ps), 4U); + f_js2[JS2_tFAW] = _f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(js1[js1_ind].tFAW + jedec_spec2[JS2_DERATE][JS2_tFAW].ps), 0U); + f_js2[JS2_tZQCALns] = _f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tZQCALns].ps) * 1000U, 0U); + f_js2[JS2_tRCpb] = f_js2[JS2_tRAS] + f_js2[JS2_tRPpb]; + f_js2[JS2_tRCab] = f_js2[JS2_tRAS] + f_js2[JS2_tRPab]; +} + +static const uint32_t _reg_PI_MR1_DATA_Fx_CSx[3][CS_CNT] = { + { + _reg_PI_MR1_DATA_F0_0, + _reg_PI_MR1_DATA_F0_1 + }, + { + _reg_PI_MR1_DATA_F1_0, + _reg_PI_MR1_DATA_F1_1 + }, + { + _reg_PI_MR1_DATA_F2_0, + _reg_PI_MR1_DATA_F2_1 + } +}; + +static const uint32_t _reg_PI_MR2_DATA_Fx_CSx[3][CS_CNT] = { + { + _reg_PI_MR2_DATA_F0_0, + _reg_PI_MR2_DATA_F0_1 + }, + { + _reg_PI_MR2_DATA_F1_0, + _reg_PI_MR2_DATA_F1_1 + }, + { + _reg_PI_MR2_DATA_F2_0, + _reg_PI_MR2_DATA_F2_1 + } +}; + +static const uint32_t _reg_PI_MR3_DATA_Fx_CSx[3][CS_CNT] = { + { + _reg_PI_MR3_DATA_F0_0, + _reg_PI_MR3_DATA_F0_1 + }, + { + _reg_PI_MR3_DATA_F1_0, + _reg_PI_MR3_DATA_F1_1 + }, + { + _reg_PI_MR3_DATA_F2_0, + _reg_PI_MR3_DATA_F2_1 + } +}; + +static const uint32_t _reg_PI_MR11_DATA_Fx_CSx[3][CS_CNT] = { + { + _reg_PI_MR11_DATA_F0_0, + _reg_PI_MR11_DATA_F0_1 + }, + { + _reg_PI_MR11_DATA_F1_0, + _reg_PI_MR11_DATA_F1_1 + }, + { + _reg_PI_MR11_DATA_F2_0, + _reg_PI_MR11_DATA_F2_1 + } +}; + +static const uint32_t _reg_PI_MR12_DATA_Fx_CSx[3][CS_CNT] = { + { + _reg_PI_MR12_DATA_F0_0, + _reg_PI_MR12_DATA_F0_1 + }, + { + _reg_PI_MR12_DATA_F1_0, + _reg_PI_MR12_DATA_F1_1 + }, + { + _reg_PI_MR12_DATA_F2_0, + _reg_PI_MR12_DATA_F2_1 + } +}; + +static const uint32_t _reg_PI_MR14_DATA_Fx_CSx[3][CS_CNT] = { + { + _reg_PI_MR14_DATA_F0_0, + _reg_PI_MR14_DATA_F0_1 + }, + { + _reg_PI_MR14_DATA_F1_0, + _reg_PI_MR14_DATA_F1_1 + }, + { + _reg_PI_MR14_DATA_F2_0, + _reg_PI_MR14_DATA_F2_1 + } +}; + +/******************************************************************************* + * load table data into DDR registers + ******************************************************************************/ +static void ddrtbl_load(void) +{ + uint32_t i; + uint32_t slice; + uint32_t cs; + uint32_t adr; + uint32_t dataL; + uint32_t tmp[2]; + + const uint32_t DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_S4; + const uint32_t DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_S4; + const uint32_t DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_S4; + const uint32_t DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_S4; + + const uint32_t DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_S4; + + const uint32_t DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_S4; + const uint32_t DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_S4; + const uint32_t DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_S4; + + /*********************************************************************** + * TIMING REGISTERS + ***********************************************************************/ + /* search jedec_spec1 index */ + for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1U; i++) { + if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) { + break; + } + } + if (JS1_USABLEC_SPEC_HI < i) { + js1_ind = JS1_USABLEC_SPEC_HI; + } else { + js1_ind = i; + } + + RL = js1[js1_ind].RLwDBI; + + WL = js1[js1_ind].WL; + + /* calculate jedec_spec2 */ + _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); + + /*********************************************************************** + * PREPARE TBL + ***********************************************************************/ + _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, + DDR_PHY_SLICE_REGSET_S4, DDR_PHY_SLICE_REGSET_NUM_S4); + _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, + DDR_PHY_ADR_V_REGSET_S4, DDR_PHY_ADR_V_REGSET_NUM_S4); + _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, + DDR_PHY_ADR_G_REGSET_S4, DDR_PHY_ADR_G_REGSET_NUM_S4); + _tblcopy(_cnf_DDR_PI_REGSET, + DDR_PI_REGSET_S4, DDR_PI_REGSET_NUM_S4); + + /*********************************************************************** + * Adjust PI paramters + ***********************************************************************/ + if (js2[JS2_tIEdly] > RL) { + js2[JS2_tIEdly] = RL; + } + + if (js2[JS2_tIEdly] >= 0x0fU) { + dataL = 0x0fU; + } else { + dataL = js2[JS2_tIEdly]; + } + + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataL); + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY, (dataL - 2U)); + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_OE_DLY, dataL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataL - 1U); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, WL - 4U); + + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, WL); + + tmp[0] = js1[js1_ind].MR1; + tmp[1] = js1[js1_ind].MR2; + + for (cs = 0U; cs < CS_CNT; cs++) { + for (i = 1U; i < 3U; i++) { + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR1_DATA_Fx_CSx[i][cs], tmp[0]); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR2_DATA_Fx_CSx[i][cs], tmp[1]); + } + } + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) { + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_SET_DFI_INPUT_RST_PAD, 0x01U); + } +#endif /* DDR_BACKUPMODE */ + + /*********************************************************************** + * Read Vref (SoC side) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->vref_r); + if (dataL) { + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_VREF_INITIAL_START_POINT, dataL & 0x00ffU); + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_VREF_INITIAL_STOP_POINT, (dataL & 0xff00U) >> 8); + } + + /*********************************************************************** + * Write Vref (MR14) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->vref_w); + if (dataL) { + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WDQLVL_VREF_DELTA_F0, (((dataL & 0xff00U) >> 8) - (dataL & 0x00ffU) + 1) / 2); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WDQLVL_VREF_DELTA_F1, (((dataL & 0xff00U) >> 8) - (dataL & 0x00ffU) + 1) / 2); + for (cs = 0U; cs < CS_CNT; cs++) { + for (i = 0U; i < 3U; i++) { + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR14_DATA_Fx_CSx[i][cs], (((dataL & 0xff00U) >> 8) + (dataL & 0x00ffU)) / 2); + } + } + } + + /*********************************************************************** + * CA Vref (MR12) Default configuration + ***********************************************************************/ + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_1, DDR_CAVREF_VAL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_0, DDR_CAVREF_VAL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_1, DDR_CAVREF_VAL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_0, DDR_CAVREF_VAL); + + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_CALVL_VREF_INITIAL_START_POINT_F0, DDR_CAVREF_VAL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F0, DDR_CAVREF_VAL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_CALVL_VREF_INITIAL_START_POINT_F1, DDR_CAVREF_VAL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F1, DDR_CAVREF_VAL); + + /*********************************************************************** + * Low Freq setting + ***********************************************************************/ + if (3 * ddr_mbps < 4 * 1600 * ddr_mbpsdiv) { + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL, 0x1342); + } + + if (ddr_mbps < 4 * 640 * ddr_mbpsdiv) { + /* PCLK(10-100MHz) */ + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_PAD_DSLICE_IO_CFG, 0x05); + ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_PAD_ADR_IO_CFG_0, 0x05); + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_ACS_IO_CFG, 0x05); + + /* CAL_CLK(10-20MHz) */ + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DATA_DC_CAL_CLK_SEL, 0x04); + ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_ADR_DC_CAL_CLK_SEL_0, 0x04); + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_CLK_DC_CAL_CLK_SEL, 0x04); + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_CAL_CLK_SELECT_0, 0x05); + } + + /*********************************************************************** + * FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) + ***********************************************************************/ + ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x01U); + ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01U); + + /*********************************************************************** + * SET DATA SLICE TABLE + ***********************************************************************/ + for (slice = 0U; slice < SLICE_CNT; slice++) { + adr = DDR_PHY_SLICE_REGSET_OFS + DDR_PHY_SLICE_REGSET_SIZE * slice; + for (i = 0U; i < DDR_PHY_SLICE_REGSET_NUM; i++) { + reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_SLICE_REGSET[i]); + } + } + + /*********************************************************************** + * SET ADR SLICE TABLE + ***********************************************************************/ + adr = DDR_PHY_ADR_V_REGSET_OFS; + for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { + reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); + } + + /*********************************************************************** + * SET ADRCTRL SLICE TABLE + ***********************************************************************/ + adr = DDR_PHY_ADR_G_REGSET_OFS; + for (i = 0U; i < DDR_PHY_ADR_G_REGSET_NUM; i++) { + reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]); + } + + /*********************************************************************** + * SET PI REGISTERS + ***********************************************************************/ + adr = DDR_PI_REGSET_OFS; + ddrtbl_load_num = 83U; + for (i = 0U; i < ddrtbl_load_num; i++) { + reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]); + } +} + +static void ddrtbl_load_pi(void) +{ + uint32_t ch, dataL; + + const uint32_t DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_S4; + const uint32_t DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_S4; + + /*********************************************************************** + * SET PI REGISTERS + ***********************************************************************/ + dataL = ddrtbl_load_num; + while (dataL < DDR_PI_REGSET_NUM) { + reg_ddrphy_write_a(DDR_PI_REGSET_OFS + dataL, _cnf_DDR_PI_REGSET[dataL]); + ++dataL; + } + + foreach_vch(ch) { + /* --- DATA_BYTE_SWAP --- */ + dataL = (uint32_t)(Boardcnf->ch[ch].dqs_swap); + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01U); + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0, dataL & 0x0fU); + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1, (dataL >> 4) & 0x0fU); + + if (!(ch_have_this_cs[1] & (1U << ch))) { + ddr_setval(ch, _reg_PI_CS_MAP, 0x01U); + } + } +} + +/******************************************************************************* + * CONFIGURE DDR REGISTERS + ******************************************************************************/ +static void ddr_config(void) +{ + uint32_t ch, slice; + uint32_t dataL; + uint8_t high_byte[SLICE_CNT]; + + const uint32_t _par_CALVL_DEVICE_MAP = 1U; + + foreach_vch(ch) { + /*********************************************************************** + * BOARD SETTINGS (DQ, DM, VREF_DRIVING) + ***********************************************************************/ + for (slice = 0U; slice < SLICE_CNT; slice++) { + high_byte[slice] = ((uint32_t)(Boardcnf->ch[ch].dqs_swap) >> (4U * slice)) % 2; + ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0, Boardcnf->ch[ch].dq_swap[slice]); + ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1, (uint32_t)(Boardcnf->ch[ch].dm_swap[slice])); + if (high_byte[slice]) { + /* HIGHER 16 BYTE */ + ddr_setval_s(ch, slice, _reg_PHY_CALVL_VREF_DRIVING_SLICE, 0x00U); + } else { + /* LOWER 16 BYTE */ + ddr_setval_s(ch, slice, _reg_PHY_CALVL_VREF_DRIVING_SLICE, 0x01U); + } + } + + /*********************************************************************** + * BOARD SETTINGS (CA, ADDR_SEL) + ***********************************************************************/ + dataL = (0x00ffffffU & (uint32_t)(Boardcnf->ch[ch].ca_swap)); + + /* --- ADR_ADDR_SEL --- */ + ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL_0, dataL); + + /* --- ADR_CALVL_SWIZZLE --- */ + if (high_byte[1]) { + dataL |= 0x00888888U; + } + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000U); + ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); + + /*********************************************************************** + * mask CS_MAP if RANK1 is not found + ***********************************************************************/ + if (!(ch_have_this_cs[1] & (1U << ch))) { + ddr_setval(ch, _reg_PHY_ADR_CALVL_RANK_CTRL_0, 0x00U); + for (slice = 0U; slice < SLICE_CNT; slice++) { + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00U); + } + } + } +} + +/******************************************************************************* + * DBSC register setting functions + ******************************************************************************/ +static void dbsc_regset_pre(void) +{ + uint32_t ch, cs; + + /*********************************************************************** + * PRIMARY SETTINGS + ***********************************************************************/ + /* LPDDR4, BL=16, DFI interface */ + dbsc_write_32(DBSC_DBKIND, 0x0000000aU); + dbsc_write_32(DBSC_DBKINDA, 0x0000000aU); + dbsc_write_32(DBSC_DBBL, 0x00000002U); + dbsc_write_32(DBSC_DBBLA, 0x00000002U); + dbsc_write_32(DBSC_DBPHYCONF0, 0x00000001U); + + dbsc_write_32(DBSC_DBSYSCONF0, 0x00000001U); + + /* FREQRATIO=2 */ + dbsc_write_32(DBSC_DBSYSCONF1, 0x00000002U); + dbsc_write_32(DBSC_DBSYSCONF1A, 0x00000002U); + + dbsc_write_32(DBSC_DBSYSCONF2, 0x00000001U); + dbsc_write_32(DBSC_DBSYSCONF2A, 0x00000061U); + + foreach_ech(ch) { + for (cs = 0U; cs < CS_CNT; cs++) { + if (ddr_density[ch][cs] == 0xffU) { + mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00U); + mmio_write_32(DBSC_DBMEMCONFA(ch, cs), 0x00U); + } else { + mmio_write_32(DBSC_DBMEMCONF(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs])); + mmio_write_32(DBSC_DBMEMCONFA(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs])); + } + } + } +} + +static void dbsc_regset(void) +{ + uint32_t dataL; + uint32_t tmp[4]; + + /* RFC */ + js2[JS2_tRFCab] = _f_scale(ddr_mbps, ddr_mbpsdiv, + 1UL * jedec_spec2_tRFC_ab[max_density] * 1000, 0); + + /* DBTR0.CL : RL */ + dbsc_write_32(DBSC_DBTR(0), RL); + + /* DBTR1.CWL : WL */ + dbsc_write_32(DBSC_DBTR(1), WL); + + /* DBTR2.AL : 0 */ + dbsc_write_32(DBSC_DBTR(2), 0U); + + /* DBTR3.TRCD: tRCD */ + dbsc_write_32(DBSC_DBTR(3), js2[JS2_tRCD]); + + /* DBTR4.TRPA,TRP: tRPab,tRPpb */ + dbsc_write_32(DBSC_DBTR(4), (js2[JS2_tRPab] << 16) | js2[JS2_tRPpb]); + + /* DBTR5.TRC : use tRCpb */ + dbsc_write_32(DBSC_DBTR(5), js2[JS2_tRCpb]); + + /* DBTR6.TRAS : tRAS */ + dbsc_write_32(DBSC_DBTR(6), js2[JS2_tRAS]); + + /* DBTR7.TRRD : tRRD */ + dbsc_write_32(DBSC_DBTR(7), (js2[JS2_tRRD] << 16) | js2[JS2_tRRD]); + + /* DBTR8.TFAW : tFAW */ + dbsc_write_32(DBSC_DBTR(8), js2[JS2_tFAW]); + + /* DBTR9.TRDPR : nRTP */ + dbsc_write_32(DBSC_DBTR(9), js1[js1_ind].nRTP); + + /* DBTR10.TWR : nWR */ + dbsc_write_32(DBSC_DBTR(10), js1[js1_ind].nWR); + + /* DBTR11.TRDWR : RL + BL / 2 + Rounddown(tRPST) + PHY_ODTLoff - ODTLon + tDQSCK - tODTon,min + PCB delay (out+in) + tPHY_ODToff */ + dbsc_write_32(DBSC_DBTR(11), + RL + (16 / 2) + 1 + 2 - js1[js1_ind].ODTLon + js2[JS2_tDQSCK] - js2[JS2_tODTon_min] + _f_scale(ddr_mbps, ddr_mbpsdiv, (1500 + 500 + 800), 0)); + + /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */ + dataL = WL + 1 + (16 / 2) + js2[JS2_tWTR]; + dbsc_write_32(DBSC_DBTR(12), (dataL << 16) | dataL); + + /* DBTR13.TRFCAB : tRFCab */ + dbsc_write_32(DBSC_DBTR(13), + (js2[JS2_tRFCab])); + + /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */ + dbsc_write_32(DBSC_DBTR(14), + ((js2[JS2_tCKEHCMD] + 3U) << 16) | (js2[JS2_tCKEHCMD] + 3U)); + + /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */ + dbsc_write_32(DBSC_DBTR(15), + (js2[JS2_tSR] << 16) | (js2[JS2_tCKELPD])); + + /* DBTR16 */ + tmp[0] = WL; + tmp[1] = WL - 4U; + tmp[2] = RL + 33U + 2U; + tmp[3] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1U; + dbsc_write_32(DBSC_DBTR(16), + (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR24 */ + /* WRCSLAT */ + tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1) - 5U; + /* WRCSGAP = 6 + 1 */ + tmp[1] = 7U; + /* RDCSLAT */ + tmp[2] = RL - 6U; + /* RDCSGAP */ + tmp[3] = 4U + 2U; + dbsc_write_32(DBSC_DBTR(24), + (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0)*/ + dbsc_write_32(DBSC_DBTR(17), (js2[JS2_tMRR] << 24) | (js2[JS2_tMRD] << 16)); + + /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */ + dbsc_write_32(DBSC_DBTR(18), 0U); + + /* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */ + dbsc_write_32(DBSC_DBTR(19), 0U); + + /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */ + dataL = js2[JS2_tRFCab] + js2[JS2_tCKEHCMD] + 3U; + dbsc_write_32(DBSC_DBTR(20), (dataL << 16) | dataL); + + /* DBTR21.TCCD */ + dbsc_write_32(DBSC_DBTR(21), (ddr_tccd << 16) | ddr_tccd); + + /* DBTR22.ZQLAT : */ + dbsc_write_32(DBSC_DBTR(22), (js2[JS2_tZQCALns] << 16) | js2[JS2_tZQLAT]); + + /* DBTR23.RRSPC */ + dbsc_write_32(DBSC_DBTR(23), 0x00000003U); + + /* DBTR25 : do not use in LPDDR4 */ + dbsc_write_32(DBSC_DBTR(25), 0U); + + /* DBRNK : */ + /* DBSC_DBRNK2 rkrr */ + dbsc_write_32(DBSC_DBRNK(2), 0x000000CC); + + /* DBSC_DBRNK3 rkrw */ + dbsc_write_32(DBSC_DBRNK(3), 0x00000066); + + /* DBSC_DBRNK4 rkwr */ + dbsc_write_32(DBSC_DBRNK(4), 0x00000066); + + /* DBSC_DBRNK5 rkww */ + dbsc_write_32(DBSC_DBRNK(5), 0x000000CC); + + /*********************************************************************** + * timing registers for Scheduler + ***********************************************************************/ + /* SCFCTST0 */ + /* SCFCTST0 ACT-ACT*/ + tmp[3] = 1UL * js2[JS2_tRCpb] * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + /* SCFCTST0 RDA-ACT*/ + tmp[2] = 1UL * ((16U / 2U) + js2[JS2_tRTP] - 8U + js2[JS2_tRPpb]) * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + /* SCFCTST0 WRA-ACT*/ + tmp[1] = 1UL * (WL + 1U + (16U / 2U) + js1[js1_ind].nWR) * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + /* SCFCTST0 PRE-ACT*/ + tmp[0] = 1UL * js2[JS2_tRPpb] * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + dbsc_write_32(DBSC_SCFCTST0, (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* SCFCTST1 */ + /* SCFCTST1 RD-WR*/ + tmp[3] = 1UL * (mmio_read_32(DBSC_DBTR(11)) & 0xffU) * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + /* SCFCTST1 WR-RD*/ + tmp[2] = 1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xffU) * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + /* SCFCTST1 ACT-RD/WR*/ + tmp[1] = 1UL * js2[JS2_tRCD] * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + /* SCFCTST1 ASYNCOFS*/ + tmp[0] = 12U; + dbsc_write_32(DBSC_SCFCTST1, (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBSCHRW1 */ + /* DBSCHRW1 SCTRFCAB*/ + tmp[0] = 1UL * js2[JS2_tRFCab] * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + dataL =(((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000U) >> 16) + + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFFU) + + (0x28U * 2U)) * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv + 7U; + if (tmp[0] < dataL) { + tmp[0] = dataL; + } + dbsc_write_32(DBSC_DBSCHRW1, tmp[0] + + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) + * bus_mbps * ddr_mbpsdiv + (ddr_mbps - 1U)) / ddr_mbps / bus_mbpsdiv); + + /*********************************************************************** + * QOS and CAM + ***********************************************************************/ + dbsc_write_32(DBSC_DBBCAMDIS, 0x00000001U); +} + +static void dbsc_regset_post(void) +{ + uint32_t dataL; + +#if RCAR_REWT_TRAINING != 0 + uint32_t ctrl_clk; + uint32_t clk_count; + uint32_t phymster_req_interval; +#endif /* RCAR_REWT_TRAINING */ + + /*set DBI */ + dbsc_write_32(DBSC_DBDBICNT, 0x00000003U); + + /*set REFCYCLE */ + dataL = DBSC_REFINT * ddr_mbps / 2000U / ddr_mbpsdiv; + dbsc_write_32(DBSC_DBRFCNF1, 0x00080000U | (dataL & 0x0000ffffU)); + dbsc_write_32(DBSC_DBRFCNF2, 0x00010000U | DBSC_REFINTS); + +#if RCAR_REWT_TRAINING != 0 + /* Periodic-WriteDQ Training seeting */ + dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000U); + + ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x03U); + ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00U); + ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01U); + + /* DFI_PHYMSTR_ACK , WTmode = b'01 */ + dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011U); +#endif /* RCAR_REWT_TRAINING */ + + /* PCLK */ + if (ddr_mbps < 4 * 640 * ddr_mbpsdiv) { + ddr_setval_ach(_reg_PHY_PAD_CAL_IO_CFG_0, 0x05U); + } else { + ddr_setval_ach(_reg_PHY_PAD_CAL_IO_CFG_0, 0x06U); + } + + /* periodic SoC zqcal enable */ + ddr_setval_ach(_reg_PHY_CAL_MODE_0, ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_CAL_MODE_0) | 0x02U); + + /* periodic dram zqcal enable */ + dbsc_write_32(DBSC_DBCALCNF, 0x01000010U); + + /* periodic phy ctrl update enable */ + dbsc_write_32(DBSC_DBDFICUPDCNF, 0x504C0001U); + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) { + /* SRX */ + send_dbcmd(0x0A840001U); + } +#endif /* DDR_BACKUPMODE */ + /* set Auto Refresh */ + dbsc_write_32(DBSC_DBRFEN, 0x00000001U); + +#if RCAR_REWT_TRAINING != 0 + /* Periodic WriteDQ Training */ + clk_count = 1024U - ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_LONG_COUNT_MASK) * 32U; + ctrl_clk = ddr_mbps / ddr_mbpsdiv / 4U; + dataL = clk_count * (1000U * 1000U * 1000U / (1000U * ctrl_clk)); + + phymster_req_interval = REWT_TRAINING_INTERVAL - 3000; + + ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, phymster_req_interval * 1000U * 100U / (dataL / 10U) ); +#endif /* RCAR_REWT_TRAINING */ + + /* dram access enable */ + dbsc_write_32(DBSC_DBACEN, 0x00000001U); + + /* MR13: vrcg(normal mode) */ + send_dbcmd(0x0e840dc0U); + + MSG_LF("dbsc_regset_post(done)\n"); +} + +/******************************************************************************* + * DFI_INIT_START + ******************************************************************************/ +static uint32_t dfi_init_start(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + const uint32_t RETRY_MAX = 0x10000U; + + /*********************************************************************** + * init start + ***********************************************************************/ + pll3_control(0U); /* Low frequency mode */ + /* dbdficnt0: + * dfi_dram_clk_disable=1 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start =0 + */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10U); + } + + /* dbdficnt0: + * dfi_dram_clk_disable=1 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start =1 + */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11U); + } + + wait_dbpdstat1(0x03U); + + /*********************************************************************** + * dll rst + ***********************************************************************/ + /* dll_rst negate */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01U); + } + + /*********************************************************************** + * wait init_complete + ***********************************************************************/ + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) { + foreach_vch(ch) { + dataL = mmio_read_32(DBSC_DBDFISTAT(ch)); + if (dataL & 0x00000001U) { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) { + break; + } + } + + /*********************************************************************** + * all ch ok? + ***********************************************************************/ + if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) { + return (phytrainingok); + } + /* dbdficnt0: + * dfi_dram_clk_disable=0 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start =0 + */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010U); + } + + return (phytrainingok); +} + +/******************************************************************************* + * DDR mode register setting + ******************************************************************************/ +static void ddr_register_set(void) +{ + int32_t fspwp; + uint32_t tmp; + + for (fspwp = 0U; fspwp < 2U; fspwp++) { + /* MR13: fspop,fspwp */ + send_dbcmd(0x0e840d08U | ((2U - fspwp) << 6)); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR1_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840100U | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR2_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840200U | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840300U | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840b00U | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840c00U | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR14_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840e00U | tmp); + + /* MR22 */ + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR22_DATA_F0_0); + send_dbcmd(0x0e801600U | tmp); + + if (ch_have_this_cs[1]) { + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR22_DATA_F0_1); + send_dbcmd(0x0e811600U | tmp); + } + + /* ZQCAL start */ + send_dbcmd(0x0d84004fU); + + /* ZQLAT */ + send_dbcmd(0x0d840051U); + } + + /* MR13, fspwp */ + send_dbcmd(0x0e840d08U); +} + +/******************************************************************************* + * Training handshake functions + ******************************************************************************/ +static void wait_dbpdstat1(uint32_t status) +{ + uint32_t i, ch, dataL; + + for (i = 0U; i < 2U; i++) { + do { + dataL = status; + foreach_vch(ch) { + dataL &= mmio_read_32(DBSC_DBPDSTAT1(ch)); + } + } while (dataL != status); + } +} + +static uint32_t wait_freqchgreq(uint32_t req_assert) +{ + uint32_t dataL; + uint32_t count; + uint32_t ch; + + count = 0xFFFFFFU; + + if (req_assert) { + do { + dataL = 1U; + foreach_vch(ch) { + dataL &= mmio_read_32(DBSC_DBPDSTAT(ch)); + } + count = count - 1U; + } while (((dataL & 0x01U) != 0x01U) & (count != 0U)); + } else { + do { + dataL = 0U; + foreach_vch(ch) { + dataL |= mmio_read_32(DBSC_DBPDSTAT(ch)); + } + count = count - 1U; + } while (((dataL & 0x01U) != 0x00U) & (count != 0U)); + } + + return (count == 0U); +} + +static void set_freqchgack(uint32_t ackassert) +{ + uint32_t ch; + uint32_t dataL; + + if (ackassert) { + dataL = 0x0000CF01U; + } else { + dataL = 0x00000000U; + } + + foreach_vch(ch) { + mmio_write_32(DBSC_DBPDCNT2(ch), dataL); + } +} + +static void set_dfifrequency(uint32_t freq) +{ + uint32_t ch; + + foreach_vch(ch) { + mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24, (freq << 24)); + } +} + +static uint32_t pll3_freq(uint32_t fsel) +{ + uint32_t timeout; + + wait_freqchgreq(1); + + if (fsel == 0U) { + pll3_control(0); /* Low frequency mode */ + } else { + pll3_control(1); /* High frequency mode */ + } + + set_dfifrequency(fsel); + set_freqchgack(1); + + timeout = wait_freqchgreq(0); + set_freqchgack(0); + + wait_dbpdstat1(0x03U); + + if (timeout) { + FATAL_MSG("BL2: Time out[2]\n"); + return (1); + } + return (0); +} + +/******************************************************************************* + * training by pi + ******************************************************************************/ +static uint32_t pi_training_go(void) +{ + uint32_t flag; + uint32_t dataL; + uint32_t retry; + const uint32_t RETRY_MAX = 4096 * 16; + uint32_t ch; + + uint32_t mst_ch; + uint32_t cur_frq; + uint32_t complete; + uint32_t frqchg_req; + + /*********************************************************************** + * pi_start + ***********************************************************************/ + foreach_vch(ch) { + while((ddr_getval(ch, _reg_PI_INT_STATUS)) != 0U); + } + + foreach_vch(ch) { + mmio_write_32(DBSC_DBPDRGA(ch), DDR_REGDEF_ADR(_reg_PI_START)); + mmio_write_32(DBSC_DBPDRGD(ch), 0x00000B01U); + } + + foreach_vch(ch) { + while((mmio_read_32(DBSC_DBPDRGA(ch)) & 0x00008000U) == 0U); + mmio_write_32(DBSC_DBPDRGA(ch), mmio_read_32(DBSC_DBPDRGA(ch))); + } + + /* set dfi_phymstr_ack = 1 */ + dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001U); + + /*********************************************************************** + * wait pi_int_status[0] + ***********************************************************************/ + flag = 0U; + complete = 0U; + cur_frq = 0U; + retry = RETRY_MAX; + + do { + for (frqchg_req = 0U, ch = 0U; ch < DRAM_CH_CNT; ch++) { + if (((~complete) & ddr_phyvalid) & (1U << ch)) { + if (mmio_read_32(DBSC_DBPDSTAT(ch)) & 0x01U) { + frqchg_req = 1U; + mst_ch = ch; + break; + } + } + } + + if (frqchg_req) { + cur_frq = (0x0300U & mmio_read_32(DBSC_DBPDSTAT(mst_ch))) >> 8; + flag = pll3_freq(cur_frq); + if (flag) { + break; + } + } else { + foreach_vch(ch) { + if (complete & (1U << ch)) { + continue; + } + mmio_write_32(DBSC_DBPDRGA(ch), DDR_REGDEF_ADR(_reg_PI_INT_STATUS) | 0x00004000U); + if (0x00008000U & mmio_read_32(DBSC_DBPDRGA(ch))) { + mmio_write_32(DBSC_DBPDRGA(ch), DDR_REGDEF_ADR(_reg_PI_INT_STATUS) | 0x00008000U); + dataL = mmio_read_32(DBSC_DBPDRGD(ch)); + mmio_write_32(DBSC_DBPDRGA(ch), DDR_REGDEF_ADR(_reg_PI_INT_STATUS) | 0x00000000U); + if (dataL & 0x01U) { + complete |= (1U << ch); + } + } + } + if (complete == ddr_phyvalid) { + break; + } + } + } while (--retry); + + foreach_vch(ch) { + /* dummy read */ + dataL = ddr_getval(ch, _reg_PI_START); + dataL = ddr_getval(ch, _reg_PI_INT_STATUS); + ddr_setval(ch, _reg_PI_INT_ACK, dataL); + } + + return complete; +} + +static void manual_frequency_change(void) +{ + uint32_t ch; + + /* FSP-OP:1 FSP-WR:1 VRCG:1 */ + send_dbcmd(0x0e840dc8U); + + /* PDE */ + send_dbcmd(0x08840000U); + + /* init start ass */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBDFICNT(ch), 0x01000011U); + } + + /* wait init comp neg */ + foreach_vch(ch) { + while((mmio_read_32(DBSC_DBDFISTAT(ch)) & 0x00000001U) != 0U); + } + + pll3_control(1); + + /* init start neg */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBDFICNT(ch), 0x01000010U); + } + + /* wait init comp ass */ + foreach_vch(ch) { + while((mmio_read_32(DBSC_DBDFISTAT(ch)) & 0x00000001U) != 1U); + } + + /* PDX */ + send_dbcmd(0x08840001U); + + /* set MR13 for FSP */ + ddr_setval_ach(_reg_PI_MR13_DATA_0, 0xc8U); + ddr_setval_ach(_reg_PI_MR13_DATA_1, 0xc8U); +} + +static uint32_t manual_training_wrlvl(void) +{ + uint32_t dataL; + uint32_t ch, cs, rank; + uint32_t wr_training_ng; + + if (ch_have_this_cs[1] != 0) { + rank = 2; + } else { + rank = 1; + } + + /* WR LVL */ + wr_training_ng = 0x00U; + + for(cs = 0; rank > cs; cs++) { + ddr_setval_ach(_reg_PI_WRLVL_CS, cs); + ddr_setval_ach(_reg_PI_WRLVL_REQ, 0x1U); + + foreach_vch(ch) { + while(1) { + dataL = ddr_getval(ch, _reg_PI_INT_STATUS); + if(dataL & 0x00001000U) break; + } + } + foreach_vch(ch) { + if (ddr_getval(ch, _reg_PHY_WRLVL_STATUS_OBS) & ( 1U << 12 )) { /* bit12 wrlvl_error */ + wr_training_ng |= 1U << ch; + } + } + ddr_setval_ach(_reg_PI_INT_ACK, 0x3FFFFFU); + } + return ~wr_training_ng; +} + +static uint32_t manual_training_rdgtlvl(void) +{ + uint32_t dataL; + uint32_t ch, cs, rank; + uint32_t gt_training_ng; + + if (ch_have_this_cs[1] != 0) { + rank = 2; + } else { + rank = 1; + } + + /* RD GATE LVL */ + gt_training_ng = 0x00U; + + for(cs = 0; rank > cs; cs++) { + ddr_setval_ach(_reg_PI_RDLVL_CS, cs); + ddr_setval_ach(_reg_PI_RDLVL_GATE_REQ, 0x1U); + + foreach_vch(ch) { + while(1) { + dataL = ddr_getval(ch, _reg_PI_INT_STATUS); + if(dataL & 0x00001000U) break; + } + } + foreach_vch(ch) { + if (ddr_getval(ch, _reg_PHY_GTLVL_STATUS_OBS) & ( 3U << 6 )) { /* bit6 Minimum delay setup error, bit7 Maximum delay setup error */ + gt_training_ng |= 1U << ch; + } + } + ddr_setval_ach(_reg_PI_INT_ACK, 0x3FFFFFU); + } + return ~gt_training_ng; +} + +static uint32_t manual_training_rdlvl(void) +{ + uint32_t dataL; + uint32_t ch, cs, rank; + uint32_t rd_training_ng; + + if (ch_have_this_cs[1] != 0) { + rank = 2; + } else { + rank = 1; + } + + /* RD LVL */ + rd_training_ng = 0x00U; + + for(cs = 0; rank > cs; cs++) { + ddr_setval_ach(_reg_PI_RDLVL_CS, cs); + ddr_setval_ach(_reg_PI_RDLVL_REQ, 0x1U); + + foreach_vch(ch) { + while(1) { + dataL = ddr_getval(ch, _reg_PI_INT_STATUS); + if(dataL & 0x00001000U) break; + } + } + foreach_vch(ch) { + if (ddr_getval(ch, _reg_PI_INT_STATUS) & ( 1U << 1 )) { /* bit1 PI_RDLVL_ERROR_BIT */ + rd_training_ng |= 1U << ch; + } + } + ddr_setval_ach(_reg_PI_INT_ACK, 0x3FFFFFU); + } + return ~rd_training_ng; +} + +static uint32_t manual_training_wdqlvl(void) +{ + uint32_t dataL; + uint32_t ch, cs, rank; + uint32_t wdq_training_ng; + + if (ch_have_this_cs[1] != 0) { + rank = 2; + } else { + rank = 1; + } + + /* WDQ LVL */ + wdq_training_ng = 0x00U; + + for(cs = 0; rank > cs; cs++) { + ddr_setval_ach(_reg_PI_WDQLVL_CS, cs); + ddr_setval_ach(_reg_PI_WDQLVL_REQ, 0x1U); + + foreach_vch(ch) { + while(1) { + dataL = ddr_getval(ch, _reg_PI_INT_STATUS); + if(dataL & 0x00001000U) break; + } + } + foreach_vch(ch) { + if (ddr_getval(ch, _reg_PI_INT_STATUS) & ( 1U << 5 )) { /* bit5 PI_WDQLVL_ERROR_BIT */ + wdq_training_ng |= 1U << ch; + } + } + ddr_setval_ach(_reg_PI_INT_ACK, 0x3FFFFFU); + } + return ~wdq_training_ng; +} + +/*********************************************************************** + * CA Vref Training + ***********************************************************************/ +static uint32_t ca_vref_training(void) +{ + uint32_t dvw, dvw_tmp[DRAM_CH_CNT][CS_CNT]; + uint32_t cavref, cavref_set_min[DRAM_CH_CNT][CS_CNT], cavref_set_max[DRAM_CH_CNT][CS_CNT]; + uint32_t ch, cs, rank; + uint32_t i, dataL, tmp; + uint32_t vref_start, vref_end; + uint32_t ca_training_ng; + + foreach_ech(ch) { + for (cs = 0; CS_CNT > cs; cs++) { + dvw_tmp[ch][cs] = 0x0000U; + cavref_set_min[ch][cs] = 0x0000U; + cavref_set_max[ch][cs] = 0x0000U; + } + } + + /*********************************************************************** + * CA Vref (MR12) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->vref_ca); + if (dataL) { + vref_start = dataL & 0x00ffU; + vref_end = (dataL & 0xff00U) >> 8; + } else { + vref_start = 0x000eU; + vref_end = 0x0014U; + } + + /*********************************************************************** + * CA training setting + ***********************************************************************/ + ddr_setval_ach(_reg_PI_MR13_DATA_0, 0xc8U); + ddr_setval_ach(_reg_PI_MR13_DATA_1, 0xc8U); + + ddr_setval_ach(_reg_PI_CA_TRAIN_VREF_EN, 0x0001U); + + if (ch_have_this_cs[1] != 0) { + rank = 2; + } else { + rank = 1; + } + + /*********************************************************************** + * Search Best CA VREF + ***********************************************************************/ + for(cs =0; rank > cs; cs++) { + for (cavref = vref_start; cavref <= vref_end; cavref += DDR_CAVREF_DELTA) { + ddr_setval_ach(_reg_PI_CALVL_CS, cs); + if (cs) { + ddr_setval_ach(_reg_PI_MR12_DATA_F1_1, cavref); + } else { + ddr_setval_ach(_reg_PI_MR12_DATA_F1_0, cavref); + } + ddr_setval_ach(_reg_PI_CALVL_REQ, 0x0001U); + + dataL = 0x00U; + while(dataL == 0x00U) { + dataL = 0x01U << 19; + foreach_vch(ch) { + dataL &= (ddr_getval(ch, _reg_PI_INT_STATUS)); + } + } + + foreach_vch(ch) { + if((0x00000010U & ddr_getval(ch, _reg_PI_INT_STATUS)) == 0x00000000U) { + dvw = 0x0000ffffU; + for (i = 0; i < 6; i++){ + ddr_setval(ch, _reg_PHY_ADR_CALVL_OBS_SELECT_0, i); + dataL = ddr_getval(ch, _reg_PHY_ADR_CALVL_CH0_OBS0_0); + tmp = (dataL & 0x000007ffU) - ((dataL >> 16) & 0x000007ffU); + if(dvw > tmp) { + dvw = tmp; + } + } + + if(dvw_tmp[ch][cs] < dvw) { + dvw_tmp[ch][cs] = dvw; + cavref_set_min[ch][cs] = cavref; + cavref_set_max[ch][cs] = cavref; + } else if (dvw_tmp[ch][cs] == dvw) { + cavref_set_max[ch][cs] = cavref; + } + } + ddr_setval(ch, _reg_PI_INT_ACK, ddr_getval(ch, _reg_PI_INT_STATUS)); + } + } + } + + /*********************************************************************** + * Use the Best CA VREF to do CA training + ***********************************************************************/ + if (rank == 2) { + ddr_setval_ach(_reg_PHY_ADR_CALVL_RANK_CTRL_0, 0x03U); + } + + foreach_vch(ch) { + ddr_setval(ch, _reg_PI_MR12_DATA_F1_0, (cavref_set_min[ch][0] + cavref_set_max[ch][0]) / 2); + ddr_setval(ch, _reg_PI_MR12_DATA_F1_1, (cavref_set_min[ch][rank - 1] + cavref_set_max[ch][rank - 1]) / 2); + } + + ca_training_ng = 0x00U; + for(cs = 0; rank > cs; cs++) { + ddr_setval_ach(_reg_PI_CALVL_CS, cs); + ddr_setval_ach(_reg_PI_CALVL_REQ, 0x0001U); + + dataL = 0x00U; + while(dataL == 0x00U) { + dataL = 0x01U << 19; + foreach_vch(ch) { + dataL &= (ddr_getval(ch, _reg_PI_INT_STATUS)); + } + } + + foreach_vch(ch) { + if (ddr_getval(ch, _reg_PHY_CSLVL_OBS1) & 0xF0000000U) { + ca_training_ng |= 1U << ch; + } + ddr_setval(ch, _reg_PI_INT_ACK, ddr_getval(ch, _reg_PI_INT_STATUS)); + } + } + + ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01U); + ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01U); + + return ~ca_training_ng; +} + +/******************************************************************************* + * DSKEWCALLOCK status check + ******************************************************************************/ +static uint32_t dskewcallock_chk(void) +{ + uint32_t ch; + uint32_t dataL; + uint32_t dskewcallock_ok; + + ddr_setval_ach(_reg_SC_PHY_PLL_SPO_CAL_SNAP_OBS, 0x01U); + + dskewcallock_ok = 0U; + foreach_ech(ch) { + dataL = 0x01U & (ddr_getval(ch, _reg_PHY_PLL_SPO_CAL_OBS_0) >> 16); + dataL &= 0x01U & (ddr_getval(ch, _reg_PHY_PLL_SPO_CAL_OBS_1) >> 16); + dskewcallock_ok |= dataL << ch; + } + + return dskewcallock_ok; +} + +/******************************************************************************* + * Initialize ddr + ******************************************************************************/ +static uint32_t init_ddr(void) +{ + uint32_t phytrainingok; + uint32_t ch; + uint32_t err; + + MSG_LF("init_ddr:0\n"); +#ifdef DDR_BACKUPMODE + dram_get_boot_status(&ddrBackup); +#endif + + /*********************************************************************** + * PLL3 initialization setting + ***********************************************************************/ + /* Reset Status Monitor clear */ + cpg_write_32(CPG_FSRCHKCLRR4, 0x00000200U); + /* Reset Status Monitor set */ + cpg_write_32(CPG_FSRCHKSETR4, 0x00000200U); + /* ddrphy soft reset assert */ + cpg_write_32(CPG_SRST4, mmio_read_32(CPG_SRST4) | 0x00000200U); + /* wait reset FB */ + while((mmio_read_32(CPG_FSRCHKRA4) & 0x00000200U) != 0U); + /* Reset Status Monitor clear */ + cpg_write_32(CPG_FSRCHKCLRR4, 0x00000200U); + + pll3_control(1); /* Initialize PLL3 setting */ + + /* ddrphy soft reset negate */ + cpg_write_32(CPG_SRSTCLR4, 0x00000200U); + while((mmio_read_32(CPG_SRST4) & 0x00000200U) != 0U); + + /*********************************************************************** + * unlock phy + ***********************************************************************/ + /* Unlock DDRPHY register */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU); + } + + /*********************************************************************** + * dbsc register pre-setting + ***********************************************************************/ + dbsc_regset_pre(); + + /*********************************************************************** + * load ddrphy registers + ***********************************************************************/ + ddrtbl_load(); + + /*********************************************************************** + * configure ddrphy registers + ***********************************************************************/ + ddr_config(); + + /*********************************************************************** + * ddr backupmode end + ***********************************************************************/ +#ifdef DDR_BACKUPMODE + if (ddrBackup) { + NOTICE("BL2: [WARM_BOOT]\n"); + } else { + NOTICE("BL2: [COLD_BOOT]\n"); + } + + err = dram_update_boot_status(ddrBackup); + if (err) { + NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); + return INITDRAM_ERR_I; + } +#endif + MSG_LF("init_ddr:1\n"); + + /*********************************************************************** + * dfi_init_start (start ddrphy) + ***********************************************************************/ + phytrainingok = dfi_init_start(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:1\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:2\n"); + + /*********************************************************************** + * load pi registers + ***********************************************************************/ + ddrtbl_load_pi(); + + /*********************************************************************** + * dbsc register set + ***********************************************************************/ + dbsc_regset(); + MSG_LF("init_ddr:3\n"); + + /*********************************************************************** + * setup DDR mode registers + ***********************************************************************/ + /* Dummy PDE */ + send_dbcmd(0x08840000U); + + /* PDX */ + send_dbcmd(0x08840001U); + + /* MRS */ + ddr_register_set(); + + MSG_LF("init_ddr:4\n"); + + /*********************************************************************** + * exec pi_training + ***********************************************************************/ + phytrainingok &= pi_training_go(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:2\n"); + return (phytrainingok); + } + + /*********************************************************************** + * exec frequency change + ***********************************************************************/ + manual_frequency_change(); + + /*********************************************************************** + * CA Vref Training + ***********************************************************************/ + phytrainingok &= ca_vref_training(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:3\n"); + return (phytrainingok); + } + + /*********************************************************************** + * exec wr_training + ***********************************************************************/ + phytrainingok &= manual_training_wrlvl(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:4\n"); + return (phytrainingok); + } + + /*********************************************************************** + * exec rdgt_training + ***********************************************************************/ + phytrainingok &= manual_training_rdgtlvl(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:5\n"); + return (phytrainingok); + } + + /*********************************************************************** + * exec rd_training + ***********************************************************************/ + phytrainingok &= manual_training_rdlvl(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:6\n"); + return (phytrainingok); + } + + /*********************************************************************** + * exec wdq_training + ***********************************************************************/ + phytrainingok &= manual_training_wdqlvl(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:7\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:5\n"); + + /*********************************************************************** + * FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (disable) + ***********************************************************************/ + ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U); + ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x00U); + + MSG_LF("init_ddr:6\n"); + + /*********************************************************************** + * DSKEWCALLOCK status check + ***********************************************************************/ + phytrainingok &= dskewcallock_chk(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:8\n"); + return (phytrainingok); + } + + /*********************************************************************** + * training complete, setup dbsc + ***********************************************************************/ + dbsc_regset_post(); + MSG_LF("init_ddr:7\n"); + + /*********************************************************************** + * lock phy + ***********************************************************************/ + /* Lock DDRPHY register */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U); + } + + return phytrainingok; +} + +/******************************************************************************* + * DDR Initialize entry + ******************************************************************************/ +int32_t InitDram(void) +{ + uint32_t ch, cs; + uint32_t dataL; + uint32_t failcount; + + dbsc_write_32(DBSC_DBSYSCNT0, 0x00001234U); + dbsc_write_32(DBSC_DBSYSCNT0A, 0x00001234U); + + /*********************************************************************** + * Judge product and cut + ***********************************************************************/ +/* + Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; +*/ + /*********************************************************************** + * Judge board type + ***********************************************************************/ + _cnf_BOARDTYPE = boardcnf_get_brd_type(); + if (_cnf_BOARDTYPE >= BOARDNUM) { + FATAL_MSG("BL2: DDR:Unknown Board\n"); + return 0xffU; + } + Boardcnf = (const struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE]; + + ddr_phyvalid = (uint32_t)(Boardcnf->phyvalid); + + max_density = 0U; + + for (cs = 0U; cs < CS_CNT; cs++) { + ch_have_this_cs[cs] = 0U; + } + + foreach_ech(ch) { + for (cs = 0U; cs < CS_CNT; cs++) { + ddr_density[ch][cs] = 0xffU; + } + } + + foreach_vch(ch) { + for (cs = 0U; cs < CS_CNT; cs++) { + dataL = (uint32_t)(Boardcnf->ch[ch].ddr_density[cs]); + ddr_density[ch][cs] = dataL; + if (dataL == 0xffU) { + continue; + } + if (dataL > max_density) { + max_density = dataL; + } + ch_have_this_cs[cs] |= (1U << ch); + } + } + + /*********************************************************************** + * Judge board clock frequency (in MHz) + ***********************************************************************/ + boardcnf_get_brd_clk(_cnf_BOARDTYPE, &brd_clk, &brd_clkdiv); + if ((0x01U << 14) & mmio_read_32(RST_MODEMR0)) { + brd_clkdiva = 1U; + } else { + brd_clkdiva = 0U; + } + + /*********************************************************************** + * Judge ddr operating frequency clock(in Mbps) + ***********************************************************************/ + boardcnf_get_ddr_mbps(_cnf_BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv); + + ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv, brd_clk, brd_clkdiv * (brd_clkdiva + 1U)); + ddr_mul_nf = (16U * ddr_mbps * (brd_clkdiv * (brd_clkdiva + 1U))) / (ddr_mbpsdiv * brd_clk) - (16U * ddr_mul); + ddr_mul_low = CLK_DIV(1600U, 1U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U)); + if((ddr_mul_low * brd_clk / (brd_clkdiv * (brd_clkdiva + 1U))) != 1600U) { + ddr_mul_low += 1; + } + + dataL = 0x03U & (mmio_read_32(RST_MODEMR0) >> 13); + bus_mbps = 0U; + bus_mbpsdiv = 0U; + + switch (dataL) { + case 0U: + bus_mbps = brd_clk * 0x32U; + bus_mbpsdiv = brd_clkdiv; + break; + case 1U: + bus_mbps = brd_clk * 0x28U; + bus_mbpsdiv = brd_clkdiv; + break; + case 2U: + /* Not supported */ + bus_mbps = brd_clk * 0x40U; + bus_mbpsdiv = brd_clkdiv * 2U; + break; + case 3U: + bus_mbps = brd_clk * 0x28U; + bus_mbpsdiv = brd_clkdiv * 2U; + break; + default: + bus_mbps = brd_clk * 0x28U; + bus_mbpsdiv = brd_clkdiv * 2U; + break; + } + + /*********************************************************************** + * Adjust tccd + ***********************************************************************/ + ddr_tccd = 8U; + + NOTICE("BL2: DDR%d(%s)", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); + + MSG_LF("Start\n"); + + /*********************************************************************** + * initialize DDR + ***********************************************************************/ + dataL = init_ddr(); + if (dataL == ddr_phyvalid) { + failcount = 0U; + } else { + failcount = 1U; + } + + NOTICE("..%d\n", failcount); + + dbsc_write_32(DBSC_DBSYSCNT0, 0x00000000U); + dbsc_write_32(DBSC_DBSYSCNT0A, 0x00000000U); + + if (failcount == 0U) { + return INITDRAM_OK; + } else { + return INITDRAM_NG; + } +} + +/******************************************************************************* + * END + ******************************************************************************/ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.c new file mode 100644 index 0000000..b837191 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.c @@ -0,0 +1,254 @@ +/******************************************************************************* + * Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DRAM Param setting + ******************************************************************************/ +#define JS2_DERATE 0 +#define DBSC_REFINT 1920 /* Average periodic refresh interval/Average Refresh Interval [ns] */ +#define DBSC_REFINTS 0 /* 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. */ + +#define REWT_TRAINING_INTERVAL 20000 /* Periodic-WriteDQ Training Interval [us] */ + +/******************************************************************************* + * NUMBER OF BOARD CONFIGRATION + * PLEASE DEFINE + ******************************************************************************/ +#define BOARDNUM 3 /* Add User platform BOARD */ + +/******************************************************************************* + * PLEASE SET board number or board judge function + ******************************************************************************/ +#define BOARD_JUDGE_AUTO +#ifdef BOARD_JUDGE_AUTO +static uint32_t _board_judge(void); +static uint32_t boardcnf_get_brd_type(void) { + return _board_judge(); +} +#else /* BOARD_JUDGE_AUTO */ +static uint32_t boardcnf_get_brd_type(void) { + return (0); +} +#endif /* BOARD_JUDGE_AUTO */ + +/******************************************************************************* + * BOARD CONFIGRATION + * PLEASE DEFINE boardcnfs[] + ******************************************************************************/ +struct _boardcnf_ch { + /* + 0x00...0000B: 4Gb dual channel die / 2Gb single channel die + 0x01...0001B: 6Gb dual channel die / 3Gb single channel die + 0x02...0010B: 8Gb dual channel die / 4Gb single channel die + 0x03...0011B: 12Gb dual channel die / 6Gb single channel die + 0x04...0100B: 16Gb dual channel die / 8Gb single channel die + 0xff...NO_MEMORY + */ + uint8_t ddr_density[CS_CNT]; + /* SoC caX([5][4][3][2][1][0]) -> MEM caY: */ + uint32_t ca_swap; + /* SoC dqsX([3][2][1][0]) -> MEM dqsY: */ + uint16_t dqs_swap; + /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ + uint32_t dq_swap[SLICE_CNT]; + /* SoC dm -> MEM dqY/dm: (8 means DM) */ + uint8_t dm_swap[SLICE_CNT]; +}; + +struct _boardcnf { + /* ch in use */ + uint16_t phyvalid; + /* Read vref (SoC) training range : [15:8]stop / [7:0]start, 0x0000 = default val */ + uint16_t vref_r; + /* Write vref (MR14) training range : [15:8]stop / [7:0]start, 0x0000 = default val */ + uint16_t vref_w; + /* CA vref (MR12) training range : [15:8]stop / [7:0]start, 0x0000 = default val */ + uint16_t vref_ca; + + struct _boardcnf_ch ch[2]; +}; + +static const struct _boardcnf boardcnfs[BOARDNUM] = { +/* + * boardcnf[0] RENESAS S4 Spider (16Gbit 2rank) + */ +{ + 0x03, /* phyvalid */ + 0x0000, /* vref_r */ + 0x0000, /* vref_w */ + 0x0000, /* vref_ca */ + { +/* ch[0] */ { /* M0CAxB/M0DQ[23:16],M0DQ[31:24] */ +/* ddr_density[] */ { 0x04, 0x04 }, +/* ca_swap */ 0x243510U, +/* dqs_swap */ 0x10, +/* dq_swap[] */ { 0x21706345, 0x23510746 }, +/* dm_swap[] */ { 0x08, 0x08 } + }, +/* ch[1] */ { /* M0CAxA/M0DQ[15: 0] */ +/* ddr_density[] */ { 0x04, 0x04 }, +/* ca_swap */ 0x345210U, +/* dqs_swap */ 0x10, +/* dq_swap[] */ { 0x30124675, 0x53126047 }, +/* dm_swap[] */ { 0x08, 0x08 } + } + } +}, +/* + * boardcnf[1] RENESAS S4-N Spider (16Gbit 2rank) + */ +{ + 0x03, /* phyvalid */ + 0x0000, /* vref_r */ + 0x0000, /* vref_w */ + 0x0000, /* vref_ca */ + { +/* ch[0] */ { /* M0CAxB/M0DQ[23:16],M0DQ[31:24] */ +/* ddr_density[] */ { 0x04, 0x04 }, +/* ca_swap */ 0x243510U, +/* dqs_swap */ 0x10, +/* dq_swap[] */ { 0x21705634, 0x23516048 }, +/* dm_swap[] */ { 0x08, 0x07 } + }, +/* ch[1] */ { /* M0CAxA/M0DQ[15: 0] */ +/* ddr_density[] */ { 0x04, 0x04 }, +/* ca_swap */ 0x345201U, +/* dqs_swap */ 0x10, +/* dq_swap[] */ { 0x03124675, 0x35126047 }, +/* dm_swap[] */ { 0x08, 0x08 } + } + } +}, +/* + * boardcnf[2] RENESAS S4(2ch) + */ +{ + 0x03, /* phyvalid */ + 0x0000, /* vref_r */ + 0x0000, /* vref_w */ + 0x0000, /* vref_ca */ + { +/* ch[0] */ { +/* ddr_density[] */ { 0x04, 0x04 }, +/* ca_swap */ 0x00543210U, +/* dqs_swap */ 0x10, +/* dq_swap[] */ { 0x76543210, 0x76543210 }, +/* dm_swap[] */ { 0x08, 0x08 } + }, +/* ch[1] */ { +/* ddr_density[] */ { 0x04, 0x04 }, +/* ca_swap */ 0x00543210U, +/* dqs_swap */ 0x10, +/* dq_swap[] */ { 0x76543210, 0x76543210 }, +/* dm_swap[] */ { 0x08, 0x08 } + } + } +} +}; + +/******************************************************************************* + * EXTAL CLOCK DEFINITION + * PLEASE DEFINE HOW TO JUDGE BORAD CLK + ******************************************************************************/ +/* + * RENESAS SPIDER BOARD EXAMPLE + * judge by md14/md13 + * + * 16.00MHz CLK,DIV= 48,3 (md14,md13==0,0) + * 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1) + * 40.00MHz CLK,DIV=120,3 (md14,md13==1,1) +*/ +void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) { + uint32_t md; + + md = (mmio_read_32(RST_MODEMR0) >> 13) & 0x3; + switch(md) { + case 0x0 : *clk = 48; *div = 3; break; /* 48 / 3 = 16.00MHz */ + case 0x1 : *clk = 60; *div = 3; break; /* 60 / 3 = 20.00MHz */ +/* case 0x2 : *clk = 75; *div = 3; break; */ /* Not supported */ + case 0x3 : *clk =120; *div = 3; break; /* 120 / 3 = 40.00MHz */ + } + (void)brd; +} + +/******************************************************************************* + * DDR MBPS TARGET + * PLEASE DEFINE HOW TO JUDGE DDR BPS + ******************************************************************************/ +/* + DDRxxxx (judge by md17) : Mbps + SSCG enable / disable for PLL1 (judge by md37/md36) +*/ +void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div) { + uint32_t md; + uint32_t sscg; + + md = (mmio_read_32(RST_MODEMR0) >> 17) & 0x01U; + sscg = (mmio_read_32(RST_MODEMR1) >> 4) & 0x03U; + + switch(sscg) { + case 0x0 : + switch(md) { + case 0x0 : *mbps = 3200; *div = 1; break; + case 0x1 : *mbps = 2120; *div = 1; break; + } + break; + case 0x1 : + switch(md) { + case 0x0 : *mbps = 3120; *div = 1; break; + case 0x1 : *mbps = 2120; *div = 1; break; + } + break; + case 0x2 : + switch(md) { + case 0x0 : *mbps = 3040; *div = 1; break; + case 0x1 : *mbps = 2120; *div = 1; break; + } + break; + case 0x3 : + switch(md) { + case 0x0 : *mbps = 3000; *div = 1; break; + case 0x1 : *mbps = 2120; *div = 1; break; + } + break; + } + (void)brd; +} + +#ifdef BOARD_JUDGE_AUTO +/******************************************************************************* + * SAMPLE board detect function + ******************************************************************************/ +static uint32_t _board_judge(void) { + uint32_t brd; + + brd = 0; /* spider (16Gbit 2rank)*/ + + return brd; +} +#endif diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.h new file mode 100644 index 0000000..4595f3b --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.h @@ -0,0 +1,73 @@ +/******************************************************************************* +* File Name : boot_init_dram_config.h +* Version : 1.0 +* Description : This file containing structure definitions for board settings +******************************************************************************/ + +/***************************************************************************** +* History : Please refer the readme.txt +* +******************************************************************************/ + +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* © 2020-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#ifndef BOOT_INIT_DRAM_CONFIG +#define BOOT_INIT_DRAM_CONFIG + +#include +#include "boot_init_dram_regdef.h" +/******************************************************************************* + * DRAM Param setting + * this parameter is depending on the user + ******************************************************************************/ +#define JS2_DERATE 0 +#define BOARDNUM 5 +#define USE_BOARD 0 + +/******************************************************************************* + * BOARD CONFIGRATION + * PLEASE DEFINE boardcnfs[] + ******************************************************************************/ + +struct board_cfg_t +{ + uint32_t phyvalid; + uint32_t vref_r; + uint32_t vref_w; + uint32_t vref_ca; + + + uint32_t ddr_density[CH_CNT][CS_CNT]; + uint32_t ca_swap[CH_CNT]; + uint32_t dqs_swap[CH_CNT]; + uint32_t dq_swap[CH_CNT][SLICE_CNT]; + uint32_t dm_swap[CH_CNT][SLICE_CNT]; +}; + +void judge_board_clk_freq(uint32_t* board_clk, uint32_t* board_clkdiv, uint32_t* board_clkdiva); +void judge_ddr_ope_freq(uint32_t* ddr_mbps, uint32_t* ddr_mbpsdiv); +void judge_bus_clk_freq(uint32_t* bus_mbps, uint32_t* bus_mbpsdiv, const uint32_t* board_clk, const uint32_t* board_clkdiv); +extern const struct board_cfg_t board_cfg[BOARDNUM]; + +#endif /* BOOT_INIT_DRAM_CONFIG */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_regdef.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_regdef.h new file mode 100644 index 0000000..705a895 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_regdef.h @@ -0,0 +1,260 @@ +/******************************************************************************* + * Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +#if defined(__RH850G3K__) +#include "remap_register.h" +#endif + +#define RCAR_DDR_VERSION "rev.0.30rc7" +#define DRAM_CH_CNT 0x02 +#define SLICE_CNT 0x02 +#define CS_CNT 0x02 + +/* for pll setting */ +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) +#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb))) + +/* for ddr density setting */ +#define DBMEMCONF_REG(d3, row, bank, col, dw) (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw)) +#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (28 - 3 - 10 - 1), 3, 10, 1)) /* 16bit */ +#define DBMEMCONF_VAL(ch,cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) + +/* system registers : CPG */ +#define CPG_FRQCRD_KICK_BIT (1U << 31) + +#define CPG_PLL3CR_KICK_BIT (1U << 31) + +#define CPG_PLLECR_PLL3E_BIT (1U << 3) +#define CPG_PLLECR_PLL3ST_BIT (1U << 11) + +#if defined(__RH850G3K__) +#define CPG_BASE (BASE_CPG_ADDR) +#else +#define CPG_BASE (0xE6150000U) +#endif +#define CPG_CPGWPR (CPG_BASE + 0x0000U) +#define CPG_CPGWPCR (CPG_BASE + 0x0004U) +#define CPG_FRQCRA (CPG_BASE + 0x0800U) +#define CPG_FRQCRB (CPG_BASE + 0x0804U) +#define CPG_FRQCRC (CPG_BASE + 0x0808U) +#define CPG_FRQCRD (CPG_BASE + 0x080CU) +#define CPG_PLLECR (CPG_BASE + 0x0820U) +#define CPG_PLL3CR0 (CPG_BASE + 0x083CU) +#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U) +#define CPG_Z0CKKSCR (CPG_BASE + 0x08A8U) +#define CPG_Z1CKKSCR (CPG_BASE + 0x08ACU) +#define CPG_SRST4 (CPG_BASE + 0x2C10U) +#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U) +#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U) +#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U) +#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U) + +#if defined(__RH850G3K__) +#define RST_BASE (BASE_RESET_ADDR) +#else +#define RST_BASE (0xE6160000U) +#endif +#define RST_MODEMR0 (RST_BASE + 0x0000U) +#define RST_MODEMR1 (RST_BASE + 0x0004U) + +/* Product Register */ +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) + +#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */ + +#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */ +#define PRR_PRODUCT_11 (0x00000001U) /* ver 1.1 */ +#define PRR_PRODUCT_12 (0x00000002U) /* ver 1.2 */ + +/* DBSC registers */ +#if defined(__RH850G3K__) +#define DBSC_BASE (BASE_DBSC_ADDR) +#else +#define DBSC_BASE (0xE6790000U) +#endif +#define DBSC_DBSYSCONF0 (DBSC_BASE + 0x0000U) +#define DBSC_DBSYSCONF1 (DBSC_BASE + 0x0004U) +#define DBSC_DBSYSCONF1A (DBSC_BASE + 0x0008U) +#define DBSC_DBSYSCONF2 (DBSC_BASE + 0x000CU) +#define DBSC_DBPHYCONF0 (DBSC_BASE + 0x0010U) +#define DBSC_DBSYSCONF2A (DBSC_BASE + 0x0014U) +#define DBSC_DBKIND (DBSC_BASE + 0x0020U) +#define DBSC_DBKINDA (DBSC_BASE + 0x0024U) + +#define DBSC_DBMEMCONF(ch, cs) (DBSC_BASE + 0x0030U + 0x2000U * (ch & 0x04U) + 0x10U * (ch & 0x03U) + 0x04U * cs) +#define DBSC_DBMEMCONF_0_0 (DBSC_BASE + 0x0030U) +#define DBSC_DBMEMCONF_0_1 (DBSC_BASE + 0x0034U) +#define DBSC_DBMEMCONF_0_2 (DBSC_BASE + 0x0038U) +#define DBSC_DBMEMCONF_0_3 (DBSC_BASE + 0x003CU) +#define DBSC_DBMEMCONF_1_0 (DBSC_BASE + 0x0040U) +#define DBSC_DBMEMCONF_1_1 (DBSC_BASE + 0x0044U) +#define DBSC_DBMEMCONF_1_2 (DBSC_BASE + 0x0048U) +#define DBSC_DBMEMCONF_1_3 (DBSC_BASE + 0x004CU) +#define DBSC_DBMEMCONF_2_0 (DBSC_BASE + 0x0050U) +#define DBSC_DBMEMCONF_2_1 (DBSC_BASE + 0x0054U) +#define DBSC_DBMEMCONF_2_2 (DBSC_BASE + 0x0058U) +#define DBSC_DBMEMCONF_2_3 (DBSC_BASE + 0x005CU) +#define DBSC_DBMEMCONF_3_0 (DBSC_BASE + 0x0060U) +#define DBSC_DBMEMCONF_3_1 (DBSC_BASE + 0x0064U) +#define DBSC_DBMEMCONF_3_2 (DBSC_BASE + 0x0068U) +#define DBSC_DBMEMCONF_3_3 (DBSC_BASE + 0x006CU) + +#define DBSC_DBMEMCONFA(ch, cs) (DBSC_BASE + 0x0070U + 0x2000U * (ch & 0x04U) + 0x10U * (ch & 0x03U) + 0x04U * cs) +#define DBSC_DBMEMCONF_0_0A (DBSC_BASE + 0x0070U) +#define DBSC_DBMEMCONF_0_1A (DBSC_BASE + 0x0074U) +#define DBSC_DBMEMCONF_0_2A (DBSC_BASE + 0x0078U) +#define DBSC_DBMEMCONF_0_3A (DBSC_BASE + 0x007CU) +#define DBSC_DBMEMCONF_1_0A (DBSC_BASE + 0x0080U) +#define DBSC_DBMEMCONF_1_1A (DBSC_BASE + 0x0084U) +#define DBSC_DBMEMCONF_1_2A (DBSC_BASE + 0x0088U) +#define DBSC_DBMEMCONF_1_3A (DBSC_BASE + 0x008CU) +#define DBSC_DBMEMCONF_2_0A (DBSC_BASE + 0x0090U) +#define DBSC_DBMEMCONF_2_1A (DBSC_BASE + 0x0094U) +#define DBSC_DBMEMCONF_2_2A (DBSC_BASE + 0x0098U) +#define DBSC_DBMEMCONF_2_3A (DBSC_BASE + 0x009CU) +#define DBSC_DBMEMCONF_3_0A (DBSC_BASE + 0x00A0U) +#define DBSC_DBMEMCONF_3_1A (DBSC_BASE + 0x00A4U) +#define DBSC_DBMEMCONF_3_2A (DBSC_BASE + 0x00A8U) +#define DBSC_DBMEMCONF_3_3A (DBSC_BASE + 0x00ACU) + +#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U) +#define DBSC_DBSYSCNT0A (DBSC_BASE + 0x0108U) + +#define DBSC_DBACEN (DBSC_BASE + 0x0200U) +#define DBSC_DBRFEN (DBSC_BASE + 0x0204U) +#define DBSC_DBCMD (DBSC_BASE + 0x0208U) +#define DBSC_DBWAIT (DBSC_BASE + 0x0210U) + +#define DBSC_DBTR(x) (DBSC_BASE + 0x0300U + 0x04U * (x)) +#define DBSC_DBTR0 (DBSC_BASE + 0x0300U) +#define DBSC_DBTR1 (DBSC_BASE + 0x0304U) +#define DBSC_DBTR3 (DBSC_BASE + 0x030CU) +#define DBSC_DBTR4 (DBSC_BASE + 0x0310U) +#define DBSC_DBTR5 (DBSC_BASE + 0x0314U) +#define DBSC_DBTR6 (DBSC_BASE + 0x0318U) +#define DBSC_DBTR7 (DBSC_BASE + 0x031CU) +#define DBSC_DBTR8 (DBSC_BASE + 0x0320U) +#define DBSC_DBTR9 (DBSC_BASE + 0x0324U) +#define DBSC_DBTR10 (DBSC_BASE + 0x0328U) +#define DBSC_DBTR11 (DBSC_BASE + 0x032CU) +#define DBSC_DBTR12 (DBSC_BASE + 0x0330U) +#define DBSC_DBTR13 (DBSC_BASE + 0x0334U) +#define DBSC_DBTR14 (DBSC_BASE + 0x0338U) +#define DBSC_DBTR15 (DBSC_BASE + 0x033CU) +#define DBSC_DBTR16 (DBSC_BASE + 0x0340U) +#define DBSC_DBTR17 (DBSC_BASE + 0x0344U) +#define DBSC_DBTR18 (DBSC_BASE + 0x0348U) +#define DBSC_DBTR19 (DBSC_BASE + 0x034CU) +#define DBSC_DBTR20 (DBSC_BASE + 0x0350U) +#define DBSC_DBTR21 (DBSC_BASE + 0x0354U) +#define DBSC_DBTR22 (DBSC_BASE + 0x0358U) +#define DBSC_DBTR23 (DBSC_BASE + 0x035CU) +#define DBSC_DBTR24 (DBSC_BASE + 0x0360U) +#define DBSC_DBTR25 (DBSC_BASE + 0x0364U) +#define DBSC_DBTR26 (DBSC_BASE + 0x0368U) + +#define DBSC_DBBL (DBSC_BASE + 0x0400U) +#define DBSC_DBBLA (DBSC_BASE + 0x0404U) + +#define DBSC_DBRFCNF1 (DBSC_BASE + 0x0414U) +#define DBSC_DBRFCNF2 (DBSC_BASE + 0x0418U) + +#define DBSC_DBCALCNF (DBSC_BASE + 0x0424U) + +#define DBSC_DBRNK(x) (DBSC_BASE + 0x0430U + 0x04U * (x)) +#define DBSC_DBRNK2 (DBSC_BASE + 0x0438U) +#define DBSC_DBRNK3 (DBSC_BASE + 0x043CU) +#define DBSC_DBRNK4 (DBSC_BASE + 0x0440U) +#define DBSC_DBRNK5 (DBSC_BASE + 0x0444U) + +#define DBSC_DBDBICNT (DBSC_BASE + 0x0518U) +#define DBSC_DBDFIPMSTRCNF (DBSC_BASE + 0x0520U) +#define DBSC_DBDFICUPDCNF (DBSC_BASE + 0x052CU) + +#define DBSC_DBDFISTAT(ch) (DBSC_BASE + 0x0600U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBDFISTAT_0 (DBSC_BASE + 0x0600U) +#define DBSC_DBDFISTAT_1 (DBSC_BASE + 0x0640U) +#define DBSC_DBDFISTAT_2 (DBSC_BASE + 0x0680U) +#define DBSC_DBDFISTAT_3 (DBSC_BASE + 0x06C0U) + +#define DBSC_DBDFICNT(ch) (DBSC_BASE + 0x0604U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBDFICNT_0 (DBSC_BASE + 0x0604U) +#define DBSC_DBDFICNT_1 (DBSC_BASE + 0x0644U) +#define DBSC_DBDFICNT_2 (DBSC_BASE + 0x0684U) +#define DBSC_DBDFICNT_3 (DBSC_BASE + 0x06C4U) + +#define DBSC_DBPDCNT2(ch) (DBSC_BASE + 0x0618U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBPDCNT2_0 (DBSC_BASE + 0x0618U) +#define DBSC_DBPDCNT2_1 (DBSC_BASE + 0x0658U) +#define DBSC_DBPDCNT2_2 (DBSC_BASE + 0x0698U) +#define DBSC_DBPDCNT2_3 (DBSC_BASE + 0x06D8U) + +#define DBSC_DBPDCNT3(ch) (DBSC_BASE + 0x061CU + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBPDCNT3_0 (DBSC_BASE + 0x061CU) +#define DBSC_DBPDCNT3_1 (DBSC_BASE + 0x065CU) +#define DBSC_DBPDCNT3_2 (DBSC_BASE + 0x069CU) +#define DBSC_DBPDCNT3_3 (DBSC_BASE + 0x06DCU) + +#define DBSC_DBPDLK(ch) (DBSC_BASE + 0x0620U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBPDLK_0 (DBSC_BASE + 0x0620U) +#define DBSC_DBPDLK_1 (DBSC_BASE + 0x0660U) +#define DBSC_DBPDLK_2 (DBSC_BASE + 0x06a0U) +#define DBSC_DBPDLK_3 (DBSC_BASE + 0x06e0U) + +#define DBSC_DBPDRGA(ch) (DBSC_BASE + 0x0624U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBPDRGA_0 (DBSC_BASE + 0x0624U) +#define DBSC_DBPDRGA_1 (DBSC_BASE + 0x0664U) +#define DBSC_DBPDRGA_2 (DBSC_BASE + 0x06A4U) +#define DBSC_DBPDRGA_3 (DBSC_BASE + 0x06E4U) + +#define DBSC_DBPDRGD(ch) (DBSC_BASE + 0x0628U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBPDRGD_0 (DBSC_BASE + 0x0628U) +#define DBSC_DBPDRGD_1 (DBSC_BASE + 0x0668U) +#define DBSC_DBPDRGD_2 (DBSC_BASE + 0x06A8U) +#define DBSC_DBPDRGD_3 (DBSC_BASE + 0x06E8U) + +#define DBSC_DBPDSTAT(ch) (DBSC_BASE + 0x0630U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBPDSTAT_0 (DBSC_BASE + 0x0630U) +#define DBSC_DBPDSTAT_1 (DBSC_BASE + 0x0670U) +#define DBSC_DBPDSTAT_2 (DBSC_BASE + 0x06B0U) +#define DBSC_DBPDSTAT_3 (DBSC_BASE + 0x06F0U) + +#define DBSC_DBPDSTAT1(ch) (DBSC_BASE + 0x0634U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) + +#define DBSC_DBBUS0CNF0 (DBSC_BASE + 0x0800U) +#define DBSC_DBBUS0CNF1 (DBSC_BASE + 0x0804U) + +#define DBSC_DBBCAMDIS (DBSC_BASE + 0x09FCU) + +#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U) + +#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U) +#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U) + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ddr_regdef.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ddr_regdef.h new file mode 100644 index 0000000..44b1c25 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ddr_regdef.h @@ -0,0 +1,1320 @@ +/******************************************************************************* + * Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +#define _reg_PHY_CLK_WR_BYPASS_SLAVE_DELAY 0x000b1000U +#define _reg_PHY_IO_PAD_DELAY_TIMING_BYPASS 0x10041000U +#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS 0x000a1001U +#define _reg_PHY_WRITE_PATH_LAT_ADD_BYPASS 0x10031001U +#define _reg_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY 0x000a1002U +#define _reg_PHY_BYPASS_TWO_CYC_PREAMBLE 0x10021002U +#define _reg_PHY_CLK_BYPASS_OVERRIDE 0x18011002U +#define _reg_PHY_SW_WRDQ0_SHIFT 0x00061003U +#define _reg_PHY_SW_WRDQ1_SHIFT 0x08061003U +#define _reg_PHY_SW_WRDQ2_SHIFT 0x10061003U +#define _reg_PHY_SW_WRDQ3_SHIFT 0x18061003U +#define _reg_PHY_SW_WRDQ4_SHIFT 0x00061004U +#define _reg_PHY_SW_WRDQ5_SHIFT 0x08061004U +#define _reg_PHY_SW_WRDQ6_SHIFT 0x10061004U +#define _reg_PHY_SW_WRDQ7_SHIFT 0x18061004U +#define _reg_PHY_SW_WRDM_SHIFT 0x00061005U +#define _reg_PHY_SW_WRDQS_SHIFT 0x08041005U +#define _reg_PHY_PER_RANK_CS_MAP 0x10021005U +#define _reg_PHY_PER_CS_TRAINING_MULTICAST_EN 0x18011005U +#define _reg_PHY_PER_CS_TRAINING_INDEX 0x00011006U +#define _reg_PHY_LP4_BOOT_RDDATA_EN_IE_DLY 0x08021006U +#define _reg_PHY_LP4_BOOT_RDDATA_EN_DLY 0x10051006U +#define _reg_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY 0x18051006U +#define _reg_PHY_LP4_BOOT_RPTR_UPDATE 0x00041007U +#define _reg_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST 0x08041007U +#define _reg_PHY_LP4_BOOT_WRPATH_GATE_DISABLE 0x10021007U +#define _reg_PHY_LP4_BOOT_RDDATA_EN_OE_DLY 0x18051007U +#define _reg_PHY_CTRL_LPBK_EN 0x00021008U +#define _reg_PHY_LPBK_CONTROL 0x08091008U +#define _reg_PHY_LPBK_DFX_TIMEOUT_EN 0x18011008U +#define _reg_PHY_AUTO_TIMING_MARGIN_CONTROL 0x00201009U +#define _reg_PHY_AUTO_TIMING_MARGIN_OBS 0x001c100aU +#define _reg_PHY_PRBS_PATTERN_START 0x0007100bU +#define _reg_PHY_PRBS_PATTERN_MASK 0x0809100bU +#define _reg_PHY_RDLVL_MULTI_PATT_ENABLE 0x1801100bU +#define _reg_PHY_RDLVL_MULTI_PATT_RST_DISABLE 0x0001100cU +#define _reg_PHY_VREF_INITIAL_STEPSIZE 0x0806100cU +#define _reg_PHY_VREF_TRAIN_OBS 0x1007100cU +#define _reg_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY 0x000a100dU +#define _reg_PHY_GATE_ERROR_DELAY_SELECT 0x1004100dU +#define _reg_SC_PHY_SNAP_OBS_REGS 0x1801100dU +#define _reg_PHY_GATE_SMPL1_SLAVE_DELAY 0x0009100eU +#define _reg_PHY_LPDDR 0x1001100eU +#define _reg_PHY_MEM_CLASS 0x1803100eU +#define _reg_PHY_GATE_SMPL2_SLAVE_DELAY 0x0009100fU +#define _reg_ON_FLY_GATE_ADJUST_EN 0x1002100fU +#define _reg_PHY_GATE_TRACKING_OBS 0x00201010U +#define _reg_PHY_DFI40_POLARITY 0x00011011U +#define _reg_PHY_LP4_PST_AMBLE 0x08021011U +#define _reg_PHY_RDLVL_PATT8 0x00201012U +#define _reg_PHY_RDLVL_PATT9 0x00201013U +#define _reg_PHY_RDLVL_PATT10 0x00201014U +#define _reg_PHY_RDLVL_PATT11 0x00201015U +#define _reg_PHY_RDLVL_PATT12 0x00201016U +#define _reg_PHY_RDLVL_PATT13 0x00201017U +#define _reg_PHY_RDLVL_PATT14 0x00201018U +#define _reg_PHY_RDLVL_PATT15 0x00201019U +#define _reg_PHY_SLAVE_LOOP_CNT_UPDATE 0x0003101aU +#define _reg_PHY_SW_FIFO_PTR_RST_DISABLE 0x0801101aU +#define _reg_PHY_MASTER_DLY_LOCK_OBS_SELECT 0x1004101aU +#define _reg_PHY_RDDQ_ENC_OBS_SELECT 0x1803101aU +#define _reg_PHY_RDDQS_DQ_ENC_OBS_SELECT 0x0004101bU +#define _reg_PHY_WR_ENC_OBS_SELECT 0x0804101bU +#define _reg_PHY_WR_SHIFT_OBS_SELECT 0x1004101bU +#define _reg_PHY_FIFO_PTR_OBS_SELECT 0x1804101bU +#define _reg_PHY_LVL_DEBUG_MODE 0x0001101cU +#define _reg_SC_PHY_LVL_DEBUG_CONT 0x0801101cU +#define _reg_PHY_WRLVL_ALGO 0x1002101cU +#define _reg_PHY_WRLVL_PER_START 0x1808101cU +#define _reg_PHY_WRLVL_CAPTURE_CNT 0x0006101dU +#define _reg_PHY_WRLVL_UPDT_WAIT_CNT 0x0804101dU +#define _reg_PHY_DQ_MASK 0x1008101dU +#define _reg_PHY_GTLVL_PER_START 0x000a101eU +#define _reg_PHY_GTLVL_CAPTURE_CNT 0x1006101eU +#define _reg_PHY_GTLVL_UPDT_WAIT_CNT 0x1804101eU +#define _reg_PHY_RDLVL_CAPTURE_CNT 0x0006101fU +#define _reg_PHY_RDLVL_UPDT_WAIT_CNT 0x0804101fU +#define _reg_PHY_RDLVL_OP_MODE 0x1002101fU +#define _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x1805101fU +#define _reg_PHY_RDLVL_PERIODIC_OBS_SELECT 0x00081020U +#define _reg_PHY_RDLVL_DATA_MASK 0x08081020U +#define _reg_PHY_WDQLVL_CLK_JITTER_TOLERANCE 0x10081020U +#define _reg_PHY_WDQLVL_BURST_CNT 0x18061020U +#define _reg_PHY_WDQLVL_PATT 0x00031021U +#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET 0x080b1021U +#define _reg_PHY_WDQLVL_UPDT_WAIT_CNT 0x18041021U +#define _reg_PHY_WDQLVL_DQDM_OBS_SELECT 0x00041022U +#define _reg_PHY_WDQLVL_PERIODIC_OBS_SELECT 0x08081022U +#define _reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS 0x10011022U +#define _reg_PHY_WDQLVL_DATADM_MASK 0x00091023U +#define _reg_PHY_USER_PATT0 0x00201024U +#define _reg_PHY_USER_PATT1 0x00201025U +#define _reg_PHY_USER_PATT2 0x00201026U +#define _reg_PHY_USER_PATT3 0x00201027U +#define _reg_PHY_USER_PATT4 0x00101028U +#define _reg_PHY_NTP_MULT_TRAIN 0x10011028U +#define _reg_PHY_NTP_EARLY_THRESHOLD 0x000a1029U +#define _reg_PHY_NTP_PERIOD_THRESHOLD 0x100a1029U +#define _reg_PHY_NTP_PERIOD_THRESHOLD_MIN 0x000a102aU +#define _reg_PHY_NTP_PERIOD_THRESHOLD_MAX 0x100a102aU +#define _reg_PHY_CALVL_VREF_DRIVING_SLICE 0x0001102bU +#define _reg_SC_PHY_MANUAL_CLEAR 0x0806102bU +#define _reg_PHY_FIFO_PTR_OBS 0x1008102bU +#define _reg_PHY_LPBK_RESULT_OBS 0x0020102cU +#define _reg_PHY_LPBK_ERROR_COUNT_OBS 0x0010102dU +#define _reg_PHY_MASTER_DLY_LOCK_OBS 0x100b102dU +#define _reg_PHY_RDDQ_SLV_DLY_ENC_OBS 0x0007102eU +#define _reg_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS 0x0807102eU +#define _reg_PHY_MEAS_DLY_STEP_VALUE 0x1008102eU +#define _reg_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS 0x1808102eU +#define _reg_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS 0x0008102fU +#define _reg_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS 0x080b102fU +#define _reg_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS 0x1807102fU +#define _reg_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS 0x00081030U +#define _reg_PHY_WR_ADDER_SLV_DLY_ENC_OBS 0x08081030U +#define _reg_PHY_WR_SHIFT_OBS 0x10031030U +#define _reg_PHY_WRLVL_HARD0_DELAY_OBS 0x000a1031U +#define _reg_PHY_WRLVL_HARD1_DELAY_OBS 0x100a1031U +#define _reg_PHY_WRLVL_STATUS_OBS 0x00111032U +#define _reg_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS 0x000a1033U +#define _reg_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS 0x100a1033U +#define _reg_PHY_WRLVL_ERROR_OBS 0x00101034U +#define _reg_PHY_GTLVL_HARD0_DELAY_OBS 0x100e1034U +#define _reg_PHY_GTLVL_HARD1_DELAY_OBS 0x000e1035U +#define _reg_PHY_GTLVL_STATUS_OBS 0x00121036U +#define _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x000a1037U +#define _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x100a1037U +#define _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS 0x00021038U +#define _reg_PHY_RDLVL_STATUS_OBS 0x00201039U +#define _reg_PHY_RDLVL_PERIODIC_OBS 0x0020103aU +#define _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS 0x000b103bU +#define _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS 0x100b103bU +#define _reg_PHY_WDQLVL_STATUS_OBS 0x0020103cU +#define _reg_PHY_WDQLVL_PERIODIC_OBS 0x0020103dU +#define _reg_PHY_DDL_MODE 0x001f103eU +#define _reg_PHY_DDL_MASK 0x0006103fU +#define _reg_PHY_DDL_TEST_OBS 0x00201040U +#define _reg_PHY_DDL_TEST_MSTR_DLY_OBS 0x00201041U +#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD 0x00081042U +#define _reg_PHY_LP4_WDQS_OE_EXTEND 0x08011042U +#define _reg_SC_PHY_RX_CAL_START 0x10011042U +#define _reg_PHY_RX_CAL_OVERRIDE 0x18011042U +#define _reg_PHY_RX_CAL_SAMPLE_WAIT 0x00081043U +#define _reg_PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE 0x08011043U +#define _reg_PHY_RX_CAL_DQ0 0x10091043U +#define _reg_PHY_RX_CAL_DQ1 0x00091044U +#define _reg_PHY_RX_CAL_DQ2 0x10091044U +#define _reg_PHY_RX_CAL_DQ3 0x00091045U +#define _reg_PHY_RX_CAL_DQ4 0x10091045U +#define _reg_PHY_RX_CAL_DQ5 0x00091046U +#define _reg_PHY_RX_CAL_DQ6 0x10091046U +#define _reg_PHY_RX_CAL_DQ7 0x00091047U +#define _reg_PHY_RX_CAL_DM 0x00121048U +#define _reg_PHY_RX_CAL_DQS 0x00091049U +#define _reg_PHY_RX_CAL_FDBK 0x10091049U +#define _reg_PHY_RX_CAL_OBS 0x000b104aU +#define _reg_PHY_RX_CAL_LOCK_OBS 0x1009104aU +#define _reg_PHY_RX_CAL_DISABLE 0x0001104bU +#define _reg_PHY_RX_CAL_SE_ADJUST 0x0807104bU +#define _reg_PHY_RX_CAL_DIFF_ADJUST 0x1007104bU +#define _reg_PHY_RX_CAL_COMP_VAL 0x1801104bU +#define _reg_PHY_RX_CAL_INDEX_MASK 0x000c104cU +#define _reg_PHY_PAD_RX_BIAS_EN 0x100b104cU +#define _reg_PHY_STATIC_TOG_DISABLE 0x0005104dU +#define _reg_PHY_DATA_DC_CAL_SAMPLE_WAIT 0x0808104dU +#define _reg_PHY_DATA_DC_CAL_TIMEOUT 0x1008104dU +#define _reg_PHY_DATA_DC_WEIGHT 0x1802104dU +#define _reg_PHY_DATA_DC_ADJUST_START 0x0006104eU +#define _reg_PHY_DATA_DC_ADJUST_SAMPLE_CNT 0x0808104eU +#define _reg_PHY_DATA_DC_ADJUST_THRSHLD 0x1008104eU +#define _reg_PHY_DATA_DC_ADJUST_DIRECT 0x1801104eU +#define _reg_PHY_DATA_DC_CAL_POLARITY 0x0001104fU +#define _reg_PHY_DATA_DC_CAL_START 0x0801104fU +#define _reg_PHY_DATA_DC_SW_RANK 0x1002104fU +#define _reg_PHY_FDBK_PWR_CTRL 0x1803104fU +#define _reg_PHY_SLV_DLY_CTRL_GATE_DISABLE 0x00011050U +#define _reg_PHY_RDPATH_GATE_DISABLE 0x08011050U +#define _reg_PHY_DCC_RXCAL_CTRL_GATE_DISABLE 0x10011050U +#define _reg_PHY_SLICE_PWR_RDC_DISABLE 0x18011050U +#define _reg_PHY_PARITY_ERROR_REGIF 0x000b1051U +#define _reg_PHY_DS_FSM_ERROR_INFO 0x100e1051U +#define _reg_PHY_DS_FSM_ERROR_INFO_MASK 0x000e1052U +#define _reg_SC_PHY_DS_FSM_ERROR_INFO_WOCLR 0x100e1052U +#define _reg_PHY_DS_TRAIN_CALIB_ERROR_INFO 0x00051053U +#define _reg_PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK 0x08051053U +#define _reg_SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR 0x10051053U +#define _reg_PHY_DQ_TSEL_ENABLE 0x00031054U +#define _reg_PHY_DQ_TSEL_SELECT 0x08101054U +#define _reg_PHY_DQS_TSEL_ENABLE 0x18031054U +#define _reg_PHY_DQS_TSEL_SELECT 0x00101055U +#define _reg_PHY_TWO_CYC_PREAMBLE 0x10021055U +#define _reg_PHY_VREF_INITIAL_START_POINT 0x18071055U +#define _reg_PHY_VREF_INITIAL_STOP_POINT 0x00071056U +#define _reg_PHY_VREF_TRAINING_CTRL 0x08021056U +#define _reg_PHY_NTP_TRAIN_EN 0x10011056U +#define _reg_PHY_NTP_WDQ_STEP_SIZE 0x18081056U +#define _reg_PHY_NTP_WDQ_START 0x000b1057U +#define _reg_PHY_NTP_WDQ_STOP 0x100b1057U +#define _reg_PHY_NTP_WDQ_BIT_EN 0x00081058U +#define _reg_PHY_WDQLVL_DVW_MIN 0x080a1058U +#define _reg_PHY_SW_WDQLVL_DVW_MIN_EN 0x18011058U +#define _reg_PHY_WDQLVL_PER_START_OFFSET 0x00061059U +#define _reg_PHY_FAST_LVL_EN 0x08041059U +#define _reg_PHY_PAD_TX_DCD 0x10051059U +#define _reg_PHY_PAD_RX_DCD_0 0x18051059U +#define _reg_PHY_PAD_RX_DCD_1 0x0005105aU +#define _reg_PHY_PAD_RX_DCD_2 0x0805105aU +#define _reg_PHY_PAD_RX_DCD_3 0x1005105aU +#define _reg_PHY_PAD_RX_DCD_4 0x1805105aU +#define _reg_PHY_PAD_RX_DCD_5 0x0005105bU +#define _reg_PHY_PAD_RX_DCD_6 0x0805105bU +#define _reg_PHY_PAD_RX_DCD_7 0x1005105bU +#define _reg_PHY_PAD_DM_RX_DCD 0x1805105bU +#define _reg_PHY_PAD_DQS_RX_DCD 0x0005105cU +#define _reg_PHY_PAD_FDBK_RX_DCD 0x0805105cU +#define _reg_PHY_PAD_DSLICE_IO_CFG 0x1006105cU +#define _reg_PHY_RDDQ0_SLAVE_DELAY 0x000a105dU +#define _reg_PHY_RDDQ1_SLAVE_DELAY 0x100a105dU +#define _reg_PHY_RDDQ2_SLAVE_DELAY 0x000a105eU +#define _reg_PHY_RDDQ3_SLAVE_DELAY 0x100a105eU +#define _reg_PHY_RDDQ4_SLAVE_DELAY 0x000a105fU +#define _reg_PHY_RDDQ5_SLAVE_DELAY 0x100a105fU +#define _reg_PHY_RDDQ6_SLAVE_DELAY 0x000a1060U +#define _reg_PHY_RDDQ7_SLAVE_DELAY 0x100a1060U +#define _reg_PHY_RDDM_SLAVE_DELAY 0x000a1061U +#define _reg_PHY_DATA_DC_CAL_CLK_SEL 0x10031061U +#define _reg_PHY_DQ_OE_TIMING 0x00081062U +#define _reg_PHY_DQ_TSEL_RD_TIMING 0x08081062U +#define _reg_PHY_DQ_TSEL_WR_TIMING 0x10081062U +#define _reg_PHY_DQS_OE_TIMING 0x18081062U +#define _reg_PHY_IO_PAD_DELAY_TIMING 0x00041063U +#define _reg_PHY_DQS_TSEL_RD_TIMING 0x08081063U +#define _reg_PHY_DQS_OE_RD_TIMING 0x10081063U +#define _reg_PHY_DQS_TSEL_WR_TIMING 0x18081063U +#define _reg_PHY_VREF_SETTING_TIME 0x00101064U +#define _reg_PHY_PAD_VREF_CTRL_DQ 0x100c1064U +#define _reg_PHY_PER_CS_TRAINING_EN 0x00011065U +#define _reg_PHY_DQ_IE_TIMING 0x08081065U +#define _reg_PHY_DQS_IE_TIMING 0x10081065U +#define _reg_PHY_RDDATA_EN_IE_DLY 0x18021065U +#define _reg_PHY_IE_MODE 0x00021066U +#define _reg_PHY_DBI_MODE 0x08011066U +#define _reg_PHY_RDDATA_EN_TSEL_DLY 0x10051066U +#define _reg_PHY_RDDATA_EN_OE_DLY 0x18051066U +#define _reg_PHY_SW_MASTER_MODE 0x00041067U +#define _reg_PHY_MASTER_DELAY_START 0x080b1067U +#define _reg_PHY_MASTER_DELAY_STEP 0x18061067U +#define _reg_PHY_MASTER_DELAY_WAIT 0x00081068U +#define _reg_PHY_MASTER_DELAY_HALF_MEASURE 0x08081068U +#define _reg_PHY_RPTR_UPDATE 0x10041068U +#define _reg_PHY_WRLVL_DLY_STEP 0x18081068U +#define _reg_PHY_WRLVL_DLY_FINE_STEP 0x00041069U +#define _reg_PHY_WRLVL_RESP_WAIT_CNT 0x08061069U +#define _reg_PHY_GTLVL_DLY_STEP 0x10041069U +#define _reg_PHY_GTLVL_RESP_WAIT_CNT 0x18051069U +#define _reg_PHY_GTLVL_BACK_STEP 0x000a106aU +#define _reg_PHY_GTLVL_FINAL_STEP 0x100a106aU +#define _reg_PHY_WDQLVL_DLY_STEP 0x0008106bU +#define _reg_PHY_WDQLVL_QTR_DLY_STEP 0x0804106bU +#define _reg_PHY_TOGGLE_PRE_SUPPORT 0x1001106bU +#define _reg_PHY_RDLVL_DLY_STEP 0x1804106bU +#define _reg_PHY_RDLVL_MAX_EDGE 0x000a106cU +#define _reg_PHY_RDLVL_DVW_MIN 0x000a106dU +#define _reg_PHY_SW_RDLVL_DVW_MIN_EN 0x1001106dU +#define _reg_PHY_RDLVL_PER_START_OFFSET 0x1806106dU +#define _reg_PHY_WRPATH_GATE_DISABLE 0x0002106eU +#define _reg_PHY_WRPATH_GATE_TIMING 0x0803106eU +#define _reg_PHY_DATA_DC_INIT_DISABLE 0x1002106eU +#define _reg_PHY_DATA_DC_DQS_INIT_SLV_DELAY 0x000a106fU +#define _reg_PHY_DATA_DC_DQ_INIT_SLV_DELAY 0x100b106fU +#define _reg_PHY_DATA_DC_WRLVL_ENABLE 0x00011070U +#define _reg_PHY_DATA_DC_WDQLVL_ENABLE 0x08011070U +#define _reg_PHY_DATA_DC_DM_CLK_SE_THRSHLD 0x10081070U +#define _reg_PHY_DATA_DC_DM_CLK_DIFF_THRSHLD 0x18081070U +#define _reg_PHY_WDQ_OSC_DELTA 0x00071071U +#define _reg_PHY_MEAS_DLY_STEP_ENABLE 0x08061071U +#define _reg_PHY_RDDATA_EN_DLY 0x10051071U +#define _reg_PHY_DQ_DM_SWIZZLE0 0x00201072U +#define _reg_PHY_DQ_DM_SWIZZLE1 0x00041073U +#define _reg_PHY_CLK_WRDQ0_SLAVE_DELAY 0x000b1074U +#define _reg_PHY_CLK_WRDQ1_SLAVE_DELAY 0x100b1074U +#define _reg_PHY_CLK_WRDQ2_SLAVE_DELAY 0x000b1075U +#define _reg_PHY_CLK_WRDQ3_SLAVE_DELAY 0x100b1075U +#define _reg_PHY_CLK_WRDQ4_SLAVE_DELAY 0x000b1076U +#define _reg_PHY_CLK_WRDQ5_SLAVE_DELAY 0x100b1076U +#define _reg_PHY_CLK_WRDQ6_SLAVE_DELAY 0x000b1077U +#define _reg_PHY_CLK_WRDQ7_SLAVE_DELAY 0x100b1077U +#define _reg_PHY_CLK_WRDM_SLAVE_DELAY 0x000b1078U +#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY 0x100a1078U +#define _reg_PHY_WRLVL_THRESHOLD_ADJUST 0x00021079U +#define _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY 0x080a1079U +#define _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY 0x000a107aU +#define _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY 0x100a107aU +#define _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY 0x000a107bU +#define _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY 0x100a107bU +#define _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY 0x000a107cU +#define _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY 0x100a107cU +#define _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY 0x000a107dU +#define _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY 0x100a107dU +#define _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY 0x000a107eU +#define _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY 0x100a107eU +#define _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY 0x000a107fU +#define _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY 0x100a107fU +#define _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY 0x000a1080U +#define _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY 0x100a1080U +#define _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY 0x000a1081U +#define _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY 0x100a1081U +#define _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY 0x000a1082U +#define _reg_PHY_RDDQS_GATE_SLAVE_DELAY 0x100a1082U +#define _reg_PHY_RDDQS_LATENCY_ADJUST 0x00041083U +#define _reg_PHY_WRITE_PATH_LAT_ADD 0x08031083U +#define _reg_PHY_WRLVL_DELAY_EARLY_THRESHOLD 0x100a1083U +#define _reg_PHY_WRLVL_DELAY_PERIOD_THRESHOLD 0x000a1084U +#define _reg_PHY_WRLVL_EARLY_FORCE_ZERO 0x10011084U +#define _reg_PHY_GTLVL_RDDQS_SLV_DLY_START 0x000a1085U +#define _reg_PHY_GTLVL_LAT_ADJ_START 0x10041085U +#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_START 0x000b1086U +#define _reg_PHY_NTP_WRLAT_START 0x10041086U +#define _reg_PHY_NTP_PASS 0x18011086U +#define _reg_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START 0x000a1087U +#define _reg_PHY_DATA_DC_DQS_CLK_ADJUST 0x00081088U +#define _reg_PHY_DATA_DC_DQ0_CLK_ADJUST 0x08081088U +#define _reg_PHY_DATA_DC_DQ1_CLK_ADJUST 0x10081088U +#define _reg_PHY_DATA_DC_DQ2_CLK_ADJUST 0x18081088U +#define _reg_PHY_DATA_DC_DQ3_CLK_ADJUST 0x00081089U +#define _reg_PHY_DATA_DC_DQ4_CLK_ADJUST 0x08081089U +#define _reg_PHY_DATA_DC_DQ5_CLK_ADJUST 0x10081089U +#define _reg_PHY_DATA_DC_DQ6_CLK_ADJUST 0x18081089U +#define _reg_PHY_DATA_DC_DQ7_CLK_ADJUST 0x0008108aU +#define _reg_PHY_DATA_DC_DM_CLK_ADJUST 0x0808108aU +#define _reg_PHY_DSLICE_PAD_BOOSTPN_SETTING 0x1010108aU +#define _reg_PHY_DSLICE_PAD_RX_CTLE_SETTING 0x0006108bU +#define _reg_PHY_DQ_FFE 0x0802108bU +#define _reg_PHY_DQS_FFE 0x1002108bU +#define _reg_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0 0x000b1200U +#define _reg_PHY_ADR_CLK_BYPASS_OVERRIDE_0 0x10011200U +#define _reg_SC_PHY_ADR_MANUAL_CLEAR_0 0x18031200U +#define _reg_PHY_ADR_LPBK_RESULT_OBS_0 0x00201201U +#define _reg_PHY_ADR_LPBK_ERROR_COUNT_OBS_0 0x00101202U +#define _reg_PHY_ADR_MEAS_DLY_STEP_VALUE_0 0x10081202U +#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0 0x18041202U +#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_0 0x000b1203U +#define _reg_PHY_ADR_BASE_SLV_DLY_ENC_OBS_0 0x10071203U +#define _reg_PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0 0x18081203U +#define _reg_PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0 0x00031204U +#define _reg_PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0 0x08031204U +#define _reg_SC_PHY_ADR_SNAP_OBS_REGS_0 0x10011204U +#define _reg_PHY_ADR_TSEL_ENABLE_0 0x18011204U +#define _reg_PHY_ADR_LPBK_CONTROL_0 0x00071205U +#define _reg_PHY_ADR_PRBS_PATTERN_START_0 0x08071205U +#define _reg_PHY_ADR_PRBS_PATTERN_MASK_0 0x10051205U +#define _reg_PHY_ADR_PWR_RDC_DISABLE_0 0x18011205U +#define _reg_PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0 0x00011206U +#define _reg_PHY_ADR_TYPE_0 0x08021206U +#define _reg_PHY_ADR_WRADDR_SHIFT_OBS_0 0x10031206U +#define _reg_PHY_ADR_IE_MODE_0 0x18011206U +#define _reg_PHY_ADR_DDL_MODE_0 0x001b1207U +#define _reg_PHY_ADR_DDL_MASK_0 0x00061208U +#define _reg_PHY_ADR_DDL_TEST_OBS_0 0x00201209U +#define _reg_PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0 0x0020120aU +#define _reg_PHY_ADR_CALVL_START_0 0x000b120bU +#define _reg_PHY_ADR_CALVL_COARSE_DLY_0 0x100b120bU +#define _reg_PHY_ADR_CALVL_QTR_0 0x000b120cU +#define _reg_PHY_ADR_CALVL_SWIZZLE0_0 0x0018120dU +#define _reg_PHY_ADR_CALVL_SWIZZLE1_0 0x0018120eU +#define _reg_PHY_ADR_CALVL_RANK_CTRL_0 0x1802120eU +#define _reg_PHY_ADR_CALVL_NUM_PATTERNS_0 0x0002120fU +#define _reg_PHY_ADR_CALVL_RESP_WAIT_CNT_0 0x0804120fU +#define _reg_PHY_ADR_CALVL_PERIODIC_START_OFFSET_0 0x1009120fU +#define _reg_PHY_ADR_CALVL_DEBUG_MODE_0 0x00011210U +#define _reg_SC_PHY_ADR_CALVL_DEBUG_CONT_0 0x08011210U +#define _reg_SC_PHY_ADR_CALVL_ERROR_CLR_0 0x10011210U +#define _reg_PHY_ADR_CALVL_OBS_SELECT_0 0x18031210U +#define _reg_PHY_ADR_CALVL_CH0_OBS0_0 0x00201211U +#define _reg_PHY_ADR_CALVL_CH1_OBS0_0 0x00201212U +#define _reg_PHY_ADR_CALVL_CH2_OBS0_0 0x00201213U +#define _reg_PHY_ADR_CALVL_CH3_OBS0_0 0x00201214U +#define _reg_PHY_ADR_CALVL_OBS1_0 0x00201215U +#define _reg_PHY_ADR_CALVL_OBS2_0 0x00201216U +#define _reg_PHY_ADR_CALVL_FG_0_0 0x00141217U +#define _reg_PHY_ADR_CALVL_BG_0_0 0x00141218U +#define _reg_PHY_ADR_CALVL_FG_1_0 0x00141219U +#define _reg_PHY_ADR_CALVL_BG_1_0 0x0014121aU +#define _reg_PHY_ADR_CALVL_FG_2_0 0x0014121bU +#define _reg_PHY_ADR_CALVL_BG_2_0 0x0014121cU +#define _reg_PHY_ADR_CALVL_FG_3_0 0x0014121dU +#define _reg_PHY_ADR_CALVL_BG_3_0 0x0014121eU +#define _reg_PHY_ADR_ADDR_SEL_0 0x0018121fU +#define _reg_PHY_ADR_LP4_BOOT_SLV_DELAY_0 0x000a1220U +#define _reg_PHY_ADR_BIT_MASK_0 0x10061220U +#define _reg_PHY_ADR_SEG_MASK_0 0x18061220U +#define _reg_PHY_ADR_CALVL_TRAIN_MASK_0 0x00061221U +#define _reg_PHY_ADR_CSLVL_TRAIN_MASK_0 0x08061221U +#define _reg_PHY_ADR_STATIC_TOG_DISABLE_0 0x10041221U +#define _reg_PHY_ADR_SW_TXIO_CTRL_0 0x18061221U +#define _reg_PHY_ADR_DC_INIT_DISABLE_0 0x00021222U +#define _reg_PHY_ADR_DC_ADR0_CLK_ADJUST_0 0x08081222U +#define _reg_PHY_ADR_DC_ADR1_CLK_ADJUST_0 0x10081222U +#define _reg_PHY_ADR_DC_ADR2_CLK_ADJUST_0 0x18081222U +#define _reg_PHY_ADR_DC_ADR3_CLK_ADJUST_0 0x00081223U +#define _reg_PHY_ADR_DC_ADR4_CLK_ADJUST_0 0x08081223U +#define _reg_PHY_ADR_DC_ADR5_CLK_ADJUST_0 0x10081223U +#define _reg_PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0 0x18011223U +#define _reg_PHY_ADR_DC_CAL_SAMPLE_WAIT_0 0x00081224U +#define _reg_PHY_ADR_DC_CAL_TIMEOUT_0 0x08081224U +#define _reg_PHY_ADR_DC_WEIGHT_0 0x10021224U +#define _reg_PHY_ADR_DC_ADJUST_START_0 0x18061224U +#define _reg_PHY_ADR_DC_ADJUST_SAMPLE_CNT_0 0x00081225U +#define _reg_PHY_ADR_DC_ADJUST_THRSHLD_0 0x08081225U +#define _reg_PHY_ADR_DC_ADJUST_DIRECT_0 0x10011225U +#define _reg_PHY_ADR_DC_CAL_POLARITY_0 0x18011225U +#define _reg_PHY_ADR_DC_CAL_START_0 0x00011226U +#define _reg_PHY_ADR_SW_TXPWR_CTRL_0 0x08061226U +#define _reg_PHY_PARITY_ERROR_REGIF_ADR_0 0x100b1226U +#define _reg_PHY_AS_FSM_ERROR_INFO_0 0x00091227U +#define _reg_PHY_AS_FSM_ERROR_INFO_MASK_0 0x10091227U +#define _reg_SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0 0x00091228U +#define _reg_PHY_AS_TRAIN_CALIB_ERROR_INFO_0 0x10011228U +#define _reg_PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0 0x18011228U +#define _reg_SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0 0x00011229U +#define _reg_PHY_ADR_TSEL_SELECT_0 0x0008122aU +#define _reg_PHY_ADR_DC_CAL_CLK_SEL_0 0x0803122aU +#define _reg_PHY_PAD_ADR_IO_CFG_0 0x100b122aU +#define _reg_PHY_ADR0_SW_WRADDR_SHIFT_0 0x0005122bU +#define _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY_0 0x080b122bU +#define _reg_PHY_ADR1_SW_WRADDR_SHIFT_0 0x1805122bU +#define _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY_0 0x000b122cU +#define _reg_PHY_ADR2_SW_WRADDR_SHIFT_0 0x1005122cU +#define _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY_0 0x000b122dU +#define _reg_PHY_ADR3_SW_WRADDR_SHIFT_0 0x1005122dU +#define _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY_0 0x000b122eU +#define _reg_PHY_ADR4_SW_WRADDR_SHIFT_0 0x1005122eU +#define _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY_0 0x000b122fU +#define _reg_PHY_ADR5_SW_WRADDR_SHIFT_0 0x1005122fU +#define _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY_0 0x000b1230U +#define _reg_PHY_ADR_SW_MASTER_MODE_0 0x10041230U +#define _reg_PHY_ADR_MASTER_DELAY_START_0 0x000b1231U +#define _reg_PHY_ADR_MASTER_DELAY_STEP_0 0x10061231U +#define _reg_PHY_ADR_MASTER_DELAY_WAIT_0 0x18081231U +#define _reg_PHY_ADR_MASTER_DELAY_HALF_MEASURE_0 0x00081232U +#define _reg_PHY_ADR_SW_CALVL_DVW_MIN_0 0x080a1232U +#define _reg_PHY_ADR_SW_CALVL_DVW_MIN_EN_0 0x18011232U +#define _reg_PHY_ADR_CALVL_DLY_STEP_0 0x00041233U +#define _reg_PHY_ADR_CALVL_CAPTURE_CNT_0 0x00041234U +#define _reg_PHY_ADR_MEAS_DLY_STEP_ENABLE_0 0x08011234U +#define _reg_PHY_ADR_DC_INIT_SLV_DELAY_0 0x100a1234U +#define _reg_PHY_ADR_DC_CALVL_ENABLE_0 0x00011235U +#define _reg_PHY_ADR_DC_DM_CLK_THRSHLD_0 0x08081235U +#define _reg_PHY_FREQ_SEL 0x00031300U +#define _reg_PHY_FREQ_SEL_FROM_REGIF 0x00011301U +#define _reg_PHY_FREQ_SEL_MULTICAST_EN 0x08011301U +#define _reg_PHY_FREQ_SEL_INDEX 0x10021301U +#define _reg_PHY_SW_GRP0_SHIFT_0 0x18051301U +#define _reg_PHY_SW_GRP1_SHIFT_0 0x00051302U +#define _reg_PHY_SW_GRP2_SHIFT_0 0x08051302U +#define _reg_PHY_SW_GRP3_SHIFT_0 0x10051302U +#define _reg_PHY_SW_GRP0_SHIFT_1 0x18051302U +#define _reg_PHY_SW_GRP1_SHIFT_1 0x00051303U +#define _reg_PHY_SW_GRP2_SHIFT_1 0x08051303U +#define _reg_PHY_SW_GRP3_SHIFT_1 0x10051303U +#define _reg_PHY_GRP_BYPASS_SLAVE_DELAY 0x000b1304U +#define _reg_PHY_SW_GRP_BYPASS_SHIFT 0x10051304U +#define _reg_PHY_GRP_BYPASS_OVERRIDE 0x18011304U +#define _reg_SC_PHY_MANUAL_UPDATE 0x00011305U +#define _reg_PHY_MANUAL_UPDATE_PHYUPD_ENABLE 0x08011305U +#define _reg_PHY_CSLVL_START 0x100b1305U +#define _reg_PHY_CSLVL_COARSE_DLY 0x000b1306U +#define _reg_PHY_CSLVL_DEBUG_MODE 0x10011306U +#define _reg_SC_PHY_CSLVL_DEBUG_CONT 0x18011306U +#define _reg_SC_PHY_CSLVL_ERROR_CLR 0x00011307U +#define _reg_PHY_CSLVL_OBS0 0x00201308U +#define _reg_PHY_CSLVL_OBS1 0x00201309U +#define _reg_PHY_CSLVL_OBS2 0x0020130aU +#define _reg_PHY_CSLVL_ENABLE 0x0001130bU +#define _reg_PHY_CSLVL_PERIODIC_START_OFFSET 0x0809130bU +#define _reg_PHY_LP4_BOOT_DISABLE 0x1801130bU +#define _reg_PHY_CSLVL_CS_MAP 0x0002130cU +#define _reg_PHY_CSLVL_QTR 0x080b130cU +#define _reg_PHY_CSLVL_COARSE_CHK 0x000b130dU +#define _reg_PHY_CSLVL_COARSE_CAPTURE_CNT 0x1004130dU +#define _reg_PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE 0x1803130dU +#define _reg_PHY_ADRCTL_SNAP_OBS_REGS 0x0001130eU +#define _reg_PHY_DFI_PHYUPD_TYPE 0x0802130eU +#define _reg_PHY_ADRCTL_LPDDR 0x1001130eU +#define _reg_PHY_LP4_ACTIVE 0x1801130eU +#define _reg_PHY_LPDDR3_CS 0x0001130fU +#define _reg_PHY_CLK_DC_CAL_SAMPLE_WAIT 0x0808130fU +#define _reg_PHY_CLK_DC_CAL_TIMEOUT 0x1008130fU +#define _reg_PHY_CLK_DC_WEIGHT 0x1802130fU +#define _reg_PHY_CLK_DC_FREQ_CHG_ADJ 0x00011310U +#define _reg_PHY_CLK_DC_ADJUST_START 0x08061310U +#define _reg_PHY_CLK_DC_ADJUST_SAMPLE_CNT 0x10081310U +#define _reg_PHY_CLK_DC_ADJUST_THRSHLD 0x18081310U +#define _reg_PHY_CLK_DC_ADJUST_DIRECT 0x00011311U +#define _reg_PHY_CLK_DC_CAL_POLARITY 0x08011311U +#define _reg_PHY_CLK_DC_CAL_START 0x10011311U +#define _reg_SC_PHY_UPDATE_CLK_CAL_VALUES 0x18011311U +#define _reg_PHY_CONTINUOUS_CLK_CAL_UPDATE 0x00011312U +#define _reg_PHY_SW_TXIO_CTRL_0 0x08041312U +#define _reg_PHY_SW_TXIO_CTRL_1 0x10041312U +#define _reg_PHY_MEMCLK_SW_TXIO_CTRL 0x18011312U +#define _reg_PHY_ADRCTL_SW_TXPWR_CTRL_0 0x00041313U +#define _reg_PHY_ADRCTL_SW_TXPWR_CTRL_1 0x08041313U +#define _reg_PHY_MEMCLK_SW_TXPWR_CTRL 0x10011313U +#define _reg_PHY_USER_DEF_REG_AC_0 0x00201314U +#define _reg_PHY_USER_DEF_REG_AC_1 0x00201315U +#define _reg_PHY_USER_DEF_REG_AC_2 0x00201316U +#define _reg_PHY_USER_DEF_REG_AC_3 0x00201317U +#define _reg_PHY_TOP_STATIC_TOG_DISABLE 0x00011318U +#define _reg_PHY_BYTE_DISABLE_STATIC_TOG_DISABLE 0x08011318U +#define _reg_PHY_STATIC_TOG_CONTROL 0x10101318U +#define _reg_PHY_ADRCTL_STATIC_TOG_DISABLE 0x00041319U +#define _reg_PHY_MEMCLK_STATIC_TOG_DISABLE 0x08011319U +#define _reg_PHY_LP4_BOOT_PLL_BYPASS 0x10011319U +#define _reg_PHY_CLK_SWITCH_OBS 0x0020131aU +#define _reg_PHY_PLL_WAIT 0x0010131bU +#define _reg_PHY_SW_PLL_BYPASS 0x0001131cU +#define _reg_PHY_SET_DFI_INPUT_RST_PAD 0x0001131dU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT0_0 0x0802131dU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT1_0 0x1002131dU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT2_0 0x1802131dU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT3_0 0x0002131eU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT0_1 0x0802131eU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT1_1 0x1002131eU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT2_1 0x1802131eU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT3_1 0x0002131fU +#define _reg_PHY_CLK_DC_ADJUST_0 0x0808131fU +#define _reg_PHY_CLK_DC_INIT_DISABLE 0x1001131fU +#define _reg_PHY_CLK_DC_DM_THRSHLD 0x1808131fU +#define _reg_PHY_LP4_BOOT_PLL_CTRL 0x000d1320U +#define _reg_PHY_PLL_CTRL_OVERRIDE 0x10101320U +#define _reg_PHY_USE_PLL_DSKEWCALLOCK 0x00011321U +#define _reg_PHY_PLL_SPO_CAL_CTRL 0x08131321U +#define _reg_SC_PHY_PLL_SPO_CAL_SNAP_OBS 0x00021322U +#define _reg_PHY_PLL_OBS_0 0x08101322U +#define _reg_PHY_PLL_SPO_CAL_OBS_0 0x00111323U +#define _reg_PHY_PLL_OBS_1 0x00101324U +#define _reg_PHY_PLL_SPO_CAL_OBS_1 0x00111325U +#define _reg_PHY_PLL_TESTOUT_SEL 0x18011325U +#define _reg_PHY_LP4_BOOT_LOW_FREQ_SEL 0x00011326U +#define _reg_PHY_TCKSRE_WAIT 0x08041326U +#define _reg_PHY_LP_WAKEUP 0x10081326U +#define _reg_PHY_LS_IDLE_EN 0x18011326U +#define _reg_PHY_LP_CTRLUPD_CNTR_CFG 0x000a1327U +#define _reg_PHY_TDFI_PHY_WRDELAY 0x10011327U +#define _reg_PHY_PAD_FDBK_TERM 0x00121328U +#define _reg_PHY_PAD_DATA_TERM 0x00111329U +#define _reg_PHY_PAD_DQS_TERM 0x0011132aU +#define _reg_PHY_PAD_ADDR_TERM 0x0012132bU +#define _reg_PHY_PAD_CLK_TERM 0x0012132cU +#define _reg_PHY_PAD_CKE_TERM 0x0012132dU +#define _reg_PHY_PAD_RST_TERM 0x0012132eU +#define _reg_PHY_PAD_CS_TERM 0x0012132fU +#define _reg_PHY_PAD_ODT_TERM 0x00121330U +#define _reg_PHY_ADRCTL_RX_CAL 0x000a1331U +#define _reg_PHY_ADRCTL_LP3_RX_CAL 0x100d1331U +#define _reg_PHY_TST_CLK_PAD_CTRL 0x00201332U +#define _reg_PHY_TST_CLK_PAD_CTRL2 0x00171333U +#define _reg_PHY_TST_CLK_PAD_CTRL3 0x00171334U +#define _reg_PHY_TST_CLK_PAD_CTRL4 0x001b1335U +#define _reg_PHY_CAL_MODE_0 0x000d1336U +#define _reg_PHY_CAL_CLEAR_0 0x10011336U +#define _reg_PHY_CAL_START_0 0x18011336U +#define _reg_PHY_CAL_INTERVAL_COUNT_0 0x00201337U +#define _reg_PHY_CAL_SAMPLE_WAIT_0 0x00081338U +#define _reg_PHY_LP4_BOOT_CAL_CLK_SELECT_0 0x08031338U +#define _reg_PHY_CAL_RESULT_OBS_0 0x00181339U +#define _reg_PHY_CAL_RESULT2_OBS_0 0x0018133aU +#define _reg_PHY_CAL_RESULT4_OBS_0 0x0018133bU +#define _reg_PHY_CAL_RESULT5_OBS_0 0x0018133cU +#define _reg_PHY_CAL_RESULT6_OBS_0 0x0018133dU +#define _reg_PHY_CAL_RESULT7_OBS_0 0x0018133eU +#define _reg_PHY_CAL_CPTR_CNT_0 0x1807133eU +#define _reg_PHY_CAL_PU_FINE_ADJ_0 0x0008133fU +#define _reg_PHY_CAL_PD_FINE_ADJ_0 0x0808133fU +#define _reg_PHY_CAL_RCV_FINE_ADJ_0 0x1008133fU +#define _reg_PHY_CAL_DBG_CFG_0 0x1801133fU +#define _reg_SC_PHY_PAD_DBG_CONT_0 0x00011340U +#define _reg_PHY_CAL_RESULT3_OBS_0 0x00201341U +#define _reg_PHY_ADRCTL_PVT_MAP_0 0x00071342U +#define _reg_PHY_CAL_SLOPE_ADJ_0 0x08141342U +#define _reg_PHY_CAL_SLOPE_ADJ_PASS2_0 0x00141343U +#define _reg_PHY_CAL_TWO_PASS_CFG_0 0x00191344U +#define _reg_PHY_CAL_SW_CAL_CFG_0 0x00171345U +#define _reg_PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0 0x18061345U +#define _reg_PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0 0x00061346U +#define _reg_PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0 0x08051346U +#define _reg_PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0 0x10061346U +#define _reg_PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0 0x18061346U +#define _reg_PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0 0x00051347U +#define _reg_PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0 0x08061347U +#define _reg_PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0 0x10061347U +#define _reg_PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0 0x18051347U +#define _reg_PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0 0x00061348U +#define _reg_PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0 0x08061348U +#define _reg_PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0 0x10051348U +#define _reg_PHY_PAD_ATB_CTRL 0x00101349U +#define _reg_PHY_PARITY_ERROR_REGIF_AC 0x100b1349U +#define _reg_PHY_ADRCTL_MANUAL_UPDATE 0x0001134aU +#define _reg_PHY_AC_LPBK_ERR_CLEAR 0x0801134aU +#define _reg_PHY_AC_LPBK_OBS_SELECT 0x1001134aU +#define _reg_PHY_AC_LPBK_ENABLE 0x1802134aU +#define _reg_PHY_AC_LPBK_CONTROL 0x0009134bU +#define _reg_PHY_AC_PRBS_PATTERN_START 0x1007134bU +#define _reg_PHY_AC_PRBS_PATTERN_MASK 0x1804134bU +#define _reg_PHY_AC_LPBK_RESULT_OBS 0x0020134cU +#define _reg_PHY_AC_CLK_LPBK_OBS_SELECT 0x0001134dU +#define _reg_PHY_AC_CLK_LPBK_ENABLE 0x0801134dU +#define _reg_PHY_AC_CLK_LPBK_CONTROL 0x1006134dU +#define _reg_PHY_AC_CLK_LPBK_RESULT_OBS 0x0010134eU +#define _reg_PHY_AC_PWR_RDC_DISABLE 0x1001134eU +#define _reg_PHY_TOP_PWR_RDC_DISABLE 0x1801134eU +#define _reg_PHY_AC_SLV_DLY_CTRL_GATE_DISABLE 0x0001134fU +#define _reg_PHY_CALVL_DEVICE_MAP 0x0805134fU +#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL_0 0x1002134fU +#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL_1 0x1802134fU +#define _reg_PHY_DDL_AC_ENABLE 0x00201350U +#define _reg_PHY_DDL_AC_MODE 0x001a1351U +#define _reg_PHY_DDL_AC_MASK 0x00061352U +#define _reg_PHY_INIT_UPDATE_CONFIG 0x08031352U +#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD_AC 0x10081352U +#define _reg_PHY_ERR_MASK_EN 0x18031352U +#define _reg_PHY_ERR_STATUS 0x00031353U +#define _reg_PHY_DS0_DQS_ERR_COUNTER 0x00201354U +#define _reg_PHY_DS1_DQS_ERR_COUNTER 0x00201355U +#define _reg_PHY_DLL_RST_EN 0x00021356U +#define _reg_PHY_AC_INIT_COMPLETE_OBS 0x080a1356U +#define _reg_PHY_DS_INIT_COMPLETE_OBS 0x18021356U +#define _reg_PHY_UPDATE_MASK 0x00011357U +#define _reg_PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE 0x08011357U +#define _reg_PHY_GRP_SLV_DLY_ENC_OBS_SELECT 0x10041357U +#define _reg_PHY_GRP_SHIFT_OBS_SELECT 0x18031357U +#define _reg_PHY_GRP_SLV_DLY_ENC_OBS 0x000b1358U +#define _reg_PHY_GRP_SHIFT_OBS 0x10031358U +#define _reg_PHY_PARITY_ERROR_INJECTION_ENABLE 0x00011359U +#define _reg_PHY_PARITY_ERROR_REGIF_PS 0x080b1359U +#define _reg_PHY_PLL_LOCK_DEASSERT_MASK 0x18031359U +#define _reg_PHY_PARITY_ERROR_INFO 0x0005135aU +#define _reg_PHY_PARITY_ERROR_INFO_MASK 0x0805135aU +#define _reg_SC_PHY_PARITY_ERROR_INFO_WOCLR 0x1005135aU +#define _reg_PHY_TIMEOUT_ERROR_INFO 0x000e135bU +#define _reg_PHY_TIMEOUT_ERROR_INFO_MASK 0x100e135bU +#define _reg_SC_PHY_TIMEOUT_ERROR_INFO_WOCLR 0x000e135cU +#define _reg_PHY_PLL_FREQUENCY_ERROR 0x1004135cU +#define _reg_PHY_PLL_FREQUENCY_ERROR_MASK 0x1806135cU +#define _reg_SC_PHY_PLL_FREQUENCY_ERROR_WOCLR 0x0006135dU +#define _reg_PHY_PLL_DSKEWCALOUT_MIN 0x080c135dU +#define _reg_PHY_PLL_DSKEWCALOUT_MAX 0x000c135eU +#define _reg_PHY_PLL_DSKEWCALOUT_ERROR_INFO 0x1002135eU +#define _reg_PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK 0x1802135eU +#define _reg_SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR 0x0002135fU +#define _reg_PHY_TOP_FSM_ERROR_INFO 0x0809135fU +#define _reg_PHY_TOP_FSM_ERROR_INFO_MASK 0x00091360U +#define _reg_SC_PHY_TOP_FSM_ERROR_INFO_WOCLR 0x10091360U +#define _reg_PHY_FSM_TRANSIENT_ERROR_INFO 0x00081361U +#define _reg_PHY_FSM_TRANSIENT_ERROR_INFO_MASK 0x08081361U +#define _reg_SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR 0x10081361U +#define _reg_PHY_TOP_TRAIN_CALIB_ERROR_INFO 0x18021361U +#define _reg_PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK 0x00021362U +#define _reg_SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR 0x08021362U +#define _reg_PHY_TRAIN_CALIB_ERROR_INFO 0x10051362U +#define _reg_PHY_TRAIN_CALIB_ERROR_INFO_MASK 0x18051362U +#define _reg_SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR 0x00051363U +#define _reg_PHY_GLOBAL_ERROR_INFO 0x08061363U +#define _reg_PHY_GLOBAL_ERROR_INFO_MASK 0x10061363U +#define _reg_PHY_TRAINING_TIMEOUT_VALUE 0x00141364U +#define _reg_PHY_INIT_TIMEOUT_VALUE 0x00141365U +#define _reg_PHY_LP_TIMEOUT_VALUE 0x00101366U +#define _reg_PHY_PHYUPD_TIMEOUT_VALUE 0x00201367U +#define _reg_PHY_PHYMSTR_TIMEOUT_VALUE 0x00141368U +#define _reg_PHY_PLL_LOCK_0_MIN_VALUE 0x18051368U +#define _reg_PHY_PLL_LOCK_TIMEOUT_VALUE 0x00101369U +#define _reg_PHY_RDDATA_VALID_TIMEOUT_VALUE 0x10081369U +#define _reg_PHY_PLL_FREQUENCY_DELTA 0x18041369U +#define _reg_PHY_PLL_FREQUENCY_COMPARE_INTERVAL 0x0010136aU +#define _reg_PHY_ADRCTL_FSM_ERROR_INFO_0 0x100e136aU +#define _reg_PHY_ADRCTL_FSM_ERROR_INFO_MASK_0 0x000e136bU +#define _reg_SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0 0x100e136bU +#define _reg_PHY_ADRCTL_FSM_ERROR_INFO_1 0x000e136cU +#define _reg_PHY_ADRCTL_FSM_ERROR_INFO_MASK_1 0x100e136cU +#define _reg_SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1 0x000e136dU +#define _reg_PHY_MEMCLK_FSM_ERROR_INFO_0 0x100e136dU +#define _reg_PHY_MEMCLK_FSM_ERROR_INFO_MASK_0 0x000e136eU +#define _reg_SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0 0x100e136eU +#define _reg_PHY_PAD_CAL_IO_CFG_0 0x0012136fU +#define _reg_PHY_PAD_ACS_IO_CFG 0x000d1370U +#define _reg_PHY_PLL_BYPASS 0x00011371U +#define _reg_PHY_PLL_CTRL 0x000d1372U +#define _reg_PHY_LOW_FREQ_SEL 0x10011372U +#define _reg_PHY_PAD_VREF_CTRL_AC 0x000c1373U +#define _reg_PHY_CSLVL_CAPTURE_CNT 0x10041373U +#define _reg_PHY_CSLVL_DLY_STEP 0x18041373U +#define _reg_PHY_SW_CSLVL_DVW_MIN 0x00091374U +#define _reg_PHY_SW_CSLVL_DVW_MIN_EN 0x10011374U +#define _reg_PHY_LVL_MEAS_DLY_STEP_ENABLE 0x18011374U +#define _reg_PHY_GRP0_SLAVE_DELAY_0 0x000b1375U +#define _reg_PHY_GRP1_SLAVE_DELAY_0 0x100b1375U +#define _reg_PHY_GRP2_SLAVE_DELAY_0 0x000b1376U +#define _reg_PHY_GRP3_SLAVE_DELAY_0 0x100b1376U +#define _reg_PHY_GRP0_SLAVE_DELAY_1 0x000b1377U +#define _reg_PHY_GRP1_SLAVE_DELAY_1 0x000b1378U +#define _reg_PHY_GRP2_SLAVE_DELAY_1 0x000b1379U +#define _reg_PHY_GRP3_SLAVE_DELAY_1 0x000b137aU +#define _reg_PHY_CLK_DC_CAL_CLK_SEL 0x0003137bU +#define _reg_PHY_PAD_FDBK_DRIVE 0x001e137cU +#define _reg_PHY_PAD_FDBK_DRIVE2 0x0013137dU +#define _reg_PHY_PAD_DATA_DRIVE 0x001f137eU +#define _reg_PHY_PAD_DATA_DRIVE2 0x0001137fU +#define _reg_PHY_PAD_DQS_DRIVE 0x00201380U +#define _reg_PHY_PAD_DQS_DRIVE2 0x00011381U +#define _reg_PHY_PAD_ADDR_DRIVE 0x001e1382U +#define _reg_PHY_PAD_ADDR_DRIVE2 0x001c1383U +#define _reg_PHY_PAD_CLK_DRIVE 0x00201384U +#define _reg_PHY_PAD_CLK_DRIVE2 0x00131385U +#define _reg_PHY_PAD_CKE_DRIVE 0x001e1386U +#define _reg_PHY_PAD_CKE_DRIVE2 0x001c1387U +#define _reg_PHY_PAD_RST_DRIVE 0x001e1388U +#define _reg_PHY_PAD_RST_DRIVE2 0x001c1389U +#define _reg_PHY_PAD_CS_DRIVE 0x001e138aU +#define _reg_PHY_PAD_CS_DRIVE2 0x001c138bU +#define _reg_PHY_PAD_ODT_DRIVE 0x001e138cU +#define _reg_PHY_PAD_ODT_DRIVE2 0x001c138dU +#define _reg_PHY_CAL_CLK_SELECT_0 0x0003138eU +#define _reg_PHY_CAL_VREF_SWITCH_TIMER_0 0x0810138eU +#define _reg_PHY_CAL_SETTLING_PRD_0 0x1807138eU +#define _reg_PI_START 0x00010800U +#define _reg_PI_DRAM_CLASS 0x08040800U +#define _reg_PI_VERSION 0x00200801U +#define _reg_PI_ID 0x00100802U +#define _reg_PI_NORMAL_LVL_SEQ 0x00010803U +#define _reg_PI_INIT_LVL_EN 0x08010803U +#define _reg_PI_NOTCARE_PHYUPD 0x10010803U +#define _reg_PI_TCMD_GAP 0x00100804U +#define _reg_RESERVED_R0 0x10080804U +#define _reg_PI_TRAIN_ALL_FREQ_REQ 0x18010804U +#define _reg_PI_DFI_VERSION 0x00010805U +#define _reg_PI_DFI_PHYMSTR_TYPE 0x08020805U +#define _reg_PI_DFI_PHYMSTR_CS_STATE_R 0x10010805U +#define _reg_PI_DFI_PHYMSTR_STATE_SEL_R 0x18010805U +#define _reg_PI_TDFI_PHYMSTR_MAX 0x00200806U +#define _reg_PI_TDFI_PHYMSTR_RESP 0x00140807U +#define _reg_PI_TDFI_PHYUPD_RESP 0x00140808U +#define _reg_PI_TDFI_PHYUPD_MAX 0x00200809U +#define _reg_PI_FREQ_MAP 0x0020080aU +#define _reg_PI_INIT_WORK_FREQ 0x0005080bU +#define _reg_PI_INIT_DFS_CALVL_ONLY 0x0801080bU +#define _reg_PI_SW_RST_N 0x1001080bU +#define _reg_RESERVED_V3U 0x1801080bU +#define _reg_PI_CS_MAP 0x0002080cU +#define _reg_PI_RANK_NUM_PER_CKE 0x0805080cU +#define _reg_PI_SRX_LVL_TARGET_CS_EN 0x1001080cU +#define _reg_PI_TMRR 0x1804080cU +#define _reg_PI_PREAMBLE_SUPPORT 0x0002080dU +#define _reg_PI_MCAREF_FORWARD_ONLY 0x0801080dU +#define _reg_PI_WRLVL_MRR_DQ_RETURN_HIZ 0x1001080dU +#define _reg_PI_ON_DFIBUS 0x1801080dU +#define _reg_PI_SWLVL_LOAD 0x0001080eU +#define _reg_PI_SWLVL_OP_DONE 0x0801080eU +#define _reg_PI_SW_WRLVL_RESP_0 0x1001080eU +#define _reg_PI_SW_WRLVL_RESP_1 0x1801080eU +#define _reg_PI_SW_RDLVL_RESP_0 0x0002080fU +#define _reg_PI_SW_RDLVL_RESP_1 0x0802080fU +#define _reg_PI_SW_CALVL_RESP_0 0x1002080fU +#define _reg_PI_SW_LEVELING_MODE 0x1803080fU +#define _reg_PI_SWLVL_START 0x00010810U +#define _reg_PI_SWLVL_EXIT 0x08010810U +#define _reg_PI_SWLVL_WR_SLICE_0 0x10010810U +#define _reg_PI_SWLVL_RD_SLICE_0 0x18010810U +#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_0 0x00010811U +#define _reg_PI_SW_WDQLVL_RESP_0 0x08020811U +#define _reg_PI_SWLVL_WR_SLICE_1 0x10010811U +#define _reg_PI_SWLVL_RD_SLICE_1 0x18010811U +#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_1 0x00010812U +#define _reg_PI_SW_WDQLVL_RESP_1 0x08020812U +#define _reg_PI_SWLVL_SM2_START 0x10010812U +#define _reg_PI_SWLVL_SM2_WR 0x18010812U +#define _reg_PI_SWLVL_SM2_RD 0x00010813U +#define _reg_PI_SEQUENTIAL_LVL_REQ 0x08010813U +#define _reg_PI_DFS_PERIOD_EN 0x10010813U +#define _reg_PI_SRE_PERIOD_EN 0x18010813U +#define _reg_PI_DFI40_POLARITY 0x00010814U +#define _reg_PI_WRLVL_REQ 0x08010814U +#define _reg_PI_WRLVL_CS 0x10010814U +#define _reg_PI_WLDQSEN 0x18060814U +#define _reg_PI_WLMRD 0x00060815U +#define _reg_PI_WRLVL_INTERVAL 0x08100815U +#define _reg_PI_WRLVL_PERIODIC 0x18010815U +#define _reg_PI_WRLVL_ON_SREF_EXIT 0x00010816U +#define _reg_PI_WRLVL_DISABLE_DFS 0x08010816U +#define _reg_PI_WRLVL_RESP_MASK 0x10020816U +#define _reg_PI_WRLVL_ROTATE 0x18010816U +#define _reg_PI_WRLVL_CS_MAP 0x00020817U +#define _reg_PI_WRLVL_ERROR_STATUS 0x08010817U +#define _reg_PI_TDFI_WRLVL_EN 0x10080817U +#define _reg_PI_TDFI_WRLVL_RESP 0x00200818U +#define _reg_PI_TDFI_WRLVL_MAX 0x00200819U +#define _reg_PI_WRLVL_STROBE_NUM 0x0005081aU +#define _reg_PI_TODTH_WR 0x0804081aU +#define _reg_PI_TODTH_RD 0x1004081aU +#define _reg_PI_ODT_VALUE 0x1802081aU +#define _reg_PI_RDLVL_REQ 0x0001081bU +#define _reg_PI_RDLVL_GATE_REQ 0x0801081bU +#define _reg_PI_RDLVL_CS 0x1001081bU +#define _reg_PI_RDLVL_PAT_0 0x0020081cU +#define _reg_PI_RDLVL_PAT_1 0x0020081dU +#define _reg_PI_RDLVL_PAT_2 0x0020081eU +#define _reg_PI_RDLVL_PAT_3 0x0020081fU +#define _reg_PI_RDLVL_PAT_4 0x00200820U +#define _reg_PI_RDLVL_PAT_5 0x00200821U +#define _reg_PI_RDLVL_PAT_6 0x00200822U +#define _reg_PI_RDLVL_PAT_7 0x00200823U +#define _reg_PI_RDLVL_SEQ_EN 0x00040824U +#define _reg_PI_RDLVL_PERIODIC 0x08010824U +#define _reg_PI_RDLVL_ON_SREF_EXIT 0x10010824U +#define _reg_PI_RDLVL_DISABLE_DFS 0x18010824U +#define _reg_PI_RDLVL_GATE_PERIODIC 0x00010825U +#define _reg_PI_RDLVL_GATE_ON_SREF_EXIT 0x08010825U +#define _reg_PI_RDLVL_GATE_DISABLE_DFS 0x10010825U +#define _reg_PI_RDLVL_ROTATE 0x18010825U +#define _reg_PI_RDLVL_GATE_ROTATE 0x00010826U +#define _reg_PI_RDLVL_CS_MAP 0x08020826U +#define _reg_PI_RDLVL_GATE_CS_MAP 0x10020826U +#define _reg_PI_TDFI_RDLVL_RR 0x000a0827U +#define _reg_PI_TDFI_RDLVL_RESP 0x00200828U +#define _reg_PI_RDLVL_RESP_MASK 0x00020829U +#define _reg_PI_TDFI_RDLVL_EN 0x08080829U +#define _reg_PI_TDFI_RDLVL_MAX 0x0020082aU +#define _reg_PI_RDLVL_ERROR_STATUS 0x0001082bU +#define _reg_PI_RDLVL_INTERVAL 0x0810082bU +#define _reg_PI_RDLVL_GATE_INTERVAL 0x0010082cU +#define _reg_PI_RDLVL_PATTERN_START 0x1004082cU +#define _reg_PI_RDLVL_PATTERN_NUM 0x1804082cU +#define _reg_PI_RDLVL_STROBE_NUM 0x0005082dU +#define _reg_PI_RDLVL_GATE_STROBE_NUM 0x0805082dU +#define _reg_PI_RD_PREAMBLE_TRAINING_EN 0x1001082dU +#define _reg_PI_REG_DIMM_ENABLE 0x1801082dU +#define _reg_PI_TDFI_RDDATA_EN 0x0007082eU +#define _reg_PI_TDFI_PHY_WRLAT 0x0807082eU +#define _reg_PI_CALVL_REQ 0x1001082eU +#define _reg_PI_CALVL_CS 0x1801082eU +#define _reg_PI_WRLVL_EN_DEASSERT_2_MRR 0x0001082fU +#define _reg_RESERVED_R1 0x0804082fU +#define _reg_PI_CALVL_SEQ_EN 0x1002082fU +#define _reg_PI_CALVL_PERIODIC 0x1801082fU +#define _reg_PI_CALVL_ON_SREF_EXIT 0x00010830U +#define _reg_PI_CALVL_DISABLE_DFS 0x08010830U +#define _reg_PI_CALVL_ROTATE 0x10010830U +#define _reg_PI_CALVL_CS_MAP 0x18020830U +#define _reg_PI_TDFI_CALVL_EN 0x00080831U +#define _reg_PI_TDFI_CALVL_RESP 0x00200832U +#define _reg_PI_TDFI_CALVL_MAX 0x00200833U +#define _reg_PI_CALVL_RESP_MASK 0x00010834U +#define _reg_PI_CALVL_ERROR_STATUS 0x08020834U +#define _reg_PI_CALVL_INTERVAL 0x10100834U +#define _reg_PI_TCACKEL 0x00050835U +#define _reg_PI_TCAMRD 0x08060835U +#define _reg_PI_TCACKEH 0x10050835U +#define _reg_PI_TCAEXT 0x18050835U +#define _reg_PI_CA_TRAIN_VREF_EN 0x00010836U +#define _reg_PI_CALVL_VREF_INITIAL_STEPSIZE 0x08040836U +#define _reg_PI_CALVL_VREF_NORMAL_STEPSIZE 0x10040836U +#define _reg_PI_TDFI_INIT_START_MIN 0x18080836U +#define _reg_PI_TDFI_INIT_COMPLETE_MIN 0x00080837U +#define _reg_PI_TCKCKEH 0x08040837U +#define _reg_PI_CALVL_STROBE_NUM 0x10050837U +#define _reg_PI_SW_CA_TRAIN_VREF 0x18070837U +#define _reg_PI_CLKDISABLE_2_INIT_START 0x00080838U +#define _reg_PI_INIT_STARTORCOMPLETE_2_CLKDISABLE 0x08080838U +#define _reg_PI_DRAM_CLK_DISABLE_DEASSERT_SEL 0x10010838U +#define _reg_PI_REFRESH_BETWEEN_SEGMENT_DISABLE 0x18010838U +#define _reg_PI_MC_DFS_PI_SET_VREF_ENABLE 0x00010839U +#define _reg_PI_FSM_ERROR_INFO_MASK 0x080d0839U +#define _reg_PI_SC_FSM_ERROR_INFO_WOCLR 0x000d083aU +#define _reg_PI_FSM_ERROR_INFO 0x100d083aU +#define _reg_PI_WDQLVL_VREF_EN 0x0001083bU +#define _reg_PI_WDQLVL_BST_NUM 0x0803083bU +#define _reg_PI_WDQLVL_RESP_MASK 0x1002083bU +#define _reg_PI_WDQLVL_ROTATE 0x1801083bU +#define _reg_PI_WDQLVL_CS_MAP 0x0002083cU +#define _reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE 0x0805083cU +#define _reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE 0x1005083cU +#define _reg_PI_WDQLVL_PERIODIC 0x1801083cU +#define _reg_PI_WDQLVL_REQ 0x0001083dU +#define _reg_PI_WDQLVL_CS 0x0801083dU +#define _reg_PI_TDFI_WDQLVL_EN 0x1008083dU +#define _reg_PI_TDFI_WDQLVL_RESP 0x0020083eU +#define _reg_PI_TDFI_WDQLVL_MAX 0x0020083fU +#define _reg_PI_WDQLVL_INTERVAL 0x00100840U +#define _reg_PI_WDQLVL_ON_SREF_EXIT 0x10010840U +#define _reg_PI_WDQLVL_DISABLE_DFS 0x18010840U +#define _reg_PI_WDQLVL_ERROR_STATUS 0x00020841U +#define _reg_PI_WDQLVL_OSC_EN 0x08010841U +#define _reg_PI_DQS_OSC_PERIOD_EN 0x10010841U +#define _reg_PI_BANK_DIFF 0x18020841U +#define _reg_PI_ROW_DIFF 0x00030842U +#define _reg_PI_TCCD 0x08050842U +#define _reg_RESERVED_R2 0x10040842U +#define _reg_RESERVED_R3 0x18040842U +#define _reg_RESERVED_R4 0x00040843U +#define _reg_RESERVED_R5 0x08040843U +#define _reg_RESERVED_R6 0x10040843U +#define _reg_RESERVED_R7 0x18040843U +#define _reg_RESERVED_R8 0x00040844U +#define _reg_RESERVED_R9 0x08040844U +#define _reg_RESERVED_R10 0x10040844U +#define _reg_RESERVED_R11 0x18040844U +#define _reg_RESERVED_R12 0x00040845U +#define _reg_RESERVED_R13 0x08040845U +#define _reg_RESERVED_R14 0x10040845U +#define _reg_RESERVED_R15 0x18040845U +#define _reg_RESERVED_R16 0x00040846U +#define _reg_RESERVED_R17 0x08040846U +#define _reg_RESERVED_R18 0x10040846U +#define _reg_RESERVED_R19 0x18040846U +#define _reg_RESERVED_R20 0x00040847U +#define _reg_RESERVED_R21 0x08040847U +#define _reg_PI_INT_STATUS 0x00170848U +#define _reg_PI_INT_ACK 0x00160849U +#define _reg_PI_INT_MASK 0x0017084aU +#define _reg_PI_BIST_EXP_DATA_P0 0x0020084bU +#define _reg_PI_BIST_EXP_DATA_P1 0x0020084cU +#define _reg_PI_BIST_FAIL_DATA_P0 0x0020084dU +#define _reg_PI_BIST_FAIL_DATA_P1 0x0020084eU +#define _reg_PI_BIST_FAIL_ADDR_P0 0x0020084fU +#define _reg_PI_BIST_FAIL_ADDR_P1 0x00010850U +#define _reg_PI_BSTLEN 0x08050850U +#define _reg_PI_LONG_COUNT_MASK 0x10050850U +#define _reg_PI_DATA_BYTE_SWAP_EN 0x18010850U +#define _reg_PI_DATA_BYTE_SWAP_SLICE0 0x00010851U +#define _reg_PI_DATA_BYTE_SWAP_SLICE1 0x08010851U +#define _reg_PI_CTRLUPD_REQ_PER_AREF_EN 0x10010851U +#define _reg_PI_TDFI_CTRLUPD_MIN 0x18080851U +#define _reg_PI_UPDATE_ERROR_STATUS 0x00020852U +#define _reg_PI_BIST_GO 0x08010852U +#define _reg_PI_BIST_RESULT 0x10020852U +#define _reg_PI_ADDR_SPACE 0x18060852U +#define _reg_PI_BIST_DATA_CHECK 0x00010853U +#define _reg_PI_BIST_ADDR_CHECK 0x08010853U +#define _reg_PI_BIST_START_ADDRESS_P0 0x00200854U +#define _reg_PI_BIST_START_ADDRESS_P1 0x00010855U +#define _reg_PI_MBIST_INIT_PATTERN 0x08080855U +#define _reg_PI_BIST_DATA_MASK 0x00200856U +#define _reg_PI_BIST_ERR_COUNT 0x000c0857U +#define _reg_PI_BIST_ERR_STOP 0x100c0857U +#define _reg_PI_BIST_ADDR_MASK_0_P0 0x00200858U +#define _reg_PI_BIST_ADDR_MASK_0_P1 0x00020859U +#define _reg_PI_BIST_ADDR_MASK_1_P0 0x0020085aU +#define _reg_PI_BIST_ADDR_MASK_1_P1 0x0002085bU +#define _reg_PI_BIST_ADDR_MASK_2_P0 0x0020085cU +#define _reg_PI_BIST_ADDR_MASK_2_P1 0x0002085dU +#define _reg_PI_BIST_ADDR_MASK_3_P0 0x0020085eU +#define _reg_PI_BIST_ADDR_MASK_3_P1 0x0002085fU +#define _reg_PI_BIST_ADDR_MASK_4_P0 0x00200860U +#define _reg_PI_BIST_ADDR_MASK_4_P1 0x00020861U +#define _reg_PI_BIST_ADDR_MASK_5_P0 0x00200862U +#define _reg_PI_BIST_ADDR_MASK_5_P1 0x00020863U +#define _reg_PI_BIST_ADDR_MASK_6_P0 0x00200864U +#define _reg_PI_BIST_ADDR_MASK_6_P1 0x00020865U +#define _reg_PI_BIST_ADDR_MASK_7_P0 0x00200866U +#define _reg_PI_BIST_ADDR_MASK_7_P1 0x00020867U +#define _reg_PI_BIST_ADDR_MASK_8_P0 0x00200868U +#define _reg_PI_BIST_ADDR_MASK_8_P1 0x00020869U +#define _reg_PI_BIST_ADDR_MASK_9_P0 0x0020086aU +#define _reg_PI_BIST_ADDR_MASK_9_P1 0x0002086bU +#define _reg_PI_BIST_MODE 0x0803086bU +#define _reg_PI_BIST_ADDR_MODE 0x1002086bU +#define _reg_PI_BIST_PAT_MODE 0x1802086bU +#define _reg_PI_BIST_USER_PAT_P0 0x0020086cU +#define _reg_PI_BIST_USER_PAT_P1 0x0020086dU +#define _reg_PI_BIST_PAT_NUM 0x0004086eU +#define _reg_PI_BIST_STAGE_0 0x001e086fU +#define _reg_PI_BIST_STAGE_1 0x001e0870U +#define _reg_PI_BIST_STAGE_2 0x001e0871U +#define _reg_PI_BIST_STAGE_3 0x001e0872U +#define _reg_PI_BIST_STAGE_4 0x001e0873U +#define _reg_PI_BIST_STAGE_5 0x001e0874U +#define _reg_PI_BIST_STAGE_6 0x001e0875U +#define _reg_PI_BIST_STAGE_7 0x001e0876U +#define _reg_PI_COL_DIFF 0x00040877U +#define _reg_PI_SELF_REFRESH_EN 0x08010877U +#define _reg_PI_PWRUP_SREFRESH_EXIT 0x10010877U +#define _reg_PI_MONITOR_SRC_SEL_0 0x18040877U +#define _reg_PI_MONITOR_CAP_SEL_0 0x00010878U +#define _reg_PI_MONITOR_0 0x08080878U +#define _reg_PI_MONITOR_SRC_SEL_1 0x10040878U +#define _reg_PI_MONITOR_CAP_SEL_1 0x18010878U +#define _reg_PI_MONITOR_1 0x00080879U +#define _reg_PI_MONITOR_SRC_SEL_2 0x08040879U +#define _reg_PI_MONITOR_CAP_SEL_2 0x10010879U +#define _reg_PI_MONITOR_2 0x18080879U +#define _reg_PI_MONITOR_SRC_SEL_3 0x0004087aU +#define _reg_PI_MONITOR_CAP_SEL_3 0x0801087aU +#define _reg_PI_MONITOR_3 0x1008087aU +#define _reg_PI_MONITOR_SRC_SEL_4 0x1804087aU +#define _reg_PI_MONITOR_CAP_SEL_4 0x0001087bU +#define _reg_PI_MONITOR_4 0x0808087bU +#define _reg_PI_MONITOR_SRC_SEL_5 0x1004087bU +#define _reg_PI_MONITOR_CAP_SEL_5 0x1801087bU +#define _reg_PI_MONITOR_5 0x0008087cU +#define _reg_PI_MONITOR_SRC_SEL_6 0x0804087cU +#define _reg_PI_MONITOR_CAP_SEL_6 0x1001087cU +#define _reg_PI_MONITOR_6 0x1808087cU +#define _reg_PI_MONITOR_SRC_SEL_7 0x0004087dU +#define _reg_PI_MONITOR_CAP_SEL_7 0x0801087dU +#define _reg_PI_MONITOR_7 0x1008087dU +#define _reg_PI_MONITOR_STROBE 0x0008087eU +#define _reg_PI_DLL_LOCK 0x0001087fU +#define _reg_PI_FREQ_NUMBER_STATUS 0x0805087fU +#define _reg_RESERVED_R22 0x1001087fU +#define _reg_PI_PHYMSTR_TYPE 0x1802087fU +#define _reg_RESERVED_R23 0x00010880U +#define _reg_PI_POWER_REDUC_EN 0x08010880U +#define _reg_RESERVED_R24 0x10010880U +#define _reg_RESERVED_R25 0x18010880U +#define _reg_RESERVED_R26 0x00010881U +#define _reg_RESERVED_R27 0x08010881U +#define _reg_RESERVED_R28 0x10010881U +#define _reg_RESERVED_R29 0x18010881U +#define _reg_RESERVED_R30 0x00010882U +#define _reg_RESERVED_R31 0x08010882U +#define _reg_RESERVED_R32 0x10010882U +#define _reg_RESERVED_R33 0x18010882U +#define _reg_RESERVED_R34 0x00010883U +#define _reg_RESERVED_R35 0x08010883U +#define _reg_RESERVED_R36 0x10010883U +#define _reg_RESERVED_R37 0x18010883U +#define _reg_RESERVED_R38 0x00010884U +#define _reg_PI_WRLVL_MAX_STROBE_PEND 0x08080884U +#define _reg_PI_TREFBW_THR 0x10090884U +#define _reg_PI_FREQ_CHANGE_REG_COPY 0x00050885U +#define _reg_PI_FREQ_SEL_FROM_REGIF 0x00010886U +#define _reg_RESERVED_R39 0x08050886U +#define _reg_PI_CATR 0x10020886U +#define _reg_PI_NO_CATR_READ 0x18010886U +#define _reg_PI_MASK_INIT_COMPLETE 0x00010887U +#define _reg_PI_DISCONNECT_MC 0x08010887U +#define _reg_PI_TRACE_MC_MR13 0x10010887U +#define _reg_PI_TSDO_F0 0x18080887U +#define _reg_PI_TSDO_F1 0x00080888U +#define _reg_PI_TSDO_F2 0x08080888U +#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F0 0x00080889U +#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F1 0x0008088aU +#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x0008088bU +#define _reg_PI_WRLAT_F0 0x0807088bU +#define _reg_PI_CASLAT_LIN_F0 0x1007088bU +#define _reg_PI_WRLAT_F1 0x1807088bU +#define _reg_PI_CASLAT_LIN_F1 0x0007088cU +#define _reg_PI_WRLAT_F2 0x0807088cU +#define _reg_PI_CASLAT_LIN_F2 0x1007088cU +#define _reg_PI_TRFC_F0 0x000a088dU +#define _reg_PI_TREF_F0 0x0014088eU +#define _reg_PI_TRFC_F1 0x000a088fU +#define _reg_PI_TREF_F1 0x00140890U +#define _reg_PI_TRFC_F2 0x000a0891U +#define _reg_PI_TREF_F2 0x00140892U +#define _reg_PI_TDFI_CTRL_DELAY_F0 0x18040892U +#define _reg_PI_TDFI_CTRL_DELAY_F1 0x00040893U +#define _reg_PI_TDFI_CTRL_DELAY_F2 0x08040893U +#define _reg_PI_WRLVL_EN_F0 0x10020893U +#define _reg_PI_WRLVL_EN_F1 0x18020893U +#define _reg_PI_WRLVL_EN_F2 0x00020894U +#define _reg_PI_TDFI_WRLVL_WW_F0 0x080a0894U +#define _reg_PI_TDFI_WRLVL_WW_F1 0x000a0895U +#define _reg_PI_TDFI_WRLVL_WW_F2 0x100a0895U +#define _reg_PI_TODTL_2CMD_F0 0x00080896U +#define _reg_PI_ODT_EN_F0 0x08010896U +#define _reg_PI_TODTL_2CMD_F1 0x10080896U +#define _reg_PI_ODT_EN_F1 0x18010896U +#define _reg_PI_TODTL_2CMD_F2 0x00080897U +#define _reg_PI_ODT_EN_F2 0x08010897U +#define _reg_PI_ODTLON_F0 0x10040897U +#define _reg_PI_TODTON_MIN_F0 0x18040897U +#define _reg_PI_ODTLON_F1 0x00040898U +#define _reg_PI_TODTON_MIN_F1 0x08040898U +#define _reg_PI_ODTLON_F2 0x10040898U +#define _reg_PI_TODTON_MIN_F2 0x18040898U +#define _reg_PI_RDLVL_EN_F0 0x00020899U +#define _reg_PI_RDLVL_GATE_EN_F0 0x08020899U +#define _reg_PI_RDLVL_EN_F1 0x10020899U +#define _reg_PI_RDLVL_GATE_EN_F1 0x18020899U +#define _reg_PI_RDLVL_EN_F2 0x0002089aU +#define _reg_PI_RDLVL_GATE_EN_F2 0x0802089aU +#define _reg_PI_RDLVL_PAT0_EN_F0 0x1002089aU +#define _reg_PI_RDLVL_RXCAL_EN_F0 0x1802089aU +#define _reg_PI_RDLVL_DFE_EN_F0 0x0002089bU +#define _reg_PI_RDLVL_MULTI_EN_F0 0x0802089bU +#define _reg_PI_RDLVL_PAT0_EN_F1 0x1002089bU +#define _reg_PI_RDLVL_RXCAL_EN_F1 0x1802089bU +#define _reg_PI_RDLVL_DFE_EN_F1 0x0002089cU +#define _reg_PI_RDLVL_MULTI_EN_F1 0x0802089cU +#define _reg_PI_RDLVL_PAT0_EN_F2 0x1002089cU +#define _reg_PI_RDLVL_RXCAL_EN_F2 0x1802089cU +#define _reg_PI_RDLVL_DFE_EN_F2 0x0002089dU +#define _reg_PI_RDLVL_MULTI_EN_F2 0x0802089dU +#define _reg_PI_RDLAT_ADJ_F0 0x1007089dU +#define _reg_PI_RDLAT_ADJ_F1 0x1807089dU +#define _reg_PI_RDLAT_ADJ_F2 0x0007089eU +#define _reg_PI_WRLAT_ADJ_F0 0x0807089eU +#define _reg_PI_WRLAT_ADJ_F1 0x1007089eU +#define _reg_PI_WRLAT_ADJ_F2 0x1807089eU +#define _reg_PI_TDFI_PHY_WRDATA_F0 0x0003089fU +#define _reg_PI_TDFI_PHY_WRDATA_F1 0x0803089fU +#define _reg_PI_TDFI_PHY_WRDATA_F2 0x1003089fU +#define _reg_PI_TDFI_CALVL_CC_F0 0x000a08a0U +#define _reg_PI_TDFI_CALVL_CAPTURE_F0 0x100a08a0U +#define _reg_PI_TDFI_CALVL_CC_F1 0x000a08a1U +#define _reg_PI_TDFI_CALVL_CAPTURE_F1 0x100a08a1U +#define _reg_PI_TDFI_CALVL_CC_F2 0x000a08a2U +#define _reg_PI_TDFI_CALVL_CAPTURE_F2 0x100a08a2U +#define _reg_PI_CALVL_EN_F0 0x000208a3U +#define _reg_PI_CALVL_EN_F1 0x080208a3U +#define _reg_PI_CALVL_EN_F2 0x100208a3U +#define _reg_PI_TMRZ_F0 0x180508a3U +#define _reg_PI_TCAENT_F0 0x000e08a4U +#define _reg_PI_TMRZ_F1 0x100508a4U +#define _reg_PI_TCAENT_F1 0x000e08a5U +#define _reg_PI_TMRZ_F2 0x100508a5U +#define _reg_PI_TCAENT_F2 0x000e08a6U +#define _reg_PI_TDFI_CACSCA_F0 0x100508a6U +#define _reg_PI_TDFI_CASEL_F0 0x180508a6U +#define _reg_PI_TVREF_SHORT_F0 0x000a08a7U +#define _reg_PI_TVREF_LONG_F0 0x100a08a7U +#define _reg_PI_TDFI_CACSCA_F1 0x000508a8U +#define _reg_PI_TDFI_CASEL_F1 0x080508a8U +#define _reg_PI_TVREF_SHORT_F1 0x100a08a8U +#define _reg_PI_TVREF_LONG_F1 0x000a08a9U +#define _reg_PI_TDFI_CACSCA_F2 0x100508a9U +#define _reg_PI_TDFI_CASEL_F2 0x180508a9U +#define _reg_PI_TVREF_SHORT_F2 0x000a08aaU +#define _reg_PI_TVREF_LONG_F2 0x100a08aaU +#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F0 0x000708abU +#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F0 0x080708abU +#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F1 0x100708abU +#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F1 0x180708abU +#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F2 0x000708acU +#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x080708acU +#define _reg_PI_CALVL_VREF_DELTA_F0 0x100408acU +#define _reg_PI_CALVL_VREF_DELTA_F1 0x180408acU +#define _reg_PI_CALVL_VREF_DELTA_F2 0x000408adU +#define _reg_PI_TDFI_CALVL_STROBE_F0 0x080408adU +#define _reg_PI_TXP_F0 0x100508adU +#define _reg_PI_TMRWCKEL_F0 0x180808adU +#define _reg_PI_TCKELCK_F0 0x000508aeU +#define _reg_PI_TDFI_CALVL_STROBE_F1 0x080408aeU +#define _reg_PI_TXP_F1 0x100508aeU +#define _reg_PI_TMRWCKEL_F1 0x180808aeU +#define _reg_PI_TCKELCK_F1 0x000508afU +#define _reg_PI_TDFI_CALVL_STROBE_F2 0x080408afU +#define _reg_PI_TXP_F2 0x100508afU +#define _reg_PI_TMRWCKEL_F2 0x180808afU +#define _reg_PI_TCKELCK_F2 0x000508b0U +#define _reg_PI_TDFI_INIT_START_F0 0x080a08b0U +#define _reg_PI_TDFI_INIT_COMPLETE_F0 0x001008b1U +#define _reg_PI_TDFI_INIT_START_F1 0x100a08b1U +#define _reg_PI_TDFI_INIT_COMPLETE_F1 0x001008b2U +#define _reg_PI_TDFI_INIT_START_F2 0x100a08b2U +#define _reg_PI_TDFI_INIT_COMPLETE_F2 0x001008b3U +#define _reg_PI_TCKEHDQS_F0 0x100608b3U +#define _reg_PI_TFC_F0 0x000a08b4U +#define _reg_PI_TCKEHDQS_F1 0x100608b4U +#define _reg_PI_TFC_F1 0x000a08b5U +#define _reg_PI_TCKEHDQS_F2 0x100608b5U +#define _reg_PI_TFC_F2 0x000a08b6U +#define _reg_PI_TDFI_WDQLVL_WR_F0 0x100a08b6U +#define _reg_PI_TDFI_WDQLVL_RW_F0 0x000a08b7U +#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x100708b7U +#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x180708b7U +#define _reg_PI_WDQLVL_VREF_DELTA_F0 0x000408b8U +#define _reg_PI_WDQLVL_EN_F0 0x080208b8U +#define _reg_PI_NTP_TRAIN_EN_F0 0x100208b8U +#define _reg_PI_TDFI_WDQLVL_WR_F1 0x000a08b9U +#define _reg_PI_TDFI_WDQLVL_RW_F1 0x100a08b9U +#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x000708baU +#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x080708baU +#define _reg_PI_WDQLVL_VREF_DELTA_F1 0x100408baU +#define _reg_PI_WDQLVL_EN_F1 0x180208baU +#define _reg_PI_NTP_TRAIN_EN_F1 0x000208bbU +#define _reg_PI_TDFI_WDQLVL_WR_F2 0x080a08bbU +#define _reg_PI_TDFI_WDQLVL_RW_F2 0x000a08bcU +#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x100708bcU +#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x180708bcU +#define _reg_PI_WDQLVL_VREF_DELTA_F2 0x000408bdU +#define _reg_PI_WDQLVL_EN_F2 0x080208bdU +#define _reg_PI_NTP_TRAIN_EN_F2 0x100208bdU +#define _reg_PI_TRTP_F0 0x180808bdU +#define _reg_PI_TRP_F0 0x000808beU +#define _reg_PI_TRCD_F0 0x080808beU +#define _reg_PI_TWTR_F0 0x100608beU +#define _reg_PI_TWR_F0 0x180808beU +#define _reg_PI_TRAS_MAX_F0 0x001008bfU +#define _reg_PI_TRAS_MIN_F0 0x100808bfU +#define _reg_PI_TDQSCK_MAX_F0 0x180408bfU +#define _reg_PI_TCCDMW_F0 0x000608c0U +#define _reg_PI_TSR_F0 0x080808c0U +#define _reg_PI_TMRD_F0 0x100808c0U +#define _reg_PI_TMRW_F0 0x180808c0U +#define _reg_PI_TRTP_F1 0x000808c1U +#define _reg_PI_TRP_F1 0x080808c1U +#define _reg_PI_TRCD_F1 0x100808c1U +#define _reg_PI_TWTR_F1 0x180608c1U +#define _reg_PI_TWR_F1 0x000808c2U +#define _reg_PI_TRAS_MAX_F1 0x081008c2U +#define _reg_PI_TRAS_MIN_F1 0x180808c2U +#define _reg_PI_TDQSCK_MAX_F1 0x000408c3U +#define _reg_PI_TCCDMW_F1 0x080608c3U +#define _reg_PI_TSR_F1 0x100808c3U +#define _reg_PI_TMRD_F1 0x180808c3U +#define _reg_PI_TMRW_F1 0x000808c4U +#define _reg_PI_TRTP_F2 0x080808c4U +#define _reg_PI_TRP_F2 0x100808c4U +#define _reg_PI_TRCD_F2 0x180808c4U +#define _reg_PI_TWTR_F2 0x000608c5U +#define _reg_PI_TWR_F2 0x080808c5U +#define _reg_PI_TRAS_MAX_F2 0x101008c5U +#define _reg_PI_TRAS_MIN_F2 0x000808c6U +#define _reg_PI_TDQSCK_MAX_F2 0x080408c6U +#define _reg_PI_TCCDMW_F2 0x100608c6U +#define _reg_PI_TSR_F2 0x180808c6U +#define _reg_PI_TMRD_F2 0x000808c7U +#define _reg_PI_TMRW_F2 0x080808c7U +#define _reg_PI_TDFI_CTRLUPD_MAX_F0 0x001508c8U +#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F0 0x002008c9U +#define _reg_PI_TDFI_CTRLUPD_MAX_F1 0x001508caU +#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F1 0x002008cbU +#define _reg_PI_TDFI_CTRLUPD_MAX_F2 0x001508ccU +#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F2 0x002008cdU +#define _reg_PI_TXSR_F0 0x001008ceU +#define _reg_PI_TXSR_F1 0x101008ceU +#define _reg_PI_TXSR_F2 0x001008cfU +#define _reg_PI_WDQ_OSC_DELTA_INDEX_F0 0x100408cfU +#define _reg_PI_WDQ_OSC_DELTA_INDEX_F1 0x180408cfU +#define _reg_PI_WDQ_OSC_DELTA_INDEX_F2 0x000408d0U +#define _reg_PI_MR13_DATA_0 0x080808d0U +#define _reg_PI_MR40_DATA_0 0x100808d0U +#define _reg_PI_MR13_DATA_1 0x180808d0U +#define _reg_PI_MR40_DATA_1 0x000808d1U +#define _reg_PI_DQS_OSC_BASE_VALUE_0_0 0x081008d1U +#define _reg_PI_DQS_OSC_BASE_VALUE_0_1 0x001008d2U +#define _reg_PI_MR1_DATA_F0_0 0x100808d2U +#define _reg_PI_MR2_DATA_F0_0 0x180808d2U +#define _reg_PI_MR3_DATA_F0_0 0x000808d3U +#define _reg_PI_MR11_DATA_F0_0 0x080808d3U +#define _reg_PI_MR12_DATA_F0_0 0x100808d3U +#define _reg_PI_MR14_DATA_F0_0 0x180808d3U +#define _reg_PI_MR22_DATA_F0_0 0x000808d4U +#define _reg_PI_MR23_DATA_F0_0 0x080808d4U +#define _reg_PI_MR1_DATA_F1_0 0x100808d4U +#define _reg_PI_MR2_DATA_F1_0 0x180808d4U +#define _reg_PI_MR3_DATA_F1_0 0x000808d5U +#define _reg_PI_MR11_DATA_F1_0 0x080808d5U +#define _reg_PI_MR12_DATA_F1_0 0x100808d5U +#define _reg_PI_MR14_DATA_F1_0 0x180808d5U +#define _reg_PI_MR22_DATA_F1_0 0x000808d6U +#define _reg_PI_MR23_DATA_F1_0 0x080808d6U +#define _reg_PI_MR1_DATA_F2_0 0x100808d6U +#define _reg_PI_MR2_DATA_F2_0 0x180808d6U +#define _reg_PI_MR3_DATA_F2_0 0x000808d7U +#define _reg_PI_MR11_DATA_F2_0 0x080808d7U +#define _reg_PI_MR12_DATA_F2_0 0x100808d7U +#define _reg_PI_MR14_DATA_F2_0 0x180808d7U +#define _reg_PI_MR22_DATA_F2_0 0x000808d8U +#define _reg_PI_MR23_DATA_F2_0 0x080808d8U +#define _reg_PI_MR1_DATA_F0_1 0x100808d8U +#define _reg_PI_MR2_DATA_F0_1 0x180808d8U +#define _reg_PI_MR3_DATA_F0_1 0x000808d9U +#define _reg_PI_MR11_DATA_F0_1 0x080808d9U +#define _reg_PI_MR12_DATA_F0_1 0x100808d9U +#define _reg_PI_MR14_DATA_F0_1 0x180808d9U +#define _reg_PI_MR22_DATA_F0_1 0x000808daU +#define _reg_PI_MR23_DATA_F0_1 0x080808daU +#define _reg_PI_MR1_DATA_F1_1 0x100808daU +#define _reg_PI_MR2_DATA_F1_1 0x180808daU +#define _reg_PI_MR3_DATA_F1_1 0x000808dbU +#define _reg_PI_MR11_DATA_F1_1 0x080808dbU +#define _reg_PI_MR12_DATA_F1_1 0x100808dbU +#define _reg_PI_MR14_DATA_F1_1 0x180808dbU +#define _reg_PI_MR22_DATA_F1_1 0x000808dcU +#define _reg_PI_MR23_DATA_F1_1 0x080808dcU +#define _reg_PI_MR1_DATA_F2_1 0x100808dcU +#define _reg_PI_MR2_DATA_F2_1 0x180808dcU +#define _reg_PI_MR3_DATA_F2_1 0x000808ddU +#define _reg_PI_MR11_DATA_F2_1 0x080808ddU +#define _reg_PI_MR12_DATA_F2_1 0x100808ddU +#define _reg_PI_MR14_DATA_F2_1 0x180808ddU +#define _reg_PI_MR22_DATA_F2_1 0x000808deU +#define _reg_PI_MR23_DATA_F2_1 0x080808deU +#define _reg_PI_PARITY_ERROR_REGIF 0x100b08deU + +#define DDR_REGDEF_ADR(regdef) ((regdef)&0xffff) +#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff) +#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff) + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.c new file mode 100644 index 0000000..055e568 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.c @@ -0,0 +1,354 @@ +/******************************************************************************* + * Copyright (c) 2022-2023 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC setting function + ******************************************************************************/ +/****************************************************************************** + * @file ecc_enable_s4.c + * - Version : 0.02 + * @brief Enable setting process of ECC for DRAM. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 09.08.2022 0.01 First Release + * : 04.04.2023 0.02 Removed stdio.h and string.h. + *****************************************************************************/ + + +#include + +static void ecm_unlock(void); +static void ecm_write(uint32_t adr, uint32_t val); +static void ecm_lock(void); + +#include "boot_init_dram_regdef.h" +#include "ecc_enable_s4.h" + +static void ecm_unlock(void) +{ + uint32_t tmp_adr; + tmp_adr = ((0xACCEU << 16U) | (ECMWPCNTR & 0xffffU)); + mem_write32(ECMWACNTR, tmp_adr); + mem_write32(ECMWPCNTR, 0xACCE0001); +} + +static void ecm_write(uint32_t adr, uint32_t val) +{ + mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU))); + mem_write32(adr, val); +} + +static void ecm_lock(void) +{ + mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (ECMWACNTR & 0xffffU))); + mem_write32(ECMWPCNTR, 0xACCE0000U); +} + +void enable_ecc(void) +{ + NOTICE("ECC for DRAM is enable.\n"); + uint32_t ecm_tmp; + + /* Unlock the access protect for DBSC registers */ + mem_write32(DBSC_DBSYSCNT0, 0x00001234U); + mem_write32(DBSC_DBSYSCNT0A, 0x00001234U); + + /* (A) Initialization for DRAM */ + mmio_write_32(DBSC_DBACEN, 0x00000000U); + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR and ECMERRFATALR registers to inform + the control domain of the fatal error. */ + ecm_tmp = mem_read32(ECMERRTGTR0); + ecm_tmp &= ~(0x3U); + ecm_write(ECMERRTGTR0, ecm_tmp); + + ecm_tmp = mem_read32(ECMERRCTLR0); + ecm_tmp |= 0x3U; + ecm_write(ECMERRCTLR0, ecm_tmp); + + ecm_tmp = mem_read32(ECMERRFATALR0); + ecm_tmp |= 0x3U; + ecm_write(ECMERRFATALR0, ecm_tmp); + + /* (B) Setting ECC protection area */ + /* Set the bottom row address of the ECC protection area */ + mem_write32(DBFSDRAMECCAREA00, ECC_PROT_SIZE0); + mem_write32(DBFSDRAMECCAREA01, ECC_PROT_SIZE1); + + /* (2) Initialization for DRAM connected to DBSCCORE */ + /* Specify RANK0 as the initialization target */ + ecm_tmp = mem_read32(DBFSCONF00A); + ecm_tmp = 0x0U; + mem_write32(DBFSCONF00A, ecm_tmp); + + /* Set the start and end row address of the initialization area */ + mem_write32(DBFSCONF01A, START_ECC_INIT_AREA0); + mem_write32(DBFSCONF05A, END_ECC_INIT_AREA0); + + /* Set 0x1 to start initialization */ + ecm_tmp = mem_read32(DBFSCTRL01A); + ecm_tmp |= 0x01U; + mem_write32(DBFSCTRL01A, ecm_tmp); + + /* Wait until to DRAM initialization is complete */ + NOTICE("DRAM rank 0 is initializing.......\n"); + do + { + ecm_tmp = mem_read32(DBFSSTAT01A); + } while ((ecm_tmp & 0x01U) != 0x01U); + + /* If DRAM is connected to RANK1, Initialize RANK1 */ + /* Specify RANK0 as the initialization target */ + ecm_tmp = mem_read32(DBFSCONF00A); + ecm_tmp |= 0x1U; + mem_write32(DBFSCONF00A, ecm_tmp); + + /* Set the start and end row address of the initialization area */ + mem_write32(DBFSCONF01A, START_ECC_INIT_AREA1); + mem_write32(DBFSCONF05A, END_ECC_INIT_AREA1); + + /* Set 0x1 to start initialization */ + ecm_tmp = mem_read32(DBFSCTRL01A); + ecm_tmp |= 0x01U; + mem_write32(DBFSCTRL01A, ecm_tmp); + + /* Wait until to DRAM initialization is complete */ + NOTICE("DRAM rank 1 is initializing.......\n"); + do + { + ecm_tmp = mem_read32(DBFSSTAT01A); + } while ((ecm_tmp & 0x01U) != 0x01U); + + /* (C) Setting ECC protection enable */ + ecm_tmp = mem_read32(DBFSCONFAXI0); + ecm_tmp |= (0x3 << 8U); + mem_write32(DBFSCONFAXI0, ecm_tmp); + + /* (D) System RAM initialization */ + /* Wait for initialization of System RAM */ + NOTICE("System RAM is initializing.......\n"); + do + { + ; + } while ((mem_read32(DBFSSTAT00A) & 0x1U) != 0x1U); + + /* (E) Setting for ECC error interrupt */ + /* (1) Set the ECC error interrupt for read data. */ + mem_write32(DBFSINTENB02A, 0xFF00U); + + /* (2) Set the ECC error interrupt during RMW operation for System RAM. */ + ecm_tmp = mem_read32(DBFSINTENB02A); + ecm_tmp |= (0xFFU << 24U); + mem_write32(DBFSINTENB02A, ecm_tmp); + + /* (3) Set the ECC error interrupt during RMW operation for DRAM. */ + mem_write32(DBFSINTENB04A, 0xFFFFU); + + /* Lock the ECM registers */ + ecm_lock(); + + /* Enable the write protect of ECM registers */ + mmio_write_32(DBSC_DBACEN, 0x00000001U); + + /* Enable the access protect for DBSC registers */ + mem_write32(DBSC_DBSYSCNT0, 0x00000000U); + mem_write32(DBSC_DBSYSCNT0A, 0x00000000U); +} + +void ecc_rtsram_enable(void) +{ + uint32_t ecc_tmp; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR and + ECMERRFATALR registers to inform the control domain of the fatal error. */ + + /* Set bit 29 of ECMERRTGTR7 to 0 and bit 29 of ECMERRCTLR7 to 1. + (RT-SRAM ecc 2-bit error) */ + ecc_tmp = mem_read32(ECMERRTGTR7); + ecc_tmp |= (1U << 29U) ; + ecm_write(ECMERRTGTR7, ecc_tmp); + + ecc_tmp = mem_read32(ECMERRCTLR7); + ecc_tmp |= (1U << 29U); + ecm_write(ECMERRCTLR7, ecc_tmp); + + /* Set bit 19 of ECMERRTGTR7 to 0 and bit 19 of ECMERRCTLR7 to 1. + (RT-SRAM ecc 2-bit error (for ICUMX)) */ + ecc_tmp = mem_read32(ECMERRTGTR7); + ecc_tmp |= (1U << 19U); + ecm_write(ECMERRTGTR7, ecc_tmp); + + ecc_tmp = mem_read32(ECMERRCTLR7); + ecc_tmp |= (1U << 19U); + ecm_write(ECMERRCTLR7, ecc_tmp); + + /* Set bit 29 and 19 of ECMERRFATALR7 to 1. (Notification of fatal error) */ + ecc_tmp = mem_read32(ECMERRFATALR7); + ecc_tmp |= ((1U << 29U) | (1U << 19U)); + ecm_write(ECMERRFATALR7, ecc_tmp); + + /* (2) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers to + notify the correctable error to software. */ + + /* Set bit 30 of ECMERRTGTR7 to 1 and bit 30 of ECMERRCTLR7 to 1. + (RT-SRAM ecc 1-bit error) */ + ecc_tmp = mem_read32(ECMERRTGTR7); + ecc_tmp |= (1U << 30U); + ecm_write(ECMERRTGTR7, ecc_tmp); + + ecc_tmp = mem_read32(ECMERRCTLR7); + ecc_tmp |= (1U << 30U); + ecm_write(ECMERRCTLR7, ecc_tmp); + + /* Set bit 20 of ECMERRTGTR7 to 1 and bit 20 of ECMERRCTLR7 to 1. + (RT-SRAM ecc 1-bit error (for ICUMX)) */ + ecc_tmp = mem_read32(ECMERRTGTR7); + ecc_tmp |= (1U << 20U); + ecm_write(ECMERRTGTR7, ecc_tmp); + + ecc_tmp = mem_read32(ECMERRCTLR7); + ecc_tmp |= (1U << 20U); + ecm_write(ECMERRCTLR7, ecc_tmp); + + /* Lock the ECM registers */ + ecm_lock(); +} + +void edc_axi_enable(void) +{ + uint32_t edc_tmp; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR + and ECMERRFATALR registers to inform the control domain of the fatal error. */ + + /* Set bit 10 - bit 6 of ECMERRTGTR7 to all 0 and bit 10 - bit 6 of + ECMERRCTLR7 to 1. (Error of AXI-Bus ECM of each hierarchy) */ + edc_tmp = mem_read32(ECMERRTGTR7); + edc_tmp &= ~(0x1fU << 6U); + ecm_write(ECMERRTGTR7, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR7); + edc_tmp |= (0x1fU << 6U); + ecm_write(ECMERRCTLR7, edc_tmp); + + /* Set bit 23 - bit 16 of ECMERRTGTR39 to all 0 and bit 23 - bit 16 of + ECMERRCTLR39 to 1. (Error of AXI-Bus ECM of each hierarchy) */ + edc_tmp = mem_read32(ECMERRTGTR39); + edc_tmp &= ~(0xffU << 16U); + ecm_write(ECMERRTGTR39, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR39); + edc_tmp |= (0xffU << 6U); + ecm_write(ECMERRCTLR39, edc_tmp); + + /* Set bit 26 of ECMERRTGTR1 to 0 and bit 26 of + ECMERRCTLR1 to 1. (CCI bus EDC error) */ + edc_tmp = mem_read32(ECMERRTGTR1); + edc_tmp &= ~(0x1U << 26U); + ecm_write(ECMERRTGTR1, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR1); + edc_tmp |= (0x1U << 26U); + ecm_write(ECMERRCTLR1, edc_tmp); + + /* Set bit 10 - bit 6 of ECMERRFATALR7 to 1. + (Notification of fatal error) */ + edc_tmp = mem_read32(ECMERRFATALR7); + edc_tmp |= (0x1fU << 6U); + ecm_write(ECMERRFATALR7, edc_tmp); + + /* Set bit 23 - bit 16 of ECMERRFATALR39 to 1. + (Notification of fatal error) */ + edc_tmp = mem_read32(ECMERRFATALR39); + edc_tmp |= (0xffU << 16U); + ecm_write(ECMERRFATALR39, edc_tmp); + + /* Set bit 26 of ECMERRFATALR1 to 1. + (Notification of fatal error) */ + edc_tmp = mem_read32(ECMERRFATALR1); + edc_tmp |= (0x1U << 26U); + ecm_write(ECMERRFATALR1, edc_tmp); + + /* Lock the ECM registers */ + ecm_lock(); +} + +void edc_vram_enable(void) +{ + uint32_t edc_tmp; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR and + ECMERRFATALR registers to inform the control domain of the fatal error. */ + + /* Set bit 19 of ECMERRTGTR17 to 0 and bit 19 of ECMERRCTLR17 to 1. + (RT-VRAM edc 1-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR17); + edc_tmp &= ~(0x1U << 19U); + ecm_write(ECMERRTGTR17, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR17); + edc_tmp |= (0x1U << 19U); + ecm_write(ECMERRCTLR17, edc_tmp); + + /* Set bit 18 of ECMERRTGTR17 to 0 and bit 18 of ECMERRCTLR17 to 1. + (RT-VRAM edc multi-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR17); + edc_tmp &= ~(0x1U << 18U); + ecm_write(ECMERRTGTR17, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR17); + edc_tmp |= (0x1U << 18U); + ecm_write(ECMERRCTLR17, edc_tmp); + + /* Set bit 19, 18 of ECMERRFATALR17 to 1. (Notification of fatal error) */ + edc_tmp = mem_read32(ECMERRFATALR17); + edc_tmp |= (0x3U << 18U); + ecm_write(ECMERRFATALR17, edc_tmp); + + /* Set bit 0 of EDC_CFG to 1. (EDC Error Control) */ + edc_tmp = mem_read32(EDC_CFG); + edc_tmp |= (0x1U << 0U); + ecm_write(EDC_CFG, edc_tmp); + + /* Lock the ECM registers */ + ecm_lock(); +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.h new file mode 100644 index 0000000..2bbf663 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.h @@ -0,0 +1,104 @@ +/******************************************************************************* + * Copyright (c) 2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC driver header + ******************************************************************************/ + +#ifndef ECC_PROTECT +#define ECC_PROTECT +#include "remap_register.h" +#if(__RH850__) + #include "mem_io.h" + #include "log.h" + #define ECM_BASE (BASE_ECC_ADDR) + #define DBSC_BASE (BASE_DBSC_ADDR) +#else + #include + #include + #define ECM_BASE (0xE6250000U) + #define DBSC_BASE (0xE6790000U) +#endif/* __RH850__ */ + +#define RTVRAM_REG_BASE (0xFFEC0000U) + +void enable_ecc(void); +void ecc_rtsram_enable(void); +void edc_axi_enable(void); +void edc_vram_enable(void); + +#define DBSC_DBACEN (DBSC_BASE + 0x0200U) + +#define ECMWACNTR (ECM_BASE + 0x0A04U) +#define ECMWPCNTR (ECM_BASE + 0x0A00U) +#define ECMERRTGTR0 (ECM_BASE + 0x0200U) +#define ECMERRCTLR0 (ECM_BASE + 0x0000U) +#define ECMERRTGTR1 (ECM_BASE + 0x0200U + 0x4U * 1U) +#define ECMERRCTLR1 (ECM_BASE + 0x0000U + 0x4U * 1U) +#define ECMERRTGTR7 (ECM_BASE + 0x0200U + 0x4U * 7U) +#define ECMERRCTLR7 (ECM_BASE + 0x0000U + 0x4U * 7U) +#define ECMERRTGTR17 (ECM_BASE + 0x0200U + 0x4U * 17U) +#define ECMERRCTLR17 (ECM_BASE + 0x0000U + 0x4U * 17U) +#define ECMERRTGTR39 (ECM_BASE + 0x0200U + 0x4U * 39U) +#define ECMERRCTLR39 (ECM_BASE + 0x0000U + 0x4U * 39U) +#define ECMERRFATALR0 (ECM_BASE + 0x0600U) +#define ECMERRFATALR1 (ECM_BASE + 0x0600U + 0x4U * 1U) +#define ECMERRFATALR7 (ECM_BASE + 0x0600U + 0x4U * 7U) +#define ECMERRFATALR17 (ECM_BASE + 0x0600U + 0x4U * 17U) +#define ECMERRFATALR39 (ECM_BASE + 0x0600U + 0x4U * 39U) + +#define DBFSCONF00A (DBSC_BASE + 0x7640U) +#define DBFSCONF01A (DBSC_BASE + 0x7644U) +#define DBFSCONF05A (DBSC_BASE + 0x7654U) +#define DBFSCTRL01A (DBSC_BASE + 0x7604U) +#define DBFSSTAT01A (DBSC_BASE + 0x7684U) +#define DBFSSTAT00A (DBSC_BASE + 0x7680U) +#define DBFSINTENB02A (DBSC_BASE + 0x7088U) +#define DBFSINTENB04A (DBSC_BASE + 0x7090U) + +#define DBFSDRAMECCAREA00 (DBSC_BASE + 0x7450U) +#define DBFSDRAMECCAREA01 (DBSC_BASE + 0x7454U) +#define DBFSCONFAXI0 (DBSC_BASE + 0x7400U) + +#define EDC_CFG (RTVRAM_REG_BASE + 0x4110U) + +/********************* Set by the user *********************/ +/* The row address of ECC Protection Area Size for memory rank 0/1 */ +#define ECC_PROT_SIZE0 (0x2000U) +#define ECC_PROT_SIZE1 (0x2000U) + +/* Start and End row address of ECC Protection area for rank0 */ +#define START_ECC_INIT_AREA0 (0x00000000U) +#define END_ECC_INIT_AREA0 (0x00001FFFU) + +/* Start and End row address of ECC Protection area for rank1 */ +#define START_ECC_INIT_AREA1 (0x00000000U) +#define END_ECC_INIT_AREA1 (0x00001FFFU) +/*********** Other settings cannot be changed ***************/ + +#endif/* ECC_PROTECT */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/init_dram_tbl_s4.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/init_dram_tbl_s4.h new file mode 100644 index 0000000..599ceed --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/init_dram_tbl_s4.h @@ -0,0 +1,615 @@ +/******************************************************************************* + * Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +#define DDR_PHY_SLICE_REGSET_OFS_S4 0x1000 +#define DDR_PHY_ADR_V_REGSET_OFS_S4 0x1200 +#define DDR_PHY_ADR_G_REGSET_OFS_S4 0x1300 +#define DDR_PI_REGSET_OFS_S4 0x0800 + +#define DDR_PHY_SLICE_REGSET_SIZE_S4 0x100 +#define DDR_PHY_ADR_V_REGSET_SIZE_S4 0x80 +#define DDR_PHY_ADR_G_REGSET_SIZE_S4 0x100 +#define DDR_PI_REGSET_SIZE_S4 0x100 + +#define DDR_PHY_SLICE_REGSET_NUM_S4 140 +#define DDR_PHY_ADR_V_REGSET_NUM_S4 54 +#define DDR_PHY_ADR_G_REGSET_NUM_S4 143 +#define DDR_PI_REGSET_NUM_S4 223 + +static const uint32_t DDR_PHY_SLICE_REGSET_S4[DDR_PHY_SLICE_REGSET_NUM_S4] = { +/*1000*/ 0x000004F0, +/*1001*/ 0x00000000, +/*1002*/ 0x00030200, +/*1003*/ 0x00000000, +/*1004*/ 0x00000000, +/*1005*/ 0x01030000, +/*1006*/ 0x00010000, +/*1007*/ 0x01030004, +/*1008*/ 0x00000000, +/*1009*/ 0x00000000, +/*100a*/ 0x00000000, +/*100b*/ 0x01000001, +/*100c*/ 0x00000200, +/*100d*/ 0x000800C0, +/*100e*/ 0x06010190, +/*100f*/ 0x00030030, +/*1010*/ 0x00000000, +/*1011*/ 0x00000000, +/*1012*/ 0x55555A3C, +/*1013*/ 0x00005555, +/*1014*/ 0x0000B5B5, +/*1015*/ 0x00004A4A, +/*1016*/ 0x00005656, +/*1017*/ 0x0000A9A9, +/*1018*/ 0x0000A9A9, +/*1019*/ 0x0000B5B5, +/*101a*/ 0x00000000, +/*101b*/ 0x00000000, +/*101c*/ 0x2A000000, +/*101d*/ 0x00000808, +/*101e*/ 0x04000000, +/*101f*/ 0x00000408, +/*1020*/ 0x10600000, +/*1021*/ 0x0C008006, +/*1022*/ 0x00000000, +/*1023*/ 0x00000000, +/*1024*/ 0x55AA55AA, +/*1025*/ 0x33CC33CC, +/*1026*/ 0x0FF00FF0, +/*1027*/ 0x0F0FF0F0, +/*1028*/ 0x00008E38, +/*1029*/ 0x01000100, +/*102a*/ 0x00800180, +/*102b*/ 0x00000001, +/*102c*/ 0x00000000, +/*102d*/ 0x00000000, +/*102e*/ 0x00000000, +/*102f*/ 0x00000000, +/*1030*/ 0x00000000, +/*1031*/ 0x00000000, +/*1032*/ 0x00000000, +/*1033*/ 0x00000000, +/*1034*/ 0x00000000, +/*1035*/ 0x00000000, +/*1036*/ 0x00000000, +/*1037*/ 0x00000000, +/*1038*/ 0x00000000, +/*1039*/ 0x00000000, +/*103a*/ 0x00000000, +/*103b*/ 0x00000000, +/*103c*/ 0x00000000, +/*103d*/ 0x00000000, +/*103e*/ 0x00000000, +/*103f*/ 0x00000000, +/*1040*/ 0x00000000, +/*1041*/ 0x00000000, +/*1042*/ 0x00000104, +/*1043*/ 0x00000120, +/*1044*/ 0x00000000, +/*1045*/ 0x00000000, +/*1046*/ 0x00000000, +/*1047*/ 0x00000000, +/*1048*/ 0x00000000, +/*1049*/ 0x00000000, +/*104a*/ 0x00000000, +/*104b*/ 0x00000000, +/*104c*/ 0x07FF0000, +/*104d*/ 0x00800800, +/*104e*/ 0x00081020, +/*104f*/ 0x04010000, +/*1050*/ 0x00000000, +/*1051*/ 0x00000000, +/*1052*/ 0x00000000, +/*1053*/ 0x00000000, +/*1054*/ 0x01CC0C01, +/*1055*/ 0x2003CC0C, +/*1056*/ 0x20000139, +/*1057*/ 0x07FF0200, +/*1058*/ 0x0100DD01, +/*1059*/ 0x00000103, +/*105a*/ 0x00000000, +/*105b*/ 0x00000000, +/*105c*/ 0x00060000, +/*105d*/ 0x00A000A0, +/*105e*/ 0x00A000A0, +/*105f*/ 0x00A000A0, +/*1060*/ 0x00A000A0, +/*1061*/ 0x000500A0, +/*1062*/ 0x51517042, +/*1063*/ 0x31C08000, +/*1064*/ 0x09AD0064, +/*1065*/ 0x00C0C001, +/*1066*/ 0x0E0C0101, +/*1067*/ 0x10001000, +/*1068*/ 0x0C073E42, +/*1069*/ 0x0F0C3708, +/*106a*/ 0x01C00190, +/*106b*/ 0x04000420, +/*106c*/ 0x00000322, +/*106d*/ 0x0A0000D0, +/*106e*/ 0x00030200, +/*106f*/ 0x02800000, +/*1070*/ 0x80800000, +/*1071*/ 0x000E0010, +/*1072*/ 0x76543210, +/*1073*/ 0x00000008, +/*1074*/ 0x02800280, +/*1075*/ 0x02800280, +/*1076*/ 0x02800280, +/*1077*/ 0x02800280, +/*1078*/ 0x00000280, +/*1079*/ 0x0000A000, +/*107a*/ 0x00A000A0, +/*107b*/ 0x00A000A0, +/*107c*/ 0x00A000A0, +/*107d*/ 0x00A000A0, +/*107e*/ 0x00A000A0, +/*107f*/ 0x00A000A0, +/*1080*/ 0x00A000A0, +/*1081*/ 0x00A000A0, +/*1082*/ 0x01C200A0, +/*1083*/ 0x01A00005, +/*1084*/ 0x00000000, +/*1085*/ 0x00000000, +/*1086*/ 0x00080200, +/*1087*/ 0x00000000, +/*1088*/ 0x20202020, +/*1089*/ 0x20202020, +/*108a*/ 0x01012020, +/*108b*/ 0x00000000 +}; + +static const uint32_t DDR_PHY_ADR_V_REGSET_S4[DDR_PHY_ADR_V_REGSET_NUM_S4] = { +/*1200*/ 0x00000000, +/*1201*/ 0x00000000, +/*1202*/ 0x00000000, +/*1203*/ 0x00000000, +/*1204*/ 0x00000000, +/*1205*/ 0x00000100, +/*1206*/ 0x00000200, +/*1207*/ 0x00000000, +/*1208*/ 0x00000000, +/*1209*/ 0x00000000, +/*120a*/ 0x00000000, +/*120b*/ 0x00800200, +/*120c*/ 0x00000080, +/*120d*/ 0x00DCBA98, +/*120e*/ 0x01000000, +/*120f*/ 0x00200003, +/*1210*/ 0x00000000, +/*1211*/ 0x00000000, +/*1212*/ 0x00000000, +/*1213*/ 0x00000000, +/*1214*/ 0x00000000, +/*1215*/ 0x00000000, +/*1216*/ 0x00000000, +/*1217*/ 0x0000002A, +/*1218*/ 0x00000015, +/*1219*/ 0x00000015, +/*121a*/ 0x0000002A, +/*121b*/ 0x00000033, +/*121c*/ 0x0000000C, +/*121d*/ 0x0000000C, +/*121e*/ 0x00000033, +/*121f*/ 0x00543210, +/*1220*/ 0x003F0000, +/*1221*/ 0x0000013F, +/*1222*/ 0x20202003, +/*1223*/ 0x00202020, +/*1224*/ 0x20008008, +/*1225*/ 0x00000810, +/*1226*/ 0x00000F00, +/*1227*/ 0x00000000, +/*1228*/ 0x00000000, +/*1229*/ 0x00000000, +/*122a*/ 0x000605CC, +/*122b*/ 0x00030000, +/*122c*/ 0x00000300, +/*122d*/ 0x00000300, +/*122e*/ 0x00000300, +/*122f*/ 0x00000300, +/*1230*/ 0x00000300, +/*1231*/ 0x42080010, +/*1232*/ 0x0000803E, +/*1233*/ 0x00000008, +/*1234*/ 0x01000001, +/*1235*/ 0x00008000 +}; + +static const uint32_t DDR_PHY_ADR_G_REGSET_S4[DDR_PHY_ADR_G_REGSET_NUM_S4] = { +/*1300*/ 0x00000000, +/*1301*/ 0x00000100, +/*1302*/ 0x00000000, +/*1303*/ 0x00000000, +/*1304*/ 0x00050000, +/*1305*/ 0x04000000, +/*1306*/ 0x00000020, +/*1307*/ 0x00000000, +/*1308*/ 0x00000000, +/*1309*/ 0x00000000, +/*130a*/ 0x00000000, +/*130b*/ 0x00002001, +/*130c*/ 0x00004003, +/*130d*/ 0x00010028, +/*130e*/ 0x01010100, +/*130f*/ 0x00800800, +/*1310*/ 0x08102000, +/*1311*/ 0x00000000, +/*1312*/ 0x00000000, +/*1313*/ 0x00010E06, +/*1314*/ 0x00000000, +/*1315*/ 0x00000000, +/*1316*/ 0x00000000, +/*1317*/ 0x00000000, +/*1318*/ 0x00040000, +/*1319*/ 0x00000000, +/*131a*/ 0x00000000, +/*131b*/ 0x00000064, +/*131c*/ 0x00000000, +/*131d*/ 0x00000100, +/*131e*/ 0x00000200, +/*131f*/ 0x80012000, +/*1320*/ 0x00041B42, +/*1321*/ 0x05000000, +/*1322*/ 0x00000000, +/*1323*/ 0x00000000, +/*1324*/ 0x00000000, +/*1325*/ 0x01000000, +/*1326*/ 0x01070501, +/*1327*/ 0x00000054, +/*1328*/ 0x00004410, +/*1329*/ 0x00004410, +/*132a*/ 0x00004410, +/*132b*/ 0x00004410, +/*132c*/ 0x00004410, +/*132d*/ 0x00004410, +/*132e*/ 0x00004410, +/*132f*/ 0x00004410, +/*1330*/ 0x00004410, +/*1331*/ 0x00000000, +/*1332*/ 0x00000000, +/*1333*/ 0x00000000, +/*1334*/ 0x00060000, +/*1335*/ 0x00000000, +/*1336*/ 0x00000090, +/*1337*/ 0x0000A25A, +/*1338*/ 0x00000008, +/*1339*/ 0x00000000, +/*133a*/ 0x00000000, +/*133b*/ 0x00000000, +/*133c*/ 0x00000000, +/*133d*/ 0x00000000, +/*133e*/ 0x03000000, +/*133f*/ 0x00000000, +/*1340*/ 0x00000000, +/*1341*/ 0x00000000, +/*1342*/ 0x04102000, +/*1343*/ 0x00041020, +/*1344*/ 0x00C98C98, +/*1345*/ 0x3F400000, +/*1346*/ 0x3F3F1F3F, +/*1347*/ 0x0000001F, +/*1348*/ 0x00000000, +/*1349*/ 0x00000000, +/*134a*/ 0x00000000, +/*134b*/ 0x00010000, +/*134c*/ 0x00000000, +/*134d*/ 0x00000000, +/*134e*/ 0x00000000, +/*134f*/ 0x00000100, +/*1350*/ 0x00000000, +/*1351*/ 0x00000000, +/*1352*/ 0x00040700, +/*1353*/ 0x00000000, +/*1354*/ 0x00000000, +/*1355*/ 0x00000000, +/*1356*/ 0x00000002, +/*1357*/ 0x00000100, +/*1358*/ 0x00000000, +/*1359*/ 0x00000000, +/*135a*/ 0x00001F00, +/*135b*/ 0x00000000, +/*135c*/ 0x00000000, +/*135d*/ 0x00080000, +/*135e*/ 0x000007FF, +/*135f*/ 0x00000000, +/*1360*/ 0x00000000, +/*1361*/ 0x00000000, +/*1362*/ 0x00000000, +/*1363*/ 0x00000000, +/*1364*/ 0x000FFFFF, +/*1365*/ 0x000FFFFF, +/*1366*/ 0x0000FFFF, +/*1367*/ 0xFFFFFFF0, +/*1368*/ 0x030FFFFF, +/*1369*/ 0x01FFFFFF, +/*136a*/ 0x0000FFFF, +/*136b*/ 0x00000000, +/*136c*/ 0x00000000, +/*136d*/ 0x00000000, +/*136e*/ 0x00000000, +/*136f*/ 0x00000000, +/*1370*/ 0x00000006, +/*1371*/ 0x00000000, +/*1372*/ 0x00001142, +/*1373*/ 0x08010600, +/*1374*/ 0x00000080, +/*1375*/ 0x03000300, +/*1376*/ 0x03000300, +/*1377*/ 0x00000300, +/*1378*/ 0x00000300, +/*1379*/ 0x00000300, +/*137a*/ 0x00000300, +/*137b*/ 0x00000005, +/*137c*/ 0x0004BFCC, +/*137d*/ 0x0000010C, +/*137e*/ 0x0000027F, +/*137f*/ 0x00000000, +/*1380*/ 0x0000027F, +/*1381*/ 0x00000000, +/*1382*/ 0x00127F00, +/*1383*/ 0x0089FF00, +/*1384*/ 0x00827FCC, +/*1385*/ 0x00000000, +/*1386*/ 0x00127F80, +/*1387*/ 0x01980000, +/*1388*/ 0x00127F80, +/*1389*/ 0x01980000, +/*138a*/ 0x00127F00, +/*138b*/ 0x01980000, +/*138c*/ 0x00127F00, +/*138d*/ 0x01980000, +/*138e*/ 0x20040006 +}; + +static const uint32_t DDR_PI_REGSET_S4[DDR_PI_REGSET_NUM_S4] = { +/*0800*/ 0x00000B00, +/*0801*/ 0x00000000, +/*0802*/ 0x00000000, +/*0803*/ 0x00000101, +/*0804*/ 0x00640000, +/*0805*/ 0x00000001, +/*0806*/ 0x00000000, +/*0807*/ 0x00000000, +/*0808*/ 0x00000000, +/*0809*/ 0x00000000, +/*080a*/ 0x00000003, +/*080b*/ 0x00010100, +/*080c*/ 0x08000003, +/*080d*/ 0x00000103, +/*080e*/ 0x00000000, +/*080f*/ 0x00000000, +/*0810*/ 0x00000000, +/*0811*/ 0x00000000, +/*0812*/ 0x00000000, +/*0813*/ 0x00000000, +/*0814*/ 0x0A000000, +/*0815*/ 0x00000028, +/*0816*/ 0x00000100, +/*0817*/ 0x00320003, +/*0818*/ 0x00000000, +/*0819*/ 0x00000000, +/*081a*/ 0x01010102, +/*081b*/ 0x00000000, +/*081c*/ 0x55555A3C, +/*081d*/ 0x00000055, +/*081e*/ 0x000000B5, +/*081f*/ 0x0000004A, +/*0820*/ 0x00000056, +/*0821*/ 0x000000A9, +/*0822*/ 0x000000A9, +/*0823*/ 0x000000B5, +/*0824*/ 0x01000000, +/*0825*/ 0x00010000, +/*0826*/ 0x00030300, +/*0827*/ 0x0000001A, +/*0828*/ 0x000007D0, +/*0829*/ 0x00000300, +/*082a*/ 0x00000000, +/*082b*/ 0x00000000, +/*082c*/ 0x01080000, +/*082d*/ 0x00010101, +/*082e*/ 0x00000000, +/*082f*/ 0x00030000, +/*0830*/ 0x03000100, +/*0831*/ 0x00000017, +/*0832*/ 0x00000000, +/*0833*/ 0x00000000, +/*0834*/ 0x00000000, +/*0835*/ 0x0A0A140A, +/*0836*/ 0x10020300, +/*0837*/ 0x00020805, +/*0838*/ 0x00000404, +/*0839*/ 0x00000000, +/*083a*/ 0x00000000, +/*083b*/ 0x01000101, +/*083c*/ 0x00020203, +/*083d*/ 0x00340000, +/*083e*/ 0x00000000, +/*083f*/ 0x00000000, +/*0840*/ 0x01000000, +/*0841*/ 0x00000000, +/*0842*/ 0x00000800, +/*0843*/ 0x00020002, +/*0844*/ 0x00010001, +/*0845*/ 0x00010000, +/*0846*/ 0x00020002, +/*0847*/ 0x00000002, +/*0848*/ 0x00000000, +/*0849*/ 0x00000000, +/*084a*/ 0x00000000, +/*084b*/ 0x00000000, +/*084c*/ 0x00000000, +/*084d*/ 0x00000000, +/*084e*/ 0x00000000, +/*084f*/ 0x00000000, +/*0850*/ 0x00100400, +/*0851*/ 0x08010100, +/*0852*/ 0x08000000, +/*0853*/ 0x00000100, +/*0854*/ 0x00000000, +/*0855*/ 0x0000AA00, +/*0856*/ 0x00000000, +/*0857*/ 0x00010000, +/*0858*/ 0x00000000, +/*0859*/ 0x00000000, +/*085a*/ 0x00000000, +/*085b*/ 0x00000000, +/*085c*/ 0x00000000, +/*085d*/ 0x00000000, +/*085e*/ 0x00000000, +/*085f*/ 0x00000000, +/*0860*/ 0x00000000, +/*0861*/ 0x00000000, +/*0862*/ 0x00000000, +/*0863*/ 0x00000000, +/*0864*/ 0x00000000, +/*0865*/ 0x00000000, +/*0866*/ 0x00000000, +/*0867*/ 0x00000000, +/*0868*/ 0x00000000, +/*0869*/ 0x00000000, +/*086a*/ 0x00000000, +/*086b*/ 0x00000000, +/*086c*/ 0x00000000, +/*086d*/ 0x00000000, +/*086e*/ 0x00000000, +/*086f*/ 0x00000000, +/*0870*/ 0x00000000, +/*0871*/ 0x00000000, +/*0872*/ 0x00000000, +/*0873*/ 0x00000000, +/*0874*/ 0x00000000, +/*0875*/ 0x00000000, +/*0876*/ 0x00000000, +/*0877*/ 0x00000002, +/*0878*/ 0x01010001, +/*0879*/ 0x00010200, +/*087a*/ 0x04000103, +/*087b*/ 0x01050001, +/*087c*/ 0x00010600, +/*087d*/ 0x00000107, +/*087e*/ 0x00000000, +/*087f*/ 0x00000000, +/*0880*/ 0x00000100, +/*0881*/ 0x00000000, +/*0882*/ 0x00000000, +/*0883*/ 0x00000000, +/*0884*/ 0x00040100, +/*0885*/ 0x00000000, +/*0886*/ 0x00000000, +/*0887*/ 0x01000000, +/*0888*/ 0x00002B2B, +/*0889*/ 0x00000034, +/*088a*/ 0x0000006C, +/*088b*/ 0x120C046C, +/*088c*/ 0x00481248, +/*088d*/ 0x00000006, +/*088e*/ 0x00000046, +/*088f*/ 0x00000256, +/*0890*/ 0x00002073, +/*0891*/ 0x00000256, +/*0892*/ 0x04002073, +/*0893*/ 0x00000404, +/*0894*/ 0x00002A00, +/*0895*/ 0x002A002A, +/*0896*/ 0x01000100, +/*0897*/ 0x00000100, +/*0898*/ 0x00000000, +/*0899*/ 0x00000000, +/*089a*/ 0x00010000, +/*089b*/ 0x00010100, +/*089c*/ 0x00010100, +/*089d*/ 0x15040100, +/*089e*/ 0x0E0E0215, +/*089f*/ 0x00040402, +/*08a0*/ 0x000C0034, +/*08a1*/ 0x00210049, +/*08a2*/ 0x00210049, +/*08a3*/ 0x01000001, +/*08a4*/ 0x00040005, +/*08a5*/ 0x00040216, +/*08a6*/ 0x01000216, +/*08a7*/ 0x00060006, +/*08a8*/ 0x02170100, +/*08a9*/ 0x01000217, +/*08aa*/ 0x02170217, +/*08ab*/ 0x11111111, +/*08ac*/ 0x00001111, +/*08ad*/ 0x0A070600, +/*08ae*/ 0x1F130A0D, +/*08af*/ 0x1F130A14, +/*08b0*/ 0x0000C014, +/*08b1*/ 0x00C01000, +/*08b2*/ 0x00C01000, +/*08b3*/ 0x00021000, +/*08b4*/ 0x00240005, +/*08b5*/ 0x00240216, +/*08b6*/ 0x003E0216, +/*08b7*/ 0x1609003A, +/*08b8*/ 0x00000007, +/*08b9*/ 0x003A003E, +/*08ba*/ 0x00071609, +/*08bb*/ 0x00003E00, +/*08bc*/ 0x1609003A, +/*08bd*/ 0x08000007, +/*08be*/ 0x04010404, +/*08bf*/ 0x01030277, +/*08c0*/ 0x0A0A0320, +/*08c1*/ 0x18272D10, +/*08c2*/ 0x5A752F28, +/*08c3*/ 0x1E202008, +/*08c4*/ 0x272D1016, +/*08c5*/ 0x752F2818, +/*08c6*/ 0x2020085A, +/*08c7*/ 0x0000161E, +/*08c8*/ 0x0000008C, +/*08c9*/ 0x00000578, +/*08ca*/ 0x000040E6, +/*08cb*/ 0x000288FC, +/*08cc*/ 0x000040E6, +/*08cd*/ 0x000288FC, +/*08ce*/ 0x02660006, +/*08cf*/ 0x04040266, +/*08d0*/ 0xC83CC804, +/*08d1*/ 0x0000003C, +/*08d2*/ 0x00040000, +/*08d3*/ 0x0F1166F1, +/*08d4*/ 0x3F740006, +/*08d5*/ 0x0F1166F1, +/*08d6*/ 0x3F740006, +/*08d7*/ 0x0F1166F1, +/*08d8*/ 0x00040006, +/*08d9*/ 0x0F1166F1, +/*08da*/ 0x3F74002E, +/*08db*/ 0x0F1166F1, +/*08dc*/ 0x3F74002E, +/*08dd*/ 0x0F1166F1, +/*08de*/ 0x0000002E +}; + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h new file mode 100644 index 0000000..8cdb901 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h @@ -0,0 +1,302 @@ +/******************************************************************************* + * Copyright (c) 2015-2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +#if defined(__RH850G3K__) +#include "remap_register.h" +#endif + +#define RCAR_DDR_VERSION "rev.0.08rc7" +#define DRAM_CH_CNT 0x04 +#define SLICE_CNT 0x02 +#define CS_CNT 0x02 + +/* for pll setting */ +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) +#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb))) + +/* for ddr density setting */ +#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30) | ((row) << 24) | ((BG) << 20) | ((bank) << 16) | ((col) << 8) | (dw)) +#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (28 - 2 - 2 - 10 - 1), 2, 2, 10, 1)) /* 16bit */ +#define DBMEMCONF_VAL(ch,cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) + +/* system registers : CPG */ +#define CPG_FRQCRD_KICK_BIT (1U << 31) +#define CPG_PLL3CR0_KICK_BIT (1U << 31) + +#define CPG_PLLECR_PLL3E_BIT (1U << 3) +#define CPG_PLLECR_PLL3ST_BIT (1U << 11) + +#if defined(__RH850G3K__) +#define CPG_BASE (BASE_CPG_ADDR) +#else +#define CPG_BASE (0xE6150000U) +#endif +#define CPG_CPGWPR (CPG_BASE + 0x0000U) +#define CPG_CPGWPCR (CPG_BASE + 0x0004U) +#define CPG_FRQCRA (CPG_BASE + 0x0800U) +#define CPG_FRQCRB (CPG_BASE + 0x0804U) +#define CPG_FRQCRC (CPG_BASE + 0x0808U) +#define CPG_FRQCRD0 (CPG_BASE + 0x080CU) +#define CPG_PLLECR (CPG_BASE + 0x0820U) +#define CPG_PLL3CR0 (CPG_BASE + 0x083CU) +#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U) +#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U) +#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U) +#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U) +#define CPG_SRCR4 (CPG_BASE + 0x2C10U) +#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U) + +#define CPG_PLL3FBCKMCSR (CPG_BASE + 0x0C60U) +#define CPG_PLL3FBCKMECR (CPG_BASE + 0x0C64U) +#define CPG_PLL3FBCKMLCH (CPG_BASE + 0x0C68U) +#define CPG_PLL3FBCKMLCL (CPG_BASE + 0x0C6CU) +#define CPG_PLL3FBCKMCNT (CPG_BASE + 0x0C70U) +#define CPG_PLL3FBCKMCNTE (CPG_BASE + 0x0C74U) + +#if defined(__RH850G3K__) +#define RST_BASE (BASE_RESET_ADDR) +#else +#define RST_BASE (0xE6160000U) +#endif +#define RST_MODEMR0 (RST_BASE + 0x0000U) +#define RST_MODEMR1 (RST_BASE + 0x0004U) + +/* Product Register */ +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) + +#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */ + +#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */ +#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */ + +/* DBSC registers */ +#if defined(__RH850G3K__) +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#else +#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#endif + +#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U) +#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U) +#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U) +#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U) +#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U) +#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U) +#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U) +#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U) + +#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs)) +#define DBSC_DBMEMCONF_0_0 (DBSC_D_BASE + 0x0030U) +#define DBSC_DBMEMCONF_0_1 (DBSC_D_BASE + 0x0034U) +#define DBSC_DBMEMCONF_0_2 (DBSC_D_BASE + 0x0038U) +#define DBSC_DBMEMCONF_0_3 (DBSC_D_BASE + 0x003CU) +#define DBSC_DBMEMCONF_1_0 (DBSC_D_BASE + 0x0040U) +#define DBSC_DBMEMCONF_1_1 (DBSC_D_BASE + 0x0044U) +#define DBSC_DBMEMCONF_1_2 (DBSC_D_BASE + 0x0048U) +#define DBSC_DBMEMCONF_1_3 (DBSC_D_BASE + 0x004CU) +#define DBSC_DBMEMCONF_2_0 (DBSC_D_BASE + 0x0050U) +#define DBSC_DBMEMCONF_2_1 (DBSC_D_BASE + 0x0054U) +#define DBSC_DBMEMCONF_2_2 (DBSC_D_BASE + 0x0058U) +#define DBSC_DBMEMCONF_2_3 (DBSC_D_BASE + 0x005CU) +#define DBSC_DBMEMCONF_3_0 (DBSC_D_BASE + 0x0060U) +#define DBSC_DBMEMCONF_3_1 (DBSC_D_BASE + 0x0064U) +#define DBSC_DBMEMCONF_3_2 (DBSC_D_BASE + 0x0068U) +#define DBSC_DBMEMCONF_3_3 (DBSC_D_BASE + 0x006CU) + +#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs)) +#define DBSC_DBMEMCONF_0_0A (DBSC_A_BASE + 0x0030U) +#define DBSC_DBMEMCONF_0_1A (DBSC_A_BASE + 0x0034U) +#define DBSC_DBMEMCONF_0_2A (DBSC_A_BASE + 0x0038U) +#define DBSC_DBMEMCONF_0_3A (DBSC_A_BASE + 0x003CU) +#define DBSC_DBMEMCONF_1_0A (DBSC_A_BASE + 0x0040U) +#define DBSC_DBMEMCONF_1_1A (DBSC_A_BASE + 0x0044U) +#define DBSC_DBMEMCONF_1_2A (DBSC_A_BASE + 0x0048U) +#define DBSC_DBMEMCONF_1_3A (DBSC_A_BASE + 0x004CU) +#define DBSC_DBMEMCONF_2_0A (DBSC_A_BASE + 0x0050U) +#define DBSC_DBMEMCONF_2_1A (DBSC_A_BASE + 0x0054U) +#define DBSC_DBMEMCONF_2_2A (DBSC_A_BASE + 0x0058U) +#define DBSC_DBMEMCONF_2_3A (DBSC_A_BASE + 0x005CU) +#define DBSC_DBMEMCONF_3_0A (DBSC_A_BASE + 0x0060U) +#define DBSC_DBMEMCONF_3_1A (DBSC_A_BASE + 0x0064U) +#define DBSC_DBMEMCONF_3_2A (DBSC_A_BASE + 0x0068U) +#define DBSC_DBMEMCONF_3_3A (DBSC_A_BASE + 0x006CU) + +#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U) + +#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U) +#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U) +#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U) +#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U) + +#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + 0x04U * (x)) +#define DBSC_DBTR0 (DBSC_D_BASE + 0x0300U) +#define DBSC_DBTR1 (DBSC_D_BASE + 0x0304U) +#define DBSC_DBTR2 (DBSC_D_BASE + 0x0308U) +#define DBSC_DBTR3 (DBSC_D_BASE + 0x030CU) +#define DBSC_DBTR4 (DBSC_D_BASE + 0x0310U) +#define DBSC_DBTR5 (DBSC_D_BASE + 0x0314U) +#define DBSC_DBTR6 (DBSC_D_BASE + 0x0318U) +#define DBSC_DBTR7 (DBSC_D_BASE + 0x031CU) +#define DBSC_DBTR8 (DBSC_D_BASE + 0x0320U) +#define DBSC_DBTR9 (DBSC_D_BASE + 0x0324U) +#define DBSC_DBTR10 (DBSC_D_BASE + 0x0328U) +#define DBSC_DBTR11 (DBSC_D_BASE + 0x032CU) +#define DBSC_DBTR12 (DBSC_D_BASE + 0x0330U) +#define DBSC_DBTR13 (DBSC_D_BASE + 0x0334U) +#define DBSC_DBTR14 (DBSC_D_BASE + 0x0338U) +#define DBSC_DBTR15 (DBSC_D_BASE + 0x033CU) +#define DBSC_DBTR16 (DBSC_D_BASE + 0x0340U) +#define DBSC_DBTR17 (DBSC_D_BASE + 0x0344U) +#define DBSC_DBTR18 (DBSC_D_BASE + 0x0348U) +#define DBSC_DBTR19 (DBSC_D_BASE + 0x034CU) +#define DBSC_DBTR20 (DBSC_D_BASE + 0x0350U) +#define DBSC_DBTR21 (DBSC_D_BASE + 0x0354U) +#define DBSC_DBTR22 (DBSC_D_BASE + 0x0358U) +#define DBSC_DBTR23 (DBSC_D_BASE + 0x035CU) +#define DBSC_DBTR24 (DBSC_D_BASE + 0x0360U) +#define DBSC_DBTR25 (DBSC_D_BASE + 0x0364U) +#define DBSC_DBTR26 (DBSC_D_BASE + 0x0368U) +#define DBSC_DBTR27 (DBSC_D_BASE + 0x036CU) +#define DBSC_DBTR28 (DBSC_D_BASE + 0x0370U) +#define DBSC_DBTR29 (DBSC_D_BASE + 0x0374U) +#define DBSC_DBTR30 (DBSC_D_BASE + 0x0378U) +#define DBSC_DBTR31 (DBSC_D_BASE + 0x037CU) +#define DBSC_DBTR32 (DBSC_D_BASE + 0x0380U) +#define DBSC_DBTR33 (DBSC_D_BASE + 0x0384U) +#define DBSC_DBTR34 (DBSC_D_BASE + 0x0388U) +#define DBSC_DBTR35 (DBSC_D_BASE + 0x038CU) +#define DBSC_DBTR36 (DBSC_D_BASE + 0x0390U) +#define DBSC_DBTR37 (DBSC_D_BASE + 0x0394U) + +#define DBSC_DBBL (DBSC_D_BASE + 0x0400U) +#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U) + +#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U) +#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U) + +#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U) + +#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + 0x04U * (x)) +#define DBSC_DBRNK2 (DBSC_D_BASE + 0x0438U) +#define DBSC_DBRNK3 (DBSC_D_BASE + 0x043CU) +#define DBSC_DBRNK4 (DBSC_D_BASE + 0x0440U) +#define DBSC_DBRNK5 (DBSC_D_BASE + 0x0444U) + +#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U) +#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U) +#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U) + +#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBDFISTAT_0 (DBSC_D_BASE + 0x0600U) +#define DBSC_DBDFISTAT_1 (DBSC_D_BASE + 0x0640U) +#define DBSC_DBDFISTAT_2 (DBSC_D_BASE + 0x0680U) +#define DBSC_DBDFISTAT_3 (DBSC_D_BASE + 0x06C0U) + +#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBDFICNT_0 (DBSC_D_BASE + 0x0604U) +#define DBSC_DBDFICNT_1 (DBSC_D_BASE + 0x0644U) +#define DBSC_DBDFICNT_2 (DBSC_D_BASE + 0x0684U) +#define DBSC_DBDFICNT_3 (DBSC_D_BASE + 0x06C4U) + +#define DBSC_DBPDCNT0_0 (DBSC_D_BASE + 0x0610U) +#define DBSC_DBPDCNT0_1 (DBSC_D_BASE + 0x0614U) +#define DBSC_DBPDCNT0_2 (DBSC_D_BASE + 0x0618U) +#define DBSC_DBPDCNT0_3 (DBSC_D_BASE + 0x061CU) + +#define DBSC_DBPDCNT1_0 (DBSC_D_BASE + 0x0650U) +#define DBSC_DBPDCNT1_1 (DBSC_D_BASE + 0x0654U) +#define DBSC_DBPDCNT1_2 (DBSC_D_BASE + 0x0658U) +#define DBSC_DBPDCNT1_3 (DBSC_D_BASE + 0x065CU) + +#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDCNT2_0 (DBSC_D_BASE + 0x0690U) +#define DBSC_DBPDCNT2_1 (DBSC_D_BASE + 0x0694U) +#define DBSC_DBPDCNT2_2 (DBSC_D_BASE + 0x0698U) +#define DBSC_DBPDCNT2_3 (DBSC_D_BASE + 0x069CU) + +#define DBSC_DBPDCNT3_0 (DBSC_D_BASE + 0x06D0U) +#define DBSC_DBPDCNT3_1 (DBSC_D_BASE + 0x06D4U) +#define DBSC_DBPDCNT3_2 (DBSC_D_BASE + 0x06D8U) +#define DBSC_DBPDCNT3_3 (DBSC_D_BASE + 0x06DCU) + +#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDLK_0 (DBSC_D_BASE + 0x0620U) +#define DBSC_DBPDLK_1 (DBSC_D_BASE + 0x0660U) +#define DBSC_DBPDLK_2 (DBSC_D_BASE + 0x06a0U) +#define DBSC_DBPDLK_3 (DBSC_D_BASE + 0x06e0U) + +#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDRGA_0 (DBSC_D_BASE + 0x0624U) +#define DBSC_DBPDRGA_1 (DBSC_D_BASE + 0x0664U) +#define DBSC_DBPDRGA_2 (DBSC_D_BASE + 0x06A4U) +#define DBSC_DBPDRGA_3 (DBSC_D_BASE + 0x06E4U) + +#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDRGD_0 (DBSC_D_BASE + 0x0628U) +#define DBSC_DBPDRGD_1 (DBSC_D_BASE + 0x0668U) +#define DBSC_DBPDRGD_2 (DBSC_D_BASE + 0x06A8U) +#define DBSC_DBPDRGD_3 (DBSC_D_BASE + 0x06E8U) + +#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDSTAT0_0 (DBSC_D_BASE + 0x0630U) +#define DBSC_DBPDSTAT1_0 (DBSC_D_BASE + 0x0670U) + +#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDSTAT0_1 (DBSC_D_BASE + 0x0634U) +#define DBSC_DBPDSTA1T_1 (DBSC_D_BASE + 0x0674U) + +#define DBSC_DBCAM0CTRL0 (DBSC_A_BASE + 0x0940U) + +#define DBSC_DBCAMSTAT0(x) (DBSC_A_BASE + 0x0980U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U)) +#define DBSC_DBCAM0STAT0 (DBSC_A_BASE + 0x0980U) +#define DBSC_DBCAM1STAT0 (DBSC_A_BASE + 0x0990U) +#define DBSC_DBCAM2STAT0 (DBSC_A_BASE + 0x09A0U) +#define DBSC_DBCAM3STAT0 (DBSC_A_BASE + 0x09B0U) + +#define DBSC_DBCAMSTAT1(x) (DBSC_A_BASE + 0x0984U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U)) +#define DBSC_DBCAM0STAT1 (DBSC_A_BASE + 0x0984U) +#define DBSC_DBCAM1STAT1 (DBSC_A_BASE + 0x0994U) +#define DBSC_DBCAM2STAT1 (DBSC_A_BASE + 0x09A4U) +#define DBSC_DBCAM3STAT1 (DBSC_A_BASE + 0x09B4U) + +#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU) + +#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U) + +#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U) + +#define DBSC_DBSCHFCTST01(x) (DBSC_A_BASE + 0x1040U + 0x04U * (x)) +#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U) +#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U) + +#define DBSC_DBSCHQOS(x,y) (DBSC_A_BASE + 0x1100U + 0x10U * (x) + 0x04U * (y)) diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c new file mode 100644 index 0000000..badbd04 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c @@ -0,0 +1,220 @@ +/******************************************************************************* + * Copyright (c) 2022-2025 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC setting function + ******************************************************************************/ +/****************************************************************************** + * @file ecc_enable_v4h.c + * - Version : 0.06 + * @brief Enable setting process of ECC for DRAM. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 09.08.2022 0.01 First Release + * : 22.03.2023 0.02 Added AXI Timeout setting + * : 04.04.2023 0.03 Removed stdio.h and string.h. + * : 24.08.2023 0.04 Removed enable_ecc function. + * : 13.06.2024 0.05 Fix register setting for EDC_CFG, and revise + * : the ecm_lock()/ecm_unlock() process. + * : 07.04.2025 0.06 Remove unused functions. + *****************************************************************************/ + +#include +#include +#include +#include + +#if (ECM_ENABLE == 1) +#include "ecc_enable_v4h.h" +#include "v4h/lpddr5/boot_init_dram_regdef.h" +#include "ecm_enable_v4h.h" + +#define AXI_SICREMAP_NUM (5U) +#define RGID_BASE1 (0xFE600000U) +#define RGID_BASE2 (0xE7A00000U) +#define RGID_BASE3 (0xEB800000U) +#define RGID_BASE4 (0xFD800000U) +#define RGID_BASE5 (0xFEA00000U) + +#define FDT_COUNTER_MASK (0x0000FFFFU) + +static void axi_timeout_setting(void); + +void edc_axi_enable(void) +{ + uint32_t edc_tmp; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers + to inform the external device of the error via the ERROROUT# pin. */ + + /* Set bit 11 - bit 2 of ECMERRTGTR7 to all 0 and bit 11 - bit 2 of + ECMERRCTLR7 to 1. (Error of AXI-Bus ECM of each hierarchy) */ + edc_tmp = mem_read32(ECMERRTGTR7); + edc_tmp &= ~(0x3FFU << 2U); + ecm_write(ECMERRTGTR7, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR7); + edc_tmp |= (0x3FFU << 2U); + ecm_write(ECMERRCTLR7, edc_tmp); + + /* Set bit 28 - bit 16 of ECMERRTGTR39 to all 0 and bit 28 - bit 16 of + ECMERRCTLR39 to 1. (Error of AXI-Bus ECM of each hierarchy) */ + edc_tmp = mem_read32(ECMERRTGTR39); + edc_tmp &= ~(0x1FFFU << 16U); + ecm_write(ECMERRTGTR39, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR39); + edc_tmp |= (0x1FFFU << 16U); + ecm_write(ECMERRCTLR39, edc_tmp); + + /* Set bit 26 of ECMERRTGTR1 to 0 and bit 26 of + ECMERRCTLR1 to 1. (CCI bus EDC error) */ + edc_tmp = mem_read32(ECMERRTGTR1); + edc_tmp &= ~(0x1U << 26U); + ecm_write(ECMERRTGTR1, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR1); + edc_tmp |= (0x1U << 26U); + ecm_write(ECMERRCTLR1, edc_tmp); + + axi_timeout_setting(); + + /* Lock the ECM registers */ + ecm_lock(); +} + +void edc_vram_enable(void) +{ + uint32_t edc_tmp; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers + to inform the external device of the error via the ERROROUT# pin. */ + + /* Set bit 30 of ECMERRTGTR7 to 0 and bit 30 of ECMERRCTLR7 to 1. + (RT-VRAM edc 1-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR7); + edc_tmp &= ~(0x1U << 30U); + ecm_write(ECMERRTGTR7, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR7); + edc_tmp |= (0x1U << 30U); + ecm_write(ECMERRCTLR7, edc_tmp); + + /* Set bit 29 of ECMERRTGTR7 to 0 and bit 29 of ECMERRCTLR7 to 1. + (RT-VRAM edc multi-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR7); + edc_tmp &= ~(0x1U << 29U); + ecm_write(ECMERRTGTR7, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR7); + edc_tmp |= (0x1U << 29U); + ecm_write(ECMERRCTLR7, edc_tmp); + + /* Set bit 19 of ECMERRTGTR17 to 0 and bit 19 of ECMERRCTLR17 to 1. + (RT-VRAM edc 1-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR17); + edc_tmp &= ~(0x1U << 19U); + ecm_write(ECMERRTGTR17, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR17); + edc_tmp |= (0x1U << 19U); + ecm_write(ECMERRCTLR17, edc_tmp); + + /* Set bit 18 of ECMERRTGTR17 to 0 and bit 18 of ECMERRCTLR17 to 1. + (RT-VRAM edc multi-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR17); + edc_tmp &= ~(0x1U << 18U); + ecm_write(ECMERRTGTR17, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR17); + edc_tmp |= (0x1U << 18U); + ecm_write(ECMERRCTLR17, edc_tmp); + + /* Set bit 0 of EDC_CFG to 1. (EDC Error Control) */ + edc_tmp = mem_read32(EDC_CFG); + edc_tmp |= (0x1U << 0U); + mem_write32(EDC_CFG, edc_tmp); + + /* Lock the ECM registers */ + ecm_lock(); +} + +static void axi_timeout_setting(void) +{ + uint32_t reg; + uint32_t loop; + REMAP_TABLE axi_remap_tbl[AXI_SICREMAP_NUM] = { + {RGID_BASE1, 0U}, + {RGID_BASE2, 0U}, + {RGID_BASE3, 0U}, + {RGID_BASE4, 0U}, + {RGID_BASE5, 0U}, + }; + + /* Register of AXI Base */ + for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++) + { + remap_register(axi_remap_tbl[loop].base_addr, &axi_remap_tbl[loop].rmp_addr); + } + + /* Set the COUNTER bits of the FDT_* registers for all safety-related modules to minimum value with 1ms or more. */ + for (loop = 0U; loop < FDT_REG_MAX; loop++) + { + reg = mem_read32(g_fdt_tbl[loop].reg_addr); + reg &= ~(FDT_COUNTER_MASK); + reg |= g_fdt_tbl[loop].value; + mem_write32(g_fdt_tbl[loop].reg_addr, reg); + + INFO("FDT[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_fdt_tbl[loop].reg_addr), g_fdt_tbl[loop].value); + } + + for(loop = 0U; loop < INTEN_REG_MAX; loop++) + { + /* Set access protection setting value of Region ID (AXI bus of Region ID register) */ + mem_write32(g_inten_tbl[loop].reg_addr, g_inten_tbl[loop].value); + + INFO("INTEN[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_inten_tbl[loop].reg_addr), g_inten_tbl[loop].value); + } + + /* Unregister of AXI Base */ + for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++) + { + remap_unregister(axi_remap_tbl[loop].rmp_addr); + } + + wdt_restart(); +} +#endif /* ECM_ENABLE == 1 */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h new file mode 100644 index 0000000..8a04f4b --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h @@ -0,0 +1,123 @@ +/******************************************************************************* + * Copyright (c) 2022-2024 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC driver header + ******************************************************************************/ + +#ifndef ECC_PROTECT +#define ECC_PROTECT +#include "remap_register.h" +/* DBSC registers */ +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#define ECM_BASE (BASE_ECC_ADDR) +#else +#include +#include +#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#define ECM_BASE (0xE6250000U) +#endif/* defined(__RH850G3K__) */ + +#define RTVRAM_REG_BASE (0xFFEC0000U) + +void edc_axi_enable(void); +void edc_vram_enable(void); + +#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U) +#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U) +#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U) + +#define DBSC_DBACEN0 (DBSC_A_BASE + 0x0200U) +#define DBSC_DBACEN1 (DBSC_DBACEN0 + 0x8000U) + +#define ECMWACNTR (ECM_BASE + 0x0A04U) +#define ECMWPCNTR (ECM_BASE + 0x0A00U) +#define ECMERRTGTR0 (ECM_BASE + 0x0200U) +#define ECMERRCTLR0 (ECM_BASE + 0x0000U) +#define ECMERRTGTR1 (ECM_BASE + 0x0200U + 0x4U * 1U) +#define ECMERRCTLR1 (ECM_BASE + 0x0000U + 0x4U * 1U) +#define ECMERRTGTR7 (ECM_BASE + 0x0200U + 0x4U * 7U) +#define ECMERRCTLR7 (ECM_BASE + 0x0000U + 0x4U * 7U) +#define ECMERRTGTR17 (ECM_BASE + 0x0200U + 0x4U * 17U) +#define ECMERRCTLR17 (ECM_BASE + 0x0000U + 0x4U * 17U) +#define ECMERRTGTR39 (ECM_BASE + 0x0200U + 0x4U * 39U) +#define ECMERRCTLR39 (ECM_BASE + 0x0000U + 0x4U * 39U) +#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U) +#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U) +#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U) +#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U) +#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U) +#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U) +#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U) +#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U) +#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U) +#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U) +#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U) +#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U) +#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U) +#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U) +#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U) +#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U) + +#define DB0FSDRAMECCAREA0 (DBSC_A_BASE + 0x7450U) +#define DB0FSDRAMECCAREA1 (DBSC_A_BASE + 0x7454U) +#define DB1FSDRAMECCAREA0 (DB0FSDRAMECCAREA0 + 0x8000U) +#define DB1FSDRAMECCAREA1 (DB0FSDRAMECCAREA1 + 0x8000U) + +#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U) +#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U) + +#define EDC_CFG (RTVRAM_REG_BASE + 0x4110U) + +/********************* Set by the user *********************/ +/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */ +#define ECC_PROT_SIZE00 (0x1000U) +#define ECC_PROT_SIZE01 (0x1000U) +#define ECC_PROT_SIZE10 (0x1000U) +#define ECC_PROT_SIZE11 (0x1000U) + +/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */ +#define START_ECC_INIT_AREA00 (0x00000000U) +#define START_ECC_INIT_AREA10 (0x00000000U) +#define END_ECC_INIT_AREA00 (0x00000FFFU) +#define END_ECC_INIT_AREA10 (0x00000FFFU) + +/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */ +#define START_ECC_INIT_AREA01 (0x00000000U) +#define START_ECC_INIT_AREA11 (0x00000000U) +#define END_ECC_INIT_AREA01 (0x00000FFFU) +#define END_ECC_INIT_AREA11 (0x00000FFFU) +/*********** Other settings cannot be changed ***************/ + +#endif/* ECC_PROTECT */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c new file mode 100644 index 0000000..fe88dd5 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c @@ -0,0 +1,531 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM initialize function + ******************************************************************************/ +/****************************************************************************** + * @file ecm_enable_v4h.c + * - Version : 0.01 + * @brief ECM setting. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.01.2025 0.01 First Release + *****************************************************************************/ + +#include +#include "ecm_enable_v4h.h" + +#if (ECM_ERROR_ENABLE == 1) +#include "log.h" +#endif /* ECM_ERROR_ENABLE == 1 */ +#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1)) +#include "ecc_enable_v4h.h" +#include "mem_io.h" +#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +#define TYPE1_ECM_REG_MAX (13U) +#define TYPE2_ECM_REG_MAX (22U) +#define TYPE3_ECM_CTLREG_MAX (1U) +#define TYPE3_ECM_TGTREG_MAX (2U) + +typedef struct{ + uint32_t phys_addr; /* Physical address of ECM registers. */ + uint32_t value; /* Setting value of ECM registers. */ +} ECM_ERROR_TABLE; +#endif /* ECM_ERROR_ENABLE == 1 */ + +#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1)) +void ecm_unlock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0001U); +} + +void ecm_write(uint32_t adr, uint32_t val) +{ + mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU))); + mem_write32(adr, val); +} + +void ecm_lock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0000U); +} +#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_init_setting(void) +{ + uint32_t reg; + uint32_t loop; + + const ECM_ERROR_TABLE ecmerrctlr_type1_tbl[TYPE1_ECM_REG_MAX] = { + [0] = {0xFD850000U, 0x00381000U}, /* ECMERRCTLR0 */ + [1] = {0xFD850004U, 0xA400C000U}, /* ECMERRCTLR1 */ + /* Skip ECMERRCTLR2 setting */ + /* Skip ECMERRCTLR3 setting */ + /* Skip ECMERRCTLR4 setting */ + /* Skip ECMERRCTLR5 setting */ + [2] = {0xFD850018U, 0xCC000000U}, /* ECMERRCTLR6 */ + [3] = {0xFD85001CU, 0x0C000000U}, /* ECMERRCTLR7 */ + /* Skip ECMERRCTLR8 setting */ + /* Skip ECMERRCTLR9 setting */ + /* Skip ECMERRCTLR10 setting */ + /* Skip ECMERRCTLR11 setting */ + /* Skip ECMERRCTLR12 setting */ + /* Skip ECMERRCTLR13 setting */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + /* Skip ECMERRCTLR16 setting */ + [4] = {0xFD850044U, 0x2D000000U}, /* ECMERRCTLR17 */ + [5] = {0xFD850048U, 0x0EC0003FU}, /* ECMERRCTLR18 */ + [6] = {0xFD85004CU, 0x00FFFF08U}, /* ECMERRCTLR19 */ + [7] = {0xFD850050U, 0x0000001EU}, /* ECMERRCTLR20 */ + [8] = {0xFD850054U, 0x9F800000U}, /* ECMERRCTLR21 */ + /* Skip ECMERRCTLR22 setting */ + /* Skip ECMERRCTLR23 setting */ + /* Skip ECMERRCTLR24 setting */ + /* Skip ECMERRCTLR25 setting */ + /* Skip ECMERRCTLR26 setting */ + /* Skip ECMERRCTLR27 setting */ + /* Skip ECMERRCTLR28 setting */ + /* Skip ECMERRCTLR29 setting */ + /* Skip ECMERRCTLR30 setting */ + /* Skip ECMERRCTLR31 setting */ + /* Skip ECMERRCTLR32 setting */ + /* Skip ECMERRCTLR33 setting */ + /* Skip ECMERRCTLR34 setting */ + [9] = {0xFD85008CU, 0x300003C0U}, /* ECMERRCTLR35 */ + /* Skip ECMERRCTLR36 setting */ + /* Skip ECMERRCTLR37 setting */ + [10] = {0xFD850098U, 0x33300054U}, /* ECMERRCTLR38 */ + /* Skip ECMERRCTLR39 setting */ + /* Skip ECMERRCTLR40 setting */ + [11] = {0xFD8500A4U, 0x01000880U}, /* ECMERRCTLR41 */ + [12] = {0xFD8500A8U, 0x00040020U}, /* ECMERRCTLR42 */ + }; + + const ECM_ERROR_TABLE ecmerrtgtr_type1_tbl[TYPE1_ECM_REG_MAX] = { + [0] = {0xFD850200U, 0x00381000U}, /* ECMERRTGTR0 */ + [1] = {0xFD850204U, 0xA400C000U}, /* ECMERRTGTR1 */ + /* Skip ECMERRTGTR2 setting */ + /* Skip ECMERRTGTR3 setting */ + /* Skip ECMERRTGTR4 setting */ + /* Skip ECMERRTGTR5 setting */ + [2] = {0xFD850218U, 0xCC000000U}, /* ECMERRTGTR6 */ + [3] = {0xFD85021CU, 0x0C000000U}, /* ECMERRTGTR7 */ + /* Skip ECMERRTGTR8 setting */ + /* Skip ECMERRTGTR9 setting */ + /* Skip ECMERRTGTR10 setting */ + /* Skip ECMERRTGTR11 setting */ + /* Skip ECMERRTGTR12 setting */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + /* Skip ECMERRTGTR16 setting */ + [4] = {0xFD850244U, 0x2D000000U}, /* ECMERRTGTR17 */ + [5] = {0xFD850248U, 0x0EC0003FU}, /* ECMERRTGTR18 */ + [6] = {0xFD85024CU, 0x00FFFF08U}, /* ECMERRTGTR19 */ + [7] = {0xFD850250U, 0x0000001EU}, /* ECMERRTGTR20 */ + [8] = {0xFD850254U, 0x9F800000U}, /* ECMERRTGTR21 */ + /* Skip ECMERRTGTR22 setting */ + /* Skip ECMERRTGTR23 setting */ + /* Skip ECMERRTGTR24 setting */ + /* Skip ECMERRTGTR25 setting */ + /* Skip ECMERRTGTR26 setting */ + /* Skip ECMERRTGTR27 setting */ + /* Skip ECMERRTGTR28 setting */ + /* Skip ECMERRTGTR29 setting */ + /* Skip ECMERRTGTR30 setting */ + /* Skip ECMERRTGTR31 setting */ + /* Skip ECMERRTGTR32 setting */ + /* Skip ECMERRTGTR33 setting */ + /* Skip ECMERRTGTR34 setting */ + [9] = {0xFD85028CU, 0x300003C0U}, /* ECMERRTGTR35 */ + /* Skip ECMERRTGTR36 setting */ + /* Skip ECMERRTGTR37 setting */ + [10] = {0xFD850298U, 0x33300054U}, /* ECMERRTGTR38 */ + /* Skip ECMERRTGTR39 setting */ + /* Skip ECMERRTGTR40 setting */ + [11] = {0xFD8502A4U, 0x01000880U}, /* ECMERRTGTR41 */ + [12] = {0xFD8502A8U, 0x00040020U}, /* ECMERRTGTR42 */ + }; + + const ECM_ERROR_TABLE ecmerrctlr_type2_tbl[TYPE2_ECM_REG_MAX] = { + [0] = {0xFD850000U, 0x4000000FU}, /* ECMERRCTLR0 */ + [1] = {0xFD850004U, 0x1C004000U}, /* ECMERRCTLR1 */ + [2] = {0xFD850008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */ + [3] = {0xFD85000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */ + [4] = {0xFD850010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */ + [5] = {0xFD850014U, 0xC1FFFFFFU}, /* ECMERRCTLR5 */ + [6] = {0xFD850018U, 0x15000A80U}, /* ECMERRCTLR6 */ + [7] = {0xFD85001CU, 0x00803481U}, /* ECMERRCTLR7 */ + /* Skip ECMERRCTLR8 setting */ + /* Skip ECMERRCTLR9 setting */ + /* Skip ECMERRCTLR10 setting */ + /* Skip ECMERRCTLR11 setting */ + /* Skip ECMERRCTLR12 setting */ + /* Skip ECMERRCTLR13 setting */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + [8] = {0xFD850040U, 0x00003E9FU}, /* ECMERRCTLR16 */ + [9] = {0xFD850044U, 0x00938060U}, /* ECMERRCTLR17 */ + [10] = {0xFD850048U, 0x003C1FC0U}, /* ECMERRCTLR18 */ + [11] = {0xFD85004CU, 0xFF0000F0U}, /* ECMERRCTLR19 */ + [12] = {0xFD850050U, 0x02222220U}, /* ECMERRCTLR20 */ + [13] = {0xFD850054U, 0x0061BE0FU}, /* ECMERRCTLR21 */ + /* Skip ECMERRCTLR22 setting */ + /* Skip ECMERRCTLR23 setting */ + /* Skip ECMERRCTLR24 setting */ + /* Skip ECMERRCTLR25 setting */ + /* Skip ECMERRCTLR26 setting */ + /* Skip ECMERRCTLR27 setting */ + /* Skip ECMERRCTLR28 setting */ + /* Skip ECMERRCTLR29 setting */ + /* Skip ECMERRCTLR30 setting */ + /* Skip ECMERRCTLR31 setting */ + [14] = {0xFD850080U, 0x03E9043BU}, /* ECMERRCTLR32 */ + [15] = {0xFD850084U, 0x03E9043BU}, /* ECMERRCTLR33 */ + /* Skip ECMERRCTLR34 setting */ + [16] = {0xFD85008CU, 0xC3F00C00U}, /* ECMERRCTLR35 */ + [17] = {0xFD850090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */ + /* Skip ECMERRCTLR37 setting */ + [18] = {0xFD850098U, 0x00000002U}, /* ECMERRCTLR38 */ + /* Skip ECMERRCTLR39 setting */ + [19] = {0xFD8500A0U, 0x000067FEU}, /* ECMERRCTLR40 */ + [20] = {0xFD8500A4U, 0x20010000U}, /* ECMERRCTLR41 */ + [21] = {0xFD8500A8U, 0x00800400U}, /* ECMERRCTLR42 */ + }; + + const ECM_ERROR_TABLE ecmerrtgtr_type2_tbl[TYPE2_ECM_REG_MAX] = { + [0] = {0xFD850200U, 0x4000000FU}, /* ECMERRTGTR0 */ + [1] = {0xFD850204U, 0x1C004000U}, /* ECMERRTGTR1 */ + [2] = {0xFD850208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */ + [3] = {0xFD85020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */ + [4] = {0xFD850210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */ + [5] = {0xFD850214U, 0xC1FFFFFFU}, /* ECMERRTGTR5 */ + [6] = {0xFD850218U, 0x15000A80U}, /* ECMERRTGTR6 */ + [7] = {0xFD85021CU, 0x00803481U}, /* ECMERRTGTR7 */ + /* Skip ECMERRTGTR8 setting */ + /* Skip ECMERRTGTR9 setting */ + /* Skip ECMERRTGTR10 setting */ + /* Skip ECMERRTGTR11 setting */ + /* Skip ECMERRTGTR12 setting */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [8] = {0xFD850240U, 0x00003E9FU}, /* ECMERRTGTR16 */ + [9] = {0xFD850244U, 0x00938060U}, /* ECMERRTGTR17 */ + [10] = {0xFD850248U, 0x003C1FC0U}, /* ECMERRTGTR18 */ + [11] = {0xFD85024CU, 0xFF0000F0U}, /* ECMERRTGTR19 */ + [12] = {0xFD850250U, 0x02222220U}, /* ECMERRTGTR20 */ + [13] = {0xFD850254U, 0x0061BE0FU}, /* ECMERRTGTR21 */ + /* Skip ECMERRTGTR22 setting */ + /* Skip ECMERRTGTR23 setting */ + /* Skip ECMERRTGTR24 setting */ + /* Skip ECMERRTGTR25 setting */ + /* Skip ECMERRTGTR26 setting */ + /* Skip ECMERRTGTR27 setting */ + /* Skip ECMERRTGTR28 setting */ + /* Skip ECMERRTGTR29 setting */ + /* Skip ECMERRTGTR30 setting */ + /* Skip ECMERRTGTR31 setting */ + [14] = {0xFD850280U, 0x03E9043BU}, /* ECMERRTGTR32 */ + [15] = {0xFD850284U, 0x03E9043BU}, /* ECMERRTGTR33 */ + /* Skip ECMERRTGTR34 setting */ + [16] = {0xFD85028CU, 0xC3F00C00U}, /* ECMERRTGTR35 */ + [17] = {0xFD850290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */ + /* Skip ECMERRTGTR37 setting */ + [18] = {0xFD850298U, 0x00000002U}, /* ECMERRTGTR38 */ + /* Skip ECMERRTGTR39 setting */ + [19] = {0xFD8502A0U, 0x000067FEU}, /* ECMERRTGTR40 */ + [20] = {0xFD8502A4U, 0x20010000U}, /* ECMERRTGTR41 */ + [21] = {0xFD8502A8U, 0x00800400U}, /* ECMERRTGTR42 */ + }; + + const ECM_ERROR_TABLE ecmerrctlr_type3_tbl[TYPE3_ECM_CTLREG_MAX] = { + /* Skip ECMERRCTLR0 setting */ + /* Skip ECMERRCTLR1 setting */ + /* Skip ECMERRCTLR2 setting */ + /* Skip ECMERRCTLR3 setting */ + /* Skip ECMERRCTLR4 setting */ + /* Skip ECMERRCTLR5 setting */ + /* Skip ECMERRCTLR6 setting */ + /* Skip ECMERRCTLR7 setting */ + /* Skip ECMERRCTLR8 setting */ + /* Skip ECMERRCTLR9 setting */ + /* Skip ECMERRCTLR10 setting */ + /* Skip ECMERRCTLR11 setting */ + /* Skip ECMERRCTLR12 setting */ + /* Skip ECMERRCTLR13 setting */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + [0] = {0xFD850040U, 0x3FFFC000U}, /* ECMERRCTLR16 */ + /* Skip ECMERRCTLR17 setting */ + /* Skip ECMERRCTLR18 setting */ + /* Skip ECMERRCTLR19 setting */ + /* Skip ECMERRCTLR20 setting */ + /* Skip ECMERRCTLR21 setting */ + /* Skip ECMERRCTLR22 setting */ + /* Skip ECMERRCTLR23 setting */ + /* Skip ECMERRCTLR24 setting */ + /* Skip ECMERRCTLR25 setting */ + /* Skip ECMERRCTLR26 setting */ + /* Skip ECMERRCTLR27 setting */ + /* Skip ECMERRCTLR28 setting */ + /* Skip ECMERRCTLR29 setting */ + /* Skip ECMERRCTLR30 setting */ + /* Skip ECMERRCTLR31 setting */ + /* Skip ECMERRCTLR32 setting */ + /* Skip ECMERRCTLR33 setting */ + /* Skip ECMERRCTLR34 setting */ + /* Skip ECMERRCTLR35 setting */ + /* Skip ECMERRCTLR36 setting */ + /* Skip ECMERRCTLR37 setting */ + /* Skip ECMERRCTLR38 setting */ + /* Skip ECMERRCTLR39 setting */ + /* Skip ECMERRCTLR40 setting */ + /* Skip ECMERRCTLR41 setting */ + /* Skip ECMERRCTLR42 setting */ + }; + + const ECM_ERROR_TABLE ecmerrtgtr_type3_tbl[TYPE3_ECM_TGTREG_MAX] = { + [0] = {0xFD850200U, 0x80000000U}, /* ECMERRTGTR0 */ + /* Skip ECMERRTGTR1 setting */ + /* Skip ECMERRTGTR2 setting */ + /* Skip ECMERRTGTR3 setting */ + /* Skip ECMERRTGTR4 setting */ + /* Skip ECMERRTGTR5 setting */ + /* Skip ECMERRTGTR6 setting */ + /* Skip ECMERRTGTR7 setting */ + /* Skip ECMERRTGTR8 setting */ + /* Skip ECMERRTGTR9 setting */ + /* Skip ECMERRTGTR10 setting */ + /* Skip ECMERRTGTR11 setting */ + /* Skip ECMERRTGTR12 setting */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [1] = {0xFD850240U, 0x3FFFC000U}, /* ECMERRTGTR16 */ + /* Skip ECMERRTGTR17 setting */ + /* Skip ECMERRTGTR18 setting */ + /* Skip ECMERRTGTR19 setting */ + /* Skip ECMERRTGTR20 setting */ + /* Skip ECMERRTGTR21 setting */ + /* Skip ECMERRTGTR22 setting */ + /* Skip ECMERRTGTR23 setting */ + /* Skip ECMERRTGTR24 setting */ + /* Skip ECMERRTGTR25 setting */ + /* Skip ECMERRTGTR26 setting */ + /* Skip ECMERRTGTR27 setting */ + /* Skip ECMERRTGTR28 setting */ + /* Skip ECMERRTGTR29 setting */ + /* Skip ECMERRTGTR30 setting */ + /* Skip ECMERRTGTR31 setting */ + /* Skip ECMERRTGTR32 setting */ + /* Skip ECMERRTGTR33 setting */ + /* Skip ECMERRTGTR34 setting */ + /* Skip ECMERRTGTR35 setting */ + /* Skip ECMERRTGTR36 setting */ + /* Skip ECMERRTGTR37 setting */ + /* Skip ECMERRTGTR38 setting */ + /* Skip ECMERRTGTR39 setting */ + /* Skip ECMERRTGTR40 setting */ + /* Skip ECMERRTGTR41 setting */ + /* Skip ECMERRTGTR42 setting */ + }; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + NOTICE("ECMERRCTLR and ECMERRTGTR register initial setting.\n"); + /* For the initial setting flow for Type-1, please refer to the following + * section in the "SAN(Safety Application Note)." + * Section 4.1.2.5 : (1) + * Section 4.1.4.5 : (1) + * Section 4.12.1.5 : (1) + * Section 4.13.1.5 : (1) + * Section 4.14.5 : (1) + * Section 4.16.5 : (1) + * Section 4.18.5 : (1) + * Section 4.2.7.5 : (1) + * Section 4.2.9.5 : (1) + * Section 4.23.5 : (1) + * Section 4.3.11.5 : (1) + * Section 4.3.12.5 : (1) + * Section 4.3.14.5 : (1) + * Section 4.3.19.5 : (1) + * Section 4.3.21.5 : (1) + * Section 4.4.14.5 : (1) + * Section 4.4.16.5 : (3) + * Section 4.4.18.5 : (1) + * Section 4.4.20.5 : (1) + * Section 4.4.3.5 : (1) + * Section 4.4.4.5 : (1) + * Section 4.4.6.5 : (1) + * Section 4.4.7.5 : (1) + * Section 4.4.9.5 : (1) + * Section 4.5.1.5 : (1) + * Section 4.7.1.5 : (1) + * Section 4.7.10.5 : (1) + * Section 4.7.3.5 : (1) + * Section 4.7.4.5 : (1) + * Section 4.7.7.5 : (1) + * Section 4.7.8.5 : (1) + * Section 5.6.5 : (1) + * Section 5.8.1.5 : (1) + */ + for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++) + { + reg = mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr); + reg |= (ecmerrctlr_type1_tbl[loop].value); + ecm_write(ecmerrctlr_type1_tbl[loop].phys_addr, reg); + + INFO("[Type-1]ECMERRCTLR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", + loop, + ecmerrctlr_type1_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr), + ecmerrctlr_type1_tbl[loop].value); + } + + for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++) + { + reg = mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr); + reg &= ~(ecmerrtgtr_type1_tbl[loop].value); + ecm_write(ecmerrtgtr_type1_tbl[loop].phys_addr, reg); + + INFO("[Type-1]ECMERRTGTR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", + loop, + ecmerrtgtr_type1_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr), + ecmerrtgtr_type1_tbl[loop].value); + } + + /* For the initial setting flow for Type-2, please refer to the following + * section in the "SAN(Safety Application Note)." + * Section 4.1.1.5 : (1) + * Section 4.12.2.5 : (1) + * Section 4.12.3.5 : (1) + * Section 4.15.5 : (1) + * Section 4.16.5 : (1) + * Section 4.2.1.5 : (1) + * Section 4.2.10.5 : (1) + * Section 4.2.12.5 : (1) + * Section 4.2.2.5 : (1) + * Section 4.2.4.5 : (1) + * Section 4.2.8.5 : (1) + * Section 4.3.1.5 : (1) + * Section 4.3.10.5 : (1) + * Section 4.3.11.5 : (1) + * Section 4.3.12.5 : (1) + * Section 4.3.13.5 : (1) + * Section 4.3.15.5 : (1) + * Section 4.3.16.5 : (1) + * Section 4.3.2.5 : (1) + * Section 4.3.5.5 : (1) + * Section 4.3.7.5 : (1) + * Section 4.3.8.5 : (1) + * Section 4.4.10.5 : (1) + * Section 4.4.12.5 : (8) + * Section 4.4.13.5 : (1) + * Section 4.4.15.5 : (1) + * Section 4.4.2.5 : (1) + * Section 4.5.3.5 : (1) + * Section 4.6.5 : (1) + * Section 4.7.2.5 : (1) + * Section 5.11.5 : (1) + * Section 5.12.5 : (1) + * Section 5.13.5 : (1) + * Section 5.4.5 : (1) + * Section 5.8.2.5 : (1) + */ + for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++) + { + /* Initial Setting Type-2 for ECMERRCTLR registers */ + reg = mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr); + reg |= (ecmerrctlr_type2_tbl[loop].value); + ecm_write(ecmerrctlr_type2_tbl[loop].phys_addr, reg); + + INFO("[Type-2]ECMERRCTLR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", + loop, + ecmerrctlr_type2_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr), + ecmerrctlr_type2_tbl[loop].value); + } + + for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++) + { + /* Initial Setting Type-2 for ECMERRTGTR registers */ + reg = mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr); + reg &= ~(ecmerrtgtr_type2_tbl[loop].value); + ecm_write(ecmerrtgtr_type2_tbl[loop].phys_addr, reg); + + INFO("[Type-2]ECMERRTGTR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", + loop, + ecmerrtgtr_type2_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr), + ecmerrtgtr_type2_tbl[loop].value); + } + + /* For the initial setting flow for Type-3, please refer to the following + * section in the "SAN(Safety Application Note)." + * Section 4.19.1.5 : (3) + * Section 6.2.5 : (12) + */ + for (loop = 0U; loop < TYPE3_ECM_CTLREG_MAX; loop++) + { + /* Initial Setting Type-3 for ECMERRCTLR registers */ + reg = mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr); + reg |= (ecmerrctlr_type3_tbl[loop].value); + ecm_write(ecmerrctlr_type3_tbl[loop].phys_addr, reg); + + INFO("[Type-3]ECMERRCTLR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", + loop, + ecmerrctlr_type3_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr), + ecmerrctlr_type3_tbl[loop].value); + } + + for (loop = 0U; loop < TYPE3_ECM_TGTREG_MAX; loop++) + { + /* Initial Setting Type-3 for ECMERRTGTR registers */ + reg = mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr); + reg &= ~(ecmerrtgtr_type3_tbl[loop].value); + ecm_write(ecmerrtgtr_type3_tbl[loop].phys_addr, reg); + + INFO("[Type-3]ECMERRTGTR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", + loop, + ecmerrtgtr_type3_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr), + ecmerrtgtr_type3_tbl[loop].value); + } + + /* Lock the ECM registers */ + ecm_lock(); +} +/* End of function ecm_init_setting(void) */ +#endif /* ECM_ERROR_ENABLE == 1 */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h new file mode 100644 index 0000000..fa5a8a6 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM driver header + ******************************************************************************/ + +#ifndef ECM_ENABLE_V4H +#define ECM_ENABLE_V4H + +#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1)) +void ecm_unlock(void); +void ecm_write(uint32_t adr, uint32_t val); +void ecm_lock(void); +#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_init_setting(void); +#endif /* ECM_ERROR_ENABLE == 1 */ + +#endif/* ECM_ENABLE_V4H */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h new file mode 100644 index 0000000..8cdb901 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h @@ -0,0 +1,302 @@ +/******************************************************************************* + * Copyright (c) 2015-2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +#if defined(__RH850G3K__) +#include "remap_register.h" +#endif + +#define RCAR_DDR_VERSION "rev.0.08rc7" +#define DRAM_CH_CNT 0x04 +#define SLICE_CNT 0x02 +#define CS_CNT 0x02 + +/* for pll setting */ +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) +#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb))) + +/* for ddr density setting */ +#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30) | ((row) << 24) | ((BG) << 20) | ((bank) << 16) | ((col) << 8) | (dw)) +#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (28 - 2 - 2 - 10 - 1), 2, 2, 10, 1)) /* 16bit */ +#define DBMEMCONF_VAL(ch,cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) + +/* system registers : CPG */ +#define CPG_FRQCRD_KICK_BIT (1U << 31) +#define CPG_PLL3CR0_KICK_BIT (1U << 31) + +#define CPG_PLLECR_PLL3E_BIT (1U << 3) +#define CPG_PLLECR_PLL3ST_BIT (1U << 11) + +#if defined(__RH850G3K__) +#define CPG_BASE (BASE_CPG_ADDR) +#else +#define CPG_BASE (0xE6150000U) +#endif +#define CPG_CPGWPR (CPG_BASE + 0x0000U) +#define CPG_CPGWPCR (CPG_BASE + 0x0004U) +#define CPG_FRQCRA (CPG_BASE + 0x0800U) +#define CPG_FRQCRB (CPG_BASE + 0x0804U) +#define CPG_FRQCRC (CPG_BASE + 0x0808U) +#define CPG_FRQCRD0 (CPG_BASE + 0x080CU) +#define CPG_PLLECR (CPG_BASE + 0x0820U) +#define CPG_PLL3CR0 (CPG_BASE + 0x083CU) +#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U) +#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U) +#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U) +#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U) +#define CPG_SRCR4 (CPG_BASE + 0x2C10U) +#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U) + +#define CPG_PLL3FBCKMCSR (CPG_BASE + 0x0C60U) +#define CPG_PLL3FBCKMECR (CPG_BASE + 0x0C64U) +#define CPG_PLL3FBCKMLCH (CPG_BASE + 0x0C68U) +#define CPG_PLL3FBCKMLCL (CPG_BASE + 0x0C6CU) +#define CPG_PLL3FBCKMCNT (CPG_BASE + 0x0C70U) +#define CPG_PLL3FBCKMCNTE (CPG_BASE + 0x0C74U) + +#if defined(__RH850G3K__) +#define RST_BASE (BASE_RESET_ADDR) +#else +#define RST_BASE (0xE6160000U) +#endif +#define RST_MODEMR0 (RST_BASE + 0x0000U) +#define RST_MODEMR1 (RST_BASE + 0x0004U) + +/* Product Register */ +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) + +#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */ + +#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */ +#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */ + +/* DBSC registers */ +#if defined(__RH850G3K__) +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#else +#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#endif + +#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U) +#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U) +#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U) +#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U) +#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U) +#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U) +#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U) +#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U) + +#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs)) +#define DBSC_DBMEMCONF_0_0 (DBSC_D_BASE + 0x0030U) +#define DBSC_DBMEMCONF_0_1 (DBSC_D_BASE + 0x0034U) +#define DBSC_DBMEMCONF_0_2 (DBSC_D_BASE + 0x0038U) +#define DBSC_DBMEMCONF_0_3 (DBSC_D_BASE + 0x003CU) +#define DBSC_DBMEMCONF_1_0 (DBSC_D_BASE + 0x0040U) +#define DBSC_DBMEMCONF_1_1 (DBSC_D_BASE + 0x0044U) +#define DBSC_DBMEMCONF_1_2 (DBSC_D_BASE + 0x0048U) +#define DBSC_DBMEMCONF_1_3 (DBSC_D_BASE + 0x004CU) +#define DBSC_DBMEMCONF_2_0 (DBSC_D_BASE + 0x0050U) +#define DBSC_DBMEMCONF_2_1 (DBSC_D_BASE + 0x0054U) +#define DBSC_DBMEMCONF_2_2 (DBSC_D_BASE + 0x0058U) +#define DBSC_DBMEMCONF_2_3 (DBSC_D_BASE + 0x005CU) +#define DBSC_DBMEMCONF_3_0 (DBSC_D_BASE + 0x0060U) +#define DBSC_DBMEMCONF_3_1 (DBSC_D_BASE + 0x0064U) +#define DBSC_DBMEMCONF_3_2 (DBSC_D_BASE + 0x0068U) +#define DBSC_DBMEMCONF_3_3 (DBSC_D_BASE + 0x006CU) + +#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs)) +#define DBSC_DBMEMCONF_0_0A (DBSC_A_BASE + 0x0030U) +#define DBSC_DBMEMCONF_0_1A (DBSC_A_BASE + 0x0034U) +#define DBSC_DBMEMCONF_0_2A (DBSC_A_BASE + 0x0038U) +#define DBSC_DBMEMCONF_0_3A (DBSC_A_BASE + 0x003CU) +#define DBSC_DBMEMCONF_1_0A (DBSC_A_BASE + 0x0040U) +#define DBSC_DBMEMCONF_1_1A (DBSC_A_BASE + 0x0044U) +#define DBSC_DBMEMCONF_1_2A (DBSC_A_BASE + 0x0048U) +#define DBSC_DBMEMCONF_1_3A (DBSC_A_BASE + 0x004CU) +#define DBSC_DBMEMCONF_2_0A (DBSC_A_BASE + 0x0050U) +#define DBSC_DBMEMCONF_2_1A (DBSC_A_BASE + 0x0054U) +#define DBSC_DBMEMCONF_2_2A (DBSC_A_BASE + 0x0058U) +#define DBSC_DBMEMCONF_2_3A (DBSC_A_BASE + 0x005CU) +#define DBSC_DBMEMCONF_3_0A (DBSC_A_BASE + 0x0060U) +#define DBSC_DBMEMCONF_3_1A (DBSC_A_BASE + 0x0064U) +#define DBSC_DBMEMCONF_3_2A (DBSC_A_BASE + 0x0068U) +#define DBSC_DBMEMCONF_3_3A (DBSC_A_BASE + 0x006CU) + +#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U) + +#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U) +#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U) +#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U) +#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U) + +#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + 0x04U * (x)) +#define DBSC_DBTR0 (DBSC_D_BASE + 0x0300U) +#define DBSC_DBTR1 (DBSC_D_BASE + 0x0304U) +#define DBSC_DBTR2 (DBSC_D_BASE + 0x0308U) +#define DBSC_DBTR3 (DBSC_D_BASE + 0x030CU) +#define DBSC_DBTR4 (DBSC_D_BASE + 0x0310U) +#define DBSC_DBTR5 (DBSC_D_BASE + 0x0314U) +#define DBSC_DBTR6 (DBSC_D_BASE + 0x0318U) +#define DBSC_DBTR7 (DBSC_D_BASE + 0x031CU) +#define DBSC_DBTR8 (DBSC_D_BASE + 0x0320U) +#define DBSC_DBTR9 (DBSC_D_BASE + 0x0324U) +#define DBSC_DBTR10 (DBSC_D_BASE + 0x0328U) +#define DBSC_DBTR11 (DBSC_D_BASE + 0x032CU) +#define DBSC_DBTR12 (DBSC_D_BASE + 0x0330U) +#define DBSC_DBTR13 (DBSC_D_BASE + 0x0334U) +#define DBSC_DBTR14 (DBSC_D_BASE + 0x0338U) +#define DBSC_DBTR15 (DBSC_D_BASE + 0x033CU) +#define DBSC_DBTR16 (DBSC_D_BASE + 0x0340U) +#define DBSC_DBTR17 (DBSC_D_BASE + 0x0344U) +#define DBSC_DBTR18 (DBSC_D_BASE + 0x0348U) +#define DBSC_DBTR19 (DBSC_D_BASE + 0x034CU) +#define DBSC_DBTR20 (DBSC_D_BASE + 0x0350U) +#define DBSC_DBTR21 (DBSC_D_BASE + 0x0354U) +#define DBSC_DBTR22 (DBSC_D_BASE + 0x0358U) +#define DBSC_DBTR23 (DBSC_D_BASE + 0x035CU) +#define DBSC_DBTR24 (DBSC_D_BASE + 0x0360U) +#define DBSC_DBTR25 (DBSC_D_BASE + 0x0364U) +#define DBSC_DBTR26 (DBSC_D_BASE + 0x0368U) +#define DBSC_DBTR27 (DBSC_D_BASE + 0x036CU) +#define DBSC_DBTR28 (DBSC_D_BASE + 0x0370U) +#define DBSC_DBTR29 (DBSC_D_BASE + 0x0374U) +#define DBSC_DBTR30 (DBSC_D_BASE + 0x0378U) +#define DBSC_DBTR31 (DBSC_D_BASE + 0x037CU) +#define DBSC_DBTR32 (DBSC_D_BASE + 0x0380U) +#define DBSC_DBTR33 (DBSC_D_BASE + 0x0384U) +#define DBSC_DBTR34 (DBSC_D_BASE + 0x0388U) +#define DBSC_DBTR35 (DBSC_D_BASE + 0x038CU) +#define DBSC_DBTR36 (DBSC_D_BASE + 0x0390U) +#define DBSC_DBTR37 (DBSC_D_BASE + 0x0394U) + +#define DBSC_DBBL (DBSC_D_BASE + 0x0400U) +#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U) + +#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U) +#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U) + +#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U) + +#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + 0x04U * (x)) +#define DBSC_DBRNK2 (DBSC_D_BASE + 0x0438U) +#define DBSC_DBRNK3 (DBSC_D_BASE + 0x043CU) +#define DBSC_DBRNK4 (DBSC_D_BASE + 0x0440U) +#define DBSC_DBRNK5 (DBSC_D_BASE + 0x0444U) + +#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U) +#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U) +#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U) + +#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBDFISTAT_0 (DBSC_D_BASE + 0x0600U) +#define DBSC_DBDFISTAT_1 (DBSC_D_BASE + 0x0640U) +#define DBSC_DBDFISTAT_2 (DBSC_D_BASE + 0x0680U) +#define DBSC_DBDFISTAT_3 (DBSC_D_BASE + 0x06C0U) + +#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBDFICNT_0 (DBSC_D_BASE + 0x0604U) +#define DBSC_DBDFICNT_1 (DBSC_D_BASE + 0x0644U) +#define DBSC_DBDFICNT_2 (DBSC_D_BASE + 0x0684U) +#define DBSC_DBDFICNT_3 (DBSC_D_BASE + 0x06C4U) + +#define DBSC_DBPDCNT0_0 (DBSC_D_BASE + 0x0610U) +#define DBSC_DBPDCNT0_1 (DBSC_D_BASE + 0x0614U) +#define DBSC_DBPDCNT0_2 (DBSC_D_BASE + 0x0618U) +#define DBSC_DBPDCNT0_3 (DBSC_D_BASE + 0x061CU) + +#define DBSC_DBPDCNT1_0 (DBSC_D_BASE + 0x0650U) +#define DBSC_DBPDCNT1_1 (DBSC_D_BASE + 0x0654U) +#define DBSC_DBPDCNT1_2 (DBSC_D_BASE + 0x0658U) +#define DBSC_DBPDCNT1_3 (DBSC_D_BASE + 0x065CU) + +#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDCNT2_0 (DBSC_D_BASE + 0x0690U) +#define DBSC_DBPDCNT2_1 (DBSC_D_BASE + 0x0694U) +#define DBSC_DBPDCNT2_2 (DBSC_D_BASE + 0x0698U) +#define DBSC_DBPDCNT2_3 (DBSC_D_BASE + 0x069CU) + +#define DBSC_DBPDCNT3_0 (DBSC_D_BASE + 0x06D0U) +#define DBSC_DBPDCNT3_1 (DBSC_D_BASE + 0x06D4U) +#define DBSC_DBPDCNT3_2 (DBSC_D_BASE + 0x06D8U) +#define DBSC_DBPDCNT3_3 (DBSC_D_BASE + 0x06DCU) + +#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDLK_0 (DBSC_D_BASE + 0x0620U) +#define DBSC_DBPDLK_1 (DBSC_D_BASE + 0x0660U) +#define DBSC_DBPDLK_2 (DBSC_D_BASE + 0x06a0U) +#define DBSC_DBPDLK_3 (DBSC_D_BASE + 0x06e0U) + +#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDRGA_0 (DBSC_D_BASE + 0x0624U) +#define DBSC_DBPDRGA_1 (DBSC_D_BASE + 0x0664U) +#define DBSC_DBPDRGA_2 (DBSC_D_BASE + 0x06A4U) +#define DBSC_DBPDRGA_3 (DBSC_D_BASE + 0x06E4U) + +#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDRGD_0 (DBSC_D_BASE + 0x0628U) +#define DBSC_DBPDRGD_1 (DBSC_D_BASE + 0x0668U) +#define DBSC_DBPDRGD_2 (DBSC_D_BASE + 0x06A8U) +#define DBSC_DBPDRGD_3 (DBSC_D_BASE + 0x06E8U) + +#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDSTAT0_0 (DBSC_D_BASE + 0x0630U) +#define DBSC_DBPDSTAT1_0 (DBSC_D_BASE + 0x0670U) + +#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDSTAT0_1 (DBSC_D_BASE + 0x0634U) +#define DBSC_DBPDSTA1T_1 (DBSC_D_BASE + 0x0674U) + +#define DBSC_DBCAM0CTRL0 (DBSC_A_BASE + 0x0940U) + +#define DBSC_DBCAMSTAT0(x) (DBSC_A_BASE + 0x0980U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U)) +#define DBSC_DBCAM0STAT0 (DBSC_A_BASE + 0x0980U) +#define DBSC_DBCAM1STAT0 (DBSC_A_BASE + 0x0990U) +#define DBSC_DBCAM2STAT0 (DBSC_A_BASE + 0x09A0U) +#define DBSC_DBCAM3STAT0 (DBSC_A_BASE + 0x09B0U) + +#define DBSC_DBCAMSTAT1(x) (DBSC_A_BASE + 0x0984U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U)) +#define DBSC_DBCAM0STAT1 (DBSC_A_BASE + 0x0984U) +#define DBSC_DBCAM1STAT1 (DBSC_A_BASE + 0x0994U) +#define DBSC_DBCAM2STAT1 (DBSC_A_BASE + 0x09A4U) +#define DBSC_DBCAM3STAT1 (DBSC_A_BASE + 0x09B4U) + +#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU) + +#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U) + +#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U) + +#define DBSC_DBSCHFCTST01(x) (DBSC_A_BASE + 0x1040U + 0x04U * (x)) +#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U) +#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U) + +#define DBSC_DBSCHQOS(x,y) (DBSC_A_BASE + 0x1100U + 0x10U * (x) + 0x04U * (y)) diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c new file mode 100644 index 0000000..dcfb84b --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c @@ -0,0 +1,217 @@ +/******************************************************************************* + * Copyright (c) 2023-2024 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC setting function + ******************************************************************************/ +/****************************************************************************** + * @file ecc_enable_v4m.c + * - Version : 0.03 + * @brief Enable setting process of ECC for DRAM. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + * : 13.06.2024 0.02 Fix register setting for EDC_CFG, and revise + * : the ecm_lock()/ecm_unlock() process. + * : 07.04.2025 0.06 Remove unused functions. + *****************************************************************************/ + +#include +#include +#include +#include + +#if (ECM_ENABLE == 1) +#include "ecc_enable_v4m.h" +#include "v4m/lpddr5/boot_init_dram_regdef.h" +#include "ecm_enable_v4m.h" + +#define AXI_SICREMAP_NUM (5U) +#define RGID_BASE1 (0xFE600000U) +#define RGID_BASE2 (0xE7A00000U) +#define RGID_BASE3 (0xEB800000U) +#define RGID_BASE4 (0xFD800000U) +#define RGID_BASE5 (0xFEA00000U) + +#define FDT_COUNTER_MASK (0x0000FFFFU) + +static void axi_timeout_setting(void); + +void edc_axi_enable(void) +{ + uint32_t edc_tmp; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers + to inform the external device of the error via the ERROROUT# pin. */ + + /* Set bit 11 - bit 2 of ECMERRTGTR7 to all 0 and bit 11 - bit 2 of + ECMERRCTLR7 to 1. (Error of AXI-Bus ECM of each hierarchy) */ + edc_tmp = mem_read32(ECMERRTGTR7); + edc_tmp &= ~(0x3FFU << 2U); + ecm_write(ECMERRTGTR7, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR7); + edc_tmp |= (0x3FFU << 2U); + ecm_write(ECMERRCTLR7, edc_tmp); + + /* Set bit 28 - bit 16 of ECMERRTGTR39 to all 0 and bit 28 - bit 16 of + ECMERRCTLR39 to 1. (Error of AXI-Bus ECM of each hierarchy) */ + edc_tmp = mem_read32(ECMERRTGTR39); + edc_tmp &= ~(0x1FFFU << 16U); + ecm_write(ECMERRTGTR39, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR39); + edc_tmp |= (0x1FFFU << 16U); + ecm_write(ECMERRCTLR39, edc_tmp); + + /* Set bit 26 of ECMERRTGTR1 to 0 and bit 26 of + ECMERRCTLR1 to 1. (CCI bus EDC error) */ + edc_tmp = mem_read32(ECMERRTGTR1); + edc_tmp &= ~(0x1U << 26U); + ecm_write(ECMERRTGTR1, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR1); + edc_tmp |= (0x1U << 26U); + ecm_write(ECMERRCTLR1, edc_tmp); + + axi_timeout_setting(); + + /* Lock the ECM registers */ + ecm_lock(); +} + +void edc_vram_enable(void) +{ + uint32_t edc_tmp; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers + to inform the external device of the error via the ERROROUT# pin. */ + + /* Set bit 30 of ECMERRTGTR7 to 0 and bit 30 of ECMERRCTLR7 to 1. + (RT-VRAM edc 1-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR7); + edc_tmp &= ~(0x1U << 30U); + ecm_write(ECMERRTGTR7, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR7); + edc_tmp |= (0x1U << 30U); + ecm_write(ECMERRCTLR7, edc_tmp); + + /* Set bit 29 of ECMERRTGTR7 to 0 and bit 29 of ECMERRCTLR7 to 1. + (RT-VRAM edc multi-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR7); + edc_tmp &= ~(0x1U << 29U); + ecm_write(ECMERRTGTR7, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR7); + edc_tmp |= (0x1U << 29U); + ecm_write(ECMERRCTLR7, edc_tmp); + + /* Set bit 19 of ECMERRTGTR17 to 0 and bit 19 of ECMERRCTLR17 to 1. + (RT-VRAM edc 1-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR17); + edc_tmp &= ~(0x1U << 19U); + ecm_write(ECMERRTGTR17, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR17); + edc_tmp |= (0x1U << 19U); + ecm_write(ECMERRCTLR17, edc_tmp); + + /* Set bit 18 of ECMERRTGTR17 to 0 and bit 18 of ECMERRCTLR17 to 1. + (RT-VRAM edc multi-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR17); + edc_tmp &= ~(0x1U << 18U); + ecm_write(ECMERRTGTR17, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR17); + edc_tmp |= (0x1U << 18U); + ecm_write(ECMERRCTLR17, edc_tmp); + + /* Set bit 0 of EDC_CFG to 1. (EDC Error Control) */ + edc_tmp = mem_read32(EDC_CFG); + edc_tmp |= (0x1U << 0U); + mem_write32(EDC_CFG, edc_tmp); + + /* Lock the ECM registers */ + ecm_lock(); +} + +static void axi_timeout_setting(void) +{ + uint32_t reg; + uint32_t loop; + REMAP_TABLE axi_remap_tbl[AXI_SICREMAP_NUM] = { + {RGID_BASE1, 0U}, + {RGID_BASE2, 0U}, + {RGID_BASE3, 0U}, + {RGID_BASE4, 0U}, + {RGID_BASE5, 0U}, + }; + + /* Register of AXI Base */ + for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++) + { + remap_register(axi_remap_tbl[loop].base_addr, &axi_remap_tbl[loop].rmp_addr); + } + + /* Set the COUNTER bits of the FDT_* registers for all safety-related modules to minimum value with 1ms or more. */ + for (loop = 0U; loop < FDT_REG_MAX; loop++) + { + reg = mem_read32(g_fdt_tbl[loop].reg_addr); + reg &= ~(FDT_COUNTER_MASK); + reg |= g_fdt_tbl[loop].value; + mem_write32(g_fdt_tbl[loop].reg_addr, reg); + + INFO("FDT[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_fdt_tbl[loop].reg_addr), g_fdt_tbl[loop].value); + } + + for(loop = 0U; loop < INTEN_REG_MAX; loop++) + { + /* Set access protection setting value of Region ID (AXI bus of Region ID register) */ + mem_write32(g_inten_tbl[loop].reg_addr, g_inten_tbl[loop].value); + + INFO("INTEN[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_inten_tbl[loop].reg_addr), g_inten_tbl[loop].value); + } + + /* Unregister of AXI Base */ + for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++) + { + remap_unregister(axi_remap_tbl[loop].rmp_addr); + } + + wdt_restart(); +} +#endif /* ECM_ENABLE == 1 */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h new file mode 100644 index 0000000..8a04f4b --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h @@ -0,0 +1,123 @@ +/******************************************************************************* + * Copyright (c) 2022-2024 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC driver header + ******************************************************************************/ + +#ifndef ECC_PROTECT +#define ECC_PROTECT +#include "remap_register.h" +/* DBSC registers */ +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#define ECM_BASE (BASE_ECC_ADDR) +#else +#include +#include +#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#define ECM_BASE (0xE6250000U) +#endif/* defined(__RH850G3K__) */ + +#define RTVRAM_REG_BASE (0xFFEC0000U) + +void edc_axi_enable(void); +void edc_vram_enable(void); + +#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U) +#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U) +#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U) + +#define DBSC_DBACEN0 (DBSC_A_BASE + 0x0200U) +#define DBSC_DBACEN1 (DBSC_DBACEN0 + 0x8000U) + +#define ECMWACNTR (ECM_BASE + 0x0A04U) +#define ECMWPCNTR (ECM_BASE + 0x0A00U) +#define ECMERRTGTR0 (ECM_BASE + 0x0200U) +#define ECMERRCTLR0 (ECM_BASE + 0x0000U) +#define ECMERRTGTR1 (ECM_BASE + 0x0200U + 0x4U * 1U) +#define ECMERRCTLR1 (ECM_BASE + 0x0000U + 0x4U * 1U) +#define ECMERRTGTR7 (ECM_BASE + 0x0200U + 0x4U * 7U) +#define ECMERRCTLR7 (ECM_BASE + 0x0000U + 0x4U * 7U) +#define ECMERRTGTR17 (ECM_BASE + 0x0200U + 0x4U * 17U) +#define ECMERRCTLR17 (ECM_BASE + 0x0000U + 0x4U * 17U) +#define ECMERRTGTR39 (ECM_BASE + 0x0200U + 0x4U * 39U) +#define ECMERRCTLR39 (ECM_BASE + 0x0000U + 0x4U * 39U) +#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U) +#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U) +#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U) +#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U) +#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U) +#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U) +#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U) +#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U) +#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U) +#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U) +#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U) +#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U) +#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U) +#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U) +#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U) +#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U) + +#define DB0FSDRAMECCAREA0 (DBSC_A_BASE + 0x7450U) +#define DB0FSDRAMECCAREA1 (DBSC_A_BASE + 0x7454U) +#define DB1FSDRAMECCAREA0 (DB0FSDRAMECCAREA0 + 0x8000U) +#define DB1FSDRAMECCAREA1 (DB0FSDRAMECCAREA1 + 0x8000U) + +#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U) +#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U) + +#define EDC_CFG (RTVRAM_REG_BASE + 0x4110U) + +/********************* Set by the user *********************/ +/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */ +#define ECC_PROT_SIZE00 (0x1000U) +#define ECC_PROT_SIZE01 (0x1000U) +#define ECC_PROT_SIZE10 (0x1000U) +#define ECC_PROT_SIZE11 (0x1000U) + +/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */ +#define START_ECC_INIT_AREA00 (0x00000000U) +#define START_ECC_INIT_AREA10 (0x00000000U) +#define END_ECC_INIT_AREA00 (0x00000FFFU) +#define END_ECC_INIT_AREA10 (0x00000FFFU) + +/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */ +#define START_ECC_INIT_AREA01 (0x00000000U) +#define START_ECC_INIT_AREA11 (0x00000000U) +#define END_ECC_INIT_AREA01 (0x00000FFFU) +#define END_ECC_INIT_AREA11 (0x00000FFFU) +/*********** Other settings cannot be changed ***************/ + +#endif/* ECC_PROTECT */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c new file mode 100644 index 0000000..4c615e4 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c @@ -0,0 +1,534 @@ +/******************************************************************************* + * Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM initialize function + ******************************************************************************/ +/****************************************************************************** + * @file ecm_enable_v4m.c + * - Version : 0.01 + * @brief ECM setting. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.01.2025 0.01 First Release + *****************************************************************************/ + +#include +#include "ecm_enable_v4m.h" + +#if (ECM_ERROR_ENABLE == 1) +#include "log.h" +#endif /* ECM_ERROR_ENABLE == 1 */ +#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1)) +#include "ecc_enable_v4m.h" +#include "mem_io.h" +#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +#define TYPE1_ECM_REG_MAX (14U) +#define TYPE2_ECM_REG_MAX (21U) +#define TYPE3_ECM_CTLREG_MAX (1U) +#define TYPE3_ECM_TGTREG_MAX (2U) + +typedef struct{ + uint32_t phys_addr; /* Physical address of ECM registers. */ + uint32_t value; /* Setting value of ECM registers. */ +} ECM_ERROR_TABLE; +#endif /* ECM_ERROR_ENABLE == 1 */ + +#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1)) +void ecm_unlock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0001U); +} + +void ecm_write(uint32_t adr, uint32_t val) +{ + mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU))); + mem_write32(adr, val); +} + +void ecm_lock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0000U); +} +#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_init_setting(void) +{ + uint32_t reg; + uint32_t loop; + + const ECM_ERROR_TABLE ecmerrctlr_type1_tbl[TYPE1_ECM_REG_MAX] = { + [0] = {0xFD850000U, 0x00381000U}, /* ECMERRCTLR0 */ + [1] = {0xFD850004U, 0xA400C000U}, /* ECMERRCTLR1 */ + /* Skip ECMERRCTLR2 setting */ + /* Skip ECMERRCTLR3 setting */ + /* Skip ECMERRCTLR4 setting */ + /* Skip ECMERRCTLR5 setting */ + [2] = {0xFD850018U, 0xCC000000U}, /* ECMERRCTLR6 */ + [3] = {0xFD85001CU, 0x08000000U}, /* ECMERRCTLR7 */ + /* Skip ECMERRCTLR8 setting */ + /* Skip ECMERRCTLR9 setting */ + /* Skip ECMERRCTLR10 setting */ + /* Skip ECMERRCTLR11 setting */ + /* Skip ECMERRCTLR12 setting */ + /* Skip ECMERRCTLR13 setting */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + /* Skip ECMERRCTLR16 setting */ + [4] = {0xFD850044U, 0x2D001000U}, /* ECMERRCTLR17 */ + [5] = {0xFD850048U, 0x0CC001FFU}, /* ECMERRCTLR18 */ + [6] = {0xFD85004CU, 0xFFF80000U}, /* ECMERRCTLR19 */ + [7] = {0xFD850050U, 0x0000001EU}, /* ECMERRCTLR20 */ + [8] = {0xFD850054U, 0x9F000000U}, /* ECMERRCTLR21 */ + /* Skip ECMERRCTLR22 setting */ + /* Skip ECMERRCTLR23 setting */ + /* Skip ECMERRCTLR24 setting */ + /* Skip ECMERRCTLR25 setting */ + /* Skip ECMERRCTLR26 setting */ + /* Skip ECMERRCTLR27 setting */ + /* Skip ECMERRCTLR28 setting */ + /* Skip ECMERRCTLR29 setting */ + /* Skip ECMERRCTLR30 setting */ + /* Skip ECMERRCTLR31 setting */ + [9] = {0xFD850080U, 0x10000000U}, /* ECMERRCTLR32 */ + [10] = {0xFD850084U, 0x10000000U}, /* ECMERRCTLR33 */ + /* Skip ECMERRCTLR34 setting */ + [11] = {0xFD85008CU, 0x20002280U}, /* ECMERRCTLR35 */ + /* Skip ECMERRCTLR36 setting */ + /* Skip ECMERRCTLR37 setting */ + [12] = {0xFD850098U, 0x33300054U}, /* ECMERRCTLR38 */ + /* Skip ECMERRCTLR39 setting */ + /* Skip ECMERRCTLR40 setting */ + [13] = {0xFD8500A4U, 0x01000880U}, /* ECMERRCTLR41 */ + /* Skip ECMERRCTLR42 setting */ + }; + + const ECM_ERROR_TABLE ecmerrtgtr_type1_tbl[TYPE1_ECM_REG_MAX] = { + [0] = {0xFD850200U, 0x00381000U}, /* ECMERRTGTR0 */ + [1] = {0xFD850204U, 0xA400C000U}, /* ECMERRTGTR1 */ + /* Skip ECMERRTGTR2 setting */ + /* Skip ECMERRTGTR3 setting */ + /* Skip ECMERRTGTR4 setting */ + /* Skip ECMERRTGTR5 setting */ + [2] = {0xFD850218U, 0xCC000000U}, /* ECMERRTGTR6 */ + [3] = {0xFD85021CU, 0x08000000U}, /* ECMERRTGTR7 */ + /* Skip ECMERRTGTR8 setting */ + /* Skip ECMERRTGTR9 setting */ + /* Skip ECMERRTGTR10 setting */ + /* Skip ECMERRTGTR11 setting */ + /* Skip ECMERRTGTR12 setting */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + /* Skip ECMERRTGTR16 setting */ + [4] = {0xFD850244U, 0x2D001000U}, /* ECMERRTGTR17 */ + [5] = {0xFD850248U, 0x0CC001FFU}, /* ECMERRTGTR18 */ + [6] = {0xFD85024CU, 0xFFF80000U}, /* ECMERRTGTR19 */ + [7] = {0xFD850250U, 0x0000001EU}, /* ECMERRTGTR20 */ + [8] = {0xFD850254U, 0x9F000000U}, /* ECMERRTGTR21 */ + /* Skip ECMERRTGTR22 setting */ + /* Skip ECMERRTGTR23 setting */ + /* Skip ECMERRTGTR24 setting */ + /* Skip ECMERRTGTR25 setting */ + /* Skip ECMERRTGTR26 setting */ + /* Skip ECMERRTGTR27 setting */ + /* Skip ECMERRTGTR28 setting */ + /* Skip ECMERRTGTR29 setting */ + /* Skip ECMERRTGTR30 setting */ + /* Skip ECMERRTGTR31 setting */ + [9] = {0xFD850280U, 0x10000000U}, /* ECMERRTGTR32 */ + [10] = {0xFD850284U, 0x10000000U}, /* ECMERRTGTR33 */ + /* Skip ECMERRTGTR34 setting */ + [11] = {0xFD85028CU, 0x20002280U}, /* ECMERRTGTR35 */ + /* Skip ECMERRTGTR36 setting */ + /* Skip ECMERRTGTR37 setting */ + [12] = {0xFD850298U, 0x33300054U}, /* ECMERRTGTR38 */ + /* Skip ECMERRTGTR39 setting */ + /* Skip ECMERRTGTR40 setting */ + [13] = {0xFD8502A4U, 0x01000880U}, /* ECMERRTGTR41 */ + /* Skip ECMERRTGTR42 setting */ + }; + + const ECM_ERROR_TABLE ecmerrctlr_type2_tbl[TYPE2_ECM_REG_MAX] = { + [0] = {0xFD850000U, 0x40000003U}, /* ECMERRCTLR0 */ + [1] = {0xFD850004U, 0x04004000U}, /* ECMERRCTLR1 */ + [2] = {0xFD850008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */ + [3] = {0xFD85000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */ + [4] = {0xFD850010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */ + [5] = {0xFD850014U, 0x81FFFFFFU}, /* ECMERRCTLR5 */ + [6] = {0xFD850018U, 0x15000A80U}, /* ECMERRCTLR6 */ + [7] = {0xFD85001CU, 0x00801481U}, /* ECMERRCTLR7 */ + /* Skip ECMERRCTLR8 setting */ + /* Skip ECMERRCTLR9 setting */ + /* Skip ECMERRCTLR10 setting */ + /* Skip ECMERRCTLR11 setting */ + /* Skip ECMERRCTLR12 setting */ + /* Skip ECMERRCTLR13 setting */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + [8] = {0xFD850040U, 0x00003E9FU}, /* ECMERRCTLR16 */ + [9] = {0xFD850044U, 0x00938060U}, /* ECMERRCTLR17 */ + [10] = {0xFD850048U, 0x00341600U}, /* ECMERRCTLR18 */ + [11] = {0xFD85004CU, 0x0007FF30U}, /* ECMERRCTLR19 */ + [12] = {0xFD850050U, 0x02200220U}, /* ECMERRCTLR20 */ + [13] = {0xFD850054U, 0x0061820FU}, /* ECMERRCTLR21 */ + /* Skip ECMERRCTLR22 setting */ + /* Skip ECMERRCTLR23 setting */ + /* Skip ECMERRCTLR24 setting */ + /* Skip ECMERRCTLR25 setting */ + /* Skip ECMERRCTLR26 setting */ + /* Skip ECMERRCTLR27 setting */ + /* Skip ECMERRCTLR28 setting */ + /* Skip ECMERRCTLR29 setting */ + /* Skip ECMERRCTLR30 setting */ + /* Skip ECMERRCTLR31 setting */ + [14] = {0xFD850080U, 0x03E9043BU}, /* ECMERRCTLR32 */ + [15] = {0xFD850084U, 0x03E9043BU}, /* ECMERRCTLR33 */ + /* Skip ECMERRCTLR34 setting */ + [16] = {0xFD85008CU, 0x83B00800U}, /* ECMERRCTLR35 */ + [17] = {0xFD850090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */ + /* Skip ECMERRCTLR37 setting */ + [18] = {0xFD850098U, 0x00000002U}, /* ECMERRCTLR38 */ + /* Skip ECMERRCTLR39 setting */ + [19] = {0xFD8500A0U, 0x0000601EU}, /* ECMERRCTLR40 */ + [20] = {0xFD8500A4U, 0x20010000U}, /* ECMERRCTLR41 */ + /* Skip ECMERRCTLR42 setting */ + }; + + const ECM_ERROR_TABLE ecmerrtgtr_type2_tbl[TYPE2_ECM_REG_MAX] = { + [0] = {0xFD850200U, 0x40000003U}, /* ECMERRTGTR0 */ + [1] = {0xFD850204U, 0x04004000U}, /* ECMERRTGTR1 */ + [2] = {0xFD850208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */ + [3] = {0xFD85020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */ + [4] = {0xFD850210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */ + [5] = {0xFD850214U, 0x81FFFFFFU}, /* ECMERRTGTR5 */ + [6] = {0xFD850218U, 0x15000A80U}, /* ECMERRTGTR6 */ + [7] = {0xFD85021CU, 0x00801481U}, /* ECMERRTGTR7 */ + /* Skip ECMERRTGTR8 setting */ + /* Skip ECMERRTGTR9 setting */ + /* Skip ECMERRTGTR10 setting */ + /* Skip ECMERRTGTR11 setting */ + /* Skip ECMERRTGTR12 setting */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [8] = {0xFD850240U, 0x00003E9FU}, /* ECMERRTGTR16 */ + [9] = {0xFD850244U, 0x00938060U}, /* ECMERRTGTR17 */ + [10] = {0xFD850248U, 0x00341600U}, /* ECMERRTGTR18 */ + [11] = {0xFD85024CU, 0x0007FF30U}, /* ECMERRTGTR19 */ + [12] = {0xFD850250U, 0x02200220U}, /* ECMERRTGTR20 */ + [13] = {0xFD850254U, 0x0061820FU}, /* ECMERRTGTR21 */ + /* Skip ECMERRTGTR22 setting */ + /* Skip ECMERRTGTR23 setting */ + /* Skip ECMERRTGTR24 setting */ + /* Skip ECMERRTGTR25 setting */ + /* Skip ECMERRTGTR26 setting */ + /* Skip ECMERRTGTR27 setting */ + /* Skip ECMERRTGTR28 setting */ + /* Skip ECMERRTGTR29 setting */ + /* Skip ECMERRTGTR30 setting */ + /* Skip ECMERRTGTR31 setting */ + [14] = {0xFD850280U, 0x03E9043BU}, /* ECMERRTGTR32 */ + [15] = {0xFD850284U, 0x03E9043BU}, /* ECMERRTGTR33 */ + /* Skip ECMERRTGTR34 setting */ + [16] = {0xFD85028CU, 0x83B00800U}, /* ECMERRTGTR35 */ + [17] = {0xFD850290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */ + /* Skip ECMERRTGTR37 setting */ + [18] = {0xFD850298U, 0x00000002U}, /* ECMERRTGTR38 */ + /* Skip ECMERRTGTR39 setting */ + [19] = {0xFD8502A0U, 0x0000601EU}, /* ECMERRTGTR40 */ + [20] = {0xFD8502A4U, 0x20010000U}, /* ECMERRTGTR41 */ + /* Skip ECMERRTGTR42 setting */ + }; + + const ECM_ERROR_TABLE ecmerrctlr_type3_tbl[TYPE3_ECM_CTLREG_MAX] = { + /* Skip ECMERRCTLR0 setting */ + /* Skip ECMERRCTLR1 setting */ + /* Skip ECMERRCTLR2 setting */ + /* Skip ECMERRCTLR3 setting */ + /* Skip ECMERRCTLR4 setting */ + /* Skip ECMERRCTLR5 setting */ + /* Skip ECMERRCTLR6 setting */ + /* Skip ECMERRCTLR7 setting */ + /* Skip ECMERRCTLR8 setting */ + /* Skip ECMERRCTLR9 setting */ + /* Skip ECMERRCTLR10 setting */ + /* Skip ECMERRCTLR11 setting */ + /* Skip ECMERRCTLR12 setting */ + /* Skip ECMERRCTLR13 setting */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + [0] = {0xFD850040U, 0x33F00000U}, /* ECMERRCTLR16 */ + /* Skip ECMERRCTLR17 setting */ + /* Skip ECMERRCTLR18 setting */ + /* Skip ECMERRCTLR19 setting */ + /* Skip ECMERRCTLR20 setting */ + /* Skip ECMERRCTLR21 setting */ + /* Skip ECMERRCTLR22 setting */ + /* Skip ECMERRCTLR23 setting */ + /* Skip ECMERRCTLR24 setting */ + /* Skip ECMERRCTLR25 setting */ + /* Skip ECMERRCTLR26 setting */ + /* Skip ECMERRCTLR27 setting */ + /* Skip ECMERRCTLR28 setting */ + /* Skip ECMERRCTLR29 setting */ + /* Skip ECMERRCTLR30 setting */ + /* Skip ECMERRCTLR31 setting */ + /* Skip ECMERRCTLR32 setting */ + /* Skip ECMERRCTLR33 setting */ + /* Skip ECMERRCTLR34 setting */ + /* Skip ECMERRCTLR35 setting */ + /* Skip ECMERRCTLR36 setting */ + /* Skip ECMERRCTLR37 setting */ + /* Skip ECMERRCTLR38 setting */ + /* Skip ECMERRCTLR39 setting */ + /* Skip ECMERRCTLR40 setting */ + /* Skip ECMERRCTLR41 setting */ + /* Skip ECMERRCTLR42 setting */ + }; + + const ECM_ERROR_TABLE ecmerrtgtr_type3_tbl[TYPE3_ECM_TGTREG_MAX] = { + [0] = {0xFD850200U, 0x80000000U}, /* ECMERRTGTR0 */ + /* Skip ECMERRTGTR1 setting */ + /* Skip ECMERRTGTR2 setting */ + /* Skip ECMERRTGTR3 setting */ + /* Skip ECMERRTGTR4 setting */ + /* Skip ECMERRTGTR5 setting */ + /* Skip ECMERRTGTR6 setting */ + /* Skip ECMERRTGTR7 setting */ + /* Skip ECMERRTGTR8 setting */ + /* Skip ECMERRTGTR9 setting */ + /* Skip ECMERRTGTR10 setting */ + /* Skip ECMERRTGTR11 setting */ + /* Skip ECMERRTGTR12 setting */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [1] = {0xFD850240U, 0x33F00000U}, /* ECMERRTGTR16 */ + /* Skip ECMERRTGTR17 setting */ + /* Skip ECMERRTGTR18 setting */ + /* Skip ECMERRTGTR19 setting */ + /* Skip ECMERRTGTR20 setting */ + /* Skip ECMERRTGTR21 setting */ + /* Skip ECMERRTGTR22 setting */ + /* Skip ECMERRTGTR23 setting */ + /* Skip ECMERRTGTR24 setting */ + /* Skip ECMERRTGTR25 setting */ + /* Skip ECMERRTGTR26 setting */ + /* Skip ECMERRTGTR27 setting */ + /* Skip ECMERRTGTR28 setting */ + /* Skip ECMERRTGTR29 setting */ + /* Skip ECMERRTGTR30 setting */ + /* Skip ECMERRTGTR31 setting */ + /* Skip ECMERRTGTR32 setting */ + /* Skip ECMERRTGTR33 setting */ + /* Skip ECMERRTGTR34 setting */ + /* Skip ECMERRTGTR35 setting */ + /* Skip ECMERRTGTR36 setting */ + /* Skip ECMERRTGTR37 setting */ + /* Skip ECMERRTGTR38 setting */ + /* Skip ECMERRTGTR39 setting */ + /* Skip ECMERRTGTR40 setting */ + /* Skip ECMERRTGTR41 setting */ + /* Skip ECMERRTGTR42 setting */ + }; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + NOTICE("ECMERRCTLR and ECMERRTGTR register initial setting.\n"); + /* For the initial setting flow for Type-1, please refer to the following + * section in the "SAN(Safety Application Note)." + * Section 4.1.2.5 : (1) + * Section 4.1.4.5 : (1) + * Section 4.12.1.5 : (1) + * Section 4.14.5 : (1) + * Section 4.2.7.5 : (1) + * Section 4.2.9.5 : (1) + * Section 4.23.5 : (1) + * Section 4.25.5 : (1) + * Section 4.3.14.5 : (1) + * Section 4.3.19.5 : (1) + * Section 4.3.21.5 : (1) + * Section 4.4.16.5 : (1) + * Section 4.4.18.5 : (1) + * Section 4.4.20.5 : (1) + * Section 4.4.3.5 : (1) + * Section 4.4.4.5 : (1) + * Section 4.4.6.5 : (1) + * Section 4.4.7.5 : (1) + * Section 4.4.9.5 : (1) + * Section 4.5.1.5 : (1) + * Section 4.7.1.5 : (1) + * Section 4.7.10.5 : (1) + * Section 4.7.3.5 : (1) + * Section 4.7.4.5 : (1) + * Section 4.7.7.5 : (1) + * Section 4.7.8.5 : (1) + * Section 5.8.1.5 : (1) + */ + for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++) + { + /* Initial Setting Type-1 for ECMERRCTLR registers */ + reg = mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr); + reg |= (ecmerrctlr_type1_tbl[loop].value); + ecm_write(ecmerrctlr_type1_tbl[loop].phys_addr, reg); + + INFO("[Type-1]ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrctlr_type1_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr), + ecmerrctlr_type1_tbl[loop].value); + } + + for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++) + { + /* Initial Setting Type-1 for ECMERRTGTR registers */ + reg = mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr); + reg &= ~(ecmerrtgtr_type1_tbl[loop].value); + ecm_write(ecmerrtgtr_type1_tbl[loop].phys_addr, reg); + + INFO("[Type-1]ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrtgtr_type1_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr), + ecmerrtgtr_type1_tbl[loop].value); + } + + /* For the initial setting flow for Type-2, please refer to the following + * section in the "SAN(Safety Application Note)." + * Section 4.1.1.5 : (1) + * Section 4.12.2.5 : (1) + * Section 4.12.3.5 : (1) + * Section 4.15.5 : (1) + * Section 4.16.5 : (1) + * Section 4.18.5 : (1) + * Section 4.2.1.5 : (1) + * Section 4.2.10.5 : (1) + * Section 4.2.12.5 : (1) + * Section 4.2.2.5 : (1) + * Section 4.2.4.5 : (1) + * Section 4.2.8.5 : (1) + * Section 4.3.1.5 : (1) + * Section 4.3.10.5 : (1) + * Section 4.3.11.5 : (1) + * Section 4.3.12.5 : (1) + * Section 4.3.13.5 : (1) + * Section 4.3.15.5 : (1) + * Section 4.3.16.5 : (1) + * Section 4.3.2.5 : (1) + * Section 4.3.5.5 : (1) + * Section 4.3.7.5 : (1) + * Section 4.3.8.5 : (1) + * Section 4.4.10.5 : (1) + * Section 4.4.12.5 : (6) + * Section 4.4.13.5 : (1) + * Section 4.4.14.5 : (1) + * Section 4.4.15.5 : (1) + * Section 4.4.2.5 : (1) + * Section 4.5.3.5 : (1) + * Section 4.6.5 : (1) + * Section 4.7.2.5 : (1) + * Section 5.11.5 : (1) + * Section 5.12.5 : (1) + * Section 5.13.5 : (1) + * Section 5.4.5 : (1) + * Section 5.6.5 : (1) + * Section 5.8.2.5 : (1) + */ + for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++) + { + /* Initial Setting Type-2 for ECMERRCTLR registers */ + reg = mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr); + reg |= (ecmerrctlr_type2_tbl[loop].value); + ecm_write(ecmerrctlr_type2_tbl[loop].phys_addr, reg); + + INFO("[Type-2]ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrctlr_type2_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr), + ecmerrctlr_type2_tbl[loop].value); + } + + for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++) + { + /* Initial Setting Type-2 for ECMERRTGTR registers */ + reg = mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr); + reg &= ~(ecmerrtgtr_type2_tbl[loop].value); + ecm_write(ecmerrtgtr_type2_tbl[loop].phys_addr, reg); + + INFO("[Type-2]ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrtgtr_type2_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr), + ecmerrtgtr_type2_tbl[loop].value); + } + + /* For the initial setting flow for Type-3, please refer to the following + * section in the "SAN(Safety Application Note)." + * Section 4.19.1.5 : (3) + * Section 6.2.5 : (12) + */ + for (loop = 0U; loop < TYPE3_ECM_CTLREG_MAX; loop++) + { + /* Initial Setting Type-3 for ECMERRCTLR registers */ + reg = mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr); + reg |= (ecmerrctlr_type3_tbl[loop].value); + ecm_write(ecmerrctlr_type3_tbl[loop].phys_addr, reg); + + INFO("[Type-3]ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrctlr_type3_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr), + ecmerrctlr_type3_tbl[loop].value); + } + + for (loop = 0U; loop < TYPE3_ECM_TGTREG_MAX; loop++) + { + /* Initial Setting Type-3 for ECMERRTGTR registers */ + reg = mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr); + reg &= ~(ecmerrtgtr_type3_tbl[loop].value); + ecm_write(ecmerrtgtr_type3_tbl[loop].phys_addr, reg); + + INFO("[Type-3]ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrtgtr_type3_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr), + ecmerrtgtr_type3_tbl[loop].value); + } + + /* Lock the ECM registers */ + ecm_lock(); +} +/* End of function ecm_init_setting(void) */ +#endif /* ECM_ERROR_ENABLE == 1 */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h new file mode 100644 index 0000000..2c2f80b --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h @@ -0,0 +1,47 @@ +/******************************************************************************* + * Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM driver header + ******************************************************************************/ + +#ifndef ECM_ENABLE_V4M +#define ECM_ENABLE_V4M + +#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1)) +void ecm_unlock(void); +void ecm_write(uint32_t adr, uint32_t val); +void ecm_lock(void); +#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_init_setting(void); +#endif /* ECM_ERROR_ENABLE == 1 */ + +#endif/* ECM_ENABLE_V4M */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/dma/dma.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/dma/dma.c new file mode 100644 index 0000000..a9d6e77 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/dma/dma.c @@ -0,0 +1,182 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : DMA driver + ******************************************************************************/ +/****************************************************************************** + * @file dma.c + * - Version : 0.07 + * @brief DMA driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 30.09.2021 0.02 Change function name load_start and + * load_end function. + * : 15.10.2021 0.03 modified to not use CHCLR. + * : 06.01.2022 0.04 Add exception handling for ICUMX_WDTA. + * : 02.02.2022 0.05 Add MFIS Lock/Unlock. + * : 22.06.2022 0.06 Replace address align check to function. + * : Remove some defines. + * : 20.12.2022 0.07 Add mask when writing to TCR register. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +#define DMOR_INIT (uint16_t)(0x0301U) +#define DMOR_HW_INIT (uint16_t)(0x0000U) +#define TCR_CNT_SHIFT (6U) +#define TCR_UPPER8BIT_MASK (0x00FFFFFFU) +#define CHCR_TRN_MODE (0x00105409U) +#define CHCR_TE_BIT (0x00000002U) +#define TE_FLAG (0x00000000U) +#define CHCR_CAE_BIT (0x80000000U) +#define CHCR_CAE_BIT_NOERROR (0x00000000U) +#define CHCR_CAIE_BIT (0x40000000U) +#define CHCR_DPM_BIT (0x30000000U) +#define CHCR_RPT_BIT (0x0F000000U) +#define CHCR_WAIT_BIT (0x00800000U) +#define CHCR_DPB_BIT (0x00400000U) +#define CHCR_DSE_BIT (0x00080000U) +#define CHCR_DSIE_BIT (0x00040000U) +#define CHCR_DM_BIT (0x0000C000U) +#define CHCR_SM_BIT (0x00003000U) +#define CHCR_RS_BIT (0x00000F00U) +#define CHCR_TS_BIT (0x00300018U) +#define CHCR_IE_BIT (0x00000004U) +#define CHCR_TE_BIT (0x00000002U) +#define CHCR_DE_BIT (0x00000001U) +#define CHCR_CONF_MASK (CHCR_TS_BIT | CHCR_DM_BIT | CHCR_SM_BIT | CHCR_RS_BIT | CHCR_DE_BIT) +#define CHCR_DESCRIPTOR_CONF_MASK (CHCR_DPM_BIT | CHCR_RPT_BIT | CHCR_WAIT_BIT | CHCR_DPB_BIT) +#define CHCR_INTERRUPT_MASK (CHCR_CAIE_BIT | CHCR_DSIE_BIT | CHCR_IE_BIT) +#define CHCR_FLAG_MASK (CHCR_CAE_BIT | CHCR_DSE_BIT | CHCR_TE_BIT) +#define CHCR_ALL_BIT_MASK (CHCR_CONF_MASK | CHCR_DESCRIPTOR_CONF_MASK | CHCR_INTERRUPT_MASK | CHCR_FLAG_MASK) +#define DAR_HW_INIT (0x00000000U) +#define SAR_HW_INIT (0x00000000U) +#define TCR_HW_INIT (0x00000000U) + +/* fraction mask for 256-byte units */ +#define FRACTION_MASK_256_BYTE (0x000000FFU) + +void dma_init(void) +{ + uint32_t reg; + + /* DMA operation */ + mem_write16(RTDMA_DMOR, DMOR_INIT); + /* DMA secure control register */ + reg = mem_read32(RTDMA_DMSEC); + reg |= ((uint32_t)1U << DMACH); + mem_write32(RTDMA_DMSEC, reg); + + reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH)); + reg &= ~(CHCR_ALL_BIT_MASK); + mem_write32(dma_get_rtdma_chcr_addr(DMACH), reg); +} +/* End of function dma_init(void) */ + +void dma_trans_start(uint32_t dst, uint32_t src, uint32_t len) +{ + uint32_t reg; + + /* dst and src must be 64-byte boundary. */ + dma_address_align_check(dst, src); + + /* round up 256 byte alignment */ + len += FRACTION_MASK_256_BYTE; + len &= (~(uint32_t)(FRACTION_MASK_256_BYTE)); + + /* DMA destination address */ + mem_write32(dma_get_rtdma_dar_addr(DMACH), dst); + /* DMA source address */ + mem_write32(dma_get_rtdma_sar_addr(DMACH), src); + /* DMA 64bytes-unit transfer count */ + mem_write32(dma_get_rtdma_tcr_addr(DMACH), ((len >> TCR_CNT_SHIFT) & TCR_UPPER8BIT_MASK)); + /* Lock to avoid conflict with RPC */ + mfis_lock(); + /* DMA channel control */ + reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH)); + reg |= CHCR_TRN_MODE; + mem_write32(dma_get_rtdma_chcr_addr(DMACH), reg); +} +/* End of function dma_trans_start(uint32_t dst, uint32_t src, uint32_t len) */ + +void dma_trans_end_check(void) +{ + uint32_t reg; + + /* Check end of DMA transfer. */ + do + { + wdt_restart(); + reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH)); + /* Check error of DMA transfer */ + if ((reg & CHCR_CAE_BIT) != CHCR_CAE_BIT_NOERROR) + { + ERROR("DMA - Channel Address Error\n"); + panic; + } + } while ((reg & CHCR_TE_BIT) == TE_FLAG); + + reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH)); + reg &= ~(CHCR_ALL_BIT_MASK); + mem_write32(dma_get_rtdma_chcr_addr(DMACH), reg); + + rpc_end_state_check(); + /* Unlock to avoid conflict with RPC */ + mfis_unlock(); +} +/* End of function dma_trans_end_check(void) */ + +void dma_release(void) +{ + uint32_t reg; + + /* DMA channel control */ + reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH)); + reg &= ~(CHCR_ALL_BIT_MASK); + mem_write32(dma_get_rtdma_chcr_addr(DMACH), reg); + + /* DMA destination address */ + mem_write32(dma_get_rtdma_dar_addr(DMACH), DAR_HW_INIT); + /* DMA source address */ + mem_write32(dma_get_rtdma_sar_addr(DMACH), SAR_HW_INIT); + /* DMA 64bytes-unit transfer count */ + mem_write32(dma_get_rtdma_tcr_addr(DMACH), TCR_HW_INIT); + + reg = mem_read32(RTDMA_DMSEC); + reg &= (~((uint32_t)1U << DMACH)); + mem_write32(RTDMA_DMSEC, reg); + + /* DMA operation */ + mem_write16(RTDMA_DMOR, DMOR_HW_INIT); +} +/* End of function dma_release(void) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_boot.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_boot.c new file mode 100644 index 0000000..92e5d0a --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_boot.c @@ -0,0 +1,249 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC boot + ******************************************************************************/ +/****************************************************************************** + * @file emmc_boot.c + * - Version : 0.07 + * @brief eMMC initialze interface. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 30.09.2021 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Add WWDT timer reset function + * : 06.04.2022 0.05 Fix Set SDCLK to 200MHz + * : 23.05.2022 0.06 Integration of S4 and V4H + * : 24.06.2024 0.07 Add process that set SDHI_D1.8/3.3V to 1.8V. + *****************************************************************************/ + +#include "emmc_boot.h" +#include "mem_io.h" +#include "log.h" +#include "rom_api.h" +#include "image_load_emmc.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_multiboot.h" +#include "emmc_def.h" +#include "emmc_config.h" +#if (RCAR_LSI == RCAR_V4M) /* Gray Hawk */ +#include "i2c.h" +#include "remap.h" +#endif /* (RCAR_LSI == RCAR_V4M) */ + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Unions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Structs */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Globals */ +/************************************************************************************************/ + +/************************************************************************************************/ +/* Macros */ +/************************************************************************************************/ + +/************************************************************************************************/ +/* Prototypes */ +/************************************************************************************************/ +static void power_on_mmc(void); +static void set_sd_clock(void); +static void init_mmc_pin_function(void); +#if (RCAR_LSI == RCAR_V4M) /* Gray Hawk */ +static void sdhi_random_address_read_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *rd_buf); +static void sdhi_page_write_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *wr_buf); +static void pmic_set_sdhi_vdd18(void); +#endif /* (RCAR_LSI == RCAR_V4M) */ + +void emmc_initialize( void ) +{ +#if (RCAR_LSI == RCAR_V4M) /* Gray Hawk */ + /* Register I2C base address(physical:0xE6600000) to SIC REMAP14 for V4M. */ + set_sicremap_fcpr(); + pmic_set_sdhi_vdd18(); +#endif /* (RCAR_LSI == RCAR_V4M) */ + + /***************************************************************** + PFC setting + *****************************************************************/ + init_mmc_pin_function(); + + /***************************************************************** + CPG setting + *****************************************************************/ + power_on_mmc(); + set_sd_clock(); + +#if (RCAR_SA9_TYPE == EMMC_BOOT) + EMMC_ERROR_CODE result; + /* eMMC driver initialize */ + (void)emmc_init(); /* Normal clock mode */ + + /* Card power on */ + (void)emmc_memcard_power(TRUE); + + /* Card mount */ + result = emmc_mount(); + + if (result != EMMC_SUCCESS) + { + NOTICE("eMMC initialize error!!\n"); + panic; + } +#endif /* (RCAR_SA9_TYPE == EMMC_BOOT) */ +} /* End of function emmc_initialize( void ) */ + +/************************************************************************************************/ +/* Func power_on_mmc */ +/************************************************************************************************/ +static void power_on_mmc(void) +{ + uint32_t reg; + uint32_t tmp_val; + + tmp_val = CPG_MSTPCR_SDHI; + + reg = mem_read32(CPG_MSTPCR7D0); + if ((reg & tmp_val) != 0x0U) + { + reg &= ~(tmp_val); + cpg_reg_write(CPG_MSTPCR7D0, CPG_MSTPSR7D0, reg); + } + + do + { + reg = mem_read32(CPG_MSTPCR7D0); + } + while ((reg & tmp_val) != 0x0U); /* wait tmp_val=0 */ +} /* End of function power_on_mmc(void) */ + +/************************************************************************************************/ +/* Func set_sd_clock */ +/************************************************************************************************/ +static void set_sd_clock(void) +{ + uint32_t reg; + + reg = mem_read32(CPG_SD0CKCR0); + reg &= (~(CPG_SD0CKCR0_STP0HCK | CPG_SD0CKCR0_SDSRCFC_MASK | CPG_SD0CKCR0_SD0FC_MASK)); + reg |= CPG_SD0CKCR0_200MHZ; + cpg_reg_write(CPG_SD0CKCR0, CPG_SD0CKCR0, reg); /* Stop SDnH clock & SDn=200MHz */ +} /* End of function set_sd_clock(void) */ + +/************************************************************************************************/ +/* Func init_mmc_pin_function */ +/************************************************************************************************/ +static void init_mmc_pin_function(void) +{ + uint32_t reg; + + reg = mem_read32(PFC_POC_MMC_RW); + reg &= (~(PFC_POC_MMC_MASK)); + reg |= PFC_POC_MMC_VAL; + pfc_reg_write(PFC_POC_MMC_RW, reg); +} /* End of function init_mmc_pin_function(void) */ + +#if (RCAR_LSI == RCAR_V4M) /* Gray Hawk */ +static void sdhi_random_address_read_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *rd_buf) +{ + uint32_t data; + + /* for PMIC_RAA271005 */ + data = (access_add & 0x300U) >> 8U; + i2c3_write(sl_add, 0x00U, data); /* Bank Set */ + + i2c3_read(sl_add, (access_add & 0x0FFU), rd_buf); +} +/* End of function sdhi_random_address_read_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *rd_buf) */ + +static void sdhi_page_write_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *wr_buf) +{ + uint32_t data; + + /* for PMIC_RAA271005 */ + data = (access_add & 0x300U) >> 8U; + i2c3_write(sl_add, 0x00U, data); /* Bank Set */ + + i2c3_read(sl_add, (access_add & 0x0FFU), wr_buf); +} +/* End of function sdhi_page_write_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *wr_buf) */ + +static void pmic_set_sdhi_vdd18(void) +{ + /* In case of Gray Hawk board, change SDHI_18/33 voltage. */ + uint32_t slv_addr = 0xA8U; /* for PMIC-RAA271005: "reg 0xA8 0xA9 prot 0xAA 0xAB" */ + uint32_t data; + + /* Init I2C */ + i2c3_init(); + + /* Setting 1.8V to SDHI_D1.8/3.3V(VDDQ18_33_SDHI) on PMIC-RAA271005 */ + data = 0x1U; + i2c3_write(slv_addr, 0x00U, data); /* Write IO_PAGE. Chenge BANK1 */ + + i2c3_read(slv_addr, 0x3BU, &data); + if ((data & 0x0CU) != 0x0U) + { + data &= ~(0x0CU); + i2c3_write(slv_addr, 0x3BU, data); + } + + sdhi_random_address_read_pmic(slv_addr, 0x02U, &data); + if ((data & 0xF0U) == 0xB0U) + { + // RAA271005 rev.B only + data = 0x1U; + sdhi_page_write_pmic(slv_addr, 0x00U, &data); /* Write IO_PAGE. Chenge BANK1 */ + + sdhi_random_address_read_pmic(slv_addr, 0x3BU, &data); /* Read FLT_CTRL1 */ + + data &= 0xF3U; /* LDO1 Fault remove */ + sdhi_page_write_pmic(slv_addr, 0x3BU, &data); /* Write FLT_CTRL1 */ + + data = 0x0U; + sdhi_page_write_pmic(slv_addr, 0x00U, &data); /* Write IO_PAGE. Chenge BANK0 */ + } + + data = 0x75U; /* LDO voltage 1.8V Value */ + i2c3_write(slv_addr, 0xBAU, data); + sdhi_random_address_read_pmic(slv_addr, 0xBAU, &data); +} +/* End of function pmic_set_sdhi_vdd18(void) */ +#endif /* (RCAR_LSI == RCAR_V4M) */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_cmd.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_cmd.c new file mode 100644 index 0000000..c2455b3 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_cmd.c @@ -0,0 +1,580 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC CMD driver + ******************************************************************************/ +/****************************************************************************** + * @file emmc_cmd.c + * - Version : 0.04 + * @brief control of CMD in SDHI. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.02.2022 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Modify SDHI access from DMA to PIO. + *****************************************************************************/ + +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "micro_wait.h" +#include "log.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static void emmc_read_response(uint32_t *response); +static void emmc_little_to_big(uint8_t *p, uint32_t value); +static void emmc_data_transfer_dma(void); +static EMMC_ERROR_CODE emmc_response_check(const uint32_t *response, uint32_t error_mask); +static void emmc_softreset(void); +static void emmc_WaitCmd2Cmd_8Cycle(void); + +/* ********************************* CODE ********************************** */ + +/* execute MMC command. + * + * - Pre-conditions:
+ * * Clock to memory card IF is enabled. + * - Post-conditions:
+ * Requested command is executed successfully + * + * param[in] error_mask Errors to be checked (error values; HAL_MEMCARD_ERRORS) + * param[in,out] *response Response from the card (virtual address) + * return eMMC error code. + */ +EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response) +{ + EMMC_ERROR_CODE rtn_code = EMMC_ERR; + HAL_MEMCARD_RESPONSE_TYPE response_type; + HAL_MEMCARD_COMMAND_TYPE cmd_type; + EMMC_INT_STATE state; + + /* parameter check */ + if (response == NULL) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.clock_enable != TRUE) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + if (mmc_drv_obj.state_machine_blocking == TRUE) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR); + return EMMC_ERR; + } + + state = ESTATE_BEGIN; + response_type = (HAL_MEMCARD_RESPONSE_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK); + cmd_type = (HAL_MEMCARD_COMMAND_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_COMMAND_TYPE_MASK); + + /* state machine */ + while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END)) { + /* The interrupt factor flag is observed. */ + (void)emmc_interrupt(); + + /* wait interrupt */ + if (mmc_drv_obj.state_machine_blocking == TRUE) { + continue; + } + + switch (state) { + case ESTATE_BEGIN: + /* Busy check */ + if ((mmc_drv_obj.error_info.info2 & SD_INFO2_CBSY) != 0U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR_CARD_BUSY; + } + + /* clear register */ + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, SD_INFO2_CLEAR); + mem_write32(SD_INFO1_MASK, SD_INFO1_INFO0); + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + + /* fallthrough */ + + case ESTATE_ISSUE_CMD: + /* ARG */ + mem_write32(SD_ARG, mmc_drv_obj.cmd_info.arg); + /* issue cmd */ + mem_write32(SD_CMD, mmc_drv_obj.cmd_info.hw); + /* Set driver flag */ + mmc_drv_obj.state_machine_blocking = TRUE; + + if (response_type == HAL_MEMCARD_RESPONSE_NONE) { + state = ESTATE_NON_RESP_CMD; + } else { + state = ESTATE_RCV_RESP; + } + + break; + + case ESTATE_NON_RESP_CMD: + /* interrupt disable */ + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); + + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 0U) { + /* not receive expected interrupt */ + rtn_code = EMMC_ERR_RESPONSE; + state = ESTATE_ERROR; + } else { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } + break; + + case ESTATE_RCV_RESP: + /* interrupt disable */ + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); + + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + break; + } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 0U) { + /* not receive expected interrupt */ + rtn_code = EMMC_ERR_RESPONSE; + state = ESTATE_ERROR; + break; + } else { + /* nop */ + } + + /* read response */ + emmc_read_response(response); + + /* check response */ + rtn_code = emmc_response_check(response, error_mask); + if (rtn_code != EMMC_SUCCESS) { + state = ESTATE_ERROR; + break; + } + + if (response_type == HAL_MEMCARD_RESPONSE_R1b) { + /* R1b */ + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + state = ESTATE_RCV_RESPONSE_BUSY; + } else { + state = ESTATE_CHECK_RESPONSE_COMPLETE; + } + break; + + case ESTATE_RCV_RESPONSE_BUSY: + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + break; + } + /* DAT0 not Busy */ + if ((SD_INFO2_DAT0 & mmc_drv_obj.error_info.info2) != 0U) { + state = ESTATE_CHECK_RESPONSE_COMPLETE; + break; + } + break; + + case ESTATE_CHECK_RESPONSE_COMPLETE: + if (cmd_type >= HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE) { + state = ESTATE_DATA_TRANSFER; + } else { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } + break; + + case ESTATE_DATA_TRANSFER: + /* ADTC command */ + mmc_drv_obj.during_transfer = TRUE; + mmc_drv_obj.state_machine_blocking = TRUE; + + if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) { + /* DMA */ + emmc_data_transfer_dma(); + } else { + /* PIO */ + /* interrupt enable (FIFO read/write enable) */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) { + mem_write32(SD_INFO2_MASK, ( SD_INFO2_BWE | SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + } else { + mem_write32(SD_INFO2_MASK, ( SD_INFO2_BRE | SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + } + } + state = ESTATE_DATA_TRANSFER_COMPLETE; + break; + + case ESTATE_DATA_TRANSFER_COMPLETE: + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_TRANSFER_ERROR; + break; + } else { + /* success. nothing to do. */ + } + + /* DMAC error ? */ + if (mmc_drv_obj.dma_error_flag == TRUE) { + /* Error occurred in DMAC driver. */ + rtn_code = EMMC_ERR_FROM_DMAC_TRANSFER; + state = ESTATE_TRANSFER_ERROR; + } else if (mmc_drv_obj.during_dma_transfer == TRUE) { + /* DMAC not finished. unknown error */ + rtn_code = EMMC_ERR; + state = ESTATE_TRANSFER_ERROR; + } else { + mem_write32(SD_INFO1_MASK, SD_INFO1_INFO2); + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + + mmc_drv_obj.state_machine_blocking = TRUE; + + state = ESTATE_ACCESS_END; + } + break; + + case ESTATE_ACCESS_END: + + /* clear flag */ + if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) { + mem_write32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ + mem_write32(SD_STOP, 0x00000000U); + mmc_drv_obj.during_dma_transfer = FALSE; + } + + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, SD_INFO2_CLEAR); + + if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO2) != 0U) { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } else { + state = ESTATE_ERROR; + } + break; + + case ESTATE_TRANSFER_ERROR: + /* The error occurred in the Data transfer. */ + if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) { + mem_write32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ + mem_write32(SD_STOP, 0x00000000U); + mmc_drv_obj.during_dma_transfer = FALSE; + } + /* fallthrough */ + + case ESTATE_ERROR: + emmc_softreset(); + ERROR("%s:0x%08x\n",__func__,rtn_code); + return rtn_code; + + default: + state = ESTATE_END; + break; + } /* switch (state) */ + } /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */ + + /* force terminate */ + if (mmc_drv_obj.force_terminate == TRUE) { + /* timeout timer is expired. Or, PIO data transfer error. */ + /* Timeout occurred in the DMA transfer. */ + if (mmc_drv_obj.during_dma_transfer == TRUE) { + mmc_drv_obj.during_dma_transfer = FALSE; + } + emmc_softreset(); + + return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */ + } + + /* success */ + mmc_drv_obj.during_transfer = FALSE; + + return EMMC_SUCCESS; +} + +/** host controller softrest. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param None. + * return None. + */ +static void emmc_softreset(void) +{ + int32_t loop = 10000; + int32_t retry = 1000; + + /* flag clear */ + mmc_drv_obj.during_transfer = FALSE; + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.state_machine_blocking = FALSE; + mmc_drv_obj.force_terminate = FALSE; + mmc_drv_obj.dma_error_flag = FALSE; + + /* during operation ? */ + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U) { + /* wait CMDSEQ = 0 */ + while (loop > 0) { + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) == 0U) { + break; /* ready */ + } + + loop--; + if ((loop == 0) && (retry > 0)) { + micro_wait(1000U); /* wait 1ms */ + loop = 10000; + retry--; + } + } + } + + /* reset */ + mem_write32(SOFT_RST, ( mem_read32(SOFT_RST) & (~SOFT_RST_SDRST) )); /* Soft reset */ + mem_write32(SOFT_RST, ( mem_read32(SOFT_RST) | SOFT_RST_SDRST )); /* Soft reset released */ + + /* initialize */ + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, SD_INFO2_CLEAR); + mem_write32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ + +} + +/** read response + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * param[in,out] *response Response from the card + * return None. + */ +static void emmc_read_response(uint32_t *response) +{ + + uint8_t *p = NULL; + + if (response == NULL) { + return; + } + + /* read response */ + if (mmc_drv_obj.response_length == EMMC_MAX_RESPONSE_LENGTH) { + /* CSD or CID */ + p = (uint8_t *)(response); + emmc_little_to_big(p, ((mem_read32(SD_RSP76) << 8U) | (mem_read32(SD_RSP54) >> 24U))); /* [127:96] */ + emmc_little_to_big(p + 4U, ((mem_read32(SD_RSP54) << 8U) | (mem_read32(SD_RSP32) >> 24U))); /* [95:64] */ + emmc_little_to_big(p + 8U, ((mem_read32(SD_RSP32) << 8U) | (mem_read32(SD_RSP10) >> 24U))); /* [63:32] */ + emmc_little_to_big(p + 12U, (mem_read32(SD_RSP10) << 8U)); /* [31:0] */ + } else { + *response = mem_read32(SD_RSP10); /* [39:8] */ + } +} + +/** response check + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * param[in] *response Response from the card + * param[in] error_mask Errors to be checked (for R1/R1b response) + * return error code. + */ +static EMMC_ERROR_CODE emmc_response_check(const uint32_t *response, uint32_t error_mask) +{ + + HAL_MEMCARD_RESPONSE_TYPE response_type = (HAL_MEMCARD_RESPONSE_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) + & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK); + + if (response == NULL) { + return EMMC_ERR_PARAM; + } + + if (response_type == HAL_MEMCARD_RESPONSE_NONE) { + return EMMC_SUCCESS; + } + + /* response check */ + if (response_type <= HAL_MEMCARD_RESPONSE_R1b) { + /* R1 or R1b */ + mmc_drv_obj.current_state = (EMMC_R1_STATE)((*response & EMMC_R1_STATE_MASK) >> EMMC_R1_STATE_SHIFT); + if ((*response & error_mask) != 0U) { + return EMMC_ERR_CARD_STATUS_BIT; + } + } else if (response_type == HAL_MEMCARD_RESPONSE_R4) { + /* R4 */ + if ((*response & EMMC_R4_STATUS) != 0U) { + return EMMC_ERR_CARD_STATUS_BIT; + } + } else { + ; /* nothing to do. other type does not have status bit */ + } + + return EMMC_SUCCESS; +} + +/** brief converts endian from little to big + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param[in,out] p destination buffer address. + * param[in] value convert data.(little) + * return None. + */ +static void emmc_little_to_big(uint8_t *p, uint32_t value) +{ + if (p == NULL) { + return; + } + + p[0] = (uint8_t)(value >> 24U); + p[1] = (uint8_t)(value >> 16U); + p[2] = (uint8_t)(value >> 8U); + p[3] = (uint8_t)value; +} + +/** data transfer with DMA. + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * return error code. + */ +static void emmc_data_transfer_dma(void) +{ + mmc_drv_obj.during_dma_transfer = TRUE; + mmc_drv_obj.dma_error_flag = FALSE; + + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + + /* DMAC setting */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) { + /* transfer complete interrupt enable */ + mem_write32(DM_CM_INFO1_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE )); + mem_write32(DM_CM_INFO2_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE )); + /* BUFF --> FIFO */ + mem_write32(DM_CM_DTRAN_MODE, ( DM_CM_DTRAN_MODE_CH0 | DM_CM_DTRAN_MODE_BIT_WIDTH )); /* CH0(downstream), 64-bit width */ + } else { + /* transfer complete interrupt enable */ + mem_write32(DM_CM_INFO1_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE )); + mem_write32(DM_CM_INFO2_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE )); + /* FIFO --> BUFF */ + mem_write32(DM_CM_DTRAN_MODE, ( DM_CM_DTRAN_MODE_CH1 | DM_CM_DTRAN_MODE_BIT_WIDTH )); /* CH0(downstream), 64-bit width */ + } + mem_write32(DM_DTRAN_ADDR, ( ( (uintptr_t)mmc_drv_obj.buff_address_virtual & DM_DTRAN_ADDR_WRITE_MASK ) )); /* Set address */ + + mem_write32(DM_CM_DTRAN_CTRL, DM_CM_DTRAN_CTRL_START); /* DMAC Start */ +} + +/** wait cmd-cmd 8cycle + * + * - Pre-conditions:
+ * + * - Post-conditions:
+ * . + * + * return None. + */ +static void emmc_WaitCmd2Cmd_8Cycle(void) +{ + uint32_t dataL, wait = 0U; + + dataL = mem_read32(SD_CLK_CTRL); + dataL &= 0x000000FFU; + + switch (dataL) { + case 0xFFU: /* 1/1 10 us wait ( 1/200MHz)*8= 0.04 us(min) */ + wait = 10U; + break; + case 0x00U: /* 1/2 10 us wait ( 2/200MHz)*8= 0.08 us(min) */ + wait = 10U; + break; + case 0x01U: /* 1/4 10 us wait ( 4/200MHz)*8= 0.16 us(min) */ + wait = 10U; + break; + case 0x02U: /* 1/8 10 us wait ( 8/200MHz)*8= 0.32 us(min) */ + wait = 10U; + break; + case 0x04U: /* 1/16 10 us wait ( 16/200MHz)*8= 0.64 us(min) */ + wait = 10U; + break; + case 0x08U: /* 1/32 10 us wait ( 32/200MHz)*8= 1.28 us(min) */ + wait = 10U; + break; + case 0x10U: /* 1/64 10 us wait ( 64/200MHz)*8= 2.56 us(min) */ + wait = 10U; + break; + case 0x20U: /* 1/128 10 us wait (128/200MHz)*8= 5.12 us(min) */ + wait = 10U; + break; + case 0x40U: /* 1/256 20 us wait (256/200MHz)*8= 10.24 us(min) */ + wait = 20U; + break; + case 0x80U: /* 1/512 30 us wait (512/200MHz)*8= 20.48 us(min) */ + wait = 30U; + break; + default: + /* nop */ + break; + } + micro_wait(wait); + +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_init.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_init.c new file mode 100644 index 0000000..46ed5ca --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_init.c @@ -0,0 +1,311 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC initialze + ******************************************************************************/ +/****************************************************************************** + * @file emmc_init.c + * - Version : 0.05 + * @brief initialize of SDHI driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.02.2022 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Modify SDHI access from DMA to PIO. + * : 06.04/2022 0.05 Del SDnH clock & SDn=200MHz(Duplicate settings) + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ +st_mmc_base mmc_drv_obj; + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static void emmc_drv_init(void); +static EMMC_ERROR_CODE emmc_dev_init(void); +static EMMC_ERROR_CODE emmc_dev_finalize(void); +static void emmc_memset(void *buff, uint8_t data, uint32_t cnt); +static EMMC_ERROR_CODE emmc_reset_controller(void); +static void emmc_driver_config(void); +static void emmc_set_data_timeout(uint32_t data_timeout); + +/* ********************************* CODE ********************************** */ + +/** brief eMMC initialize. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR error from interrupt API. + */ +EMMC_ERROR_CODE emmc_init(void) +{ + /* initialize H/W */ + (void)emmc_reset_controller(); + + /* Configuration */ + emmc_driver_config(); + + return EMMC_SUCCESS; +} + +/** terminate emmc driver + * + * EMMC H/W and S/W resource is released. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * return None. + */ +EMMC_ERROR_CODE emmc_terminate(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* H/W finalize */ + result = emmc_dev_finalize(); + + /* driver finalize */ + emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base)); /* clear global variable */ + + return result; +} + +/** Function executes full reset to MMC host controller without taking power out from the memory card. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * Reset MMC host controller without taking power out from the memory card. + * Memory card preserves its state. + * + * return None + */ +static EMMC_ERROR_CODE emmc_reset_controller(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* initialize mmc driver */ + emmc_drv_init(); + + mmc_drv_obj.base_address = MMC0_SD_BASE; + + /* initialize H/W */ + result = emmc_dev_init(); + + mmc_drv_obj.initialize = TRUE; + + return result; + +} + +/** Configuration eMMC driver + * + * - Pre-conditions:
+ * initialized eMMC driver. + * - Post-conditions:
+ * . + * + * return None + */ +static void emmc_driver_config(void) +{ + /* Read/Write data timeout */ + emmc_set_data_timeout(EMMC_RW_DATA_TIMEOUT); +} + +/** Sets data timeout + * + * Sets the data timeout value for read and write operations. + * + * - Pre-conditions:
+ * initialized eMMC driver. + * + * - Post-conditions:
+ * After this function is called, the timeout value is set according to argument. + * + * param[in] time_out The desired timeout value in milliseconds. + * return None + */ +static void emmc_set_data_timeout(uint32_t data_timeout) +{ + mmc_drv_obj.data_timeout = data_timeout; +} + +/** eMMC driver initialize. (software) + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * return None. + */ +static void emmc_drv_init(void) +{ + /* initialize */ + emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base)); + + mmc_drv_obj.data_timeout = EMMC_RW_DATA_TIMEOUT; + + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; +} + +/** eMMC driver initialize. (H/W) + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * return None. + */ +static EMMC_ERROR_CODE emmc_dev_init(void) +{ + + /* MMCIF initialize */ + mem_write32(SD_INFO1, 0x00000000U); /* all interrupt clear */ + mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* all interrupt clear */ + mem_write32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ + + mem_write32(HOST_MODE, 0x00000000U); /* SD_BUF access width = 64-bit */ + mem_write32(SD_OPTION, 0x0000C0EEU); /* Bus width = 1bit, timeout=MAX */ + mem_write32(SD_CLK_CTRL, 0x00000000U); /* Automatic Control=Disable, Clock Output=Disable */ + + return EMMC_SUCCESS; +} + +/** EMMC H/W finalize + * + * EMMC Host and Card hardware resource is released. + * + * - Pre-conditions:
+ * . + * + * - Post-conditions:
+ * . + * return None. + */ +static EMMC_ERROR_CODE emmc_dev_finalize(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* MMC power off + * the power supply of eMMC device is always turning on. + * RST_n : Hi --> Low level. + */ + result = emmc_memcard_power(FALSE); + + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, 0x00000800U); + mem_write32(DM_CM_INFO1, 0x00000000U); + mem_write32(DM_CM_INFO2, 0x00000000U); + + mem_write32(SD_CLK_CTRL, 0x00000020U); + mem_write32(CC_EXT_MODE, 0x00000000U); + mem_write32(SD_STOP, 0x00000000U); + mem_write32(SD_SECCNT, 0x00000000U); + mem_write32(DM_CM_DTRAN_MODE, 0x00000000U); + mem_write32(DM_DTRAN_ADDR, 0x00000000U); + mem_write32(SD_OPTION, 0x00000000U); + mem_write32(DM_CM_DTRAN_CTRL, 0x00000000U); + + return result; +} + +/** Set power to memory card IF. + * This function control Vcc and Vccq and RST_n. + * + * attention + * CPU cannot control Vcc&Vccq. + * The power supply of eMMC device is always turning on. + * + * param[in] mode TRUE = power on, FALSE = power off + * + * retval EMMC_SUCCESS powering succeeded + * retval EMMC_ERR_CARD_POWER powering failed + */ +EMMC_ERROR_CODE emmc_memcard_power(uint32_t mode) +{ + if (mode == TRUE) { + /* power on (Vcc&Vccq is always power on) */ + mmc_drv_obj.card_power_enable = TRUE; + } else { + /* power off (Vcc&Vccq is always power on) */ + mmc_drv_obj.card_power_enable = FALSE; + mmc_drv_obj.mount = FALSE; + mmc_drv_obj.selected = FALSE; + } + + return EMMC_SUCCESS; +} + +/** memset(). no use C standard library. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param[in,out] buff pointer to buffer (virtual) + * param[in] data fill data. + * param[in] cnt fill size (number of bytes) + * return None. + */ +static void emmc_memset(void *buff, uint8_t data, uint32_t cnt) +{ + uint8_t *tmp = NULL; + tmp = (uint8_t *)buff; + + if (buff == NULL) { + return; + } + + while (cnt > 0U) { + *tmp = data; + tmp++; + cnt--; + } +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_interrupt.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_interrupt.c new file mode 100644 index 0000000..e1d344d --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_interrupt.c @@ -0,0 +1,227 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC interrupt + ******************************************************************************/ +/****************************************************************************** + * @file emmc_interrupt.c + * - Version : 0.04 + * @brief state check of SDHI. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.02.2022 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Modify SDHI access from DMA to PIO. + *****************************************************************************/ + +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "log.h" +#include +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual); + + +/* ********************************* CODE ********************************** */ + + + +/** emmc driver interrupt service routine. + * + * - Pre-conditions:
+ * Must be block emmc driver state machine. + * - Post-conditions:
+ * unblocking emmc driver state machine. + * + * retval INT_SUCCESS + */ +uint32_t emmc_interrupt(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* SD_INFO */ + mmc_drv_obj.error_info.info1 = mem_read32(SD_INFO1); + mmc_drv_obj.error_info.info2 = mem_read32(SD_INFO2); + + /* SD_INFO EVENT */ + mmc_drv_obj.int_event1 = mmc_drv_obj.error_info.info1 & mem_read32(SD_INFO1_MASK); + mmc_drv_obj.int_event2 = mmc_drv_obj.error_info.info2 & mem_read32(SD_INFO2_MASK); + + /* ERR_STS */ + mmc_drv_obj.error_info.status1 = mem_read32(SD_ERR_STS1); + mmc_drv_obj.error_info.status2 = mem_read32(SD_ERR_STS2); + + /* DM_CM_INFO */ + mmc_drv_obj.error_info.dm_info1 = mem_read32(DM_CM_INFO1); + mmc_drv_obj.error_info.dm_info2 = mem_read32(DM_CM_INFO2); + + /* DM_CM_INFO EVENT */ + mmc_drv_obj.dm_event1 = mmc_drv_obj.error_info.dm_info1 & mem_read32(DM_CM_INFO1_MASK); + mmc_drv_obj.dm_event2 = mmc_drv_obj.error_info.dm_info2 & mem_read32(DM_CM_INFO2_MASK); + + /* ERR SD_INFO2 */ + if ((SD_INFO2_ALL_ERR & mmc_drv_obj.int_event2) != 0U) { + mem_write32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */ + mem_write32(SD_INFO1, 0x00000000U); /* interrupt clear */ + mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } + + /* PIO Transfer */ + /* BWE/BRE */ + else if ((( SD_INFO2_BWE | SD_INFO2_BRE) & mmc_drv_obj.int_event2) != 0U) { + /* BWE */ + if (( SD_INFO2_BWE & mmc_drv_obj.int_event2) != 0U) { + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BWE)); /* interrupt clear */ + } + /* BRE */ + else { + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BRE)); /* interrupt clear */ + } + + result = emmc_trans_sector((uint32_t *)mmc_drv_obj.buff_address_virtual); /* sector R/W */ + mmc_drv_obj.buff_address_virtual += EMMC_BLOCK_LENGTH; + mmc_drv_obj.remain_size -= EMMC_BLOCK_LENGTH; + + if (result != EMMC_SUCCESS) { + /* data transfer error */ + ERROR("%s:0x%08x\n",__func__, result); + + /* Panic */ + mem_write32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */ + mem_write32(SD_INFO1, 0x00000000U); /* interrupt clear */ + mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */ + mmc_drv_obj.force_terminate = TRUE; + } else { + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; + } + + /* DMA_TRANSFER */ + /* DM_CM_INFO1: DMA-ch0 transfer complete or error occured */ + else if ((DM_CM_INFO_DTRANEND0 & mmc_drv_obj.dm_event1) != 0U) { + mem_write32(DM_CM_INFO1, 0x00000000U); + mem_write32(DM_CM_INFO2, 0x00000000U); + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BWE)); /* interrupt clear */ + /* DM_CM_INFO2: DMA-ch0 error occured */ + if (( DM_CM_INFO_DTRANEND0 & mmc_drv_obj.dm_event2) != 0U) { + mmc_drv_obj.dma_error_flag = TRUE; + } else { + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; /* wait next interrupt */ + } + /* DM_CM_INFO1: DMA-ch1 transfer complete or error occured */ + else if ((DM_CM_INFO_DTRANEND1 & mmc_drv_obj.dm_event1) != 0U) { + mem_write32(DM_CM_INFO1, 0x00000000U); + mem_write32(DM_CM_INFO2, 0x00000000U); + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BRE)); /* interrupt clear */ + /* DM_CM_INFO2: DMA-ch1 error occured */ + if (( DM_CM_INFO_DTRANEND1 & mmc_drv_obj.dm_event2) != 0U) { + mmc_drv_obj.dma_error_flag = TRUE; + } else { + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; /* wait next interrupt */ + } + + /* Response end */ + else if ((SD_INFO1_INFO0 & mmc_drv_obj.int_event1) != 0U) { + mem_write32(SD_INFO1, (mem_read32(SD_INFO1) & ~SD_INFO1_INFO0)); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } + /* Access end */ + else if ((SD_INFO1_INFO2 & mmc_drv_obj.int_event1) != 0U) { + mem_write32(SD_INFO1, (mem_read32(SD_INFO1) & ~SD_INFO1_INFO2)); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } else { + /* nothing to do. */ + } + + return 0U; +} + +/** Data transfer function with PIO (Single sector). + * + * - Pre-conditions:
+ * Called from interrupt service. + * - Post-conditions:
+ * . + * + * param[in,out] buff_address_virtual Dest/Src buffer address(virtual). + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_PARAM parameter error. + * retval EMMC_ERR_STATE state error. + */ +static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual) +{ + uint32_t length, i; + uint64_t *bufPtrLL; + + if (buff_address_virtual == NULL) { + return EMMC_ERR_PARAM; + } + + if ((mmc_drv_obj.during_transfer != TRUE) || (mmc_drv_obj.remain_size == 0U)) { + return EMMC_ERR_STATE; + } + + bufPtrLL = (uint64_t*)buff_address_virtual; + length = mmc_drv_obj.remain_size; + + /* data transefer */ + for (i = 0U; i < (length >> 3U); i++) { + /* Write */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) { + mem_write64(SD_BUF0, *bufPtrLL); /* buffer --> FIFO */ + } + /* Read */ + else { + *bufPtrLL = mem_read64(SD_BUF0); /* FIFO --> buffer */ + } + bufPtrLL++; + } + + return EMMC_SUCCESS; +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_mount.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_mount.c new file mode 100644 index 0000000..ba0a0f9 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_mount.c @@ -0,0 +1,767 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC Mount + ******************************************************************************/ +/****************************************************************************** + * @file emmc_mount.c + * - Version : 0.04 + * @brief initialize of condition. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.02.2022 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Modify SDHI access from DMA to PIO. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include +#include "micro_wait.h" +#include "remap.h" +#include "log.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static EMMC_ERROR_CODE emmc_clock_ctrl(uint32_t mode); +static EMMC_ERROR_CODE emmc_card_init(void); +static EMMC_ERROR_CODE emmc_high_speed(void); +static EMMC_ERROR_CODE emmc_bus_width(uint32_t width); +static uint32_t emmc_set_timeout_register_value(uint32_t freq); +static void set_sd_clk(uint32_t clkDiv); +static uint32_t emmc_calc_tran_speed(uint32_t* freq); + +/* ********************************* CODE ********************************** */ + +/** eMMC mount operation. + * + * Sequence is the following. + * 1) Bus initialization (emmc_card_init()) + * 2) Switching to high speed mode. (emmc_high_speed()) + * 3) Changing the data bus width. (emmc_bus_width()) + * + * - Pre-conditions:
+ * eMMC driver is initialized. The power supply of MMC IF must be turning on. + * - Post-conditions:
+ * MMC card state changes to transfer state. + * + * return eMMC error code. + */ +EMMC_ERROR_CODE emmc_mount(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || (mmc_drv_obj.card_power_enable != TRUE) + || ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U)) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* initialize card (IDLE state --> Transfer state) */ + result = emmc_card_init(); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + (void)emmc_clock_ctrl(FALSE); + return result; + } + + /* Switching high speed mode */ + result = emmc_high_speed(); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + (void)emmc_clock_ctrl(FALSE); + return result; + } + + /* Changing the data bus width */ + result = emmc_bus_width(8U); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + (void)emmc_clock_ctrl(FALSE); + return result; + } + + /* mount complete */ + mmc_drv_obj.mount = TRUE; + + return EMMC_SUCCESS; +} + +/** Bus initialization function + * + * - Pre-conditions:
+ * eMMC driver is initialized. The power supply of MMC IF must be turning on. + * - Post-conditions:
+ * MMC card state changes to transfer state. + * + * retval EMMC_SUCCESS successful. + * return eMMC error code. + * attention upper layer must be check pre-conditions. + */ +static EMMC_ERROR_CODE emmc_card_init(void) +{ + int32_t retry; + uint32_t freq = MMC_400KHZ; /* 390KHz */ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t resultCalc = 0U; + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || (mmc_drv_obj.card_power_enable != TRUE) + || ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U)) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* clock on (force change) */ + mmc_drv_obj.current_freq = 0U; + mmc_drv_obj.max_freq = MMC_20MHZ; /* MMC_20MHZ = MMC_12MHZ = 12.187MHz */ + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return EMMC_ERR; + } + + micro_wait(1000U); /* wait 1ms */ + + /* CMD0, arg=0x00000000 */ + result = emmc_send_idle_cmd (0x00000000U); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + micro_wait(200U); /* wait 74clock 390kHz(189.74us)*/ + + /* CMD1 */ + emmc_make_nontrans_cmd(CMD1_SEND_OP_COND, EMMC_HOST_OCR_VALUE); + for (retry = 300; retry > 0; retry--) { + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + if ((mmc_drv_obj.r3_ocr & EMMC_OCR_STATUS_BIT) != 0U) { + break; /* card is ready. exit loop */ + } + micro_wait(1000U); /* wait 1ms */ + } + + if (retry == 0) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_TIMEOUT); + return EMMC_ERR_TIMEOUT; + } + + if ((mmc_drv_obj.r3_ocr & EMMC_OCR_ACCESS_MODE_MASK) != EMMC_OCR_ACCESS_MODE_SECT) { + /* unknown value */ + ERROR("%s:0x%08x\n",__func__,EMMC_ERR); + return EMMC_ERR; + } + + /* CMD2 */ + emmc_make_nontrans_cmd(CMD2_ALL_SEND_CID_MMC, 0x00000000U); + mmc_drv_obj.response = (uint32_t *)(&mmc_drv_obj.cid_data[0U]); /* use CID special buffer */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + /* CMD3 */ + emmc_make_nontrans_cmd(CMD3_SET_RELATIVE_ADDR, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + /* CMD9 : CSD */ + emmc_make_nontrans_cmd(CMD9_SEND_CSD, EMMC_RCA << 16U); + mmc_drv_obj.response = (uint32_t *)(&mmc_drv_obj.csd_data[0U]); /* use CSD special buffer */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + /* card version check */ + if (EMMC_CSD_SPEC_VARS() < 4U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_ILLEGAL_CARD); + return EMMC_ERR_ILLEGAL_CARD; + } + + /* CMD7 (select card) */ + emmc_make_nontrans_cmd(CMD7_SELECT_CARD, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + mmc_drv_obj.selected = TRUE; + + /* card speed check */ + resultCalc = emmc_calc_tran_speed(&freq); /* Card spec is calculated from TRAN_SPEED(CSD). */ + if (resultCalc == 0U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_ILLEGAL_CARD); + return EMMC_ERR_ILLEGAL_CARD; + } + mmc_drv_obj.max_freq = freq; /* max frequency (card spec) */ + + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return EMMC_ERR; + } + + /* set read/write timeout */ + mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(freq); + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) | mmc_drv_obj.data_timeout)); + + /* SET_BLOCKLEN:512byte */ + /* CMD16 */ + emmc_make_nontrans_cmd(CMD16_SET_BLOCKLEN, EMMC_BLOCK_LENGTH); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + /* Transfer Data Length */ + mem_write32(SD_SIZE, EMMC_BLOCK_LENGTH); + + /* CMD8 : EXT_CSD */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0U]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + /* CMD12 is not send. + * If BUS initialization is failed, user must be execute Bus initialization again. + * Bus initialization is start CMD0(soft reset command). + */ + ERROR("%s\n",__func__); + return result; + } + + return EMMC_SUCCESS; +} + +/** Switching to high-speed mode + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * EXT_CSD data must be stored in mmc_drv_obj.ext_csd_data[]. + * + * - Post-conditions:
+ * Change the clock frequency to 26MHz or 52MHz. + * + * retval EMMC_SUCCESS successful or aleady switching. + * retval EMMC_ERR_STATE state error. + * retval EMMC_ERR unknown error. + * return emmc error code. + */ +static EMMC_ERROR_CODE emmc_high_speed(void) +{ + uint32_t freq; /**< High speed mode clock frequency */ + EMMC_ERROR_CODE result = EMMC_ERR; + uint8_t cardType; + + /* state check */ + if (mmc_drv_obj.selected != TRUE) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* max frequency */ + cardType = (uint8_t)mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_CARD_TYPE]; + if ((cardType & EMMC_EXT_CSD_CARD_TYPE_52MHZ) != 0U) { + freq = MMC_52MHZ; + } else if ((cardType & EMMC_EXT_CSD_CARD_TYPE_26MHZ) != 0U) { + freq = MMC_26MHZ; + } else { + freq = MMC_20MHZ; + } + + /* Hi-Speed-mode selction */ + if (( MMC_52MHZ == freq) || ( MMC_26MHZ == freq)) { + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + } + + /* set mmc clock */ + mmc_drv_obj.max_freq = freq; + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return EMMC_ERR; + } + + /* set read/write timeout */ + mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(freq); + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) | mmc_drv_obj.data_timeout)); + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK_WITHOUT_CRC, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + return EMMC_SUCCESS; +} + +/** Changing the data bus width + * + * if chinging the data bus width failed, card is reset by CMD0. + * Please do Bus initialization over again. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * + * - Post-conditions:
+ * Change the data bus width to 8bit or 4bit. + * mmc_drv_obj.ext_csd_data is updated. + * + * param[in] width bus width (8 or 4) + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_PARAM parameter error + * retval EMMC_ERR_STATE state error. + * + */ +static EMMC_ERROR_CODE emmc_bus_width(uint32_t width) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* parameter check */ + if ((width != 8U) && (width != 4U) && (width != 1U)) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.selected != TRUE) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH)(width >> 2U); /* 2 = 8bit, 1 = 4bit, 0 =1bit */ + + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, ( EMMC_SWITCH_BUS_WIDTH_1 | ((uint32_t)(mmc_drv_obj.bus_width) << 8U))); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + /* occurred error */ + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; + goto EXIT; + } + + switch (mmc_drv_obj.bus_width) { + case HAL_MEMCARD_DATA_WIDTH_1_BIT: + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_WIDTH|SD_OPTION_WIDTH8)) | SD_OPTION_WIDTH )); + break; + case HAL_MEMCARD_DATA_WIDTH_4_BIT: + mem_write32(SD_OPTION, (mem_read32(SD_OPTION) & ~(SD_OPTION_WIDTH|SD_OPTION_WIDTH8))); + break; + case HAL_MEMCARD_DATA_WIDTH_8_BIT: + default: + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_WIDTH|SD_OPTION_WIDTH8)) | SD_OPTION_WIDTH8 )); + break; + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + goto EXIT; + } + + /* CMD8 : EXT_CSD */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0U]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + goto EXIT; + } + + return EMMC_SUCCESS; + +EXIT: + ERROR("%s:0x%08x\n",__func__,result); + return result; +} + +/** select access partition + * + * This function write the EXT_CSD register(PARTITION_ACCESS: PARTITION_CONFIG[2:0]). + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * selected partition can access. + * + * param[in] id user selects partitions to access. + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_STATE state error. + * retval EMMC_ERR_PARAM parameter error. + * return emmc error code. + */ +EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t partition; + uint32_t partition_config; + + /* state check */ + if (mmc_drv_obj.mount != TRUE) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* id has PARTITION_ACCESS(Bit[2:0]) */ + if ((uint32_t)((uint32_t)id & ~(uint32_t)PARTITION_ID_MASK) != 0U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* EXT_CSD[179] value */ + partition_config = (uint32_t)mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_PARTITION_CONFIG]; + if ((partition_config & (uint32_t)PARTITION_ID_MASK) == (uint32_t)id) { + result = EMMC_SUCCESS; + } else { + + partition_config = ((partition_config & (~(uint32_t)PARTITION_ID_MASK)) | (uint32_t)id); + partition = EMMC_SWITCH_PARTITION_CONFIG | (partition_config << 8U); + + result = emmc_set_ext_csd(partition); + } + + return result; +} + +/** set EXT CSD data + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * mmc_drv_obj.ext_csd_data[] is updated. + * + * param[in] arg argument of CMD6 + * return emmc error code. + */ +EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, arg); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + + /* CMD8 : EXT_CSD */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0U]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + return EMMC_SUCCESS; +} + +/** set request MMC clock frequency. + * + * Function returns EMMC_SUCCESS if clock is already running in the desired frequency. + * EMMC_ERR is returned if the HW doesn't support requested clock frequency. + * If matching frequence cannot be set the closest frequence below should be selected. + * For example if 50MHz is requested, but HW supports only 48MHz then 48MHz should be returned in the freq parameter. + * + * - Pre-conditions:
+ * initialized eMMC driver with emmc_init(). + * Memory card and MMCSDIO host controller needs to be powered up beforehand. + * + * - Post-conditions:
+ * Desired clock frequency is set to memory card IF. + * + * param[in] freq frequency [Hz] + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_STATE state error. + * retval EMMC_ERR busy + */ +EMMC_ERROR_CODE emmc_set_request_mmc_clock(const uint32_t *freq) +{ + /* parameter check */ + if (freq == NULL) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || (mmc_drv_obj.card_power_enable != TRUE)) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* clock is already running in the desired frequency. */ + if ((mmc_drv_obj.clock_enable == TRUE) && (mmc_drv_obj.current_freq == *freq)) { + return EMMC_SUCCESS; + } + + /* busy check */ + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR; + } + + set_sd_clk(*freq); + mmc_drv_obj.clock_enable = FALSE; + + return emmc_clock_ctrl(TRUE); /* clock on */ +} + +/** set sd clock. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * set mmc clock. + * + * param[in] clkDiv request freq + * return None. + */ +static void set_sd_clk(uint32_t clkDiv) +{ + uint32_t dataL; + + dataL = (mem_read32(SD_CLK_CTRL) & (~SD_CLK_CTRL_CLKDIV_MASK)); + + switch (clkDiv) { + case 1U: /* 1/1 */ + dataL |= 0x000000FFU; + break; + case 2U: /* 1/2 */ + dataL |= 0x00000000U; + break; + case 4U: /* 1/4 */ + dataL |= 0x00000001U; + break; + case 8U: /* 1/8 */ + dataL |= 0x00000002U; + break; + case 16U: /* 1/16 */ + dataL |= 0x00000004U; + break; + case 32U:/* 1/32 */ + dataL |= 0x00000008U; + break; + case 64U:/* 1/64 */ + dataL |= 0x00000010U; + break; + case 128U:/* 1/128 */ + dataL |= 0x00000020U; + break; + case 256U: /* 1/256 */ + dataL |= 0x00000040U; + break; + case 512U:/* 1/512 */ + dataL |= 0x00000080U; + break; + default: + /* nop */ + break; + } + + mem_write32(SD_CLK_CTRL, dataL); + mmc_drv_obj.current_freq = (uint32_t)clkDiv; +} + + +/** Enable/Disable MMC clock + * + * - Pre-conditions:
+ * Before enabling the clock for the first time the desired clock frequency must be set with + * emmc_set_clock_freq(). + * Berore setting mmc_drv_obj.data_timeout with emmc_set_data_timeout(). + * + * - Post-conditions:
+ * After this function is called, clock to memory card IF is on/off. + * + * param[in] mode TRUE = clock on, FALSE = clock off + * retval EMMC_SUCCESS succeeded + * retval EMMC_ERR Busy + */ +static EMMC_ERROR_CODE emmc_clock_ctrl(uint32_t mode) +{ + uint32_t value; + + /* busy check */ + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR; + } + + if (mode == TRUE) { + /* clock ON */ + value = ((mem_read32(SD_CLK_CTRL) | MMC_SD_CLK_START) & SD_CLK_WRITE_MASK); + mem_write32(SD_CLK_CTRL, value); /* on */ + mmc_drv_obj.clock_enable = TRUE; + } else { + /* clock OFF */ + value = ((mem_read32(SD_CLK_CTRL) & MMC_SD_CLK_STOP) & SD_CLK_WRITE_MASK); + mem_write32(SD_CLK_CTRL, value); /* off */ + mmc_drv_obj.clock_enable = FALSE; + } + + return EMMC_SUCCESS; +} + +/** Calculate Card support frequency. + * TRAN_SPEED defines the clock frequency when not in high speed mode. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * None. + * return Frquency[Hz] + */ +static uint32_t emmc_calc_tran_speed(uint32_t* freq) +{ + const uint32_t unit[8U] = {10000U, 100000U, 1000000U, 10000000U, 0U, 0U, 0U, 0U}; /**< frequency unit (1/10) */ + const uint32_t mult[16U] = {0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, 35U, 40U, 45U, 52U, 55U, 60U, 70U, 80U}; /**< multiple factor (x10) */ + uint32_t maxFreq = 0U; + uint32_t result = 0U; + uint32_t tran_speed = EMMC_CSD_TRAN_SPEED(); + + /* tran_speed = 0x32 + * unit[tran_speed&0x7] = uint[0x2] = 1000000 + * mult[(tran_speed&0x78)>>3] = mult[0x30>>3] = mult[6] = 26 + * 1000000 * 26 = 26000000 (26MHz) + */ + + maxFreq = unit[tran_speed & EMMC_TRANSPEED_FREQ_UNIT_MASK] + * mult[(tran_speed & EMMC_TRANSPEED_MULT_MASK) >> EMMC_TRANSPEED_MULT_SHIFT]; + + if (maxFreq == 0U) { + result = 0U; + } else if ( MMC_FREQ_52MHZ <= maxFreq) { + *freq = MMC_52MHZ; + result = 1U; + } else if ( MMC_FREQ_26MHZ <= maxFreq) { + *freq = MMC_26MHZ; + result = 1U; + } else if ( MMC_FREQ_20MHZ <= maxFreq) { + *freq = MMC_20MHZ; + result = 1U; + } else { + *freq = MMC_400KHZ; + result = 1U; + } + + return result; +} + +/** Calculate read/write timeout. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * set mmc clock. + * + * param[in] freq Base clock Div + * return SD_OPTION Timeout Counter + */ +static uint32_t emmc_set_timeout_register_value(uint32_t freq) +{ + uint32_t timeoutCnt = 0U; /* SD_OPTION - Timeout Counter */ + + switch (freq) { + case 1U:/* SDCLK * 2^27 */ + timeoutCnt = 0xE0U; + break; + case 2U:/* SDCLK * 2^27 */ + timeoutCnt = 0xE0U; + break; + case 4U:/* SDCLK * 2^26 */ + timeoutCnt = 0xD0U; + break; + case 8U:/* SDCLK * 2^25 */ + timeoutCnt = 0xC0U; + break; + case 16U:/* SDCLK * 2^24 */ + timeoutCnt = 0xB0U; + break; + case 32U:/* SDCLK * 2^23 */ + timeoutCnt = 0xA0U; + break; + case 64U:/* SDCLK * 2^22 */ + timeoutCnt = 0x90U; + break; + case 128U:/* SDCLK * 2^21 */ + timeoutCnt = 0x80U; + break; + case 256U:/* SDCLK * 2^20 */ + timeoutCnt = 0x70U; + break; + case 512U:/* SDCLK * 2^19 */ + timeoutCnt = 0x60U; + break; + default: + /* nop */ + break; + } + + return timeoutCnt; +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_multiboot.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_multiboot.c new file mode 100644 index 0000000..4f01c82 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_multiboot.c @@ -0,0 +1,95 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC multi boot + ******************************************************************************/ +/****************************************************************************** + * @file emmc_multiboot.c + * - Version : 0.04 + * @brief data access interface to emmc. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.02.2022 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Modify SDHI access from DMA to PIO. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_def.h" +#include "emmc_multiboot.h" +#include "rom_api.h" +#include "types.h" + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +uint32_t emmc_check_result(uint32_t result); + +/* ********************************* CODE ********************************** */ + + +#if defined(__RH850__) +uint32_t emmc_trans_data(uint32_t next_bootPartition, uintptr_t sourceSct, uintptr_t targetAd, uint32_t sectorSize) +{ + EMMC_ERROR_CODE result; + uint32_t rtn_val = EMMC_DEV_ERR; + + /* Partition select */ + result = emmc_select_partition((EMMC_PARTITION_ID)next_bootPartition); + + if (result == EMMC_SUCCESS) { + result = emmc_read_sector((uint32_t *)targetAd, sourceSct, sectorSize, LOADIMAGE_FLAGS_DMA_ENABLE); + } + + /* EMMC_ERROR_CODE -> ROM_XX */ + rtn_val = emmc_check_result((uint32_t)result); + + return rtn_val; +} +#endif /* #if defined(__RH850__) */ +uint32_t emmc_check_result(uint32_t result) +{ + uint32_t ret = EMMC_DEV_ERR_FAULT_INJECTION; + + if (result == EMMC_SUCCESS) { + ret = EMMC_DEV_OK; + } else if (result == EMMC_ERR) { + ret = EMMC_DEV_ERR; + } else { /* other */ + ret = EMMC_DEV_ERR_HW; + } + + return ret; +} +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_read.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_read.c new file mode 100644 index 0000000..0145bd7 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_read.c @@ -0,0 +1,204 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC Read data access driver + ******************************************************************************/ +/****************************************************************************** + * @file emmc_read.c + * - Version : 0.04 + * @brief read data access function to emmc. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.02.2022 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Modify SDHI access from DMA to PIO. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "log.h" +#include + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +#define EMMC_RW_SECTOR_COUNT_MAX 0x0000ffffUL + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +static EMMC_ERROR_CODE emmc_multiple_block_read (uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode); + +static inline uint32_t get_min_value(uint32_t a, uint32_t b) +{ + uint32_t ret = a; + + if(b < a) + { + ret = b; + } + + return ret; +} + +/* ********************************* CODE ********************************** */ + +/** function of read sector + * + * This function always use block read. + * Single block read is not used. + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * . + * + * param[in,out] buff_address_virtual virtual address of read data buffer. + * param[in] sector_number data address for MMC device (sector number). + * param[in] count number of sector. + * param[in] transfermode Mode of data transfer, DMA or not DMA. + */ +EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, + uint32_t feature_flags) +{ + uint32_t trans_count; + uint32_t remain; + EMMC_ERROR_CODE result = EMMC_ERR; + HAL_MEMCARD_DATA_TRANSFER_MODE transfermode; + + /* parameter check */ + if (count == 0U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.mount != TRUE) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* DMA? */ + if ((feature_flags & LOADIMAGE_FLAGS_DMA_ENABLE) != 0U) { + transfermode = HAL_MEMCARD_DMA; + } else { + transfermode = HAL_MEMCARD_NOT_DMA; + } + + remain = count; + while (remain != 0U) { + trans_count = get_min_value(remain, EMMC_RW_SECTOR_COUNT_MAX); + result = emmc_multiple_block_read(buff_address_virtual, sector_number, trans_count, transfermode); + if (result != EMMC_SUCCESS) { + return result; + } + + buff_address_virtual += (EMMC_BLOCK_LENGTH_DW * trans_count); + sector_number += trans_count; + remain -= trans_count; + wdt_restart(); + } + + return EMMC_SUCCESS; +} + +/** multiple block read + * + * Multiple block read with pre-defined block count. + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * . + * + * param[in,out] buff_address_virtual virtual address of read data buffer. + * param[in] sector_number data address for MMC device (sector number). + * param[in] count number of sector. (0x1 - 0xffff) + * param[in] transfer_mode Mode of data transfer, DMA or not DMA. + */ +static EMMC_ERROR_CODE emmc_multiple_block_read(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* parameter check */ + if ((count > EMMC_RW_SECTOR_COUNT_MAX) || (count == 0U) + || ((transfer_mode != HAL_MEMCARD_DMA) && (transfer_mode != HAL_MEMCARD_NOT_DMA))) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* CMD23 */ + emmc_make_nontrans_cmd(CMD23_SET_BLOCK_COUNT, count); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + mem_write32(SD_SECCNT, count); + mem_write32(SD_STOP, 0x00000100U); + mem_write32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE)); /* SD_BUF Read/Write DMA Transfer enable */ + + /* CMD18 */ + emmc_make_trans_cmd(CMD18_READ_MULTIPLE_BLOCK, sector_number, buff_address_virtual, count << EMMC_SECTOR_SIZE_SHIFT, + HAL_MEMCARD_READ, transfer_mode); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; /* CMD18 error code */ + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + + /* ready status check */ + if ((mmc_drv_obj.r1_card_status & EMMC_R1_READY) == 0U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR_CARD_BUSY; + } + + /* state check */ + if (mmc_drv_obj.current_state != EMMC_R1_STATE_TRAN) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_CARD_STATE); + return EMMC_ERR_CARD_STATE; + } + + return EMMC_SUCCESS; +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_utility.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_utility.c new file mode 100644 index 0000000..11a66fe --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/emmc/emmc_utility.c @@ -0,0 +1,301 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC Utility + ******************************************************************************/ +/****************************************************************************** + * @file emmc_utility.c + * - Version : 0.04 + * @brief Analysis of SDHI data. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.02.2022 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Modify SDHI access from DMA to PIO. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +#define BUSY_SIGNAL (1U << 10U) + +static const uint32_t cmd_reg_hw[EMMC_CMD_MAX + 1U] = { + 0x00000000U, /* CMD0 */ + 0x00000701U, /* CMD1 */ + 0x00000002U, /* CMD2 */ + 0x00000003U, /* CMD3 */ + 0x00000004U, /* CMD4 */ + 0x00000505U, /* CMD5 */ + 0x00000406U, /* CMD6 */ + 0x00000007U, /* CMD7 */ + 0x00001C08U, /* CMD8 */ + 0x00000009U, /* CMD9 */ + 0x0000000AU, /* CMD10 */ + 0x00000000U, /* reserved */ + 0x0000000CU, /* CMD12 */ + 0x0000000DU, /* CMD13 */ + 0x00001C0EU, /* CMD14 */ + 0x0000000FU, /* CMD15 */ + 0x00000010U, /* CMD16 */ + 0x00000011U, /* CMD17 */ + 0x00007C12U, /* CMD18 */ + 0x00000C13U, /* CMD19 */ + 0x00000000U, + 0x00001C15U, /* CMD21 */ + 0x00000000U, + 0x00000017U, /* CMD23 */ + 0x00000018U, /* CMD24 */ + 0x00006C19U, /* CMD25 */ + 0x00000C1AU, /* CMD26 */ + 0x0000001BU, /* CMD27 */ + 0x0000001CU, /* CMD28 */ + 0x0000001DU, /* CMD29 */ + 0x0000001EU, /* CMD30 */ + 0x00001C1FU, /* CMD31 */ + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000423U, /* CMD35 */ + 0x00000424U, /* CMD36 */ + 0x00000000U, + 0x00000026U, /* CMD38 */ + 0x00000427U, /* CMD39 */ + 0x00000428U, /* CMD40 : send cmd */ + 0x00000000U, + 0x0000002AU, /* CMD42 */ + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000C31U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00007C35U, + 0x00006C36U, + 0x00000037U, /* CMD55 */ + 0x00000038U, /* CMD56 : Read */ + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U +}; +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +/** make non-transfer command data + * + * Response data buffer is automatically selected. + * + * - Pre-conditions:
+ * Clock to memory card IF is enabled. + * + * - Post-conditions:
+ * After this function is called, command can be executed. + * + * param[in] cmd command information. + * param[in] arg command argument + * return None. + */ +void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg) +{ + /* command information */ + mmc_drv_obj.cmd_info.cmd = cmd; + mmc_drv_obj.cmd_info.arg = arg; + mmc_drv_obj.cmd_info.dir = HAL_MEMCARD_READ; + mmc_drv_obj.cmd_info.hw = cmd_reg_hw[(uint32_t)cmd & HAL_MEMCARD_COMMAND_INDEX_MASK]; + + /* clear data transfer information */ + mmc_drv_obj.trans_size = 0U; + mmc_drv_obj.remain_size = 0U; + mmc_drv_obj.buff_address_virtual = NULL; + mmc_drv_obj.buff_address_physical = NULL; + + /* response information */ + mmc_drv_obj.response_length = 6U; + + switch ((HAL_MEMCARD_RESPONSE_TYPE)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK)) { + case HAL_MEMCARD_RESPONSE_NONE: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + mmc_drv_obj.response_length = 0U; + break; + case HAL_MEMCARD_RESPONSE_R1: + mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; + break; + case HAL_MEMCARD_RESPONSE_R1b: + mmc_drv_obj.cmd_info.hw |= BUSY_SIGNAL; /* bit10 = R1 busy bit */ + mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; + break; + case HAL_MEMCARD_RESPONSE_R2: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + mmc_drv_obj.response_length = 17U; + break; + case HAL_MEMCARD_RESPONSE_R3: + mmc_drv_obj.response = &mmc_drv_obj.r3_ocr; + break; + case HAL_MEMCARD_RESPONSE_R4: + mmc_drv_obj.response = &mmc_drv_obj.r4_resp; + break; + case HAL_MEMCARD_RESPONSE_R5: + mmc_drv_obj.response = &mmc_drv_obj.r5_resp; + break; + default: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + break; + } +} + +/** Making command information for data transfer command. + * + * - Pre-conditions:
+ * None. + * + * - Post-conditions:
+ * After this function is called, command can be executed. + * + * param[in] cmd command + * param[in] arg command argument + * param[in] buff_address_virtual Pointer to buffer where data is/will be stored. (virtual address) + * Client is responsible of allocation and deallocation of the buffer. + * param[in] len transfer length in bytes + * param[in] dir direction + * param[in] transfer_mode Mode of data transfer, DMA or not DMA. + * return None. + */ +void emmc_make_trans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual, /* virtual address */ +uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode) +{ + emmc_make_nontrans_cmd(cmd, arg); /* update common information */ + + /* for data transfer command */ + mmc_drv_obj.cmd_info.dir = dir; + mmc_drv_obj.buff_address_virtual = buff_address_virtual; + mmc_drv_obj.buff_address_physical = buff_address_virtual; + mmc_drv_obj.trans_size = len; + mmc_drv_obj.remain_size = len; + mmc_drv_obj.transfer_mode = transfer_mode; +} + +/** Send idle command. + * Function execute CMD0. + * + * - Pre-conditions:
+ * Clock to MMC I/F enabled. + * + * - Post-conditions:
+ * Card reset to idle or pre-idle state. + * + * param[in] arg CMD0 argument. + * return error code + */ +EMMC_ERROR_CODE emmc_send_idle_cmd(uint32_t arg) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t freq; + + /* initialize state */ + mmc_drv_obj.mount = FALSE; + mmc_drv_obj.selected = FALSE; + mmc_drv_obj.during_transfer = FALSE; + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.dma_error_flag = FALSE; + mmc_drv_obj.force_terminate = FALSE; + mmc_drv_obj.state_machine_blocking = FALSE; + + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; + mmc_drv_obj.max_freq = MMC_20MHZ; /* 20MHz */ + mmc_drv_obj.current_state = EMMC_R1_STATE_IDLE; + + /* CMD0 (MMC clock is current frequency. if Data transfer mode, 20MHz or higher.) */ + emmc_make_nontrans_cmd(CMD0_GO_IDLE_STATE, arg); /* CMD0 */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + + /* change MMC clock(400KHz) */ + freq = MMC_400KHZ; + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) { + return result; + } + + return EMMC_SUCCESS; +} + +/** get bit field data for 16bytes data(CSD register). + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param[in] data 16bytes data. + * param[in] top bit number(top). 128>top + * param[in] bottom bit number(bottom). (0<=bottom<=top) + * return bit field. + */ +uint32_t emmc_bit_field(const uint8_t *data, uint32_t top, uint32_t bottom) +{ + uint32_t value; + + uint32_t index_top = (uint32_t)(15U - (top >> 3U)); + uint32_t index_bottom = (uint32_t)(15U - (bottom >> 3U)); + + if (index_top == index_bottom) { + value = data[index_top]; + } else if ((index_top + 1U) == index_bottom) { + value = (uint32_t)(((uint32_t)data[index_top] << 8U) | data[index_bottom]); + } else if ((index_top + 2U) == index_bottom) { + value = (uint32_t)( + ((uint32_t)data[index_top] << 16U) | ((uint32_t)data[index_top + 1U] << 8U) | data[index_top + 2U]); + } else { + value = (uint32_t)( + ((uint32_t)data[index_top] << 24U) | ((uint32_t)data[index_top + 1U] << 16U) + | ((uint32_t)data[index_top + 2U] << 8U) | data[index_top + 3U]); + } + + value = ((value >> (bottom & 0x07U)) & ((1U << ((top - bottom) + 1U)) - 1U)); + + return value; +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/fcpr/fcpr.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/fcpr/fcpr.c new file mode 100644 index 0000000..8c96010 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/fcpr/fcpr.c @@ -0,0 +1,79 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : FCPR initialize + ******************************************************************************/ + /****************************************************************************** + * @file fcpr.c + * - Version : 0.04 + * @brief Initial setting process of FCPR. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.10.2022 0.01 First Release + * : 22.11.2022 0.02 Defenition Remap address + * : 14.06.2023 0.03 Update the setting process for FCPR. + * : 21.08.2023 0.04 Add support for V4M. + *****************************************************************************/ + +#include +#include +#include +#include +#include + +#define CPG_MSTPCR_FCPR (((uint32_t)1U) << 17U) + +void fcpr_init(void) +{ + /* Register FPCR base address to SIC REMAP14 for V4M. */ + /* There are no problems for V4H because same value had set for V4H in BootROM. */ + set_sicremap_fcpr(); + +#if (SET_FCPR_PARAM == FCPR_ENABLE) + uint32_t reg; + + /* Enables supply of the clock signal */ + reg = mem_read32(CPG_MSTPCR28D0); + /* If supply of clock to FCPR is stopped */ + if (FALSE != (CPG_MSTPCR_FCPR & reg)) + { + /* Supply of clock to FCPR is start */ + reg &= ~(CPG_MSTPCR_FCPR); + mem_write32(CPG_MSTPCR28D0, reg); + } + + /* Set value to FCPR_CMP_CTRL */ + mem_write32(FCPR_CMP_CTRL, COMPRESSION_ENABLE); + /* Set value to FCPR_CMP_SPACE */ + mem_write32(FCPR_CMP_SPACE, 0x00000000U); + /* Set value to FCPR_CMP_STADR */ + mem_write32(FCPR_CMP_STADR, COMPRESSION_START_ADDR); + /* Set value to FCPR_CMP_EDADR */ + mem_write32(FCPR_CMP_EDADR, COMPRESSION_END_ADDR); + +#endif /* SET_FCPR_PARAM == FCPR_ENABLE */ +} +/* End of function fcpr_init(void) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/gpio/gpio.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/gpio/gpio.c new file mode 100644 index 0000000..e358b3c --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/gpio/gpio.c @@ -0,0 +1,102 @@ +/******************************************************************************* + * DESCRIPTION : GPIO Control function + ******************************************************************************/ +/****************************************************************************** + * @file gpio.c + * - Version : 0.01 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 18.11.2024 0.01 First Release +*****************************************************************************/ +#if defined(__CX_IPL__) /* V4H_Cx_Loader */ +#include "mem_io.h" +#include "rcar_def.h" +#include "rcar_register.h" +#include "gic.h" +#include "ip_control.h" +#include "timer.h" + +#define GP0_8_BASE (BASE_PFC0_ADDR + 0x0180U) +#define GP1_24_BASE (PFC_GP1_BASE + 0x0180U) +#else /* Gen4_ICUMX_Loader */ +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_BASE (PFC_BASE + PFC_PORT_GRP0) +#define GP0_8_BASE (PFC_BASE + PFC_PORT_GRP0 + 0x0180) +#define GP1_24_BASE (PFC_BASE + PFC_PORT_GRP1 + 0x0180) +#endif + +#define GP1_23_BASE GP1_24_BASE + +#define GPIO_IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ +#define GPIO_INOUTSEL 0x04 /* General Input/Output Switching Register */ +#define GPIO_OUTDT 0x08 /* General Output Register */ +#define GPIO_INDT 0x0c /* General Input Register */ +#define GPIO_INTDT 0x10 /* Interrupt Display Register */ +#define GPIO_INTCLR 0x14 /* Interrupt Clear Register */ +#define GPIO_INTMSK 0x18 /* Interrupt Mask Register */ +#define GPIO_MSKCLR 0x1c /* Interrupt Mask Clear Register */ +#define GPIO_POSNEG 0x20 /* Positive/Negative Logic Select Register */ +#define GPIO_EDGLEVEL 0x24 /* Edge/level Select Register */ +#define GPIO_FILONOFF 0x28 /* Chattering Prevention On/Off Register */ +#define GPIO_BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */ +#define GPIO_INEN 0x50 /* General Input Enable Register */ + +#define BIT(nr) (1 << (nr)) +void gpio_output_clr_set(uintptr_t regs, int offset, int set) +{ + if (set) + mem_bitclrset32(regs + GPIO_OUTDT, 0x0, BIT(offset)); /* set */ + else + mem_bitclrset32(regs + GPIO_OUTDT, BIT(offset), 0x0); /* clear */ + + mem_bitclrset32(regs + GPIO_POSNEG, BIT(offset), 0x0); + mem_bitclrset32(regs + GPIO_INEN, BIT(offset), 0x0); + mem_bitclrset32(regs + GPIO_IOINTSEL, BIT(offset), 0x0); + mem_bitclrset32(regs + GPIO_INOUTSEL, 0x0, BIT(offset)); /* set output */ +} +/* End of function gpio_output_clr_set(uintptr_t regs, int offset, int set) */ + +#if (BOOT_TIME_CHECK != 0) +void gpio_N1307(int set) { + if (set == 2) { + gpio_output_clr_set(GP0_8_BASE, 8, 0); + gpio_output_clr_set(GP0_8_BASE, 8, 1); + micro_wait(10U); + gpio_output_clr_set(GP0_8_BASE, 8, 0); + } else if (set) + gpio_output_clr_set(GP0_8_BASE, 8, 1); + else + gpio_output_clr_set(GP0_8_BASE, 8, 0); +} + +void gpio_N1305(int set) { + if (set == 2) { + gpio_output_clr_set(GP1_24_BASE, 24, 0); + micro_wait(10U); + gpio_output_clr_set(GP1_24_BASE, 24, 1); + micro_wait(10U); + // gpio_output_clr_set(GP1_24_BASE, 24, 0); + } else if (set) + gpio_output_clr_set(GP1_24_BASE, 24, 1); + else + gpio_output_clr_set(GP1_24_BASE, 24, 0); +} +#endif + +void gpio_V4H_SERDES_1V8_en(int set) { + if (set) { + gpio_output_clr_set(GP1_23_BASE, 23, 1); + } else { + gpio_output_clr_set(GP1_23_BASE, 23, 0); + } +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/i2c/i2c.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/i2c/i2c.c new file mode 100644 index 0000000..005642a --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/i2c/i2c.c @@ -0,0 +1,408 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : I2C driver + ******************************************************************************/ +/****************************************************************************** + * @file i2c.c + * - Version : 0.02 + * @brief I2C driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 16.11.2023 0.01 First Release + * : 24.06.2024 0.02 Remove pre-process branch of i2c3_read(). + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Setting value for PFC */ +#define IP0SR4_SDA3 (0xF0000000U) /* bit[31:28] */ +#define IP0SR4_SCL3 (0x0F000000U) /* bit[27:24] */ +#define GPSR4_SDA3 (0x00000080U) /* bit7 */ +#define GPSR4_SCL3 (0x00000040U) /* bit6 */ +#define MODSEL4_SDA3 (0x00000080U) /* bit7 */ +#define MODSEL4_SCL3 (0x00000040U) /* bit6 */ +#define PUEN4_SDA3 (0x00000080U) /* bit7 */ +#define PUEN4_SCL3 (0x00000040U) /* bit6 */ + +static void i2c3_init_pin_function(void); + +void i2c3_init(void) +{ + /* + * Module Standby setting for I2C3 is not nessesary + * because H/W initial value is 'Enables supply of the clock signal'. + */ + + /* PFC setting for I2C3. */ + i2c3_init_pin_function(); + + /* CDFD=0, HLSE=0, SME=0 */ + mem_write32((uintptr_t)I2C3_ICCCR2, 0x00000000U); + /* SCGD=H'3, CDF=H'6 */ + mem_write32((uintptr_t)I2C3_ICCCR, (SET_SCGD | SET_CDF)); + + mem_write32((uintptr_t)I2C3_ICSCR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICSSR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICSIER, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICSAR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE)); + mem_write32((uintptr_t)I2C3_ICMSR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMIER, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMAR, 0x00000000U); +} +/* End of function i2c3_init(void) */ + +static void i2c3_init_pin_function(void) +{ + uint32_t data; + + /* SDA3, SCL3 -> 0 */ + data = mem_read32((uintptr_t)PFC_IP0SR4_RW); + data &= ~(IP0SR4_SDA3 | IP0SR4_SCL3); + pfc_reg_write(PFC_IP0SR4_RW, data); + + /* SDA3, SCL3 -> 1 */ + data = mem_read32((uintptr_t)PFC_GPSR4_RW); + data |= (GPSR4_SDA3 | GPSR4_SCL3); + pfc_reg_write(PFC_GPSR4_RW, data); + + /* Select SDA3 and SCL3 to I2C mode */ + data = mem_read32((uintptr_t)PFC_MODSEL4_RW); + data |= (MODSEL4_SDA3 | MODSEL4_SCL3); + pfc_reg_write(PFC_MODSEL4_RW, data); + + /* SDA3, SCL3 -> 0 */ + data = mem_read32((uintptr_t)PFC_PUEN4_RW); + data &= ~(PUEN4_SDA3 | PUEN4_SCL3); + pfc_reg_write(PFC_PUEN4_RW, data); +} +/* End of function i2c3_init_pin_function(void) */ + +void i2c3_write(uint32_t slaveAdd, uint32_t regAdd, uint32_t setData) +{ + uint32_t data; + uint32_t err_count = 0U; + uint32_t status; + + while(true) + { + data = mem_read32((uintptr_t)I2C3_ICMCR); + data &= (FLAG_FSCL | FLAG_FSDA); + if(data == FLAG_FSCL) + { + break; + } + } + + status = I2C_NG; + while(I2C_NG == status) + { + /* Set MDBS and MIE (initialize) */ + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE)); + /* Set slave address */ + slaveAdd &= ~FLG_RW; /* write mode */ + mem_write32((uintptr_t)I2C3_ICMAR, slaveAdd); + /* Set register address */ + mem_write32((uintptr_t)I2C3_ICTXD, regAdd); + + while(true) + { + data = mem_read32((uintptr_t)I2C3_ICMCR); + data &= (FLAG_FSCL | FLAG_FSDA); + if(data == FLAG_FSCL) + { + break; + } + } + + /* Set MDBS, MIE and ESG */ + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_ESG)); /* start condition */ + + /* MDE(master data empty) & MAT(master address transmitted */ + status = i2c3_err_check(FLAG_MDE, FLAG_MAT, (FLAG_MNR|FLAG_MAL)); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("1:I2C data write error\n"); + panic; + } + } + } + + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE)); + + status = I2C_NG; + while(I2C_NG == status) + { + /* MDE and MAT clear */ + data = mem_read32((uintptr_t)I2C3_ICMSR); + data &= (FLAG_MNR | FLAG_MAL | FLAG_MST | FLAG_MDT | FLAG_MDR); + mem_write32((uintptr_t)I2C3_ICMSR, data); + /* MDE(master data empty) & MDT(master data transmitted) */ + status = i2c3_err_check(FLAG_MDE, FLAG_MDT, FLAG_MNR); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("2:I2C data write error\n"); + panic; + } + } + } + + status = I2C_NG; + while(I2C_NG == status) + { + /* send voltage */ + mem_write32((uintptr_t)I2C3_ICTXD, setData); + /* MDE and MAT clear */ + data = mem_read32((uintptr_t)I2C3_ICMSR); + data &= (FLAG_MNR | FLAG_MAL | FLAG_MST | FLAG_MDR | FLAG_MAT); + mem_write32((uintptr_t)I2C3_ICMSR, data); + /* MDE(master data empty) & MDT(master data transmitted) */ + status = i2c3_err_check(FLAG_MDE, FLAG_MDT, FLAG_MNR); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("3:I2C data write error\n"); + panic; + } + } + } + + /* Set MDBS, MIE and FSB */ + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_FSB)); /* stop condition */ + mem_write32((uintptr_t)I2C3_ICMSR, 0x00000000U); /* MST(master stop transmitted) clear */ + + while(true) + { + data = mem_read32((uintptr_t)I2C3_ICMSR); + if((data & FLAG_MST) != 0U) /* MST(master stop transmitted) */ + { + break; + } + } + + mem_write32((uintptr_t)I2C3_ICMSR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE)); + +} +/* End of function i2c3_write(uint32_t slaveAdd, uint32_t regAdd, uint32_t setData) */ + +void i2c3_read(uint32_t slaveAdd, uint32_t regAdd, uint32_t *revData) +{ + uint32_t data; + uint32_t err_count = 0; + uint32_t status; + + while(true) + { + data = mem_read32((uintptr_t)I2C3_ICMCR); + data &= (FLAG_FSCL | FLAG_FSDA); + if(data == FLAG_FSCL) + { + break; + } + } + + status = I2C_NG; + while(I2C_NG == status) + { + /* Set MDBS and MIE (initialize) */ + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE)); + /* Set slave address */ + slaveAdd &= ~FLG_RW; /* write mode */ + mem_write32((uintptr_t)I2C3_ICMAR, slaveAdd); + /* Set register address */ + mem_write32((uintptr_t)I2C3_ICTXD, regAdd); + + while(true) + { + data = mem_read32((uintptr_t)I2C3_ICMCR); + data &= (FLAG_FSCL | FLAG_FSDA); + if(data == FLAG_FSCL) + { + break; + } + } + + /* Set MDBS, MIE and ESG */ + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_ESG)); /* start condition */ + + /* MDE(master data empty) & MAT(master address transmitted */ + status = i2c3_err_check(FLAG_MDE, FLAG_MAT, (FLAG_MNR|FLAG_MAL)); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("1:I2C data read error\n"); + panic; + } + } + } + + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE)); + + status = I2C_NG; + while(I2C_NG == status) + { + /* MDE and MAT clear */ + data = mem_read32((uintptr_t)I2C3_ICMSR); + data &= 0x000000F6U; + mem_write32((uintptr_t)I2C3_ICMSR, data); + /* MDE(master data empty) */ + status = i2c3_err_check(FLAG_MDE, FLAG_NONE, FLAG_MNR); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("2:I2C data read error\n"); + panic; + } + } + } + + status = I2C_NG; + while(I2C_NG == status) + { + /* Set slave address */ + slaveAdd |= FLG_RW; /* read mode */ + mem_write32((uintptr_t)I2C3_ICMAR, slaveAdd); + /* Set MDBS, MIE and ESG */ + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_ESG)); /* start condition */ + mem_write32((uintptr_t)I2C3_ICMSR, 0x00000000U); + + /* MDR(master data recieved) & MAT(master address transmitted) */ + status = i2c3_err_check(FLAG_MDR, FLAG_MAT, (FLAG_MNR|FLAG_MAL)); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("3:I2C data read error\n"); + panic; + } + } + } + + status = I2C_NG; + while(I2C_NG == status) + { + /* Set MDBS, MIE and FSB */ + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_FSB)); /* stop condition */ + /* MDE and MAT clear */ + data = mem_read32((uintptr_t)I2C3_ICMSR); + data &= 0x000000FCU; + mem_write32((uintptr_t)I2C3_ICMSR, data); + status = i2c3_err_check(FLAG_MDR, FLAG_NONE, FLAG_MNR); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("4:I2C data read error\n"); + panic; + } + } + if(I2C_OK == status) + { + *revData = mem_read32((uintptr_t)I2C3_ICRXD) & 0x000000FFU; + } + mem_write32((uintptr_t)I2C3_ICMSR, 0x00000000U); /* MST(master stop transmitted) clear */ + } + + while(true) + { + data = mem_read32((uintptr_t)I2C3_ICMSR); + if((data & FLAG_MST) != 0U) + { + break; + } + } + + mem_write32((uintptr_t)I2C3_ICMSR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE)); +} +/* End of function i2c3_read(uint32_t slaveAdd, uint32_t regAdd, uint32_t *revData) */ + +uint32_t i2c3_err_check(uint32_t first, uint32_t second, uint32_t error) +{ + uint32_t data; + uint32_t status = I2C_OK; + + while(true) + { + data = mem_read32((uintptr_t)I2C3_ICMSR); + if((data & first) != 0U) + { + if((second == FLAG_NONE) || ((data & second) != 0U)) + { + status = I2C_OK; + break; + } + } + if((data & error) != 0U) + { + mem_write32((uintptr_t)I2C3_ICMSR, ~error); + status = I2C_NG; + break; + } + } + return status; +} +/* End of function i2c3_err_check(uint32_t first, uint32_t second, uint32_t error) */ + +void i2c3_release(void) +{ + mem_write32((uintptr_t)I2C3_ICCCR2, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICCCR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICSCR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICSSR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICSIER, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICSAR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMCR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMSR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMIER, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMAR, 0x00000000U); +} +/* End of function i2c3_release(void) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/i2c/i2c5.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/i2c/i2c5.c new file mode 100644 index 0000000..ca56fde --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/i2c/i2c5.c @@ -0,0 +1,468 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : I2C driver + ******************************************************************************/ +/****************************************************************************** + * @file i2c.c + * - Version : 0.02 + * @brief I2C driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 16.11.2023 0.01 First Release + * : 24.06.2024 0.02 Remove pre-process branch of i2c5_read(). + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Setting value for PFC */ +#define IP1SR8_SDA5_MASK (0x0000F000U) /* bit[15:12] */ +#define IP1SR8_SCL5_MASK (0x00000F00U) /* bit[11:8] */ +#define IP1SR8_SDA5 (0x00000000U) /* bit[15:12] */ +#define IP1SR8_SCL5 (0x00000000U) /* bit[11:8] */ +#define GPSR8_SDA5 (0x00000800U) /* bit11 */ +#define GPSR8_SCL5 (0x00000400U) /* bit10 */ +#define MODSEL8_SDA5 (0x00000800U) /* bit11 */ +#define MODSEL8_SCL5 (0x00000400U) /* bit10 */ +#define PUEN8_SDA5 (0x00000800U) /* bit11 */ +#define PUEN8_SCL5 (0x00000400U) /* bit10 */ + +#define CPG_MSTPCR_I2C5 (((uint32_t)1U) << 23U) + +static void i2c5_init_pin_function(void); + +void i2c5_init(void) +{ + uint32_t reg; + + /* + * Module Standby setting for I2C5 + */ + reg = mem_read32(CPG_MSTPSR5D0); + /* If supply of clock to I2C5 is stopped */ + if (FALSE != (CPG_MSTPCR_I2C5 & reg)) + { + /* Supply of clock to I2C5 is start */ + reg &= ~(CPG_MSTPCR_I2C5); + cpg_reg_write(CPG_MSTPCR5D0, CPG_MSTPSR5D0, reg); + } + + /* PFC setting for I2C5. */ + i2c5_init_pin_function(); + + /* clock init */ + /* CDFD=1, HLSE=1, SME=1, FMPE=1 */ + mem_write32((uintptr_t)I2C5_ICCCR2, 0x7U | (1 << 7)); + //Clock to filter glitches = 133.3/(1 + 6) = 19Mhz + mem_write32((uintptr_t)I2C5_ICCCR, 0x6); + mem_write32((uintptr_t)I2C5_ICMPR, 21); + mem_write32((uintptr_t)I2C5_ICHPR, 133); + mem_write32((uintptr_t)I2C5_ICLPR, 150); + /* 1st bit setup cycle */ + mem_write32((uintptr_t)I2C5_ICFBSCR, 0x07); + + /* reset slave interface */ + mem_write32((uintptr_t)I2C5_ICSIER, 0U); + mem_write32((uintptr_t)I2C5_ICSCR, FLAG_SDBS); + mem_write32((uintptr_t)I2C5_ICSAR, 0U); + mem_write32((uintptr_t)I2C5_ICSSR, 0U); + + /* reset master interface */ + mem_write32((uintptr_t)I2C5_ICMIER, 0U); + mem_write32((uintptr_t)I2C5_ICMCR, FLAG_MDBS); + mem_write32((uintptr_t)I2C5_ICMAR, 0U); + mem_write32((uintptr_t)I2C5_ICMSR, 0U); +} +/* End of function i2c5_init(void) */ + +static void i2c5_init_pin_function(void) +{ + uint32_t data; + + /* SDA5(GP8_11), SCL5(GP8_10) -> 0 */ + data = mem_read32((uintptr_t)PFC_IP1SR8_RW); + data &= ~(IP1SR8_SDA5_MASK | IP1SR8_SCL5_MASK); + // data |= (IP1SR8_SDA5 | IP1SR8_SCL5); /* useless */ + pfc_reg_write(PFC_IP1SR8_RW, data); + + /* SDA5, SCL5 -> 1 */ + data = mem_read32((uintptr_t)PFC_GPSR8_RW); + data |= (GPSR8_SDA5 | GPSR8_SCL5); + pfc_reg_write(PFC_GPSR8_RW, data); + + /* Select SDA5 and SCL5 to I2C mode */ + data = mem_read32((uintptr_t)PFC_MODSEL8_RW); + data |= (MODSEL8_SDA5 | MODSEL8_SCL5); + pfc_reg_write(PFC_MODSEL8_RW, data); + + /* SDA5, SCL5 -> 0 */ + data = mem_read32((uintptr_t)PFC_PUEN8_RW); + data &= ~(PUEN8_SDA5 | PUEN8_SCL5); + pfc_reg_write(PFC_PUEN8_RW, data); +} +/* End of function i2c5_init_pin_function(void) */ + +static void i2c5_set_address_reg(uint32_t slaveAdd, uint32_t regAdd) +{ + uint32_t data; + uint32_t err_count = 0U; + uint32_t status; + + while(true) + { + data = mem_read32((uintptr_t)I2C5_ICMCR); + data &= (FLAG_FSCL | FLAG_FSDA); + if(data == FLAG_FSCL) + { + break; + } + } + + /* 107.3.10.1. Master Transmitter + (b) set value for the master control registers, first data byte, and address */ + status = I2C_NG; + while(I2C_NG == status) + { + /* Clear all ICMSR */ + mem_write32((uintptr_t)I2C5_ICMSR, 0U); + /* Set slave address */ + slaveAdd &= ~FLG_RW; /* write mode */ + mem_write32((uintptr_t)I2C5_ICMAR, slaveAdd); + /* Set register address */ + mem_write32((uintptr_t)I2C5_ICTXD, regAdd); + + while(true) + { + data = mem_read32((uintptr_t)I2C5_ICMCR); + data &= (FLAG_FSCL | FLAG_FSDA); + if(data == FLAG_FSCL) + { + break; + } + } + + /* 5. set the Master Control register (ICMCR) = H'89 */ + /* Set MDBS, MIE and ESG */ + mem_write32((uintptr_t)I2C5_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_ESG)); /* start condition */ + + /* (c) waiting for outputting address + 1. wait for master event (ICMSR.MAT and ICMSR.MDE) */ + /* MDE(master data empty) & MAT(master address transmitted) */ + status = i2c5_err_check(FLAG_MDE, FLAG_MAT, (FLAG_MNR|FLAG_MAL)); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("1:I2C data write error\n"); + panic; + } + } + } +} + +static void __i2c5_write(uint32_t slaveAdd, uint32_t regAdd, uint32_t setData) +{ + uint32_t data; + uint32_t err_count = 0U; + uint32_t status; + + /* 107.3.10.1. Master Transmitter */ + i2c5_set_address_reg(slaveAdd, regAdd); + + /* 2. set ICMCR to H'88 */ + mem_write32((uintptr_t)I2C5_ICMCR, (FLAG_MDBS | FLAG_MIE)); + + status = I2C_NG; + while(I2C_NG == status) + { + /* 3. Clear the ICMSR.MAT and ICMSR.MDE bits. */ + data = mem_read32((uintptr_t)I2C5_ICMSR); + data &= __INV(FLAG_MAT | FLAG_MDE); + mem_write32((uintptr_t)I2C5_ICMSR, data); + + /* (d). Monitoring transmission of data + 1. wait for master event ICMSR.MDE(master data empty) */ + status = i2c5_err_check(FLAG_MDE, FLAG_NONE, FLAG_MNR); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("2:I2C data write error\n"); + panic; + } + } + } + + /* 2. ICTXD = data */ + mem_write32((uintptr_t)I2C5_ICTXD, setData); + + /* 3. clear the ICMSR.MDE bit + Clear ICMSR.MDE after setting the last byte to be transmitted. + After the last byte data is loaded into the shift register, + ICMSR.MDE is generated. Before clearning ICMSR.MDE, you must + set ICMCR to H'8A (set the force stop control bit). */ + status = I2C_NG; + while(I2C_NG == status) + { + data = mem_read32((uintptr_t)I2C5_ICMSR); + data &= __INV(FLAG_MDE); + mem_write32((uintptr_t)I2C5_ICMSR, data); + + status = i2c5_err_check(FLAG_MDE, FLAG_NONE, FLAG_MNR); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("3:I2C data write error\n"); + panic; + } + } + } + + /* Before clearning ICMSR.MDE, you must + set ICMCR to H'8A (set the force stop control bit). */ + mem_write32((uintptr_t)I2C5_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_FSB)); + + status = I2C_NG; + while(I2C_NG == status) + { + data = mem_read32((uintptr_t)I2C5_ICMSR); + data &= __INV(FLAG_MDE); + mem_write32((uintptr_t)I2C5_ICMSR, data); + + /* (e) wait for end of transmission + 1. wait for the master event, ICMSR.MST */ + status = i2c5_err_check(FLAG_MST, FLAG_NONE, FLAG_MNR); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("3:I2C data write error\n"); + panic; + } + } + } + + /* 2. clear the ICMSR.MST bit */ + data = mem_read32((uintptr_t)I2C5_ICMSR); + data &= __INV(FLAG_MST); + mem_write32((uintptr_t)I2C5_ICMSR, data); +} +/* End of function i2c5_write(uint32_t slaveAdd, uint32_t regAdd, uint32_t setData) */ + +static void __i2c5_read(uint32_t slaveAdd, uint32_t regAdd, uint32_t *revData) +{ + uint32_t data; + uint32_t err_count = 0; + uint32_t status; + + /* 107.3.10.3. Master Transmitter - repeated START - Master receiver */ + i2c5_set_address_reg(slaveAdd, regAdd); + + status = I2C_NG; + while(I2C_NG == status) + { + /* 2. set ICMAR to address of slave ... (read mode: 1) */ + /* Set slave address */ + slaveAdd |= FLG_RW; /* read mode */ + mem_write32((uintptr_t)I2C5_ICMAR, slaveAdd); + /* Set MDBS, MIE and ESG */ + mem_write32((uintptr_t)I2C5_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_ESG)); /* start condition */ + /* 3. Clear the ICMSR.MAT and ICMSR.MDE bits. */ + data = mem_read32((uintptr_t)I2C5_ICMSR); + data &= __INV(FLAG_MAT | FLAG_MDE); + mem_write32((uintptr_t)I2C5_ICMSR, data); + + /* (d). Monitor transmission of data. + 1. wait for master event, ICMSR.MDE */ + /* MDE(master data empty) */ + status = i2c5_err_check(FLAG_MDE, FLAG_NONE, FLAG_MNR); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("2:I2C data read error\n"); + panic; + } + } + } + + status = I2C_NG; + while(I2C_NG == status) + { + /* 2. set ICMCR = H'89 (MDBS = 1, MIE = 1, ESG = 1) */ + mem_write32((uintptr_t)I2C5_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_ESG)); /* start condition */ + + /* 3. clear the MDE bit. */ + data = mem_read32((uintptr_t)I2C5_ICMSR); + data &= __INV(FLAG_MDE); + mem_write32((uintptr_t)I2C5_ICMSR, data); + + /* (e) wait for outputting slave-address of master reception + 1. wait for master event (ICMSR.MAT and ICMSR.MDR bits.) */ + status = i2c5_err_check(FLAG_MDR, FLAG_MAT, (FLAG_MNR|FLAG_MAL)); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("3:I2C data read error\n"); + panic; + } + } + } + + status = I2C_NG; + while(I2C_NG == status) + { + /* 2. set ICMCR to H'88(MDBS, MIE) */ + mem_write32((uintptr_t)I2C5_ICMCR, (FLAG_MDBS | FLAG_MIE)); + /* 3. clear the ICMSR.MAT and ICMSR.MDR bits. */ + data = mem_read32((uintptr_t)I2C5_ICMSR); + data &= __INV(FLAG_MAT | FLAG_MDR); + mem_write32((uintptr_t)I2C5_ICMSR, data); + /* (f) Monitor reception of data + 3. set ICMR.FSB to 1 before the last byte data transfer is started */ + mem_write32((uintptr_t)I2C5_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_FSB)); /* stop condition */ + /* (g) Monitor reception of data + 1. handle the receive interrupt(ICMSR.MDR) in the last byte: + that is, read the data and clear the ICMSR.MDR. */ + status = i2c5_err_check(FLAG_MDR, FLAG_NONE, FLAG_MNR); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("4:I2C data read error\n"); + panic; + } + } + if(I2C_OK == status) + { + *revData = mem_read32((uintptr_t)I2C5_ICRXD) & 0x000000FFU; + } + /* clear ICMSR.MDR */ + data = mem_read32((uintptr_t)I2C5_ICMSR); + data &= __INV(FLAG_MDR); + mem_write32((uintptr_t)I2C5_ICMSR, data); + } + + /* 2. wait for master event, ICMSR.MST */ + while(true) + { + data = mem_read32((uintptr_t)I2C5_ICMSR); + if((data & FLAG_MST) != 0U) + { + break; + } + } + + /* 3. clear the ICMSR.MST(master stop transmitted) bit */ + data = mem_read32((uintptr_t)I2C5_ICMSR); + data &= __INV(FLAG_MST); + mem_write32((uintptr_t)I2C5_ICMSR, data); +} +/* End of function i2c5_read(uint32_t slaveAdd, uint32_t regAdd, uint32_t *revData) */ + +uint32_t i2c5_err_check(uint32_t first, uint32_t second, uint32_t error) +{ + uint32_t data; + uint32_t status = I2C_OK; + + while(true) + { + data = mem_read32((uintptr_t)I2C5_ICMSR); + if((data & first) != 0U) + { + if((second == FLAG_NONE) || ((data & second) != 0U)) + { + status = I2C_OK; + break; + } + } + if((data & error) != 0U) + { + mem_write32((uintptr_t)I2C5_ICMSR, ~error); + status = I2C_NG; + break; + } + } + return status; +} +/* End of function i2c5_err_check(uint32_t first, uint32_t second, uint32_t error) */ + +void i2c5_release(void) +{ + mem_write32((uintptr_t)I2C5_ICCCR2, 0x00000000U); + mem_write32((uintptr_t)I2C5_ICCCR, 0x00000000U); + mem_write32((uintptr_t)I2C5_ICSCR, 0x00000000U); + mem_write32((uintptr_t)I2C5_ICSSR, 0x00000000U); + mem_write32((uintptr_t)I2C5_ICSIER, 0x00000000U); + mem_write32((uintptr_t)I2C5_ICSAR, 0x00000000U); + mem_write32((uintptr_t)I2C5_ICMCR, 0x00000000U); + mem_write32((uintptr_t)I2C5_ICMSR, 0x00000000U); + mem_write32((uintptr_t)I2C5_ICMIER, 0x00000000U); + mem_write32((uintptr_t)I2C5_ICMAR, 0x00000000U); +} +/* End of function i2c5_release(void) */ + +static uint32_t cur_page = 0x00; +static inline void i2c5_page_change(uint32_t slaveAdd, uint32_t new_page) { + if (cur_page != new_page) { + __i2c5_write(slaveAdd, 0x00, new_page); + __i2c5_write(slaveAdd, 0x00, new_page); + __i2c5_read(slaveAdd, 0x00, &cur_page); + if (cur_page != new_page) { + ERROR("I2C5: page change error (0x%x:0x%x)\n", cur_page, new_page); + panic; + } + } +} + +void i2c5_write(uint32_t slaveAdd, uint32_t regAdd, uint32_t revData) { + i2c5_page_change(slaveAdd, (regAdd & 0xFF00) >> 8); + __i2c5_write(slaveAdd, regAdd & 0xFF, revData); +} + +void i2c5_read(uint32_t slaveAdd, uint32_t regAdd, uint32_t *revData) { + i2c5_page_change(slaveAdd, (regAdd & 0xFF00) >> 8); + __i2c5_read(slaveAdd, regAdd & 0xFF, revData); +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ip_control.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ip_control.c new file mode 100644 index 0000000..c47658f --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/ip_control.c @@ -0,0 +1,122 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : IP's control function + ******************************************************************************/ +/****************************************************************************** + * @file ip_control.c + * - Version : 0.08 + * @brief Initial setting controller. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 30.09.2021 0.02 Support of eMMC boot. + * : 15.10.2021 0.03 modify include of flash /eMMC. + * : 03.12.2021 0.04 CA IPL boot support (workaround) + * : 06.01.2022 0.05 Add exception handling for ICUMX_WDTA. + * : 02.02.2022 0.06 Add MFIS Lock/Unlock. + * : 23.05.2022 0.07 Integration of S4 and V4H + * : 23.08.2023 0.08 Add support for V4M. + * : 13.10.2023 0.09 Add calling of sysc_c4_power_on function. + *****************************************************************************/ + +#include +#include +#include +#if (RCAR_SA9_TYPE == FLASH_BOOT) +#include +#include +#include +#elif (RCAR_SA9_TYPE == EMMC_BOOT) +#include +#else +/* no process */ +#endif +#include +#include +#include +#include + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#include +#endif + +#if (RCAR_LSI == RCAR_V4M) +#include +#endif + +void ip_init(void) +{ + scif_init(); + set_vect_table(); + wdt_init(); + cpg_init(); +#if (RCAR_SA9_TYPE == FLASH_BOOT) + dma_init(); + rpc_init(); + mfis_init(); + #if (CA_LOAD_TYPE == CA_IPL) + emmc_initialize(); /* workaround */ + #endif /* (CA_LOAD_TYPE == CA_IPL) */ +#elif (RCAR_SA9_TYPE == EMMC_BOOT) /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + emmc_initialize(); +#else /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + /* No process */ +#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + fcpr_init(); +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +#if (RCAR_LSI == RCAR_V4M) + /* + * For accessing Region ID registers by ICUMX, + * and starting Cortex-A76 by CR52 2nd IPL. + */ + sysc_c4_power_on(); +#endif /* RCAR_LSI == RCAR_V4M */ +#if (SAN_ENABLE == 1) + i2c5_init(); +#endif +} +/* End of function ip_init(void) */ + +void ip_release(void) +{ +#if (SAN_ENABLE == 1) + i2c5_release(); +#endif +#if (RCAR_SA9_TYPE == FLASH_BOOT) + rpc_release(); + dma_release(); +#elif (RCAR_SA9_TYPE == EMMC_BOOT) + emmc_terminate(); +#else + /* No process */ +#endif + wdt_restart(); +} +/* End of function ip_release(void) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/mfis/mfis.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/mfis/mfis.c new file mode 100644 index 0000000..9f133cc --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/mfis/mfis.c @@ -0,0 +1,82 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MFIS driver + ******************************************************************************/ +/****************************************************************************** + * @file mfis.c + * - Version : 0.01 + * @brief Initial setting process of MFIS. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.04.2022 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include + +#define MFIS_CODE_VALID (0xACCE0000U) +#define MFISWPCNTR_ENABLE (0U) /* 1' b0: Enable write protection */ + +#define MFISLCKR_LCK_BIT ((uint32_t)1U << 0U) +#define MFISLCKR_UNLOCK (0U) + +void mfis_init(void) +{ + /* Write Protection Control Register */ + /* Enable write protection setting */ + mem_write32(MFIS_WPCNTR, (uint32_t)(MFIS_CODE_VALID + MFISWPCNTR_ENABLE)); + + /* IPL considers the situation that mutex of MFIS is not released, release it. */ + mfis_unlock(); +} +/* End of function mfis_init(void) */ + +void mfis_lock(void) +{ + /* MFIS Lock Register [j] (MFISLCKR[j]) */ + /* bit in LCK != 0? */ + while((mem_read32(MFIS_LCKR) & MFISLCKR_LCK_BIT) != MFISLCKR_UNLOCK) + { + micro_wait(10U); /* 10us */ + } + /* this bit is automatically set to "1" */ +} +/* End of function mfis_lock(void) */ + +void mfis_unlock(void) +{ + /* Write Access Control Register */ + /* MFISLCKR[j] Register address setting */ + mem_write32(MFIS_WACNTR, (uint32_t)(MFIS_CODE_VALID + MFISLCKR_ADDRESS)); + + /* MFIS Lock Register [j] (MFISLCKR[j]) */ + mem_write32(MFIS_LCKR, (uint32_t)MFISLCKR_UNLOCK); +} +/* End of function mfis_unlock(void) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/qos/qos.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/qos/qos.c new file mode 100644 index 0000000..fd0674d --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/qos/qos.c @@ -0,0 +1,413 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : QoS initialize function + ******************************************************************************/ +/****************************************************************************** + * @file qos.c + * - Version : 0.04 + * @brief Initial setting process of QoS. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 23.05.2022 0.02 Integration of S4 and V4H + * Update QoS setting rev.0.02 (for S4) + * Update QoS setting rev.0.03 (for V4H) + * : 20.01.2023 0.03 Add DBSC W/A 1,2,3 (OTLINT-5579) + * : 21.08.2023 0.04 Add support for V4M. + *****************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include +#include +#include +#else +#include +#endif +#include +#include +#include + +#if (RCAR_LSI == RCAR_S4) +#define RCAR_QOS_VERSION "base_v6.1" +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define RCAR_QOS_VERSION "base_v6.1" +#endif /* RCAR_LSI == RCAR_S4 */ + +#define RCAR_DRAM_SPLIT_DISABLE (0U) +#define RCAR_DRAM_SPLIT_ENABLE (1U) +#define RCAR_REWT_TRAINING_DISABLE (0U) +#define RCAR_REWT_TRAINING_ENABLE (1U) + +#if defined(__RH850G3K__) +#define AXMM_BASE (BASE_AXMM_ADDR) +#else +#define AXMM_BASE (0xE6780000U) +#endif +#define AXMM_MMCR (AXMM_BASE + 0x4300U) +#define AXMM_ADSPLCR0 (AXMM_BASE + 0x4008U) +#define AXMM_ADSPLCR1 (AXMM_BASE + 0x400CU) +#define AXMM_ADSPLCR2 (AXMM_BASE + 0x4010U) +#define AXMM_ADSPLCR3 (AXMM_BASE + 0x4014U) + + +#if (RCAR_LSI == RCAR_S4) +#if defined(__RH850G3K__) +#define DBSC_BASE (BASE_DBSC_ADDR) +#else +#define DBSC_BASE (0xE6790000U) +#endif + +#define DBSC_CH_NUM (1U) /* Number of DBSCx */ +#define DBSC_A_CH_OFFSET (0U) /* 1ch only (for S4)*/ +#define DBSC_D_CH_OFFSET (0U) /* 1ch only (for S4)*/ + +#define DBSC_SYSCNT0 (DBSC_BASE + 0x0100U) +#define DBSC_SYSCNT0A (DBSC_BASE + 0x0108U) +#define DBSC_DBBUS0CNF2 (DBSC_BASE + 0x0808U) +#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) +#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) +#define DBSC_DBCAMDIS (DBSC_BASE + 0x09FCU) +#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) +#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) +#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) +#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) +#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) +#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) +#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) +#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) +#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) +#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) +#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) +#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) +#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) +#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) +#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) +#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) +#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) +#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) +#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) +#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) +#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) +#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) +#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) +#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) +#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) +#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if defined(__RH850G3K__) +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) +#define DBSC_A_BASE (BASE_DBSC_ADDR) +#else +#define DBSC_D_BASE (0xE67A4000U) +#define DBSC_A_BASE (0xE6790000U) +#endif + +#define DBSC_CH_NUM (2U) /* ch number of DBSCx */ +#define DBSC_A_CH_OFFSET (0x8000U) +#define DBSC_D_CH_OFFSET (0x4000U) + +#define DBSC_SYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DBSC_SYSCNT0A (DBSC_A_BASE + 0x0100U) +#define DBSC_DBBUS0CNF2 (DBSC_A_BASE + 0x0808U) +#define DBSC_DBCAM0CNF1 (DBSC_A_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_A_BASE + 0x0908U) +#define DBSC_DBCAMDIS (DBSC_A_BASE + 0x09FCU) +#define DBSC_DBCAM0CNF3 (DBSC_A_BASE + 0x090CU) +#define DBSC_DBSCHCNT0 (DBSC_A_BASE + 0x1000U) +#define DBSC_DBSCHSZ0 (DBSC_A_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_A_BASE + 0x1020U) +#define DBSC_DBSCHQOS_0_0 (DBSC_A_BASE + 0x1100U) +#define DBSC_DBSCHQOS_0_1 (DBSC_A_BASE + 0x1104U) +#define DBSC_DBSCHQOS_0_2 (DBSC_A_BASE + 0x1108U) +#define DBSC_DBSCHQOS_0_3 (DBSC_A_BASE + 0x110CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_A_BASE + 0x1140U) +#define DBSC_DBSCHQOS_4_1 (DBSC_A_BASE + 0x1144U) +#define DBSC_DBSCHQOS_4_2 (DBSC_A_BASE + 0x1148U) +#define DBSC_DBSCHQOS_4_3 (DBSC_A_BASE + 0x114CU) +#define DBSC_DBSCHQOS_9_0 (DBSC_A_BASE + 0x1190U) +#define DBSC_DBSCHQOS_9_1 (DBSC_A_BASE + 0x1194U) +#define DBSC_DBSCHQOS_9_2 (DBSC_A_BASE + 0x1198U) +#define DBSC_DBSCHQOS_9_3 (DBSC_A_BASE + 0x119CU) +#define DBSC_DBSCHQOS_12_0 (DBSC_A_BASE + 0x11C0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_A_BASE + 0x11C4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_A_BASE + 0x11C8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_A_BASE + 0x11CCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_A_BASE + 0x11D0U) +#define DBSC_DBSCHQOS_13_1 (DBSC_A_BASE + 0x11D4U) +#define DBSC_DBSCHQOS_13_2 (DBSC_A_BASE + 0x11D8U) +#define DBSC_DBSCHQOS_13_3 (DBSC_A_BASE + 0x11DCU) +#define DBSC_DBSCHQOS_14_0 (DBSC_A_BASE + 0x11E0U) +#define DBSC_DBSCHQOS_14_1 (DBSC_A_BASE + 0x11E4U) +#define DBSC_DBSCHQOS_14_2 (DBSC_A_BASE + 0x11E8U) +#define DBSC_DBSCHQOS_14_3 (DBSC_A_BASE + 0x11ECU) +#define DBSC_DBSCHQOS_15_0 (DBSC_A_BASE + 0x11F0U) +#define DBSC_DBSCHQOS_15_1 (DBSC_A_BASE + 0x11F4U) +#define DBSC_DBSCHQOS_15_2 (DBSC_A_BASE + 0x11F8U) +#define DBSC_DBSCHQOS_15_3 (DBSC_A_BASE + 0x11FCU) +#define DBSC_SCFCTST2 (DBSC_A_BASE + 0x1048U) +#endif /* RCAR_LSI == RCAR_S4 */ + +#if defined(__RH850G3K__) +#define QOS_BASE (BASE_QOS_ADDR) +#else +#define QOS_BASE (0xE67E0000U) +#endif +#define QOS_FIX_QOS_BANK0 (QOS_BASE + 0x00000000U) +#define QOS_FIX_QOS_BANK1 (QOS_BASE + 0x00001000U) +#define QOS_BE_QOS_BANK0 (QOS_BASE + 0x00002000U) +#define QOS_BE_QOS_BANK1 (QOS_BASE + 0x00003000U) +#define QOS_SL_INIT (QOS_BASE + 0x00008000U) +#define QOS_REF_ARS (QOS_BASE + 0x00008004U) +#define QOS_STATQC (QOS_BASE + 0x00008008U) +#define QOS_REF_ENBL (QOS_BASE + 0x00008044U) +#define QOS_BWG (QOS_BASE + 0x0000804CU) +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE +#define QOSWT_FIX_QOS_BANK0 (QOS_BASE + 0x00000800U) +#define QOSWT_FIX_QOS_BANK1 (QOS_BASE + 0x00001800U) +#define QOSWT_BE_QOS_BANK0 (QOS_BASE + 0x00002800U) +#define QOSWT_BE_QOS_BANK1 (QOS_BASE + 0x00003800U) +#define QOSWT_WTEN (QOS_BASE + 0x00008030U) +#define QOSWT_WTREF (QOS_BASE + 0x00008034U) +#define QOSWT_WTSET0 (QOS_BASE + 0x00008038U) +#define QOSWT_WTSET1 (QOS_BASE + 0x0000803CU) +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + +#define QOS_RAS (QOS_BASE + 0x00010000U) +#define QOS_RAEN (QOS_BASE + 0x00010018U) +#define QOS_DANN_LOW (QOS_BASE + 0x00010030U) +#define QOS_DANN_HIGH (QOS_BASE + 0x00010034U) +#define QOS_DANT (QOS_BASE + 0x00010038U) +#define QOS_EMS_LOW (QOS_BASE + 0x00010040U) +#define QOS_EMS_HIGH (QOS_BASE + 0x00010044U) +#define QOS_FSS (QOS_BASE + 0x00010048U) +#define QOS_INSFC (QOS_BASE + 0x00010050U) +#define QOS_EARLYR (QOS_BASE + 0x00010060U) +#define QOS_RACNT0 (QOS_BASE + 0x00010080U) +#define QOS_STATGEN0 (QOS_BASE + 0x00010088U) + +#define CCI_BASE (BASE_CCI_ADDR) +#define CCIQOS00 (CCI_BASE + 0xC020U) +#define CCIQOS01 (CCI_BASE + 0xC024U) +#define CCIQOS10 (CCI_BASE + 0xD000U) +#define CCIQOS11 (CCI_BASE + 0xD004U) +#if (RCAR_LSI == RCAR_S4) +#define CCIQOS12 (CCI_BASE + 0xD008U) +#define CCIQOS13 (CCI_BASE + 0xD00CU) +#endif + +static void dbsc_setting(void) +{ + for(uint32_t loop = 0; loop < DBSC_CH_NUM; loop++) + { + /* DBSC CAM, Scheduling Setting */ + mem_write32((DBSC_SYSCNT0 + (DBSC_D_CH_OFFSET * loop)), 0x00001234U); + mem_write32((DBSC_SYSCNT0A + (DBSC_A_CH_OFFSET * loop)), 0x00001234U); + mem_write32((DBSC_DBCAM0CNF1 + (DBSC_A_CH_OFFSET * loop)), 0x00104214U); /* dbcam0cnf1 */ + mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U); /* dbcam0cnf2 */ + mem_write32((DBSC_DBCAM0CNF3 + (DBSC_A_CH_OFFSET * loop)), 0x00000003U); /* dbcam0cnf3 */ + +#if (RCAR_LSI == RCAR_S4) + #if (WA_OTLINT5579 == 1 && ECC_ENABLE == 1) + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000002U); /* OTLINT-5579: V4H DBSC W/A-1,2 */ + #else + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000000U); + #endif +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + #if (WA_OTLINT5579 == 1 && ECC_ENABLE == 1) + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000013U); /* OTLINT-5579: V4H DBSC W/A-1,2,3 */ + #elif (WA_OTLINT5579 == 1 && ECC_ENABLE == 0) + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000011U); /* OTLINT-5579: V4H DBSC W/A-3 */ + #else + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); + #endif +#endif + + mem_write32((DBSC_DBSCHCNT0 + (DBSC_A_CH_OFFSET * loop)), 0x000F0037U); /* dbschcnt0 */ + mem_write32((DBSC_DBSCHSZ0 + (DBSC_A_CH_OFFSET * loop)), 0x00000001U); /* dbschsz0 */ + mem_write32((DBSC_DBSCHRW0 + (DBSC_A_CH_OFFSET * loop)), 0xF7311111U); /* dbschrw0 */ + mem_write32((DBSC_SCFCTST2 + (DBSC_A_CH_OFFSET * loop)), 0x111F1FFFU); + +#if (((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) && WA_OTLINT5579 == 1) + mem_write32((DBSC_DBBUS0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x00000007U); /* OTLINT-5579: V4H DBSC WA3 */ +#else + mem_write32((DBSC_DBBUS0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x00000003U); /* S4, V4H w/o DBSC WA3 */ +#endif + + /* DBSC QoS Setting */ + mem_write32((DBSC_DBSCHQOS_0_0 + (DBSC_A_CH_OFFSET * loop)), 0x0000FFFFU); + mem_write32((DBSC_DBSCHQOS_0_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000480U); + mem_write32((DBSC_DBSCHQOS_0_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_0_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_4_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000600U); + mem_write32((DBSC_DBSCHQOS_4_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000480U); + mem_write32((DBSC_DBSCHQOS_4_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_4_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_9_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000400U); + mem_write32((DBSC_DBSCHQOS_9_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_9_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000200U); + mem_write32((DBSC_DBSCHQOS_9_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); + mem_write32((DBSC_DBSCHQOS_12_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000040U); + mem_write32((DBSC_DBSCHQOS_12_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000030U); + mem_write32((DBSC_DBSCHQOS_12_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000020U); + mem_write32((DBSC_DBSCHQOS_12_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); + mem_write32((DBSC_DBSCHQOS_13_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_13_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000240U); + mem_write32((DBSC_DBSCHQOS_13_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_13_3 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U); + mem_write32((DBSC_DBSCHQOS_14_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000200U); + mem_write32((DBSC_DBSCHQOS_14_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_14_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); + mem_write32((DBSC_DBSCHQOS_14_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000080U); + mem_write32((DBSC_DBSCHQOS_15_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); + mem_write32((DBSC_DBSCHQOS_15_1 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U); + mem_write32((DBSC_DBSCHQOS_15_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000080U); + mem_write32((DBSC_DBSCHQOS_15_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000040U); + + mem_write32((DBSC_SYSCNT0 + (DBSC_D_CH_OFFSET * loop)), 0x00000000U); + mem_write32((DBSC_SYSCNT0A + (DBSC_A_CH_OFFSET * loop)), 0x00000000U); + } +} +/* End of function dbsc_setting(void) */ + +void qos_init(void) +{ + uint32_t i; + + /* Setting the register of DBSC4 for QoS initialize */ + dbsc_setting(); + + NOTICE("QoS setting(%s)\n", RCAR_QOS_VERSION); + NOTICE("DRAM refresh interval 1.91 usec\n"); + +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE + NOTICE("Periodic Write DQ Training\n"); +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + +#if (RCAR_LSI == RCAR_S4) + /* Resource Alloc setting */ + mem_write32(QOS_RAS, 0x00000028U); + mem_write32(QOS_DANN_LOW, 0x02020201U); + mem_write32(QOS_DANN_HIGH, 0x04040200U); + mem_write32(QOS_DANT, 0x00181004U); + mem_write32(QOS_EMS_LOW, 0x00000000U); + mem_write32(QOS_EMS_HIGH, 0x00000000U); + mem_write32(QOS_FSS, 0x0000000AU); + mem_write32(QOS_INSFC, 0x030F0001U); + mem_write32(QOS_EARLYR, 0x00000000U); + mem_write32(QOS_RACNT0, 0x00050003U); + mem_write32(QOS_STATGEN0, 0x00000000U); + + /* QoS MSTAT setting */ + mem_write32(QOS_SL_INIT, 0x00050100U); + mem_write32(QOS_REF_ARS, 0x00FB0000U); + mem_write32(QOS_REF_ENBL, 0x00000012U); + mem_write32(QOS_BWG, 0x00000002U); + mem_write32(AXMM_MMCR, 0x00010000U); + + mem_write32(CCIQOS00, 0x08000000); + mem_write32(CCIQOS01, 0x08000000); + mem_write32(CCIQOS10, 0x00000001); + mem_write32(CCIQOS11, 0x00000001); + mem_write32(CCIQOS12, 0x00000001); + mem_write32(CCIQOS13, 0x00000001); +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_ENABLE) + /* Address Split 2ch */ + mem_write32(AXMM_ADSPLCR0, 0x00000000U); + mem_write32(AXMM_ADSPLCR1, 0x00FF1B0CU); + mem_write32(AXMM_ADSPLCR2, 0x00000000U); + mem_write32(AXMM_ADSPLCR3, 0x00000000U); +#endif + + mem_write32(CCIQOS00, 0x08000000); + mem_write32(CCIQOS01, 0x08000000); + mem_write32(CCIQOS10, 0x00000000); + mem_write32(CCIQOS11, 0x00000000); + + /* Resource Alloc setting */ + mem_write32(QOS_RAS, 0x00000040U); + mem_write32(QOS_DANN_LOW, 0x02020201U); + mem_write32(QOS_DANN_HIGH, 0x04040200U); + mem_write32(QOS_DANT, 0x00181008U); + mem_write32(QOS_EMS_LOW, 0x00000000U); + mem_write32(QOS_EMS_HIGH, 0x00000000U); + mem_write32(QOS_FSS, 0x0000000AU); + mem_write32(QOS_INSFC, 0x030F0001U); + mem_write32(QOS_EARLYR, 0x00000000U); + mem_write32(QOS_RACNT0, 0x00050003U); + mem_write32(QOS_STATGEN0, 0x00000000U); + + /* QoS MSTAT setting */ + mem_write32(QOS_SL_INIT, 0x00050100U); + mem_write32(QOS_REF_ARS, 0x00FB0000U); + mem_write32(QOS_REF_ENBL, 0x00000012U); + mem_write32(QOS_BWG, 0x00000004U); + #if (((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) && WA_OTLINT5579 == 1) + mem_write32(AXMM_MMCR, 0x00000000U); /* OTLINT-5579: V4H DBSC WA3 */ + #else + mem_write32(AXMM_MMCR, 0x00010000U); + #endif + +#endif /* RCAR_LSI == RCAR_S4 */ + + for (i = 0U; i < QOS_TBL_MAX; i++) + { + mem_write64((QOS_FIX_QOS_BANK0 + (i * 8U)), g_qosbw_tbl[i].fix); + mem_write64((QOS_FIX_QOS_BANK1 + (i * 8U)), g_qosbw_tbl[i].fix); + mem_write64((QOS_BE_QOS_BANK0 + (i * 8U)), g_qosbw_tbl[i].be); + mem_write64((QOS_BE_QOS_BANK1 + (i * 8U)), g_qosbw_tbl[i].be); + } + +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE + for (i = 0U; i < QOS_TBL_MAX; i++) + { + mem_write64((QOSWT_FIX_QOS_BANK0 + (i * 8U)), g_qoswt_tbl[i].fix); + mem_write64((QOSWT_FIX_QOS_BANK1 + (i * 8U)), g_qoswt_tbl[i].fix); + mem_write64((QOSWT_BE_QOS_BANK0 + (i * 8U)), g_qoswt_tbl[i].be); + mem_write64((QOSWT_BE_QOS_BANK1 + (i * 8U)), g_qoswt_tbl[i].be); + } +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + + /* QoS SRAM setting */ + mem_write32(QOS_RAEN, 0x00000001U); +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE + mem_write32(QOSWT_WTREF, 0x02080208U); + mem_write32(QOSWT_WTSET0, 0x14A6050BU); + mem_write32(QOSWT_WTSET1, 0x14A6050BU); + mem_write32(QOSWT_WTEN, 0x00000001U); +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + mem_write32(QOS_STATQC, 0x00000101U); +} +/* End of function qos_init(void) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/dma2.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/dma2.c new file mode 100644 index 0000000..b4a2513 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/dma2.c @@ -0,0 +1,218 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2015-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : DMA driver + ******************************************************************************/ +/****************************************************************************** + * @file dma.c + * - Version : 0.05 + * @brief RT-DMAC driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 15.10.2021 0.01 First Release + * : 10.02.2022 0.02 Add dma_start_xbyte function. + * : 18.03.2022 0.03 Modify to read modify write when write to + * : register. + * : 29.03.2022 0.04 Modify magic number to definition. + * : 09.11.2022 0.05 License notation change. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * from flash_writer's reg_rcar.h + */ +/* RT-DMA Control */ +#define RTDMACTL_BASE (BASE_RTDMACTL_ADDR) +#define RTDMAC_RDMOR (RTDMACTL_BASE + 0x0060U) /* R/W 16 DMA operation register (for channels 0 to 15) */ +/* RT-DMAC0(for RPC) */ +#define RTDMAC_BASE (BASE_RTDMA0_ADDR) +#define RTDMAC_RDMSEC (RTDMAC_BASE + 0x00B0U) /* R/W 32 DMA secure control register (for channels 0 to 15) */ +#define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x0000U + (0x80U * (x))) /* R/W 32 DMA source address register_0 */ +#define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x0004U + (0x80U * (x))) /* R/W 32 DMA destination address register_0 */ +#define RTDMAC_RDMTCR(x) (RTDMAC_BASE + 0x0008U + (0x80U * (x))) /* R/W 32 DMA transfer count register_0 */ +#define RTDMAC_RDMCHCR(x) (RTDMAC_BASE + 0x000CU + (0x80U * (x))) /* R/W 32 DMA channel control register_0 */ + +#include "dma2.h" + +#define RDMOR_INITIAL (0x0301U) +#define DMACH (0U) +#define RDMTCR_CNT_SHIFT (6U) +#define RDMCHCR_TRN_MODE (0x00105409U) +#define RDMCHCR_TRN_MODE_SRC_FIX (0x00104409U) +#define RDMCHCR_TRN_MODE_1BYTE (0x00005401U) +#define RDMCHCR_TE_BIT (0x00000002U) +#define TE_FLAG (0x00000000U) +#define RDMCHCR_CAE_BIT (0x80000000U) +#define RDMCHCR_CAE_BIT_NOERROR (0x00000000U) +#define RDMCHCR_CAIE_BIT (0x40000000U) +#define RDMCHCR_DPM_BIT (0x30000000U) +#define RDMCHCR_RPT_BIT (0x0F000000U) +#define RDMCHCR_WAIT_BIT (0x00800000U) +#define RDMCHCR_DPB_BIT (0x00400000U) +#define RDMCHCR_DSE_BIT (0x00080000U) +#define RDMCHCR_DSIE_BIT (0x00040000U) +#define RDMCHCR_DM_BIT (0x0000C000U) +#define RDMCHCR_SM_BIT (0x00003000U) +#define RDMCHCR_RS_BIT (0x00000F00U) +#define RDMCHCR_TS_BIT (0x00300018U) +#define RDMCHCR_IE_BIT (0x00000004U) +#define RDMCHCR_TE_BIT (0x00000002U) +#define RDMCHCR_DE_BIT (0x00000001U) +#define RDMCHCR_CONF_MASK (RDMCHCR_TS_BIT | RDMCHCR_DM_BIT | RDMCHCR_SM_BIT \ + | RDMCHCR_RS_BIT | RDMCHCR_DE_BIT) +#define RDMCHCR_DESCRIPTOR_CONF_MASK (RDMCHCR_DPM_BIT | RDMCHCR_RPT_BIT | RDMCHCR_WAIT_BIT | RDMCHCR_DPB_BIT) +#define RDMCHCR_INTERRUPT_MASK (RDMCHCR_CAIE_BIT | RDMCHCR_DSIE_BIT | RDMCHCR_IE_BIT) +#define RDMCHCR_FLAG_MASK (RDMCHCR_CAE_BIT | RDMCHCR_DSE_BIT | RDMCHCR_TE_BIT) +#define RDMCHCR_ALL_BIT_MASK (RDMCHCR_CONF_MASK | RDMCHCR_DESCRIPTOR_CONF_MASK \ + | RDMCHCR_INTERRUPT_MASK | RDMCHCR_FLAG_MASK) +#define CMNSR_TEND (0x00000001U) +#define RDMTCR_UPPER_MASK (0xFF000000U) + +/* fraction mask for 64-byte units */ +#define FRACTION_MASK_64_BYTE (0x0000003FU) +/* fraction mask for 256-byte units */ +#define FRACTION_MASK_256_BYTE (0x000000FFU) + +void dma2_init(void) +{ + uint32_t reg; + + /* DMA transfer disabled */ + reg = mem_read32(RTDMAC_RDMCHCR(DMACH)); + reg &= ~(RDMCHCR_ALL_BIT_MASK); + mem_write32(RTDMAC_RDMCHCR(DMACH), reg); + + /* DMA operation */ + mem_write16(RTDMAC_RDMOR, RDMOR_INITIAL); + /* DMA secure control register */ + reg = mem_read32(RTDMAC_RDMSEC); + reg |= ((uint32_t)1U << DMACH); + mem_write32(RTDMAC_RDMSEC, reg); +} +/* End of function dma_init */ + +void dma2_start(uint32_t dst, uint32_t src, uint32_t len, uint32_t mode) +{ + uint32_t reg; + + if (((dst & FRACTION_MASK_64_BYTE) != 0U) || ((src & FRACTION_MASK_64_BYTE) != 0U)) + { + /* dst or src are not 64-bit alignment. */ + ERROR("not 64-bit alignment in DMA(2) transfer\n"); + while(1) + { + ; /* panic */ + } + } + + /* round up 256 byte alignment */ + len += FRACTION_MASK_256_BYTE; + len &= (~(uint32_t)(FRACTION_MASK_256_BYTE)); + + /* DMA destination address */ + mem_write32(RTDMAC_RDMDAR(DMACH), dst); + /* DMA source address */ + mem_write32(RTDMAC_RDMSAR(DMACH), src); + /* DMA 64bytes-unit transfer count */ + mem_write32(RTDMAC_RDMTCR(DMACH), ((len >> RDMTCR_CNT_SHIFT) & (~RDMTCR_UPPER_MASK))); + /* DMA channel control */ + reg = mem_read32(RTDMAC_RDMCHCR(DMACH)); + if (mode == DMA_MODE_SRC_FIX) + { + reg |= RDMCHCR_TRN_MODE_SRC_FIX; + mem_write32(RTDMAC_RDMCHCR(DMACH), reg); + } + else + { + reg |= RDMCHCR_TRN_MODE; + mem_write32(RTDMAC_RDMCHCR(DMACH), reg); + } +} +/* End of function dma_start */ + +void dma2_start_xbyte(uint32_t dst, uint32_t src, uint32_t len, uint32_t trns_unit) +{ + uint32_t reg; + + /* DMA destination address */ + mem_write32(RTDMAC_RDMDAR(DMACH), dst); + /* DMA source address */ + mem_write32(RTDMAC_RDMSAR(DMACH), src); + /* DMA transfer count */ + mem_write32(RTDMAC_RDMTCR(DMACH), ((len >> trns_unit) & (~RDMTCR_UPPER_MASK))); + /* DMA channel control */ + reg = mem_read32(RTDMAC_RDMCHCR(DMACH)); + if (trns_unit == TRANS_UNIT_1BYTE) + { + /* DMA channel control (transfer unit is 1 byte)*/ + reg |= RDMCHCR_TRN_MODE_1BYTE; + mem_write32(RTDMAC_RDMCHCR(DMACH), reg); + } + if (trns_unit == TRANS_UNIT_64BYTES) + { + /* DMA channel control (transfer unit is 64 bytes) */ + reg |= RDMCHCR_TRN_MODE; + mem_write32(RTDMAC_RDMCHCR(DMACH), reg); + } +} +/* End of function dma_start_byte */ + +void dma2_end(void) +{ + uint32_t reg; + + /* Check end of DMA transfer. */ + do + { + wdt_restart(); + /* Check error of DMA transfer */ + if ((mem_read32(RTDMAC_RDMCHCR(DMACH)) & RDMCHCR_CAE_BIT) != RDMCHCR_CAE_BIT_NOERROR) + { + ERROR("DMA(2) - Channel Address Error\n"); + while(1) + { + ; /* panic */ + } + } + } + while ((mem_read32(RTDMAC_RDMCHCR(DMACH)) & RDMCHCR_TE_BIT) == TE_FLAG); + + /* DMA transfer disabled */ + reg = mem_read32(RTDMAC_RDMCHCR(DMACH)); + reg &= ~(RDMCHCR_ALL_BIT_MASK); + mem_write32(RTDMAC_RDMCHCR(DMACH), reg); + + rpc_end_state_check(); +} +/* End of function dma_end */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/dma2.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/dma2.h new file mode 100644 index 0000000..80dbd19 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/dma2.h @@ -0,0 +1,56 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2015-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : DMA driver header + ******************************************************************************/ +/****************************************************************************** + * @file dma.h + * - Version : 0.03 + * @brief DMA driver header + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 16.02.2022 0.01 First Release + * : 01.04.2022 0.02 Add definitions. + * : 09.11.2022 0.03 License notation change. + *****************************************************************************/ + +#ifndef DMA2_H_ +#define DMA2_H_ + +#define TRANS_UNIT_1BYTE (0x0) +#define TRANS_UNIT_64BYTES (0x6) + +#define DMA_MODE_SRC_INC (0x0U) +#define DMA_MODE_SRC_FIX (0x1U) +#define TRANS_SIZE_1BYTE (0x1U) +#define TRANS_SIZE_64BYTE (0x40U) + +void dma2_init(void); +void dma2_start(uint32_t dst, uint32_t src, uint32_t len, uint32_t mode); +void dma2_start_xbyte(uint32_t dst, uint32_t src, uint32_t len, uint32_t trns_unit); +void dma2_end(void); + +#endif /* DMA2_H_ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/qspi_xdr_mode.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/qspi_xdr_mode.c new file mode 100644 index 0000000..567ac97 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/qspi_xdr_mode.c @@ -0,0 +1,367 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RPC driver + ******************************************************************************/ +/****************************************************************************** + * @file rpc.c + * - Version : 0.08 + * @brief Initial setting process of RPC. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Add rpc_release function. + * : 27.07.2022 0.03 Add QSPI Flash vendor ID check and QSPI Flash + * : command initialization. + * : 22.08.2022 0.04 Add DDR mode for QSPI Flash. + * : 21.09.2022 0.05 Fix comparison of test data + * : in adjust_strobe_timing function. + * : 12.01.2023 0.06 Add PFC setting to qspi_ddr_transfer_mode() + * : function. + * : 04.04.2023 0.07 Removed stdio.h. + * : 17.06.2024 0.08 Fix PUEN register setting when QSPI DDR mode. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RPC_PHYCNT_DDRCAL ((uint32_t)1U << 19U) +#define RPC_PHYCNT_PHYMEM_SPI_DDR ((uint32_t)1U << 0U) +#define RPC_PHYCNT_PHYMEM_MASK (0x00000003U) +#define RPC_DRCR_RCF ((uint32_t)1U << 9U) +#define RPC_DRCR_SSLN_NEGATE (0x01000000U) +#define RPC_DRCR_RBE_RBURST_MASK (0x001F0000U) +#define RPC_DRCR_RBE_RBURST_1DATA (0x00000000U) /* Smallest data unit (8byte) */ +#define RPC_DRCR_RBE_RBURST_32DATA (0x001F0000U) /* biggest data unit (256byte) */ +#define RPC_DRCR_RBE_ENABLE (0x00000100U) +#define RPC_DRCMR_CMD_SHIFT (16U) +#define RPC_DRCMR_CMD_MASK ((uint32_t)0xFFU << RPC_DRCMR_CMD_SHIFT) +#define RPC_DRCMR_OCMD_MASK ((uint32_t)0xFFU << 0U) +#define RPC_DRCMR_HW_INIT (0x00030000U) +#define RPC_DREAR_EAV_MASK ((uint32_t)0xFFU << 16U) +#define RPC_DREAR_EAC_MASK ((uint32_t)0x7U << 0U) +#define RPC_DREAR_EAC_EXT_ADDR_25BIT ((uint32_t)0x1U << 0U) +#define RPC_DREAR_HW_INIT (0x00000000U) +#define RPC_DRENR_CDB_MASK (0xC0000000U) +#define RPC_DRENR_CDB_1BIT (0x00000000U) +#define RPC_DRENR_ADB_MASK (0x03000000U) +#define RPC_DRENR_ADB_4BIT (0x02000000U) +#define RPC_DRENR_DRDB_MASK (0x00030000U) +#define RPC_DRENR_DRDB_4BIT (0x00020000U) +#define RPC_DRENR_DME_MASK (0x00008000U) +#define RPC_DRENR_DME_ENABLE (0x00008000U) +#define RPC_DRENR_CDE_ENABLE ((uint32_t)0x1U << 14U) +#define RPC_DRENR_ADE_MASK (0x00000F00U) +#define RPC_DRENR_ADE_32BIT_ADDR ((uint32_t)0xFU << 8U) +#define RPC_DRENR_HW_INIT (0x00004700U) +#define RPC_DRENR_TRANS_DISABLE (0x00000000U) +#define RPC_SMCMR_CMD_SHIFT (16U) +#define RPC_SMCMR_CMD_MASK (0x00FF0000U) +#define RPC_SMCMR_OCMD_MASK (0x000000FFU) +#define RPC_SMDRENR_HYPE_MASK (0x00007000U) +#define RPC_SMDRENR_ADDRE (0x00000100U) +#define RPC_SMDRENR_OPDRE (0x00000010U) +#define RPC_SMDRENR_SPIDRE (0x00000001U) +#define RPC_SMENR_CDB_MASK (0xC0000000U) +#define RPC_SMENR_OCDB_MASK (0x30000000U) +#define RPC_SMENR_ADB_MASK (0x03000000U) +#define RPC_SMENR_OPDB_MASK (0x00300000U) +#define RPC_SMENR_SPIDB_MASK (0x00030000U) +#define RPC_SMENR_DME_EN (0x00008000U) +#define RPC_SMENR_CDE_EN (0x00004000U) +#define RPC_SMENR_OCDE_EN (0x00001000U) +#define RPC_SMENR_ADE_MASK (0x00000F00U) +#define RPC_SMENR_OPDE_MASK (0x000000F0U) +#define RPC_SMENR_SPIDE_MASK (0x0000000FU) +#define RPC_SMENR_SPIDE_SPI_32 (0x0000000FU) +#define RPC_SMCR_SSLKP (0x00000100U) +#define RPC_SMCR_SPIRE (0x00000004U) +#define RPC_SMCR_SPIWE (0x00000002U) +#define RPC_SMCR_SPIE (0x00000001U) +#define RPC_CMNCR_MD (0x80000000U) /* bit[31]:Operating Mode Switch -> Manual mode */ +#define RPC_CMNCR_MOIIO_MASK (0x00FF0000U) +#define RPC_CMNCR_MOIIO3_HI_Z (0x00C00000U) +#define RPC_CMNCR_MOIIO2_HI_Z (0x00300000U) +#define RPC_CMNCR_MOIIO1_HI_Z (0x000C0000U) +#define RPC_CMNCR_MOIIO0_HI_Z (0x00030000U) +#define RPC_CMNCR_BSZ_MASK (0x00000003U) +#define RPC_DRDRENR_DRDRE (0x00000001U) +#define RPC_DRDRENR_ADDRE (0x00000100U) +#define RPC_PHYOFFSET1_DDRTMG_MSK (0x30000000U) +#define RPC_PHYOFFSET1_DDRTMG_DDR (0x20000000U) + +#define STRTIM_SMALLEST (0x0000000FU) +#define STRTIM_MASK_3 (0x00000008U) +#define STRTIM_MASK (0x00000007U) +#define STRTIM_MATCH_ERROR (0xFFFFFFFFU) + +/* For PFC register */ +#define PFC_PUEN3_QSPI0_IO3 (0x00010000U) /* bit16 */ +#define PFC_PUEN3_QSPI0_IO2 (0x00020000U) /* bit17 */ + +/* verification data for strobe timing adjustment */ +#define QSPI_TESTDATA (0x5A5AA5A5U) +#define QSPI_TESTDATA_OFFSET (0x00000400U) +#define QSPI_TESTDATA_FLASH_ADDR (FLASH_CONTENT_CERT_ADDR + QSPI_TESTDATA_OFFSET) /* Offset 0x00240400 */ + +static inline void set_strtim(uint32_t strobe_timing); +#if (QSPI_DDR_MODE==1) +static void adjust_strobe_timing(void); +#endif + +#if (QSPI_DDR_MODE==0) +void qspi_sdr_transfer_mode(uint32_t command) +{ + uint32_t reg; + /* check the transfer end flag */ + rpc_end_state_check(); + + /* For the initial setting flow of RPC, see Figure 112.12 in */ + /* "R-Car Series, S4 Series User's Manual" and */ + /* "R-Car Series, V4H Series User's Manual". */ + /* This RPC setting is for S25FS512S device */ + /* A register that does not set a value expects */ + /* the initial value of HW. */ + + /* PHY calibration */ + set_strtim(STRTIM_SMALLEST); + reg = mem_read32(RPC_PHYCNT); + reg |= RPC_PHYCNT_CAL; + mem_write32(RPC_PHYCNT, reg); + /* External Address Space Read Mode */ + reg = mem_read32(RPC_CMNCR); + reg &= ~(RPC_CMNCR_MD); + mem_write32(RPC_CMNCR, reg); + /* Read cache Flash */ + reg = mem_read32(RPC_DRCR); + mem_write32(RPC_DRCR, (reg | RPC_DRCR_RCF)); + /* 32bit address read command*/ + reg = mem_read32(RPC_DRCMR); + reg &= ~(RPC_DRCMR_CMD_MASK | RPC_DRCMR_OCMD_MASK); + reg |= (command << RPC_SMCMR_CMD_SHIFT); + mem_write32(RPC_DRCMR, reg); + /* Extended external address valid range is [25:0]*/ + reg = mem_read32(RPC_DREAR); + reg &= ~(RPC_DREAR_EAV_MASK | RPC_DREAR_EAC_MASK); + reg |= RPC_DREAR_EAC_EXT_ADDR_25BIT; + mem_write32(RPC_DREAR, reg); + /* output command is 32bit width */ + reg = mem_read32(RPC_DRENR); + reg &= ~(RPC_DRENR_CDE_ENABLE | RPC_DRENR_ADE_MASK); + reg |= (RPC_DRENR_CDE_ENABLE | RPC_DRENR_ADE_32BIT_ADDR); + mem_write32(RPC_DRENR, reg); +} +/* End of function rpc_init(void) */ + +#else +void qspi_ddr_transfer_mode(uint32_t command) +{ + uint32_t reg; + + /* check the transfer end flag */ + rpc_end_state_check(); + + cpg_reg_write(CPG_RPCCKCR, CPG_RPCCKCR, RPC_CLK_160MHZ); /* RPCD2 = 80MHz */ + + /* Disable pull-up/down function of QSPI0_IO2/QSPI0_IO3 when QSPI DDR transfer mode. */ + reg = mem_read32(PFC_PUEN3_RW); + reg &= ~(PFC_PUEN3_QSPI0_IO3 | PFC_PUEN3_QSPI0_IO2); + pfc_reg_write(PFC_PUEN3_RW, reg); + + /* For the initial setting flow of RPC, see Figure 112.12 in */ + /* "R-Car Series, S4 Series User's Manual" and */ + /* "R-Car Series, V4H Series User's Manual". */ + /* This RPC setting is for S25FS512S device */ + /* A register that does not set a value expects */ + /* the initial value of HW. */ + + /* PHY calibration */ + set_strtim(STRTIM_SMALLEST); + reg = mem_read32(RPC_PHYCNT); + reg |= RPC_PHYCNT_DDRCAL; + reg |= RPC_PHYCNT_PHYMEM_SPI_DDR; + mem_write32(RPC_PHYCNT, reg); + /* External Address Space Read Mode */ + reg = mem_read32(RPC_CMNCR); + reg &= ~(RPC_CMNCR_MD | RPC_CMNCR_MOIIO_MASK | RPC_CMNCR_BSZ_MASK); + reg |= (RPC_CMNCR_MOIIO0_HI_Z | RPC_CMNCR_MOIIO1_HI_Z | RPC_CMNCR_MOIIO2_HI_Z | RPC_CMNCR_MOIIO3_HI_Z); + mem_write32(RPC_CMNCR, reg); + /* Read cache Flash */ + reg = mem_read32(RPC_DRCR); + reg &= ~(RPC_DRCR_RBE_RBURST_MASK); + reg |= (RPC_DRCR_SSLN_NEGATE | RPC_DRCR_RBE_RBURST_1DATA | RPC_DRCR_RCF | RPC_DRCR_RBE_ENABLE); + mem_write32(RPC_DRCR, (reg | RPC_DRCR_RCF)); + /* 32bit address read command*/ + reg = mem_read32(RPC_DRCMR); + reg &= ~(RPC_DRCMR_CMD_MASK | RPC_DRCMR_OCMD_MASK); + reg |= (command << RPC_SMCMR_CMD_SHIFT); + mem_write32(RPC_DRCMR, reg); + /* Extended external address valid range is [25:0]*/ + reg = mem_read32(RPC_DREAR); + reg &= ~(RPC_DREAR_EAV_MASK | RPC_DREAR_EAC_MASK); + reg |= RPC_DREAR_EAC_EXT_ADDR_25BIT; + mem_write32(RPC_DREAR, reg); + /* output command is 32bit width */ + reg = mem_read32(RPC_DRENR); + reg &= ~(RPC_DRENR_CDB_MASK | RPC_DRENR_ADB_MASK | RPC_DRENR_DRDB_MASK + | RPC_DRENR_DME_MASK | RPC_DRENR_CDE_ENABLE | RPC_DRENR_ADE_MASK); + reg |= (RPC_DRENR_CDB_1BIT | RPC_DRENR_ADB_4BIT | RPC_DRENR_DRDB_4BIT + | RPC_DRENR_DME_ENABLE | RPC_DRENR_CDE_ENABLE | RPC_DRENR_ADE_32BIT_ADDR); + mem_write32(RPC_DRENR, reg); + /* Set Dummy Cycle */ + mem_write32(RPC_DRDMCR, (uint32_t)RCAR_QSPI_DDR_DUMMY_CYCLE - 1U); + /* Specifies DDR transfer of the data read. */ + reg = mem_read32(RPC_DRDRENR); + reg |= RPC_DRDRENR_DRDRE | RPC_DRDRENR_ADDRE; + mem_write32(RPC_DRDRENR, reg); + /* timing adjustment in DDR read operation. */ + reg = mem_read32(RPC_PHYOFFSET1); + reg &= ~(RPC_PHYOFFSET1_DDRTMG_MSK); + reg |= RPC_PHYOFFSET1_DDRTMG_DDR; + mem_write32(RPC_PHYOFFSET1, reg); + + /* Change PHYCNT.DDRCAL */ + reg = mem_read32(RPC_PHYCNT); + reg |= RPC_PHYCNT_PHYMEM_SPI_DDR; + reg &= ~RPC_PHYCNT_CAL; + reg |= RPC_PHYCNT_DDRCAL; + mem_write32(RPC_PHYCNT, reg); + + adjust_strobe_timing(); + + /* Set data burst length to 256 byte */ + reg = mem_read32(RPC_DRCR); + reg |= RPC_DRCR_RBE_RBURST_32DATA; + mem_write32(RPC_DRCR, reg); +} + +static void adjust_strobe_timing(void) +{ + uint32_t reg; + uint32_t flash_data; + uint32_t remap_flash_addr; + uint32_t strobe_timing = STRTIM_SMALLEST; + uint32_t first_match = STRTIM_MATCH_ERROR; + uint32_t match_count = 0U; + uint32_t loop; + + /* Convert verification data to logical addresses. */ + remap_register(QSPI_TESTDATA_FLASH_ADDR, &remap_flash_addr); + + INFO("Adjust strobe timing\n"); + + INFO("QSPI_TESTDATA_FLASH_ADDR = 0x%08x\n",remap_flash_addr); + + for(loop = 0U; loop <= STRTIM_SMALLEST; loop++) + { + /* RPC Transfer Disable */ + mem_write32(RPC_DRENR, RPC_DRENR_TRANS_DISABLE); + + /* Read cache Flash */ + reg = mem_read32(RPC_DRCR); + mem_write32(RPC_DRCR, (reg | RPC_DRCR_RCF)); + + /* set strobe timing */ + set_strtim(strobe_timing); + + /* RPC Transfer Enable */ + reg = mem_read32(RPC_DRENR); + reg &= ~(RPC_DRENR_CDB_MASK | RPC_DRENR_ADB_MASK | RPC_DRENR_DRDB_MASK + | RPC_DRENR_DME_MASK | RPC_DRENR_CDE_ENABLE | RPC_DRENR_ADE_MASK); + reg |= (RPC_DRENR_CDB_1BIT | RPC_DRENR_ADB_4BIT | RPC_DRENR_DRDB_4BIT + | RPC_DRENR_DME_ENABLE | RPC_DRENR_CDE_ENABLE | RPC_DRENR_ADE_32BIT_ADDR); + mem_write32(RPC_DRENR, reg); + + /* Read verification Data on QSPIFlash */ + flash_data = mem_read32(remap_flash_addr); + + /* check the transfer end flag */ + rpc_end_state_check(); + + INFO("strobe timing:0x%x\tflash_data:0x%x\ttest_data:0x%x\n", strobe_timing, flash_data, QSPI_TESTDATA); + + /* Comparison of Verification Data */ + if(flash_data == QSPI_TESTDATA) + { + /* First match of validation data. */ + if(first_match == STRTIM_MATCH_ERROR) + { + first_match = strobe_timing; + } + match_count++; + } + else + { + /* If out of timing to match */ + if(first_match != STRTIM_MATCH_ERROR) + { + /* Terminate the exploration of Strobe timing. */ + break; + } + } + strobe_timing--; + } + + /* Verification Data is not matched */ + if(first_match == STRTIM_MATCH_ERROR) + { + ERROR("Failed Strobe timing adjustment of DDR transfer mode.\n"); + panic; + } + + INFO("first_match:0x%x\tmatch_count:0x%x\n", first_match, match_count); + remap_unregister(remap_flash_addr); + + /* strobe timing value adjustment */ + strobe_timing = first_match - (match_count / 2U); + + /* set strobe timing */ + set_strtim(strobe_timing); + INFO("RPC_PHYCNT\t = 0x%08x\n",mem_read32(RPC_PHYCNT)); +} +#endif + +static inline void set_strtim(uint32_t strobe_timing) +{ + uint32_t reg; + reg = mem_read32(RPC_PHYCNT); + reg &= ~((STRTIM_MASK_3 << 24U) | (STRTIM_MASK << 15U)); + reg |= ((strobe_timing & STRTIM_MASK_3) << 24U); /* bit[27] */ + reg |= ((strobe_timing & STRTIM_MASK) << 15U); /* bit[17:15] */ + mem_write32(RPC_PHYCNT, reg); +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/rpc.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/rpc.c new file mode 100644 index 0000000..68310af --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/rpc.c @@ -0,0 +1,280 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RPC driver + ******************************************************************************/ +/****************************************************************************** + * @file rpc.c + * - Version : 0.08 + * @brief Initial setting process of RPC. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Add rpc_release function. + * : 27.07.2022 0.03 Add QSPI Flash vendor ID check and QSPI Flash + * : command initialization. + * : 22.08.2022 0.04 Add DDR mode for QSPI Flash. + * : 21.09.2022 0.05 Fix comparison of test data + * : in adjust_strobe_timing function. + * : 12.01.2023 0.06 Add PFC setting to qspi_ddr_transfer_mode() + * : function. + * : 04.04.2023 0.07 Removed stdio.h. + * : 17.06.2024 0.08 Fix PUEN register setting when QSPI DDR mode. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RST_MODEMR0_BOOTMODE (0xFU << 1U) +#define BOOTMODE_QSPI_SINGLE_40MHZ (0x4U) +#define BOOTMODE_QSPI_DMA (0x6U) + +typedef struct{ + uint32_t reg_addr; /* registers address. */ + uint32_t value; /* setting value. */ +} st_register_table_t; + +#define RPC_TBL_MAX (13U) + +static st_register_table_t g_rpc_reg_hwinit_val_tbl[RPC_TBL_MAX]; + +/* The number of Flash vendor */ +#if USER_ADDED_QSPI == 0 +#define VENDOR_NUM (1U) +#endif /* USER_ADDED_QSPI == 0 */ +/* Command for S25FS512S */ +#define MT25QU01GB_READ_FAST (0x0CU) /* 4FAST_READ, read_fast */ +#define MT25QU01GB_SEC_ER_4BYTE_ADDR (0xDCU) /* 4SE, sector_erase_4byte_addr */ +#define MT25QU01GB_PARA_4KBYTE_ER (0x21U) /* 4P4E, parameter_4kbyte_erase */ +#define MT25QU01GB_PP_4BYTE_ADDR (0x12U) /* 4PP, pp_4byte_addr */ +#define MT25QU01GB_READ_ANY_REG (0x05U) /* READ STATUS, read_any_register */ +#define MT25QU01GB_READ_STATUS (0x70U) /* READ FLAG STATUS, read_stts_register */ +#define MT25QU01GB_WRITE_ENABLE (0x06U) /* WREN, write_enable */ +#define S25FS512S_READ_32BIT_ADDR (0x13U) /* read 32bit address */ +#define S25FS512S_DDR_QUAD_IO_READ_32BIT_ADDR (0xEEU) /* DDR quad I/O read 32bit address */ + +#if USER_ADDED_QSPI == 1 +/* User can customize for another vendor's QSPI Flash. */ +#define VENDOR_NUM (2U) +/* Command for XXXXXXXXX */ +#define XXXXXXXXX_READ_FAST (0x0CU) /* 4-byte read_fast */ +#define XXXXXXXXX_SEC_ER_4BYTE_ADDR (0xDCU) /* sector_erase_4byte_addr */ +#define XXXXXXXXX_PARA_4KBYTE_ER (0x21U) /* parameter_4kbyte_erase */ +#define XXXXXXXXX_PP_4BYTE_ADDR (0x12U) /* page_program_4byte_addr */ +#define XXXXXXXXX_READ_ANY_REG (0x05U) /* READ STATUS, read_any_register */ +#define XXXXXXXXX_READ_STATUS (0x2BU) /* RDSCUR, read_stts_register */ +#define XXXXXXXXX_WRITE_ENABLE (0x06U) /* WREN, write_enable */ +#define XXXXXXXXX_READ_32BIT_ADDR (0x13U) /* read 32bit address */ +#define XXXXXXXXX_DDR_QUAD_IO_READ_32BIT_ADDR (0xEEU) /* DDR quad I/O read 32bit address */ +#endif /* USER_ADDED_QSPI == 1 */ + +static const st_qspi_cmd_tbl_t qspi_cmd_tbls[VENDOR_NUM] = +{ + /* Command table for MT25QU01GB */ + { + MT25QU01GB_READ_FAST, /* read_fast */ + MT25QU01GB_SEC_ER_4BYTE_ADDR, /* sector_erase_4byte_addr */ + MT25QU01GB_PARA_4KBYTE_ER, /* parameter_4kbyte_erase */ + MT25QU01GB_PP_4BYTE_ADDR, /* pp_4byte_addr */ + MT25QU01GB_READ_ANY_REG, /* read_any_register */ + MT25QU01GB_READ_STATUS, /* read_status */ + MT25QU01GB_WRITE_ENABLE, /* write_enable */ + S25FS512S_READ_32BIT_ADDR, /* read 32bit address */ + S25FS512S_DDR_QUAD_IO_READ_32BIT_ADDR /* DDR quad I/O read 32bit address */ + }, +#if USER_ADDED_QSPI == 1 + /* Command table for XXXXXXXXX */ + /* User can customize for another vendor's QSPI Flash. */ + { + XXXXXXXXX_READ_FAST, /* read_fast */ + XXXXXXXXX_SEC_ER_4BYTE_ADDR, /* sector_erase_4byte_addr */ + XXXXXXXXX_PARA_4KBYTE_ER, /* parameter_4kbyte_erase */ + XXXXXXXXX_PP_4BYTE_ADDR, /* pp_4byte_addr */ + XXXXXXXXX_READ_ANY_REG, /* read_any_register */ + XXXXXXXXX_READ_STATUS, /* read_status */ + XXXXXXXXX_WRITE_ENABLE, /* write_enable */ + XXXXXXXXX_READ_32BIT_ADDR, /* read 32bit address */ + XXXXXXXXX_DDR_QUAD_IO_READ_32BIT_ADDR /* DDR quad I/O read 32bit address */ + } +#endif /* USER_ADDED_QSPI == 1 */ +}; + +static const uint32_t dev_id_index[VENDOR_NUM] = +{ + /* QSPI Flash device ID */ + DEVID_MT25QU01GB, /* MT25QU01GB */ +#if USER_ADDED_QSPI == 1 + /* User can customize for another vendor's QSPI Flash. */ + DEVID_XXXXXXXXX +#endif /* USER_ADDED_QSPI == 1 */ +}; + +const st_qspi_cmd_tbl_t* gp_qspi_cmd_tbl; + +static void rpc_save_hw_init_val(void); +static uint32_t init_qspi_cmd(uint32_t device_id); + +void rpc_init(void) +{ + /* Save HW initial value of RPC registers */ + rpc_save_hw_init_val(); +} + +void qspi_flash_rw_init(void) +{ + uint32_t reg; + uint32_t qspi_flash_id; + uint32_t rtn_val; + static bool qspi_flash_id_checked = false; + + if (qspi_flash_id_checked == true) + { + NOTICE("QSPI Flash ID has been checked.\n"); + return; + } + qspi_flash_id_checked = true; + + /* judge boot device */ + reg = (mem_read32(RST_MODEMR0) & RST_MODEMR0_BOOTMODE) >> 1U; + + if ((reg == BOOTMODE_QSPI_SINGLE_40MHZ) || + (reg == BOOTMODE_QSPI_DMA)) + { + /* check the transfer end flag */ + rpc_end_state_check(); + + /* Initialize command for QSPI Flash. */ + read_qspi_flash_id(&qspi_flash_id); + qspi_flash_id = (qspi_flash_id & DEVICE_ID_MASK); + NOTICE("QSPI Flash ID = 0x%08x\n", qspi_flash_id); + rtn_val = init_qspi_cmd(qspi_flash_id); + if(rtn_val != QSPI_CMD_INIT_SUCCESS) + { + /* unknown QSPI Flash ID */ + ERROR("QSPI Flash command initialization error!!\n"); + panic; + } + +#if (QSPI_DDR_MODE==1) + /* Initialize for QSPI DDR transfer mode */ + qspi_ddr_transfer_mode(gp_qspi_cmd_tbl->ddr_quad_io_read_32bit_addr); +#else + /* Initialize for QSPI SDR transfer mode */ + qspi_sdr_transfer_mode(gp_qspi_cmd_tbl->read_32bit_addr); +#endif + } +} +/* End of function rpc_init(void) */ + +void rpc_release(void) +{ + uint32_t loop; + + /* Set HW initial value to RPC registers */ + for(loop = 0; loop < RPC_TBL_MAX; loop++) + { + mem_write32(g_rpc_reg_hwinit_val_tbl[loop].reg_addr, g_rpc_reg_hwinit_val_tbl[loop].value); + } +} +/* End of function rpc_release(void) */ + +void rpc_end_state_check(void) +{ + /* Wait until RPC data transfer is completed */ + while ((mem_read32(RPC_CMNSR) & CMNSR_TEND) != 1U) + { + ; + } +} +/* End of function rpc_end_state_check(void) */ + + +static void rpc_save_hw_init_val(void) +{ + uint32_t loop; + + g_rpc_reg_hwinit_val_tbl[0].reg_addr = RPC_CMNCR; + g_rpc_reg_hwinit_val_tbl[1].reg_addr = RPC_DRCR; + g_rpc_reg_hwinit_val_tbl[2].reg_addr = RPC_DRCMR; + g_rpc_reg_hwinit_val_tbl[3].reg_addr = RPC_DREAR; + g_rpc_reg_hwinit_val_tbl[4].reg_addr = RPC_DRENR; + g_rpc_reg_hwinit_val_tbl[5].reg_addr = RPC_SMCR; + g_rpc_reg_hwinit_val_tbl[6].reg_addr = RPC_SMCMR; + g_rpc_reg_hwinit_val_tbl[7].reg_addr = RPC_SMENR; + /* RPC_SMRDR0 is Read only */ + /* RPC_CMNSR is Read only */ + g_rpc_reg_hwinit_val_tbl[8].reg_addr = RPC_DRDMCR; + g_rpc_reg_hwinit_val_tbl[9].reg_addr = RPC_DRDRENR; + g_rpc_reg_hwinit_val_tbl[10].reg_addr = RPC_SMDRENR; + g_rpc_reg_hwinit_val_tbl[11].reg_addr = RPC_PHYCNT; + g_rpc_reg_hwinit_val_tbl[12].reg_addr = RPC_PHYOFFSET1; + + /* Save RPC register initial value */ + for(loop = 0; loop < RPC_TBL_MAX; loop++) + { + g_rpc_reg_hwinit_val_tbl[loop].value = mem_read32(g_rpc_reg_hwinit_val_tbl[loop].reg_addr); + } +} + +uint8_t prk3_rev = 3; +static uint32_t init_qspi_cmd(uint32_t device_id) +{ + uint32_t i = 0U; + uint32_t rtn_val = QSPI_CMD_INIT_ERROR; + + gp_qspi_cmd_tbl = NULL; + + for (i = 0U; i < VENDOR_NUM; i++) + { + if (device_id == dev_id_index[i]) + { + gp_qspi_cmd_tbl = &qspi_cmd_tbls[i]; + if (device_id == DEVID_XXXXXXXXX) + prk3_rev = 4; + rtn_val = QSPI_CMD_INIT_SUCCESS; + break; + } + } + return rtn_val; +} + +int check_Erase_Fail(uint32_t status) { + if (prk3_rev <= 3) + return (status & BIT5); + return (status & BIT6); +} +/* End of function init_qspi_cmd(uint32_t device_id) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/rpcqspidrv.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/rpcqspidrv.c new file mode 100644 index 0000000..d4ba398 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/rpcqspidrv.c @@ -0,0 +1,809 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2015-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RPC driver for QSPI Flash + ******************************************************************************/ +/****************************************************************************** + * @file rpcqspidrv.c + * - Version : 0.07 + * @brief RPC driver for QSPI Flash. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 15.10.2021 0.01 First Release + * : 16.02.2022 0.02 Modify how to write to RPC_WRBUF register. + * : 15.03.2022 0.03 Modify to use inline function in mem_io.h + * : when access to register. + * : 18.03.2022 0.04 Modify to read modify write when write to + * : register. + * : 23.03.2022 0.05 Modify command for QSPI Flash to refer to + * : command table. + * : 01.04.2022 0.06 Modify magic number to definition. + * : 09.11.2022 0.07 License notation change. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dma2.h" + +static uint32_t read_register_qspi_flash(uint32_t cmd, uint32_t *readData); + +void init_rpc_qspi_flash_4fastread_ext_mode(void) +{ + uint32_t reg; + + reg = mem_read32(RPC_PHYCNT); + reg |= (RPC_PHYCNT_STRTIM3 + | RPC_PHYCNT_STRTIM2 + | RPC_PHYCNT_STRTIM1 + | RPC_PHYCNT_STRTIM0); + reg &= ~(RPC_PHYCNT_HS + | RPC_PHYCNT_WBUF2 + | RPC_PHYCNT_WBUF + | RPC_PHYCNT_PHYMEM_HYP); + mem_write32(RPC_PHYCNT, reg); + reg |= RPC_PHYCNT_CAL; + mem_write32(RPC_PHYCNT, reg); + + reg = mem_read32(RPC_CMNCR); + reg &= ~(CMNCR_MD_MANUAL /* External address space read mode */ + | CMNCR_BSZ_MASK); /* Data Bus Size: Serial flash memory x 1*/ + reg |= (CMNCR_MOIIO3_HIZ + | CMNCR_MOIIO2_HIZ + | CMNCR_MOIIO1_HIZ + | CMNCR_MOIIO0_HIZ + | CMNCR_IO0FV_HIZ); + mem_write32(RPC_CMNCR, reg); + /* bit31 MD = 0 : External address space read mode */ + /* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */ + + reg = mem_read32(RPC_DRCR); + reg &= ~(DRCR_SSLN + | DRCR_RCF + | DRCR_SSLE); + reg |= (DRCR_RBURST_32UNITS + | DRCR_RBE_BURST); + mem_write32(RPC_DRCR, reg); + /* bit20-16 RBURST[4:0] = 11111 : 32 continuous data unit */ + /* bit8 RBE = 1 : Burst read */ + + reg = mem_read32(RPC_DRCMR); + reg &= ~(DRCMR_CMD_MASK + | DRCMR_OCMD_MASK); + reg |= ((gp_qspi_cmd_tbl -> read_fast) << DRCMR_SMCMR_CMD_SHIFT); + mem_write32(RPC_DRCMR, reg); + /* bit23-16 CMD[7:0] = 0x0C : 4FAST_READ 0Ch Command 4-byte address command */ + + reg = mem_read32(RPC_DREAR); + reg &= ~(DREAR_EAV_MASK + | DREAR_EAC_MASK); + reg |= DREAR_EAC_26BITS; + mem_write32(RPC_DREAR, reg); + /* bit23-16 EAV[7:0] = 0 : ADR[32:26] output set0 */ + /* bit2-0 EAC[2:0] = 001 : ADR[25:0 ] Enable */ + + reg = mem_read32(RPC_DRENR); + reg &= ~(DRENR_CDB_MASK + | DRENR_OCDB_MASK + | DRENR_ADB_MASK + | DRENR_OPDB_MASK + | DRENR_DRDB_MASK + | DRENR_OCDE_EN + | DRENR_ADE_MASK + | DRENR_OPDE_MASK); + reg |= (DRENR_DME_EN + | DRENR_CDE_EN + | DRENR_ADE_ONE_SERIAL); + mem_write32(RPC_DRENR, reg); + /* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */ + /* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */ + /* bit17-16 DRDB[1:0] = 00 : 1bit width transfer data (QSPI0_IO0) */ + /* bit15 DME = 1 : dummy cycle enable */ + /* bit14 CDE = 1 : Command enable */ + /* bit11-8 ADE[3:0] = 1111 : ADR[31:0] output (32 Bit Address) */ + + reg = mem_read32(RPC_DRDMCR); + reg &= ~(DRDMCR_DMCYC_MASK); + reg |= DRDMCR_DMCYC_8; + mem_write32(RPC_DRDMCR, reg); + /* bit2-0 DMCYC[2:0] = 111 : 8 cycle dummy wait */ + + reg = mem_read32(RPC_DRDRENR); + reg &= ~(DRDRENR_HYPE_MASK + | DRDRENR_ADDRE + | DRDRENR_OPDRE + | DRDRENR_DRDRE); + mem_write32(RPC_DRDRENR, reg); + /* bit8 ADDRE = 0 : Address SDR transfer */ + /* bit0 DRDRE = 0 : DATA SDR transfer */ +} +/* End of function init_rpc_qspi_flash_4fastread_ext_mode */ + +void init_rpc_qspi_flash(void) +{ + uint32_t reg; + + power_on_rpc(); + + set_rpc_clock_mode(RPC_CLK_80M); + reset_rpc(); + set_rpc_ssl_delay(); + + reg = mem_read32(RPC_OFFSET1); + reg &= ~(PHYOFFSET1_MASK); + reg |= PHYOFFSET1_DMA_QSPI; + mem_write32(RPC_OFFSET1, reg); +} +/* End of function init_rpc_qspi_flash */ + +/* 4SE DCh 4-byte address */ +void sector_erase_4byte_qspi_flash(uint32_t sector_addr) +{ + uint32_t reg; + + reg = mem_read32(RPC_PHYCNT); + reg |= (RPC_PHYCNT_CAL + | RPC_PHYCNT_STRTIM3 + | RPC_PHYCNT_STRTIM2 + | RPC_PHYCNT_STRTIM1 + | RPC_PHYCNT_STRTIM0); + reg &= ~(RPC_PHYCNT_HS + | RPC_PHYCNT_WBUF2 + | RPC_PHYCNT_WBUF + | RPC_PHYCNT_PHYMEM_HYP); + mem_write32(RPC_PHYCNT, reg); + /* bit31 CAL = 1 : PHY calibration */ + /* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */ + + reg = mem_read32(RPC_CMNCR); + reg &= ~(CMNCR_BSZ_MASK); + reg |= (CMNCR_MD_MANUAL + | CMNCR_MOIIO3_HIZ + | CMNCR_MOIIO2_HIZ + | CMNCR_MOIIO1_HIZ + | CMNCR_MOIIO0_HIZ + | CMNCR_IO0FV_HIZ); + mem_write32(RPC_CMNCR, reg); + /* bit31 MD = 1 : Manual mode */ + /* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */ + + reg = mem_read32(RPC_SMCMR); + reg &= ~(SMCMR_CMD_MASK + | SMCMR_OCMD_MASK); + reg |= ((gp_qspi_cmd_tbl -> sector_erase_4byte_addr) << DRCMR_SMCMR_CMD_SHIFT); + mem_write32(RPC_SMCMR, reg); + /* bit23-16 CMD[7:0] = 0xDC : Sector Erase 4-byte address command */ + + mem_write32(RPC_SMADR, sector_addr); + + reg = mem_read32(RPC_SMDRENR); + reg &= ~(SMDRENR_HYPE_MASK + | SMDRENR_ADDRE + | SMDRENR_OPDRE + | SMDRENR_SPIDRE); + mem_write32(RPC_SMDRENR, reg); + /* bit8 ADDRE = 0 : Address SDR transfer */ + /* bit0 SPIDRE = 0 : DATA SDR transfer */ + + reg = mem_read32(RPC_SMENR); + reg &= ~(SMENR_CDB_MASK + | SMENR_OCDB_MASK + | SMENR_ADB_MASK + | SMENR_OPDB_MASK + | SMENR_SPIDB_MASK + | SMENR_DME_EN + | SMENR_OCDE_EN + | SMENR_ADE_MASK + | SMENR_OPDE_MASK + | SMENR_SPIDE_MASK); + reg |= (SMENR_CDE_EN + | SMENR_ADE_SERIAL_31); + mem_write32(RPC_SMENR, reg); + /* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */ + /* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */ + /* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */ + /* bit15 DME = 0 : No dummy cycle */ + /* bit14 CDE = 1 : Command enable */ + /* bit11-8 ADE[3:0] = 1111 : ADR[31:0] output (32 Bit Address) */ + /* bit3-0 SPIDE[3:0] = 0000 : No transfer */ + + reg = mem_read32(RPC_SMCR); + reg &= ~(SMCR_SSLKP + | SMCR_SPIRE + | SMCR_SPIWE); + reg |= SMCR_SPIE; + mem_write32(RPC_SMCR, reg); + /* bit2 SPIRE = 0 : Data read disable */ + /* bit1 SPIWE = 0 : Data write disable */ + /* bit0 SPIE = 1 : SPI transfer start */ + + wait_rpc_tx_end(); +} +/* End of function sector_erase_4byte_qspi_flash */ + +/* 4P4E 21h 4-byte address */ +void parameter_sector_erase_4kb_qspi_flash(uint32_t sector_addr) +{ + uint32_t reg; + + reg = mem_read32(RPC_PHYCNT); + reg |= (RPC_PHYCNT_CAL + | RPC_PHYCNT_STRTIM3 + | RPC_PHYCNT_STRTIM2 + | RPC_PHYCNT_STRTIM1 + | RPC_PHYCNT_STRTIM0); + reg &= ~(RPC_PHYCNT_HS + | RPC_PHYCNT_WBUF2 + | RPC_PHYCNT_WBUF + | RPC_PHYCNT_PHYMEM_HYP); + mem_write32(RPC_PHYCNT, reg); + /* bit31 CAL = 1 : PHY calibration */ + /* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */ + + reg = mem_read32(RPC_CMNCR); + reg &= ~(CMNCR_BSZ_MASK); + reg |= (CMNCR_MD_MANUAL + | CMNCR_MOIIO3_HIZ + | CMNCR_MOIIO2_HIZ + | CMNCR_MOIIO1_HIZ + | CMNCR_MOIIO0_HIZ + | CMNCR_IO0FV_HIZ); + mem_write32(RPC_CMNCR, reg); + /* bit31 MD = 1 : Manual mode */ + /* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */ + + reg = mem_read32(RPC_SMCMR); + reg &= ~(SMCMR_CMD_MASK + | SMCMR_OCMD_MASK); + reg |= ((gp_qspi_cmd_tbl -> parameter_4kbyte_erase) << DRCMR_SMCMR_CMD_SHIFT); + mem_write32(RPC_SMCMR, reg); + /* bit23-16 CMD[7:0] = 0x21 : Parameter 4-kB Sector Erasecommand */ + + mem_write32(RPC_SMADR, sector_addr); + + reg = mem_read32(RPC_SMDRENR); + reg &= ~(SMDRENR_HYPE_MASK + | SMDRENR_ADDRE + | SMDRENR_OPDRE + | SMDRENR_SPIDRE); + mem_write32(RPC_SMDRENR, reg); + /* bit8 ADDRE = 0 : Address SDR transfer */ + /* bit0 SPIDRE = 0 : DATA SDR transfer */ + + reg = mem_read32(RPC_SMENR); + reg &= ~(SMENR_CDB_MASK + | SMENR_OCDB_MASK + | SMENR_ADB_MASK + | SMENR_OPDB_MASK + | SMENR_SPIDB_MASK + | SMENR_DME_EN + | SMENR_OCDE_EN + | SMENR_ADE_MASK + | SMENR_OPDE_MASK + | SMENR_SPIDE_MASK); + reg |= (SMENR_CDE_EN + | SMENR_ADE_SERIAL_31); + mem_write32(RPC_SMENR, reg); + /* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */ + /* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */ + /* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */ + /* bit15 DME = 0 : No dummy cycle */ + /* bit14 CDE = 1 : Command enable */ + /* bit11-8 ADE[3:0] = 1111 : ADR[31:0] output (32 Bit Address) */ + /* bit3-0 SPIDE[3:0] = 0000 : No transfer */ + + reg = mem_read32(RPC_SMCR); + reg &= ~(SMCR_SSLKP + | SMCR_SPIRE + | SMCR_SPIWE); + reg |= SMCR_SPIE; + mem_write32(RPC_SMCR, reg); + /* bit2 SPIRE = 0 : Data read disable */ + /* bit1 SPIWE = 0 : Data write disable */ + /* bit0 SPIE = 1 : SPI transfer start */ + + wait_rpc_tx_end(); +} +/* End of function parameter_sector_erase_4kb_qspi_flash */ + +/* Page Program (4PP:12h) 4-byte address */ +void write_data_4pp_with_buf_qspi_flash(uint32_t addr, uint32_t source_addr) +{ + uintptr_t i=0; + uint32_t reg; + + reg = mem_read32(RPC_DRCR); + reg |= (DRCR_SSLN + | DRCR_RBURST_32UNITS + | DRCR_RCF + | DRCR_RBE_BURST + | DRCR_SSLE); + mem_write32(RPC_DRCR, reg); + /* bit9 RCF = 1 : Read Cache Clear */ + + reg = mem_read32(RPC_PHYCNT); + reg |= (RPC_PHYCNT_CAL + | RPC_PHYCNT_STRTIM3 + | RPC_PHYCNT_STRTIM2 + | RPC_PHYCNT_STRTIM1 + | RPC_PHYCNT_STRTIM0 + | RPC_PHYCNT_WBUF2 + | RPC_PHYCNT_WBUF); + reg &= ~(RPC_PHYCNT_HS + | RPC_PHYCNT_PHYMEM_HYP); + mem_write32(RPC_PHYCNT, reg); + /* bit31 CAL = 1 : PHY calibration */ + /* bit2 WBUF = 1 : Write Buffer Enable */ + /* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */ + + for(i = 0; i < RPC_WRITE_BUF_SIZE; i = i + TRANS_SIZE_64BYTE) + { + dma2_start_xbyte(RPC_WRBUF_PHYS+i, source_addr+i, TRANS_SIZE_64BYTE, TRANS_UNIT_64BYTES); + dma2_end(); + // dma_trans_start(RPC_WRBUF_PHYS+i, source_addr+i, TRANS_SIZE_64BYTE); + // dma_trans_end_check(); + } + + reg = mem_read32(RPC_CMNCR); + reg &= ~(CMNCR_BSZ_MASK); + reg |= (CMNCR_MD_MANUAL + | CMNCR_MOIIO3_HIZ + | CMNCR_MOIIO2_HIZ + | CMNCR_MOIIO1_HIZ + | CMNCR_MOIIO0_HIZ + | CMNCR_IO0FV_HIZ); + mem_write32(RPC_CMNCR, reg); + /* bit31 MD = 1 : Manual mode */ + /* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */ + + reg = mem_read32(RPC_SMCMR); + reg &= ~(SMCMR_CMD_MASK + | SMCMR_OCMD_MASK); + reg |= ((gp_qspi_cmd_tbl -> pp_4byte_addr) << DRCMR_SMCMR_CMD_SHIFT); + mem_write32(RPC_SMCMR, reg); + /* bit23-16 CMD[7:0] = 0x12 : Page Program 4-byte address */ + + mem_write32(RPC_SMADR, addr); + + reg = mem_read32(RPC_SMDRENR); + reg &= ~(SMDRENR_HYPE_MASK + | SMDRENR_ADDRE + | SMDRENR_OPDRE + | SMDRENR_SPIDRE); + mem_write32(RPC_SMDRENR, reg); + /* bit8 ADDRE = 0 : Address SDR transfer */ + /* bit0 SPIDRE = 0 : DATA SDR transfer */ + + reg = mem_read32(RPC_SMENR); + reg &= ~(SMENR_CDB_MASK + | SMENR_OCDB_MASK + | SMENR_ADB_MASK + | SMENR_OPDB_MASK + | SMENR_SPIDB_MASK + | SMENR_DME_EN + | SMENR_OCDE_EN + | SMENR_ADE_MASK + | SMENR_OPDE_MASK + | SMENR_SPIDE_MASK); + reg |= (SMENR_CDE_EN + | SMENR_ADE_SERIAL_31 + | SMENR_SPIDE_SPI_32); + mem_write32(RPC_SMENR, reg); + /* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */ + /* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */ + /* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */ + /* bit15 DME = 0 : No dummy cycle */ + /* bit14 CDE = 1 : Command enable */ + /* bit11-8 ADE[3:0] = 1111 : ADR[31:0] is output */ + /* bit3-0 SPIDE[3:0] = 1111 : 32bit transfer */ + + reg = mem_read32(RPC_SMCR); + reg &= ~(SMCR_SSLKP + | SMCR_SPIRE); + reg |= (SMCR_SPIWE + | SMCR_SPIE); + mem_write32(RPC_SMCR, reg); + /* bit2 SPIRE = 0 : Data read disable */ + /* bit1 SPIWE = 1 : Data write enable */ + /* bit0 SPIE = 1 : SPI transfer start */ + + wait_rpc_tx_end(); + + reg = mem_read32(RPC_PHYCNT); + reg |= (RPC_PHYCNT_STRTIM3 + | RPC_PHYCNT_STRTIM2 + | RPC_PHYCNT_STRTIM1 + | RPC_PHYCNT_STRTIM0 + | RPC_PHYCNT_WBUF2); + reg &= ~(RPC_PHYCNT_HS + | RPC_PHYCNT_WBUF + | RPC_PHYCNT_PHYMEM_HYP); + mem_write32(RPC_PHYCNT, reg); + /* bit31 CAL = 0 : No PHY calibration */ + /* bit2 WBUF = 0 : Write Buffer Disable */ + /* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */ + + reg = mem_read32(RPC_DRCR); + reg |= (DRCR_SSLN + | DRCR_RBURST_32UNITS + | DRCR_RCF + | DRCR_RBE_BURST + | DRCR_SSLE); + mem_write32(RPC_DRCR, reg); + /* bit9 RCF = 1 : Read Cache Clear */ +} +/* End of function write_data_4pp_with_buf_qspi_flash */ + +/* OnBoard QspiFlash(MT25QU01GB) */ +uint32_t read_wip_status_register(uint32_t *readData) /* for QSPIx1ch */ +{ + return read_register_qspi_flash(gp_qspi_cmd_tbl -> read_any_register, readData); +} + +#define RDCR_cmd 0x15 +uint32_t read_configuration_register(uint32_t *readData) /* for QSPIx1ch */ +{ + return read_register_qspi_flash(RDCR_cmd, readData); +} + +#define WRSR_cmd 0x01 +void write_status_register(uint16_t stat_conf) +{ + uint32_t reg; + + reg = mem_read32(RPC_PHYCNT); + reg |= (RPC_PHYCNT_CAL + | RPC_PHYCNT_STRTIM3 + | RPC_PHYCNT_STRTIM2 + | RPC_PHYCNT_STRTIM1 + | RPC_PHYCNT_STRTIM0); + reg &= ~(RPC_PHYCNT_HS + | RPC_PHYCNT_WBUF2 + | RPC_PHYCNT_WBUF + | RPC_PHYCNT_PHYMEM_HYP); + mem_write32(RPC_PHYCNT, reg); + /* bit31 CAL = 1 : PHY calibration */ + /* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */ + + reg = mem_read32(RPC_CMNCR); + reg &= ~(CMNCR_BSZ_MASK); + reg |= (CMNCR_MD_MANUAL + | CMNCR_MOIIO3_HIZ + | CMNCR_MOIIO2_HIZ + | CMNCR_MOIIO1_HIZ + | CMNCR_MOIIO0_HIZ + | CMNCR_IO0FV_HIZ); + mem_write32(RPC_CMNCR, reg); + /* bit31 MD = 1 : Manual mode */ + /* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */ + + reg = mem_read32(RPC_SMCMR); + reg &= ~(SMCMR_CMD_MASK + | SMCMR_OCMD_MASK); + reg |= ((WRSR_cmd) << DRCMR_SMCMR_CMD_SHIFT); + mem_write32(RPC_SMCMR, reg); + /* bit23-16 CMD[7:0] = 0x01 : write status/configuration register command */ + + reg = mem_read32(RPC_SMENR); + reg &= ~(SMENR_CDB_MASK + | SMENR_OCDB_MASK + | SMENR_ADB_MASK + | SMENR_OPDB_MASK + | SMENR_SPIDB_MASK + | SMENR_DME_EN + | SMENR_OCDE_EN + | SMENR_ADE_MASK + | SMENR_OPDE_MASK + | SMENR_SPIDE_MASK); + reg |= (SMENR_CDE_EN + | SMENR_SPIDE_SPI_16); + mem_write32(RPC_SMENR, reg); + /* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */ + /* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */ + /* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */ + /* bit15 DME = 0 : No dummy cycle */ + /* bit14 CDE = 1 : Command enable */ + /* bit11-8 ADE[3:0] = 0000 : Address output disable */ + /* bit3-0 SPIDE[3:0] = 1100 : 16bit transfer */ + + mem_write16(RPC_SMWDR0, stat_conf); + + reg = mem_read32(RPC_SMCR); + reg &= ~(SMCR_SSLKP + | SMCR_SPIRE); + reg |= (SMCR_SPIWE + | SMCR_SPIE); + mem_write32(RPC_SMCR, reg); + /* bit2 SPIRE = 0 : Data read disable */ + /* bit1 SPIWE = 1 : Data write enable */ + /* bit0 SPIE = 1 : SPI transfer start */ + + wait_rpc_tx_end(); +} + +void set_rpc_clock_mode(uint32_t mode) +{ + uint32_t dataL=0; + uint32_t reg; + + if(mode == RPC_CLK_160M){ + dataL = RPCCKCR_RPCFC_160M; /* RPC clock 160MHz */ + }else if(mode == RPC_CLK_80M){ + dataL = RPCCKCR_RPCFC_80M; /* RPC clock 80MHz */ + }else{ + dataL = RPCCKCR_RPCFC_40M; /* RPC clock 40MHz */ + } + + reg = mem_read32(CPG_RPCCKCR); + reg &= ~(RPCCKCR_RPCFC_MASK); + dataL |= reg; + mem_write32(CPG_CPGWPR, ~dataL); + mem_write32(CPG_RPCCKCR, dataL); + + (void)mem_read32(CPG_RPCCKCR); /* dummy read */ +} +/* End of function set_rpc_clock_mode */ + +void wait_rpc_tx_end(void) +{ + uint32_t dataL=0; + + while(1) + { + wdt_restart(); + dataL = mem_read32(RPC_CMNSR); + if(dataL & BIT0) break; + /* Wait for TEND = 1 */ + } +} +/* End of function wait_rpc_tx_end */ + +void reset_rpc(void) +{ + mem_write32(CPG_CPGWPR, ~BIT29); + mem_write32(CPG_SRCR6, BIT29); + /* wait: tRLRH Reset# low pulse width 10us */ + micro_wait(20); /* wait 20us */ + + mem_write32(CPG_CPGWPR, ~BIT29); + mem_write32(CPG_SRSTCLR6, BIT29); + /* wait: tREADY1(35us) - tRHSL(10us) = 25us */ + micro_wait(40); /* wait 40us */ +} +/* End of function reset_rpc */ + +void set_rpc_ssl_delay(void) +{ + uint32_t reg; + + reg = mem_read32(RPC_SSLDR); + reg |= SSLDR_SLNDL; + mem_write32(RPC_SSLDR, reg); + /* bit10-8 SLNDL[2:0] = 100 : 5.5 cycles of QSPIn_SPCLK */ +} +/* End of function set_rpc_ssl_delay */ + +void power_on_rpc(void) +{ + uint32_t dataL=0; + dataL = mem_read32(CPG_MSTPSR6); + if(dataL & BIT29){ /* case RPC(QSPI) Standby */ + dataL &= ~BIT29; + mem_write32(CPG_CPGWPR, ~dataL); + mem_write32(CPG_MSTPCR6, dataL); + while( BIT29 & mem_read32(CPG_MSTPSR6) ); /* wait bit=0 */ + } +} +/* End of function power_on_rpc */ + +uint32_t read_qspi_flash_id(uint32_t *readData) /* for QSPIx1ch */ +{ + return read_register_qspi_flash(FLASH_CMD_READ_ID, readData); +} + +uint32_t read_status_qspi_flash(uint32_t *readData) { + return read_register_qspi_flash(gp_qspi_cmd_tbl -> read_stts_register, readData); +} + +static uint32_t read_register_qspi_flash(uint32_t cmd, uint32_t *readData) /* for QSPIx1ch */ +{ + uint32_t reg; + + reg = mem_read32(RPC_PHYCNT); + reg |= (RPC_PHYCNT_STRTIM3 + | RPC_PHYCNT_STRTIM2 + | RPC_PHYCNT_STRTIM1 + | RPC_PHYCNT_STRTIM0); + reg &= ~(RPC_PHYCNT_HS + | RPC_PHYCNT_WBUF2 + | RPC_PHYCNT_WBUF + | RPC_PHYCNT_PHYMEM_HYP); + mem_write32(RPC_PHYCNT, reg); + reg |= RPC_PHYCNT_CAL; + mem_write32(RPC_PHYCNT, reg); + /* bit31 CAL = 1 : PHY calibration */ + /* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */ + + reg = mem_read32(RPC_CMNCR); + reg &= ~(CMNCR_BSZ_MASK); + reg |= (CMNCR_MD_MANUAL + | CMNCR_MOIIO3_HIZ + | CMNCR_MOIIO2_HIZ + | CMNCR_MOIIO1_HIZ + | CMNCR_MOIIO0_HIZ + | CMNCR_IO0FV_HIZ); + mem_write32(RPC_CMNCR, reg); + /* bit31 MD = 1 : Manual mode */ + /* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */ + + reg = mem_read32(RPC_SMCMR); + reg &= ~(SMCMR_CMD_MASK + | SMCMR_OCMD_MASK); + reg |= ((cmd) << DRCMR_SMCMR_CMD_SHIFT); + mem_write32(RPC_SMCMR, reg); + /* bit23-16 CMD[7:0] = 0x05 : Status Read command (for Palladium QSPI model) */ + + reg = mem_read32(RPC_SMDRENR); + reg &= ~(SMDRENR_HYPE_MASK + | SMDRENR_ADDRE + | SMDRENR_OPDRE + | SMDRENR_SPIDRE); + mem_write32(RPC_SMDRENR, reg); + /* bit8 ADDRE = 0 : Address SDR transfer */ + /* bit0 SPIDRE = 0 : DATA SDR transfer */ + + reg = mem_read32(RPC_SMENR); + reg &= ~(SMENR_CDB_MASK + | SMENR_OCDB_MASK + | SMENR_ADB_MASK + | SMENR_OPDB_MASK + | SMENR_SPIDB_MASK + | SMENR_DME_EN + | SMENR_OCDE_EN + | SMENR_ADE_MASK + | SMENR_OPDE_MASK + | SMENR_SPIDE_MASK); + reg |= (SMENR_CDE_EN + | SMENR_SPIDE_SPI_32); + mem_write32(RPC_SMENR, reg); + /* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */ + /* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */ + /* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */ + /* bit15 DME = 0 : No dummy cycle */ + /* bit14 CDE = 1 : Command enable */ + /* bit11-8 ADE[3:0] = 0000 : Address output disable */ + /* bit3-0 SPIDE[3:0] = 1111 : 32bit transfer */ + + reg = mem_read32(RPC_SMCR); + reg &= ~(SMCR_SSLKP + | SMCR_SPIWE); + reg |= (SMCR_SPIRE + | SMCR_SPIE); + mem_write32(RPC_SMCR, reg); + /* bit2 SPIRE = 1 : Data read enable */ + /* bit1 SPIWE = 0 : Data write disable */ + /* bit0 SPIE = 1 : SPI transfer start */ + + wait_rpc_tx_end(); + + readData[0] = mem_read32(RPC_SMRDR0); /* read data[31:0] */ + + return(readData[0]); +} +/* End of function read_register_qspi_flash */ + +void write_command_qspi_flash(uint32_t command) /* for QSPIx1ch */ +{ + uint32_t reg; + + reg = mem_read32(RPC_PHYCNT); + reg |= (RPC_PHYCNT_CAL + | RPC_PHYCNT_STRTIM3 + | RPC_PHYCNT_STRTIM2 + | RPC_PHYCNT_STRTIM1 + | RPC_PHYCNT_STRTIM0); + reg &= ~(RPC_PHYCNT_HS + | RPC_PHYCNT_WBUF2 + | RPC_PHYCNT_WBUF + | RPC_PHYCNT_PHYMEM_HYP); + mem_write32(RPC_PHYCNT, reg); + /* bit31 CAL = 1 : PHY calibration */ + /* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */ + + reg = mem_read32(RPC_CMNCR); + reg &= ~(CMNCR_BSZ_MASK); + reg |= (CMNCR_MD_MANUAL + | CMNCR_MOIIO3_HIZ + | CMNCR_MOIIO2_HIZ + | CMNCR_MOIIO1_HIZ + | CMNCR_MOIIO0_HIZ + | CMNCR_IO0FV_HIZ); + mem_write32(RPC_CMNCR, reg); + /* bit31 MD = 1 : Manual mode */ + /* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */ + + reg = mem_read32(RPC_SMCMR); + reg &= ~(SMCMR_CMD_MASK + | SMCMR_OCMD_MASK); + reg |= (command & (SMCMR_CMD_MASK | SMCMR_OCMD_MASK)); + mem_write32(RPC_SMCMR, reg); + /* bit23-16 CMD[7:0] : command */ + + reg = mem_read32(RPC_SMDRENR); + reg &= ~(SMDRENR_HYPE_MASK + | SMDRENR_ADDRE + | SMDRENR_OPDRE + | SMDRENR_SPIDRE); + mem_write32(RPC_SMDRENR, reg); + /* bit8 ADDRE = 0 : Address SDR transfer */ + /* bit0 SPIDRE = 0 : DATA SDR transfer */ + + reg = mem_read32(RPC_SMENR); + reg &= ~(SMENR_CDB_MASK + | SMENR_OCDB_MASK + | SMENR_ADB_MASK + | SMENR_OPDB_MASK + | SMENR_SPIDB_MASK + | SMENR_DME_EN + | SMENR_OCDE_EN + | SMENR_ADE_MASK + | SMENR_ADE_MASK + | SMENR_OPDE_MASK + | SMENR_SPIDE_MASK); + reg |= SMENR_CDE_EN; + mem_write32(RPC_SMENR, reg); + /* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */ + /* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */ + /* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */ + /* bit15 DME = 0 : No dummy cycle */ + /* bit14 CDE = 1 : Command enable */ + /* bit11-8 ADE[3:0] = 0000 : Address output disable */ + /* bit3-0 SPIDE[3:0] = 0000 : No transfer */ + + reg = mem_read32(RPC_SMCR); + reg &= ~(SMCR_SSLKP + | SMCR_SPIRE + | SMCR_SPIWE); + reg |= SMCR_SPIE; + mem_write32(RPC_SMCR, reg); + /* bit2 SPIRE = 0 : Data read disable */ + /* bit1 SPIWE = 0 : Data write disable */ + /* bit0 SPIE = 1 : SPI transfer start */ + + wait_rpc_tx_end(); + +} +/* End of function write_command_qspi_flash */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/spiflash2drv.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/spiflash2drv.c new file mode 100644 index 0000000..31359fc --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rpc/spiflash2drv.c @@ -0,0 +1,213 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2020-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : QSPI Flash driver for S25FS512S + ******************************************************************************/ +/****************************************************************************** + * @file spiflash2drv.c + * - Version : 0.04 + * @brief QSPI Flash driver for S25FS512S. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 15.10.2021 0.01 First Release + * : 23.03.2022 0.02 Modify command for QSPI Flash to refer to + * : command table. + * : 01.04.2022 0.03 Modify magic number to definition. + * : 09.11.2022 0.04 License notation change. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "dma2.h" + +#define QSPI_PARAM_SEC_SIZE (0x1000U) +#define QSPI_PARAM_SEC_MASK (0xFFFFF000U) + +void fast_rd_qspi_flash(uint32_t sourceSpiAdd, uint32_t destinationAdd, uint32_t byteCount) +{ + uint32_t sourceAdd; + + init_rpc_qspi_flash_4fastread_ext_mode(); + + sourceAdd = SPI_IOADDRESS_TOP + sourceSpiAdd; + + // dma_trans_start(destinationAdd, sourceAdd, byteCount); + // dma_trans_end_check(); + // dma2_init(); + dma2_start(destinationAdd, sourceAdd, byteCount, DMA_MODE_SRC_INC); + dma2_end(); +} +/* End of function fast_rd_qspi_flash */ + +/* Qspi:Sector Erase */ +/* 4SE DCh */ +void sector_erase_NNNkb_qspi_flash_s25s512s(uint32_t addr) +{ + uint32_t status; + + /* WRITE ENABLE */ + write_command_qspi_flash((gp_qspi_cmd_tbl -> write_enable) << DRCMR_SMCMR_CMD_SHIFT); + + sector_erase_4byte_qspi_flash(addr); + + while(1) + { + read_status_qspi_flash(&status); + if( check_Erase_Fail(status) ) + { + // put_str("Erase Error", CRLF_OFF); + ERROR("Erase Error!!\n"); + break; + } + read_wip_status_register(&status); + if( !(status & BIT0) ) + { + break; + } + } +} +/* End of function sector_erase_NNNkb_qspi_flash_s25s512s */ + +/* Qspi:Parameter 4-kB Sector Erase */ +/* 4P4E 21h */ +void parameter_sector_erase_4kb_qspi_flash_s25s512s(uint32_t addr) +{ + uint32_t status; + + /* WRITE ENABLE */ + write_command_qspi_flash((gp_qspi_cmd_tbl -> write_enable) << DRCMR_SMCMR_CMD_SHIFT); + + parameter_sector_erase_4kb_qspi_flash(addr); + + while(1) + { + read_status_qspi_flash(&status); + if( check_Erase_Fail(status) ) + { + ERROR("Erase Error!!\n"); + break; + } + read_wip_status_register(&status); + if( !(status & BIT0) ) + { + break; + } + } +} +/* End of function parameter_sector_erase_4kb_qspi_flash_s25s512s */ + +/* Qspi:Page Program (4PP:12h) */ +void page_program_with_buf_qspi_flash_s25s512s(uint32_t addr, uint32_t source_addr) +{ + uint32_t status; + + /* WRITE ENABLE */ + write_command_qspi_flash((gp_qspi_cmd_tbl -> write_enable) << DRCMR_SMCMR_CMD_SHIFT); + + write_data_4pp_with_buf_qspi_flash(addr,source_addr); /* 4PP */ + + /* Add */ + while(1) + { + read_wip_status_register(&status); + if( !(status & BIT0) ) + { + break; + } + } + +} +/* End of function page_program_with_buf_qspi_flash_s25s512s */ + +/* Qspi:Clear Block Protection of SR1V */ +void clear_bp_qspi_flash(void) +{ + uint32_t statusReg; + while(1) + { + read_wip_status_register(&statusReg); + if( !(statusReg & BIT0) ) + { + break; + } + } +} +/* End of function clear_bp_qspi_flash */ + +void save_data_with_buf_qspi_flash(uint32_t srcAdd,uint32_t svFlashAdd,uint32_t svSize) +{ + uint32_t flashAdd; + uint32_t writeDataAdd; + + /* WRITE ENABLE */ + write_command_qspi_flash((gp_qspi_cmd_tbl -> write_enable) << DRCMR_SMCMR_CMD_SHIFT); + + writeDataAdd = srcAdd; + + for(flashAdd=svFlashAdd; flashAdd<(svFlashAdd+svSize); flashAdd += RPC_WRITE_BUF_SIZE) + { /* 256byte:RPC Write Buffer size */ + page_program_with_buf_qspi_flash_s25s512s(flashAdd, writeDataAdd); + writeDataAdd = writeDataAdd + RPC_WRITE_BUF_SIZE; + } +} +/* End of function save_data_with_buf_qspi_flash */ + +void sector_erase_qspi_flash(uint32_t EraseStatAdd,uint32_t EraseEndAdd) +{ + uint32_t sectorAd; + uint32_t SectorStatTopAdd; + uint32_t SectorEndTopAdd; + + SectorStatTopAdd = EraseStatAdd & FLASH_SECTOR_MASK; + SectorEndTopAdd = EraseEndAdd & FLASH_SECTOR_MASK; + + for(sectorAd = SectorStatTopAdd; sectorAd <= SectorEndTopAdd; sectorAd += FLASH_SECTOR_SIZE) + { + sector_erase_NNNkb_qspi_flash_s25s512s(sectorAd); + } +} +/* End of function sector_erase_qspi_flash_s25s512s */ + +void parameter_sector_erase_qspi_flash(uint32_t EraseStatAdd,uint32_t EraseEndAdd) +{ + uint32_t sectorAd; + uint32_t SectorStatTopAdd; + uint32_t SectorEndTopAdd; + + SectorStatTopAdd = EraseStatAdd & QSPI_PARAM_SEC_MASK; + SectorEndTopAdd = EraseEndAdd & QSPI_PARAM_SEC_MASK; + + for(sectorAd = SectorStatTopAdd; sectorAd <= SectorEndTopAdd; sectorAd += QSPI_PARAM_SEC_SIZE) + { + parameter_sector_erase_4kb_qspi_flash_s25s512s(sectorAd); + } +} +/* End of function parameter_sector_erase_qspi_flash */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rtvram/rtvram.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rtvram/rtvram.c new file mode 100644 index 0000000..291d639 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/rtvram/rtvram.c @@ -0,0 +1,77 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-VRAM driver + ******************************************************************************/ +/****************************************************************************** + * @file RTVRAM.c + * - Version : 0.03 + * @brief RT-VRAM driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 17.11.2021 0.01 First Release + * : 03.12.2021 0.02 remove Cache flush. + * : 06.01.2022 0.03 Static analysis support + *****************************************************************************/ + +#include +#include +#include +#include +#include + +#define RTVRAM_VBUF_CFG_CACHE_MODE_8WAY (1U << 8U) +#define RTVRAM_VBUF_CFG_VBUF_SIZE_28M (6U << 0U) + +#define RTVRAM_EXT_MODE_EXT (1U << 0U) + +#define RTVRAM_VBUF_NUM (7U) + +#define RTVRAM_EXTEND_ENABLE (1U) + +void rtvram_extendmode(void) +{ +#if (RTVRAM_EXTEND == RTVRAM_EXTEND_ENABLE) + uint32_t reg; + uint32_t loop; + + /* Set each 4MB from the top of SDRAM as the buffer area of RT-VRAM. */ + for(loop = 0; loop < RTVRAM_VBUF_NUM; loop++) + { + mem_write32(get_vbuf_baddr_addr(loop), (uint32_t)((SDRAM_40BIT_ADDR_TOP + (RTVRAM_VBUF_AREA_SIZE * loop)) >> 16U)); + } + + reg = mem_read32(RTVRAM_VBUF_CFG); + reg |= (RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | RTVRAM_VBUF_CFG_VBUF_SIZE_28M); /* Cache Mode: 8-way, VBF size: 28M */ + mem_write32(RTVRAM_VBUF_CFG, reg); + + /* Set at the end */ + mem_write32(RTVRAM_EXT_MODE, RTVRAM_EXT_MODE_EXT); /* Change from Compatible Mode to Extended Mode */ + + syncm(); +#endif +} +/* End of function rtvram_extendmode(void) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/san/v4h.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/san/v4h.c new file mode 100644 index 0000000..05696ca --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/san/v4h.c @@ -0,0 +1,458 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : I2C driver + ******************************************************************************/ +/****************************************************************************** + * @file i2c.c + * - Version : 0.02 + * @brief I2C driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 16.11.2023 0.01 First Release + * : 24.06.2024 0.02 Remove pre-process branch of i2c5_read(). + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Setting value for PFC */ +#define GPSR4_TSN0_MDIO (0x00000001U) /* bit0 */ + +#define PMIC_ADDR ((0x54) << 1) /* regulation register */ +#define PMIC_ADDR_P ((0x55) << 1) /* protection register */ +#define PMIC_ADDR_OTP ((0x64) << 1) /* OTP register ? */ + +void PMIC_SM_27A(void) { +/* +// PRESET -> PRESETOUT Check +// Set SDI and EN High, and Presetout low +MCU_VMONOUT0 = B_PIN_STATE_HIGH; +MCU_VMONOUT1 = B_PIN_STATE_HIGH; +MCU_SDI4 = B_PIN_STATE_HIGH; +MCU_ERROROUT_M = B_PIN_STATE_HIGH; +MCU_PRESET_OUT = B_PIN_STATE_LOW; +MCU_EN_PIN = B_PIN_STATE_HIGH; + +delay_1ms(20); // Set delay to wait for LBIST to finish + +while (PMIC_GLOBAL_PGOOD != B_PIN_STATE_HIGH){} // Wait for PGOOD to go high + +while (PMIC_PRESETB != B_PIN_STATE_HIGH) {} // Wait for PRESET to go high + +delay_1ms(6); // Set delay to pass 25% of TIMEOUT_PRESET_CHK_TOUT + +MCU_PRESET_OUT = B_PIN_STATE_HIGH; // Set PRESETOUT High +*/ + + // from RAA271005_SAN.pdf page 91 + // PRESET# Check is executed by the PMIC automatically + + // // PGOOD_PMIC(TSN0_MDIO, GP4_00) + // /* Set GPSR to GPIO */ + // data = mem_read32((uintptr_t)PFC_GPSR4_RW); + // data &= ~(GPSR4_TSN0_MDIO); + // pfc_reg_write(PFC_GPSR4_RW, data); + + // /* PUEN disable */ + // data = mem_read32((uintptr_t)PFC_PUEN4_RW); + // data &= ~(GPSR4_TSN0_MDIO); + // pfc_reg_write(PFC_PUEN4_RW, data); + + // /* skip POSNEG + // data = mem_read32((uintptr_t)PFC_PUEN4_RW); + // data |= (GPSR4_TSN0_MDIO); + // mem_write32((uintptr_t)PFC_PUEN4_RW, data); + // */ + // /* skip INOUTSEL + // data = mem_read32((uintptr_t)PFC_INOUTSEL4_RW); + // data &= ~(GPSR4_TSN0_MDIO); + // mem_write32((uintptr_t)PFC_INOUTSEL4_RW, data); + // */ + // /* INEN */ + // data = mem_read32((uintptr_t)PFC_INEN4_RW); + // data |= (GPSR4_TSN0_MDIO); + // mem_write32((uintptr_t)PFC_INEN4_RW, data); + + // /* INDT */ + // do { + // data = mem_read32((uintptr_t)PFC_INDT4_R); + // } while ((data & GPSR4_TSN0_MDIO) != 0); +} + +#define D_SINT_CODE 0x2A +#define FUSA_CTRL_2 (0x09) +#define FUSA_CTRL_3 (0x0A) +#define FUSA_SOC_CHK_1 (0x15) +// SINT Check +void PMIC_SM_27B(void) { + uint32_t data = D_SINT_CODE; + + i2c5_write(PMIC_ADDR_P, FUSA_CTRL_2, data); + i2c5_read(PMIC_ADDR_P, FUSA_SOC_CHK_1, &data); + NOTICE("SINT Check = 0x%x\n", data); + i2c5_write(PMIC_ADDR_P, FUSA_CTRL_3, data); +} + +#define FUSA_CTRL_4 (0x0B) +#define EXT_PIN_CHK_EN (1U << 5) +#define EXT_PIN_CHK_SD1 (1U << 4) +#define EXT_PIN_CHK_SD2 (1U << 2) +#define EXT_PIN_CHK_SD3 (1U << 1) +#define EXT_PIN_CHK_SD4 (1U << 0) + +/* To read/write an adress after 0x100, + it is necessary to write a value to IO_PAGE and + access the target address after changing the page. + */ +#define FUSA_CTRL_D (0x11D) +// EXT PINCHECK2 +void PMIC_SM_27C(void) { +/* +// SDI1 Test +pmic_rtn_code_tmp = r_pmic_i2c_write(D_PMIC_I2C_PROT_ADDRESS, 0x0B, 0xFF); // Tell the PMIC to look for all SDIs to be high, to do this we set all bits (0xFF) +delay_1us(1); +MCU_ERROROUT_M = B_PIN_STATE_LOW; // Set SDI1 LOW +pmic_rtn_code_tmp = r_pmic_i2c_write(D_PMIC_I2C_PROT_ADDRESS, 0x0B, 0xEF); // Check for the SDI1 to be low +delay_1us(1); +MCU_ERROROUT_M = B_PIN_STATE_HIGH; // Set SDI1 HIGH + +// SDI2 Test +pmic_rtn_code_tmp = r_pmic_i2c_write(D_PMIC_I2C_PROT_ADDRESS, 0x0B, 0xFF); // Tell the PMIC to look for all SDIs to be high, to do this we set all bits (0xFF) +delay_1us(1); +MCU_VMONOUT0 = B_PIN_STATE_LOW; // Set SDI2 LOW +pmic_rtn_code_tmp = r_pmic_i2c_write(D_PMIC_I2C_PROT_ADDRESS, 0x0B, 0xFB); // Check for the SDI2 to be low +delay_1us(1); +MCU_VMONOUT0 = B_PIN_STATE_HIGH; // Set SDI2 HIGH + +// SDI3 Test +pmic_rtn_code_tmp = r_pmic_i2c_write(D_PMIC_I2C_PROT_ADDRESS, 0x0B, 0xFF); // Tell the PMIC to look for all SDIs to be high, to do this we set all bits (0xFF) +delay_1us(1); +MCU_VMONOUT1 = B_PIN_STATE_LOW; // Set SDI3 LOW +pmic_rtn_code_tmp = r_pmic_i2c_write(D_PMIC_I2C_PROT_ADDRESS, 0x0B, 0xFC); // Check for the SDI3 to be low +delay_1us(1); +MCU_VMONOUT1 = B_PIN_STATE_HIGH; // Set SDI3 HIGH + +// SDI4 Test +pmic_rtn_code_tmp = r_pmic_i2c_write(D_PMIC_I2C_PROT_ADDRESS, 0x0B, 0xFF); // Tell the PMIC to look for all SDIs to be high, to do this we set all bits (0xFF) +delay_1us(1); +MCU_SDI4 = B_PIN_STATE_LOW; // Set SDI4 LOW +pmic_rtn_code_tmp = r_pmic_i2c_write(D_PMIC_I2C_PROT_ADDRESS, 0x0B, 0xFE); // Check for the SDI4 to be low +delay_1us(1); +MCU_SDI4 = B_PIN_STATE_HIGH; // Set SDI4 HIGH + +comms_rtrncode_tmp = r_pmic_i2c_write(D_PMIC_I2C_PROT_ADDRESS, 0x0B, 0x00); // Must clear out 0x0B after external pin check 2 complete +*/ + uint32_t data = 0xFF; + + NOTICE("EXT PINCHECK2\n"); + // SDI1,2,3,4 Test + // Tell the PMIC to look for all SDIs to be high, to do this we set all bits (0xFF) + i2c5_write(PMIC_ADDR_P, FUSA_CTRL_4, data); + micro_wait(1U); + + // Must clear out 0x0B after external pin check 2 complete + i2c5_write(PMIC_ADDR_P, FUSA_CTRL_4, 0x0); +} + +#define D_LENGTH_FUSA_CTRL_CVM 4 // Based on how many CVM slots is enabled +#define FUSA_CHK_CVM1 (0x0D) +#define CVM_TEST_START (1U << 0) +#define CVM_TEST_DONE (1U << 7) +#define FUSA_STATUS_CVM1 (0x0E) +#define CVM_TEST_FAIL_3 (0x3U << 6) +#define CVM_TEST_FAIL_2 (0x3U << 4) +#define CVM_TEST_FAIL_1 (0x3U << 2) +#define FUSA_STATUS_CVM2 (0x0F) +#define CVM_TEST_FAIL_6 (0x3U << 4) +#define CVM_TEST_FAIL_5 (0x3U << 2) +#define CVM_TEST_FAIL_4 (0x3U << 0) + +#define FUSA_CHK_CVM2H (0x10D) +#define FUSA_CHK_CVM2L (0x10E) +#define FUSA_CHK_CVM3H (0x10F) +#define FUSA_CHK_CVM3L (0x110) +#define FUSA_CHK_CVM4H (0x111) +#define FUSA_CHK_CVM4L (0x112) +#define FUSA_CHK_CVM5H (0x113) +#define FUSA_CHK_CVM5L (0x114) + +#define FUSA_CTRL_CVM1 (0x125) +#define FUSA_CTRL_CVM2 (0x126) +#define FUSA_CTRL_CVM3 (0x127) +#define FUSA_CTRL_CVM4 (0x128) +#define FUSA_CTRL_CVM5 (0x129) +#define FUSA_CTRL_CVM6 (0x12A) + +#define ADCMON_MASK_ExtINPs (0x133) +#define FaultMask_EXT_0_Prot (1U << 0) +#define FaultMask_EXT_1_Prot (1U << 0) + +// CVM Test +void PMIC_SM_27D(void) { +/* +//Array that holds the 8bit dac information ADC1 +uint8_t g_ary_cvm_vthref[4] = { + 0x0F, //2 + 0x3A, //3 + 0x60, //4 + 0x3A //3 +}; + +//Array that holds the 12bit dac information ADC2 +uint8_t g_ary_cvm_vthsense[8] = { + 0x03, 0xE1, + 0x00, 0xD3, + 0x00, 0xD3, + 0x03, 0xE1 +}; + +D_LENGTH_FUSA_CTRL_CVM = 4; // Based on how many CVM slots is enabled + +comms_rtn_code_tmp = r_pmic_i2c_write(D_PMIC_I2C_PROT_ADDRESS, 0x0D, 0x01); // Start CVM Test +delay_1ms(1); + +for(idx = 0; idx = LOG_NOTICE + uint32_t data = 0xFF; + char *str, *str2, *str3; + + i2c5_read(PMIC_ADDR_P, FUSA_STATUS_1, &data); + if ((data & SOC_ACTIVATED) != 0) + str = "PASSED"; + else + str = "FAILED"; + + switch (data & (0x7 << 5)) { + case SCS_POWER_OFF: str2 = "power off"; break; + case SCS_SELF_DIAG: str2 = "self diagnosis"; break; + case SCS_POWER_UP : str2 = "power up sequence"; break; + case SCS_SOC_ACTIV: str2 = "SoC activation"; break; + case SCS_ACTIVE: str2 = "ACTIVE"; break; + case SCS_RESET: str2 = "RESET"; break; + case SCS_ERROR: str2 = "ERROR"; break; + case SCS_LOCK: str2 = "LOCK"; break; + default: + str2 = "unknown"; + break; + } + + switch (data & 0x7) { + case SAS_IDLE: str3 = "idle"; break; + case SAS_EXT_PIN_CHK_1: str3 = "EXT PIN check(1)"; break; + case SAS_SINT_CHK: str3 = "SINT check"; break; + case SAS_EXT_PIN_CHK_2: str3 = "EXT PIN check(2)"; break; + case SAS_START_WDT: str3 = "start WDT"; break; + default: + str3 = "unknown"; + break; + } + + NOTICE("SoC Activation: %s(%s), %s, 0x%x\n", str, str3, str2, data); +#endif +} + +#define WDT_KICK_REG (0x95) +#define WDT_LFSR (0x96) +#define WDT_CFG0 (0x107) +#define WDT_CFG0_QNA (0x1 << 2) +#define WDT_CFG0_16QNA (0x1 << 1) +#define WDT_CFG0_EN (0x1 << 0) +#define WDT_CFG3 (0x10A) +void PMIC_SM_12_wdt(void) { + uint32_t tmp, question, answer0; + + i2c5_read(PMIC_ADDR_P, WDT_CFG0, &tmp); + if ((tmp & WDT_CFG0_EN) == 0) { + NOTICE("WDT is disabled\n"); + i2c5_read(PMIC_ADDR_P, 0x01, &tmp); /* set PAGE to 0x00 */ + return; + } + + i2c5_read(PMIC_ADDR_P, WDT_LFSR, &question); // Read the question + if ((tmp & WDT_CFG0_16QNA) == 0) { + // Grab only the first two bits to figure out what to do + tmp = question >> 6; + answer0 = question & 0x3F; + + micro_wait(4U); + if (tmp == 0x1) { + answer0 = (answer0 << 1) | (tmp << 6); + } else if (tmp == 0x2) { + answer0 = (answer0 >> 1) | (tmp << 6); + } else if (tmp == 0x3) { + answer0 = (~answer0) | (tmp << 6); + } /* else if (tmp == 0x0) { + // answer0 = (answer0) | (tmp << 6); + } */ + i2c5_write(PMIC_ADDR_P, WDT_KICK_REG, answer0); + NOTICE("4Q&A: DONE\n"); + } else { + static uint8_t g_ary_wdt_answer[] = { + 0x00, 0x4F, 0x16, 0x59, + 0x8a, 0xc5, 0x9c, 0xd3, + 0x2d, 0x62, 0x3b, 0x74, + 0xa7, 0xe8, 0xb1, 0xfe, + }; + uint32_t err_cnt = 0; + + // Grab the upper nibble to respond to, logic shift the lower nibble away + tmp = question >> 4; + answer0 = g_ary_wdt_answer[tmp]; + + i2c5_write(PMIC_ADDR_P, WDT_KICK_REG, answer0); + i2c5_read(PMIC_ADDR_P, WDT_CFG3, &question); + err_cnt |= (question & 0xFF) << 24; // Check WDT Error counter + micro_wait(4U); + + // For the second answer, take the first answer and flip the upper nibble + i2c5_write(PMIC_ADDR_P, WDT_KICK_REG, (answer0 ^ 0xF0) & 0xFF); + i2c5_read(PMIC_ADDR_P, WDT_CFG3, &question); + err_cnt |= (question & 0xFF) << 16; // Check WDT Error counter + micro_wait(4U); + + // For the third answer, take the first answer and flip the lower nibble + i2c5_write(PMIC_ADDR_P, WDT_KICK_REG, (answer0 ^ 0x0F) & 0xFF); + i2c5_read(PMIC_ADDR_P, WDT_CFG3, &question); + err_cnt |= (question & 0xFF) << 8; // Check WDT Error counter + micro_wait(4U); + + // For the fourth answer, take the first answer and invert the whole byte + i2c5_write(PMIC_ADDR_P, WDT_KICK_REG, (answer0 ^ 0xFF) & 0xFF); + i2c5_read(PMIC_ADDR_P, WDT_CFG3, &question); + err_cnt |= (question & 0xFF) << 0; // Check WDT Error counter + if (err_cnt) { + NOTICE("16Q&A: Error 0x%x\n", err_cnt); + } else { + NOTICE("16Q&A: DONE\n"); + } + i2c5_read(PMIC_ADDR_P, 0x01, &tmp); /* set PAGE to 0x00 */ + } +} + +// External Pin Check for ECM +void SM_6_3_1(void) {} +// External Pin Check for RST +void SM_6_3_2(void) {} +// initial Toggle Test +void SM_5_3_6(void) {} +// check POST result of other than "stop" type hierachies +void SM_5_1(void) {} +// read Back Test for Integrity Check +void SM_6_23(void) {} +// self test for AES-ACC +void SM_4_21(void) {} +// self check for Field BIST +void SM_5_1_6(void) {} +// self check for Field BIST +void SM_5_2_6(void) {} +// write access protection check at start-up +void SM_6_2(void) {} +// timeout monitoring for confirmation of PHY start +void SM_6_11(void) {} +// initial loopback test using PWM +void SM_6_14_6(void) {} +// integrity check for Program Code +void SM_6_22(void) {} +// start-up test for THS +void SM_6_24_2(void) {} +// start-up test for CVM +void SM_6_24_3(void) {} +// Power isolation Cell Error Detector Test at start-up +void SM_6_29(void) {} +// clock monitor test at start-up +void SM_6_30(void) {} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/sysc/sysc.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/sysc/sysc.c new file mode 100644 index 0000000..29a3f1b --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/sysc/sysc.c @@ -0,0 +1,109 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : System Controller function + ******************************************************************************/ +/****************************************************************************** + * @file sysc.c + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.09.2023 0.01 First Release + * : 13.11.2023 0.02 Add software reset + * : 16.11.2023 0.03 Add APSREG initialization process. + * : 22.10.2024 0.04 Update the C4 power domain setting process. +*****************************************************************************/ +#include "mem_io.h" +#include "sysc.h" +#include "cpg_register.h" +#include "log.h" +#include "cpu_on.h" +#include "ap_system_core_register.h" + +/* + * V4M turns on C4 power before starting CA + * V4M HWM:SYSC:Operation:Power Control of Non Arm CPU Modules + */ +#if (RCAR_LSI == RCAR_V4M) +void sysc_c4_power_on(void) +{ + uint32_t reg; + + /* + * Need to execute APSREG initialization before C4 power on according to + * R-Car V4M Series User's Manual '5.4.3 Register Initialization Before C4 power on'. + */ + reg = mem_read32(ap_core_get_ap_cluster_n_aux0_addr(0U)); + reg |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT; + mem_write32(ap_core_get_ap_cluster_n_aux0_addr(0U), reg); + + reg = mem_read32(AP_CORE_APSREG_CCI500_AUX); + reg |= AP_CORE_APSREG_CCI500_AUX_ACTDIS; + mem_write32(AP_CORE_APSREG_CCI500_AUX, reg); + + /* 1.Write the set value in SYSCIER0 and SYSCIMR0 */ + reg = mem_read32(SYSC_SYSCIER0); + mem_write32(SYSC_SYSCIER0, reg | SYSCIER0_PDR31); + reg = mem_read32(SYSC_SYSCIMR0); + mem_write32(SYSC_SYSCIMR0, reg | SYSCIMR0_PDR31); + + /* 2.Confirm that SYSCSR.BUSY[1] becomes 1.*/ + while (true) + { + reg = mem_read32(SYSC_SYSCSR); + if (SYSCSR_BUSY1 == (reg & SYSCSR_BUSY1)) + { + break; + } + } + + /* 3.Write the reset value in SRCR11 and SESTCLR11 */ + reg = mem_read32(CPG_SRCR11); + mem_write32(CPG_SRCR11, reg | CPGSRCR_PDR11); + mem_write32(CPG_SRSTCLR11, CPGSRCR_PDR11); + + /* 4.Write the set value in PDRONCR31 */ + mem_write32(SYSC_PDRONCR31, PDRONCR31_PWRON); + + /* 5.Confirm that SYSCISCR0.PDR[31] becomes 1.*/ + while (true) + { + reg = mem_read32(SYSC_SYSCISCR0); + if (SYSCISCR0_PDR31 == (reg & SYSCISCR0_PDR31)) + { + break; + } + } + + /* 6.Clear the bit31(PDR[31]) in SYSCISCR0 to 0. */ + mem_write32(SYSC_SYSCISCR0, SYSCISCR0_PDR31); +} +/* End of function sysc_c4_power_on(void) */ +#endif /* RCAR_LSI == RCAR_V4M */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/wdt/rwdt.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/wdt/rwdt.c new file mode 100644 index 0000000..aa638de --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/wdt/rwdt.c @@ -0,0 +1,101 @@ +/******************************************************************************* + * DESCRIPTION : RCLK watchdog timer driver + ******************************************************************************/ +/****************************************************************************** + * @file rwdt.c + * - Version : 0.014 + * @brief RCLK Watchdog Timer driver + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.04.2025 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +/* Initialization RCLK Watchdog Timer, see 154.1.3 Operation of h/w manual */ +void rwdt_init(int start) +{ + uint8_t wdta_val; + + wdta_val = mem_read8(RWDT_RWTCSRA); + if (((wdta_val & RWTCSRA_TME) != 0) && start) { + wdta_val &= ~(RWTCSRA_TME); + mem_write32(RWDT_RWTCSRA, RWTCSRA_UPPER | wdta_val); + + mem_write32(RWDT_RWTCNT, RWTCNT_UPPER | 0x0U); + + wdta_val = mem_read8(RWDT_RWTCSRA); + wdta_val &= ~(RWTCSRA_WOVF); + mem_write32(RWDT_RWTCSRA, RWTCSRA_UPPER | wdta_val); + + /* skip set CKS0, CKS1 */ + } + + do { + wdta_val = mem_read8(RWDT_RWTCSRA); + } while ((wdta_val & RWTCSRA_WRFLG) != 0); + + /* start the counting by setting the TME bit in RWTCSRA to 1 */ + /* + if (start) { + wdta_val |= RWTCSRA_TME; + mem_write32(RWDT_RWTCSRA, RWTCSRA_UPPER | wdta_val); + } + */ +} + +/* +void rwdt_update(void) +{ + mem_write32(RWDT_RWTCNT, RWTCNT_UPPER | 0U); +} + +// RWTCNT overflow +void rwdt_handler(void) +{ + uint8_t wdta_val; + + wdta_val = mem_read8(RWDT_RWTCSRA); + if ((wdta_val & RWTCSRA_WOVF) != 0) { + // it's overflowed. + } + + // RWTCNT, RWTCSRA, RWTCSRB are initialized. + // should we run rwdt_init() again? +} +*/ + +/* Initialization System Watchdog Timer */ +void swdt_init(int start) +{ + uint8_t wdta_val; + + wdta_val = mem_read8(SWDT_SWTCSRA); + if (((wdta_val & RWTCSRA_TME) != 0) && start) { + wdta_val &= ~(RWTCSRA_TME); + mem_write32(SWDT_SWTCSRA, RWTCSRA_UPPER | wdta_val); + + mem_write32(SWDT_SWTCNT, RWTCNT_UPPER | 0x0U); + + wdta_val = mem_read8(SWDT_SWTCSRA); + wdta_val &= ~(RWTCSRA_WOVF); + mem_write32(SWDT_SWTCSRA, RWTCSRA_UPPER | wdta_val); + + /* skip set CKS0, CKS1 */ + } + + do { + wdta_val = mem_read8(SWDT_SWTCSRA); + } while ((wdta_val & RWTCSRA_WRFLG) != 0); + + /* start the counting by setting the TME bit in SWTCSRA to 1 */ + /* do nothing */ +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/wdt/wdt.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/wdt/wdt.c new file mode 100644 index 0000000..12e169e --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/ip/wdt/wdt.c @@ -0,0 +1,148 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : window watchdog timer driver + ******************************************************************************/ +/****************************************************************************** + * @file wdt.c + * - Version : 0.04 + * @brief Window Watchdog Timer driver + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 06.01.2022 0.02 Add exception handling for ICUMX_WDTA. + * : 20.01.2022 0.03 Add ICUMX name unification. + * : 11.01.2023 0.04 Modify activation code writing to + * : ICUMX_WDTA0EVAC register. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + + +#define ICUMX_WDTA0_BASE (0xFFFEE080U) /* Watchdog Timer base */ +#define ICUMX_WDTA0WDTE (ICUMX_WDTA0_BASE) +#define ICUMX_WDTA0EVAC (ICUMX_WDTA0_BASE+0x0004U) +#define ICUMX_WDTA0REF (ICUMX_WDTA0_BASE+0x0008U) +#define ICUMX_WDTA0MD (ICUMX_WDTA0_BASE+0x000CU) + + +#define WDTA0MD_WDTA0WIE (1U<<3) /* Enables the 75% interrupt request INTWDTA0 */ +#define WDTA0MD_WDTA0ERM (1U<<2) /* 0:NMI request mode 1:Reset mode */ +#define WDTA0MD_WDTA0WS10 (3U) /* 11B: window-open period is 100% */ + +/* overflow time setting */ +#define WDT_11MS (0x0U) +#define WDT_23MS (0x1U) +#define WDT_46MS (0x2U) +#define WDT_93MS (0x3U) +#define WDT_187MS (0x4U) +#define WDT_374MS (0x5U) +#define WDT_749MS (0x6U) +#define WDT_1498MS (0x7U) + +/* Activation code */ +#define WDT_ACT_CODE (0xACU) + +/* ICUMX Configuration Register */ +#define ICUMX_CFG4 (0xFFFEE270U) +/* Bit definition for Configuration Register */ +#define ICUMX_CFG4_ICUMOPWDVAC (0x00000020U) + +/* Initialization Window Watchdog Timer */ +void wdt_init(void) +{ + uint8_t wdta_val; + + /* This API is executed before copying a part of Loader to Local RAM. */ + /* Therefore, this API can not use the Memory mapped I/O API. */ + /* When reading or writing memory, execute the same processing as */ + /* Memory mapped I/O API in this function. */ + wdta_val = WDTA0MD_WDTA0ERM; /* NMI request mode */ + wdta_val |= WDTA0MD_WDTA0WIE; /* Enables the 75% interrupt request INTWDTA0 */ + wdta_val |= WDTA0MD_WDTA0WS10; + wdta_val |= (WDT_1498MS << 4U); /* overflow interval time */ + mem_write8(ICUMX_WDTA0MD, wdta_val); + + /* set watchdog timer handler */ + intc_set_interrupt(WDT0_INT, 7U, (INT_HANDLER)wdt_handler); + + /* watchdog timer restart */ + wdt_restart(); +} +/* End of function wdt_init(uint32_t overflow_time) */ + +void wdt_restart(void) +{ + uint8_t reg8; + uint32_t reg32; + + reg32 = mem_read32(ICUMX_CFG4); + + if((reg32 & ICUMX_CFG4_ICUMOPWDVAC) != 0U) + { + reg8 = mem_read8(ICUMX_WDTA0REF); + reg8 = WDT_ACT_CODE - reg8; + /* Watchdog Timer restart. */ + /* Subtract ICUMX_WDTA0REF from activation code when VAC(Variable Activation Code) is enabled. */ + mem_write8(ICUMX_WDTA0EVAC, reg8); + } + else + { + /* Watchdog Timer restart. */ + mem_write8(ICUMX_WDTA0EVAC, WDT_ACT_CODE); + } +} +/* End of function wdt_restart(void) */ + +#include +#include +#define RST_SRESCR0 (RST_BASE + 0x18) +#define RST_SPRES 0x5AA58000UL + +/* Interrupt handling function */ +void wdt_handler(void) +{ + intc_disable_interrupt(WDT0_INT); + ERROR("\n"); + ERROR("ICUMX: System WDT overflow\n"); +#ifdef WDT_RESET + micro_wait(11*1000U); /* wait 11 miliseconds */ + /* try to reset */ + mem_write32(RST_SRESCR0, RST_SPRES); +#else +#warning "WDT_RESET is not defined. System will not reset." + /* If WDT_RESET is not defined, the system will not reset. */ + /* This is useful for debugging purposes, but in production, */ + /* it is recommended to define WDT_RESET to ensure the system resets on WDT overflow. */ +#endif + panic; +} +/* End of function wdt_handler(void) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/icumx_loader.ld b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/icumx_loader.ld new file mode 100644 index 0000000..d8a22e5 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/icumx_loader.ld @@ -0,0 +1,192 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader linker directive + ******************************************************************************/ + +DEFAULTS { +//Memory + remap_addr = 0xFDE00000 //remap15 address(target address = 0xEB200000) + remap_size = 1M //RT-SRAM size + + rt_sram_addr = 0xEB200000 //RT-SRAM address + local_ram_addr = 0xfede0000 //LRAM address + local_ram_size = 128K //LRAM size + +// Size +//No override area + stack_size = 16K //ICUMX Loader stack size + sa9_size = 64K //content cert size(cert info 1K + content cert(14) * 2K) + bss_size = 16K +// Configuration Table + qosbw_table_size = 4K + qoswt_table_size = 4K + rgid_m_table_size = 1K + rgid_r_table_size = 8K + rgid_w_table_size = 8K + rgid_sec_table_size = 8K + rgid_axi_table_size = 1K + rgid_gid_table_size = 1K //include .data section + configuration_size = qosbw_table_size + qoswt_table_size + rgid_m_table_size + rgid_r_table_size + rgid_w_table_size + rgid_sec_table_size + rgid_axi_table_size + rgid_gid_table_size + +// ICUMX Loader + ipl_top_addr = 0xEB210000 + ipl_size = 128K //ICUMX Loader size + vector_table_size = 2K //vector table size + ipl_rom_size = ipl_size - (vector_table_size + configuration_size + bss_size) + +// Address +// ICUMX Loader + vector_table_address_offset = ipl_top_addr - rt_sram_addr + code_fetch_remap_vector_table = 0x1200000 + vector_table_address_offset // 0xEB200000 - 0xEA000000 + ipl start address offset + code_fetch_remap_ipl = code_fetch_remap_vector_table + (vector_table_size + configuration_size) + +// No override area + stack_addr_offset = remap_size - stack_size + sa9_addr_offset = 0x30000 + bss_addr_offset = sa9_addr_offset - bss_size + +// Configuration Table + configuration_table_address_offset = vector_table_address_offset + vector_table_size + configuration_table_address = code_fetch_remap_vector_table + vector_table_size + qosbw_table_address = configuration_table_address + qoswt_table_address = qosbw_table_address + qosbw_table_size + rgid_m_table_address = qoswt_table_address + qoswt_table_size + rgid_r_table_address = rgid_m_table_address + rgid_m_table_size + rgid_w_table_address = rgid_r_table_address + rgid_r_table_size + rgid_sec_table_address = rgid_w_table_address + rgid_w_table_size + rgid_axi_table_address = rgid_sec_table_address + rgid_sec_table_size + rgid_gid_table_address = rgid_axi_table_address + rgid_axi_table_size + +// Offset + qosbw_table_address_offset = vector_table_address_offset + vector_table_size + qoswt_table_address_offset = qosbw_table_address_offset + qosbw_table_size + rgid_m_table_address_offset = qoswt_table_address_offset + qoswt_table_size + rgid_r_table_address_offset = rgid_m_table_address_offset + rgid_m_table_size + rgid_w_table_address_offset = rgid_r_table_address_offset + rgid_r_table_size + rgid_sec_table_address_offset = rgid_w_table_address_offset + rgid_w_table_size + rgid_axi_table_address_offset = rgid_sec_table_address_offset + rgid_sec_table_size + rgid_gid_table_address_offset = rgid_axi_table_address_offset + rgid_axi_table_size + ipl_rom_address_offset = configuration_table_address_offset + configuration_size +} +MEMORY +{ + vector_table : ORIGIN = code_fetch_remap_vector_table , LENGTH = vector_table_size // ICUMX Loader (CFREMAP) + qosbw_table : ORIGIN = remap_addr + qosbw_table_address_offset , LENGTH = qosbw_table_size // configuration table (QOSBW) + qoswt_table : ORIGIN = remap_addr + qoswt_table_address_offset , LENGTH = qoswt_table_size // configuration table (QOSWT) + rgid_m_table : ORIGIN = remap_addr + rgid_m_table_address_offset , LENGTH = rgid_m_table_size // configuration table (Region ID(Master)) + rgid_r_table : ORIGIN = remap_addr + rgid_r_table_address_offset , LENGTH = rgid_r_table_size // configuration table (Region ID(Read)) + rgid_w_table : ORIGIN = remap_addr + rgid_w_table_address_offset , LENGTH = rgid_w_table_size // configuration table (Region ID(Write)) + rgid_sec_table : ORIGIN = remap_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure)) + rgid_axi_table : ORIGIN = remap_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (R/W for AXI) + rgid_gid_table : ORIGIN = remap_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (R/W for GID) + ipl_rom : ORIGIN = code_fetch_remap_ipl , LENGTH = ipl_rom_size + +// Physical address + phys_vector_table : ORIGIN = rt_sram_addr + vector_table_address_offset, LENGTH = vector_table_size //ICUMX Loader(RT-SRAM) + phys_qosbw_table : ORIGIN = rt_sram_addr + qosbw_table_address_offset, LENGTH = qosbw_table_size //configuration table (QOSBW) + phys_qoswt_table : ORIGIN = rt_sram_addr + qoswt_table_address_offset, LENGTH = qoswt_table_size //configuration table (QOSWT) + phys_rgid_m_table : ORIGIN = rt_sram_addr + rgid_m_table_address_offset, LENGTH = rgid_m_table_size // configuration table (Region ID(Master)) + phys_rgid_r_table : ORIGIN = rt_sram_addr + rgid_r_table_address_offset, LENGTH = rgid_r_table_size // configuration table (Region ID(Read)) + phys_rgid_w_table : ORIGIN = rt_sram_addr + rgid_w_table_address_offset, LENGTH = rgid_w_table_size // configuration table (Region ID(Write)) + phys_rgid_sec_table : ORIGIN = rt_sram_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure)) + phys_rgid_axi_table : ORIGIN = rt_sram_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (Region ID(R/W for AXI)) + phys_rgid_gid_table : ORIGIN = rt_sram_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (Region ID(R/W for GID)) + phys_ipl_rom : ORIGIN = rt_sram_addr + ipl_rom_address_offset, LENGTH = ipl_rom_size //ICUMX Loader(RT-SRAM) + +// No override area + sa9_load : ORIGIN = remap_addr + sa9_addr_offset, LENGTH = sa9_size // Content cert + stack : ORIGIN = remap_addr + stack_addr_offset, LENGTH = stack_size // ICUMX Loader stack + bss : ORIGIN = remap_addr + bss_addr_offset, LENGTH = bss_size // ICUMX Loader bss area + local_ram : ORIGIN = local_ram_addr, LENGTH = local_ram_size - stack_size // Local RAM +} + +// +// Program layout for starting in ROM, copying data to RAM, +// and continuing to execute out of ROM. +// +SECTIONS +{ +// +// ROM SECTIONS(Remap) +// +// Place .text into fast_memory. Fail if it does not fit. + .reset ALIGN(4) : > vector_table + .EIINTTBL_ICU ALIGN(512) : > . + .qosbw_tbl ALIGN(4) : > qosbw_table + .qoswt_tbl ALIGN(4) : > qoswt_table + .rgid_m_tbl ALIGN(4) : > rgid_m_table + .rgid_r_tbl ALIGN(4) : > rgid_r_table + .rgid_w_tbl ALIGN(4) : > rgid_w_table + .rgid_sec_tbl ALIGN(4) : > rgid_sec_table + .rgid_axi_tbl ALIGN(4) : > rgid_axi_table + .rgid_gid_tbl ALIGN(4) : > rgid_gid_table + .data ALIGN(4) : > . + .text ALIGN(4) : > ipl_rom + .RE_CR.text ALIGN(4) : > . + .rosdata ALIGN(4) : > . + .rodata ALIGN(4) : > . + .secinfo ALIGN(4) : > . + + .rom_end ALIGN(4) : > . + .canary ALIGN(4) : > bss + .bss ALIGN(4) : > . + +// ROM mirror SECTIONS(RT-SRAM) + _start = ipl_top_addr; + .ROM_NOCOPY.reset ROM_NOCOPY(.reset) ALIGN(4) : > phys_vector_table + .ROM_NOCOPY.EIINTTBL_ICU ROM_NOCOPY(.EIINTTBL_ICU) ALIGN(4) : > . + .ROM_NOCOPY.qosbw_tbl ROM_NOCOPY(.qosbw_tbl) ALIGN(4) : > phys_qosbw_table + .ROM_NOCOPY.qoswt_tbl ROM_NOCOPY(.qoswt_tbl) ALIGN(4) : > phys_qoswt_table + .ROM_NOCOPY.rgid_m_tbl ROM_NOCOPY(.rgid_m_tbl) ALIGN(4) : > phys_rgid_m_table + .ROM_NOCOPY.rgid_r_tbl ROM_NOCOPY(.rgid_r_tbl) ALIGN(4) : > phys_rgid_r_table + .ROM_NOCOPY.rgid_w_tbl ROM_NOCOPY(.rgid_w_tbl) ALIGN(4) : > phys_rgid_w_table + .ROM_NOCOPY.rgid_sec_tbl ROM_NOCOPY(.rgid_sec_tbl) ALIGN(4) : > phys_rgid_sec_table + .ROM_NOCOPY.rgid_axi_tbl ROM_NOCOPY(.rgid_axi_tbl) ALIGN(4) : > phys_rgid_axi_table + .ROM_NOCOPY.rgid_gid_tbl ROM_NOCOPY(.rgid_gid_tbl) ALIGN(4) : > phys_rgid_gid_table + .ROM_NOCOPY.data ROM_NOCOPY(.data) ALIGN(4) : > . + .ROM_NOCOPY.text ROM_NOCOPY(.text) ALIGN(4) : > phys_ipl_rom + .ROM_NOCOPY.RE_CR.text ROM_NOCOPY(.RE_CR.text) ALIGN(4) : > . + .ROM_NOCOPY.rosdata ROM_NOCOPY(.rosdata) ALIGN(4) : > . + .ROM_NOCOPY.rodata ROM_NOCOPY(.rodata) ALIGN(4) : > . + .ROM_NOCOPY.secinfo ROM_NOCOPY(.secinfo) ALIGN(4) : > . + .cr_hot_plug_magic ALIGN(16): > . // This section must be placed at the last of binary. + + + +// +// RAM SECTIONS +// + .top_stack : > stack + .RT.stack ALIGN(4) PAD(stack_size) ABS : > . + .end_stack : > . + + .top.local.ram : > local_ram + .sdata ALIGN(4) : > . + .tdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .end.local.ram : > . + + .sa9_load ALIGN(4) PAD(sa9_size) : > sa9_load +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/icumx_loader_v4m.ld b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/icumx_loader_v4m.ld new file mode 100644 index 0000000..6c6e4b9 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/icumx_loader_v4m.ld @@ -0,0 +1,194 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader linker directive + ******************************************************************************/ + +DEFAULTS { +//Memory + remap_addr = 0xFDE00000 //remap15 address(target address = 0xEB200000) + remap_size = 1M //RT-SRAM size + + rt_sram_addr = 0xEB200000 //RT-SRAM address + local_ram_addr = 0xfede0000 //LRAM address + local_ram_size = 128K //LRAM size + +// Size +//No override area + stack_size = 16K //ICUMX Loader stack size + bootrom_work_size = 2K + sa9_size = 64K //content cert size(cert info 1K + content cert(14) * 2K) + bss_size = 16K +// Configuration Table + qosbw_table_size = 4K + qoswt_table_size = 4K + rgid_m_table_size = 1K + rgid_r_table_size = 8K + rgid_w_table_size = 8K + rgid_sec_table_size = 8K + rgid_axi_table_size = 1K + rgid_gid_table_size = 1K //include .data section + configuration_size = qosbw_table_size + qoswt_table_size + rgid_m_table_size + rgid_r_table_size + rgid_w_table_size + rgid_sec_table_size + rgid_axi_table_size + rgid_gid_table_size + +// ICUMX Loader + ipl_top_addr = 0xEB210000 + ipl_size = 128K //ICUMX Loader size + vector_table_size = 2K //vector table size + ipl_rom_size = ipl_size - (vector_table_size + configuration_size + bss_size) + +// Address +// ICUMX Loader + vector_table_address_offset = ipl_top_addr - rt_sram_addr + code_fetch_remap_vector_table = 0x1200000 + vector_table_address_offset // 0xEB200000 - 0xEA000000 + ipl start address offset + code_fetch_remap_ipl = code_fetch_remap_vector_table + (vector_table_size + configuration_size) + +// No override area + stack_addr_offset = 110K // stack top address : 0xFEDFB800 (This is in Local RAM) + sa9_addr_offset = 0x30000 + bss_addr_offset = sa9_addr_offset - bss_size + +// Configuration Table + configuration_table_address_offset = vector_table_address_offset + vector_table_size + configuration_table_address = code_fetch_remap_vector_table + vector_table_size + qosbw_table_address = configuration_table_address + qoswt_table_address = qosbw_table_address + qosbw_table_size + rgid_m_table_address = qoswt_table_address + qoswt_table_size + rgid_r_table_address = rgid_m_table_address + rgid_m_table_size + rgid_w_table_address = rgid_r_table_address + rgid_r_table_size + rgid_sec_table_address = rgid_w_table_address + rgid_w_table_size + rgid_axi_table_address = rgid_sec_table_address + rgid_sec_table_size + rgid_gid_table_address = rgid_axi_table_address + rgid_axi_table_size + +// Offset + qosbw_table_address_offset = vector_table_address_offset + vector_table_size + qoswt_table_address_offset = qosbw_table_address_offset + qosbw_table_size + rgid_m_table_address_offset = qoswt_table_address_offset + qoswt_table_size + rgid_r_table_address_offset = rgid_m_table_address_offset + rgid_m_table_size + rgid_w_table_address_offset = rgid_r_table_address_offset + rgid_r_table_size + rgid_sec_table_address_offset = rgid_w_table_address_offset + rgid_w_table_size + rgid_axi_table_address_offset = rgid_sec_table_address_offset + rgid_sec_table_size + rgid_gid_table_address_offset = rgid_axi_table_address_offset + rgid_axi_table_size + ipl_rom_address_offset = configuration_table_address_offset + configuration_size +} +MEMORY +{ + vector_table : ORIGIN = code_fetch_remap_vector_table , LENGTH = vector_table_size // ICUMX Loader (CFREMAP) + qosbw_table : ORIGIN = remap_addr + qosbw_table_address_offset , LENGTH = qosbw_table_size // configuration table (QOSBW) + qoswt_table : ORIGIN = remap_addr + qoswt_table_address_offset , LENGTH = qoswt_table_size // configuration table (QOSWT) + rgid_m_table : ORIGIN = remap_addr + rgid_m_table_address_offset , LENGTH = rgid_m_table_size // configuration table (Region ID(Master)) + rgid_r_table : ORIGIN = remap_addr + rgid_r_table_address_offset , LENGTH = rgid_r_table_size // configuration table (Region ID(Read)) + rgid_w_table : ORIGIN = remap_addr + rgid_w_table_address_offset , LENGTH = rgid_w_table_size // configuration table (Region ID(Write)) + rgid_sec_table : ORIGIN = remap_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure)) + rgid_axi_table : ORIGIN = remap_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (R/W for AXI) + rgid_gid_table : ORIGIN = remap_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (R/W for GID) + ipl_rom : ORIGIN = code_fetch_remap_ipl , LENGTH = ipl_rom_size + +// Physical address + phys_vector_table : ORIGIN = rt_sram_addr + vector_table_address_offset, LENGTH = vector_table_size //ICUMX Loader(RT-SRAM) + phys_qosbw_table : ORIGIN = rt_sram_addr + qosbw_table_address_offset, LENGTH = qosbw_table_size //configuration table (QOSBW) + phys_qoswt_table : ORIGIN = rt_sram_addr + qoswt_table_address_offset, LENGTH = qoswt_table_size //configuration table (QOSWT) + phys_rgid_m_table : ORIGIN = rt_sram_addr + rgid_m_table_address_offset, LENGTH = rgid_m_table_size // configuration table (Region ID(Master)) + phys_rgid_r_table : ORIGIN = rt_sram_addr + rgid_r_table_address_offset, LENGTH = rgid_r_table_size // configuration table (Region ID(Read)) + phys_rgid_w_table : ORIGIN = rt_sram_addr + rgid_w_table_address_offset, LENGTH = rgid_w_table_size // configuration table (Region ID(Write)) + phys_rgid_sec_table : ORIGIN = rt_sram_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure)) + phys_rgid_axi_table : ORIGIN = rt_sram_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (Region ID(R/W for AXI)) + phys_rgid_gid_table : ORIGIN = rt_sram_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (Region ID(R/W for GID)) + phys_ipl_rom : ORIGIN = rt_sram_addr + ipl_rom_address_offset, LENGTH = ipl_rom_size //ICUMX Loader(RT-SRAM) + +// No override area + sa9_load : ORIGIN = remap_addr + sa9_addr_offset, LENGTH = sa9_size // Content cert + stack : ORIGIN = local_ram_addr + stack_addr_offset, LENGTH = stack_size // ICUMX Loader stack (This is in Local RAM) + bss : ORIGIN = remap_addr + bss_addr_offset, LENGTH = bss_size // ICUMX Loader bss area + local_ram : ORIGIN = local_ram_addr, LENGTH = local_ram_size - stack_size - bootrom_work_size // Local RAM + bootrom_work : ORIGIN = local_ram_addr + stack_addr_offset + stack_size, LENGTH = bootrom_work_size // BootROM work area +} + +// +// Program layout for starting in ROM, copying data to RAM, +// and continuing to execute out of ROM. +// +SECTIONS +{ +// +// ROM SECTIONS(Remap) +// +// Place .text into fast_memory. Fail if it does not fit. + .reset ALIGN(4) : > vector_table + .EIINTTBL_ICU ALIGN(512) : > . + .qosbw_tbl ALIGN(4) : > qosbw_table + .qoswt_tbl ALIGN(4) : > qoswt_table + .rgid_m_tbl ALIGN(4) : > rgid_m_table + .rgid_r_tbl ALIGN(4) : > rgid_r_table + .rgid_w_tbl ALIGN(4) : > rgid_w_table + .rgid_sec_tbl ALIGN(4) : > rgid_sec_table + .rgid_axi_tbl ALIGN(4) : > rgid_axi_table + .rgid_gid_tbl ALIGN(4) : > rgid_gid_table + .data ALIGN(4) : > . + .text ALIGN(4) : > ipl_rom + .RE_CR.text ALIGN(4) : > . + .rosdata ALIGN(4) : > . + .rodata ALIGN(4) : > . + .secinfo ALIGN(4) : > . + + .rom_end ALIGN(4) : > . + .canary ALIGN(4) : > bss + .bss ALIGN(4) : > . + +// ROM mirror SECTIONS(RT-SRAM) + _start = ipl_top_addr; + .ROM_NOCOPY.reset ROM_NOCOPY(.reset) ALIGN(4) : > phys_vector_table + .ROM_NOCOPY.EIINTTBL_ICU ROM_NOCOPY(.EIINTTBL_ICU) ALIGN(4) : > . + .ROM_NOCOPY.qosbw_tbl ROM_NOCOPY(.qosbw_tbl) ALIGN(4) : > phys_qosbw_table + .ROM_NOCOPY.qoswt_tbl ROM_NOCOPY(.qoswt_tbl) ALIGN(4) : > phys_qoswt_table + .ROM_NOCOPY.rgid_m_tbl ROM_NOCOPY(.rgid_m_tbl) ALIGN(4) : > phys_rgid_m_table + .ROM_NOCOPY.rgid_r_tbl ROM_NOCOPY(.rgid_r_tbl) ALIGN(4) : > phys_rgid_r_table + .ROM_NOCOPY.rgid_w_tbl ROM_NOCOPY(.rgid_w_tbl) ALIGN(4) : > phys_rgid_w_table + .ROM_NOCOPY.rgid_sec_tbl ROM_NOCOPY(.rgid_sec_tbl) ALIGN(4) : > phys_rgid_sec_table + .ROM_NOCOPY.rgid_axi_tbl ROM_NOCOPY(.rgid_axi_tbl) ALIGN(4) : > phys_rgid_axi_table + .ROM_NOCOPY.rgid_gid_tbl ROM_NOCOPY(.rgid_gid_tbl) ALIGN(4) : > phys_rgid_gid_table + .ROM_NOCOPY.data ROM_NOCOPY(.data) ALIGN(4) : > . + .ROM_NOCOPY.text ROM_NOCOPY(.text) ALIGN(4) : > phys_ipl_rom + .ROM_NOCOPY.RE_CR.text ROM_NOCOPY(.RE_CR.text) ALIGN(4) : > . + .ROM_NOCOPY.rosdata ROM_NOCOPY(.rosdata) ALIGN(4) : > . + .ROM_NOCOPY.rodata ROM_NOCOPY(.rodata) ALIGN(4) : > . + .ROM_NOCOPY.secinfo ROM_NOCOPY(.secinfo) ALIGN(4) : > . + .cr_hot_plug_magic ALIGN(16): > . // This section must be placed at the last of binary. + + + +// +// RAM SECTIONS +// + .top.local.ram : > local_ram + .sdata ALIGN(4) : > . + .tdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .top_stack : > stack + .RT.stack ALIGN(4) PAD(stack_size) ABS : > . + .end_stack : > . + .used_by_bootrom ALIGN(4) PAD(bootrom_work_size) ABS : > bootrom_work // 0xFEDFF800 - 0xFEDFFFFF is prohibited writing + .end.local.ram : > . + + .sa9_load ALIGN(4) PAD(sa9_size) : > sa9_load +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader.S b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader.S new file mode 100644 index 0000000..e824f24 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader.S @@ -0,0 +1,168 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader start code + ******************************************************************************/ + + .global code_start + .global _loader_main + .global ___ghsend_RT_stack /* RT-SRAM stack Logical end address */ + .global ___ghs_set_stack_chk_guard + + BOOTROM_CODE_START_ADDRESS .set 0x01104000 /* Boot ROM start address */ + BOOTROM_CODE_END_ADDRESS .set 0x0112CFFC /* Boot ROM end address */ + SICREMAP_WINDOW_AREA_START_ADDRESS .set 0xFC000000 /* Remap 0 start address */ + SICREMAP_WINDOW_AREA_END_ADDRESS .set 0xFEBFFFFC /* SIC area end address */ + ICU_REGISTER_AREA_START_ADDRESS .set 0xFEDE0000 /* ICUMXB register area start address */ + ICU_REGISTER_AREA_END_ADDRESS .set 0xFFFEFFFC /* ICUMXB register area end address */ + + MPAT_SX_SR_ENABLE .set 0x000000E8 /* SV mode Read/Execution enable */ + MPAT_SW_SR_ENABLE .set 0x000000D8 /* SV mode Read/Writer enable */ + MPRC_E3_TO_E0_ENABLE .set 0x0000000F /* E0,E1,E2,E3 enable */ + MPM_SVP_MPE_ENABLE .set 0x00000003 /* SV mode protect enable, MPU enable */ + MPAT_ALL_DISABLE .set 0x00000040 + MPM_ALL_DISABLE .set 0x00000000 + + .section ".reset", "ax" + .align 2 + + +code_start: +/* ; initialize registers */ + mov r0, r1 + mov r0, r2 + mov r0, r3 + mov r0, r4 + mov r0, r5 + mov r0, r6 + mov r0, r7 + mov r0, r8 + mov r0, r9 + mov r0, r10 + mov r0, r11 + mov r0, r12 + mov r0, r13 + mov r0, r14 + mov r0, r15 + mov r0, r16 + mov r0, r17 + mov r0, r18 + mov r0, r19 + mov r0, r20 + mov r0, r21 + mov r0, r22 + mov r0, r23 + mov r0, r24 + mov r0, r25 + mov r0, r26 + mov r0, r27 + mov r0, r28 + mov r0, r29 + ldsr r0, 0, 0 + ldsr r0, 16, 0 + +/* set global pointer * + mov ___ghsbegin_sdabase, gp +/* set stack pointer */ + mov ___ghsend_RT_stack, sp + +/* MPU Disable */ + stsr 0, r6 ,5 + andi 0xFFFE, r6, r6 + ldsr r6, 0, 5 + SYNCM + +/* MPU setting */ + mov BOOTROM_CODE_START_ADDRESS, r12 /* MPLA0 */ + ldsr r12, 0, 6 + mov BOOTROM_CODE_END_ADDRESS, r12 /* MPUA0 */ + ldsr r12, 1, 6 + mov ___ghsbegin_reset, r12 /* MPLA1 */ + ldsr r12, 4, 6 + mov ___ghsend_rom_end, r12 /* MPUA1 */ + ldsr r12, 5, 6 + mov SICREMAP_WINDOW_AREA_START_ADDRESS, r12 /* MPLA2 */ + ldsr r12, 8, 6 + mov SICREMAP_WINDOW_AREA_END_ADDRESS, r12 /* MPUA2 */ + ldsr r12, 9, 6 + mov ICU_REGISTER_AREA_START_ADDRESS, r12 /* MPLA3 */ + ldsr r12, 12, 6 + mov ICU_REGISTER_AREA_END_ADDRESS, r12 /* MPUA3 */ + ldsr r12, 13, 6 + mov MPAT_SX_SR_ENABLE, r12 /* MPAT0 */ + ldsr r12, 2, 6 + mov MPAT_SX_SR_ENABLE, r12 /* MPAT1 */ + ldsr r12, 6, 6 + mov MPAT_SW_SR_ENABLE, r12 /* MPAT2 */ + ldsr r12, 10, 6 + mov MPAT_SW_SR_ENABLE, r12 /* MPAT3 */ + ldsr r12, 14, 6 + mov MPRC_E3_TO_E0_ENABLE, r12 /* MPRC */ + ldsr r12, 1, 5 + mov MPM_SVP_MPE_ENABLE, r12 /* MPM */ + ldsr r12, 0, 5 + SYNCM + +/* BSS clear */ + mov ___ghsbegin_bss, r6 + mov ___ghsend_bss, r7 + mov r0, r1 +loop_clear: + st.dw r0, 0[r6] + addi 8, r6, r6 + cmp r7, r6 + bl loop_clear + +/* Set canary before jump another function. */ +/* Don't call functions before calling __ghs_set_stack_chk_guard. */ + jarl ___ghs_set_stack_chk_guard, lp + + mov _loader_main, r2 + jarl [r2], lp + +/* Release MPU setting */ + mov MPM_ALL_DISABLE, r12 + ldsr r12, 0, 5 /* MPM */ + ldsr zero, 1, 5 /* MPRC */ + mov MPAT_ALL_DISABLE, r12 + ldsr r12, 2, 6 /* MPAT0 */ + ldsr r12, 6, 6 /* MPAT1 */ + ldsr r12, 10, 6 /* MPAT2 */ + ldsr r12, 14, 6 /* MPAT3 */ + ldsr zero, 0, 6 /* MPLA0 */ + ldsr zero, 1, 6 /* MPUA0 */ + ldsr zero, 4, 6 /* MPLA1 */ + ldsr zero, 5, 6 /* MPUA1 */ + ldsr zero, 8, 6 /* MPLA2 */ + ldsr zero, 9, 6 /* MPUA2 */ + ldsr zero, 12, 6 /* MPLA3 */ + ldsr zero, 13, 6 /* MPUA3 */ + SYNCM + + jmp [r10] + nop + halt + + .section ".padding" + .align 4 diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader_main_common.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader_main_common.c new file mode 100644 index 0000000..e29c7e8 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader_main_common.c @@ -0,0 +1,270 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main common function + ******************************************************************************/ +/****************************************************************************** + * @file loader_main_common.c + * - Version : 0.04 + * @brief 1.Output boot message. + * 2.Judge boot mode. + * 3.Set BL31 parameter. + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.04.2022 0.01 First Release + * : 04.04.2023 0.02 Removed stdio.h. + * : 21.08.2023 0.03 Add support for V4M. + * : 19.09.2023 0.04 Add log output for build option LSI. + *****************************************************************************/ + +#include +#include /* NULL pointer */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RST_MODEMR0_MD5 (0x00000020U) + +/* Define for Work Around of APMU */ +#define CL0GRP3_BIT (1U << 3) +#define CL1GRP3_BIT (1U << 7) +#define RTGRP3_BIT (1U << 19) +#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) + +static void judge_bootmode(uint32_t lcs); + +/* global variable */ +uint32_t is_verify = SECURE_BOOT; + +static void judge_bootmode(uint32_t lcs) +{ + uint32_t md; + + /* LCS Status check */ + if((lcs != LCS_CM) + && (lcs != LCS_DM) + && (lcs != LCS_SD) + && (lcs != LCS_SE) + && (lcs != LCS_FA)) + { + ERROR("LCS state error." + "LCS = 0x%x", lcs); + panic; + } + + md = (mem_read32(RST_MODEMR0) & RST_MODEMR0_MD5) >> 5U; + if (lcs == LCS_SE) + { + /* LCS=SE => Secure boot */ + is_verify = SECURE_BOOT; + } + else if ((lcs != LCS_SD) && (md == 0U)) + { + /* LCS=CM/DM/FA and MD5=0 => Secure boot */ + is_verify = SECURE_BOOT; + } + else + { + /* LCS=SD or MD5=1 => Normal boot */ + is_verify = NORMAL_BOOT; + } + + if (NORMAL_BOOT != is_verify) + { + NOTICE("Secure boot(ICUMX)\n"); + } + else + { + NOTICE("Normal boot(ICUMX)\n"); + } +} +/* End of function judge_bootmode(uint32_t lcs) */ + +void print_boot_msg(void) +{ + uint32_t lcs = 0U; /* store LCS state */ + uint32_t lcs_size = sizeof(lcs); + uint32_t prr; + uint32_t reg; /* store register value */ + uint32_t ret; /* store return value */ + __attribute__((__unused__)) const char *str; + __attribute__((__unused__)) const char *product_s4 = "S4"; + __attribute__((__unused__)) const char *product_v4h = "V4H"; + __attribute__((__unused__)) const char *product_v4m = "V4M"; + __attribute__((__unused__)) const char *unknown = "unknown"; + __attribute__((__unused__)) const char *boot_hyper80_160= "HyperFlash"; + __attribute__((__unused__)) const char *boot_serial40 = "Serial Flash"; + __attribute__((__unused__)) const char *boot_qspi80_160 = "Octal SPI Flash"; + __attribute__((__unused__)) const char *boot_emmc50x8 = "eMMC(50MHz x8)"; + const char *lcs_name[8U] = { + [LCS_CM] = "CM", + [LCS_DM] = "DM", + [LCS_SD] = "SD", + [LCS_SE] = "SE", + [LCS_FA] = "FA", + }; + + NOTICE("ICUMX Loader Rev.%s\n", IPL_VERSION); + + NOTICE("LSI=%d (Build Option : S4=0, V4H=1, V4M=2)\n", RCAR_LSI); + + NOTICE("%s\n", build_message); +#if (BOOT_TIME_CHECK != 0) + gpio_N1305(2); +#endif + /* Get PRR */ + prr = mem_read32(PRR); + prr &= (PRR_PRODUCT_MASK | PRR_MAJOR_MASK | PRR_MINOR_MASK); + switch (prr & PRR_PRODUCT_MASK) + { + case PRR_PRODUCT_S4: + { + str = product_s4; + break; + } + case PRR_PRODUCT_V4H: + { + str = product_v4h; + break; + } + case PRR_PRODUCT_V4M: + { + str = product_v4m; + break; + } + default: + { + str = unknown; + break; + } + } + NOTICE("PRR is R-Car %s Ver%d.%d\n", str, + ((prr & PRR_MAJOR_MASK) >> PRR_MAJOR_SHIFT) + PRR_MAJOR_OFFSET, + (prr & PRR_MINOR_MASK)); + + reg = mem_read32(RST_MODEMR0); + reg &= RST_MODEMR0_BOOT_DEV_MASK; + + switch (reg) + { + case RST_MODEMR0_BOOT_DEV_HYPERFLASH160: + case RST_MODEMR0_BOOT_DEV_HYPERFLASH80: + { + str = boot_hyper80_160; + break; + } + case RST_MODEMR0_BOOT_DEV_SERIAL_FLASH40: + case RST_MODEMR0_BOOT_DEV_SERIAL_FLASH: + { + str = boot_serial40; + break; + } + case RST_MODEMR0_BOOT_DEV_QSPI_FLASH80: + { + str = boot_qspi80_160; + break; + } + case RST_MODEMR0_BOOT_DEV_EMMC_50X8: + { + str = boot_emmc50x8; + break; + } + default: + { + str = unknown; + break; + } + } + NOTICE("Boot device is %s(0x%x)\n", str, reg); +#if (QSPI_DDR_MODE==1) + NOTICE("Change QSPI DDR Transfer mode\n"); +#endif + + /* Get LCS state */ + ret = call_ROM_GetLcs(&lcs, lcs_size); + str = unknown; + if (ret == ROMAPI_OK) + { + if (NULL != lcs_name[lcs]) + { + str = lcs_name[lcs]; + } + } + NOTICE("LCM state is %s\n", str); + + /* If PRR is S4 Ver.1.0 */ + if ((PRR_PRODUCT_S4 == (prr & PRR_PRODUCT_MASK)) && (0U == (prr & PRR_CUT_MASK))) + { + set_sicremap_s4v10(); /* downgrade SICREMAP setting. */ + is_verify = NORMAL_BOOT;/* S4 Ver.1.0 is Normal Boot only. */ + } + else + { + /* LCS judgement for secure boot */ + judge_bootmode(lcs); + } + +#if (SET_FCPR_PARAM == FCPR_ENABLE) + NOTICE("Data Compression Enable\n"); + NOTICE("Start address = 0x%08x End address = 0x%08x\n", COMPRESSION_START_ADDR, COMPRESSION_END_ADDR); +#endif + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + NOTICE("Access protection Enable\n"); +#endif +} +/* End of function print_boot_msg(void) */ + +/* Work Around setting for APMU */ +void wa_setting_apmu(void) +{ + uint32_t apmu_tmp; + + /* Work Around setting for D0_ACCENR-DOMAIN3_ACCENR */ + apmu_tmp = mem_read32(APMU_D0_ACCENR); + apmu_tmp |= APMU_ACC_ENB_FOR_ARM_CPU; + apmu_reg_write(APMU_D0_ACCENR, apmu_tmp); + + apmu_tmp = mem_read32(APMU_D1_ACCENR); + apmu_tmp |= APMU_ACC_ENB_FOR_ARM_CPU; + apmu_reg_write(APMU_D1_ACCENR, apmu_tmp); + + apmu_tmp = mem_read32(APMU_D2_ACCENR); + apmu_tmp |= APMU_ACC_ENB_FOR_ARM_CPU; + apmu_reg_write(APMU_D2_ACCENR, apmu_tmp); + + apmu_tmp = mem_read32(APMU_D3_ACCENR); + apmu_tmp |= APMU_ACC_ENB_FOR_ARM_CPU; + apmu_reg_write(APMU_D3_ACCENR, apmu_tmp); +} +/* End of function wa_setting_apmu(void) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader_main_s4.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader_main_s4.c new file mode 100644 index 0000000..2d556af --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader_main_s4.c @@ -0,0 +1,490 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main function + ******************************************************************************/ +/****************************************************************************** + * @file loader_main.c + * - Version : 0.15 + * @brief 1. IP initialization. + * 2. DMA transfer the binary image from Flash to RAM. + * 3. Authentication of the transferred image. + * 4. Boot CR and CA core. + * 5. Release of used resources. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Modify macro definition name. + * Add process to call rpc_release function. + * : 30.09.2021 0.03 Support of eMMC boot. + * : 15.10.2021 0.04 Modified the MCU boot sequence. + * remove include of Flash/eMMC. + * : 03.12.2021 0.05 Add RT-VRAM extend mode. + * : CA IPL boot support + * : 06.01.2022 0.06 Support for two-stage boot of G4MH + * : Add the Reset mask release process for RWDT. + * : Add exception handling for ICUMX_WDTA. + * : 20.01.2022 0.07 Capture DDR rev.0.02rc11 + * Add ICUMX name unification. + * : 28.02.2022 0.08 Modify the process of setting the parameters + * used by BL31 in IPL. + * : 14.04.2022 0.09 Fixed Set SDCLK to 200MHz. + * : 23.05.2022 0.10 Integration of S4 and V4H + * Renamed from loader_main.c to loader_main_s4.c. + * : 04.07.2022 0.11 Change loading Control Domain process to + * calling load_main_for_mcu() function. + * : 05.08.2022 0.12 Add authentication of software minimum + * version table. + * : 30.09.2022 0.13 Modify pre-process pranch in load_main_for_mcu + * function. + * Modify authentication process of software + * minimum version. + * : 12.01.2023 0.14 Modified argument to fixed + * when calls smoni_set_param() function. + * Modified processing sequence for Access + * protection. + * : 04.04.2023 0.15 Removed stdio.h. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Provided code */ +#include "../ip/ddr/boot_init_dram.h" +# if (ECC_ENABLE == 1) + #include "../ip/ddr/s4/lpddr4x/ecc_enable_s4.h" +# endif + +#define CA_IPL (0U) +#define BL31 (1U) + +#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U) +#define WDTRSTCR_PASSWORD (0xA55A0000U) + +/* flag of set BL31 parameter*/ +#define CA_APP_SET_PARAM_ENABLE (1U) +/* Calculation set address for BL31 parameter */ +#define SMONI_IPL_PARAM_OFFSET (0x00022200U) +#define SMONI_EP_INFO_OFFSET (SMONI_IPL_PARAM_OFFSET + 0x0030U) +#define OPTEE_EP_INFO_OFFSET (SMONI_IPL_PARAM_OFFSET + 0x0088U) +#define BL31_KIND_BOOT_ADDR (SMONI_IPL_PARAM_OFFSET + 0x0D00U) +/* KIND BOOT flag*/ +#define BL31_COLD_BOOT (0x0000000000000000U) +#define BL31_WARM_BOOT (0x0000000000000001U) +#define SMONI_KIND_BOOT_PARAM (0xFFFFFFFFFFFFFFFFU) +/* Program top address of Secure Monitor(BL31), OP-TEE and u-boot. */ +#define SMONI_PHYS_TOP_ADDR (0x46400000U) +#define OPTEE_PHYS_TOP_ADDR (0x44100000U) +#define UBOOT_PHYS_TOP_ADDR (0x50000000U) + +/* struct */ +typedef struct{ + uint8_t uctype; + uint8_t ucversion; + uint16_t ussize; + uint32_t uiattr; + uint32_t psecmonimageinfo_low; + uint32_t psecmonimageinfo_high; + uint32_t psecoptepinfo_low; + uint32_t psecoptepinfo_high; + uint32_t psecoptimageinfo_low; + uint32_t psecoptimageinfo_high; + uint32_t pnonsecepinfo_low; + uint32_t pnonsecepinfo_high; + uint32_t pnonsecimageinfo_low; + uint32_t pnonsecimageinfo_high; +}st_smoni_iplparams_t; + +typedef struct{ + uint8_t uctype; + uint8_t ucversion; + uint16_t ussize; + uint32_t uiattr; + uint32_t ulpc_low; + uint32_t ulpc_high; + uint32_t ulspsr_low; + uint32_t ulspsr_high; + uint32_t ularg0_low; + uint32_t ularg0_high; + uint32_t ularg1_low; + uint32_t ularg1_high; + uint32_t ularg2_low; + uint32_t ularg2_high; + uint32_t ularg3_low; + uint32_t ularg3_high; + uint32_t ularg4_low; + uint32_t ularg4_high; + uint32_t ularg5_low; + uint32_t ularg5_high; + uint32_t ularg6_low; + uint32_t ularg6_high; + uint32_t ularg7_low; + uint32_t ularg7_high; +}st_smoni_entrypointinfo_t; + +static void load_main_for_mcu(const LOAD_INFO *li, uint32_t is_verify); +static void smoni_set_param(uint32_t smoni_entry_point, + uint32_t tee_entry_point, + uint32_t uboot_entry_point); + +static void load_main_for_mcu(const LOAD_INFO *li); + +#if ((CR_SECURE_DEBUG == SECURE_DEBUG_ENABLE) || (ADD_HOTPLUG_MAGIC == ADD_MAGIC_NUMBER)) +#define HOTPLUG_MAGIC_NUM (0x853F912EU) +#else +#define HOTPLUG_MAGIC_NUM (0x00000000U) +#endif +__attribute__ ((section (".cr_hot_plug_magic"))) const uint32_t magic_num[4] = {0x00000000U, 0x00000000U, + 0x00000000U, HOTPLUG_MAGIC_NUM}; + +uint32_t loader_main(void) +{ + uint32_t reg; /* store register value */ + int32_t result; /* store result of ddr_init() */ + uint32_t is_verify = SECURE_BOOT; + uint32_t boot_ca_id; + uint32_t auth_count = 0U; + __attribute__((__unused__)) uint32_t loop = 0U; + __attribute__((__unused__)) uint32_t ca_load_num; /* number of load for Optional CA program */ + LOAD_INFO li[MAX_PLACED] = {0U}; + + +/***************************************************************************** + * Initialize Hardware + *****************************************************************************/ + /* IP initialize */ + ip_init(); + + /* Unmask the detection of RWDT overflow */ + reg = mem_read32(RST_WDTRSTCR); + reg &= ~WDTRSTCR_RWDT_RSTMSK; + reg |= WDTRSTCR_PASSWORD; + mem_write32(RST_WDTRSTCR, reg); + +# if (ECC_ENABLE == 1) +/***************************************************************************** + * ECC and EDC Initialize + *****************************************************************************/ + ecc_rtsram_enable(); + edc_axi_enable(); + edc_vram_enable(); +#endif + +/***************************************************************************** + * Work Around for APMU + *****************************************************************************/ + wa_setting_apmu(); + +/***************************************************************************** + * Output boot message + *****************************************************************************/ + is_verify =print_boot_msg(); + +/***************************************************************************** + * Setting Access protection + *****************************************************************************/ + /* Region ID access protection */ + rgid_protection(); + ram_protection(); + + /* Change the Region ID (Master) of the Module used for data transfer to a temporary setting. */ + set_master_rgid_4_tfr_mod(); + +/***************************************************************************** + * Load Certficate from QSPI + *****************************************************************************/ + /* Load content certificate */ + ca_load_num = load_content_cert(); + + /* Get load information */ + load_init(li); + +/***************************************************************************** + * Authenticate Software minimum version table + *****************************************************************************/ + auth_min_ver_tbl(is_verify, li); + +/***************************************************************************** + * Load Control Domain + *****************************************************************************/ + load_main_for_mcu(li, is_verify); + +/***************************************************************************** + * DDR Initialization + *****************************************************************************/ + + /* DDR initialize */ + result = InitDram(); + if (INITDRAM_OK != result) + { + ERROR("Failed to DRAM initialize (%d).\n", result); + panic; + } + +#if (ECC_ENABLE == 1) + /* ECC Protection */ + enable_ecc(); +#endif /* ECC_ENABLE */ + + /* QoS configuration */ + qos_init(); + + /* RT-VRAM Extend mode */ + rtvram_extendmode(); + +/***************************************************************************** + * Load RTOS from Flash + *****************************************************************************/ + /* Start loading RTOS image from Flash into SDRAM */ + load_image(&li[RTOS_ID]); + + /* finish loading RTOS */ + load_end(); + + +/***************************************************************************** + * Load Cx IPL from Flash + *****************************************************************************/ +#if (CA_LOAD_TYPE == CA_IPL) + /* Start loading Cx IPL image from Flash into SDRAM */ + load_image(&li[CA_PROGRAM_ID]); + + /* Authenticate of RTOS */ + rom_secureboot(is_verify, &li[RTOS_ID]); + + /* boot CR */ + arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr); + + /* The CA image to boot is CA IPL. */ + boot_ca_id = CA_PROGRAM_ID; + + /* finish loading Cx IPL */ + load_end(); +#elif (CA_LOAD_TYPE == BL31) + /* Authenticate of RTOS */ + rom_secureboot(is_verify, &li[RTOS_ID]); + + /* boot CR */ + arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr); + + /* The CA image to boot is CA prgram#1. */ + boot_ca_id = CA_OPTIONAL_ID; + +/***************************************************************************** + * Load CA Program#1--#8 from Flash + *****************************************************************************/ + /* Start loading CA Program#n image from Flash into SDRAM */ + for (loop = 0U; loop < ca_load_num; loop++) + { + /* Loading start */ + load_image(&li[boot_ca_id + loop]); + + /* Authenticate of CA Program#n-1 */ + if (loop != 0U) + { + rom_secureboot(is_verify, &li[boot_ca_id + loop - 1U]); + auth_count++; + } + + /* finish loading CA Program#n */ + load_end(); + } +#endif /* (CA_LOAD_TYPE == CA_IPL) */ +/***************************************************************************** + * Load Secure Firmware from Flash + *****************************************************************************/ + /* Start loading Secure FW image from Flash into SDRAM */ + load_image(&li[SECURE_FW_ID]); + + /* Authenticate of Cx IPL or CA Program#n */ + rom_secureboot(is_verify, &li[boot_ca_id + auth_count]); + + /* Set Secure Monitor parameter */ + smoni_set_param(SMONI_PHYS_TOP_ADDR, /* BL31 */ + OPTEE_PHYS_TOP_ADDR, /* OP-TEE */ + UBOOT_PHYS_TOP_ADDR); /* U-Boot */ + + /* boot CA */ + arm_cpu_on(RCAR_PWR_TARGET_CA, li[boot_ca_id].boot_addr); + + /* finish loading Secure Firmware */ + load_end(); + + /* load_secure data(for ICUMXB) */ + load_securedata(SECURE_FW_ID); + + /* Authenticate of Secure Firmware */ + rom_secureboot(is_verify, &li[SECURE_FW_ID]); + + /* finish loading secure data */ + load_end(); + + /* Finally Protection setting */ + ram_protection_final(); + rgid_protection_final(); + +#if (ECC_ENABLE == 1) + /* Notice the ecc enable */ + NOTICE("Enabled ECC and EDC for RT-SRAM, AXI, VRAM, SDRAM. \n"); +# endif + NOTICE("Load finish.\n"); + ip_release(); + + return remap_get_remap_addr(li[SECURE_FW_ID].boot_addr); +} +/* End of function loader_main(void) */ + +static void load_main_for_mcu(const LOAD_INFO *li, uint32_t is_verify) +{ +#if (BOOT_MCU != 0U) + mcu_load_main(li, is_verify); +#endif /* (BOOT_MCU != 0U) */ +} +/* End of function load_main_for_mcu(const LOAD_INFO *li, uint32_t is_verify) */ + +static void smoni_set_param(uint32_t smoni_entry_point, + uint32_t tee_entry_point, + uint32_t uboot_entry_point) +{ +#if (SET_CA_PARAM == CA_APP_SET_PARAM_ENABLE) + uint32_t mapped_addr; + st_smoni_iplparams_t *smoni_ipl_param; + st_smoni_entrypointinfo_t *smoni_ep_info; + st_smoni_entrypointinfo_t *optee_ep_info; + + remap_register(smoni_entry_point, &mapped_addr); + + /* set struct address */ + smoni_ipl_param = (st_smoni_iplparams_t *) + (mapped_addr + SMONI_IPL_PARAM_OFFSET); + smoni_ep_info = (st_smoni_entrypointinfo_t *) + (mapped_addr + SMONI_EP_INFO_OFFSET); + optee_ep_info = (st_smoni_entrypointinfo_t *) + (mapped_addr + OPTEE_EP_INFO_OFFSET); + + + + /* set parameter */ + smoni_ipl_param->uctype = 0x03U; + smoni_ipl_param->ucversion = 0x01U; + smoni_ipl_param->ussize = 0x0030U; + smoni_ipl_param->uiattr = 0x00000000U; + smoni_ipl_param->psecmonimageinfo_low = 0x00000000U; + smoni_ipl_param->psecmonimageinfo_high = 0x00000000U; + smoni_ipl_param->psecoptepinfo_low = 0x00000000U; + smoni_ipl_param->psecoptepinfo_high = 0x00000000U; + smoni_ipl_param->psecoptimageinfo_low = 0x00000000U; + smoni_ipl_param->psecoptimageinfo_high = 0x00000000U; + smoni_ipl_param->pnonsecepinfo_low = + remap_get_phys_addr((uint32_t)smoni_ep_info); + smoni_ipl_param->pnonsecepinfo_high = 0x00000000U; + smoni_ipl_param->pnonsecimageinfo_low = 0x00000000U; + smoni_ipl_param->pnonsecimageinfo_high = 0x00000000U; + + smoni_ep_info->uctype = 0x01U; + smoni_ep_info->ucversion = 0x01U; + smoni_ep_info->ussize = 0x0058U; /* structure size */ + smoni_ep_info->uiattr = 0x00000001U; /* SECURE */ + smoni_ep_info->ulpc_low = uboot_entry_point; + smoni_ep_info->ulpc_high = 0x00000000U; + /* SPSR_EL3.E[9] = b1 (BigEndian) * + * .A[8] = b1 (DataAbort MASK) * + * .I[7] = b1 (IRQ MASK) * + * .F[6] = b1 (FIQ MASK) * + * .M[4] = b0 (AArcch64) * + * .M[3:1] = b0101 (EL1h) */ + smoni_ep_info->ulspsr_low = 0x000003C5U; + smoni_ep_info->ulspsr_high = 0x00000000U; + smoni_ep_info->ularg0_low = 0x00000000U; + smoni_ep_info->ularg0_high = 0x00000000U; + smoni_ep_info->ularg1_low = 0x00000000U; + smoni_ep_info->ularg1_high = 0x00000000U; + smoni_ep_info->ularg2_low = 0x00000000U; + smoni_ep_info->ularg2_high = 0x00000000U; + smoni_ep_info->ularg3_low = 0x00000000U; + smoni_ep_info->ularg3_high = 0x00000000U; + smoni_ep_info->ularg4_low = 0x00000000U; + smoni_ep_info->ularg4_high = 0x00000000U; + smoni_ep_info->ularg5_low = 0x00000000U; + smoni_ep_info->ularg5_high = 0x00000000U; + smoni_ep_info->ularg6_low = 0x00000000U; + smoni_ep_info->ularg6_high = 0x00000000U; + smoni_ep_info->ularg7_low = 0x00000000U; + smoni_ep_info->ularg7_high = 0x00000000U; + + optee_ep_info->uctype = 0x01U; + optee_ep_info->ucversion = 0x02U; + optee_ep_info->ussize = 0x0058U; + optee_ep_info->uiattr = 0x00000008U; + optee_ep_info->ulpc_low = tee_entry_point; + optee_ep_info->ulpc_high = 0x00000000U; + optee_ep_info->ulspsr_low = 0x000003C5U; + optee_ep_info->ulspsr_high = 0x00000000U; + optee_ep_info->ularg0_low = 0x00000000U; + optee_ep_info->ularg0_high = 0x00000000U; + optee_ep_info->ularg1_low = 0x00000000U; + optee_ep_info->ularg1_high = 0x00000000U; + optee_ep_info->ularg2_low = 0x00000000U; + optee_ep_info->ularg2_high = 0x00000000U; + optee_ep_info->ularg3_low = 0x00000000U; + optee_ep_info->ularg3_high = 0x00000000U; + optee_ep_info->ularg4_low = 0x00000000U; + optee_ep_info->ularg4_high = 0x00000000U; + optee_ep_info->ularg5_low = 0x00000000U; + optee_ep_info->ularg5_high = 0x00000000U; + optee_ep_info->ularg6_low = 0x00000000U; + optee_ep_info->ularg6_high = 0x00000000U; + optee_ep_info->ularg7_low = 0x00000000U; + optee_ep_info->ularg7_high = 0x00000000U; + + mapped_addr += BL31_KIND_BOOT_ADDR; + mem_write32((mapped_addr), (uint32_t)((uint64_t)BL31_COLD_BOOT & 0xFFFFFFFFU)); + mem_write32(((mapped_addr) + 0x4U), + (uint32_t)(((uint64_t)BL31_COLD_BOOT >> 32U) & 0xFFFFFFFFU)); + + remap_unregister(mapped_addr); +#endif /* (SET_CA_PARAM == CA_APP_SET_PARAM_ENABLE) */ +} +/* End of function smoni_set_param(uint32_t smoni_entry_point) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader_main_v4h.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader_main_v4h.c new file mode 100644 index 0000000..9d45e81 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader_main_v4h.c @@ -0,0 +1,496 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main function for V4H + ******************************************************************************/ +/****************************************************************************** + * @file loader_main.c + * - Version : 0.14 + * @brief 1. IP initialization. + * 2. DMA transfer the binary image from Flash to RAM. + * 3. Authentication of the transferred image. + * 4. Boot CR and CA core. + * 5. Release of used resources. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Modify macro definition name. + * Add process to call rpc_release function. + * : 30.09.2021 0.03 Support of eMMC boot. + * : (30.11.2021 0.04) Support boot sequence of V4H. + * : 03.12.2021 0.05 Add RT-VRAM extend mode. + * : 23.05.2022 0.06 Integration of S4 and V4H + * Renamed from loader_main.c to loader_main_v4h.c. + * : 05.08.2022 0.07 Add authentication of software minimum + * version table. + * : 30.09.2022 0.08 Modify authentication process of software + * minimum version. + * : 20.01.2023 0.09 Add W/A OTLINT-5556: increased latency + * : 17.04.2023 0.10 Add setting for V4H v2.x leak current reduce + * Removed stdio.h. + * Add certificate authentication functions to be + * execute before image transfer. + * : 15.05.2023 0.11 Change the jump address of secure firmware from + * on SIC remap area to CF remap area. + * : 13.06.2024 0.12 Updated ECM register setting in wa_for_v4h2 + * function. + * : 27.12.2024 0.13 Change the location of ECC and EDC + * initialization function. + * : 07.04.2025 0.14 Added ecm_init_setting function calling. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rcar_def.h" +#if (ECM_ERROR_ENABLE == 1) +#include "../ip/ddr/v4h/lpddr5/ecm_enable_v4h.h" +#endif /* ECM_ERROR_ENABLE == 1 */ + +/* Provided code */ +#include "../ip/ddr/boot_init_dram.h" +#include "../ip/ddr/v4h/lpddr5/ecc_enable_v4h.h" +#include +#include +#include + +/* Time analysis */ +#include +#include +#if (0 == (MEASURE_TIME)) + #define store_time_checkpoint(x,y) + #define print_time_checkpoints(x) +#endif +#include + +#define ICISTP_BASE (BASE_ICISTP_ADDR) +#define ICISTPSTPER000 (ICISTP_BASE + 0x30300U) + +#define EDC_BASE (BASE_ECM_ADDR) +#define EDCSTRT20 (EDC_BASE + 0x80C0U) +#define TIDSTRT20 (EDC_BASE + 0x81C0U) + +/* SYSC register */ +#define SYSC_BASE (BASE_SYSC_ADDR) +#define SYSC_SYSCSR (SYSC_BASE + 0x0000U) /* SYSC Status Register */ +#define SYSC_SYSCISCR1 (SYSC_BASE + 0x0814U) /* Interrupt Status/Clear Register1 */ +#define SYSC_SYSCIER1 (SYSC_BASE + 0x0824U) /* Interrupt Enable Register1 */ +#define SYSC_SYSCIMR1 (SYSC_BASE + 0x0834U) /* Interrupt MASK Register1 */ + +/* Power Domain Register */ +#define SYSC_PDR41 (0x0A40U) /* A1CNN0 */ +#define SYSC_PDR42 (0x0A80U) /* A2CN0 */ +#define SYSC_PDR43 (0x0AC0U) /* A3IR */ +#define SYSC_PDRSR (SYSC_BASE + 0x1000U) /* Base address of Power Domain Status Register */ +#define SYSC_PDRSR41 (SYSC_PDRSR + (SYSC_PDR41)) +#define SYSC_PDRSR42 (SYSC_PDRSR + (SYSC_PDR42)) +#define SYSC_PDRSR43 (SYSC_PDRSR + (SYSC_PDR43)) +#define SYSC_PDRONCR (SYSC_BASE + 0x1004U) /* Base address of Power Domain Power-ON Control Register */ +#define SYSC_PDRONCR41 (SYSC_PDRONCR + (SYSC_PDR41)) +#define SYSC_PDRONCR42 (SYSC_PDRONCR + (SYSC_PDR42)) +#define SYSC_PDRONCR43 (SYSC_PDRONCR + (SYSC_PDR43)) + +#define PDR_MAX (3U) /* Number of PDR's to be set */ +#define SYSC_BIT_PDR41 (0x00000200U) /* SYSC register target PDR41 bit */ +#define SYSC_BIT_PDR42 (0x00000400U) /* SYSC register target PDR42 bit */ +#define SYSC_BIT_PDR43 (0x00000800U) /* SYSC register target PDR43 bit */ + +#define SYSCSR_BUSY_MASK (0x00000003U) /* SYSC Power On or Power Off seaquence status */ +#define SYSCSR_NOT_BUSY (0x00000003U) /* Not processing */ + +#define SYSC_PDRSR_PWR_MASK (0x00001111U) /* PDR Power On / Off Status MASK */ +#define SYSC_PDRSR_PWROFF (0x00000001U) /* PDR Power OFF Status */ +#define SYSC_PDRONCR_PWRON (0x00000001U) /* PDR Power On request */ +#define SYSC_PDR_PWR_PROC (0x00000000U) /* PDR Power On or Poweer off processing */ + +#define RGID_SET_RGID_FIN_FLG_ADDR (0xFD95EFFCU) /* 0xE635EFFC:Remap 12 */ +#define RGID_SET_RGID_FIN_FLG_VAL (0x64U) + + +#if (ADD_HOTPLUG_MAGIC == ADD_MAGIC_NUMBER) +#define HOTPLUG_MAGIC_NUM (0x853F912EU) +#else +#define HOTPLUG_MAGIC_NUM (0x00000000U) +#endif +__attribute__ ((section (".cr_hot_plug_magic"))) const uint32_t magic_num[4] = {0x00000000U, 0x00000000U, + 0x00000000U, HOTPLUG_MAGIC_NUM}; + +/* Prototype functions */ +#include +static void wa_for_v4h2(void); +static void set_leak_current_reduce_for_v4h2x(void); + +uint32_t loader_main(void) +{ + uint32_t boot_ca_id; + uint32_t auth_count = 0U; + uint32_t boot_cpu; + uint32_t tmp; + __attribute__((__unused__)) uint32_t loop = 0U; + __attribute__((__unused__)) uint32_t ca_load_num; /* number of load for Optional CA program */ + LOAD_INFO li[MAX_PLACED] = {0U}; + +#if (1 == (MEASURE_TIME)) + scmt_module_start(); + store_time_checkpoint("loader_main", 0); +#endif +#if (SAN_ENABLE == 1) + /* Appendix A Sequence of Activation + step (5) Stop RWDT and System WDT */ + rwdt_init(0); + swdt_init(0); +#endif +/***************************************************************************** + * Initialize Hardware + *****************************************************************************/ + /* IP initialize, step(6) of Sequence of Activation? */ + ip_init(); + +#if (ECM_ERROR_ENABLE == 1) + ecm_init_setting(); +#endif /* ECM_ERROR_ENABLE == 1 */ +/***************************************************************************** + * Work Around for APMU + *****************************************************************************/ + wa_setting_apmu(); + +/***************************************************************************** + * Output boot message + *****************************************************************************/ + print_boot_msg(); +/***************************************************************************** + * WA for V4H ver2.0 + *****************************************************************************/ + uint32_t Prr_Cut; + Prr_Cut = mem_read32(PRR) & PRR_CUT_MASK; + + if (Prr_Cut >= PRR_PRODUCT_20) + { + /* IPL setting for V4H v2.x leak current reduce */ + set_leak_current_reduce_for_v4h2x(); + + wa_for_v4h2(); + } + + /* WA OTLINT-5556 increased latency: APMU FRSTCTRL bit[29] disable */ + tmp = mem_read32(BASE_APMU_ADDR + 0x68U); + tmp = tmp & ~(1 << 29); + mem_write32((BASE_APMU_ADDR + 0x68U), tmp); + +#if (ECM_ENABLE == 1) +/***************************************************************************** + * ECC and EDC Initialize + *****************************************************************************/ + edc_axi_enable(); + edc_vram_enable(); +#endif + +#if (SAN_ENABLE == 1) + /* step(7) Initial Checks */ + SM_6_3_1(); + SM_6_3_2(); + SM_5_3_6(); + SM_5_1(); + SM_6_23(); + SM_4_21(); + SM_5_1_6(); + SM_5_2_6(); + SM_6_2(); + SM_6_11(); + SM_6_14_6(); + SM_6_22(); + SM_6_24_2(); + SM_6_24_3(); + SM_6_29(); + SM_6_30(); + PMIC_SM_27A(); + PMIC_SM_27B(); + PMIC_SM_27C(); + PMIC_SM_27D(); + + /* step(8) start the timers for Periodical checks */ + + check_SoC_Activation(); + /* step(9) send the first WDT message */ + PMIC_SM_12_wdt(); +#endif +/***************************************************************************** + * Setting Access protection + *****************************************************************************/ + /* Region ID access protection */ + rgid_protection(); + ram_protection(); + + /* Change the Region ID (Master) of the Module used for data transfer to a temporary setting. */ + set_master_rgid_4_tfr_mod(); + +/***************************************************************************** + * Clear ECM Status Bits + *****************************************************************************/ + /* Check the V4H is v1.0 */ + if(Prr_Cut == PRR_PRODUCT_10) + { + clear_ecm_st_axi(); + } + store_time_checkpoint("init_done", 0); + +/***************************************************************************** + * Load Certficate from QSPI + *****************************************************************************/ + int slot; + + slot = ab_select_slot(); +#ifndef STRICT_AB_BOOTING +#warning "STRICT_AB_BOOTING is not defined, using default slot selection" + if (slot < 0) { + ERROR("Failed to select slot: %d, using default slot\n", slot); + slot = 0; + } else +#endif + NOTICE("slot: %d\n", slot); + + /* Load content certificate */ + ca_load_num = load_content_cert(slot); + store_time_checkpoint("load_cert_done", + CONTENT_CERT_INFO_SIZE + ca_load_num*CONTENT_CERT_SIZE); + + /* Get load information */ + load_init(li, slot); + + /* verify the each content certs before Image load */ + preload_verify_cntcert(li); + +/***************************************************************************** + * Authenticate Software minimum version table + *****************************************************************************/ + auth_min_ver_tbl(li); + store_time_checkpoint("verify_cert_done", 0); + +/***************************************************************************** + * Load Cx IPL from Flash + *****************************************************************************/ + /* Start loading Cx IPL image from Flash into SDRAM */ + load_image(&li[CA_PROGRAM_ID]); + + /* The CA image to boot is CA IPL. */ + boot_ca_id = CA_PROGRAM_ID; + + /* boot CPU is CR */ + boot_cpu = RCAR_PWR_TARGET_CR; + + /* finish loading Cx IPL */ + load_end(); + store_time_checkpoint("load_Cx_IPL_done", li[CA_PROGRAM_ID].image_size); +#if (BOOT_TIME_CHECK != 0) + gpio_N1305(2); +#endif + /* Set V4H_SDRDES_1V8(GP1_23) to high before optee start */ + gpio_V4H_SERDES_1V8_en(1); +/***************************************************************************** + * Load Secure Firmware from Flash + *****************************************************************************/ + /* Start loading Secure FW image from Flash into SDRAM */ + load_image(&li[SECURE_FW_ID]); + store_time_checkpoint("load_Secure_FW_start (DMA-background)", li[SECURE_FW_ID].image_size); + + /* Authenticate of CA Program#n */ + rom_secureboot(&li[boot_ca_id + auth_count]); + store_time_checkpoint("verify_Cx_IPL_done", 0); + + /* SystemRAM has an undefined initial value, clear the address of + * the SystemRAM that is going to store set finish flag of RGID. */ + mem_write8(RGID_SET_RGID_FIN_FLG_ADDR, 0xFFU); + + /* Before Boot CPU, Set the division ratio for CPU operating frequency */ + adj_cr_variant_freq(); + + /* boot CA */ + arm_cpu_on(boot_cpu, li[boot_ca_id].boot_addr); + store_time_checkpoint("start_Cx_IPL_done", 0); + + /* finish loading Secure Firmware */ + load_end(); + store_time_checkpoint("load_Secure_FW_done", 0); + + /* load_secure data(for ICUMXB) */ + load_securedata(SECURE_FW_ID, slot); + store_time_checkpoint("load_Secure_Data_start (DMA-background)", SECUREDATA_SIZE); + + /* Authenticate of Secure Firmware */ + rom_secureboot(&li[SECURE_FW_ID]); + store_time_checkpoint("verify_Secure_FW_done", 0); + + /* finish loading secure data */ + load_end(); + store_time_checkpoint("load_Secure_Data_done", 0); +#if (BOOT_TIME_CHECK != 0) + gpio_N1305(2); +#endif + /* Finally Protection setting */ + rgid_protection_final(); + + /* set RGID setting finish flag. + * because polling from CX 2nd IPL. */ + mem_write8(RGID_SET_RGID_FIN_FLG_ADDR, RGID_SET_RGID_FIN_FLG_VAL); + +#if (ECM_ENABLE == 1) + /* Notice the ecc enable */ + NOTICE("Enabled EDC for AXI-Bus, RT-VRAM. \n"); +#endif + NOTICE("Load finish.\n"); + // ip_release(); + + store_time_checkpoint("done (Jumping to [SECURE_FW_ID].boot_addr)", 0); + print_time_checkpoints(); + return get_cfremap_addr(li[SECURE_FW_ID].boot_addr); +} +/* End of function loader_main(void) */ + +void clear_ecm_st_axi(void) +{ + mem_write32(ICISTPSTPER000,0x30U); + mem_write32(EDCSTRT20, 0x10U); + mem_write32(TIDSTRT20, 0x12U); +}/* End of function clear_ecm_st_axi(void) */ + +static void wa_for_v4h2(void) +{ + uint32_t tmp; + + /* 1. Release of pseudo power shutdown */ + /* Process moved to function set_leak_current_reduce_for_v4h2x(). */ + + /* 2. Reset ON for A2CN0 and Reset OFF for A2CN0 */ + tmp = mem_read32(BASE_CPG_ADDR + 0x2C00U); /* Software Reset Register 0 (SRCR0) */ + tmp = tmp | (0x1U << 23U); + mem_write32(CPG_CPGWPR, ~tmp); + mem_write32((BASE_CPG_ADDR + 0x2C00U),tmp); + + tmp = mem_read32(BASE_CPG_ADDR + 0x2C80U); /* Software Reset Clearing Register 0 (SRSTCLR0) */ + tmp = tmp | (0x1U << 23U); + mem_write32(CPG_CPGWPR, ~tmp); + mem_write32((BASE_CPG_ADDR + 0x2C80U),tmp); + + /* Unlock the ECM register protect. */ + mem_write32(ECMWPCNTR, 0xACCE0001); + + /* 3. ECM Enable */ + tmp = mem_read32(BASE_ECM_ADDR + 0x50018U); /* ECM Error Control Register 6 (ECMERRCTLR6) */ + tmp = tmp | (0xfU << 24U); + mem_write32((BASE_ECM_ADDR + 0x50018U),tmp); + + /* Lock the ECM register protect. */ + mem_write32(ECMWPCNTR, 0xACCE0000U); +}/* End of function wa_for_v4h2(void) */ + +static void set_leak_current_reduce_for_v4h2x(void) +{ + uint32_t reg; + const uint32_t pdrsr_tbl[PDR_MAX] = { /* SYSC PDRSR register table */ + SYSC_PDRSR43, /* A3IR */ + SYSC_PDRSR42, /* A2CN0 */ + SYSC_PDRSR41 /* A1CNN0 */ + }; + const uint32_t pdroncr_tbl[PDR_MAX] = { /* SYSC PDRONCR register table */ + SYSC_PDRONCR43, /* A3IR */ + SYSC_PDRONCR42, /* A2CN0 */ + SYSC_PDRONCR41 /* A1CNN0 */ + }; + + /* Power ON / OFF process complete interrupt enable for PDR41-PDR43 */ + reg = mem_read32(SYSC_SYSCIER1); + reg |= (SYSC_BIT_PDR41 | SYSC_BIT_PDR42 | SYSC_BIT_PDR43); + mem_write32(SYSC_SYSCIER1, reg); + INFO("SYSCIER1(0x%08x) = %08x\n",SYSC_SYSCIER1,mem_read32(SYSC_SYSCIER1)); + + /* MASK complete interrupt request to INTC for PDR41-PDR43 */ + reg = mem_read32(SYSC_SYSCIMR1); + reg |= (SYSC_BIT_PDR41 | SYSC_BIT_PDR42 | SYSC_BIT_PDR43); + mem_write32(SYSC_SYSCIMR1, reg); + INFO("SYSCIMR1(0x%08x) = %08x\n",SYSC_SYSCIMR1,mem_read32(SYSC_SYSCIMR1)); + + for(uint32_t loop = 0U; loop < PDR_MAX; loop++) + { + /* Check PDRn Power on state */ + reg = mem_read32(pdrsr_tbl[loop]); + INFO("PDRSR(0x%08x) = %08x\n",pdrsr_tbl[loop],reg); + reg &= SYSC_PDRSR_PWR_MASK; + /* Only when the Power state of PDRn is OFF, the Power On Request is processed */ + if((reg == SYSC_PDRSR_PWROFF) == true) + { + /* Wait until SYSC is in Not busy status */ + do{ + /* Get SYSC processing Power ON / OFF status */ + reg = mem_read32(SYSC_SYSCSR); + INFO("SYSCSR(0x%08x) = %08x\n", SYSC_SYSCSR, reg); + reg &= SYSCSR_BUSY_MASK; + } while((reg == SYSCSR_NOT_BUSY) != true); + + /* PDRn Power ON request */ + mem_write32(pdroncr_tbl[loop], SYSC_PDRONCR_PWRON); + INFO("PDRONCRn(0x%08x) = %08x\n",pdroncr_tbl[loop],mem_read32(pdroncr_tbl[loop])); + + /* Power ON process complete interrupt status for PDR41-PDR43 */ + do{ + reg = mem_read32(SYSC_SYSCISCR1); + INFO("SYSCISCR1(0x%08x) = %08x\n", SYSC_SYSCISCR1, reg); + reg &= (SYSC_BIT_PDR43 >> loop); /* loop = 0:PDR43 1:PDR42 2:PDR41 */ + } while((reg !=SYSC_PDR_PWR_PROC) != true); + + /* Clear Power ON process complete interrupt status for PDR41-PDR43 */ + mem_write32(SYSC_SYSCISCR1, reg); + INFO("SYSCISCR1(0x%08x) = %08x\n",SYSC_SYSCISCR1,mem_read32(SYSC_SYSCISCR1)); + } + } + + /* Power ON / OFF process complete interrupt disable for PDR41-PDR43 */ + reg = mem_read32(SYSC_SYSCIER1); + reg &= ~(SYSC_BIT_PDR41 | SYSC_BIT_PDR42 | SYSC_BIT_PDR43); + mem_write32(SYSC_SYSCIER1, reg); + INFO("SYSCIER1(0x%08x) = %08x\n",SYSC_SYSCIER1,mem_read32(SYSC_SYSCIER1)); + + /* MASK complete interrupt request to INTC for PDR41-PDR43 */ + reg = mem_read32(SYSC_SYSCIMR1); + reg &= ~(SYSC_BIT_PDR41 | SYSC_BIT_PDR42 | SYSC_BIT_PDR43); + mem_write32(SYSC_SYSCIMR1, reg); + INFO("SYSCIMR1(0x%08x) = %08x\n",SYSC_SYSCIMR1,mem_read32(SYSC_SYSCIMR1)); +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader_main_v4m.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader_main_v4m.c new file mode 100644 index 0000000..af1ac9c --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/loader/loader_main_v4m.c @@ -0,0 +1,269 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main function for V4M + ******************************************************************************/ +/****************************************************************************** + * @file loader_main_v4m.c + * - Version : 0.04 + * @brief 1. IP initialization. + * 2. DMA transfer the binary image from Flash to RAM. + * 3. Authentication of the transferred image. + * 4. Boot CR and CA core. + * 5. Release of used resources. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + * : 14.11.2023 0.02 Fixed file header path of ECC. + * : 16.11.2023 0.03 Added avs_low_power_mode_setting function + * calling. + * : 07.04.2025 0.04 Added ecm_init_setting function calling. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rcar_def.h" +#if (ECM_ERROR_ENABLE == 1) +#include "../ip/ddr/v4m/lpddr5/ecm_enable_v4m.h" +#endif /* ECM_ERROR_ENABLE == 1 */ + +/* Provided code */ +#include "../ip/ddr/boot_init_dram.h" +#include "../ip/ddr/v4m/lpddr5/ecc_enable_v4m.h" +#include + +#define ICISTP_BASE (BASE_ICISTP_ADDR) +#define ICISTPSTPER000 (ICISTP_BASE + 0x30300U) + +#define EDC_BASE (BASE_ECM_ADDR) +#define EDCSTRT20 (EDC_BASE + 0x80C0U) +#define TIDSTRT20 (EDC_BASE + 0x81C0U) + +/* SYSC register */ +#define SYSC_BASE (BASE_SYSC_ADDR) +#define SYSC_SYSCSR (SYSC_BASE + 0x0000U) /* SYSC Status Register */ +#define SYSC_SYSCISCR1 (SYSC_BASE + 0x0814U) /* Interrupt Status/Clear Register1 */ +#define SYSC_SYSCIER1 (SYSC_BASE + 0x0824U) /* Interrupt Enable Register1 */ +#define SYSC_SYSCIMR1 (SYSC_BASE + 0x0834U) /* Interrupt MASK Register1 */ + +/* Power Domain Register */ +#define SYSC_PDR41 (0x0A40U) /* A1CNN0 */ +#define SYSC_PDR42 (0x0A80U) /* A2CN0 */ +#define SYSC_PDR43 (0x0AC0U) /* A3IR */ +#define SYSC_PDRSR (SYSC_BASE + 0x1000U) /* Base address of Power Domain Status Register */ +#define SYSC_PDRSR41 (SYSC_PDRSR + (SYSC_PDR41)) +#define SYSC_PDRSR42 (SYSC_PDRSR + (SYSC_PDR42)) +#define SYSC_PDRSR43 (SYSC_PDRSR + (SYSC_PDR43)) +#define SYSC_PDRONCR (SYSC_BASE + 0x1004U) /* Base address of Power Domain Power-ON Control Register */ +#define SYSC_PDRONCR41 (SYSC_PDRONCR + (SYSC_PDR41)) +#define SYSC_PDRONCR42 (SYSC_PDRONCR + (SYSC_PDR42)) +#define SYSC_PDRONCR43 (SYSC_PDRONCR + (SYSC_PDR43)) + +#define PDR_MAX (3U) /* Number of PDR's to be set */ +#define SYSC_BIT_PDR41 (0x00000200U) /* SYSC register target PDR41 bit */ +#define SYSC_BIT_PDR42 (0x00000400U) /* SYSC register target PDR42 bit */ +#define SYSC_BIT_PDR43 (0x00000800U) /* SYSC register target PDR43 bit */ + +#define SYSCSR_BUSY_MASK (0x00000003U) /* SYSC Power On or Power Off seaquence status */ +#define SYSCSR_NOT_BUSY (0x00000003U) /* Not processing */ + +#define SYSC_PDRSR_PWR_MASK (0x00001111U) /* PDR Power On / Off Status MASK */ +#define SYSC_PDRSR_PWROFF (0x00000001U) /* PDR Power OFF Status */ +#define SYSC_PDRONCR_PWRON (0x00000001U) /* PDR Power On request */ +#define SYSC_PDR_PWR_PROC (0x00000000U) /* PDR Power On or Poweer off processing */ + +#define RGID_SET_RGID_FIN_FLG_ADDR (0xFD95EFFCU) /* 0xE635EFFC:Remap 12 */ +#define RGID_SET_RGID_FIN_FLG_VAL (0x64U) + + +#if (ADD_HOTPLUG_MAGIC == ADD_MAGIC_NUMBER) +#define HOTPLUG_MAGIC_NUM (0x853F912EU) +#else +#define HOTPLUG_MAGIC_NUM (0x00000000U) +#endif +__attribute__ ((section (".cr_hot_plug_magic"))) const uint32_t magic_num[4] = {0x00000000U, 0x00000000U, + 0x00000000U, HOTPLUG_MAGIC_NUM}; + +uint32_t loader_main(void) +{ + uint32_t boot_ca_id; + uint32_t auth_count = 0U; + uint32_t boot_cpu; + uint32_t tmp; + __attribute__((__unused__)) uint32_t loop = 0U; + __attribute__((__unused__)) uint32_t ca_load_num; /* number of load for Optional CA program */ + LOAD_INFO li[MAX_PLACED] = {0U}; + + +/***************************************************************************** + * Initialize Hardware + *****************************************************************************/ + /* IP initialize */ + ip_init(); + +#if (ECM_ERROR_ENABLE == 1) + ecm_init_setting(); +#endif /* ECM_ERROR_ENABLE == 1 */ + +#if (ECM_ENABLE == 1) +/***************************************************************************** + * ECC and EDC Initialize + *****************************************************************************/ + edc_axi_enable(); + edc_vram_enable(); +#endif + +/***************************************************************************** + * Work Around for APMU + *****************************************************************************/ + wa_setting_apmu(); + +/***************************************************************************** + * Output boot message + *****************************************************************************/ + print_boot_msg(); + +/***************************************************************************** + * Low Power Mode setting for V4M + *****************************************************************************/ + avs_low_power_mode_setting(); + +/***************************************************************************** + * WA for V4M + *****************************************************************************/ + /* WA OTLINT-5556 increased latency: APMU FRSTCTRL bit[29] disable */ + tmp = mem_read32(BASE_APMU_ADDR + 0x68U); + tmp = tmp & ~(1U << 29U); + mem_write32((BASE_APMU_ADDR + 0x68U), tmp); + +/***************************************************************************** + * Setting Access protection + *****************************************************************************/ + /* Region ID access protection */ + rgid_protection(); + ram_protection(); + + /* Change the Region ID (Master) of the Module used for data transfer to a temporary setting. */ + set_master_rgid_4_tfr_mod(); + +/***************************************************************************** + * Load Certficate from QSPI + *****************************************************************************/ + /* Load content certificate */ + ca_load_num = load_content_cert(); + + /* Get load information */ + load_init(li); + + /* verify the each content certs before Image load */ + preload_verify_cntcert(li); + +/***************************************************************************** + * Authenticate Software minimum version table + *****************************************************************************/ + auth_min_ver_tbl(li); + +/***************************************************************************** + * Load Cx IPL from Flash + *****************************************************************************/ + /* Start loading Cx IPL image from Flash into SDRAM */ + load_image(&li[CA_PROGRAM_ID]); + + /* The CA image to boot is CA IPL. */ + boot_ca_id = CA_PROGRAM_ID; + + /* boot CPU is CR */ + boot_cpu = RCAR_PWR_TARGET_CR; + + /* finish loading Cx IPL */ + load_end(); +/***************************************************************************** + * Load Secure Firmware from Flash + *****************************************************************************/ + /* Start loading Secure FW image from Flash into SDRAM */ + load_image(&li[SECURE_FW_ID]); + + /* Authenticate of CA Program#n */ + rom_secureboot(&li[boot_ca_id + auth_count]); + + /* SystemRAM has an undefined initial value, clear the address of + * the SystemRAM that is going to store set finish flag of RGID. */ + mem_write8(RGID_SET_RGID_FIN_FLG_ADDR, 0xFFU); + + /* Before Boot CPU, Set the division ratio for CPU operating frequency */ + adj_cr_variant_freq(); + + /* boot CA */ + arm_cpu_on(boot_cpu, li[boot_ca_id].boot_addr); + + /* finish loading Secure Firmware */ + load_end(); + + /* load_secure data(for ICUMXB) */ + load_securedata(SECURE_FW_ID); + + /* Authenticate of Secure Firmware */ + rom_secureboot(&li[SECURE_FW_ID]); + + /* finish loading secure data */ + load_end(); + + /* Finally Protection setting */ + rgid_protection_final(); + + /* set RGID setting finish flag. + * because polling from CX 2nd IPL. */ + mem_write8(RGID_SET_RGID_FIN_FLG_ADDR, RGID_SET_RGID_FIN_FLG_VAL); + +#if (ECM_ENABLE == 1) + /* Notice the ecc enable */ + NOTICE("Enabled EDC for AXI-Bus, RT-VRAM. \n"); +#endif + NOTICE("Load finish.\n"); + ip_release(); + + return get_cfremap_addr(li[SECURE_FW_ID].boot_addr); +} +/* End of function loader_main(void) */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/codesram_ecc.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/codesram_ecc.c new file mode 100644 index 0000000..bc3c0a2 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/codesram_ecc.c @@ -0,0 +1,228 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Control ECC and Address parity check for CodeSRAM + ******************************************************************************/ + /****************************************************************************** + * @file codesram_ecc.c + * - Version : 0.01 + * @brief 1. Enable / Disable ECC and Address parity check for CodeSRAM. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 19.01.2023 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#define CSRM_ECCCTL_EMCA_EN_MOD (0x00004000U) +#define CSRM_ECCCTL_APERR (0x00001000U) +#define CSRM_ECCCTL_ECERVF (0x00000040U) +#define CSRM_ECCCTL_EC1ECP (0x00000020U) +#define CSRM_ECCCTL_ECER2F (0x00000004U) +#define CSRM_ECCCTL_ECER1F (0x00000002U) + +#define CSRM_APCTL_APCEN (0x00000001U) +#define CSRM_NO_ERROR (0x00000000U) + +#define CODESRAM_BUS_NUM_SHIFT (20U) + +void disable_codesram_ecc_parity(uint32_t boot_addr, uint32_t size) +{ + uint32_t loop; + uint32_t bus_num; + uint32_t set_num; + uint32_t reg; + + /* Code-SRAMn ECC Control Register */ + const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL, + MCU_CSRM1ECCCTL, + MCU_CSRM2ECCCTL, + MCU_CSRM3ECCCTL, + MCU_CSRM4ECCCTL, + MCU_CSRM5ECCCTL}; + + /* Code-SRAMn Address Parity Control Register */ + const uint32_t apctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0APCTL, + MCU_CSRM1APCTL, + MCU_CSRM2APCTL, + MCU_CSRM3APCTL, + MCU_CSRM4APCTL, + MCU_CSRM5APCTL}; + + /* Calculate the area used by Code SRAM. */ + bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + + for (loop = 0U; loop < set_num; loop++) + { + /* Disable ECC error detection and error correction for CodeSRAM. */ + reg = mem_read32(eccctl_reg[bus_num + loop]); + reg &= ~(CSRM_ECCCTL_ECERVF); + reg |= CSRM_ECCCTL_EMCA_EN_MOD; + reg |= CSRM_ECCCTL_EC1ECP; + mem_write32(eccctl_reg[bus_num + loop], reg); + /* Disable Address parity check for CodeSRAM. */ + reg = mem_read32(apctl_reg[bus_num + loop]); + reg &= ~(CSRM_APCTL_APCEN); + mem_write32(apctl_reg[bus_num + loop], reg); + } +} +/* End of function disable_codesram_ecc_parity */ + +void enable_codesram_ecc_parity(uint32_t boot_addr, uint32_t size) +{ + uint32_t loop; + uint32_t bus_num; + uint32_t set_num; + uint32_t reg; + + /* Code-SRAMn ECC Control Register */ + const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL, + MCU_CSRM1ECCCTL, + MCU_CSRM2ECCCTL, + MCU_CSRM3ECCCTL, + MCU_CSRM4ECCCTL, + MCU_CSRM5ECCCTL}; + + /* Code-SRAMn Address Parity Control Register */ + const uint32_t apctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0APCTL, + MCU_CSRM1APCTL, + MCU_CSRM2APCTL, + MCU_CSRM3APCTL, + MCU_CSRM4APCTL, + MCU_CSRM5APCTL}; + + /* Calculate the area used by Code SRAM. */ + bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + + for (loop = 0U; loop < set_num; loop++) + { + /* Enable ECC error detection and error correction for CodeSRAM. */ + reg = mem_read32(eccctl_reg[bus_num + loop]); + reg &= ~(CSRM_ECCCTL_EC1ECP); + reg |= CSRM_ECCCTL_ECERVF; + reg |= CSRM_ECCCTL_EMCA_EN_MOD; + mem_write32(eccctl_reg[bus_num + loop], reg); + /* Enable Address parity check for CodeSRAM. */ + reg = mem_read32(apctl_reg[bus_num + loop]); + reg |= CSRM_APCTL_APCEN; + mem_write32(apctl_reg[bus_num + loop], reg); + } +} +/* End of function enable_codesram_ecc_parity */ + +void chk_codesram_ecc_parity(uint32_t boot_addr, uint32_t size) +{ + uint32_t loop; + uint32_t bus_num; + uint32_t set_num; + uint32_t reg; + uint32_t err_chk; + + /* Code-SRAMn ECC Control Register */ + const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL, + MCU_CSRM1ECCCTL, + MCU_CSRM2ECCCTL, + MCU_CSRM3ECCCTL, + MCU_CSRM4ECCCTL, + MCU_CSRM5ECCCTL}; + + /* Calculate the area used by Code SRAM. */ + bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + + /* Check ECC error and Address parity error for CodeSRAM. */ + for (loop = 0U; loop < set_num; loop++) + { + reg = mem_read32(eccctl_reg[bus_num + loop]); + err_chk = reg; + err_chk &= (CSRM_ECCCTL_ECER2F | CSRM_ECCCTL_ECER1F); + if(err_chk != CSRM_NO_ERROR) + { + /* ECC error occurred. */ + ERROR("CodeSRAM ECC error detected !!\n"); + panic; + } + err_chk = reg; + err_chk &= CSRM_ECCCTL_APERR; + if(err_chk != CSRM_NO_ERROR) + { + /* Address parity error occurred. */ + ERROR("CodeSRAM Address parity error detected !!\n"); + panic; + } + } +} +/* End of function chk_codesram_ecc_parity */ + +void initialize_codesram_ecc_parity(uint32_t boot_addr, uint32_t size) +{ + uint32_t loop; + uint32_t bus_num; + uint32_t set_num; + uint32_t reg; + + /* Code-SRAMn ECC Control Register */ + const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL, + MCU_CSRM1ECCCTL, + MCU_CSRM2ECCCTL, + MCU_CSRM3ECCCTL, + MCU_CSRM4ECCCTL, + MCU_CSRM5ECCCTL}; + + /* Code-SRAMn Address Parity Control Register */ + const uint32_t apctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0APCTL, + MCU_CSRM1APCTL, + MCU_CSRM2APCTL, + MCU_CSRM3APCTL, + MCU_CSRM4APCTL, + MCU_CSRM5APCTL}; + + /* Calculate the area used by Code SRAM. */ + bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + + for (loop = 0U; loop < set_num; loop++) + { + /* Initialize ECC error detection and error correction setting for CodeSRAM. */ + reg = mem_read32(eccctl_reg[bus_num + loop]); + reg &= ~(CSRM_ECCCTL_EC1ECP | CSRM_ECCCTL_ECERVF); + reg |= CSRM_ECCCTL_EMCA_EN_MOD; + mem_write32(eccctl_reg[bus_num + loop], reg); + /* Initialize Address parity check setting for CodeSRAM. */ + reg = mem_read32(apctl_reg[bus_num + loop]); + reg |= CSRM_APCTL_APCEN; + mem_write32(apctl_reg[bus_num + loop], reg); + } +} +/* End of function initialize_codesram_ecc_parity */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/codesram_ecc.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/codesram_ecc.h new file mode 100644 index 0000000..7cb662f --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/codesram_ecc.h @@ -0,0 +1,39 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC and Address parity check for CodeSRAM header + ******************************************************************************/ + +#ifndef CODESRAM_ECC_H__ +#define CODESRAM_ECC_H__ + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void disable_codesram_ecc_parity(uint32_t boot_addr, uint32_t size); +void enable_codesram_ecc_parity(uint32_t boot_addr, uint32_t size); +void chk_codesram_ecc_parity(uint32_t boot_addr, uint32_t size); +void initialize_codesram_ecc_parity(uint32_t boot_addr, uint32_t size); + +#endif /* CODESRAM_ECC_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.c new file mode 100644 index 0000000..93a5b56 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.c @@ -0,0 +1,300 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MCU power management driver + ******************************************************************************/ + /****************************************************************************** + * @file cpu_on.c + * - Version : 0.02 + * @brief 1. Boot process of MCU CPU core. + * 2. Set Option Byte to OPBT. + * 3. Disable the Bus Guard. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.06.2022 0.01 First Release + * : 02.02.2023 0.02 Moved definitions to header file. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +/* MCU */ +#define MCU_OPBT_MAX (12U) +#define MCU_ICUM_OPBT_MAX (7U) +#define MCU_PBG_MAX (7U) +#define MCU_HBG_MAX (9U) +#define LOCAL_FLASH_BUS_MODE (0x12B9B0A1U) + +#define MCU_RESET_READY (0x00000001U) +#define MCU_RCT_RUNNING (0x00000001U) + +#define CODESRAM_ROUND_MASK (0x000FFFFFU) + +#define OPBT_EMPTY_VALUE (0xFFFFFFFFU) + +static void csrm_n_csifcode_protect(uint32_t bit_shift); + +void mcu_cpu_on(uint32_t target) +{ + uint32_t boot_ctrl = 0U; + uint32_t ret; + + if(MCU_PWR_TARGET_G4MH == target) + { +#if ((BOOT_MCU & MCU_BOOT_G4MH) != 0U) + boot_ctrl = MCU_G4MH_BOOT_CTLR; +#endif /* ((BOOT_MCU & MCU_BOOT_G4MH) != 0U) */ + } + else if(MCU_PWR_TARGET_ICUMH == target) + { +#if ((BOOT_MCU & MCU_BOOT_ICUMH) != 0U) + boot_ctrl = MCU_ICUMH_BOOT_CTLR; +#endif /* ((BOOT_MCU & MCU_BOOT_ICUMH) != 0) */ + } + else + { + /* No Process */ + } + + /* Execute the reset process of MCU core. * + * If the register address is not set in "A", * + * exit the function without executing anything. */ + if(boot_ctrl != 0U) + { + /* Release write protection of SCDS0 */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_REL_CODE); + + /* MCU core reset */ + ret = mem_read32(boot_ctrl); + ret |= MCU_RESET_READY; + mem_write32(boot_ctrl, ret); + ret = mem_read32(MCU_OPBT_CTRL); + ret |= MCU_RESET_READY; + mem_write32(MCU_OPBT_CTRL, ret); + + /* Wait until the MCU status is set to start. */ + do + { + ret = mem_read32(MCU_OPBT_STAT); + ret &= MCU_RCT_RUNNING; + } while (ret != MCU_RCT_RUNNING); + + /* write protection of SCDS0 */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_PROT_CODE); + } +} +/* End of function mcu_cpu_on(uint32_t target) */ + +void mcu_set_opbt(void) +{ + uint32_t loop; + const uint32_t opbt_reg[MCU_OPBT_MAX] = + { MCU_RESET_VECTOR_PE0, + MCU_RESET_VECTOR_PE1, + MCU_OPBT0, + MCU_OPBT1, + MCU_OPBT2, + MCU_OPBT3, + MCU_OPBT4, + MCU_OPBT6, + MCU_OPBT7, + MCU_OPBT8, + MCU_OPBT9, + MCU_OPBT96 + }; + + uint32_t opbt_val[MCU_OPBT_MAX] = + { 0x00000400U, + 0x00000400U, + 0x3D810010U, + 0x00700000U, + 0x707FFFFFU, + 0x00000000U, + 0x0C0C0C0FU, + 0x00000F00U, + 0x00000FFFU, + 0x02000000U, + 0x03000300U, + 0x00000000U + }; + + for (loop = 0U; loop < MCU_OPBT_MAX; loop++) + { + mem_write32(opbt_reg[loop], opbt_val[loop]); + opbt_val[loop] = OPBT_EMPTY_VALUE; + } +} +/* End of function mcu_set_opbt(uint32_t g4mh_addr) */ + +void mcu_set_icum_opbt(void) +{ + uint32_t loop; + const uint32_t opbt_reg[MCU_ICUM_OPBT_MAX] = + { MCU_ICUM_OPBT0, + MCU_ICUM_OPBT1, + MCU_ICUM_OPBT2, + MCU_ICUM_OPBT4, + MCU_ICUM_OPBT5, + MCU_ICUM_OPBT6, + MCU_ICUM_OPBT7 + }; + +#if (BOOT_MCU == MCU_BOOT_G4MH_ICUMH) + uint32_t opbt_val[MCU_ICUM_OPBT_MAX] = + { 0x0FFFFFFFU, + 0x00500000U, + 0x00500000U, + 0xFFFFFFEFU, + 0x00600000U, + 0xFFFFFFFFU, + 0xFFFFFFFFU + }; +#else + uint32_t opbt_val[MCU_ICUM_OPBT_MAX] = + { OPBT_EMPTY_VALUE, + OPBT_EMPTY_VALUE, + OPBT_EMPTY_VALUE, + OPBT_EMPTY_VALUE, + OPBT_EMPTY_VALUE, + OPBT_EMPTY_VALUE, + OPBT_EMPTY_VALUE + }; +#endif + + for (loop = 0U; loop < MCU_ICUM_OPBT_MAX; loop++) + { + mem_write32(opbt_reg[loop], opbt_val[loop]); + opbt_val[loop] = OPBT_EMPTY_VALUE; + } +} +/* End of function mcu_set_icum_opbt(uint32_t icumh_addr) */ + +void mcu_set_hbg(void) +{ + uint32_t loop; + const uint32_t pbg_reg[MCU_PBG_MAX][2U] = + { /* register address setting value */ + {MCUAXI_PBG_PBGPROT0_0, 0x00000000U}, + {MCUAXI_PBG_PBGPROT0_1, 0x00000000U}, + {MCUAXI_PBG_PBGPROT0_2, 0x00000000U}, + {MCUAXI_PBG_PBGPROT0_3, 0x00000000U}, + {MCUAXI_PBG_PBGPROT0_4, 0x00000000U}, + {MCUAXI_PBG_PBGPROT0_5, 0x00000000U}, + {MCUAXI_PBG_PBGPROT0_6, 0x00000000U} + }; + + const uint32_t hbg_reg[MCU_HBG_MAX][2U] = + { /* register address setting value */ + {MCU_HBG_CS0_HBGPROT0, 0x00000000U}, + {MCU_HBG_CS1_HBGPROT0, 0x00000000U}, + {MCU_HBG_CS2_HBGPROT0, 0x00000000U}, + {MCU_HBG_CS3_HBGPROT0, 0x00000000U}, + {MCU_HBG_CS4_HBGPROT0, 0x00000000U}, + {MCU_HBG_CS5_HBGPROT0, 0x00000000U}, + {MCU_HBG_DS_HBGPROT0, 0x00000000U}, + {MCU_HBG_SOCM_HBGPROT0, 0x00000000U}, + {MCU_HBG_SOCS_HBGPROT0, 0x00000000U} + }; + + const uint32_t hbg_prot_reg[MCU_HBG_MAX] = + { + MCU_HBGSLVER_CS0_HBGKCPROT, + MCU_HBGSLVER_CS1_HBGKCPROT, + MCU_HBGSLVER_CS2_HBGKCPROT, + MCU_HBGSLVER_CS3_HBGKCPROT, + MCU_HBGSLVER_CS4_HBGKCPROT, + MCU_HBGSLVER_CS5_HBGKCPROT, + MCU_HBGSLVER_DS_HBGKCPROT, + MCU_HBGSLVER_SOCM_HBGKCPROT, + MCU_HBGSLVER_SOCS_HBGKCPROT + }; + + /* Release write protection of SCDS0 */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_REL_CODE); + + /* Set PBG register */ + for (loop = 0U; loop < MCU_PBG_MAX; loop++) + { + mem_write32(pbg_reg[loop][0U], pbg_reg[loop][1U]); + } + + /* write protection of SCDS0 */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_PROT_CODE); + + /* Set HBG register */ + for (loop = 0U; loop < MCU_HBG_MAX; loop++) + { + hbg_reg_write(hbg_prot_reg[loop], hbg_reg[loop][0U], hbg_reg[loop][1U]); + } +} +/* End of function mcu_set_hbg(void) */ + +void mcu_set_csrm(uint32_t boot_addr, uint32_t size) +{ + uint32_t loop; + uint32_t bus_num; + uint32_t set_num; + const uint32_t csrm_reg[MCU_CSRM_MAX] = + { MCU_CSRM0CSIFCODE, + MCU_CSRM1CSIFCODE, + MCU_CSRM2CSIFCODE, + MCU_CSRM3CSIFCODE, + MCU_CSRM4CSIFCODE, + MCU_CSRM5CSIFCODE, + }; + + /* Calculate the area used by Code SRAM. */ + bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> 20U); + set_num = ((size & CODESRAM_BUS_NUM_MASK) >> 20U); + + /* Set CSRM register */ + for (loop = 0U; loop < set_num; loop++) + { + mem_write32(csrm_reg[bus_num + loop], LOCAL_FLASH_BUS_MODE); + + /* Write protection of CSRMnCSIFCODE registers */ + csrm_n_csifcode_protect((bus_num + loop)); + } +} +/* End of function mcu_set_csrm(void) */ + +void hbg_reg_write(uint32_t prot_reg_addr, uint32_t reg_addr, uint32_t val) +{ + mem_write32(prot_reg_addr, MCU_HBG_REL_CODE); + mem_write32(reg_addr, val); + mem_write32(prot_reg_addr, MCU_HBG_PROT_CODE); +} +/* End of function hbg_reg_write(uint32_t prot_reg_addr, uint32_t reg_addr, uint32_t val) */ + +static void csrm_n_csifcode_protect(uint32_t bit_shift) +{ + /* Control CSIFCODE_LOCK to protect writing to CSRMnCSIFCODE during product mass production. */ +} +/* End of function csrm_n_csifcode_protect(uint32_t bit_shift) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.h new file mode 100644 index 0000000..ac40f44 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.h @@ -0,0 +1,62 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MCU power management driver header + ******************************************************************************/ + +#ifndef CPU_ON_FOR_MCU_H__ +#define CPU_ON_FOR_MCU_H__ + +#define MCU_PWR_TARGET_G4MH (0U) +#define MCU_PWR_TARGET_ICUMH (1U) + +#define MCU_BOOT_NONE (0U) +#define MCU_BOOT_G4MH (1U) +#define MCU_BOOT_ICUMH (2U) +#define MCU_BOOT_G4MH_ICUMH (3U) + +#define MCU_HBG_REL_CODE (0xA5A5A501U) +#define MCU_HBG_PROT_CODE (0xA5A5A500U) + +#define G4MH_PRG_1_BOOT_ADDR (0x10000000U) +#define G4MH_PRG_1_SIZE (0x00100000U) +#define G4MH_PRG_2_BOOT_ADDR (0x10100000U) +#define G4MH_PRG_2_SIZE (0x00400000U) +#define ICUMH_PRG_BOOT_ADDR (0x10500000U) +#define ICUMH_PRG_SIZE (0x00100000U) + +#define MCU_CSRM_MAX (6U) +#define CODESRAM_BUS_NUM_MASK (0x00700000U) + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void mcu_cpu_on(uint32_t target); +void mcu_set_opbt(void); +void mcu_set_icum_opbt(void); +void mcu_set_hbg(void); +void mcu_set_csrm(uint32_t boot_addr, uint32_t size); +void hbg_reg_write(uint32_t prot_reg_addr, uint32_t reg_addr, uint32_t val); + +#endif /* CPU_ON_FOR_MCU_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.c new file mode 100644 index 0000000..5ea17a4 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.c @@ -0,0 +1,117 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function for MCU + ******************************************************************************/ +/****************************************************************************** + * @file image_load_for_mcu.c + * - Version : 0.01 + * @brief Loading image driver for MCU. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 04.07.2022 0.01 First Release + *****************************************************************************/ + +/* indelude */ +#include +#include +#include +#include +#include +#if (RCAR_SA9_TYPE == FLASH_BOOT) +#include +#elif (RCAR_SA9_TYPE == EMMC_BOOT) +#include +#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + +void image_load_for_mcu(const LOAD_INFO *li, uint32_t is_verify) +{ + uint32_t aes_flg = MCU_IMG_NOT_ENCRYPTED; + + if (is_verify != NORMAL_BOOT) + { + /* A flag whether MCU image is encrypted */ + aes_flg = get_aes_flg_in_cert(li -> cnt_cert_addr); + } + + if(aes_flg == MCU_IMG_NOT_ENCRYPTED) + { + /* Transfer by SDMAC on ICUMX */ + icu_sdmac_trans_start(li); + } + else + { + /* Transfer by AES driver on ICUMX */ + mcu_img_decrypt(li); + } +} +/* End of function image_load_for_mcu(const LOAD_INFO *li) */ + +void load_end_for_mcu(const LOAD_INFO *li, uint32_t is_verify) +{ + uint32_t aes_flg = MCU_IMG_NOT_ENCRYPTED; + + if (is_verify != NORMAL_BOOT) + { + /* A flag whether MCU image is encrypted */ + aes_flg = get_aes_flg_in_cert(li -> cnt_cert_addr); + } + + if(aes_flg == MCU_IMG_NOT_ENCRYPTED) + { + icu_sdmac_trans_end(); + } + else + { + mcu_img_decrypt_end(li); + } +} +/* End of function load_end_for_mcu(const LOAD_INFO *li) */ + +void load_image_info_print(const LOAD_INFO *li) +{ +#if (RCAR_SA9_TYPE == FLASH_BOOT) + load_image_info_print_for_flash(li); +#elif (RCAR_SA9_TYPE == EMMC_BOOT) + load_image_info_print_for_emmc(li); +#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */ +} +/* End of function load_image_info_print(const LOAD_INFO *li) */ + +void load_securedata_for_mcu(void) +{ + LOAD_INFO tmp_li; + + tmp_li.image_size = SECUREDATA_SIZE; + tmp_li.src_addr = RTVRAM_BASE; + tmp_li.boot_addr = DATA_SRAM_BASE; +#if (RCAR_SA9_TYPE == EMMC_BOOT) + tmp_li.part_num = EMMC_PARTITION_1; +#endif + /* */ + icu_sdmac_trans_start(&tmp_li); + icu_sdmac_trans_end(); +}/* End of function load_securedata(uint32_t target_id) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.h new file mode 100644 index 0000000..1511f64 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.h @@ -0,0 +1,67 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function for MCU header + ******************************************************************************/ + +#ifndef IMAGE_LOAD_FOR_MCU_H__ +#define IMAGE_LOAD_FOR_MCU_H__ + +#include +#include +#include +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) +#include +#include +#include +#include +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ + +void image_load_for_mcu(const LOAD_INFO *li, uint32_t is_verify); +void load_end_for_mcu(const LOAD_INFO *li, uint32_t is_verify); +void load_image_info_print(const LOAD_INFO *li); +void load_securedata_for_mcu(void); + +/* Inline function */ +static inline uint32_t get_aes_flg_in_cert(uint32_t cert_addr) +{ +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) + uint32_t aes_flg; + uint32_t val; + + val = mem_read32(cert_addr + CERT_INFO_FLG_OFFSET); + aes_flg = ((val >> CERT_FLAG_ENCRYPTION_USED_BIT_LOCATION) & 0x1U); + + return aes_flg; +#else + return MCU_IMG_NOT_ENCRYPTED; +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ +} +/* End of function get_aes_flg_in_cert(uint32_t cert_addr) */ + +#endif /* IMAGE_LOAD_FOR_MCU_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/loader_main_mcu.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/loader_main_mcu.c new file mode 100644 index 0000000..48dc21b --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/loader_main_mcu.c @@ -0,0 +1,456 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main for MCU + ******************************************************************************/ + /****************************************************************************** + * @file loader_main_mcu.c + * - Version : 0.03 + * @brief 1. Loading G4MH(1st) image including integrity check. + * 2. Loading ICUMH image including integrity check. + * 3. Loading G4MH(2nd) image including integrity check. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.06.2022 0.01 First Release + * : 05.08.2022 0.02 Add sw_version_check function call to + * : mcu_img_verify function. + * : 19.01.2023 0.03 Add ECC and Address parity check for CodeSRAM. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) +#include +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ +#include +#include +#include + +#define ICUMH_OPBT_OFFSET (0x200U) + +#define MCU_TRANSFER_UNIT (0x00040000U) /* 256KiB */ +#define RTVRAM_TMP_G4MH_TOP_A (0xE2080000U) +#define RTVRAM_TMP_G4MH_TOP_B (0xE20C0000U) + +#define GREG120_CODE (0x5AA5A55AU) +#define G4MH_LOAD_FIN_CODE (0x0000001EU) + +/* Prototype */ +static void load_g4mh_1st(const LOAD_INFO *li, uint32_t is_verify); +static void load_icumh(const LOAD_INFO *li, uint32_t is_verify); +static void load_g4mh_2nd(const LOAD_INFO *li, uint32_t is_verify); +static void w_load_even(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify); +static void w_load_odd(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify); +static void mcu_key_cert_check(LOAD_INFO *li, uint32_t is_verify); +static void mcu_cnt_cert_check(const LOAD_INFO *li, uint32_t is_verify); +static void mcu_img_verify(const LOAD_INFO *li, uint32_t is_verify); + + +static void load_g4mh_1st(const LOAD_INFO *li, uint32_t is_verify) +{ + LOAD_INFO tmp_li = {0U}; + + /* Copy li to tmporary structure. (Because original li members are required later.) */ + (void)memcpy((void *)&tmp_li, li, sizeof(LOAD_INFO)); + /* Change boot_addr to RTVRAM_BASE. */ + tmp_li.boot_addr = RTVRAM_BASE; + + /* Output image info. */ + load_image_info_print(li); + + /* Check load information. */ + check_load_area(li); + + /* Release write protection of SCDS0. */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_REL_CODE); + mem_write32(MCU_GREG120, 0x00000000U); + + /* Set G4MH Option Byte. */ + mcu_set_opbt(); + /* Set ICUMH Option Byte. */ + mcu_set_icum_opbt(); + + mem_write32(MCU_GREG120, GREG120_CODE); + micro_wait(10U); + + /* Write protection of SCDS0. */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_PROT_CODE); + + /* Load G4MH(1st) image from external flash to RT-VRAM. */ + load_start(&tmp_li); + + /* Verify Key Certificate. */ + mcu_key_cert_check(&tmp_li, is_verify); + + /* Disable bus guard of MCU. */ + mcu_set_hbg(); + + /* Finish loading G4MH(1st) image from external flash to RT-VRAM. */ + load_end(); + + /* Change src_addr from external flash to RT-VRAM. */ + tmp_li.src_addr = tmp_li.boot_addr; + /* Change boot_addr from RT-VRAM to CodeSRAM. */ + tmp_li.boot_addr = li->boot_addr; + + /* Disable ECC error and Address parity error check for CodeSRAM. */ + disable_codesram_ecc_parity(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE); + + /* Load G4MH(1st) image from RT-VRAM to CodeSRAM. */ + image_load_for_mcu(&tmp_li, is_verify); + + /* Verify Content Certificate */ + mcu_cnt_cert_check(&tmp_li, is_verify); + + /* Finish loading G4MH(1st) image from RT-VRAM to CodeSRAM. */ + load_end_for_mcu(&tmp_li, is_verify); + + /* Enable ECC error and Address parity error check for CodeSRAM. */ + enable_codesram_ecc_parity(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE); + + /* Verify G4MH(1st) image. */ + mcu_img_verify(&tmp_li, is_verify); + + /* Check ECC error and Address parity error detection for CodeSRAM. */ + chk_codesram_ecc_parity(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE); + + /* Reset CSRM registers that related CodeSRAM ECC to H/W initial value. */ + initialize_codesram_ecc_parity(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE); + + + /* Change Bus mode of CodeSRAM to the Local Flash Bus mode. */ + mcu_set_csrm(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE); + + /* Boot G4MH */ + mcu_cpu_on(MCU_PWR_TARGET_G4MH); +} +/* End of function load_g4mh_1st(const LOAD_INFO *li) */ + +static void load_icumh(const LOAD_INFO *li, uint32_t is_verify) +{ +#if (BOOT_MCU == MCU_BOOT_G4MH_ICUMH) + LOAD_INFO tmp_li = {0U}; + + /* Copy li to tmporary structure. (Because original li members are required later.) */ + (void)memcpy((void *)&tmp_li, li, sizeof(LOAD_INFO)); + /* Change boot_addr to RTVRAM_BASE. */ + tmp_li.boot_addr = RTVRAM_BASE; + + /* Output image info. */ + load_image_info_print(li); + + /* Check load information. */ + check_load_area(li); + + /* Load ICUMH image from external flash to RT-VRAM. */ + load_start(&tmp_li); + + /* Verify Key Certificate. */ + mcu_key_cert_check(&tmp_li, is_verify); + + /* Finish loading ICUMH image from external flash to RT-VRAM. */ + load_end(); + + /* Change src_addr from external flash to RT-VRAM. */ + tmp_li.src_addr = tmp_li.boot_addr; + /* Change boot_addr from RT-VRAM to CodeSRAM. */ + tmp_li.boot_addr = li->boot_addr; + + /* Disable ECC error and Address parity error check for CodeSRAM. */ + disable_codesram_ecc_parity(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE); + + /* Load ICUMH image from RT-VRAM to CodeSRAM. */ + image_load_for_mcu(&tmp_li, is_verify); + + /* Verify Content Certificate */ + mcu_cnt_cert_check(&tmp_li, is_verify); + + /* Finish loading ICUMH image from RT-VRAM to CodeSRAM. */ + load_end_for_mcu(&tmp_li, is_verify); + + /* Load Secure data from external flash to RT-VRAM */ + load_securedata(ICUMH_PROGRAM_ID); + + /* Enable ECC error and Address parity error check for CodeSRAM. */ + enable_codesram_ecc_parity(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE); + + /* Verify ICUMH image. */ + mcu_img_verify(&tmp_li, is_verify); + + /* Finish loading Secure data from external flash to RT-VRAM. */ + load_end(); + + /* Check ECC error and Address parity error detection for CodeSRAM. */ + chk_codesram_ecc_parity(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE); + + /* Reset CSRM registers that related CodeSRAM ECC to H/W initial value. */ + initialize_codesram_ecc_parity(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE); + + /* Load Secure data from RT-VRAM to Data-SRAM. */ + load_securedata_for_mcu(); + + /* Change Bus mode of CodeSRAM to the Local Flash Bus mode. */ + mcu_set_csrm(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE); + + /* Boot ICUMH */ + mcu_cpu_on(MCU_PWR_TARGET_ICUMH); +#endif /* (BOOT_MCU == MCU_BOOT_G4MH_ICUMH) */ +} +/* End of function load_icumh(const LOAD_INFO *li) */ + +static void load_g4mh_2nd(const LOAD_INFO *li, uint32_t is_verify) +{ + uint32_t count = 0U; + uint32_t dst_size = li->image_size; + uint32_t even_or_odd = 0U; + LOAD_INFO tmp_li = {0U}; + void (*p_w_load_func[])(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify) + = {w_load_even, w_load_odd}; + + /* Copy li to tmporary structure. (Because original li members are required later.) */ + (void)memcpy((void *)&tmp_li, li, sizeof(LOAD_INFO)); + + /* A transfer unit is 256KiB. */ + tmp_li.image_size = MCU_TRANSFER_UNIT; + /* Change boot_addr to 0xE2080000. */ + tmp_li.boot_addr = RTVRAM_TMP_G4MH_TOP_A; + + /* Output image info. */ + load_image_info_print(li); + + /* Check load information. */ + check_load_area(li); + + /* Load image from external flash to RT-VRAM. */ + load_start(&tmp_li); + + /* Verify Key Certificate. */ + mcu_key_cert_check(&tmp_li, is_verify); + + /* Finish loading image from external flash to RT-VRAM. */ + load_end(); + + /* Disable ECC error and Address parity error check for CodeSRAM. */ + disable_codesram_ecc_parity(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE); + + if (dst_size <= tmp_li.image_size) + { + /* If image size is less than 256KiB. */ + tmp_li.image_size = dst_size; + mcu_cnt_cert_check(li, is_verify); + } + else /* If image size is larger than 256KiB. */ + { + /* dst_size - 256KiB */ + dst_size -= tmp_li.image_size; + + if (dst_size < tmp_li.image_size) + { + /* If remaining image size is less than 256KiB. */ + count++; + even_or_odd = count; + tmp_li.image_size = dst_size; + dst_size = 0U; + } + else /* If remaining image size is still larger than 256KiB. */ + { + count++; + even_or_odd = count; + dst_size -= tmp_li.image_size; + } + /* Load image(#count) from external flash to RT-VRAM. * + * Load image(#count-1) from RT-VRAM to CodeSRAM. */ + p_w_load_func[even_or_odd](li, &tmp_li, count, is_verify); + + /* Verify Content Certificate */ + mcu_cnt_cert_check(&tmp_li, is_verify); + + /* Finish loading image(#count) from external flash to RT-VRAM. */ + load_end(); + /* Finish loading image(#count-1) from RT-VRAM to CodeSRAM. */ + load_end_for_mcu(&tmp_li, is_verify); + + /* Load remaining image. */ + while (dst_size != 0U) + { + if (dst_size < tmp_li.image_size) + { + /* If remaining image size is less than 256KiB. */ + count++; + even_or_odd = count % 2U; + tmp_li.image_size = dst_size; + dst_size = 0U; + } + else /* If remaining image size is still larger than 256KiB. */ + { + count++; + even_or_odd = count % 2U; + dst_size -= tmp_li.image_size; + } + /* Load image(#count) from external flash to RT-VRAM. * + * Load image(#count-1) from RT-VRAM to CodeSRAM. (with decryption) */ + p_w_load_func[even_or_odd](li, &tmp_li, count, is_verify); + /* Finish loading image(#count) from external flash to RT-VRAM. */ + load_end(); + /* Finish loading image(#count-1) from RT-VRAM to CodeSRAM. */ + load_end_for_mcu(&tmp_li, is_verify); + } + } + tmp_li.src_addr = (RTVRAM_TMP_G4MH_TOP_A + (even_or_odd * MCU_TRANSFER_UNIT)); + tmp_li.boot_addr = (li->boot_addr + (MCU_TRANSFER_UNIT * (count))); + + /* Load image from RT-VRAM to CodeSRAM (with decryption). */ + image_load_for_mcu(&tmp_li, is_verify); + + /* Finish loading image(bottom) from RT-VRAM to CodeSRAM. */ + load_end_for_mcu(&tmp_li); + + /* Enable ECC error and Address parity error check for CodeSRAM. */ + enable_codesram_ecc_parity(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE); + + /* Verify G4MH(2nd) image. */ + mcu_img_verify(li, is_verify); + + /* Check ECC error and Address parity error detection for CodeSRAM. */ + chk_codesram_ecc_parity(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE); + + /* Reset CSRM registers that related CodeSRAM ECC to H/W initial value. */ + initialize_codesram_ecc_parity(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE); + + /* Change Bus mode of CodeSRAM to the Local Flash Bus mode. */ + mcu_set_csrm(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE); + + /* Release write protection of SCDS0. */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_REL_CODE); + mem_write32(MCU_BOOT_STAT, G4MH_LOAD_FIN_CODE); + /* Write protection of SCDS0. */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_PROT_CODE); + + hbg_reg_write(MCU_HBGSLVER_PFS_HBGKCPROT, MCU_HBG_PFS_HBGPROT0, 0x00000000U); +} +/* End of function load_g4mh_2nd(const LOAD_INFO *li) */ + +static void w_load_even(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify) +{ + tmp_li->src_addr = (li->src_addr + (MCU_TRANSFER_UNIT * count)); + tmp_li->boot_addr = RTVRAM_TMP_G4MH_TOP_A; + + /* Load image(#count) from external flash to RT-VRAM. */ + load_start(tmp_li); + + tmp_li->src_addr = RTVRAM_TMP_G4MH_TOP_B; + tmp_li->boot_addr = (li->boot_addr + (MCU_TRANSFER_UNIT * (count - 1U))); + + /* Load image(#count-1) from RT-VRAM to CodeSRAM. (with decryption) */ + image_load_for_mcu(tmp_li, is_verify); +} +/* End of function w_load_even(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count) */ + +static void w_load_odd(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify) +{ + tmp_li->src_addr = (li->src_addr + (MCU_TRANSFER_UNIT * count)); + tmp_li->boot_addr = RTVRAM_TMP_G4MH_TOP_B; + + /* Load image(#count) from external flash to RT-VRAM. */ + load_start(tmp_li); + + tmp_li->src_addr = RTVRAM_TMP_G4MH_TOP_A; + tmp_li->boot_addr = (li->boot_addr + (MCU_TRANSFER_UNIT * (count - 1U))); + + /* Load image(#count-1) from RT-VRAM to CodeSRAM. (with decryption) */ + image_load_for_mcu(tmp_li, is_verify); +} +/* End of function w_load_even(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count) */ + +static void mcu_key_cert_check(LOAD_INFO *li, uint32_t is_verify) +{ +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) + if (is_verify != NORMAL_BOOT) + { + r_mcu_key_cert_check_api(li); + } +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ +} +/* End of function mcu_key_cert_check(LOAD_INFO *li, uint32_t is_verify). */ + +static void mcu_cnt_cert_check(const LOAD_INFO *li, uint32_t is_verify) +{ +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) + if (is_verify != NORMAL_BOOT) + { + r_mcu_cnt_cert_check_api(li); + } +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ +} +/* End of function mcu_key_cert_check(const LOAD_INFO *li, uint32_t is_verify) */ + +void mcu_img_decrypt(const LOAD_INFO *li) +{ +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) + r_mcu_img_decrypt_api(li); +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ +} +/* End of function mcu_img_decrypt(const LOAD_INFO *li, uint32_t is_verify) */ + +void mcu_img_decrypt_end(const LOAD_INFO *li) +{ + /* Argument li is not used but compliant to MISRA Rule 2.2. */ +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) + r_mcu_img_decrypt_end(); +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ +} +/* End of function mcu_img_decrypt_end(const LOAD_INFO *li) */ + +static void mcu_img_verify(const LOAD_INFO *li, uint32_t is_verify) +{ +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) + if (is_verify != NORMAL_BOOT) + { + r_mcu_img_verify_api(li); + sw_version_check(li); + } +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ +} +/* End of function mcu_img_verify(const LOAD_INFO *li, uint32_t is_verify) */ + +void mcu_load_main(const LOAD_INFO *li, uint32_t is_verify) +{ + load_g4mh_1st(&li[G4MH_PROGRAM_ID], is_verify); /* Load G4MH(1st) image. */ + load_icumh(&li[ICUMH_PROGRAM_ID], is_verify); /* Load ICUMH image. */ + load_g4mh_2nd(&li[G4MH_PROGRAM_ID + 1U], is_verify); /* Load G4MH(2nd) image. */ +} +/* End of function mcu_load_main(const LOAD_INFO *li, uint32_t is_verify) */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/loader_main_mcu.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/loader_main_mcu.h new file mode 100644 index 0000000..5cf989b --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/loader_main_mcu.h @@ -0,0 +1,45 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MCU Secure Boot Main header + ******************************************************************************/ + +#ifndef LOADER_MAIN_MCU_H__ +#define LOADER_MAIN_MCU_H__ + +#include +#include + +#define MCU_SEC_BOOT_ENABLE (1U) +#define MCU_IMG_NOT_ENCRYPTED (0U) + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ + +void mcu_img_decrypt(const LOAD_INFO *li); +void mcu_img_decrypt_end(const LOAD_INFO *li); +void mcu_load_main(const LOAD_INFO *li, uint32_t is_verify); + +#endif /* LOADER_MAIN_MCU_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/sdmac.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/sdmac.c new file mode 100644 index 0000000..2ff451f --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/sdmac.c @@ -0,0 +1,110 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function by SDMAC on ICUMX + ******************************************************************************/ +/****************************************************************************** + * @file sdmac.c + * - Version : 0.01 + * @brief Driver of SCMAC on ICUMX. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.06.2022 0.01 First Release + *****************************************************************************/ + +/* indelude */ +#include +#include +#include +#include +#include +#include + +void icu_sdmac_trans_start(const LOAD_INFO *li) +{ + uint16_t reg; + uint32_t len = li->image_size; + + /* src_addr and boot_addr must be 64-byte boundary. */ + dma_address_align_check(li->boot_addr, li->src_addr); + + /* If len is not 64-byte boundary, */ + /* round up len to 64-byte boundary. */ + len += SDMAC_FRACTION_MASK_64_BYTE; + len &= ~(SDMAC_FRACTION_MASK_64_BYTE); + + /* Clear channel 0 registers */ + mem_write32(ICUMX_DMACHRST, ICUMX_DMACHRST_CLR_CH0); + /* Clear flags */ + mem_write32(ICUMX_DMACHFCR_0, ICUMX_DMACHFCR_INIT); + /* Round-robin mode / Enable DMA transfer */ + mem_write16(ICUMX_DMAOR, ICUMX_DMAOR_INIT); + + /* DMA Transfer mode * + * Slow speed mode : Normal mode * + * Priority setting : Disable * + * Transfer Request source : Auto Request * + * Destination Address mode : Fixed * + * Source address mode : Incremented * + * DMA destination transaction size : 64byte * + * DMA source transaction size : 64byte */ + mem_write32(ICUMX_DMATMR_0, ICUMX_DMATMR_0_INIT); + + /* Set destination address */ + mem_write32(ICUMX_DMADAR_0, li->boot_addr); + /* Set source address */ + mem_write32(ICUMX_DMASAR_0, li->src_addr); + /* Set transfer size */ + mem_write32(ICUMX_DMATSR_0, len); + reg = mem_read16(ICUMX_DMACHCR_0); + /* Enable channel address error notification / Enable DMA */ + reg |= ICUMX_DMACHCR_0_START; + mem_write16(ICUMX_DMACHCR_0, reg); +} +/* End of function icu_sdmac_trans_start(LOAD_INFO *li) */ + +void icu_sdmac_trans_end(void) +{ + uint32_t reg; + + wdt_restart(); + /* Check end of DMA transfer. */ + do + { + reg = mem_read32(ICUMX_DMACHSTA_0); + /* Check error of DMA transfer */ + if ((reg & ICUMX_DMACHSTA_CAE) != DMACHSTA_CAE_BIT_NOERROR) + { + ERROR("SDMAC on ICUMX - Channel Address Error\n"); + panic; + } + } while ((reg & ICUMX_DMACHSTA_TE) != DMACHSTA_TE_END_DMA); + + /* Clear flags */ + mem_write32(ICUMX_DMACHFCR_0, ICUMX_DMACHFCR_INIT); +} +/* End of function icu_sdmac_trans_end(void) */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/sdmac.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/sdmac.h new file mode 100644 index 0000000..0f241c4 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/sdmac.h @@ -0,0 +1,99 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function by SDMAC on ICUMX header + ******************************************************************************/ + +#ifndef SDMAC_H__ +#define SDMAC_H__ + +#include +#include + +/* Prototype */ +void icu_sdmac_trans_start(const LOAD_INFO *li); +void icu_sdmac_trans_end(void); + +/* Definitions */ +#define ICUMX_DMACHRST_CLR_CH0 (0x00000001U) +#define ICUMX_DMACHRST_CLR_CH1 (0x00000002U) +#define ICUMX_DMACHRST_CLR_CH2 (0x00000004U) + +#define ICUMX_DMACHFCR_CAEC (0x00000008U) +#define ICUMX_DMACHFCR_TEC (0x00000002U) +#define ICUMX_DMACHFCR_DEC (0x00000001U) +#define ICUMX_DMACHFCR_INIT (ICUMX_DMACHFCR_CAEC | ICUMX_DMACHFCR_TEC | ICUMX_DMACHFCR_DEC) + +#define ICUMX_DMAOR_PR_ROUND_ROBIN (0x0300U) +#define ICUMX_DMAOR_DME_ENABLE (0x0001U) +#define ICUMX_DMAOR_INIT (ICUMX_DMAOR_PR_ROUND_ROBIN | ICUMX_DMAOR_DME_ENABLE) + +#define ICUMX_DMATMR_SLM_NORMAL (0x00000000U) +#define ICUMX_DMATMR_PRI_DISABLE (0x00000000U) +#define ICUMX_DMATMR_TRS_AT_REQ (0x00000000U) +#define ICUMX_DMATMR_TRS_HARD_REQ (0x00001000U) +#define ICUMX_DMATMR_DM_INC (0x00000400U) +#define ICUMX_DMATMR_SM_INC (0x00000100U) +#define ICUMX_DMATMR_DTS_64B (0x00000060U) +#define ICUMX_DMATMR_STS_64B (0x00000006U) +#define ICUMX_DMATMR_0_INIT (ICUMX_DMATMR_SLM_NORMAL | ICUMX_DMATMR_PRI_DISABLE | ICUMX_DMATMR_TRS_AT_REQ \ + | ICUMX_DMATMR_DM_INC | ICUMX_DMATMR_SM_INC | ICUMX_DMATMR_DTS_64B \ + | ICUMX_DMATMR_STS_64B) +#define ICUMX_DMATMR_1_INIT (ICUMX_DMATMR_SLM_NORMAL | ICUMX_DMATMR_PRI_DISABLE \ + | ICUMX_DMATMR_TRS_HARD_REQ | ICUMX_DMATMR_SM_INC | ICUMX_DMATMR_DTS_64B \ + | ICUMX_DMATMR_STS_64B) +#define ICUMX_DMATMR_2_INIT (ICUMX_DMATMR_SLM_NORMAL | ICUMX_DMATMR_PRI_DISABLE \ + | ICUMX_DMATMR_TRS_HARD_REQ | ICUMX_DMATMR_DM_INC | ICUMX_DMATMR_DTS_64B \ + | ICUMX_DMATMR_STS_64B) + +#define ICUMX_DMACHCR_CAEE_ENABLE (0x0010U) +#define ICUMX_DMACHCR_CAIE_ENABLE (0x0008U) +#define ICUMX_DMACHCR_IE_ENABLE (0x0002U) +#define ICUMX_DMACHCR_DE_ENABLE (0x0001U) +#define ICUMX_DMACHCR_0_START (ICUMX_DMACHCR_CAEE_ENABLE | ICUMX_DMACHCR_DE_ENABLE) +#define ICUMX_DMACHCR_1_START (ICUMX_DMACHCR_CAEE_ENABLE | ICUMX_DMACHCR_CAIE_ENABLE \ + | ICUMX_DMACHCR_DE_ENABLE) +#define ICUMX_DMACHCR_2_START (ICUMX_DMACHCR_CAEE_ENABLE | ICUMX_DMACHCR_CAIE_ENABLE \ + | ICUMX_DMACHCR_IE_ENABLE | ICUMX_DMACHCR_DE_ENABLE) + +#define ICUMX_DMACHSTA_CAE (0x00000008U) +#define ICUMX_DMACHSTA_TE (0x00000002U) +#define DMACHSTA_CAE_BIT_NOERROR (0x00000000U) +#define DMACHSTA_TE_END_DMA (0x00000002U) + +#define ICUMX_DMARS_TC_1 (0x00010000U) +#define ICUMX_DMARS_TL_TMR_DTS (0x00001000U) +#define ICUMX_DMARS_TL_TMR_STS (0x00000000U) +#define ICUMX_DMARS_FPT_DE_IS_1 (0x00000000U) +#define ICUMX_DMARS_PLE_ENABLE (0x00000400U) +#define ICUMX_DMARS_PLE_DISABLE (0x00000000U) +#define ICUMX_DMARS_RS_FOR_CH2 (0x00000001U) +#define ICUMX_DMARS_1_INIT (ICUMX_DMARS_TC_1 | ICUMX_DMARS_TL_TMR_DTS | ICUMX_DMARS_FPT_DE_IS_1 \ + | ICUMX_DMARS_PLE_ENABLE) +#define ICUMX_DMARS_2_INIT (ICUMX_DMARS_TC_1 | ICUMX_DMARS_TL_TMR_STS | ICUMX_DMARS_FPT_DE_IS_1 \ + | ICUMX_DMARS_PLE_DISABLE | ICUMX_DMARS_RS_FOR_CH2) + +#define SDMAC_FRACTION_MASK_64_BYTE (0x3FU) + +#endif /* SDMAC_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/sdmac_register.h b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/sdmac_register.h new file mode 100644 index 0000000..69be66a --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mcu/sdmac_register.h @@ -0,0 +1,77 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Registers of SDMAC on ICUMX + ******************************************************************************/ + +#ifndef SDMAC_REGISTER_H__ +#define SDMAC_REGISTER_H__ + +/* SDMAC on ICUMX base address */ +#define ICUMX_SDMAC_BASE (0xFF600000U) + +/* Channel offset address */ +#define ICUMX_SDMAC_CH0 (0x80U * 0U) +#define ICUMX_SDMAC_CH1 (0x80U * 1U) +#define ICUMX_SDMAC_CH2 (0x80U * 2U) + +/* SDMAC Interrupt Status Register */ +#define ICUMX_DMAISTA (ICUMX_SDMAC_BASE + 0x0020U) +/* SDMAC Operation Register */ +#define ICUMX_DMAOR (ICUMX_SDMAC_BASE + 0x0060U) +/* SDMAC Channel Reset Register */ +#define ICUMX_DMACHRST (ICUMX_SDMAC_BASE + 0x0080U) +/* SDMAC Source Address Register */ +#define ICUMX_DMASAR_0 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH0) +#define ICUMX_DMASAR_1 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH1) +#define ICUMX_DMASAR_2 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH2) +/* SDMAC Destination Address Register */ +#define ICUMX_DMADAR_0 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH0) +#define ICUMX_DMADAR_1 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH1) +#define ICUMX_DMADAR_2 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH2) +/* SDMAC Transfer Size Register */ +#define ICUMX_DMATSR_0 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH0) +#define ICUMX_DMATSR_1 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH1) +#define ICUMX_DMATSR_2 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH2) +/* SDMAC Transfer Mode Register */ +#define ICUMX_DMATMR_0 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH0) +#define ICUMX_DMATMR_1 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH1) +#define ICUMX_DMATMR_2 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH2) +/* SDMAC Channel Control Register */ +#define ICUMX_DMACHCR_0 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH0) +#define ICUMX_DMACHCR_1 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH1) +#define ICUMX_DMACHCR_2 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH2) +/* SDMAC Channel Status Register */ +#define ICUMX_DMACHSTA_0 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH0) +#define ICUMX_DMACHSTA_1 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH1) +#define ICUMX_DMACHSTA_2 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH2) +/* SDMAC Channel Flag Clear Register */ +#define ICUMX_DMACHFCR_0 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH0) +#define ICUMX_DMACHFCR_1 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH1) +#define ICUMX_DMACHFCR_2 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH2) +/* SDMAC Resource Select Register */ +#define ICUMX_DMARS_1 (ICUMX_SDMAC_BASE + 0x2040U + ICUMX_SDMAC_CH1) +#define ICUMX_DMARS_2 (ICUMX_SDMAC_BASE + 0x2040U + ICUMX_SDMAC_CH2) + +#endif /* SDMAC_REGISTER_H__ */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mk.sh b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mk.sh new file mode 100644 index 0000000..5003967 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/mk.sh @@ -0,0 +1,54 @@ +#!/bin/bash +export LANG=C + +_no_clean=0 +_loglevel=1 +_build_param="" +_default_b="LSI=V4H FORCE_115200=1" +_echo="@" +if [ -f env.ini ]; then + . env.ini +fi + +while getopts "cl:vp:h" opt; do + case $opt in + c) _no_clean=1 + ;; + l) _loglevel=$OPTARG + ;; + v) _echo="" + ;; + p) if [ "x$OPTARG" = "x0" ]; then + _build_param="${_build_param} MEASURE_TIME=1 MEASURE_TIME_NOPRINT=1" + elif [ "x$OPTARG" = "x1" ]; then + _build_param="${_build_param} MEASURE_TIME=1" + fi + ;; + h) + echo "usage: $0 [option]" + echo " -l set loglevel (default: $_loglevel)" + echo " -p enable MEASURE_TIME (0: NO PRINT, 1: PRINT)" + echo "" + echo " -c do not clean before build" + echo " -v build verbosely" + exit 0 + esac +done +shift $((OPTIND-1)) + +if [ $_no_clean -ne 1 ]; then + make clean + make CC=echo AS=echo LD=echo OC=echo OD=echo >& /dev/null +fi +BUILD_PARAM="${BUILD_PARAM} ${_build_param} LOG_LEVEL=$_loglevel V=$_echo" + +_uuid=`uuidgen` +_obj_bat=/run/lock/${_uuid}.bat + GHS_PATH=`winepath -w $(readlink -f ../comp_202015)` + echo "@path %path%;${GHS_PATH}" > ${_obj_bat} + echo "@set GHS_LMHOST=@10.230.22.105" >> ${_obj_bat} + echo "@set GHS_LMWHICH=ghs" >> ${_obj_bat} + echo "make -f dos.mk ${_default_b} ${BUILD_PARAM} $*" >> ${_obj_bat} + echo 'set /p "_wait=WAIT..."' >> ${_obj_bat} +wineconsole z\:\\run\\lock\\${_uuid}.bat +rm ${_obj_bat} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/protect/ram_protection.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/protect/ram_protection.c new file mode 100644 index 0000000..1a4fec5 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/protect/ram_protection.c @@ -0,0 +1,271 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : memory protection function + ******************************************************************************/ + /****************************************************************************** + * @file ram_protection.c + * - Version : 0.03 + * @brief Access protection setting of memory. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 19.12.2022 0.01 First Release + * : 11.01.2024 0.02 Added icu_remove_write_access function. + * : 19.01.2024 0.03 Updated debug log. + * : 31.01.2024 0.04 Fixed the error in SECDIVn register + * setting value for ram_protect_init_4_rtsram() + * and ram_protect_init_4_rtvram. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Value for calculating the offset address to set in SECDIVD. */ +#define RTSRAM_SECDIVD_SUBVALUE (0xE0000000U) /* RT-VRAM0 Base address */ +#define RTVRAM_SECDIVD_SUBVALUE (0xE2000000U) /* RT-VRAM1 Base address */ + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +static void ram_protect_init_4_rtsram(void); +static void ram_protect_init_4_rtvram(const RTRAM_PROTECTION_STRUCTUR *cnf_tbl); +static void ram_protect_init_4_sysram(void); +static void ram_protect_init_4_dram(void); +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ + +void ram_protection(void) +{ +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + /* RT-SRAM */ + NOTICE("RT-SRAM Protection setting...\n"); + ram_protect_init_4_rtsram(); + NOTICE("finish!\n"); + + /* RT-VRAM */ + NOTICE("RT-VRAM Protection setting...\n"); + ram_protect_init_4_rtvram(g_rtvram1_protection_table_1); + NOTICE("finish!\n"); + + /* System RAM */ + NOTICE("System RAM Protection setting...\n"); + ram_protect_init_4_sysram(); + NOTICE("finish!\n"); + + /* DRAM */ + NOTICE("DRAM Protection setting...\n"); + ram_protect_init_4_dram(); + NOTICE("finish!\n"); +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ +} +/* End of function ram_protection(void) */ + +#if (RCAR_LSI == RCAR_S4) +void ram_protection_final(void) +{ +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + NOTICE("RT-VRAM Protection setting(finally)...\n"); + ram_protect_init_4_rtvram(g_rtvram1_protection_table_2); + NOTICE("finish!\n"); +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ +} +/* End of function ram_protection_final(void) */ +#endif /* #if (RCAR_LSI == RCAR_S4) */ + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +static void ram_protect_init_4_rtsram(void) +{ + uint32_t loop; + uint32_t val; + uint32_t set_val; + uint32_t addr; + + /* set division point for RT-SRAM */ + for (loop = 0U; loop < (RAM_PROTECTION_MAX - 1U); ++loop) + { + addr = get_rtsram_secdivd_addr(loop); + val = mem_read32(addr); + val &= ~(RTSRAM_SECDIVD_DIVADDR_MASK); + set_val = g_rtsram_protection_table[loop + 1U].addr - RTSRAM_SECDIVD_SUBVALUE; + val |= ((set_val & RTSRAM_ADDR_OFFSET_MASK) >> 12U); + mem_write32(addr, val); + INFO("SECDIVD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } + + /* Set division area protection register for RT-SRAM */ + for (loop = 0U; loop < RAM_PROTECTION_MAX; ++loop) + { + /* Read Access Configuration */ + addr = get_rtsram_secctrrd_addr(loop); + val = mem_read32(addr); + val &= ~(RTSRAM_SECCTRRD_SECGRP_MASK | RTSRAM_SECCTRRD_SAFGRP_MASK); + val |= g_rtsram_protection_table[loop].setting_value.read_val; + mem_write32(addr, val); + INFO("SECCTRRD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + /* Write Access Configuration */ + addr = get_rtsram_secctrwd_addr(loop); + val = mem_read32(addr); + val &= ~(RTSRAM_SECCTRWD_SECGRP_MASK | RTSRAM_SECCTRWD_SAFGRP_MASK); + val |= g_rtsram_protection_table[loop].setting_value.write_val; + mem_write32(addr, val); + INFO("SECCTRWD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } +} +/* End of function ram_protect_init_4_rtsram(void) */ + +static void ram_protect_init_4_rtvram(const RTRAM_PROTECTION_STRUCTUR *cnf_tbl) +{ + uint32_t loop; + uint32_t val; + uint32_t set_val; + uint32_t addr; + + /* set division point for RT-VRAM1 */ + for (loop = 0U; loop < (RAM_PROTECTION_MAX - 1U); ++loop) + { + addr = get_rtvram_secdivd_addr(loop); + val = mem_read32(addr); + val &= ~(RTVRAM_SECDIVD_DIVADDR_MASK); + set_val = cnf_tbl[loop + 1U].addr - RTVRAM_SECDIVD_SUBVALUE; + val |= ((set_val & RTVRAM_ADDR_MASK) >> 12U); + mem_write32(addr, val); + INFO("SECDIVD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } + + /* Set division area protection register for RT-VRAM1 */ + for (loop = 0U; loop < RAM_PROTECTION_MAX; ++loop) + { + /* Read Access Configuration */ + addr = get_rtvram_secctrrd_addr(loop); + val = mem_read32(addr); + val &= ~(RTVRAM_SECCTRRD_SECGRP_MASK | RTVRAM_SECCTRRD_SAFGRP_MASK); + val |= cnf_tbl[loop].setting_value.read_val; + mem_write32(addr, val); + INFO("SECCTRRD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + /* Write Access Configuration */ + addr = get_rtvram_secctrwd_addr(loop); + val = mem_read32(addr); + val &= ~(RTVRAM_SECCTRWD_SECGRP_MASK | RTVRAM_SECCTRWD_SAFGRP_MASK); + val |= cnf_tbl[loop].setting_value.write_val; + mem_write32(addr, val); + INFO("SECCTRWD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } +} +/* End of function ram_protect_init_4_rtvram(const RTRAM_PROTECTION_STRUCTUR *cnf_tbl) */ + + +static void ram_protect_init_4_sysram(void) +{ + uint32_t loop; + uint32_t val; + uint32_t addr; + + /* set division point for SystemRAM */ + for (loop = 0U; loop < (RAM_PROTECTION_MAX - 1U); ++loop) + { + addr = get_sptdivcr_addr(loop); + val = mem_read32(addr); + val &= ~(AXMM_SPTDIVCR_DIVADDR_MASK); + val |= ((g_system_ram_protection_table[loop + 1U].addr & SYSTEM_RAM_ADDR_MASK) >> 12U); + mem_write32(addr, val); + INFO("SPTDIVCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } + + /* Set division area protection register for RT-VRAM */ + for (loop = 0U; loop < RAM_PROTECTION_MAX; ++loop) + { + /* Read / Write Access Configuration */ + addr = get_sptrgncr_addr(loop); + val = g_system_ram_protection_table[loop].setting_value.rw_val; + mem_write32(addr, val); + INFO("SPTRGNCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + /* Secure setting */ + addr = get_sptseccr_addr(loop); + val = mem_read32(addr); + val &= ~(AXMM_SPTSECCR_SECGRP_MASK | AXMM_SPTSECCR_SECGWP_MASK); + val |= g_system_ram_protection_table[loop].setting_value.sec_val; + mem_write32(addr, val); + INFO("SPTSECCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } +} +/* End of function ram_protect_init_4_sysram(void) */ + + +static void ram_protect_init_4_dram(void) +{ + uint32_t loop; + uint32_t val; + uint32_t addr; + + /* set division point for SDRAM */ + for (loop = 0U; loop < (DRAM_PROTECTION_MAX - 1U); ++loop) + { + addr = get_dptdivcr_addr(loop); + val = mem_read32(addr); + val &= ~(AXMM_DPTDIVCR_DIVADDR_MASK); + val |= ((g_dram_protection_table[loop + 1U].addr & SDRAM_ADDR_MASK) >> 16U); + mem_write32(addr, val); + INFO("DPTDIVCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } + + /* Set division area protection register for RT-VRAM */ + for (loop = 0U; loop < DRAM_PROTECTION_MAX; ++loop) + { + /* Read / Write Access Configuration */ + addr = get_dptrgncr_addr(loop); + val = g_dram_protection_table[loop].setting_value.rw_val; + mem_write32(addr, val); + INFO("DPTRGNCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + /* Secure setting */ + addr = get_dptseccr_addr(loop); + val = mem_read32(addr); + val &= ~(AXMM_DPTSECCR_SECGRP_MASK | AXMM_DPTSECCR_SECGWP_MASK); + val |= g_dram_protection_table[loop].setting_value.sec_val; + mem_write32(addr, val); + INFO("DPTSECCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } +} +/* End of function ram_protect_init_4_dram(void) */ +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ + +void icu_remove_write_access(void) +{ +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + uint32_t reg; + uint32_t addr; + + addr = get_sptrgncr_addr(SYSTEM_RAM_CX_2ND_IPL); + reg = mem_read32(addr); + reg |= REGIONID0_WRITE_PRIVILEGE; /* Remove write privilege to System RAM Area0 from RGID0(ICUMX). */ + mem_write32(addr, reg); +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ +} +/* End of function icu_remove_write_access(void) */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/protect/region_id.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/protect/region_id.c new file mode 100644 index 0000000..51c8f16 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/protect/region_id.c @@ -0,0 +1,587 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Region ID protection function + ******************************************************************************/ + /****************************************************************************** + * @file region_id.c + * - Version : 0.08 + * @brief Each module to R/W access protection by Region ID. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.03.2022 0.01 First Release + * : 23.05.2022 0.02 Modify remap address + * : 21.10.2022 0.03 Supported for V4H + * : 23.01.2023 0.04 Remove pre-process branch for S4N. + * Added a process for judgement the number of + * Clusters to the rgid_gid_setting function. + * Changed to temporarily sweeten the protection + * setting only when the IPL is running. + * : 21.08.2023 0.05 Add support for V4M. + * : 13.11.2023 0.06 Changed to use CCI MPU GID register setting + * table in rgid_gid_setting function. + * : 13.09.2024 0.07 Change setting order of Region ID. + * (Swap Write and Secure.) + * : 06.01.2025 0.08 Added IMP Region ID setting process. + * Added Domain protection setting process. + * Added IPMMU Region ID setting process. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Unregistered base address of Region ID in SIC Remap. */ +#if (RCAR_LSI == RCAR_S4) +#define RGID_SICREMAP_NUM (1U) +#define RGID_BASE1 (0xFF800000U) + +#define GID_SETTING_VALUE (0x0002BFC4U) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define RGID_SICREMAP_NUM (5U) +#define RGID_BASE1 (0xFD800000U) +#define RGID_BASE2 (0xE7A00000U) +#define RGID_BASE3 (0xEB800000U) +#define RGID_BASE4 (0xFE600000U) +#define RGID_BASE5 (0xFF800000U) +/* For IPMMU Region ID setting */ +#define RGID_IPMMU_SICREMAP_NUM (3U) +#define RGID_IPMMU_BASE1 (0xEE400000U) +#define RGID_IPMMU_BASE2 (0xEEC00000U) +#define RGID_IPMMU_BASE3 (0xEEE00000U) +#endif + +#define RGID_M_SDHI (38U) + +#define RGIDMEN_RTDM_BASE (0xFD441800U) /* 0xFFC41800:Remap 10 */ +#define RGIDMEN_SYDM_BASE (0xFCB51800U) /* 0xE7751800:Remap 5 */ +#define RGIDMEN_RGIDEN_MASK (0x0000FFFFU) + +#define GID_BASE (0xF12F0000U) + +#if (RCAR_LSI == RCAR_V4H) +#define IMP_IMPSLV_PRESET (0xFF902000U) /* PRESET Register (IMPSLV) */ +#define IMPSLV_PRESET_INIT_SET_VAL (0x0000000AU) /* Initial set value */ +#define IMP_SPMI_PRESET (0xFFA8E000U) /* PRESET Register (SPMI) */ +#define SPMI_PRESET_INIT_SET_VAL (0x0000000AU) /* Initial set value */ +#define IMP_SPMI_MBCTRL120 (0xFFA8C868U) /* Master Bus ConTRoL120 (SPMI) */ +#define SPMI_MBCTRL120_INIT_SET_VAL (0x00030000U) /* Initial set value */ +#define IMP_SPMI_MBCTRL130 (0xFFA8D028U) /* Master Bus ConTRoL130 (SPMI) */ +#define SPMI_MBCTRL130_INIT_SET_VAL (0x00030000U) /* Initial set value */ +#define IMP_SPMC_PRESET (0xFFAB2000U) /* PRESET Register (SPMC) */ +#define SPMC_PRESET_INIT_SET_VAL (0x00000009U) /* Initial set value */ +#endif /* (RCAR_LSI == RCAR_V4H) */ + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +static void rgid_rtdma_master_setting(void); +static void rgid_sysdma_master_setting(void); +static uint32_t get_rgidmen_rtdm_addr(uint32_t module, uint32_t ch); +static uint32_t get_rgidmen_sydm_addr(uint32_t module, uint32_t ch); +static void rgid_gid_setting(void); +#if (RCAR_SA9_TYPE == FLASH_BOOT) +static void set_rgid_rtdma_master(uint32_t module, uint32_t ch, uint32_t rgid); +#else /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ +static void set_rgid_master(uint32_t id, uint32_t val); +#endif /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ +static void rgid_register_protection(void); +static void domain_protection_setting(void); +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ + +void rgid_protection(void) +{ +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + uint32_t loop; + + REMAP_TABLE rgid_remap_tbl[RGID_SICREMAP_NUM] = { + {RGID_BASE1, 0U}, +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + {RGID_BASE2, 0U}, + {RGID_BASE3, 0U}, + {RGID_BASE4, 0U}, + {RGID_BASE5, 0U}, +#endif +}; + + REMAP_TABLE ipmmu_rgid_remap_tbl[RGID_IPMMU_SICREMAP_NUM] = { + {RGID_IPMMU_BASE1, 0U}, + {RGID_IPMMU_BASE2, 0U}, + {RGID_IPMMU_BASE3, 0U}, + }; + + /* Set domain protection registers */ + domain_protection_setting(); + + /* Set RGID of DMA (Master) */ + rgid_rtdma_master_setting(); + rgid_sysdma_master_setting(); + + /* Set RGID of GID */ + rgid_gid_setting(); + + /* Register of IPMMU Region ID Base */ + for (loop = 0U; loop < RGID_IPMMU_SICREMAP_NUM; loop++) + { + remap_register(ipmmu_rgid_remap_tbl[loop].base_addr, &ipmmu_rgid_remap_tbl[loop].rmp_addr); + } + + /* IPMMU Region ID setting */ + for(loop = 0U; loop < IPMMU_RGID_MAX; loop++) + { + /* Set access protection setting value of IPMMU */ + mem_write32(g_ipmmu_rgid_tbl[loop].addr, g_ipmmu_rgid_tbl[loop].value); + + INFO("IMRGID_IPMMU[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_ipmmu_rgid_tbl[loop].addr, mem_read32(g_ipmmu_rgid_tbl[loop].addr), g_ipmmu_rgid_tbl[loop].value); + } + + for(loop = 0U; loop < IPMMU_RGID_MAX; loop++) + { + /* Set access protection setting value of IPMMU Secure */ + mem_write32(g_ipmmu_rgid_sec_tbl[loop].addr, g_ipmmu_rgid_sec_tbl[loop].value); + + INFO("IMSECGRP_IPMMU[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_ipmmu_rgid_sec_tbl[loop].addr, mem_read32(g_ipmmu_rgid_sec_tbl[loop].addr), g_ipmmu_rgid_sec_tbl[loop].value); + } + + for(loop = 0U; loop < IPMMU_RGID_MAX; loop++) + { + /* Set access protection setting value of IPMMU Region ID Enable */ + mem_write32(g_ipmmu_rgid_en_tbl[loop].addr, g_ipmmu_rgid_en_tbl[loop].value); + + INFO("IMRGIDEN_IPMMU[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_ipmmu_rgid_en_tbl[loop].addr, mem_read32(g_ipmmu_rgid_en_tbl[loop].addr), g_ipmmu_rgid_en_tbl[loop].value); + } + + /* Unregister of IPMMU Region ID Base */ + for (loop = 0U; loop < RGID_IPMMU_SICREMAP_NUM; loop++) + { + remap_unregister(ipmmu_rgid_remap_tbl[loop].rmp_addr); + } + + /* Register of Region ID Base */ + for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++) + { + remap_register(rgid_remap_tbl[loop].base_addr, &rgid_remap_tbl[loop].rmp_addr); + } + +#if (RCAR_LSI == RCAR_V4H) + /* For the IMP Region ID setting flow, see "Table U34.3" in */ + /* "R-Car Series, V4H Series User's Manual". */ + /* Following setting is described as step7 in "Table U34.3". */ + mem_write32(IMP_IMPSLV_PRESET, IMPSLV_PRESET_INIT_SET_VAL); + mem_write32(IMP_SPMI_PRESET, SPMI_PRESET_INIT_SET_VAL); + mem_write32(IMP_SPMI_MBCTRL120, SPMI_MBCTRL120_INIT_SET_VAL); + mem_write32(IMP_SPMI_MBCTRL130, SPMI_MBCTRL130_INIT_SET_VAL); + mem_write32(IMP_SPMC_PRESET, SPMC_PRESET_INIT_SET_VAL); + + /* IMP Region ID setting */ + for(loop = 0U; loop < IMP_MASTER_MAX; loop++) + { + /* Set access protection setting value of IMP (Master) */ + mem_write32(g_imp_rgid_m_tbl[loop].addr, g_imp_rgid_m_tbl[loop].value); + + INFO("IMP_Master[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_imp_rgid_m_tbl[loop].addr, mem_read32(g_imp_rgid_m_tbl[loop].addr), g_imp_rgid_m_tbl[loop].value); + } + + for(loop = 0U; loop < IMP_SLAVE_MAX; loop++) + { + /* Set access protection setting value of IMP (Slave) */ + mem_write32(g_imp_rgid_s_tbl[loop].addr, g_imp_rgid_s_tbl[loop].value); + + INFO("IMP_Slave[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_imp_rgid_s_tbl[loop].addr, mem_read32(g_imp_rgid_s_tbl[loop].addr), g_imp_rgid_s_tbl[loop].value); + } +#endif /* (RCAR_LSI == RCAR_V4H) */ + + for(loop = 0U; loop < RGID_M_MAX; loop++) + { + /* Set access protection setting value of Region ID (Master) */ + mem_write32(g_rgid_m_tbl[loop].addr, g_rgid_m_tbl[loop].value); + + INFO("RGIDM[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_m_tbl[loop].addr, mem_read32(g_rgid_m_tbl[loop].addr), g_rgid_m_tbl[loop].value); + } + + for(loop = 0U; loop < RGID_R_MAX; loop++) + { + /* Set access protection setting value of Region ID (READ) */ + mem_write32(g_rgid_r_tbl[loop].addr, g_rgid_r_tbl[loop].value); /* Read */ + + INFO("RGIDR[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_r_tbl[loop].addr, mem_read32(g_rgid_r_tbl[loop].addr), g_rgid_r_tbl[loop].value); + } + + wdt_restart(); + + for(loop = 0U; loop < RGID_SEC_MAX; loop++) + { + /* Set access protection setting value of Region ID (Secure) */ + mem_write32(g_rgid_sec_tbl[loop].addr, g_rgid_sec_tbl[loop].value); /* Secure */ + + INFO("SEC_MODID[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_sec_tbl[loop].addr, mem_read32(g_rgid_sec_tbl[loop].addr), g_rgid_sec_tbl[loop].value); + } + + wdt_restart(); + + for(loop = 0U; loop < RGID_W_MAX; loop++) + { + /* Set access protection setting value of Region ID (Write) */ + mem_write32(g_rgid_w_tbl[loop].addr, g_rgid_w_tbl[loop].value); /* Write */ + + INFO("RGIDW[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_w_tbl[loop].addr, mem_read32(g_rgid_w_tbl[loop].addr), g_rgid_w_tbl[loop].value); + } + + wdt_restart(); + + /* Unregister of Region ID Base */ + for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++) + { + remap_unregister(rgid_remap_tbl[loop].rmp_addr); + } +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ +} +/* End of function rgid_protection(void) */ + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +static void rgid_rtdma_master_setting(void) +{ + uint32_t addr; + uint32_t val; + + /* Region ID(Master) RT-DMAC set:Region ID (i = 0-3(S4/V4H) 0-1(V4M), j = 0-15) */ + for(uint32_t module = 0U; module < RTDMA_MODULE_MAX; module++) { + for(uint32_t ch = 0U; ch < RTDMA_CH_MAX; ch++) { + addr = get_rgidmen_rtdm_addr(module, ch); + val = mem_read32(addr); + val &= ~(RGIDMEN_RGIDEN_MASK); + val |= g_rgid_rtdma_setting_value[module][ch][0U]; + mem_write32(addr, val); + + INFO("RGIDMEN_RTDM[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val); + + addr = dma_get_rtdma_regionid_addr(module, ch); + val = mem_read32(addr); + val &= ~(DMA_REGIONID_MASK); + val |= g_rgid_rtdma_setting_value[module][ch][1U]; + mem_write32(addr, val); + + INFO("RDMREGIONID_[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val); + } + } +} +/* End of function rgid_rtdma_master_setting(void) */ + +static uint32_t get_rgidmen_rtdm_addr(uint32_t module, uint32_t ch) +{ + return (RGIDMEN_RTDM_BASE + (module * 0x40U) + (ch * 0x04U)); +} +/* End of function get_rgidmen_rtdm_addr(uint32_t module, uint32_t ch) */ + +static void rgid_sysdma_master_setting(void) +{ + uint32_t addr; + uint32_t val; + + + /* Region ID(Master) SYSDMAC set:Region ID (i = 0, j = 0-15)(i = 1, j = 0-15(S4/V4H) 0-7(V4M)) */ + for(uint32_t module = 0U; module < SYSDMA_MODULE_MAX; module++) { + for(uint32_t ch = 0U; ch < SYSDMA_CH_MAX; ch++) { + if (g_rgid_sysdma_setting_value[module][ch][1U] != RGID_INVALID) + { + addr = get_rgidmen_sydm_addr(module, ch); + val = mem_read32(addr); + val &= ~(RGIDMEN_RGIDEN_MASK); + val |= g_rgid_sysdma_setting_value[module][ch][0U]; + mem_write32(addr, val); + + INFO("RGIDMEN_SYDM[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val); + + addr = dma_get_sysdma_regionid_addr(module, ch); + val = mem_read32(addr); + val &= ~(DMA_REGIONID_MASK); + val |= g_rgid_sysdma_setting_value[module][ch][1U]; + mem_write32(addr, val); + + INFO("SDMREGIONID_[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val); + } + } + } +} +/* End of function rgid_sysdma_master_setting(void) */ + +static uint32_t get_rgidmen_sydm_addr(uint32_t module, uint32_t ch) +{ + return (RGIDMEN_SYDM_BASE + (module * 0x40U) + (ch * 0x04U)); +} +/* End of function get_rgidmen_sydm_addr(uint32_t module, uint32_t ch) */ + +static void rgid_gid_setting(void) +{ + uint32_t rmp_addr; + + /* Register of GID Base */ + remap_register(GID_BASE, &rmp_addr); + + for(uint32_t loop = 0U; loop < RGID_GID_MAX; loop++) + { + /* Set access protection setting value of CCI MPU GID register */ + mem_write32(g_rgid_gid_tbl[loop].addr, g_rgid_gid_tbl[loop].value); + + INFO("GID[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_gid_tbl[loop].addr, mem_read32(g_rgid_gid_tbl[loop].addr), g_rgid_gid_tbl[loop].value); + } + + /* Unregister of GID Base */ + remap_unregister(rmp_addr); +} +/* End of function rgid_gid_setting(void) */ +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ + +/* Change the Region ID of the Master to be used for the transfer to the value of the argument. */ +void set_master_rgid_4_tfr_mod(void) +{ +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +#if (RCAR_SA9_TYPE == FLASH_BOOT) + uint32_t module; + uint32_t ch; + + module = 0U; + ch = 0U; + set_rgid_rtdma_master(module, ch, RGID_0); +#else/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ + set_rgid_master(RGID_M_SDHI, RGID_0); +#endif/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ +#endif/* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ +} +/* End of function set_master_rgid_4_tfr_mod(void) */ + +/* Set the final expected value of Region ID. */ +void rgid_protection_final(void) +{ +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +#if (RCAR_SA9_TYPE == FLASH_BOOT) + /* Updated Master authority for RT-DMA. */ + rgid_rtdma_master_setting(); +#else/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ + /* Updated Master authority for SDHI. */ + set_rgid_master(RGID_M_SDHI, RGID_2); +#endif/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ + /* Access protection setting function for AXI bus of Region ID register */ + rgid_register_protection(); +#endif/* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ +} +/* End of function rgid_protection_final(void) */ + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +#if (RCAR_SA9_TYPE == FLASH_BOOT) +static void set_rgid_rtdma_master(uint32_t module, uint32_t ch, uint32_t rgid) +{ + uint32_t addr; + uint32_t val; + + /* Region ID(Master) RT-DMAC set:Region ID */ + addr = get_rgidmen_rtdm_addr(module, ch); + val = mem_read32(addr); + val |= (1UL << rgid); + mem_write32(addr, val); + + INFO("RGIDMEN_RTDM[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val); + + addr = dma_get_rtdma_regionid_addr(module, ch); + val = mem_read32(addr); + val &= ~(DMA_REGIONID_MASK); + val |= rgid; + mem_write32(addr, val); + + INFO("RDMREGIONID_[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val); +} +/* End of function set_rgid_rtdma_master(uint32_t module, uint32_t ch, uint32_t rgid) */ +#else /* (RCAR_SA9_TYPE == FLASH_BOOT) */ +/* Individual setting function of RGIDM register */ +static void set_rgid_master(uint32_t id, uint32_t rgid) +{ +#if (RCAR_LSI == RCAR_S4) + uint32_t loop; + + REMAP_TABLE rgid_remap_tbl[RGID_SICREMAP_NUM] = { + {RGID_BASE1, 0U}, + }; + + /* Register of Region ID Base */ + for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++) + { + remap_register(rgid_remap_tbl[loop].base_addr, &rgid_remap_tbl[loop].rmp_addr); + } + + /* Set access protection setting value of Region ID (Master) */ + mem_write32(g_rgid_m_tbl[id].addr, rgid); + INFO("RGIDM[%d](0x%08x) =\t0x%08x\n", id, g_rgid_m_tbl[id].addr, mem_read32(g_rgid_m_tbl[id].addr)); + + /* Unregister of Region ID Base */ + for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++) + { + remap_unregister(rgid_remap_tbl[loop].rmp_addr); + } +#endif /* #if (RCAR_LSI == RCAR_S4) */ +} +/* End of function set_rgid_master(uint32_t id, uint32_t rgid) */ +#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + +/* Access protection setting function for AXI bus of Region ID register */ +static void rgid_register_protection(void) +{ + uint32_t loop; + + REMAP_TABLE rgid_remap_tbl[RGID_SICREMAP_NUM] = { + {RGID_BASE1, 0U}, +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + {RGID_BASE2, 0U}, + {RGID_BASE3, 0U}, + {RGID_BASE4, 0U}, + {RGID_BASE5, 0U}, +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + }; + + /* Register of Region ID Base */ + for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++) + { + remap_register(rgid_remap_tbl[loop].base_addr, &rgid_remap_tbl[loop].rmp_addr); + } + + for(loop = 0U; loop < RGID_AXI_MAX; loop++) + { + /* Set access protection setting value of Region ID (AXI bus of Region ID register) */ + mem_write32(g_rgid_axi_tbl[loop].addr, g_rgid_axi_tbl[loop].value); + + INFO("RGID_AXI[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_axi_tbl[loop].addr, mem_read32(g_rgid_axi_tbl[loop].addr), g_rgid_axi_tbl[loop].value); + } + + /* Unregister of Region ID Base */ + for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++) + { + remap_unregister(rgid_remap_tbl[loop].rmp_addr); + } +} +/* End of function rgid_register_protection(void) */ + +static void domain_protection_setting(void) +{ + uint32_t loop; + + /* Set CPG domain write access control register */ + for(loop = 0U; loop <= CPG_PROTECTION; loop++) + { + cpg_reg_write((CPG_D1WACRA00 + (loop * 4U)), (CPG_D1WACRA00 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D2WACRA00 + (loop * 4U)), (CPG_D2WACRA00 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D3WACRA00 + (loop * 4U)), (CPG_D3WACRA00 + (loop * 4U)), WRITE_ENABLE); + } + + /* Set PFC domain write access control register */ + /* Port Group0 */ + pfc_reg_write(PFC_DM1PR0_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR0_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR0_RW, WRITE_ENABLE); + + /* Port Group1 */ + pfc_reg_write(PFC_DM1PR1_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR1_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR1_RW, WRITE_ENABLE); + + /* Port Group2 */ + pfc_reg_write(PFC_DM1PR2_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR2_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR2_RW, WRITE_ENABLE); + + /* Port Group3 */ + pfc_reg_write(PFC_DM1PR3_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR3_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR3_RW, WRITE_ENABLE); + + /* Port Group4 */ + pfc_reg_write(PFC_DM1PR4_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR4_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR4_RW, WRITE_ENABLE); + + /* Port Group5 */ + pfc_reg_write(PFC_DM1PR5_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR5_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR5_RW, WRITE_ENABLE); + + /* Port Group6 */ + pfc_reg_write(PFC_DM1PR6_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR6_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR6_RW, WRITE_ENABLE); + + /* Port Group7 */ + pfc_reg_write(PFC_DM1PR7_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR7_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR7_RW, WRITE_ENABLE); + +#if (RCAR_LSI == RCAR_V4H) + /* Port Group8 */ + pfc_reg_write(PFC_DM1PR8_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR8_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR8_RW, WRITE_ENABLE); +#endif/* #if (RCAR_LSI == RCAR_V4H) */ + + /* System Group */ + pfc_reg_write(PFC_DM1PRSYS_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PRSYS_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PRSYS_RW, WRITE_ENABLE); + + /* Set SYSC domain write access control register */ + for(loop = 0U; loop <= SYSC_PROTECTION; loop++) + { + mem_write32((SYSC_SYSCD1WACR0 + (loop * 4U)), WRITE_ENABLE); + mem_write32((SYSC_SYSCD2WACR0 + (loop * 4U)), WRITE_ENABLE); + mem_write32((SYSC_SYSCD3WACR0 + (loop * 4U)), WRITE_ENABLE); + } + + /* Set Reset domain write access control register */ + for(loop = 0U; loop <= RESET_PROTECTION; loop++) + { + cpg_reg_write((CPG_D1WACR_MSTPCR0 + (loop * 4U)), (CPG_D1WACR_MSTPCR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D1WACR_RAHSR0 + (loop * 4U)), (CPG_D1WACR_RAHSR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D1WACR_SRCR0 + (loop * 4U)), (CPG_D1WACR_SRCR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D1WACR_SRSTCLR0 + (loop * 4U)), (CPG_D1WACR_SRSTCLR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D2WACR_MSTPCR0 + (loop * 4U)), (CPG_D2WACR_MSTPCR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D2WACR_RAHSR0 + (loop * 4U)), (CPG_D2WACR_RAHSR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D2WACR_SRCR0 + (loop * 4U)), (CPG_D2WACR_SRCR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D2WACR_SRSTCLR0 + (loop * 4U)), (CPG_D2WACR_SRSTCLR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D3WACR_MSTPCR0 + (loop * 4U)), (CPG_D3WACR_MSTPCR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D3WACR_RAHSR0 + (loop * 4U)), (CPG_D3WACR_RAHSR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D3WACR_SRCR0 + (loop * 4U)), (CPG_D3WACR_SRCR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D3WACR_SRSTCLR0 + (loop * 4U)), (CPG_D3WACR_SRSTCLR0 + (loop * 4U)), WRITE_ENABLE); + } +} +/* End of function domain_protection_setting(void) */ +#endif/* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/protect/stack_protect.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/protect/stack_protect.c new file mode 100644 index 0000000..21a6493 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/protect/stack_protect.c @@ -0,0 +1,86 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Stack protect function + ******************************************************************************/ + /****************************************************************************** + * @file stack_protect.c + * - Version : 0.01 + * @brief Check for Stack Smashing Attacks. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 31.01.2023 0.01 First Release + *****************************************************************************/ + +#include +#include + +/* Specify fixed canary value as reference implementation. */ +#define CANARY_VAL (0xB9DFF6A0U) + +#define STACK_PROTECT_ENABLE (1U) + +/* Save canary to __stack_chk_guard. */ +extern uintptr_t __stack_chk_guard; +__attribute__((section(".canary"))) uintptr_t __stack_chk_guard; + +/* Prototype */ +extern void __ghs_set_stack_chk_guard(void); +#if (STACK_PROTECT == STACK_PROTECT_ENABLE) +extern void __stack_chk_fail(void); +static inline uintptr_t *__ghs_get_stack_chk_guard_address(void); +#endif + +void __ghs_set_stack_chk_guard(void) +{ +#if (STACK_PROTECT == STACK_PROTECT_ENABLE) + /* Initialize the stack canary before any code that may require a stack canary. */ + /* So don't add valiables larger than 8-bytes to this function. */ + /* Don't call function that uses stack canaries from this function. */ + /* If customize CANARY_VAL to random value, don't allow the function */ + /* to be inlined or this function may require a canary. */ + + *__ghs_get_stack_chk_guard_address() = (uintptr_t)CANARY_VAL; + +#endif +} +/* End of function __ghs_set_stack_chk_guard(void) */ + +#if (STACK_PROTECT == STACK_PROTECT_ENABLE) +static inline uintptr_t *__ghs_get_stack_chk_guard_address(void) +{ + /* Don't modify this function. */ + return &__stack_chk_guard; +} +/* End of function __ghs_get_stack_chk_guard_address(void) */ + +void __stack_chk_fail(void) +{ + ERROR("Stack smashing detected\n"); + panic; +} +/* End of function __stack_chk_fail(void) */ +#endif /* (STACK_PROTECT == STACK_PROTECT_ENABLE) */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/remap/remap.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/remap/remap.c new file mode 100644 index 0000000..337748d --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/remap/remap.c @@ -0,0 +1,286 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : remap driver + ******************************************************************************/ +/****************************************************************************** + * @file remap.c + * - Version : 0.06 + * @brief 1. Setting of SIC REMAP AREA. + * 2. Release of SIC REMAP AREA. + * 3. Calculation of logical address. + * 4. Calculation of physical address. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Modify remap_reg_write function to inline. + * : 06.01.2022 0.03 Static analysis support + * : 23.05.2022 0.04 Supported SICREMAP address for S4 ver1.0 + * S4/V4H differences applied to s_remap_tbl. + * : 15.05.2023 0.05 Add get_cfremap_addr() function to jump + * the secure firmware on CF remap Area. + * : 21.08.2023 0.06 Add support for V4M. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +/* Range of SICREMAP2M register */ +#define REMAP_REG_MAX (16U) + +#define REMAP_2M_BITS (21U) +#define REMAP_2M_SIZE ((uint32_t)1U << REMAP_2M_BITS) +#define REMAP_2M_MASK (REMAP_2M_SIZE - 1U) +#define REMAP_TBL_MAX (sizeof(s_remap_tbl)/sizeof(s_remap_tbl[0])) +#define REMAP_UNUSED (0xFFFFFFFFU) + +typedef struct { + uint32_t number; + uint32_t address; +}st_remap_address_table_t; + +/* Remap management table */ +static st_remap_address_table_t s_remap_tbl[REMAP_REG_MAX] = { + [0] = {REMAP_UNUSED, 0x00000000U}, + [1] = {REMAP_UNUSED, 0x00000000U}, + [2] = {REMAP_UNUSED, 0x00000000U}, + [3] = {REMAP_UNUSED, 0x00000000U}, +#if (RCAR_LSI == RCAR_S4) + [4] = {4, 0xD8E00000}, /* MCU */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + [4] = {REMAP_UNUSED, 0x00000000U}, +#endif + [5] = {5, 0xE7600000U}, /* Region ID */ + [6] = {6, 0xE7200000U}, /* SYS-DMAC0 */ + [7] = {7, 0xE6400000U}, /* HSCIF */ + [8] = {8, 0xEE000000U}, /* MMC */ + [9] = {9, 0xE6E00000U}, /* SCIF */ + [10] = {10, 0xFFC00000U}, /* RT-DMAC0,PFC(MCU) */ + [11] = {11, 0xEE200000U}, /* RPC */ + [12] = {12, 0xE6200000U}, /* ECM,AP-System Core */ + [13] = {13, 0xE6000000U}, /* PFC,GPIO,CPGA,RESET */ + [14] = {14, 0xE6600000U}, /* CC63S,AXMM,QoS,FCPR */ + [15] = {15, 0xEB200000U}, /* RT-SRAM */ +}; + +static inline uint32_t get_sicremap2m_addr(uint32_t num) +{ + return (REMAP_BASE + (num * 0x0004U)); +} +/* End of function get_sicremap2m_addr(uint32_t num) */ + +static inline void remap_reg_write(uint32_t num, uint32_t value) +{ + /* Specific write Procedure for Write-Protected Register. */ + do + { + mem_write32(ICUMX_PROT0PCMD, PROTCMD_START); + mem_write32(get_sicremap2m_addr(num), value); + mem_write32(get_sicremap2m_addr(num), ~value); + mem_write32(get_sicremap2m_addr(num), value); + } while (mem_read32(ICUMX_PROT0PS) == PROTS0ERR); +} +/* End of function remap_reg_write(uint32_t num, uint32_t value) */ + +void remap_register(uint32_t addr, uint32_t *remap_addr) +{ + uint32_t loop; + uint32_t set_addr; + + /* Check unused area in order from the top of + the remap management table. */ + for (loop = 0U; loop < REMAP_TBL_MAX; ++loop) + { + if (REMAP_UNUSED == s_remap_tbl[loop].number) + { + break; + } + } + + /* When necessary area can not be secured */ + if (REMAP_TBL_MAX <= loop) + { + ERROR("There is no space in the logical address area.\n"); + panic; + } + + syncm(); + + /* Set remap area */ + set_addr = addr & ~REMAP_2M_MASK; + + /* Update the table managing the remap space */ + s_remap_tbl[loop].address = set_addr; + s_remap_tbl[loop].number = (uint8_t)loop; + /* Set SICREMAP register */ + remap_reg_write(loop, set_addr); + INFO("s_remap_tbl[%d].number = 0x%x\n",loop,s_remap_tbl[loop].number); + INFO("s_remap_tbl[%d].address = 0x%x\n",loop,s_remap_tbl[loop].address); + + syncm(); + + /* Calculating the logical address of the + address received as an argument */ + *remap_addr = icu_remap_calc(loop); + *remap_addr += addr & REMAP_2M_MASK; +} +/* End of function remap_register(uint32_t addr, uint32_t size, uint32_t *remap_addr) */ + +void remap_unregister(uint32_t remap_addr) +{ + uint32_t loop; + + /* Is the remap space where the address of the argument is used? */ + for (loop = 0U; loop < REMAP_TBL_MAX; ++loop) + { + INFO("s_remap_tbl[%d].number = 0x%x\n",loop,s_remap_tbl[loop].number); + if ((REMAP_UNUSED != s_remap_tbl[loop].number) + && ((icu_remap_calc(loop) <= remap_addr) + && (remap_addr < icu_remap_calc(loop + 1U)))) + { + break; + } + } + + /* When an area to release can not be found */ + if (REMAP_TBL_MAX <= loop) + { + ERROR("Not registered in the logical address.\n" + "remap address = 0x%x\n",remap_addr); + panic; + } + syncm(); + + /* release remap area */ + /* Update the table managing the remap space */ + s_remap_tbl[loop].address = 0U; + s_remap_tbl[loop].number = REMAP_UNUSED; + /* Release SICREMAP register */ + remap_reg_write(loop, icu_remap_calc(loop)); + + syncm(); +} +/* End of function remap_unregister(uint32_t remap_addr) */ + +uint32_t remap_get_phys_addr(uint32_t remap_addr) +{ + uint32_t phys_addr; + uint32_t reg; + + /* It checks whether the argument is within the range + of the logical address. */ + if ((ICU_REMAP0 > remap_addr) + || (icu_remap_calc(REMAP_REG_MAX) <= remap_addr)) + { + ERROR("Address convert error.\n" + "source address = 0x%x\n",remap_addr); + panic; + } + + /* Calculate the physical address of the argument */ + phys_addr = remap_addr - ICU_REMAP0; + phys_addr >>= REMAP_2M_BITS; + reg = get_sicremap2m_addr(phys_addr); + reg = mem_read32(reg); + phys_addr = reg + (remap_addr & REMAP_2M_MASK); + + return phys_addr; +} +/* End of function remap_get_phys_addr(uint32_t remap_addr) */ + +uint32_t remap_get_remap_addr(uint32_t phys_addr) +{ + uint32_t remap_addr; + uint32_t reg; + uint32_t loop; + + /* It checks whether the argument is within the range + of the physical address registered in SICREMAP. */ + for (loop = 0U; loop < REMAP_REG_MAX; loop++) + { + reg = mem_read32(get_sicremap2m_addr(loop)); + if ((reg <= phys_addr) + && (phys_addr <= (reg + REMAP_2M_MASK))) + { + break; + } + } + + /* argument value is not used in the remap area. */ + if (REMAP_REG_MAX <= loop) + { + ERROR("Address convert error.\n" + "source address = 0x%x\n",phys_addr); + panic; + } + + /* Calculate the logical address of the argument */ + remap_addr = icu_remap_calc(loop); + remap_addr += phys_addr - reg; + + return remap_addr; +} +/* End of function remap_get_remap_addr(uint32_t phys_addr) */ + +uint32_t get_cfremap_addr(uint32_t fetch_addr) +{ + uint32_t cf_remap_addr = 0x0U; + uint32_t cf_current_base = mem_read32(ICUMX_CFREMAP); + + /* Get current setting of "physical address for cf remap base", + and calculate cf remap address of target fetch */ + cf_remap_addr = fetch_addr - cf_current_base; + + /* Check whether the calculated address is outside of Code Fetch area */ + if ((CFREMAP_AREA_SIZE <= cf_remap_addr) || (fetch_addr < cf_current_base)) + { + ERROR("Target fetch address is invalid: 0x%08x\n", fetch_addr); + panic; + } + + return cf_remap_addr; +} + +void set_sicremap_s4v10(void) +{ +#if (RCAR_LSI == RCAR_S4) + /* Change the setting of SICREMAP for S4 Ver1.0 to be the setting of SICREMAP for S4 Ver1.1. */ + remap_reg_write(ICU_REMAP_NUM_RGID, ICU_REMAP_RGID); /* SIC REMAP5:Region ID */ + remap_reg_write(ICU_REMAP_NUM_MCU , ICU_REMAP_MCU); /* SIC REMAP4:MCU */ +#endif +} +/* End of function set_sicremap_s4v10(void) */ + +void set_sicremap_fcpr(void) +{ + remap_reg_write(ICU_REMAP_NUM_FCPR, ICU_REMAP_FCPR); /* SIC REMAP14:FCPR */ +} +/* End of function set_sicremap_fcpr(void) */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/rom_api/rom_api.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/rom_api/rom_api.c new file mode 100644 index 0000000..2957a6e --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/rom_api/rom_api.c @@ -0,0 +1,381 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : boot ROM API + ******************************************************************************/ +/****************************************************************************** + * @file rom_api.c + * - Version : 0.13 + * @brief 1.Call ROM_SecureBootAPI. + * 2.Call ROM_GetLcsAPI. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : (30.11.2021 0.02) Modify argument of ROM_GetLcs. + * : 23.05.2022 0.03 Supported Secure boot for ROM API. + * : 05.08.2022 0.04 Add sw_version_check function and macros. + * Add sw_version_check function call to + * rom_secureboot function. + * : 30.09.2022 0.05 Add auth_min_ver_tbl function. + * : 09.12.2022 0.06 Remove argument 'is_verify' used in + * auth_min_ver_tbl function. + * : 14.02.2023 0.07 Add Hash save process to rom_secureboot. + * : 14.04.2023 0.08 Add certificate authentication functions. + * : 21.08.2023 0.09 Add support for V4M. + * : 11.01.2024 0.10 Add process that change writing privilege + * to System RAM by ICUMX. + * : 08.02.2024 0.11 Update icu_remove_write_access calling + * condition to always calling. + * : 05.12.2024 0.12 Remove icu_remove_write_access function. + * : 26.05.2025 0.13 Add verification support for the OP-TEE + * content cert. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* For software version check */ +#define TBL_VERSION_CHECK_DISABLE (0U) +#define TFMV_MIN_VER_TBL_TOP (0xFDE35000U) /* remapped address */ +#define NTFMV_MIN_VER_TBL_TOP (0xFDE35800U) /* remapped address */ +#define NTFMV_LD_ID_OFST (7U) +#define SW_MIN_VER_TBL_UNIT (0x10U) +#define TBL_VER_OFST (4U) +#define TBL_IMG_OFST (8U) + +/* Hash size definition */ +#define SECURE_BOOT_COMPARE_HASH_SIZE_BYTE (64U) /* SHA-256 * 2 */ +/* Definitions for get_hash_save_addr() */ +#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) +/* cnt=0: TFMV Software minimum version table */ +/* cnt=1: NTFMV Software minimum version table */ +/* cnt=2: CR52 2nd IPL */ +#define CR52_IPL_HASH_SAVE_CNT (0x2U) +/* cnt=3: Secure FW */ +#define SECURE_FW_HASH_SAVE_CNT (0x3U) +#else +#define CR52_IPL_HASH_SAVE_CNT (0x0U) +#define SECURE_FW_HASH_SAVE_CNT (0x1U) +#endif +#define CR52_IPL_HASH_SAVE_ADDR (0xE635FF40U) /* Physical address */ +#define SECURE_FW_HASH_SAVE_ADDR (0xE635FFC0U) /* Physical address */ +/* For TFMV/NTFMV Software minimum version table */ +#define OTHERS_HASH_SAVE_ADDR (0xE635FC00U) /* Physical address */ + +static uint32_t call_ROM_SecureBootVerify(uint32_t *pKeyCert, uint32_t *pContentCert); +static uint32_t call_ROM_SecureBootCompare(uint32_t *pContentCert, uint32_t *hash, uint32_t hash_size); +static uint32_t call_ROM_SecureBootDecrypt(uint32_t *pContentCert); +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +static uint32_t get_hash_save_addr(void); +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +extern uint32_t is_verify; + +void rom_secureboot(LOAD_INFO* li) +{ + uint32_t *keycert = (uint32_t*)li->key_cert_addr; + uint32_t *contentcert = (uint32_t*)li->cnt_cert_addr; +#if (RCAR_LSI == RCAR_S4) + uint32_t hash[16]; /* hash space is 64byte */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + uint32_t *hash; /* SystemRAM logical address */ +#endif /* (RCAR_LSI == RCAR_S4) */ + uint32_t ret; + + /* If boot mode is Secure BOOT, the ROM API is used to authenticate the image. */ + if (NORMAL_BOOT != is_verify) + { + /* Content cert certification */ + ret = call_ROM_SecureBootVerify(keycert, contentcert); + if (ROMAPI_OK != ret) + { + ERROR("%s Certificate Verification Failed!!!(0x%x)\n", li->name, ret); + panic; + } + + /* Decryption image */ + ret = call_ROM_SecureBootDecrypt(contentcert); + if ((ROMAPI_OK != ret) && (ROM_ERR_IMG_VERIFIER_NO_ENCRYPT_IMG != ret)) + { + ERROR("%s Decryption Failed!!!(0x%x)\n", li->name, ret); + panic; + } + } /* if (NORMAL_BOOT != is_verify) */ + + /* + * System RAM is divided two regions that Cx 2nd IPL and others by RAM protection. + * After loading and decrypting Cx 2nd IPL, writing privilege to Cx 2nd IPL region + * from RGID0(ICUMX) to be disabled and then comparing Hash. + * This implementation is according to operation in SAN (Application Domain Safety Application Note) + * chapter 6.23.5. + */ +/* Remove the following comment out if user want to enable protection of System Ram. */ +/* if(CA_PROGRAM_ID == (li->image_id)) */ +/* { */ +/* icu_remove_write_access(); */ +/* } */ + + if (NORMAL_BOOT != is_verify) + { + /* Hash save SystemRAM logical address calculation (V4H only) */ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + hash = (uint32_t *)get_hash_save_addr(); +#endif + /* Image certification */ + ret = call_ROM_SecureBootCompare(contentcert, hash, SECURE_BOOT_COMPARE_HASH_SIZE_BYTE); + if (ROMAPI_OK != ret) + { + ERROR("%s Image Verification Failed!!!(0x%x)\n", li->name, ret); + panic; + } + + /* Software version check */ + sw_version_check(li); + } /* if (NORMAL_BOOT != is_verify) */ +} +/* End of function rom_secureboot(LOAD_INFO* li) */ + +static uint32_t call_ROM_SecureBootVerify(uint32_t *pKeyCert, uint32_t *pContentCert) +{ + /* Secure Boot API address */ + static const uintptr_t s_rom_secureboot_verify_addr = ROM_SECUREBOOT_VERIFY; + ROM_SECUREBOOT_VERIFY_API func; + uint32_t ret; + + func = (ROM_SECUREBOOT_VERIFY_API)s_rom_secureboot_verify_addr; + + ret = func(pKeyCert, pContentCert); + return ret; +} +/* End of function call_ROM_SecureBootVerify(uint32_t *pKeyCert, uint32_t *pContentCert) */ + +static uint32_t call_ROM_SecureBootCompare(uint32_t *pContentCert, uint32_t *hash, uint32_t hash_size) +{ + /* Secure Boot API address */ + static const uintptr_t s_rom_secureboot_compare_addr = ROM_SECUREBOOT_COMPARE; + ROM_SECUREBOOT_COMPARE_API func; + uint32_t ret; + + func = (ROM_SECUREBOOT_COMPARE_API)s_rom_secureboot_compare_addr; + + ret = func(pContentCert, hash, hash_size); + return ret; +} +/* End of function call_ROM_SecureBootCompare(uint32_t *pContentCert, uint32_t *hash, uint32_t hash_size) */ + +static uint32_t call_ROM_SecureBootDecrypt(uint32_t *pContentCert) +{ + /* Secure Boot API address */ + static const uintptr_t s_rom_secureboot_decrypt_addr = ROM_SECUREBOOT_DECRYPT; + ROM_SECUREBOOT_DECRYPT_API func; + uint32_t ret; + + func = (ROM_SECUREBOOT_DECRYPT_API)s_rom_secureboot_decrypt_addr; + + ret = func(pContentCert); + return ret; +} +/* End of function call_ROM_SecureBootDecrypt(uint32_t *pContentCert) */ + +uint32_t call_ROM_GetLcs(uint32_t *pLcs, uint32_t lcs_size) +{ + /* Get LCS stete API address */ + static const uintptr_t s_rom_getlcs_addr = ROM_GETLCS; + ROM_GETLCS_API func; + uint32_t ret; + + func = (ROM_GETLCS_API)s_rom_getlcs_addr; + + ret = func(pLcs, lcs_size); + return ret; +} +/* End of function call_ROM_GetLcs(uint32_t *pLcs, uint32_t lcs_size) */ + +void sw_version_check(const LOAD_INFO* li) +{ +#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) + uint32_t ver_tbl_base; + uint32_t ver_tbl_addr; + uint32_t ver_tbl_version; + uint32_t ver_tbl_ofst; + uint32_t img_version; + uint32_t id_adj = 0U; + uint32_t val; + uint32_t rmp_addr; + uint32_t load_id; + + load_id = get_load_info_id(li); + + if (load_id < TFMV_MIN_VER_TBL_ID) + { + /* If image is other than Software minimum version table */ + if(li->key_cert_addr == TFMV_KEY_CERT_ADDR) + { + /* Refer to TFMV Software minimum version table */ + ver_tbl_base = TFMV_MIN_VER_TBL_TOP; /* 0xFDE35000 */ + } + else + { + /* Refer to NTFMV Software minimum version table */ + ver_tbl_base = NTFMV_MIN_VER_TBL_TOP; /* 0xFDE35800 */ + id_adj = NTFMV_LD_ID_OFST; + } + + /* Calculate Software minimum version address for Load ID */ + ver_tbl_addr = ver_tbl_base + (SW_MIN_VER_TBL_UNIT * (load_id - id_adj)); + + val = mem_read32(ver_tbl_addr); + if(val != TBL_VERSION_CHECK_DISABLE) + { + /* If a flag in Software minimum version is enable */ + ver_tbl_version = mem_read32(ver_tbl_addr + TBL_VER_OFST); + ver_tbl_ofst = mem_read32(ver_tbl_addr + TBL_IMG_OFST); + + /* Read image version in Load ID's image */ + remap_register(li->boot_addr + ver_tbl_ofst, &rmp_addr); + img_version = mem_read32(rmp_addr); + remap_unregister(rmp_addr); + + if(img_version < ver_tbl_version) + { + ERROR("%s Software version check result is failed.\n", li->name); + panic; + } + } + } +#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */ +} +/* End of function sw_version_check(const LOAD_INFO* li) */ + +void auth_min_ver_tbl(LOAD_INFO* li) +{ +#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) + rom_secureboot(&li[TFMV_MIN_VER_TBL_ID]); + rom_secureboot(&li[NTFMV_MIN_VER_TBL_ID]); +#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */ +} +/* End of function auth_min_ver_tbl(LOAD_INFO* li) */ + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +static uint32_t get_hash_save_addr(void) +{ + uint32_t hash_addr; + static uint32_t cnt = 0U; + + if(cnt == CR52_IPL_HASH_SAVE_CNT) + { + /* When loading image is Cx 2nd IPL. */ + hash_addr = remap_get_remap_addr(CR52_IPL_HASH_SAVE_ADDR); + } + else if(cnt == SECURE_FW_HASH_SAVE_CNT) + { + /* When loading image is Secure FW. */ + hash_addr = remap_get_remap_addr(SECURE_FW_HASH_SAVE_ADDR); + } + else + { + /* When loading image is TFMV/NTFMV Software minimum version table. */ + hash_addr = remap_get_remap_addr(OTHERS_HASH_SAVE_ADDR); + } + /* Count how many times this function called. */ + cnt++; + + if(cnt > SECURE_FW_HASH_SAVE_CNT + 1U) + { + NOTICE("get_hash_save_addr: Unexpected cnt value.\n"); + } + + return hash_addr; +} +/* End of function get_hash_save_addr(void) */ + +void preload_verify_cntcert(const LOAD_INFO* li) +{ + if (NORMAL_BOOT != is_verify) + { + /* Set error code value as initial value */ + int32_t ret = -1; + + /* verify the content cert of RTOS */ + ret = call_ROM_SecureBootVerify((uint32_t *)li[RTOS_ID].key_cert_addr, (uint32_t *)li[RTOS_ID].cnt_cert_addr); + if (ROMAPI_OK != ret) + { + ERROR("%s Certificate Verification Failed!!!(0x%x)\n", li[RTOS_ID].name, ret); + panic; + } + + /* verify the content cert of Secure FW */ + ret = call_ROM_SecureBootVerify((uint32_t *)li[SECURE_FW_ID].key_cert_addr, (uint32_t *)li[SECURE_FW_ID].cnt_cert_addr); + if (ROMAPI_OK != ret) + { + ERROR("%s Certificate Verification Failed!!!(0x%x)\n", li[SECURE_FW_ID].name, ret); + panic; + } + + /* verify the content cert of CxIPL */ + ret = call_ROM_SecureBootVerify((uint32_t *)li[CA_PROGRAM_ID].key_cert_addr, (uint32_t *)li[CA_PROGRAM_ID].cnt_cert_addr); + if (ROMAPI_OK != ret) + { + ERROR("%s Certificate Verification Failed!!!(0x%x)\n", li[CA_PROGRAM_ID].name, ret); + panic; + } + + /* verify the content cert of Secure Monitor */ + ret = call_ROM_SecureBootVerify((uint32_t *)li[CA_OPTIONAL_ID].key_cert_addr, (uint32_t *)li[CA_OPTIONAL_ID].cnt_cert_addr); + if (ROMAPI_OK != ret) + { + ERROR("%s Certificate Verification Failed!!!(0x%x)\n", li[CA_OPTIONAL_ID].name, ret); + panic; + } + + /* verity the content cert of U-boot */ + ret = call_ROM_SecureBootVerify((uint32_t *)li[CA_OPTIONAL_ID + 1U].key_cert_addr, (uint32_t *)li[CA_OPTIONAL_ID + 1U].cnt_cert_addr); + if (ROMAPI_OK != ret) + { + ERROR("%s Certificate Verification Failed!!!(0x%x)\n", li[CA_OPTIONAL_ID + 1U].name, ret); + panic; + } + +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) + /* verity the content cert of OP-TEE */ + ret = call_ROM_SecureBootVerify((uint32_t *)li[CA_OPTIONAL_ID + 2U].key_cert_addr, (uint32_t *)li[CA_OPTIONAL_ID + 2U].cnt_cert_addr); + if (ROMAPI_OK != ret) + { + ERROR("%s Certificate Verification Failed!!!(0x%x)\n", li[CA_OPTIONAL_ID + 2U].name, ret); + panic; + } +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ + } +} + +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/t.diff b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/t.diff new file mode 100644 index 0000000..aa210dc --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/t.diff @@ -0,0 +1,468 @@ +diff --git a/Gen4_ICUMX_Loader/dos.mk b/Gen4_ICUMX_Loader/dos.mk +index 9ec4e05..ca8e2a5 100644 +--- a/Gen4_ICUMX_Loader/dos.mk ++++ b/Gen4_ICUMX_Loader/dos.mk +@@ -86,12 +86,6 @@ else + endif + $(eval $(call add_define,RCAR_LSI)) + +-#/* PRK3 board revision ("0" for EVB, other for PRK3) *********************** +-ifeq ("$(PRK3)", "") +-PRK3 = 0 +-endif +-$(eval $(call add_define,PRK3)) +- + # timing measurement + ifeq ("$(MEASURE_TIME)", "") + MEASURE_TIME = 0 +@@ -363,6 +357,7 @@ OBJ_FILE += image_load/image_load_flash.o \ + ip/dma/dma.o \ + ip/rpc/rpc.o \ + ip/rpc/qspi_xdr_mode.o \ ++ ip/rpc/dma2.o \ + ip/rpc/rpcqspidrv.o \ + ip/rpc/spiflash2drv.o \ + ip/mfis/mfis.o +diff --git a/Gen4_ICUMX_Loader/env.ini b/Gen4_ICUMX_Loader/env.ini +index 9032153..dd0a92b 100644 +--- a/Gen4_ICUMX_Loader/env.ini ++++ b/Gen4_ICUMX_Loader/env.ini +@@ -4,5 +4,4 @@ OPTEE_LOAD_ENABLE=1 \ + BL2_LOAD_ENABLE=1 \ + QNX_OS_LOAD_ENABLE=1 \ + STACK_PROTECT=1 \ +-PRK3=4 \ + " +diff --git a/Gen4_ICUMX_Loader/include/rpcqspidrv.h b/Gen4_ICUMX_Loader/include/rpcqspidrv.h +index a306dce..769fda0 100644 +--- a/Gen4_ICUMX_Loader/include/rpcqspidrv.h ++++ b/Gen4_ICUMX_Loader/include/rpcqspidrv.h +@@ -41,7 +41,7 @@ + #define RPCQSPIDRV_H__ + + #include +-// #include "reg_rcar.h" ++#include + + #define SPI_IOADDRESS_TOP 0x08000000 /* RPC memory space 0x08000000-0x0BFFFFFF = 64MBytes */ + #define RPC_CLK_40M 0x01 +@@ -51,11 +51,7 @@ + #define DEVICE_ID_MASK (0x00FFFFFFU) + + #define RPC_WRITE_BUF_SIZE (0x100U) /* 256byte:RPC Write Buffer size */ +-#if (PRK3 > 0) + #define FLASH_SECTOR_SIZE (0x00010000U) /* Flash 1sector is 64KiB */ +-#else +-#define FLASH_SECTOR_SIZE (0x00040000U) /* Flash 1sector is 256KiB */ +-#endif + #define FLASH_SECTOR_MASK ((~(FLASH_SECTOR_SIZE-1)) & 0xFFFFFFFFU) + + #define DRCMR_SMCMR_CMD_SHIFT (16U) +diff --git a/Gen4_ICUMX_Loader/ip/rpc/rpc.c b/Gen4_ICUMX_Loader/ip/rpc/rpc.c +index 9519c2c..68310af 100644 +--- a/Gen4_ICUMX_Loader/ip/rpc/rpc.c ++++ b/Gen4_ICUMX_Loader/ip/rpc/rpc.c +@@ -47,18 +47,17 @@ + + #include + #include +-#include +-#include ++#include + #include + #include +-#include + #include + #include +-#include +-#include +-#include +-#include ++#include + #include ++#include ++#include ++#include ++#include + + #define RST_MODEMR0_BOOTMODE (0xFU << 1U) + #define BOOTMODE_QSPI_SINGLE_40MHZ (0x4U) +@@ -145,7 +144,6 @@ static const uint32_t dev_id_index[VENDOR_NUM] = + }; + + const st_qspi_cmd_tbl_t* gp_qspi_cmd_tbl; +-uint8_t prk3_rev = 3; + + static void rpc_save_hw_init_val(void); + static uint32_t init_qspi_cmd(uint32_t device_id); +@@ -190,7 +188,6 @@ void qspi_flash_rw_init(void) + ERROR("QSPI Flash command initialization error!!\n"); + panic; + } +- init_rpc_qspi_flash_4fastread_ext_mode(); + + #if (QSPI_DDR_MODE==1) + /* Initialize for QSPI DDR transfer mode */ +@@ -253,6 +250,7 @@ static void rpc_save_hw_init_val(void) + } + } + ++uint8_t prk3_rev = 3; + static uint32_t init_qspi_cmd(uint32_t device_id) + { + uint32_t i = 0U; +diff --git a/Gen4_ICUMX_Loader/ip/rpc/rpcqspidrv.c b/Gen4_ICUMX_Loader/ip/rpc/rpcqspidrv.c +index f4343ce..d4ba398 100644 +--- a/Gen4_ICUMX_Loader/ip/rpc/rpcqspidrv.c ++++ b/Gen4_ICUMX_Loader/ip/rpc/rpcqspidrv.c +@@ -44,20 +44,19 @@ + * : 09.11.2022 0.07 License notation change. + *****************************************************************************/ + +-// #include "common.h" + #include + #include +-#include "rpcqspidrv.h" +-// #include "reg_rcar.h" +-#include ++#include ++#include ++#include + #include +-#include "bit.h" +-#include "micro_wait.h" +-#include "remap.h" +-#include "mem_io.h" +-#include "dma.h" +-// #include "qspi_cmd.h" ++#include ++#include + #include ++#include ++#include ++ ++#include "dma2.h" + + static uint32_t read_register_qspi_flash(uint32_t cmd, uint32_t *readData); + +@@ -371,10 +370,10 @@ void write_data_4pp_with_buf_qspi_flash(uint32_t addr, uint32_t source_addr) + + for(i = 0; i < RPC_WRITE_BUF_SIZE; i = i + TRANS_SIZE_64BYTE) + { +- // dma_start_xbyte(RPC_WRBUF_PHYS+i, source_addr+i, TRANS_SIZE_64BYTE, TRANS_UNIT_64BYTES); +- dma_trans_start(RPC_WRBUF_PHYS+i, source_addr+i, TRANS_SIZE_64BYTE); +- // dma_end(); +- dma_trans_end_check(); ++ dma2_start_xbyte(RPC_WRBUF_PHYS+i, source_addr+i, TRANS_SIZE_64BYTE, TRANS_UNIT_64BYTES); ++ dma2_end(); ++ // dma_trans_start(RPC_WRBUF_PHYS+i, source_addr+i, TRANS_SIZE_64BYTE); ++ // dma_trans_end_check(); + } + + reg = mem_read32(RPC_CMNCR); +@@ -467,7 +466,6 @@ void write_data_4pp_with_buf_qspi_flash(uint32_t addr, uint32_t source_addr) + } + /* End of function write_data_4pp_with_buf_qspi_flash */ + +-#if (PRK3 > 0) + /* OnBoard QspiFlash(MT25QU01GB) */ + uint32_t read_wip_status_register(uint32_t *readData) /* for QSPIx1ch */ + { +@@ -554,216 +552,6 @@ void write_status_register(uint16_t stat_conf) + + wait_rpc_tx_end(); + } +-#else /* PRK3 == 0 */ +-/* OnBoard QspiFlash(S25FS128S) */ +-/* 65h Read Any Register command (RADR 65h) */ +-void read_any_register_qspi_flash(uint32_t addr, unsigned char *readData) /* Add24bit,Data8bit */ +-{ +- uint32_t reg; +- +- reg = mem_read32(RPC_PHYCNT); +- reg |= (RPC_PHYCNT_STRTIM3 +- | RPC_PHYCNT_STRTIM2 +- | RPC_PHYCNT_STRTIM1 +- | RPC_PHYCNT_STRTIM0); +- reg &= ~(RPC_PHYCNT_HS +- | RPC_PHYCNT_WBUF2 +- | RPC_PHYCNT_WBUF +- | RPC_PHYCNT_PHYMEM_HYP); +- mem_write32(RPC_PHYCNT, reg); +- reg |= RPC_PHYCNT_CAL; +- mem_write32(RPC_PHYCNT, reg); +- /* bit31 CAL = 1 : PHY calibration */ +- /* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */ +- +- reg = mem_read32(RPC_CMNCR); +- reg &= ~(CMNCR_BSZ_MASK); +- reg |= (CMNCR_MD_MANUAL +- | CMNCR_MOIIO3_HIZ +- | CMNCR_MOIIO2_HIZ +- | CMNCR_MOIIO1_HIZ +- | CMNCR_MOIIO0_HIZ +- | CMNCR_IO0FV_HIZ); +- mem_write32(RPC_CMNCR, reg); +- /* bit31 MD = 1 : Manual mode */ +- /* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */ +- +- reg = mem_read32(RPC_SMCMR); +- reg &= ~(SMCMR_CMD_MASK +- | SMCMR_OCMD_MASK); +- reg |= ((gp_qspi_cmd_tbl -> read_any_register) << DRCMR_SMCMR_CMD_SHIFT); +- mem_write32(RPC_SMCMR, reg); +- /* bit23-16 CMD[7:0] = 0x65 : Read Any Register command (RADR 65h) */ +- +- mem_write32(RPC_SMADR, addr); +- +- reg = mem_read32(RPC_SMDMCR); +- reg &= ~(SMDMCR_DMCYC_MASK); +- reg |= SMDMCR_DMCYC_8; +- mem_write32(RPC_SMDMCR, reg); +- /* bit2-0 DMCYC[2:0] = 111 : 8 cycle dummy wait */ +- +- reg = mem_read32(RPC_SMDRENR); +- reg &= ~(SMDRENR_HYPE_MASK +- | SMDRENR_ADDRE +- | SMDRENR_OPDRE +- | SMDRENR_SPIDRE); +- mem_write32(RPC_SMDRENR, reg); +- /* bit8 ADDRE = 0 : Address SDR transfer */ +- /* bit0 SPIDRE = 0 : DATA SDR transfer */ +- +- reg = mem_read32(RPC_SMENR); +- reg &= ~(SMENR_CDB_MASK +- | SMENR_OCDB_MASK +- | SMENR_ADB_MASK +- | SMENR_OPDB_MASK +- | SMENR_SPIDB_MASK +- | SMENR_OCDE_EN +- | SMENR_ADE_MASK +- | SMENR_OPDE_MASK +- | SMENR_SPIDE_MASK); +- reg |= (SMENR_DME_EN +- | SMENR_CDE_EN +- | SMENR_ADE_SERIAL_23 +- | SMENR_SPIDE_SPI_8); +- mem_write32(RPC_SMENR, reg); +- /* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */ +- /* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */ +- /* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */ +- /* bit15 DME = 1 : dummy cycle enable */ +- /* bit14 CDE = 1 : Command enable */ +- /* bit11-8 ADE[3:0] = 0111 : ADR[23:0] output (24 Bit Address) */ +- /* bit3-0 SPIDE[3:0] = 1000 : 8bit transfer */ +- +- reg = mem_read32(RPC_SMCR); +- reg &= ~(SMCR_SSLKP +- | SMCR_SPIWE); +- reg |= (SMCR_SPIRE +- | SMCR_SPIE); +- mem_write32(RPC_SMCR, reg); +- /* bit2 SPIRE = 1 : Data read enable */ +- /* bit1 SPIWE = 0 : Data write disable */ +- /* bit0 SPIE = 1 : SPI transfer start */ +- +- wait_rpc_tx_end(); +- +- *readData = mem_read8(RPC_SMRDR0); /* read data[7:0] */ +-} +-/* End of function read_any_register_qspi_flash */ +- +-/* OnBoard QspiFlash(S25FS128S) */ +-/* 71h Write Any Register command (WRAR 71h) */ +-void write_any_register_qspi_flash(uint32_t addr, unsigned char writeData) /* Add24bit,Data8bit */ +-{ +- uint32_t reg; +- +- reg = mem_read32(RPC_PHYCNT); +- reg |= (RPC_PHYCNT_CAL +- | RPC_PHYCNT_STRTIM3 +- | RPC_PHYCNT_STRTIM2 +- | RPC_PHYCNT_STRTIM1 +- | RPC_PHYCNT_STRTIM0); +- reg &= ~(RPC_PHYCNT_HS +- | RPC_PHYCNT_WBUF2 +- | RPC_PHYCNT_WBUF +- | RPC_PHYCNT_PHYMEM_HYP); +- mem_write32(RPC_PHYCNT, reg); +- /* bit31 CAL = 1 : PHY calibration */ +- /* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */ +- +- reg = mem_read32(RPC_CMNCR); +- reg &= ~(CMNCR_BSZ_MASK); +- reg |= (CMNCR_MD_MANUAL +- | CMNCR_MOIIO3_HIZ +- | CMNCR_MOIIO2_HIZ +- | CMNCR_MOIIO1_HIZ +- | CMNCR_MOIIO0_HIZ +- | CMNCR_IO0FV_HIZ); +- mem_write32(RPC_CMNCR, reg); +- /* bit31 MD = 1 : Manual mode */ +- /* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */ +- +- reg = mem_read32(RPC_SMCMR); +- reg &= ~(SMCMR_CMD_MASK +- | SMCMR_OCMD_MASK); +- reg |= ((gp_qspi_cmd_tbl -> write_any_register) << DRCMR_SMCMR_CMD_SHIFT); +- mem_write32(RPC_SMCMR, reg); +- /* bit23-16 CMD[7:0] = 0x71 : Write Any Register Command (WRAR) */ +- +- mem_write32(RPC_SMADR, addr); +- +- reg = mem_read32(RPC_SMDRENR); +- reg &= ~(SMDRENR_HYPE_MASK +- | SMDRENR_ADDRE +- | SMDRENR_OPDRE +- | SMDRENR_SPIDRE); +- mem_write32(RPC_SMDRENR, reg); +- /* bit8 ADDRE = 0 : Address SDR transfer */ +- /* bit0 SPIDRE = 0 : DATA SDR transfer */ +- +- reg = mem_read32(RPC_SMENR); +- reg &= ~(SMENR_CDB_MASK +- | SMENR_OCDB_MASK +- | SMENR_ADB_MASK +- | SMENR_OPDB_MASK +- | SMENR_SPIDB_MASK +- | SMENR_DME_EN +- | SMENR_OCDE_EN +- | SMENR_ADE_MASK +- | SMENR_OPDE_MASK +- | SMENR_SPIDE_MASK); +- reg |= (SMENR_CDE_EN +- | SMENR_ADE_SERIAL_23 +- | SMENR_SPIDE_SPI_8); +- mem_write32(RPC_SMENR, reg); +- /* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */ +- /* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */ +- /* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */ +- /* bit15 DME = 0 : No dummy cycle */ +- /* bit14 CDE = 1 : Command enable */ +- /* bit11-8 ADE[3:0] = 0111 : ADR[24:0] is output */ +- /* bit3-0 SPIDE[3:0] = 1000 : 8bit transfer */ +- +- mem_write8(RPC_SMWDR0, writeData); +- +- reg = mem_read32(RPC_SMCR); +- reg &= ~(SMCR_SSLKP +- | SMCR_SPIRE); +- reg |= (SMCR_SPIWE +- | SMCR_SPIE); +- mem_write32(RPC_SMCR, reg); +- /* bit2 SPIRE = 0 : Data read disable */ +- /* bit1 SPIWE = 1 : Data write disable */ +- /* bit0 SPIE = 1 : SPI transfer start */ +- +- wait_rpc_tx_end(); +- +- reg = mem_read32(RPC_PHYCNT); +- reg |= (RPC_PHYCNT_STRTIM3 +- | RPC_PHYCNT_STRTIM2 +- | RPC_PHYCNT_STRTIM1 +- | RPC_PHYCNT_STRTIM0 +- | RPC_PHYCNT_WBUF2); +- reg &= ~(RPC_PHYCNT_HS +- | RPC_PHYCNT_WBUF +- | RPC_PHYCNT_PHYMEM_HYP); +- mem_write32(RPC_PHYCNT, reg); +- /* bit31 CAL = 0 : No PHY calibration */ +- /* bit2 WBUF = 0 : Write Buffer Disable */ +- /* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */ +- +- reg = mem_read32(RPC_DRCR); +- reg |= (DRCR_SSLN +- | DRCR_RBURST_32UNITS +- | DRCR_RCF +- | DRCR_RBE_BURST +- | DRCR_SSLE); +- mem_write32(RPC_DRCR, reg); +- /* bit9 RCF = 1 : Read Cache Clear */ +- +-} +-/* End of function write_any_register_qspi_flash */ +-#endif /* PRK3 > 0 */ + + void set_rpc_clock_mode(uint32_t mode) + { +@@ -794,6 +582,7 @@ void wait_rpc_tx_end(void) + + while(1) + { ++ wdt_restart(); + dataL = mem_read32(RPC_CMNSR); + if(dataL & BIT0) break; + /* Wait for TEND = 1 */ +diff --git a/Gen4_ICUMX_Loader/ip/rpc/spiflash2drv.c b/Gen4_ICUMX_Loader/ip/rpc/spiflash2drv.c +index 30b1a50..31359fc 100644 +--- a/Gen4_ICUMX_Loader/ip/rpc/spiflash2drv.c ++++ b/Gen4_ICUMX_Loader/ip/rpc/spiflash2drv.c +@@ -39,18 +39,14 @@ + * : 09.11.2022 0.04 License notation change. + *****************************************************************************/ + +-// #include "common.h" + #include + #include +-#include +-#include "bit.h" +-#include "spiflash2drv.h" +-#include "rpcqspidrv.h" +-// #include "dgtable.h" +-// #include "dgflash.h" +-// #include "qspi_cmd.h" ++#include ++#include + #include +-#include ++#include ++ ++#include "dma2.h" + + #define QSPI_PARAM_SEC_SIZE (0x1000U) + #define QSPI_PARAM_SEC_MASK (0xFFFFF000U) +@@ -63,8 +59,11 @@ void fast_rd_qspi_flash(uint32_t sourceSpiAdd, uint32_t destinationAdd, uint32_t + + sourceAdd = SPI_IOADDRESS_TOP + sourceSpiAdd; + +- dma_trans_start(destinationAdd, sourceAdd, byteCount); +- dma_trans_end_check(); ++ // dma_trans_start(destinationAdd, sourceAdd, byteCount); ++ // dma_trans_end_check(); ++ // dma2_init(); ++ dma2_start(destinationAdd, sourceAdd, byteCount, DMA_MODE_SRC_INC); ++ dma2_end(); + } + /* End of function fast_rd_qspi_flash */ + +@@ -138,11 +137,7 @@ void page_program_with_buf_qspi_flash_s25s512s(uint32_t addr, uint32_t source_ad + /* Add */ + while(1) + { +-#if (PRK3 > 0) + read_wip_status_register(&status); +-#else +- read_status_qspi_flash(&status); +-#endif + if( !(status & BIT0) ) + { + break; +@@ -197,9 +192,7 @@ void sector_erase_qspi_flash(uint32_t EraseStatAdd,uint32_t EraseEndAdd) + for(sectorAd = SectorStatTopAdd; sectorAd <= SectorEndTopAdd; sectorAd += FLASH_SECTOR_SIZE) + { + sector_erase_NNNkb_qspi_flash_s25s512s(sectorAd); +- NOTICE("."); + } +- NOTICE("Erase Completed\n"); + } + /* End of function sector_erase_qspi_flash_s25s512s */ + +@@ -215,8 +208,6 @@ void parameter_sector_erase_qspi_flash(uint32_t EraseStatAdd,uint32_t EraseEndAd + for(sectorAd = SectorStatTopAdd; sectorAd <= SectorEndTopAdd; sectorAd += QSPI_PARAM_SEC_SIZE) + { + parameter_sector_erase_4kb_qspi_flash_s25s512s(sectorAd); +- NOTICE("."); + } +- NOTICE("Erase Completed\n"); + } + /* End of function parameter_sector_erase_qspi_flash */ diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/s4/sa9.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/s4/sa9.c new file mode 100644 index 0000000..94e1618 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/s4/sa9.c @@ -0,0 +1,289 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 9(0x240000) + ******************************************************************************/ + +#include + +#define FLASH_BOOT (0U) +#define EMMC_BOOT (1U) +#define CA_IPL (0U) +#define BL31 (1U) + +/* CA program load num */ +#define CA_IMAGE_NUM (0x00000003U) +/* Source address on flash for Secure FW */ +#define SECURE_FW_SRC_ADDRESS (0x00280000U) +/* Source address on flash for RTOS */ +#define RTOS_SRC_ADDRESS (0x00500000U) +/* Source address on flash for ICUMH program */ +#define ICUMH_PROG_SRC_ADDRESS (0x00380000U) +/* Source address on flash for G4MH program (1st) */ +#define G4MH_PROG_SRC_ADDRESS (0x00900000U) +/* Source address on flash for G4MH program (2nd) */ +#define G4MH_PROG_02_SRC_ADDRESS (0x00A00000U) +#if (CA_LOAD_TYPE == CA_IPL) +/* Source address on flash for CX IPL */ +#define CX_IPL_SRC_ADDRESS (0x00480000U) +#else +/* Reserved */ +#define CX_IPL_SRC_ADDRESS (0x00000000U) +#endif +/* ----------- customized ----------- */ +/* Source address on flash for BL31 */ +#define CA_PROG_01_SRC_ADDRESS (0x00E00000U) +/* Source address on flash for OP-TEE */ +#define CA_PROG_02_SRC_ADDRESS (0x00E80000U) +/* Source address on flash for U-Boot */ +#define CA_PROG_03_SRC_ADDRESS (0x00F80000U) +/* Reserved */ +#define CA_PROG_04_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_05_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_06_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_07_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_08_SRC_ADDRESS (0x00000000U) +/* ----------- customized ----------- */ + +#if (RCAR_SA9_TYPE == FLASH_BOOT) +#define SECURE_FW_PARTITION (0x00000000U) +#define RTOS_PARTITION (0x00000000U) +#define ICUMH_PROG_PARTITION (0x00000000U) +#define G4MH_PROG_PARTITION (0x00000000U) +#define G4MH_PROG_02_PARTITION (0x00000000U) +#define CX_IPL_PARTITION (0x00000000U) + #if (CA_LOAD_TYPE == CA_IPL) +#define CA_PROG_01_PARTITION (0x00000001U) +#define CA_PROG_02_PARTITION (0x00000001U) +#define CA_PROG_03_PARTITION (0x00000001U) +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) + #else /* #if (CA_LOAD_TYPE == CA_IPL) */ +#define CA_PROG_01_PARTITION (0x00000000U) +#define CA_PROG_02_PARTITION (0x00000000U) +#define CA_PROG_03_PARTITION (0x00000000U) +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) + #endif /* #if (CA_LOAD_TYPE == CA_IPL) */ +#else /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ +#define SECURE_FW_PARTITION (0x00000001U) +#define RTOS_PARTITION (0x00000001U) +#define ICUMH_PROG_PARTITION (0x00000001U) +#define G4MH_PROG_PARTITION (0x00000001U) +#define G4MH_PROG_02_PARTITION (0x00000001U) +#define CX_IPL_PARTITION (0x00000001U) +#define CA_PROG_01_PARTITION (0x00000001U) +#define CA_PROG_02_PARTITION (0x00000001U) +#define CA_PROG_03_PARTITION (0x00000001U) +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) +#endif /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ + +#if (RCAR_SA9_TYPE != EMMC_BOOT) +/* Test data for QSPI DDR mode */ +#define QSPI_TESTDATA (0x5A5AA5A5U) +#else +#define QSPI_TESTDATA (0x00000000U) +#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + +/* Destination address for Secure FW */ +#define SECURE_FW_ADDRESS (0xEB240000U) +#define SECURE_FW_ADDRESSH (0x00000000U) +/* Destination size for Secure FW */ +#define SECURE_FW_DST_SIZE (0x00028000U) /* 640KiB / 4 */ +/* Destination address for RTOS */ +#define RTOS_ADDRESS (0xE2100000U) +#define RTOS_ADDRESSH (0x00000000U) +/* Destination size for RTOS */ +#define RTOS_DST_SIZE (0x00100000U) /* 4MiB / 4 */ +/* Destination address for ICUMH program */ +#define ICUMH_PROG_ADDRESS (0x10500000U) +#define ICUMH_PROG_ADDRESSH (0x00000000U) +/* Destination size for ICUMH program */ +#define ICUMH_PROG_DST_SIZE (0x00040000U) /* 1MiB / 4 */ +/* Destination address for G4MH program (1st) */ +#define G4MH_PROG_ADDRESS (0x10000000U) +#define G4MH_PROG_ADDRESSH (0x00000000U) +/* Destination size for G4MH program (1st) */ +#define G4MH_PROG_DST_SIZE (0x00040000U) /* 1MiB / 4 */ +/* Destination address for G4MH program (2nd) */ +#define G4MH_PROG_02_ADDRESS (0x10100000U) +#define G4MH_PROG_02_ADDRESSH (0x00000000U) +/* Destination size for G4MH program (2nd) */ +#define G4MH_PROG_02_DST_SIZE (0x00040000U) /* 1MiB / 4 */ +#if (CA_LOAD_TYPE == CA_IPL) +/* Destination address for CA Loader */ +#define CX_IPL_ADDRESS (0xE6300000U) +#define CX_UPL_ADDRESSH (0x00000000U) +/* Destination size for CA Loader */ +#define CX_IPL_SIZE (0x0000C000U) /* 192KiB / 4 */ +#else /* (CA_LOAD_TYPE == CA_IPL) */ +/* CX IPL Reserved */ +#define CX_IPL_ADDRESS (0x00000000U) +#define CX_UPL_ADDRESSH (0x00000000U) +#define CX_IPL_SIZE (0x00000000U) +#endif /* (CA_LOAD_TYPE == CA_IPL) */ +/* ----------- customized ----------- */ +/* Destination address for BL31 */ +#define CA_PROG_01_ADDRESS (0x46400000U) +#define CA_PROG_01_ADDRESSH (0x00000000U) +#define CA_PROG_01_SIZE (0x00008800U) /* 136KiB / 4 */ +/* Destination address for OP-TEE */ +#define CA_PROG_02_ADDRESS (0x44100000U) +#define CA_PROG_02_ADDRESSH (0x00000000U) +#define CA_PROG_02_SIZE (0x00040000U) /* 1MiB / 4 */ +/* Destination address for U-Boot */ +#define CA_PROG_03_ADDRESS (0x50000000U) +#define CA_PROG_03_ADDRESSH (0x00000000U) +#define CA_PROG_03_SIZE (0x00080000U) /* 2MiB / 4 */ +/* Reserved */ +#define CA_PROG_04_ADDRESS (0x00000000U) +#define CA_PROG_04_ADDRESSH (0x00000000U) +#define CA_PROG_04_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_05_ADDRESS (0x00000000U) +#define CA_PROG_05_ADDRESSH (0x00000000U) +#define CA_PROG_05_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_06_ADDRESS (0x00000000U) +#define CA_PROG_06_ADDRESSH (0x00000000U) +#define CA_PROG_06_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_07_ADDRESS (0x00000000U) +#define CA_PROG_07_ADDRESSH (0x00000000U) +#define CA_PROG_07_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_08_ADDRESS (0x00000000U) +#define CA_PROG_08_ADDRESSH (0x00000000U) +#define CA_PROG_08_SIZE (0x00000000U) +/* ----------- customized ----------- */ + +/* sa9 */ +__attribute__ ((section (".sa9_top"))) const uint32_t top_cert[1024 / 4] = { + [0x0000 / 4] = CA_IMAGE_NUM, + [0x0008 / 4] = SECURE_FW_SRC_ADDRESS, + [0x0010 / 4] = SECURE_FW_PARTITION, + [0x0018 / 4] = RTOS_SRC_ADDRESS, + [0x0020 / 4] = RTOS_PARTITION, + [0x0028 / 4] = CX_IPL_SRC_ADDRESS, + [0x0030 / 4] = CX_IPL_PARTITION, + [0x0038 / 4] = ICUMH_PROG_SRC_ADDRESS, + [0x0040 / 4] = ICUMH_PROG_PARTITION, + [0x0048 / 4] = G4MH_PROG_SRC_ADDRESS, + [0x0050 / 4] = G4MH_PROG_PARTITION, + [0x0058 / 4] = G4MH_PROG_02_SRC_ADDRESS, + [0x0060 / 4] = G4MH_PROG_02_PARTITION, + [0x0068 / 4] = CA_PROG_01_SRC_ADDRESS, + [0x0070 / 4] = CA_PROG_01_PARTITION, + [0x0078 / 4] = CA_PROG_02_SRC_ADDRESS, + [0x0080 / 4] = CA_PROG_02_PARTITION, + [0x0088 / 4] = CA_PROG_03_SRC_ADDRESS, + [0x0090 / 4] = CA_PROG_03_PARTITION, + [0x0098 / 4] = CA_PROG_04_SRC_ADDRESS, + [0x00A0 / 4] = CA_PROG_04_PARTITION, + [0x00A8 / 4] = CA_PROG_05_SRC_ADDRESS, + [0x00B0 / 4] = CA_PROG_05_PARTITION, + [0x00B8 / 4] = CA_PROG_06_SRC_ADDRESS, + [0x00C0 / 4] = CA_PROG_06_PARTITION, + [0x00C8 / 4] = CA_PROG_07_SRC_ADDRESS, + [0x00D0 / 4] = CA_PROG_07_PARTITION, + [0x00D8 / 4] = CA_PROG_08_SRC_ADDRESS, + [0x00E0 / 4] = CA_PROG_08_PARTITION, +}; +__attribute__ ((section (".qspi_test_data"))) const uint32_t test_data[1] = { + QSPI_TESTDATA +}; +__attribute__ ((section (".sa9_firm"))) const uint32_t firm_cert[2048 / 4] = { + [0x0154 / 4] = SECURE_FW_ADDRESS, + [0x0264 / 4] = SECURE_FW_DST_SIZE, +}; +__attribute__ ((section (".sa9_rtos"))) const uint32_t rtos_cert[2048 / 4] = { + [0x0154 / 4] = RTOS_ADDRESS, + [0x0264 / 4] = RTOS_DST_SIZE, +}; +__attribute__ ((section (".sa9_cx_ipl"))) const uint32_t cx_ipl_cert[2048 / 4] = { + [0x0154 / 4] = CX_IPL_ADDRESS, + [0x0264 / 4] = CX_IPL_SIZE, +}; +__attribute__ ((section (".sa9_ca_01"))) const uint32_t ca_01_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_01_ADDRESS, + [0x0264 / 4] = CA_PROG_01_SIZE, +}; + +__attribute__ ((section (".sa9_ca_02"))) const uint32_t ca_02_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_02_ADDRESS, + [0x0264 / 4] = CA_PROG_02_SIZE, +}; +__attribute__ ((section (".sa9_ca_03"))) const uint32_t ca_03_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_03_ADDRESS, + [0x0264 / 4] = CA_PROG_03_SIZE, +}; +__attribute__ ((section (".sa9_ca_04"))) const uint32_t ca_04_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_04_ADDRESS, + [0x0264 / 4] = CA_PROG_04_SIZE, +}; +__attribute__ ((section (".sa9_ca_05"))) const uint32_t ca_05_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_05_ADDRESS, + [0x0264 / 4] = CA_PROG_05_SIZE, +}; +__attribute__ ((section (".sa9_ca_06"))) const uint32_t ca_06_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_06_ADDRESS, + [0x0264 / 4] = CA_PROG_06_SIZE, +}; +__attribute__ ((section (".sa9_ca_07"))) const uint32_t ca_07_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_07_ADDRESS, + [0x0264 / 4] = CA_PROG_07_SIZE, +}; +__attribute__ ((section (".sa9_ca_08"))) const uint32_t ca_08_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_08_ADDRESS, + [0x0264 / 4] = CA_PROG_08_SIZE, +}; +__attribute__ ((section (".sa9_icumh"))) const uint32_t icumh_cert[2048 / 4] = { + [0x0154 / 4] = ICUMH_PROG_ADDRESS, + [0x0264 / 4] = ICUMH_PROG_DST_SIZE, +}; +__attribute__ ((section (".sa9_g4mh"))) const uint32_t g4mh_cert[2048 / 4] = { + [0x0154 / 4] = G4MH_PROG_ADDRESS, + [0x0264 / 4] = G4MH_PROG_DST_SIZE, +}; +__attribute__ ((section (".sa9_g4mh_02"))) const uint32_t g4mh_02_cert[2048 / 4] = { + [0x0154 / 4] = G4MH_PROG_02_ADDRESS, + [0x0264 / 4] = G4MH_PROG_02_DST_SIZE, +}; + +/* TFMV key(8KB) + NTFMV key(8KB) + minimum version table(4KB) */ +__attribute__ ((section (".reserved"))) const uint32_t reserved[20480 / 4] = {0}; diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/s4/sa9.ld b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/s4/sa9.ld new file mode 100644 index 0000000..ce24d18 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/s4/sa9.ld @@ -0,0 +1,66 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 9(0x240000) linker directive + ******************************************************************************/ +DEFAULTS { + dummy_addr = 0xEB230000 + + dummy_size = 64K +} +MEMORY +{ + rt_sram : ORIGIN = dummy_addr, LENGTH = dummy_size +} +SECTIONS +{ +// +// Dummy Certificate +// + _start = dummy_addr; + .sa9_top ALIGN(1024) : > rt_sram /* Offset 0x00240000 */ + .qspi_test_data ALIGN(1024) : > . /* Offset 0x00240400 */ + .reserved ALIGN(4096) : > . + .sa9_firm ALIGN(1024) : > . /* Offset 0x00246000 */ + .sa9_rtos ALIGN(1024) : > . /* Offset 0x00246800 */ + .sa9_cx_ipl ALIGN(1024) : > . /* Offset 0x00247000 */ + .sa9_icumh ALIGN(1024) : > . /* Offset 0x00247800 */ + .sa9_g4mh ALIGN(1024) : > . /* Offset 0x00248000 */ + .sa9_g4mh_02 ALIGN(1024) : > . /* Offset 0x00248800 */ + .sa9_ca_01 ALIGN(1024) : > . /* Offset 0x00249000 */ + .sa9_ca_02 ALIGN(1024) : > . /* Offset 0x00249800 */ + .sa9_ca_03 ALIGN(1024) : > . /* Offset 0x0024A000 */ + .sa9_ca_04 ALIGN(1024) : > . /* Offset 0x0024A800 */ + .sa9_ca_05 ALIGN(1024) : > . /* Offset 0x0024B000 */ + .sa9_ca_06 ALIGN(1024) : > . /* Offset 0x0024B800 */ + .sa9_ca_07 ALIGN(1024) : > . /* Offset 0x0024C000 */ + .sa9_ca_08 ALIGN(1024) : > . /* Offset 0x0024C800 */ + + + .sdata : > . + .tdata : > . + .rosdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/sa0.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/sa0.c new file mode 100644 index 0000000..24fa664 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/sa0.c @@ -0,0 +1,63 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 0(0x00000) + ******************************************************************************/ + +#include + +#define BOOT_PARAM (0x00000000U) +#define SFLASH_CLKSELR (0x00000005U) /* H'05 = B'0000_0101 = 80MHz Quad I/O */ +#define SFLASH_DMCYC (0xFFFFFFFFU) +// #define SFLASH_DMCYC (0x00000007U) /* H'07 = B'0_0111 = 8 Dummy Cycles */ +/* Actually setting the dummy cycles to 0x7 causes a boot error, + but setting 0xFFFFFFFF will let it go to default value of 0x7 - that works. */ +/* Botting QSPI wiht CLKSELR+DMCYC works + with MODEMR[1:0]: 0x0 0x820509ac - Wont work with 0x820109AC */ +#define CERT_MAGIC (0xE291F358U) +#define LOADER_ADDR (0xEB210000U) +#define LOADER_SIZE (128U * 1024U / 4U) + +/* SA0 */ +/* boot parameter */ +__attribute__ ((section(".sa0_boot"))) const uint32_t boot[] = { + [0] = BOOT_PARAM, +#if 0 + [1] = SFLASH_CLKSELR, + [2] = SFLASH_DMCYC, + [3] = 0xFFFFFFFFU, +#else + [1] = 0xFFFFFF02U, /* for 133MHz Quad read output */ +#endif + // [1] = 0xFFFFFF00U, /* for 80MHz Quad read output or Single Fast Read */ +}; + + +/* A-side contents Key (0x3000) */ +__attribute__ ((section(".sa0_content_a"))) const uint32_t content_a[872 / 4] = { +// [0x000 / 4] = CERT_MAGIC, /* magic */ + [0x00C / 4] = 0x00000000U, /* magic */ + [0x154 / 4] = LOADER_ADDR, /* address */ + [0x264 / 4] = LOADER_SIZE, /* size */ +}; diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/sa0.ld b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/sa0.ld new file mode 100644 index 0000000..4dd7e9e --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/sa0.ld @@ -0,0 +1,53 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 0(0x00000) linker directive + ******************************************************************************/ +DEFAULTS { + dummy_addr = 0xEB200000 + dummy_size = 2M + +} +MEMORY +{ + dram : ORIGIN = dummy_addr, LENGTH = dummy_size +} +SECTIONS +{ +// +// Dummy Certificate +// + .sa0 ALIGN(16) : { + _start=0; + *(.sa0_boot) _boot=0; + .=0x3000; + *(.sa0_content_a) _content_a=.; + } > dram + + .sdata : > . + .tdata : > . + .rosdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/v4h/sa9.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/v4h/sa9.c new file mode 100644 index 0000000..d0b264b --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/v4h/sa9.c @@ -0,0 +1,302 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 9(0x240000) + ******************************************************************************/ + +#include +#include + +#define FLASH_BOOT (0U) +#define EMMC_BOOT (1U) +#define CA_IPL (0U) +#define BL31 (1U) + +#define RTOS_LOAD_NUM_1 (1U) +#define RTOS_LOAD_NUM_3 (3U) + +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#error "OPTEE_LOAD_ENABLE==1 should be for RCAR_V4H" +#endif +#if (BL2_LOAD_ENABLE == 0) +#error "BL2_LOAD_ENABLE==1 should be for RCAR_V4H" +#endif +#if (QNX_OS_LOAD_ENABLE == 0) +#error "QNX_OS_LOAD_ENABLE==1 should be for RCAR_V4H" +#endif + +/* CA program load num */ +#define CA_IMAGE_NUM (0x00000005U) +/* Source address on flash for Secure FW */ +#define SECURE_FW_SRC_ADDRESS (0x00280000U) +/* Source address on flash for RTOS#0 */ +#define RTOS_SRC_ADDRESS (0x00500000U) +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* Source address on eMMC for RTOS#1 */ +#define RTOS1_SRC_ADDRESS (0x01000000U) +/* Source address on eMMC for RTOS#2 */ +#define RTOS2_SRC_ADDRESS (0x01200000U) +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +#if (CA_LOAD_TYPE == CA_IPL) +/* Source address on flash for CX IPL */ +#define CX_IPL_SRC_ADDRESS (0x00480000U) +#else +/* Reserved */ +#define CX_IPL_SRC_ADDRESS (0x00000000U) +#endif +/* ----------- customized ----------- */ +/* Source address on flash for BL31 */ +#define CA_PROG_01_SRC_ADDRESS (0x00D00000U) +/* Source address on flash for U-Boot */ +#define CA_PROG_02_SRC_ADDRESS (0x00E00000U) +/* Source address on flash for TEE-OS */ +#define CA_PROG_03_SRC_ADDRESS (0x00C00000U) +/* Source address of CA76-Loader */ +#define CA_PROG_04_SRC_ADDRESS (0x004C0000U) +/* Source address of QNX-OS */ +#define CA_PROG_05_SRC_ADDRESS (0x01000000U) +/* Reserved */ +#define CA_PROG_06_SRC_ADDRESS (0x01000000U) +/* Reserved */ +#define CA_PROG_07_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_08_SRC_ADDRESS (0x00000000U) +/* ----------- customized ----------- */ + +#if (RCAR_SA9_TYPE == FLASH_BOOT) +#define SECURE_FW_PARTITION (0x00000000U) +#define CX_IPL_PARTITION (0x00000000U) + #if (CA_LOAD_TYPE == CA_IPL) +#define RTOS_PARTITION (0x00000001U) +#define CA_PROG_01_PARTITION (0x00000001U) +#define CA_PROG_02_PARTITION (0x00000001U) +#define CA_PROG_03_PARTITION (0x00000001U) +#define CA_PROG_04_PARTITION (0x00000001U) +#define CA_PROG_05_PARTITION (0x00000001U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) + #if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RTOS1_PARTITION (0x00000001U) +#define RTOS2_PARTITION (0x00000001U) + #endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + #else /* #if (CA_LOAD_TYPE == CA_IPL) */ +#define RTOS_PARTITION (0x00000000U) +#define CA_PROG_01_PARTITION (0x00000000U) +#define CA_PROG_02_PARTITION (0x00000000U) +#define CA_PROG_03_PARTITION (0x00000000U) +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) + #endif /* #if (CA_LOAD_TYPE == CA_IPL) */ +#else /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ +#define SECURE_FW_PARTITION (0x00000001U) +#define RTOS_PARTITION (0x00000001U) +#define CX_IPL_PARTITION (0x00000001U) +#define CA_PROG_01_PARTITION (0x00000001U) +#define CA_PROG_02_PARTITION (0x00000001U) +#define CA_PROG_03_PARTITION (0x00000001U) +#define CA_PROG_04_PARTITION (0x00000001U) +#define CA_PROG_05_PARTITION (0x00000001U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) +#endif + +#if (RCAR_SA9_TYPE != EMMC_BOOT) +/* Test data for QSPI DDR mode */ +#define QSPI_TESTDATA (0x5A5AA5A5U) +#else +#define QSPI_TESTDATA (0x00000000U) +#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + +/* Destination address for Secure FW */ +#define SECURE_FW_ADDRESS (0xEB240000U) +#define SECURE_FW_ADDRESSH (0x00000000U) +/* Destination size for Secure FW */ +#define SECURE_FW_DST_SIZE (0x00028000U) /* 640KiB / 4 */ +/* Destination address for RTOS#0 */ +#define RTOS_ADDRESS (0xE2100000U) +#define RTOS_ADDRESSH (0x00000000U) +/* Destination size for RTOS#0 */ +#define RTOS_DST_SIZE (0x001C0000U) /* 7MiB / 4 */ +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* Destination address for RTOS#1 */ +#define RTOS1_ADDRESS (0xE3100000U) +#define RTOS1_ADDRESSH (0x00000000U) +/* Destination size for RTOS#1 */ +#define RTOS1_DST_SIZE (0x00080000U) /* 2MiB / 4 */ +/* Destination address for RTOS#2 */ +#define RTOS2_ADDRESS (0xE2000000U) +#define RTOS2_ADDRESSH (0x00000000U) +/* Destination size for RTOS#2 */ +#define RTOS2_DST_SIZE (0x00004000U) /* 64KiB / 4 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +#if (CA_LOAD_TYPE == CA_IPL) +/* Destination address for CA Loader */ +#define CX_IPL_ADDRESS (0xE6300000U) +#define CX_UPL_ADDRESSH (0x00000000U) +/* Destination size for CA Loader */ +#define CX_IPL_SIZE (0x0000C000U) /* 192KiB / 4 */ +#else +/* CX IPL Reserved */ +#define CX_IPL_ADDRESS (0x00000000U) +#define CX_UPL_ADDRESSH (0x00000000U) +#define CX_IPL_SIZE (0x00000000U) +#endif +/* ----------- customized ----------- */ +/* Destination address for BL31 */ +#define CA_PROG_01_ADDRESS (0x46400000U) +#define CA_PROG_01_ADDRESSH (0x00000000U) +#define CA_PROG_01_SIZE (0x00008800U) /* 136KiB / 4 */ +/* Destination address for U-Boot */ +#define CA_PROG_02_ADDRESS (0x50000000U) +#define CA_PROG_02_ADDRESSH (0x00000000U) +#define CA_PROG_02_SIZE (0x00040000U) /* 1MiB / 4 */ +/* Destination address for tee-OS */ +#define CA_PROG_03_ADDRESS (0x44100000U) +#define CA_PROG_03_ADDRESSH (0x00000000U) +#define CA_PROG_03_SIZE (0x00040000U) /* 1MiB / 4 */ +/* Destination address for CA76-Loader */ +#define CA_PROG_04_ADDRESS (0x41D00000U) +#define CA_PROG_04_ADDRESSH (0x00000000U) +#define CA_PROG_04_SIZE (0x00008000U) /* 128KiB / 4 */ +/* Destination address of QNX-OS */ +#define CA_PROG_05_ADDRESS (0x50100000U) +#define CA_PROG_05_ADDRESSH (0x00000000U) +#define CA_PROG_05_SIZE (0x00200000U) /* 8MiB / 4 */ +/* Reserved */ +#define CA_PROG_06_ADDRESS (0x00000000U) +#define CA_PROG_06_ADDRESSH (0x00000000U) +#define CA_PROG_06_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_07_ADDRESS (0x00000000U) +#define CA_PROG_07_ADDRESSH (0x00000000U) +#define CA_PROG_07_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_08_ADDRESS (0x00000000U) +#define CA_PROG_08_ADDRESSH (0x00000000U) +#define CA_PROG_08_SIZE (0x00000000U) +/* ----------- customized ----------- */ + +/* sa9 */ +__attribute__ ((section (".sa9_top"))) const uint32_t top_cert[1024 / 4] = { + [0x0000 / 4] = CA_IMAGE_NUM, + [0x0008 / 4] = SECURE_FW_SRC_ADDRESS, + [0x0010 / 4] = SECURE_FW_PARTITION, + [0x0018 / 4] = RTOS_SRC_ADDRESS, + [0x0020 / 4] = RTOS_PARTITION, + [0x0028 / 4] = CX_IPL_SRC_ADDRESS, + [0x0030 / 4] = CX_IPL_PARTITION, + [0x0068 / 4] = CA_PROG_01_SRC_ADDRESS, + [0x0070 / 4] = CA_PROG_01_PARTITION, + [0x0078 / 4] = CA_PROG_02_SRC_ADDRESS, + [0x0080 / 4] = CA_PROG_02_PARTITION, + [0x0088 / 4] = CA_PROG_03_SRC_ADDRESS, + [0x0090 / 4] = CA_PROG_03_PARTITION, + [0x0098 / 4] = CA_PROG_04_SRC_ADDRESS, + [0x00A0 / 4] = CA_PROG_04_PARTITION, + [0x00A8 / 4] = CA_PROG_05_SRC_ADDRESS, + [0x00B0 / 4] = CA_PROG_05_PARTITION, + [0x00B8 / 4] = CA_PROG_06_SRC_ADDRESS, + [0x00C0 / 4] = CA_PROG_06_PARTITION, + [0x00C8 / 4] = CA_PROG_07_SRC_ADDRESS, + [0x00D0 / 4] = CA_PROG_07_PARTITION, + [0x00D8 / 4] = CA_PROG_08_SRC_ADDRESS, + [0x00E0 / 4] = CA_PROG_08_PARTITION, +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + [0x0108 / 4] = RTOS1_SRC_ADDRESS, + [0x0110 / 4] = RTOS1_PARTITION, + [0x0118 / 4] = RTOS2_SRC_ADDRESS, + [0x0120 / 4] = RTOS2_PARTITION, +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +}; +__attribute__ ((section (".qspi_test_data"))) const uint32_t test_data[1] = { + QSPI_TESTDATA +}; +__attribute__ ((section (".sa9_firm"))) const uint32_t firm_cert[2048 / 4] = { + [0x0154 / 4] = SECURE_FW_ADDRESS, + [0x0264 / 4] = SECURE_FW_DST_SIZE, +}; +__attribute__ ((section (".sa9_rtos"))) const uint32_t rtos_cert[2048 / 4] = { + [0x0154 / 4] = RTOS_ADDRESS, + [0x0264 / 4] = RTOS_DST_SIZE, +}; +__attribute__ ((section (".sa9_cx_ipl"))) const uint32_t cx_ipl_cert[2048 / 4] = { + [0x0154 / 4] = CX_IPL_ADDRESS, + [0x0264 / 4] = CX_IPL_SIZE, +}; +__attribute__ ((section (".sa9_ca_01"))) const uint32_t ca_01_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_01_ADDRESS, + [0x0264 / 4] = CA_PROG_01_SIZE, +}; + +__attribute__ ((section (".sa9_ca_02"))) const uint32_t ca_02_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_02_ADDRESS, + [0x0264 / 4] = CA_PROG_02_SIZE, +}; +__attribute__ ((section (".sa9_ca_03"))) const uint32_t ca_03_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_03_ADDRESS, + [0x0264 / 4] = CA_PROG_03_SIZE, +}; +__attribute__ ((section (".sa9_ca_04"))) const uint32_t ca_04_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_04_ADDRESS, + [0x0264 / 4] = CA_PROG_04_SIZE, +}; +__attribute__ ((section (".sa9_ca_05"))) const uint32_t ca_05_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_05_ADDRESS, + [0x0264 / 4] = CA_PROG_05_SIZE, +}; +__attribute__ ((section (".sa9_ca_06"))) const uint32_t ca_06_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_06_ADDRESS, + [0x0264 / 4] = CA_PROG_06_SIZE, +}; +__attribute__ ((section (".sa9_ca_07"))) const uint32_t ca_07_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_07_ADDRESS, + [0x0264 / 4] = CA_PROG_07_SIZE, +}; +__attribute__ ((section (".sa9_ca_08"))) const uint32_t ca_08_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_08_ADDRESS, + [0x0264 / 4] = CA_PROG_08_SIZE, +}; + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +__attribute__ ((section (".sa9_rtos_01"))) const uint32_t rtos1_cert[2048 / 4] = { + [0x0154 / 4] = RTOS1_ADDRESS, + [0x0264 / 4] = RTOS1_DST_SIZE, +}; +__attribute__ ((section (".sa9_rtos_02"))) const uint32_t rtos2_cert[2048 / 4] = { + [0x0154 / 4] = RTOS2_ADDRESS, + [0x0264 / 4] = RTOS2_DST_SIZE, +}; +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* TFMV key(8KB) + NTFMV key(8KB) + minimum version table(4KB) */ +__attribute__ ((section (".reserved"))) const uint32_t reserved[20480 / 4] = {0}; +/* G4MH cert * 2 + ICUMH Cert */ +__attribute__ ((section (".reserved2"))) const uint32_t reserved2[6144 / 4] = {0}; diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/v4h/sa9.ld b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/v4h/sa9.ld new file mode 100644 index 0000000..dbf3dc7 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/v4h/sa9.ld @@ -0,0 +1,67 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 9(0x240000) linker directive + ******************************************************************************/ +DEFAULTS { + dummy_addr = 0xEB230000 + + dummy_size = 64K + +} +MEMORY +{ + rt_sram : ORIGIN = dummy_addr, LENGTH = dummy_size +} +SECTIONS +{ +// +// Dummy Certificate +// + _start = dummy_addr; + .sa9_top ALIGN(1024) : > rt_sram /* Offset 0x00240000 */ + .qspi_test_data ALIGN(1024) : > . /* Offset 0x00240400 */ + .reserved ALIGN(4096) : > . + .sa9_firm ALIGN(1024) : > . /* Offset 0x00246000 */ + .sa9_rtos ALIGN(1024) : > . /* Offset 0x00246800 */ + .sa9_cx_ipl ALIGN(1024) : > . /* Offset 0x00247000 */ + .reserved2 ALIGN(1024) : > . + .sa9_ca_01 ALIGN(1024) : > . /* Offset 0x00249000 */ + .sa9_ca_02 ALIGN(1024) : > . /* Offset 0x00249800 */ + .sa9_ca_03 ALIGN(1024) : > . /* Offset 0x0024A000 */ + .sa9_ca_04 ALIGN(1024) : > . /* Offset 0x0024A800 */ + .sa9_ca_05 ALIGN(1024) : > . /* Offset 0x0024B000 */ + .sa9_ca_06 ALIGN(1024) : > . /* Offset 0x0024B800 */ + .sa9_ca_07 ALIGN(1024) : > . /* Offset 0x0024C000 */ + .sa9_ca_08 ALIGN(1024) : > . /* Offset 0x0024C800 */ + /* 0x0024D000 - 0x0024DFFF is area for TFMV/NTFMV minimum version table certificate */ + .sa9_rtos_01 ALIGN(1024) PAD(4096) : > . /* Offset 0x0024E000 */ + .sa9_rtos_02 ALIGN(1024) : > . /* Offset 0x0024E800 */ + + .sdata : > . + .tdata : > . + .rosdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/v4m/sa9.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/v4m/sa9.c new file mode 100644 index 0000000..2aa9e4e --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/v4m/sa9.c @@ -0,0 +1,316 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 9(0x240000) + ******************************************************************************/ + +#include +#include + +#define FLASH_BOOT (0U) +#define EMMC_BOOT (1U) +#define CA_IPL (0U) +#define BL31 (1U) + +#define RTOS_LOAD_NUM_1 (1U) +#define RTOS_LOAD_NUM_3 (3U) + +/* CA program load num */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define CA_IMAGE_NUM (0x00000002U) +#else +#define CA_IMAGE_NUM (0x00000003U) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +/* Source address on flash for Secure FW */ +#define SECURE_FW_SRC_ADDRESS (0x00280000U) +/* Source address on flash for RTOS#0 */ +#define RTOS_SRC_ADDRESS (0x00000000U) +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* Source address on eMMC for RTOS#1 */ +#define RTOS1_SRC_ADDRESS (0x01000000U) +/* Source address on eMMC for RTOS#2 */ +#define RTOS2_SRC_ADDRESS (0x01200000U) +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +#if (CA_LOAD_TYPE == CA_IPL) +/* Source address on flash for CX IPL */ +#define CX_IPL_SRC_ADDRESS (0x00480000U) +#else +/* Reserved */ +#define CX_IPL_SRC_ADDRESS (0x00000000U) +#endif +/* ----------- customized ----------- */ +/* Source address on flash for BL31 */ +#define CA_PROG_01_SRC_ADDRESS (0x01400000U) +/* Source address on flash for U-Boot */ +#define CA_PROG_02_SRC_ADDRESS (0x01580000U) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +/* Reserved */ +#define CA_PROG_03_SRC_ADDRESS (0x00000000U) +#else +/* Source address on flash for OP-TEE */ +#define CA_PROG_03_SRC_ADDRESS (0x01480000U) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +/* Reserved */ +#define CA_PROG_04_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_05_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_06_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_07_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_08_SRC_ADDRESS (0x00000000U) +/* ----------- customized ----------- */ + +#if (RCAR_SA9_TYPE == FLASH_BOOT) +#define SECURE_FW_PARTITION (0x00000000U) +#define CX_IPL_PARTITION (0x00000000U) + #if (CA_LOAD_TYPE == CA_IPL) +#define RTOS_PARTITION (0x00000001U) +#define CA_PROG_01_PARTITION (0x00000001U) +#define CA_PROG_02_PARTITION (0x00000001U) + #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define CA_PROG_03_PARTITION (0x00000000U) + #else +#define CA_PROG_03_PARTITION (0x00000001U) + #endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) + #if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RTOS1_PARTITION (0x00000001U) +#define RTOS2_PARTITION (0x00000001U) + #endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + #else /* #if (CA_LOAD_TYPE == CA_IPL) */ +#define RTOS_PARTITION (0x00000000U) +#define CA_PROG_01_PARTITION (0x00000000U) +#define CA_PROG_02_PARTITION (0x00000000U) +#define CA_PROG_03_PARTITION (0x00000000U) +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) + #endif /* #if (CA_LOAD_TYPE == CA_IPL) */ +#else /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ +#define SECURE_FW_PARTITION (0x00000001U) +#define RTOS_PARTITION (0x00000001U) +#define CX_IPL_PARTITION (0x00000001U) +#define CA_PROG_01_PARTITION (0x00000001U) +#define CA_PROG_02_PARTITION (0x00000001U) + #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define CA_PROG_03_PARTITION (0x00000000U) + #else +#define CA_PROG_03_PARTITION (0x00000001U) + #endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) +#endif + +#if (RCAR_SA9_TYPE != EMMC_BOOT) +/* Test data for QSPI DDR mode */ +#define QSPI_TESTDATA (0x5A5AA5A5U) +#else +#define QSPI_TESTDATA (0x00000000U) +#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + +/* Destination address for Secure FW */ +#define SECURE_FW_ADDRESS (0xEB240000U) +#define SECURE_FW_ADDRESSH (0x00000000U) +/* Destination size for Secure FW */ +#define SECURE_FW_DST_SIZE (0x00028000U) /* 640KiB / 4 */ +/* Destination address for RTOS#0 */ +#define RTOS_ADDRESS (0xE2100000U) +#define RTOS_ADDRESSH (0x00000000U) +/* Destination size for RTOS#0 */ +#define RTOS_DST_SIZE (0x00400000U) /* 16MiB / 4 */ +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* Destination address for RTOS#1 */ +#define RTOS1_ADDRESS (0xE3100000U) +#define RTOS1_ADDRESSH (0x00000000U) +/* Destination size for RTOS#1 */ +#define RTOS1_DST_SIZE (0x00080000U) /* 2MiB / 4 */ +/* Destination address for RTOS#2 */ +#define RTOS2_ADDRESS (0xE2000000U) +#define RTOS2_ADDRESSH (0x00000000U) +/* Destination size for RTOS#2 */ +#define RTOS2_DST_SIZE (0x00004000U) /* 64KiB / 4 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +#if (CA_LOAD_TYPE == CA_IPL) +/* Destination address for CA Loader */ +#define CX_IPL_ADDRESS (0xE6300000U) +#define CX_UPL_ADDRESSH (0x00000000U) +/* Destination size for CA Loader */ +#define CX_IPL_SIZE (0x0000C000U) /* 192KiB / 4 */ +#else +/* CX IPL Reserved */ +#define CX_IPL_ADDRESS (0x00000000U) +#define CX_UPL_ADDRESSH (0x00000000U) +#define CX_IPL_SIZE (0x00000000U) +#endif +/* ----------- customized ----------- */ +/* Destination address for BL31 */ +#define CA_PROG_01_ADDRESS (0x46400000U) +#define CA_PROG_01_ADDRESSH (0x00000000U) +#define CA_PROG_01_SIZE (0x00008800U) /* 136KiB / 4 */ +/* Destination address for U-Boot */ +#define CA_PROG_02_ADDRESS (0x50000000U) +#define CA_PROG_02_ADDRESSH (0x00000000U) +#define CA_PROG_02_SIZE (0x00080000U) /* 2MiB / 4 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +/* Reserved */ +#define CA_PROG_03_ADDRESS (0x00000000U) +#define CA_PROG_03_ADDRESSH (0x00000000U) +#define CA_PROG_03_SIZE (0x00000000U) +#else +/* Destination address for OP-TEE */ +#define CA_PROG_03_ADDRESS (0x44100000U) +#define CA_PROG_03_ADDRESSH (0x00000000U) +#define CA_PROG_03_SIZE (0x00040000U) /* 1MiB / 4 */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +/* Reserved */ +#define CA_PROG_04_ADDRESS (0x00000000U) +#define CA_PROG_04_ADDRESSH (0x00000000U) +#define CA_PROG_04_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_05_ADDRESS (0x00000000U) +#define CA_PROG_05_ADDRESSH (0x00000000U) +#define CA_PROG_05_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_06_ADDRESS (0x00000000U) +#define CA_PROG_06_ADDRESSH (0x00000000U) +#define CA_PROG_06_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_07_ADDRESS (0x00000000U) +#define CA_PROG_07_ADDRESSH (0x00000000U) +#define CA_PROG_07_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_08_ADDRESS (0x00000000U) +#define CA_PROG_08_ADDRESSH (0x00000000U) +#define CA_PROG_08_SIZE (0x00000000U) +/* ----------- customized ----------- */ + +/* sa9 */ +__attribute__ ((section (".sa9_top"))) const uint32_t top_cert[1024 / 4] = { + [0x0000 / 4] = CA_IMAGE_NUM, + [0x0008 / 4] = SECURE_FW_SRC_ADDRESS, + [0x0010 / 4] = SECURE_FW_PARTITION, + [0x0018 / 4] = RTOS_SRC_ADDRESS, + [0x0020 / 4] = RTOS_PARTITION, + [0x0028 / 4] = CX_IPL_SRC_ADDRESS, + [0x0030 / 4] = CX_IPL_PARTITION, + [0x0068 / 4] = CA_PROG_01_SRC_ADDRESS, + [0x0070 / 4] = CA_PROG_01_PARTITION, + [0x0078 / 4] = CA_PROG_02_SRC_ADDRESS, + [0x0080 / 4] = CA_PROG_02_PARTITION, + [0x0088 / 4] = CA_PROG_03_SRC_ADDRESS, + [0x0090 / 4] = CA_PROG_03_PARTITION, + [0x0098 / 4] = CA_PROG_04_SRC_ADDRESS, + [0x00A0 / 4] = CA_PROG_04_PARTITION, + [0x00A8 / 4] = CA_PROG_05_SRC_ADDRESS, + [0x00B0 / 4] = CA_PROG_05_PARTITION, + [0x00B8 / 4] = CA_PROG_06_SRC_ADDRESS, + [0x00C0 / 4] = CA_PROG_06_PARTITION, + [0x00C8 / 4] = CA_PROG_07_SRC_ADDRESS, + [0x00D0 / 4] = CA_PROG_07_PARTITION, + [0x00D8 / 4] = CA_PROG_08_SRC_ADDRESS, + [0x00E0 / 4] = CA_PROG_08_PARTITION, +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + [0x0108 / 4] = RTOS1_SRC_ADDRESS, + [0x0110 / 4] = RTOS1_PARTITION, + [0x0118 / 4] = RTOS2_SRC_ADDRESS, + [0x0120 / 4] = RTOS2_PARTITION, +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +}; +__attribute__ ((section (".qspi_test_data"))) const uint32_t test_data[1] = { + QSPI_TESTDATA +}; +__attribute__ ((section (".sa9_firm"))) const uint32_t firm_cert[2048 / 4] = { + [0x0154 / 4] = SECURE_FW_ADDRESS, + [0x0264 / 4] = SECURE_FW_DST_SIZE, +}; +__attribute__ ((section (".sa9_rtos"))) const uint32_t rtos_cert[2048 / 4] = { + [0x0154 / 4] = RTOS_ADDRESS, + [0x0264 / 4] = RTOS_DST_SIZE, +}; +__attribute__ ((section (".sa9_cx_ipl"))) const uint32_t cx_ipl_cert[2048 / 4] = { + [0x0154 / 4] = CX_IPL_ADDRESS, + [0x0264 / 4] = CX_IPL_SIZE, +}; +__attribute__ ((section (".sa9_ca_01"))) const uint32_t ca_01_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_01_ADDRESS, + [0x0264 / 4] = CA_PROG_01_SIZE, +}; + +__attribute__ ((section (".sa9_ca_02"))) const uint32_t ca_02_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_02_ADDRESS, + [0x0264 / 4] = CA_PROG_02_SIZE, +}; +__attribute__ ((section (".sa9_ca_03"))) const uint32_t ca_03_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_03_ADDRESS, + [0x0264 / 4] = CA_PROG_03_SIZE, +}; +__attribute__ ((section (".sa9_ca_04"))) const uint32_t ca_04_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_04_ADDRESS, + [0x0264 / 4] = CA_PROG_04_SIZE, +}; +__attribute__ ((section (".sa9_ca_05"))) const uint32_t ca_05_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_05_ADDRESS, + [0x0264 / 4] = CA_PROG_05_SIZE, +}; +__attribute__ ((section (".sa9_ca_06"))) const uint32_t ca_06_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_06_ADDRESS, + [0x0264 / 4] = CA_PROG_06_SIZE, +}; +__attribute__ ((section (".sa9_ca_07"))) const uint32_t ca_07_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_07_ADDRESS, + [0x0264 / 4] = CA_PROG_07_SIZE, +}; +__attribute__ ((section (".sa9_ca_08"))) const uint32_t ca_08_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_08_ADDRESS, + [0x0264 / 4] = CA_PROG_08_SIZE, +}; + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +__attribute__ ((section (".sa9_rtos_01"))) const uint32_t rtos1_cert[2048 / 4] = { + [0x0154 / 4] = RTOS1_ADDRESS, + [0x0264 / 4] = RTOS1_DST_SIZE, +}; +__attribute__ ((section (".sa9_rtos_02"))) const uint32_t rtos2_cert[2048 / 4] = { + [0x0154 / 4] = RTOS2_ADDRESS, + [0x0264 / 4] = RTOS2_DST_SIZE, +}; +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* TFMV key(8KB) + NTFMV key(8KB) + minimum version table(4KB) */ +__attribute__ ((section (".reserved"))) const uint32_t reserved[20480 / 4] = {0}; +/* G4MH cert * 2 + ICUMH Cert */ +__attribute__ ((section (".reserved2"))) const uint32_t reserved2[6144 / 4] = {0}; diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/v4m/sa9.ld b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/v4m/sa9.ld new file mode 100644 index 0000000..11c8421 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/dummy_create/v4m/sa9.ld @@ -0,0 +1,68 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 9(0x240000) linker directive + ******************************************************************************/ +DEFAULTS { + dummy_addr = 0xEB230000 + + dummy_size = 64K + +} +MEMORY +{ + rt_sram : ORIGIN = dummy_addr, LENGTH = dummy_size +} +SECTIONS +{ +// +// Dummy Certificate +// + _start = dummy_addr; + .sa9_top ALIGN(1024) : > rt_sram /* Offset 0x00240000 */ + .qspi_test_data ALIGN(1024) : > . /* Offset 0x00240400 */ + .reserved ALIGN(4096) : > . + .sa9_firm ALIGN(1024) : > . /* Offset 0x00246000 */ + .sa9_rtos ALIGN(1024) : > . /* Offset 0x00246800 */ + .sa9_cx_ipl ALIGN(1024) : > . /* Offset 0x00247000 */ + .reserved2 ALIGN(1024) : > . + .sa9_ca_01 ALIGN(1024) : > . /* Offset 0x00249000 */ + .sa9_ca_02 ALIGN(1024) : > . /* Offset 0x00249800 */ + .sa9_ca_03 ALIGN(1024) : > . /* Offset 0x0024A000 */ + .sa9_ca_04 ALIGN(1024) : > . /* Offset 0x0024A800 */ + .sa9_ca_05 ALIGN(1024) : > . /* Offset 0x0024B000 */ + .sa9_ca_06 ALIGN(1024) : > . /* Offset 0x0024B800 */ + .sa9_ca_07 ALIGN(1024) : > . /* Offset 0x0024C000 */ + .sa9_ca_08 ALIGN(1024) : > . /* Offset 0x0024C800 */ + /* 0x0024D000 - 0x0024DFFF is area for TFMV/NTFMV minimum version table certificate */ + .sa9_rtos_01 ALIGN(1024) PAD(4096) : > . /* Offset 0x0024E000 */ + .sa9_rtos_02 ALIGN(1024) : > . /* Offset 0x0024E800 */ + + + .sdata : > . + .tdata : > . + .rosdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/ntfmv_ver_tbl.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/ntfmv_ver_tbl.c new file mode 100644 index 0000000..4f50da6 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/ntfmv_ver_tbl.c @@ -0,0 +1,111 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : NTFMV Software minimum version table + ******************************************************************************/ +/****************************************************************************** + * @file ntfmv_ver_tbl.c + * - Version : 0.02 + * @brief NTFMV Software minimum version table. + * This is sample source code. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.08.2022 0.01 First Release + * : 21.08.2023 0.02 Add support for V4M. + *****************************************************************************/ + +#include + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +/* Minimum software version of U-Boot(V4H) */ +#define CA_PROG_02_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_02_SW_VERSION (0x00000000U) +#define CA_PROG_02_VER_OFFSET (0x00000000U) +#else /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ +/* Reserved */ +#define CA_PROG_02_CHECK_FLAG (0x00000000U) +#define CA_PROG_02_SW_VERSION (0x00000000U) +#define CA_PROG_02_VER_OFFSET (0x00000000U) +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +/* Minimum software version of U-Boot(S4) */ +#define CA_PROG_03_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_03_SW_VERSION (0x00000000U) +#define CA_PROG_03_VER_OFFSET (0x00000000U) + +/* Reserved */ +#define CA_PROG_04_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_04_SW_VERSION (0x00000000U) +#define CA_PROG_04_VER_OFFSET (0x00000000U) + +/* Reserved */ +#define CA_PROG_05_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_05_SW_VERSION (0x00000000U) +#define CA_PROG_05_VER_OFFSET (0x00000000U) + +/* Reserved */ +#define CA_PROG_06_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_06_SW_VERSION (0x00000000U) +#define CA_PROG_06_VER_OFFSET (0x00000000U) + +/* Reserved */ +#define CA_PROG_07_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_07_SW_VERSION (0x00000000U) +#define CA_PROG_07_VER_OFFSET (0x00000000U) + +/* Reserved */ +#define CA_PROG_08_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_08_SW_VERSION (0x00000000U) +#define CA_PROG_08_VER_OFFSET (0x00000000U) + +/* For 16-byte boundary */ +#define RESERVED_FOR_PADDING (0x00000000U) + +__attribute__ ((section (".ntfmv_tbl_top"))) const uint32_t ntfmv_ver_tbl[] = { + [0x0000 / 4] = CA_PROG_02_CHECK_FLAG, + [0x0004 / 4] = CA_PROG_02_SW_VERSION, + [0x0008 / 4] = CA_PROG_02_VER_OFFSET, + [0x0010 / 4] = CA_PROG_03_CHECK_FLAG, + [0x0014 / 4] = CA_PROG_03_SW_VERSION, + [0x0018 / 4] = CA_PROG_03_VER_OFFSET, + [0x0020 / 4] = CA_PROG_04_CHECK_FLAG, + [0x0024 / 4] = CA_PROG_04_SW_VERSION, + [0x0028 / 4] = CA_PROG_04_VER_OFFSET, + [0x0030 / 4] = CA_PROG_05_CHECK_FLAG, + [0x0034 / 4] = CA_PROG_05_SW_VERSION, + [0x0038 / 4] = CA_PROG_05_VER_OFFSET, + [0x0040 / 4] = CA_PROG_06_CHECK_FLAG, + [0x0044 / 4] = CA_PROG_06_SW_VERSION, + [0x0048 / 4] = CA_PROG_06_VER_OFFSET, + [0x0050 / 4] = CA_PROG_07_CHECK_FLAG, + [0x0054 / 4] = CA_PROG_07_SW_VERSION, + [0x0058 / 4] = CA_PROG_07_VER_OFFSET, + [0x0060 / 4] = CA_PROG_08_CHECK_FLAG, + [0x0064 / 4] = CA_PROG_08_SW_VERSION, + [0x0068 / 4] = CA_PROG_08_VER_OFFSET, + [0x006C / 4] = RESERVED_FOR_PADDING, /* Adjust to 16-byte boundary */ +}; + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/ntfmv_ver_tbl.ld b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/ntfmv_ver_tbl.ld new file mode 100644 index 0000000..b6b3d77 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/ntfmv_ver_tbl.ld @@ -0,0 +1,60 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : linker directive for NTFMV Software minimum version table + ******************************************************************************/ +/****************************************************************************** + * @file ntfmv_ver_tbl.ld + * - Version : 0.01 + * @brief linker directive for NTFMV Software minimum version table. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.08.2022 0.01 First Release + *****************************************************************************/ + +DEFAULTS { + tbl_base_addr = 0xEB235800 + + tbl_size = 2K +} +MEMORY +{ + rt_sram : ORIGIN = tbl_base_addr, LENGTH = tbl_size +} +SECTIONS +{ +// +// NTFMV Software minimum version table +// + _start = tbl_base_addr; + .ntfmv_tbl_top ALIGN(1024) : > rt_sram + + .sdata : > . + .tdata : > . + .rosdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +} diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/tfmv_ver_tbl.c b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/tfmv_ver_tbl.c new file mode 100644 index 0000000..699a004 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/tfmv_ver_tbl.c @@ -0,0 +1,141 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : TFMV Software minimum version table + ******************************************************************************/ +/****************************************************************************** + * @file tfmv_ver_tbl.c + * - Version : 0.01 + * @brief TFMV Software minimum version table. + * This is sample source code. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.08.2022 0.01 First Release + *****************************************************************************/ + +#include + +#define CA_IPL (0U) + +/* Minimum software version of Secure FW */ +#define SECURE_FW_CHECK_FLAG (0x00000001U) /* 0:disable other:enable */ +#define SECURE_FW_SW_VERSION (0x00000001U) +#define SECURE_FW_VER_OFFSET (0x00000400U) + +/* Minimum software version of RTOS */ +#define RTOS_SW_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define RTOS_SW_SW_VERSION (0x00000000U) +#define RTOS_SW_VER_OFFSET (0x00000000U) + +#if (CA_LOAD_TYPE == CA_IPL) +/* Minimum software version of CX 2nd IPL */ +#define CX_2ND_IPL_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CX_2ND_IPL_SW_VERSION (0x00000000U) +#define CX_2ND_IPL_VER_OFFSET (0x00000000U) +#else /* (CA_LOAD_TYPE == CA_IPL) */ +/* Reserved */ +#define CX_2ND_IPL_CHECK_FLAG (0x00000000U) +#define CX_2ND_IPL_SW_VERSION (0x00000000U) +#define CX_2ND_IPL_VER_OFFSET (0x00000000U) +#endif /* (CA_LOAD_TYPE == CA_IPL) */ + +#if (RCAR_LSI == RCAR_S4) +/* Minimum software version of ICUMH program */ +#define ICUMH_PROG_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define ICUMH_PROG_SW_VERSION (0x00000000U) +#define ICUMH_PROG_VER_OFFSET (0x00000000U) + +/* Minimum software version of G4MH program(1st) */ +#define G4MH_PROG_01_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define G4MH_PROG_01_SW_VERSION (0x00000000U) +#define G4MH_PROG_01_VER_OFFSET (0x00000000U) + +/* Minimum software version of G4MH program(2nd) */ +#define G4MH_PROG_02_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define G4MH_PROG_02_SW_VERSION (0x00000000U) +#define G4MH_PROG_02_VER_OFFSET (0x00000000U) + +#else /* (RCAR_LSI == RCAR_S4) */ +/* Reserved */ +#define ICUMH_PROG_CHECK_FLAG (0x00000000U) +#define ICUMH_PROG_SW_VERSION (0x00000000U) +#define ICUMH_PROG_VER_OFFSET (0x00000000U) +#define G4MH_PROG_01_CHECK_FLAG (0x00000000U) +#define G4MH_PROG_01_SW_VERSION (0x00000000U) +#define G4MH_PROG_01_VER_OFFSET (0x00000000U) +#define G4MH_PROG_02_CHECK_FLAG (0x00000000U) +#define G4MH_PROG_02_SW_VERSION (0x00000000U) +#define G4MH_PROG_02_VER_OFFSET (0x00000000U) +#endif /* (RCAR_LSI == RCAR_S4) */ + +/* Minimum software version of BL31 */ +#define CA_PROG_01_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_01_SW_VERSION (0x00000000U) +#define CA_PROG_01_VER_OFFSET (0x00000000U) + +#if (RCAR_LSI == RCAR_S4) +/* Minimum software version of OP-TEE */ +#define CA_PROG_02_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_02_SW_VERSION (0x00000000U) +#define CA_PROG_02_VER_OFFSET (0x00000000U) +#else /* (RCAR_LSI == RCAR_S4) */ +/* Reserved */ +#define CA_PROG_02_CHECK_FLAG (0x00000000U) +#define CA_PROG_02_SW_VERSION (0x00000000U) +#define CA_PROG_02_VER_OFFSET (0x00000000U) +#endif /* (RCAR_LSI == RCAR_S4) */ + +/* For 16-byte boundary */ +#define RESERVED_FOR_PADDING (0x00000000U) + +__attribute__ ((section (".tfmv_tbl_top"))) const uint32_t tfmv_ver_tbl[] = { + [0x0000 / 4] = SECURE_FW_CHECK_FLAG, + [0x0004 / 4] = SECURE_FW_SW_VERSION, + [0x0008 / 4] = SECURE_FW_VER_OFFSET, + [0x0010 / 4] = RTOS_SW_CHECK_FLAG, + [0x0014 / 4] = RTOS_SW_SW_VERSION, + [0x0018 / 4] = RTOS_SW_VER_OFFSET, + [0x0020 / 4] = CX_2ND_IPL_CHECK_FLAG, + [0x0024 / 4] = CX_2ND_IPL_SW_VERSION, + [0x0028 / 4] = CX_2ND_IPL_VER_OFFSET, + [0x0030 / 4] = ICUMH_PROG_CHECK_FLAG, + [0x0034 / 4] = ICUMH_PROG_SW_VERSION, + [0x0038 / 4] = ICUMH_PROG_VER_OFFSET, + [0x0040 / 4] = G4MH_PROG_01_CHECK_FLAG, + [0x0044 / 4] = G4MH_PROG_01_SW_VERSION, + [0x0048 / 4] = G4MH_PROG_01_VER_OFFSET, + [0x0050 / 4] = G4MH_PROG_02_CHECK_FLAG, + [0x0054 / 4] = G4MH_PROG_02_SW_VERSION, + [0x0058 / 4] = G4MH_PROG_02_VER_OFFSET, + [0x0060 / 4] = CA_PROG_01_CHECK_FLAG, + [0x0064 / 4] = CA_PROG_01_SW_VERSION, + [0x0068 / 4] = CA_PROG_01_VER_OFFSET, + [0x0070 / 4] = CA_PROG_02_CHECK_FLAG, + [0x0074 / 4] = CA_PROG_02_SW_VERSION, + [0x0078 / 4] = CA_PROG_02_VER_OFFSET, + [0x007C / 4] = RESERVED_FOR_PADDING, /* Adjust to 16-byte boundary */ +}; + diff --git a/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/tfmv_ver_tbl.ld b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/tfmv_ver_tbl.ld new file mode 100644 index 0000000..b371a60 --- /dev/null +++ b/IPL/Customer/Mobis/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/tfmv_ver_tbl.ld @@ -0,0 +1,60 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : linker directive for TFMV Software minimum version table + ******************************************************************************/ +/****************************************************************************** + * @file tfmv_ver_tbl.ld + * - Version : 0.01 + * @brief linker directive for TFMV Software minimum version table. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.08.2022 0.01 First Release + *****************************************************************************/ + +DEFAULTS { + tbl_base_addr = 0xEB235000 + + tbl_size = 2K +} +MEMORY +{ + rt_sram : ORIGIN = tbl_base_addr, LENGTH = tbl_size +} +SECTIONS +{ +// +// TFMV Software minimum version table +// + _start = tbl_base_addr; + .tfmv_tbl_top ALIGN(1024) : > rt_sram + + .sdata : > . + .tdata : > . + .rosdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +} diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/Makefile b/IPL/Customer/Mobis/V4H_Cx_Loader/Makefile new file mode 100644 index 0000000..1af0d89 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/Makefile @@ -0,0 +1,593 @@ +#******************************************************************************* +# DISCLAIMER +# This software is supplied by Renesas Electronics Corporation and is only +# intended for use with Renesas products. No other uses are authorized. This +# software is owned by Renesas Electronics Corporation and is protected under +# all applicable laws, including copyright laws. +# THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +# THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +# LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +# AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +# TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +# ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +# FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +# ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +# BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +# Renesas reserves the right, without notice, to make changes to this software +# and to discontinue the availability of this software. By using this software, +# you agree to the additional terms and conditions found by accessing the +# following link: +# http://www.renesas.com/disclaimer +# Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +#******************************************************************************/ + + + +# ****************************************************************************** +# * DESCRIPTION : makefile for Loader +# ****************************************************************************** +# ****************************************************************************** +# * @file Makefile +# * - Version : 0.14 +# * @brief +# * . +# ****************************************************************************** +# ****************************************************************************** +# * History : DD.MM.YYYY Version Description +# * : 02.02.2022 0.01 First Release +# * : 17.02.2022 0.02 Support AArch32 +# * : 23.03.2022 0.03 Removed unnecessary functions +# * : 09.05.2022 0.04 Used the standard library +# * Renamed the image +# * Added make option "LSI" +# * Removed make option "AArch" +# * Changed to make common things common in LSI +# * : 17.06.2022 0.05 Support secure boot for S4 +# * : 02.08.2022 0.06 Support WDT +# * : 07.11.2022 0.07 Support DDR initialization/QOS initialization processing +# * : 14.12.2022 0.08 Fixed make option "EMMC_TRANS_MODE" +# * Support MMU +# * : 15.12.2022 0.09 Support RegionID check +# * Fixed "LSI" default settings +# * : 04.04.2023 0.10 Fixed not used standerd library. +# * : 21.08.2023 0.11 Add support for V4M. +# * : 04.09.2023 0.12 Add C4 power domain setting. +# * : 19.12.2024 0.13 Add build option "RTOS_LOAD_NUM" +# * Add build option "ECM_ERROR_ENABLE" +# * and "ECMERRTGTR_INTC". +# * : 26.05.2025 0.14 Add build option "OPTEE_LOAD_ENABLE" +# ****************************************************************************** + +################################################### +# makefile +################################################### + +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +INCLUDE_DIR = -Iinclude + +OUTDIR := build + +# LSI setting common define +RCAR_S4:=0 +RCAR_V4H:=1 +RCAR_V4M:=2 +NORMAL:=0 +SECURE:=1 +HS400:=0 +HS200:=1 +HIGH_SPEED:=2 +NO_HIGH_SPEED:=3 +$(eval $(call add_define,RCAR_S4)) +$(eval $(call add_define,RCAR_V4H)) +$(eval $(call add_define,RCAR_V4M)) +$(eval $(call add_define,NORMAL)) +$(eval $(call add_define,SECURE)) +$(eval $(call add_define,HS400)) +$(eval $(call add_define,HS200)) +$(eval $(call add_define,HIGH_SPEED)) +$(eval $(call add_define,NO_HIGH_SPEED)) +ifneq ("$(FORCE_115200)", "") +$(eval $(call add_define,FORCE_115200)) +endif +$(eval $(call add_define,MOBIS_PRK3)) + +#/* Select LSI("S4" or "V4H" or "V4M")*********************** +ifeq ("$(LSI)", "") +LSI = S4 +endif + +ifeq (${LSI},S4) + RCAR_LSI:=${RCAR_S4} + #output file name + FILE_NAME = ca55_loader +else ifeq (${LSI},V4H) + RCAR_LSI:=${RCAR_V4H} + #output file name + FILE_NAME = cr52_loader +else ifeq (${LSI},V4M) + RCAR_LSI:=${RCAR_V4M} + #output file name + FILE_NAME = cr52_loader +else + $(error "Error: ${LSI} is not supported.") +endif +$(eval $(call add_define,RCAR_LSI)) + +ifndef BOOT_MODE + BOOT_MODE:=${NORMAL} +else + ifeq (${BOOT_MODE},NORMAL) + BOOT_MODE:=${NORMAL} + else ifeq (${BOOT_MODE},SECURE) + BOOT_MODE:=${SECURE} + ifeq (${LSI},S4) + $(eval $(call add_define,TARGET_CORTEX_A)) + $(eval $(call add_define,TARGET_DEVICE_S4X)) + $(eval $(call add_define,AARCH64)) + else ifeq (${LSI},V4H) + $(eval $(call add_define,TARGET_DEVICE_V4H)) + else ifeq (${LSI},V4M) + $(eval $(call add_define,TARGET_DEVICE_V4M)) + endif + else + $(error "Error: ${BOOT_MODE} is not supported.") + endif + $(eval $(call add_define,BOOT_MODE)) +endif + +ifndef EMMC_TRANS_MODE + EMMC_TRANS_MODE:=${HS400} +else + ifeq (${EMMC_TRANS_MODE},HS400) + EMMC_TRANS_MODE:=${HS400} + else ifeq (${EMMC_TRANS_MODE},HS200) + EMMC_TRANS_MODE:=${HS200} + else ifeq (${EMMC_TRANS_MODE},HIGH_SPEED) + EMMC_TRANS_MODE:=${HIGH_SPEED} + else ifeq (${EMMC_TRANS_MODE},NO_HIGH_SPEED) + EMMC_TRANS_MODE:=${NO_HIGH_SPEED} + else + $(error "Error: ${EMMC_TRANS_MODE} is not supported.") + endif + $(eval $(call add_define,EMMC_TRANS_MODE)) +endif + +# Process RCAR_DRAM_SPLIT flag (V4H only) +ifeq (${LSI},V4H) + ifndef RCAR_DRAM_SPLIT + RCAR_DRAM_SPLIT := 1 + $(eval $(call add_define,RCAR_DRAM_SPLIT)) + else + ifeq (${RCAR_DRAM_SPLIT},0) + $(eval $(call add_define,RCAR_DRAM_SPLIT)) + else ifeq (${RCAR_DRAM_SPLIT},1) + $(eval $(call add_define,RCAR_DRAM_SPLIT)) + else + $(error "Error:RCAR_DRAM_SPLIT=${RCAR_DRAM_SPLIT} is not supported.") + endif + endif +else ifeq (${LSI},V4M) + ifndef RCAR_DRAM_SPLIT + RCAR_DRAM_SPLIT := 0 + $(eval $(call add_define,RCAR_DRAM_SPLIT)) + else + ifneq (${RCAR_DRAM_SPLIT},0) + $(error "Error:RCAR_DRAM_SPLIT=${RCAR_DRAM_SPLIT} is not supported.") + endif + endif +endif + +# Process RCAR_PERIODIC_WRITE_TRAINING flag +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef RCAR_PERIODIC_WRITE_TRAINING + RCAR_PERIODIC_WRITE_TRAINING := 1 + $(eval $(call add_define,RCAR_PERIODIC_WRITE_TRAINING)) + else + ifeq (${RCAR_PERIODIC_WRITE_TRAINING},0) + $(eval $(call add_define,RCAR_PERIODIC_WRITE_TRAINING)) + else ifeq (${RCAR_PERIODIC_WRITE_TRAINING},1) + $(eval $(call add_define,RCAR_PERIODIC_WRITE_TRAINING)) + else + $(error "Error:RCAR_PERIODIC_WRITE_TRAINING=${RCAR_PERIODIC_WRITE_TRAINING} is not supported.") + endif + endif +endif + +# Process RCAR_PERIODIC_READ_TRAINING flag +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef RCAR_PERIODIC_READ_TRAINING + RCAR_PERIODIC_READ_TRAINING := 1 + $(eval $(call add_define,RCAR_PERIODIC_READ_TRAINING)) + else + ifeq (${RCAR_PERIODIC_READ_TRAINING},0) + $(eval $(call add_define,RCAR_PERIODIC_READ_TRAINING)) + else ifeq (${RCAR_PERIODIC_READ_TRAINING},1) + $(eval $(call add_define,RCAR_PERIODIC_READ_TRAINING)) + else + $(error "Error:RCAR_PERIODIC_READ_TRAINING=${RCAR_PERIODIC_READ_TRAINING} is not supported.") + endif + endif +endif + +# Process DBSC_REFINTS flag +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef DBSC_REFINTS + DBSC_REFINTS := 0 + $(eval $(call add_define,DBSC_REFINTS)) + else + ifeq (${DBSC_REFINTS},0) + $(eval $(call add_define,DBSC_REFINTS)) + else ifeq (${DBSC_REFINTS},1) + $(eval $(call add_define,DBSC_REFINTS)) + else + $(error "Error:DBSC_REFINTS=${DBSC_REFINTS} is not supported.") + endif + endif +endif + +# Process RTVRAM_EXTEND flag +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef RTVRAM_EXTEND + RTVRAM_EXTEND := 1 + $(eval $(call add_define,RTVRAM_EXTEND)) + else + ifeq (${RTVRAM_EXTEND},0) + $(eval $(call add_define,RTVRAM_EXTEND)) + else ifeq (${RTVRAM_EXTEND},1) + $(eval $(call add_define,RTVRAM_EXTEND)) + else + $(error "Error:RTVRAM_EXTEND=${RTVRAM_EXTEND} is not supported.") + endif + endif +endif + +# timing measurement +ifeq ("$(MEASURE_TIME)", "") + MEASURE_TIME = 0 +else + $(eval $(call add_define,MEASURE_TIME)) + # Set log level to Error, so we dont waste time with unnecessary prints + LOG_LEVEL := 1 + OBJ_FILE += \ + common/scmt_checkpoint.o \ + common/timer/scmt.o +endif + +# Process BL2_LOAD_ENABLE flag +ifeq (${LSI},V4H) + ifndef BL2_LOAD_ENABLE + BL2_LOAD_ENABLE := 1 + $(eval $(call add_define,BL2_LOAD_ENABLE)) + else + ifeq (${BL2_LOAD_ENABLE},0) + $(eval $(call add_define,BL2_LOAD_ENABLE)) + else ifeq (${BL2_LOAD_ENABLE},1) + $(eval $(call add_define,BL2_LOAD_ENABLE)) + else + $(error "Error:BL2_LOAD_ENABLE=${BL2_LOAD_ENABLE} is not supported.") + endif + endif +endif + +# Process QNX_OS_LOAD_ENABLE flag +ifeq (${LSI},V4H) + ifndef QNX_OS_LOAD_ENABLE + QNX_OS_LOAD_ENABLE := 1 + $(eval $(call add_define,QNX_OS_LOAD_ENABLE)) + else + ifeq (${QNX_OS_LOAD_ENABLE},0) + $(eval $(call add_define,QNX_OS_LOAD_ENABLE)) + else ifeq (${QNX_OS_LOAD_ENABLE},1) + $(eval $(call add_define,QNX_OS_LOAD_ENABLE)) + else + $(error "Error:QNX_OS_LOAD_ENABLE=${QNX_OS_LOAD_ENABLE} is not supported.") + endif + endif +endif + +# Process RTOS_LOAD_NUM flag +# 1:RTOS#0 only 3:RTOS#0,#1,#2 +ifndef RTOS_LOAD_NUM + RTOS_LOAD_NUM := 1 + $(eval $(call add_define,RTOS_LOAD_NUM)) +else + ifeq (${RTOS_LOAD_NUM},1) + $(eval $(call add_define,RTOS_LOAD_NUM)) + else ifeq (${RTOS_LOAD_NUM},3) + $(eval $(call add_define,RTOS_LOAD_NUM)) + else + $(error "Error:RTOS_LOAD_NUM=${RTOS_LOAD_NUM} is not supported.") + endif +endif + +# Process OPTEE_LOAD_ENABLE flag +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef OPTEE_LOAD_ENABLE + OPTEE_LOAD_ENABLE := 1 + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else + ifeq (${OPTEE_LOAD_ENABLE},0) + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else ifeq (${OPTEE_LOAD_ENABLE},1) + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else + $(error "Error:OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.") + endif + endif +endif + +OUTPUT_FILE = $(FILE_NAME).elf + +# object file name +OBJ_FILE += common/string.o \ + common/log/log.o \ + common/log/scif.o \ + common/timer/generic_timer.o \ + image_load/image_load.o \ + ip/ip_control.o \ + ip/emmc/emmc_boot.o \ + ip/emmc/emmc_cmd.o \ + ip/emmc/emmc_init.o \ + ip/emmc/emmc_interrupt.o \ + ip/emmc/emmc_mount.o \ + ip/emmc/emmc_multiboot.o \ + ip/emmc/emmc_read.o \ + ip/emmc/emmc_utility.o \ + loader/stack.o \ + loader/loader_main.o \ + ip/interrupt.o + +ifeq (${BOOT_MODE},SECURE) +OBJ_FILE += secure/secure_boot.o \ + secure/src/comm_drv/icum_d_comm_pe.o \ + secure/src/icumif_lib/r_icumif.o \ + secure/shared/src/mem_info_def.o \ + secure/user_api/user_icumif_api.o + +INCLUDE_DIR += -Isecure/src/comm_drv -Isecure/src/icumif_lib -Isecure/icumif -Isecure/include -Isecure/user_api -Isecure/shared/src + +endif + +ifeq (${LSI},S4) + OBJ_FILE += \ + loader/loader_s4.o \ + ip/swdt/swdt.o \ + loader/loader_mmu_table.o \ + loader/loader_exceptions.o + #linker script name + MEMORY_DEF = loader/loader_s4.ld +else ifeq (${LSI},V4H) + OBJ_FILE += \ + cpu_on/cpu_on.o \ + ip/qos/qos.o \ + cnf_tbl/cnf_tbl_v4h.o \ + ip/rtvram/rtvram.o \ + loader/loader_v4h.o \ + loader/loader_main_common.o \ + protect/region_id/region_id.o \ + cnf_tbl/rgidcnf_tbl_v4h.o \ + ip/ddr/v4h/lpddr5/ecc_enable_v4h.o \ + ip/ddr/v4h/lpddr5/ecm_enable_v4h.o + #linker script name + MEMORY_DEF = loader/loader_v4h.ld + + INCLUDE_DIR += -Iip/ddr +else ifeq (${LSI},V4M) + OBJ_FILE += \ + cpu_on/cpu_on.o \ + ip/qos/qos.o \ + cnf_tbl/cnf_tbl_v4m.o \ + ip/rtvram/rtvram.o \ + loader/loader_v4m.o \ + loader/loader_main_common.o \ + protect/region_id/region_id.o \ + cnf_tbl/rgidcnf_tbl_v4m.o \ + ip/ddr/v4m/lpddr5/ecc_enable_v4m.o \ + ip/ddr/v4m/lpddr5/ecm_enable_v4m.o + #linker script name + MEMORY_DEF = loader/loader_v4m.ld + + INCLUDE_DIR += -Iip/ddr + +endif + +################################################### +# Process access protection flag +# 0:Disable 1:Enable +ifndef ACC_PROT_ENABLE +ACC_PROT_ENABLE := 0 +$(eval $(call add_define,ACC_PROT_ENABLE)) +else + ifeq (${ACC_PROT_ENABLE},0) + $(eval $(call add_define,ACC_PROT_ENABLE)) + else ifeq (${ACC_PROT_ENABLE},1) + $(eval $(call add_define,ACC_PROT_ENABLE)) + else + $(error "Error:ACC_PROT_ENABLE=${ACC_PROT_ENABLE} is not supported.") + endif +endif + +# Debug build +DEBUG:=0 + +# Process DEBUG flag +$(eval $(call assert_boolean,DEBUG)) +$(eval $(call add_define,DEBUG)) +ifeq (${DEBUG},0) + $(eval $(call add_define,NDEBUG)) +else + CFLAGS += -g + ASFLAGS += -g -Wa,--gdwarf-2 +endif + +# booting performance check +ifeq ("$(BOOT_TIME_CHECK)", "") +BOOT_TIME_CHECK = 0 +endif +$(eval $(call add_define,BOOT_TIME_CHECK)) +ifneq (${BOOT_TIME_CHECK},0) +OBJ_FILE += ip/gpio/gpio.o +endif + +# Process LOG_LEVEL +ifndef LOG_LEVEL +LOG_LEVEL := 2 +endif +$(eval $(call add_define,LOG_LEVEL)) + +# Process ECC_ENABLE +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef ECC_ENABLE + ECC_ENABLE:= 0 + $(eval $(call add_define,ECC_ENABLE)) + else + ifeq (${ECC_ENABLE},0) + $(eval $(call add_define,ECC_ENABLE)) + else ifeq (${ECC_ENABLE},1) + $(eval $(call add_define,ECC_ENABLE)) + else + $(error "Error: ECC_ENABLE=${ECC_ENABLE} is not supported.") + endif + endif +endif + +# Process ECM_ERROR_ENABLE flag +ifndef ECM_ERROR_ENABLE + ECM_ERROR_ENABLE := 1 + $(eval $(call add_define,ECM_ERROR_ENABLE)) +else + ifeq (${ECM_ERROR_ENABLE},0) + $(eval $(call add_define,ECM_ERROR_ENABLE)) + else ifeq (${ECM_ERROR_ENABLE},1) + $(eval $(call add_define,ECM_ERROR_ENABLE)) + else + $(error "Error:ECM_ERROR_ENABLE=${ECM_ERROR_ENABLE} is not supported.") + endif +endif + +# Process ECMERRTGTR_INTC flag +ifndef ECMERRTGTR_INTC + ECMERRTGTR_INTC := 1 + $(eval $(call add_define,ECMERRTGTR_INTC)) +else + ifeq (${ECMERRTGTR_INTC},0) + $(eval $(call add_define,ECMERRTGTR_INTC)) + else ifeq (${ECMERRTGTR_INTC},1) + $(eval $(call add_define,ECMERRTGTR_INTC)) + else + $(error "Error:ECMERRTGTR_INTC=${ECMERRTGTR_INTC} is not supported.") + endif +endif + +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + include ip/ddr/ddr.mk +endif + +# Process DBSC HUNGUP WA +ifndef WA_OTLINT5579 + WA_OTLINT5579:= 1 +endif +$(eval $(call add_define,WA_OTLINT5579)) + +# Private Option for QoS and DBSC +RCAR_PERIODIC_TRAINING_SEPARATE_MODE:= 0 +$(eval $(call add_define,RCAR_PERIODIC_TRAINING_SEPARATE_MODE)) + +################################################### + +OUTDIR_REL := $(OUTDIR)/release +OUTDIR_OBJ := $(OUTDIR)/obj + +OBJ_FILE := $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o) + +CC = $(CROSS_COMPILE)gcc +CPP = ${CROSS_COMPILE}cpp +AS = ${CROSS_COMPILE}gcc +AR = ${CROSS_COMPILE}ar +LD = $(CROSS_COMPILE)ld +OC = ${CROSS_COMPILE}objcopy +OD = ${CROSS_COMPILE}objdump + +ifeq (${LSI},S4) +ASFLAGS += -march=armv8.2-a +CFLAGS += -march=armv8.2-a \ + -O0 +else ifeq ($(filter ${LSI},V4H V4M),${LSI}) +ASFLAGS += -march=armv8-r +CFLAGS += -march=armv8-r \ + -O2 +endif + +ASFLAGS += -ffreestanding -Wa,--fatal-warnings \ + -Wmissing-include-dirs \ + -c -D__ASSEMBLY \ + $(INCLUDE_DIR) $(DEFINES) + +CFLAGS += -ffreestanding -Wall \ + -Wmissing-include-dirs \ + -std=c99 -c \ + -D__CX_IPL__ \ + $(INCLUDE_DIR) $(DEFINES) + +#LDFLAGS = --fatal-warnings -O1 -nostdlib +LDFLAGS = --fatal-warnings -O1 -lm + +BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__ + +LIBS = -L$(subst libc.a, ,$(shell $(CC) -print-file-name=libc.a 2> /dev/null)) -lc +LIBS += -L$(subst libgcc.a, ,$(shell $(CC) -print-libgcc-file-name 2> /dev/null)) -lgcc + +################################################### +.SUFFIXES : .s .c .o + +################################################### +# command + +.PHONY: all +all: $(OUTPUT_FILE) + +################################################### +# Linker +################################################### +$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE) + @echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' | \ + $(CC) $(CFLAGS) -xc - -o $(OUTDIR_OBJ)/build_message.o + @if [ ! -e "$(OUTDIR_REL)" ]; then mkdir "$(OUTDIR_REL)"; fi + + $(V)$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \ + -T $(MEMORY_DEF) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE) \ + $(LDFLAGS) \ + -Map $(OUTDIR_REL)/$(FILE_NAME).map \ + $(LIBS) + + $(V)$(OC) -O srec --srec-forceS3 $(OUTDIR_REL)/$(OUTPUT_FILE) $(OUTDIR_REL)/$(FILE_NAME).srec + $(V)$(OC) -O binary $(OUTDIR_REL)/$(OUTPUT_FILE) $(OUTDIR_REL)/$(FILE_NAME).bin + $(V)$(OD) -dx $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump + + @chmod 644 $(OUTDIR_REL)/$(FILE_NAME).* +ifneq ("$(V)", "") + @echo "Build complete: $(OUTPUT_FILE)" + @echo "Output files:" + @echo " - $(OUTDIR_REL)/$(FILE_NAME).srec" +endif + +################################################### +# Compile +################################################### + +$(OUTDIR_OBJ)/%.o:%.c + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + $(V)$(CC) $(CFLAGS) -o $@ -c $< + +$(OUTDIR_OBJ)/%.o:%.S + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + $(V)$(AS) $(ASFLAGS) -o $@ -c $< + + +.PHONY: clean +clean: + @rm -rf $(OUTDIR) diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4h.c b/IPL/Customer/Mobis/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4h.c new file mode 100644 index 0000000..18942e6 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4h.c @@ -0,0 +1,323 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table + ******************************************************************************/ +/****************************************************************************** + * @file cnf_tbl.c + * - Version : 0.04 + * @brief Configuration table for V4H. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 23.05.2022 0.02 Integration of S4 and V4H + * Renamed from conf_tbl.c to cnf_tbl_v4h.c. + * : 22.05.2023 0.03 Update the qos config table for response to past + * follow back. + * : 08.06.2023 0.04 Update the qos config table for ISP and VSPX. + *****************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include +#endif +#include + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".qosbw_tbl" +#else +__attribute__ ((section(".qoswt_tbl"))) +#endif +const QOS_SETTING_TABLE g_qosbw_tbl[] = { + [0] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [1] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [2] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [3] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [4] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [5] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [6] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [7] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [8] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [9] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [10] = {0x000C04010000FFFFULL, 0x0000000000000000ULL}, + [11] = {0x000C04080000FFFFULL, 0x00200030004FFC01ULL}, + [12] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [13] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [14] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [15] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [16] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [17] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [18] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [19] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [20] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [21] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [22] = {0x000C04100000FFFFULL, 0x0000000000000000ULL}, + [23] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL}, + [24] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL}, + [25] = {0x000000000000FFF0ULL, 0x0000000000000000ULL}, + [26] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [27] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [28] = {0x000C04100000FFFFULL, 0x0000000000000000ULL}, + [29] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [30] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL}, + [31] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [32] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [33] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [34] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [35] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [36] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [37] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [38] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [39] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [40] = {0x000C04010000FFFFULL, 0x001000F0004FFC01ULL}, + [41] = {0x000C04010000FFFFULL, 0x001000F0004FFC01ULL}, + [42] = {0x000C04010000FFFFULL, 0x002000F0004FFC01ULL}, + [43] = {0x000C04010000FFFFULL, 0x002000F0004FFC01ULL}, + [44] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [45] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [46] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [47] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [48] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [49] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [50] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [51] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [52] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [53] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [54] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [55] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [56] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [57] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [58] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [59] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [60] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [61] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [62] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [63] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [64] = {0x000C04200000FFFFULL, 0x00100030004FFC01ULL}, + [65] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [66] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [67] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [68] = {0x000C0C4F0000FFFFULL, 0x00100030004FFC01ULL}, + [69] = {0x000C0C4F0000FFFFULL, 0x00100030004FFC01ULL}, + [70] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [71] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [72] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [73] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [74] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL}, + [75] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL}, + [76] = {0x000C149E0000FFFFULL, 0x00100030004FFC01ULL}, + [77] = {0x000C149E0000FFFFULL, 0x00100030004FFC01ULL}, + [78] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [79] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [80] = {0x00140C050000FFFFULL, 0x00100030004FFC01ULL}, + [81] = {0x0014450E0000FFFFULL, 0x00100030004FFC01ULL}, + [82] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL}, + [83] = {0x0014289E0000FFFFULL, 0x00000000000FFC00ULL}, + [84] = {0x0014289E0000FFFFULL, 0x00000000000FFC00ULL}, + [85] = {0x0014149E0000FFFFULL, 0x0000000000000000ULL}, + [86] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [87] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [88] = {0x001004080000FFFFULL, 0x0000000000000000ULL}, + [89] = {0x001004080000FFFFULL, 0x0000000000000000ULL}, + [90] = {0x001004080000FFFFULL, 0x0000000000000000ULL}, + [91] = {0x000C00000000FFFFULL, 0x001000F0004FFC01ULL}, + [92] = {0x000C00000000FFFFULL, 0x001000F0004FFC01ULL}, + [93] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [94] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [95] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [96] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [97] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [98] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [99] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [100] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [101] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [102] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [103] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [104] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [105] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [106] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [107] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [108] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [109] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [110] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [111] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [112] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [113] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [114] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [115] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [116] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [117] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [118] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [119] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [120] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [121] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [122] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [123] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [124] = {0x001404010000FFFFULL, 0x00100030004FFC01ULL} +}; + + +/* Now go back to default rules */ +#if defined(__RH850G3K__) +#pragma ghs section rodata=default + +#pragma ghs section rodata=".qoswt_tbl" +#else +__attribute__ ((section(".qosbw_tbl"))) +#endif +const QOS_SETTING_TABLE g_qoswt_tbl[] = { + [0] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [1] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [2] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [3] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [4] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [5] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [6] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [7] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [8] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [9] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [10] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [11] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [12] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [13] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [14] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [15] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [16] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [17] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [18] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [19] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [20] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [21] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [22] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [23] = {0x000C04050000FFFFULL, 0x0000000000000000ULL}, + [24] = {0x000C080C0000FFFFULL, 0x0000000000000000ULL}, + [25] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [26] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [27] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [28] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [29] = {0x000C04050000C001ULL, 0x0000000000000000ULL}, + [30] = {0x000C080C0000C001ULL, 0x0000000000000000ULL}, + [31] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [32] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [33] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [34] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [35] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [36] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [37] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [38] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [39] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [40] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [41] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [42] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [43] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [44] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [45] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [46] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [47] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [48] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [49] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [50] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [51] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [52] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [53] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [54] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [55] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [56] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [57] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [58] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [59] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [60] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [61] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [62] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [63] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [64] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [65] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [66] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [67] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [68] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [69] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [70] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [71] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [72] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [73] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [74] = {0x001424870000C001ULL, 0x0000000000000000ULL}, + [75] = {0x001424870000C001ULL, 0x0000000000000000ULL}, + [76] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [77] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [78] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [79] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [80] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [81] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [82] = {0x001424870000FFFFULL, 0x0000000000000000ULL}, + [83] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [84] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [85] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [86] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [87] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [88] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [89] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [90] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [91] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [92] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [93] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [94] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [95] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [96] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [97] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [98] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [99] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [100] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [101] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [102] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [103] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [104] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [105] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [106] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [107] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [108] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [109] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [110] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [111] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [112] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [113] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [114] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [115] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [116] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [117] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [118] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [119] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [120] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [121] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [122] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [123] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [124] = {0x0000000000000000ULL, 0x0000000000000000ULL} +}; + + +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4m.c b/IPL/Customer/Mobis/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4m.c new file mode 100644 index 0000000..7a3e6cd --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4m.c @@ -0,0 +1,318 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table + ******************************************************************************/ +/****************************************************************************** + * @file cnf_tbl_v4m.c + * - Version : 0.01 + * @brief Configuration table for V4M. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + *****************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include +#endif +#include + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".qosbw_tbl" +#else +__attribute__ ((section(".qoswt_tbl"))) +#endif +const QOS_SETTING_TABLE g_qosbw_tbl[] = { + [0] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [1] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [2] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [3] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [4] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [5] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [6] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [7] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [8] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [9] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [10] = {0x000C04010000FFFFULL, 0x0000000000000000ULL}, + [11] = {0x000C04080000FFFFULL, 0x00200030004FFC01ULL}, + [12] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [13] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [14] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [15] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [16] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [17] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [18] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [19] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [20] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [21] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [22] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [23] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL}, + [24] = {0x0000000000000000ULL, 0x00100030004FFC01ULL}, + [25] = {0x000000000000FFF0ULL, 0x0000000000000000ULL}, + [26] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [27] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [28] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [29] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [30] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL}, + [31] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [32] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [33] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [34] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [35] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [36] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [37] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [38] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [39] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [40] = {0x000C04010000FFFFULL, 0x001000F0004FFC01ULL}, + [41] = {0x000C04010000FFFFULL, 0x001000F0004FFC01ULL}, + [42] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [43] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [44] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [45] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [46] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [47] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [48] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [49] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [50] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [51] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [52] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [53] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [54] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [55] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [56] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [57] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [58] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [59] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [60] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [61] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [62] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [63] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [64] = {0x000C04200000FFFFULL, 0x00100030004FFC01ULL}, + [65] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [66] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [67] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [68] = {0x000C0C4F0000FFFFULL, 0x00100030004FFC01ULL}, + [69] = {0x000C0C4F0000FFFFULL, 0x00100030004FFC01ULL}, + [70] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [71] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [72] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [73] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [74] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL}, + [75] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL}, + [76] = {0x000C149E0000FFFFULL, 0x00100030004FFC01ULL}, + [77] = {0x000C149E0000FFFFULL, 0x00100030004FFC01ULL}, + [78] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [79] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [80] = {0x00140C050000FFFFULL, 0x00100030004FFC01ULL}, + [81] = {0x0014450E0000FFFFULL, 0x00100030004FFC01ULL}, + [82] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL}, + [83] = {0x0014289E0000FFFFULL, 0x00000000000FFC00ULL}, + [84] = {0x0014289E0000FFFFULL, 0x00000000000FFC00ULL}, + [85] = {0x0014149E0000FFFFULL, 0x0000000000000000ULL}, + [86] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [87] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [88] = {0x001004080000FFFFULL, 0x0000000000000000ULL}, + [89] = {0x001004080000FFFFULL, 0x0000000000000000ULL}, + [90] = {0x001004080000FFFFULL, 0x0000000000000000ULL}, + [91] = {0x000C00000000FFFFULL, 0x001000F0004FFC01ULL}, + [92] = {0x000C00000000FFFFULL, 0x001000F0004FFC01ULL}, + [93] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [94] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [95] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [96] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [97] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [98] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [99] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [100] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [101] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [102] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [103] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [104] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [105] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [106] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [107] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [108] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [109] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [110] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [111] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [112] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [113] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [114] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [115] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [116] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [117] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [118] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [119] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [120] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [121] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [122] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [123] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [124] = {0x001404010000FFFFULL, 0x00100030004FFC01ULL} +}; + + +/* Now go back to default rules */ +#if defined(__RH850G3K__) +#pragma ghs section rodata=default + +#pragma ghs section rodata=".qoswt_tbl" +#else +__attribute__ ((section(".qosbw_tbl"))) +#endif +const QOS_SETTING_TABLE g_qoswt_tbl[] = { + [0] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [1] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [2] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [3] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [4] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [5] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [6] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [7] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [8] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [9] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [10] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [11] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [12] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [13] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [14] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [15] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [16] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [17] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [18] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [19] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [20] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [21] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [22] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [23] = {0x000C04050000FFFFULL, 0x0000000000000000ULL}, + [24] = {0x000C080C0000FFFFULL, 0x0000000000000000ULL}, + [25] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [26] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [27] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [28] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [29] = {0x000C04050000C001ULL, 0x0000000000000000ULL}, + [30] = {0x000C080C0000C001ULL, 0x0000000000000000ULL}, + [31] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [32] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [33] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [34] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [35] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [36] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [37] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [38] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [39] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [40] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [41] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [42] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [43] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [44] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [45] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [46] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [47] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [48] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [49] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [50] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [51] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [52] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [53] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [54] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [55] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [56] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [57] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [58] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [59] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [60] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [61] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [62] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [63] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [64] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [65] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [66] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [67] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [68] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [69] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [70] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [71] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [72] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [73] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [74] = {0x001424870000C001ULL, 0x0000000000000000ULL}, + [75] = {0x001424870000C001ULL, 0x0000000000000000ULL}, + [76] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [77] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [78] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [79] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [80] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [81] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [82] = {0x001424870000FFFFULL, 0x0000000000000000ULL}, + [83] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [84] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [85] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [86] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [87] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [88] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [89] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [90] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [91] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [92] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [93] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [94] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [95] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [96] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [97] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [98] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [99] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [100] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [101] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [102] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [103] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [104] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [105] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [106] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [107] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [108] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [109] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [110] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [111] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [112] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [113] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [114] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [115] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [116] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [117] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [118] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [119] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [120] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [121] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [122] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [123] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [124] = {0x0000000000000000ULL, 0x0000000000000000ULL} +}; + + +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4h.c b/IPL/Customer/Mobis/V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4h.c new file mode 100644 index 0000000..f0d1dee --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4h.c @@ -0,0 +1,3434 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table + ******************************************************************************/ +/****************************************************************************** + * @file rgidcnf_tbl_v4h.c + * - Version : 0.07 + * @brief Configuration table for V4H. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 16.12.2022 0.01 First Release + * : 23.01.2023 0.02 Added RAM protection table. + * Update Region ID settings. + * : 07.02.2024 0.03 Update System RAM protection setting Area0. + * : 30.08.2024 0.04 Updated Region ID and RAM protection setting + * for QNX. + * : 05.12.2024 0.05 Update RAM protection settings for ICCOM + * memory area (SDRAM Area5). + * Update Region ID settings for VSPD and VSPX. + * Update Region ID settings for IPMMU. + * Update RAM protection setting. + * : 16.12.2024 0.06 Updated Region ID setting. + * Updated Region ID setting and RAM protection + * setting for booting CR52 3 cores. + * Added IMP Region ID table. + * Added IPMMU Region ID table. + * : 26.05.2025 0.07 Updated RAM protection settings for + * protection area. + *****************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include +#endif +#include +#include +#include "ram_protection.h" + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_m_tbl" +#else +__attribute__ ((section(".rgid_m_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_master_tbl[] = { + [0] = {0xE6581000U, 0x00000002U}, /* RGIDM_MODID[0]:PCI0 */ + [1] = {0xE6581020U, 0x00000002U}, /* RGIDM_MODID[1]:PCI1 */ + [2] = {0xE6581024U, 0x00000002U}, /* RGIDM_MODID[2]:PCI2 */ + [3] = {0xE6581034U, 0x00000002U}, /* RGIDM_MODID[3]:PCI3 */ + [4] = {0xE6581010U, 0x00000002U}, /* RGIDM_MODID[4]:AVB0 */ + [5] = {0xE6581014U, 0x00000001U}, /* RGIDM_MODID[5]:AVB1 */ + [6] = {0xE6581018U, 0x00000001U}, /* RGIDM_MODID[6]:AVB2 */ + [7] = {0xE6581040U, 0x00000002U}, /* RGIDM_MODID[7]:TSN */ + [8] = {0xE6621004U, 0x00000000U}, /* RGIDM_MODID[8]:CR0 */ + [9] = {0xE662100CU, 0x00000000U}, /* RGIDM_MODID[9]:DCLS_ICUMX */ + [10] = {0xE6621010U, 0x00000000U}, /* RGIDM_MODID[10]:ICUMX */ + [11] = {0xE6621014U, 0x00000000U}, /* RGIDM_MODID[11]:SDMAC_ICUMX */ + [12] = {0xFFC41018U, 0x00000001U}, /* RGIDM_MODID[12]:CR52SS0 */ + [13] = {0xFFC4105CU, 0x00000001U}, /* RGIDM_MODID[13]:CR52SS1 */ + [14] = {0xFFC41060U, 0x00000006U}, /* RGIDM_MODID[14]:CR52SS2 */ + [15] = {0xFFC4101CU, 0x00000003U}, /* RGIDM_MODID[15]:CSD */ + [16] = {0xFFC41024U, 0x00000002U}, /* RGIDM_MODID[16]:INTAP0 */ + [17] = {0xFF861018U, 0x00000002U}, /* RGIDM_MODID[17]:FBABUSTOP0 */ + [18] = {0xFF86101CU, 0x00000002U}, /* RGIDM_MODID[18]:FBABUSTOP1 */ + [19] = {0xE7751020U, 0x00000002U}, /* RGIDM_MODID[19]:SDHI0 */ + [20] = {0xE7751010U, 0x00000001U}, /* RGIDM_MODID[20]:FRAY */ + [21] = {0xE7751014U, 0x00000002U}, /* RGIDM_MODID[21]:IPC */ + [22] = {0xFF811000U, 0x00000002U}, /* RGIDM_MODID[22]:AXMM2AXSTM */ + [23] = {0xFF811004U, 0x00000003U}, /* RGIDM_MODID[23]:CSDE0 */ + [24] = {0xFF811008U, 0x00000003U}, /* RGIDM_MODID[24]:CSDE1 */ + [25] = {0xFF881004U, 0x00000002U}, /* RGIDM_MODID[25]:FBABUSIR0 */ + [26] = {0xFF881008U, 0x00000002U}, /* RGIDM_MODID[26]:FBABUSIR1 */ + [27] = {0xFF88100CU, 0x00000002U}, /* RGIDM_MODID[27]:FBABUSIR2 */ + [28] = {0xFF881010U, 0x00000002U}, /* RGIDM_MODID[28]:FBABUSIR3 */ + [29] = {0xFF881014U, 0x00000002U}, /* RGIDM_MODID[29]:FBABUSIR4 */ + [30] = {0xFD811014U, 0x00000002U}, /* RGIDM_MODID[30]:RGX0 */ + [31] = {0xFE681004U, 0x00000002U}, /* RGIDM_MODID[31]:FBABUSVC */ + [32] = {0xFE681008U, 0x00000005U}, /* RGIDM_MODID[32]:FCPCS */ + [33] = {0xFE681010U, 0x00000002U}, /* RGIDM_MODID[33]:IMR00 */ + [34] = {0xFE681014U, 0x00000002U}, /* RGIDM_MODID[34]:IMR01 */ + [35] = {0xFE681024U, 0x00000002U}, /* RGIDM_MODID[35]:IMR10 */ + [36] = {0xFE681028U, 0x00000002U}, /* RGIDM_MODID[36]:IMR11 */ + [37] = {0xFE68100CU, 0x00000002U}, /* RGIDM_MODID[37]:IMR20 */ + [38] = {0xFE681018U, 0x00000002U}, /* RGIDM_MODID[38]:IMR21 */ + [39] = {0xFE681040U, 0x00000002U}, /* RGIDM_MODID[39]:IMS0 */ + [40] = {0xFE681044U, 0x00000002U}, /* RGIDM_MODID[40]:IMS1 */ + [41] = {0xFE681048U, 0x00000005U}, /* RGIDM_MODID[41]:IV1ES */ + [42] = {0xFEBE1000U, 0x00000002U}, /* RGIDM_MODID[42]:DSITLINK0 */ + [43] = {0xFEBE1004U, 0x00000002U}, /* RGIDM_MODID[43]:DSTLINK1 */ + [44] = {0xFEBE1008U, 0x00000002U}, /* RGIDM_MODID[44]:FBABUSVIO */ + [45] = {0xFEBE1014U, 0x00000002U}, /* RGIDM_MODID[45]:FCPVD0 */ + [46] = {0xFEBE1018U, 0x00000002U}, /* RGIDM_MODID[46]:FCPVD1 */ + [47] = {0xFEBE101CU, 0x00000002U}, /* RGIDM_MODID[47]:FCPVX0 */ + [48] = {0xFEBE1020U, 0x00000002U}, /* RGIDM_MODID[48]:FCPVX1 */ + [49] = {0xFEBF1020U, 0x00000002U}, /* RGIDM_MODID[49]:ISP00 */ + [50] = {0xFEBF1024U, 0x00000002U}, /* RGIDM_MODID[50]:ISP01 */ + [51] = {0xFEBF1000U, 0x00000002U}, /* RGIDM_MODID[51]:ISP02 */ + [52] = {0xFEBF1004U, 0x00000002U}, /* RGIDM_MODID[52]:ISP03 */ + [53] = {0xFEBF1008U, 0x00000002U}, /* RGIDM_MODID[53]:ISP04 */ + [54] = {0xFEBF1028U, 0x00000002U}, /* RGIDM_MODID[54]:ISP10 */ + [55] = {0xFEBF102CU, 0x00000002U}, /* RGIDM_MODID[55]:ISP11 */ + [56] = {0xFEBF1044U, 0x00000002U}, /* RGIDM_MODID[56]:ISP12 */ + [57] = {0xFEBF104CU, 0x00000002U}, /* RGIDM_MODID[57]:ISP13 */ + [58] = {0xFEBF1050U, 0x00000002U}, /* RGIDM_MODID[58]:ISP14 */ + [59] = {0xFEBF1010U, 0x00000002U}, /* RGIDM_MODID[59]:VIN0 */ + [60] = {0xFEBF1014U, 0x00000002U}, /* RGIDM_MODID[60]:VIN1 */ + [61] = {0xE7B11004U, 0x00000002U}, /* RGIDM_MODID[61]:FBABUSVIP0 */ + [62] = {0xE7B11010U, 0x00000002U}, /* RGIDM_MODID[62]:SMPO */ + [63] = {0xE7B11018U, 0x00000002U}, /* RGIDM_MODID[63]:SMPS */ + [64] = {0xE7B1101CU, 0x00000002U}, /* RGIDM_MODID[64]:UMFL */ + [65] = {0xE7B41018U, 0x00000002U}, /* RGIDM_MODID[65]:PAP */ + [66] = {0xE7B41028U, 0x00000002U}, /* RGIDM_MODID[66]:FBABUSVIP1 */ + [67] = {0xEB801000U, 0x00000002U}, /* RGIDM_MODID[67]:DSP00 */ + [68] = {0xEB801004U, 0x00000002U}, /* RGIDM_MODID[68]:DSP01 */ + [69] = {0xEB801008U, 0x00000002U}, /* RGIDM_MODID[69]:DSP10 */ + [70] = {0xEB80100CU, 0x00000002U}, /* RGIDM_MODID[70]:DSP11 */ + [71] = {0xEB801010U, 0x00000002U}, /* RGIDM_MODID[71]:DSP20 */ + [72] = {0xEB801014U, 0x00000002U}, /* RGIDM_MODID[72]:DSP21 */ + [73] = {0xEB801018U, 0x00000002U}, /* RGIDM_MODID[73]:DSP30 */ + [74] = {0xEB80101CU, 0x00000002U}, /* RGIDM_MODID[74]:DSP31 */ + [75] = {0xE67BF500U, 0x0000000EU}, /* RGIDM_MODID[75]:VRAM_R */ + [76] = {0xE67BF504U, 0x0000000EU}, /* RGIDM_MODID[76]:VRAM_W */ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_r_tbl" +#else +__attribute__ ((section(".rgid_r_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_read_tbl[] = { + [0] = {0xFFC82000U, 0x0000000FU}, /* RGIDR_MODID[0]:ARMGC0*/ + [1] = {0xFFC82004U, 0x0000000FU}, /* RGIDR_MODID[1]:ARMGC1*/ + [2] = {0xFFC82008U, 0x00000000U}, /* RGIDR_MODID[2]:ARMGC2*/ + [3] = {0xFFC8200CU, 0x0000000FU}, /* RGIDR_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDR_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDR_MODID[5]:ARRT02*/ + [4] = {0xFFC82018U, 0x0000000FU}, /* RGIDR_MODID[6]:ARRT03*/ + [5] = {0xFFC8201CU, 0x0000000FU}, /* RGIDR_MODID[7]:ARRT04*/ + [6] = {0xFFC82020U, 0x0000000FU}, /* RGIDR_MODID[8]:ARRT05*/ + [7] = {0xFFC82024U, 0x0000000FU}, /* RGIDR_MODID[9]:ARRT06*/ + [8] = {0xFFC82028U, 0x0000000FU}, /* RGIDR_MODID[10]:ARRT07*/ + [9] = {0xFFC8202CU, 0x00000000U}, /* RGIDR_MODID[11]:ARRT08*/ + [10] = {0xFFC82030U, 0x00000001U}, /* RGIDR_MODID[12]:LIFEC0*/ + [11] = {0xFFC82034U, 0x0000000EU}, /* RGIDR_MODID[13]:SWDT*/ + [12] = {0xFFC82038U, 0x0000006EU}, /* RGIDR_MODID[14]:TMU0*/ + [13] = {0xFFC8203CU, 0x0000000EU}, /* RGIDR_MODID[15]:WDT*/ + [14] = {0xFFC82040U, 0x0000000EU}, /* RGIDR_MODID[16]:WWDT0*/ + [15] = {0xFFC82044U, 0x0000000EU}, /* RGIDR_MODID[17]:WWDT1*/ + [16] = {0xFFC82048U, 0x0000000EU}, /* RGIDR_MODID[18]:WWDT2*/ + [17] = {0xFFC8204CU, 0x0000000EU}, /* RGIDR_MODID[19]:WWDT3*/ + [18] = {0xFFC82050U, 0x0000000EU}, /* RGIDR_MODID[20]:WWDT4*/ + [19] = {0xFFC82054U, 0x0000000EU}, /* RGIDR_MODID[21]:WWDT5*/ + [20] = {0xFFC82058U, 0x0000000EU}, /* RGIDR_MODID[22]:WWDT6*/ + [21] = {0xFFC82068U, 0x0000000FU}, /* RGIDR_MODID[23]:ECMRT3*/ + [22] = {0xE6002000U, 0x0000000EU}, /* RGIDR_MODID[24]:ADVFSC*/ + [23] = {0xE6002004U, 0x0000000FU}, /* RGIDR_MODID[25]:APMU0*/ + [24] = {0xE6002008U, 0x00000002U}, /* RGIDR_MODID[26]:APMU1*/ + [25] = {0xE600200CU, 0x00000000U}, /* RGIDR_MODID[27]:APMU10*/ + [26] = {0xE6002010U, 0x00000000U}, /* RGIDR_MODID[28]:APMU11*/ + [27] = {0xE6002014U, 0x00000000U}, /* RGIDR_MODID[29]:APMU12*/ + [28] = {0xE6002018U, 0x00000000U}, /* RGIDR_MODID[30]:APMU13*/ + [29] = {0xE600201CU, 0x00000000U}, /* RGIDR_MODID[31]:APMU14*/ + [30] = {0xE6002020U, 0x00000000U}, /* RGIDR_MODID[32]:APMU15*/ + [31] = {0xE6002024U, 0x00000004U}, /* RGIDR_MODID[33]:APMU2*/ + [32] = {0xE6002028U, 0x00000004U}, /* RGIDR_MODID[34]:APMU3*/ + [33] = {0xE600202CU, 0x00000000U}, /* RGIDR_MODID[35]:APMU4*/ + [34] = {0xE6002030U, 0x00000000U}, /* RGIDR_MODID[36]:APMU5*/ + [35] = {0xE6002034U, 0x00000000U}, /* RGIDR_MODID[37]:APMU6*/ + [36] = {0xE6002038U, 0x00000000U}, /* RGIDR_MODID[38]:APMU7*/ + [37] = {0xE600203CU, 0x00000000U}, /* RGIDR_MODID[39]:APMU8*/ + [38] = {0xE6002040U, 0x00000000U}, /* RGIDR_MODID[40]:APMU9*/ + [39] = {0xE6002044U, 0x0000000FU}, /* RGIDR_MODID[41]:ARS00*/ + /* After setting */ /* RGIDR_MODID[42]:ARS01*/ + /* After setting */ /* RGIDR_MODID[43]:ARS02*/ + [40] = {0xE6002050U, 0x0000000FU}, /* RGIDR_MODID[44]:ARS03*/ + [41] = {0xE6002054U, 0x0000000FU}, /* RGIDR_MODID[45]:ARS04*/ + [42] = {0xE6002058U, 0x0000000FU}, /* RGIDR_MODID[46]:ARS05*/ + [43] = {0xE600205CU, 0x0000000FU}, /* RGIDR_MODID[47]:ARS06*/ + [44] = {0xE6002060U, 0x0000000FU}, /* RGIDR_MODID[48]:ARS07*/ + [45] = {0xE6002064U, 0x00000000U}, /* RGIDR_MODID[49]:ARS08*/ + [46] = {0xE6002068U, 0x0000000EU}, /* RGIDR_MODID[50]:CMT0*/ + [47] = {0xE600206CU, 0x0000000EU}, /* RGIDR_MODID[51]:CMT1*/ + [48] = {0xE6002070U, 0x0000000EU}, /* RGIDR_MODID[52]:CMT2*/ + [49] = {0xE6002074U, 0x0000000EU}, /* RGIDR_MODID[53]:CMT3*/ + [50] = {0xE6002078U, 0x0000000AU}, /* RGIDR_MODID[54]:CKM*/ + [51] = {0xE600207CU, 0x0000000EU}, /* RGIDR_MODID[55]:DBE*/ + [52] = {0xE6002080U, 0x0000000EU}, /* RGIDR_MODID[56]:IRQC*/ + [53] = {0xE6002084U, 0x0000000FU}, /* RGIDR_MODID[57]:ECMPS0*/ + [54] = {0xE6002088U, 0x0000000BU}, /* RGIDR_MODID[58]:OTP0*/ + [55] = {0xE600208CU, 0x0000000FU}, /* RGIDR_MODID[59]:OTP1*/ + [56] = {0xE600209CU, 0x0000000EU}, /* RGIDR_MODID[60]:SCMT*/ + [57] = {0xE60020A8U, 0x0000004EU}, /* RGIDR_MODID[61]:TSC1*/ + [58] = {0xE60020ACU, 0x0000004EU}, /* RGIDR_MODID[62]:TSC2*/ + [59] = {0xE60020B0U, 0x0000004EU}, /* RGIDR_MODID[63]:TSC3*/ + [60] = {0xE60020B4U, 0x0000004EU}, /* RGIDR_MODID[64]:TSC4*/ + [61] = {0xE60020B8U, 0x00000006U}, /* RGIDR_MODID[65]:UCMT*/ + [62] = {0xE6002100U, 0x0000006FU}, /* RGIDR_MODID[66]:CPG0*/ + [63] = {0xE6002104U, 0x0000000AU}, /* RGIDR_MODID[67]:CPG1*/ + [64] = {0xE6002108U, 0x0000004EU}, /* RGIDR_MODID[68]:CPG2*/ + [65] = {0xE600210CU, 0x00000028U}, /* RGIDR_MODID[69]:CPG3*/ + [66] = {0xE6002110U, 0x0000006FU}, /* RGIDR_MODID[70]:PFC00*/ + [67] = {0xE6002114U, 0x0000000AU}, /* RGIDR_MODID[71]:PFC01*/ + [68] = {0xE6002118U, 0x0000004EU}, /* RGIDR_MODID[72]:PFC02*/ + [69] = {0xE600211CU, 0x00000028U}, /* RGIDR_MODID[73]:PFC03*/ + [70] = {0xE6002120U, 0x0000006FU}, /* RGIDR_MODID[74]:PFC10*/ + [71] = {0xE6002124U, 0x0000000AU}, /* RGIDR_MODID[75]:PFC11*/ + [72] = {0xE6002128U, 0x0000004EU}, /* RGIDR_MODID[76]:PFC12*/ + [73] = {0xE600212CU, 0x00000028U}, /* RGIDR_MODID[77]:PFC13*/ + [74] = {0xE6002130U, 0x0000006FU}, /* RGIDR_MODID[78]:PFC20*/ + [75] = {0xE6002134U, 0x0000000AU}, /* RGIDR_MODID[79]:PFC21*/ + [76] = {0xE6002138U, 0x0000004EU}, /* RGIDR_MODID[80]:PFC22*/ + [77] = {0xE600213CU, 0x00000028U}, /* RGIDR_MODID[81]:PFC23*/ + [78] = {0xE6002140U, 0x0000006FU}, /* RGIDR_MODID[82]:PFC30*/ + [79] = {0xE6002144U, 0x0000000AU}, /* RGIDR_MODID[83]:PFC31*/ + [80] = {0xE6002148U, 0x0000004EU}, /* RGIDR_MODID[84]:PFC32*/ + [81] = {0xE600214CU, 0x00000028U}, /* RGIDR_MODID[85]:PFC33*/ + [82] = {0xE6002150U, 0x0000006FU}, /* RGIDR_MODID[86]:PFCS0*/ + [83] = {0xE6002154U, 0x0000000AU}, /* RGIDR_MODID[87]:PFCS1*/ + [84] = {0xE6002158U, 0x0000004EU}, /* RGIDR_MODID[88]:PFCS2*/ + [85] = {0xE600215CU, 0x00000028U}, /* RGIDR_MODID[89]:PFCS3*/ + [86] = {0xE6002160U, 0x0000006FU}, /* RGIDR_MODID[90]:RESET0*/ + [87] = {0xE6002164U, 0x0000000AU}, /* RGIDR_MODID[91]:RESET1*/ + [88] = {0xE6002168U, 0x0000004EU}, /* RGIDR_MODID[92]:RESET2*/ + [89] = {0xE600216CU, 0x00000028U}, /* RGIDR_MODID[93]:RESET3*/ + [90] = {0xE6002170U, 0x0000006FU}, /* RGIDR_MODID[94]:SYS0*/ + [91] = {0xE6002174U, 0x0000000AU}, /* RGIDR_MODID[95]:SYS1*/ + [92] = {0xE6002178U, 0x0000004EU}, /* RGIDR_MODID[96]:SYS2*/ + [93] = {0xE600217CU, 0x00000028U}, /* RGIDR_MODID[97]:SYS3*/ + [94] = {0xE7762000U, 0x0000000EU}, /* RGIDR_MODID[98]:DMAMSI0*/ + [95] = {0xE7762004U, 0x0000000EU}, /* RGIDR_MODID[99]:DMAMSI1*/ + [96] = {0xE7762008U, 0x0000000EU}, /* RGIDR_MODID[100]:DMAMSI2*/ + [97] = {0xE776200CU, 0x0000000EU}, /* RGIDR_MODID[101]:DMAMSI3*/ + [98] = {0xE7762010U, 0x0000000EU}, /* RGIDR_MODID[102]:DMAMSI4*/ + [99] = {0xE7762014U, 0x0000000EU}, /* RGIDR_MODID[103]:DMAMSI5*/ + [100] = {0xE7762018U, 0x0000000FU}, /* RGIDR_MODID[104]:ECMSP3*/ + [101] = {0xE7762024U, 0x0000000FU}, /* RGIDR_MODID[105]:ARSP30*/ + /* After setting */ /* RGIDR_MODID[106]:ARSP31*/ + /* After setting */ /* RGIDR_MODID[107]:ARSP32*/ + [102] = {0xE7762030U, 0x0000000FU}, /* RGIDR_MODID[108]:ARSP33*/ + [103] = {0xE7762034U, 0x0000000FU}, /* RGIDR_MODID[109]:ARSP34*/ + [104] = {0xE7762038U, 0x0000000FU}, /* RGIDR_MODID[110]:ARSP35*/ + [105] = {0xE776203CU, 0x0000000FU}, /* RGIDR_MODID[111]:ARSP36*/ + [106] = {0xE7762040U, 0x0000000FU}, /* RGIDR_MODID[112]:ARSP37*/ + [107] = {0xE7762044U, 0x00000000U}, /* RGIDR_MODID[113]:ARSP38*/ + [108] = {0xE7762048U, 0x0000000EU}, /* RGIDR_MODID[114]:MSI0*/ + [109] = {0xE776204CU, 0x0000000EU}, /* RGIDR_MODID[115]:MSI1*/ + [110] = {0xE7762050U, 0x0000000EU}, /* RGIDR_MODID[116]:MSI2*/ + [111] = {0xE7762054U, 0x0000000EU}, /* RGIDR_MODID[117]:MSI3*/ + [112] = {0xE7762058U, 0x0000000EU}, /* RGIDR_MODID[118]:MSI4*/ + [113] = {0xE776205CU, 0x0000000EU}, /* RGIDR_MODID[119]:MSI5*/ + [114] = {0xE7792000U, 0x0000000FU}, /* RGIDR_MODID[120]:ARSP40*/ + /* After setting */ /* RGIDR_MODID[121]:ARSP41*/ + /* After setting */ /* RGIDR_MODID[122]:ARSP42*/ + [115] = {0xE779200CU, 0x0000000FU}, /* RGIDR_MODID[123]:ARSP43*/ + [116] = {0xE7792010U, 0x0000000FU}, /* RGIDR_MODID[124]:ARSP44*/ + [117] = {0xE7792014U, 0x0000000FU}, /* RGIDR_MODID[125]:ARSP45*/ + [118] = {0xE7792018U, 0x0000000FU}, /* RGIDR_MODID[126]:ARSP46*/ + [119] = {0xE779201CU, 0x0000000FU}, /* RGIDR_MODID[127]:ARSP47*/ + [120] = {0xE7792020U, 0x00000000U}, /* RGIDR_MODID[128]:ARSP48*/ + [121] = {0xE7792024U, 0x0000004FU}, /* RGIDR_MODID[129]:DMAHSCIF0*/ + [122] = {0xE7792028U, 0x0000004FU}, /* RGIDR_MODID[130]:DMAHSCIF1*/ + [123] = {0xE779202CU, 0x0000004FU}, /* RGIDR_MODID[131]:DMAHSCIF2*/ + [124] = {0xE7792030U, 0x0000004FU}, /* RGIDR_MODID[132]:DMAHSCIF3*/ + [125] = {0xE7792034U, 0x0000004FU}, /* RGIDR_MODID[133]:DMASCIF0*/ + [126] = {0xE7792038U, 0x0000004FU}, /* RGIDR_MODID[134]:DMASCIF1*/ + [127] = {0xE779203CU, 0x0000004FU}, /* RGIDR_MODID[135]:DMASCIF3*/ + [128] = {0xE7792040U, 0x0000004FU}, /* RGIDR_MODID[136]:DMASCIF4*/ + [129] = {0xE7792044U, 0x0000000FU}, /* RGIDR_MODID[137]:ECMSP4*/ + [130] = {0xE7792048U, 0x0000004FU}, /* RGIDR_MODID[138]:HSCIF0*/ + [131] = {0xE779204CU, 0x0000004FU}, /* RGIDR_MODID[139]:HSCIF1*/ + [132] = {0xE7792050U, 0x0000004FU}, /* RGIDR_MODID[140]:HSCIF2*/ + [133] = {0xE7792054U, 0x0000004FU}, /* RGIDR_MODID[141]:HSCIF3*/ + [134] = {0xE7792058U, 0x0000004FU}, /* RGIDR_MODID[142]:SCIF0*/ + [135] = {0xE779205CU, 0x0000004FU}, /* RGIDR_MODID[143]:SCIF1*/ + [136] = {0xE7792060U, 0x0000004FU}, /* RGIDR_MODID[144]:SCIF3*/ + [137] = {0xE7792064U, 0x0000004FU}, /* RGIDR_MODID[145]:SCIF4*/ + [138] = {0xE7792068U, 0x0000006EU}, /* RGIDR_MODID[146]:TMU1*/ + [139] = {0xE779206CU, 0x0000006EU}, /* RGIDR_MODID[147]:TMU2*/ + [140] = {0xE7792070U, 0x0000006EU}, /* RGIDR_MODID[148]:TMU3*/ + [141] = {0xE7792074U, 0x0000006EU}, /* RGIDR_MODID[149]:TMU4*/ + [142] = {0xE7792078U, 0x0000004AU}, /* RGIDR_MODID[150]:CANFD*/ + [143] = {0xE779207CU, 0x0000004AU}, /* RGIDR_MODID[151]:DMACANFD*/ + [144] = {0xE7792080U, 0x00000002U}, /* RGIDR_MODID[152]:DMATPU0*/ + [145] = {0xE7792084U, 0x00000002U}, /* RGIDR_MODID[153]:PWM0*/ + [146] = {0xE7792088U, 0x00000002U}, /* RGIDR_MODID[154]:PWM1*/ + [147] = {0xE779208CU, 0x00000002U}, /* RGIDR_MODID[155]:PWM2*/ + [148] = {0xE7792090U, 0x00000002U}, /* RGIDR_MODID[156]:PWM3*/ + [149] = {0xE7792094U, 0x00000002U}, /* RGIDR_MODID[157]:PWM4*/ + [150] = {0xE7792098U, 0x00000002U}, /* RGIDR_MODID[158]:PWM5*/ + [151] = {0xE779209CU, 0x00000002U}, /* RGIDR_MODID[159]:PWM6*/ + [152] = {0xE77920A0U, 0x00000002U}, /* RGIDR_MODID[160]:PWM7*/ + [153] = {0xE77920A4U, 0x00000002U}, /* RGIDR_MODID[161]:PWM8*/ + [154] = {0xE77920A8U, 0x00000002U}, /* RGIDR_MODID[162]:PWM9*/ + [155] = {0xE77920ACU, 0x00000002U}, /* RGIDR_MODID[163]:TPU0*/ + [156] = {0xFE672000U, 0x0000002FU}, /* RGIDR_MODID[164]:ARVC10*/ + /* After setting */ /* RGIDR_MODID[165]:ARVC11*/ + /* After setting */ /* RGIDR_MODID[166]:ARVC12*/ + [157] = {0xFE67200CU, 0x0000002FU}, /* RGIDR_MODID[167]:ARVC13*/ + [158] = {0xFE672010U, 0x0000002FU}, /* RGIDR_MODID[168]:ARVC14*/ + [159] = {0xFE672014U, 0x0000002FU}, /* RGIDR_MODID[169]:ARVC15*/ + [160] = {0xFE672018U, 0x0000002FU}, /* RGIDR_MODID[170]:ARVC16*/ + [161] = {0xFE67201CU, 0x0000002FU}, /* RGIDR_MODID[171]:ARVC17*/ + [162] = {0xFE672020U, 0x00000000U}, /* RGIDR_MODID[172]:ARVC18*/ + [163] = {0xFE672024U, 0x0000000FU}, /* RGIDR_MODID[173]:ECMVC1*/ + [164] = {0xFE672028U, 0x00000028U}, /* RGIDR_MODID[174]:FCPCS*/ + [165] = {0xFE67202CU, 0x00000028U}, /* RGIDR_MODID[175]:VCP4LC*/ + [166] = {0xFE672030U, 0x00000028U}, /* RGIDR_MODID[176]:VCP4LV*/ + [167] = {0xFEBD2000U, 0x0000000FU}, /* RGIDR_MODID[177]:ARVI40*/ + /* After setting */ /* RGIDR_MODID[178]:ARVI41*/ + /* After setting */ /* RGIDR_MODID[179]:ARVI42*/ + [168] = {0xFEBD200CU, 0x0000000FU}, /* RGIDR_MODID[180]:ARVI43*/ + [169] = {0xFEBD2010U, 0x0000000FU}, /* RGIDR_MODID[181]:ARVI44*/ + [170] = {0xFEBD2014U, 0x0000000FU}, /* RGIDR_MODID[182]:ARVI45*/ + [171] = {0xFEBD2018U, 0x0000000FU}, /* RGIDR_MODID[183]:ARVI46*/ + [172] = {0xFEBD201CU, 0x0000000FU}, /* RGIDR_MODID[184]:ARVI47*/ + [173] = {0xFEBD2020U, 0x00000000U}, /* RGIDR_MODID[185]:ARVI48*/ + [174] = {0xFEBD2024U, 0x0000000FU}, /* RGIDR_MODID[186]:DIS0*/ + [175] = {0xFEBD202CU, 0x0000000FU}, /* RGIDR_MODID[187]:DSC*/ + [176] = {0xFEBD2030U, 0x0000000FU}, /* RGIDR_MODID[188]:ECMVIO2*/ + [177] = {0xFEBD2034U, 0x0000000FU}, /* RGIDR_MODID[189]:FCPVD0*/ + [178] = {0xFEBD2038U, 0x0000000FU}, /* RGIDR_MODID[190]:FCPVD1*/ + [179] = {0xFEBD203CU, 0x0000004EU}, /* RGIDR_MODID[191]:VSPD0*/ + [180] = {0xFEBD2040U, 0x0000004EU}, /* RGIDR_MODID[192]:VSPD1*/ + [181] = {0xE6582000U, 0x0000000AU}, /* RGIDR_MODID[193]:CKMHSC*/ + [182] = {0xE6582004U, 0x0000000CU}, /* RGIDR_MODID[194]:AXIPCI001*/ + [183] = {0xE6582008U, 0x0000000CU}, /* RGIDR_MODID[195]:AXIPCI002*/ + [184] = {0xE658200CU, 0x0000000CU}, /* RGIDR_MODID[196]:AXIPCI003*/ + [185] = {0xE6582014U, 0x0000000CU}, /* RGIDR_MODID[197]:AXIPCI005*/ + [186] = {0xE6582018U, 0x0000000CU}, /* RGIDR_MODID[198]:AXIPCI006*/ + [187] = {0xE658201CU, 0x0000000CU}, /* RGIDR_MODID[199]:AXIPCI007*/ + [188] = {0xE6582020U, 0x0000000CU}, /* RGIDR_MODID[200]:AXIPCI008*/ + [189] = {0xE6582024U, 0x0000000CU}, /* RGIDR_MODID[201]:AXIPCI009*/ + [190] = {0xE6582028U, 0x0000000CU}, /* RGIDR_MODID[202]:AXIPCI010*/ + [191] = {0xE658202CU, 0x0000000CU}, /* RGIDR_MODID[203]:AXIPCI011*/ + [192] = {0xE6582030U, 0x0000000CU}, /* RGIDR_MODID[204]:AXIPCI012*/ + [193] = {0xE6582034U, 0x0000000CU}, /* RGIDR_MODID[205]:AXIPCI013*/ + [194] = {0xE6582038U, 0x0000000CU}, /* RGIDR_MODID[206]:AXIPCI014*/ + [195] = {0xE658203CU, 0x0000000CU}, /* RGIDR_MODID[207]:AXIPCI015*/ + [196] = {0xE6582040U, 0x0000000CU}, /* RGIDR_MODID[208]:AXIPCI100*/ + [197] = {0xE6582044U, 0x0000000CU}, /* RGIDR_MODID[209]:AXIPCI101*/ + [198] = {0xE6582048U, 0x0000000CU}, /* RGIDR_MODID[210]:AXIPCI102*/ + [199] = {0xE658204CU, 0x0000000CU}, /* RGIDR_MODID[211]:AXIPCI103*/ + [200] = {0xE6582050U, 0x0000000CU}, /* RGIDR_MODID[212]:AXIPCI104*/ + [201] = {0xE6582054U, 0x0000000CU}, /* RGIDR_MODID[213]:AXIPCI105*/ + [202] = {0xE6582058U, 0x0000000CU}, /* RGIDR_MODID[214]:AXIPCI106*/ + [203] = {0xE658205CU, 0x0000000CU}, /* RGIDR_MODID[215]:AXIPCI107*/ + [204] = {0xE6582060U, 0x0000000CU}, /* RGIDR_MODID[216]:AXIPCI108*/ + [205] = {0xE6582064U, 0x0000000CU}, /* RGIDR_MODID[217]:AXIPCI109*/ + [206] = {0xE6582068U, 0x0000000CU}, /* RGIDR_MODID[218]:AXIPCI110*/ + [207] = {0xE658206CU, 0x0000000CU}, /* RGIDR_MODID[219]:AXIPCI111*/ + [208] = {0xE6582070U, 0x0000000CU}, /* RGIDR_MODID[220]:AXIPCI112*/ + [209] = {0xE6582074U, 0x0000000CU}, /* RGIDR_MODID[221]:AXIPCI113*/ + [210] = {0xE6582078U, 0x0000000CU}, /* RGIDR_MODID[222]:AXIPCI114*/ + [211] = {0xE658207CU, 0x0000000CU}, /* RGIDR_MODID[223]:AXIPCI115*/ + [212] = {0xE6582084U, 0x0000000EU}, /* RGIDR_MODID[224]:GPTP*/ + [213] = {0xE6582088U, 0x0000004EU}, /* RGIDR_MODID[225]:IPMMUHC00*/ + [214] = {0xE65820F0U, 0x0000000EU}, /* RGIDR_MODID[226]:TSN0*/ + [215] = {0xE65820F4U, 0x0000000CU}, /* RGIDR_MODID[227]:AXIPCI000*/ + [216] = {0xE65820F8U, 0x0000000CU}, /* RGIDR_MODID[228]:AXIPCI004*/ + [217] = {0xE65820FCU, 0x0000004EU}, /* RGIDR_MODID[229]:IPMMUHC01*/ + [218] = {0xE6582100U, 0x0000004EU}, /* RGIDR_MODID[230]:AVB0*/ + [219] = {0xE6582104U, 0x0000004EU}, /* RGIDR_MODID[231]:AVB1*/ + [220] = {0xE6582108U, 0x0000004EU}, /* RGIDR_MODID[232]:AVB2*/ + [221] = {0xE658210CU, 0x0000004EU}, /* RGIDR_MODID[233]:IPMMUHC10*/ + [222] = {0xE6582110U, 0x0000004EU}, /* RGIDR_MODID[234]:IPMMUHC11*/ + [223] = {0xE6582114U, 0x0000004EU}, /* RGIDR_MODID[235]:IPMMUHC12*/ + [224] = {0xE6582118U, 0x0000004EU}, /* RGIDR_MODID[236]:IPMMUHC13*/ + [225] = {0xE658211CU, 0x0000000CU}, /* RGIDR_MODID[237]:PPHY0*/ + [226] = {0xE6582120U, 0x0000000CU}, /* RGIDR_MODID[238]:PPHY1*/ + [227] = {0xE6582124U, 0x0000004EU}, /* RGIDR_MODID[239]:IPMMUHC14*/ + [228] = {0xE6582128U, 0x0000004EU}, /* RGIDR_MODID[240]:IPMMUHC15*/ + [229] = {0xE658212CU, 0x0000000EU}, /* RGIDR_MODID[241]:FBAHSC*/ + [230] = {0xE6582130U, 0x0000004EU}, /* RGIDR_MODID[242]:IPMMUHC02*/ + [231] = {0xE6582138U, 0x0000000FU}, /* RGIDR_MODID[243]:ECMHSC*/ + [232] = {0xE658213CU, 0x0000000FU}, /* RGIDR_MODID[244]:ARHC0*/ + /* After setting */ /* RGIDR_MODID[245]:ARHC1*/ + /* After setting */ /* RGIDR_MODID[246]:ARHC2*/ + [233] = {0xE6582148U, 0x0000000FU}, /* RGIDR_MODID[247]:ARHC3*/ + [234] = {0xE658214CU, 0x0000000FU}, /* RGIDR_MODID[248]:ARHC4*/ + [235] = {0xE6582150U, 0x0000000FU}, /* RGIDR_MODID[249]:ARHC5*/ + [236] = {0xE6582154U, 0x0000000FU}, /* RGIDR_MODID[250]:ARHC6*/ + [237] = {0xE6582158U, 0x0000000FU}, /* RGIDR_MODID[251]:ARHC7*/ + [238] = {0xE658215CU, 0x00000000U}, /* RGIDR_MODID[252]:ARHC8*/ + [239] = {0xE6582160U, 0x0000004EU}, /* RGIDR_MODID[253]:IPMMUHC03*/ + [240] = {0xE6582164U, 0x0000004EU}, /* RGIDR_MODID[254]:IPMMUHC04*/ + [241] = {0xE6582168U, 0x0000004EU}, /* RGIDR_MODID[255]:IPMMUHC05*/ + [242] = {0xE658216CU, 0x0000004EU}, /* RGIDR_MODID[256]:IPMMUHC06*/ + [243] = {0xE6582170U, 0x0000004EU}, /* RGIDR_MODID[257]:IPMMUHC07*/ + [244] = {0xE6582174U, 0x0000004EU}, /* RGIDR_MODID[258]:IPMMUHC08*/ + [245] = {0xE6582178U, 0x0000004EU}, /* RGIDR_MODID[259]:IPMMUHC09*/ + [246] = {0xFF882000U, 0x0000000FU}, /* RGIDR_MODID[260]:ARIMP00*/ + /* After setting */ /* RGIDR_MODID[261]:ARIMP01*/ + /* After setting */ /* RGIDR_MODID[262]:ARIMP02*/ + [247] = {0xFF88200CU, 0x0000000FU}, /* RGIDR_MODID[263]:ARIMP03*/ + [248] = {0xFF882010U, 0x0000000FU}, /* RGIDR_MODID[264]:ARIMP04*/ + [249] = {0xFF882014U, 0x0000004EU}, /* RGIDR_MODID[265]:AXIFBABUSIR0*/ + [250] = {0xFF882018U, 0x0000004EU}, /* RGIDR_MODID[266]:AXIFBABUSIR1*/ + [251] = {0xFF88201CU, 0x0000004EU}, /* RGIDR_MODID[267]:AXIFBABUSIR2*/ + [252] = {0xFF882020U, 0x0000004EU}, /* RGIDR_MODID[268]:AXIFBABUSIR3*/ + [253] = {0xFF882024U, 0x0000004EU}, /* RGIDR_MODID[269]:AXIFBABUSIR4*/ + [254] = {0xFF882028U, 0x0000004EU}, /* RGIDR_MODID[270]:AXIIMP0*/ + [255] = {0xFF88202CU, 0x0000004EU}, /* RGIDR_MODID[271]:CKMCNR*/ + [256] = {0xFF882030U, 0x0000004EU}, /* RGIDR_MODID[272]:CKMDSP*/ + [257] = {0xFF882034U, 0x0000000FU}, /* RGIDR_MODID[273]:ARIMP05*/ + [258] = {0xFF882038U, 0x0000000FU}, /* RGIDR_MODID[274]:ARIMP06*/ + [259] = {0xFF88203CU, 0x0000000FU}, /* RGIDR_MODID[275]:ARIMP07*/ + [260] = {0xFF882040U, 0x00000000U}, /* RGIDR_MODID[276]:ARIMP08*/ + [261] = {0xFF882044U, 0x0000004EU}, /* RGIDR_MODID[277]:CKMIR*/ + [262] = {0xFF882048U, 0x0000000FU}, /* RGIDR_MODID[278]:ECMIR*/ + [263] = {0xFF88204CU, 0x0000000FU}, /* RGIDR_MODID[279]:DSPPS*/ + [264] = {0xFF882050U, 0x0000004EU}, /* RGIDR_MODID[280]:IPMMUIR1*/ + [265] = {0xFF882054U, 0x0000004EU}, /* RGIDR_MODID[281]:IPMMUIR0*/ + [266] = {0xFF882058U, 0x0000004EU}, /* RGIDR_MODID[282]:IPMMUIR10*/ + [267] = {0xFF88205CU, 0x0000004EU}, /* RGIDR_MODID[283]:IPMMUIR11*/ + [268] = {0xFF882060U, 0x0000004EU}, /* RGIDR_MODID[284]:IPMMUIR12*/ + [269] = {0xFF882064U, 0x0000004EU}, /* RGIDR_MODID[285]:IPMMUIR13*/ + [270] = {0xFF882068U, 0x0000004EU}, /* RGIDR_MODID[286]:IPMMUIR14*/ + [271] = {0xFF88206CU, 0x0000004EU}, /* RGIDR_MODID[287]:IPMMUIR15*/ + [272] = {0xFF882070U, 0x0000004EU}, /* RGIDR_MODID[288]:IPMMUIR2*/ + [273] = {0xFF882074U, 0x0000004EU}, /* RGIDR_MODID[289]:IPMMUIR3*/ + [274] = {0xFF882078U, 0x0000004EU}, /* RGIDR_MODID[290]:IPMMUIR4*/ + [275] = {0xFF88207CU, 0x0000004EU}, /* RGIDR_MODID[291]:IPMMUIR5*/ + [276] = {0xFF882080U, 0x0000004EU}, /* RGIDR_MODID[292]:IPMMUIR6*/ + [277] = {0xFF882084U, 0x0000004EU}, /* RGIDR_MODID[293]:IPMMUIR7*/ + [278] = {0xFF882088U, 0x0000004EU}, /* RGIDR_MODID[294]:IPMMUIR8*/ + [279] = {0xFF88208CU, 0x0000004EU}, /* RGIDR_MODID[295]:IPMMUIR9*/ + [280] = {0xFD812000U, 0x0000000FU}, /* RGIDR_MODID[296]:ARPV0*/ + /* After setting */ /* RGIDR_MODID[297]:ARPV1*/ + [281] = {0xFD812008U, 0x0000002CU}, /* RGIDR_MODID[298]:AXIRGXS*/ + /* After setting */ /* RGIDR_MODID[299]:ARPV2*/ + [282] = {0xFD812010U, 0x0000000FU}, /* RGIDR_MODID[300]:ARPV3*/ + [283] = {0xFD812014U, 0x0000000FU}, /* RGIDR_MODID[301]:ARPV4*/ + [284] = {0xFD812018U, 0x0000000FU}, /* RGIDR_MODID[302]:ARPV5*/ + [285] = {0xFD81201CU, 0x0000000FU}, /* RGIDR_MODID[303]:ARPV6*/ + [286] = {0xFD812020U, 0x0000000FU}, /* RGIDR_MODID[304]:ARPV7*/ + [287] = {0xFD812024U, 0x00000000U}, /* RGIDR_MODID[305]:ARPV8*/ + [288] = {0xFD812028U, 0x0000000AU}, /* RGIDR_MODID[306]:CKM3DG*/ + [289] = {0xFD81202CU, 0x0000000FU}, /* RGIDR_MODID[307]:ECM3DG*/ + [290] = {0xFD812030U, 0x0000000EU}, /* RGIDR_MODID[308]:FBAPVC*/ + [291] = {0xFD812034U, 0x0000000EU}, /* RGIDR_MODID[309]:FBAPVD0*/ + [292] = {0xFD812038U, 0x0000000EU}, /* RGIDR_MODID[310]:FBAPVD1*/ + [293] = {0xFD81203CU, 0x0000000EU}, /* RGIDR_MODID[311]:FBAPVD2*/ + [294] = {0xFD812040U, 0x0000000EU}, /* RGIDR_MODID[312]:FBAPVE*/ + [295] = {0xFD812044U, 0x0000004EU}, /* RGIDR_MODID[313]:IPMMUPV000*/ + [296] = {0xFD812048U, 0x0000004EU}, /* RGIDR_MODID[314]:IPMMUPV001*/ + [297] = {0xFD81204CU, 0x0000004EU}, /* RGIDR_MODID[315]:IPMMUPV010*/ + [298] = {0xFD812050U, 0x0000004EU}, /* RGIDR_MODID[316]:IPMMUPV011*/ + [299] = {0xFD812054U, 0x0000004EU}, /* RGIDR_MODID[317]:IPMMUPV012*/ + [300] = {0xFD812058U, 0x0000004EU}, /* RGIDR_MODID[318]:IPMMUPV013*/ + [301] = {0xFD81205CU, 0x0000004EU}, /* RGIDR_MODID[319]:IPMMUPV014*/ + [302] = {0xFD812060U, 0x0000004EU}, /* RGIDR_MODID[320]:IPMMUPV015*/ + [303] = {0xFD812064U, 0x0000004EU}, /* RGIDR_MODID[321]:IPMMUPV002*/ + [304] = {0xFD812068U, 0x0000004EU}, /* RGIDR_MODID[322]:IPMMUPV003*/ + [305] = {0xFD81206CU, 0x0000004EU}, /* RGIDR_MODID[323]:IPMMUPV004*/ + [306] = {0xFD812070U, 0x0000004EU}, /* RGIDR_MODID[324]:IPMMUPV005*/ + [307] = {0xFD812074U, 0x0000004EU}, /* RGIDR_MODID[325]:IPMMUPV006*/ + [308] = {0xFD812078U, 0x0000004EU}, /* RGIDR_MODID[326]:IPMMUPV007*/ + [309] = {0xFD81207CU, 0x0000004EU}, /* RGIDR_MODID[327]:IPMMUPV008*/ + [310] = {0xFD812080U, 0x0000004EU}, /* RGIDR_MODID[328]:IPMMUPV009*/ + [311] = {0xE6622000U, 0x0000000FU}, /* RGIDR_MODID[329]:ARRC0*/ + /* After setting */ /* RGIDR_MODID[330]:ARRC1*/ + /* After setting */ /* RGIDR_MODID[331]:ARRC2*/ + [312] = {0xE662200CU, 0x0000000FU}, /* RGIDR_MODID[332]:ARRC3*/ + [313] = {0xE6622010U, 0x0000000FU}, /* RGIDR_MODID[333]:ARRC4*/ + [314] = {0xE6622014U, 0x0000000FU}, /* RGIDR_MODID[334]:ARRC5*/ + [315] = {0xE6622018U, 0x0000000FU}, /* RGIDR_MODID[335]:ARRC6*/ + [316] = {0xE662201CU, 0x0000000FU}, /* RGIDR_MODID[336]:ARRC7*/ + [317] = {0xE6622020U, 0x00000000U}, /* RGIDR_MODID[337]:ARRC8*/ + [318] = {0xE6622024U, 0x00000009U}, /* RGIDR_MODID[338]:CR0*/ + [319] = {0xE6622028U, 0x0000004FU}, /* RGIDR_MODID[339]:ICUMX*/ + [320] = {0xE662202CU, 0x0000000FU}, /* RGIDR_MODID[340]:ECMRC*/ + [321] = {0xFFC32000U, 0x0000004EU}, /* RGIDR_MODID[341]:DMAWCRC0*/ + [322] = {0xFFC32004U, 0x0000004EU}, /* RGIDR_MODID[342]:DMAWCRC1*/ + [323] = {0xFFC32008U, 0x0000004EU}, /* RGIDR_MODID[343]:DMAWCRC2*/ + [324] = {0xFFC3200CU, 0x0000004EU}, /* RGIDR_MODID[344]:DMAWCRC3*/ + [325] = {0xFFC42000U, 0x0000000FU}, /* RGIDR_MODID[345]:ARMREG00*/ + [326] = {0xFFC42004U, 0x0000000DU}, /* RGIDR_MODID[346]:ARMREG01*/ + [327] = {0xFFC42008U, 0x00000000U}, /* RGIDR_MODID[347]:ARMREG10*/ + [328] = {0xFFC4200CU, 0x00000000U}, /* RGIDR_MODID[348]:ARMREG11*/ + [329] = {0xFFC42010U, 0x0000000BU}, /* RGIDR_MODID[349]:ARMREG12*/ + [330] = {0xFFC42014U, 0x0000000FU}, /* RGIDR_MODID[350]:ARMREG13*/ + [331] = {0xFFC42018U, 0x0000000BU}, /* RGIDR_MODID[351]:ARMREG14*/ + [332] = {0xFFC4201CU, 0x00000002U}, /* RGIDR_MODID[352]:AXICR52SS0*/ + [333] = {0xFFC42020U, 0x0000000EU}, /* RGIDR_MODID[353]:AXICSD0*/ + [334] = {0xFFC42024U, 0x0000000EU}, /* RGIDR_MODID[354]:AXIINTAP0*/ + [335] = {0xFFC42028U, 0x00000000U}, /* RGIDR_MODID[355]:AXIINTAP1*/ + [336] = {0xFFC4202CU, 0x00000009U}, /* RGIDR_MODID[356]:AXISECROM*/ + [337] = {0xFFC42030U, 0x0000000FU}, /* RGIDR_MODID[357]:AXISYSRAM0*/ + [338] = {0xFFC42034U, 0x0000004FU}, /* RGIDR_MODID[358]:AXISYSRAM1*/ + [339] = {0xFFC42038U, 0x00000000U}, /* RGIDR_MODID[359]:ARGREG15*/ + [340] = {0xFFC4203CU, 0x00000000U}, /* RGIDR_MODID[360]:ARMREG2*/ + [341] = {0xFFC42040U, 0x00000000U}, /* RGIDR_MODID[361]:ARMREG3*/ + [342] = {0xFFC42044U, 0x00000000U}, /* RGIDR_MODID[362]:ARMREG4*/ + [343] = {0xFFC42048U, 0x0000000FU}, /* RGIDR_MODID[363]:ARMREG5*/ + [344] = {0xFFC4204CU, 0x0000000FU}, /* RGIDR_MODID[364]:ARMREG6*/ + [345] = {0xFFC42050U, 0x00000000U}, /* RGIDR_MODID[365]:ARMREG7*/ + [346] = {0xFFC42054U, 0x0000000DU}, /* RGIDR_MODID[366]:ARMREG8*/ + [347] = {0xFFC42058U, 0x0000000DU}, /* RGIDR_MODID[367]:ARMREG9*/ + [348] = {0xFFC4205CU, 0x0000000FU}, /* RGIDR_MODID[368]:ARRD0*/ + /* After setting */ /* RGIDR_MODID[369]:ARRD1*/ + /* After setting */ /* RGIDR_MODID[370]:ARRD2*/ + [349] = {0xFFC42068U, 0x0000000FU}, /* RGIDR_MODID[371]:ARRD3*/ + [350] = {0xFFC4206CU, 0x0000000FU}, /* RGIDR_MODID[372]:ARRD4*/ + [351] = {0xFFC42070U, 0x0000000FU}, /* RGIDR_MODID[373]:ARRD5*/ + [352] = {0xFFC42074U, 0x0000000FU}, /* RGIDR_MODID[374]:ARRD6*/ + [353] = {0xFFC42078U, 0x0000000FU}, /* RGIDR_MODID[375]:ARRD7*/ + [354] = {0xFFC4207CU, 0x00000000U}, /* RGIDR_MODID[376]:ARRD8*/ + [355] = {0xFFC42080U, 0x0000000FU}, /* RGIDR_MODID[377]:ARRT0*/ + /* After setting */ /* RGIDR_MODID[378]:ARRT1*/ + /* After setting */ /* RGIDR_MODID[379]:ARRT2*/ + [356] = {0xFFC4208CU, 0x0000000FU}, /* RGIDR_MODID[380]:ARRT3*/ + [357] = {0xFFC42090U, 0x0000000FU}, /* RGIDR_MODID[381]:ARRT4*/ + [358] = {0xFFC42094U, 0x0000000FU}, /* RGIDR_MODID[382]:ARRT5*/ + [359] = {0xFFC42098U, 0x0000000FU}, /* RGIDR_MODID[383]:ARRT6*/ + [360] = {0xFFC4209CU, 0x0000000FU}, /* RGIDR_MODID[384]:ARRT7*/ + [361] = {0xFFC420A0U, 0x00000000U}, /* RGIDR_MODID[385]:ARRT8*/ + [362] = {0xFFC420A4U, 0x0000000AU}, /* RGIDR_MODID[386]:CKMRT*/ + [363] = {0xFFC420A8U, 0x0000004EU}, /* RGIDR_MODID[387]:CRC0*/ + [364] = {0xFFC420ACU, 0x0000004EU}, /* RGIDR_MODID[388]:CRC1*/ + [365] = {0xFFC420B0U, 0x0000004EU}, /* RGIDR_MODID[389]:CRC2*/ + [366] = {0xFFC420B4U, 0x0000004EU}, /* RGIDR_MODID[390]:CRC3*/ + [367] = {0xFFC420B8U, 0x0000000EU}, /* RGIDR_MODID[391]:CSD*/ + [368] = {0xFFC420BCU, 0x0000000FU}, /* RGIDR_MODID[392]:ECM*/ + [369] = {0xFFC420C0U, 0x0000000FU}, /* RGIDR_MODID[393]:ECMRT*/ + [370] = {0xFFC420C4U, 0x0000000EU}, /* RGIDR_MODID[394]:FBACR52*/ + [371] = {0xFFC420C8U, 0x0000000EU}, /* RGIDR_MODID[395]:FBART*/ + [372] = {0xFFC420CCU, 0x0000000EU}, /* RGIDR_MODID[396]:INTTP*/ + [373] = {0xFFC420D0U, 0x0000004EU}, /* RGIDR_MODID[397]:IPMMURT000*/ + [374] = {0xFFC420D4U, 0x0000004EU}, /* RGIDR_MODID[398]:IPMMURT100*/ + [375] = {0xFFC420D8U, 0x0000004EU}, /* RGIDR_MODID[399]:KCRC4*/ + [376] = {0xFFC420DCU, 0x0000004EU}, /* RGIDR_MODID[400]:KCRC5*/ + [377] = {0xFFC420E0U, 0x0000004EU}, /* RGIDR_MODID[401]:KCRC6*/ + [378] = {0xFFC420E4U, 0x0000004EU}, /* RGIDR_MODID[402]:KCRC7*/ + [379] = {0xFFC420E8U, 0x0000004FU}, /* RGIDR_MODID[403]:MFI00*/ + [380] = {0xFFC420ECU, 0x0000004EU}, /* RGIDR_MODID[404]:MFI01*/ + [381] = {0xFFC420F0U, 0x0000004EU}, /* RGIDR_MODID[405]:MFI10*/ + [382] = {0xFFC420F4U, 0x0000004EU}, /* RGIDR_MODID[406]:MFI02*/ + [383] = {0xFFC420F8U, 0x0000004EU}, /* RGIDR_MODID[407]:MFI03*/ + [384] = {0xFFC420FCU, 0x0000004EU}, /* RGIDR_MODID[408]:MFI04*/ + [385] = {0xFFC42100U, 0x00000000U}, /* RGIDR_MODID[409]:MFI05*/ + [386] = {0xFFC42104U, 0x00000000U}, /* RGIDR_MODID[410]:MFI06*/ + [387] = {0xFFC42108U, 0x00000000U}, /* RGIDR_MODID[411]:MFI07*/ + [388] = {0xFFC4210CU, 0x00000000U}, /* RGIDR_MODID[412]:MFI08*/ + [389] = {0xFFC42110U, 0x0000004EU}, /* RGIDR_MODID[413]:MFI09*/ + [390] = {0xFFC42114U, 0x0000004FU}, /* RGIDR_MODID[414]:MFI15*/ + [391] = {0xFFC42118U, 0x0000000AU}, /* RGIDR_MODID[415]:CKMCR52*/ + [392] = {0xFFC4211CU, 0x0000004BU}, /* RGIDR_MODID[416]:RTDM0P*/ + [393] = {0xFFC42120U, 0x0000000FU}, /* RGIDR_MODID[417]:ECMRD*/ + [394] = {0xFFC42124U, 0x0000004BU}, /* RGIDR_MODID[418]:RTDM1P*/ + [395] = {0xFFC4212CU, 0x0000004BU}, /* RGIDR_MODID[419]:RTDM2P*/ + [396] = {0xFFC42130U, 0x0000000BU}, /* RGIDR_MODID[420]:SYSRAM10*/ + [397] = {0xFFC42134U, 0x0000004BU}, /* RGIDR_MODID[421]:RTDM3P*/ + [398] = {0xFFC42138U, 0x00000003U}, /* RGIDR_MODID[422]:SYSRAM00*/ + [399] = {0xFFC4213CU, 0x0000004EU}, /* RGIDR_MODID[423]:TSIPL0*/ + [400] = {0xFFC42140U, 0x0000004EU}, /* RGIDR_MODID[424]:TSIPL1*/ + [401] = {0xFFC42144U, 0x0000004EU}, /* RGIDR_MODID[425]:TSIPL2*/ + [402] = {0xFFC42148U, 0x0000004EU}, /* RGIDR_MODID[426]:TSIPL3*/ + [403] = {0xFFC4214CU, 0x0000004EU}, /* RGIDR_MODID[427]:TSIPL4*/ + [404] = {0xFFC42150U, 0x0000004EU}, /* RGIDR_MODID[428]:TSIPL5*/ + [405] = {0xFFC42154U, 0x0000004EU}, /* RGIDR_MODID[429]:TSIPL6*/ + [406] = {0xFFC42158U, 0x0000004EU}, /* RGIDR_MODID[430]:TSIPL7*/ + [407] = {0xFFC4215CU, 0x0000004EU}, /* RGIDR_MODID[431]:WCRC0*/ + [408] = {0xFFC42160U, 0x0000004EU}, /* RGIDR_MODID[432]:WCRC1*/ + [409] = {0xFFC42164U, 0x0000004EU}, /* RGIDR_MODID[433]:WCRC2*/ + [410] = {0xFFC42168U, 0x0000004EU}, /* RGIDR_MODID[434]:WCRC3*/ + [411] = {0xFFC42180U, 0x0000004EU}, /* RGIDR_MODID[435]:MFI11*/ + [412] = {0xFFC42184U, 0x00000000U}, /* RGIDR_MODID[436]:MFI12*/ + [413] = {0xFFC42188U, 0x00000000U}, /* RGIDR_MODID[437]:MFI13*/ + [414] = {0xFFC4218CU, 0x00000000U}, /* RGIDR_MODID[438]:MFI14*/ + [415] = {0xFFC42190U, 0x0000004EU}, /* RGIDR_MODID[439]:IPMMURT001*/ + [416] = {0xFFC42194U, 0x0000004EU}, /* RGIDR_MODID[440]:IPMMURT010*/ + [417] = {0xFFC42198U, 0x0000004EU}, /* RGIDR_MODID[441]:IPMMURT011*/ + [418] = {0xFFC4219CU, 0x0000004EU}, /* RGIDR_MODID[442]:IPMMURT012*/ + [419] = {0xFFC421A0U, 0x0000004EU}, /* RGIDR_MODID[443]:IPMMURT013*/ + [420] = {0xFFC421A4U, 0x0000004EU}, /* RGIDR_MODID[444]:IPMMURT014*/ + [421] = {0xFFC421A8U, 0x0000004EU}, /* RGIDR_MODID[445]:IPMMURT015*/ + [422] = {0xFFC421ACU, 0x0000004EU}, /* RGIDR_MODID[446]:IPMMURT002*/ + [423] = {0xFFC421B0U, 0x0000004EU}, /* RGIDR_MODID[447]:IPMMURT003*/ + [424] = {0xFFC421B4U, 0x0000004EU}, /* RGIDR_MODID[448]:IPMMURT004*/ + [425] = {0xFFC421B8U, 0x0000004EU}, /* RGIDR_MODID[449]:IPMMURT005*/ + [426] = {0xFFC421BCU, 0x0000004EU}, /* RGIDR_MODID[450]:IPMMURT006*/ + [427] = {0xFFC421C0U, 0x0000004EU}, /* RGIDR_MODID[451]:IPMMURT007*/ + [428] = {0xFFC421C4U, 0x0000004EU}, /* RGIDR_MODID[452]:IPMMURT008*/ + [429] = {0xFFC421C8U, 0x0000004EU}, /* RGIDR_MODID[453]:IPMMURT009*/ + [430] = {0xFFC421CCU, 0x0000004EU}, /* RGIDR_MODID[454]:IPKMURT101*/ + [431] = {0xFFC421D0U, 0x0000004EU}, /* RGIDR_MODID[455]:IPMMURT110*/ + [432] = {0xFFC421D4U, 0x0000004EU}, /* RGIDR_MODID[456]:IPMMURT111*/ + [433] = {0xFFC421D8U, 0x0000004EU}, /* RGIDR_MODID[457]:IPMMURT112*/ + [434] = {0xFFC421DCU, 0x0000004EU}, /* RGIDR_MODID[458]:IPMMURT113*/ + [435] = {0xFFC421E0U, 0x0000004EU}, /* RGIDR_MODID[459]:IPMMURT114*/ + [436] = {0xFFC421E4U, 0x0000004EU}, /* RGIDR_MODID[460]:IPMMURT115*/ + [437] = {0xFFC421E8U, 0x0000004EU}, /* RGIDR_MODID[461]:IPMMURT102*/ + [438] = {0xFFC421ECU, 0x0000004EU}, /* RGIDR_MODID[462]:IPMMURT103*/ + [439] = {0xFFC421F0U, 0x0000004EU}, /* RGIDR_MODID[463]:IPMMURT104*/ + [440] = {0xFFC421F4U, 0x0000004EU}, /* RGIDR_MODID[464]:IPMMURT105*/ + [441] = {0xFFC421F8U, 0x0000004EU}, /* RGIDR_MODID[465]:IPMMURT106*/ + [442] = {0xFFC421FCU, 0x0000004EU}, /* RGIDR_MODID[466]:IPMMURT107*/ + [443] = {0xFFC42200U, 0x0000004BU}, /* RGIDR_MODID[467]:RTDM000*/ + [444] = {0xFFC42204U, 0x0000004BU}, /* RGIDR_MODID[468]:RTDM001*/ + [445] = {0xFFC42208U, 0x0000004BU}, /* RGIDR_MODID[469]:RTDM010*/ + [446] = {0xFFC4220CU, 0x0000004BU}, /* RGIDR_MODID[470]:RTDM011*/ + [447] = {0xFFC42210U, 0x0000004BU}, /* RGIDR_MODID[471]:RTDM012*/ + [448] = {0xFFC42214U, 0x0000004BU}, /* RGIDR_MODID[472]:RTDM013*/ + [449] = {0xFFC42218U, 0x0000004BU}, /* RGIDR_MODID[473]:RTDM014*/ + [450] = {0xFFC4221CU, 0x0000004BU}, /* RGIDR_MODID[474]:RTDM015*/ + [451] = {0xFFC42220U, 0x0000004BU}, /* RGIDR_MODID[475]:RTDM002*/ + [452] = {0xFFC42224U, 0x0000004BU}, /* RGIDR_MODID[476]:RTDM003*/ + [453] = {0xFFC42228U, 0x0000004BU}, /* RGIDR_MODID[477]:RTDM004*/ + [454] = {0xFFC4222CU, 0x0000004BU}, /* RGIDR_MODID[478]:RTDM005*/ + [455] = {0xFFC42230U, 0x0000004BU}, /* RGIDR_MODID[479]:RTDM006*/ + [456] = {0xFFC42234U, 0x0000004BU}, /* RGIDR_MODID[480]:RTDM007*/ + [457] = {0xFFC42238U, 0x0000004BU}, /* RGIDR_MODID[481]:RTDM008*/ + [458] = {0xFFC4223CU, 0x0000004BU}, /* RGIDR_MODID[482]:RTDM009*/ + [459] = {0xFFC42240U, 0x0000004BU}, /* RGIDR_MODID[483]:RTDM100*/ + [460] = {0xFFC42244U, 0x0000004BU}, /* RGIDR_MODID[484]:RTDM101*/ + [461] = {0xFFC42248U, 0x0000004BU}, /* RGIDR_MODID[485]:RTDM110*/ + [462] = {0xFFC4224CU, 0x0000004BU}, /* RGIDR_MODID[486]:RTDM111*/ + [463] = {0xFFC42250U, 0x0000004BU}, /* RGIDR_MODID[487]:RTDM112*/ + [464] = {0xFFC42254U, 0x0000004BU}, /* RGIDR_MODID[488]:RTDM113*/ + [465] = {0xFFC42258U, 0x0000004BU}, /* RGIDR_MODID[489]:RTDM114*/ + [466] = {0xFFC4225CU, 0x0000004BU}, /* RGIDR_MODID[490]:RTDM115*/ + [467] = {0xFFC42260U, 0x0000004BU}, /* RGIDR_MODID[491]:RTDM102*/ + [468] = {0xFFC42264U, 0x0000004BU}, /* RGIDR_MODID[492]:RTDM103*/ + [469] = {0xFFC42268U, 0x0000004BU}, /* RGIDR_MODID[493]:RTDM104*/ + [470] = {0xFFC4226CU, 0x0000004BU}, /* RGIDR_MODID[494]:RTDM105*/ + [471] = {0xFFC42270U, 0x0000004BU}, /* RGIDR_MODID[495]:RTDM106*/ + [472] = {0xFFC42274U, 0x0000004BU}, /* RGIDR_MODID[496]:RTDM107*/ + [473] = {0xFFC42278U, 0x0000004BU}, /* RGIDR_MODID[497]:RTDM108*/ + [474] = {0xFFC4227CU, 0x0000004BU}, /* RGIDR_MODID[498]:RTDM109*/ + [475] = {0xFFC42280U, 0x0000004BU}, /* RGIDR_MODID[499]:RTDM200*/ + [476] = {0xFFC42284U, 0x0000004BU}, /* RGIDR_MODID[500]:RTDM201*/ + [477] = {0xFFC42288U, 0x0000004BU}, /* RGIDR_MODID[501]:RTDM210*/ + [478] = {0xFFC4228CU, 0x0000004BU}, /* RGIDR_MODID[502]:RTDM211*/ + [479] = {0xFFC42290U, 0x0000004BU}, /* RGIDR_MODID[503]:RTDM212*/ + [480] = {0xFFC42294U, 0x0000004BU}, /* RGIDR_MODID[504]:RTDM213*/ + [481] = {0xFFC42298U, 0x0000004BU}, /* RGIDR_MODID[505]:RTDM214*/ + [482] = {0xFFC4229CU, 0x0000004BU}, /* RGIDR_MODID[506]:RTDM215*/ + [483] = {0xFFC422A0U, 0x0000004BU}, /* RGIDR_MODID[507]:RTDM202*/ + [484] = {0xFFC422A4U, 0x0000004BU}, /* RGIDR_MODID[508]:RTDM203*/ + [485] = {0xFFC422A8U, 0x0000004BU}, /* RGIDR_MODID[509]:RTDM204*/ + [486] = {0xFFC422ACU, 0x0000004BU}, /* RGIDR_MODID[510]:RTDM205*/ + [487] = {0xFFC422B0U, 0x0000004BU}, /* RGIDR_MODID[511]:RTDM206*/ + [488] = {0xFFC422B4U, 0x0000004BU}, /* RGIDR_MODID[512]:RTDM207*/ + [489] = {0xFFC422B8U, 0x0000004BU}, /* RGIDR_MODID[513]:RTDM208*/ + [490] = {0xFFC422BCU, 0x0000004BU}, /* RGIDR_MODID[514]:RTDM209*/ + [491] = {0xFFC422C0U, 0x0000004BU}, /* RGIDR_MODID[515]:RTDM300*/ + [492] = {0xFFC422C4U, 0x0000004BU}, /* RGIDR_MODID[516]:RTDM301*/ + [493] = {0xFFC422C8U, 0x0000004BU}, /* RGIDR_MODID[517]:RTDM310*/ + [494] = {0xFFC422CCU, 0x0000004BU}, /* RGIDR_MODID[518]:RTDM311*/ + [495] = {0xFFC422D0U, 0x0000004BU}, /* RGIDR_MODID[519]:RTDM312*/ + [496] = {0xFFC422D4U, 0x0000004BU}, /* RGIDR_MODID[520]:RTDM313*/ + [497] = {0xFFC422D8U, 0x0000004BU}, /* RGIDR_MODID[521]:RTDM314*/ + [498] = {0xFFC422DCU, 0x0000004BU}, /* RGIDR_MODID[522]:RTDM315*/ + [499] = {0xFFC422E0U, 0x0000004BU}, /* RGIDR_MODID[523]:RTDM302*/ + [500] = {0xFFC422E4U, 0x0000004BU}, /* RGIDR_MODID[524]:RTDM303*/ + [501] = {0xFFC422E8U, 0x0000004BU}, /* RGIDR_MODID[525]:RTDM304*/ + [502] = {0xFFC422ECU, 0x0000004BU}, /* RGIDR_MODID[526]:RTDM305*/ + [503] = {0xFFC422F0U, 0x0000004BU}, /* RGIDR_MODID[527]:RTDM306*/ + [504] = {0xFFC422F4U, 0x0000004BU}, /* RGIDR_MODID[528]:RTDM307*/ + [505] = {0xFFC422F8U, 0x0000004BU}, /* RGIDR_MODID[529]:RTDM308*/ + [506] = {0xFFC422FCU, 0x0000004BU}, /* RGIDR_MODID[530]:RTDM309*/ + [507] = {0xFFC42300U, 0x0000004EU}, /* RGIDR_MODID[531]:IPMMURT108*/ + [508] = {0xFFC42304U, 0x0000004EU}, /* RGIDR_MODID[532]:IPMMURT109*/ + [509] = {0xFFC42308U, 0x00000001U}, /* RGIDR_MODID[533]:SYSRAM01*/ + [510] = {0xFFC4230CU, 0x0000000BU}, /* RGIDR_MODID[534]:SYSRAM02*/ + [511] = {0xFFC42310U, 0x00000001U}, /* RGIDR_MODID[535]:SYSRAM03*/ + [512] = {0xFFC42314U, 0x00000001U}, /* RGIDR_MODID[536]:SYSRAM04*/ + [513] = {0xFFC42318U, 0x00000001U}, /* RGIDR_MODID[537]:SYSRAM05*/ + [514] = {0xFFC4231CU, 0x00000001U}, /* RGIDR_MODID[538]:SYSRAM06*/ + [515] = {0xFFC42320U, 0x00000000U}, /* RGIDR_MODID[539]:SYSRAM07*/ + [516] = {0xFFC42324U, 0x0000000BU}, /* RGIDR_MODID[540]:SYSRAM11*/ + [517] = {0xFFC42328U, 0x0000000BU}, /* RGIDR_MODID[541]:SYSRAM12*/ + [518] = {0xFFC4232CU, 0x0000000BU}, /* RGIDR_MODID[542]:SYSRAM13*/ + [519] = {0xFFC42330U, 0x0000000BU}, /* RGIDR_MODID[543]:SYSRAM14*/ + [520] = {0xFFC42334U, 0x0000000BU}, /* RGIDR_MODID[544]:SYSRAM15*/ + [521] = {0xFFC42338U, 0x0000000BU}, /* RGIDR_MODID[545]:SYSRAM16*/ + [522] = {0xFFC4233CU, 0x00000000U}, /* RGIDR_MODID[546]:SYSRAM17*/ + [523] = {0xFFC42360U, 0x00000002U}, /* RGIDR_MODID[547]:BKBUF*/ + [524] = {0xFFC42364U, 0x00000002U}, /* RGIDR_MODID[548]:AXICR52SS1*/ + [525] = {0xFFC42368U, 0x00000002U}, /* RGIDR_MODID[549]:AXICR52SS2*/ + [526] = {0xFF862000U, 0x0000000FU}, /* RGIDR_MODID[550]:ARSC0*/ + /* After setting */ /* RGIDR_MODID[551]:ARSC1*/ + /* After setting */ /* RGIDR_MODID[552]:ARSC2*/ + [527] = {0xFF86200CU, 0x0000000FU}, /* RGIDR_MODID[553]:ARSC3*/ + [528] = {0xFF862010U, 0x0000000FU}, /* RGIDR_MODID[554]:ARSC4*/ + [529] = {0xFF862014U, 0x0000000FU}, /* RGIDR_MODID[555]:ARSC5*/ + [530] = {0xFF862018U, 0x0000000FU}, /* RGIDR_MODID[556]:ARSC6*/ + [531] = {0xFF86201CU, 0x0000000FU}, /* RGIDR_MODID[557]:ARSC7*/ + [532] = {0xFF862020U, 0x00000000U}, /* RGIDR_MODID[558]:ARSC8*/ + [533] = {0xFF862024U, 0x0000000FU}, /* RGIDR_MODID[559]:ARSTM0*/ + /* After setting */ /* RGIDR_MODID[560]:ARSTM1*/ + [534] = {0xFF86202CU, 0x0000000EU}, /* RGIDR_MODID[561]:CSD1S*/ + [535] = {0xFF862030U, 0x0000000EU}, /* RGIDR_MODID[562]:AXIFBABUSTOP0*/ + [536] = {0xFF862034U, 0x0000000EU}, /* RGIDR_MODID[563]:AXIFBABUSTOP1*/ + /* After setting */ /* RGIDR_MODID[564]:ARSTM2*/ + [537] = {0xFF86203CU, 0x0000000FU}, /* RGIDR_MODID[565]:ARSTM3*/ + [538] = {0xFF862040U, 0x0000000FU}, /* RGIDR_MODID[566]:ARSTM4*/ + [539] = {0xFF862044U, 0x0000000FU}, /* RGIDR_MODID[567]:ARSTM5*/ + [540] = {0xFF862048U, 0x0000000FU}, /* RGIDR_MODID[568]:ARSTM6*/ + [541] = {0xFF86204CU, 0x0000000FU}, /* RGIDR_MODID[569]:ARSTM7*/ + [542] = {0xFF862050U, 0x00000000U}, /* RGIDR_MODID[570]:ARSTM8*/ + [543] = {0xFF862054U, 0x0000000FU}, /* RGIDR_MODID[571]:ECMTOP*/ + [544] = {0xFF862058U, 0x0000000EU}, /* RGIDR_MODID[572]:FBA*/ + [545] = {0xFF86205CU, 0x0000000EU}, /* RGIDR_MODID[573]:FBC*/ + [546] = {0xFF862060U, 0x0000000CU}, /* RGIDR_MODID[574]:AXICCI00*/ + [547] = {0xFF862064U, 0x0000000CU}, /* RGIDR_MODID[575]:AXICCI01*/ + [548] = {0xFF862068U, 0x0000000CU}, /* RGIDR_MODID[576]:AXICCI10*/ + [549] = {0xFF86206CU, 0x0000000CU}, /* RGIDR_MODID[577]:AXICCI11*/ + [550] = {0xFF862070U, 0x0000000CU}, /* RGIDR_MODID[578]:AXICCI12*/ + [551] = {0xFF862074U, 0x0000000CU}, /* RGIDR_MODID[579]:AXICCI13*/ + [552] = {0xFF862078U, 0x0000000CU}, /* RGIDR_MODID[580]:AXICCI14*/ + [553] = {0xFF86207CU, 0x0000000CU}, /* RGIDR_MODID[581]:AXICCI15*/ + [554] = {0xFF862080U, 0x0000000CU}, /* RGIDR_MODID[582]:AXICCI2*/ + [555] = {0xFF862084U, 0x0000000CU}, /* RGIDR_MODID[583]:AXICCI3*/ + [556] = {0xFF862088U, 0x0000000CU}, /* RGIDR_MODID[584]:AXICCI4*/ + [557] = {0xFF86208CU, 0x0000000CU}, /* RGIDR_MODID[585]:AXICCI5*/ + [558] = {0xFF862090U, 0x0000000CU}, /* RGIDR_MODID[586]:AXICCI6*/ + [559] = {0xFF862094U, 0x0000000CU}, /* RGIDR_MODID[587]:AXICCI7*/ + [560] = {0xFF862098U, 0x0000000CU}, /* RGIDR_MODID[588]:AXICCI8*/ + [561] = {0xFF86209CU, 0x0000000FU}, /* RGIDR_MODID[589]:AXICCI9*/ + [562] = {0xFF8620A0U, 0x0000000FU}, /* RGIDR_MODID[590]:ECMSTM*/ + [563] = {0xE7782000U, 0x0000002CU}, /* RGIDR_MODID[591]:DMASSI00*/ + [564] = {0xE7782004U, 0x0000002CU}, /* RGIDR_MODID[592]:DMASSI01*/ + [565] = {0xE7782008U, 0x0000002CU}, /* RGIDR_MODID[593]:DMASSI02*/ + [566] = {0xE778200CU, 0x0000002CU}, /* RGIDR_MODID[594]:DMASSI03*/ + [567] = {0xE7782010U, 0x0000002CU}, /* RGIDR_MODID[595]:DMASSI04*/ + [568] = {0xE7782014U, 0x0000004EU}, /* RGIDR_MODID[596]:DMAI2C0*/ + [569] = {0xE7782018U, 0x0000004EU}, /* RGIDR_MODID[597]:DMAI2C1*/ + [570] = {0xE778201CU, 0x0000004EU}, /* RGIDR_MODID[598]:DMAI2C2*/ + [571] = {0xE7782020U, 0x0000004EU}, /* RGIDR_MODID[599]:DMAI2C3*/ + [572] = {0xE7782024U, 0x0000004EU}, /* RGIDR_MODID[600]:DMAI2C4*/ + [573] = {0xE7782028U, 0x0000004EU}, /* RGIDR_MODID[601]:DMAI2C5*/ + [574] = {0xE778202CU, 0x0000002CU}, /* RGIDR_MODID[602]:DMASSI05*/ + [575] = {0xE7782030U, 0x0000002CU}, /* RGIDR_MODID[603]:DMASSI06*/ + [576] = {0xE7782034U, 0x0000002CU}, /* RGIDR_MODID[604]:DMASSI07*/ + [577] = {0xE67C2000U, 0x00000007U}, /* RGIDR_MODID[605]:ARMM*/ + /* After setting */ /* RGIDR_MODID[606]:AXIARNMM*/ + [578] = {0xE67C2008U, 0x0000000FU}, /* RGIDR_MODID[607]:ARSM0*/ + /* After setting */ /* RGIDR_MODID[608]:ARSM1*/ + /* After setting */ /* RGIDR_MODID[609]:ARSM2*/ + [579] = {0xE67C2014U, 0x0000000FU}, /* RGIDR_MODID[610]:AXIQOS0*/ + [580] = {0xE67C2018U, 0x0000000FU}, /* RGIDR_MODID[611]:AXIQOS1*/ + [581] = {0xE67C201CU, 0x0000000FU}, /* RGIDR_MODID[612]:AXIQOS2*/ + [582] = {0xE67C2020U, 0x0000000FU}, /* RGIDR_MODID[613]:AXIQOS3*/ + [583] = {0xE67C2024U, 0x0000000FU}, /* RGIDR_MODID[614]:AXIQOS4*/ + [584] = {0xE67C2028U, 0x0000000FU}, /* RGIDR_MODID[615]:AXIQOS5*/ + [585] = {0xE67C202CU, 0x0000000FU}, /* RGIDR_MODID[616]:AXIQOS6*/ + [586] = {0xE67C2030U, 0x0000000FU}, /* RGIDR_MODID[617]:AXIQOS7*/ + [587] = {0xE67C2034U, 0x0000000FU}, /* RGIDR_MODID[618]:ARSM3*/ + [588] = {0xE67C2038U, 0x0000000FU}, /* RGIDR_MODID[619]:ARSM4*/ + [589] = {0xE67C203CU, 0x0000000FU}, /* RGIDR_MODID[620]:ARSM5*/ + [590] = {0xE67C2040U, 0x0000000FU}, /* RGIDR_MODID[621]:ARSM6*/ + [591] = {0xE67C2044U, 0x0000000FU}, /* RGIDR_MODID[622]:ARSM7*/ + [592] = {0xE67C2048U, 0x00000000U}, /* RGIDR_MODID[623]:ARSM8*/ + [593] = {0xE67C204CU, 0x0000000BU}, /* RGIDR_MODID[624]:AXMM0*/ + [594] = {0xE67C2050U, 0x0000000BU}, /* RGIDR_MODID[625]:AXMM1*/ + [595] = {0xE67C2054U, 0x00000000U}, /* RGIDR_MODID[626]:AXMMPMON*/ + [596] = {0xE67C2058U, 0x0000000AU}, /* RGIDR_MODID[627]:CKMMM*/ + [597] = {0xE67C205CU, 0x0000000FU}, /* RGIDR_MODID[628]:ECMMM*/ + [598] = {0xE67C2060U, 0x0000000EU}, /* RGIDR_MODID[629]:FBADBSC0*/ + [599] = {0xE67C2064U, 0x0000000EU}, /* RGIDR_MODID[630]:FBADBSC1*/ + [600] = {0xE67C2068U, 0x0000000EU}, /* RGIDR_MODID[631]:FBAMM*/ + [601] = {0xE67C206CU, 0x0000004EU}, /* RGIDR_MODID[632]:IPMMUMM00*/ + [602] = {0xE67C2070U, 0x0000000FU}, /* RGIDR_MODID[633]:DBS0A0*/ + [603] = {0xE67C2074U, 0x0000000AU}, /* RGIDR_MODID[634]:DBS0A1*/ + [604] = {0xE67C2078U, 0x0000000FU}, /* RGIDR_MODID[635]:DBS1A0*/ + [605] = {0xE67C207CU, 0x0000000AU}, /* RGIDR_MODID[636]:DBS1A1*/ + [606] = {0xE67C2080U, 0x0000000FU}, /* RGIDR_MODID[637]:AXCIDBS*/ + [607] = {0xE67C2084U, 0x00000009U}, /* RGIDR_MODID[638]:FCPRC*/ + [608] = {0xE67C2088U, 0x0000000FU}, /* RGIDR_MODID[639]:DBS0D0*/ + [609] = {0xE67C208CU, 0x0000000AU}, /* RGIDR_MODID[640]:DBS0D1*/ + [610] = {0xE67C2090U, 0x0000000FU}, /* RGIDR_MODID[641]:DBS1D0*/ + [611] = {0xE67C2094U, 0x0000000AU}, /* RGIDR_MODID[642]:DBS1D1*/ + [612] = {0xE67C2098U, 0x0000000EU}, /* RGIDR_MODID[643]:FBADDR*/ + [613] = {0xE67C209CU, 0x0000004EU}, /* RGIDR_MODID[644]:IPMMUMM01*/ + [614] = {0xE67C20A0U, 0x0000004EU}, /* RGIDR_MODID[645]:IPMMUMM10*/ + [615] = {0xE67C20A4U, 0x0000004EU}, /* RGIDR_MODID[646]:IPMMUMM11*/ + [616] = {0xE67C20A8U, 0x0000004EU}, /* RGIDR_MODID[647]:IPMMUMM12*/ + [617] = {0xE67C20ACU, 0x0000004EU}, /* RGIDR_MODID[648]:IPMMUMM13*/ + [618] = {0xE67C20B0U, 0x0000004EU}, /* RGIDR_MODID[649]:IPMMUMM14*/ + [619] = {0xE67C20B4U, 0x0000004EU}, /* RGIDR_MODID[650]:IPMMUMM15*/ + [620] = {0xE67C20B8U, 0x0000004EU}, /* RGIDR_MODID[651]:IPMMUMM02*/ + [621] = {0xE67C20BCU, 0x0000004EU}, /* RGIDR_MODID[652]:IPMMUMM03*/ + [622] = {0xE67C20C0U, 0x0000004EU}, /* RGIDR_MODID[653]:IPMMUMM04*/ + [623] = {0xE67C20C4U, 0x0000004EU}, /* RGIDR_MODID[654]:IPMMUMM05*/ + [624] = {0xE67C20C8U, 0x0000004EU}, /* RGIDR_MODID[655]:IPMMUMM06*/ + [625] = {0xE67C20CCU, 0x0000004EU}, /* RGIDR_MODID[656]:IPMMUMM07*/ + [626] = {0xE67C20D0U, 0x0000004EU}, /* RGIDR_MODID[657]:IPMMUMM08*/ + [627] = {0xE67C20D4U, 0x0000004EU}, /* RGIDR_MODID[658]:IPMMUMM09*/ + [628] = {0xFF802000U, 0x0000000FU}, /* RGIDR_MODID[659]:ARSN0*/ + /* After setting */ /* RGIDR_MODID[660]:ARSN1*/ + /* After setting */ /* RGIDR_MODID[661]:ARSN2*/ + [629] = {0xFF80200CU, 0x0000000FU}, /* RGIDR_MODID[662]:ARSN3*/ + [630] = {0xFF802010U, 0x0000000FU}, /* RGIDR_MODID[663]:ARSN4*/ + [631] = {0xFF802014U, 0x0000000FU}, /* RGIDR_MODID[664]:ARSN5*/ + [632] = {0xFF802018U, 0x0000000FU}, /* RGIDR_MODID[665]:ARSN6*/ + [633] = {0xFF80201CU, 0x00000007U}, /* RGIDR_MODID[666]:ARSN7*/ + [634] = {0xFF802020U, 0x00000000U}, /* RGIDR_MODID[667]:ARSN8*/ + [635] = {0xFF802024U, 0x0000000FU}, /* RGIDR_MODID[668]:ECMTOP3*/ + [636] = {0xE7752000U, 0x0000000FU}, /* RGIDR_MODID[669]:ARSD00*/ + /* After setting */ /* RGIDR_MODID[670]:ARSD01*/ + /* After setting */ /* RGIDR_MODID[671]:ARSD02*/ + [637] = {0xE775200CU, 0x0000000FU}, /* RGIDR_MODID[672]:ARSD03*/ + [638] = {0xE7752010U, 0x0000000FU}, /* RGIDR_MODID[673]:ARSD04*/ + [639] = {0xE7752014U, 0x0000000FU}, /* RGIDR_MODID[674]:ARSD05*/ + [640] = {0xE7752018U, 0x0000000FU}, /* RGIDR_MODID[675]:ARSD06*/ + [641] = {0xE775201CU, 0x0000004AU}, /* RGIDR_MODID[676]:AXIFRAY*/ + [642] = {0xE7752020U, 0x0000000FU}, /* RGIDR_MODID[677]:AXIIPC*/ + [643] = {0xE7752028U, 0x0000004FU}, /* RGIDR_MODID[678]:AXIRPC*/ + [644] = {0xE775202CU, 0x0000000FU}, /* RGIDR_MODID[679]:AXISDHI0*/ + [645] = {0xE7752030U, 0x0000000FU}, /* RGIDR_MODID[680]:ARSD07*/ + [646] = {0xE7752034U, 0x00000000U}, /* RGIDR_MODID[681]:ARSD08*/ + [647] = {0xE7752038U, 0x0000000FU}, /* RGIDR_MODID[682]:ARSP00*/ + /* After setting */ /* RGIDR_MODID[683]:ARSP01*/ + /* After setting */ /* RGIDR_MODID[684]:ARSP02*/ + [648] = {0xE7752044U, 0x0000000FU}, /* RGIDR_MODID[685]:ARSP03*/ + [649] = {0xE7752048U, 0x0000000FU}, /* RGIDR_MODID[686]:ARSP04*/ + [650] = {0xE775204CU, 0x0000000FU}, /* RGIDR_MODID[687]:ARSP05*/ + [651] = {0xE7752050U, 0x0000000FU}, /* RGIDR_MODID[688]:ARSP06*/ + [652] = {0xE7752054U, 0x00000007U}, /* RGIDR_MODID[689]:ARSP07*/ + [653] = {0xE7752058U, 0x00000000U}, /* RGIDR_MODID[690]:ARSP08*/ + [654] = {0xE775205CU, 0x0000004EU}, /* RGIDR_MODID[691]:IPMMUDS001*/ + [655] = {0xE7752060U, 0x0000000AU}, /* RGIDR_MODID[692]:CKMPER0*/ + [656] = {0xE7752064U, 0x0000000FU}, /* RGIDR_MODID[693]:ECMPER0*/ + [657] = {0xE7752068U, 0x0000000EU}, /* RGIDR_MODID[694]:FBAPER0*/ + [658] = {0xE775206CU, 0x0000004EU}, /* RGIDR_MODID[695]:FSO0*/ + [659] = {0xE7752070U, 0x0000004EU}, /* RGIDR_MODID[696]:FSO1*/ + [660] = {0xE7752074U, 0x0000004EU}, /* RGIDR_MODID[697]:FSO10*/ + [661] = {0xE7752078U, 0x0000004EU}, /* RGIDR_MODID[698]:FSO2*/ + [662] = {0xE775207CU, 0x0000004EU}, /* RGIDR_MODID[699]:FSO3*/ + [663] = {0xE7752080U, 0x0000004EU}, /* RGIDR_MODID[700]:FSO4*/ + [664] = {0xE7752084U, 0x0000004EU}, /* RGIDR_MODID[701]:FSO5*/ + [665] = {0xE7752088U, 0x0000004EU}, /* RGIDR_MODID[702]:FSO6*/ + [666] = {0xE775208CU, 0x0000004EU}, /* RGIDR_MODID[703]:FSO7*/ + [667] = {0xE7752090U, 0x0000004EU}, /* RGIDR_MODID[704]:FSO8*/ + [668] = {0xE7752094U, 0x0000004EU}, /* RGIDR_MODID[705]:FSO9*/ + [669] = {0xE7752098U, 0x0000002CU}, /* RGIDR_MODID[706]:ADG*/ + [670] = {0xE775209CU, 0x0000000FU}, /* RGIDR_MODID[707]:ECMSD0*/ + [671] = {0xE77520A0U, 0x0000004EU}, /* RGIDR_MODID[708]:IPMMUDS010*/ + [672] = {0xE77520A4U, 0x0000004EU}, /* RGIDR_MODID[709]:IPMMUDS011*/ + [673] = {0xE77520A8U, 0x0000004EU}, /* RGIDR_MODID[710]:I2C0*/ + [674] = {0xE77520ACU, 0x0000004EU}, /* RGIDR_MODID[711]:I2C1*/ + [675] = {0xE77520B0U, 0x0000004EU}, /* RGIDR_MODID[712]:I2C2*/ + [676] = {0xE77520B4U, 0x0000004EU}, /* RGIDR_MODID[713]:I2C3*/ + [677] = {0xE77520B8U, 0x0000004EU}, /* RGIDR_MODID[714]:I2C4*/ + [678] = {0xE77520BCU, 0x0000004EU}, /* RGIDR_MODID[715]:I2C5*/ + [679] = {0xE77520C0U, 0x0000004EU}, /* RGIDR_MODID[716]:IPMMUDS012*/ + [680] = {0xE77520C4U, 0x0000000FU}, /* RGIDR_MODID[717]:IPC*/ + [681] = {0xE77520C8U, 0x0000004EU}, /* RGIDR_MODID[718]:IPMMUDS000*/ + [682] = {0xE77520CCU, 0x0000004EU}, /* RGIDR_MODID[719]:IPMMUDS013*/ + [683] = {0xE77520D0U, 0x0000004EU}, /* RGIDR_MODID[720]:IPMMUDS014*/ + [684] = {0xE77520D4U, 0x0000004EU}, /* RGIDR_MODID[721]:IPMMUDS015*/ + [685] = {0xE77520D8U, 0x0000004EU}, /* RGIDR_MODID[722]:IPMMUDS002*/ + [686] = {0xE77520DCU, 0x0000004EU}, /* RGIDR_MODID[723]:IPMMUDS003*/ + [687] = {0xE77520E0U, 0x0000004EU}, /* RGIDR_MODID[724]:IPMMUDS004*/ + [688] = {0xE77520E4U, 0x0000004EU}, /* RGIDR_MODID[725]:IPMMUDS005*/ + [689] = {0xE77520E8U, 0x0000002CU}, /* RGIDR_MODID[726]:SSI*/ + [690] = {0xE77520ECU, 0x0000004EU}, /* RGIDR_MODID[727]:IPMMUDS006*/ + [691] = {0xE77520F0U, 0x0000004EU}, /* RGIDR_MODID[728]:IPMMUDS007*/ + [692] = {0xE77520F4U, 0x0000000CU}, /* RGIDR_MODID[729]:SYDM1P*/ + [693] = {0xE77520F8U, 0x0000004EU}, /* RGIDR_MODID[730]:IPMMUDS008*/ + [694] = {0xE77520FCU, 0x0000000CU}, /* RGIDR_MODID[731]:SYDM2P*/ + [695] = {0xE7752100U, 0x0000004EU}, /* RGIDR_MODID[732]:IPMMUDS009*/ + [696] = {0xE7752240U, 0x0000000CU}, /* RGIDR_MODID[733]:SYDM100*/ + [697] = {0xE7752244U, 0x0000000CU}, /* RGIDR_MODID[734]:SYDM101*/ + [698] = {0xE7752248U, 0x0000000CU}, /* RGIDR_MODID[735]:SYDM110*/ + [699] = {0xE775224CU, 0x0000000CU}, /* RGIDR_MODID[736]:SYDM111*/ + [700] = {0xE7752250U, 0x0000000CU}, /* RGIDR_MODID[737]:SYDM112*/ + [701] = {0xE7752254U, 0x0000000CU}, /* RGIDR_MODID[738]:SYDM113*/ + [702] = {0xE7752258U, 0x0000000CU}, /* RGIDR_MODID[739]:SYDM114*/ + [703] = {0xE775225CU, 0x0000000CU}, /* RGIDR_MODID[740]:SYDM115*/ + [704] = {0xE7752260U, 0x0000000CU}, /* RGIDR_MODID[741]:SYDM102*/ + [705] = {0xE7752264U, 0x0000000CU}, /* RGIDR_MODID[742]:SYDM103*/ + [706] = {0xE7752268U, 0x0000000CU}, /* RGIDR_MODID[743]:SYDM104*/ + [707] = {0xE775226CU, 0x0000000CU}, /* RGIDR_MODID[744]:SYDM105*/ + [708] = {0xE7752270U, 0x0000000CU}, /* RGIDR_MODID[745]:SYDM106*/ + [709] = {0xE7752274U, 0x0000000CU}, /* RGIDR_MODID[746]:SYDM107*/ + [710] = {0xE7752278U, 0x0000000CU}, /* RGIDR_MODID[747]:SYDM108*/ + [711] = {0xE775227CU, 0x0000000CU}, /* RGIDR_MODID[748]:SYDM109*/ + [712] = {0xE7752280U, 0x0000000CU}, /* RGIDR_MODID[749]:SYDM200*/ + [713] = {0xE7752284U, 0x0000000CU}, /* RGIDR_MODID[750]:SYDM201*/ + [714] = {0xE7752288U, 0x0000000CU}, /* RGIDR_MODID[751]:SYDM210*/ + [715] = {0xE775228CU, 0x0000000CU}, /* RGIDR_MODID[752]:SYDM211*/ + [716] = {0xE7752290U, 0x0000000CU}, /* RGIDR_MODID[753]:SYDM212*/ + [717] = {0xE7752294U, 0x0000000CU}, /* RGIDR_MODID[754]:SYDM213*/ + [718] = {0xE7752298U, 0x0000000CU}, /* RGIDR_MODID[755]:SYDM214*/ + [719] = {0xE775229CU, 0x0000000CU}, /* RGIDR_MODID[756]:SYDM215*/ + [720] = {0xE77522A0U, 0x0000000CU}, /* RGIDR_MODID[757]:SYDM202*/ + [721] = {0xE77522A4U, 0x0000000CU}, /* RGIDR_MODID[758]:SYDM203*/ + [722] = {0xE77522A8U, 0x0000000CU}, /* RGIDR_MODID[759]:SYDM204*/ + [723] = {0xE77522ACU, 0x0000000CU}, /* RGIDR_MODID[760]:SYDM205*/ + [724] = {0xE77522B0U, 0x0000000CU}, /* RGIDR_MODID[761]:SYDM206*/ + [725] = {0xE77522B4U, 0x0000000CU}, /* RGIDR_MODID[762]:SYDM207*/ + [726] = {0xE77522B8U, 0x0000000CU}, /* RGIDR_MODID[763]:SYDM208*/ + [727] = {0xE77522BCU, 0x0000000CU}, /* RGIDR_MODID[764]:SYDM209*/ + [728] = {0xFE682000U, 0x0000000FU}, /* RGIDR_MODID[765]:ARVC0*/ + /* After setting */ /* RGIDR_MODID[766]:ARVC1*/ + /* After setting */ /* RGIDR_MODID[767]:ARVC2*/ + [729] = {0xFE68200CU, 0x0000000FU}, /* RGIDR_MODID[768]:ARVC3*/ + [730] = {0xFE682010U, 0x0000000EU}, /* RGIDR_MODID[769]:AXIFBABUSVC*/ + [731] = {0xFE682014U, 0x0000000FU}, /* RGIDR_MODID[770]:ARVC4*/ + [732] = {0xFE682018U, 0x0000000FU}, /* RGIDR_MODID[771]:ARVC5*/ + [733] = {0xFE68201CU, 0x0000000FU}, /* RGIDR_MODID[772]:ARVC6*/ + [734] = {0xFE682020U, 0x0000000FU}, /* RGIDR_MODID[773]:ARVC7*/ + [735] = {0xFE682024U, 0x00000000U}, /* RGIDR_MODID[774]:ARVC8*/ + [736] = {0xFE682028U, 0x0000000AU}, /* RGIDR_MODID[775]:CKMVC*/ + [737] = {0xFE68202CU, 0x0000000FU}, /* RGIDR_MODID[776]:ECMVC0*/ + [738] = {0xFE682030U, 0x0000004EU}, /* RGIDR_MODID[777]:IMR2*/ + [739] = {0xFE682034U, 0x0000004EU}, /* RGIDR_MODID[778]:IMR0*/ + [740] = {0xFE682038U, 0x0000004EU}, /* RGIDR_MODID[779]:IMR1*/ + [741] = {0xFE68203CU, 0x0000004EU}, /* RGIDR_MODID[780]:IPMMUVC01*/ + [742] = {0xFE682040U, 0x0000004EU}, /* RGIDR_MODID[781]:IPMMUVC10*/ + [743] = {0xFE682044U, 0x0000000CU}, /* RGIDR_MODID[782]:IMS0*/ + [744] = {0xFE682048U, 0x0000000CU}, /* RGIDR_MODID[783]:IMS1*/ + [745] = {0xFE68204CU, 0x0000004EU}, /* RGIDR_MODID[784]:IPMMUVC00*/ + [746] = {0xFE682050U, 0x0000004EU}, /* RGIDR_MODID[785]:IPMMUVC11*/ + [747] = {0xFE682054U, 0x0000004EU}, /* RGIDR_MODID[786]:IPMMUVC12*/ + [748] = {0xFE682058U, 0x0000004EU}, /* RGIDR_MODID[787]:IPMMUVC13*/ + [749] = {0xFE68205CU, 0x0000004EU}, /* RGIDR_MODID[788]:IPMMUVC14*/ + [750] = {0xFE682060U, 0x0000004EU}, /* RGIDR_MODID[789]:IPMMUVC15*/ + [751] = {0xFE682064U, 0x0000004EU}, /* RGIDR_MODID[790]:IPMMUVC02*/ + [752] = {0xFE682068U, 0x0000004EU}, /* RGIDR_MODID[791]:IPMMUVC03*/ + [753] = {0xFE68206CU, 0x0000004EU}, /* RGIDR_MODID[792]:IPMMUVC04*/ + [754] = {0xFE682070U, 0x0000004EU}, /* RGIDR_MODID[793]:IPMMUVC05*/ + [755] = {0xFE682074U, 0x0000004EU}, /* RGIDR_MODID[794]:IPMMUVC06*/ + [756] = {0xFE682078U, 0x0000004EU}, /* RGIDR_MODID[795]:IPMMUVC07*/ + [757] = {0xFE68207CU, 0x0000004EU}, /* RGIDR_MODID[796]:IPMMUVC08*/ + [758] = {0xFE682080U, 0x0000004EU}, /* RGIDR_MODID[797]:IPMMUVC09*/ + [759] = {0xFE682084U, 0x00000028U}, /* RGIDR_MODID[798]:IV1ES*/ + [760] = {0xFEBE2000U, 0x0000004EU}, /* RGIDR_MODID[799]:CSITOP0*/ + [761] = {0xFEBE2004U, 0x0000000FU}, /* RGIDR_MODID[800]:ARVI10*/ + /* After setting */ /* RGIDR_MODID[801]:ARVI11*/ + /* After setting */ /* RGIDR_MODID[802]:ARVI12*/ + [762] = {0xFEBE2010U, 0x0000000FU}, /* RGIDR_MODID[803]:ARVI13*/ + [763] = {0xFEBE2014U, 0x0000000FU}, /* RGIDR_MODID[804]:ARVI14*/ + [764] = {0xFEBE2018U, 0x0000000FU}, /* RGIDR_MODID[805]:ARVI15*/ + [765] = {0xFEBE201CU, 0x0000000FU}, /* RGIDR_MODID[806]:ARVI16*/ + [766] = {0xFEBE2020U, 0x0000000FU}, /* RGIDR_MODID[807]:ARVI17*/ + [767] = {0xFEBE2024U, 0x00000000U}, /* RGIDR_MODID[808]:ARVI18*/ + [768] = {0xFEBE2028U, 0x0000000AU}, /* RGIDR_MODID[809]:CKMVIO*/ + [769] = {0xFEBE202CU, 0x0000004EU}, /* RGIDR_MODID[810]:CSITOP1*/ + [770] = {0xFEBE2034U, 0x0000004EU}, /* RGIDR_MODID[811]:DSITLINK0*/ + [771] = {0xFEBE2038U, 0x0000004EU}, /* RGIDR_MODID[812]:DSITLINK1*/ + [772] = {0xFEBE203CU, 0x0000000FU}, /* RGIDR_MODID[813]:ECMVIO1*/ + [773] = {0xFEBE2044U, 0x0000004EU}, /* RGIDR_MODID[814]:IPMMUVI001*/ + [774] = {0xFEBE2048U, 0x0000000CU}, /* RGIDR_MODID[815]:FCPVX0*/ + [775] = {0xFEBE204CU, 0x0000000CU}, /* RGIDR_MODID[816]:FCPVX1*/ + [776] = {0xFEBE2058U, 0x0000004EU}, /* RGIDR_MODID[817]:IPMMUVI000*/ + [777] = {0xFEBE205CU, 0x0000004EU}, /* RGIDR_MODID[818]:IPMMUVI100*/ + [778] = {0xFEBE2060U, 0x0000004EU}, /* RGIDR_MODID[819]:IPMMUVI010*/ + [779] = {0xFEBE2064U, 0x0000004EU}, /* RGIDR_MODID[820]:IPMMUVI011*/ + [780] = {0xFEBE2068U, 0x0000004EU}, /* RGIDR_MODID[821]:VSPX0*/ + [781] = {0xFEBE206CU, 0x0000004EU}, /* RGIDR_MODID[822]:VSPX1*/ + [782] = {0xFEBE2078U, 0x0000004EU}, /* RGIDR_MODID[823]:IPMMUVI012*/ + [783] = {0xFEBE207CU, 0x0000004EU}, /* RGIDR_MODID[824]:IPMMUVI013*/ + [784] = {0xFEBE2080U, 0x0000004EU}, /* RGIDR_MODID[825]:IPMMUVI014*/ + [785] = {0xFEBE2084U, 0x0000004EU}, /* RGIDR_MODID[826]:IPMMUVI015*/ + [786] = {0xFEBE2088U, 0x0000004EU}, /* RGIDR_MODID[827]:IPMMUVI002*/ + [787] = {0xFEBE208CU, 0x0000004EU}, /* RGIDR_MODID[828]:IPMMUVI003*/ + [788] = {0xFEBE2090U, 0x0000004EU}, /* RGIDR_MODID[829]:IPMMUVI004*/ + [789] = {0xFEBE2094U, 0x0000004EU}, /* RGIDR_MODID[830]:IPMMUVI005*/ + [790] = {0xFEBE2098U, 0x0000004EU}, /* RGIDR_MODID[831]:IPMMUVI006*/ + [791] = {0xFEBE209CU, 0x0000004EU}, /* RGIDR_MODID[832]:IPMMUVI007*/ + [792] = {0xFEBE20A0U, 0x0000004EU}, /* RGIDR_MODID[833]:IPMMUVI008*/ + [793] = {0xFEBE20A4U, 0x0000004EU}, /* RGIDR_MODID[834]:IPMMUVI009*/ + [794] = {0xFEBE20A8U, 0x0000004EU}, /* RGIDR_MODID[835]:IPMMUVI101*/ + [795] = {0xFEBE20ACU, 0x0000004EU}, /* RGIDR_MODID[836]:IPMMUVI110*/ + [796] = {0xFEBE20B0U, 0x0000004EU}, /* RGIDR_MODID[837]:IPMMUVI111*/ + [797] = {0xFEBE20B4U, 0x0000004EU}, /* RGIDR_MODID[838]:IPMMUVI112*/ + [798] = {0xFEBE20B8U, 0x0000004EU}, /* RGIDR_MODID[839]:IPMMUVI113*/ + [799] = {0xFEBE20BCU, 0x0000004EU}, /* RGIDR_MODID[840]:IPMMUVI114*/ + [800] = {0xFEBE20C0U, 0x0000004EU}, /* RGIDR_MODID[841]:IPMMUVI115*/ + [801] = {0xFEBE20C4U, 0x0000004EU}, /* RGIDR_MODID[842]:IPMMUVI102*/ + [802] = {0xFEBE20C8U, 0x0000004EU}, /* RGIDR_MODID[843]:IPMMUVI103*/ + [803] = {0xFEBE20CCU, 0x0000004EU}, /* RGIDR_MODID[844]:IPMMUVI104*/ + [804] = {0xFEBE20D0U, 0x0000004EU}, /* RGIDR_MODID[845]:IPMMUVI105*/ + [805] = {0xFEBE20D4U, 0x0000004EU}, /* RGIDR_MODID[846]:IPMMUVI106*/ + [806] = {0xFEBE20D8U, 0x0000004EU}, /* RGIDR_MODID[847]:IPMMUVI107*/ + [807] = {0xFEBE20DCU, 0x0000004EU}, /* RGIDR_MODID[848]:IPMMUVI108*/ + [808] = {0xFEBE20E0U, 0x0000004EU}, /* RGIDR_MODID[849]:IPMMUVI109*/ + [809] = {0xFEBE2104U, 0x0000000EU}, /* RGIDR_MODID[850]:AXIFBABUSVIO*/ + [810] = {0xFEBF2000U, 0x0000000FU}, /* RGIDR_MODID[851]:ARVI0*/ + /* After setting */ /* RGIDR_MODID[852]:ARVI1*/ + /* After setting */ /* RGIDR_MODID[853]:ARVI2*/ + [811] = {0xFEBF200CU, 0x0000000FU}, /* RGIDR_MODID[854]:ARVI3*/ + [812] = {0xFEBF2010U, 0x0000000FU}, /* RGIDR_MODID[855]:ARVI4*/ + [813] = {0xFEBF2014U, 0x0000000FU}, /* RGIDR_MODID[856]:ARVI5*/ + [814] = {0xFEBF2018U, 0x0000000FU}, /* RGIDR_MODID[857]:ARVI6*/ + [815] = {0xFEBF201CU, 0x0000000FU}, /* RGIDR_MODID[858]:ARVI7*/ + [816] = {0xFEBF2020U, 0x00000000U}, /* RGIDR_MODID[859]:ARVI8*/ + [817] = {0xFEBF2024U, 0x0000000FU}, /* RGIDR_MODID[860]:ECMVIO0*/ + [818] = {0xFEBF2028U, 0x0000004EU}, /* RGIDR_MODID[861]:ISP0*/ + [819] = {0xFEBF202CU, 0x0000004EU}, /* RGIDR_MODID[862]:ISP0CORE*/ + [820] = {0xFEBF2030U, 0x0000004EU}, /* RGIDR_MODID[863]:ISP1*/ + [821] = {0xFEBF2034U, 0x0000004EU}, /* RGIDR_MODID[864]:ISP1CORE*/ + [822] = {0xFEBF2054U, 0x0000004EU}, /* RGIDR_MODID[865]:VIN00*/ + [823] = {0xFEBF2058U, 0x0000004EU}, /* RGIDR_MODID[866]:VIN01*/ + [824] = {0xFEBF205CU, 0x0000004EU}, /* RGIDR_MODID[867]:VIN02*/ + [825] = {0xFEBF2060U, 0x0000004EU}, /* RGIDR_MODID[868]:VIN03*/ + [826] = {0xFEBF2064U, 0x0000004EU}, /* RGIDR_MODID[869]:VIN04*/ + [827] = {0xFEBF2068U, 0x0000004EU}, /* RGIDR_MODID[870]:VIN05*/ + [828] = {0xFEBF206CU, 0x0000004EU}, /* RGIDR_MODID[871]:VIN06*/ + [829] = {0xFEBF2070U, 0x0000004EU}, /* RGIDR_MODID[872]:VIN07*/ + [830] = {0xFEBF2074U, 0x0000004EU}, /* RGIDR_MODID[873]:VIN10*/ + [831] = {0xFEBF2078U, 0x0000004EU}, /* RGIDR_MODID[874]:VIN11*/ + [832] = {0xFEBF207CU, 0x0000004EU}, /* RGIDR_MODID[875]:VIN12*/ + [833] = {0xFEBF2080U, 0x0000004EU}, /* RGIDR_MODID[876]:VIN13*/ + [834] = {0xFEBF2084U, 0x0000004EU}, /* RGIDR_MODID[877]:VIN14*/ + [835] = {0xFEBF2088U, 0x0000004EU}, /* RGIDR_MODID[878]:VIN15*/ + [836] = {0xFEBF208CU, 0x0000004EU}, /* RGIDR_MODID[879]:VIN16*/ + [837] = {0xFEBF2090U, 0x0000004EU}, /* RGIDR_MODID[880]:VIN17*/ + [838] = {0xE7B12000U, 0x0000000FU}, /* RGIDR_MODID[881]:ARVIP00*/ + /* After setting */ /* RGIDR_MODID[882]:ARVIP01*/ + /* After setting */ /* RGIDR_MODID[883]:ARVIP02*/ + [839] = {0xE7B1200CU, 0x0000000FU}, /* RGIDR_MODID[884]:ARVIP03*/ + [840] = {0xE7B12010U, 0x0000000EU}, /* RGIDR_MODID[885]:AXIFBABUSVIP0*/ + [841] = {0xE7B12014U, 0x0000000FU}, /* RGIDR_MODID[886]:ARVIP04*/ + [842] = {0xE7B12018U, 0x0000000FU}, /* RGIDR_MODID[887]:ARVIP05*/ + [843] = {0xE7B1201CU, 0x0000000FU}, /* RGIDR_MODID[888]:ARVIP06*/ + [844] = {0xE7B12020U, 0x00000007U}, /* RGIDR_MODID[889]:ARVIP07*/ + [845] = {0xE7B12024U, 0x00000000U}, /* RGIDR_MODID[890]:ARVIP08*/ + [846] = {0xE7B12028U, 0x0000000AU}, /* RGIDR_MODID[891]:CKMVIP*/ + [847] = {0xE7B1202CU, 0x0000000FU}, /* RGIDR_MODID[892]:ECMVIP0*/ + [848] = {0xE7B12030U, 0x0000004EU}, /* RGIDR_MODID[893]:IPMMUVIP000*/ + [849] = {0xE7B12038U, 0x0000004EU}, /* RGIDR_MODID[894]:SMPO0*/ + [850] = {0xE7B1203CU, 0x0000004EU}, /* RGIDR_MODID[895]:SMPS0*/ + [851] = {0xE7B12040U, 0x0000000CU}, /* RGIDR_MODID[896]:UMFL0*/ + [852] = {0xE7B12044U, 0x0000004EU}, /* RGIDR_MODID[897]:IPMMUVIP001*/ + [853] = {0xE7B12048U, 0x0000004EU}, /* RGIDR_MODID[898]:IPMMUVIP010*/ + [854] = {0xE7B1204CU, 0x0000004EU}, /* RGIDR_MODID[899]:IPMMUVIP011*/ + [855] = {0xE7B12050U, 0x0000004EU}, /* RGIDR_MODID[900]:UMFL0M_W*/ + [856] = {0xE7B12054U, 0x0000004EU}, /* RGIDR_MODID[901]:IPMMUVIP012*/ + [857] = {0xE7B12058U, 0x0000004EU}, /* RGIDR_MODID[902]:IPMMUVIP013*/ + [858] = {0xE7B1205CU, 0x0000004EU}, /* RGIDR_MODID[903]:IPMMUVIP014*/ + [859] = {0xE7B12060U, 0x0000004EU}, /* RGIDR_MODID[904]:IPMMUVIP015*/ + [860] = {0xE7B12064U, 0x0000004EU}, /* RGIDR_MODID[905]:IPMMUVIP002*/ + [861] = {0xE7B12068U, 0x0000004EU}, /* RGIDR_MODID[906]:IPMMUVIP003*/ + [862] = {0xE7B1206CU, 0x0000004EU}, /* RGIDR_MODID[907]:IPMMUVIP004*/ + [863] = {0xE7B12070U, 0x0000004EU}, /* RGIDR_MODID[908]:IPMMUVIP005*/ + [864] = {0xE7B12074U, 0x0000004EU}, /* RGIDR_MODID[909]:IPMMUVIP006*/ + [865] = {0xE7B12078U, 0x0000004EU}, /* RGIDR_MODID[910]:IPMMUVIP007*/ + [866] = {0xE7B1207CU, 0x0000004EU}, /* RGIDR_MODID[911]:IPMMUVIP008*/ + [867] = {0xE7B12080U, 0x0000004EU}, /* RGIDR_MODID[912]:IPMMUVIP009*/ + [868] = {0xE7B42000U, 0x0000000FU}, /* RGIDR_MODID[913]:ARVIP10*/ + /* After setting */ /* RGIDR_MODID[914]:ARVIP11*/ + /* After setting */ /* RGIDR_MODID[915]:ARVIP12*/ + [869] = {0xE7B4200CU, 0x0000000FU}, /* RGIDR_MODID[916]:ARVIP13*/ + [870] = {0xE7B42010U, 0x0000000EU}, /* RGIDR_MODID[917]:AXIFBABUSVIP1*/ + [871] = {0xE7B42014U, 0x0000000FU}, /* RGIDR_MODID[918]:ARVIIP14*/ + [872] = {0xE7B42018U, 0x0000000FU}, /* RGIDR_MODID[919]:ARVIIP15*/ + [873] = {0xE7B4201CU, 0x0000000FU}, /* RGIDR_MODID[920]:ARVIIP16*/ + [874] = {0xE7B42020U, 0x0000000FU}, /* RGIDR_MODID[921]:ARVIIP17*/ + [875] = {0xE7B42024U, 0x00000000U}, /* RGIDR_MODID[922]:ARVIIP18*/ + [876] = {0xE7B42038U, 0x0000000FU}, /* RGIDR_MODID[923]:ECMVIP1*/ + [877] = {0xE7B4203CU, 0x0000004EU}, /* RGIDR_MODID[924]:IPMMUVIP101*/ + [878] = {0xE7B42040U, 0x0000004EU}, /* RGIDR_MODID[925]:IPMMUVIP100*/ + [879] = {0xE7B42044U, 0x0000004EU}, /* RGIDR_MODID[926]:IPMMUVIP110*/ + [880] = {0xE7B42048U, 0x0000004EU}, /* RGIDR_MODID[927]:IPMMUVIP111*/ + [881] = {0xE7B4204CU, 0x0000004EU}, /* RGIDR_MODID[928]:IPMMUVIP112*/ + [882] = {0xE7B42050U, 0x0000004EU}, /* RGIDR_MODID[929]:IPMMUVIP113*/ + [883] = {0xE7B42054U, 0x0000004EU}, /* RGIDR_MODID[930]:IPMMUVIP114*/ + [884] = {0xE7B42058U, 0x0000004EU}, /* RGIDR_MODID[931]:IPMMUVIP115*/ + [885] = {0xE7B4205CU, 0x0000004EU}, /* RGIDR_MODID[932]:IPMMUVIP102*/ + [886] = {0xE7B42060U, 0x0000004EU}, /* RGIDR_MODID[933]:IPMMUVIP103*/ + [887] = {0xE7B42064U, 0x0000004EU}, /* RGIDR_MODID[934]:IPMMUVIP104*/ + [888] = {0xE7B42068U, 0x0000004EU}, /* RGIDR_MODID[935]:IPMMUVIP105*/ + [889] = {0xE7B4206CU, 0x0000004EU}, /* RGIDR_MODID[936]:IPMMUVIP106*/ + [890] = {0xE7B42070U, 0x0000004EU}, /* RGIDR_MODID[937]:IPMMUVIP107*/ + [891] = {0xE7B42074U, 0x0000004EU}, /* RGIDR_MODID[938]:IPMMUVIP108*/ + [892] = {0xE7B42078U, 0x0000004EU}, /* RGIDR_MODID[939]:IPMMUVIP109*/ + [893] = {0xE7B42118U, 0x00000004U}, /* RGIDR_MODID[940]:PAP*/ + [894] = {0xEB802000U, 0x0000000FU}, /* RGIDR_MODID[941]:ARDSP0*/ + /* After setting */ /* RGIDR_MODID[942]:ARDSP1*/ + /* After setting */ /* RGIDR_MODID[943]:ARDSP2*/ + [895] = {0xEB80200CU, 0x0000000FU}, /* RGIDR_MODID[944]:ARDSP3*/ + [896] = {0xEB802010U, 0x0000000FU}, /* RGIDR_MODID[945]:ARDSP4*/ + [897] = {0xEB802014U, 0x0000000FU}, /* RGIDR_MODID[946]:ARDSP5*/ + [898] = {0xEB802018U, 0x0000000FU}, /* RGIDR_MODID[947]:ARDSP6*/ + [899] = {0xEB80201CU, 0x0000000FU}, /* RGIDR_MODID[948]:ARDSP7*/ + [900] = {0xEB802020U, 0x0000000FU}, /* RGIDR_MODID[949]:ECMDSP*/ + [901] = {0xEB802024U, 0x0000000CU}, /* RGIDR_MODID[950]:AXIDSP0*/ + [902] = {0xEB802028U, 0x0000000CU}, /* RGIDR_MODID[951]:AXIDSP1*/ + [903] = {0xEB80202CU, 0x0000000CU}, /* RGIDR_MODID[952]:AXIDSP2*/ + [904] = {0xEB802030U, 0x0000000CU}, /* RGIDR_MODID[953]:AXIDSP3*/ + [906] = {0xE67B9660U, 0x0000000FU}, /* RGIDR_MODID[954]:ARCC*/ + [905] = {0xE67B9674U, 0x0000000FU}, /* RGIDR_MODID[955]:ARRTRAM*/ + [907] = {0xE7752024U, 0x00000000U}, /* RGIDR_MODID[956]:RSV0*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_w_tbl" +#else +__attribute__ ((section(".rgid_w_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_write_tbl[] = { + [0] = {0xFFC82400U, 0x0000000EU}, /* RGIDW_MODID[0]:ARMGC0*/ + [1] = {0xFFC82404U, 0x0000000EU}, /* RGIDW_MODID[1]:ARMGC1*/ + [2] = {0xFFC82408U, 0x00000000U}, /* RGIDW_MODID[2]:ARMGC2*/ + [3] = {0xFFC8240CU, 0x00000002U}, /* RGIDW_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDW_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDW_MODID[5]:ARRT02*/ + [4] = {0xFFC82418U, 0x00000001U}, /* RGIDW_MODID[6]:ARRT03*/ + [5] = {0xFFC8241CU, 0x00000002U}, /* RGIDW_MODID[7]:ARRT04*/ + [6] = {0xFFC82420U, 0x00000001U}, /* RGIDW_MODID[8]:ARRT05*/ + [7] = {0xFFC82424U, 0x00000002U}, /* RGIDW_MODID[9]:ARRT06*/ + [8] = {0xFFC82428U, 0x00000002U}, /* RGIDW_MODID[10]:ARRT07*/ + [9] = {0xFFC8242CU, 0x00000000U}, /* RGIDW_MODID[11]:ARRT08*/ + [10] = {0xFFC82430U, 0x00000001U}, /* RGIDW_MODID[12]:LIFEC0*/ + [11] = {0xFFC82434U, 0x0000000EU}, /* RGIDW_MODID[13]:SWDT*/ + [12] = {0xFFC82438U, 0x0000006EU}, /* RGIDW_MODID[14]:TMU0*/ + [13] = {0xFFC8243CU, 0x0000000EU}, /* RGIDW_MODID[15]:WDT*/ + [14] = {0xFFC82440U, 0x0000000EU}, /* RGIDW_MODID[16]:WWDT0*/ + [15] = {0xFFC82444U, 0x0000000EU}, /* RGIDW_MODID[17]:WWDT1*/ + [16] = {0xFFC82448U, 0x0000000EU}, /* RGIDW_MODID[18]:WWDT2*/ + [17] = {0xFFC8244CU, 0x0000000EU}, /* RGIDW_MODID[19]:WWDT3*/ + [18] = {0xFFC82450U, 0x0000000EU}, /* RGIDW_MODID[20]:WWDT4*/ + [19] = {0xFFC82454U, 0x0000000EU}, /* RGIDW_MODID[21]:WWDT5*/ + [20] = {0xFFC82458U, 0x0000000EU}, /* RGIDW_MODID[22]:WWDT6*/ + [21] = {0xFFC82468U, 0x0000000AU}, /* RGIDW_MODID[23]:ECMRT3*/ + [22] = {0xE6002400U, 0x00000006U}, /* RGIDW_MODID[24]:ADVFSC*/ + [23] = {0xE6002404U, 0x0000000FU}, /* RGIDW_MODID[25]:APMU0*/ + [24] = {0xE6002408U, 0x00000002U}, /* RGIDW_MODID[26]:APMU1*/ + [25] = {0xE600240CU, 0x00000000U}, /* RGIDW_MODID[27]:APMU10*/ + [26] = {0xE6002410U, 0x00000000U}, /* RGIDW_MODID[28]:APMU11*/ + [27] = {0xE6002414U, 0x00000000U}, /* RGIDW_MODID[29]:APMU12*/ + [28] = {0xE6002418U, 0x00000000U}, /* RGIDW_MODID[30]:APMU13*/ + [29] = {0xE600241CU, 0x00000000U}, /* RGIDW_MODID[31]:APMU14*/ + [30] = {0xE6002420U, 0x00000000U}, /* RGIDW_MODID[32]:APMU15*/ + [31] = {0xE6002424U, 0x00000004U}, /* RGIDW_MODID[33]:APMU2*/ + [32] = {0xE6002428U, 0x00000004U}, /* RGIDW_MODID[34]:APMU3*/ + [33] = {0xE600242CU, 0x00000000U}, /* RGIDW_MODID[35]:APMU4*/ + [34] = {0xE6002430U, 0x00000000U}, /* RGIDW_MODID[36]:APMU5*/ + [35] = {0xE6002434U, 0x00000000U}, /* RGIDW_MODID[37]:APMU6*/ + [36] = {0xE6002438U, 0x00000000U}, /* RGIDW_MODID[38]:APMU7*/ + [37] = {0xE600243CU, 0x00000000U}, /* RGIDW_MODID[39]:APMU8*/ + [38] = {0xE6002440U, 0x00000000U}, /* RGIDW_MODID[40]:APMU9*/ + [39] = {0xE6002444U, 0x00000002U}, /* RGIDW_MODID[41]:ARS00*/ + /* After setting */ /* RGIDW_MODID[42]:ARS01*/ + /* After setting */ /* RGIDW_MODID[43]:ARS02*/ + [40] = {0xE6002450U, 0x00000001U}, /* RGIDW_MODID[44]:ARS03*/ + [41] = {0xE6002454U, 0x00000002U}, /* RGIDW_MODID[45]:ARS04*/ + [42] = {0xE6002458U, 0x00000001U}, /* RGIDW_MODID[46]:ARS05*/ + [43] = {0xE600245CU, 0x00000002U}, /* RGIDW_MODID[47]:ARS06*/ + [44] = {0xE6002460U, 0x00000002U}, /* RGIDW_MODID[48]:ARS07*/ + [45] = {0xE6002464U, 0x00000000U}, /* RGIDW_MODID[49]:ARS08*/ + [46] = {0xE6002468U, 0x0000000EU}, /* RGIDW_MODID[50]:CMT0*/ + [47] = {0xE600246CU, 0x0000000EU}, /* RGIDW_MODID[51]:CMT1*/ + [48] = {0xE6002470U, 0x0000000EU}, /* RGIDW_MODID[52]:CMT2*/ + [49] = {0xE6002474U, 0x0000000EU}, /* RGIDW_MODID[53]:CMT3*/ + [50] = {0xE6002478U, 0x0000000AU}, /* RGIDW_MODID[54]:CKM*/ + [51] = {0xE600247CU, 0x0000000EU}, /* RGIDW_MODID[55]:DBE*/ + [52] = {0xE6002480U, 0x0000000EU}, /* RGIDW_MODID[56]:IRQC*/ + [53] = {0xE6002484U, 0x0000000AU}, /* RGIDW_MODID[57]:ECMPS0*/ + [54] = {0xE6002488U, 0x0000000BU}, /* RGIDW_MODID[58]:OTP0*/ + [55] = {0xE600248CU, 0x0000000FU}, /* RGIDW_MODID[59]:OTP1*/ + [56] = {0xE600249CU, 0x0000000EU}, /* RGIDW_MODID[60]:SCMT*/ + [57] = {0xE60024A8U, 0x0000004AU}, /* RGIDW_MODID[61]:TSC1*/ + [58] = {0xE60024ACU, 0x0000004AU}, /* RGIDW_MODID[62]:TSC2*/ + [59] = {0xE60024B0U, 0x0000004AU}, /* RGIDW_MODID[63]:TSC3*/ + [60] = {0xE60024B4U, 0x0000004AU}, /* RGIDW_MODID[64]:TSC4*/ + [61] = {0xE60024B8U, 0x00000006U}, /* RGIDW_MODID[65]:UCMT*/ + [62] = {0xE6002500U, 0x0000006FU}, /* RGIDW_MODID[66]:CPG0*/ + [63] = {0xE6002504U, 0x0000000AU}, /* RGIDW_MODID[67]:CPG1*/ + [64] = {0xE6002508U, 0x0000004EU}, /* RGIDW_MODID[68]:CPG2*/ + [65] = {0xE600250CU, 0x00000028U}, /* RGIDW_MODID[69]:CPG3*/ + [66] = {0xE6002510U, 0x0000006FU}, /* RGIDW_MODID[70]:PFC00*/ + [67] = {0xE6002514U, 0x0000000AU}, /* RGIDW_MODID[71]:PFC01*/ + [68] = {0xE6002518U, 0x0000004EU}, /* RGIDW_MODID[72]:PFC02*/ + [69] = {0xE600251CU, 0x00000028U}, /* RGIDW_MODID[73]:PFC03*/ + [70] = {0xE6002520U, 0x0000006FU}, /* RGIDW_MODID[74]:PFC10*/ + [71] = {0xE6002524U, 0x0000000AU}, /* RGIDW_MODID[75]:PFC11*/ + [72] = {0xE6002528U, 0x0000004EU}, /* RGIDW_MODID[76]:PFC12*/ + [73] = {0xE600252CU, 0x00000028U}, /* RGIDW_MODID[77]:PFC13*/ + [74] = {0xE6002530U, 0x0000006FU}, /* RGIDW_MODID[78]:PFC20*/ + [75] = {0xE6002534U, 0x0000000AU}, /* RGIDW_MODID[79]:PFC21*/ + [76] = {0xE6002538U, 0x0000004EU}, /* RGIDW_MODID[80]:PFC22*/ + [77] = {0xE600253CU, 0x00000028U}, /* RGIDW_MODID[81]:PFC23*/ + [78] = {0xE6002540U, 0x0000006FU}, /* RGIDW_MODID[82]:PFC30*/ + [79] = {0xE6002544U, 0x0000000AU}, /* RGIDW_MODID[83]:PFC31*/ + [80] = {0xE6002548U, 0x0000004EU}, /* RGIDW_MODID[84]:PFC32*/ + [81] = {0xE600254CU, 0x00000028U}, /* RGIDW_MODID[85]:PFC33*/ + [82] = {0xE6002550U, 0x0000006FU}, /* RGIDW_MODID[86]:PFCS0*/ + [83] = {0xE6002554U, 0x0000000AU}, /* RGIDW_MODID[87]:PFCS1*/ + [84] = {0xE6002558U, 0x0000004EU}, /* RGIDW_MODID[88]:PFCS2*/ + [85] = {0xE600255CU, 0x00000028U}, /* RGIDW_MODID[89]:PFCS3*/ + [86] = {0xE6002560U, 0x0000006FU}, /* RGIDW_MODID[90]:RESET0*/ + [87] = {0xE6002564U, 0x0000000AU}, /* RGIDW_MODID[91]:RESET1*/ + [88] = {0xE6002568U, 0x0000004EU}, /* RGIDW_MODID[92]:RESET2*/ + [89] = {0xE600256CU, 0x00000028U}, /* RGIDW_MODID[93]:RESET3*/ + [90] = {0xE6002570U, 0x0000006FU}, /* RGIDW_MODID[94]:SYS0*/ + [91] = {0xE6002574U, 0x0000000AU}, /* RGIDW_MODID[95]:SYS1*/ + [92] = {0xE6002578U, 0x0000004EU}, /* RGIDW_MODID[96]:SYS2*/ + [93] = {0xE600257CU, 0x00000028U}, /* RGIDW_MODID[97]:SYS3*/ + [94] = {0xE7762400U, 0x0000000EU}, /* RGIDW_MODID[98]:DMAMSI0*/ + [95] = {0xE7762404U, 0x0000000EU}, /* RGIDW_MODID[99]:DMAMSI1*/ + [96] = {0xE7762408U, 0x0000000EU}, /* RGIDW_MODID[100]:DMAMSI2*/ + [97] = {0xE776240CU, 0x0000000EU}, /* RGIDW_MODID[101]:DMAMSI3*/ + [98] = {0xE7762410U, 0x0000000EU}, /* RGIDW_MODID[102]:DMAMSI4*/ + [99] = {0xE7762414U, 0x0000000EU}, /* RGIDW_MODID[103]:DMAMSI5*/ + [100] = {0xE7762418U, 0x0000000AU}, /* RGIDW_MODID[104]:ECMSP3*/ + [101] = {0xE7762424U, 0x00000002U}, /* RGIDW_MODID[105]:ARSP30*/ + /* After setting */ /* RGIDW_MODID[106]:ARSP31*/ + /* After setting */ /* RGIDW_MODID[107]:ARSP32*/ + [102] = {0xE7762430U, 0x00000001U}, /* RGIDW_MODID[108]:ARSP33*/ + [103] = {0xE7762434U, 0x00000002U}, /* RGIDW_MODID[109]:ARSP34*/ + [104] = {0xE7762438U, 0x00000001U}, /* RGIDW_MODID[110]:ARSP35*/ + [105] = {0xE776243CU, 0x00000002U}, /* RGIDW_MODID[111]:ARSP36*/ + [106] = {0xE7762440U, 0x00000002U}, /* RGIDW_MODID[112]:ARSP37*/ + [107] = {0xE7762444U, 0x00000000U}, /* RGIDW_MODID[113]:ARSP38*/ + [108] = {0xE7762448U, 0x0000000EU}, /* RGIDW_MODID[114]:MSI0*/ + [109] = {0xE776244CU, 0x0000000EU}, /* RGIDW_MODID[115]:MSI1*/ + [110] = {0xE7762450U, 0x0000000EU}, /* RGIDW_MODID[116]:MSI2*/ + [111] = {0xE7762454U, 0x0000000EU}, /* RGIDW_MODID[117]:MSI3*/ + [112] = {0xE7762458U, 0x0000000EU}, /* RGIDW_MODID[118]:MSI4*/ + [113] = {0xE776245CU, 0x0000000EU}, /* RGIDW_MODID[119]:MSI5*/ + [114] = {0xE7792400U, 0x00000002U}, /* RGIDW_MODID[120]:ARSP40*/ + /* After setting */ /* RGIDW_MODID[121]:ARSP41*/ + /* After setting */ /* RGIDW_MODID[122]:ARSP42*/ + [115] = {0xE779240CU, 0x00000001U}, /* RGIDW_MODID[123]:ARSP43*/ + [116] = {0xE7792410U, 0x00000002U}, /* RGIDW_MODID[124]:ARSP44*/ + [117] = {0xE7792414U, 0x00000001U}, /* RGIDW_MODID[125]:ARSP45*/ + [118] = {0xE7792418U, 0x00000002U}, /* RGIDW_MODID[126]:ARSP46*/ + [119] = {0xE779241CU, 0x00000002U}, /* RGIDW_MODID[127]:ARSP47*/ + [120] = {0xE7792420U, 0x00000000U}, /* RGIDW_MODID[128]:ARSP48*/ + [121] = {0xE7792424U, 0x0000004FU}, /* RGIDW_MODID[129]:DMAHSCIF0*/ + [122] = {0xE7792428U, 0x0000004FU}, /* RGIDW_MODID[130]:DMAHSCIF1*/ + [123] = {0xE779242CU, 0x0000004FU}, /* RGIDW_MODID[131]:DMAHSCIF2*/ + [124] = {0xE7792430U, 0x0000004FU}, /* RGIDW_MODID[132]:DMAHSCIF3*/ + [125] = {0xE7792434U, 0x0000004FU}, /* RGIDW_MODID[133]:DMASCIF0*/ + [126] = {0xE7792438U, 0x0000004FU}, /* RGIDW_MODID[134]:DMASCIF1*/ + [127] = {0xE779243CU, 0x0000004FU}, /* RGIDW_MODID[135]:DMASCIF3*/ + [128] = {0xE7792440U, 0x0000004FU}, /* RGIDW_MODID[136]:DMASCIF4*/ + [129] = {0xE7792444U, 0x0000000AU}, /* RGIDW_MODID[137]:ECMSP4*/ + [130] = {0xE7792448U, 0x0000004FU}, /* RGIDW_MODID[138]:HSCIF0*/ + [131] = {0xE779244CU, 0x0000004FU}, /* RGIDW_MODID[139]:HSCIF1*/ + [132] = {0xE7792450U, 0x0000004FU}, /* RGIDW_MODID[140]:HSCIF2*/ + [133] = {0xE7792454U, 0x0000004FU}, /* RGIDW_MODID[141]:HSCIF3*/ + [134] = {0xE7792458U, 0x0000004FU}, /* RGIDW_MODID[142]:SCIF0*/ + [135] = {0xE779245CU, 0x0000004FU}, /* RGIDW_MODID[143]:SCIF1*/ + [136] = {0xE7792460U, 0x0000004FU}, /* RGIDW_MODID[144]:SCIF3*/ + [137] = {0xE7792464U, 0x0000004FU}, /* RGIDW_MODID[145]:SCIF4*/ + [138] = {0xE7792468U, 0x0000006EU}, /* RGIDW_MODID[146]:TMU1*/ + [139] = {0xE779246CU, 0x0000006EU}, /* RGIDW_MODID[147]:TMU2*/ + [140] = {0xE7792470U, 0x0000006EU}, /* RGIDW_MODID[148]:TMU3*/ + [141] = {0xE7792474U, 0x0000006EU}, /* RGIDW_MODID[149]:TMU4*/ + [142] = {0xE7792478U, 0x0000004AU}, /* RGIDW_MODID[150]:CANFD*/ + [143] = {0xE779247CU, 0x0000004AU}, /* RGIDW_MODID[151]:DMACANFD*/ + [144] = {0xE7792480U, 0x00000002U}, /* RGIDW_MODID[152]:DMATPU0*/ + [145] = {0xE7792484U, 0x00000002U}, /* RGIDW_MODID[153]:PWM0*/ + [146] = {0xE7792488U, 0x00000002U}, /* RGIDW_MODID[154]:PWM1*/ + [147] = {0xE779248CU, 0x00000002U}, /* RGIDW_MODID[155]:PWM2*/ + [148] = {0xE7792490U, 0x00000002U}, /* RGIDW_MODID[156]:PWM3*/ + [149] = {0xE7792494U, 0x00000002U}, /* RGIDW_MODID[157]:PWM4*/ + [150] = {0xE7792498U, 0x00000002U}, /* RGIDW_MODID[158]:PWM5*/ + [151] = {0xE779249CU, 0x00000002U}, /* RGIDW_MODID[159]:PWM6*/ + [152] = {0xE77924A0U, 0x00000002U}, /* RGIDW_MODID[160]:PWM7*/ + [153] = {0xE77924A4U, 0x00000002U}, /* RGIDW_MODID[161]:PWM8*/ + [154] = {0xE77924A8U, 0x00000002U}, /* RGIDW_MODID[162]:PWM9*/ + [155] = {0xE77924ACU, 0x00000002U}, /* RGIDW_MODID[163]:TPU0*/ + [156] = {0xFE672400U, 0x00000002U}, /* RGIDW_MODID[164]:ARVC10*/ + /* After setting */ /* RGIDW_MODID[165]:ARVC11*/ + /* After setting */ /* RGIDW_MODID[166]:ARVC12*/ + [157] = {0xFE67240CU, 0x00000001U}, /* RGIDW_MODID[167]:ARVC13*/ + [158] = {0xFE672410U, 0x00000002U}, /* RGIDW_MODID[168]:ARVC14*/ + [159] = {0xFE672414U, 0x00000001U}, /* RGIDW_MODID[169]:ARVC15*/ + [160] = {0xFE672418U, 0x00000002U}, /* RGIDW_MODID[170]:ARVC16*/ + [161] = {0xFE67241CU, 0x00000002U}, /* RGIDW_MODID[171]:ARVC17*/ + [162] = {0xFE672420U, 0x00000000U}, /* RGIDW_MODID[172]:ARVC18*/ + [163] = {0xFE672424U, 0x0000000AU}, /* RGIDW_MODID[173]:ECMVC1*/ + [164] = {0xFE672428U, 0x00000028U}, /* RGIDW_MODID[174]:FCPCS*/ + [165] = {0xFE67242CU, 0x00000028U}, /* RGIDW_MODID[175]:VCP4LC*/ + [166] = {0xFE672430U, 0x00000028U}, /* RGIDW_MODID[176]:VCP4LV*/ + [167] = {0xFEBD2400U, 0x00000002U}, /* RGIDW_MODID[177]:ARVI40*/ + /* After setting */ /* RGIDW_MODID[178]:ARVI41*/ + /* After setting */ /* RGIDW_MODID[179]:ARVI42*/ + [168] = {0xFEBD240CU, 0x00000001U}, /* RGIDW_MODID[180]:ARVI43*/ + [169] = {0xFEBD2410U, 0x00000002U}, /* RGIDW_MODID[181]:ARVI44*/ + [170] = {0xFEBD2414U, 0x00000001U}, /* RGIDW_MODID[182]:ARVI45*/ + [171] = {0xFEBD2418U, 0x00000002U}, /* RGIDW_MODID[183]:ARVI46*/ + [172] = {0xFEBD241CU, 0x00000002U}, /* RGIDW_MODID[184]:ARVI47*/ + [173] = {0xFEBD2420U, 0x00000000U}, /* RGIDW_MODID[185]:ARVI48*/ + [174] = {0xFEBD2424U, 0x0000000FU}, /* RGIDW_MODID[186]:DIS0*/ + [175] = {0xFEBD242CU, 0x0000000FU}, /* RGIDW_MODID[187]:DSC*/ + [176] = {0xFEBD2430U, 0x0000000EU}, /* RGIDW_MODID[188]:ECMVIO2*/ + [177] = {0xFEBD2434U, 0x0000000FU}, /* RGIDW_MODID[189]:FCPVD0*/ + [178] = {0xFEBD2438U, 0x0000000FU}, /* RGIDW_MODID[190]:FCPVD1*/ + [179] = {0xFEBD243CU, 0x0000004EU}, /* RGIDW_MODID[191]:VSPD0*/ + [180] = {0xFEBD2440U, 0x0000004EU}, /* RGIDW_MODID[192]:VSPD1*/ + [181] = {0xE6582400U, 0x0000000AU}, /* RGIDW_MODID[193]:CKMHSC*/ + [182] = {0xE6582404U, 0x0000000CU}, /* RGIDW_MODID[194]:AXIPCI001*/ + [183] = {0xE6582408U, 0x0000000CU}, /* RGIDW_MODID[195]:AXIPCI002*/ + [184] = {0xE658240CU, 0x0000000CU}, /* RGIDW_MODID[196]:AXIPCI003*/ + [185] = {0xE6582414U, 0x0000000CU}, /* RGIDW_MODID[197]:AXIPCI005*/ + [186] = {0xE6582418U, 0x0000000CU}, /* RGIDW_MODID[198]:AXIPCI006*/ + [187] = {0xE658241CU, 0x0000000CU}, /* RGIDW_MODID[199]:AXIPCI007*/ + [188] = {0xE6582420U, 0x0000000CU}, /* RGIDW_MODID[200]:AXIPCI008*/ + [189] = {0xE6582424U, 0x0000000CU}, /* RGIDW_MODID[201]:AXIPCI009*/ + [190] = {0xE6582428U, 0x0000000CU}, /* RGIDW_MODID[202]:AXIPCI010*/ + [191] = {0xE658242CU, 0x0000000CU}, /* RGIDW_MODID[203]:AXIPCI011*/ + [192] = {0xE6582430U, 0x0000000CU}, /* RGIDW_MODID[204]:AXIPCI012*/ + [193] = {0xE6582434U, 0x0000000CU}, /* RGIDW_MODID[205]:AXIPCI013*/ + [194] = {0xE6582438U, 0x0000000CU}, /* RGIDW_MODID[206]:AXIPCI014*/ + [195] = {0xE658243CU, 0x0000000CU}, /* RGIDW_MODID[207]:AXIPCI015*/ + [196] = {0xE6582440U, 0x0000000CU}, /* RGIDW_MODID[208]:AXIPCI100*/ + [197] = {0xE6582444U, 0x0000000CU}, /* RGIDW_MODID[209]:AXIPCI101*/ + [198] = {0xE6582448U, 0x0000000CU}, /* RGIDW_MODID[210]:AXIPCI102*/ + [199] = {0xE658244CU, 0x0000000CU}, /* RGIDW_MODID[211]:AXIPCI103*/ + [200] = {0xE6582450U, 0x0000000CU}, /* RGIDW_MODID[212]:AXIPCI104*/ + [201] = {0xE6582454U, 0x0000000CU}, /* RGIDW_MODID[213]:AXIPCI105*/ + [202] = {0xE6582458U, 0x0000000CU}, /* RGIDW_MODID[214]:AXIPCI106*/ + [203] = {0xE658245CU, 0x0000000CU}, /* RGIDW_MODID[215]:AXIPCI107*/ + [204] = {0xE6582460U, 0x0000000CU}, /* RGIDW_MODID[216]:AXIPCI108*/ + [205] = {0xE6582464U, 0x0000000CU}, /* RGIDW_MODID[217]:AXIPCI109*/ + [206] = {0xE6582468U, 0x0000000CU}, /* RGIDW_MODID[218]:AXIPCI110*/ + [207] = {0xE658246CU, 0x0000000CU}, /* RGIDW_MODID[219]:AXIPCI111*/ + [208] = {0xE6582470U, 0x0000000CU}, /* RGIDW_MODID[220]:AXIPCI112*/ + [209] = {0xE6582474U, 0x0000000CU}, /* RGIDW_MODID[221]:AXIPCI113*/ + [210] = {0xE6582478U, 0x0000000CU}, /* RGIDW_MODID[222]:AXIPCI114*/ + [211] = {0xE658247CU, 0x0000000CU}, /* RGIDW_MODID[223]:AXIPCI115*/ + [212] = {0xE6582484U, 0x0000000EU}, /* RGIDW_MODID[224]:GPTP*/ + [213] = {0xE6582488U, 0x0000004EU}, /* RGIDW_MODID[225]:IPMMUHC00*/ + [214] = {0xE65824F0U, 0x0000000EU}, /* RGIDW_MODID[226]:TSN0*/ + [215] = {0xE65824F4U, 0x0000000CU}, /* RGIDW_MODID[227]:AXIPCI000*/ + [216] = {0xE65824F8U, 0x0000000CU}, /* RGIDW_MODID[228]:AXIPCI004*/ + [217] = {0xE65824FCU, 0x0000004EU}, /* RGIDW_MODID[229]:IPMMUHC01*/ + [218] = {0xE6582500U, 0x0000004EU}, /* RGIDW_MODID[230]:AVB0*/ + [219] = {0xE6582504U, 0x0000004EU}, /* RGIDW_MODID[231]:AVB1*/ + [220] = {0xE6582508U, 0x0000004EU}, /* RGIDW_MODID[232]:AVB2*/ + [221] = {0xE658250CU, 0x0000004EU}, /* RGIDW_MODID[233]:IPMMUHC10*/ + [222] = {0xE6582510U, 0x0000004EU}, /* RGIDW_MODID[234]:IPMMUHC11*/ + [223] = {0xE6582514U, 0x0000004EU}, /* RGIDW_MODID[235]:IPMMUHC12*/ + [224] = {0xE6582518U, 0x0000004EU}, /* RGIDW_MODID[236]:IPMMUHC13*/ + [225] = {0xE658251CU, 0x0000000CU}, /* RGIDW_MODID[237]:PPHY0*/ + [226] = {0xE6582520U, 0x0000000CU}, /* RGIDW_MODID[238]:PPHY1*/ + [227] = {0xE6582524U, 0x0000004EU}, /* RGIDW_MODID[239]:IPMMUHC14*/ + [228] = {0xE6582528U, 0x0000004EU}, /* RGIDW_MODID[240]:IPMMUHC15*/ + [229] = {0xE658252CU, 0x0000000EU}, /* RGIDW_MODID[241]:FBAHSC*/ + [230] = {0xE6582530U, 0x0000004EU}, /* RGIDW_MODID[242]:IPMMUHC02*/ + [231] = {0xE6582538U, 0x0000000AU}, /* RGIDW_MODID[243]:ECMHSC*/ + [232] = {0xE658253CU, 0x00000002U}, /* RGIDW_MODID[244]:ARHC0*/ + /* After setting */ /* RGIDW_MODID[245]:ARHC1*/ + /* After setting */ /* RGIDW_MODID[246]:ARHC2*/ + [233] = {0xE6582548U, 0x00000001U}, /* RGIDW_MODID[247]:ARHC3*/ + [234] = {0xE658254CU, 0x00000002U}, /* RGIDW_MODID[248]:ARHC4*/ + [235] = {0xE6582550U, 0x00000001U}, /* RGIDW_MODID[249]:ARHC5*/ + [236] = {0xE6582554U, 0x00000002U}, /* RGIDW_MODID[250]:ARHC6*/ + [237] = {0xE6582558U, 0x00000002U}, /* RGIDW_MODID[251]:ARHC7*/ + [238] = {0xE658255CU, 0x00000000U}, /* RGIDW_MODID[252]:ARHC8*/ + [239] = {0xE6582560U, 0x0000004EU}, /* RGIDW_MODID[253]:IPMMUHC03*/ + [240] = {0xE6582564U, 0x0000004EU}, /* RGIDW_MODID[254]:IPMMUHC04*/ + [241] = {0xE6582568U, 0x0000004EU}, /* RGIDW_MODID[255]:IPMMUHC05*/ + [242] = {0xE658256CU, 0x0000004EU}, /* RGIDW_MODID[256]:IPMMUHC06*/ + [243] = {0xE6582570U, 0x0000004EU}, /* RGIDW_MODID[257]:IPMMUHC07*/ + [244] = {0xE6582574U, 0x0000004EU}, /* RGIDW_MODID[258]:IPMMUHC08*/ + [245] = {0xE6582578U, 0x0000004EU}, /* RGIDW_MODID[259]:IPMMUHC09*/ + [246] = {0xFF882400U, 0x00000002U}, /* RGIDW_MODID[260]:ARIMP00*/ + /* After setting */ /* RGIDW_MODID[261]:ARIMP01*/ + /* After setting */ /* RGIDW_MODID[262]:ARIMP02*/ + [247] = {0xFF88240CU, 0x00000001U}, /* RGIDW_MODID[263]:ARIMP03*/ + [248] = {0xFF882410U, 0x00000002U}, /* RGIDW_MODID[264]:ARIMP04*/ + [249] = {0xFF882414U, 0x0000004EU}, /* RGIDW_MODID[265]:AXIFBABUSIR0*/ + [250] = {0xFF882418U, 0x0000004EU}, /* RGIDW_MODID[266]:AXIFBABUSIR1*/ + [251] = {0xFF88241CU, 0x0000004EU}, /* RGIDW_MODID[267]:AXIFBABUSIR2*/ + [252] = {0xFF882420U, 0x0000004EU}, /* RGIDW_MODID[268]:AXIFBABUSIR3*/ + [253] = {0xFF882424U, 0x0000004EU}, /* RGIDW_MODID[269]:AXIFBABUSIR4*/ + [254] = {0xFF882428U, 0x0000004EU}, /* RGIDW_MODID[270]:AXIIMP0*/ + [255] = {0xFF88242CU, 0x0000004EU}, /* RGIDW_MODID[271]:CKMCNR*/ + [256] = {0xFF882430U, 0x0000004EU}, /* RGIDW_MODID[272]:CKMDSP*/ + [257] = {0xFF882434U, 0x00000001U}, /* RGIDW_MODID[273]:ARIMP05*/ + [258] = {0xFF882438U, 0x00000002U}, /* RGIDW_MODID[274]:ARIMP06*/ + [259] = {0xFF88243CU, 0x00000002U}, /* RGIDW_MODID[275]:ARIMP07*/ + [260] = {0xFF882440U, 0x00000000U}, /* RGIDW_MODID[276]:ARIMP08*/ + [261] = {0xFF882444U, 0x0000004EU}, /* RGIDW_MODID[277]:CKMIR*/ + [262] = {0xFF882448U, 0x0000000AU}, /* RGIDW_MODID[278]:ECMIR*/ + [263] = {0xFF88244CU, 0x0000000FU}, /* RGIDW_MODID[279]:DSPPS*/ + [264] = {0xFF882450U, 0x0000004EU}, /* RGIDW_MODID[280]:IPMMUIR1*/ + [265] = {0xFF882454U, 0x0000004EU}, /* RGIDW_MODID[281]:IPMMUIR0*/ + [266] = {0xFF882458U, 0x0000004EU}, /* RGIDW_MODID[282]:IPMMUIR10*/ + [267] = {0xFF88245CU, 0x0000004EU}, /* RGIDW_MODID[283]:IPMMUIR11*/ + [268] = {0xFF882460U, 0x0000004EU}, /* RGIDW_MODID[284]:IPMMUIR12*/ + [269] = {0xFF882464U, 0x0000004EU}, /* RGIDW_MODID[285]:IPMMUIR13*/ + [270] = {0xFF882468U, 0x0000004EU}, /* RGIDW_MODID[286]:IPMMUIR14*/ + [271] = {0xFF88246CU, 0x0000004EU}, /* RGIDW_MODID[287]:IPMMUIR15*/ + [272] = {0xFF882470U, 0x0000004EU}, /* RGIDW_MODID[288]:IPMMUIR2*/ + [273] = {0xFF882474U, 0x0000004EU}, /* RGIDW_MODID[289]:IPMMUIR3*/ + [274] = {0xFF882478U, 0x0000004EU}, /* RGIDW_MODID[290]:IPMMUIR4*/ + [275] = {0xFF88247CU, 0x0000004EU}, /* RGIDW_MODID[291]:IPMMUIR5*/ + [276] = {0xFF882480U, 0x0000004EU}, /* RGIDW_MODID[292]:IPMMUIR6*/ + [277] = {0xFF882484U, 0x0000004EU}, /* RGIDW_MODID[293]:IPMMUIR7*/ + [278] = {0xFF882488U, 0x0000004EU}, /* RGIDW_MODID[294]:IPMMUIR8*/ + [279] = {0xFF88248CU, 0x0000004EU}, /* RGIDW_MODID[295]:IPMMUIR9*/ + [280] = {0xFD812400U, 0x00000002U}, /* RGIDW_MODID[296]:ARPV0*/ + /* After setting */ /* RGIDW_MODID[297]:ARPV1*/ + [281] = {0xFD812408U, 0x0000002CU}, /* RGIDW_MODID[298]:AXIRGXS*/ + /* After setting */ /* RGIDW_MODID[299]:ARPV2*/ + [282] = {0xFD812410U, 0x00000001U}, /* RGIDW_MODID[300]:ARPV3*/ + [283] = {0xFD812414U, 0x00000002U}, /* RGIDW_MODID[301]:ARPV4*/ + [284] = {0xFD812418U, 0x00000001U}, /* RGIDW_MODID[302]:ARPV5*/ + [285] = {0xFD81241CU, 0x00000002U}, /* RGIDW_MODID[303]:ARPV6*/ + [286] = {0xFD812420U, 0x00000002U}, /* RGIDW_MODID[304]:ARPV7*/ + [287] = {0xFD812424U, 0x00000000U}, /* RGIDW_MODID[305]:ARPV8*/ + [288] = {0xFD812428U, 0x0000000AU}, /* RGIDW_MODID[306]:CKM3DG*/ + [289] = {0xFD81242CU, 0x0000000AU}, /* RGIDW_MODID[307]:ECM3DG*/ + [290] = {0xFD812430U, 0x0000000EU}, /* RGIDW_MODID[308]:FBAPVC*/ + [291] = {0xFD812434U, 0x0000000EU}, /* RGIDW_MODID[309]:FBAPVD0*/ + [292] = {0xFD812438U, 0x0000000EU}, /* RGIDW_MODID[310]:FBAPVD1*/ + [293] = {0xFD81243CU, 0x0000000EU}, /* RGIDW_MODID[311]:FBAPVD2*/ + [294] = {0xFD812440U, 0x0000000EU}, /* RGIDW_MODID[312]:FBAPVE*/ + [295] = {0xFD812444U, 0x0000004EU}, /* RGIDW_MODID[313]:IPMMUPV000*/ + [296] = {0xFD812448U, 0x0000004EU}, /* RGIDW_MODID[314]:IPMMUPV001*/ + [297] = {0xFD81244CU, 0x0000004EU}, /* RGIDW_MODID[315]:IPMMUPV010*/ + [298] = {0xFD812450U, 0x0000004EU}, /* RGIDW_MODID[316]:IPMMUPV011*/ + [299] = {0xFD812454U, 0x0000004EU}, /* RGIDW_MODID[317]:IPMMUPV012*/ + [300] = {0xFD812458U, 0x0000004EU}, /* RGIDW_MODID[318]:IPMMUPV013*/ + [301] = {0xFD81245CU, 0x0000004EU}, /* RGIDW_MODID[319]:IPMMUPV014*/ + [302] = {0xFD812460U, 0x0000004EU}, /* RGIDW_MODID[320]:IPMMUPV015*/ + [303] = {0xFD812464U, 0x0000004EU}, /* RGIDW_MODID[321]:IPMMUPV002*/ + [304] = {0xFD812468U, 0x0000004EU}, /* RGIDW_MODID[322]:IPMMUPV003*/ + [305] = {0xFD81246CU, 0x0000004EU}, /* RGIDW_MODID[323]:IPMMUPV004*/ + [306] = {0xFD812470U, 0x0000004EU}, /* RGIDW_MODID[324]:IPMMUPV005*/ + [307] = {0xFD812474U, 0x0000004EU}, /* RGIDW_MODID[325]:IPMMUPV006*/ + [308] = {0xFD812478U, 0x0000004EU}, /* RGIDW_MODID[326]:IPMMUPV007*/ + [309] = {0xFD81247CU, 0x0000004EU}, /* RGIDW_MODID[327]:IPMMUPV008*/ + [310] = {0xFD812480U, 0x0000004EU}, /* RGIDW_MODID[328]:IPMMUPV009*/ + [311] = {0xE6622400U, 0x00000002U}, /* RGIDW_MODID[329]:ARRC0*/ + /* After setting */ /* RGIDW_MODID[330]:ARRC1*/ + /* After setting */ /* RGIDW_MODID[331]:ARRC2*/ + [312] = {0xE662240CU, 0x00000001U}, /* RGIDW_MODID[332]:ARRC3*/ + [313] = {0xE6622410U, 0x00000002U}, /* RGIDW_MODID[333]:ARRC4*/ + [314] = {0xE6622414U, 0x00000001U}, /* RGIDW_MODID[334]:ARRC5*/ + [315] = {0xE6622418U, 0x00000002U}, /* RGIDW_MODID[335]:ARRC6*/ + [316] = {0xE662241CU, 0x00000002U}, /* RGIDW_MODID[336]:ARRC7*/ + [317] = {0xE6622420U, 0x00000000U}, /* RGIDW_MODID[337]:ARRC8*/ + [318] = {0xE6622424U, 0x00000009U}, /* RGIDW_MODID[338]:CR0*/ + [319] = {0xE6622428U, 0x0000004FU}, /* RGIDW_MODID[339]:ICUMX*/ + [320] = {0xE662242CU, 0x0000000AU}, /* RGIDW_MODID[340]:ECMRC*/ + [321] = {0xFFC32400U, 0x0000004EU}, /* RGIDW_MODID[341]:DMAWCRC0*/ + [322] = {0xFFC32404U, 0x0000004EU}, /* RGIDW_MODID[342]:DMAWCRC1*/ + [323] = {0xFFC32408U, 0x0000004EU}, /* RGIDW_MODID[343]:DMAWCRC2*/ + [324] = {0xFFC3240CU, 0x0000004EU}, /* RGIDW_MODID[344]:DMAWCRC3*/ + [325] = {0xFFC42400U, 0x0000000FU}, /* RGIDW_MODID[345]:ARMREG00*/ + [326] = {0xFFC42404U, 0x0000000CU}, /* RGIDW_MODID[346]:ARMREG01*/ + [327] = {0xFFC42408U, 0x00000000U}, /* RGIDW_MODID[347]:ARMREG10*/ + [328] = {0xFFC4240CU, 0x00000000U}, /* RGIDW_MODID[348]:ARMREG11*/ + [329] = {0xFFC42410U, 0x0000000AU}, /* RGIDW_MODID[349]:ARMREG12*/ + [330] = {0xFFC42414U, 0x0000000FU}, /* RGIDW_MODID[350]:ARMREG13*/ + [331] = {0xFFC42418U, 0x0000000AU}, /* RGIDW_MODID[351]:ARMREG14*/ + [332] = {0xFFC4241CU, 0x00000003U}, /* RGIDW_MODID[352]:AXICR52SS0*/ + [333] = {0xFFC42420U, 0x0000000EU}, /* RGIDW_MODID[353]:AXICSD0*/ + [334] = {0xFFC42424U, 0x0000000EU}, /* RGIDW_MODID[354]:AXIINTAP0*/ + [335] = {0xFFC42428U, 0x00000000U}, /* RGIDW_MODID[355]:AXIINTAP1*/ + [336] = {0xFFC42430U, 0x0000000FU}, /* RGIDW_MODID[356]:AXISYSRAM0*/ + [337] = {0xFFC42434U, 0x0000004FU}, /* RGIDW_MODID[357]:AXISYSRAM1*/ + [338] = {0xFFC42438U, 0x00000000U}, /* RGIDW_MODID[358]:ARGREG15*/ + [339] = {0xFFC4243CU, 0x00000000U}, /* RGIDW_MODID[359]:ARMREG2*/ + [340] = {0xFFC42440U, 0x00000000U}, /* RGIDW_MODID[360]:ARMREG3*/ + [341] = {0xFFC42444U, 0x00000000U}, /* RGIDW_MODID[361]:ARMREG4*/ + [342] = {0xFFC42448U, 0x0000000FU}, /* RGIDW_MODID[362]:ARMREG5*/ + [343] = {0xFFC4244CU, 0x0000000AU}, /* RGIDW_MODID[363]:ARMREG6*/ + [344] = {0xFFC42450U, 0x00000000U}, /* RGIDW_MODID[364]:ARMREG7*/ + [345] = {0xFFC42454U, 0x0000000CU}, /* RGIDW_MODID[365]:ARMREG8*/ + [346] = {0xFFC42458U, 0x0000000CU}, /* RGIDW_MODID[366]:ARMREG9*/ + [347] = {0xFFC4245CU, 0x00000002U}, /* RGIDW_MODID[367]:ARRD0*/ + /* After setting */ /* RGIDW_MODID[368]:ARRD1*/ + /* After setting */ /* RGIDW_MODID[369]:ARRD2*/ + [348] = {0xFFC42468U, 0x00000001U}, /* RGIDW_MODID[370]:ARRD3*/ + [349] = {0xFFC4246CU, 0x00000002U}, /* RGIDW_MODID[371]:ARRD4*/ + [350] = {0xFFC42470U, 0x00000001U}, /* RGIDW_MODID[372]:ARRD5*/ + [351] = {0xFFC42474U, 0x00000002U}, /* RGIDW_MODID[373]:ARRD6*/ + [352] = {0xFFC42478U, 0x00000002U}, /* RGIDW_MODID[374]:ARRD7*/ + [353] = {0xFFC4247CU, 0x00000000U}, /* RGIDW_MODID[375]:ARRD8*/ + [354] = {0xFFC42480U, 0x00000002U}, /* RGIDW_MODID[376]:ARRT0*/ + /* After setting */ /* RGIDW_MODID[377]:ARRT1*/ + /* After setting */ /* RGIDW_MODID[378]:ARRT2*/ + [355] = {0xFFC4248CU, 0x00000001U}, /* RGIDW_MODID[379]:ARRT3*/ + [356] = {0xFFC42490U, 0x00000002U}, /* RGIDW_MODID[380]:ARRT4*/ + [357] = {0xFFC42494U, 0x00000001U}, /* RGIDW_MODID[381]:ARRT5*/ + [358] = {0xFFC42498U, 0x00000002U}, /* RGIDW_MODID[382]:ARRT6*/ + [359] = {0xFFC4249CU, 0x00000002U}, /* RGIDW_MODID[383]:ARRT7*/ + [360] = {0xFFC424A0U, 0x00000000U}, /* RGIDW_MODID[384]:ARRT8*/ + [361] = {0xFFC424A4U, 0x0000000AU}, /* RGIDW_MODID[385]:CKMRT*/ + [362] = {0xFFC424A8U, 0x0000004EU}, /* RGIDW_MODID[386]:CRC0*/ + [363] = {0xFFC424ACU, 0x0000004EU}, /* RGIDW_MODID[387]:CRC1*/ + [364] = {0xFFC424B0U, 0x0000004EU}, /* RGIDW_MODID[388]:CRC2*/ + [365] = {0xFFC424B4U, 0x0000004EU}, /* RGIDW_MODID[389]:CRC3*/ + [366] = {0xFFC424B8U, 0x0000000EU}, /* RGIDW_MODID[390]:CSD*/ + [367] = {0xFFC424BCU, 0x0000000EU}, /* RGIDW_MODID[391]:ECM*/ + [368] = {0xFFC424C0U, 0x0000000AU}, /* RGIDW_MODID[392]:ECMRT*/ + [369] = {0xFFC424C4U, 0x0000000EU}, /* RGIDW_MODID[393]:FBACR52*/ + [370] = {0xFFC424C8U, 0x0000000EU}, /* RGIDW_MODID[394]:FBART*/ + [371] = {0xFFC424CCU, 0x0000000EU}, /* RGIDW_MODID[395]:INTTP*/ + [372] = {0xFFC424D0U, 0x0000004EU}, /* RGIDW_MODID[396]:IPMMURT000*/ + [373] = {0xFFC424D4U, 0x0000004EU}, /* RGIDW_MODID[397]:IPMMURT100*/ + [374] = {0xFFC424D8U, 0x0000004EU}, /* RGIDW_MODID[398]:KCRC4*/ + [375] = {0xFFC424DCU, 0x0000004EU}, /* RGIDW_MODID[399]:KCRC5*/ + [376] = {0xFFC424E0U, 0x0000004EU}, /* RGIDW_MODID[400]:KCRC6*/ + [377] = {0xFFC424E4U, 0x0000004EU}, /* RGIDW_MODID[401]:KCRC7*/ + [378] = {0xFFC424E8U, 0x0000004FU}, /* RGIDW_MODID[402]:MFI00*/ + [379] = {0xFFC424ECU, 0x0000004EU}, /* RGIDW_MODID[403]:MFI01*/ + [380] = {0xFFC424F0U, 0x0000004EU}, /* RGIDW_MODID[404]:MFI10*/ + [381] = {0xFFC424F4U, 0x0000004EU}, /* RGIDW_MODID[405]:MFI02*/ + [382] = {0xFFC424F8U, 0x0000004EU}, /* RGIDW_MODID[406]:MFI03*/ + [383] = {0xFFC424FCU, 0x0000004EU}, /* RGIDW_MODID[407]:MFI04*/ + [384] = {0xFFC42500U, 0x00000000U}, /* RGIDW_MODID[408]:MFI05*/ + [385] = {0xFFC42504U, 0x00000000U}, /* RGIDW_MODID[409]:MFI06*/ + [386] = {0xFFC42508U, 0x00000000U}, /* RGIDW_MODID[410]:MFI07*/ + [387] = {0xFFC4250CU, 0x00000000U}, /* RGIDW_MODID[411]:MFI08*/ + [388] = {0xFFC42510U, 0x0000004EU}, /* RGIDW_MODID[412]:MFI09*/ + [389] = {0xFFC42514U, 0x0000004FU}, /* RGIDW_MODID[413]:MFI15*/ + [390] = {0xFFC42518U, 0x0000000AU}, /* RGIDW_MODID[414]:CKMCR52*/ + [391] = {0xFFC4251CU, 0x0000004BU}, /* RGIDW_MODID[415]:RTDM0P*/ + [392] = {0xFFC42520U, 0x0000000AU}, /* RGIDW_MODID[416]:ECMRD*/ + [393] = {0xFFC42524U, 0x0000004BU}, /* RGIDW_MODID[417]:RTDM1P*/ + [394] = {0xFFC4252CU, 0x0000004BU}, /* RGIDW_MODID[418]:RTDM2P*/ + [395] = {0xFFC42530U, 0x0000000BU}, /* RGIDW_MODID[419]:SYSRAM10*/ + [396] = {0xFFC42534U, 0x0000004BU}, /* RGIDW_MODID[420]:RTDM3P*/ + [397] = {0xFFC42538U, 0x00000001U}, /* RGIDW_MODID[421]:SYSRAM00*/ + [398] = {0xFFC4253CU, 0x0000004EU}, /* RGIDW_MODID[422]:TSIPL0*/ + [399] = {0xFFC42540U, 0x0000004EU}, /* RGIDW_MODID[423]:TSIPL1*/ + [400] = {0xFFC42544U, 0x0000004EU}, /* RGIDW_MODID[424]:TSIPL2*/ + [401] = {0xFFC42548U, 0x0000004EU}, /* RGIDW_MODID[425]:TSIPL3*/ + [402] = {0xFFC4254CU, 0x0000004EU}, /* RGIDW_MODID[426]:TSIPL4*/ + [403] = {0xFFC42550U, 0x0000004EU}, /* RGIDW_MODID[427]:TSIPL5*/ + [404] = {0xFFC42554U, 0x0000004EU}, /* RGIDW_MODID[428]:TSIPL6*/ + [405] = {0xFFC42558U, 0x0000004EU}, /* RGIDW_MODID[429]:TSIPL7*/ + [406] = {0xFFC4255CU, 0x0000004EU}, /* RGIDW_MODID[430]:WCRC0*/ + [407] = {0xFFC42560U, 0x0000004EU}, /* RGIDW_MODID[431]:WCRC1*/ + [408] = {0xFFC42564U, 0x0000004EU}, /* RGIDW_MODID[432]:WCRC2*/ + [409] = {0xFFC42568U, 0x0000004EU}, /* RGIDW_MODID[433]:WCRC3*/ + [410] = {0xFFC42580U, 0x0000004EU}, /* RGIDW_MODID[434]:MFI11*/ + [411] = {0xFFC42584U, 0x00000000U}, /* RGIDW_MODID[435]:MFI12*/ + [412] = {0xFFC42588U, 0x00000000U}, /* RGIDW_MODID[436]:MFI13*/ + [413] = {0xFFC4258CU, 0x00000000U}, /* RGIDW_MODID[437]:MFI14*/ + [414] = {0xFFC42590U, 0x0000004EU}, /* RGIDW_MODID[438]:IPMMURT001*/ + [415] = {0xFFC42594U, 0x0000004EU}, /* RGIDW_MODID[439]:IPMMURT010*/ + [416] = {0xFFC42598U, 0x0000004EU}, /* RGIDW_MODID[440]:IPMMURT011*/ + [417] = {0xFFC4259CU, 0x0000004EU}, /* RGIDW_MODID[441]:IPMMURT012*/ + [418] = {0xFFC425A0U, 0x0000004EU}, /* RGIDW_MODID[442]:IPMMURT013*/ + [419] = {0xFFC425A4U, 0x0000004EU}, /* RGIDW_MODID[443]:IPMMURT014*/ + [420] = {0xFFC425A8U, 0x0000004EU}, /* RGIDW_MODID[444]:IPMMURT015*/ + [421] = {0xFFC425ACU, 0x0000004EU}, /* RGIDW_MODID[445]:IPMMURT002*/ + [422] = {0xFFC425B0U, 0x0000004EU}, /* RGIDW_MODID[446]:IPMMURT003*/ + [423] = {0xFFC425B4U, 0x0000004EU}, /* RGIDW_MODID[447]:IPMMURT004*/ + [424] = {0xFFC425B8U, 0x0000004EU}, /* RGIDW_MODID[448]:IPMMURT005*/ + [425] = {0xFFC425BCU, 0x0000004EU}, /* RGIDW_MODID[449]:IPMMURT006*/ + [426] = {0xFFC425C0U, 0x0000004EU}, /* RGIDW_MODID[450]:IPMMURT007*/ + [427] = {0xFFC425C4U, 0x0000004EU}, /* RGIDW_MODID[451]:IPMMURT008*/ + [428] = {0xFFC425C8U, 0x0000004EU}, /* RGIDW_MODID[452]:IPMMURT009*/ + [429] = {0xFFC425CCU, 0x0000004EU}, /* RGIDW_MODID[453]:IPKMURT101*/ + [430] = {0xFFC425D0U, 0x0000004EU}, /* RGIDW_MODID[454]:IPMMURT110*/ + [431] = {0xFFC425D4U, 0x0000004EU}, /* RGIDW_MODID[455]:IPMMURT111*/ + [432] = {0xFFC425D8U, 0x0000004EU}, /* RGIDW_MODID[456]:IPMMURT112*/ + [433] = {0xFFC425DCU, 0x0000004EU}, /* RGIDW_MODID[457]:IPMMURT113*/ + [434] = {0xFFC425E0U, 0x0000004EU}, /* RGIDW_MODID[458]:IPMMURT114*/ + [435] = {0xFFC425E4U, 0x0000004EU}, /* RGIDW_MODID[459]:IPMMURT115*/ + [436] = {0xFFC425E8U, 0x0000004EU}, /* RGIDW_MODID[460]:IPMMURT102*/ + [437] = {0xFFC425ECU, 0x0000004EU}, /* RGIDW_MODID[461]:IPMMURT103*/ + [438] = {0xFFC425F0U, 0x0000004EU}, /* RGIDW_MODID[462]:IPMMURT104*/ + [439] = {0xFFC425F4U, 0x0000004EU}, /* RGIDW_MODID[463]:IPMMURT105*/ + [440] = {0xFFC425F8U, 0x0000004EU}, /* RGIDW_MODID[464]:IPMMURT106*/ + [441] = {0xFFC425FCU, 0x0000004EU}, /* RGIDW_MODID[465]:IPMMURT107*/ + [442] = {0xFFC42600U, 0x0000004BU}, /* RGIDW_MODID[466]:RTDM000*/ + [443] = {0xFFC42604U, 0x0000004BU}, /* RGIDW_MODID[467]:RTDM001*/ + [444] = {0xFFC42608U, 0x0000004BU}, /* RGIDW_MODID[468]:RTDM010*/ + [445] = {0xFFC4260CU, 0x0000004BU}, /* RGIDW_MODID[469]:RTDM011*/ + [446] = {0xFFC42610U, 0x0000004BU}, /* RGIDW_MODID[470]:RTDM012*/ + [447] = {0xFFC42614U, 0x0000004BU}, /* RGIDW_MODID[471]:RTDM013*/ + [448] = {0xFFC42618U, 0x0000004BU}, /* RGIDW_MODID[472]:RTDM014*/ + [449] = {0xFFC4261CU, 0x0000004BU}, /* RGIDW_MODID[473]:RTDM015*/ + [450] = {0xFFC42620U, 0x0000004BU}, /* RGIDW_MODID[474]:RTDM002*/ + [451] = {0xFFC42624U, 0x0000004BU}, /* RGIDW_MODID[475]:RTDM003*/ + [452] = {0xFFC42628U, 0x0000004BU}, /* RGIDW_MODID[476]:RTDM004*/ + [453] = {0xFFC4262CU, 0x0000004BU}, /* RGIDW_MODID[477]:RTDM005*/ + [454] = {0xFFC42630U, 0x0000004BU}, /* RGIDW_MODID[478]:RTDM006*/ + [455] = {0xFFC42634U, 0x0000004BU}, /* RGIDW_MODID[479]:RTDM007*/ + [456] = {0xFFC42638U, 0x0000004BU}, /* RGIDW_MODID[480]:RTDM008*/ + [457] = {0xFFC4263CU, 0x0000004BU}, /* RGIDW_MODID[481]:RTDM009*/ + [458] = {0xFFC42640U, 0x0000004BU}, /* RGIDW_MODID[482]:RTDM100*/ + [459] = {0xFFC42644U, 0x0000004BU}, /* RGIDW_MODID[483]:RTDM101*/ + [460] = {0xFFC42648U, 0x0000004BU}, /* RGIDW_MODID[484]:RTDM110*/ + [461] = {0xFFC4264CU, 0x0000004BU}, /* RGIDW_MODID[485]:RTDM111*/ + [462] = {0xFFC42650U, 0x0000004BU}, /* RGIDW_MODID[486]:RTDM112*/ + [463] = {0xFFC42654U, 0x0000004BU}, /* RGIDW_MODID[487]:RTDM113*/ + [464] = {0xFFC42658U, 0x0000004BU}, /* RGIDW_MODID[488]:RTDM114*/ + [465] = {0xFFC4265CU, 0x0000004BU}, /* RGIDW_MODID[489]:RTDM115*/ + [466] = {0xFFC42660U, 0x0000004BU}, /* RGIDW_MODID[490]:RTDM102*/ + [467] = {0xFFC42664U, 0x0000004BU}, /* RGIDW_MODID[491]:RTDM103*/ + [468] = {0xFFC42668U, 0x0000004BU}, /* RGIDW_MODID[492]:RTDM104*/ + [469] = {0xFFC4266CU, 0x0000004BU}, /* RGIDW_MODID[493]:RTDM105*/ + [470] = {0xFFC42670U, 0x0000004BU}, /* RGIDW_MODID[494]:RTDM106*/ + [471] = {0xFFC42674U, 0x0000004BU}, /* RGIDW_MODID[495]:RTDM107*/ + [472] = {0xFFC42678U, 0x0000004BU}, /* RGIDW_MODID[496]:RTDM108*/ + [473] = {0xFFC4267CU, 0x0000004BU}, /* RGIDW_MODID[497]:RTDM109*/ + [474] = {0xFFC42680U, 0x0000004BU}, /* RGIDW_MODID[498]:RTDM200*/ + [475] = {0xFFC42684U, 0x0000004BU}, /* RGIDW_MODID[499]:RTDM201*/ + [476] = {0xFFC42688U, 0x0000004BU}, /* RGIDW_MODID[500]:RTDM210*/ + [477] = {0xFFC4268CU, 0x0000004BU}, /* RGIDW_MODID[501]:RTDM211*/ + [478] = {0xFFC42690U, 0x0000004BU}, /* RGIDW_MODID[502]:RTDM212*/ + [479] = {0xFFC42694U, 0x0000004BU}, /* RGIDW_MODID[503]:RTDM213*/ + [480] = {0xFFC42698U, 0x0000004BU}, /* RGIDW_MODID[504]:RTDM214*/ + [481] = {0xFFC4269CU, 0x0000004BU}, /* RGIDW_MODID[505]:RTDM215*/ + [482] = {0xFFC426A0U, 0x0000004BU}, /* RGIDW_MODID[506]:RTDM202*/ + [483] = {0xFFC426A4U, 0x0000004BU}, /* RGIDW_MODID[507]:RTDM203*/ + [484] = {0xFFC426A8U, 0x0000004BU}, /* RGIDW_MODID[508]:RTDM204*/ + [485] = {0xFFC426ACU, 0x0000004BU}, /* RGIDW_MODID[509]:RTDM205*/ + [486] = {0xFFC426B0U, 0x0000004BU}, /* RGIDW_MODID[510]:RTDM206*/ + [487] = {0xFFC426B4U, 0x0000004BU}, /* RGIDW_MODID[511]:RTDM207*/ + [488] = {0xFFC426B8U, 0x0000004BU}, /* RGIDW_MODID[512]:RTDM208*/ + [489] = {0xFFC426BCU, 0x0000004BU}, /* RGIDW_MODID[513]:RTDM209*/ + [490] = {0xFFC426C0U, 0x0000004BU}, /* RGIDW_MODID[514]:RTDM300*/ + [491] = {0xFFC426C4U, 0x0000004BU}, /* RGIDW_MODID[515]:RTDM301*/ + [492] = {0xFFC426C8U, 0x0000004BU}, /* RGIDW_MODID[516]:RTDM310*/ + [493] = {0xFFC426CCU, 0x0000004BU}, /* RGIDW_MODID[517]:RTDM311*/ + [494] = {0xFFC426D0U, 0x0000004BU}, /* RGIDW_MODID[518]:RTDM312*/ + [495] = {0xFFC426D4U, 0x0000004BU}, /* RGIDW_MODID[519]:RTDM313*/ + [496] = {0xFFC426D8U, 0x0000004BU}, /* RGIDW_MODID[520]:RTDM314*/ + [497] = {0xFFC426DCU, 0x0000004BU}, /* RGIDW_MODID[521]:RTDM315*/ + [498] = {0xFFC426E0U, 0x0000004BU}, /* RGIDW_MODID[522]:RTDM302*/ + [499] = {0xFFC426E4U, 0x0000004BU}, /* RGIDW_MODID[523]:RTDM303*/ + [500] = {0xFFC426E8U, 0x0000004BU}, /* RGIDW_MODID[524]:RTDM304*/ + [501] = {0xFFC426ECU, 0x0000004BU}, /* RGIDW_MODID[525]:RTDM305*/ + [502] = {0xFFC426F0U, 0x0000004BU}, /* RGIDW_MODID[526]:RTDM306*/ + [503] = {0xFFC426F4U, 0x0000004BU}, /* RGIDW_MODID[527]:RTDM307*/ + [504] = {0xFFC426F8U, 0x0000004BU}, /* RGIDW_MODID[528]:RTDM308*/ + [505] = {0xFFC426FCU, 0x0000004BU}, /* RGIDW_MODID[529]:RTDM309*/ + [506] = {0xFFC42700U, 0x0000004EU}, /* RGIDW_MODID[530]:IPMMURT108*/ + [507] = {0xFFC42704U, 0x0000004EU}, /* RGIDW_MODID[531]:IPMMURT109*/ + [508] = {0xFFC42708U, 0x00000001U}, /* RGIDW_MODID[532]:SYSRAM01*/ + [509] = {0xFFC4270CU, 0x0000000BU}, /* RGIDW_MODID[533]:SYSRAM02*/ + [510] = {0xFFC42710U, 0x00000001U}, /* RGIDW_MODID[534]:SYSRAM03*/ + [511] = {0xFFC42714U, 0x00000001U}, /* RGIDW_MODID[535]:SYSRAM04*/ + [512] = {0xFFC42718U, 0x00000001U}, /* RGIDW_MODID[536]:SYSRAM05*/ + [513] = {0xFFC4271CU, 0x00000001U}, /* RGIDW_MODID[537]:SYSRAM06*/ + [514] = {0xFFC42720U, 0x00000000U}, /* RGIDW_MODID[538]:SYSRAM07*/ + [515] = {0xFFC42724U, 0x0000000BU}, /* RGIDW_MODID[539]:SYSRAM11*/ + [516] = {0xFFC42728U, 0x0000000AU}, /* RGIDW_MODID[540]:SYSRAM12*/ + [517] = {0xFFC4272CU, 0x0000000BU}, /* RGIDW_MODID[541]:SYSRAM13*/ + [518] = {0xFFC42730U, 0x0000000BU}, /* RGIDW_MODID[542]:SYSRAM14*/ + [519] = {0xFFC42734U, 0x0000000BU}, /* RGIDW_MODID[543]:SYSRAM15*/ + [520] = {0xFFC42738U, 0x0000000BU}, /* RGIDW_MODID[544]:SYSRAM16*/ + [521] = {0xFFC4273CU, 0x00000000U}, /* RGIDW_MODID[545]:SYSRAM17*/ + [522] = {0xFFC42760U, 0x00000002U}, /* RGIDW_MODID[546]:BKBUF*/ + [523] = {0xFFC42764U, 0x00000003U}, /* RGIDW_MODID[547]:AXICR52SS1*/ + [524] = {0xFFC42768U, 0x00000003U}, /* RGIDW_MODID[548]:AXICR52SS2*/ + [525] = {0xFF862400U, 0x00000002U}, /* RGIDW_MODID[549]:ARSC0*/ + /* After setting */ /* RGIDW_MODID[550]:ARSC1*/ + /* After setting */ /* RGIDW_MODID[551]:ARSC2*/ + [526] = {0xFF86240CU, 0x00000001U}, /* RGIDW_MODID[552]:ARSC3*/ + [527] = {0xFF862410U, 0x00000002U}, /* RGIDW_MODID[553]:ARSC4*/ + [528] = {0xFF862414U, 0x00000001U}, /* RGIDW_MODID[554]:ARSC5*/ + [529] = {0xFF862418U, 0x00000002U}, /* RGIDW_MODID[555]:ARSC6*/ + [530] = {0xFF86241CU, 0x00000002U}, /* RGIDW_MODID[556]:ARSC7*/ + [531] = {0xFF862420U, 0x00000000U}, /* RGIDW_MODID[557]:ARSC8*/ + [532] = {0xFF862424U, 0x00000002U}, /* RGIDW_MODID[558]:ARSTM0*/ + /* After setting */ /* RGIDW_MODID[559]:ARSTM1*/ + [533] = {0xFF86242CU, 0x0000000EU}, /* RGIDW_MODID[560]:CSD1S*/ + [534] = {0xFF862430U, 0x0000000EU}, /* RGIDW_MODID[561]:AXIFBABUSTOP0*/ + [535] = {0xFF862434U, 0x0000000EU}, /* RGIDW_MODID[562]:AXIFBABUSTOP1*/ + /* After setting */ /* RGIDW_MODID[563]:ARSTM2*/ + [536] = {0xFF86243CU, 0x00000001U}, /* RGIDW_MODID[564]:ARSTM3*/ + [537] = {0xFF862440U, 0x00000002U}, /* RGIDW_MODID[565]:ARSTM4*/ + [538] = {0xFF862444U, 0x00000001U}, /* RGIDW_MODID[566]:ARSTM5*/ + [539] = {0xFF862448U, 0x00000002U}, /* RGIDW_MODID[567]:ARSTM6*/ + [540] = {0xFF86244CU, 0x00000002U}, /* RGIDW_MODID[568]:ARSTM7*/ + [541] = {0xFF862450U, 0x00000000U}, /* RGIDW_MODID[569]:ARSTM8*/ + [542] = {0xFF862454U, 0x0000000AU}, /* RGIDW_MODID[570]:ECMTOP*/ + [543] = {0xFF862458U, 0x0000000EU}, /* RGIDW_MODID[571]:FBA*/ + [544] = {0xFF86245CU, 0x0000000EU}, /* RGIDW_MODID[572]:FBC*/ + [545] = {0xFF862460U, 0x0000000CU}, /* RGIDW_MODID[573]:AXICCI00*/ + [546] = {0xFF862464U, 0x0000000EU}, /* RGIDW_MODID[574]:AXICCI01*/ + [547] = {0xFF862468U, 0x0000000CU}, /* RGIDW_MODID[575]:AXICCI10*/ + [548] = {0xFF86246CU, 0x0000000CU}, /* RGIDW_MODID[576]:AXICCI11*/ + [549] = {0xFF862470U, 0x0000000CU}, /* RGIDW_MODID[577]:AXICCI12*/ + [550] = {0xFF862474U, 0x0000000CU}, /* RGIDW_MODID[578]:AXICCI13*/ + [551] = {0xFF862478U, 0x0000000CU}, /* RGIDW_MODID[579]:AXICCI14*/ + [552] = {0xFF86247CU, 0x0000000CU}, /* RGIDW_MODID[580]:AXICCI15*/ + [553] = {0xFF862480U, 0x0000000EU}, /* RGIDW_MODID[581]:AXICCI2*/ + [554] = {0xFF862484U, 0x0000000CU}, /* RGIDW_MODID[582]:AXICCI3*/ + [555] = {0xFF862488U, 0x0000000CU}, /* RGIDW_MODID[583]:AXICCI4*/ + [556] = {0xFF86248CU, 0x0000000CU}, /* RGIDW_MODID[584]:AXICCI5*/ + [557] = {0xFF862490U, 0x0000000CU}, /* RGIDW_MODID[585]:AXICCI6*/ + [558] = {0xFF862494U, 0x0000000CU}, /* RGIDW_MODID[586]:AXICCI7*/ + [559] = {0xFF862498U, 0x0000000CU}, /* RGIDW_MODID[587]:AXICCI8*/ + [560] = {0xFF86249CU, 0x00000009U}, /* RGIDW_MODID[588]:AXICCI9*/ + [561] = {0xFF8624A0U, 0x0000000AU}, /* RGIDW_MODID[589]:ECMSTM*/ + [562] = {0xE7782400U, 0x0000002CU}, /* RGIDW_MODID[590]:DMASSI00*/ + [563] = {0xE7782404U, 0x0000002CU}, /* RGIDW_MODID[591]:DMASSI01*/ + [564] = {0xE7782408U, 0x0000002CU}, /* RGIDW_MODID[592]:DMASSI02*/ + [565] = {0xE778240CU, 0x0000002CU}, /* RGIDW_MODID[593]:DMASSI03*/ + [566] = {0xE7782410U, 0x0000002CU}, /* RGIDW_MODID[594]:DMASSI04*/ + [567] = {0xE7782414U, 0x0000004EU}, /* RGIDW_MODID[595]:DMAI2C0*/ + [568] = {0xE7782418U, 0x0000004EU}, /* RGIDW_MODID[596]:DMAI2C1*/ + [569] = {0xE778241CU, 0x0000004EU}, /* RGIDW_MODID[597]:DMAI2C2*/ + [570] = {0xE7782420U, 0x0000004EU}, /* RGIDW_MODID[598]:DMAI2C3*/ + [571] = {0xE7782424U, 0x0000004EU}, /* RGIDW_MODID[599]:DMAI2C4*/ + [572] = {0xE7782428U, 0x0000004EU}, /* RGIDW_MODID[600]:DMAI2C5*/ + [573] = {0xE778242CU, 0x0000002CU}, /* RGIDW_MODID[601]:DMASSI05*/ + [574] = {0xE7782430U, 0x0000002CU}, /* RGIDW_MODID[602]:DMASSI06*/ + [575] = {0xE7782434U, 0x0000002CU}, /* RGIDW_MODID[603]:DMASSI07*/ + [576] = {0xE67C2400U, 0x00000002U}, /* RGIDW_MODID[604]:ARMM*/ + /* After setting */ /* RGIDW_MODID[605]:AXIARNMM*/ + [577] = {0xE67C2408U, 0x00000002U}, /* RGIDW_MODID[606]:ARSM0*/ + /* After setting */ /* RGIDW_MODID[607]:ARSM1*/ + /* After setting */ /* RGIDW_MODID[608]:ARSM2*/ + [578] = {0xE67C2414U, 0x0000000FU}, /* RGIDW_MODID[609]:AXIQOS0*/ + [579] = {0xE67C2418U, 0x0000000FU}, /* RGIDW_MODID[610]:AXIQOS1*/ + [580] = {0xE67C241CU, 0x0000000FU}, /* RGIDW_MODID[611]:AXIQOS2*/ + [581] = {0xE67C2420U, 0x0000000FU}, /* RGIDW_MODID[612]:AXIQOS3*/ + [582] = {0xE67C2424U, 0x0000000FU}, /* RGIDW_MODID[613]:AXIQOS4*/ + [583] = {0xE67C2428U, 0x0000000FU}, /* RGIDW_MODID[614]:AXIQOS5*/ + [584] = {0xE67C242CU, 0x0000000FU}, /* RGIDW_MODID[615]:AXIQOS6*/ + [585] = {0xE67C2430U, 0x0000000FU}, /* RGIDW_MODID[616]:AXIQOS7*/ + [586] = {0xE67C2434U, 0x00000001U}, /* RGIDW_MODID[617]:ARSM3*/ + [587] = {0xE67C2438U, 0x00000002U}, /* RGIDW_MODID[618]:ARSM4*/ + [588] = {0xE67C243CU, 0x00000001U}, /* RGIDW_MODID[619]:ARSM5*/ + [589] = {0xE67C2440U, 0x00000002U}, /* RGIDW_MODID[620]:ARSM6*/ + [590] = {0xE67C2444U, 0x00000002U}, /* RGIDW_MODID[621]:ARSM7*/ + [591] = {0xE67C2448U, 0x00000000U}, /* RGIDW_MODID[622]:ARSM8*/ + [592] = {0xE67C244CU, 0x0000000BU}, /* RGIDW_MODID[623]:AXMM0*/ + [593] = {0xE67C2450U, 0x0000000BU}, /* RGIDW_MODID[624]:AXMM1*/ + [594] = {0xE67C2454U, 0x00000000U}, /* RGIDW_MODID[625]:AXMMPMON*/ + [595] = {0xE67C2458U, 0x0000000AU}, /* RGIDW_MODID[626]:CKMMM*/ + [596] = {0xE67C245CU, 0x0000000AU}, /* RGIDW_MODID[627]:ECMMM*/ + [597] = {0xE67C2460U, 0x0000000EU}, /* RGIDW_MODID[628]:FBADBSC0*/ + [598] = {0xE67C2464U, 0x0000000EU}, /* RGIDW_MODID[629]:FBADBSC1*/ + [599] = {0xE67C2468U, 0x0000000EU}, /* RGIDW_MODID[630]:FBAMM*/ + [600] = {0xE67C246CU, 0x0000004EU}, /* RGIDW_MODID[631]:IPMMUMM00*/ + [601] = {0xE67C2470U, 0x0000000FU}, /* RGIDW_MODID[632]:DBS0A0*/ + [602] = {0xE67C2474U, 0x0000000AU}, /* RGIDW_MODID[633]:DBS0A1*/ + [603] = {0xE67C2478U, 0x0000000FU}, /* RGIDW_MODID[634]:DBS1A0*/ + [604] = {0xE67C247CU, 0x0000000AU}, /* RGIDW_MODID[635]:DBS1A1*/ + [605] = {0xE67C2480U, 0x0000000FU}, /* RGIDW_MODID[636]:AXCIDBS*/ + [606] = {0xE67C2484U, 0x00000009U}, /* RGIDW_MODID[637]:FCPRC*/ + [607] = {0xE67C2488U, 0x0000000FU}, /* RGIDW_MODID[638]:DBS0D0*/ + [608] = {0xE67C248CU, 0x0000000AU}, /* RGIDW_MODID[639]:DBS0D1*/ + [609] = {0xE67C2490U, 0x0000000FU}, /* RGIDW_MODID[640]:DBS1D0*/ + [610] = {0xE67C2494U, 0x0000000AU}, /* RGIDW_MODID[641]:DBS1D1*/ + [611] = {0xE67C2498U, 0x0000000EU}, /* RGIDW_MODID[642]:FBADDR*/ + [612] = {0xE67C249CU, 0x0000004EU}, /* RGIDW_MODID[643]:IPMMUMM01*/ + [613] = {0xE67C24A0U, 0x0000004EU}, /* RGIDW_MODID[644]:IPMMUMM10*/ + [614] = {0xE67C24A4U, 0x0000004EU}, /* RGIDW_MODID[645]:IPMMUMM11*/ + [615] = {0xE67C24A8U, 0x0000004EU}, /* RGIDW_MODID[646]:IPMMUMM12*/ + [616] = {0xE67C24ACU, 0x0000004EU}, /* RGIDW_MODID[647]:IPMMUMM13*/ + [617] = {0xE67C24B0U, 0x0000004EU}, /* RGIDW_MODID[648]:IPMMUMM14*/ + [618] = {0xE67C24B4U, 0x0000004EU}, /* RGIDW_MODID[649]:IPMMUMM15*/ + [619] = {0xE67C24B8U, 0x0000004EU}, /* RGIDW_MODID[650]:IPMMUMM02*/ + [620] = {0xE67C24BCU, 0x0000004EU}, /* RGIDW_MODID[651]:IPMMUMM03*/ + [621] = {0xE67C24C0U, 0x0000004EU}, /* RGIDW_MODID[652]:IPMMUMM04*/ + [622] = {0xE67C24C4U, 0x0000004EU}, /* RGIDW_MODID[653]:IPMMUMM05*/ + [623] = {0xE67C24C8U, 0x0000004EU}, /* RGIDW_MODID[654]:IPMMUMM06*/ + [624] = {0xE67C24CCU, 0x0000004EU}, /* RGIDW_MODID[655]:IPMMUMM07*/ + [625] = {0xE67C24D0U, 0x0000004EU}, /* RGIDW_MODID[656]:IPMMUMM08*/ + [626] = {0xE67C24D4U, 0x0000004EU}, /* RGIDW_MODID[657]:IPMMUMM09*/ + [627] = {0xFF802400U, 0x00000002U}, /* RGIDW_MODID[658]:ARSN0*/ + /* After setting */ /* RGIDW_MODID[659]:ARSN1*/ + /* After setting */ /* RGIDW_MODID[660]:ARSN2*/ + [628] = {0xFF80240CU, 0x00000001U}, /* RGIDW_MODID[661]:ARSN3*/ + [629] = {0xFF802410U, 0x00000002U}, /* RGIDW_MODID[662]:ARSN4*/ + [630] = {0xFF802414U, 0x00000001U}, /* RGIDW_MODID[663]:ARSN5*/ + [631] = {0xFF802418U, 0x00000002U}, /* RGIDW_MODID[664]:ARSN6*/ + [632] = {0xFF80241CU, 0x00000002U}, /* RGIDW_MODID[665]:ARSN7*/ + [633] = {0xFF802420U, 0x00000000U}, /* RGIDW_MODID[666]:ARSN8*/ + [634] = {0xFF802424U, 0x0000000AU}, /* RGIDW_MODID[667]:ECMTOP3*/ + [635] = {0xE7752400U, 0x00000002U}, /* RGIDW_MODID[668]:ARSD00*/ + /* After setting */ /* RGIDW_MODID[669]:ARSD01*/ + /* After setting */ /* RGIDW_MODID[670]:ARSD02*/ + [636] = {0xE775240CU, 0x00000001U}, /* RGIDW_MODID[671]:ARSD03*/ + [637] = {0xE7752410U, 0x00000002U}, /* RGIDW_MODID[672]:ARSD04*/ + [638] = {0xE7752414U, 0x00000001U}, /* RGIDW_MODID[673]:ARSD05*/ + [639] = {0xE7752418U, 0x00000002U}, /* RGIDW_MODID[674]:ARSD06*/ + [640] = {0xE775241CU, 0x0000004AU}, /* RGIDW_MODID[675]:AXIFRAY*/ + [641] = {0xE7752420U, 0x0000000FU}, /* RGIDW_MODID[676]:AXIIPC*/ + [642] = {0xE7752428U, 0x0000004FU}, /* RGIDW_MODID[677]:AXIRPC*/ + [643] = {0xE775242CU, 0x0000000FU}, /* RGIDW_MODID[678]:AXISDHI0*/ + [644] = {0xE7752430U, 0x00000002U}, /* RGIDW_MODID[679]:ARSD07*/ + [645] = {0xE7752434U, 0x00000000U}, /* RGIDW_MODID[680]:ARSD08*/ + [646] = {0xE7752438U, 0x00000002U}, /* RGIDW_MODID[681]:ARSP00*/ + /* After setting */ /* RGIDW_MODID[682]:ARSP01*/ + /* After setting */ /* RGIDW_MODID[683]:ARSP02*/ + [647] = {0xE7752444U, 0x00000001U}, /* RGIDW_MODID[684]:ARSP03*/ + [648] = {0xE7752448U, 0x00000002U}, /* RGIDW_MODID[685]:ARSP04*/ + [649] = {0xE775244CU, 0x00000001U}, /* RGIDW_MODID[686]:ARSP05*/ + [650] = {0xE7752450U, 0x00000002U}, /* RGIDW_MODID[687]:ARSP06*/ + [651] = {0xE7752454U, 0x00000002U}, /* RGIDW_MODID[688]:ARSP07*/ + [652] = {0xE7752458U, 0x00000000U}, /* RGIDW_MODID[689]:ARSP08*/ + [653] = {0xE775245CU, 0x0000004EU}, /* RGIDW_MODID[690]:IPMMUDS001*/ + [654] = {0xE7752460U, 0x0000000AU}, /* RGIDW_MODID[691]:CKMPER0*/ + [655] = {0xE7752464U, 0x0000000AU}, /* RGIDW_MODID[692]:ECMPER0*/ + [656] = {0xE7752468U, 0x0000000EU}, /* RGIDW_MODID[693]:FBAPER0*/ + [657] = {0xE775246CU, 0x0000004EU}, /* RGIDW_MODID[694]:FSO0*/ + [658] = {0xE7752470U, 0x0000004EU}, /* RGIDW_MODID[695]:FSO1*/ + [659] = {0xE7752474U, 0x0000004EU}, /* RGIDW_MODID[696]:FSO10*/ + [660] = {0xE7752478U, 0x0000004EU}, /* RGIDW_MODID[697]:FSO2*/ + [661] = {0xE775247CU, 0x0000004EU}, /* RGIDW_MODID[698]:FSO3*/ + [662] = {0xE7752480U, 0x0000004EU}, /* RGIDW_MODID[699]:FSO4*/ + [663] = {0xE7752484U, 0x0000004EU}, /* RGIDW_MODID[700]:FSO5*/ + [664] = {0xE7752488U, 0x0000004EU}, /* RGIDW_MODID[701]:FSO6*/ + [665] = {0xE775248CU, 0x0000004EU}, /* RGIDW_MODID[702]:FSO7*/ + [666] = {0xE7752490U, 0x0000004EU}, /* RGIDW_MODID[703]:FSO8*/ + [667] = {0xE7752494U, 0x0000004EU}, /* RGIDW_MODID[704]:FSO9*/ + [668] = {0xE7752498U, 0x0000002CU}, /* RGIDW_MODID[705]:ADG*/ + [669] = {0xE775249CU, 0x0000000AU}, /* RGIDW_MODID[706]:ECMSD0*/ + [670] = {0xE77524A0U, 0x0000004EU}, /* RGIDW_MODID[707]:IPMMUDS010*/ + [671] = {0xE77524A4U, 0x0000004EU}, /* RGIDW_MODID[708]:IPMMUDS011*/ + [672] = {0xE77524A8U, 0x0000004EU}, /* RGIDW_MODID[709]:I2C0*/ + [673] = {0xE77524ACU, 0x0000004EU}, /* RGIDW_MODID[710]:I2C1*/ + [674] = {0xE77524B0U, 0x0000004EU}, /* RGIDW_MODID[711]:I2C2*/ + [675] = {0xE77524B4U, 0x0000004EU}, /* RGIDW_MODID[712]:I2C3*/ + [676] = {0xE77524B8U, 0x0000004EU}, /* RGIDW_MODID[713]:I2C4*/ + [677] = {0xE77524BCU, 0x0000004EU}, /* RGIDW_MODID[714]:I2C5*/ + [678] = {0xE77524C0U, 0x0000004EU}, /* RGIDW_MODID[715]:IPMMUDS012*/ + [679] = {0xE77524C4U, 0x0000000FU}, /* RGIDW_MODID[716]:IPC*/ + [680] = {0xE77524C8U, 0x0000004EU}, /* RGIDW_MODID[717]:IPMMUDS000*/ + [681] = {0xE77524CCU, 0x0000004EU}, /* RGIDW_MODID[718]:IPMMUDS013*/ + [682] = {0xE77524D0U, 0x0000004EU}, /* RGIDW_MODID[719]:IPMMUDS014*/ + [683] = {0xE77524D4U, 0x0000004EU}, /* RGIDW_MODID[720]:IPMMUDS015*/ + [684] = {0xE77524D8U, 0x0000004EU}, /* RGIDW_MODID[721]:IPMMUDS002*/ + [685] = {0xE77524DCU, 0x0000004EU}, /* RGIDW_MODID[722]:IPMMUDS003*/ + [686] = {0xE77524E0U, 0x0000004EU}, /* RGIDW_MODID[723]:IPMMUDS004*/ + [687] = {0xE77524E4U, 0x0000004EU}, /* RGIDW_MODID[724]:IPMMUDS005*/ + [688] = {0xE77524E8U, 0x0000002CU}, /* RGIDW_MODID[725]:SSI*/ + [689] = {0xE77524ECU, 0x0000004EU}, /* RGIDW_MODID[726]:IPMMUDS006*/ + [690] = {0xE77524F0U, 0x0000004EU}, /* RGIDW_MODID[727]:IPMMUDS007*/ + [691] = {0xE77524F4U, 0x0000000CU}, /* RGIDW_MODID[728]:SYDM1P*/ + [692] = {0xE77524F8U, 0x0000004EU}, /* RGIDW_MODID[729]:IPMMUDS008*/ + [693] = {0xE77524FCU, 0x0000000CU}, /* RGIDW_MODID[730]:SYDM2P*/ + [694] = {0xE7752500U, 0x0000004EU}, /* RGIDW_MODID[731]:IPMMUDS009*/ + [695] = {0xE7752640U, 0x0000000CU}, /* RGIDW_MODID[732]:SYDM100*/ + [696] = {0xE7752644U, 0x0000000CU}, /* RGIDW_MODID[733]:SYDM101*/ + [697] = {0xE7752648U, 0x0000000CU}, /* RGIDW_MODID[734]:SYDM110*/ + [698] = {0xE775264CU, 0x0000000CU}, /* RGIDW_MODID[735]:SYDM111*/ + [699] = {0xE7752650U, 0x0000000CU}, /* RGIDW_MODID[736]:SYDM112*/ + [700] = {0xE7752654U, 0x0000000CU}, /* RGIDW_MODID[737]:SYDM113*/ + [701] = {0xE7752658U, 0x0000000CU}, /* RGIDW_MODID[738]:SYDM114*/ + [702] = {0xE775265CU, 0x0000000CU}, /* RGIDW_MODID[739]:SYDM115*/ + [703] = {0xE7752660U, 0x0000000CU}, /* RGIDW_MODID[740]:SYDM102*/ + [704] = {0xE7752664U, 0x0000000CU}, /* RGIDW_MODID[741]:SYDM103*/ + [705] = {0xE7752668U, 0x0000000CU}, /* RGIDW_MODID[742]:SYDM104*/ + [706] = {0xE775266CU, 0x0000000CU}, /* RGIDW_MODID[743]:SYDM105*/ + [707] = {0xE7752670U, 0x0000000CU}, /* RGIDW_MODID[744]:SYDM106*/ + [708] = {0xE7752674U, 0x0000000CU}, /* RGIDW_MODID[745]:SYDM107*/ + [709] = {0xE7752678U, 0x0000000CU}, /* RGIDW_MODID[746]:SYDM108*/ + [710] = {0xE775267CU, 0x0000000CU}, /* RGIDW_MODID[747]:SYDM109*/ + [711] = {0xE7752680U, 0x0000000CU}, /* RGIDW_MODID[748]:SYDM200*/ + [712] = {0xE7752684U, 0x0000000CU}, /* RGIDW_MODID[749]:SYDM201*/ + [713] = {0xE7752688U, 0x0000000CU}, /* RGIDW_MODID[750]:SYDM210*/ + [714] = {0xE775268CU, 0x0000000CU}, /* RGIDW_MODID[751]:SYDM211*/ + [715] = {0xE7752690U, 0x0000000CU}, /* RGIDW_MODID[752]:SYDM212*/ + [716] = {0xE7752694U, 0x0000000CU}, /* RGIDW_MODID[753]:SYDM213*/ + [717] = {0xE7752698U, 0x0000000CU}, /* RGIDW_MODID[754]:SYDM214*/ + [718] = {0xE775269CU, 0x0000000CU}, /* RGIDW_MODID[755]:SYDM215*/ + [719] = {0xE77526A0U, 0x0000000CU}, /* RGIDW_MODID[756]:SYDM202*/ + [720] = {0xE77526A4U, 0x0000000CU}, /* RGIDW_MODID[757]:SYDM203*/ + [721] = {0xE77526A8U, 0x0000000CU}, /* RGIDW_MODID[758]:SYDM204*/ + [722] = {0xE77526ACU, 0x0000000CU}, /* RGIDW_MODID[759]:SYDM205*/ + [723] = {0xE77526B0U, 0x0000000CU}, /* RGIDW_MODID[760]:SYDM206*/ + [724] = {0xE77526B4U, 0x0000000CU}, /* RGIDW_MODID[761]:SYDM207*/ + [725] = {0xE77526B8U, 0x0000000CU}, /* RGIDW_MODID[762]:SYDM208*/ + [726] = {0xE77526BCU, 0x0000000CU}, /* RGIDW_MODID[763]:SYDM209*/ + [727] = {0xFE682400U, 0x00000002U}, /* RGIDW_MODID[764]:ARVC0*/ + /* After setting */ /* RGIDW_MODID[765]:ARVC1*/ + /* After setting */ /* RGIDW_MODID[766]:ARVC2*/ + [728] = {0xFE68240CU, 0x00000001U}, /* RGIDW_MODID[767]:ARVC3*/ + [729] = {0xFE682410U, 0x0000000EU}, /* RGIDW_MODID[768]:AXIFBABUSVC*/ + [730] = {0xFE682414U, 0x00000002U}, /* RGIDW_MODID[769]:ARVC4*/ + [731] = {0xFE682418U, 0x00000001U}, /* RGIDW_MODID[770]:ARVC5*/ + [732] = {0xFE68241CU, 0x00000002U}, /* RGIDW_MODID[771]:ARVC6*/ + [733] = {0xFE682420U, 0x00000002U}, /* RGIDW_MODID[772]:ARVC7*/ + [734] = {0xFE682424U, 0x00000000U}, /* RGIDW_MODID[773]:ARVC8*/ + [735] = {0xFE682428U, 0x0000000AU}, /* RGIDW_MODID[774]:CKMVC*/ + [736] = {0xFE68242CU, 0x0000000AU}, /* RGIDW_MODID[775]:ECMVC0*/ + [737] = {0xFE682430U, 0x0000004EU}, /* RGIDW_MODID[776]:IMR2*/ + [738] = {0xFE682434U, 0x0000004EU}, /* RGIDW_MODID[777]:IMR0*/ + [739] = {0xFE682438U, 0x0000004EU}, /* RGIDW_MODID[778]:IMR1*/ + [740] = {0xFE68243CU, 0x0000004EU}, /* RGIDW_MODID[779]:IPMMUVC01*/ + [741] = {0xFE682440U, 0x0000004EU}, /* RGIDW_MODID[780]:IPMMUVC10*/ + [742] = {0xFE682444U, 0x0000000CU}, /* RGIDW_MODID[781]:IMS0*/ + [743] = {0xFE682448U, 0x0000000CU}, /* RGIDW_MODID[782]:IMS1*/ + [744] = {0xFE68244CU, 0x0000004EU}, /* RGIDW_MODID[783]:IPMMUVC00*/ + [745] = {0xFE682450U, 0x0000004EU}, /* RGIDW_MODID[784]:IPMMUVC11*/ + [746] = {0xFE682454U, 0x0000004EU}, /* RGIDW_MODID[785]:IPMMUVC12*/ + [747] = {0xFE682458U, 0x0000004EU}, /* RGIDW_MODID[786]:IPMMUVC13*/ + [748] = {0xFE68245CU, 0x0000004EU}, /* RGIDW_MODID[787]:IPMMUVC14*/ + [749] = {0xFE682460U, 0x0000004EU}, /* RGIDW_MODID[788]:IPMMUVC15*/ + [750] = {0xFE682464U, 0x0000004EU}, /* RGIDW_MODID[789]:IPMMUVC02*/ + [751] = {0xFE682468U, 0x0000004EU}, /* RGIDW_MODID[790]:IPMMUVC03*/ + [752] = {0xFE68246CU, 0x0000004EU}, /* RGIDW_MODID[791]:IPMMUVC04*/ + [753] = {0xFE682470U, 0x0000004EU}, /* RGIDW_MODID[792]:IPMMUVC05*/ + [754] = {0xFE682474U, 0x0000004EU}, /* RGIDW_MODID[793]:IPMMUVC06*/ + [755] = {0xFE682478U, 0x0000004EU}, /* RGIDW_MODID[794]:IPMMUVC07*/ + [756] = {0xFE68247CU, 0x0000004EU}, /* RGIDW_MODID[795]:IPMMUVC08*/ + [757] = {0xFE682480U, 0x0000004EU}, /* RGIDW_MODID[796]:IPMMUVC09*/ + [758] = {0xFE682484U, 0x00000028U}, /* RGIDW_MODID[797]:IV1ES*/ + [759] = {0xFEBE2400U, 0x0000004EU}, /* RGIDW_MODID[798]:CSITOP0*/ + [760] = {0xFEBE2404U, 0x00000002U}, /* RGIDW_MODID[799]:ARVI10*/ + /* After setting */ /* RGIDW_MODID[800]:ARVI11*/ + /* After setting */ /* RGIDW_MODID[801]:ARVI12*/ + [761] = {0xFEBE2410U, 0x00000001U}, /* RGIDW_MODID[802]:ARVI13*/ + [762] = {0xFEBE2414U, 0x00000002U}, /* RGIDW_MODID[803]:ARVI14*/ + [763] = {0xFEBE2418U, 0x00000001U}, /* RGIDW_MODID[804]:ARVI15*/ + [764] = {0xFEBE241CU, 0x00000002U}, /* RGIDW_MODID[805]:ARVI16*/ + [765] = {0xFEBE2420U, 0x00000002U}, /* RGIDW_MODID[806]:ARVI17*/ + [766] = {0xFEBE2424U, 0x00000000U}, /* RGIDW_MODID[807]:ARVI18*/ + [767] = {0xFEBE2428U, 0x0000000AU}, /* RGIDW_MODID[808]:CKMVIO*/ + [768] = {0xFEBE242CU, 0x0000004EU}, /* RGIDW_MODID[809]:CSITOP1*/ + [769] = {0xFEBE2434U, 0x0000004EU}, /* RGIDW_MODID[810]:DSITLINK0*/ + [770] = {0xFEBE2438U, 0x0000004EU}, /* RGIDW_MODID[811]:DSITLINK1*/ + [771] = {0xFEBE243CU, 0x0000000AU}, /* RGIDW_MODID[812]:ECMVIO1*/ + [772] = {0xFEBE2444U, 0x0000004EU}, /* RGIDW_MODID[813]:IPMMUVI001*/ + [773] = {0xFEBE2448U, 0x0000000CU}, /* RGIDW_MODID[814]:FCPVX0*/ + [774] = {0xFEBE244CU, 0x0000000CU}, /* RGIDW_MODID[815]:FCPVX1*/ + [775] = {0xFEBE2458U, 0x0000004EU}, /* RGIDW_MODID[816]:IPMMUVI000*/ + [776] = {0xFEBE245CU, 0x0000004EU}, /* RGIDW_MODID[817]:IPMMUVI100*/ + [777] = {0xFEBE2460U, 0x0000004EU}, /* RGIDW_MODID[818]:IPMMUVI010*/ + [778] = {0xFEBE2464U, 0x0000004EU}, /* RGIDW_MODID[819]:IPMMUVI011*/ + [779] = {0xFEBE2468U, 0x0000004EU}, /* RGIDW_MODID[820]:VSPX0*/ + [780] = {0xFEBE246CU, 0x0000004EU}, /* RGIDW_MODID[821]:VSPX1*/ + [781] = {0xFEBE2478U, 0x0000004EU}, /* RGIDW_MODID[822]:IPMMUVI012*/ + [782] = {0xFEBE247CU, 0x0000004EU}, /* RGIDW_MODID[823]:IPMMUVI013*/ + [783] = {0xFEBE2480U, 0x0000004EU}, /* RGIDW_MODID[824]:IPMMUVI014*/ + [784] = {0xFEBE2484U, 0x0000004EU}, /* RGIDW_MODID[825]:IPMMUVI015*/ + [785] = {0xFEBE2488U, 0x0000004EU}, /* RGIDW_MODID[826]:IPMMUVI002*/ + [786] = {0xFEBE248CU, 0x0000004EU}, /* RGIDW_MODID[827]:IPMMUVI003*/ + [787] = {0xFEBE2490U, 0x0000004EU}, /* RGIDW_MODID[828]:IPMMUVI004*/ + [788] = {0xFEBE2494U, 0x0000004EU}, /* RGIDW_MODID[829]:IPMMUVI005*/ + [789] = {0xFEBE2498U, 0x0000004EU}, /* RGIDW_MODID[830]:IPMMUVI006*/ + [790] = {0xFEBE249CU, 0x0000004EU}, /* RGIDW_MODID[831]:IPMMUVI007*/ + [791] = {0xFEBE24A0U, 0x0000004EU}, /* RGIDW_MODID[832]:IPMMUVI008*/ + [792] = {0xFEBE24A4U, 0x0000004EU}, /* RGIDW_MODID[833]:IPMMUVI009*/ + [793] = {0xFEBE24A8U, 0x0000004EU}, /* RGIDW_MODID[834]:IPMMUVI101*/ + [794] = {0xFEBE24ACU, 0x0000004EU}, /* RGIDW_MODID[835]:IPMMUVI110*/ + [795] = {0xFEBE24B0U, 0x0000004EU}, /* RGIDW_MODID[836]:IPMMUVI111*/ + [796] = {0xFEBE24B4U, 0x0000004EU}, /* RGIDW_MODID[837]:IPMMUVI112*/ + [797] = {0xFEBE24B8U, 0x0000004EU}, /* RGIDW_MODID[838]:IPMMUVI113*/ + [798] = {0xFEBE24BCU, 0x0000004EU}, /* RGIDW_MODID[839]:IPMMUVI114*/ + [799] = {0xFEBE24C0U, 0x0000004EU}, /* RGIDW_MODID[840]:IPMMUVI115*/ + [800] = {0xFEBE24C4U, 0x0000004EU}, /* RGIDW_MODID[841]:IPMMUVI102*/ + [801] = {0xFEBE24C8U, 0x0000004EU}, /* RGIDW_MODID[842]:IPMMUVI103*/ + [802] = {0xFEBE24CCU, 0x0000004EU}, /* RGIDW_MODID[843]:IPMMUVI104*/ + [803] = {0xFEBE24D0U, 0x0000004EU}, /* RGIDW_MODID[844]:IPMMUVI105*/ + [804] = {0xFEBE24D4U, 0x0000004EU}, /* RGIDW_MODID[845]:IPMMUVI106*/ + [805] = {0xFEBE24D8U, 0x0000004EU}, /* RGIDW_MODID[846]:IPMMUVI107*/ + [806] = {0xFEBE24DCU, 0x0000004EU}, /* RGIDW_MODID[847]:IPMMUVI108*/ + [807] = {0xFEBE24E0U, 0x0000004EU}, /* RGIDW_MODID[848]:IPMMUVI109*/ + [808] = {0xFEBE2504U, 0x0000000EU}, /* RGIDW_MODID[849]:AXIFBABUSVIO*/ + [809] = {0xFEBF2400U, 0x00000002U}, /* RGIDW_MODID[850]:ARVI0*/ + /* After setting */ /* RGIDW_MODID[851]:ARVI1*/ + /* After setting */ /* RGIDW_MODID[852]:ARVI2*/ + [810] = {0xFEBF240CU, 0x00000001U}, /* RGIDW_MODID[853]:ARVI3*/ + [811] = {0xFEBF2410U, 0x00000002U}, /* RGIDW_MODID[854]:ARVI4*/ + [812] = {0xFEBF2414U, 0x00000001U}, /* RGIDW_MODID[855]:ARVI5*/ + [813] = {0xFEBF2418U, 0x00000002U}, /* RGIDW_MODID[856]:ARVI6*/ + [814] = {0xFEBF241CU, 0x00000002U}, /* RGIDW_MODID[857]:ARVI7*/ + [815] = {0xFEBF2420U, 0x00000000U}, /* RGIDW_MODID[858]:ARVI8*/ + [816] = {0xFEBF2424U, 0x0000000AU}, /* RGIDW_MODID[859]:ECMVIO0*/ + [817] = {0xFEBF2428U, 0x0000004EU}, /* RGIDW_MODID[860]:ISP0*/ + [818] = {0xFEBF242CU, 0x0000004EU}, /* RGIDW_MODID[861]:ISP0CORE*/ + [819] = {0xFEBF2430U, 0x0000004EU}, /* RGIDW_MODID[862]:ISP1*/ + [820] = {0xFEBF2434U, 0x0000004EU}, /* RGIDW_MODID[863]:ISP1CORE*/ + [821] = {0xFEBF2454U, 0x0000004EU}, /* RGIDW_MODID[864]:VIN00*/ + [822] = {0xFEBF2458U, 0x0000004EU}, /* RGIDW_MODID[865]:VIN01*/ + [823] = {0xFEBF245CU, 0x0000004EU}, /* RGIDW_MODID[866]:VIN02*/ + [824] = {0xFEBF2460U, 0x0000004EU}, /* RGIDW_MODID[867]:VIN03*/ + [825] = {0xFEBF2464U, 0x0000004EU}, /* RGIDW_MODID[868]:VIN04*/ + [826] = {0xFEBF2468U, 0x0000004EU}, /* RGIDW_MODID[869]:VIN05*/ + [827] = {0xFEBF246CU, 0x0000004EU}, /* RGIDW_MODID[870]:VIN06*/ + [828] = {0xFEBF2470U, 0x0000004EU}, /* RGIDW_MODID[871]:VIN07*/ + [829] = {0xFEBF2474U, 0x0000004EU}, /* RGIDW_MODID[872]:VIN10*/ + [830] = {0xFEBF2478U, 0x0000004EU}, /* RGIDW_MODID[873]:VIN11*/ + [831] = {0xFEBF247CU, 0x0000004EU}, /* RGIDW_MODID[874]:VIN12*/ + [832] = {0xFEBF2480U, 0x0000004EU}, /* RGIDW_MODID[875]:VIN13*/ + [833] = {0xFEBF2484U, 0x0000004EU}, /* RGIDW_MODID[876]:VIN14*/ + [834] = {0xFEBF2488U, 0x0000004EU}, /* RGIDW_MODID[877]:VIN15*/ + [835] = {0xFEBF248CU, 0x0000004EU}, /* RGIDW_MODID[878]:VIN16*/ + [836] = {0xFEBF2490U, 0x0000004EU}, /* RGIDW_MODID[879]:VIN17*/ + [837] = {0xE7B12400U, 0x00000002U}, /* RGIDW_MODID[880]:ARVIP00*/ + /* After setting */ /* RGIDW_MODID[881]:ARVIP01*/ + /* After setting */ /* RGIDW_MODID[882]:ARVIP02*/ + [838] = {0xE7B1240CU, 0x00000001U}, /* RGIDW_MODID[883]:ARVIP03*/ + [839] = {0xE7B12410U, 0x0000000EU}, /* RGIDW_MODID[884]:AXIFBABUSVIP0*/ + [840] = {0xE7B12414U, 0x00000002U}, /* RGIDW_MODID[885]:ARVIP04*/ + [841] = {0xE7B12418U, 0x00000001U}, /* RGIDW_MODID[886]:ARVIP05*/ + [842] = {0xE7B1241CU, 0x00000002U}, /* RGIDW_MODID[887]:ARVIP06*/ + [843] = {0xE7B12420U, 0x00000002U}, /* RGIDW_MODID[888]:ARVIP07*/ + [844] = {0xE7B12424U, 0x00000000U}, /* RGIDW_MODID[889]:ARVIP08*/ + [845] = {0xE7B12428U, 0x0000000AU}, /* RGIDW_MODID[890]:CKMVIP*/ + [846] = {0xE7B1242CU, 0x0000000AU}, /* RGIDW_MODID[891]:ECMVIP0*/ + [847] = {0xE7B12430U, 0x0000004EU}, /* RGIDW_MODID[892]:IPMMUVIP000*/ + [848] = {0xE7B12438U, 0x0000004EU}, /* RGIDW_MODID[893]:SMPO0*/ + [849] = {0xE7B1243CU, 0x0000004EU}, /* RGIDW_MODID[894]:SMPS0*/ + [850] = {0xE7B12440U, 0x0000000CU}, /* RGIDW_MODID[895]:UMFL0*/ + [851] = {0xE7B12444U, 0x0000004EU}, /* RGIDW_MODID[896]:IPMMUVIP001*/ + [852] = {0xE7B12448U, 0x0000004EU}, /* RGIDW_MODID[897]:IPMMUVIP010*/ + [853] = {0xE7B1244CU, 0x0000004EU}, /* RGIDW_MODID[898]:IPMMUVIP011*/ + [854] = {0xE7B12450U, 0x0000004EU}, /* RGIDW_MODID[899]:UMFL0M_W*/ + [855] = {0xE7B12454U, 0x0000004EU}, /* RGIDW_MODID[900]:IPMMUVIP012*/ + [856] = {0xE7B12458U, 0x0000004EU}, /* RGIDW_MODID[901]:IPMMUVIP013*/ + [857] = {0xE7B1245CU, 0x0000004EU}, /* RGIDW_MODID[902]:IPMMUVIP014*/ + [858] = {0xE7B12460U, 0x0000004EU}, /* RGIDW_MODID[903]:IPMMUVIP015*/ + [859] = {0xE7B12464U, 0x0000004EU}, /* RGIDW_MODID[904]:IPMMUVIP002*/ + [860] = {0xE7B12468U, 0x0000004EU}, /* RGIDW_MODID[905]:IPMMUVIP003*/ + [861] = {0xE7B1246CU, 0x0000004EU}, /* RGIDW_MODID[906]:IPMMUVIP004*/ + [862] = {0xE7B12470U, 0x0000004EU}, /* RGIDW_MODID[907]:IPMMUVIP005*/ + [863] = {0xE7B12474U, 0x0000004EU}, /* RGIDW_MODID[908]:IPMMUVIP006*/ + [864] = {0xE7B12478U, 0x0000004EU}, /* RGIDW_MODID[909]:IPMMUVIP007*/ + [865] = {0xE7B1247CU, 0x0000004EU}, /* RGIDW_MODID[910]:IPMMUVIP008*/ + [866] = {0xE7B12480U, 0x0000004EU}, /* RGIDW_MODID[911]:IPMMUVIP009*/ + [867] = {0xE7B42400U, 0x00000002U}, /* RGIDW_MODID[912]:ARVIP10*/ + /* After setting */ /* RGIDW_MODID[913]:ARVIP11*/ + /* After setting */ /* RGIDW_MODID[914]:ARVIP12*/ + [868] = {0xE7B4240CU, 0x00000001U}, /* RGIDW_MODID[915]:ARVIP13*/ + [869] = {0xE7B42410U, 0x0000000EU}, /* RGIDW_MODID[916]:AXIFBABUSVIP1*/ + [870] = {0xE7B42414U, 0x00000002U}, /* RGIDW_MODID[917]:ARVIIP14*/ + [871] = {0xE7B42418U, 0x00000001U}, /* RGIDW_MODID[918]:ARVIIP15*/ + [872] = {0xE7B4241CU, 0x00000002U}, /* RGIDW_MODID[919]:ARVIIP16*/ + [873] = {0xE7B42420U, 0x00000002U}, /* RGIDW_MODID[920]:ARVIIP17*/ + [874] = {0xE7B42424U, 0x00000000U}, /* RGIDW_MODID[921]:ARVIIP18*/ + [875] = {0xE7B42438U, 0x0000000AU}, /* RGIDW_MODID[922]:ECMVIP1*/ + [876] = {0xE7B4243CU, 0x0000004EU}, /* RGIDW_MODID[923]:IPMMUVIP101*/ + [877] = {0xE7B42440U, 0x0000004EU}, /* RGIDW_MODID[924]:IPMMUVIP100*/ + [878] = {0xE7B42444U, 0x0000004EU}, /* RGIDW_MODID[925]:IPMMUVIP110*/ + [879] = {0xE7B42448U, 0x0000004EU}, /* RGIDW_MODID[926]:IPMMUVIP111*/ + [880] = {0xE7B4244CU, 0x0000004EU}, /* RGIDW_MODID[927]:IPMMUVIP112*/ + [881] = {0xE7B42450U, 0x0000004EU}, /* RGIDW_MODID[928]:IPMMUVIP113*/ + [882] = {0xE7B42454U, 0x0000004EU}, /* RGIDW_MODID[929]:IPMMUVIP114*/ + [883] = {0xE7B42458U, 0x0000004EU}, /* RGIDW_MODID[930]:IPMMUVIP115*/ + [884] = {0xE7B4245CU, 0x0000004EU}, /* RGIDW_MODID[931]:IPMMUVIP102*/ + [885] = {0xE7B42460U, 0x0000004EU}, /* RGIDW_MODID[932]:IPMMUVIP103*/ + [886] = {0xE7B42464U, 0x0000004EU}, /* RGIDW_MODID[933]:IPMMUVIP104*/ + [887] = {0xE7B42468U, 0x0000004EU}, /* RGIDW_MODID[934]:IPMMUVIP105*/ + [888] = {0xE7B4246CU, 0x0000004EU}, /* RGIDW_MODID[935]:IPMMUVIP106*/ + [889] = {0xE7B42470U, 0x0000004EU}, /* RGIDW_MODID[936]:IPMMUVIP107*/ + [890] = {0xE7B42474U, 0x0000004EU}, /* RGIDW_MODID[937]:IPMMUVIP108*/ + [891] = {0xE7B42478U, 0x0000004EU}, /* RGIDW_MODID[938]:IPMMUVIP109*/ + [892] = {0xE7B42518U, 0x00000004U}, /* RGIDW_MODID[939]:PAP*/ + [893] = {0xEB802400U, 0x00000002U}, /* RGIDW_MODID[940]:ARDSP0*/ + /* After setting */ /* RGIDW_MODID[941]:ARDSP1*/ + /* After setting */ /* RGIDW_MODID[942]:ARDSP2*/ + [894] = {0xEB80240CU, 0x00000001U}, /* RGIDW_MODID[943]:ARDSP3*/ + [895] = {0xEB802410U, 0x00000002U}, /* RGIDW_MODID[944]:ARDSP4*/ + [896] = {0xEB802414U, 0x00000001U}, /* RGIDW_MODID[945]:ARDSP5*/ + [897] = {0xEB802418U, 0x00000002U}, /* RGIDW_MODID[946]:ARDSP6*/ + [898] = {0xEB80241CU, 0x00000002U}, /* RGIDW_MODID[947]:ARDSP7*/ + [899] = {0xEB802420U, 0x0000000AU}, /* RGIDW_MODID[948]:ECMDSP*/ + [900] = {0xEB802424U, 0x0000000CU}, /* RGIDW_MODID[949]:AXIDSP0*/ + [901] = {0xEB802428U, 0x0000000CU}, /* RGIDW_MODID[950]:AXIDSP1*/ + [902] = {0xEB80242CU, 0x0000000CU}, /* RGIDW_MODID[951]:AXIDSP2*/ + [903] = {0xEB802430U, 0x0000000CU}, /* RGIDW_MODID[952]:AXIDSP3*/ + [905] = {0xE67B969CU, 0x00000000U}, /* RGIDW_MODID[953]:ARCC*/ + [904] = {0xE67B96B0U, 0x00000000U}, /* RGIDW_MODID[954]:ARRTRAM*/ + [906] = {0xE7752424U, 0x00000000U}, /* RGIDW_MODID[955]:RSV0*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_sec_tbl" +#else +__attribute__ ((section(".rgid_sec_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[] = { + [0] = {0xFFC83400U, 0x00000000U}, /* SEC_MODID[0]:ARMGC0*/ + [1] = {0xFFC83404U, 0x00000002U}, /* SEC_MODID[1]:ARMGC1*/ + [2] = {0xFFC83408U, 0x00000002U}, /* SEC_MODID[2]:ARMGC2*/ + [3] = {0xFFC8340CU, 0x00000002U}, /* SEC_MODID[3]:ARRT00*/ + [4] = {0xFFC83410U, 0x00000002U}, /* SEC_MODID[4]:ARRT01*/ + [5] = {0xFFC83414U, 0x00000002U}, /* SEC_MODID[5]:ARRT02*/ + [6] = {0xFFC83418U, 0x00000002U}, /* SEC_MODID[6]:ARRT03*/ + [7] = {0xFFC8341CU, 0x00000002U}, /* SEC_MODID[7]:ARRT04*/ + [8] = {0xFFC83420U, 0x00000002U}, /* SEC_MODID[8]:ARRT05*/ + [9] = {0xFFC83424U, 0x00000002U}, /* SEC_MODID[9]:ARRT06*/ + [10] = {0xFFC83428U, 0x00000002U}, /* SEC_MODID[10]:ARRT07*/ + [11] = {0xFFC8342CU, 0x00000002U}, /* SEC_MODID[11]:ARRT08*/ + [12] = {0xFFC83430U, 0x00000000U}, /* SEC_MODID[12]:LIFEC0*/ + [13] = {0xFFC83434U, 0x00000002U}, /* SEC_MODID[13]:SWDT*/ + [14] = {0xFFC83438U, 0x00000002U}, /* SEC_MODID[14]:TMU0*/ + [15] = {0xFFC8343CU, 0x00000002U}, /* SEC_MODID[15]:WDT*/ + [16] = {0xFFC83440U, 0x00000002U}, /* SEC_MODID[16]:WWDT0*/ + [17] = {0xFFC83444U, 0x00000002U}, /* SEC_MODID[17]:WWDT1*/ + [18] = {0xFFC83448U, 0x00000002U}, /* SEC_MODID[18]:WWDT2*/ + [19] = {0xFFC8344CU, 0x00000002U}, /* SEC_MODID[19]:WWDT3*/ + [20] = {0xFFC83450U, 0x00000002U}, /* SEC_MODID[20]:WWDT4*/ + [21] = {0xFFC83454U, 0x00000002U}, /* SEC_MODID[21]:WWDT5*/ + [22] = {0xFFC83458U, 0x00000002U}, /* SEC_MODID[22]:WWDT6*/ + [23] = {0xFFC83468U, 0x00000002U}, /* SEC_MODID[23]:ECMRT3*/ + [24] = {0xE6003400U, 0x00000002U}, /* SEC_MODID[24]:ADVFSC*/ + [25] = {0xE6003404U, 0x00000002U}, /* SEC_MODID[25]:APMU0*/ + [26] = {0xE6003408U, 0x00000002U}, /* SEC_MODID[26]:APMU1*/ + [27] = {0xE600340CU, 0x00000002U}, /* SEC_MODID[27]:APMU10*/ + [28] = {0xE6003410U, 0x00000002U}, /* SEC_MODID[28]:APMU11*/ + [29] = {0xE6003414U, 0x00000002U}, /* SEC_MODID[29]:APMU12*/ + [30] = {0xE6003418U, 0x00000002U}, /* SEC_MODID[30]:APMU13*/ + [31] = {0xE600341CU, 0x00000002U}, /* SEC_MODID[31]:APMU14*/ + [32] = {0xE6003420U, 0x00000002U}, /* SEC_MODID[32]:APMU15*/ + [33] = {0xE6003424U, 0x00000002U}, /* SEC_MODID[33]:APMU2*/ + [34] = {0xE6003428U, 0x00000002U}, /* SEC_MODID[34]:APMU3*/ + [35] = {0xE600342CU, 0x00000002U}, /* SEC_MODID[35]:APMU4*/ + [36] = {0xE6003430U, 0x00000002U}, /* SEC_MODID[36]:APMU5*/ + [37] = {0xE6003434U, 0x00000002U}, /* SEC_MODID[37]:APMU6*/ + [38] = {0xE6003438U, 0x00000002U}, /* SEC_MODID[38]:APMU7*/ + [39] = {0xE600343CU, 0x00000002U}, /* SEC_MODID[39]:APMU8*/ + [40] = {0xE6003440U, 0x00000002U}, /* SEC_MODID[40]:APMU9*/ + [41] = {0xE6003444U, 0x00000002U}, /* SEC_MODID[41]:ARS00*/ + [42] = {0xE6003448U, 0x00000002U}, /* SEC_MODID[42]:ARS01*/ + [43] = {0xE600344CU, 0x00000002U}, /* SEC_MODID[43]:ARS02*/ + [44] = {0xE6003450U, 0x00000002U}, /* SEC_MODID[44]:ARS03*/ + [45] = {0xE6003454U, 0x00000002U}, /* SEC_MODID[45]:ARS04*/ + [46] = {0xE6003458U, 0x00000002U}, /* SEC_MODID[46]:ARS05*/ + [47] = {0xE600345CU, 0x00000002U}, /* SEC_MODID[47]:ARS06*/ + [48] = {0xE6003460U, 0x00000002U}, /* SEC_MODID[48]:ARS07*/ + [49] = {0xE6003464U, 0x00000002U}, /* SEC_MODID[49]:ARS08*/ + [50] = {0xE6003468U, 0x00000002U}, /* SEC_MODID[50]:CMT0*/ + [51] = {0xE600346CU, 0x00000002U}, /* SEC_MODID[51]:CMT1*/ + [52] = {0xE6003470U, 0x00000002U}, /* SEC_MODID[52]:CMT2*/ + [53] = {0xE6003474U, 0x00000002U}, /* SEC_MODID[53]:CMT3*/ + [54] = {0xE6003478U, 0x00000002U}, /* SEC_MODID[54]:CKM*/ + [55] = {0xE600347CU, 0x00000002U}, /* SEC_MODID[55]:DBE*/ + [56] = {0xE6003480U, 0x00000002U}, /* SEC_MODID[56]:IRQC*/ + [57] = {0xE6003484U, 0x00000002U}, /* SEC_MODID[57]:ECMPS0*/ + [58] = {0xE6003488U, 0x00000002U}, /* SEC_MODID[58]:OTP0*/ + [59] = {0xE600348CU, 0x00000002U}, /* SEC_MODID[59]:OTP1*/ + [60] = {0xE600349CU, 0x00000002U}, /* SEC_MODID[60]:SCMT*/ + [61] = {0xE60034A8U, 0x00000002U}, /* SEC_MODID[61]:TSC1*/ + [62] = {0xE60034ACU, 0x00000002U}, /* SEC_MODID[62]:TSC2*/ + [63] = {0xE60034B0U, 0x00000002U}, /* SEC_MODID[63]:TSC3*/ + [64] = {0xE60034B4U, 0x00000002U}, /* SEC_MODID[64]:TSC4*/ + [65] = {0xE60034B8U, 0x00000002U}, /* SEC_MODID[65]:UCMT*/ + [66] = {0xE6003500U, 0x00000002U}, /* SEC_MODID[66]:CPG0*/ + [67] = {0xE6003504U, 0x00000002U}, /* SEC_MODID[67]:CPG1*/ + [68] = {0xE6003508U, 0x00000002U}, /* SEC_MODID[68]:CPG2*/ + [69] = {0xE600350CU, 0x00000002U}, /* SEC_MODID[69]:CPG3*/ + [70] = {0xE6003510U, 0x00000002U}, /* SEC_MODID[70]:PFC00*/ + [71] = {0xE6003514U, 0x00000002U}, /* SEC_MODID[71]:PFC01*/ + [72] = {0xE6003518U, 0x00000002U}, /* SEC_MODID[72]:PFC02*/ + [73] = {0xE600351CU, 0x00000002U}, /* SEC_MODID[73]:PFC03*/ + [74] = {0xE6003520U, 0x00000002U}, /* SEC_MODID[74]:PFC10*/ + [75] = {0xE6003524U, 0x00000002U}, /* SEC_MODID[75]:PFC11*/ + [76] = {0xE6003528U, 0x00000002U}, /* SEC_MODID[76]:PFC12*/ + [77] = {0xE600352CU, 0x00000002U}, /* SEC_MODID[77]:PFC13*/ + [78] = {0xE6003530U, 0x00000002U}, /* SEC_MODID[78]:PFC20*/ + [79] = {0xE6003534U, 0x00000002U}, /* SEC_MODID[79]:PFC21*/ + [80] = {0xE6003538U, 0x00000002U}, /* SEC_MODID[80]:PFC22*/ + [81] = {0xE600353CU, 0x00000002U}, /* SEC_MODID[81]:PFC23*/ + [82] = {0xE6003540U, 0x00000002U}, /* SEC_MODID[82]:PFC30*/ + [83] = {0xE6003544U, 0x00000002U}, /* SEC_MODID[83]:PFC31*/ + [84] = {0xE6003548U, 0x00000002U}, /* SEC_MODID[84]:PFC32*/ + [85] = {0xE600354CU, 0x00000002U}, /* SEC_MODID[85]:PFC33*/ + [86] = {0xE6003550U, 0x00000002U}, /* SEC_MODID[86]:PFCS0*/ + [87] = {0xE6003554U, 0x00000002U}, /* SEC_MODID[87]:PFCS1*/ + [88] = {0xE6003558U, 0x00000002U}, /* SEC_MODID[88]:PFCS2*/ + [89] = {0xE600355CU, 0x00000002U}, /* SEC_MODID[89]:PFCS3*/ + [90] = {0xE6003560U, 0x00000002U}, /* SEC_MODID[90]:RESET0*/ + [91] = {0xE6003564U, 0x00000002U}, /* SEC_MODID[91]:RESET1*/ + [92] = {0xE6003568U, 0x00000002U}, /* SEC_MODID[92]:RESET2*/ + [93] = {0xE600356CU, 0x00000002U}, /* SEC_MODID[93]:RESET3*/ + [94] = {0xE6003570U, 0x00000002U}, /* SEC_MODID[94]:SYS0*/ + [95] = {0xE6003574U, 0x00000002U}, /* SEC_MODID[95]:SYS1*/ + [96] = {0xE6003578U, 0x00000002U}, /* SEC_MODID[96]:SYS2*/ + [97] = {0xE600357CU, 0x00000002U}, /* SEC_MODID[97]:SYS3*/ + [98] = {0xE7763400U, 0x00000002U}, /* SEC_MODID[98]:DMAMSI0*/ + [99] = {0xE7763404U, 0x00000002U}, /* SEC_MODID[99]:DMAMSI1*/ + [100] = {0xE7763408U, 0x00000002U}, /* SEC_MODID[100]:DMAMSI2*/ + [101] = {0xE776340CU, 0x00000002U}, /* SEC_MODID[101]:DMAMSI3*/ + [102] = {0xE7763410U, 0x00000002U}, /* SEC_MODID[102]:DMAMSI4*/ + [103] = {0xE7763414U, 0x00000002U}, /* SEC_MODID[103]:DMAMSI5*/ + [104] = {0xE7763418U, 0x00000002U}, /* SEC_MODID[104]:ECMSP3*/ + [105] = {0xE7763424U, 0x00000002U}, /* SEC_MODID[105]:ARSP30*/ + [106] = {0xE7763428U, 0x00000002U}, /* SEC_MODID[106]:ARSP31*/ + [107] = {0xE776342CU, 0x00000002U}, /* SEC_MODID[107]:ARSP32*/ + [108] = {0xE7763430U, 0x00000002U}, /* SEC_MODID[108]:ARSP33*/ + [109] = {0xE7763434U, 0x00000002U}, /* SEC_MODID[109]:ARSP34*/ + [110] = {0xE7763438U, 0x00000002U}, /* SEC_MODID[110]:ARSP35*/ + [111] = {0xE776343CU, 0x00000002U}, /* SEC_MODID[111]:ARSP36*/ + [112] = {0xE7763440U, 0x00000002U}, /* SEC_MODID[112]:ARSP37*/ + [113] = {0xE7763444U, 0x00000002U}, /* SEC_MODID[113]:ARSP38*/ + [114] = {0xE7763448U, 0x00000002U}, /* SEC_MODID[114]:MSI0*/ + [115] = {0xE776344CU, 0x00000002U}, /* SEC_MODID[115]:MSI1*/ + [116] = {0xE7763450U, 0x00000002U}, /* SEC_MODID[116]:MSI2*/ + [117] = {0xE7763454U, 0x00000002U}, /* SEC_MODID[117]:MSI3*/ + [118] = {0xE7763458U, 0x00000002U}, /* SEC_MODID[118]:MSI4*/ + [119] = {0xE776345CU, 0x00000002U}, /* SEC_MODID[119]:MSI5*/ + [120] = {0xE7793400U, 0x00000002U}, /* SEC_MODID[120]:ARSP40*/ + [121] = {0xE7793404U, 0x00000002U}, /* SEC_MODID[121]:ARSP41*/ + [122] = {0xE7793408U, 0x00000002U}, /* SEC_MODID[122]:ARSP42*/ + [123] = {0xE779340CU, 0x00000002U}, /* SEC_MODID[123]:ARSP43*/ + [124] = {0xE7793410U, 0x00000002U}, /* SEC_MODID[124]:ARSP44*/ + [125] = {0xE7793414U, 0x00000002U}, /* SEC_MODID[125]:ARSP45*/ + [126] = {0xE7793418U, 0x00000002U}, /* SEC_MODID[126]:ARSP46*/ + [127] = {0xE779341CU, 0x00000002U}, /* SEC_MODID[127]:ARSP47*/ + [128] = {0xE7793420U, 0x00000002U}, /* SEC_MODID[128]:ARSP48*/ + [129] = {0xE7793424U, 0x00000002U}, /* SEC_MODID[129]:DMAHSCIF0*/ + [130] = {0xE7793428U, 0x00000002U}, /* SEC_MODID[130]:DMAHSCIF1*/ + [131] = {0xE779342CU, 0x00000002U}, /* SEC_MODID[131]:DMAHSCIF2*/ + [132] = {0xE7793430U, 0x00000002U}, /* SEC_MODID[132]:DMAHSCIF3*/ + [133] = {0xE7793434U, 0x00000002U}, /* SEC_MODID[133]:DMASCIF0*/ + [134] = {0xE7793438U, 0x00000002U}, /* SEC_MODID[134]:DMASCIF1*/ + [135] = {0xE779343CU, 0x00000002U}, /* SEC_MODID[135]:DMASCIF3*/ + [136] = {0xE7793440U, 0x00000002U}, /* SEC_MODID[136]:DMASCIF4*/ + [137] = {0xE7793444U, 0x00000002U}, /* SEC_MODID[137]:ECMSP4*/ + [138] = {0xE7793448U, 0x00000002U}, /* SEC_MODID[138]:HSCIF0*/ + [139] = {0xE779344CU, 0x00000002U}, /* SEC_MODID[139]:HSCIF1*/ + [140] = {0xE7793450U, 0x00000002U}, /* SEC_MODID[140]:HSCIF2*/ + [141] = {0xE7793454U, 0x00000002U}, /* SEC_MODID[141]:HSCIF3*/ + [142] = {0xE7793458U, 0x00000002U}, /* SEC_MODID[142]:SCIF0*/ + [143] = {0xE779345CU, 0x00000002U}, /* SEC_MODID[143]:SCIF1*/ + [144] = {0xE7793460U, 0x00000002U}, /* SEC_MODID[144]:SCIF3*/ + [145] = {0xE7793464U, 0x00000002U}, /* SEC_MODID[145]:SCIF4*/ + [146] = {0xE7793468U, 0x00000002U}, /* SEC_MODID[146]:TMU1*/ + [147] = {0xE779346CU, 0x00000002U}, /* SEC_MODID[147]:TMU2*/ + [148] = {0xE7793470U, 0x00000002U}, /* SEC_MODID[148]:TMU3*/ + [149] = {0xE7793474U, 0x00000002U}, /* SEC_MODID[149]:TMU4*/ + [150] = {0xE7793478U, 0x00000002U}, /* SEC_MODID[150]:CANFD*/ + [151] = {0xE779347CU, 0x00000002U}, /* SEC_MODID[151]:DMACANFD*/ + [152] = {0xE7793480U, 0x00000002U}, /* SEC_MODID[152]:DMATPU0*/ + [153] = {0xE7793484U, 0x00000002U}, /* SEC_MODID[153]:PWM0*/ + [154] = {0xE7793488U, 0x00000002U}, /* SEC_MODID[154]:PWM1*/ + [155] = {0xE779348CU, 0x00000002U}, /* SEC_MODID[155]:PWM2*/ + [156] = {0xE7793490U, 0x00000002U}, /* SEC_MODID[156]:PWM3*/ + [157] = {0xE7793494U, 0x00000002U}, /* SEC_MODID[157]:PWM4*/ + [158] = {0xE7793498U, 0x00000002U}, /* SEC_MODID[158]:PWM5*/ + [159] = {0xE779349CU, 0x00000002U}, /* SEC_MODID[159]:PWM6*/ + [160] = {0xE77934A0U, 0x00000002U}, /* SEC_MODID[160]:PWM7*/ + [161] = {0xE77934A4U, 0x00000002U}, /* SEC_MODID[161]:PWM8*/ + [162] = {0xE77934A8U, 0x00000002U}, /* SEC_MODID[162]:PWM9*/ + [163] = {0xE77934ACU, 0x00000002U}, /* SEC_MODID[163]:TPU0*/ + [164] = {0xFE673400U, 0x00000002U}, /* SEC_MODID[164]:ARVC10*/ + [165] = {0xFE673404U, 0x00000002U}, /* SEC_MODID[165]:ARVC11*/ + [166] = {0xFE673408U, 0x00000002U}, /* SEC_MODID[166]:ARVC12*/ + [167] = {0xFE67340CU, 0x00000002U}, /* SEC_MODID[167]:ARVC13*/ + [168] = {0xFE673410U, 0x00000002U}, /* SEC_MODID[168]:ARVC14*/ + [169] = {0xFE673414U, 0x00000002U}, /* SEC_MODID[169]:ARVC15*/ + [170] = {0xFE673418U, 0x00000002U}, /* SEC_MODID[170]:ARVC16*/ + [171] = {0xFE67341CU, 0x00000002U}, /* SEC_MODID[171]:ARVC17*/ + [172] = {0xFE673420U, 0x00000002U}, /* SEC_MODID[172]:ARVC18*/ + [173] = {0xFE673424U, 0x00000002U}, /* SEC_MODID[173]:ECMVC1*/ + [174] = {0xFE673428U, 0x00000002U}, /* SEC_MODID[174]:FCPCS*/ + [175] = {0xFE67342CU, 0x00000002U}, /* SEC_MODID[175]:VCP4LC*/ + [176] = {0xFE673430U, 0x00000002U}, /* SEC_MODID[176]:VCP4LV*/ + [177] = {0xFEBD3400U, 0x00000002U}, /* SEC_MODID[177]:ARVI40*/ + [178] = {0xFEBD3404U, 0x00000002U}, /* SEC_MODID[178]:ARVI41*/ + [179] = {0xFEBD3408U, 0x00000002U}, /* SEC_MODID[179]:ARVI42*/ + [180] = {0xFEBD340CU, 0x00000002U}, /* SEC_MODID[180]:ARVI43*/ + [181] = {0xFEBD3410U, 0x00000002U}, /* SEC_MODID[181]:ARVI44*/ + [182] = {0xFEBD3414U, 0x00000002U}, /* SEC_MODID[182]:ARVI45*/ + [183] = {0xFEBD3418U, 0x00000002U}, /* SEC_MODID[183]:ARVI46*/ + [184] = {0xFEBD341CU, 0x00000002U}, /* SEC_MODID[184]:ARVI47*/ + [185] = {0xFEBD3420U, 0x00000002U}, /* SEC_MODID[185]:ARVI48*/ + [186] = {0xFEBD3424U, 0x00000002U}, /* SEC_MODID[186]:DIS0*/ + [187] = {0xFEBD342CU, 0x00000002U}, /* SEC_MODID[187]:DSC*/ + [188] = {0xFEBD3430U, 0x00000002U}, /* SEC_MODID[188]:ECMVIO2*/ + [189] = {0xFEBD3434U, 0x00000002U}, /* SEC_MODID[189]:FCPVD0*/ + [190] = {0xFEBD3438U, 0x00000002U}, /* SEC_MODID[190]:FCPVD1*/ + [191] = {0xFEBD343CU, 0x00000002U}, /* SEC_MODID[191]:VSPD0*/ + [192] = {0xFEBD3440U, 0x00000002U}, /* SEC_MODID[192]:VSPD1*/ + [193] = {0xE6583400U, 0x00000002U}, /* SEC_MODID[193]:CKMHSC*/ + [194] = {0xE6583404U, 0x00000002U}, /* SEC_MODID[194]:AXIPCI001*/ + [195] = {0xE6583408U, 0x00000002U}, /* SEC_MODID[195]:AXIPCI002*/ + [196] = {0xE658340CU, 0x00000002U}, /* SEC_MODID[196]:AXIPCI003*/ + [197] = {0xE6583414U, 0x00000002U}, /* SEC_MODID[197]:AXIPCI005*/ + [198] = {0xE6583418U, 0x00000002U}, /* SEC_MODID[198]:AXIPCI006*/ + [199] = {0xE658341CU, 0x00000002U}, /* SEC_MODID[199]:AXIPCI007*/ + [200] = {0xE6583420U, 0x00000002U}, /* SEC_MODID[200]:AXIPCI008*/ + [201] = {0xE6583424U, 0x00000002U}, /* SEC_MODID[201]:AXIPCI009*/ + [202] = {0xE6583428U, 0x00000002U}, /* SEC_MODID[202]:AXIPCI010*/ + [203] = {0xE658342CU, 0x00000002U}, /* SEC_MODID[203]:AXIPCI011*/ + [204] = {0xE6583430U, 0x00000002U}, /* SEC_MODID[204]:AXIPCI012*/ + [205] = {0xE6583434U, 0x00000002U}, /* SEC_MODID[205]:AXIPCI013*/ + [206] = {0xE6583438U, 0x00000002U}, /* SEC_MODID[206]:AXIPCI014*/ + [207] = {0xE658343CU, 0x00000002U}, /* SEC_MODID[207]:AXIPCI015*/ + [208] = {0xE6583440U, 0x00000002U}, /* SEC_MODID[208]:AXIPCI100*/ + [209] = {0xE6583444U, 0x00000002U}, /* SEC_MODID[209]:AXIPCI101*/ + [210] = {0xE6583448U, 0x00000002U}, /* SEC_MODID[210]:AXIPCI102*/ + [211] = {0xE658344CU, 0x00000002U}, /* SEC_MODID[211]:AXIPCI103*/ + [212] = {0xE6583450U, 0x00000002U}, /* SEC_MODID[212]:AXIPCI104*/ + [213] = {0xE6583454U, 0x00000002U}, /* SEC_MODID[213]:AXIPCI105*/ + [214] = {0xE6583458U, 0x00000002U}, /* SEC_MODID[214]:AXIPCI106*/ + [215] = {0xE658345CU, 0x00000002U}, /* SEC_MODID[215]:AXIPCI107*/ + [216] = {0xE6583460U, 0x00000002U}, /* SEC_MODID[216]:AXIPCI108*/ + [217] = {0xE6583464U, 0x00000002U}, /* SEC_MODID[217]:AXIPCI109*/ + [218] = {0xE6583468U, 0x00000002U}, /* SEC_MODID[218]:AXIPCI110*/ + [219] = {0xE658346CU, 0x00000002U}, /* SEC_MODID[219]:AXIPCI111*/ + [220] = {0xE6583470U, 0x00000002U}, /* SEC_MODID[220]:AXIPCI112*/ + [221] = {0xE6583474U, 0x00000002U}, /* SEC_MODID[221]:AXIPCI113*/ + [222] = {0xE6583478U, 0x00000002U}, /* SEC_MODID[222]:AXIPCI114*/ + [223] = {0xE658347CU, 0x00000002U}, /* SEC_MODID[223]:AXIPCI115*/ + [224] = {0xE6583484U, 0x00000002U}, /* SEC_MODID[224]:GPTP*/ + [225] = {0xE6583488U, 0x00000002U}, /* SEC_MODID[225]:IPMMUHC00*/ + [226] = {0xE65834F0U, 0x00000002U}, /* SEC_MODID[226]:TSN0*/ + [227] = {0xE65834F4U, 0x00000002U}, /* SEC_MODID[227]:AXIPCI000*/ + [228] = {0xE65834F8U, 0x00000002U}, /* SEC_MODID[228]:AXIPCI004*/ + [229] = {0xE65834FCU, 0x00000002U}, /* SEC_MODID[229]:IPMMUHC01*/ + [230] = {0xE6583500U, 0x00000002U}, /* SEC_MODID[230]:AVB0*/ + [231] = {0xE6583504U, 0x00000002U}, /* SEC_MODID[231]:AVB1*/ + [232] = {0xE6583508U, 0x00000002U}, /* SEC_MODID[232]:AVB2*/ + [233] = {0xE658350CU, 0x00000002U}, /* SEC_MODID[233]:IPMMUHC10*/ + [234] = {0xE6583510U, 0x00000002U}, /* SEC_MODID[234]:IPMMUHC11*/ + [235] = {0xE6583514U, 0x00000002U}, /* SEC_MODID[235]:IPMMUHC12*/ + [236] = {0xE6583518U, 0x00000002U}, /* SEC_MODID[236]:IPMMUHC13*/ + [237] = {0xE658351CU, 0x00000002U}, /* SEC_MODID[237]:PPHY0*/ + [238] = {0xE6583520U, 0x00000002U}, /* SEC_MODID[238]:PPHY1*/ + [239] = {0xE6583524U, 0x00000002U}, /* SEC_MODID[239]:IPMMUHC14*/ + [240] = {0xE6583528U, 0x00000002U}, /* SEC_MODID[240]:IPMMUHC15*/ + [241] = {0xE658352CU, 0x00000002U}, /* SEC_MODID[241]:FBAHSC*/ + [242] = {0xE6583530U, 0x00000002U}, /* SEC_MODID[242]:IPMMUHC02*/ + [243] = {0xE6583538U, 0x00000002U}, /* SEC_MODID[243]:ECMHSC*/ + [244] = {0xE658353CU, 0x00000002U}, /* SEC_MODID[244]:ARHC0*/ + [245] = {0xE6583540U, 0x00000002U}, /* SEC_MODID[245]:ARHC1*/ + [246] = {0xE6583544U, 0x00000002U}, /* SEC_MODID[246]:ARHC2*/ + [247] = {0xE6583548U, 0x00000002U}, /* SEC_MODID[247]:ARHC3*/ + [248] = {0xE658354CU, 0x00000002U}, /* SEC_MODID[248]:ARHC4*/ + [249] = {0xE6583550U, 0x00000002U}, /* SEC_MODID[249]:ARHC5*/ + [250] = {0xE6583554U, 0x00000002U}, /* SEC_MODID[250]:ARHC6*/ + [251] = {0xE6583558U, 0x00000002U}, /* SEC_MODID[251]:ARHC7*/ + [252] = {0xE658355CU, 0x00000002U}, /* SEC_MODID[252]:ARHC8*/ + [253] = {0xE6583560U, 0x00000002U}, /* SEC_MODID[253]:IPMMUHC03*/ + [254] = {0xE6583564U, 0x00000002U}, /* SEC_MODID[254]:IPMMUHC04*/ + [255] = {0xE6583568U, 0x00000002U}, /* SEC_MODID[255]:IPMMUHC05*/ + [256] = {0xE658356CU, 0x00000002U}, /* SEC_MODID[256]:IPMMUHC06*/ + [257] = {0xE6583570U, 0x00000002U}, /* SEC_MODID[257]:IPMMUHC07*/ + [258] = {0xE6583574U, 0x00000002U}, /* SEC_MODID[258]:IPMMUHC08*/ + [259] = {0xE6583578U, 0x00000002U}, /* SEC_MODID[259]:IPMMUHC09*/ + [260] = {0xFF883400U, 0x00000002U}, /* SEC_MODID[260]:ARIMP00*/ + [261] = {0xFF883404U, 0x00000002U}, /* SEC_MODID[261]:ARIMP01*/ + [262] = {0xFF883408U, 0x00000002U}, /* SEC_MODID[262]:ARIMP02*/ + [263] = {0xFF88340CU, 0x00000002U}, /* SEC_MODID[263]:ARIMP03*/ + [264] = {0xFF883410U, 0x00000002U}, /* SEC_MODID[264]:ARIMP04*/ + [265] = {0xFF883414U, 0x00000002U}, /* SEC_MODID[265]:AXIFBABUSIR0*/ + [266] = {0xFF883418U, 0x00000002U}, /* SEC_MODID[266]:AXIFBABUSIR1*/ + [267] = {0xFF88341CU, 0x00000002U}, /* SEC_MODID[267]:AXIFBABUSIR2*/ + [268] = {0xFF883420U, 0x00000002U}, /* SEC_MODID[268]:AXIFBABUSIR3*/ + [269] = {0xFF883424U, 0x00000002U}, /* SEC_MODID[269]:AXIFBABUSIR4*/ + [270] = {0xFF883428U, 0x00000002U}, /* SEC_MODID[270]:AXIIMP0*/ + [271] = {0xFF88342CU, 0x00000002U}, /* SEC_MODID[271]:CKMCNR*/ + [272] = {0xFF883430U, 0x00000002U}, /* SEC_MODID[272]:CKMDSP*/ + [273] = {0xFF883434U, 0x00000002U}, /* SEC_MODID[273]:ARIMP05*/ + [274] = {0xFF883438U, 0x00000002U}, /* SEC_MODID[274]:ARIMP06*/ + [275] = {0xFF88343CU, 0x00000002U}, /* SEC_MODID[275]:ARIMP07*/ + [276] = {0xFF883440U, 0x00000002U}, /* SEC_MODID[276]:ARIMP08*/ + [277] = {0xFF883444U, 0x00000002U}, /* SEC_MODID[277]:CKMIR*/ + [278] = {0xFF883448U, 0x00000002U}, /* SEC_MODID[278]:ECMIR*/ + [279] = {0xFF88344CU, 0x00000002U}, /* SEC_MODID[279]:DSPPS*/ + [280] = {0xFF883450U, 0x00000002U}, /* SEC_MODID[280]:IPMMUIR1*/ + [281] = {0xFF883454U, 0x00000002U}, /* SEC_MODID[281]:IPMMUIR0*/ + [282] = {0xFF883458U, 0x00000002U}, /* SEC_MODID[282]:IPMMUIR10*/ + [283] = {0xFF88345CU, 0x00000002U}, /* SEC_MODID[283]:IPMMUIR11*/ + [284] = {0xFF883460U, 0x00000002U}, /* SEC_MODID[284]:IPMMUIR12*/ + [285] = {0xFF883464U, 0x00000002U}, /* SEC_MODID[285]:IPMMUIR13*/ + [286] = {0xFF883468U, 0x00000002U}, /* SEC_MODID[286]:IPMMUIR14*/ + [287] = {0xFF88346CU, 0x00000002U}, /* SEC_MODID[287]:IPMMUIR15*/ + [288] = {0xFF883470U, 0x00000002U}, /* SEC_MODID[288]:IPMMUIR2*/ + [289] = {0xFF883474U, 0x00000002U}, /* SEC_MODID[289]:IPMMUIR3*/ + [290] = {0xFF883478U, 0x00000002U}, /* SEC_MODID[290]:IPMMUIR4*/ + [291] = {0xFF88347CU, 0x00000002U}, /* SEC_MODID[291]:IPMMUIR5*/ + [292] = {0xFF883480U, 0x00000002U}, /* SEC_MODID[292]:IPMMUIR6*/ + [293] = {0xFF883484U, 0x00000002U}, /* SEC_MODID[293]:IPMMUIR7*/ + [294] = {0xFF883488U, 0x00000002U}, /* SEC_MODID[294]:IPMMUIR8*/ + [295] = {0xFF88348CU, 0x00000002U}, /* SEC_MODID[295]:IPMMUIR9*/ + [296] = {0xFD813400U, 0x00000002U}, /* SEC_MODID[296]:ARPV0*/ + [297] = {0xFD813404U, 0x00000002U}, /* SEC_MODID[297]:ARPV1*/ + [298] = {0xFD813408U, 0x00000002U}, /* SEC_MODID[298]:AXIRGXS*/ + [299] = {0xFD81340CU, 0x00000002U}, /* SEC_MODID[299]:ARPV2*/ + [300] = {0xFD813410U, 0x00000002U}, /* SEC_MODID[300]:ARPV3*/ + [301] = {0xFD813414U, 0x00000002U}, /* SEC_MODID[301]:ARPV4*/ + [302] = {0xFD813418U, 0x00000002U}, /* SEC_MODID[302]:ARPV5*/ + [303] = {0xFD81341CU, 0x00000002U}, /* SEC_MODID[303]:ARPV6*/ + [304] = {0xFD813420U, 0x00000002U}, /* SEC_MODID[304]:ARPV7*/ + [305] = {0xFD813424U, 0x00000002U}, /* SEC_MODID[305]:ARPV8*/ + [306] = {0xFD813428U, 0x00000002U}, /* SEC_MODID[306]:CKM3DG*/ + [307] = {0xFD81342CU, 0x00000002U}, /* SEC_MODID[307]:ECM3DG*/ + [308] = {0xFD813430U, 0x00000002U}, /* SEC_MODID[308]:FBAPVC*/ + [309] = {0xFD813434U, 0x00000002U}, /* SEC_MODID[309]:FBAPVD0*/ + [310] = {0xFD813438U, 0x00000002U}, /* SEC_MODID[310]:FBAPVD1*/ + [311] = {0xFD81343CU, 0x00000002U}, /* SEC_MODID[311]:FBAPVD2*/ + [312] = {0xFD813440U, 0x00000002U}, /* SEC_MODID[312]:FBAPVE*/ + [313] = {0xFD813444U, 0x00000002U}, /* SEC_MODID[313]:IPMMUPV000*/ + [314] = {0xFD813448U, 0x00000002U}, /* SEC_MODID[314]:IPMMUPV001*/ + [315] = {0xFD81344CU, 0x00000002U}, /* SEC_MODID[315]:IPMMUPV010*/ + [316] = {0xFD813450U, 0x00000002U}, /* SEC_MODID[316]:IPMMUPV011*/ + [317] = {0xFD813454U, 0x00000002U}, /* SEC_MODID[317]:IPMMUPV012*/ + [318] = {0xFD813458U, 0x00000002U}, /* SEC_MODID[318]:IPMMUPV013*/ + [319] = {0xFD81345CU, 0x00000002U}, /* SEC_MODID[319]:IPMMUPV014*/ + [320] = {0xFD813460U, 0x00000002U}, /* SEC_MODID[320]:IPMMUPV015*/ + [321] = {0xFD813464U, 0x00000002U}, /* SEC_MODID[321]:IPMMUPV002*/ + [322] = {0xFD813468U, 0x00000002U}, /* SEC_MODID[322]:IPMMUPV003*/ + [323] = {0xFD81346CU, 0x00000002U}, /* SEC_MODID[323]:IPMMUPV004*/ + [324] = {0xFD813470U, 0x00000002U}, /* SEC_MODID[324]:IPMMUPV005*/ + [325] = {0xFD813474U, 0x00000002U}, /* SEC_MODID[325]:IPMMUPV006*/ + [326] = {0xFD813478U, 0x00000002U}, /* SEC_MODID[326]:IPMMUPV007*/ + [327] = {0xFD81347CU, 0x00000002U}, /* SEC_MODID[327]:IPMMUPV008*/ + [328] = {0xFD813480U, 0x00000002U}, /* SEC_MODID[328]:IPMMUPV009*/ + [329] = {0xE6623400U, 0x00000002U}, /* SEC_MODID[329]:ARRC0*/ + [330] = {0xE6623404U, 0x00000002U}, /* SEC_MODID[330]:ARRC1*/ + [331] = {0xE6623408U, 0x00000002U}, /* SEC_MODID[331]:ARRC2*/ + [332] = {0xE662340CU, 0x00000002U}, /* SEC_MODID[332]:ARRC3*/ + [333] = {0xE6623410U, 0x00000002U}, /* SEC_MODID[333]:ARRC4*/ + [334] = {0xE6623414U, 0x00000002U}, /* SEC_MODID[334]:ARRC5*/ + [335] = {0xE6623418U, 0x00000002U}, /* SEC_MODID[335]:ARRC6*/ + [336] = {0xE662341CU, 0x00000002U}, /* SEC_MODID[336]:ARRC7*/ + [337] = {0xE6623420U, 0x00000002U}, /* SEC_MODID[337]:ARRC8*/ + [338] = {0xE6623424U, 0x00000000U}, /* SEC_MODID[338]:CR0*/ + [339] = {0xE6623428U, 0x00000002U}, /* SEC_MODID[339]:ICUMX*/ + [340] = {0xE662342CU, 0x00000002U}, /* SEC_MODID[340]:ECMRC*/ + [341] = {0xFFC33400U, 0x00000002U}, /* SEC_MODID[341]:DMAWCRC0*/ + [342] = {0xFFC33404U, 0x00000002U}, /* SEC_MODID[342]:DMAWCRC1*/ + [343] = {0xFFC33408U, 0x00000002U}, /* SEC_MODID[343]:DMAWCRC2*/ + [344] = {0xFFC3340CU, 0x00000002U}, /* SEC_MODID[344]:DMAWCRC3*/ + [345] = {0xFFC43400U, 0x00000002U}, /* SEC_MODID[345]:ARMREG00*/ + [346] = {0xFFC43404U, 0x00000002U}, /* SEC_MODID[346]:ARMREG01*/ + [347] = {0xFFC43408U, 0x00000002U}, /* SEC_MODID[347]:ARMREG10*/ + [348] = {0xFFC4340CU, 0x00000002U}, /* SEC_MODID[348]:ARMREG11*/ + [349] = {0xFFC43410U, 0x00000002U}, /* SEC_MODID[349]:ARMREG12*/ + [350] = {0xFFC43414U, 0x00000000U}, /* SEC_MODID[350]:ARMREG13*/ + [351] = {0xFFC43418U, 0x00000000U}, /* SEC_MODID[351]:ARMREG14*/ + [352] = {0xFFC4341CU, 0x00000002U}, /* SEC_MODID[352]:AXICR52SS0*/ + [353] = {0xFFC43420U, 0x00000002U}, /* SEC_MODID[353]:AXICSD0*/ + [354] = {0xFFC43424U, 0x00000002U}, /* SEC_MODID[354]:AXIINTAP0*/ + [355] = {0xFFC43428U, 0x00000002U}, /* SEC_MODID[355]:AXIINTAP1*/ + [356] = {0xFFC4342CU, 0x00000002U}, /* SEC_MODID[356]:AXISECROM*/ + [357] = {0xFFC43430U, 0x00000002U}, /* SEC_MODID[357]:AXISYSRAM0*/ + [358] = {0xFFC43434U, 0x00000002U}, /* SEC_MODID[358]:AXISYSRAM1*/ + [359] = {0xFFC43438U, 0x00000002U}, /* SEC_MODID[359]:ARGREG15*/ + [360] = {0xFFC4343CU, 0x00000002U}, /* SEC_MODID[360]:ARMREG2*/ + [361] = {0xFFC43440U, 0x00000002U}, /* SEC_MODID[361]:ARMREG3*/ + [362] = {0xFFC43444U, 0x00000002U}, /* SEC_MODID[362]:ARMREG4*/ + [363] = {0xFFC43448U, 0x00000002U}, /* SEC_MODID[363]:ARMREG5*/ + [364] = {0xFFC4344CU, 0x00000002U}, /* SEC_MODID[364]:ARMREG6*/ + [365] = {0xFFC43450U, 0x00000002U}, /* SEC_MODID[365]:ARMREG7*/ + [366] = {0xFFC43454U, 0x00000000U}, /* SEC_MODID[366]:ARMREG8*/ + [367] = {0xFFC43458U, 0x00000000U}, /* SEC_MODID[367]:ARMREG9*/ + [368] = {0xFFC4345CU, 0x00000002U}, /* SEC_MODID[368]:ARRD0*/ + [369] = {0xFFC43460U, 0x00000002U}, /* SEC_MODID[369]:ARRD1*/ + [370] = {0xFFC43464U, 0x00000002U}, /* SEC_MODID[370]:ARRD2*/ + [371] = {0xFFC43468U, 0x00000002U}, /* SEC_MODID[371]:ARRD3*/ + [372] = {0xFFC4346CU, 0x00000002U}, /* SEC_MODID[372]:ARRD4*/ + [373] = {0xFFC43470U, 0x00000002U}, /* SEC_MODID[373]:ARRD5*/ + [374] = {0xFFC43474U, 0x00000002U}, /* SEC_MODID[374]:ARRD6*/ + [375] = {0xFFC43478U, 0x00000002U}, /* SEC_MODID[375]:ARRD7*/ + [376] = {0xFFC4347CU, 0x00000002U}, /* SEC_MODID[376]:ARRD8*/ + [377] = {0xFFC43480U, 0x00000002U}, /* SEC_MODID[377]:ARRT0*/ + [378] = {0xFFC43484U, 0x00000002U}, /* SEC_MODID[378]:ARRT1*/ + [379] = {0xFFC43488U, 0x00000002U}, /* SEC_MODID[379]:ARRT2*/ + [380] = {0xFFC4348CU, 0x00000002U}, /* SEC_MODID[380]:ARRT3*/ + [381] = {0xFFC43490U, 0x00000002U}, /* SEC_MODID[381]:ARRT4*/ + [382] = {0xFFC43494U, 0x00000002U}, /* SEC_MODID[382]:ARRT5*/ + [383] = {0xFFC43498U, 0x00000002U}, /* SEC_MODID[383]:ARRT6*/ + [384] = {0xFFC4349CU, 0x00000002U}, /* SEC_MODID[384]:ARRT7*/ + [385] = {0xFFC434A0U, 0x00000002U}, /* SEC_MODID[385]:ARRT8*/ + [386] = {0xFFC434A4U, 0x00000002U}, /* SEC_MODID[386]:CKMRT*/ + [387] = {0xFFC434A8U, 0x00000002U}, /* SEC_MODID[387]:CRC0*/ + [388] = {0xFFC434ACU, 0x00000002U}, /* SEC_MODID[388]:CRC1*/ + [389] = {0xFFC434B0U, 0x00000002U}, /* SEC_MODID[389]:CRC2*/ + [390] = {0xFFC434B4U, 0x00000002U}, /* SEC_MODID[390]:CRC3*/ + [391] = {0xFFC434B8U, 0x00000002U}, /* SEC_MODID[391]:CSD*/ + [392] = {0xFFC434BCU, 0x00000002U}, /* SEC_MODID[392]:ECM*/ + [393] = {0xFFC434C0U, 0x00000002U}, /* SEC_MODID[393]:ECMRT*/ + [394] = {0xFFC434C4U, 0x00000002U}, /* SEC_MODID[394]:FBACR52*/ + [395] = {0xFFC434C8U, 0x00000002U}, /* SEC_MODID[395]:FBART*/ + [396] = {0xFFC434CCU, 0x00000002U}, /* SEC_MODID[396]:INTTP*/ + [397] = {0xFFC434D0U, 0x00000002U}, /* SEC_MODID[397]:IPMMURT000*/ + [398] = {0xFFC434D4U, 0x00000002U}, /* SEC_MODID[398]:IPMMURT100*/ + [399] = {0xFFC434D8U, 0x00000002U}, /* SEC_MODID[399]:KCRC4*/ + [400] = {0xFFC434DCU, 0x00000002U}, /* SEC_MODID[400]:KCRC5*/ + [401] = {0xFFC434E0U, 0x00000002U}, /* SEC_MODID[401]:KCRC6*/ + [402] = {0xFFC434E4U, 0x00000002U}, /* SEC_MODID[402]:KCRC7*/ + [403] = {0xFFC434E8U, 0x00000002U}, /* SEC_MODID[403]:MFI00*/ + [404] = {0xFFC434ECU, 0x00000002U}, /* SEC_MODID[404]:MFI01*/ + [405] = {0xFFC434F0U, 0x00000002U}, /* SEC_MODID[405]:MFI10*/ + [406] = {0xFFC434F4U, 0x00000002U}, /* SEC_MODID[406]:MFI02*/ + [407] = {0xFFC434F8U, 0x00000002U}, /* SEC_MODID[407]:MFI03*/ + [408] = {0xFFC434FCU, 0x00000002U}, /* SEC_MODID[408]:MFI04*/ + [409] = {0xFFC43500U, 0x00000002U}, /* SEC_MODID[409]:MFI05*/ + [410] = {0xFFC43504U, 0x00000002U}, /* SEC_MODID[410]:MFI06*/ + [411] = {0xFFC43508U, 0x00000002U}, /* SEC_MODID[411]:MFI07*/ + [412] = {0xFFC4350CU, 0x00000002U}, /* SEC_MODID[412]:MFI08*/ + [413] = {0xFFC43510U, 0x00000002U}, /* SEC_MODID[413]:MFI09*/ + [414] = {0xFFC43514U, 0x00000002U}, /* SEC_MODID[414]:MFI15*/ + [415] = {0xFFC43518U, 0x00000002U}, /* SEC_MODID[415]:CKMCR52*/ + [416] = {0xFFC4351CU, 0x00000002U}, /* SEC_MODID[416]:RTDM0P*/ + [417] = {0xFFC43520U, 0x00000002U}, /* SEC_MODID[417]:ECMRD*/ + [418] = {0xFFC43524U, 0x00000002U}, /* SEC_MODID[418]:RTDM1P*/ + [419] = {0xFFC4352CU, 0x00000002U}, /* SEC_MODID[419]:RTDM2P*/ + [420] = {0xFFC43530U, 0x00000002U}, /* SEC_MODID[420]:SYSRAM10*/ + [421] = {0xFFC43534U, 0x00000002U}, /* SEC_MODID[421]:RTDM3P*/ + [422] = {0xFFC43538U, 0x00000000U}, /* SEC_MODID[422]:SYSRAM00*/ + [423] = {0xFFC4353CU, 0x00000002U}, /* SEC_MODID[423]:TSIPL0*/ + [424] = {0xFFC43540U, 0x00000002U}, /* SEC_MODID[424]:TSIPL1*/ + [425] = {0xFFC43544U, 0x00000002U}, /* SEC_MODID[425]:TSIPL2*/ + [426] = {0xFFC43548U, 0x00000002U}, /* SEC_MODID[426]:TSIPL3*/ + [427] = {0xFFC4354CU, 0x00000002U}, /* SEC_MODID[427]:TSIPL4*/ + [428] = {0xFFC43550U, 0x00000002U}, /* SEC_MODID[428]:TSIPL5*/ + [429] = {0xFFC43554U, 0x00000002U}, /* SEC_MODID[429]:TSIPL6*/ + [430] = {0xFFC43558U, 0x00000002U}, /* SEC_MODID[430]:TSIPL7*/ + [431] = {0xFFC4355CU, 0x00000002U}, /* SEC_MODID[431]:WCRC0*/ + [432] = {0xFFC43560U, 0x00000002U}, /* SEC_MODID[432]:WCRC1*/ + [433] = {0xFFC43564U, 0x00000002U}, /* SEC_MODID[433]:WCRC2*/ + [434] = {0xFFC43568U, 0x00000002U}, /* SEC_MODID[434]:WCRC3*/ + [435] = {0xFFC43580U, 0x00000002U}, /* SEC_MODID[435]:MFI11*/ + [436] = {0xFFC43584U, 0x00000002U}, /* SEC_MODID[436]:MFI12*/ + [437] = {0xFFC43588U, 0x00000002U}, /* SEC_MODID[437]:MFI13*/ + [438] = {0xFFC4358CU, 0x00000002U}, /* SEC_MODID[438]:MFI14*/ + [439] = {0xFFC43590U, 0x00000002U}, /* SEC_MODID[439]:IPMMURT001*/ + [440] = {0xFFC43594U, 0x00000002U}, /* SEC_MODID[440]:IPMMURT010*/ + [441] = {0xFFC43598U, 0x00000002U}, /* SEC_MODID[441]:IPMMURT011*/ + [442] = {0xFFC4359CU, 0x00000002U}, /* SEC_MODID[442]:IPMMURT012*/ + [443] = {0xFFC435A0U, 0x00000002U}, /* SEC_MODID[443]:IPMMURT013*/ + [444] = {0xFFC435A4U, 0x00000002U}, /* SEC_MODID[444]:IPMMURT014*/ + [445] = {0xFFC435A8U, 0x00000002U}, /* SEC_MODID[445]:IPMMURT015*/ + [446] = {0xFFC435ACU, 0x00000002U}, /* SEC_MODID[446]:IPMMURT002*/ + [447] = {0xFFC435B0U, 0x00000002U}, /* SEC_MODID[447]:IPMMURT003*/ + [448] = {0xFFC435B4U, 0x00000002U}, /* SEC_MODID[448]:IPMMURT004*/ + [449] = {0xFFC435B8U, 0x00000002U}, /* SEC_MODID[449]:IPMMURT005*/ + [450] = {0xFFC435BCU, 0x00000002U}, /* SEC_MODID[450]:IPMMURT006*/ + [451] = {0xFFC435C0U, 0x00000002U}, /* SEC_MODID[451]:IPMMURT007*/ + [452] = {0xFFC435C4U, 0x00000002U}, /* SEC_MODID[452]:IPMMURT008*/ + [453] = {0xFFC435C8U, 0x00000002U}, /* SEC_MODID[453]:IPMMURT009*/ + [454] = {0xFFC435CCU, 0x00000002U}, /* SEC_MODID[454]:IPKMURT101*/ + [455] = {0xFFC435D0U, 0x00000002U}, /* SEC_MODID[455]:IPMMURT110*/ + [456] = {0xFFC435D4U, 0x00000002U}, /* SEC_MODID[456]:IPMMURT111*/ + [457] = {0xFFC435D8U, 0x00000002U}, /* SEC_MODID[457]:IPMMURT112*/ + [458] = {0xFFC435DCU, 0x00000002U}, /* SEC_MODID[458]:IPMMURT113*/ + [459] = {0xFFC435E0U, 0x00000002U}, /* SEC_MODID[459]:IPMMURT114*/ + [460] = {0xFFC435E4U, 0x00000002U}, /* SEC_MODID[460]:IPMMURT115*/ + [461] = {0xFFC435E8U, 0x00000002U}, /* SEC_MODID[461]:IPMMURT102*/ + [462] = {0xFFC435ECU, 0x00000002U}, /* SEC_MODID[462]:IPMMURT103*/ + [463] = {0xFFC435F0U, 0x00000002U}, /* SEC_MODID[463]:IPMMURT104*/ + [464] = {0xFFC435F4U, 0x00000002U}, /* SEC_MODID[464]:IPMMURT105*/ + [465] = {0xFFC435F8U, 0x00000002U}, /* SEC_MODID[465]:IPMMURT106*/ + [466] = {0xFFC435FCU, 0x00000002U}, /* SEC_MODID[466]:IPMMURT107*/ + [467] = {0xFFC43600U, 0x00000002U}, /* SEC_MODID[467]:RTDM000*/ + [468] = {0xFFC43604U, 0x00000002U}, /* SEC_MODID[468]:RTDM001*/ + [469] = {0xFFC43608U, 0x00000002U}, /* SEC_MODID[469]:RTDM010*/ + [470] = {0xFFC4360CU, 0x00000002U}, /* SEC_MODID[470]:RTDM011*/ + [471] = {0xFFC43610U, 0x00000002U}, /* SEC_MODID[471]:RTDM012*/ + [472] = {0xFFC43614U, 0x00000002U}, /* SEC_MODID[472]:RTDM013*/ + [473] = {0xFFC43618U, 0x00000002U}, /* SEC_MODID[473]:RTDM014*/ + [474] = {0xFFC4361CU, 0x00000002U}, /* SEC_MODID[474]:RTDM015*/ + [475] = {0xFFC43620U, 0x00000002U}, /* SEC_MODID[475]:RTDM002*/ + [476] = {0xFFC43624U, 0x00000002U}, /* SEC_MODID[476]:RTDM003*/ + [477] = {0xFFC43628U, 0x00000002U}, /* SEC_MODID[477]:RTDM004*/ + [478] = {0xFFC4362CU, 0x00000002U}, /* SEC_MODID[478]:RTDM005*/ + [479] = {0xFFC43630U, 0x00000002U}, /* SEC_MODID[479]:RTDM006*/ + [480] = {0xFFC43634U, 0x00000002U}, /* SEC_MODID[480]:RTDM007*/ + [481] = {0xFFC43638U, 0x00000002U}, /* SEC_MODID[481]:RTDM008*/ + [482] = {0xFFC4363CU, 0x00000002U}, /* SEC_MODID[482]:RTDM009*/ + [483] = {0xFFC43640U, 0x00000002U}, /* SEC_MODID[483]:RTDM100*/ + [484] = {0xFFC43644U, 0x00000002U}, /* SEC_MODID[484]:RTDM101*/ + [485] = {0xFFC43648U, 0x00000002U}, /* SEC_MODID[485]:RTDM110*/ + [486] = {0xFFC4364CU, 0x00000002U}, /* SEC_MODID[486]:RTDM111*/ + [487] = {0xFFC43650U, 0x00000002U}, /* SEC_MODID[487]:RTDM112*/ + [488] = {0xFFC43654U, 0x00000002U}, /* SEC_MODID[488]:RTDM113*/ + [489] = {0xFFC43658U, 0x00000002U}, /* SEC_MODID[489]:RTDM114*/ + [490] = {0xFFC4365CU, 0x00000002U}, /* SEC_MODID[490]:RTDM115*/ + [491] = {0xFFC43660U, 0x00000002U}, /* SEC_MODID[491]:RTDM102*/ + [492] = {0xFFC43664U, 0x00000002U}, /* SEC_MODID[492]:RTDM103*/ + [493] = {0xFFC43668U, 0x00000002U}, /* SEC_MODID[493]:RTDM104*/ + [494] = {0xFFC4366CU, 0x00000002U}, /* SEC_MODID[494]:RTDM105*/ + [495] = {0xFFC43670U, 0x00000002U}, /* SEC_MODID[495]:RTDM106*/ + [496] = {0xFFC43674U, 0x00000002U}, /* SEC_MODID[496]:RTDM107*/ + [497] = {0xFFC43678U, 0x00000002U}, /* SEC_MODID[497]:RTDM108*/ + [498] = {0xFFC4367CU, 0x00000002U}, /* SEC_MODID[498]:RTDM109*/ + [499] = {0xFFC43680U, 0x00000002U}, /* SEC_MODID[499]:RTDM200*/ + [500] = {0xFFC43684U, 0x00000002U}, /* SEC_MODID[500]:RTDM201*/ + [501] = {0xFFC43688U, 0x00000002U}, /* SEC_MODID[501]:RTDM210*/ + [502] = {0xFFC4368CU, 0x00000002U}, /* SEC_MODID[502]:RTDM211*/ + [503] = {0xFFC43690U, 0x00000002U}, /* SEC_MODID[503]:RTDM212*/ + [504] = {0xFFC43694U, 0x00000002U}, /* SEC_MODID[504]:RTDM213*/ + [505] = {0xFFC43698U, 0x00000002U}, /* SEC_MODID[505]:RTDM214*/ + [506] = {0xFFC4369CU, 0x00000002U}, /* SEC_MODID[506]:RTDM215*/ + [507] = {0xFFC436A0U, 0x00000002U}, /* SEC_MODID[507]:RTDM202*/ + [508] = {0xFFC436A4U, 0x00000002U}, /* SEC_MODID[508]:RTDM203*/ + [509] = {0xFFC436A8U, 0x00000002U}, /* SEC_MODID[509]:RTDM204*/ + [510] = {0xFFC436ACU, 0x00000002U}, /* SEC_MODID[510]:RTDM205*/ + [511] = {0xFFC436B0U, 0x00000002U}, /* SEC_MODID[511]:RTDM206*/ + [512] = {0xFFC436B4U, 0x00000002U}, /* SEC_MODID[512]:RTDM207*/ + [513] = {0xFFC436B8U, 0x00000002U}, /* SEC_MODID[513]:RTDM208*/ + [514] = {0xFFC436BCU, 0x00000002U}, /* SEC_MODID[514]:RTDM209*/ + [515] = {0xFFC436C0U, 0x00000002U}, /* SEC_MODID[515]:RTDM300*/ + [516] = {0xFFC436C4U, 0x00000002U}, /* SEC_MODID[516]:RTDM301*/ + [517] = {0xFFC436C8U, 0x00000002U}, /* SEC_MODID[517]:RTDM310*/ + [518] = {0xFFC436CCU, 0x00000002U}, /* SEC_MODID[518]:RTDM311*/ + [519] = {0xFFC436D0U, 0x00000002U}, /* SEC_MODID[519]:RTDM312*/ + [520] = {0xFFC436D4U, 0x00000002U}, /* SEC_MODID[520]:RTDM313*/ + [521] = {0xFFC436D8U, 0x00000002U}, /* SEC_MODID[521]:RTDM314*/ + [522] = {0xFFC436DCU, 0x00000002U}, /* SEC_MODID[522]:RTDM315*/ + [523] = {0xFFC436E0U, 0x00000002U}, /* SEC_MODID[523]:RTDM302*/ + [524] = {0xFFC436E4U, 0x00000002U}, /* SEC_MODID[524]:RTDM303*/ + [525] = {0xFFC436E8U, 0x00000002U}, /* SEC_MODID[525]:RTDM304*/ + [526] = {0xFFC436ECU, 0x00000002U}, /* SEC_MODID[526]:RTDM305*/ + [527] = {0xFFC436F0U, 0x00000002U}, /* SEC_MODID[527]:RTDM306*/ + [528] = {0xFFC436F4U, 0x00000002U}, /* SEC_MODID[528]:RTDM307*/ + [529] = {0xFFC436F8U, 0x00000002U}, /* SEC_MODID[529]:RTDM308*/ + [530] = {0xFFC436FCU, 0x00000002U}, /* SEC_MODID[530]:RTDM309*/ + [531] = {0xFFC43700U, 0x00000002U}, /* SEC_MODID[531]:IPMMURT108*/ + [532] = {0xFFC43704U, 0x00000002U}, /* SEC_MODID[532]:IPMMURT109*/ + [533] = {0xFFC43708U, 0x00000000U}, /* SEC_MODID[533]:SYSRAM01*/ + [534] = {0xFFC4370CU, 0x00000002U}, /* SEC_MODID[534]:SYSRAM02*/ + [535] = {0xFFC43710U, 0x00000000U}, /* SEC_MODID[535]:SYSRAM03*/ + [536] = {0xFFC43714U, 0x00000000U}, /* SEC_MODID[536]:SYSRAM04*/ + [537] = {0xFFC43718U, 0x00000000U}, /* SEC_MODID[537]:SYSRAM05*/ + [538] = {0xFFC4371CU, 0x00000000U}, /* SEC_MODID[538]:SYSRAM06*/ + [539] = {0xFFC43720U, 0x00000002U}, /* SEC_MODID[539]:SYSRAM07*/ + [540] = {0xFFC43724U, 0x00000002U}, /* SEC_MODID[540]:SYSRAM11*/ + [541] = {0xFFC43728U, 0x00000002U}, /* SEC_MODID[541]:SYSRAM12*/ + [542] = {0xFFC4372CU, 0x00000002U}, /* SEC_MODID[542]:SYSRAM13*/ + [543] = {0xFFC43730U, 0x00000002U}, /* SEC_MODID[543]:SYSRAM14*/ + [544] = {0xFFC43734U, 0x00000002U}, /* SEC_MODID[544]:SYSRAM15*/ + [545] = {0xFFC43738U, 0x00000002U}, /* SEC_MODID[545]:SYSRAM16*/ + [546] = {0xFFC4373CU, 0x00000002U}, /* SEC_MODID[546]:SYSRAM17*/ + [547] = {0xFFC43760U, 0x00000002U}, /* SEC_MODID[547]:BKBUF*/ + [548] = {0xFFC43764U, 0x00000002U}, /* SEC_MODID[548]:AXICR52SS1*/ + [549] = {0xFFC43768U, 0x00000002U}, /* SEC_MODID[549]:AXICR52SS2*/ + [550] = {0xFF863400U, 0x00000002U}, /* SEC_MODID[550]:ARSC0*/ + [551] = {0xFF863404U, 0x00000002U}, /* SEC_MODID[551]:ARSC1*/ + [552] = {0xFF863408U, 0x00000002U}, /* SEC_MODID[552]:ARSC2*/ + [553] = {0xFF86340CU, 0x00000002U}, /* SEC_MODID[553]:ARSC3*/ + [554] = {0xFF863410U, 0x00000002U}, /* SEC_MODID[554]:ARSC4*/ + [555] = {0xFF863414U, 0x00000002U}, /* SEC_MODID[555]:ARSC5*/ + [556] = {0xFF863418U, 0x00000002U}, /* SEC_MODID[556]:ARSC6*/ + [557] = {0xFF86341CU, 0x00000002U}, /* SEC_MODID[557]:ARSC7*/ + [558] = {0xFF863420U, 0x00000002U}, /* SEC_MODID[558]:ARSC8*/ + [559] = {0xFF863424U, 0x00000002U}, /* SEC_MODID[559]:ARSTM0*/ + [560] = {0xFF863428U, 0x00000002U}, /* SEC_MODID[560]:ARSTM1*/ + [561] = {0xFF86342CU, 0x00000002U}, /* SEC_MODID[561]:CSD1S*/ + [562] = {0xFF863430U, 0x00000002U}, /* SEC_MODID[562]:AXIFBABUSTOP0*/ + [563] = {0xFF863434U, 0x00000002U}, /* SEC_MODID[563]:AXIFBABUSTOP1*/ + [564] = {0xFF863438U, 0x00000002U}, /* SEC_MODID[564]:ARSTM2*/ + [565] = {0xFF86343CU, 0x00000002U}, /* SEC_MODID[565]:ARSTM3*/ + [566] = {0xFF863440U, 0x00000002U}, /* SEC_MODID[566]:ARSTM4*/ + [567] = {0xFF863444U, 0x00000002U}, /* SEC_MODID[567]:ARSTM5*/ + [568] = {0xFF863448U, 0x00000002U}, /* SEC_MODID[568]:ARSTM6*/ + [569] = {0xFF86344CU, 0x00000002U}, /* SEC_MODID[569]:ARSTM7*/ + [570] = {0xFF863450U, 0x00000002U}, /* SEC_MODID[570]:ARSTM8*/ + [571] = {0xFF863454U, 0x00000002U}, /* SEC_MODID[571]:ECMTOP*/ + [572] = {0xFF863458U, 0x00000002U}, /* SEC_MODID[572]:FBA*/ + [573] = {0xFF86345CU, 0x00000002U}, /* SEC_MODID[573]:FBC*/ + [574] = {0xFF863460U, 0x00000002U}, /* SEC_MODID[574]:AXICCI00*/ + [575] = {0xFF863464U, 0x00000002U}, /* SEC_MODID[575]:AXICCI01*/ + [576] = {0xFF863468U, 0x00000002U}, /* SEC_MODID[576]:AXICCI10*/ + [577] = {0xFF86346CU, 0x00000002U}, /* SEC_MODID[577]:AXICCI11*/ + [578] = {0xFF863470U, 0x00000002U}, /* SEC_MODID[578]:AXICCI12*/ + [579] = {0xFF863474U, 0x00000002U}, /* SEC_MODID[579]:AXICCI13*/ + [580] = {0xFF863478U, 0x00000002U}, /* SEC_MODID[580]:AXICCI14*/ + [581] = {0xFF86347CU, 0x00000002U}, /* SEC_MODID[581]:AXICCI15*/ + [582] = {0xFF863480U, 0x00000002U}, /* SEC_MODID[582]:AXICCI2*/ + [583] = {0xFF863484U, 0x00000002U}, /* SEC_MODID[583]:AXICCI3*/ + [584] = {0xFF863488U, 0x00000002U}, /* SEC_MODID[584]:AXICCI4*/ + [585] = {0xFF86348CU, 0x00000002U}, /* SEC_MODID[585]:AXICCI5*/ + [586] = {0xFF863490U, 0x00000002U}, /* SEC_MODID[586]:AXICCI6*/ + [587] = {0xFF863494U, 0x00000002U}, /* SEC_MODID[587]:AXICCI7*/ + [588] = {0xFF863498U, 0x00000002U}, /* SEC_MODID[588]:AXICCI8*/ + [589] = {0xFF86349CU, 0x00000002U}, /* SEC_MODID[589]:AXICCI9*/ + [590] = {0xFF8634A0U, 0x00000002U}, /* SEC_MODID[590]:ECMSTM*/ + [591] = {0xE7783400U, 0x00000002U}, /* SEC_MODID[591]:DMASSI00*/ + [592] = {0xE7783404U, 0x00000002U}, /* SEC_MODID[592]:DMASSI01*/ + [593] = {0xE7783408U, 0x00000002U}, /* SEC_MODID[593]:DMASSI02*/ + [594] = {0xE778340CU, 0x00000002U}, /* SEC_MODID[594]:DMASSI03*/ + [595] = {0xE7783410U, 0x00000002U}, /* SEC_MODID[595]:DMASSI04*/ + [596] = {0xE7783414U, 0x00000002U}, /* SEC_MODID[596]:DMAI2C0*/ + [597] = {0xE7783418U, 0x00000002U}, /* SEC_MODID[597]:DMAI2C1*/ + [598] = {0xE778341CU, 0x00000002U}, /* SEC_MODID[598]:DMAI2C2*/ + [599] = {0xE7783420U, 0x00000002U}, /* SEC_MODID[599]:DMAI2C3*/ + [600] = {0xE7783424U, 0x00000002U}, /* SEC_MODID[600]:DMAI2C4*/ + [601] = {0xE7783428U, 0x00000002U}, /* SEC_MODID[601]:DMAI2C5*/ + [602] = {0xE778342CU, 0x00000002U}, /* SEC_MODID[602]:DMASSI05*/ + [603] = {0xE7783430U, 0x00000002U}, /* SEC_MODID[603]:DMASSI06*/ + [604] = {0xE7783434U, 0x00000002U}, /* SEC_MODID[604]:DMASSI07*/ + [605] = {0xE67C3400U, 0x00000002U}, /* SEC_MODID[605]:ARMM*/ + [606] = {0xE67C3404U, 0x00000002U}, /* SEC_MODID[606]:AXIARNMM*/ + [607] = {0xE67C3408U, 0x00000002U}, /* SEC_MODID[607]:ARSM0*/ + [608] = {0xE67C340CU, 0x00000002U}, /* SEC_MODID[608]:ARSM1*/ + [609] = {0xE67C3410U, 0x00000002U}, /* SEC_MODID[609]:ARSM2*/ + [610] = {0xE67C3414U, 0x00000002U}, /* SEC_MODID[610]:AXIQOS0*/ + [611] = {0xE67C3418U, 0x00000002U}, /* SEC_MODID[611]:AXIQOS1*/ + [612] = {0xE67C341CU, 0x00000002U}, /* SEC_MODID[612]:AXIQOS2*/ + [613] = {0xE67C3420U, 0x00000002U}, /* SEC_MODID[613]:AXIQOS3*/ + [614] = {0xE67C3424U, 0x00000002U}, /* SEC_MODID[614]:AXIQOS4*/ + [615] = {0xE67C3428U, 0x00000002U}, /* SEC_MODID[615]:AXIQOS5*/ + [616] = {0xE67C342CU, 0x00000002U}, /* SEC_MODID[616]:AXIQOS6*/ + [617] = {0xE67C3430U, 0x00000002U}, /* SEC_MODID[617]:AXIQOS7*/ + [618] = {0xE67C3434U, 0x00000002U}, /* SEC_MODID[618]:ARSM3*/ + [619] = {0xE67C3438U, 0x00000002U}, /* SEC_MODID[619]:ARSM4*/ + [620] = {0xE67C343CU, 0x00000002U}, /* SEC_MODID[620]:ARSM5*/ + [621] = {0xE67C3440U, 0x00000002U}, /* SEC_MODID[621]:ARSM6*/ + [622] = {0xE67C3444U, 0x00000002U}, /* SEC_MODID[622]:ARSM7*/ + [623] = {0xE67C3448U, 0x00000002U}, /* SEC_MODID[623]:ARSM8*/ + [624] = {0xE67C344CU, 0x00000000U}, /* SEC_MODID[624]:AXMM0*/ + [625] = {0xE67C3450U, 0x00000000U}, /* SEC_MODID[625]:AXMM1*/ + [626] = {0xE67C3454U, 0x00000002U}, /* SEC_MODID[626]:AXMMPMON*/ + [627] = {0xE67C3458U, 0x00000002U}, /* SEC_MODID[627]:CKMMM*/ + [628] = {0xE67C345CU, 0x00000002U}, /* SEC_MODID[628]:ECMMM*/ + [629] = {0xE67C3460U, 0x00000002U}, /* SEC_MODID[629]:FBADBSC0*/ + [630] = {0xE67C3464U, 0x00000002U}, /* SEC_MODID[630]:FBADBSC1*/ + [631] = {0xE67C3468U, 0x00000002U}, /* SEC_MODID[631]:FBAMM*/ + [632] = {0xE67C346CU, 0x00000002U}, /* SEC_MODID[632]:IPMMUMM00*/ + [633] = {0xE67C3470U, 0x00000002U}, /* SEC_MODID[633]:DBS0A0*/ + [634] = {0xE67C3474U, 0x00000002U}, /* SEC_MODID[634]:DBS0A1*/ + [635] = {0xE67C3478U, 0x00000002U}, /* SEC_MODID[635]:DBS1A0*/ + [636] = {0xE67C347CU, 0x00000002U}, /* SEC_MODID[636]:DBS1A1*/ + [637] = {0xE67C3480U, 0x00000002U}, /* SEC_MODID[637]:AXCIDBS*/ + [638] = {0xE67C3484U, 0x00000002U}, /* SEC_MODID[638]:FCPRC*/ + [639] = {0xE67C3488U, 0x00000002U}, /* SEC_MODID[639]:DBS0D0*/ + [640] = {0xE67C348CU, 0x00000002U}, /* SEC_MODID[640]:DBS0D1*/ + [641] = {0xE67C3490U, 0x00000002U}, /* SEC_MODID[641]:DBS1D0*/ + [642] = {0xE67C3494U, 0x00000002U}, /* SEC_MODID[642]:DBS1D1*/ + [643] = {0xE67C3498U, 0x00000002U}, /* SEC_MODID[643]:FBADDR*/ + [644] = {0xE67C349CU, 0x00000002U}, /* SEC_MODID[644]:IPMMUMM01*/ + [645] = {0xE67C34A0U, 0x00000002U}, /* SEC_MODID[645]:IPMMUMM10*/ + [646] = {0xE67C34A4U, 0x00000002U}, /* SEC_MODID[646]:IPMMUMM11*/ + [647] = {0xE67C34A8U, 0x00000002U}, /* SEC_MODID[647]:IPMMUMM12*/ + [648] = {0xE67C34ACU, 0x00000002U}, /* SEC_MODID[648]:IPMMUMM13*/ + [649] = {0xE67C34B0U, 0x00000002U}, /* SEC_MODID[649]:IPMMUMM14*/ + [650] = {0xE67C34B4U, 0x00000002U}, /* SEC_MODID[650]:IPMMUMM15*/ + [651] = {0xE67C34B8U, 0x00000002U}, /* SEC_MODID[651]:IPMMUMM02*/ + [652] = {0xE67C34BCU, 0x00000002U}, /* SEC_MODID[652]:IPMMUMM03*/ + [653] = {0xE67C34C0U, 0x00000002U}, /* SEC_MODID[653]:IPMMUMM04*/ + [654] = {0xE67C34C4U, 0x00000002U}, /* SEC_MODID[654]:IPMMUMM05*/ + [655] = {0xE67C34C8U, 0x00000002U}, /* SEC_MODID[655]:IPMMUMM06*/ + [656] = {0xE67C34CCU, 0x00000002U}, /* SEC_MODID[656]:IPMMUMM07*/ + [657] = {0xE67C34D0U, 0x00000002U}, /* SEC_MODID[657]:IPMMUMM08*/ + [658] = {0xE67C34D4U, 0x00000002U}, /* SEC_MODID[658]:IPMMUMM09*/ + [659] = {0xFF803400U, 0x00000002U}, /* SEC_MODID[659]:ARSN0*/ + [660] = {0xFF803404U, 0x00000002U}, /* SEC_MODID[660]:ARSN1*/ + [661] = {0xFF803408U, 0x00000002U}, /* SEC_MODID[661]:ARSN2*/ + [662] = {0xFF80340CU, 0x00000002U}, /* SEC_MODID[662]:ARSN3*/ + [663] = {0xFF803410U, 0x00000002U}, /* SEC_MODID[663]:ARSN4*/ + [664] = {0xFF803414U, 0x00000002U}, /* SEC_MODID[664]:ARSN5*/ + [665] = {0xFF803418U, 0x00000002U}, /* SEC_MODID[665]:ARSN6*/ + [666] = {0xFF80341CU, 0x00000002U}, /* SEC_MODID[666]:ARSN7*/ + [667] = {0xFF803420U, 0x00000002U}, /* SEC_MODID[667]:ARSN8*/ + [668] = {0xFF803424U, 0x00000002U}, /* SEC_MODID[668]:ECMTOP3*/ + [669] = {0xE7753400U, 0x00000002U}, /* SEC_MODID[669]:ARSD00*/ + [670] = {0xE7753404U, 0x00000002U}, /* SEC_MODID[670]:ARSD01*/ + [671] = {0xE7753408U, 0x00000002U}, /* SEC_MODID[671]:ARSD02*/ + [672] = {0xE775340CU, 0x00000002U}, /* SEC_MODID[672]:ARSD03*/ + [673] = {0xE7753410U, 0x00000002U}, /* SEC_MODID[673]:ARSD04*/ + [674] = {0xE7753414U, 0x00000002U}, /* SEC_MODID[674]:ARSD05*/ + [675] = {0xE7753418U, 0x00000002U}, /* SEC_MODID[675]:ARSD06*/ + [676] = {0xE775341CU, 0x00000002U}, /* SEC_MODID[676]:AXIFRAY*/ + [677] = {0xE7753420U, 0x00000002U}, /* SEC_MODID[677]:AXIIPC*/ + [678] = {0xE7753428U, 0x00000002U}, /* SEC_MODID[678]:AXIRPC*/ + [679] = {0xE775342CU, 0x00000002U}, /* SEC_MODID[679]:AXISDHI0*/ + [680] = {0xE7753430U, 0x00000002U}, /* SEC_MODID[680]:ARSD07*/ + [681] = {0xE7753434U, 0x00000002U}, /* SEC_MODID[681]:ARSD08*/ + [682] = {0xE7753438U, 0x00000002U}, /* SEC_MODID[682]:ARSP00*/ + [683] = {0xE775343CU, 0x00000002U}, /* SEC_MODID[683]:ARSP01*/ + [684] = {0xE7753440U, 0x00000002U}, /* SEC_MODID[684]:ARSP02*/ + [685] = {0xE7753444U, 0x00000002U}, /* SEC_MODID[685]:ARSP03*/ + [686] = {0xE7753448U, 0x00000002U}, /* SEC_MODID[686]:ARSP04*/ + [687] = {0xE775344CU, 0x00000002U}, /* SEC_MODID[687]:ARSP05*/ + [688] = {0xE7753450U, 0x00000002U}, /* SEC_MODID[688]:ARSP06*/ + [689] = {0xE7753454U, 0x00000002U}, /* SEC_MODID[689]:ARSP07*/ + [690] = {0xE7753458U, 0x00000002U}, /* SEC_MODID[690]:ARSP08*/ + [691] = {0xE775345CU, 0x00000002U}, /* SEC_MODID[691]:IPMMUDS001*/ + [692] = {0xE7753460U, 0x00000002U}, /* SEC_MODID[692]:CKMPER0*/ + [693] = {0xE7753464U, 0x00000002U}, /* SEC_MODID[693]:ECMPER0*/ + [694] = {0xE7753468U, 0x00000002U}, /* SEC_MODID[694]:FBAPER0*/ + [695] = {0xE775346CU, 0x00000002U}, /* SEC_MODID[695]:FSO0*/ + [696] = {0xE7753470U, 0x00000002U}, /* SEC_MODID[696]:FSO1*/ + [697] = {0xE7753474U, 0x00000002U}, /* SEC_MODID[697]:FSO10*/ + [698] = {0xE7753478U, 0x00000002U}, /* SEC_MODID[698]:FSO2*/ + [699] = {0xE775347CU, 0x00000002U}, /* SEC_MODID[699]:FSO3*/ + [700] = {0xE7753480U, 0x00000002U}, /* SEC_MODID[700]:FSO4*/ + [701] = {0xE7753484U, 0x00000002U}, /* SEC_MODID[701]:FSO5*/ + [702] = {0xE7753488U, 0x00000002U}, /* SEC_MODID[702]:FSO6*/ + [703] = {0xE775348CU, 0x00000002U}, /* SEC_MODID[703]:FSO7*/ + [704] = {0xE7753490U, 0x00000002U}, /* SEC_MODID[704]:FSO8*/ + [705] = {0xE7753494U, 0x00000002U}, /* SEC_MODID[705]:FSO9*/ + [706] = {0xE7753498U, 0x00000002U}, /* SEC_MODID[706]:ADG*/ + [707] = {0xE775349CU, 0x00000002U}, /* SEC_MODID[707]:ECMSD0*/ + [708] = {0xE77534A0U, 0x00000002U}, /* SEC_MODID[708]:IPMMUDS010*/ + [709] = {0xE77534A4U, 0x00000002U}, /* SEC_MODID[709]:IPMMUDS011*/ + [710] = {0xE77534A8U, 0x00000002U}, /* SEC_MODID[710]:I2C0*/ + [711] = {0xE77534ACU, 0x00000002U}, /* SEC_MODID[711]:I2C1*/ + [712] = {0xE77534B0U, 0x00000002U}, /* SEC_MODID[712]:I2C2*/ + [713] = {0xE77534B4U, 0x00000002U}, /* SEC_MODID[713]:I2C3*/ + [714] = {0xE77534B8U, 0x00000002U}, /* SEC_MODID[714]:I2C4*/ + [715] = {0xE77534BCU, 0x00000002U}, /* SEC_MODID[715]:I2C5*/ + [716] = {0xE77534C0U, 0x00000002U}, /* SEC_MODID[716]:IPMMUDS012*/ + [717] = {0xE77534C4U, 0x00000002U}, /* SEC_MODID[717]:IPC*/ + [718] = {0xE77534C8U, 0x00000002U}, /* SEC_MODID[718]:IPMMUDS000*/ + [719] = {0xE77534CCU, 0x00000002U}, /* SEC_MODID[719]:IPMMUDS013*/ + [720] = {0xE77534D0U, 0x00000002U}, /* SEC_MODID[720]:IPMMUDS014*/ + [721] = {0xE77534D4U, 0x00000002U}, /* SEC_MODID[721]:IPMMUDS015*/ + [722] = {0xE77534D8U, 0x00000002U}, /* SEC_MODID[722]:IPMMUDS002*/ + [723] = {0xE77534DCU, 0x00000002U}, /* SEC_MODID[723]:IPMMUDS003*/ + [724] = {0xE77534E0U, 0x00000002U}, /* SEC_MODID[724]:IPMMUDS004*/ + [725] = {0xE77534E4U, 0x00000002U}, /* SEC_MODID[725]:IPMMUDS005*/ + [726] = {0xE77534E8U, 0x00000002U}, /* SEC_MODID[726]:SSI*/ + [727] = {0xE77534ECU, 0x00000002U}, /* SEC_MODID[727]:IPMMUDS006*/ + [728] = {0xE77534F0U, 0x00000002U}, /* SEC_MODID[728]:IPMMUDS007*/ + [729] = {0xE77534F4U, 0x00000002U}, /* SEC_MODID[729]:SYDM1P*/ + [730] = {0xE77534F8U, 0x00000002U}, /* SEC_MODID[730]:IPMMUDS008*/ + [731] = {0xE77534FCU, 0x00000002U}, /* SEC_MODID[731]:SYDM2P*/ + [732] = {0xE7753500U, 0x00000002U}, /* SEC_MODID[732]:IPMMUDS009*/ + [733] = {0xE7753640U, 0x00000002U}, /* SEC_MODID[733]:SYDM100*/ + [734] = {0xE7753644U, 0x00000002U}, /* SEC_MODID[734]:SYDM101*/ + [735] = {0xE7753648U, 0x00000002U}, /* SEC_MODID[735]:SYDM110*/ + [736] = {0xE775364CU, 0x00000002U}, /* SEC_MODID[736]:SYDM111*/ + [737] = {0xE7753650U, 0x00000002U}, /* SEC_MODID[737]:SYDM112*/ + [738] = {0xE7753654U, 0x00000002U}, /* SEC_MODID[738]:SYDM113*/ + [739] = {0xE7753658U, 0x00000002U}, /* SEC_MODID[739]:SYDM114*/ + [740] = {0xE775365CU, 0x00000002U}, /* SEC_MODID[740]:SYDM115*/ + [741] = {0xE7753660U, 0x00000002U}, /* SEC_MODID[741]:SYDM102*/ + [742] = {0xE7753664U, 0x00000002U}, /* SEC_MODID[742]:SYDM103*/ + [743] = {0xE7753668U, 0x00000002U}, /* SEC_MODID[743]:SYDM104*/ + [744] = {0xE775366CU, 0x00000002U}, /* SEC_MODID[744]:SYDM105*/ + [745] = {0xE7753670U, 0x00000002U}, /* SEC_MODID[745]:SYDM106*/ + [746] = {0xE7753674U, 0x00000002U}, /* SEC_MODID[746]:SYDM107*/ + [747] = {0xE7753678U, 0x00000002U}, /* SEC_MODID[747]:SYDM108*/ + [748] = {0xE775367CU, 0x00000002U}, /* SEC_MODID[748]:SYDM109*/ + [749] = {0xE7753680U, 0x00000002U}, /* SEC_MODID[749]:SYDM200*/ + [750] = {0xE7753684U, 0x00000002U}, /* SEC_MODID[750]:SYDM201*/ + [751] = {0xE7753688U, 0x00000002U}, /* SEC_MODID[751]:SYDM210*/ + [752] = {0xE775368CU, 0x00000002U}, /* SEC_MODID[752]:SYDM211*/ + [753] = {0xE7753690U, 0x00000002U}, /* SEC_MODID[753]:SYDM212*/ + [754] = {0xE7753694U, 0x00000002U}, /* SEC_MODID[754]:SYDM213*/ + [755] = {0xE7753698U, 0x00000002U}, /* SEC_MODID[755]:SYDM214*/ + [756] = {0xE775369CU, 0x00000002U}, /* SEC_MODID[756]:SYDM215*/ + [757] = {0xE77536A0U, 0x00000002U}, /* SEC_MODID[757]:SYDM202*/ + [758] = {0xE77536A4U, 0x00000002U}, /* SEC_MODID[758]:SYDM203*/ + [759] = {0xE77536A8U, 0x00000002U}, /* SEC_MODID[759]:SYDM204*/ + [760] = {0xE77536ACU, 0x00000002U}, /* SEC_MODID[760]:SYDM205*/ + [761] = {0xE77536B0U, 0x00000002U}, /* SEC_MODID[761]:SYDM206*/ + [762] = {0xE77536B4U, 0x00000002U}, /* SEC_MODID[762]:SYDM207*/ + [763] = {0xE77536B8U, 0x00000002U}, /* SEC_MODID[763]:SYDM208*/ + [764] = {0xE77536BCU, 0x00000002U}, /* SEC_MODID[764]:SYDM209*/ + [765] = {0xFE683400U, 0x00000002U}, /* SEC_MODID[765]:ARVC0*/ + [766] = {0xFE683404U, 0x00000002U}, /* SEC_MODID[766]:ARVC1*/ + [767] = {0xFE683408U, 0x00000002U}, /* SEC_MODID[767]:ARVC2*/ + [768] = {0xFE68340CU, 0x00000002U}, /* SEC_MODID[768]:ARVC3*/ + [769] = {0xFE683410U, 0x00000002U}, /* SEC_MODID[769]:AXIFBABUSVC*/ + [770] = {0xFE683414U, 0x00000002U}, /* SEC_MODID[770]:ARVC4*/ + [771] = {0xFE683418U, 0x00000002U}, /* SEC_MODID[771]:ARVC5*/ + [772] = {0xFE68341CU, 0x00000002U}, /* SEC_MODID[772]:ARVC6*/ + [773] = {0xFE683420U, 0x00000002U}, /* SEC_MODID[773]:ARVC7*/ + [774] = {0xFE683424U, 0x00000002U}, /* SEC_MODID[774]:ARVC8*/ + [775] = {0xFE683428U, 0x00000002U}, /* SEC_MODID[775]:CKMVC*/ + [776] = {0xFE68342CU, 0x00000002U}, /* SEC_MODID[776]:ECMVC0*/ + [777] = {0xFE683430U, 0x00000002U}, /* SEC_MODID[777]:IMR2*/ + [778] = {0xFE683434U, 0x00000002U}, /* SEC_MODID[778]:IMR0*/ + [779] = {0xFE683438U, 0x00000002U}, /* SEC_MODID[779]:IMR1*/ + [780] = {0xFE68343CU, 0x00000002U}, /* SEC_MODID[780]:IPMMUVC01*/ + [781] = {0xFE683440U, 0x00000002U}, /* SEC_MODID[781]:IPMMUVC10*/ + [782] = {0xFE683444U, 0x00000002U}, /* SEC_MODID[782]:IMS0*/ + [783] = {0xFE683448U, 0x00000002U}, /* SEC_MODID[783]:IMS1*/ + [784] = {0xFE68344CU, 0x00000002U}, /* SEC_MODID[784]:IPMMUVC00*/ + [785] = {0xFE683450U, 0x00000002U}, /* SEC_MODID[785]:IPMMUVC11*/ + [786] = {0xFE683454U, 0x00000002U}, /* SEC_MODID[786]:IPMMUVC12*/ + [787] = {0xFE683458U, 0x00000002U}, /* SEC_MODID[787]:IPMMUVC13*/ + [788] = {0xFE68345CU, 0x00000002U}, /* SEC_MODID[788]:IPMMUVC14*/ + [789] = {0xFE683460U, 0x00000002U}, /* SEC_MODID[789]:IPMMUVC15*/ + [790] = {0xFE683464U, 0x00000002U}, /* SEC_MODID[790]:IPMMUVC02*/ + [791] = {0xFE683468U, 0x00000002U}, /* SEC_MODID[791]:IPMMUVC03*/ + [792] = {0xFE68346CU, 0x00000002U}, /* SEC_MODID[792]:IPMMUVC04*/ + [793] = {0xFE683470U, 0x00000002U}, /* SEC_MODID[793]:IPMMUVC05*/ + [794] = {0xFE683474U, 0x00000002U}, /* SEC_MODID[794]:IPMMUVC06*/ + [795] = {0xFE683478U, 0x00000002U}, /* SEC_MODID[795]:IPMMUVC07*/ + [796] = {0xFE68347CU, 0x00000002U}, /* SEC_MODID[796]:IPMMUVC08*/ + [797] = {0xFE683480U, 0x00000002U}, /* SEC_MODID[797]:IPMMUVC09*/ + [798] = {0xFE683484U, 0x00000002U}, /* SEC_MODID[798]:IV1ES*/ + [799] = {0xFEBE3400U, 0x00000002U}, /* SEC_MODID[799]:CSITOP0*/ + [800] = {0xFEBE3404U, 0x00000002U}, /* SEC_MODID[800]:ARVI10*/ + [801] = {0xFEBE3408U, 0x00000002U}, /* SEC_MODID[801]:ARVI11*/ + [802] = {0xFEBE340CU, 0x00000002U}, /* SEC_MODID[802]:ARVI12*/ + [803] = {0xFEBE3410U, 0x00000002U}, /* SEC_MODID[803]:ARVI13*/ + [804] = {0xFEBE3414U, 0x00000002U}, /* SEC_MODID[804]:ARVI14*/ + [805] = {0xFEBE3418U, 0x00000002U}, /* SEC_MODID[805]:ARVI15*/ + [806] = {0xFEBE341CU, 0x00000002U}, /* SEC_MODID[806]:ARVI16*/ + [807] = {0xFEBE3420U, 0x00000002U}, /* SEC_MODID[807]:ARVI17*/ + [808] = {0xFEBE3424U, 0x00000002U}, /* SEC_MODID[808]:ARVI18*/ + [809] = {0xFEBE3428U, 0x00000002U}, /* SEC_MODID[809]:CKMVIO*/ + [810] = {0xFEBE342CU, 0x00000002U}, /* SEC_MODID[810]:CSITOP1*/ + [811] = {0xFEBE3434U, 0x00000002U}, /* SEC_MODID[811]:DSITLINK0*/ + [812] = {0xFEBE3438U, 0x00000002U}, /* SEC_MODID[812]:DSITLINK1*/ + [813] = {0xFEBE343CU, 0x00000002U}, /* SEC_MODID[813]:ECMVIO1*/ + [814] = {0xFEBE3444U, 0x00000002U}, /* SEC_MODID[814]:IPMMUVI001*/ + [815] = {0xFEBE3448U, 0x00000002U}, /* SEC_MODID[815]:FCPVX0*/ + [816] = {0xFEBE344CU, 0x00000002U}, /* SEC_MODID[816]:FCPVX1*/ + [817] = {0xFEBE3458U, 0x00000002U}, /* SEC_MODID[817]:IPMMUVI000*/ + [818] = {0xFEBE345CU, 0x00000002U}, /* SEC_MODID[818]:IPMMUVI100*/ + [819] = {0xFEBE3460U, 0x00000002U}, /* SEC_MODID[819]:IPMMUVI010*/ + [820] = {0xFEBE3464U, 0x00000002U}, /* SEC_MODID[820]:IPMMUVI011*/ + [821] = {0xFEBE3468U, 0x00000002U}, /* SEC_MODID[821]:VSPX0*/ + [822] = {0xFEBE346CU, 0x00000002U}, /* SEC_MODID[822]:VSPX1*/ + [823] = {0xFEBE3478U, 0x00000002U}, /* SEC_MODID[823]:IPMMUVI012*/ + [824] = {0xFEBE347CU, 0x00000002U}, /* SEC_MODID[824]:IPMMUVI013*/ + [825] = {0xFEBE3480U, 0x00000002U}, /* SEC_MODID[825]:IPMMUVI014*/ + [826] = {0xFEBE3484U, 0x00000002U}, /* SEC_MODID[826]:IPMMUVI015*/ + [827] = {0xFEBE3488U, 0x00000002U}, /* SEC_MODID[827]:IPMMUVI002*/ + [828] = {0xFEBE348CU, 0x00000002U}, /* SEC_MODID[828]:IPMMUVI003*/ + [829] = {0xFEBE3490U, 0x00000002U}, /* SEC_MODID[829]:IPMMUVI004*/ + [830] = {0xFEBE3494U, 0x00000002U}, /* SEC_MODID[830]:IPMMUVI005*/ + [831] = {0xFEBE3498U, 0x00000002U}, /* SEC_MODID[831]:IPMMUVI006*/ + [832] = {0xFEBE349CU, 0x00000002U}, /* SEC_MODID[832]:IPMMUVI007*/ + [833] = {0xFEBE34A0U, 0x00000002U}, /* SEC_MODID[833]:IPMMUVI008*/ + [834] = {0xFEBE34A4U, 0x00000002U}, /* SEC_MODID[834]:IPMMUVI009*/ + [835] = {0xFEBE34A8U, 0x00000002U}, /* SEC_MODID[835]:IPMMUVI101*/ + [836] = {0xFEBE34ACU, 0x00000002U}, /* SEC_MODID[836]:IPMMUVI110*/ + [837] = {0xFEBE34B0U, 0x00000002U}, /* SEC_MODID[837]:IPMMUVI111*/ + [838] = {0xFEBE34B4U, 0x00000002U}, /* SEC_MODID[838]:IPMMUVI112*/ + [839] = {0xFEBE34B8U, 0x00000002U}, /* SEC_MODID[839]:IPMMUVI113*/ + [840] = {0xFEBE34BCU, 0x00000002U}, /* SEC_MODID[840]:IPMMUVI114*/ + [841] = {0xFEBE34C0U, 0x00000002U}, /* SEC_MODID[841]:IPMMUVI115*/ + [842] = {0xFEBE34C4U, 0x00000002U}, /* SEC_MODID[842]:IPMMUVI102*/ + [843] = {0xFEBE34C8U, 0x00000002U}, /* SEC_MODID[843]:IPMMUVI103*/ + [844] = {0xFEBE34CCU, 0x00000002U}, /* SEC_MODID[844]:IPMMUVI104*/ + [845] = {0xFEBE34D0U, 0x00000002U}, /* SEC_MODID[845]:IPMMUVI105*/ + [846] = {0xFEBE34D4U, 0x00000002U}, /* SEC_MODID[846]:IPMMUVI106*/ + [847] = {0xFEBE34D8U, 0x00000002U}, /* SEC_MODID[847]:IPMMUVI107*/ + [848] = {0xFEBE34DCU, 0x00000002U}, /* SEC_MODID[848]:IPMMUVI108*/ + [849] = {0xFEBE34E0U, 0x00000002U}, /* SEC_MODID[849]:IPMMUVI109*/ + [850] = {0xFEBE3504U, 0x00000002U}, /* SEC_MODID[850]:AXIFBABUSVIO*/ + [851] = {0xFEBF3400U, 0x00000002U}, /* SEC_MODID[851]:ARVI0*/ + [852] = {0xFEBF3404U, 0x00000002U}, /* SEC_MODID[852]:ARVI1*/ + [853] = {0xFEBF3408U, 0x00000002U}, /* SEC_MODID[853]:ARVI2*/ + [854] = {0xFEBF340CU, 0x00000002U}, /* SEC_MODID[854]:ARVI3*/ + [855] = {0xFEBF3410U, 0x00000002U}, /* SEC_MODID[855]:ARVI4*/ + [856] = {0xFEBF3414U, 0x00000002U}, /* SEC_MODID[856]:ARVI5*/ + [857] = {0xFEBF3418U, 0x00000002U}, /* SEC_MODID[857]:ARVI6*/ + [858] = {0xFEBF341CU, 0x00000002U}, /* SEC_MODID[858]:ARVI7*/ + [859] = {0xFEBF3420U, 0x00000002U}, /* SEC_MODID[859]:ARVI8*/ + [860] = {0xFEBF3424U, 0x00000002U}, /* SEC_MODID[860]:ECMVIO0*/ + [861] = {0xFEBF3428U, 0x00000002U}, /* SEC_MODID[861]:ISP0*/ + [862] = {0xFEBF342CU, 0x00000002U}, /* SEC_MODID[862]:ISP0CORE*/ + [863] = {0xFEBF3430U, 0x00000002U}, /* SEC_MODID[863]:ISP1*/ + [864] = {0xFEBF3434U, 0x00000002U}, /* SEC_MODID[864]:ISP1CORE*/ + [865] = {0xFEBF3454U, 0x00000002U}, /* SEC_MODID[865]:VIN00*/ + [866] = {0xFEBF3458U, 0x00000002U}, /* SEC_MODID[866]:VIN01*/ + [867] = {0xFEBF345CU, 0x00000002U}, /* SEC_MODID[867]:VIN02*/ + [868] = {0xFEBF3460U, 0x00000002U}, /* SEC_MODID[868]:VIN03*/ + [869] = {0xFEBF3464U, 0x00000002U}, /* SEC_MODID[869]:VIN04*/ + [870] = {0xFEBF3468U, 0x00000002U}, /* SEC_MODID[870]:VIN05*/ + [871] = {0xFEBF346CU, 0x00000002U}, /* SEC_MODID[871]:VIN06*/ + [872] = {0xFEBF3470U, 0x00000002U}, /* SEC_MODID[872]:VIN07*/ + [873] = {0xFEBF3474U, 0x00000002U}, /* SEC_MODID[873]:VIN10*/ + [874] = {0xFEBF3478U, 0x00000002U}, /* SEC_MODID[874]:VIN11*/ + [875] = {0xFEBF347CU, 0x00000002U}, /* SEC_MODID[875]:VIN12*/ + [876] = {0xFEBF3480U, 0x00000002U}, /* SEC_MODID[876]:VIN13*/ + [877] = {0xFEBF3484U, 0x00000002U}, /* SEC_MODID[877]:VIN14*/ + [878] = {0xFEBF3488U, 0x00000002U}, /* SEC_MODID[878]:VIN15*/ + [879] = {0xFEBF348CU, 0x00000002U}, /* SEC_MODID[879]:VIN16*/ + [880] = {0xFEBF3490U, 0x00000002U}, /* SEC_MODID[880]:VIN17*/ + [881] = {0xE7B13400U, 0x00000002U}, /* SEC_MODID[881]:ARVIP00*/ + [882] = {0xE7B13404U, 0x00000002U}, /* SEC_MODID[882]:ARVIP01*/ + [883] = {0xE7B13408U, 0x00000002U}, /* SEC_MODID[883]:ARVIP02*/ + [884] = {0xE7B1340CU, 0x00000002U}, /* SEC_MODID[884]:ARVIP03*/ + [885] = {0xE7B13410U, 0x00000002U}, /* SEC_MODID[885]:AXIFBABUSVIP0*/ + [886] = {0xE7B13414U, 0x00000002U}, /* SEC_MODID[886]:ARVIP04*/ + [887] = {0xE7B13418U, 0x00000002U}, /* SEC_MODID[887]:ARVIP05*/ + [888] = {0xE7B1341CU, 0x00000002U}, /* SEC_MODID[888]:ARVIP06*/ + [889] = {0xE7B13420U, 0x00000002U}, /* SEC_MODID[889]:ARVIP07*/ + [890] = {0xE7B13424U, 0x00000002U}, /* SEC_MODID[890]:ARVIP08*/ + [891] = {0xE7B13428U, 0x00000002U}, /* SEC_MODID[891]:CKMVIP*/ + [892] = {0xE7B1342CU, 0x00000002U}, /* SEC_MODID[892]:ECMVIP0*/ + [893] = {0xE7B13430U, 0x00000002U}, /* SEC_MODID[893]:IPMMUVIP000*/ + [894] = {0xE7B13438U, 0x00000002U}, /* SEC_MODID[894]:SMPO0*/ + [895] = {0xE7B1343CU, 0x00000002U}, /* SEC_MODID[895]:SMPS0*/ + [896] = {0xE7B13440U, 0x00000002U}, /* SEC_MODID[896]:UMFL0*/ + [897] = {0xE7B13444U, 0x00000002U}, /* SEC_MODID[897]:IPMMUVIP001*/ + [898] = {0xE7B13448U, 0x00000002U}, /* SEC_MODID[898]:IPMMUVIP010*/ + [899] = {0xE7B1344CU, 0x00000002U}, /* SEC_MODID[899]:IPMMUVIP011*/ + [900] = {0xE7B13450U, 0x00000002U}, /* SEC_MODID[900]:UMFL0M_W*/ + [901] = {0xE7B13454U, 0x00000002U}, /* SEC_MODID[901]:IPMMUVIP012*/ + [902] = {0xE7B13458U, 0x00000002U}, /* SEC_MODID[902]:IPMMUVIP013*/ + [903] = {0xE7B1345CU, 0x00000002U}, /* SEC_MODID[903]:IPMMUVIP014*/ + [904] = {0xE7B13460U, 0x00000002U}, /* SEC_MODID[904]:IPMMUVIP015*/ + [905] = {0xE7B13464U, 0x00000002U}, /* SEC_MODID[905]:IPMMUVIP002*/ + [906] = {0xE7B13468U, 0x00000002U}, /* SEC_MODID[906]:IPMMUVIP003*/ + [907] = {0xE7B1346CU, 0x00000002U}, /* SEC_MODID[907]:IPMMUVIP004*/ + [908] = {0xE7B13470U, 0x00000002U}, /* SEC_MODID[908]:IPMMUVIP005*/ + [909] = {0xE7B13474U, 0x00000002U}, /* SEC_MODID[909]:IPMMUVIP006*/ + [910] = {0xE7B13478U, 0x00000002U}, /* SEC_MODID[910]:IPMMUVIP007*/ + [911] = {0xE7B1347CU, 0x00000002U}, /* SEC_MODID[911]:IPMMUVIP008*/ + [912] = {0xE7B13480U, 0x00000002U}, /* SEC_MODID[912]:IPMMUVIP009*/ + [913] = {0xE7B43400U, 0x00000002U}, /* SEC_MODID[913]:ARVIP10*/ + [914] = {0xE7B43404U, 0x00000002U}, /* SEC_MODID[914]:ARVIP11*/ + [915] = {0xE7B43408U, 0x00000002U}, /* SEC_MODID[915]:ARVIP12*/ + [916] = {0xE7B4340CU, 0x00000002U}, /* SEC_MODID[916]:ARVIP13*/ + [917] = {0xE7B43410U, 0x00000002U}, /* SEC_MODID[917]:AXIFBABUSVIP1*/ + [918] = {0xE7B43414U, 0x00000002U}, /* SEC_MODID[918]:ARVIIP14*/ + [919] = {0xE7B43418U, 0x00000002U}, /* SEC_MODID[919]:ARVIIP15*/ + [920] = {0xE7B4341CU, 0x00000002U}, /* SEC_MODID[920]:ARVIIP16*/ + [921] = {0xE7B43420U, 0x00000002U}, /* SEC_MODID[921]:ARVIIP17*/ + [922] = {0xE7B43424U, 0x00000002U}, /* SEC_MODID[922]:ARVIIP18*/ + [923] = {0xE7B43438U, 0x00000002U}, /* SEC_MODID[923]:ECMVIP1*/ + [924] = {0xE7B4343CU, 0x00000002U}, /* SEC_MODID[924]:IPMMUVIP101*/ + [925] = {0xE7B43440U, 0x00000002U}, /* SEC_MODID[925]:IPMMUVIP100*/ + [926] = {0xE7B43444U, 0x00000002U}, /* SEC_MODID[926]:IPMMUVIP110*/ + [927] = {0xE7B43448U, 0x00000002U}, /* SEC_MODID[927]:IPMMUVIP111*/ + [928] = {0xE7B4344CU, 0x00000002U}, /* SEC_MODID[928]:IPMMUVIP112*/ + [929] = {0xE7B43450U, 0x00000002U}, /* SEC_MODID[929]:IPMMUVIP113*/ + [930] = {0xE7B43454U, 0x00000002U}, /* SEC_MODID[930]:IPMMUVIP114*/ + [931] = {0xE7B43458U, 0x00000002U}, /* SEC_MODID[931]:IPMMUVIP115*/ + [932] = {0xE7B4345CU, 0x00000002U}, /* SEC_MODID[932]:IPMMUVIP102*/ + [933] = {0xE7B43460U, 0x00000002U}, /* SEC_MODID[933]:IPMMUVIP103*/ + [934] = {0xE7B43464U, 0x00000002U}, /* SEC_MODID[934]:IPMMUVIP104*/ + [935] = {0xE7B43468U, 0x00000002U}, /* SEC_MODID[935]:IPMMUVIP105*/ + [936] = {0xE7B4346CU, 0x00000002U}, /* SEC_MODID[936]:IPMMUVIP106*/ + [937] = {0xE7B43470U, 0x00000002U}, /* SEC_MODID[937]:IPMMUVIP107*/ + [938] = {0xE7B43474U, 0x00000002U}, /* SEC_MODID[938]:IPMMUVIP108*/ + [939] = {0xE7B43478U, 0x00000002U}, /* SEC_MODID[939]:IPMMUVIP109*/ + [940] = {0xE7B43518U, 0x00000002U}, /* SEC_MODID[940]:PAP*/ + [941] = {0xEB803400U, 0x00000002U}, /* SEC_MODID[941]:ARDSP0*/ + [942] = {0xEB803404U, 0x00000002U}, /* SEC_MODID[942]:ARDSP1*/ + [943] = {0xEB803408U, 0x00000002U}, /* SEC_MODID[943]:ARDSP2*/ + [944] = {0xEB80340CU, 0x00000002U}, /* SEC_MODID[944]:ARDSP3*/ + [945] = {0xEB803410U, 0x00000002U}, /* SEC_MODID[945]:ARDSP4*/ + [946] = {0xEB803414U, 0x00000002U}, /* SEC_MODID[946]:ARDSP5*/ + [947] = {0xEB803418U, 0x00000002U}, /* SEC_MODID[947]:ARDSP6*/ + [948] = {0xEB80341CU, 0x00000002U}, /* SEC_MODID[948]:ARDSP7*/ + [949] = {0xEB803420U, 0x00000002U}, /* SEC_MODID[949]:ECMDSP*/ + [950] = {0xEB803424U, 0x00000002U}, /* SEC_MODID[950]:AXIDSP0*/ + [951] = {0xEB803428U, 0x00000002U}, /* SEC_MODID[951]:AXIDSP1*/ + [952] = {0xEB80342CU, 0x00000002U}, /* SEC_MODID[952]:AXIDSP2*/ + [953] = {0xEB803430U, 0x00000002U}, /* SEC_MODID[953]:AXIDSP3*/ + [955] = {0xE67B9624U, 0x00000001U}, /* SEC_MODID[954]:ARCC*/ + [954] = {0xE67B9638U, 0x00000001U}, /* SEC_MODID[955]:ARRTRAM*/ + [956] = {0xE7753424U, 0x00000002U}, /* SEC_MODID[956]:RSV0*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_axi_tbl" +#else +__attribute__ ((section(".rgid_axi_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[] = { + [0] = {0xFFC82010U, 0x0000000FU}, /* RGIDR_MODID[4]:ARRT01*/ + [1] = {0xFFC82014U, 0x0000000FU}, /* RGIDR_MODID[5]:ARRT02*/ + [2] = {0xE6002048U, 0x0000000FU}, /* RGIDR_MODID[42]:ARS01*/ + [3] = {0xE600204CU, 0x0000000FU}, /* RGIDR_MODID[43]:ARS02*/ + [4] = {0xE7762028U, 0x0000000FU}, /* RGIDR_MODID[106]:ARSP31*/ + [5] = {0xE776202CU, 0x0000000FU}, /* RGIDR_MODID[107]:ARSP32*/ + [6] = {0xE7792004U, 0x0000000FU}, /* RGIDR_MODID[121]:ARSP41*/ + [7] = {0xE7792008U, 0x0000000FU}, /* RGIDR_MODID[122]:ARSP42*/ + [8] = {0xFE672004U, 0x0000002FU}, /* RGIDR_MODID[165]:ARVC11*/ + [9] = {0xFE672008U, 0x0000002FU}, /* RGIDR_MODID[166]:ARVC12*/ + [10] = {0xFEBD2004U, 0x0000000FU}, /* RGIDR_MODID[178]:ARVI41*/ + [11] = {0xFEBD2008U, 0x0000000FU}, /* RGIDR_MODID[179]:ARVI42*/ + [12] = {0xE6582140U, 0x0000000FU}, /* RGIDR_MODID[245]:ARHC1*/ + [13] = {0xE6582144U, 0x0000000FU}, /* RGIDR_MODID[246]:ARHC2*/ + [14] = {0xFF882004U, 0x0000000FU}, /* RGIDR_MODID[261]:ARIMP01*/ + [15] = {0xFF882008U, 0x0000000FU}, /* RGIDR_MODID[262]:ARIMP02*/ + [16] = {0xFD812004U, 0x0000000FU}, /* RGIDR_MODID[297]:ARPV1*/ + [17] = {0xFD81200CU, 0x0000000FU}, /* RGIDR_MODID[299]:ARPV2*/ + [18] = {0xE6622004U, 0x0000000FU}, /* RGIDR_MODID[330]:ARRC1*/ + [19] = {0xE6622008U, 0x0000000FU}, /* RGIDR_MODID[331]:ARRC2*/ + [20] = {0xFFC42060U, 0x0000000FU}, /* RGIDR_MODID[369]:ARRD1*/ + [21] = {0xFFC42064U, 0x0000000FU}, /* RGIDR_MODID[370]:ARRD2*/ + [22] = {0xFFC42084U, 0x0000000FU}, /* RGIDR_MODID[378]:ARRT1*/ + [23] = {0xFFC42088U, 0x0000000FU}, /* RGIDR_MODID[379]:ARRT2*/ + [26] = {0xFF862004U, 0x0000000FU}, /* RGIDR_MODID[551]:ARSC1*/ + [27] = {0xFF862008U, 0x0000000FU}, /* RGIDR_MODID[552]:ARSC2*/ + [24] = {0xFF862028U, 0x0000000FU}, /* RGIDR_MODID[560]:ARSTM1*/ + [25] = {0xFF862038U, 0x0000000FU}, /* RGIDR_MODID[564]:ARSTM2*/ + [28] = {0xE67C2004U, 0x0000000FU}, /* RGIDR_MODID[606]:AXIARNMM*/ + [29] = {0xE67C200CU, 0x0000000FU}, /* RGIDR_MODID[608]:ARSM1*/ + [30] = {0xE67C2010U, 0x0000000FU}, /* RGIDR_MODID[609]:ARSM2*/ + [31] = {0xFF802004U, 0x0000000FU}, /* RGIDR_MODID[660]:ARSN1*/ + [32] = {0xFF802008U, 0x0000000FU}, /* RGIDR_MODID[661]:ARSN2*/ + [33] = {0xE7752004U, 0x0000000FU}, /* RGIDR_MODID[670]:ARSD01*/ + [34] = {0xE7752008U, 0x0000000FU}, /* RGIDR_MODID[671]:ARSD02*/ + [35] = {0xE775203CU, 0x0000000FU}, /* RGIDR_MODID[683]:ARSP01*/ + [36] = {0xE7752040U, 0x0000000FU}, /* RGIDR_MODID[684]:ARSP02*/ + [37] = {0xFE682004U, 0x0000000FU}, /* RGIDR_MODID[766]:ARVC1*/ + [38] = {0xFE682008U, 0x0000000FU}, /* RGIDR_MODID[767]:ARVC2*/ + [39] = {0xFEBE2008U, 0x0000000FU}, /* RGIDR_MODID[801]:ARVI11*/ + [40] = {0xFEBE200CU, 0x0000000FU}, /* RGIDR_MODID[802]:ARVI12*/ + [41] = {0xFEBF2004U, 0x0000000FU}, /* RGIDR_MODID[852]:ARVI1*/ + [42] = {0xFEBF2008U, 0x0000000FU}, /* RGIDR_MODID[853]:ARVI2*/ + [43] = {0xE7B12004U, 0x0000000FU}, /* RGIDR_MODID[882]:ARVIP01*/ + [44] = {0xE7B12008U, 0x0000000FU}, /* RGIDR_MODID[883]:ARVIP02*/ + [45] = {0xE7B42004U, 0x0000000FU}, /* RGIDR_MODID[914]:ARVIP11*/ + [46] = {0xE7B42008U, 0x0000000FU}, /* RGIDR_MODID[915]:ARVIP12*/ + [47] = {0xEB802004U, 0x0000000FU}, /* RGIDR_MODID[942]:ARDSP1*/ + [48] = {0xEB802008U, 0x0000000FU}, /* RGIDR_MODID[943]:ARDSP2*/ + [49] = {0xFFC82410U, 0x00000000U}, /* RGIDW_MODID[4]:ARRT01*/ + [50] = {0xFFC82414U, 0x00000000U}, /* RGIDW_MODID[5]:ARRT02*/ + [51] = {0xE6002448U, 0x00000000U}, /* RGIDW_MODID[42]:ARS01*/ + [52] = {0xE600244CU, 0x00000000U}, /* RGIDW_MODID[43]:ARS02*/ + [53] = {0xE7762428U, 0x00000000U}, /* RGIDW_MODID[106]:ARSP31*/ + [54] = {0xE776242CU, 0x00000000U}, /* RGIDW_MODID[107]:ARSP32*/ + [55] = {0xE7792404U, 0x00000000U}, /* RGIDW_MODID[121]:ARSP41*/ + [56] = {0xE7792408U, 0x00000000U}, /* RGIDW_MODID[122]:ARSP42*/ + [57] = {0xFE672404U, 0x00000000U}, /* RGIDW_MODID[165]:ARVC11*/ + [58] = {0xFE672408U, 0x00000000U}, /* RGIDW_MODID[166]:ARVC12*/ + [59] = {0xFEBD2404U, 0x00000000U}, /* RGIDW_MODID[178]:ARVI41*/ + [60] = {0xFEBD2408U, 0x00000000U}, /* RGIDW_MODID[179]:ARVI42*/ + [61] = {0xE6582540U, 0x00000000U}, /* RGIDW_MODID[245]:ARHC1*/ + [62] = {0xE6582544U, 0x00000000U}, /* RGIDW_MODID[246]:ARHC2*/ + [63] = {0xFF882404U, 0x00000000U}, /* RGIDW_MODID[261]:ARIMP01*/ + [64] = {0xFF882408U, 0x00000000U}, /* RGIDW_MODID[262]:ARIMP02*/ + [65] = {0xFD812404U, 0x00000000U}, /* RGIDW_MODID[297]:ARPV1*/ + [66] = {0xFD81240CU, 0x00000000U}, /* RGIDW_MODID[299]:ARPV2*/ + [67] = {0xE6622404U, 0x00000000U}, /* RGIDW_MODID[330]:ARRC1*/ + [68] = {0xE6622408U, 0x00000000U}, /* RGIDW_MODID[331]:ARRC2*/ + [69] = {0xFFC42460U, 0x00000000U}, /* RGIDW_MODID[368]:ARRD1*/ + [70] = {0xFFC42464U, 0x00000000U}, /* RGIDW_MODID[369]:ARRD2*/ + [71] = {0xFFC42484U, 0x00000000U}, /* RGIDW_MODID[377]:ARRT1*/ + [72] = {0xFFC42488U, 0x00000000U}, /* RGIDW_MODID[378]:ARRT2*/ + [75] = {0xFF862404U, 0x00000000U}, /* RGIDW_MODID[550]:ARSC1*/ + [76] = {0xFF862408U, 0x00000000U}, /* RGIDW_MODID[551]:ARSC2*/ + [73] = {0xFF862428U, 0x00000000U}, /* RGIDW_MODID[559]:ARSTM1*/ + [74] = {0xFF862438U, 0x00000000U}, /* RGIDW_MODID[563]:ARSTM2*/ + [77] = {0xE67C2404U, 0x00000000U}, /* RGIDW_MODID[605]:AXIARNMM*/ + [78] = {0xE67C240CU, 0x00000000U}, /* RGIDW_MODID[607]:ARSM1*/ + [79] = {0xE67C2410U, 0x00000000U}, /* RGIDW_MODID[608]:ARSM2*/ + [80] = {0xFF802404U, 0x00000000U}, /* RGIDW_MODID[659]:ARSN1*/ + [81] = {0xFF802408U, 0x00000000U}, /* RGIDW_MODID[660]:ARSN2*/ + [82] = {0xE7752404U, 0x00000000U}, /* RGIDW_MODID[669]:ARSD01*/ + [83] = {0xE7752408U, 0x00000000U}, /* RGIDW_MODID[670]:ARSD02*/ + [84] = {0xE775243CU, 0x00000000U}, /* RGIDW_MODID[682]:ARSP01*/ + [85] = {0xE7752440U, 0x00000000U}, /* RGIDW_MODID[683]:ARSP02*/ + [86] = {0xFE682404U, 0x00000000U}, /* RGIDW_MODID[765]:ARVC1*/ + [87] = {0xFE682408U, 0x00000000U}, /* RGIDW_MODID[766]:ARVC2*/ + [88] = {0xFEBE2408U, 0x00000000U}, /* RGIDW_MODID[800]:ARVI11*/ + [89] = {0xFEBE240CU, 0x00000000U}, /* RGIDW_MODID[801]:ARVI12*/ + [90] = {0xFEBF2404U, 0x00000000U}, /* RGIDW_MODID[851]:ARVI1*/ + [91] = {0xFEBF2408U, 0x00000000U}, /* RGIDW_MODID[852]:ARVI2*/ + [92] = {0xE7B12404U, 0x00000000U}, /* RGIDW_MODID[881]:ARVIP01*/ + [93] = {0xE7B12408U, 0x00000000U}, /* RGIDW_MODID[882]:ARVIP02*/ + [94] = {0xE7B42404U, 0x00000000U}, /* RGIDW_MODID[913]:ARVIP11*/ + [95] = {0xE7B42408U, 0x00000000U}, /* RGIDW_MODID[914]:ARVIP12*/ + [96] = {0xEB802404U, 0x00000000U}, /* RGIDW_MODID[941]:ARDSP1*/ + [97] = {0xEB802408U, 0x00000000U}, /* RGIDW_MODID[942]:ARDSP2*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +/* RAM protection setting for SECDIV[n]D_0 / SECCTRR[m]D_0 / SECCTRW[m]D_0 */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram0_protection_table[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM0_ICUMX_IPL_AREA] = {NOT_USED_VALUE, {0x0000FFFCU, 0x0000FFFEU}}, /* not used for address value */ + /* Area0 phys:0xE0000000-0xE003FFFF R:RGID0/1 W:RGID0 */ + [RTVRAM0_ICUMX_FW_AREA] = {RTVRAM0_AREA1_TOP, {0x0004FFFEU, 0x0004FFFEU}}, /* Area1 phys:0xE0040000-0xE00FFFFF R:RGID0 W:RGID0 */ + [2] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [3] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for SECDIV[n]D_1 / SECCTRR[m]D_1 / SECCTRW[m]D_1 */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM1_BLANK_AREA] = {NOT_USED_VALUE, {0x0000FFB6U, 0x0000FFB7U}}, /* not used for address value */ + /* Area0 phys:0xE2000000-0xE200FFFF R:RGID0/3/6 W:RGID3/6 */ + [RTVRAM1_EXTEND_CACHE_AREA] = {RTVRAM1_AREA1_TOP, {0x0000BFFFU, 0x0000BFFFU}}, /* Area1 phys:0xE2010000-0xE20FFFFF R:RGID14 W:RGID14 */ + [RTVRAM1_RTOS_AREA] = {RTVRAM1_AREA2_TOP, {0x0000FFF4U, 0x0000FFF5U}}, /* Area2 phys:0xE2100000-0xE3BFFFFF R:RGID0/1/3 W:RGID1/3 */ + [3] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for SPTDIVCR[n] / SPTRGNCR[n] / SPTSECCR[n] */ +const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX] = { + /* access Secure */ + /* address R | W R|W */ + [SYSTEM_RAM_CX_2ND_IPL] = {NOT_USED_VALUE, {0xFFD8FFD8U, 0x00000000U}}, /* not used for address value */ + /* + * Change the access permission from 0xFFCCFFCC to 0xFFCCFFCD + * if user want to enable protection of System Ram Area0. + */ + /* Area0 phys:0xE6300000-0xE635DFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [SYSTEM_RAM_SHARED_MEM] = {SYSTEM_RAM_AREA1_TOP, {0xFFD8FFD8U, 0x00000000U}}, /* Area1 phys:0xE635E000-0xE635FFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [2] = {SYSTEM_RAM_AREA2_TOP, {0xFFDAFFDAU, 0x00000000U}}, /* Area2 phys:0xE6360000-0xE63FFFFF R:RGID0/2/5 W:RGID0/2/5 */ + [3] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for DPTDIVCR[n] / DPTRGNCR[n] / DPTSECCR[n] */ +const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX] = { + /* access secure */ + /* address R | W R|W */ + [RTVRAM1_EXTEND_AREA] = {NOT_USED_VALUE, {0xBFFFBFFFU, 0x00000000U}}, /* not used for address value */ + /* Area0 phys:0x04_00000000-0x04_01BFFFFF R:RGID14 W:RGID14 */ + [CR_FW_SHARED_AREA] = {DRAM_ADDR_AREA1, {0xFFBCFFBCU, 0x00000000U}}, /* Area1 phys:0x04_01C00000-0x04_01CFFFFF R:RGID0/1/6 W:RGID0/1/6 */ + /* This secure setting is added by sdram_protection() in loader_main function. */ + [SDRAM_BLANK_AREA] = {DRAM_ADDR_AREA2, {0xFF90FF90U, 0x00000000U}}, /* Area2:OPTEE_DISABLE phys:0x04_01D00000-0x04_063FFFFF + * Area2:OPTEE_ENABLE phys:0x04_01D00000-0x04_040FFFFF + * R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFBFFF9U, 0x00000404U}}, /* Area3 phys:0x04_06400000-0x04_0643FFFF R:RGID2 W:RGID1/2 */ + [SDRAM_PUBLIC_AREA] = {DRAM_ADDR_AREA4, {0xFF90FF90U, 0x00000000U}}, /* Area4 phys:0x04_06440000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA5, {0xFFB9FFB9U, 0x00000000U}}, /* Area5 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA6, {0xFFB1FFB1U, 0x00000000U}}, /* Area6 phys:0x04_08000000-0x04_1DBFFFFF R:RGID1/2/3/6 W:RGID1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA7, {0xFFB9FFB9U, 0x00000000U}}, /* Area7 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFBDFFBDU, 0x00000000U}}, /* Area8 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFDDFFDDU, 0x00000000U}}, /* Area9 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA11,{0xBF90BF90U, 0x00000000U}}, /* Area11 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA12,{0xFFFFFFFFU, 0x00000000U}}, /* Area12 phys:0x05_00000000-0x05_FFFFFFFF */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFF9FFF9U, 0x00000000U}}, /* Area13 phys:0x06_00000000-0x06_FFFFFFFF R:RGID1/2 W:RGID1/2 */ + [14] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [16] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +#else + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFAFFFAU, 0x00000404U}}, /* Area3 phys:0x04_04100000-0x04_063FFFFF R:RGID0/2 W:RGID0/2 */ + [SDRAM_PROTECT_AREA2] = {DRAM_ADDR_AREA4, {0xFFFBFFF9U, 0x00000404U}}, /* Area4 phys:0x04_06400000-0x04_0643FFFF R:RGID2 W:RGID1/2 */ + [SDRAM_BLANK_AREA2] = {DRAM_ADDR_AREA5, {0xFF90FF90U, 0x00000000U}}, /* Area5 phys:0x04_06440000-0x04_07DFFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [OPTEE_SHARED_AREA] = {DRAM_ADDR_AREA6, {0xFFFBFFFBU, 0x00000000U}}, /* Area6 phys:0x04_07E00000-0x04_07EFFFFF R:RGID2 W:RGID2 */ + [SDRAM_BLANK_AREA3] = {DRAM_ADDR_AREA7, {0xFF90FF90U, 0x00000000U}}, /* Area7 phys:0x04_07F00000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFB9FFB9U, 0x00000000U}}, /* Area8 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFB1FFB1U, 0x00000000U}}, /* Area9 phys:0x04_08000000-0x04_1DBFFFFF R:RGID1/2/3/6 W:RGID1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA11,{0xFFBDFFBDU, 0x00000000U}}, /* Area11 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA12,{0xFFDDFFDDU, 0x00000000U}}, /* Area12 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFB9FFB9U, 0x00000000U}}, /* Area13 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA14,{0xBF90BF90U, 0x00000000U}}, /* Area14 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA15,{0xFFFFFFFFU, 0x00000000U}}, /* Area15 phys:0x05_00000000-0x05_FFFFFFFF */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA16,{0xFFF9FFF9U, 0x00000000U}}, /* Area16 phys:0x06_00000000-0x06_FFFFFFFF R:RGID1/2 W:RGID1/2 */ +#endif /*OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + [17] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [18] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [19] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [20] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [21] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [22] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [23] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [24] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [25] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [26] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [27] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [28] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [29] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [30] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [31] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [32] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [33] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [34] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [35] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [36] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [37] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [38] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [39] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [40] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [41] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [42] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [43] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [44] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [45] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [46] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [47] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [48] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [49] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [50] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [51] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [52] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [53] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [54] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [55] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [56] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [57] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [58] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [59] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [60] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [61] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [62] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [63] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +const REGION_ID_SETTING_TABLE g_imp_rgid_m_tbl[IMP_MASTER_MAX] = { + [0] = {0xFFA8E270U, 0x00010202U}, /* SPMI BMATTR00 */ + [1] = {0xFFA8E274U, 0x00010202U}, /* SPMI BMATTR01 */ + [2] = {0xFFA8E278U, 0x00010202U}, /* SPMI BMATTR02 */ + [3] = {0xFFA8E27CU, 0x00010202U}, /* SPMI BMATTR03 */ + [4] = {0xFFA8E280U, 0x00010202U}, /* SPMI BMATTR04 */ + [5] = {0xFFA8E284U, 0x00010202U}, /* SPMI BMATTR05 */ + [6] = {0xFFA8E288U, 0x00010202U}, /* SPMI BMATTR06 */ + [7] = {0xFFA8E28CU, 0x00010202U}, /* SPMI BMATTR07 */ + [8] = {0xFFA8E290U, 0x00010202U}, /* SPMI BMATTR08 */ + [9] = {0xFFA8E294U, 0x00010202U}, /* SPMI BMATTR09 */ + [10] = {0xFFA8E298U, 0x00010202U}, /* SPMI BMATTR10 */ + [11] = {0xFFA8E29CU, 0x00010202U}, /* SPMI BMATTRSP0 */ + [12] = {0xFFAB2270U, 0x00010202U}, /* SPMC BMATTR00 */ + [13] = {0xFFAB2274U, 0x00010202U}, /* SPMC BMATTR01 */ + [14] = {0xFFAB2278U, 0x00010202U}, /* SPMC BMATTR02 */ + [15] = {0xFFAB227CU, 0x00010202U}, /* SPMC BMATTR03 */ + [16] = {0xFFAB2280U, 0x00010202U}, /* SPMC BMATTR04 */ + [17] = {0xFFAB2284U, 0x00010202U}, /* SPMC BMATTR05 */ + [18] = {0xFFAB2288U, 0x00010202U}, /* SPMC BMATTR06 */ +}; + +const REGION_ID_SETTING_TABLE g_imp_rgid_s_tbl[IMP_SLAVE_MAX] = { + [0] = {0xFF902100U, 0x004E004FU}, /* IMPSLV RCR0 */ + [1] = {0xFF902108U, 0x004E004FU}, /* IMPSLV RCR2 */ + [2] = {0xFFAB2100U, 0x004E004FU}, /* SPMC RCR0 */ + [3] = {0xFFAB2110U, 0x004E004FU}, /* SPMC RC00 */ + [4] = {0xFFAB2114U, 0x004E004FU}, /* SPMC RC01 */ + [5] = {0xFFAB2118U, 0x004E004FU}, /* SPMC RC02 */ + [6] = {0xFFAB2200U, 0x004E004FU}, /* SPMC RCB0 */ + [7] = {0xFFAB2204U, 0x004E004FU}, /* SPMC RCB1 */ + [8] = {0xFFAB2208U, 0x004E004FU}, /* SPMC RCB2 */ + [9] = {0xFFAB220CU, 0x004E004FU}, /* SPMC RCB3 */ + [10] = {0xFFAB2210U, 0x004E004FU}, /* SPMC RCB4 */ + [11] = {0xFFAB2104U, 0x004E004FU}, /* SPMC RCR1 */ + [12] = {0xFFA8E100U, 0x004E004FU}, /* SPMI RCR0 */ + [13] = {0xFFA8E110U, 0x004E004FU}, /* SPMI RC00 */ + [14] = {0xFFA8E114U, 0x004E004FU}, /* SPMI RC01 */ + [15] = {0xFFA8E118U, 0x004E004FU}, /* SPMI RC02 */ + [16] = {0xFFA8E11CU, 0x004E004FU}, /* SPMI RC03 */ + [17] = {0xFFA8E120U, 0x004E004FU}, /* SPMI RC04 */ + [18] = {0xFFA8E124U, 0x004E004FU}, /* SPMI RC05 */ + [19] = {0xFFA8E128U, 0x004E004FU}, /* SPMI RC06 */ + [20] = {0xFFA8E12CU, 0x004E004FU}, /* SPMI RC07 */ + [21] = {0xFFA8E130U, 0x004E004FU}, /* SPMI RC08 */ + [22] = {0xFFA8E134U, 0x004E004FU}, /* SPMI RC09 */ + [23] = {0xFFA8E138U, 0x004E004FU}, /* SPMI RC10 */ + [24] = {0xFFA8E13CU, 0x004E004FU}, /* SPMI RC11 */ + [25] = {0xFFA8E140U, 0x004E004FU}, /* SPMI RC12 */ + [26] = {0xFFA8E144U, 0x004E004FU}, /* SPMI RC13 */ + [27] = {0xFFA8E200U, 0x004E004FU}, /* SPMI RCB0 */ + [28] = {0xFFA8E204U, 0x004E004FU}, /* SPMI RCB1 */ + [29] = {0xFFA8E208U, 0x004E004FU}, /* SPMI RCB2 */ + [30] = {0xFFA8E20CU, 0x004E004FU}, /* SPMI RCB3 */ + [31] = {0xFFA8E210U, 0x004E004FU}, /* SPMI RCB4 */ + [32] = {0xFFA8E214U, 0x004E004FU}, /* SPMI RCB5 */ + [33] = {0xFFA8E218U, 0x004E004FU}, /* SPMI RCB6 */ + [34] = {0xFFA8E21CU, 0x004E004FU}, /* SPMI RCB7 */ + [35] = {0xFFA8E104U, 0x004E004FU}, /* SPMI RCR1 */ + [36] = {0xFF902110U, 0x004E004FU}, /* IMPSLV RC00 */ + [37] = {0xFF902104U, 0x004E004FU}, /* IMPSLV RCR1 */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX] = { + [0] = {0xEEE80570U, 0x00000002U}, /* IMRGID_IPMMU_VI0 */ + [1] = {0xEEEC0570U, 0x00000002U}, /* IMRGID_IPMMU_VI1 */ + [2] = {0xEEDC0570U, 0x00000002U}, /* IMRGID_IPMMU_VC0 */ + [3] = {0xEED80570U, 0x00000002U}, /* IMRGID_IPMMU_IR */ + [4] = {0xEE480570U, 0x00000001U}, /* IMRGID_IPMMU_RT0 */ + [5] = {0xEE4C0570U, 0x00000001U}, /* IMRGID_IPMMU_RT1 */ + [6] = {0xEED00570U, 0x00000001U}, /* IMRGID_IPMMU_DS0 */ + [7] = {0xEED40570U, 0x00000001U}, /* IMRGID_IPMMU_HSC */ + [8] = {0xEEF00570U, 0x00000002U}, /* IMRGID_IPMMU_VIP0 */ + [9] = {0xEEF40570U, 0x00000002U}, /* IMRGID_IPMMU_VIP1 */ + [10] = {0xEEE00570U, 0x00000002U}, /* IMRGID_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX] = { + [0] = {0xEEE80578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI0 */ + [1] = {0xEEEC0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI1 */ + [2] = {0xEEDC0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VC0 */ + [3] = {0xEED80578U, 0x00000001U}, /* IMSECGRP_IPMMU_IR */ + [4] = {0xEE480578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT0 */ + [5] = {0xEE4C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT1 */ + [6] = {0xEED00578U, 0x00000001U}, /* IMSECGRP_IPMMU_DS0 */ + [7] = {0xEED40578U, 0x00000001U}, /* IMSECGRP_IPMMU_HSC */ + [8] = {0xEEF00578U, 0x00000001U}, /* IMSECGRP_IPMMU_VIP0 */ + [9] = {0xEEF40578U, 0x00000001U}, /* IMSECGRP_IPMMU_VIP1 */ + [10] = {0xEEE00578U, 0x00000001U}, /* IMSECGRP_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX] = { + [0] = {0xEEE80574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI0 */ + [1] = {0xEEEC0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI1 */ + [2] = {0xEEDC0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VC0 */ + [3] = {0xEED80574U, 0x00000002U}, /* IMRGIDEN_IPMMU_IR */ + [4] = {0xEE480574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT0 */ + [5] = {0xEE4C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT1 */ + [6] = {0xEED00574U, 0x00000002U}, /* IMRGIDEN_IPMMU_DS0 */ + [7] = {0xEED40574U, 0x00000002U}, /* IMRGIDEN_IPMMU_HSC */ + [8] = {0xEEF00574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VIP0 */ + [9] = {0xEEF40574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VIP1 */ + [10] = {0xEEE00574U, 0x00000002U}, /* IMRGIDEN_IPMMU_3DG */ +}; + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4m.c b/IPL/Customer/Mobis/V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4m.c new file mode 100644 index 0000000..501ef62 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4m.c @@ -0,0 +1,3020 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table + ******************************************************************************/ +/****************************************************************************** + * @file rgidcnf_tbl_v4m.c + * - Version : 0.09 + * @brief Configuration table for V4M. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + * : 15.09.2023 0.02 Update setting table according to + * HWUM Rev.0.50. + * : 10.10.2023 0.03 Removed unimplemented registers. + * : 23.01.2024 0.04 Added RAM protection table. + * Update Region ID settings. + * : 07.02.2024 0.05 Update System RAM protection setting Area0. + * : 11.10.2024 0.06 Updated Region ID and RAM protection setting + * for QNX. + * : 05.12.2024 0.07 Update RAM protection settings for ICCOM + * memory area (SDRAM Area5). + * Update Region ID settings for VSPD and VSPX. + * Update Region ID settings for IPMMU. + * Update RAM protection setting. + * : 16.12.2024 0.08 Updated Region ID setting. + * Updated Region ID setting and RAM protection + * setting for booting CR52 3 cores. + * Update Region ID settings for ISP ch1. + * Update Region ID settings for PCI1. + * Added IPMMU Region ID table. + * : 26.05.2025 0.09 Updated RAM protection settings for + * protection area. + *****************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include +#endif +#include +#include +#include "ram_protection.h" + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_m_tbl" +#else +__attribute__ ((section(".rgid_m_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_master_tbl[] = { + [0] = {0xE6581000U, 0x00000002U}, /* RGIDM_MODID[0]:PCI0 */ + [1] = {0xE6581020U, 0x00000002U}, /* RGIDM_MODID[1]:PCI1 */ + [2] = {0xE6581010U, 0x00000002U}, /* RGIDM_MODID[3]:AVB0 */ + [3] = {0xE6581014U, 0x00000001U}, /* RGIDM_MODID[4]:AVB1 */ + [4] = {0xE6581018U, 0x00000001U}, /* RGIDM_MODID[5]:AVB2 */ + [5] = {0xE662100CU, 0x00000000U}, /* RGIDM_MODID[6]:DCLS_ICUMX */ + [6] = {0xE6621010U, 0x00000000U}, /* RGIDM_MODID[7]:ICUMX */ + [7] = {0xE6621014U, 0x00000000U}, /* RGIDM_MODID[8]:SDMAC_ICUMX */ + [8] = {0xFFC41018U, 0x00000001U}, /* RGIDM_MODID[9]:CR52SS0 */ + [9] = {0xFFC4105CU, 0x00000001U}, /* RGIDM_MODID[10]:CR52SS1 */ + [10] = {0xFFC41060U, 0x00000006U}, /* RGIDM_MODID[11]:CR52SS2 */ + [11] = {0xFFC4101CU, 0x00000003U}, /* RGIDM_MODID[12]:CSD */ + [12] = {0xFFC41024U, 0x00000002U}, /* RGIDM_MODID[13]:INTAP0 */ + [13] = {0xFF861018U, 0x00000002U}, /* RGIDM_MODID[14]:FBABUSTOP0 */ + [14] = {0xE7751020U, 0x00000002U}, /* RGIDM_MODID[15]:SDHI0 */ + [15] = {0xE7751010U, 0x00000001U}, /* RGIDM_MODID[16]:FRAY */ + [16] = {0xFF811000U, 0x00000002U}, /* RGIDM_MODID[17]:AXMM2AXSTM */ + [17] = {0xFF811004U, 0x00000003U}, /* RGIDM_MODID[18]:CSDE0 */ + [18] = {0xFF811008U, 0x00000003U}, /* RGIDM_MODID[19]:CSDE1 */ + [19] = {0xFFC41020U, 0x00000003U}, /* RGIDM_MODID[20]:CSDE2 */ + [20] = {0xFF881004U, 0x00000002U}, /* RGIDM_MODID[21]:FBABUSIR0 */ + [21] = {0xFF881008U, 0x00000002U}, /* RGIDM_MODID[22]:FBABUSIR1 */ + [22] = {0xFF88100CU, 0x00000002U}, /* RGIDM_MODID[23]:FBABUSIR2 */ + [23] = {0xFF881010U, 0x00000002U}, /* RGIDM_MODID[24]:FBABUSIR3 */ + [24] = {0xFD811014U, 0x00000002U}, /* RGIDM_MODID[25]:RGX0 */ + [25] = {0xFE681004U, 0x00000002U}, /* RGIDM_MODID[26]:FBABUSVC */ + [26] = {0xFE681010U, 0x00000002U}, /* RGIDM_MODID[27]:IMR00 */ + [27] = {0xFE681014U, 0x00000002U}, /* RGIDM_MODID[28]:IMR01 */ + [28] = {0xFE681024U, 0x00000002U}, /* RGIDM_MODID[29]:IMR10 */ + [29] = {0xFE681028U, 0x00000002U}, /* RGIDM_MODID[30]:IMR11 */ + [30] = {0xFE681040U, 0x00000002U}, /* RGIDM_MODID[31]:IMS0 */ + [31] = {0xFE681044U, 0x00000002U}, /* RGIDM_MODID[32]:IMS1 */ + [32] = {0xFE681048U, 0x00000005U}, /* RGIDM_MODID[33]:IV1ES */ + [33] = {0xFEBE1000U, 0x00000002U}, /* RGIDM_MODID[34]:DSITLINK0 */ + [34] = {0xFEBE1008U, 0x00000002U}, /* RGIDM_MODID[36]:FBABUSVIO */ + [35] = {0xFEBE1014U, 0x00000002U}, /* RGIDM_MODID[37]:FCPVD0 */ + [36] = {0xFEBE101CU, 0x00000002U}, /* RGIDM_MODID[38]:FCPVX0 */ + [37] = {0xFEBF1020U, 0x00000002U}, /* RGIDM_MODID[39]:ISP00 */ + [38] = {0xFEBF1024U, 0x00000002U}, /* RGIDM_MODID[40]:ISP01 */ + [39] = {0xFEBF1000U, 0x00000002U}, /* RGIDM_MODID[41]:ISP02 */ + [40] = {0xFEBF1004U, 0x00000002U}, /* RGIDM_MODID[42]:ISP03 */ + [41] = {0xFEBF1008U, 0x00000002U}, /* RGIDM_MODID[43]:ISP04 */ + [42] = {0xFEBF1010U, 0x00000002U}, /* RGIDM_MODID[44]:VIN0 */ + [43] = {0xFEBF1014U, 0x00000002U}, /* RGIDM_MODID[45]:VIN1 */ + [44] = {0xE7B11004U, 0x00000002U}, /* RGIDM_MODID[46]:FBABUSVIP0 */ + [45] = {0xE7B11010U, 0x00000002U}, /* RGIDM_MODID[47]:SMPO */ + [46] = {0xE7B11018U, 0x00000002U}, /* RGIDM_MODID[48]:SMPS */ + [47] = {0xE7B1101CU, 0x00000002U}, /* RGIDM_MODID[49]:UMFL */ + [48] = {0xFF881018U, 0x00000002U}, /* RGIDM_MODID[50]:DSP00 */ + [49] = {0xFF881024U, 0x00000002U}, /* RGIDM_MODID[51]:DSP01 */ + [50] = {0xFF881038U, 0x00000002U}, /* RGIDM_MODID[52]:DSP10 */ + [51] = {0xFF881044U, 0x00000002U}, /* RGIDM_MODID[53]:DSP11 */ + [52] = {0xFF881048U, 0x00000002U}, /* RGIDM_MODID[54]:DSP20 */ + [53] = {0xFF88104CU, 0x00000002U}, /* RGIDM_MODID[55]:DSP21 */ + [54] = {0xFF881050U, 0x00000002U}, /* RGIDM_MODID[56]:DSP30 */ + [55] = {0xFF881054U, 0x00000002U}, /* RGIDM_MODID[57]:DSP31 */ + [56] = {0xFF881058U, 0x00000002U}, /* RGIDM_MODID[58]:IMP0R100 */ + [57] = {0xFF88105CU, 0x00000002U}, /* RGIDM_MODID[59]:IMP0R101 */ + [58] = {0xFF881060U, 0x00000002U}, /* RGIDM_MODID[60]:IMP0R102 */ + [59] = {0xFF881064U, 0x00000002U}, /* RGIDM_MODID[61]:IMP0R103 */ + [60] = {0xFF881068U, 0x00000002U}, /* RGIDM_MODID[62]:IMP0R104 */ + [61] = {0xFF88106CU, 0x00000002U}, /* RGIDM_MODID[63]:IMP0R105 */ + [62] = {0xFF881070U, 0x00000002U}, /* RGIDM_MODID[64]:IMP0R106 */ + [63] = {0xFF881074U, 0x00000002U}, /* RGIDM_MODID[65]:IMP0R107 */ + [64] = {0xFF881078U, 0x00000002U}, /* RGIDM_MODID[66]:IMP0R108 */ + [65] = {0xFF88107CU, 0x00000002U}, /* RGIDM_MODID[67]:IMP0R109 */ + [66] = {0xFF881080U, 0x00000002U}, /* RGIDM_MODID[68]:IMP0R200 */ + [67] = {0xFF881084U, 0x00000002U}, /* RGIDM_MODID[69]:IMP0R201 */ + [68] = {0xFF881088U, 0x00000002U}, /* RGIDM_MODID[70]:IMP0R202 */ + [69] = {0xFF88108CU, 0x00000002U}, /* RGIDM_MODID[71]:IMP0W100 */ + [70] = {0xFF881090U, 0x00000002U}, /* RGIDM_MODID[72]:IMP0W101 */ + [71] = {0xFF881094U, 0x00000002U}, /* RGIDM_MODID[73]:IMP0W102 */ + [72] = {0xFF881098U, 0x00000002U}, /* RGIDM_MODID[74]:IMP0W103 */ + [73] = {0xFF88109CU, 0x00000002U}, /* RGIDM_MODID[75]:IMP0W104 */ + [74] = {0xFF8810A0U, 0x00000002U}, /* RGIDM_MODID[76]:IMP0W105 */ + [75] = {0xFF8810A4U, 0x00000002U}, /* RGIDM_MODID[77]:IMP0W106 */ + [76] = {0xFF8810A8U, 0x00000002U}, /* RGIDM_MODID[78]:IMP0W107 */ + [77] = {0xFF8810ACU, 0x00000002U}, /* RGIDM_MODID[79]:IMP0W108 */ + [78] = {0xFF8810B0U, 0x00000002U}, /* RGIDM_MODID[80]:IMP0W109 */ + [79] = {0xFF8810B4U, 0x00000002U}, /* RGIDM_MODID[81]:IMP0W200 */ + [80] = {0xFF8810B8U, 0x00000002U}, /* RGIDM_MODID[82]:IMP0W201 */ + [81] = {0xFF8810BCU, 0x00000002U}, /* RGIDM_MODID[83]:IMP0W202 */ + [82] = {0xE67BF500U, 0x0000000EU}, /* RGIDM_MODID[84]:VRAM_R */ + [83] = {0xE67BF504U, 0x0000000EU}, /* RGIDM_MODID[85]:VRAM_W */ + [84] = {0xE7B11008U, 0x00000002U}, /* RGIDM_MODID[86]:PAP */ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_r_tbl" +#else +__attribute__ ((section(".rgid_r_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_read_tbl[] = { + [0] = {0xFFC82000U, 0x0000000FU}, /* RGIDR_MODID[0]:ARMGC0*/ + [1] = {0xFFC82004U, 0x0000000FU}, /* RGIDR_MODID[1]:ARMGC1*/ + [2] = {0xFFC82008U, 0x00000000U}, /* RGIDR_MODID[2]:ARMGC2*/ + [3] = {0xFFC8200CU, 0x0000000FU}, /* RGIDR_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDR_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDR_MODID[5]:ARRT02*/ + [4] = {0xFFC82018U, 0x0000000FU}, /* RGIDR_MODID[6]:ARRT03*/ + [5] = {0xFFC8201CU, 0x0000000FU}, /* RGIDR_MODID[7]:ARRT04*/ + [6] = {0xFFC82020U, 0x0000000FU}, /* RGIDR_MODID[8]:ARRT05*/ + [7] = {0xFFC82024U, 0x0000000FU}, /* RGIDR_MODID[9]:ARRT06*/ + [8] = {0xFFC82028U, 0x0000000FU}, /* RGIDR_MODID[10]:ARRT07*/ + [9] = {0xFFC8202CU, 0x00000000U}, /* RGIDR_MODID[11]:ARRT08*/ + [10] = {0xFFC82030U, 0x00000001U}, /* RGIDR_MODID[12]:LIFEC0*/ + [11] = {0xFFC82034U, 0x0000000EU}, /* RGIDR_MODID[13]:SWDT*/ + [12] = {0xFFC82038U, 0x0000006EU}, /* RGIDR_MODID[14]:TMU0*/ + [13] = {0xFFC8203CU, 0x0000000EU}, /* RGIDR_MODID[15]:WDT*/ + [14] = {0xFFC82040U, 0x0000000EU}, /* RGIDR_MODID[16]:WWDT0*/ + [15] = {0xFFC82044U, 0x0000000EU}, /* RGIDR_MODID[17]:WWDT1*/ + [16] = {0xFFC82048U, 0x0000000EU}, /* RGIDR_MODID[18]:WWDT2*/ + [17] = {0xFFC8204CU, 0x0000000EU}, /* RGIDR_MODID[19]:WWDT3*/ + [18] = {0xFFC82050U, 0x0000000EU}, /* RGIDR_MODID[20]:WWDT4*/ + [19] = {0xFFC82054U, 0x0000000EU}, /* RGIDR_MODID[21]:WWDT5*/ + [20] = {0xFFC82058U, 0x0000000EU}, /* RGIDR_MODID[22]:WWDT6*/ + [21] = {0xFFC82068U, 0x0000000FU}, /* RGIDR_MODID[23]:ECMRT3*/ + [22] = {0xE6002004U, 0x0000000FU}, /* RGIDR_MODID[24]:APMU0*/ + [23] = {0xE6002008U, 0x00000002U}, /* RGIDR_MODID[25]:APMU1*/ + [24] = {0xE600200CU, 0x00000000U}, /* RGIDR_MODID[26]:APMU10*/ + [25] = {0xE6002010U, 0x00000000U}, /* RGIDR_MODID[27]:APMU11*/ + [26] = {0xE6002014U, 0x00000000U}, /* RGIDR_MODID[28]:APMU12*/ + [27] = {0xE6002018U, 0x00000000U}, /* RGIDR_MODID[29]:APMU13*/ + [28] = {0xE600201CU, 0x00000000U}, /* RGIDR_MODID[30]:APMU14*/ + [29] = {0xE6002020U, 0x00000000U}, /* RGIDR_MODID[31]:APMU15*/ + [30] = {0xE6002024U, 0x00000004U}, /* RGIDR_MODID[32]:APMU2*/ + [31] = {0xE6002028U, 0x00000004U}, /* RGIDR_MODID[33]:APMU3*/ + [32] = {0xE600202CU, 0x00000000U}, /* RGIDR_MODID[34]:APMU4*/ + [33] = {0xE6002030U, 0x00000000U}, /* RGIDR_MODID[35]:APMU5*/ + [34] = {0xE6002034U, 0x00000000U}, /* RGIDR_MODID[36]:APMU6*/ + [35] = {0xE6002038U, 0x00000000U}, /* RGIDR_MODID[37]:APMU7*/ + [36] = {0xE600203CU, 0x00000000U}, /* RGIDR_MODID[38]:APMU8*/ + [37] = {0xE6002040U, 0x00000000U}, /* RGIDR_MODID[39]:APMU9*/ + [38] = {0xE6002044U, 0x0000000FU}, /* RGIDR_MODID[40]:ARS00*/ + /* After setting */ /* RGIDR_MODID[41]:ARS01*/ + /* After setting */ /* RGIDR_MODID[42]:ARS02*/ + [39] = {0xE6002050U, 0x0000000FU}, /* RGIDR_MODID[43]:ARS03*/ + [40] = {0xE6002054U, 0x0000000FU}, /* RGIDR_MODID[44]:ARS04*/ + [41] = {0xE6002058U, 0x0000000FU}, /* RGIDR_MODID[45]:ARS05*/ + [42] = {0xE600205CU, 0x0000000FU}, /* RGIDR_MODID[46]:ARS06*/ + [43] = {0xE6002060U, 0x0000000FU}, /* RGIDR_MODID[47]:ARS07*/ + [44] = {0xE6002064U, 0x00000000U}, /* RGIDR_MODID[48]:ARS08*/ + [45] = {0xE6002068U, 0x0000000EU}, /* RGIDR_MODID[49]:CMT0*/ + [46] = {0xE600206CU, 0x0000000EU}, /* RGIDR_MODID[50]:CMT1*/ + [47] = {0xE6002070U, 0x0000000EU}, /* RGIDR_MODID[51]:CMT2*/ + [48] = {0xE6002074U, 0x0000000EU}, /* RGIDR_MODID[52]:CMT3*/ + [49] = {0xE6002078U, 0x0000000AU}, /* RGIDR_MODID[53]:CKM*/ + [50] = {0xE600207CU, 0x0000000EU}, /* RGIDR_MODID[54]:DBE*/ + [51] = {0xE6002080U, 0x0000000EU}, /* RGIDR_MODID[55]:IRQC*/ + [52] = {0xE6002084U, 0x0000000FU}, /* RGIDR_MODID[56]:ECMPS0*/ + [53] = {0xE6002088U, 0x0000000BU}, /* RGIDR_MODID[57]:OTP0*/ + [54] = {0xE600208CU, 0x0000000FU}, /* RGIDR_MODID[58]:OTP1*/ + [55] = {0xE600209CU, 0x0000000EU}, /* RGIDR_MODID[59]:SCMT*/ + [56] = {0xE60020A8U, 0x0000004EU}, /* RGIDR_MODID[60]:TSC1*/ + [57] = {0xE60020ACU, 0x0000004EU}, /* RGIDR_MODID[61]:TSC2*/ + [58] = {0xE60020B8U, 0x00000006U}, /* RGIDR_MODID[62]:UCMT*/ + [59] = {0xE6002100U, 0x0000006FU}, /* RGIDR_MODID[63]:CPG0*/ + [60] = {0xE6002104U, 0x0000000AU}, /* RGIDR_MODID[64]:CPG1*/ + [61] = {0xE6002108U, 0x0000004EU}, /* RGIDR_MODID[65]:CPG2*/ + [62] = {0xE600210CU, 0x00000028U}, /* RGIDR_MODID[66]:CPG3*/ + [63] = {0xE6002110U, 0x0000006FU}, /* RGIDR_MODID[67]:PFC00*/ + [64] = {0xE6002114U, 0x0000000AU}, /* RGIDR_MODID[68]:PFC01*/ + [65] = {0xE6002118U, 0x0000004EU}, /* RGIDR_MODID[69]:PFC02*/ + [66] = {0xE600211CU, 0x00000028U}, /* RGIDR_MODID[70]:PFC03*/ + [67] = {0xE6002120U, 0x0000006FU}, /* RGIDR_MODID[71]:PFC10*/ + [68] = {0xE6002124U, 0x0000000AU}, /* RGIDR_MODID[72]:PFC11*/ + [69] = {0xE6002128U, 0x0000004EU}, /* RGIDR_MODID[73]:PFC12*/ + [70] = {0xE600212CU, 0x00000028U}, /* RGIDR_MODID[74]:PFC13*/ + [71] = {0xE6002130U, 0x0000006FU}, /* RGIDR_MODID[75]:PFC20*/ + [72] = {0xE6002134U, 0x0000000AU}, /* RGIDR_MODID[76]:PFC21*/ + [73] = {0xE6002138U, 0x0000004EU}, /* RGIDR_MODID[77]:PFC22*/ + [74] = {0xE600213CU, 0x00000028U}, /* RGIDR_MODID[78]:PFC23*/ + [75] = {0xE6002150U, 0x0000006FU}, /* RGIDR_MODID[79]:PFCS0*/ + [76] = {0xE6002154U, 0x0000000AU}, /* RGIDR_MODID[80]:PFCS1*/ + [77] = {0xE6002158U, 0x0000004EU}, /* RGIDR_MODID[81]:PFCS2*/ + [78] = {0xE600215CU, 0x00000028U}, /* RGIDR_MODID[82]:PFCS3*/ + [79] = {0xE6002160U, 0x0000006FU}, /* RGIDR_MODID[83]:RESET0*/ + [80] = {0xE6002164U, 0x0000000AU}, /* RGIDR_MODID[84]:RESET1*/ + [81] = {0xE6002168U, 0x0000004EU}, /* RGIDR_MODID[85]:RESET2*/ + [82] = {0xE600216CU, 0x00000028U}, /* RGIDR_MODID[86]:RESET3*/ + [83] = {0xE6002170U, 0x0000006FU}, /* RGIDR_MODID[87]:SYS0*/ + [84] = {0xE6002174U, 0x0000000AU}, /* RGIDR_MODID[88]:SYS1*/ + [85] = {0xE6002178U, 0x0000004EU}, /* RGIDR_MODID[89]:SYS2*/ + [86] = {0xE600217CU, 0x00000028U}, /* RGIDR_MODID[90]:SYS3*/ + [87] = {0xE7762000U, 0x0000000EU}, /* RGIDR_MODID[91]:DMAMSI0*/ + [88] = {0xE7762004U, 0x0000000EU}, /* RGIDR_MODID[92]:DMAMSI1*/ + [89] = {0xE7762008U, 0x0000000EU}, /* RGIDR_MODID[93]:DMAMSI2*/ + [90] = {0xE776200CU, 0x0000000EU}, /* RGIDR_MODID[94]:DMAMSI3*/ + [91] = {0xE7762010U, 0x0000000EU}, /* RGIDR_MODID[95]:DMAMSI4*/ + [92] = {0xE7762014U, 0x0000000EU}, /* RGIDR_MODID[96]:DMAMSI5*/ + [93] = {0xE7762018U, 0x0000000FU}, /* RGIDR_MODID[97]:ECMSP3*/ + [94] = {0xE7762024U, 0x0000000FU}, /* RGIDR_MODID[98]:ARSP30*/ + /* After setting */ /* RGIDR_MODID[99]:ARSP31*/ + /* After setting */ /* RGIDR_MODID[100]:ARSP32*/ + [95] = {0xE7762030U, 0x0000000FU}, /* RGIDR_MODID[101]:ARSP33*/ + [96] = {0xE7762034U, 0x0000000FU}, /* RGIDR_MODID[102]:ARSP34*/ + [97] = {0xE7762038U, 0x0000000FU}, /* RGIDR_MODID[103]:ARSP35*/ + [98] = {0xE776203CU, 0x0000000FU}, /* RGIDR_MODID[104]:ARSP36*/ + [99] = {0xE7762040U, 0x0000000FU}, /* RGIDR_MODID[105]:ARSP37*/ + [100] = {0xE7762044U, 0x00000000U}, /* RGIDR_MODID[106]:ARSP38*/ + [101] = {0xE7762048U, 0x0000000EU}, /* RGIDR_MODID[107]:MSI0*/ + [102] = {0xE776204CU, 0x0000000EU}, /* RGIDR_MODID[108]:MSI1*/ + [103] = {0xE7762050U, 0x0000000EU}, /* RGIDR_MODID[109]:MSI2*/ + [104] = {0xE7762054U, 0x0000000EU}, /* RGIDR_MODID[110]:MSI3*/ + [105] = {0xE7762058U, 0x0000000EU}, /* RGIDR_MODID[111]:MSI4*/ + [106] = {0xE776205CU, 0x0000000EU}, /* RGIDR_MODID[112]:MSI5*/ + [107] = {0xE7792000U, 0x0000000FU}, /* RGIDR_MODID[113]:ARSP40*/ + /* After setting */ /* RGIDR_MODID[114]:ARSP41*/ + /* After setting */ /* RGIDR_MODID[115]:ARSP42*/ + [108] = {0xE779200CU, 0x0000000FU}, /* RGIDR_MODID[116]:ARSP43*/ + [109] = {0xE7792010U, 0x0000000FU}, /* RGIDR_MODID[117]:ARSP44*/ + [110] = {0xE7792014U, 0x0000000FU}, /* RGIDR_MODID[118]:ARSP45*/ + [111] = {0xE7792018U, 0x0000000FU}, /* RGIDR_MODID[119]:ARSP46*/ + [112] = {0xE779201CU, 0x0000000FU}, /* RGIDR_MODID[120]:ARSP47*/ + [113] = {0xE7792020U, 0x00000000U}, /* RGIDR_MODID[121]:ARSP48*/ + [114] = {0xE7792024U, 0x0000004FU}, /* RGIDR_MODID[122]:DMAHSCIF0*/ + [115] = {0xE7792028U, 0x0000004FU}, /* RGIDR_MODID[123]:DMAHSCIF1*/ + [116] = {0xE779202CU, 0x0000004FU}, /* RGIDR_MODID[124]:DMAHSCIF2*/ + [117] = {0xE7792030U, 0x0000004FU}, /* RGIDR_MODID[125]:DMAHSCIF3*/ + [118] = {0xE7792034U, 0x0000004FU}, /* RGIDR_MODID[126]:DMASCIF0*/ + [119] = {0xE7792038U, 0x0000004FU}, /* RGIDR_MODID[127]:DMASCIF1*/ + [120] = {0xE779203CU, 0x0000004FU}, /* RGIDR_MODID[128]:DMASCIF3*/ + [121] = {0xE7792040U, 0x0000004FU}, /* RGIDR_MODID[129]:DMASCIF4*/ + [122] = {0xE7792044U, 0x0000000FU}, /* RGIDR_MODID[130]:ECMSP4*/ + [123] = {0xE7792048U, 0x0000004FU}, /* RGIDR_MODID[131]:HSCIF0*/ + [124] = {0xE779204CU, 0x0000004FU}, /* RGIDR_MODID[132]:HSCIF1*/ + [125] = {0xE7792050U, 0x0000004FU}, /* RGIDR_MODID[133]:HSCIF2*/ + [126] = {0xE7792054U, 0x0000004FU}, /* RGIDR_MODID[134]:HSCIF3*/ + [127] = {0xE7792058U, 0x0000004FU}, /* RGIDR_MODID[135]:SCIF0*/ + [128] = {0xE779205CU, 0x0000004FU}, /* RGIDR_MODID[136]:SCIF1*/ + [129] = {0xE7792060U, 0x0000004FU}, /* RGIDR_MODID[137]:SCIF3*/ + [130] = {0xE7792064U, 0x0000004FU}, /* RGIDR_MODID[138]:SCIF4*/ + [131] = {0xE7792068U, 0x0000006EU}, /* RGIDR_MODID[139]:TMU1*/ + [132] = {0xE779206CU, 0x0000006EU}, /* RGIDR_MODID[140]:TMU2*/ + [133] = {0xE7792070U, 0x0000006EU}, /* RGIDR_MODID[141]:TMU3*/ + [134] = {0xE7792074U, 0x0000006EU}, /* RGIDR_MODID[142]:TMU4*/ + [135] = {0xE7792078U, 0x0000004AU}, /* RGIDR_MODID[143]:CANFD*/ + [136] = {0xE779207CU, 0x0000004AU}, /* RGIDR_MODID[144]:DMACANFD*/ + [137] = {0xE7792080U, 0x00000002U}, /* RGIDR_MODID[145]:DMATPU0*/ + [138] = {0xE7792084U, 0x00000002U}, /* RGIDR_MODID[146]:PWM0*/ + [139] = {0xE7792088U, 0x00000002U}, /* RGIDR_MODID[147]:PWM1*/ + [140] = {0xE779208CU, 0x00000002U}, /* RGIDR_MODID[148]:PWM2*/ + [141] = {0xE7792090U, 0x00000002U}, /* RGIDR_MODID[149]:PWM3*/ + [142] = {0xE7792094U, 0x00000002U}, /* RGIDR_MODID[150]:PWM4*/ + [143] = {0xE77920ACU, 0x00000002U}, /* RGIDR_MODID[151]:TPU0*/ + [144] = {0xFEBD2000U, 0x0000000FU}, /* RGIDR_MODID[152]:ARVI40*/ + /* After setting */ /* RGIDR_MODID[153]:ARVI41*/ + /* After setting */ /* RGIDR_MODID[154]:ARVI42*/ + [145] = {0xFEBD200CU, 0x0000000FU}, /* RGIDR_MODID[155]:ARVI43*/ + [146] = {0xFEBD2010U, 0x0000000FU}, /* RGIDR_MODID[156]:ARVI44*/ + [147] = {0xFEBD2014U, 0x0000000FU}, /* RGIDR_MODID[157]:ARVI45*/ + [148] = {0xFEBD2018U, 0x0000000FU}, /* RGIDR_MODID[158]:ARVI46*/ + [149] = {0xFEBD201CU, 0x0000000FU}, /* RGIDR_MODID[159]:ARVI47*/ + [150] = {0xFEBD2020U, 0x00000000U}, /* RGIDR_MODID[160]:ARVI48*/ + [151] = {0xFEBD2024U, 0x0000000FU}, /* RGIDR_MODID[161]:DIS0*/ + [152] = {0xFEBD2030U, 0x0000000FU}, /* RGIDR_MODID[162]:ECMVIO2*/ + [153] = {0xFEBD2034U, 0x0000000FU}, /* RGIDR_MODID[163]:FCPVD0*/ + [154] = {0xFEBD203CU, 0x0000004EU}, /* RGIDR_MODID[164]:VSPD0*/ + [155] = {0xE6582000U, 0x0000000AU}, /* RGIDR_MODID[165]:CKMHSC*/ + [156] = {0xE6582004U, 0x0000000CU}, /* RGIDR_MODID[166]:AXIPCI001*/ + [157] = {0xE6582008U, 0x0000000CU}, /* RGIDR_MODID[167]:AXIPCI002*/ + [158] = {0xE658200CU, 0x0000000CU}, /* RGIDR_MODID[168]:AXIPCI003*/ + [159] = {0xE6582014U, 0x0000000CU}, /* RGIDR_MODID[169]:AXIPCI005*/ + [160] = {0xE6582018U, 0x0000000CU}, /* RGIDR_MODID[170]:AXIPCI006*/ + [161] = {0xE658201CU, 0x0000000CU}, /* RGIDR_MODID[171]:AXIPCI007*/ + [162] = {0xE6582020U, 0x0000000CU}, /* RGIDR_MODID[172]:AXIPCI008*/ + [163] = {0xE6582024U, 0x0000000CU}, /* RGIDR_MODID[173]:AXIPCI009*/ + [164] = {0xE6582028U, 0x0000000CU}, /* RGIDR_MODID[174]:AXIPCI010*/ + [165] = {0xE658202CU, 0x0000000CU}, /* RGIDR_MODID[175]:AXIPCI011*/ + [166] = {0xE6582030U, 0x0000000CU}, /* RGIDR_MODID[176]:AXIPCI012*/ + [167] = {0xE6582034U, 0x0000000CU}, /* RGIDR_MODID[177]:AXIPCI013*/ + [168] = {0xE6582038U, 0x0000000CU}, /* RGIDR_MODID[178]:AXIPCI014*/ + [169] = {0xE658203CU, 0x0000000CU}, /* RGIDR_MODID[179]:AXIPCI015*/ + [170] = {0xE6582084U, 0x0000000EU}, /* RGIDR_MODID[180]:GPTP*/ + [171] = {0xE6582088U, 0x0000004EU}, /* RGIDR_MODID[181]:IPMMUHC00*/ + [172] = {0xE65820F4U, 0x0000000CU}, /* RGIDR_MODID[182]:AXIPCI000*/ + [173] = {0xE65820F8U, 0x0000000CU}, /* RGIDR_MODID[183]:AXIPCI004*/ + [174] = {0xE65820FCU, 0x0000004EU}, /* RGIDR_MODID[184]:IPMMUHC01*/ + [175] = {0xE6582100U, 0x0000004EU}, /* RGIDR_MODID[185]:AVB0*/ + [176] = {0xE6582104U, 0x0000004EU}, /* RGIDR_MODID[186]:AVB1*/ + [177] = {0xE6582108U, 0x0000004EU}, /* RGIDR_MODID[187]:AVB2*/ + [178] = {0xE658210CU, 0x0000004EU}, /* RGIDR_MODID[188]:IPMMUHC10*/ + [179] = {0xE6582110U, 0x0000004EU}, /* RGIDR_MODID[189]:IPMMUHC11*/ + [180] = {0xE6582114U, 0x0000004EU}, /* RGIDR_MODID[190]:IPMMUHC12*/ + [181] = {0xE6582118U, 0x0000004EU}, /* RGIDR_MODID[191]:IPMMUHC13*/ + [182] = {0xE658211CU, 0x0000000CU}, /* RGIDR_MODID[192]:PPHY0*/ + [183] = {0xE6582124U, 0x0000004EU}, /* RGIDR_MODID[193]:IPMMUHC14*/ + [184] = {0xE6582128U, 0x0000004EU}, /* RGIDR_MODID[194]:IPMMUHC15*/ + [185] = {0xE658212CU, 0x0000000EU}, /* RGIDR_MODID[195]:FBAHSC*/ + [186] = {0xE6582130U, 0x0000004EU}, /* RGIDR_MODID[196]:IPMMUHC02*/ + [187] = {0xE6582138U, 0x0000000FU}, /* RGIDR_MODID[197]:ECMHSC*/ + [188] = {0xE658213CU, 0x0000000FU}, /* RGIDR_MODID[198]:ARHC0*/ + /* After setting */ /* RGIDR_MODID[199]:ARHC1*/ + /* After setting */ /* RGIDR_MODID[200]:ARHC2*/ + [189] = {0xE6582148U, 0x0000000FU}, /* RGIDR_MODID[201]:ARHC3*/ + [190] = {0xE658214CU, 0x0000000FU}, /* RGIDR_MODID[202]:ARHC4*/ + [191] = {0xE6582150U, 0x0000000FU}, /* RGIDR_MODID[203]:ARHC5*/ + [192] = {0xE6582154U, 0x0000000FU}, /* RGIDR_MODID[204]:ARHC6*/ + [193] = {0xE6582158U, 0x0000000FU}, /* RGIDR_MODID[205]:ARHC7*/ + [194] = {0xE658215CU, 0x00000000U}, /* RGIDR_MODID[206]:ARHC8*/ + [195] = {0xE6582160U, 0x0000004EU}, /* RGIDR_MODID[207]:IPMMUHC03*/ + [196] = {0xE6582164U, 0x0000004EU}, /* RGIDR_MODID[208]:IPMMUHC04*/ + [197] = {0xE6582168U, 0x0000004EU}, /* RGIDR_MODID[209]:IPMMUHC05*/ + [198] = {0xE658216CU, 0x0000004EU}, /* RGIDR_MODID[210]:IPMMUHC06*/ + [199] = {0xE6582170U, 0x0000004EU}, /* RGIDR_MODID[211]:IPMMUHC07*/ + [200] = {0xE6582174U, 0x0000004EU}, /* RGIDR_MODID[212]:IPMMUHC08*/ + [201] = {0xE6582178U, 0x0000004EU}, /* RGIDR_MODID[213]:IPMMUHC09*/ + [202] = {0xFF882000U, 0x0000000FU}, /* RGIDR_MODID[214]:ARIMP00*/ + /* After setting */ /* RGIDR_MODID[215]:ARIMP01*/ + /* After setting */ /* RGIDR_MODID[216]:ARIMP02*/ + [203] = {0xFF88200CU, 0x0000000FU}, /* RGIDR_MODID[217]:ARIMP03*/ + [204] = {0xFF882010U, 0x0000000FU}, /* RGIDR_MODID[218]:ARIMP04*/ + [205] = {0xFF882014U, 0x0000004EU}, /* RGIDR_MODID[219]:AXIFBABUSIR0*/ + [206] = {0xFF882018U, 0x0000004EU}, /* RGIDR_MODID[220]:AXIFBABUSIR1*/ + [207] = {0xFF88201CU, 0x0000004EU}, /* RGIDR_MODID[221]:AXIFBABUSIR2*/ + [208] = {0xFF882020U, 0x0000004EU}, /* RGIDR_MODID[222]:AXIFBABUSIR3*/ + [209] = {0xFF882028U, 0x0000004EU}, /* RGIDR_MODID[223]:AXIIMP0*/ + [210] = {0xFF882034U, 0x0000000FU}, /* RGIDR_MODID[224]:ARIMP05*/ + [211] = {0xFF882038U, 0x0000000FU}, /* RGIDR_MODID[225]:ARIMP06*/ + [212] = {0xFF88203CU, 0x0000000FU}, /* RGIDR_MODID[226]:ARIMP07*/ + [213] = {0xFF882040U, 0x00000000U}, /* RGIDR_MODID[227]:ARIMP08*/ + [214] = {0xFF882048U, 0x0000000FU}, /* RGIDR_MODID[228]:ECMIR*/ + [215] = {0xFF88204CU, 0x0000000FU}, /* RGIDR_MODID[229]:DSPPS*/ + [216] = {0xFF882050U, 0x0000004EU}, /* RGIDR_MODID[230]:IPMMUIR1*/ + [217] = {0xFF882054U, 0x0000004EU}, /* RGIDR_MODID[231]:IPMMUIR0*/ + [218] = {0xFF882058U, 0x0000004EU}, /* RGIDR_MODID[232]:IPMMUIR10*/ + [219] = {0xFF88205CU, 0x0000004EU}, /* RGIDR_MODID[233]:IPMMUIR11*/ + [220] = {0xFF882060U, 0x0000004EU}, /* RGIDR_MODID[234]:IPMMUIR12*/ + [221] = {0xFF882064U, 0x0000004EU}, /* RGIDR_MODID[235]:IPMMUIR13*/ + [222] = {0xFF882068U, 0x0000004EU}, /* RGIDR_MODID[236]:IPMMUIR14*/ + [223] = {0xFF88206CU, 0x0000004EU}, /* RGIDR_MODID[237]:IPMMUIR15*/ + [224] = {0xFF882070U, 0x0000004EU}, /* RGIDR_MODID[238]:IPMMUIR2*/ + [225] = {0xFF882074U, 0x0000004EU}, /* RGIDR_MODID[239]:IPMMUIR3*/ + [226] = {0xFF882078U, 0x0000004EU}, /* RGIDR_MODID[240]:IPMMUIR4*/ + [227] = {0xFF88207CU, 0x0000004EU}, /* RGIDR_MODID[241]:IPMMUIR5*/ + [228] = {0xFF882080U, 0x0000004EU}, /* RGIDR_MODID[242]:IPMMUIR6*/ + [229] = {0xFF882084U, 0x0000004EU}, /* RGIDR_MODID[243]:IPMMUIR7*/ + [230] = {0xFF882088U, 0x0000004EU}, /* RGIDR_MODID[244]:IPMMUIR8*/ + [231] = {0xFF88208CU, 0x0000004EU}, /* RGIDR_MODID[245]:IPMMUIR9*/ + [232] = {0xFD812000U, 0x0000000FU}, /* RGIDR_MODID[246]:ARPV0*/ + /* After setting */ /* RGIDR_MODID[247]:ARPV1*/ + [233] = {0xFD812008U, 0x0000002CU}, /* RGIDR_MODID[248]:AXIRGXS*/ + /* After setting */ /* RGIDR_MODID[249]:ARPV2*/ + [234] = {0xFD812010U, 0x0000000FU}, /* RGIDR_MODID[250]:ARPV3*/ + [235] = {0xFD812014U, 0x0000000FU}, /* RGIDR_MODID[251]:ARPV4*/ + [236] = {0xFD812018U, 0x0000000FU}, /* RGIDR_MODID[252]:ARPV5*/ + [237] = {0xFD81201CU, 0x0000000FU}, /* RGIDR_MODID[253]:ARPV6*/ + [238] = {0xFD812020U, 0x0000000FU}, /* RGIDR_MODID[254]:ARPV7*/ + [239] = {0xFD812024U, 0x00000000U}, /* RGIDR_MODID[255]:ARPV8*/ + [240] = {0xFD81202CU, 0x0000000FU}, /* RGIDR_MODID[256]:ECM3DG*/ + [241] = {0xFD812030U, 0x0000000EU}, /* RGIDR_MODID[257]:FBAPVC*/ + [242] = {0xFD812034U, 0x0000000EU}, /* RGIDR_MODID[258]:FBAPVD0*/ + [243] = {0xFD812038U, 0x0000000EU}, /* RGIDR_MODID[259]:FBAPVD1*/ + [244] = {0xFD81203CU, 0x0000000EU}, /* RGIDR_MODID[260]:FBAPVD2*/ + [245] = {0xFD812040U, 0x0000000EU}, /* RGIDR_MODID[261]:FBAPVE*/ + [246] = {0xFD812044U, 0x0000004EU}, /* RGIDR_MODID[262]:IPMMUPV000*/ + [247] = {0xFD812048U, 0x0000004EU}, /* RGIDR_MODID[263]:IPMMUPV001*/ + [248] = {0xFD81204CU, 0x0000004EU}, /* RGIDR_MODID[264]:IPMMUPV010*/ + [249] = {0xFD812050U, 0x0000004EU}, /* RGIDR_MODID[265]:IPMMUPV011*/ + [250] = {0xFD812054U, 0x0000004EU}, /* RGIDR_MODID[266]:IPMMUPV012*/ + [251] = {0xFD812058U, 0x0000004EU}, /* RGIDR_MODID[267]:IPMMUPV013*/ + [252] = {0xFD81205CU, 0x0000004EU}, /* RGIDR_MODID[268]:IPMMUPV014*/ + [253] = {0xFD812060U, 0x0000004EU}, /* RGIDR_MODID[269]:IPMMUPV015*/ + [254] = {0xFD812064U, 0x0000004EU}, /* RGIDR_MODID[270]:IPMMUPV002*/ + [255] = {0xFD812068U, 0x0000004EU}, /* RGIDR_MODID[271]:IPMMUPV003*/ + [256] = {0xFD81206CU, 0x0000004EU}, /* RGIDR_MODID[272]:IPMMUPV004*/ + [257] = {0xFD812070U, 0x0000004EU}, /* RGIDR_MODID[273]:IPMMUPV005*/ + [258] = {0xFD812074U, 0x0000004EU}, /* RGIDR_MODID[274]:IPMMUPV006*/ + [259] = {0xFD812078U, 0x0000004EU}, /* RGIDR_MODID[275]:IPMMUPV007*/ + [260] = {0xFD81207CU, 0x0000004EU}, /* RGIDR_MODID[276]:IPMMUPV008*/ + [261] = {0xFD812080U, 0x0000004EU}, /* RGIDR_MODID[277]:IPMMUPV009*/ + [262] = {0xE6622000U, 0x0000000FU}, /* RGIDR_MODID[278]:ARRC0*/ + /* After setting */ /* RGIDR_MODID[279]:ARRC1*/ + /* After setting */ /* RGIDR_MODID[280]:ARRC2*/ + [263] = {0xE662200CU, 0x0000000FU}, /* RGIDR_MODID[281]:ARRC3*/ + [264] = {0xE6622010U, 0x0000000FU}, /* RGIDR_MODID[282]:ARRC4*/ + [265] = {0xE6622014U, 0x0000000FU}, /* RGIDR_MODID[283]:ARRC5*/ + [266] = {0xE6622018U, 0x0000000FU}, /* RGIDR_MODID[284]:ARRC6*/ + [267] = {0xE662201CU, 0x0000000FU}, /* RGIDR_MODID[285]:ARRC7*/ + [268] = {0xE6622020U, 0x00000000U}, /* RGIDR_MODID[286]:ARRC8*/ + [269] = {0xE6622028U, 0x0000004FU}, /* RGIDR_MODID[287]:ICUMX*/ + [270] = {0xE662202CU, 0x0000000FU}, /* RGIDR_MODID[288]:ECMRC*/ + [271] = {0xFFC32000U, 0x0000004EU}, /* RGIDR_MODID[289]:DMAWCRC0*/ + [272] = {0xFFC32004U, 0x0000004EU}, /* RGIDR_MODID[290]:DMAWCRC1*/ + [273] = {0xFFC32008U, 0x0000004EU}, /* RGIDR_MODID[291]:DMAWCRC2*/ + [274] = {0xFFC3200CU, 0x0000004EU}, /* RGIDR_MODID[292]:DMAWCRC3*/ + [275] = {0xFFC42000U, 0x0000000FU}, /* RGIDR_MODID[293]:ARMREG00*/ + [276] = {0xFFC42004U, 0x0000000DU}, /* RGIDR_MODID[294]:ARMREG01*/ + [277] = {0xFFC42008U, 0x00000000U}, /* RGIDR_MODID[295]:ARMREG10*/ + [278] = {0xFFC4200CU, 0x00000000U}, /* RGIDR_MODID[296]:ARMREG11*/ + [279] = {0xFFC42010U, 0x0000000BU}, /* RGIDR_MODID[297]:ARMREG12*/ + [280] = {0xFFC42014U, 0x0000000FU}, /* RGIDR_MODID[298]:ARMREG13*/ + [281] = {0xFFC42018U, 0x0000000BU}, /* RGIDR_MODID[299]:ARMREG14*/ + [282] = {0xFFC4201CU, 0x00000002U}, /* RGIDR_MODID[300]:AXICR52SS0*/ + [283] = {0xFFC42020U, 0x0000000EU}, /* RGIDR_MODID[301]:AXICSD0*/ + [284] = {0xFFC42024U, 0x0000000EU}, /* RGIDR_MODID[302]:AXIINTAP0*/ + [285] = {0xFFC4202CU, 0x00000009U}, /* RGIDR_MODID[303]:AXISECROM*/ + [286] = {0xFFC42030U, 0x0000000FU}, /* RGIDR_MODID[304]:AXISYSRAM0*/ + [287] = {0xFFC42034U, 0x0000004FU}, /* RGIDR_MODID[305]:AXISYSRAM1*/ + [288] = {0xFFC42038U, 0x00000000U}, /* RGIDR_MODID[306]:ARGREG15*/ + [289] = {0xFFC4203CU, 0x00000000U}, /* RGIDR_MODID[307]:ARMREG2*/ + [290] = {0xFFC42040U, 0x00000000U}, /* RGIDR_MODID[308]:ARMREG3*/ + [291] = {0xFFC42044U, 0x00000000U}, /* RGIDR_MODID[309]:ARMREG4*/ + [292] = {0xFFC42048U, 0x0000000FU}, /* RGIDR_MODID[310]:ARMREG5*/ + [293] = {0xFFC4204CU, 0x0000000FU}, /* RGIDR_MODID[311]:ARMREG6*/ + [294] = {0xFFC42050U, 0x00000000U}, /* RGIDR_MODID[312]:ARMREG7*/ + [295] = {0xFFC42054U, 0x0000000DU}, /* RGIDR_MODID[313]:ARMREG8*/ + [296] = {0xFFC42058U, 0x0000000DU}, /* RGIDR_MODID[314]:ARMREG9*/ + [297] = {0xFFC4205CU, 0x0000000FU}, /* RGIDR_MODID[315]:ARRD0*/ + /* After setting */ /* RGIDR_MODID[316]:ARRD1*/ + /* After setting */ /* RGIDR_MODID[317]:ARRD2*/ + [298] = {0xFFC42068U, 0x0000000FU}, /* RGIDR_MODID[318]:ARRD3*/ + [299] = {0xFFC4206CU, 0x0000000FU}, /* RGIDR_MODID[319]:ARRD4*/ + [300] = {0xFFC42070U, 0x0000000FU}, /* RGIDR_MODID[320]:ARRD5*/ + [301] = {0xFFC42074U, 0x0000000FU}, /* RGIDR_MODID[321]:ARRD6*/ + [302] = {0xFFC42078U, 0x0000000FU}, /* RGIDR_MODID[322]:ARRD7*/ + [303] = {0xFFC4207CU, 0x00000000U}, /* RGIDR_MODID[323]:ARRD8*/ + [304] = {0xFFC42080U, 0x0000000FU}, /* RGIDR_MODID[324]:ARRT0*/ + /* After setting */ /* RGIDR_MODID[325]:ARRT1*/ + /* After setting */ /* RGIDR_MODID[326]:ARRT2*/ + [305] = {0xFFC4208CU, 0x0000000FU}, /* RGIDR_MODID[327]:ARRT3*/ + [306] = {0xFFC42090U, 0x0000000FU}, /* RGIDR_MODID[328]:ARRT4*/ + [307] = {0xFFC42094U, 0x0000000FU}, /* RGIDR_MODID[329]:ARRT5*/ + [308] = {0xFFC42098U, 0x0000000FU}, /* RGIDR_MODID[330]:ARRT6*/ + [309] = {0xFFC4209CU, 0x0000000FU}, /* RGIDR_MODID[331]:ARRT7*/ + [310] = {0xFFC420A0U, 0x00000000U}, /* RGIDR_MODID[332]:ARRT8*/ + [311] = {0xFFC420A4U, 0x0000000AU}, /* RGIDR_MODID[333]:CKMRT*/ + [312] = {0xFFC420A8U, 0x0000004EU}, /* RGIDR_MODID[334]:CRC0*/ + [313] = {0xFFC420ACU, 0x0000004EU}, /* RGIDR_MODID[335]:CRC1*/ + [314] = {0xFFC420B0U, 0x0000004EU}, /* RGIDR_MODID[336]:CRC2*/ + [315] = {0xFFC420B4U, 0x0000004EU}, /* RGIDR_MODID[337]:CRC3*/ + [316] = {0xFFC420B8U, 0x0000000EU}, /* RGIDR_MODID[338]:CSD*/ + [317] = {0xFFC420BCU, 0x0000000FU}, /* RGIDR_MODID[339]:ECM*/ + [318] = {0xFFC420C0U, 0x0000000FU}, /* RGIDR_MODID[340]:ECMRT*/ + [319] = {0xFFC420C4U, 0x0000000EU}, /* RGIDR_MODID[341]:FBACR52*/ + [320] = {0xFFC420C8U, 0x0000000EU}, /* RGIDR_MODID[342]:FBART*/ + [321] = {0xFFC420CCU, 0x0000000EU}, /* RGIDR_MODID[343]:INTTP*/ + [322] = {0xFFC420D0U, 0x0000004EU}, /* RGIDR_MODID[344]:IPMMURT000*/ + [323] = {0xFFC420D4U, 0x0000004EU}, /* RGIDR_MODID[345]:IPMMURT100*/ + [324] = {0xFFC420D8U, 0x0000004EU}, /* RGIDR_MODID[346]:KCRC4*/ + [325] = {0xFFC420DCU, 0x0000004EU}, /* RGIDR_MODID[347]:KCRC5*/ + [326] = {0xFFC420E0U, 0x0000004EU}, /* RGIDR_MODID[348]:KCRC6*/ + [327] = {0xFFC420E4U, 0x0000004EU}, /* RGIDR_MODID[349]:KCRC7*/ + [328] = {0xFFC420E8U, 0x0000004FU}, /* RGIDR_MODID[350]:MFI00*/ + [329] = {0xFFC420ECU, 0x0000004EU}, /* RGIDR_MODID[351]:MFI01*/ + [330] = {0xFFC420F0U, 0x0000004EU}, /* RGIDR_MODID[352]:MFI10*/ + [331] = {0xFFC420F4U, 0x0000004EU}, /* RGIDR_MODID[353]:MFI02*/ + [332] = {0xFFC420F8U, 0x0000004EU}, /* RGIDR_MODID[354]:MFI03*/ + [333] = {0xFFC420FCU, 0x0000004EU}, /* RGIDR_MODID[355]:MFI04*/ + [334] = {0xFFC42100U, 0x00000000U}, /* RGIDR_MODID[356]:MFI05*/ + [335] = {0xFFC42104U, 0x00000000U}, /* RGIDR_MODID[357]:MFI06*/ + [336] = {0xFFC42108U, 0x00000000U}, /* RGIDR_MODID[358]:MFI07*/ + [337] = {0xFFC4210CU, 0x00000000U}, /* RGIDR_MODID[359]:MFI08*/ + [338] = {0xFFC42110U, 0x0000004EU}, /* RGIDR_MODID[360]:MFI09*/ + [339] = {0xFFC42114U, 0x0000004FU}, /* RGIDR_MODID[361]:MFI15*/ + [340] = {0xFFC42118U, 0x0000000AU}, /* RGIDR_MODID[362]:CKMCR52*/ + [341] = {0xFFC4211CU, 0x0000004BU}, /* RGIDR_MODID[363]:RTDM0P*/ + [342] = {0xFFC42120U, 0x0000000FU}, /* RGIDR_MODID[364]:ECMRD*/ + [343] = {0xFFC42124U, 0x0000004BU}, /* RGIDR_MODID[365]:RTDM1P*/ + [344] = {0xFFC42130U, 0x0000000BU}, /* RGIDR_MODID[366]:SYSRAM10*/ + [345] = {0xFFC42138U, 0x00000003U}, /* RGIDR_MODID[367]:SYSRAM00*/ + [346] = {0xFFC4213CU, 0x0000004EU}, /* RGIDR_MODID[368]:TSIPL0*/ + [347] = {0xFFC42140U, 0x0000004EU}, /* RGIDR_MODID[369]:TSIPL1*/ + [348] = {0xFFC42144U, 0x0000004EU}, /* RGIDR_MODID[370]:TSIPL2*/ + [349] = {0xFFC42148U, 0x0000004EU}, /* RGIDR_MODID[371]:TSIPL3*/ + [350] = {0xFFC4214CU, 0x0000004EU}, /* RGIDR_MODID[372]:TSIPL4*/ + [351] = {0xFFC42150U, 0x0000004EU}, /* RGIDR_MODID[373]:TSIPL5*/ + [352] = {0xFFC42154U, 0x0000004EU}, /* RGIDR_MODID[374]:TSIPL6*/ + [353] = {0xFFC42158U, 0x0000004EU}, /* RGIDR_MODID[375]:TSIPL7*/ + [354] = {0xFFC4215CU, 0x0000004EU}, /* RGIDR_MODID[376]:WCRC0*/ + [355] = {0xFFC42160U, 0x0000004EU}, /* RGIDR_MODID[377]:WCRC1*/ + [356] = {0xFFC42164U, 0x0000004EU}, /* RGIDR_MODID[378]:WCRC2*/ + [357] = {0xFFC42168U, 0x0000004EU}, /* RGIDR_MODID[379]:WCRC3*/ + [358] = {0xFFC42180U, 0x0000004EU}, /* RGIDR_MODID[380]:MFI11*/ + [359] = {0xFFC42184U, 0x00000000U}, /* RGIDR_MODID[381]:MFI12*/ + [360] = {0xFFC42188U, 0x00000000U}, /* RGIDR_MODID[382]:MFI13*/ + [361] = {0xFFC4218CU, 0x00000000U}, /* RGIDR_MODID[383]:MFI14*/ + [362] = {0xFFC42190U, 0x0000004EU}, /* RGIDR_MODID[384]:IPMMURT001*/ + [363] = {0xFFC42194U, 0x0000004EU}, /* RGIDR_MODID[385]:IPMMURT010*/ + [364] = {0xFFC42198U, 0x0000004EU}, /* RGIDR_MODID[386]:IPMMURT011*/ + [365] = {0xFFC4219CU, 0x0000004EU}, /* RGIDR_MODID[387]:IPMMURT012*/ + [366] = {0xFFC421A0U, 0x0000004EU}, /* RGIDR_MODID[388]:IPMMURT013*/ + [367] = {0xFFC421A4U, 0x0000004EU}, /* RGIDR_MODID[389]:IPMMURT014*/ + [368] = {0xFFC421A8U, 0x0000004EU}, /* RGIDR_MODID[390]:IPMMURT015*/ + [369] = {0xFFC421ACU, 0x0000004EU}, /* RGIDR_MODID[391]:IPMMURT002*/ + [370] = {0xFFC421B0U, 0x0000004EU}, /* RGIDR_MODID[392]:IPMMURT003*/ + [371] = {0xFFC421B4U, 0x0000004EU}, /* RGIDR_MODID[393]:IPMMURT004*/ + [372] = {0xFFC421B8U, 0x0000004EU}, /* RGIDR_MODID[394]:IPMMURT005*/ + [373] = {0xFFC421BCU, 0x0000004EU}, /* RGIDR_MODID[395]:IPMMURT006*/ + [374] = {0xFFC421C0U, 0x0000004EU}, /* RGIDR_MODID[396]:IPMMURT007*/ + [375] = {0xFFC421C4U, 0x0000004EU}, /* RGIDR_MODID[397]:IPMMURT008*/ + [376] = {0xFFC421C8U, 0x0000004EU}, /* RGIDR_MODID[398]:IPMMURT009*/ + [377] = {0xFFC421CCU, 0x0000004EU}, /* RGIDR_MODID[399]:IPKMURT101*/ + [378] = {0xFFC421D0U, 0x0000004EU}, /* RGIDR_MODID[400]:IPMMURT110*/ + [379] = {0xFFC421D4U, 0x0000004EU}, /* RGIDR_MODID[401]:IPMMURT111*/ + [380] = {0xFFC421D8U, 0x0000004EU}, /* RGIDR_MODID[402]:IPMMURT112*/ + [381] = {0xFFC421DCU, 0x0000004EU}, /* RGIDR_MODID[403]:IPMMURT113*/ + [382] = {0xFFC421E0U, 0x0000004EU}, /* RGIDR_MODID[404]:IPMMURT114*/ + [383] = {0xFFC421E4U, 0x0000004EU}, /* RGIDR_MODID[405]:IPMMURT115*/ + [384] = {0xFFC421E8U, 0x0000004EU}, /* RGIDR_MODID[406]:IPMMURT102*/ + [385] = {0xFFC421ECU, 0x0000004EU}, /* RGIDR_MODID[407]:IPMMURT103*/ + [386] = {0xFFC421F0U, 0x0000004EU}, /* RGIDR_MODID[408]:IPMMURT104*/ + [387] = {0xFFC421F4U, 0x0000004EU}, /* RGIDR_MODID[409]:IPMMURT105*/ + [388] = {0xFFC421F8U, 0x0000004EU}, /* RGIDR_MODID[410]:IPMMURT106*/ + [389] = {0xFFC421FCU, 0x0000004EU}, /* RGIDR_MODID[411]:IPMMURT107*/ + [390] = {0xFFC42200U, 0x0000004BU}, /* RGIDR_MODID[412]:RTDM000*/ + [391] = {0xFFC42204U, 0x0000004BU}, /* RGIDR_MODID[413]:RTDM001*/ + [392] = {0xFFC42208U, 0x0000004BU}, /* RGIDR_MODID[414]:RTDM010*/ + [393] = {0xFFC4220CU, 0x0000004BU}, /* RGIDR_MODID[415]:RTDM011*/ + [394] = {0xFFC42210U, 0x0000004BU}, /* RGIDR_MODID[416]:RTDM012*/ + [395] = {0xFFC42214U, 0x0000004BU}, /* RGIDR_MODID[417]:RTDM013*/ + [396] = {0xFFC42218U, 0x0000004BU}, /* RGIDR_MODID[418]:RTDM014*/ + [397] = {0xFFC4221CU, 0x0000004BU}, /* RGIDR_MODID[419]:RTDM015*/ + [398] = {0xFFC42220U, 0x0000004BU}, /* RGIDR_MODID[420]:RTDM002*/ + [399] = {0xFFC42224U, 0x0000004BU}, /* RGIDR_MODID[421]:RTDM003*/ + [400] = {0xFFC42228U, 0x0000004BU}, /* RGIDR_MODID[422]:RTDM004*/ + [401] = {0xFFC4222CU, 0x0000004BU}, /* RGIDR_MODID[423]:RTDM005*/ + [402] = {0xFFC42230U, 0x0000004BU}, /* RGIDR_MODID[424]:RTDM006*/ + [403] = {0xFFC42234U, 0x0000004BU}, /* RGIDR_MODID[425]:RTDM007*/ + [404] = {0xFFC42238U, 0x0000004BU}, /* RGIDR_MODID[426]:RTDM008*/ + [405] = {0xFFC4223CU, 0x0000004BU}, /* RGIDR_MODID[427]:RTDM009*/ + [406] = {0xFFC42240U, 0x0000004BU}, /* RGIDR_MODID[428]:RTDM100*/ + [407] = {0xFFC42244U, 0x0000004BU}, /* RGIDR_MODID[429]:RTDM101*/ + [408] = {0xFFC42248U, 0x0000004BU}, /* RGIDR_MODID[430]:RTDM110*/ + [409] = {0xFFC4224CU, 0x0000004BU}, /* RGIDR_MODID[431]:RTDM111*/ + [410] = {0xFFC42250U, 0x0000004BU}, /* RGIDR_MODID[432]:RTDM112*/ + [411] = {0xFFC42254U, 0x0000004BU}, /* RGIDR_MODID[433]:RTDM113*/ + [412] = {0xFFC42258U, 0x0000004BU}, /* RGIDR_MODID[434]:RTDM114*/ + [413] = {0xFFC4225CU, 0x0000004BU}, /* RGIDR_MODID[435]:RTDM115*/ + [414] = {0xFFC42260U, 0x0000004BU}, /* RGIDR_MODID[436]:RTDM102*/ + [415] = {0xFFC42264U, 0x0000004BU}, /* RGIDR_MODID[437]:RTDM103*/ + [416] = {0xFFC42268U, 0x0000004BU}, /* RGIDR_MODID[438]:RTDM104*/ + [417] = {0xFFC4226CU, 0x0000004BU}, /* RGIDR_MODID[439]:RTDM105*/ + [418] = {0xFFC42270U, 0x0000004BU}, /* RGIDR_MODID[440]:RTDM106*/ + [419] = {0xFFC42274U, 0x0000004BU}, /* RGIDR_MODID[441]:RTDM107*/ + [420] = {0xFFC42278U, 0x0000004BU}, /* RGIDR_MODID[442]:RTDM108*/ + [421] = {0xFFC4227CU, 0x0000004BU}, /* RGIDR_MODID[443]:RTDM109*/ + [422] = {0xFFC42300U, 0x0000004EU}, /* RGIDR_MODID[444]:IPMMURT108*/ + [423] = {0xFFC42304U, 0x0000004EU}, /* RGIDR_MODID[445]:IPMMURT109*/ + [424] = {0xFFC42308U, 0x00000001U}, /* RGIDR_MODID[446]:SYSRAM01*/ + [425] = {0xFFC4230CU, 0x0000000BU}, /* RGIDR_MODID[447]:SYSRAM02*/ + [426] = {0xFFC42310U, 0x00000001U}, /* RGIDR_MODID[448]:SYSRAM03*/ + [427] = {0xFFC42314U, 0x00000001U}, /* RGIDR_MODID[449]:SYSRAM04*/ + [428] = {0xFFC42318U, 0x00000001U}, /* RGIDR_MODID[450]:SYSRAM05*/ + [429] = {0xFFC4231CU, 0x00000001U}, /* RGIDR_MODID[451]:SYSRAM06*/ + [430] = {0xFFC42320U, 0x00000000U}, /* RGIDR_MODID[452]:SYSRAM07*/ + [431] = {0xFFC42324U, 0x0000000BU}, /* RGIDR_MODID[453]:SYSRAM11*/ + [432] = {0xFFC42328U, 0x0000000BU}, /* RGIDR_MODID[454]:SYSRAM12*/ + [433] = {0xFFC4232CU, 0x0000000BU}, /* RGIDR_MODID[455]:SYSRAM13*/ + [434] = {0xFFC42330U, 0x0000000BU}, /* RGIDR_MODID[456]:SYSRAM14*/ + [435] = {0xFFC42334U, 0x0000000BU}, /* RGIDR_MODID[457]:SYSRAM15*/ + [436] = {0xFFC42338U, 0x0000000BU}, /* RGIDR_MODID[458]:SYSRAM16*/ + [437] = {0xFFC4233CU, 0x00000000U}, /* RGIDR_MODID[459]:SYSRAM17*/ + [438] = {0xFFC42360U, 0x00000002U}, /* RGIDR_MODID[460]:BKBUF*/ + [439] = {0xFFC42364U, 0x00000002U}, /* RGIDR_MODID[461]:AXICR52SS1*/ + [440] = {0xFFC42368U, 0x00000002U}, /* RGIDR_MODID[462]:AXICR52SS2*/ + [441] = {0xFF862000U, 0x0000000FU}, /* RGIDR_MODID[463]:ARSC0*/ + /* After setting */ /* RGIDR_MODID[464]:ARSC1*/ + /* After setting */ /* RGIDR_MODID[465]:ARSC2*/ + [442] = {0xFF86200CU, 0x0000000FU}, /* RGIDR_MODID[466]:ARSC3*/ + [443] = {0xFF862010U, 0x0000000FU}, /* RGIDR_MODID[467]:ARSC4*/ + [444] = {0xFF862014U, 0x0000000FU}, /* RGIDR_MODID[468]:ARSC5*/ + [445] = {0xFF862018U, 0x0000000FU}, /* RGIDR_MODID[469]:ARSC6*/ + [446] = {0xFF86201CU, 0x0000000FU}, /* RGIDR_MODID[470]:ARSC7*/ + [447] = {0xFF862020U, 0x00000000U}, /* RGIDR_MODID[471]:ARSC8*/ + [448] = {0xFF862024U, 0x0000000FU}, /* RGIDR_MODID[472]:ARSTM0*/ + /* After setting */ /* RGIDR_MODID[473]:ARSTM1*/ + [449] = {0xFF86202CU, 0x0000000EU}, /* RGIDR_MODID[474]:CSD1S*/ + [450] = {0xFF862030U, 0x0000000EU}, /* RGIDR_MODID[475]:AXIFBABUSTOP0*/ + /* After setting */ /* RGIDR_MODID[476]:ARSTM2*/ + [451] = {0xFF86203CU, 0x0000000FU}, /* RGIDR_MODID[477]:ARSTM3*/ + [452] = {0xFF862040U, 0x0000000FU}, /* RGIDR_MODID[478]:ARSTM4*/ + [453] = {0xFF862044U, 0x0000000FU}, /* RGIDR_MODID[479]:ARSTM5*/ + [454] = {0xFF862048U, 0x0000000FU}, /* RGIDR_MODID[480]:ARSTM6*/ + [455] = {0xFF86204CU, 0x0000000FU}, /* RGIDR_MODID[481]:ARSTM7*/ + [456] = {0xFF862050U, 0x00000000U}, /* RGIDR_MODID[482]:ARSTM8*/ + [457] = {0xFF862054U, 0x0000000FU}, /* RGIDR_MODID[483]:ECMTOP*/ + [458] = {0xFF862058U, 0x0000000EU}, /* RGIDR_MODID[484]:FBA*/ + [459] = {0xFF86205CU, 0x0000000EU}, /* RGIDR_MODID[485]:FBC*/ + [460] = {0xFF862034U, 0x0000000CU}, /* RGIDR_MODID[486]:AXICCI00*/ + [461] = {0xFF862060U, 0x0000000CU}, /* RGIDR_MODID[487]:AXICCI01*/ + [462] = {0xFF862064U, 0x0000000CU}, /* RGIDR_MODID[488]:AXICCI10*/ + [463] = {0xFF862068U, 0x0000000CU}, /* RGIDR_MODID[489]:AXICCI11*/ + [464] = {0xFF86206CU, 0x0000000CU}, /* RGIDR_MODID[490]:AXICCI12*/ + [465] = {0xFF862070U, 0x0000000CU}, /* RGIDR_MODID[491]:AXICCI13*/ + [466] = {0xFF862074U, 0x0000000CU}, /* RGIDR_MODID[492]:AXICCI14*/ + [467] = {0xFF862078U, 0x0000000CU}, /* RGIDR_MODID[493]:AXICCI15*/ + [468] = {0xFF86207CU, 0x0000000CU}, /* RGIDR_MODID[494]:AXICCI2*/ + [469] = {0xFF862080U, 0x0000000CU}, /* RGIDR_MODID[495]:AXICCI3*/ + [470] = {0xFF862084U, 0x0000000CU}, /* RGIDR_MODID[496]:AXICCI4*/ + [471] = {0xFF862088U, 0x0000000CU}, /* RGIDR_MODID[497]:AXICCI5*/ + [472] = {0xFF86208CU, 0x0000000CU}, /* RGIDR_MODID[498]:AXICCI6*/ + [473] = {0xFF862090U, 0x0000000CU}, /* RGIDR_MODID[499]:AXICCI7*/ + [474] = {0xFF862094U, 0x0000000CU}, /* RGIDR_MODID[500]:AXICCI8*/ + [475] = {0xFF862098U, 0x0000000FU}, /* RGIDR_MODID[501]:AXICCI9*/ + [476] = {0xFF8620A0U, 0x0000000FU}, /* RGIDR_MODID[502]:ECMSTM*/ + [477] = {0xE7782000U, 0x0000002CU}, /* RGIDR_MODID[503]:DMASSI00*/ + [478] = {0xE7782004U, 0x0000002CU}, /* RGIDR_MODID[504]:DMASSI01*/ + [479] = {0xE7782008U, 0x0000002CU}, /* RGIDR_MODID[505]:DMASSI02*/ + [480] = {0xE778200CU, 0x0000002CU}, /* RGIDR_MODID[506]:DMASSI03*/ + [481] = {0xE7782010U, 0x0000002CU}, /* RGIDR_MODID[507]:DMASSI04*/ + [482] = {0xE7782014U, 0x0000004EU}, /* RGIDR_MODID[508]:DMAI2C0*/ + [483] = {0xE7782018U, 0x0000004EU}, /* RGIDR_MODID[509]:DMAI2C1*/ + [484] = {0xE778201CU, 0x0000004EU}, /* RGIDR_MODID[510]:DMAI2C2*/ + [485] = {0xE7782020U, 0x0000004EU}, /* RGIDR_MODID[511]:DMAI2C3*/ + [486] = {0xE778202CU, 0x0000002CU}, /* RGIDR_MODID[512]:DMASSI05*/ + [487] = {0xE7782030U, 0x0000002CU}, /* RGIDR_MODID[513]:DMASSI06*/ + [488] = {0xE7782034U, 0x0000002CU}, /* RGIDR_MODID[514]:DMASSI07*/ + [489] = {0xE67C2000U, 0x00000007U}, /* RGIDR_MODID[515]:ARMM*/ + /* After setting */ /* RGIDR_MODID[516]:AXIARNMM*/ + [490] = {0xE67C2008U, 0x0000000FU}, /* RGIDR_MODID[517]:ARSM0*/ + /* After setting */ /* RGIDR_MODID[518]:ARSM1*/ + /* After setting */ /* RGIDR_MODID[519]:ARSM2*/ + [491] = {0xE67C2014U, 0x0000000FU}, /* RGIDR_MODID[520]:AXIQOS0*/ + [492] = {0xE67C2018U, 0x0000000FU}, /* RGIDR_MODID[521]:AXIQOS1*/ + [493] = {0xE67C201CU, 0x0000000FU}, /* RGIDR_MODID[522]:AXIQOS2*/ + [494] = {0xE67C2020U, 0x0000000FU}, /* RGIDR_MODID[523]:AXIQOS3*/ + [495] = {0xE67C2024U, 0x0000000FU}, /* RGIDR_MODID[524]:AXIQOS4*/ + [496] = {0xE67C2028U, 0x0000000FU}, /* RGIDR_MODID[525]:AXIQOS5*/ + [497] = {0xE67C2034U, 0x0000000FU}, /* RGIDR_MODID[526]:ARSM3*/ + [498] = {0xE67C2038U, 0x0000000FU}, /* RGIDR_MODID[527]:ARSM4*/ + [499] = {0xE67C203CU, 0x0000000FU}, /* RGIDR_MODID[528]:ARSM5*/ + [500] = {0xE67C2040U, 0x0000000FU}, /* RGIDR_MODID[529]:ARSM6*/ + [501] = {0xE67C2044U, 0x0000000FU}, /* RGIDR_MODID[530]:ARSM7*/ + [502] = {0xE67C2048U, 0x00000000U}, /* RGIDR_MODID[531]:ARSM8*/ + [503] = {0xE67C204CU, 0x0000000BU}, /* RGIDR_MODID[532]:AXMM0*/ + [504] = {0xE67C2050U, 0x0000000BU}, /* RGIDR_MODID[533]:AXMM1*/ + [505] = {0xE67C2054U, 0x00000000U}, /* RGIDR_MODID[534]:AXMMPMON*/ + [506] = {0xE67C2058U, 0x0000000AU}, /* RGIDR_MODID[535]:CKMMM*/ + [507] = {0xE67C205CU, 0x0000000FU}, /* RGIDR_MODID[536]:ECMMM*/ + [508] = {0xE67C2060U, 0x0000000EU}, /* RGIDR_MODID[537]:FBADBSC0*/ + [509] = {0xE67C2068U, 0x0000000EU}, /* RGIDR_MODID[538]:FBAMM*/ + [510] = {0xE67C206CU, 0x0000004EU}, /* RGIDR_MODID[539]:IPMMUMM00*/ + [511] = {0xE67C2070U, 0x0000000FU}, /* RGIDR_MODID[540]:DBS0A0*/ + [512] = {0xE67C2074U, 0x0000000AU}, /* RGIDR_MODID[541]:DBS0A1*/ + [513] = {0xE67C2084U, 0x00000009U}, /* RGIDR_MODID[542]:FCPRC*/ + [514] = {0xE67C2088U, 0x0000000FU}, /* RGIDR_MODID[543]:DBS0D0*/ + [515] = {0xE67C208CU, 0x0000000AU}, /* RGIDR_MODID[544]:DBS0D1*/ + [516] = {0xE67C2098U, 0x0000000EU}, /* RGIDR_MODID[545]:FBADDR*/ + [517] = {0xE67C209CU, 0x0000004EU}, /* RGIDR_MODID[546]:IPMMUMM01*/ + [518] = {0xE67C20A0U, 0x0000004EU}, /* RGIDR_MODID[547]:IPMMUMM10*/ + [519] = {0xE67C20A4U, 0x0000004EU}, /* RGIDR_MODID[548]:IPMMUMM11*/ + [520] = {0xE67C20A8U, 0x0000004EU}, /* RGIDR_MODID[549]:IPMMUMM12*/ + [521] = {0xE67C20ACU, 0x0000004EU}, /* RGIDR_MODID[550]:IPMMUMM13*/ + [522] = {0xE67C20B0U, 0x0000004EU}, /* RGIDR_MODID[551]:IPMMUMM14*/ + [523] = {0xE67C20B4U, 0x0000004EU}, /* RGIDR_MODID[552]:IPMMUMM15*/ + [524] = {0xE67C20B8U, 0x0000004EU}, /* RGIDR_MODID[553]:IPMMUMM02*/ + [525] = {0xE67C20BCU, 0x0000004EU}, /* RGIDR_MODID[554]:IPMMUMM03*/ + [526] = {0xE67C20C0U, 0x0000004EU}, /* RGIDR_MODID[555]:IPMMUMM04*/ + [527] = {0xE67C20C4U, 0x0000004EU}, /* RGIDR_MODID[556]:IPMMUMM05*/ + [528] = {0xE67C20C8U, 0x0000004EU}, /* RGIDR_MODID[557]:IPMMUMM06*/ + [529] = {0xE67C20CCU, 0x0000004EU}, /* RGIDR_MODID[558]:IPMMUMM07*/ + [530] = {0xE67C20D0U, 0x0000004EU}, /* RGIDR_MODID[559]:IPMMUMM08*/ + [531] = {0xE67C20D4U, 0x0000004EU}, /* RGIDR_MODID[560]:IPMMUMM09*/ + [532] = {0xFF802000U, 0x0000000FU}, /* RGIDR_MODID[561]:ARSN0*/ + /* After setting */ /* RGIDR_MODID[562]:ARSN1*/ + /* After setting */ /* RGIDR_MODID[563]:ARSN2*/ + [533] = {0xFF80200CU, 0x0000000FU}, /* RGIDR_MODID[564]:ARSN3*/ + [534] = {0xFF802010U, 0x0000000FU}, /* RGIDR_MODID[565]:ARSN4*/ + [535] = {0xFF802014U, 0x0000000FU}, /* RGIDR_MODID[566]:ARSN5*/ + [536] = {0xFF802018U, 0x0000000FU}, /* RGIDR_MODID[567]:ARSN6*/ + [537] = {0xFF80201CU, 0x00000007U}, /* RGIDR_MODID[568]:ARSN7*/ + [538] = {0xFF802020U, 0x00000000U}, /* RGIDR_MODID[569]:ARSN8*/ + [539] = {0xFF802024U, 0x0000000FU}, /* RGIDR_MODID[570]:ECMTOP3*/ + [540] = {0xE7752000U, 0x0000000FU}, /* RGIDR_MODID[571]:ARSD00*/ + /* After setting */ /* RGIDR_MODID[572]:ARSD01*/ + /* After setting */ /* RGIDR_MODID[573]:ARSD02*/ + [541] = {0xE775200CU, 0x0000000FU}, /* RGIDR_MODID[574]:ARSD03*/ + [542] = {0xE7752010U, 0x0000000FU}, /* RGIDR_MODID[575]:ARSD04*/ + [543] = {0xE7752014U, 0x0000000FU}, /* RGIDR_MODID[576]:ARSD05*/ + [544] = {0xE7752018U, 0x0000000FU}, /* RGIDR_MODID[577]:ARSD06*/ + [545] = {0xE775201CU, 0x0000004AU}, /* RGIDR_MODID[578]:AXIFRAY*/ + [546] = {0xE7752028U, 0x0000004FU}, /* RGIDR_MODID[579]:AXIRPC*/ + [547] = {0xE775202CU, 0x0000000FU}, /* RGIDR_MODID[580]:AXISDHI0*/ + [548] = {0xE7752030U, 0x0000000FU}, /* RGIDR_MODID[581]:ARSD07*/ + [549] = {0xE7752034U, 0x00000000U}, /* RGIDR_MODID[582]:ARSD08*/ + [550] = {0xE7752038U, 0x0000000FU}, /* RGIDR_MODID[583]:ARSP00*/ + /* After setting */ /* RGIDR_MODID[584]:ARSP01*/ + /* After setting */ /* RGIDR_MODID[585]:ARSP02*/ + [551] = {0xE7752044U, 0x0000000FU}, /* RGIDR_MODID[586]:ARSP03*/ + [552] = {0xE7752048U, 0x0000000FU}, /* RGIDR_MODID[587]:ARSP04*/ + [553] = {0xE775204CU, 0x0000000FU}, /* RGIDR_MODID[588]:ARSP05*/ + [554] = {0xE7752050U, 0x0000000FU}, /* RGIDR_MODID[589]:ARSP06*/ + [555] = {0xE7752054U, 0x00000007U}, /* RGIDR_MODID[590]:ARSP07*/ + [556] = {0xE7752058U, 0x00000000U}, /* RGIDR_MODID[591]:ARSP08*/ + [557] = {0xE775205CU, 0x0000004EU}, /* RGIDR_MODID[592]:IPMMUDS001*/ + [558] = {0xE7752060U, 0x0000000AU}, /* RGIDR_MODID[593]:CKMPER0*/ + [559] = {0xE7752064U, 0x0000000FU}, /* RGIDR_MODID[594]:ECMPER0*/ + [560] = {0xE7752068U, 0x0000000EU}, /* RGIDR_MODID[595]:FBAPER0*/ + [561] = {0xE775206CU, 0x0000004EU}, /* RGIDR_MODID[596]:FSO0*/ + [562] = {0xE7752070U, 0x0000004EU}, /* RGIDR_MODID[597]:FSO1*/ + [563] = {0xE7752074U, 0x0000004EU}, /* RGIDR_MODID[598]:FSO10*/ + [564] = {0xE7752078U, 0x0000004EU}, /* RGIDR_MODID[599]:FSO2*/ + [565] = {0xE775207CU, 0x0000004EU}, /* RGIDR_MODID[600]:FSO3*/ + [566] = {0xE7752080U, 0x0000004EU}, /* RGIDR_MODID[601]:FSO4*/ + [567] = {0xE7752084U, 0x0000004EU}, /* RGIDR_MODID[602]:FSO5*/ + [568] = {0xE7752088U, 0x0000004EU}, /* RGIDR_MODID[603]:FSO6*/ + [569] = {0xE775208CU, 0x0000004EU}, /* RGIDR_MODID[604]:FSO7*/ + [570] = {0xE7752090U, 0x0000004EU}, /* RGIDR_MODID[605]:FSO8*/ + [571] = {0xE7752094U, 0x0000004EU}, /* RGIDR_MODID[606]:FSO9*/ + [572] = {0xE7752098U, 0x0000002CU}, /* RGIDR_MODID[607]:ADG*/ + [573] = {0xE775209CU, 0x0000000FU}, /* RGIDR_MODID[608]:ECMSD0*/ + [574] = {0xE77520A0U, 0x0000004EU}, /* RGIDR_MODID[609]:IPMMUDS010*/ + [575] = {0xE77520A4U, 0x0000004EU}, /* RGIDR_MODID[610]:IPMMUDS011*/ + [576] = {0xE77520A8U, 0x0000004EU}, /* RGIDR_MODID[611]:I2C0*/ + [577] = {0xE77520ACU, 0x0000004EU}, /* RGIDR_MODID[612]:I2C1*/ + [578] = {0xE77520B0U, 0x0000004EU}, /* RGIDR_MODID[613]:I2C2*/ + [579] = {0xE77520B4U, 0x0000004EU}, /* RGIDR_MODID[614]:I2C3*/ + [580] = {0xE77520C0U, 0x0000004EU}, /* RGIDR_MODID[615]:IPMMUDS012*/ + [581] = {0xE77520C8U, 0x0000004EU}, /* RGIDR_MODID[616]:IPMMUDS000*/ + [582] = {0xE77520CCU, 0x0000004EU}, /* RGIDR_MODID[617]:IPMMUDS013*/ + [583] = {0xE77520D0U, 0x0000004EU}, /* RGIDR_MODID[618]:IPMMUDS014*/ + [584] = {0xE77520D4U, 0x0000004EU}, /* RGIDR_MODID[619]:IPMMUDS015*/ + [585] = {0xE77520D8U, 0x0000004EU}, /* RGIDR_MODID[620]:IPMMUDS002*/ + [586] = {0xE77520DCU, 0x0000004EU}, /* RGIDR_MODID[621]:IPMMUDS003*/ + [587] = {0xE77520E0U, 0x0000004EU}, /* RGIDR_MODID[622]:IPMMUDS004*/ + [588] = {0xE77520E4U, 0x0000004EU}, /* RGIDR_MODID[623]:IPMMUDS005*/ + [589] = {0xE77520E8U, 0x0000002CU}, /* RGIDR_MODID[624]:SSI*/ + [590] = {0xE77520ECU, 0x0000004EU}, /* RGIDR_MODID[625]:IPMMUDS006*/ + [591] = {0xE77520F0U, 0x0000004EU}, /* RGIDR_MODID[626]:IPMMUDS007*/ + [592] = {0xE77520F4U, 0x0000000CU}, /* RGIDR_MODID[627]:SYDM1P*/ + [593] = {0xE77520F8U, 0x0000004EU}, /* RGIDR_MODID[628]:IPMMUDS008*/ + [594] = {0xE77520FCU, 0x0000000CU}, /* RGIDR_MODID[629]:SYDM2P*/ + [595] = {0xE7752100U, 0x0000004EU}, /* RGIDR_MODID[630]:IPMMUDS009*/ + [596] = {0xE7752240U, 0x0000000CU}, /* RGIDR_MODID[631]:SYDM100*/ + [597] = {0xE7752244U, 0x0000000CU}, /* RGIDR_MODID[632]:SYDM101*/ + [598] = {0xE7752248U, 0x0000000CU}, /* RGIDR_MODID[633]:SYDM110*/ + [599] = {0xE775224CU, 0x0000000CU}, /* RGIDR_MODID[634]:SYDM111*/ + [600] = {0xE7752250U, 0x0000000CU}, /* RGIDR_MODID[635]:SYDM112*/ + [601] = {0xE7752254U, 0x0000000CU}, /* RGIDR_MODID[636]:SYDM113*/ + [602] = {0xE7752258U, 0x0000000CU}, /* RGIDR_MODID[637]:SYDM114*/ + [603] = {0xE775225CU, 0x0000000CU}, /* RGIDR_MODID[638]:SYDM115*/ + [604] = {0xE7752260U, 0x0000000CU}, /* RGIDR_MODID[639]:SYDM102*/ + [605] = {0xE7752264U, 0x0000000CU}, /* RGIDR_MODID[640]:SYDM103*/ + [606] = {0xE7752268U, 0x0000000CU}, /* RGIDR_MODID[641]:SYDM104*/ + [607] = {0xE775226CU, 0x0000000CU}, /* RGIDR_MODID[642]:SYDM105*/ + [608] = {0xE7752270U, 0x0000000CU}, /* RGIDR_MODID[643]:SYDM106*/ + [609] = {0xE7752274U, 0x0000000CU}, /* RGIDR_MODID[644]:SYDM107*/ + [610] = {0xE7752278U, 0x0000000CU}, /* RGIDR_MODID[645]:SYDM108*/ + [611] = {0xE775227CU, 0x0000000CU}, /* RGIDR_MODID[646]:SYDM109*/ + [612] = {0xE7752280U, 0x0000000CU}, /* RGIDR_MODID[647]:SYDM200*/ + [613] = {0xE7752284U, 0x0000000CU}, /* RGIDR_MODID[648]:SYDM201*/ + [614] = {0xE7752288U, 0x0000000CU}, /* RGIDR_MODID[649]:SYDM210*/ + [615] = {0xE775228CU, 0x0000000CU}, /* RGIDR_MODID[650]:SYDM211*/ + [616] = {0xE7752290U, 0x0000000CU}, /* RGIDR_MODID[651]:SYDM212*/ + [617] = {0xE7752294U, 0x0000000CU}, /* RGIDR_MODID[652]:SYDM213*/ + [618] = {0xE7752298U, 0x0000000CU}, /* RGIDR_MODID[653]:SYDM214*/ + [619] = {0xE775229CU, 0x0000000CU}, /* RGIDR_MODID[654]:SYDM215*/ + [620] = {0xE77522A0U, 0x0000000CU}, /* RGIDR_MODID[655]:SYDM202*/ + [621] = {0xE77522A4U, 0x0000000CU}, /* RGIDR_MODID[656]:SYDM203*/ + [622] = {0xE77522A8U, 0x0000000CU}, /* RGIDR_MODID[657]:SYDM204*/ + [623] = {0xE77522ACU, 0x0000000CU}, /* RGIDR_MODID[658]:SYDM205*/ + [624] = {0xE77522B0U, 0x0000000CU}, /* RGIDR_MODID[659]:SYDM206*/ + [625] = {0xE77522B4U, 0x0000000CU}, /* RGIDR_MODID[660]:SYDM207*/ + [626] = {0xE77522B8U, 0x0000000CU}, /* RGIDR_MODID[661]:SYDM208*/ + [627] = {0xE77522BCU, 0x0000000CU}, /* RGIDR_MODID[662]:SYDM209*/ + [628] = {0xFE682000U, 0x0000000FU}, /* RGIDR_MODID[663]:ARVC0*/ + /* After setting */ /* RGIDR_MODID[664]:ARVC1*/ + /* After setting */ /* RGIDR_MODID[665]:ARVC2*/ + [629] = {0xFE68200CU, 0x0000000FU}, /* RGIDR_MODID[666]:ARVC3*/ + [630] = {0xFE682010U, 0x0000000EU}, /* RGIDR_MODID[667]:AXIFBABUSVC*/ + [631] = {0xFE682014U, 0x0000000FU}, /* RGIDR_MODID[668]:ARVC4*/ + [632] = {0xFE682018U, 0x0000000FU}, /* RGIDR_MODID[669]:ARVC5*/ + [633] = {0xFE68201CU, 0x0000000FU}, /* RGIDR_MODID[670]:ARVC6*/ + [634] = {0xFE682020U, 0x0000000FU}, /* RGIDR_MODID[671]:ARVC7*/ + [635] = {0xFE682024U, 0x00000000U}, /* RGIDR_MODID[672]:ARVC8*/ + [636] = {0xFE68202CU, 0x0000000FU}, /* RGIDR_MODID[673]:ECMVC0*/ + [637] = {0xFE682034U, 0x0000004EU}, /* RGIDR_MODID[674]:IMR0*/ + [638] = {0xFE682038U, 0x0000004EU}, /* RGIDR_MODID[675]:IMR1*/ + [639] = {0xFE68203CU, 0x0000004EU}, /* RGIDR_MODID[676]:IPMMUVC01*/ + [640] = {0xFE682040U, 0x0000004EU}, /* RGIDR_MODID[677]:IPMMUVC10*/ + [641] = {0xFE682044U, 0x0000000CU}, /* RGIDR_MODID[678]:IMS0*/ + [642] = {0xFE682048U, 0x0000000CU}, /* RGIDR_MODID[679]:IMS1*/ + [643] = {0xFE68204CU, 0x0000004EU}, /* RGIDR_MODID[680]:IPMMUVC00*/ + [644] = {0xFE682050U, 0x0000004EU}, /* RGIDR_MODID[681]:IPMMUVC11*/ + [645] = {0xFE682054U, 0x0000004EU}, /* RGIDR_MODID[682]:IPMMUVC12*/ + [646] = {0xFE682058U, 0x0000004EU}, /* RGIDR_MODID[683]:IPMMUVC13*/ + [647] = {0xFE68205CU, 0x0000004EU}, /* RGIDR_MODID[684]:IPMMUVC14*/ + [648] = {0xFE682060U, 0x0000004EU}, /* RGIDR_MODID[685]:IPMMUVC15*/ + [649] = {0xFE682064U, 0x0000004EU}, /* RGIDR_MODID[686]:IPMMUVC02*/ + [650] = {0xFE682068U, 0x0000004EU}, /* RGIDR_MODID[687]:IPMMUVC03*/ + [651] = {0xFE68206CU, 0x0000004EU}, /* RGIDR_MODID[688]:IPMMUVC04*/ + [652] = {0xFE682070U, 0x0000004EU}, /* RGIDR_MODID[689]:IPMMUVC05*/ + [653] = {0xFE682074U, 0x0000004EU}, /* RGIDR_MODID[690]:IPMMUVC06*/ + [654] = {0xFE682078U, 0x0000004EU}, /* RGIDR_MODID[691]:IPMMUVC07*/ + [655] = {0xFE68207CU, 0x0000004EU}, /* RGIDR_MODID[692]:IPMMUVC08*/ + [656] = {0xFE682080U, 0x0000004EU}, /* RGIDR_MODID[693]:IPMMUVC09*/ + [657] = {0xFE682084U, 0x00000028U}, /* RGIDR_MODID[694]:IV1ES*/ + [658] = {0xFEBE2000U, 0x0000004EU}, /* RGIDR_MODID[695]:CSITOP0*/ + [659] = {0xFEBE2004U, 0x0000000FU}, /* RGIDR_MODID[696]:ARVI10*/ + /* After setting */ /* RGIDR_MODID[697]:ARVI11*/ + /* After setting */ /* RGIDR_MODID[698]:ARVI12*/ + [660] = {0xFEBE2010U, 0x0000000FU}, /* RGIDR_MODID[699]:ARVI13*/ + [661] = {0xFEBE2014U, 0x0000000FU}, /* RGIDR_MODID[700]:ARVI14*/ + [662] = {0xFEBE2018U, 0x0000000FU}, /* RGIDR_MODID[701]:ARVI15*/ + [663] = {0xFEBE201CU, 0x0000000FU}, /* RGIDR_MODID[702]:ARVI16*/ + [664] = {0xFEBE2020U, 0x0000000FU}, /* RGIDR_MODID[703]:ARVI17*/ + [665] = {0xFEBE2024U, 0x00000000U}, /* RGIDR_MODID[704]:ARVI18*/ + [666] = {0xFEBE202CU, 0x0000004EU}, /* RGIDR_MODID[705]:CSITOP1*/ + [667] = {0xFEBE2034U, 0x0000004EU}, /* RGIDR_MODID[706]:DSITLINK0*/ + [668] = {0xFEBE203CU, 0x0000000FU}, /* RGIDR_MODID[707]:ECMVIO1*/ + [669] = {0xFEBE2044U, 0x0000004EU}, /* RGIDR_MODID[708]:IPMMUVI001*/ + [670] = {0xFEBE2048U, 0x0000000CU}, /* RGIDR_MODID[709]:FCPVX0*/ + [671] = {0xFEBE2058U, 0x0000004EU}, /* RGIDR_MODID[710]:IPMMUVI000*/ + [672] = {0xFEBE205CU, 0x0000004EU}, /* RGIDR_MODID[711]:IPMMUVI100*/ + [673] = {0xFEBE2060U, 0x0000004EU}, /* RGIDR_MODID[712]:IPMMUVI010*/ + [674] = {0xFEBE2064U, 0x0000004EU}, /* RGIDR_MODID[713]:IPMMUVI011*/ + [675] = {0xFEBE2068U, 0x0000004EU}, /* RGIDR_MODID[714]:VSPX0*/ + [676] = {0xFEBE2078U, 0x0000004EU}, /* RGIDR_MODID[715]:IPMMUVI012*/ + [677] = {0xFEBE207CU, 0x0000004EU}, /* RGIDR_MODID[716]:IPMMUVI013*/ + [678] = {0xFEBE2080U, 0x0000004EU}, /* RGIDR_MODID[717]:IPMMUVI014*/ + [679] = {0xFEBE2084U, 0x0000004EU}, /* RGIDR_MODID[718]:IPMMUVI015*/ + [680] = {0xFEBE2088U, 0x0000004EU}, /* RGIDR_MODID[719]:IPMMUVI002*/ + [681] = {0xFEBE208CU, 0x0000004EU}, /* RGIDR_MODID[720]:IPMMUVI003*/ + [682] = {0xFEBE2090U, 0x0000004EU}, /* RGIDR_MODID[721]:IPMMUVI004*/ + [683] = {0xFEBE2094U, 0x0000004EU}, /* RGIDR_MODID[722]:IPMMUVI005*/ + [684] = {0xFEBE2098U, 0x0000004EU}, /* RGIDR_MODID[723]:IPMMUVI006*/ + [685] = {0xFEBE209CU, 0x0000004EU}, /* RGIDR_MODID[724]:IPMMUVI007*/ + [686] = {0xFEBE20A0U, 0x0000004EU}, /* RGIDR_MODID[725]:IPMMUVI008*/ + [687] = {0xFEBE20A4U, 0x0000004EU}, /* RGIDR_MODID[726]:IPMMUVI009*/ + [688] = {0xFEBE20A8U, 0x0000004EU}, /* RGIDR_MODID[727]:IPMMUVI101*/ + [689] = {0xFEBE20ACU, 0x0000004EU}, /* RGIDR_MODID[728]:IPMMUVI110*/ + [690] = {0xFEBE20B0U, 0x0000004EU}, /* RGIDR_MODID[729]:IPMMUVI111*/ + [691] = {0xFEBE20B4U, 0x0000004EU}, /* RGIDR_MODID[730]:IPMMUVI112*/ + [692] = {0xFEBE20B8U, 0x0000004EU}, /* RGIDR_MODID[731]:IPMMUVI113*/ + [693] = {0xFEBE20BCU, 0x0000004EU}, /* RGIDR_MODID[732]:IPMMUVI114*/ + [694] = {0xFEBE20C0U, 0x0000004EU}, /* RGIDR_MODID[733]:IPMMUVI115*/ + [695] = {0xFEBE20C4U, 0x0000004EU}, /* RGIDR_MODID[734]:IPMMUVI102*/ + [696] = {0xFEBE20C8U, 0x0000004EU}, /* RGIDR_MODID[735]:IPMMUVI103*/ + [697] = {0xFEBE20CCU, 0x0000004EU}, /* RGIDR_MODID[736]:IPMMUVI104*/ + [698] = {0xFEBE20D0U, 0x0000004EU}, /* RGIDR_MODID[737]:IPMMUVI105*/ + [699] = {0xFEBE20D4U, 0x0000004EU}, /* RGIDR_MODID[738]:IPMMUVI106*/ + [700] = {0xFEBE20D8U, 0x0000004EU}, /* RGIDR_MODID[739]:IPMMUVI107*/ + [701] = {0xFEBE20DCU, 0x0000004EU}, /* RGIDR_MODID[740]:IPMMUVI108*/ + [702] = {0xFEBE20E0U, 0x0000004EU}, /* RGIDR_MODID[741]:IPMMUVI109*/ + [703] = {0xFEBE2104U, 0x0000000EU}, /* RGIDR_MODID[742]:AXIFBABUSVIO*/ + [704] = {0xFEBF2000U, 0x0000000FU}, /* RGIDR_MODID[743]:ARVI0*/ + /* After setting */ /* RGIDR_MODID[744]:ARVI1*/ + /* After setting */ /* RGIDR_MODID[745]:ARVI2*/ + [705] = {0xFEBF200CU, 0x0000000FU}, /* RGIDR_MODID[746]:ARVI3*/ + [706] = {0xFEBF2010U, 0x0000000FU}, /* RGIDR_MODID[747]:ARVI4*/ + [707] = {0xFEBF2014U, 0x0000000FU}, /* RGIDR_MODID[748]:ARVI5*/ + [708] = {0xFEBF2018U, 0x0000000FU}, /* RGIDR_MODID[749]:ARVI6*/ + [709] = {0xFEBF201CU, 0x0000000FU}, /* RGIDR_MODID[750]:ARVI7*/ + [710] = {0xFEBF2020U, 0x00000000U}, /* RGIDR_MODID[751]:ARVI8*/ + [711] = {0xFEBF2024U, 0x0000000FU}, /* RGIDR_MODID[752]:ECMVIO0*/ + [712] = {0xFEBF2028U, 0x0000004EU}, /* RGIDR_MODID[753]:ISP0*/ + [713] = {0xFEBF202CU, 0x0000004EU}, /* RGIDR_MODID[754]:ISP0CORE*/ + [714] = {0xFEBF2030U, 0x0000004EU}, /* RGIDR_MODID[755]:ISP1*/ + [715] = {0xFEBF2054U, 0x0000004EU}, /* RGIDR_MODID[756]:VIN00*/ + [716] = {0xFEBF2058U, 0x0000004EU}, /* RGIDR_MODID[757]:VIN01*/ + [717] = {0xFEBF205CU, 0x0000004EU}, /* RGIDR_MODID[758]:VIN02*/ + [718] = {0xFEBF2060U, 0x0000004EU}, /* RGIDR_MODID[759]:VIN03*/ + [719] = {0xFEBF2064U, 0x0000004EU}, /* RGIDR_MODID[760]:VIN04*/ + [720] = {0xFEBF2068U, 0x0000004EU}, /* RGIDR_MODID[761]:VIN05*/ + [721] = {0xFEBF206CU, 0x0000004EU}, /* RGIDR_MODID[762]:VIN06*/ + [722] = {0xFEBF2070U, 0x0000004EU}, /* RGIDR_MODID[763]:VIN07*/ + [723] = {0xFEBF2074U, 0x0000004EU}, /* RGIDR_MODID[764]:VIN10*/ + [724] = {0xFEBF2078U, 0x0000004EU}, /* RGIDR_MODID[765]:VIN11*/ + [725] = {0xFEBF207CU, 0x0000004EU}, /* RGIDR_MODID[766]:VIN12*/ + [726] = {0xFEBF2080U, 0x0000004EU}, /* RGIDR_MODID[767]:VIN13*/ + [727] = {0xFEBF2084U, 0x0000004EU}, /* RGIDR_MODID[768]:VIN14*/ + [728] = {0xFEBF2088U, 0x0000004EU}, /* RGIDR_MODID[769]:VIN15*/ + [729] = {0xFEBF208CU, 0x0000004EU}, /* RGIDR_MODID[770]:VIN16*/ + [730] = {0xFEBF2090U, 0x0000004EU}, /* RGIDR_MODID[771]:VIN17*/ + [731] = {0xE7B12000U, 0x0000000FU}, /* RGIDR_MODID[772]:ARVIP00*/ + /* After setting */ /* RGIDR_MODID[773]:ARVIP01*/ + /* After setting */ /* RGIDR_MODID[774]:ARVIP02*/ + [732] = {0xE7B1200CU, 0x0000000FU}, /* RGIDR_MODID[775]:ARVIP03*/ + [733] = {0xE7B12010U, 0x0000000EU}, /* RGIDR_MODID[776]:AXIFBABUSVIP0*/ + [734] = {0xE7B12014U, 0x0000000FU}, /* RGIDR_MODID[777]:ARVIP04*/ + [735] = {0xE7B12018U, 0x0000000FU}, /* RGIDR_MODID[778]:ARVIP05*/ + [736] = {0xE7B1201CU, 0x0000000FU}, /* RGIDR_MODID[779]:ARVIP06*/ + [737] = {0xE7B12020U, 0x00000007U}, /* RGIDR_MODID[780]:ARVIP07*/ + [738] = {0xE7B12024U, 0x00000000U}, /* RGIDR_MODID[781]:ARVIP08*/ + [739] = {0xE7B1202CU, 0x0000000FU}, /* RGIDR_MODID[782]:ECMVIP0*/ + [740] = {0xE7B12030U, 0x0000004EU}, /* RGIDR_MODID[783]:IPMMUVIP000*/ + [741] = {0xE7B12038U, 0x0000004EU}, /* RGIDR_MODID[784]:SMPO0*/ + [742] = {0xE7B1203CU, 0x0000004EU}, /* RGIDR_MODID[785]:SMPS0*/ + [743] = {0xE7B12040U, 0x0000004EU}, /* RGIDR_MODID[786]:UMFL0*/ + [744] = {0xE7B12044U, 0x0000004EU}, /* RGIDR_MODID[787]:IPMMUVIP001*/ + [745] = {0xE7B12048U, 0x0000004EU}, /* RGIDR_MODID[788]:IPMMUVIP010*/ + [746] = {0xE7B1204CU, 0x0000004EU}, /* RGIDR_MODID[789]:IPMMUVIP011*/ + [747] = {0xE7B12050U, 0x0000004EU}, /* RGIDR_MODID[790]:UMFL0M_W*/ + [748] = {0xE7B12054U, 0x0000004EU}, /* RGIDR_MODID[791]:IPMMUVIP012*/ + [749] = {0xE7B12058U, 0x0000004EU}, /* RGIDR_MODID[792]:IPMMUVIP013*/ + [750] = {0xE7B1205CU, 0x0000004EU}, /* RGIDR_MODID[793]:IPMMUVIP014*/ + [751] = {0xE7B12060U, 0x0000004EU}, /* RGIDR_MODID[794]:IPMMUVIP015*/ + [752] = {0xE7B12064U, 0x0000004EU}, /* RGIDR_MODID[795]:IPMMUVIP002*/ + [753] = {0xE7B12068U, 0x0000004EU}, /* RGIDR_MODID[796]:IPMMUVIP003*/ + [754] = {0xE7B1206CU, 0x0000004EU}, /* RGIDR_MODID[797]:IPMMUVIP004*/ + [755] = {0xE7B12070U, 0x0000004EU}, /* RGIDR_MODID[798]:IPMMUVIP005*/ + [756] = {0xE7B12074U, 0x0000004EU}, /* RGIDR_MODID[799]:IPMMUVIP006*/ + [757] = {0xE7B12078U, 0x0000004EU}, /* RGIDR_MODID[800]:IPMMUVIP007*/ + [758] = {0xE7B1207CU, 0x0000004EU}, /* RGIDR_MODID[801]:IPMMUVIP008*/ + [759] = {0xE7B12080U, 0x0000004EU}, /* RGIDR_MODID[802]:IPMMUVIP009*/ + [760] = {0xFF8820A0U, 0x0000000FU}, /* RGIDR_MODID[803]:ARDSP0*/ + /* After setting */ /* RGIDR_MODID[804]:ARDSP1*/ + /* After setting */ /* RGIDR_MODID[805]:ARDSP2*/ + [761] = {0xFF8820ACU, 0x0000000FU}, /* RGIDR_MODID[806]:ARDSP3*/ + [762] = {0xFF8820B0U, 0x0000000FU}, /* RGIDR_MODID[807]:ARDSP4*/ + [763] = {0xFF8820B4U, 0x0000000FU}, /* RGIDR_MODID[808]:ARDSP5*/ + [764] = {0xFF8820B8U, 0x0000000FU}, /* RGIDR_MODID[809]:ARDSP6*/ + [765] = {0xFF8820BCU, 0x0000000FU}, /* RGIDR_MODID[810]:ARDSP7*/ + [766] = {0xFF8820C0U, 0x0000000FU}, /* RGIDR_MODID[811]:ECMDSP*/ + [767] = {0xFF882090U, 0x0000000CU}, /* RGIDR_MODID[812]:AXIDSP0*/ + [768] = {0xFF882094U, 0x0000000CU}, /* RGIDR_MODID[813]:AXIDSP1*/ + [769] = {0xFF882098U, 0x0000000CU}, /* RGIDR_MODID[814]:AXIDSP2*/ + [770] = {0xFF88209CU, 0x0000000CU}, /* RGIDR_MODID[815]:AXIDSP3*/ + [771] = {0xFF8820C4U, 0x0000004EU}, /* RGIDR_MODID[816]:IMPM0100*/ + [772] = {0xFF8820C8U, 0x0000004EU}, /* RGIDR_MODID[817]:IMPM0101*/ + [773] = {0xFF8820CCU, 0x0000004EU}, /* RGIDR_MODID[818]:IMPM0102*/ + [774] = {0xFF8820D0U, 0x0000004EU}, /* RGIDR_MODID[819]:IMPM0103*/ + [775] = {0xFF8820D4U, 0x0000004EU}, /* RGIDR_MODID[820]:IMPM0104*/ + [776] = {0xFF8820D8U, 0x0000004EU}, /* RGIDR_MODID[821]:IMPM0105*/ + [777] = {0xFF8820DCU, 0x0000004EU}, /* RGIDR_MODID[822]:IMPM0106*/ + [778] = {0xFF8820E0U, 0x0000004EU}, /* RGIDR_MODID[823]:IMPM0107*/ + [779] = {0xFF8820E4U, 0x0000004EU}, /* RGIDR_MODID[824]:IMPM0200*/ + [780] = {0xFF8820E8U, 0x0000004EU}, /* RGIDR_MODID[825]:IMPM0201*/ + [781] = {0xFF8820ECU, 0x0000004EU}, /* RGIDR_MODID[826]:IMPS0000*/ + [782] = {0xFF8820F0U, 0x0000004EU}, /* RGIDR_MODID[827]:IMPS0001*/ + [783] = {0xFF8820F4U, 0x0000004EU}, /* RGIDR_MODID[828]:IMPS0002*/ + [784] = {0xFF8820F8U, 0x0000004EU}, /* RGIDR_MODID[829]:IMPS0003*/ + [785] = {0xFF8820FCU, 0x0000004EU}, /* RGIDR_MODID[830]:IMPS0100*/ + [786] = {0xFF882100U, 0x0000004EU}, /* RGIDR_MODID[831]:IMPS0101*/ + [787] = {0xFF882104U, 0x0000004EU}, /* RGIDR_MODID[832]:IMPS0102*/ + [788] = {0xFF882108U, 0x0000004EU}, /* RGIDR_MODID[833]:IMPS0103*/ + [789] = {0xFF88210CU, 0x0000004EU}, /* RGIDR_MODID[834]:IMPS0104*/ + [790] = {0xFF882110U, 0x0000004EU}, /* RGIDR_MODID[835]:IMPS0105*/ + [791] = {0xFF882114U, 0x0000004EU}, /* RGIDR_MODID[836]:IMPS0106*/ + [792] = {0xFF882118U, 0x0000004EU}, /* RGIDR_MODID[837]:IMPS0107*/ + [793] = {0xFF88211CU, 0x0000004EU}, /* RGIDR_MODID[838]:IMPS0108*/ + [794] = {0xFF882120U, 0x0000004EU}, /* RGIDR_MODID[839]:IMPS0109*/ + [795] = {0xFF882124U, 0x0000004EU}, /* RGIDR_MODID[840]:IMPS0110*/ + [796] = {0xFF882128U, 0x0000004EU}, /* RGIDR_MODID[841]:IMPS0111*/ + [797] = {0xFF88212CU, 0x0000004EU}, /* RGIDR_MODID[842]:IMPS0200*/ + [798] = {0xFF882130U, 0x0000004EU}, /* RGIDR_MODID[843]:IMPS0201*/ + [799] = {0xFF882134U, 0x0000004EU}, /* RGIDR_MODID[844]:IMPS0202*/ + [801] = {0xE67B9660U, 0x0000000FU}, /* RGIDR_MODID[845]:ARCC*/ + [800] = {0xE67B9674U, 0x0000000FU}, /* RGIDR_MODID[846]:ARRTRAM*/ + [802] = {0xE7752024U, 0x00000000U}, /* RGIDR_MODID[847]:RSV0*/ + [803] = {0xE7B1210CU, 0x00000004U}, /* RGIDR_MODID[848]:PAP*/ + [804] = {0xFEBD2028U, 0x0000000CU}, /* RGIDR_MODID[849]:DOC*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_w_tbl" +#else +__attribute__ ((section(".rgid_w_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_write_tbl[] = { + [0] = {0xFFC82400U, 0x0000000EU}, /* RGIDW_MODID[0]:ARMGC0*/ + [1] = {0xFFC82404U, 0x0000000EU}, /* RGIDW_MODID[1]:ARMGC1*/ + [2] = {0xFFC82408U, 0x00000000U}, /* RGIDW_MODID[2]:ARMGC2*/ + [3] = {0xFFC8240CU, 0x00000002U}, /* RGIDW_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDW_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDW_MODID[5]:ARRT02*/ + [4] = {0xFFC82418U, 0x00000001U}, /* RGIDW_MODID[6]:ARRT03*/ + [5] = {0xFFC8241CU, 0x00000002U}, /* RGIDW_MODID[7]:ARRT04*/ + [6] = {0xFFC82420U, 0x00000001U}, /* RGIDW_MODID[8]:ARRT05*/ + [7] = {0xFFC82424U, 0x00000002U}, /* RGIDW_MODID[9]:ARRT06*/ + [8] = {0xFFC82428U, 0x00000002U}, /* RGIDW_MODID[10]:ARRT07*/ + [9] = {0xFFC8242CU, 0x00000000U}, /* RGIDW_MODID[11]:ARRT08*/ + [10] = {0xFFC82430U, 0x00000001U}, /* RGIDW_MODID[12]:LIFEC0*/ + [11] = {0xFFC82434U, 0x0000000EU}, /* RGIDW_MODID[13]:SWDT*/ + [12] = {0xFFC82438U, 0x0000006EU}, /* RGIDW_MODID[14]:TMU0*/ + [13] = {0xFFC8243CU, 0x0000000EU}, /* RGIDW_MODID[15]:WDT*/ + [14] = {0xFFC82440U, 0x0000000EU}, /* RGIDW_MODID[16]:WWDT0*/ + [15] = {0xFFC82444U, 0x0000000EU}, /* RGIDW_MODID[17]:WWDT1*/ + [16] = {0xFFC82448U, 0x0000000EU}, /* RGIDW_MODID[18]:WWDT2*/ + [17] = {0xFFC8244CU, 0x0000000EU}, /* RGIDW_MODID[19]:WWDT3*/ + [18] = {0xFFC82450U, 0x0000000EU}, /* RGIDW_MODID[20]:WWDT4*/ + [19] = {0xFFC82454U, 0x0000000EU}, /* RGIDW_MODID[21]:WWDT5*/ + [20] = {0xFFC82458U, 0x0000000EU}, /* RGIDW_MODID[22]:WWDT6*/ + [21] = {0xFFC82468U, 0x0000000AU}, /* RGIDW_MODID[23]:ECMRT3*/ + [22] = {0xE6002404U, 0x0000000FU}, /* RGIDW_MODID[24]:APMU0*/ + [23] = {0xE6002408U, 0x00000002U}, /* RGIDW_MODID[25]:APMU1*/ + [24] = {0xE600240CU, 0x00000000U}, /* RGIDW_MODID[26]:APMU10*/ + [25] = {0xE6002410U, 0x00000000U}, /* RGIDW_MODID[27]:APMU11*/ + [26] = {0xE6002414U, 0x00000000U}, /* RGIDW_MODID[28]:APMU12*/ + [27] = {0xE6002418U, 0x00000000U}, /* RGIDW_MODID[29]:APMU13*/ + [28] = {0xE600241CU, 0x00000000U}, /* RGIDW_MODID[30]:APMU14*/ + [29] = {0xE6002420U, 0x00000000U}, /* RGIDW_MODID[31]:APMU15*/ + [30] = {0xE6002424U, 0x00000004U}, /* RGIDW_MODID[32]:APMU2*/ + [31] = {0xE6002428U, 0x00000004U}, /* RGIDW_MODID[33]:APMU3*/ + [32] = {0xE600242CU, 0x00000000U}, /* RGIDW_MODID[34]:APMU4*/ + [33] = {0xE6002430U, 0x00000000U}, /* RGIDW_MODID[35]:APMU5*/ + [34] = {0xE6002434U, 0x00000000U}, /* RGIDW_MODID[36]:APMU6*/ + [35] = {0xE6002438U, 0x00000000U}, /* RGIDW_MODID[37]:APMU7*/ + [36] = {0xE600243CU, 0x00000000U}, /* RGIDW_MODID[38]:APMU8*/ + [37] = {0xE6002440U, 0x00000000U}, /* RGIDW_MODID[39]:APMU9*/ + [38] = {0xE6002444U, 0x00000002U}, /* RGIDW_MODID[40]:ARS00*/ + /* After setting */ /* RGIDW_MODID[41]:ARS01*/ + /* After setting */ /* RGIDW_MODID[42]:ARS02*/ + [39] = {0xE6002450U, 0x00000001U}, /* RGIDW_MODID[43]:ARS03*/ + [40] = {0xE6002454U, 0x00000002U}, /* RGIDW_MODID[44]:ARS04*/ + [41] = {0xE6002458U, 0x00000001U}, /* RGIDW_MODID[45]:ARS05*/ + [42] = {0xE600245CU, 0x00000002U}, /* RGIDW_MODID[46]:ARS06*/ + [43] = {0xE6002460U, 0x00000002U}, /* RGIDW_MODID[47]:ARS07*/ + [44] = {0xE6002464U, 0x00000000U}, /* RGIDW_MODID[48]:ARS08*/ + [45] = {0xE6002468U, 0x0000000EU}, /* RGIDW_MODID[49]:CMT0*/ + [46] = {0xE600246CU, 0x0000000EU}, /* RGIDW_MODID[50]:CMT1*/ + [47] = {0xE6002470U, 0x0000000EU}, /* RGIDW_MODID[51]:CMT2*/ + [48] = {0xE6002474U, 0x0000000EU}, /* RGIDW_MODID[52]:CMT3*/ + [49] = {0xE6002478U, 0x0000000AU}, /* RGIDW_MODID[53]:CKM*/ + [50] = {0xE600247CU, 0x0000000EU}, /* RGIDW_MODID[54]:DBE*/ + [51] = {0xE6002480U, 0x0000000EU}, /* RGIDW_MODID[55]:IRQC*/ + [52] = {0xE6002484U, 0x0000000AU}, /* RGIDW_MODID[56]:ECMPS0*/ + [53] = {0xE6002488U, 0x0000000BU}, /* RGIDW_MODID[57]:OTP0*/ + [54] = {0xE600248CU, 0x0000000FU}, /* RGIDW_MODID[58]:OTP1*/ + [55] = {0xE600249CU, 0x0000000EU}, /* RGIDW_MODID[59]:SCMT*/ + [56] = {0xE60024A8U, 0x0000004AU}, /* RGIDW_MODID[60]:TSC1*/ + [57] = {0xE60024ACU, 0x0000004AU}, /* RGIDW_MODID[61]:TSC2*/ + [58] = {0xE60024B8U, 0x00000006U}, /* RGIDW_MODID[62]:UCMT*/ + [59] = {0xE6002500U, 0x0000006FU}, /* RGIDW_MODID[63]:CPG0*/ + [60] = {0xE6002504U, 0x0000000AU}, /* RGIDW_MODID[64]:CPG1*/ + [61] = {0xE6002508U, 0x0000004EU}, /* RGIDW_MODID[65]:CPG2*/ + [62] = {0xE600250CU, 0x00000028U}, /* RGIDW_MODID[66]:CPG3*/ + [63] = {0xE6002510U, 0x0000006FU}, /* RGIDW_MODID[67]:PFC00*/ + [64] = {0xE6002514U, 0x0000000AU}, /* RGIDW_MODID[68]:PFC01*/ + [65] = {0xE6002518U, 0x0000004EU}, /* RGIDW_MODID[69]:PFC02*/ + [66] = {0xE600251CU, 0x00000028U}, /* RGIDW_MODID[70]:PFC03*/ + [67] = {0xE6002520U, 0x0000006FU}, /* RGIDW_MODID[71]:PFC10*/ + [68] = {0xE6002524U, 0x0000000AU}, /* RGIDW_MODID[72]:PFC11*/ + [69] = {0xE6002528U, 0x0000004EU}, /* RGIDW_MODID[73]:PFC12*/ + [70] = {0xE600252CU, 0x00000028U}, /* RGIDW_MODID[74]:PFC13*/ + [71] = {0xE6002530U, 0x0000006FU}, /* RGIDW_MODID[75]:PFC20*/ + [72] = {0xE6002534U, 0x0000000AU}, /* RGIDW_MODID[76]:PFC21*/ + [73] = {0xE6002538U, 0x0000004EU}, /* RGIDW_MODID[77]:PFC22*/ + [74] = {0xE600253CU, 0x00000028U}, /* RGIDW_MODID[78]:PFC23*/ + [75] = {0xE6002550U, 0x0000006FU}, /* RGIDW_MODID[79]:PFCS0*/ + [76] = {0xE6002554U, 0x0000000AU}, /* RGIDW_MODID[80]:PFCS1*/ + [77] = {0xE6002558U, 0x0000004EU}, /* RGIDW_MODID[81]:PFCS2*/ + [78] = {0xE600255CU, 0x00000028U}, /* RGIDW_MODID[82]:PFCS3*/ + [79] = {0xE6002560U, 0x0000006FU}, /* RGIDW_MODID[83]:RESET0*/ + [80] = {0xE6002564U, 0x0000000AU}, /* RGIDW_MODID[84]:RESET1*/ + [81] = {0xE6002568U, 0x0000004EU}, /* RGIDW_MODID[85]:RESET2*/ + [82] = {0xE600256CU, 0x00000028U}, /* RGIDW_MODID[86]:RESET3*/ + [83] = {0xE6002570U, 0x0000006FU}, /* RGIDW_MODID[87]:SYS0*/ + [84] = {0xE6002574U, 0x0000000AU}, /* RGIDW_MODID[88]:SYS1*/ + [85] = {0xE6002578U, 0x0000004EU}, /* RGIDW_MODID[89]:SYS2*/ + [86] = {0xE600257CU, 0x00000028U}, /* RGIDW_MODID[90]:SYS3*/ + [87] = {0xE7762400U, 0x0000000EU}, /* RGIDW_MODID[91]:DMAMSI0*/ + [88] = {0xE7762404U, 0x0000000EU}, /* RGIDW_MODID[92]:DMAMSI1*/ + [89] = {0xE7762408U, 0x0000000EU}, /* RGIDW_MODID[93]:DMAMSI2*/ + [90] = {0xE776240CU, 0x0000000EU}, /* RGIDW_MODID[94]:DMAMSI3*/ + [91] = {0xE7762410U, 0x0000000EU}, /* RGIDW_MODID[95]:DMAMSI4*/ + [92] = {0xE7762414U, 0x0000000EU}, /* RGIDW_MODID[96]:DMAMSI5*/ + [93] = {0xE7762418U, 0x0000000AU}, /* RGIDW_MODID[97]:ECMSP3*/ + [94] = {0xE7762424U, 0x00000002U}, /* RGIDW_MODID[98]:ARSP30*/ + /* After setting */ /* RGIDW_MODID[99]:ARSP31*/ + /* After setting */ /* RGIDW_MODID[100]:ARSP32*/ + [95] = {0xE7762430U, 0x00000001U}, /* RGIDW_MODID[101]:ARSP33*/ + [96] = {0xE7762434U, 0x00000002U}, /* RGIDW_MODID[102]:ARSP34*/ + [97] = {0xE7762438U, 0x00000001U}, /* RGIDW_MODID[103]:ARSP35*/ + [98] = {0xE776243CU, 0x00000002U}, /* RGIDW_MODID[104]:ARSP36*/ + [99] = {0xE7762440U, 0x00000002U}, /* RGIDW_MODID[105]:ARSP37*/ + [100] = {0xE7762444U, 0x00000000U}, /* RGIDW_MODID[106]:ARSP38*/ + [101] = {0xE7762448U, 0x0000000EU}, /* RGIDW_MODID[107]:MSI0*/ + [102] = {0xE776244CU, 0x0000000EU}, /* RGIDW_MODID[108]:MSI1*/ + [103] = {0xE7762450U, 0x0000000EU}, /* RGIDW_MODID[109]:MSI2*/ + [104] = {0xE7762454U, 0x0000000EU}, /* RGIDW_MODID[110]:MSI3*/ + [105] = {0xE7762458U, 0x0000000EU}, /* RGIDW_MODID[111]:MSI4*/ + [106] = {0xE776245CU, 0x0000000EU}, /* RGIDW_MODID[112]:MSI5*/ + [107] = {0xE7792400U, 0x00000002U}, /* RGIDW_MODID[113]:ARSP40*/ + /* After setting */ /* RGIDW_MODID[114]:ARSP41*/ + /* After setting */ /* RGIDW_MODID[115]:ARSP42*/ + [108] = {0xE779240CU, 0x00000001U}, /* RGIDW_MODID[116]:ARSP43*/ + [109] = {0xE7792410U, 0x00000002U}, /* RGIDW_MODID[117]:ARSP44*/ + [110] = {0xE7792414U, 0x00000001U}, /* RGIDW_MODID[118]:ARSP45*/ + [111] = {0xE7792418U, 0x00000002U}, /* RGIDW_MODID[119]:ARSP46*/ + [112] = {0xE779241CU, 0x00000002U}, /* RGIDW_MODID[120]:ARSP47*/ + [113] = {0xE7792420U, 0x00000000U}, /* RGIDW_MODID[121]:ARSP48*/ + [114] = {0xE7792424U, 0x0000004FU}, /* RGIDW_MODID[122]:DMAHSCIF0*/ + [115] = {0xE7792428U, 0x0000004FU}, /* RGIDW_MODID[123]:DMAHSCIF1*/ + [116] = {0xE779242CU, 0x0000004FU}, /* RGIDW_MODID[124]:DMAHSCIF2*/ + [117] = {0xE7792430U, 0x0000004FU}, /* RGIDW_MODID[125]:DMAHSCIF3*/ + [118] = {0xE7792434U, 0x0000004FU}, /* RGIDW_MODID[126]:DMASCIF0*/ + [119] = {0xE7792438U, 0x0000004FU}, /* RGIDW_MODID[127]:DMASCIF1*/ + [120] = {0xE779243CU, 0x0000004FU}, /* RGIDW_MODID[128]:DMASCIF3*/ + [121] = {0xE7792440U, 0x0000004FU}, /* RGIDW_MODID[129]:DMASCIF4*/ + [122] = {0xE7792444U, 0x0000000AU}, /* RGIDW_MODID[130]:ECMSP4*/ + [123] = {0xE7792448U, 0x0000004FU}, /* RGIDW_MODID[131]:HSCIF0*/ + [124] = {0xE779244CU, 0x0000004FU}, /* RGIDW_MODID[132]:HSCIF1*/ + [125] = {0xE7792450U, 0x0000004FU}, /* RGIDW_MODID[133]:HSCIF2*/ + [126] = {0xE7792454U, 0x0000004FU}, /* RGIDW_MODID[134]:HSCIF3*/ + [127] = {0xE7792458U, 0x0000004FU}, /* RGIDW_MODID[135]:SCIF0*/ + [128] = {0xE779245CU, 0x0000004FU}, /* RGIDW_MODID[136]:SCIF1*/ + [129] = {0xE7792460U, 0x0000004FU}, /* RGIDW_MODID[137]:SCIF3*/ + [130] = {0xE7792464U, 0x0000004FU}, /* RGIDW_MODID[138]:SCIF4*/ + [131] = {0xE7792468U, 0x0000006EU}, /* RGIDW_MODID[139]:TMU1*/ + [132] = {0xE779246CU, 0x0000006EU}, /* RGIDW_MODID[140]:TMU2*/ + [133] = {0xE7792470U, 0x0000006EU}, /* RGIDW_MODID[141]:TMU3*/ + [134] = {0xE7792474U, 0x0000006EU}, /* RGIDW_MODID[142]:TMU4*/ + [135] = {0xE7792478U, 0x0000004AU}, /* RGIDW_MODID[143]:CANFD*/ + [136] = {0xE779247CU, 0x0000004AU}, /* RGIDW_MODID[144]:DMACANFD*/ + [137] = {0xE7792480U, 0x00000002U}, /* RGIDW_MODID[145]:DMATPU0*/ + [138] = {0xE7792484U, 0x00000002U}, /* RGIDW_MODID[146]:PWM0*/ + [139] = {0xE7792488U, 0x00000002U}, /* RGIDW_MODID[147]:PWM1*/ + [140] = {0xE779248CU, 0x00000002U}, /* RGIDW_MODID[148]:PWM2*/ + [141] = {0xE7792490U, 0x00000002U}, /* RGIDW_MODID[149]:PWM3*/ + [142] = {0xE7792494U, 0x00000002U}, /* RGIDW_MODID[150]:PWM4*/ + [143] = {0xE77924ACU, 0x00000002U}, /* RGIDW_MODID[151]:TPU0*/ + [144] = {0xFEBD2400U, 0x00000002U}, /* RGIDW_MODID[152]:ARVI40*/ + /* After setting */ /* RGIDW_MODID[153]:ARVI41*/ + /* After setting */ /* RGIDW_MODID[154]:ARVI42*/ + [145] = {0xFEBD240CU, 0x00000001U}, /* RGIDW_MODID[155]:ARVI43*/ + [146] = {0xFEBD2410U, 0x00000002U}, /* RGIDW_MODID[156]:ARVI44*/ + [147] = {0xFEBD2414U, 0x00000001U}, /* RGIDW_MODID[157]:ARVI45*/ + [148] = {0xFEBD2418U, 0x00000002U}, /* RGIDW_MODID[158]:ARVI46*/ + [149] = {0xFEBD241CU, 0x00000002U}, /* RGIDW_MODID[159]:ARVI47*/ + [150] = {0xFEBD2420U, 0x00000000U}, /* RGIDW_MODID[160]:ARVI48*/ + [151] = {0xFEBD2424U, 0x0000000FU}, /* RGIDW_MODID[161]:DIS0*/ + [152] = {0xFEBD2430U, 0x0000000EU}, /* RGIDW_MODID[162]:ECMVIO2*/ + [153] = {0xFEBD2434U, 0x0000000FU}, /* RGIDW_MODID[163]:FCPVD0*/ + [154] = {0xFEBD243CU, 0x0000004EU}, /* RGIDW_MODID[164]:VSPD0*/ + [155] = {0xE6582400U, 0x0000000AU}, /* RGIDW_MODID[165]:CKMHSC*/ + [156] = {0xE6582404U, 0x0000000CU}, /* RGIDW_MODID[166]:AXIPCI001*/ + [157] = {0xE6582408U, 0x0000000CU}, /* RGIDW_MODID[167]:AXIPCI002*/ + [158] = {0xE658240CU, 0x0000000CU}, /* RGIDW_MODID[168]:AXIPCI003*/ + [159] = {0xE6582414U, 0x0000000CU}, /* RGIDW_MODID[169]:AXIPCI005*/ + [160] = {0xE6582418U, 0x0000000CU}, /* RGIDW_MODID[170]:AXIPCI006*/ + [161] = {0xE658241CU, 0x0000000CU}, /* RGIDW_MODID[171]:AXIPCI007*/ + [162] = {0xE6582420U, 0x0000000CU}, /* RGIDW_MODID[172]:AXIPCI008*/ + [163] = {0xE6582424U, 0x0000000CU}, /* RGIDW_MODID[173]:AXIPCI009*/ + [164] = {0xE6582428U, 0x0000000CU}, /* RGIDW_MODID[174]:AXIPCI010*/ + [165] = {0xE658242CU, 0x0000000CU}, /* RGIDW_MODID[175]:AXIPCI011*/ + [166] = {0xE6582430U, 0x0000000CU}, /* RGIDW_MODID[176]:AXIPCI012*/ + [167] = {0xE6582434U, 0x0000000CU}, /* RGIDW_MODID[177]:AXIPCI013*/ + [168] = {0xE6582438U, 0x0000000CU}, /* RGIDW_MODID[178]:AXIPCI014*/ + [169] = {0xE658243CU, 0x0000000CU}, /* RGIDW_MODID[179]:AXIPCI015*/ + [170] = {0xE6582484U, 0x0000000EU}, /* RGIDW_MODID[180]:GPTP*/ + [171] = {0xE6582488U, 0x0000004EU}, /* RGIDW_MODID[181]:IPMMUHC00*/ + [172] = {0xE65824F4U, 0x0000000CU}, /* RGIDW_MODID[182]:AXIPCI000*/ + [173] = {0xE65824F8U, 0x0000000CU}, /* RGIDW_MODID[183]:AXIPCI004*/ + [174] = {0xE65824FCU, 0x0000004EU}, /* RGIDW_MODID[184]:IPMMUHC01*/ + [175] = {0xE6582500U, 0x0000004EU}, /* RGIDW_MODID[185]:AVB0*/ + [176] = {0xE6582504U, 0x0000004EU}, /* RGIDW_MODID[186]:AVB1*/ + [177] = {0xE6582508U, 0x0000004EU}, /* RGIDW_MODID[187]:AVB2*/ + [178] = {0xE658250CU, 0x0000004EU}, /* RGIDW_MODID[188]:IPMMUHC10*/ + [179] = {0xE6582510U, 0x0000004EU}, /* RGIDW_MODID[189]:IPMMUHC11*/ + [180] = {0xE6582514U, 0x0000004EU}, /* RGIDW_MODID[190]:IPMMUHC12*/ + [181] = {0xE6582518U, 0x0000004EU}, /* RGIDW_MODID[191]:IPMMUHC13*/ + [182] = {0xE658251CU, 0x0000000CU}, /* RGIDW_MODID[192]:PPHY0*/ + [183] = {0xE6582524U, 0x0000004EU}, /* RGIDW_MODID[193]:IPMMUHC14*/ + [184] = {0xE6582528U, 0x0000004EU}, /* RGIDW_MODID[194]:IPMMUHC15*/ + [185] = {0xE658252CU, 0x0000000EU}, /* RGIDW_MODID[195]:FBAHSC*/ + [186] = {0xE6582530U, 0x0000004EU}, /* RGIDW_MODID[196]:IPMMUHC02*/ + [187] = {0xE6582538U, 0x0000000AU}, /* RGIDW_MODID[197]:ECMHSC*/ + [188] = {0xE658253CU, 0x00000002U}, /* RGIDW_MODID[198]:ARHC0*/ + /* After setting */ /* RGIDW_MODID[199]:ARHC1*/ + /* After setting */ /* RGIDW_MODID[200]:ARHC2*/ + [189] = {0xE6582548U, 0x00000001U}, /* RGIDW_MODID[201]:ARHC3*/ + [190] = {0xE658254CU, 0x00000002U}, /* RGIDW_MODID[202]:ARHC4*/ + [191] = {0xE6582550U, 0x00000001U}, /* RGIDW_MODID[203]:ARHC5*/ + [192] = {0xE6582554U, 0x00000002U}, /* RGIDW_MODID[204]:ARHC6*/ + [193] = {0xE6582558U, 0x00000002U}, /* RGIDW_MODID[205]:ARHC7*/ + [194] = {0xE658255CU, 0x00000000U}, /* RGIDW_MODID[206]:ARHC8*/ + [195] = {0xE6582560U, 0x0000004EU}, /* RGIDW_MODID[207]:IPMMUHC03*/ + [196] = {0xE6582564U, 0x0000004EU}, /* RGIDW_MODID[208]:IPMMUHC04*/ + [197] = {0xE6582568U, 0x0000004EU}, /* RGIDW_MODID[209]:IPMMUHC05*/ + [198] = {0xE658256CU, 0x0000004EU}, /* RGIDW_MODID[210]:IPMMUHC06*/ + [199] = {0xE6582570U, 0x0000004EU}, /* RGIDW_MODID[211]:IPMMUHC07*/ + [200] = {0xE6582574U, 0x0000004EU}, /* RGIDW_MODID[212]:IPMMUHC08*/ + [201] = {0xE6582578U, 0x0000004EU}, /* RGIDW_MODID[213]:IPMMUHC09*/ + [202] = {0xFF882400U, 0x00000002U}, /* RGIDW_MODID[214]:ARIMP00*/ + /* After setting */ /* RGIDW_MODID[215]:ARIMP01*/ + /* After setting */ /* RGIDW_MODID[216]:ARIMP02*/ + [203] = {0xFF88240CU, 0x00000001U}, /* RGIDW_MODID[217]:ARIMP03*/ + [204] = {0xFF882410U, 0x00000002U}, /* RGIDW_MODID[218]:ARIMP04*/ + [205] = {0xFF882414U, 0x0000004EU}, /* RGIDW_MODID[219]:AXIFBABUSIR0*/ + [206] = {0xFF882418U, 0x0000004EU}, /* RGIDW_MODID[220]:AXIFBABUSIR1*/ + [207] = {0xFF88241CU, 0x0000004EU}, /* RGIDW_MODID[221]:AXIFBABUSIR2*/ + [208] = {0xFF882420U, 0x0000004EU}, /* RGIDW_MODID[222]:AXIFBABUSIR3*/ + [209] = {0xFF882428U, 0x0000004EU}, /* RGIDW_MODID[223]:AXIIMP0*/ + [210] = {0xFF882434U, 0x00000001U}, /* RGIDW_MODID[224]:ARIMP05*/ + [211] = {0xFF882438U, 0x00000002U}, /* RGIDW_MODID[225]:ARIMP06*/ + [212] = {0xFF88243CU, 0x00000002U}, /* RGIDW_MODID[226]:ARIMP07*/ + [213] = {0xFF882440U, 0x00000000U}, /* RGIDW_MODID[227]:ARIMP08*/ + [214] = {0xFF882448U, 0x0000000AU}, /* RGIDW_MODID[228]:ECMIR*/ + [215] = {0xFF88244CU, 0x0000000FU}, /* RGIDW_MODID[229]:DSPPS*/ + [216] = {0xFF882450U, 0x0000004EU}, /* RGIDW_MODID[230]:IPMMUIR1*/ + [217] = {0xFF882454U, 0x0000004EU}, /* RGIDW_MODID[231]:IPMMUIR0*/ + [218] = {0xFF882458U, 0x0000004EU}, /* RGIDW_MODID[232]:IPMMUIR10*/ + [219] = {0xFF88245CU, 0x0000004EU}, /* RGIDW_MODID[233]:IPMMUIR11*/ + [220] = {0xFF882460U, 0x0000004EU}, /* RGIDW_MODID[234]:IPMMUIR12*/ + [221] = {0xFF882464U, 0x0000004EU}, /* RGIDW_MODID[235]:IPMMUIR13*/ + [222] = {0xFF882468U, 0x0000004EU}, /* RGIDW_MODID[236]:IPMMUIR14*/ + [223] = {0xFF88246CU, 0x0000004EU}, /* RGIDW_MODID[237]:IPMMUIR15*/ + [224] = {0xFF882470U, 0x0000004EU}, /* RGIDW_MODID[238]:IPMMUIR2*/ + [225] = {0xFF882474U, 0x0000004EU}, /* RGIDW_MODID[239]:IPMMUIR3*/ + [226] = {0xFF882478U, 0x0000004EU}, /* RGIDW_MODID[240]:IPMMUIR4*/ + [227] = {0xFF88247CU, 0x0000004EU}, /* RGIDW_MODID[241]:IPMMUIR5*/ + [228] = {0xFF882480U, 0x0000004EU}, /* RGIDW_MODID[242]:IPMMUIR6*/ + [229] = {0xFF882484U, 0x0000004EU}, /* RGIDW_MODID[243]:IPMMUIR7*/ + [230] = {0xFF882488U, 0x0000004EU}, /* RGIDW_MODID[244]:IPMMUIR8*/ + [231] = {0xFF88248CU, 0x0000004EU}, /* RGIDW_MODID[245]:IPMMUIR9*/ + [232] = {0xFD812400U, 0x00000002U}, /* RGIDW_MODID[246]:ARPV0*/ + /* After setting */ /* RGIDW_MODID[247]:ARPV1*/ + [233] = {0xFD812408U, 0x0000002CU}, /* RGIDW_MODID[248]:AXIRGXS*/ + /* After setting */ /* RGIDW_MODID[249]:ARPV2*/ + [234] = {0xFD812410U, 0x00000001U}, /* RGIDW_MODID[250]:ARPV3*/ + [235] = {0xFD812414U, 0x00000002U}, /* RGIDW_MODID[251]:ARPV4*/ + [236] = {0xFD812418U, 0x00000001U}, /* RGIDW_MODID[252]:ARPV5*/ + [237] = {0xFD81241CU, 0x00000002U}, /* RGIDW_MODID[253]:ARPV6*/ + [238] = {0xFD812420U, 0x00000002U}, /* RGIDW_MODID[254]:ARPV7*/ + [239] = {0xFD812424U, 0x00000000U}, /* RGIDW_MODID[255]:ARPV8*/ + [240] = {0xFD81242CU, 0x0000000AU}, /* RGIDW_MODID[256]:ECM3DG*/ + [241] = {0xFD812430U, 0x0000000EU}, /* RGIDW_MODID[257]:FBAPVC*/ + [242] = {0xFD812434U, 0x0000000EU}, /* RGIDW_MODID[258]:FBAPVD0*/ + [243] = {0xFD812438U, 0x0000000EU}, /* RGIDW_MODID[259]:FBAPVD1*/ + [244] = {0xFD81243CU, 0x0000000EU}, /* RGIDW_MODID[260]:FBAPVD2*/ + [245] = {0xFD812440U, 0x0000000EU}, /* RGIDW_MODID[261]:FBAPVE*/ + [246] = {0xFD812444U, 0x0000004EU}, /* RGIDW_MODID[262]:IPMMUPV000*/ + [247] = {0xFD812448U, 0x0000004EU}, /* RGIDW_MODID[263]:IPMMUPV001*/ + [248] = {0xFD81244CU, 0x0000004EU}, /* RGIDW_MODID[264]:IPMMUPV010*/ + [249] = {0xFD812450U, 0x0000004EU}, /* RGIDW_MODID[265]:IPMMUPV011*/ + [250] = {0xFD812454U, 0x0000004EU}, /* RGIDW_MODID[266]:IPMMUPV012*/ + [251] = {0xFD812458U, 0x0000004EU}, /* RGIDW_MODID[267]:IPMMUPV013*/ + [252] = {0xFD81245CU, 0x0000004EU}, /* RGIDW_MODID[268]:IPMMUPV014*/ + [253] = {0xFD812460U, 0x0000004EU}, /* RGIDW_MODID[269]:IPMMUPV015*/ + [254] = {0xFD812464U, 0x0000004EU}, /* RGIDW_MODID[270]:IPMMUPV002*/ + [255] = {0xFD812468U, 0x0000004EU}, /* RGIDW_MODID[271]:IPMMUPV003*/ + [256] = {0xFD81246CU, 0x0000004EU}, /* RGIDW_MODID[272]:IPMMUPV004*/ + [257] = {0xFD812470U, 0x0000004EU}, /* RGIDW_MODID[273]:IPMMUPV005*/ + [258] = {0xFD812474U, 0x0000004EU}, /* RGIDW_MODID[274]:IPMMUPV006*/ + [259] = {0xFD812478U, 0x0000004EU}, /* RGIDW_MODID[275]:IPMMUPV007*/ + [260] = {0xFD81247CU, 0x0000004EU}, /* RGIDW_MODID[276]:IPMMUPV008*/ + [261] = {0xFD812480U, 0x0000004EU}, /* RGIDW_MODID[277]:IPMMUPV009*/ + [262] = {0xE6622400U, 0x00000002U}, /* RGIDW_MODID[278]:ARRC0*/ + /* After setting */ /* RGIDW_MODID[279]:ARRC1*/ + /* After setting */ /* RGIDW_MODID[280]:ARRC2*/ + [263] = {0xE662240CU, 0x00000001U}, /* RGIDW_MODID[281]:ARRC3*/ + [264] = {0xE6622410U, 0x00000002U}, /* RGIDW_MODID[282]:ARRC4*/ + [265] = {0xE6622414U, 0x00000001U}, /* RGIDW_MODID[283]:ARRC5*/ + [266] = {0xE6622418U, 0x00000002U}, /* RGIDW_MODID[284]:ARRC6*/ + [267] = {0xE662241CU, 0x00000002U}, /* RGIDW_MODID[285]:ARRC7*/ + [268] = {0xE6622420U, 0x00000000U}, /* RGIDW_MODID[286]:ARRC8*/ + [269] = {0xE6622428U, 0x0000004FU}, /* RGIDW_MODID[287]:ICUMX*/ + [270] = {0xE662242CU, 0x0000000AU}, /* RGIDW_MODID[288]:ECMRC*/ + [271] = {0xFFC32400U, 0x0000004EU}, /* RGIDW_MODID[289]:DMAWCRC0*/ + [272] = {0xFFC32404U, 0x0000004EU}, /* RGIDW_MODID[290]:DMAWCRC1*/ + [273] = {0xFFC32408U, 0x0000004EU}, /* RGIDW_MODID[291]:DMAWCRC2*/ + [274] = {0xFFC3240CU, 0x0000004EU}, /* RGIDW_MODID[292]:DMAWCRC3*/ + [275] = {0xFFC42400U, 0x0000000FU}, /* RGIDW_MODID[293]:ARMREG00*/ + [276] = {0xFFC42404U, 0x0000000CU}, /* RGIDW_MODID[294]:ARMREG01*/ + [277] = {0xFFC42408U, 0x00000000U}, /* RGIDW_MODID[295]:ARMREG10*/ + [278] = {0xFFC4240CU, 0x00000000U}, /* RGIDW_MODID[296]:ARMREG11*/ + [279] = {0xFFC42410U, 0x0000000AU}, /* RGIDW_MODID[297]:ARMREG12*/ + [280] = {0xFFC42414U, 0x0000000FU}, /* RGIDW_MODID[298]:ARMREG13*/ + [281] = {0xFFC42418U, 0x0000000AU}, /* RGIDW_MODID[299]:ARMREG14*/ + [282] = {0xFFC4241CU, 0x00000003U}, /* RGIDW_MODID[300]:AXICR52SS0*/ + [283] = {0xFFC42420U, 0x0000000EU}, /* RGIDW_MODID[301]:AXICSD0*/ + [284] = {0xFFC42424U, 0x0000000EU}, /* RGIDW_MODID[302]:AXIINTAP0*/ + [285] = {0xFFC42430U, 0x0000000FU}, /* RGIDW_MODID[303]:AXISYSRAM0*/ + [286] = {0xFFC42434U, 0x0000004FU}, /* RGIDW_MODID[304]:AXISYSRAM1*/ + [287] = {0xFFC42438U, 0x00000000U}, /* RGIDW_MODID[305]:ARGREG15*/ + [288] = {0xFFC4243CU, 0x00000000U}, /* RGIDW_MODID[306]:ARMREG2*/ + [289] = {0xFFC42440U, 0x00000000U}, /* RGIDW_MODID[307]:ARMREG3*/ + [290] = {0xFFC42444U, 0x00000000U}, /* RGIDW_MODID[308]:ARMREG4*/ + [291] = {0xFFC42448U, 0x0000000FU}, /* RGIDW_MODID[309]:ARMREG5*/ + [292] = {0xFFC4244CU, 0x0000000AU}, /* RGIDW_MODID[310]:ARMREG6*/ + [293] = {0xFFC42450U, 0x00000000U}, /* RGIDW_MODID[311]:ARMREG7*/ + [294] = {0xFFC42454U, 0x0000000CU}, /* RGIDW_MODID[312]:ARMREG8*/ + [295] = {0xFFC42458U, 0x0000000CU}, /* RGIDW_MODID[313]:ARMREG9*/ + [296] = {0xFFC4245CU, 0x00000002U}, /* RGIDW_MODID[314]:ARRD0*/ + /* After setting */ /* RGIDW_MODID[315]:ARRD1*/ + /* After setting */ /* RGIDW_MODID[316]:ARRD2*/ + [297] = {0xFFC42468U, 0x00000001U}, /* RGIDW_MODID[317]:ARRD3*/ + [298] = {0xFFC4246CU, 0x00000002U}, /* RGIDW_MODID[318]:ARRD4*/ + [299] = {0xFFC42470U, 0x00000001U}, /* RGIDW_MODID[319]:ARRD5*/ + [300] = {0xFFC42474U, 0x00000002U}, /* RGIDW_MODID[320]:ARRD6*/ + [301] = {0xFFC42478U, 0x00000002U}, /* RGIDW_MODID[321]:ARRD7*/ + [302] = {0xFFC4247CU, 0x00000000U}, /* RGIDW_MODID[322]:ARRD8*/ + [303] = {0xFFC42480U, 0x00000002U}, /* RGIDW_MODID[323]:ARRT0*/ + /* After setting */ /* RGIDW_MODID[324]:ARRT1*/ + /* After setting */ /* RGIDW_MODID[325]:ARRT2*/ + [304] = {0xFFC4248CU, 0x00000001U}, /* RGIDW_MODID[326]:ARRT3*/ + [305] = {0xFFC42490U, 0x00000002U}, /* RGIDW_MODID[327]:ARRT4*/ + [306] = {0xFFC42494U, 0x00000001U}, /* RGIDW_MODID[328]:ARRT5*/ + [307] = {0xFFC42498U, 0x00000002U}, /* RGIDW_MODID[329]:ARRT6*/ + [308] = {0xFFC4249CU, 0x00000002U}, /* RGIDW_MODID[330]:ARRT7*/ + [309] = {0xFFC424A0U, 0x00000000U}, /* RGIDW_MODID[331]:ARRT8*/ + [310] = {0xFFC424A4U, 0x0000000AU}, /* RGIDW_MODID[332]:CKMRT*/ + [311] = {0xFFC424A8U, 0x0000004EU}, /* RGIDW_MODID[333]:CRC0*/ + [312] = {0xFFC424ACU, 0x0000004EU}, /* RGIDW_MODID[334]:CRC1*/ + [313] = {0xFFC424B0U, 0x0000004EU}, /* RGIDW_MODID[335]:CRC2*/ + [314] = {0xFFC424B4U, 0x0000004EU}, /* RGIDW_MODID[336]:CRC3*/ + [315] = {0xFFC424B8U, 0x0000000EU}, /* RGIDW_MODID[337]:CSD*/ + [316] = {0xFFC424BCU, 0x0000000EU}, /* RGIDW_MODID[338]:ECM*/ + [317] = {0xFFC424C0U, 0x0000000AU}, /* RGIDW_MODID[339]:ECMRT*/ + [318] = {0xFFC424C4U, 0x0000000EU}, /* RGIDW_MODID[340]:FBACR52*/ + [319] = {0xFFC424C8U, 0x0000000EU}, /* RGIDW_MODID[341]:FBART*/ + [320] = {0xFFC424CCU, 0x0000000EU}, /* RGIDW_MODID[342]:INTTP*/ + [321] = {0xFFC424D0U, 0x0000004EU}, /* RGIDW_MODID[343]:IPMMURT000*/ + [322] = {0xFFC424D4U, 0x0000004EU}, /* RGIDW_MODID[344]:IPMMURT100*/ + [323] = {0xFFC424D8U, 0x0000004EU}, /* RGIDW_MODID[345]:KCRC4*/ + [324] = {0xFFC424DCU, 0x0000004EU}, /* RGIDW_MODID[346]:KCRC5*/ + [325] = {0xFFC424E0U, 0x0000004EU}, /* RGIDW_MODID[347]:KCRC6*/ + [326] = {0xFFC424E4U, 0x0000004EU}, /* RGIDW_MODID[348]:KCRC7*/ + [327] = {0xFFC424E8U, 0x0000004FU}, /* RGIDW_MODID[349]:MFI00*/ + [328] = {0xFFC424ECU, 0x0000004EU}, /* RGIDW_MODID[350]:MFI01*/ + [329] = {0xFFC424F0U, 0x0000004EU}, /* RGIDW_MODID[351]:MFI10*/ + [330] = {0xFFC424F4U, 0x0000004EU}, /* RGIDW_MODID[352]:MFI02*/ + [331] = {0xFFC424F8U, 0x0000004EU}, /* RGIDW_MODID[353]:MFI03*/ + [332] = {0xFFC424FCU, 0x0000004EU}, /* RGIDW_MODID[354]:MFI04*/ + [333] = {0xFFC42500U, 0x00000000U}, /* RGIDW_MODID[355]:MFI05*/ + [334] = {0xFFC42504U, 0x00000000U}, /* RGIDW_MODID[356]:MFI06*/ + [335] = {0xFFC42508U, 0x00000000U}, /* RGIDW_MODID[357]:MFI07*/ + [336] = {0xFFC4250CU, 0x00000000U}, /* RGIDW_MODID[358]:MFI08*/ + [337] = {0xFFC42510U, 0x0000004EU}, /* RGIDW_MODID[359]:MFI09*/ + [338] = {0xFFC42514U, 0x0000004FU}, /* RGIDW_MODID[360]:MFI15*/ + [339] = {0xFFC42518U, 0x0000000AU}, /* RGIDW_MODID[361]:CKMCR52*/ + [340] = {0xFFC4251CU, 0x0000004BU}, /* RGIDW_MODID[362]:RTDM0P*/ + [341] = {0xFFC42520U, 0x0000000AU}, /* RGIDW_MODID[363]:ECMRD*/ + [342] = {0xFFC42524U, 0x0000004BU}, /* RGIDW_MODID[364]:RTDM1P*/ + [343] = {0xFFC42530U, 0x0000000BU}, /* RGIDW_MODID[365]:SYSRAM10*/ + [344] = {0xFFC42538U, 0x00000001U}, /* RGIDW_MODID[366]:SYSRAM00*/ + [345] = {0xFFC4253CU, 0x0000004EU}, /* RGIDW_MODID[367]:TSIPL0*/ + [346] = {0xFFC42540U, 0x0000004EU}, /* RGIDW_MODID[368]:TSIPL1*/ + [347] = {0xFFC42544U, 0x0000004EU}, /* RGIDW_MODID[369]:TSIPL2*/ + [348] = {0xFFC42548U, 0x0000004EU}, /* RGIDW_MODID[370]:TSIPL3*/ + [349] = {0xFFC4254CU, 0x0000004EU}, /* RGIDW_MODID[371]:TSIPL4*/ + [350] = {0xFFC42550U, 0x0000004EU}, /* RGIDW_MODID[372]:TSIPL5*/ + [351] = {0xFFC42554U, 0x0000004EU}, /* RGIDW_MODID[373]:TSIPL6*/ + [352] = {0xFFC42558U, 0x0000004EU}, /* RGIDW_MODID[374]:TSIPL7*/ + [353] = {0xFFC4255CU, 0x0000004EU}, /* RGIDW_MODID[375]:WCRC0*/ + [354] = {0xFFC42560U, 0x0000004EU}, /* RGIDW_MODID[376]:WCRC1*/ + [355] = {0xFFC42564U, 0x0000004EU}, /* RGIDW_MODID[377]:WCRC2*/ + [356] = {0xFFC42568U, 0x0000004EU}, /* RGIDW_MODID[378]:WCRC3*/ + [357] = {0xFFC42580U, 0x0000004EU}, /* RGIDW_MODID[379]:MFI11*/ + [358] = {0xFFC42584U, 0x00000000U}, /* RGIDW_MODID[380]:MFI12*/ + [359] = {0xFFC42588U, 0x00000000U}, /* RGIDW_MODID[381]:MFI13*/ + [360] = {0xFFC4258CU, 0x00000000U}, /* RGIDW_MODID[382]:MFI14*/ + [361] = {0xFFC42590U, 0x0000004EU}, /* RGIDW_MODID[383]:IPMMURT001*/ + [362] = {0xFFC42594U, 0x0000004EU}, /* RGIDW_MODID[384]:IPMMURT010*/ + [363] = {0xFFC42598U, 0x0000004EU}, /* RGIDW_MODID[385]:IPMMURT011*/ + [364] = {0xFFC4259CU, 0x0000004EU}, /* RGIDW_MODID[386]:IPMMURT012*/ + [365] = {0xFFC425A0U, 0x0000004EU}, /* RGIDW_MODID[387]:IPMMURT013*/ + [366] = {0xFFC425A4U, 0x0000004EU}, /* RGIDW_MODID[388]:IPMMURT014*/ + [367] = {0xFFC425A8U, 0x0000004EU}, /* RGIDW_MODID[389]:IPMMURT015*/ + [368] = {0xFFC425ACU, 0x0000004EU}, /* RGIDW_MODID[390]:IPMMURT002*/ + [369] = {0xFFC425B0U, 0x0000004EU}, /* RGIDW_MODID[391]:IPMMURT003*/ + [370] = {0xFFC425B4U, 0x0000004EU}, /* RGIDW_MODID[392]:IPMMURT004*/ + [371] = {0xFFC425B8U, 0x0000004EU}, /* RGIDW_MODID[393]:IPMMURT005*/ + [372] = {0xFFC425BCU, 0x0000004EU}, /* RGIDW_MODID[394]:IPMMURT006*/ + [373] = {0xFFC425C0U, 0x0000004EU}, /* RGIDW_MODID[395]:IPMMURT007*/ + [374] = {0xFFC425C4U, 0x0000004EU}, /* RGIDW_MODID[396]:IPMMURT008*/ + [375] = {0xFFC425C8U, 0x0000004EU}, /* RGIDW_MODID[397]:IPMMURT009*/ + [376] = {0xFFC425CCU, 0x0000004EU}, /* RGIDW_MODID[398]:IPKMURT101*/ + [377] = {0xFFC425D0U, 0x0000004EU}, /* RGIDW_MODID[399]:IPMMURT110*/ + [378] = {0xFFC425D4U, 0x0000004EU}, /* RGIDW_MODID[400]:IPMMURT111*/ + [379] = {0xFFC425D8U, 0x0000004EU}, /* RGIDW_MODID[401]:IPMMURT112*/ + [380] = {0xFFC425DCU, 0x0000004EU}, /* RGIDW_MODID[402]:IPMMURT113*/ + [381] = {0xFFC425E0U, 0x0000004EU}, /* RGIDW_MODID[403]:IPMMURT114*/ + [382] = {0xFFC425E4U, 0x0000004EU}, /* RGIDW_MODID[404]:IPMMURT115*/ + [383] = {0xFFC425E8U, 0x0000004EU}, /* RGIDW_MODID[405]:IPMMURT102*/ + [384] = {0xFFC425ECU, 0x0000004EU}, /* RGIDW_MODID[406]:IPMMURT103*/ + [385] = {0xFFC425F0U, 0x0000004EU}, /* RGIDW_MODID[407]:IPMMURT104*/ + [386] = {0xFFC425F4U, 0x0000004EU}, /* RGIDW_MODID[408]:IPMMURT105*/ + [387] = {0xFFC425F8U, 0x0000004EU}, /* RGIDW_MODID[409]:IPMMURT106*/ + [388] = {0xFFC425FCU, 0x0000004EU}, /* RGIDW_MODID[410]:IPMMURT107*/ + [389] = {0xFFC42600U, 0x0000004BU}, /* RGIDW_MODID[411]:RTDM000*/ + [390] = {0xFFC42604U, 0x0000004BU}, /* RGIDW_MODID[412]:RTDM001*/ + [391] = {0xFFC42608U, 0x0000004BU}, /* RGIDW_MODID[413]:RTDM010*/ + [392] = {0xFFC4260CU, 0x0000004BU}, /* RGIDW_MODID[414]:RTDM011*/ + [393] = {0xFFC42610U, 0x0000004BU}, /* RGIDW_MODID[415]:RTDM012*/ + [394] = {0xFFC42614U, 0x0000004BU}, /* RGIDW_MODID[416]:RTDM013*/ + [395] = {0xFFC42618U, 0x0000004BU}, /* RGIDW_MODID[417]:RTDM014*/ + [396] = {0xFFC4261CU, 0x0000004BU}, /* RGIDW_MODID[418]:RTDM015*/ + [397] = {0xFFC42620U, 0x0000004BU}, /* RGIDW_MODID[419]:RTDM002*/ + [398] = {0xFFC42624U, 0x0000004BU}, /* RGIDW_MODID[420]:RTDM003*/ + [399] = {0xFFC42628U, 0x0000004BU}, /* RGIDW_MODID[421]:RTDM004*/ + [400] = {0xFFC4262CU, 0x0000004BU}, /* RGIDW_MODID[422]:RTDM005*/ + [401] = {0xFFC42630U, 0x0000004BU}, /* RGIDW_MODID[423]:RTDM006*/ + [402] = {0xFFC42634U, 0x0000004BU}, /* RGIDW_MODID[424]:RTDM007*/ + [403] = {0xFFC42638U, 0x0000004BU}, /* RGIDW_MODID[425]:RTDM008*/ + [404] = {0xFFC4263CU, 0x0000004BU}, /* RGIDW_MODID[426]:RTDM009*/ + [405] = {0xFFC42640U, 0x0000004BU}, /* RGIDW_MODID[427]:RTDM100*/ + [406] = {0xFFC42644U, 0x0000004BU}, /* RGIDW_MODID[428]:RTDM101*/ + [407] = {0xFFC42648U, 0x0000004BU}, /* RGIDW_MODID[429]:RTDM110*/ + [408] = {0xFFC4264CU, 0x0000004BU}, /* RGIDW_MODID[430]:RTDM111*/ + [409] = {0xFFC42650U, 0x0000004BU}, /* RGIDW_MODID[431]:RTDM112*/ + [410] = {0xFFC42654U, 0x0000004BU}, /* RGIDW_MODID[432]:RTDM113*/ + [411] = {0xFFC42658U, 0x0000004BU}, /* RGIDW_MODID[433]:RTDM114*/ + [412] = {0xFFC4265CU, 0x0000004BU}, /* RGIDW_MODID[434]:RTDM115*/ + [413] = {0xFFC42660U, 0x0000004BU}, /* RGIDW_MODID[435]:RTDM102*/ + [414] = {0xFFC42664U, 0x0000004BU}, /* RGIDW_MODID[436]:RTDM103*/ + [415] = {0xFFC42668U, 0x0000004BU}, /* RGIDW_MODID[437]:RTDM104*/ + [416] = {0xFFC4266CU, 0x0000004BU}, /* RGIDW_MODID[438]:RTDM105*/ + [417] = {0xFFC42670U, 0x0000004BU}, /* RGIDW_MODID[439]:RTDM106*/ + [418] = {0xFFC42674U, 0x0000004BU}, /* RGIDW_MODID[440]:RTDM107*/ + [419] = {0xFFC42678U, 0x0000004BU}, /* RGIDW_MODID[441]:RTDM108*/ + [420] = {0xFFC4267CU, 0x0000004BU}, /* RGIDW_MODID[442]:RTDM109*/ + [421] = {0xFFC42700U, 0x0000004EU}, /* RGIDW_MODID[443]:IPMMURT108*/ + [422] = {0xFFC42704U, 0x0000004EU}, /* RGIDW_MODID[444]:IPMMURT109*/ + [423] = {0xFFC42708U, 0x00000001U}, /* RGIDW_MODID[445]:SYSRAM01*/ + [424] = {0xFFC4270CU, 0x0000000BU}, /* RGIDW_MODID[446]:SYSRAM02*/ + [425] = {0xFFC42710U, 0x00000001U}, /* RGIDW_MODID[447]:SYSRAM03*/ + [426] = {0xFFC42714U, 0x00000001U}, /* RGIDW_MODID[448]:SYSRAM04*/ + [427] = {0xFFC42718U, 0x00000001U}, /* RGIDW_MODID[449]:SYSRAM05*/ + [428] = {0xFFC4271CU, 0x00000001U}, /* RGIDW_MODID[450]:SYSRAM06*/ + [429] = {0xFFC42720U, 0x00000000U}, /* RGIDW_MODID[451]:SYSRAM07*/ + [430] = {0xFFC42724U, 0x0000000BU}, /* RGIDW_MODID[452]:SYSRAM11*/ + [431] = {0xFFC42728U, 0x0000000AU}, /* RGIDW_MODID[453]:SYSRAM12*/ + [432] = {0xFFC4272CU, 0x0000000BU}, /* RGIDW_MODID[454]:SYSRAM13*/ + [433] = {0xFFC42730U, 0x0000000BU}, /* RGIDW_MODID[455]:SYSRAM14*/ + [434] = {0xFFC42734U, 0x0000000BU}, /* RGIDW_MODID[456]:SYSRAM15*/ + [435] = {0xFFC42738U, 0x0000000BU}, /* RGIDW_MODID[457]:SYSRAM16*/ + [436] = {0xFFC4273CU, 0x00000000U}, /* RGIDW_MODID[458]:SYSRAM17*/ + [437] = {0xFFC42760U, 0x00000002U}, /* RGIDW_MODID[459]:BKBUF*/ + [438] = {0xFFC42764U, 0x00000003U}, /* RGIDW_MODID[460]:AXICR52SS1*/ + [439] = {0xFFC42768U, 0x00000003U}, /* RGIDW_MODID[461]:AXICR52SS2*/ + [440] = {0xFF862400U, 0x00000002U}, /* RGIDW_MODID[462]:ARSC0*/ + /* After setting */ /* RGIDW_MODID[463]:ARSC1*/ + /* After setting */ /* RGIDW_MODID[464]:ARSC2*/ + [441] = {0xFF86240CU, 0x00000001U}, /* RGIDW_MODID[465]:ARSC3*/ + [442] = {0xFF862410U, 0x00000002U}, /* RGIDW_MODID[466]:ARSC4*/ + [443] = {0xFF862414U, 0x00000001U}, /* RGIDW_MODID[467]:ARSC5*/ + [444] = {0xFF862418U, 0x00000002U}, /* RGIDW_MODID[468]:ARSC6*/ + [445] = {0xFF86241CU, 0x00000002U}, /* RGIDW_MODID[469]:ARSC7*/ + [446] = {0xFF862420U, 0x00000000U}, /* RGIDW_MODID[470]:ARSC8*/ + [447] = {0xFF862424U, 0x00000002U}, /* RGIDW_MODID[471]:ARSTM0*/ + /* After setting */ /* RGIDW_MODID[472]:ARSTM1*/ + [448] = {0xFF86242CU, 0x0000000EU}, /* RGIDW_MODID[473]:CSD1S*/ + [449] = {0xFF862430U, 0x0000000EU}, /* RGIDW_MODID[474]:AXIFBABUSTOP0*/ + /* After setting */ /* RGIDW_MODID[475]:ARSTM2*/ + [450] = {0xFF86243CU, 0x00000001U}, /* RGIDW_MODID[476]:ARSTM3*/ + [451] = {0xFF862440U, 0x00000002U}, /* RGIDW_MODID[477]:ARSTM4*/ + [452] = {0xFF862444U, 0x00000001U}, /* RGIDW_MODID[478]:ARSTM5*/ + [453] = {0xFF862448U, 0x00000002U}, /* RGIDW_MODID[479]:ARSTM6*/ + [454] = {0xFF86244CU, 0x00000002U}, /* RGIDW_MODID[480]:ARSTM7*/ + [455] = {0xFF862450U, 0x00000000U}, /* RGIDW_MODID[481]:ARSTM8*/ + [456] = {0xFF862454U, 0x0000000AU}, /* RGIDW_MODID[482]:ECMTOP*/ + [457] = {0xFF862458U, 0x0000000EU}, /* RGIDW_MODID[483]:FBA*/ + [458] = {0xFF86245CU, 0x0000000EU}, /* RGIDW_MODID[484]:FBC*/ + [459] = {0xFF862434U, 0x0000000CU}, /* RGIDW_MODID[485]:AXICCI00*/ + [460] = {0xFF862460U, 0x0000000EU}, /* RGIDW_MODID[486]:AXICCI01*/ + [461] = {0xFF862464U, 0x0000000CU}, /* RGIDW_MODID[487]:AXICCI10*/ + [462] = {0xFF862468U, 0x0000000CU}, /* RGIDW_MODID[488]:AXICCI11*/ + [463] = {0xFF86246CU, 0x0000000CU}, /* RGIDW_MODID[489]:AXICCI12*/ + [464] = {0xFF862470U, 0x0000000CU}, /* RGIDW_MODID[490]:AXICCI13*/ + [465] = {0xFF862474U, 0x0000000CU}, /* RGIDW_MODID[491]:AXICCI14*/ + [466] = {0xFF862478U, 0x0000000CU}, /* RGIDW_MODID[492]:AXICCI15*/ + [467] = {0xFF86247CU, 0x0000000EU}, /* RGIDW_MODID[493]:AXICCI2*/ + [468] = {0xFF862480U, 0x0000000CU}, /* RGIDW_MODID[494]:AXICCI3*/ + [469] = {0xFF862484U, 0x0000000CU}, /* RGIDW_MODID[495]:AXICCI4*/ + [470] = {0xFF862488U, 0x0000000CU}, /* RGIDW_MODID[496]:AXICCI5*/ + [471] = {0xFF86248CU, 0x0000000CU}, /* RGIDW_MODID[497]:AXICCI6*/ + [472] = {0xFF862490U, 0x0000000CU}, /* RGIDW_MODID[498]:AXICCI7*/ + [473] = {0xFF862494U, 0x0000000CU}, /* RGIDW_MODID[499]:AXICCI8*/ + [474] = {0xFF862498U, 0x00000009U}, /* RGIDW_MODID[500]:AXICCI9*/ + [475] = {0xFF8624A0U, 0x0000000AU}, /* RGIDW_MODID[501]:ECMSTM*/ + [476] = {0xE7782400U, 0x0000002CU}, /* RGIDW_MODID[502]:DMASSI00*/ + [477] = {0xE7782404U, 0x0000002CU}, /* RGIDW_MODID[503]:DMASSI01*/ + [478] = {0xE7782408U, 0x0000002CU}, /* RGIDW_MODID[504]:DMASSI02*/ + [479] = {0xE778240CU, 0x0000002CU}, /* RGIDW_MODID[505]:DMASSI03*/ + [480] = {0xE7782410U, 0x0000002CU}, /* RGIDW_MODID[506]:DMASSI04*/ + [481] = {0xE7782414U, 0x0000004EU}, /* RGIDW_MODID[507]:DMAI2C0*/ + [482] = {0xE7782418U, 0x0000004EU}, /* RGIDW_MODID[508]:DMAI2C1*/ + [483] = {0xE778241CU, 0x0000004EU}, /* RGIDW_MODID[509]:DMAI2C2*/ + [484] = {0xE7782420U, 0x0000004EU}, /* RGIDW_MODID[510]:DMAI2C3*/ + [485] = {0xE778242CU, 0x0000002CU}, /* RGIDW_MODID[511]:DMASSI05*/ + [486] = {0xE7782430U, 0x0000002CU}, /* RGIDW_MODID[512]:DMASSI06*/ + [487] = {0xE7782434U, 0x0000002CU}, /* RGIDW_MODID[513]:DMASSI07*/ + [488] = {0xE67C2400U, 0x00000002U}, /* RGIDW_MODID[514]:ARMM*/ + /* After setting */ /* RGIDW_MODID[515]:AXIARNMM*/ + [489] = {0xE67C2408U, 0x00000002U}, /* RGIDW_MODID[516]:ARSM0*/ + /* After setting */ /* RGIDW_MODID[517]:ARSM1*/ + /* After setting */ /* RGIDW_MODID[518]:ARSM2*/ + [490] = {0xE67C2414U, 0x0000000FU}, /* RGIDW_MODID[519]:AXIQOS0*/ + [491] = {0xE67C2418U, 0x0000000FU}, /* RGIDW_MODID[520]:AXIQOS1*/ + [492] = {0xE67C241CU, 0x0000000FU}, /* RGIDW_MODID[521]:AXIQOS2*/ + [493] = {0xE67C2420U, 0x0000000FU}, /* RGIDW_MODID[522]:AXIQOS3*/ + [494] = {0xE67C2424U, 0x0000000FU}, /* RGIDW_MODID[523]:AXIQOS4*/ + [495] = {0xE67C2428U, 0x0000000FU}, /* RGIDW_MODID[524]:AXIQOS5*/ + [496] = {0xE67C2434U, 0x00000001U}, /* RGIDW_MODID[525]:ARSM3*/ + [497] = {0xE67C2438U, 0x00000002U}, /* RGIDW_MODID[526]:ARSM4*/ + [498] = {0xE67C243CU, 0x00000001U}, /* RGIDW_MODID[527]:ARSM5*/ + [499] = {0xE67C2440U, 0x00000002U}, /* RGIDW_MODID[528]:ARSM6*/ + [500] = {0xE67C2444U, 0x00000002U}, /* RGIDW_MODID[529]:ARSM7*/ + [501] = {0xE67C2448U, 0x00000000U}, /* RGIDW_MODID[530]:ARSM8*/ + [502] = {0xE67C244CU, 0x0000000BU}, /* RGIDW_MODID[531]:AXMM0*/ + [503] = {0xE67C2450U, 0x0000000BU}, /* RGIDW_MODID[532]:AXMM1*/ + [504] = {0xE67C2454U, 0x00000000U}, /* RGIDW_MODID[533]:AXMMPMON*/ + [505] = {0xE67C2458U, 0x0000000AU}, /* RGIDW_MODID[534]:CKMMM*/ + [506] = {0xE67C245CU, 0x0000000AU}, /* RGIDW_MODID[535]:ECMMM*/ + [507] = {0xE67C2460U, 0x0000000EU}, /* RGIDW_MODID[536]:FBADBSC0*/ + [508] = {0xE67C2468U, 0x0000000EU}, /* RGIDW_MODID[537]:FBAMM*/ + [509] = {0xE67C246CU, 0x0000004EU}, /* RGIDW_MODID[538]:IPMMUMM00*/ + [510] = {0xE67C2470U, 0x0000000FU}, /* RGIDW_MODID[539]:DBS0A0*/ + [511] = {0xE67C2474U, 0x0000000AU}, /* RGIDW_MODID[540]:DBS0A1*/ + [512] = {0xE67C2484U, 0x00000009U}, /* RGIDW_MODID[541]:FCPRC*/ + [513] = {0xE67C2488U, 0x0000000FU}, /* RGIDW_MODID[542]:DBS0D0*/ + [514] = {0xE67C248CU, 0x0000000AU}, /* RGIDW_MODID[543]:DBS0D1*/ + [515] = {0xE67C2498U, 0x0000000EU}, /* RGIDW_MODID[544]:FBADDR*/ + [516] = {0xE67C249CU, 0x0000004EU}, /* RGIDW_MODID[545]:IPMMUMM01*/ + [517] = {0xE67C24A0U, 0x0000004EU}, /* RGIDW_MODID[546]:IPMMUMM10*/ + [518] = {0xE67C24A4U, 0x0000004EU}, /* RGIDW_MODID[547]:IPMMUMM11*/ + [519] = {0xE67C24A8U, 0x0000004EU}, /* RGIDW_MODID[548]:IPMMUMM12*/ + [520] = {0xE67C24ACU, 0x0000004EU}, /* RGIDW_MODID[549]:IPMMUMM13*/ + [521] = {0xE67C24B0U, 0x0000004EU}, /* RGIDW_MODID[550]:IPMMUMM14*/ + [522] = {0xE67C24B4U, 0x0000004EU}, /* RGIDW_MODID[551]:IPMMUMM15*/ + [523] = {0xE67C24B8U, 0x0000004EU}, /* RGIDW_MODID[552]:IPMMUMM02*/ + [524] = {0xE67C24BCU, 0x0000004EU}, /* RGIDW_MODID[553]:IPMMUMM03*/ + [525] = {0xE67C24C0U, 0x0000004EU}, /* RGIDW_MODID[554]:IPMMUMM04*/ + [526] = {0xE67C24C4U, 0x0000004EU}, /* RGIDW_MODID[555]:IPMMUMM05*/ + [527] = {0xE67C24C8U, 0x0000004EU}, /* RGIDW_MODID[556]:IPMMUMM06*/ + [528] = {0xE67C24CCU, 0x0000004EU}, /* RGIDW_MODID[557]:IPMMUMM07*/ + [529] = {0xE67C24D0U, 0x0000004EU}, /* RGIDW_MODID[558]:IPMMUMM08*/ + [530] = {0xE67C24D4U, 0x0000004EU}, /* RGIDW_MODID[559]:IPMMUMM09*/ + [531] = {0xFF802400U, 0x00000002U}, /* RGIDW_MODID[560]:ARSN0*/ + /* After setting */ /* RGIDW_MODID[561]:ARSN1*/ + /* After setting */ /* RGIDW_MODID[562]:ARSN2*/ + [532] = {0xFF80240CU, 0x00000001U}, /* RGIDW_MODID[563]:ARSN3*/ + [533] = {0xFF802410U, 0x00000002U}, /* RGIDW_MODID[564]:ARSN4*/ + [534] = {0xFF802414U, 0x00000001U}, /* RGIDW_MODID[565]:ARSN5*/ + [535] = {0xFF802418U, 0x00000002U}, /* RGIDW_MODID[566]:ARSN6*/ + [536] = {0xFF80241CU, 0x00000002U}, /* RGIDW_MODID[567]:ARSN7*/ + [537] = {0xFF802420U, 0x00000000U}, /* RGIDW_MODID[568]:ARSN8*/ + [538] = {0xFF802424U, 0x0000000AU}, /* RGIDW_MODID[569]:ECMTOP3*/ + [539] = {0xE7752400U, 0x00000002U}, /* RGIDW_MODID[570]:ARSD00*/ + /* After setting */ /* RGIDW_MODID[571]:ARSD01*/ + /* After setting */ /* RGIDW_MODID[572]:ARSD02*/ + [540] = {0xE775240CU, 0x00000001U}, /* RGIDW_MODID[573]:ARSD03*/ + [541] = {0xE7752410U, 0x00000002U}, /* RGIDW_MODID[574]:ARSD04*/ + [542] = {0xE7752414U, 0x00000001U}, /* RGIDW_MODID[575]:ARSD05*/ + [543] = {0xE7752418U, 0x00000002U}, /* RGIDW_MODID[576]:ARSD06*/ + [544] = {0xE775241CU, 0x0000004AU}, /* RGIDW_MODID[577]:AXIFRAY*/ + [545] = {0xE7752428U, 0x0000004FU}, /* RGIDW_MODID[578]:AXIRPC*/ + [546] = {0xE775242CU, 0x0000000FU}, /* RGIDW_MODID[579]:AXISDHI0*/ + [547] = {0xE7752430U, 0x00000002U}, /* RGIDW_MODID[580]:ARSD07*/ + [548] = {0xE7752434U, 0x00000000U}, /* RGIDW_MODID[581]:ARSD08*/ + [549] = {0xE7752438U, 0x00000002U}, /* RGIDW_MODID[582]:ARSP00*/ + /* After setting */ /* RGIDW_MODID[583]:ARSP01*/ + /* After setting */ /* RGIDW_MODID[584]:ARSP02*/ + [550] = {0xE7752444U, 0x00000001U}, /* RGIDW_MODID[585]:ARSP03*/ + [551] = {0xE7752448U, 0x00000002U}, /* RGIDW_MODID[586]:ARSP04*/ + [552] = {0xE775244CU, 0x00000001U}, /* RGIDW_MODID[587]:ARSP05*/ + [553] = {0xE7752450U, 0x00000002U}, /* RGIDW_MODID[588]:ARSP06*/ + [554] = {0xE7752454U, 0x00000002U}, /* RGIDW_MODID[589]:ARSP07*/ + [555] = {0xE7752458U, 0x00000000U}, /* RGIDW_MODID[590]:ARSP08*/ + [556] = {0xE775245CU, 0x0000004EU}, /* RGIDW_MODID[591]:IPMMUDS001*/ + [557] = {0xE7752460U, 0x0000000AU}, /* RGIDW_MODID[592]:CKMPER0*/ + [558] = {0xE7752464U, 0x0000000AU}, /* RGIDW_MODID[593]:ECMPER0*/ + [559] = {0xE7752468U, 0x0000000EU}, /* RGIDW_MODID[594]:FBAPER0*/ + [560] = {0xE775246CU, 0x0000004EU}, /* RGIDW_MODID[595]:FSO0*/ + [561] = {0xE7752470U, 0x0000004EU}, /* RGIDW_MODID[596]:FSO1*/ + [562] = {0xE7752474U, 0x0000004EU}, /* RGIDW_MODID[597]:FSO10*/ + [563] = {0xE7752478U, 0x0000004EU}, /* RGIDW_MODID[598]:FSO2*/ + [564] = {0xE775247CU, 0x0000004EU}, /* RGIDW_MODID[599]:FSO3*/ + [565] = {0xE7752480U, 0x0000004EU}, /* RGIDW_MODID[600]:FSO4*/ + [566] = {0xE7752484U, 0x0000004EU}, /* RGIDW_MODID[601]:FSO5*/ + [567] = {0xE7752488U, 0x0000004EU}, /* RGIDW_MODID[602]:FSO6*/ + [568] = {0xE775248CU, 0x0000004EU}, /* RGIDW_MODID[603]:FSO7*/ + [569] = {0xE7752490U, 0x0000004EU}, /* RGIDW_MODID[604]:FSO8*/ + [570] = {0xE7752494U, 0x0000004EU}, /* RGIDW_MODID[605]:FSO9*/ + [571] = {0xE7752498U, 0x0000002CU}, /* RGIDW_MODID[606]:ADG*/ + [572] = {0xE775249CU, 0x0000000AU}, /* RGIDW_MODID[607]:ECMSD0*/ + [573] = {0xE77524A0U, 0x0000004EU}, /* RGIDW_MODID[608]:IPMMUDS010*/ + [574] = {0xE77524A4U, 0x0000004EU}, /* RGIDW_MODID[609]:IPMMUDS011*/ + [575] = {0xE77524A8U, 0x0000004EU}, /* RGIDW_MODID[610]:I2C0*/ + [576] = {0xE77524ACU, 0x0000004EU}, /* RGIDW_MODID[611]:I2C1*/ + [577] = {0xE77524B0U, 0x0000004EU}, /* RGIDW_MODID[612]:I2C2*/ + [578] = {0xE77524B4U, 0x0000004EU}, /* RGIDW_MODID[613]:I2C3*/ + [579] = {0xE77524C0U, 0x0000004EU}, /* RGIDW_MODID[614]:IPMMUDS012*/ + [580] = {0xE77524C8U, 0x0000004EU}, /* RGIDW_MODID[615]:IPMMUDS000*/ + [581] = {0xE77524CCU, 0x0000004EU}, /* RGIDW_MODID[616]:IPMMUDS013*/ + [582] = {0xE77524D0U, 0x0000004EU}, /* RGIDW_MODID[617]:IPMMUDS014*/ + [583] = {0xE77524D4U, 0x0000004EU}, /* RGIDW_MODID[618]:IPMMUDS015*/ + [584] = {0xE77524D8U, 0x0000004EU}, /* RGIDW_MODID[619]:IPMMUDS002*/ + [585] = {0xE77524DCU, 0x0000004EU}, /* RGIDW_MODID[620]:IPMMUDS003*/ + [586] = {0xE77524E0U, 0x0000004EU}, /* RGIDW_MODID[621]:IPMMUDS004*/ + [587] = {0xE77524E4U, 0x0000004EU}, /* RGIDW_MODID[622]:IPMMUDS005*/ + [588] = {0xE77524E8U, 0x0000002CU}, /* RGIDW_MODID[623]:SSI*/ + [589] = {0xE77524ECU, 0x0000004EU}, /* RGIDW_MODID[624]:IPMMUDS006*/ + [590] = {0xE77524F0U, 0x0000004EU}, /* RGIDW_MODID[625]:IPMMUDS007*/ + [591] = {0xE77524F4U, 0x0000000CU}, /* RGIDW_MODID[626]:SYDM1P*/ + [592] = {0xE77524F8U, 0x0000004EU}, /* RGIDW_MODID[627]:IPMMUDS008*/ + [593] = {0xE77524FCU, 0x0000000CU}, /* RGIDW_MODID[628]:SYDM2P*/ + [594] = {0xE7752500U, 0x0000004EU}, /* RGIDW_MODID[629]:IPMMUDS009*/ + [595] = {0xE7752640U, 0x0000000CU}, /* RGIDW_MODID[630]:SYDM100*/ + [596] = {0xE7752644U, 0x0000000CU}, /* RGIDW_MODID[631]:SYDM101*/ + [597] = {0xE7752648U, 0x0000000CU}, /* RGIDW_MODID[632]:SYDM110*/ + [598] = {0xE775264CU, 0x0000000CU}, /* RGIDW_MODID[633]:SYDM111*/ + [599] = {0xE7752650U, 0x0000000CU}, /* RGIDW_MODID[634]:SYDM112*/ + [600] = {0xE7752654U, 0x0000000CU}, /* RGIDW_MODID[635]:SYDM113*/ + [601] = {0xE7752658U, 0x0000000CU}, /* RGIDW_MODID[636]:SYDM114*/ + [602] = {0xE775265CU, 0x0000000CU}, /* RGIDW_MODID[637]:SYDM115*/ + [603] = {0xE7752660U, 0x0000000CU}, /* RGIDW_MODID[638]:SYDM102*/ + [604] = {0xE7752664U, 0x0000000CU}, /* RGIDW_MODID[639]:SYDM103*/ + [605] = {0xE7752668U, 0x0000000CU}, /* RGIDW_MODID[640]:SYDM104*/ + [606] = {0xE775266CU, 0x0000000CU}, /* RGIDW_MODID[641]:SYDM105*/ + [607] = {0xE7752670U, 0x0000000CU}, /* RGIDW_MODID[642]:SYDM106*/ + [608] = {0xE7752674U, 0x0000000CU}, /* RGIDW_MODID[643]:SYDM107*/ + [609] = {0xE7752678U, 0x0000000CU}, /* RGIDW_MODID[644]:SYDM108*/ + [610] = {0xE775267CU, 0x0000000CU}, /* RGIDW_MODID[645]:SYDM109*/ + [611] = {0xE7752680U, 0x0000000CU}, /* RGIDW_MODID[646]:SYDM200*/ + [612] = {0xE7752684U, 0x0000000CU}, /* RGIDW_MODID[647]:SYDM201*/ + [613] = {0xE7752688U, 0x0000000CU}, /* RGIDW_MODID[648]:SYDM210*/ + [614] = {0xE775268CU, 0x0000000CU}, /* RGIDW_MODID[649]:SYDM211*/ + [615] = {0xE7752690U, 0x0000000CU}, /* RGIDW_MODID[650]:SYDM212*/ + [616] = {0xE7752694U, 0x0000000CU}, /* RGIDW_MODID[651]:SYDM213*/ + [617] = {0xE7752698U, 0x0000000CU}, /* RGIDW_MODID[652]:SYDM214*/ + [618] = {0xE775269CU, 0x0000000CU}, /* RGIDW_MODID[653]:SYDM215*/ + [619] = {0xE77526A0U, 0x0000000CU}, /* RGIDW_MODID[654]:SYDM202*/ + [620] = {0xE77526A4U, 0x0000000CU}, /* RGIDW_MODID[655]:SYDM203*/ + [621] = {0xE77526A8U, 0x0000000CU}, /* RGIDW_MODID[656]:SYDM204*/ + [622] = {0xE77526ACU, 0x0000000CU}, /* RGIDW_MODID[657]:SYDM205*/ + [623] = {0xE77526B0U, 0x0000000CU}, /* RGIDW_MODID[658]:SYDM206*/ + [624] = {0xE77526B4U, 0x0000000CU}, /* RGIDW_MODID[659]:SYDM207*/ + [625] = {0xE77526B8U, 0x0000000CU}, /* RGIDW_MODID[660]:SYDM208*/ + [626] = {0xE77526BCU, 0x0000000CU}, /* RGIDW_MODID[661]:SYDM209*/ + [627] = {0xFE682400U, 0x00000002U}, /* RGIDW_MODID[662]:ARVC0*/ + /* After setting */ /* RGIDW_MODID[663]:ARVC1*/ + /* After setting */ /* RGIDW_MODID[664]:ARVC2*/ + [628] = {0xFE68240CU, 0x00000001U}, /* RGIDW_MODID[665]:ARVC3*/ + [629] = {0xFE682410U, 0x0000000EU}, /* RGIDW_MODID[666]:AXIFBABUSVC*/ + [630] = {0xFE682414U, 0x00000002U}, /* RGIDW_MODID[667]:ARVC4*/ + [631] = {0xFE682418U, 0x00000001U}, /* RGIDW_MODID[668]:ARVC5*/ + [632] = {0xFE68241CU, 0x00000002U}, /* RGIDW_MODID[669]:ARVC6*/ + [633] = {0xFE682420U, 0x00000002U}, /* RGIDW_MODID[670]:ARVC7*/ + [634] = {0xFE682424U, 0x00000000U}, /* RGIDW_MODID[671]:ARVC8*/ + [635] = {0xFE68242CU, 0x0000000AU}, /* RGIDW_MODID[672]:ECMVC0*/ + [636] = {0xFE682434U, 0x0000004EU}, /* RGIDW_MODID[673]:IMR0*/ + [637] = {0xFE682438U, 0x0000004EU}, /* RGIDW_MODID[674]:IMR1*/ + [638] = {0xFE68243CU, 0x0000004EU}, /* RGIDW_MODID[675]:IPMMUVC01*/ + [639] = {0xFE682440U, 0x0000004EU}, /* RGIDW_MODID[676]:IPMMUVC10*/ + [640] = {0xFE682444U, 0x0000000CU}, /* RGIDW_MODID[677]:IMS0*/ + [641] = {0xFE682448U, 0x0000000CU}, /* RGIDW_MODID[678]:IMS1*/ + [642] = {0xFE68244CU, 0x0000004EU}, /* RGIDW_MODID[679]:IPMMUVC00*/ + [643] = {0xFE682450U, 0x0000004EU}, /* RGIDW_MODID[680]:IPMMUVC11*/ + [644] = {0xFE682454U, 0x0000004EU}, /* RGIDW_MODID[681]:IPMMUVC12*/ + [645] = {0xFE682458U, 0x0000004EU}, /* RGIDW_MODID[682]:IPMMUVC13*/ + [646] = {0xFE68245CU, 0x0000004EU}, /* RGIDW_MODID[683]:IPMMUVC14*/ + [647] = {0xFE682460U, 0x0000004EU}, /* RGIDW_MODID[684]:IPMMUVC15*/ + [648] = {0xFE682464U, 0x0000004EU}, /* RGIDW_MODID[685]:IPMMUVC02*/ + [649] = {0xFE682468U, 0x0000004EU}, /* RGIDW_MODID[686]:IPMMUVC03*/ + [650] = {0xFE68246CU, 0x0000004EU}, /* RGIDW_MODID[687]:IPMMUVC04*/ + [651] = {0xFE682470U, 0x0000004EU}, /* RGIDW_MODID[688]:IPMMUVC05*/ + [652] = {0xFE682474U, 0x0000004EU}, /* RGIDW_MODID[689]:IPMMUVC06*/ + [653] = {0xFE682478U, 0x0000004EU}, /* RGIDW_MODID[690]:IPMMUVC07*/ + [654] = {0xFE68247CU, 0x0000004EU}, /* RGIDW_MODID[691]:IPMMUVC08*/ + [655] = {0xFE682480U, 0x0000004EU}, /* RGIDW_MODID[692]:IPMMUVC09*/ + [656] = {0xFE682484U, 0x00000028U}, /* RGIDW_MODID[693]:IV1ES*/ + [657] = {0xFEBE2400U, 0x0000004EU}, /* RGIDW_MODID[694]:CSITOP0*/ + [658] = {0xFEBE2404U, 0x00000002U}, /* RGIDW_MODID[695]:ARVI10*/ + /* After setting */ /* RGIDW_MODID[696]:ARVI11*/ + /* After setting */ /* RGIDW_MODID[697]:ARVI12*/ + [659] = {0xFEBE2410U, 0x00000001U}, /* RGIDW_MODID[698]:ARVI13*/ + [660] = {0xFEBE2414U, 0x00000002U}, /* RGIDW_MODID[699]:ARVI14*/ + [661] = {0xFEBE2418U, 0x00000001U}, /* RGIDW_MODID[700]:ARVI15*/ + [662] = {0xFEBE241CU, 0x00000002U}, /* RGIDW_MODID[701]:ARVI16*/ + [663] = {0xFEBE2420U, 0x00000002U}, /* RGIDW_MODID[702]:ARVI17*/ + [664] = {0xFEBE2424U, 0x00000000U}, /* RGIDW_MODID[703]:ARVI18*/ + [665] = {0xFEBE242CU, 0x0000004EU}, /* RGIDW_MODID[704]:CSITOP1*/ + [666] = {0xFEBE2434U, 0x0000004EU}, /* RGIDW_MODID[705]:DSITLINK0*/ + [667] = {0xFEBE243CU, 0x0000000AU}, /* RGIDW_MODID[706]:ECMVIO1*/ + [668] = {0xFEBE2444U, 0x0000004EU}, /* RGIDW_MODID[707]:IPMMUVI001*/ + [669] = {0xFEBE2448U, 0x0000000CU}, /* RGIDW_MODID[708]:FCPVX0*/ + [670] = {0xFEBE2458U, 0x0000004EU}, /* RGIDW_MODID[709]:IPMMUVI000*/ + [671] = {0xFEBE245CU, 0x0000004EU}, /* RGIDW_MODID[710]:IPMMUVI100*/ + [672] = {0xFEBE2460U, 0x0000004EU}, /* RGIDW_MODID[711]:IPMMUVI010*/ + [673] = {0xFEBE2464U, 0x0000004EU}, /* RGIDW_MODID[712]:IPMMUVI011*/ + [674] = {0xFEBE2468U, 0x0000004EU}, /* RGIDW_MODID[713]:VSPX0*/ + [675] = {0xFEBE2478U, 0x0000004EU}, /* RGIDW_MODID[714]:IPMMUVI012*/ + [676] = {0xFEBE247CU, 0x0000004EU}, /* RGIDW_MODID[715]:IPMMUVI013*/ + [677] = {0xFEBE2480U, 0x0000004EU}, /* RGIDW_MODID[716]:IPMMUVI014*/ + [678] = {0xFEBE2484U, 0x0000004EU}, /* RGIDW_MODID[717]:IPMMUVI015*/ + [679] = {0xFEBE2488U, 0x0000004EU}, /* RGIDW_MODID[718]:IPMMUVI002*/ + [680] = {0xFEBE248CU, 0x0000004EU}, /* RGIDW_MODID[719]:IPMMUVI003*/ + [681] = {0xFEBE2490U, 0x0000004EU}, /* RGIDW_MODID[720]:IPMMUVI004*/ + [682] = {0xFEBE2494U, 0x0000004EU}, /* RGIDW_MODID[721]:IPMMUVI005*/ + [683] = {0xFEBE2498U, 0x0000004EU}, /* RGIDW_MODID[722]:IPMMUVI006*/ + [684] = {0xFEBE249CU, 0x0000004EU}, /* RGIDW_MODID[723]:IPMMUVI007*/ + [685] = {0xFEBE24A0U, 0x0000004EU}, /* RGIDW_MODID[724]:IPMMUVI008*/ + [686] = {0xFEBE24A4U, 0x0000004EU}, /* RGIDW_MODID[725]:IPMMUVI009*/ + [687] = {0xFEBE24A8U, 0x0000004EU}, /* RGIDW_MODID[726]:IPMMUVI101*/ + [688] = {0xFEBE24ACU, 0x0000004EU}, /* RGIDW_MODID[727]:IPMMUVI110*/ + [689] = {0xFEBE24B0U, 0x0000004EU}, /* RGIDW_MODID[728]:IPMMUVI111*/ + [690] = {0xFEBE24B4U, 0x0000004EU}, /* RGIDW_MODID[729]:IPMMUVI112*/ + [691] = {0xFEBE24B8U, 0x0000004EU}, /* RGIDW_MODID[730]:IPMMUVI113*/ + [692] = {0xFEBE24BCU, 0x0000004EU}, /* RGIDW_MODID[731]:IPMMUVI114*/ + [693] = {0xFEBE24C0U, 0x0000004EU}, /* RGIDW_MODID[732]:IPMMUVI115*/ + [694] = {0xFEBE24C4U, 0x0000004EU}, /* RGIDW_MODID[733]:IPMMUVI102*/ + [695] = {0xFEBE24C8U, 0x0000004EU}, /* RGIDW_MODID[734]:IPMMUVI103*/ + [696] = {0xFEBE24CCU, 0x0000004EU}, /* RGIDW_MODID[735]:IPMMUVI104*/ + [697] = {0xFEBE24D0U, 0x0000004EU}, /* RGIDW_MODID[736]:IPMMUVI105*/ + [698] = {0xFEBE24D4U, 0x0000004EU}, /* RGIDW_MODID[737]:IPMMUVI106*/ + [699] = {0xFEBE24D8U, 0x0000004EU}, /* RGIDW_MODID[738]:IPMMUVI107*/ + [700] = {0xFEBE24DCU, 0x0000004EU}, /* RGIDW_MODID[739]:IPMMUVI108*/ + [701] = {0xFEBE24E0U, 0x0000004EU}, /* RGIDW_MODID[740]:IPMMUVI109*/ + [702] = {0xFEBE2504U, 0x0000000EU}, /* RGIDW_MODID[741]:AXIFBABUSVIO*/ + [703] = {0xFEBF2400U, 0x00000002U}, /* RGIDW_MODID[742]:ARVI0*/ + /* After setting */ /* RGIDW_MODID[743]:ARVI1*/ + /* After setting */ /* RGIDW_MODID[744]:ARVI2*/ + [704] = {0xFEBF240CU, 0x00000001U}, /* RGIDW_MODID[745]:ARVI3*/ + [705] = {0xFEBF2410U, 0x00000002U}, /* RGIDW_MODID[746]:ARVI4*/ + [706] = {0xFEBF2414U, 0x00000001U}, /* RGIDW_MODID[747]:ARVI5*/ + [707] = {0xFEBF2418U, 0x00000002U}, /* RGIDW_MODID[748]:ARVI6*/ + [708] = {0xFEBF241CU, 0x00000002U}, /* RGIDW_MODID[749]:ARVI7*/ + [709] = {0xFEBF2420U, 0x00000000U}, /* RGIDW_MODID[750]:ARVI8*/ + [710] = {0xFEBF2424U, 0x0000000AU}, /* RGIDW_MODID[751]:ECMVIO0*/ + [711] = {0xFEBF2428U, 0x0000004EU}, /* RGIDW_MODID[752]:ISP0*/ + [712] = {0xFEBF242CU, 0x0000004EU}, /* RGIDW_MODID[753]:ISP0CORE*/ + [713] = {0xFEBF2430U, 0x0000004EU}, /* RGIDW_MODID[754]:ISP1*/ + [714] = {0xFEBF2454U, 0x0000004EU}, /* RGIDW_MODID[755]:VIN00*/ + [715] = {0xFEBF2458U, 0x0000004EU}, /* RGIDW_MODID[756]:VIN01*/ + [716] = {0xFEBF245CU, 0x0000004EU}, /* RGIDW_MODID[757]:VIN02*/ + [717] = {0xFEBF2460U, 0x0000004EU}, /* RGIDW_MODID[758]:VIN03*/ + [718] = {0xFEBF2464U, 0x0000004EU}, /* RGIDW_MODID[759]:VIN04*/ + [719] = {0xFEBF2468U, 0x0000004EU}, /* RGIDW_MODID[760]:VIN05*/ + [720] = {0xFEBF246CU, 0x0000004EU}, /* RGIDW_MODID[761]:VIN06*/ + [721] = {0xFEBF2470U, 0x0000004EU}, /* RGIDW_MODID[762]:VIN07*/ + [722] = {0xFEBF2474U, 0x0000004EU}, /* RGIDW_MODID[763]:VIN10*/ + [723] = {0xFEBF2478U, 0x0000004EU}, /* RGIDW_MODID[764]:VIN11*/ + [724] = {0xFEBF247CU, 0x0000004EU}, /* RGIDW_MODID[765]:VIN12*/ + [725] = {0xFEBF2480U, 0x0000004EU}, /* RGIDW_MODID[766]:VIN13*/ + [726] = {0xFEBF2484U, 0x0000004EU}, /* RGIDW_MODID[767]:VIN14*/ + [727] = {0xFEBF2488U, 0x0000004EU}, /* RGIDW_MODID[768]:VIN15*/ + [728] = {0xFEBF248CU, 0x0000004EU}, /* RGIDW_MODID[769]:VIN16*/ + [729] = {0xFEBF2490U, 0x0000004EU}, /* RGIDW_MODID[770]:VIN17*/ + [730] = {0xE7B12400U, 0x00000002U}, /* RGIDW_MODID[771]:ARVIP00*/ + /* After setting */ /* RGIDW_MODID[772]:ARVIP01*/ + /* After setting */ /* RGIDW_MODID[773]:ARVIP02*/ + [731] = {0xE7B1240CU, 0x00000001U}, /* RGIDW_MODID[774]:ARVIP03*/ + [732] = {0xE7B12410U, 0x0000000EU}, /* RGIDW_MODID[775]:AXIFBABUSVIP0*/ + [733] = {0xE7B12414U, 0x00000002U}, /* RGIDW_MODID[776]:ARVIP04*/ + [734] = {0xE7B12418U, 0x00000001U}, /* RGIDW_MODID[777]:ARVIP05*/ + [735] = {0xE7B1241CU, 0x00000002U}, /* RGIDW_MODID[778]:ARVIP06*/ + [736] = {0xE7B12420U, 0x00000002U}, /* RGIDW_MODID[779]:ARVIP07*/ + [737] = {0xE7B12424U, 0x00000000U}, /* RGIDW_MODID[780]:ARVIP08*/ + [738] = {0xE7B1242CU, 0x0000000AU}, /* RGIDW_MODID[781]:ECMVIP0*/ + [739] = {0xE7B12430U, 0x0000004EU}, /* RGIDW_MODID[782]:IPMMUVIP000*/ + [740] = {0xE7B12438U, 0x0000004EU}, /* RGIDW_MODID[783]:SMPO0*/ + [741] = {0xE7B1243CU, 0x0000004EU}, /* RGIDW_MODID[784]:SMPS0*/ + [742] = {0xE7B12440U, 0x0000004EU}, /* RGIDW_MODID[785]:UMFL0*/ + [743] = {0xE7B12444U, 0x0000004EU}, /* RGIDW_MODID[786]:IPMMUVIP001*/ + [744] = {0xE7B12448U, 0x0000004EU}, /* RGIDW_MODID[787]:IPMMUVIP010*/ + [745] = {0xE7B1244CU, 0x0000004EU}, /* RGIDW_MODID[788]:IPMMUVIP011*/ + [746] = {0xE7B12450U, 0x0000004EU}, /* RGIDW_MODID[789]:UMFL0M_W*/ + [747] = {0xE7B12454U, 0x0000004EU}, /* RGIDW_MODID[790]:IPMMUVIP012*/ + [748] = {0xE7B12458U, 0x0000004EU}, /* RGIDW_MODID[791]:IPMMUVIP013*/ + [749] = {0xE7B1245CU, 0x0000004EU}, /* RGIDW_MODID[792]:IPMMUVIP014*/ + [750] = {0xE7B12460U, 0x0000004EU}, /* RGIDW_MODID[793]:IPMMUVIP015*/ + [751] = {0xE7B12464U, 0x0000004EU}, /* RGIDW_MODID[794]:IPMMUVIP002*/ + [752] = {0xE7B12468U, 0x0000004EU}, /* RGIDW_MODID[795]:IPMMUVIP003*/ + [753] = {0xE7B1246CU, 0x0000004EU}, /* RGIDW_MODID[796]:IPMMUVIP004*/ + [754] = {0xE7B12470U, 0x0000004EU}, /* RGIDW_MODID[797]:IPMMUVIP005*/ + [755] = {0xE7B12474U, 0x0000004EU}, /* RGIDW_MODID[798]:IPMMUVIP006*/ + [756] = {0xE7B12478U, 0x0000004EU}, /* RGIDW_MODID[799]:IPMMUVIP007*/ + [757] = {0xE7B1247CU, 0x0000004EU}, /* RGIDW_MODID[800]:IPMMUVIP008*/ + [758] = {0xE7B12480U, 0x0000004EU}, /* RGIDW_MODID[801]:IPMMUVIP009*/ + [759] = {0xFF8824A0U, 0x00000002U}, /* RGIDW_MODID[802]:ARDSP0*/ + /* After setting */ /* RGIDW_MODID[803]:ARDSP1*/ + /* After setting */ /* RGIDW_MODID[804]:ARDSP2*/ + [760] = {0xFF8824ACU, 0x00000001U}, /* RGIDW_MODID[805]:ARDSP3*/ + [761] = {0xFF8824B0U, 0x00000002U}, /* RGIDW_MODID[806]:ARDSP4*/ + [762] = {0xFF8824B4U, 0x00000001U}, /* RGIDW_MODID[807]:ARDSP5*/ + [763] = {0xFF8824B8U, 0x00000002U}, /* RGIDW_MODID[808]:ARDSP6*/ + [764] = {0xFF8824BCU, 0x00000002U}, /* RGIDW_MODID[809]:ARDSP7*/ + [765] = {0xFF8824C0U, 0x0000000AU}, /* RGIDW_MODID[810]:ECMDSP*/ + [766] = {0xFF882490U, 0x0000000CU}, /* RGIDW_MODID[811]:AXIDSP0*/ + [767] = {0xFF882494U, 0x0000000CU}, /* RGIDW_MODID[812]:AXIDSP1*/ + [768] = {0xFF882498U, 0x0000000CU}, /* RGIDW_MODID[813]:AXIDSP2*/ + [769] = {0xFF88249CU, 0x0000000CU}, /* RGIDW_MODID[814]:AXIDSP3*/ + [771] = {0xE67B969CU, 0x00000000U}, /* RGIDW_MODID[815]:ARCC*/ + [770] = {0xE67B96B0U, 0x00000000U}, /* RGIDW_MODID[816]:ARRTRAM*/ + [772] = {0xE7752424U, 0x00000000U}, /* RGIDW_MODID[817]:RSV0*/ + [773] = {0xE7B1250CU, 0x00000004U}, /* RGIDW_MODID[818]:PAP*/ + [774] = {0xFF8824C4U, 0x0000004EU}, /* RGIDW_MODID[819]:IMPM0100*/ + [775] = {0xFF8824C8U, 0x0000004EU}, /* RGIDW_MODID[820]:IMPM0101*/ + [776] = {0xFF8824CCU, 0x0000004EU}, /* RGIDW_MODID[821]:IMPM0102*/ + [777] = {0xFF8824D0U, 0x0000004EU}, /* RGIDW_MODID[822]:IMPM0103*/ + [778] = {0xFF8824D4U, 0x0000004EU}, /* RGIDW_MODID[823]:IMPM0104*/ + [779] = {0xFF8824D8U, 0x0000004EU}, /* RGIDW_MODID[824]:IMPM0105*/ + [780] = {0xFF8824DCU, 0x0000004EU}, /* RGIDW_MODID[825]:IMPM0106*/ + [781] = {0xFF8824E0U, 0x0000004EU}, /* RGIDW_MODID[826]:IMPM0107*/ + [782] = {0xFF8824E4U, 0x0000004EU}, /* RGIDW_MODID[827]:IMPM0200*/ + [783] = {0xFF8824E8U, 0x0000004EU}, /* RGIDW_MODID[828]:IMPM0201*/ + [784] = {0xFF8824ECU, 0x0000004EU}, /* RGIDW_MODID[829]:IMPS0000*/ + [785] = {0xFF8824F0U, 0x0000004EU}, /* RGIDW_MODID[830]:IMPS0001*/ + [786] = {0xFF8824F4U, 0x0000004EU}, /* RGIDW_MODID[831]:IMPS0002*/ + [787] = {0xFF8824F8U, 0x0000004EU}, /* RGIDW_MODID[832]:IMPS0003*/ + [788] = {0xFF8824FCU, 0x0000004EU}, /* RGIDW_MODID[833]:IMPS0100*/ + [789] = {0xFF882500U, 0x0000004EU}, /* RGIDW_MODID[834]:IMPS0101*/ + [790] = {0xFF882504U, 0x0000004EU}, /* RGIDW_MODID[835]:IMPS0102*/ + [791] = {0xFF882508U, 0x0000004EU}, /* RGIDW_MODID[836]:IMPS0103*/ + [792] = {0xFF88250CU, 0x0000004EU}, /* RGIDW_MODID[837]:IMPS0104*/ + [793] = {0xFF882510U, 0x0000004EU}, /* RGIDW_MODID[838]:IMPS0105*/ + [794] = {0xFF882514U, 0x0000004EU}, /* RGIDW_MODID[839]:IMPS0106*/ + [795] = {0xFF882518U, 0x0000004EU}, /* RGIDW_MODID[840]:IMPS0107*/ + [796] = {0xFF88251CU, 0x0000004EU}, /* RGIDW_MODID[841]:IMPS0108*/ + [797] = {0xFF882520U, 0x0000004EU}, /* RGIDW_MODID[842]:IMPS0109*/ + [798] = {0xFF882524U, 0x0000004EU}, /* RGIDW_MODID[843]:IMPS0110*/ + [799] = {0xFF882528U, 0x0000004EU}, /* RGIDW_MODID[844]:IMPS0111*/ + [800] = {0xFF88252CU, 0x0000004EU}, /* RGIDW_MODID[845]:IMPS0200*/ + [801] = {0xFF882530U, 0x0000004EU}, /* RGIDW_MODID[846]:IMPS0201*/ + [802] = {0xFF882534U, 0x0000004EU}, /* RGIDW_MODID[847]:IMPS0202*/ + [803] = {0xFEBD2428U, 0x0000000CU}, /* RGIDW_MODID[848]:DOC*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_sec_tbl" +#else +__attribute__ ((section(".rgid_sec_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[] = { + [0] = {0xFFC83400U, 0x00000000U}, /* SEC_MODID[0]:ARMGC0*/ + [1] = {0xFFC83404U, 0x00000002U}, /* SEC_MODID[1]:ARMGC1*/ + [2] = {0xFFC83408U, 0x00000002U}, /* SEC_MODID[2]:ARMGC2*/ + [3] = {0xFFC8340CU, 0x00000002U}, /* SEC_MODID[3]:ARRT00*/ + [4] = {0xFFC83410U, 0x00000002U}, /* SEC_MODID[4]:ARRT01*/ + [5] = {0xFFC83414U, 0x00000002U}, /* SEC_MODID[5]:ARRT02*/ + [6] = {0xFFC83418U, 0x00000002U}, /* SEC_MODID[6]:ARRT03*/ + [7] = {0xFFC8341CU, 0x00000002U}, /* SEC_MODID[7]:ARRT04*/ + [8] = {0xFFC83420U, 0x00000002U}, /* SEC_MODID[8]:ARRT05*/ + [9] = {0xFFC83424U, 0x00000002U}, /* SEC_MODID[9]:ARRT06*/ + [10] = {0xFFC83428U, 0x00000002U}, /* SEC_MODID[10]:ARRT07*/ + [11] = {0xFFC8342CU, 0x00000002U}, /* SEC_MODID[11]:ARRT08*/ + [12] = {0xFFC83430U, 0x00000000U}, /* SEC_MODID[12]:LIFEC0*/ + [13] = {0xFFC83434U, 0x00000002U}, /* SEC_MODID[13]:SWDT*/ + [14] = {0xFFC83438U, 0x00000002U}, /* SEC_MODID[14]:TMU0*/ + [15] = {0xFFC8343CU, 0x00000002U}, /* SEC_MODID[15]:WDT*/ + [16] = {0xFFC83440U, 0x00000002U}, /* SEC_MODID[16]:WWDT0*/ + [17] = {0xFFC83444U, 0x00000002U}, /* SEC_MODID[17]:WWDT1*/ + [18] = {0xFFC83448U, 0x00000002U}, /* SEC_MODID[18]:WWDT2*/ + [19] = {0xFFC8344CU, 0x00000002U}, /* SEC_MODID[19]:WWDT3*/ + [20] = {0xFFC83450U, 0x00000002U}, /* SEC_MODID[20]:WWDT4*/ + [21] = {0xFFC83454U, 0x00000002U}, /* SEC_MODID[21]:WWDT5*/ + [22] = {0xFFC83458U, 0x00000002U}, /* SEC_MODID[22]:WWDT6*/ + [23] = {0xFFC83468U, 0x00000002U}, /* SEC_MODID[23]:ECMRT3*/ + [24] = {0xE6003404U, 0x00000002U}, /* SEC_MODID[24]:APMU0*/ + [25] = {0xE6003408U, 0x00000002U}, /* SEC_MODID[25]:APMU1*/ + [26] = {0xE600340CU, 0x00000002U}, /* SEC_MODID[26]:APMU10*/ + [27] = {0xE6003410U, 0x00000002U}, /* SEC_MODID[27]:APMU11*/ + [28] = {0xE6003414U, 0x00000002U}, /* SEC_MODID[28]:APMU12*/ + [29] = {0xE6003418U, 0x00000002U}, /* SEC_MODID[29]:APMU13*/ + [30] = {0xE600341CU, 0x00000002U}, /* SEC_MODID[30]:APMU14*/ + [31] = {0xE6003420U, 0x00000002U}, /* SEC_MODID[31]:APMU15*/ + [32] = {0xE6003424U, 0x00000002U}, /* SEC_MODID[32]:APMU2*/ + [33] = {0xE6003428U, 0x00000002U}, /* SEC_MODID[33]:APMU3*/ + [34] = {0xE600342CU, 0x00000002U}, /* SEC_MODID[34]:APMU4*/ + [35] = {0xE6003430U, 0x00000002U}, /* SEC_MODID[35]:APMU5*/ + [36] = {0xE6003434U, 0x00000002U}, /* SEC_MODID[36]:APMU6*/ + [37] = {0xE6003438U, 0x00000002U}, /* SEC_MODID[37]:APMU7*/ + [38] = {0xE600343CU, 0x00000002U}, /* SEC_MODID[38]:APMU8*/ + [39] = {0xE6003440U, 0x00000002U}, /* SEC_MODID[39]:APMU9*/ + [40] = {0xE6003444U, 0x00000002U}, /* SEC_MODID[40]:ARS00*/ + [41] = {0xE6003448U, 0x00000002U}, /* SEC_MODID[41]:ARS01*/ + [42] = {0xE600344CU, 0x00000002U}, /* SEC_MODID[42]:ARS02*/ + [43] = {0xE6003450U, 0x00000002U}, /* SEC_MODID[43]:ARS03*/ + [44] = {0xE6003454U, 0x00000002U}, /* SEC_MODID[44]:ARS04*/ + [45] = {0xE6003458U, 0x00000002U}, /* SEC_MODID[45]:ARS05*/ + [46] = {0xE600345CU, 0x00000002U}, /* SEC_MODID[46]:ARS06*/ + [47] = {0xE6003460U, 0x00000002U}, /* SEC_MODID[47]:ARS07*/ + [48] = {0xE6003464U, 0x00000002U}, /* SEC_MODID[48]:ARS08*/ + [49] = {0xE6003468U, 0x00000002U}, /* SEC_MODID[49]:CMT0*/ + [50] = {0xE600346CU, 0x00000002U}, /* SEC_MODID[50]:CMT1*/ + [51] = {0xE6003470U, 0x00000002U}, /* SEC_MODID[51]:CMT2*/ + [52] = {0xE6003474U, 0x00000002U}, /* SEC_MODID[52]:CMT3*/ + [53] = {0xE6003478U, 0x00000002U}, /* SEC_MODID[53]:CKM*/ + [54] = {0xE600347CU, 0x00000002U}, /* SEC_MODID[54]:DBE*/ + [55] = {0xE6003480U, 0x00000002U}, /* SEC_MODID[55]:IRQC*/ + [56] = {0xE6003484U, 0x00000002U}, /* SEC_MODID[56]:ECMPS0*/ + [57] = {0xE6003488U, 0x00000002U}, /* SEC_MODID[57]:OTP0*/ + [58] = {0xE600348CU, 0x00000002U}, /* SEC_MODID[58]:OTP1*/ + [59] = {0xE600349CU, 0x00000002U}, /* SEC_MODID[59]:SCMT*/ + [60] = {0xE60034A8U, 0x00000002U}, /* SEC_MODID[60]:TSC1*/ + [61] = {0xE60034ACU, 0x00000002U}, /* SEC_MODID[61]:TSC2*/ + [62] = {0xE60034B8U, 0x00000002U}, /* SEC_MODID[62]:UCMT*/ + [63] = {0xE6003500U, 0x00000002U}, /* SEC_MODID[63]:CPG0*/ + [64] = {0xE6003504U, 0x00000002U}, /* SEC_MODID[64]:CPG1*/ + [65] = {0xE6003508U, 0x00000002U}, /* SEC_MODID[65]:CPG2*/ + [66] = {0xE600350CU, 0x00000002U}, /* SEC_MODID[66]:CPG3*/ + [67] = {0xE6003510U, 0x00000002U}, /* SEC_MODID[67]:PFC00*/ + [68] = {0xE6003514U, 0x00000002U}, /* SEC_MODID[68]:PFC01*/ + [69] = {0xE6003518U, 0x00000002U}, /* SEC_MODID[69]:PFC02*/ + [70] = {0xE600351CU, 0x00000002U}, /* SEC_MODID[70]:PFC03*/ + [71] = {0xE6003520U, 0x00000002U}, /* SEC_MODID[71]:PFC10*/ + [72] = {0xE6003524U, 0x00000002U}, /* SEC_MODID[72]:PFC11*/ + [73] = {0xE6003528U, 0x00000002U}, /* SEC_MODID[73]:PFC12*/ + [74] = {0xE600352CU, 0x00000002U}, /* SEC_MODID[74]:PFC13*/ + [75] = {0xE6003530U, 0x00000002U}, /* SEC_MODID[75]:PFC20*/ + [76] = {0xE6003534U, 0x00000002U}, /* SEC_MODID[76]:PFC21*/ + [77] = {0xE6003538U, 0x00000002U}, /* SEC_MODID[77]:PFC22*/ + [78] = {0xE600353CU, 0x00000002U}, /* SEC_MODID[78]:PFC23*/ + [79] = {0xE6003550U, 0x00000002U}, /* SEC_MODID[79]:PFCS0*/ + [80] = {0xE6003554U, 0x00000002U}, /* SEC_MODID[80]:PFCS1*/ + [81] = {0xE6003558U, 0x00000002U}, /* SEC_MODID[81]:PFCS2*/ + [82] = {0xE600355CU, 0x00000002U}, /* SEC_MODID[82]:PFCS3*/ + [83] = {0xE6003560U, 0x00000002U}, /* SEC_MODID[83]:RESET0*/ + [84] = {0xE6003564U, 0x00000002U}, /* SEC_MODID[84]:RESET1*/ + [85] = {0xE6003568U, 0x00000002U}, /* SEC_MODID[85]:RESET2*/ + [86] = {0xE600356CU, 0x00000002U}, /* SEC_MODID[86]:RESET3*/ + [87] = {0xE6003570U, 0x00000002U}, /* SEC_MODID[87]:SYS0*/ + [88] = {0xE6003574U, 0x00000002U}, /* SEC_MODID[88]:SYS1*/ + [89] = {0xE6003578U, 0x00000002U}, /* SEC_MODID[89]:SYS2*/ + [90] = {0xE600357CU, 0x00000002U}, /* SEC_MODID[90]:SYS3*/ + [91] = {0xE7763400U, 0x00000002U}, /* SEC_MODID[91]:DMAMSI0*/ + [92] = {0xE7763404U, 0x00000002U}, /* SEC_MODID[92]:DMAMSI1*/ + [93] = {0xE7763408U, 0x00000002U}, /* SEC_MODID[93]:DMAMSI2*/ + [94] = {0xE776340CU, 0x00000002U}, /* SEC_MODID[94]:DMAMSI3*/ + [95] = {0xE7763410U, 0x00000002U}, /* SEC_MODID[95]:DMAMSI4*/ + [96] = {0xE7763414U, 0x00000002U}, /* SEC_MODID[96]:DMAMSI5*/ + [97] = {0xE7763418U, 0x00000002U}, /* SEC_MODID[97]:ECMSP3*/ + [98] = {0xE7763424U, 0x00000002U}, /* SEC_MODID[98]:ARSP30*/ + [99] = {0xE7763428U, 0x00000002U}, /* SEC_MODID[99]:ARSP31*/ + [100] = {0xE776342CU, 0x00000002U}, /* SEC_MODID[100]:ARSP32*/ + [101] = {0xE7763430U, 0x00000002U}, /* SEC_MODID[101]:ARSP33*/ + [102] = {0xE7763434U, 0x00000002U}, /* SEC_MODID[102]:ARSP34*/ + [103] = {0xE7763438U, 0x00000002U}, /* SEC_MODID[103]:ARSP35*/ + [104] = {0xE776343CU, 0x00000002U}, /* SEC_MODID[104]:ARSP36*/ + [105] = {0xE7763440U, 0x00000002U}, /* SEC_MODID[105]:ARSP37*/ + [106] = {0xE7763444U, 0x00000002U}, /* SEC_MODID[106]:ARSP38*/ + [107] = {0xE7763448U, 0x00000002U}, /* SEC_MODID[107]:MSI0*/ + [108] = {0xE776344CU, 0x00000002U}, /* SEC_MODID[108]:MSI1*/ + [109] = {0xE7763450U, 0x00000002U}, /* SEC_MODID[109]:MSI2*/ + [110] = {0xE7763454U, 0x00000002U}, /* SEC_MODID[110]:MSI3*/ + [111] = {0xE7763458U, 0x00000002U}, /* SEC_MODID[111]:MSI4*/ + [112] = {0xE776345CU, 0x00000002U}, /* SEC_MODID[112]:MSI5*/ + [113] = {0xE7793400U, 0x00000002U}, /* SEC_MODID[113]:ARSP40*/ + [114] = {0xE7793404U, 0x00000002U}, /* SEC_MODID[114]:ARSP41*/ + [115] = {0xE7793408U, 0x00000002U}, /* SEC_MODID[115]:ARSP42*/ + [116] = {0xE779340CU, 0x00000002U}, /* SEC_MODID[116]:ARSP43*/ + [117] = {0xE7793410U, 0x00000002U}, /* SEC_MODID[117]:ARSP44*/ + [118] = {0xE7793414U, 0x00000002U}, /* SEC_MODID[118]:ARSP45*/ + [119] = {0xE7793418U, 0x00000002U}, /* SEC_MODID[119]:ARSP46*/ + [120] = {0xE779341CU, 0x00000002U}, /* SEC_MODID[120]:ARSP47*/ + [121] = {0xE7793420U, 0x00000002U}, /* SEC_MODID[121]:ARSP48*/ + [122] = {0xE7793424U, 0x00000002U}, /* SEC_MODID[122]:DMAHSCIF0*/ + [123] = {0xE7793428U, 0x00000002U}, /* SEC_MODID[123]:DMAHSCIF1*/ + [124] = {0xE779342CU, 0x00000002U}, /* SEC_MODID[124]:DMAHSCIF2*/ + [125] = {0xE7793430U, 0x00000002U}, /* SEC_MODID[125]:DMAHSCIF3*/ + [126] = {0xE7793434U, 0x00000002U}, /* SEC_MODID[126]:DMASCIF0*/ + [127] = {0xE7793438U, 0x00000002U}, /* SEC_MODID[127]:DMASCIF1*/ + [128] = {0xE779343CU, 0x00000002U}, /* SEC_MODID[128]:DMASCIF3*/ + [129] = {0xE7793440U, 0x00000002U}, /* SEC_MODID[129]:DMASCIF4*/ + [130] = {0xE7793444U, 0x00000002U}, /* SEC_MODID[130]:ECMSP4*/ + [131] = {0xE7793448U, 0x00000002U}, /* SEC_MODID[131]:HSCIF0*/ + [132] = {0xE779344CU, 0x00000002U}, /* SEC_MODID[132]:HSCIF1*/ + [133] = {0xE7793450U, 0x00000002U}, /* SEC_MODID[133]:HSCIF2*/ + [134] = {0xE7793454U, 0x00000002U}, /* SEC_MODID[134]:HSCIF3*/ + [135] = {0xE7793458U, 0x00000002U}, /* SEC_MODID[135]:SCIF0*/ + [136] = {0xE779345CU, 0x00000002U}, /* SEC_MODID[136]:SCIF1*/ + [137] = {0xE7793460U, 0x00000002U}, /* SEC_MODID[137]:SCIF3*/ + [138] = {0xE7793464U, 0x00000002U}, /* SEC_MODID[138]:SCIF4*/ + [139] = {0xE7793468U, 0x00000002U}, /* SEC_MODID[139]:TMU1*/ + [140] = {0xE779346CU, 0x00000002U}, /* SEC_MODID[140]:TMU2*/ + [141] = {0xE7793470U, 0x00000002U}, /* SEC_MODID[141]:TMU3*/ + [142] = {0xE7793474U, 0x00000002U}, /* SEC_MODID[142]:TMU4*/ + [143] = {0xE7793478U, 0x00000002U}, /* SEC_MODID[143]:CANFD*/ + [144] = {0xE779347CU, 0x00000002U}, /* SEC_MODID[144]:DMACANFD*/ + [145] = {0xE7793480U, 0x00000002U}, /* SEC_MODID[145]:DMATPU0*/ + [146] = {0xE7793484U, 0x00000002U}, /* SEC_MODID[146]:PWM0*/ + [147] = {0xE7793488U, 0x00000002U}, /* SEC_MODID[147]:PWM1*/ + [148] = {0xE779348CU, 0x00000002U}, /* SEC_MODID[148]:PWM2*/ + [149] = {0xE7793490U, 0x00000002U}, /* SEC_MODID[149]:PWM3*/ + [150] = {0xE7793494U, 0x00000002U}, /* SEC_MODID[150]:PWM4*/ + [151] = {0xE77934ACU, 0x00000002U}, /* SEC_MODID[151]:TPU0*/ + [152] = {0xFEBD3400U, 0x00000002U}, /* SEC_MODID[152]:ARVI40*/ + [153] = {0xFEBD3404U, 0x00000002U}, /* SEC_MODID[153]:ARVI41*/ + [154] = {0xFEBD3408U, 0x00000002U}, /* SEC_MODID[154]:ARVI42*/ + [155] = {0xFEBD340CU, 0x00000002U}, /* SEC_MODID[155]:ARVI43*/ + [156] = {0xFEBD3410U, 0x00000002U}, /* SEC_MODID[156]:ARVI44*/ + [157] = {0xFEBD3414U, 0x00000002U}, /* SEC_MODID[157]:ARVI45*/ + [158] = {0xFEBD3418U, 0x00000002U}, /* SEC_MODID[158]:ARVI46*/ + [159] = {0xFEBD341CU, 0x00000002U}, /* SEC_MODID[159]:ARVI47*/ + [160] = {0xFEBD3420U, 0x00000002U}, /* SEC_MODID[160]:ARVI48*/ + [161] = {0xFEBD3424U, 0x00000002U}, /* SEC_MODID[161]:DIS0*/ + [162] = {0xFEBD3430U, 0x00000002U}, /* SEC_MODID[162]:ECMVIO2*/ + [163] = {0xFEBD3434U, 0x00000002U}, /* SEC_MODID[163]:FCPVD0*/ + [164] = {0xFEBD343CU, 0x00000002U}, /* SEC_MODID[164]:VSPD0*/ + [165] = {0xE6583400U, 0x00000002U}, /* SEC_MODID[165]:CKMHSC*/ + [166] = {0xE6583404U, 0x00000002U}, /* SEC_MODID[166]:AXIPCI001*/ + [167] = {0xE6583408U, 0x00000002U}, /* SEC_MODID[167]:AXIPCI002*/ + [168] = {0xE658340CU, 0x00000002U}, /* SEC_MODID[168]:AXIPCI003*/ + [169] = {0xE6583414U, 0x00000002U}, /* SEC_MODID[169]:AXIPCI005*/ + [170] = {0xE6583418U, 0x00000002U}, /* SEC_MODID[170]:AXIPCI006*/ + [171] = {0xE658341CU, 0x00000002U}, /* SEC_MODID[171]:AXIPCI007*/ + [172] = {0xE6583420U, 0x00000002U}, /* SEC_MODID[172]:AXIPCI008*/ + [173] = {0xE6583424U, 0x00000002U}, /* SEC_MODID[173]:AXIPCI009*/ + [174] = {0xE6583428U, 0x00000002U}, /* SEC_MODID[174]:AXIPCI010*/ + [175] = {0xE658342CU, 0x00000002U}, /* SEC_MODID[175]:AXIPCI011*/ + [176] = {0xE6583430U, 0x00000002U}, /* SEC_MODID[176]:AXIPCI012*/ + [177] = {0xE6583434U, 0x00000002U}, /* SEC_MODID[177]:AXIPCI013*/ + [178] = {0xE6583438U, 0x00000002U}, /* SEC_MODID[178]:AXIPCI014*/ + [179] = {0xE658343CU, 0x00000002U}, /* SEC_MODID[179]:AXIPCI015*/ + [180] = {0xE6583484U, 0x00000002U}, /* SEC_MODID[180]:GPTP*/ + [181] = {0xE6583488U, 0x00000002U}, /* SEC_MODID[181]:IPMMUHC00*/ + [182] = {0xE65834F4U, 0x00000002U}, /* SEC_MODID[182]:AXIPCI000*/ + [183] = {0xE65834F8U, 0x00000002U}, /* SEC_MODID[183]:AXIPCI004*/ + [184] = {0xE65834FCU, 0x00000002U}, /* SEC_MODID[184]:IPMMUHC01*/ + [185] = {0xE6583500U, 0x00000002U}, /* SEC_MODID[185]:AVB0*/ + [186] = {0xE6583504U, 0x00000002U}, /* SEC_MODID[186]:AVB1*/ + [187] = {0xE6583508U, 0x00000002U}, /* SEC_MODID[187]:AVB2*/ + [188] = {0xE658350CU, 0x00000002U}, /* SEC_MODID[188]:IPMMUHC10*/ + [189] = {0xE6583510U, 0x00000002U}, /* SEC_MODID[189]:IPMMUHC11*/ + [190] = {0xE6583514U, 0x00000002U}, /* SEC_MODID[190]:IPMMUHC12*/ + [191] = {0xE6583518U, 0x00000002U}, /* SEC_MODID[191]:IPMMUHC13*/ + [192] = {0xE658351CU, 0x00000002U}, /* SEC_MODID[192]:PPHY0*/ + [193] = {0xE6583524U, 0x00000002U}, /* SEC_MODID[193]:IPMMUHC14*/ + [194] = {0xE6583528U, 0x00000002U}, /* SEC_MODID[194]:IPMMUHC15*/ + [195] = {0xE658352CU, 0x00000002U}, /* SEC_MODID[195]:FBAHSC*/ + [196] = {0xE6583530U, 0x00000002U}, /* SEC_MODID[196]:IPMMUHC02*/ + [197] = {0xE6583538U, 0x00000002U}, /* SEC_MODID[197]:ECMHSC*/ + [198] = {0xE658353CU, 0x00000002U}, /* SEC_MODID[198]:ARHC0*/ + [199] = {0xE6583540U, 0x00000002U}, /* SEC_MODID[199]:ARHC1*/ + [200] = {0xE6583544U, 0x00000002U}, /* SEC_MODID[200]:ARHC2*/ + [201] = {0xE6583548U, 0x00000002U}, /* SEC_MODID[201]:ARHC3*/ + [202] = {0xE658354CU, 0x00000002U}, /* SEC_MODID[202]:ARHC4*/ + [203] = {0xE6583550U, 0x00000002U}, /* SEC_MODID[203]:ARHC5*/ + [204] = {0xE6583554U, 0x00000002U}, /* SEC_MODID[204]:ARHC6*/ + [205] = {0xE6583558U, 0x00000002U}, /* SEC_MODID[205]:ARHC7*/ + [206] = {0xE658355CU, 0x00000002U}, /* SEC_MODID[206]:ARHC8*/ + [207] = {0xE6583560U, 0x00000002U}, /* SEC_MODID[207]:IPMMUHC03*/ + [208] = {0xE6583564U, 0x00000002U}, /* SEC_MODID[208]:IPMMUHC04*/ + [209] = {0xE6583568U, 0x00000002U}, /* SEC_MODID[209]:IPMMUHC05*/ + [210] = {0xE658356CU, 0x00000002U}, /* SEC_MODID[210]:IPMMUHC06*/ + [211] = {0xE6583570U, 0x00000002U}, /* SEC_MODID[211]:IPMMUHC07*/ + [212] = {0xE6583574U, 0x00000002U}, /* SEC_MODID[212]:IPMMUHC08*/ + [213] = {0xE6583578U, 0x00000002U}, /* SEC_MODID[213]:IPMMUHC09*/ + [214] = {0xFF883400U, 0x00000002U}, /* SEC_MODID[214]:ARIMP00*/ + [215] = {0xFF883404U, 0x00000002U}, /* SEC_MODID[215]:ARIMP01*/ + [216] = {0xFF883408U, 0x00000002U}, /* SEC_MODID[216]:ARIMP02*/ + [217] = {0xFF88340CU, 0x00000002U}, /* SEC_MODID[217]:ARIMP03*/ + [218] = {0xFF883410U, 0x00000002U}, /* SEC_MODID[218]:ARIMP04*/ + [219] = {0xFF883414U, 0x00000002U}, /* SEC_MODID[219]:AXIFBABUSIR0*/ + [220] = {0xFF883418U, 0x00000002U}, /* SEC_MODID[220]:AXIFBABUSIR1*/ + [221] = {0xFF88341CU, 0x00000002U}, /* SEC_MODID[221]:AXIFBABUSIR2*/ + [222] = {0xFF883420U, 0x00000002U}, /* SEC_MODID[222]:AXIFBABUSIR3*/ + [223] = {0xFF883428U, 0x00000002U}, /* SEC_MODID[223]:AXIIMP0*/ + [224] = {0xFF883434U, 0x00000002U}, /* SEC_MODID[224]:ARIMP05*/ + [225] = {0xFF883438U, 0x00000002U}, /* SEC_MODID[225]:ARIMP06*/ + [226] = {0xFF88343CU, 0x00000002U}, /* SEC_MODID[226]:ARIMP07*/ + [227] = {0xFF883440U, 0x00000002U}, /* SEC_MODID[227]:ARIMP08*/ + [228] = {0xFF883448U, 0x00000002U}, /* SEC_MODID[228]:ECMIR*/ + [229] = {0xFF88344CU, 0x00000002U}, /* SEC_MODID[229]:DSPPS*/ + [230] = {0xFF883450U, 0x00000002U}, /* SEC_MODID[230]:IPMMUIR1*/ + [231] = {0xFF883454U, 0x00000002U}, /* SEC_MODID[231]:IPMMUIR0*/ + [232] = {0xFF883458U, 0x00000002U}, /* SEC_MODID[232]:IPMMUIR10*/ + [233] = {0xFF88345CU, 0x00000002U}, /* SEC_MODID[233]:IPMMUIR11*/ + [234] = {0xFF883460U, 0x00000002U}, /* SEC_MODID[234]:IPMMUIR12*/ + [235] = {0xFF883464U, 0x00000002U}, /* SEC_MODID[235]:IPMMUIR13*/ + [236] = {0xFF883468U, 0x00000002U}, /* SEC_MODID[236]:IPMMUIR14*/ + [237] = {0xFF88346CU, 0x00000002U}, /* SEC_MODID[237]:IPMMUIR15*/ + [238] = {0xFF883470U, 0x00000002U}, /* SEC_MODID[238]:IPMMUIR2*/ + [239] = {0xFF883474U, 0x00000002U}, /* SEC_MODID[239]:IPMMUIR3*/ + [240] = {0xFF883478U, 0x00000002U}, /* SEC_MODID[240]:IPMMUIR4*/ + [241] = {0xFF88347CU, 0x00000002U}, /* SEC_MODID[241]:IPMMUIR5*/ + [242] = {0xFF883480U, 0x00000002U}, /* SEC_MODID[242]:IPMMUIR6*/ + [243] = {0xFF883484U, 0x00000002U}, /* SEC_MODID[243]:IPMMUIR7*/ + [244] = {0xFF883488U, 0x00000002U}, /* SEC_MODID[244]:IPMMUIR8*/ + [245] = {0xFF88348CU, 0x00000002U}, /* SEC_MODID[245]:IPMMUIR9*/ + [246] = {0xFD813400U, 0x00000002U}, /* SEC_MODID[246]:ARPV0*/ + [247] = {0xFD813404U, 0x00000002U}, /* SEC_MODID[247]:ARPV1*/ + [248] = {0xFD813408U, 0x00000002U}, /* SEC_MODID[248]:AXIRGXS*/ + [249] = {0xFD81340CU, 0x00000002U}, /* SEC_MODID[249]:ARPV2*/ + [250] = {0xFD813410U, 0x00000002U}, /* SEC_MODID[250]:ARPV3*/ + [251] = {0xFD813414U, 0x00000002U}, /* SEC_MODID[251]:ARPV4*/ + [252] = {0xFD813418U, 0x00000002U}, /* SEC_MODID[252]:ARPV5*/ + [253] = {0xFD81341CU, 0x00000002U}, /* SEC_MODID[253]:ARPV6*/ + [254] = {0xFD813420U, 0x00000002U}, /* SEC_MODID[254]:ARPV7*/ + [255] = {0xFD813424U, 0x00000002U}, /* SEC_MODID[255]:ARPV8*/ + [256] = {0xFD81342CU, 0x00000002U}, /* SEC_MODID[256]:ECM3DG*/ + [257] = {0xFD813430U, 0x00000002U}, /* SEC_MODID[257]:FBAPVC*/ + [258] = {0xFD813434U, 0x00000002U}, /* SEC_MODID[258]:FBAPVD0*/ + [259] = {0xFD813438U, 0x00000002U}, /* SEC_MODID[259]:FBAPVD1*/ + [260] = {0xFD81343CU, 0x00000002U}, /* SEC_MODID[260]:FBAPVD2*/ + [261] = {0xFD813440U, 0x00000002U}, /* SEC_MODID[261]:FBAPVE*/ + [262] = {0xFD813444U, 0x00000002U}, /* SEC_MODID[262]:IPMMUPV000*/ + [263] = {0xFD813448U, 0x00000002U}, /* SEC_MODID[263]:IPMMUPV001*/ + [264] = {0xFD81344CU, 0x00000002U}, /* SEC_MODID[264]:IPMMUPV010*/ + [265] = {0xFD813450U, 0x00000002U}, /* SEC_MODID[265]:IPMMUPV011*/ + [266] = {0xFD813454U, 0x00000002U}, /* SEC_MODID[266]:IPMMUPV012*/ + [267] = {0xFD813458U, 0x00000002U}, /* SEC_MODID[267]:IPMMUPV013*/ + [268] = {0xFD81345CU, 0x00000002U}, /* SEC_MODID[268]:IPMMUPV014*/ + [269] = {0xFD813460U, 0x00000002U}, /* SEC_MODID[269]:IPMMUPV015*/ + [270] = {0xFD813464U, 0x00000002U}, /* SEC_MODID[270]:IPMMUPV002*/ + [271] = {0xFD813468U, 0x00000002U}, /* SEC_MODID[271]:IPMMUPV003*/ + [272] = {0xFD81346CU, 0x00000002U}, /* SEC_MODID[272]:IPMMUPV004*/ + [273] = {0xFD813470U, 0x00000002U}, /* SEC_MODID[273]:IPMMUPV005*/ + [274] = {0xFD813474U, 0x00000002U}, /* SEC_MODID[274]:IPMMUPV006*/ + [275] = {0xFD813478U, 0x00000002U}, /* SEC_MODID[275]:IPMMUPV007*/ + [276] = {0xFD81347CU, 0x00000002U}, /* SEC_MODID[276]:IPMMUPV008*/ + [277] = {0xFD813480U, 0x00000002U}, /* SEC_MODID[277]:IPMMUPV009*/ + [278] = {0xE6623400U, 0x00000002U}, /* SEC_MODID[278]:ARRC0*/ + [279] = {0xE6623404U, 0x00000002U}, /* SEC_MODID[279]:ARRC1*/ + [280] = {0xE6623408U, 0x00000002U}, /* SEC_MODID[280]:ARRC2*/ + [281] = {0xE662340CU, 0x00000002U}, /* SEC_MODID[281]:ARRC3*/ + [282] = {0xE6623410U, 0x00000002U}, /* SEC_MODID[282]:ARRC4*/ + [283] = {0xE6623414U, 0x00000002U}, /* SEC_MODID[283]:ARRC5*/ + [284] = {0xE6623418U, 0x00000002U}, /* SEC_MODID[284]:ARRC6*/ + [285] = {0xE662341CU, 0x00000002U}, /* SEC_MODID[285]:ARRC7*/ + [286] = {0xE6623420U, 0x00000002U}, /* SEC_MODID[286]:ARRC8*/ + [287] = {0xE6623428U, 0x00000002U}, /* SEC_MODID[287]:ICUMX*/ + [288] = {0xE662342CU, 0x00000002U}, /* SEC_MODID[288]:ECMRC*/ + [289] = {0xFFC33400U, 0x00000002U}, /* SEC_MODID[289]:DMAWCRC0*/ + [290] = {0xFFC33404U, 0x00000002U}, /* SEC_MODID[290]:DMAWCRC1*/ + [291] = {0xFFC33408U, 0x00000002U}, /* SEC_MODID[291]:DMAWCRC2*/ + [292] = {0xFFC3340CU, 0x00000002U}, /* SEC_MODID[292]:DMAWCRC3*/ + [293] = {0xFFC43400U, 0x00000002U}, /* SEC_MODID[293]:ARMREG00*/ + [294] = {0xFFC43404U, 0x00000002U}, /* SEC_MODID[294]:ARMREG01*/ + [295] = {0xFFC43408U, 0x00000002U}, /* SEC_MODID[295]:ARMREG10*/ + [296] = {0xFFC4340CU, 0x00000002U}, /* SEC_MODID[296]:ARMREG11*/ + [297] = {0xFFC43410U, 0x00000002U}, /* SEC_MODID[297]:ARMREG12*/ + [298] = {0xFFC43414U, 0x00000000U}, /* SEC_MODID[298]:ARMREG13*/ + [299] = {0xFFC43418U, 0x00000000U}, /* SEC_MODID[299]:ARMREG14*/ + [300] = {0xFFC4341CU, 0x00000002U}, /* SEC_MODID[300]:AXICR52SS0*/ + [301] = {0xFFC43420U, 0x00000002U}, /* SEC_MODID[301]:AXICSD0*/ + [302] = {0xFFC43424U, 0x00000002U}, /* SEC_MODID[302]:AXIINTAP0*/ + [303] = {0xFFC4342CU, 0x00000002U}, /* SEC_MODID[303]:AXISECROM*/ + [304] = {0xFFC43430U, 0x00000002U}, /* SEC_MODID[304]:AXISYSRAM0*/ + [305] = {0xFFC43434U, 0x00000002U}, /* SEC_MODID[305]:AXISYSRAM1*/ + [306] = {0xFFC43438U, 0x00000002U}, /* SEC_MODID[306]:ARGREG15*/ + [307] = {0xFFC4343CU, 0x00000002U}, /* SEC_MODID[307]:ARMREG2*/ + [308] = {0xFFC43440U, 0x00000002U}, /* SEC_MODID[308]:ARMREG3*/ + [309] = {0xFFC43444U, 0x00000002U}, /* SEC_MODID[309]:ARMREG4*/ + [310] = {0xFFC43448U, 0x00000002U}, /* SEC_MODID[310]:ARMREG5*/ + [311] = {0xFFC4344CU, 0x00000002U}, /* SEC_MODID[311]:ARMREG6*/ + [312] = {0xFFC43450U, 0x00000002U}, /* SEC_MODID[312]:ARMREG7*/ + [313] = {0xFFC43454U, 0x00000000U}, /* SEC_MODID[313]:ARMREG8*/ + [314] = {0xFFC43458U, 0x00000000U}, /* SEC_MODID[314]:ARMREG9*/ + [315] = {0xFFC4345CU, 0x00000002U}, /* SEC_MODID[315]:ARRD0*/ + [316] = {0xFFC43460U, 0x00000002U}, /* SEC_MODID[316]:ARRD1*/ + [317] = {0xFFC43464U, 0x00000002U}, /* SEC_MODID[317]:ARRD2*/ + [318] = {0xFFC43468U, 0x00000002U}, /* SEC_MODID[318]:ARRD3*/ + [319] = {0xFFC4346CU, 0x00000002U}, /* SEC_MODID[319]:ARRD4*/ + [320] = {0xFFC43470U, 0x00000002U}, /* SEC_MODID[320]:ARRD5*/ + [321] = {0xFFC43474U, 0x00000002U}, /* SEC_MODID[321]:ARRD6*/ + [322] = {0xFFC43478U, 0x00000002U}, /* SEC_MODID[322]:ARRD7*/ + [323] = {0xFFC4347CU, 0x00000002U}, /* SEC_MODID[323]:ARRD8*/ + [324] = {0xFFC43480U, 0x00000002U}, /* SEC_MODID[324]:ARRT0*/ + [325] = {0xFFC43484U, 0x00000002U}, /* SEC_MODID[325]:ARRT1*/ + [326] = {0xFFC43488U, 0x00000002U}, /* SEC_MODID[326]:ARRT2*/ + [327] = {0xFFC4348CU, 0x00000002U}, /* SEC_MODID[327]:ARRT3*/ + [328] = {0xFFC43490U, 0x00000002U}, /* SEC_MODID[328]:ARRT4*/ + [329] = {0xFFC43494U, 0x00000002U}, /* SEC_MODID[329]:ARRT5*/ + [330] = {0xFFC43498U, 0x00000002U}, /* SEC_MODID[330]:ARRT6*/ + [331] = {0xFFC4349CU, 0x00000002U}, /* SEC_MODID[331]:ARRT7*/ + [332] = {0xFFC434A0U, 0x00000002U}, /* SEC_MODID[332]:ARRT8*/ + [333] = {0xFFC434A4U, 0x00000002U}, /* SEC_MODID[333]:CKMRT*/ + [334] = {0xFFC434A8U, 0x00000002U}, /* SEC_MODID[334]:CRC0*/ + [335] = {0xFFC434ACU, 0x00000002U}, /* SEC_MODID[335]:CRC1*/ + [336] = {0xFFC434B0U, 0x00000002U}, /* SEC_MODID[336]:CRC2*/ + [337] = {0xFFC434B4U, 0x00000002U}, /* SEC_MODID[337]:CRC3*/ + [338] = {0xFFC434B8U, 0x00000002U}, /* SEC_MODID[338]:CSD*/ + [339] = {0xFFC434BCU, 0x00000002U}, /* SEC_MODID[339]:ECM*/ + [340] = {0xFFC434C0U, 0x00000002U}, /* SEC_MODID[340]:ECMRT*/ + [341] = {0xFFC434C4U, 0x00000002U}, /* SEC_MODID[341]:FBACR52*/ + [342] = {0xFFC434C8U, 0x00000002U}, /* SEC_MODID[342]:FBART*/ + [343] = {0xFFC434CCU, 0x00000002U}, /* SEC_MODID[343]:INTTP*/ + [344] = {0xFFC434D0U, 0x00000002U}, /* SEC_MODID[344]:IPMMURT000*/ + [345] = {0xFFC434D4U, 0x00000002U}, /* SEC_MODID[345]:IPMMURT100*/ + [346] = {0xFFC434D8U, 0x00000002U}, /* SEC_MODID[346]:KCRC4*/ + [347] = {0xFFC434DCU, 0x00000002U}, /* SEC_MODID[347]:KCRC5*/ + [348] = {0xFFC434E0U, 0x00000002U}, /* SEC_MODID[348]:KCRC6*/ + [349] = {0xFFC434E4U, 0x00000002U}, /* SEC_MODID[349]:KCRC7*/ + [350] = {0xFFC434E8U, 0x00000002U}, /* SEC_MODID[350]:MFI00*/ + [351] = {0xFFC434ECU, 0x00000002U}, /* SEC_MODID[351]:MFI01*/ + [352] = {0xFFC434F0U, 0x00000002U}, /* SEC_MODID[352]:MFI10*/ + [353] = {0xFFC434F4U, 0x00000002U}, /* SEC_MODID[353]:MFI02*/ + [354] = {0xFFC434F8U, 0x00000002U}, /* SEC_MODID[354]:MFI03*/ + [355] = {0xFFC434FCU, 0x00000002U}, /* SEC_MODID[355]:MFI04*/ + [356] = {0xFFC43500U, 0x00000002U}, /* SEC_MODID[356]:MFI05*/ + [357] = {0xFFC43504U, 0x00000002U}, /* SEC_MODID[357]:MFI06*/ + [358] = {0xFFC43508U, 0x00000002U}, /* SEC_MODID[358]:MFI07*/ + [359] = {0xFFC4350CU, 0x00000002U}, /* SEC_MODID[359]:MFI08*/ + [360] = {0xFFC43510U, 0x00000002U}, /* SEC_MODID[360]:MFI09*/ + [361] = {0xFFC43514U, 0x00000002U}, /* SEC_MODID[361]:MFI15*/ + [362] = {0xFFC43518U, 0x00000002U}, /* SEC_MODID[362]:CKMCR52*/ + [363] = {0xFFC4351CU, 0x00000002U}, /* SEC_MODID[363]:RTDM0P*/ + [364] = {0xFFC43520U, 0x00000002U}, /* SEC_MODID[364]:ECMRD*/ + [365] = {0xFFC43524U, 0x00000002U}, /* SEC_MODID[365]:RTDM1P*/ + [366] = {0xFFC43530U, 0x00000002U}, /* SEC_MODID[366]:SYSRAM10*/ + [367] = {0xFFC43538U, 0x00000000U}, /* SEC_MODID[367]:SYSRAM00*/ + [368] = {0xFFC4353CU, 0x00000002U}, /* SEC_MODID[368]:TSIPL0*/ + [369] = {0xFFC43540U, 0x00000002U}, /* SEC_MODID[369]:TSIPL1*/ + [370] = {0xFFC43544U, 0x00000002U}, /* SEC_MODID[370]:TSIPL2*/ + [371] = {0xFFC43548U, 0x00000002U}, /* SEC_MODID[371]:TSIPL3*/ + [372] = {0xFFC4354CU, 0x00000002U}, /* SEC_MODID[372]:TSIPL4*/ + [373] = {0xFFC43550U, 0x00000002U}, /* SEC_MODID[373]:TSIPL5*/ + [374] = {0xFFC43554U, 0x00000002U}, /* SEC_MODID[374]:TSIPL6*/ + [375] = {0xFFC43558U, 0x00000002U}, /* SEC_MODID[375]:TSIPL7*/ + [376] = {0xFFC4355CU, 0x00000002U}, /* SEC_MODID[376]:WCRC0*/ + [377] = {0xFFC43560U, 0x00000002U}, /* SEC_MODID[377]:WCRC1*/ + [378] = {0xFFC43564U, 0x00000002U}, /* SEC_MODID[378]:WCRC2*/ + [379] = {0xFFC43568U, 0x00000002U}, /* SEC_MODID[379]:WCRC3*/ + [380] = {0xFFC43580U, 0x00000002U}, /* SEC_MODID[380]:MFI11*/ + [381] = {0xFFC43584U, 0x00000002U}, /* SEC_MODID[381]:MFI12*/ + [382] = {0xFFC43588U, 0x00000002U}, /* SEC_MODID[382]:MFI13*/ + [383] = {0xFFC4358CU, 0x00000002U}, /* SEC_MODID[383]:MFI14*/ + [384] = {0xFFC43590U, 0x00000002U}, /* SEC_MODID[384]:IPMMURT001*/ + [385] = {0xFFC43594U, 0x00000002U}, /* SEC_MODID[385]:IPMMURT010*/ + [386] = {0xFFC43598U, 0x00000002U}, /* SEC_MODID[386]:IPMMURT011*/ + [387] = {0xFFC4359CU, 0x00000002U}, /* SEC_MODID[387]:IPMMURT012*/ + [388] = {0xFFC435A0U, 0x00000002U}, /* SEC_MODID[388]:IPMMURT013*/ + [389] = {0xFFC435A4U, 0x00000002U}, /* SEC_MODID[389]:IPMMURT014*/ + [390] = {0xFFC435A8U, 0x00000002U}, /* SEC_MODID[390]:IPMMURT015*/ + [391] = {0xFFC435ACU, 0x00000002U}, /* SEC_MODID[391]:IPMMURT002*/ + [392] = {0xFFC435B0U, 0x00000002U}, /* SEC_MODID[392]:IPMMURT003*/ + [393] = {0xFFC435B4U, 0x00000002U}, /* SEC_MODID[393]:IPMMURT004*/ + [394] = {0xFFC435B8U, 0x00000002U}, /* SEC_MODID[394]:IPMMURT005*/ + [395] = {0xFFC435BCU, 0x00000002U}, /* SEC_MODID[395]:IPMMURT006*/ + [396] = {0xFFC435C0U, 0x00000002U}, /* SEC_MODID[396]:IPMMURT007*/ + [397] = {0xFFC435C4U, 0x00000002U}, /* SEC_MODID[397]:IPMMURT008*/ + [398] = {0xFFC435C8U, 0x00000002U}, /* SEC_MODID[398]:IPMMURT009*/ + [399] = {0xFFC435CCU, 0x00000002U}, /* SEC_MODID[399]:IPKMURT101*/ + [400] = {0xFFC435D0U, 0x00000002U}, /* SEC_MODID[400]:IPMMURT110*/ + [401] = {0xFFC435D4U, 0x00000002U}, /* SEC_MODID[401]:IPMMURT111*/ + [402] = {0xFFC435D8U, 0x00000002U}, /* SEC_MODID[402]:IPMMURT112*/ + [403] = {0xFFC435DCU, 0x00000002U}, /* SEC_MODID[403]:IPMMURT113*/ + [404] = {0xFFC435E0U, 0x00000002U}, /* SEC_MODID[404]:IPMMURT114*/ + [405] = {0xFFC435E4U, 0x00000002U}, /* SEC_MODID[405]:IPMMURT115*/ + [406] = {0xFFC435E8U, 0x00000002U}, /* SEC_MODID[406]:IPMMURT102*/ + [407] = {0xFFC435ECU, 0x00000002U}, /* SEC_MODID[407]:IPMMURT103*/ + [408] = {0xFFC435F0U, 0x00000002U}, /* SEC_MODID[408]:IPMMURT104*/ + [409] = {0xFFC435F4U, 0x00000002U}, /* SEC_MODID[409]:IPMMURT105*/ + [410] = {0xFFC435F8U, 0x00000002U}, /* SEC_MODID[410]:IPMMURT106*/ + [411] = {0xFFC435FCU, 0x00000002U}, /* SEC_MODID[411]:IPMMURT107*/ + [412] = {0xFFC43600U, 0x00000002U}, /* SEC_MODID[412]:RTDM000*/ + [413] = {0xFFC43604U, 0x00000002U}, /* SEC_MODID[413]:RTDM001*/ + [414] = {0xFFC43608U, 0x00000002U}, /* SEC_MODID[414]:RTDM010*/ + [415] = {0xFFC4360CU, 0x00000002U}, /* SEC_MODID[415]:RTDM011*/ + [416] = {0xFFC43610U, 0x00000002U}, /* SEC_MODID[416]:RTDM012*/ + [417] = {0xFFC43614U, 0x00000002U}, /* SEC_MODID[417]:RTDM013*/ + [418] = {0xFFC43618U, 0x00000002U}, /* SEC_MODID[418]:RTDM014*/ + [419] = {0xFFC4361CU, 0x00000002U}, /* SEC_MODID[419]:RTDM015*/ + [420] = {0xFFC43620U, 0x00000002U}, /* SEC_MODID[420]:RTDM002*/ + [421] = {0xFFC43624U, 0x00000002U}, /* SEC_MODID[421]:RTDM003*/ + [422] = {0xFFC43628U, 0x00000002U}, /* SEC_MODID[422]:RTDM004*/ + [423] = {0xFFC4362CU, 0x00000002U}, /* SEC_MODID[423]:RTDM005*/ + [424] = {0xFFC43630U, 0x00000002U}, /* SEC_MODID[424]:RTDM006*/ + [425] = {0xFFC43634U, 0x00000002U}, /* SEC_MODID[425]:RTDM007*/ + [426] = {0xFFC43638U, 0x00000002U}, /* SEC_MODID[426]:RTDM008*/ + [427] = {0xFFC4363CU, 0x00000002U}, /* SEC_MODID[427]:RTDM009*/ + [428] = {0xFFC43640U, 0x00000002U}, /* SEC_MODID[428]:RTDM100*/ + [429] = {0xFFC43644U, 0x00000002U}, /* SEC_MODID[429]:RTDM101*/ + [430] = {0xFFC43648U, 0x00000002U}, /* SEC_MODID[430]:RTDM110*/ + [431] = {0xFFC4364CU, 0x00000002U}, /* SEC_MODID[431]:RTDM111*/ + [432] = {0xFFC43650U, 0x00000002U}, /* SEC_MODID[432]:RTDM112*/ + [433] = {0xFFC43654U, 0x00000002U}, /* SEC_MODID[433]:RTDM113*/ + [434] = {0xFFC43658U, 0x00000002U}, /* SEC_MODID[434]:RTDM114*/ + [435] = {0xFFC4365CU, 0x00000002U}, /* SEC_MODID[435]:RTDM115*/ + [436] = {0xFFC43660U, 0x00000002U}, /* SEC_MODID[436]:RTDM102*/ + [437] = {0xFFC43664U, 0x00000002U}, /* SEC_MODID[437]:RTDM103*/ + [438] = {0xFFC43668U, 0x00000002U}, /* SEC_MODID[438]:RTDM104*/ + [439] = {0xFFC4366CU, 0x00000002U}, /* SEC_MODID[439]:RTDM105*/ + [440] = {0xFFC43670U, 0x00000002U}, /* SEC_MODID[440]:RTDM106*/ + [441] = {0xFFC43674U, 0x00000002U}, /* SEC_MODID[441]:RTDM107*/ + [442] = {0xFFC43678U, 0x00000002U}, /* SEC_MODID[442]:RTDM108*/ + [443] = {0xFFC4367CU, 0x00000002U}, /* SEC_MODID[443]:RTDM109*/ + [444] = {0xFFC43700U, 0x00000002U}, /* SEC_MODID[444]:IPMMURT108*/ + [445] = {0xFFC43704U, 0x00000002U}, /* SEC_MODID[445]:IPMMURT109*/ + [446] = {0xFFC43708U, 0x00000000U}, /* SEC_MODID[446]:SYSRAM01*/ + [447] = {0xFFC4370CU, 0x00000002U}, /* SEC_MODID[447]:SYSRAM02*/ + [448] = {0xFFC43710U, 0x00000000U}, /* SEC_MODID[448]:SYSRAM03*/ + [449] = {0xFFC43714U, 0x00000000U}, /* SEC_MODID[449]:SYSRAM04*/ + [450] = {0xFFC43718U, 0x00000000U}, /* SEC_MODID[450]:SYSRAM05*/ + [451] = {0xFFC4371CU, 0x00000000U}, /* SEC_MODID[451]:SYSRAM06*/ + [452] = {0xFFC43720U, 0x00000002U}, /* SEC_MODID[452]:SYSRAM07*/ + [453] = {0xFFC43724U, 0x00000002U}, /* SEC_MODID[453]:SYSRAM11*/ + [454] = {0xFFC43728U, 0x00000002U}, /* SEC_MODID[454]:SYSRAM12*/ + [455] = {0xFFC4372CU, 0x00000002U}, /* SEC_MODID[455]:SYSRAM13*/ + [456] = {0xFFC43730U, 0x00000002U}, /* SEC_MODID[456]:SYSRAM14*/ + [457] = {0xFFC43734U, 0x00000002U}, /* SEC_MODID[457]:SYSRAM15*/ + [458] = {0xFFC43738U, 0x00000002U}, /* SEC_MODID[458]:SYSRAM16*/ + [459] = {0xFFC4373CU, 0x00000002U}, /* SEC_MODID[459]:SYSRAM17*/ + [460] = {0xFFC43760U, 0x00000002U}, /* SEC_MODID[460]:BKBUF*/ + [461] = {0xFFC43764U, 0x00000002U}, /* SEC_MODID[461]:AXICR52SS1*/ + [462] = {0xFFC43768U, 0x00000002U}, /* SEC_MODID[462]:AXICR52SS2*/ + [463] = {0xFF863400U, 0x00000002U}, /* SEC_MODID[463]:ARSC0*/ + [464] = {0xFF863404U, 0x00000002U}, /* SEC_MODID[464]:ARSC1*/ + [465] = {0xFF863408U, 0x00000002U}, /* SEC_MODID[465]:ARSC2*/ + [466] = {0xFF86340CU, 0x00000002U}, /* SEC_MODID[466]:ARSC3*/ + [467] = {0xFF863410U, 0x00000002U}, /* SEC_MODID[467]:ARSC4*/ + [468] = {0xFF863414U, 0x00000002U}, /* SEC_MODID[468]:ARSC5*/ + [469] = {0xFF863418U, 0x00000002U}, /* SEC_MODID[469]:ARSC6*/ + [470] = {0xFF86341CU, 0x00000002U}, /* SEC_MODID[470]:ARSC7*/ + [471] = {0xFF863420U, 0x00000002U}, /* SEC_MODID[471]:ARSC8*/ + [472] = {0xFF863424U, 0x00000002U}, /* SEC_MODID[472]:ARSTM0*/ + [473] = {0xFF863428U, 0x00000002U}, /* SEC_MODID[473]:ARSTM1*/ + [474] = {0xFF86342CU, 0x00000002U}, /* SEC_MODID[474]:CSD1S*/ + [475] = {0xFF863430U, 0x00000002U}, /* SEC_MODID[475]:AXIFBABUSTOP0*/ + [476] = {0xFF863438U, 0x00000002U}, /* SEC_MODID[476]:ARSTM2*/ + [477] = {0xFF86343CU, 0x00000002U}, /* SEC_MODID[477]:ARSTM3*/ + [478] = {0xFF863440U, 0x00000002U}, /* SEC_MODID[478]:ARSTM4*/ + [479] = {0xFF863444U, 0x00000002U}, /* SEC_MODID[479]:ARSTM5*/ + [480] = {0xFF863448U, 0x00000002U}, /* SEC_MODID[480]:ARSTM6*/ + [481] = {0xFF86344CU, 0x00000002U}, /* SEC_MODID[481]:ARSTM7*/ + [482] = {0xFF863450U, 0x00000002U}, /* SEC_MODID[482]:ARSTM8*/ + [483] = {0xFF863454U, 0x00000002U}, /* SEC_MODID[483]:ECMTOP*/ + [484] = {0xFF863458U, 0x00000002U}, /* SEC_MODID[484]:FBA*/ + [485] = {0xFF86345CU, 0x00000002U}, /* SEC_MODID[485]:FBC*/ + [486] = {0xFF863434U, 0x00000002U}, /* SEC_MODID[486]:AXICCI00*/ + [487] = {0xFF863460U, 0x00000002U}, /* SEC_MODID[487]:AXICCI01*/ + [488] = {0xFF863464U, 0x00000002U}, /* SEC_MODID[488]:AXICCI10*/ + [489] = {0xFF863468U, 0x00000002U}, /* SEC_MODID[489]:AXICCI11*/ + [490] = {0xFF86346CU, 0x00000002U}, /* SEC_MODID[490]:AXICCI12*/ + [491] = {0xFF863470U, 0x00000002U}, /* SEC_MODID[491]:AXICCI13*/ + [492] = {0xFF863474U, 0x00000002U}, /* SEC_MODID[492]:AXICCI14*/ + [493] = {0xFF863478U, 0x00000002U}, /* SEC_MODID[493]:AXICCI15*/ + [494] = {0xFF86347CU, 0x00000002U}, /* SEC_MODID[494]:AXICCI2*/ + [495] = {0xFF863480U, 0x00000002U}, /* SEC_MODID[495]:AXICCI3*/ + [496] = {0xFF863484U, 0x00000002U}, /* SEC_MODID[496]:AXICCI4*/ + [497] = {0xFF863488U, 0x00000002U}, /* SEC_MODID[497]:AXICCI5*/ + [498] = {0xFF86348CU, 0x00000002U}, /* SEC_MODID[498]:AXICCI6*/ + [499] = {0xFF863490U, 0x00000002U}, /* SEC_MODID[499]:AXICCI7*/ + [500] = {0xFF863494U, 0x00000002U}, /* SEC_MODID[500]:AXICCI8*/ + [501] = {0xFF863498U, 0x00000002U}, /* SEC_MODID[501]:AXICCI9*/ + [502] = {0xFF8634A0U, 0x00000002U}, /* SEC_MODID[502]:ECMSTM*/ + [503] = {0xE7783400U, 0x00000002U}, /* SEC_MODID[503]:DMASSI00*/ + [504] = {0xE7783404U, 0x00000002U}, /* SEC_MODID[504]:DMASSI01*/ + [505] = {0xE7783408U, 0x00000002U}, /* SEC_MODID[505]:DMASSI02*/ + [506] = {0xE778340CU, 0x00000002U}, /* SEC_MODID[506]:DMASSI03*/ + [507] = {0xE7783410U, 0x00000002U}, /* SEC_MODID[507]:DMASSI04*/ + [508] = {0xE7783414U, 0x00000002U}, /* SEC_MODID[508]:DMAI2C0*/ + [509] = {0xE7783418U, 0x00000002U}, /* SEC_MODID[509]:DMAI2C1*/ + [510] = {0xE778341CU, 0x00000002U}, /* SEC_MODID[510]:DMAI2C2*/ + [511] = {0xE7783420U, 0x00000002U}, /* SEC_MODID[511]:DMAI2C3*/ + [512] = {0xE778342CU, 0x00000002U}, /* SEC_MODID[512]:DMASSI05*/ + [513] = {0xE7783430U, 0x00000002U}, /* SEC_MODID[513]:DMASSI06*/ + [514] = {0xE7783434U, 0x00000002U}, /* SEC_MODID[514]:DMASSI07*/ + [515] = {0xE67C3400U, 0x00000002U}, /* SEC_MODID[515]:ARMM*/ + [516] = {0xE67C3404U, 0x00000002U}, /* SEC_MODID[516]:AXIARNMM*/ + [517] = {0xE67C3408U, 0x00000002U}, /* SEC_MODID[517]:ARSM0*/ + [518] = {0xE67C340CU, 0x00000002U}, /* SEC_MODID[518]:ARSM1*/ + [519] = {0xE67C3410U, 0x00000002U}, /* SEC_MODID[519]:ARSM2*/ + [520] = {0xE67C3414U, 0x00000002U}, /* SEC_MODID[520]:AXIQOS0*/ + [521] = {0xE67C3418U, 0x00000002U}, /* SEC_MODID[521]:AXIQOS1*/ + [522] = {0xE67C341CU, 0x00000002U}, /* SEC_MODID[522]:AXIQOS2*/ + [523] = {0xE67C3420U, 0x00000002U}, /* SEC_MODID[523]:AXIQOS3*/ + [524] = {0xE67C3424U, 0x00000002U}, /* SEC_MODID[524]:AXIQOS4*/ + [525] = {0xE67C3428U, 0x00000002U}, /* SEC_MODID[525]:AXIQOS5*/ + [526] = {0xE67C3434U, 0x00000002U}, /* SEC_MODID[526]:ARSM3*/ + [527] = {0xE67C3438U, 0x00000002U}, /* SEC_MODID[527]:ARSM4*/ + [528] = {0xE67C343CU, 0x00000002U}, /* SEC_MODID[528]:ARSM5*/ + [529] = {0xE67C3440U, 0x00000002U}, /* SEC_MODID[529]:ARSM6*/ + [530] = {0xE67C3444U, 0x00000002U}, /* SEC_MODID[530]:ARSM7*/ + [531] = {0xE67C3448U, 0x00000002U}, /* SEC_MODID[531]:ARSM8*/ + [532] = {0xE67C344CU, 0x00000000U}, /* SEC_MODID[532]:AXMM0*/ + [533] = {0xE67C3450U, 0x00000000U}, /* SEC_MODID[533]:AXMM1*/ + [534] = {0xE67C3454U, 0x00000002U}, /* SEC_MODID[534]:AXMMPMON*/ + [535] = {0xE67C3458U, 0x00000002U}, /* SEC_MODID[535]:CKMMM*/ + [536] = {0xE67C345CU, 0x00000002U}, /* SEC_MODID[536]:ECMMM*/ + [537] = {0xE67C3460U, 0x00000002U}, /* SEC_MODID[537]:FBADBSC0*/ + [538] = {0xE67C3468U, 0x00000002U}, /* SEC_MODID[538]:FBAMM*/ + [539] = {0xE67C346CU, 0x00000002U}, /* SEC_MODID[539]:IPMMUMM00*/ + [540] = {0xE67C3470U, 0x00000002U}, /* SEC_MODID[540]:DBS0A0*/ + [541] = {0xE67C3474U, 0x00000002U}, /* SEC_MODID[541]:DBS0A1*/ + [542] = {0xE67C3484U, 0x00000002U}, /* SEC_MODID[542]:FCPRC*/ + [543] = {0xE67C3488U, 0x00000002U}, /* SEC_MODID[543]:DBS0D0*/ + [544] = {0xE67C348CU, 0x00000002U}, /* SEC_MODID[544]:DBS0D1*/ + [545] = {0xE67C3498U, 0x00000002U}, /* SEC_MODID[545]:FBADDR*/ + [546] = {0xE67C349CU, 0x00000002U}, /* SEC_MODID[546]:IPMMUMM01*/ + [547] = {0xE67C34A0U, 0x00000002U}, /* SEC_MODID[547]:IPMMUMM10*/ + [548] = {0xE67C34A4U, 0x00000002U}, /* SEC_MODID[548]:IPMMUMM11*/ + [549] = {0xE67C34A8U, 0x00000002U}, /* SEC_MODID[549]:IPMMUMM12*/ + [550] = {0xE67C34ACU, 0x00000002U}, /* SEC_MODID[550]:IPMMUMM13*/ + [551] = {0xE67C34B0U, 0x00000002U}, /* SEC_MODID[551]:IPMMUMM14*/ + [552] = {0xE67C34B4U, 0x00000002U}, /* SEC_MODID[552]:IPMMUMM15*/ + [553] = {0xE67C34B8U, 0x00000002U}, /* SEC_MODID[553]:IPMMUMM02*/ + [554] = {0xE67C34BCU, 0x00000002U}, /* SEC_MODID[554]:IPMMUMM03*/ + [555] = {0xE67C34C0U, 0x00000002U}, /* SEC_MODID[555]:IPMMUMM04*/ + [556] = {0xE67C34C4U, 0x00000002U}, /* SEC_MODID[556]:IPMMUMM05*/ + [557] = {0xE67C34C8U, 0x00000002U}, /* SEC_MODID[557]:IPMMUMM06*/ + [558] = {0xE67C34CCU, 0x00000002U}, /* SEC_MODID[558]:IPMMUMM07*/ + [559] = {0xE67C34D0U, 0x00000002U}, /* SEC_MODID[559]:IPMMUMM08*/ + [560] = {0xE67C34D4U, 0x00000002U}, /* SEC_MODID[560]:IPMMUMM09*/ + [561] = {0xFF803400U, 0x00000002U}, /* SEC_MODID[561]:ARSN0*/ + [562] = {0xFF803404U, 0x00000002U}, /* SEC_MODID[562]:ARSN1*/ + [563] = {0xFF803408U, 0x00000002U}, /* SEC_MODID[563]:ARSN2*/ + [564] = {0xFF80340CU, 0x00000002U}, /* SEC_MODID[564]:ARSN3*/ + [565] = {0xFF803410U, 0x00000002U}, /* SEC_MODID[565]:ARSN4*/ + [566] = {0xFF803414U, 0x00000002U}, /* SEC_MODID[566]:ARSN5*/ + [567] = {0xFF803418U, 0x00000002U}, /* SEC_MODID[567]:ARSN6*/ + [568] = {0xFF80341CU, 0x00000002U}, /* SEC_MODID[568]:ARSN7*/ + [569] = {0xFF803420U, 0x00000002U}, /* SEC_MODID[569]:ARSN8*/ + [570] = {0xFF803424U, 0x00000002U}, /* SEC_MODID[570]:ECMTOP3*/ + [571] = {0xE7753400U, 0x00000002U}, /* SEC_MODID[571]:ARSD00*/ + [572] = {0xE7753404U, 0x00000002U}, /* SEC_MODID[572]:ARSD01*/ + [573] = {0xE7753408U, 0x00000002U}, /* SEC_MODID[573]:ARSD02*/ + [574] = {0xE775340CU, 0x00000002U}, /* SEC_MODID[574]:ARSD03*/ + [575] = {0xE7753410U, 0x00000002U}, /* SEC_MODID[575]:ARSD04*/ + [576] = {0xE7753414U, 0x00000002U}, /* SEC_MODID[576]:ARSD05*/ + [577] = {0xE7753418U, 0x00000002U}, /* SEC_MODID[577]:ARSD06*/ + [578] = {0xE775341CU, 0x00000002U}, /* SEC_MODID[578]:AXIFRAY*/ + [579] = {0xE7753428U, 0x00000002U}, /* SEC_MODID[579]:AXIRPC*/ + [580] = {0xE775342CU, 0x00000002U}, /* SEC_MODID[580]:AXISDHI0*/ + [581] = {0xE7753430U, 0x00000002U}, /* SEC_MODID[581]:ARSD07*/ + [582] = {0xE7753434U, 0x00000002U}, /* SEC_MODID[582]:ARSD08*/ + [583] = {0xE7753438U, 0x00000002U}, /* SEC_MODID[583]:ARSP00*/ + [584] = {0xE775343CU, 0x00000002U}, /* SEC_MODID[584]:ARSP01*/ + [585] = {0xE7753440U, 0x00000002U}, /* SEC_MODID[585]:ARSP02*/ + [586] = {0xE7753444U, 0x00000002U}, /* SEC_MODID[586]:ARSP03*/ + [587] = {0xE7753448U, 0x00000002U}, /* SEC_MODID[587]:ARSP04*/ + [588] = {0xE775344CU, 0x00000002U}, /* SEC_MODID[588]:ARSP05*/ + [589] = {0xE7753450U, 0x00000002U}, /* SEC_MODID[589]:ARSP06*/ + [590] = {0xE7753454U, 0x00000002U}, /* SEC_MODID[590]:ARSP07*/ + [591] = {0xE7753458U, 0x00000002U}, /* SEC_MODID[591]:ARSP08*/ + [592] = {0xE775345CU, 0x00000002U}, /* SEC_MODID[592]:IPMMUDS001*/ + [593] = {0xE7753460U, 0x00000002U}, /* SEC_MODID[593]:CKMPER0*/ + [594] = {0xE7753464U, 0x00000002U}, /* SEC_MODID[594]:ECMPER0*/ + [595] = {0xE7753468U, 0x00000002U}, /* SEC_MODID[595]:FBAPER0*/ + [596] = {0xE775346CU, 0x00000002U}, /* SEC_MODID[596]:FSO0*/ + [597] = {0xE7753470U, 0x00000002U}, /* SEC_MODID[597]:FSO1*/ + [598] = {0xE7753474U, 0x00000002U}, /* SEC_MODID[598]:FSO10*/ + [599] = {0xE7753478U, 0x00000002U}, /* SEC_MODID[599]:FSO2*/ + [600] = {0xE775347CU, 0x00000002U}, /* SEC_MODID[600]:FSO3*/ + [601] = {0xE7753480U, 0x00000002U}, /* SEC_MODID[601]:FSO4*/ + [602] = {0xE7753484U, 0x00000002U}, /* SEC_MODID[602]:FSO5*/ + [603] = {0xE7753488U, 0x00000002U}, /* SEC_MODID[603]:FSO6*/ + [604] = {0xE775348CU, 0x00000002U}, /* SEC_MODID[604]:FSO7*/ + [605] = {0xE7753490U, 0x00000002U}, /* SEC_MODID[605]:FSO8*/ + [606] = {0xE7753494U, 0x00000002U}, /* SEC_MODID[606]:FSO9*/ + [607] = {0xE7753498U, 0x00000002U}, /* SEC_MODID[607]:ADG*/ + [608] = {0xE775349CU, 0x00000002U}, /* SEC_MODID[608]:ECMSD0*/ + [609] = {0xE77534A0U, 0x00000002U}, /* SEC_MODID[609]:IPMMUDS010*/ + [610] = {0xE77534A4U, 0x00000002U}, /* SEC_MODID[610]:IPMMUDS011*/ + [611] = {0xE77534A8U, 0x00000002U}, /* SEC_MODID[611]:I2C0*/ + [612] = {0xE77534ACU, 0x00000002U}, /* SEC_MODID[612]:I2C1*/ + [613] = {0xE77534B0U, 0x00000002U}, /* SEC_MODID[613]:I2C2*/ + [614] = {0xE77534B4U, 0x00000002U}, /* SEC_MODID[614]:I2C3*/ + [615] = {0xE77534C0U, 0x00000002U}, /* SEC_MODID[615]:IPMMUDS012*/ + [616] = {0xE77534C8U, 0x00000002U}, /* SEC_MODID[616]:IPMMUDS000*/ + [617] = {0xE77534CCU, 0x00000002U}, /* SEC_MODID[617]:IPMMUDS013*/ + [618] = {0xE77534D0U, 0x00000002U}, /* SEC_MODID[618]:IPMMUDS014*/ + [619] = {0xE77534D4U, 0x00000002U}, /* SEC_MODID[619]:IPMMUDS015*/ + [620] = {0xE77534D8U, 0x00000002U}, /* SEC_MODID[620]:IPMMUDS002*/ + [621] = {0xE77534DCU, 0x00000002U}, /* SEC_MODID[621]:IPMMUDS003*/ + [622] = {0xE77534E0U, 0x00000002U}, /* SEC_MODID[622]:IPMMUDS004*/ + [623] = {0xE77534E4U, 0x00000002U}, /* SEC_MODID[623]:IPMMUDS005*/ + [624] = {0xE77534E8U, 0x00000002U}, /* SEC_MODID[624]:SSI*/ + [625] = {0xE77534ECU, 0x00000002U}, /* SEC_MODID[625]:IPMMUDS006*/ + [626] = {0xE77534F0U, 0x00000002U}, /* SEC_MODID[626]:IPMMUDS007*/ + [627] = {0xE77534F4U, 0x00000002U}, /* SEC_MODID[627]:SYDM1P*/ + [628] = {0xE77534F8U, 0x00000002U}, /* SEC_MODID[628]:IPMMUDS008*/ + [629] = {0xE77534FCU, 0x00000002U}, /* SEC_MODID[629]:SYDM2P*/ + [630] = {0xE7753500U, 0x00000002U}, /* SEC_MODID[630]:IPMMUDS009*/ + [631] = {0xE7753640U, 0x00000002U}, /* SEC_MODID[631]:SYDM100*/ + [632] = {0xE7753644U, 0x00000002U}, /* SEC_MODID[632]:SYDM101*/ + [633] = {0xE7753648U, 0x00000002U}, /* SEC_MODID[633]:SYDM110*/ + [634] = {0xE775364CU, 0x00000002U}, /* SEC_MODID[634]:SYDM111*/ + [635] = {0xE7753650U, 0x00000002U}, /* SEC_MODID[635]:SYDM112*/ + [636] = {0xE7753654U, 0x00000002U}, /* SEC_MODID[636]:SYDM113*/ + [637] = {0xE7753658U, 0x00000002U}, /* SEC_MODID[637]:SYDM114*/ + [638] = {0xE775365CU, 0x00000002U}, /* SEC_MODID[638]:SYDM115*/ + [639] = {0xE7753660U, 0x00000002U}, /* SEC_MODID[639]:SYDM102*/ + [640] = {0xE7753664U, 0x00000002U}, /* SEC_MODID[640]:SYDM103*/ + [641] = {0xE7753668U, 0x00000002U}, /* SEC_MODID[641]:SYDM104*/ + [642] = {0xE775366CU, 0x00000002U}, /* SEC_MODID[642]:SYDM105*/ + [643] = {0xE7753670U, 0x00000002U}, /* SEC_MODID[643]:SYDM106*/ + [644] = {0xE7753674U, 0x00000002U}, /* SEC_MODID[644]:SYDM107*/ + [645] = {0xE7753678U, 0x00000002U}, /* SEC_MODID[645]:SYDM108*/ + [646] = {0xE775367CU, 0x00000002U}, /* SEC_MODID[646]:SYDM109*/ + [647] = {0xE7753680U, 0x00000002U}, /* SEC_MODID[647]:SYDM200*/ + [648] = {0xE7753684U, 0x00000002U}, /* SEC_MODID[648]:SYDM201*/ + [649] = {0xE7753688U, 0x00000002U}, /* SEC_MODID[649]:SYDM210*/ + [650] = {0xE775368CU, 0x00000002U}, /* SEC_MODID[650]:SYDM211*/ + [651] = {0xE7753690U, 0x00000002U}, /* SEC_MODID[651]:SYDM212*/ + [652] = {0xE7753694U, 0x00000002U}, /* SEC_MODID[652]:SYDM213*/ + [653] = {0xE7753698U, 0x00000002U}, /* SEC_MODID[653]:SYDM214*/ + [654] = {0xE775369CU, 0x00000002U}, /* SEC_MODID[654]:SYDM215*/ + [655] = {0xE77536A0U, 0x00000002U}, /* SEC_MODID[655]:SYDM202*/ + [656] = {0xE77536A4U, 0x00000002U}, /* SEC_MODID[656]:SYDM203*/ + [657] = {0xE77536A8U, 0x00000002U}, /* SEC_MODID[657]:SYDM204*/ + [658] = {0xE77536ACU, 0x00000002U}, /* SEC_MODID[658]:SYDM205*/ + [659] = {0xE77536B0U, 0x00000002U}, /* SEC_MODID[659]:SYDM206*/ + [660] = {0xE77536B4U, 0x00000002U}, /* SEC_MODID[660]:SYDM207*/ + [661] = {0xE77536B8U, 0x00000002U}, /* SEC_MODID[661]:SYDM208*/ + [662] = {0xE77536BCU, 0x00000002U}, /* SEC_MODID[662]:SYDM209*/ + [663] = {0xFE683400U, 0x00000002U}, /* SEC_MODID[663]:ARVC0*/ + [664] = {0xFE683404U, 0x00000002U}, /* SEC_MODID[664]:ARVC1*/ + [665] = {0xFE683408U, 0x00000002U}, /* SEC_MODID[665]:ARVC2*/ + [666] = {0xFE68340CU, 0x00000002U}, /* SEC_MODID[666]:ARVC3*/ + [667] = {0xFE683410U, 0x00000002U}, /* SEC_MODID[667]:AXIFBABUSVC*/ + [668] = {0xFE683414U, 0x00000002U}, /* SEC_MODID[668]:ARVC4*/ + [669] = {0xFE683418U, 0x00000002U}, /* SEC_MODID[669]:ARVC5*/ + [670] = {0xFE68341CU, 0x00000002U}, /* SEC_MODID[670]:ARVC6*/ + [671] = {0xFE683420U, 0x00000002U}, /* SEC_MODID[671]:ARVC7*/ + [672] = {0xFE683424U, 0x00000002U}, /* SEC_MODID[672]:ARVC8*/ + [673] = {0xFE68342CU, 0x00000002U}, /* SEC_MODID[673]:ECMVC0*/ + [674] = {0xFE683434U, 0x00000002U}, /* SEC_MODID[674]:IMR0*/ + [675] = {0xFE683438U, 0x00000002U}, /* SEC_MODID[675]:IMR1*/ + [676] = {0xFE68343CU, 0x00000002U}, /* SEC_MODID[676]:IPMMUVC01*/ + [677] = {0xFE683440U, 0x00000002U}, /* SEC_MODID[677]:IPMMUVC10*/ + [678] = {0xFE683444U, 0x00000002U}, /* SEC_MODID[678]:IMS0*/ + [679] = {0xFE683448U, 0x00000002U}, /* SEC_MODID[679]:IMS1*/ + [680] = {0xFE68344CU, 0x00000002U}, /* SEC_MODID[680]:IPMMUVC00*/ + [681] = {0xFE683450U, 0x00000002U}, /* SEC_MODID[681]:IPMMUVC11*/ + [682] = {0xFE683454U, 0x00000002U}, /* SEC_MODID[682]:IPMMUVC12*/ + [683] = {0xFE683458U, 0x00000002U}, /* SEC_MODID[683]:IPMMUVC13*/ + [684] = {0xFE68345CU, 0x00000002U}, /* SEC_MODID[684]:IPMMUVC14*/ + [685] = {0xFE683460U, 0x00000002U}, /* SEC_MODID[685]:IPMMUVC15*/ + [686] = {0xFE683464U, 0x00000002U}, /* SEC_MODID[686]:IPMMUVC02*/ + [687] = {0xFE683468U, 0x00000002U}, /* SEC_MODID[687]:IPMMUVC03*/ + [688] = {0xFE68346CU, 0x00000002U}, /* SEC_MODID[688]:IPMMUVC04*/ + [689] = {0xFE683470U, 0x00000002U}, /* SEC_MODID[689]:IPMMUVC05*/ + [690] = {0xFE683474U, 0x00000002U}, /* SEC_MODID[690]:IPMMUVC06*/ + [691] = {0xFE683478U, 0x00000002U}, /* SEC_MODID[691]:IPMMUVC07*/ + [692] = {0xFE68347CU, 0x00000002U}, /* SEC_MODID[692]:IPMMUVC08*/ + [693] = {0xFE683480U, 0x00000002U}, /* SEC_MODID[693]:IPMMUVC09*/ + [694] = {0xFE683484U, 0x00000002U}, /* SEC_MODID[694]:IV1ES*/ + [695] = {0xFEBE3400U, 0x00000002U}, /* SEC_MODID[695]:CSITOP0*/ + [696] = {0xFEBE3404U, 0x00000002U}, /* SEC_MODID[696]:ARVI10*/ + [697] = {0xFEBE3408U, 0x00000002U}, /* SEC_MODID[697]:ARVI11*/ + [698] = {0xFEBE340CU, 0x00000002U}, /* SEC_MODID[698]:ARVI12*/ + [699] = {0xFEBE3410U, 0x00000002U}, /* SEC_MODID[699]:ARVI13*/ + [700] = {0xFEBE3414U, 0x00000002U}, /* SEC_MODID[700]:ARVI14*/ + [701] = {0xFEBE3418U, 0x00000002U}, /* SEC_MODID[701]:ARVI15*/ + [702] = {0xFEBE341CU, 0x00000002U}, /* SEC_MODID[702]:ARVI16*/ + [703] = {0xFEBE3420U, 0x00000002U}, /* SEC_MODID[703]:ARVI17*/ + [704] = {0xFEBE3424U, 0x00000002U}, /* SEC_MODID[704]:ARVI18*/ + [705] = {0xFEBE342CU, 0x00000002U}, /* SEC_MODID[705]:CSITOP1*/ + [706] = {0xFEBE3434U, 0x00000002U}, /* SEC_MODID[706]:DSITLINK0*/ + [707] = {0xFEBE343CU, 0x00000002U}, /* SEC_MODID[707]:ECMVIO1*/ + [708] = {0xFEBE3444U, 0x00000002U}, /* SEC_MODID[708]:IPMMUVI001*/ + [709] = {0xFEBE3448U, 0x00000002U}, /* SEC_MODID[709]:FCPVX0*/ + [710] = {0xFEBE3458U, 0x00000002U}, /* SEC_MODID[710]:IPMMUVI000*/ + [711] = {0xFEBE345CU, 0x00000002U}, /* SEC_MODID[711]:IPMMUVI100*/ + [712] = {0xFEBE3460U, 0x00000002U}, /* SEC_MODID[712]:IPMMUVI010*/ + [713] = {0xFEBE3464U, 0x00000002U}, /* SEC_MODID[713]:IPMMUVI011*/ + [714] = {0xFEBE3468U, 0x00000002U}, /* SEC_MODID[714]:VSPX0*/ + [715] = {0xFEBE3478U, 0x00000002U}, /* SEC_MODID[715]:IPMMUVI012*/ + [716] = {0xFEBE347CU, 0x00000002U}, /* SEC_MODID[716]:IPMMUVI013*/ + [717] = {0xFEBE3480U, 0x00000002U}, /* SEC_MODID[717]:IPMMUVI014*/ + [718] = {0xFEBE3484U, 0x00000002U}, /* SEC_MODID[718]:IPMMUVI015*/ + [719] = {0xFEBE3488U, 0x00000002U}, /* SEC_MODID[719]:IPMMUVI002*/ + [720] = {0xFEBE348CU, 0x00000002U}, /* SEC_MODID[720]:IPMMUVI003*/ + [721] = {0xFEBE3490U, 0x00000002U}, /* SEC_MODID[721]:IPMMUVI004*/ + [722] = {0xFEBE3494U, 0x00000002U}, /* SEC_MODID[722]:IPMMUVI005*/ + [723] = {0xFEBE3498U, 0x00000002U}, /* SEC_MODID[723]:IPMMUVI006*/ + [724] = {0xFEBE349CU, 0x00000002U}, /* SEC_MODID[724]:IPMMUVI007*/ + [725] = {0xFEBE34A0U, 0x00000002U}, /* SEC_MODID[725]:IPMMUVI008*/ + [726] = {0xFEBE34A4U, 0x00000002U}, /* SEC_MODID[726]:IPMMUVI009*/ + [727] = {0xFEBE34A8U, 0x00000002U}, /* SEC_MODID[727]:IPMMUVI101*/ + [728] = {0xFEBE34ACU, 0x00000002U}, /* SEC_MODID[728]:IPMMUVI110*/ + [729] = {0xFEBE34B0U, 0x00000002U}, /* SEC_MODID[729]:IPMMUVI111*/ + [730] = {0xFEBE34B4U, 0x00000002U}, /* SEC_MODID[730]:IPMMUVI112*/ + [731] = {0xFEBE34B8U, 0x00000002U}, /* SEC_MODID[731]:IPMMUVI113*/ + [732] = {0xFEBE34BCU, 0x00000002U}, /* SEC_MODID[732]:IPMMUVI114*/ + [733] = {0xFEBE34C0U, 0x00000002U}, /* SEC_MODID[733]:IPMMUVI115*/ + [734] = {0xFEBE34C4U, 0x00000002U}, /* SEC_MODID[734]:IPMMUVI102*/ + [735] = {0xFEBE34C8U, 0x00000002U}, /* SEC_MODID[735]:IPMMUVI103*/ + [736] = {0xFEBE34CCU, 0x00000002U}, /* SEC_MODID[736]:IPMMUVI104*/ + [737] = {0xFEBE34D0U, 0x00000002U}, /* SEC_MODID[737]:IPMMUVI105*/ + [738] = {0xFEBE34D4U, 0x00000002U}, /* SEC_MODID[738]:IPMMUVI106*/ + [739] = {0xFEBE34D8U, 0x00000002U}, /* SEC_MODID[739]:IPMMUVI107*/ + [740] = {0xFEBE34DCU, 0x00000002U}, /* SEC_MODID[740]:IPMMUVI108*/ + [741] = {0xFEBE34E0U, 0x00000002U}, /* SEC_MODID[741]:IPMMUVI109*/ + [742] = {0xFEBE3504U, 0x00000002U}, /* SEC_MODID[742]:AXIFBABUSVIO*/ + [743] = {0xFEBF3400U, 0x00000002U}, /* SEC_MODID[743]:ARVI0*/ + [744] = {0xFEBF3404U, 0x00000002U}, /* SEC_MODID[744]:ARVI1*/ + [745] = {0xFEBF3408U, 0x00000002U}, /* SEC_MODID[745]:ARVI2*/ + [746] = {0xFEBF340CU, 0x00000002U}, /* SEC_MODID[746]:ARVI3*/ + [747] = {0xFEBF3410U, 0x00000002U}, /* SEC_MODID[747]:ARVI4*/ + [748] = {0xFEBF3414U, 0x00000002U}, /* SEC_MODID[748]:ARVI5*/ + [749] = {0xFEBF3418U, 0x00000002U}, /* SEC_MODID[749]:ARVI6*/ + [750] = {0xFEBF341CU, 0x00000002U}, /* SEC_MODID[750]:ARVI7*/ + [751] = {0xFEBF3420U, 0x00000002U}, /* SEC_MODID[751]:ARVI8*/ + [752] = {0xFEBF3424U, 0x00000002U}, /* SEC_MODID[752]:ECMVIO0*/ + [753] = {0xFEBF3428U, 0x00000002U}, /* SEC_MODID[753]:ISP0*/ + [754] = {0xFEBF342CU, 0x00000002U}, /* SEC_MODID[754]:ISP0CORE*/ + [755] = {0xFEBF3430U, 0x00000002U}, /* SEC_MODID[755]:ISP1*/ + [756] = {0xFEBF3454U, 0x00000002U}, /* SEC_MODID[756]:VIN00*/ + [757] = {0xFEBF3458U, 0x00000002U}, /* SEC_MODID[757]:VIN01*/ + [758] = {0xFEBF345CU, 0x00000002U}, /* SEC_MODID[758]:VIN02*/ + [759] = {0xFEBF3460U, 0x00000002U}, /* SEC_MODID[759]:VIN03*/ + [760] = {0xFEBF3464U, 0x00000002U}, /* SEC_MODID[760]:VIN04*/ + [761] = {0xFEBF3468U, 0x00000002U}, /* SEC_MODID[761]:VIN05*/ + [762] = {0xFEBF346CU, 0x00000002U}, /* SEC_MODID[762]:VIN06*/ + [763] = {0xFEBF3470U, 0x00000002U}, /* SEC_MODID[763]:VIN07*/ + [764] = {0xFEBF3474U, 0x00000002U}, /* SEC_MODID[764]:VIN10*/ + [765] = {0xFEBF3478U, 0x00000002U}, /* SEC_MODID[765]:VIN11*/ + [766] = {0xFEBF347CU, 0x00000002U}, /* SEC_MODID[766]:VIN12*/ + [767] = {0xFEBF3480U, 0x00000002U}, /* SEC_MODID[767]:VIN13*/ + [768] = {0xFEBF3484U, 0x00000002U}, /* SEC_MODID[768]:VIN14*/ + [769] = {0xFEBF3488U, 0x00000002U}, /* SEC_MODID[769]:VIN15*/ + [770] = {0xFEBF348CU, 0x00000002U}, /* SEC_MODID[770]:VIN16*/ + [771] = {0xFEBF3490U, 0x00000002U}, /* SEC_MODID[771]:VIN17*/ + [772] = {0xE7B13400U, 0x00000002U}, /* SEC_MODID[772]:ARVIP00*/ + [773] = {0xE7B13404U, 0x00000002U}, /* SEC_MODID[773]:ARVIP01*/ + [774] = {0xE7B13408U, 0x00000002U}, /* SEC_MODID[774]:ARVIP02*/ + [775] = {0xE7B1340CU, 0x00000002U}, /* SEC_MODID[775]:ARVIP03*/ + [776] = {0xE7B13410U, 0x00000002U}, /* SEC_MODID[776]:AXIFBABUSVIP0*/ + [777] = {0xE7B13414U, 0x00000002U}, /* SEC_MODID[777]:ARVIP04*/ + [778] = {0xE7B13418U, 0x00000002U}, /* SEC_MODID[778]:ARVIP05*/ + [779] = {0xE7B1341CU, 0x00000002U}, /* SEC_MODID[779]:ARVIP06*/ + [780] = {0xE7B13420U, 0x00000002U}, /* SEC_MODID[780]:ARVIP07*/ + [781] = {0xE7B13424U, 0x00000002U}, /* SEC_MODID[781]:ARVIP08*/ + [782] = {0xE7B1342CU, 0x00000002U}, /* SEC_MODID[782]:ECMVIP0*/ + [783] = {0xE7B13430U, 0x00000002U}, /* SEC_MODID[783]:IPMMUVIP000*/ + [784] = {0xE7B13438U, 0x00000002U}, /* SEC_MODID[784]:SMPO0*/ + [785] = {0xE7B1343CU, 0x00000002U}, /* SEC_MODID[785]:SMPS0*/ + [786] = {0xE7B13440U, 0x00000002U}, /* SEC_MODID[786]:UMFL0*/ + [787] = {0xE7B13444U, 0x00000002U}, /* SEC_MODID[787]:IPMMUVIP001*/ + [788] = {0xE7B13448U, 0x00000002U}, /* SEC_MODID[788]:IPMMUVIP010*/ + [789] = {0xE7B1344CU, 0x00000002U}, /* SEC_MODID[789]:IPMMUVIP011*/ + [790] = {0xE7B13450U, 0x00000002U}, /* SEC_MODID[790]:UMFL0M_W*/ + [791] = {0xE7B13454U, 0x00000002U}, /* SEC_MODID[791]:IPMMUVIP012*/ + [792] = {0xE7B13458U, 0x00000002U}, /* SEC_MODID[792]:IPMMUVIP013*/ + [793] = {0xE7B1345CU, 0x00000002U}, /* SEC_MODID[793]:IPMMUVIP014*/ + [794] = {0xE7B13460U, 0x00000002U}, /* SEC_MODID[794]:IPMMUVIP015*/ + [795] = {0xE7B13464U, 0x00000002U}, /* SEC_MODID[795]:IPMMUVIP002*/ + [796] = {0xE7B13468U, 0x00000002U}, /* SEC_MODID[796]:IPMMUVIP003*/ + [797] = {0xE7B1346CU, 0x00000002U}, /* SEC_MODID[797]:IPMMUVIP004*/ + [798] = {0xE7B13470U, 0x00000002U}, /* SEC_MODID[798]:IPMMUVIP005*/ + [799] = {0xE7B13474U, 0x00000002U}, /* SEC_MODID[799]:IPMMUVIP006*/ + [800] = {0xE7B13478U, 0x00000002U}, /* SEC_MODID[800]:IPMMUVIP007*/ + [801] = {0xE7B1347CU, 0x00000002U}, /* SEC_MODID[801]:IPMMUVIP008*/ + [802] = {0xE7B13480U, 0x00000002U}, /* SEC_MODID[802]:IPMMUVIP009*/ + [803] = {0xFF8834A0U, 0x00000002U}, /* SEC_MODID[803]:ARDSP0*/ + [804] = {0xFF8834A4U, 0x00000002U}, /* SEC_MODID[804]:ARDSP1*/ + [805] = {0xFF8834A8U, 0x00000002U}, /* SEC_MODID[805]:ARDSP2*/ + [806] = {0xFF8834ACU, 0x00000002U}, /* SEC_MODID[806]:ARDSP3*/ + [807] = {0xFF8834B0U, 0x00000002U}, /* SEC_MODID[807]:ARDSP4*/ + [808] = {0xFF8834B4U, 0x00000002U}, /* SEC_MODID[808]:ARDSP5*/ + [809] = {0xFF8834B8U, 0x00000002U}, /* SEC_MODID[809]:ARDSP6*/ + [810] = {0xFF8834BCU, 0x00000002U}, /* SEC_MODID[810]:ARDSP7*/ + [811] = {0xFF8834C0U, 0x00000002U}, /* SEC_MODID[811]:ECMDSP*/ + [812] = {0xFF883490U, 0x00000002U}, /* SEC_MODID[812]:AXIDSP0*/ + [813] = {0xFF883494U, 0x00000002U}, /* SEC_MODID[813]:AXIDSP1*/ + [814] = {0xFF883498U, 0x00000002U}, /* SEC_MODID[814]:AXIDSP2*/ + [815] = {0xFF88349CU, 0x00000002U}, /* SEC_MODID[815]:AXIDSP3*/ + [816] = {0xE7753424U, 0x00000002U}, /* SEC_MODID[816]:RSV0*/ + [817] = {0xE7B1350CU, 0x00000002U}, /* SEC_MODID[817]:PAP*/ + [818] = {0xFEBD3428U, 0x00000002U}, /* SEC_MODID[818]:DOC*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_axi_tbl" +#else +__attribute__ ((section(".rgid_axi_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[] = { + [0] = {0xFFC82010U, 0x0000000FU}, /* RGIDR_MODID[4]:ARRT01*/ + [1] = {0xFFC82014U, 0x0000000FU}, /* RGIDR_MODID[5]:ARRT02*/ + [2] = {0xE6002048U, 0x0000000FU}, /* RGIDR_MODID[41]:ARS01*/ + [3] = {0xE600204CU, 0x0000000FU}, /* RGIDR_MODID[42]:ARS02*/ + [4] = {0xE7762028U, 0x0000000FU}, /* RGIDR_MODID[99]:ARSP31*/ + [5] = {0xE776202CU, 0x0000000FU}, /* RGIDR_MODID[100]:ARSP32*/ + [6] = {0xE7792004U, 0x0000000FU}, /* RGIDR_MODID[114]:ARSP41*/ + [7] = {0xE7792008U, 0x0000000FU}, /* RGIDR_MODID[115]:ARSP42*/ + [8] = {0xFEBD2004U, 0x0000000FU}, /* RGIDR_MODID[153]:ARVI41*/ + [9] = {0xFEBD2008U, 0x0000000FU}, /* RGIDR_MODID[154]:ARVI42*/ + [10] = {0xE6582140U, 0x0000000FU}, /* RGIDR_MODID[199]:ARHC1*/ + [11] = {0xE6582144U, 0x0000000FU}, /* RGIDR_MODID[200]:ARHC2*/ + [12] = {0xFF882004U, 0x0000000FU}, /* RGIDR_MODID[215]:ARIMP01*/ + [13] = {0xFF882008U, 0x0000000FU}, /* RGIDR_MODID[216]:ARIMP02*/ + [14] = {0xFD812004U, 0x0000000FU}, /* RGIDR_MODID[247]:ARPV1*/ + [15] = {0xFD81200CU, 0x0000000FU}, /* RGIDR_MODID[249]:ARPV2*/ + [16] = {0xE6622004U, 0x0000000FU}, /* RGIDR_MODID[279]:ARRC1*/ + [17] = {0xE6622008U, 0x0000000FU}, /* RGIDR_MODID[280]:ARRC2*/ + [18] = {0xFFC42060U, 0x0000000FU}, /* RGIDR_MODID[316]:ARRD1*/ + [19] = {0xFFC42064U, 0x0000000FU}, /* RGIDR_MODID[317]:ARRD2*/ + [20] = {0xFFC42084U, 0x0000000FU}, /* RGIDR_MODID[325]:ARRT1*/ + [21] = {0xFFC42088U, 0x0000000FU}, /* RGIDR_MODID[326]:ARRT2*/ + [24] = {0xFF862004U, 0x0000000FU}, /* RGIDR_MODID[464]:ARSC1*/ + [25] = {0xFF862008U, 0x0000000FU}, /* RGIDR_MODID[465]:ARSC2*/ + [22] = {0xFF862028U, 0x0000000FU}, /* RGIDR_MODID[473]:ARSTM1*/ + [23] = {0xFF862038U, 0x0000000FU}, /* RGIDR_MODID[476]:ARSTM2*/ + [26] = {0xE67C2004U, 0x0000000FU}, /* RGIDR_MODID[516]:AXIARNMM*/ + [27] = {0xE67C200CU, 0x0000000FU}, /* RGIDR_MODID[518]:ARSM1*/ + [28] = {0xE67C2010U, 0x0000000FU}, /* RGIDR_MODID[519]:ARSM2*/ + [29] = {0xFF802004U, 0x0000000FU}, /* RGIDR_MODID[562]:ARSN1*/ + [30] = {0xFF802008U, 0x0000000FU}, /* RGIDR_MODID[563]:ARSN2*/ + [31] = {0xE7752004U, 0x0000000FU}, /* RGIDR_MODID[572]:ARSD01*/ + [32] = {0xE7752008U, 0x0000000FU}, /* RGIDR_MODID[573]:ARSD02*/ + [33] = {0xE775203CU, 0x0000000FU}, /* RGIDR_MODID[584]:ARSP01*/ + [34] = {0xE7752040U, 0x0000000FU}, /* RGIDR_MODID[585]:ARSP02*/ + [35] = {0xFE682004U, 0x0000000FU}, /* RGIDR_MODID[664]:ARVC1*/ + [36] = {0xFE682008U, 0x0000000FU}, /* RGIDR_MODID[665]:ARVC2*/ + [37] = {0xFEBE2008U, 0x0000000FU}, /* RGIDR_MODID[697]:ARVI11*/ + [38] = {0xFEBE200CU, 0x0000000FU}, /* RGIDR_MODID[698]:ARVI12*/ + [39] = {0xFEBF2004U, 0x0000000FU}, /* RGIDR_MODID[744]:ARVI1*/ + [40] = {0xFEBF2008U, 0x0000000FU}, /* RGIDR_MODID[745]:ARVI2*/ + [41] = {0xE7B12004U, 0x0000000FU}, /* RGIDR_MODID[772]:ARVIP01*/ + [42] = {0xE7B12008U, 0x0000000FU}, /* RGIDR_MODID[773]:ARVIP02*/ + [43] = {0xFF8820A4U, 0x0000000FU}, /* RGIDR_MODID[803]:ARDSP1*/ + [44] = {0xFF8820A8U, 0x0000000FU}, /* RGIDR_MODID[804]:ARDSP2*/ + [45] = {0xFFC82410U, 0x00000000U}, /* RGIDW_MODID[4]:ARRT01*/ + [46] = {0xFFC82414U, 0x00000000U}, /* RGIDW_MODID[5]:ARRT02*/ + [47] = {0xE6002448U, 0x00000000U}, /* RGIDW_MODID[41]:ARS01*/ + [48] = {0xE600244CU, 0x00000000U}, /* RGIDW_MODID[42]:ARS02*/ + [49] = {0xE7762428U, 0x00000000U}, /* RGIDW_MODID[99]:ARSP31*/ + [50] = {0xE776242CU, 0x00000000U}, /* RGIDW_MODID[100]:ARSP32*/ + [51] = {0xE7792404U, 0x00000000U}, /* RGIDW_MODID[114]:ARSP41*/ + [52] = {0xE7792408U, 0x00000000U}, /* RGIDW_MODID[115]:ARSP42*/ + [53] = {0xFEBD2404U, 0x00000000U}, /* RGIDW_MODID[153]:ARVI41*/ + [54] = {0xFEBD2408U, 0x00000000U}, /* RGIDW_MODID[154]:ARVI42*/ + [55] = {0xE6582540U, 0x00000000U}, /* RGIDW_MODID[199]:ARHC1*/ + [56] = {0xE6582544U, 0x00000000U}, /* RGIDW_MODID[200]:ARHC2*/ + [57] = {0xFF8824A4U, 0x00000000U}, /* RGIDW_MODID[802]:ARDSP1*/ + [58] = {0xFF8824A8U, 0x00000000U}, /* RGIDW_MODID[803]:ARDSP2*/ + [59] = {0xFF882404U, 0x00000000U}, /* RGIDW_MODID[215]:ARIMP01*/ + [60] = {0xFF882408U, 0x00000000U}, /* RGIDW_MODID[216]:ARIMP02*/ + [61] = {0xFD812404U, 0x00000000U}, /* RGIDW_MODID[247]:ARPV1*/ + [62] = {0xFD81240CU, 0x00000000U}, /* RGIDW_MODID[249]:ARPV2*/ + [63] = {0xE6622404U, 0x00000000U}, /* RGIDW_MODID[279]:ARRC1*/ + [64] = {0xE6622408U, 0x00000000U}, /* RGIDW_MODID[280]:ARRC2*/ + [65] = {0xFFC42460U, 0x00000000U}, /* RGIDW_MODID[315]:ARRD1*/ + [66] = {0xFFC42464U, 0x00000000U}, /* RGIDW_MODID[316]:ARRD2*/ + [67] = {0xFFC42484U, 0x00000000U}, /* RGIDW_MODID[324]:ARRT1*/ + [68] = {0xFFC42488U, 0x00000000U}, /* RGIDW_MODID[325]:ARRT2*/ + [71] = {0xFF862404U, 0x00000000U}, /* RGIDW_MODID[463]:ARSC1*/ + [72] = {0xFF862408U, 0x00000000U}, /* RGIDW_MODID[464]:ARSC2*/ + [69] = {0xFF862428U, 0x00000000U}, /* RGIDW_MODID[472]:ARSTM1*/ + [70] = {0xFF862438U, 0x00000000U}, /* RGIDW_MODID[475]:ARSTM2*/ + [73] = {0xE67C2404U, 0x00000000U}, /* RGIDW_MODID[515]:AXIARNMM*/ + [74] = {0xE67C240CU, 0x00000000U}, /* RGIDW_MODID[517]:ARSM1*/ + [75] = {0xE67C2410U, 0x00000000U}, /* RGIDW_MODID[518]:ARSM2*/ + [76] = {0xFF802404U, 0x00000000U}, /* RGIDW_MODID[561]:ARSN1*/ + [77] = {0xFF802408U, 0x00000000U}, /* RGIDW_MODID[562]:ARSN2*/ + [78] = {0xE7752404U, 0x00000000U}, /* RGIDW_MODID[571]:ARSD01*/ + [79] = {0xE7752408U, 0x00000000U}, /* RGIDW_MODID[572]:ARSD02*/ + [80] = {0xE775243CU, 0x00000000U}, /* RGIDW_MODID[583]:ARSP01*/ + [81] = {0xE7752440U, 0x00000000U}, /* RGIDW_MODID[584]:ARSP02*/ + [82] = {0xFE682404U, 0x00000000U}, /* RGIDW_MODID[663]:ARVC1*/ + [83] = {0xFE682408U, 0x00000000U}, /* RGIDW_MODID[664]:ARVC2*/ + [84] = {0xFEBE2408U, 0x00000000U}, /* RGIDW_MODID[696]:ARVI11*/ + [85] = {0xFEBE240CU, 0x00000000U}, /* RGIDW_MODID[697]:ARVI12*/ + [86] = {0xFEBF2404U, 0x00000000U}, /* RGIDW_MODID[743]:ARVI1*/ + [87] = {0xFEBF2408U, 0x00000000U}, /* RGIDW_MODID[744]:ARVI2*/ + [88] = {0xE7B12404U, 0x00000000U}, /* RGIDW_MODID[771]:ARVIP01*/ + [89] = {0xE7B12408U, 0x00000000U}, /* RGIDW_MODID[772]:ARVIP02*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +/* RAM protection setting for SECDIV[n]D_0 / SECCTRR[m]D_0 / SECCTRW[m]D_0 */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram0_protection_table[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM0_ICUMX_IPL_AREA] = {NOT_USED_VALUE, {0x0000FFFCU, 0x0000FFFEU}}, /* not used for address value */ + /* Area0 phys:0xE0000000-0xE003FFFF R:RGID0/1 W:RGID0 */ + [RTVRAM0_ICUMX_FW_AREA] = {RTVRAM0_AREA1_TOP, {0x0004FFFEU, 0x0004FFFEU}}, /* Area1 phys:0xE0040000-0xE00FFFFF R:RGID0 W:RGID0 */ + [2] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [3] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for SECDIV[n]D_1 / SECCTRR[m]D_1 / SECCTRW[m]D_1 */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM1_BLANK_AREA] = {NOT_USED_VALUE, {0x0000FFB6U, 0x0000FFB7U}}, /* not used for address value */ + /* Area0 phys:0xE2000000-0xE200FFFF R:RGID0/3/6 W:RGID3/6 */ + [RTVRAM1_EXTEND_CACHE_AREA] = {RTVRAM1_AREA1_TOP, {0x0000BFFFU, 0x0000BFFFU}}, /* Area1 phys:0xE2010000-0xE20FFFFF R:RGID14 W:RGID14 */ + [RTVRAM1_RTOS_AREA] = {RTVRAM1_AREA2_TOP, {0x0000FFF4U, 0x0000FFF5U}}, /* Area2 phys:0xE2100000-0xE3BFFFFF R:RGID0/1/3 W:RGID1/3 */ + [3] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for SPTDIVCR[n] / SPTRGNCR[n] / SPTSECCR[n] */ +const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX] = { + /* access Secure */ + /* address R | W R|W */ + [SYSTEM_RAM_CX_2ND_IPL] = {NOT_USED_VALUE, {0xFFD8FFD8U, 0x00000000U}}, /* not used for address value */ + /* + * Change the access permission from 0xFFD8FFD8 to 0xFFD8FFD9 + * if user want to enable protection of System Ram Area0. + */ + /* Area0 phys:0xE6300000-0xE635DFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [SYSTEM_RAM_SHARED_MEM] = {SYSTEM_RAM_AREA1_TOP, {0xFFD8FFD8U, 0x00000000U}}, /* Area1 phys:0xE635E000-0xE635FFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [2] = {SYSTEM_RAM_AREA2_TOP, {0xFFDAFFDAU, 0x00000000U}}, /* Area2 phys:0xE6360000-0xE63FFFFF R:RGID0/2/5 W:RGID0/2/5 */ + [3] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for DPTDIVCR[n] / DPTRGNCR[n] / DPTSECCR[n] */ +const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX] = { + /* access secure */ + /* address R | W R|W */ + [RTVRAM1_EXTEND_AREA] = {NOT_USED_VALUE, {0xBFFFBFFFU, 0x00000000U}}, /* not used for address value */ + /* Area0 phys:0x04_00000000-0x04_01BFFFFF R:RGID14 W:RGID14 */ + [CR_FW_SHARED_AREA] = {DRAM_ADDR_AREA1, {0xFFBCFFBCU, 0x00000000U}}, /* Area1 phys:0x04_01C00000-0x04_01CFFFFF R:RGID0/1/6 W:RGID0/1/6 */ + /* This secure setting is added by sdram_protection() in loader_main function. */ + [SDRAM_BLANK_AREA] = {DRAM_ADDR_AREA2, {0xFF90FF90U, 0x00000000U}}, /* Area2:OPTEE_DISABLE phys:0x04_01D00000-0x04_063FFFFF + * Area2:OPTEE_ENABLE phys:0x04_01D00000-0x04_040FFFFF + * R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFBFFF9U, 0x00000404U}}, /* Area3 phys:0x04_06400000-0x04_0643FFFF R:RGID2 W:RGID1/2 */ + [SDRAM_PUBLIC_AREA] = {DRAM_ADDR_AREA4, {0xFF90FF90U, 0x00000000U}}, /* Area4 phys:0x04_06440000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA5, {0xFFB9FFB9U, 0x00000000U}}, /* Area5 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA6, {0xFFB1FFB1U, 0x00000000U}}, /* Area6 phys:0x04_08000000-0x04_1DBFFFFF R:RGID1/2/3/6 W:RGID1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA7, {0xFFB9FFB9U, 0x00000000U}}, /* Area7 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFBDFFBDU, 0x00000000U}}, /* Area8 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFDDFFDDU, 0x00000000U}}, /* Area9 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA11,{0xBF90BF90U, 0x00000000U}}, /* Area11 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA12,{0xFFF9FFF9U, 0x00000000U}}, /* Area12 phys:0x05_00000000-0x05_FFFFFFFF R:RGID1/2 W:RGID1/2 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA13,{0xFFFFFFFFU, 0x00000000U}}, /* Area13 phys:0x06_00000000-0x06_FFFFFFFF */ + [14] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [16] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +#else + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFAFFFAU, 0x00000404U}}, /* Area3 phys:0x04_04100000-0x04_063FFFFF R:RGID0/2 W:RGID0/2 */ + [SDRAM_PROTECT_AREA2] = {DRAM_ADDR_AREA4, {0xFFFBFFF9U, 0x00000404U}}, /* Area4 phys:0x04_06400000-0x04_0643FFFF R:RGID2 W:RGID1/2 */ + [SDRAM_BLANK_AREA2] = {DRAM_ADDR_AREA5, {0xFF90FF90U, 0x00000000U}}, /* Area5 phys:0x04_06440000-0x04_07DFFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [OPTEE_SHARED_AREA] = {DRAM_ADDR_AREA6, {0xFFFBFFFBU, 0x00000000U}}, /* Area6 phys:0x04_07E00000-0x04_07EFFFFF R:RGID2 W:RGID2 */ + [SDRAM_BLANK_AREA3] = {DRAM_ADDR_AREA7, {0xFF90FF90U, 0x00000000U}}, /* Area7 phys:0x04_07F00000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFB9FFB9U, 0x00000000U}}, /* Area8 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFB1FFB1U, 0x00000000U}}, /* Area9 phys:0x04_08000000-0x04_1DBFFFFF R:RGID1/2/3/6 W:RGID1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA11,{0xFFBDFFBDU, 0x00000000U}}, /* Area11 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA12,{0xFFDDFFDDU, 0x00000000U}}, /* Area12 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFB9FFB9U, 0x00000000U}}, /* Area13 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA14,{0xBF90BF90U, 0x00000000U}}, /* Area14 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA15,{0xFFF9FFF9U, 0x00000000U}}, /* Area15 phys:0x05_00000000-0x05_FFFFFFFF R:RGID1/2 W:RGID1/2 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA16,{0xFFFFFFFFU, 0x00000000U}}, /* Area16 phys:0x06_00000000-0x06_FFFFFFFF */ +#endif /*OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + [17] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [18] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [19] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [20] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [21] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [22] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [23] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [24] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [25] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [26] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [27] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [28] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [29] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [30] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [31] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [32] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [33] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [34] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [35] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [36] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [37] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [38] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [39] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [40] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [41] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [42] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [43] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [44] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [45] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [46] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [47] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [48] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [49] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [50] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [51] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [52] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [53] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [54] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [55] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [56] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [57] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [58] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [59] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [60] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [61] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [62] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [63] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX] = { + [0] = {0xEEE80570U, 0x00000002U}, /* IMRGID_IPMMU_VI0 */ + [1] = {0xEEEC0570U, 0x00000002U}, /* IMRGID_IPMMU_VI1 */ + [2] = {0xEEDC0570U, 0x00000002U}, /* IMRGID_IPMMU_VC0 */ + [3] = {0xEED80570U, 0x00000002U}, /* IMRGID_IPMMU_IR */ + [4] = {0xEE480570U, 0x00000001U}, /* IMRGID_IPMMU_RT0 */ + [5] = {0xEE4C0570U, 0x00000001U}, /* IMRGID_IPMMU_RT1 */ + [6] = {0xEED00570U, 0x00000001U}, /* IMRGID_IPMMU_DS0 */ + [7] = {0xEED40570U, 0x00000001U}, /* IMRGID_IPMMU_HSC */ + [8] = {0xEEF00570U, 0x00000002U}, /* IMRGID_IPMMU_VIP0 */ + [9] = {0xEEE00570U, 0x00000002U}, /* IMRGID_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX] = { + [0] = {0xEEE80578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI0 */ + [1] = {0xEEEC0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI1 */ + [2] = {0xEEDC0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VC0 */ + [3] = {0xEED80578U, 0x00000001U}, /* IMSECGRP_IPMMU_IR */ + [4] = {0xEE480578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT0 */ + [5] = {0xEE4C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT1 */ + [6] = {0xEED00578U, 0x00000001U}, /* IMSECGRP_IPMMU_DS0 */ + [7] = {0xEED40578U, 0x00000001U}, /* IMSECGRP_IPMMU_HSC */ + [8] = {0xEEF00578U, 0x00000001U}, /* IMSECGRP_IPMMU_VIP0 */ + [9] = {0xEEE00578U, 0x00000001U}, /* IMSECGRP_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX] = { + [0] = {0xEEE80574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI0 */ + [1] = {0xEEEC0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI1 */ + [2] = {0xEEDC0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VC0 */ + [3] = {0xEED80574U, 0x00000002U}, /* IMRGIDEN_IPMMU_IR */ + [4] = {0xEE480574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT0 */ + [5] = {0xEE4C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT1 */ + [6] = {0xEED00574U, 0x00000002U}, /* IMRGIDEN_IPMMU_DS0 */ + [7] = {0xEED40574U, 0x00000002U}, /* IMRGIDEN_IPMMU_HSC */ + [8] = {0xEEF00574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VIP0 */ + [9] = {0xEEE00574U, 0x00000002U}, /* IMRGIDEN_IPMMU_3DG */ +}; + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/common/crc32.c b/IPL/Customer/Mobis/V4H_Cx_Loader/common/crc32.c new file mode 100644 index 0000000..0ac3393 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/common/crc32.c @@ -0,0 +1,273 @@ +/* + * This file is derived from crc32.c from the zlib-1.1.3 distribution + * by Jean-loup Gailly and Mark Adler. + */ + +/* crc32.c -- compute the CRC-32 of a data stream + * Copyright (C) 1995-1998 Mark Adler + * For conditions of distribution and use, see copyright notice in zlib.h + */ + +#ifdef USE_HOSTCC +#include +#include +#else +// #include +#include +#endif +// #include +#include +/* from u-boot's compiler_types.h */ +#define __inline__ inline + +/* from u-boot's linux/types.h */ +#ifdef __CHECKER__ +#define __bitwise__ __attribute__((bitwise)) +# define __force __attribute__((force)) +#else +#define __bitwise__ +# define __force +#endif + +/* from u-boot's compiler.h */ +# define cpu_to_le32(x) (x) +# define le32_to_cpu(x) (x) + +#include +/* from u-boot's asm-generic/int-ll64.h */ +typedef unsigned int __u32; + +/* from u-boot's linux/types.h */ +// typedef __u32 __bitwise __be32; +#define __be32 __u32 + +/* from u-boot's linux/byteorder/swab.h */ +#define ___swab32(x) \ + ((__u32)( \ + (((__u32)(x) & (__u32)0x000000ffUL) << 24) | \ + (((__u32)(x) & (__u32)0x0000ff00UL) << 8) | \ + (((__u32)(x) & (__u32)0x00ff0000UL) >> 8) | \ + (((__u32)(x) & (__u32)0xff000000UL) >> 24) )) + +#ifndef __arch__swab32 +# define __arch__swab32(x) ___swab32(x) +#endif + +static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x) +{ + return __arch__swab32(x); +} + +# define __swab32(x) \ +(__builtin_constant_p((__u32)(x)) ? \ + ___swab32((x)) : \ + __fswab32((x))) + +/* from u-boot's linux/byteorder/little_endian.h */ +#define __cpu_to_be32(x) ((__force __be32)__swab32((x))) + +/* from u-boot's generic.h */ +#undef htonl +#define ___htonl(x) __cpu_to_be32(x) +#define htonl(x) ___htonl(x) + +// #include +#include + +#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) +#include +#endif + +#define tole(x) cpu_to_le32(x) + +#ifdef CONFIG_DYNAMIC_CRC_TABLE + +static int crc_table_empty = 1; +static uint32_t crc_table[256]; +static void make_crc_table OF((void)); + +/* + Generate a table for a byte-wise 32-bit CRC calculation on the polynomial: + x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1. + + Polynomials over GF(2) are represented in binary, one bit per coefficient, + with the lowest powers in the most significant bit. Then adding polynomials + is just exclusive-or, and multiplying a polynomial by x is a right shift by + one. If we call the above polynomial p, and represent a byte as the + polynomial q, also with the lowest power in the most significant bit (so the + byte 0xb1 is the polynomial x^7+x^3+x+1), then the CRC is (q*x^32) mod p, + where a mod b means the remainder after dividing a by b. + + This calculation is done using the shift-register method of multiplying and + taking the remainder. The register is initialized to zero, and for each + incoming bit, x^32 is added mod p to the register if the bit is a one (where + x^32 mod p is p+x^32 = x^26+...+1), and the register is multiplied mod p by + x (which is shifting right by one and adding x^32 mod p if the bit shifted + out is a one). We start with the highest power (least significant bit) of + q and repeat for all eight bits of q. + + The table is simply the CRC of all possible eight bit values. This is all + the information needed to generate CRC's on data a byte at a time for all + combinations of CRC register values and incoming bytes. +*/ +static void make_crc_table(void) +{ + uint32_t c; + int n, k; + uLong poly; /* polynomial exclusive-or pattern */ + /* terms of polynomial defining this crc (except x^32): */ + static uint8_t p[] = { + 0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26}; + + /* make exclusive-or pattern from polynomial (0xedb88320L) */ + poly = 0L; + for (n = 0; n < sizeof(p)/sizeof(uint8_t); n++) + poly |= 1L << (31 - p[n]); + + for (n = 0; n < 256; n++) + { + c = (uLong)n; + for (k = 0; k < 8; k++) + c = c & 1 ? poly ^ (c >> 1) : c >> 1; + crc_table[n] = tole(c); + } + crc_table_empty = 0; +} +#elif !defined(CONFIG_ARM64_CRC32) +/* ======================================================================== + * Table of CRC-32's of all single-byte values (made by make_crc_table) + */ + +static const uint32_t crc_table[256] = { +tole(0x00000000L), tole(0x77073096L), tole(0xee0e612cL), tole(0x990951baL), +tole(0x076dc419L), tole(0x706af48fL), tole(0xe963a535L), tole(0x9e6495a3L), +tole(0x0edb8832L), tole(0x79dcb8a4L), tole(0xe0d5e91eL), tole(0x97d2d988L), +tole(0x09b64c2bL), tole(0x7eb17cbdL), tole(0xe7b82d07L), tole(0x90bf1d91L), +tole(0x1db71064L), tole(0x6ab020f2L), tole(0xf3b97148L), tole(0x84be41deL), +tole(0x1adad47dL), tole(0x6ddde4ebL), tole(0xf4d4b551L), tole(0x83d385c7L), +tole(0x136c9856L), tole(0x646ba8c0L), tole(0xfd62f97aL), tole(0x8a65c9ecL), +tole(0x14015c4fL), tole(0x63066cd9L), tole(0xfa0f3d63L), tole(0x8d080df5L), +tole(0x3b6e20c8L), tole(0x4c69105eL), tole(0xd56041e4L), tole(0xa2677172L), +tole(0x3c03e4d1L), tole(0x4b04d447L), tole(0xd20d85fdL), tole(0xa50ab56bL), +tole(0x35b5a8faL), tole(0x42b2986cL), tole(0xdbbbc9d6L), tole(0xacbcf940L), +tole(0x32d86ce3L), tole(0x45df5c75L), tole(0xdcd60dcfL), tole(0xabd13d59L), +tole(0x26d930acL), tole(0x51de003aL), tole(0xc8d75180L), tole(0xbfd06116L), +tole(0x21b4f4b5L), tole(0x56b3c423L), tole(0xcfba9599L), tole(0xb8bda50fL), +tole(0x2802b89eL), tole(0x5f058808L), tole(0xc60cd9b2L), tole(0xb10be924L), +tole(0x2f6f7c87L), tole(0x58684c11L), tole(0xc1611dabL), tole(0xb6662d3dL), +tole(0x76dc4190L), tole(0x01db7106L), tole(0x98d220bcL), tole(0xefd5102aL), +tole(0x71b18589L), tole(0x06b6b51fL), tole(0x9fbfe4a5L), tole(0xe8b8d433L), +tole(0x7807c9a2L), tole(0x0f00f934L), tole(0x9609a88eL), tole(0xe10e9818L), +tole(0x7f6a0dbbL), tole(0x086d3d2dL), tole(0x91646c97L), tole(0xe6635c01L), +tole(0x6b6b51f4L), tole(0x1c6c6162L), tole(0x856530d8L), tole(0xf262004eL), +tole(0x6c0695edL), tole(0x1b01a57bL), tole(0x8208f4c1L), tole(0xf50fc457L), +tole(0x65b0d9c6L), tole(0x12b7e950L), tole(0x8bbeb8eaL), tole(0xfcb9887cL), +tole(0x62dd1ddfL), tole(0x15da2d49L), tole(0x8cd37cf3L), tole(0xfbd44c65L), +tole(0x4db26158L), tole(0x3ab551ceL), tole(0xa3bc0074L), tole(0xd4bb30e2L), +tole(0x4adfa541L), tole(0x3dd895d7L), tole(0xa4d1c46dL), tole(0xd3d6f4fbL), +tole(0x4369e96aL), tole(0x346ed9fcL), tole(0xad678846L), tole(0xda60b8d0L), +tole(0x44042d73L), tole(0x33031de5L), tole(0xaa0a4c5fL), tole(0xdd0d7cc9L), +tole(0x5005713cL), tole(0x270241aaL), tole(0xbe0b1010L), tole(0xc90c2086L), +tole(0x5768b525L), tole(0x206f85b3L), tole(0xb966d409L), tole(0xce61e49fL), +tole(0x5edef90eL), tole(0x29d9c998L), tole(0xb0d09822L), tole(0xc7d7a8b4L), +tole(0x59b33d17L), tole(0x2eb40d81L), tole(0xb7bd5c3bL), tole(0xc0ba6cadL), +tole(0xedb88320L), tole(0x9abfb3b6L), tole(0x03b6e20cL), tole(0x74b1d29aL), +tole(0xead54739L), tole(0x9dd277afL), tole(0x04db2615L), tole(0x73dc1683L), +tole(0xe3630b12L), tole(0x94643b84L), tole(0x0d6d6a3eL), tole(0x7a6a5aa8L), +tole(0xe40ecf0bL), tole(0x9309ff9dL), tole(0x0a00ae27L), tole(0x7d079eb1L), +tole(0xf00f9344L), tole(0x8708a3d2L), tole(0x1e01f268L), tole(0x6906c2feL), +tole(0xf762575dL), tole(0x806567cbL), tole(0x196c3671L), tole(0x6e6b06e7L), +tole(0xfed41b76L), tole(0x89d32be0L), tole(0x10da7a5aL), tole(0x67dd4accL), +tole(0xf9b9df6fL), tole(0x8ebeeff9L), tole(0x17b7be43L), tole(0x60b08ed5L), +tole(0xd6d6a3e8L), tole(0xa1d1937eL), tole(0x38d8c2c4L), tole(0x4fdff252L), +tole(0xd1bb67f1L), tole(0xa6bc5767L), tole(0x3fb506ddL), tole(0x48b2364bL), +tole(0xd80d2bdaL), tole(0xaf0a1b4cL), tole(0x36034af6L), tole(0x41047a60L), +tole(0xdf60efc3L), tole(0xa867df55L), tole(0x316e8eefL), tole(0x4669be79L), +tole(0xcb61b38cL), tole(0xbc66831aL), tole(0x256fd2a0L), tole(0x5268e236L), +tole(0xcc0c7795L), tole(0xbb0b4703L), tole(0x220216b9L), tole(0x5505262fL), +tole(0xc5ba3bbeL), tole(0xb2bd0b28L), tole(0x2bb45a92L), tole(0x5cb36a04L), +tole(0xc2d7ffa7L), tole(0xb5d0cf31L), tole(0x2cd99e8bL), tole(0x5bdeae1dL), +tole(0x9b64c2b0L), tole(0xec63f226L), tole(0x756aa39cL), tole(0x026d930aL), +tole(0x9c0906a9L), tole(0xeb0e363fL), tole(0x72076785L), tole(0x05005713L), +tole(0x95bf4a82L), tole(0xe2b87a14L), tole(0x7bb12baeL), tole(0x0cb61b38L), +tole(0x92d28e9bL), tole(0xe5d5be0dL), tole(0x7cdcefb7L), tole(0x0bdbdf21L), +tole(0x86d3d2d4L), tole(0xf1d4e242L), tole(0x68ddb3f8L), tole(0x1fda836eL), +tole(0x81be16cdL), tole(0xf6b9265bL), tole(0x6fb077e1L), tole(0x18b74777L), +tole(0x88085ae6L), tole(0xff0f6a70L), tole(0x66063bcaL), tole(0x11010b5cL), +tole(0x8f659effL), tole(0xf862ae69L), tole(0x616bffd3L), tole(0x166ccf45L), +tole(0xa00ae278L), tole(0xd70dd2eeL), tole(0x4e048354L), tole(0x3903b3c2L), +tole(0xa7672661L), tole(0xd06016f7L), tole(0x4969474dL), tole(0x3e6e77dbL), +tole(0xaed16a4aL), tole(0xd9d65adcL), tole(0x40df0b66L), tole(0x37d83bf0L), +tole(0xa9bcae53L), tole(0xdebb9ec5L), tole(0x47b2cf7fL), tole(0x30b5ffe9L), +tole(0xbdbdf21cL), tole(0xcabac28aL), tole(0x53b39330L), tole(0x24b4a3a6L), +tole(0xbad03605L), tole(0xcdd70693L), tole(0x54de5729L), tole(0x23d967bfL), +tole(0xb3667a2eL), tole(0xc4614ab8L), tole(0x5d681b02L), tole(0x2a6f2b94L), +tole(0xb40bbe37L), tole(0xc30c8ea1L), tole(0x5a05df1bL), tole(0x2d02ef8dL) +}; +#endif + +/* ========================================================================= */ +// # if __BYTE_ORDER == __LITTLE_ENDIAN +# define DO_CRC(x) crc = tab[(crc ^ (x)) & 255] ^ (crc >> 8) +// # else +// # define DO_CRC(x) crc = tab[((crc >> 24) ^ (x)) & 255] ^ (crc << 8) +// # endif + +/* ========================================================================= */ + +/* No ones complement version. JFFS2 (and other things ?) + * don't use ones compliment in their CRC calculations. + */ +uint32_t crc32_no_comp(uint32_t crc, const unsigned char *buf, uint len) +{ +#ifdef CONFIG_ARM64_CRC32 + crc = cpu_to_le32(crc); + while (len--) + crc = __builtin_aarch64_crc32b(crc, *buf++); + return le32_to_cpu(crc); +#else + const uint32_t *tab = crc_table; + const uint32_t *b =(const uint32_t *)buf; + size_t rem_len; +#ifdef CONFIG_DYNAMIC_CRC_TABLE + if (crc_table_empty) + make_crc_table(); +#endif + crc = cpu_to_le32(crc); + /* Align it */ + if (((long)b) & 3 && len) { + uint8_t *p = (uint8_t *)b; + do { + DO_CRC(*p++); + } while ((--len) && ((long)p)&3); + b = (uint32_t *)p; + } + + rem_len = len & 3; + len = len >> 2; + for (--b; len; --len) { + /* load data 32 bits wide, xor data 32 bits wide. */ + crc ^= *++b; /* use pre increment for speed */ + DO_CRC(0); + DO_CRC(0); + DO_CRC(0); + DO_CRC(0); + } + len = rem_len; + /* And the last few bytes */ + if (len) { + uint8_t *p = (uint8_t *)(b + 1) - 1; + do { + DO_CRC(*++p); /* use pre increment for speed */ + } while (--len); + } + + return le32_to_cpu(crc); +#endif +} +#undef DO_CRC + +uint32_t crc32(uint32_t crc, const unsigned char *p, uint len) +{ + return crc32_no_comp(crc ^ 0xffffffffL, p, len) ^ 0xffffffffL; +} diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/common/log/log.c b/IPL/Customer/Mobis/V4H_Cx_Loader/common/log/log.c new file mode 100644 index 0000000..170d2c0 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/common/log/log.c @@ -0,0 +1,264 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + +/******************************************************************************* + * DESCRIPTION : log + ******************************************************************************/ +/****************************************************************************** + * @file log.c + * - Version : 0.04 + * @brief Access protection setting driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + * : 16.06.2022 0.02 Change log output + * : 31.10.2022 0.03 License notation change. + * : 04.04.2023 0.04 Removed sprintf. + *****************************************************************************/ + +#include "stdarg.h" +#include "stdint.h" +#include "math.h" +#include "log.h" +#include "scif.h" + +#define NULL_CHAR '\0' + +/*********************************************************** + * log_printf + ***********************************************************/ + +#define DOUBLE_PRINT_RES (0.001) +static uint32_t double_print(double num) +{ + uint8_t num_buf[10]; + uint32_t count = 0U; + uint32_t i = 0U; + uint32_t rem; + double unum; + double res = 1/DOUBLE_PRINT_RES; + + if (num < 0) { + (void)console_putc((uint8_t)'-'); + count = 1U; + unum = -num; + } else { + unum = num; + } + + unum /= (DOUBLE_PRINT_RES); + + while (1) { + if (i == 0) { + rem = fmin(9, round( fmod(unum, 10.0) ) ); //last digit is rounded to correctly handle hidden digits. (last digit is processed first) + } else { + rem = fmod(unum, 10.0); + } + num_buf[i] = (uint8_t)('0' + rem); + + i++; + unum = unum / 10.0; + res = res / 10.0; + if ( (res <= 5.0) && (res > 0.5) ) { + num_buf[i] = (uint8_t)('.'); + i++; + } + + if ( (unum < 1.0) && (res < 1.0) ) { + break; + } + } + + while (i != 0U) { + i--; + (void)console_putc(num_buf[i]); + count++; + }; + + return count; +} + +static uint32_t uint32_print(uint32_t num) +{ + uint8_t num_buf[10]; + uint32_t count = 0U; + uint32_t i = 0U; + uint32_t rem; + uint32_t unum = num; + + while (1) { + rem = unum % 10U; + num_buf[i] = (uint8_t)('0' + rem); + + i++; + unum = unum / 10U; + if (unum < 1U) { + break; + } + } + + while (i != 0U) { + i--; + (void)console_putc(num_buf[i]); + count++; + }; + + return count; +} + + +static uint32_t int32_print(int32_t num) +{ + uint32_t unum; + uint32_t count = 0U; + + if (num < 0) { + (void)console_putc((uint8_t)'-'); + count = 1U; + unum = (uint32_t)-num; + } else { + unum = (uint32_t)num; + } + + count += uint32_print(unum); + + return count; +} + + +static uint32_t uint32_hex_print(uint32_t num) +{ + uint32_t i; + uint32_t count = 0U; + uint8_t c; + + for (i = 0U; i < 8U; i++) { + /* 0-F */ + c = (uint8_t)((num >> ((7U - i) * 4U)) & 0x0FU); + if (c >= 0x0AU) { + /* A-F */ + c += (uint8_t)('a' - 0x0AU); + } else { + /* 0-9 */ + c += (uint8_t)'0'; + } + (void)console_putc(c); + count++; + } + + return count; +} + + +static uint32_t uint8_hex_print(uint8_t num) +{ + uint32_t i; + uint32_t count = 0U; + uint8_t c; + + for (i = 0U; i < 2U; i++) { + /* 0-F */ + c = ((num >> ((1U - i) * 4U)) & 0x0FU); + if (c >= 0x0AU) { + /* A-F */ + c += (uint8_t)('a' - 0x0AU); + } else { + /* 0-9 */ + c += (uint8_t)'0'; + } + (void)console_putc(c); + count++; + } + + return count; +} + + +static uint32_t str_print(const char *str) +{ + uint32_t count = 0; + + while (*str != NULL_CHAR) { + (void)console_putc((uint8_t)*str); + str++; + count++; + } + + return count; +} + + +void log_printf(const char *fmt, ...) +{ + va_list args; + double dnum; + int32_t num; + uint32_t unum; + char *str; + uint32_t count = 0U; + + va_start(args, fmt); + while (*fmt != NULL_CHAR) { + if (*fmt == '%') { + fmt++; + switch (*fmt) { + case 'i': + /* No break */ + case 'd': + num = va_arg(args, int32_t); + count += int32_print(num); + break; + case 's': + str = va_arg(args, char *); + count += str_print(str); + break; + case 'x': + unum = va_arg(args, uint32_t); + count += uint32_hex_print(unum); + break; + case 'b': + unum = (uint8_t)va_arg(args, uint32_t); + count += uint8_hex_print(unum); + break; + case 'u': + unum = va_arg(args, uint32_t); + count += uint32_print(unum); + break; + case 'f': + dnum = va_arg(args, double); + count += double_print(dnum); + break; + default: + break; + } + } else { + (void)console_putc((uint8_t)*fmt); + count++; + } + fmt++; + } + va_end(args); +} diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/common/log/scif.c b/IPL/Customer/Mobis/V4H_Cx_Loader/common/log/scif.c new file mode 100644 index 0000000..866fddb --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/common/log/scif.c @@ -0,0 +1,172 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ +/******************************************************************************* + * DESCRIPTION : SCIF driver + ******************************************************************************/ +/****************************************************************************** + * @file scif.c + * - Version : 0.07 + * @brief 1. Initial setting of SCIF. + * 2. Initial setting of HSCIF. + * 3. Log output function. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Modify the timing of MODEMR judgement. + * : 15.10.2021 0.03 Modify register access to read modify write. + * : 03.12.2021 0.04 Fix incorrect configuration process. + * : 06.01.2022 0.05 Static analysis support + * : 16.06.2022 0.06 Change line feed code + * : 31.10.2022 0.07 License notation change. + *****************************************************************************/ + +#include +#include +#include +#include +#include + +/* Define */ +#define SCIF_SCFSR_TEND (uint16_t)((uint16_t)1U << 6U) +#define SCIF_SCFSR_TDFE (uint16_t)((uint16_t)1U << 5U) +#define TRANS_END_CHECK (uint16_t)(SCIF_SCFSR_TEND | SCIF_SCFSR_TDFE) + + +static void (*rcar_putc)(uint8_t outchar); + +static void scif_console_init(uint32_t modemr); +static void scif_console_putc(uint8_t outchar); +static void hscif_console_putc(uint8_t outchar); + + +static void scif_console_init(uint32_t modemr) +{ + switch(modemr) + { + case MODEMR_HSCIF_DLMODE_3000000: + { + /* Set the pointer to a function that outputs one character. */ + rcar_putc = hscif_console_putc; + break; + } + case MODEMR_HSCIF_DLMODE_1843200: + { + /* Set the pointer to a function that outputs one character. */ + rcar_putc = hscif_console_putc; + break; + } + case MODEMR_HSCIF_DLMODE_921600: + { + /* Set the pointer to a function that outputs one character. */ + rcar_putc = hscif_console_putc; + break; + } + case MODEMR_SCIF_DLMODE: + default: + { + /* Set the pointer to a function that outputs one character. */ + rcar_putc = scif_console_putc; + break; + } + } +} +/* End of function scif_console_init(void) */ + +void scif_init(void) +{ + uint32_t modemr; + +#ifdef FORCE_115200 /* force to serial speed to 115200 bps */ +#define _MODE31 (0xEB22FFF0) /* Gen4_ICUMX_loader at RT-VRAM */ +#define _MODE_115200 0x00115200 + modemr = mem_read32(_MODE31); + if (modemr == _MODE_115200) + modemr = MODEMR_SCIF_DLMODE; + else +#endif + { + modemr = ((mem_read32(RST_MODEMR0) & RST_MODEMR0_MD31) >> 31U); + modemr |= ((mem_read32(RST_MODEMR1) & RST_MODEMR1_MD32) << 1U); + } + scif_console_init(modemr); +} +/* End of function scif_init(void) */ + +void console_putc(uint8_t outchar) +{ + if (outchar == 0x0A) /* \n */ + { + rcar_putc( 0x0D ); /* \r */ + } + rcar_putc(outchar); +} +/* End of function console_putc(void) */ + + +static void scif_console_putc(uint8_t outchar) +{ + uint16_t reg; + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK)) + { + ; + } + + mem_write8(SCIF_SCFTDR, outchar); /* Transfer one character */ + reg = mem_read16(SCIF_SCFSR); + reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */ + mem_write16(SCIF_SCFSR, reg); + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK)) + { + ; + } +} +/* End of function scif_console_putc(uint8_t outchar) */ + +static void hscif_console_putc(uint8_t outchar) +{ + uint16_t reg; + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK)) + { + ; + } + + mem_write8(HSCIF_HSFTDR, outchar); /* Transfer one character */ + reg = mem_read16(HSCIF_HSFSR); + reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */ + mem_write16(HSCIF_HSFSR, reg); + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK)) + { + ; + } +} +/* End of function hscif_console_putc(uint8_t outchar) */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/common/scmt_checkpoint.c b/IPL/Customer/Mobis/V4H_Cx_Loader/common/scmt_checkpoint.c new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/common/string.c b/IPL/Customer/Mobis/V4H_Cx_Loader/common/string.c new file mode 100644 index 0000000..e8fb474 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/common/string.c @@ -0,0 +1,84 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Standard library + ******************************************************************************/ +/****************************************************************************** + * @file string.c + * - Version : 0.01 + * @brief standard library. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 04.04.2023 0.01 First Release + *****************************************************************************/ + +#include +#include +#include + +void *memcpy(void *dst, const void *src, size_t len) +{ + uint8_t *p1 = (uint8_t *)dst; + const uint8_t *p2 = (const uint8_t *)src; + while(len > 0U) + { + *(p1++) = *(p2++); + len--; + } + return dst; +} +/* End of function memcpy( void* dst, const void* src, size_t n ) */ + +void *memset(void *dst, int val, size_t len) +{ + uint8_t *p = (uint8_t *)dst; + const uint8_t uc = (uint8_t)val; + + while (len > 0U) + { + *p++ = uc; + len--; + } + return (dst); +} +/* End of function memset(void *dst, int val, size_t len) */ + +/** + * memcmp - Compare two areas of memory + * @cs: One area of memory + * @ct: Another area of memory + * @count: The size of the area. + */ +int memcmp(const void * cs, const void * ct, size_t count) +{ + const unsigned char *su1, *su2; + int res = 0; + + for( su1 = cs, su2 = ct; 0 < count; ++su1, ++su2, count--) + if ((res = *su1 - *su2) != 0) + break; + return res; +} diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/common/timer/generic_timer.c b/IPL/Customer/Mobis/V4H_Cx_Loader/common/timer/generic_timer.c new file mode 100644 index 0000000..6075807 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/common/timer/generic_timer.c @@ -0,0 +1,177 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + +/******************************************************************************* + * DESCRIPTION : generic timer + ******************************************************************************/ +/****************************************************************************** + * @file generic_timer.c + * - Version : 0.08 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 19.01.2022 0.01 First Release + * : 17.02.2022 0.02 Support AArch32 + * : 09.05.2022 0.03 Supports argument check of micro_wait() + * Moved the definition of the define value + * Removed __ARM_ARCH_8R__ and __ARM_ARCH_8A__ + * Change macro to inline function + * Added initial settings + * Remove unnecessary casts + * Change the value of RCAR_CNTC_EXTAL + * : 16.06.2022 0.04 Change the value of RCAR_CNTC_EXTAL + * : 16.06.2022 0.05 Change log output + * : 31.10.2022 0.06 License notation change. + * : 04.04.2023 0.07 Removed stdio.h. + * : 21.08.2023 0.08 Add support for V4M. + *****************************************************************************/ + +#include +#include +#include +#include + +#if (RCAR_LSI == RCAR_S4) +#define RCAR_CNTC_EXTAL (16666666U) /* 16.666666MHz */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define RCAR_CNTC_EXTAL (16666600U) /* 16.666600MHz */ +#endif /* RCAR_LSI == RCAR_S4 */ +#define CNTFID_OFF (0x0020U) +#define CNTCR_OFF (0x0000U) +#define CNTCR_EN ((1U) << 0U) +#define RCAR_CNTC_BASE (0xE6080000U) +#define RCAR_CONV_MICROSEC (1000000U) +#define RCAR_MAX_WAITTIME (10000000U) +#define RCAR_MIN_WAITTIME (0U) + +#ifdef __aarch64__ +static inline uint64_t get_cntfrq(void) +{ + uint64_t freq; + __asm__ volatile ("mrs %0, cntfrq_el0" : "=r" (freq)); + + return(freq); +} + +static inline void set_cntfrq(uint64_t reg_cntfid) +{ + __asm__ volatile ("msr cntfrq_el0, %0" :: "r" (reg_cntfid)); +} + +static inline uint64_t get_cntpct(void) +{ + uint64_t base_count; + __asm__ volatile ("mrs %0, cntpct_el0" : "=r" (base_count)); + + return(base_count); +} + +#elif __arm__ +static inline uint32_t get_cntfrq(void) +{ + uint32_t freq; + __asm__ volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); + + return(freq); +} + +static inline void set_cntfrq(uint32_t reg_cntfid) +{ + __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (reg_cntfid)); +} + +static inline uint64_t get_cntpct(void) +{ + uint64_t base_count; + __asm__ volatile ("mrrc p15, 0, %Q0, %R0, c14" : "=r" (base_count)); + + return(base_count); +} +#endif /* __aarch64__ */ + +void generic_timer_init(void) +{ + /* Update memory mapped and register based freqency */ + /* AArch64:cntfrq_el0 */ + /* AArch32:cntfrq */ + set_cntfrq(RCAR_CNTC_EXTAL); + + mem_write32(RCAR_CNTC_BASE + CNTFID_OFF, RCAR_CNTC_EXTAL); + + /* Enable counter */ + mem_bitset32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_EN); +} +/* End of function generic_timer_init(void) */ + +void micro_wait(uint64_t micro_sec) +{ + uint64_t base_count = 0U; + uint64_t get_count = 0U; + uint64_t wait_time = 0U; +#ifdef __aarch64__ + uint64_t freq = 0U; +#elif __arm__ + uint32_t freq = 0U; +#endif /* __aarch64__ */ + + + if((micro_sec > RCAR_MIN_WAITTIME) && (micro_sec <= RCAR_MAX_WAITTIME)) + { + /* AArch64:cntfrq_el0 */ + /* AArch32:cntfrq */ + freq = get_cntfrq(); + /* AArch64:cntpct_el0 */ + /* AArch32:cntpct */ + base_count = get_cntpct(); + + micro_sec *= freq; + while (micro_sec > wait_time) + { + /* cntpct */ + get_count = get_cntpct(); + + /* INT30-C Pre confirmation */ + if (get_count < base_count) + { + ERROR("micro_wait(Timer value error!!).\n"); + panic; + } + else + { + wait_time = ((get_count - base_count) * RCAR_CONV_MICROSEC); + } + } + } + else + { + ERROR("micro_wait(wait time)\n"); + ERROR("wait time = 0x%x\n", (unsigned int)micro_sec); + panic; + } + +} +/* End of function micro_wait(uint64_t micro_sec) */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/common/timer/scmt.c b/IPL/Customer/Mobis/V4H_Cx_Loader/common/timer/scmt.c new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/cpu_on/cpu_on.c b/IPL/Customer/Mobis/V4H_Cx_Loader/cpu_on/cpu_on.c new file mode 100644 index 0000000..ea9c24a --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/cpu_on/cpu_on.c @@ -0,0 +1,304 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Power management driver + ******************************************************************************/ +/****************************************************************************** + * @file cpu_on.c + * - Version : 0.12 + * @brief 1. Boot process of ARM CPU core. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 17.02.2022 0.01 First Release + * : 25.02.2022 0.02 Changed to boot Cortex-R on Core 0. + * : 23.03.2022 0.03 Removed unnecessary header file inclusions + * : 09.05.2022 0.04 Removed unnecessary processing + * Removed unnecessary cast + * : 31.10.2022 0.05 License notation change. + * : 21.08.2023 0.06 Add support for V4M. + * : 16.11.2023 0.07 Changed not to execute ASPREG setting + * in case of V4M. + * : 10.09.2024 0.08 Updated Region ID and RAM protection setting + * for QNX. + * : 11.10.2024 0.09 Updated Region ID and RAM protection setting + * for QNX for V4M. + * : 09.12.2024 0.10 Updated OTP_MEM_OTPMONITOR60 register to + * OTP_MEM_OTPMONITOR17 register for V4M. + * And Improve the adj_ca_variant_freq function. + * : 19.12.2024 0.11 Add support for booting CR52 core2. + * : 18.03.2025 0.12 Add INTC initialization process. + *****************************************************************************/ + +#include +#include +#include +#include +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#include "access_protection.h" +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ +#include + + +/* ARM */ +#define CA_CORE0_WUP_REQ (0x00000001U) +#define CA_CORE0_VLD_RVBARP (0x00000001U) +#define CR_BTMD_RBAR (0x00000000U) +#define CR_VLD_BARP (0x00000001U << 0U) +#define CR_BAREN_VALID (0x00000001U << 4U) +#define CRRST (0x00000000U) + +#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 (0x00000001U << 1U) +#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0 (0x00000001U << 0U) +#define AP_CORE_APSREG_CCI500_AUX_ACTDIS (0x00000001U << 0U) +#define AP_CORE_APSREG_P_CCI500_AUX_ASPRTM (0x00000001U << 1U) + +/* APMU */ +#define APMU_BASE (BASE_APMU_ADDR) +#define CORTEX_R_CORE (0U) /* Target Cortex R52 cores (0 to 2) */ +#define APMU_CRRSTCTRL(n) (APMU_BASE + ((n) * 0x40U) + 0x0304U) /* Cortex-R Reset Control Register */ +#define APMU_CRBARP(n) (APMU_BASE + ((n) * 0x40U) + 0x033CU) /* Cortex-R Boot Address Register Protected */ + +#define APMU_PWRCTRLC0 (APMU_BASE + 0x0800U) /* Power Control Register for Core 0 */ +#define APMU_RVBARPLC0 (APMU_BASE + 0x0838U) /* Reset Vector Base Address Register Protected Low for Core 0 */ +#define APMU_RVBARPHC0 (APMU_BASE + 0x083CU) /* Reset Vector Base Address Register Protected High for Core 0 */ + +#define AP_CORE_BASE (BASE_AP_CORE_ADDR) /* 0xE6280000 */ + +#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0(x) (AP_CORE_BASE + 0x00000010U + ((uint8_t)(x) * 0x1000U)) +#define AP_CORE_APSREG_CCI500_AUX (AP_CORE_BASE + 0x00009010U) +#define AP_CORE_APSREG_P_CCI500_AUX (AP_CORE_BASE + 0x00029010U) + +#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT (AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 | AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0) + +#if (RCAR_LSI == RCAR_V4H) +#define V4H_5_NI_CA (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */ +#define V4H_3_NI_CA (0x5FU) /* 1600[MHz] = 50/3[MHz] x (0x5F + 0x1) */ +#elif (RCAR_LSI == RCAR_V4M) +#define V4M_5_NI_CA (0x5FU) /* 3200/4[MHz] = 50/3[MHz] x (0x5F + 0x1) */ +#define V4M_3_NI_CA (0x6FU) /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */ +#define V4M_2_NI_CA (0x6FU) /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */ +#endif /* RCAR_LSI == RCAR_V4H */ + +#define CPG_PLL2CR0_KICK_BIT (0x80000000U) +#define CPG_PLLECR_PLL2ST_BIT (0x00000200U) + +#if (RCAR_LSI == RCAR_V4M) +#define CPG_BASE (BASE_CPG_ADDR) +#define CPG_SRSTCLR5 (CPG_BASE + 0x2C94U) +#define CPG_SRSTCLR11 (CPG_BASE + 0x2CACU) +#define CPG_MSTPCR5 (CPG_BASE + 0x2D14U) +#define CPG_SRSTCLR5_VAL (0x80000000U) +#define CPG_SRSTCLR11_VAL (0x00080000U) +#define CPG_MSTPCR5_VAL (0x80000000U) + +static void intc_init(void); +#endif /* RCAR_LSI == RCAR_V4M */ + +static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr, int n) +{ + if(RCAR_PWR_TARGET_CR == target) + { + /* CR Boot address set */ + mem_write32(APMU_CRBARP(n), (uint32_t)(boot_addr | CR_VLD_BARP)); + mem_write32(APMU_CRBARP(n), (uint32_t)(boot_addr | CR_VLD_BARP | CR_BAREN_VALID)); + } + else + { + /* CA Boot address set */ + mem_write32(APMU_RVBARPLC0, boot_addr | CA_CORE0_VLD_RVBARP); +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + mem_write32(APMU_RVBARPHC0, 0x00000020U); /* CA boot address 0x20_XXXXXXXX */ +#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE) + mem_write32(APMU_RVBARPHC0, 0x00000000U); +#endif +#else + mem_write32(APMU_RVBARPHC0, 0x00000000U); +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + } +} +/* End of function arm_cpu_set_address(uint32_t target, uint32_t boot_addr) */ + +void arm_cpu_on(uint32_t target, uint32_t boot_addr, int core_id) +{ + uint32_t res_data; + + if(RCAR_PWR_TARGET_CR == target) + { + if (core_id < 0) + core_id = CORTEX_R_CORE; + + NOTICE("enable CR-52 core %d\n", core_id); + + /* CR Boot address set. */ + arm_cpu_set_address(target, boot_addr, core_id); + + /* CR reset. */ + mem_write32(APMU_CRRSTCTRL(core_id), CRRST); + } + else + { +#if (RCAR_LSI == RCAR_V4M) + /* For the initial setting flow of INTC, see Section 15.4.5 in + * "R-Car Series, V4M Series User's Manual". + */ + /* INTC initialize */ + intc_init(); +#endif /* RCAR_LSI == RCAR_V4M */ + + /* CA Boot address set. */ + arm_cpu_set_address(target, boot_addr, 0); + +#if (RCAR_LSI == RCAR_V4H) + /* + * In case of V4M, doesn't execute following process at Cx 2nd IPL. + * Because following register setting is needed to execute before C4 power on. + */ + /* AP-System core initialize */ + res_data = mem_read32(AP_CORE_APSREG_AP_CLUSTER_N_AUX0(0U)); + res_data |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT; + mem_write32(AP_CORE_APSREG_AP_CLUSTER_N_AUX0(0U), res_data); + + res_data = mem_read32(AP_CORE_APSREG_CCI500_AUX); + res_data |= AP_CORE_APSREG_CCI500_AUX_ACTDIS; + mem_write32(AP_CORE_APSREG_CCI500_AUX, res_data); + /* AP_CORE_APSREG_P_CCI500_AUX setting is only for V4H. */ + res_data = mem_read32(AP_CORE_APSREG_P_CCI500_AUX); + res_data |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM; + mem_write32(AP_CORE_APSREG_P_CCI500_AUX, res_data); +#endif /* RCAR_LSI == RCAR_V4H */ + /* CA core0 wake up sequence. */ + mem_write32(APMU_PWRCTRLC0, CA_CORE0_WUP_REQ); + /* Wait until CA core0 wake up sequence finished. */ + do + { + res_data = mem_read32(APMU_PWRCTRLC0); + }while(CA_CORE0_WUP_REQ & res_data); + } +} +/* End of function arm_cpu_on(uint32_t target, uint32_t boot_addr) */ + +void adj_ca_variant_freq(void) +{ + uint32_t product = mem_read32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK; + uint32_t pll2_freq = mem_read32(CPG_PLL2CR0); + +#if (RCAR_LSI == RCAR_V4H) + /* Set the CPU frequency division ratio according to the type of variant. */ + switch (product) + { + case VARIANT_V4H_7: + /* Default value, do nothing */; + break; + case VARIANT_V4H_5: + pll2_freq = (pll2_freq & ~(0xFFU << 20U)); + pll2_freq = (pll2_freq | (V4H_5_NI_CA << 20U)); + break; + case VARIANT_V4H_3: + pll2_freq = (pll2_freq & ~(0xFFU << 20U)); + pll2_freq = (pll2_freq | (V4H_3_NI_CA << 20U)); + break; + default: + ; /* Do nothing */ + break; + } + + if (VARIANT_V4H_5 == product || VARIANT_V4H_3 == product) + { + /* Write Division value to FRQCRC0 register */ + mem_write32(CPG_CPGWPR, ~(pll2_freq)); + mem_write32(CPG_PLL2CR0, pll2_freq); + + mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT)); + mem_write32(CPG_PLL2CR0, (mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT)); + + while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL2ST_BIT) != CPG_PLLECR_PLL2ST_BIT) + { + ; + } + } +#elif (RCAR_LSI == RCAR_V4M) + /* Set the CPU frequency division ratio according to the type of variant. */ + switch (product) + { + case VARIANT_V4M_7: + /* Default value, do nothing */; + break; + case VARIANT_V4M_5: + pll2_freq = (pll2_freq & ~(0xFFU << 20U)); + pll2_freq = (pll2_freq | (V4M_5_NI_CA << 20U)); + break; + case VARIANT_V4M_3: + pll2_freq = (pll2_freq & ~(0xFFU << 20U)); + pll2_freq = (pll2_freq | (V4M_3_NI_CA << 20U)); + break; + case VARIANT_V4M_2: + pll2_freq = (pll2_freq & ~(0xFFU << 20U)); + pll2_freq = (pll2_freq | (V4M_2_NI_CA << 20U)); + break; + default: + ; /* Do nothing */ + break; + } + + if (VARIANT_V4M_5 == product || VARIANT_V4M_3 == product || VARIANT_V4M_2 == product) + { + /* Write Division value to FRQCRC0 register */ + mem_write32(CPG_CPGWPR, ~(pll2_freq)); + mem_write32(CPG_PLL2CR0, pll2_freq); + + mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT)); + mem_write32(CPG_PLL2CR0, (mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT)); + + while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL2ST_BIT) != CPG_PLLECR_PLL2ST_BIT) + { + ; + } + } +#endif /* RCAR_LSI == RCAR_V4H */ +} +/* End of function adj_cpu_variant_freq(void) */ + +#if (RCAR_LSI == RCAR_V4M) +static void intc_init(void) +{ + uint32_t reg; + + mem_write32(CPG_CPGWPR, ~(CPG_SRSTCLR5_VAL)); + mem_write32(CPG_SRSTCLR5, CPG_SRSTCLR5_VAL); + + mem_write32(CPG_CPGWPR, ~(CPG_SRSTCLR11_VAL)); + mem_write32(CPG_SRSTCLR11, CPG_SRSTCLR11_VAL); + + mem_write32(CPG_CPGWPR, ~(CPG_MSTPCR5_VAL)); + reg = mem_read32(CPG_MSTPCR5); + reg |= CPG_MSTPCR5_VAL; + mem_write32(CPG_MSTPCR5, reg); +} +/* End of function intc_init(void) */ +#endif /* RCAR_LSI == RCAR_V4M */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/image_load/android_ab.c b/IPL/Customer/Mobis/V4H_Cx_Loader/image_load/android_ab.c new file mode 100644 index 0000000..6687b6e --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/image_load/android_ab.c @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: BSD-2-Clause +/* + * Copyright (C) 2017 The Android Open Source Project + */ +// #include +#include +#include +// #include +#include +// #include +#include +// #include +// #include +// #include +#include +// #include +#include + +#include +#include +#include +typedef unsigned long int ulong; +typedef uint32_t u32; +#define typeof(x) __typeof__(x) +#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +volatile uint8_t *_disk_buffer = (volatile uint8_t *)DISK_BUFFER_ADDR; + +/** + * Compute the CRC-32 of the bootloader control struct. + * + * Only the bytes up to the crc32_le field are considered for the CRC-32 + * calculation. + * + * @param[in] abc bootloader control block + * + * @return crc32 sum + */ +static uint32_t ab_control_compute_crc(struct bootloader_control *abc) +{ + return crc32(0, (void *)abc, offsetof(typeof(*abc), crc32_le)); +} + +/** + * Initialize bootloader_control to the default value. + * + * It allows us to boot all slots in order from the first one. This value + * should be used when the bootloader message is corrupted, but not when + * a valid message indicates that all slots are unbootable. + * + * @param[in] abc bootloader control block + * + * @return 0 on success and a negative on error + */ +static int ab_control_default(struct bootloader_control *abc) +{ + int i; + const struct slot_metadata metadata = { + .priority = 15, + .tries_remaining = 7, + .successful_boot = 0, + .verity_corrupted = 0, + .reserved = 0 + }; + + if (!abc) + return -EFAULT; + + memcpy(abc->slot_suffix, "a\0\0\0", 4); + abc->magic = BOOT_CTRL_MAGIC; + abc->version = BOOT_CTRL_VERSION; + abc->nb_slot = NUM_SLOTS; + memset(abc->reserved0, 0, sizeof(abc->reserved0)); + for (i = 0; i < abc->nb_slot; ++i) + abc->slot_info[i] = metadata; + + memset(abc->reserved1, 0, sizeof(abc->reserved1)); + abc->crc32_le = ab_control_compute_crc(abc); + + return 0; +} + +/** + * Load the boot_control struct from disk into newly allocated memory. + * + * This function allocates and returns an integer number of disk blocks, + * based on the block size of the passed device to help performing a + * read-modify-write operation on the boot_control struct. + * The boot_control struct offset (2 KiB) must be a multiple of the device + * block size, for simplicity. + * + * @param[in] dev_desc Device where to read the boot_control struct from + * @param[in] part_info Partition in 'dev_desc' where to read from, normally + * the "misc" partition should be used + * @param[out] pointer to pointer to bootloader_control data + * @return 0 on success and a negative on error + */ +static int ab_control_create_from_disk( + // struct blk_desc *dev_desc, + // const struct disk_partition *part_info, + struct bootloader_control **abc) +{ + // ulong abc_offset, abc_blocks, ret; + + // abc_offset = offsetof(struct bootloader_message_ab, slot_suffix); + // if (abc_offset % CX_EMMC_SECTOR_SIZE) { + // ERROR("Boot control block not block aligned.\n"); + // return -EINVAL; + // } + // abc_offset /= CX_EMMC_SECTOR_SIZE; + + // abc_blocks = DIV_ROUND_UP(sizeof(struct bootloader_control), + // CX_EMMC_SECTOR_SIZE); + // if (abc_offset + abc_blocks > part_info->size) { + // ERROR("boot control partition too small. Need at" + // " least %lu blocks but have %lu blocks.\n", + // abc_offset + abc_blocks, part_info->size); + // return -EINVAL; + // } + // *abc = malloc_cache_aligned(abc_blocks * CX_EMMC_SECTOR_SIZE); + // if (!*abc) + // return -ENOMEM; + + // [ab_control_create_from_disk:112] start 0x3f800(260096), abc_offset(0x4,4), blocks 1 + // ret = blk_dread(dev_desc, part_info->start + abc_offset, abc_blocks, + // *abc); + uint32_t rtn_val = EMMC_DEV_ERR; + +#define CX_EMMC_MISC_PART 0 // user partition +#define CX_EMMC_MISC_START 0x3F800 // 127MB in user partition +#define CX_EMMC_AB_CONTROL (CX_EMMC_MISC_START + 4) +#define CX_EMMC_AB_SIZE (1) + rtn_val = emmc_trans_data(CX_EMMC_MISC_PART, (uintptr_t)(CX_EMMC_AB_CONTROL), + (uintptr_t)_disk_buffer, CX_EMMC_AB_SIZE); + if(EMMC_DEV_OK != rtn_val) + { + ERROR("Could not read from boot ctrl partition\n"); + *abc = NULL; + return -EIO; + } + + *abc = (struct bootloader_control *)_disk_buffer; + return 0; +} + +/** + * Store the loaded boot_control block. + * + * Store back to the same location it was read from with + * ab_control_create_from_misc(). + * + * @param[in] dev_desc Device where we should write the boot_control struct + * @param[in] part_info Partition on the 'dev_desc' where to write + * @param[in] abc Pointer to the boot control struct and the extra bytes after + * it up to the nearest block boundary + * @return 0 on success and a negative on error + */ +// static int ab_control_store(struct blk_desc *dev_desc, +// const struct disk_partition *part_info, +// struct bootloader_control *abc) +// { +// ulong abc_offset, abc_blocks, ret; + +// abc_offset = offsetof(struct bootloader_message_ab, slot_suffix) / +// part_info->blksz; +// abc_blocks = DIV_ROUND_UP(sizeof(struct bootloader_control), +// part_info->blksz); +// ret = blk_dwrite(dev_desc, part_info->start + abc_offset, abc_blocks, +// abc); +// if (IS_ERR_VALUE(ret)) { +// log_err("ANDROID: Could not write back the misc partition\n"); +// return -EIO; +// } + +// return 0; +// } + +/** + * Compare two slots. + * + * The function determines slot which is should we boot from among the two. + * + * @param[in] a The first bootable slot metadata + * @param[in] b The second bootable slot metadata + * @return Negative if the slot "a" is better, positive of the slot "b" is + * better or 0 if they are equally good. + */ +static int ab_compare_slots(const struct slot_metadata *a, + const struct slot_metadata *b) +{ + /* Higher priority is better */ + if (a->priority != b->priority) + return b->priority - a->priority; + + /* Higher successful_boot value is better, in case of same priority */ + if (a->successful_boot != b->successful_boot) + return b->successful_boot - a->successful_boot; + + /* Higher tries_remaining is better to ensure round-robin */ + if (a->tries_remaining != b->tries_remaining) + return b->tries_remaining - a->tries_remaining; + + return 0; +} + +int ab_select_slot( + // struct blk_desc *dev_desc, struct disk_partition *part_info + void +) +{ + struct bootloader_control *abc = NULL; + u32 crc32_le; + int slot, i, ret; + bool store_needed = false; + char slot_suffix[4]; + + mem_write32(AB_INFO_FLAG_ADDR, AB_INFO_FLAG_INIT); + ret = ab_control_create_from_disk(/*dev_desc, part_info,*/ &abc); + if (ret < 0) { + /* + * This condition represents an actual problem with the code or + * the board setup, like an invalid partition information. + * Signal a repair mode and do not try to boot from either slot. + */ + return ret; + } + + crc32_le = ab_control_compute_crc(abc); + if (abc->crc32_le != crc32_le) { + ERROR("Invalid CRC-32 (expected %.8x, found %.8x)," + "re-initializing A/B metadata.\n", crc32_le, abc->crc32_le); + + ret = ab_control_default(abc); + if (ret < 0) { + // free(abc); + return -ENODATA; + } + store_needed = true; + } + + if (abc->magic != BOOT_CTRL_MAGIC) { + ERROR("Unknown A/B metadata: %.8x\n", abc->magic); + // free(abc); + return -ENODATA; + } + + if (abc->version > BOOT_CTRL_VERSION) { + ERROR("Unsupported A/B metadata version: %.8x\n", abc->version); + // free(abc); + return -ENODATA; + } + + /* + * At this point a valid boot control metadata is stored in abc, + * followed by other reserved data in the same block. We select a with + * the higher priority slot that + * - is not marked as corrupted and + * - either has tries_remaining > 0 or successful_boot is true. + * If the selected slot has a false successful_boot, we also decrement + * the tries_remaining until it eventually becomes unbootable because + * tries_remaining reaches 0. This mechanism produces a bootloader + * induced rollback, typically right after a failed update. + */ + + /* Safety check: limit the number of slots. */ + if (abc->nb_slot > ARRAY_SIZE(abc->slot_info)) { + abc->nb_slot = ARRAY_SIZE(abc->slot_info); + NOTICE("[%s:%d] abc->nb_slot > ARRAY_SIZE(abc->slot_info)\n", __func__, __LINE__); + store_needed = true; + } + + slot = -1; + for (i = 0; i < abc->nb_slot; ++i) { + if (abc->slot_info[i].verity_corrupted || + !abc->slot_info[i].tries_remaining) { + NOTICE("unbootable slot %d tries: %d, corrupt: %d\n", + i, abc->slot_info[i].tries_remaining, + abc->slot_info[i].verity_corrupted); + continue; + } + NOTICE("bootable slot %d pri: %d, tries: %d, " + "corrupt: %d, successful: %d\n", + i, abc->slot_info[i].priority, + abc->slot_info[i].tries_remaining, + abc->slot_info[i].verity_corrupted, + abc->slot_info[i].successful_boot); + + if (slot < 0 || + ab_compare_slots(&abc->slot_info[i], + &abc->slot_info[slot]) < 0) { + slot = i; + } + } + + if (slot >= 0 && !abc->slot_info[slot].successful_boot) { + ERROR("Attempting slot %d, tries remaining %d\n", + slot, abc->slot_info[slot].tries_remaining); + abc->slot_info[slot].tries_remaining--; + store_needed = true; + } + + if (slot >= 0) { + /* + * Legacy user-space requires this field to be set in the BCB. + * Newer releases load this slot suffix from the command line + * or the device tree. + */ + memset(slot_suffix, 0, sizeof(slot_suffix)); + slot_suffix[0] = BOOT_SLOT_NAME(slot); + if (memcmp(abc->slot_suffix, slot_suffix, + sizeof(slot_suffix))) { + memcpy(abc->slot_suffix, slot_suffix, + sizeof(slot_suffix)); + NOTICE("[%s:%d] slot_suffix is differ\n", __func__, __LINE__); + store_needed = true; + } + } + + if (store_needed) { + abc->crc32_le = ab_control_compute_crc(abc); + // ab_control_store(dev_desc, part_info, abc); + crc32_le = AB_INFO_FLAG_STORE; + } + else + crc32_le = AB_INFO_FLAG_OK; + // free(abc); + if (slot == 1) + crc32_le |= AB_INFO_SELECT_2nd; + mem_write32(AB_INFO_FLAG_ADDR, crc32_le); + + if (slot < 0) + return -EINVAL; + + return slot; +} diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/image_load/image_load.c b/IPL/Customer/Mobis/V4H_Cx_Loader/image_load/image_load.c new file mode 100644 index 0000000..2448924 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/image_load/image_load.c @@ -0,0 +1,494 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file image_load.c + * - Version : 0.11 + * @brief Access protection setting driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.11.2021 0.01 First Release + * : 10.02.2022 0.02 Updated eMMC driver + * Removed the comment + * Change the line feed code of log output + * Change the number of CA programs + * : 17.02.2022 0.03 Support AArch32 + * : 22.03.2022 0.04 Support for GSCE[3.3b] + * : 11.05.2022 0.05 Used the standard library + * Integrated LOAD_INFO + * Changed image_name table + * Changed check_load_area + * - Change RAM check process + * - Change address check process + * - Add Image check process + * - Processing integration + * Changed to processing for each device + * Change structure member name + * Added function return value judgment + * Changed LOGICAL_CONTENT_CERT_ADDR to + * get_logic_cont_cert_addr + * Changed uint32_t to uintptr_t + * Change log output + * Add argument of load_init() + * Change to error when key information is invalid + * Remove unnecessary type conversion + * : 11.07.2022 0.06 Change log output + * Support secure boot for S4 + * Change load start processing other than 512byte align + * : 02.09.2022 0.07 Added 512byte boundary check + * : 31.10.2022 0.08 License notation change. + * : 21.08.2023 0.09 Add support for V4M. + * : 19.12.2024 0.10 Add support for RTOS#1 and RTOS#2. + * : 26.05.2025 0.11 Change key cert address of [CA_OPTIONAL_ID+2]. +*****************************************************************************/ +/* indelude */ +#include +#include +#include +#include + +#include +#include + +#define KEY_SIZE_FLG_MSK (0x00000003U) +#define KEY_SIZE_BIT_SHIFT (21U) +#define CERT_INFO_FLG_OFFSET (0x0000000CU) +#define KEY_SIZE_4096 (0x00000002U) +#define KEY_SIZE_3072 (0x00000001U) +#define KEY_SIZE_2048 (0x00000000U) +#define WORD_TO_BYTE (4U) +#define NOT_OVERLAP_FLAG (0U) +#define OVERLAP_FLAG (1U) +#define RAM_RANGE_OK (0U) +#define RAM_RANGE_NG (1U) +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1) +#define RAM_MAX (4U) +#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RAM_MAX (5U) /* ++ SRAM in RT-VRAM (0xE2000000 - 0xE200FFFF) */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +#define ADDRESS_RANGE_512 (512U) + +static void check_load_area(LOAD_INFO* li); +static void get_info_from_cert(uint32_t cert_addr, uint32_t *size, + uint32_t *dest_addr); + +void load_image(LOAD_INFO* li) +{ + /* log output of load image for information */ + load_image_info_print_for_emmc(li); + + /* Check transfer range of image. */ + check_load_area(li); + + /* Image load start. */ + load_start(li); +} +/* End of function load_image(LOAD_INFO* li) */ + +void load_init(LOAD_INFO* li, uint32_t num) +{ + uint32_t loop; + uintptr_t buf; + + const char *image_name[MAX_PLACED] = { +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + [RTOS_ID] = "RTOS", +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ +#ifdef MOBIS_PRK3 + [CA_OPTIONAL_ID] = "BL31", + [CA_OPTIONAL_ID + 1] = "u-boot", + [CA_OPTIONAL_ID + 2] = "tee OS", + [CA_OPTIONAL_ID + 3] = "BL2", + [CA_OPTIONAL_ID + 4] = "QNX OS", +#else + [CA_OPTIONAL_ID] = "CA Program #1", + [CA_OPTIONAL_ID + 1] = "CA Program #2", + [CA_OPTIONAL_ID + 2] = "CA Program #3", + [CA_OPTIONAL_ID + 3] = "CA Program #4", + [CA_OPTIONAL_ID + 4] = "CA Program #5", +#endif + [CA_OPTIONAL_ID + 5] = "CA Program #6", + [CA_OPTIONAL_ID + 6] = "CA Program #7", + [CA_OPTIONAL_ID + 7] = "CA Program #8", +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + [RTOS1_ID] = "RTOS#1", + [RTOS2_ID] = "RTOS#2", +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + }; + + const uint32_t key_cert[MAX_PLACED] = { +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + [RTOS_ID] = TFMV_KEY_CERT_ADDR, +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + [CA_OPTIONAL_ID] = TFMV_KEY_CERT_ADDR, /* bl31 */ +#if (RCAR_LSI == RCAR_S4) + [CA_OPTIONAL_ID + 1] = TFMV_KEY_CERT_ADDR, +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + [CA_OPTIONAL_ID + 1] = NTFMV_KEY_CERT_ADDR, /* u-boot */ +#endif +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + [CA_OPTIONAL_ID + 2] = NTFMV_KEY_CERT_ADDR, +#else + [CA_OPTIONAL_ID + 2] = TFMV_KEY_CERT_ADDR, /* tee OS */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#if (BL2_LOAD_ENABLE == BL2_DISABLE) + [CA_OPTIONAL_ID + 3] = NTFMV_KEY_CERT_ADDR, +#else + [CA_OPTIONAL_ID + 3] = TFMV_KEY_CERT_ADDR, /* ca76-loader */ +#endif /* BL2_LOAD_ENABLE == BL2_DISABLE */ + [CA_OPTIONAL_ID + 4] = NTFMV_KEY_CERT_ADDR, /* qnx OS */ + [CA_OPTIONAL_ID + 5] = NTFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID + 6] = NTFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID + 7] = NTFMV_KEY_CERT_ADDR, +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + [RTOS1_ID] = TFMV_KEY_CERT_ADDR, + [RTOS2_ID] = TFMV_KEY_CERT_ADDR, +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + }; + + + if (num >= 1U && num <= 8U) + { + /* Set Load info parameter */ + for (loop = CA_OPTIONAL_ID; loop < CA_OPTIONAL_ID + num; loop++) + { + li[loop].name = image_name[loop]; + li[loop].key_cert_addr = key_cert[loop]; + li[loop].cnt_cert_addr = get_logic_cont_cert_addr(loop); + get_info_from_cert(li[loop].cnt_cert_addr, &li[loop].image_size, &li[loop].boot_addr); + buf = get_src_addr_offset_in_cert(loop); + li[loop].src_addr = (SRC_TOP + mem_read32(buf)); + buf = get_part_num_in_cert(loop); + li[loop].part_num = mem_read32(buf); + li[loop].load_id = loop; + } + } + else + { + ERROR("load_init(CA program num error).\n"); + panic; + } + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + li[RTOS_ID].name = image_name[RTOS_ID]; + li[RTOS_ID].key_cert_addr = key_cert[RTOS_ID]; + li[RTOS_ID].cnt_cert_addr = get_logic_cont_cert_addr(RTOS_ID); + get_info_from_cert(li[RTOS_ID].cnt_cert_addr, &li[RTOS_ID].image_size, &li[RTOS_ID].boot_addr); + buf = get_src_addr_offset_in_cert(RTOS_ID); + li[RTOS_ID].src_addr = (SRC_TOP + mem_read32(buf)); + buf = get_part_num_in_cert(RTOS_ID); + li[RTOS_ID].part_num = mem_read32(buf); + li[RTOS_ID].load_id = RTOS_ID; + + #if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + /* Set Load info parameter for RTOS#1 and RTOS#2 */ + for (loop = RTOS1_ID; loop <= RTOS2_ID; loop++) + { + li[loop].name = image_name[loop]; + li[loop].key_cert_addr = key_cert[loop]; + li[loop].cnt_cert_addr = get_logic_cont_cert_addr(loop); + get_info_from_cert(li[loop].cnt_cert_addr, &li[loop].image_size, &li[loop].boot_addr); + buf = get_src_addr_offset_in_cert(loop); + li[loop].src_addr = (SRC_TOP + mem_read32(buf)); + buf = get_part_num_in_cert(loop); + li[loop].part_num = mem_read32(buf); + li[loop].load_id = loop; + } + #endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + +}/* End of function load_init(LOAD_INFO* li) */ + +void load_update_part_num(LOAD_INFO* li, uint32_t num, int slot) +{ + uint32_t loop; + + /* Set Load info parameter */ + for (loop = CA_OPTIONAL_ID; loop < CA_OPTIONAL_ID + num; loop++) + { + li[loop].part_num = (slot == 1) ? 2 : 1; + } + li[RTOS_ID].part_num = (slot == 1) ? 2 : 1; +} + +static void check_load_area(LOAD_INFO* li) +{ + uint32_t src; + uint32_t dst; + uint32_t len; + uint32_t dst_end; + uint32_t overlap; + uint32_t loop; + uint32_t rge_chk_flg; + static uint32_t s_num = 1U; + + /* The memory range of destination. */ + const ADDRESS_RANGE add_list[RAM_MAX] = { + [TARGET_MEM_DRAM] = {DRAM_BASE, DRAM_END}, + [TARGET_MEM_RTSRAM] = {RTSRAM_BASE, RTSRAM_END}, + [TARGET_MEM_RTVRAM] = {RTVRAM_VBUF_TOP, RTVRAM_VBUF_END}, + [TARGET_MEM_SYSRAM] = {SYSRAM_BASE, SYSRAM_END}, +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + [TARGET_MEM_SRAM_IN_RTVRAM] = {RTVRAM_SRAM_TOP, RTVRAM_SRAM_END}, +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + }; + + /* The image range check */ + const IMAGE_RANGE size_list[CA_IMAGESIZECHK_DEF] = { + { CA_PROGRAM1_ID, CA_PROGRAM1_ADR, CA_PROGRAM1_SIZE}, + { CA_PROGRAM2_ID, CA_PROGRAM2_ADR, CA_PROGRAM2_SIZE}, +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) + { CA_PROGRAM3_ID, CA_PROGRAM3_ADR, CA_PROGRAM3_SIZE}, +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ +#if (BL2_LOAD_ENABLE == BL2_ENABLE) + { CA_PROGRAM4_ID, CA_PROGRAM4_ADR, CA_PROGRAM4_SIZE}, +#endif /* BL2_LOAD_ENABLE == BL2_ENABLE */ +#if (QNX_OS_LOAD_ENABLE == QNX_OS_ENABLE) + { CA_PROGRAM5_ID, CA_PROGRAM5_ADR, CA_PROGRAM5_SIZE}, +#endif /* QNX_OS_LOAD_ENABLE == QNX_OS_ENABLE */ + }; + + static ADDRESS_RANGE s_placed_image[MAX_PLACED] = { + [0] = {IPL_TOP, IPL_END} + }; + + + src = li->src_addr; + dst = li->boot_addr; + len = li->image_size; + + /* Check image size */ + if (len == 0U) + { + ERROR("image size error\n"); + panic; + } + + /* Check whether source is overflow */ + /* INT30-C Pre confirmation */ + if (src > (UINT32_MAX - len)) + { + ERROR("1:overflow is occurred at source\n"); + ERROR("1:source address = 0x%x image size = 0x%x\n", (unsigned int)src, (unsigned int)len); + panic; + } + + /* Check whether destination is overflow */ + /* INT30-C Pre confirmation */ + if (dst > (UINT32_MAX - len)) + { + ERROR("1:overflow is occurred at destination\n"); + ERROR("1:destination address = 0x%x image size = 0x%x\n", (unsigned int)dst, + (unsigned int)len); + panic; + } + else + { + dst_end = dst + len - 1U; + } + + /* Check source address range. */ + /* No error check is performed because it is detected by the eMMC device */ + + /* Check destination address range. */ + + /* 512byte boundary check */ + if (0U != (dst % ADDRESS_RANGE_512)) + { + ERROR("check_load_area (destination address)\n"); + ERROR("destination address = 0x%x \n", (unsigned int)dst); + panic; + } + + /* range check */ + rge_chk_flg = RAM_RANGE_NG; + + for(loop = 0U; loop < RAM_MAX; loop++) + { + if (add_list[loop].cx_topadd <= dst) + { + if(dst_end <= add_list[loop].cx_endadd) + { + rge_chk_flg = RAM_RANGE_OK; + break; + } + } + } + + if(rge_chk_flg != RAM_RANGE_OK) + { + ERROR("check_load_area (destination address)\n"); + ERROR("destination address = 0x%x image size = 0x%x\n", (unsigned int)dst, + (unsigned int)len); + panic; + } + + /* Check whether destination is overflow */ + for (loop = 0U; loop < CA_IMAGESIZECHK_DEF; loop++) + { + if (li->load_id == size_list[loop].load_id) + { + if ((size_list[loop].image_adr != 0U) && (dst != size_list[loop].image_adr)) + { + ERROR("check load area.(outside secure area)\n"); + ERROR("destination address = 0x%x(0x%x) image size = 0x%x\n", (unsigned int)dst, + (unsigned int)(size_list[loop].image_adr), (unsigned int)len); + panic; + } + if ((size_list[loop].image_size != 0U) && (len > size_list[loop].image_size)) + { + ERROR("check load area.(outside secure area)\n"); + ERROR("destination address = 0x%x image size = 0x%x(0x%x)\n", (unsigned int)dst, + (unsigned int)len, (unsigned int)(size_list[loop].image_size)); + panic; + } + } + } + + /* Check there are no overlaps the image that will be loaded and + the images that have already loaded. */ + overlap = NOT_OVERLAP_FLAG; + loop = 0U; + do + { + /* check overlap */ + if ((dst >= s_placed_image[loop].cx_topadd) + && (dst <= s_placed_image[loop].cx_endadd)) + { + overlap = OVERLAP_FLAG; + } + else if ((dst_end >= s_placed_image[loop].cx_topadd) + && (dst_end <= s_placed_image[loop].cx_endadd)) + { + overlap = OVERLAP_FLAG; + } + else if ((dst < s_placed_image[loop].cx_topadd) + && (s_placed_image[loop].cx_endadd < dst_end)) + { + overlap = OVERLAP_FLAG; + } + else + { + loop++; + } + } while ((loop < s_num) && (overlap == NOT_OVERLAP_FLAG)); + + /* Check the overlap flag. + Parameter error if overwrite occurred. + Otherwise, add parameters of the image to be loaded into + Placed_image. */ + if (overlap == NOT_OVERLAP_FLAG) + { + s_placed_image[s_num].cx_topadd = dst; + s_placed_image[s_num].cx_endadd = dst_end; + s_num++; + } + else + { + ERROR("check load area (overlap)\n"); + ERROR("destination address = 0x%x image size = 0x%x\n", (unsigned int)dst, (unsigned int)len); + ERROR("overlapped image is [%u]\n", (unsigned int)loop); + ERROR("top address = 0x%x end address = 0x%x\n", + (unsigned int)s_placed_image[loop].cx_topadd, (unsigned int)s_placed_image[loop].cx_endadd); + panic; + } +} +/* End of function check_load_area(uint32_t dst, uint32_t src, uint32_t len) */ + +static void get_info_from_cert(uint32_t cert_addr, uint32_t *size, + uint32_t *dest_addr) +{ + uint32_t val; + uint32_t certInfo1; + uintptr_t pSize; + uintptr_t pDestL; + + /* Get key length of content certificate. */ + val = mem_read32((uintptr_t)cert_addr + CERT_INFO_FLG_OFFSET); + certInfo1 = (val >> KEY_SIZE_BIT_SHIFT) & KEY_SIZE_FLG_MSK; + + /* Get the transfer address and transfer size from + the certificate in accordance with the key length. */ + if (KEY_SIZE_4096 == certInfo1) /* key size = 4096 */ + { + pSize = cert_addr + CERT_INFO_SIZE_OFFSET2; + *size = mem_read32(pSize) * WORD_TO_BYTE; + pDestL = cert_addr + CERT_INFO_DST_OFFSET2; + *dest_addr = mem_read32(pDestL); + } + else if (KEY_SIZE_3072 == certInfo1) /* key size = 3072 */ + { + pSize = cert_addr + CERT_INFO_SIZE_OFFSET1; + *size = mem_read32(pSize) * WORD_TO_BYTE; + pDestL = cert_addr + CERT_INFO_DST_OFFSET1; + *dest_addr = mem_read32(pDestL); + } + else if (KEY_SIZE_2048 == certInfo1) /* key size = 2048 */ + { + pSize = cert_addr + CERT_INFO_SIZE_OFFSET; + *size = mem_read32(pSize) * WORD_TO_BYTE; + pDestL = cert_addr + CERT_INFO_DST_OFFSET; + *dest_addr = mem_read32(pDestL); + } + else + { + ERROR("get_info_from_cert key size error.\n"); + panic; + } +} +/* End of function get_info_from_cert(uint32_t cert_addr, uint32_t *size, uint32_t *dest_addr) */ + +void load_start(LOAD_INFO* li) +{ + uint32_t rtn_val = EMMC_DEV_ERR; + uint32_t sector_count; + uint32_t fraction; + + /* Converted to number of sectors transferred. */ + sector_count = li->image_size >> CX_EMMC_SECTOR_SIZE_SHIFT; + + fraction = li->image_size % CX_EMMC_SECTOR_SIZE; + /* Add 1 if there is a fraction */ + if(0U != fraction) + { + sector_count += 1U; + } + + rtn_val = emmc_trans_data(li->part_num, (uintptr_t)(li->src_addr >> CX_EMMC_SECTOR_SIZE_SHIFT), + (uintptr_t)li->boot_addr, sector_count); + + if(EMMC_DEV_OK != rtn_val) + { + ERROR("load_start(emmc_trans_data error).\n"); + panic; + } +} +/* End of function load_start(LOAD_INFO* li) */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/access_protection.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/access_protection.h new file mode 100644 index 0000000..222ccf9 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/access_protection.h @@ -0,0 +1,37 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2022-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Region ID function header + ******************************************************************************/ + +#ifndef REGION_ID_H__ +#define REGION_ID_H__ + +#define PROTECTION_DISABLE (0U) +#define PROTECTION_ENABLE (1U) + +void rgid_protection_check(void); +void ram_protection_check(void); + +#endif /* REGION_ID_H__ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/android_ab.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/android_ab.h new file mode 100644 index 0000000..36b7af8 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/android_ab.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (C) 2017 The Android Open Source Project + */ + +#ifndef __ANDROID_AB_H +#define __ANDROID_AB_H + +// struct blk_desc; +// struct disk_partition; + +/* Android standard boot slot names are 'a', 'b', 'c', ... */ +#define BOOT_SLOT_NAME(slot_num) ('a' + (slot_num)) + +/* Number of slots */ +#define NUM_SLOTS 2 + +/* CX_EMMC_AB_CONTROL from icumx_IPL */ +#define DISK_BUFFER__IPL (0xEB22E000U) +#define DISK_BUFFER_ADDR (0x41DFE000U) + +/* pass ab info from Cx_IPL to BL2 */ +#define AB_INFO_FLAG__IPL (0xEB22FFFCU) +#define AB_INFO_FLAG_ADDR (0x41DFFFFCU) +#define AB_INFO_FLAG_INIT (0xDEADBEEFU) +#define AB_INFO_SELECT_1st (0x00000000U) +#define AB_INFO_SELECT_2nd (0x10000000U) +#define AB_INFO_FLAG_STORE (0x0BADF00DU) +#define AB_INFO_FLAG_OK (0x00FACADEU) + +/** + * Select the slot where to boot from. + * + * On Android devices with more than one boot slot (multiple copies of the + * kernel and system images) selects which slot should be used to boot from and + * registers the boot attempt. This is used in by the new A/B update model where + * one slot is updated in the background while running from the other slot. If + * the selected slot did not successfully boot in the past, a boot attempt is + * registered before returning from this function so it isn't selected + * indefinitely. + * + * @param[in] dev_desc Place to store the device description pointer + * @param[in] part_info Place to store the partition information + * @return The slot number (>= 0) on success, or a negative on error + */ +int ab_select_slot( + // struct blk_desc *dev_desc, struct disk_partition *part_info + void +); + +#endif /* __ANDROID_AB_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/android_bootloader_message.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/android_bootloader_message.h new file mode 100644 index 0000000..286d7ab --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/android_bootloader_message.h @@ -0,0 +1,256 @@ +/* + * This is from the Android Project, + * Repository: https://android.googlesource.com/platform/bootable/recovery + * File: bootloader_message/include/bootloader_message/bootloader_message.h + * Commit: See U-Boot commit description + * + * Copyright (C) 2008 The Android Open Source Project + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __ANDROID_BOOTLOADER_MESSAGE_H +#define __ANDROID_BOOTLOADER_MESSAGE_H + +#ifndef __UBOOT__ +#include +#include +#include +#else +/* compiler.h defines the types that otherwise are included from stdint.h and + * stddef.h + */ +#include +#endif + +// Spaces used by misc partition are as below: +// 0 - 2K For bootloader_message +// 2K - 16K Used by Vendor's bootloader (the 2K - 4K range may be optionally used +// as bootloader_message_ab struct) +// 16K - 64K Used by uncrypt and recovery to store wipe_package for A/B devices +// Note that these offsets are admitted by bootloader,recovery and uncrypt, so they +// are not configurable without changing all of them. +static const size_t BOOTLOADER_MESSAGE_OFFSET_IN_MISC = 0; +static const size_t WIPE_PACKAGE_OFFSET_IN_MISC = 16 * 1024; + +/* Bootloader Message (2-KiB) + * + * This structure describes the content of a block in flash + * that is used for recovery and the bootloader to talk to + * each other. + * + * The command field is updated by linux when it wants to + * reboot into recovery or to update radio or bootloader firmware. + * It is also updated by the bootloader when firmware update + * is complete (to boot into recovery for any final cleanup) + * + * The status field was used by the bootloader after the completion + * of an "update-radio" or "update-hboot" command, which has been + * deprecated since Froyo. + * + * The recovery field is only written by linux and used + * for the system to send a message to recovery or the + * other way around. + * + * The stage field is written by packages which restart themselves + * multiple times, so that the UI can reflect which invocation of the + * package it is. If the value is of the format "#/#" (eg, "1/3"), + * the UI will add a simple indicator of that status. + * + * We used to have slot_suffix field for A/B boot control metadata in + * this struct, which gets unintentionally cleared by recovery or + * uncrypt. Move it into struct bootloader_message_ab to avoid the + * issue. + */ +struct bootloader_message { + char command[32]; + char status[32]; + char recovery[768]; + + // The 'recovery' field used to be 1024 bytes. It has only ever + // been used to store the recovery command line, so 768 bytes + // should be plenty. We carve off the last 256 bytes to store the + // stage string (for multistage packages) and possible future + // expansion. + char stage[32]; + + // The 'reserved' field used to be 224 bytes when it was initially + // carved off from the 1024-byte recovery field. Bump it up to + // 1184-byte so that the entire bootloader_message struct rounds up + // to 2048-byte. + char reserved[1184]; +}; + +/** + * We must be cautious when changing the bootloader_message struct size, + * because A/B-specific fields may end up with different offsets. + */ +#ifndef __UBOOT__ +#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus) +static_assert(sizeof(struct bootloader_message) == 2048, + "struct bootloader_message size changes, which may break A/B devices"); +#endif +#endif /* __UBOOT__ */ + +/** + * The A/B-specific bootloader message structure (4-KiB). + * + * We separate A/B boot control metadata from the regular bootloader + * message struct and keep it here. Everything that's A/B-specific + * stays after struct bootloader_message, which should be managed by + * the A/B-bootloader or boot control HAL. + * + * The slot_suffix field is used for A/B implementations where the + * bootloader does not set the androidboot.ro.boot.slot_suffix kernel + * commandline parameter. This is used by fs_mgr to mount /system and + * other partitions with the slotselect flag set in fstab. A/B + * implementations are free to use all 32 bytes and may store private + * data past the first NUL-byte in this field. It is encouraged, but + * not mandatory, to use 'struct bootloader_control' described below. + * + * The update_channel field is used to store the Omaha update channel + * if update_engine is compiled with Omaha support. + */ +struct bootloader_message_ab { + struct bootloader_message message; + char slot_suffix[32]; + char update_channel[128]; + + // Round up the entire struct to 4096-byte. + char reserved[1888]; +}; + +/** + * Be cautious about the struct size change, in case we put anything post + * bootloader_message_ab struct (b/29159185). + */ +#ifndef __UBOOT__ +#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus) +static_assert(sizeof(struct bootloader_message_ab) == 4096, + "struct bootloader_message_ab size changes"); +#endif +#endif /* __UBOOT__ */ + +#define BOOT_CTRL_MAGIC 0x42414342 /* Bootloader Control AB */ +#define BOOT_CTRL_VERSION 1 + +struct slot_metadata { + // Slot priority with 15 meaning highest priority, 1 lowest + // priority and 0 the slot is unbootable. + uint8_t priority : 4; + // Number of times left attempting to boot this slot. + uint8_t tries_remaining : 3; + // 1 if this slot has booted successfully, 0 otherwise. + uint8_t successful_boot : 1; + // 1 if this slot is corrupted from a dm-verity corruption, 0 + // otherwise. + uint8_t verity_corrupted : 1; + // Reserved for further use. + uint8_t reserved : 7; +} __attribute__((packed)); + +/* Bootloader Control AB + * + * This struct can be used to manage A/B metadata. It is designed to + * be put in the 'slot_suffix' field of the 'bootloader_message' + * structure described above. It is encouraged to use the + * 'bootloader_control' structure to store the A/B metadata, but not + * mandatory. + */ +struct bootloader_control { + // NUL terminated active slot suffix. + char slot_suffix[4]; + // Bootloader Control AB magic number (see BOOT_CTRL_MAGIC). + uint32_t magic; + // Version of struct being used (see BOOT_CTRL_VERSION). + uint8_t version; + // Number of slots being managed. + uint8_t nb_slot : 3; + // Number of times left attempting to boot recovery. + uint8_t recovery_tries_remaining : 3; + // Ensure 4-bytes alignment for slot_info field. + uint8_t reserved0[2]; + // Per-slot information. Up to 4 slots. + struct slot_metadata slot_info[4]; + // Reserved for further use. + uint8_t reserved1[8]; + // CRC32 of all 28 bytes preceding this field (little endian + // format). + uint32_t crc32_le; +} __attribute__((packed)); + +#ifndef __UBOOT__ +#if (__STDC_VERSION__ >= 201112L) || defined(__cplusplus) +static_assert(sizeof(struct bootloader_control) == + sizeof(((struct bootloader_message_ab *)0)->slot_suffix), + "struct bootloader_control has wrong size"); +#endif +#endif /* __UBOOT__ */ + +#ifndef __UBOOT__ +#ifdef __cplusplus + +#include +#include + +// Return the block device name for the bootloader message partition and waits +// for the device for up to 10 seconds. In case of error returns the empty +// string. +std::string get_bootloader_message_blk_device(std::string* err); + +// Read bootloader message into boot. Error message will be set in err. +bool read_bootloader_message(bootloader_message* boot, std::string* err); + +// Read bootloader message from the specified misc device into boot. +bool read_bootloader_message_from(bootloader_message* boot, const std::string& misc_blk_device, + std::string* err); + +// Write bootloader message to BCB. +bool write_bootloader_message(const bootloader_message& boot, std::string* err); + +// Write bootloader message to the specified BCB device. +bool write_bootloader_message_to(const bootloader_message& boot, + const std::string& misc_blk_device, std::string* err); + +// Write bootloader message (boots into recovery with the options) to BCB. Will +// set the command and recovery fields, and reset the rest. +bool write_bootloader_message(const std::vector& options, std::string* err); + +// Write bootloader message (boots into recovery with the options) to the specific BCB device. Will +// set the command and recovery fields, and reset the rest. +bool write_bootloader_message_to(const std::vector& options, + const std::string& misc_blk_device, std::string* err); + +// Update bootloader message (boots into recovery with the options) to BCB. Will +// only update the command and recovery fields. +bool update_bootloader_message(const std::vector& options, std::string* err); + +// Update bootloader message (boots into recovery with the |options|) in |boot|. Will only update +// the command and recovery fields. +bool update_bootloader_message_in_struct(bootloader_message* boot, + const std::vector& options); + +// Clear BCB. +bool clear_bootloader_message(std::string* err); + +// Writes the reboot-bootloader reboot reason to the bootloader_message. +bool write_reboot_bootloader(std::string* err); + +// Read the wipe package from BCB (from offset WIPE_PACKAGE_OFFSET_IN_MISC). +bool read_wipe_package(std::string* package_data, size_t size, std::string* err); + +// Write the wipe package into BCB (to offset WIPE_PACKAGE_OFFSET_IN_MISC). +bool write_wipe_package(const std::string& package_data, std::string* err); + +#else + +#include + +// C Interface. +bool write_bootloader_message(const char* options); +bool write_reboot_bootloader(void); + +#endif // ifdef __cplusplus +#endif /* __UBOOT__ */ + +#endif /* __ANDROID_BOOTLOADER_MESSAGE_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/axmm_register.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/axmm_register.h new file mode 100644 index 0000000..b3a6c8a --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/axmm_register.h @@ -0,0 +1,73 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : AXMM register header + ******************************************************************************/ + +#ifndef AXMM_REGISTER_H__ +#define AXMM_REGISTER_H__ + +#include + +/* System RAM / SDRAM register base address */ +#define AXMM_BASE (0xE6780000U) + +#define AXMM_DPTDIVCR (AXMM_BASE + 0x6000U) +#define AXMM_DPTRGNCR (AXMM_BASE + 0x6100U) +#define AXMM_DPTSECCR (AXMM_BASE + 0x6200U) +#define AXMM_SPTDIVCR (AXMM_BASE + 0x6300U) +#define AXMM_SPTRGNCR (AXMM_BASE + 0x6400U) +#define AXMM_SPTSECCR (AXMM_BASE + 0x6500U) + +static inline uint32_t get_dptdivcr_addr(uint32_t num) +{ + return ((AXMM_DPTDIVCR + (num * 4U))); +} + +static inline uint32_t get_dptrgncr_addr(uint32_t num) +{ + return ((AXMM_DPTRGNCR + (num * 4U))); +} + +static inline uint32_t get_dptseccr_addr(uint32_t num) +{ + return ((AXMM_DPTSECCR + (num * 4U))); +} + +static inline uint32_t get_sptdivcr_addr(uint32_t num) +{ + return ((AXMM_SPTDIVCR + (num * 4U))); +} + +static inline uint32_t get_sptrgncr_addr(uint32_t num) +{ + return ((AXMM_SPTRGNCR + (num * 4U))); +} + +static inline uint32_t get_sptseccr_addr(uint32_t num) +{ + return ((AXMM_SPTSECCR + (num * 4U))); +} + +#endif /* AXMM_REGISTER_H__ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/cnf_tbl.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/cnf_tbl.h new file mode 100644 index 0000000..9691245 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/cnf_tbl.h @@ -0,0 +1,126 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table header + ******************************************************************************/ + +#ifndef CNF_TBL_H_ +#define CNF_TBL_H_ + +#include + +typedef struct{ + uint64_t fix; + uint64_t be; +} QOS_SETTING_TABLE; + +typedef struct{ + uint32_t phys_addr; /* Physical address of Region ID registers. */ + uint32_t value; /* setting value of Region ID registers. */ +} REGION_ID_SETTING_TABLE; + +/* For RAM protection table */ +typedef struct { + uint32_t rw_val; + uint32_t sec_val; +}RAM_PROTECTION_VALUE_FORMAT; + +typedef struct { + uint32_t read_val; + uint32_t write_val; +}RTRAM_PROTECTION_VALUE_FORMAT; + +typedef struct { + uint32_t addr; + RTRAM_PROTECTION_VALUE_FORMAT setting_value; +}RTRAM_PROTECTION_STRUCTUR; + +typedef struct { + uint32_t addr; + RAM_PROTECTION_VALUE_FORMAT setting_value; +}SYSTEM_RAM_PROTECTION_STRUCTUR; + +typedef struct { + uint64_t addr; + RAM_PROTECTION_VALUE_FORMAT setting_value; +}DRAM_PROTECTION_STRUCTUR; + + +#if (RCAR_LSI == RCAR_S4) +#define QOS_TBL_MAX (48U) /* Max setting number of QoS Bank registers. */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define QOS_TBL_MAX (125U) /* Max setting number of QoS Bank registers. */ +#endif /* RCAR_LSI == RCAR_S4 */ + +#if (RCAR_LSI == RCAR_V4H) +#define RGID_MASTER_MAX (77U) /* Max number of Region registers. (Master) */ +#define RGID_READ_MAX (908U) /* Max number of Region registers. (Read) */ +#define RGID_WRITE_MAX (907U) /* Max number of Region registers. (Write) */ +#define RGID_SEC_MAX (957U) /* Max number of Region registers. (Secure) */ +#define RGID_AXI_MAX (98U) /* Max number of Region registers. (Read/Write for AXI-bus) */ +#elif (RCAR_LSI == RCAR_V4M) +#define RGID_MASTER_MAX (85U) /* Max number of Region registers. (Master) */ +#define RGID_READ_MAX (805U) /* Max number of Region registers. (Read) */ +#define RGID_WRITE_MAX (804U) /* Max number of Region registers. (Write) */ +#define RGID_SEC_MAX (819U) /* Max number of Region registers. (Secure) */ +#define RGID_AXI_MAX (90U) /* Max number of Region registers. (Read/Write for AXI-bus) */ +#endif /* RCAR_LSI == RCAR_V4H */ + +#define RAM_PROTECTION_MAX (16U) /* Max number of RAM Protection registers. (RT-VRAM0/RT-VRAM1/SystemRAM) */ +#define DRAM_PROTECTION_MAX (64U) /* Max number of RAM Protection registers. (SDRAM) */ + +#if (RCAR_LSI == RCAR_V4H) +#define IMP_MASTER_MAX (19U) +#define IMP_SLAVE_MAX (38U) +#endif /* (RCAR_LSI == RCAR_V4H) */ + +#if (RCAR_LSI == RCAR_V4H) +#define IPMMU_RGID_MAX (11U) +#elif (RCAR_LSI == RCAR_V4M) +#define IPMMU_RGID_MAX (10U) +#endif /* (RCAR_LSI == RCAR_V4H) */ + +extern const QOS_SETTING_TABLE g_qosbw_tbl[QOS_TBL_MAX]; +extern const QOS_SETTING_TABLE g_qoswt_tbl[QOS_TBL_MAX]; + +extern const REGION_ID_SETTING_TABLE g_rgid_master_tbl[RGID_MASTER_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_read_tbl[RGID_READ_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_write_tbl[RGID_WRITE_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[RGID_SEC_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[RGID_AXI_MAX]; +#if (RCAR_LSI == RCAR_V4H) +extern const REGION_ID_SETTING_TABLE g_imp_rgid_m_tbl[IMP_MASTER_MAX]; +extern const REGION_ID_SETTING_TABLE g_imp_rgid_s_tbl[IMP_SLAVE_MAX]; +#endif /* (RCAR_LSI == RCAR_V4H) */ +extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX]; +extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX]; +extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX]; + +/* For RAM protection */ +extern const RTRAM_PROTECTION_STRUCTUR g_rtvram0_protection_table[RAM_PROTECTION_MAX]; +extern const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table[RAM_PROTECTION_MAX]; +extern const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX]; +extern const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX]; + +#endif /* CNF_TBL_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/cpu_on.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/cpu_on.h new file mode 100644 index 0000000..cf8bbb3 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/cpu_on.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : cpu on function header + ******************************************************************************/ +/****************************************************************************** + * @file cpu_on.h + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 17.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + * : 09.12.2024 0.03 Remove OTP_MEM_OTPMONITOR60 register. + * : 19.12.2024 0.04 Add definition for booting CR52 core 2. +*****************************************************************************/ + +#ifndef CPU_ON_H__ +#define CPU_ON_H__ + +#define RCAR_PWR_TARGET_CR (0U) +#define RCAR_PWR_TARGET_CA (1U) + + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void arm_cpu_on(uint32_t target, uint32_t boot_addr, int core_id); +void adj_ca_variant_freq(void); + +#define OTP_MEM_1_BASE (0xE61BF000U) +#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U) +#define OTP_MEM_PRODUCT_MASK (0x000000FFU) +#if (RCAR_LSI == RCAR_V4H) +#define VARIANT_V4H_7 (0x00U) +#define VARIANT_V4H_5 (0x01U) +#define VARIANT_V4H_3 (0x02U) +#elif (RCAR_LSI == RCAR_V4M) +#define VARIANT_V4M_7 (0x00U) +#define VARIANT_V4M_5 (0x01U) +#define VARIANT_V4M_3 (0x02U) +#define VARIANT_V4M_2 (0x04U) +#endif /* RCAR_LSI == RCAR_V4H */ + +#endif /* CPU_ON_H__ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/crc.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/crc.h new file mode 100644 index 0000000..3a96170 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/crc.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + */ + +#ifndef _UBOOT_CRC_H +#define _UBOOT_CRC_H + +// #include /* 'uint*' definitions */ +typedef unsigned int uint; + +/** + * crc32 - Calculate the CRC32 for a block of data + * + * @crc: Input crc to chain from a previous calculution (use 0 to start a new + * calculation) + * @buf: Bytes to checksum + * @len: Number of bytes to checksum + * @return checksum value + */ +uint32_t crc32(uint32_t crc, const unsigned char *buf, uint len); + +/** + * crc32_no_comp - Calculate the CRC32 for a block of data (no one's compliment) + * + * This version uses a different algorithm which doesn't use one's compliment. + * JFFS2 (and other things?) use this. + * + * @crc: Input crc to chain from a previous calculution (use 0 to start a new + * calculation) + * @buf: Bytes to checksum + * @len: Number of bytes to checksum + * @return checksum value + */ +uint32_t crc32_no_comp(uint32_t crc, const unsigned char *buf, uint len); + +#endif /* _UBOOT_CRC_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_boot.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_boot.h new file mode 100644 index 0000000..94cb5ef --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_boot.h @@ -0,0 +1,46 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc boot header + ******************************************************************************/ +/****************************************************************************** + * @file emmc_boot.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +#ifndef EMMC_BOOT_ +#define EMMC_BOOT_ + +void emmc_initialize( void ); + +#endif /* EMMC_BOOT_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_config.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_config.h new file mode 100644 index 0000000..88305b6 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_config.h @@ -0,0 +1,68 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc config header + ******************************************************************************/ +/****************************************************************************** + * @file emmc_config.h + * - Version : 0.03 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 18.03.2022 0.02 Delete unnecessary define + * Delete unnecessary include file + * : 31.10.2022 0.03 License notation change. + *****************************************************************************/ + +#ifndef EMMC_CONFIG_H__ +#define EMMC_CONFIG_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* MMC driver config */ +#define EMMC_RCA (1U) /* RCA */ +#define EMMC_RW_DATA_TIMEOUT (0x40U) /* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */ +#define EMMC_CMD_MAX (60U) /* Don't change. */ + +/* etc */ +#define LOADIMAGE_FLAGS_DMA_ENABLE (0x00000001U) + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* #ifndef EMMC_CONFIG_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_def.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_def.h new file mode 100644 index 0000000..d5680d1 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_def.h @@ -0,0 +1,86 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc def header + ******************************************************************************/ +/****************************************************************************** + * @file emmc_def.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +#ifndef EMMC_DEF_H__ +#define EMMC_DEF_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_std.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ +extern st_mmc_base mmc_drv_obj; + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* eMMC driver API */ +EMMC_ERROR_CODE emmc_init(void); +void import_mmc_drv_obj(void); +void export_mmc_drv_obj(void); +EMMC_ERROR_CODE emmc_terminate(void); +EMMC_ERROR_CODE emmc_memcard_power(uint32_t mode); +EMMC_ERROR_CODE emmc_mount(void); +EMMC_ERROR_CODE emmc_set_request_mmc_clock(const uint32_t *freq); +EMMC_ERROR_CODE emmc_send_idle_cmd (uint32_t arg); +EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id); +EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, uint32_t feature_flags); +uint32_t emmc_bit_field (const uint8_t *data, uint32_t top, uint32_t bottom); + + +/* interrupt service */ +uint32_t emmc_interrupt(void); + + +/* send command API */ +EMMC_ERROR_CODE emmc_exec_cmd (uint32_t error_mask, uint32_t *response); +void emmc_make_nontrans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg); +void emmc_make_trans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual, + uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode); +EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg); + +/* ********************************* CODE ********************************** */ + +#endif /* #define EMMC_DEF_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_hal.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_hal.h new file mode 100644 index 0000000..9c87276 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_hal.h @@ -0,0 +1,175 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc HW Layer header + ******************************************************************************/ +/****************************************************************************** + * @file emmc_hal.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +#ifndef EMMC_HAL_H__ +#define EMMC_HAL_H__ +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +/* Memory card response types */ +#define HAL_MEMCARD_COMMAND_INDEX_MASK (0x0003fU) + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* memory access operation */ +typedef enum +{ + HAL_MEMCARD_READ = 0U, /**< read */ + HAL_MEMCARD_WRITE = 1U /**< write */ +} HAL_MEMCARD_OPERATION; + +/* Type of data width on memorycard bus */ +typedef enum +{ + HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U, + HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U, + HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U +} HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */ + +/* mode of data transfer */ +typedef enum +{ + HAL_MEMCARD_DMA = 0U, + HAL_MEMCARD_NOT_DMA = 1U +} HAL_MEMCARD_DATA_TRANSFER_MODE; + + +/* Memory card response types. */ +typedef enum hal_memcard_response_type +{ + HAL_MEMCARD_RESPONSE_NONE = 0x00000U, + HAL_MEMCARD_RESPONSE_R1 = 0x00100U, + HAL_MEMCARD_RESPONSE_R1b = 0x00200U, + HAL_MEMCARD_RESPONSE_R2 = 0x00300U, + HAL_MEMCARD_RESPONSE_R3 = 0x00400U, + HAL_MEMCARD_RESPONSE_R4 = 0x00500U, + HAL_MEMCARD_RESPONSE_R5 = 0x00600U, + HAL_MEMCARD_RESPONSE_R6 = 0x00700U, + HAL_MEMCARD_RESPONSE_R7 = 0x00800U, + HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U +} HAL_MEMCARD_RESPONSE_TYPE; + + +/* Memory card command types. */ +typedef enum hal_memcard_command_type +{ + HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U, + HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U, + HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U, + HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U, + HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U, + HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U +} HAL_MEMCARD_COMMAND_TYPE; + +/* Type of memory card */ +typedef enum hal_memcard_command_card_type +{ + HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U +} HAL_MEMCARD_COMMAND_CARD_TYPE; + +/* Memory card application command. */ +typedef enum hal_memcard_command_app_norm +{ +HAL_MEMCARD_COMMAND_NORMAL = 0x00000U, +HAL_MEMCARD_COMMAND_APP = 0x20000U, +HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U +} HAL_MEMCARD_COMMAND_APP_NORM; + + +/* Memory card command codes. */ +typedef enum +{ +/* class 0 and class 1 */ + CMD0_GO_IDLE_STATE = 0 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD0 */ + CMD1_SEND_OP_COND = 1 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD1 */ + CMD2_ALL_SEND_CID_MMC = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD2 */ + CMD2_ALL_SEND_CID_SD = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD3_SET_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD3 */ + CMD3_SEND_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R6 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD4_SET_DSR = 4 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD4 */ + CMD5_SLEEP_AWAKE = 5 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD5 */ + CMD6_SWITCH = 6 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD6 */ + CMD6_SWITCH_FUNC = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + ACMD6_SET_BUS_WIDTH = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + CMD7_SELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7 */ + CMD7_SELECT_CARD_PROG = 7 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7(from Disconnected State to Programming State) */ + CMD7_DESELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, + CMD8_SEND_EXT_CSD = 8 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD8 */ + CMD8_SEND_IF_COND = 8 | HAL_MEMCARD_RESPONSE_R7 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD9_SEND_CSD = 9 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD9 */ + CMD10_SEND_CID = 10 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD10 */ + CMD11_READ_DAT_UNTIL_STOP = 11 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD11 */ + CMD12_STOP_TRANSMISSION = 12 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 */ + CMD12_STOP_TRANSMISSION_WRITE = 12 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 R1b : write case */ + CMD13_SEND_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD13 */ + ACMD13_SD_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + CMD14_BUSTEST_R = 14 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD14 */ + CMD15_GO_INACTIVE_STATE = 15 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD15 */ + +/* class 2 */ + CMD16_SET_BLOCKLEN = 16 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD16 */ + CMD17_READ_SINGLE_BLOCK = 17 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD17 */ + CMD18_READ_MULTIPLE_BLOCK = 18 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD18 */ + CMD19_BUS_TEST_W = 19 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD19 */ +/* class 3 */ + CMD20_WRITE_DAT_UNTIL_STOP = 20 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD20 */ + CMD21 = 21, /* CMD21 */ + CMD22 = 22, /* CMD22 */ + ACMD22_SEND_NUM_WR_BLOCKS = 22 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + +/* class 4 */ + CMD23_SET_BLOCK_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL /* CMD23 */ + +} HAL_MEMCARD_COMMAND; + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* EMMC_HAL_H__ */ + +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_multiboot.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_multiboot.h new file mode 100644 index 0000000..336b40a --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_multiboot.h @@ -0,0 +1,62 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc multi boot header + ******************************************************************************/ +/****************************************************************************** + * @file emmc_multiboot.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +#ifndef EMMC_MULTIBOOT_H_ +#define EMMC_MULTIBOOT_H_ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ +/* EMMC */ +#define EMMC_DEV_OK (0x525F4F4BU) /* "R_OK" */ +#define EMMC_DEV_ERR (0xFFFFFFFFU) +#define EMMC_DEV_ERR_HW (0x00000004U) +#define EMMC_DEV_ERR_FAULT_INJECTION (0x00000005U) + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + + +/* ************************** FUNCTION PROTOTYPES ************************** */ +uint32_t emmc_trans_data(uint32_t next_bootPartition, uintptr_t sourceSct, uintptr_t targetAd, uint32_t sectorSize); +/* ******************************** END ************************************ */ +#endif /* #ifndef EMMC_MULTIBOOT_H_*/ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_registers.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_registers.h new file mode 100644 index 0000000..3b1fd16 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_registers.h @@ -0,0 +1,174 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc register header + ******************************************************************************/ +/****************************************************************************** + * @file emmc_register.h + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 24.10.2022 0.02 SDIF_MODE register to support HS200/400 + * : 31.10.2022 0.03 License notation change. + * : 07.06.2024 0.04 Modify the transfer end bit of DMAC channel. + *****************************************************************************/ + +#ifndef EMMC_REGISTERS_H__ +#define EMMC_REGISTERS_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +/* MMC0 channel */ +#define MMC0_SD_BASE (BASE_MMC0_ADDR) /* reg addr is 0xEE140000U */ + +#define SD_CMD (MMC0_SD_BASE + 0x0000U) +#define SD_ARG (MMC0_SD_BASE + 0x0010U) +#define SD_STOP (MMC0_SD_BASE + 0x0020U) +#define SD_SECCNT (MMC0_SD_BASE + 0x0028U) +#define SD_RSP10 (MMC0_SD_BASE + 0x0030U) +#define SD_RSP32 (MMC0_SD_BASE + 0x0040U) +#define SD_RSP54 (MMC0_SD_BASE + 0x0050U) +#define SD_RSP76 (MMC0_SD_BASE + 0x0060U) +#define SD_INFO1 (MMC0_SD_BASE + 0x0070U) +#define SD_INFO2 (MMC0_SD_BASE + 0x0078U) +#define SD_INFO1_MASK (MMC0_SD_BASE + 0x0080U) +#define SD_INFO2_MASK (MMC0_SD_BASE + 0x0088U) +#define SD_CLK_CTRL (MMC0_SD_BASE + 0x0090U) +#define SD_SIZE (MMC0_SD_BASE + 0x0098U) +#define SD_OPTION (MMC0_SD_BASE + 0x00A0U) +#define SD_ERR_STS1 (MMC0_SD_BASE + 0x00B0U) +#define SD_ERR_STS2 (MMC0_SD_BASE + 0x00B8U) +#define SD_BUF0 (MMC0_SD_BASE + 0x00C0U) +#define CC_EXT_MODE (MMC0_SD_BASE + 0x0360U) +#define SOFT_RST (MMC0_SD_BASE + 0x0380U) +#define HOST_MODE (MMC0_SD_BASE + 0x0390U) +#define SDIF_MODE (MMC0_SD_BASE + 0x0398U) +#define DM_CM_DTRAN_MODE (MMC0_SD_BASE + 0x0820U) +#define DM_CM_DTRAN_CTRL (MMC0_SD_BASE + 0x0828U) +#define DM_CM_INFO1 (MMC0_SD_BASE + 0x0840U) +#define DM_CM_INFO1_MASK (MMC0_SD_BASE + 0x0848U) +#define DM_CM_INFO2 (MMC0_SD_BASE + 0x0850U) +#define DM_CM_INFO2_MASK (MMC0_SD_BASE + 0x0858U) +#define DM_DTRAN_ADDR (MMC0_SD_BASE + 0x0880U) +#define SCC_DTCNTL (MMC0_SD_BASE + 0x1000U) +#define SCC_TAPSET (MMC0_SD_BASE + 0x1008U) +#define SCC_DT2FF (MMC0_SD_BASE + 0x1010U) +#define SCC_CKSEL (MMC0_SD_BASE + 0x1018U) +#define SCC_SMPCMP (MMC0_SD_BASE + 0x1030U) +#define SCC_TMPPORT2 (MMC0_SD_BASE + 0x1038U) + +/* SD_INFO1 Registers */ +#define SD_INFO1_INFO2 (0x00000004U) /* Access end*/ +#define SD_INFO1_INFO0 (0x00000001U) /* Response end*/ + +/* SD_INFO2 Registers */ +#define SD_INFO2_CBSY (0x00004000U) /* Command Type Register Busy*/ +#define SD_INFO2_BWE (0x00000200U) /* SD_BUF Write Enable*/ +#define SD_INFO2_BRE (0x00000100U) /* SD_BUF Read Enable*/ +#define SD_INFO2_DAT0 (0x00000080U) /* SDDAT0*/ +#define SD_INFO2_ALL_ERR (0x0000807FU) +#define SD_INFO2_CLEAR (0x00000800U) /* BIT11 The write value should always be 1. HWM_0003 */ + +/* DM_INFO1 Registers */ +#define DM_CM_INFO_DTRANEND0 (0x00010000U) /* DMAC Channel 0 Transfer End */ +#define DM_CM_INFO_DTRANEND1 (0x00100000U) /* DMAC Channel 1 Transfer End */ + +/* DM_INFO2 Registers */ +#define DM_CM_INFO2_DTRANEND0 (0x00010000U) /* DMAC Channel 0 Error */ +#define DM_CM_INFO2_DTRANEND1 (0x00020000U) /* DMAC Channel 1 Error */ + +/* SOFT_RST */ +#define SOFT_RST_SDRST (0x00000001U) + +/* SD_CLK_CTRL */ +#define SD_CLK_CTRL_CLKDIV_MASK (0x000000FFU) +#define SD_CLK_WRITE_MASK (0x000003FFU) + +/* SD_OPTION */ +#define SD_OPTION_WIDTH (0x00008000U) +#define SD_OPTION_WIDTH8 (0x00002000U) +#define SD_OPTION_TIMEOUT_CNT_MASK (0x000000F0U) + + +/* MMC Clock Frequency +* 200MHz * 1/x = output clock +*/ +#define MMC_400KHZ (512U) /* 200MHz * 1/512 = 390 KHz */ +#define MMC_20MHZ (16U) /* 200MHz * 1/16 = 12.5 MHz Normal speed mode*/ +#define MMC_26MHZ (8U) /* 200MHz * 1/8 = 25 MHz High speed mode 26Mhz*/ +#define MMC_52MHZ (4U) /* 200MHz * 1/4 = 50 MHz High speed mode 52Mhz*/ +#define MMC_200MHZ (1U) /* 200MHz * 1/1 = 200 MHz HS200/HS400 mode 200Mhz*/ + +#define MMC_FREQ_52MHZ (52000000U) +#define MMC_FREQ_26MHZ (26000000U) +#define MMC_FREQ_20MHZ (20000000U) + +/* MMC Clock DIV */ +#define MMC_SD_CLK_START (0x00000100U) /* CLOCK On */ +#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */ + +/* DM_CM_DTRAN_MODE */ +#define DM_CM_DTRAN_MODE_CH0 (0x00000000U) /* CH0 : downstream*/ +#define DM_CM_DTRAN_MODE_CH1 (0x00010000U) /* CH1 : upstream*/ +#define DM_CM_DTRAN_MODE_BIT_WIDTH (0x00000030U) + +/* CC_EXT_MODE */ +#define CC_EXT_MODE_DMASDRW_ENABLE (0x00000002U) /* SD_BUF Read/Write DMA Transfer */ +#define CC_EXT_MODE_CLEAR (0x00001010U) /* BIT 12 & 4 always 1. */ + +/* DM_CM_INFO_MASK */ +#define DM_CM_INFO_MASK_CLEAR (0xFFEEFEFEU) +#define DM_CM_INFO_CH0_ENABLE (0x00010001U) +#define DM_CM_INFO_CH1_ENABLE (0x00100001U) + +/* DM_CM_INFO2_MASK */ +#define DM_CM_INFO2_MASK_CLEAR (0xFFFCFFFEU) +#define DM_CM_INFO2_CH0_ENABLE (0x00010001U) +#define DM_CM_INFO2_CH1_ENABLE (0x00020001U) + +/* DM_DTRAN_ADDR */ +#define DM_DTRAN_ADDR_WRITE_MASK (0xFFFFFFF8U) + +/*DM_CM_DTRAN_CTRL */ +#define DM_CM_DTRAN_CTRL_START (0x00000001U) + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* EMMC_REGISTERS_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_std.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_std.h new file mode 100644 index 0000000..25c3f18 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/emmc_std.h @@ -0,0 +1,312 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc std header + ******************************************************************************/ +/****************************************************************************** + * @file emmc_std.h + * - Version : 0.03 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 24.10.2022 0.02 Add supports for HS200/400 + * : 31.10.2022 0.03 License notation change. + *****************************************************************************/ + +#ifndef EMMC_STD_H__ +#define EMMC_STD_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_hal.h" +#include "emmc_registers.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/*CSD register Macros */ +#define EMMC_CSD_SPEC_VARS() (emmc_bit_field(mmc_drv_obj.csd_data, 125,122)) +#define EMMC_CSD_TRAN_SPEED() (emmc_bit_field(mmc_drv_obj.csd_data, 103,96)) + +/* for sector access */ +#define EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */ +#define EMMC_SECTOR_PADD_MASK ((1U << EMMC_SECTOR_SIZE_SHIFT) - 1U) +#define EMMC_SECTOR_SIZE (512U) +#define EMMC_BLOCK_LENGTH (512U) +#define EMMC_BLOCK_LENGTH_DW (128U) + +/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */ +typedef enum +{ + EMMC_ERR = 0U, /**< unknown error */ + EMMC_SUCCESS , /**< OK */ + EMMC_ERR_FROM_DMAC , /**< DMAC allocation error */ + EMMC_ERR_FROM_DMAC_TRANSFER , /**< DMAC transfer error */ + EMMC_ERR_CARD_STATUS_BIT , /**< card status error. Non-masked error bit was set in the card status */ + EMMC_ERR_CMD_TIMEOUT , /**< command timeout error */ + EMMC_ERR_DATA_TIMEOUT , /**< data timeout error */ + EMMC_ERR_CMD_CRC , /**< command CRC error */ + EMMC_ERR_DATA_CRC , /**< data CRC error */ + EMMC_ERR_PARAM , /**< parameter error */ + EMMC_ERR_RESPONSE , /**< response error */ + EMMC_ERR_RESPONSE_BUSY , /**< response busy error */ + EMMC_ERR_TRANSFER , /**< data transfer error */ + EMMC_ERR_READ_SECTOR , /**< read sector error */ + EMMC_ERR_WRITE_SECTOR , /**< write sector error */ + EMMC_ERR_STATE , /**< state error */ + EMMC_ERR_TIMEOUT , /**< timeout error */ + EMMC_ERR_ILLEGAL_CARD , /**< illegal card */ + EMMC_ERR_CARD_BUSY , /**< Busy state */ + EMMC_ERR_CARD_STATE , /**< card state error */ + EMMC_ERR_SET_TRACE , /**< trace information error */ + EMMC_ERR_FROM_TIMER , /**< Timer error */ + EMMC_ERR_FORCE_TERMINATE , /**< Force terminate */ + EMMC_ERR_CARD_POWER , /**< card power fail */ + EMMC_ERR_ERASE_SECTOR , /**< erase sector error */ + EMMC_ERR_INFO2 , /**< exec cmd error info2 */ + RCAR_ERR /**< Error judged by R-Car register */ + +} EMMC_ERROR_CODE; + +/* Error code judged by R-car register or eMMC return*/ +#define EMMC_TUNING_FAIL (0U) /* Fail judged by eMMC return*/ +#define TUNING_SUCCESS (1U) /* Tuning success */ +#define RCAR_TUNING_FAIL (2U) /* Fail judged by R-car register*/ + +/* Response */ +/** R1 */ +#define EMMC_R1_ERROR_MASK (0xFDBFE080U) /* Type 'E' bit and bit14(must be 0). ignore bit22 */ +#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) /* Ignore bit23 (Not check CRC error) */ +#define EMMC_R1_STATE_MASK (0x00001E00U) /* [12:9] */ +#define EMMC_R1_READY (0x00000100U) /* bit8 */ +#define EMMC_R1_STATE_SHIFT (9U) + +/** R4 */ +#define EMMC_R4_STATUS (0x00008000U) + +/** CSD */ +#define EMMC_TRANSPEED_FREQ_UNIT_MASK (0x07U) /* bit[2:0] */ +#define EMMC_TRANSPEED_MULT_MASK (0x78U) /* bit[6:3] */ +#define EMMC_TRANSPEED_MULT_SHIFT (3U) + +/** OCR */ +#define EMMC_HOST_OCR_VALUE (0x40FF8080U) +#define EMMC_OCR_STATUS_BIT (0x80000000U) /* Card power up status bit */ +#define EMMC_OCR_ACCESS_MODE_MASK (0x60000000U) /* bit[30:29] */ +#define EMMC_OCR_ACCESS_MODE_SECT (0x40000000U) + +/** EXT_CSD */ +#define EMMC_EXT_CSD_CARD_TYPE (196U) +#define EMMC_EXT_CSD_PARTITION_CONFIG (179U) +#define EMMC_EXT_CSD_PWR_CL_DDR_200_360 (253U) /* Power class for 200MHz, DDR at VCC= 3.6V */ +#define EMMC_EXT_CSD_PWR_CL_200_195 (237U) /* Power class for 200MHz, at VCCQ =1.95V, VCC = 3.6V */ +#define EMMC_EXT_CSD_PWR_CL_26_195 (201U) /* Power class for 26MHz at 1.95V 1 R */ +#define EMMC_EXT_CSD_PWR_CL_52_195 (200U) /* Power class for 52MHz at 1.95V 1 R */ + +#define EMMC_EXT_CSD_CARD_TYPE_26MHZ (0x01U) +#define EMMC_EXT_CSD_CARD_TYPE_52MHZ (0x02U) +#define EMMC_EXT_CSD_CARD_TYPE_200MHZ (0x10U) +#define EMMC_EXT_CSD_CARD_TYPE_400MHZ (0x40U) + +/** SWITCH (CMD6) argument */ +#define EXTCSD_ACCESS_BYTE (0x03000000U) /* H'03000000 */ + +#define BUS_WIDTH_ADD (183U<<16U) /* H'00b70000 */ +#define HS_TIMING_ADD (185U<<16U) /* H'00b90000 */ +#define POW_CLASS_ADD (187U<<16U) /* H'00bb0000 */ + +#define BUS_WIDTH_1 (0U<<8U) /* H'00000000 */ +#define BUS_WIDTH_8 (2U<<8U) /* H'00000200 */ +#define BUS_WIDTH_8_DDR (6U<<8U) /* H'00000400 */ + +#define HS_TIMING_1 (1U<<8U) /* H'00000100 */ +#define HS_TIMING_HS200 (2U<<8U) /* H'00000200 */ +#define HS_TIMING_HS400 (3U<<8U) /* H'00000300 */ + +#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1) /**< H'03b90100 */ +#define EMMC_SWITCH_HS200 (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_HS200) /**< H'03b90200 */ +#define EMMC_SWITCH_HS400 (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_HS400) /**< H'03b90300 */ + +#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1) /**< H'03b70000 */ +#define EMMC_SWITCH_BUS_WIDTH_8_DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8_DDR) /**< H'03b70600 */ + + +#define EMMC_SWITCH_PARTITION_CONFIG (0x03B30000UL) /**< Partition config = 0x00 */ + +/** for st_mmc_base */ +#define EMMC_MAX_RESPONSE_LENGTH (17U) +#define EMMC_MAX_CID_LENGTH (16U) +#define EMMC_MAX_CSD_LENGTH (16U) +#define EMMC_MAX_EXT_CSD_LENGTH (512U) + +/* speed mode */ +#define TIMING_HIGH_SPEED_OFF (0U) +#define TIMING_HIGH_SPEED (1U) +#define TIMING_HS200 (2U) +#define TIMING_HS400 (3U) + +/* MMC Clock Frequency */ +/* 200MHz * 1/x = output clock */ +#define HS400_50MHZ (8U) /* 400MHz * 1/8 = 50MHz */ +#define HS400_200MHZ (2U) /* 400MHz * 1/2 = 200MHz */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* Partition id */ +typedef enum +{ + PARTITION_ID_USER = 0x0, /**< User Area */ + PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */ + PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */ + PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */ + PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */ + PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */ + PARTITION_ID_GP_3 = 0x6, /**< General Purpose partition 3 */ + PARTITION_ID_GP_4 = 0x7, /**< General Purpose partition 4 */ + PARTITION_ID_MASK = 0x7 /**< [2:0] */ +} EMMC_PARTITION_ID; + +/* card state in R1 response [12:9] */ +typedef enum +{ + EMMC_R1_STATE_IDLE = 0, + EMMC_R1_STATE_READY, + EMMC_R1_STATE_IDENT, + EMMC_R1_STATE_STBY, + EMMC_R1_STATE_TRAN, + EMMC_R1_STATE_DATA, + EMMC_R1_STATE_RCV, + EMMC_R1_STATE_PRG, + EMMC_R1_STATE_DIS, + EMMC_R1_STATE_BTST, + EMMC_R1_STATE_SLEP +} EMMC_R1_STATE; + +typedef enum{ + ESTATE_BEGIN = 0, + ESTATE_ISSUE_CMD, + ESTATE_NON_RESP_CMD, + ESTATE_RCV_RESP, + ESTATE_RCV_RESPONSE_BUSY, + ESTATE_CHECK_RESPONSE_COMPLETE, + ESTATE_DATA_TRANSFER, + ESTATE_DATA_TRANSFER_COMPLETE, + ESTATE_ACCESS_END, + ESTATE_TRANSFER_ERROR, + ESTATE_ERROR, + ESTATE_END +}EMMC_INT_STATE; + +/* eMMC boot driver error information */ +typedef struct +{ + volatile uint32_t info1; /**< SD_INFO1 register value. (hardware dependence) */ + volatile uint32_t info2; /**< SD_INFO2 register value. (hardware dependence) */ + volatile uint32_t status1; /**< SD_ERR_STS1 register value. (hardware dependence) */ + volatile uint32_t status2; /**< SD_ERR_STS2 register value. (hardware dependence) */ + volatile uint32_t dm_info1; /**< DM_CM_INFO1 register value. (hardware dependence) */ + volatile uint32_t dm_info2; /**< DM_CM_INFO2 register value. (hardware dependence) */ +} st_error_info; + + +/* Command information */ +typedef struct +{ + HAL_MEMCARD_COMMAND cmd; /**< Command information */ + uint32_t arg; /**< argument */ + HAL_MEMCARD_OPERATION dir; /**< direction */ + uint32_t hw; /**< H/W dependence. SD_CMD register value. */ +} st_command_info; + + +/* MMC driver base */ +typedef struct +{ + st_error_info error_info; /**< error information */ + st_command_info cmd_info; /**< command information */ + + /* for data transfer */ + uint32_t *buff_address_virtual; /**< Dest or Src buff */ + uint32_t *buff_address_physical; /**< Dest or Src buff */ + HAL_MEMCARD_DATA_WIDTH bus_width; /**< bus width */ + uint32_t trans_size; /**< transfer size for this command */ + uint32_t remain_size; /**< remain size for this command */ + uint32_t response_length; /**< response length for this command */ + + /* clock */ + uint32_t max_freq; /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */ + uint32_t current_freq; /**< current MMC clock[Hz] (the closest frequency supported by HW) */ + uint32_t set_freq; /**< Frequency to be set. */ + + /* state flag */ + uint32_t card_power_enable; /**< True : Power ON */ + uint32_t clock_enable; /**< True : Clock ON */ + uint32_t initialize; /**< True : initialize complete. */ + uint32_t mount; /**< True : mount complete. */ + uint32_t selected; /**< True : selected card. */ + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; /**< 0: DMA, 1:PIO */ + EMMC_R1_STATE current_state; /**< card state */ + volatile uint32_t during_transfer; /**< True : during transfer */ + volatile uint32_t during_dma_transfer; /**< True : during transfer (DMA)*/ + volatile uint32_t dma_error_flag; /**< True : occurred DMAC error */ + volatile uint32_t force_terminate; /**< force terminate flag */ + volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */ + + /* timeout */ + uint32_t data_timeout; /**< read and write data timeout.*/ + + /* interrupt */ + volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */ + volatile uint32_t int_event2; /**< interrupt SD_INFO2 Event */ + volatile uint32_t dm_event1; /**< interrupt DM_CM_INFO1 Event */ + volatile uint32_t dm_event2; /**< interrupt DM_CM_INFO2 Event */ + + /* response */ + uint32_t *response; /**< pointer to buffer for executing command. */ + uint32_t r1_card_status; /**< R1 response data */ + uint32_t r3_ocr; /**< R3 response data */ + uint32_t r4_resp; /**< R4 response data */ + uint32_t r5_resp; /**< R5 response data */ + + /* Card registers (4byte align) */ + uint8_t csd_data[EMMC_MAX_CSD_LENGTH]; /**< CSD */ + uint8_t cid_data[EMMC_MAX_CID_LENGTH]; /**< CID */ + uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH]; /**< EXT_CSD */ + uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH]; /**< other response */ + + /* SDHI base address */ + uintptr_t base_address; +} st_mmc_base; + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +/* ******************************** END ************************************ */ +#endif /* EMMC_STD_H__ */ +/* EMMC_STD_H__ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/gic.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/gic.h new file mode 100644 index 0000000..08d6f8a --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/gic.h @@ -0,0 +1,417 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : GIC Control Function + ******************************************************************************/ +/****************************************************************************** + * @file gic.h + * - Version : 0.04 + * @brief Controls GIC-600 registers and interrupts. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.08.2022 0.01 First Release + * : 20.09.2022 0.02 Set ChildrenAsleep of GICR_WAKER to 1 and end processing + * : 31.10.2022 0.03 License notation change. + * : 04.04.2023 0.04 Removed stdio.h. + *****************************************************************************/ + +#ifndef GIC_H +#define GIC_H + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ +#include + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ + +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ +/* GIC base */ +#define GICD_BASE (0xF1000000UL) +#define GICR_BASE (GICD_BASE + 0x60000U) + +/* Generic Interrupt Controller Distributor (GICD) */ +#define GICD_CTLR *((volatile uint32_t *)(GICD_BASE + 0x000U)) +#define GICD_IGROUPR(n) *((volatile uint32_t *)(GICD_BASE + 0x080U + 4U*(n))) +#define GICD_ISENABLER(n) *((volatile uint32_t *)(GICD_BASE + 0x100U + 4U*(n))) +#define GICD_ICENABLER(n) *((volatile uint32_t *)(GICD_BASE + 0x180U + 4U*(n))) +#define GICD_ISPENDR(n) *((volatile uint32_t *)(GICD_BASE + 0x200U + 4U*(n))) +#define GICD_ICPENDR(n) *((volatile uint32_t *)(GICD_BASE + 0x280U + 4U*(n))) +#define GICD_IPRIORITYR(n) *((volatile uint32_t *)(GICD_BASE + 0x400U + 4U*(n))) +#define GICD_ICFGR(n) *((volatile uint32_t *)(GICD_BASE + 0xC00U + 4U*(n))) +#define GICD_IGRPMODR(n) *((volatile uint32_t *)(GICD_BASE + 0xD00U + 4U*(n))) +#define GICD_IROUTER(n) *((volatile uint64_t *)(GICD_BASE + 0x6000U + 8U*(n))) + +/* Generic Interrupt Controller Redistributor (GICR) */ +#define GICR_CTLR *((volatile uint32_t *)(GICR_BASE + 0x0000U)) +#define GICR_WAKER *((volatile uint32_t *)(GICR_BASE + 0x0014U)) +#define GICR_PWRR *((volatile uint32_t *)(GICR_BASE + 0x0024U)) + +#define CHILDREN_ASLEEP (1U << 2U) +#define PROCESSOR_SLEEP (1U << 1U) +#define RDPOWER_DOWN (1U << 0U) + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + +/******************************************************************************* +** Function Prototypes ** +*******************************************************************************/ + +/******************************************************************************* +** Macro ** +*******************************************************************************/ + +/******************************************************************************* + * Definitions for CPU system register interface to GICv3 + ******************************************************************************/ +/* ICC_SRE_EL3 */ +#define ICC_SRE_EN_BIT (8U) +#define ICC_SRE_DIB_BIT (4U) +#define ICC_SRE_DFB_BIT (2U) +#define ICC_SRE_SRE_BIT (1U) + +/* SCR_EL3 */ +#define SCR_NS_BIT (1U) + +/* Affinity Leve mask value */ +#define AFFINITY0_MASK (0xFFU) +#define AFFINITY1_MASK (0xFF00U) +#define AFFINITY2_MASK (0xFF0000U) +#define AFFINITY3_MASK (0xFF00000000U) +#define IRM_OFF (0x80000000U) + +/* Get ICC_IAR0 */ +static inline uint64_t get_ICC_IAR0(void) +{ + uint64_t value = 0U; + __asm__ volatile("mrs %0, S3_0_c12_c8_0" : "=r" (value)); + return value; +} + +/* Set ICC_PMR */ +static inline void set_ICC_PMR(uint64_t value) +{ + __asm__ volatile ("msr S3_0_C4_C6_0, %0" :: "r" (value)); +} + +/* Set ICC_IGRPEN0 */ +static inline void set_ICC_IGRPEN0(uint64_t value) +{ + __asm__ volatile ("msr S3_0_c12_c12_6, %0" :: "r" (value)); +} + +/* Set ICC_SRE_EL1 */ +static inline void set_ICC_SRE_EL1(uint64_t value) +{ + __asm__ volatile ("msr S3_0_C12_C12_5, %0" :: "r" (value)); +} + +/* Get ICC_SRE_EL3 */ +static inline uint64_t get_ICC_SRE_EL3(void) +{ + uint64_t value = 0U; + __asm__ volatile("mrs %0, S3_6_C12_C12_5" : "=r" (value)); + return value; +} + +/* Set ICC_SRE_EL3 */ +static inline void set_ICC_SRE_EL3(uint64_t value) +{ + __asm__ volatile ("msr S3_6_C12_C12_5, %0" :: "r" (value)); +} + +/* Get MPIDR_EL1 */ +static inline uint64_t get_MPIDR_EL1(void) +{ + uint64_t value = 0U; + __asm__ volatile("mrs %0, mpidr_el1" : "=r" (value)); + return value; +} + +/* ISB */ +static inline void GIC_isb(void) +{ + __asm__ volatile ("isb"); +} + +/* Enable the interrupt distributor using the GIC's CTLR register */ +static inline void GIC_EnableDistributor(void) +{ + GICD_CTLR |= 0x31U; +} + +/* Disable the interrupt distributor using the GIC's CTLR register */ +static inline void GIC_DisableDistributor(void) +{ + GICD_CTLR &= 0xFFFFFFFEU; +} + +/* Set the interrupt enable from the GIC's ISENABLER register */ +static inline void GIC_SetEnable(uint32_t intid, uint32_t value) +{ + uint32_t reg = GICD_ISENABLER(intid / 32U); + uint32_t shift = (intid % 32U); + + reg &= (~(1U << shift)); + reg |= ( (value & 1U) << shift); + + GICD_ISENABLER(intid / 32U) = reg; +} + +/* Set the interrupt disable from the GIC's ICENABLER register */ +static inline void GIC_SetClearEnable(uint32_t intid, uint32_t value) +{ + uint32_t reg = GICD_ICENABLER(intid / 32U); + uint32_t shift = (intid % 32U); + + reg &= (~(1U << shift)); + reg |= ( (value & 1U) << shift); + + GICD_ICENABLER(intid / 32U) = reg; +} + +/* Sets the interrupt configuration using GIC's ICFGR register */ +static inline void GIC_SetConfiguration(uint32_t intid, uint32_t int_config) +{ + uint32_t icfgr = GICD_ICFGR(intid / 16U); + uint32_t shift = (intid % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= ( int_config << shift); + + GICD_ICFGR(intid / 16U) = icfgr; +} + +/* Set the priority for the given interrupt in the GIC's IPRIORITYR register */ +static inline void GIC_SetPriority(uint32_t intid, uint32_t priority) +{ + uint32_t mask = GICD_IPRIORITYR(intid / 4U); + uint32_t shift = ((intid % 4U) * 8U); + + mask &= (~(0xFFU << shift)); + mask |= ( (priority & 0xFFU) << shift); + + GICD_IPRIORITYR(intid / 4U) = mask; +} + +/* Set the interrupt group from the GIC's IGROUPR register */ +static inline void GIC_SetGroup(uint32_t intid, uint32_t group) +{ + uint32_t igroupr = GICD_IGROUPR(intid / 32U); + uint32_t shift = (intid % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICD_IGROUPR(intid / 32U) = igroupr; +} + +/* Set the interrupt group from the GIC's IGRPMODR register */ +static inline void GIC_SetGrpMode(uint32_t intid, uint32_t mode) +{ + uint32_t imode = GICD_IGRPMODR(intid / 32U); + uint32_t shift = (intid % 32U); + + imode &= (~(1U << shift)); + imode |= ( (mode & 1U) << shift); + + GICD_IGRPMODR(intid / 32U) = imode; +} + +/* Set the interrupt routing from the GIC's IROUTER register */ +static inline void GIC_SetRouter(uint32_t intid) +{ + uint64_t affinity = 0U; + + /* Get Affinity level */ + affinity = get_MPIDR_EL1(); + affinity &= (AFFINITY0_MASK | AFFINITY1_MASK | AFFINITY2_MASK | AFFINITY3_MASK); + /* Interrupt routing mode bit OFF */ + affinity &= (~(IRM_OFF)); + + GICD_IROUTER(intid) = affinity; +} + +/* Get power register value from the GIC's GICR_PWRR register */ +static inline uint32_t GIC_Getpwwr(void) +{ + return (GICR_PWRR); +} + +/* Set power register value from the GIC's GICR_PWRR register */ +static inline void GIC_Setpwwr(uint32_t set_value) +{ + GICR_PWRR = set_value; +} + +/* Get power management cotrol register from the GIC's GICR_WAKER register */ +static inline uint32_t GIC_Getwaker(void) +{ + return (GICR_WAKER); +} + +/* Set power management cotrol register from the GIC's GICR_WAKER register */ +static inline void GIC_Setwaker(uint32_t set_value) +{ + GICR_WAKER = set_value; +} + +/* Enables the given interrupt using GIC's ISENABLER register */ +static inline void GIC_EnableFIQ(uint32_t intid) +{ + + /* Disable interrupt forwarding */ + GIC_DisableDistributor(); + + /* Set level-sensitive */ + GIC_SetConfiguration(intid, 0U); + + /* Set priority */ + GIC_SetPriority(intid, 0U); + + /* Set group 0 (secure) */ + GIC_SetGroup(intid, 0U); + + /* Set group 0 (secure) */ + GIC_SetGrpMode(intid, 0U); + + /* Enable distributor */ + GIC_EnableDistributor(); + + /* Enable the SPI interrupt */ + GIC_SetEnable(intid, 1U); + + /* Set the interrupt routing */ + GIC_SetRouter(intid); +} + +/* Enable the interrupt redistributor wakeup */ +static inline void GIC_WakeupRedistributor(void) +{ + uint32_t get_value = 0U; + uint32_t set_value = 0U; + + get_value = GIC_Getpwwr(); + set_value = get_value & ~(RDPOWER_DOWN); + GIC_Setpwwr(set_value); + + get_value = GIC_Getwaker(); + set_value = get_value & ~(PROCESSOR_SLEEP); + GIC_Setwaker(set_value); + + do + { + get_value = GIC_Getwaker(); + }while((get_value & CHILDREN_ASLEEP) == CHILDREN_ASLEEP); +} + +/* Enable the CPU's interrupt interface */ +static inline void GIC_EnableInterface(void) +{ + uint64_t reg = 0U; + uint64_t icc_sre_el3 = 0U; + + /* Disable the legacy interrupt bypass */ + icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; + + reg = get_ICC_SRE_EL3(); + set_ICC_SRE_EL3(reg | icc_sre_el3); + + set_ICC_SRE_EL1(ICC_SRE_SRE_BIT); + GIC_isb(); + + set_ICC_IGRPEN0(1U); /* enable interface grp0 */ + GIC_isb(); +} + +/* Disable the CPU's interrupt interface */ +static inline void GIC_DisableInterface(uint32_t intid) +{ + uint32_t get_value = 0U; + uint32_t set_value = 0U; + + /* Clear Enable the SPI interrupt */ + GIC_SetClearEnable(intid, 1U); + + /* Set ChildrenAsleep of GICR_WAKER to 1 and end processing */ + get_value = GIC_Getwaker(); + set_value = get_value | PROCESSOR_SLEEP; + GIC_Setwaker(set_value); + + do + { + get_value = GIC_Getwaker(); + }while((get_value & CHILDREN_ASLEEP) != CHILDREN_ASLEEP); + +} + +/* Read the CPU's IAR register */ +static inline uint32_t GIC_AcknowledgePending(void) +{ + return (uint32_t)(get_ICC_IAR0()); +} + +/* Set the interrupt priority mask using CPU's PMR register */ +static inline void GIC_SetInterfacePriorityMask(uint64_t priority) +{ + /* Specify F8. 32 priority levels are bit0-2 invalid */ + set_ICC_PMR(priority << 3U); +} + +/* Initialize and enable the GIC */ +static inline void GIC_Enable(void) +{ + GIC_WakeupRedistributor(); + /* Enable interface */ + GIC_EnableInterface(); + /* Set priority mask */ + GIC_SetInterfacePriorityMask(0xFFUL); +} + +/******************************************************************************* +** Function ** +*******************************************************************************/ +/* Interrupt configuration */ +#define Interrupt_Config(void) GIC_Enable(void) + +/* Enable */ +#define Interrupt_Enable(intid) GIC_EnableFIQ((uint32_t)intid) + +/* Disable */ +#define Interrupt_Disable(intid) GIC_DisableInterface((uint32_t)intid) + +#endif /* GIC_H */ +/******************************************************************************* +** End of File ** +*******************************************************************************/ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/hscif_register.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/hscif_register.h new file mode 100644 index 0000000..1eb9ae9 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/hscif_register.h @@ -0,0 +1,61 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : HSCIF register header + ******************************************************************************/ +/****************************************************************************** + * @file hscif_register.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +#ifndef HSCIF_REGISTER_H_ +#define HSCIF_REGISTER_H_ + +#include + +/* HSCIF0 base address */ +/* 0xE6540000U */ +#define HSCIF0_BASE (BASE_HSCIF_ADDR) + +#define HSCIF_HSSMR (HSCIF0_BASE + 0x0000U) /* 16 Serial mode register */ +#define HSCIF_HSBRR (HSCIF0_BASE + 0x0004U) /* 8 Bit rate register */ +#define HSCIF_HSSCR (HSCIF0_BASE + 0x0008U) /* 16 Serial control register */ +#define HSCIF_HSFTDR (HSCIF0_BASE + 0x000CU) /* 8 Transmit FIFO data register */ +#define HSCIF_HSFSR (HSCIF0_BASE + 0x0010U) /* 16 Serial status register */ +#define HSCIF_HSFCR (HSCIF0_BASE + 0x0018U) /* 16 FIFO control register */ +#define HSCIF_HSLSR (HSCIF0_BASE + 0x0024U) /* 16 Line status register */ +#define HSCIF_DL (HSCIF0_BASE + 0x0030U) /* 16 Frequency division register */ +#define HSCIF_CKS (HSCIF0_BASE + 0x0034U) /* 16 Clock Select register */ +#define HSCIF_HSSRR (HSCIF0_BASE + 0x0040U) /* 16 Sampling rate register */ + +#endif /* HSCIF_REGISTER_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/image_load.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/image_load.h new file mode 100644 index 0000000..b996256 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/image_load.h @@ -0,0 +1,272 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file image_load.h + * - Version : 0.09 + * @brief Access protection setting driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 10.02.2022 0.02 Change the number of CA programs + * : 17.02.2022 0.03 Support AArch32 + * : 18.05.2022 0.04 Integrated LOAD_INFO + * Defined value integration + * Remove unused define values + * Changed to processing for each device + * Change structure member name + * Remove LOGICAL_CONTENT_CERT_ADDR + * Add get_logic_cont_cert_addr + * Change the argument type of get_src_addr_offset_in_cert + * Added argument check + * Remove unnecessary macros + * Add argument of load_init() + * Change for memory map update + * : 16.06.2022 0.05 Change log output + * Support secure boot for S4 + * : 31.10.2022 0.06 License notation change. + * : 21.08.2023 0.07 Add support for V4M. + * : 19.12.2024 0.08 Add definitions for RTOS#1 and RTOS#2. + * : 26.05.2025 0.09 Change address and size of CA program2. + *****************************************************************************/ + +#ifndef LOAD_IMAGE_H_ +#define LOAD_IMAGE_H_ + +#include "log.h" + +/* define */ +/* For Build Option RTOS_LOAD_NUM */ +#define RTOS_LOAD_NUM_1 (1U) /* RTOS is RTOS#0 only. */ +#define RTOS_LOAD_NUM_3 (3U) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */ + +/* For Build Option OPTEE_LOAD_ENABLE */ +#define OPTEE_DISABLE (0U) /* Load OP-TEE image disable. */ +#define OPTEE_ENABLE (1U) /* Load OP-TEE image enable. */ + +/* For Build Option BL2_LOAD_ENABLE */ +#define BL2_DISABLE (0U) /* Load BL2 image disable. */ +#define BL2_ENABLE (1U) /* Load BL2 image enable. */ + +/* For Build Option QNX_OS_LOAD_ENABLE */ +#define QNX_OS_DISABLE (0U) /* Load QNX_OS image disable. */ +#define QNX_OS_ENABLE (1U) /* Load QNX_OS image enable. */ + +/* DRAM address */ +#define DRAM_BASE (0x40000000U) +#define DRAM_SIZE (0x80000000U) +#define DRAM_END ((DRAM_BASE + DRAM_SIZE) - 1U) + +/* RT-SRAM */ +/* S4:RT-SRAM V4H/V4M:RT-VRAM0 Mirror */ +#define RTSRAM_BASE (0xEB200000U) +#define RTSRAM_SIZE ((1024U - 16U) * 1024U) /* 1MB - 16KB(stack size) */ +#define RTSRAM_END ((RTSRAM_BASE + RTSRAM_SIZE) - 1U) + +/* RT-VRAM */ +/* S4:RT-VRAM V4H/V4M:RT-VRAM1 */ +#define RTVRAM_BASE (0xE2000000U) +#define RTVRAM_SIZE (1024U * 1024U) /* 1MB */ +#define RTVRAM_VBUF_28M (28U) /* 28MB */ +#define RTVRAM_VBUF_SIZE ((RTVRAM_VBUF_28M - 1U) * 1024U * 1024U) /* 3MB to 27MB (The first 1MB is actual RAM.) */ +#define RTVRAM_VBUF_TOP (RTVRAM_BASE + RTVRAM_SIZE) /* 0xE2100000 */ +#define RTVRAM_VBUF_END ((RTVRAM_VBUF_TOP + RTVRAM_VBUF_SIZE) - 1U) +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RTVRAM_8WAY_28M_SRAM_SIZE (0x00010000U) /* 64KiB */ +#define RTVRAM_SRAM_TOP (RTVRAM_BASE) +#define RTVRAM_SRAM_END (RTVRAM_SRAM_TOP + RTVRAM_8WAY_28M_SRAM_SIZE - 1U) /* 0xE2000000 - 0xE200FFFF */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* System RAM */ +#define SYSRAM_BASE (0xE6300000U) +#if (RCAR_LSI == RCAR_S4) +#define SYSRAM_SIZE (384U * 1024U) /* 384KB */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define SYSRAM_SIZE (1024U * 1024U) /* 1MB */ +#endif /* RCAR_LSI == RCAR_S4 */ +#define SYSRAM_END ((SYSRAM_BASE + SYSRAM_SIZE) - 1U) + +/* Cx Loader */ +#define IPL_TOP (0xE6300000U) +#define IPL_SIZE (0x00030000U) /* 192KiB */ +#define IPL_END ((IPL_TOP +IPL_SIZE) - 1U) + +/* Certificate size */ +#define CONTENT_CERT_OFFSET (0x00006000U) /* certificate top offset */ +#define CONTENT_CERT_INFO_SIZE (0x00001000U) /* Content cert header area size(4KiB) */ +#define CONTENT_CERT_DST_SIZE (0x00000800U) /* content cert dst size */ +#define KEY_CERT_SIZE (0x00002000U) /* Key cert area size(8KiB) */ + +/* Load ID */ +#define RTOS_ID (1U) +#define CA_PROGRAM_ID (2U) +#define CA_OPTIONAL_ID (6U) +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RTOS1_ID (16U) /* 16:RTOS#1 */ +#define RTOS2_ID (17U) /* 17:RTOS#2 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* Number of Max loading image */ +#define CA_MAX_IMAGE (8U) /* CA Load program MAX image num */ +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1) +#define MAX_PLACED (16U) /* Load program MAX image num */ +#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define MAX_PLACED (18U) /* Load program MAX image num */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_1 */ + +#define TARGET_MEM_DRAM (0U) +#define TARGET_MEM_RTSRAM (1U) +#define TARGET_MEM_RTVRAM (2U) +#define TARGET_MEM_SYSRAM (3U) +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define TARGET_MEM_SRAM_IN_RTVRAM (4U) +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* get info from cert address offset */ +#define CERT_INFO_SIZE_OFFSET (0x00000264U) /* Offset Type1 */ +#define CERT_INFO_DST_OFFSET (0x00000154U) /* Offset Type1 */ +#define CERT_INFO_SIZE_OFFSET1 (0x00000364U) /* Offset Type2 */ +#define CERT_INFO_DST_OFFSET1 (0x000001D4U) /* Offset Type2 */ +#define CERT_INFO_SIZE_OFFSET2 (0x00000464U) /* Offset Type2 */ +#define CERT_INFO_DST_OFFSET2 (0x00000254U) /* Offset Type2 */ + +/* Certificate logical address */ +#define CONTENT_CERT_DEST_ADDR (0xEB230000U) +#define CONTENT_CERT_DEST_SIZE (0x00008000U) /* 32KB */ + +/* BL31/BL32(S4), BL31/tee-OS/u-boot(V4H) check */ +/* check image num */ +#ifdef MOBIS_PRK3 + #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + #error "OPTEE_LOAD_ENABLE==1 should be for PRK3" + #endif + #if (BL2_LOAD_ENABLE == BL2_DISABLE) + #error "BL2_LOAD_ENABLE==1 should be for PRK3" + #endif + #if (QNX_OS_LOAD_ENABLE == QNX_OS_DISABLE) + #error "QNX_OS_LOAD_ENABLE==1 should be for PRK3" + #endif +#define CA_IMAGESIZECHK_DEF (5U) +#else +#define CA_IMAGESIZECHK_DEF (2U) +#endif +/* load_id */ +#define CA_PROGRAM1_ID (6U) /* bl31 */ +#define CA_PROGRAM2_ID (7U) /* u-boot */ +#define CA_PROGRAM3_ID (8U) /* tee-os */ +#define CA_PROGRAM4_ID (9U) /* ca76-loader */ +#define CA_PROGRAM5_ID (10U) /* qnx OS */ +#define CA_BL2_ID CA_PROGRAM4_ID +#define CA_QNX_OS_ID CA_PROGRAM5_ID + +#define CA_PROGRAM1_ADR (0x46400000U) +#define CA_PROGRAM1_SIZE (0x00022000U) +#if (RCAR_LSI == RCAR_S4) +#define CA_PROGRAM2_ADR (0x44100000U) +#define CA_PROGRAM2_SIZE (0x00100000U) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define CA_PROGRAM2_ADR (0x00000000U) +#define CA_PROGRAM2_SIZE (0x00000000U) +#endif /* RCAR_LSI == RCAR_S4 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) +#define CA_PROGRAM3_ADR (0x44100000U) +#define CA_PROGRAM3_SIZE (0x00100000U) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ +#if (BL2_LOAD_ENABLE == BL2_ENABLE) +#define CA_PROGRAM4_ADR (0x41D00000U) +#define CA_PROGRAM4_SIZE (0x00020000U) /* 128KB */ +#endif /* BL2_LOAD_ENABLE == BL2_ENABLE */ +#if (QNX_OS_LOAD_ENABLE == QNX_OS_ENABLE) +#define CA_PROGRAM5_ADR (0x50100000U) +#define CA_PROGRAM5_SIZE (0x00800000U) /* 8MB */ +#endif /* QNX_OS_LOAD_ENABLE == QNX_OS_ENABLE */ + +/* key cert address */ +#define TFMV_KEY_CERT_ADDR (CONTENT_CERT_DEST_ADDR + CONTENT_CERT_INFO_SIZE) /* 0xEB231000 */ +#define NTFMV_KEY_CERT_ADDR (TFMV_KEY_CERT_ADDR + KEY_CERT_SIZE) /* 0xEB233000 */ + +/* struct */ +/* load image range */ +typedef struct { + uint32_t load_id; + uint32_t image_adr; + uint32_t image_size; +} IMAGE_RANGE; + +/* load address range */ +typedef struct { + uint32_t cx_topadd; + uint32_t cx_endadd; +} ADDRESS_RANGE; + +/* load info */ +typedef struct{ + const char *name; /* store load image name */ + uint32_t image_size; /* store image size */ + uint32_t boot_addr; /* store boot address of image */ + uint32_t key_cert_addr; /* store key cert address */ + uint32_t cnt_cert_addr; /* store content cert address */ + uint32_t src_addr; /* store source address */ + uint32_t part_num; /* store eMMC partition number */ + uint32_t load_id; /* store Load ID */ + uint32_t cmac[4U]; /* store cmac */ + +} LOAD_INFO; + +static inline uint32_t get_src_addr_offset_in_cert(uint32_t id) +{ + /* INT30-C Pre confirmation */ + if (id > UINT32_MAX / 0x10U) + { + ERROR("get_src_addr_offset_in_cert id error.\n"); + panic; + } + + return (CONTENT_CERT_DEST_ADDR + ((id * 0x10U) + 0x8U)); +} + +static inline uint32_t get_logic_cont_cert_addr(uint32_t num) +{ + /* INT30-C Pre confirmation */ + if (num > UINT32_MAX / 0x10U) + { + ERROR("get_logic_cont_cert_addr num error.\n"); + panic; + } + return (CONTENT_CERT_DEST_ADDR + CONTENT_CERT_OFFSET + (num * CONTENT_CERT_DST_SIZE)); +} + +/* Prototype */ +void load_image(LOAD_INFO* li); +void load_init(LOAD_INFO* li, uint32_t num); +void load_update_part_num(LOAD_INFO* li, uint32_t num, int slot); +void load_start(LOAD_INFO* li); +#endif /* LOAD_IMAGE_H_ */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/image_load_emmc.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/image_load_emmc.h new file mode 100644 index 0000000..45aae02 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/image_load_emmc.h @@ -0,0 +1,113 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Image load function for eMMC header + ******************************************************************************/ +/****************************************************************************** + * @file image_load_emmc.h + * - Version : 0.05 + * @brief Access protection setting driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 17.02.2022 0.02 Support AArch32 + * : 10.05.2022 0.03 Defined value integration + * Change the argument type of get_part_num_in_cert + * Added argument check + * Changed define name + * Change log output + * Change the direct value reference + * Remove Prototype + * : 08.07.2022 0.04 Change log output + * Adds the defined used in the emmc_trans_data argument + * : 31.10.2022 0.05 License notation change. + *****************************************************************************/ + +#ifndef LOAD_IMAGE_EMMC_H_ +#define LOAD_IMAGE_EMMC_H_ + +#include +#include + +/* define */ +/* eMMC */ +#define CX_EMMC_TOP (0x00000000U) +#define CX_EMMC_BOOT_PART_SIZE (31U * 1024U * 1024U) /* 31MB */ +#define CX_EMMC_END ((CX_EMMC_TOP + CX_EMMC_BOOT_PART_SIZE) - 1U) +#define SRC_TOP (CX_EMMC_TOP) + +/* For eMMC */ +#define CX_EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */ +#define CX_EMMC_SECTOR_SIZE (512U) +#define CX_EMMC_CONTENT_CERT_ADDR (0x00240000U) +#define CX_EMMC_CONTENT_CERT_SECTOR_NUMBER (CX_EMMC_CONTENT_CERT_ADDR >> CX_EMMC_SECTOR_SIZE_SHIFT) + +/* A side certificate setting */ +/* RT-SRAM Offset */ +#define SEC_BOOT_KEY_CERT_OFFSET (0x00001000U) +#define SEC_DEBUG_SEC_CERT_OFFSET (0x00006000U) + +/* A side RT-SRAM physical address */ +/* RT-SRAM(0xEB200000) + CERT_OFFSET */ +#define SEC_BOOT_KEY_CERT_ADDR (ADDR_RT_SRAM_TOP + SEC_BOOT_KEY_CERT_OFFSET) + +/* A/B side certificate setting */ +/* Boot side Offset */ +#define CERT_OFFSET_2ND (0x8000U) + +/* A/B side RT-SRAM physical address */ +/* RT-SRAM(0xEB200000) + CERT_OFFSET (+ 2nd OFFSET)*/ +#define GET_SEC_BOOT_KEY_CERT_ADDR(a) ((SEC_BOOT_KEY_CERT_ADDR) + ((CERT_OFFSET_2ND) * (a))) + +#define SEC_DEBUG_CERT_SIZE (6396U) + + +static inline void load_image_info_print_for_emmc(LOAD_INFO* li) +{ + + NOTICE("======== %s image load info ========\n", li->name); + NOTICE("load address \t= 0x%x\n" "image size \t= 0x%x\n" + "source address \t= (p:%u)0x%x\n", + (unsigned int)li->boot_addr, (unsigned int)(li->image_size), + (unsigned int)li->part_num, (unsigned int)li->src_addr ); +} + +static inline uint32_t get_part_num_in_cert(uint32_t id) +{ + /* INT30-C Pre confirmation */ + if (UINT32_MAX - id < 1U) + { + ERROR("get_part_num_in_cert id error.\n"); + panic; + } + + return (CONTENT_CERT_DEST_ADDR + ((id + 1U) * 0x10U)); +} + +#endif /* LOAD_IMAGE_EMMC_H_ */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/inline_asm.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/inline_asm.h new file mode 100644 index 0000000..d74e80d --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/inline_asm.h @@ -0,0 +1,55 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : inline asm func header + ******************************************************************************/ + +#ifndef INLINE_ASM_H__ +#define INLINE_ASM_H__ + +#if defined(__RH850G3K__) +static inline void syncm(void) +{ + __asm__ __volatile__ ("SYNCM"); +} + +static inline void synci(void) +{ + __asm__ __volatile__ ("SYNCI"); +} +#else +static inline void syncm(void) +{ + __asm__ volatile ("dsb"); +} + +static inline void synci(void) +{ + __asm__ volatile ("dsb"); + __asm__ volatile ("isb"); +} + +#endif + +#endif /* INLINE_ASM_H__ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/interrupt.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/interrupt.h new file mode 100644 index 0000000..e950bad --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/interrupt.h @@ -0,0 +1,56 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : INTC header + ******************************************************************************/ +/****************************************************************************** + * @file interrupt.h + * - Version : 0.05 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + * : 15.12.2022 0.03 V4H interrupt support. + * : 27.12.2022 0.04 Change argument of pabort_error. + * : 21.08.2023 0.05 Add support for V4M. + *****************************************************************************/ +#ifndef INTERRUPT_H_ +#define INTERRUPT_H_ + +/* Prototype */ +#if (RCAR_LSI == RCAR_S4) +extern void handler_fiq(void); +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +void dabort_error(uint32_t occ_add, uint32_t dfsr, uint32_t dfar); +void pabort_error(uint32_t ifsr, uint32_t ifar); +void Undefined_error(uint32_t occ_add); +#endif /* RCAR_LSI == RCAR_S4 */ +extern void handler_error(uint32_t ex_type); + +#endif /* INTERRUPT_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/ip_control.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/ip_control.h new file mode 100644 index 0000000..99472bb --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/ip_control.h @@ -0,0 +1,51 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : IP's control header + ******************************************************************************/ +/****************************************************************************** + * @file ip_control.h + * - Version : 0.03 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 02.08.2022 0.02 Added define value + * : 31.10.2022 0.03 License notation change. + *****************************************************************************/ + +#ifndef IP_CONTROL_H_ +#define IP_CONTROL_H_ + +#define INTC_SPI_SWDT (548U) + +/* Prototype */ +void ip_init(void); +void ip_release(void); + +#endif /* IP_CONTROL_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/loader_main.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/loader_main.h new file mode 100644 index 0000000..03fb61a --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/loader_main.h @@ -0,0 +1,85 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Loader main header + ******************************************************************************/ +/****************************************************************************** + * @file loader_main.h + * - Version : 0.34 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 18.02.2022 0.02 Updated IPL_VERSION 0.7.0 + * : 22.03.2022 0.03 Updated IPL_VERSION 0.8.0 + * : 20.05.2022 0.04 Updated IPL_VERSION 0.9.0 + * : 12.07.2022 0.05 Updated IPL_VERSION 0.11.0 + * : 22.08.2022 0.06 Updated IPL_VERSION 0.12.0 + * : 03.10.2022 0.07 Updated IPL_VERSION 0.13.0 + * : 27.10.2022 0.08 Updated IPL_VERSION 0.14.0 + * : 31.10.2022 0.09 License notation change. + * : 07.11.2022 0.10 Removed unnecessary define values. + * : 14.12.2022 0.11 Updated IPL_VERSION 0.15.0 + * : 08.02.2023 0.12 Updated IPL_VERSION 0.17.0 + * : 17.02.2023 0.13 Updated IPL_VERSION 0.17.1 + * : 24.04.2023 0.14 Updated IPL_VERSION 0.18.0 + * : 22.05.2023 0.15 Updated IPL_VERSION 0.19.0 + * : 19.06.2023 0.16 Updated IPL_VERSION 0.21.0 + * : 22.08.2023 0.17 Updated IPL_VERSION 1.25.0 + * : 19.09.2023 0.18 Updated IPL_VERSION 1.30.0 + * : 23.10.2023 0.19 Updated IPL_VERSION 1.31.0 + * : 17.11.2023 0.20 Updated IPL_VERSION 1.41.0 + * : 26.01.2024 0.21 Updated IPL_VERSION 1.42.0 + * : 07.02.2024 0.22 Updated IPL_VERSION 1.44.0 + * : 05.04.2024 0.23 Updated IPL_VERSION 1.45.0 + * : 11.06.2024 0.24 Updated IPL_VERSION 1.48.0 + * : 19.08.2024 0.25 Updated IPL_VERSION 1.50.0 + * : 19.09.2024 0.26 Updated IPL_VERSION 1.51.2 + * : 22.10.2024 0.27 Updated IPL_VERSION 1.52.0 + * : 23.10.2024 0.28 Updated IPL_VERSION 1.53.0 + * : 28.10.2024 0.29 Updated IPL_VERSION 1.53.1 + * : 28.10.2024 0.30 Updated IPL_VERSION 1.54.0 + * : 05.12.2024 0.31 Updated IPL_VERSION 1.55.0 + * : 08.01.2025 0.32 Updated IPL_VERSION 1.56.0 + * : 09.04.2025 0.33 Updated IPL_VERSION 1.57.0 + * : 26.05.2025 0.34 Updated IPL_VERSION 1.58.0 + *****************************************************************************/ + +#ifndef LOADER_MAIN_H_ +#define LOADER_MAIN_H_ + +/* define */ +#define IPL_VERSION "1.58.0" + +/* Global */ +extern const char build_message[]; + +/* prototype */ +uint32_t loader_main(void); + +#endif /* LOAD_MAIN_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/loader_main_common.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/loader_main_common.h new file mode 100644 index 0000000..646558e --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/loader_main_common.h @@ -0,0 +1,43 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main common header + ******************************************************************************/ + +#ifndef LOADER_MAIN_COMMON_H_ +#define LOADER_MAIN_COMMON_H_ + +#include + +/* prototype */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + void smoni_set_param(uintptr_t smoni_entry_point, + uintptr_t uboot_entry_point); +#else +void smoni_set_param(uintptr_t smoni_entry_point, + uintptr_t uboot_entry_point, + uintptr_t tee_entry_point); +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + +#endif /* LOADER_MAIN_COMMON_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/loader_mmu_table.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/loader_mmu_table.h new file mode 100644 index 0000000..27e3f99 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/loader_mmu_table.h @@ -0,0 +1,80 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + +/******************************************************************************* + * DESCRIPTION : Definitions used by the MMU. + ******************************************************************************/ +/****************************************************************************** + * @file loader_mmu_table.h + * - Version : 0.01 + * @brief MMU define. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 14.12.2022 0.01 First Release +*****************************************************************************/ + +#ifndef MMU_TABLE_H_ +#define MMU_TABLE_H_ + +#include /* for uint32_t */ + +/* b[1:0] Block and Table descriptors */ +#define MMU_TBL_TYPE_TABLE (3UL << 0) +#define MMU_TBL_TYPE_BLOCK (1UL << 0) +#define MMU_TBL_TYPE_PAGE (3UL << 0) + +/* Lower attributes:SH[1:0] unused */ +#define MMU_TBL_BLOCK_OUTER_SHARE (2ULL << 8) +#define MMU_TBL_BLOCK_INNER_SHARE (3ULL << 8) + +/* Lower attributes:AF[10] */ +#define MMU_TBL_BLOCK_AF (1UL << 10) + +/* Lower attributes:AP[2:1] access permissions model */ +#define MMU_TBL_AP_APP_RW (1UL << 6) +#define MMU_TBL_AP_APP_R (3UL << 6) + +/* Lower attributes:AttrIndx[2:0] */ +#define MMU_TBL_ATTRINDX0 (0UL << 2) /* Device-nGnRnE memory */ +#define MMU_TBL_ATTRINDX1 (1UL << 2) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */ +#define MMU_TBL_ATTRINDX2 (2UL << 2) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */ + +/* Upper attributes:Block descriptors */ +#define MMU_TBL_BLOCK_XN (1UL << 54) + +#define MMU_TBL_BLOCK_NOEXEC_DEVICE (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX0 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK) +#define MMU_TBL_BLOCK_EXECREAD_MEMORY ( MMU_TBL_AP_APP_R | MMU_TBL_ATTRINDX1 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK) +#define MMU_TBL_BLOCK_NOEXEC_MEMORY (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX2 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK) +/* Level 3 */ +#define MMU_TBL_PAGE_NOEXEC_DEVICE (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX0 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE) +#define MMU_TBL_PAGE_EXECREAD_MEMORY ( MMU_TBL_AP_APP_R | MMU_TBL_ATTRINDX1 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE) +#define MMU_TBL_PAGE_NOEXEC_MEMORY (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX2 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE) + +extern const uint64_t g_loader_level1_table[]; +extern const uint64_t g_loader_level2_table[]; +extern const uint64_t g_loader_level3_table[]; + +#endif /* MMU_TABLE_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/log.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/log.h new file mode 100644 index 0000000..52c252d --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/log.h @@ -0,0 +1,101 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : log header file + ******************************************************************************/ +/****************************************************************************** + * @file log.h + * - Version : 0.06 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 12.05.2022 0.02 Changed __LOG_H__ to LOG_H_ + * Changed panic (Static analysis) + * : 16.06.2022 0.03 Change log output + * : 31.10.2022 0.04 License notation change. + * : 07.11.2022 0.05 Change log macro. + * : 04.04.2023 0.06 Removed stdio.h. + *****************************************************************************/ +#ifndef LOG_H_ +#define LOG_H_ + +#include + +#define LOG_NONE (0) +#define LOG_ERROR (1) +#define LOG_NOTICE (2) +#define LOG_WARNING (3) +#define LOG_INFO (4) +#define LOG_VERBOSE (5) + + +#if LOG_LEVEL >= LOG_NOTICE +# define NOTICE(...) log_printf("N:" __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#if LOG_LEVEL >= LOG_ERROR +# define ERROR(...) log_printf("E:" __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_WARNING +# define WARN(...) log_printf("W:" __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_INFO +# define INFO(...) log_printf("I:" __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_VERBOSE +# define VERBOSE(...) log_printf("V:" __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + + +#define panic \ + do { \ + log_printf("P:%s\n", __func__); \ + while(true){} \ + } while (false) + + +void log_printf(const char *fmt, ...); + +void gpio_N1307(int set); +void gpio_N1305(int set); + +#endif /* LOG_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/mem_io.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/mem_io.h new file mode 100644 index 0000000..922e7d3 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/mem_io.h @@ -0,0 +1,104 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Memory access driver header + ******************************************************************************/ +/****************************************************************************** + * @file mem_io.h + * - Version : 0.05 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 17.02.2022 0.02 Change the return type of mem_read64 + * : 31.10.2022 0.03 License notation change. + * : 07.11.2022 0.04 Added to convert mmio. + * : 21.08.2023 0.05 Add support for V4M. + *****************************************************************************/ +#ifndef MEM_IO_H_ +#define MEM_IO_H_ + +#include + +static inline void mem_write8(uintptr_t addr, uint8_t data) +{ + *(volatile uint8_t*)addr = data; +} + +static inline uint8_t mem_read8(uintptr_t addr) +{ + return (*(volatile uint8_t*)addr); +} + +static inline void mem_write16(uintptr_t addr, uint16_t data) +{ + *(volatile uint16_t*)addr = data; +} + +static inline uint16_t mem_read16(uintptr_t addr) +{ + return (*(volatile uint16_t*)addr); +} + +static inline void mem_write32(uintptr_t addr, uint32_t data) +{ + *(volatile uint32_t*)addr = data; +} + +static inline uint32_t mem_read32(uintptr_t addr) +{ + return (*(volatile uint32_t*)addr); +} + +static inline void mem_write64(uintptr_t addr, uint64_t data) +{ + *(volatile uint64_t*)addr = data; +} + +static inline uint64_t mem_read64(uintptr_t addr) +{ + return (*(volatile uint64_t*)addr); +} + +static inline void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set) +{ + mem_write32(addr, (mem_read32(addr) & ~clr) | set); +} + +static inline void mem_bitset32(uintptr_t addr, uint32_t set) +{ + mem_write32(addr, (mem_read32(addr) | set) ); +} + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define mmio_write_32(a,b) mem_write32(a,b) +#define mmio_read_32(a) mem_read32(a) +#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c) +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + +#endif /* MEM_IO_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/qos.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/qos.h new file mode 100644 index 0000000..057fcee --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/qos.h @@ -0,0 +1,33 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : QoS driver header + ******************************************************************************/ + +#ifndef QOS_INIT_H_ +#define QOS_INIT_H_ + +extern void qos_init(void); + +#endif /* QOS_INIT_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/ram_protection.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/ram_protection.h new file mode 100644 index 0000000..3568486 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/ram_protection.h @@ -0,0 +1,150 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2024-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RAM protection driver header + ******************************************************************************/ +#ifndef RAM_PROTECTION_H_ +#define RAM_PROTECTION_H_ + +#include +#include + +#define RTVRAM0_AREA1_TOP (0xE0040000U) +#define RTVRAM0_ADDR_END (0xE0100000U) + +#define RTVRAM1_AREA1_TOP (0xE2010000U) +#define RTVRAM1_AREA2_TOP (0xE2100000U) +#define RTVRAM1_ADDR_END (0xE3C00000U) + +#define SYSTEM_RAM_AREA1_TOP (0xE635E000U) +#define SYSTEM_RAM_AREA2_TOP (0xE6360000U) +#define SYSTEM_RAM_ADDR_END (0xE6400000U) + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define DRAM_ADDR_AREA1 (0x0401C00000ULL) +#define DRAM_ADDR_AREA2 (0x0401D00000ULL) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define DRAM_ADDR_AREA3 (0x0406400000ULL) +#define DRAM_ADDR_AREA4 (0x0406440000ULL) +#define DRAM_ADDR_AREA5 (0x0407FC0000ULL) +#define DRAM_ADDR_AREA6 (0x0408000000ULL) +#define DRAM_ADDR_AREA7 (0x041DC00000ULL) +#define DRAM_ADDR_AREA8 (0x0420000000ULL) +#define DRAM_ADDR_AREA9 (0x0440000000ULL) +#define DRAM_ADDR_AREA10 (0x0460000000ULL) +#define DRAM_ADDR_AREA11 (0x0480000000ULL) +#define DRAM_ADDR_AREA12 (0x0500000000ULL) +#define DRAM_ADDR_AREA13 (0x0600000000ULL) +#else +#define DRAM_ADDR_AREA3 (0x0404100000ULL) +#define DRAM_ADDR_AREA4 (0x0406400000ULL) +#define DRAM_ADDR_AREA5 (0x0406440000ULL) +#define DRAM_ADDR_AREA6 (0x0407E00000ULL) +#define DRAM_ADDR_AREA7 (0x0407F00000ULL) +#define DRAM_ADDR_AREA8 (0x0407FC0000ULL) +#define DRAM_ADDR_AREA9 (0x0408000000ULL) +#define DRAM_ADDR_AREA10 (0x041DC00000ULL) +#define DRAM_ADDR_AREA11 (0x0420000000ULL) +#define DRAM_ADDR_AREA12 (0x0440000000ULL) +#define DRAM_ADDR_AREA13 (0x0460000000ULL) +#define DRAM_ADDR_AREA14 (0x0480000000ULL) +#define DRAM_ADDR_AREA15 (0x0500000000ULL) +#define DRAM_ADDR_AREA16 (0x0600000000ULL) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + +#else +#define DRAM_ADDR_AREA1 (0x0401C00000ULL) +#define DRAM_ADDR_AREA2 (0x0406400000ULL) +#define DRAM_ADDR_AREA3 (0x0406440000ULL) +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ +#define DRAM_ADDR_END (0x0700000000ULL) + +#define NOT_USED_VALUE (0x00000000U) + +/* RAM DIVISION AREA ID */ +/* RT-SRAM */ +#define RTVRAM0_ICUMX_IPL_AREA (0U) /* 0xEB200000 -- 0xEB23FFFF */ +#define RTVRAM0_ICUMX_FW_AREA (1U) /* 0xEB240000 -- 0xEB2FFFFF */ +/* RT-VRAM */ +#define RTVRAM1_BLANK_AREA (0U) /* 0xE2000000 -- 0xE200FFFF */ +#define RTVRAM1_EXTEND_CACHE_AREA (1U) /* 0xE2010000 -- 0xE20FFFFF */ +#define RTVRAM1_RTOS_AREA (2U) /* 0xE2100000 -- 0xE3BFFFFF */ +/* System RAM */ +#define SYSTEM_RAM_CX_2ND_IPL (0U) /* 0xE6300000 -- 0xE635DFFF */ +#define SYSTEM_RAM_SHARED_MEM (1U) /* 0xE635E000 -- 0xE635FFFF */ +/* SDRAM */ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define RTVRAM1_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */ +#define CR_FW_SHARED_AREA (1U) /* 0x04_01C00000 -- 0x04_01CFFFFF */ +#define SDRAM_BLANK_AREA (2U) /* OPTEE_DISABLE:0x04_01D00000 -- 0x04_063FFFFF + * OPTEE_ENABLE :0x04_01D00000 -- 0x04_040FFFFF */ +#define SDRAM_PROTECT_AREA (3U) /* OPTEE_DISABLE:0x04_06400000 -- 0x04_0643FFFF + * OPTEE_ENABLE :0x04_04100000 -- 0x04_0643FFFF */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define SDRAM_PUBLIC_AREA (4U) /* 0x04_06440000 -- 0x04_07FBFFFF */ +#define ICCOM_USED_AREA (5U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */ +#define LINUX_USED_AREA (6U) /* 0x04_08000000 -- 0x04_1DBFFFFF */ +#define CAAREA2_USED_AREA (7U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */ +#define CR52_USED_AREA (8U) /* 0x04_20000000 -- 0x04_3FFFFFFF */ +#define CAAREA3_USED_AREA (9U) /* 0x04_40000000 -- 0x04_5FFFFFFF */ +#define CAAREA2_USED_AREA2 (10U) /* 0x04_60000000 -- 0x04_7FFFFFFF */ +#define CAAREA1_USED_AREA (11U) /* 0x04_80000000 -- 0x04_FFFFFFFF */ +#else +#define SDRAM_PROTECT_AREA2 (4U) /* 0x04_06400000 -- 0x04_0643FFFF */ +#define SDRAM_BLANK_AREA2 (5U) /* 0x04_06440000 -- 0x04_07DFFFFF */ +#define OPTEE_SHARED_AREA (6U) /* 0x04_07E00000 -- 0x04_07EFFFFF */ +#define SDRAM_BLANK_AREA3 (7U) /* 0x04_07F00000 -- 0x04_07FBFFFF */ +#define ICCOM_USED_AREA (8U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */ +#define LINUX_USED_AREA (9U) /* 0x04_08000000 -- 0x04_1DBFFFFF */ +#define CAAREA2_USED_AREA (10U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */ +#define CR52_USED_AREA (11U) /* 0x04_20000000 -- 0x04_3FFFFFFF */ +#define CAAREA3_USED_AREA (12U) /* 0x04_40000000 -- 0x04_5FFFFFFF */ +#define CAAREA2_USED_AREA2 (13U) /* 0x04_60000000 -- 0x04_7FFFFFFF */ +#define CAAREA1_USED_AREA (14U) /* 0x04_80000000 -- 0x04_FFFFFFFF */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#if (RCAR_LSI == RCAR_V4H) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define RESERVERD_AREA (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define CAAREA1_USED_AREA2 (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#else +#define RESERVERD_AREA (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define CAAREA1_USED_AREA2 (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#elif (RCAR_LSI == RCAR_V4M) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define CAAREA1_USED_AREA2 (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define RESERVERD_AREA (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#else +#define CAAREA1_USED_AREA2 (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define RESERVERD_AREA (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#endif /* RCAR_LSI == RCAR_V4H */ +#else +#define RTVRAM1_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */ +#define SDRAM_BLANK_AREA (1U) /* 0x04_01C00000 -- 0x04_063FFFFF */ +#define SDRAM_PROTECT_AREA (2U) /* 0x04_06400000 -- 0x04_0643FFFF */ +#define SDRAM_PUBLIC_AREA (3U) /* 0x04_06440000 -- 0x06_FFFFFFFF */ +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +#endif /* RAM_PROTECTION_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/rcar_def.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/rcar_def.h new file mode 100644 index 0000000..8ddcbfa --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/rcar_def.h @@ -0,0 +1,66 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : R-Car common header + ******************************************************************************/ +/****************************************************************************** + * @file rcar_def.h + * - Version : 0.05 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 17.02.2022 0.02 Support V4H + * : 31.10.2022 0.03 License notation change. + * : 23.05.2023 0.04 Add the define "PRR_PRODUCT_21" for V4H v2.1. + * : 21.08.2023 0.05 Add support for V4M. + *****************************************************************************/ + +#ifndef RCAR_DEF_H_ +#define RCAR_DEF_H_ + +/* Product Register */ +#define PRR (0xFFF00044U) /* PRR register */ +#define PRR_PRODUCT_MASK (0x00007F00U) /* Product mask */ +#define PRR_CUT_MASK (0x000000FFU) /* Cut Number bit mask */ +#define PRR_MAJOR_MASK (0x000000F0U) /* Major bit mask */ +#define PRR_MINOR_MASK (0x0000000FU) /* Minor bit mask */ +#define PRR_MAJOR_SHIFT (4U) /* Major bit shift */ +#define PRR_MAJOR_OFFSET (1U) + +#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */ +#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */ +#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */ + +#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */ +#define PRR_PRODUCT_11 (0x00000001U) /* ver 1.1 */ +#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */ +#define PRR_PRODUCT_21 (0x00000011U) /* ver 2.1 */ +#define PRR_PRODUCT_22 (0x00000012U) /* ver 2.2 */ +#endif /* RCAR_DEF_H_ */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/rcar_register.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/rcar_register.h new file mode 100644 index 0000000..9b5fa33 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/rcar_register.h @@ -0,0 +1,157 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : rcar register header + ******************************************************************************/ +/****************************************************************************** + * @file rcar_register.h + * - Version : 0.07 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 17.02.2022 0.02 Add APMU + * Support AArch32 + * : 09.05.2022 0.03 Changed to processing for each device + * : 24.10.2022 0.04 Add supports for HS200/400 + * : 31.10.2022 0.05 License notation change. + * : 07.11.2022 0.06 Added QOS and RTVRAM related registers. + * : 21.08.2023 0.07 Add support for V4M. + *****************************************************************************/ + +#ifndef RCAR_REGISTER_H_ +#define RCAR_REGISTER_H_ + +#include + +#define BASE_ADDR_PFC (0xE6000000U) /* PFC,GPIO,LIFC,CPGA,RESET */ +#define BASE_ADDR_RPC (0xEE200000U) /* RPC */ +#if (RCAR_LSI == RCAR_S4) +#define BASE_ADDR_SCIF (0xE6C00000U) /* SCIF */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define BASE_ADDR_SCIF (0xE6E00000U) /* SCIF */ +#endif /* RCAR_LSI == RCAR_S4 */ +#define BASE_ADDR_MMC (0xEE000000U) /* MMC */ +#define BASE_ADDR_HSCIF (0xE6400000U) /* HSCIF */ +#define BASE_AP_CORE_ADDR (0xE6280000U) /* ECM */ + +/* Base address offset of each register */ +/* CPGA */ +#define OFFSET_CPGA (0x00150000U) +/* RESET */ +#define OFFSET_RESET (0x00160000U) +/* APMU */ +#define OFFSET_APMU (0x00170000U) + +/*RPC*/ +#define OFFSET_RPC (0x00000000U) + +/*SCIF*/ +#if (RCAR_LSI == RCAR_S4) +#define OFFSET_SCIF3 (0x00050000U) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define OFFSET_SCIF0 (0x00060000U) +#endif /* RCAR_LSI == RCAR_S4 */ + +/* SDHI2/MMC0 */ +#define OFFSET_SDHI (0x00140000U) + +/* HSCIF */ +#define OFFSET_HSCIF0 (0x00140000U) + +/* PFC0 */ +#define OFFSET_PFC0 (0x00050000U) + +/* PFC1 */ +#if (RCAR_LSI == RCAR_S4) +#define OFFSET_PFC1 (0x00051000U) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define OFFSET_PFC1 (0x00058000U) +#endif /* RCAR_LSI == RCAR_S4 */ + +/* Port Group */ +#define OFFSET_PORTGR (0x00000800U) + +/* CPGWPR */ +#define OFFSET_CPG_CPGWPR (0x00000000U) + +/* SD0CKCR */ +#define OFFSET_CPG_SD0CKCR (0x00000870U) + +/* PLL2CR0 */ +#define OFFSET_CPG_PLL2CR0 (0x00000834U) + +/* PLLECR */ +#define OFFSET_CPG_PLLECR (0x00000820U) + +/* QOS */ +#define ICU_CC (0xE6600000U) /* CC63S,I2C,AXMM,QoS */ +#define ICU_OFFSET_CCI (0x001a0000U) /* (0xE67A0000U) */ +#define BASE_CCI_ADDR (ICU_CC + ICU_OFFSET_CCI) + +/* RTVRAM */ +#define SDRAM_40BIT_ADDR_TOP (0x0400000000ULL) +#define RTVRAM_VBUF_AREA_SIZE (4U * 1024U * 1024U) /* 4MB */ + +#define BASE_CPG_ADDR (BASE_ADDR_PFC + OFFSET_CPGA) +#define BASE_RESET_ADDR (BASE_ADDR_PFC + OFFSET_RESET) +#define BASE_APMU_ADDR (BASE_ADDR_PFC + OFFSET_APMU) +#define BASE_RPC_ADDR (BASE_ADDR_RPC + OFFSET_RPC) +#if (RCAR_LSI == RCAR_S4) +#define BASE_SCIF_ADDR (BASE_ADDR_SCIF + OFFSET_SCIF3) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define BASE_SCIF_ADDR (BASE_ADDR_SCIF + OFFSET_SCIF0) +#endif /* RCAR_LSI == RCAR_S4 */ +#define BASE_MMC0_ADDR (BASE_ADDR_MMC + OFFSET_SDHI) +#define BASE_HSCIF_ADDR (BASE_ADDR_HSCIF + OFFSET_HSCIF0) +#define BASE_PFC0_ADDR (BASE_ADDR_PFC + OFFSET_PFC0) +#define BASE_PFC1_ADDR (BASE_ADDR_PFC + OFFSET_PFC1) +#define BASE_CPG_ADDR (BASE_ADDR_PFC + OFFSET_CPGA) +#define PFC_GP1_BASE (BASE_PFC0_ADDR + OFFSET_PORTGR) +#define PFC_GP3_BASE (BASE_PFC1_ADDR + OFFSET_PORTGR) +#define CPG_CPGWPR (BASE_CPG_ADDR + OFFSET_CPG_CPGWPR) +#define CPG_PLL2CR0 (BASE_CPG_ADDR + OFFSET_CPG_PLL2CR0) +#define CPG_PLLECR (BASE_CPG_ADDR + OFFSET_CPG_PLLECR) +#define CPG_SD0CKCR (BASE_CPG_ADDR + OFFSET_CPG_SD0CKCR) +#define CPG_FRQCRC0 (BASE_CPG_ADDR + OFFSET_CPG_FRQCRC0 0x0808U) + +#define OFFSET_PFC_DRV0CTRL (0x00000080U) +#define OFFSET_PFC_DRV1CTRL (0x00000084U) +#define OFFSET_PFC_DRV2CTRL (0x00000088U) + +#if (RCAR_LSI == RCAR_S4) +#define PFC_DRVCTRL1_GP1_DM0 (PFC_GP1_BASE + OFFSET_PFC_DRV1CTRL) // R/W 32 POC control register0 PortGroup 3 +#define PFC_DRVCTRL2_GP1_DM0 (PFC_GP1_BASE + OFFSET_PFC_DRV2CTRL) // R/W 32 POC control register1 PortGroup 3 +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define PFC_DRVCTRL0_GP3_DM0 (PFC_GP3_BASE + OFFSET_PFC_DRV0CTRL) // R/W 32 POC control register0 PortGroup 3 +#define PFC_DRVCTRL1_GP3_DM0 (PFC_GP3_BASE + OFFSET_PFC_DRV1CTRL) // R/W 32 POC control register1 PortGroup 3 +#endif /* RCAR_LSI == RCAR_S4 */ + +#define PFC_PMMR(addr) ((addr) & (uintptr_t)0xFFFFF800U) // R/W 32 LSI Multiplexed Pin Setting Mask Register + +#endif /* RCAR_REGISTER_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/rst_register.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/rst_register.h new file mode 100644 index 0000000..52ad7ec --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/rst_register.h @@ -0,0 +1,65 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : RST register header + ******************************************************************************/ +/****************************************************************************** + * @file rst_register.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +#ifndef RST_REGISTER_H_ +#define RST_REGISTER_H_ + +#include + +#define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */ + +#define RST_MODEMR0 (RST_BASE + 0x0000U) /* Mode pin register0 */ +#define RST_MODEMR1 (RST_BASE + 0x0004U) /* Mode pin register1 */ +#define RST_MODEMR0_MD31 (1U << 31U) +#define RST_MODEMR1_MD32 (1U << 0U) + +#define RST_MODEMR0_BOOT_DEV_MASK (0x0000001EU) +#define RST_MODEMR0_BOOT_DEV_HYPERFLASH160 (0x00000004U) +#define RST_MODEMR0_BOOT_DEV_HYPERFLASH80 (0x00000006U) +#define RST_MODEMR0_BOOT_DEV_QSPI_FLASH40 (0x00000008U) +#define RST_MODEMR0_BOOT_DEV_EMMC_50X8 (0x0000001AU) + +/* SCIF / HSCIF clock speed */ +#define MODEMR_SCIF_DLMODE (0x00000000U) +#define MODEMR_HSCIF_DLMODE_921600 (0x00000001U) +#define MODEMR_HSCIF_DLMODE_1843200 (0x00000002U) +#define MODEMR_HSCIF_DLMODE_3000000 (0x00000003U) + +#endif /* RST_REGISTER_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/rtvram.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/rtvram.h new file mode 100644 index 0000000..ae0c5f3 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/rtvram.h @@ -0,0 +1,35 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-VRAM driver header + ******************************************************************************/ + +#ifndef RTVRAM_H_ +#define RTVRAM_H_ + +#include + +void rtvram_extendmode(void); + +#endif /* RTVRAM_H__ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/rtvram_register.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/rtvram_register.h new file mode 100644 index 0000000..4b27268 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/rtvram_register.h @@ -0,0 +1,92 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-VRAM register header + ******************************************************************************/ + +#ifndef RTVRAM_REGISTER_H__ +#define RTVRAM_REGISTER_H__ + +#include + +/* RT-VRAM register base address */ +#define RTVRAM_REG_BASE (0xFFEC0000U) + +#define RTVRAM_SECDIVD (RTVRAM_REG_BASE + 0x0000U) +#define RTVRAM_SECCTRRD (RTVRAM_REG_BASE + 0x0040U) +#define RTVRAM_SECCTRWD (RTVRAM_REG_BASE + 0x0340U) +#define RTVRAM_EXT_MODE (RTVRAM_REG_BASE + 0x8500U) +#define RTVRAM_VBUF_CFG (RTVRAM_REG_BASE + 0x6504U) +#define RTVRAM_CACHE_FLUSH (RTVRAM_REG_BASE + 0x4530U) +#define RTVRAM_VBUF_BADDR (RTVRAM_REG_BASE + 0xC580U) + +/* RT-VRAM0 register base address */ +#define RTVRAM0_REG_BASE (0xFFE90000U) +/* RT-VRAM1 register base address */ +#define RTVRAM1_REG_BASE (0xFFEC0000U) + +#define RTVRAM0_SECDIVD (RTVRAM0_REG_BASE + 0x0000U) +#define RTVRAM0_SECCTRRD (RTVRAM0_REG_BASE + 0x0040U) +#define RTVRAM0_SECCTRWD (RTVRAM0_REG_BASE + 0x0340U) + +#define RTVRAM1_SECDIVD (RTVRAM1_REG_BASE + 0x0000U) +#define RTVRAM1_SECCTRRD (RTVRAM1_REG_BASE + 0x0040U) +#define RTVRAM1_SECCTRWD (RTVRAM1_REG_BASE + 0x0340U) + +static inline uint32_t get_rtvram0_secdivd_addr(uint32_t num) +{ + return ((RTVRAM0_SECDIVD + (num * 4U))); +} + +static inline uint32_t get_rtvram0_secctrrd_addr(uint32_t num) +{ + return ((RTVRAM0_SECCTRRD + (num * 4U))); +} + +static inline uint32_t get_rtvram0_secctrwd_addr(uint32_t num) +{ + return ((RTVRAM0_SECCTRWD + (num * 4U))); +} + +static inline uint32_t get_rtvram1_secdivd_addr(uint32_t num) +{ + return ((RTVRAM1_SECDIVD + (num * 4U))); +} + +static inline uint32_t get_rtvram1_secctrrd_addr(uint32_t num) +{ + return ((RTVRAM1_SECCTRRD + (num * 4U))); +} + +static inline uint32_t get_rtvram1_secctrwd_addr(uint32_t num) +{ + return ((RTVRAM1_SECCTRWD + (num * 4U))); +} + +static inline uint32_t get_vbuf_baddr_addr(uint32_t num) +{ + return ((RTVRAM_VBUF_BADDR + (num * 4U))); +} + +#endif /* RTVRAM_REGISTER_H__ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/scif.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/scif.h new file mode 100644 index 0000000..80d8a6e --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/scif.h @@ -0,0 +1,51 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : SCIF driver header + ******************************************************************************/ +/****************************************************************************** + * @file scif.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +#ifndef SCIF_H_ +#define SCIF_H_ + +#include +#include + +/* Prototype */ +void scif_init(void); +void console_putc(uint8_t outchar); + +#endif /* SCIF_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/scif_register.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/scif_register.h new file mode 100644 index 0000000..d26b6c6 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/scif_register.h @@ -0,0 +1,60 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : SCIF register header + ******************************************************************************/ +/****************************************************************************** + * @file scif_register.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + + +#ifndef SCIF_REGISTER_H_ +#define SCIF_REGISTER_H_ + +#include + +/* SCIF3 base address */ +/* 0xE6C50000 */ +#define SCIF_BASE (BASE_SCIF_ADDR) + +#define SCIF_SCSMR (SCIF_BASE + 0x0000U) /* 16 Serial mode register */ +#define SCIF_SCBRR (SCIF_BASE + 0x0004U) /* 8 Bit rate register */ +#define SCIF_SCSCR (SCIF_BASE + 0x0008U) /* 16 Serial control register */ +#define SCIF_SCFTDR (SCIF_BASE + 0x000CU) /* 8 Transmit FIFO data register */ +#define SCIF_SCFSR (SCIF_BASE + 0x0010U) /* 16 Serial status register */ +#define SCIF_SCFCR (SCIF_BASE + 0x0018U) /* 16 FIFO control register */ +#define SCIF_SCLSR (SCIF_BASE + 0x0024U) /* 16 Line status register */ +#define SCIF_CKS (SCIF_BASE + 0x0034U) /* 16 Clock Select register */ + +#endif /* SCIF_REGISTER_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/scmt.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/scmt.h new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/scmt_checkpoint.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/scmt_checkpoint.h new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/scmt_config.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/scmt_config.h new file mode 100644 index 0000000..398b69f --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/scmt_config.h @@ -0,0 +1,80 @@ +#ifndef SCMT_CONFIG_H_ +#define SCMT_CONFIG_H_ + +/* Activate measurement functions. Provide dummy functions otherwise */ +#ifndef MEASURE_TIME +#define MEASURE_TIME (0) +#endif + +/* Replace printing by dummy function. This will keep timer init, but removes impact of printing on system performance */ +#ifndef MEASURE_TIME_NOPRINT +#define MEASURE_TIME_NOPRINT (0) +#endif + +/* Only first IPL should init the timer. + In case of bus access issues, you can check addresses and register values with SCMT_DEBUG. + (Dont forget to add a call to scmt_module_start then and set debug level to NOTICE(2). ) */ +#define SCMT_INIT (0) +#define SCMT_DEBUG (0) + +/* SCMT base address */ +/* V4H:0xE6040000 */ +/* V4H-ICUMX: 0xFC000000 + (13*0x00200000) + 0x00040000 = 0xFDA40000 */ +#define SCMT_BASE (0xE6040000) + +/* For boot time measurement, you can signal the start of SCMT by GPIO pin toggle */ +/* See code for adaption of toggled pin */ +#define SCMT_TOGGLE_GPIO (0) + +/* SCMT is counting with OSCCLK = 131.57 kHz */ +/* Tick = 7.6 µs*/ +/* Full 32-bit wrap around therefore: 32643 seconds == 9.07 hours */ +/* NOTE: WRAPAROUND HANDLING NOT IMPLEMENTED! */ +#define SCMT_MS2TICKS(ms) ((ms)*131.579) + +/* If the startup time until start of SCMT is known, we can set it as start value of the timer to see absolute time right away */ +//#define SCMT_START_VALUE (0) /* No offset, add offset using your spreadsheet program */ +//#define SCMT_START_VALUE (2750) /* 20.9ms with MODEMR[1:0]: 0x0 0x801105a4 > ICUMX Boot from HyperFlash 160MHz, Unsecure Boot */ +//#define SCMT_START_VALUE (2842) /* 21.6ms with MODEMR[1:0]: 0x0 0x801105a4 > ICUMX Boot from HyperFlash 80MHz, Unsecure Boot */ +//#define SCMT_START_VALUE (2974) /* 22.6ms with MODEMR[1:0]: 0x0 0x801105a8 > ICUMX Boot from SerialFlash 133MHz QuadIO, Unsecure Boot */ +//#define SCMT_START_VALUE (3237) /* 24.6ms with MODEMR[1:0]: 0x0 0x801105a8 > ICUMX Boot from SerialFlash 80MHz QuadIO, Unsecure Boot */ +#define SCMT_START_VALUE (7184) /* 54.6ms with MODEMR[1:0]: 0x0 0x801105a8 > ICUMX Boot from SerialFlash 40MHz, Unsecure Boot */ + +/* Start a little self-test routine to check Timer-Frequency against baudrate */ +/* #define TIMER_TEST_VS_BAUD (921600) */ +#define TIMER_TEST_VS_BAUD (0) + +/* SCMT frequency slightly depends on MD-Pin settings!! See V4H UM Table 8.1.4e Note 5 */ +#define TIMER_FREQ (131578.9) + +/* Module name show in log output */ +#define MODULE "Cx:" + +/* Arry size for time checkpoints */ +#define TIME_CHECKPOINTS_MAX (20) + +/* Print additional infos about compiler or MODEMR register */ +#define PRINT_INFO (0) + +/* Calculates milliseconds from timer ticks. May be disabled if compiler is currently not prepared to handle floats */ +#define PRINT_FLOAT (1) + +/* PRINTING + You need to configure a way to hook into the systems print functionality +*/ + +/* Uses the ERROR macro defined by log.h - Works for ICUMX and CR Core */ +#include /* Access to ERROR() print function */ +#define PRINTFN(args...) ERROR(args) + +/* Uses facilities provided by Dummy_CA76 application */ +// #define USE_LOG_PRINTF (1) +// void log_printf(const char *fmt, ...); /* Provided by scmt_checkpoint_log.c */ +// int32_t PutChar(char outChar); /* Provided by devdrv.c */ +// #define PRINTFN(args...) {log_printf(args);} +// #define PUTFN(outChar) PutChar(outChar) + + + + +#endif diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/scmt_register.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/scmt_register.h new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/secure_boot.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/secure_boot.h new file mode 100644 index 0000000..3814186 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/secure_boot.h @@ -0,0 +1,60 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + +/******************************************************************************* + * DESCRIPTION : ICUMIF control function header + ******************************************************************************/ +/****************************************************************************** + * @file secure_boot.h + * - Version : 0.03 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 17.06.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + * : 16.02.2023 0.03 Added prototype declaration of final_hash_cmp. + *****************************************************************************/ + +#ifndef SECURE_BOOT_H_ +#define SECURE_BOOT_H_ + +#define SECURE_BOOT (0x0U) +#define NORMAL_BOOT (0x211883DFU) + +#define ROMAPI_OK (0x00000000U) +#define ROM_ERR_IMG_VERIFIER_NO_ENCRYPT_IMG (0xF100001DU) + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void secureboot_init(void); +uint32_t judge_bootmode(void); +void secureboot_verify(LOAD_INFO* li, uint32_t start, uint32_t end); +int secureboot_image(LOAD_INFO* li, int do_panic); +void final_hash_cmp(void); + +#endif /* SECURE_BOOT_H_ */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/string.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/string.h new file mode 100644 index 0000000..6a0e97f --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/string.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : string function header + ******************************************************************************/ +/****************************************************************************** + * @file string.h + * - Version : 0.01 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 06.04.2023 0.01 First Release +*****************************************************************************/ + +#ifndef STRING_H__ +#define STRING_H__ + +#include + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void *memcpy(void *dst, const void *src, size_t len); +void *memset(void *dst, int val, size_t len); +int memcmp(const void * cs, const void * ct, size_t count); + +#endif /* STRING_H__ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/swdt.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/swdt.h new file mode 100644 index 0000000..5e8e663 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/swdt.h @@ -0,0 +1,105 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : swdt header + ******************************************************************************/ +/****************************************************************************** + * @file swdt.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 12.08.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ +#ifndef SWDT_H_ +#define SWDT_H_ + +#include +#include "mem_io.h" +#include "rst_register.h" + +#define SWDT_BASE (0xE6030000U) +#define SWDT_WTCNT (SWDT_BASE + 0x0000U) +#define SWDT_WTCSRA (SWDT_BASE + 0x0004U) +#define SWDT_WTCSRB (SWDT_BASE + 0x0008U) + +#define WTCNT_UPPER_BYTE (0x5A5A0000U) +#define WTCSRA_UPPER_BYTE (0xA5A5A500U) +#define WTCSRB_UPPER_BYTE (0xA5A5A500U) +#define WTCNT_RESET_VALUE (0xF488U) +#define WTCSRA_BIT_CKS (0x0007U) +#define WTCSRB_BIT_CKS (0x003FU) +#define SWDT_RSTMSK (0U << 1U) +#define WTCSRA_WOVFE (1U << 3U) +#define WTCSRA_WRFLG (1U << 5U) +#define WTCSRA_TME (1U << 7U) + +#define WDTRSTCR_MASK_ALL (0x0000FFFFU) +#define WTCSRA_MASK_ALL (0x000000FFU) +#define WTCNT_INIT_DATA (WTCNT_UPPER_BYTE + WTCNT_RESET_VALUE) +#define WTCSRA_INIT_DATA (WTCSRA_UPPER_BYTE + 0x0FU) +#define WTCSRB_INIT_DATA (WTCSRB_UPPER_BYTE + 0x21U) + +/* CKS0 setting */ +#define OSCCLK_32 (32U) /* 011:OSCCLK/32 */ +#define WTCSRA_CKS0_OSCCLK (0x00000003U) + +/* WDT Timeout Setting */ +/* OSCCLK */ +#define OSCCLK_133330HZ (133330U) /* MD13=0 MD14=0*/ +#define OSCCLK_131570HZ (131570U) /* MD13=H MD14=L*/ + +/* clock */ +/* (micro sec / (Hz / RPhi) */ +#define CLK_133330HZ ((uint32_t)((1U * 1000U * 1000U) \ + / (OSCCLK_133330HZ / OSCCLK_32))) +#define CLK_131570HZ ((uint32_t)((1U * 1000U * 1000U) \ + / (OSCCLK_131570HZ / OSCCLK_32))) + +#define SWDT_COUNT_SEC (10U) /* set param(1--10sec) */ + +/* SWDT over flow sec need count*/ +#define SWDT_COUNT_133330HZ ((uint32_t)((SWDT_COUNT_SEC * 1000U * 1000U) \ + / CLK_133330HZ)) +#define SWDT_COUNT_131570HZ ((uint32_t)((SWDT_COUNT_SEC * 1000U * 1000U) \ + / CLK_131570HZ)) + +#define SWDTCNT_133330HZ (0x10000U - SWDT_COUNT_133330HZ) +#define SWDTCNT_131570HZ (0x10000U - SWDT_COUNT_131570HZ) + +#define MD14_MD13_TYPE_0 (0x00000000U) /* MD14=0 MD13=0 */ +#define MD14_MD13_TYPE_1 (0x00002000U) /* MD14=0 MD13=1 */ +#define MD14_MD13_TYPE_3 (0x00006000U) /* MD14=1 MD13=1 */ +#define CHECK_MD13_MD14 (0x00006000U) + +/* Prototype */ +void swdt_init(void); +void swdt_exec(void); +void swdt_release(void); +#endif /* SWDT_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/timer.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/timer.h new file mode 100644 index 0000000..207c84a --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/timer.h @@ -0,0 +1,51 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : timer header + ******************************************************************************/ +/****************************************************************************** + * @file timer.h + * - Version : 0.03 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 09.05.2022 0.02 Moved the definition of the define value + * : 31.10.2022 0.03 License notation change. + *****************************************************************************/ +#ifndef TIMER_H_ +#define TIMER_H_ + +#include +#include + +/* Prototype */ +void generic_timer_init(void); +void micro_wait(uint64_t micro_sec); + +#endif /* TIMER_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/include/types.h b/IPL/Customer/Mobis/V4H_Cx_Loader/include/types.h new file mode 100644 index 0000000..b4860d2 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/include/types.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Type header + ******************************************************************************/ +/****************************************************************************** + * @file types.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + + +#ifndef TYPES_H +#define TYPES_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * File Name: types.h + * Contents : Types Define + ****************************************************************************/ +#include +#include + +#ifndef FALSE +#define FALSE (0U) +#endif + +#ifndef TRUE +#define TRUE (1U) +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/boot_init_dram.h b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/boot_init_dram.h new file mode 100644 index 0000000..c6b8b47 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/boot_init_dram.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#ifndef BOOT_INIT_DRAM +#define BOOT_INIT_DRAM + +extern uint32_t R_DRAM_Init(void); +#if (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) +void r_set_pi_rdlvl_interval(void); +#endif + +#define INITDRAM_OK (0) +#define INITDRAM_NG (0xFFFFFFFFU) +#define INITDRAM_ERR_I (0xFFFFFFFFU) + +#endif /* BOOT_INIT_DRAM */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/ddr.mk b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/ddr.mk new file mode 100644 index 0000000..a245832 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/ddr.mk @@ -0,0 +1,12 @@ +# +# Copyright (c) 2015-2023, Renesas Electronics Corporation All rights reserved. +# + +ifeq (${LSI},V4H) + OBJ_FILE += ip/ddr/v4h/lpddr5/boot_init_dram.o + OBJ_FILE += ip/ddr/v4h/lpddr5/boot_init_dram_config.o +else ifeq (${LSI},V4M) + OBJ_FILE += ip/ddr/v4m/lpddr5/boot_init_dram.o + OBJ_FILE += ip/ddr/v4m/lpddr5/boot_init_dram_config.o +endif +OBJ_FILE += ip/ddr/dram_sub_func.o \ No newline at end of file diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/dram_sub_func.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/dram_sub_func.c new file mode 100644 index 0000000..9d3b535 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/dram_sub_func.c @@ -0,0 +1,36 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#include +#include "dram_sub_func.h" + +void R_DRAM_Get_Boot_Status(uint32_t *status) +{ + *status = DRAM_BOOT_STATUS_COLD; +} + +uint32_t R_DRAM_Update_Boot_Status(uint32_t status) +{ + uint32_t ret = 0U; + return ret; +} diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/dram_sub_func.h b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/dram_sub_func.h new file mode 100644 index 0000000..ac9493b --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/dram_sub_func.h @@ -0,0 +1,33 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#ifndef DRAM_SUB_FUNC +#define DRAM_SUB_FUNC + +#define DRAM_BOOT_STATUS_COLD (0U) +#define DRAM_BOOT_STATUS_WARM (1U) + +void R_DRAM_Get_Boot_Status(uint32_t *status); +uint32_t R_DRAM_Update_Boot_Status(uint32_t status); + +#endif /* DRAM_SUB_FUNC_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram.c new file mode 100644 index 0000000..1fc3ebb --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram.c @@ -0,0 +1,4613 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#else +#include "mem_io.h" +#include "log.h" +#endif +#include "ddr_regdef.h" +#include "init_dram_tbl_v4h_lp5.h" +#include "boot_init_dram_regdef.h" +#include "boot_init_dram.h" +#include "dram_sub_func.h" + +/******************************************************************************* + * load board configuration + ******************************************************************************/ +#include "boot_init_dram_config.h" + +//! @details Implement for suspend to Ram. +#define DDR_BACKUPMODE + +//! @details Define the function of log output. +#define FATAL_MSG(x) NOTICE(x) + +/******************************************************************************* + * variables + ******************************************************************************/ +static uint32_t Prr_Product; +static uint32_t Prr_Cut; +//! @details The board parameter index which you use. +static uint32_t BOARDTYPE; +//! @details The board clock frequency +static uint32_t brd_clk; +//! @details The board clock frequency division +static uint32_t brd_clkdiv; +//! @details The board clock frequency division A +static uint32_t brd_clkdiva; +//! @details The Mbps of DDR +static uint32_t ddr_mbps; +//! @details The Mbps division of DDR +static uint32_t ddr_mbpsdiv; +//! @details Decimal multiplication setting value +static uint32_t sscg; +//! @details The Mbps of Bus, The Mbps division of Bus +static uint32_t bus_clk, bus_clkdiv; +//! @details The tccd value of DDR +static uint32_t ddr_tccd; +//! @details The parameter structure of the board you use +static const st_boardcnf_t *Boardcnf; +//! @details Value indicating the enabled channel +static uint32_t ddr_phyvalid; +//! @details Memory capacity in each channel and each CS +static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; +//! @details Indicates channels used for each memory rank +static uint32_t ch_have_this_cs[CS_CNT]; +//! @details The maximum memory capacity +static uint32_t max_density; +//! @details One of the DDR memory multiplier setting value +static uint32_t ddr_mul; +//! @details One of the DDR memory multiplier setting value +static uint32_t ddr_mul_nf; +//! @details One of the DDR memory multiplier setting value +static uint32_t ddr_mul_low; +//! @details One of the DDR memory multiplier setting value +static uint32_t ddr_mul_reg; + +//! @details Number of elements in DDRPHY register setting array +#define DDR_PHY_REGSET_MAX 153 +//! @details Number of elements in PI register setting array +#define DDR_PI_REGSET_MAX 1381 + +//! @details Array for DDRPHY Slice settings +static uint32_t DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX]; +//! @details Array for DDRPHY ADRRESS VALUE Slice settings +static uint32_t DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; +//! @details Array for DDRPHY ADRRESS CONTROL Slice settings +static uint32_t DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; +//! @details Array for DDR PI Slice settings +static uint32_t DDR_PI_REGSET[DDR_PI_REGSET_MAX]; +#ifdef DDR_BACKUPMODE +//! @details Boot mode of ICUMX Loader +static uint32_t ddrBackup; +#endif + +#ifndef RCAR_PLL3_FRAC_MODE +//! @details SS Mode for PLL3 +#define RCAR_PLL3_FRAC_MODE (1U) +#endif + +#ifndef RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE +//! @details Fast loading mode of DDRPHY register +#define RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE (1U) +#endif + +//! @details PLL3 configuration value of low frequency mode +#define PLL3_LOW_FREQUENCY_MODE (0U) +//! @details PLL3 configuration value of high frequency mode +#define PLL3_HIGH_FREQUENCY_MODE (2U) +//! @details PLL3 configuration value of high frequency mode load register +#define PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER (3U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static uint32_t r_vch_nxt(uint32_t pos); +static void r_cpg_write_32(uint32_t a, uint32_t v); +static void r_pll3_control(uint32_t mode); +static void r_send_dbcmd2(uint32_t cmd); +static uint32_t r_reg_ddrphy_read(uint32_t phyno, uint32_t regadd); +static void r_reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata); +static void r_reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata); +static void r_reg_ddrphy_masked_write(uint32_t phyno, uint32_t regadd, uint32_t regdata, uint32_t msk); +static void r_ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t regdef, uint32_t val); +static uint32_t r_ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t regdef); +static void r_ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val); +static void r_ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); +static void r_ddr_setval_ach(uint32_t regdef, uint32_t val); +static void r_ddr_setval_ach_as(uint32_t regdef, uint32_t val); +static uint32_t r_ddr_getval(uint32_t ch, uint32_t regdef); +static void r_tbl_copy(uint32_t *to, const uint32_t *from, uint32_t size); +static void r_ddrtbl_setval(uint32_t *tbl, uint32_t regdef, uint32_t val); +static void r_ddrtbl_setval_pi(uint32_t *tbl, uint32_t regdef, uint32_t val); +static uint32_t r_ddrtbl_getval(const uint32_t *tbl, uint32_t regdef); +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) +static uint32_t r_ddrtbl_getval_pi(const uint32_t *tbl, uint32_t regdef); +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ +static uint16_t r_f_scale(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint16_t cyc); +static uint32_t r_f_scale_l(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint32_t cyc); +static void r_f_scale_js2(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t *f_js2); +static void r_ddrtbl_load(void); +static void r_ddr_config(void); +static void r_dbsc_regset(void); +static void r_dbsc_regset_post(void); +static void r_ddr_register_set(void); +static void r_ddr_register_read(void); +static uint32_t r_wait_freqchgreq(uint32_t req_assert); +static void r_set_freqchgack(uint32_t ack_assert); +static uint32_t r_pi_training(void); +static void r_write_leveling_adjust(void); +static uint32_t r_wl_gt_training(void); +static void r_write_dca(void); +static uint32_t r_dramdca_training(void); +static uint32_t r_write_leveling(void); +static void r_manual_write_dca(void); +static uint32_t r_read_gate_training(void); +static uint32_t r_read_vref_training(void); +static uint32_t r_read_write_training(void); +static uint32_t r_read_training(void); +static uint32_t r_pll3_freq(void); +static uint32_t r_init_ddr(void); +static void r_dbsc_write_32(uintptr_t addr, uint32_t data); +static uint32_t r_pi_int_ack_0_assert(uint32_t bit); + +/** +* Macro for channel selection loop +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-01:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] pos Start channel of validity check +* @return uint32_t Effective channel +* @details Returns the ID of the channel to be used.\n +* -# Check for valid channels between the value of posn and the maximum number of CHs.\n +* -# If a valid channel is found, returns the value of that channel. +*/ +static uint32_t r_vch_nxt(uint32_t pos) +{ + uint32_t posn; + + for (posn = pos; posn < DRAM_CH_CNT; posn++) + { + if ((ddr_phyvalid & (1U << posn)) != 0x0U) + { + break; + } + } + return posn; +} + +//! @details Select only valid channels in all channels from CH0. +#define r_foreach_vch(ch) \ +for (ch = r_vch_nxt(0); ch < DRAM_CH_CNT; ch = r_vch_nxt(ch + 1U)) + +//! @details All channels are selected. +#define r_foreach_ech(ch) \ +for (ch = 0U; ch < DRAM_CH_CNT; ch++) + +//! @details Printing functions +#define MSG_LF(...) + +/** +* Clock settings and reset control +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-02:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] a Destination address +* @param[in] v Setting value +* @details +* -# Write the complement value of setting value to the CPG_CPGWPR register\n +* for releaseing the protect.\n +* -# Write setting value to destination address. +*/ +static void r_cpg_write_32(uint32_t a, uint32_t v) +{ + mmio_write_32(CPG_CPGWPR, ~v); + mmio_write_32(a, v); +} + +/** +* Setting PLL3 +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-01:V4H-LPDDR5-DDR-HW-DD-10-02-02 +* @param[in] mode Selection of frequency +* @details +*-# Determine the set value according to the frequency mode of the argument.\n +*-# Write the set value to CPG_FRQCRD0 register and CPG_FRQCRD0 one.\n +*-# Reflect settings +*/ +static void r_pll3_control(uint32_t mode) +{ + uint32_t dataDIV, ssmode_high, dataMUL; + uint32_t ssmode, dataNF; + /* PLL3VCO = EXTAL * ddr_mul * 1/2 */ + /* clk_ctlr_sync = PLL3VCO * pll3_div */ + /* ddr_mul = (NI[7:0] + 1) * 2 + NF[24:0] / 2^24 */ + +#if RCAR_PLL3_FRAC_MODE == 1U + ssmode_high = 0x4U; +#else + ssmode_high = 0x0U; +#endif + + switch (mode) + { + case PLL3_LOW_FREQUENCY_MODE: + /* Low frequency mode (50MHz) */ + dataMUL = (ddr_mul_low / 2U) - 1U; /* PLL3VCO = 1600MHz */ + dataDIV = 0x9U; /* div = 32 */ + dataNF = 0x00U; + ssmode = 0x0U; + break; + case PLL3_HIGH_FREQUENCY_MODE: + /* High frequency mode */ + dataMUL = (ddr_mul / 2U) - 1U; + dataDIV = 0x0U; /* div = 2 */ + dataNF = ddr_mul_nf; + ssmode = ssmode_high; + break; + case PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER: + /* High frequency mode for loading to DDRPHY registers */ + dataMUL = (ddr_mul_reg / 2U) - 1U; + dataDIV = 0x0U; /* div = 2 */ + dataNF = 0x00U; + ssmode = ssmode_high; + break; + default: + /* High frequency mode */ + dataMUL = (ddr_mul / 2U) - 1U; + dataDIV = 0x0U; /* div = 2 */ + dataNF = ddr_mul_nf; + ssmode = ssmode_high; + break; + }/* mode */ + + dataMUL = (dataMUL << 20) | (ssmode << 16); + dataNF = (dataNF << 21); + + if (((mmio_read_32(CPG_PLL3CR0) & 0x3FFFFF7FU) != dataMUL) || (mmio_read_32(CPG_PLL3CR1) != dataNF)) + { + /* PLL3CR0 multiplie set */ + r_cpg_write_32(CPG_PLL3CR0, dataMUL); + /* PLL3CR1 multiplie set */ + r_cpg_write_32(CPG_PLL3CR1, dataNF); + r_cpg_write_32(CPG_PLL3CR0, mmio_read_32(CPG_PLL3CR0) | CPG_PLL3CR0_KICK_BIT); + while ((mmio_read_32(CPG_PLLECR) & CPG_PLLECR_PLL3ST_BIT) != CPG_PLLECR_PLL3ST_BIT) + { + ; /* Nothing */ + } + } + + /* PLL3 DIV set(Target value) */ + while (((mmio_read_32(CPG_FRQCRD0) & CPG_FRQCRD_KICK_BIT)) != 0x0U) + { + ; /* Nothing */ + } + r_cpg_write_32(CPG_FRQCRD0, dataDIV | (mmio_read_32(CPG_FRQCRD0) & 0xFFFFFFF0U)); + r_cpg_write_32(CPG_FRQCRD0, mmio_read_32(CPG_FRQCRD0) | CPG_FRQCRD_KICK_BIT); + while (((mmio_read_32(CPG_FRQCRD0) & CPG_FRQCRD_KICK_BIT)) != 0x0U) + { + ; /* Nothing */ + } +} + +/** +* DRAM Command Write Access +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-03:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] cmd DRAM command. +* @details +* -# First, execute the dummy read to DBSC_DBCMD.\n +* -# Confirm that no DBSC command operation is in progress 0.\n +* -# Write the contents of the command to be sent to DRAM.. +*/ +static void r_send_dbcmd2(uint32_t cmd) +{ + /* dummy read */ + mmio_read_32(DBSC_DBCMD); + + while (((mmio_read_32(DBSC_DBWAIT)) & 0x01U) != 0x0U) + { + ; /* Nothing */ + } + while (((mmio_read_32(DBSC_DBWAIT + 0x00004000U)) & 0x01U) != 0x0U) + { + ; /* Nothing */ + } + + r_dbsc_write_32((DBSC_DBCMD), cmd); +} + +/** +* DDRPHY register read +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-04:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] phyno Target channel +* @param[in] regadd Destination address of target ddrphy register +* @return uint32_t Result of read access +* @details +* -# Write the destination address of ddrphy to DBSC_DBPDRGA(ch) register.\n +* -# Wait until the status bit in the DBSC_DBPDRGD register indicates completion. +* -# Read the value of the DDRPHY register from DBSC_DBPDRGD. +* -# Clear the status bit of DBSC_DBPDRGD register twice. +* -# Read the value of the DDRPHY register from DBSC_DBPDRGD. +* -# Dummy reads the variable val. +*/ +static uint32_t r_reg_ddrphy_read(uint32_t phyno, uint32_t regadd) +{ + uint32_t val; + + val = 0U; + mmio_write_32(DBSC_DBPDRGA(phyno), (regadd | 0x00004000U)); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x0000C000U)) + { + ; /* Nothing */ + } + + val = mmio_read_32(DBSC_DBPDRGA(phyno)); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + val = mmio_read_32(DBSC_DBPDRGD(phyno)); + (void)val; + + return val; +} + +/** +* DDRPHY register write +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-05:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] phyno Target channel +* @param[in] regadd Destination address of target ddrphy register +* @param[in] regdata Setting value to be written +* @details +* -# Write the destination address of ddrphy to DBSC_DBPDRGA(ch) register.\n +* -# Write setting value to be written to target address. +* -# Clear the status bit of DBSC_DBPDRGD register twice. +* -# Write the destination address of ddrphy to DBSC_DBPDRGA(ch) register.\n +*/ +static void r_reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) +{ + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGD(phyno), regdata); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x00008000U)) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), (regadd | 0x00008000U)); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); +} + +/** +* DDRPHY register write for valid channels +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-06:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] regadd Destination address +* @param[in] regdata Setting value to be written +* @details +* -# Call the "r_reg_ddrphy_write" func for only valid channels. +*/ +static void r_reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) +{ + uint32_t ch; + + r_foreach_vch((ch)) + { + r_reg_ddrphy_write(ch, regadd, regdata); + } +} + +/** +* Write the value to the register of ddrphy. +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-23:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] phyno The channel of DBSC +* @param[in] regadd Destination address +* @param[in] regdata Setting value to be written +* @param[in] msk The value of Mask +* @details +* -# Write the value of the argument msk to DBSC_DBPDRGM. Wait until the write process completed.\n +* -# Write the value of the argument regadd to DBSC_DBPDRGA. Wait until the write process completed.\n +* -# Write the value of the argument regdate to DBSC_DBPDRGD. Wait until the write process completed.\n +* -# Write the value of the argument regadd to DBSC_DBPDRGA. Wait until the write process completed.\n +* -# Write the value of the argument regadd to DBSC_DBPDRGA.\n +* -# Write the value of the argument msk to DBSC_DBPDRGM. Wait until the write process completed.\n +*/ +static void r_reg_ddrphy_masked_write(uint32_t phyno, uint32_t regadd, uint32_t regdata, uint32_t msk) +{ + mmio_write_32(DBSC_DBPDRGM(phyno), msk); + while (mmio_read_32(DBSC_DBPDRGM(phyno)) != msk) + { + ; /* do nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* do nothing */ + } + + mmio_write_32(DBSC_DBPDRGD(phyno), regdata); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x00008000U)) + { + ; /* do nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* do nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + + mmio_write_32(DBSC_DBPDRGM(phyno), 0x00U); + while (mmio_read_32(DBSC_DBPDRGM(phyno)) != 0x00U) + { + ; /* do nothing */ + } +} + +/** +* DDRPHY register access write (field modify) +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-07:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] ch Target ch +* @param[in] slice Target slice +* @param[in] regdef Information of destination bit field +* @param[in] val Setting value to be written +* @details +* -# Calculate the bit field in which to write the setting value\n +* from "regdef" value. +* -# Call r_reg_ddrphy_write() to write the setting value.\n +*/ +static void r_ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + + adr = DDR_REGDEF_ADR(regdef) + (0x100U * slice); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + tmp = 0xFFFFFFFFU; + } + else + { + tmp = ((1U << len) - 1U) << lsb; + } + + msk = (~(((tmp >> 21) & 0x08U) | ((tmp >> 14) & 0x04U) | ((tmp >> 7) & 0x02U) | (tmp & 0x01U))) & 0x0FU; + + r_reg_ddrphy_masked_write(ch, adr, (val << lsb), msk); +} + +/** +* DDRPHY register access read (field modify) +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-08:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] ch Target ch +* @param[in] slice Target slice +* @param[in] regdef Information of destination bit field +* @details +* -# Calculate the address and the bit-field from "regdef" value.\n +* -# Call r_reg_ddrphy_read() to read value from the target address. +*/ +static uint32_t r_ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + + adr = DDR_REGDEF_ADR(regdef) + (0x100U * slice); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U); + } + + tmp = r_reg_ddrphy_read(ch, adr); + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +/** +* DDRPHY register access write for slice0 (field modify) +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-09:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] ch Target ch +* @param[in] regdef Information of destination bit field +* @param[in] val Setting value to be written +* @details +* -# Call the "r_ddr_setval_s" func. In this case, the argument slice is 0. +*/ +static void r_ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) +{ + r_ddr_setval_s(ch, 0U, regdef, val); +} + +/** +* DDRPHY register access write for all channel/slice (field modify) +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-10:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] slice Target slice +* @param[in] regdef Information of destination bit field +* @param[in] val Setting value to be written +* @details +* -# Call the "r_ddr_setval_s" func for valid channels. +*/ +static void r_ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val) +{ + uint32_t ch; + + r_foreach_vch((ch)) + { + r_ddr_setval_s(ch, slice, regdef, val); + } +} + +/** +* DDRPHY register access write for all channel and slice0 (field modify) +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-11:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] regdef Information of destination bit field +* @param[in] val Setting value to be written +* @details Call the "r_ddr_setval_ach_s" func. In this case, the argument slice is 0. +*/ +static void r_ddr_setval_ach(uint32_t regdef, uint32_t val) +{ + r_ddr_setval_ach_s(0U, regdef, val); +} + +/** +* DDRPHY register access write for all channels and all slices (field modify) +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-12:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] regdef Information of destination bit field +* @param[in] val Setting value to be written +* @details +* -# Call the "r_ddr_setval_ach_s" func for all sleces. +*/ +static void r_ddr_setval_ach_as(uint32_t regdef, uint32_t val) +{ + uint32_t slice; + + for (slice = 0U; slice < SLICE_CNT; slice++) + { + r_ddr_setval_ach_s(slice, regdef, val); + } +} + +/** +* DDRPHY register access read to slices0 (field modify) +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-13:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] ch Target channel +* @param[in] regdef Information of destination bit field +* @details +* -# Call the "r_ddr_getval_s" func to slece0. +*/ +static uint32_t r_ddr_getval(uint32_t ch, uint32_t regdef) +{ + return r_ddr_getval_s(ch, 0U, regdef); +} + +/** +* DBSC register access +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-14:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] addr Destination address +* @param[in] data Setting value to be written +* @details +* -# Stores "data" in the pointer indicated by the argument "addr". +*/ +static void r_dbsc_write_32(uintptr_t addr, uint32_t data) +{ + *((volatile uint32_t*)addr) = data; + if ((addr & 0x000A0000U) == 0x000A0000U) + { + *((volatile uint32_t*)(addr + 0x00004000U)) = data; + } + else + { + *((volatile uint32_t*)(addr + 0x00008000U)) = data; + } +} + +/** +* handling functions for setteing ddrphy value table +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-15:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] to First pointer of the static array where the setting value is stored +* @param[in] from First pointer of the source static array +* @param[in] size The size of the source static array +* @details +* -# Copy all the elements of the array specified by "from" pointer to by "to" pointer. +*/ +static void r_tbl_copy(uint32_t *to, const uint32_t *from, uint32_t size) +{ + uint32_t i; + + for (i = 0U; i < size; i++) + { + to[i] = from[i]; + } +} + +/** +* Edit the setting table to the PHY register. +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-16:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] tbl The pointer of target configuration table +* @param[in] regdef Information of destination bit field +* @param[in] val Setting value to be written +* @details +* -# Calculate the target index of *tbl and the bit-field to write the setting value\n +* from "regdef" value.\n +* -# Write the setting value to the target bit-field in the index. +*/ +static void r_ddrtbl_setval(uint32_t *tbl, uint32_t regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000000FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U) << lsb; + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + tbl[adr & adrmsk] = tmp; +} + +/** +* Edit the setting table to the PI register. +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-17:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] tbl The pointer of target configuration table +* @param[in] regdef Information of destination bit field +* @param[in] val Setting value to be written +* @details +* -# Calculate the target index of *tbl and the bit-field to write the setting value\n +* from "regdef" value.\n +* -# Write the setting value to the target bit-field in the index. +*/ +static void r_ddrtbl_setval_pi(uint32_t *tbl, uint32_t regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000007FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U) << lsb; + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + tbl[adr & adrmsk] = tmp; +} + +/** +* Reads the setting values from the setting table to the PHY registers +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-18:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] tbl The pointer of target configuration table +* @param[in] regdef Information of destination bit field +* @details +* -# Calculate the target index of *tbl and the bit-field to read the setting value.\n +* -# Read the setting value from the target bit-field in the index. +*/ +static uint32_t r_ddrtbl_getval(const uint32_t *tbl, uint32_t regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000000FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U); + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) +/** +* Reads the setting values from the setting table to the PI registers +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-19:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] tbl The pointer of target configuration table +* @param[in] regdef Information of destination bit field +* @details +* -# Calculate the target index of *tbl and the bit-field to read the setting value.\n +* -# Read the setting value from the target bit-field in the index. +*/ +static uint32_t r_ddrtbl_getval_pi(const uint32_t *tbl, uint32_t regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000007FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U); + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp >> lsb) & msk; + + return tmp; +} +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + +//! @details functions and parameters for timing setting +typedef struct +{ + //! @details Frequency + uint32_t fx3; + //! @details setting value of Read Latency + uint8_t RLset1; + //! @details setting value of Read Latency + uint8_t RLset2; + //! @details setting value of Write Latency + uint8_t WLsetA; + //! @details setting value of Write Latency + uint8_t WLsetB; + //! @details Write-Recovery for Auto-Precharge commands + uint32_t nWR; + //! @details the minimum interval from a READ command to a PRE command + uint32_t nRBTP; + //! @details On Die Termination + uint32_t ODTLon; + //! @details Mode Register 1 + uint8_t MR1; + //! @details Mode Register 2 + uint8_t MR2; + //! @details The setting time from CAS command to the Start-up of WCK in READ operation + uint32_t WCKENLR; + //! @details The setting time from CAS command to the Start-up of WCK in WRITE operation + uint32_t WCKENLW; + //! @details The setting time from CAS command to the Start-up of WCK in FAST-sync operation + uint32_t WCKENLF; + //! @details The setting time from the Start-up of WCK to WCK Clocling Start + uint32_t WCKPRESTA; + //! @details The setting time from WCK Clocling Start to Reflecting frequency of WCK + uint32_t WCKPRETGLR; +} jedec_spec1_t; + +//! @details Minimum value table for JS1 configuration table that can be taken +#define JS1_USABLEC_SPEC_LO 5U +//! @details Maximum value table for JS1 configuration table that can be taken +#define JS1_USABLEC_SPEC_HI 11U +//! @details The number of JS1 setting table +#define JS1_FREQ_TBL_NUM 12U +//! @details Macro to set the value of MR1 +#define JS1_MR1(f) (0x00U | ((f) << 4)) /* CK mode = 0B */ +//! @details Macro to set the value of MR2 +#define JS1_MR2(f) (((f) << 4) | (f)) +//! @details Declaration of setting table of jedec spec1 +static const jedec_spec1_t js1[JS1_FREQ_TBL_NUM] = +{ + /* fx3, RL1, RL2, WLA.WLB.nWR.nRBTP, ODTLon */ + { 800, 3, 3, 2, 2, 3, 0, 1, JS1_MR1(0), JS1_MR2(0), 0, 0, 0, 1, 3 }, /* 533.333Mbps*/ + { 1600, 4, 4, 2, 3, 5, 0, 1, JS1_MR1(1), JS1_MR2(1), 0, 0, 0, 1, 4 }, /* 1066.666Mbps*/ + { 2400, 5, 6, 3, 4, 7, 0, 2, JS1_MR1(2), JS1_MR2(2), 1, 1, 1, 1, 4 }, /* 1600.000Mbps*/ + { 3200, 7, 7, 4, 5, 10, 0, 2, JS1_MR1(3), JS1_MR2(3), 2, 1, 1, 2, 4 }, /* 2133.333Mbps*/ + { 4000, 8, 9, 4, 7, 12, 1, 2, JS1_MR1(4), JS1_MR2(4), 2, 1, 1, 2, 5 }, /* 2666.666Mbps*/ + { 4800, 10, 10, 5, 8, 14, 1, 3, JS1_MR1(5), JS1_MR2(5), 4, 2, 1, 2, 5 }, /* 3200.000Mbps*/ + { 5600, 11, 12, 6, 9, 16, 2, 4, JS1_MR1(6), JS1_MR2(6), 4, 2, 1, 3, 5 }, /* 3733.333Mbps*/ + { 6400, 13, 14, 6, 11, 19, 2, 3, JS1_MR1(7), JS1_MR2(7), 5, 2, 1, 3, 6 }, /* 4266.666Mbps*/ + { 7200, 14, 15, 7, 12, 21, 3, 4, JS1_MR1(8), JS1_MR2(8), 6, 3, 2, 3, 6 }, /* 4800.000Mbps*/ + { 8250, 16, 17, 8, 14, 24, 4, 5, JS1_MR1(9), JS1_MR2(9), 7, 3, 2, 4, 6 }, /* 5500.000Mbps*/ + { 9000, 17, 19, 9, 15, 26, 4, 6, JS1_MR1(10), JS1_MR2(10), 7, 4, 2, 4, 7 }, /* 6000.000Mbps*/ + { 9600, 18, 20, 9, 16, 28, 4, 6, JS1_MR1(11), JS1_MR2(11), 8, 4, 2, 4, 7 } /* 6400.000Mbps*/ +}; + +//! @details Define of structure of jedec spec2 +typedef struct +{ + //! @details Value in pico seconds + uint16_t ps; + //! @details Value in cycle count + uint16_t cyc; +} jedec_spec2_t; + +//! @details Element for self refresh +#define JS2_tSR 0U +//! @details Exit power-down mode to first valid command +#define JS2_tXP 1U +//! @details Active to read or write delay +#define JS2_tRCD 2U +//! @details Minimum Row Precharge Delay Time +#define JS2_tRPpb 3U +//! @details Minimum Row Precharge Delay Time +#define JS2_tRPab 4U +//! @details ACTIVE-to-PRECHARGE command +#define JS2_tRAS 5U +//! @details Internal WRITE-to-READ command delay +#define JS2_tWTR_S 6U +//! @details Internal WRITE-to-READ command delay +#define JS2_tWTR_L 7U +//! @details Active bank a to active bank b command +#define JS2_tRRD 8U +//! @details Precharge Power Down +#define JS2_tPPD 9U +//! @details Four bank ACT window +#define JS2_tFAW 10U +//! @details Mode Register Read +#define JS2_tMRR 11U +//! @details Mode Register Write +#define JS2_tMRW 12U +//! @details LOAD MODE REGISTER command cycle time +#define JS2_tMRD 13U +//! @details ZQ Calibration +#define JS2_tZQCALns 14U +//! @details ZQ Latency +#define JS2_tZQLAT 15U +//! @details Minimum time on die termination +#define JS2_tODTon_min 16U +//! @details recommended minimum time for Deep Sleep Mode duration +#define JS2_tPDN_DSM 17U +//! @details Required time to be fully re-powered up from Deep Sleep Mode +#define JS2_tXSR_DSM 18U +//! @details Delay from Deep Sleep Mode Exit to Power-Down Exit +#define JS2_tXDSM_XP 19U +//! @details Setting value of DQ to WCK input offset +#define JS2_tWCK2DQI_HF 20U +//! @details Setting value of WCK to DQ output offset +#define JS2_tWCK2DQO_HF 21U +//! @details Setting value of DQ to WCK input offset +#define JS2_tWCK2DQI_LF 22U +//! @details Setting value of WCK to DQ output offset +#define JS2_tWCK2DQO_LF 23U +//! @details Delay time from Stop WCK2DQI Interval Oscillator command to Mode Register Readout +#define JS2_tOSCODQI 24U +//! @details Reception time to change the value fof REF(CA) for Command Bus Training Mode2 +#define JS2_tDQ72DQns 25U +//! @details Reception time to change the value fof REF(CA) for Command Bus Training Mode1 +#define JS2_tCAENTns 26U +//! @details Minimum CA Low Duration time +#define JS2_tCSCAL 27U +//! @details The number of table +#define JS2_TBLCNT 28U +//! @details ACTIVATE-to-ACTIVATE command period with per bank precharge +#define JS2_tRCpb (JS2_TBLCNT) +//! @details ACTIVATE-to-ACTIVATE command period with all bank precharge +#define JS2_tRCab (JS2_TBLCNT + 1U) +//! @details Refresh Cycle Time with All Banks +#define JS2_tRFCab (JS2_TBLCNT + 2U) +//! @details READ Burst end to PRECHARGE command delay +#define JS2_tRBTP (JS2_TBLCNT + 3U) +//! @details Exit Self Refresh to Valid commands +#define JS2_tXSR (JS2_TBLCNT + 4U) + +#define JS2_tPDN (JS2_TBLCNT + 5U) +#define JS2_tWLWCKOFF (JS2_TBLCNT + 6U) +#define JS2_CNT (JS2_TBLCNT + 7U) + +#ifndef JS2_DERATE +#define JS2_DERATE 0 +#endif + +//! @details Declaration of setting table of jedec spec2 +static const jedec_spec2_t jedec_spec2[2][JS2_TBLCNT] = +{ + { +/*tSR */ { 15000, 2 }, +/*tXP */ { 7000, 3 }, +/*tRCD */ { 18000, 2 }, +/*tRPpb */ { 18000, 2 }, +/*tRPab */ { 21000, 2 }, +/*tRAS */ { 42000, 3 }, +/*tWTR_S */ { 6250, 4 }, +/*tWTR_L */ { 12000, 4 }, +/*tRRD */ { 5000, 2 }, +/*tPPD */ { 0, 2 }, +/*tFAW */ { 20000, 0 }, +/*tMRR*/ { 0, 4 }, +/*tMRW*/ { 10000, 5 }, +/*tMRD*/ { 14000, 5 }, +/*tZQCALns*/ { 1500, 0 }, +/*tZQLAT*/ { 30000, 4 }, +/*tODTon_min*/ { 1500, 0 }, +/*tPDN_DSMus*/ { 4000, 0 }, +/*tXSR_DSMus*/ { 200, 0 }, +/*tXDSM_XPus*/ { 190, 0 }, +/*tWCK2DQI_HF*/ { 700, 0 }, +/*tWCK2DQO_HF*/ { 1600, 0 }, +/*tWCK2DQI_LF*/ { 900, 0 }, +/*tWCK2DQO_LF*/ { 1900, 0 }, +/*tOSCODQI*/ { 40000, 8 }, +/*tDQ72DQns*/ { 125, 0 }, +/*tCAENTns*/ { 250, 0 }, +/*tCSCAL*/ { 1750, 0 } + },{ +/*tSR */ { 15000, 2 }, +/*tXP */ { 7000, 3 }, +/*tRCD */ { 19875, 2 }, +/*tRPpb */ { 19875, 2 }, +/*tRPab */ { 22875, 2 }, +/*tRAS */ { 43875, 3 }, +/*tWTR_S */ { 6250, 4 }, +/*tWTR_L */ { 12000, 4 }, +/*tRRD */ { 5000, 2 }, +/*tPPD */ { 0, 2 }, +/*tFAW */ { 20000, 0 }, +/*tMRR*/ { 0, 4 }, +/*tMRW*/ { 10000, 5 }, +/*tMRD*/ { 14000, 5 }, +/*tZQCALns*/ { 1500, 0 }, +/*tZQLAT*/ { 30000, 4 }, +/*tODTon_min*/ { 1500, 0 }, +/*tPDN_DSMus*/ { 4000, 0 }, +/*tXSR_DSMus*/ { 200, 0 }, +/*tXDSM_XPus*/ { 190, 0 }, +/*tWCK2DQI_HF*/ { 715, 0 }, +/*tWCK2DQO_HF*/ { 1635, 0 }, +/*tWCK2DQI_LF*/ { 920, 0 }, +/*tWCK2DQO_LF*/ { 1940, 0 }, +/*tOSCODQI*/ { 40000, 8 }, +/*tDQ72DQns*/ { 125, 0 }, +/*tCAENTns*/ { 250, 0 }, +/*tCSCAL*/ { 1750, 0 } + } +}; + +//! @details 4Gb, 6Gb, 8Gb,12Gb,16Gb (24Gb/32Gb non) +static const uint16_t jedec_spec2_tRFC_ab[9] = +{ +/* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 130, 180, 180, 210, 210, 280, 280, 380, 380 +}; + +//! @details Index of jedec spec1 setting table you use +static uint32_t js1_ind; +//! @details Static global array of jedec spec2 setting table +static uint32_t js2[JS2_CNT]; +//! @details Read latency +static uint32_t RL; +//! @details Write latency +static uint32_t WL; + +/** +* Selection the best value for the setting value among the two elements of structure jedec_spec2 +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-20:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] f_ddr_mbps DDR transmission frequency +* @param[in] f_ddr_mbpsdiv Division DDR transmission frequency +* @param[in] ps Optimal setting value in pico second +* @param[in] cyc Optimal setting value in cycle count +* @return uint32_t Selected the best value for DBSC timing setting +* @details +* -# Convert the optimal value in pico second to in cycle count.\n +* -# Compare the value of the result of the conversion with the value of the argument cyc.\n +* -# Returns the larger value. +*/ +static uint16_t r_f_scale(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint16_t cyc) +{ + uint32_t tmp; + uint32_t f_scale_div; + + tmp = (((uint32_t)(ps) + 9U) / 10U) * f_ddr_mbps; + f_scale_div = tmp / (800000U * f_ddr_mbpsdiv); + if (tmp != (f_scale_div * 800000U * f_ddr_mbpsdiv)) + { + f_scale_div = f_scale_div + 1U; + } + + if (f_scale_div > cyc) + { + cyc = (uint16_t)f_scale_div; + } + + return cyc; +} + +/** +* Selection the best value for the setting value among the two elements of structure jedec_spec2 +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-21:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] f_ddr_mbps DDR transmission frequency +* @param[in] f_ddr_mbpsdiv Division DDR transmission frequency +* @param[in] ps Optimal setting value in pico second +* @param[in] cyc Optimal setting value in cycle count +* @return uint32_t Selected the best value for DBSC timing setting +* @details +* -# Convert the optimal value in pico second to in cycle count. Perform fractional rounding.\n +* -# Compare the value of the result of the conversion with the value of the argument cyc.\n +* -# Returns the larger value. +*/ +static uint32_t r_f_scale_l(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint32_t cyc) +{ + uint32_t tmp; + uint32_t f_scale_div; + + tmp = (((uint32_t)(ps) + 9U) / 10U) * f_ddr_mbps; + f_scale_div = tmp / (8U * f_ddr_mbpsdiv); + if (tmp != (f_scale_div * 8U * f_ddr_mbpsdiv)) + { + f_scale_div = f_scale_div + 1U; + } + + if (f_scale_div > cyc) + { + cyc = (uint32_t)f_scale_div; + } + + return cyc; +} + +/** +* Selection the best value for the setting value among the two elements of structure jedec_spec2 +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-22:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] f_ddr_mbps DDR transmission frequency +* @param[in] f_ddr_mbpsdiv Division DDR transmission frequency +* @param[out] f_js2 Table to store optimized setting value +* @details +* -# Calculate and assign each setting value of jecec_spec2 by "r_f_scale" func with the following arguments.\n +* -# f_ddr_mbps/f_ddr_mbpsdiv/jedec_spec2[JS2_DERATE][i].ps/jedec_spec2[JS2_DERATE][i].cyc\n +* -# Only the following array elements are calculated using different formulas from those described above.\n +* -# JS2_tRRD/JS2_tFAW/JS2_tZQCALns/JS2_tRCpb/JS2_tRCab +*/ +static void r_f_scale_js2(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t *f_js2) +{ + uint32_t i; + + for (i = 0U; i < JS2_TBLCNT; i++) + { + f_js2[i] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, + (uint32_t)jedec_spec2[JS2_DERATE][i].ps, + jedec_spec2[JS2_DERATE][i].cyc); + } + + f_js2[JS2_tZQCALns] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tZQCALns].ps) * 1000U, 0U); + f_js2[JS2_tDQ72DQns] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tDQ72DQns].ps) * 1000U, 0U); + f_js2[JS2_tCAENTns] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tCAENTns].ps) * 1000U, 0U); + f_js2[JS2_tRCpb] = f_js2[JS2_tRAS] + f_js2[JS2_tRPpb]; + f_js2[JS2_tRCab] = f_js2[JS2_tRAS] + f_js2[JS2_tRPab]; + f_js2[JS2_tRFCab] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 1UL * jedec_spec2_tRFC_ab[max_density] * 1000U, 0U); + + f_js2[JS2_tRBTP] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 7500U, 2U) - 2U; + f_js2[JS2_tXSR] = f_js2[JS2_tRFCab] + r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 7500U, 2U); + f_js2[JS2_tPDN] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 10000U, 0U) + 1U; + f_js2[JS2_tPDN_DSM] = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tPDN_DSM].ps) * 10U, 0U); + f_js2[JS2_tXSR_DSM] = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tXSR_DSM].ps) * 10U, 0U); + f_js2[JS2_tXDSM_XP] = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tXDSM_XP].ps) * 10U, 0U); + f_js2[JS2_tWLWCKOFF] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 14000U, 5U); + +} + +//! @details Array of addresses for setting PI_DARRAY3_0 in each CS and frequency-set +static const uint32_t PI_DARRAY3_0_CSx_Fx[CS_CNT][3] = +{ + { + PI_DARRAY3_0_CS0_F0, + PI_DARRAY3_0_CS0_F1, + PI_DARRAY3_0_CS0_F2 + }, + { + PI_DARRAY3_0_CS1_F0, + PI_DARRAY3_0_CS1_F1, + PI_DARRAY3_0_CS1_F2 + } +}; + +//! @details Array of addresses for setting PI_DARRAY3_1 in each CS and frequency-set +static const uint32_t PI_DARRAY3_1_CSx_Fx[CS_CNT][3] = +{ + { + PI_DARRAY3_1_CS0_F0, + PI_DARRAY3_1_CS0_F1, + PI_DARRAY3_1_CS0_F2 + }, + { + PI_DARRAY3_1_CS1_F0, + PI_DARRAY3_1_CS1_F1, + PI_DARRAY3_1_CS1_F2 + } +}; + +/** +* Load table data into DDR registers +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-08:V4H-LPDDR5-DDR-HW-DD-04-01 +* V4H-LPDDR5-DDR-SW-UD-08:V4H-LPDDR5-DDR-HW-DD-10-01-02 +* @details Execute the following processes in order.\n +* -# Determine Jedec_spec1 configuration table based on ddr_mbps and ddr_mbpsdiv.\n +* -# Calculate the value of the Jedec_Spec2 configuration table from ddr_mbps and ddr_mbpsdiv.\n +* -# Copy the configuration table described in init_dram_tbl_v4h_lp5.h to a local array.\n +* -# Change PI register table settings to match ddr_mbps and ddr_mbpsdiv.\n +* -# Set PHY_SET_DFI_INPUT_RST_PAD to High only if WARM_BOOT.\n +* -# If the set value vref_r is not 0, change the "Read Vref (SoC side) Training range" setting\n +* in the configuration table.\n +* -# If the set value vref_w is not 0, change the "Write Vref (MR14, MR15) Training range" setting\n +* in the configuration table.\n +* -# If the set value vref_ca is not 0, change the "CA Vref (MR12) Training range" setting\n +* in the configuration table.\n +* -# If ddr_mbps/ddr_mbpsdiv is less than 5120, change the contents of the PHY register setting table.\n +* -# If ddr_mbps/ddr_mbpsdiv is less than 4576, change the contents of the PHY register setting table.\n +* -# Reflect the contents of the configuration table in the register.\n +*/ +static void r_ddrtbl_load(void) +{ + uint32_t i; + uint32_t slice; + uint32_t cs; + uint32_t adr; + uint32_t dataL; + uint32_t tmp[2]; + + const uint32_t DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_V4H; + const uint32_t DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_V4H; + const uint32_t DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_V4H; + const uint32_t DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_V4H; + + const uint32_t DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_V4H; + + const uint32_t DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_V4H; + const uint32_t DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_V4H; + const uint32_t DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_V4H; + const uint32_t DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_V4H; + + /*********************************************************************** + * TIMING REGISTERS + ***********************************************************************/ + /* search jedec_spec1 index */ + for (i = JS1_USABLEC_SPEC_LO; i < (JS1_FREQ_TBL_NUM - 1U); i++) + { + if ((js1[i].fx3 * 2U * ddr_mbpsdiv) >= (ddr_mbps * 3U)) + { + break; + } + } + + if (JS1_USABLEC_SPEC_HI < i) + { + js1_ind = JS1_USABLEC_SPEC_HI; + } + else + { + js1_ind = i; + } + + RL = js1[js1_ind].RLset1; + + WL = js1[js1_ind].WLsetA; + + /* calculate jedec_spec2 */ + r_f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); + + /*********************************************************************** + * PREPARE TBL + ***********************************************************************/ + r_tbl_copy(DDR_PHY_SLICE_REGSET, + DDR_PHY_SLICE_REGSET_V4H, DDR_PHY_SLICE_REGSET_NUM_V4H); + r_tbl_copy(DDR_PHY_ADR_V_REGSET, + DDR_PHY_ADR_V_REGSET_V4H, DDR_PHY_ADR_V_REGSET_NUM_V4H); + r_tbl_copy(DDR_PHY_ADR_G_REGSET, + DDR_PHY_ADR_G_REGSET_V4H, DDR_PHY_ADR_G_REGSET_NUM_V4H); + r_tbl_copy(DDR_PI_REGSET, + DDR_PI_REGSET_V4H, DDR_PI_REGSET_NUM_V4H); + + /*********************************************************************** + * Adjust PI paramters + ***********************************************************************/ + + dataL = 10000U * ddr_mbps / ddr_mbpsdiv / 8U / 256U; + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_CAL_INTERVAL_COUNT_0, dataL); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_F2, WL); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_WR_ADJ_F2, (js1[js1_ind].WCKENLW * 4U) + 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_RD_ADJ_F2, (js1[js1_ind].WCKENLR * 4U) + 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_STATIC_F2, (js1[js1_ind].WCKPRESTA * 4U)); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_TOGGLE_RD_F2, (js1[js1_ind].WCKPRETGLR) * 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CASLAT_F2, RL); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_FS_ADJ_F2, (js1[js1_ind].WCKENLF * 4U) + 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRFC_F2, js2[JS2_tRFCab]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLVL_WCKOFF_F2, (js2[JS2_tWLWCKOFF]) + 3U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_ADJ_F2, (WL * 4U) + 2U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCAENT_F2, js2[JS2_tCAENTns]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVREF_LONG_F2, (js2[JS2_tCAENTns]) + 1U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVREF_SHORT_F2, (js2[JS2_tCAENTns]) + 1U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRCD_F2, js2[JS2_tRCD]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRP_F2, js2[JS2_tRPab]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRTP_F2, js1[js1_ind].nRBTP); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MIN_F2, js2[JS2_tRAS]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRD_F2, (js2[JS2_tMRD]) + 1U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TSR_F2, js2[JS2_tSR]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQCAL_F2, js2[JS2_tZQCALns]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQLAT_F2, js2[JS2_tZQLAT]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQ72DQ_F2, js2[JS2_tDQ72DQns]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MC_TRFC_F2, js2[JS2_tRFCab]); + + if (ddr_mbps < (3201U * ddr_mbpsdiv)) + { + /* 2751-3200 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x10U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x07U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x0BU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x07U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x25U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x012DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x0BU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x04U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_GATE_SLAVE_DELAY, 0x05U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x03U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x57U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x613U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F0, 0x2BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x2BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x2BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x22U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x1DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x43U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x51U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x29U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_STROBE_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x64U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x12U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x10U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_TWCKENL_RD_ADJ_F2, 0x10U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_RDLAT_ADJ_F2, 0x1EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x0EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQSCK_MAX_F2, 0x01U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x0C26U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x797CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x9BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0014U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x04U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000064U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x000320U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x00000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000029U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x000051U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x000003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_30_F2, 0x00002BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRDCM_LVL_EN_F1, 0x00U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRDCM_LVL_EN_F2, 0x00U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DRAMDCA_LVL_EN_F1, 0x00U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DRAMDCA_LVL_EN_F2, 0x00U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x013880U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x013880U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x0C3500U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000014U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x000320U); + } + else if (ddr_mbps < (3734U * ddr_mbpsdiv)) + { + /* 3201-3733 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x13U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x0AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x0DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x2AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x0149U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x0DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x04U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_GATE_SLAVE_DELAY, 0x9CU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x04U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x5BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x717U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F0, 0x2CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x2CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x2CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x24U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x1FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x45U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x5FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x30U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_STROBE_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x75U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x13U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x12U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_TWCKENL_RD_ADJ_F2, 0x10U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_RDLAT_ADJ_F2, 0x20U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x10U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x0E2EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x8DCCU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0xB5U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0018U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000075U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x0003A6U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000030U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x00005FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x000005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_30_F2, 0x00002DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x016C90U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x016C90U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x0E3D98U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000018U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x0003A6U); + } + else if (ddr_mbps < (4268U * ddr_mbpsdiv)) + { + /* 3734-4267 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x16U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x09U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x0BU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x0EU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x2EU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x0164U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x0EU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x05U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_GATE_SLAVE_DELAY, 0x30U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x04U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x64U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x81CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F0, 0x2DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x2DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x2DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x2BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x20U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x46U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x6CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x37U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x86U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x14U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x13U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_TWCKENL_RD_ADJ_F2, 0x14U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_RDLAT_ADJ_F2, 0x27U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x13U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x1038U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0xA230U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0xCFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x001BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000086U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x00042BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000037U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x00006CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x000006U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_30_F2, 0x000032U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x01A0ABU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x01A0ABU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x1046ABU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x00001BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x00042BU); + } + else if (ddr_mbps < (4801U * ddr_mbpsdiv)) + { + /* 4269-4800 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x18U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x0AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x0DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x10U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x31U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x017FU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x10U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x05U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_GATE_SLAVE_DELAY, 0xC6U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x05U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x68U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x2DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x920U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F0, 0x2EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x2EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x2EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x21U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x47U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x3DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x79U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x14U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x96U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x15U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_TWCKENL_RD_ADJ_F2, 0x18U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_RDLAT_ADJ_F2, 0x29U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x15U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x1240U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0xB680U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x0E9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x001EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000096U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000008U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x0004B0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000015U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x00003DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x000079U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x000008U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_30_F2, 0x000034U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x01D4A9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x01D4A9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x124E91U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x00001EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x0004B0U); + } + else if (ddr_mbps < (5501U * ddr_mbpsdiv)) + { + /* 4801 - 5500 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x1CU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x0CU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x10U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x13U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x37U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x01A3U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x13U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x06U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_GATE_SLAVE_DELAY, 0x8FU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x06U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x71U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x32U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0xA79U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F0, 0x30U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x30U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x30U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x23U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x49U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x46U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x8BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x15U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0xADU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x17U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_TWCKENL_RD_ADJ_F2, 0x1CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_RDLAT_ADJ_F2, 0x2EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x18U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x14F2U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0xD174U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x10BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x0000ADU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x000561U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000019U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000046U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x00008BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x00000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_30_F2, 0x000038U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x0219AFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x0219AFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x1500CFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x000561U); + } + else if (ddr_mbps < (6001U * ddr_mbpsdiv)) + { + /* 5501 - 6000 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x1FU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x12U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x15U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x3AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x01BDU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x15U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x07U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_GATE_SLAVE_DELAY, 0x1BU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x06U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x75U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x34U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0xB6BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F0, 0x31U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x31U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x31U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x4DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x98U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0xBCU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_TWCKENL_RD_ADJ_F2, 0x1CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_RDLAT_ADJ_F2, 0x30U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x1AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x16D6U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0xE45CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x123U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x0000BCU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x0005DDU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x00001BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x00004DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x000098U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_30_F2, 0x00003AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x024A16U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x024A16U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x16E4D8U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x0005DDU); + } + else + { + ; /* Nothing */ + } /* (ddr_mbps < (3201U * ddr_mbpsdiv) */ + + tmp[0] = js1[js1_ind].MR1; + tmp[1] = js1[js1_ind].MR2; + + for (cs = 0U; cs < CS_CNT; cs++) + { + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CSx_Fx[cs][2], tmp[0]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CSx_Fx[cs][2], tmp[1]); + } + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) + { + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_SET_DFI_INPUT_RST_PAD, 0x01U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_PWRUP_SREFRESH_EXIT, 0x01U); + } +#endif /* DDR_BACKUPMODE */ + + /*********************************************************************** + * Read Vref (SoC side) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->bdcfg_vref_r); + if (dataL != 0x0U) + { + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_START_POINT, dataL & 0x000000FFU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_STOP_POINT, (dataL & 0x0000FF00U) >> 8); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_STEPSIZE, (dataL & 0x00FF0000U) >> 16); + } + + /*********************************************************************** + * Write Vref (MR14, MR15) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->bdcfg_vref_w); + if (dataL != 0x0U) + { + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F0, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F1, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F2, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0, (dataL & 0xFF00U) >> 8); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, (dataL & 0xFF00U) >> 8); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2, (dataL & 0xFF00U) >> 8); + } + + /*********************************************************************** + * CA Vref (MR12) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->bdcfg_vref_ca); + if (dataL != 0x0U) + { + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_START_POINT_F0, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_START_POINT_F1, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_START_POINT_F2, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_STOP_POINT_F0, (dataL & 0xFF00U) >> 8); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_STOP_POINT_F1, (dataL & 0xFF00U) >> 8); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_STOP_POINT_F2, (dataL & 0xFF00U) >> 8); + } + + /*********************************************************************** + * Low Freq setting + ***********************************************************************/ + if (ddr_mbps < (8U * 640U * ddr_mbpsdiv)) + { + /* CAL_CLK(10-20MHz) */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_DATA_DC_CAL_CLK_SEL, 0x05U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_CLK_DC_CAL_CLK_SEL, 0x04U); + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_CAL_CLK_SELECT_0, 0x05U); + } + + if (ddr_mbps < (8U * 572U * ddr_mbpsdiv)) + { + /* CAL_CLK(10-20MHz) */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_PCLK_CLK_SEL, 0x03U); + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x02U); + } + + if (ddr_mbps < (8U * 401U * ddr_mbpsdiv)) + { + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PLL_CTRL, 0x1542U); + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PLL_CTRL_8X, 0x3342U); + } + + /*********************************************************************** + * SET DATA SLICE TABLE + ***********************************************************************/ + for (slice = 0U; slice < SLICE_CNT; slice++) + { + adr = DDR_PHY_SLICE_REGSET_OFS + (DDR_PHY_SLICE_REGSET_SIZE * slice); + for (i = 0U; i < DDR_PHY_SLICE_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PHY_SLICE_REGSET[i]); + } + } + + /*********************************************************************** + * SET ADR SLICE TABLE + ***********************************************************************/ + adr = DDR_PHY_ADR_V_REGSET_OFS; + for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PHY_ADR_V_REGSET[i]); + } + + /*********************************************************************** + * SET ADRCTRL SLICE TABLE + ***********************************************************************/ + adr = DDR_PHY_ADR_G_REGSET_OFS; + for (i = 0U; i < DDR_PHY_ADR_G_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PHY_ADR_G_REGSET[i]); + } + + /*********************************************************************** + * SET PI REGISTERS + ***********************************************************************/ + adr = DDR_PI_REGSET_OFS; + for (i = 0U; i < DDR_PI_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PI_REGSET[i]); + } +} + +/** +* CONFIGURE DDR REGISTERS +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-09:V4H-LPDDR5-DDR-HW-DD-10-01-03 +* @details +* -# Set up wiring for DQ and DM pins and VREF_DRIVING.\n +* -# Set the CA pin wiring and ADR_CALVL_SWIZZLE settings.\n +* -# Make wiring settings for the CS pin.\n +* -# When memory rank is 1, set RANK setting to 1 to disable CS training.\n +* -# Configure the DATA_BYTE_SWAP setting.\n +*/ +static void r_ddr_config(void) +{ + uint32_t ch, slice; + uint32_t dataL; + uint8_t high_byte[SLICE_CNT]; + + r_foreach_vch((ch)) + { + /*********************************************************************** + * BOARD SETTINGS (DQ, DM, VREF_DRIVING) + ***********************************************************************/ + for (slice = 0U; slice < SLICE_CNT; slice++) + { + high_byte[slice] = ((uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap) >> (4U * slice)) % 2U; + r_ddr_setval_s(ch, slice, PHY_DQ_DM_SWIZZLE0, Boardcnf->ch[ch].bdcfg_dq_swap[slice]); + r_ddr_setval_s(ch, slice, PHY_DQ_DM_SWIZZLE1, (uint32_t)(Boardcnf->ch[ch].bdcfg_dm_swap[slice])); + if (high_byte[slice] != 0U) + { + /* HIGHER 16 BYTE */ + r_ddr_setval_s(ch, slice, PHY_CALVL_VREF_DRIVING_SLICE, 0x00U); + } + else + { + /* LOWER 16 BYTE */ + r_ddr_setval_s(ch, slice, PHY_CALVL_VREF_DRIVING_SLICE, 0x01U); + } + } + dataL = (0x000000FFU & (uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap)); + r_ddr_setval(ch, PHY_DATA_BYTE_ORDER_SEL, (0x76543200U | dataL)); + + /*********************************************************************** + * BOARD SETTINGS (CA, ADDR_MUX) + ***********************************************************************/ + dataL = (0x0FFFFFFFU & (uint32_t)(Boardcnf->ch[ch].bdcfg_ca_swap)); + + /* --- ADDR_MUX --- */ + r_ddr_setval(ch, PI_ADDR_MUX_0, (0x000000FU & dataL)); + r_ddr_setval(ch, PI_ADDR_MUX_1, (0x000000FU & (dataL >> 4))); + r_ddr_setval(ch, PI_ADDR_MUX_2, (0x000000FU & (dataL >> 8))); + r_ddr_setval(ch, PI_ADDR_MUX_3, (0x000000FU & (dataL >> 12))); + r_ddr_setval(ch, PI_ADDR_MUX_4, (0x000000FU & (dataL >> 16))); + r_ddr_setval(ch, PI_ADDR_MUX_5, (0x000000FU & (dataL >> 20))); + r_ddr_setval(ch, PI_ADDR_MUX_6, (0x000000FU & (dataL >> 24))); + + /* --- ADR_CALVL_SWIZZLE --- */ + r_ddr_setval(ch, PHY_ADR_CALVL_SWIZZLE0, dataL); + + /*********************************************************************** + * BOARD SETTINGS (CS) + ***********************************************************************/ + /* --- CKE_MUX --- */ + /* SoC CKE -> DRAM CS */ + dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_cs_swap); + r_ddr_setval(ch, PI_CKE_MUX_0, ((0x0FU & dataL) + 2U)); + r_ddr_setval(ch, PI_CKE_MUX_1, ((0x0FU & (dataL >> 4)) + 2U)); + r_ddr_setval(ch, PHY_CS_ACS_ALLOCATION_BIT2_2, ((0x0FU & (dataL)) + 1U)); + r_ddr_setval(ch, PHY_CS_ACS_ALLOCATION_BIT3_2, ((0x0FU & (dataL >> 4)) + 1U)); + + /*********************************************************************** + * mask CS_MAP if RANK1 is not found + ***********************************************************************/ + if ((ch_have_this_cs[1] & (1U << ch)) == 0x0U) + { + r_ddr_setval(ch, PHY_ADR_CALVL_RANK_CTRL, 0x00U); + for (slice = 0U; slice < SLICE_CNT; slice++) + { + r_ddr_setval_s(ch, slice, PHY_PER_CS_TRAINING_EN, 0x00U); + } + } + } + + r_foreach_vch((ch)) + { + /* --- DATA_BYTE_SWAP --- */ + dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap); + r_ddr_setval(ch, PI_DATA_BYTE_SWAP_EN, 0x01U); + r_ddr_setval(ch, PI_DATA_BYTE_SWAP_SLICE0, dataL & 0x0FU); + r_ddr_setval(ch, PI_DATA_BYTE_SWAP_SLICE1, (dataL >> 4) & 0x0FU); + + if ((ch_have_this_cs[1] & (1U << ch)) == 0x0U) + { + r_ddr_setval(ch, PI_CS_MAP, 0x01U); + } + } +} + +/** +* DBSC register setting functions +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-03:V4H-LPDDR5-DDR-HW-DD-10-04-02 +* @details +* -# Set SDRAM type, Burst length, and PHY type.\n +* -# Frequency mode setting.\n +* -# Write SDRAM configuration contents to registers.\n +*/ +static void r_dbsc_regset_pre(void) +{ + uint32_t ch, cs; + + /*********************************************************************** + * PRIMARY SETTINGS + ***********************************************************************/ + /* LPDDR5, BL=16, DFI interface */ + r_dbsc_write_32(DBSC_DBMEMKIND, 0x0000000CU); + r_dbsc_write_32(DBSC_DBMEMKINDA, 0x0000000CU); + r_dbsc_write_32(DBSC_DBBL, 0x00000002U); + r_dbsc_write_32(DBSC_DBBLA, 0x00000002U); + r_dbsc_write_32(DBSC_DBPHYCONF0, 0x00000001U); + + r_dbsc_write_32(DBSC_DBSYSCONF0, 0x00000001U); + + /* FREQRATIO=2 */ + r_dbsc_write_32(DBSC_DBSYSCONF1, 0x00020000U); + r_dbsc_write_32(DBSC_DBSYSCONF1A, 0x00000000U); + + r_dbsc_write_32(DBSC_DBSYSCONF2, 0x00000001U); + r_dbsc_write_32(DBSC_DBSYSCONF2A, 0x00000241U); + + r_foreach_ech((ch)) + { + for (cs = 0U; cs < CS_CNT; cs++) + { + if (ddr_density[ch][cs] == 0xFFU) + { + mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00U); + mmio_write_32(DBSC_DBMEMCONFA(ch, cs), 0x00U); + } + else + { + mmio_write_32(DBSC_DBMEMCONF(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs])); + mmio_write_32(DBSC_DBMEMCONFA(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs])); + } + } + } +} + +/** +* Set DBSC timing parameters. +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-04:V4H-LPDDR5-DDR-HW-DD-10-04-03 +* @details +* -# Set the timing registers of the DBSC.\n +* -# Configure Scheduler settings.\n +*/ +static void r_dbsc_regset(void) +{ + uint32_t tmp[4]; + + /* DBTR0.CL : RL */ + r_dbsc_write_32(DBSC_DBTR(0U), RL); + + /* DBTR1.CWL : WL */ + r_dbsc_write_32(DBSC_DBTR(1U), WL); + + /* DBTR2.AL = 0 */ + r_dbsc_write_32(DBSC_DBTR(2U), 0x00000000U); + + /* DBTR3.TRCD: tRCD */ + r_dbsc_write_32(DBSC_DBTR(3U), js2[JS2_tRCD]); + + /* DBTR4.TRPA,TRP: tRPab,tRPpb */ + r_dbsc_write_32(DBSC_DBTR(4U), ((js2[JS2_tRPab] << 16) | js2[JS2_tRPpb])); + + /* DBTR5.TRC : tRCpb */ + r_dbsc_write_32(DBSC_DBTR(5U), js2[JS2_tRCpb]); + + /* DBTR6.TRAS : tRAS */ + r_dbsc_write_32(DBSC_DBTR(6U), js2[JS2_tRAS]); + + /* DBTR7.TRRD : tRRD */ + r_dbsc_write_32(DBSC_DBTR(7U), ((js2[JS2_tRRD] - 1U) << 16) | (js2[JS2_tRRD] - 1U)); + + /* DBTR8.TFAW : tFAW */ + r_dbsc_write_32(DBSC_DBTR(8U), (js2[JS2_tFAW] - 1U)); + + /* DBTR9.TRDPR: nRBTP */ + r_dbsc_write_32(DBSC_DBTR(9U), (js1[js1_ind].nRBTP)); + + /* DBTR10.TWR : nWR */ + r_dbsc_write_32(DBSC_DBTR(10U), js1[js1_ind].nWR); + + /* DBTR11.TRDWR : RL + BL/n_max + RU(tWCK2DQO(max)/tCK) + RD(tRPST/tCK) - ODTLon - RD(tODTon(min)/tCK) + 1 + feature */ + r_dbsc_write_32(DBSC_DBTR(11U), (RL + 4U + js2[JS2_tWCK2DQO_HF] + 0U - js1[js1_ind].ODTLon - (js2[JS2_tODTon_min] - 1U) + 1U + 0U)); + + /* DBTR12.TWRRD_S : WL + BL/2 + tWTR_S, TWRRD_L : WL + BL + tWTR_L */ + r_dbsc_write_32(DBSC_DBTR(12U), (((WL + 2U + js2[JS2_tWTR_S]) << 16) | (WL + 4U + js2[JS2_tWTR_L]))); + + /* DBTR13.TRFCAB : tRFCab */ + r_dbsc_write_32(DBSC_DBTR(13U), (js2[JS2_tRFCab])); + + /* DBTR14.TCSCAL,TCKEHDLL,tCKEH : tCSCAL,tXP,tXP */ + r_dbsc_write_32(DBSC_DBTR(14U), ((js2[JS2_tCSCAL] << 24) | (js2[JS2_tXP] << 16) | js2[JS2_tXP])); + + /* DBTR15.TESPD,TCKESR,TCKEL : tESPD = 2,tSR,tSR */ + r_dbsc_write_32(DBSC_DBTR(15U), ((0x02U << 24) | (js2[JS2_tSR] << 16) | js2[JS2_tSR])); + + /* DBTR16 */ + /* wdql(tphy_wrlat + tphy_wrdata) */ + tmp[0] = (WL * 4U) - 1U + 5U; + /* dqenltcy(tphy_wrlat) */ + tmp[1] = (WL * 4U) - 2U - 2U + 5U; + /* dql(tphy_rdlat + trddata_en) RL * 4 + phy_rptr_update + phy_rddqs_latency_adjust + 39 */ + tmp[2] = (RL * 4U) + r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE) + r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST) + 39U; + /* dqienltncy(trddata_en) RL * 4 - phy_rddata_en_dly_X + 4 * phy_wck_freq_ratio_X */ + tmp[3] = (RL * 4U) + 4U - r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY); + r_dbsc_write_32(DBSC_DBTR(16U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR17.TMODRD,TMOD: tMRR,tMRW */ + r_dbsc_write_32(DBSC_DBTR(17U), ((js2[JS2_tMRR] << 24) | (js2[JS2_tMRW] << 16))); + + /* DBTR18. RODTL, RODTA = 0 */ + r_dbsc_write_32(DBSC_DBTR(18U), 0x00000000U); + + /* DBTR19. TZQCL, TZQCS = 0 */ + r_dbsc_write_32(DBSC_DBTR(19U), 0x00000000U); + + /* DBTR20.TXSDLL, TXS : tXSR,tXSR */ + r_dbsc_write_32(DBSC_DBTR(20U), ((js2[JS2_tXSR]) << 16) | (js2[JS2_tXSR])); + + /* DBTR21.TCCD */ + r_dbsc_write_32(DBSC_DBTR(21U), ((ddr_tccd << 16) | (ddr_tccd * 2U))); + + /* DBTR22.TZQCAL,TZQLAT : tZQCAL,tZQLAT */ + r_dbsc_write_32(DBSC_DBTR(22U), ((js2[JS2_tZQCALns] << 16) | js2[JS2_tZQLAT])); + + /* DBTR23. RRSPC = 0 */ + r_dbsc_write_32(DBSC_DBTR(23U), 0x00000000U); + + /* DBTR24 */ + /* WRCSLAT(tphy_wrcslat) */ + tmp[0] = (WL * 4U) - 2U; + /* WRCSGAP(tphy_wrcsgap) */ + tmp[1] = 0x0CU; + /* RDCSLAT(tphy_rdcslat) */ + tmp[2] = RL * 4U; + /* RDCSGAP(tphy_rdcsgap) */ + tmp[3] = 0x0CU; + r_dbsc_write_32(DBSC_DBTR(24U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR25. TWDQLVLDIS = 0 */ + r_dbsc_write_32(DBSC_DBTR(25U), 0x00000000U); + + /* DBTR26. TWCK2DQOOSC,TDQSOSC : WCK2DQI interval timer run time, WCK2DQO interval timer run time */ + r_dbsc_write_32(DBSC_DBTR(26U), 0x00000000U); + + /* DBTR27.TPDN : tPDN */ + r_dbsc_write_32(DBSC_DBTR(27U), js2[JS2_tPDN]); + + /* DBTR28.txsrdsm : tXSR_DSM */ + r_dbsc_write_32(DBSC_DBTR(28U), js2[JS2_tXSR_DSM]); + + /* DBTR29.tdsmxp : tXDSM_XP */ + r_dbsc_write_32(DBSC_DBTR(29U), js2[JS2_tXDSM_XP]); + + /* DBTR30.TCMDPD : tCMDPD = 3 */ + r_dbsc_write_32(DBSC_DBTR(30U), 0x00000003U); + + /* DBTR31.TWCK2DQOMAX,TWCK2DQIMAX : tWCK2DQI/O_HF/LF */ + r_dbsc_write_32(DBSC_DBTR(31U), ((js2[JS2_tWCK2DQO_HF] << 4) | js2[JS2_tWCK2DQI_HF])); + + /* DBTR32 */ + /* twckenr */ + tmp[0] = (js1[js1_ind].WCKENLR * 4U) + 4U - 1U; + /* twckenw */ + tmp[1] = (js1[js1_ind].WCKENLW * 4U) + 4U - 1U; + /* twckenlf */ + tmp[2] = (js1[js1_ind].WCKENLF * 4U) + 4U; + /* twckpresta */ + tmp[3] = js1[js1_ind].WCKPRESTA * 4U; + r_dbsc_write_32(DBSC_DBTR(32U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR33 */ + /* TWCKTGL */ + tmp[0] = 4U; + /* TWCKDIS (RL+ bl/n_max) * 4 + RU(tWCKPST/tWCK) : tWCKPST = 2.5(MR10[3:2]) */ + tmp[1] = ((RL + 4U) * 4U) + 3U; + r_dbsc_write_32(DBSC_DBTR(33U), ((tmp[1] << 8) | tmp[0])); + + /* DBTR34 */ + /* TWCKSUS = 4 */ + tmp[0] = 4U; + /* TWCKPST RU(tWCKPST/tCK) : tWCKPST=2.5(MR10[3:2]) */ + tmp[1] = 1U; + r_dbsc_write_32(DBSC_DBTR(34U), ((tmp[1] << 8) | tmp[0])); + + /* DBTR35 */ + /* TRD2WCKOFF RL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[0] = RL + 4U + 0U +1U; + /* TWR2WCKOFF WL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[1] = WL + 4U + 0U +1U; + r_dbsc_write_32(DBSC_DBTR(35U), ((tmp[1] << 16) | tmp[0])); + + /* DBTR36 */ + /* TWSSUSWRX : CAS(WCKSUS)WRX */ + tmp[0] = 3U; + /* TWSOFFWRX : CAS(WS_OFF)WRX */ + tmp[1] = 3U; + /* TWSFSWRX : CAS(WS_FS)WRX */ + tmp[2] = 2U; + r_dbsc_write_32(DBSC_DBTR(36U), ((tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR37 */ + /* tOSCO */ + r_dbsc_write_32(DBSC_DBTR(37U), js2[JS2_tOSCODQI]); + + /* DBRNK2 */ + /* RNKRR = 12 */ + r_dbsc_write_32(DBSC_DBRNK(2U), 0x000000CCU); + + /* DBRNK3 */ + /* RNKRW = 6 */ + r_dbsc_write_32(DBSC_DBRNK(3U), 0x00000066U); + + /* DBRNK4 */ + /* RNKWR = 6 */ + r_dbsc_write_32(DBSC_DBRNK(4U), 0x00000066U); + + /* DBRNK5 */ + /* RNKWW = 14 */ + r_dbsc_write_32(DBSC_DBRNK(5U), 0x000000EEU); + + /*********************************************************************** + * timing registers for Scheduler + ***********************************************************************/ + /* SCFCTST0 */ + /* SCPREACT */ + tmp[0] = 1UL * js2[JS2_tRPpb] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* SCACTRDWR */ + tmp[1] = 1UL * (WL + 2U + 1U + js1[js1_ind].nWR + js2[JS2_tRPpb]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* SCRDACRT */ + tmp[2] = 1UL * ((js1[js1_ind].nRBTP + 2U) + js2[JS2_tRPpb]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* SCACTACT */ + tmp[3] = 1UL * js2[JS2_tRCpb] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + r_dbsc_write_32(DBSC_DBSCHFCTST0, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* SCFCTST1 */ + /* SCASYNCOFS */ + tmp[0] = 12; + /* SCACTRDWR */ + tmp[1] = 1UL * js2[JS2_tRCD] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* SCWRRD */ + tmp[2] = 1UL * (mmio_read_32(DBSC_DBTR(12U)) & 0xFFU) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* SCRDWR */ + tmp[3] = 1UL * (mmio_read_32(DBSC_DBTR(11U)) & 0xFFU) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + r_dbsc_write_32(DBSC_DBSCHFCTST1, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBSCHRW1 */ + /* SCTRFCAB */ + tmp[0] = 1UL * (js2[JS2_tRFCab] + js2[JS2_tZQLAT]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + r_dbsc_write_32(DBSC_DBSCHRW1, tmp[0]); + + /* DBSCHTR0 */ + /* SCDT0 */ + tmp[0] = (1UL * 4U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + /* SCDT1 */ + tmp[1] = (1UL * 8U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + /* SCDT2 */ + tmp[2] = (1UL * 12U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + /* SCDT3 */ + tmp[3] = (1UL * 16U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + r_dbsc_write_32(DBSC_DBSCHTR0, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /*********************************************************************** + * QOS and CAM + ***********************************************************************/ + r_dbsc_write_32(DBSC_DBBCAMDIS, 0x00000001U); +} + +/** +* DBSC Register Setting +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-05:V4H-LPDDR5-DDR-HW-DD-01-05 +* V4H-LPDDR5-DDR-SW-UD-05:V4H-LPDDR5-DDR-HW-DD-02-01 +* V4H-LPDDR5-DDR-SW-UD-05:V4H-LPDDR5-DDR-HW-DD-04-02 +* V4H-LPDDR5-DDR-SW-UD-05:V4H-LPDDR5-DDR-HW-DD-10-04-04 +* @details Execute following flow. +* -# If memory rank is 2, CS_TRAINING_EN is set to the other side.\n +* -# Configure DBI read/write settings.\n +* -# Execute DRAM refresh settings.\n +* -# Set WTmode of DFI PHY to OFF.\n +* -# Set up PHY Periodic Write DQ training.\n +* -# Set WTmode of DFI PHY to ON.\n +* -# Calibration settings for PHY PAD.\n +* -# Set SDRAM calibration.\n +* -# Make DFI Control Update Setting settings..\n +* -# In the case of WARM_BOOT, cancel the self-refresh setting.\n +* -# Enable SDRAM auto refresh.\n +* -# Set up PHY Periodic Write DQ training.\n +* -# Enable access to SDRAM.\n +*/ +static void r_dbsc_regset_post(void) +{ + uint32_t ch, slice; + uint32_t dataL; + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + uint32_t ctrl_clk; + uint32_t clk_count; + uint32_t phymster_req_interval; +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + + if (Prr_Cut < PRR_PRODUCT_30) + { + if (ch_have_this_cs[1] != 0x0U) + { + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + r_ddr_setval_s(ch, slice, PHY_PER_CS_TRAINING_EN, 0x00U); + } + } + } + } + + r_dbsc_write_32(DBSC_DBDBICNT, 0x00000003U); + + /* set REFCYCLE */ + dataL = DBSC_REFINT * ddr_mbps / 8000U / ddr_mbpsdiv; + /* refpmax=8 */ + r_dbsc_write_32(DBSC_DBRFCNF1, 0x00080000U | (dataL & 0x0000FFFFU)); + /* refpmin=1 */ + r_dbsc_write_32(DBSC_DBRFCNF2, 0x00010000U | DBSC_REFINTS); + + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000U); +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + +#if (RCAR_PERIODIC_WRITE_TRAINING != 0U) + /* Periodic-WriteDQ Training setting */ + r_ddr_setval_ach(PI_WDQLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_WDQLVL_VREF_EN, 0x00U); + r_ddr_setval_ach_as(PHY_DATA_DC_WDQLVL_ENABLE, 0x00U); + r_ddr_setval_ach(PI_WDQLVL_PERIODIC, 0x01U); +#endif /* (RCAR_PERIODIC_WRITE_TRAINING != 0U) */ + +#if (RCAR_PERIODIC_READ_TRAINING != 0U) + /* Periodic-ReadDQ Training setting */ + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F2, 0x00U); + r_ddr_setval_ach_as(PHY_RDLVL_DLY_STEP, 0x04U); + r_ddr_setval_ach(PI_RDLVL_PERIODIC, 0x01U); +#endif /* (RCAR_PERIODIC_READ_TRAINING != 0) */ + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + /* DFI_PHYMSTR_ACK , WTmode = b'01 */ + r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011U); +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + + /* periodic SoC zqcal enable */ + r_ddr_setval_ach(PHY_CAL_MODE_0, r_ddrtbl_getval(DDR_PHY_ADR_G_REGSET, PHY_CAL_MODE_0) | 0x02U); + + /* periodic dram zqcal enable */ + r_dbsc_write_32(DBSC_DBCALCNF, 0x01000010U); + + /* periodic phy ctrl update enable */ + r_dbsc_write_32(DBSC_DBDFICUPDCNF, 0x504C0001U); + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) + { + /* SRX */ + r_send_dbcmd2(0x0A840001U); + } +#endif /* DDR_BACKUPMODE */ + /* set Auto Refresh */ + r_dbsc_write_32(DBSC_DBRFEN, 0x00000001U); + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + /* Periodic-WriteDQ/ReadDQ Training Interval setting */ + phymster_req_interval = PERIODIC_TRAINING_INTERVAL - 3000U; + clk_count = 1024U - (r_ddrtbl_getval_pi(DDR_PI_REGSET, PI_LONG_COUNT_MASK) * 32U); + ctrl_clk = ddr_mbps / ddr_mbpsdiv / 8U; + dataL = phymster_req_interval * ctrl_clk / clk_count; +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + +#if (RCAR_PERIODIC_WRITE_TRAINING != 0U) + r_ddr_setval_ach(PI_WDQLVL_INTERVAL, dataL); +#endif /* RCAR_PERIODIC_WRITE_TRAINING */ + +#if ((RCAR_PERIODIC_READ_TRAINING != 0U) && (RCAR_PERIODIC_TRAINING_SEPARATE_MODE == 0U)) + r_ddr_setval_ach(PI_RDLVL_INTERVAL, dataL); +#endif /* ((RCAR_PERIODIC_READ_TRAINING != 0U) && (RCAR_PERIODIC_TRAINING_SEPARATE_MODE == 0U)) */ + + /* dram access enable */ + r_dbsc_write_32(DBSC_DBACEN, 0x00000001U); + + MSG_LF("dbsc_regset_post(done)\n"); +} + +/** +* training by PI +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-02:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Enable WCK signal training and read gate training.\n +* -# Start PI training.\n +* -# After DFI initialization for all channels is once turned off, turned on all chennels of it.\n +* -# Power down the DRAM device once and then release the power down mode.\n +* -# Perform training in low frequency mode and training in high frequency mode.\n +* -# Wait for the DFI training completion status bit to stand until the time limit.\n +* -# Turn off DFI initialization for all channels.\n +* -# Turn off WTMODE of DFI PHY.\n +* -# Check if CA/CS Training has failed.\n +* -# Checking if Wrlvl training is in error.\n +* -# If an error can be confirmed from the check result, the result is returned as a return value.\n +* -# Clear the status register for PI training.\n +*/ +static uint32_t r_pi_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + uint32_t frqchg_req; + uint32_t flag; + + uint32_t complete_ng; + uint32_t ca_training_ng; + uint32_t wr_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + /*********************************************************************** + * init start + ***********************************************************************/ + + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WRDCM_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WDQLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_DFS_INITIALIZATION_SEQ_9, 0x00000000U); + r_ddr_setval_ach(PI_DFS_INITIALIZATION_SEQ_10, 0x00000000U); + + /* PI_START */ + r_ddr_setval_ach(PI_START, 0x01U); + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) + { + r_ddr_setval_ach(PI_DLL_RST, 0x01U); + r_ddr_setval_ach(PI_PWRUP_SREFRESH_EXIT, 0x00U); + } +#endif /* DDR_BACKUPMODE */ + + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000020U); + } + + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000021U); + } + + /* Dummy PDE */ + r_send_dbcmd2(0x08840000U); + + /* PDX */ + r_send_dbcmd2(0x08840001U); + + /*********************************************************************** + * wait init_complete + ***********************************************************************/ + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + frqchg_req = 0U; + for (ch = 0U; ch < DRAM_CH_CNT; ch++) + { + if ((((~phytrainingok) & ddr_phyvalid) & (1U << ch)) != 0x0U) + { + if ((mmio_read_32(DBSC_DBPDSTAT0(ch)) & 0x01U) != 0x0U) + { + frqchg_req = 1U; + break; + } + } + } + + if (frqchg_req != 0x0U) + { + flag = r_pll3_freq(); + if (flag != 0x0U) + { + break; + } + } + else + { + r_foreach_vch((ch)) + { + dataL = mmio_read_32(DBSC_DBDFISTAT(ch)); + if ((dataL & 0x00000001U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + }/* (frqchg_req != 0x0U) */ + } + + /* dbdficnt0: + * dfi_dram_clk_disable=0 + * dfi_frequency = 0 + * freq_ratio = 10 (4:1) + * init_start =0 + */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000020U); + } + + /* DFI_PHYMSTR_ACK */ + r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001U); + + complete_ng = 0x0U; + ca_training_ng = 0x0U; + wr_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* CA/CS Training Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 4 )); /* PI_CALVL_ERROR_BIT */ + dataL |= (r_ddr_getval(ch, PHY_ADR_CALVL_OBS1) & (0x3U << 30 )); /* error on decrement/increment pass */ + dataL |= (r_ddr_getval(ch, PHY_ADR_CALVL_OBS2) & (0x3U << 24 )); /* start outside of initial search range */ + dataL |= (r_ddr_getval(ch, PHY_CSLVL_OBS1) & (0xFU << 28 )); /* CSlvl error */ + if (dataL != 0x0U) + { + ca_training_ng |= 1U << ch; + MSG_LF("pi_training_error:1\n"); + } + + /* Wrlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3 )); /* PI_WRLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12 )); /* SLICE0 wrlvl error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12 )); /* SLICE1 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS); /* SLICE0 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS); /* SLICE1 wrlvl error */ + if (dataL != 0x0U) + { + wr_training_ng |= 1U << ch; + MSG_LF("pi_training_error:2\n"); + } + } + + complete_ng = (wr_training_ng | ca_training_ng); + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x07U); + } + + return phytrainingok; +} + +/** +* Write Leveling Cycle Adjust +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-05:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Get delay value from the result write leveling of slice 0.\n +* -# Calculate latency of dfi_wrdata_en / dfi_wrdata / dfi_wrdata_mask signals based on delay values.\n +* -# Get delay value from the result write leveling of slice 1.\n +* -# Calculate latency of dfi_wrdata_en / dfi_wrdata / dfi_wrdata_mask signals based on delay values.\n +*/ +static void r_write_leveling_adjust(void) +{ + uint32_t ch; + uint32_t result_hard0; + uint32_t result_hard1; + uint32_t avg; + uint32_t avg_frac; + uint32_t avg_cycle; + + r_foreach_vch((ch)) + { + /* SLICE0 */ + result_hard0 = r_ddr_getval_s(ch, 0U, PHY_WRLVL_HARD0_DELAY_OBS); + result_hard1 = r_ddr_getval_s(ch, 0U, PHY_WRLVL_HARD1_DELAY_OBS); + + if (result_hard0 <= result_hard1) + { + avg = (result_hard0 + result_hard1) / 2U; + } + else + { + avg = (result_hard0 + result_hard1 + 0x400U) / 2U; + } + avg_frac = avg & 0xFFU; + avg_cycle = (avg >> 8) & 0x3U; + + if (avg_cycle == 0x3U) + { + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_DEC, 0x1U); + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_ADD, 0x0U); + } + else + { + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_DEC, 0x0U); + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_ADD, avg_cycle); + } + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_FRAC, avg_frac); + + /* SLICE1 */ + result_hard0 = r_ddr_getval_s(ch, 1U, PHY_WRLVL_HARD0_DELAY_OBS); + result_hard1 = r_ddr_getval_s(ch, 1U, PHY_WRLVL_HARD1_DELAY_OBS); + + if (result_hard0 <= result_hard1) + { + avg = (result_hard0 + result_hard1) / 2U; + } + else + { + avg = (result_hard0 + result_hard1 + 0x400U) / 2U; + } + avg_frac = avg & 0xFFU; + avg_cycle = (avg >> 8) & 0x3U; + + if (avg_cycle == 0x3U) + { + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_DEC, 0x1U); + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_ADD, 0x0U); + } + else + { + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_DEC, 0x0U); + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_ADD, avg_cycle); + } + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_FRAC, avg_frac); + } + + r_ddr_setval_ach_as(SC_PHY_WCK_CALC, 0x01U); + +} + +/** +* Re-run Write Leveling & Read Gate Training +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-06:V4H-LPDDR5-DDR-HW-FD-10-0 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Set CA leveling OFF, read gate leveling ON, write gate leveling ON, PI dram wck training ON.\n +* -# Perform PI_DFS configuration.\n +* -# Start PI frequency training in manual mode.\n +* -# Perform training in high-frequency mode.\n +* -# Check for Write leveling Error and Gate leveling Error.\n +* -# If an error is identified, the resulting value is inverted and returned.\n +* -# Clear the PI status register.\n +*/ +static uint32_t r_wl_gt_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + + uint32_t complete_ng; + uint32_t wr_training_ng; + uint32_t gt_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + r_ddr_setval_ach(PI_CALVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x01U); + + r_ddr_setval_ach(PI_DFS_ENTRY_SEQ_0, 0x181F0000U); + r_ddr_setval_ach(PI_DFS_INITIALIZATION_SEQ_1, 0x00000000U); + r_ddr_setval_ach(PI_TRAIN_ALL_FREQ_REQ, 0x01U); + + /* Freq Change High to High*/ + dataL = r_pll3_freq(); + if (dataL != 0x0U) + { + return (1); + } + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if ((dataL & 0x1U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + wr_training_ng = 0x0U; + gt_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Wrlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3 )); /* PI_WRLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12 )); /* SLICE0 wrlvl error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12 )); /* SLICE1 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS); /* SLICE0 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS); /* SLICE1 wrlvl error */ + if (dataL != 0x0U) + { + wr_training_ng |= 1U << ch; + MSG_LF("wl_gt_training_error:1\n"); + } + /* Gtlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 2 )); /* PI_RDLVL_GATE_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7 )); /* SLICE0 delay setup error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7 )); /* SLICE1 delay setup error */ + if (dataL != 0x0U) + { + gt_training_ng |= 1U << ch; + MSG_LF("wl_gt_training_error:2\n"); + } + } + + complete_ng = (wr_training_ng | gt_training_ng); + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x07U); + } + + return phytrainingok; +} + +/** +* Write DCA Training +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-07:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Get DCA Training CS0 Flip-0 training results for RANK0.\n +* -# Get DCA Training CS1 Flip-0 training results for RANK0.\n +* -# Calculate DRAMDCA settings from training results and write them to registers.\n +* -# Set DRAM DCA in MR30.\n +* -# Ensure that the training has been successfully completed..\n +* -# Clear CA status to 0.\n +*/ +static void r_write_dca(void) +{ + uint32_t ch; + uint32_t dataL; + uint32_t phytrainingok; + uint32_t retry; + const uint32_t RETRY_MAX = 0x10000U; + + r_ddr_setval_ach_as(PHY_DATA_DC_CAL_START, 0x01U); + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = (r_ddr_getval_s(ch, 0U, PHY_DATA_DC_CAL_START)) | (r_ddr_getval_s(ch, 1U, PHY_DATA_DC_CAL_START)); + if (dataL == 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } +} + +/** +* DRAM DCA Training and Calculations +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-07:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Get DCA Training CS0 Flip-0 training results for RANK0.\n +* -# Get DCA Training CS1 Flip-0 training results for RANK0.\n +* -# Calculate DRAMDCA settings from training results and write them to registers.\n +* -# Set DRAM DCA in MR30.\n +* -# Ensure that the training has been successfully completed..\n +* -# Clear CA status to 0.\n +*/ +static uint32_t r_dramdca_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t dataL; + uint32_t rank; + uint32_t dca_result_l_0[DRAM_CH_CNT][CS_CNT]; /* DCA_result_lower_flip0_[ch][cs] */ + uint32_t dca_result_u_0[DRAM_CH_CNT][CS_CNT]; /* DCA_result_upper_flip0_[ch][cs] */ + uint32_t dca_result_l_1[DRAM_CH_CNT][CS_CNT]; /* DCA_result_lower_flip1_[ch][cs] */ + uint32_t dca_result_u_1[DRAM_CH_CNT][CS_CNT]; /* DCA_result_upper_flip1_[ch][cs] */ + uint32_t tempu; + uint32_t templ; + + const uint32_t mr30_conv[16] = + { + 0x08U, 0x07U, 0x06U, 0x05U, 0x04U, 0x03U, 0x02U, 0x01U, + 0x00U, 0x09U, 0x0AU, 0x0BU, 0x0CU, 0x0DU, 0x0EU, 0x0FU + }; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + /*********************************************************************** + * Run DRAM DCA Training for Flip-0 + ***********************************************************************/ + r_ddr_setval_ach(PI_DCMLVL_CS_SW, rank); + + /* DRAMDCA go */ + r_ddr_setval_ach(PI_DRAMDCA_LVL_REQ, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = r_pi_int_ack_0_assert(28U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + /* result for DRAMDCA flip-0 */ + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS0_F2); + dca_result_u_0[ch][0] = mr30_conv[dataL >> 4]; + dca_result_l_0[ch][0] = mr30_conv[dataL & 0x0FU]; + if ((rank & 0x02U) != 0x0U) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS1_F2); + dca_result_u_0[ch][1] = mr30_conv[dataL >> 4]; + dca_result_l_0[ch][1] = mr30_conv[dataL & 0x0FU]; + } + } + + /*********************************************************************** + * Run DRAM DCA Training for Flip-1 + ***********************************************************************/ + r_ddr_setval_ach(PI_DRAMDCA_FLIP_MASK, 0x01U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_ACTIVE_SEQ_2, 0x00000000U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_ACTIVE_SEQ_3, 0x00000000U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_ACTIVE_SEQ_4, 0x00000000U); + + /* DRAMDCA go */ + r_ddr_setval_ach(PI_DRAMDCA_LVL_REQ, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = r_pi_int_ack_0_assert(28U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + /* result for DRAMDCA flip-1 */ + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS0_F2); + dca_result_u_1[ch][0] = mr30_conv[dataL >> 4]; + dca_result_l_1[ch][0] = mr30_conv[dataL & 0x0FU]; + if ((rank & 0x02U) != 0x0U) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS1_F2); + dca_result_u_1[ch][1] = mr30_conv[dataL >> 4]; + dca_result_l_1[ch][1] = mr30_conv[dataL & 0x0FU]; + } + } + + /*********************************************************************** + * Calculate and set DRAMDCA value + ***********************************************************************/ + r_foreach_vch((ch)) + { + /* CS0 */ + tempu = (dca_result_u_0[ch][0] + dca_result_u_1[ch][0]) / 2U; + templ = (dca_result_l_0[ch][0] + dca_result_l_1[ch][0]) / 2U; + dataL = (mr30_conv[tempu] << 4) | (mr30_conv[templ]); + r_ddr_setval(ch, PI_DARRAY3_20_CS0_F2, dataL); + if ((rank & 0x02U) != 0x0U) + { + /* CS1 */ + tempu = (dca_result_u_0[ch][1] + dca_result_u_1[ch][1]) / 2U; + templ = (dca_result_l_0[ch][1] + dca_result_l_1[ch][1]) / 2U; + dataL = (mr30_conv[tempu] << 4) | (mr30_conv[templ]); + r_ddr_setval(ch, PI_DARRAY3_20_CS1_F2, dataL); + } + } + + /* set DRAMDCA value in MR30 */ + r_ddr_setval_ach(PI_SW_SEQ_0, 0x01A11E14U); + r_ddr_setval_ach(PI_SW_SEQ_1, 0x001F0000U); + r_ddr_setval_ach(PI_SEQ_DEC_SW_CS, rank); + r_ddr_setval_ach(PI_SW_SEQ_START, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = r_pi_int_ack_0_assert(19U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + r_ddr_setval_ach(PI_SEQ_DEC_SW_CS, 0x00U); + r_ddr_setval_ach(PI_DRAMDCA_FLIP_MASK, 0x02U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_ACTIVE_SEQ_2, 0x001101FCU); + r_ddr_setval_ach(PI_DRAMDCA_LVL_ACTIVE_SEQ_3, 0x00211A00U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_ACTIVE_SEQ_4, 0x00051500U); + + return phytrainingok; +} + +/** +* Re-run Write Leveling +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-09:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# CALVL training is set to OFF, WRDCM training is set to OFF, and DRAMDCA training is set to OFF.\n +* -# Set the memory rank for the Write leveling target and start leveling.\n +* -# Wait until leveling is complete.\n +* -# Check for Write leveling errors.\n +* -# If an error is confirmed to have occurred, the result is returned as a return value.\n +* -# Clear the PI status bit.\n +*/ +static uint32_t r_write_leveling(void) +{ + uint32_t ch; + uint32_t rank; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + uint32_t complete_ng; + uint32_t wr_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + r_ddr_setval_ach(PI_CALVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WRDCM_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WRLVL_CS_SW, rank); + r_ddr_setval_ach(PI_WRLVL_REQ, 0x01U); + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = ((r_ddr_getval(ch, PI_INT_STATUS)) >> 29); + if ((dataL & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + wr_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Wrlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3 )); /* PI_WRLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12 )); /* SLICE0 wrlvl error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12 )); /* SLICE1 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS); /* SLICE0 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS); /* SLICE1 wrlvl error */ + if (dataL != 0x0U) + { + wr_training_ng |= 1U << ch; + MSG_LF("write_leveling_error:1\n"); + } + } + + complete_ng = wr_training_ng; + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x07U); + } + + return phytrainingok; +} + +/** +* Manual Write DCA Training +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-xx:V4H-LPDDR5-DDR-HW-FD-xx +* @details Execute following processes.\n +* -# Execute following processes.\n +* -# Write DCA training according to memory rank.\n +*/ +static void r_manual_write_dca(void) +{ + uint32_t ch; + uint32_t slice; + uint32_t rank; + uint32_t cs; + uint32_t i; + uint32_t phy_slv_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; + uint32_t phy_slv_dly_avg[DRAM_CH_CNT][SLICE_CNT]; + uint32_t slv_dly_min[DRAM_CH_CNT][SLICE_CNT]; + uint32_t slv_dly_max[DRAM_CH_CNT][SLICE_CNT]; + uint32_t phy_dcc_code_min[DRAM_CH_CNT][SLICE_CNT]; + uint32_t phy_dcc_code_max[DRAM_CH_CNT][SLICE_CNT]; + uint32_t phy_dcc_code_mid; + uint32_t tmp; + uint32_t complete; + uint32_t retry; + const uint32_t RETRY_MAX = 0x10000U; + + const uint8_t ratio_min = 0x06U; + const uint8_t ratio_max = 0x03U; + const uint8_t ratio_min_div = 0x0AU; + const uint8_t ratio_max_div = 0x02U; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x02U; + } + else + { + rank = 0x01U; + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + phy_dcc_code_min[ch][slice] = 0x7FU; + phy_dcc_code_max[ch][slice] = 0x00U; + } + } + + for (cs = 0U; cs < rank; cs++) + { + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_INDEX, cs); + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + phy_slv_dly[ch][cs][slice] = r_ddr_getval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY); + } + } + }/* for (cs = 0U; cs < rank; cs++ */ + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if (rank == 0x02U) + { + /* Calculate average between ranks */ + phy_slv_dly_avg[ch][slice] = (phy_slv_dly[ch][0][slice] + phy_slv_dly[ch][1][slice]) / 2U; + } + else + { + phy_slv_dly_avg[ch][slice] = phy_slv_dly[ch][0][slice]; + } + /* Determine the search range */ + slv_dly_min[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07FU) * ratio_min / ratio_min_div; + slv_dly_max[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07FU) * ratio_max / ratio_max_div; + if (slv_dly_max[ch][slice] > 0x7FU) + { + slv_dly_max[ch][slice] = 0x7FU; + } + } + } + + complete = 0x00U; + + r_ddr_setval_ach_as(PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x01U); + + for (i = 0U; i <= 0x7FU; i++) + { + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if (slv_dly_max[ch][slice] < (slv_dly_min[ch][slice] + i)) + { + complete |= ((0x01U << ch) << (8U * slice)); + } + else + { + /* CS0/1 same setting, Need masked write */ + r_ddr_setval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY, (slv_dly_min[ch][slice] + i)); + r_ddr_setval_s(ch, slice, SC_PHY_WCK_CALC, 0x01U); + r_ddr_setval(ch, SC_PHY_MANUAL_UPDATE, 0x01U); + } + } + } + + if (complete == (ddr_phyvalid | (ddr_phyvalid << 8))) + { + break; + } + + /* Exec write dca */ + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if ((((complete >> (8U * slice)) >> ch) & 0x01U) != 0x01U) + { + r_ddr_setval_s(ch, slice, PHY_DATA_DC_CAL_START, 0x01U); + } + } + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if ((((complete >> (8U * slice)) >> ch) & 0x01U) != 0x01U) + { + retry = 0U; + while (retry++ < RETRY_MAX) + { + tmp = r_ddr_getval_s(ch, slice,PHY_DATA_DC_CAL_START); + if (tmp == 0x00U) + { + break; + } + } + } + } + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if ((slv_dly_min[ch][slice] + i) <= slv_dly_max[ch][slice]) + { + tmp = (r_ddr_getval_s(ch, slice, PHY_DATA_DC_DQS_CLK_ADJUST)); + if ((tmp >> 6) == 0x01U) + { + tmp = 0x00U; + } + else if ((tmp >> 6) == 0x02U) + { + tmp = 0x3FU; + } + else + { + ; /* nop */ + } + + if (tmp < phy_dcc_code_min[ch][slice]) + { + phy_dcc_code_min[ch][slice] = tmp; + } + + if (phy_dcc_code_max[ch][slice] < tmp) + { + phy_dcc_code_max[ch][slice] = tmp; + } + } + } + } + }/* for (i = 0U; i <= 0x7FU; i++) */ + + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U); + for (cs = 0U; cs < rank; cs++) + { + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_INDEX, cs); + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + r_ddr_setval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY, phy_slv_dly[ch][cs][slice]); + r_ddr_setval_s(ch, slice, SC_PHY_WCK_CALC, 0x01U); + r_ddr_setval(ch, SC_PHY_MANUAL_UPDATE, 0x01U); + } + } + } + + r_ddr_setval_ach_as(PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x00U); + + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01U); + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + phy_dcc_code_mid = (phy_dcc_code_min[ch][slice] + phy_dcc_code_max[ch][slice]) / 2U; + r_ddr_setval_s(ch, slice, PHY_DATA_DC_DQS_CLK_ADJUST, phy_dcc_code_mid); + } + } +} + +/** +* Re-run read gate training by pi +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-11:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Write leveling set to OFF, read gate leveling set to ON.\n +* -# Set memory rank for leveling target, turn on read gate leveling.\n +* -# Waiting for leveling to be completed until the time limit.\n +* -# Check for errors during gate leveling.\n +* -# If an error is confirmed to have occurred, the result is returned as a return value.\n +* -# Clear the PI status register.\n +*/ +static uint32_t r_read_gate_training(void) +{ + uint32_t ch; + uint32_t rank; + uint32_t dataL; + uint32_t phytrainingok; + uint32_t retry; + uint32_t complete_ng; + uint32_t gt_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + r_ddr_setval_ach(PI_WRLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x01U); + r_ddr_setval_ach(PI_RDLVL_CS_SW, rank); + r_ddr_setval_ach(PI_RDLVL_GATE_REQ, 0x01U); + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = ((r_ddr_getval(ch, PI_INT_STATUS)) >> 24); + if ((dataL & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + gt_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Gtlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 2 )); /* PI_RDLVL_GATE_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7 )); /* SLICE0 delay setup error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7 )); /* SLICE1 delay setup error */ + if (dataL != 0x0U) + { + gt_training_ng |= 1U << ch; + MSG_LF("read_gate_training_error\n"); + } + } + + complete_ng = gt_training_ng; + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x07U); + } + + return phytrainingok; +} + +/** +* Read Data Training with VREF Training +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-12:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Set reading leveling to ON and Vref leveling of reading to OFF.\n +* -# Set Vref reading training to OFF.\n +* -# Get start value, end value and number of steps for Vref training.\n +* -# Determine the optimal VREFSEL value while increasing the Vref training setpoint by the starting value+step value.\n +*/ +static uint32_t r_read_vref_training(void) +{ + uint32_t ch; + uint32_t phytrainingok = 0U; + uint32_t retry; + uint32_t dataL; + uint32_t rank; + uint32_t curr_rank; + uint32_t vref_start, vref_stop, vref_step; + uint32_t vref_stop_index; + uint32_t dvw_min_byte0[DRAM_CH_CNT], dvw_min_byte1[DRAM_CH_CNT]; + uint32_t obs_sel; + uint32_t win_byte0, win_byte1; + uint32_t best_vref_byte0, best_vref_byte1; + uint32_t best_vref_byte0_index = 0U; + uint32_t best_vref_byte1_index = 0U; + uint32_t best_dvw_min_byte0, best_dvw_min_byte1; + uint32_t best_thrshld; + uint32_t vref_outlier; + uint32_t best_lower_vref, best_upper_vref; + uint32_t outlier_cnt; + uint32_t tempLE, tempTE; + uint32_t dvw_min_byte0_table[DRAM_CH_CNT][128]; + uint32_t dvw_min_byte1_table[DRAM_CH_CNT][128]; + int32_t i; + + for (ch = 0U; ch < DRAM_CH_CNT; ch++) + { + dvw_min_byte0[ch] = 0x0U; + dvw_min_byte1[ch] = 0x0U; + } + + const uint32_t RETRY_MAX = 0x10000U; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x02U; + } + else + { + rank = 0x01U; + } + + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F0, 0x00U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F1, 0x00U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F2, 0x00U); + r_ddr_setval_ach_as(PHY_VREF_TRAINING_CTRL, 0x00U); + + /* ch0 vref_point */ + vref_start = r_ddr_getval(0U, PHY_VREF_INITIAL_START_POINT); + vref_stop = r_ddr_getval(0U, PHY_VREF_INITIAL_STOP_POINT); + vref_step = r_ddr_getval(0U, PHY_VREF_INITIAL_STEPSIZE); + vref_stop_index = (vref_stop - vref_start) / vref_step; + + if (vref_stop_index > 0x80U) + { + return phytrainingok; + } + + for (i = 0; i <= vref_stop_index; i++) + { + r_foreach_vch((ch)) + { + dataL = (r_ddr_getval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | (vref_start + (vref_step * i)))); + dataL = (r_ddr_getval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | (vref_start + (vref_step * i)))); + } + + for (curr_rank = 0U; curr_rank < rank; curr_rank++) + { + /* All ch Read Training Start */ + r_ddr_setval_ach(PI_RDLVL_CS_SW, (1U << curr_rank)); + r_ddr_setval_ach(PI_RDLVL_REQ, 0x01U); + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if (((dataL >> 25) & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + /* Read Training End */ + r_ddr_setval_ach(PI_INT_ACK_0, (0x1U << 25)); + + r_foreach_vch((ch)) + { + /* minimum Data Valie Window for each VREF */ + dvw_min_byte0[ch] = 0xFFFFFFFFU; + dvw_min_byte1[ch] = 0xFFFFFFFFU; + for (obs_sel = 0x00U; obs_sel < 0x19U; obs_sel++) + { + if ((obs_sel < 0x11U) || (obs_sel == 0x18U)) + { + r_ddr_setval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_OBS_SELECT, obs_sel); + r_ddr_setval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_OBS_SELECT, obs_sel); + + tempLE = r_ddr_getval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + tempTE = r_ddr_getval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + if (tempTE > tempLE) + { + win_byte0 = tempTE - tempLE; + } + else + { + win_byte0 = 0U; + } + tempLE = r_ddr_getval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + tempTE = r_ddr_getval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + if (tempTE > tempLE) + { + win_byte1 = tempTE - tempLE; + } + else + { + win_byte1 = 0U; + } + + if (dvw_min_byte0[ch] > win_byte0) + { + dvw_min_byte0[ch] = win_byte0; + } + if (dvw_min_byte1[ch] > win_byte1) + { + dvw_min_byte1[ch] = win_byte1; + } + } + } + } + }/* For all memory rank */ + r_foreach_vch((ch)) + { + dvw_min_byte0_table[ch][i] = dvw_min_byte0[ch]; + dvw_min_byte1_table[ch][i] = dvw_min_byte1[ch]; + } + }/* For all vref_stop_index steps */ + + r_foreach_vch((ch)) + { + /* Search best VREF byte0 */ + best_vref_byte0 = vref_start; + best_vref_byte0_index = 0U; + best_dvw_min_byte0 = dvw_min_byte0_table[ch][0U]; + for (i = 0U; i <= vref_stop_index; i++) + { + if (best_dvw_min_byte0 < dvw_min_byte0_table[ch][i]) + { + best_vref_byte0 = vref_start + (vref_step * i); + best_vref_byte0_index = i; + best_dvw_min_byte0 = dvw_min_byte0_table[ch][i]; + } + } + + /* Search best_lower VREF byte0 */ + dataL = r_ddr_getval_s(ch, 0U, PHY_RDLVL_DLY_STEP); + if (dataL == 0U) + { + best_thrshld = r_ddr_getval_s(ch, 0U, PHY_RDLVL_BEST_THRSHLD); + } + else + { + best_thrshld = r_ddr_getval_s(ch, 0U, PHY_RDLVL_BEST_THRSHLD) * dataL; + } + vref_outlier = r_ddr_getval_s(ch, 0U, PHY_RDLVL_VREF_OUTLIER); + best_lower_vref = best_vref_byte0; + outlier_cnt = vref_outlier; + for (i = best_vref_byte0_index; i >= 0; i--) + { + if (dvw_min_byte0_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) + { + best_lower_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + if (i == 0) + { + break; + } + } + + /* Search best_upper VREF byte0 */ + vref_outlier = r_ddr_getval_s(ch, 0U, PHY_RDLVL_VREF_OUTLIER); + best_upper_vref = best_vref_byte0; + outlier_cnt = vref_outlier; + for (i = best_vref_byte0_index; i <= vref_stop_index; i++) + { + if (dvw_min_byte0_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) + { + best_upper_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + } + + /* Calculate center of best vref range byte0 */ + best_vref_byte0 = (best_lower_vref + best_upper_vref) / 2U; + + /* Search best VREF byte1 */ + best_vref_byte1 = vref_start; + best_vref_byte1_index = 0U; + best_dvw_min_byte1 = dvw_min_byte1_table[ch][0U]; + for (i = 0U; i <= vref_stop_index; i++) + { + if (best_dvw_min_byte1 < dvw_min_byte1_table[ch][i]) + { + best_vref_byte1 = vref_start + (vref_step * i); + best_vref_byte1_index = i; + best_dvw_min_byte1 = dvw_min_byte1_table[ch][i]; + } + } + + /* Search best_lower VREF byte1 */ + dataL = r_ddr_getval_s(ch, 1U, PHY_RDLVL_DLY_STEP); + if (dataL == 0U) + { + best_thrshld = r_ddr_getval_s(ch, 1U, PHY_RDLVL_BEST_THRSHLD); + } + else + { + best_thrshld = r_ddr_getval_s(ch, 1U, PHY_RDLVL_BEST_THRSHLD) * dataL; + } + + vref_outlier = r_ddr_getval_s(ch, 1U, PHY_RDLVL_VREF_OUTLIER); + best_lower_vref = best_vref_byte1; + outlier_cnt = vref_outlier; + for (i = best_vref_byte1_index; i >= 0; i--) + { + if (dvw_min_byte1_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) + { + best_lower_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + if (i == 0) + { + break; + } + } + + /* Search best_upper VREF byte1 */ + vref_outlier = r_ddr_getval_s(ch, 1U, PHY_RDLVL_VREF_OUTLIER); + best_upper_vref = best_vref_byte1; + outlier_cnt = vref_outlier; + for (i = best_vref_byte1_index; i <= vref_stop_index; i++) + { + if (dvw_min_byte1_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) + { + best_upper_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + } + + /* Calculate center of best vref range byte1 */ + best_vref_byte1 = (best_lower_vref + best_upper_vref) / 2U; + + dataL = (r_ddr_getval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | best_vref_byte0)); + dataL = (r_ddr_getval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | best_vref_byte1)); + } + + return phytrainingok; +} + +/** +* Read Data & RDDQ Training with best VREF & Write DQ VREF Training +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-13:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Set read DQS/RDQS slave delay setting to 0.\n +* -# Write leveling set to OFF, read gate leveling set to OFF.\n +* -# Turn on read and write leveling.\n +* -# Start frequency training.\n +* -# Training in high-frequency mode.\n +* -# Wait until training is complete.\n +* -# Check for errors in write dq leveling and read leveling.\n +* -# If an error is confirmed to have occurred, return the inverted result value.\n +* -# Clear the PI status register.\n +*/ +static uint32_t r_read_write_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + uint32_t complete_ng; + uint32_t rd_training_ng; + uint32_t wdq_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + /* RDDQ_SLAVE_DELAY Set 0x0050 -> 0x0000 */ + r_ddr_setval_ach_as(PHY_RDDQ0_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ1_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ2_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ3_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ4_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ5_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ6_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ7_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDM_SLAVE_DELAY, 0x0000U); + + r_ddr_setval_ach(PI_WRLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_WDQLVL_EN_F2, 0x03U); + + r_ddr_setval_ach(PI_TRAIN_ALL_FREQ_REQ, 0x01U); + + /* Freq Change High to High*/ + dataL = r_pll3_freq(); + if (dataL != 0x0U) + { + return (1); + } + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if ((dataL & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + rd_training_ng = 0x0U; + wdq_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Rdlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 1 )); /* PI_RDLVL_ERROR_BIT */ + if (dataL != 0x0U) + { + rd_training_ng |= 1U << ch; + MSG_LF("read_write_training_error:1\n"); + } + + /* Wdqlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 5 )); /* PI_WDQLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18 )); /* SLICE0 wdqlvl_fail_dqZ */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18 )); /* SLICE1 wdqlvl_fail_dqZ */ + if (dataL != 0x0U) + { + wdq_training_ng |= 1U << ch; + MSG_LF("read_write_training_error:2\n"); + } + } + + complete_ng = (wdq_training_ng | rd_training_ng); + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x07U); + } + + return phytrainingok; +} + +/** +* Correct RDDQ Training result & Re-Run Read Data Training +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-15:V4H-LPDDR5-DDR-HW-FD-10-03 +* @details Execute following processes.\n +* -# Set the Read DQ correction value and its upper limit from the board settings\n +* -# Check DDR memory ranks.\n +* -# Add the offset value to the current Read DQ value and write it to the register.\n +* -# Write the setting value to PI_RDLVL_TRAIN_SEQ_x.\n +* -# Start the Read training.\n +* -# PI_INT_ACK assert.\n +* -# Execute the Rdlvl Err Check.\n +* -# Confirmation that training has been successfully completed.\n +* -# Return the result of the confirmation as the return value.\n +*/ +static uint32_t r_read_training(void) +{ + uint32_t ch; + uint32_t slice; + uint32_t rank; + uint32_t i; + uint32_t phytrainingok; + uint32_t dataL; + uint32_t complete_ng; + uint32_t rd_training_ng; + uint32_t rddq_delay_offset; + uint32_t rddq_delay_max; + + const uint32_t rddq_delay_addr[9] = + { + PHY_RDDQ0_SLAVE_DELAY, PHY_RDDQ1_SLAVE_DELAY, PHY_RDDQ2_SLAVE_DELAY, + PHY_RDDQ3_SLAVE_DELAY, PHY_RDDQ4_SLAVE_DELAY, PHY_RDDQ5_SLAVE_DELAY, + PHY_RDDQ6_SLAVE_DELAY, PHY_RDDQ7_SLAVE_DELAY, PHY_RDDM_SLAVE_DELAY + }; + + const uint32_t rddq_delay_offset_ps = 0x19U; + const uint32_t rddq_delay_max_ps = 0x67U; + + rddq_delay_offset = rddq_delay_offset_ps * ddr_mbps * 256U / (ddr_mbpsdiv * 2U * 1000000U); + rddq_delay_max = rddq_delay_max_ps * ddr_mbps * 256U / (ddr_mbpsdiv * 2U * 1000000U); + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + for (i = 0U; i < 9U; i++) + { + dataL = r_ddr_getval_s(ch, slice, rddq_delay_addr[i]) + rddq_delay_offset; + if (dataL > rddq_delay_max) + { + dataL = rddq_delay_max; + } + r_ddr_setval_s(ch, slice, rddq_delay_addr[i], dataL); + } + } + } + + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_1, 0x00089080U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_2, 0x000811C0U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_3, 0x040811C0U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_4, 0x02000000U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_5, 0x00000000U); + r_ddr_setval_ach(PI_RDLVL_CS_SW, rank); + + /* Read training go */ + r_ddr_setval_ach(PI_RDLVL_REQ, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = 0x0U; + phytrainingok = r_pi_int_ack_0_assert(25U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + complete_ng = 0x0U; + rd_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Rdlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 1)); /* PI_RDLVL_ERROR_BIT */ + if (dataL != 0x0U) + { + rd_training_ng |= 1U << ch; + MSG_LF("read_training_error\n"); + } + } + + complete_ng = rd_training_ng; + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + return phytrainingok; +} + +/** +* DDR mode register setting +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-06:V4H-LPDDR5-DDR-HW-FD-10-05 +* @details Execute following processes.\n +* -# Set the mode register 28 of the SDRAM.\n +*/ +static void r_ddr_register_set(void) +{ + /* MR28 ZQ Mode: Command-Based ZQ Calibration, ZQ interval: Background Cal Interval < 64ms */ + r_send_dbcmd2(0x0E841C24U); +} + +/** +* DDR mode register read +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-14:V4H-LPDDR5-DDR-HW-FD-02-05 +* @details Execute following processes.\n +* -# Execute following processes.\n +* -# Set the mode register 27 and 57 of the SDRAM.\n +*/ +static void r_ddr_register_read(void) +{ + uint32_t dataL; + + dataL = (uint32_t)(Boardcnf->bdcfg_rfm_chk); + if (dataL != 0x0U) + { + /* MR27 rank0 */ + r_send_dbcmd2(0x0F801B00U); + /* MR57 rank0 */ + r_send_dbcmd2(0x0F803900U); + + if (ch_have_this_cs[1] != 0x0U) + { + /* MR27 rank1 */ + r_send_dbcmd2(0x0F811B00U); + /* MR57 rank1 */ + r_send_dbcmd2(0x0F813900U); + } + } +} + +/** +* Training handshake functions +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-08:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Wait for the status bit specified in the argument to become 1 until the time limit.\n +* -# After checking status bits on all channels, clear the target status bits\n +and returns the result of the check as the return value. +*/ +static uint32_t r_pi_int_ack_0_assert(uint32_t bit) +{ + uint32_t dataL; + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + const uint32_t RETRY_MAX = 0x10000U; + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if (((dataL >> bit) & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, (0x1U << bit)); + } + return phytrainingok; +} + +/** +* Wait for status register update +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-xx:V4H-LPDDR5-DDR-HW-FD-xx +* @details Execute following processes.\n +* -# Read value the DBSC_DBPDSTAT1(ch) register\n +* -# Wait until the contents of the status register are the same as status\n +*/ +static void r_wait_dbpdstat1(uint32_t status) +{ + uint32_t i, ch, dataL; + uint32_t freqchg_req_chk; + + for (i = 0U; i < 2U; i++) + { + do + { + dataL = status; + freqchg_req_chk = 0U; + r_foreach_vch((ch)) + { + dataL &= mmio_read_32(DBSC_DBPDSTAT1(ch)); + freqchg_req_chk |= mmio_read_32(DBSC_DBPDSTAT0(ch)); + } + } while ((dataL != status) && ((freqchg_req_chk & 0x1U) == 0x0U)); + } +} + +/** +* Training handshake functions +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-14:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t Check to see if time is running out +* @details Execute following processes.\n +* -# Check the value of the argument req_assert.\n +* -# If req_assert is 1, wait until FREQCHGREQ of all channels is 1 before time expires.\n +* -# If req_assert is 0, wait until FREQCHGREQ of all channels is 0 before time expires.\n +* -# Returns the result of whether time has expired or not as a return value.\n +*/ +static uint32_t r_wait_freqchgreq(uint32_t req_assert) +{ + uint32_t dataL; + uint32_t count; + uint32_t ch; + + count = 0xFFFFFFU; + + if (req_assert != 0x0U) + { + do + { + dataL = 1U; + r_foreach_vch((ch)) + { + dataL &= mmio_read_32(DBSC_DBPDSTAT0(ch)); + } + count = count - 1U; + } + while (((dataL & 0x1U) != 0x1U) && (count != 0U)); + } + else + { + do + { + dataL = 0U; + r_foreach_vch((ch)) + { + dataL |= mmio_read_32(DBSC_DBPDSTAT0(ch)); + } + count = count - 1U; + } + while (((dataL & 0x1U) != 0x0U) && (count != 0U)); + }/* (req_assert != 0x0U) */ + + return (count == 0x0U); +} + +/** +* Training handshake functions +* @par TraceID Cover_SW_UD:Cover_HW_DD +* :V4H-LPDDR5-DDR-SW-UD-07-04:V4H-LPDDR5-DDR-HW-FD-10-03 +* @details Execute following processes.\n +* -# Check the value of the argument ackassert..\n +* -# If the value of ackassert is greater than or equal to 0, write 0x0000CF01U to DBSC_DBPDCNT2.\n +* -# If the value of ackassert is 0, write 0x00000000U to DBSC_DBPDCNT2.\n +*/ +static void r_set_freqchgack(uint32_t ack_assert) +{ + uint32_t ch; + uint32_t dataL; + + if (ack_assert != 0x0U) + { + dataL = 0x0000CF01U; + } + else + { + dataL = 0x00000000U; + } + + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDCNT2(ch), dataL); + } +} + +/** +* Set up the pll3 frequency +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-xx:V4H-LPDDR5-DDR-HW-FD-xx +* @details Execute following processes.\n +* -# Wait for frequency change request.\n +* -# DBSC_DBPDSTAT0 value determines whether r_pll3_control is called\n +* in low frequency mode or high frequency mode.\n +* -# Call r_set_freqchgack(1U) function.\n +* -# Check update completion until timeout.\n +* -# Call r_set_freqchgack(0U) function.\n +* -# If timed out, return with error log\n +* -# Wait for status register update\n +*/ +static uint32_t r_pll3_freq(void) +{ + uint32_t timeout; + uint32_t fsel; + + r_wait_freqchgreq(1); + + fsel = (0x0300U & mmio_read_32(DBSC_DBPDSTAT0(0U))) >> 8; + if (fsel == 0U) + { + r_pll3_control(PLL3_LOW_FREQUENCY_MODE); /* Low frequency mode */ + } + else + { + r_pll3_control(PLL3_HIGH_FREQUENCY_MODE); /* High frequency mode */ + } + + r_set_freqchgack(1U); + + timeout = r_wait_freqchgreq(0); + r_set_freqchgack(0U); + + if (timeout != 0x0U) + { + FATAL_MSG("Time out\n"); + return (1); + } + + r_wait_dbpdstat1(0x07U); + + return (0); +} + +/** +* Initialize ddr +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-02:V4H-LPDDR5-DDR-HW-DD-10-02-02 +* @details Execute following processes.\n +* -# Status monitor and perform reset and software reset for DDR.\n +* -# Disable DDRPHY software reset.\n +* -# Unprotect the DDRPHY register.\n +* -# Perform pre-setting of DBSC registers.\n +* -# Configure the ddrphy registers.\n +* -# Process ddr backup.\n +* -# Set DBSC registers.\n +* -# Initialize DFI and perform PI training.\n +* -# Setup DDR mode registers pre-traning.\n +* -# Adjustment of number of write leveling cycles.\n +* -# Perform PI training in manual mode.\n +* -# Perform DRAM DCA training.\n +* -# Perform write leveling.\n +* -# Exec phydca training.\n +* -# Execute read gate training.\n +* -# Perform Vref training on read gate.\n +* -# Read DQ Write DQ Execute.\n +* -# frequency selection change (F1->F2).\n +* -# Disable the FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST.\n +* -# Start setting DDR mode registers.\n +* -# Set DBSC registers after training is completed.\n +* -# Set write protection for PHY registers.\n +*/ +static uint32_t r_init_ddr(void) +{ + uint32_t phytrainingok; + uint32_t ch; + uint32_t err; + + MSG_LF("init_ddr:0\n"); +#ifdef DDR_BACKUPMODE + R_DRAM_Get_Boot_Status(&ddrBackup); +#endif + + /*********************************************************************** + * PLL3 initialization setting + ***********************************************************************/ + /* Reset Status Monitor clear */ + r_cpg_write_32(CPG_FSRCHKCLRR4, 0x00000600U); + /* Reset Status Monitor set */ + r_cpg_write_32(CPG_FSRCHKSETR4, 0x00000600U); + /* ddrphy soft reset assert */ + r_cpg_write_32(CPG_SRCR4, mmio_read_32(CPG_SRCR4) | 0x00000600U); + /* wait reset FB */ + while ((mmio_read_32(CPG_FSRCHKRA4) & 0x00000600U) != 0U) + { + ; /* Nothing */ + } + /* Reset Status Monitor clear */ + r_cpg_write_32(CPG_FSRCHKCLRR4, 0x00000600U); + +#if (RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE == 1U) + r_pll3_control(PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER); /* Initialize PLL3 setting */ +#else + r_pll3_control(PLL3_HIGH_FREQUENCY_MODE); /* Initialize PLL3 setting */ +#endif /* (RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE == 1U) */ + + /* ddrphy soft reset negate */ + r_cpg_write_32(CPG_SRSTCLR4, 0x00000600U); + while ((mmio_read_32(CPG_SRCR4) & 0x00000600U) != 0U) + { + ; /* Nothing */ + } + + /*********************************************************************** + * unlock phy + ***********************************************************************/ + /* Unlock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU); + } + + /*********************************************************************** + * dbsc register pre-setting + ***********************************************************************/ + r_dbsc_regset_pre(); + + /*********************************************************************** + * load ddrphy registers + ***********************************************************************/ + r_ddrtbl_load(); + + /*********************************************************************** + * configure ddrphy registers + ***********************************************************************/ + r_ddr_config(); + + /*********************************************************************** + * ddr backupmode end + ***********************************************************************/ +#ifdef DDR_BACKUPMODE + if (ddrBackup != 0x0U) + { + NOTICE("[WARM_BOOT]\n"); + } + else + { + NOTICE("[COLD_BOOT]\n"); + } + + err = R_DRAM_Update_Boot_Status(ddrBackup); + if (err != 0x0U) + { + NOTICE("[BOOT_STATUS_UPDATE_ERROR]\n"); + return INITDRAM_ERR_I; + } +#endif + MSG_LF("init_ddr:1\n"); + + /*********************************************************************** + * dbsc register set + ***********************************************************************/ + r_dbsc_regset(); + MSG_LF("init_ddr:2\n"); + + /*********************************************************************** + * frequency selection change (F1->F2) + ***********************************************************************/ + r_ddr_setval_ach(PHY_FREQ_SEL_INDEX, 0x01U); + r_ddr_setval_ach(PHY_FREQ_SEL_MULTICAST_EN, 0x00U); + + /*********************************************************************** + * dfi_init_start (start ddrphy) & exec pi_training + ***********************************************************************/ + phytrainingok = r_pi_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:1\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:3\n"); + + /*********************************************************************** + * write leveling cycle adjust + ***********************************************************************/ + r_write_leveling_adjust(); + MSG_LF("init_ddr:4\n"); + + /*********************************************************************** + * exec write leveling & read gate training + ***********************************************************************/ + phytrainingok = r_wl_gt_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:2\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:5\n"); + + /*********************************************************************** + * exec write dca training + ***********************************************************************/ + r_write_dca(); + + MSG_LF("init_ddr:6\n"); + + /*********************************************************************** + * exec dram dca training + ***********************************************************************/ + phytrainingok = r_dramdca_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:3\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:7\n"); + + /*********************************************************************** + * exec write leveling + ***********************************************************************/ + phytrainingok = r_write_leveling(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:4\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:8\n"); + + /*********************************************************************** + * exec manual write dca training + ***********************************************************************/ + r_manual_write_dca(); + + MSG_LF("init_ddr:9\n"); + + /*********************************************************************** + * exec read gate training + ***********************************************************************/ + phytrainingok = r_read_gate_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:5\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:10\n"); + + /*********************************************************************** + * exec read vref training + ***********************************************************************/ + phytrainingok = r_read_vref_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:6\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:11\n"); + + /*********************************************************************** + * exec read dq & write dq training with best vref + ***********************************************************************/ + phytrainingok = r_read_write_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:7\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:12\n"); + + /*********************************************************************** + * correct rddq training result & exec read dq training + ***********************************************************************/ + phytrainingok = r_read_training(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:8\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:13\n"); + + /*********************************************************************** + * PER_CS_TRAINING_MULTICAST SET (disable) + ***********************************************************************/ + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U); + + MSG_LF("init_ddr:14\n"); + + /*********************************************************************** + * setup DDR mode registers + ***********************************************************************/ + /* MRS */ + r_ddr_register_set(); + + /* MRR */ + r_ddr_register_read(); + + MSG_LF("init_ddr:15\n"); + + /*********************************************************************** + * training complete, setup dbsc + ***********************************************************************/ + r_dbsc_regset_post(); + + MSG_LF("init_ddr:16\n"); + + /*********************************************************************** + * lock phy + ***********************************************************************/ + /* Lock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U); + } + + return phytrainingok; +} + +/** +* DDR Initialize entry +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-01:V4H-LPDDR5-DDR-HW-FD-01-01 +* V4H-LPDDR5-DDR-SW-UD-01:V4H-LPDDR5-DDR-HW-DD-01-04-01 +* V4H-LPDDR5-DDR-SW-UD-01:V4H-LPDDR5-DDR-HW-DD-01-04-02 +* V4H-LPDDR5-DDR-SW-UD-01:V4H-LPDDR5-DDR-HW-DD-01-04-03 +* V4H-LPDDR5-DDR-SW-UD-01:V4H-LPDDR5-DDR-HW-DD-01-03-02 +* V4H-LPDDR5-DDR-SW-UD-01:V4H-LPDDR5-DDR-HW-DD-10-01-01 +* V4H-LPDDR5-DDR-SW-UD-01:V4H-LPDDR5-DDR-HW-DD-10-04-01 +* @details Execute following processes.\n +* -# Remove write protection on DBSC register.\n +* -# Reads the ID and version of the SoC used.\n +* -# Read DDR configuration information from a config file.\n +* -# Calculate board clock frequency and operating frequency from DDR configuration information.\n +* -# Call the main function of DDR initialization.\n +* -# Perform DBSC write protection after initialization is complete.\n +*/ +uint32_t R_DRAM_Init(void) +{ + uint32_t ch, cs; + uint32_t dataL; + uint32_t failcount; + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00001234U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00001234U); + + /*********************************************************************** + * Judge product and cut + ***********************************************************************/ + Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; + + if (Prr_Product != PRR_PRODUCT_V4H) + { + FATAL_MSG("DDR:Unknown Product\n"); + return 0xFFU; + } + else if (Prr_Cut > 0xFFU) + { + FATAL_MSG("DDR:Unknown Product Version\n"); + return 0xFFU; + } + else + { + ; /* Nothing */ + } + + /*********************************************************************** + * Judge board type + ***********************************************************************/ + BOARDTYPE = r_boardcnf_get_brd_type(); + if (BOARDTYPE >= BOARDNUM) + { + FATAL_MSG("DDR:Unknown Board\n"); + return 0xFFU; + } + + Boardcnf = (const st_boardcnf_t *)&boardcnfs[BOARDTYPE]; + + ddr_phyvalid = (uint32_t)(Boardcnf->bdcfg_phyvalid); + + max_density = 0U; + + for (cs = 0U; cs < CS_CNT; cs++) + { + ch_have_this_cs[cs] = 0U; + } + + r_foreach_ech((ch)) + { + for (cs = 0U; cs < CS_CNT; cs++) + { + ddr_density[ch][cs] = 0xFFU; + } + } + + r_foreach_vch((ch)) + { + for (cs = 0U; cs < CS_CNT; cs++) + { + dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_ddr_density[cs]); + ddr_density[ch][cs] = dataL; + if (dataL == 0xFFU) + { + continue; + } + if (dataL > max_density) + { + max_density = dataL; + } + ch_have_this_cs[cs] |= (1U << ch); + } + } + + /*********************************************************************** + * Judge board clock frequency (in MHz) + ***********************************************************************/ + r_boardcnf_get_brd_clk(BOARDTYPE, &brd_clk, &brd_clkdiv); + if (((0x01U << 14) & mmio_read_32(RST_MODEMR0)) != 0x0U) + { + brd_clkdiva = 1U; + } + else + { + brd_clkdiva = 0U; + } + + /*********************************************************************** + * Judge ddr operating frequency clock(in Mbps) + ***********************************************************************/ + r_boardcnf_get_ddr_mbps(BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv, &sscg); + + ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U)); + ddr_mul_low = CLK_DIV(6400U, 1U * 2U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U)); + + if (sscg != 0x0U) + { + ddr_mul_reg = ddr_mul_low - 2U; + } + else + { + ddr_mul_reg = ddr_mul_low; + } + +#if RCAR_PLL3_FRAC_MODE == 1U + ddr_mul_nf = ((8U * ddr_mbps * brd_clkdiv * (brd_clkdiva + 1U)) / (ddr_mbpsdiv * brd_clk * 2U)) - (8U * (ddr_mul / 2U) * 2U); +#else + ddr_mul_nf = 0x00U; +#endif + + dataL = 0x03U & (mmio_read_32(RST_MODEMR0) >> 13); + bus_clk = 0U; + bus_clkdiv = 0U; + + switch (dataL) + { + case 0U: + bus_clk = brd_clk * 0x18U; + bus_clkdiv = brd_clkdiv; + break; + case 1U: + bus_clk = brd_clk * 0x14U; + bus_clkdiv = brd_clkdiv; + break; + case 2U: + /* Not supported */ + bus_clk = brd_clk * 0x20U; + bus_clkdiv = brd_clkdiv * 2U; + break; + case 3U: + bus_clk = brd_clk * 0x18U; + bus_clkdiv = brd_clkdiv * 2U; + break; + default: + bus_clk = brd_clk * 0x18U; + bus_clkdiv = brd_clkdiv * 2U; + break; + } + + /*********************************************************************** + * Adjust tccd + ***********************************************************************/ + ddr_tccd = 2U; + + NOTICE("DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); + + MSG_LF("Start\n"); + + /*********************************************************************** + * initialize DDR + ***********************************************************************/ + dataL = r_init_ddr(); + if (dataL == ddr_phyvalid) + { + failcount = 0U; + } + else + { + failcount = 1U; + } + + NOTICE("..%d\n", failcount); + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00000000U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00000000U); + + if (failcount == 0U) + { + return INITDRAM_OK; + } + else + { + return INITDRAM_NG; + } +} + +#if (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) +/** +* DDR Initialize entry +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-16:V4H-LPDDR5-DDR-HW-FD-10-03 +* @details Set PI READ Leveling interval.\n +* -# First, unlock DDRPHY register.\n +* -# Clear PI_INT_STATUS register.\n +* -# Wait for wdq training to be done.\n +* -# Set PI read leveling interval.\n +* -# Last, lock DDRPHY register.\n +*/ +void r_set_pi_rdlvl_interval(void) +{ + uint32_t ch; + uint32_t dataL; + uint32_t ctrl_clk; + uint32_t clk_count; + uint32_t phymster_req_interval; + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00001234U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00001234U); + + /* Unlock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU); + } + + /* PI_INT_STATUS clear */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x07U); + } + + /* wait wdq training done */ + (void)r_pi_int_ack_0_assert(31U); + + /* set pi_rdlvl_interval */ + phymster_req_interval = PERIODIC_TRAINING_INTERVAL - 3000U; + clk_count = 1024U - (r_ddrtbl_getval_pi(DDR_PI_REGSET, PI_LONG_COUNT_MASK) * 32U); + ctrl_clk = ddr_mbps / ddr_mbpsdiv / 8U; + dataL = phymster_req_interval * ctrl_clk / clk_count; + r_ddr_setval_ach(PI_RDLVL_INTERVAL, dataL); + + /* Lock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U); + } + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00000000U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00000000U); + +} +#endif /* (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) */ + +/******************************************************************************* + * END + ******************************************************************************/ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.c new file mode 100644 index 0000000..b6571b8 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.c @@ -0,0 +1,194 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#else +#include "mem_io.h" +#include "log.h" +#endif +#include "boot_init_dram_config.h" +#include "boot_init_dram_regdef.h" + +/******************************************************************************* + * PLEASE SET board number or board judge function + ******************************************************************************/ +// #define BOARD_JUDGE_AUTO +#ifdef BOARD_JUDGE_AUTO +static uint32_t r_board_judge(void); +uint32_t r_boardcnf_get_brd_type(void) +{ + return r_board_judge(); +} +#else /* BOARD_JUDGE_AUTO */ +uint32_t r_boardcnf_get_brd_type(void) +{ + return (2); +} +#endif /* BOARD_JUDGE_AUTO */ + +/** +* RENESAS WHITE HAWK BOARD EXAMPLE +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-01-02:V4H-LPDDR5-DDR-HW-DD-01-04-01 +* @param[in] brd Argument for dummy read +* @param[in] clk The pointer which indicate the clock frequency +* @param[in] div The pointer which indicate the clock frequency division +* @details judged by md14/md13\n +* 16.66MHz CLK,DIV= 50,3 (md14,md13==0,0) +* 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1) +* 33.33MHz CLK,DIV=100,3 (md14,md13==1,1) +*/ +void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div) +{ + uint32_t md; + + md = (mmio_read_32(RST_MODEMR0) >> 13) & 0x3U; + switch (md) + { + case 0x0U : *clk = 50U; *clk_div = 3U; break; /* 50 / 3 = 16.66MHz */ + case 0x1U : *clk = 60U; *clk_div = 3U; break; /* 60 / 3 = 20.00MHz */ + case 0x2U : NOTICE("MD14/MD13 is invalid!!\n"); panic; /* Not supported */ + case 0x3U : *clk = 100U; *clk_div = 3U; break; /* 100 / 3 = 33.33MHz */ + default : /* nop */ break; + } + (void)brd; +} + +/******************************************************************************* + * DDR MBPS TARGET + * PLEASE DEFINE HOW TO JUDGE DDR BPS + ******************************************************************************/ +/** +* DDRxxxx (judge by md19, md17) : Mbps +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-01-03:V4H-LPDDR5-DDR-HW-DD-01-04-02 +* @param[in] brd Argument for dummy read +* @param[in] mbps The pointer which indicate the ddr frequency +* @param[in] div The pointer which indicate the ddr frequency division +* @details SSCG enable / disable for PLL1 (judge by md37/md36) +* According to Bit[17] of RST_MODEMR0 and Bit[5:4] of RST_MODEMR1, +* determine the value of ddr mbps and mbps division. +*/ +void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg) +{ + uint32_t md; + uint32_t product; + + md = (mmio_read_32(RST_MODEMR0) >> 17) & 0x05U; + md = (md | (md >> 1)) & 0x03U; + *sscg = (mmio_read_32(RST_MODEMR1) >> 4) & 0x03U; + product = mmio_read_32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK; + + if (product == 0x01U) + { + /* V4H-5 */ + switch (md) + { + case 0x0U : *mbps = 5000U; *mbps_div = 1U; break; /* 5000Mbps */ + case 0x1U : *mbps = 5000U; *mbps_div = 1U; break; /* 5000Mbps */ + case 0x2U : *mbps = 5000U; *mbps_div = 1U; break; /* 5000Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + } + else if (product == 0x02U) + { + /* V4H-3 */ + switch (md) + { + case 0x0U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + case 0x1U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + case 0x2U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + } + else + { + /* V4H-7 */ + switch (*sscg) + { + case 0x0U : + switch (md) + { + case 0x0U : *mbps = 6400U; *mbps_div = 1U; break; /* 6400Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + default : /* nop */ break; + } + break; + case 0x1U : + switch (md) + { + case 0x0U : *mbps = 19000U; *mbps_div = 3U; break; /* 6333Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + default : /* nop */ break; + } + break; + case 0x2U : /* Not supported */ + NOTICE("This MD37/MD36 value is invalid!!\n");panic; + case 0x3U : + switch (md) + { + case 0x0U : *mbps = 19000U; *mbps_div = 3U; break; /* 6333Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + default : /* nop */ break; + } + break; + default : + /* nop */ + break; + } + } + (void)brd; +} + +#ifdef BOARD_JUDGE_AUTO +/******************************************************************************* + * SAMPLE board detect function + ******************************************************************************/ +/** +* Select the setting parameters about the Spieder board you use. +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-10:V4H-LPDDR5-DDR-HW-DD-01-03-02 +* @return uint32_t Selected table index, this is sample value 0. +* @details Pass the return value from the r_board_judge function. +* In case that "BOARD_JUDGE_AUTO" is not defined, Another process will be called.\n\n +*/ +static uint32_t r_board_judge(void) +{ + uint32_t brd; + + brd = 0U; /* white hawk (64Gbit 1rank)*/ + + return brd; +} +#endif diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.h b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.h new file mode 100644 index 0000000..d4467ce --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.h @@ -0,0 +1,282 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#ifndef BOOT_INIT_DRAM_CONFIG +#define BOOT_INIT_DRAM_CONFIG + +#include "boot_init_dram_regdef.h" + +//! @details DRAM Param setting +#define JS2_DERATE 0U +//! @details Average periodic refresh interval/Average Refresh Interval [ns] +#define DBSC_REFINT 1920U +#ifndef DBSC_REFINTS +//! 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. +#define DBSC_REFINTS 0U +#endif +//! @details Periodic-WriteDQ/ReadDQ Training Interval [us] +#define PERIODIC_TRAINING_INTERVAL 20000U + +/******************************************************************************* + * NUMBER OF BOARD CONFIGRATION + * PLEASE DEFINE + ******************************************************************************/ +//! @details Add User platform BOARD +#define BOARDNUM 3U + +/******************************************************************************* + * BOARD CONFIGRATION + * PLEASE DEFINE boardcnfs[] + ******************************************************************************/ +uint32_t r_boardcnf_get_brd_type(void); +void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div); +void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg); + +/******************************************************************************* + * BOARD CONFIGRATION + * PLEASE DEFINE boardcnfs[] + ******************************************************************************/ +typedef struct{ + /* + 0x00...0000B: 4Gb dual channel die / 2Gb single channel die + 0x01...0001B: 6Gb dual channel die / 3Gb single channel die + 0x02...0010B: 8Gb dual channel die / 4Gb single channel die + 0x03...0011B: 12Gb dual channel die / 6Gb single channel die + 0x04...0100B: 16Gb dual channel die / 8Gb single channel die + 0x05...0101B: 24Gb dual channel die / 12Gb single channel die + 0x06...0110B: 32Gb dual channel die / 16Gb single channel die + 0x07...0111B: 24Gb single channel die + 0x08...1000B: 32Gb single channel die + 0xFF...NO_MEMORY + */ + uint8_t bdcfg_ddr_density[CS_CNT]; + /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */ + uint32_t bdcfg_ca_swap; + /* SoC dqsX([1][0]) -> MEM dqsY: */ + uint8_t bdcfg_dqs_swap; + /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ + uint32_t bdcfg_dq_swap[SLICE_CNT]; + /* SoC dm -> MEM dqY/dm: (8 means DM) */ + uint8_t bdcfg_dm_swap[SLICE_CNT]; + /* SoC ckeX([1][0]) -> MEM csY */ + uint8_t bdcfg_cs_swap; +}st_boardcnf_ch_t; + +typedef struct { + + /* ch in use */ + uint8_t bdcfg_phyvalid; + /* Read vref (SoC) training range : [23:16]step / [15:8]stop / [7:0]start, 0x00000000 = default val */ + uint32_t bdcfg_vref_r; + /* Write vref (MR14, MR15) training range : [15:8]stop / [7:0]start, 0x0000 = default val */ + uint16_t bdcfg_vref_w; + /* CA vref (MR12) training range : [15:8]stop / [7:0]start, 0x0000 = default val */ + uint16_t bdcfg_vref_ca; + /* RFM required check : 0x01 = check enable, 0x00 = check disable */ + uint8_t bdcfg_rfm_chk; + //! @details Board parameter about channels + st_boardcnf_ch_t ch[4]; +}st_boardcnf_t; + +static const st_boardcnf_t boardcnfs[BOARDNUM] = { +/* + * boardcnf[0] RENESAS V4H White Hawk (64Gbit 1rank) + */ +{ + 0x0FU, /* bdcfg_phyvalid */ + 0x00000000U, /* bdcfg_vref_r */ + 0x0000U, /* bdcfg_vref_w */ + 0x0000U, /* bdcfg_vref_ca */ + 0x01U, /* bdcfg_rfm_chk */ + { +/* ch[0] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x04506132U, +/* bdcfg_dqs_swap */ 0x01U, +/* bdcfg_dq_swap[] */ { 0x26147085U, 0x12306845U }, +/* bdcfg_dm_swap[] */ { 0x03U, 0x07U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[1] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x02341065U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x56782314U, 0x71048365U }, +/* bdcfg_dm_swap[] */ { 0x00U, 0x02U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[2] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x02150643U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x58264071U, 0x41207536U }, +/* bdcfg_dm_swap[] */ { 0x03U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[3] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x01546230U, +/* bdcfg_dqs_swap */ 0x01U, +/* bdcfg_dq_swap[] */ { 0x45761328U, 0x62801745U }, +/* bdcfg_dm_swap[] */ { 0x00U, 0x03U }, +/* bdcfg_cs_swap */ 0x10U + } + } +}, +#if 0 // added from v3.33.3, not used + /* + * boardcnf[1] RENESAS V4H White Hawk (64Gbit 2rank) + */ +{ + 0x0FU, /* bdcfg_phyvalid */ + 0x00000000U, /* bdcfg_vref_r */ + 0x0000U, /* bdcfg_vref_w */ + 0x0000U, /* bdcfg_vref_ca */ + 0x01U, /* bdcfg_rfm_chk */ + { +/* ch[0] */ { +/* bdcfg_ddr_density[] */ { 0x04U, 0x04U }, +/* bdcfg_ca_swap */ 0x04506132U, +/* bdcfg_dqs_swap */ 0x01U, +/* bdcfg_dq_swap[] */ { 0x26147085U, 0x12306845U }, +/* bdcfg_dm_swap[] */ { 0x03U, 0x07U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[1] */ { +/* bdcfg_ddr_density[] */ { 0x04U, 0x04U }, +/* bdcfg_ca_swap */ 0x02341065U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x56782314U, 0x71048365U }, +/* bdcfg_dm_swap[] */ { 0x00U, 0x02U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[2] */ { +/* bdcfg_ddr_density[] */ { 0x04U, 0x04U }, +/* bdcfg_ca_swap */ 0x02150643U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x58264071U, 0x41207536U }, +/* bdcfg_dm_swap[] */ { 0x03U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[3] */ { +/* bdcfg_ddr_density[] */ { 0x04U, 0x04U }, +/* bdcfg_ca_swap */ 0x01546230U, +/* bdcfg_dqs_swap */ 0x01U, +/* bdcfg_dq_swap[] */ { 0x45761328U, 0x62801745U }, +/* bdcfg_dm_swap[] */ { 0x00U, 0x03U }, +/* bdcfg_cs_swap */ 0x10U + } + } +}, +#endif +/* + * boardcnf[1] RENESAS V4H (4ch) + */ +{ + 0x0FU, /* bdcfg_phyvalid */ + 0x00000000U, /* bdcfg_vref_r */ + 0x0000U, /* bdcfg_vref_w */ + 0x0000U, /* bdcfg_vref_ca */ + 0x01U, /* bdcfg_rfm_chk */ + { +/* ch[0] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x06543210U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U }, +/* bdcfg_dm_swap[] */ { 0x08U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[1] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x06543210U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U }, +/* bdcfg_dm_swap[] */ { 0x08U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[2] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x06543210U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U }, +/* bdcfg_dm_swap[] */ { 0x08U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[3] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x06543210U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U }, +/* bdcfg_dm_swap[] */ { 0x08U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + } + } +}, +/* + * boardcnf[2]MOBIS Proto1 20240717 + */ +{ + 0x0FU, /* bdcfg_phyvalid */ + 0x00000000U, /* bdcfg_vref_r */ + 0x0000U, /* bdcfg_vref_w */ + 0x0000U, /* bdcfg_vref_ca */ + 0x01U, /* bdcfg_rfm_chk */ + { +/* ch[0] */ { +/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU }, +/* bdcfg_ca_swap */0x04506132U, +/* bdcfg_dqs_swap */0x01U, +/* bdcfg_dq_swap[] */{ 0x26147085U, 0x12306845U }, +/* bdcfg_dm_swap[] */{ 0x03U, 0x07U }, +/* bdcfg_cs_swap */0x10U + }, +/* ch[1] */ { +/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU }, +/* bdcfg_ca_swap */0x02341065U, +/* bdcfg_dqs_swap */0x10U, +/* bdcfg_dq_swap[] */{ 0x58762314U, 0x71048365U }, +/* bdcfg_dm_swap[] */{ 0x00U, 0x02U }, +/* bdcfg_cs_swap */0x10U + }, +/* ch[2] */ { +/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU }, +/* bdcfg_ca_swap */0x02150643U, +/* bdcfg_dqs_swap */0x10U, +/* bdcfg_dq_swap[] */{ 0x58264071U, 0x41207536U }, +/* bdcfg_dm_swap[] */{ 0x03U, 0x08U }, +/* bdcfg_cs_swap */0x10U + }, +/* ch[3] */ { +/* bdcfg_ddr_density[] */{ 0x06U, 0xFFU }, +/* bdcfg_ca_swap */0x01546230U, +/* bdcfg_dqs_swap */0x01U, +/* bdcfg_dq_swap[] */{ 0x48761325U, 0x62801745U }, +/* bdcfg_dm_swap[] */{ 0x00U, 0x03U }, +/* bdcfg_cs_swap */0x10U + } + } +} + +}; +#endif /* BOOT_INIT_DRAM_CONFIG */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h new file mode 100644 index 0000000..a31f1f0 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h @@ -0,0 +1,203 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#ifndef BOOT_INIT_DRAM_REGDEF +#define BOOT_INIT_DRAM_REGDEF + +#if defined(__RH850G3K__) +#include "remap_register.h" +#endif + +//! @details The version of DDR code +#define RCAR_DDR_VERSION "rev.1.10" +//! @details The number of channels V4H has +#define DRAM_CH_CNT 0x04U +//! @details The number of slices V4H has +#define SLICE_CNT 0x02U +//! @details The number of chip select V4H has +#define CS_CNT 0x02U + +//! @details for pll setting +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) + +//! @details for ddr density setting +#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30U) | ((row) << 24U) | ((BG) << 20U) | ((bank) << 16U) | ((col) << 8U) | (dw)) +//! @details for 16bit value +#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density % 2U), (((density+ 1U) / 2U) + (28U - 2U - 2U - 10U - 1U)), 2U, 2U, 10U, 1U)) /* 16bit */ + +//! @details Kick bit setting CPG PLL3 division +#define CPG_FRQCRD_KICK_BIT (1U << 31) +//! @details Kick bit to reflect setting CPG PLL3 value +#define CPG_PLL3CR0_KICK_BIT (1U << 31) +//! @details Status bit to check CPG PLL3 works normally +#define CPG_PLLECR_PLL3ST_BIT (1U << 11) + +#if defined(__RH850G3K__) +//! @details If this bin is processed by RH850G3K, address will be remapped. +#define CPG_BASE (BASE_CPG_ADDR) +#else +//! @details If this bin is processed by Arm core, address will be "0xE6150000U". +#define CPG_BASE (0xE6150000U) +#endif +//! @details 32-bit readable/writable register +#define CPG_CPGWPR (CPG_BASE + 0x0000U) +//! @details The register specifies the DDR and DBSC clock (ZB3, ZB3D2,ZB3D4) frequency +#define CPG_FRQCRD0 (CPG_BASE + 0x080CU) +//! @details PLL Enable Control Register +#define CPG_PLLECR (CPG_BASE + 0x0820U) +//! @details The register specifies the integer multiplication ratio +#define CPG_PLL3CR0 (CPG_BASE + 0x083CU) +//! @details The register specifies the fractional multiplication +#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U) +//! @details Functional Safety Reset Check Clear Register +#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U) +//! @details Functional Safety Reset Check Set Register +#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U) +//! @details Functional Safety Reset Check Register A +#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U) +//! @details Software Reset Status Register +#define CPG_SRCR4 (CPG_BASE + 0x2C10U) +//! @details Software Reset Clearing Register +#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U) + +#if defined(__RH850G3K__) +//! @details If this bin is processed by RH850G3K, address will be remapped. +#define RST_BASE (BASE_RESET_ADDR) +#else +//! @details If this bin is processed by Arm core, address will be 0xE6160000U. +#define RST_BASE (0xE6160000U) +#endif +//! @details 32-bit read-only register, which is initialized only by POR. +#define RST_MODEMR0 (RST_BASE + 0x0000U) +//! @details 32-bit read-only register, which is initialized only by POR. +#define RST_MODEMR1 (RST_BASE + 0x0004U) + +#if defined(__RH850G3K__) +#define OTP_MEM_1_BASE (BASE_OTP_MEM_ADDR) +#else +#define OTP_MEM_1_BASE (0xE61BF000U) +#endif +#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U) +#define OTP_MEM_PRODUCT_MASK (0x000000FFU) + +/* Product Register */ +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) + +#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */ + +#define PRR_PRODUCT_30 (0x00000020U) /* ver 3.0 */ + +/* DBSC registers */ +#if defined(__RH850G3K__) +//! @details If this bin is processed by RH850G3K, address will be remapped. +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#else +//! @details If this bin is processed by RH850G3K, address will be remapped. +#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#endif +//! @details DBSC4 System Configuration Register 0 +#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U) +//! @details DBSC4 System Configuration Register 1(for DFI domain) +#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U) +//! @details DBSC4 System Configuration Register 1(for AXI domain) +#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U) +//! @details DBSC4 System Configuration Register 2 +#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U) +//! @details PHY type Configuration Register +#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U) +//! @details PHY type Configuration Register 2A +#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U) +//! @details Memory Type register (for DFI domain) +#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U) +//! @details Memory Type register (for AXI domain) +#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U) +//! @details SDRAM Configuration setting Register (for DFI domain) +#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + (0x2000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs))) +//! @details SDRAM Configuration setting Register (for AXI domain) +#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + (0x4000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs))) +//! @details DBSC System Register 0(For DFI Domain) +#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U) +//! @details DBSC System Register 0(For AXI Domain) +#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U) +//! @details SDRAM Access Enable Register +#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U) +//! @details Auto-Refresh Enable Register +#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U) +//! @details Manual Command-Issuing Register +#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U) +//! @details Operation Complition Waiting Register +#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U) +//! @details SDRAM Operation Setting Register(for DFI domain) +#define DBSC_DBBL (DBSC_D_BASE + 0x0400U) +//! @details SDRAM Operation Setting Register(for AXI domain) +#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U) +//! @details Refresh Configuration Register 1 +#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U) +//! @details Refresh Configuration Register 2 +#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U) +//! @details SDRAM Callibration Configuration Register +#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U) +//! @details DBI Configuration Register +#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U) +//! @details DFI PHY Master Control Register +#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U) +//! @details DFI Control Update Configuration Register +#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U) +//! @details CAM Unit Operation Setting Register +#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU) +//! @details Read/Write Scheduling Setting Register 1 +#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U) +//! @details Data Transfer Cycle Setting +#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U) +//! @details SDRAM Timing Register X +#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + (0x04U * (x))) +//! @details Multirank Operation Setting Register x +#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + (0x04U * (x))) +//! @details DFI Status Interface Input Regiser +#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details DFI Status Interface Output Regiser +#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details PHY Unit Control Register 02 +#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details PHY Unit Lock register +#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details PHY Unit register address +#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details PHY Unit register access +#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details PHY Unit Registers Mask for channel +#define DBSC_DBPDRGM(ch) (DBSC_D_BASE + 0x062CU + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details PHY Status Register0 ch +#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details PHY Status Register1 ch +#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details Interval Setting for scheduler +#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U) +//! @details Interval Setting for scheduler +#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U) + +#endif /* BOOT_INIT_DRAM_REGDEF */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ddr_regdef.h b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ddr_regdef.h new file mode 100644 index 0000000..f566504 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ddr_regdef.h @@ -0,0 +1,269 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#ifndef DDR_REGDEF +#define DDR_REGDEF + +#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL 0x10031000U +#define PHY_PER_CS_TRAINING_MULTICAST_EN 0x10011006U +#define PHY_VREF_INITIAL_STEPSIZE 0x1808100DU +#define PHY_RDLVL_BEST_THRSHLD 0x0004100EU +#define PHY_RDLVL_VREF_OUTLIER 0x1003100EU +#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x1005102CU +#define PHY_CALVL_VREF_DRIVING_SLICE 0x18011030U +#define PHY_WRLVL_HARD0_DELAY_OBS 0x000A1038U +#define PHY_WRLVL_HARD1_DELAY_OBS 0x100A1038U +#define PHY_WRLVL_STATUS_OBS 0x001C1039U +#define PHY_WRLVL_ERROR_OBS 0x0010103BU +#define PHY_GTLVL_STATUS_OBS 0x0012103DU +#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x1009103EU +#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x0009103FU +#define PHY_WDQLVL_STATUS_OBS 0x00201043U +#define PHY_DATA_DC_CAL_START 0x1801104DU +#define PHY_SLV_DLY_CTRL_GATE_DISABLE 0x1001104EU +#define PHY_REGULATOR_EN_CNT 0x18061050U +#define PHY_VREF_INITIAL_START_POINT 0x00091055U +#define PHY_VREF_INITIAL_STOP_POINT 0x10091055U +#define PHY_VREF_TRAINING_CTRL 0x00021056U +#define PHY_RDDQ0_SLAVE_DELAY 0x0009105DU +#define PHY_RDDQ1_SLAVE_DELAY 0x1009105DU +#define PHY_RDDQ2_SLAVE_DELAY 0x0009105EU +#define PHY_RDDQ3_SLAVE_DELAY 0x1009105EU +#define PHY_RDDQ4_SLAVE_DELAY 0x0009105FU +#define PHY_RDDQ5_SLAVE_DELAY 0x1009105FU +#define PHY_RDDQ6_SLAVE_DELAY 0x00091060U +#define PHY_RDDQ7_SLAVE_DELAY 0x10091060U +#define PHY_RDDM_SLAVE_DELAY 0x00091061U +#define PHY_RX_CAL_ALL_DLY 0x18061061U +#define PHY_RX_PCLK_CLK_SEL 0x00031062U +#define PHY_DATA_DC_CAL_CLK_SEL 0x18031063U +#define PHY_PAD_VREF_CTRL_DQ 0x000E1067U +#define PHY_PER_CS_TRAINING_EN 0x00011068U +#define PHY_RDDATA_EN_TSEL_DLY 0x18051069U +#define PHY_RDDATA_EN_OE_DLY 0x0005106AU +#define PHY_RPTR_UPDATE 0x1004106CU +#define PHY_WRLVL_RESP_WAIT_CNT 0x0806106DU +#define PHY_RDLVL_DLY_STEP 0x08041070U +#define PHY_RDLVL_MAX_EDGE 0x00091071U +#define PHY_RDDATA_EN_DLY 0x10051076U +#define PHY_DQ_DM_SWIZZLE0 0x00201077U +#define PHY_DQ_DM_SWIZZLE1 0x00041078U +#define PHY_CLK_WRDQS_SLAVE_DELAY 0x0009107EU +#define PHY_WRITE_PATH_LAT_DEC 0x1001107EU +#define PHY_RDDQS_GATE_SLAVE_DELAY 0x00091088U +#define PHY_RDDQS_LATENCY_ADJUST 0x10051088U +#define PHY_WRITE_PATH_LAT_ADD 0x18031088U +#define PHY_WRITE_PATH_LAT_FRAC 0x00081089U +#define PHY_GTLVL_LAT_ADJ_START 0x0005108AU +#define PHY_ADR_CALVL_SWIZZLE0 0x00201202U +#define PHY_ADR_MEAS_DLY_STEP_ENABLE 0x10011203U +#define PHY_ADR_CALVL_RANK_CTRL 0x18021205U +#define PHY_ADR_CALVL_OBS1 0x0020120AU +#define PHY_ADR_CALVL_OBS2 0x0020120BU +#define PHY_ADR_CALVL_DLY_STEP 0x00041210U +#define PHY_CS_ACS_ALLOCATION_BIT2_2 0x08021215U +#define PHY_CS_ACS_ALLOCATION_BIT3_2 0x10021215U +#define PHY_CSLVL_OBS1 0x00201221U +#define PHY_CLK_DC_CAL_CLK_SEL 0x0803123AU +#define PHY_FREQ_SEL_MULTICAST_EN 0x08011301U +#define PHY_FREQ_SEL_INDEX 0x10021301U +#define SC_PHY_MANUAL_UPDATE 0x18011304U +#define PHY_SET_DFI_INPUT_RST_PAD 0x18011311U +#define PHY_CAL_MODE_0 0x000D132CU +#define PHY_CAL_INTERVAL_COUNT_0 0x0020132DU +#define PHY_DATA_BYTE_ORDER_SEL 0x0020133EU +#define PHY_PAD_ACS_RX_PCLK_CLK_SEL 0x10031348U +#define PHY_PLL_CTRL 0x000E134BU +#define PHY_PLL_CTRL_8X 0x100E134BU +#define PHY_CAL_CLK_SELECT_0 0x00031360U +#define SC_PHY_WCK_CALC 0x1801101AU +#define PI_START 0x00010800U +#define PI_TRAIN_ALL_FREQ_REQ 0x18010802U +#define PI_CS_MAP 0x08020813U +#define PI_WRLVL_REQ 0x1001081CU +#define PI_WRLVL_CS_SW 0x1802081CU +#define PI_RDLVL_REQ 0x18010824U +#define PI_RDLVL_GATE_REQ 0x00010825U +#define PI_RDLVL_CS_SW 0x08020825U +#define PI_DRAMDCA_FLIP_MASK 0x0802083BU +#define PI_DRAMDCA_LVL_REQ 0x1001083DU +#define PI_DCMLVL_CS_SW 0x1802083DU +#define PI_WRDCM_LVL_EN_F1 0x0002083FU +#define PI_DRAMDCA_LVL_EN_F1 0x0802083FU +#define PI_WRDCM_LVL_EN_F2 0x1802083FU +#define PI_DRAMDCA_LVL_EN_F2 0x00020840U +#define PI_TCKCKEL_F2 0x1804089DU +#define PI_INT_STATUS 0x00200900U +#define PI_INT_ACK_0 0x00200902U +#define PI_INT_ACK_1 0x00030903U +#define PI_ADDR_MUX_0 0x00030910U +#define PI_ADDR_MUX_1 0x08030910U +#define PI_ADDR_MUX_2 0x10030910U +#define PI_ADDR_MUX_3 0x18030910U +#define PI_ADDR_MUX_4 0x00030911U +#define PI_ADDR_MUX_5 0x08030911U +#define PI_ADDR_MUX_6 0x10030911U +#define PI_DATA_BYTE_SWAP_EN 0x18010911U +#define PI_DATA_BYTE_SWAP_SLICE0 0x00010912U +#define PI_DATA_BYTE_SWAP_SLICE1 0x08010912U +#define PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x00080964U +#define PI_WRLAT_F2 0x1007096AU +#define PI_TWCKENL_WR_ADJ_F2 0x1806096AU +#define PI_TWCKENL_RD_ADJ_F2 0x0006096BU +#define PI_TWCKPRE_STATIC_F2 0x0806096BU +#define PI_TWCKPRE_TOGGLE_RD_F2 0x1806096BU +#define PI_TWCKENL_FS_ADJ_F2 0x0006096CU +#define PI_CASLAT_F2 0x0807096CU +#define PI_TRFC_F2 0x000A0971U +#define PI_TREF_F2 0x00140972U +#define PI_TDFI_WRLVL_WW_F0 0x000A0974U +#define PI_TDFI_WRLVL_WW_F1 0x000A0975U +#define PI_WRLVL_EN_F2 0x18020975U +#define PI_TDFI_WRLVL_WW_F2 0x000A0976U +#define PI_WRLVL_WCKOFF_F2 0x10080976U +#define PI_RDLVL_EN_F2 0x1802097AU +#define PI_RDLVL_GATE_EN_F2 0x0002097BU +#define PI_RDLVL_VREF_EN_F0 0x1004097BU +#define PI_RDLVL_VREF_EN_F1 0x0004097DU +#define PI_RDLVL_VREF_EN_F2 0x1004097EU +#define PI_RDLAT_ADJ_F2 0x00090981U +#define PI_WRLAT_ADJ_F2 0x00070982U +#define PI_TDFI_CALVL_CC_F2 0x000A0985U +#define PI_TDFI_CALVL_CAPTURE_F2 0x100A0985U +#define PI_CALVL_EN_F2 0x10020986U +#define PI_TCAENT_F2 0x000E0989U +#define PI_TVREF_SHORT_F2 0x000A098FU +#define PI_TVREF_LONG_F2 0x100A098FU +#define PI_TVRCG_ENABLE_F2 0x000A0990U +#define PI_TVRCG_DISABLE_F2 0x100A0990U +#define PI_CALVL_VREF_INITIAL_START_POINT_F0 0x00070991U +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F0 0x08070991U +#define PI_CALVL_VREF_INITIAL_START_POINT_F1 0x18070991U +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F1 0x00070992U +#define PI_CALVL_VREF_INITIAL_START_POINT_F2 0x10070992U +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x18070992U +#define PI_TDFI_CALVL_STROBE_F2 0x08040995U +#define PI_TXP_F2 0x10050995U +#define PI_TMRWCKEL_F2 0x18080995U +#define PI_TCKEHDQS_F2 0x1006099DU +#define PI_TFC_F2 0x000A099EU +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x100709A0U +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x180709A0U +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x000709A4U +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x080709A4U +#define PI_TDFI_WDQLVL_WR_F2 0x000A09A6U +#define PI_TDFI_WDQLVL_RW_F2 0x100A09A6U +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x000709A7U +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x080709A7U +#define PI_WDQLVL_EN_F2 0x180209A7U +#define PI_MBIST_RDLAT_ADJ_F2 0x080909A8U +#define PI_MBIST_TWCKENL_RD_ADJ_F2 0x180609A8U +#define PI_TRTP_F2 0x180809B3U +#define PI_TRP_F2 0x000809B4U +#define PI_TRCD_F2 0x080809B4U +#define PI_TWTR_S_F2 0x180609B4U +#define PI_TWTR_L_F2 0x000609B5U +#define PI_TWTR_F2 0x100609B5U +#define PI_TWR_F2 0x180809B5U +#define PI_TRAS_MIN_F2 0x100909B6U +#define PI_TDQSCK_MAX_F2 0x000409B7U +#define PI_TSR_F2 0x100809B7U +#define PI_TMRD_F2 0x180809B7U +#define PI_TDFI_CTRLUPD_MAX_F2 0x001509BCU +#define PI_TDFI_CTRLUPD_INTERVAL_F2 0x002009BDU +#define PI_TINIT_F2 0x001809CCU +#define PI_TINIT1_F2 0x001809CDU +#define PI_TINIT3_F2 0x001809CEU +#define PI_TINIT4_F2 0x001809CFU +#define PI_TINIT5_F2 0x001809D0U +#define PI_TXSNR_F2 0x001009D1U +#define PI_TZQCAL_F2 0x100C09D6U +#define PI_TZQLAT_F2 0x000709D7U +#define PI_ZQRESET_F2 0x100C09D8U +#define PI_TDQ72DQ_F2 0x100A09DDU +#define PI_TCBTRTW_F2 0x000609DEU +#define PI_MC_TRFC_F2 0x000A09E1U +#define PI_CKE_MUX_0 0x000309E6U +#define PI_CKE_MUX_1 0x080309E6U +#define PI_SEQ_DEC_SW_CS 0x00020A4EU +#define PI_SW_SEQ_START 0x10010A4EU +#define PI_SW_SEQ_0 0x001B0BF1U +#define PI_SW_SEQ_1 0x001B0BF2U +#define PI_DFS_ENTRY_SEQ_0 0x001D0BFBU +#define PI_DFS_INITIALIZATION_SEQ_1 0x001D0C24U +#define PI_DFS_INITIALIZATION_SEQ_9 0x001D0C2CU +#define PI_DFS_INITIALIZATION_SEQ_10 0x001D0C2DU +#define PI_SEQ_WAIT_16_F2 0x00180C77U +#define PI_SEQ_WAIT_17_F2 0x00180C7AU +#define PI_SEQ_WAIT_18_F2 0x00180C7DU +#define PI_SEQ_WAIT_19_F2 0x00180C80U +#define PI_SEQ_WAIT_20_F2 0x00180C83U +#define PI_SEQ_WAIT_21_F2 0x00180C86U +#define PI_SEQ_WAIT_22_F2 0x00180C89U +#define PI_SEQ_WAIT_23_F2 0x00180C8CU +#define PI_SEQ_WAIT_24_F2 0x00180C8FU +#define PI_SEQ_WAIT_25_F2 0x00180C92U +#define PI_SEQ_WAIT_26_F2 0x00180C95U +#define PI_SEQ_WAIT_30_F2 0x00180CA1U +#define PI_DARRAY3_0_CS0_F0 0x00080D0BU +#define PI_DARRAY3_1_CS0_F0 0x08080D0BU +#define PI_DARRAY3_0_CS0_F1 0x00080D15U +#define PI_DARRAY3_1_CS0_F1 0x08080D15U +#define PI_DARRAY3_0_CS0_F2 0x00080D1FU +#define PI_DARRAY3_1_CS0_F2 0x08080D1FU +#define PI_DARRAY3_4_CS0_F2 0x00080D20U +#define PI_DARRAY3_20_CS0_F2 0x00080D24U +#define PI_DARRAY3_0_CS1_F0 0x00080D29U +#define PI_DARRAY3_1_CS1_F0 0x08080D29U +#define PI_DARRAY3_0_CS1_F1 0x00080D33U +#define PI_DARRAY3_1_CS1_F1 0x08080D33U +#define PI_DARRAY3_0_CS1_F2 0x00080D3DU +#define PI_DARRAY3_1_CS1_F2 0x08080D3DU +#define PI_DARRAY3_4_CS1_F2 0x00080D3EU +#define PI_DARRAY3_20_CS1_F2 0x00080D42U +#define PI_DLL_RST 0x00010941U +#define PI_PWRUP_SREFRESH_EXIT 0x1801093DU +#define PI_PWRUP_SREFRESH_EXIT 0x1801093DU +#define PI_RDLVL_TRAIN_SEQ_1 0x001B0C42U +#define PI_RDLVL_TRAIN_SEQ_2 0x001B0C43U +#define PI_RDLVL_TRAIN_SEQ_3 0x001B0C44U +#define PI_RDLVL_TRAIN_SEQ_4 0x001B0C45U +#define PI_RDLVL_TRAIN_SEQ_5 0x001B0C46U +#define PI_WDQLVL_VREF_EN 0x0804089EU +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_2 0x001B0868U +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_3 0x001B0869U +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_4 0x001B086AU +#define PHY_PER_CS_TRAINING_INDEX 0x18011006U +#define PHY_DATA_DC_DQS_CLK_ADJUST 0x0008108CU +#define PHY_DATA_DC_WDQLVL_ENABLE 0x08021075U +#define PI_WDQLVL_PERIODIC 0x000108A0U +#define PHY_MEAS_DLY_STEP_ENABLE 0x08061076U +#define PI_RDLVL_PERIODIC 0x0801082EU +#define PI_LONG_COUNT_MASK 0x1005090FU +#define PI_WDQLVL_INTERVAL 0x001008A4U +#define PI_RDLVL_INTERVAL 0x08100835U +#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xFFFFU) +#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xFFU) +#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xFFU) + +#endif /* DDR_REGDEF */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c new file mode 100644 index 0000000..4245fdc --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c @@ -0,0 +1,183 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC initialize function + ******************************************************************************/ +/****************************************************************************** + * @file ecc_enable_v4h.c + * - Version : 0.06 + * @brief Enable setting process of ECC for DRAM. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 09.08.2022 0.01 First Release + * : 16.11.2022 0.02 Change ecc_enable to ecc_sdram_enable + * : 04.04.2023 0.03 Removed stdio.h and string.h. + * : 20.09.2023 0.04 Update the ecc_sdram_enable function according to HWSAN rev0.82. + * : 13.06.2024 0.05 Fix register setting for EDC_CFG, and revise + * : the ecm_lock()/ecm_unlock() process. + * : 27.01.2025 0.06 Remove unused functions. + *****************************************************************************/ + +#include + +#if (ECC_ENABLE == 1) +#include "ecc_enable_v4h.h" +#include "ecm_enable_v4h.h" +#include "mem_io.h" +#include "v4h/lpddr5/boot_init_dram_regdef.h" + +/* Reference:"ECC for DRAM and System RAM" in R19AN0083EJ0082_R-CarV4H_SAN_for_Customer.pdf*/ +void ecc_sdram_enable(void) +{ + NOTICE("ECC for DRAM is enable.\n"); + + uint32_t ecm_tmp; + + /* Before writing to DBSC register, it shall be set to "0x00001234" for the following registers. + After writing to DBSC register, it shall be set to a value other than "0x00001234" for the following registers. */ + mem_write32(DB0SYSCNT0, 0x00001234U); + mem_write32(DB1SYSCNT0, 0x00001234U); + mem_write32(DB0SYSCNT0A, 0x00001234U); + mem_write32(DB1SYSCNT0A, 0x00001234U); + + /* (A) Setting ECM */ + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers + to inform the external device of the error via the ERROROUT# pin. */ + /* Set bit 3, 1 of ECMERRTGTR0 to 0 and bit 3, 1 of ECMERRCTLR0 to 1. */ + ecm_tmp = mem_read32(ECMERRTGTR0); + ecm_tmp &= ~(0xAU); + ecm_write(ECMERRTGTR0, ecm_tmp); + + ecm_tmp = mem_read32(ECMERRCTLR0); + ecm_tmp |= (0xAU); + ecm_write(ECMERRCTLR0, ecm_tmp); + + /* (B) Setting ECC protection area */ + /* Set the bottom row address of the ECC protection area */ + mem_write32(DB0FSDRAMECCAREA00, ECC_PROT_SIZE00); + mem_write32(DB1FSDRAMECCAREA00, ECC_PROT_SIZE10); + + /* (C) Initialization for DRAM */ + mem_write32(DBSC_DB0ACEN, 0x00000000U); + mem_write32(DBSC_DB1ACEN, 0x00000000U); + + /*** Initialization for DRAM connected to DBS0 Initialize RANK0 in according with the following procedure.***/ + /* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB0FSCONF00A[1:0]. */ + mem_write32(DB0FSCONF00A, 0x0U); + + /* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */ + mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA00); + + /* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */ + mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA00); + + /* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */ + mem_write32(DB0FSCTRL01A, 0x01U); + + /*** Initialization for DRAM connected to DBS1 Initialize RANK0 in according with the following procedure.***/ + /* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB1FSCONF00A[1:0]. */ + mem_write32(DB1FSCONF00A, 0x0U); + + /* [Step2] Set the start row address of the initialization area in DB1FSCONF01A[31:0]. */ + mem_write32(DB1FSCONF01A, START_ECC_INIT_AREA10); + + /* [Step3] Set the end row address of the initialization area in DB1FSCONF02A[31:0]. */ + mem_write32(DB1FSCONF02A, END_ECC_INIT_AREA10); + + /* [Step4] Set 0x1 to DB1FSCTRL01A[0] to start initialization. */ + mem_write32(DB1FSCTRL01A, 0x01U); + + /* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */ + /* [Step5] When DB1FSSTAT01A[0] is set to 0x1, DBS1/RANK0 initialization is complete.*/ + NOTICE("DRAM rank 0 of DBSC0/1 is initializing.......\n"); + do + { + ecm_tmp = 0x01U; + ecm_tmp &= mem_read32(DB0FSSTAT01A); + ecm_tmp &= mem_read32(DB1FSSTAT01A); + } while ((ecm_tmp & 0x01U) != 0x01U); + + /* (D) Setting ECC protection enable */ + /* Enable ECC protection for dbs0/rank0 by setting 0x1 in DB0FSCONFAXI0[8]. */ + ecm_tmp = mem_read32(DB0FSCONFAXI0); + ecm_tmp |= (0x1U << 8U); + mem_write32(DB0FSCONFAXI0, ecm_tmp); + + /* Enable ECC protection for dbs1/rank0 by setting 0x1 in DB1FSCONFAXI0[8]. */ + ecm_tmp = mem_read32(DB1FSCONFAXI0); + ecm_tmp |= (0x1U << 8U); + mem_write32(DB1FSCONFAXI0, ecm_tmp); + + /* (E) System RAM initialization */ + NOTICE("System RAM of DBSC0 is initializing.......\n"); + do + { + ecm_tmp = 0x01U; + ecm_tmp &= mem_read32(DB0FSSTAT00A); + } while (ecm_tmp != 0x1U); + + NOTICE("System RAM of DBSC1 is initializing.......\n"); + do + { + ecm_tmp = 0x01U; + ecm_tmp &= mem_read32(DB1FSSTAT00A); + } while (ecm_tmp != 0x1U); + + /* (F) Setting for ECC error interrupt */ + /* (1) Set the ECC error interrupt for read data. */ + mem_write32(DB0FSINTENB02A, 0xFF00U); + mem_write32(DB1FSINTENB02A, 0xFF00U); + + /* (2) Set the ECC error interrupt during RMW operation for System RAM. */ + ecm_tmp = mem_read32(DB0FSINTENB02A); + ecm_tmp |= 0xFF000000U; + mem_write32(DB0FSINTENB02A, ecm_tmp); + ecm_tmp = mem_read32(DB1FSINTENB02A); + ecm_tmp |= 0xFF000000U; + mem_write32(DB1FSINTENB02A, ecm_tmp); + + /* (3) Set the ECC error interrupt during RMW operation for DRAM. */ + mem_write32(DB0FSINTENB04A, 0xFFFFFFFFU); + mem_write32(DB1FSINTENB04A, 0xFFFFFFFFU); + + /* Lock the ECM registers */ + ecm_lock(); + + /* Enable the write protect of ECM registers */ + mem_write32(DBSC_DB0ACEN, 0x00000001U); + mem_write32(DBSC_DB1ACEN, 0x00000001U); + + /* Enable the access protect for DBSC registers */ + mem_write32(DB0SYSCNT0, 0x00000000U); + mem_write32(DB1SYSCNT0, 0x00000000U); + mem_write32(DB0SYSCNT0A, 0x00000000U); + mem_write32(DB1SYSCNT0A, 0x00000000U); +} +#endif /* ECC_ENABLE == 1 */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h new file mode 100644 index 0000000..4798011 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h @@ -0,0 +1,111 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC driver header + ******************************************************************************/ + +#ifndef ECC_PROTECT +#define ECC_PROTECT +/* DBSC registers */ +#if defined(__RH850G3K__) +#include "remap_register.h" +#include "mem_io.h" +#include "log.h" +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#define ECM_BASE (BASE_ECC_ADDR) +#else +#if (ECC_ENABLE == 1) +#include "mem_io.h" +#include "log.h" +#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#endif /* ECC_ENABLE == 1 */ +#define ECM_BASE (0xE6250000U) +#endif/* defined(__RH850G3K__) */ + +#if (ECC_ENABLE == 1) +void ecc_sdram_enable(void); + +#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U) +#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U) +#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U) + +#define DBSC_DB0ACEN (DBSC_A_BASE + 0x0200U) +#define DBSC_DB1ACEN (DBSC_DB0ACEN + 0x8000U) +#endif /* ECC_ENABLE == 1 */ + +#define ECMWACNTR (ECM_BASE + 0x0A04U) +#define ECMWPCNTR (ECM_BASE + 0x0A00U) +#if (ECC_ENABLE == 1) +#define ECMERRTGTR0 (ECM_BASE + 0x0200U) +#define ECMERRCTLR0 (ECM_BASE + 0x0000U) +#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U) +#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U) +#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U) +#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U) +#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U) +#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U) +#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U) +#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U) +#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U) +#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U) +#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U) +#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U) +#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U) +#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U) +#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U) +#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U) + +#define DB0FSDRAMECCAREA00 (DBSC_A_BASE + 0x7450U) +#define DB0FSDRAMECCAREA01 (DBSC_A_BASE + 0x7454U) +#define DB1FSDRAMECCAREA00 (DB0FSDRAMECCAREA00 + 0x8000U) +#define DB1FSDRAMECCAREA01 (DB0FSDRAMECCAREA01 + 0x8000U) + +#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U) +#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U) + +/********************* Set by the user *********************/ +/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */ +#define ECC_PROT_SIZE00 (0xCCCCU) +#define ECC_PROT_SIZE01 (0xCCCCU) +#define ECC_PROT_SIZE10 (0xCCCCU) +#define ECC_PROT_SIZE11 (0xCCCCU) + +/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */ +#define START_ECC_INIT_AREA00 (0x00000000U) +#define START_ECC_INIT_AREA10 (0x00000000U) +#define END_ECC_INIT_AREA00 (0x0000CCCBU) +#define END_ECC_INIT_AREA10 (0x0000CCCBU) + +/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */ +#define START_ECC_INIT_AREA01 (0x00000000U) +#define START_ECC_INIT_AREA11 (0x00000000U) +#define END_ECC_INIT_AREA01 (0x0000CCCBU) +#define END_ECC_INIT_AREA11 (0x0000CCCBU) +/*********** Other settings cannot be changed ***************/ +#endif /* ECC_ENABLE == 1 */ + +#endif/* ECC_PROTECT */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c new file mode 100644 index 0000000..cdcdef6 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c @@ -0,0 +1,260 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM initialize function + ******************************************************************************/ +/****************************************************************************** + * @file ecm_enable_v4h.c + * - Version : 0.01 + * @brief ECM setting. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.01.2025 0.01 First Release + *****************************************************************************/ + +#include +#include "ecm_enable_v4h.h" + +#if (ECM_ERROR_ENABLE == 1) +#include "log.h" +#endif /* ECM_ERROR_ENABLE == 1 */ +#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1)) +#include "ecc_enable_v4h.h" +#include "mem_io.h" +#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +#define ECM_ERR_REG_MAX (40U) + +typedef struct{ + uint32_t phys_addr; /* Physical address of ECM registers. */ + uint32_t value; /* Setting value of ECM registers. */ +} ECM_ERROR_TABLE; +#endif /* ECM_ERROR_ENABLE == 1 */ + +#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1)) +void ecm_unlock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0001U); +} + +void ecm_write(uint32_t adr, uint32_t val) +{ + mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU))); + mem_write32(adr, val); +} + +void ecm_lock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0000U); +} +#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_error_enable(void) +{ + uint32_t reg; + uint32_t loop; + + const ECM_ERROR_TABLE ecmerrctlr_tbl[ECM_ERR_REG_MAX] = { + [0] = {0xE6250000U, 0xFFFFF00FU}, /* ECMERRCTLR0 */ + [1] = {0xE6250004U, 0xFFF8C000U}, /* ECMERRCTLR1 */ + [2] = {0xE6250008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */ + [3] = {0xE625000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */ + [4] = {0xE6250010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */ + [5] = {0xE6250014U, 0xFFFFFFFFU}, /* ECMERRCTLR5 */ + [6] = {0xE6250018U, 0xFF000A80U}, /* ECMERRCTLR6 */ + [7] = {0xE625001CU, 0x6F980FFFU}, /* ECMERRCTLR7 */ + [8] = {0xE6250020U, 0xFFF00000U}, /* ECMERRCTLR8 */ + [9] = {0xE6250024U, 0xFF000000U}, /* ECMERRCTLR9 */ + [10] = {0xE6250028U, 0x557D554FU}, /* ECMERRCTLR10 */ + [11] = {0xE625002CU, 0xFFFC1555U}, /* ECMERRCTLR11 */ + [12] = {0xE6250030U, 0x5557FFFFU}, /* ECMERRCTLR12 */ + [13] = {0xE6250034U, 0x00000055U}, /* ECMERRCTLR13 */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + [14] = {0xE6250040U, 0x3FFFFFFFU}, /* ECMERRCTLR16 */ + [15] = {0xE6250044U, 0x2FFF8CE0U}, /* ECMERRCTLR17 */ + [16] = {0xE6250048U, 0x0EC03FFFU}, /* ECMERRCTLR18 */ + [17] = {0xE625004CU, 0xFFFFFFF9U}, /* ECMERRCTLR19 */ + [18] = {0xE6250050U, 0xFE66667EU}, /* ECMERRCTLR20 */ + [19] = {0xE6250054U, 0xBFE3BE0FU}, /* ECMERRCTLR21 */ + [20] = {0xE6250058U, 0x10000000U}, /* ECMERRCTLR22 */ + [21] = {0xE625005CU, 0x7EF3C008U}, /* ECMERRCTLR23 */ + [22] = {0xE6250060U, 0x7FFE8ADBU}, /* ECMERRCTLR24 */ + [23] = {0xE6250064U, 0xCF807FFFU}, /* ECMERRCTLR25 */ + [24] = {0xE6250068U, 0x7EF3C008U}, /* ECMERRCTLR26 */ + [25] = {0xE625006CU, 0x7FFE8ADBU}, /* ECMERRCTLR27 */ + [26] = {0xE6250070U, 0xCF807FFFU}, /* ECMERRCTLR28 */ + [27] = {0xE6250074U, 0x0073C008U}, /* ECMERRCTLR29 */ + [28] = {0xE6250078U, 0x7FE68A9BU}, /* ECMERRCTLR30 */ + [29] = {0xE625007CU, 0x8C007E00U}, /* ECMERRCTLR31 */ + [30] = {0xE6250080U, 0xCFFFFFFFU}, /* ECMERRCTLR32 */ + [31] = {0xE6250084U, 0x0FFFFFFFU}, /* ECMERRCTLR33 */ + [32] = {0xE6250088U, 0x000003FFU}, /* ECMERRCTLR34 */ + [33] = {0xE625008CU, 0xFFFFFFC0U}, /* ECMERRCTLR35 */ + [34] = {0xE6250090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */ + /* Skip ECMERRCTLR37 setting */ + [35] = {0xE6250098U, 0xFFF000FFU}, /* ECMERRCTLR38 */ + [36] = {0xE625009CU, 0x1FFF0000U}, /* ECMERRCTLR39 */ + [37] = {0xE62500A0U, 0x1FFC7FFFU}, /* ECMERRCTLR40 */ + [38] = {0xE62500A4U, 0xEFFF7FFBU}, /* ECMERRCTLR41 */ + [39] = {0xE62500A8U, 0x3FBFFDFFU}, /* ECMERRCTLR42 */ + }; + +#if (ECMERRTGTR_INTC == 1) + const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = { + [0] = {0xE6250200U, 0xFFFFF00FU}, /* ECMERRTGTR0 */ + [1] = {0xE6250204U, 0xFFF8C000U}, /* ECMERRTGTR1 */ + [2] = {0xE6250208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */ + [3] = {0xE625020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */ + [4] = {0xE6250210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */ + [5] = {0xE6250214U, 0xFFFFFFFFU}, /* ECMERRTGTR5 */ + [6] = {0xE6250218U, 0xFF000A80U}, /* ECMERRTGTR6 */ + [7] = {0xE625021CU, 0x6F980FFFU}, /* ECMERRTGTR7 */ + [8] = {0xE6250220U, 0xFFF00000U}, /* ECMERRTGTR8 */ + [9] = {0xE6250224U, 0xFF000000U}, /* ECMERRTGTR9 */ + [10] = {0xE6250228U, 0x557D554FU}, /* ECMERRTGTR10 */ + [11] = {0xE625022CU, 0xFFFC1555U}, /* ECMERRTGTR11 */ + [12] = {0xE6250230U, 0x5557FFFFU}, /* ECMERRTGTR12 */ + [13] = {0xE6250234U, 0x00000055U}, /* ECMERRTGTR13 */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [14] = {0xE6250240U, 0x3FFFFFFFU}, /* ECMERRTGTR16 */ + [15] = {0xE6250244U, 0x2FFF8CE0U}, /* ECMERRTGTR17 */ + [16] = {0xE6250248U, 0x0EC03FFFU}, /* ECMERRTGTR18 */ + [17] = {0xE625024CU, 0xFFFFFFF9U}, /* ECMERRTGTR19 */ + [18] = {0xE6250250U, 0xFE66667EU}, /* ECMERRTGTR20 */ + [19] = {0xE6250254U, 0xBFE3BE0FU}, /* ECMERRTGTR21 */ + [20] = {0xE6250258U, 0x10000000U}, /* ECMERRTGTR22 */ + [21] = {0xE625025CU, 0x7EF3C008U}, /* ECMERRTGTR23 */ + [22] = {0xE6250260U, 0x7FFE8ADBU}, /* ECMERRTGTR24 */ + [23] = {0xE6250264U, 0xCF807FFFU}, /* ECMERRTGTR25 */ + [24] = {0xE6250268U, 0x7EF3C008U}, /* ECMERRTGTR26 */ + [25] = {0xE625026CU, 0x7FFE8ADBU}, /* ECMERRTGTR27 */ + [26] = {0xE6250270U, 0xCF807FFFU}, /* ECMERRTGTR28 */ + [27] = {0xE6250274U, 0x0073C008U}, /* ECMERRTGTR29 */ + [28] = {0xE6250278U, 0x7FE68A9BU}, /* ECMERRTGTR30 */ + [29] = {0xE625027CU, 0x8C007E00U}, /* ECMERRTGTR31 */ + [30] = {0xE6250280U, 0xCFFFFFFFU}, /* ECMERRTGTR32 */ + [31] = {0xE6250284U, 0x0FFFFFFFU}, /* ECMERRTGTR33 */ + [32] = {0xE6250288U, 0x000003FFU}, /* ECMERRTGTR34 */ + [33] = {0xE625028CU, 0xFFFFFFC0U}, /* ECMERRTGTR35 */ + [34] = {0xE6250290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */ + /* Skip ECMERRTGTR37 setting */ + [35] = {0xE6250298U, 0xFFF000FFU}, /* ECMERRTGTR38 */ + [36] = {0xE625029CU, 0x1FFF0000U}, /* ECMERRTGTR39 */ + [37] = {0xE62502A0U, 0x1FFC7FFFU}, /* ECMERRTGTR40 */ + [38] = {0xE62502A4U, 0xEFFF7FFBU}, /* ECMERRTGTR41 */ + [39] = {0xE62502A8U, 0x3FBFFDFFU}, /* ECMERRTGTR42 */ + }; +#elif (ECMERRTGTR_INTC == 0) + const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = { + [0] = {0xE6250200U, 0x00000000U}, /* ECMERRTGTR0 */ + [1] = {0xE6250204U, 0x00000000U}, /* ECMERRTGTR1 */ + [2] = {0xE6250208U, 0x00000000U}, /* ECMERRTGTR2 */ + [3] = {0xE625020CU, 0x00000000U}, /* ECMERRTGTR3 */ + [4] = {0xE6250210U, 0x00000000U}, /* ECMERRTGTR4 */ + [5] = {0xE6250214U, 0x00000000U}, /* ECMERRTGTR5 */ + [6] = {0xE6250218U, 0x00000000U}, /* ECMERRTGTR6 */ + [7] = {0xE625021CU, 0x00000000U}, /* ECMERRTGTR7 */ + [8] = {0xE6250220U, 0x00000000U}, /* ECMERRTGTR8 */ + [9] = {0xE6250224U, 0x00000000U}, /* ECMERRTGTR9 */ + [10] = {0xE6250228U, 0x00000000U}, /* ECMERRTGTR10 */ + [11] = {0xE625022CU, 0x00000000U}, /* ECMERRTGTR11 */ + [12] = {0xE6250230U, 0x00000000U}, /* ECMERRTGTR12 */ + [13] = {0xE6250234U, 0x00000000U}, /* ECMERRTGTR13 */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [14] = {0xE6250240U, 0x00000000U}, /* ECMERRTGTR16 */ + [15] = {0xE6250244U, 0x00000000U}, /* ECMERRTGTR17 */ + [16] = {0xE6250248U, 0x00000000U}, /* ECMERRTGTR18 */ + [17] = {0xE625024CU, 0x00000000U}, /* ECMERRTGTR19 */ + [18] = {0xE6250250U, 0x00000000U}, /* ECMERRTGTR20 */ + [19] = {0xE6250254U, 0x00000000U}, /* ECMERRTGTR21 */ + [20] = {0xE6250258U, 0x00000000U}, /* ECMERRTGTR22 */ + [21] = {0xE625025CU, 0x00000000U}, /* ECMERRTGTR23 */ + [22] = {0xE6250260U, 0x00000000U}, /* ECMERRTGTR24 */ + [23] = {0xE6250264U, 0x00000000U}, /* ECMERRTGTR25 */ + [24] = {0xE6250268U, 0x00000000U}, /* ECMERRTGTR26 */ + [25] = {0xE625026CU, 0x00000000U}, /* ECMERRTGTR27 */ + [26] = {0xE6250270U, 0x00000000U}, /* ECMERRTGTR28 */ + [27] = {0xE6250274U, 0x00000000U}, /* ECMERRTGTR29 */ + [28] = {0xE6250278U, 0x00000000U}, /* ECMERRTGTR30 */ + [29] = {0xE625027CU, 0x00000000U}, /* ECMERRTGTR31 */ + [30] = {0xE6250280U, 0x00000000U}, /* ECMERRTGTR32 */ + [31] = {0xE6250284U, 0x00000000U}, /* ECMERRTGTR33 */ + [32] = {0xE6250288U, 0x00000000U}, /* ECMERRTGTR34 */ + [33] = {0xE625028CU, 0x00000000U}, /* ECMERRTGTR35 */ + [34] = {0xE6250290U, 0x00000000U}, /* ECMERRTGTR36 */ + /* Skip ECMERRTGTR37 setting */ + [35] = {0xE6250298U, 0x00000000U}, /* ECMERRTGTR38 */ + [36] = {0xE625029CU, 0x00000000U}, /* ECMERRTGTR39 */ + [37] = {0xE62502A0U, 0x00000000U}, /* ECMERRTGTR40 */ + [38] = {0xE62502A4U, 0x00000000U}, /* ECMERRTGTR41 */ + [39] = {0xE62502A8U, 0x00000000U}, /* ECMERRTGTR42 */ + }; +#endif /* ECMERRTGTR_INTC == 1 */ + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + NOTICE("ECMERRCTLR register setting.\n"); + for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++) + { + /* Set ECMERRCTLR registers. */ + reg = mem_read32(ecmerrctlr_tbl[loop].phys_addr); + reg |= ecmerrctlr_tbl[loop].value; + ecm_write(ecmerrctlr_tbl[loop].phys_addr, reg); + + INFO("ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrctlr_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_tbl[loop].phys_addr), + ecmerrctlr_tbl[loop].value); + } + + NOTICE("ECMERRTGTR register setting.\n"); + for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++) + { + /* Set ECMERRTGTR registers. */ + reg = mem_read32(ecmerrtgtr_tbl[loop].phys_addr); + reg |= ecmerrtgtr_tbl[loop].value; + ecm_write(ecmerrtgtr_tbl[loop].phys_addr, reg); + + INFO("ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrtgtr_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_tbl[loop].phys_addr), + ecmerrtgtr_tbl[loop].value); + } + + /* Lock the ECM registers */ + ecm_lock(); +} +/* End of function ecm_error_enable(void) */ +#endif /* ECM_ERROR_ENABLE == 1 */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h new file mode 100644 index 0000000..980b294 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM driver header + ******************************************************************************/ + +#ifndef ECM_ENABLE +#define ECM_ENABLE + +#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1)) +void ecm_unlock(void); +void ecm_write(uint32_t adr, uint32_t val); +void ecm_lock(void); +#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_error_enable(void); +#endif /* ECM_ERROR_ENABLE == 1 */ + +#endif/* ECM_ENABLE */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/init_dram_tbl_v4h_lp5.h b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/init_dram_tbl_v4h_lp5.h new file mode 100644 index 0000000..81e90ee --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/init_dram_tbl_v4h_lp5.h @@ -0,0 +1,1753 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#ifndef INIT_DRAM_TBL_V4H_LP5 +#define INIT_DRAM_TBL_V4H_LP5 + +//! @details The address offsets of Data Slice +#define DDR_PHY_SLICE_REGSET_OFS_V4H 0x1000 +//! @details The address offsets of Address Slice +#define DDR_PHY_ADR_V_REGSET_OFS_V4H 0x1200 +//! @details The address offsets of Address Control Slice +#define DDR_PHY_ADR_G_REGSET_OFS_V4H 0x1300 +//! @details The address offsets of PI Register +#define DDR_PI_REGSET_OFS_V4H 0x0800 + +//! @details Number of array elements in Data Slice +#define DDR_PHY_SLICE_REGSET_SIZE_V4H 0x100 +//! @details Number of array elements in Data Slice +#define DDR_PHY_SLICE_REGSET_NUM_V4H 153 +//! @details Number of array elements in Address Slice +#define DDR_PHY_ADR_V_REGSET_NUM_V4H 61 +//! @details Number of array elements in Address Control Slice +#define DDR_PHY_ADR_G_REGSET_NUM_V4H 97 +//! @details Number of array elements in PI Registe +#define DDR_PI_REGSET_NUM_V4H 1381 + +//! @details The setting table of Data Slice for V4H +static const uint32_t DDR_PHY_SLICE_REGSET_V4H[DDR_PHY_SLICE_REGSET_NUM_V4H] = { +/*1000*/ 0x30020370, +/*1001*/ 0x00000000, +/*1002*/ 0x01000002, +/*1003*/ 0x00000000, +/*1004*/ 0x00000000, +/*1005*/ 0x00000000, +/*1006*/ 0x00010300, +/*1007*/ 0x04000100, +/*1008*/ 0x00010000, +/*1009*/ 0x01000000, +/*100A*/ 0x00000000, +/*100B*/ 0x00000000, +/*100C*/ 0x00010000, +/*100D*/ 0x08010000, +/*100E*/ 0x00022003, +/*100F*/ 0x00000000, +/*1010*/ 0x040F0100, +/*1011*/ 0x1404034F, +/*1012*/ 0x04040102, +/*1013*/ 0x04040404, +/*1014*/ 0x00000100, +/*1015*/ 0x00000000, +/*1016*/ 0x00000000, +/*1017*/ 0x000800C0, +/*1018*/ 0x000F18FF, +/*1019*/ 0x00000000, +/*101A*/ 0x00000001, +/*101B*/ 0x00070000, +/*101C*/ 0x0000AAAA, +/*101D*/ 0x00005555, +/*101E*/ 0x0000B5B5, +/*101F*/ 0x00004A4A, +/*1020*/ 0x00005656, +/*1021*/ 0x0000A9A9, +/*1022*/ 0x0000A9A9, +/*1023*/ 0x0000B5B5, +/*1024*/ 0x00000000, +/*1025*/ 0xBFBF0000, +/*1026*/ 0xCCCCF7F7, +/*1027*/ 0x00000000, +/*1028*/ 0x00000000, +/*1029*/ 0x00000000, +/*102A*/ 0x00080815, +/*102B*/ 0x08040000, +/*102C*/ 0x00000004, +/*102D*/ 0x00103000, +/*102E*/ 0x000C0040, +/*102F*/ 0x00200200, +/*1030*/ 0x01010000, +/*1031*/ 0x00000000, +/*1032*/ 0x00000000, +/*1033*/ 0x00000000, +/*1034*/ 0x00000000, +/*1035*/ 0x00000000, +/*1036*/ 0x00000000, +/*1037*/ 0x00000000, +/*1038*/ 0x00000000, +/*1039*/ 0x00000000, +/*103A*/ 0x00000000, +/*103B*/ 0x00000000, +/*103C*/ 0x00000000, +/*103D*/ 0x00000000, +/*103E*/ 0x00000020, +/*103F*/ 0x00000000, +/*1040*/ 0x00000000, +/*1041*/ 0x00000000, +/*1042*/ 0x00000000, +/*1043*/ 0x00000000, +/*1044*/ 0x00000000, +/*1045*/ 0x00000000, +/*1046*/ 0x00000000, +/*1047*/ 0x00000000, +/*1048*/ 0x00000000, +/*1049*/ 0x00000004, +/*104A*/ 0x001F07FF, +/*104B*/ 0x08000303, +/*104C*/ 0x10200080, +/*104D*/ 0x00000006, +/*104E*/ 0x00000401, +/*104F*/ 0x00000000, +/*1050*/ 0x20CEC201, +/*1051*/ 0x00000001, +/*1052*/ 0x00017706, +/*1053*/ 0x01007706, +/*1054*/ 0x00000000, +/*1055*/ 0x008D006D, +/*1056*/ 0x00100001, +/*1057*/ 0x03FF0100, +/*1058*/ 0x00006E01, +/*1059*/ 0x00000301, +/*105A*/ 0x00000000, +/*105B*/ 0x00000000, +/*105C*/ 0x00000000, +/*105D*/ 0x00500050, +/*105E*/ 0x00500050, +/*105F*/ 0x00500050, +/*1060*/ 0x00500050, +/*1061*/ 0x0D000050, +/*1062*/ 0x10100004, +/*1063*/ 0x06102010, +/*1064*/ 0x61619041, +/*1065*/ 0x07097000, +/*1066*/ 0x00644180, +/*1067*/ 0x00803280, +/*1068*/ 0x00808001, +/*1069*/ 0x13010101, +/*106A*/ 0x02000016, +/*106B*/ 0x10001003, +/*106C*/ 0x06093E42, +/*106D*/ 0x0F063D01, +/*106E*/ 0x011700C8, +/*106F*/ 0x04100140, +/*1070*/ 0x00000100, +/*1071*/ 0x000001D1, +/*1072*/ 0x05000068, +/*1073*/ 0x00030402, +/*1074*/ 0x01400000, +/*1075*/ 0x80800300, +/*1076*/ 0x00160010, +/*1077*/ 0x76543210, +/*1078*/ 0x00000008, +/*1079*/ 0x03010301, +/*107A*/ 0x03010301, +/*107B*/ 0x03010301, +/*107C*/ 0x03010301, +/*107D*/ 0x03010301, +/*107E*/ 0x00000000, +/*107F*/ 0x00500050, +/*1080*/ 0x00500050, +/*1081*/ 0x00500050, +/*1082*/ 0x00500050, +/*1083*/ 0x00500050, +/*1084*/ 0x00500050, +/*1085*/ 0x00500050, +/*1086*/ 0x00500050, +/*1087*/ 0x00500050, +/*1088*/ 0x00070087, +/*1089*/ 0x00000000, +/*108A*/ 0x08010007, +/*108B*/ 0x00000000, +/*108C*/ 0x20202020, +/*108D*/ 0x20202020, +/*108E*/ 0x20202020, +/*108F*/ 0x00000000, +/*1090*/ 0x00000000, +/*1091*/ 0x00000000, +/*1092*/ 0x00000000, +/*1093*/ 0x00000000, +/*1094*/ 0x00000000, +/*1095*/ 0x00000000, +/*1096*/ 0x00000000, +/*1097*/ 0x00000000, +/*1098*/ 0x00000000 +}; + +//! @details The setting table of Address Slice for V4H +static const uint32_t DDR_PHY_ADR_V_REGSET_V4H[DDR_PHY_ADR_V_REGSET_NUM_V4H] = { +/*1200*/ 0x00200030, +/*1201*/ 0x00200002, +/*1202*/ 0x76543210, +/*1203*/ 0x00010001, +/*1204*/ 0x06543210, +/*1205*/ 0x03070000, +/*1206*/ 0x00001000, +/*1207*/ 0x00000000, +/*1208*/ 0x00000000, +/*1209*/ 0x00000000, +/*120A*/ 0x00000000, +/*120B*/ 0x00000000, +/*120C*/ 0x00000000, +/*120D*/ 0x00000000, +/*120E*/ 0x00000000, +/*120F*/ 0x0000807F, +/*1210*/ 0x00000001, +/*1211*/ 0x00000003, +/*1212*/ 0x00000000, +/*1213*/ 0x000F0000, +/*1214*/ 0x030C000F, +/*1215*/ 0x00020103, +/*1216*/ 0x0000000F, +/*1217*/ 0x00000100, +/*1218*/ 0x00000000, +/*1219*/ 0x00000000, +/*121A*/ 0x00000000, +/*121B*/ 0x00000000, +/*121C*/ 0x00000000, +/*121D*/ 0x02000400, +/*121E*/ 0x0000002A, +/*121F*/ 0x00000000, +/*1220*/ 0x00000000, +/*1221*/ 0x00000000, +/*1222*/ 0x00000000, +/*1223*/ 0x00200101, +/*1224*/ 0x10002C03, +/*1225*/ 0x00000003, +/*1226*/ 0x00030240, +/*1227*/ 0x00008008, +/*1228*/ 0x00081020, +/*1229*/ 0x01200000, +/*122A*/ 0x00010001, +/*122B*/ 0x00000000, +/*122C*/ 0x00100302, +/*122D*/ 0x003E4208, +/*122E*/ 0x01400140, +/*122F*/ 0x01400140, +/*1230*/ 0x01400140, +/*1231*/ 0x01400140, +/*1232*/ 0x00000100, +/*1233*/ 0x00000100, +/*1234*/ 0x00000100, +/*1235*/ 0x00000100, +/*1236*/ 0x00000000, +/*1237*/ 0x00000000, +/*1238*/ 0x00000000, +/*1239*/ 0x00000000, +/*123A*/ 0x00020580, +/*123B*/ 0x03000040, +/*123C*/ 0x00000000 +}; +//! @details The setting table of Address Control Slice for V4H +static const uint32_t DDR_PHY_ADR_G_REGSET_V4H[DDR_PHY_ADR_G_REGSET_NUM_V4H] = { +/*1300*/ 0x00000000, +/*1301*/ 0x00000100, +/*1302*/ 0x00000001, +/*1303*/ 0x23800000, +/*1304*/ 0x00000000, +/*1305*/ 0x01000101, +/*1306*/ 0x00000000, +/*1307*/ 0x00000001, +/*1308*/ 0x00000000, +/*1309*/ 0x00000000, +/*130A*/ 0x00000000, +/*130B*/ 0x00000000, +/*130C*/ 0x00040101, +/*130D*/ 0x00000000, +/*130E*/ 0x00000000, +/*130F*/ 0x00000064, +/*1310*/ 0x00000000, +/*1311*/ 0x00000000, +/*1312*/ 0x39421B42, +/*1313*/ 0x00010124, +/*1314*/ 0x00520052, +/*1315*/ 0x00000052, +/*1316*/ 0x00000000, +/*1317*/ 0x00000000, +/*1318*/ 0x00010001, +/*1319*/ 0x00000000, +/*131A*/ 0x00000000, +/*131B*/ 0x00010001, +/*131C*/ 0x00000000, +/*131D*/ 0x00000000, +/*131E*/ 0x00010001, +/*131F*/ 0x07030102, +/*1320*/ 0x01030307, +/*1321*/ 0x00000054, +/*1322*/ 0x00004096, +/*1323*/ 0x08200820, +/*1324*/ 0x08200820, +/*1325*/ 0x08200820, +/*1326*/ 0x08200820, +/*1327*/ 0x00000820, +/*1328*/ 0x004103B8, +/*1329*/ 0x0000003F, +/*132A*/ 0x000C0006, +/*132B*/ 0x00000000, +/*132C*/ 0x000004C0, +/*132D*/ 0x00007A12, +/*132E*/ 0x00000208, +/*132F*/ 0x00000000, +/*1330*/ 0x00000000, +/*1331*/ 0x00000000, +/*1332*/ 0x00000000, +/*1333*/ 0x00000000, +/*1334*/ 0x03000000, +/*1335*/ 0x00000000, +/*1336*/ 0x00000000, +/*1337*/ 0x04102002, +/*1338*/ 0x00041020, +/*1339*/ 0x01C98C98, +/*133A*/ 0x3F400000, +/*133B*/ 0x003F3F3F, +/*133C*/ 0x00000000, +/*133D*/ 0x00000000, +/*133E*/ 0x76543210, +/*133F*/ 0x00010198, +/*1340*/ 0x00000007, +/*1341*/ 0x00000000, +/*1342*/ 0x00000000, +/*1343*/ 0x00000000, +/*1344*/ 0x00000002, +/*1345*/ 0x00000000, +/*1346*/ 0x00000000, +/*1347*/ 0x00000000, +/*1348*/ 0x01032380, +/*1349*/ 0x00000100, +/*134A*/ 0x00000000, +/*134B*/ 0x31421342, +/*134C*/ 0x00308000, +/*134D*/ 0x00000080, +/*134E*/ 0x00063F77, +/*134F*/ 0x00000006, +/*1350*/ 0x0000033F, +/*1351*/ 0x00000000, +/*1352*/ 0x0000033F, +/*1353*/ 0x00000000, +/*1354*/ 0x0000033F, +/*1355*/ 0x00000000, +/*1356*/ 0x00033F00, +/*1357*/ 0x00CC0000, +/*1358*/ 0x00033F77, +/*1359*/ 0x00000000, +/*135A*/ 0x00033F00, +/*135B*/ 0x00EE0000, +/*135C*/ 0x00033F00, +/*135D*/ 0x00EE0000, +/*135E*/ 0x00033F00, +/*135F*/ 0x00EE0000, +/*1360*/ 0x00200106 +}; +//! @details The setting table of PI Register for V4H +static const uint32_t DDR_PI_REGSET_V4H[DDR_PI_REGSET_NUM_V4H] = { +/*0800*/ 0x00000D00, +/*0801*/ 0x00010100, +/*0802*/ 0x00640004, +/*0803*/ 0x00000001, +/*0804*/ 0x00000000, +/*0805*/ 0x00000000, +/*0806*/ 0x00000000, +/*0807*/ 0x00000000, +/*0808*/ 0xFFFFFFFF, +/*0809*/ 0x02010000, +/*080A*/ 0x00000003, +/*080B*/ 0x00000005, +/*080C*/ 0x00000002, +/*080D*/ 0x00000000, +/*080E*/ 0x00000101, +/*080F*/ 0x0012080E, +/*0810*/ 0x00000000, +/*0811*/ 0x001E2C0E, +/*0812*/ 0x00000000, +/*0813*/ 0x00030300, +/*0814*/ 0x01010700, +/*0815*/ 0x00000001, +/*0816*/ 0x00000000, +/*0817*/ 0x00000000, +/*0818*/ 0x00000000, +/*0819*/ 0x00000000, +/*081A*/ 0x00000000, +/*081B*/ 0x00000000, +/*081C*/ 0x01000000, +/*081D*/ 0x00002807, +/*081E*/ 0x00000000, +/*081F*/ 0x32000300, +/*0820*/ 0x00000000, +/*0821*/ 0x00000000, +/*0822*/ 0x04022004, +/*0823*/ 0x01040100, +/*0824*/ 0x00010000, +/*0825*/ 0x00000100, +/*0826*/ 0x000000AA, +/*0827*/ 0x00000055, +/*0828*/ 0x000000B5, +/*0829*/ 0x0000004A, +/*082A*/ 0x00000056, +/*082B*/ 0x000000A9, +/*082C*/ 0x000000A9, +/*082D*/ 0x000000B5, +/*082E*/ 0x00000000, +/*082F*/ 0x01000000, +/*0830*/ 0x00030300, +/*0831*/ 0x0000001A, +/*0832*/ 0x000007D0, +/*0833*/ 0x00000300, +/*0834*/ 0x00000000, +/*0835*/ 0x00000000, +/*0836*/ 0x01000000, +/*0837*/ 0x00000101, +/*0838*/ 0x00000000, +/*0839*/ 0x00000000, +/*083A*/ 0x00000000, +/*083B*/ 0x00000200, +/*083C*/ 0x03030300, +/*083D*/ 0x01000000, +/*083E*/ 0x00000000, +/*083F*/ 0x00000100, +/*0840*/ 0x00000003, +/*0841*/ 0x001100EF, +/*0842*/ 0x01A1120B, +/*0843*/ 0x00051400, +/*0844*/ 0x001A0700, +/*0845*/ 0x001101FC, +/*0846*/ 0x00011A00, +/*0847*/ 0x00000000, +/*0848*/ 0x001F0000, +/*0849*/ 0x00000000, +/*084A*/ 0x00000000, +/*084B*/ 0x00051500, +/*084C*/ 0x001103FC, +/*084D*/ 0x00011A00, +/*084E*/ 0x00051500, +/*084F*/ 0x001102FC, +/*0850*/ 0x00011A00, +/*0851*/ 0x00001A00, +/*0852*/ 0x00000000, +/*0853*/ 0x001F0000, +/*0854*/ 0x001100FC, +/*0855*/ 0x00011A00, +/*0856*/ 0x01A1120B, +/*0857*/ 0x001A0701, +/*0858*/ 0x00000000, +/*0859*/ 0x001F0000, +/*085A*/ 0x00000000, +/*085B*/ 0x00000000, +/*085C*/ 0x001100EF, +/*085D*/ 0x01A1120B, +/*085E*/ 0x00051400, +/*085F*/ 0x01910480, +/*0860*/ 0x01821009, +/*0861*/ 0x001F0000, +/*0862*/ 0x00000000, +/*0863*/ 0x00000000, +/*0864*/ 0x00000000, +/*0865*/ 0x00000000, +/*0866*/ 0x001A0700, +/*0867*/ 0x01A11E14, +/*0868*/ 0x001101FC, +/*0869*/ 0x00211A00, +/*086A*/ 0x00051500, +/*086B*/ 0x001103FC, +/*086C*/ 0x00011A00, +/*086D*/ 0x00051500, +/*086E*/ 0x001102FC, +/*086F*/ 0x00011A00, +/*0870*/ 0x00031A00, +/*0871*/ 0x001A0701, +/*0872*/ 0x00000000, +/*0873*/ 0x001F0000, +/*0874*/ 0x00000000, +/*0875*/ 0x00000000, +/*0876*/ 0x01A11E14, +/*0877*/ 0x01A1120B, +/*0878*/ 0x00000000, +/*0879*/ 0x001F0000, +/*087A*/ 0x00000000, +/*087B*/ 0x00000000, +/*087C*/ 0x00000000, +/*087D*/ 0x00000000, +/*087E*/ 0x001100FD, +/*087F*/ 0x00012E00, +/*0880*/ 0x00051700, +/*0881*/ 0x01A1120B, +/*0882*/ 0x001A0701, +/*0883*/ 0x001F0000, +/*0884*/ 0x00000000, +/*0885*/ 0x00000000, +/*0886*/ 0x001100EF, +/*0887*/ 0x01A1120B, +/*0888*/ 0x00051400, +/*0889*/ 0x001A0700, +/*088A*/ 0x001102FD, +/*088B*/ 0x00012E00, +/*088C*/ 0x00000000, +/*088D*/ 0x001F0000, +/*088E*/ 0x00000000, +/*088F*/ 0x00000000, +/*0890*/ 0x00070700, +/*0891*/ 0x00000000, +/*0892*/ 0x01000000, +/*0893*/ 0x00000300, +/*0894*/ 0x17030000, +/*0895*/ 0x00000000, +/*0896*/ 0x00000000, +/*0897*/ 0x00000000, +/*0898*/ 0x0A0A140A, +/*0899*/ 0x10020201, +/*089A*/ 0x332A0002, +/*089B*/ 0x01010000, +/*089C*/ 0x0B000404, +/*089D*/ 0x04030308, +/*089E*/ 0x00010100, +/*089F*/ 0x02020301, +/*08A0*/ 0x01001000, +/*08A1*/ 0x00000034, +/*08A2*/ 0x00000000, +/*08A3*/ 0x00000000, +/*08A4*/ 0x00000000, +/*08A5*/ 0x00000000, +/*08A6*/ 0x55AA55AA, +/*08A7*/ 0x33CC33CC, +/*08A8*/ 0x0FF00FF0, +/*08A9*/ 0x0F0FF0F0, +/*08AA*/ 0x00008E38, +/*08AB*/ 0x00000001, +/*08AC*/ 0x00000002, +/*08AD*/ 0x00020001, +/*08AE*/ 0x00020001, +/*08AF*/ 0x02010201, +/*08B0*/ 0x0000000F, +/*08B1*/ 0x00000000, +/*08B2*/ 0x00000000, +/*08B3*/ 0x00000000, +/*08B4*/ 0x00000000, +/*08B5*/ 0x00000000, +/*08B6*/ 0x00000000, +/*08B7*/ 0x00000000, +/*08B8*/ 0x00000000, +/*08B9*/ 0x00000000, +/*08BA*/ 0x00000000, +/*08BB*/ 0xAAAAA593, +/*08BC*/ 0xA5939999, +/*08BD*/ 0x00000000, +/*08BE*/ 0x00005555, +/*08BF*/ 0x00003333, +/*08C0*/ 0x0000CCCC, +/*08C1*/ 0x00000000, +/*08C2*/ 0x0003FFFF, +/*08C3*/ 0x00003333, +/*08C4*/ 0x0000CCCC, +/*08C5*/ 0x00000000, +/*08C6*/ 0x036DB6DB, +/*08C7*/ 0x00249249, +/*08C8*/ 0x05B6DB6D, +/*08C9*/ 0x00000000, +/*08CA*/ 0x00000000, +/*08CB*/ 0x00000000, +/*08CC*/ 0x00000000, +/*08CD*/ 0x00000000, +/*08CE*/ 0x036DB6DB, +/*08CF*/ 0x00249249, +/*08D0*/ 0x05B6DB6D, +/*08D1*/ 0x00000000, +/*08D2*/ 0x00000000, +/*08D3*/ 0x00000000, +/*08D4*/ 0x00000000, +/*08D5*/ 0x00000000, +/*08D6*/ 0x01000000, +/*08D7*/ 0x00000100, +/*08D8*/ 0x00000000, +/*08D9*/ 0x00000000, +/*08DA*/ 0x00000000, +/*08DB*/ 0x00000000, +/*08DC*/ 0x00000000, +/*08DD*/ 0x00000000, +/*08DE*/ 0x00000000, +/*08DF*/ 0x00000000, +/*08E0*/ 0x00010000, +/*08E1*/ 0x00000000, +/*08E2*/ 0x00000000, +/*08E3*/ 0x00000000, +/*08E4*/ 0x00000000, +/*08E5*/ 0x00000000, +/*08E6*/ 0x00000000, +/*08E7*/ 0x00000000, +/*08E8*/ 0x00000000, +/*08E9*/ 0x00000000, +/*08EA*/ 0x00000000, +/*08EB*/ 0x00000000, +/*08EC*/ 0x00000000, +/*08ED*/ 0x00010000, +/*08EE*/ 0x00000000, +/*08EF*/ 0x00000000, +/*08F0*/ 0x00000000, +/*08F1*/ 0x00000000, +/*08F2*/ 0x00000000, +/*08F3*/ 0x00000000, +/*08F4*/ 0x00000000, +/*08F5*/ 0x00000000, +/*08F6*/ 0x00000000, +/*08F7*/ 0x00000000, +/*08F8*/ 0x00000000, +/*08F9*/ 0x00000000, +/*08FA*/ 0x00080000, +/*08FB*/ 0x00000000, +/*08FC*/ 0x00000000, +/*08FD*/ 0x00000000, +/*08FE*/ 0x00000000, +/*08FF*/ 0x00000000, +/*0900*/ 0x00000000, +/*0901*/ 0x00000000, +/*0902*/ 0x00000000, +/*0903*/ 0x00000000, +/*0904*/ 0x00000000, +/*0905*/ 0x00000000, +/*0906*/ 0x00000000, +/*0907*/ 0x00000000, +/*0908*/ 0x00000000, +/*0909*/ 0x00000000, +/*090A*/ 0x00000000, +/*090B*/ 0x00000000, +/*090C*/ 0x00000000, +/*090D*/ 0x00000000, +/*090E*/ 0x00000000, +/*090F*/ 0x01180400, +/*0910*/ 0x03020100, +/*0911*/ 0x00060504, +/*0912*/ 0x00010100, +/*0913*/ 0x00000008, +/*0914*/ 0x00080000, +/*0915*/ 0x00000001, +/*0916*/ 0x00000000, +/*0917*/ 0x0001AA00, +/*0918*/ 0x00000100, +/*0919*/ 0x00000000, +/*091A*/ 0x00010000, +/*091B*/ 0x00000000, +/*091C*/ 0x00000000, +/*091D*/ 0x00000000, +/*091E*/ 0x00000000, +/*091F*/ 0x00000000, +/*0920*/ 0x00000000, +/*0921*/ 0x00000000, +/*0922*/ 0x00000000, +/*0923*/ 0x00000000, +/*0924*/ 0x00000000, +/*0925*/ 0x00000000, +/*0926*/ 0x00000000, +/*0927*/ 0x00000000, +/*0928*/ 0x00000000, +/*0929*/ 0x00000000, +/*092A*/ 0x00000000, +/*092B*/ 0x00000000, +/*092C*/ 0x00000000, +/*092D*/ 0x00000000, +/*092E*/ 0x00000000, +/*092F*/ 0x00000000, +/*0930*/ 0x00000000, +/*0931*/ 0x00000000, +/*0932*/ 0x00000000, +/*0933*/ 0x00000000, +/*0934*/ 0x00000000, +/*0935*/ 0x00000000, +/*0936*/ 0x00000000, +/*0937*/ 0x00000000, +/*0938*/ 0x00000000, +/*0939*/ 0x00000000, +/*093A*/ 0x00000000, +/*093B*/ 0x00000000, +/*093C*/ 0x00020000, +/*093D*/ 0x00000100, +/*093E*/ 0x00010000, +/*093F*/ 0x0000000B, +/*0940*/ 0x0000001C, +/*0941*/ 0x00000100, +/*0942*/ 0x00000000, +/*0943*/ 0x00000000, +/*0944*/ 0x00000000, +/*0945*/ 0x00000000, +/*0946*/ 0x03010000, +/*0947*/ 0x01000100, +/*0948*/ 0x01020001, +/*0949*/ 0x00010300, +/*094A*/ 0x05000104, +/*094B*/ 0x01060001, +/*094C*/ 0x00010700, +/*094D*/ 0x00000000, +/*094E*/ 0x00000000, +/*094F*/ 0x00010000, +/*0950*/ 0x00000000, +/*0951*/ 0x00000000, +/*0952*/ 0x00000000, +/*0953*/ 0x00000000, +/*0954*/ 0x00000301, +/*0955*/ 0x00000000, +/*0956*/ 0x00000000, +/*0957*/ 0x01010000, +/*0958*/ 0x00000000, +/*0959*/ 0x00000200, +/*095A*/ 0x00000000, +/*095B*/ 0xB8000000, +/*095C*/ 0x010000FF, +/*095D*/ 0x0000FFE8, +/*095E*/ 0x00FFA801, +/*095F*/ 0xFFD80100, +/*0960*/ 0x00007F10, +/*0961*/ 0x00000000, +/*0962*/ 0x00000034, +/*0963*/ 0x0000003D, +/*0964*/ 0x00020079, +/*0965*/ 0x02000200, +/*0966*/ 0x02000204, +/*0967*/ 0x06000C06, +/*0968*/ 0x04040200, +/*0969*/ 0x04100804, +/*096A*/ 0x14090004, +/*096B*/ 0x1C081024, +/*096C*/ 0x0000120C, +/*096D*/ 0x00000015, +/*096E*/ 0x000000CF, +/*096F*/ 0x00000026, +/*0970*/ 0x0000017F, +/*0971*/ 0x00000130, +/*0972*/ 0x04000C2E, +/*0973*/ 0x00000404, +/*0974*/ 0x01080032, +/*0975*/ 0x01080032, +/*0976*/ 0x000F0032, +/*0977*/ 0x00000000, +/*0978*/ 0x00000000, +/*0979*/ 0x00000000, +/*097A*/ 0x00010300, +/*097B*/ 0x00010301, +/*097C*/ 0x03030000, +/*097D*/ 0x00000001, +/*097E*/ 0x00010303, +/*097F*/ 0x00030000, +/*0980*/ 0x0013000C, +/*0981*/ 0x0A060037, +/*0982*/ 0x03030526, +/*0983*/ 0x000C0032, +/*0984*/ 0x0017003D, +/*0985*/ 0x0025004B, +/*0986*/ 0x00010101, +/*0987*/ 0x0000000E, +/*0988*/ 0x00000019, +/*0989*/ 0x010000C8, +/*098A*/ 0x000F000F, +/*098B*/ 0x0007000C, +/*098C*/ 0x001A0100, +/*098D*/ 0x0015001A, +/*098E*/ 0x0100000B, +/*098F*/ 0x00C900C9, +/*0990*/ 0x005100A1, +/*0991*/ 0x29003329, +/*0992*/ 0x33290033, +/*0993*/ 0x0A070600, +/*0994*/ 0x0A07060D, +/*0995*/ 0x0D09070D, +/*0996*/ 0x000C000D, +/*0997*/ 0x00001000, +/*0998*/ 0x00000C00, +/*0999*/ 0x00001000, +/*099A*/ 0x00000C00, +/*099B*/ 0x02001000, +/*099C*/ 0x0002000E, +/*099D*/ 0x00160019, +/*099E*/ 0x1E1A00C8, +/*099F*/ 0x00100004, +/*09A0*/ 0x361C0008, +/*09A1*/ 0x00000000, +/*09A2*/ 0x0000000C, +/*09A3*/ 0x0006000C, +/*09A4*/ 0x0300361C, +/*09A5*/ 0x04001300, +/*09A6*/ 0x000D0019, +/*09A7*/ 0x0000361C, +/*09A8*/ 0x20003300, +/*09A9*/ 0x00000000, +/*09AA*/ 0x02000000, +/*09AB*/ 0x04040802, +/*09AC*/ 0x00060404, +/*09AD*/ 0x0003C34F, +/*09AE*/ 0x05022001, +/*09AF*/ 0x0203000A, +/*09B0*/ 0x04040408, +/*09B1*/ 0xC34F0604, +/*09B2*/ 0x10010005, +/*09B3*/ 0x040A0502, +/*09B4*/ 0x0A080F11, +/*09B5*/ 0x1C0A040A, +/*09B6*/ 0x0022C34F, +/*09B7*/ 0x0C0C1002, +/*09B8*/ 0x00019E0A, +/*09B9*/ 0x0000102C, +/*09BA*/ 0x000002FE, +/*09BB*/ 0x00001DEC, +/*09BC*/ 0x0000185C, +/*09BD*/ 0x0000F398, +/*09BE*/ 0x04000400, +/*09BF*/ 0x03030400, +/*09C0*/ 0x002AF803, +/*09C1*/ 0x00002AF8, +/*09C2*/ 0x0000D6D7, +/*09C3*/ 0x00000003, +/*09C4*/ 0x0000006E, +/*09C5*/ 0x00000016, +/*09C6*/ 0x00004E20, +/*09C7*/ 0x00004E20, +/*09C8*/ 0x00030D40, +/*09C9*/ 0x00000005, +/*09CA*/ 0x000000C8, +/*09CB*/ 0x00000027, +/*09CC*/ 0x00027100, +/*09CD*/ 0x00027100, +/*09CE*/ 0x00186A00, +/*09CF*/ 0x00000028, +/*09D0*/ 0x00000640, +/*09D1*/ 0x01000136, +/*09D2*/ 0x00530040, +/*09D3*/ 0x00010004, +/*09D4*/ 0x00960040, +/*09D5*/ 0x00010004, +/*09D6*/ 0x04B00040, +/*09D7*/ 0x00000318, +/*09D8*/ 0x00280005, +/*09D9*/ 0x05040404, +/*09DA*/ 0x00070603, +/*09DB*/ 0x06030503, +/*09DC*/ 0x0503000D, +/*09DD*/ 0x00640603, +/*09DE*/ 0x06040608, +/*09DF*/ 0x00040604, +/*09E0*/ 0x00260015, +/*09E1*/ 0x01050130, +/*09E2*/ 0x01000100, +/*09E3*/ 0x00020201, +/*09E4*/ 0x04040000, +/*09E5*/ 0x01010104, +/*09E6*/ 0x03020302, +/*09E7*/ 0x00000100, +/*09E8*/ 0x02020101, +/*09E9*/ 0x00000000, +/*09EA*/ 0x09910260, +/*09EB*/ 0x11911600, +/*09EC*/ 0x19A21009, +/*09ED*/ 0x19A10100, +/*09EE*/ 0x19A10201, +/*09EF*/ 0x19A10302, +/*09F0*/ 0x19A10A03, +/*09F1*/ 0x19A10B04, +/*09F2*/ 0x19A10C05, +/*09F3*/ 0x19A10E07, +/*09F4*/ 0x19A10F08, +/*09F5*/ 0x19A1110A, +/*09F6*/ 0x19A1120B, +/*09F7*/ 0x19A1130C, +/*09F8*/ 0x19A1140D, +/*09F9*/ 0x19A00C00, +/*09FA*/ 0x199F0000, +/*09FB*/ 0x199F0000, +/*09FC*/ 0x199F0000, +/*09FD*/ 0x199F0000, +/*09FE*/ 0x01910300, +/*09FF*/ 0x01A21009, +/*0A00*/ 0x019F0000, +/*0A01*/ 0x019F0000, +/*0A02*/ 0x019F0000, +/*0A03*/ 0x019F0000, +/*0A04*/ 0x001140BF, +/*0A05*/ 0x01811009, +/*0A06*/ 0x01850400, +/*0A07*/ 0x01A10C05, +/*0A08*/ 0x01850300, +/*0A09*/ 0x01A10C11, +/*0A0A*/ 0x01850300, +/*0A0B*/ 0x001100BF, +/*0A0C*/ 0x01811009, +/*0A0D*/ 0x01850500, +/*0A0E*/ 0x019F0000, +/*0A0F*/ 0x019F0000, +/*0A10*/ 0x01510001, +/*0A11*/ 0x01D102A0, +/*0A12*/ 0x01E21009, +/*0A13*/ 0x00051900, +/*0A14*/ 0x019F0000, +/*0A15*/ 0x019F0000, +/*0A16*/ 0x019F0000, +/*0A17*/ 0x019F0000, +/*0A18*/ 0x019F0000, +/*0A19*/ 0x019F0000, +/*0A1A*/ 0x019F0000, +/*0A1B*/ 0x019F0000, +/*0A1C*/ 0x019F0000, +/*0A1D*/ 0x019F0000, +/*0A1E*/ 0x019F0000, +/*0A1F*/ 0x01510001, +/*0A20*/ 0x01D10290, +/*0A21*/ 0x01E21009, +/*0A22*/ 0x01510001, +/*0A23*/ 0x01D10000, +/*0A24*/ 0x01E21009, +/*0A25*/ 0x00051800, +/*0A26*/ 0x019F0000, +/*0A27*/ 0x019F0000, +/*0A28*/ 0x019F0000, +/*0A29*/ 0x019F0000, +/*0A2A*/ 0x019F0000, +/*0A2B*/ 0x019F0000, +/*0A2C*/ 0x019F0000, +/*0A2D*/ 0x019F0000, +/*0A2E*/ 0x0011008F, +/*0A2F*/ 0x00910000, +/*0A30*/ 0x01811009, +/*0A31*/ 0x01910040, +/*0A32*/ 0x01A21009, +/*0A33*/ 0x019F0000, +/*0A34*/ 0x01911000, +/*0A35*/ 0x01A21009, +/*0A36*/ 0x01A10100, +/*0A37*/ 0x01A10201, +/*0A38*/ 0x01A10302, +/*0A39*/ 0x01A10A03, +/*0A3A*/ 0x01A10B04, +/*0A3B*/ 0x01A10C05, +/*0A3C*/ 0x01A10E07, +/*0A3D*/ 0x01A10F08, +/*0A3E*/ 0x01A1110A, +/*0A3F*/ 0x01A1120B, +/*0A40*/ 0x01A1130C, +/*0A41*/ 0x01A1140D, +/*0A42*/ 0x01A00C00, +/*0A43*/ 0x01910800, +/*0A44*/ 0x01A21009, +/*0A45*/ 0x019F0000, +/*0A46*/ 0x019F0000, +/*0A47*/ 0x019F0000, +/*0A48*/ 0x0101017F, +/*0A49*/ 0x00010101, +/*0A4A*/ 0x00000000, +/*0A4B*/ 0x00000000, +/*0A4C*/ 0x00000000, +/*0A4D*/ 0x00000000, +/*0A4E*/ 0x01000000, +/*0A4F*/ 0x01000101, +/*0A50*/ 0x00000000, +/*0A51*/ 0x00000000, +/*0A52*/ 0x00050000, +/*0A53*/ 0x00070100, +/*0A54*/ 0x000F0200, +/*0A55*/ 0x00000000, +/*0A56*/ 0x01A10100, +/*0A57*/ 0x01A10201, +/*0A58*/ 0x01A10302, +/*0A59*/ 0x01A00B04, +/*0A5A*/ 0x00210D06, +/*0A5B*/ 0x01A1110A, +/*0A5C*/ 0x01A1140D, +/*0A5D*/ 0x00098000, +/*0A5E*/ 0x019F0000, +/*0A5F*/ 0x019F0000, +/*0A60*/ 0x019F0000, +/*0A61*/ 0x019F0000, +/*0A62*/ 0x019F0000, +/*0A63*/ 0x019F0000, +/*0A64*/ 0x019F0000, +/*0A65*/ 0x019F0000, +/*0A66*/ 0x019F0000, +/*0A67*/ 0x019F0000, +/*0A68*/ 0x019F0000, +/*0A69*/ 0x019F0000, +/*0A6A*/ 0x019F0000, +/*0A6B*/ 0x019F0000, +/*0A6C*/ 0x019F0000, +/*0A6D*/ 0x019F0000, +/*0A6E*/ 0x019F0000, +/*0A6F*/ 0x019F0000, +/*0A70*/ 0x019F0000, +/*0A71*/ 0x019F0000, +/*0A72*/ 0x019F0000, +/*0A73*/ 0x019F0000, +/*0A74*/ 0x019F0000, +/*0A75*/ 0x019F0000, +/*0A76*/ 0x019F0000, +/*0A77*/ 0x019F0000, +/*0A78*/ 0x019F0000, +/*0A79*/ 0x019F0000, +/*0A7A*/ 0x019F0000, +/*0A7B*/ 0x019F0000, +/*0A7C*/ 0x019F0000, +/*0A7D*/ 0x019F0000, +/*0A7E*/ 0x019F0000, +/*0A7F*/ 0x019F0000, +/*0A80*/ 0x019F0000, +/*0A81*/ 0x019F0000, +/*0A82*/ 0x019F0000, +/*0A83*/ 0x019F0000, +/*0A84*/ 0x019F0000, +/*0A85*/ 0x019F0000, +/*0A86*/ 0x019F0000, +/*0A87*/ 0x019F0000, +/*0A88*/ 0x019F0000, +/*0A89*/ 0x019F0000, +/*0A8A*/ 0x019F0000, +/*0A8B*/ 0x019F0000, +/*0A8C*/ 0x019F0000, +/*0A8D*/ 0x019F0000, +/*0A8E*/ 0x019F0000, +/*0A8F*/ 0x019F0000, +/*0A90*/ 0x019F0000, +/*0A91*/ 0x019F0000, +/*0A92*/ 0x01A10100, +/*0A93*/ 0x01A10201, +/*0A94*/ 0x01A10302, +/*0A95*/ 0x01A10A03, +/*0A96*/ 0x01A10B04, +/*0A97*/ 0x00210D06, +/*0A98*/ 0x01A1110A, +/*0A99*/ 0x00000000, +/*0A9A*/ 0x01A1140D, +/*0A9B*/ 0x00000000, +/*0A9C*/ 0x00000000, +/*0A9D*/ 0x00000000, +/*0A9E*/ 0x01A1120B, +/*0A9F*/ 0x000A0000, +/*0AA0*/ 0x001F0000, +/*0AA1*/ 0x001F0000, +/*0AA2*/ 0x001F0000, +/*0AA3*/ 0x001F0000, +/*0AA4*/ 0x001F0000, +/*0AA5*/ 0x001F0000, +/*0AA6*/ 0x000A0000, +/*0AA7*/ 0x01061300, +/*0AA8*/ 0x00000000, +/*0AA9*/ 0x00000000, +/*0AAA*/ 0x00061180, +/*0AAB*/ 0x000612C0, +/*0AAC*/ 0x00000000, +/*0AAD*/ 0x00000000, +/*0AAE*/ 0x001F0000, +/*0AAF*/ 0x00000000, +/*0AB0*/ 0x00000000, +/*0AB1*/ 0x00000000, +/*0AB2*/ 0x00000000, +/*0AB3*/ 0x00000000, +/*0AB4*/ 0x00000000, +/*0AB5*/ 0x00000000, +/*0AB6*/ 0x00000000, +/*0AB7*/ 0x00000000, +/*0AB8*/ 0x00000000, +/*0AB9*/ 0x00000000, +/*0ABA*/ 0x01811009, +/*0ABB*/ 0x0011EFAF, +/*0ABC*/ 0x01A1120B, +/*0ABD*/ 0x001F0000, +/*0ABE*/ 0x001F0000, +/*0ABF*/ 0x001F0000, +/*0AC0*/ 0x001F0000, +/*0AC1*/ 0x001F0000, +/*0AC2*/ 0x001F0000, +/*0AC3*/ 0x001100BF, +/*0AC4*/ 0x01A1120B, +/*0AC5*/ 0x080D0000, +/*0AC6*/ 0x001F0000, +/*0AC7*/ 0x001F0000, +/*0AC8*/ 0x001F0000, +/*0AC9*/ 0x080C0000, +/*0ACA*/ 0x001F0000, +/*0ACB*/ 0x001F0000, +/*0ACC*/ 0x001F0000, +/*0ACD*/ 0x001F0000, +/*0ACE*/ 0x001F0000, +/*0ACF*/ 0x001F0000, +/*0AD0*/ 0x001F0000, +/*0AD1*/ 0x001F0000, +/*0AD2*/ 0x001F0200, +/*0AD3*/ 0x001F0200, +/*0AD4*/ 0x001F0200, +/*0AD5*/ 0x001F0200, +/*0AD6*/ 0x001F0200, +/*0AD7*/ 0x001F0200, +/*0AD8*/ 0x001F0200, +/*0AD9*/ 0x001F0200, +/*0ADA*/ 0x001F0200, +/*0ADB*/ 0x001F0200, +/*0ADC*/ 0x001F0200, +/*0ADD*/ 0x001F0200, +/*0ADE*/ 0x001100EF, +/*0ADF*/ 0x01A1120B, +/*0AE0*/ 0x001F0000, +/*0AE1*/ 0x00000000, +/*0AE2*/ 0x00000000, +/*0AE3*/ 0x00000000, +/*0AE4*/ 0x00000000, +/*0AE5*/ 0x00000000, +/*0AE6*/ 0x00000000, +/*0AE7*/ 0x00000000, +/*0AE8*/ 0x00000000, +/*0AE9*/ 0x00000000, +/*0AEA*/ 0x00000000, +/*0AEB*/ 0x00000000, +/*0AEC*/ 0x00000000, +/*0AED*/ 0x00000000, +/*0AEE*/ 0x01A1120B, +/*0AEF*/ 0x001F0000, +/*0AF0*/ 0x00000000, +/*0AF1*/ 0x00000000, +/*0AF2*/ 0x00000000, +/*0AF3*/ 0x00000000, +/*0AF4*/ 0x00000000, +/*0AF5*/ 0x00000000, +/*0AF6*/ 0x00000000, +/*0AF7*/ 0x00000000, +/*0AF8*/ 0x00000000, +/*0AF9*/ 0x00000000, +/*0AFA*/ 0x00000000, +/*0AFB*/ 0x00000000, +/*0AFC*/ 0x00000000, +/*0AFD*/ 0x00000000, +/*0AFE*/ 0x001100EF, +/*0AFF*/ 0x01A1120B, +/*0B00*/ 0x001F0000, +/*0B01*/ 0x00000000, +/*0B02*/ 0x00000000, +/*0B03*/ 0x00000000, +/*0B04*/ 0x00000000, +/*0B05*/ 0x00000000, +/*0B06*/ 0x00000000, +/*0B07*/ 0x00000000, +/*0B08*/ 0x00000000, +/*0B09*/ 0x00000000, +/*0B0A*/ 0x00000000, +/*0B0B*/ 0x00000000, +/*0B0C*/ 0x00000000, +/*0B0D*/ 0x00000000, +/*0B0E*/ 0x00211F14, +/*0B0F*/ 0x00212014, +/*0B10*/ 0x00212116, +/*0B11*/ 0x00212217, +/*0B12*/ 0x001F0000, +/*0B13*/ 0x00000000, +/*0B14*/ 0x00000000, +/*0B15*/ 0x00000000, +/*0B16*/ 0x00000000, +/*0B17*/ 0x00000000, +/*0B18*/ 0x001A85FF, +/*0B19*/ 0x00051E00, +/*0B1A*/ 0x001F0000, +/*0B1B*/ 0x00000000, +/*0B1C*/ 0x00211F14, +/*0B1D*/ 0x00212015, +/*0B1E*/ 0x00212116, +/*0B1F*/ 0x00212217, +/*0B20*/ 0x01A1120B, +/*0B21*/ 0x001F0000, +/*0B22*/ 0x00000000, +/*0B23*/ 0x00000000, +/*0B24*/ 0x00000000, +/*0B25*/ 0x00000000, +/*0B26*/ 0x0031FFBF, +/*0B27*/ 0x01A11009, +/*0B28*/ 0x01A10E07, +/*0B29*/ 0x01A10F08, +/*0B2A*/ 0x003100BF, +/*0B2B*/ 0x01A11009, +/*0B2C*/ 0x00051800, +/*0B2D*/ 0x003F0000, +/*0B2E*/ 0x003F0000, +/*0B2F*/ 0x003F0000, +/*0B30*/ 0x003F0000, +/*0B31*/ 0x003F0000, +/*0B32*/ 0x003F0000, +/*0B33*/ 0x003F0000, +/*0B34*/ 0x003F0000, +/*0B35*/ 0x003F0000, +/*0B36*/ 0x0031FFBF, +/*0B37*/ 0x01A11009, +/*0B38*/ 0x01A10E07, +/*0B39*/ 0x01A10F08, +/*0B3A*/ 0x003100BF, +/*0B3B*/ 0x01A11009, +/*0B3C*/ 0x00051800, +/*0B3D*/ 0x003F0000, +/*0B3E*/ 0x003F0000, +/*0B3F*/ 0x003F0000, +/*0B40*/ 0x003F0000, +/*0B41*/ 0x003F0000, +/*0B42*/ 0x003F0000, +/*0B43*/ 0x003F0000, +/*0B44*/ 0x003F0000, +/*0B45*/ 0x003F0000, +/*0B46*/ 0x08084340, +/*0B47*/ 0x0011FFFF, +/*0B48*/ 0x2011FFFB, +/*0B49*/ 0x00012E00, +/*0B4A*/ 0x001100EF, +/*0B4B*/ 0x01A1120B, +/*0B4C*/ 0x001F0000, +/*0B4D*/ 0x001F0000, +/*0B4E*/ 0x001F0000, +/*0B4F*/ 0x001F0000, +/*0B50*/ 0x001F0000, +/*0B51*/ 0x001F0000, +/*0B52*/ 0x001F0000, +/*0B53*/ 0x001F0000, +/*0B54*/ 0x001F0000, +/*0B55*/ 0x001F0000, +/*0B56*/ 0x001F0000, +/*0B57*/ 0x001F0000, +/*0B58*/ 0x001F0000, +/*0B59*/ 0x001F0000, +/*0B5A*/ 0x001F0000, +/*0B5B*/ 0x001F0000, +/*0B5C*/ 0x001F0000, +/*0B5D*/ 0x001F0000, +/*0B5E*/ 0x083E4340, +/*0B5F*/ 0x00212E00, +/*0B60*/ 0x01A1120B, +/*0B61*/ 0x003F0000, +/*0B62*/ 0x003F0000, +/*0B63*/ 0x003F0000, +/*0B64*/ 0x003F0000, +/*0B65*/ 0x003F0000, +/*0B66*/ 0x003F0000, +/*0B67*/ 0x08201020, +/*0B68*/ 0x28100020, +/*0B69*/ 0x08083020, +/*0B6A*/ 0x08400020, +/*0B6B*/ 0x08402020, +/*0B6C*/ 0x08483020, +/*0B6D*/ 0x10083020, +/*0B6E*/ 0x20180020, +/*0B6F*/ 0x30480020, +/*0B70*/ 0x78880020, +/*0B71*/ 0x488010E0, +/*0B72*/ 0x494B0000, +/*0B73*/ 0x49089080, +/*0B74*/ 0x49080000, +/*0B75*/ 0x490011C0, +/*0B76*/ 0x0A000020, +/*0B77*/ 0x08000020, +/*0B78*/ 0x08000020, +/*0B79*/ 0x08000020, +/*0B7A*/ 0x08000020, +/*0B7B*/ 0x08000020, +/*0B7C*/ 0x08000020, +/*0B7D*/ 0x08000020, +/*0B7E*/ 0x08000020, +/*0B7F*/ 0x08000020, +/*0B80*/ 0x08000020, +/*0B81*/ 0x08000020, +/*0B82*/ 0x08000020, +/*0B83*/ 0x08000020, +/*0B84*/ 0x08000020, +/*0B85*/ 0x08000020, +/*0B86*/ 0x08000020, +/*0B87*/ 0x08000020, +/*0B88*/ 0x08000020, +/*0B89*/ 0x08000020, +/*0B8A*/ 0x08000020, +/*0B8B*/ 0x08000020, +/*0B8C*/ 0x08000020, +/*0B8D*/ 0x08000020, +/*0B8E*/ 0x08000020, +/*0B8F*/ 0x08000020, +/*0B90*/ 0x08000020, +/*0B91*/ 0x08000020, +/*0B92*/ 0x08000020, +/*0B93*/ 0x08000020, +/*0B94*/ 0x001100FF, +/*0B95*/ 0x01810302, +/*0B96*/ 0x001100DF, +/*0B97*/ 0x00010D06, +/*0B98*/ 0x001100EF, +/*0B99*/ 0x01A1120B, +/*0B9A*/ 0x001F0000, +/*0B9B*/ 0x001F0000, +/*0B9C*/ 0x001F0000, +/*0B9D*/ 0x001F0000, +/*0B9E*/ 0x001F0000, +/*0B9F*/ 0x001F0000, +/*0BA0*/ 0x001F0000, +/*0BA1*/ 0x001F0000, +/*0BA2*/ 0x001F0000, +/*0BA3*/ 0x001F0000, +/*0BA4*/ 0x00010D06, +/*0BA5*/ 0x01810302, +/*0BA6*/ 0x0181160E, +/*0BA7*/ 0x001F0000, +/*0BA8*/ 0x001F0000, +/*0BA9*/ 0x001F0000, +/*0BAA*/ 0x001F0000, +/*0BAB*/ 0x001F0000, +/*0BAC*/ 0x081A52FD, +/*0BAD*/ 0x001A12FF, +/*0BAE*/ 0x00051A00, +/*0BAF*/ 0x001A13FF, +/*0BB0*/ 0x00051B00, +/*0BB1*/ 0x001F13FF, +/*0BB2*/ 0x081A52FD, +/*0BB3*/ 0x001A12FF, +/*0BB4*/ 0x00051A00, +/*0BB5*/ 0x001A13FF, +/*0BB6*/ 0x00051B00, +/*0BB7*/ 0x001F13FF, +/*0BB8*/ 0x081A52FD, +/*0BB9*/ 0x001A12FF, +/*0BBA*/ 0x00051A00, +/*0BBB*/ 0x001A13FF, +/*0BBC*/ 0x00051B00, +/*0BBD*/ 0x001F13FF, +/*0BBE*/ 0x00032300, +/*0BBF*/ 0x00032400, +/*0BC0*/ 0x001F0000, +/*0BC1*/ 0x001F0000, +/*0BC2*/ 0x00800000, +/*0BC3*/ 0x0031FFBF, +/*0BC4*/ 0x01A11009, +/*0BC5*/ 0x01A10E07, +/*0BC6*/ 0x01A10F08, +/*0BC7*/ 0x003100BF, +/*0BC8*/ 0x01A11009, +/*0BC9*/ 0x00051800, +/*0BCA*/ 0x003F0000, +/*0BCB*/ 0x003F0000, +/*0BCC*/ 0x003F0000, +/*0BCD*/ 0x003F0000, +/*0BCE*/ 0x003F0000, +/*0BCF*/ 0x003F0000, +/*0BD0*/ 0x003F0000, +/*0BD1*/ 0x003F0000, +/*0BD2*/ 0x00800000, +/*0BD3*/ 0x0031FFBF, +/*0BD4*/ 0x01A11009, +/*0BD5*/ 0x01A10E07, +/*0BD6*/ 0x01A10F08, +/*0BD7*/ 0x003100BF, +/*0BD8*/ 0x01A11009, +/*0BD9*/ 0x00051800, +/*0BDA*/ 0x003F0000, +/*0BDB*/ 0x003F0000, +/*0BDC*/ 0x003F0000, +/*0BDD*/ 0x003F0000, +/*0BDE*/ 0x003F0000, +/*0BDF*/ 0x003F0000, +/*0BE0*/ 0x003F0000, +/*0BE1*/ 0x003F0000, +/*0BE2*/ 0x081100DF, +/*0BE3*/ 0x08010D06, +/*0BE4*/ 0x0011000F, +/*0BE5*/ 0x0181160E, +/*0BE6*/ 0x001100EF, +/*0BE7*/ 0x01A1120B, +/*0BE8*/ 0x001F0000, +/*0BE9*/ 0x001F0000, +/*0BEA*/ 0x001F0000, +/*0BEB*/ 0x009C0000, +/*0BEC*/ 0x08010D06, +/*0BED*/ 0x0181160E, +/*0BEE*/ 0x01A1120B, +/*0BEF*/ 0x001F0000, +/*0BF0*/ 0x001F0000, +/*0BF1*/ 0x001F0000, +/*0BF2*/ 0x00000000, +/*0BF3*/ 0x00000000, +/*0BF4*/ 0x00000000, +/*0BF5*/ 0x00000000, +/*0BF6*/ 0x00000000, +/*0BF7*/ 0x00000000, +/*0BF8*/ 0x00000000, +/*0BF9*/ 0x00000000, +/*0BFA*/ 0x00000000, +/*0BFB*/ 0x11910048, +/*0BFC*/ 0x09910060, +/*0BFD*/ 0x19A21009, +/*0BFE*/ 0x19A10100, +/*0BFF*/ 0x19A10201, +/*0C00*/ 0x19A10302, +/*0C01*/ 0x19A10A03, +/*0C02*/ 0x19A10B04, +/*0C03*/ 0x18051C00, +/*0C04*/ 0x19A1110A, +/*0C05*/ 0x19A1120B, +/*0C06*/ 0x19A1130C, +/*0C07*/ 0x19A1140D, +/*0C08*/ 0x19A1160E, +/*0C09*/ 0x181140BF, +/*0C0A*/ 0x19A11009, +/*0C0B*/ 0x19A10C05, +/*0C0C*/ 0x19A00C00, +/*0C0D*/ 0x19A10E07, +/*0C0E*/ 0x19A10F08, +/*0C0F*/ 0x19910280, +/*0C10*/ 0x19A21009, +/*0C11*/ 0x18051000, +/*0C12*/ 0x18861101, +/*0C13*/ 0x181F0000, +/*0C14*/ 0x18000000, +/*0C15*/ 0x18000000, +/*0C16*/ 0x18000000, +/*0C17*/ 0x18000000, +/*0C18*/ 0x18000000, +/*0C19*/ 0x18000000, +/*0C1A*/ 0x18000000, +/*0C1B*/ 0x18000000, +/*0C1C*/ 0x18000000, +/*0C1D*/ 0x18000000, +/*0C1E*/ 0x18000000, +/*0C1F*/ 0x18000000, +/*0C20*/ 0x18000000, +/*0C21*/ 0x18000000, +/*0C22*/ 0x18000000, +/*0C23*/ 0x18861100, +/*0C24*/ 0x19A11009, +/*0C25*/ 0x101B0001, +/*0C26*/ 0x181B0100, +/*0C27*/ 0x18000500, +/*0C28*/ 0x181B0200, +/*0C29*/ 0x00000000, +/*0C2A*/ 0x181B0600, +/*0C2B*/ 0x181B0C00, +/*0C2C*/ 0x181B0100, +/*0C2D*/ 0x181B0200, +/*0C2E*/ 0x181B0300, +/*0C2F*/ 0x181B0400, +/*0C30*/ 0x181F0000, +/*0C31*/ 0x18000000, +/*0C32*/ 0x18000000, +/*0C33*/ 0x18000000, +/*0C34*/ 0x18000000, +/*0C35*/ 0x18000000, +/*0C36*/ 0x18000000, +/*0C37*/ 0x18000000, +/*0C38*/ 0x18000000, +/*0C39*/ 0x18000000, +/*0C3A*/ 0x18000000, +/*0C3B*/ 0x18000000, +/*0C3C*/ 0x18000000, +/*0C3D*/ 0x18000000, +/*0C3E*/ 0x18000000, +/*0C3F*/ 0x18000000, +/*0C40*/ 0x18000000, +/*0C41*/ 0x004B1040, +/*0C42*/ 0x001011C0, +/*0C43*/ 0x00089080, +/*0C44*/ 0x000811C0, +/*0C45*/ 0x040811C0, +/*0C46*/ 0x02000000, +/*0C47*/ 0x00000000, +/*0C48*/ 0x00000000, +/*0C49*/ 0x00000000, +/*0C4A*/ 0x00000000, +/*0C4B*/ 0x00000000, +/*0C4C*/ 0x00000000, +/*0C4D*/ 0x00000000, +/*0C4E*/ 0x00000000, +/*0C4F*/ 0x00000000, +/*0C50*/ 0x00000000, +/*0C51*/ 0x00000000, +/*0C52*/ 0x00000000, +/*0C53*/ 0x00000000, +/*0C54*/ 0x00000000, +/*0C55*/ 0x00000000, +/*0C56*/ 0x00000000, +/*0C57*/ 0x5F407FAA, +/*0C58*/ 0x007B776F, +/*0C59*/ 0x4AB555AA, +/*0C5A*/ 0xB5A9A956, +/*0C5B*/ 0x9F80BFAA, +/*0C5C*/ 0x00BBB7AF, +/*0C5D*/ 0x00000000, +/*0C5E*/ 0x00000000, +/*0C5F*/ 0x00000000, +/*0C60*/ 0x00000000, +/*0C61*/ 0x00000000, +/*0C62*/ 0x00000000, +/*0C63*/ 0x00000000, +/*0C64*/ 0x00000000, +/*0C65*/ 0x00002AF8, +/*0C66*/ 0x0000D6D7, +/*0C67*/ 0x0000006E, +/*0C68*/ 0x00000000, +/*0C69*/ 0x00000000, +/*0C6A*/ 0x00000000, +/*0C6B*/ 0x00000000, +/*0C6C*/ 0x00000000, +/*0C6D*/ 0x00000000, +/*0C6E*/ 0x00000000, +/*0C6F*/ 0x00000000, +/*0C70*/ 0x00000000, +/*0C71*/ 0x00000000, +/*0C72*/ 0x00000000, +/*0C73*/ 0x00000000, +/*0C74*/ 0x00000000, +/*0C75*/ 0x0000000E, +/*0C76*/ 0x00000019, +/*0C77*/ 0x000000C8, +/*0C78*/ 0x00000001, +/*0C79*/ 0x00000001, +/*0C7A*/ 0x00000003, +/*0C7B*/ 0x00000007, +/*0C7C*/ 0x00000007, +/*0C7D*/ 0x00000009, +/*0C7E*/ 0x00000001, +/*0C7F*/ 0x00000001, +/*0C80*/ 0x00000003, +/*0C81*/ 0x00000001, +/*0C82*/ 0x00000001, +/*0C83*/ 0x00000003, +/*0C84*/ 0x0000006E, +/*0C85*/ 0x000000C8, +/*0C86*/ 0x00000640, +/*0C87*/ 0x00000001, +/*0C88*/ 0x00000001, +/*0C89*/ 0x00000003, +/*0C8A*/ 0x00000002, +/*0C8B*/ 0x00000004, +/*0C8C*/ 0x0000001C, +/*0C8D*/ 0x00000007, +/*0C8E*/ 0x0000000B, +/*0C8F*/ 0x00000051, +/*0C90*/ 0x0000000C, +/*0C91*/ 0x00000015, +/*0C92*/ 0x000000A1, +/*0C93*/ 0x00000003, +/*0C94*/ 0x00000000, +/*0C95*/ 0x0000000C, +/*0C96*/ 0x00000000, +/*0C97*/ 0x00000000, +/*0C98*/ 0x00000000, +/*0C99*/ 0x0000000F, +/*0C9A*/ 0x0000000F, +/*0C9B*/ 0x0000000F, +/*0C9C*/ 0x00002AF9, +/*0C9D*/ 0x00002AF9, +/*0C9E*/ 0x00002AF9, +/*0C9F*/ 0x00000034, +/*0CA0*/ 0x0000001E, +/*0CA1*/ 0x0000003C, +/*0CA2*/ 0x00000000, +/*0CA3*/ 0x00000000, +/*0CA4*/ 0x00000000, +/*0CA5*/ 0x00000000, +/*0CA6*/ 0x00000000, +/*0CA7*/ 0x00000000, +/*0CA8*/ 0x00000000, +/*0CA9*/ 0x00000000, +/*0CAA*/ 0x00000000, +/*0CAB*/ 0x00000000, +/*0CAC*/ 0x00000000, +/*0CAD*/ 0x00000000, +/*0CAE*/ 0x00000000, +/*0CAF*/ 0x00000000, +/*0CB0*/ 0x00000000, +/*0CB1*/ 0x00000000, +/*0CB2*/ 0x00000000, +/*0CB3*/ 0x00000000, +/*0CB4*/ 0x00000000, +/*0CB5*/ 0x00000000, +/*0CB6*/ 0x00000000, +/*0CB7*/ 0x00000000, +/*0CB8*/ 0x00000000, +/*0CB9*/ 0x00000000, +/*0CBA*/ 0x00000000, +/*0CBB*/ 0x00000000, +/*0CBC*/ 0x00000000, +/*0CBD*/ 0x00000000, +/*0CBE*/ 0x00000000, +/*0CBF*/ 0x00000000, +/*0CC0*/ 0x00000000, +/*0CC1*/ 0x00000000, +/*0CC2*/ 0x00000000, +/*0CC3*/ 0x00000000, +/*0CC4*/ 0x00000000, +/*0CC5*/ 0x00000000, +/*0CC6*/ 0x00000000, +/*0CC7*/ 0x00000000, +/*0CC8*/ 0x00000000, +/*0CC9*/ 0x00000000, +/*0CCA*/ 0x00000000, +/*0CCB*/ 0x00000000, +/*0CCC*/ 0x00000000, +/*0CCD*/ 0x00000000, +/*0CCE*/ 0x00000000, +/*0CCF*/ 0x00000000, +/*0CD0*/ 0x00000000, +/*0CD1*/ 0x00000000, +/*0CD2*/ 0x00000000, +/*0CD3*/ 0x00000000, +/*0CD4*/ 0x000000C0, +/*0CD5*/ 0x00000000, +/*0CD6*/ 0x00000000, +/*0CD7*/ 0x55550000, +/*0CD8*/ 0x00003C5A, +/*0CD9*/ 0x00000000, +/*0CDA*/ 0x00000000, +/*0CDB*/ 0x00000000, +/*0CDC*/ 0x00000000, +/*0CDD*/ 0x00000000, +/*0CDE*/ 0x00000000, +/*0CDF*/ 0x00000000, +/*0CE0*/ 0x00000000, +/*0CE1*/ 0x00000000, +/*0CE2*/ 0x00000000, +/*0CE3*/ 0x00000000, +/*0CE4*/ 0x00000000, +/*0CE5*/ 0x00000000, +/*0CE6*/ 0x00000000, +/*0CE7*/ 0x00000000, +/*0CE8*/ 0x00000000, +/*0CE9*/ 0x00000000, +/*0CEA*/ 0x00000000, +/*0CEB*/ 0x00000000, +/*0CEC*/ 0x00000000, +/*0CED*/ 0x00000000, +/*0CEE*/ 0x00000000, +/*0CEF*/ 0x00000000, +/*0CF0*/ 0x00000000, +/*0CF1*/ 0x00000000, +/*0CF2*/ 0x00000000, +/*0CF3*/ 0x00000000, +/*0CF4*/ 0x00000000, +/*0CF5*/ 0x00000000, +/*0CF6*/ 0x00000000, +/*0CF7*/ 0x00000000, +/*0CF8*/ 0x00000000, +/*0CF9*/ 0x00000000, +/*0CFA*/ 0x00000000, +/*0CFB*/ 0x00000000, +/*0CFC*/ 0x00000000, +/*0CFD*/ 0x00000000, +/*0CFE*/ 0x00000000, +/*0CFF*/ 0x00000000, +/*0D00*/ 0x00000000, +/*0D01*/ 0x00000000, +/*0D02*/ 0x00000000, +/*0D03*/ 0x00000000, +/*0D04*/ 0x00000000, +/*0D05*/ 0x00000000, +/*0D06*/ 0x00000000, +/*0D07*/ 0x00000000, +/*0D08*/ 0x00000000, +/*0D09*/ 0x00000000, +/*0D0A*/ 0x00000000, +/*0D0B*/ 0x00D60000, +/*0D0C*/ 0x50005000, +/*0D0D*/ 0x803E0050, +/*0D0E*/ 0x00000200, +/*0D0F*/ 0x00000000, +/*0D10*/ 0x00000000, +/*0D11*/ 0x00007800, +/*0D12*/ 0x00000000, +/*0D13*/ 0x00000000, +/*0D14*/ 0x00000000, +/*0D15*/ 0x00C61110, +/*0D16*/ 0x2C002834, +/*0D17*/ 0x0C06002C, +/*0D18*/ 0x00000200, +/*0D19*/ 0x00000000, +/*0D1A*/ 0x00000000, +/*0D1B*/ 0x00007800, +/*0D1C*/ 0x00000000, +/*0D1D*/ 0x00000000, +/*0D1E*/ 0x00000000, +/*0D1F*/ 0x00C6BBB0, +/*0D20*/ 0x2C002834, +/*0D21*/ 0x0C06002C, +/*0D22*/ 0x00000200, +/*0D23*/ 0x00000000, +/*0D24*/ 0x00000000, +/*0D25*/ 0x00007800, +/*0D26*/ 0x00000000, +/*0D27*/ 0x00000000, +/*0D28*/ 0x00000000, +/*0D29*/ 0x00D60000, +/*0D2A*/ 0x50005000, +/*0D2B*/ 0x803E0050, +/*0D2C*/ 0x00000200, +/*0D2D*/ 0x00000000, +/*0D2E*/ 0x00000000, +/*0D2F*/ 0x00007800, +/*0D30*/ 0x00000000, +/*0D31*/ 0x00000000, +/*0D32*/ 0x00000000, +/*0D33*/ 0x00C61110, +/*0D34*/ 0x2C002834, +/*0D35*/ 0x082E002C, +/*0D36*/ 0x00000200, +/*0D37*/ 0x00000000, +/*0D38*/ 0x00000000, +/*0D39*/ 0x00007800, +/*0D3A*/ 0x00000000, +/*0D3B*/ 0x00000000, +/*0D3C*/ 0x00000000, +/*0D3D*/ 0x00C6BBB0, +/*0D3E*/ 0x2C002834, +/*0D3F*/ 0x082E002C, +/*0D40*/ 0x00000200, +/*0D41*/ 0x00000000, +/*0D42*/ 0x00000000, +/*0D43*/ 0x00007800, +/*0D44*/ 0x00000000, +/*0D45*/ 0x00000000, +/*0D46*/ 0x00000000, +/*0D47*/ 0x80808080, +/*0D48*/ 0x800D8080, +/*0D49*/ 0x80808080, +/*0D4A*/ 0x17808080, +/*0D4B*/ 0x80808025, +/*0D4C*/ 0x2221201F, +/*0D4D*/ 0x80808080, +/*0D4E*/ 0x80808080, +/*0D4F*/ 0x80808080, +/*0D50*/ 0x80808080, +/*0D51*/ 0x80808080, +/*0D52*/ 0x80808080, +/*0D53*/ 0x80808080, +/*0D54*/ 0x80808080, +/*0D55*/ 0x80808080, +/*0D56*/ 0x80808080, +/*0D57*/ 0x80808080, +/*0D58*/ 0x80808080, +/*0D59*/ 0x80808080, +/*0D5A*/ 0x80808080, +/*0D5B*/ 0x0A030201, +/*0D5C*/ 0x0E800C0B, +/*0D5D*/ 0x1211100F, +/*0D5E*/ 0x80161413, +/*0D5F*/ 0x08004C80, +/*0D60*/ 0x8080801E, +/*0D61*/ 0x80804E80, +/*0D62*/ 0x80808080, +/*0D63*/ 0x80808080, +/*0D64*/ 0x80808080 +}; + +#endif /* INIT_DRAM_TBL_V4H_LP5 */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram.c new file mode 100644 index 0000000..10d1d0f --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram.c @@ -0,0 +1,4542 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#else +#include "mem_io.h" +#include "log.h" +#endif +#include "ddr_regdef.h" +#include "init_dram_tbl_v4m_lp5.h" +#include "boot_init_dram_regdef.h" +#include "boot_init_dram.h" +#include "dram_sub_func.h" + +/******************************************************************************* + * load board configuration + ******************************************************************************/ +#include "boot_init_dram_config.h" + +#define DDR_BACKUPMODE +#define FATAL_MSG(x) NOTICE(x) + +/******************************************************************************* + * variables + ******************************************************************************/ +static uint32_t Prr_Product; +static uint32_t Prr_Cut; +static uint32_t BOARDTYPE; +static uint32_t brd_clk; +static uint32_t brd_clkdiv; +static uint32_t brd_clkdiva; +static uint32_t ddr_mbps; +static uint32_t ddr_mbpsdiv; +static uint32_t sscg; +static uint32_t med_freq_en; +static uint32_t bus_clk, bus_clkdiv; +static uint32_t ddr_tccd; +static const st_boardcnf_t *Boardcnf; +static uint32_t ddr_phyvalid; +static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; +static uint32_t ch_have_this_cs[CS_CNT]; +static uint32_t max_density; +static uint32_t ddr_mul; +static uint32_t ddr_medium_div; +static uint32_t ddr_mul_nf; +static uint32_t ddr_mul_low; +static uint32_t ddr_mul_reg; + +#define DDR_PHY_REGSET_MAX 140 +#define DDR_PI_REGSET_MAX 1301 + +static uint32_t DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t DDR_PI_REGSET[DDR_PI_REGSET_MAX]; +#ifdef DDR_BACKUPMODE +static uint32_t ddrBackup; +#endif /* DDR_BACKUPMODE */ +#ifndef RCAR_PLL3_FRAC_MODE +#define RCAR_PLL3_FRAC_MODE (1U) +#endif +#ifndef RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE +#define RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE (1U) +#endif +#ifndef RCAR_MEDIUM_FREQUENCY_TRAINING_MODE +#define RCAR_MEDIUM_FREQUENCY_TRAINING_MODE (1U) +#endif +#define PLL3_LOW_FREQUENCY_MODE (0U) +#define PLL3_MEDIUM_FREQUENCY_MODE (1U) +#define PLL3_HIGH_FREQUENCY_MODE (2U) +#define PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER (3U) +#define PLL3_MEDIUM_FREQUENCY_THRESHOLD (1550U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static uint32_t r_vch_nxt(uint32_t pos); +static void r_cpg_write_32(uint32_t a, uint32_t v); +static void r_pll3_control(uint32_t mode); +static void r_send_dbcmd(uint32_t cmd); +static uint32_t r_reg_ddrphy_read(uint32_t phyno, uint32_t regadd); +static void r_reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata); +static void r_reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata); +static void r_reg_ddrphy_masked_write(uint32_t phyno, uint32_t regadd, uint32_t regdata, uint32_t msk); +static void r_ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t regdef, uint32_t val); +static uint32_t r_ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t regdef); +static void r_ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val); +static void r_ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); +static void r_ddr_setval_ach(uint32_t regdef, uint32_t val); +static void r_ddr_setval_ach_as(uint32_t regdef, uint32_t val); +static uint32_t r_ddr_getval(uint32_t ch, uint32_t regdef); +static void r_dbsc_write_32(uintptr_t addr, uint32_t data); +static void r_tbl_copy(uint32_t *to, const uint32_t *from, uint32_t size); +static void r_ddrtbl_setval(uint32_t *tbl, uint32_t regdef, uint32_t val); +static void r_ddrtbl_setval_pi(uint32_t *tbl, uint32_t regdef, uint32_t val); +static uint32_t r_ddrtbl_getval(const uint32_t *tbl, uint32_t regdef); +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) +static uint32_t r_ddrtbl_getval_pi(const uint32_t *tbl, uint32_t regdef); +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ +static uint16_t r_f_scale(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint16_t cyc); +static uint32_t r_f_scale_l(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint32_t cyc); +static void r_f_scale_js2(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t *f_js2); +static void r_ddrtbl_load(void); +static void r_ddr_config(void); +static void r_dbsc_regset_pre(void); +static void r_dbsc_regset(void); +static void r_dbsc_regset_post(void); +static uint32_t r_pi_training(void); +static void r_write_leveling_adjust(void); +static uint32_t r_wl_gt_training(void); +static void r_write_dca(void); +static uint32_t r_dramdca_training(void); +static uint32_t r_write_leveling(void); +static void r_manual_write_dca(void); +static uint32_t r_read_gate_training(void); +static uint32_t r_read_vref_training(void); +static uint32_t r_read_write_training(void); +static uint32_t r_read_training(void); +static void r_ddr_register_set(void); +static void r_ddr_register_read(void); +static uint32_t r_pi_int_ack_0_assert(uint32_t bit); +static void r_wait_dbpdstat1(uint32_t status); +static uint32_t r_wait_freqchgreq(uint32_t req_assert); +static void r_set_freqchgack(uint32_t ack_assert); +static uint32_t r_pll3_freq(void); +static uint32_t r_init_ddr(void); +#if (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) +void r_set_pi_rdlvl_interval(void); +#endif /* (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) */ + +/******************************************************************************* + * macro for channel selection loop + ******************************************************************************/ +static uint32_t r_vch_nxt(uint32_t pos) +{ + uint32_t posn; + + for (posn = pos; posn < DRAM_CH_CNT; posn++) + { + if ((ddr_phyvalid & (1U << posn)) != 0x0U) + { + break; + } + } + return posn; +} + +#define r_foreach_vch(ch) \ +for (ch = r_vch_nxt(0); ch < DRAM_CH_CNT; ch = r_vch_nxt(ch + 1U)) + +#define r_foreach_ech(ch) \ +for (ch = 0U; ch < DRAM_CH_CNT; ch++) + +/******************************************************************************* + * Printing functions + ******************************************************************************/ +#define MSG_LF(...) + +/******************************************************************************* + * clock settings, reset control + ******************************************************************************/ +static void r_cpg_write_32(uint32_t a, uint32_t v) +{ + mmio_write_32(CPG_CPGWPR, ~v); + mmio_write_32(a, v); +} + +static void r_pll3_control(uint32_t mode) +{ + uint32_t dataDIV, dataMUL; + uint32_t ssmode, ssmode_high, dataNF; + /* PLL3VCO = EXTAL * ddr_mul * 1/2 */ + /* clk_ctlr_sync = PLL3VCO * pll3_div */ + /* ddr_mul = (NI[7:0] + 1) * 2 + NF[24:0] / 2^24 */ + +#if (RCAR_PLL3_FRAC_MODE == 1U) + ssmode_high = 0x4U; +#else + ssmode_high = 0x0U; +#endif /* (RCAR_PLL3_FRAC_MODE == 1U) */ + + switch (mode) + { + case PLL3_LOW_FREQUENCY_MODE: + /* Low frequency mode (50MHz) */ + dataMUL = (ddr_mul_low / 2U) - 1U; /* PLL3VCO = 1600MHz */ + dataDIV = 0x9U; /* div = 32 */ + dataNF = 0x00U; + ssmode = 0x0U; + break; + case PLL3_MEDIUM_FREQUENCY_MODE: + /* Medium frequency mode */ + dataMUL = (ddr_mul / 2U) - 1U; + dataDIV = ddr_medium_div; + dataNF = ddr_mul_nf; + ssmode = ssmode_high; + break; + case PLL3_HIGH_FREQUENCY_MODE: + /* High frequency mode */ + dataMUL = (ddr_mul / 2U) - 1U; + dataDIV = 0x0U; /* div = 2 */ + dataNF = ddr_mul_nf; + ssmode = ssmode_high; + break; + case PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER: + /* High frequency mode for loading to DDRPHY registers */ + dataMUL = (ddr_mul_reg / 2U) - 1U; + dataDIV = 0x0U; /* div = 2 */ + dataNF = 0x00U; + ssmode = ssmode_high; + break; + default: + /* High frequency mode */ + dataMUL = (ddr_mul / 2U) - 1U; + dataDIV = 0x0U; /* div = 2 */ + dataNF = ddr_mul_nf; + ssmode = ssmode_high; + break; + }/* mode setting */ + + dataMUL = (dataMUL << 20) | (ssmode << 16); + dataNF = (dataNF << 21); + + if (((mmio_read_32(CPG_PLL3CR0) & 0x3FFFFF7FU) != dataMUL) || (mmio_read_32(CPG_PLL3CR1) != dataNF)) + { + /* PLL3CR0 multiplie set */ + r_cpg_write_32(CPG_PLL3CR0, dataMUL); + /* PLL3CR1 multiplie set */ + r_cpg_write_32(CPG_PLL3CR1, dataNF); + r_cpg_write_32(CPG_PLL3CR0, mmio_read_32(CPG_PLL3CR0) | CPG_PLL3CR0_KICK_BIT); + while ((mmio_read_32(CPG_PLLECR) & CPG_PLLECR_PLL3ST_BIT) != CPG_PLLECR_PLL3ST_BIT) + { + ; /* Nothing */ + } + } + + /* PLL3 DIV set(Target value) */ + while (((mmio_read_32(CPG_FRQCRD0) & CPG_FRQCRD_KICK_BIT)) != 0x0U) + { + ; /* Nothing */ + } + r_cpg_write_32(CPG_FRQCRD0, dataDIV | (mmio_read_32(CPG_FRQCRD0) & 0xFFFFFFF0U)); + r_cpg_write_32(CPG_FRQCRD0, mmio_read_32(CPG_FRQCRD0) | CPG_FRQCRD_KICK_BIT); + while (((mmio_read_32(CPG_FRQCRD0) & CPG_FRQCRD_KICK_BIT)) != 0x0U) + { + ; /* Nothing */ + } +} + +/******************************************************************************* + * DDR memory register access + ******************************************************************************/ +static void r_send_dbcmd(uint32_t cmd) +{ + /* dummy read */ + (void)mmio_read_32(DBSC_DBCMD); + + while (((mmio_read_32(DBSC_DBWAIT)) & 0x01U) != 0x0U) + { + ; /* Nothing */ + } + + r_dbsc_write_32((DBSC_DBCMD), cmd); +} + +/******************************************************************************* + * DDRPHY register access (raw) + ******************************************************************************/ +static uint32_t r_reg_ddrphy_read(uint32_t phyno, uint32_t regadd) +{ + uint32_t val; + + val = 0U; + mmio_write_32(DBSC_DBPDRGA(phyno), (regadd | 0x00004000U)); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x0000C000U)) + { + ; /* Nothing */ + } + + val = mmio_read_32(DBSC_DBPDRGA(phyno)); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + val = mmio_read_32(DBSC_DBPDRGD(phyno)); + (void)val; + + return val; +} + +static void r_reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) +{ + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGD(phyno), regdata); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x00008000U)) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), (regadd | 0x00008000U)); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); +} + +static void r_reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) +{ + uint32_t ch; + + r_foreach_vch((ch)) + { + r_reg_ddrphy_write(ch, regadd, regdata); + } +} + +static void r_reg_ddrphy_masked_write(uint32_t phyno, uint32_t regadd, uint32_t regdata, uint32_t msk) +{ + mmio_write_32(DBSC_DBPDRGM(phyno), msk); + while (mmio_read_32(DBSC_DBPDRGM(phyno)) != msk) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGD(phyno), regdata); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x00008000U)) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + + mmio_write_32(DBSC_DBPDRGM(phyno), 0x00U); + while (mmio_read_32(DBSC_DBPDRGM(phyno)) != 0x00U) + { + ; /* Nothing */ + } +} + +/******************************************************************************* + * DDRPHY register access (field modify) + ******************************************************************************/ +static void r_ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + + adr = DDR_REGDEF_ADR(regdef) + (0x100U * slice); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + tmp = 0xFFFFFFFFU; + } + else + { + tmp = ((1U << len) - 1U) << lsb; + } + + msk = (~(((tmp >> 21) & 0x08U) | ((tmp >> 14) & 0x04U) | ((tmp >> 7) & 0x02U) | (tmp & 0x01U))) & 0x0FU; + + r_reg_ddrphy_masked_write(ch, adr, (val << lsb), msk); +} + +static uint32_t r_ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + + adr = DDR_REGDEF_ADR(regdef) + (0x100U * slice); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U); + } + + tmp = r_reg_ddrphy_read(ch, adr); + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +static void r_ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) +{ + r_ddr_setval_s(ch, 0U, regdef, val); +} + +static void r_ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val) +{ + uint32_t ch; + + r_foreach_vch((ch)) + { + r_ddr_setval_s(ch, slice, regdef, val); + } +} + +static void r_ddr_setval_ach(uint32_t regdef, uint32_t val) +{ + r_ddr_setval_ach_s(0U, regdef, val); +} + +static void r_ddr_setval_ach_as(uint32_t regdef, uint32_t val) +{ + uint32_t slice; + + for (slice = 0U; slice < SLICE_CNT; slice++) + { + r_ddr_setval_ach_s(slice, regdef, val); + } +} + +static uint32_t r_ddr_getval(uint32_t ch, uint32_t regdef) +{ + return r_ddr_getval_s(ch, 0U, regdef); +} + +/******************************************************************************* + * DBSC0 register access + ******************************************************************************/ +static void r_dbsc_write_32(uintptr_t addr, uint32_t data) +{ + *((volatile uint32_t*)addr) = data; +} + +/******************************************************************************* + * handling functions for setteing ddrphy value table + ******************************************************************************/ +static void r_tbl_copy(uint32_t *to, const uint32_t *from, uint32_t size) +{ + uint32_t i; + + for (i = 0U; i < size; i++) + { + to[i] = from[i]; + } +} + +static void r_ddrtbl_setval(uint32_t *tbl, uint32_t regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000000FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U) << lsb; + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + tbl[adr & adrmsk] = tmp; +} + +static void r_ddrtbl_setval_pi(uint32_t *tbl, uint32_t regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000007FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U) << lsb; + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + tbl[adr & adrmsk] = tmp; +} + +static uint32_t r_ddrtbl_getval(const uint32_t *tbl, uint32_t regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000000FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U); + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) +static uint32_t r_ddrtbl_getval_pi(const uint32_t *tbl, uint32_t regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000007FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U); + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp >> lsb) & msk; + + return tmp; +} +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + +/******************************************************************************* + * functions and parameters for timing setting + ******************************************************************************/ +typedef struct +{ + uint32_t fx3; + uint8_t RLset1; + uint8_t RLset2; + uint8_t WLsetA; + uint8_t WLsetB; + uint32_t nWR; + uint32_t nRBTP; + uint32_t ODTLon; + uint8_t MR1; + uint8_t MR2; + uint32_t WCKENLR; + uint32_t WCKENLW; + uint32_t WCKENLF; + uint32_t WCKPRESTA; + uint32_t WCKPRETGLR; +} jedec_spec1_t; + +#define JS1_USABLEC_SPEC_LO 5U +#define JS1_USABLEC_SPEC_HI 11U +#define JS1_FREQ_TBL_NUM 12U +#define JS1_MR1(f) (0x00U | ((f) << 4)) /* CK mode = 0B */ +#define JS1_MR2(f) (((f) << 4) | (f)) + +static const jedec_spec1_t js1[JS1_FREQ_TBL_NUM] = +{ + /* fx3,RL1,RL2,WLA.WLB.nWR.nRBTP,ODTLon */ + { 800, 3, 3, 2, 2, 3, 0, 1, JS1_MR1(0), JS1_MR2(0), 0, 0, 0, 1, 3 }, /* 533.333Mbps */ + { 1600, 4, 4, 2, 3, 5, 0, 1, JS1_MR1(1), JS1_MR2(1), 0, 0, 0, 1, 4 }, /* 1066.666Mbps */ + { 2400, 5, 6, 3, 4, 7, 0, 2, JS1_MR1(2), JS1_MR2(2), 1, 1, 1, 1, 4 }, /* 1600.000Mbps */ + { 3200, 7, 7, 4, 5, 10, 0, 2, JS1_MR1(3), JS1_MR2(3), 2, 1, 1, 2, 4 }, /* 2133.333Mbps */ + { 4000, 8, 9, 4, 7, 12, 1, 2, JS1_MR1(4), JS1_MR2(4), 2, 1, 1, 2, 5 }, /* 2666.666Mbps */ + { 4800, 10, 10, 5, 8, 14, 1, 3, JS1_MR1(5), JS1_MR2(5), 4, 2, 1, 2, 5 }, /* 3200.000Mbps */ + { 5600, 11, 12, 6, 9, 16, 2, 4, JS1_MR1(6), JS1_MR2(6), 4, 2, 1, 3, 5 }, /* 3733.333Mbps */ + { 6400, 13, 14, 6, 11, 19, 2, 3, JS1_MR1(7), JS1_MR2(7), 5, 2, 1, 3, 6 }, /* 4266.666Mbps */ + { 7200, 14, 15, 7, 12, 21, 3, 4, JS1_MR1(8), JS1_MR2(8), 6, 3, 2, 3, 6 }, /* 4800.000Mbps */ + { 8250, 16, 17, 8, 14, 24, 4, 5, JS1_MR1(9), JS1_MR2(9), 7, 3, 2, 4, 6 }, /* 5500.000Mbps */ + { 9000, 17, 19, 9, 15, 26, 4, 6, JS1_MR1(10), JS1_MR2(10), 7, 4, 2, 4, 7 }, /* 6000.000Mbps */ + { 9600, 18, 20, 9, 16, 28, 4, 6, JS1_MR1(11), JS1_MR2(11), 8, 4, 2, 4, 7 } /* 6400.000Mbps */ +}; + +typedef struct +{ + uint16_t ps; + uint16_t cyc; +} jedec_spec2_t; + +#define JS2_tSR 0U +#define JS2_tXP 1U +#define JS2_tRCD 2U +#define JS2_tRPpb 3U +#define JS2_tRPab 4U +#define JS2_tRAS 5U +#define JS2_tWTR_S 6U +#define JS2_tWTR_L 7U +#define JS2_tRRD 8U +#define JS2_tPPD 9U +#define JS2_tFAW 10U +#define JS2_tMRR 11U +#define JS2_tMRW 12U +#define JS2_tMRD 13U +#define JS2_tZQCALns 14U +#define JS2_tZQLAT 15U +#define JS2_tODTon_min 16U +#define JS2_tPDN_DSM 17U +#define JS2_tXSR_DSM 18U +#define JS2_tXDSM_XP 19U +#define JS2_tWCK2DQI_HF 20U +#define JS2_tWCK2DQO_HF 21U +#define JS2_tWCK2DQI_LF 22U +#define JS2_tWCK2DQO_LF 23U +#define JS2_tOSCODQI 24U +#define JS2_tDQ72DQns 25U +#define JS2_tCAENTns 26U +#define JS2_tCSCAL 27U +#define JS2_tWCKSTOP 28U +#define JS2_TBLCNT 29U + +#define JS2_tRCpb (JS2_TBLCNT) +#define JS2_tRCab (JS2_TBLCNT + 1U) +#define JS2_tRFCab (JS2_TBLCNT + 2U) +#define JS2_tRBTP (JS2_TBLCNT + 3U) +#define JS2_tXSR (JS2_TBLCNT + 4U) +#define JS2_tPDN (JS2_TBLCNT + 5U) +#define JS2_tWLWCKOFF (JS2_TBLCNT + 6U) +#define JS2_CNT (JS2_TBLCNT + 7U) + +#ifndef JS2_DERATE +#define JS2_DERATE 0 +#endif + +static const jedec_spec2_t jedec_spec2[2][JS2_TBLCNT] = +{ + { +/* tSR */ { 15000, 2 }, +/* tXP */ { 7000, 3 }, +/* tRCD */ { 18000, 2 }, +/* tRPpb */ { 18000, 2 }, +/* tRPab */ { 21000, 2 }, +/* tRAS */ { 42000, 3 }, +/* tWTR_S */ { 6250, 4 }, +/* tWTR_L */ { 12000, 4 }, +/* tRRD */ { 5000, 2 }, +/* tPPD */ { 0, 2 }, +/* tFAW */ { 20000, 0 }, +/* tMRR */ { 0, 4 }, +/* tMRW */ { 10000, 5 }, +/* tMRD */ { 14000, 5 }, +/* tZQCALns */ { 1500, 0 }, +/* tZQLAT */ { 30000, 4 }, +/* tODTon_min */ { 1500, 0 }, +/* tPDN_DSMus */ { 4000, 0 }, +/* tXSR_DSMus */ { 200, 0 }, +/* tXDSM_XPus */ { 190, 0 }, +/* tWCK2DQI_HF */ { 700, 0 }, +/* tWCK2DQO_HF */ { 1600, 0 }, +/* tWCK2DQI_LF */ { 900, 0 }, +/* tWCK2DQO_LF */ { 1900, 0 }, +/* tOSCODQI */ { 40000, 8 }, +/* tDQ72DQns */ { 125, 0 }, +/* tCAENTns */ { 250, 0 }, +/* tCSCAL */ { 1750, 0 }, +/* tWCKSTOP */ { 6000, 2 } + },{ +/* tSR */ { 15000, 2 }, +/* tXP */ { 7000, 3 }, +/* tRCD */ { 19875, 2 }, +/* tRPpb */ { 19875, 2 }, +/* tRPab */ { 22875, 2 }, +/* tRAS */ { 43875, 3 }, +/* tWTR_S */ { 6250, 4 }, +/* tWTR_L */ { 12000, 4 }, +/* tRRD */ { 5000, 2 }, +/* tPPD */ { 0, 2 }, +/* tFAW */ { 20000, 0 }, +/* tMRR */ { 0, 4 }, +/* tMRW */ { 10000, 5 }, +/* tMRD */ { 14000, 5 }, +/* tZQCALns */ { 1500, 0 }, +/* tZQLAT */ { 30000, 4 }, +/* tODTon_min */ { 1500, 0 }, +/* tPDN_DSMus */ { 4000, 0 }, +/* tXSR_DSMus */ { 200, 0 }, +/* tXDSM_XPus */ { 190, 0 }, +/* tWCK2DQI_HF */ { 715, 0 }, +/* tWCK2DQO_HF */ { 1635, 0 }, +/* tWCK2DQI_LF */ { 920, 0 }, +/* tWCK2DQO_LF */ { 1940, 0 }, +/* tOSCODQI */ { 40000, 8 }, +/* tDQ72DQns */ { 125, 0 }, +/* tCAENTns */ { 250, 0 }, +/* tCSCAL */ { 1750, 0 }, +/* tWCKSTOP */ { 6000, 2 } + } +}; + +static const uint16_t jedec_spec2_tRFC_ab[9] = +{ +/* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 130, 180, 180, 210, 210, 280, 280, 380, 380 +}; + +static uint32_t js1_ind; +static uint32_t js2[JS2_CNT]; +static uint32_t RL; +static uint32_t WL; + +static uint16_t r_f_scale(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint16_t cyc) +{ + uint32_t tmp; + uint32_t f_scale_div; + + tmp = (((uint32_t)(ps) + 9U) / 10U) * f_ddr_mbps; + f_scale_div = tmp / (800000U * f_ddr_mbpsdiv); + if (tmp != (f_scale_div * 800000U * f_ddr_mbpsdiv)) + { + f_scale_div = f_scale_div + 1U; + } + + if (f_scale_div > cyc) + { + cyc = (uint16_t)f_scale_div; + } + + return cyc; +} + +static uint32_t r_f_scale_l(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint32_t cyc) +{ + uint32_t tmp; + uint32_t f_scale_div; + + tmp = (((uint32_t)(ps) + 9U) / 10U) * f_ddr_mbps; + f_scale_div = tmp / (8U * f_ddr_mbpsdiv); + if (tmp != (f_scale_div * 8U * f_ddr_mbpsdiv)) + { + f_scale_div = f_scale_div + 1U; + } + + if (f_scale_div > cyc) + { + cyc = (uint32_t)f_scale_div; + } + + return cyc; +} + +static void r_f_scale_js2(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t *f_js2) +{ + uint32_t i; + + for (i = 0U; i < JS2_TBLCNT; i++) + { + f_js2[i] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, + (uint32_t)jedec_spec2[JS2_DERATE][i].ps, + jedec_spec2[JS2_DERATE][i].cyc); + } + + f_js2[JS2_tZQCALns] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tZQCALns].ps) * 1000U, 0U); + f_js2[JS2_tDQ72DQns] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tDQ72DQns].ps) * 1000U, 0U); + f_js2[JS2_tCAENTns] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tCAENTns].ps) * 1000U, 0U); + f_js2[JS2_tRCpb] = f_js2[JS2_tRAS] + f_js2[JS2_tRPpb]; + f_js2[JS2_tRCab] = f_js2[JS2_tRAS] + f_js2[JS2_tRPab]; + f_js2[JS2_tRFCab] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 1UL * jedec_spec2_tRFC_ab[max_density] * 1000U, 0U); + + f_js2[JS2_tRBTP] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 7500U, 2U) - 2U; + f_js2[JS2_tXSR] = f_js2[JS2_tRFCab] + r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 7500U, 2U); + f_js2[JS2_tPDN] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 10000U, 0U) + 1U; + f_js2[JS2_tPDN_DSM] = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tPDN_DSM].ps) * 10U, 0U); + f_js2[JS2_tXSR_DSM] = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tXSR_DSM].ps) * 10U, 0U); + f_js2[JS2_tXDSM_XP] = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tXDSM_XP].ps) * 10U, 0U); + f_js2[JS2_tWLWCKOFF] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 14000U, 5U); +} + +static const uint32_t PI_DARRAY3_0_CSx_Fx[CS_CNT][3] = +{ + { + PI_DARRAY3_0_CS0_F0, + PI_DARRAY3_0_CS0_F1, + PI_DARRAY3_0_CS0_F2 + }, + { + PI_DARRAY3_0_CS1_F0, + PI_DARRAY3_0_CS1_F1, + PI_DARRAY3_0_CS1_F2 + } +}; + +static const uint32_t PI_DARRAY3_1_CSx_Fx[CS_CNT][3] = +{ + { + PI_DARRAY3_1_CS0_F0, + PI_DARRAY3_1_CS0_F1, + PI_DARRAY3_1_CS0_F2 + }, + { + PI_DARRAY3_1_CS1_F0, + PI_DARRAY3_1_CS1_F1, + PI_DARRAY3_1_CS1_F2 + } +}; + +/******************************************************************************* + * load table data into DDR registers + ******************************************************************************/ +static void r_ddrtbl_load(void) +{ + uint32_t i; + uint32_t slice; + uint32_t cs; + uint32_t adr; + uint32_t dataL; + uint32_t tmp[2]; + + /* Setting RDDQ delay = 103ps */ + const uint32_t rddq_delay = 103U; + + const uint32_t DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_V4M; + const uint32_t DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_V4M; + const uint32_t DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_V4M; + const uint32_t DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_V4M; + + const uint32_t DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_V4M; + + const uint32_t DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_V4M; + const uint32_t DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_V4M; + const uint32_t DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_V4M; + const uint32_t DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_V4M; + + /*********************************************************************** + * TIMING REGISTERS + ***********************************************************************/ + /* search jedec_spec1 index */ + for (i = JS1_USABLEC_SPEC_LO; i < (JS1_FREQ_TBL_NUM - 1U); i++) + { + if ((js1[i].fx3 * 2U * ddr_mbpsdiv) >= (ddr_mbps * 3U)) + { + break; + } + } + + if (JS1_USABLEC_SPEC_HI < i) + { + js1_ind = JS1_USABLEC_SPEC_HI; + } + else + { + js1_ind = i; + } + + RL = js1[js1_ind].RLset1; + + WL = js1[js1_ind].WLsetA; + + /* calculate jedec_spec2 */ + r_f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); + + /*********************************************************************** + * PREPARE TBL + ***********************************************************************/ + r_tbl_copy(DDR_PHY_SLICE_REGSET, + DDR_PHY_SLICE_REGSET_V4M, DDR_PHY_SLICE_REGSET_NUM_V4M); + r_tbl_copy(DDR_PHY_ADR_V_REGSET, + DDR_PHY_ADR_V_REGSET_V4M, DDR_PHY_ADR_V_REGSET_NUM_V4M); + r_tbl_copy(DDR_PHY_ADR_G_REGSET, + DDR_PHY_ADR_G_REGSET_V4M, DDR_PHY_ADR_G_REGSET_NUM_V4M); + r_tbl_copy(DDR_PI_REGSET, + DDR_PI_REGSET_V4M, DDR_PI_REGSET_NUM_V4M); + + /*********************************************************************** + * Adjust PI paramters + ***********************************************************************/ + dataL = 10000U * ddr_mbps / ddr_mbpsdiv / 8U / 256U; + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_CAL_INTERVAL_COUNT_0, dataL); + + dataL = rddq_delay * ddr_mbps * 256U / (ddr_mbpsdiv * 2U * 1000000U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ0_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ1_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ2_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ3_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ4_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ5_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ6_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ7_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDM_SLAVE_DELAY, dataL); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_F2, WL); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_WR_ADJ_F2, (js1[js1_ind].WCKENLW * 4U) + 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_RD_ADJ_F2, (js1[js1_ind].WCKENLR * 4U) + 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_STATIC_F2, (js1[js1_ind].WCKPRESTA * 4U)); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_TOGGLE_RD_F2, (js1[js1_ind].WCKPRETGLR * 4U)); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CASLAT_F2, RL); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_FS_ADJ_F2, (js1[js1_ind].WCKENLF * 4U) + 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRFC_F2, js2[JS2_tRFCab]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLVL_WCKOFF_F2, (js2[JS2_tWLWCKOFF]) + 3U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_ADJ_F2, (WL * 4U) + 2U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCAENT_F2, js2[JS2_tCAENTns]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVREF_LONG_F2, (js2[JS2_tCAENTns]) + 1U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRCD_F2, js2[JS2_tRCD]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRP_F2, js2[JS2_tRPab]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRTP_F2, js1[js1_ind].nRBTP); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MIN_F2, js2[JS2_tRAS]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRD_F2, (js2[JS2_tMRD]) + 1U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TSR_F2, js2[JS2_tSR]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQCAL_F2, js2[JS2_tZQCALns]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQLAT_F2, js2[JS2_tZQLAT]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQ72DQ_F2, js2[JS2_tDQ72DQns]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MC_TRFC_F2, js2[JS2_tRFCab]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_WRLAT_ADJ_F2, (WL * 4U) - 2U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_TWCKENL_RD_ADJ_F2, (js1[js1_ind].WCKENLR * 4U) + 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WCK_STOP_F2, (js2[JS2_tWCKSTOP]) + 2U); + + if (ddr_mbps < (3201U * ddr_mbpsdiv)) + { + /* 2751 - 3200 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_PER_START, 0x40U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x05U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x07U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x0BU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x07U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x25U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x012DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x0BU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x04U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x03U); + + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_TCKSRE_WAIT, 0x01U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x57U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2, 0x0DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x000613U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x002BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x0022U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x0043U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x001DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x0065U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x0029U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_STROBE_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x12U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x0064U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x0012U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0010U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2, 0x0022U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x0EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2, 0x62B8U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQSCK_MAX_F2, 0x01U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x000C26U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x0000797CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2, 0x009BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x013880U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x013880U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x0C3500U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000014U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x000320U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x009BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0014U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x04U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000064U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x000320U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x00000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000029U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x000065U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x000005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2, 0x000000U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2, 0x000065U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2, 0x0016U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F2, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2, 0x0007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2, 0x0016U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F2, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2, 0x0007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2, 0x0016U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F2, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2, 0x0007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2, 0x0016U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F2, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2, 0x0007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_2_CS0_F2, 0xD6U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_2_CS1_F2, 0xD6U); + } + else if (ddr_mbps < (3734U * ddr_mbpsdiv)) + { + /* 3201 - 3733 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_PER_START, 0x40U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x06U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x0AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x0DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x2AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x0149U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x0DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x04U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x04U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x5BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2, 0x10U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x000717U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x002CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x0024U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x0045U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x001FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x0076U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x0030U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_STROBE_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x13U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x0075U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x0014U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2, 0x0024U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x10U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2, 0x7329U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQSCK_MAX_F2, 0x01U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x000E2EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x00008DCCU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2, 0x00B6U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x016C90U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x016C90U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x0E3D98U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000018U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x0003A6U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x00B5U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0018U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000075U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x0003A6U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000030U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x000076U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x000007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2, 0x000000U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2, 0x000076U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2, 0x0019U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2, 0x000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2, 0x0007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2, 0x0019U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2, 0x000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2, 0x0007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2, 0x0019U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2, 0x000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2, 0x0007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2, 0x0019U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2, 0x000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2, 0x0007U); + } + else if (ddr_mbps < (4268U * ddr_mbpsdiv)) + { + /* 3734 - 4267 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_PER_START, 0x40U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x07U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x09U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x0BU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x0EU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x2EU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x0164U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x0EU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x05U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x04U); + + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x64U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2, 0x12U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x00081CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x002DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x002BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x0046U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x0020U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x0087U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x0037U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x14U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x0086U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x0015U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2, 0x002BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x13U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2, 0x83A0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x001038U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x0000A230U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2, 0x00CFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x01A0ABU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x01A0ABU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x1046ABU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x00001BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x00042BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x00CFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x001BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000086U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x00042BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000037U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x000087U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x000008U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2, 0x000000U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2, 0x000087U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2, 0x0009U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2, 0x0009U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2, 0x0009U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2, 0x0009U); + } + else if (ddr_mbps < (4801U * ddr_mbpsdiv)) + { + /* 4268 - 4800 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_PER_START, 0x40U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x0AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x0DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x10U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x31U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x017FU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x10U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x05U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x05U); + + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x68U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2, 0x13U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x000920U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x002EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x002DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x0047U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x0021U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x0097U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x003DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x14U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x0096U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x0017U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0014U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2, 0x002DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x15U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2, 0x940BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x001240U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x0000B680U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2, 0x00E9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x01D4A9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x01D4A9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x124E91U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x00001EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x0004B0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x00E9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x001EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000096U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000008U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x0004B0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000015U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x00003DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x000097U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x00000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2, 0x000001U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2, 0x000097U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2, 0x001FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F2, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2, 0x000DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2, 0x0009U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2, 0x001FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F2, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2, 0x000DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2, 0x0009U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2, 0x001FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F2, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2, 0x000DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2, 0x0009U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2, 0x001FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F2, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2, 0x000DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2, 0x0009U); + } + else if (ddr_mbps < (5501U * ddr_mbpsdiv)) + { + /* 4801 - 5500 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x09U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x0CU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x10U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x13U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x37U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x01A3U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x13U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x06U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x06U); + + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x71U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2, 0x0DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2, 0x15U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x000A79U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x0030U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x0032U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x0049U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x0023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x00AEU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x0046U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x15U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x00ADU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x0019U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0016U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2, 0x0032U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x18U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2, 0xA9D9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x0014F2U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x0000D174U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2, 0x010CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x0219AFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x0219AFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x1500CFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x000561U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x010BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x0000ADU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x000561U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000019U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000046U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x0000AEU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x00000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2, 0x000003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2, 0x0000AEU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2, 0x0023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2, 0x0023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2, 0x0023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2, 0x0023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2, 0x000AU); + } + else if (ddr_mbps < (6001U * ddr_mbpsdiv)) + { + /* 5501 - 6000 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x12U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x15U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x3AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x01BDU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x15U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x06U); + + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x75U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2, 0x16U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x000B6BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x0031U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x0034U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x00BDU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x004DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x00BCU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0017U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2, 0x0034U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x1AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2, 0xB924U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x0016D6U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x0000E45CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2, 0x0124U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x024A16U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x024A16U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x16E4D8U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x0005DDU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x0123U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x0000BCU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x0005DDU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x00001BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x00004DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x0000BDU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2, 0x000004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2, 0x0000BDU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2, 0x0026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2, 0x0026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2, 0x0026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2, 0x0026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2, 0x000AU); + } + else + { + ; /* Nothing */ + } /* (ddr_mbps < (3201U * ddr_mbpsdiv)) */ + +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + if (med_freq_en == 0x01U) + { + if (ddr_mbps < (1601U * ddr_mbpsdiv * ddr_medium_div)) + { + /* 1068 - 1600 */ + /* default */ + ; + } + else if (ddr_mbps < (2134U * ddr_mbpsdiv * ddr_medium_div)) + { + /* 1601 - 2133 */ + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F1, 0x4AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_F1, 0x04U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_RD_ADJ_F1, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_STATIC_F1, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F1, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F1, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CASLAT_F1, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRFC_F1, 0x0066U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F1, 0x00040AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x0028U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F1, 0x001AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_ADJ_F1, 0x12U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F1, 0x0041U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F1, 0x001BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCAENT_F1, 0x0043U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVREF_LONG_F1, 0x0044U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F1, 0x0044U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F1, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F1, 0x11U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F1, 0x0043U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F1, 0x0010U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F1, 0x000DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F1, 0x001AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_TWCKENL_RD_ADJ_F1, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRP_F1, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRCD_F1, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F1, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F1, 0x41D0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MIN_F1, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TSR_F1, 0x04U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F1, 0x000814U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F1, 0x000050C8U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F1, 0x0068U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F1, 0x00D056U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F1, 0x00D056U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F1, 0x082356U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F1, 0x00000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F1, 0x000216U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F1, 0x0068U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F1, 0x000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQCAL_F1, 0x0190U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQLAT_F1, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQ72DQ_F1, 0x0022U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MC_TRFC_F1, 0x0066U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F1, 0x000043U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F1, 0x000216U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F1, 0x00000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F1, 0x00001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F1, 0x000044U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F1, 0x000003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F1, 0x000044U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F1, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F1, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F1, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F1, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F1, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F1, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F1, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F1, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CS0_F1, 0x30U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CS0_F1, 0x33U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CS1_F1, 0x30U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CS1_F1, 0x33U); + } + else + { + /* 2134 - 2750 */ + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F1, 0x4FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_F1, 0x04U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_RD_ADJ_F1, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_STATIC_F1, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_TOGGLE_RD_F1, 0x14U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F1, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F1, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CASLAT_F1, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRFC_F1, 0x0083U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F1, 0x000538U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x002AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F1, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_ADJ_F1, 0x12U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F1, 0x0042U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F1, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCAENT_F1, 0x0056U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVREF_LONG_F1, 0x0057U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F1, 0x0057U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F1, 0x0024U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F1, 0x12U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F1, 0x0056U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F1, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F1, 0x000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F1, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_WRLAT_ADJ_F1, 0x0012U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_TWCKENL_RD_ADJ_F1, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRTP_F1, 0x01U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRP_F1, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRCD_F1, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F1, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F1, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F1, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F1, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F1, 0x54E5U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MIN_F1, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TSR_F1, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F1, 0x000A70U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F1, 0x00006860U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F1, 0x0086U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F1, 0x010CC0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F1, 0x010CC0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F1, 0x0A7F7BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F1, 0x000012U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F1, 0x0002B0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F1, 0x0086U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F1, 0x0012U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQCAL_F1, 0x0204U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQLAT_F1, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQ72DQ_F1, 0x002BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F1, 0x04U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MC_TRFC_F1, 0x0083U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WCK_STOP_F1, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F1, 0x000056U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F1, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F1, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F1, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F1, 0x0002B0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F1, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F1, 0x00000DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F1, 0x000024U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F1, 0x000057U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F1, 0x000004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F1, 0x000057U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F1, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F1, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F1, 0x0006U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F1, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F1, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F1, 0x0006U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F1, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F1, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F1, 0x0006U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F1, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F1, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F1, 0x0006U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CS0_F1, 0x40U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CS0_F1, 0x44U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CS1_F1, 0x40U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CS1_F1, 0x44U); + } /* (ddr_mbps < (1601U * ddr_mbpsdiv * ddr_medium_div)) */ + } /* (med_freq_en == 0x01U) */ +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ + + tmp[0] = js1[js1_ind].MR1; + tmp[1] = js1[js1_ind].MR2; + + for (cs = 0U; cs < CS_CNT; cs++) + { + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CSx_Fx[cs][2], tmp[0]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CSx_Fx[cs][2], tmp[1]); + } + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) + { + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_SET_DFI_INPUT_RST_PAD, 0x01U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_PWRUP_SREFRESH_EXIT, 0x01U); + } +#endif /* DDR_BACKUPMODE */ + + /*********************************************************************** + * Read Vref (SoC side) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->bdcfg_vref_r); + if (dataL != 0x0U) + { + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_START_POINT, dataL & 0x000000FFU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_STOP_POINT, (dataL & 0x0000FF00U) >> 8); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_STEPSIZE, (dataL & 0x00FF0000U) >> 16); + } + + /*********************************************************************** + * Write Vref (MR14, MR15) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->bdcfg_vref_w); + if (dataL != 0x0U) + { + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F0, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F1, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F2, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0, (dataL & 0xFF00U) >> 8); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, (dataL & 0xFF00U) >> 8); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2, (dataL & 0xFF00U) >> 8); + } + + /*********************************************************************** + * CA Vref (MR12) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->bdcfg_vref_ca); + if (dataL != 0x0U) + { + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_START_POINT_F2, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_STOP_POINT_F2, (dataL & 0xFF00U) >> 8); + } + + /*********************************************************************** + * Low Freq setting + ***********************************************************************/ + if (ddr_mbps < (8U * 640U * ddr_mbpsdiv)) + { + /* CAL_CLK(10-20MHz) */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_DATA_DC_CAL_CLK_SEL, 0x05U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_CLK_DC_CAL_CLK_SEL, 0x04U); + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_CAL_CLK_SELECT_0, 0x05U); + } + + if (ddr_mbps < (8U * 572U * ddr_mbpsdiv)) + { + /* CAL_CLK(10-20MHz) */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_PCLK_CLK_SEL, 0x03U); + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x02U); + } + + if (ddr_mbps < (8U * 401U * ddr_mbpsdiv)) + { + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PLL_CTRL, 0x1542U); + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PLL_CTRL_8X, 0x3342U); + } + + /*********************************************************************** + * SET DATA SLICE TABLE + ***********************************************************************/ + for (slice = 0U; slice < SLICE_CNT; slice++) + { + adr = DDR_PHY_SLICE_REGSET_OFS + (DDR_PHY_SLICE_REGSET_SIZE * slice); + for (i = 0U; i < DDR_PHY_SLICE_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PHY_SLICE_REGSET[i]); + } + } + + /*********************************************************************** + * SET ADR SLICE TABLE + ***********************************************************************/ + adr = DDR_PHY_ADR_V_REGSET_OFS; + for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PHY_ADR_V_REGSET[i]); + } + + /*********************************************************************** + * SET ADRCTRL SLICE TABLE + ***********************************************************************/ + adr = DDR_PHY_ADR_G_REGSET_OFS; + for (i = 0U; i < DDR_PHY_ADR_G_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PHY_ADR_G_REGSET[i]); + } + + /*********************************************************************** + * SET PI REGISTERS + ***********************************************************************/ + adr = DDR_PI_REGSET_OFS; + for (i = 0U; i < DDR_PI_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PI_REGSET[i]); + } + +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + /*********************************************************************** + * SET MEDIUM FREQ SETTING + ************************************************************************/ + if (med_freq_en == 0x01U) + { + r_ddr_setval_ach(PHY_FREQ_SEL_MULTICAST_EN, 0x00U); + r_ddr_setval_ach(PHY_FREQ_SEL_INDEX, 0x00U); + + dataL = rddq_delay * ddr_mbps * 256U / (ddr_mbpsdiv * ddr_medium_div * 2U * 1000000U); + r_ddr_setval_ach_as(PHY_RDDQ0_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDQ1_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDQ2_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDQ3_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDQ4_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDQ5_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDQ6_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDQ7_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDM_SLAVE_DELAY, dataL); + + if (ddr_mbps < (1601U * ddr_mbpsdiv * ddr_medium_div)) + { + /* 1068 - 1600 */ + r_ddr_setval_ach_as(PHY_REGULATOR_EN_CNT, 0x03U); + r_ddr_setval_ach_as(PHY_RX_CAL_ALL_DLY, 0x04U); + r_ddr_setval_ach_as(PHY_RX_PCLK_CLK_SEL, 0x02U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_TSEL_DLY, 0x02U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_OE_DLY, 0x05U); + r_ddr_setval_ach_as(PHY_RPTR_UPDATE, 0x06U); + r_ddr_setval_ach_as(PHY_WRLVL_RESP_WAIT_CNT, 0x19U); + r_ddr_setval_ach_as(PHY_RDLVL_MAX_EDGE, 0x00DBU); + r_ddr_setval_ach_as(PHY_RDDATA_EN_DLY, 0x05U); + r_ddr_setval_ach_as(PHY_RDDQS_LATENCY_ADJUST, 0x02U); + r_ddr_setval_ach_as(PHY_GTLVL_LAT_ADJ_START, 0x01U); + r_ddr_setval_ach_as(PHY_DATA_DC_WDQLVL_ENABLE, 0x00U); + r_ddr_setval_ach(PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddr_setval_ach(PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddr_setval_ach(PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE, 0x32U); + r_ddr_setval_ach(PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x01U); + r_ddr_setval_ach(PHY_PLL_CTRL, 0x1742U); + r_ddr_setval_ach(PHY_PLL_CTRL_8X, 0x3542U); + } + else if (ddr_mbps < (2134U * ddr_mbpsdiv * ddr_medium_div)) + { + /* 1601 - 2133 */ + r_ddr_setval_ach_as(PHY_REGULATOR_EN_CNT, 0x04U); + r_ddr_setval_ach_as(PHY_RX_CAL_ALL_DLY, 0x05U); + r_ddr_setval_ach_as(PHY_RX_PCLK_CLK_SEL, 0x02U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_TSEL_DLY, 0x04U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_OE_DLY, 0x07U); + r_ddr_setval_ach_as(PHY_RPTR_UPDATE, 0x07U); + r_ddr_setval_ach_as(PHY_WRLVL_RESP_WAIT_CNT, 0x1EU); + r_ddr_setval_ach_as(PHY_RDLVL_MAX_EDGE, 0x00F7U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_DLY, 0x07U); + r_ddr_setval_ach_as(PHY_RDDQS_LATENCY_ADJUST, 0x02U); + r_ddr_setval_ach_as(PHY_GTLVL_LAT_ADJ_START, 0x02U); + r_ddr_setval_ach_as(PHY_DATA_DC_WDQLVL_ENABLE, 0x00U); + r_ddr_setval_ach(PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddr_setval_ach(PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddr_setval_ach(PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE, 0x32U); + r_ddr_setval_ach(PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x01U); + r_ddr_setval_ach(PHY_PLL_CTRL, 0x1542U); + r_ddr_setval_ach(PHY_PLL_CTRL_8X, 0x3342U); + } + else + { + /* 2134 - 2750 */ + r_ddr_setval_ach_as(PHY_REGULATOR_EN_CNT, 0x05U); + r_ddr_setval_ach_as(PHY_RX_CAL_ALL_DLY, 0x06U); + r_ddr_setval_ach_as(PHY_RX_PCLK_CLK_SEL, 0x03U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_TSEL_DLY, 0x06U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_OE_DLY, 0x09U); + r_ddr_setval_ach_as(PHY_RPTR_UPDATE, 0x07U); + r_ddr_setval_ach_as(PHY_WRLVL_RESP_WAIT_CNT, 0x22U); + r_ddr_setval_ach_as(PHY_RDLVL_MAX_EDGE, 0x0116U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_DLY, 0x09U); + r_ddr_setval_ach_as(PHY_RDDQS_LATENCY_ADJUST, 0x03U); + r_ddr_setval_ach_as(PHY_GTLVL_LAT_ADJ_START, 0x03U); + r_ddr_setval_ach_as(PHY_DATA_DC_WDQLVL_ENABLE, 0x00U); + r_ddr_setval_ach(PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddr_setval_ach(PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddr_setval_ach(PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE, 0x32U); + r_ddr_setval_ach(PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x02U); + r_ddr_setval_ach(PHY_PLL_CTRL, 0x1542U); + r_ddr_setval_ach(PHY_PLL_CTRL_8X, 0x3342U); + } /* (ddr_mbps < (1601U * ddr_mbpsdiv * ddr_medium_div)) */ + + if (ddr_mbps < (8U * 160U * ddr_mbpsdiv * ddr_medium_div)) + { + /* CAL_CLK(10-20MHz) */ + r_ddr_setval_ach_as(PHY_DATA_DC_CAL_CLK_SEL, 0x03U); + r_ddr_setval_ach(PHY_CLK_DC_CAL_CLK_SEL, 0x02U); + r_ddr_setval_ach(PHY_CAL_CLK_SELECT_0, 0x03U); + } + else if (ddr_mbps < (8U * 320U * ddr_mbpsdiv * ddr_medium_div)) + { + /* CAL_CLK(10-20MHz) */ + r_ddr_setval_ach_as(PHY_DATA_DC_CAL_CLK_SEL, 0x04U); + r_ddr_setval_ach(PHY_CLK_DC_CAL_CLK_SEL, 0x03U); + r_ddr_setval_ach(PHY_CAL_CLK_SELECT_0, 0x04U); + } + else + { + /* CAL_CLK(10-20MHz) */ + r_ddr_setval_ach_as(PHY_DATA_DC_CAL_CLK_SEL, 0x05U); + r_ddr_setval_ach(PHY_CLK_DC_CAL_CLK_SEL, 0x04U); + r_ddr_setval_ach(PHY_CAL_CLK_SELECT_0, 0x05U); + } /* (ddr_mbps < (8U * 160U * ddr_mbpsdiv * ddr_medium_div)) */ + + r_ddr_setval_ach(PHY_FREQ_SEL_MULTICAST_EN, 0x01U); + } /* (med_freq_en == 0x01U) */ +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ +} + +/******************************************************************************* + * CONFIGURE DDR REGISTERS + ******************************************************************************/ +static void r_ddr_config(void) +{ + uint32_t ch, slice; + uint32_t dataL; + uint8_t high_byte[SLICE_CNT]; + + r_foreach_vch((ch)) + { + /*********************************************************************** + * BOARD SETTINGS (DQ, DM, VREF_DRIVING) + ***********************************************************************/ + for (slice = 0U; slice < SLICE_CNT; slice++) + { + high_byte[slice] = ((uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap) >> (4U * slice)) % 2U; + r_ddr_setval_s(ch, slice, PHY_DQ_DM_SWIZZLE0, Boardcnf->ch[ch].bdcfg_dq_swap[slice]); + r_ddr_setval_s(ch, slice, PHY_DQ_DM_SWIZZLE1, (uint32_t)(Boardcnf->ch[ch].bdcfg_dm_swap[slice])); + if (high_byte[slice] != 0U) + { + /* HIGHER 16 BYTE */ + r_ddr_setval_s(ch, slice, PHY_CALVL_VREF_DRIVING_SLICE, 0x00U); + } + else + { + /* LOWER 16 BYTE */ + r_ddr_setval_s(ch, slice, PHY_CALVL_VREF_DRIVING_SLICE, 0x01U); + } + } + dataL = (0x000000FFU & (uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap)); + r_ddr_setval(ch, PHY_DATA_BYTE_ORDER_SEL, (0x76543200U | dataL)); + + /*********************************************************************** + * BOARD SETTINGS (CA, ADDR_MUX) + ***********************************************************************/ + dataL = (0x0FFFFFFFU & (uint32_t)(Boardcnf->ch[ch].bdcfg_ca_swap)); + + /* --- ADDR_MUX --- */ + r_ddr_setval(ch, PI_ADDRESS_MUX_0, (0x000000FU & dataL)); + r_ddr_setval(ch, PI_ADDRESS_MUX_1, (0x000000FU & (dataL >> 4))); + r_ddr_setval(ch, PI_ADDRESS_MUX_2, (0x000000FU & (dataL >> 8))); + r_ddr_setval(ch, PI_ADDRESS_MUX_3, (0x000000FU & (dataL >> 12))); + r_ddr_setval(ch, PI_ADDRESS_MUX_4, (0x000000FU & (dataL >> 16))); + r_ddr_setval(ch, PI_ADDRESS_MUX_5, (0x000000FU & (dataL >> 20))); + r_ddr_setval(ch, PI_ADDRESS_MUX_6, (0x000000FU & (dataL >> 24))); + + /* --- ADR_CALVL_SWIZZLE --- */ + r_ddr_setval(ch, PHY_ADR_CALVL_SWIZZLE0, dataL); + + /*********************************************************************** + * BOARD SETTINGS (CS) + ***********************************************************************/ + /* --- CKE_MUX --- */ + /* SoC CKE -> DRAM CS */ + dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_cs_swap); + r_ddr_setval(ch, PI_CKE_MUX_0, (0x0FU & dataL)); + r_ddr_setval(ch, PI_CKE_MUX_1, (0x0FU & (dataL >> 4))); + r_ddr_setval(ch, PHY_CS_ACS_ALLOCATION_BIT2_2, ((0x0FU & (dataL)) + 1U)); + r_ddr_setval(ch, PHY_CS_ACS_ALLOCATION_BIT3_2, ((0x0FU & (dataL >> 4)) + 1U)); + + /*********************************************************************** + * mask CS_MAP if RANK1 is not found + ***********************************************************************/ + if ((ch_have_this_cs[1] & (1U << ch)) == 0x0U) + { + r_ddr_setval(ch, PHY_ADR_CALVL_RANK_CTRL, 0x00U); + for (slice = 0U; slice < SLICE_CNT; slice++) + { + r_ddr_setval_s(ch, slice, PHY_PER_CS_TRAINING_EN, 0x00U); + } + } + } + + r_foreach_vch((ch)) + { + /* --- DATA_BYTE_SWAP --- */ + dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap); + r_ddr_setval(ch, PI_DATA_BYTE_SWAP_EN, 0x01U); + r_ddr_setval(ch, PI_DATA_BYTE_SWAP_SLICE0, dataL & 0x0FU); + r_ddr_setval(ch, PI_DATA_BYTE_SWAP_SLICE1, (dataL >> 4) & 0x0FU); + + if ((ch_have_this_cs[1] & (1U << ch)) == 0x0U) + { + r_ddr_setval(ch, PI_CS_MAP, 0x01U); + } + } +} + +/******************************************************************************* + * DBSC register setting functions + ******************************************************************************/ +static void r_dbsc_regset_pre(void) +{ + uint32_t ch, cs; + + /*********************************************************************** + * PRIMARY SETTINGS + ***********************************************************************/ + /* LPDDR5, BL=16, DFI interface */ + r_dbsc_write_32(DBSC_DBMEMKIND, 0x0000000CU); + r_dbsc_write_32(DBSC_DBMEMKINDA, 0x0000000CU); + r_dbsc_write_32(DBSC_DBBL, 0x00000002U); + r_dbsc_write_32(DBSC_DBBLA, 0x00000002U); + r_dbsc_write_32(DBSC_DBPHYCONF0, 0x00000001U); + + r_dbsc_write_32(DBSC_DBSYSCONF0, 0x00000001U); + + /* FREQRATIO=2 */ + r_dbsc_write_32(DBSC_DBSYSCONF1, 0x00020000U); + r_dbsc_write_32(DBSC_DBSYSCONF1A, 0x00000000U); + + r_dbsc_write_32(DBSC_DBSYSCONF2, 0x00000001U); + r_dbsc_write_32(DBSC_DBSYSCONF2A, 0x00000241U); + + r_foreach_ech((ch)) + { + for (cs = 0U; cs < CS_CNT; cs++) + { + if (ddr_density[ch][cs] == 0xFFU) + { + mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00U); + mmio_write_32(DBSC_DBMEMCONFA(ch, cs), 0x00U); + } + else + { + mmio_write_32(DBSC_DBMEMCONF(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs])); + mmio_write_32(DBSC_DBMEMCONFA(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs])); + } + } + } +} + +static void r_dbsc_regset(void) +{ + uint32_t tmp[4]; + + /* DBTR0.cl : RL */ + r_dbsc_write_32(DBSC_DBTR(0U), RL); + + /* DBTR1.cwl : WL */ + r_dbsc_write_32(DBSC_DBTR(1U), WL); + + /* DBTR2.al = 0 */ + r_dbsc_write_32(DBSC_DBTR(2U), 0x00000000U); + + /* DBTR3.trcd : tRCD */ + r_dbsc_write_32(DBSC_DBTR(3U), js2[JS2_tRCD]); + + /* DBTR4.trpa,trp : tRPab,tRPpb */ + r_dbsc_write_32(DBSC_DBTR(4U), ((js2[JS2_tRPab] << 16) | js2[JS2_tRPpb])); + + /* DBTR5.trc : tRCpb */ + r_dbsc_write_32(DBSC_DBTR(5U), js2[JS2_tRCpb]); + + /* DBTR6.tras : tRAS */ + r_dbsc_write_32(DBSC_DBTR(6U), js2[JS2_tRAS]); + + /* DBTR7.trrd : tRRD */ + r_dbsc_write_32(DBSC_DBTR(7U), (((js2[JS2_tRRD] - 1U) << 16) | (js2[JS2_tRRD] - 1U))); + + /* DBTR8.tfaw : tFAW */ + r_dbsc_write_32(DBSC_DBTR(8U), (js2[JS2_tFAW] - 1U)); + + /* DBTR9.trdpr : nRBTP */ + r_dbsc_write_32(DBSC_DBTR(9U), js1[js1_ind].nRBTP); + + /* DBTR10.twr : nWR */ + r_dbsc_write_32(DBSC_DBTR(10U), js1[js1_ind].nWR); + + /* DBTR11.trdwr : RL + BL/n_max + RU(tWCK2DQO(max)/tCK) + RD(tRPST/tCK) - ODTLon - RD(tODTon(min)/tCK) + 1 + feature */ + r_dbsc_write_32(DBSC_DBTR(11U), (RL + 4U + js2[JS2_tWCK2DQO_HF] + 0U - js1[js1_ind].ODTLon - (js2[JS2_tODTon_min] - 1U) + 1U + 0U)); + + /* DBTR12.twrrd_s,twrrd : WL + BL/2 + tWTR_S,WL + BL + tWTR_L */ + r_dbsc_write_32(DBSC_DBTR(12U), (((WL + 2U + js2[JS2_tWTR_S]) << 16) | (WL + 4U + js2[JS2_tWTR_L]))); + + /* DBTR13.trfcab : tRFCab */ + r_dbsc_write_32(DBSC_DBTR(13U), js2[JS2_tRFCab]); + + /* DBTR14.tcscal,tckehdll,tckeh : tCSCAL,tXP,tXP */ + r_dbsc_write_32(DBSC_DBTR(14U), ((js2[JS2_tCSCAL] << 24) | (js2[JS2_tXP] << 16) | js2[JS2_tXP])); + + /* DBTR15.tespd,tckesr,tckel : tESPD = 2,tSR,tSR */ + r_dbsc_write_32(DBSC_DBTR(15U), ((0x02U << 24) | (js2[JS2_tSR] << 16) | js2[JS2_tSR])); + + /* DBTR16 */ + /* wdql(tphy_wrlat + tphy_wrdata) */ + tmp[0] = (WL * 4U) - 1U + 5U; + /* dqenltcy(tphy_wrlat) */ + tmp[1] = (WL * 4U) - 2U - 2U + 5U; + /* dql(tphy_rdlat + trddata_en) : RL * 4 + phy_rptr_update + phy_rddqs_latency_adjust + 39 */ + tmp[2] = (RL * 4U) + r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE) + r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST) + 39U; + /* dqienltncy(trddata_en) : RL * 4 - phy_rddata_en_dly_X + 4 * phy_wck_freq_ratio_X */ + tmp[3] = (RL * 4U) + 4U - r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY); + r_dbsc_write_32(DBSC_DBTR(16U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR17.tmodrd,tmod : tMRR,tMRW */ + r_dbsc_write_32(DBSC_DBTR(17U), ((js2[JS2_tMRR] << 24) | (js2[JS2_tMRW] << 16))); + + /* DBTR18.rodtl,rodta = 0 */ + r_dbsc_write_32(DBSC_DBTR(18U), 0x00000000U); + + /* DBTR19.tzqcl,tzqcs = 0 */ + r_dbsc_write_32(DBSC_DBTR(19U), 0x00000000U); + + /* DBTR20.txsdll,txs : tXSR,tXSR */ + r_dbsc_write_32(DBSC_DBTR(20U), ((js2[JS2_tXSR] << 16) | js2[JS2_tXSR])); + + /* DBTR21.tccd */ + r_dbsc_write_32(DBSC_DBTR(21U), ((ddr_tccd << 16) | (ddr_tccd * 2U))); + + /* DBTR22.tzqcal,tzqlat : tZQCAL,tZQLAT */ + r_dbsc_write_32(DBSC_DBTR(22U), ((js2[JS2_tZQCALns] << 16) | js2[JS2_tZQLAT])); + + /* DBTR23.rrspc = 0 */ + r_dbsc_write_32(DBSC_DBTR(23U), 0x00000000U); + + /* DBTR24 */ + /* wrcslat(tphy_wrcslat) */ + tmp[0] = (WL * 4U) - 2U; + /* wrcsgap(tphy_wrcsgap) */ + tmp[1] = 0x0CU; + /* rdcslat(tphy_rdcslat) */ + tmp[2] = RL * 4U; + /* rdcsgap(tphy_rdcsgap) */ + tmp[3] = 0x0CU; + r_dbsc_write_32(DBSC_DBTR(24U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR25 */ + r_dbsc_write_32(DBSC_DBTR(25U), 0x00000000U); + + /* DBTR26 */ + r_dbsc_write_32(DBSC_DBTR(26U), 0x00000000U); + + /* DBTR27.tpdn : tPDN */ + r_dbsc_write_32(DBSC_DBTR(27U), js2[JS2_tPDN]); + + /* DBTR28.txsrdsm : tXSR_DSM */ + r_dbsc_write_32(DBSC_DBTR(28U), js2[JS2_tXSR_DSM]); + + /* DBTR29.tdsmxp : tXDSM_XP */ + r_dbsc_write_32(DBSC_DBTR(29U), js2[JS2_tXDSM_XP]); + + /* DBTR30.tcmdpd : tCMDPD = 3 */ + r_dbsc_write_32(DBSC_DBTR(30U), 0x00000003U); + + /* DBTR31.twck2dqomax,twck2dqimax : tWCK2DQO_HF/LF,tWCK2DQI_HF/LF */ + r_dbsc_write_32(DBSC_DBTR(31U), ((js2[JS2_tWCK2DQO_HF] << 4) | js2[JS2_tWCK2DQI_HF])); + + /* DBTR32 */ + /* twckenr */ + tmp[0] = (js1[js1_ind].WCKENLR * 4U) + 4U - 1U; + /* twckenw */ + tmp[1] = (js1[js1_ind].WCKENLW * 4U) + 4U - 1U; + /* twckenlf */ + tmp[2] = (js1[js1_ind].WCKENLF * 4U) + 4U; + /* twckpresta */ + tmp[3] = js1[js1_ind].WCKPRESTA * 4U; + r_dbsc_write_32(DBSC_DBTR(32U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR33 */ + /* twcktgl */ + tmp[0] = 4U; + /* twckdis : (RL+ bl/n_max) * 4 + RU(tWCKPST/tWCK),tWCKPST = MR10[3:2] = 2.5 */ + tmp[1] = ((RL + 4U) * 4U) + 3U; + r_dbsc_write_32(DBSC_DBTR(33U), ((tmp[1] << 8) | tmp[0])); + + /* DBTR34 */ + /* twcksus = 4 */ + tmp[0] = 4U; + /* twckpst : RU(tWCKPST/tCK),tWCKPST = MR10[3:2] = 2.5 */ + tmp[1] = 1U; + r_dbsc_write_32(DBSC_DBTR(34U), ((tmp[1] << 8) | tmp[0])); + + /* DBTR35 */ + /* trd2wckoff : RL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[0] = RL + 4U + 0U +1U; + /* twr2wckoff : WL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[1] = WL + 4U + 0U +1U; + r_dbsc_write_32(DBSC_DBTR(35U), ((tmp[1] << 16) | tmp[0])); + + /* DBTR36 */ + /* twssuswrx : CAS(WCKSUS)WRX */ + tmp[0] = 3U; + /* twsoffwrx : CAS(WS_OFF)WRX */ + tmp[1] = 3U; + /* twsfswrx : CAS(WS_FS)WRX */ + tmp[2] = 2U; + r_dbsc_write_32(DBSC_DBTR(36U), ((tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR37.tosco : tOSCODQI */ + r_dbsc_write_32(DBSC_DBTR(37U), js2[JS2_tOSCODQI]); + + /* DBRNK2 */ + /* rnkrr = 12 */ + r_dbsc_write_32(DBSC_DBRNK(2U), 0x000000CCU); + + /* DBRNK3 */ + /* rnkrw = 6 */ + r_dbsc_write_32(DBSC_DBRNK(3U), 0x00000066U); + + /* DBRNK4 */ + /* rnkwr = 6 */ + r_dbsc_write_32(DBSC_DBRNK(4U), 0x00000066U); + + /* DBRNK5 */ + /* rnkww = 14 */ + r_dbsc_write_32(DBSC_DBRNK(5U), 0x000000EEU); + + /* DBBUS0CNF1 */ + /* BGADM */ + r_dbsc_write_32(DBSC_DBBUS0CNF1, 0x00010000U); + + /*********************************************************************** + * timing registers for Scheduler + ***********************************************************************/ + /* SCFCTST0 */ + /* scpreact */ + tmp[0] = 1UL * js2[JS2_tRPpb] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* scactrdwr */ + tmp[1] = 1UL * (WL + 2U + 1U + js1[js1_ind].nWR + js2[JS2_tRPpb]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* scrdacrt */ + tmp[2] = 1UL * ((js1[js1_ind].nRBTP + 2U) + js2[JS2_tRPpb]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* scactact */ + tmp[3] = 1UL * js2[JS2_tRCpb] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + r_dbsc_write_32(DBSC_DBSCHFCTST0, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* SCFCTST1 */ + /* scasyncofs */ + tmp[0] = 12U; + /* scactrdwr */ + tmp[1] = 1UL * js2[JS2_tRCD] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* scwrrd */ + tmp[2] = 1UL * (mmio_read_32(DBSC_DBTR(12U)) & 0xFFU) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* scrdwr */ + tmp[3] = 1UL * (mmio_read_32(DBSC_DBTR(11U)) & 0xFFU) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + r_dbsc_write_32(DBSC_DBSCHFCTST1, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBSCHRW1 */ + /* sctrfcab */ + tmp[0] = 1UL * (js2[JS2_tRFCab] + js2[JS2_tZQLAT]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + r_dbsc_write_32(DBSC_DBSCHRW1, tmp[0]); + + /* DBSCHTR0 */ + /* scdt0 */ + tmp[0] = (1UL * 4U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + /* scdt1 */ + tmp[1] = (1UL * 8U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + /* scdt2 */ + tmp[2] = (1UL * 12U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + /* scdt3 */ + tmp[3] = (1UL * 16U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + r_dbsc_write_32(DBSC_DBSCHTR0, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /*********************************************************************** + * QOS and CAM + ***********************************************************************/ + r_dbsc_write_32(DBSC_DBBCAMDIS, 0x00000001U); +} + +static void r_dbsc_regset_post(void) +{ + uint32_t dataL; + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + uint32_t ctrl_clk; + uint32_t clk_count; + uint32_t phymster_req_interval; +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + + r_dbsc_write_32(DBSC_DBDBICNT, 0x00000003U); + + /* set REFCYCLE */ + dataL = DBSC_REFINT * ddr_mbps / 8000U / ddr_mbpsdiv; + /* refpmax=8 */ + r_dbsc_write_32(DBSC_DBRFCNF1, 0x00080000U | (dataL & 0x0000FFFFU)); + /* refpmin=1 */ + r_dbsc_write_32(DBSC_DBRFCNF2, 0x00010000U | DBSC_REFINTS); + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000U); +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + +#if (RCAR_PERIODIC_WRITE_TRAINING != 0U) + /* Periodic-WriteDQ Training setting */ + r_ddr_setval_ach(PI_WDQLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_WDQLVL_VREF_EN, 0x00U); + r_ddr_setval_ach_as(PHY_DATA_DC_WDQLVL_ENABLE, 0x00U); + r_ddr_setval_ach(PI_WDQLVL_PERIODIC, 0x01U); +#endif /* (RCAR_PERIODIC_WRITE_TRAINING != 0U) */ + +#if (RCAR_PERIODIC_READ_TRAINING != 0U) + /* Periodic-ReadDQ Training setting */ + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F2, 0x00U); + r_ddr_setval_ach_as(PHY_RDLVL_DLY_STEP, 0x04U); + r_ddr_setval_ach(PI_RDLVL_PERIODIC, 0x01U); +#endif /* (RCAR_PERIODIC_READ_TRAINING != 0U) */ + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + /* DFI_PHYMSTR_ACK , WTmode = b'01 */ + r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011U); +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + + /* periodic SoC zqcal enable */ + r_ddr_setval_ach(PHY_CAL_MODE_0, r_ddrtbl_getval(DDR_PHY_ADR_G_REGSET, PHY_CAL_MODE_0) | 0x02U); + +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + if (med_freq_en == 0x01U) + { + /* Prepare DFS after initialization */ + /* Medium frequency mode (F1) */ + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F1, 0x03U); + r_ddr_setval_ach(PI_RDLVL_EN_F1, 0x01U); + r_ddr_setval_ach(PI_WDQLVL_EN_F1, 0x03U); + /* High frequency mode (F2) */ + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x03U); + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_WDQLVL_EN_F2, 0x03U); + } +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ + + /* periodic dram zqcal enable */ + r_dbsc_write_32(DBSC_DBCALCNF, 0x01000010U); + + /* periodic phy ctrl update enable */ + r_dbsc_write_32(DBSC_DBDFICUPDCNF, 0x504C0001U); + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) + { + /* SRX */ + r_send_dbcmd(0x0A840001U); + } +#endif /* DDR_BACKUPMODE */ + /* set Auto Refresh */ + r_dbsc_write_32(DBSC_DBRFEN, 0x00000001U); + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + /* Periodic-WriteDQ/ReadDQ Training Interval setting */ + phymster_req_interval = PERIODIC_TRAINING_INTERVAL - 3000U; + clk_count = 1024U - (r_ddrtbl_getval_pi(DDR_PI_REGSET, PI_LONG_COUNT_MASK) * 32U); + ctrl_clk = ddr_mbps / ddr_mbpsdiv / 8U; + dataL = phymster_req_interval * ctrl_clk / clk_count; +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + +#if (RCAR_PERIODIC_WRITE_TRAINING != 0U) + r_ddr_setval_ach(PI_WDQLVL_INTERVAL, dataL); +#endif /* (RCAR_PERIODIC_WRITE_TRAINING != 0U) */ + +#if ((RCAR_PERIODIC_READ_TRAINING != 0U) && (RCAR_PERIODIC_TRAINING_SEPARATE_MODE == 0U)) + r_ddr_setval_ach(PI_RDLVL_INTERVAL, dataL); +#endif /* ((RCAR_PERIODIC_READ_TRAINING != 0U) && (RCAR_PERIODIC_TRAINING_SEPARATE_MODE == 0U)) */ + + /* dram access enable */ + r_dbsc_write_32(DBSC_DBACEN, 0x00000001U); + + MSG_LF("dbsc_regset_post(done)\n"); +} + +/******************************************************************************* + * DFI_INIT_START and PI_TRAINING + ******************************************************************************/ +static uint32_t r_pi_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + uint32_t frqchg_req; + uint32_t flag; + uint32_t complete_ng; + uint32_t ca_training_ng; + uint32_t wr_training_ng; + uint32_t gt_training_ng; + uint32_t rd_training_ng; + uint32_t wdq_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + /*********************************************************************** + * init start + **********************************************************************/ +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + if (med_freq_en == 0x01U) + { + r_ddr_setval_ach(PI_FREQ_MAP, 0x07U); + r_ddr_setval_ach(PI_INIT_WORK_FREQ, 0x02U); + r_ddr_setval_ach(PI_CALVL_EN_F1, 0x01U); + r_ddr_setval_ach(PI_WRLVL_EN_F1, 0x01U); + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F1, 0x01U); + r_ddr_setval_ach(PI_WRDCM_LVL_EN_F1, 0x00U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_EN_F1, 0x00U); + r_ddr_setval_ach(PI_RDLVL_EN_F1, 0x01U); + r_ddr_setval_ach(PI_WDQLVL_EN_F1, 0x01U); + r_ddr_setval_ach(PI_RDLVL_RDDQ_EN_F1, 0x00U); + + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F1, 0x00U); + r_ddr_setval_ach_as(PHY_VREF_TRAINING_CTRL, 0x00U); + r_ddr_setval_ach(PI_WDQLVL_VREF_EN, 0x00U); + } +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ + + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WRDCM_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WDQLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_SEQ_ARRAY_81, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_82, 0x00000000U); + + /* PI_START */ + r_ddr_setval_ach(PI_START, 0x01U); + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) + { + r_ddr_setval_ach(PI_DLL_RST, 0x01U); + r_ddr_setval_ach(PI_PWRUP_SREFRESH_EXIT, 0x00U); + } +#endif /* DDR_BACKUPMODE */ + + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000020U); + } + + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000021U); + } + + /* Dummy PDE */ + r_send_dbcmd(0x08840000U); + + /* PDX */ + r_send_dbcmd(0x08840001U); + + /*********************************************************************** + * wait init_complete + ***********************************************************************/ + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + frqchg_req = 0U; + for (ch = 0U; ch < DRAM_CH_CNT; ch++) + { + if ((((~phytrainingok) & ddr_phyvalid) & (1U << ch)) != 0x0U) + { + if ((mmio_read_32(DBSC_DBPDSTAT0(ch)) & 0x01U) != 0x0U) + { + frqchg_req = 1U; + break; + } + } + } + + if (frqchg_req != 0x0U) + { + flag = r_pll3_freq(); + if (flag != 0x0U) + { + break; + } + } + else + { + r_foreach_vch((ch)) + { + dataL = mmio_read_32(DBSC_DBDFISTAT(ch)); + if ((dataL & 0x00000001U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + }/* frqchg_req != 0x0U */ + } + + /* dbdficnt0: + * dfi_dram_clk_disable=0 + * dfi_frequency = 0 + * freq_ratio = 10 (4:1) + * init_start =0 + */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000020U); + } + + /* DFI_PHYMSTR_ACK */ + r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001U); + + complete_ng = 0x0U; + ca_training_ng = 0x0U; + wr_training_ng = 0x0U; + gt_training_ng = 0x0U; + rd_training_ng = 0x0U; + wdq_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* CA/CS Training Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 4)); /* PI_CALVL_ERROR_BIT */ + dataL |= (r_ddr_getval(ch, PHY_ADR_CALVL_OBS1) & (0x3U << 30)); /* error on decrement/increment pass */ + dataL |= (r_ddr_getval(ch, PHY_ADR_CALVL_OBS2) & (0x3U << 24)); /* start outside of initial search range */ + dataL |= (r_ddr_getval(ch, PHY_CSLVL_OBS1) & (0xFU << 28)); /* CSlvl error */ + if (dataL != 0x0U) + { + ca_training_ng |= 1U << ch; + MSG_LF("pi_training_error:1\n"); + } + + /* Wrlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3)); /* PI_WRLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12)); /* SLICE0 wrlvl error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12)); /* SLICE1 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS); /* SLICE0 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS); /* SLICE1 wrlvl error */ + if (dataL != 0x0U) + { + wr_training_ng |= 1U << ch; + MSG_LF("pi_training_error:2\n"); + } + +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + if (med_freq_en == 0x01U) + { + /* Gtlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 2)); /* PI_RDLVL_GATE_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7)); /* SLICE0 delay setup error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7)); /* SLICE1 delay setup error */ + if (dataL != 0x0U) + { + gt_training_ng |= 1U << ch; + MSG_LF("pi_training_error:3\n"); + } + + /* Rdlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 1)); /* PI_RDLVL_ERROR_BIT */ + if (dataL != 0x0U) + { + rd_training_ng |= 1U << ch; + MSG_LF("pi_training_error:4\n"); + } + + /* Wdqlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 5)); /* PI_WDQLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18)); /* SLICE0 wdqlvl_fail_dqZ */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18)); /* SLICE1 wdqlvl_fail_dqZ */ + if (dataL != 0x0U) + { + wdq_training_ng |= 1U << ch; + MSG_LF("pi_training_error:5\n"); + } + } +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ + } + + complete_ng = (wdq_training_ng | rd_training_ng | gt_training_ng | wr_training_ng | ca_training_ng); + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x01U); + } + + return phytrainingok; +} + +/******************************************************************************* + * Write Leveling Cycle Adjust + ******************************************************************************/ +static void r_write_leveling_adjust(void) +{ + uint32_t ch; + uint32_t result_hard0; + uint32_t result_hard1; + uint32_t avg; + uint32_t avg_frac; + uint32_t avg_cycle; + + r_foreach_vch((ch)) + { + /* SLICE0 */ + result_hard0 = r_ddr_getval_s(ch, 0U, PHY_WRLVL_HARD0_DELAY_OBS); + result_hard1 = r_ddr_getval_s(ch, 0U, PHY_WRLVL_HARD1_DELAY_OBS); + + if (result_hard0 <= result_hard1) + { + avg = (result_hard0 + result_hard1) / 2U; + } + else + { + avg = (result_hard0 + result_hard1 + 0x400U) / 2U; + } + avg_frac = avg & 0xFFU; + avg_cycle = (avg >> 8) & 0x3U; + + if (avg_cycle == 0x3U) + { + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_DEC, 0x1U); + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_ADD, 0x0U); + } + else + { + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_DEC, 0x0U); + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_ADD, avg_cycle); + } + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_FRAC, avg_frac); + + /* SLICE1 */ + result_hard0 = r_ddr_getval_s(ch, 1U, PHY_WRLVL_HARD0_DELAY_OBS); + result_hard1 = r_ddr_getval_s(ch, 1U, PHY_WRLVL_HARD1_DELAY_OBS); + + if (result_hard0 <= result_hard1) + { + avg = (result_hard0 + result_hard1) / 2U; + } + else + { + avg = (result_hard0 + result_hard1 + 0x400U) / 2U; + } + avg_frac = avg & 0xFFU; + avg_cycle = (avg >> 8) & 0x3U; + + if (avg_cycle == 0x3U) + { + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_DEC, 0x1U); + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_ADD, 0x0U); + } + else + { + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_DEC, 0x0U); + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_ADD, avg_cycle); + } + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_FRAC, avg_frac); + } + + r_ddr_setval_ach_as(SC_PHY_WCK_CALC, 0x01U); +} + +/******************************************************************************* + * Re-run Write Leveling & Read Gate Training + ******************************************************************************/ +static uint32_t r_wl_gt_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + + uint32_t complete_ng; + uint32_t wr_training_ng; + uint32_t gt_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + r_ddr_setval_ach(PI_CALVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x01U); + r_ddr_setval_ach(PI_SEQ_ARRAY_29, 0x181F0000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_64, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_65, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_66, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_67, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_68, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_69, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_70, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_71, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_72, 0x00000000U); + r_ddr_setval_ach(PI_TRAIN_ALL_FREQ_REQ, 0x01U); + + /* Freq Change High to High */ + dataL = r_pll3_freq(); + if (dataL != 0x0U) + { + return (1); + } + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if ((dataL & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + wr_training_ng = 0x0U; + gt_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Wrlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3)); /* PI_WRLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12)); /* SLICE0 wrlvl error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12)); /* SLICE1 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS); /* SLICE0 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS); /* SLICE1 wrlvl error */ + if (dataL != 0x0U) + { + wr_training_ng |= 1U << ch; + MSG_LF("wl_gt_training_error:1\n"); + } + /* Gtlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 2)); /* PI_RDLVL_GATE_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7)); /* SLICE0 delay setup error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7)); /* SLICE1 delay setup error */ + if (dataL != 0x0U) + { + gt_training_ng |= 1U << ch; + MSG_LF("wl_gt_training_error:2\n"); + } + } + + complete_ng = (wr_training_ng | gt_training_ng); + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x01U); + } + + return phytrainingok; +} + +/******************************************************************************* + * Write DCA Training + ******************************************************************************/ +static void r_write_dca(void) +{ + uint32_t ch; + uint32_t dataL; + uint32_t phytrainingok; + uint32_t retry; + const uint32_t RETRY_MAX = 0x10000U; + + r_ddr_setval_ach_as(PHY_DATA_DC_CAL_START, 0x01U); + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = (r_ddr_getval_s(ch, 0U, PHY_DATA_DC_CAL_START)) | (r_ddr_getval_s(ch, 1U, PHY_DATA_DC_CAL_START)); + if (dataL == 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } +} + +/******************************************************************************* + * DRAM DCA Training and Calculations + ******************************************************************************/ +static uint32_t r_dramdca_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t dataL; + uint32_t rank; + uint32_t dca_result_l_0[DRAM_CH_CNT][CS_CNT]; /* DCA_result_lower_flip0_[ch][cs] */ + uint32_t dca_result_u_0[DRAM_CH_CNT][CS_CNT]; /* DCA_result_upper_flip0_[ch][cs] */ + uint32_t dca_result_l_1[DRAM_CH_CNT][CS_CNT]; /* DCA_result_lower_flip1_[ch][cs] */ + uint32_t dca_result_u_1[DRAM_CH_CNT][CS_CNT]; /* DCA_result_upper_flip1_[ch][cs] */ + uint32_t tempu; + uint32_t templ; + + const uint32_t mr30_conv[16] = + { + 0x08U, 0x07U, 0x06U, 0x05U, 0x04U, 0x03U, 0x02U, 0x01U, + 0x00U, 0x09U, 0x0AU, 0x0BU, 0x0CU, 0x0DU, 0x0EU, 0x0FU + }; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + /*********************************************************************** + * Run DRAM DCA Training for Flip-0 + ***********************************************************************/ + r_ddr_setval_ach(PI_DCMLVL_CS_SW, rank); + + /* DRAMDCA go */ + r_ddr_setval_ach(PI_DRAMDCA_LVL_REQ, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = r_pi_int_ack_0_assert(26U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + /* result for DRAMDCA flip-0 */ + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS0_F2); + dca_result_u_0[ch][0] = mr30_conv[dataL >> 4]; + dca_result_l_0[ch][0] = mr30_conv[dataL & 0x0FU]; + if ((rank & 0x02U) != 0x0U) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS1_F2); + dca_result_u_0[ch][1] = mr30_conv[dataL >> 4]; + dca_result_l_0[ch][1] = mr30_conv[dataL & 0x0FU]; + } + } + + /*********************************************************************** + * Run DRAM DCA Training for Flip-1 + ***********************************************************************/ + r_ddr_setval_ach(PI_DRAMDCA_FLIP_MASK, 0x01U); + r_ddr_setval_ach(PI_SEQ_ARRAY_333, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_334, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_335, 0x00000000U); + + /* DRAMDCA go */ + r_ddr_setval_ach(PI_DRAMDCA_LVL_REQ, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = r_pi_int_ack_0_assert(26U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + /* result for DRAMDCA flip-1 */ + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS0_F2); + dca_result_u_1[ch][0] = mr30_conv[dataL >> 4]; + dca_result_l_1[ch][0] = mr30_conv[dataL & 0x0FU]; + if ((rank & 0x02U) != 0x0U) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS1_F2); + dca_result_u_1[ch][1] = mr30_conv[dataL >> 4]; + dca_result_l_1[ch][1] = mr30_conv[dataL & 0x0FU]; + } + } + + /*********************************************************************** + * Calculate and set DRAMDCA value + ***********************************************************************/ + r_foreach_vch((ch)) + { + /* CS0 */ + tempu = (dca_result_u_0[ch][0] + dca_result_u_1[ch][0]) / 2U; + templ = (dca_result_l_0[ch][0] + dca_result_l_1[ch][0]) / 2U; + dataL = (mr30_conv[tempu] << 4) | (mr30_conv[templ]); + r_ddr_setval(ch, PI_DARRAY3_20_CS0_F2, dataL); + if ((rank & 0x02U) != 0x0U) + { + /* CS1 */ + tempu = (dca_result_u_0[ch][1] + dca_result_u_1[ch][1]) / 2U; + templ = (dca_result_l_0[ch][1] + dca_result_l_1[ch][1]) / 2U; + dataL = (mr30_conv[tempu] << 4) | (mr30_conv[templ]); + r_ddr_setval(ch, PI_DARRAY3_20_CS1_F2, dataL); + } + } + + /* set DRAMDCA value in MR30 */ + r_ddr_setval_ach(PI_SEQ_ARRAY_349, 0x01A11E14U); + r_ddr_setval_ach(PI_SEQ_ARRAY_350, 0x001F0000U); + r_ddr_setval_ach(PI_SEQ_DEC_SW_CS, rank); + r_ddr_setval_ach(PI_SW_SEQ_START, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = r_pi_int_ack_0_assert(18U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + r_ddr_setval_ach(PI_SEQ_DEC_SW_CS, 0x00U); + r_ddr_setval_ach(PI_DRAMDCA_FLIP_MASK, 0x02U); + r_ddr_setval_ach(PI_SEQ_ARRAY_333, 0x001101FCU); + r_ddr_setval_ach(PI_SEQ_ARRAY_334, 0x00211A00U); + r_ddr_setval_ach(PI_SEQ_ARRAY_335, 0x00051500U); + + return phytrainingok; +} + +/******************************************************************************* + * Re-run Write Leveling + ******************************************************************************/ +static uint32_t r_write_leveling(void) +{ + uint32_t ch; + uint32_t rank; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + uint32_t complete_ng; + uint32_t wr_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + r_ddr_setval_ach(PI_CALVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WRDCM_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WRLVL_CS_SW, rank); + r_ddr_setval_ach(PI_WRLVL_REQ, 0x01U); + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = ((r_ddr_getval(ch, PI_INT_STATUS)) >> 27); + if ((dataL & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + wr_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Wrlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3)); /* PI_WRLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12)); /* SLICE0 wrlvl error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12)); /* SLICE1 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS); /* SLICE0 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS); /* SLICE1 wrlvl error */ + if (dataL != 0x0U) + { + wr_training_ng |= 1U << ch; + MSG_LF("write_leveling_error:1\n"); + } + } + + complete_ng = wr_training_ng; + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x01U); + } + + return phytrainingok; +} + +/******************************************************************************* + * Manual Write DCA Training + ******************************************************************************/ +static void r_manual_write_dca(void) +{ + uint32_t ch; + uint32_t slice; + uint32_t rank; + uint32_t cs; + uint32_t i; + uint32_t phy_slv_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; + uint32_t phy_slv_dly_avg[DRAM_CH_CNT][SLICE_CNT]; + uint32_t slv_dly_min[DRAM_CH_CNT][SLICE_CNT]; + uint32_t slv_dly_max[DRAM_CH_CNT][SLICE_CNT]; + uint32_t phy_dcc_code_min[DRAM_CH_CNT][SLICE_CNT]; + uint32_t phy_dcc_code_max[DRAM_CH_CNT][SLICE_CNT]; + uint32_t phy_dcc_code_mid; + uint32_t tmp; + uint32_t complete; + uint32_t retry; + const uint32_t RETRY_MAX = 0x10000U; + const uint8_t ratio_min = 0x06U; + const uint8_t ratio_max = 0x03U; + const uint8_t ratio_min_div = 0x0AU; + const uint8_t ratio_max_div = 0x02U; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x02U; + } + else + { + rank = 0x01U; + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + phy_dcc_code_min[ch][slice] = 0x7FU; + phy_dcc_code_max[ch][slice] = 0x00U; + } + } + + for (cs = 0U; cs < rank; cs++) + { + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_INDEX, cs); + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + phy_slv_dly[ch][cs][slice] = r_ddr_getval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY); + } + } + } /* for (cs = 0U; cs < rank; cs++ */ + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if (rank == 0x02U) + { + /* Calculate average between ranks */ + phy_slv_dly_avg[ch][slice] = (phy_slv_dly[ch][0][slice] + phy_slv_dly[ch][1][slice]) / 2U; + } + else + { + phy_slv_dly_avg[ch][slice] = phy_slv_dly[ch][0][slice]; + } + + /* Determine the search range */ + slv_dly_min[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07FU) * ratio_min / ratio_min_div; + slv_dly_max[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07FU) * ratio_max / ratio_max_div; + + if (slv_dly_max[ch][slice] > 0x7FU) + { + slv_dly_max[ch][slice] = 0x7FU; + } + } + } + + complete = 0x00U; + + r_ddr_setval_ach_as(PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x01U); + + for (i = 0U; i <= 0x7FU; i++) + { + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if (slv_dly_max[ch][slice] < (slv_dly_min[ch][slice] + i)) + { + complete |= ((0x01U << ch) << (8U * slice)); + } + else + { + /* CS0/1 same setting, Need masked write */ + r_ddr_setval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY, (slv_dly_min[ch][slice] + i)); + r_ddr_setval_s(ch, slice, SC_PHY_WCK_CALC, 0x01U); + r_ddr_setval(ch, SC_PHY_MANUAL_UPDATE, 0x01U); + } + } + } + + if (complete == (ddr_phyvalid | (ddr_phyvalid << 8))) + { + break; + } + + /* Exec write dca */ + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if ((((complete >> (8U * slice)) >> ch) & 0x01U) != 0x01U) + { + r_ddr_setval_s(ch, slice, PHY_DATA_DC_CAL_START, 0x01U); + } + } + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if ((((complete >> (8U * slice)) >> ch) & 0x01U) != 0x01U) + { + retry = 0U; + while (retry++ < RETRY_MAX) + { + tmp = r_ddr_getval_s(ch, slice, PHY_DATA_DC_CAL_START); + if (tmp == 0x00U) + { + break; + } + } + } + } + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if ((slv_dly_min[ch][slice] + i) <= slv_dly_max[ch][slice]) + { + tmp = (r_ddr_getval_s(ch, slice, PHY_DATA_DC_DQS_CLK_ADJUST)); + if ((tmp >> 6) == 0x01U) + { + tmp = 0x00U; + } + else if ((tmp >> 6) == 0x02U) + { + tmp = 0x3FU; + } + else + { + ; /* Nothing */ + } + + if (tmp < phy_dcc_code_min[ch][slice]) + { + phy_dcc_code_min[ch][slice] = tmp; + } + + if (phy_dcc_code_max[ch][slice] < tmp) + { + phy_dcc_code_max[ch][slice] = tmp; + } + } + } + } + } /* for (i = 0U; i <= 0x7FU; i++) */ + + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U); + + for (cs = 0U; cs < rank; cs++) + { + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_INDEX, cs); + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + r_ddr_setval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY, phy_slv_dly[ch][cs][slice]); + r_ddr_setval_s(ch, slice, SC_PHY_WCK_CALC, 0x01U); + r_ddr_setval(ch, SC_PHY_MANUAL_UPDATE, 0x01U); + } + } + } + + r_ddr_setval_ach_as(PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x00U); + + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01U); + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + phy_dcc_code_mid = (phy_dcc_code_min[ch][slice] + phy_dcc_code_max[ch][slice]) / 2U; + r_ddr_setval_s(ch, slice, PHY_DATA_DC_DQS_CLK_ADJUST, phy_dcc_code_mid); + } + } +} + +/******************************************************************************* + * Re-run Read Gate Training + ******************************************************************************/ +static uint32_t r_read_gate_training(void) +{ + uint32_t ch; + uint32_t rank; + uint32_t dataL; + uint32_t phytrainingok; + uint32_t retry; + uint32_t complete_ng; + uint32_t gt_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + r_ddr_setval_ach(PI_WRLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x01U); + r_ddr_setval_ach(PI_RDLVL_CS_SW, rank); + r_ddr_setval_ach(PI_RDLVL_GATE_REQ, 0x01U); + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = ((r_ddr_getval(ch, PI_INT_STATUS)) >> 22); + if ((dataL & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + gt_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Gtlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 2)); /* PI_RDLVL_GATE_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7)); /* SLICE0 delay setup error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7)); /* SLICE1 delay setup error */ + if (dataL != 0x0U) + { + gt_training_ng |= 1U << ch; + MSG_LF("read_gate_training_error\n"); + } + } + + complete_ng = gt_training_ng; + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x01U); + } + + return phytrainingok; +} + +/*********************************************************************** + * Read Data Training with VREF Training + ***********************************************************************/ +static uint32_t r_read_vref_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + uint32_t rank; + uint32_t curr_rank; + uint32_t vref_start, vref_stop, vref_step; + uint32_t vref_stop_index; + uint32_t dvw_min_byte0[DRAM_CH_CNT], dvw_min_byte1[DRAM_CH_CNT]; + uint32_t obs_sel; + uint32_t win_byte0, win_byte1; + uint32_t best_vref_byte0, best_vref_byte1; + uint32_t best_vref_byte0_index, best_vref_byte1_index; + uint32_t best_dvw_min_byte0, best_dvw_min_byte1; + uint32_t best_thrshld; + uint32_t vref_outlier; + uint32_t best_lower_vref, best_upper_vref; + uint32_t outlier_cnt; + uint32_t tempLE, tempTE; + uint32_t dvw_min_byte0_table[DRAM_CH_CNT][128]; + uint32_t dvw_min_byte1_table[DRAM_CH_CNT][128]; + int32_t i; + + const uint32_t RETRY_MAX = 0x10000U; + + best_vref_byte0_index = 0U; + best_vref_byte1_index = 0U; + phytrainingok = 0U; + + for (ch = 0U; ch < DRAM_CH_CNT; ch++) + { + dvw_min_byte0[ch] = 0x0U; + dvw_min_byte1[ch] = 0x0U; + } + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x02U; + } + else + { + rank = 0x01U; + } + + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F0, 0x00U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F1, 0x00U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F2, 0x00U); + r_ddr_setval_ach_as(PHY_VREF_TRAINING_CTRL, 0x00U); + + /* ch0 vref_point */ + vref_start = r_ddr_getval(0U, PHY_VREF_INITIAL_START_POINT); + vref_stop = r_ddr_getval(0U, PHY_VREF_INITIAL_STOP_POINT); + vref_step = r_ddr_getval(0U, PHY_VREF_INITIAL_STEPSIZE); + vref_stop_index = (vref_stop - vref_start) / vref_step; + + if (vref_stop_index > 0x80U) + { + return phytrainingok; + } + + for (i = 0; i <= vref_stop_index; i++) + { + r_foreach_vch((ch)) + { + dataL = (r_ddr_getval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | (vref_start + (vref_step * i)))); + dataL = (r_ddr_getval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | (vref_start + (vref_step * i)))); + } + + for (curr_rank = 0U; curr_rank < rank; curr_rank++) + { + /* All ch Read Training Start */ + r_ddr_setval_ach(PI_RDLVL_CS_SW, (0x1U << curr_rank)); + r_ddr_setval_ach(PI_RDLVL_REQ, 0x01U); + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if (((dataL >> 23) & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + /* Read Training End */ + r_ddr_setval_ach(PI_INT_ACK_0, (0x1U << 23)); + + r_foreach_vch((ch)) + { + /* minimum Data Valie Window for each VREF */ + dvw_min_byte0[ch] = 0xFFFFFFFFU; + dvw_min_byte1[ch] = 0xFFFFFFFFU; + for (obs_sel = 0x00U; obs_sel < 0x19U; obs_sel++) + { + if ((obs_sel < 0x11U) || (obs_sel == 0x18U)) + { + r_ddr_setval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_OBS_SELECT, obs_sel); + r_ddr_setval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_OBS_SELECT, obs_sel); + + tempLE = r_ddr_getval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + tempTE = r_ddr_getval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + if (tempTE > tempLE) + { + win_byte0 = tempTE - tempLE; + } + else + { + win_byte0 = 0U; + } + tempLE = r_ddr_getval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + tempTE = r_ddr_getval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + if (tempTE > tempLE) + { + win_byte1 = tempTE - tempLE; + } + else + { + win_byte1 = 0U; + } + + if (dvw_min_byte0[ch] > win_byte0) + { + dvw_min_byte0[ch] = win_byte0; + } + if (dvw_min_byte1[ch] > win_byte1) + { + dvw_min_byte1[ch] = win_byte1; + } + } + } + } + } /* For all memory rank */ + r_foreach_vch((ch)) + { + dvw_min_byte0_table[ch][i] = dvw_min_byte0[ch]; + dvw_min_byte1_table[ch][i] = dvw_min_byte1[ch]; + } + } /* For all vref_stop_index steps */ + + r_foreach_vch((ch)) + { + /* Search best VREF byte0 */ + best_vref_byte0 = vref_start; + best_vref_byte0_index = 0U; + best_dvw_min_byte0 = dvw_min_byte0_table[ch][0U]; + for (i = 0; i <= vref_stop_index; i++) + { + if (best_dvw_min_byte0 < dvw_min_byte0_table[ch][i]) + { + best_vref_byte0 = vref_start + (vref_step * i); + best_vref_byte0_index = i; + best_dvw_min_byte0 = dvw_min_byte0_table[ch][i]; + } + } + + /* Search best_lower VREF byte0 */ + dataL = r_ddr_getval_s(ch, 0U, PHY_RDLVL_DLY_STEP); + if (dataL == 0U) + { + best_thrshld = r_ddr_getval_s(ch, 0U, PHY_RDLVL_BEST_THRSHLD); + } + else + { + best_thrshld = r_ddr_getval_s(ch, 0U, PHY_RDLVL_BEST_THRSHLD) * dataL; + } + + vref_outlier = r_ddr_getval_s(ch, 0U, PHY_RDLVL_VREF_OUTLIER); + best_lower_vref = best_vref_byte0; + outlier_cnt = vref_outlier; + for (i = best_vref_byte0_index; i >= 0; i--) + { + if (dvw_min_byte0_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) + { + best_lower_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + if (i == 0) + { + break; + } + } + + /* Search best_upper VREF byte0 */ + vref_outlier = r_ddr_getval_s(ch, 0U, PHY_RDLVL_VREF_OUTLIER); + best_upper_vref = best_vref_byte0; + outlier_cnt = vref_outlier; + for (i = best_vref_byte0_index; i <= vref_stop_index; i++) + { + if (dvw_min_byte0_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) + { + best_upper_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + } + + /* Calculate center of best vref range byte0 */ + best_vref_byte0 = (best_lower_vref + best_upper_vref) / 2U; + + /* Search best VREF byte1 */ + best_vref_byte1 = vref_start; + best_vref_byte1_index = 0U; + best_dvw_min_byte1 = dvw_min_byte1_table[ch][0U]; + for (i = 0; i <= vref_stop_index; i++) + { + if (best_dvw_min_byte1 < dvw_min_byte1_table[ch][i]) + { + best_vref_byte1 = vref_start + (vref_step * i); + best_vref_byte1_index = i; + best_dvw_min_byte1 = dvw_min_byte1_table[ch][i]; + } + } + + /* Search best_lower VREF byte1 */ + dataL = r_ddr_getval_s(ch, 1U, PHY_RDLVL_DLY_STEP); + if (dataL == 0U) + { + best_thrshld = r_ddr_getval_s(ch, 1U, PHY_RDLVL_BEST_THRSHLD); + } + else + { + best_thrshld = r_ddr_getval_s(ch, 1U, PHY_RDLVL_BEST_THRSHLD) * dataL; + } + + vref_outlier = r_ddr_getval_s(ch, 1U, PHY_RDLVL_VREF_OUTLIER); + best_lower_vref = best_vref_byte1; + outlier_cnt = vref_outlier; + for (i = best_vref_byte1_index; i >= 0; i--) + { + if (dvw_min_byte1_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) + { + best_lower_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + if (i == 0) + { + break; + } + } + + /* Search best_upper VREF byte1 */ + vref_outlier = r_ddr_getval_s(ch, 1U, PHY_RDLVL_VREF_OUTLIER); + best_upper_vref = best_vref_byte1; + outlier_cnt = vref_outlier; + for (i = best_vref_byte1_index; i <= vref_stop_index; i++) + { + if (dvw_min_byte1_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) + { + best_upper_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + } + + /* Calculate center of best vref range byte1 */ + best_vref_byte1 = (best_lower_vref + best_upper_vref) / 2U; + + dataL = (r_ddr_getval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | best_vref_byte0)); + dataL = (r_ddr_getval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | best_vref_byte1)); + } + + return phytrainingok; +} + +/******************************************************************************* + * Read Data & RDDQ Training with best VREF & Write DQ VREF Training + ******************************************************************************/ +static uint32_t r_read_write_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + uint32_t complete_ng; + uint32_t rd_training_ng; + uint32_t wdq_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + /* RDDQ_SLAVE_DELAY Set 0x0000 */ + r_ddr_setval_ach_as(PHY_RDDQ0_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ1_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ2_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ3_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ4_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ5_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ6_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ7_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDM_SLAVE_DELAY, 0x0000U); + + r_ddr_setval_ach(PI_WRLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_WDQLVL_EN_F2, 0x03U); + + r_ddr_setval_ach(PI_TRAIN_ALL_FREQ_REQ, 0x01U); + + /* Freq Change High to High */ + dataL = r_pll3_freq(); + if (dataL != 0x0U) + { + return (1); + } + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if ((dataL & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + rd_training_ng = 0x0U; + wdq_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Rdlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 1)); /* PI_RDLVL_ERROR_BIT */ + if (dataL != 0x0U) + { + rd_training_ng |= 1U << ch; + MSG_LF("read_write_training_error:1\n"); + } + + /* Wdqlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 5)); /* PI_WDQLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18)); /* SLICE0 wdqlvl_fail_dqZ */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18)); /* SLICE1 wdqlvl_fail_dqZ */ + if (dataL != 0x0U) + { + wdq_training_ng |= 1U << ch; + MSG_LF("read_write_training_error:2\n"); + } + } + + complete_ng = (wdq_training_ng | rd_training_ng); + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x01U); + } + + return phytrainingok; +} + +/*********************************************************************** + * Correct RDDQ Training result & Re-Run Read Data Training + ***********************************************************************/ +static uint32_t r_read_training(void) +{ + uint32_t ch; + uint32_t slice; + uint32_t rank; + uint32_t i; + uint32_t phytrainingok; + uint32_t dataL; + uint32_t complete_ng; + uint32_t rd_training_ng; + uint32_t rddq_delay_offset; + uint32_t rddq_delay_max; + + const uint32_t rddq_delay_addr[9] = + { + PHY_RDDQ0_SLAVE_DELAY, PHY_RDDQ1_SLAVE_DELAY, PHY_RDDQ2_SLAVE_DELAY, + PHY_RDDQ3_SLAVE_DELAY, PHY_RDDQ4_SLAVE_DELAY, PHY_RDDQ5_SLAVE_DELAY, + PHY_RDDQ6_SLAVE_DELAY, PHY_RDDQ7_SLAVE_DELAY, PHY_RDDM_SLAVE_DELAY + }; + + const uint32_t rddq_delay_offset_ps = 0x19U; + const uint32_t rddq_delay_max_ps = 0x67U; + + rddq_delay_offset = rddq_delay_offset_ps * ddr_mbps * 256U / (ddr_mbpsdiv * 2U * 1000000U); + rddq_delay_max = rddq_delay_max_ps * ddr_mbps * 256U / (ddr_mbpsdiv * 2U * 1000000U); + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + for (i = 0U; i < 9U; i++) + { + dataL = r_ddr_getval_s(ch, slice, rddq_delay_addr[i]) + rddq_delay_offset; + if (dataL > rddq_delay_max) + { + dataL = rddq_delay_max; + } + r_ddr_setval_s(ch, slice, rddq_delay_addr[i], dataL); + } + } + } + + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_1, 0x00089080U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_2, 0x000811C0U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_3, 0x040811C0U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_4, 0x02000000U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_5, 0x00000000U); + r_ddr_setval_ach(PI_RDLVL_CS_SW, rank); + + /* Read training go */ + r_ddr_setval_ach(PI_RDLVL_REQ, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = 0x0U; + phytrainingok = r_pi_int_ack_0_assert(23U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + complete_ng = 0x0U; + rd_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Rdlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 1)); /* PI_RDLVL_ERROR_BIT */ + if (dataL != 0x0U) + { + rd_training_ng |= 1U << ch; + MSG_LF("read_training_error\n"); + } + } + + complete_ng = rd_training_ng; + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + return phytrainingok; +} + +/******************************************************************************* + * DDR mode register setting + ******************************************************************************/ +static void r_ddr_register_set(void) +{ + /* MR28 ZQ Mode: Command-Based ZQ Calibration, ZQ interval: Background Cal Interval < 64ms */ + r_send_dbcmd(0x0E841C24U); +} + +/******************************************************************************* + * DDR mode register read + ******************************************************************************/ +static void r_ddr_register_read(void) +{ + uint32_t dataL; + + dataL = (uint32_t)(Boardcnf->bdcfg_rfm_chk); + if (dataL != 0x0U) + { + /* MR27 rank0 */ + r_send_dbcmd(0x0F801B00U); + /* MR57 rank0 */ + r_send_dbcmd(0x0F803900U); + + if (ch_have_this_cs[1] != 0x0U) + { + /* MR27 rank1 */ + r_send_dbcmd(0x0F811B00U); + /* MR57 rank1 */ + r_send_dbcmd(0x0F813900U); + } + } +} + +/******************************************************************************* + * Training handshake functions + ******************************************************************************/ +static uint32_t r_pi_int_ack_0_assert(uint32_t bit) +{ + uint32_t dataL; + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + const uint32_t RETRY_MAX = 0x10000U; + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if (((dataL >> bit) & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, (0x1U << bit)); + } + return phytrainingok; +} + +static void r_wait_dbpdstat1(uint32_t status) +{ + uint32_t i, ch, dataL; + uint32_t freqchg_req_chk; + + for (i = 0U; i < 2U; i++) + { + do + { + dataL = status; + freqchg_req_chk = 0U; + r_foreach_vch((ch)) + { + dataL &= mmio_read_32(DBSC_DBPDSTAT1(ch)); + freqchg_req_chk |= mmio_read_32(DBSC_DBPDSTAT0(ch)); + } + } while ((dataL != status) && ((freqchg_req_chk & 0x1U) == 0x0U)); + } +} + +static uint32_t r_wait_freqchgreq(uint32_t req_assert) +{ + uint32_t dataL; + uint32_t count; + uint32_t ch; + + count = 0xFFFFFFU; + + if (req_assert != 0x0U) + { + do + { + dataL = 1U; + r_foreach_vch((ch)) + { + dataL &= mmio_read_32(DBSC_DBPDSTAT0(ch)); + } + count = count - 1U; + } while (((dataL & 0x1U) != 0x1U) && (count != 0U)); + } + else + { + do + { + dataL = 0U; + r_foreach_vch((ch)) + { + dataL |= mmio_read_32(DBSC_DBPDSTAT0(ch)); + } + count = count - 1U; + } while (((dataL & 0x1U) != 0x0U) && (count != 0U)); + } /* (req_assert != 0x0U) */ + + return (count == 0U); +} + +static void r_set_freqchgack(uint32_t ack_assert) +{ + uint32_t ch; + uint32_t dataL; + + if (ack_assert != 0x0U) + { + dataL = 0x0000CF01U; + } + else + { + dataL = 0x00000000U; + } + + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDCNT2(ch), dataL); + } +} + +static uint32_t r_pll3_freq(void) +{ + uint32_t timeout; + uint32_t fsel; + + (void)r_wait_freqchgreq(1); + + fsel = (0x0300U & mmio_read_32(DBSC_DBPDSTAT0(0U))) >> 8; + if (fsel == 0U) + { + r_pll3_control(PLL3_LOW_FREQUENCY_MODE); /* Low frequency mode */ + } + else if (fsel == 1U) + { + r_pll3_control(PLL3_MEDIUM_FREQUENCY_MODE); /* Medium frequency mode */ + } + else + { + r_pll3_control(PLL3_HIGH_FREQUENCY_MODE); /* High frequency mode */ + } + + r_set_freqchgack(1U); + + timeout = r_wait_freqchgreq(0); + r_set_freqchgack(0U); + + if (timeout != 0x0U) + { + FATAL_MSG("Time out\n"); + return (1); + } + + r_wait_dbpdstat1(0x07U); + + return (0); +} + +/******************************************************************************* + * Initialize ddr + ******************************************************************************/ +static uint32_t r_init_ddr(void) +{ + uint32_t phytrainingok; + uint32_t ch; + uint32_t err; + + MSG_LF("init_ddr:0\n"); +#ifdef DDR_BACKUPMODE + R_DRAM_Get_Boot_Status(&ddrBackup); +#endif /* DDR_BACKUPMODE */ + + /*********************************************************************** + * PLL3 initialization setting + **********************************************************************/ + /* Reset Status Monitor clear */ + r_cpg_write_32(CPG_FSRCHKCLRR4, 0x00000200U); + /* Reset Status Monitor set */ + r_cpg_write_32(CPG_FSRCHKSETR4, 0x00000200U); + /* ddrphy soft reset assert */ + r_cpg_write_32(CPG_SRCR4, mmio_read_32(CPG_SRCR4) | 0x00000200U); + /* wait reset FB */ + while ((mmio_read_32(CPG_FSRCHKRA4) & 0x00000200U) != 0U) + { + ; /* Nothing */ + } + /* Reset Status Monitor clear */ + r_cpg_write_32(CPG_FSRCHKCLRR4, 0x00000200U); + +#if (RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE == 1U) + r_pll3_control(PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER); /* Initialize PLL3 setting */ +#else + r_pll3_control(PLL3_HIGH_FREQUENCY_MODE); /* Initialize PLL3 setting */ +#endif /* (RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE == 1U) */ + + /* ddrphy soft reset negate */ + r_cpg_write_32(CPG_SRSTCLR4, 0x00000200U); + while ((mmio_read_32(CPG_SRCR4) & 0x00000200U) != 0U) + { + ; /* Nothing */ + } + + /*********************************************************************** + * unlock phy + **********************************************************************/ + /* Unlock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU); + } + + /*********************************************************************** + * dbsc register pre-setting + ***********************************************************************/ + r_dbsc_regset_pre(); + + /*********************************************************************** + * load ddrphy registers + ***********************************************************************/ + r_ddrtbl_load(); + + /*********************************************************************** + * configure ddrphy registers + ***********************************************************************/ + r_ddr_config(); + + /*********************************************************************** + * ddr backupmode end + ***********************************************************************/ +#ifdef DDR_BACKUPMODE + if (ddrBackup != 0x0U) + { + NOTICE("[WARM_BOOT]\n"); + } + else + { + NOTICE("[COLD_BOOT]\n"); + } + + err = R_DRAM_Update_Boot_Status(ddrBackup); + if (err != 0x0U) + { + NOTICE("[BOOT_STATUS_UPDATE_ERROR]\n"); + return INITDRAM_ERR_I; + } +#endif /* DDR_BACKUPMODE */ + MSG_LF("init_ddr:1\n"); + + /*********************************************************************** + * dbsc register set + ***********************************************************************/ + r_dbsc_regset(); + + MSG_LF("init_ddr:2\n"); + + /*********************************************************************** + * dfi_init_start (start ddrphy) & exec pi_training + ***********************************************************************/ + phytrainingok = r_pi_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:1\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:3\n"); + + /*********************************************************************** + * frequency selection change (F1->F2) + ***********************************************************************/ + r_ddr_setval_ach(PHY_FREQ_SEL_INDEX, 0x01U); + r_ddr_setval_ach(PHY_FREQ_SEL_MULTICAST_EN, 0x00U); +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + if (med_freq_en == 0x01U) + { + r_ddr_setval_ach(PI_WDQLVL_VREF_EN, 0x01U); + r_ddr_setval_ach(PI_FREQ_MAP, 0x04U); + r_ddr_setval_ach(PI_INIT_WORK_FREQ, 0x02U); + } +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ + + /*********************************************************************** + * write leveling cycle adjust + ***********************************************************************/ + r_write_leveling_adjust(); + + MSG_LF("init_ddr:4\n"); + + /*********************************************************************** + * exec write leveling & read gate training + ***********************************************************************/ + phytrainingok = r_wl_gt_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:2\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:5\n"); + + /*********************************************************************** + * exec write dca training + ***********************************************************************/ + r_write_dca(); + + MSG_LF("init_ddr:6\n"); + + /*********************************************************************** + * exec dram dca training + ***********************************************************************/ + phytrainingok = r_dramdca_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:3\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:7\n"); + + /*********************************************************************** + * exec write leveling + ***********************************************************************/ + phytrainingok = r_write_leveling(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:4\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:8\n"); + + /*********************************************************************** + * exec manual write dca training + ***********************************************************************/ + r_manual_write_dca(); + + MSG_LF("init_ddr:9\n"); + + /*********************************************************************** + * exec read gate training + ***********************************************************************/ + phytrainingok = r_read_gate_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:5\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:10\n"); + + /*********************************************************************** + * exec read vref training + ***********************************************************************/ + phytrainingok = r_read_vref_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:6\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:11\n"); + + /*********************************************************************** + * exec read dq & write dq training with best vref + ***********************************************************************/ + phytrainingok = r_read_write_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:7\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:12\n"); + + /*********************************************************************** + * correct rddq training result & exec read dq training + ***********************************************************************/ + phytrainingok = r_read_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:8\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:13\n"); + + /*********************************************************************** + * PER_CS_TRAINING_MULTICAST SET (disable) + ***********************************************************************/ + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U); + + /*********************************************************************** + * Restore PI_SEQ_ARRAY for DFS + ***********************************************************************/ +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + if (med_freq_en == 0x01U) + { + r_ddr_setval_ach(PI_SEQ_ARRAY_29, 0x11910048U); + r_ddr_setval_ach(PI_SEQ_ARRAY_64, 0x1810214AU); + r_ddr_setval_ach(PI_SEQ_ARRAY_65, 0x1810314BU); + r_ddr_setval_ach(PI_SEQ_ARRAY_66, 0x18101149U); + r_ddr_setval_ach(PI_SEQ_ARRAY_67, 0x18061180U); + r_ddr_setval_ach(PI_SEQ_ARRAY_68, 0x18067FC0U); + r_ddr_setval_ach(PI_SEQ_ARRAY_69, 0x18101149U); + r_ddr_setval_ach(PI_SEQ_ARRAY_70, 0x18051200U); + r_ddr_setval_ach(PI_SEQ_ARRAY_71, 0x19A11C15U); + r_ddr_setval_ach(PI_SEQ_ARRAY_72, 0x19A11009U); + r_ddr_setval_ach(PI_FREQ_MAP, 0x07U); + } +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ + MSG_LF("init_ddr:14\n"); + + /*********************************************************************** + * setup DDR mode registers + ***********************************************************************/ + /* MRS */ + r_ddr_register_set(); + + /* MRR */ + r_ddr_register_read(); + + MSG_LF("init_ddr:15\n"); + + /*********************************************************************** + * training complete, setup dbsc + ***********************************************************************/ + r_dbsc_regset_post(); + + MSG_LF("init_ddr:16\n"); + + /*********************************************************************** + * lock phy + ***********************************************************************/ + /* Lock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U); + } + + return phytrainingok; +} + +/******************************************************************************* + * DDR Initialize entry + ******************************************************************************/ +uint32_t R_DRAM_Init(void) +{ + uint32_t ch, cs; + uint32_t dataL; + uint32_t failcount; + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00001234U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00001234U); + + /*********************************************************************** + * Judge product and cut + ***********************************************************************/ + Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; + + if (Prr_Product != PRR_PRODUCT_V4M) + { + FATAL_MSG("DDR:Unknown Product\n"); + return 0xFFU; + } + else if (Prr_Cut > 0xFFU) + { + FATAL_MSG("DDR:Unknown Product Version\n"); + return 0xFFU; + } + else + { + ; /* Nothing */ + } + + /*********************************************************************** + * Judge board type + ***********************************************************************/ + BOARDTYPE = r_boardcnf_get_brd_type(); + if (BOARDTYPE >= BOARDNUM) + { + FATAL_MSG("DDR:Unknown Board\n"); + return 0xFFU; + } + + Boardcnf = (const st_boardcnf_t *)&boardcnfs[BOARDTYPE]; + + ddr_phyvalid = (uint32_t)(Boardcnf->bdcfg_phyvalid); + + max_density = 0U; + + for (cs = 0U; cs < CS_CNT; cs++) + { + ch_have_this_cs[cs] = 0U; + } + + r_foreach_ech((ch)) + { + for (cs = 0U; cs < CS_CNT; cs++) + { + ddr_density[ch][cs] = 0xFFU; + } + } + + r_foreach_vch((ch)) + { + for (cs = 0U; cs < CS_CNT; cs++) + { + dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_ddr_density[cs]); + ddr_density[ch][cs] = dataL; + if (dataL == 0xFFU) + { + continue; + } + if (dataL > max_density) + { + max_density = dataL; + } + ch_have_this_cs[cs] |= (1U << ch); + } + } + + /*********************************************************************** + * Judge board clock frequency (in MHz) + ***********************************************************************/ + r_boardcnf_get_brd_clk(BOARDTYPE, &brd_clk, &brd_clkdiv); + if (((0x01U << 14) & mmio_read_32(RST_MODEMR0)) != 0x0U) + { + brd_clkdiva = 1U; + } + else + { + brd_clkdiva = 0U; + } + + /*********************************************************************** + * Judge ddr operating frequency clock(in Mbps) + ***********************************************************************/ + r_boardcnf_get_ddr_mbps(BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv, &sscg, &med_freq_en); + + ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U)); + ddr_mul_low = CLK_DIV(6400U, 1U * 2U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U)); + + if (ddr_mbps >= (PLL3_MEDIUM_FREQUENCY_THRESHOLD * ddr_mbpsdiv * 4U)) + { + /* divider N = 8 */ + ddr_medium_div = 0x04U; + } + else if (ddr_mbps >= (PLL3_MEDIUM_FREQUENCY_THRESHOLD * ddr_mbpsdiv * 3U)) + { + /* divider N = 6 */ + ddr_medium_div = 0x03U; + } + else + { + /* divider N = 4 */ + ddr_medium_div = 0x02U; + } + + if ((sscg == 0x1U) || (sscg == 0x3U)) + { + ddr_mul_reg = ddr_mul_low - 2U; + } + else + { + ddr_mul_reg = ddr_mul_low; + } + +#if (RCAR_PLL3_FRAC_MODE == 1U) + ddr_mul_nf = ((8U * ddr_mbps * brd_clkdiv * (brd_clkdiva + 1U)) / (ddr_mbpsdiv * brd_clk * 2U)) - (8U * (ddr_mul / 2U) * 2U); +#else + ddr_mul_nf = 0x00U; +#endif /* (RCAR_PLL3_FRAC_MODE == 1U) */ + + dataL = 0x03U & (mmio_read_32(RST_MODEMR0) >> 13); + bus_clk = 0U; + bus_clkdiv = 0U; + + switch (dataL) + { + case 0U: + bus_clk = brd_clk * 0x18U; + bus_clkdiv = brd_clkdiv; + break; + case 1U: + bus_clk = brd_clk * 0x14U; + bus_clkdiv = brd_clkdiv; + break; + case 2U: + /* Not supported */ + bus_clk = brd_clk * 0x20U; + bus_clkdiv = brd_clkdiv * 2U; + break; + case 3U: + bus_clk = brd_clk * 0x18U; + bus_clkdiv = brd_clkdiv * 2U; + break; + default: + bus_clk = brd_clk * 0x18U; + bus_clkdiv = brd_clkdiv * 2U; + break; + } + + /*********************************************************************** + * Adjust tccd + ***********************************************************************/ + ddr_tccd = 2U; + +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + if (med_freq_en == 0x01U) + { + NOTICE("DDR%d/%d(%s)\n", ddr_mbps / ddr_mbpsdiv, ddr_mbps / ddr_mbpsdiv / ddr_medium_div, RCAR_DDR_VERSION); + } + else + { + NOTICE("DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); + } +#else + NOTICE("DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ + + MSG_LF("Start\n"); + + /*********************************************************************** + * initialize DDR + ***********************************************************************/ + dataL = r_init_ddr(); + if (dataL == ddr_phyvalid) + { + failcount = 0U; + } + else + { + failcount = 1U; + } + + NOTICE("..%d\n", failcount); + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00000000U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00000000U); + + if (failcount == 0U) + { + return INITDRAM_OK; + } + else + { + return INITDRAM_NG; + } +} + +#if (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) +void r_set_pi_rdlvl_interval(void) +{ + uint32_t ch; + uint32_t dataL; + uint32_t ctrl_clk; + uint32_t clk_count; + uint32_t phymster_req_interval; + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00001234U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00001234U); + + /* Unlock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU); + } + + /* PI_INT_STATUS clear */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x01U); + } + + /* wait wdq training done */ + (void)r_pi_int_ack_0_assert(29U); + + /* set pi_rdlvl_interval */ + phymster_req_interval = PERIODIC_TRAINING_INTERVAL - 3000U; + clk_count = 1024U - (r_ddrtbl_getval_pi(DDR_PI_REGSET, PI_LONG_COUNT_MASK) * 32U); + ctrl_clk = ddr_mbps / ddr_mbpsdiv / 8U; + dataL = phymster_req_interval * ctrl_clk / clk_count; + r_ddr_setval_ach(PI_RDLVL_INTERVAL, dataL); + + /* Lock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U); + } + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00000000U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00000000U); +} +#endif /* (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) */ + +/******************************************************************************* + * END + ******************************************************************************/ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.c new file mode 100644 index 0000000..be344b9 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.c @@ -0,0 +1,240 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#else +#include "mem_io.h" +#include "log.h" +#endif +#include "boot_init_dram_regdef.h" +#include "boot_init_dram_config.h" + +/******************************************************************************* + * PLEASE SET board number or board judge function + ******************************************************************************/ +#define BOARD_JUDGE_AUTO +#ifdef BOARD_JUDGE_AUTO +static uint32_t r_board_judge(void); +uint32_t r_boardcnf_get_brd_type(void) +{ + return r_board_judge(); +} +#else /* BOARD_JUDGE_AUTO */ +uint32_t r_boardcnf_get_brd_type(void) +{ + return (0); +} +#endif /* BOARD_JUDGE_AUTO */ + +/******************************************************************************* + * EXTAL CLOCK DEFINITION + * PLEASE DEFINE HOW TO JUDGE BORAD CLK + ******************************************************************************/ +/* + * RENESAS GRAY HAWK BOARD EXAMPLE + * judge by md14/md13 + * + * 16.66MHz CLK,DIV= 50,3 (md14,md13==0,0) + * 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1) + * 33.33MHz CLK,DIV=100,3 (md14,md13==1,1) +*/ +void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div) +{ + uint32_t md; + + md = (mmio_read_32(RST_MODEMR0) >> 13) & 0x3U; + switch (md) + { + case 0x0U : *clk = 50U; *clk_div = 3U; break; /* 50 / 3 = 16.66MHz */ + case 0x1U : *clk = 60U; *clk_div = 3U; break; /* 60 / 3 = 20.00MHz */ + case 0x2U : NOTICE("MD14/MD13 is invalid!!\n"); panic; /* Not supported */ + case 0x3U : *clk =100U; *clk_div = 3U; break; /* 100 / 3 = 33.33MHz */ + default : /* Nothing */ break; + } + (void)brd; +} + +/******************************************************************************* + * DDR MBPS TARGET + * PLEASE DEFINE HOW TO JUDGE DDR BPS + ******************************************************************************/ +/* + DDRxxxx (judge by md19,17) : Mbps + SSCG enable / disable for PLL1 (judge by md18/md37/md36) +*/ +void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg, uint32_t *med_freq_en) +{ + uint32_t md; + uint32_t product; + + md = (mmio_read_32(RST_MODEMR0) >> 17) & 0x05U; + md = (md | (md >> 1)) & 0x03U; + *sscg = ((mmio_read_32(RST_MODEMR0) >> 16) & 0x04U) | ((mmio_read_32(RST_MODEMR1) >> 4) & 0x03U); + product = mmio_read_32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK; + + if (product == 0x01U) + { + /* V4M-5 */ + switch (md) + { + case 0x0U : *mbps = 5000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5000Mbps */ + case 0x1U : *mbps = 5000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5000Mbps */ + case 0x2U : *mbps = 5000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5000Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + } + else if (product == 0x02U) + { + /* V4M-3 */ + switch (md) + { + case 0x0U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + case 0x1U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + case 0x2U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + } + else if (product == 0x04U) + { + /* V4M-2 */ + switch (md) + { + case 0x0U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + case 0x1U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + case 0x2U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + } + else + { + /* V4M-7 */ + switch (*sscg) + { + case 0x0U : + switch (md) + { + case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + case 0x1U : + switch (md) + { + case 0x0U : *mbps = 19000U; *mbps_div = 3U; *med_freq_en = 1U; break; /* 6333Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + case 0x2U : + switch (md) + { + case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + case 0x3U : + switch (md) + { + case 0x0U : *mbps = 19000U; *mbps_div = 3U; *med_freq_en = 1U; break; /* 6333Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + case 0x4U : + switch (md) + { + case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + case 0x5U : + switch (md) + { + case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + case 0x6U : + switch (md) + { + case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + case 0x7U : + switch (md) + { + case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + default : + /* Nothing */ + break; + }/* Setting of SSCG */ + } /* (product == 0x01U) */ + + (void)brd; +} + +#ifdef BOARD_JUDGE_AUTO +/******************************************************************************* + * SAMPLE board detect function + ******************************************************************************/ +static uint32_t r_board_judge(void) +{ + uint32_t brd; + + brd = 0U; /* gray hawk (64Gbit 2rank) */ + + return brd; +} +#endif diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.h b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.h new file mode 100644 index 0000000..b8ada4d --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.h @@ -0,0 +1,156 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +#ifndef BOOT_INIT_DRAM_CONFIG_H_ +#define BOOT_INIT_DRAM_CONFIG_H_ + +/******************************************************************************* + * DRAM Param setting + ******************************************************************************/ +#define JS2_DERATE 0U +#define DBSC_REFINT 1920U /* Average periodic refresh interval/Average Refresh Interval [ns] */ +#ifndef DBSC_REFINTS +#define DBSC_REFINTS 0U /* 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. */ +#endif +#define PERIODIC_TRAINING_INTERVAL 20000U /* Periodic-WriteDQ/ReadDQ Training Interval [us] */ + +/******************************************************************************* + * NUMBER OF BOARD CONFIGURATION + * PLEASE DEFINE + ******************************************************************************/ +#define BOARDNUM 2U /* Add User platform BOARD */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +uint32_t r_boardcnf_get_brd_type(void); +void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div); +void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg, uint32_t *med_freq_en); + +/******************************************************************************* + * BOARD CONFIGURATION + * PLEASE DEFINE boardcnfs[] + ******************************************************************************/ +typedef struct +{ + /* + 0x00...0000B: 4Gb dual channel die / 2Gb single channel die + 0x01...0001B: 6Gb dual channel die / 3Gb single channel die + 0x02...0010B: 8Gb dual channel die / 4Gb single channel die + 0x03...0011B: 12Gb dual channel die / 6Gb single channel die + 0x04...0100B: 16Gb dual channel die / 8Gb single channel die + 0x05...0101B: 24Gb dual channel die / 12Gb single channel die + 0x06...0110B: 32Gb dual channel die / 16Gb single channel die + 0x07...0111B: 24Gb single channel die + 0x08...1000B: 32Gb single channel die + 0xFF...NO_MEMORY + */ + uint8_t bdcfg_ddr_density[CS_CNT]; + /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */ + uint32_t bdcfg_ca_swap; + /* SoC dqsX([1][0]) -> MEM dqsY: */ + uint8_t bdcfg_dqs_swap; + /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ + uint32_t bdcfg_dq_swap[SLICE_CNT]; + /* SoC dm -> MEM dqY/dm: (8 means DM) */ + uint8_t bdcfg_dm_swap[SLICE_CNT]; + /* SoC ckeX([1][0]) -> MEM csY */ + uint8_t bdcfg_cs_swap; +} st_boardcnf_ch_t; + +typedef struct +{ + /* ch in use */ + uint8_t bdcfg_phyvalid; + /* Read vref (SoC) training range : [23:16]step / [15:8]stop / [7:0]start, 0x00000000 = default val */ + uint32_t bdcfg_vref_r; + /* Write vref (MR14, MR15) training range : [15:8]stop / [7:0]start, 0x0000 = default val */ + uint16_t bdcfg_vref_w; + /* CA vref (MR12) training range : [15:8]stop / [7:0]start, 0x0000 = default val */ + uint16_t bdcfg_vref_ca; + /* RFM required check : 0x01 = check enable, 0x00 = check disable */ + uint8_t bdcfg_rfm_chk; + + st_boardcnf_ch_t ch[2]; +} st_boardcnf_t; + +static const st_boardcnf_t boardcnfs[BOARDNUM] = { +/* + * boardcnf[0] RENESAS V4M Gray Hawk (64Gbit 2rank) + */ +{ + 0x03U, /* bdcfg_phyvalid */ + 0x00000000U, /* bdcfg_vref_r */ + 0x0000U, /* bdcfg_vref_w */ + 0x0000U, /* bdcfg_vref_ca */ + 0x01U, /* bdcfg_rfm_chk */ + { +/* ch[0] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0x06U }, +/* bdcfg_ca_swap */ 0x06235104U, +/* bdcfg_dqs_swap */ 0x01U, +/* bdcfg_dq_swap[] */ { 0x43061257U, 0x30721685U }, +/* bdcfg_dm_swap[] */ { 0x08U, 0x04U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[1] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0x06U }, +/* bdcfg_ca_swap */ 0x04012653U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x58147026U, 0x70132685U }, +/* bdcfg_dm_swap[] */ { 0x03U, 0x04U }, +/* bdcfg_cs_swap */ 0x10U + } + } +}, +/* + * boardcnf[1] RENESAS V4M (2ch) + */ +{ + 0x03U, /* bdcfg_phyvalid */ + 0x00000000U, /* bdcfg_vref_r */ + 0x0000U, /* bdcfg_vref_w */ + 0x0000U, /* bdcfg_vref_ca */ + 0x01U, /* bdcfg_rfm_chk */ + { +/* ch[0] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0x06U }, +/* bdcfg_ca_swap */ 0x06543210U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U }, +/* bdcfg_dm_swap[] */ { 0x08U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[1] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0x06U }, +/* bdcfg_ca_swap */ 0x06543210U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U }, +/* bdcfg_dm_swap[] */ { 0x08U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + } + } +} +}; + +#endif /* BOOT_INIT_DRAM_CONFIG_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h new file mode 100644 index 0000000..67bfc20 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h @@ -0,0 +1,165 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +#ifndef BOOT_INIT_DRAM_REGDEF_H_ +#define BOOT_INIT_DRAM_REGDEF_H_ + +#if defined(__RH850G3K__) +#include "remap_register.h" +#endif + +#define RCAR_DDR_VERSION "rev.1.00" +#define DRAM_CH_CNT 0x02U +#define SLICE_CNT 0x02U +#define CS_CNT 0x02U + +/* for pll setting */ +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) + +/* for ddr density setting */ +#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30U) | ((row) << 24U) | ((BG) << 20U) | ((bank) << 16U) | ((col) << 8U) | (dw)) +#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density % 2U), (((density + 1U) / 2U) + (28U - 2U - 2U - 10U - 1U)), 2U, 2U, 10U, 1U)) /* 16bit */ + +/* system registers : CPG */ +#define CPG_FRQCRD_KICK_BIT (1U << 31) +#define CPG_PLL3CR0_KICK_BIT (1U << 31) +#define CPG_PLLECR_PLL3ST_BIT (1U << 11) + +#if defined(__RH850G3K__) +#define CPG_BASE (BASE_CPG_ADDR) +#else +#define CPG_BASE (0xE6150000U) +#endif +#define CPG_CPGWPR (CPG_BASE + 0x0000U) +#define CPG_FRQCRD0 (CPG_BASE + 0x080CU) +#define CPG_PLLECR (CPG_BASE + 0x0820U) +#define CPG_PLL3CR0 (CPG_BASE + 0x083CU) +#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U) +#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U) +#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U) +#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U) +#define CPG_SRCR4 (CPG_BASE + 0x2C10U) +#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U) + +#if defined(__RH850G3K__) +#define RST_BASE (BASE_RESET_ADDR) +#else +#define RST_BASE (0xE6160000U) +#endif +#define RST_MODEMR0 (RST_BASE + 0x0000U) +#define RST_MODEMR1 (RST_BASE + 0x0004U) + +#if defined(__RH850G3K__) +#define OTP_MEM_1_BASE (BASE_OTP_MEM_ADDR) +#else +#define OTP_MEM_1_BASE (0xE61BF000U) +#endif +#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U) +#define OTP_MEM_PRODUCT_MASK (0x000000FFU) + +/* Product Register */ +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) + +#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */ + +#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */ +#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */ + +/* DBSC registers */ +#if defined(__RH850G3K__) +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4M DBSC0 clk_dbsc region */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4M DBSC0 clk_axim region */ +#else +#define DBSC_D_BASE (0xE67A4000U) /* forV4M DBSC0 clk_dbsc region */ +#define DBSC_A_BASE (0xE6790000U) /* forV4M DBSC0 clk_axim region */ +#endif + +#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U) +#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U) +#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U) +#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U) +#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U) +#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U) +#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U) +#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U) + +#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + (0x2000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs))) + +#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + (0x4000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs))) + +#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U) + +#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U) +#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U) +#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U) +#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U) + +#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + (0x04U * (x))) + +#define DBSC_DBBL (DBSC_D_BASE + 0x0400U) +#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U) + +#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U) +#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U) + +#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U) + +#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + (0x04U * (x))) + +#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U) +#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U) +#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U) + +#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBPDRGM(ch) (DBSC_D_BASE + 0x062CU + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBBUS0CNF1 (DBSC_A_BASE + 0x0804U) + +#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU) + +#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U) + +#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U) + +#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U) +#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U) + +#endif /* BOOT_INIT_DRAM_REGDEF_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ddr_regdef.h b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ddr_regdef.h new file mode 100644 index 0000000..88b6c08 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ddr_regdef.h @@ -0,0 +1,390 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +#ifndef DDR_REGDEF_H_ +#define DDR_REGDEF_H_ + +#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL 0x10031000U +#define PHY_PER_CS_TRAINING_MULTICAST_EN 0x18011006U +#define PHY_PER_CS_TRAINING_INDEX 0x00011007U +#define PHY_VREF_INITIAL_STEPSIZE 0x1808100EU +#define PHY_RDLVL_BEST_THRSHLD 0x0004100FU +#define PHY_RDLVL_VREF_OUTLIER 0x1003100FU +#define SC_PHY_WCK_CALC 0x1801101BU +#define PHY_WRLVL_PER_START 0x00071020U +#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x08051022U +#define PHY_CALVL_VREF_DRIVING_SLICE 0x08011026U +#define PHY_WRLVL_HARD0_DELAY_OBS 0x000A102DU +#define PHY_WRLVL_HARD1_DELAY_OBS 0x100A102DU +#define PHY_WRLVL_STATUS_OBS 0x001C102EU +#define PHY_WRLVL_ERROR_OBS 0x00021030U +#define PHY_GTLVL_STATUS_OBS 0x00121032U +#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x10091033U +#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x00091034U +#define PHY_WDQLVL_STATUS_OBS 0x00201038U +#define PHY_DATA_DC_CAL_START 0x08011041U +#define PHY_SLV_DLY_CTRL_GATE_DISABLE 0x00011042U +#define PHY_REGULATOR_EN_CNT 0x00061044U +#define PHY_VREF_INITIAL_START_POINT 0x00091048U +#define PHY_VREF_INITIAL_STOP_POINT 0x10091048U +#define PHY_VREF_TRAINING_CTRL 0x00021049U +#define PHY_RDDQ0_SLAVE_DELAY 0x00091050U +#define PHY_RDDQ1_SLAVE_DELAY 0x10091050U +#define PHY_RDDQ2_SLAVE_DELAY 0x00091051U +#define PHY_RDDQ3_SLAVE_DELAY 0x10091051U +#define PHY_RDDQ4_SLAVE_DELAY 0x00091052U +#define PHY_RDDQ5_SLAVE_DELAY 0x10091052U +#define PHY_RDDQ6_SLAVE_DELAY 0x00091053U +#define PHY_RDDQ7_SLAVE_DELAY 0x10091053U +#define PHY_RDDM_SLAVE_DELAY 0x00091054U +#define PHY_RX_CAL_ALL_DLY 0x18061054U +#define PHY_RX_PCLK_CLK_SEL 0x00031055U +#define PHY_DATA_DC_CAL_CLK_SEL 0x08031055U +#define PHY_PAD_VREF_CTRL_DQ 0x100E1058U +#define PHY_PER_CS_TRAINING_EN 0x10011059U +#define PHY_RDDATA_EN_TSEL_DLY 0x0805105BU +#define PHY_RDDATA_EN_OE_DLY 0x1005105BU +#define PHY_RPTR_UPDATE 0x0804105EU +#define PHY_WRLVL_RESP_WAIT_CNT 0x0006105FU +#define PHY_RDLVL_DLY_STEP 0x08041062U +#define PHY_RDLVL_MAX_EDGE 0x00091063U +#define PHY_DATA_DC_WDQLVL_ENABLE 0x08021068U +#define PHY_RDDATA_EN_DLY 0x10051069U +#define PHY_DQ_DM_SWIZZLE0 0x0020106AU +#define PHY_DQ_DM_SWIZZLE1 0x0004106BU +#define PHY_CLK_WRDQS_SLAVE_DELAY 0x00091071U +#define PHY_WRITE_PATH_LAT_DEC 0x10011071U +#define PHY_RDDQS_LATENCY_ADJUST 0x1005107BU +#define PHY_WRITE_PATH_LAT_ADD 0x1803107BU +#define PHY_WRITE_PATH_LAT_FRAC 0x0008107CU +#define PHY_GTLVL_LAT_ADJ_START 0x0005107DU +#define PHY_DATA_DC_DQS_CLK_ADJUST 0x0008107FU +#define PHY_ADR_CALVL_SWIZZLE0 0x00201202U +#define PHY_ADR_MEAS_DLY_STEP_ENABLE 0x10011203U +#define PHY_ADR_CALVL_RANK_CTRL 0x18021205U +#define PHY_ADR_CALVL_OBS1 0x0020120AU +#define PHY_ADR_CALVL_OBS2 0x0020120BU +#define PHY_ADR_CALVL_DLY_STEP 0x00041210U +#define PHY_CS_ACS_ALLOCATION_BIT2_2 0x08021215U +#define PHY_CS_ACS_ALLOCATION_BIT3_2 0x10021215U +#define PHY_CSLVL_OBS1 0x00201221U +#define PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE 0x1008122DU +#define PHY_CLK_DC_CAL_CLK_SEL 0x0803123AU +#define PHY_FREQ_SEL_MULTICAST_EN 0x08011301U +#define PHY_FREQ_SEL_INDEX 0x10021301U +#define SC_PHY_MANUAL_UPDATE 0x18011304U +#define PHY_SET_DFI_INPUT_RST_PAD 0x18011311U +#define PHY_TCKSRE_WAIT 0x1004131FU +#define PHY_CAL_MODE_0 0x000D132CU +#define PHY_CAL_INTERVAL_COUNT_0 0x0020132DU +#define PHY_DATA_BYTE_ORDER_SEL 0x0020133FU +#define PHY_PAD_ACS_RX_PCLK_CLK_SEL 0x1003134AU +#define PHY_PLL_CTRL 0x000E134DU +#define PHY_PLL_CTRL_8X 0x100E134DU +#define PHY_CAL_CLK_SELECT_0 0x00031361U + +#define PI_START 0x00010800U +#define PI_TRAIN_ALL_FREQ_REQ 0x18010804U +#define PI_FREQ_MAP 0x0020080DU +#define PI_INIT_WORK_FREQ 0x0005080EU +#define PI_CS_MAP 0x08020815U +#define PI_WRLVL_REQ 0x0801081FU +#define PI_WRLVL_CS_SW 0x1002081FU +#define PI_RDLVL_REQ 0x10010827U +#define PI_RDLVL_GATE_REQ 0x18010827U +#define PI_RDLVL_CS_SW 0x00020828U +#define PI_RDLVL_PERIODIC 0x08010831U +#define PI_RDLVL_INTERVAL 0x08100838U +#define PI_DRAMDCA_FLIP_MASK 0x0802083EU +#define PI_DRAMDCA_LVL_REQ 0x10010840U +#define PI_DCMLVL_CS_SW 0x18020840U +#define PI_WRDCM_LVL_EN_F1 0x00020842U +#define PI_DRAMDCA_LVL_EN_F1 0x08020842U +#define PI_WRDCM_LVL_EN_F2 0x18020842U +#define PI_DRAMDCA_LVL_EN_F2 0x00020843U +#define PI_TCKCKEL_F2 0x18040851U +#define PI_WDQLVL_VREF_EN 0x08040852U +#define PI_WDQLVL_PERIODIC 0x00010854U +#define PI_WDQLVL_INTERVAL 0x00100858U +#define PI_INT_STATUS 0x002008B7U +#define PI_INT_ACK_0 0x002008B9U +#define PI_INT_ACK_1 0x000108BAU +#define PI_LONG_COUNT_MASK 0x100508BCU +#define PI_ADDRESS_MUX_0 0x000308BDU +#define PI_ADDRESS_MUX_1 0x080308BDU +#define PI_ADDRESS_MUX_2 0x100308BDU +#define PI_ADDRESS_MUX_3 0x180308BDU +#define PI_ADDRESS_MUX_4 0x000308BEU +#define PI_ADDRESS_MUX_5 0x080308BEU +#define PI_ADDRESS_MUX_6 0x100308BEU +#define PI_DATA_BYTE_SWAP_EN 0x180108BEU +#define PI_DATA_BYTE_SWAP_SLICE0 0x000108BFU +#define PI_DATA_BYTE_SWAP_SLICE1 0x080108BFU +#define PI_PWRUP_SREFRESH_EXIT 0x100108C2U +#define PI_DLL_RST 0x000108C6U +#define PI_TDELAY_RDWR_2_BUS_IDLE_F1 0x000808E8U +#define PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x000808E9U +#define PI_WRLAT_F1 0x100708EDU +#define PI_TWCKENL_RD_ADJ_F1 0x000608EEU +#define PI_TWCKPRE_STATIC_F1 0x080608EEU +#define PI_TWCKPRE_TOGGLE_RD_F1 0x180608EEU +#define PI_WCK_ACTIVE_WR_F1 0x000708EFU +#define PI_WCK_ACTIVE_RD_F1 0x080708EFU +#define PI_CASLAT_F1 0x180708EFU +#define PI_WRLAT_F2 0x000708F0U +#define PI_TWCKENL_WR_ADJ_F2 0x080608F0U +#define PI_TWCKENL_RD_ADJ_F2 0x100608F0U +#define PI_TWCKPRE_STATIC_F2 0x180608F0U +#define PI_TWCKPRE_TOGGLE_RD_F2 0x080608F1U +#define PI_WCK_ACTIVE_WR_F2 0x100708F1U +#define PI_WCK_ACTIVE_RD_F2 0x180708F1U +#define PI_TWCKENL_FS_ADJ_F2 0x000608F2U +#define PI_CASLAT_F2 0x080708F2U +#define PI_TRFC_F1 0x000A08F4U +#define PI_TREF_F1 0x001408F5U +#define PI_TRFC_F2 0x000A08F6U +#define PI_TREF_F2 0x001408F7U +#define PI_WRLVL_EN_F1 0x000208FAU +#define PI_TDFI_WRLVL_WW_F1 0x080A08FAU +#define PI_WRLVL_EN_F2 0x000208FBU +#define PI_TDFI_WRLVL_WW_F2 0x080A08FBU +#define PI_WRLVL_WCKOFF_F2 0x180808FBU +#define PI_RDLVL_EN_F1 0x100208FFU +#define PI_RDLVL_GATE_EN_F1 0x180208FFU +#define PI_RDLVL_EN_F2 0x00020900U +#define PI_RDLVL_GATE_EN_F2 0x08020900U +#define PI_RDLVL_VREF_EN_F0 0x18040900U +#define PI_RDLVL_RDDQ_EN_F1 0x00040902U +#define PI_RDLVL_VREF_EN_F1 0x08040902U +#define PI_RDLVL_VREF_EN_F2 0x18040903U +#define PI_RDLAT_ADJ_F1 0x10090905U +#define PI_RDLAT_ADJ_F2 0x00090906U +#define PI_WRLAT_ADJ_F1 0x18070906U +#define PI_WRLAT_ADJ_F2 0x00070907U +#define PI_TDFI_CALVL_CC_F1 0x000A0909U +#define PI_TDFI_CALVL_CAPTURE_F1 0x100A0909U +#define PI_TDFI_CALVL_CC_F2 0x000A090AU +#define PI_TDFI_CALVL_CAPTURE_F2 0x100A090AU +#define PI_CALVL_EN_F1 0x0802090BU +#define PI_CALVL_EN_F2 0x1002090BU +#define PI_TCAENT_F1 0x000E090DU +#define PI_TCAENT_F2 0x000E090EU +#define PI_TVREF_LONG_F1 0x000A0912U +#define PI_TVRCG_ENABLE_F1 0x100A0912U +#define PI_TVRCG_DISABLE_F1 0x000A0913U +#define PI_TVREF_LONG_F2 0x100A0914U +#define PI_TVRCG_ENABLE_F2 0x000A0915U +#define PI_TVRCG_DISABLE_F2 0x100A0915U +#define PI_CALVL_VREF_INITIAL_START_POINT_F2 0x10070917U +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x18070917U +#define PI_TDFI_CALVL_STROBE_F2 0x0804091AU +#define PI_TXP_F2 0x1005091AU +#define PI_TMRWCKEL_F2 0x1808091AU +#define PI_TCKEHDQS_F1 0x10060921U +#define PI_TFC_F1 0x000A0922U +#define PI_TCKEHDQS_F2 0x10060922U +#define PI_TFC_F2 0x000A0923U +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x10070925U +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x18070925U +#define PI_TDFI_WDQLVL_WR_F1 0x080A0928U +#define PI_TDFI_WDQLVL_RW_F1 0x000A0929U +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x10070929U +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x18070929U +#define PI_WDQLVL_EN_F1 0x0802092AU +#define PI_WDQLVL_RDLAT_ADJ_F1 0x0009092BU +#define PI_WDQLVL_WRLAT_ADJ_F1 0x1009092BU +#define PI_WDQLVL_TWCKENL_RD_ADJ_F1 0x0006092CU +#define PI_TDFI_WDQLVL_WR_F2 0x080A092CU +#define PI_TDFI_WDQLVL_RW_F2 0x000A092DU +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x1007092DU +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x1807092DU +#define PI_WDQLVL_EN_F2 0x0802092EU +#define PI_WDQLVL_RDLAT_ADJ_F2 0x0009092FU +#define PI_WDQLVL_WRLAT_ADJ_F2 0x1009092FU +#define PI_WDQLVL_TWCKENL_RD_ADJ_F2 0x00060930U +#define PI_TRTP_F1 0x18080936U +#define PI_TRP_F1 0x00080937U +#define PI_TRCD_F1 0x08080937U +#define PI_TWTR_S_F1 0x18060937U +#define PI_TWTR_L_F1 0x00060938U +#define PI_TWTR_F1 0x10060938U +#define PI_TWR_F1 0x18080938U +#define PI_TRAS_MAX_F1 0x00100939U +#define PI_TRAS_MIN_F1 0x10090939U +#define PI_TSR_F1 0x1008093AU +#define PI_TRTP_F2 0x0808093BU +#define PI_TRP_F2 0x1008093BU +#define PI_TRCD_F2 0x1808093BU +#define PI_TWTR_S_F2 0x0806093CU +#define PI_TWTR_L_F2 0x1006093CU +#define PI_TWTR_F2 0x0006093DU +#define PI_TWR_F2 0x0808093DU +#define PI_TRAS_MAX_F2 0x1010093DU +#define PI_TRAS_MIN_F2 0x0009093EU +#define PI_TDQSCK_MAX_F2 0x1004093EU +#define PI_TSR_F2 0x0008093FU +#define PI_TMRD_F2 0x0808093FU +#define PI_TDFI_CTRLUPD_MAX_F1 0x00150942U +#define PI_TDFI_CTRLUPD_INTERVAL_F1 0x00200943U +#define PI_TDFI_CTRLUPD_MAX_F2 0x00150944U +#define PI_TDFI_CTRLUPD_INTERVAL_F2 0x00200945U +#define PI_TXSR_F1 0x10100946U +#define PI_TXSR_F2 0x00100947U +#define PI_TINIT_F1 0x0018094EU +#define PI_TINIT1_F1 0x0018094FU +#define PI_TINIT3_F1 0x00180950U +#define PI_TINIT4_F1 0x00180951U +#define PI_TINIT5_F1 0x00180952U +#define PI_TXSNR_F1 0x00100953U +#define PI_TINIT_F2 0x00180954U +#define PI_TINIT1_F2 0x00180955U +#define PI_TINIT3_F2 0x00180956U +#define PI_TINIT4_F2 0x00180957U +#define PI_TINIT5_F2 0x00180958U +#define PI_TXSNR_F2 0x00100959U +#define PI_TZQCAL_F1 0x100C095CU +#define PI_TZQLAT_F1 0x0007095DU +#define PI_TZQCAL_F2 0x100C095EU +#define PI_TZQLAT_F2 0x0007095FU +#define PI_ZQRESET_F1 0x000C0960U +#define PI_ZQRESET_F2 0x100C0960U +#define PI_TDQ72DQ_F1 0x000A0964U +#define PI_TCBTRTW_F1 0x10060964U +#define PI_TDQ72DQ_F2 0x100A0965U +#define PI_TCBTRTW_F2 0x00060966U +#define PI_MC_TRFC_F1 0x100A0968U +#define PI_MC_TRFC_F2 0x000A0969U +#define PI_TDFI_WCK_STOP_F1 0x0808096EU +#define PI_TDFI_WCK_STOP_F2 0x1808096EU +#define PI_CKE_MUX_0 0x1802096FU +#define PI_CKE_MUX_1 0x00020970U +#define PI_SEQ_DEC_SW_CS 0x0002097BU +#define PI_SW_SEQ_START 0x1001097BU +#define PI_SEQ_ARRAY_29 0x001D09C9U +#define PI_SEQ_ARRAY_64 0x001D09ECU +#define PI_SEQ_ARRAY_65 0x001D09EDU +#define PI_SEQ_ARRAY_66 0x001D09EEU +#define PI_SEQ_ARRAY_67 0x001D09EFU +#define PI_SEQ_ARRAY_68 0x001D09F0U +#define PI_SEQ_ARRAY_69 0x001D09F1U +#define PI_SEQ_ARRAY_70 0x001D09F2U +#define PI_SEQ_ARRAY_71 0x001D09F3U +#define PI_SEQ_ARRAY_72 0x001D09F4U +#define PI_SEQ_ARRAY_81 0x001D09FDU +#define PI_SEQ_ARRAY_82 0x001D09FEU +#define PI_SEQ_ARRAY_333 0x001B0AF9U +#define PI_SEQ_ARRAY_334 0x001B0AFAU +#define PI_SEQ_ARRAY_335 0x001B0AFBU +#define PI_SEQ_ARRAY_349 0x001B0B09U +#define PI_SEQ_ARRAY_350 0x001B0B0AU +#define PI_RDLVL_TRAIN_SEQ_1 0x001B0B9EU +#define PI_RDLVL_TRAIN_SEQ_2 0x001B0B9FU +#define PI_RDLVL_TRAIN_SEQ_3 0x001B0BA0U +#define PI_RDLVL_TRAIN_SEQ_4 0x001B0BA1U +#define PI_RDLVL_TRAIN_SEQ_5 0x001B0BA2U +#define PI_SEQ_WAIT_16_F1 0x00180BD2U +#define PI_SEQ_WAIT_16_F2 0x00180BD3U +#define PI_SEQ_WAIT_17_F1 0x00180BD5U +#define PI_SEQ_WAIT_17_F2 0x00180BD6U +#define PI_SEQ_WAIT_18_F2 0x00180BD9U +#define PI_SEQ_WAIT_19_F1 0x00180BDBU +#define PI_SEQ_WAIT_19_F2 0x00180BDCU +#define PI_SEQ_WAIT_20_F1 0x00180BDEU +#define PI_SEQ_WAIT_20_F2 0x00180BDFU +#define PI_SEQ_WAIT_21_F1 0x00180BE1U +#define PI_SEQ_WAIT_21_F2 0x00180BE2U +#define PI_SEQ_WAIT_22_F1 0x00180BE4U +#define PI_SEQ_WAIT_22_F2 0x00180BE5U +#define PI_SEQ_WAIT_23_F1 0x00180BE7U +#define PI_SEQ_WAIT_23_F2 0x00180BE8U +#define PI_SEQ_WAIT_24_F1 0x00180BEAU +#define PI_SEQ_WAIT_24_F2 0x00180BEBU +#define PI_SEQ_WAIT_25_F1 0x00180BEDU +#define PI_SEQ_WAIT_25_F2 0x00180BEEU +#define PI_SEQ_WAIT_26_F1 0x00180BF0U +#define PI_SEQ_WAIT_26_F2 0x00180BF1U +#define PI_SEQ_WAIT_27_F2 0x00180BF4U +#define PI_SEQ_WAIT_31_F1 0x00180BFFU +#define PI_SEQ_WAIT_31_F2 0x00180C00U +#define PI_WP_GAP_0_F1 0x100F0C0DU +#define PI_WP_GAP_0_F2 0x000F0C0EU +#define PI_RP_GAP_0_F1 0x000F0C0FU +#define PI_RP_GAP_0_F2 0x100F0C0FU +#define PI_WR_GAP_S_0_F1 0x100F0C10U +#define PI_WR_GAP_S_0_F2 0x000F0C11U +#define PI_WR_GAP_L_0_F1 0x000F0C12U +#define PI_WR_GAP_L_0_F2 0x100F0C12U +#define PI_RW_GAP_0_F1 0x100F0C13U +#define PI_RW_GAP_0_F2 0x000F0C14U +#define PI_WP_GAP_1_F1 0x000F0C1BU +#define PI_WP_GAP_1_F2 0x100F0C1BU +#define PI_RP_GAP_1_F1 0x100F0C1CU +#define PI_RP_GAP_1_F2 0x000F0C1DU +#define PI_WR_GAP_S_1_F1 0x000F0C1EU +#define PI_WR_GAP_S_1_F2 0x100F0C1EU +#define PI_WR_GAP_L_1_F1 0x100F0C1FU +#define PI_WR_GAP_L_1_F2 0x000F0C20U +#define PI_RW_GAP_1_F1 0x000F0C21U +#define PI_RW_GAP_1_F2 0x100F0C21U +#define PI_WP_GAP_2_F1 0x100F0C28U +#define PI_WP_GAP_2_F2 0x000F0C29U +#define PI_RP_GAP_2_F1 0x000F0C2AU +#define PI_RP_GAP_2_F2 0x100F0C2AU +#define PI_WR_GAP_S_2_F1 0x100F0C2BU +#define PI_WR_GAP_S_2_F2 0x000F0C2CU +#define PI_WR_GAP_L_2_F1 0x000F0C2DU +#define PI_WR_GAP_L_2_F2 0x100F0C2DU +#define PI_RW_GAP_2_F1 0x100F0C2EU +#define PI_RW_GAP_2_F2 0x000F0C2FU +#define PI_WP_GAP_3_F1 0x000F0C36U +#define PI_WP_GAP_3_F2 0x100F0C36U +#define PI_RP_GAP_3_F1 0x100F0C37U +#define PI_RP_GAP_3_F2 0x000F0C38U +#define PI_WR_GAP_S_3_F1 0x000F0C39U +#define PI_WR_GAP_S_3_F2 0x100F0C39U +#define PI_WR_GAP_L_3_F1 0x100F0C3AU +#define PI_WR_GAP_L_3_F2 0x000F0C3BU +#define PI_RW_GAP_3_F1 0x000F0C3CU +#define PI_RW_GAP_3_F2 0x100F0C3CU +#define PI_DARRAY3_0_CS0_F0 0x00080C9DU +#define PI_DARRAY3_1_CS0_F0 0x08080C9DU +#define PI_DARRAY3_0_CS0_F1 0x00080CA7U +#define PI_DARRAY3_1_CS0_F1 0x08080CA7U +#define PI_DARRAY3_0_CS0_F2 0x00080CB1U +#define PI_DARRAY3_1_CS0_F2 0x08080CB1U +#define PI_DARRAY3_2_CS0_F2 0x10080CB1U +#define PI_DARRAY3_20_CS0_F2 0x00080CB6U +#define PI_DARRAY3_0_CS1_F0 0x00080CBBU +#define PI_DARRAY3_1_CS1_F0 0x08080CBBU +#define PI_DARRAY3_0_CS1_F1 0x00080CC5U +#define PI_DARRAY3_1_CS1_F1 0x08080CC5U +#define PI_DARRAY3_0_CS1_F2 0x00080CCFU +#define PI_DARRAY3_1_CS1_F2 0x08080CCFU +#define PI_DARRAY3_2_CS1_F2 0x10080CCFU +#define PI_DARRAY3_20_CS1_F2 0x00080CD4U + +#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xFFFFU) +#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xFFU) +#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xFFU) + +#endif /* DDR_REGDEF_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c new file mode 100644 index 0000000..380bb5a --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c @@ -0,0 +1,171 @@ +/******************************************************************************* + * Copyright (c) 2023-2025 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC initialize function + ******************************************************************************/ +/****************************************************************************** + * @file ecc_enable_v4m.c + * - Version : 0.05 + * @brief Enable setting process of ECC for DRAM. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + * : 21.08.2023 0.02 Update the ecc setting according to HW SAN rev0.82. + * : 08.04.2024 0.03 Update the ecc register setting. + * : 13.06.2024 0.04 Fix register setting for EDC_CFG, and revise + * : the ecm_lock()/ecm_unlock() process. + * : 27.01.2025 0.05 Add ECM setting process. + * Remove unused functions. + *****************************************************************************/ + +#include + +#if (ECC_ENABLE == 1) +#include "ecc_enable_v4m.h" +#include "ecm_enable_v4m.h" +#include "mem_io.h" +#include "v4m/lpddr5/boot_init_dram_regdef.h" + +/* Reference:"ECC for DRAM and System RAM" in R19AN0083EJ0082_R-CarV4H_SAN_for_Customer.pdf*/ +void ecc_sdram_enable(void) +{ + NOTICE("ECC for DRAM is enable.\n"); + + uint32_t ecm_tmp; + + /* Before writing to DBSC register, it shall be set to "0x00001234" for the following registers. + After writing to DBSC register, it shall be set to a value other than "0x00001234" for the following registers. */ + mem_write32(DB0SYSCNT0, 0x00001234U); + mem_write32(DB0SYSCNT0A, 0x00001234U); + + /* (A) Setting ECM */ + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + /* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers + to inform the external device of the error via the ERROROUT# pin. */ + /* Set bit 1 of ECMERRTGTR0 to 0 and bit 1 of ECMERRCTLR0 to 1. */ + ecm_tmp = mem_read32(ECMERRTGTR0); + ecm_tmp &= ~(0x2U); + ecm_write(ECMERRTGTR0, ecm_tmp); + + ecm_tmp = mem_read32(ECMERRCTLR0); + ecm_tmp |= (0x2U); + ecm_write(ECMERRCTLR0, ecm_tmp); + + /* (B) Setting ECC protection area */ + /* Set the bottom row address of the ECC protection area */ + mem_write32(DB0FSDRAMECCAREA00, ECC_PROT_SIZE00); + mem_write32(DB0FSDRAMECCAREA01, ECC_PROT_SIZE01); + + /* (C) Initialization for DRAM */ + mem_write32(DBSC_DB0ACEN, 0x00000000U); + + /*** Initialization for DRAM connected to DBS0 Initialize RANK0 in according with the following procedure.***/ + /* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB0FSCONF00A[1:0]. */ + mem_write32(DB0FSCONF00A, 0x0U); + + /* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */ + mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA00); + + /* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */ + mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA00); + + /* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */ + mem_write32(DB0FSCTRL01A, 0x01U); + + /* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */ + NOTICE("DRAM rank 0 of DBSC0 is initializing.......\n"); + do + { + ecm_tmp = 0x01U; + ecm_tmp &= mem_read32(DB0FSSTAT01A); + } while ((ecm_tmp & 0x01U) != 0x01U); + + /*** If DRAM is connected to RANK1, Initialize RANK1 by the following procedure ***/ + /* [Step1] Specify RANK1 as the initialization target. Set 0x1 to DB0FSCONF00A[1:0]. */ + mem_write32(DB0FSCONF00A, 0x1U); + + /* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */ + mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA01); + + /* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */ + mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA01); + + /* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */ + mem_write32(DB0FSCTRL01A, 0x01U); + + /* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */ + NOTICE("DRAM rank 1 of DBSC0 is initializing.......\n"); + do + { + ecm_tmp = 0x01U; + ecm_tmp &= mem_read32(DB0FSSTAT01A); + } while ((ecm_tmp & 0x01U) != 0x01U); + + /* (D) Setting ECC protection enable */ + ecm_tmp = mem_read32(DB0FSCONFAXI0); + ecm_tmp |= (0x3U << 8U); + mem_write32(DB0FSCONFAXI0, ecm_tmp); + + /* (E) System RAM initialization */ + /* Read DB0FSSTAT00A and wait until its value changes to 0x1. */ + /* When DB0FSSTAT00A changes to 0x1, the System RAM area initialization is complete of dbs0 */ + NOTICE("System RAM is initializing.......\n"); + do + { + ecm_tmp = 0x01U; + ecm_tmp &= mem_read32(DB0FSSTAT00A); + } while (ecm_tmp != 0x1U); + + /* (F) Setting for ECC error interrupt */ + /* (1) Set the ECC error interrupt for read data */ + mem_write32(DB0FSINTENB02A, 0xFF00U); + + /* (2) Set the ECC error interrupt during RMW operation for System RAM. */ + ecm_tmp = mem_read32(DB0FSINTENB02A); + ecm_tmp |= 0xFF000000U; + mem_write32(DB0FSINTENB02A, ecm_tmp); + + /* (3) Set the ECC error interrupt during RMW operation for DRAM. */ + mem_write32(DB0FSINTENB04A, 0xFFFFFFFFU); + + /* Lock the ECM registers */ + ecm_lock(); + + /* Enable the write protect of ECM registers */ + mem_write32(DBSC_DB0ACEN, 0x00000001U); + + /* Enable the access protect for DBSC registers */ + mem_write32(DB0SYSCNT0, 0x00000000U); + mem_write32(DB0SYSCNT0A, 0x00000000U); +} +#endif /* ECC_ENABLE == 1 */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h new file mode 100644 index 0000000..9c007b7 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h @@ -0,0 +1,116 @@ +/******************************************************************************* + * Copyright (c) 2023-2025 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC driver header + ******************************************************************************/ + +#ifndef ECC_PROTECT +#define ECC_PROTECT +/* DBSC registers */ +#if defined(__RH850G3K__) +#include "remap_register.h" +#include "mem_io.h" +#include "log.h" +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#define ECM_BASE (BASE_ECC_ADDR) +#else +#if (ECC_ENABLE == 1) +#include "mem_io.h" +#include "log.h" +#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#endif /* ECC_ENABLE == 1 */ +#define ECM_BASE (0xE6250000U) +#endif/* defined(__RH850G3K__) */ + +#if (ECC_ENABLE == 1) +void ecc_sdram_enable(void); + +#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U) +#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U) +#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U) + +#define DBSC_DB0ACEN (DBSC_A_BASE + 0x0200U) +#define DBSC_DB1ACEN (DBSC_DB0ACEN + 0x8000U) +#endif /* ECC_ENABLE == 1 */ + +#define ECMWACNTR (ECM_BASE + 0x0A04U) +#define ECMWPCNTR (ECM_BASE + 0x0A00U) +#if (ECC_ENABLE == 1) +#define ECMERRTGTR0 (ECM_BASE + 0x0200U) +#define ECMERRCTLR0 (ECM_BASE + 0x0000U) +#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U) +#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U) +#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U) +#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U) +#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U) +#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U) +#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U) +#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U) +#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U) +#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U) +#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U) +#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U) +#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U) +#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U) +#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U) +#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U) + +#define DB0FSDRAMECCAREA00 (DBSC_A_BASE + 0x7450U) +#define DB0FSDRAMECCAREA01 (DBSC_A_BASE + 0x7454U) +#define DB1FSDRAMECCAREA00 (DB0FSDRAMECCAREA00 + 0x8000U) +#define DB1FSDRAMECCAREA01 (DB0FSDRAMECCAREA01 + 0x8000U) + +#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U) +#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U) + +/********************* Set by the user *********************/ +/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */ +#define ECC_PROT_SIZE00 (0xCCCCU) +#define ECC_PROT_SIZE01 (0xCCCCU) +#define ECC_PROT_SIZE10 (0xCCCCU) +#define ECC_PROT_SIZE11 (0xCCCCU) + +/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */ +#define START_ECC_INIT_AREA00 (0x00000000U) +#define START_ECC_INIT_AREA10 (0x00000000U) +#define END_ECC_INIT_AREA00 (0x0000CCCBU) +#define END_ECC_INIT_AREA10 (0x0000CCCBU) + +/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */ +#define START_ECC_INIT_AREA01 (0x00000000U) +#define START_ECC_INIT_AREA11 (0x00000000U) +#define END_ECC_INIT_AREA01 (0x0000CCCBU) +#define END_ECC_INIT_AREA11 (0x0000CCCBU) +/*********** Other settings cannot be changed ***************/ +#endif /* ECC_ENABLE == 1 */ + +#endif/* ECC_PROTECT */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c new file mode 100644 index 0000000..5d78cc9 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c @@ -0,0 +1,265 @@ +/******************************************************************************* + * Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM initialize function + ******************************************************************************/ +/****************************************************************************** + * @file ecm_enable_v4m.c + * - Version : 0.01 + * @brief ECM setting. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.01.2025 0.01 First Release + *****************************************************************************/ + +#include +#include "ecm_enable_v4m.h" + +#if (ECM_ERROR_ENABLE == 1) +#include "log.h" +#endif /* ECM_ERROR_ENABLE == 1 */ +#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1)) +#include "ecc_enable_v4m.h" +#include "mem_io.h" +#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +#define ECM_ERR_REG_MAX (39U) + +typedef struct{ + uint32_t phys_addr; /* Physical address of ECM registers. */ + uint32_t value; /* Setting value of ECM registers. */ +} ECM_ERROR_TABLE; +#endif /* ECM_ERROR_ENABLE == 1 */ + +#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1)) +void ecm_unlock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0001U); +} + +void ecm_write(uint32_t adr, uint32_t val) +{ + mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU))); + mem_write32(adr, val); +} + +void ecm_lock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0000U); +} +#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_error_enable(void) +{ + uint32_t reg; + uint32_t loop; + + const ECM_ERROR_TABLE ecmerrctlr_tbl[ECM_ERR_REG_MAX] = { + [0] = {0xE6250000U, 0xFFFFF003U}, /* ECMERRCTLR0 */ + [1] = {0xE6250004U, 0xA7F8C000U}, /* ECMERRCTLR1 */ + [2] = {0xE6250008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */ + [3] = {0xE625000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */ + [4] = {0xE6250010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */ + [5] = {0xE6250014U, 0x8FFFFFFFU}, /* ECMERRCTLR5 */ + [6] = {0xE6250018U, 0xFF000A80U}, /* ECMERRCTLR6 */ + [7] = {0xE625001CU, 0x68980FFFU}, /* ECMERRCTLR7 */ + [8] = {0xE6250020U, 0x60A00000U}, /* ECMERRCTLR8 */ + [9] = {0xE6250024U, 0xFF000000U}, /* ECMERRCTLR9 */ + [10] = {0xE6250028U, 0x557D554CU}, /* ECMERRCTLR10 */ + [11] = {0xE625002CU, 0xFF3C1555U}, /* ECMERRCTLR11 */ + [12] = {0xE6250030U, 0x0003FFFFU}, /* ECMERRCTLR12 */ + /* Skip ECMERRCTLR13 setting */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + [13] = {0xE6250040U, 0x33F03FFFU}, /* ECMERRCTLR16 */ + [14] = {0xE6250044U, 0x2DFF9CE0U}, /* ECMERRCTLR17 */ + [15] = {0xE6250048U, 0x0CC037FFU}, /* ECMERRCTLR18 */ + [16] = {0xE625004CU, 0xFFFFFF31U}, /* ECMERRCTLR19 */ + [17] = {0xE6250050U, 0xFE60067EU}, /* ECMERRCTLR20 */ + [18] = {0xE6250054U, 0xBF61820FU}, /* ECMERRCTLR21 */ + [19] = {0xE6250058U, 0x10000000U}, /* ECMERRCTLR22 */ + [20] = {0xE625005CU, 0x7E90C008U}, /* ECMERRCTLR23 */ + [21] = {0xE6250060U, 0x7E788AD9U}, /* ECMERRCTLR24 */ + [22] = {0xE6250064U, 0xC7807AB7U}, /* ECMERRCTLR25 */ + [23] = {0xE6250068U, 0x7E90C008U}, /* ECMERRCTLR26 */ + [24] = {0xE625006CU, 0x7E788AD9U}, /* ECMERRCTLR27 */ + [25] = {0xE6250070U, 0xC7807AB7U}, /* ECMERRCTLR28 */ + [26] = {0xE6250074U, 0x0010C008U}, /* ECMERRCTLR29 */ + [27] = {0xE6250078U, 0x7E608A99U}, /* ECMERRCTLR30 */ + [28] = {0xE625007CU, 0x84007A00U}, /* ECMERRCTLR31 */ + [29] = {0xE6250080U, 0xDFFFFFFFU}, /* ECMERRCTLR32 */ + [30] = {0xE6250084U, 0x1FFFFFFFU}, /* ECMERRCTLR33 */ + [31] = {0xE6250088U, 0x0000001FU}, /* ECMERRCTLR34 */ + [32] = {0xE625008CU, 0xA3BEEA80U}, /* ECMERRCTLR35 */ + [33] = {0xE6250090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */ + /* Skip ECMERRCTLR37 setting */ + [34] = {0xE6250098U, 0xFFF000FFU}, /* ECMERRCTLR38 */ + [35] = {0xE625009CU, 0x19FF0000U}, /* ECMERRCTLR39 */ + [36] = {0xE62500A0U, 0x0000601EU}, /* ECMERRCTLR40 */ + [37] = {0xE62500A4U, 0xEFFF7FFBU}, /* ECMERRCTLR41 */ + [38] = {0xE62500A8U, 0x0000000FU}, /* ECMERRCTLR42 */ + }; + +#if (ECMERRTGTR_INTC == 1) + const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = { + [0] = {0xE6250200U, 0xFFFFF003U}, /* ECMERRTGTR0 */ + [1] = {0xE6250204U, 0xA7F8C000U}, /* ECMERRTGTR1 */ + [2] = {0xE6250208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */ + [3] = {0xE625020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */ + [4] = {0xE6250210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */ + [5] = {0xE6250214U, 0x8FFFFFFFU}, /* ECMERRTGTR5 */ + [6] = {0xE6250218U, 0xFF000A80U}, /* ECMERRTGTR6 */ + [7] = {0xE625021CU, 0x68980FFFU}, /* ECMERRTGTR7 */ + [8] = {0xE6250220U, 0x60A00000U}, /* ECMERRTGTR8 */ + [9] = {0xE6250224U, 0xFF000000U}, /* ECMERRTGTR9 */ + [10] = {0xE6250228U, 0x557D554CU}, /* ECMERRTGTR10 */ + [11] = {0xE625022CU, 0xFF3C1555U}, /* ECMERRTGTR11 */ + [12] = {0xE6250230U, 0x0003FFFFU}, /* ECMERRTGTR12 */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [13] = {0xE6250240U, 0x33F03FFFU}, /* ECMERRTGTR16 */ + [14] = {0xE6250244U, 0x2DFF9CE0U}, /* ECMERRTGTR17 */ + [15] = {0xE6250248U, 0x0CC037FFU}, /* ECMERRTGTR18 */ + [16] = {0xE625024CU, 0xFFFFFF31U}, /* ECMERRTGTR19 */ + [17] = {0xE6250250U, 0xFE60067EU}, /* ECMERRTGTR20 */ + [18] = {0xE6250254U, 0xBF61820FU}, /* ECMERRTGTR21 */ + [19] = {0xE6250258U, 0x10000000U}, /* ECMERRTGTR22 */ + [20] = {0xE625025CU, 0x7E90C008U}, /* ECMERRTGTR23 */ + [21] = {0xE6250260U, 0x7E788AD9U}, /* ECMERRTGTR24 */ + [22] = {0xE6250264U, 0xC7807AB7U}, /* ECMERRTGTR25 */ + [23] = {0xE6250268U, 0x7E90C008U}, /* ECMERRTGTR26 */ + [24] = {0xE625026CU, 0x7E788AD9U}, /* ECMERRTGTR27 */ + [25] = {0xE6250270U, 0xC7807AB7U}, /* ECMERRTGTR28 */ + [26] = {0xE6250274U, 0x0010C008U}, /* ECMERRTGTR29 */ + [27] = {0xE6250278U, 0x7E608A99U}, /* ECMERRTGTR30 */ + [28] = {0xE625027CU, 0x84007A00U}, /* ECMERRTGTR31 */ + [29] = {0xE6250280U, 0xDFFFFFFFU}, /* ECMERRTGTR32 */ + [30] = {0xE6250284U, 0x1FFFFFFFU}, /* ECMERRTGTR33 */ + [31] = {0xE6250288U, 0x0000001FU}, /* ECMERRTGTR34 */ + [32] = {0xE625028CU, 0xA3BEEA80U}, /* ECMERRTGTR35 */ + [33] = {0xE6250290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */ + /* Skip ECMERRTGTR37 setting */ + [34] = {0xE6250298U, 0xFFF000FFU}, /* ECMERRTGTR38 */ + [35] = {0xE625029CU, 0x19FF0000U}, /* ECMERRTGTR39 */ + [36] = {0xE62502A0U, 0x0000601EU}, /* ECMERRTGTR40 */ + [37] = {0xE62502A4U, 0xEFFF7FFBU}, /* ECMERRTGTR41 */ + [38] = {0xE62502A8U, 0x0000000FU}, /* ECMERRTGTR42 */ + }; +#elif (ECMERRTGTR_INTC == 0) + const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = { + [0] = {0xE6250200U, 0x00000000U}, /* ECMERRTGTR0 */ + [1] = {0xE6250204U, 0x00000000U}, /* ECMERRTGTR1 */ + [2] = {0xE6250208U, 0x00000000U}, /* ECMERRTGTR2 */ + [3] = {0xE625020CU, 0x00000000U}, /* ECMERRTGTR3 */ + [4] = {0xE6250210U, 0x00000000U}, /* ECMERRTGTR4 */ + [5] = {0xE6250214U, 0x00000000U}, /* ECMERRTGTR5 */ + [6] = {0xE6250218U, 0x00000000U}, /* ECMERRTGTR6 */ + [7] = {0xE625021CU, 0x00000000U}, /* ECMERRTGTR7 */ + [8] = {0xE6250220U, 0x00000000U}, /* ECMERRTGTR8 */ + [9] = {0xE6250224U, 0x00000000U}, /* ECMERRTGTR9 */ + [10] = {0xE6250228U, 0x00000000U}, /* ECMERRTGTR10 */ + [11] = {0xE625022CU, 0x00000000U}, /* ECMERRTGTR11 */ + [12] = {0xE6250230U, 0x00000000U}, /* ECMERRTGTR12 */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [13] = {0xE6250240U, 0x00000000U}, /* ECMERRTGTR16 */ + [14] = {0xE6250244U, 0x00000000U}, /* ECMERRTGTR17 */ + [15] = {0xE6250248U, 0x00000000U}, /* ECMERRTGTR18 */ + [16] = {0xE625024CU, 0x00000000U}, /* ECMERRTGTR19 */ + [17] = {0xE6250250U, 0x00000000U}, /* ECMERRTGTR20 */ + [18] = {0xE6250254U, 0x00000000U}, /* ECMERRTGTR21 */ + [19] = {0xE6250258U, 0x00000000U}, /* ECMERRTGTR22 */ + [20] = {0xE625025CU, 0x00000000U}, /* ECMERRTGTR23 */ + [21] = {0xE6250260U, 0x00000000U}, /* ECMERRTGTR24 */ + [22] = {0xE6250264U, 0x00000000U}, /* ECMERRTGTR25 */ + [23] = {0xE6250268U, 0x00000000U}, /* ECMERRTGTR26 */ + [24] = {0xE625026CU, 0x00000000U}, /* ECMERRTGTR27 */ + [25] = {0xE6250270U, 0x00000000U}, /* ECMERRTGTR28 */ + [26] = {0xE6250274U, 0x00000000U}, /* ECMERRTGTR29 */ + [27] = {0xE6250278U, 0x00000000U}, /* ECMERRTGTR30 */ + [28] = {0xE625027CU, 0x00000000U}, /* ECMERRTGTR31 */ + [29] = {0xE6250280U, 0x00000000U}, /* ECMERRTGTR32 */ + [30] = {0xE6250284U, 0x00000000U}, /* ECMERRTGTR33 */ + [31] = {0xE6250288U, 0x00000000U}, /* ECMERRTGTR34 */ + [32] = {0xE625028CU, 0x00000000U}, /* ECMERRTGTR35 */ + [33] = {0xE6250290U, 0x00000000U}, /* ECMERRTGTR36 */ + /* Skip ECMERRTGTR37 setting */ + [34] = {0xE6250298U, 0x00000000U}, /* ECMERRTGTR38 */ + [35] = {0xE625029CU, 0x00000000U}, /* ECMERRTGTR39 */ + [36] = {0xE62502A0U, 0x00000000U}, /* ECMERRTGTR40 */ + [37] = {0xE62502A4U, 0x00000000U}, /* ECMERRTGTR41 */ + [38] = {0xE62502A8U, 0x00000000U}, /* ECMERRTGTR42 */ + }; +#endif /* ECMERRTGTR_INTC == 1 */ + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + NOTICE("ECMERRCTLR register setting.\n"); + for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++) + { + /* Set ECMERRCTLR registers. */ + reg = mem_read32(ecmerrctlr_tbl[loop].phys_addr); + reg |= ecmerrctlr_tbl[loop].value; + ecm_write(ecmerrctlr_tbl[loop].phys_addr, reg); + + INFO("ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrctlr_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_tbl[loop].phys_addr), + ecmerrctlr_tbl[loop].value); + } + + NOTICE("ECMERRTGTR register setting.\n"); + for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++) + { + /* Set ECMERRTGTR registers. */ + reg = mem_read32(ecmerrtgtr_tbl[loop].phys_addr); + reg |= ecmerrtgtr_tbl[loop].value; + ecm_write(ecmerrtgtr_tbl[loop].phys_addr, reg); + + INFO("ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrtgtr_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_tbl[loop].phys_addr), + ecmerrtgtr_tbl[loop].value); + } + + /* Lock the ECM registers */ + ecm_lock(); +} +/* End of function ecm_error_enable(void) */ +#endif /* ECM_ERROR_ENABLE == 1 */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h new file mode 100644 index 0000000..88c3ea2 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h @@ -0,0 +1,47 @@ +/******************************************************************************* + * Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM driver header + ******************************************************************************/ + +#ifndef ECM_ENABLE +#define ECM_ENABLE + +#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1)) +void ecm_unlock(void); +void ecm_write(uint32_t adr, uint32_t val); +void ecm_lock(void); +#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_error_enable(void); +#endif /* ECM_ERROR_ENABLE == 1 */ + +#endif/* ECM_ENABLE */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/init_dram_tbl_v4m_lp5.h b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/init_dram_tbl_v4m_lp5.h new file mode 100644 index 0000000..2dad73a --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/init_dram_tbl_v4m_lp5.h @@ -0,0 +1,1654 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +#ifndef INIT_DRAM_TBL_V4M_LP5_H_ +#define INIT_DRAM_TBL_V4M_LP5_H_ + +#define DDR_PHY_SLICE_REGSET_OFS_V4M 0x1000 +#define DDR_PHY_ADR_V_REGSET_OFS_V4M 0x1200 +#define DDR_PHY_ADR_G_REGSET_OFS_V4M 0x1300 +#define DDR_PI_REGSET_OFS_V4M 0x0800 + +#define DDR_PHY_SLICE_REGSET_SIZE_V4M 0x100 +#define DDR_PHY_ADR_V_REGSET_SIZE_V4M 0x100 +#define DDR_PHY_ADR_G_REGSET_SIZE_V4M 0x100 +#define DDR_PI_REGSET_SIZE_V4M 0x600 + +#define DDR_PHY_SLICE_REGSET_NUM_V4M 140 +#define DDR_PHY_ADR_V_REGSET_NUM_V4M 61 +#define DDR_PHY_ADR_G_REGSET_NUM_V4M 98 +#define DDR_PI_REGSET_NUM_V4M 1301 + +static const uint32_t DDR_PHY_SLICE_REGSET_V4M[DDR_PHY_SLICE_REGSET_NUM_V4M] = { +/*1000*/ 0x30020370, +/*1001*/ 0x00000000, +/*1002*/ 0x01000002, +/*1003*/ 0x00010000, +/*1004*/ 0x00000000, +/*1005*/ 0x00000000, +/*1006*/ 0x01030000, +/*1007*/ 0x00010000, +/*1008*/ 0x01000004, +/*1009*/ 0x00000000, +/*100A*/ 0x00000001, +/*100B*/ 0x00000000, +/*100C*/ 0x00000000, +/*100D*/ 0x00010000, +/*100E*/ 0x08010000, +/*100F*/ 0x00022003, +/*1010*/ 0x00000000, +/*1011*/ 0x040F0100, +/*1012*/ 0x1404034F, +/*1013*/ 0x04020102, +/*1014*/ 0x10040404, +/*1015*/ 0x00000100, +/*1016*/ 0x00000000, +/*1017*/ 0x00FF0000, +/*1018*/ 0x18FF0008, +/*1019*/ 0x0000000F, +/*101A*/ 0x00000000, +/*101B*/ 0x00000001, +/*101C*/ 0x00070000, +/*101D*/ 0x00000000, +/*101E*/ 0x00000000, +/*101F*/ 0x00000000, +/*1020*/ 0x0008087F, +/*1021*/ 0x08040000, +/*1022*/ 0x00000004, +/*1023*/ 0x00401030, +/*1024*/ 0x0200000C, +/*1025*/ 0x00000020, +/*1026*/ 0x00000101, +/*1027*/ 0x00000000, +/*1028*/ 0x00000000, +/*1029*/ 0x00000000, +/*102A*/ 0x00000000, +/*102B*/ 0x00000000, +/*102C*/ 0x00000000, +/*102D*/ 0x00000000, +/*102E*/ 0x00000000, +/*102F*/ 0x00000000, +/*1030*/ 0x00000000, +/*1031*/ 0x00000000, +/*1032*/ 0x00000000, +/*1033*/ 0x00000020, +/*1034*/ 0x00000000, +/*1035*/ 0x00000000, +/*1036*/ 0x00000000, +/*1037*/ 0x00000000, +/*1038*/ 0x00000000, +/*1039*/ 0x00000000, +/*103A*/ 0x00000000, +/*103B*/ 0x00000000, +/*103C*/ 0x00000000, +/*103D*/ 0x00000004, +/*103E*/ 0x001F07FF, +/*103F*/ 0x00800800, +/*1040*/ 0x00061020, +/*1041*/ 0x04010000, +/*1042*/ 0x00000000, +/*1043*/ 0xCEC20101, +/*1044*/ 0x0000000A, +/*1045*/ 0x00017706, +/*1046*/ 0x01007706, +/*1047*/ 0x00000000, +/*1048*/ 0x008D006D, +/*1049*/ 0x00100001, +/*104A*/ 0x03FF0100, +/*104B*/ 0x00006E01, +/*104C*/ 0x00000301, +/*104D*/ 0x00000000, +/*104E*/ 0x00000000, +/*104F*/ 0x00000000, +/*1050*/ 0x00540054, +/*1051*/ 0x00540054, +/*1052*/ 0x00540054, +/*1053*/ 0x00540054, +/*1054*/ 0x0D000054, +/*1055*/ 0x90510604, +/*1056*/ 0x70006161, +/*1057*/ 0x41800531, +/*1058*/ 0x32800064, +/*1059*/ 0x80010080, +/*105A*/ 0x01010080, +/*105B*/ 0x00161301, +/*105C*/ 0x00030200, +/*105D*/ 0x42100010, +/*105E*/ 0x0106093E, +/*105F*/ 0x000F063D, +/*1060*/ 0x011700C8, +/*1061*/ 0x04100140, +/*1062*/ 0x00000100, +/*1063*/ 0x000001D1, +/*1064*/ 0x00000000, +/*1065*/ 0x05000068, +/*1066*/ 0x00030400, +/*1067*/ 0x01400000, +/*1068*/ 0x80800300, +/*1069*/ 0x00160010, +/*106A*/ 0x76543210, +/*106B*/ 0x00000008, +/*106C*/ 0x03010301, +/*106D*/ 0x03010301, +/*106E*/ 0x03010301, +/*106F*/ 0x03010301, +/*1070*/ 0x03010301, +/*1071*/ 0x00000000, +/*1072*/ 0x00500050, +/*1073*/ 0x00500050, +/*1074*/ 0x00500050, +/*1075*/ 0x00500050, +/*1076*/ 0x00500050, +/*1077*/ 0x00500050, +/*1078*/ 0x00500050, +/*1079*/ 0x00500050, +/*107A*/ 0x00500050, +/*107B*/ 0x00070087, +/*107C*/ 0x00000000, +/*107D*/ 0x08010007, +/*107E*/ 0x00000000, +/*107F*/ 0x20202020, +/*1080*/ 0x20202020, +/*1081*/ 0x20202020, +/*1082*/ 0x00000000, +/*1083*/ 0x00000000, +/*1084*/ 0x00000000, +/*1085*/ 0x00000000, +/*1086*/ 0x00000000, +/*1087*/ 0x00000000, +/*1088*/ 0x00000000, +/*1089*/ 0x00000000, +/*108A*/ 0x00000000, +/*108B*/ 0x00000000 +}; + +static const uint32_t DDR_PHY_ADR_V_REGSET_V4M[DDR_PHY_ADR_V_REGSET_NUM_V4M] = { +/*1200*/ 0x00200030, +/*1201*/ 0x00202002, +/*1202*/ 0x76543210, +/*1203*/ 0x00010001, +/*1204*/ 0x06543210, +/*1205*/ 0x03070000, +/*1206*/ 0x00001000, +/*1207*/ 0x00000000, +/*1208*/ 0x00000000, +/*1209*/ 0x00000000, +/*120A*/ 0x00000000, +/*120B*/ 0x00000000, +/*120C*/ 0x00000000, +/*120D*/ 0x00000000, +/*120E*/ 0x00000000, +/*120F*/ 0x0000807F, +/*1210*/ 0x00000001, +/*1211*/ 0x00000003, +/*1212*/ 0x00000000, +/*1213*/ 0x000F0000, +/*1214*/ 0x030C000F, +/*1215*/ 0x00020103, +/*1216*/ 0x0000000F, +/*1217*/ 0x00000100, +/*1218*/ 0x00000000, +/*1219*/ 0x00000000, +/*121A*/ 0x00000000, +/*121B*/ 0x00000000, +/*121C*/ 0x00000000, +/*121D*/ 0x00040000, +/*121E*/ 0x002A0200, +/*121F*/ 0x00000000, +/*1220*/ 0x00000000, +/*1221*/ 0x00000000, +/*1222*/ 0x00000000, +/*1223*/ 0x00200101, +/*1224*/ 0x10002C03, +/*1225*/ 0x00000003, +/*1226*/ 0x00030240, +/*1227*/ 0x00008008, +/*1228*/ 0x00081020, +/*1229*/ 0x01200000, +/*122A*/ 0x00010001, +/*122B*/ 0x00000000, +/*122C*/ 0x00100302, +/*122D*/ 0x003E4208, +/*122E*/ 0x01400140, +/*122F*/ 0x01400140, +/*1230*/ 0x01400140, +/*1231*/ 0x01400140, +/*1232*/ 0x00000100, +/*1233*/ 0x00000100, +/*1234*/ 0x00000100, +/*1235*/ 0x00000100, +/*1236*/ 0x00000000, +/*1237*/ 0x00000000, +/*1238*/ 0x00000000, +/*1239*/ 0x00000000, +/*123A*/ 0x00020580, +/*123B*/ 0x03000040, +/*123C*/ 0x00000000 +}; + +static const uint32_t DDR_PHY_ADR_G_REGSET_V4M[DDR_PHY_ADR_G_REGSET_NUM_V4M] = { +/*1300*/ 0x00000000, +/*1301*/ 0x00000100, +/*1302*/ 0x00000001, +/*1303*/ 0x23800000, +/*1304*/ 0x00000000, +/*1305*/ 0x01000101, +/*1306*/ 0x01000000, +/*1307*/ 0x00000000, +/*1308*/ 0x00000000, +/*1309*/ 0x00000000, +/*130A*/ 0x00000000, +/*130B*/ 0x00000000, +/*130C*/ 0x00040101, +/*130D*/ 0x00000000, +/*130E*/ 0x00000000, +/*130F*/ 0x00000064, +/*1310*/ 0x00000000, +/*1311*/ 0x00000000, +/*1312*/ 0x39421B42, +/*1313*/ 0x00010124, +/*1314*/ 0x00520052, +/*1315*/ 0x00000052, +/*1316*/ 0x00000000, +/*1317*/ 0x00000000, +/*1318*/ 0x00010001, +/*1319*/ 0x00000000, +/*131A*/ 0x00000000, +/*131B*/ 0x00010001, +/*131C*/ 0x00000000, +/*131D*/ 0x00000000, +/*131E*/ 0x00010001, +/*131F*/ 0x07030102, +/*1320*/ 0x01030307, +/*1321*/ 0x00000094, +/*1322*/ 0x00004096, +/*1323*/ 0x08200820, +/*1324*/ 0x08200820, +/*1325*/ 0x08200820, +/*1326*/ 0x08200820, +/*1327*/ 0x08200820, +/*1328*/ 0x004103B8, +/*1329*/ 0x0000003F, +/*132A*/ 0x000C0006, +/*132B*/ 0x00000000, +/*132C*/ 0x000004C0, +/*132D*/ 0x00000000, +/*132E*/ 0x00000208, +/*132F*/ 0x00000000, +/*1330*/ 0x00000000, +/*1331*/ 0x00000000, +/*1332*/ 0x00000000, +/*1333*/ 0x00000000, +/*1334*/ 0x03000000, +/*1335*/ 0x00000000, +/*1336*/ 0x00000000, +/*1337*/ 0x00000002, +/*1338*/ 0x00041020, +/*1339*/ 0x00041020, +/*133A*/ 0x01C98C98, +/*133B*/ 0x3F400000, +/*133C*/ 0x003F3F3F, +/*133D*/ 0x00000000, +/*133E*/ 0x00000000, +/*133F*/ 0x76543210, +/*1340*/ 0x01010098, +/*1341*/ 0x00000007, +/*1342*/ 0x00000000, +/*1343*/ 0x00000000, +/*1344*/ 0x00000000, +/*1345*/ 0x00000002, +/*1346*/ 0x00000000, +/*1347*/ 0x00000000, +/*1348*/ 0x0000017F, +/*1349*/ 0x00000000, +/*134A*/ 0x01032380, +/*134B*/ 0x00000100, +/*134C*/ 0x00000000, +/*134D*/ 0x31421342, +/*134E*/ 0x00308000, +/*134F*/ 0x00000080, +/*1350*/ 0x00063F77, +/*1351*/ 0x00000006, +/*1352*/ 0x0000033F, +/*1353*/ 0x0000033F, +/*1354*/ 0x0000033F, +/*1355*/ 0x00033F00, +/*1356*/ 0x00CC0000, +/*1357*/ 0x00033F00, +/*1358*/ 0x00CC0000, +/*1359*/ 0x00033F77, +/*135A*/ 0x00000000, +/*135B*/ 0x00033F00, +/*135C*/ 0x00EE0000, +/*135D*/ 0x00033F00, +/*135E*/ 0x00EE0000, +/*135F*/ 0x00033F00, +/*1360*/ 0x00EE0000, +/*1361*/ 0x00200106 +}; + +static const uint32_t DDR_PI_REGSET_V4M[DDR_PI_REGSET_NUM_V4M] = { +/*0800*/ 0x00000D00, +/*0801*/ 0x00000000, +/*0802*/ 0x00000000, +/*0803*/ 0x00010100, +/*0804*/ 0x00640004, +/*0805*/ 0x00000001, +/*0806*/ 0x00000000, +/*0807*/ 0x00000000, +/*0808*/ 0x00000000, +/*0809*/ 0x00000000, +/*080A*/ 0xFFFFFFFF, +/*080B*/ 0x02010000, +/*080C*/ 0x00000003, +/*080D*/ 0x00000005, +/*080E*/ 0x00000002, +/*080F*/ 0x00000000, +/*0810*/ 0x00000101, +/*0811*/ 0x0012080E, +/*0812*/ 0x00000000, +/*0813*/ 0x001E2C0E, +/*0814*/ 0x00000000, +/*0815*/ 0x00030300, +/*0816*/ 0x01010700, +/*0817*/ 0x00000001, +/*0818*/ 0x00000001, +/*0819*/ 0x00000000, +/*081A*/ 0x00000000, +/*081B*/ 0x00000000, +/*081C*/ 0x00000000, +/*081D*/ 0x00000000, +/*081E*/ 0x00000000, +/*081F*/ 0x07010000, +/*0820*/ 0x00000028, +/*0821*/ 0x00000000, +/*0822*/ 0x00320003, +/*0823*/ 0x00000000, +/*0824*/ 0x00000000, +/*0825*/ 0x04022004, +/*0826*/ 0x01040100, +/*0827*/ 0x00000000, +/*0828*/ 0x00000001, +/*0829*/ 0x000000AA, +/*082A*/ 0x00000055, +/*082B*/ 0x000000B5, +/*082C*/ 0x0000004A, +/*082D*/ 0x00000056, +/*082E*/ 0x000000A9, +/*082F*/ 0x000000A9, +/*0830*/ 0x000000B5, +/*0831*/ 0x00000000, +/*0832*/ 0x01000000, +/*0833*/ 0x00030300, +/*0834*/ 0x0000001A, +/*0835*/ 0x000007D0, +/*0836*/ 0x00000300, +/*0837*/ 0x00000000, +/*0838*/ 0x00000000, +/*0839*/ 0x01000000, +/*083A*/ 0x00000101, +/*083B*/ 0x00000000, +/*083C*/ 0x00000000, +/*083D*/ 0x00000000, +/*083E*/ 0x00000200, +/*083F*/ 0x03030300, +/*0840*/ 0x01000000, +/*0841*/ 0x00000000, +/*0842*/ 0x01000000, +/*0843*/ 0x07010001, +/*0844*/ 0x00000007, +/*0845*/ 0x00000000, +/*0846*/ 0x03000100, +/*0847*/ 0x00000000, +/*0848*/ 0x00001703, +/*0849*/ 0x00000000, +/*084A*/ 0x00000000, +/*084B*/ 0x00000000, +/*084C*/ 0x0A0A140A, +/*084D*/ 0x10020201, +/*084E*/ 0x332A0002, +/*084F*/ 0x01010000, +/*0850*/ 0x0B000404, +/*0851*/ 0x04030308, +/*0852*/ 0x00010100, +/*0853*/ 0x02020301, +/*0854*/ 0x01001000, +/*0855*/ 0x00000034, +/*0856*/ 0x00000000, +/*0857*/ 0x00000000, +/*0858*/ 0x00000000, +/*0859*/ 0x00000000, +/*085A*/ 0x00000000, +/*085B*/ 0x00080000, +/*085C*/ 0x00000000, +/*085D*/ 0x55AA55AA, +/*085E*/ 0x33CC33CC, +/*085F*/ 0x0FF00FF0, +/*0860*/ 0x0F0FF0F0, +/*0861*/ 0x00008E38, +/*0862*/ 0x00000001, +/*0863*/ 0x00000002, +/*0864*/ 0x00020001, +/*0865*/ 0x00020001, +/*0866*/ 0x02010201, +/*0867*/ 0x0000000F, +/*0868*/ 0x00000000, +/*0869*/ 0x00000000, +/*086A*/ 0x00000000, +/*086B*/ 0x00000000, +/*086C*/ 0x00000000, +/*086D*/ 0x00000000, +/*086E*/ 0x00000000, +/*086F*/ 0x00000000, +/*0870*/ 0x00000000, +/*0871*/ 0x00000000, +/*0872*/ 0xAAAAA593, +/*0873*/ 0xA5939999, +/*0874*/ 0x00000000, +/*0875*/ 0x0000AA55, +/*0876*/ 0x00006633, +/*0877*/ 0x000198CC, +/*0878*/ 0x00000000, +/*0879*/ 0x0003FFFF, +/*087A*/ 0x00006633, +/*087B*/ 0x000198CC, +/*087C*/ 0x00000000, +/*087D*/ 0x036DB6DB, +/*087E*/ 0x00249249, +/*087F*/ 0x05B6DB6D, +/*0880*/ 0x00000000, +/*0881*/ 0x00000000, +/*0882*/ 0x00000000, +/*0883*/ 0x00000000, +/*0884*/ 0x00000000, +/*0885*/ 0x036DB6DB, +/*0886*/ 0x00249249, +/*0887*/ 0x05B6DB6D, +/*0888*/ 0x00000000, +/*0889*/ 0x00000000, +/*088A*/ 0x00000000, +/*088B*/ 0x00000000, +/*088C*/ 0x00000000, +/*088D*/ 0x01000000, +/*088E*/ 0x00000100, +/*088F*/ 0x00000000, +/*0890*/ 0x00000000, +/*0891*/ 0x00000000, +/*0892*/ 0x00000000, +/*0893*/ 0x00000000, +/*0894*/ 0x00000000, +/*0895*/ 0x00000000, +/*0896*/ 0x00000000, +/*0897*/ 0x00010000, +/*0898*/ 0x00000000, +/*0899*/ 0x00000000, +/*089A*/ 0x00000000, +/*089B*/ 0x00000000, +/*089C*/ 0x00000000, +/*089D*/ 0x00000000, +/*089E*/ 0x00000000, +/*089F*/ 0x00000000, +/*08A0*/ 0x00000000, +/*08A1*/ 0x00000000, +/*08A2*/ 0x00000000, +/*08A3*/ 0x00000000, +/*08A4*/ 0x00010000, +/*08A5*/ 0x00000000, +/*08A6*/ 0x00000000, +/*08A7*/ 0x00000000, +/*08A8*/ 0x00000000, +/*08A9*/ 0x00000000, +/*08AA*/ 0x00000000, +/*08AB*/ 0x00000000, +/*08AC*/ 0x00000000, +/*08AD*/ 0x00000000, +/*08AE*/ 0x00000000, +/*08AF*/ 0x00000000, +/*08B0*/ 0x00000000, +/*08B1*/ 0x00080000, +/*08B2*/ 0x00000000, +/*08B3*/ 0x00000000, +/*08B4*/ 0x00000000, +/*08B5*/ 0x00000000, +/*08B6*/ 0x00000000, +/*08B7*/ 0x00000000, +/*08B8*/ 0x00000000, +/*08B9*/ 0x00000000, +/*08BA*/ 0x00000000, +/*08BB*/ 0x00000000, +/*08BC*/ 0x01000400, +/*08BD*/ 0x03020100, +/*08BE*/ 0x00060504, +/*08BF*/ 0x00010000, +/*08C0*/ 0x02000008, +/*08C1*/ 0x00000000, +/*08C2*/ 0x01000001, +/*08C3*/ 0x00010000, +/*08C4*/ 0x00000006, +/*08C5*/ 0x0000000E, +/*08C6*/ 0x00000100, +/*08C7*/ 0x00000000, +/*08C8*/ 0x00000000, +/*08C9*/ 0x00000000, +/*08CA*/ 0x00000000, +/*08CB*/ 0x03010000, +/*08CC*/ 0x01000100, +/*08CD*/ 0x01020001, +/*08CE*/ 0x00010300, +/*08CF*/ 0x05000104, +/*08D0*/ 0x01060001, +/*08D1*/ 0x00010700, +/*08D2*/ 0x00000000, +/*08D3*/ 0x00000000, +/*08D4*/ 0x00010000, +/*08D5*/ 0x00000000, +/*08D6*/ 0x00000000, +/*08D7*/ 0x00000000, +/*08D8*/ 0x00000000, +/*08D9*/ 0x01000000, +/*08DA*/ 0x00000008, +/*08DB*/ 0x00000000, +/*08DC*/ 0x01010000, +/*08DD*/ 0x00000000, +/*08DE*/ 0x00000200, +/*08DF*/ 0x00000001, +/*08E0*/ 0xB8000000, +/*08E1*/ 0x010000FF, +/*08E2*/ 0x0000FFE8, +/*08E3*/ 0x00FFA801, +/*08E4*/ 0xFFD80100, +/*08E5*/ 0x00007F10, +/*08E6*/ 0x00000000, +/*08E7*/ 0x00000034, +/*08E8*/ 0x00000042, +/*08E9*/ 0x00020079, +/*08EA*/ 0x02000200, +/*08EB*/ 0x02000204, +/*08EC*/ 0x0F0D0C06, +/*08ED*/ 0x08030600, +/*08EE*/ 0x10080408, +/*08EF*/ 0x05080806, +/*08F0*/ 0x10241409, +/*08F1*/ 0x170E1C08, +/*08F2*/ 0x000B120C, +/*08F3*/ 0x00000063, +/*08F4*/ 0x0000004C, +/*08F5*/ 0x00000305, +/*08F6*/ 0x00000130, +/*08F7*/ 0x10000C2E, +/*08F8*/ 0x00040404, +/*08F9*/ 0x08003200, +/*08FA*/ 0x08002701, +/*08FB*/ 0x0F003201, +/*08FC*/ 0x00000000, +/*08FD*/ 0x00000000, +/*08FE*/ 0x00000000, +/*08FF*/ 0x01030000, +/*0900*/ 0x01030103, +/*0901*/ 0x03000000, +/*0902*/ 0x00000103, +/*0903*/ 0x01030300, +/*0904*/ 0x03000000, +/*0905*/ 0x0014000C, +/*0906*/ 0x0E060037, +/*0907*/ 0x03030526, +/*0908*/ 0x000C0032, +/*0909*/ 0x0019003F, +/*090A*/ 0x0025004B, +/*090B*/ 0x00010101, +/*090C*/ 0x00000007, +/*090D*/ 0x00000032, +/*090E*/ 0x010000C8, +/*090F*/ 0x00080000, +/*0910*/ 0x00040008, +/*0911*/ 0x00000100, +/*0912*/ 0x00330033, +/*0913*/ 0x01000015, +/*0914*/ 0x00C90000, +/*0915*/ 0x005100C9, +/*0916*/ 0x2E002E2E, +/*0917*/ 0x3329002E, +/*0918*/ 0x0A070600, +/*0919*/ 0x0A07060D, +/*091A*/ 0x0D09070D, +/*091B*/ 0x000C000D, +/*091C*/ 0x00001000, +/*091D*/ 0x00000C00, +/*091E*/ 0x00001000, +/*091F*/ 0x00000C00, +/*0920*/ 0x02001000, +/*0921*/ 0x00100007, +/*0922*/ 0x00160032, +/*0923*/ 0x1E1A00C8, +/*0924*/ 0x00140004, +/*0925*/ 0x361C0010, +/*0926*/ 0x00000000, +/*0927*/ 0x0006000C, +/*0928*/ 0x00000F00, +/*0929*/ 0x361C000B, +/*092A*/ 0x00000300, +/*092B*/ 0x000E0014, +/*092C*/ 0x00001B08, +/*092D*/ 0x361C0018, +/*092E*/ 0x00000300, +/*092F*/ 0x00220037, +/*0930*/ 0x00000024, +/*0931*/ 0x00000003, +/*0932*/ 0x08020200, +/*0933*/ 0x04040404, +/*0934*/ 0x0006C906, +/*0935*/ 0x20010003, +/*0936*/ 0x000A0602, +/*0937*/ 0x04040405, +/*0938*/ 0x07040404, +/*0939*/ 0x0009315C, +/*093A*/ 0x06031001, +/*093B*/ 0x0F11040A, +/*093C*/ 0x040A0A04, +/*093D*/ 0xC5701C0A, +/*093E*/ 0x10020022, +/*093F*/ 0x000A0D0C, +/*0940*/ 0x000000C6, +/*0941*/ 0x000007BC, +/*0942*/ 0x0000060A, +/*0943*/ 0x00003C64, +/*0944*/ 0x0000185C, +/*0945*/ 0x0000F398, +/*0946*/ 0x004E000D, +/*0947*/ 0x03030136, +/*0948*/ 0x00157C03, +/*0949*/ 0x0000157C, +/*094A*/ 0x0000D6D8, +/*094B*/ 0x00000002, +/*094C*/ 0x00000037, +/*094D*/ 0x0000000B, +/*094E*/ 0x00009C40, +/*094F*/ 0x00009C40, +/*0950*/ 0x00061A80, +/*0951*/ 0x0000000A, +/*0952*/ 0x00000190, +/*0953*/ 0x0000004E, +/*0954*/ 0x00027100, +/*0955*/ 0x00027100, +/*0956*/ 0x00186A00, +/*0957*/ 0x00000028, +/*0958*/ 0x00000640, +/*0959*/ 0x01000136, +/*095A*/ 0x002A0040, +/*095B*/ 0x00010004, +/*095C*/ 0x012C0040, +/*095D*/ 0x00010006, +/*095E*/ 0x04B00040, +/*095F*/ 0x00000318, +/*0960*/ 0x0028000A, +/*0961*/ 0x05040404, +/*0962*/ 0x00040603, +/*0963*/ 0x06030503, +/*0964*/ 0x05030019, +/*0965*/ 0x00640603, +/*0966*/ 0x06040608, +/*0967*/ 0x00040604, +/*0968*/ 0x004C000B, +/*0969*/ 0x01050130, +/*096A*/ 0x01000100, +/*096B*/ 0x02020100, +/*096C*/ 0x04000000, +/*096D*/ 0x06010404, +/*096E*/ 0x07010401, +/*096F*/ 0x00000001, +/*0970*/ 0x00030201, +/*0971*/ 0x02010100, +/*0972*/ 0x00000002, +/*0973*/ 0x00000000, +/*0974*/ 0x017F0000, +/*0975*/ 0x01010101, +/*0976*/ 0x00000001, +/*0977*/ 0x00000000, +/*0978*/ 0x00000000, +/*0979*/ 0x00000000, +/*097A*/ 0x00000000, +/*097B*/ 0x01000000, +/*097C*/ 0x01000101, +/*097D*/ 0x00000000, +/*097E*/ 0x00000000, +/*097F*/ 0x08201020, +/*0980*/ 0x28100020, +/*0981*/ 0x08083020, +/*0982*/ 0x08400020, +/*0983*/ 0x08402020, +/*0984*/ 0x08483020, +/*0985*/ 0x10083020, +/*0986*/ 0x20180020, +/*0987*/ 0x30480020, +/*0988*/ 0x78880020, +/*0989*/ 0x488010E0, +/*098A*/ 0x494B0000, +/*098B*/ 0x49089080, +/*098C*/ 0x49080000, +/*098D*/ 0x490011C0, +/*098E*/ 0x0A000020, +/*098F*/ 0x08000020, +/*0990*/ 0x08000020, +/*0991*/ 0x08000020, +/*0992*/ 0x08000020, +/*0993*/ 0x08000020, +/*0994*/ 0x08000020, +/*0995*/ 0x08000020, +/*0996*/ 0x08000020, +/*0997*/ 0x08000020, +/*0998*/ 0x08000020, +/*0999*/ 0x08000020, +/*099A*/ 0x08000020, +/*099B*/ 0x08000020, +/*099C*/ 0x08000020, +/*099D*/ 0x08000020, +/*099E*/ 0x08000020, +/*099F*/ 0x08000020, +/*09A0*/ 0x08000020, +/*09A1*/ 0x08000020, +/*09A2*/ 0x08000020, +/*09A3*/ 0x08000020, +/*09A4*/ 0x08000020, +/*09A5*/ 0x08000020, +/*09A6*/ 0x08000020, +/*09A7*/ 0x08000020, +/*09A8*/ 0x08000020, +/*09A9*/ 0x08000020, +/*09AA*/ 0x08000020, +/*09AB*/ 0x08000020, +/*09AC*/ 0x08084340, +/*09AD*/ 0x0011FFFF, +/*09AE*/ 0x2011FFFB, +/*09AF*/ 0x00012E00, +/*09B0*/ 0x001100EF, +/*09B1*/ 0x01A1120B, +/*09B2*/ 0x001F0000, +/*09B3*/ 0x081E4340, +/*09B4*/ 0x00212E00, +/*09B5*/ 0x01A1120B, +/*09B6*/ 0x003F0000, +/*09B7*/ 0x001A12FF, +/*09B8*/ 0x00051A00, +/*09B9*/ 0x001A13FF, +/*09BA*/ 0x00051B00, +/*09BB*/ 0x001F13FF, +/*09BC*/ 0x001F13FF, +/*09BD*/ 0x001A12FF, +/*09BE*/ 0x00051A00, +/*09BF*/ 0x001A13FF, +/*09C0*/ 0x00051B00, +/*09C1*/ 0x001F13FF, +/*09C2*/ 0x001F13FF, +/*09C3*/ 0x001A12FF, +/*09C4*/ 0x00051A00, +/*09C5*/ 0x001A13FF, +/*09C6*/ 0x00051B00, +/*09C7*/ 0x001F13FF, +/*09C8*/ 0x001F13FF, +/*09C9*/ 0x11910048, +/*09CA*/ 0x09910060, +/*09CB*/ 0x19A21009, +/*09CC*/ 0x19A10100, +/*09CD*/ 0x19A10201, +/*09CE*/ 0x19A10302, +/*09CF*/ 0x19A10A03, +/*09D0*/ 0x19A10B04, +/*09D1*/ 0x18051C00, +/*09D2*/ 0x19A1110A, +/*09D3*/ 0x19A1120B, +/*09D4*/ 0x19A1130C, +/*09D5*/ 0x19A1140D, +/*09D6*/ 0x19A1160E, +/*09D7*/ 0x181140BF, +/*09D8*/ 0x19A11009, +/*09D9*/ 0x18051900, +/*09DA*/ 0x19A10C05, +/*09DB*/ 0x10051F00, +/*09DC*/ 0x19A00C00, +/*09DD*/ 0x10001F00, +/*09DE*/ 0x19A10E07, +/*09DF*/ 0x10051F00, +/*09E0*/ 0x19A10F08, +/*09E1*/ 0x10051F00, +/*09E2*/ 0x181102FD, +/*09E3*/ 0x19A11C15, +/*09E4*/ 0x18051F00, +/*09E5*/ 0x19910280, +/*09E6*/ 0x19A21009, +/*09E7*/ 0x18051000, +/*09E8*/ 0x180E1200, +/*09E9*/ 0x18861101, +/*09EA*/ 0x181F0000, +/*09EB*/ 0x18861100, +/*09EC*/ 0x1810214A, +/*09ED*/ 0x1810314B, +/*09EE*/ 0x18101149, +/*09EF*/ 0x18061180, +/*09F0*/ 0x18067FC0, +/*09F1*/ 0x18101149, +/*09F2*/ 0x18051200, +/*09F3*/ 0x19A11C15, +/*09F4*/ 0x19A11009, +/*09F5*/ 0x18051800, +/*09F6*/ 0x101B0001, +/*09F7*/ 0x181B0100, +/*09F8*/ 0x18000500, +/*09F9*/ 0x181B0200, +/*09FA*/ 0x00000000, +/*09FB*/ 0x181B0600, +/*09FC*/ 0x181B0C00, +/*09FD*/ 0x181B0100, +/*09FE*/ 0x181B0200, +/*09FF*/ 0x181B0300, +/*0A00*/ 0x181B0400, +/*0A01*/ 0x1C440316, +/*0A02*/ 0x100D0000, +/*0A03*/ 0x101C0000, +/*0A04*/ 0x181F0000, +/*0A05*/ 0x09910260, +/*0A06*/ 0x11911600, +/*0A07*/ 0x19A21009, +/*0A08*/ 0x18051900, +/*0A09*/ 0x19A10100, +/*0A0A*/ 0x19A10201, +/*0A0B*/ 0x19A10302, +/*0A0C*/ 0x19A10A03, +/*0A0D*/ 0x19A10B04, +/*0A0E*/ 0x19A10C05, +/*0A0F*/ 0x19A10E07, +/*0A10*/ 0x19A10F08, +/*0A11*/ 0x19A1110A, +/*0A12*/ 0x19A1120B, +/*0A13*/ 0x19A1130C, +/*0A14*/ 0x19A1140D, +/*0A15*/ 0x19A00C00, +/*0A16*/ 0x199F0000, +/*0A17*/ 0x199F0000, +/*0A18*/ 0x001100BF, +/*0A19*/ 0x01A1120B, +/*0A1A*/ 0x080D0000, +/*0A1B*/ 0x001F0000, +/*0A1C*/ 0x001F0000, +/*0A1D*/ 0x001F0000, +/*0A1E*/ 0x080C0000, +/*0A1F*/ 0x001F0000, +/*0A20*/ 0x001F0000, +/*0A21*/ 0x001F0000, +/*0A22*/ 0x001F0000, +/*0A23*/ 0x001F0000, +/*0A24*/ 0x001F0200, +/*0A25*/ 0x00050000, +/*0A26*/ 0x00070100, +/*0A27*/ 0x000F0200, +/*0A28*/ 0x00000000, +/*0A29*/ 0x01A10100, +/*0A2A*/ 0x01A10201, +/*0A2B*/ 0x01A10302, +/*0A2C*/ 0x01A00B04, +/*0A2D*/ 0x00210D06, +/*0A2E*/ 0x01A1110A, +/*0A2F*/ 0x01A1140D, +/*0A30*/ 0x00098000, +/*0A31*/ 0x019F0000, +/*0A32*/ 0x01A10100, +/*0A33*/ 0x01A10201, +/*0A34*/ 0x01A10302, +/*0A35*/ 0x01A10A03, +/*0A36*/ 0x01A10B04, +/*0A37*/ 0x00210D06, +/*0A38*/ 0x01A1110A, +/*0A39*/ 0x00000000, +/*0A3A*/ 0x01A1140D, +/*0A3B*/ 0x00000000, +/*0A3C*/ 0x00000000, +/*0A3D*/ 0x01A11C15, +/*0A3E*/ 0x01A1120B, +/*0A3F*/ 0x01A0190F, +/*0A40*/ 0x000A0000, +/*0A41*/ 0x001F0000, +/*0A42*/ 0x000A0000, +/*0A43*/ 0x01061300, +/*0A44*/ 0x00000000, +/*0A45*/ 0x00000000, +/*0A46*/ 0x00061180, +/*0A47*/ 0x000612C0, +/*0A48*/ 0x00000000, +/*0A49*/ 0x00000000, +/*0A4A*/ 0x001F0000, +/*0A4B*/ 0x01910300, +/*0A4C*/ 0x01A21009, +/*0A4D*/ 0x019F0000, +/*0A4E*/ 0x001140BF, +/*0A4F*/ 0x01811009, +/*0A50*/ 0x00051900, +/*0A51*/ 0x01A10C05, +/*0A52*/ 0x00051F00, +/*0A53*/ 0x01A10C11, +/*0A54*/ 0x00051F00, +/*0A55*/ 0x001100BF, +/*0A56*/ 0x01811009, +/*0A57*/ 0x00051800, +/*0A58*/ 0x019F0000, +/*0A59*/ 0x019F0000, +/*0A5A*/ 0x019F0000, +/*0A5B*/ 0x019F0000, +/*0A5C*/ 0x019F0000, +/*0A5D*/ 0x01510001, +/*0A5E*/ 0x01D102A0, +/*0A5F*/ 0x01E21009, +/*0A60*/ 0x00051900, +/*0A61*/ 0x019F0000, +/*0A62*/ 0x01510001, +/*0A63*/ 0x01D10290, +/*0A64*/ 0x01E21009, +/*0A65*/ 0x00051900, +/*0A66*/ 0x01510001, +/*0A67*/ 0x01D10000, +/*0A68*/ 0x01E21009, +/*0A69*/ 0x00051800, +/*0A6A*/ 0x019F0000, +/*0A6B*/ 0x0011008F, +/*0A6C*/ 0x01811009, +/*0A6D*/ 0x00051800, +/*0A6E*/ 0x01910040, +/*0A6F*/ 0x01A21009, +/*0A70*/ 0x019F0000, +/*0A71*/ 0x01911000, +/*0A72*/ 0x01A21009, +/*0A73*/ 0x00051800, +/*0A74*/ 0x01A10100, +/*0A75*/ 0x01A10201, +/*0A76*/ 0x01A10302, +/*0A77*/ 0x01A10A03, +/*0A78*/ 0x01A10B04, +/*0A79*/ 0x01A10C05, +/*0A7A*/ 0x01A10E07, +/*0A7B*/ 0x01A10F08, +/*0A7C*/ 0x01A1110A, +/*0A7D*/ 0x01A1120B, +/*0A7E*/ 0x01A1130C, +/*0A7F*/ 0x01A1140D, +/*0A80*/ 0x01A00C00, +/*0A81*/ 0x01910800, +/*0A82*/ 0x01A21009, +/*0A83*/ 0x019F0000, +/*0A84*/ 0x01811009, +/*0A85*/ 0x0011EFAF, +/*0A86*/ 0x01A1120B, +/*0A87*/ 0x001F0000, +/*0A88*/ 0x001F0200, +/*0A89*/ 0x001100EF, +/*0A8A*/ 0x01A1120B, +/*0A8B*/ 0x001F0000, +/*0A8C*/ 0x01A1120B, +/*0A8D*/ 0x001F0000, +/*0A8E*/ 0x001F0000, +/*0A8F*/ 0x001100EF, +/*0A90*/ 0x01A1120B, +/*0A91*/ 0x001F0000, +/*0A92*/ 0x00211F14, +/*0A93*/ 0x00212015, +/*0A94*/ 0x00212116, +/*0A95*/ 0x00212217, +/*0A96*/ 0x01A1120B, +/*0A97*/ 0x001F0000, +/*0A98*/ 0x00211F14, +/*0A99*/ 0x00212015, +/*0A9A*/ 0x00212116, +/*0A9B*/ 0x00212217, +/*0A9C*/ 0x001F0000, +/*0A9D*/ 0x001A85FF, +/*0A9E*/ 0x001F0000, +/*0A9F*/ 0x001100FF, +/*0AA0*/ 0x01810302, +/*0AA1*/ 0x001100DF, +/*0AA2*/ 0x00010D06, +/*0AA3*/ 0x001100EF, +/*0AA4*/ 0x01A1120B, +/*0AA5*/ 0x001F0000, +/*0AA6*/ 0x00010D06, +/*0AA7*/ 0x01810302, +/*0AA8*/ 0x0181160E, +/*0AA9*/ 0x01A1120B, +/*0AAA*/ 0x001F0000, +/*0AAB*/ 0x00032300, +/*0AAC*/ 0x00032400, +/*0AAD*/ 0x001F0000, +/*0AAE*/ 0x0031FFBF, +/*0AAF*/ 0x01A11009, +/*0AB0*/ 0x00051900, +/*0AB1*/ 0x01A10E07, +/*0AB2*/ 0x00051F00, +/*0AB3*/ 0x01A10F08, +/*0AB4*/ 0x00051F00, +/*0AB5*/ 0x003100BF, +/*0AB6*/ 0x01A11009, +/*0AB7*/ 0x00051800, +/*0AB8*/ 0x003F0000, +/*0AB9*/ 0x003F0000, +/*0ABA*/ 0x003F0000, +/*0ABB*/ 0x003F0000, +/*0ABC*/ 0x003F0000, +/*0ABD*/ 0x0031FFBF, +/*0ABE*/ 0x01A11009, +/*0ABF*/ 0x00051900, +/*0AC0*/ 0x01A10E07, +/*0AC1*/ 0x00051F00, +/*0AC2*/ 0x01A10F08, +/*0AC3*/ 0x00051F00, +/*0AC4*/ 0x003100BF, +/*0AC5*/ 0x01A11009, +/*0AC6*/ 0x00051800, +/*0AC7*/ 0x003F0000, +/*0AC8*/ 0x003F0000, +/*0AC9*/ 0x003F0000, +/*0ACA*/ 0x003F0000, +/*0ACB*/ 0x003F0000, +/*0ACC*/ 0x001100EF, +/*0ACD*/ 0x01A1120B, +/*0ACE*/ 0x00051400, +/*0ACF*/ 0x001A0800, +/*0AD0*/ 0x001102FD, +/*0AD1*/ 0x00012E00, +/*0AD2*/ 0x00000000, +/*0AD3*/ 0x001F0000, +/*0AD4*/ 0x001100FD, +/*0AD5*/ 0x00012E00, +/*0AD6*/ 0x00051700, +/*0AD7*/ 0x001A0801, +/*0AD8*/ 0x01A1120B, +/*0AD9*/ 0x001F0000, +/*0ADA*/ 0x001100EF, +/*0ADB*/ 0x01A1120B, +/*0ADC*/ 0x00051400, +/*0ADD*/ 0x001A0800, +/*0ADE*/ 0x001101FC, +/*0ADF*/ 0x00011A00, +/*0AE0*/ 0x00000000, +/*0AE1*/ 0x001F0000, +/*0AE2*/ 0x00051500, +/*0AE3*/ 0x001103FC, +/*0AE4*/ 0x00011A00, +/*0AE5*/ 0x00051500, +/*0AE6*/ 0x001102FC, +/*0AE7*/ 0x00011A00, +/*0AE8*/ 0x00001A00, +/*0AE9*/ 0x00000000, +/*0AEA*/ 0x001F0000, +/*0AEB*/ 0x001100FC, +/*0AEC*/ 0x00011A00, +/*0AED*/ 0x001A0801, +/*0AEE*/ 0x01A1120B, +/*0AEF*/ 0x00000000, +/*0AF0*/ 0x001F0000, +/*0AF1*/ 0x001108E7, +/*0AF2*/ 0x01A1120B, +/*0AF3*/ 0x00051400, +/*0AF4*/ 0x01910480, +/*0AF5*/ 0x01821009, +/*0AF6*/ 0x001F0000, +/*0AF7*/ 0x001A0800, +/*0AF8*/ 0x01A11E14, +/*0AF9*/ 0x001101FC, +/*0AFA*/ 0x00211A00, +/*0AFB*/ 0x00051500, +/*0AFC*/ 0x001103FC, +/*0AFD*/ 0x00011A00, +/*0AFE*/ 0x00051500, +/*0AFF*/ 0x001102FC, +/*0B00*/ 0x00011A00, +/*0B01*/ 0x00031A00, +/*0B02*/ 0x001A0801, +/*0B03*/ 0x00000000, +/*0B04*/ 0x001F0000, +/*0B05*/ 0x01A11E14, +/*0B06*/ 0x001108F7, +/*0B07*/ 0x01A1120B, +/*0B08*/ 0x001F0000, +/*0B09*/ 0x00000000, +/*0B0A*/ 0x00000000, +/*0B0B*/ 0x00000000, +/*0B0C*/ 0x00000000, +/*0B0D*/ 0x00000000, +/*0B0E*/ 0x00000000, +/*0B0F*/ 0x00000000, +/*0B10*/ 0x00000000, +/*0B11*/ 0x00000000, +/*0B12*/ 0x001F0000, +/*0B13*/ 0x0404FF7F, +/*0B14*/ 0x0404FF7F, +/*0B15*/ 0x0404FF7F, +/*0B16*/ 0x0404FF7F, +/*0B17*/ 0x0404FF7F, +/*0B18*/ 0x0404FF7F, +/*0B19*/ 0x0404FF7F, +/*0B1A*/ 0x0404FF7F, +/*0B1B*/ 0x00000000, +/*0B1C*/ 0x00000000, +/*0B1D*/ 0x00000000, +/*0B1E*/ 0x00000000, +/*0B1F*/ 0x00000000, +/*0B20*/ 0x00000000, +/*0B21*/ 0x00000000, +/*0B22*/ 0x00000000, +/*0B23*/ 0x00000000, +/*0B24*/ 0x00000000, +/*0B25*/ 0x00000000, +/*0B26*/ 0x00000000, +/*0B27*/ 0x00000000, +/*0B28*/ 0x00000000, +/*0B29*/ 0x00000000, +/*0B2A*/ 0x00000000, +/*0B2B*/ 0x00000000, +/*0B2C*/ 0x00000000, +/*0B2D*/ 0x00000000, +/*0B2E*/ 0x00000000, +/*0B2F*/ 0x00000000, +/*0B30*/ 0x00000000, +/*0B31*/ 0x00000000, +/*0B32*/ 0x00000000, +/*0B33*/ 0x00000000, +/*0B34*/ 0x00000000, +/*0B35*/ 0x00000000, +/*0B36*/ 0x00000000, +/*0B37*/ 0x00000000, +/*0B38*/ 0x00000000, +/*0B39*/ 0x00000000, +/*0B3A*/ 0x00000000, +/*0B3B*/ 0x00000000, +/*0B3C*/ 0x00000000, +/*0B3D*/ 0x00000000, +/*0B3E*/ 0x00000000, +/*0B3F*/ 0x00000000, +/*0B40*/ 0x00000000, +/*0B41*/ 0x00000000, +/*0B42*/ 0x00000000, +/*0B43*/ 0x00000000, +/*0B44*/ 0x00000000, +/*0B45*/ 0x00000000, +/*0B46*/ 0x00000000, +/*0B47*/ 0x00000000, +/*0B48*/ 0x00000000, +/*0B49*/ 0x00000000, +/*0B4A*/ 0x00000000, +/*0B4B*/ 0x00000000, +/*0B4C*/ 0x00000000, +/*0B4D*/ 0x00000000, +/*0B4E*/ 0x00000000, +/*0B4F*/ 0x00000000, +/*0B50*/ 0x00000000, +/*0B51*/ 0x00000000, +/*0B52*/ 0x00000000, +/*0B53*/ 0x00000000, +/*0B54*/ 0x00000000, +/*0B55*/ 0x00000000, +/*0B56*/ 0x00000000, +/*0B57*/ 0x00000000, +/*0B58*/ 0x00000000, +/*0B59*/ 0x00000000, +/*0B5A*/ 0x00000000, +/*0B5B*/ 0x00000000, +/*0B5C*/ 0x00000000, +/*0B5D*/ 0x00000000, +/*0B5E*/ 0x00000000, +/*0B5F*/ 0x00000000, +/*0B60*/ 0x00000000, +/*0B61*/ 0x00000000, +/*0B62*/ 0x00000000, +/*0B63*/ 0x00000000, +/*0B64*/ 0x00000000, +/*0B65*/ 0x00000000, +/*0B66*/ 0x00000000, +/*0B67*/ 0x00000000, +/*0B68*/ 0x00000000, +/*0B69*/ 0x00000000, +/*0B6A*/ 0x00000000, +/*0B6B*/ 0x00000000, +/*0B6C*/ 0x00000000, +/*0B6D*/ 0x00000000, +/*0B6E*/ 0x00000000, +/*0B6F*/ 0x00000000, +/*0B70*/ 0x00000000, +/*0B71*/ 0x00000000, +/*0B72*/ 0x00000000, +/*0B73*/ 0x00000000, +/*0B74*/ 0x00000000, +/*0B75*/ 0x00000000, +/*0B76*/ 0x00000000, +/*0B77*/ 0x00000000, +/*0B78*/ 0x00000000, +/*0B79*/ 0x00000000, +/*0B7A*/ 0x00000000, +/*0B7B*/ 0x00000000, +/*0B7C*/ 0x00000000, +/*0B7D*/ 0x00000000, +/*0B7E*/ 0x00000000, +/*0B7F*/ 0x00000000, +/*0B80*/ 0x00000000, +/*0B81*/ 0x00000000, +/*0B82*/ 0x00070000, +/*0B83*/ 0x0011000B, +/*0B84*/ 0x001D0017, +/*0B85*/ 0x0059003F, +/*0B86*/ 0x0072006C, +/*0B87*/ 0x00790078, +/*0B88*/ 0x00960086, +/*0B89*/ 0x00A2009F, +/*0B8A*/ 0x00B600B1, +/*0B8B*/ 0x00C500BF, +/*0B8C*/ 0x00DC00D8, +/*0B8D*/ 0x00E000DD, +/*0B8E*/ 0x00E600E3, +/*0B8F*/ 0x00F100EC, +/*0B90*/ 0x00FA00F3, +/*0B91*/ 0x010200FF, +/*0B92*/ 0x01200111, +/*0B93*/ 0x012E0128, +/*0B94*/ 0x013F0136, +/*0B95*/ 0x014B0145, +/*0B96*/ 0x015D0159, +/*0B97*/ 0x01680167, +/*0B98*/ 0x016A0169, +/*0B99*/ 0x016C016B, +/*0B9A*/ 0x016E016D, +/*0B9B*/ 0x00000000, +/*0B9C*/ 0x00000000, +/*0B9D*/ 0x004B1040, +/*0B9E*/ 0x001011C0, +/*0B9F*/ 0x00089080, +/*0BA0*/ 0x000811C0, +/*0BA1*/ 0x040811C0, +/*0BA2*/ 0x02000000, +/*0BA3*/ 0x00000000, +/*0BA4*/ 0x00000000, +/*0BA5*/ 0x00000000, +/*0BA6*/ 0x00000000, +/*0BA7*/ 0x00000000, +/*0BA8*/ 0x00000000, +/*0BA9*/ 0x00000000, +/*0BAA*/ 0x00000000, +/*0BAB*/ 0x00000000, +/*0BAC*/ 0x00000000, +/*0BAD*/ 0x00000000, +/*0BAE*/ 0x00000000, +/*0BAF*/ 0x00000000, +/*0BB0*/ 0x00000000, +/*0BB1*/ 0x00000000, +/*0BB2*/ 0x00000000, +/*0BB3*/ 0x5F407FAA, +/*0BB4*/ 0x007B776F, +/*0BB5*/ 0x4AB555AA, +/*0BB6*/ 0xB5A9A956, +/*0BB7*/ 0x9F80BFAA, +/*0BB8*/ 0x00BBB7AF, +/*0BB9*/ 0x00000000, +/*0BBA*/ 0x00000000, +/*0BBB*/ 0x00000000, +/*0BBC*/ 0x00000000, +/*0BBD*/ 0x00000000, +/*0BBE*/ 0x00000000, +/*0BBF*/ 0x00000000, +/*0BC0*/ 0x00000000, +/*0BC1*/ 0x0000157C, +/*0BC2*/ 0x0000D6D8, +/*0BC3*/ 0x00000037, +/*0BC4*/ 0x00000000, +/*0BC5*/ 0x00000000, +/*0BC6*/ 0x00000000, +/*0BC7*/ 0x00000000, +/*0BC8*/ 0x00000000, +/*0BC9*/ 0x00000000, +/*0BCA*/ 0x00000000, +/*0BCB*/ 0x00000000, +/*0BCC*/ 0x00000000, +/*0BCD*/ 0x00000000, +/*0BCE*/ 0x00000000, +/*0BCF*/ 0x00000000, +/*0BD0*/ 0x00000000, +/*0BD1*/ 0x00000007, +/*0BD2*/ 0x00000032, +/*0BD3*/ 0x000000C8, +/*0BD4*/ 0x00000001, +/*0BD5*/ 0x00000001, +/*0BD6*/ 0x00000003, +/*0BD7*/ 0x00000007, +/*0BD8*/ 0x00000007, +/*0BD9*/ 0x00000009, +/*0BDA*/ 0x00000001, +/*0BDB*/ 0x00000001, +/*0BDC*/ 0x00000003, +/*0BDD*/ 0x00000001, +/*0BDE*/ 0x00000001, +/*0BDF*/ 0x00000003, +/*0BE0*/ 0x00000037, +/*0BE1*/ 0x00000190, +/*0BE2*/ 0x00000640, +/*0BE3*/ 0x00000001, +/*0BE4*/ 0x00000001, +/*0BE5*/ 0x00000003, +/*0BE6*/ 0x00000001, +/*0BE7*/ 0x00000007, +/*0BE8*/ 0x0000001C, +/*0BE9*/ 0x00000004, +/*0BEA*/ 0x00000015, +/*0BEB*/ 0x00000051, +/*0BEC*/ 0x00000008, +/*0BED*/ 0x00000033, +/*0BEE*/ 0x000000C9, +/*0BEF*/ 0x00000007, +/*0BF0*/ 0x00000002, +/*0BF1*/ 0x0000000E, +/*0BF2*/ 0x00000000, +/*0BF3*/ 0x00000000, +/*0BF4*/ 0x00000005, +/*0BF5*/ 0x00000008, +/*0BF6*/ 0x00000008, +/*0BF7*/ 0x00000008, +/*0BF8*/ 0x00000000, +/*0BF9*/ 0x00000000, +/*0BFA*/ 0x00000000, +/*0BFB*/ 0x0000157D, +/*0BFC*/ 0x0000157D, +/*0BFD*/ 0x0000157D, +/*0BFE*/ 0x00000008, +/*0BFF*/ 0x00000033, +/*0C00*/ 0x000000C9, +/*0C01*/ 0x00000000, +/*0C02*/ 0x00000000, +/*0C03*/ 0x00000000, +/*0C04*/ 0x00000000, +/*0C05*/ 0x00000000, +/*0C06*/ 0x00000000, +/*0C07*/ 0x00000000, +/*0C08*/ 0x00000000, +/*0C09*/ 0x00000000, +/*0C0A*/ 0x00000000, +/*0C0B*/ 0x00000000, +/*0C0C*/ 0x00000000, +/*0C0D*/ 0x000D000F, +/*0C0E*/ 0x00040028, +/*0C0F*/ 0x00060002, +/*0C10*/ 0x0009000C, +/*0C11*/ 0x000C0010, +/*0C12*/ 0x00150009, +/*0C13*/ 0x00040006, +/*0C14*/ 0x0004000B, +/*0C15*/ 0x00020002, +/*0C16*/ 0x00020004, +/*0C17*/ 0x00040002, +/*0C18*/ 0x00020002, +/*0C19*/ 0x00020004, +/*0C1A*/ 0x000F0002, +/*0C1B*/ 0x0028000D, +/*0C1C*/ 0x00020004, +/*0C1D*/ 0x000C0006, +/*0C1E*/ 0x00100009, +/*0C1F*/ 0x0009000C, +/*0C20*/ 0x00060015, +/*0C21*/ 0x000B0004, +/*0C22*/ 0x00020004, +/*0C23*/ 0x00040002, +/*0C24*/ 0x00020002, +/*0C25*/ 0x00020004, +/*0C26*/ 0x00040002, +/*0C27*/ 0x00020002, +/*0C28*/ 0x000D000F, +/*0C29*/ 0x00040028, +/*0C2A*/ 0x00060002, +/*0C2B*/ 0x0009000C, +/*0C2C*/ 0x000C0010, +/*0C2D*/ 0x00150009, +/*0C2E*/ 0x00040006, +/*0C2F*/ 0x0004000B, +/*0C30*/ 0x00020002, +/*0C31*/ 0x00020004, +/*0C32*/ 0x00040002, +/*0C33*/ 0x00020002, +/*0C34*/ 0x00020004, +/*0C35*/ 0x000F0002, +/*0C36*/ 0x0028000D, +/*0C37*/ 0x00020004, +/*0C38*/ 0x000C0006, +/*0C39*/ 0x00100009, +/*0C3A*/ 0x0009000C, +/*0C3B*/ 0x00060015, +/*0C3C*/ 0x000B0004, +/*0C3D*/ 0x00020004, +/*0C3E*/ 0x00040002, +/*0C3F*/ 0x00020002, +/*0C40*/ 0x00020004, +/*0C41*/ 0x00040002, +/*0C42*/ 0x00020002, +/*0C43*/ 0x00000000, +/*0C44*/ 0x00000000, +/*0C45*/ 0x00000000, +/*0C46*/ 0x00000000, +/*0C47*/ 0x00000000, +/*0C48*/ 0x00000000, +/*0C49*/ 0x00000000, +/*0C4A*/ 0x00000000, +/*0C4B*/ 0x00000000, +/*0C4C*/ 0x00000000, +/*0C4D*/ 0x00000000, +/*0C4E*/ 0x00000000, +/*0C4F*/ 0x00000000, +/*0C50*/ 0x00000000, +/*0C51*/ 0x00000000, +/*0C52*/ 0x00000000, +/*0C53*/ 0x00000000, +/*0C54*/ 0x00000000, +/*0C55*/ 0x00000000, +/*0C56*/ 0x00000000, +/*0C57*/ 0x00000000, +/*0C58*/ 0x00000000, +/*0C59*/ 0x00000000, +/*0C5A*/ 0x00000000, +/*0C5B*/ 0x00000000, +/*0C5C*/ 0x00000000, +/*0C5D*/ 0x00000000, +/*0C5E*/ 0x00000000, +/*0C5F*/ 0x00000000, +/*0C60*/ 0x00000000, +/*0C61*/ 0x00000000, +/*0C62*/ 0x00000000, +/*0C63*/ 0x00000000, +/*0C64*/ 0x00000000, +/*0C65*/ 0x00000000, +/*0C66*/ 0x000000C0, +/*0C67*/ 0x00000000, +/*0C68*/ 0x00000000, +/*0C69*/ 0x55550000, +/*0C6A*/ 0x00003C5A, +/*0C6B*/ 0x00000000, +/*0C6C*/ 0x00000000, +/*0C6D*/ 0x00000000, +/*0C6E*/ 0x00000000, +/*0C6F*/ 0x00000000, +/*0C70*/ 0x00000000, +/*0C71*/ 0x00000000, +/*0C72*/ 0x00000000, +/*0C73*/ 0x00000000, +/*0C74*/ 0x00000000, +/*0C75*/ 0x00000000, +/*0C76*/ 0x00000000, +/*0C77*/ 0x00000000, +/*0C78*/ 0x00000000, +/*0C79*/ 0x00000000, +/*0C7A*/ 0x00000000, +/*0C7B*/ 0x00000000, +/*0C7C*/ 0x00000000, +/*0C7D*/ 0x00000000, +/*0C7E*/ 0x00000000, +/*0C7F*/ 0x00000000, +/*0C80*/ 0x00000000, +/*0C81*/ 0x00000000, +/*0C82*/ 0x00000000, +/*0C83*/ 0x00000000, +/*0C84*/ 0x00000000, +/*0C85*/ 0x00000000, +/*0C86*/ 0x00000000, +/*0C87*/ 0x00000000, +/*0C88*/ 0x00000000, +/*0C89*/ 0x00000000, +/*0C8A*/ 0x00000000, +/*0C8B*/ 0x00000000, +/*0C8C*/ 0x00000000, +/*0C8D*/ 0x00000000, +/*0C8E*/ 0x00000000, +/*0C8F*/ 0x00000000, +/*0C90*/ 0x00000000, +/*0C91*/ 0x00000000, +/*0C92*/ 0x00000000, +/*0C93*/ 0x00000000, +/*0C94*/ 0x00000000, +/*0C95*/ 0x00000000, +/*0C96*/ 0x00000000, +/*0C97*/ 0x00000000, +/*0C98*/ 0x00000000, +/*0C99*/ 0x00000000, +/*0C9A*/ 0x00000000, +/*0C9B*/ 0x00000000, +/*0C9C*/ 0x00000000, +/*0C9D*/ 0x00D60000, +/*0C9E*/ 0x50005000, +/*0C9F*/ 0x803E0050, +/*0CA0*/ 0x80000200, +/*0CA1*/ 0x00000000, +/*0CA2*/ 0x00002000, +/*0CA3*/ 0x00000000, +/*0CA4*/ 0x00000000, +/*0CA5*/ 0x00000000, +/*0CA6*/ 0x00000000, +/*0CA7*/ 0x00D62220, +/*0CA8*/ 0x2C002834, +/*0CA9*/ 0x0406002C, +/*0CAA*/ 0x80000200, +/*0CAB*/ 0x00000000, +/*0CAC*/ 0x00002000, +/*0CAD*/ 0x00000000, +/*0CAE*/ 0x00000000, +/*0CAF*/ 0x00000000, +/*0CB0*/ 0x00000000, +/*0CB1*/ 0x00C6BBB0, +/*0CB2*/ 0x2C002834, +/*0CB3*/ 0x0C06002C, +/*0CB4*/ 0x80000200, +/*0CB5*/ 0x00000000, +/*0CB6*/ 0x00002000, +/*0CB7*/ 0x00000000, +/*0CB8*/ 0x00000000, +/*0CB9*/ 0x00000000, +/*0CBA*/ 0x00000000, +/*0CBB*/ 0x00D60000, +/*0CBC*/ 0x50005000, +/*0CBD*/ 0x803E0050, +/*0CBE*/ 0x80000200, +/*0CBF*/ 0x00000000, +/*0CC0*/ 0x00002000, +/*0CC1*/ 0x00000000, +/*0CC2*/ 0x00000000, +/*0CC3*/ 0x00000000, +/*0CC4*/ 0x00000000, +/*0CC5*/ 0x00D62220, +/*0CC6*/ 0x2C002834, +/*0CC7*/ 0x002E002C, +/*0CC8*/ 0x80000200, +/*0CC9*/ 0x00000000, +/*0CCA*/ 0x00002000, +/*0CCB*/ 0x00000000, +/*0CCC*/ 0x00000000, +/*0CCD*/ 0x00000000, +/*0CCE*/ 0x00000000, +/*0CCF*/ 0x00C6BBB0, +/*0CD0*/ 0x2C002834, +/*0CD1*/ 0x082E002C, +/*0CD2*/ 0x80000200, +/*0CD3*/ 0x00000000, +/*0CD4*/ 0x00002000, +/*0CD5*/ 0x00000000, +/*0CD6*/ 0x00000000, +/*0CD7*/ 0x00000000, +/*0CD8*/ 0x00000000, +/*0CD9*/ 0x20002000, +/*0CDA*/ 0x20002000, +/*0CDB*/ 0x20002000, +/*0CDC*/ 0x2000000D, +/*0CDD*/ 0x20002000, +/*0CDE*/ 0x20002000, +/*0CDF*/ 0x20002000, +/*0CE0*/ 0x00172000, +/*0CE1*/ 0x20000025, +/*0CE2*/ 0x20002000, +/*0CE3*/ 0x0020001F, +/*0CE4*/ 0x00220021, +/*0CE5*/ 0x20002000, +/*0CE6*/ 0x20002000, +/*0CE7*/ 0x20002000, +/*0CE8*/ 0x20002000, +/*0CE9*/ 0x20002000, +/*0CEA*/ 0x20002000, +/*0CEB*/ 0x20002000, +/*0CEC*/ 0x20002000, +/*0CED*/ 0x20002000, +/*0CEE*/ 0x20002000, +/*0CEF*/ 0x20002000, +/*0CF0*/ 0x20002000, +/*0CF1*/ 0x20002000, +/*0CF2*/ 0x20002000, +/*0CF3*/ 0x20002000, +/*0CF4*/ 0x20002000, +/*0CF5*/ 0x20002000, +/*0CF6*/ 0x20002000, +/*0CF7*/ 0x20002000, +/*0CF8*/ 0x20002000, +/*0CF9*/ 0x20002000, +/*0CFA*/ 0x20002000, +/*0CFB*/ 0x20002000, +/*0CFC*/ 0x20002000, +/*0CFD*/ 0x20002000, +/*0CFE*/ 0x20002000, +/*0CFF*/ 0x20002000, +/*0D00*/ 0x20002000, +/*0D01*/ 0x00020001, +/*0D02*/ 0x000A0003, +/*0D03*/ 0x000C000B, +/*0D04*/ 0x000E2000, +/*0D05*/ 0x0010000F, +/*0D06*/ 0x00120011, +/*0D07*/ 0x00140013, +/*0D08*/ 0x00190016, +/*0D09*/ 0x100C2000, +/*0D0A*/ 0x00080000, +/*0D0B*/ 0x001C001E, +/*0D0C*/ 0x20002000, +/*0D0D*/ 0x20002000, +/*0D0E*/ 0x20002000, +/*0D0F*/ 0x20002000, +/*0D10*/ 0x20002000, +/*0D11*/ 0x20002000, +/*0D12*/ 0x20002000, +/*0D13*/ 0x20002000, +/*0D14*/ 0x20002000 +}; + +#endif /* INIT_DRAM_TBL_V4M_LP5_H_ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_boot.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_boot.c new file mode 100644 index 0000000..1a53474 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_boot.c @@ -0,0 +1,95 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc boot + ******************************************************************************/ +/****************************************************************************** + * @file emmc_boot.c + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 18.03.2022 0.02 Removed unnecessary functions + * Removed unnecessary header file inclusions + * : 16.06.2022 0.03 Change log output + * : 31.10.2022 0.04 License notation change. + *****************************************************************************/ + +#include "emmc_boot.h" +#include "log.h" +#include "emmc_std.h" +#include "emmc_def.h" + + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Unions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Structs */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Globals */ +/************************************************************************************************/ + +/************************************************************************************************/ +/* Macros */ +/************************************************************************************************/ + +/************************************************************************************************/ +/* Prototypes */ +/************************************************************************************************/ + +void emmc_initialize( void ) +{ + EMMC_ERROR_CODE result; + + /* eMMC driver initialize */ + (void)emmc_init(); /* Normal clock mode */ + + /* Card power on */ + (void)emmc_memcard_power(TRUE); + + /* Card mount */ + result = emmc_mount(); + + if (result != EMMC_SUCCESS) + { + NOTICE("eMMC initialize error!!\n"); + panic; + } +} diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_cmd.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_cmd.c new file mode 100644 index 0000000..29c83d9 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_cmd.c @@ -0,0 +1,622 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc command + ******************************************************************************/ +/****************************************************************************** + * @file emmc_cmd.c + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 16.06.2022 0.02 Change log output + * : 31.10.2022 0.03 License notation change. + * : 07.06.2024 0.04 Modify the transfer end bit of DMAC channel. + *****************************************************************************/ + +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "timer.h" +#include "log.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static void emmc_read_response(uint32_t *response); +static void emmc_little_to_big(uint8_t *p, uint32_t value); +static void emmc_data_transfer_dma(void); +static EMMC_ERROR_CODE emmc_response_check(const uint32_t *response, uint32_t error_mask); +static void emmc_softreset(void); +static void emmc_WaitCmd2Cmd_8Cycle(void); + +/* ********************************* CODE ********************************** */ + +/* execute MMC command. + * + * - Pre-conditions:
+ * * Clock to memory card IF is enabled. + * - Post-conditions:
+ * Requested command is executed successfully + * + * param[in] error_mask Errors to be checked (error values; HAL_MEMCARD_ERRORS) + * param[in,out] *response Response from the card (virtual address) + * return eMMC error code. + */ +EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response) +{ + EMMC_ERROR_CODE rtn_code = EMMC_ERR; + HAL_MEMCARD_RESPONSE_TYPE response_type; + HAL_MEMCARD_COMMAND_TYPE cmd_type; + EMMC_INT_STATE state; + + /* parameter check */ + if (response == NULL) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.clock_enable != TRUE) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + if (mmc_drv_obj.state_machine_blocking == TRUE) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR); + return EMMC_ERR; + } + + state = ESTATE_BEGIN; + response_type = (HAL_MEMCARD_RESPONSE_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK); + cmd_type = (HAL_MEMCARD_COMMAND_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_COMMAND_TYPE_MASK); + + /* state machine */ + while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END)) + { + /* The interrupt factor flag is observed. */ + (void)emmc_interrupt(); + + /* wait interrupt */ + if (mmc_drv_obj.state_machine_blocking == TRUE) + { + continue; + } + + switch (state) + { + case ESTATE_BEGIN: + /* Busy check */ + if ((mmc_drv_obj.error_info.info2 & SD_INFO2_CBSY) != 0U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR_CARD_BUSY; + } + + /* clear register */ + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, SD_INFO2_CLEAR); + mem_write32(SD_INFO1_MASK, SD_INFO1_INFO0); + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + + /* fallthrough */ + + case ESTATE_ISSUE_CMD: + /* ARG */ + mem_write32(SD_ARG, mmc_drv_obj.cmd_info.arg); + /* issue cmd */ + mem_write32(SD_CMD, mmc_drv_obj.cmd_info.hw); + /* Set driver flag */ + mmc_drv_obj.state_machine_blocking = TRUE; + + if (response_type == HAL_MEMCARD_RESPONSE_NONE) + { + state = ESTATE_NON_RESP_CMD; + } else { + state = ESTATE_RCV_RESP; + } + + break; + + case ESTATE_NON_RESP_CMD: + /* interrupt disable */ + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); + + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) + { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 0U) { + /* not receive expected interrupt */ + rtn_code = EMMC_ERR_RESPONSE; + state = ESTATE_ERROR; + } else { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } + break; + + case ESTATE_RCV_RESP: + /* interrupt disable */ + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); + + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) + { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + break; + } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 0U) { + /* not receive expected interrupt */ + rtn_code = EMMC_ERR_RESPONSE; + state = ESTATE_ERROR; + break; + } else { + /* nop */ + } + + /* read response */ + emmc_read_response(response); + + /* check response */ + rtn_code = emmc_response_check(response, error_mask); + if (rtn_code != EMMC_SUCCESS) + { + state = ESTATE_ERROR; + break; + } + + if (response_type == HAL_MEMCARD_RESPONSE_R1b) + { + /* R1b */ + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + state = ESTATE_RCV_RESPONSE_BUSY; + } else { + state = ESTATE_CHECK_RESPONSE_COMPLETE; + } + break; + + case ESTATE_RCV_RESPONSE_BUSY: + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) + { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + break; + } + /* DAT0 not Busy */ + if ((SD_INFO2_DAT0 & mmc_drv_obj.error_info.info2) != 0U) + { + state = ESTATE_CHECK_RESPONSE_COMPLETE; + break; + } + break; + + case ESTATE_CHECK_RESPONSE_COMPLETE: + if (cmd_type >= HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE) + { + state = ESTATE_DATA_TRANSFER; + } else { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } + break; + + case ESTATE_DATA_TRANSFER: + /* ADTC command */ + mmc_drv_obj.during_transfer = TRUE; + mmc_drv_obj.state_machine_blocking = TRUE; + + if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) + { + /* DMA */ + emmc_data_transfer_dma(); + } else { + /* PIO */ + /* interrupt enable (FIFO read/write enable) */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) + { + mem_write32(SD_INFO2_MASK, ( SD_INFO2_BWE | SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + } else { + mem_write32(SD_INFO2_MASK, ( SD_INFO2_BRE | SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + } + } + state = ESTATE_DATA_TRANSFER_COMPLETE; + break; + + case ESTATE_DATA_TRANSFER_COMPLETE: + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) + { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_TRANSFER_ERROR; + break; + } else { + /* success. nothing to do. */ + } + + /* DMAC error ? */ + if (mmc_drv_obj.dma_error_flag == TRUE) + { + /* Error occurred in DMAC driver. */ + rtn_code = EMMC_ERR_FROM_DMAC_TRANSFER; + state = ESTATE_TRANSFER_ERROR; + } else if (mmc_drv_obj.during_dma_transfer == TRUE) { + /* DMAC not finished. unknown error */ + rtn_code = EMMC_ERR; + state = ESTATE_TRANSFER_ERROR; + } else { + mem_write32(SD_INFO1_MASK, SD_INFO1_INFO2); + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + + mmc_drv_obj.state_machine_blocking = TRUE; + + state = ESTATE_ACCESS_END; + } + break; + + case ESTATE_ACCESS_END: + + /* clear flag */ + if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) + { + mem_write32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ + mem_write32(SD_STOP, 0x00000000U); + mmc_drv_obj.during_dma_transfer = FALSE; + } + + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, SD_INFO2_CLEAR); + + if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO2) != 0U) + { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } else { + state = ESTATE_ERROR; + } + break; + + case ESTATE_TRANSFER_ERROR: + /* The error occurred in the Data transfer. */ + if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) + { + mem_write32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ + mem_write32(SD_STOP, 0x00000000U); + mmc_drv_obj.during_dma_transfer = FALSE; + } + /* fallthrough */ + + case ESTATE_ERROR: + emmc_softreset(); + ERROR("%s:0x%x\n",__func__,rtn_code); + return rtn_code; + + default: + state = ESTATE_END; + break; + } /* switch (state) */ + } /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */ + + /* force terminate */ + if (mmc_drv_obj.force_terminate == TRUE) + { + /* timeout timer is expired. Or, PIO data transfer error. */ + /* Timeout occurred in the DMA transfer. */ + if (mmc_drv_obj.during_dma_transfer == TRUE) + { + mmc_drv_obj.during_dma_transfer = FALSE; + } + emmc_softreset(); + + return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */ + } + + /* success */ + mmc_drv_obj.during_transfer = FALSE; + + return EMMC_SUCCESS; +} + +/** host controller softrest. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param None. + * return None. + */ +static void emmc_softreset(void) +{ + int32_t loop = 10000; + int32_t retry = 1000; + + /* flag clear */ + mmc_drv_obj.during_transfer = FALSE; + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.state_machine_blocking = FALSE; + mmc_drv_obj.force_terminate = FALSE; + mmc_drv_obj.dma_error_flag = FALSE; + + /* during operation ? */ + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U) + { + /* wait CMDSEQ = 0 */ + while (loop > 0) + { + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) == 0U) + { + break; /* ready */ + } + + loop--; + if ((loop == 0) && (retry > 0)) + { + micro_wait(1000U); /* wait 1ms */ + loop = 10000; + retry--; + } + } + } + + /* reset */ + mem_write32(SOFT_RST, ( mem_read32(SOFT_RST) & (~SOFT_RST_SDRST) )); /* Soft reset */ + mem_write32(SOFT_RST, ( mem_read32(SOFT_RST) | SOFT_RST_SDRST )); /* Soft reset released */ + + /* initialize */ + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, SD_INFO2_CLEAR); + mem_write32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ + +} + +/** read response + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * param[in,out] *response Response from the card + * return None. + */ +static void emmc_read_response(uint32_t *response) +{ + + uint8_t *p = NULL; + + if (response == NULL) + { + return; + } + + /* read response */ + if (mmc_drv_obj.response_length == EMMC_MAX_RESPONSE_LENGTH) + { + /* CSD or CID */ + p = (uint8_t *)(response); + emmc_little_to_big(p, ((mem_read32(SD_RSP76) << 8U) | (mem_read32(SD_RSP54) >> 24U))); /* [127:96] */ + emmc_little_to_big(p + 4U, ((mem_read32(SD_RSP54) << 8U) | (mem_read32(SD_RSP32) >> 24U))); /* [95:64] */ + emmc_little_to_big(p + 8U, ((mem_read32(SD_RSP32) << 8U) | (mem_read32(SD_RSP10) >> 24U))); /* [63:32] */ + emmc_little_to_big(p + 12U, (mem_read32(SD_RSP10) << 8U)); /* [31:0] */ + } else { + *response = mem_read32(SD_RSP10); /* [39:8] */ + } +} + +/** response check + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * param[in] *response Response from the card + * param[in] error_mask Errors to be checked (for R1/R1b response) + * return error code. + */ +static EMMC_ERROR_CODE emmc_response_check(const uint32_t *response, uint32_t error_mask) +{ + + HAL_MEMCARD_RESPONSE_TYPE response_type = (HAL_MEMCARD_RESPONSE_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) + & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK); + + if (response == NULL) + { + return EMMC_ERR_PARAM; + } + + if (response_type == HAL_MEMCARD_RESPONSE_NONE) + { + return EMMC_SUCCESS; + } + + /* response check */ + if (response_type <= HAL_MEMCARD_RESPONSE_R1b) + { + /* R1 or R1b */ + mmc_drv_obj.current_state = (EMMC_R1_STATE)((*response & EMMC_R1_STATE_MASK) >> EMMC_R1_STATE_SHIFT); + if ((*response & error_mask) != 0U) + { + return EMMC_ERR_CARD_STATUS_BIT; + } + } else if (response_type == HAL_MEMCARD_RESPONSE_R4) { + /* R4 */ + if ((*response & EMMC_R4_STATUS) != 0U) + { + return EMMC_ERR_CARD_STATUS_BIT; + } + } else { + ; /* nothing to do. other type does not have status bit */ + } + + return EMMC_SUCCESS; +} + +/** brief converts endian from little to big + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param[in,out] p destination buffer address. + * param[in] value convert data.(little) + * return None. + */ +static void emmc_little_to_big(uint8_t *p, uint32_t value) +{ + if (p == NULL) + { + return; + } + + p[0] = (uint8_t)(value >> 24U); + p[1] = (uint8_t)(value >> 16U); + p[2] = (uint8_t)(value >> 8U); + p[3] = (uint8_t)value; +} + +/** data transfer with DMA. + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * return error code. + */ +static void emmc_data_transfer_dma(void) +{ + mmc_drv_obj.during_dma_transfer = TRUE; + mmc_drv_obj.dma_error_flag = FALSE; + + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + + /* DMAC setting */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) + { + /* transfer complete interrupt enable when write to eMMC */ + mem_write32(DM_CM_INFO1_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE )); + /* When writing to eMMC, set only bit 17 to "0". */ + mem_write32(DM_CM_INFO2_MASK, ( DM_CM_INFO2_MASK_CLEAR | DM_CM_INFO2_CH0_ENABLE )); + /* BUFF --> FIFO */ + mem_write32(DM_CM_DTRAN_MODE, ( DM_CM_DTRAN_MODE_CH0 | DM_CM_DTRAN_MODE_BIT_WIDTH )); /* CH0(downstream), 64-bit width */ + } else { + /* transfer complete interrupt enable when read from eMMC */ + mem_write32(DM_CM_INFO1_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE )); + /* When reading from eMMC, set only bit 16 to "0". */ + mem_write32(DM_CM_INFO2_MASK, ( DM_CM_INFO2_MASK_CLEAR | DM_CM_INFO2_CH1_ENABLE )); + /* FIFO --> BUFF */ + mem_write32(DM_CM_DTRAN_MODE, ( DM_CM_DTRAN_MODE_CH1 | DM_CM_DTRAN_MODE_BIT_WIDTH )); /* CH1(upstream), 64-bit width */ + } + mem_write32(DM_DTRAN_ADDR, ( ( (uintptr_t)mmc_drv_obj.buff_address_virtual & DM_DTRAN_ADDR_WRITE_MASK ) )); /* Set address */ + + mem_write32(DM_CM_DTRAN_CTRL, DM_CM_DTRAN_CTRL_START); /* DMAC Start */ +} + +/** wait cmd-cmd 8cycle + * + * - Pre-conditions:
+ * + * - Post-conditions:
+ * . + * + * return None. + */ +static void emmc_WaitCmd2Cmd_8Cycle(void) +{ + uint32_t dataL, wait = 0U; + + dataL = mem_read32(SD_CLK_CTRL); + dataL &= 0x000000FFU; + + switch (dataL) + { + case 0xFFU: /* 1/1 10 us wait ( 1/200MHz)*8= 0.04 us(min) */ + wait = 10U; + break; + case 0x00U: /* 1/2 10 us wait ( 2/200MHz)*8= 0.08 us(min) */ + wait = 10U; + break; + case 0x01U: /* 1/4 10 us wait ( 4/200MHz)*8= 0.16 us(min) */ + wait = 10U; + break; + case 0x02U: /* 1/8 10 us wait ( 8/200MHz)*8= 0.32 us(min) */ + wait = 10U; + break; + case 0x04U: /* 1/16 10 us wait ( 16/200MHz)*8= 0.64 us(min) */ + wait = 10U; + break; + case 0x08U: /* 1/32 10 us wait ( 32/200MHz)*8= 1.28 us(min) */ + wait = 10U; + break; + case 0x10U: /* 1/64 10 us wait ( 64/200MHz)*8= 2.56 us(min) */ + wait = 10U; + break; + case 0x20U: /* 1/128 10 us wait (128/200MHz)*8= 5.12 us(min) */ + wait = 10U; + break; + case 0x40U: /* 1/256 20 us wait (256/200MHz)*8= 10.24 us(min) */ + wait = 20U; + break; + case 0x80U: /* 1/512 30 us wait (512/200MHz)*8= 20.48 us(min) */ + wait = 30U; + break; + default: + /* nop */ + break; + } + micro_wait(wait); + +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_init.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_init.c new file mode 100644 index 0000000..b1d5a71 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_init.c @@ -0,0 +1,399 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc initialize + ******************************************************************************/ +/****************************************************************************** + * @file emmc_init.c + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 22.03.2022 0.02 Removed CPG setting + * Added Function End comment + * Added header file inclusion + * : 24.10.2022 0.03 Add CPG setting to support HS200/400 + * : 31.10.2022 0.04 License notation change. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "mem_io.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +#undef DUMP_EMMC_REGISTERS +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ +st_mmc_base mmc_drv_obj; +#define CX_IPL_EMMC_DATA (0x41DFF000UL) +#define CX_IPL_CSD_DATA (CX_IPL_EMMC_DATA) +#define CX_IPL_CID_DATA (CX_IPL_CSD_DATA + EMMC_MAX_CSD_LENGTH) +#define CX_IPL_EXT_CSD_DATA (CX_IPL_CID_DATA + EMMC_MAX_CID_LENGTH) +volatile uint8_t *default_csd_data = (volatile uint8_t *)CX_IPL_CSD_DATA; +volatile uint8_t *default_cid_data = (volatile uint8_t *)CX_IPL_CID_DATA; +volatile uint8_t *default_ext_csd_data = (volatile uint8_t *)CX_IPL_EXT_CSD_DATA; + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static void emmc_drv_init(void); +static EMMC_ERROR_CODE emmc_dev_init(void); +static EMMC_ERROR_CODE emmc_dev_finalize(void); +static void emmc_memset(void *buff, uint8_t data, uint32_t cnt); +static EMMC_ERROR_CODE emmc_reset_controller(void); +static void emmc_driver_config(void); +static void emmc_set_data_timeout(uint32_t data_timeout); + +/* ********************************* CODE ********************************** */ + +#if defined(DUMP_EMMC_REGISTERS) && (LOG_LEVEL >= LOG_NOTICE) +static void dump_buf(const uint8_t *buf, int size) +{ + int i; + for (i = 0; i < size; i++) + { + if ((i % 16) == 0) + { + log_printf("\n%x: ", i); + } + log_printf("%b ", (uint8_t)buf[i]); + } + log_printf("\n"); +} +#endif + +void dump_mmc_drv_obj(void) +{ +#if defined(DUMP_EMMC_REGISTERS) && (LOG_LEVEL >= LOG_NOTICE) + NOTICE("[%s:%d] size of mmc_drv_obj %d\n", __func__, __LINE__, sizeof(mmc_drv_obj)); + NOTICE("CSD data:"); + dump_buf(mmc_drv_obj.csd_data, sizeof(mmc_drv_obj.csd_data)); + NOTICE("CID data:"); + dump_buf(mmc_drv_obj.cid_data, sizeof(mmc_drv_obj.cid_data)); + NOTICE("ext CSD data:"); + dump_buf(mmc_drv_obj.ext_csd_data, sizeof(mmc_drv_obj.ext_csd_data)); +#endif +} + +void import_mmc_drv_obj(void) +{ + /* Fill mmc_drv_obj with default values */ + emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base)); + + for(int i=0; i < EMMC_MAX_CID_LENGTH; i++) + { + mmc_drv_obj.cid_data[i] = default_cid_data[i]; + } + for(int i=0; i < EMMC_MAX_CSD_LENGTH; i++) + { + mmc_drv_obj.csd_data[i] = default_csd_data[i]; + } + for(int i=0; i < EMMC_MAX_EXT_CSD_LENGTH; i++) + { + mmc_drv_obj.ext_csd_data[i] = default_ext_csd_data[i]; + } + dump_mmc_drv_obj(); + + mmc_drv_obj.card_power_enable = TRUE; + mmc_drv_obj.clock_enable = TRUE; + mmc_drv_obj.initialize = TRUE; + mmc_drv_obj.mount = TRUE; + mmc_drv_obj.selected = TRUE; +} + +void export_mmc_drv_obj(void) +{ + for(int i=0; i < EMMC_MAX_CID_LENGTH; i++) + { + *((volatile uint8_t *)&default_cid_data[i]) = mmc_drv_obj.cid_data[i]; + } + for(int i=0; i < EMMC_MAX_CSD_LENGTH; i++) + { + *((volatile uint8_t *)&default_csd_data[i]) = mmc_drv_obj.csd_data[i]; + } + for(int i=0; i < EMMC_MAX_EXT_CSD_LENGTH; i++) + { + *((volatile uint8_t *)&default_ext_csd_data[i]) = mmc_drv_obj.ext_csd_data[i]; + } + + dump_mmc_drv_obj(); +} + +/** brief eMMC initialize. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR error from interrupt API. + */ +EMMC_ERROR_CODE emmc_init(void) +{ + /* initialize H/W */ + (void)emmc_reset_controller(); + + /* Configuration */ + emmc_driver_config(); + + return EMMC_SUCCESS; +} + +/** terminate emmc driver + * + * EMMC H/W and S/W resource is released. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * return None. + */ +EMMC_ERROR_CODE emmc_terminate(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* H/W finalize */ + result = emmc_dev_finalize(); + + /* driver finalize */ + emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base)); /* clear global variable */ + + return result; +} + +/** Function executes full reset to MMC host controller without taking power out from the memory card. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * Reset MMC host controller without taking power out from the memory card. + * Memory card preserves its state. + * + * return None + */ +static EMMC_ERROR_CODE emmc_reset_controller(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* initialize mmc driver */ + emmc_drv_init(); + + mmc_drv_obj.base_address = MMC0_SD_BASE; + + /* initialize H/W */ + result = emmc_dev_init(); + + mmc_drv_obj.initialize = TRUE; + + return result; + +} + +/** Configuration eMMC driver + * + * - Pre-conditions:
+ * initialized eMMC driver. + * - Post-conditions:
+ * . + * + * return None + */ +static void emmc_driver_config(void) +{ + /* Read/Write data timeout */ + emmc_set_data_timeout(EMMC_RW_DATA_TIMEOUT); +} + +/** Sets data timeout + * + * Sets the data timeout value for read and write operations. + * + * - Pre-conditions:
+ * initialized eMMC driver. + * + * - Post-conditions:
+ * After this function is called, the timeout value is set according to argument. + * + * param[in] time_out The desired timeout value in milliseconds. + * return None + */ +static void emmc_set_data_timeout(uint32_t data_timeout) +{ + mmc_drv_obj.data_timeout = data_timeout; +} + +/** eMMC driver initialize. (software) + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * return None. + */ +static void emmc_drv_init(void) +{ + /* initialize */ + emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base)); + + mmc_drv_obj.data_timeout = EMMC_RW_DATA_TIMEOUT; + + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; +} + +/** eMMC driver initialize. (H/W) + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * return None. + */ +static EMMC_ERROR_CODE emmc_dev_init(void) +{ + /* InitSdCkcr */ + mem_write32(CPG_CPGWPR, ~(0x00000001U)); + mem_write32(CPG_SD0CKCR, 0x00000001U); /* SD0H-Clock=800MHz(Supply), SD0=200MHz(Supply) */ + + /* MMCIF initialize */ + mem_write32(SD_INFO1, 0x00000000U); /* all interrupt clear */ + mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* all interrupt clear */ + mem_write32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ + + mem_write32(HOST_MODE, 0x00000000U); /* SD_BUF access width = 64-bit */ + mem_write32(SD_OPTION, 0x0000C0EEU); /* Bus width = 1bit, timeout=MAX */ + mem_write32(SD_CLK_CTRL, 0x00000000U); /* Automatic Control=Disable, Clock Output=Disable */ + + return EMMC_SUCCESS; +} + +/** EMMC H/W finalize + * + * EMMC Host and Card hardware resource is released. + * + * - Pre-conditions:
+ * . + * + * - Post-conditions:
+ * . + * return None. + */ +static EMMC_ERROR_CODE emmc_dev_finalize(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* MMC power off + * the power supply of eMMC device is always turning on. + * RST_n : Hi --> Low level. + */ + result = emmc_memcard_power(FALSE); + + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, 0x00000800U); + mem_write32(DM_CM_INFO1, 0x00000000U); + mem_write32(DM_CM_INFO2, 0x00000000U); + + mem_write32(SD_CLK_CTRL, 0x00000020U); + mem_write32(CC_EXT_MODE, 0x00000000U); + mem_write32(SD_STOP, 0x00000000U); + mem_write32(SD_SECCNT, 0x00000000U); + mem_write32(DM_CM_DTRAN_MODE, 0x00000000U); + mem_write32(DM_DTRAN_ADDR, 0x00000000U); + mem_write32(SD_OPTION, 0x00000000U); + mem_write32(DM_CM_DTRAN_CTRL, 0x00000000U); + + return result; +} + +/** Set power to memory card IF. + * This function control Vcc and Vccq and RST_n. + * + * attention + * CPU cannot control Vcc&Vccq. + * The power supply of eMMC device is always turning on. + * + * param[in] mode TRUE = power on, FALSE = power off + * + * retval EMMC_SUCCESS powering succeeded + * retval EMMC_ERR_CARD_POWER powering failed + */ +EMMC_ERROR_CODE emmc_memcard_power(uint32_t mode) +{ + if (mode == TRUE) + { + /* power on (Vcc&Vccq is always power on) */ + mmc_drv_obj.card_power_enable = TRUE; + } else { + /* power off (Vcc&Vccq is always power on) */ + mmc_drv_obj.card_power_enable = FALSE; + mmc_drv_obj.mount = FALSE; + mmc_drv_obj.selected = FALSE; + } + + return EMMC_SUCCESS; +} + +/** memset(). no use C standard library. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param[in,out] buff pointer to buffer (virtual) + * param[in] data fill data. + * param[in] cnt fill size (number of bytes) + * return None. + */ +static void emmc_memset(void *buff, uint8_t data, uint32_t cnt) +{ + uint8_t *tmp = NULL; + tmp = (uint8_t *)buff; + + if (buff == NULL) + { + return; + } + + while (cnt > 0U) + { + *tmp = data; + tmp++; + cnt--; + } +} + +/* ******************************** END ************************************ */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_interrupt.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_interrupt.c new file mode 100644 index 0000000..48e3beb --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_interrupt.c @@ -0,0 +1,239 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc interrupt + ******************************************************************************/ +/****************************************************************************** + * @file emmc_interrupt.c + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 16.06.2022 0.02 Change log output + * : 31.10.2022 0.03 License notation change. + * : 07.06.2024 0.04 Modify the transfer end bit of DMAC channel. + *****************************************************************************/ + +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "log.h" +#include "mem_io.h" +#include +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual); + + +/* ********************************* CODE ********************************** */ + + + +/** emmc driver interrupt service routine. + * + * - Pre-conditions:
+ * Must be block emmc driver state machine. + * - Post-conditions:
+ * unblocking emmc driver state machine. + * + * retval INT_SUCCESS + */ +uint32_t emmc_interrupt(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* SD_INFO */ + mmc_drv_obj.error_info.info1 = mem_read32(SD_INFO1); + mmc_drv_obj.error_info.info2 = mem_read32(SD_INFO2); + + /* SD_INFO EVENT */ + mmc_drv_obj.int_event1 = mmc_drv_obj.error_info.info1 & mem_read32(SD_INFO1_MASK); + mmc_drv_obj.int_event2 = mmc_drv_obj.error_info.info2 & mem_read32(SD_INFO2_MASK); + + /* ERR_STS */ + mmc_drv_obj.error_info.status1 = mem_read32(SD_ERR_STS1); + mmc_drv_obj.error_info.status2 = mem_read32(SD_ERR_STS2); + + /* DM_CM_INFO */ + mmc_drv_obj.error_info.dm_info1 = mem_read32(DM_CM_INFO1); + mmc_drv_obj.error_info.dm_info2 = mem_read32(DM_CM_INFO2); + + /* DM_CM_INFO EVENT */ + mmc_drv_obj.dm_event1 = mmc_drv_obj.error_info.dm_info1 & mem_read32(DM_CM_INFO1_MASK); + mmc_drv_obj.dm_event2 = mmc_drv_obj.error_info.dm_info2 & mem_read32(DM_CM_INFO2_MASK); + + /* ERR SD_INFO2 */ + if ((SD_INFO2_ALL_ERR & mmc_drv_obj.int_event2) != 0U) + { + mem_write32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */ + mem_write32(SD_INFO1, 0x00000000U); /* interrupt clear */ + mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } + + /* PIO Transfer */ + /* BWE/BRE */ + else if ((( SD_INFO2_BWE | SD_INFO2_BRE) & mmc_drv_obj.int_event2) != 0U) { + /* BWE */ + if (( SD_INFO2_BWE & mmc_drv_obj.int_event2) != 0U) + { + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BWE)); /* interrupt clear */ + } + /* BRE */ + else { + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BRE)); /* interrupt clear */ + } + + result = emmc_trans_sector((uint32_t *)mmc_drv_obj.buff_address_virtual); /* sector R/W */ + mmc_drv_obj.buff_address_virtual += EMMC_BLOCK_LENGTH; + mmc_drv_obj.remain_size -= EMMC_BLOCK_LENGTH; + + if (result != EMMC_SUCCESS) + { + /* data transfer error */ + ERROR("%s:0x%x\n",__func__, result); + + /* Panic */ + mem_write32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */ + mem_write32(SD_INFO1, 0x00000000U); /* interrupt clear */ + mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */ + mmc_drv_obj.force_terminate = TRUE; + } else { + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; + } + + /* DMA_TRANSFER */ + /* DM_CM_INFO1: DMA-ch0 transfer complete or error occured */ + else if ((DM_CM_INFO_DTRANEND0 & mmc_drv_obj.dm_event1) != 0U) { + mem_write32(DM_CM_INFO1, 0x00000000U); + mem_write32(DM_CM_INFO2, 0x00000000U); + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BWE)); /* interrupt clear */ + /* DM_CM_INFO2: DMA-ch0 error occured */ + if (( DM_CM_INFO2_DTRANEND0 & mmc_drv_obj.dm_event2) != 0U) + { + mmc_drv_obj.dma_error_flag = TRUE; + } else { + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; /* wait next interrupt */ + } + /* DM_CM_INFO1: DMA-ch1 transfer complete or error occured */ + else if ((DM_CM_INFO_DTRANEND1 & mmc_drv_obj.dm_event1) != 0U) { + mem_write32(DM_CM_INFO1, 0x00000000U); + mem_write32(DM_CM_INFO2, 0x00000000U); + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BRE)); /* interrupt clear */ + /* DM_CM_INFO2: DMA-ch1 error occured */ + if (( DM_CM_INFO2_DTRANEND1 & mmc_drv_obj.dm_event2) != 0U) + { + mmc_drv_obj.dma_error_flag = TRUE; + } else { + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; /* wait next interrupt */ + } + + /* Response end */ + else if ((SD_INFO1_INFO0 & mmc_drv_obj.int_event1) != 0U) { + mem_write32(SD_INFO1, (mem_read32(SD_INFO1) & ~SD_INFO1_INFO0)); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } + /* Access end */ + else if ((SD_INFO1_INFO2 & mmc_drv_obj.int_event1) != 0U) { + mem_write32(SD_INFO1, (mem_read32(SD_INFO1) & ~SD_INFO1_INFO2)); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } else { + /* nothing to do. */ + } + + return 0U; +} + +/** Data transfer function with PIO (Single sector). + * + * - Pre-conditions:
+ * Called from interrupt service. + * - Post-conditions:
+ * . + * + * param[in,out] buff_address_virtual Dest/Src buffer address(virtual). + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_PARAM parameter error. + * retval EMMC_ERR_STATE state error. + */ +static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual) +{ + uint32_t length, i; + uint64_t *bufPtrLL; + + if (buff_address_virtual == NULL) + { + return EMMC_ERR_PARAM; + } + + if ((mmc_drv_obj.during_transfer != TRUE) || (mmc_drv_obj.remain_size == 0U)) + { + return EMMC_ERR_STATE; + } + + bufPtrLL = (uint64_t*)buff_address_virtual; + length = mmc_drv_obj.remain_size; + + /* data transefer */ + for (i = 0U; i < (length >> 3U); i++) + { + /* Write */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) + { + mem_write64(SD_BUF0, *bufPtrLL); /* buffer --> FIFO */ + } + /* Read */ + else { + *bufPtrLL = mem_read64(SD_BUF0); /* FIFO --> buffer */ + } + bufPtrLL++; + } + + return EMMC_SUCCESS; +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_mount.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_mount.c new file mode 100644 index 0000000..3784b82 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_mount.c @@ -0,0 +1,1592 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc mount + ******************************************************************************/ +/****************************************************************************** + * @file emmc_mount.c + * - Version : 0.08 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 17.02.2022 0.02 V4H software restrictions + * : 18.03.2022 0.03 Unrestricted V4H software + * : 16.06.2022 0.04 Change log output + * : 24.10.2022 0.05 Support HS200/400 + * : 31.10.2022 0.06 License notation change. + * : 08.12.2022 0.07 Support build option of EMMC_TRANS_MODE + * and add cmd21 function + * : 21.08.2023 0.08 Add support for V4M. +*****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include +#include "timer.h" +#include "log.h" + +#define BIT0 (0x0000000000000001U) +#define BIT1 (0x0000000000000002U) +#define BIT2 (0x0000000000000004U) +#define BIT3 (0x0000000000000008U) +#define BIT4 (0x0000000000000010U) +#define BIT5 (0x0000000000000020U) +#define BIT6 (0x0000000000000040U) +#define BIT8 (0x0000000000000100U) +#define BIT2_0 (BIT2|BIT1|BIT0) +#define BIT3_0 (BIT3|BIT2|BIT1|BIT0) +#define BIT6_0 (BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0) +#define BIT23_16 (0x0000000000FF0000U) + +#define SMPCMP_SUCCESS (0x0U) +#define FAIL (0x0U) +#define SUCCESS (0x1U) +#define FIRST (0x1U) + +#define MMC_CMD21 (0x00001C15U) + +/* for S4 */ +#define PFC_DRVCTRL1_GP1_DM0_MMC_MASK (0x77770000U) +#define PFC_DRVCTRL1_GP1_DM0_MMC_VALUE (0x66660000U) +#define PFC_DRVCTRL2_GP1_DM0_MMC_MASK (0x07777777U) +#define PFC_DRVCTRL2_GP1_DM0_MMC_VALUE (0x06666666U) + +/* for V4H */ +#define PFC_DRVCTRL0_GP3_DM0_MMC_MASK (0x77777777U) +#define PFC_DRVCTRL0_GP3_DM0_MMC_VALUE (0x66666666U) +#define PFC_DRVCTRL1_GP3_DM0_MMC_MASK (0x00000777U) +#define PFC_DRVCTRL1_GP3_DM0_MMC_VALUE (0x00000666U) + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static EMMC_ERROR_CODE emmc_clock_ctrl(uint32_t mode); +static EMMC_ERROR_CODE emmc_card_init(void); +static EMMC_ERROR_CODE emmc_mode_select(uint32_t *speed_mode); +static EMMC_ERROR_CODE emmc_bus_width(uint32_t width); +static EMMC_ERROR_CODE emmc_power_select(void); +static uint32_t emmc_set_timeout_register_value(uint32_t freq); +static void set_sd_clk(uint32_t clkDiv); +static uint32_t emmc_calc_tran_speed(void); +static EMMC_ERROR_CODE emmc_scc_tuning(void); +static uint8_t emmc_scc_tuningmain(uint32_t tapset); +static EMMC_ERROR_CODE emmc_exec_cmd21(void); +static EMMC_ERROR_CODE emmc_tapset_position_find(uint32_t tapsetNum, const uint8_t result_tuning[], uint32_t *tapset); +static EMMC_ERROR_CODE emmc_data_read(void *buf); +static EMMC_ERROR_CODE emmc_wait_readbuf_enable(void); +static EMMC_ERROR_CODE emmc_wait_readbuf_end(void); +static void pfc_reg_modify_write(uintptr_t addr, uint32_t mask, uint32_t data); +/* ********************************* CODE ********************************** */ + +/** eMMC mount operation. + * + * Sequence is the following. + * 1) Bus initialization (emmc_card_init()) + * 2) Changing the data bus width. (emmc_bus_width()) + * 3) Selecting high speed or HS200 or HS400 mode refering to CARD_TYPE[196]. (emmc_mode_select()) + * 4) Selecting power class. (emmc_power_select()) + * 5) If selected mode is HS200 or HS400, perform timing tuning. (emmc_scc_tuning()) + * 6) If selected mode is HS400, switching to HS400 mode. + * + * - Pre-conditions:
+ * eMMC driver is initialized. The power supply of MMC IF must be turning on. + * - Post-conditions:
+ * MMC card state changes to transfer state. + * + * return eMMC error code. + */ +EMMC_ERROR_CODE emmc_mount(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t speed_mode; + + /* Frequency initialization setting */ + mmc_drv_obj.set_freq = MMC_400KHZ; + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || (mmc_drv_obj.card_power_enable != TRUE) + || ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U)) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* initialize card (IDLE state --> Transfer state) */ + result = emmc_card_init(); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + (void)emmc_clock_ctrl(FALSE); + return result; + } + + /* Changing the data bus width */ + result = emmc_bus_width(8U); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + (void)emmc_clock_ctrl(FALSE); + return result; + } + + /* Selecting Power class */ + result = emmc_power_select(); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + (void)emmc_clock_ctrl(FALSE); + return result; + } + + /* Switching HS400 or HS200 or High speed mode */ + result = emmc_mode_select(&speed_mode); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + (void)emmc_clock_ctrl(FALSE); + return result; + } + + switch (speed_mode) + { + case TIMING_HS400: + NOTICE("eMMC Transfer mode: HS400\n"); + break; + case TIMING_HS200: + NOTICE("eMMC Transfer mode: HS200\n"); + break; + case TIMING_HIGH_SPEED: + NOTICE("eMMC Transfer mode: High Speed\n"); + break; + default: + NOTICE("eMMC Transfer mode: No High Speed\n"); + break; + } + + /* Tuning for HS200 and HS400 */ + if ((speed_mode==TIMING_HS200) || (speed_mode==TIMING_HS400)) + { + /* EnableSccHs200Mmc */ + mem_write32(SCC_DTCNTL, 0x00080001U); /* TAPNUM=8, TAPEN=1 */ + mem_write32(SCC_CKSEL, 0x00000001U); /* DTSEL=1 */ + mem_write32(SCC_TMPPORT2, 0x00000000U); + + /* Timing Tuning for HS200/HS400 */ + result = emmc_scc_tuning(); + if(result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + } else { + /* DisableSccMmc */ + mem_write32(SCC_DTCNTL, 0x00080000U); /* TAPNUM=8, TAPEN=0 */ + mem_write32(SCC_CKSEL, 0x00000000U); /* DTSEL=0 */ + mem_write32(SCC_TMPPORT2, 0x00000000U); + } + + /* Setting for HS400 */ + if (speed_mode==TIMING_HS400) + { + /*Set the SoC's driver strength for HS400 mode */ +#if (RCAR_LSI == RCAR_S4) + /* DRVCTRL1_1[30:28][26:24][22:20][18:16]/ = D2, D1, D0, CLK */ + pfc_reg_modify_write(PFC_DRVCTRL1_GP1_DM0, PFC_DRVCTRL1_GP1_DM0_MMC_MASK, PFC_DRVCTRL1_GP1_DM0_MMC_VALUE); + /* DRVCTRL2_1[26:24][22:20][18:16][14:12][10:8][6:4][2:1]/ = CMD, D7, DS, D6, D4, D5, D3 */ + pfc_reg_modify_write(PFC_DRVCTRL2_GP1_DM0, PFC_DRVCTRL2_GP1_DM0_MMC_MASK, PFC_DRVCTRL2_GP1_DM0_MMC_VALUE); +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + /* DRVCTRL0_3[30:28][26:24][22:20][18:16][14:12][10:8][6:4][2:1]/ = D4, D5, D3, DS, CLK, D2, D0, D1 */ + pfc_reg_modify_write(PFC_DRVCTRL0_GP3_DM0, PFC_DRVCTRL0_GP3_DM0_MMC_MASK, PFC_DRVCTRL0_GP3_DM0_MMC_VALUE); + /* DRVCTRL1_3[10:8][6:4][2:0] = CMD, D6, D7 */ + pfc_reg_modify_write(PFC_DRVCTRL1_GP3_DM0, PFC_DRVCTRL1_GP3_DM0_MMC_MASK, PFC_DRVCTRL1_GP3_DM0_MMC_VALUE); +#endif + + /* EnableHs400Mmc*/ + mem_write32(SDIF_MODE, 0x00000001U); + + /* Set HS_TIMING to 0x01 (High Speed) */ + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* Host changes frequency to <= 52MHz */ + mmc_drv_obj.set_freq = MMC_52MHZ; + result = emmc_set_request_mmc_clock(&mmc_drv_obj.set_freq); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* Set the bus width to DDR 8bit (CMD6) */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_BUS_WIDTH_8_DDR); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* Set the bus width to 8bit for SD card access control option register */ + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_WIDTH|SD_OPTION_WIDTH8)) | SD_OPTION_WIDTH8 )); + + /* Set HS_TIMING to 0x03 (HS400) */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS400); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK_WITHOUT_CRC, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n", __func__); + panic; + } + + /* InitSdCkcrForHS400 */ + mem_write32(CPG_CPGWPR, ~(0x00000001U)); + mem_write32(CPG_SD0CKCR, 0x00000001U); /* SD0H-Clock=800MHz(Supply), SD0=200MHz(Supply) */ + + /* Host changes frequency to 200MHz */ + mmc_drv_obj.max_freq = HS400_200MHZ; + mmc_drv_obj.set_freq = mmc_drv_obj.max_freq; + result = emmc_set_request_mmc_clock(&mmc_drv_obj.set_freq); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* EnableSccHs400Mmc */ + mem_write32(SCC_DTCNTL, 0x00040001U); /* TAPNUM=4, TAPEN=1 */ + mem_write32(SCC_CKSEL, 0x00000001U); /* DTSEL=1 */ + mem_write32(SCC_TMPPORT2, 0x80000010U); /* HS400EN=1, HS400OSEL=1 (use SDxH clock) */ + } + + /* mount complete */ + mmc_drv_obj.mount = TRUE; + + return EMMC_SUCCESS; +} + +/** Bus initialization function + * + * - Pre-conditions:
+ * eMMC driver is initialized. The power supply of MMC IF must be turning on. + * - Post-conditions:
+ * MMC card state changes to transfer state. + * + * retval EMMC_SUCCESS successful. + * return eMMC error code. + * attention upper layer must be check pre-conditions. + */ +static EMMC_ERROR_CODE emmc_card_init(void) +{ + int32_t retry; + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t resultCalc = 0U; + mmc_drv_obj.set_freq = MMC_400KHZ; /* 390KHz */ + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || (mmc_drv_obj.card_power_enable != TRUE) + || ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U)) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* clock on (force change) */ + mmc_drv_obj.current_freq = 0U; + mmc_drv_obj.max_freq = MMC_20MHZ; /* MMC_20MHZ = MMC_12MHZ = 12.187MHz */ + result = emmc_set_request_mmc_clock(&mmc_drv_obj.set_freq); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return EMMC_ERR; + } + + micro_wait(1000U); /* wait 1ms */ + + /* CMD0, arg=0x00000000 */ + result = emmc_send_idle_cmd (0x00000000U); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + micro_wait(200U); /* wait 74clock 390kHz(189.74us)*/ + + /* CMD1 */ + emmc_make_nontrans_cmd(CMD1_SEND_OP_COND, EMMC_HOST_OCR_VALUE); + for (retry = 300; retry > 0; retry--) + { + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + if ((mmc_drv_obj.r3_ocr & EMMC_OCR_STATUS_BIT) != 0U) + { + break; /* card is ready. exit loop */ + } + micro_wait(1000U); /* wait 1ms */ + } + + if (retry == 0) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_TIMEOUT); + return EMMC_ERR_TIMEOUT; + } + + if ((mmc_drv_obj.r3_ocr & EMMC_OCR_ACCESS_MODE_MASK) != EMMC_OCR_ACCESS_MODE_SECT) + { + /* unknown value */ + ERROR("%s:0x%x\n",__func__,EMMC_ERR); + return EMMC_ERR; + } + + /* CMD2 */ + emmc_make_nontrans_cmd(CMD2_ALL_SEND_CID_MMC, 0x00000000U); + mmc_drv_obj.response = (uint32_t *)(&mmc_drv_obj.cid_data[0U]); /* use CID special buffer */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* CMD3 */ + emmc_make_nontrans_cmd(CMD3_SET_RELATIVE_ADDR, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* CMD9 : CSD */ + emmc_make_nontrans_cmd(CMD9_SEND_CSD, EMMC_RCA << 16U); + mmc_drv_obj.response = (uint32_t *)(&mmc_drv_obj.csd_data[0U]); /* use CSD special buffer */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* card version check */ + if (EMMC_CSD_SPEC_VARS() < 4U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_ILLEGAL_CARD); + return EMMC_ERR_ILLEGAL_CARD; + } + + /* CMD7 (select card) */ + emmc_make_nontrans_cmd(CMD7_SELECT_CARD, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + mmc_drv_obj.selected = TRUE; + + /* card speed check */ + resultCalc = emmc_calc_tran_speed(); /* Card spec is calculated from TRAN_SPEED(CSD). */ + if (resultCalc == 0U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_ILLEGAL_CARD); + return EMMC_ERR_ILLEGAL_CARD; + } + mmc_drv_obj.max_freq = mmc_drv_obj.set_freq; /* max frequency (card spec) */ + + result = emmc_set_request_mmc_clock(&mmc_drv_obj.set_freq); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return EMMC_ERR; + } + + /* set read/write timeout */ + mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(mmc_drv_obj.set_freq); + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) | mmc_drv_obj.data_timeout)); + + /* SET_BLOCKLEN:512byte */ + /* CMD16 */ + emmc_make_nontrans_cmd(CMD16_SET_BLOCKLEN, EMMC_BLOCK_LENGTH); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* Transfer Data Length */ + mem_write32(SD_SIZE, EMMC_BLOCK_LENGTH); + + /* CMD8 : EXT_CSD */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0U]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + /* CMD12 is not send. + * If BUS initialization is failed, user must be execute Bus initialization again. + * Bus initialization is start CMD0(soft reset command). + */ + ERROR("%s\n",__func__); + return result; + } + + return EMMC_SUCCESS; +} + +/** Switching to high-speed or HS200/HS400 mode + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * EXT_CSD data must be stored in mmc_drv_obj.ext_csd_data[]. + * + * - Post-conditions:
+ * Change the clock frequency to 26MHz or 52MHz or 200MHz. + * + * retval EMMC_SUCCESS successful or aleady switching. + * retval EMMC_ERR_STATE state error. + * retval EMMC_ERR unknown error. + * return emmc error code. + */ +static EMMC_ERROR_CODE emmc_mode_select(uint32_t *speed_mode) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + +#if ((EMMC_TRANS_MODE == HS400) || (EMMC_TRANS_MODE == HS200) || (EMMC_TRANS_MODE == HIGH_SPEED)) + uint8_t cardType; + cardType = (uint8_t)mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_CARD_TYPE]; +#endif + + /* state check */ + if (mmc_drv_obj.selected != TRUE) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + panic; + } + + #if (EMMC_TRANS_MODE == HS400) + if ((cardType & EMMC_EXT_CSD_CARD_TYPE_400MHZ) != 0U) + { + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS200); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + panic; + } + + *speed_mode = TIMING_HS400; + mmc_drv_obj.max_freq = MMC_200MHZ; + } else { + ERROR("HS400 is not supported."); + panic; + } + #elif (EMMC_TRANS_MODE == HS200) + if ((cardType & EMMC_EXT_CSD_CARD_TYPE_200MHZ) != 0U) + { + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS200); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + panic; + } + + *speed_mode = TIMING_HS200; + mmc_drv_obj.max_freq = MMC_200MHZ; + } else { + ERROR("HS200 is not supported."); + panic; + } + #elif (EMMC_TRANS_MODE == HIGH_SPEED) + if ((cardType & EMMC_EXT_CSD_CARD_TYPE_52MHZ) != 0U) + { + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + panic; + } + + *speed_mode = TIMING_HIGH_SPEED; + mmc_drv_obj.max_freq = MMC_52MHZ; + } else if ((cardType & EMMC_EXT_CSD_CARD_TYPE_26MHZ) != 0U) { + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + panic; + } + + *speed_mode = TIMING_HIGH_SPEED; + mmc_drv_obj.max_freq = MMC_26MHZ; + } else { + ERROR("High Speed is not supported."); + panic; + } + #elif (EMMC_TRANS_MODE == NO_HIGH_SPEED) + *speed_mode = TIMING_HIGH_SPEED_OFF; + mmc_drv_obj.max_freq = MMC_20MHZ; + #endif /* EMMC_TRANS_MODE == HS400 */ + +#if ((EMMC_TRANS_MODE == HS400) || (EMMC_TRANS_MODE == HS200)) + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK_WITHOUT_CRC, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + panic; + } +#endif /* ((EMMC_TRANS_MODE == HS400) || (EMMC_TRANS_MODE == HS200)) */ + + /* set mmc clock */ + mmc_drv_obj.set_freq = mmc_drv_obj.max_freq; + result = emmc_set_request_mmc_clock(&mmc_drv_obj.set_freq); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + panic; + } + + /* set read/write timeout */ + mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(mmc_drv_obj.set_freq); + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) | mmc_drv_obj.data_timeout)); + + return result; +} + +/** Changing the data bus width + * + * if chinging the data bus width failed, card is reset by CMD0. + * Please do Bus initialization over again. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * + * - Post-conditions:
+ * Change the data bus width to 8bit or 4bit. + * mmc_drv_obj.ext_csd_data is updated. + * + * param[in] width bus width (8 or 4) + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_PARAM parameter error + * retval EMMC_ERR_STATE state error. + * + */ +static EMMC_ERROR_CODE emmc_bus_width(uint32_t width) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* parameter check */ + if ((width != 8U) && (width != 4U) && (width != 1U)) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.selected != TRUE) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH)(width >> 2U); /* 2 = 8bit, 1 = 4bit, 0 =1bit */ + + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, ( EMMC_SWITCH_BUS_WIDTH_1 | ((uint32_t)(mmc_drv_obj.bus_width) << 8U))); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + /* occurred error */ + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; + goto EXIT; + } + + switch (mmc_drv_obj.bus_width) + { + case HAL_MEMCARD_DATA_WIDTH_1_BIT: + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_WIDTH|SD_OPTION_WIDTH8)) | SD_OPTION_WIDTH )); + break; + case HAL_MEMCARD_DATA_WIDTH_4_BIT: + mem_write32(SD_OPTION, (mem_read32(SD_OPTION) & ~(SD_OPTION_WIDTH|SD_OPTION_WIDTH8))); + break; + case HAL_MEMCARD_DATA_WIDTH_8_BIT: + default: + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_WIDTH|SD_OPTION_WIDTH8)) | SD_OPTION_WIDTH8 )); + break; + } + + /* CMD8 : EXT_CSD */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0U]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + goto EXIT; + } + + return EMMC_SUCCESS; + +EXIT: + ERROR("%s:0x%x\n",__func__,result); + return result; +} + +/** Switching to power class according to speed mode + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * EXT_CSD data must be stored in mmc_drv_obj.ext_csd_data[]. + * + * - Post-conditions:
+ * Change the power class according to each speed mode. + * + * param[in] speed mode (TIMING_HIGH_SPEED_MODE(0x0) or TIMING_HIGH_SPEED(0x1) or TIMING_HS200(0x2) or TIMING_HS400(0x3)) + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_PARAM parameter error + * retval EMMC_ERR_STATE state error. + * + */ +static EMMC_ERROR_CODE emmc_power_select(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t powerClass; + + powerClass = (uint8_t)mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_PWR_CL_DDR_200_360]; /* 200MHz, DDR, VCC=3.6V */ + + /* read value [7:4]=8bit bus, [3:0]=4bit bus */ + powerClass = (powerClass & 0xF0U) >> 4U; /* 8bit */ + powerClass = (EXTCSD_ACCESS_BYTE|POW_CLASS_ADD|(powerClass << 8U)); + + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, powerClass); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + } + + return result; +} + +/** select access partition + * + * This function write the EXT_CSD register(PARTITION_ACCESS: PARTITION_CONFIG[2:0]). + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * selected partition can access. + * + * param[in] id user selects partitions to access. + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_STATE state error. + * retval EMMC_ERR_PARAM parameter error. + * return emmc error code. + */ +EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t partition; + uint32_t partition_config; + + /* state check */ + if (mmc_drv_obj.mount != TRUE) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* id has PARTITION_ACCESS(Bit[2:0]) */ + if ((uint32_t)((uint32_t)id & ~(uint32_t)PARTITION_ID_MASK) != 0U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* EXT_CSD[179] value */ + partition_config = (uint32_t)mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_PARTITION_CONFIG]; + if ((partition_config & (uint32_t)PARTITION_ID_MASK) == (uint32_t)id) + { + result = EMMC_SUCCESS; + } else { + + partition_config = ((partition_config & (~(uint32_t)PARTITION_ID_MASK)) | (uint32_t)id); + partition = EMMC_SWITCH_PARTITION_CONFIG | (partition_config << 8U); + + result = emmc_set_ext_csd(partition); + } + + return result; +} + +/** set EXT CSD data + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * mmc_drv_obj.ext_csd_data[] is updated. + * + * param[in] arg argument of CMD6 + * return emmc error code. + */ +EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, arg); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + + /* CMD8 : EXT_CSD */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0U]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + return EMMC_SUCCESS; +} + +/** set request MMC clock frequency. + * + * Function returns EMMC_SUCCESS if clock is already running in the desired frequency. + * EMMC_ERR is returned if the HW doesn't support requested clock frequency. + * If matching frequence cannot be set the closest frequence below should be selected. + * For example if 50MHz is requested, but HW supports only 48MHz then 48MHz should be returned in the freq parameter. + * + * - Pre-conditions:
+ * initialized eMMC driver with emmc_init(). + * Memory card and MMCSDIO host controller needs to be powered up beforehand. + * + * - Post-conditions:
+ * Desired clock frequency is set to memory card IF. + * + * param[in] freq frequency [Hz] + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_STATE state error. + * retval EMMC_ERR busy + */ +EMMC_ERROR_CODE emmc_set_request_mmc_clock(const uint32_t *freq) +{ + /* parameter check */ + if (freq == NULL) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || (mmc_drv_obj.card_power_enable != TRUE)) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* clock is already running in the desired frequency. */ + if ((mmc_drv_obj.clock_enable == TRUE) && (mmc_drv_obj.current_freq == *freq)) + { + return EMMC_SUCCESS; + } + + /* busy check */ + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR; + } + + set_sd_clk(*freq); + mmc_drv_obj.clock_enable = FALSE; + + return emmc_clock_ctrl(TRUE); /* clock on */ +} + +/** set sd clock. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * set mmc clock. + * + * param[in] clkDiv request freq + * return None. + */ +static void set_sd_clk(uint32_t clkDiv) +{ + uint32_t dataL; + + dataL = (mem_read32(SD_CLK_CTRL) & (~SD_CLK_CTRL_CLKDIV_MASK)); + + switch (clkDiv) + { + case 1U: /* 1/1 */ + dataL |= 0x000000FFU; + break; + case 2U: /* 1/2 */ + dataL |= 0x00000000U; + break; + case 4U: /* 1/4 */ + dataL |= 0x00000001U; + break; + case 8U: /* 1/8 */ + dataL |= 0x00000002U; + break; + case 16U: /* 1/16 */ + dataL |= 0x00000004U; + break; + case 32U:/* 1/32 */ + dataL |= 0x00000008U; + break; + case 64U:/* 1/64 */ + dataL |= 0x00000010U; + break; + case 128U:/* 1/128 */ + dataL |= 0x00000020U; + break; + case 256U: /* 1/256 */ + dataL |= 0x00000040U; + break; + case 512U:/* 1/512 */ + dataL |= 0x00000080U; + break; + default: + /* nop */ + break; + } + + mem_write32(SD_CLK_CTRL, dataL); + mmc_drv_obj.current_freq = (uint32_t)clkDiv; +} + + +/** Enable/Disable MMC clock + * + * - Pre-conditions:
+ * Before enabling the clock for the first time the desired clock frequency must be set with + * emmc_set_clock_freq(). + * Berore setting mmc_drv_obj.data_timeout with emmc_set_data_timeout(). + * + * - Post-conditions:
+ * After this function is called, clock to memory card IF is on/off. + * + * param[in] mode TRUE = clock on, FALSE = clock off + * retval EMMC_SUCCESS succeeded + * retval EMMC_ERR Busy + */ +static EMMC_ERROR_CODE emmc_clock_ctrl(uint32_t mode) +{ + uint32_t value; + + /* busy check */ + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR; + } + + if (mode == TRUE) + { + /* clock ON */ + value = ((mem_read32(SD_CLK_CTRL) | MMC_SD_CLK_START) & SD_CLK_WRITE_MASK); + mem_write32(SD_CLK_CTRL, value); /* on */ + mmc_drv_obj.clock_enable = TRUE; + } else { + /* clock OFF */ + value = ((mem_read32(SD_CLK_CTRL) & MMC_SD_CLK_STOP) & SD_CLK_WRITE_MASK); + mem_write32(SD_CLK_CTRL, value); /* off */ + mmc_drv_obj.clock_enable = FALSE; + } + + return EMMC_SUCCESS; +} + +/** Calculate Card support frequency. + * TRAN_SPEED defines the clock frequency when not in high speed mode. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * None. + * return Frquency[Hz] + */ +static uint32_t emmc_calc_tran_speed(void) +{ + const uint32_t unit[8U] = {10000U, 100000U, 1000000U, 10000000U, 0U, 0U, 0U, 0U}; /**< frequency unit (1/10) */ + const uint32_t mult[16U] = {0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, 35U, 40U, 45U, 52U, 55U, 60U, 70U, 80U}; /**< multiple factor (x10) */ + uint32_t maxFreq = 0U; + uint32_t result = 0U; + uint32_t tran_speed = EMMC_CSD_TRAN_SPEED(); + + /* tran_speed = 0x32 + * unit[tran_speed&0x7] = uint[0x2] = 1000000 + * mult[(tran_speed&0x78)>>3] = mult[0x30>>3] = mult[6] = 26 + * 1000000 * 26 = 26000000 (26MHz) + */ + + maxFreq = unit[tran_speed & EMMC_TRANSPEED_FREQ_UNIT_MASK] + * mult[(tran_speed & EMMC_TRANSPEED_MULT_MASK) >> EMMC_TRANSPEED_MULT_SHIFT]; + + if (maxFreq == 0U) + { + result = 0U; + } else if ( MMC_FREQ_52MHZ <= maxFreq) { + mmc_drv_obj.set_freq = MMC_52MHZ; + result = 1U; + } else if ( MMC_FREQ_26MHZ <= maxFreq) { + mmc_drv_obj.set_freq = MMC_26MHZ; + result = 1U; + } else if ( MMC_FREQ_20MHZ <= maxFreq) { + mmc_drv_obj.set_freq = MMC_20MHZ; + result = 1U; + } else { + mmc_drv_obj.set_freq = MMC_400KHZ; + result = 1U; + } + + return result; +} + +/** Calculate read/write timeout. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * set mmc clock. + * + * param[in] freq Base clock Div + * return SD_OPTION Timeout Counter + */ +static uint32_t emmc_set_timeout_register_value(uint32_t freq) +{ + uint32_t timeoutCnt = 0U; /* SD_OPTION - Timeout Counter */ + + switch (freq) + { + case 1U:/* SDCLK * 2^27 */ + timeoutCnt = 0xE0U; + break; + case 2U:/* SDCLK * 2^27 */ + timeoutCnt = 0xE0U; + break; + case 4U:/* SDCLK * 2^26 */ + timeoutCnt = 0xD0U; + break; + case 8U:/* SDCLK * 2^25 */ + timeoutCnt = 0xC0U; + break; + case 16U:/* SDCLK * 2^24 */ + timeoutCnt = 0xB0U; + break; + case 32U:/* SDCLK * 2^23 */ + timeoutCnt = 0xA0U; + break; + case 64U:/* SDCLK * 2^22 */ + timeoutCnt = 0x90U; + break; + case 128U:/* SDCLK * 2^21 */ + timeoutCnt = 0x80U; + break; + case 256U:/* SDCLK * 2^20 */ + timeoutCnt = 0x70U; + break; + case 512U:/* SDCLK * 2^19 */ + timeoutCnt = 0x60U; + break; + default: + /* nop */ + break; + } + + return timeoutCnt; +} + +/** Excecute tuning process and find optimal sampling clock position. + * + * Excecute tuning process in emmc_scc_tuningmain() and + * find optimal sampling clock position in emmc_tapset_position_find. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * None. + * + * return emmc error code. + */ +static EMMC_ERROR_CODE emmc_scc_tuning(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t i; + uint8_t result_tuning[8]; + uint32_t smpcmp[8]; + uint32_t dataL; + uint32_t tapset; + uint32_t allPass; + uint32_t tapsetNum; + + /* Hardware Adjustment Register */ + mem_write32(SCC_DT2FF, 0x00000300U); /* fixed value */ + + dataL = mem_read32(SCC_DTCNTL); + tapsetNum = (dataL & BIT23_16) >> 16U; + + /* CRC16(for Data) Disable */ + mem_write32(SDIF_MODE, (mem_read32(SDIF_MODE) | BIT8)); + + allPass = TRUE; /* allPass flag */ + for (i = 0; i < tapsetNum; i++) + { + result_tuning[i] = emmc_scc_tuningmain(i); + smpcmp[i] = mem_read32(SCC_SMPCMP); + + if( result_tuning[i] != TUNING_SUCCESS ) + { + result_tuning[i] = FAIL; + allPass = FALSE; /* if fail : clear allPass flag */ + } + } + + /* Detecting a change point of the input data + SCC_SMPCMP[24:16] : CMPNGU = There is a change point of data just before TAP-CLK. + SCC_SMPCMP[8:0] : CMPNGD = There is a change point of data just after TAP-CLK. + If "result_tuning[i]" is all pass, confirm SCC_SMPCMP and avoid setting value close to change point */ + if (allPass == TRUE) + { + for (i = 0; i < tapsetNum; i++) + { + if(smpcmp[i] == SMPCMP_SUCCESS) + { + result_tuning[i] = SUCCESS; /* result=Pass */ + } else { + result_tuning[i] = FAIL; /* result=Fail */ + } + } + } + + /* CRC16(for Data) Enable */ + mem_write32(SDIF_MODE, (mem_read32(SDIF_MODE) & ~BIT8)); + + /* Int flag clear */ + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, 0x00000000U); + + result = emmc_tapset_position_find(tapsetNum, result_tuning, &tapset); + if (result != EMMC_SUCCESS) + { + ERROR("%s:0x%x\n",__func__,RCAR_ERR); + panic; + } + + mem_write32(SCC_TAPSET, tapset); + + /* SET_BLOCKLEN */ + /* CMD16 */ + emmc_make_nontrans_cmd(CMD16_SET_BLOCKLEN, 512); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + panic; + } + + /* Transfer Data Length */ + mem_write32(SD_SIZE, 512U); + + return result; +} + +/** Excecute tuning process. + * + * Set sampling clock position 'tapset'(0-7) and + * Excecute tuninng process by CMD21. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * None. + * + * param[in] tapset number 0-7 + * retval TUNING_SUCCESS successful + * retval EMMC_TUNING_FAIL error from eMMC + * retval RCAR_TUNING_FAIL error from R-car + * return result of tuning + */ +static uint8_t emmc_scc_tuningmain(uint32_t tapset) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint8_t result_tuning = TUNING_SUCCESS; + uint64_t i; + uint32_t dataL; + uint32_t sd_info2; + uint8_t tuningBuf[128] __attribute__ ((aligned (8))); /* 1024bit (64bit alignment) */ + + const uint32_t eMmcTuningBlockPattern[32]={ + 0xFF00FFFFU, 0x0000FFFFU, 0xCCCCFFFFU, 0xCCCC33CCU, + 0xCC3333CCU, 0xFFFFCCCCU, 0xFFFFEEFFU, 0xFFEEEEFFU, + 0xFFDDFFFFU, 0xDDDDFFFFU, 0xBBFFFFFFU, 0xBBFFFFFFU, + 0xFFFFFFBBU, 0xFFFFFF77U, 0x77FF7777U, 0xFFEEDDBBU, + 0x00FFFFFFU, 0x00FFFFFFU, 0xCCFFFF00U, 0xCC33CCCCU, + 0x3333CCCCU, 0xFFCCCCCCU, 0xFFEEFFFFU, 0xEEEEFFFFU, + 0xDDFFFFFFU, 0xDDFFFFFFU, 0xFFFFFFDDU, 0xFFFFFFBBU, + 0xFFFFBBBBU, 0xFFFF77FFU, 0xFF7777FFU, 0xEEDDBB77U, + }; + + /* SCC_TAPSET : Sampling Clock Position */ + mem_write32(SCC_TAPSET, tapset); + + /* Clear flags */ + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, 0x00000000U); + + /* The data length of the tuning block is fixed. The BLOCKLEN command is unnecessary */ + + /* Transfer Data Length */ + mem_write32(SD_SIZE, 128); + + /* Block Count Disable */ + mem_write32(SD_STOP, 0x00000000U); + + /* MMC_CMD21:SEND_TUNING_BLOCK */ + /* CMD21 */ + result = emmc_exec_cmd21(); + if (result != EMMC_SUCCESS) + { + result_tuning = EMMC_TUNING_FAIL; + goto EXIT; + } + + /* Check Error */ + /* BIT2: END error (Communications Errors) */ + /* BIT1: CRC error (Communications Errors) */ + /* BIT0: CMD error (Communications Errors) */ + sd_info2 = mem_read32(SD_INFO2); + if ((BIT2_0 & sd_info2) != 0U) + { + result_tuning = RCAR_TUNING_FAIL; + goto EXIT; + } + + result = emmc_data_read((void*)tuningBuf); + if (result != EMMC_SUCCESS) + { + result_tuning = RCAR_TUNING_FAIL; + goto EXIT; + } + + /* Check Error */ + /* BIT3: Data timeout(other than response timeout) (Timeouts) */ + /* BIT2: END error (Communications Errors) */ + /* BIT1: CRC error (Communications Errors) */ + /* BIT0: CMD error (Communications Errors) */ + sd_info2 = mem_read32(SD_INFO2); + if ((BIT3_0 & sd_info2) != 0U) + { + result_tuning = RCAR_TUNING_FAIL; + goto EXIT; + } else { + /* Tuning Data Verify */ + for (i = 0; i < (128U>>2U); i++) + { + dataL = mem_read32((uintptr_t)tuningBuf + (uintptr_t)(i<<2U)); + if(dataL != eMmcTuningBlockPattern[i]) + { + result_tuning = RCAR_TUNING_FAIL; + goto EXIT; + } + } + } + + goto EXIT; + +EXIT: + return result_tuning; +} + +/** Send CMD21(SEND_TUNING_BLOCK) to eMMC. + * + * Send CMD21 to eMMC and check error using SD_INFO1,2. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * None. + * + * return result(EMMC_SUCCESS or RCAR_ERR). + */ +static EMMC_ERROR_CODE emmc_exec_cmd21(void) +{ + EMMC_ERROR_CODE result = RCAR_ERR; + uint32_t loop = 1U; + uint32_t sd_info1; + uint32_t sd_info2; + + mem_write32(SD_ARG, 0); + mem_write32(SD_CMD, MMC_CMD21); + + while(loop == 1U) + { + sd_info1 = mem_read32(SD_INFO1); + if(((sd_info1 & BIT0)) == 1U) /* INFO0 = 1 (Response End) */ + { + mem_write32(SD_INFO1, 0x0000FFFE); /* clear BIT0 */ + result = EMMC_SUCCESS; + loop = 0U; + } + + sd_info2 = mem_read32(SD_INFO2); + if ((BIT6_0 & sd_info2) != 0U) + { + result = RCAR_ERR; + break; + } + } + + return result; +} + +/** Find optimal sampling clock position. + * + * Based on the 'tapsetNum' number of result_tuning, + * Choose optimal sampling clock position and store it in tapset. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * None. + * + * param[in] total number of tapset: 0-7 + * result[] of tuning: 0 or 1 + * pointer to tapset + * retval EMMC_SUCCESS successful + * retval RCAR_ERR the number of tuning failure is smaller than 3 + * return emmc error code. + */ +static EMMC_ERROR_CODE emmc_tapset_position_find(uint32_t tapsetNum, const uint8_t result_tuning[], uint32_t *tapset) +{ + EMMC_ERROR_CODE result = EMMC_SUCCESS; + uint8_t tbl[8*2U] = {}; + uint32_t i; + uint32_t maxCount; + uint32_t maxPassPos; + uint32_t nowCount; + uint32_t passPos; + + /* tbl <- result_tuning */ + if ((tapsetNum >= 1U) && (tapsetNum <= 8U)) + { + for (i = 0; i < tapsetNum; i++) + { + tbl[i] = result_tuning[i]; + tbl[i+tapsetNum] = result_tuning[i]; + } + } else { + ERROR("invalid tapsetNum\n"); + panic; + } + + /* Search */ + maxCount = 0; + maxPassPos = 0; + nowCount = 0; + passPos = 0; + for (i = 0; i < (tapsetNum*2U); i++) + { + if (tbl[i] == SUCCESS) + { + nowCount++; + if (nowCount == FIRST) + { + passPos = i; + } + if (nowCount >= tapsetNum) + { + maxCount = tapsetNum; + maxPassPos = 0; + break; + } + } else { + if (nowCount != 0U) + { + if (maxCount < nowCount) + { + maxCount = nowCount; + maxPassPos = passPos; + } + } + nowCount = 0; + passPos = 0; + } + } + + /* Check 3 or more */ + if (maxCount < 3U) + { + *tapset = 0; + result = RCAR_ERR; /* Error End */ + } + + /* Set value select */ + if (maxCount == tapsetNum) + { + *tapset = 0; /* All pass : Default value = 0 */ + } else { + *tapset = maxPassPos+(maxCount>>1); + } + if (*tapset > 7U) + { + *tapset -= 8U; + } + + return result; /* Normal End */ +} + +/** Read emmc SD_BUF data. + * + * Read 128byte data and write the data to *buf. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * Completing writing emmc data to *buf. + * + * param[in] pointer to buffer in which read data is stored + * retval EMMC_SUCCESS successful + * retval RCAR_ERR SD_INFO2 error + * return emmc error code. + */ +static EMMC_ERROR_CODE emmc_data_read(void *buf) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t i; + uint64_t *bufPtrLL; + + bufPtrLL = (uint64_t*)buf; + mem_write32(SD_INFO1, 0x0000FFFEU); /* clear BIT0 */ + + result = emmc_wait_readbuf_enable(); + if (result != EMMC_SUCCESS) + { + ERROR("%s:0x%x\n",__func__,RCAR_ERR); + panic; + } + + for (i = 0; i < (128U>>3U); i++) /* 64-bit access */ + { + *bufPtrLL = mem_read64(SD_BUF0); + bufPtrLL++; + } + + result = emmc_wait_readbuf_end(); + if (result != EMMC_SUCCESS) + { + ERROR("%s:0x%x\n",__func__,RCAR_ERR); + } + + return result; +} + +/** Check if emmc read operation has enabled and error occured. + * + * Check BIT8 of SD_INFO2. If the bit is set, + * emmc read operation has enabled and EMMC_SUCCESS is returned. + * Check BIT0-6 of SD_INFO2. If their bit is set, + * some errors has occured and RCAR_ERR is returned. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * None. + * + * retval EMMC_SUCCESS successful + * retval RCAR_ERR SD_INFO2 error + * return emmc error code. + */ +static EMMC_ERROR_CODE emmc_wait_readbuf_enable(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t dataL; + + while(true) + { + dataL = mem_read32(SD_INFO2); + if((dataL & BIT8) != 0U) /* SD_BUF Read Enable = 1 */ + { + mem_write32(SD_INFO2, 0x0000FEFFU); /* clear BIT8 */ + result = EMMC_SUCCESS; + break; + } + + /* Check Error */ + /* BIT6: Response timeout (Timeouts) */ + /* BIT5: SD_BUF Illegal Read Access */ + /* BIT4: SD_BUF Illegal Write Access */ + /* BIT3: Data timeout(other than response timeout) (Timeouts) */ + /* BIT2: END error (Communications Errors) */ + /* BIT1: CRC error (Communications Errors) */ + /* BIT0: CMD error (Communications Errors) */ + if ((BIT6_0 & dataL) != 0U) + { + result = RCAR_ERR; + break; + } + } + + return result; +} + +/** Check if emmc read operation has completed and some error occured. + * + * Check BIT2 of SD_INFO1. If the bit is set, + * emmc read operation has completed and EMMC_SUCCESS is returned. + * Check BIT0-6 of SD_INFO2. If their bit is set, + * some errors occured and RCAR_ERR is returned. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * None. + * + * retval EMMC_SUCCESS successful + * retval RCAR_ERR SD_INFO2 error + * return emmc error code. + */ +static EMMC_ERROR_CODE emmc_wait_readbuf_end(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t dataL; + + while(true) + { + dataL = mem_read32(SD_INFO1); + if((dataL & BIT2) != 0U) /* Access End = 1 */ + { + mem_write32(SD_INFO1, 0x0000FFFBU); /* clear BIT2 */ + result = EMMC_SUCCESS; + break; + } + + dataL = mem_read32(SD_INFO2); + + /* Check Error */ + /* BIT6: Response timeout (Timeouts) */ + /* BIT5: SD_BUF Illegal Read Access */ + /* BIT4: SD_BUF Illegal Write Access */ + /* BIT3: Data timeout(other than response timeout) (Timeouts) */ + /* BIT2: END error (Communications Errors) */ + /* BIT1: CRC error (Communications Errors) */ + /* BIT0: CMD error (Communications Errors) */ + if ((BIT6_0 & dataL) != 0U) + { + result = RCAR_ERR; + break; + } + } + + return result; +} + +/** PFC register write operation. + * + * Write data masked with mask to addr after writing PMMR register. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * Update PFC register + * + * param[in] register address + * mask value + * data to write + * return None. + */ +static void pfc_reg_modify_write(uintptr_t addr, uint32_t mask, uint32_t data) +{ + uint32_t localdata; + + localdata = mem_read32(addr); + localdata &= ~(mask); + localdata |= data; + mem_write32(PFC_PMMR(addr), ~(localdata)); + mem_write32(addr, localdata); +} diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_multiboot.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_multiboot.c new file mode 100644 index 0000000..74bd2fb --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_multiboot.c @@ -0,0 +1,94 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc multi boot + ******************************************************************************/ +/****************************************************************************** + * @file emmc multiboot.c + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_def.h" +#include "emmc_multiboot.h" +#include "types.h" + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +uint32_t emmc_check_result(uint32_t result); + +/* ********************************* CODE ********************************** */ + + +uint32_t emmc_trans_data(uint32_t next_bootPartition, uintptr_t sourceSct, uintptr_t targetAd, uint32_t sectorSize) +{ + EMMC_ERROR_CODE result; + uint32_t rtn_val = EMMC_DEV_ERR; + + /* Partition select */ + result = emmc_select_partition((EMMC_PARTITION_ID)next_bootPartition); + + if (result == EMMC_SUCCESS) + { + result = emmc_read_sector((uint32_t *)targetAd, sourceSct, sectorSize, LOADIMAGE_FLAGS_DMA_ENABLE); + } + + /* EMMC_ERROR_CODE -> ROM_XX */ + rtn_val = emmc_check_result((uint32_t)result); + + return rtn_val; +} +uint32_t emmc_check_result(uint32_t result) +{ + uint32_t ret = EMMC_DEV_ERR_FAULT_INJECTION; + + if (result == EMMC_SUCCESS) + { + ret = EMMC_DEV_OK; + } else if (result == EMMC_ERR) { + ret = EMMC_DEV_ERR; + } else { /* other */ + ret = EMMC_DEV_ERR_HW; + } + + return ret; +} +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_read.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_read.c new file mode 100644 index 0000000..f1f00c4 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_read.c @@ -0,0 +1,216 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc read + ******************************************************************************/ +/****************************************************************************** + * @file emmc_read.c + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 23.03.2022 0.02 Added header file inclusion + * : 16.06.2022 0.03 Change log output + * : 31.10.2022 0.04 License notation change. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "log.h" +#include "mem_io.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +#define EMMC_RW_SECTOR_COUNT_MAX 0x0000ffffUL + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +static EMMC_ERROR_CODE emmc_multiple_block_read (uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode); + +static inline uint32_t get_min_value(uint32_t a, uint32_t b) +{ + uint32_t ret = a; + + if(b < a) + { + ret = b; + } + + return ret; +} + +/* ********************************* CODE ********************************** */ + +/** function of read sector + * + * This function always use block read. + * Single block read is not used. + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * . + * + * param[in,out] buff_address_virtual virtual address of read data buffer. + * param[in] sector_number data address for MMC device (sector number). + * param[in] count number of sector. + * param[in] transfermode Mode of data transfer, DMA or not DMA. + */ +EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, + uint32_t feature_flags) +{ + uint32_t trans_count; + uint32_t remain; + EMMC_ERROR_CODE result = EMMC_ERR; + HAL_MEMCARD_DATA_TRANSFER_MODE transfermode; + + /* parameter check */ + if (count == 0U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.mount != TRUE) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* DMA? */ + if ((feature_flags & LOADIMAGE_FLAGS_DMA_ENABLE) != 0U) + { + transfermode = HAL_MEMCARD_DMA; + } else { + transfermode = HAL_MEMCARD_NOT_DMA; + } + + remain = count; + while (remain != 0U) + { + trans_count = get_min_value(remain, EMMC_RW_SECTOR_COUNT_MAX); + result = emmc_multiple_block_read(buff_address_virtual, sector_number, trans_count, transfermode); + if (result != EMMC_SUCCESS) + { + return result; + } + + buff_address_virtual += (EMMC_BLOCK_LENGTH_DW * trans_count); + sector_number += trans_count; + remain -= trans_count; + } + + return EMMC_SUCCESS; +} + +/** multiple block read + * + * Multiple block read with pre-defined block count. + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * . + * + * param[in,out] buff_address_virtual virtual address of read data buffer. + * param[in] sector_number data address for MMC device (sector number). + * param[in] count number of sector. (0x1 - 0xffff) + * param[in] transfer_mode Mode of data transfer, DMA or not DMA. + */ +static EMMC_ERROR_CODE emmc_multiple_block_read(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* parameter check */ + if ((count > EMMC_RW_SECTOR_COUNT_MAX) || (count == 0U) + || ((transfer_mode != HAL_MEMCARD_DMA) && (transfer_mode != HAL_MEMCARD_NOT_DMA))) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* CMD23 */ + emmc_make_nontrans_cmd(CMD23_SET_BLOCK_COUNT, count); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + mem_write32(SD_SECCNT, count); + mem_write32(SD_STOP, 0x00000100U); + mem_write32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE)); /* SD_BUF Read/Write DMA Transfer enable */ + + /* CMD18 */ + emmc_make_trans_cmd(CMD18_READ_MULTIPLE_BLOCK, sector_number, buff_address_virtual, count << EMMC_SECTOR_SIZE_SHIFT, + HAL_MEMCARD_READ, transfer_mode); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; /* CMD18 error code */ + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + + /* ready status check */ + if ((mmc_drv_obj.r1_card_status & EMMC_R1_READY) == 0U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR_CARD_BUSY; + } + + /* state check */ + if (mmc_drv_obj.current_state != EMMC_R1_STATE_TRAN) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_STATE); + return EMMC_ERR_CARD_STATE; + } + + return EMMC_SUCCESS; +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_utility.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_utility.c new file mode 100644 index 0000000..6112b5e --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/emmc/emmc_utility.c @@ -0,0 +1,305 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc utility + ******************************************************************************/ +/****************************************************************************** + * @file emmc_utility + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +#define BUSY_SIGNAL (1U << 10U) + +static const uint32_t cmd_reg_hw[EMMC_CMD_MAX + 1U] = +{ + 0x00000000U, /* CMD0 */ + 0x00000701U, /* CMD1 */ + 0x00000002U, /* CMD2 */ + 0x00000003U, /* CMD3 */ + 0x00000004U, /* CMD4 */ + 0x00000505U, /* CMD5 */ + 0x00000406U, /* CMD6 */ + 0x00000007U, /* CMD7 */ + 0x00001C08U, /* CMD8 */ + 0x00000009U, /* CMD9 */ + 0x0000000AU, /* CMD10 */ + 0x00000000U, /* reserved */ + 0x0000000CU, /* CMD12 */ + 0x0000000DU, /* CMD13 */ + 0x00001C0EU, /* CMD14 */ + 0x0000000FU, /* CMD15 */ + 0x00000010U, /* CMD16 */ + 0x00000011U, /* CMD17 */ + 0x00007C12U, /* CMD18 */ + 0x00000C13U, /* CMD19 */ + 0x00000000U, + 0x00001C15U, /* CMD21 */ + 0x00000000U, + 0x00000017U, /* CMD23 */ + 0x00000018U, /* CMD24 */ + 0x00006C19U, /* CMD25 */ + 0x00000C1AU, /* CMD26 */ + 0x0000001BU, /* CMD27 */ + 0x0000001CU, /* CMD28 */ + 0x0000001DU, /* CMD29 */ + 0x0000001EU, /* CMD30 */ + 0x00001C1FU, /* CMD31 */ + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000423U, /* CMD35 */ + 0x00000424U, /* CMD36 */ + 0x00000000U, + 0x00000026U, /* CMD38 */ + 0x00000427U, /* CMD39 */ + 0x00000428U, /* CMD40 : send cmd */ + 0x00000000U, + 0x0000002AU, /* CMD42 */ + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000C31U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00007C35U, + 0x00006C36U, + 0x00000037U, /* CMD55 */ + 0x00000038U, /* CMD56 : Read */ + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U +}; +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +/** make non-transfer command data + * + * Response data buffer is automatically selected. + * + * - Pre-conditions:
+ * Clock to memory card IF is enabled. + * + * - Post-conditions:
+ * After this function is called, command can be executed. + * + * param[in] cmd command information. + * param[in] arg command argument + * return None. + */ +void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg) +{ + /* command information */ + mmc_drv_obj.cmd_info.cmd = cmd; + mmc_drv_obj.cmd_info.arg = arg; + mmc_drv_obj.cmd_info.dir = HAL_MEMCARD_READ; + mmc_drv_obj.cmd_info.hw = cmd_reg_hw[(uint32_t)cmd & HAL_MEMCARD_COMMAND_INDEX_MASK]; + + /* clear data transfer information */ + mmc_drv_obj.trans_size = 0U; + mmc_drv_obj.remain_size = 0U; + mmc_drv_obj.buff_address_virtual = NULL; + mmc_drv_obj.buff_address_physical = NULL; + + /* response information */ + mmc_drv_obj.response_length = 6U; + + switch ((HAL_MEMCARD_RESPONSE_TYPE)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK)) + { + case HAL_MEMCARD_RESPONSE_NONE: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + mmc_drv_obj.response_length = 0U; + break; + case HAL_MEMCARD_RESPONSE_R1: + mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; + break; + case HAL_MEMCARD_RESPONSE_R1b: + mmc_drv_obj.cmd_info.hw |= BUSY_SIGNAL; /* bit10 = R1 busy bit */ + mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; + break; + case HAL_MEMCARD_RESPONSE_R2: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + mmc_drv_obj.response_length = 17U; + break; + case HAL_MEMCARD_RESPONSE_R3: + mmc_drv_obj.response = &mmc_drv_obj.r3_ocr; + break; + case HAL_MEMCARD_RESPONSE_R4: + mmc_drv_obj.response = &mmc_drv_obj.r4_resp; + break; + case HAL_MEMCARD_RESPONSE_R5: + mmc_drv_obj.response = &mmc_drv_obj.r5_resp; + break; + default: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + break; + } +} + +/** Making command information for data transfer command. + * + * - Pre-conditions:
+ * None. + * + * - Post-conditions:
+ * After this function is called, command can be executed. + * + * param[in] cmd command + * param[in] arg command argument + * param[in] buff_address_virtual Pointer to buffer where data is/will be stored. (virtual address) + * Client is responsible of allocation and deallocation of the buffer. + * param[in] len transfer length in bytes + * param[in] dir direction + * param[in] transfer_mode Mode of data transfer, DMA or not DMA. + * return None. + */ +void emmc_make_trans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual, /* virtual address */ +uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode) +{ + emmc_make_nontrans_cmd(cmd, arg); /* update common information */ + + /* for data transfer command */ + mmc_drv_obj.cmd_info.dir = dir; + mmc_drv_obj.buff_address_virtual = buff_address_virtual; + mmc_drv_obj.buff_address_physical = buff_address_virtual; + mmc_drv_obj.trans_size = len; + mmc_drv_obj.remain_size = len; + mmc_drv_obj.transfer_mode = transfer_mode; +} + +/** Send idle command. + * Function execute CMD0. + * + * - Pre-conditions:
+ * Clock to MMC I/F enabled. + * + * - Post-conditions:
+ * Card reset to idle or pre-idle state. + * + * param[in] arg CMD0 argument. + * return error code + */ +EMMC_ERROR_CODE emmc_send_idle_cmd(uint32_t arg) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* initialize state */ + mmc_drv_obj.mount = FALSE; + mmc_drv_obj.selected = FALSE; + mmc_drv_obj.during_transfer = FALSE; + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.dma_error_flag = FALSE; + mmc_drv_obj.force_terminate = FALSE; + mmc_drv_obj.state_machine_blocking = FALSE; + + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; + mmc_drv_obj.max_freq = MMC_20MHZ; /* 20MHz */ + mmc_drv_obj.current_state = EMMC_R1_STATE_IDLE; + + /* CMD0 (MMC clock is current frequency. if Data transfer mode, 20MHz or higher.) */ + emmc_make_nontrans_cmd(CMD0_GO_IDLE_STATE, arg); /* CMD0 */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + + /* change MMC clock(400KHz) */ + mmc_drv_obj.set_freq = MMC_400KHZ; + result = emmc_set_request_mmc_clock(&mmc_drv_obj.set_freq); + if (result != EMMC_SUCCESS) + { + return result; + } + + return EMMC_SUCCESS; +} + +/** get bit field data for 16bytes data(CSD register). + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param[in] data 16bytes data. + * param[in] top bit number(top). 128>top + * param[in] bottom bit number(bottom). (0<=bottom<=top) + * return bit field. + */ +uint32_t emmc_bit_field(const uint8_t *data, uint32_t top, uint32_t bottom) +{ + uint32_t value; + + uint32_t index_top = (uint32_t)(15U - (top >> 3U)); + uint32_t index_bottom = (uint32_t)(15U - (bottom >> 3U)); + + if (index_top == index_bottom) + { + value = data[index_top]; + } else if ((index_top + 1U) == index_bottom) { + value = (uint32_t)(((uint32_t)data[index_top] << 8U) | data[index_bottom]); + } else if ((index_top + 2U) == index_bottom) { + value = (uint32_t)( + ((uint32_t)data[index_top] << 16U) | ((uint32_t)data[index_top + 1U] << 8U) | data[index_top + 2U]); + } else { + value = (uint32_t)( + ((uint32_t)data[index_top] << 24U) | ((uint32_t)data[index_top + 1U] << 16U) + | ((uint32_t)data[index_top + 2U] << 8U) | data[index_top + 3U]); + } + + value = ((value >> (bottom & 0x07U)) & ((1U << ((top - bottom) + 1U)) - 1U)); + + return value; +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/gpio b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/gpio new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/interrupt.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/interrupt.c new file mode 100644 index 0000000..951705e --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/interrupt.c @@ -0,0 +1,102 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : INTC handler function + ******************************************************************************/ +/****************************************************************************** + * @file interrupt.c + * - Version : 0.05 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.08.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + * : 15.12.2022 0.03 V4H interrupt support. + * : 27.12.2022 0.04 Change argument of pabort_error. + * : 21.08.2023 0.05 Add support for V4M. + *****************************************************************************/ +#include "ip_control.h" +#include "log.h" +#include "gic.h" +#include "swdt.h" +#include "interrupt.h" + +#if (RCAR_LSI == RCAR_S4) +void handler_fiq(void) +{ + uint32_t intid = GIC_AcknowledgePending(); + if (intid == INTC_SPI_SWDT) + { + swdt_exec(); + } + else + { + ERROR("Invalid interrupt occurred.(%d)\n",intid); + panic; + } +} +/* End of function handler_fiq(void) */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +void dabort_error(uint32_t occ_add, uint32_t dfsr, uint32_t dfar) +{ + + ERROR("Data abort.\n"); + ERROR(" Data abort occurrred address : 0x%x\n", occ_add); + ERROR(" DFSR:0x%x DFAR:0x%x\n", dfsr, dfar); + panic; + +} +/* End of function dabort_error(uint32_t occ_add, uint32_t dfsr, uint32_t dfare) */ + +void pabort_error(uint32_t ifsr, uint32_t ifar) +{ + + ERROR("Prefetch abort.\n"); + ERROR(" IFSR:0x%x IFAR:0x%x\n", ifsr, ifar); + panic; +} +/* End of function pabort_error(uint32_t ifsr, uint32_t ifar) */ + +void Undefined_error(uint32_t occ_add) +{ + + ERROR("Undefined Instruction.\n"); + ERROR(" Undefined Instruction occurrred address : 0x%x\n", occ_add); + panic; +} +/* End of function Undefined_error(uint32_t occ_add) */ +#endif /* RCAR_LSI == RCAR_S4 */ + +void handler_error(uint32_t ex_type) +{ + + ERROR("Unhandled exception occurred.\n"); + ERROR(" Exception type = 0x%x.\n", ex_type); + panic; +} +/* End of function handler_error(uint32_t ex_type) */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ip_control.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ip_control.c new file mode 100644 index 0000000..6a1d9ff --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/ip_control.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : IP's control function + ******************************************************************************/ +/****************************************************************************** + * @file ip_control.c + * - Version : 0.08 + * @brief Initial setting controller. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 30.11.2021 0.01 First Release + * : 18.01.2022 0.02 Changed log output + * Supported Generic Timer + * : 22.03.2022 0.03 Removed unnecessary header file inclusions + * Removed unnecessary functions + * : 10.05.2022 0.04 Added function return value judgment + * : 16.06.2022 0.05 Change log output + * : 02.08.2022 0.06 Added SWDT and GIC + * : 31.10.2022 0.07 License notation change. + * : 04.09.2023 0.08 Add C4 power domain setting. + * : 13.10.2023 0.09 Moved C4 power domain setting to ICUMX IPL. + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include "gic.h" +#include "swdt.h" +#if (1 == (MEASURE_TIME)) + #include + #include +#else + #define scmt_wait_ticks(x) + #define store_time_checkpoint(x,y) +#endif + +void ip_init(void) +{ + scif_init(); + generic_timer_init(); + +#if (RCAR_LSI == RCAR_S4) + Interrupt_Config(); + Interrupt_Enable(INTC_SPI_SWDT); + swdt_init(); +#endif /* RCAR_LSI == RCAR_S4 */ +#ifndef MOBIS_PRK3 + emmc_initialize(); + store_time_checkpoint("emmc_initialize", 0); +#endif +} +/* End of function ip_init(void) */ + +void ip_release(void) +{ +#if (BL2_LOAD_ENABLE == BL2_DISABLE) + EMMC_ERROR_CODE result = EMMC_ERR; + + result = emmc_terminate(); + if(EMMC_SUCCESS != result) + { + ERROR("ip_release error (emmc_terminate).\n"); + panic; + } +#endif + +#if (RCAR_LSI == RCAR_S4) + swdt_release(); + Interrupt_Disable(INTC_SPI_SWDT); +#endif /* RCAR_LSI == RCAR_S4 */ +} +/* End of function ip_release(void) */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/qos/qos.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/qos/qos.c new file mode 100644 index 0000000..f1a22cd --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/qos/qos.c @@ -0,0 +1,553 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : QoS initialize function + ******************************************************************************/ +/****************************************************************************** + * @file qos.c + * - Version : 0.14 + * @brief Initial setting process of QoS. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 23.05.2022 0.02 Integration of S4 and V4H + * Update QoS setting rev.0.02 (for S4) + * Update QoS setting rev.0.03 (for V4H) + * : 20.01.2023 0.03 Add DBSC W/A 1,2,3 (OTLINT-5579) + * : 19.04.2023 0.04 Update the setting version from v6.1 to v7.0(for V4H). + * : 22.05.2023 0.05 Update the setting version from v7.0 to v7.1.1(for V4H). + * : 22.05.2023 0.06 Update the setting version from v7.1.1 to v8.0.0(for V4H). + * : 08.06.2023 0.07 Update the setting version from v8.0.0 to v8.0.1(for V4H). + * : 15.06.2023 0.08 Update the setting version from v8.0.1 to v8.0.2(for V4H). + * : 21.08.2023 0.09 Add support for V4M. + * : 20.09.2023 0.10 Update the setting version from v9.0.1 to v10.0.0(for V4M). + * : 20.09.2023 0.11 Update the setting version from v10.0.0 to v10.1.0(for V4H). + * : 11.10.2023 0.12 Update the setting version from v10.1.0 to v10.2.1(for V4H/V4M). + * : 17.01.2024 0.13 Update the setting version from v10.1.0 to v11.0.0(for V4H/V4M). + * : 05.04.2024 0.14 Update the setting version from v11.0.0 to v12.0.0(for V4H/V4M). + *****************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include +#include +#include +#else +#include +#include +#endif +#include +#include +#include +#include + +#if (RCAR_LSI == RCAR_S4) +#define RCAR_QOS_VERSION "base_v6.1" +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define RCAR_QOS_VERSION "v12.0.0" +#endif /* RCAR_LSI == RCAR_S4 */ + +#define RCAR_DRAM_SPLIT_DISABLE (0U) +#define RCAR_DRAM_SPLIT_ENABLE (1U) +#define RCAR_REWT_TRAINING_DISABLE (0U) +#define RCAR_REWT_TRAINING_ENABLE (1U) + +#if defined(__RH850G3K__) +#define AXMM_BASE (BASE_AXMM_ADDR) +#else +#define AXMM_BASE (0xE6780000U) +#endif +#define AXMM_MMCR (AXMM_BASE + 0x4300U) +#define AXMM_ADSPLCR0 (AXMM_BASE + 0x4008U) +#define AXMM_ADSPLCR1 (AXMM_BASE + 0x400CU) +#define AXMM_ADSPLCR2 (AXMM_BASE + 0x4010U) +#define AXMM_ADSPLCR3 (AXMM_BASE + 0x4014U) +#define AXMM_TR3CR (AXMM_BASE + 0x5100CU) + +#if (RCAR_LSI == RCAR_S4) +#if defined(__RH850G3K__) +#define DBSC_BASE (BASE_DBSC_ADDR) +#else +#define DBSC_BASE (0xE6790000U) +#endif + +#define DBSC_CH_NUM (1U) /* Number of DBSCx */ +#define DBSC_A_CH_OFFSET (0U) /* 1ch only (for S4)*/ +#define DBSC_D_CH_OFFSET (0U) /* 1ch only (for S4)*/ + +#define DBSC_SYSCNT0 (DBSC_BASE + 0x0100U) +#define DBSC_SYSCNT0A (DBSC_BASE + 0x0108U) +#define DBSC_DBBUS0CNF2 (DBSC_BASE + 0x0808U) +#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) +#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) +#define DBSC_DBCAMDIS (DBSC_BASE + 0x09FCU) +#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) +#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) +#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) +#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) +#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) +#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) +#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) +#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) +#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) +#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) +#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) +#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) +#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) +#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) +#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) +#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) +#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) +#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) +#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) +#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) +#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) +#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) +#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) +#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) +#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) +#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if defined(__RH850G3K__) +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) +#define DBSC_A_BASE (BASE_DBSC_ADDR) +#else +#define DBSC_D_BASE (0xE67A4000U) +#define DBSC_A_BASE (0xE6790000U) +#endif + +#if (RCAR_LSI == RCAR_V4H) +#define DBSC_CH_NUM (2U) /* ch number of DBSCx */ +#elif (RCAR_LSI == RCAR_V4M) +#define DBSC_CH_NUM (1U) /* ch number of DBSCx */ +#endif + +#define DBSC_A_CH_OFFSET (0x8000U) +#define DBSC_D_CH_OFFSET (0x4000U) + +#define DBSC_SYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DBSC_SYSCNT1 (DBSC_A_BASE + 0x0104U) +#define DBSC_SYSCNT0A (DBSC_A_BASE + 0x0100U) +#define DBSC_DBBUS0CNF2 (DBSC_A_BASE + 0x0808U) +#define DBSC_DBCAM0CNF1 (DBSC_A_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_A_BASE + 0x0908U) +#define DBSC_DBCAMDIS (DBSC_A_BASE + 0x09FCU) +#define DBSC_DBCAM0CNF3 (DBSC_A_BASE + 0x090CU) +#define DBSC_DBSCHCNT0 (DBSC_A_BASE + 0x1000U) +#define DBSC_DBSCHSZ0 (DBSC_A_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_A_BASE + 0x1020U) +#define DBSC_DBSCHQOS_0_0 (DBSC_A_BASE + 0x1100U) +#define DBSC_DBSCHQOS_0_1 (DBSC_A_BASE + 0x1104U) +#define DBSC_DBSCHQOS_0_2 (DBSC_A_BASE + 0x1108U) +#define DBSC_DBSCHQOS_0_3 (DBSC_A_BASE + 0x110CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_A_BASE + 0x1140U) +#define DBSC_DBSCHQOS_4_1 (DBSC_A_BASE + 0x1144U) +#define DBSC_DBSCHQOS_4_2 (DBSC_A_BASE + 0x1148U) +#define DBSC_DBSCHQOS_4_3 (DBSC_A_BASE + 0x114CU) +#define DBSC_DBSCHQOS_9_0 (DBSC_A_BASE + 0x1190U) +#define DBSC_DBSCHQOS_9_1 (DBSC_A_BASE + 0x1194U) +#define DBSC_DBSCHQOS_9_2 (DBSC_A_BASE + 0x1198U) +#define DBSC_DBSCHQOS_9_3 (DBSC_A_BASE + 0x119CU) +#define DBSC_DBSCHQOS_12_0 (DBSC_A_BASE + 0x11C0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_A_BASE + 0x11C4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_A_BASE + 0x11C8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_A_BASE + 0x11CCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_A_BASE + 0x11D0U) +#define DBSC_DBSCHQOS_13_1 (DBSC_A_BASE + 0x11D4U) +#define DBSC_DBSCHQOS_13_2 (DBSC_A_BASE + 0x11D8U) +#define DBSC_DBSCHQOS_13_3 (DBSC_A_BASE + 0x11DCU) +#define DBSC_DBSCHQOS_14_0 (DBSC_A_BASE + 0x11E0U) +#define DBSC_DBSCHQOS_14_1 (DBSC_A_BASE + 0x11E4U) +#define DBSC_DBSCHQOS_14_2 (DBSC_A_BASE + 0x11E8U) +#define DBSC_DBSCHQOS_14_3 (DBSC_A_BASE + 0x11ECU) +#define DBSC_DBSCHQOS_15_0 (DBSC_A_BASE + 0x11F0U) +#define DBSC_DBSCHQOS_15_1 (DBSC_A_BASE + 0x11F4U) +#define DBSC_DBSCHQOS_15_2 (DBSC_A_BASE + 0x11F8U) +#define DBSC_DBSCHQOS_15_3 (DBSC_A_BASE + 0x11FCU) +#define DBSC_SCFCTST2 (DBSC_A_BASE + 0x1048U) + +#define AXMM_TR0CR0 (AXMM_BASE + 0x51000U) +#define AXMM_TR1CR0 (AXMM_BASE + 0x51004U) +#define AXMM_TR2CR0 (AXMM_BASE + 0x51008U) +#define AXMM_TR3CR0 (AXMM_BASE + 0x5100CU) +#define AXMM_TR0CR1 (AXMM_BASE + 0x51100U) +#define AXMM_TR1CR1 (AXMM_BASE + 0x51104U) +#define AXMM_TR2CR1 (AXMM_BASE + 0x51108U) +#define AXMM_TR3CR1 (AXMM_BASE + 0x5110CU) +#define AXMM_TR0CR2 (AXMM_BASE + 0x51200U) +#define AXMM_TR1CR2 (AXMM_BASE + 0x51204U) +#define AXMM_TR2CR2 (AXMM_BASE + 0x51208U) +#define AXMM_TR3CR2 (AXMM_BASE + 0x5120CU) +#define DBSC_FCPRSCTRL (DBSC_A_BASE + 0x0110U) +#define ACTEXT_RT0_R (0xFFC50800U) +#define ACTEXT_RT0_W (0xFFC51800U) +#define ACTEXT_IR0_R (0xFF890800U) +#define ACTEXT_IR0_W (0xFF891800U) +#define ACTEXT_IR1_R (0xFF892800U) +#define ACTEXT_IR1_W (0xFF893800U) +#define SI0_RW_MAX (0xF1201110U) +#define SI1_RW_MAX (0xF1202110U) +#endif /* RCAR_LSI == RCAR_S4 */ + +#if defined(__RH850G3K__) +#define QOS_BASE (BASE_QOS_ADDR) +#else +#define QOS_BASE (0xE67E0000U) +#endif +#define QOS_FIX_QOS_BANK0 (QOS_BASE + 0x00000000U) +#define QOS_FIX_QOS_BANK1 (QOS_BASE + 0x00001000U) +#define QOS_BE_QOS_BANK0 (QOS_BASE + 0x00002000U) +#define QOS_BE_QOS_BANK1 (QOS_BASE + 0x00003000U) +#define QOS_SL_INIT (QOS_BASE + 0x00008000U) +#define QOS_REF_ARS (QOS_BASE + 0x00008004U) +#define QOS_STATQC (QOS_BASE + 0x00008008U) +#define QOS_REF_ENBL (QOS_BASE + 0x00008044U) +#define QOS_BWG (QOS_BASE + 0x0000804CU) +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE +#define QOSWT_FIX_QOS_BANK0 (QOS_BASE + 0x00000800U) +#define QOSWT_FIX_QOS_BANK1 (QOS_BASE + 0x00001800U) +#define QOSWT_BE_QOS_BANK0 (QOS_BASE + 0x00002800U) +#define QOSWT_BE_QOS_BANK1 (QOS_BASE + 0x00003800U) +#define QOSWT_WTEN (QOS_BASE + 0x00008030U) +#define QOSWT_WTREF (QOS_BASE + 0x00008034U) +#define QOSWT_WTSET0 (QOS_BASE + 0x00008038U) +#define QOSWT_WTSET1 (QOS_BASE + 0x0000803CU) +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + +#define QOS_RAS (QOS_BASE + 0x00010000U) +#define QOS_RAEN (QOS_BASE + 0x00010018U) +#define QOS_DANN_LOW (QOS_BASE + 0x00010030U) +#define QOS_DANN_HIGH (QOS_BASE + 0x00010034U) +#define QOS_DANT (QOS_BASE + 0x00010038U) +#define QOS_EMS_LOW (QOS_BASE + 0x00010040U) +#define QOS_EMS_HIGH (QOS_BASE + 0x00010044U) +#define QOS_FSS (QOS_BASE + 0x00010048U) +#define QOS_INSFC (QOS_BASE + 0x00010050U) +#define QOS_EARLYR (QOS_BASE + 0x00010060U) +#define QOS_RACNT0 (QOS_BASE + 0x00010080U) +#define QOS_STATGEN0 (QOS_BASE + 0x00010088U) + +#define CCI_BASE (BASE_CCI_ADDR) +#define CCIQOS00 (CCI_BASE + 0xC020U) +#define CCIQOS01 (CCI_BASE + 0xC024U) +#define CCIQOS10 (CCI_BASE + 0xD000U) +#define CCIQOS11 (CCI_BASE + 0xD004U) +#if (RCAR_LSI == RCAR_S4) +#define CCIQOS12 (CCI_BASE + 0xD008U) +#define CCIQOS13 (CCI_BASE + 0xD00CU) +#endif + +static void dbsc_setting(void) +{ + for(uint32_t loop = 0; loop < DBSC_CH_NUM; loop++) + { + /* DBSC CAM, Scheduling Setting */ + mem_write32((DBSC_SYSCNT0 + (DBSC_D_CH_OFFSET * loop)), 0x00001234U); + mem_write32((DBSC_SYSCNT0A + (DBSC_A_CH_OFFSET * loop)), 0x00001234U); + mem_write32((DBSC_DBCAM0CNF1 + (DBSC_A_CH_OFFSET * loop)), 0x00048218U); /* dbcam0cnf1 */ +#if ((ECC_ENABLE == 1) && (RCAR_LSI == RCAR_V4H)) + /* For WA for DBSC5 Hang5 issue. */ + if ((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21) + { + mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000002C4U); /* dbcam0cnf2 */ + } + else + { + mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U); /* dbcam0cnf2 */ + } +#elif (RCAR_LSI == RCAR_V4M) + mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U); /* dbcam0cnf2 */ +#else + mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U); /* dbcam0cnf2 */ +#endif + mem_write32((DBSC_DBCAM0CNF3 + (DBSC_A_CH_OFFSET * loop)), 0x00000003U); /* dbcam0cnf3 */ + +#if (RCAR_LSI == RCAR_S4) + #if ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 1)) + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000002U); /* OTLINT-5579: V4H DBSC W/A-1,2 */ + #else + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000000U); + #endif +#elif (RCAR_LSI == RCAR_V4H) + #if ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 1)) + if((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21) + { + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000013U); /* OTLINT-5579: V4H DBSC W/A-1,2,3 */ + } + else if((mem_read32(PRR) & PRR_CUT_MASK) == PRR_PRODUCT_22) + { + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000012U); + } + else + { + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); + } + #elif ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 0)) + if((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21) + { + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000011U); /* OTLINT-5579: V4H DBSC W/A-3 */ + } + else + { + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); + } + #else + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); + #endif +#elif (RCAR_LSI == RCAR_V4M) + # if (ECC_ENABLE == 1) + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000012U); + #else + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); + # endif +#endif + + mem_write32((DBSC_DBSCHCNT0 + (DBSC_A_CH_OFFSET * loop)), 0x000F0037U); /* dbschcnt0 */ + mem_write32((DBSC_DBSCHSZ0 + (DBSC_A_CH_OFFSET * loop)), 0x00000001U); /* dbschsz0 */ + mem_write32((DBSC_DBSCHRW0 + (DBSC_A_CH_OFFSET * loop)), 0xF7311111U); /* dbschrw0 */ + mem_write32((DBSC_SCFCTST2 + (DBSC_A_CH_OFFSET * loop)), 0x111F1FFFU); + +#if (((RCAR_LSI == RCAR_V4H) && (WA_OTLINT5579 == 1)) || (RCAR_LSI == RCAR_V4M)) + mem_write32((DBSC_DBBUS0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x00000007U); /* OTLINT-5579: V4H DBSC WA3 */ +#else + mem_write32((DBSC_DBBUS0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x00000003U); /* S4, V4H w/o DBSC WA3 */ +#endif + + /* DBSC QoS Setting */ + mem_write32((DBSC_DBSCHQOS_0_0 + (DBSC_A_CH_OFFSET * loop)), 0x0000FFFFU); + mem_write32((DBSC_DBSCHQOS_0_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000480U); + mem_write32((DBSC_DBSCHQOS_0_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_0_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_4_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000400U); + mem_write32((DBSC_DBSCHQOS_4_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_4_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000200U); + mem_write32((DBSC_DBSCHQOS_4_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); + mem_write32((DBSC_DBSCHQOS_9_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_9_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000240U); + mem_write32((DBSC_DBSCHQOS_9_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_9_3 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U); + mem_write32((DBSC_DBSCHQOS_12_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000040U); + mem_write32((DBSC_DBSCHQOS_12_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000030U); + mem_write32((DBSC_DBSCHQOS_12_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000020U); + mem_write32((DBSC_DBSCHQOS_12_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); + mem_write32((DBSC_DBSCHQOS_13_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_13_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000240U); + mem_write32((DBSC_DBSCHQOS_13_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_13_3 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U); + mem_write32((DBSC_DBSCHQOS_14_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000200U); + mem_write32((DBSC_DBSCHQOS_14_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_14_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); + mem_write32((DBSC_DBSCHQOS_14_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000080U); + mem_write32((DBSC_DBSCHQOS_15_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); + mem_write32((DBSC_DBSCHQOS_15_1 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U); + mem_write32((DBSC_DBSCHQOS_15_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000080U); + mem_write32((DBSC_DBSCHQOS_15_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000040U); + if (loop == 0) /* Target register is only DBSC0 side. */ + { + mem_write32(DBSC_FCPRSCTRL, 0x00000001U); + } + mem_write32((DBSC_SYSCNT1 + (DBSC_A_CH_OFFSET * loop)), 0x00000001U); + mem_write32((DBSC_SYSCNT0 + (DBSC_D_CH_OFFSET * loop)), 0x00000000U); + mem_write32((DBSC_SYSCNT0A + (DBSC_A_CH_OFFSET * loop)), 0x00000000U); + } +} +/* End of function dbsc_setting(void) */ + +void qos_init(void) +{ + uint32_t i; + + /* Setting the register of DBSC4 for QoS initialize */ + dbsc_setting(); + + NOTICE("QoS setting(%s)\n", RCAR_QOS_VERSION); + NOTICE("DRAM refresh interval 1.91 usec\n"); + +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE + NOTICE("Periodic Write DQ Training\n"); +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + +#if (RCAR_LSI == RCAR_S4) + /* Resource Alloc setting */ + mem_write32(QOS_RAS, 0x00000028U); + mem_write32(QOS_DANN_LOW, 0x02020201U); + mem_write32(QOS_DANN_HIGH, 0x04040200U); + mem_write32(QOS_DANT, 0x00181004U); + mem_write32(QOS_EMS_LOW, 0x00000000U); + mem_write32(QOS_EMS_HIGH, 0x00000000U); + mem_write32(QOS_FSS, 0x0000000AU); + mem_write32(QOS_INSFC, 0x030F0001U); + mem_write32(QOS_EARLYR, 0x00000000U); + mem_write32(QOS_RACNT0, 0x00050003U); + mem_write32(QOS_STATGEN0, 0x00000000U); + + /* QoS MSTAT setting */ + mem_write32(QOS_SL_INIT, 0x00050100U); + mem_write32(QOS_REF_ARS, 0x00FB0000U); + mem_write32(QOS_REF_ENBL, 0x00000012U); + mem_write32(QOS_BWG, 0x00000002U); + mem_write32(AXMM_MMCR, 0x00010000U); + + mem_write32(CCIQOS00, 0x08000000); + mem_write32(CCIQOS01, 0x08000000); + mem_write32(CCIQOS10, 0x00000001); + mem_write32(CCIQOS11, 0x00000001); + mem_write32(CCIQOS12, 0x00000001); + mem_write32(CCIQOS13, 0x00000001); +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + #if (RCAR_LSI == RCAR_V4H) + #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_ENABLE) + /* Address Split 2ch */ + mem_write32(AXMM_ADSPLCR0, 0x00000000U); + mem_write32(AXMM_ADSPLCR1, 0x00FF1B0CU); + mem_write32(AXMM_ADSPLCR2, 0x00000000U); + mem_write32(AXMM_ADSPLCR3, 0x00000000U); + #endif +#endif + +#if (RCAR_LSI == RCAR_V4H) + mem_write32(CCIQOS00, 0x08000000); + mem_write32(CCIQOS01, 0x08000000); + if ((mem_read32(PRR) & PRR_CUT_MASK) >= PRR_PRODUCT_20) + { + mem_write32(CCIQOS10, 0x00000001U); + mem_write32(CCIQOS11, 0x00000001U); + } + else + { + mem_write32(CCIQOS10, 0x00000000U); + mem_write32(CCIQOS11, 0x00000000U); + } + #endif + /* Resource Alloc setting */ +#if (RCAR_LSI == RCAR_V4H) + mem_write32(QOS_RAS, 0x00000048U); +#elif (RCAR_LSI == RCAR_V4M) + mem_write32(QOS_RAS, 0x00000030U); +#endif + mem_write32(QOS_DANN_LOW, 0x02020201U); + mem_write32(QOS_DANN_HIGH, 0x04040200U); + mem_write32(QOS_DANT, 0x00181008U); + mem_write32(QOS_EMS_LOW, 0x00000000U); + mem_write32(QOS_EMS_HIGH, 0x00000000U); + mem_write32(QOS_FSS, 0x0000000AU); + mem_write32(QOS_INSFC, 0x030F0001U); + mem_write32(QOS_EARLYR, 0x00000000U); + mem_write32(QOS_RACNT0, 0x00050003U); + mem_write32(QOS_STATGEN0, 0x00000000U); + + /* QoS MSTAT setting */ + mem_write32(QOS_SL_INIT, 0x00070120U); + mem_write32(QOS_REF_ARS, 0x011B0000U); + mem_write32(QOS_REF_ENBL, 0x00000012U); + mem_write32(QOS_BWG, 0x00000004U); + #if ((RCAR_LSI == RCAR_V4H) && (WA_OTLINT5579 == 1)) + if ((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21) + { + mem_write32(AXMM_MMCR, 0x00000000U); /* OTLINT-5579: V4H DBSC WA3 */ + } + else + { + mem_write32(AXMM_MMCR, 0x00010000U); /* OTLINT-5579: V4H DBSC WA3 */ + } + #elif (RCAR_LSI == RCAR_V4M) + mem_write32(AXMM_MMCR, 0x00010000U); + #else + mem_write32(AXMM_MMCR, 0x00010000U); + #endif + mem_write32(ACTEXT_RT0_R, 0x00000003U); + mem_write32(ACTEXT_RT0_W, 0x00000003U); + mem_write32(ACTEXT_IR0_R, 0x00000003U); + mem_write32(ACTEXT_IR0_W, 0x00000003U); + mem_write32(ACTEXT_IR1_R, 0x00000003U); + mem_write32(ACTEXT_IR1_W, 0x00000003U); +#if (RCAR_LSI == RCAR_V4H) + mem_write32(AXMM_TR3CR, 0x00010000U); +#endif + +#if (RCAR_LSI == RCAR_V4M) + mem_write32(AXMM_TR0CR0, 0x00000000U); + mem_write32(AXMM_TR1CR0, 0x00000000U); + mem_write32(AXMM_TR2CR0, 0x00000000U); + mem_write32(AXMM_TR3CR0, 0x00000000U); + mem_write32(AXMM_TR0CR1, 0x70707070U); + mem_write32(AXMM_TR1CR1, 0x70707070U); + mem_write32(AXMM_TR2CR1, 0x70707070U); + mem_write32(AXMM_TR3CR1, 0x70707070U); + mem_write32(AXMM_TR0CR2, 0x70707070U); + mem_write32(AXMM_TR1CR2, 0x70707070U); + mem_write32(AXMM_TR2CR2, 0x70707070U); + mem_write32(AXMM_TR3CR2, 0x70707070U); +#endif + + +#if (RCAR_LSI == RCAR_V4H) + if ((mem_read32(PRR) & PRR_CUT_MASK) >= PRR_PRODUCT_20) + { + /* WA1 patch for IPL CA76 hang-up issue, REL_TRI_DN-7592 */ + mem_write32(SI0_RW_MAX, 0x00000038U); + mem_write32(SI1_RW_MAX, 0x00000038U); + } +#endif + +#endif /* RCAR_LSI == RCAR_S4 */ + + for (i = 0U; i < QOS_TBL_MAX; i++) + { + mem_write64((QOS_FIX_QOS_BANK0 + (i * 8U)), g_qosbw_tbl[i].fix); + mem_write64((QOS_FIX_QOS_BANK1 + (i * 8U)), g_qosbw_tbl[i].fix); + mem_write64((QOS_BE_QOS_BANK0 + (i * 8U)), g_qosbw_tbl[i].be); + mem_write64((QOS_BE_QOS_BANK1 + (i * 8U)), g_qosbw_tbl[i].be); + } + +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE + for (i = 0U; i < QOS_TBL_MAX; i++) + { + mem_write64((QOSWT_FIX_QOS_BANK0 + (i * 8U)), g_qoswt_tbl[i].fix); + mem_write64((QOSWT_FIX_QOS_BANK1 + (i * 8U)), g_qoswt_tbl[i].fix); + mem_write64((QOSWT_BE_QOS_BANK0 + (i * 8U)), g_qoswt_tbl[i].be); + mem_write64((QOSWT_BE_QOS_BANK1 + (i * 8U)), g_qoswt_tbl[i].be); + } +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + + /* QoS SRAM setting */ + mem_write32(QOS_RAEN, 0x00000001U); +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE + mem_write32(QOSWT_WTREF, 0x02080208U); + mem_write32(QOSWT_WTSET0, 0x0D90050FU); + mem_write32(QOSWT_WTSET1, 0x0D90050FU); + mem_write32(QOSWT_WTEN, 0x00000001U); +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + mem_write32(QOS_STATQC, 0x00000101U); +} +/* End of function qos_init(void) */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/rtvram/rtvram.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/rtvram/rtvram.c new file mode 100644 index 0000000..ae64c17 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/rtvram/rtvram.c @@ -0,0 +1,81 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-VRAM driver + ******************************************************************************/ +/****************************************************************************** + * @file RTVRAM.c + * - Version : 0.03 + * @brief RT-VRAM driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 17.11.2021 0.01 First Release + * : 03.12.2021 0.02 remove Cache flush. + * : 06.01.2022 0.03 Static analysis support + *****************************************************************************/ + +#if defined(__RH850G3K__) +#include +#else +#include +#endif +#include +#include +#include +#include + +#define RTVRAM_VBUF_CFG_CACHE_MODE_8WAY (1U << 8U) +#define RTVRAM_VBUF_CFG_VBUF_SIZE_28M (6U << 0U) + +#define RTVRAM_EXT_MODE_EXT (1U << 0U) + +#define RTVRAM_VBUF_NUM (7U) + +#define RTVRAM_EXTEND_ENABLE (1U) + +void rtvram_extendmode(void) +{ +#if (RTVRAM_EXTEND == RTVRAM_EXTEND_ENABLE) + uint32_t reg; + uint32_t loop; + + /* Set each 4MB from the top of SDRAM as the buffer area of RT-VRAM. */ + for(loop = 0; loop < RTVRAM_VBUF_NUM; loop++) + { + mem_write32(get_vbuf_baddr_addr(loop), (uint32_t)((SDRAM_40BIT_ADDR_TOP + (RTVRAM_VBUF_AREA_SIZE * loop)) >> 16U)); + } + + reg = mem_read32(RTVRAM_VBUF_CFG); + reg |= (RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | RTVRAM_VBUF_CFG_VBUF_SIZE_28M); /* Cache Mode: 8-way, VBF size: 28M */ + mem_write32(RTVRAM_VBUF_CFG, reg); + + /* Set at the end */ + mem_write32(RTVRAM_EXT_MODE, RTVRAM_EXT_MODE_EXT); /* Change from Compatible Mode to Extended Mode */ + + syncm(); +#endif +} +/* End of function rtvram_extendmode(void) */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/ip/swdt/swdt.c b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/swdt/swdt.c new file mode 100644 index 0000000..c2f776c --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/ip/swdt/swdt.c @@ -0,0 +1,123 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Watchdog Timer function + ******************************************************************************/ +/****************************************************************************** + * @file swdt.c + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 12.08.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. +*****************************************************************************/ +#include "mem_io.h" +#include "rcar_def.h" +#include "rcar_register.h" +#include "swdt.h" +#include "gic.h" +#include "log.h" +#include "ip_control.h" + +void swdt_init(void) +{ + uint32_t sr; + uint32_t reg; + uint32_t val; + uint32_t chk_data; + + /* 1. Clear the TME bit in SWTCSRA to 0 to temporarily stop counting. */ + reg = mem_read32(SWDT_WTCSRA) & WTCSRA_TME; + if (WTCSRA_TME == reg) + { + mem_write32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE); + } + + /* 2.Write the set value in SWTCNT */ + /* OSCCLK check */ + reg = mem_read32(RST_MODEMR0); + chk_data = reg & CHECK_MD13_MD14; + + val = WTCNT_UPPER_BYTE; + + if (MD14_MD13_TYPE_0 == chk_data) + { + val |= SWDTCNT_133330HZ; + } + else if(MD14_MD13_TYPE_1 == chk_data) + { + val |= SWDTCNT_131570HZ; + } + else if(MD14_MD13_TYPE_3 == chk_data) + { + val |= SWDTCNT_131570HZ; + } + else + { + ERROR("MODEMR ERROR value = 0x%x\n", chk_data); + panic; + } + + mem_write32(SWDT_WTCNT, val); + + /* 3. Clear the bit4(WOVF) in SWTCSRA to 0. */ + mem_write32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE | WTCSRA_WOVFE | WTCSRA_CKS0_OSCCLK); + + /* 5.Confirm that SWTCSRA.WRFLG becomes 0.*/ + while (true) + { + if ((mem_read32(SWDT_WTCSRA) & WTCSRA_WRFLG) == 0U) + { + break; + } + } + + /* 6. Start the counting by setting the TME bit in SWTCSRA to 1. */ + sr = mem_read32(SWDT_WTCSRA) & WTCSRA_MASK_ALL; + + mem_write32(SWDT_WTCSRA, (WTCSRA_UPPER_BYTE | sr | WTCSRA_TME)); + +} +/* End of function swdt_init(void) */ + +void swdt_release(void) +{ + + mem_write32(SWDT_WTCSRA, WTCSRA_INIT_DATA); + mem_write32(SWDT_WTCNT, WTCNT_INIT_DATA); +} +/* End of function swdt_release(void) */ + +void swdt_exec(void) +{ + ERROR("System Watchdog Timer overflow.\n"); + panic; +} +/* End of function swdt_exec(void) */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/loader/asm_macros.S b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/asm_macros.S new file mode 100644 index 0000000..952a364 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/asm_macros.S @@ -0,0 +1,55 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : macro + ******************************************************************************/ +/****************************************************************************** + * @file asm_macros.S + * - Version : 0.03 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 07.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + * : 17.02.2023 0.03 Modified instruction to lower case. + *****************************************************************************/ +#ifndef ASM_MACROS_S +#define ASM_MACROS_S + + .macro mov_imm _reg, _val + .if (\_val) > 65535 + mov \_reg, (\_val >> 0) & 0xffff + movk \_reg, (\_val >> 16) & 0xffff, lsl #16 + movk \_reg, (\_val >> 32) & 0xffff, lsl #32 + movk \_reg, (\_val >> 48) & 0xffff, lsl #48 + .else + mov \_reg, (\_val) + .endif + .endm + +#endif /* ASM_MACROS_S */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_exceptions.S b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_exceptions.S new file mode 100644 index 0000000..025bb8f --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_exceptions.S @@ -0,0 +1,207 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file loader_exceptions.S + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.08.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ +#define SYNC_SP_EL0 (0x0U) +#define IRQ_SP_EL0 (0x1U) +#define FIQ_SP_EL0 (0x2U) +#define SERROR_SP_EL0 (0x3U) +#define SYNC_SP_ELX (0x4U) +#define IRQ_SP_ELX (0x5U) +#define FIQ_SP_ELX (0x6U) +#define SERROR_SP_ELX (0x7U) +#define SYNC_AARCH64 (0x8U) +#define IRQ_AARCH64 (0x9U) +#define FIQ_AARCH64 (0xAU) +#define SERROR_AARCH64 (0xBU) +#define SYNC_AARCH32 (0xCU) +#define IRQ_AARCH32 (0xDU) +#define FIQ_AARCH32 (0xEU) +#define SERROR_AARCH32 (0xFU) + + .global loader_exceptions + .global SyncSP0 + .global IrqSP0 + .global FiqSP0 + .global SErrorSP0 + .global SyncSPx + .global IrqSPx + .global FiqSPx + .global SErrorSPx + .global SyncA64 + .global IrqA64 + .global FiqA64 + .global SErrorA64 + .global SyncA32 + .global IrqA32 + .global FiqA32 + .global SErrorA32 + + /* Pre macro for a vector */ + .macro bigin_vector label, section_name=.vectors + .cfi_sections .debug_frame + .section \section_name, "ax" + .align 7, 0 + .type \label, %function + .cfi_startproc + \label: + .endm + + /* Post macro for a vector */ + .macro end_vector label + .cfi_endproc + .fill \label + (32 * 4) - . + .endm + + +/*****************************************************************************/ +/* Exception Vector Table */ +/*****************************************************************************/ + .section .vectors, "ax" + .align 11, 0 + +loader_exceptions: + + /***********************/ + /* Current EL with SP0 */ + /***********************/ +bigin_vector SyncSP0 + mov x0, #SYNC_SP_EL0 + msr spsel, #0 + bl handler_error +end_vector SyncSP0 + +bigin_vector IrqSP0 + mov x0, #IRQ_SP_EL0 + msr spsel, #0 + bl handler_error +end_vector IrqSP0 + +bigin_vector FiqSP0 + mov x0, #FIQ_SP_EL0 + msr spsel, #0 + b handler_fiq +end_vector FiqSP0 + +bigin_vector SErrorSP0 + mov x0, #SERROR_SP_EL0 + msr spsel, #0 + bl handler_error +end_vector SErrorSP0 + + /***********************/ + /* Current EL with SPx */ + /***********************/ +bigin_vector SyncSPx + mov x0, #SYNC_SP_ELX + msr spsel, #0 + bl handler_error +end_vector SyncSPx + +bigin_vector IrqSPx + mov x0, #IRQ_SP_ELX + msr spsel, #0 + bl handler_error +end_vector IrqSPx + +bigin_vector FiqSPx + mov x0, #FIQ_SP_ELX + msr spsel, #0 + bl handler_error +end_vector FiqSPx + +bigin_vector SErrorSPx + mov x0, #SERROR_SP_ELX + msr spsel, #0 + bl handler_error +end_vector SErrorSPx + + /**************************/ + /* Lower EL using AArch64 */ + /**************************/ +bigin_vector SyncA64 + mov x0, #SYNC_AARCH64 + msr spsel, #0 + bl handler_error +end_vector SyncA64 + +bigin_vector IrqA64 + mov x0, #IRQ_AARCH64 + msr spsel, #0 + bl handler_error +end_vector IrqA64 + +bigin_vector FiqA64 + mov x0, #FIQ_AARCH64 + msr spsel, #0 + bl handler_error +end_vector FiqA64 + +bigin_vector SErrorA64 + mov x0, #SERROR_AARCH64 + msr spsel, #0 + bl handler_error +end_vector SErrorA64 + + /**************************/ + /* Lower EL using AArch32 */ + /**************************/ +bigin_vector SyncA32 + mov x0, #SYNC_AARCH32 + msr spsel, #0 + bl handler_error +end_vector SyncA32 + +bigin_vector IrqA32 + mov x0, #IRQ_AARCH32 + msr spsel, #0 + bl handler_error +end_vector IrqA32 + +bigin_vector FiqA32 + mov x0, #FIQ_AARCH32 + msr spsel, #0 + bl handler_error +end_vector FiqA32 + +bigin_vector SErrorA32 + mov x0, #SERROR_AARCH32 + msr spsel, #0 + bl handler_error +end_vector SErrorA32 + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_main.c b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_main.c new file mode 100644 index 0000000..6a48982 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_main.c @@ -0,0 +1,575 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Loader main function + ******************************************************************************/ +/****************************************************************************** + * @file loader_main.c + * - Version : 0.17 + * @brief 1. IP initialization. + * 2. Transfer image. + * 3. Release of used resources. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 30.11.2021 0.01 First Release + * : 14.02.2022 0.02 Changed log output + * Added device version log output + * Removed Include in micro_wait.h + * Removed the parameter setting process to BL31 + * Removed LCS judgement + * Memory map change + * : 17.02.2022 0.03 Support AArch32 + * : 22.03.2022 0.04 Support for GSCE[5.4a, 5.4b],[10.3b] + * Support for coverity + * cid:3430806, 3307617, 3430797 + * Changed comment + * : 10.05.2022 0.05 Integrated processing + * Changed to processing for each device + * Change log output + * Add argument of load_init() + * : 16.06.2022 0.06 Change log output + * Support secure boot for S4 + * : 31.10.2022 0.07 License notation change. + * : 07.11.2022 0.08 Added the parameter setting process to BL31 + * Added DDR initialization/QOS initialization + * : 07.12.2022 0.09 Warning support when log output is disabled + * : 15.12.2022 0.10 Support RegionID check + * : 04.04.2023 0.11 Removed stdio.h. + * : 21.08.2023 0.12 Add support for V4M. + * : 23.01.2024 0.13 Add calling of ram_protection_check function. + * Move calling of final_hash_cmp function. + * : 10.09.2024 0.14 Updated Region ID and RAM protection setting + * for QNX. + * : 11.10.2024 0.15 Updated Region ID and RAM protection setting + * for QNX for V4M. + * : 19.12.2024 0.16 Add loading RTOS#1 and RTOS#2 process. + * Add calling ecm_error_enable() function. + * : 26.05.2025 0.17 Add argument of OP-TEE boot address to + * smoni_set_param function. +*****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#include "cpu_on.h" +#include "qos.h" +#include "rtvram.h" +#include "loader_main_common.h" +#include "../ip/ddr/boot_init_dram.h" +#include "access_protection.h" +#if (ECC_ENABLE == 1) +#if (RCAR_LSI == RCAR_V4H) +#include "../ip/ddr/v4h/lpddr5/ecc_enable_v4h.h" +#elif (RCAR_LSI == RCAR_V4M) +#include "../ip/ddr/v4m/lpddr5/ecc_enable_v4m.h" +#endif /* RCAR_LSI == RCAR_V4H */ +#endif /* ECC_ENABLE == 1 */ +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ +#if (BOOT_MODE == SECURE) +#include "secure_boot.h" +#endif /* BOOT_MODE == SECURE */ +/* Time analysis */ +#if (1 == (MEASURE_TIME)) + #include + #include +#else + #define scmt_wait_ticks(x) + #define store_time_checkpoint(x,y) + #define print_time_checkpoints(x) +#endif +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +#include "axmm_register.h" +#include "ram_protection.h" +#endif +#if (ECM_ERROR_ENABLE == 1) +#if (RCAR_LSI == RCAR_V4H) +#include "../ip/ddr/v4h/lpddr5/ecm_enable_v4h.h" +#elif (RCAR_LSI == RCAR_V4M) +#include "../ip/ddr/v4m/lpddr5/ecm_enable_v4m.h" +#endif /* RCAR_LSI == RCAR_V4H */ +#endif /* ECM_ERROR_ENABLE == 1 */ +#include +#include +#include + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +#define AXMM_DPTSECCR_NUM (SDRAM_PROTECT_AREA) /* set 0 to 15 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) +#define AXMM_DPTSECCR_NUM2 (SDRAM_PROTECT_AREA2) /* set 0 to 15 */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ + +#define AXMM_DPTSECCR_SECGRP_MASK (0x00000F00U) +#define AXMM_DPTSECCR_SECGRP_SEC (0x00000400U) +#define AXMM_DPTSECCR_SECGWP_MASK (0x0000000FU) +#define AXMM_DPTSECCR_SECGWP_SEC (0x00000004U) + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define DPTRGNCR_PROTECT_AREA (3U) +#define DPTRGNCR_LINUX_AREA (6U) +#else +#define DPTRGNCR_PROTECT_AREA (4U) +#define DPTRGNCR_LINUX_AREA (9U) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#define SECCTRWD_AREA0 (0U) +#define SECCTRWD_AREA2 (2U) + +#define AXMM_DPTRGNCR_RGN0RP_MASK (0x00010000U) +#define AXMM_DPTRGNCR_RGN0RP (0x00010000U) +#define AXMM_DPTRGNCR_RGN0WP_MASK (0x00000001U) +#define AXMM_DPTRGNCR_RGN0WP (0x00000001U) +#define SECCTRWD_SAFG15WP_MASK (0x00000005U) +#define SECCTRWD_SAFG15WP (0x00000005U) + +static void remove_rgid0_previlege(void); +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +static void sdram_protection(uint32_t num); +#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ + +uint32_t loader_main(void) +{ + uint32_t ca_load_num; /* number of load for CA program */ + uint32_t loop; + uint32_t reg; /* store register value */ +#ifdef MOBIS_PRK3 + int slot = 0; +#endif +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + int32_t result; /* store result of ddr_init() */ +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + + __attribute__((unused))const char *str; +#if (RCAR_LSI == RCAR_S4) + const char *product_s4 = "S4"; +#elif (RCAR_LSI == RCAR_V4H) + const char *product_v4h = "V4H"; +#elif (RCAR_LSI == RCAR_V4M) + const char *product_v4m = "V4M"; +#endif /* RCAR_LSI == RCAR_S4 */ + const char *unknown = "unknown"; +#if (BOOT_MODE == SECURE) + uint32_t bootmode; /* store boot mode */ +#endif /* BOOT_MODE == SECURE */ + + LOAD_INFO li[MAX_PLACED]; + +#if (1 == (MEASURE_TIME)) + scmt_module_start(); + store_time_checkpoint("loader_main", 0); +#endif +/***************************************************************************** + * Initialize Hardware + *****************************************************************************/ + /* IP initialize */ + ip_init(); + +/***************************************************************************** + * Output boot message + *****************************************************************************/ +#if (RCAR_LSI == RCAR_S4) + NOTICE("CA55 Loader Program Rev.%s\n", IPL_VERSION); +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + NOTICE("CR52 Loader Program Rev.%s\n", IPL_VERSION); +#endif /* RCAR_LSI == RCAR_S4 */ + + NOTICE("%s\n", build_message); + + /* Get PRR */ + reg = mem_read32(PRR); + switch (reg & PRR_PRODUCT_MASK) + { + #if (RCAR_LSI == RCAR_S4) + case PRR_PRODUCT_S4: + { + str = product_s4; + break; + } + #elif (RCAR_LSI == RCAR_V4H) + case PRR_PRODUCT_V4H: + { + str = product_v4h; + break; + } + #elif (RCAR_LSI == RCAR_V4M) + case PRR_PRODUCT_V4M: + { + str = product_v4m; + break; + } + #endif /* RCAR_LSI == RCAR_S4 */ + default: + { + str = unknown; + break; + } + } + NOTICE("PRR is R-Car %s Ver.%d.%d\n", str, + ((int)(reg & PRR_MAJOR_MASK) >> PRR_MAJOR_SHIFT) + + PRR_MAJOR_OFFSET, (int)(reg & PRR_MINOR_MASK)); + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + /* Notice the ecc enable */ + NOTICE("Access Protection Enable\n"); + #endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + store_time_checkpoint("init_done", 0); + +/***************************************************************************** + * DDR Initialization + *****************************************************************************/ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + + /* DDR initialize */ + result = R_DRAM_Init(); + if (INITDRAM_OK != result) + { + ERROR("Failed to DRAM initialize (%d).\n", (int)result); + panic; + } + +#if (ECM_ERROR_ENABLE == 1) + ecm_error_enable(); +#endif /* ECM_ERROR_ENABLE == 1 */ + +#if (ECC_ENABLE == 1) + /* ECC Protection */ + ecc_sdram_enable(); +#endif /* ECC_ENABLE == 1 */ + + /* QoS configuration */ + qos_init(); + + /* RT-VRAM Extend mode */ + rtvram_extendmode(); + + /* memory copy */ + memcpy((void *)DISK_BUFFER_ADDR, (void *)DISK_BUFFER__IPL, 4096); + memset((void *)DISK_BUFFER__IPL, 0xFF, 4096); + memcpy((void *)AB_INFO_FLAG_ADDR, (void *)AB_INFO_FLAG__IPL, 4); + memset((void *)AB_INFO_FLAG__IPL, 0xFF, 4); +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + store_time_checkpoint("DDR_and_Bus_init_done", 0); + +/***************************************************************************** + * Load Certficate + *****************************************************************************/ + + /* Load content certificate */ + ca_load_num = mem_read32(CONTENT_CERT_DEST_ADDR); + + /* Get load information */ + load_init(li, ca_load_num); + +#if (BOOT_MODE == SECURE) +/***************************************************************************** + * Check SecureBoot + *****************************************************************************/ + secureboot_init(); + + /* LCS judgement for secure boot */ + bootmode = judge_bootmode(); + + if (NORMAL_BOOT != bootmode) + { + /* Content cert certification */ +#if (BL2_LOAD_ENABLE == BL2_DISABLE) + secureboot_verify(li, CA_OPTIONAL_ID, CA_OPTIONAL_ID + ca_load_num); +#else + secureboot_verify(li, CA_BL2_ID, CA_BL2_ID + 1); +#endif + store_time_checkpoint("verify_cert_done", 0); + } +#endif /* BOOT_MODE == SECURE */ + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/***************************************************************************** + * Load RTOS#2 + *****************************************************************************/ + /* Start loading RTOS#2 image */ + load_image(&li[RTOS2_ID]); + store_time_checkpoint("load_RTOS#2_done", li[RTOS2_ID].image_size); + + #if (BOOT_MODE == SECURE) + /* Decryption image and Image cerfification */ + if (NORMAL_BOOT != bootmode) + { + secureboot_image(&li[RTOS2_ID], 1); + store_time_checkpoint("verify_RTOS#2_done", 0); + } + #endif /* BOOT_MODE == SECURE */ + + /* boot CR core2 */ + arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS2_ID].boot_addr, 2); + store_time_checkpoint("started_RTOS#2", 0); +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +/***************************************************************************** + * Load RTOS#0 + *****************************************************************************/ +#define _IPL_END (0xEB22FFF4) +#ifdef MOBIS_PRK3 + emmc_initialize(); + store_time_checkpoint("emmc_initialize", 0); +#if (BL2_LOAD_ENABLE == BL2_ENABLE) /* do not clear eMMC */ + export_mmc_drv_obj(); +#endif + + reg = mem_read32(AB_INFO_FLAG_ADDR); + if (reg & AB_INFO_SELECT_2nd) + slot = 1; + // slot = ab_select_slot(); + load_update_part_num(li, ca_load_num, slot); + NOTICE("slot: %d\n", slot); + + mem_write32(_IPL_END, 0x0); +#endif + + /* Start loading RTOS#0 image */ + load_image(&li[RTOS_ID]); + store_time_checkpoint("load_RTOS#0_done", li[RTOS_ID].image_size); + + #if (BOOT_MODE == SECURE) + /* Decryption image and Image cerfification */ + if (NORMAL_BOOT != bootmode) + { + /* WARNING! WARNING! WARNING! WARNING! */ + /* TODO: set 1 to panic! later */ + secureboot_image(&li[RTOS_ID], 0); + store_time_checkpoint("verify_RTOS#0_done", 0); + } + #endif /* BOOT_MODE == SECURE */ + + /* boot CR core0 */ + arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr, -1); + +#ifdef MOBIS_PRK3 + /* enable CR-52 Core 2 */ + arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr, 2); + store_time_checkpoint("started_RTOS#0", 0); +#endif +#if (BOOT_TIME_CHECK != 0) + gpio_N1305(2); +#endif +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + +/***************************************************************************** + * Load CA Program#2--#8 + *****************************************************************************/ +#if (BL2_LOAD_ENABLE == BL2_DISABLE) + /* Start loading CA Program#n image */ + for (loop = 0U; loop < ca_load_num; loop++) +#else + /* load bl2 */ + loop = (CA_BL2_ID - CA_OPTIONAL_ID); +#endif + { + /* Loading start */ + NOTICE("Loading %s...\n", li[CA_OPTIONAL_ID + loop].name); + load_image(&li[CA_OPTIONAL_ID + loop]); + store_time_checkpoint("load_CA_#_done", li[CA_OPTIONAL_ID + loop].image_size); + +#if (BOOT_MODE == SECURE) + /* Decryption image and Image certification */ + if (NORMAL_BOOT != bootmode) + { + secureboot_image(&li[CA_OPTIONAL_ID + loop], 1); + store_time_checkpoint("verify_CA_#_done", 0); + } +#endif /* BOOT_MODE == SECURE */ + } + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + /* Set Secure Monitor parameter */ + #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + smoni_set_param(li[CA_OPTIONAL_ID].boot_addr, /* BL31 */ + li[CA_OPTIONAL_ID + 1U].boot_addr); /* U-Boot */ + #else + #if (BL2_LOAD_ENABLE == BL2_DISABLE) /* BL2 will load these */ + smoni_set_param(li[CA_OPTIONAL_ID].boot_addr, /* BL31 */ + li[CA_OPTIONAL_ID + 1U].boot_addr, /* U-Boot */ + li[CA_OPTIONAL_ID + 2U].boot_addr); /* OP-TEE */ + #endif + #endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + + /* Before Boot CPU, Set the division ratio for CPU operating frequency */ + adj_ca_variant_freq(); + +/* boot CA */ +#if (BL2_LOAD_ENABLE == BL2_DISABLE) + arm_cpu_on(RCAR_PWR_TARGET_CA, li[CA_OPTIONAL_ID].boot_addr, -1); +#else /* run BL2, not BL31 */ + arm_cpu_on(RCAR_PWR_TARGET_CA, li[CA_BL2_ID].boot_addr, -1); +#endif + store_time_checkpoint("started_CA_core", 0); + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/***************************************************************************** + * Load RTOS#1 + *****************************************************************************/ + /* Start loading RTOS#1 image */ + load_image(&li[RTOS1_ID]); + store_time_checkpoint("load_RTOS#1_done", li[RTOS1_ID].image_size); + + #if (BOOT_MODE == SECURE) + /* Decryption image and Image cerfification */ + if (NORMAL_BOOT != bootmode) + { + secureboot_image(&li[RTOS1_ID], 1); + store_time_checkpoint("verify_RTOS#1_done", 0); + } + #endif /* BOOT_MODE == SECURE */ + +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + + #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + sdram_protection(AXMM_DPTSECCR_NUM); + #if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) + sdram_protection(AXMM_DPTSECCR_NUM2); + #endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ + remove_rgid0_previlege(); + /* + * SAN(Safety Application Note) 6.23.5 Operation + * Checker processor : + * Check RegionID/LifeC & memory area protection settings (including order & content of intermediate updates) + * done by ICUMX. + */ + rgid_protection_check(); + ram_protection_check(); + #endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ + + #if (BOOT_MODE == SECURE) + if (NORMAL_BOOT != bootmode) + { + /* Compare Hash verified at ICUMX IPL (V4H only). (Target images are Secure FW and Cx 2nd IPL.) */ + /* + * SAN(Safety Application Note) 6.23.5 Operation + * Checker processor : + * Re-do comparison of hash in Flash vs hash generated by ICUMX to confirm proper comparison. + */ + final_hash_cmp(); + store_time_checkpoint("final_verify_done", 0); + } + #endif /* BOOT_MODE == SECURE */ + + NOTICE("Load finish.(CR52 Loader)\n"); + +#elif (RCAR_LSI == RCAR_S4) + #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + sdram_protection(AXMM_DPTSECCR_NUM); + #endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ + NOTICE("Load finish.(CA55 Loader)\n"); +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + // ip_release(); + + store_time_checkpoint("Cx_done_starting_RTOS#1", 0); + // scmt_wait_ticks(SCMT_MS2TICKS(1000)); + print_time_checkpoints(); +#if (BOOT_TIME_CHECK != 0) + gpio_N1305(2); +#endif + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1) + #ifdef MOBIS_PRK3 + return li[RTOS_ID].boot_addr; + #else + return li[CA_OPTIONAL_ID].boot_addr; + #endif +#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + return li[RTOS1_ID].boot_addr; +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +} +/* End of function loader_main(void) */ + + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +static void sdram_protection(uint32_t num) +{ + uint32_t val; + uint32_t addr; + + /* Calculation of the address of the DPTSECCR register. */ + addr = (AXMM_DPTSECCR + (num * 4U)); + + val = mem_read32(addr); + val &= ~(AXMM_DPTSECCR_SECGRP_MASK | AXMM_DPTSECCR_SECGWP_MASK); + val |= (AXMM_DPTSECCR_SECGRP_SEC | AXMM_DPTSECCR_SECGWP_SEC); + mem_write32(addr, val); +}/* End of function void sdram_protection(void) */ + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +static void remove_rgid0_previlege(void) +{ + uint32_t val; + uint32_t addr; + + /* Calculation of the address of the DPTRGNCR register. */ + addr = get_dptrgncr_addr(DPTRGNCR_PROTECT_AREA); + + val = mem_read32(addr); + val &= ~(AXMM_DPTRGNCR_RGN0RP_MASK | AXMM_DPTRGNCR_RGN0WP_MASK); + val |= (AXMM_DPTRGNCR_RGN0RP| AXMM_DPTRGNCR_RGN0WP); /* Remove RGID0 read/write previlege on SDRAM Area. */ + mem_write32(addr, val); + + /* Calculation of the address of the DPTRGNCR register. */ + addr = get_dptrgncr_addr(DPTRGNCR_LINUX_AREA); + + val = mem_read32(addr); + val &= ~(AXMM_DPTRGNCR_RGN0RP_MASK | AXMM_DPTRGNCR_RGN0WP_MASK); + val |= (AXMM_DPTRGNCR_RGN0RP| AXMM_DPTRGNCR_RGN0WP); /* Remove RGID0 read/write previlege on SDRAM Area. */ + mem_write32(addr, val); + + /* Calculation of the address of the SECCTRW0D_1 register. */ + addr = get_rtvram1_secctrwd_addr(SECCTRWD_AREA0); + + val = mem_read32(addr); + val &= ~(SECCTRWD_SAFG15WP_MASK); + val |= SECCTRWD_SAFG15WP; /* Remove RGID0/2 write previlege on RT-VRAM1 Area0. */ + mem_write32(addr, val); + + /* Calculation of the address of the SECCTRW2D_1 register. */ + addr = get_rtvram1_secctrwd_addr(SECCTRWD_AREA2); + + val = mem_read32(addr); + val &= ~(SECCTRWD_SAFG15WP_MASK); + val |= SECCTRWD_SAFG15WP; /* Remove RGID0/2 write previlege on RT-VRAM1 Area2. */ + mem_write32(addr, val); +} +/* End of function void remove_rgid0_previlege(void) */ +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_main_common.c b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_main_common.c new file mode 100644 index 0000000..7563829 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_main_common.c @@ -0,0 +1,274 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main common function + ******************************************************************************/ +/****************************************************************************** + * @file loader_main_common.c + * - Version : 0.05 + * @brief 1.Set BL31 parameter. + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 15.11.2022 0.01 First Release + * : 04.04.2023 0.02 Removed stdio.h. + * : 13.09.2024 0.03 Updated smoni_ep_info->ulpc_high to 0x20, + * smoni_ipl_param->pnonsecepinfo_high to 0x20. + * : 11.10.2024 0.04 Updated Region ID and RAM protection setting + * for QNX for V4M. + * : 26.05.2025 0.05 Added optee_ep_info parameter. + *****************************************************************************/ + +#include +#include +#include +#include +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#include "access_protection.h" +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +#define SMONI_IPL_PARAM_OFFSET (0x00022200U) +#define SMONI_EP_INFO_OFFSET (SMONI_IPL_PARAM_OFFSET + 0x0030U) +#define OPTEE_EP_INFO_OFFSET (SMONI_IPL_PARAM_OFFSET + 0x0088U) +#define BL31_KIND_BOOT_ADDR (SMONI_IPL_PARAM_OFFSET + 0x0D00U) +#define BL31_COLD_BOOT (0x0000000000000000U) +#define BL31_WARM_BOOT (0x0000000000000001U) +#define SMONI_KIND_BOOT_PARAM (0xFFFFFFFFFFFFFFFFU) + +/* struct */ +typedef struct{ + uint8_t uctype; + uint8_t ucversion; + uint16_t ussize; + uint32_t uiattr; + uint32_t psecmonimageinfo_low; + uint32_t psecmonimageinfo_high; + uint32_t psecoptepinfo_low; + uint32_t psecoptepinfo_high; + uint32_t psecoptimageinfo_low; + uint32_t psecoptimageinfo_high; + uint32_t pnonsecepinfo_low; + uint32_t pnonsecepinfo_high; + uint32_t pnonsecimageinfo_low; + uint32_t pnonsecimageinfo_high; +}st_smoni_iplparams_t; + +typedef struct{ + uint8_t uctype; + uint8_t ucversion; + uint16_t ussize; + uint32_t uiattr; + uint32_t ulpc_low; + uint32_t ulpc_high; + uint32_t ulspsr_low; + uint32_t ulspsr_high; + uint32_t ularg0_low; + uint32_t ularg0_high; + uint32_t ularg1_low; + uint32_t ularg1_high; + uint32_t ularg2_low; + uint32_t ularg2_high; + uint32_t ularg3_low; + uint32_t ularg3_high; + uint32_t ularg4_low; + uint32_t ularg4_high; + uint32_t ularg5_low; + uint32_t ularg5_high; + uint32_t ularg6_low; + uint32_t ularg6_high; + uint32_t ularg7_low; + uint32_t ularg7_high; +}st_smoni_entrypointinfo_t; + +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + void smoni_set_param(uintptr_t smoni_entry_point, + uintptr_t uboot_entry_point) +#else +void smoni_set_param(uintptr_t smoni_entry_point, + uintptr_t uboot_entry_point, + uintptr_t tee_entry_point) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +{ + st_smoni_iplparams_t *smoni_ipl_param; + st_smoni_entrypointinfo_t *smoni_ep_info; +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) + st_smoni_entrypointinfo_t *optee_ep_info; +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ +#ifdef AARCH64 + union { + uintptr_t ptr; + struct { + uint32_t low; + uint32_t high; + } u32; + } _tmp; +#endif + + /* set struct address */ + smoni_ipl_param = (st_smoni_iplparams_t *) + (smoni_entry_point + SMONI_IPL_PARAM_OFFSET); + smoni_ep_info = (st_smoni_entrypointinfo_t *) + (smoni_entry_point + SMONI_EP_INFO_OFFSET); +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) + optee_ep_info = (st_smoni_entrypointinfo_t *) + (smoni_entry_point + OPTEE_EP_INFO_OFFSET); +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ + + /* set parameter */ + smoni_ipl_param->uctype = 0x03U; + smoni_ipl_param->ucversion = 0x01U; + smoni_ipl_param->ussize = 0x0030U; + smoni_ipl_param->uiattr = 0x00000000U; + smoni_ipl_param->psecmonimageinfo_low = 0x00000000U; + smoni_ipl_param->psecmonimageinfo_high = 0x00000000U; +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + smoni_ipl_param->psecoptepinfo_low = 0x00000000U; +#else + #ifdef AARCH64 + _tmp.ptr = (uintptr_t)optee_ep_info; + smoni_ipl_param->psecoptepinfo_low = _tmp.u32.low; + #else + smoni_ipl_param->psecoptepinfo_low = (uint32_t)optee_ep_info; + #endif +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + smoni_ipl_param->psecoptepinfo_high = 0x00000020U; /* OP-TEE entry point information 0x20_46422288 */ +#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE) + smoni_ipl_param->psecoptepinfo_high = 0x00000000U; +#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ +#else + smoni_ipl_param->psecoptepinfo_high = 0x00000000U; +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + smoni_ipl_param->psecoptimageinfo_low = 0x00000000U; + smoni_ipl_param->psecoptimageinfo_high = 0x00000000U; +#ifdef AARCH64 + _tmp.ptr = (uintptr_t)smoni_ep_info; + smoni_ipl_param->pnonsecepinfo_low = _tmp.u32.low; +#else + smoni_ipl_param->pnonsecepinfo_low = (uint32_t)smoni_ep_info; +#endif +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + smoni_ipl_param->pnonsecepinfo_high = 0x00000020U; /* Secure monitor entry point 0x20_XXXXXXXX */ + smoni_ipl_param->pnonsecepinfo_high = 0x00000020U; /* Secure monitor entry point 0x20_46400000 */ +#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE) + smoni_ipl_param->pnonsecepinfo_high = 0x00000000U; +#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ +#else + smoni_ipl_param->pnonsecepinfo_high = 0x00000000U; +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + smoni_ipl_param->pnonsecimageinfo_low = 0x00000000U; + smoni_ipl_param->pnonsecimageinfo_high = 0x00000000U; + + smoni_ep_info->uctype = 0x01U; + smoni_ep_info->ucversion = 0x01U; + smoni_ep_info->ussize = 0x0058U; /* structure size */ + smoni_ep_info->uiattr = 0x00000001U; /* SECURE */ +#ifdef AARCH64 + _tmp.ptr = (uintptr_t)uboot_entry_point; + smoni_ep_info->ulpc_low = _tmp.u32.low; +#else + smoni_ep_info->ulpc_low = uboot_entry_point; +#endif +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + smoni_ep_info->ulpc_high = 0x00000020U; /* U-boot entry point 0x20_50000000 */ +#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE) + smoni_ep_info->ulpc_high = 0x00000000U; +#endif +#else + smoni_ep_info->ulpc_high = 0x00000000U; +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + /* SPSR_EL3.E[9] = b1 (BigEndian) * + * .A[8] = b1 (DataAbort MASK) * + * .I[7] = b1 (IRQ MASK) * + * .F[6] = b1 (FIQ MASK) * + * .M[4] = b0 (AArcch64) * + * .M[3:1] = b0101 (EL1h) */ + smoni_ep_info->ulspsr_low = 0x000003C5U; + smoni_ep_info->ulspsr_high = 0x00000000U; + smoni_ep_info->ularg0_low = 0x00000000U; + smoni_ep_info->ularg0_high = 0x00000000U; + smoni_ep_info->ularg1_low = 0x00000000U; + smoni_ep_info->ularg1_high = 0x00000000U; + smoni_ep_info->ularg2_low = 0x00000000U; + smoni_ep_info->ularg2_high = 0x00000000U; + smoni_ep_info->ularg3_low = 0x00000000U; + smoni_ep_info->ularg3_high = 0x00000000U; + smoni_ep_info->ularg4_low = 0x00000000U; + smoni_ep_info->ularg4_high = 0x00000000U; + smoni_ep_info->ularg5_low = 0x00000000U; + smoni_ep_info->ularg5_high = 0x00000000U; + smoni_ep_info->ularg6_low = 0x00000000U; + smoni_ep_info->ularg6_high = 0x00000000U; + smoni_ep_info->ularg7_low = 0x00000000U; + smoni_ep_info->ularg7_high = 0x00000000U; + +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) + optee_ep_info->uctype = 0x01U; + optee_ep_info->ucversion = 0x02U; + optee_ep_info->ussize = 0x0058U; + optee_ep_info->uiattr = 0x00000008U; +#ifdef AARCH64 + _tmp.ptr = (uintptr_t)tee_entry_point; + optee_ep_info->ulpc_low = _tmp.u32.low; +#else + optee_ep_info->ulpc_low = tee_entry_point; +#endif +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + optee_ep_info->ulpc_high = 0x00000020U; /* OP-TEE entry point 0x20_44100000 */ +#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE) + optee_ep_info->ulpc_high = 0x00000000U; +#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ +#else + optee_ep_info->ulpc_high = 0x00000000U; +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + optee_ep_info->ulspsr_low = 0x000003C5U; + optee_ep_info->ulspsr_high = 0x00000000U; + optee_ep_info->ularg0_low = 0x00000000U; + optee_ep_info->ularg0_high = 0x00000000U; + optee_ep_info->ularg1_low = 0x00000000U; + optee_ep_info->ularg1_high = 0x00000000U; + optee_ep_info->ularg2_low = 0x00000000U; + optee_ep_info->ularg2_high = 0x00000000U; + optee_ep_info->ularg3_low = 0x00000000U; + optee_ep_info->ularg3_high = 0x00000000U; + optee_ep_info->ularg4_low = 0x00000000U; + optee_ep_info->ularg4_high = 0x00000000U; + optee_ep_info->ularg5_low = 0x00000000U; + optee_ep_info->ularg5_high = 0x00000000U; + optee_ep_info->ularg6_low = 0x00000000U; + optee_ep_info->ularg6_high = 0x00000000U; + optee_ep_info->ularg7_low = 0x00000000U; + optee_ep_info->ularg7_high = 0x00000000U; +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ + + smoni_entry_point += BL31_KIND_BOOT_ADDR; + mem_write32((smoni_entry_point), (uint32_t)((uint64_t)BL31_COLD_BOOT & 0xFFFFFFFFU)); + mem_write32(((smoni_entry_point) + 0x4U), + (uint32_t)(((uint64_t)BL31_COLD_BOOT >> 32U) & 0xFFFFFFFFU)); +} +/* End of function smoni_set_param(uint32_t smoni_entry_point) */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_mmu_table.c b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_mmu_table.c new file mode 100644 index 0000000..156212f --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_mmu_table.c @@ -0,0 +1,1086 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + +/******************************************************************************* + * DESCRIPTION : MMU Setting table level1 + ******************************************************************************/ +/****************************************************************************** + * @file loader_mmu_table1.c + * - Version : 0.02 + * @brief MMU setting table No.1. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 14.12.2022 0.01 First Release + * : 13.02.2023 0.02 Modify each table to be fixed address. + *****************************************************************************/ +#include /* for uint32_t */ +#include +#include "loader_mmu_table.h" + +/* Must match with MMU_LV2_STAT defined in loader_s4.ld. */ +#define MMU_TBL_ADDR (0xE6311000U) +/* Must match with MMU_LV3_STAT defined in loader_s4.ld. */ +#define MMU_TBL_SYSRAM_ADDR (0xE6310000U) + +const uint64_t g_loader_level3_table[] __attribute__ ((aligned (4096))) __attribute__ ((section(".lv3_tbl"))) = +{ + 0x00000000E6200000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6201000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6202000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6203000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6204000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6205000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6206000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6207000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6208000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6209000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E620A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E620B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E620C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E620D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E620E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E620F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6210000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6211000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6212000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6213000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6214000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6215000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6216000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6217000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6218000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6219000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E621A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E621B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E621C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E621D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E621E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E621F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6220000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6221000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6222000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6223000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6224000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6225000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6226000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6227000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6228000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6229000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E622A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E622B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E622C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E622D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E622E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E622F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6230000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6231000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6232000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6233000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6234000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6235000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6236000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6237000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6238000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6239000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E623A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E623B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E623C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E623D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E623E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E623F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6240000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6241000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6242000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6243000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6244000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6245000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6246000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6247000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6248000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6249000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E624A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E624B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E624C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E624D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E624E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E624F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6250000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6251000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6252000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6253000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6254000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6255000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6256000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6257000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6258000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6259000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E625A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E625B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E625C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E625D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E625E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E625F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6260000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6261000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6262000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6263000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6264000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6265000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6266000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6267000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6268000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6269000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E626A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E626B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E626C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E626D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E626E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E626F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6270000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6271000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6272000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6273000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6274000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6275000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6276000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6277000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6278000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6279000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E627A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E627B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E627C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E627D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E627E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E627F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6280000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6281000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6282000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6283000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6284000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6285000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6286000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6287000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6288000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6289000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E628A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E628B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E628C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E628D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E628E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E628F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6290000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6291000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6292000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6293000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6294000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6295000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6296000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6297000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6298000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6299000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E629A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E629B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E629C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E629D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E629E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E629F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62AA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62AB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62AC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62AD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62AE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62AF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62BA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62BB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62BC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62BD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62BE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62BF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62CA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62CB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62CC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62CD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62CE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62CF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62DA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62DB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62DC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62DD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62DE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62DF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62EA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62EB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62EC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62ED000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62EE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62EF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62FA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62FB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62FC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62FD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62FE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62FF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6300000U | MMU_TBL_PAGE_EXECREAD_MEMORY, /* SystemRAM Start */ + 0x00000000E6301000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6302000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6303000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6304000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6305000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6306000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6307000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6308000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6309000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E630A000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E630B000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E630C000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E630D000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E630E000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E630F000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6310000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6311000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6312000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6313000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6314000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6315000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6316000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6317000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6318000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6319000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E631A000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E631B000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E631C000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E631D000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E631E000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E631F000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6320000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6321000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6322000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6323000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6324000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6325000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6326000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6327000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6328000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6329000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E632A000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E632B000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E632C000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E632D000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E632E000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E632F000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6330000U | MMU_TBL_PAGE_NOEXEC_MEMORY, /* SystemRAM (.bss) */ + 0x00000000E6331000U | MMU_TBL_PAGE_NOEXEC_MEMORY, /* SystemRAM (.stack) */ + 0x00000000E6332000U | MMU_TBL_PAGE_NOEXEC_MEMORY, /* SystemRAM (.stack) */ + 0x00000000E6333000U | MMU_TBL_PAGE_NOEXEC_MEMORY, /* SystemRAM (Reserved) Start */ + 0x00000000E6334000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6335000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6336000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6337000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6338000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6339000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E633A000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E633B000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E633C000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E633D000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E633E000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E633F000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6340000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6341000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6342000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6343000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6344000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6345000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6346000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6347000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6348000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6349000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E634A000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E634B000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E634C000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E634D000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E634E000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E634F000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6350000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6351000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6352000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6353000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6354000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6355000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6356000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6357000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6358000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6359000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E635A000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E635B000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E635C000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E635D000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E635E000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E635F000U | MMU_TBL_PAGE_NOEXEC_MEMORY, /* SystemRAM (Reserved) End */ + 0x00000000E6360000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6361000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6362000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6363000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6364000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6365000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6366000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6367000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6368000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6369000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E636A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E636B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E636C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E636D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E636E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E636F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6370000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6371000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6372000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6373000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6374000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6375000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6376000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6377000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6378000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6379000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E637A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E637B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E637C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E637D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E637E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E637F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6380000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6381000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6382000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6383000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6384000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6385000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6386000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6387000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6388000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6389000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E638A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E638B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E638C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E638D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E638E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E638F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6390000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6391000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6392000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6393000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6394000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6395000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6396000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6397000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6398000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6399000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E639A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E639B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E639C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E639D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E639E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E639F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63AA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63AB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63AC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63AD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63AE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63AF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63BA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63BB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63BC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63BD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63BE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63BF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63CA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63CB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63CC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63CD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63CE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63CF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63DA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63DB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63DC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63DD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63DE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63DF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63EA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63EB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63EC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63ED000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63EE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63EF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63FA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63FB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63FC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63FD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63FE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63FF000U | MMU_TBL_PAGE_NOEXEC_DEVICE +}; + +const uint64_t g_loader_level2_table[] __attribute__ ((aligned (4096))) __attribute__ ((section(".lv2_tbl"))) = +{ + 0x00000000C0000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C0200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C0400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C0600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C0800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C0A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C0C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C0E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CA000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CA200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CA400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CA600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CA800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CAA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CAC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CAE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CB000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CB200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CB400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CB600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CB800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CBA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CBC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CBE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CC000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CC200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CC400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CC600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CC800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CCA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CCC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CCE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CD000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CD200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CD400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CD600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CD800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CDA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CDC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CDE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CE000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CE200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CE400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CE600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CE800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CEA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CEC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CEE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CF000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CF200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CF400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CF600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CF800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CFA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CFC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CFE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DA000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DA200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DA400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DA600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DA800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DAA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DAC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DAE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DB000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DB200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DB400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DB600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DB800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DBA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DBC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DBE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DC000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DC200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DC400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DC600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DC800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DCA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DCC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DCE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DD000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DD200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DD400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DD600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DD800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DDA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DDC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DDE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DE000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DE200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DE400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DE600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DE800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DEA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DEC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DEE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DF000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DF200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DF400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DF600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DF800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DFA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DFC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DFE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E2000000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, /* RT-VRAM Start */ + 0x00000000E2200000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E2400000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E2600000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E2800000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E2A00000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E2C00000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E2E00000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E3000000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E3200000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E3400000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E3600000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E3800000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E3A00000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, /* RT-VRAM End */ + 0x00000000E3C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E3E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E6000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + MMU_TBL_SYSRAM_ADDR | MMU_TBL_TYPE_TABLE, + 0x00000000E6400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E6600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E6800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E6A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E6C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E6E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EA000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EA200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EA400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EA600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EA800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EAA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EAC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EAE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EB000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EB200000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, /* RT-SRAM Start-End (H'00 EB2FFFFF) */ + 0x00000000EB400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EB600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EB800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EBA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EBC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EBE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EC000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EC200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EC400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EC600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EC800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ECA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ECC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ECE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ED000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ED200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ED400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ED600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ED800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EDA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EDC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EDE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EE000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EE200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EE400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EE600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EE800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EEA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EEC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EEE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EF000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EF200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EF400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EF600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EF800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EFA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EFC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EFE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FA000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FA200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FA400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FA600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FA800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FAA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FAC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FAE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FB000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FB200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FB400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FB600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FB800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FBA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FBC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FBE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FC000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FC200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FC400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FC600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FC800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FCA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FCC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FCE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FD000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FD200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FD400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FD600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FD800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FDA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FDC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FDE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FE000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FE200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FE400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FE600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FE800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FEA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FEC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FEE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FF000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FF200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FF400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FF600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FF800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FFA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FFC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FFE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE +}; + +const uint64_t g_loader_level1_table[] __attribute__ ((aligned (32))) __attribute__ ((section(".lv1_tbl"))) = +{ + 0x0000000000000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x0000000040000000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x0000000080000000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + MMU_TBL_ADDR | MMU_TBL_TYPE_TABLE +}; diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_s4.S b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_s4.S new file mode 100644 index 0000000..45c0ab3 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_s4.S @@ -0,0 +1,336 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file loader_s4.S + * - Version : 0.06 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 27.06.2022 0.02 Remove unused definitions + * : 02.08.2022 0.03 Support WDT + * : 31.10.2022 0.04 License notation change. + * : 14.12.2022 0.05 Support MMU + * : 17.02.2023 0.06 Modified instruction and General purpose + * register to lower case. + *****************************************************************************/ + +#include "asm_macros.S" + +/* SCTLR definitions */ +#define SCTLR_M_BIT (1 << 0) +#define SCTLR_A_BIT (1 << 1) +#define SCTLR_SA_BIT (1 << 3) +#define SCTLR_I_BIT (1 << 12) +#define SCTLR_WXN_BIT (1 << 19) +#define SCTLR_EE_BIT (1 << 25) +#define SCTLR_RESET_VAL (SCTLR_SA_BIT) +#define SCTLR_MMU_ON (SCTLR_M_BIT) +#define SCTLR_OFF ~(SCTLR_M_BIT | SCTLR_I_BIT | SCTLR_A_BIT) + +/* SCR definitions */ +#define SCR_RES1_BITS ((1 << 4) | (1 << 5)) +#define SCR_TWEDEL_SHIFT (30) +#define SCR_TWEDEL_MASK (0xf) +#define SCR_AMVOFFEN_BIT (1 << 35) +#define SCR_TWEDEn_BIT (1 << 29) +#define SCR_ECVEN_BIT (1 << 28) +#define SCR_FGTEN_BIT (1 << 27) +#define SCR_ATA_BIT (1 << 26) +#define SCR_FIEN_BIT (1 << 21) +#define SCR_EEL2_BIT (1 << 18) +#define SCR_API_BIT (1 << 17) +#define SCR_APK_BIT (1 << 16) +#define SCR_TERR_BIT (1 << 15) +#define SCR_TWE_BIT (1 << 13) +#define SCR_TWI_BIT (1 << 12) +#define SCR_ST_BIT (1 << 11) +#define SCR_RW_BIT (1 << 10) +#define SCR_SIF_BIT (1 << 9) +#define SCR_HCE_BIT (1 << 8) +#define SCR_SMD_BIT (1 << 7) +#define SCR_EA_BIT (1 << 3) +#define SCR_FIQ_BIT (1 << 2) +#define SCR_IRQ_BIT (1 << 1) +#define SCR_NS_BIT (1 << 0) +#define SCR_VALID_BIT_MASK (0x2f8f) +#define SCR_RESET_VAL SCR_RES1_BITS + +/* CPSR/SPSR definitions */ +#define DAIF_FIQ_BIT (1 << 0) +#define DAIF_IRQ_BIT (1 << 1) +#define DAIF_ABT_BIT (1 << 2) +#define DAIF_DBG_BIT (1 << 3) +#define SPSR_DAIF_SHIFT (6) +#define SPSR_DAIF_MASK (0xf) + +#define SPSR_AIF_SHIFT (6) +#define SPSR_AIF_MASK (0x7) + +#define SPSR_E_SHIFT (9) +#define SPSR_E_MASK (0x1) +#define SPSR_E_LITTLE (0x0) +#define SPSR_E_BIG (0x1) + +#define SPSR_T_SHIFT (5) +#define SPSR_T_MASK (0x1) +#define SPSR_T_ARM (0x0) +#define SPSR_T_THUMB (0x1) + +#define SPSR_M_SHIFT (4) +#define SPSR_M_MASK (0x1) +#define SPSR_M_AARCH64 (0x0) +#define SPSR_M_AARCH32 (0x1) + +#define SPSR_EL_SHIFT (2) +#define SPSR_EL_WIDTH (2) + +/* TCR definitions */ +#define TCR_BIT31_RES1 (1 << 31) +#define TCR_BIT23_RES1 (1 << 23) +#define TCR_PS (0 << 16) +#define TCR_TG0 (0 << 14) +#define TCR_SH0 (3 << 12) +#define TCR_ORGN0 (3 << 10) +#define TCR_IRGN0 (3 << 8) +#define TCR_T0SZ (32 << 0) + +#define TCR_VAL \ + (TCR_BIT31_RES1 | TCR_BIT23_RES1 | TCR_PS | TCR_TG0 | TCR_SH0 | TCR_ORGN0 | TCR_IRGN0 | TCR_T0SZ) + +/* MAIR definitions */ +#define MAIR_ATTR0 (0x00 << 0) /* Device-nGnRnE memory */ +#define MAIR_ATTR1 (0x4A << 8) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */ +#define MAIR_ATTR2 (0x44 << 16) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */ +#define MAIR_ATTR3 (0x00 << 24) +#define MAIR_ATTR4 (0x00 << 32) +#define MAIR_ATTR5 (0x00 << 40) +#define MAIR_ATTR6 (0x00 << 48) +#define MAIR_ATTR7 (0x00 << 56) + +#define MAIR_VAL \ + (MAIR_ATTR7 | MAIR_ATTR6 | MAIR_ATTR5 | MAIR_ATTR4 | MAIR_ATTR3 | MAIR_ATTR2 | MAIR_ATTR1 | MAIR_ATTR0) +#define MAIR_INIT_VAL (0x44E048E000098AA4) + +#define BIT_64Cx(nr) (1 << (nr)) +#define SPSR_SSBS_BIT_AARCH64 BIT_64Cx(12) +#define SPSR_SSBS_BIT_AARCH32 BIT_64Cx(23) + +#define DISABLE_ALL_EXCEPTIONS \ + (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) + +#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) +#define MODE_RW_SHIFT (0x4) +#define MODE_SP_MASK (0x1) +#define MODE_SP_SHIFT (0x0) +#define MODE_EL_MASK (0x3) +#define MODE_EL_SHIFT (0x2) +#define MODE_EL3 (0x3) + +#define MODE_RW_64 (0x0) +#define MODE_SP_ELX (0x1) + +#define SPSR_64 (((MODE_RW_64 << MODE_RW_SHIFT) | \ +((MODE_EL3 & MODE_EL_MASK) << MODE_EL_SHIFT) | \ +((MODE_SP_ELX & MODE_SP_MASK) << MODE_SP_SHIFT) | \ +((DISABLE_ALL_EXCEPTIONS & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ +(~(SPSR_SSBS_BIT_AARCH64))) + + + .global Startup + +/***************************************************************************** + * Reset Hander + *****************************************************************************/ +Startup: + /* initialize registers*/ + ldr x0, =0 + ldr x1, =0 + ldr x2, =0 + ldr x3, =0 + ldr x4, =0 + ldr x5, =0 + ldr x6, =0 + ldr x7, =0 + ldr x8, =0 + ldr x9, =0 + ldr x10, =0 + ldr x11, =0 + ldr x12, =0 + ldr x13, =0 + ldr x14, =0 + ldr x15, =0 + ldr x16, =0 + ldr x17, =0 + ldr x18, =0 + ldr x19, =0 + ldr x20, =0 + ldr x21, =0 + ldr x22, =0 + ldr x23, =0 + ldr x24, =0 + ldr x25, =0 + ldr x26, =0 + ldr x27, =0 + ldr x28, =0 + ldr x29, =0 + ldr x30, =0 + + ldr x0, =__STACKS_END__ + + mrs x1, sctlr_el3 + mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ + | SCTLR_SA_BIT | SCTLR_A_BIT)) + orr x0, x0, x1 + msr sctlr_el3, x0 + isb + + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el3 + orr x0, x0, x1 + msr sctlr_el3, x0 + isb + + mrs x1, scr_el3 + mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT | SCR_FIQ_BIT ) \ + & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) + orr x0, x0, x1 + msr scr_el3, x0 + + /* --------------------------------------------------------------------- + * Set the exception vectors. + * --------------------------------------------------------------------- + */ + adr x0, loader_exceptions + msr vbar_el3, x0 + isb + + msr daifclr, #(DAIF_ABT_BIT | DAIF_FIQ_BIT) + + /* --------------------------------------------------------------------- + * Set the MMU table. + * --------------------------------------------------------------------- + */ + ldr x0 ,=TCR_VAL + msr tcr_el3, x0 + + ldr x0, =MAIR_VAL + msr mair_el3, x0 + + ldr x0, =g_loader_level1_table + msr ttbr0_el3, x0 + + /* --------------------------------------------------------------------- + * Enable MMU. + * --------------------------------------------------------------------- + */ + + isb + tlbi alle3 + isb + + mrs x0, sctlr_el3 + ldr x1 ,=SCTLR_MMU_ON + orr x0, x0, x1 + msr sctlr_el3, x0 + + dsb sy + isb + tlbi alle3 + isb + + /* clear bss section */ + mov x0, #0x0 + ldr x1, =__BSS_START__ + ldr x2, =__BSS_SIZE__ +bss_loop: + subs x2, x2, #4 + bcc bss_end + str w0, [x1, x2] + b bss_loop +bss_end: + + /* copy data section */ + ldr x0, =__DATA_COPY_START__ + ldr x1, =__DATA_START__ + ldr x2, =__DATA_SIZE__ +data_loop: + subs x2, x2, #4 + bcc data_end + ldr w3, [x0, x2] + str w3, [x1, x2] + b data_loop +data_end: + + msr spsel, #0 + + ldr x0, =__STACKS_END__ + mov sp, x0 + + bl loader_main + + msr elr_el3, x0 + + mov x0, #SPSR_64 + msr spsr_el3, x0 + + /* --------------------------------------------------------------------- + * Disable MMU. + * --------------------------------------------------------------------- + */ + mrs x0, sctlr_el3 + ldr x1 ,=SCTLR_OFF + and x0, x0, x1 + msr sctlr_el3, x0 + + dsb sy + isb + tlbi alle3 + ic iallu + + /* --------------------------------------------------------------------- + * Set initial value. + * --------------------------------------------------------------------- + */ + msr ttbr0_el3, xzr + + ldr x0, =MAIR_INIT_VAL + msr mair_el3, x0 + + msr tcr_el3, xzr + + msr vbar_el3, xzr + isb + + eret + + + .end \ No newline at end of file diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_s4.ld b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_s4.ld new file mode 100644 index 0000000..3e0d894 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_s4.ld @@ -0,0 +1,140 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Loader linker directive + ******************************************************************************/ +/****************************************************************************** + * @file loader,ld + * - Version : 0.07 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 21.02.2022 0.02 Changed section name + * : 10.05.2022 0.03 Changed section name + * Added memory + * Change binary size to multiples of 16 + * : 20.06.2022 0.04 Support secure boot for S4 + * : 02.08.2022 0.05 Support WDT + * : 31.10.2022 0.06 License notation change. + * : 13.02.2023 0.07 Added sections for MMU table. + *****************************************************************************/ + +OUTPUT_FORMAT("elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(Startup) + +MEMORY { + SYSRAM (rwxa): ORIGIN = 0xE6300000, LENGTH = 0x00030000 + + /* Must match with MMU_TBL_SYSRAM_ADDR defined in loader_mmu_table.c. */ + MMU_LV3_STAT (rwa): ORIGIN = 0xE6310000, LENGTH = 0x00001000 /* level3:4KiB */ + /* Must match with MMU_TBL_ADDR defined in loader_mmu_table.c. */ + MMU_LV2_STAT (rwa): ORIGIN = 0xE6311000, LENGTH = 0x00001000 /* level2:4KiB */ + MMU_LV1_STAT (rwa): ORIGIN = 0xE6312000, LENGTH = 0x00000100 /* level1:32byte */ + CXIPLDATA (rwa): ORIGIN = 0xE6330000, LENGTH = 0x00001000 + CXIPLSTACK (rwa): ORIGIN = 0xE6331000, LENGTH = 0x00002000 + SHARED_RAM (rwa): ORIGIN = 0x41C00000, LENGTH = 0x0000C000 + SHARED_SDRAM (rwa): ORIGIN = 0x41E00000, LENGTH = 0x00200000 +} + +SECTIONS +{ + .loader_start : { + __RO_START__ = .; + build/obj/loader/loader_s4.o(.text*) + . = NEXT(2048); + *(.vectors) + . = ALIGN(4096); + } > SYSRAM + + .loader_ro : { + *(.text*) + *(.rodata*) + . = ALIGN(8); + __CONST_START__ = .; + *(.constdata.CONFIG_DATA) + __RO_END_UNALIGNED__ = .; + . = NEXT(4096); + __RO_END__ = .; + __DATA_COPY_START__ = .; + } > SYSRAM + + .lv3_tbl : { + build/obj/loader/loader_mmu_table.o(.rodata) + } > MMU_LV3_STAT + + .lv2_tbl : { + build/obj/loader/loader_mmu_table.o(.rodata) + } > MMU_LV2_STAT + + .lv1_tbl : { + build/obj/loader/loader_mmu_table.o(.rodata) + } > MMU_LV1_STAT + + .data : { + __DATA_START__ = .; + *(.data*) + . = NEXT(16); + __DATA_END__ = .; + } > CXIPLDATA AT > SYSRAM + + __DATA_SIZE__ = SIZEOF(.data); + + stacks (NOLOAD) : ALIGN(16) { + __STACKS_START__ = .; + KEEP(*(Cx_loader_stack)) + __STACKS_END__ = .; + } > CXIPLSTACK + + .bss.SHARED_TOP : { + __SHARED_TOP_START__ = .; + *(.bss.SHARED_TOP) + *(.bss.SHARED_LCS) + *(.bss.SHARED_CMAC) + *(.bss.SHARED_HASH) + . = NEXT(0x00200000); + __SHARED__END__ = .; + } > SHARED_SDRAM + + .SHARED_RAM : { + __FWRAM_START__ = .; + . += 0; + . = NEXT(0x0000C000); + __FWRAM_END__ = .; + } > SHARED_RAM + + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } > CXIPLDATA + + __BSS_SIZE__ = SIZEOF(.bss); +} diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4h.S b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4h.S new file mode 100644 index 0000000..e186940 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4h.S @@ -0,0 +1,387 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file loader_v4h.S + * - Version : 0.07 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 17.02.2022 0.01 First Release + * : 09.05.2022 0.02 Removed the last nop instruction + * : 31.10.2022 0.03 License notation change. + * : 15.12.2022 0.04 V4H interrupt support. + * : 28.12.2022 0.05 MPU support. + * Address acquisition changes in interrupt handlers + * : 16.02.2023 0.06 Modified instruction to lower case. + * : 19.12.2024 0.07 Added the process that jump to RTOS#1. + *****************************************************************************/ + +/* SCTLR definitions */ +#define SCTLR_I (1 << 12) +#define SCTLR_M (1 << 0) + +/* MAIR definitions */ +#define MAIR_ATTR0 (0x00 << 0) /* Device-nGnRnE memory */ +#define MAIR_ATTR1 (0x4A << 8) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */ +#define MAIR_ATTR2 (0x44 << 16) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */ +#define MAIR_VAL (MAIR_ATTR2 | MAIR_ATTR1 | MAIR_ATTR0) + +#define SUP_EXCEPTION (0x2U) +#define HYP_EXCEPTION (0x5U) +#define IRQ_EXCEPTION (0x6U) +#define FIQ_EXCEPTION (0x7U) + +#define RTOS_LOAD_NUM_1 (1) /* RTOS is RTOS#0 only. */ +#define RTOS_LOAD_NUM_3 (3) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */ + + .global Startup + .global Vector + .global dabt_report_exception + .global pabt_report_exception + + .extern dabort_error + .extern pabort_error + .extern Undefined_error + .extern handler_error + + .align 5 + +Vector: + b Startup /* Reset */ + b Undefined_Handler /* Undefined Instruction */ + b Supervisor_Handler /* Supervisor Call */ + b Prefetch_Handler /* Prefetch Abort */ + b Abort_Handler /* Data Abort */ + b HypTrap_Handler /* Hyp Trap */ + b IRQ_Handler /* IRQ interrupt */ + b FIQ_Handler /* FIQ interrupt */ + +/***************************************************************************** + * Reset Hander + *****************************************************************************/ +Startup: +/* initialize registers*/ + /* initialize registers*/ + mov r0, #0 + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 + mov r8, #0 + mov r9, #0 + mov r10, #0 + mov r11, #0 + mov r12, #0 + mov lr, #0 + + ldr r13, =__STACKS_END__ + +/* Instruction cache enable */ + mrc p15, 4, r0, c1, c0, 0 /* HSCTLR */ + mrc p15, 0, r1, c1, c0, 0 /* SCTLR */ + bic r0, r0, #SCTLR_M /* M=0 */ + bic r1, r1, #SCTLR_M /* M=0 */ + orr r0, r0, #SCTLR_I /* I=1 */ + orr r1, r1, #SCTLR_I /* I=1 */ + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + mcr p15, 4, r0, c1, c0, 0 /* HSCTLR */ + mcr p15, 0, r1, c1, c0, 0 /* SCTLR */ + isb + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + isb + +/* CR52_CONFIGURE_MPU */ + mrc p15, 0, r0, c10, c2, 0 /* Read MAIR0 into R0 */ + mrc p15, 4, r1, c10, c2, 0 /* Read HMAIR0 into R1 */ + ldr r0, =MAIR_VAL /* Set MAIR */ + ldr r1, =MAIR_VAL /* Set MAIR */ + mcr p15, 0, r0, c10, c2, 0 /* Write R0 to MAIR0 */ + mcr p15, 4, r1, c10, c2, 0 /* Write R1 to HMAIR0 */ + +/* region 0: 0x00000000~0x3FFFFFFF */ + ldr r0, =0x00000006 /* SH=b'00/AP=b'11/XN=b'0 */ + ldr r1, =0x3FFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 0 /* Write R0 into PRBAR0 */ + mcr p15, 0, r1, c6, c8, 1 /* Write R1 into PRLAR0 */ + mcr p15, 4, r0, c6, c8, 0 /* Write R0 into HPRBAR0 */ + mcr p15, 4, r1, c6, c8, 1 /* Write R1 into HPRLAR0 */ +/* region 1: 0x40000000~0xBFFFFFFF */ + ldr r0, =0x40000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xBFFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 4 /* Write R0 into PRBAR1 */ + mcr p15, 0, r1, c6, c8, 5 /* Write R1 into PRLAR1 */ + mcr p15, 4, r0, c6, c8, 4 /* Write R0 into HPRBAR1 */ + mcr p15, 4, r1, c6, c8, 5 /* Write R1 into HPRLAR1 */ +/* region 2: 0xC0000000~0xE3FFFFFF */ + ldr r0, =0xC0000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE3FFFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c9, 0 /* Write R0 into PRBAR2 */ + mcr p15, 0, r1, c6, c9, 1 /* Write R1 into PRLAR2 */ + mcr p15, 4, r0, c6, c9, 0 /* Write R0 into HPRBAR2 */ + mcr p15, 4, r1, c6, c9, 1 /* Write R1 into HPRLAR2 */ +/* region 3: 0xE4000000~0xE4FFFFFF */ + ldr r0, =0xE4000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE4FFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c9, 4 /* Write R0 into PRBAR3 */ + mcr p15, 0, r1, c6, c9, 5 /* Write R1 into PRLAR3 */ + mcr p15, 4, r0, c6, c9, 4 /* Write R0 into HPRBAR3 */ + mcr p15, 4, r1, c6, c9, 5 /* Write R1 into HPRLAR3 */ +/* region 4: 0xE5000000~0xE62FFFFF */ + ldr r0, =0xE5000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE62FFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c10, 0 /* Write R0 into PRBAR4 */ + mcr p15, 0, r1, c6, c10, 1 /* Write R1 into PRLAR4 */ + mcr p15, 4, r0, c6, c10, 0 /* Write R0 into HPRBAR4 */ + mcr p15, 4, r1, c6, c10, 1 /* Write R1 into HPRLAR4 */ +/* region 5: 0xE6300000~0xE632FFFF */ + ldr r0, =0xE6300006 /* SH=b'00/AP=b'11/XN=b'0 */ + ldr r1, =0xE632FFC3 /* AttrIndx=1(Write-Through) */ + mcr p15, 0, r0, c6, c10, 4 /* Write R0 into PRBAR5 */ + mcr p15, 0, r1, c6, c10, 5 /* Write R1 into PRLAR5 */ + mcr p15, 4, r0, c6, c10, 4 /* Write R0 into HPRBAR5 */ + mcr p15, 4, r1, c6, c10, 5 /* Write R1 into HPRLAR5 */ +/* region 6: 0xE6330000~0xE635FFFF */ + ldr r0, =0xE6330003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE635FFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c11, 0 /* Write R0 into PRBAR6 */ + mcr p15, 0, r1, c6, c11, 1 /* Write R1 into PRLAR6 */ + mcr p15, 4, r0, c6, c11, 0 /* Write R0 into HPRBAR6 */ + mcr p15, 4, r1, c6, c11, 1 /* Write R1 into HPRLAR6 */ +/* region 7: 0xE6360000~0xEB1FFFFF */ + ldr r0, =0xE6360003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xEB1FFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c11, 4 /* Write R0 into PRBAR7 */ + mcr p15, 0, r1, c6, c11, 5 /* Write R1 into PRLAR7 */ + mcr p15, 4, r0, c6, c11, 4 /* Write R0 into HPRBAR7 */ + mcr p15, 4, r1, c6, c11, 5 /* Write R1 into HPRLAR7 */ +/* region 8: 0xEB200000~0xEB3FFFFF */ + ldr r0, =0xEB200003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xEB3FFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c12, 0 /* Write R0 into PRBAR8 */ + mcr p15, 0, r1, c6, c12, 1 /* Write R1 into PRLAR8 */ + mcr p15, 4, r0, c6, c12, 0 /* Write R0 into HPRBAR8 */ + mcr p15, 4, r1, c6, c12, 1 /* Write R1 into HPRLAR8 */ +/* region 9: 0xEB400000~0xFFFFFFFF */ + ldr r0, =0xEB400003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xFFFFFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c12, 4 /* Write R0 into PRBAR9 */ + mcr p15, 0, r1, c6, c12, 5 /* Write R1 into PRLAR9 */ + mcr p15, 4, r0, c6, c12, 4 /* Write R0 into HPRBAR9 */ + mcr p15, 4, r1, c6, c12, 5 /* Write R1 into HPRLAR9 */ + +/* CR52_SET_MPU_ON */ + mrc p15, 4, r0, c1, c0, 0 /* Read HSCTLR */ + mrc p15, 0, r1, c1, c0, 0 /* Read SCTLR */ + orr r0, r0, #SCTLR_M /* MPU enable */ + orr r1, r1, #SCTLR_M /* MPU enable */ + mcr p15, 4, r0, c1, c0, 0 /* Write HSCTLR */ + mcr p15, 0, r1, c1, c0, 0 /* Write SCTLR */ + isb + + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + isb + +/* Jump to physical address from mirror address */ + ldr r0, =JUMP_MAIN + bx r0 + +JUMP_MAIN: + ldr r0, =Vector + mcr p15, 4, r0, c12, c0, 0 /* HVBAR */ + +/* clear bss section */ + mov r0, #0x0 + ldr r1, =__BSS_START__ + ldr r2, =__BSS_SIZE__ +bss_loop: + subs r2, r2, #4 + bcc bss_end + str r0, [r1, +r2] + b bss_loop +bss_end: + +/* copy data section */ + ldr r0, =__DATA_COPY_START__ + ldr r1, =__DATA_START__ + ldr r2, =__DATA_SIZE__ +data_loop: + subs r2, r2, #4 + bcc data_end + ldr r3, [r0, +r2] + str r3, [r1, +r2] + b data_loop +data_end: + +/* Loader Main */ + bl loader_main + +#if ((RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) || defined(MOBIS_PRK3)) +/* Keep return value from loader_main function (Boot address of RTOS#1) */ + mov r11, r0 +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* region 0: 0x00000000~0x3FFFFFFF */ + ldr r0, =0x00000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0x3FFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 0 /* Write R0 into PRBAR0 */ + mcr p15, 0, r1, c6, c8, 1 /* Write R1 into PRLAR0 */ + mcr p15, 4, r0, c6, c8, 0 /* Write R0 into HPRBAR0 */ + mcr p15, 4, r1, c6, c8, 1 /* Write R1 into HPRLAR0 */ +/* region 1: 0x40000000~0xBFFFFFFF */ + ldr r0, =0x40000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xBFFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 4 /* Write R0 into PRBAR1 */ + mcr p15, 0, r1, c6, c8, 5 /* Write R1 into PRLAR1 */ + mcr p15, 4, r0, c6, c8, 4 /* Write R0 into HPRBAR1 */ + mcr p15, 4, r1, c6, c8, 5 /* Write R1 into HPRLAR1 */ +#if ((RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) || defined(MOBIS_PRK3)) +/* region 2: 0xC0000000~0xE3FFFFFF */ +/* Change MPU setting for RTOS#1. */ + ldr r0, =0xC0000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE3FFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c9, 0 /* Write R0 into PRBAR2 */ + mcr p15, 0, r1, c6, c9, 1 /* Write R1 into PRLAR2 */ + mcr p15, 4, r0, c6, c9, 0 /* Write R0 into HPRBAR2 */ + mcr p15, 4, r1, c6, c9, 1 /* Write R1 into HPRLAR2 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +/* region 3: 0xE4000000~0xE4FFFFFF */ + ldr r0, =0xE4000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE4FFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c9, 4 /* Write R0 into PRBAR3 */ + mcr p15, 0, r1, c6, c9, 5 /* Write R1 into PRLAR3 */ + mcr p15, 4, r0, c6, c9, 4 /* Write R0 into HPRBAR3 */ + mcr p15, 4, r1, c6, c9, 5 /* Write R1 into HPRLAR3 */ +/* region 5: 0xE6300000~0xE632FFFF */ + ldr r0, =0xE6300002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE632FFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c10, 4 /* Write R0 into PRBAR5 */ + mcr p15, 0, r1, c6, c10, 5 /* Write R1 into PRLAR5 */ + mcr p15, 4, r0, c6, c10, 4 /* Write R0 into HPRBAR5 */ + mcr p15, 4, r1, c6, c10, 5 /* Write R0 into HPRLAR5 */ +/* region 6: 0xE6330000~0xE635FFFF */ + ldr r0, =0xE6330002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE635FFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c11, 0 /* Write R0 into PRBAR6 */ + mcr p15, 0, r1, c6, c11, 1 /* Write R1 into PRLAR6 */ + mcr p15, 4, r0, c6, c11, 0 /* Write R0 into HPRBAR6 */ + mcr p15, 4, r1, c6, c11, 1 /* Write R1 into HPRLAR6 */ +/* region 8: 0xEB200000~0xEB3FFFFF */ + ldr r0, =0xEB200002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xEB3FFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c12, 0 /* Write R0 into PRBAR8 */ + mcr p15, 0, r1, c6, c12, 1 /* Write R1 into PRLAR8 */ + mcr p15, 4, r0, c6, c12, 0 /* Write R0 into HPRBAR8 */ + mcr p15, 4, r1, c6, c12, 1 /* Write R1 into HPRLAR8 */ + + isb + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + isb + +/* Instruction cache disable */ + mrc p15, 4, r0, c1, c0, 0 /* Read HSCTLR */ + mrc p15, 0, r1, c1, c0, 0 /* Read SCTLR */ + bic r0, r0, #SCTLR_I /* I=0 */ + bic r1, r1, #SCTLR_I /* I=0 */ + mcr p15, 4, r0, c1, c0, 0 /* Write HSCTLR */ + mcr p15, 0, r1, c1, c0, 0 /* Write SCTLR */ + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + isb + +#if defined(MOBIS_PRK3) +/* declare IPL-2nd is finished */ + ldr r0, =0xEB22FFF4 + ldr r1, =0xE632FFFF + str r1, [r0] +#endif +#if ((RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) || defined(MOBIS_PRK3)) +/* Jump to RTOS#1 */ + bx r11 +#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1) +loader_end: + wfi + b loader_end +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +anker: + wfi + b anker + +/* Undefined Instruction */ +Undefined_Handler: + mrs r0, ELR_hyp + b Undefined_error + +/* Supervisor Call */ +Supervisor_Handler: + mov r0, #SUP_EXCEPTION + b handler_error + +/* Prefetch Abort */ +Prefetch_Handler: + b pabt_report_exception + +/* Data Abort */ +Abort_Handler: + mrs r0, ELR_hyp + b dabt_report_exception + +/* Hyp Trap */ +HypTrap_Handler: + mov r0, #HYP_EXCEPTION + b handler_error + +/*IRQ interrupt */ +IRQ_Handler: + mov r0, #IRQ_EXCEPTION + b handler_error + +/* FIQ interrupt */ +FIQ_Handler: + mov r0, #FIQ_EXCEPTION + b handler_error + +/******************************************************** + * abort exception + ********************************************************/ +dabt_report_exception: + mrc p15, 0, r1, c5, c0, 0 /* Read DFSR */ + mrc p15, 0, r2, c6, c0, 0 /* Read DFAR */ + b dabort_error + +pabt_report_exception: + mrc p15, 0, r0, c5, c0, 1 /* Read IFSR */ + mrc p15, 0, r1, c6, c0, 2 /* Read IFAR */ + b pabort_error + + .end diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4h.ld b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4h.ld new file mode 100644 index 0000000..d0f3c36 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4h.ld @@ -0,0 +1,137 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Loader linker directive + ******************************************************************************/ +/****************************************************************************** + * @file AArch32_loader,ld + * - Version : 0.05 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 17.02.2022 0.01 First Release + * : 21.02.2022 0.02 Changed section name + * : 10.05.2022 0.03 Changed section name + * Added memory + * Change binary size to multiples of 16 + * : 31.10.2022 0.04 License notation change. + * : 07.11.2022 0.05 Changed the size of CXIPLDATA. + * Added Qos settings assignment. + * : 15.12.2022 0.10 Support RegionID check + *****************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(Startup) + +MEMORY { + SYSRAM (rwxa): ORIGIN = 0xE6300000, LENGTH = 0x00030000 + CXIPLDATA (rwa): ORIGIN = 0xE6330000, LENGTH = 0x00003000 + CXIPLSTACK (rwa): ORIGIN = 0xE6333000, LENGTH = 0x00002000 + SHARED_RAM (rwa): ORIGIN = 0x41C00000, LENGTH = 0x0000C000 + SHARED_SDRAM (rwa): ORIGIN = 0x41E00000, LENGTH = 0x00200000 +} + +SECTIONS +{ + .loader_start : { + __RO_START__ = .; + build/obj/loader/loader_v4h.o(.text*) + . = NEXT(1024); + *(.vectors) + . = ALIGN(4096); + } > SYSRAM + + .loader_ro : { + *(.text*) + *(.rodata*) + . = ALIGN(8); + __CONST_START__ = .; + . = ALIGN(16); + *(.qoswt_tbl) + . = ALIGN(8); + *(.qosbw_tbl) + . = ALIGN(8); + *(.constdata.CONFIG_DATA) + . = ALIGN(8); + *(.rgid_w_tbl) + . = ALIGN(8); + *(.rgid_r_tbl) + . = ALIGN(8); + *(.rgid_m_tbl) + . = ALIGN(8); + *(.rgid_sec_tbl) + . = ALIGN(8); + *(.rgid_axi_tbl) + __RO_END_UNALIGNED__ = .; + . = NEXT(4096); + __RO_END__ = .; + __DATA_COPY_START__ = .; + } > SYSRAM + + .data : { + __DATA_START__ = .; + *(.data*) + . = NEXT(16); + __DATA_END__ = .; + } > CXIPLDATA AT > SYSRAM + + __DATA_SIZE__ = SIZEOF(.data); + + stacks (NOLOAD) : ALIGN(16) { + __STACKS_START__ = .; + KEEP(*(Cx_loader_stack)) + __STACKS_END__ = .; + } > CXIPLSTACK + + .bss.SHARED_TOP : { + __SHARED_TOP_START__ = .; + *(.bss.SHARED_TOP) + *(.bss.SHARED_LCS) + *(.bss.SHARED_CMAC) + *(.bss.SHARED_HASH) + . = NEXT(0x00200000); + __SHARED__END__ = .; + } > SHARED_SDRAM + + .SHARED_RAM : { + __FWRAM_START__ = .; + . += 0; + . = NEXT(0x0000C000); + __FWRAM_END__ = .; + } > SHARED_RAM + + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } > CXIPLDATA + + __BSS_SIZE__ = SIZEOF(.bss); +} diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4m.S b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4m.S new file mode 100644 index 0000000..5106219 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4m.S @@ -0,0 +1,375 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file loader_v4m.S + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + * : 19.12.2024 0.02 Added the process that jump to RTOS#1. + *****************************************************************************/ + +/* SCTLR definitions */ +#define SCTLR_I (1 << 12) +#define SCTLR_M (1 << 0) + +/* MAIR definitions */ +#define MAIR_ATTR0 (0x00 << 0) /* Device-nGnRnE memory */ +#define MAIR_ATTR1 (0x4A << 8) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */ +#define MAIR_ATTR2 (0x44 << 16) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */ +#define MAIR_VAL (MAIR_ATTR2 | MAIR_ATTR1 | MAIR_ATTR0) + +#define SUP_EXCEPTION (0x2U) +#define HYP_EXCEPTION (0x5U) +#define IRQ_EXCEPTION (0x6U) +#define FIQ_EXCEPTION (0x7U) + +#define RTOS_LOAD_NUM_1 (1) /* RTOS is RTOS#0 only. */ +#define RTOS_LOAD_NUM_3 (3) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */ + + .global Startup + .global Vector + .global dabt_report_exception + .global pabt_report_exception + + .extern dabort_error + .extern pabort_error + .extern Undefined_error + .extern handler_error + + .align 5 + +Vector: + b Startup /* Reset */ + b Undefined_Handler /* Undefined Instruction */ + b Supervisor_Handler /* Supervisor Call */ + b Prefetch_Handler /* Prefetch Abort */ + b Abort_Handler /* Data Abort */ + b HypTrap_Handler /* Hyp Trap */ + b IRQ_Handler /* IRQ interrupt */ + b FIQ_Handler /* FIQ interrupt */ + +/***************************************************************************** + * Reset Hander + *****************************************************************************/ +Startup: +/* initialize registers*/ + /* initialize registers*/ + mov r0, #0 + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 + mov r8, #0 + mov r9, #0 + mov r10, #0 + mov r11, #0 + mov r12, #0 + mov lr, #0 + + ldr r13, =__STACKS_END__ + +/* Instruction cache enable */ + mrc p15, 4, r0, c1, c0, 0 /* HSCTLR */ + mrc p15, 0, r1, c1, c0, 0 /* SCTLR */ + bic r0, r0, #SCTLR_M /* M=0 */ + bic r1, r1, #SCTLR_M /* M=0 */ + orr r0, r0, #SCTLR_I /* I=1 */ + orr r1, r1, #SCTLR_I /* I=1 */ + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + mcr p15, 4, r0, c1, c0, 0 /* HSCTLR */ + mcr p15, 0, r1, c1, c0, 0 /* SCTLR */ + isb + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + isb + +/* CR52_CONFIGURE_MPU */ + mrc p15, 0, r0, c10, c2, 0 /* Read MAIR0 into R0 */ + mrc p15, 4, r1, c10, c2, 0 /* Read HMAIR0 into R1 */ + ldr r0, =MAIR_VAL /* Set MAIR */ + ldr r1, =MAIR_VAL /* Set MAIR */ + mcr p15, 0, r0, c10, c2, 0 /* Write R0 to MAIR0 */ + mcr p15, 4, r1, c10, c2, 0 /* Write R1 to HMAIR0 */ + +/* region 0: 0x00000000~0x3FFFFFFF */ + ldr r0, =0x00000006 /* SH=b'00/AP=b'11/XN=b'0 */ + ldr r1, =0x3FFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 0 /* Write R0 into PRBAR0 */ + mcr p15, 0, r1, c6, c8, 1 /* Write R1 into PRLAR0 */ + mcr p15, 4, r0, c6, c8, 0 /* Write R0 into HPRBAR0 */ + mcr p15, 4, r1, c6, c8, 1 /* Write R1 into HPRLAR0 */ +/* region 1: 0x40000000~0xBFFFFFFF */ + ldr r0, =0x40000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xBFFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 4 /* Write R0 into PRBAR1 */ + mcr p15, 0, r1, c6, c8, 5 /* Write R1 into PRLAR1 */ + mcr p15, 4, r0, c6, c8, 4 /* Write R0 into HPRBAR1 */ + mcr p15, 4, r1, c6, c8, 5 /* Write R1 into HPRLAR1 */ +/* region 2: 0xC0000000~0xE3FFFFFF */ + ldr r0, =0xC0000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE3FFFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c9, 0 /* Write R0 into PRBAR2 */ + mcr p15, 0, r1, c6, c9, 1 /* Write R1 into PRLAR2 */ + mcr p15, 4, r0, c6, c9, 0 /* Write R0 into HPRBAR2 */ + mcr p15, 4, r1, c6, c9, 1 /* Write R1 into HPRLAR2 */ +/* region 3: 0xE4000000~0xE4FFFFFF */ + ldr r0, =0xE4000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE4FFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c9, 4 /* Write R0 into PRBAR3 */ + mcr p15, 0, r1, c6, c9, 5 /* Write R1 into PRLAR3 */ + mcr p15, 4, r0, c6, c9, 4 /* Write R0 into HPRBAR3 */ + mcr p15, 4, r1, c6, c9, 5 /* Write R1 into HPRLAR3 */ +/* region 4: 0xE5000000~0xE62FFFFF */ + ldr r0, =0xE5000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE62FFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c10, 0 /* Write R0 into PRBAR4 */ + mcr p15, 0, r1, c6, c10, 1 /* Write R1 into PRLAR4 */ + mcr p15, 4, r0, c6, c10, 0 /* Write R0 into HPRBAR4 */ + mcr p15, 4, r1, c6, c10, 1 /* Write R1 into HPRLAR4 */ +/* region 5: 0xE6300000~0xE632FFFF */ + ldr r0, =0xE6300006 /* SH=b'00/AP=b'11/XN=b'0 */ + ldr r1, =0xE632FFC3 /* AttrIndx=1(Write-Through) */ + mcr p15, 0, r0, c6, c10, 4 /* Write R0 into PRBAR5 */ + mcr p15, 0, r1, c6, c10, 5 /* Write R1 into PRLAR5 */ + mcr p15, 4, r0, c6, c10, 4 /* Write R0 into HPRBAR5 */ + mcr p15, 4, r1, c6, c10, 5 /* Write R1 into HPRLAR5 */ +/* region 6: 0xE6330000~0xE635FFFF */ + ldr r0, =0xE6330003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE635FFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c11, 0 /* Write R0 into PRBAR6 */ + mcr p15, 0, r1, c6, c11, 1 /* Write R1 into PRLAR6 */ + mcr p15, 4, r0, c6, c11, 0 /* Write R0 into HPRBAR6 */ + mcr p15, 4, r1, c6, c11, 1 /* Write R1 into HPRLAR6 */ +/* region 7: 0xE6360000~0xEB1FFFFF */ + ldr r0, =0xE6360003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xEB1FFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c11, 4 /* Write R0 into PRBAR7 */ + mcr p15, 0, r1, c6, c11, 5 /* Write R1 into PRLAR7 */ + mcr p15, 4, r0, c6, c11, 4 /* Write R0 into HPRBAR7 */ + mcr p15, 4, r1, c6, c11, 5 /* Write R1 into HPRLAR7 */ +/* region 8: 0xEB200000~0xEB3FFFFF */ + ldr r0, =0xEB200003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xEB3FFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c12, 0 /* Write R0 into PRBAR8 */ + mcr p15, 0, r1, c6, c12, 1 /* Write R1 into PRLAR8 */ + mcr p15, 4, r0, c6, c12, 0 /* Write R0 into HPRBAR8 */ + mcr p15, 4, r1, c6, c12, 1 /* Write R1 into HPRLAR8 */ +/* region 9: 0xEB400000~0xFFFFFFFF */ + ldr r0, =0xEB400003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xFFFFFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c12, 4 /* Write R0 into PRBAR9 */ + mcr p15, 0, r1, c6, c12, 5 /* Write R1 into PRLAR9 */ + mcr p15, 4, r0, c6, c12, 4 /* Write R0 into HPRBAR9 */ + mcr p15, 4, r1, c6, c12, 5 /* Write R1 into HPRLAR9 */ + +/* CR52_SET_MPU_ON */ + mrc p15, 4, r0, c1, c0, 0 /* Read HSCTLR */ + mrc p15, 0, r1, c1, c0, 0 /* Read SCTLR */ + orr r0, r0, #SCTLR_M /* MPU enable */ + orr r1, r1, #SCTLR_M /* MPU enable */ + mcr p15, 4, r0, c1, c0, 0 /* Write HSCTLR */ + mcr p15, 0, r1, c1, c0, 0 /* Write SCTLR */ + isb + + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + isb + +/* Jump to physical address from mirror address */ + ldr r0, =JUMP_MAIN + bx r0 + +JUMP_MAIN: + ldr r0, =Vector + mcr p15, 4, r0, c12, c0, 0 /* HVBAR */ + +/* clear bss section */ + mov r0, #0x0 + ldr r1, =__BSS_START__ + ldr r2, =__BSS_SIZE__ +bss_loop: + subs r2, r2, #4 + bcc bss_end + str r0, [r1, +r2] + b bss_loop +bss_end: + +/* copy data section */ + ldr r0, =__DATA_COPY_START__ + ldr r1, =__DATA_START__ + ldr r2, =__DATA_SIZE__ +data_loop: + subs r2, r2, #4 + bcc data_end + ldr r3, [r0, +r2] + str r3, [r1, +r2] + b data_loop +data_end: + +/* Loader Main */ + bl loader_main + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* Keep return value from loader_main function (Boot address of RTOS#1) */ + mov r11, r0 +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* region 0: 0x00000000~0x3FFFFFFF */ + ldr r0, =0x00000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0x3FFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 0 /* Write R0 into PRBAR0 */ + mcr p15, 0, r1, c6, c8, 1 /* Write R1 into PRLAR0 */ + mcr p15, 4, r0, c6, c8, 0 /* Write R0 into HPRBAR0 */ + mcr p15, 4, r1, c6, c8, 1 /* Write R1 into HPRLAR0 */ +/* region 1: 0x40000000~0xBFFFFFFF */ + ldr r0, =0x40000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xBFFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 4 /* Write R0 into PRBAR1 */ + mcr p15, 0, r1, c6, c8, 5 /* Write R1 into PRLAR1 */ + mcr p15, 4, r0, c6, c8, 4 /* Write R0 into HPRBAR1 */ + mcr p15, 4, r1, c6, c8, 5 /* Write R1 into HPRLAR1 */ +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* region 2: 0xC0000000~0xE3FFFFFF */ +/* Change MPU setting for RTOS#1. */ + ldr r0, =0xC0000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE3FFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c9, 0 /* Write R0 into PRBAR2 */ + mcr p15, 0, r1, c6, c9, 1 /* Write R1 into PRLAR2 */ + mcr p15, 4, r0, c6, c9, 0 /* Write R0 into HPRBAR2 */ + mcr p15, 4, r1, c6, c9, 1 /* Write R1 into HPRLAR2 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +/* region 3: 0xE4000000~0xE4FFFFFF */ + ldr r0, =0xE4000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE4FFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c9, 4 /* Write R0 into PRBAR3 */ + mcr p15, 0, r1, c6, c9, 5 /* Write R1 into PRLAR3 */ + mcr p15, 4, r0, c6, c9, 4 /* Write R0 into HPRBAR3 */ + mcr p15, 4, r1, c6, c9, 5 /* Write R1 into HPRLAR3 */ +/* region 5: 0xE6300000~0xE632FFFF */ + ldr r0, =0xE6300002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE632FFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c10, 4 /* Write R0 into PRBAR5 */ + mcr p15, 0, r1, c6, c10, 5 /* Write R1 into PRLAR5 */ + mcr p15, 4, r0, c6, c10, 4 /* Write R0 into HPRBAR5 */ + mcr p15, 4, r1, c6, c10, 5 /* Write R0 into HPRLAR5 */ +/* region 6: 0xE6330000~0xE635FFFF */ + ldr r0, =0xE6330002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE635FFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c11, 0 /* Write R0 into PRBAR6 */ + mcr p15, 0, r1, c6, c11, 1 /* Write R1 into PRLAR6 */ + mcr p15, 4, r0, c6, c11, 0 /* Write R0 into HPRBAR6 */ + mcr p15, 4, r1, c6, c11, 1 /* Write R1 into HPRLAR6 */ +/* region 8: 0xEB200000~0xEB3FFFFF */ + ldr r0, =0xEB200002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xEB3FFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c12, 0 /* Write R0 into PRBAR8 */ + mcr p15, 0, r1, c6, c12, 1 /* Write R1 into PRLAR8 */ + mcr p15, 4, r0, c6, c12, 0 /* Write R0 into HPRBAR8 */ + mcr p15, 4, r1, c6, c12, 1 /* Write R1 into HPRLAR8 */ + + isb + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + isb + +/* Instruction cache disable */ + mrc p15, 4, r0, c1, c0, 0 /* Read HSCTLR */ + mrc p15, 0, r1, c1, c0, 0 /* Read SCTLR */ + bic r0, r0, #SCTLR_I /* I=0 */ + bic r1, r1, #SCTLR_I /* I=0 */ + mcr p15, 4, r0, c1, c0, 0 /* Write HSCTLR */ + mcr p15, 0, r1, c1, c0, 0 /* Write SCTLR */ + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + isb + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* Jump to RTOS#1 */ + bx r11 +#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1) +loader_end: + wfi + b loader_end +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +anker: + wfi + b anker + +/* Undefined Instruction */ +Undefined_Handler: + mrs r0, ELR_hyp + b Undefined_error + +/* Supervisor Call */ +Supervisor_Handler: + mov r0, #SUP_EXCEPTION + b handler_error + +/* Prefetch Abort */ +Prefetch_Handler: + b pabt_report_exception + +/* Data Abort */ +Abort_Handler: + mrs r0, ELR_hyp + b dabt_report_exception + +/* Hyp Trap */ +HypTrap_Handler: + mov r0, #HYP_EXCEPTION + b handler_error + +/*IRQ interrupt */ +IRQ_Handler: + mov r0, #IRQ_EXCEPTION + b handler_error + +/* FIQ interrupt */ +FIQ_Handler: + mov r0, #FIQ_EXCEPTION + b handler_error + +/******************************************************** + * abort exception + ********************************************************/ +dabt_report_exception: + mrc p15, 0, r1, c5, c0, 0 /* Read DFSR */ + mrc p15, 0, r2, c6, c0, 0 /* Read DFAR */ + b dabort_error + +pabt_report_exception: + mrc p15, 0, r0, c5, c0, 1 /* Read IFSR */ + mrc p15, 0, r1, c6, c0, 2 /* Read IFAR */ + b pabort_error + + .end diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4m.ld b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4m.ld new file mode 100644 index 0000000..bd7f0a2 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/loader_v4m.ld @@ -0,0 +1,129 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Loader linker directive + ******************************************************************************/ +/****************************************************************************** + * @file loader_v4m.ld + * - Version : 0.01 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + *****************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(Startup) + +MEMORY { + SYSRAM (rwxa): ORIGIN = 0xE6300000, LENGTH = 0x00030000 + CXIPLDATA (rwa): ORIGIN = 0xE6330000, LENGTH = 0x00003000 + CXIPLSTACK (rwa): ORIGIN = 0xE6333000, LENGTH = 0x00002000 + SHARED_RAM (rwa): ORIGIN = 0x41C00000, LENGTH = 0x0000C000 + SHARED_SDRAM (rwa): ORIGIN = 0x41E00000, LENGTH = 0x00200000 +} + +SECTIONS +{ + .loader_start : { + __RO_START__ = .; + build/obj/loader/loader_v4m.o(.text*) + . = NEXT(1024); + *(.vectors) + . = ALIGN(4096); + } > SYSRAM + + .loader_ro : { + *(.text*) + *(.rodata*) + . = ALIGN(8); + __CONST_START__ = .; + . = ALIGN(16); + *(.qoswt_tbl) + . = ALIGN(8); + *(.qosbw_tbl) + . = ALIGN(8); + *(.constdata.CONFIG_DATA) + . = ALIGN(8); + *(.rgid_w_tbl) + . = ALIGN(8); + *(.rgid_r_tbl) + . = ALIGN(8); + *(.rgid_m_tbl) + . = ALIGN(8); + *(.rgid_sec_tbl) + . = ALIGN(8); + *(.rgid_axi_tbl) + __RO_END_UNALIGNED__ = .; + . = NEXT(4096); + __RO_END__ = .; + __DATA_COPY_START__ = .; + } > SYSRAM + + .data : { + __DATA_START__ = .; + *(.data*) + . = NEXT(16); + __DATA_END__ = .; + } > CXIPLDATA AT > SYSRAM + + __DATA_SIZE__ = SIZEOF(.data); + + stacks (NOLOAD) : ALIGN(16) { + __STACKS_START__ = .; + KEEP(*(Cx_loader_stack)) + __STACKS_END__ = .; + } > CXIPLSTACK + + .bss.SHARED_TOP : { + __SHARED_TOP_START__ = .; + *(.bss.SHARED_TOP) + *(.bss.SHARED_LCS) + *(.bss.SHARED_CMAC) + *(.bss.SHARED_HASH) + . = NEXT(0x00200000); + __SHARED__END__ = .; + } > SHARED_SDRAM + + .SHARED_RAM : { + __FWRAM_START__ = .; + . += 0; + . = NEXT(0x0000C000); + __FWRAM_END__ = .; + } > SHARED_RAM + + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } > CXIPLDATA + + __BSS_SIZE__ = SIZEOF(.bss); +} diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/loader/stack.S b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/stack.S new file mode 100644 index 0000000..7fe0238 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/loader/stack.S @@ -0,0 +1,48 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Make up stack space + ******************************************************************************/ +/****************************************************************************** + * @file stack.S + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 21.02.2022 0.02 Changed stacks name + * : 09.05.2022 0.03 Changed stacks name + * : 31.10.2022 0.04 License notation change. + *****************************************************************************/ + + .section Cx_loader_stack, "aw", %nobits + .align 5 +stacks: + .space (8*1024), 0 + + .end diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/mk.sh b/IPL/Customer/Mobis/V4H_Cx_Loader/mk.sh new file mode 100644 index 0000000..eefbe01 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/mk.sh @@ -0,0 +1,46 @@ +#!/bin/bash +set -e +set -o pipefail +export CROSS_COMPILE=`pwd`/../gcc-arm-none-eabi-10.3-2021.10/bin/arm-none-eabi- +export LANG=C + +_no_clean=0 +_loglevel=1 +_secure="SECURE" +_default_b="LSI=V4H FORCE_115200=1 EMMC_TRANS_MODE=HS400 \ +OPTEE_LOAD_ENABLE=1 \ +BL2_LOAD_ENABLE=1 \ +QNX_OS_LOAD_ENABLE=1 \ +" +_echo="@" +while getopts "sl:vcph" opt; do + case $opt in + s) _secure="NORMAL" + ;; + l) _loglevel=$OPTARG + ;; + p) _build_param="${_build_param} MEASURE_TIME=1" + ;; + v) _echo="" + ;; + c) _no_clean=1 + ;; + h) + echo "usage: $0 [option]" + echo " -s toggle boot_mode (default: $_secure)" + echo " -l set loglevel (default: $_loglevel)" + echo " -p enable MEASURE_TIME" + echo "" + echo " -c do not clean before build" + echo " -v build verbosely" + exit 0 + esac +done +shift $((OPTIND-1)) + +if [ $_no_clean -ne 1 ]; then + make clean +fi +BUILD_PARAM="${BUILD_PARAM} ${_build_param} LOG_LEVEL=$_loglevel" + +make ${_default_b} ${BUILD_PARAM} BOOT_MODE=$_secure V=$_echo $* diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/protect/region_id/region_id.c b/IPL/Customer/Mobis/V4H_Cx_Loader/protect/region_id/region_id.c new file mode 100644 index 0000000..0db7396 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/protect/region_id/region_id.c @@ -0,0 +1,439 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Access protection Function function + ******************************************************************************/ + /****************************************************************************** + * @file region_id.c + * - Version : 0.05 + * @brief Each module to R/W access protection by Region ID. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 15.12.2022 0.01 First Release + * : 24.02.2023 0.02 Polling the RGID setting process finish + * : 23.01.2024 0.03 Added ram_protection_check function. + * : 31.01.2024 0.04 Fixed the error in SECDIVn register + * calculating value. + * : 06.01.2025 0.05 Added reading back IMP Region ID register + * value. + * Added reading back IPMMU Region ID register + * value. + *****************************************************************************/ + +#include +#include "access_protection.h" +#include "axmm_register.h" +#include "cnf_tbl.h" +#include "mem_io.h" +#include "log.h" +#include "rtvram_register.h" + +#define RGID_SET_RGID_FIN_FLG_ADDR (0xE635EFFCU) +#define RGID_SET_RGID_FIN_FLG_VAL (0x64U) + +/* RAM protection for RT-VRAM0/RT-VRAM1 */ +#define SHIFT_FOR_SECDIVD (12U) +/* RAM protection for System RAM */ +#define SHIFT_FOR_SPTDIVCR (12U) +/* RAM protection for SDRAM */ +#define SHIFT_FOR_DPTDIVCR (16U) + +/* Value for calculating the offset address to set in SECDIVD. */ +#define RTSRAM_SECDIVD_SUBVALUE (0xE0000000U) /* RT-VRAM0 Base address */ +#define RTVRAM_SECDIVD_SUBVALUE (0xE2000000U) /* RT-VRAM1 Base address */ + +#define RTSRAM_ADDR_OFFSET_MASK (0xFFFFF000U) +#define RTVRAM_ADDR_MASK (0xFFFFF000U) + +void rgid_protection_check(void) +{ + uint32_t loop; + uint32_t reg; + + /* Polling until RGID setting completion flag is set by ICUMX IPL. */ + do{ + reg = mem_read8(RGID_SET_RGID_FIN_FLG_ADDR); + } while(reg != RGID_SET_RGID_FIN_FLG_VAL); + + for(loop = 0U; loop < RGID_MASTER_MAX; loop++) + { + /* Get RGIDM_MODID value */ + reg = mem_read32((uintptr_t)g_rgid_master_tbl[loop].phys_addr); /* Read */ + if (reg != g_rgid_master_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("RGIDM_MODID:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_rgid_master_tbl[loop].phys_addr, reg, g_rgid_master_tbl[loop].value); + panic; + } + } + + for(loop = 0U; loop < RGID_READ_MAX; loop++) + { + /* Get RGIDR_MODID value */ + reg = mem_read32((uintptr_t)g_rgid_read_tbl[loop].phys_addr); /* Read */ + if (reg != g_rgid_read_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("RGIDR_MODID:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_rgid_read_tbl[loop].phys_addr, reg, g_rgid_read_tbl[loop].value); + panic; + } + } + + for(loop = 0U; loop < RGID_WRITE_MAX; loop++) + { + /* Get RGIDW_MODID value */ + reg = mem_read32((uintptr_t)g_rgid_write_tbl[loop].phys_addr); /* Read */ + if (reg != g_rgid_write_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("RGIDW_MODID:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_rgid_write_tbl[loop].phys_addr, reg, g_rgid_write_tbl[loop].value); + panic; + } + } + + for(loop = 0U; loop < RGID_SEC_MAX; loop++) + { + /* Get SEC_MODID value */ + reg = mem_read32((uintptr_t)g_rgid_sec_tbl[loop].phys_addr); /* Read */ + if (reg != g_rgid_sec_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("SEC_MODID:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_rgid_sec_tbl[loop].phys_addr, reg, g_rgid_sec_tbl[loop].value); + panic; + } + } + + for(loop = 0U; loop < RGID_AXI_MAX; loop++) + { + /* Get AXI_MODID value */ + reg = mem_read32((uintptr_t)g_rgid_axi_tbl[loop].phys_addr); /* Read */ + if (reg != g_rgid_axi_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("AXI_MODID:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_rgid_axi_tbl[loop].phys_addr, reg, g_rgid_axi_tbl[loop].value); + panic; + } + } + +#if (RCAR_LSI == RCAR_V4H) + for(loop = 0U; loop < IMP_MASTER_MAX; loop++) + { + /* Get IMP Region ID Master value */ + reg = mem_read32((uintptr_t)g_imp_rgid_m_tbl[loop].phys_addr); /* Read */ + if (reg != g_imp_rgid_m_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("IMP_RGID_MASTER:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_imp_rgid_m_tbl[loop].phys_addr, reg, g_imp_rgid_m_tbl[loop].value); + panic; + } + } + + for(loop = 0U; loop < IMP_SLAVE_MAX; loop++) + { + /* Get IMP Region ID Slave value */ + reg = mem_read32((uintptr_t)g_imp_rgid_s_tbl[loop].phys_addr); /* Read */ + if (reg != g_imp_rgid_s_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("IMP_RGID_SLAVE:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_imp_rgid_s_tbl[loop].phys_addr, reg, g_imp_rgid_s_tbl[loop].value); + panic; + } + } +#endif /* (RCAR_LSI == RCAR_V4H) */ + + for(loop = 0U; loop < IPMMU_RGID_MAX; loop++) + { + /* Get IPMMU Region ID */ + reg = mem_read32((uintptr_t)g_ipmmu_rgid_tbl[loop].phys_addr); /* Read */ + if (reg != g_ipmmu_rgid_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("IMRGID_IPMMU:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_ipmmu_rgid_tbl[loop].phys_addr, reg, g_ipmmu_rgid_tbl[loop].value); + panic; + } + } + + for(loop = 0U; loop < IPMMU_RGID_MAX; loop++) + { + /* Get IPMMU Region ID Secure */ + reg = mem_read32((uintptr_t)g_ipmmu_rgid_sec_tbl[loop].phys_addr); /* Read */ + if (reg != g_ipmmu_rgid_sec_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("IMSECGRP_IPMMU:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_ipmmu_rgid_sec_tbl[loop].phys_addr, reg, g_ipmmu_rgid_sec_tbl[loop].value); + panic; + } + } + + for(loop = 0U; loop < IPMMU_RGID_MAX; loop++) + { + /* Get IPMMU Region ID Enable */ + reg = mem_read32((uintptr_t)g_ipmmu_rgid_en_tbl[loop].phys_addr); /* Read */ + if (reg != g_ipmmu_rgid_en_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("IMRGIDEN_IPMMU:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_ipmmu_rgid_en_tbl[loop].phys_addr, reg, g_ipmmu_rgid_en_tbl[loop].value); + panic; + } + } + +} +/* End of function rgid_protection_check(void) */ + +void ram_protection_check(void) +{ + uint32_t loop; + uint32_t expect_val; + uint32_t area_addr; + uint32_t area_reg_val; + /* For RT-VRAM0 / RT-VRAM1 */ + uint32_t read_addr; + uint32_t read_reg_val; + uint32_t write_addr; + uint32_t write_reg_val; + /* For System RAM / SDRAM */ + uint32_t rw_addr; + uint32_t rw_reg_val; + uint32_t sec_addr; + uint32_t sec_reg_val; + + /* Check RAM protection for RT-VRAM0 */ + /* Check SECDIV[n]D_0 register */ + for (loop = 0; loop < RAM_PROTECTION_MAX - 1U; loop++) + { + area_addr = get_rtvram0_secdivd_addr(loop); + area_reg_val = mem_read32((uintptr_t)area_addr); + expect_val = g_rtvram0_protection_table[loop + 1U].addr - RTSRAM_SECDIVD_SUBVALUE; + expect_val = ((expect_val & RTSRAM_ADDR_OFFSET_MASK) >> 12U); + + if (area_reg_val != expect_val) + { + ERROR("RAM protection check error\n"); + ERROR("SECDIVnD_0:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , area_addr + , area_reg_val + , expect_val); + panic; + } + } + + + /* Check SECCTRR[m]D_0 / SECCTRW[m]D_0 register */ + for (loop = 0; loop < RAM_PROTECTION_MAX; loop++) + { + read_addr = get_rtvram0_secctrrd_addr(loop); + read_reg_val = mem_read32((uintptr_t)read_addr); + write_addr = get_rtvram0_secctrwd_addr(loop); + write_reg_val = mem_read32((uintptr_t)write_addr); + + if (read_reg_val != g_rtvram0_protection_table[loop].setting_value.read_val) + { + ERROR("RAM protection check error\n"); + ERROR("SECCTRRmD_0:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , read_addr + , read_reg_val + , g_rtvram0_protection_table[loop].setting_value.read_val); + panic; + } + if (write_reg_val != g_rtvram0_protection_table[loop].setting_value.write_val) + { + ERROR("RAM protection check error\n"); + ERROR("SECCTRWmD_0:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , write_addr + , write_reg_val + , g_rtvram0_protection_table[loop].setting_value.write_val); + panic; + } + } + + /* Check RAM protection for RT-VRAM1 */ + /* Check SECDIV[n]D_1 register */ + for (loop = 0; loop < RAM_PROTECTION_MAX - 1U; loop++) + { + area_addr = get_rtvram1_secdivd_addr(loop); + area_reg_val = mem_read32((uintptr_t)area_addr); + expect_val = g_rtvram1_protection_table[loop + 1U].addr - RTVRAM_SECDIVD_SUBVALUE; + expect_val = ((expect_val & RTVRAM_ADDR_MASK) >> 12U); + + if (area_reg_val != expect_val) + { + ERROR("RAM protection check error\n"); + ERROR("SECDIVnD_1:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , area_addr + , area_reg_val + , expect_val); + panic; + } + } + + /* Check SECCTRR[m]D_1 / SECCTRW[m]D_1 register */ + for (loop = 0; loop < RAM_PROTECTION_MAX; loop++) + { + read_addr = get_rtvram1_secctrrd_addr(loop); + read_reg_val = mem_read32((uintptr_t)read_addr); + write_addr = get_rtvram1_secctrwd_addr(loop); + write_reg_val = mem_read32((uintptr_t)write_addr); + + if (read_reg_val != g_rtvram1_protection_table[loop].setting_value.read_val) + { + ERROR("RAM protection check error\n"); + ERROR("SECCTRRmD_1:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , read_addr + , read_reg_val + , g_rtvram1_protection_table[loop].setting_value.read_val); + panic; + } + if (write_reg_val != g_rtvram1_protection_table[loop].setting_value.write_val) + { + ERROR("RAM protection check error\n"); + ERROR("SECCTRWmD_1:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , write_addr + , write_reg_val + , g_rtvram1_protection_table[loop].setting_value.write_val); + panic; + } + } + + /* Check RAM protection for System RAM */ + /* Check SPTDIVCR[n] register */ + for (loop = 0; loop < RAM_PROTECTION_MAX - 1U; loop++) + { + area_addr = get_sptdivcr_addr(loop); + area_reg_val = mem_read32((uintptr_t)area_addr); + + if (area_reg_val != (g_system_ram_protection_table[loop + 1U].addr >> SHIFT_FOR_SPTDIVCR)) + { + ERROR("RAM protection check error\n"); + ERROR("SPTDIVCR:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , area_addr + , area_reg_val + , (g_system_ram_protection_table[loop + 1U].addr >> SHIFT_FOR_SPTDIVCR)); + panic; + } + } + + /* Check SPTRGNCR[n] / SPTSECCR[n] register */ + for (loop = 0; loop < RAM_PROTECTION_MAX; loop++) + { + rw_addr = get_sptrgncr_addr(loop); + rw_reg_val = mem_read32((uintptr_t)rw_addr); + sec_addr = get_sptseccr_addr(loop); + sec_reg_val = mem_read32((uintptr_t)sec_addr); + + if (rw_reg_val != g_system_ram_protection_table[loop].setting_value.rw_val) + { + ERROR("RAM protection check error\n"); + ERROR("SPTRGNCR:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , rw_addr + , rw_reg_val + , g_system_ram_protection_table[loop].setting_value.rw_val); + panic; + } + if (sec_reg_val != g_system_ram_protection_table[loop].setting_value.sec_val) + { + ERROR("RAM protection check error\n"); + ERROR("SPTSECCR:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , sec_addr + , sec_reg_val + , g_system_ram_protection_table[loop].setting_value.sec_val); + panic; + } + } + + /* Check RAM protection for SDRAM */ + /* Check DPTDIVCR[n] register */ + for (loop = 0; loop < DRAM_PROTECTION_MAX - 1U; loop++) + { + area_addr = get_dptdivcr_addr(loop); + area_reg_val = mem_read32((uintptr_t)area_addr); + + if (area_reg_val != (g_dram_protection_table[loop + 1U].addr >> SHIFT_FOR_DPTDIVCR)) + { + ERROR("RAM protection check error\n"); + ERROR("DPTDIVCR:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , area_addr + , area_reg_val + , (g_dram_protection_table[loop + 1U].addr >> SHIFT_FOR_DPTDIVCR)); + panic; + } + } + + /* Check DPTRGNCR[n] / DPTSECCR[n] register */ + for (loop = 0; loop < DRAM_PROTECTION_MAX; loop++) + { + rw_addr = get_dptrgncr_addr(loop); + rw_reg_val = mem_read32((uintptr_t)rw_addr); + sec_addr = get_dptseccr_addr(loop); + sec_reg_val = mem_read32((uintptr_t)sec_addr); + + if (rw_reg_val != g_dram_protection_table[loop].setting_value.rw_val) + { + ERROR("RAM protection check error\n"); + ERROR("DPTRGNCR:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , rw_addr + , rw_reg_val + , g_dram_protection_table[loop].setting_value.rw_val); + panic; + } + if (sec_reg_val != g_dram_protection_table[loop].setting_value.sec_val) + { + ERROR("RAM protection check error\n"); + ERROR("DPTSECCR:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , sec_addr + , sec_reg_val + , g_dram_protection_table[loop].setting_value.sec_val); + panic; + } + } + +} +/* End of function ram_protection_check(void) */ + + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/ICUMXB_modifed.diff b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/ICUMXB_modifed.diff new file mode 100644 index 0000000..a439b64 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/ICUMXB_modifed.diff @@ -0,0 +1,236 @@ +diff --git b/V4H_Cx_Loader/secure/icumif/renesas_types.h a/V4H_Cx_Loader/secure/icumif/renesas_types.h +index 4c63220..5d28109 100644 +--- b/V4H_Cx_Loader/secure/icumif/renesas_types.h ++++ a/V4H_Cx_Loader/secure/icumif/renesas_types.h +@@ -18,28 +18,7 @@ + #if !defined (R_TYPEDEFS_H) + #define R_TYPEDEFS_H + +-#ifdef __cplusplus +-extern "C" { +-#endif /* __cplusplus */ +- +-typedef signed char int8_t; +-typedef unsigned char uint8_t; +-typedef signed short int16_t; +-typedef unsigned short uint16_t; +-typedef signed int int32_t; +-typedef unsigned int uint32_t; +-typedef signed long long int64_t; +-typedef unsigned long long uint64_t; +-typedef unsigned long uintptr_t; +- +-#define bool _Bool +-#define false (0) +-#define true (1) +- +-#define NULL ((void*)0) +- +-#ifdef __cplusplus +-} +-#endif /* __cplusplus */ ++#include ++#include + + #endif /* R_TYPEDEFS_H */ +diff --git b/V4H_Cx_Loader/secure/shared/src/mem_info_def.c a/V4H_Cx_Loader/secure/shared/src/mem_info_def.c +index dea5c7b..34ccc7e 100644 +--- b/V4H_Cx_Loader/secure/shared/src/mem_info_def.c ++++ a/V4H_Cx_Loader/secure/shared/src/mem_info_def.c +@@ -25,8 +25,8 @@ + #define ICUM_SHAREDMEMORY_1_SIZE (2097152u -1152u) + #define ICUM_SHAREDMEMORY_2_ADDR (0x41E00000u) + #define ICUM_SHAREDMEMORY_2_SIZE (2097152u) +-#define ICUM_SHAREDMEMORY_3_ADDR (0xE2100000u) +-#define ICUM_SHAREDMEMORY_3_SIZE (1048576u) ++#define ICUM_SHAREDMEMORY_3_ADDR (0xEB231000u) ++#define ICUM_SHAREDMEMORY_3_SIZE (0xD000u) + #define ICUM_EXPORT_DATA_ADDR (0x41C20000u) + #define ICUM_EXPORT_DATA_SIZE (114688u) + #define ICUM_DATA_WORKAREA_ADDR (0xEB2E0000u) +@@ -172,42 +172,9 @@ const uint32_t memory_information[ICUM_MEMORY_CONFIG_NUM] __attribute__((aligned + /*******************************************************************************/ + + /*******************************************************************************/ +-/* ISD request & response queue */ ++/* Communication buffer between host and ICU-M */ + /*******************************************************************************/ +-uint32_t ICUM_QUEUE[ICUM_SERVICEQUEUE_1_SIZE/sizeof(uint32_t)] __attribute__((aligned(32), section(".bss.SHARED_TOP"))); +- +-/*******************************************************************************/ +-/* Output buffer */ +-/*******************************************************************************/ +-uint8_t strbin[20096] __attribute__((aligned(32), section(".bss.SHARED_TOP"))); +- +-/*******************************************************************************/ +-/* Big buffers for tests */ +-/*******************************************************************************/ +-uint8_t BIG_BUFFER[4][SIZE_OF_BIG_BUFFER] __attribute__((aligned(256), section(".bss.SHARED_TOP"))); +- +-/*******************************************************************************/ +-/* Communication buffer between host and ICU-M */ +-/*******************************************************************************/ +-uint8_t ISD_BUFFER[SIZE_OF_ISD_BUFFER] __attribute__((aligned(32), section(".bss.SHARED_TOP"))); +- +-/*******************************************************************************/ +-/* Output buffer */ +-/*******************************************************************************/ +-uint8_t COM_BUFFER[SIZE_OF_COM_BUFFER] __attribute__((aligned(32), section(".bss.SHARED_TOP"))); +- +-/*******************************************************************************/ +-/* Big buffers ( 256 Byte aligned ) for tests */ +-/*******************************************************************************/ +-uint8_t DMAC_BUFFE[1][SIZE_OF_BIG_BUFFER] __attribute__((aligned(256), section(".bss.SHARED_TOP"))); +-uint8_t DMAC_BUFFE_2[1][SIZE_OF_BIG_BUF2] __attribute__((aligned(256), section(".bss.SHARED_TOP"))); +- +-/*******************************************************************************/ +-/* Big buffers on SDRAM for tests */ +-/*******************************************************************************/ +-uint8_t BIG_BUF_SD[3][SIZE_OF_BIG_BUFFER] __attribute__((aligned(32), section(".bss.SDRAM"))); +- +-/*******************************************************************************/ +-/* Communication buffer on SDRAM between host and ICU-M */ +-/*******************************************************************************/ +-uint8_t ISD_BUF_SD[SIZE_OF_ISD_BUFFER] __attribute__((aligned(32), section(".bss.SDRAM"))); ++uint8_t ISD_BUFFER[SIZE_OF_ISD_BUFFER] __attribute__((aligned(64), section(".bss.SHARED_TOP"))); ++uint8_t LCS_BUFFER[SIZE_OF_LCS_BUFFER] __attribute__((aligned(64), section(".bss.SHARED_LCS"))); ++uint8_t CMAC_BUFFER[SIZE_OF_CMAC_BUFFER] __attribute__((aligned(64), section(".bss.SHARED_CMAC"))); ++uint8_t HASH_BUFFER[SIZE_OF_HASH_BUFFER] __attribute__((aligned(64), section(".bss.SHARED_HASH"))); +diff --git b/V4H_Cx_Loader/secure/shared/src/shared.h a/V4H_Cx_Loader/secure/shared/src/shared.h +index b4dec66..5c71428 100644 +--- b/V4H_Cx_Loader/secure/shared/src/shared.h ++++ a/V4H_Cx_Loader/secure/shared/src/shared.h +@@ -29,23 +29,13 @@ + /********************************************************************************** + * Global external references + ***********************************************************************************/ +-/** ISD request & response queue */ +-extern uint32_t ICUM_QUEUE[]; +-/** Big buffers for tests */ +-extern uint8_t BIG_BUFFER[][SIZE_OF_BIG_BUFFER]; +-/** Communication buffer between host and ICU-M */ +-extern uint8_t ISD_BUFFER[SIZE_OF_ISD_BUFFER]; +-/** Extended communication buffer */ +-extern uint8_t COM_BUFFER[SIZE_OF_COM_BUFFER]; +- +-extern uint8_t DMAC_BUFFE[][SIZE_OF_BIG_BUFFER]; +-extern uint8_t DMAC_BUFFE_2[][SIZE_OF_BIG_BUF2]; +- +-extern uint8_t BIG_BUF_SD[][SIZE_OF_BIG_BUFFER]; +-extern uint8_t ISD_BUF_SD[SIZE_OF_ISD_BUFFER]; +- +-#if defined(TARGET_DEVICE_S4X) || defined(TARGET_DEVICE_V4H) +-extern uint16_t notification_from_cr52[9]; +-#endif ++#define SIZE_OF_LCS_BUFFER (4U) ++#define SIZE_OF_CMAC_BUFFER (16U) ++#define SIZE_OF_HASH_BUFFER (32U * 2U) ++ ++extern uint8_t ISD_BUFFER[SIZE_OF_ISD_BUFFER]; ++extern uint8_t LCS_BUFFER[SIZE_OF_LCS_BUFFER]; ++extern uint8_t CMAC_BUFFER[SIZE_OF_CMAC_BUFFER]; ++extern uint8_t HASH_BUFFER[SIZE_OF_HASH_BUFFER]; + + #endif /* SHARED_H */ +diff --git b/V4H_Cx_Loader/secure/user_api/user_icumif_api.c a/V4H_Cx_Loader/secure/user_api/user_icumif_api.c +index 4501e8a..a875a20 100644 +--- b/V4H_Cx_Loader/secure/user_api/user_icumif_api.c ++++ a/V4H_Cx_Loader/secure/user_api/user_icumif_api.c +@@ -43,90 +43,12 @@ extern void inv_dcache_range(uintptr_t addr, uint32_t size); + + void USER_ICUMIF_FlushDCache(uint32_t addr, uint32_t size) + { +- uint32_t cache_line_addr; +- uint32_t flush_size; +- uint32_t limit_size; +- +-#if defined(TARGET_CORTEX_A) && defined(AARCH64) +- unsigned long prog_status_reg_64; +- __asm volatile ("mrs %[result], DAIF" : [result] "=r" (prog_status_reg_64)); +- __asm ("msr DAIFSet, #0x3"); +-#else +- uint32_t prog_status_reg_32; +- __asm volatile ("mrs %[result], CPSR" : [result] "=r" (prog_status_reg_32)); +- __asm ("cpsid if"); +-#endif +- +- if (D_CACHE_LIMIT_ADDR > addr) +- { +- cache_line_addr = addr & D_CACHE_LINE_ADDR_MASK; +- flush_size = size + (addr - cache_line_addr); +- +- /* round to the limit size */ +- limit_size = D_CACHE_LIMIT_ADDR - cache_line_addr; +- if (flush_size > limit_size) +- { +- flush_size = limit_size; +- } +- +- flush_dcache_range((uintptr_t)cache_line_addr, flush_size); +- } +- +-#if defined(TARGET_CORTEX_A) && defined(AARCH64) +- if (CR52_CPSR_IRQ_DISABLE_STATUS != (prog_status_reg_64 & CR52_CPSR_IRQ_DISABLE_STATUS)) +- { +- __asm ("msr DAIFClr, #0x3"); +- } +-#else +- if (CR52_CPSR_IRQ_DISABLE_STATUS != (prog_status_reg_32 & CR52_CPSR_IRQ_DISABLE_STATUS)) +- { +- __asm ("cpsie if"); +- } +-#endif ++ /* do nothing */ + } + + void USER_ICUMIF_InvalidateDCache(uint32_t addr, uint32_t size) + { +- uint32_t cache_line_addr; +- uint32_t invalidate_size; +- uint32_t limit_size; +- +-#if defined(TARGET_CORTEX_A) && defined(AARCH64) +- unsigned long prog_status_reg_64; +- __asm volatile ("mrs %[result], DAIF" : [result] "=r" (prog_status_reg_64)); +- __asm ("msr DAIFSet, #0x3"); +-#else +- uint32_t prog_status_reg_32; +- __asm volatile ("mrs %[result], CPSR" : [result] "=r" (prog_status_reg_32)); +- __asm ("cpsid if"); +-#endif +- +- if (D_CACHE_LIMIT_ADDR > addr) +- { +- cache_line_addr = addr & D_CACHE_LINE_ADDR_MASK; +- invalidate_size = size + (addr - cache_line_addr); +- +- /* round to the limit size */ +- limit_size = D_CACHE_LIMIT_ADDR - cache_line_addr; +- if (invalidate_size > limit_size) +- { +- invalidate_size = limit_size; +- } +- +- inv_dcache_range(cache_line_addr, invalidate_size); +- } +- +-#if defined(TARGET_CORTEX_A) && defined(AARCH64) +- if (CR52_CPSR_IRQ_DISABLE_STATUS != (prog_status_reg_64 & CR52_CPSR_IRQ_DISABLE_STATUS)) +- { +- __asm ("msr DAIFClr, #0x3"); +- } +-#else +- if (CR52_CPSR_IRQ_DISABLE_STATUS != (prog_status_reg_32 & CR52_CPSR_IRQ_DISABLE_STATUS)) +- { +- __asm ("cpsie if"); +- } +-#endif ++ /* do nothing */ + } + + uint32_t USER_ICUMIF_GetMyPEID(void) +@@ -179,4 +101,3 @@ void USER_ICUMIF_Sync(void) + { + USER_ICUMIF_SYNC(); + } +- diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api.h new file mode 100644 index 0000000..ea7d32b --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api.h @@ -0,0 +1,672 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ + +#if !defined(R_ICUMIF_API_H) +#define R_ICUMIF_API_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/**********************************************************************************/ +/* Ensure the structure alignment */ +/**********************************************************************************/ + +#pragma pack(8) + +/**********************************************************************************/ +/* Headers */ +/**********************************************************************************/ + +/**********************************************************************************/ +/* Defines */ +/**********************************************************************************/ + +#include "renesas_types.h" + +/*===========================================================================*/ +/* Transition state of ISD service request / response queue */ +/*===========================================================================*/ +#define R_ICUMIF_REQRES_PE_REQ_ENQUE (0x01U) /* PE enqueued ISD to service request queue */ +#define R_ICUMIF_REQRES_ICUM_REQ_DEQUE (0x02U) /* ICU-M dequeued ISD from service request queue */ +#define R_ICUMIF_REQRES_ICUM_RES_ENQUE (0x03U) /* ICU-M enqueued ISD to service response queue */ +#define R_ICUMIF_REQRES_PE_RES_DEQUE (0x04U) /* PE dequeued ISD from service response queue */ + +#define R_ICUMIF_REQRES_INTERRPUT (0x00U) +#define R_ICUMIF_REQRES_NOINTERRPUT (0x01U) + +/*===========================================================================*/ +/* Priority of ICU-M service */ +/*===========================================================================*/ +#define R_ICUMIF_SERV_PRIORITY_HIGHEST (0x00U) +#define R_ICUMIF_SERV_PRIORITY_HIGH (0x3FU) +#define R_ICUMIF_SERV_PRIORITY_NORMAL (0x7fU) +#define R_ICUMIF_SERV_PRIORITY_LOWEST (0xffU) + +/*===========================================================================*/ +/* The defines of job cycle (r_job_cycle_t) used for each service parameter */ +/*===========================================================================*/ +#define JOB_ALL_AT_ONCE (0x00000000u) +#define JOB_INIT (0x00000001u) +#define JOB_UPDATE (0x00000002u) +#define JOB_FINISH (0x00000004u) + +/**********************************************************************************/ +/* Macros */ +/**********************************************************************************/ + +/*===========================================================================*/ +/* To set the memory cluster verification flags in mem_cluster_verif_t */ +/*===========================================================================*/ +#define MEM_CLUSTER(i) (1 << (i)) + +/**********************************************************************************/ +/* ICU-M interface: types */ +/**********************************************************************************/ + +/*===========================================================================*/ +/* Enumerates: ICU-M service ID */ +/*===========================================================================*/ + + /*******************************************/ + /* Note: the below enumerates should align */ + /* with the table service_handler[] */ + /*******************************************/ + +typedef enum +{ + SERVICE_00_SYSTEM_INIT = 0x00, + SERVICE_00_SYSTEM_CONFIG, + SERVICE_00_GET_INFO, + SERVICE_00_KEY_MNGT, + SERVICE_00_CANCEL_SHE, + SERVICE_00_STAGE_TRANSITION, + SERVICE_00_GET_STAGE, + SERVICE_00_GET_ID, + SERVICE_00_CMD_DEBUG = 0x0C, + SERVICE_00_SECURE_BOOT_API, + + SERVICE_01_AES_CIPHER = 0x10, + SERVICE_01_AES_AUTH_CIPHER, + SERVICE_01_AES_CMAC, + SERVICE_01_AES_CMAC_SHORT, + SERVICE_01_RSA_VERIFY, + SERVICE_01_RSA_SIGN, + SERVICE_01_RSA_ENCRYPT, + SERVICE_01_RSA_DECRYPT, + SERVICE_01_ECDSA_VERIFY, + SERVICE_01_ECDSA_SIGN, + SERVICE_01_ECDH, + SERVICE_01_HASH, + SERVICE_01_HMAC, + SERVICE_01_TLS_RSA_EXCHANGE, + SERVICE_01_TLS_ECDH_EXCHANGE, + SERVICE_01_TLS_VERIFY_DATA, + + SERVICE_02_RAND_INIT_RNG = 0x20, + SERVICE_02_RAND_EXTEND_SEED, + SERVICE_02_RAND_RND, + SERVICE_02_RAND_TRNG, + SERVICE_02_RAND_INSTANTIATE, + SERVICE_02_RAND_RESEED, + SERVICE_02_RAND_UNINSTANTIATE, + SERVICE_02_RAND_GENERATE, + + SERVICE_03_AES_KEY_UPDATE_PLAIN = 0x30, + SERVICE_03_AES_KEY_UPDATE_SHE, + SERVICE_03_AES_RAM_KEY_EXP_SHE, + SERVICE_03_PK_IMPORT, + SERVICE_03_PK_EXPORT, + SERVICE_03_RSA_KEY_GENERATE, + SERVICE_03_ECC_KEY_GENERATE, + SERVICE_03_ISO15118_UPDATE, + SERVICE_03_HMAC_IMPORT, + SERVICE_03_PK_IMPORT_EXT, + SERVICE_03_AES_KEY_UPDATE_SHE_EXT, + SERVICE_03_AES_RAM_KEY_EXP_SHE_EXT, + + SERVICE_04_ICUMDF_WRITE = 0x45, + + SERVICE_05_MEMCLSTR_DEFINITION = 0x50, + SERVICE_05_MEMCLSTR_INSTALL, + SERVICE_05_MEMCLSTR_VERIFY, + SERVICE_05_MEMCLSTR_VERIFY_AUTO, + + SERVICE_07_MONO_CTR_MGMT = 0x70, + + SERVICE_01_EDDSA_VERIFY = 0x80, + SERVICE_01_EDDSA_SIGN, + + LAST_ITEM_SERV_ID = 0x01000000 +} r_icumif_service_id_t; + +/*===========================================================================*/ +/* Enumerates: ICU-M service results */ +/*===========================================================================*/ + +typedef enum +{ + SERV_OK, /* service completed with no error */ + SERV_SYS_CFG_NOT_INITIALIZED, /* system configuration not initialized */ + SERV_ID_ERROR, /* wrong service ID */ + SERV_REQUESTER_ID_ERROR, /* wrong requester ID */ + SERV_PRM_ERROR, /* wrong service parameter error */ + SERV_KEY_INVALID, /* key invalid */ + SERV_KEY_NOT_USABLE, /* key not usable for the service */ + SERV_INVALID_KEY_GROUP, /* key group is not valid */ + SERV_INVALID_KEY_INDEX, /* wrong key index provided */ + SERV_KEY_SLOT_EMPTY, /* key slot empty */ + SERV_KEY_WRITE_PROTECTED, /* key is write protected */ + SERV_KEY_UPDATE_ERROR, /* key update error */ + SERV_SRC_MEM_ERROR, /* error on source memory range */ + SERV_DEST_MEM_ERROR, /* error on destination memory range */ + SERV_JOB_QUEUE_FULL, /* cannot accept another service request */ + SERV_UNAVAILABLE, /* service unavailable */ + SERV_INSTANCE_ALREADY_RUNNING, /* service instance already running */ + SERV_SYS_ERROR, /* the service caused a system error (exception) */ + SERV_MPU_ERROR, /* the service caused a MPU error (exception) */ + + SERV_NVM_PROG_ERROR, /* error while programming the Flash */ + SERV_NVM_SYS_ERROR, /* error in the Flash sequencer */ + SERV_NVM_SYS_ERROR_CRITICAL, /* error in the Flash sequencer */ + SERV_NVM_UNAVAILABLE, /* Flash memory unavailable (e.g. PE1 reprogramming it) */ + SERV_DATA_INVALID, /* error on the DVC (data inconsistency) */ + SERV_NVM_DATA_WARNING, /* one data slot broken */ + SERV_NVM_SIZE_ERROR, /* secure DF too small for the number of keys to manage */ + + SERV_CRYPT_ERROR, /* error in the cryptographic library */ + SERV_INVALID_MEM_CLUST_INDEX, /* wrong memory cluster index */ + SERV_INVALID_INSTALL_METHOD, /* invalid memory cluster installation method */ + SERV_INVALID_VERIF_METHOD, /* invalid memory cluster verification method */ + SERV_INVALID_CLUSTER_SIZE, /* invalid data size processed during memory cluster installation */ + SERV_CLUSTER_NOT_DEFINED, /* memory cluster not defined */ + SERV_CLUSTER_ALREADY_DEFINED, /* memory cluster already defined */ + SERV_CLUSTER_NOT_INSTALLED, /* memory cluster not installed */ + SERV_CLUSTER_INSTALL_FAIL, /* memory cluster installation fail */ + SERV_CLUSTER_VERIFICATION_FAIL, /* memory cluster verification fail */ + SERV_CLUSTER_NOT_VERIFIED, /* memory cluster not verified */ + SERV_CLUSTER_ALREADY_VERIFIED, /* memory cluster already verified */ + SERV_CLUSTER_ALREADY_INSTALLED, /* memory cluster already installed */ + SERV_CLUSTER_VERIF_STATUS_LOCK, /* memory verification status locked */ + SERV_BKGROUND_CHECK_RUNNING, /* background check running - unable to continue */ + + SERV_INVALID_ENCODING_FORMAT = 0x2A, /* invalid data encoding format */ + SERV_ISD_NOT_ACCESSIBLE, /* service request not accessible by ICUP */ + SERV_RAM_SIZE_ERROR, /* secure config ram too small for the number of keys to manage */ + + SERV_KEY_GENERATION_ERROR, /* error while generating RSA / ECC private keys */ + SERV_KEY_VERIFICATION_FAIL, /* error on signature key verification */ + SERV_INVALID_CURVE_ID, /* invalid ECC curve id */ + SERV_ECC_POINT_INVALID, /* invalid ECC public key */ + + SERV_MEMORY_FULL, /* no more memory space */ + + SERV_INIT_DELAY, /* service initialization delayed (e.g. no AES context available) */ + + SERV_MYDATA_SET_EMPTY, /* no custom data set available */ + SERV_MYDATA_SLOT_EMPTY, /* data slot available */ + SERV_MYDATA_SIZE_ERR, /* invalid data size */ + SERV_MYDATA_INVALID_IDX, /* invalid data slot index */ + + SERV_REQUEST_QUEUE_FULL, /* service request queue full */ + + SERV_MONOCTR_INVALID_TYPE, /* invalid monotonic counter type */ + SERV_MONOCTR_INVALID_IDX, /* invalid monotonic counter index */ + SERV_MONOCTR_NOT_INITIALIZED, /* monotonic counter not initialized */ + SERV_MONOCTR_INVALID_INCREMENT, /* monotonic counter invalid increment value */ + SERV_MONOCTR_INVALID, /* monotonic counter invalid counter value in Flash */ + SERV_INVALID_OPERATION, /* invalid operation */ + + SERV_KEY_CACHE_FULL, /* unable to fix another key in cache */ + SERV_MEMCLTR_CACHE_FULL, /* unable to fix another memory cluster in cache */ + SERV_SEQUENCE_ERROR, /* Wrong calling sequence */ + + SERV_CR_VERIFY_FAIL, /* Failure on challenge & response */ + + SERV_AES_TIMEOUT_ERROR, /* wrong aes driver time out error */ + SERV_AES_STATUS_ERROR, /* wrong aes driver status error */ + SERV_AES_PRM_ERROR, /* wrong aes driver parameter error */ + + SERV_NO_COMP_TRNG, /* Call initialization services during the true random number generation */ + SERV_NO_INIT_RNG, /* Using random number generation service not initialized */ + SERV_TRN_ERROR, /* online test NG, or non-online test 3 times in consecutive random values match */ + SERV_NEED_RESEED, /* A reseed is required(CTR_DRBG method) */ + + SERV_RESTRICTED, /* service is restricted by life cycle stage */ + + /* Error ID unique to the R-Car series */ + SERV_NVM_REJECTED = 0xff00, /* Failed to acquire flash access authority */ + + SERV_REQUEST = 0xfff0, + SERV_NEW_REQUEST, + SERV_PENDING, + SERV_IN_PROCESS = 0xffff, + + LAST_ITEM_SERV_ERR = 0x01000000 +} r_icumif_service_result_t; + + +/*===========================================================================*/ +/* Enumerates: verification result (CMAC, signature) */ +/*===========================================================================*/ + +typedef enum +{ + VERIFICATION_PASS, + VERIFICATION_FAIL, + + LAST_ITEM_VERIF_STATUS = 0x01000000 +} r_verif_result_t; + +/*===========================================================================*/ +/* Enumerates: number formats */ +/*===========================================================================*/ + +typedef enum +{ + FORMAT_STRING_DECIMAL, + FORMAT_STRING_HEXA, + FORMAT_BINARY_PLAIN, + + LAST_ITEM_FORMAT_TYPE = 0x01000000 +} r_number_format_t; + +/*===========================================================================*/ +/* Enumerates: hash encoding formats (rsa sign/verify) */ +/*===========================================================================*/ + +typedef enum +{ + ENCODING_FORMAT_EMSA_PSS, + ENCODING_FORMAT_EMSA_PKCS1_V15, + + LAST_ITEM_HASH_ENCODING_TYPE = 0x01000000 +} r_hash_encoding_format_t; + +/*===========================================================================*/ +/* Enumerates: message encoding formats (rsa encrypt/decrypt) */ +/*===========================================================================*/ + +typedef enum +{ + ENCODING_FORMAT_EME_OAEP, + ENCODING_FORMAT_EME_PKCS1_V15, + + LAST_ITEM_MSG_ENCODING_TYPE = 0x01000000 +} r_message_encoding_format_t; + +/*===========================================================================*/ +/* Enumerates: hash primitives */ +/*===========================================================================*/ + +typedef enum +{ + HASH_PRIMITIVE_MD5, + HASH_PRIMITIVE_RIPEMD_128, + HASH_PRIMITIVE_RIPEMD_160, + HASH_PRIMITIVE_RIPEMD_256, + HASH_PRIMITIVE_RIPEMD_320, + HASH_PRIMITIVE_SHA1, + HASH_PRIMITIVE_SHA2_224, + HASH_PRIMITIVE_SHA2_256, + HASH_PRIMITIVE_SHA2_384, + HASH_PRIMITIVE_SHA2_512, + HASH_PRIMITIVE_SHA2_512_224, + HASH_PRIMITIVE_SHA2_512_256, + HASH_PRIMITIVE_SHA3_224, + HASH_PRIMITIVE_SHA3_256, + HASH_PRIMITIVE_SHA3_384, + HASH_PRIMITIVE_SHA3_512, + HASH_PRIMITIVE_SHAKE_128, + HASH_PRIMITIVE_SHAKE_256, + + LAST_ITEM_HASH_PRIMITIVE = 0x01000000 +} r_hash_primitive_t; + +/*===========================================================================*/ +/* Enumerates: signature algorithms (for PK key imports/exports) */ +/*===========================================================================*/ + +typedef enum +{ + SIGALGO_NONE, + SIGALGO_RSA_PSS, + SIGALGO_RSA_PKCS1_V15, + + LAST_ITEM_SIGNATURE_ALGO = 0x01000000 +} r_signature_algo_t; + +/*===========================================================================*/ +/* Enumerates: ECC curves */ +/*===========================================================================*/ + +typedef enum +{ + ECC_CURVE_NIST_P192, + ECC_CURVE_NIST_P224, + ECC_CURVE_NIST_P256, + ECC_CURVE_NIST_P384, + ECC_CURVE_NIST_P521, + ECC_CURVE_BRAINPOOL_P192, + ECC_CURVE_BRAINPOOL_P224, + ECC_CURVE_BRAINPOOL_P256, + ECC_CURVE_BRAINPOOL_P320, + ECC_CURVE_BRAINPOOL_P384, + ECC_CURVE_BRAINPOOL_P512, + ECC_CURVE_BRAINPOOL_P256_T, + ECC_CURVE_BRAINPOOL_P320_T, + ECC_CURVE_BRAINPOOL_P384_T, + ECC_CURVE_BRAINPOOL_P512_T, + ECC_CURVE_CURVE25519, + ECC_CURVE_ED25519, + + LAST_ITEM_ECC_TYPE = 0x01000000 +} r_ecc_curve_t; + +/*===========================================================================*/ +/* Enumerates: KDF algorithms */ +/*===========================================================================*/ + +typedef enum +{ + KDF_ALGO_KDF1, + KDF_ALGO_KDF2, + KDF_ALGO_KDF3, + KDF_ALGO_PKDF1, + KDF_ALGO_PKDF2, + + LAST_ITEM_KDF_ALGO = 0x01000000 +} r_kdf_algo_t; + +/*===========================================================================*/ +/* Enumerates: key group */ +/*===========================================================================*/ +typedef enum +{ + KEY_GRP_AES_ROM, + KEY_GRP_AES, + KEY_GRP_AES_RAM, + KEY_GRP_SHE, + KEY_GRP_RSA, + KEY_GRP_RSA_PUB, + KEY_GRP_RSA_ROM_PUB, + KEY_GRP_ECC, + KEY_GRP_ECC_RAM, + KEY_GRP_ECC_PUB, + KEY_GRP_ECC_ROM_PUB, + KEY_GRP_AES_CR, + KEY_GRP_HMAC, + KEY_GRP_TLS_MASTER, + KEY_GRP_RSA_PUB_EXT, + KEY_GRP_ECC_PUB_EXT, + + LAST_ITEM_KEY_GRP = 0x01000000 +} r_key_group_t; + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ + +/*===========================================================================*/ +/* Type definition: requester ID */ +/*===========================================================================*/ +typedef uint8_t r_icumif_requester_id_t; + +/*===========================================================================*/ +/* Type definition: vm ID */ +/*===========================================================================*/ +typedef uint8_t r_icumif_vm_id_t; + +/*===========================================================================*/ +/* Type definition: host interrupt channel definition */ +/*===========================================================================*/ +typedef uint8_t r_icumif_host_intch_t; + +/*===========================================================================*/ +/* Type definition: transition state of ISD service request / response queue */ +/*===========================================================================*/ +typedef uint8_t r_icumif_req_res_status_t; + +/*===========================================================================*/ +/* Type definition: priority of ICU-M service */ +/*===========================================================================*/ +typedef uint8_t r_icumif_service_priority_t; + +/*===========================================================================*/ +/* Type definition: request no interrupt */ +/*===========================================================================*/ +typedef uint8_t r_icumif_req_nointerrupt_t; + +/*===========================================================================*/ +/* Type definition: responset no interrupt */ +/*===========================================================================*/ +typedef uint8_t r_icumif_res_nointerrupt_t; + +/*===========================================================================*/ +/* Type definition: job ID */ +/*===========================================================================*/ +typedef uint16_t r_icumif_job_id_t; + +/*===========================================================================*/ +/* Type definition: pointer to call back function */ +/*===========================================================================*/ +typedef void (*p_func_t)(void *p_ISD); + +/*===========================================================================*/ +/* Job slice */ +/*===========================================================================*/ +typedef uint16_t r_job_slice_t; + +/*===========================================================================*/ +/* Type definition: key index */ +/*===========================================================================*/ +typedef uint16_t r_key_index_t; + +/*===========================================================================*/ +/* Type definition: memory cluster ID */ +/*===========================================================================*/ +typedef uint8_t r_mem_cluster_id_t; + +/*===========================================================================*/ +/* Type definition: key property flag set */ +/*===========================================================================*/ +typedef uint16_t r_key_property_flags_t; + +/*===========================================================================*/ +/* Type definition: memory cluster verification map */ +/*===========================================================================*/ +typedef uint32_t r_mem_cluster_verif_t; + +/*===========================================================================*/ +/* Type definition: service job cycle */ +/*===========================================================================*/ +typedef uint32_t r_job_cycle_t; + +/**********************************************************************************/ +/* Header files inclusion for specific service properties */ +/**********************************************************************************/ + +#include "r_icumif_api_sys_init.h" +#include "r_icumif_api_get_info.h" +#include "r_icumif_api_get_id.h" +#include "r_icumif_api_aes_key_update_plain.h" +#include "r_icumif_api_aes_key_update_she.h" +#include "r_icumif_api_aes_key_export_she.h" +#include "r_icumif_api_aes_cipher.h" +#include "r_icumif_api_aes_auth_cipher.h" +#include "r_icumif_api_aes_cmac.h" +#include "r_icumif_api_aes_cmac_short.h" +#include "r_icumif_api_rand_generate.h" +#include "r_icumif_api_pk_import.h" +#include "r_icumif_api_pk_import_ext.h" +#include "r_icumif_api_pk_export.h" +#include "r_icumif_api_iso15118_update.h" +#include "r_icumif_api_rsa_key_generate.h" +#include "r_icumif_api_ecc_key_generate.h" +#include "r_icumif_api_rsa_verify.h" +#include "r_icumif_api_rsa_sign.h" +#include "r_icumif_api_rsa_encrypt.h" +#include "r_icumif_api_rsa_decrypt.h" +#include "r_icumif_api_ecdh.h" +#include "r_icumif_api_ecdsa_verify.h" +#include "r_icumif_api_ecdsa_sign.h" +#include "r_icumif_api_hash.h" +#include "r_icumif_api_hmac.h" +#include "r_icumif_api_hmac_import.h" +#include "r_icumif_api_tls_ecdh_exchange.h" +#include "r_icumif_api_tls_rsa_exchange.h" +#include "r_icumif_api_tls_verify_data.h" +#include "r_icumif_api_lifecycle.h" +#include "r_icumif_api_mem_cluster_def.h" +#include "r_icumif_api_mem_cluster_install.h" +#include "r_icumif_api_mem_cluster_verify.h" +#include "r_icumif_api_mem_cluster_verify_auto.h" +#include "r_icumif_api_sys_cfg.h" +#include "r_icumif_api_key_mgmt.h" +#include "r_icumif_api_mono_ctr.h" +#include "r_icumif_api_cancel_she.h" +#include "r_icumif_api_cmd_debug.h" +#include "r_icumif_api_eddsa_verify.h" +#include "r_icumif_api_eddsa_sign.h" +#include "r_icumif_api_secure_boot_api.h" + +/**********************************************************************************/ +/* Header files inclusion for SHE specific parameters */ +/**********************************************************************************/ + +#include "r_icumif_api_she.h" + +/*===========================================================================*/ +/* Type definition: ICU-M service descriptor (ISD) */ +/*===========================================================================*/ + +typedef struct service_descriptor +{ + r_icumif_service_id_t service_id; + r_icumif_requester_id_t requester_id; + r_icumif_vm_id_t vm_id; + r_icumif_host_intch_t host_int_ch; + volatile r_icumif_req_res_status_t req_res_status; + r_icumif_service_priority_t service_priority; + volatile r_icumif_service_result_t service_result; + volatile r_icumif_req_nointerrupt_t req_nointerrupt; + volatile r_icumif_res_nointerrupt_t res_nointerrupt; + volatile r_icumif_job_id_t job_id; + union + { + p_func_t p_callbackfunc; + uint64_t padding_sys64; + } ptr; + union service_parameters + { + ISD_SYSTEM_INIT_t SYSTEM_INIT; + ISD_SYSTEM_CONFIG_t SYSTEM_CONFIG; + ISD_GET_INFO_t GET_INFO; + ISD_GET_ID_t GET_ID; + ISD_KEY_UPDATE_PLAIN_t KEY_UPDATE_PLAIN; + ISD_KEY_UPDATE_SHE_t KEY_UPDATE_SHE; + ISD_KEY_AES_RAM_EXP_t RAM_KEY_EXPORT_SHE; + ISD_AES_CIPHER_t AES_CIPHER; + ISD_AES_AUTH_CIPHER_t AES_AUTH_CIPHER; + ISD_AES_CMAC_t AES_CMAC; + ISD_AES_CMAC_SHORT_t AES_CMAC_SHORT; + ISD_KEY_MNGT_t KEY_MGMT; + ISD_CANCEL_SHE_t CANCEL_SHE; + ISD_RAND_INIT_t RAND_INIT; + ISD_RAND_EXTEND_SEED_t RAND_EXTEND_SEED; + ISD_RAND_GENERATE_t RAND_GENERATE; + ISD_PK_IMPORT_t PK_IMPORT; + ISD_PK_EXPORT_t PK_EXPORT; + ISD_RSA_KEY_GENERATE_t RSA_KEY_GENERATE; + ISD_ECC_KEY_GENERATE_t ECC_KEY_GENERATE; + ISD_RSA_VERIFY_t RSA_VERIFY; + ISD_RSA_SIGN_t RSA_SIGN; + ISD_RSA_ENCRYPT_t RSA_ENCRYPT; + ISD_RSA_DECRYPT_t RSA_DECRYPT; + ISD_ECDH_t ECDH; + ISD_ECDSA_VERIFY_t ECDSA_VERIFY; + ISD_ECDSA_SIGN_t ECDSA_SIGN; + ISD_EDDSA_VERIFY_t EDDSA_VERIFY; + ISD_EDDSA_SIGN_t EDDSA_SIGN; + ISD_HASH_t HASH; + ISD_MEM_CLUSTER_DEF_t MEM_CLUSTER_DEF; + ISD_MEM_CLUSTER_INST_t MEM_CLUSTER_INSTALL; + ISD_MEM_CLUSTER_VERIF_t MEM_CLUSTER_VERIFY; + ISD_MEM_CLUSTER_VERIF_AUTO_t MEM_CLUSTER_VERIFY_AUTO; + ISD_MONO_CTR_t MONO_CTR_MGMT; + ISD_LIFE_CYCLE_t LIFE_CYCLE; + ISD_HMAC_t HMAC; + ISD_HMAC_IMPORT_t HMAC_IMPORT; + ISD_TLS_RSA_EXCHANGE_t TLS_RSA_EXCHANGE; + ISD_TLS_ECDH_EXCHANGE_t TLS_ECDH_EXCHANGE; + ISD_TLS_VERIFY_DATA_t TLS_VERIFY_DATA; + ISD_ISO15118_UPDATE_t ISO15118_UPDATE; + ISD_PK_IMPORT_EXT_t PK_IMPORT_EXT; + ISD_CMD_DEBUG_t CMD_DEBUG; + ISD_SECURE_BOOT_API_t SECURE_BOOT_API; + } prm; +} r_icumif_isd_t; + +/*===========================================================================*/ +/* Type definition: ICU-M firmware status */ +/*===========================================================================*/ + +typedef struct r_icumif_sts +{ + uint32_t BUSY:1; + uint32_t SECURE_BOOT:1; + uint32_t BOOT_INIT:1; + uint32_t BOOT_FINISHED:1; + uint32_t BOOT_OK:1; + uint32_t RND_INIT:1; + uint32_t EXT_DEBUGGER:1; + uint32_t INT_DEBUGGER:1; + uint32_t :1; + uint32_t FUSAERR:1; + uint32_t MONERR:1; + uint32_t BUSERR:1; + uint32_t ROMERR:1; + uint32_t RAMERR:1; + uint32_t WDTERR:1; + uint32_t SYSTEMERR:1; + uint32_t :1; + uint32_t EXTERR:1; + uint32_t FCUERR:1; + uint32_t RNDERR:1; + uint32_t DFWARNING_B:1; + uint32_t DFWARNING_A:1; + uint32_t STARTUP_BANK:1; + uint32_t BOOTERR:1; + uint32_t RPC_WAIT:1; + uint32_t TRNG:1; + uint32_t FLS_WAIT:1; + uint32_t FACIACC:1; + uint32_t SERVAVAIL:1; + uint32_t FCUINIT:1; + uint32_t PLLSET:1; + uint32_t STARTPE:1; +} r_icumif_sts_t; + +/**********************************************************************************/ +/* Structure alignment back to default configuration */ +/**********************************************************************************/ +#pragma pack() + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* R_ICUMIF_API_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_auth_cipher.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_auth_cipher.h new file mode 100644 index 0000000..e8780d6 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_auth_cipher.h @@ -0,0 +1,109 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_AES_AUTH_CIPHER_H) +#define R_ICUMIF_API_AES_AUTH_CIPHER_H + +/**********************************************************************************/ +/* Defines */ +/**********************************************************************************/ + +#define AES_BLOCK_SIZE_IN_BYTES (16u) +#define AUTH_CIPHER_SAFETY_MODE_ENABLE (0xA55AA55Au) + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ + +typedef enum +{ + AUTH_CIPHER_MOD_GCM, + AUTH_CIPHER_MOD_CCM, + + LAST_ITEM_AUTH_CIPHER_MOD = 0x01000000 +} auth_cipher_modes_t; + +typedef struct auth_cipher_status_reg +{ + uint32_t dma_used; + uint32_t status; + uint32_t transfer_num; + uint32_t control_src; + uint32_t control_dst; + uint32_t transfered_num_src; + uint32_t transfered_num_dst; + uint32_t remain_num_src; + uint32_t remain_num_dst; + uint32_t address_src; + uint32_t address_dst; +} auth_cipher_status_reg_t; + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_AES_AUTH_CIPHER +{ + union + { + const uint32_t *p_iv; + uint64_t padding_sys64; + } ptr1; + union + { + const uint32_t *p_auth_data; + uint64_t padding_sys64; + } ptr2; + union + { + const uint32_t *p_data_in; + uint64_t padding_sys64; + } ptr3; + union + { + uint32_t *p_data_out; + uint64_t padding_sys64; + } ptr4; + union + { + uint32_t *p_auth_tag; + uint64_t padding_sys64; + } ptr5; + union + { + auth_cipher_status_reg_t *p_status_reg_auth_data; + uint64_t padding_sys64; + } ptr6; + union + { + auth_cipher_status_reg_t *p_status_reg_data; + uint64_t padding_sys64; + } ptr7; + uint32_t data_size_in_bits; + uint32_t auth_data_size_in_bits; + uint32_t iv_size_in_bits; + uint8_t auth_tag_size_in_bits; + uint32_t safety_mode; + r_key_group_t key_group; + r_key_index_t key_id; + cipher_direction_t direction; + auth_cipher_modes_t cipher_mode; + r_job_slice_t job_slice; + r_job_cycle_t job_cycle; + volatile r_verif_result_t verification_result; +} ISD_AES_AUTH_CIPHER_t; + +#endif /* R_ICUMIF_API_AES_AUTH_CIPHER_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_cipher.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_cipher.h new file mode 100644 index 0000000..00c22db --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_cipher.h @@ -0,0 +1,86 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_AES_CIPHER_H) +#define R_ICUMIF_API_AES_CIPHER_H + +/**********************************************************************************/ +/* Defines */ +/**********************************************************************************/ + +#define AES_BLOCK_SIZE_IN_BYTES (16u) + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ + +typedef enum +{ + CIPHER_DIR_ENCRYPTION, + CIPHER_DIR_DECRYPTION, + + LAST_ITEM_CIPHER_DIR = 0x01000000 +} cipher_direction_t; + +typedef enum +{ + CIPHER_MOD_CBC, + CIPHER_MOD_ECB, + CIPHER_MOD_CFB, + CIPHER_MOD_OFB, + CIPHER_MOD_CTR, + CIPHER_MOD_XTS, + + LAST_ITEM_CIPHER_MOD = 0x01000000 +} cipher_modes_t; + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_AES_CIPHER +{ + union + { + const uint32_t *p_iv; + uint64_t padding_sys64; + } ptr1; + union + { + const uint32_t *p_block_in; + uint64_t padding_sys64; + } ptr2; + union + { + uint32_t *p_block_out; + uint64_t padding_sys64; + } ptr3; + union + { + uint32_t nb_blocks; + uint32_t data_size_in_bits; + } size; + r_key_group_t key_group; + r_key_index_t key_id; + r_key_group_t key_group_2; + r_key_index_t key_id_2; + cipher_direction_t direction; + cipher_modes_t cipher_mode; + r_job_slice_t job_slice; + r_job_cycle_t job_cycle; +} ISD_AES_CIPHER_t; + +#endif /* R_ICUMIF_API_AES_CIPHER_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_cmac.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_cmac.h new file mode 100644 index 0000000..0688f79 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_cmac.h @@ -0,0 +1,58 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_AES_CMAC_H) +#define R_ICUMIF_API_AES_CMAC_H + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ + +typedef enum +{ + CMAC_GENERATION, + CMAC_VERIFICATION, + + LAST_ITEM_CMAC = 0x01000000 +} cmac_operation_t; + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_AES_CMAC +{ + union + { + const uint32_t *p_msg; + uint64_t padding_sys64; + } ptr1; + union + { + uint32_t *p_cmac; + uint64_t padding_sys64; + } ptr2; + uint32_t msg_size_in_bits; + r_key_group_t key_group; + r_key_index_t key_id; + uint8_t cmac_size_in_bits; + cmac_operation_t cmac_operation; + r_job_slice_t job_slice; + r_job_cycle_t job_cycle; + volatile r_verif_result_t verification_result; +} ISD_AES_CMAC_t; + +#endif /* R_ICUMIF_API_AES_CMAC_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_cmac_short.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_cmac_short.h new file mode 100644 index 0000000..f165ed6 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_cmac_short.h @@ -0,0 +1,46 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_AES_CMAC_SHORT_H) +#define R_ICUMIF_API_AES_CMAC_SHORT_H + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ + +typedef struct cmac_position +{ + uint8_t cmac_position; + uint8_t cmac_size; + uint8_t message_position; + uint8_t message_size; +} cmac_position_t; + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_AES_CMAC_SHORT +{ + uint32_t text[2]; + cmac_position_t position_data; + r_key_group_t key_group; + r_key_index_t key_id; + cmac_operation_t cmac_operation; + volatile r_verif_result_t verification_result; +} ISD_AES_CMAC_SHORT_t; + +#endif /* R_ICUMIF_API_AES_CMAC_SHORT_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_key_export_she.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_key_export_she.h new file mode 100644 index 0000000..b030957 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_key_export_she.h @@ -0,0 +1,53 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_AES_KEY_EXPORT_SHE_H) +#define R_ICUMIF_API_AES_KEY_EXPORT_SHE_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_KEY_AES_RAM_EXP +{ + union + { + uint8_t *p_M1; + uint64_t padding_sys64; + } ptr1; + union + { + uint8_t *p_M2; + uint64_t padding_sys64; + } ptr2; + union + { + uint8_t *p_M3; + uint64_t padding_sys64; + } ptr3; + union + { + uint8_t *p_M4; + uint64_t padding_sys64; + } ptr4; + union + { + uint8_t *p_M5; + uint64_t padding_sys64; + } ptr5; +} ISD_KEY_AES_RAM_EXP_t; + +#endif /* R_ICUMIF_API_AES_KEY_EXPORT_SHE_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_key_update_plain.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_key_update_plain.h new file mode 100644 index 0000000..318ddc0 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_key_update_plain.h @@ -0,0 +1,47 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_AES_KET_UPDATE_PLAIN_H) +#define R_ICUMIF_API_AES_KET_UPDATE_PLAIN_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_KEY_UPDATE_PLAIN +{ + union + { + const uint8_t *p_key_value; + uint64_t padding_sys64; + } ptr; + r_key_group_t key_group; + r_key_index_t key_id; + uint16_t key_size_in_bytes; + r_mem_cluster_verif_t mem_cluster_verif; + struct + { + r_key_property_flags_t encryption:1; + r_key_property_flags_t decryption:1; + r_key_property_flags_t cmac_generation:1; + r_key_property_flags_t cmac_verification:1; + r_key_property_flags_t write_protected:1; + r_key_property_flags_t disable_on_debug:1; + r_key_property_flags_t no_wild_card:1; + } flags; +} ISD_KEY_UPDATE_PLAIN_t; + +#endif /* R_ICUMIF_API_AES_KET_UPDATE_PLAIN_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_key_update_she.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_key_update_she.h new file mode 100644 index 0000000..3345055 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_aes_key_update_she.h @@ -0,0 +1,54 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_AES_KEY_UPDATE_SHE_H) +#define R_ICUMIF_API_AES_KEY_UPDATE_SHE_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_KEY_UPDATE_SHE +{ + union + { + const uint8_t *p_M1; + uint64_t padding_sys64; + } ptr1; + union + { + const uint8_t *p_M2; + uint64_t padding_sys64; + } ptr2; + union + { + const uint8_t *p_M3; + uint64_t padding_sys64; + } ptr3; + union + { + uint8_t *p_M4; + uint64_t padding_sys64; + } ptr4; + union + { + uint8_t *p_M5; + uint64_t padding_sys64; + } ptr5; + uint8_t extended_key_id; +} ISD_KEY_UPDATE_SHE_t; + +#endif /* R_ICUMIF_API_AES_KEY_UPDATE_SHE_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_cancel_she.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_cancel_she.h new file mode 100644 index 0000000..5264ed9 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_cancel_she.h @@ -0,0 +1,29 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_CANCEL_SHE_H) +#define R_ICUMIF_API_CANCEL_SHE_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_CANCEL_SHE +{ + r_icumif_job_id_t cancel_job_id; +} ISD_CANCEL_SHE_t; + +#endif /* R_ICUMIF_API_CANCEL_SHE_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_cmd_debug.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_cmd_debug.h new file mode 100644 index 0000000..49bcb20 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_cmd_debug.h @@ -0,0 +1,47 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_CMD_DEBUG_H) +#define R_ICUMIF_API_CMD_DEBUG_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef enum +{ + DBG_CR_CHALLENGE, + DBG_CR_RESPONSE, + + LAST_ITEM_DBG_CR_REQ = 0x01000000 +} r_debug_request_t; + +typedef struct ISD_CMD_DEBUG +{ + r_debug_request_t cr_request; + union + { + uint32_t *p_challenge; + uint64_t padding_sys64; + } ptr1; + union + { + uint32_t *p_response; + uint64_t padding_sys64; + } ptr2; +} ISD_CMD_DEBUG_t; + +#endif /* R_ICUMIF_API_CMD_DEBUG_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_ecc_key_generate.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_ecc_key_generate.h new file mode 100644 index 0000000..6cb1984 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_ecc_key_generate.h @@ -0,0 +1,37 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_ECC_KEY_GENERATE_H) +#define R_ICUMIF_API_ECC_KEY_GENERATE_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_ECC_KEY_GENERATE +{ + r_key_group_t key_group; + r_key_index_t key_id; + r_ecc_curve_t curve_id; + r_mem_cluster_verif_t mem_cluster_verif; + struct + { + r_key_property_flags_t disable_on_debug:1; + r_key_property_flags_t write_protected:1; + } flags; +} ISD_ECC_KEY_GENERATE_t; + +#endif /* R_ICUMIF_API_ECC_KEY_GENERATE_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_ecdh.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_ecdh.h new file mode 100644 index 0000000..4328bf1 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_ecdh.h @@ -0,0 +1,57 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_ECDH_H) +#define R_ICUMIF_API_ECDH_H + +/**********************************************************************************/ +/* Defines */ +/**********************************************************************************/ +#define SET_SHARED_SECRET (0u) +#define OUTPUT_SHARED_SECRET (1u) + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_ECDH +{ + r_key_group_t ecc_priv_key_group; + r_key_index_t ecc_priv_key_id; + r_key_group_t ecc_pub_key_group; + r_key_index_t ecc_pub_key_id; + r_key_group_t shared_key_group; + r_key_index_t shared_key_id; + r_kdf_algo_t kdf_algo; + r_hash_primitive_t hash_primitive; + r_job_slice_t job_slice; + union + { + const uint8_t *p_info; + uint64_t padding_sys64; + } ptr; + uint16_t counter; + uint8_t info_size_in_bytes; + uint16_t key_size_in_bytes; + union + { + uint8_t *p_shared_secret; + uint64_t padding_sys64; + } ptr2; + uint8_t output_select; +} ISD_ECDH_t; + +#endif /* R_ICUMIF_API_ECDH_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_ecdsa_sign.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_ecdsa_sign.h new file mode 100644 index 0000000..0d83e42 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_ecdsa_sign.h @@ -0,0 +1,52 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_ECDSA_SIGN_H) +#define R_ICUMIF_API_ECDSA_SIGN_H + +/**********************************************************************************/ +/* Definition */ +/**********************************************************************************/ +#define ECDSA_SIGNATURE_NUM (2u) + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_ECDSA_SIGN +{ + union + { + const uint8_t *p_source; + uint64_t padding_sys64; + } ptr; + union + { + uint8_t *p_data; + uint64_t padding_sys64; + } signature[ECDSA_SIGNATURE_NUM]; + uint32_t source_size_in_bytes; + r_hash_primitive_t hash_primitive; + r_number_format_t signature_format; + r_key_group_t key_group; + r_key_index_t key_id; + r_job_slice_t job_slice_hash; + r_job_slice_t job_slice_point_mul; + volatile uint16_t signature_size_in_bits[ECDSA_SIGNATURE_NUM]; + uint8_t is_precalculated_hash; +} ISD_ECDSA_SIGN_t; + +#endif /* R_ICUMIF_API_ECDSA_SIGN_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_ecdsa_verify.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_ecdsa_verify.h new file mode 100644 index 0000000..58552b3 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_ecdsa_verify.h @@ -0,0 +1,53 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_ECDSA_VERIFY_H) +#define R_ICUMIF_API_ECDSA_VERIFY_H + +/**********************************************************************************/ +/* Definition */ +/**********************************************************************************/ +#define ECDSA_SIGNATURE_NUM (2u) + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_ECDSA_VERIFY +{ + union + { + const uint8_t *p_source; + uint64_t padding_sys64; + } ptr; + union + { + const uint8_t *p_data; + uint64_t padding_sys64; + } signature[ECDSA_SIGNATURE_NUM]; + uint32_t source_size_in_bytes; + uint16_t signature_size_in_bits[ECDSA_SIGNATURE_NUM]; + r_hash_primitive_t hash_primitive; + r_number_format_t signature_format; + r_key_group_t key_group; + r_key_index_t key_id; + r_job_slice_t job_slice_hash; + r_job_slice_t job_slice_point_mul; + uint8_t is_precalculated_hash; + volatile r_verif_result_t verification_result; +} ISD_ECDSA_VERIFY_t; + +#endif /* R_ICUMIF_API_ECDSA_VERIFY_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_eddsa_sign.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_eddsa_sign.h new file mode 100644 index 0000000..53106e3 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_eddsa_sign.h @@ -0,0 +1,52 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_EDDSA_SIGH_H) +#define R_ICUMIF_API_EDDSA_SIGH_H + +/**********************************************************************************/ +/* Definition */ +/**********************************************************************************/ +#define EDDSA_SIGNATURE_NUM (2u) + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_EDDSA_SIGN +{ + union + { + const uint8_t *p_source; + uint64_t padding_sys64; + } ptr; + union + { + uint8_t *p_data; + uint64_t padding_sys64; + } signature[EDDSA_SIGNATURE_NUM]; + uint32_t source_size_in_bytes; + r_hash_primitive_t hash_primitive; + r_number_format_t signature_format; + r_key_group_t key_group; + r_key_index_t key_id; + r_job_slice_t job_slice_hash; + r_job_slice_t job_slice_point_mul; + volatile uint16_t signature_size_in_bits[EDDSA_SIGNATURE_NUM]; + uint8_t is_precalculated_hash; +} ISD_EDDSA_SIGN_t; + +#endif /* R_ICUMIF_API_EDDSA_SIGH_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_eddsa_verify.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_eddsa_verify.h new file mode 100644 index 0000000..5974146 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_eddsa_verify.h @@ -0,0 +1,53 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_EDDSA_VERIFY_H) +#define R_ICUMIF_API_EDDSA_VERIFY_H + +/**********************************************************************************/ +/* Definition */ +/**********************************************************************************/ +#define EDDSA_SIGNATURE_NUM (2u) + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_EDDSA_VERIFY +{ + union + { + const uint8_t *p_source; + uint64_t padding_sys64; + } ptr; + union + { + const uint8_t *p_data; + uint64_t padding_sys64; + } signature[EDDSA_SIGNATURE_NUM]; + uint32_t source_size_in_bytes; + uint16_t signature_size_in_bits[EDDSA_SIGNATURE_NUM]; + r_hash_primitive_t hash_primitive; + r_number_format_t signature_format; + r_key_group_t key_group; + r_key_index_t key_id; + r_job_slice_t job_slice_hash; + r_job_slice_t job_slice_point_mul; + uint8_t is_precalculated_hash; + volatile r_verif_result_t verification_result; +} ISD_EDDSA_VERIFY_t; + +#endif /* R_ICUMIF_API_EDDSA_VERIFY_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_get_id.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_get_id.h new file mode 100644 index 0000000..b20c838 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_get_id.h @@ -0,0 +1,45 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_GET_ID_H) +#define R_ICUMIF_API_GET_ID_H + +/**********************************************************************************/ +/* Definition */ +/**********************************************************************************/ +#define UID_SIZE_15 (15u) + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_GET_ID +{ + union + { + uint8_t *p_challenge; + uint64_t padding_sys64; + } ptr1; + uint8_t UID[UID_SIZE_15]; + uint8_t SREG; + union + { + uint8_t *p_CMAC; + uint64_t padding_sys64; + } ptr2; +} ISD_GET_ID_t; + +#endif /* R_ICUMIF_API_GET_ID_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_get_info.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_get_info.h new file mode 100644 index 0000000..ba961b2 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_get_info.h @@ -0,0 +1,125 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_GET_INFO_H) +#define R_ICUMIF_API_GET_INFO_H + + +/**********************************************************************************/ +/* Definition */ +/**********************************************************************************/ +/* number of warning data */ +#define INFO_WARNING_DATA_NUM (16u) +/* 16 is the maximum number of secure data flash physical blocks + assumed by the target microcomputer */ +#define INFO_DF_BLOCK_NUM (16u) + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ + +typedef enum +{ + INFO_GET_FW_NAME, + INFO_GET_FW_VERSION, + INFO_GET_FW_BUILD_TYPE, + INFO_GET_JOB_COUNT, + INFO_GET_KEY_MAPPING, + INFO_GET_MYDATA_SET, + INFO_GET_MONOCTR_MAPPING, + INFO_GET_SECURE_TICK, + INFO_GET_SECURE_TICK_FREQ, + INFO_GET_TIMING_1ST_STAGE_BOOT, + INFO_GET_CMAC_MIN, + INFO_GET_BOOT_STAGE_SLICE, + INFO_GET_BOOT_STAGE_SANCTION, + INFO_GET_SECURE_BOOT, + INFO_GET_WDT, + INFO_GET_RND, + INFO_GET_DEBUG, + INFO_GET_SECURE_TICK_INTERVAL, + INFO_GET_START_PE, + INFO_GET_EARLY_STARTUP_PE, + INFO_GET_DEVICE_ID, + INFO_GET_MEMCLUSTER_MAPPING, + INFO_GET_RAM_EXECUTE, + INFO_GET_ECC_TEST_LOCK, + INFO_GET_NVM_DATA_WARNING, + INFO_GET_FLS_CFG, + INFO_GET_FREE_BLOCK, + INFO_GET_VM_CFG, + + LAST_ITEM_INFO_FW = 0x01000000 +} info_type_t; + +typedef enum +{ + DATASET_SYS_CFG, + DATASET_MEM_CLUSTER, + DATASET_AES_KEY, + DATASET_CR_KEY, + DATASET_RSA_PRIV_KEY, + DATASET_RSA_PUB_KEY, + DATASET_ECC_PRIV_KEY, + DATASET_ECC_PUB_KEY, + DATASET_MYDATA, + DATASET_RSA_PUB_EXT_KEY, + DATASET_ECC_PUB_EXT_KEY, + + DATASET_FW_INTERNAL = 0xFE, + DATASET_NONE = 0xFF, + + LAST_ITEM_DATASET = 0x01000000 +} info_dataset_type_t; + +typedef struct +{ + info_dataset_type_t dataset; + uint16_t index; +} info_warning_data_t; + +typedef struct +{ + info_warning_data_t data[INFO_WARNING_DATA_NUM]; +} info_warning_t; + +typedef struct +{ + uint16_t total_num; + uint16_t num[INFO_DF_BLOCK_NUM]; +} info_free_block_t; + +typedef struct +{ + uint64_t counter; +} secure_tick_info_t; + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_GET_INFO +{ + info_type_t info_id; + union + { + void *p_info; + uint64_t padding_sys64; + } ptr; + volatile uint8_t data_size_in_bytes; +} ISD_GET_INFO_t; + +#endif /* R_ICUMIF_API_GET_INFO_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_hash.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_hash.h new file mode 100644 index 0000000..c816203 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_hash.h @@ -0,0 +1,44 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_HASH_H) +#define R_ICUMIF_API_HASH_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_HASH +{ + union + { + const uint8_t *p_message; + uint64_t padding_sys64; + } ptr1; + union + { + uint8_t *p_hash; + uint64_t padding_sys64; + } ptr2; + uint32_t message_size_in_bytes; + volatile uint16_t hash_size_in_bytes; + r_hash_primitive_t hash_primitive; + r_job_slice_t job_slice; + r_job_cycle_t job_cycle; + uint32_t total_msg_size_in_bytes; +} ISD_HASH_t; + +#endif /* R_ICUMIF_API_HASH_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_hmac.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_hmac.h new file mode 100644 index 0000000..24cadc3 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_hmac.h @@ -0,0 +1,57 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_HMAC_H) +#define R_ICUMIF_API_HMAC_H + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ + +typedef enum +{ + HMAC_GENERATION, + HMAC_VERIFICATION, + + LAST_ITEM_HMAC = 0x01000000 +} hmac_operation_t; + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_HMAC +{ + r_key_index_t key_id; + hmac_operation_t hmac_operation; + r_hash_primitive_t hash_primitive; + union + { + const uint8_t *p_msg; + uint64_t padding_sys64; + } ptr1; + uint32_t msg_size_in_bytes; + union + { + uint8_t *p_hmac; + uint64_t padding_sys64; + } ptr2; + uint8_t hmac_size_in_bytes; + r_job_slice_t job_slice; + volatile r_verif_result_t verification_result; +} ISD_HMAC_t; + +#endif /* R_ICUMIF_API_HMAC_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_hmac_import.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_hmac_import.h new file mode 100644 index 0000000..d604f38 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_hmac_import.h @@ -0,0 +1,35 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_HMAC_IMPORT_H) +#define R_ICUMIF_API_HMAC_IMPORT_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_HMAC_IMPORT +{ + r_key_index_t key_id; + union + { + const uint8_t *p_key; + uint64_t padding_sys64; + } ptr; + uint8_t key_size_in_bytes; +} ISD_HMAC_IMPORT_t; + +#endif /* R_ICUMIF_API_HMAC_IMPORT_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_iso15118_update.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_iso15118_update.h new file mode 100644 index 0000000..d9eaa62 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_iso15118_update.h @@ -0,0 +1,54 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_ISO15118_UPDATE_H) +#define R_ICUMIF_API_ISO15118_UPDATE_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ +typedef struct ISD_ISO15118_UPDATE +{ + r_key_index_t ecc_priv_key_id_for_ecdh; + r_key_index_t ecc_pub_key_id_for_ecdh; + r_key_index_t ecc_priv_key_id_for_update; + union + { + const uint8_t *p_new_priv_key; /* include IV */ + uint64_t padding_sys64; + } ptr1; + uint32_t new_priv_key_size_in_bytes; /* include IV */ + union + { + const uint8_t *p_new_pub_key_x; + uint64_t padding_sys64; + } ptr2; + uint32_t new_pub_key_x_size_in_bytes; + union + { + const uint8_t *p_new_pub_key_y; + uint64_t padding_sys64; + } ptr3; + uint32_t new_pub_key_y_size_in_bytes; + r_mem_cluster_verif_t mem_cluster_verif; + struct + { + r_key_property_flags_t disable_on_debug:1; + r_key_property_flags_t write_protected:1; + } flags; +} ISD_ISO15118_UPDATE_t; + +#endif /* R_ICUMIF_API_ISO15118_UPDATE_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_key_mgmt.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_key_mgmt.h new file mode 100644 index 0000000..a99ed03 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_key_mgmt.h @@ -0,0 +1,40 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_KEY_MGMT_H) +#define R_ICUMIF_API_KEY_MGMT_H + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ + +typedef enum +{ + BUFFER_KEY_CONFIG, + + LAST_ITEM_KEY_MNGT_OP = 0x01000000 +} key_mngt_op_t; + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_KEY_MNGT +{ + key_mngt_op_t key_mngt_op; +} ISD_KEY_MNGT_t; + +#endif /* R_ICUMIF_API_KEY_MGMT_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_lifecycle.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_lifecycle.h new file mode 100644 index 0000000..cd8162f --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_lifecycle.h @@ -0,0 +1,77 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_LIFECYCLE_H) +#define R_ICUMIF_API_LIFECYCLE_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef enum +{ + LC_STAGE_LC0 = 0x1122, + LC_STAGE_LC1 = 0x2233, + LC_STAGE_LC2 = 0x3344, + LC_STAGE_LC2S = 0x4455, + LC_STAGE_TERMINATION = 0x5566, + + LAST_ITEM_LC_STAGE = 0x01000000 +} r_stage_type_t; + +typedef enum +{ + LC_CR_NONE, + LC_CR_CHALLENGE, + LC_CR_RESPONSE, + + LAST_ITEM_LC_CR_REQ = 0x01000000 +} r_cr_request_t; + +typedef struct +{ + uint16_t life_cycle_stage; + uint16_t lc_terminate_status; +} sys_cfg_lc_t; + +typedef enum +{ + LC_TERMINATE_NON, + LC_TERMINATE_EXECUTE, + LC_TERMINATE_COMPLETE, + + LAST_ITEM_LC_TERM = 0x01000000 +} r_trm_status_t; + +typedef struct ISD_LIFE_CYCLE +{ + r_stage_type_t current_stage; + r_stage_type_t transition_dest; + r_mem_cluster_id_t cluster_id; + r_cr_request_t cr_request; + union + { + uint8_t *p_challenge; + uint64_t padding_sys64; + } ptr1; + union + { + uint8_t *p_response; + uint64_t padding_sys64; + } ptr2; +} ISD_LIFE_CYCLE_t; + +#endif /* R_ICUMIF_API_LIFECYCLE_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mem_cluster_def.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mem_cluster_def.h new file mode 100644 index 0000000..db08b94 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mem_cluster_def.h @@ -0,0 +1,75 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ + +#if !defined(R_ICUMIF_API_MEM_CLUSTER_DEF_H) +#define R_ICUMIF_API_MEM_CLUSTER_DEF_H + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ + +typedef enum +{ + INSTALL_METHOD_0, + INSTALL_METHOD_1, + + LAST_ITEM_INSTALL_METHOD = 0x01000000 +} r_install_method_t; + +typedef enum +{ + VERIF_ON_DEMAND, + VERIF_FIRST_STAGE_BOOT, + VERIF_SECOND_STAGE_BOOT, + VERIF_BACK_GROUND, + + LAST_ITEM_VERIF_TYPE = 0x01000000 +} r_verif_method_t; + +typedef enum +{ + BOOTMODE_NORMAL, + BOOTMODE_USER, + BOOTMODE_BOTH, + + LAST_ITEM_BOOTMODE = 0x01000000 +} r_boot_mode_t; + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_MEM_CLUSTER_DEF +{ + union + { + const uint32_t *p_data; + uint64_t padding_sys64; + } ptr; + uint32_t data_size_in_bytes; + r_mem_cluster_id_t cluster_id; + r_install_method_t install_method; + r_key_group_t install_key_group; + r_key_index_t install_key_id; + r_key_group_t verif_key_group; + r_key_index_t verif_key_id; + r_verif_method_t verif_method; + r_boot_mode_t boot_mode; + r_job_slice_t job_slice_cmac_install; +} ISD_MEM_CLUSTER_DEF_t; + +#endif /* R_ICUMIF_API_MEM_CLUSTER_DEF_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mem_cluster_install.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mem_cluster_install.h new file mode 100644 index 0000000..3495814 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mem_cluster_install.h @@ -0,0 +1,43 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ + +#if !defined(R_ICUMIF_API_MEM_CLUSTER_INSTALL_H) +#define R_ICUMIF_API_MEM_CLUSTER_INSTALL_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_MEM_CLUSTER_INST +{ + union + { + const uint32_t *p_data; + uint64_t padding_sys64; + } ptr1; + uint32_t data_size_in_bytes; + union + { + const uint8_t *p_authentication_data; + uint64_t padding_sys64; + } ptr2; + uint32_t auth_data_size_in_bytes; + r_number_format_t auth_data_format; + r_mem_cluster_id_t cluster_id; +} ISD_MEM_CLUSTER_INST_t; + +#endif /* R_ICUMIF_API_MEM_CLUSTER_INSTALL_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mem_cluster_verify.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mem_cluster_verify.h new file mode 100644 index 0000000..3035306 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mem_cluster_verify.h @@ -0,0 +1,57 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ + +#if !defined(R_ICUMIF_API_MEM_CLUSTER_VERIFY_H) +#define R_ICUMIF_API_MEM_CLUSTER_VERIFY_H + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ + +typedef enum +{ + ACTION_VERIFY, + ACTION_FORCE_INSTALL, + ACTION_GET_VERIFICATION_STATUS, + ACTION_FORCE_VERIFICATION_FAIL, + ACTION_LOCK_VERIFICATION_STATUS, + + LAST_ITEM_ACTION_TYPE = 0x01000000 +} r_cluster_verif_action_t; + +typedef enum +{ + CLUSTER_NOT_VERIFIED, + CLUSTER_VERIFICATION_FAILED, + CLUSTER_VERIFIED, + + LAST_ITEM_CLUSTER_STATUS = 0x01000000 +} r_cluster_verif_status_t; + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_MEM_CLUSTER_VERIF +{ + r_mem_cluster_id_t cluster_id; + r_cluster_verif_action_t action; + r_job_slice_t job_slice; + volatile r_cluster_verif_status_t verification_status; +} ISD_MEM_CLUSTER_VERIF_t; + +#endif /* R_ICUMIF_API_MEM_CLUSTER_VERIFY_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mem_cluster_verify_auto.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mem_cluster_verify_auto.h new file mode 100644 index 0000000..8d60b1f --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mem_cluster_verify_auto.h @@ -0,0 +1,31 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ + +#if !defined(R_ICUMIF_API_MEM_CLUSTER_VERIFY_AUTO_H) +#define R_ICUMIF_API_MEM_CLUSTER_VERIFY_AUTO_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_MEM_CLUSTER_VERIF_AUTO +{ + r_job_slice_t job_slice; + uint32_t timing_interval; +} ISD_MEM_CLUSTER_VERIF_AUTO_t; + +#endif /* R_ICUMIF_API_MEM_CLUSTER_VERIFY_AUTO_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mono_ctr.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mono_ctr.h new file mode 100644 index 0000000..87b2dd4 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_mono_ctr.h @@ -0,0 +1,50 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_MONO_CTR_H) +#define R_ICUMIF_API_MONO_CTR_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef enum +{ + MONOTONIC_CTR_RAM, + MONOTONIC_CTR, + + LAST_ITEM_MONO_CTR = 0x01000000 +} mono_ctr_type_t; + +typedef enum +{ + MONO_CTR_READ, + MONO_CTR_SET_VALUE, + MONO_CTR_INCREMENT, + + LAST_ITEM_MONO_CTR_OP = 0x01000000 +} mono_ctr_op_t; + +typedef struct ISD_MONO_CTR +{ + mono_ctr_type_t mono_ctr_type; + uint8_t mono_ctr_id; + mono_ctr_op_t mono_ctr_op; + volatile uint64_t counter; +} ISD_MONO_CTR_t; + + +#endif /* R_ICUMIF_API_MONO_CTR_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_pk_export.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_pk_export.h new file mode 100644 index 0000000..96d839c --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_pk_export.h @@ -0,0 +1,66 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_PK_EXPORT_H) +#define R_ICUMIF_API_PK_EXPORT_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_PK_EXPORT +{ + union + { + uint8_t *p_modulus; + uint8_t *p_pub_point_x; + uint64_t padding_sys64; + } ptr1; + union + { + uint8_t *p_pub_exp; + uint8_t *p_pub_point_y; + uint64_t padding_sys64; + } ptr2; + union + { + uint8_t *p_signature; + uint64_t padding_sys64; + } ptr3; + r_number_format_t key_format; + r_number_format_t sig_format; + r_key_group_t key_group; + r_key_index_t key_id; + r_key_group_t sig_key_group; + r_key_index_t sig_key_id; + r_signature_algo_t sig_algo; + r_hash_primitive_t hash_primitive; + volatile r_ecc_curve_t curve_id; + union + { + volatile uint16_t point_x_size_in_bits; + volatile uint16_t modulus_size_in_bits; + } size1; + union + { + volatile uint16_t point_y_size_in_bits; + volatile uint16_t pub_exp_size_in_bits; + } size2; + volatile uint16_t sig_size_in_bits; + uint8_t skip_sign; +} ISD_PK_EXPORT_t; + +#endif /* R_ICUMIF_API_PK_EXPORT_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_pk_import.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_pk_import.h new file mode 100644 index 0000000..132746e --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_pk_import.h @@ -0,0 +1,98 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_PK_IMPORT_H) +#define R_ICUMIF_API_PK_IMPORT_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_PK_IMPORT +{ + union + { + const uint8_t *p_modulus; + const uint8_t *p_pub_point_x; + uint64_t padding_sys64; + } ptr1; + union + { + const uint8_t *p_pub_exp; + const uint8_t *p_pub_point_y; + uint64_t padding_sys64; + } ptr2; + /* added for private key value import */ + union + { + const uint8_t *p_priv_exp; + const uint8_t *p_priv_scalar; + uint64_t padding_sys64; + } ptr3; + union + { + const uint8_t *p_signature; + uint64_t padding_sys64; + } ptr4; + union + { + uint8_t *p_info; + uint64_t padding_sys64; + } ptr5; + r_number_format_t key_format; + r_number_format_t sig_format; + r_key_group_t key_group; /* need for x.509 import */ + r_key_index_t key_id; /* need for x.509 import */ + r_key_group_t sig_key_group; /* need for x.509 import */ + r_key_index_t sig_key_id; /* need for x.509 import */ + r_mem_cluster_verif_t mem_cluster_verif; /* need for x.509 import */ + r_signature_algo_t sig_algo; /* need for x.509 import */ + r_hash_primitive_t hash_primitive; /* need for x.509 import */ + r_ecc_curve_t curve_id; + union + { + uint16_t point_x_size_in_bits; + uint16_t modulus_size_in_bits; + } size1; + union + { + uint16_t point_y_size_in_bits; + uint16_t pub_exp_size_in_bits; + } size2; + /* added for private key value import */ + union + { + uint16_t priv_scalar_size_in_bits; + uint16_t priv_exp_size_in_bits; + } size3; + uint16_t sig_size_in_bits; + uint16_t info_size_in_bytes; + union + { + const uint8_t *p_x509_certificate; + uint64_t padding_sys64; + } ptr6; + uint16_t x509_certificate_size_in_bytes; + struct + { + r_key_property_flags_t disable_on_debug:1; + r_key_property_flags_t write_protected:1; + r_key_property_flags_t iso15118:1; + } flags; + uint8_t skip_verify; +} ISD_PK_IMPORT_t; + +#endif /* R_ICUMIF_API_PK_IMPORT_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_pk_import_ext.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_pk_import_ext.h new file mode 100644 index 0000000..d556f26 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_pk_import_ext.h @@ -0,0 +1,49 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_PK_IMPORT_EXT_H) +#define R_ICUMIF_API_PK_IMPORT_EXT_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_PK_IMPORT_EXT +{ + r_key_group_t key_group; + r_key_index_t key_id; + struct + { + r_key_property_flags_t disable_on_debug:1; + r_key_property_flags_t write_protected:1; + r_key_property_flags_t iso15118:1; + } flags; + r_mem_cluster_verif_t mem_cluster_verif; + r_key_group_t sig_key_group; + r_key_index_t sig_key_id; + r_signature_algo_t sig_algo; + r_hash_primitive_t hash_primitive; + union + { + const uint32_t *p_x509_certificate; + uint64_t padding_sys64; + } ptr; + uint16_t x509_certificate_size_in_bytes; + uint8_t skip_verify; +} ISD_PK_IMPORT_EXT_t; + + +#endif /* R_ICUMIF_API_PK_IMPORT_EXT_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rand_generate.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rand_generate.h new file mode 100644 index 0000000..3885487 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rand_generate.h @@ -0,0 +1,62 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_RAND_GENERATE_H) +#define R_ICUMIF_API_RAND_GENERATE_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef enum +{ + RAND_NO_TEST, + RAND_DIAG_P1_TEST, + RAND_DIAG_P2_TEST, + RAND_HEALTH_TEST, + + LAST_ITEM_RAND_TEST = 0x01000000 +} r_rand_test_t; + +typedef struct _ISD_RAND_INIT +{ + r_rand_test_t online_test; +} +ISD_RAND_INIT_t; + +typedef struct _ISD_RAND_EXTEND_SEED +{ + union + { + const uint32_t *p_entropy; + const uint64_t padding_sys64; + } ptr; +} +ISD_RAND_EXTEND_SEED_t; + +typedef struct ISD_RAND_GENERATE +{ + union + { + uint32_t *p_block_out; + uint64_t padding_sys64; + } ptr; + uint32_t nb_blocks; + r_job_slice_t job_slice; +} +ISD_RAND_GENERATE_t; + +#endif /* R_ICUMIF_API_RAND_GENERATE_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_decrypt.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_decrypt.h new file mode 100644 index 0000000..6c2f361 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_decrypt.h @@ -0,0 +1,51 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_RSA_DECRYPT_H) +#define R_ICUMIF_API_RSA_DECRYPT_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_RSA_DECRYPT +{ + union + { + const uint8_t* p_encrypted_message; /* in */ + uint64_t padding_sys64; + } ptr1; + uint16_t encrypted_message_size_in_bits; /* in */ + union + { + uint8_t* p_message; /* out */ + uint64_t padding_sys64; + } ptr2; + uint32_t message_size_in_bytes; /* out */ + union + { + const uint8_t* p_label; /* in */ + uint64_t padding_sys64; + } ptr3; + uint32_t label_size_in_bytes; /* in */ + r_hash_primitive_t hash_primitive; /* in */ + r_message_encoding_format_t message_encoding_format; /* in */ + r_key_index_t key_id; /* in */ + r_number_format_t encrypted_message_format; /* in */ + r_job_slice_t job_slice_mod_exp; /* in */ +} ISD_RSA_DECRYPT_t; + +#endif /* R_ICUMIF_API_RSA_DECRYPT_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_encrypt.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_encrypt.h new file mode 100644 index 0000000..8e20cd3 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_encrypt.h @@ -0,0 +1,52 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_RSA_ENCRYPT_H) +#define R_ICUMIF_API_RSA_ENCRYPT_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_RSA_ENCRYPT +{ + union + { + const uint8_t* p_message; /* in */ + uint64_t padding_sys64; + } ptr1; + uint32_t message_size_in_bytes; /* in */ + union + { + uint8_t* p_encrypted_message; /* out */ + uint64_t padding_sys64; + } ptr2; + uint16_t encrypted_message_size_in_bits; /* out */ + union + { + const uint8_t* p_label; /* in (option for OAEP) */ + uint64_t padding_sys64; + } ptr3; + uint32_t label_size_in_bytes; /* in (option for OAEP) */ + r_hash_primitive_t hash_primitive; /* in */ + r_message_encoding_format_t message_encoding_format; /* in */ + r_key_group_t key_group; /* in */ + r_key_index_t key_id; /* in */ + r_number_format_t encrypted_message_format; /* in */ + r_job_slice_t job_slice_mod_exp; /* in */ +} ISD_RSA_ENCRYPT_t; + +#endif /* R_ICUMIF_API_RSA_ENCRYPT_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_key_generate.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_key_generate.h new file mode 100644 index 0000000..78b2e3f --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_key_generate.h @@ -0,0 +1,37 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_KEY_GENERATE_H) +#define R_ICUMIF_API_KEY_GENERATE_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_RSA_KEY_GENERATE +{ + r_key_index_t key_id; + r_mem_cluster_verif_t mem_cluster_verif; + uint16_t modulus_size_in_bits; + struct + { + r_key_property_flags_t disable_on_debug:1; + r_key_property_flags_t write_protected:1; + } flags; +} ISD_RSA_KEY_GENERATE_t; + + +#endif /* R_ICUMIF_API_KEY_GENERATE_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_sign.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_sign.h new file mode 100644 index 0000000..87ceb5c --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_sign.h @@ -0,0 +1,48 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_RSA_SIGN_H) +#define R_ICUMIF_API_RSA_SIGN_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_RSA_SIGN +{ + union + { + const uint8_t *p_source; + uint64_t padding_sys64; + } ptr1; + union + { + uint8_t *p_signature; + uint64_t padding_sys64; + } ptr2; + uint32_t source_size_in_bytes; + r_hash_primitive_t hash_primitive; + r_hash_encoding_format_t hash_encoding_format; + r_number_format_t signature_format; + r_key_index_t key_id; + r_job_slice_t job_slice_hash; + r_job_slice_t job_slice_mod_exp; + volatile uint16_t signature_size_in_bits; + volatile uint16_t salt_size_in_bytes; + uint8_t is_precalculated_hash; +} ISD_RSA_SIGN_t; + +#endif /* R_ICUMIF_API_RSA_SIGN_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_verify.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_verify.h new file mode 100644 index 0000000..5c22e7f --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_rsa_verify.h @@ -0,0 +1,50 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_RSA_VERIFY_H) +#define R_ICUMIF_API_RSA_VERIFY_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_RSA_VERIFY +{ + union + { + const uint8_t *p_source; + uint64_t padding_sys64; + } ptr1; + union + { + const uint8_t *p_signature; + uint64_t padding_sys64; + } ptr2; + uint32_t source_size_in_bytes; + uint16_t signature_size_in_bits; + uint16_t salt_size_in_bytes; + r_hash_primitive_t hash_primitive; + r_hash_encoding_format_t hash_encoding_format; + r_number_format_t signature_format; + r_key_group_t key_group; + r_key_index_t key_id; + r_job_slice_t job_slice_hash; + r_job_slice_t job_slice_mod_exp; + uint8_t is_precalculated_hash; + volatile r_verif_result_t verification_result; +} ISD_RSA_VERIFY_t; + +#endif /* R_ICUMIF_API_RSA_VERIFY_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_secure_boot_api.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_secure_boot_api.h new file mode 100644 index 0000000..c0ba97f --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_secure_boot_api.h @@ -0,0 +1,114 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2022-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ + +#if !defined(R_ICUMIF_API_SECURE_BOOT_API_H) +#define R_ICUMIF_API_SECURE_BOOT_API_H + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ +typedef enum +{ + ROM_GET_LCS = 0, + ROM_SECURE_BOOT_VERIFY, + ROM_SECURE_BOOT_DECRYPT, + ROM_SECURE_BOOT_COMPARE, + + LAST_ITEM_BOOT_API = 0x01000000 +} boot_api_t; + +typedef struct +{ + union + { + uint32_t *p_lcs; + uint64_t padding_sys64; + } ptr; + uint32_t lcs_size_in_bytes; +} boot_api_get_lcs_t; + +typedef struct +{ + union + { + uint32_t *p_key_cert; + uint64_t padding_sys64; + } ptr1; + union + { + uint32_t *p_content_cert; + uint64_t padding_sys64; + } ptr2; + union + { + uint32_t *p_cmac; + uint64_t padding_sys64; + } ptr3; +} boot_api_boot_verify_t; + +typedef struct +{ + union + { + uint32_t *p_content_cert; + uint64_t padding_sys64; + } ptr1; + union + { + uint32_t *p_cmac; + uint64_t padding_sys64; + } ptr2; +} boot_api_boot_decrypt_t; + +typedef struct +{ + union + { + uint32_t *p_content_cert; + uint64_t padding_sys64; + } ptr1; + union + { + uint32_t *p_hash; + uint64_t padding_sys64; + } ptr2; + uint32_t hash_size_in_bytes; + union + { + uint32_t *p_cmac; + uint64_t padding_sys64; + } ptr3; +} boot_api_boot_compare_t; + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_SECURE_BOOT_API +{ + boot_api_t boot_api_id; + uint32_t api_return_value; + union api_parameters + { + boot_api_get_lcs_t get_lcs; + boot_api_boot_verify_t boot_verify; + boot_api_boot_decrypt_t boot_decrypt; + boot_api_boot_compare_t boot_compare; + } api; +} ISD_SECURE_BOOT_API_t; + +#endif /* R_ICUMIF_API_SECURE_BOOT_API_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_she.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_she.h new file mode 100644 index 0000000..f4ff621 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_she.h @@ -0,0 +1,129 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_SHE_H) +#define R_ICUMIF_API_SHE_H + +/**********************************************************************************/ +/* SHE specific parameters */ +/**********************************************************************************/ + +/*===========================================================================*/ +/* SHE key index */ +/*===========================================================================*/ +typedef enum +{ + SHE_SECRET_KEY, /* SHE key index : 0 */ + SHE_MASTER_ECU_KEY, /* SHE key index : 1 */ + SHE_BOOT_MAC_KEY, /* SHE key index : 2 */ + SHE_BOOT_MAC, /* SHE key index : 3 */ + SHE_KEY_1, /* SHE key index : 4 */ + SHE_KEY_2, /* SHE key index : 5 */ + SHE_KEY_3, /* SHE key index : 6 */ + SHE_KEY_4, /* SHE key index : 7 */ + SHE_KEY_5, /* SHE key index : 8 */ + SHE_KEY_6, /* SHE key index : 9 */ + SHE_KEY_7, /* SHE key index : 10 */ + SHE_KEY_8, /* SHE key index : 11 */ + SHE_KEY_9, /* SHE key index : 12 */ + SHE_KEY_10, /* SHE key index : 13 */ + SHE_RAM_KEY, /* SHE key index : 14 */ + SHE_KEY_11, /* SHE key index : 15 */ + SHE_KEY_12, /* SHE key index : 16 */ + SHE_KEY_13, /* SHE key index : 17 */ + SHE_KEY_14, /* SHE key index : 18 */ + SHE_KEY_15, /* SHE key index : 19 */ + SHE_KEY_16, /* SHE key index : 20 */ + SHE_KEY_17, /* SHE key index : 21 */ + SHE_KEY_18, /* SHE key index : 22 */ + SHE_KEY_19, /* SHE key index : 23 */ + SHE_KEY_20, /* SHE key index : 24 */ + + SHE_KEY_21, /* SHE key index : 25 */ + SHE_KEY_22, /* SHE key index : 26 */ + SHE_KEY_23, /* SHE key index : 27 */ + SHE_KEY_24, /* SHE key index : 28 */ + SHE_KEY_25, /* SHE key index : 29 */ + SHE_KEY_26, /* SHE key index : 30 */ + SHE_KEY_27, /* SHE key index : 31 */ + SHE_KEY_28, /* SHE key index : 32 */ + SHE_KEY_29, /* SHE key index : 33 */ + SHE_KEY_30, /* SHE key index : 34 */ + SHE_KEY_31, /* SHE key index : 35 */ + SHE_KEY_32, /* SHE key index : 36 */ + SHE_KEY_33, /* SHE key index : 37 */ + SHE_KEY_34, /* SHE key index : 38 */ + SHE_KEY_35, /* SHE key index : 39 */ + SHE_KEY_36, /* SHE key index : 40 */ + SHE_KEY_37, /* SHE key index : 41 */ + SHE_KEY_38, /* SHE key index : 42 */ + SHE_KEY_39, /* SHE key index : 43 */ + SHE_KEY_40, /* SHE key index : 44 */ + SHE_KEY_41, /* SHE key index : 45 */ + SHE_KEY_42, /* SHE key index : 46 */ + SHE_KEY_43, /* SHE key index : 47 */ + SHE_KEY_44, /* SHE key index : 48 */ + SHE_KEY_45, /* SHE key index : 49 */ + SHE_KEY_46, /* SHE key index : 50 */ + SHE_KEY_47, /* SHE key index : 51 */ + SHE_KEY_48, /* SHE key index : 52 */ + SHE_KEY_49, /* SHE key index : 53 */ + SHE_KEY_50, /* SHE key index : 54 */ + SHE_KEY_51, /* SHE key index : 55 */ + SHE_KEY_52, /* SHE key index : 56 */ + SHE_KEY_53, /* SHE key index : 57 */ + SHE_KEY_54, /* SHE key index : 58 */ + SHE_KEY_55, /* SHE key index : 59 */ + SHE_KEY_56, /* SHE key index : 60 */ + SHE_KEY_57, /* SHE key index : 61 */ + SHE_KEY_58, /* SHE key index : 62 */ + SHE_KEY_59, /* SHE key index : 63 */ + SHE_KEY_60, /* SHE key index : 64 */ + SHE_KEY_61, /* SHE key index : 65 */ + SHE_KEY_62, /* SHE key index : 66 */ + SHE_KEY_63, /* SHE key index : 67 */ + SHE_KEY_64, /* SHE key index : 68 */ + SHE_KEY_65, /* SHE key index : 69 */ + SHE_KEY_66, /* SHE key index : 70 */ + SHE_KEY_67, /* SHE key index : 71 */ + SHE_KEY_68, /* SHE key index : 72 */ + SHE_KEY_69, /* SHE key index : 73 */ + SHE_KEY_70, /* SHE key index : 74 */ + SHE_KEY_71, /* SHE key index : 75 */ + SHE_KEY_72, /* SHE key index : 76 */ + SHE_KEY_73, /* SHE key index : 77 */ + SHE_KEY_74, /* SHE key index : 78 */ + SHE_KEY_75, /* SHE key index : 79 */ + SHE_KEY_76, /* SHE key index : 80 */ + SHE_KEY_77, /* SHE key index : 81 */ + SHE_KEY_78, /* SHE key index : 82 */ + SHE_KEY_79, /* SHE key index : 83 */ + SHE_KEY_80, /* SHE key index : 84 */ + SHE_KEY_81, /* SHE key index : 85 */ + SHE_KEY_82, /* SHE key index : 86 */ + SHE_KEY_83, /* SHE key index : 87 */ + SHE_KEY_84, /* SHE key index : 88 */ + SHE_KEY_85, /* SHE key index : 89 */ + SHE_KEY_86, /* SHE key index : 90 */ + SHE_KEY_87, /* SHE key index : 91 */ + SHE_KEY_88, /* SHE key index : 92 */ + SHE_KEY_89, /* SHE key index : 93 */ + SHE_KEY_90, /* SHE key index : 94 */ + + LAST_ITEM_SHE_KEY = 0x01000000 +} r_she_key_index_t; + +#endif /* R_ICUMIF_API_SHE_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_sys_cfg.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_sys_cfg.h new file mode 100644 index 0000000..8484252 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_sys_cfg.h @@ -0,0 +1,196 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_SYS_CFG_H) +#define R_ICUMIF_API_SYS_CFG_H + +/**********************************************************************************/ +/* Defines */ +/**********************************************************************************/ +#define STARTUP_BANK_A (0xA5u) +#define STARTUP_BANK_B (0x00u) + +#define ECC_TEST_UNLOCK (0x00u) +#define ECC_TEST_LOCK (0x01u) + +#define SYS_CFG_NORMAL_STARTUP_PE (0x00u) +#define SYS_CFG_EARLY_STARTUP_PE (0x01u) + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ +#define SYS_CFG_MEMCLUSTER_MAX_ID (32u) + +typedef enum +{ + SET_KEY_MAPPING, + SET_BOOT_STAGE, + SET_MYDATA_MAPPING, + SET_MONOCTR_MAPPING, + SET_SECURE_TICK, + SET_SYS_INTERRUPT, + SET_WDT, + SET_CMAC_MIN, + SET_SECURE_BOOT_CFG, + SET_DEBUG, + SET_RAND, + SET_START_PE, + SET_EARLY_STARTUP_PE, + SET_MEMCLUSTER_MAPPING, + SET_ECC_TEST_LOCK, + SET_FLS_CFG, + SET_VM_CFG, + + LAST_ITEM_CONFIG = 0x01000000 +} sys_config_t; + +typedef struct +{ + uint16_t nb_aes_keys; + uint16_t nb_rsa_priv_keys; + uint16_t nb_rsa_pub_keys; + uint16_t nb_ecc_priv_keys; + uint16_t nb_ecc_pub_keys; + uint16_t nb_rsa_pub_ext_keys; + uint16_t nb_ecc_pub_ext_keys; + uint16_t nb_aes_ram_keys; + uint16_t nb_aes_buffer_keys; + uint16_t nb_ecc_ram_keys; + uint16_t nb_hmac_keys; + uint16_t nb_tls_master_keys; +} sys_cfg_key_mapping_t; + +typedef struct +{ + uint8_t nb_items; + uint16_t item_size_in_bytes; +} sys_cfg_mydata_set_t; + + +typedef enum +{ + SANCTION_DO_NOTHING, + SANCTION_DEVICE_STOP, + SANCTION_ICUM_ADMIN, + + LAST_ITEM_SANCTION = 0x01000000 +} r_sanction_t; + +typedef struct +{ + uint8_t peid:4; + uint8_t channel:4; +} sys_cfg_sys_int_t; + +typedef struct +{ + uint16_t int_freq; +} sys_cfg_secure_tick_t; + +typedef struct +{ + uint32_t erm; +} sys_cfg_watchdog_t; + +typedef struct +{ + uint8_t bclr_psm; + uint8_t nsbf_psm; + uint16_t enable_skip_secureboot; +} sys_cfg_boot_t; + +typedef struct +{ + uint8_t mc_length_min_ctr; + uint8_t mc_length_min_val; + uint8_t short_mac_length_min_ctr; + uint8_t short_mac_length_min_val; +} sys_cfg_cmac_min_t; + +typedef struct +{ + uint32_t rand_trng_pre_init_start; + uint32_t rand_olt_no_ds_reset; + uint32_t rand_olt_ds_reset; + uint32_t rand_first_init_type; +} sys_cfg_rand_t; + +typedef struct +{ + uint32_t cr_auth_key_type; + uint32_t cr_auth_dlt; +} sys_cfg_debug_t; + +typedef struct +{ + uint16_t warning1; + uint16_t warning2; +} sys_cfg_fls_t; + +typedef enum +{ + NONE_VM, + UNIQUE_VM_ID_ALL_CORE, + + LAST_ITEM_VM_TYPE = 0x01000000 +} sys_cfg_vm_type_t; + +typedef struct +{ + sys_cfg_vm_type_t vm_type; + uint8_t nb_vms; + uint8_t privilege_vm_id; + uint8_t memcluster_vm_id[SYS_CFG_MEMCLUSTER_MAX_ID]; +} sys_cfg_vm_t; + +typedef struct +{ + r_verif_method_t verif_method; + r_sanction_t sanction; + r_job_slice_t job_slice; +} sys_cfg_cluster_t; + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_SYSTEM_CONFIG +{ + sys_config_t sys_cfg_id; + struct config_parameters + { + sys_cfg_key_mapping_t key_mapping; + sys_cfg_mydata_set_t mydata_set; + uint8_t nb_monoctr_nv; + uint8_t mem_cluster_mapping; + sys_cfg_sys_int_t sys_interrupt; + sys_cfg_secure_tick_t secure_tick; + sys_cfg_watchdog_t watchdog; + sys_cfg_boot_t boot; + sys_cfg_cmac_min_t mac_length; + r_stage_type_t life_cycle_stage; + sys_cfg_debug_t debug; + sys_cfg_rand_t rand; + sys_cfg_cluster_t cluster; + uint8_t start_pe_set; + uint8_t early_startup_pe; + uint8_t test_lock; + sys_cfg_fls_t fls_cfg; + sys_cfg_vm_t vm_cfg; + } cfg; +} ISD_SYSTEM_CONFIG_t; + +#endif /* R_ICUMIF_API_SYS_CFG_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_sys_init.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_sys_init.h new file mode 100644 index 0000000..0c90d09 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_sys_init.h @@ -0,0 +1,40 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_SYS_INIT_H) +#define R_ICUMIF_API_SYS_INIT_H + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ + +typedef enum +{ + SYS_INIT_FW_INITIALIZATION, + + LAST_ITEM_SYS_INIT = 0x01000000 +} sys_init_t; + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_SYSTEM_INIT +{ + sys_init_t sys_init_id; +} ISD_SYSTEM_INIT_t; + +#endif /* R_ICUMIF_API_SYS_INIT_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_tls_ecdh_exchange.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_tls_ecdh_exchange.h new file mode 100644 index 0000000..576f85e --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_tls_ecdh_exchange.h @@ -0,0 +1,49 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_TLS_ECDH_EXCHANGE_H) +#define R_ICUMIF_API_TLS_ECDH_EXCHANGE_H + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_TLS_ECDH_EXCHANGE +{ + union + { + const uint8_t *p_client_random; + uint64_t padding_sys64; + } ptr1; + union + { + const uint8_t *p_server_random; + uint64_t padding_sys64; + } ptr2; + r_key_group_t ecc_priv_key_group; + r_key_index_t ecc_priv_key_id; + r_key_group_t ecc_pub_key_group; + r_key_index_t ecc_pub_key_id; + r_key_index_t master_secret_id; + r_key_index_t aes_send_key_id; + r_key_index_t aes_receive_key_id; + r_key_index_t hmac_send_key_id; + r_key_index_t hmac_receive_key_id; + uint32_t hmac_key_size_in_bytes; + r_job_slice_t job_slice_multiply; +} ISD_TLS_ECDH_EXCHANGE_t; + +#endif /* R_ICUMIF_API_TLS_ECDH_EXCHANGE_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_tls_rsa_exchange.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_tls_rsa_exchange.h new file mode 100644 index 0000000..d9cc60b --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_tls_rsa_exchange.h @@ -0,0 +1,63 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_TLS_RSA_EXCHANGE_H) +#define R_ICUMIF_API_TLS_RSA_EXCHANGE_H + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ + +typedef struct +{ + uint8_t major; + uint8_t minor; +} protocol_version_t; + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_TLS_RSA_EXCHANGE +{ + protocol_version_t protocol_version; + union + { + const uint8_t *p_client_random; + uint64_t padding_sys64; + } ptr1; + union + { + const uint8_t *p_server_random; + uint64_t padding_sys64; + } ptr2; + r_key_index_t rsa_pub_key_id; + r_key_index_t master_secret_id; + r_key_index_t aes_send_key_id; + r_key_index_t aes_receive_key_id; + r_key_index_t hmac_send_key_id; + r_key_index_t hmac_receive_key_id; + uint32_t hmac_key_size_in_bytes; + r_job_slice_t job_slice_mod_exp; + union + { + uint8_t *p_premaster; + uint64_t padding_sys64; + } ptr3; + uint32_t premaster_size_in_bytes; +} ISD_TLS_RSA_EXCHANGE_t; + +#endif /* R_ICUMIF_API_TLS_RSA_EXCHANGE_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_tls_verify_data.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_tls_verify_data.h new file mode 100644 index 0000000..2a97d6b --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/r_icumif_api_tls_verify_data.h @@ -0,0 +1,55 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ +#if !defined(R_ICUMIF_API_TLS_VERIFY_DATA_H) +#define R_ICUMIF_API_TLS_VERIFY_DATA_H + +/**********************************************************************************/ +/* Type definition */ +/**********************************************************************************/ + +typedef enum +{ + TLS_VERIFY_CLIENT, + TLS_VERIFY_SERVER, + + LAST_ITEM_TLS_VERIFY_DATA = 0x01000000 +} tls_verify_data_operation_t; + +/**********************************************************************************/ +/* Service parameters */ +/**********************************************************************************/ + +typedef struct ISD_TLS_VERIFY_DATA +{ + r_key_index_t key_id; + union + { + const uint8_t *p_msg; + uint64_t padding_sys64; + } ptr1; + uint32_t msg_size_in_bytes; + union + { + uint8_t *p_verify; + uint64_t padding_sys64; + } ptr2; + uint32_t verify_size_in_bytes; + tls_verify_data_operation_t side; + r_job_slice_t job_slice_hash; +} ISD_TLS_VERIFY_DATA_t; + +#endif /* R_ICUMIF_API_TLS_VERIFY_DATA_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/renesas_types.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/renesas_types.h new file mode 100644 index 0000000..5d28109 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/icumif/renesas_types.h @@ -0,0 +1,24 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ + +#if !defined (R_TYPEDEFS_H) +#define R_TYPEDEFS_H + +#include +#include + +#endif /* R_TYPEDEFS_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/include/icum_d_comm_pe_pub.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/include/icum_d_comm_pe_pub.h new file mode 100644 index 0000000..4007251 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/include/icum_d_comm_pe_pub.h @@ -0,0 +1,158 @@ +/******************************************************************************/ +/* Component Name ICU-M COMM(PE) Driver */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ + +#if !defined(ICUM_D_COMM_PE_PUB_H) +#define ICUM_D_COMM_PE_PUB_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/**************************************************************************************/ +/* Return Value Definition */ +/**************************************************************************************/ +#define ER_OK (0x00000000U) +#define ER_PARAM (0x00000001U) + +#define ER_D_COMM_BASE (0x00000400U) + +#define ER_D_COMM_QUE_FULL (ER_D_COMM_BASE+1U) /* Service request queue FULL */ +#define ER_D_COMM_NO_ISD (ER_D_COMM_BASE+2U) /* No ISD in service response queue */ +#define ER_D_COMM_QUE_ALREADY_INIT (ER_D_COMM_BASE+3U) /* Service queue already initialized */ +#define ER_D_COMM_QUE_NOT_INIT (ER_D_COMM_BASE+4U) /* Service queue not initialized */ +#define ER_D_COMM_PARAM_NOT_G_RAM (ER_D_COMM_BASE+5U) /* Param not within global RAM area */ +#define ER_D_COMM_QUE_NOT_ACCESS (ER_D_COMM_BASE+6U) +#define ER_D_COMM_EXIST_ISD (ER_D_COMM_BASE+7U) /* ISD is exist in service response queue */ +#define ER_D_COMM_MEMCHK_NG (ER_D_COMM_BASE+8U) /* address not within RAM area */ +#define ER_D_COMM_ALIGN_NG (ER_D_COMM_BASE+9U) /* address not alignment NG */ + +/**************************************************************************************/ +/* Definition */ +/**************************************************************************************/ + +/* Bit pattern indicate channel No. of interrupt to send ( ICUM_COMM_INT_TO_CHANNEL ) */ +#define ICUM_COMM_ICH_TO_SERV_REQUEST (0x00000002U) +#define ICUM_COMM_ICH_TO_CF_PRG_NOTIFY (0x00000004U) +#define ICUM_COMM_ICH_TO_DF_PRG_NOTIFY (0x00000008U) +#define ICUM_COMM_ICH_TO_CF_PRG_ERROR (0x00000010U) +#define ICUM_COMM_ICH_TO_DF_PRG_ERROR (0x00000020U) +#define ICUM_COMM_ICH_TO_OPERATION_END (0x00000040U) + +/* Service execution request single interrupt */ +#define ICUM_COMM_ICH_TO_SINGLE_INTERRUPT (0x00000001U) + +/* Channel No. of interrupt to receive ( ICUM_COMM_INT_FROM_CHANNEL ) */ +#define ICUM_COMM_ICH_FM_SYS_INTERRUPT (0U) +#define ICUM_COMM_ICH_FM_SERV_RESPONSE (1U) + +/* PE status information ( ICUM_COMM_INFO_PE_STATUS ) */ +#define ICUM_COMM_INF_PE_ST_FLS_DF_PRG (0U) +#define ICUM_COMM_INF_PE_ST_FLS_CF_PRG (1U) +#define ICUM_COMM_INF_PE_ST_FLS_OPRN (2U) +#define ICUM_COMM_INF_PE_ST_FACIACCDIS (3U) +#define ICUM_COMM_INF_PE_ST_PEID (8U) + +#define ICUM_COMM_MEMCHECK_OK (0x00U) +#define ICUM_COMM_MEMCHECK_ERROR (0x01U) + +/* Total number of PE */ +#define TOTAL_PE_NUM (7U) + +/* Length of service queue ( SERVICE_QUEUE_LENGTH ) */ +#define REQUEST_QUEUE_LENGTH (16U) +#define RESPONSE_QUEUE_LENGTH (16U) + +#define RESPONSE_QUEUE_OFST (16U) +#define PE_QUEUE_DUMMY (0U) + +#define TOTAL_QUEUE_LENGTH (REQUEST_QUEUE_LENGTH + PE_QUEUE_DUMMY + RESPONSE_QUEUE_LENGTH + PE_QUEUE_DUMMY) + +#define VM_QUEUE_LENGTH (4U) + +/* Defines item of memory information */ +extern const uint32_t memory_information[]; +#define MEM_INFO_SERVICEQUE_1_ADDR (memory_information[0]) +#define MEM_INFO_SERVICEQUE_1_SIZE (memory_information[1]) +#define MEM_INFO_SHAREDMEM_1_ADDR (memory_information[2]) +#define MEM_INFO_SHAREDMEM_1_SIZE (memory_information[3]) +#define MEM_INFO_SHAREDMEM_2_ADDR (memory_information[4]) +#define MEM_INFO_SHAREDMEM_2_SIZE (memory_information[5]) +#define MEM_INFO_SHAREDMEM_3_ADDR (memory_information[6]) +#define MEM_INFO_SHAREDMEM_3_SIZE (memory_information[7]) +#define MEM_INFO_ICUM_SECUREMOD (memory_information[30]) + +/**************************************************************************************/ +/* Macros */ +/**************************************************************************************/ + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0027]:[ICUMFW_UD_S4_D_COMM_PE_0027] +* Function name: GET_MY_PEID +* Description : Retrieve PEID from thread configurator register +* Arguments : None +* +* Return Value : PEID Value +***************************************************************************************/ +extern uint32_t USER_ICUMIF_GetMyPEID(void); +#define GET_MY_PEID (USER_ICUMIF_GetMyPEID()) + +/**************************************************************************************/ +/* Type definition */ +/**************************************************************************************/ + +/*====================================================================================*/ +/* Type definition: Channel number of interrupt to send */ +/*====================================================================================*/ +typedef uint32_t icum_comm_int_to_channel_t; + +/*====================================================================================*/ +/* Type definition: PE status information */ +/*====================================================================================*/ +typedef uint32_t icum_com_info_pe_status_t; + +/**************************************************************************************/ +/* Enumeration */ +/**************************************************************************************/ +/* None */ + +/**************************************************************************************/ +/* Structure Definition */ +/**************************************************************************************/ +/* None */ + +/**************************************************************************************/ +/* Prototypes */ +/**************************************************************************************/ + +uint32_t D_COMM_PE_Init(uint32_t *p_request_queue); +uint32_t D_COMM_TriggerInterruptToICUP(icum_comm_int_to_channel_t channel, + r_icumif_isd_t *p_isd); +uint32_t D_COMM_GetResponseISD(r_icumif_isd_t **p_isd); +r_icumif_sts_t *D_COMM_GetICUStatusAddr(void); +uint32_t D_COMM_SetPEStatusInfo(icum_com_info_pe_status_t info, uint8_t set_value); +void D_COMM_SetInterruptEnable(void); +uint32_t D_COMM_SetSystemCallBackFunc(R_ICUMIF_CB_REGIST_t *p_regist_info); +uint32_t D_COMM_GetICUMemCheckErrInfo(uint8_t *p_error); +void D_COMM_IRQ_Handler(void); +uint32_t D_COMM_PE_CheckMemorySharedRAM(uint32_t start_addr, uint32_t size); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* ICUM_D_COMM_PE_PUB_H */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/include/r_icumif_pub.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/include/r_icumif_pub.h new file mode 100644 index 0000000..30e6f85 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/include/r_icumif_pub.h @@ -0,0 +1,95 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ + +#if !defined(R_ICUMIF_PUB_H) +#define R_ICUMIF_PUB_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/**************************************************************************************/ +/* Return Value Definition */ +/**************************************************************************************/ +/*===========================================================================*/ +/* Definition of return value of ICU-M interface primitive */ +/*===========================================================================*/ +#define R_ICUMIF_ER_OK (0) /* Successful completion */ +#define R_ICUMIF_ER_PARAM_ALIGNMENT (-1) /* Parameter alignment error */ +#define R_ICUMIF_ER_PARAM_RANGE (-2) /* Parameter range error */ +#define R_ICUMIF_ER_ADDR_NOT_G_RAM (-3) /* Address not within global RAM area */ +#define R_ICUMIF_ER_IF_LIB_NOT_INIT (-4) /* ICU-M interface library not initialized */ +#define R_ICUMIF_ER_REQ_QUEUE_FULL (-5) /* Service request queue FULL */ + +#define R_ICUMIF_ER_SOFTWARE_ERROR (-99) /* Software error */ + +/* Used only by R_ICUMIF_IsServiceCompleted */ +#define R_ICUMIF_RTN_SERV_RUNNING (0) /* Service running */ +#define R_ICUMIF_RTN_SERV_COMPLETION (1) /* Service execution completion */ + +/**************************************************************************************/ +/* Definition */ +/**************************************************************************************/ +/* None */ + + +/**************************************************************************************/ +/* Macros */ +/**************************************************************************************/ +/* None */ + + +/**************************************************************************************/ +/* Type definition */ +/**************************************************************************************/ +/* None */ + + +/**************************************************************************************/ +/* Enumeration */ +/**************************************************************************************/ +/* None */ + +/**************************************************************************************/ +/* Structure Definition */ +/**************************************************************************************/ +/*===========================================================================*/ +/* Type definition: Registration information of call back function */ +/*===========================================================================*/ + +typedef struct R_ICUMIF_CB_REGIST +{ + void (*p_func_addr)(void); +} R_ICUMIF_CB_REGIST_t; + +/**********************************************************************************/ +/* Prototypes */ +/**********************************************************************************/ + +int32_t R_ICUMIF_Init(uint32_t *p_request_queue); +int32_t R_ICUMIF_ServiceRequest(r_icumif_isd_t *p_ISD); +int32_t R_ICUMIF_ServiceResponse(void); +int32_t R_ICUMIF_IsServiceCompleted(r_icumif_isd_t *p_ISD); +r_icumif_sts_t *R_ICUMIF_GetStatus(void); +int32_t R_ICUMIF_SetSystemCallBackFunc(R_ICUMIF_CB_REGIST_t *p_regist_info); +void R_ICUMIF_IRQ_Handler(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* #if !defined(R_ICUMIF_PUB_H) */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/include/user_icumif_api_pub.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/include/user_icumif_api_pub.h new file mode 100644 index 0000000..88149b5 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/include/user_icumif_api_pub.h @@ -0,0 +1,39 @@ +/******************************************************************************/ +/* Component Name Customer-implement component */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ + +#if !defined(USER_ICUMIF_API_PUB_H) +#define USER_ICUMIF_API_PUB_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/***************************************************************************************/ +/* Prototypes */ +/***************************************************************************************/ +extern void USER_ICUMIF_FlushDCache(uint32_t addr, uint32_t size); +extern void USER_ICUMIF_InvalidateDCache(uint32_t addr, uint32_t size); +extern uint32_t USER_ICUMIF_GetMyPEID(void); +extern void USER_ICUMIF_GetLock(uintptr_t *p_saved_psw); +extern void USER_ICUMIF_ReleaseLock(uintptr_t saved_psw); +extern void USER_ICUMIF_Sync(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* #if !defined(USER_ICUMIF_API_PUB_H) */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/secure_boot.c b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/secure_boot.c new file mode 100644 index 0000000..d0a7107 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/secure_boot.c @@ -0,0 +1,522 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : ICUMIF control function + ******************************************************************************/ +/****************************************************************************** + * @file secure_boot.c + * - Version : 0.08 + * @brief ICUMIF controller. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 16.06.2022 0.01 First Release + * : 22.07.2022 0.02 Change CMAC address settings + * Added include file + * Changed for Warning measures + * : 31.10.2022 0.03 License notation change. + * : 07.12.2022 0.04 Warning support when log output is disabled + * : 15.02.2023 0.05 Added final_hash_cmp function. + * : 04.04.2023 0.06 Removed stdio.h. + * : 21.08.2023 0.07 Add support for V4M. + * : 14.01.2024 0.08 Add parameter setting process for RTOS#1/#2. + *****************************************************************************/ +#include "log.h" +#include "timer.h" +#include "r_icumif_api.h" +#include "r_icumif_pub.h" +#include "icum_d_comm_pe_pub.h" +#include "shared.h" +#include "image_load.h" +#include "secure_boot.h" +#include "rst_register.h" + +#define LCS_CM (0x00000000U) /* CM */ +#define LCS_DM (0x00000001U) /* DM */ +#define LCS_SD (0x00000003U) /* SD */ +#define LCS_SE (0x00000005U) /* SE */ +#define LCS_FA (0x00000007U) /* FA */ + +#define RST_MODEMR0_MD5 (0x00000020U) + +#define CX_CMAC_COPY (4U) +#define CX_ICUMIF_STATUS (0x1000F800UL) +#define CX_SIZEOF_CNT (4U) +#define CX_CMAC_SIZE (16U) + +/* Definitions for hash_cmp */ +#define HASH_CMP_NUM (0x2U) /* The number of hash check images */ +#define HASH_SIZE (32U) /* Hash size (32-bytes) */ +#define CR52_IPL_HASH_SAVE_ADDR (0xE635FF40U) /* Hash save address for CR52 IPL */ +#define SECURE_FW_HASH_SAVE_ADDR (0xE635FFC0U) /* Hash save address for Secure FW */ + +static void secureboot_memset(void *buff, uint32_t data, uint32_t cnt); +static void secureboot_service(r_icumif_isd_t *p_ISD); + +void secureboot_init(void) +{ + int32_t r_errno; + volatile uint32_t *status; + + status = (volatile uint32_t *)R_ICUMIF_GetStatus(); + + /* Wait until the ICU-M system intialization is complete */ + while(true) + { + if((*status & CX_ICUMIF_STATUS) != 0UL) + { + break; + } + else + { + micro_wait(100U); /* 100 micro sec */ + } + } + + r_errno = R_ICUMIF_Init((uint32_t *)((uintptr_t)MEM_INFO_SERVICEQUE_1_ADDR)); + if(r_errno != R_ICUMIF_ER_OK) + { + ERROR("R_ICUMIF_Init:Error code = (0x%x).\n", (unsigned int)r_errno); + panic; + } + +} +/* End of function secureboot_init(void) */ + +uint32_t judge_bootmode(void) +{ + uint32_t *p_lcs; + r_icumif_isd_t *p_ISD; + uint32_t md; + uint32_t is_verify = SECURE_BOOT; + + __attribute__((unused))const char *lcs_name[8U] = { + [LCS_CM] = "CM", + [LCS_DM] = "DM", + [LCS_SD] = "SD", + [LCS_SE] = "SE", + [LCS_FA] = "FA", + }; + + secureboot_memset(ISD_BUFFER, 0U, SIZE_OF_ISD_BUFFER); + secureboot_memset(LCS_BUFFER, 0U, SIZE_OF_LCS_BUFFER); + + /* initialize the global icum service header */ + p_ISD = (r_icumif_isd_t *)ISD_BUFFER; + p_lcs = (uint32_t *)LCS_BUFFER; + + p_ISD->service_id = SERVICE_00_SECURE_BOOT_API; + p_ISD->ptr.p_callbackfunc = NULL; + p_ISD->job_id = 0U; + p_ISD->res_nointerrupt = R_ICUMIF_REQRES_NOINTERRPUT; + + p_ISD->prm.SECURE_BOOT_API.boot_api_id = ROM_GET_LCS; + p_ISD->prm.SECURE_BOOT_API.api.get_lcs.ptr.p_lcs = p_lcs; + p_ISD->prm.SECURE_BOOT_API.api.get_lcs.lcs_size_in_bytes = SIZE_OF_LCS_BUFFER; + + /* trigger the service request */ + secureboot_service(p_ISD); + + if(ROMAPI_OK != p_ISD->prm.SECURE_BOOT_API.api_return_value) + { + ERROR("SECURE_BOOT_API:Error code = (0x%x).\n", + (unsigned int)p_ISD->prm.SECURE_BOOT_API.api_return_value); + panic; + } + else + { + /* LCM Status check */ + if(( LCS_CM != *p_lcs) + && ( LCS_DM != *p_lcs) + && ( LCS_SD != *p_lcs) + && ( LCS_SE != *p_lcs) + && ( LCS_FA != *p_lcs)) + { + ERROR("LCM state error. LCS = 0x%x\n", (unsigned int)*p_lcs ); + panic; + } + else + { + NOTICE("LCM state is %s\n",lcs_name[*p_lcs]); + } + } + + md = (mem_read32(RST_MODEMR0) & RST_MODEMR0_MD5) >> 5U; + + if (LCS_SD == *p_lcs) + { + /* LCS=SD => Normal boot */ + is_verify = NORMAL_BOOT; + } + else if ((LCS_SE != *p_lcs) && ( 1U == md)) + { + /* LCS=CM/DM/FA and MD5=1 => Normal boot */ + is_verify = NORMAL_BOOT; + } + else + { + /* LCS=SE => Secure boot */ + /* LCS=CM/DM/FA and MD5=0 => Secure boot */ + is_verify = SECURE_BOOT; + } + + if (NORMAL_BOOT != is_verify) + { +#if (RCAR_LSI == RCAR_S4) + NOTICE("Secure boot(CA55 Loader)\n"); +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + #ifdef AARCH64 + NOTICE("Secure boot(CA76 Loader)\n"); + #else + NOTICE("Secure boot(CR52 Loader)\n"); + #endif +#endif /* RCAR_LSI == RCAR_S4 */ + } + else + { +#if (RCAR_LSI == RCAR_S4) + NOTICE("Normal boot(CA55 Loader)\n"); +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + #ifdef AARCH64 + NOTICE("Normal boot(CA76 Loader)\n"); + #else + NOTICE("Normal boot(CR52 Loader)\n"); + #endif +#endif /* RCAR_LSI == RCAR_S4 */ + } + + return is_verify; + +} +/* End of function judge_bootmode(void) */ + +void secureboot_verify(LOAD_INFO* li, uint32_t start, uint32_t end) +{ + uint32_t *p_cmac; + r_icumif_isd_t *p_ISD; + uint32_t loop; + uint32_t i; + volatile uintptr_t p_content_cert; + volatile uintptr_t p_key_cert; + + secureboot_memset(ISD_BUFFER, 0U, SIZE_OF_ISD_BUFFER); + + p_ISD = (r_icumif_isd_t *)ISD_BUFFER; + + /* Set Load info parameter */ + for (loop = start; loop < end; loop++) + { + secureboot_memset(CMAC_BUFFER, 0U, SIZE_OF_CMAC_BUFFER); + p_cmac = (uint32_t *)CMAC_BUFFER; + p_ISD->service_id = SERVICE_00_SECURE_BOOT_API; + p_ISD->ptr.p_callbackfunc = NULL; + p_ISD->job_id = 0U; + p_ISD->res_nointerrupt = R_ICUMIF_REQRES_NOINTERRPUT; + + p_ISD->prm.SECURE_BOOT_API.boot_api_id + = ROM_SECURE_BOOT_VERIFY; + p_key_cert = li[loop].key_cert_addr; + p_content_cert = li[loop].cnt_cert_addr; + + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr1.p_key_cert = (uint32_t*)p_key_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr2.p_content_cert = (uint32_t*)p_content_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr3.p_cmac = p_cmac; + + /* trigger the service request */ + secureboot_service(p_ISD); + if(ROMAPI_OK != p_ISD->prm.SECURE_BOOT_API.api_return_value) + { + ERROR("SECURE_BOOT_API:Error code = (0x%x).\n", + (unsigned int)p_ISD->prm.SECURE_BOOT_API.api_return_value); + panic; + } + else + { + for (i = 0U; i < CX_CMAC_COPY; i++) + { + li[loop].cmac[i] = *(p_cmac++); + } + } + } + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + /* Set Load info parameter */ + /* For RTOS#0 */ + secureboot_memset(CMAC_BUFFER, 0U, CX_CMAC_SIZE); + p_cmac = (uint32_t *)CMAC_BUFFER; + p_ISD->service_id = SERVICE_00_SECURE_BOOT_API; + p_ISD->ptr.p_callbackfunc = NULL; + p_ISD->job_id = 0U; + p_ISD->res_nointerrupt = R_ICUMIF_REQRES_NOINTERRPUT; + + p_ISD->prm.SECURE_BOOT_API.boot_api_id + = ROM_SECURE_BOOT_VERIFY; + p_key_cert = li[RTOS_ID].key_cert_addr; + p_content_cert = li[RTOS_ID].cnt_cert_addr; + + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr1.p_key_cert = (uint32_t*)p_key_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr2.p_content_cert = (uint32_t*)p_content_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr3.p_cmac = p_cmac; + + /* trigger the service request */ + secureboot_service(p_ISD); + if(ROMAPI_OK != p_ISD->prm.SECURE_BOOT_API.api_return_value) + { + ERROR("SECURE_BOOT_API:Error code = (0x%x).\n", + (unsigned int)p_ISD->prm.SECURE_BOOT_API.api_return_value); + panic; + } + else + { + for (i = 0U; i < CX_CMAC_COPY; i++) + { + li[RTOS_ID].cmac[i] = *(p_cmac++); + } + } + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + /* For RTOS#1,RTOS#2 */ + for (loop = RTOS1_ID; loop <= RTOS2_ID; loop++) + { + secureboot_memset(CMAC_BUFFER, 0U, CX_CMAC_SIZE); + p_cmac = (uint32_t *)CMAC_BUFFER; + p_ISD->service_id = SERVICE_00_SECURE_BOOT_API; + p_ISD->ptr.p_callbackfunc = NULL; + p_ISD->job_id = 0U; + p_ISD->res_nointerrupt = R_ICUMIF_REQRES_NOINTERRPUT; + + p_ISD->prm.SECURE_BOOT_API.boot_api_id + = ROM_SECURE_BOOT_VERIFY; + p_key_cert = li[loop].key_cert_addr; + p_content_cert = li[loop].cnt_cert_addr; + + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr1.p_key_cert = (uint32_t*)p_key_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr2.p_content_cert = (uint32_t*)p_content_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr3.p_cmac = p_cmac; + + /* trigger the service request */ + secureboot_service(p_ISD); + if(ROMAPI_OK != p_ISD->prm.SECURE_BOOT_API.api_return_value) + { + ERROR("SECURE_BOOT_API:Error code = (0x%x).\n", + (unsigned int)p_ISD->prm.SECURE_BOOT_API.api_return_value); + panic; + } + else + { + for (i = 0U; i < CX_CMAC_COPY; i++) + { + li[loop].cmac[i] = *(p_cmac++); + } + } + } +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + +} +/* End of function secureboot_verify(void) */ + +int secureboot_image(LOAD_INFO* li, int do_panic) +{ + uint32_t *p_cmac; + uint32_t *p_hash; + r_icumif_isd_t *p_ISD; + uint32_t i; + volatile uintptr_t p_content_cert; + + secureboot_memset(ISD_BUFFER, 0U, SIZE_OF_ISD_BUFFER); + secureboot_memset(CMAC_BUFFER, 0U, SIZE_OF_CMAC_BUFFER); + secureboot_memset(HASH_BUFFER, 0U, SIZE_OF_HASH_BUFFER); + + /* initialize the global icum service header */ + p_ISD = (r_icumif_isd_t *)ISD_BUFFER; + p_cmac = (uint32_t *)CMAC_BUFFER; + p_hash = (uint32_t *)HASH_BUFFER; + + for (i = 0U; i < CX_CMAC_COPY; i++) + { + *(p_cmac++) = li->cmac[i]; + } + + p_ISD->service_id = SERVICE_00_SECURE_BOOT_API; + p_ISD->ptr.p_callbackfunc = NULL; + p_ISD->job_id = 0U; + p_ISD->res_nointerrupt = R_ICUMIF_REQRES_NOINTERRPUT; + + p_ISD->prm.SECURE_BOOT_API.boot_api_id = ROM_SECURE_BOOT_DECRYPT; + + p_content_cert = li->cnt_cert_addr; + + p_ISD->prm.SECURE_BOOT_API.api. + boot_decrypt.ptr1.p_content_cert = (uint32_t*)p_content_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_decrypt.ptr2.p_cmac = (uint32_t *)CMAC_BUFFER; + + /* trigger the service request */ + secureboot_service(p_ISD); + if(( ROMAPI_OK != p_ISD->prm.SECURE_BOOT_API.api_return_value) && + (ROM_ERR_IMG_VERIFIER_NO_ENCRYPT_IMG != p_ISD->prm.SECURE_BOOT_API.api_return_value)) + { + ERROR("SECURE_BOOT_API:Error code = (0x%x).\n", + (unsigned int)p_ISD->prm.SECURE_BOOT_API.api_return_value); + if (do_panic) + panic; + else + return -1; + } + + p_ISD->service_id = SERVICE_00_SECURE_BOOT_API; + p_ISD->ptr.p_callbackfunc = NULL; + p_ISD->job_id = 0U; + p_ISD->res_nointerrupt = R_ICUMIF_REQRES_NOINTERRPUT; + + p_ISD->prm.SECURE_BOOT_API.boot_api_id = ROM_SECURE_BOOT_COMPARE; + + p_ISD->prm.SECURE_BOOT_API.api. + boot_compare.ptr1.p_content_cert = (uint32_t*)p_content_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_compare.ptr2.p_hash = p_hash; + p_ISD->prm.SECURE_BOOT_API.api. + boot_compare.hash_size_in_bytes = SIZE_OF_HASH_BUFFER; + p_ISD->prm.SECURE_BOOT_API.api. + boot_compare.ptr3.p_cmac = (uint32_t *)CMAC_BUFFER; + + /* trigger the service request */ + secureboot_service(p_ISD); + if(ROMAPI_OK != p_ISD->prm.SECURE_BOOT_API.api_return_value) + { + ERROR("SECURE_BOOT_API:Error code = (0x%x).\n", + (unsigned int)p_ISD->prm.SECURE_BOOT_API.api_return_value); + if (do_panic) + panic; + else + return -1; + } + + return 0; +} +/* End of function secureboot_image(LOAD_INFO* li) */ + + +static void secureboot_memset(void *buff, uint32_t data, uint32_t cnt) +{ + uint32_t *tmp = NULL; + uint32_t loop = cnt / CX_SIZEOF_CNT; /* Copy 4 bytes at a time */ + tmp = (uint32_t *)buff; + + if (buff == NULL) + { + return; + } + + while (loop > 0U) + { + *tmp = data; + tmp++; + loop--; + } +}/* End of function secureboot_memset(void *buff, uint32_t data, uint32_t cnt) */ + +static void secureboot_service(r_icumif_isd_t *p_ISD) +{ + int32_t r_errno; + + /* trigger the service request */ + r_errno = R_ICUMIF_ServiceRequest(p_ISD); + if(R_ICUMIF_ER_OK != r_errno) + { + ERROR("R_ICUMIF_ServiceRequest:Error code = (0x%x).\n", (unsigned int)r_errno); + panic; + } + + /* wait for response */ + while(true) + { + r_errno = R_ICUMIF_IsServiceCompleted(p_ISD); + if(r_errno != R_ICUMIF_RTN_SERV_RUNNING) + { + break; + } + } + + if(SERV_OK != p_ISD->service_result) + { + ERROR("R_ICUMIF_IsServiceCompleted:Error code = (0x%x).\n", p_ISD->service_result); + panic; + } + + r_errno = R_ICUMIF_ServiceResponse(); + if(R_ICUMIF_ER_OK != r_errno) + { + ERROR("R_ICUMIF_ServiceResponse:Error code = (0x%x).\n", (unsigned int)r_errno); + panic; + } + +} +/* End of function secureboot_service(r_icumif_isd_t *p_ISD) */ + +void final_hash_cmp(void) +{ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + uint32_t i; + uint32_t j; + uint8_t *hash1; + uint8_t *hash2; + uintptr_t hash_addr[HASH_CMP_NUM] = {SECURE_FW_HASH_SAVE_ADDR, CR52_IPL_HASH_SAVE_ADDR}; + + for(i = 0U; i < HASH_CMP_NUM; i++) + { + /* Hash is placed SystemRAM by ICUMX IPL. */ + hash1 = (uint8_t *)(hash_addr[i]); + hash2 = (uint8_t *)(hash_addr[i] + HASH_SIZE); + + for(j = 0U; j < HASH_SIZE; j++) + { + /* Compare Hash */ + if(*hash1 != *hash2) + { + /* Hash unmatch. */ + ERROR("Final Hash compare error!!\n"); + panic; + } + hash1++; + hash2++; + } + } +#endif /* (RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M) */ +} +/* End of function final_hash_cmp(void) */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/shared/src/lorem_ipsum.c b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/shared/src/lorem_ipsum.c new file mode 100644 index 0000000..39ff6b3 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/shared/src/lorem_ipsum.c @@ -0,0 +1,18 @@ +/******************************************************************************/ +/* Component Name Testing the ICU-M */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/* Copyright(C) 2021-2023 Renesas Electronics Corporation. */ +/******************************************************************************/ + +#include "renesas_types.h" + +/* Lorem Ipsum Generator */ +/* change the section so that the constants are not always moved away! */ + +#define ALIGNVAR(n) __attribute__ ((aligned(n))) + +const uint8_t ALIGNVAR(256) LOREM_IPSUM[] = +"Lorem ipsum dolor sit amet vestibulum. Eget porta lobortis aptent eget in. Nec id justo. Vitae ridiculus massa. Sapien commodo semper. Nullam quisque pulvinar lorem mattis purus. Quam litora lobortis ante pede augue. Purus varius pede. Tristique lacus elementum sollicitudin sit a. Sapien ut a. Justo a dapibus. In faucibus eros nunc nulla nibh curabitur cras amet dolor orci venenatis lorem nulla ut. Non malesuada pulvinar condimentum egestas integer. Proin ac rutrum leo id sit. Mauris dis fermentum. Non faucibus autem sem et dolor ultricies sit porttitor quis eget quisque commodo elit sed. Ut enim amet ante ornare eget. In placerat officiis. Dui libero a. Amet id velit sed ut aliquet tortor et morbi aliquet ante id. Quam sed dui duis quis etiam at eget eleifend. Ut aliquam odio. Porta elementum tempor. Commodo vulputate nonummy in aliquam voluptatem. Tristique ipsum excepteur. Urna porta nulla nec in morbi felis odio cupiditate. Risus vehicula hac porta sed amet curabitur blandit mauris in adipiscing ridiculus. Purus in tortor ac curabitur a commodo fusce sapien. Aut in ac mollis porttitor gravida magna volutpat enim. Libero elit lectus. Sem eget aliquam. Proin nulla tempor augue nascetur sit. Blandit eros venenatis. Duis erat facilisis. Erat dui nunc magna voluptatem duis. Velit hymenaeos ante et nulla sed ullamco praesent viverra lobortis nam nunc. Molestie bibendum nulla. Blandit est pede a malesuada est massa feugiat iaculis nam ac vitae tortor lorem enim. Nibh habitasse porta vehicula integer gravida sem condimentum pharetra. Vehicula quis in aliquam quam mi vulputate laoreet donec pede erat neque. Dolor vitae suspendisse. Et pretium tellus nec eu ultrices. Faucibus odio nec proin auctor a morbi in ante lectus urna ligula commodo libero elementum. Neque a volutpat in ipsum dui. Luctus bibendum aliquid purus dolor adipiscing. Volutpat sit posuere erat placerat senectus eget in vestibulum ipsum pellentesque nec. Wisi vitae lectus elementum aliquam diam adipiscing in enim lacus libero pretium donec pellentesque tincidunt. Fusce mi ante. Nibh sodales aliquam posuere tempor quis iaculis in integer. Euismod non vitae. Turpis cras ultrices ut tortor in amet blandit fusce. Ante lorem pharetra. Voluptates dictum ipsum. Quam ut et. Dui egestas lacus vehicula massa augue placerat justo amet. Facilisi rhoncus eros. Nam vitae quam. Enim imperdiet ipsum. Integer lorem id. Pulvinar eu ligula. Vulputate vestibulum id fringilla nulla ante. Hendrerit duis aliquet neque massa ut tempus fusce turpis. Lobortis nulla praesent. Nec dui dolor dolore in et. Arcu con vitae scelerisque vitae in. Quisque mauris in. Porttitor sociis odio id a sagittis ullamcorper arcu amet. Lectus a semper donec quis ut erat leo at. Vivamus wisi massa nullam vestibulum sed suspendisse mauris ligula. Mauris facilisis accumsan. Conubia vitae integer blandit magna feugiat ullamcorper vitae orci malesuada odio per lacinia lobortis enim suspendisse tempus quis aenean sed lacinia sed sit hymenaeos. Vel vehicula quisque erat blandit sociis cursus maecenas feugiat integer neque arcu morbi magna in in vestibulum wisi mauris vel anim. Est enim ipsum donec debitis sed proin commodo vestibulum. Iaculis luctus lectus. Id mollis nibh proin sed enim sem vivamus eget bibendum vitae nulla. Ligula dolor fusce. Ut sed platea venenatis fringilla viverra. Tincidunt pretium quis. Nec amet dolor. Fusce ut vestibulum. Vitae adipiscing at. In aliquet in. Amet mattis fermentum neque adipiscing ut. Sit aliquam iaculis. Hymenaeos eget egestas. Odio purus curae. Non incididunt mollis. Lobortis auctor convallis pretium consectetuer accumsan. Ornare tempus tempus mi turpis venenatis euismod leo eros ante adipiscing auctor tellus eu sem quam mi luctus elit pellentesque pharetra. Enim ac ultrices feugiat a eget id amet tempor donec justo vulputate nunc sodales arcu leo commodo amet. Aliquet odio donec. Praesent eget ut non quia justo. Praesent rutrum integer. Non libero porta lacus duis elit commodo turpis erat rutrum quam elit velit incididunt at. Lectus erat scelerisque. Amet velit nulla. Integer nam rhoncus volutpat neque pede. Vestibulum a amet. Porttitor nibh donec tellus libero dolor. Elit sapien augue suspendisse integer curabitur. In sed rhoncus. Donec turpis ut. In vehicula suspendisse porta mi interdum. Luctus dapibus eu. Nec et turpis eget risus aliquam. Potenti nulla wisi amet massa molestie. Posuere non justo ullamcorper eu suscipit morbi nostra interdum habitasse amet risus et metus et. Urna praesent odio in nulla etiam volutpat imperdiet congue mattis consectetuer felis. Dolor molestie rhoncus. Felis mauris lacus. Fusce quam cras. Libero felis duis aliquam eros in. Felis nec diam eget duis mauris facilisi sit ipsum. Vestibulum aliquam urna tortor tempus id. Non praesent sodales sagittis quisque praesent. Nulla eget scelerisque wisi in dolor habitasse tristique donec. Cras sociis ut in amet amet. Netus tristique ut. Pulvinar ut at erat quis mi. Metus suscipit velit potenti pharetra ullamcorper. A in eget volutpat enim sodales tellus sed mauris elit odio amet. Nunc a vitae. Mi est vestibulum. Morbi vivamus massa. Lorem mollis nihil. Etiam nec neque. Lorem auctor amet posuere erat lacus arcu risus amet. Habitasse ultricies nec in sit sit amet a nec donec morbi id elit eget id quis turpis wisi. Tincidunt sed velit. Iaculis bibendum curabitur urna taciti torquent massa pellentesque dignissim. Neque in con. Dis fusce tempor ac torquent porttitor consequat nulla dolor. In posuere a duis suspendisse augue. At id velit. Neque occaecat vulputate. Aliquam mi sit donec lobortis sed magna ante nulla donec purus maecenas. Quam eget mauris curabitur morbi vulputate. Neque mauris adipiscing. Vestibulum quis non. Quisque vestibulum nisl duis scelerisque eget nam dictum commodo praesent pulvinar turpis auctor massa lorem. Lectus molestie mattis. Amet interdum malesuada ac morbi pellentesque. Sed lorem quis. Pellentesque sed etiam purus sit aenean. Ipsum mattis tempor. Morbi nunc justo. Amet scelerisque donec ipsa eu praesent. Eleifend semper pulvinar leo lectus quam venenatis vestibulum ac. Facilisis lorem dolor enim est quisque feugiat quis eu pede nisl est fermentum nam habitasse. Tempor sollicitudin ullamcorper tellus sociosqu phasellus. Sed eget congue. Nisl diam ante. A viverra sed neque arcu vestibulum. Dui lacinia maecenas lacus pede consequat ut donec et. Id et pellentesque risus at dictum placerat nascetur nunc odio tortor odio quam aptent ligula. Ipsum odio fermentum. Sed ipsum con. Cubilia est phasellus. Pellentesque sapien pellentesque. Faucibus velit risus. Vel turpis vel qui ut pede. Eget ridiculus dolor rhoncus tristique eros. Minima est vitae. Enim venenatis mauris eget et nam sit nunc turpis. Quidem turpis integer. Sed lorem nunc. Pellentesque nibh purus. Enim viverra nec felis luctus orci. Sapien ut quis luctus non wisi. Parturient sem faucibus elit consectetuer massa. Vitae diam vestibulum. Inceptos pellentesque erat hendrerit ut sit. Facilisi ullamcorper maecenas dictum et purus aliquam magna suscipit. Ullamcorper id egestas. Lorem odio tellus. Metus orci pede auctor eget imperdiet tellus amet eget. Sed ante praesent lorem quis fermentum. Est eget integer. Id aliquet lacinia semper justo lectus vel magna quam arcu sed tristique. Duis bibendum pellentesque velit nullam in purus in convallis facilisis pellentesque risus ac nullam neque. In deserunt iaculis fringilla fringilla et. Volutpat consectetuer dolor. Erat ante dictum nullam eu dapibus. Iaculis arcu ligula. Vulputate vel arcu vel maecenas eget et adipiscing sit. Sit donec elementum lobortis massa justo erat donec et integer ut justo. Ultrices aenean at a dolor eu proin malesuada gravida. Nibh odio lacus. Ut maecenas placerat vel felis sed tortor sit duis sit nibh orci et ut ligula. Metus arcu ante. Vestibulum etiam risus pede quis euismod pellentesque ac integer. Eu leo quis ut feugiat duis nec wisi consequat blandit malesuada velit turpis hendrerit duis. Nunc ipsum pellentesque volutpat a nunc mauris est in pede nonummy faucibus. At turpis accumsan. Eros eu tincidunt nulla ipsum dignissim. Vestibulum fermentum nunc. Aliquam nunc vestibulum. Nulla blandit sem natoque duis tincidunt. Eu vestibulum felis erat taciti risus. Nam vel tortor vivamus bibendum vestibulum. Vitae magna mauris nam mauris nulla pellentesque class lectus nunc ante per. Amet eu nunc. Lacus est phasellus malesuada pulvinar vestibulum nisl phasellus magna. Integer vivamus vivamus. Venenatis ligula felis nec accusamus sed quis maecenas purus nec nunc viverra proin diam hac. Ullamcorper congue facilisi. Praesent ante tristique. Dapibus leo mauris. Eget vivamus felis nulla vitae aliquam ullamcorper quis orci in bibendum elit quis augue id. Vel nec blandit. Tincidunt quisque nec vestibulum a euismod mi vehicula euismod. Diam officia accumsan non vulputate nullam enim fermentum eu. Mi in feugiat. Arcu tortor nibh. Arcu velit luctus. Arcu tortor urna. Nullam vitae vestibulum maecenas purus varius et leo qui sed faucibus massa felis pretium eget. Elit praesent in. At curabitur condimentum massa curabitur sed pede laoreet nec at pellentesque sed nulla at est. Tempor sollicitudin quisque. Porttitor amet sit. Elit a wisi. Sit id suspendisse et ornare tempor nulla eros sodales sit felis pulvinar. Vivamus arcu vestibulum pharetra vel dui sit consequat mauris proin pellentesque porttitor quis aliquam mauris amet sapien velit elementum integer a. Magna sit tristique. Augue faucibus morbi mollis venenatis nulla arcu et pretium nulla fringilla sagittis. Interdum vehicula sodales. Nisl vestibulum ut molestie arcu ac. Consectetuer vestibulum deleniti. Id donec et. Justo et cursus duis urna ut sed ut tincidunt ullamcorper orci elit. Ullamcorper nulla quisque consectetuer dictum nam. Vivamus et interdum. Rutrum elit lorem cursus dolor turpis. Vestibulum lectus pede. Ligula arcu quam suscipit gravida rhoncus amet faucibus amet. Sed vehicula dui. Lorem venenatis sed. Libero parturient et. Quis magna mattis. Gravida ac lectus ad aliquet lacus tellus tortor pellentesque nibh aliquam nesciunt mauris pede faucibus sapien enim quis qui quisque fringilla fusce arcu nullam suspendisse nisl lobortis dictum ut sed. Est non eros ornare commodo convallis. Mi libero in. Nulla et consectetuer. Phasellus eu morbi. Ac ut purus. Massa est eu facilisis eget sem curabitur tristique at. Nullam sodales pharetra at est at in integer at lorem vel natoque. Velit molestie faucibus sem magna nunc. Sit lectus maecenas. Erat pede cras velit ultrices ipsum. Wisi nec penatibus mauris et congue. Neque nulla non. Arcu a porttitor augue id mauris. Tincidunt dui vivamus fringilla eu dictum integer cursus suscipit libero praesent diam ligula at massa ante leo massa eu quam neque. Ornare id euismod neque ridiculus eu ullamcorper semper rhoncus pellentesque malesuada id dolor maecenas dui arcu suscipit proin. Lacus sapien scelerisque conubia gravida lectus. Varius dictumst mauris penatibus sed ante. Ante dignissim quis. Ullamcorper pellentesque pulvinar. Pede ante imperdiet justo pretium ut ac nascetur cras et mauris vel in dignissim massa. Mauris vestibulum pellentesque libero officia habitasse. Ut amet ligula. Cras class lectus semper urna tortor. Sem amet vehicula. Dapibus nibh tristique. Etiam nisl praesent cras quisque donec. Pede sed massa. Nec dolor arcu. Elit id volutpat. Natoque habitasse nec. Per sit facilisis quis mi nec. Vestibulum cras lorem. Neque vestibulum accumsan. Quis ante lacus urna et lacinia viverra ad aliquam suspendisse wisi nec vestibulum tristique porttitor massa vestibulum tempus vel ac fringilla magnis suspendisse nulla. Pellentesque interdum eu. Amet augue accumsan tellus massa donec. Conubia eros amet. Velit neque enim. Erat eu lobortis. Tortor veniam velit. Erat ac in. Vitae quis justo ut volutpat massa vitae turpis et vivamus integer eros et deserunt consectetuer. Fusce eu quis. Voluptas non aliquam. Adipiscing nulla accumsan magna eros ut sit egestas at. Sed scelerisque maecenas. Maecenas at aenean diam pellentesque consequat. Parturient dis orci proident ut in. Leo vel rutrum rhoncus vitae et orci ut ac turpis porta sodales. Vel in eu velit adipiscing quisque amet mauris eu. Nec est ac eu in accumsan orci et elementum odio suspendisse vel ut con odio vestibulum quis lorem. Vitae id arcu. Aenean sit quis. Turpis vitae ultrices sit amet leo. Ante pulvinar felis. Nunc sed vestibulum iaculis in curabitur. Mi venenatis curae natoque placerat erat lorem integer eu dui proin ultricies. Aliquam varius proin egestas vehicula id consequat quis enim. Urna volutpat in. Dolor donec maecenas. Duis ultricies condimentum in euismod sapien lectus blandit donec porttitor ac mauris. Nulla sem ultricies vestibulum risus risus. Aliquam nec luctus libero elit accumsan. Eget bibendum vestibulum. Id nec sequi eget eget at. Neque eros dolor fringilla consectetuer dui varius convallis vestibulum. Congue sem ut. Euismod luctus placerat. Adipiscing donec consectetuer. Quam eleifend curabitur nulla sapiente aenean gravida gravida tempus. Eget dui eu pede sodales morbi. Adipiscing a elementum cursus non habitasse. Nibh nec aenean. At pellentesque sit metus blandit fringilla. Varius auctor augue sed id vivamus sagittis turpis ante et facilisis est tellus praesent blandit id id ipsum mauris fermentum libero eu fermentum vitae mauris amet non tempor augue est suspendisse duis id. Tristique dui commodo. Etiam a pede in in lectus. Quis quia eget non nisl integer rutrum est consectetuer. Nec lectus id. Mi ac vitae. Nulla mi eget suscipit id ridiculus amet nostra lacus convallis pellentesque velit. Praesent quisque tincidunt. Enim sed maecenas sociis nunc massa. Nascetur delectus sapien doloribus inceptos amet. Mauris orci morbi. Tempor nunc et. Nunc elit condimentum sed eu dui. Eget convallis at. Elit velit etiam. Et accumsan eu etiam eget nullam. Vestibulum porta vel neque vel non. Enim fames magna venenatis lacus tincidunt. Arcu nunc tincidunt dui vestibulum neque. Curabitur ipsum suspendisse. Purus suspendisse luctus. Metus fringilla lorem. Sed libero minus. Elementum nunc vel elit nec nec. Id in nibh. Malesuada in volutpat. Blandit felis fames. Fringilla auctor ipsum semper lorem morbi et sit metus. In blandit sem. Leo pede vel ea felis sem. Libero amet sociis. Morbi sed dictum. Donec ante erat. Perspiciatis eget eros. Mi pede volutpat. Sed ipsum semper. In quisque lorem enim eget mi. In id malesuada. Ridiculus pede nam. Aliquam nibh aliquam. Vivamus lacinia nunc. Praesent ullamcorper ante quam sollicitudin elit et risus egestas. Interdum nonummy arcu ad ipsum accumsan mattis potenti et. Purus a vel. Eget magna ut. Consequat egestas quis. Dolor urna risus. Fames gravida nisl id quam vel. Integer purus fermentum velit a in. Aptent mauris ut odio arcu lacinia. Nulla dolor leo. Tortor aliquam ut eget metus eu suspendisse erat porta ac mauris eu. Mattis nisl neque enim massa lacus. Euismod vel varius rutrum mi nibh. Litora vestibulum turpis phasellus vel nisl. In erat sagittis sed congue penatibus eget ac malesuada. Eros ridiculus vel suspendisse vel tincidunt cursus rhoncus mollis. Proin vel sit. Velit erat odio. In eu congue dis purus eleifend at suspendisse lacus convallis mauris sollicitudin. Lacinia ut malesuada ut aliquam etiam. Ullam mattis tempor natoque turpis augue. Mollis nec vestibulum. Aliquam massa nonummy. Pede gravida amet. Lacus ipsum eu. Maecenas eu vel. Hac mauris platea enim morbi ultricies. Placerat sed non quisque vel sed. Ligula sodales ullam pellentesque ipsum tortor lacus neque id sed rutrum egestas. Curabitur arcu vestibulum vel mollis tellus urna adipiscing turpis. Tempus a non suspendisse diam massa. Aliquam donec amet nam elit dignissim habitant ac nascetur etiam ipsa vivamus. Lobortis congue voluptas. Elit sed quis consequat eros neque. Leo amet eu vivamus diam convallis quam metus ut ullamcorper enim eget duis sunt elit. Pharetra nec elementum. Augue vel integer. Vel massa pede. Et tellus sem. Porttitor in pretium. Sociis ultricies elementum. Ipsum a ac. Mattis a risus quis mauris nam augue aenean maecenas lectus nam in. Id ligula fusce. Et elit nonummy nibh felis per. Mi maecenas maecenas. Eum tincidunt donec condimentum est hymenaeos. Aliquam porttitor libero. Euismod ut id. Eu cursus nulla sapien feugiat nibh. Blandit dui sed fames eros erat cras magna nec. Vehicula suscipit aenean. Blandit mauris gravida pharetra pede vulputate. Morbi elit orci. Sem varius pulvinar. Integer magnis enim sollicitudin tellus turpis. Adipiscing nulla et nibh natoque praesent. Lacinia tincidunt sem. Ultrices libero dolor. Ut lacinia massa condimentum sociis sed tincidunt non ac ipsum natoque morbi. Vestibulum placerat quam. A ut a. Enim volutpat amet nonummy per in posuere elementum purus neque posuere facilisi tincidunt duis tortor eu quam dictum odio phasellus in a nulla ligula eros sit eget. Ad consequat a. Laoreet ligula non consectetuer rutrum arcu vitae elit vivamus id fugiat dui. Elit accumsan suspendisse libero leo massa quisque tempus nascetur. Aenean massa dolor. Suspendisse dolor hac. Tincidunt natoque accumsan feugiat diam pellentesque commodo vel dolor. Nunc libero maecenas pede felis nisl amet justo vitae in sit a. Id mauris morbi. Nunc non porttitor. Et lectus elementum nullam eget sit gravida pede euismod. Cursus sed proin. Vel gravida vel. Aliquam per ad. Hac aliquam enim. Elit sociis vulputate. Augue non lacus sed taciti odio. Venenatis sociis class lectus habitant urna a dictum turpis. Ante consequat augue et et vestibulum natoque donec auctor minim lorem nunc. Enim dignissim est est habitant maecenas. Voluptas conubia mattis arcu donec quis. Mi diam accumsan. Pretium donec ultrices integer massa ullamcorper. Euismod etiam vehicula. Sed non sem. Volutpat elit augue id inceptos vel. Dictum mattis per. Pharetra volutpat tempor etiam posuere mi. Sit est facere mi risus vestibulum id neque mattis. Metus a sed tempus ut proin. Praesent nec integer curae elit ligula egestas tempor sed. Dui risus ac est enim pharetra nam maecenas ante. Eu in magnam elit ridiculus donec velit orci diam. Rutrum mollis enim posuere pede nec. Repudiandae vitae quis habitasse taciti sed massa molestie interdum. Et nulla quam massa donec quisque. Amet mollis pellentesque massa ac euismod consectetuer amet fusce. Turpis eget auctor. Molestie ridiculus et. Mi et scelerisque lectus quis ac sodales pretium voluptate. Eros tempus duis vestibulum blandit ante. Magna eiusmod habitasse dignissim wisi turpis vivamus in nam. Suspendisse rutrum eu. A elit dictum. Rutrum lorem massa. Odio elit pharetra. Urna vitae mauris sagittis congue in interdum porttitor dolor. Est blandit interdum consectetuer at fringilla. Lorem pellentesque felis hac ultricies dui gravida justo lacinia quisque integer suspendisse id lectus felis nunc potenti amet sodales sed neque nullam risus sit etiam aliquam at. Fringilla elementum ut wisi libero neque integer scelerisque tellus. Quis sem sed. Consequatur vitae aliquip vivamus con at. Dui eros rutrum. Mi consectetuer nunc. Asperiores libero nam metus diam dictumst. Habitant non id. Placerat lacus enim etiam mi urna. Praesent libero nullam. Vel ante vitae. Aenean in accumsan. Et fermentum in. Egestas in arcu sapien id purus. Ullamcorper pulvinar integer. Sed eleifend urna dui vehicula dolorem et ut tincidunt risus sit amet. Diam in in. Ut egestas torquent. Vitae mattis volutpat ipsum adipiscing nunc neque arcu libero. Et ut cras. Eu ut vitae. Neque elit nam. Integer ligula nec augue vel nec phasellus pede ex parturient lacinia blandit. Venenatis lorem excepturi. Habitasse mollis fermentum dolor feugiat tortor etiam a cras facilisis duis consectetuer. Suscipit ut risus. Felis consectetuer arcu aliquam malesuada lacinia orci justo ornare feugiat ipsum lectus et conubia ac magna justo vitae per lacus mauris amet ac pellentesque ac wisi lorem. Libero sollicitudin aenean. Vitae pede tristique mattis voluptatibus lobortis. Integer feugiat et mattis imperdiet lobortis luctus placerat dui non nec velit vel quis interdum aenean blandit metus. Blandit placerat erat. Donec nam hendrerit. Porttitor facilisi sed leo perspiciatis lorem. Hendrerit sollicitudin class aenean nec luctus. Gravida maecenas sit montes in vel. Ut dignissim id porro mollis interdum fusce eget in et ullamcorper nam. Ut egestas amet. Ut vivamus sagittis mi nunc nunc. Aliquam a nunc. Mi aliquam quis aliquam vestibulum et. Ac metus ornare. Lorem nullam cras. Diam consectetuer nunc. Cras dolor etiam velit magna vitae nunc fermentum lectus. Hendrerit mollis et. Sed voluptatum posuere. In montes duis commodo laoreet maecenas. Quis cursus dolor magna non odio. Eu sagittis odio semper erat augue. Dolor ultrices dictum. Et vel orci. Donec augue odio quam quam odio semper id consequat. Donec pede orci. Ornare ornare asperiores. Convallis porttitor nunc phasellus vestibulum convallis ipsum proin nec felis lectus accumsan. Netus orci pretium. Cras magnis donec porta repellat est. Rhoncus amet sit. Montes dictum aenean. Amet donec est. Ultrices etiam convallis ac varius auctor tempor facilis ac. Mi placerat mi. Diam pulvinar dis neque odio sed. Nec interdum placerat. Vel lorem facilisis vel ut pede in tempus eu velit sed eget praesent porttitor lacus. Wisi nam vel. Blandit posuere sed ac nam nisl at magna nunc consectetuer ac augue magna malesuada ultricies aut mattis praesentium malesuada justo sit arcu amet ipsa. Magna phasellus pellentesque. Magna faucibus quis. Et arcu reprehenderit lacus euismod at consequuntur tempore nunc. Ultrices vestibulum sociis pellentesque aptent massa fringilla enim pulvinar a auctor purus. Laoreet non vestibulum. Praesent tellus ante sed lorem et. Diam ultricies mauris. Blandit ut lacus. Sed nulla dignissim velit non nunc magna volutpat nisl commodo semper felis luctus habitant non. Ligula magna nisl vestibulum lectus nam. Fermentum massa praesent. Sodales felis varius suscipit sed luctus sit lectus tortor ac aenean tincidunt ac torquent curabitur nunc lacus sapien porttitor ipsum vivamus excepturi quam tristique. Ut id maecenas. Suscipit sagittis vivamus suspendisse ut in mi integer vel nibh id sed gravida iaculis ac. Magna commodo velit. Amet risus commodo morbi in mus. Ultrices condimentum ac. Eu augue interdum vitae tortor natoque ligula nisl vulputate conubia ut diam nec eget pede. Tortor vivamus sed massa commodo gravida nunc eget eget lorem molestie nullam. Tempus tortor nonummy. Enim porta reprehenderit. Massa ut pharetra convallis nec turpis augue viverra suspendisse quam ac pellentesque scelerisque tincidunt tortor morbi non eu varius neque dolor arcu euismod purus vitae suspendisse gravida. Gravida in eveniet. Porttitor quod est. Eget venenatis sed. Turpis porta ipsum. Eu velit integer morbi phasellus ac. Arcu eget etiam cras malesuada con. Aliquet sit orci. Hac augue semper wisi vel nulla ipsum id risus felis sapien ultrices. Sit amet erat. Risus sodales porttitor. In in consectetuer. Luctus mattis nulla. Aliquam leo velit eaque nonummy porttitor litora nam nullam facilisis elit ipsum praesentium mauris ut in sed etiam amet sapien mauris. Tellus ac libero. Libero arcu vivamus. Ipsum massa integer. Eleifend vestibulum egestas. Minima ridiculus tristique risus turpis et. Sed quisque tristique. Sed ipsum risus feugiat et dui. Pellentesque vivamus urna. Integer fermentum eget fermentum eleifend felis arcu arcu erat consectetuer et feugiat. Rhoncus condimentum quis. In elit sodales posuere amet sit. Pharetra metus odio egestas maecenas ut. Aliquam vulputate sollicitudin. Proident habitasse arcu dolores arcu donec. Neque malesuada metus. Erat ut facilisis diam velit quis. Montes erat morbi ac vel ut hendrerit neque non. Vel proin magna. Molestie ut luctus. Morbi libero et cras volutpat erat. Feugiat vestibulum sem eros vel convallis quis nec cras. Molestie tristique dictumst. Felis luctus ab ultricies tempor posuere ante magna mollis. Mauris nunc per sed luctus vestibulum. Cras sed dictum magna ut pede. Vitae erat tortor et donec vel. Blandit semper id. Tincidunt quis elit. Eu sint nibh. Pellentesque vivamus interdum. A sem massa. In netus nec tortor massa rutrum. Cras nullam magna nostra tellus ultricies. Molestie vel nonummy sit habitasse metus. Duis tristique mauris. Tempor sit vitae massa sit mollis turpis nostra eleifend elit felis ac. Tellus dolor eu dapibus egestas aenean. Libero quam consectetuer. Elit eros hac et volutpat hac. In massa sed elementum wisi semper. Vivamus ut volutpat. Mauris in placerat. Leo tincidunt dui. Imperdiet non integer curabitur pede iaculis adipiscing consequat augue. Phasellus vivamus enim. Morbi vel platea quam vitae consectetuer. Sollicitudin eget ante. Vitae mollis suscipit. Ante dolore nam feugiat non mollis vel nec sapien maecenas rutrum in ligula suspendisse fusce pretium ac nulla. In lacus sollicitudin metus tortor pellentesque leo libero elit. Feugiat habitasse eu. Sodales duis consectetuer. Quisque mauris tincidunt. At vivamus velit sed amet aliquam. Massa nunc massa. Ridiculus eros nulla suscipit lacinia arcu. Nunc nihil inceptos. Est nunc nec. Volutpat ut euismod pulvinar vitae mi. Rutrum ipsum quisque dolor sodales morbi ante phasellus mattis. Nec odio nulla eu porta euismod. At nisl at pede urna consequat. In pharetra vestibulum pede diam varius venenatis hendrerit velit massa et a natoque in amet metus amet elit. Donec lectus lobortis. Nam nihil tristique. At aliquam turpis. Viverra nec urna. Odio lorem sit iaculis diam platea auctor pede nulla. Eu velit ullamcorper. Enim per viverra. Eget in ut. Amet eu sed convallis lacinia libero mauris aliquam sed. Tellus incididunt pede amet etiam a cras sit et nunc ultrices gravida feugiat ligula amet. Platea conubia interdum eget dapibus eget metus ligula odio. Odio et et sapien sem quis mollis vestibulum quisque. Accumsan sit sapien. Con ipsa praesent ad porta sociosqu augue donec in vulputate magnis non. Wisi pellentesque posuere imperdiet nam consectetuer id ac dolor morbi ipsum lectus. Per non lacinia sed mi urna. Feugiat eum orci. Dis pulvinar in. Lectus sed luctus pede tristique porttitor. Mauris placerat vulputate nullam habitasse purus nascetur ipsum vel. Felis dui sit aliquet nisl non. Pharetra a porta. Suspendisse morbi in. Sed elit luctus sapien porttitor curabitur sed platea ac. Urna nisl amet donec blandit dis. Per morbi non nunc sed et. Mattis mauris rhoncus ornare ultricies a. Integer quis nulla tempor lobortis in at in lacus curabitur porta condimentum at dolor arcu. Erat mus porttitor donec amet ultricies. Volutpat penatibus hac nostra elit tellus orci nunc enim dictum fermentum duis. Interdum tortor consequat pellentesque odio sed tempus adipiscing in lacus metus lectus. Ullamcorper sit quis feugiat eros nunc. Amet fringilla ut maecenas eros tempor. Sed neque donec. Lacus mi urna velit lectus nascetur viverra dignissim volutpat aliquam felis hac iaculis ultricies sodales amet quis ut. Metus turpis sit. Vestibulum ultricies nunc. Suspendisse turpis numquam volutpat at pellentesque. Gravida massa duis metus nec id dui morbi aliquet. Suspendisse metus aptent varius nibh auctor. Amet nisl vel. Interdum aliquam quis. Viverra auctor enim vitae erat vitae. Aliquet suspendisse felis platea rerum ultricies aliquam massa commodo diam lorem accumsan. Ante vel curabitur. Nisl magna in. Vitae lobortis vehicula aliquam hendrerit dis turpis vel nonummy id blandit donec con sed diam quis purus neque amet magna luctus. Proin felis elit. Est facilisi vitae fusce dictum erat lectus elit ut. Est rhoncus metus. Ligula duis lacinia. Sed maecenas blandit dolor fusce et. Sed sapien proin sint ut eget lobortis suspendisse elit. A amet amet neque nec consectetuer. Rutrum in orci faucibus interdum a. Alias senectus rhoncus tellus vivamus est. Pellentesque posuere facere est tincidunt pede nec ac nulla. Amet ornare urna. Id ut at. Augue quis eget nec sapien ultricies. Dignissim hymenaeos ultricies. Ullamco vestibulum con ac at ante donec id feugiat. Ipsam aliquet nunc. Pretium lobortis lacus rhoncus justo donec. In in sapien. Suspendisse felis fusce. Lacus sit eu. In et ut vitae mauris mauris vehicula ultricies quis ac condimentum suspendisse ut class quisque. Lacus eu leo. Nam ultrices hymenaeos. Justo quam lacus wisi eu enim vitae gravida blandit in venenatis ultrices metus interdum eu aptent facilisis in est nullam eget lorem ac odio netus ridiculus fringilla sed dapibus leo. Elementum vehicula lacus. A purus aliquam. Arcu vehicula lacus sed scelerisque odio. Nec pede tellus. Pharetra enim egestas rutrum nam wisi. Platea proin sodales. In condimentum dignissim. Amet platea imperdiet. Dui donec donec. Varius rutrum massa. Purus amet aliquam a vulputate ligula. Amet mauris tempus. Aliquam pellentesque diam dolor pede elit. Sed reiciendis vehicula ipsum velit bibendum. Nunc accumsan facilisi. Nibh turpis orci et vestibulum pede ut convallis nunc nunc etiam mattis. Elit et sagittis. Accumsan posuere est. Elementum quis fermentum elementum nullam eu. Sodales morbi quisque non velit in. Aliquam in nihil amet dignissim aliquam. Quis et integer sit malesuada justo. Sunt convallis lacus. In donec donec. Nonummy volutpat posuere. Eget a pellentesque. Varius augue elit. Metus felis blandit consectetuer donec nullam. Fusce velit non ac erat eleifend odio volutpat justo. Viverra pede volutpat cupiditate sed mauris mi tincidunt eros. Consequat massa lectus. Elementum nunc tellus risus sapien sed. Ultrices eget aliquam. Imperdiet tempor ipsum molestie eros montes tortor sit sagittis aenean volutpat augue donec neque wisi. Nam nulla elit. Quis lacus lectus accumsan tellus rerum. Dui posuere libero at sem nec velit est at. Integer dui sit id etiam ut est volutpat posuere sed vivamus non. Non posuere aliquam. Sagittis vestibulum ipsum. In mattis nunc at mus tempor quam rhoncus blandit ullamcorper ullamcorper arcu. Quis luctus wisi. Dolor odio tellus eleifend et pellentesque orci et ac. Eget mauris at condimentum justo mauris. A praesent lectus. Nulla nonummy etiam. Ullamcorper venenatis massa. Ante ac potenti. Urna sed diam metus vehicula laoreet quis mauris nullam est pellentesque sit faucibus cubilia repudiandae. Id justo volutpat. Dui wisi nullam est eget fringilla felis aliquet at sit sed volutpat aptent quam vulputate. Cursus euismod venenatis eros non rutrum. Aenean pellentesque placerat quis vel sem. Fusce mauris at metus et justo nec sociis quis. Nisl id fusce. Mollis ultricies metus ut laoreet sed turpis fusce turpis. Suspendisse aliquam nec. Vivamus donec mollis consectetuer in mattis nibh blandit nec semper dolor vel convallis necessitatibus nulla. Auctor aliquam nibh. Ultrices mattis felis nulla luctus aliqua at tristique hendrerit. Sed ipsum rutrum gravida vestibulum eget. Etiam hendrerit accumsan iaculis magnis in. Condimentum amet nec lectus scelerisque tristique. Sem dictum et eros in morbi erat tincidunt praesent fusce porttitor pellentesque. Morbi sagittis fusce. Curabitur augue semper. Congue molestie sapien. Dis dictumst posuere. Mauris ut erat. Suscipit dictum parturient justo magnis nibh. Mauris magna pede. Scelerisque dui libero vestibulum justo morbi. Leo scelerisque potenti. Consectetuer bibendum ligula tempor amet condimentum aliquam imperdiet ornare. Nullam varius amet amet nec et. Quam dui vitae nibh dolor nec nibh lacus a. Magnis enim nonummy. Tellus venenatis fusce. Ipsum a non. Tellus euismod cras. Dapibus nec a proin eget et. Morbi con nisl sit sed ut. Est dictum erat ornare nam convallis et magna mattis id ac sagittis urna ante curae. Nullam a tortor. Orci nesciunt phasellus. Lectus ex fermentum fusce sed rhoncus. Sed urna enim consequat aliquet in interdum massa molestie. Ut dignissim nulla. Eget lectus magna ac enim litora. Mauris condimentum incidunt dolor volutpat velit. Adipiscing et ipsum amet senectus sodales dictum elit amet aliquam sed urna ligula netus metus. Amet volutpat sit nulla id rhoncus. Elementum pretium nisl quisque in libero risus id officia. Elit donec vestibulum. Ac magna euismod. Vivamus at adipiscing sed vivamus enim. Vitae convallis congue. Turpis feugiat viverra sed justo in. Sodales wisi tristique id adipiscing elit metus libero mauris. Mauris sit id turpis eget id. Sapien odio ipsum. Eros vel vel lacinia mollis aliquam congue pellentesque tortor suspendisse ligula cras a eu sed. Sit convallis fermentum. Nullam posuere massa id vel mauris. Fringilla egestas in. Bibendum deserunt curae non in bibendum. Nibh lectus rutrum. Enim vitae sed. Ac aptent et. Sed libero magna. Pretium risus vel. Nullam malesuada vulputate. Sodales libero lacinia. Nibh tortor neque. Lobortis etiam massa fusce dolorum libero. Nec ipsum velit malesuada tincidunt vehicula. Conubia curabitur placerat adipiscing ac sed. Amet orci consequat tortor posuere ut. Vitae ipsum a. Risus malesuada eget ornare sit vitae. Tellus lobortis rhoncus sed massa donec neque quam aliquam ac bibendum a. Feugiat tristique viverra. Turpis nam litora bibendum lectus sodales iaculis libero fusce. Turpis quibusdam ut. Magna justo elit nisl scelerisque vivamus lacus eu massa ultricies ante elit. Ante volutpat lobortis. Suspendisse suscipit diam. Tincidunt nec etiam. Elit enim est. Etiam mauris nulla commodo purus vulputate sed ante id eros tortor mi tortor non vitae. Distinctio erat volutpat. Et cursus ornare. Libero eu ullamcorper augue vestibulum eu. Tincidunt libero et sodales vestibulum mus. Proin nonummy sapien. Ac nullam id. Eget et sed eget fusce tortor. Nascetur in ut donec egestas vel. Luctus viverra amet. Cursus at nam. Mauris vitae mauris duis vivamus nec. Mattis lacus est quam metus nullam tempor amet mattis mauris adipiscing risus. In pharetra vitae. Tincidunt volutpat orci in malesuada quis sed convallis vitae eu pulvinar ac dictum leo sed laboris quis sit. Venenatis ut amet massa platea at. Sagittis lectus porttitor. Dolor vitae sagittis qui consectetuer con. Eu dolor sit. Dis nulla duis accumsan neque id libero ac suspendisse a est tellus interdum condimentum velit. Massa phasellus ut. Magna justo in. Est donec ut. Conubia nam pede. Sit scelerisque nec. Accumsan felis mauris arcu dolor sem. Quam velit tellus. Tristique nisl risus. Suspendisse nam curabitur. Lorem eget nisl purus urna quis eu egestas pede. Porttitor arcu turpis. Reiciendis dignissim nullam a ipsum elementum. Nunc vivamus arcu diam sed ut wisi pede eget non est facilisis aliquam eu etiam. Suspendisse mattis pellentesque. Pharetra soluta rutrum. Eros sed pede. Urna ultricies et consequat et volutpat vel quam cras. Nonummy ut integer eros imperdiet at interdum mauris occaecat. Mauris elementum libero. Quis blandit sed. Pede eget sed morbi sed sed. In mauris a. Lorem integer felis neque porttitor justo lacus laoreet lobortis. Id quam nunc ipsum in quis nulla pellentesque vestibulum ac pede augue dolor penatibus et elit enim mattis. Proin quam in sit orci mattis ac litora massa sollicitudin pellentesque sit. Sit etiam purus. Tempor eros class sit adipiscing leo. Augue luctus ac nunc urna vivamus morbi luctus venenatis. Sit convallis at. In fringilla donec ante adipiscing elit quam dignissim tortor. Doloribus blandit at. Est mauris sollicitudin. Sollicitudin vulputate malesuada. Luctus mattis eu. Luctus vestibulum id. Nec odio a. In lectus sollicitudin nec ac laoreet aliquam tincidunt convallis risus in arcu lectus sed ante. Ut natoque fermentum. Nibh expedita mattis. Quis aenean in donec cursus suspendisse. At a pellentesque justo tellus platea. Id libero condimentum justo laoreet vivamus. Ligula duis penatibus. Porta vivamus at molestiae sollicitudin amet imperdiet ipsum egestas. Cursus volutpat at. Phasellus cursus velit tempor condimentum nec ipsum nulla phasellus proin vitae nam gravida nisl sit. Class vehicula et. Et hendrerit porta in sit eu eleifend augue leo sed ipsum tortor ut adipiscing eget. A nostra enim. Enim quam duis et proin lectus. Con donec rhoncus nec class sit nunc in egestas sem lorem id. Quisque sagittis non. Donec nonummy lorem nibh nunc sapien sagittis purus nisl lacus augue ligula vitae vulputate rhoncus ut in sem. Sed ante in. Sit posuere libero. Sit sem nec. Faucibus vivamus volutpat aliquet fugit nam donec blandit sed nam congue amet congue est id aperiam quisque quasi. Ante aenean ligula. Vel maecenas nullam. Ac vitae sem velit mauris auctor. Nunc inceptos at ac lacus at lectus feugiat tortor sint luctus aliquam ultrices dignissim phasellus. In pede aenean lobortis egestas sed. Tellus nunc vivamus quam aenean rutrum. Turpis vehicula penatibus. Vulputate eu tempor. Sapien suscipit dictum sapien nec suspendisse aenean hendrerit porta ut mi ultrices. Varius qui placerat. Et sed vehicula curabitur enim leo. Quis rutrum mauris purus eget lorem interdum justo et. Urna posuere euismod. Mi nibh amet odio amet viverra sed potenti donec placerat sed tempus. Habitasse a nibh mauris leo a malesuada feugiat proin quis sapien leo lobortis eu eget. Quam lacus sollicitudin justo a nisl ultricies lorem metus. Velit feugiat quam. Wisi est nulla. Tincidunt sed placerat magna eget fusce etiam ridiculus sapien. Mauris eros sit nulla bibendum in. Urna scelerisque dictum. Mattis donec porta. Justo vestibulum sem. Wisi tempus suspendisse fringilla laoreet occaecati. Fringilla vestibulum mauris. Eget eu quis quis donec nunc. Nulla sem lectus. Ac in consequat consequatur sit at tincidunt eu leo. Turpis dictum curabitur porttitor libero nibh. Consectetuer magna ac. Molestie vitae sit. Et hendrerit risus mi magna facere officiis lacus sed. Posuere illum tellus mollis eros porro nisl eget rutrum ipsum eget phasellus. Viverra dolor commodo et neque ut sed condimentum magna dapibus diam in. Est vulputate ut duis a eu lacus amet diamlorem. Integer bibendum aenean ac rhoncus sit. Tellus maecenas est nam tincidunt lorem dolores neque aliquam. Pariatur vel elementum ac vel sit. Phasellus id nec. Hendrerit ad rhoncus. Aliquam tellus felis. Libero praesent tortor vel suscipit odio. Nec integer quam est sodales nulla. Aenean interdum tempor. Aenean odio vestibulum augue vel malesuada. Vestibulum quod sit eleifend nulla id quam urna porta. Est nulla adipiscing. Lectus amet et. Cillum sodales euismod. Venenatis tempor arcu. Non lacinia in gravida aliquam aliquam. Montes justo semper curae at wisi. Eu quisque scelerisque in vitae congue ligula quisque elit. Justo pellentesque maecenas. Vehicula elementum mauris. Quis urna pede. Congue sed consectetuer. Dui vitae facilisi. Lobortis venenatis cras. Nibh id senectus. Fusce vestibulum odio. Posuere justo dolor ipsum nulla proin sapien minima proin. At amet sed placerat praesent fusce. Nam placerat libero. Vestibulum velit eget. Erat phasellus tempus. Vitae nulla tortor. Quam vestibulum placerat. Pellentesque quis ut. Mollis architecto et diam dapibus ac magna irure dictum eros eros parturient. Ut mauris id magna sed varius sem augue et. Fermentum fames integer ligula mauris id tortor voluptas justo neque curabitur luctus. Sem nec cursus. Erat amet neque. Pellentesque aptent curabitur adipiscing viverra non justo imperdiet diam. At vel enim fermentum cras nec sagittis aliquam in. Leo ipsum curabitur amet malesuada tellus. Aliquet interdum vel. Et odio ac. Et sit ultricies. Nunc in id sociis semper pede. At quisque non. Ac suscipit ridiculus dui porta quis. Venenatis vitae maecenas. Ut sodales nec. Aenean blandit velit metus vitae inceptos nec neque in. Ligula lectus aliquam ante duis nostra donec ipsum mauris est ut vestibulum ut proin id. Mus tristique maecenas. Leo sed wisi non tristique tellus. Turpis dolor scelerisque. Id aliquam sociosqu. Metus risus donec ipsum et volutpat. Quam felis viverra. Lorem integer neque. Porttitor sit erat. Vestibulum tellus volutpat. Mi aliquet porta. Magnis felis erat. Semper velit iaculis wisi nisl odio. Mattis vel condimentum. Facilisis lacus justo. Nullam urna non a est doloribus quam blandit vitae. Orci proin eleifend. Phasellus vehicula tincidunt. Ipsum urna quis pretium eget netus et quis tincidunt. Suspendisse at odio. Facilisi integer sit eleifend ultricies ornare diam metus at. Accumsan cras imperdiet. Quis fermentum eleifend maecenas lectus ultrices. Scelerisque vestibulum arcu. Arcu mauris suspendisse. Aliquam adipiscing amet. Vehicula et tristique dolor varius sit aliquam gravida metus. Semper euismod donec. Mus vestibulum tempus. Consequat quam at. Facilisis tellus pede. Amet at proin. Sollicitudin rhoncus amet maecenas sed interdum. Penatibus vestibulum vivamus. Lectus vel torquent. Maecenas faucibus massa est fringilla tellus ligula maecenas augue. Ullamcorper pharetra arcu. Mauris consequat egestas. Hac amet adipiscing. Vehicula dolor laudantium. Tempor tortor ante. Vel suspendisse porttitor. Erat vitae lobortis cursus vestibulum vestibulum. Est luctus tortor nullam sapien massa. Eros lacus orci nec neque consequat. Mauris nunc dictum. Eu cras orci erat enim erat. Reiciendis ut eleifend. Maecenas sit scelerisque. Suspendisse ipsum lectus mattis eu in. Id enim a. Placerat nam nunc congue mauris erat. Wisi duis est. Phasellus enim vel mi ipsum suscipit neque dui ligula metus wisi ullamcorper quis eget pretium. Laoreet vitae eget est proin in wisi id sit. Dui pretium scelerisque eu tristique sollicitudin aliquam adipiscing facilisis commodo tellus egestas. Con erat dolor. Libero non a. Ligula ultricies molestie. Mollis eros amet. Nulla sed et. Nullam sodales eget pede elit molestie. A ipsum rhoncus amet quisque luctus. Tellus lobortis vel. Adipiscing eleifend sed justo magna magna gravida magna cursus. Cursus sem amet arcu malesuada rutrum. Nec lectus velit hymenaeos pede vitae euismod morbi morbi. Vestibulum nunc quam. Sapien purus nunc gravida curabitur blandit. Velit fermentum mauris. Ante mauris nisl mattis quam in sit praesent dui. Aliquam porttitor dui. Arcu hendrerit dolor. Proin urna quam. Aliquam etiam malesuada. Vel donec wisi. Donec pede proin. Etiam eleifend tristique neque nulla aliquet. Integer purus volutpat eget nulla pharetra mauris eget vestibulum sit vel faucibus. Ultrices massa eu elit etiam faucibus. Corrupti vel maecenas. Viverra aliquet accumsan enim tincidunt mauris. Bibendum sed sed penatibus quam quam ipsum ipsum convallis. Orci egestas tellus eleifend scelerisque sed. Quisque aenean odio. Sed ea lorem phasellus est hendrerit. Iaculis nisl morbi donec enim aenean. Amet lacinia quam. Elit justo aliquet. Arcu duis risus velit libero maecenas et metus ligula et donec orci. Aenean dolor cras. Congue ac quis. Ullamcorper scelerisque lorem duis aliquip ridiculus. Amet senectus rhoncus felis morbi donec. Hac turpis non tellus morbi sapien. Nullam a dictumst. Eu convallis amet nascetur est dolor. Risus amet ullamcorper. Ut purus justo sed massa viverra et blandit sed. Et ligula lacus. Amet vitae in. Metus semper tincidunt. Tellus sapien non. Velit qui quis. Gravida vestibulum consectetuer at ut bibendum hendrerit quidem aenean. Mollis in et pharetra curabitur sapien at tristique ut elementum non in dictumst phasellus semper. Interdum quisque eget. Enim dui ridiculus. Ipsum donec fusce sem massa donec aenean tortor diam. Sem mattis at donec vehicula vulputate at pede dolor lectus euismod laoreet massa habitasse tempor. Nullam nibh aliquam a quam sodales aliquet eleifend massa tincidunt libero tempus. Tellus class amet. Elit id eos venenatis nam tortor quis ornare feugiat. Urna lorem suspendisse. Vivamus convallis eget pede id sem tempus hac in lorem faucibus cras. Laoreet ac quas neque metus suspendisse porta ligula malesuada in urna integer sapien pharetra lorem sodales feugiat pellentesque. Tincidunt ipsum sociis. Sollicitudin tortor integer. Sagittis lectus libero et sit etiam. Lacinia in praesent et semper at. Ut quis eros. Ridiculus porttitor libero parturient curabitur vestibulum. In commodo nulla. Venenatis non vulputate velit mollis consequat. Amet purus porttitor. Duis diam est suspendisse eu massa. Et rutrum eros. Volutpat cras bibendum. Libero aenean excepteur. Urna a nibh. Est enim et. Mauris eget non ut cras est. Dictum risus euismod curabitur nunc sapien. Pellentesque eu ut. Justo augue quam. Sollicitudin non eget. Quis vel sodales id imperdiet vivamus sit nunc sociis. Aenean interdum sodales. Sit vestibulum semper cursus id metus aliquam quam nunc fermentum nunc phasellus. Id nulla ultrices curae ut tincidunt non vestibulum rhoncus. Volutpat pede ante maecenas ipsum dictum justo faucibus iusto. Velit quam non eros massa tellus. Sodales rhoncus et libero aliquam adipiscing cras id eum. Sodales quis lacinia ac lectus quis. Cursus justo ligula. Eu congue tempor. Dolor orci nullam. In eget ante libero condimentum amet vivamus proin deleniti. Per in eu nostra dolor accumsan. Quam primis maecenas. Tincidunt id quidem vel porttitor ut. Mi suscipit et. Nunc id laoreet torquent ut iaculis. Nunc urna est eget rutrum aliquam rhoncus velit a sapien ac praesent. Cras ac tristique purus commodo aptent. Eget morbi dignissim. Tellus tellus vestibulum sed est feugiat morbi et dictum dui lectus arcu. Quis eu ac. Viverra sed eu. Aute neque mauris. Eget quam mollis sit sem volutpat. Aliquam vitae laoreet. Vel aliquam felis et ac id. Leo in vehicula ac enim et odio in nec. Ac cras massa imperdiet nec mauris conubia in tempus. Accumsan risus ornare. Faucibus hendrerit dolor. Eleifend vestibulum ac. Donec neque at. Nullam faucibus maecenas. Dolor pulvinar mauris. Dolor pretium pede interdum metus nullam. Litora porta iusto mauris adipiscing commodo. Metus suspendisse justo. Ut congue egestas. Vehicula amet suspendisse turpis id enim fusce est et. Posuere mauris lacus. Laoreet ac qui. Elit tincidunt etiam. Ut amet leo. Dictum egestas neque quis donec curabitur. Et nulla libero metus felis nulla. Duis quam in. Sodales arcu porta vitae amet suspendisse. Amet nisl elit. Rerum voluptates aenean vitae ultricies maecenas ipsum fusce libero ultricies nam consectetuer ornare lacinia mattis tincidunt wisi sed. Sed facilisis placerat ultricies quam nulla non massa magna a nam non. Quis ut placerat. Nulla placerat semper. Dignissim egestas etiam. Fermentum massa faucibus maecenas cras pulvinar. In feugiat feugiat in taciti odio. Consectetuer dapibus quis mauris amet tortor pede nunc ridiculus. Ante potenti lorem. Ornare id scelerisque porta sit felis nibh bibendum enim. At nam dolor ante est posuere. Vitae montes feugiat. Sit orci sapien non magna feugiat et lobortis vestibulum. Augue sed nullam. Quam turpis eros. Potenti dui commodi. Mattis semper fermentum. Fermentum mauris pellentesque dolorem diam litora faucibus in amet. Ut nulla aliquam nisl tortor hendrerit. In vel id. Odio suspendisse dis mauris velit vulputate. Suspendisse nulla ad. Praesent eu ut. Pellentesque tincidunt cras. Dui lorem urna velit velit duis. Sit aliquam amet. Amet at non. Fermentum volutpat nec rutrum varius justo. Suscipit mi eu. Metus et enim. Urna morbi ultrices ac tellus ligula. Commodo in vestibulum. Quisque quia nulla suspendisse eget eget. Pellentesque proin viverra lorem eveniet eget in velit aenean. Fringilla in nulla. Sem metus vestibulum. Dolor massa vestibulum. Id velit wisi lectus risus ut donec quisque lorem. Fermentum rhoncus odio massa sodales vel. At cursus vivamus lacus ac maecenas metus sem odio. Nunc netus arcu. Ridiculus hendrerit vel donec justo erat amet urna elit. Tempus vero ipsum. Mi luctus sodales. Rhoncus nullam aliquam bibendum wisi luctus sagittis diam vitae tempor eget dictum. Ultrices omnis habitasse. Et nonummy quis at purus nullam. Sem ipsum sit. Felis massa vestibulum. Justo vel quaerat. Orci elit vestibulum ligula amet mi. Tincidunt velit erat suscipit vestibulum mi. Lectus neque montes lorem vel vel sed rutrum vitae. Mollis ipsum vitae et non in sem justo et. Neque duis suspendisse elit eleifend hac egestas ante et ut adipiscing vestibulum. Nullam class viverra nam eget ultrices egestas nulla voluptatibus eros nullam dui. Rutrum mauris porta. Aliquam porta nulla. Rutrum at elit lacinia eget molestie lorem rhoncus nulla nec felis molestie velit est id interdum ac sit aliquam sed dui class donec est. Conubia justo mauris ipsum at pellentesque. Volutpat volutpat eleifend. Nunc et mi metus iaculis velit turpis tempus amet. Natoque in sem. Orci blandit pede ut orci duis. Mi donec nibh. Suspendisse a mauris. Donec libero praesent. Sodales aenean nec lobortis pharetra vel vel et sit. Aliquam lacus porta. Sodales vitae fusce nec id morbi nulla consequat dui malesuada ac sed gravida in vitae erat adipiscing magna posuere fringilla elementum. Amet leo sed pede neque nec. Sed suspendisse sem. Odio eget id. Quis gravida wisi felis magna mi orci in exercitationem facilisi aliquam sem. Est justo tellus integer cursus ante lorem vel posuere lectus sit sit tortor felis lacinia dis justo id torquent vulputate ut mauris ut mi. Massa est nec sit sem vel. Amet eleifend varius accumsan nec donec semper vel ut ut pulvinar dapibus. Felis mi vivamus praesent suspendisse tellus. Elit amet condimentum. Augue lobortis nulla risus facilisi vehicula. Habitasse nisl dui nec integer orci. Vel venenatis non ipsum bibendum sed in rhoncus purus. Maecenas ut adipiscing. Duis rhoncus platea lobortis amet magna. Justo proin pulvinar. Donec hendrerit ut. Vehicula nonummy tortor. Enim faucibus lectus. Blandit faucibus urna. Mus non egestas. Eu volutpat a. Expedita tempor eu pretium dictum odio. In lobortis sapien mauris ut metus. Cras integer netus. Litora cras sit nibh voluptas ipsum elit vivamus volutpat integer vel ut. Quam amet wisi orci lacus faucibus mattis lacinia ea sit tristique elementum duis eget suspendisse. Ut eget ad sollicitudin lectus leo. Est arcu quam. Gravida sollicitudin ipsum vitae et nunc libero sed vitae rutrum nibh erat. Ligula facilisi tincidunt libero cursus vivamus porttitor aliquam urna optio hac donec justo temporibus enim dolor nulla at. Sit at semper diam ullamcorper sed. Enim elit fringilla aliquam ultricies aliquam. Nec morbi neque ipsum adipiscing nonummy. Neque neque vel posuere ac eros. Metus mollis lorem facilisi non ac. Nunc posuere donec morbi ipsum parturient. Fusce et ullamcorper ut ultricies pellentesque aliquam eleifend et. Placerat ornare nec. Eget odio odio duis pretium leo in vel integer. Ut litora elit. Massa maecenas condimentum. Vel velit eu. Luctus augue laoreet. Vestibulum pede eget non at eget tellus euismod quam lorem accumsan ultricies. Rutrum turpis in. Lacus wisi hymenaeos. A volutpat turpis nullam euismod a. Nibh enim maiores. Nunc aenean quis sed eros in bibendum quis ornare non maecenas placerat justo feugiat nibh. Tempus magna tortor aenean cras elit sem at sociosqu diam nisl pellentesque. Rutrum ac non. Rutrum id facilisis. Lectus iaculis vitae ut diam dictum. Donec porttitor in. Cras hendrerit felis. Consequat vel et auctor phasellus id tincidunt vehicula scelerisque libero sem et. Neque pede tristique odio pulvinar tincidunt. Lobortis vel montes. Quis aenean amet. Et elementum varius enim penatibus sit amet amet praesent in urna eu aliquam suspendisse quis. Laboriosam nonummy urna eros integer vel. Ultrices magna platea. Iaculis eu aenean feugiat enim faucibus massa augue pulvinar sed sit nulla. Sem tincidunt viverra libero tristique in. Donec hendrerit sodales neque eu sed magna at vel rhoncus nonummy tellus. Morbi semper convallis orci risus nulla justo accumsan nibh pede ipsum quam massa con in risus ut vitae. Urna amet pulvinar. Non fusce diam eu vestibulum curabitur ipsum mollis in pellentesque vel rutrum hendrerit tellus lacinia. Libero maecenas orci. Venenatis rutrum dolor. A iaculis nullam. In id felis tortor lorem suspendisse ac sociis sapien orci mus in eget vitae integer. Fusce eleifend laoreet. Wisi purus odio. Imperdiet orci nibh ipsum pede quis pharetra id at molestie facilisis ornare. Laoreet ut pellentesque sit aptent libero. Mauris ut at. Inventore wisi ut duis luctus tortor lacus orci aliquam elementum donec dictum. Pretium pretium ac. Eu libero eget donec ipsum tellus. Sed eget tortor nibh eu purus. Etiam erat ultrices. Mauris turpis nisl vel nec wisi nisl quis vitae. Dictumst pulvinar posuere. Phasellus lacus lectus quis nunc tincidunt sodales vitae at. Justo nec nunc vero laoreet vel rutrum faucibus auctor felis eu elementum luctus eleifend donec enim porta eu. Porttitor ridiculus pellentesque ridiculus dis tellus dignissim metus sit. Elit fermentum felis risus massa iaculis. Lectus nisl elit. Ac euismod sapien a magna amet tortor condimentum dolor quis scelerisque eros. Metus amet hymenaeos. Amet vel dolore venenatis non nullam neque praesent vivamus nulla sit animi. Porttitor commodo ante. Platea tortor arcu. Tincidunt tincidunt accumsan. Nec consequat in. Id nibh sodales suscipit molestie ultricies nec ornare fermentum. Ligula per vel sit metus nonummy. Sed praesent gravida. Sem cursus tellus lacus libero turpis risus mauris fermentum. Id vivamus praesent. Sit dolor lectus eget mauris amet. Eleifend primis pellentesque. Fermentum nulla turpis vel et nam dignissim sem lectus. Vivamus erat nunc maecenas in nisl. Placerat nisl habitasse mattis condimentum vitae. Magna urna dignissim nec tincidunt pulvinar. Integer duis et. In metus vel vitae sodales luctus velit viverra congue. In ut natoque. Commodo vulputate vel. Vel condimentum erat vel imperdiet dolor. Pede turpis duis nibh ex condimentum. Ut ipsum diam nullam bibendum cras erat maecenas erat. Dolor non lacus. Nunc elit porttitor ut elit ut est scelerisque ornare dictum quis enim. Vitae semper lorem. Vel non sodales lacus massa ad magna sed iaculis aliquam occaecati lobortis pede massa et. Sit arcu sed ligula viverra gravida. Mauris tincidunt vehicula ullamcorper dapibus duis. Duis rutrum libero. Laoreet non suscipit. Vitae eget netus. Felis rutrum iaculis. Lacus leo risus. Nullam eros volutpat. Nunc donec magna. Sit pulvinar sollicitudin tristique erat ultricies ut fusce natoque proin habitant semper rutrum et nec vitae non metus. Eget in con donec placerat sed. A in elit. Mauris purus elit. Mollis faucibus lacinia ornare faucibus dolor vel dictum sed ante ante arcu. Tempor ut enim. Adipiscing et a. Eros wisi blandit. Lobortis imperdiet id penatibus erat fermentum at aliquam vestibulum. Ac dictum quam netus sodales habitant error amet tellus. Nulla tellus sapien. Phasellus etiam ac. Enim sed quam. Elit lobortis libero donec tempus vulputate. Luctus odio orci. Etiam nec suspendisse dolor justo justo dignissim mattis nunc. Vitae proin vestibulum facilisi lorem per. Urna suspendisse velit curabitur condimentum voluptate. Nullam nec volutpat iaculis ligula diam nec enim duis purus lacus tellus tellus eu malesuada scelerisque pede pulvinar maecenas libero egestas a neque eu. Lectus id at. Risus volutpat ut. Quam auctor vel sapien cras dictum. Erat arcu nec. Voluptate arcu leo dolor ante vel tempor vestibulum et. Nibh fermentum urna nascetur lobortis amet sodales donec et et suscipit sociosqu ullamco vel tortor enim odio sed. Eros turpis semper. Facilisis orci odio eros velit diam enim mi sit. Lorem dui suspendisse imperdiet vehicula maecenas neque hic sem habitasse nullam aliquam. Porta purus cras suscipit a justo nibh imperdiet quam. Fermentum a sem pede nec ac. Ac pretium sapiente. Odio dui dictum. Sollicitudin in felis. Dignissim arcu vel. Justo ac massa quisque egestas convallis cursus augue dictum. Pretium sed suspendisse elit error cursus. Donec turpis eleifend duis elit elit. Donec rutrum sed. Consequat curabitur amet. Ut ipsum quam risus urna pharetra. A risus ultrices. Id ac tortor elementum nunc fugiat quis eu eget vehicula consectetuer tempus erat vitae aenean ultrices aliquam lacus. Scelerisque phasellus scelerisque sit in lorem sed libero mauris odio at sit pellentesque integer est. Leo est vitae eu per nulla sit sapien cursus turpis ac sed. Vel in massa venenatis pretium cras. Nostrum eu fusce. Inceptos a molestie non nibh suspendisse aptent et ultricies non ac et ultrices accumsan mollis. Integer nunc in enim dis velit. Nulla tempore donec ultrices ipsum iusto. Vestibulum sed nibh tortor sollicitudin vehicula tristique habitasse vestibulum. Lacus quam vel vitae lacinia sed. Hac nec neque turpis volutpat integer. Laoreet ipsum et augue vehicula ut mi orci dictum. Pede malesuada consectetuer. Vitae ut cras penatibus dui eleifend dignissim adipiscing amet velit vitae consequat nunc sed est. Suspendisse fusce tellus. Libero turpis bibendum. Donec vitae inceptos placerat a vestibulum non a metus urna eget est viverra nam sed. Odio odio dapibus. Etiam faucibus magna duis vel eget urna integer ut. Felis urna etiam. Ac cupiditate ac dui a nunc. Molestias impedit non. Vitae nibh orci lobortis litora a nam mauris eros. Ante risus velit. Vivamus tellus praesent vestibulum iaculis lorem. Eget ratione lorem dictum turpis sit. Morbi arcu leo dictumst eget eget. Ridiculus turpis tristique dolor velit placerat. A aliquam vestibulum. Lacus mauris wisi. In montes dolor. Ornare ultrices condimentum. Parturient a vel. Ante quis molestiae porttitor quam sollicitudin aliquam magna risus. Vel vestibulum tortor. Auctor proident et dui sociosqu sapien eu ut vivamus. Dictumst ac nostrud egestas libero tellus. Vehicula nulla magna. Tempus vitae eu. Orci molestie sed elit velit tellus justo sed et sagittis lectus fringilla risus est sed nec libero consectetuer. Potenti sollicitudin donec vel maecenas tempor nunc euismod varius a sed at. Elit justo blandit feugiat lectus in. Pharetra etiam pede tempus porta et nam taciti aliquam amet in ornare volutpat eget eget nam non leo. Leo penatibus magna. Felis ultrices vestibulum in tempor faucibus. Faucibus est sed. Pulvinar aliquet lectus justo eu metus. Sodales vivamus nulla. Dolor augue gravida duis integer a. Lectus nibh mauris. Sed nisl suspendisse amet fermentum posuere elit ipsum tincidunt. Aliquet faucibus vestibulum maecenas odio gravida. Viverra feugiat in. Eget enim ipsum. Nonummy tincidunt ut tristique sodales eget erat lorem pretium odio ligula laoreet lorem felis tortor. Eget rutrum ligula etiam nulla nisl. Purus euismod egestas. Scelerisque ipsum libero curae mattis volutpat sed duis in amet ac tortor curabitur consequat ac arcu et ut. Duis vitae donec. Tincidunt pellentesque sollicitudin. Curabitur rhoncus velit. Praesent imperdiet nunc. Tortor amet fusce. Lobortis sed vestibulum. Consectetuer pede ante. Elit eu porttitor habitasse integer integer ultrices nam vitae. Nec cras nulla. Vitae nascetur nunc mattis semper augue. Aliquam lectus massa. Ullamcorper arcu maecenas scelerisque ac quis nisl arcu semper inventore sed commodo. Velit pellentesque lorem. Ad lacus cras a rutrum praesent arcu mi est. Felis risus congue. Facilisis eros sit vitae nibh etiam. Sodales in eu urna cras libero. Aenean dapibus nec tristique rutrum curabitur felis mattis congue. Et rutrum non luctus tellus lectus in neque vitae magna morbi nec. Ac aliquet velit est id etiam lorem id ligula non integer vehicula feugiat wisi et in amet nisl. Feugiat suspendisse fusce mattis nostra pulvinar. Lorem fusce enim. Eu pede lectus amet et ipsum at at ornare in ac a. Semper et vitae potenti amet lorem. Tellus vestibulum quam condimentum proin nibh. Neque et sit. Elit nisl viverra. Cras dignissim vivamus at et turpis. Ut risus non non commodo nibh. Nibh vestibulum nullam. Platea quis nulla cras diam feugiat. Tortor dui senectus adipiscing integer dapibus. Vehicula pellentesque vestibulum. Pellentesque sed neque massa odio accumsan vehicula morbi pharetra deserunt natoque fringilla amet euismod pellentesque sit vestibulum duis. Sed rhoncus volutpat. Augue dolor et morbi fringilla ac imperdiet elit vel faucibus ultricies pellentesque ullamcorper ornare vitae dui enim at. Mi sapien tellus etiam magna amet nibh mattis vitae ultricies bibendum elit. Dui augue phasellus. Consequat velit ac. Suspendisse nascetur ultricies. Gravida curabitur justo cupiditate ut ut vivamus mauris con sunt arcu hendrerit. Nonummy convallis eros. Id proin donec risus egestas molestie. Ullamcorper praesent felis. Posuere nec at laoreet tellus sapien ut condimentum in. Integer ullamcorper quam hymenaeos pulvinar felis. Felis quis vestibulum commodo et magna. Asperiores morbi lacus quam nonummy orci. Eu nec dolor adipiscing in nonummy. Bibendum metus volutpat. Sit arcu tempor eu non adipiscing eu netus reprehenderit. Dui magna ullamcorper. Fusce varius urna. Ut con aspernatur nullam vel suscipit. Magna quam ornare est auctor suspendisse nulla nisl ligula vulputate con condimentum. Tempor vehicula justo. Penatibus sapien placerat. Sed porta magna. Fermentum luctus ligula suspendisse nec interdum ac felis donec praesent urna eros varius gravida luctus vestibulum id nec fermentum nibh duis ac vestibulum vivamus. Faucibus praesent sem. Aliquam nibh convallis. Dignissim velit aliquet delectus gravida sed. Dictumst gravida sollicitudin faucibus vestibulum varius. Odio eget sed. Ornare lacus quisque pellentesque interdum aliquet. Nulla rhoncus sodales. Sit magna eu hendrerit integer sed pellentesque facilisis pellentesque diam amet viverra magna integer ultricies. In consequat rhoncus egestas a consectetuer proin morbi tempus sapien justo pede. A leo malesuada. Adipiscing nulla id. Vestibulum auctor id in dui morbi fermentum faucibus fringilla ac enim dignissim id integer erat. Scelerisque vitae nibh. Sed enim arcu. Maecenas purus integer. Lorem non purus. Leo turpis leo etiam integer felis. Mi pede urna enim nullam lectus facilisi suspendisse duis. Volutpat vestibulum proin ut nulla auctor. Tristique aliquet feugiat. Leo adipiscing enim varius massa nec. Euismod sed a. Praesent nunc semper. Rhoncus et orci vel pede dolor. Mi sed proin curabitur ac malesuada libero ut sed maecenas phasellus velit ut per a. Nulla ornare id pellentesque quis vel. Amet ac eu. Ullamcorper nibh libero consectetuer etiam porttitor. A non tincidunt. Aenean nam praesent sociis pulvinar cras massa elit elit nec non condimentum. Neque pellentesque fusce. Velit morbi nulla rutrum sint sodales in quam amet sit aptent etiam a dolor vitae. Aenean sed placerat. Lacus aliquet potenti. Vitae lectus ante erat ac enim a congue ac. Nullam nam est. Pede dolor vivamus phasellus sem id. Sem sit amet. Vitae tellus vel malesuada vitae purus. Eros aenean non. Tristique massa lobortis. Suspendisse sed hac. Non erat dictum. Vestibulum pede lacinia. Curabitur sem dis amet libero malesuada vel pellentesque orci eum pretium congue condimentum dui hymenaeos. Nibh tincidunt euismod aliquet praesent gravida tempor fringilla egestas. Ante ridiculus et posuere cras interdum. Amet non wisi urna dolor eget purus at quisque. Metus in risus. Adipiscing pede ultricies. Ultricies pellentesque enim. Sem vel posuere. Felis sem porttitor. Tristique etiam ipsum. Adipiscing sed aliquam. Etiam vel consectetuer. Nunc mollis dui. Torquent consequat curabitur. Magna mollis varius. Justo eget amet. Ultrices magna rhoncus. Netus et blandit. Fermentum at ultrices. Suspendisse id dignissim orci velit fusce. Morbi pede justo tellus dui et. Augue eu nunc auctor rutrum a ut ligula purus. Adipisci libero ridiculus. Sit etiam sed. Pulvinar ex ut. Adipiscing turpis nulla lorem suspendisse ut. Eu tellus nulla. Nam est fringilla erat arcu sed. Sit vel eget ratione vehicula imperdiet. Ipsum vitae pellentesque. A quis erat. Sit facilisi aliquam nulla ultricies habitant scelerisque porttitor amet. In libero congue. Aliquam eget metus vel gravida morbi orci quisque tellus tortor suspendisse ipsum. Pulvinar massa proin. Tortor tellus elit purus tristique facilisi. Ut suspendisse vivamus tincidunt mollis tincidunt nunc metus at ornare turpis velit. Integer erat ligula. Fringilla lorem in at sed nec. Ut cupidatat lacus felis lacus mauris feugiat amet inceptos. Dolor diam eu elit semper massa amet nulla integer. Fermentum morbi vel. Quis sit nec. Vestibulum vestibulum ligula nibh nulla neque porttitor diam arcu rutrum suspendisse vel. Ipsum phasellus aliquet. Sodales nunc vivamus tristique eu donec penatibus sapien nunc aenean etiam leo. Pede vel ut. Eros non suspendisse. Ullamcorper libero sed. Risus nunc enim pellentesque enim luctus. Turpis cursus diam ac pretium a. Nulla integer enim. Nisl amet sed. Nulla a sed suspendisse orci porttitor nulla sodales ipsum sagittis mattis dui donec justo magna. Suscipit amet id. Vitae per quam lacus lobortis ultricies nec a eros. Ullamcorper in risus purus ipsum eros. Tempus vestibulum libero. Nec scelerisque habitant ullamcorper libero quam felis mauris dui in ridiculus eros non maecenas nonummy. Ut dolorem tristique mattis purus nisl cras ante eleifend. Varius molestie posuere mollis velit wisi sed pellentesque blandit nullam risus turpis leo porta commodo cras aliquam venenatis. Arcu fringilla aenean dictum tempor tincidunt habitasse sed ligula. Auctor aliquet molestie fusce ultrices lacus proin vestibulum sed. Viverra lectus eu. Ut justo risus. Ullamcorper convallis orci bibendum nec nulla. Nisl ac ullamcorper ut erat porttitor magna gravida reprehenderit. Vestibulum amet aliquam in ut nibh congue diam sed. In mi velit. Dui ultricies amet. Faucibus imperdiet urna nulla nullam vestibulum. Sagittis id erat. Gravida tincidunt suscipit. Leo cras quisque augue nec nisl. Vestibulum eleifend lacus lectus mauris elit. Vel in consectetuer sollicitudin tincidunt rhoncus. Arcu vehicula nulla diam eleifend tincidunt. Hendrerit tempor dolor. Vel eu in. Taciti aliquam vel blandit diam at. Elit massa sapien et wisi leo. Luctus risus metus vehicula eros eros ullamcorper sed lacus. Mollis eu pellentesque scelerisque sit aenean. Vivamus eget accusamus a mauris non magnis eu senectus. Aliquam vestibulum laoreet. Aenean orci quam. Facilisi magna nunc nec diam ad cubilia velit mi mattis vitae tristique cras ante justo sed eget nulla a ullamcorper luctus. Elit mattis ligula. Id integer ipsum magna sed sed tortor vestibulum nunc."; + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/shared/src/mem_info_def.c b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/shared/src/mem_info_def.c new file mode 100644 index 0000000..26a5641 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/shared/src/mem_info_def.c @@ -0,0 +1,226 @@ +/******************************************************************************/ +/* Component Name Memory information definition */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/* Copyright(C) 2021-2023 Renesas Electronics Corporation. */ +/******************************************************************************/ + +/*******************************************************************************/ +/* Definition */ +/*******************************************************************************/ +#if defined(TARGET_DEVICE_S4X) || defined(TARGET_DEVICE_V4H) +#define ICUM_MEMORY_CONFIG_NUM (41) +#else /* if defined(TARGET_DEVICE_S4H) */ +#define ICUM_MEMORY_CONFIG_NUM (17) +#endif +/*********************************************************/ +/* User configurable area start */ +/*********************************************************/ +/* The user can change only the value of defined macro. */ +#if defined(TARGET_DEVICE_V4H) +#define ICUM_SERVICEQUEUE_1_ADDR (0x41C00000u) +#define ICUM_SERVICEQUEUE_1_SIZE (1152u) +#define ICUM_SHAREDMEMORY_1_ADDR (0x41C00480u) +#define ICUM_SHAREDMEMORY_1_SIZE (2097152u -1152u) +#define ICUM_SHAREDMEMORY_2_ADDR (0x41E00000u) +#define ICUM_SHAREDMEMORY_2_SIZE (2097152u) +#define ICUM_SHAREDMEMORY_3_ADDR (0xEB231000u) +#define ICUM_SHAREDMEMORY_3_SIZE (0xD000u) +#define ICUM_EXPORT_DATA_ADDR (0x41C20000u) +#define ICUM_EXPORT_DATA_SIZE (114688u) +#define ICUM_DATA_WORKAREA_ADDR (0xEB2E0000u) +#define ICUM_DATA_WORKAREA_SIZE (ICUM_EXPORT_DATA_SIZE) +#define ICUM_RTOS_IMAGE_ADDR (0xE2100000u) +#define ICUM_RTOS_IMAGE_SIZE (1048576u) +#define ICUM_CA_PROGRAM_1_ADDR (0x46400000u) +#define ICUM_CA_PROGRAM_1_SIZE (65536u) +#define ICUM_CA_PROGRAM_2_ADDR (0u) +#define ICUM_CA_PROGRAM_2_SIZE (0u) +#define ICUM_CA_PROGRAM_3_ADDR (0u) +#define ICUM_CA_PROGRAM_3_SIZE (0u) +#define ICUM_CA_PROGRAM_4_ADDR (0u) +#define ICUM_CA_PROGRAM_4_SIZE (0u) +#define ICUM_CA_PROGRAM_5_ADDR (0u) +#define ICUM_CA_PROGRAM_5_SIZE (0u) +#define ICUM_CA_PROGRAM_6_ADDR (0u) +#define ICUM_CA_PROGRAM_6_SIZE (0u) +#define ICUM_CA_PROGRAM_7_ADDR (0u) +#define ICUM_CA_PROGRAM_7_SIZE (0u) +#define ICUM_CA_PROGRAM_8_ADDR (0u) +#define ICUM_CA_PROGRAM_8_SIZE (0u) +#define ICUM_SECUREMOD (0x000001FFu) /*( 1:secure mode 0:non-secure mode bit0:unused,bit1:PE1,,,bit8:PE8 )*/ +#define ICUM_PE0_REGION_ID (0x00130000u) /* PE0 */ +#define ICUM_PE1_REGION_ID (0x00130000u) /* PE1 */ +#define ICUM_PE2_REGION_ID (0x00130000u) /* PE2 */ +#define ICUM_PE3_REGION_ID (0x00130000u) /* PE3 */ +#define ICUM_PE4_REGION_ID (0x00130000u) /* PE4 */ +#define ICUM_PE5_REGION_ID (0x00130000u) /* PE5 */ +#define ICUM_PE6_REGION_ID (0x00130000u) /* PE6 */ +#define ICUM_PE7_REGION_ID (0x00130000u) /* PE7 */ +#define ICUM_PE8_REGION_ID (0x00130000u) /* PE8 */ +#define ICUM_PES_REGION_ID (0x00130000u) /* PEs */ + /* b20 : SECMASK = 1:AUTHSEC is invalid 0:AUTHSEC is valid */ + /* b19-16 : IDMASK[3:0] = invalid bit of AUTHID */ + /* b4 : AUTHSEC = 1:secure mode 0:non-secure mode */ + /* b3-0 : AUTHID[3:0] = region ID */ +#elif defined(TARGET_DEVICE_S4X) +#define ICUM_SERVICEQUEUE_1_ADDR (0x41C00000u) +#define ICUM_SERVICEQUEUE_1_SIZE (1152u) +#define ICUM_SHAREDMEMORY_1_ADDR (0x41C00480u) +#define ICUM_SHAREDMEMORY_1_SIZE (2097152u -1152u) +#define ICUM_SHAREDMEMORY_2_ADDR (0x41E00000u) +#define ICUM_SHAREDMEMORY_2_SIZE (2097152u) +#define ICUM_SHAREDMEMORY_3_ADDR (0xE2100000u) +#define ICUM_SHAREDMEMORY_3_SIZE (1048576u) +#define ICUM_EXPORT_DATA_ADDR (0x41C20000u) +#define ICUM_EXPORT_DATA_SIZE (114688u) +#define ICUM_DATA_WORKAREA_ADDR (0xEB2E0000u) +#define ICUM_DATA_WORKAREA_SIZE (ICUM_EXPORT_DATA_SIZE) +#define ICUM_RTOS_IMAGE_ADDR (0xE2100000u) +#define ICUM_RTOS_IMAGE_SIZE (1048576u) +#define ICUM_CA_PROGRAM_1_ADDR (0x46400000u) +#define ICUM_CA_PROGRAM_1_SIZE (65536u) +#define ICUM_CA_PROGRAM_2_ADDR (0u) +#define ICUM_CA_PROGRAM_2_SIZE (0u) +#define ICUM_CA_PROGRAM_3_ADDR (0u) +#define ICUM_CA_PROGRAM_3_SIZE (0u) +#define ICUM_CA_PROGRAM_4_ADDR (0u) +#define ICUM_CA_PROGRAM_4_SIZE (0u) +#define ICUM_CA_PROGRAM_5_ADDR (0u) +#define ICUM_CA_PROGRAM_5_SIZE (0u) +#define ICUM_CA_PROGRAM_6_ADDR (0u) +#define ICUM_CA_PROGRAM_6_SIZE (0u) +#define ICUM_CA_PROGRAM_7_ADDR (0u) +#define ICUM_CA_PROGRAM_7_SIZE (0u) +#define ICUM_CA_PROGRAM_8_ADDR (0u) +#define ICUM_CA_PROGRAM_8_SIZE (0u) +#define ICUM_SECUREMOD (0x000001FFu) /*( 1:secure mode 0:non-secure mode bit0:unused,bit1:PE1,,,bit8:PE8 )*/ +#define ICUM_PE0_REGION_ID (0x00100000u) /* PE0 */ +#define ICUM_PE1_REGION_ID (0x00100000u) /* PE1 */ +#define ICUM_PE2_REGION_ID (0x00100000u) /* PE2 */ +#define ICUM_PE3_REGION_ID (0x00100000u) /* PE3 */ +#define ICUM_PE4_REGION_ID (0x00100000u) /* PE4 */ +#define ICUM_PE5_REGION_ID (0x00100000u) /* PE5 */ +#define ICUM_PE6_REGION_ID (0x00100000u) /* PE6 */ +#define ICUM_PE7_REGION_ID (0x00100000u) /* PE7 */ +#define ICUM_PE8_REGION_ID (0x00100000u) /* PE8 */ +#define ICUM_PES_REGION_ID (0x00100000u) /* PEs */ + /* b20 : SECMASK = 1:AUTHSEC is invalid 0:AUTHSEC is valid */ + /* b19-16 : IDMASK[3:0] = invalid bit of AUTHID */ + /* b4 : AUTHSEC = 1:secure mode 0:non-secure mode */ + /* b3-0 : AUTHID[3:0] = region ID */ +#elif defined(TARGET_DEVICE_S4H) +#define ICUM_SERVICEQUEUE_1_ADDR (0xFE020000u) +#define ICUM_SERVICEQUEUE_1_SIZE (256u) +#define ICUM_SHAREDMEMORY_1_ADDR (0xFE000000u) +#define ICUM_SHAREDMEMORY_1_SIZE (524288u) +#define ICUM_SHAREDMEMORY_2_ADDR (0xFE400000u) +#define ICUM_SHAREDMEMORY_2_SIZE (524288u) +#define ICUM_SHAREDMEMORY_3_ADDR (0xFE800000u) /* RRAM */ +#define ICUM_SHAREDMEMORY_3_SIZE (131072u) +#define ICUM_EXPORT_DATA_ADDR (0xFE464000u) +#define ICUM_EXPORT_DATA_SIZE (114688u) +#define ICUM_DATA_WORKAREA_ADDR (0xFF200000u) +#define ICUM_DATA_WORKAREA_SIZE (ICUM_EXPORT_DATA_SIZE) +#define ICUM_HOST_IMAGE_ADDR (0x00000000u) +#define ICUM_HOST_IMAGE_SIZE (5242880u) +#define ICUM_PE0_SPID (0x00000000u) /* PE0 */ +#define ICUM_PE1_SPID (0x00000001u) /* PE1 */ +#define ICUM_PES_SPID (0x001F0000u) /* PEs */ + /* b20-16 : IDMASK[4:0] = invalid bit of AUTHID */ + /* b4-0 : AUTHID[4:0] = SPID */ +#endif +/*********************************************************/ +/* User configurable area end */ +/*********************************************************/ + +/*******************************************************************************/ +/* Headers */ +/*******************************************************************************/ + +#include "renesas_types.h" +#include "shared.h" + +/*******************************************************************************/ +/* Global data */ +/*******************************************************************************/ +#if defined(TARGET_DEVICE_S4X) || defined(TARGET_DEVICE_V4H) +const uint32_t memory_information[ICUM_MEMORY_CONFIG_NUM] __attribute__((aligned(8), section(".constdata.CONFIG_DATA"))) = +{ + ICUM_SERVICEQUEUE_1_ADDR, + ICUM_SERVICEQUEUE_1_SIZE, + ICUM_SHAREDMEMORY_1_ADDR, + ICUM_SHAREDMEMORY_1_SIZE, + ICUM_SHAREDMEMORY_2_ADDR, + ICUM_SHAREDMEMORY_2_SIZE, + ICUM_SHAREDMEMORY_3_ADDR, + ICUM_SHAREDMEMORY_3_SIZE, + ICUM_EXPORT_DATA_ADDR, + ICUM_EXPORT_DATA_SIZE, + ICUM_DATA_WORKAREA_ADDR, + ICUM_DATA_WORKAREA_SIZE, + ICUM_RTOS_IMAGE_ADDR, + ICUM_RTOS_IMAGE_SIZE, + ICUM_CA_PROGRAM_1_ADDR, + ICUM_CA_PROGRAM_1_SIZE, + ICUM_CA_PROGRAM_2_ADDR, + ICUM_CA_PROGRAM_2_SIZE, + ICUM_CA_PROGRAM_3_ADDR, + ICUM_CA_PROGRAM_3_SIZE, + ICUM_CA_PROGRAM_4_ADDR, + ICUM_CA_PROGRAM_4_SIZE, + ICUM_CA_PROGRAM_5_ADDR, + ICUM_CA_PROGRAM_5_SIZE, + ICUM_CA_PROGRAM_6_ADDR, + ICUM_CA_PROGRAM_6_SIZE, + ICUM_CA_PROGRAM_7_ADDR, + ICUM_CA_PROGRAM_7_SIZE, + ICUM_CA_PROGRAM_8_ADDR, + ICUM_CA_PROGRAM_8_SIZE, + ICUM_SECUREMOD, + ICUM_PE0_REGION_ID, + ICUM_PE1_REGION_ID, + ICUM_PE2_REGION_ID, + ICUM_PE3_REGION_ID, + ICUM_PE4_REGION_ID, + ICUM_PE5_REGION_ID, + ICUM_PE6_REGION_ID, + ICUM_PE7_REGION_ID, + ICUM_PE8_REGION_ID, + ICUM_PES_REGION_ID +}; +#elif defined(TARGET_DEVICE_S4H) +const uint32_t memory_information[ICUM_MEMORY_CONFIG_NUM] __attribute__((aligned(8), section(".constdata.CONFIG_DATA"))) = +{ + ICUM_SERVICEQUEUE_1_ADDR, + ICUM_SERVICEQUEUE_1_SIZE, + ICUM_SHAREDMEMORY_1_ADDR, + ICUM_SHAREDMEMORY_1_SIZE, + ICUM_SHAREDMEMORY_2_ADDR, + ICUM_SHAREDMEMORY_2_SIZE, + ICUM_SHAREDMEMORY_3_ADDR, + ICUM_SHAREDMEMORY_3_SIZE, + ICUM_EXPORT_DATA_ADDR, + ICUM_EXPORT_DATA_SIZE, + ICUM_DATA_WORKAREA_ADDR, + ICUM_DATA_WORKAREA_SIZE, + ICUM_HOST_IMAGE_ADDR, + ICUM_HOST_IMAGE_SIZE, + ICUM_PE0_SPID, + ICUM_PE1_SPID, + ICUM_PES_SPID +}; +#endif + +/*******************************************************************************/ +/* Below shared variables are moved in memory via the linker directive file */ +/*******************************************************************************/ + +/*******************************************************************************/ +/* Communication buffer between host and ICU-M */ +/*******************************************************************************/ +uint8_t ISD_BUFFER[SIZE_OF_ISD_BUFFER] __attribute__((aligned(64), section(".bss.SHARED_TOP"))); +uint8_t LCS_BUFFER[SIZE_OF_LCS_BUFFER] __attribute__((aligned(64), section(".bss.SHARED_LCS"))); +uint8_t CMAC_BUFFER[SIZE_OF_CMAC_BUFFER] __attribute__((aligned(64), section(".bss.SHARED_CMAC"))); +uint8_t HASH_BUFFER[SIZE_OF_HASH_BUFFER] __attribute__((aligned(64), section(".bss.SHARED_HASH"))); diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/shared/src/shared.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/shared/src/shared.h new file mode 100644 index 0000000..5c71428 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/shared/src/shared.h @@ -0,0 +1,41 @@ +/******************************************************************************/ +/* Component Name Testing the ICU-M */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/* Copyright(C) 2021-2023 Renesas Electronics Corporation. */ +/******************************************************************************/ + +#if !defined(SHARED_H) +#define SHARED_H + +/********************************************************************************** +* Include +***********************************************************************************/ + +#include "renesas_types.h" + +/********************************************************************************** +* Define +***********************************************************************************/ +/** Area size of BIG_BUFFER */ +#define SIZE_OF_BIG_BUFFER (64*4*16) +#define SIZE_OF_BIG_BUF2 (1024) +/** Area size of ISD_BUFFER */ +#define SIZE_OF_ISD_BUFFER (512) +/** Area size of COM_BUFFER */ +#define SIZE_OF_COM_BUFFER (512) + +/********************************************************************************** +* Global external references +***********************************************************************************/ +#define SIZE_OF_LCS_BUFFER (4U) +#define SIZE_OF_CMAC_BUFFER (16U) +#define SIZE_OF_HASH_BUFFER (32U * 2U) + +extern uint8_t ISD_BUFFER[SIZE_OF_ISD_BUFFER]; +extern uint8_t LCS_BUFFER[SIZE_OF_LCS_BUFFER]; +extern uint8_t CMAC_BUFFER[SIZE_OF_CMAC_BUFFER]; +extern uint8_t HASH_BUFFER[SIZE_OF_HASH_BUFFER]; + +#endif /* SHARED_H */ diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/src/comm_drv/icum_d_comm_pe.c b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/src/comm_drv/icum_d_comm_pe.c new file mode 100644 index 0000000..7490f07 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/src/comm_drv/icum_d_comm_pe.c @@ -0,0 +1,1236 @@ +/******************************************************************************/ +/* Component Name ICU-M COMM(PE) Driver */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ + +/**************************************************************************************/ +/* Header files */ +/**************************************************************************************/ +#include "r_icumif_api.h" +#include "r_icumif_pub.h" +#include "user_icumif_api_pub.h" +#include "icum_d_comm_pe_pub.h" +#include "icum_d_comm_pe.h" + +/**************************************************************************************/ +/* Local variables */ +/**************************************************************************************/ +/* Initialization state information */ +static uint32_t icumif_initialized[TOTAL_PE_NUM] = {0U}; + +static ICUM_COMM_PE_INFO_t pe_info[TOTAL_PE_NUM] = +{ + { &ICUM_CMDREGICUM_ICU2PES0, &ICUM_CMDREGICUM_PE2ICUFS0, &ICUM_CMDREGICUM_PE2ICUIE0, /* PE0:Cortex R Core0 */ + &ICUM_CMDREGICUM_ICU2PEF0, &ICUM_CMDREGICUM_ICU2PEFC0, &ICUM_CMDREGICUM_ICU2PEIE0, &ICUM_CMDREGICUM_ICU2PEIS0, + &ICUM_CMDREGICUM_SEMAPE04, &ICUM_CMDREGICUM_SEMAPE0E, INTICUP_PESEL_TO_PE0, PE_SECURE_MODE_PE0 } + ,{ &ICUM_CMDREGICUM_ICU2PES0, &ICUM_CMDREGICUM_PE2ICUFS5, &ICUM_CMDREGICUM_PE2ICUIE5, /* PE1:Cortex-R Core1 */ + &ICUM_CMDREGICUM_ICU2PEF5, &ICUM_CMDREGICUM_ICU2PEFC5, &ICUM_CMDREGICUM_ICU2PEIE5, &ICUM_CMDREGICUM_ICU2PEIS5, + &ICUM_CMDREGICUM_SEMAPE05, &ICUM_CMDREGICUM_SEMAPE0F, INTICUP_PESEL_TO_PE5, PE_SECURE_MODE_PE5 } + ,{ &ICUM_CMDREGICUM_ICU2PES0, &ICUM_CMDREGICUM_PE2ICUFS6, &ICUM_CMDREGICUM_PE2ICUIE6, /* PE2:Cortex-R Core2 */ + &ICUM_CMDREGICUM_ICU2PEF6, &ICUM_CMDREGICUM_ICU2PEFC6, &ICUM_CMDREGICUM_ICU2PEIE6, &ICUM_CMDREGICUM_ICU2PEIS6, + &ICUM_CMDREGICUM_SEMAPE06, &ICUM_CMDREGICUM_SEMAPE10, INTICUP_PESEL_TO_PE6, PE_SECURE_MODE_PE6 } + ,{ &ICUM_CMDREGICUM_ICU2PES0, &ICUM_CMDREGICUM_PE2ICUFS1, &ICUM_CMDREGICUM_PE2ICUIE1, /* PE3:Cortex-A Core0 */ + &ICUM_CMDREGICUM_ICU2PEF1, &ICUM_CMDREGICUM_ICU2PEFC1, &ICUM_CMDREGICUM_ICU2PEIE1, &ICUM_CMDREGICUM_ICU2PEIS1, + &ICUM_CMDREGICUM_SEMAPE00, &ICUM_CMDREGICUM_SEMAPE0A, INTICUP_PESEL_TO_PE1, PE_SECURE_MODE_PE1 } + ,{ &ICUM_CMDREGICUM_ICU2PES0, &ICUM_CMDREGICUM_PE2ICUFS2, &ICUM_CMDREGICUM_PE2ICUIE2, /* PE4:Cortex-A Core1 */ + &ICUM_CMDREGICUM_ICU2PEF2, &ICUM_CMDREGICUM_ICU2PEFC2, &ICUM_CMDREGICUM_ICU2PEIE2, &ICUM_CMDREGICUM_ICU2PEIS2, + &ICUM_CMDREGICUM_SEMAPE01, &ICUM_CMDREGICUM_SEMAPE0B, INTICUP_PESEL_TO_PE2, PE_SECURE_MODE_PE2 } + ,{ &ICUM_CMDREGICUM_ICU2PES0, &ICUM_CMDREGICUM_PE2ICUFS3, &ICUM_CMDREGICUM_PE2ICUIE3, /* PE5:Cortex-A Core2 */ + &ICUM_CMDREGICUM_ICU2PEF3, &ICUM_CMDREGICUM_ICU2PEFC3, &ICUM_CMDREGICUM_ICU2PEIE3, &ICUM_CMDREGICUM_ICU2PEIS3, + &ICUM_CMDREGICUM_SEMAPE02, &ICUM_CMDREGICUM_SEMAPE0C, INTICUP_PESEL_TO_PE3, PE_SECURE_MODE_PE3 } + ,{ &ICUM_CMDREGICUM_ICU2PES0, &ICUM_CMDREGICUM_PE2ICUFS4, &ICUM_CMDREGICUM_PE2ICUIE4, /* PE6:Cortex-A Core3 */ + &ICUM_CMDREGICUM_ICU2PEF4, &ICUM_CMDREGICUM_ICU2PEFC4, &ICUM_CMDREGICUM_ICU2PEIE4, &ICUM_CMDREGICUM_ICU2PEIS4, + &ICUM_CMDREGICUM_SEMAPE03, &ICUM_CMDREGICUM_SEMAPE0D, INTICUP_PESEL_TO_PE4, PE_SECURE_MODE_PE4 } +}; +/* Callback registration at interrupt occurrence */ +static R_ICUMIF_CB_REGIST_t cb_regist_info[TOTAL_PE_NUM] = { {NULL} }; + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0003]:[ICUMFW_UD_S4_D_COMM_PE_0003] +* Function name: d_COMM_Enqueue_Request +* Description : Enqueue specified ISD to service request queue +* Arguments : r_icumif_isd_t *p_isd : Address value of ISD to be passed to ICUP +* : uint8_t *p_req_index : Index of the request queue entry +* Return Value : uint32_t Enqueue processing result +* ER_OK : Successful +* ER_D_COMM_QUE_FULL : Service request queue FULL +***************************************************************************************/ +static uint32_t d_COMM_Enqueue_Request(r_icumif_isd_t *p_isd, uint8_t *p_req_index) +{ + uint32_t ret_val = ER_OK; + volatile uint32_t *p_reg; + ptr_manip_t queptr; + uint32_t *p_queptr; + int32_t next_idx; + ptr_manip_t isdptr; + uintptr_t saved_psw; + uint32_t my_peid; + volatile uint32_t lul_dummy; + uint32_t vm_chk_result; + uint32_t secure_bit; + + /* 1. Get the PEID */ + my_peid = USER_ICUMIF_GetMyPEID(); + + /* 2. For interrupt control between PEs, */ + /* Interrupt disable check */ + USER_ICUMIF_GetLock(&saved_psw); + + /* 3. Lower 24 bits of ICUM_PE2ICUS register are acquire and upper 8 bits are */ + /* complemented to generate top address of service request queue */ + secure_bit = pe_info[my_peid].secure_mode_bit; + + if ((PEID_PE0 == my_peid) || (PE_SECURE_MODE_BITOFF != (MEM_INFO_ICUM_SECUREMOD & secure_bit))) + { + p_reg = (volatile uint32_t *)pe_info[my_peid].p_semape; + } + else + { + p_reg = (volatile uint32_t *)pe_info[my_peid].p_semape_ns; + } + + queptr.val = (*p_reg & QUE_ADDR_LOWER_24BITS) | (QUE_ADDR_UPPER_8BITS_VALUE & MEM_INFO_SERVICEQUE_1_ADDR); + p_queptr = (uint32_t *)queptr.p_ptr; + + /* Get the index of the next request queue entry */ + /* 4. Check entry after one of entry index of the service request queue */ + + ret_val = ER_D_COMM_QUE_FULL; + + /* 5. Invalidate of cache area ( service response queue area ) */ + USER_ICUMIF_InvalidateDCache((uint32_t)(queptr.val + SERV_REQUEST_QUEUE_AREA_SIZE), SERV_RESPONSE_QUEUE_AREA_SIZE); + + for (next_idx = 0; next_idx < (int32_t)REQUEST_QUEUE_LENGTH; next_idx++) + { + if (0U == (*(p_queptr + next_idx))) + { + /* 4-2. */ + /* Regist ISD to service request queue */ + isdptr.p_vlt_ptr = (volatile void *)p_isd; + *(p_queptr + next_idx) = (uint32_t)isdptr.val; + + /* Set service request / response queue transition state in */ + /* ISD indicated by parameter p_isd */ + p_isd->req_res_status = R_ICUMIF_REQRES_PE_REQ_ENQUE; + /* Dummy Read */ + lul_dummy = p_isd->req_res_status; + (void)lul_dummy; + /* Synchronize */ + USER_ICUMIF_Sync(); + + /* Check if the count of queue requests for each VM has reached the specified count */ + d_COMM_PE_VmRequestCountCheck(p_queptr, p_isd->vm_id, &vm_chk_result); + + /* prevent to become full the request queue. */ + if ((((int32_t)REQUEST_QUEUE_LENGTH - 1) == next_idx) || (VM_REQ_QUE_CNT_CHECK_REACHED == vm_chk_result)) + { + p_isd->req_nointerrupt = R_ICUMIF_REQRES_INTERRPUT; + /* Dummy Read */ + lul_dummy = p_isd->req_nointerrupt; + (void)lul_dummy; + /* Synchronize */ + USER_ICUMIF_Sync(); + } + else + { + /* Do nothing */ + } + + /* Clean and invalidate of cache area */ + /* ( ISD common parameters and service request queue area ) */ + USER_ICUMIF_FlushDCache((uint32_t)isdptr.val, (uint32_t)(sizeof(r_icumif_isd_t) - sizeof(p_isd->prm))); + USER_ICUMIF_FlushDCache((uint32_t)queptr.val, SERV_REQUEST_QUEUE_AREA_SIZE); + + *p_req_index = (uint8_t)next_idx; + ret_val = ER_OK; + break; + } + else + { + /* Do nothing */ + } + } + + /* 5. Interrupt enable check */ + USER_ICUMIF_ReleaseLock(saved_psw); + + /* 6. Return the enqueue processing result */ + return (ret_val); +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0004]:[ICUMFW_UD_S4_D_COMM_PE_0004] +* Function name: d_COMM_PE_GetSemaphore +* Description : Get the Semaphore register +* Arguments : (IN)icum_comm_target_pe_t target_pe +* uint8_t request +* Return Value : ER_OK +* PE_SEMAPHORE_ER_SYSTEM +* PE_SEMAPHORE_ER_TIMEOUT +***************************************************************************************/ +static uint32_t d_COMM_PE_GetSemaphore(uint8_t target_pe, uint8_t request) +{ + register volatile uint32_t *p_reg; + uint32_t uiAuth; + uint32_t uiIcusem; + uint32_t err; + uint32_t uiCount; + uint32_t secure_bit; + + /* Get the Semaphore register address */ + secure_bit = pe_info[target_pe].secure_mode_bit; + + if ((PEID_PE0 == (uint32_t)target_pe) || (PE_SECURE_MODE_BITOFF != (MEM_INFO_ICUM_SECUREMOD & secure_bit))) + { + p_reg = (volatile uint32_t *)pe_info[target_pe].p_semape; + } + else + { + p_reg = (volatile uint32_t *)pe_info[target_pe].p_semape_ns; + } + + err = PE_SEMAPHORE_ER_TIMEOUT; + uiCount = 0U; + + /* Wait for the Semaphore */ + do { + /* Try to get the Semaphore as step1 */ + uiIcusem = *p_reg; + uiAuth = uiIcusem & PE_SEMAPHORE_AUTH_MASK; + + if (PE_SEMAPHORE_AUTH_GET1ST == uiAuth) + { + /* Try to get the Semaphore as step2 */ + uiIcusem = *p_reg; + uiAuth = (uiIcusem & PE_SEMAPHORE_AUTH_MASK); + + if (PE_SEMAPHORE_AUTH_GET2ND != uiAuth) + { + /* Error case. retry to get the Semaphore */ + /* Do nothing */ + } + else + { + /* Got the Semaphore */ + err = ER_OK; + break; + } + } + else if (PE_SEMAPHORE_AUTH_GET2ND == uiAuth) + { + /* Got the Semaphore */ + err = ER_OK; + break; + } + else + { + /* Do nothing */ + } + + uiCount++; + } while (uiCount < PE_SEMAPHORE_WAIT); + + /* Set Request bit in the Semaphore register */ + if ((ER_OK == err) && (PE_SEMAPHORE_ON == (uint32_t)request)) + { + *p_reg |= PE_SEMAPHORE_REQ; + } + else + { + /* Do nothing */ + } + + USER_ICUMIF_Sync(); + + return err; +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0005]:[ICUMFW_UD_S4_D_COMM_PE_0005] +* Function name: d_COMM_PE_FreeSemaphore +* Description : Free the Semaphore register +* Arguments : (IN)icum_comm_target_pe_t target_pe +* uint8_t response +* Return Value : ER_OK +***************************************************************************************/ +static uint32_t d_COMM_PE_FreeSemaphore(uint8_t target_pe, uint8_t response) +{ + register volatile uint32_t *p_reg; + uint32_t uiAuth; + uint32_t secure_bit; + + /* Get the Semaphore register address */ + secure_bit = pe_info[target_pe].secure_mode_bit; + + if ((PEID_PE0 == (uint32_t)target_pe) || (PE_SECURE_MODE_BITOFF != (MEM_INFO_ICUM_SECUREMOD & secure_bit))) + { + p_reg = (volatile uint32_t *)pe_info[target_pe].p_semape; + } + else + { + p_reg = (volatile uint32_t *)pe_info[target_pe].p_semape_ns; + } + + uiAuth = (*p_reg & PE_SEMAPHORE_AUTH_MASK); + + /* Check the Semaphore register status */ + if (PE_SEMAPHORE_AUTH_GET2ND == uiAuth) + { + if (PE_SEMAPHORE_ON == (uint32_t)response) + { + /* Clear Request bit in the Semaphore register */ + *p_reg &= ~PE_SEMAPHORE_RES; + } + else + { + /* Do nothing */ + } + + /* Free the Semaphore */ + *p_reg &= ~PE_SEMAPHORE_AUTH_MASK; + } + else + { + /* Do nothing */ + } + + USER_ICUMIF_Sync(); + + return ER_OK; +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0020]:[ICUMFW_UD_S4_D_COMM_PE_0020] +* Function name: d_COMM_PE_VmRequestCountCheck +* Description : Check the count of queues per VM. +* Arguments : (IN) uint32_t *p_queptr +* (IN) r_icumif_vm_id_t vm_id +* (OUT)uint32_t *p_chk_result +* Return Value : N/A +***************************************************************************************/ +static void d_COMM_PE_VmRequestCountCheck(uint32_t *p_queptr, r_icumif_vm_id_t vm_id, uint32_t *p_chk_result) +{ + uint32_t vm_id_cnt; + uint32_t queue_idx; + ptr_manip_t isdptr; + r_icumif_isd_t *p_isd; + + vm_id_cnt = 0U; + queue_idx = 0U; + *p_chk_result = VM_REQ_QUE_CNT_CHECK_OK; + + /* Search for the number of ISDs with the same VM ID */ + for (queue_idx = 0U; REQUEST_QUEUE_LENGTH > queue_idx ;queue_idx++) + { + if (0U != (*(p_queptr + queue_idx))) + { + isdptr.val = *(p_queptr + queue_idx); + p_isd = (r_icumif_isd_t *)isdptr.p_ptr; + + /* Found the VM ID to be searched */ + if (p_isd->vm_id == vm_id) + { + vm_id_cnt++; + + if (VM_QUEUE_LENGTH <= vm_id_cnt) + { + /* Count of ISDs with the same VM ID has reached the upper limit */ + *p_chk_result = VM_REQ_QUE_CNT_CHECK_REACHED; + break; + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + } + else + { + break; + } + } + + return; +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0001]:[ICUMFW_UD_S4_D_COMM_PE_0001] +* Function name: D_COMM_PE_Init +* Description : Initialize the COMM(PE) driver +* Arguments : uint32_t *p_request_queue : Pointer to service request queue +* Return Value : uint32_t Driver initialization result +* ER_OK : Successful +* ER_D_COMM_PARAM_NOT_G_RAM : Parameter is not shared RAM area +* ER_D_COMM_QUE_ALREADY_INIT : Service queue already initialization +* ER_D_COMM_QUE_NOT_ACCESS : Can not get the Semaphore +* ER_D_COMM_MEMCHK_NG : Invalid memory info +***************************************************************************************/ +uint32_t D_COMM_PE_Init(uint32_t *p_request_queue) +{ + uint32_t ret_val = ER_OK; + volatile uint32_t *p_reg; + uint32_t count; + uint32_t bit_position; + ptr_manip_t wkptr; + uint32_t my_peid; + uint32_t semaphore; + uintptr_t saved_psw; + uint32_t secure_bit; + + /* 1. Memory information check ( Service queue size ) */ + /* In the case of check NG, the process is terminated */ + if ((TOTAL_SERVICE_QUEUE_AREA_SIZE * TOTAL_PE_NUM) > MEM_INFO_SERVICEQUE_1_SIZE) + { + ret_val = ER_D_COMM_MEMCHK_NG; + } + else + { + my_peid = USER_ICUMIF_GetMyPEID(); + bit_position = PE_QUE_INIT; + + /* 2. For interrupt control between PEs, */ + /* Interrupt disable initialization state information */ + USER_ICUMIF_GetLock(&saved_psw); + + /* 3. Check the "service queue initialization" state */ + /* of the initialization state information */ + if (INIT_UNPROCESSED == (0x00000001U & (icumif_initialized[my_peid] >> bit_position))) + { + /* 3-1. Get the Semaphore to clear err bit in the Semaphore register */ + semaphore = d_COMM_PE_GetSemaphore((uint8_t)my_peid, PE_SEMAPHORE_OFF); + + if(ER_OK == semaphore) + { + /* 3-1-1. Get top address of service queue area from memory information */ + wkptr.val = (uintptr_t)MEM_INFO_SERVICEQUE_1_ADDR; + wkptr.val = wkptr.val + (my_peid * TOTAL_SERVICE_QUEUE_AREA_SIZE); + p_request_queue = wkptr.p_uint32_ptr; + *(wkptr.p_vlt_ptr) = VALUE_FOR_RAM_AREA_CHECK; + if (VALUE_FOR_RAM_AREA_CHECK == *(wkptr.p_vlt_ptr)) + { + /* 3-1-1-1. */ + /* Set lower 24 bits of p_request_queue */ + /* to lower 24 bits of ICUM_PE2ICUS register */ + secure_bit = pe_info[my_peid].secure_mode_bit; + + if ((PEID_PE0 == my_peid) || (PE_SECURE_MODE_BITOFF != (MEM_INFO_ICUM_SECUREMOD & secure_bit))) + { + p_reg = (volatile uint32_t *)pe_info[my_peid].p_semape; + } + else + { + p_reg = (volatile uint32_t *)pe_info[my_peid].p_semape_ns; + } + + *p_reg = (*p_reg & ~QUE_ADDR_LOWER_24BITS) | + ((uint32_t)((uintptr_t)((volatile void *)p_request_queue)) & QUE_ADDR_LOWER_24BITS); + + /* Clear Error bit in the Semaphore register */ + *p_reg &= ~PE_SEMAPHORE_ERR; + + /* Clear queue area from address specified by p_request_queue */ + for (count = 0U; count < TOTAL_QUEUE_LENGTH; count++) + { + p_request_queue[count] = 0U; + } + + cb_regist_info[my_peid].p_func_addr = NULL; + + /* Clean and invalidate of cache area ( service queue area ) */ + USER_ICUMIF_FlushDCache((uint32_t)wkptr.val, TOTAL_SERVICE_QUEUE_AREA_SIZE); + + /* The "service queue initialization" state is set to "processed" */ + icumif_initialized[my_peid] |= (uint32_t)(INIT_PROCESSED << bit_position); + /* Synchronize Pipeline Macro */ + USER_ICUMIF_Sync(); + } + else + { + ret_val = ER_D_COMM_PARAM_NOT_G_RAM; + } + + /* Free the Semaphore */ + (void)d_COMM_PE_FreeSemaphore((uint8_t)my_peid, PE_SEMAPHORE_OFF); + } + else + { + ret_val = ER_D_COMM_QUE_NOT_ACCESS; + } + } + else + { + /* 3-2. */ + ret_val = ER_D_COMM_QUE_ALREADY_INIT; + } + + /* 4. Interrupt enable initialization state information */ + USER_ICUMIF_ReleaseLock(saved_psw); + } + + /* 5. Return the driver initialization result */ + return (ret_val); +} + + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0002]:[ICUMFW_UD_S4_D_COMM_PE_0002] +* Function name: D_COMM_TriggerInterruptToICUP +* Description : Issue an interrupt with channel number specified for ICUP +* Arguments : icum_comm_int_to_channel_t channel : Bit pattern indicating ch number +* r_icumif_isd_t *p_isd : Address value of ISD to ICUP +* Return Value : uint32_t Interrupt issue result +* ER_OK : Successful +* ER_PARAM : Parameter error +* ER_D_COMM_QUE_NOT_INIT : Service queue initialization not yet +* ER_D_COMM_QUE_FULL : Service request queue FULL +***************************************************************************************/ +uint32_t D_COMM_TriggerInterruptToICUP(icum_comm_int_to_channel_t channel, + r_icumif_isd_t *p_isd) +{ + uint32_t ret_val = ER_OK; + uint32_t call_func_ret; + volatile uint32_t *p_reg; + volatile uint32_t *p_single_reg; + uint32_t semaphore; + uint32_t bit_position; + uint32_t my_peid; + uint8_t index; + uintptr_t saved_psw; + + /* 1. Get necessary bit of register according to PEID */ + my_peid = USER_ICUMIF_GetMyPEID(); + p_reg = (volatile uint32_t *)pe_info[my_peid].p_pe2icufs; + p_single_reg = (volatile uint32_t *)&ICUM_CMDREGICUM_PE2ICUSFS; + + index = QUEUE_INDEX_MAX; + + /* 2. Each processing is executed according to the value of parameter channel */ + switch (channel) + { + case ICUM_COMM_ICH_TO_SERV_REQUEST: + /* 2-1. Check the "service queue initialization" state of */ + /* the initialization state information */ + bit_position = PE_QUE_INIT; + if (INIT_UNPROCESSED == (0x00000001U & (icumif_initialized[my_peid] >> bit_position))) + { + /* 2-1-1. Service queue initialization not yet */ + ret_val = ER_D_COMM_QUE_NOT_INIT; + } + else + { + /* For interrupt control between PEs, */ + /* Interrupt disable initialization state information */ + USER_ICUMIF_GetLock(&saved_psw); + + /* Get the Semaphore register to access the request queue*/ + semaphore = d_COMM_PE_GetSemaphore((uint8_t)my_peid, PE_SEMAPHORE_ON); + + if (ER_OK == semaphore) + { + /* 2-1-2. */ + /* Enqueue ISD specified by parameter p_isd to service request queue */ + call_func_ret = d_COMM_Enqueue_Request(p_isd, &index); + if (ER_OK == call_func_ret) + { + if (R_ICUMIF_REQRES_INTERRPUT == (uint32_t)p_isd->req_nointerrupt) + { + if ((QUEUE_INDEX_FIRST == (uint32_t)index) && + (SERVICE_01_AES_CMAC == p_isd->service_id) && + ((r_icumif_service_priority_t)R_ICUMIF_SERV_PRIORITY_HIGHEST == + (uint32_t)p_isd->service_priority)) + { + /* Set PEID status for INTPES interrupt */ + (void)D_COMM_SetPEStatusInfo(ICUM_COMM_INF_PE_ST_PEID, (uint8_t)my_peid); + /* Issue service execution request single interrupt */ + *p_single_reg = ICUM_COMM_ICH_TO_SINGLE_INTERRUPT; + } + else + { + /* 2-1-2-1. Issue service execution request interrupt */ + *p_reg = channel; + } + } + else + { + /* Do nothing */ + } + } + else + { + /* 2-1-2-2. Service request queue FULL */ + ret_val = call_func_ret; + } + /* Free the Semaphore */ + (void)d_COMM_PE_FreeSemaphore((uint8_t)my_peid, PE_SEMAPHORE_OFF); + } + else + { + ret_val = ER_D_COMM_QUE_NOT_ACCESS; + } + + /* Interrupt enable of service response queue */ + USER_ICUMIF_ReleaseLock(saved_psw); + } + break; + case ICUM_COMM_ICH_TO_CF_PRG_NOTIFY: + case ICUM_COMM_ICH_TO_DF_PRG_NOTIFY: + case ICUM_COMM_ICH_TO_CF_PRG_ERROR: + case ICUM_COMM_ICH_TO_DF_PRG_ERROR: + case ICUM_COMM_ICH_TO_OPERATION_END: + /* 2-2. Issue an interrupt with specified channel number */ + *p_reg = channel; + break; + default: + /* 2-3. Parameter error */ + ret_val = ER_PARAM; + break; + } + + /* 3. Return the interrupt issue result */ + return (ret_val); +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0006]:[ICUMFW_UD_S4_D_COMM_PE_0006] +* Function name: D_COMM_GetResponseISD +* Description : Dequeue ISD from head of the service response queue for its self PE +* Arguments : r_icumif_isd_t **p_isd : The store address of ISD +* Return Value : uint32_t ISD acquire result +* ER_OK : Successful +* ER_D_COMM_QUE_NOT_INIT : Service queue initialization not yet +* ER_D_COMM_NO_ISD : There is no ISD in service response queue +***************************************************************************************/ +uint32_t D_COMM_GetResponseISD(r_icumif_isd_t **p_isd) +{ + uint32_t ret_val = ER_OK; + volatile uint32_t *p_reg; + ptr_manip_t queptr; + uint32_t *p_queptr; + int32_t next_idx; + ptr_manip_t isdptr; + uint32_t my_peid; + uint32_t semaphore; + uintptr_t saved_psw; + volatile uint32_t lul_dummy; + uint32_t secure_bit; + + /* 2. Check the "service queue initialization" state of */ + /* the initialization state information */ + my_peid = USER_ICUMIF_GetMyPEID(); + if (INIT_UNPROCESSED == (0x00000001U & (icumif_initialized[my_peid] >> PE_QUE_INIT))) + { + /* 2-1. Service queue initialization not yet */ + ret_val = ER_D_COMM_QUE_NOT_INIT; + } + else + { + /* 2-2. */ + /* For interrupt control between PEs, */ + /* Interrupt disable of service response queue */ + USER_ICUMIF_GetLock(&saved_psw); + + /* Get the Semaphore register to access the respnse queue */ + semaphore = d_COMM_PE_GetSemaphore((uint8_t)my_peid, PE_SEMAPHORE_OFF); + + if (ER_OK == semaphore) + { + secure_bit = pe_info[my_peid].secure_mode_bit; + + if ((PEID_PE0 == my_peid) || (PE_SECURE_MODE_BITOFF != (MEM_INFO_ICUM_SECUREMOD & secure_bit))) + { + p_reg = (volatile uint32_t *)pe_info[my_peid].p_semape; + } + else + { + p_reg = (volatile uint32_t *)pe_info[my_peid].p_semape_ns; + } + + /* Lower 24 bits of Semaphore register are acquire and upper 8 bits */ + /* are complemented to generate top address of service request queue */ + queptr.val = (*p_reg & QUE_ADDR_LOWER_24BITS) | (QUE_ADDR_UPPER_8BITS_VALUE & MEM_INFO_SERVICEQUE_1_ADDR); + p_queptr = (uint32_t *)queptr.p_ptr; + + ret_val = ER_D_COMM_NO_ISD; + p_queptr += RESPONSE_QUEUE_OFST; + + /* Invalidate of cache area ( service response queue area ) */ + queptr.val += SERV_REQUEST_QUEUE_AREA_SIZE; + USER_ICUMIF_InvalidateDCache((uint32_t)queptr.val, SERV_RESPONSE_QUEUE_AREA_SIZE); + + for (next_idx = 0; next_idx < (int32_t)RESPONSE_QUEUE_LENGTH; next_idx++) + { + /* Check entry after one of entry index of the service request queue */ + if (0U != (*(p_queptr + next_idx))) + { + if (ret_val != ER_OK) + { + /* 2-2-2. */ + /* Acquire the address of ISD */ + isdptr.val = *(p_queptr + next_idx); + *p_isd = (r_icumif_isd_t *)isdptr.p_ptr; + /* Invalidate of cache area ( ISD common_parameters ) */ + USER_ICUMIF_InvalidateDCache((uint32_t)isdptr.val, (uint32_t)(sizeof(r_icumif_isd_t) - sizeof((*p_isd)->prm))); + /* free the entry in service response queue */ + *(p_queptr + next_idx) = 0U; + /* Set service request / response queue transition state in acquired ISD */ + (*p_isd)->req_res_status = R_ICUMIF_REQRES_PE_RES_DEQUE; + /* Dummy Read */ + lul_dummy = (*p_isd)->req_res_status; + (void)lul_dummy; + /* Synchronize */ + USER_ICUMIF_Sync(); + /* Clean and invalidate of cache area */ + /* ( ISD common_parameters and service request queue area ) */ + USER_ICUMIF_FlushDCache((uint32_t)isdptr.val, (uint32_t)(sizeof(r_icumif_isd_t) - sizeof((*p_isd)->prm))); + ret_val = ER_OK; + } + else + { + ret_val = ER_D_COMM_EXIST_ISD; + break; + } + } + else + { + /* Do nothing */ + } + } + + queptr.val -= SERV_REQUEST_QUEUE_AREA_SIZE; + USER_ICUMIF_FlushDCache((uint32_t)queptr.val, SERV_REQUEST_QUEUE_AREA_SIZE); + /* when the error bit of the semaphore register is be set */ + if (PE_SEMAPHORE_ERR == (*p_reg & PE_SEMAPHORE_ERR)) + { + /* error occurred */ + ret_val = ER_D_COMM_QUE_NOT_ACCESS; + *p_reg &= ~PE_SEMAPHORE_ERR; + } + else + { + /* Do nothing */ + } + + /* Free the Semaphore */ + (void)d_COMM_PE_FreeSemaphore((uint8_t)my_peid, PE_SEMAPHORE_OFF); + } + else + { + ret_val = ER_D_COMM_QUE_NOT_ACCESS; + } + + /* 2-3. Interrupt enable of service response queue */ + USER_ICUMIF_ReleaseLock(saved_psw); + } + + /* 3. Return the ISD acquire result */ + return (ret_val); +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0007]:[ICUMFW_UD_S4_D_COMM_PE_0007] +* Function name: D_COMM_GetICUStatusAddr +* Description : Acquire address value of status information of ICU-M Firmware +* Arguments : None +* Return Value : r_icumif_sts_t * Address value of ICU-M Firmware status information +***************************************************************************************/ +r_icumif_sts_t *D_COMM_GetICUStatusAddr(void) +{ + r_icumif_sts_t *p_reg; + ptr_manip_t regptr; + uint32_t my_peid; + + /* 1. Return the address value of ICUM_ICU2PES register as function return value */ + my_peid = USER_ICUMIF_GetMyPEID(); + regptr.p_vlt_ptr = pe_info[my_peid].p_icu2pes; + p_reg = (r_icumif_sts_t *)regptr.p_ptr; + + return (p_reg); +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0008]:[ICUMFW_UD_S4_D_COMM_PE_0008] +* Function name: D_COMM_SetPEStatusInfo +* Description : Set status information of the specified PE +* Arguments : icum_com_info_pe_status_t info : Status information of PE to set +* uint8_t set_value : Value of status information +* Return Value : uint32_t Status information setting result +* ER_OK : Successful +* ER_PARAM : Parameter error +***************************************************************************************/ +uint32_t D_COMM_SetPEStatusInfo(icum_com_info_pe_status_t info, uint8_t set_value) +{ + uint32_t ret_val = ER_OK; + volatile uint32_t *p_reg; + uint32_t bit_pattern; + uint32_t mask_pattern; + uintptr_t saved_psw; + volatile uint32_t lul_dummy; + + /* 2. For interrupt control between PEs, */ + /* Interrupt disable of PE state information */ + USER_ICUMIF_GetLock(&saved_psw); + + p_reg = (volatile uint32_t *)&ICUM_CMDREGICUM_PE2ICUS0; + + /* 3. Each processing is executed according to the value of parameter info */ + switch (info) + { + case ICUM_COMM_INF_PE_ST_FACIACCDIS: + /* 3-1. */ + /* Generate bit pattern so that value of least significant bit of */ + /* parameter set_value can be set as state of */ + /* inhibiting the data flash access state of PE status information */ + bit_pattern = ((INFO_PE_ST_FACIACCDIS_BIT & (uint32_t)set_value) << info) << INFO_PE_ST_POSITION; + + /* Set generate bit pattern to upper 8 bits of ICUM_PE2ICUS register */ + mask_pattern = ~(((uint32_t)(INFO_PE_ST_FACIACCDIS_BIT << info)) << INFO_PE_ST_POSITION); + *p_reg = (*p_reg & mask_pattern) | bit_pattern; + /* Dummy Read */ + lul_dummy = *p_reg; + (void)lul_dummy; + /* Synchronize */ + USER_ICUMIF_Sync(); + break; + case ICUM_COMM_INF_PE_ST_FLS_OPRN: + /* 3-2. */ + /* Generate bit pattern so that value of least significant bit of */ + /* parameter set_value can be set as state of */ + /* inhibiting the data flash access state of PE status information */ + bit_pattern = ((INFO_PE_ST_FLS_OPRN_BIT & (uint32_t)set_value) << info) << INFO_PE_ST_POSITION; + + /* Set generate bit pattern to upper 8 bits of ICUM_PE2ICUS register */ + mask_pattern = ~(((uint32_t)(INFO_PE_ST_FLS_OPRN_BIT << info)) << INFO_PE_ST_POSITION); + *p_reg = (*p_reg & mask_pattern) | bit_pattern; + /* Dummy Read */ + lul_dummy = *p_reg; + (void)lul_dummy; + /* Synchronize */ + USER_ICUMIF_Sync(); + break; + case ICUM_COMM_INF_PE_ST_PEID: + /* 3-3. */ + /* Generate bit pattern so that value of least significant bit of */ + /* parameter set_value can be set PEID information for INTPES interrupt */ + bit_pattern = (PEID_MASK & (uint32_t)set_value); + + /* Set generate bit pattern to upper 8 bits of ICUM_PE2ICUS register */ + mask_pattern = ~(PEID_MASK); + *p_reg = (*p_reg & mask_pattern) | bit_pattern; + /* Dummy Read */ + lul_dummy = *p_reg; + (void)lul_dummy; + /* Synchronize */ + USER_ICUMIF_Sync(); + break; + case ICUM_COMM_INF_PE_ST_FLS_DF_PRG: + /* 3-4. */ + /* Generate bit pattern so that value of least significant bit of */ + /* parameter set_value can be set as state of data flash prograimming */ + bit_pattern = ((INFO_PE_ST_FLS_DF_PRG_BIT & (uint32_t)set_value) << info) << INFO_PE_ST_POSITION; + + /* Set generate bit pattern to upper 8 bits of ICUM_PE2ICUS register */ + mask_pattern = ~(((uint32_t)(INFO_PE_ST_FLS_DF_PRG_BIT << info)) << INFO_PE_ST_POSITION); + *p_reg = (*p_reg & mask_pattern) | bit_pattern; + /* Dummy Read */ + lul_dummy = *p_reg; + (void)lul_dummy; + /* Synchronize */ + USER_ICUMIF_Sync(); + break; + case ICUM_COMM_INF_PE_ST_FLS_CF_PRG: + /* 3-5. */ + /* Generate bit pattern so that value of least significant bit of */ + /* parameter set_value can be set as state of code flash prograimming */ + bit_pattern = ((INFO_PE_ST_FLS_CF_PRG_BIT & (uint32_t)set_value) << info) << INFO_PE_ST_POSITION; + + /* Set generate bit pattern to upper 8 bits of ICUM_PE2ICUS register */ + mask_pattern = ~(((uint32_t)(INFO_PE_ST_FLS_CF_PRG_BIT << info)) << INFO_PE_ST_POSITION); + *p_reg = (*p_reg & mask_pattern) | bit_pattern; + /* Dummy Read */ + lul_dummy = *p_reg; + (void)lul_dummy; + /* Synchronize */ + USER_ICUMIF_Sync(); + break; + default: + /* 3-6. Parameter error */ + ret_val = ER_PARAM; + break; + } + + /* 4. Interrupt enable of PE state information */ + USER_ICUMIF_ReleaseLock(saved_psw); + + /* 5. Return Status information setting result */ + return (ret_val); +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0009]:[ICUMFW_UD_S4_D_COMM_PE_0009] +* Function name: D_COMM_SetInterruptEnable +* Description : Enable interrupt of ICUP --> PE (INTICUP) +* Arguments : None +* Return Value : None +***************************************************************************************/ +void D_COMM_SetInterruptEnable(void) +{ + volatile uint32_t *p_reg; + uint32_t pesel_value; + uint32_t ie_value; + uint32_t my_peid; + ICUM_COMM_PE_INFO_t *p_pe_info; + uintptr_t saved_psw; + + /* Get the PEID */ + my_peid = USER_ICUMIF_GetMyPEID(); + + /* 1. For interrupt control between PEs, */ + /* Interrupt disable of initialization state information */ + USER_ICUMIF_GetLock(&saved_psw); + + /* 2. Check the state of "ICU2PEI initialization" of self PE */ + /* in initialization state information */ + p_pe_info = &pe_info[my_peid]; + if (INIT_UNPROCESSED == (0x00000001U & (icumif_initialized[my_peid] >> PE_ICU2PEI_INIT))) + { + /* 2-1. */ + /* Set Interrupt destination selection */ + pesel_value = p_pe_info->inticup_pesel_to_pe; + p_reg = (volatile uint32_t *)p_pe_info->p_icu2peis; + *p_reg = pesel_value; + + /* Set Interrupt enable */ + p_reg = (volatile uint32_t *)p_pe_info->p_icu2peie; + ie_value = (1U << ICUM_COMM_ICH_FM_SYS_INTERRUPT) | (1U << ICUM_COMM_ICH_FM_SERV_RESPONSE); + *p_reg = ie_value; + + /* The "ICU2PEI initialization" state is set to "processed" */ + icumif_initialized[my_peid] |= (uint32_t)(INIT_PROCESSED << PE_ICU2PEI_INIT); + /* Synchronize Pipeline Macro */ + USER_ICUMIF_Sync(); + } + else + { + /* Do nothing */ + } + + /* 3. Interrupt enable of initialization state information */ + USER_ICUMIF_ReleaseLock(saved_psw); +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0010]:[ICUMFW_UD_S4_D_COMM_PE_0010] +* Function name: D_COMM_SetSystemCallBackFunc +* Description : Register the function to call back when receiving system interrupt +* Arguments : R_ICUMIF_CB_REGIST_t *p_regist_info : Pointer to registration info +* Return Value : uint32_t Callback registration result +* ER_OK : Successful +***************************************************************************************/ +uint32_t D_COMM_SetSystemCallBackFunc(R_ICUMIF_CB_REGIST_t *p_regist_info) +{ + uint32_t my_peid; + + /* Get the PEID */ + my_peid = USER_ICUMIF_GetMyPEID(); + + /* 1. Save CallBack Function Address */ + cb_regist_info[my_peid].p_func_addr = p_regist_info->p_func_addr; + + /* 2. Return the callback registration result */ + return (ER_OK); +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0012]:[ICUMFW_UD_S4_D_COMM_PE_0012] +* Function name: D_COMM_GetICUMemCheckErrInfo +* Description : Get the result of memory check error +* Arguments : uint8_t *p_error : Pointer to memory check info +* Return Value : uint32_t return the result of API +* ER_OK : Successful +* ER_PARAM : Parameter error +***************************************************************************************/ +uint32_t D_COMM_GetICUMemCheckErrInfo(uint8_t *p_error) +{ + volatile uint32_t *p_reg; + uint32_t my_peid; + uint32_t ret_val = ER_OK; + uintptr_t saved_psw; + uint32_t secure_bit; + + if(p_error != NULL) + { + /* Get the PEID */ + my_peid = USER_ICUMIF_GetMyPEID(); + + /* For interrupt control between PEs, */ + /* Interrupt disable initialization state information */ + USER_ICUMIF_GetLock(&saved_psw); + + (void)d_COMM_PE_GetSemaphore((uint8_t)my_peid, PE_SEMAPHORE_OFF); + + /* get semaphore register according to the PEID of the self PE */ + secure_bit = pe_info[my_peid].secure_mode_bit; + + if ((PEID_PE0 == my_peid) || (PE_SECURE_MODE_BITOFF != (MEM_INFO_ICUM_SECUREMOD & secure_bit))) + { + p_reg = (volatile uint32_t *)pe_info[my_peid].p_semape; + } + else + { + p_reg = (volatile uint32_t *)pe_info[my_peid].p_semape_ns; + } + + /* when the error bit of the semaphore register is be set*/ + if (PE_SEMAPHORE_ERR == (*p_reg & PE_SEMAPHORE_ERR)) + { + /* memory check error to be set in *p_error */ + *p_error = ICUM_COMM_MEMCHECK_ERROR; + *p_reg &= ~PE_SEMAPHORE_ERR; + } + else + { + /* memory check OK to be set in *p_error */ + *p_error = ICUM_COMM_MEMCHECK_OK; + } + + (void)d_COMM_PE_FreeSemaphore((uint8_t)my_peid, PE_SEMAPHORE_OFF); + + /* Interrupt enable of PE state information */ + USER_ICUMIF_ReleaseLock(saved_psw); + } + else + { + ret_val = ER_PARAM; + } + + return (ret_val); +} + +/**************************************************************************************/ +/* Interrupt handler functions */ +/**************************************************************************************/ + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0014]:[ICUMFW_UD_S4_D_COMM_PE_0014] +* Function name: d_COMM_Sys_Interrupt +* Description : Execute process of system interrupt from ICU-M +* Arguments : None +* Return Value : None +***************************************************************************************/ +static void d_COMM_Sys_Interrupt(void) +{ + uint32_t my_peid; + + /* Get the PEID */ + my_peid = USER_ICUMIF_GetMyPEID(); + + /* 1. Check registration state of function to call back */ + /* when system interrupt is received */ + if (NULL != cb_regist_info[my_peid].p_func_addr) + { + /* 1-1. Call registered callback function */ + (*cb_regist_info[my_peid].p_func_addr)(); + } + else + { + /* Do nothing */ + } + + return; +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0019]:[ICUMFW_UD_S4_D_COMM_PE_0019] +* Function name: D_COMM_IRQ_Handler +* Description : Execute interrupt process of ICUP --> PE (INTICUP) +* Arguments : None +* Return Value : None +***************************************************************************************/ +void D_COMM_IRQ_Handler(void) +{ + volatile uint32_t *p_reg; + uint32_t work_icu2pef; + uint32_t i; + uint32_t my_peid; + volatile uint32_t lul_dummy; + + /* 1. Get necessary bit of register according to PEID */ + my_peid = USER_ICUMIF_GetMyPEID(); + p_reg = (volatile uint32_t *)pe_info[my_peid].p_icu2pef; + work_icu2pef = *p_reg; + + p_reg = (volatile uint32_t *)pe_info[my_peid].p_icu2pefc; + + /* Clear interrupt factor of the non set PESELs */ + if (0x00000000U != (work_icu2pef & INTICUP_ICH_MASK)) + { + *p_reg = (work_icu2pef & INTICUP_ICH_MASK); + work_icu2pef &= ~INTICUP_ICH_MASK; + } + else + { + /* Do nothing */ + } + + /* 2. Check value of bits 0 to 2 of work_icu2pef bit by bit in order */ + /* to determine occurred interrupt */ + for (i = 0U; ((INTICUP_EACH_PE_BIT_WIDTH > i) && (0U != work_icu2pef)); i++) + { + /* 2-1. Check the value of least significant bit of work_icu2pef */ + if (0x00000001U == (0x00000001U & work_icu2pef)) + { + /* 2-1-1. */ + /* Clear interrupt factor */ + *p_reg = (1U << i); + lul_dummy = *p_reg; + (void)lul_dummy; + /* Synchronize */ + USER_ICUMIF_Sync(); + + switch (i) + { + case ICUM_COMM_ICH_FM_SYS_INTERRUPT: + /* 2-1-1-1. Execute system interrupt handling process */ + d_COMM_Sys_Interrupt(); + break; + case ICUM_COMM_ICH_FM_SERV_RESPONSE: + /* 2-1-1-2. Execute service execution response interrupt */ + /* handling process */ + (void)R_ICUMIF_ServiceResponse(); + break; + default: + /* 2-1-1-4. Do nothing */ + break; + } + } + else + { + /* Do nothing */ + } + + /* 2-2. Update work_icu2pef right shifted by 1 bit */ + work_icu2pef >>= 1U; + } + + return; +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_S4_D_COMM_PE_0028]:[ICUMFW_UD_S4_D_COMM_PE_0028] +* Function name: D_COMM_PE_CheckMemorySharedRAM +* Description : Check the memory +* Arguments :(IN)uint32_t start_addr: start address +* (IN)uint32_t size: check memory size +* Return Value : ER_OK +* ER_PARAM +* ER_D_COMM_MEMCHK_NG +* ER_D_COMM_ALIGN_NG +***************************************************************************************/ +uint32_t D_COMM_PE_CheckMemorySharedRAM(uint32_t start_addr, uint32_t size) +{ + int32_t ret_val = ER_OK; + uint32_t addr_valid = 0U; + + /* 1. Address alignment check */ + /* In the case of check NG, the process is terminated */ + if (0U != (start_addr & ALIGNMENT_64BYTE_CHECK_PATTERN)) + { + ret_val = ER_D_COMM_ALIGN_NG; + } + else + { + /* 2. Address range check */ + /* In the case of check NG, the process is terminated */ + if (size <= MEM_INFO_SERVICEQUE_1_SIZE) + { + if ((MEM_INFO_SERVICEQUE_1_ADDR <= start_addr) && + ((MEM_INFO_SERVICEQUE_1_ADDR + MEM_INFO_SERVICEQUE_1_SIZE - size) >= start_addr)) + { + addr_valid = 1U; + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + if ((0U == addr_valid) && (size <= MEM_INFO_SHAREDMEM_1_SIZE)) + { + if ((MEM_INFO_SHAREDMEM_1_ADDR <= start_addr) && + ((MEM_INFO_SHAREDMEM_1_ADDR + MEM_INFO_SHAREDMEM_1_SIZE - size) >= start_addr)) + { + addr_valid = 1U; + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + if ((0U == addr_valid) && (size <= MEM_INFO_SHAREDMEM_2_SIZE)) + { + if ((MEM_INFO_SHAREDMEM_2_ADDR <= start_addr) && + ((MEM_INFO_SHAREDMEM_2_ADDR + MEM_INFO_SHAREDMEM_2_SIZE - size) >= start_addr)) + { + addr_valid = 1U; + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + if ((0U == addr_valid) && (size <= MEM_INFO_SHAREDMEM_3_SIZE)) + { + if ((MEM_INFO_SHAREDMEM_3_ADDR <= start_addr) && + ((MEM_INFO_SHAREDMEM_3_ADDR + MEM_INFO_SHAREDMEM_3_SIZE - size) >= start_addr)) + { + addr_valid = 1U; + } + else + { + /* Do nothing */ + } + } + else + { + /* Do nothing */ + } + if (0U == addr_valid) + { + ret_val = ER_D_COMM_MEMCHK_NG; + } + else + { + /* Do nothing */ + } + } + + /* 3. Return the address check result */ + return (uint32_t)ret_val; +} diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/src/comm_drv/icum_d_comm_pe.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/src/comm_drv/icum_d_comm_pe.h new file mode 100644 index 0000000..7038a87 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/src/comm_drv/icum_d_comm_pe.h @@ -0,0 +1,277 @@ +/******************************************************************************/ +/* Component Name ICU-M COMM(PE) Driver */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ + +#if !defined(ICUM_D_COMM_PE_H) +#define ICUM_D_COMM_PE_H + +/**************************************************************************************/ +/* Global Pointer Variable */ +/**************************************************************************************/ + +/*====================================================================================*/ +/* Shared RAM area address */ +/*====================================================================================*/ +extern uint8_t __ghsbegin_start_gRAM_BANK_A[]; /* Start address ( Bank_A ) */ +extern uint8_t __ghsbegin_end_gRAM_BANK_A[]; /* End address + 1 ( Bank_A ) */ + +extern uint8_t __ghsbegin_start_gRAM_MEV[]; /* Start addr ( Exclusion ) */ + +/**************************************************************************************/ +/* Definition */ +/**************************************************************************************/ + +/* ICUMD Command Register */ +#define ICUM_CMDREGICUM_ICU2PES0 (*(volatile uint32_t*)0xE6610010U) +#define ICUM_CMDREGICUM_ICU2PES1 (*(volatile uint32_t*)0xE6610128U) +#define ICUM_CMDREGICUM_ICU2PES2 (*(volatile uint32_t*)0xE6610158U) +#define ICUM_CMDREGICUM_ICU2PES3 (*(volatile uint32_t*)0xE6610188U) +#define ICUM_CMDREGICUM_ICU2PES4 (*(volatile uint32_t*)0xE66101B8U) +#define ICUM_CMDREGICUM_ICU2PES5 (*(volatile uint32_t*)0xE66101E8U) +#define ICUM_CMDREGICUM_ICU2PES6 (*(volatile uint32_t*)0xE6610218U) +#define ICUM_CMDREGICUM_ICU2PES7 (*(volatile uint32_t*)0xE6610248U) +#define ICUM_CMDREGICUM_ICU2PES8 (*(volatile uint32_t*)0xE6610278U) +#define ICUM_CMDREGICUM_PE2ICUS0 (*(volatile uint32_t*)0xE6610014U) +#define ICUM_CMDREGICUM_PE2ICUS1 (*(volatile uint32_t*)0xE661012CU) +#define ICUM_CMDREGICUM_PE2ICUS2 (*(volatile uint32_t*)0xE661015CU) +#define ICUM_CMDREGICUM_PE2ICUS3 (*(volatile uint32_t*)0xE661018CU) +#define ICUM_CMDREGICUM_PE2ICUS4 (*(volatile uint32_t*)0xE66101BCU) +#define ICUM_CMDREGICUM_PE2ICUS5 (*(volatile uint32_t*)0xE66101ECU) +#define ICUM_CMDREGICUM_PE2ICUS6 (*(volatile uint32_t*)0xE661021CU) +#define ICUM_CMDREGICUM_PE2ICUS7 (*(volatile uint32_t*)0xE661024CU) +#define ICUM_CMDREGICUM_PE2ICUS8 (*(volatile uint32_t*)0xE661027CU) +#define ICUM_CMDREGICUM_PE2ICUFS0 (*(volatile uint32_t*)0xE6610044U) +#define ICUM_CMDREGICUM_PE2ICUFS1 (*(volatile uint32_t*)0xE6610104U) +#define ICUM_CMDREGICUM_PE2ICUFS2 (*(volatile uint32_t*)0xE6610134U) +#define ICUM_CMDREGICUM_PE2ICUFS3 (*(volatile uint32_t*)0xE6610164U) +#define ICUM_CMDREGICUM_PE2ICUFS4 (*(volatile uint32_t*)0xE6610194U) +#define ICUM_CMDREGICUM_PE2ICUFS5 (*(volatile uint32_t*)0xE66101C4U) +#define ICUM_CMDREGICUM_PE2ICUFS6 (*(volatile uint32_t*)0xE66101F4U) +#define ICUM_CMDREGICUM_PE2ICUFS7 (*(volatile uint32_t*)0xE6610224U) +#define ICUM_CMDREGICUM_PE2ICUFS8 (*(volatile uint32_t*)0xE6610254U) +#define ICUM_CMDREGICUM_PE2ICUIE0 (*(volatile uint32_t*)0xE661004CU) +#define ICUM_CMDREGICUM_PE2ICUIE1 (*(volatile uint32_t*)0xE661010CU) +#define ICUM_CMDREGICUM_PE2ICUIE2 (*(volatile uint32_t*)0xE661013CU) +#define ICUM_CMDREGICUM_PE2ICUIE3 (*(volatile uint32_t*)0xE661016CU) +#define ICUM_CMDREGICUM_PE2ICUIE4 (*(volatile uint32_t*)0xE661019CU) +#define ICUM_CMDREGICUM_PE2ICUIE5 (*(volatile uint32_t*)0xE66101CCU) +#define ICUM_CMDREGICUM_PE2ICUIE6 (*(volatile uint32_t*)0xE66101FCU) +#define ICUM_CMDREGICUM_PE2ICUIE7 (*(volatile uint32_t*)0xE661022CU) +#define ICUM_CMDREGICUM_PE2ICUIE8 (*(volatile uint32_t*)0xE661025CU) +#define ICUM_CMDREGICUM_ICU2PEF0 (*(volatile uint32_t*)0xE6610050U) +#define ICUM_CMDREGICUM_ICU2PEF1 (*(volatile uint32_t*)0xE6610110U) +#define ICUM_CMDREGICUM_ICU2PEF2 (*(volatile uint32_t*)0xE6610140U) +#define ICUM_CMDREGICUM_ICU2PEF3 (*(volatile uint32_t*)0xE6610170U) +#define ICUM_CMDREGICUM_ICU2PEF4 (*(volatile uint32_t*)0xE66101A0U) +#define ICUM_CMDREGICUM_ICU2PEF5 (*(volatile uint32_t*)0xE66101D0U) +#define ICUM_CMDREGICUM_ICU2PEF6 (*(volatile uint32_t*)0xE6610200U) +#define ICUM_CMDREGICUM_ICU2PEF7 (*(volatile uint32_t*)0xE6610230U) +#define ICUM_CMDREGICUM_ICU2PEF8 (*(volatile uint32_t*)0xE6610260U) +#define ICUM_CMDREGICUM_ICU2PEFC0 (*(volatile uint32_t*)0xE6610058U) +#define ICUM_CMDREGICUM_ICU2PEFC1 (*(volatile uint32_t*)0xE6610118U) +#define ICUM_CMDREGICUM_ICU2PEFC2 (*(volatile uint32_t*)0xE6610148U) +#define ICUM_CMDREGICUM_ICU2PEFC3 (*(volatile uint32_t*)0xE6610178U) +#define ICUM_CMDREGICUM_ICU2PEFC4 (*(volatile uint32_t*)0xE66101A8U) +#define ICUM_CMDREGICUM_ICU2PEFC5 (*(volatile uint32_t*)0xE66101D8U) +#define ICUM_CMDREGICUM_ICU2PEFC6 (*(volatile uint32_t*)0xE6610208U) +#define ICUM_CMDREGICUM_ICU2PEFC7 (*(volatile uint32_t*)0xE6610238U) +#define ICUM_CMDREGICUM_ICU2PEFC8 (*(volatile uint32_t*)0xE6610268U) +#define ICUM_CMDREGICUM_ICU2PEIE0 (*(volatile uint32_t*)0xE661005CU) +#define ICUM_CMDREGICUM_ICU2PEIE1 (*(volatile uint32_t*)0xE661011CU) +#define ICUM_CMDREGICUM_ICU2PEIE2 (*(volatile uint32_t*)0xE661014CU) +#define ICUM_CMDREGICUM_ICU2PEIE3 (*(volatile uint32_t*)0xE661017CU) +#define ICUM_CMDREGICUM_ICU2PEIE4 (*(volatile uint32_t*)0xE66101ACU) +#define ICUM_CMDREGICUM_ICU2PEIE5 (*(volatile uint32_t*)0xE66101DCU) +#define ICUM_CMDREGICUM_ICU2PEIE6 (*(volatile uint32_t*)0xE661020CU) +#define ICUM_CMDREGICUM_ICU2PEIE7 (*(volatile uint32_t*)0xE661023CU) +#define ICUM_CMDREGICUM_ICU2PEIE8 (*(volatile uint32_t*)0xE661026CU) +#define ICUM_CMDREGICUM_ICU2PEIS0 (*(volatile uint32_t*)0xE6610060U) +#define ICUM_CMDREGICUM_ICU2PEIS1 (*(volatile uint32_t*)0xE6610120U) +#define ICUM_CMDREGICUM_ICU2PEIS2 (*(volatile uint32_t*)0xE6610150U) +#define ICUM_CMDREGICUM_ICU2PEIS3 (*(volatile uint32_t*)0xE6610180U) +#define ICUM_CMDREGICUM_ICU2PEIS4 (*(volatile uint32_t*)0xE66101B0U) +#define ICUM_CMDREGICUM_ICU2PEIS5 (*(volatile uint32_t*)0xE66101E0U) +#define ICUM_CMDREGICUM_ICU2PEIS6 (*(volatile uint32_t*)0xE6610210U) +#define ICUM_CMDREGICUM_ICU2PEIS7 (*(volatile uint32_t*)0xE6610240U) +#define ICUM_CMDREGICUM_ICU2PEIS8 (*(volatile uint32_t*)0xE6610270U) +#define ICUM_CMDREGICUM_PE2ICUSFS (*(volatile uint32_t*)0xE6610074U) +#define ICUM_CMDREGICUM_SEMAPE00 (*(volatile uint32_t*)0xE66100A0U) +#define ICUM_CMDREGICUM_SEMAPE01 (*(volatile uint32_t*)0xE66100A4U) +#define ICUM_CMDREGICUM_SEMAPE02 (*(volatile uint32_t*)0xE66100A8U) +#define ICUM_CMDREGICUM_SEMAPE03 (*(volatile uint32_t*)0xE66100ACU) +#define ICUM_CMDREGICUM_SEMAPE04 (*(volatile uint32_t*)0xE66100B0U) +#define ICUM_CMDREGICUM_SEMAPE05 (*(volatile uint32_t*)0xE66100B4U) +#define ICUM_CMDREGICUM_SEMAPE06 (*(volatile uint32_t*)0xE66100B8U) +#define ICUM_CMDREGICUM_SEMAPE07 (*(volatile uint32_t*)0xE66100BCU) +#define ICUM_CMDREGICUM_SEMAPE08 (*(volatile uint32_t*)0xE66100C0U) +#define ICUM_CMDREGICUM_SEMAPE0A (*(volatile uint32_t*)0xE66100C8U) +#define ICUM_CMDREGICUM_SEMAPE0B (*(volatile uint32_t*)0xE66100CCU) +#define ICUM_CMDREGICUM_SEMAPE0C (*(volatile uint32_t*)0xE66100D0U) +#define ICUM_CMDREGICUM_SEMAPE0D (*(volatile uint32_t*)0xE66100D4U) +#define ICUM_CMDREGICUM_SEMAPE0E (*(volatile uint32_t*)0xE66100D8U) +#define ICUM_CMDREGICUM_SEMAPE0F (*(volatile uint32_t*)0xE66100DCU) +#define ICUM_CMDREGICUM_SEMAPE10 (*(volatile uint32_t*)0xE66100E0U) +#define ICUM_CMDREGICUM_SEMAPE11 (*(volatile uint32_t*)0xE66100E4U) +#define ICUM_CMDREGICUM_SEMAPE12 (*(volatile uint32_t*)0xE66100E8U) + +/* Bit position of initialization process execution state ( INIT_PROCESS_TYPE ) */ +#define PE_QUE_INIT (0U) /* PE queue init */ +#define PE_INTC_INIT (4U) /* PE INTC initialization */ +#define PE_ICU2PEI_INIT (8U) /* PE ICU2PEI initialization */ + +/* Execution state of initialization process ( INIT_PROCESS_STATUS ) */ +#define INIT_UNPROCESSED (0U) +#define INIT_PROCESSED (1U) + +/* Mask pattern of service queue address ( QUE_ADDR_MASK_PATTERN ) */ +#define QUE_ADDR_LOWER_24BITS (0x00FFFFFFU) +#define QUE_ADDR_UPPER_8BITS_VALUE (0xFF000000U) + +/* Destination PE set value of INTICUP interrupt ( INTICUP_PESEL_PATTERN ) */ +#define INTICUP_PESEL_TO_PE0 (0x00000000U) /* Set value (bit 3-0) */ +#define INTICUP_PESEL_TO_PE1 (0x00000001U) /* Set value (bit 3-0) */ +#define INTICUP_PESEL_TO_PE2 (0x00000002U) /* Set value (bit 3-0) */ +#define INTICUP_PESEL_TO_PE3 (0x00000003U) /* Set value (bit 3-0) */ +#define INTICUP_PESEL_TO_PE4 (0x00000004U) /* Set value (bit 3-0) */ +#define INTICUP_PESEL_TO_PE5 (0x00000006U) /* Set value (bit 3-0) */ +#define INTICUP_PESEL_TO_PE6 (0x00000007U) /* Set value (bit 3-0) */ +#define INTICUP_PESEL_TO_PE7 (0x00000008U) /* Set value (bit 3-0) */ +#define INTICUP_PESEL_TO_PE8 (0x00000009U) /* Set value (bit 3-0) */ +/* Mask pattern for non set PESELs */ +#define INTICUP_ICH_MASK (0xFFFFFFF8U) + +/* Bit position of INTICUP interrupt each PE ( INTICUP_BIT_POSITION ) */ +#define INTICUP_EACH_PE_BIT_WIDTH (3U) + +/* PE Identifier value ( PEID_VALUE ) */ +#define PEID_PE0 (0U) +#define PEID_PE1 (1U) +#define PEID_PE2 (2U) +#define PEID_PE3 (3U) + +#define PEID_MASK (0x000000FU) +/* Bit position of PE status information ( PE2ICUS_BIT_POSITION ) */ +#define INFO_PE_ST_POSITION (24U) + +/* Bit pattern of PE status information ( INFO_PE_ST_BIT_PATTERN ) */ +#define INFO_PE_ST_FACIACCDIS_BIT (0x00000001U) +#define INFO_PE_ST_FLS_OPRN_BIT (0x00000001U) +#define INFO_PE_ST_FLS_DF_PRG_BIT (0x00000001U) +#define INFO_PE_ST_FLS_CF_PRG_BIT (0x00000001U) + +/* Section address information ( SECTION_ADDRESS_INFO ) */ +#define ADDR_START_SHARED_RAM ((uint32_t *)((void *)__ghsbegin_start_gRAM_BANK_A)) +#define ADDR_END_PLUS1_SHARED_RAM ((uint32_t *)((void *)__ghsbegin_end_gRAM_BANK_A)) + +#define PE_SEMAPHORE_RES (0x01000000U) +#define PE_SEMAPHORE_REQ (0x02000000U) +#define PE_SEMAPHORE_ERR (0x20000000U) +#define PE_SEMAPHORE_AUTH_MASK (0xC0000000U) +#define PE_SEMAPHORE_AUTH_FREE (0x00000000U) + +#define PE_SEMAPHORE_AUTH_GET1ST (0x00000000U) +#define PE_SEMAPHORE_AUTH_GET2ND (0x80000000U) +#define PE_SEMAPHORE_WAIT (0x0002645CU) + +#define PE_SEMAPHORE_ER_SYSTEM (0x00000001U) +#define PE_SEMAPHORE_ER_TIMEOUT (0x00000002U) + +#define PE_SEMAPHORE_ON (0x01U) +#define PE_SEMAPHORE_OFF (0x00U) + +#define PE_SECURE_MODE_PE0 (0x00000001U) +#define PE_SECURE_MODE_PE5 (0x00000002U) +#define PE_SECURE_MODE_PE6 (0x00000004U) +#define PE_SECURE_MODE_PE1 (0x00000008U) +#define PE_SECURE_MODE_PE2 (0x00000010U) +#define PE_SECURE_MODE_PE3 (0x00000020U) +#define PE_SECURE_MODE_PE4 (0x00000040U) +#define PE_SECURE_MODE_PE7 (0x00000080U) +#define PE_SECURE_MODE_PE8 (0x00000100U) +#define PE_SECURE_MODE_BITOFF (0U) + +#define QUEUE_INDEX_FIRST (0x00U) +#define QUEUE_INDEX_MAX (0xFFU) + +/* Size of service queue area ( SERVICE_QUEUE_AREA_SIZE ) */ +#define SERV_REQUEST_QUEUE_AREA_SIZE (64U) +#define SERV_RESPONSE_QUEUE_AREA_SIZE (64U) + +#define TOTAL_SERVICE_QUEUE_AREA_SIZE (SERV_REQUEST_QUEUE_AREA_SIZE + SERV_RESPONSE_QUEUE_AREA_SIZE) + +/* Value for checking number of queue requests per VM ( VM_REQ_QUE_CNT_CHECK ) */ +#define VM_REQ_QUE_CNT_CHECK_OK (0U) +#define VM_REQ_QUE_CNT_CHECK_REACHED (1U) + +/* Value for RAM area check ( CHECK_VALUE ) */ +#define VALUE_FOR_RAM_AREA_CHECK (0xA5A5A5A5U) + +/*====================================================================================*/ +/* Data pattern of alignment check */ +/*====================================================================================*/ +#define ALIGNMENT_64BYTE_CHECK_PATTERN (0x0000003fU) /* 64 byte alignment */ +#define ALIGNMENT_4BYTE_CHECK_PATTERN (0x00000003U) /* 4 byte alignment */ +#define ALIGNMENT_2BYTE_CHECK_PATTERN (0x00000001U) /* 2 byte alignment */ + +/**************************************************************************************/ +/* Type definition */ +/**************************************************************************************/ +/* None */ + +/**************************************************************************************/ +/* Enumeration */ +/**************************************************************************************/ +/* None */ + +/**************************************************************************************/ +/* Structure Definition */ +/**************************************************************************************/ + +typedef struct ICUM_COMM_PE_INFO +{ + volatile uint32_t* p_icu2pes; + volatile uint32_t* p_pe2icufs; + volatile uint32_t* p_pe2icuie; + volatile uint32_t* p_icu2pef; + volatile uint32_t* p_icu2pefc; + volatile uint32_t* p_icu2peie; + volatile uint32_t* p_icu2peis; + volatile uint32_t* p_semape; + volatile uint32_t* p_semape_ns; + uint32_t inticup_pesel_to_pe; + uint32_t secure_mode_bit; +} ICUM_COMM_PE_INFO_t; + +/*====================================================================================*/ +/* Union for pointer manipulation */ +/*====================================================================================*/ +typedef union ptr_manip +{ + void *p_ptr; + uint32_t *p_uint32_ptr; + volatile uint32_t *p_vlt_ptr; + uintptr_t val; +} ptr_manip_t; + +/***************************************************************************************/ +/* Prototypes */ +/***************************************************************************************/ +static uint32_t d_COMM_PE_GetSemaphore(uint8_t target_pe, uint8_t request); +static uint32_t d_COMM_PE_FreeSemaphore(uint8_t target_pe, uint8_t response); +static void d_COMM_PE_VmRequestCountCheck(uint32_t *p_queptr, r_icumif_vm_id_t vm_id, uint32_t *p_chk_result); + +#endif /* ICUM_D_COMM_PE_H */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/src/icumif_lib/r_icumif.c b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/src/icumif_lib/r_icumif.c new file mode 100644 index 0000000..97d9ba4 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/src/icumif_lib/r_icumif.c @@ -0,0 +1,461 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ + +/**************************************************************************************/ +/* Header files */ +/**************************************************************************************/ +#include "r_icumif_api.h" +#include "r_icumif_pub.h" +#include "icum_d_comm_pe_pub.h" + +#include "r_icumif.h" + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_L_IF_0001]:[ICUMFW_UD_L_IF_0001] +* Function name: R_ICUMIF_Init +* Description : Initialize the ICU-M interface library +* Arguments : uint32_t *p_request_queue : Pointer to service request queue +* Return Value : int32_t Library initialization result +* 0 : Successful +* Negative values : Parameter error +***************************************************************************************/ +int32_t R_ICUMIF_Init(uint32_t *p_request_queue) +{ + int32_t ret_val = R_ICUMIF_ER_OK; + uint32_t call_comm_ret; + + /* 1. address check using Cluster RAM area check function */ + call_comm_ret = D_COMM_PE_CheckMemorySharedRAM((uint32_t)((uintptr_t)p_request_queue), (uint32_t)sizeof(uint32_t) * (uint32_t)TOTAL_QUEUE_LENGTH); + if (ER_OK == call_comm_ret) + { + /* 2. Parameter alignment check */ + if (0U != ((uint32_t)((uintptr_t)p_request_queue) & ALIGNMENT_4BYTE_CHECK_PATTERN)) + { + ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT; + } + else + { + /* 3. Execute COMM(PE) driver initialization to initialize service queue */ + call_comm_ret = D_COMM_PE_Init(p_request_queue); + + /* 4. According to result of COMM (PE) driver initialization process, */ + /* execute respective corresponding processes */ + if (ER_D_COMM_PARAM_NOT_G_RAM == call_comm_ret) + { + /* 4-1. Parameters other than shared RAM area, process is terminated */ + ret_val = R_ICUMIF_ER_ADDR_NOT_G_RAM; + } + else if (ER_D_COMM_QUE_NOT_ACCESS == call_comm_ret) + { + /* 4-2. */ + ret_val = R_ICUMIF_ER_SOFTWARE_ERROR; + } + else + { + /* 5. Execute interrupt enable process to enable interrupts from ICUP */ + D_COMM_SetInterruptEnable(); + } + } + } + else if (ER_D_COMM_ALIGN_NG == call_comm_ret) + { + ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT; + } + else + { + /* 6. */ + ret_val = R_ICUMIF_ER_ADDR_NOT_G_RAM; + } + + /* 7. */ + return (ret_val); +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_L_IF_0002]:[ICUMFW_UD_L_IF_0002] +* Function name: R_ICUMIF_ServiceRequest +* Description : Requests ICU-M to execute the service +* Arguments : r_icumif_isd_t *p_ISD : Pointer to ISD where request parameter is set +* Return Value : int32_t Service execution request result +* 0 : Successful +* Negative values : Parameter error, Interface library uninitialized +***************************************************************************************/ +int32_t R_ICUMIF_ServiceRequest(r_icumif_isd_t *p_ISD) +{ + int32_t ret_val = R_ICUMIF_ER_OK; + uint32_t call_comm_ret; + + /* 1. address check using Cluster RAM area check function */ + call_comm_ret = D_COMM_PE_CheckMemorySharedRAM((uint32_t)((uintptr_t)p_ISD), (uint32_t)sizeof(r_icumif_isd_t)); + if (ER_OK == call_comm_ret) + { + /* 2. Parameter alignment check */ + if (0U != ((uint32_t)((uintptr_t)p_ISD) & ALIGNMENT_4BYTE_CHECK_PATTERN)) + { + ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT; + } + else + { + /* 3-1. Set ID of service request PE */ + p_ISD->requester_id = (r_icumif_requester_id_t)GET_MY_PEID; + + /* 3-2. Set channel of service execution response interrupt */ + p_ISD->host_int_ch = ICUM_COMM_ICH_FM_SERV_RESPONSE; + + /* 3-3. Set initial state to service processing state */ + p_ISD->service_result = SERV_NEW_REQUEST; + + /* 4. In order to check whether area indicated by p_ISD exists in RAM, */ + /* it checks whether service processing state is SERV_NEW_REQUEST */ + if (SERV_NEW_REQUEST != p_ISD->service_result) + { + /* Not SERV_NEW_REQUEST, process is terminated */ + ret_val = R_ICUMIF_ER_ADDR_NOT_G_RAM; + } + else + { + /* 5. Execute interrupt issue process to issue service execution req interrupt */ + call_comm_ret = D_COMM_TriggerInterruptToICUP(ICUM_COMM_ICH_TO_SERV_REQUEST, p_ISD); + + /* 6. According to result of interrupt issue process, */ + /* execute respective corresponding processes */ + switch (call_comm_ret) + { + case ER_OK: + /* 6-1. Do nothing */ + break; + case ER_D_COMM_QUE_FULL: + /* 6-2. */ + p_ISD->req_res_status = R_ICUMIF_REQRES_PE_RES_DEQUE; + p_ISD->service_result = SERV_REQUEST_QUEUE_FULL; + ret_val = R_ICUMIF_ER_REQ_QUEUE_FULL; + break; + case ER_D_COMM_QUE_NOT_INIT: + /* 6-3. */ + ret_val = R_ICUMIF_ER_IF_LIB_NOT_INIT; + break; + case ER_PARAM: + case ER_D_COMM_QUE_NOT_ACCESS: + default: + /* 6-4. */ + ret_val = R_ICUMIF_ER_SOFTWARE_ERROR; + break; + } + } + } + } + else if (ER_D_COMM_ALIGN_NG == call_comm_ret) + { + ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT; + } + else + { + /* 7. */ + ret_val = R_ICUMIF_ER_ADDR_NOT_G_RAM; + } + + /* 8. */ + return (ret_val); +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_L_IF_0003]:[ICUMFW_UD_L_IF_0003] +* Function name: R_ICUMIF_ServiceResponse +* Description : Acquires ISD from service response queue for self PE +* Arguments : None +* Return Value : int32_t Service response reception process result +* 0 : Successful +* Negative values : Interface library uninitialized +***************************************************************************************/ +int32_t R_ICUMIF_ServiceResponse(void) +{ + int32_t ret_val = R_ICUMIF_ER_OK; + uint32_t call_comm_ret; + uint32_t call_comm_ret_isd; + uint32_t exist_isd = 1U; + r_icumif_isd_t *p_isd; + + /* Repeat process until there is no ISD in service response queue for self PE */ + while (1U == exist_isd) + { + /* 1. Acquires ISD from service response queue for self PE */ + call_comm_ret = D_COMM_GetResponseISD(&p_isd); + + /* 2. According to result of acquires ISD, */ + /* execute respective corresponding processes */ + switch (call_comm_ret) + { + case ER_OK: + case ER_D_COMM_EXIST_ISD: + /* 3-1. address check using Cluster RAM area check function */ + call_comm_ret_isd = D_COMM_PE_CheckMemorySharedRAM((uint32_t)((uintptr_t)p_isd), (uint32_t)sizeof(r_icumif_isd_t)); + if (ER_OK == call_comm_ret_isd) + { + /* 3-1-1. For detect that ICU-M could not update ISD, */ + /* check value of service process state in acquired ISD */ + if (SERV_NEW_REQUEST == p_isd->service_result) + { + /* 3-1-1-1. ICU-M could not update ISD */ + p_isd->service_result = SERV_ISD_NOT_ACCESSIBLE; + } + else + { + /* 3-1-1-2. */ + /* do nothing */ + } + + /* 3-1-2. */ + if (NULL != p_isd->ptr.p_callbackfunc) + { + /* 3-1-2-1. If there is registration of callback function, */ + /* calling callback function */ + p_isd->ptr.p_callbackfunc(p_isd); + } + else + { + /* 3-1-2-2. */ + /* do nothing */ + } + if (ER_OK == call_comm_ret) + { + exist_isd = 0U; + } + else + { + /* do nothing */ + } + } + else if (ER_D_COMM_ALIGN_NG == call_comm_ret_isd) + { + ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT; + exist_isd = 0U; + } + else + { + ret_val = R_ICUMIF_ER_ADDR_NOT_G_RAM; + exist_isd = 0U; + } + break; + case ER_D_COMM_NO_ISD: + /* 3-2. No ISD in service response queue, exit from loop process */ + exist_isd = 0U; + break; + case ER_D_COMM_QUE_NOT_INIT: + /* 3-3. Interface library not initialized */ + ret_val = R_ICUMIF_ER_IF_LIB_NOT_INIT; + exist_isd = 0U; + break; + case ER_D_COMM_QUE_NOT_ACCESS: + default: + /* 3-4. Software error */ + ret_val = R_ICUMIF_ER_SOFTWARE_ERROR; + exist_isd = 0U; + break; + } + } + + /* 4. Return the service response reception process result */ + return (ret_val); +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_L_IF_0004]:[ICUMFW_UD_L_IF_0004] +* Function name: R_ICUMIF_IsServiceCompleted +* Description : Check state of service execution requested to ICU-M +* Arguments : r_icumif_isd_t *p_ISD : Pointer to ISD that service execution requested +* Return Value : int32_t Service execution state +* 0 : Service running +* Other than 0 : Service execution completion +***************************************************************************************/ +int32_t R_ICUMIF_IsServiceCompleted(r_icumif_isd_t *p_ISD) +{ + int32_t ret_val; + uint8_t mem_check = ICUM_COMM_MEMCHECK_OK; + uint32_t call_comm_ret; + + /* 1. address check using Cluster RAM area check function */ + call_comm_ret = D_COMM_PE_CheckMemorySharedRAM((uint32_t)((uintptr_t)p_ISD), (uint32_t)sizeof(r_icumif_isd_t)); + if (ER_OK == call_comm_ret) + { + /* 2. Parameter alignment check */ + if (0U != ((uint32_t)((uintptr_t)p_ISD) & ALIGNMENT_4BYTE_CHECK_PATTERN)) + { + ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT; + } + else + { + if ((p_ISD->service_id == SERVICE_01_AES_CMAC) && + ((uint32_t)p_ISD->service_priority == R_ICUMIF_SERV_PRIORITY_HIGHEST)) + { + /* Do nothing */ + } + else + { + (void)D_COMM_GetICUMemCheckErrInfo(&mem_check); + } + + if (ICUM_COMM_MEMCHECK_OK == (uint32_t)mem_check) + { + /* 3. Check service request / response queue transition state in ISD */ + ret_val = R_ICUMIF_RTN_SERV_RUNNING; + + /* 4. Service execution completion */ + switch ((uint32_t)p_ISD->req_res_status) + { + case R_ICUMIF_REQRES_ICUM_RES_ENQUE: + if ((uint32_t)p_ISD->res_nointerrupt == R_ICUMIF_REQRES_NOINTERRPUT) + { + ret_val = R_ICUMIF_RTN_SERV_COMPLETION; + } + else + { + /* Do nothing */ + } + break; + case R_ICUMIF_REQRES_PE_RES_DEQUE: + /* 4-1. Check value of service process state in ISD */ + if (SERV_REQUEST > p_ISD->service_result) + { + /* 4-1-1. Service execution completion */ + ret_val = R_ICUMIF_RTN_SERV_COMPLETION; + } + else + { + /* Do nothing */ + } + break; + case R_ICUMIF_REQRES_PE_REQ_ENQUE: + if ((uint32_t)p_ISD->req_nointerrupt == R_ICUMIF_REQRES_NOINTERRPUT) + { + ret_val = R_ICUMIF_RTN_SERV_COMPLETION; + } + else + { + /* Do nothing */ + } + break; + case R_ICUMIF_REQRES_ICUM_REQ_DEQUE: + /* 4-2. Service running */ + /* Initial value */ + break; + default: + /* 4-3. */ + ret_val = R_ICUMIF_ER_SOFTWARE_ERROR; + break; + } + } + else + { + ret_val = R_ICUMIF_ER_ADDR_NOT_G_RAM; + } + } + } + else if (ER_D_COMM_ALIGN_NG == call_comm_ret) + { + ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT; + } + else + { + /* 5. */ + ret_val = R_ICUMIF_ER_ADDR_NOT_G_RAM; + } + + /* 6. */ + return (ret_val); +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_L_IF_0005]:[ICUMFW_UD_L_IF_0005] +* Function name: R_ICUMIF_GetStatus +* Description : Acquire address value of status information of ICU-M Firmware +* Arguments : None +* Return Value : r_icumif_sts_t * Address value of ICU-M Firmware status information +***************************************************************************************/ +r_icumif_sts_t *R_ICUMIF_GetStatus(void) +{ + r_icumif_sts_t *p_status; + + /* 1. Acquire address value of status information of ICU-M Firmware */ + p_status = D_COMM_GetICUStatusAddr(); + + /* 2. */ + return (p_status); +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_L_IF_0008]:[ICUMFW_UD_L_IF_0008] +* Function name: R_ICUMIF_SetSystemCallBackFunc +* Description : Register the function to call back when receiving system interrupt +* Arguments : R_ICUMIF_CB_REGIST_t *p_regist_info : Pointer to registration info +* Return Value : int32_t Callback registration result +* 0 : Successful +* Negative values : Parameter error +***************************************************************************************/ +int32_t R_ICUMIF_SetSystemCallBackFunc(R_ICUMIF_CB_REGIST_t *p_regist_info) +{ + int32_t ret_val = R_ICUMIF_ER_OK; + uint32_t call_comm_ret; + alignment_check_t prm_ptr; + + /* 1. Parameter alignment check ( p_regist_info ) */ + if (0U != ((uint32_t)((uintptr_t)p_regist_info) & ALIGNMENT_4BYTE_CHECK_PATTERN)) + { + ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT; + } + else + { + /* 2. Parameter alignment check ( callback function address ) */ + prm_ptr.p_align_check = p_regist_info->p_func_addr; + if (0U != (prm_ptr.val_align_check & ALIGNMENT_2BYTE_CHECK_PATTERN)) + { + ret_val = R_ICUMIF_ER_PARAM_ALIGNMENT; + } + else + { + /* 3. Register the function to call back */ + call_comm_ret = D_COMM_SetSystemCallBackFunc(p_regist_info); + + /* 4. According to result of callback function regist process, */ + /* execute respective corresponding processes */ + switch (call_comm_ret) + { + case ER_OK: + /* 4-1. Do nothing */ + break; + default: + /* 4-2. Software error */ + ret_val = R_ICUMIF_ER_SOFTWARE_ERROR; + break; + } + } + } + + /* 5. Return callback registration result */ + return (ret_val); +} + +/*************************************************************************************** +* Function ID : [ICUMFW_CD_L_IF_0010]:[ICUMFW_UD_L_IF_0010] +* Function name: R_ICUMIF_IRQ_Handler +* Description : Execute interrupt process of ICUP --> PE (INTICUP) +* Arguments : None +* Return Value : None +***************************************************************************************/ +void R_ICUMIF_IRQ_Handler(void) +{ + D_COMM_IRQ_Handler(); +} diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/src/icumif_lib/r_icumif.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/src/icumif_lib/r_icumif.h new file mode 100644 index 0000000..5d1e430 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/src/icumif_lib/r_icumif.h @@ -0,0 +1,60 @@ +/******************************************************************************/ +/* Component Name ICU-M Interface Library (ICUMIF) */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/******************************************************************************* +* Copyright(C) 2021-2023 Renesas Electronics Corporation. +* +* RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +* +* These instructions, statements, and programs are the confidential information +* of Renesas Electronics Corporation. They must be used and modified solely for +* the purpose for which it was furnished by Renesas Electronics Corporation. +* All part of them must not be reproduced nor disclosed to others in any form, +* without the prior written permission of Renesas Electronics Corporation. +*******************************************************************************/ + +#if !defined(R_ICUMIF_H) +#define R_ICUMIF_H + +/**************************************************************************************/ +/* Defines */ +/**************************************************************************************/ + +/*====================================================================================*/ +/* Data pattern of alignment check */ +/*====================================================================================*/ +#define ALIGNMENT_4BYTE_CHECK_PATTERN (0x00000003U) /* 4 byte alignment */ +#define ALIGNMENT_2BYTE_CHECK_PATTERN (0x00000001U) /* 2 byte alignment */ + +/**************************************************************************************/ +/* Macros */ +/**************************************************************************************/ +/* None */ + +/**************************************************************************************/ +/* Type definition */ +/**************************************************************************************/ +/* None */ + +/**************************************************************************************/ +/* Enumeration */ +/**************************************************************************************/ +/* None */ + +/**************************************************************************************/ +/* Structure Definition */ +/**************************************************************************************/ + +/*====================================================================================*/ +/* Union for alignment check of pointer value */ +/*====================================================================================*/ +typedef union alignment_check +{ + void (*p_align_check)(void); + uint32_t val_align_check; +} alignment_check_t; + +#endif /* R_ICUMIF_H */ + diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/user_api/user_icumif_api.c b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/user_api/user_icumif_api.c new file mode 100644 index 0000000..a875a20 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/user_api/user_icumif_api.c @@ -0,0 +1,103 @@ +/******************************************************************************/ +/* Component Name Customer-implement component */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/* Copyright(C) 2021-2023 Renesas Electronics Corporation. */ +/******************************************************************************/ +/********************************************************************************** +* Include +***********************************************************************************/ + +#include "renesas_types.h" + +#include "user_icumif_api.h" + +/********************************************************************************** +* Globals +***********************************************************************************/ + +extern void flush_dcache_range(uintptr_t addr, uint32_t size); +extern void inv_dcache_range(uintptr_t addr, uint32_t size); + +/********************************************************************************** +* Define +***********************************************************************************/ + +#define D_CACHE_LINE_ADDR_MASK (0xFFFFFFC0U) + +#define D_CACHE_LIMIT_ADDR (0xFFFFFFC0U) + +#define CR52_CPSR_IRQ_DISABLE_STATUS (0x00000080U) + +#define CR52_PEID (0x00000000u) + +#define CA_CPU_ID_MASK (0x0000FF00U) +#define CA_CPU_ID_SHIT (8u) +#define CA_CLUSTER_ID_MASK (0x00FF0000U) +#define CA_CLUSTER_ID_SHIT (16u) + +/********************************************************************************** +* Function +***********************************************************************************/ + +void USER_ICUMIF_FlushDCache(uint32_t addr, uint32_t size) +{ + /* do nothing */ +} + +void USER_ICUMIF_InvalidateDCache(uint32_t addr, uint32_t size) +{ + /* do nothing */ +} + +uint32_t USER_ICUMIF_GetMyPEID(void) +{ + uint32_t peid; + +#if defined(TARGET_CORTEX_A) + uintptr_t mpidr; +#if defined(AARCH64) + __asm volatile ("mrs %0, MPIDR_EL1" : "=r" (mpidr)); +#else + __asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr)); +#endif + + peid = ((mpidr & CA_CPU_ID_MASK) >> CA_CPU_ID_SHIT) + (((mpidr & CA_CLUSTER_ID_MASK) >> CA_CLUSTER_ID_SHIT) * 2) + CR52_CPU_NUM; +#elif defined(TARGET_DEVICE_S4X) + peid = CR52_PEID; +#else + uintptr_t mpidr; + + __asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr)); + peid = ((mpidr & CA_CPU_ID_MASK) >> CA_CPU_ID_SHIT) + (((mpidr & CA_CLUSTER_ID_MASK) >> CA_CLUSTER_ID_SHIT) * 2); +#endif + + return (peid); +} + +void USER_ICUMIF_GetLock(uintptr_t *p_saved_psw) +{ + uintptr_t saved_psw; + + saved_psw = *p_saved_psw; + USER_ICUMIF_GET_LOCK(saved_psw); + *p_saved_psw = saved_psw; +} + +void USER_ICUMIF_ReleaseLock(uintptr_t saved_psw) +{ + USER_ICUMIF_RELEASE_LOCK(saved_psw); +} + +static void USER_ICUMIF_SYNC(void) +{ + __asm("dmb sy"); + __asm("dsb sy"); + __asm("isb"); +} + +void USER_ICUMIF_Sync(void) +{ + USER_ICUMIF_SYNC(); +} diff --git a/IPL/Customer/Mobis/V4H_Cx_Loader/secure/user_api/user_icumif_api.h b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/user_api/user_icumif_api.h new file mode 100644 index 0000000..0802ab5 --- /dev/null +++ b/IPL/Customer/Mobis/V4H_Cx_Loader/secure/user_api/user_icumif_api.h @@ -0,0 +1,97 @@ +/******************************************************************************/ +/* Component Name Customer-implement component */ +/******************************************************************************/ +/* Product : ICU-M Firmware */ +/******************************************************************************/ +/* Copyright(C) 2021-2023 Renesas Electronics Corporation. */ +/******************************************************************************/ + +#ifndef USER_ICUMIF_API_H_ +#define USER_ICUMIF_API_H_ + +/* Bit pattern of current program status register */ +#define FIQ_BIT (0x00000040U) +#define IRQ_BIT (0x00000080U) +#define FIQ_DISABLE (0x00000040U) +#define IRQ_DISABLE (0x00000080U) + +#if defined(TARGET_DEVICE_S4X) +#define CR52_CPU_NUM (1u) +#define CA_CPU_NUM (8u) +#else /* TARGET_DEVICE_V4H */ +#define CR52_CPU_NUM (3u) +#define CA_CPU_NUM (4u) +#endif + +void USER_ICUMIF_FlushDCache(uint32_t addr, uint32_t size); +void USER_ICUMIF_InvalidateDCache(uint32_t addr, uint32_t size); +uint32_t USER_ICUMIF_GetMyPEID(void); +void USER_ICUMIF_GetLock(uintptr_t *p_saved_psw); +void USER_ICUMIF_ReleaseLock(uintptr_t saved_psw); +void USER_ICUMIF_Sync(void); + +#if defined(TARGET_CORTEX_A) && defined(AARCH64) +#define USER_ICUMIF_GET_LOCK(X) \ + do\ + {\ + __asm ("mrs %0, DAIF" : "=r" (X));\ + if ((IRQ_DISABLE != ((X) & IRQ_BIT)) || (FIQ_DISABLE != ((X) & FIQ_BIT)))\ + {\ + __asm ("msr DAIFSet, #0x3");\ + }\ + } while (0) +#else +#define USER_ICUMIF_GET_LOCK(X) \ + do\ + {\ + __asm volatile ("mrs %0, cpsr" : "=r" (X));\ + if ((IRQ_DISABLE != ((X) & IRQ_BIT)) || (FIQ_DISABLE != ((X) & FIQ_BIT)))\ + {\ + __asm ("cpsid if");\ + }\ + } while (0) +#endif + +#if defined(TARGET_CORTEX_A) && defined(AARCH64) +#define USER_ICUMIF_RELEASE_LOCK(X) \ + do\ + {\ + if (FIQ_DISABLE != ((X) & FIQ_BIT))\ + {\ + __asm ("msr DAIFClr, #0x1");\ + }\ + else\ + {\ + }\ + if (IRQ_DISABLE != ((X) & IRQ_BIT))\ + {\ + __asm ("msr DAIFClr, #0x2");\ + }\ + else\ + {\ + }\ + } while (0) +#else +#define USER_ICUMIF_RELEASE_LOCK(X) \ + do\ + {\ + if (FIQ_DISABLE != ((X) & FIQ_BIT))\ + {\ + __asm ("cpsie f");\ + }\ + else\ + {\ + }\ + if (IRQ_DISABLE != ((X) & IRQ_BIT))\ + {\ + __asm ("cpsie i");\ + }\ + else\ + {\ + }\ + } while (0) +#endif + + +#endif /* USER_ICUMIF_API_H_ */ + diff --git a/IPL/Customer/Mobis/ca76_loader/.gitignore b/IPL/Customer/Mobis/ca76_loader/.gitignore new file mode 100644 index 0000000..567609b --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/.gitignore @@ -0,0 +1 @@ +build/ diff --git a/IPL/Customer/Mobis/ca76_loader/AArch64_boot/boot_mon.h b/IPL/Customer/Mobis/ca76_loader/AArch64_boot/boot_mon.h new file mode 100644 index 0000000..40743ab --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/AArch64_boot/boot_mon.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +;#RWDT +;#R-CarH3 77. RCLK Watchdog Timer +.EQU RWDT_RWTCNT , 0xE6020000 ;#RCLK watchdog timer counter +.EQU RWDT_RWTCSRA , 0xE6020004 ;#RCLK watchdog timer control/status register A +.EQU RWDT_RWTCSRB , 0xE6020008 ;#RCLK watchdog timer control/status register B + +;#SystemWDT +;#R-CarH3 78. System Watchdog Timer +.EQU SYSWDT_WTCNT , 0xE6030000 ;#watchdog timer counter +.EQU SYSWDT_WTCSRA , 0xE6030004 ;#watchdog timer control/status register A +.EQU SYSWDT_WTCSRB , 0xE6030008 ;#watchdog timer control/status register B + +.EQU PRR , 0xFFF00044 ;#Product Register + +.macro STARTFUNC name + .global \name + .func \name + \name: +.endm + +.macro ENDFUNC name + .type \name, %function + .endfunc +.endm + diff --git a/IPL/Customer/Mobis/ca76_loader/AArch64_boot/boot_mon.s b/IPL/Customer/Mobis/ca76_loader/AArch64_boot/boot_mon.s new file mode 100644 index 0000000..c370577 --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/AArch64_boot/boot_mon.s @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +;# W0-W30 : 32bit Register (W30=Link Register) +;# X0-X30 : 64bit Register (X30=Link Register) +;# WZR : 32bit Zero Register +;# XZR : 64bit Zero Register +;# WSP : 32bit Stack Pointer +;# SP : 64bit Stack Pointer + + .INCLUDE "boot_mon.h" + .ALIGN 4 + +;# Initialize registers +Register_init: + LDR X0, =0 + LDR X1, =0 + LDR X2, =0 + LDR X3, =0 + LDR X4, =0 + LDR X5, =0 + LDR X6, =0 + LDR X7, =0 + LDR X8, =0 + LDR X9, =0 + LDR X10, =0 + LDR X11, =0 + LDR X12, =0 + LDR X13, =0 + LDR X14, =0 + LDR X15, =0 + LDR X16, =0 + LDR X17, =0 + LDR X18, =0 + LDR X19, =0 + LDR X20, =0 + LDR X21, =0 + LDR X22, =0 + LDR X23, =0 + LDR X24, =0 + LDR X25, =0 + LDR X26, =0 + LDR X27, =0 + LDR X28, =0 + LDR X29, =0 + LDR X30, =0 + +Set_EnableRAM: +;# LDR X0, =0xE67F0018 +;# LDR W1, =0x00000001 ;#Enable DRAM/SECRAM/PUBRAM +;# STR W1, [X0] + + MRS X0, CurrentEL + CMP X0, #0x0000000C + BEQ current_EL3 + + +current_EL1: +;# Loader + LDR x0, =__STACKS_END__ +;# MSR SP_EL0,x0 +;# MSR SP_EL1,x0 +;# MSR SP_EL2,x0 + MOV sp,x0 + MOV x0, #0x50000000 + MSR ELR_EL1,x0 +;# MSR ELR_EL2,x0 +;# MSR ELR_EL3,x0 + MOV x0, #0x03C5 + MSR SPSR_EL1,x0 +;# MSR SPSR_EL2,x0 +;# MSR SPSR_EL3,x0 + +;# Enable cache +;# mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el1 + orr x0, x0, #(0x1 << 12) + orr x0, x0, #(0x1 << 1) + orr x0, x0, #(0x1 << 3) + msr sctlr_el1, x0 + isb + b bss_clr + +current_EL3: +;# Loader + LDR x0, =__STACKS_END__ +;# MSR SP_EL0,x0 +;# MSR SP_EL1,x0 +;# MSR SP_EL2,x0 + MOV sp,x0 + MOV x0, #0xE38 + MSR SCR_EL3, x0 + MOV x0, #0x44100000 +;# MSR ELR_EL1,x0 +;# MSR ELR_EL2,x0 + MSR ELR_EL3,x0 + MOV x0, #0x03C5 +;# MSR SPSR_EL1,x0 +;# MSR SPSR_EL2,x0 + MSR SPSR_EL3,x0 + +;# Board Initialize +.ifdef Area0Boot + +Init_set_WDT: + LDR W0, =RWDT_RWTCSRA + LDR W1, =0xA5A5A500 ;#Timer disabled + STR W1, [X0] + +Init_set_SYSWDT: + LDR W0, =SYSWDT_WTCSRA + LDR W1, =0xA5A5A500 ;#Timer disabled (Enable -> disabled) + STR W1, [X0] + +.endif + + + +;# Enable cache +;# mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el3 + orr x0, x0, #(0x1 << 12) + orr x0, x0, #(0x1 << 1) + orr x0, x0, #(0x1 << 3) + msr sctlr_el3, x0 + isb + + + /* clear bss section */ +bss_clr: + mov X0, #0x0 + ldr X1, =__BSS_START__ + ldr X2, =__BSS_SIZE__ +bss_loop: + subs X2, X2, #4 + bcc bss_end + str W0, [X1, X2] + b bss_loop +bss_end: + +.ifdef Area0Boot + /* copy data section */ + ldr X0, =__DATA_COPY_START__ + ldr X1, =__DATA_START__ + ldr X2, =__DATA_SIZE__ +data_loop: + subs X2, X2, #4 + bcc data_end + ldr W3, [X0, X2] + str W3, [X1, X2] + b data_loop +.endif + +data_end: + +;# BL InitScif + + BL Main + + mov X1, #0x50000000 + BR X1 + + .END + diff --git a/IPL/Customer/Mobis/ca76_loader/AArch64_boot/d_armasm.h b/IPL/Customer/Mobis/ca76_loader/AArch64_boot/d_armasm.h new file mode 100644 index 0000000..e0b9461 --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/AArch64_boot/d_armasm.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef D_ARMASM_H +#define D_ARMASM_H + +void DCacheEnable(); +void WriteTCR_EL3(uint64_t data); +void WriteMAIR_EL3(uint64_t data); +void WriteTTBR0_EL3(uint64_t data); + +#endif /* D_ARMASM_H */ + diff --git a/IPL/Customer/Mobis/ca76_loader/AArch64_boot/d_armasm.s b/IPL/Customer/Mobis/ca76_loader/AArch64_boot/d_armasm.s new file mode 100644 index 0000000..a6e51e8 --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/AArch64_boot/d_armasm.s @@ -0,0 +1,288 @@ +/**********************************************************/ +/* Sample program : Debug ARM Assembly Program */ +/* File Name : d_armasm.s */ +/* Copyright (C) Renesas Electronics Corp. 2015. */ +/**********************************************************/ + + .INCLUDE "boot_mon.h" + .ALIGN 4 + + +;# uint32_t MonCp15Mpidr(void); +STARTFUNC MonCp15Mpidr + MRS X0, VMPIDR_EL2 ;# read Multiprocessor ID register + RET +ENDFUNC MonCp15Mpidr + + +;# uint32_t MonCp15Midr(void); +STARTFUNC MonCp15Midr + MRS X0, VPIDR_EL2 ;# read Processor ID Register + RET +ENDFUNC MonCp15Midr + + +;# void WriteTCR_EL3( uint64_t data ); +;# data[63:39]=RES0 +;# data[38][37][36][35][34:32]=TBI1,TBI0,AS,RES0,IPS +;# data[31:30][29:28][27:26][25:24][23][22][21:16]=TG1,SH1,ORGN1,IRGN1,EPD1,A1 ,T1SZ +;# data[15:14][13:12][11:10][09:08][07][06][05:00]=TG0,SH0,ORGN0,IRGN0,EPD0,RES0,T0SZ +STARTFUNC WriteTCR_EL3 + MSR TCR_EL3, X0 + RET +ENDFUNC WriteTCR_EL3 + + +;# void WriteMAIR_EL3( uint64_t data ); +;# data[63:56][55:48][47:40][39:32]=Attr7,Attr6,Attr5,Attr4 +;# data[31:24][23:16][15: 8][ 7: 0]=Attr3,Attr2,Attr1,Attr0 +STARTFUNC WriteMAIR_EL3 + MSR MAIR_EL3, X0 + RET +ENDFUNC WriteMAIR_EL3 + + +;# void WriteTTBR0_EL3( uint64_t data ); +;# data[63:48]=ASID +;# data[47: 0]=BADDR +STARTFUNC WriteTTBR0_EL3 + MSR TTBR0_EL3, X0 + RET +ENDFUNC WriteTTBR0_EL3 + + +;# void CleaningAndInvalidateICache(void); +STARTFUNC CleaningAndInvalidateICache + IC IALLUIS + ISB SY + RET +ENDFUNC CleaningAndInvalidateICache + + +;# Refer: DEN0024A_v8_architecture_PG.pdf +;# void CleaningDCache(void); +STARTFUNC CleaningDCache + MRS X0, CLIDR_EL1 + AND W3, W0, #0x07000000 // Get 2 x Level of Coherence + LSR W3, W3, #23 + CBZ W3, DC_Finished + MOV W10, #0 // W10 = 2 x cache level + MOV W8, #1 // W8 = constant 0b1 +DC_Loop1: + ADD W2, W10, W10, LSR #1 // Calculate 3 x cache level + LSR W1, W0, W2 // extract 3-bit cache type for this level + AND W1, W1, #0x7 + CMP W1, #2 + B.LT DC_Skip // No data or unified cache at this level + MSR CSSELR_EL1, X10 // Select this cache level + ISB // Synchronize change of CSSELR + MRS X1, CCSIDR_EL1 // Read CCSIDR + AND W2, W1, #7 // W2 = log2(linelen)-4 + ADD W2, W2, #4 // W2 = log2(linelen) + UBFX W4, W1, #3, #10 // W4 = max way number, right aligned + CLZ W5, W4 // W5 = 32-log2(ways), bit position of way in DC operand + LSL W9, W4, W5 // W9 = max way number, aligned to position in DC operand + LSL W16, W8, W5 // W16 = amount to decrement way number per iteration +DC_Loop2: + UBFX W7, W1, #13, #15 // W7 = max set number, right aligned + LSL W7, W7, W2 // W7 = max set number, aligned to position in DC operand + LSL W17, W8, W2 // W17 = amount to decrement set number per iteration +DC_Loop3: + ORR W11, W10, W9 // W11 = combine way number and cache number... + ORR W11, W11, W7 // ... and set number for DC operand + DC CSW, X11 // Do data cache clean by set and way + SUBS W7, W7, W17 // Decrement set number + B.GE DC_Loop3 + SUBS X9, X9, X16 // Decrement way number + B.GE DC_Loop2 +DC_Skip: + ADD W10, W10, #2 // Increment 2 x cache level + CMP W3, W10 + DSB SY // Ensure completion of previous cache maintenance operation + B.GT DC_Loop1 +DC_Finished: + DSB SY ;# Add DSB + ISB ;# Add ISB + RET +ENDFUNC CleaningDCache + + +;# Refer: DEN0024A_v8_architecture_PG.pdf +;# uint32_t CleaningAndInvalidateDCache(void); +STARTFUNC CleaningAndInvalidateDCache + MRS X0, CLIDR_EL1 + AND W3, W0, #0x07000000 // Get 2 x Level of Coherence + LSR W3, W3, #23 + CBZ W3, DCI_Finished + MOV W10, #0 // W10 = 2 x cache level + MOV W8, #1 // W8 = constant 0b1 +DCI_Loop1: + ADD W2, W10, W10, LSR #1 // Calculate 3 x cache level + LSR W1, W0, W2 // extract 3-bit cache type for this level + AND W1, W1, #0x7 + CMP W1, #2 + B.LT DCI_Skip // No data or unified cache at this level + MSR CSSELR_EL1, X10 // Select this cache level + ISB // Synchronize change of CSSELR + MRS X1, CCSIDR_EL1 // Read CCSIDR + AND W2, W1, #7 // W2 = log2(linelen)-4 + ADD W2, W2, #4 // W2 = log2(linelen) + UBFX W4, W1, #3, #10 // W4 = max way number, right aligned + CLZ W5, W4 // W5 = 32-log2(ways), bit position of way in DC operand + LSL W9, W4, W5 // W9 = max way number, aligned to position in DC operand + LSL W16, W8, W5 // W16 = amount to decrement way number per iteration +DCI_Loop2: + UBFX W7, W1, #13, #15 // W7 = max set number, right aligned + LSL W7, W7, W2 // W7 = max set number, aligned to position in DC operand + LSL W17, W8, W2 // W17 = amount to decrement set number per iteration +DCI_Loop3: + ORR W11, W10, W9 // W11 = combine way number and cache number... + ORR W11, W11, W7 // ... and set number for DC operand + DC CISW, X11 // Do data cache clean and invalidate by set and way + SUBS W7, W7, W17 // Decrement set number + B.GE DCI_Loop3 + SUBS X9, X9, X16 // Decrement way number + B.GE DCI_Loop2 +DCI_Skip: + ADD W10, W10, #2 // Increment 2 x cache level + CMP W3, W10 + DSB SY // Ensure completion of previous cache maintenance operation + B.GT DCI_Loop1 +DCI_Finished: + DSB SY ;# Add DSB + ISB ;# Add ISB + RET +ENDFUNC CleaningAndInvalidateDCache + + +;# void DCacheEnable(void); +STARTFUNC DCacheEnable + MOV X20, X30 ;# Save LR data to X20 + + BL SetVmsaTable ;# MMU Table setting + + ISB ;# The ISB forces these changes to be seen before the MMU is enabled. + MRS X0, SCTLR_EL3 ;# Read System Control Register configuration data + ORR X0, X0, #1 ;# Set [M] bit and enable the MMU. + ORR X0, X0, #4 ;# Set [C] bit and enable the Data Cache. + DSB SY + MSR SCTLR_EL3, X0 ;# Write System Control Register configuration data + ISB ;# The ISB forces these changes to be seen by the next instruction + + MOV X30, X20 ;# Load LR data from X20 + RET +ENDFUNC DCacheEnable + + +;# void DCacheDisable(void); +STARTFUNC DCacheDisable + MOV X20, X30 ;# Save LR data to X20 + + DSB SY + ISB ;# + MRS X0, SCTLR_EL3 ;# +;# ORR X0, X0, #1 ;# Set [M] bit and enable the MMU. +;# ORR X0, X0, #4 ;# Set [C] bit and enable the Data Cache. + bic X0, X0, #1 ;# Set [M] bit and disable the MMU. + bic X0, X0, #4 ;# Set [C] bit and disable the Data Cache. + DSB SY + MSR SCTLR_EL3, X0 ;# + DSB SY + ISB ;# + + BL CleaningDCache + BL CleaningAndInvalidateDCache + DSB SY + ISB ;# + + MOV X30, X20 ;# Load LR data from X20 + RET +ENDFUNC DCacheDisable + + +STARTFUNC InterruptDisableDAIF + MRS X0, DAIF ;# Read DAIF + LDR W2, =0xC0 ;# bit[7]:IRQ mask bit, bit[6]:FIQ mask bit + ORR X0,X0,X2 ;# => 0:Exception not masked, 1: Exception masked + MSR DAIF, X0 ;# Write DAIF + RET +ENDFUNC InterruptDisableDAIF + + +STARTFUNC ReadSCR_EL3 + MRS X0, SCR_EL3 ;# Read SCR_EL3 + RET +ENDFUNC ReadSCR_EL3 + + +STARTFUNC InterruptDisableSCR_EL3 + MRS X0, SCR_EL3 ;# Read SCR_EL3 + LDR W2, =0x6 ;# bit[2]:Physical FIQ Routing, bit[1]:Physical IRQ Routing + BIC X0,X0,X2 ;# => 0:Interrupt not taken, 1: Interrupt are taken + MSR SCR_EL3, X0 ;# Write SCR_EL3 + RET +ENDFUNC InterruptDisableSCR_EL3 + + +STARTFUNC DropToEl1 + MRS X0, HCR_EL2 ;# Read HCR_EL2 + LDR W2, =0x80000000 ;# bit[31]:EL1 is AArch64 + ORR X0,X0,X2 ;# => 0:Lower levels are all AArch32 1:EL1 is AArch64 + MSR HCR_EL2, X0 ;# Write HCR_EL2 + + MRS X0, SCR_EL3 ;# Read SCR_EL3 + LDR W2, =0x400 ;# bit[10]:EL1 is AArch64 + ORR X0,X0,X2 ;# => 0:Lower levels are all AArch32 1:EL2/1 are AArch64 + MSR SCR_EL3, X0 ;# Write SCR_EL3 + + LDR W0, =0x3C5 ;# bit[3:0]:EL1h + MSR SPSR_EL3, X0 ;# Write SPSR_EL3 + + MOV X0, SP + MSR SP_EL1,X0 + MOV X0, X30 + MSR ELR_EL3,X0 + ERET +ENDFUNC DropToEl1 + +STARTFUNC UpToEl3 + LDR W0, =0x3CD ;# bit[3:0]:EL3h + MSR SPSR_EL3, X0 ;# Write SPSR_EL3 + + MRS X0, SP_EL1 ;# Read SP_EL1 + MOV SP, X0 +;# MOV X0, X30 +;# MRS X0, ELR_EL1 ;# Read ELR_EL1 +;# MSR ELR_EL3,X0 + RET +ENDFUNC UpToEl3 + + +STARTFUNC ChangeNonSecure + MRS X0, SCR_EL3 ;# Read SCR_EL3 + LDR W2, =0x1 ;# bit[0]:Non-secure bit +;# LDR W2, =0x481 ;# bit[0]:Non-secure bit + ORR X0,X0,X2 ;# => 0:Secure, 1:Non-secure + MSR SCR_EL3, X0 ;# Write SCR_EL3 + RET +ENDFUNC ChangeNonSecure + + +STARTFUNC ChangeSecure + MRS X0, SCR_EL3 ;# Read SCR_EL3 + LDR W2, =0x0 ;# bit[0]:Non-secure bit + ORR X0,X0,X2 ;# => 0:Secure, 1:Non-secure + MSR SCR_EL3, X0 ;# Write SCR_EL3 + RET +ENDFUNC ChangeSecure + + +;# void SoftDelayAsm(uint32_t count); ƒLƒƒƒbƒVƒ…ON‚Ìê‡A2clock‚Å1Žü‰Â”\ (AArch64) +STARTFUNC SoftDelayAsm ;# ˆø”‚ð‚»‚Ì‚Ü‚ÜŒ¸ŽZ‚ÉŽg—p‚·‚é + SUBS W0, W0, #1 ;# ƒtƒ‰ƒO‚ðXV‚µ‚‚Œ¸ŽZ 1step + BNE SoftDelayAsm ;# R0==0‚É‚È‚é‚܂Ń‹[ƒv 1step + RET ;# ŒÄ‚Ño‚µŒ³‚É–ß‚é +ENDFUNC SoftDelayAsm + + + .END diff --git a/IPL/Customer/Mobis/ca76_loader/AArch64_boot/stack.s b/IPL/Customer/Mobis/ca76_loader/AArch64_boot/stack.s new file mode 100644 index 0000000..a450de9 --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/AArch64_boot/stack.s @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + + + .section writer_stack, "aw", %nobits + .align 5 +stacks: + .space (8*1024), 0 + + .end diff --git a/IPL/Customer/Mobis/ca76_loader/LICENSE.md b/IPL/Customer/Mobis/ca76_loader/LICENSE.md new file mode 100644 index 0000000..af0ee77 --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/LICENSE.md @@ -0,0 +1 @@ +Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. diff --git a/IPL/Customer/Mobis/ca76_loader/Makefile b/IPL/Customer/Mobis/ca76_loader/Makefile new file mode 100644 index 0000000..9d95c24 --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/Makefile @@ -0,0 +1,346 @@ +# +# Copyright (c) 2020 Renesas Electronics Corporation. All rights reserved. +# +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +V=@ + +# LSI setting common define +RCAR_S4:=0 +RCAR_V4H:=1 +RCAR_V4M:=2 +NORMAL:=0 +SECURE:=1 +HS400:=0 +HS200:=1 +HIGH_SPEED:=2 +NO_HIGH_SPEED:=3 +$(eval $(call add_define,RCAR_S4)) +$(eval $(call add_define,RCAR_V4H)) +$(eval $(call add_define,RCAR_V4M)) +$(eval $(call add_define,NORMAL)) +$(eval $(call add_define,SECURE)) +$(eval $(call add_define,HS400)) +$(eval $(call add_define,HS200)) +$(eval $(call add_define,HIGH_SPEED)) +$(eval $(call add_define,NO_HIGH_SPEED)) +ifneq ("$(FORCE_115200)", "") +$(eval $(call add_define,FORCE_115200)) +endif +$(eval $(call add_define,MOBIS_PRK3)) + +#/* Select LSI("S4" or "V4H" or "V4M")*********************** +ifeq ("$(LSI)", "") +LSI = V4H +endif + +ifeq (${LSI},V4H) + RCAR_LSI:=${RCAR_V4H} +else + $(error "Error: ${LSI} is not supported.") +endif +$(eval $(call add_define,RCAR_LSI)) + +ifndef BOOT_MODE + BOOT_MODE:=${NORMAL} +else + ifeq (${BOOT_MODE},NORMAL) + BOOT_MODE:=${NORMAL} + else ifeq (${BOOT_MODE},SECURE) + BOOT_MODE:=${SECURE} + ifeq (${LSI},V4H) + $(eval $(call add_define,TARGET_CORTEX_A)) + $(eval $(call add_define,TARGET_DEVICE_V4H)) + endif + else + $(error "Error: ${BOOT_MODE} is not supported.") + endif + $(eval $(call add_define,BOOT_MODE)) +endif +$(eval $(call add_define,AARCH64)) + +ifndef EMMC_TRANS_MODE + EMMC_TRANS_MODE:=${HS400} +else + ifeq (${EMMC_TRANS_MODE},HS400) + EMMC_TRANS_MODE:=${HS400} + else ifeq (${EMMC_TRANS_MODE},HS200) + EMMC_TRANS_MODE:=${HS200} + else ifeq (${EMMC_TRANS_MODE},HIGH_SPEED) + EMMC_TRANS_MODE:=${HIGH_SPEED} + else ifeq (${EMMC_TRANS_MODE},NO_HIGH_SPEED) + EMMC_TRANS_MODE:=${NO_HIGH_SPEED} + else + $(error "Error: ${EMMC_TRANS_MODE} is not supported.") + endif + $(eval $(call add_define,EMMC_TRANS_MODE)) +endif + +RTOS_LOAD_NUM := 1 +$(eval $(call add_define,RTOS_LOAD_NUM)) + +BOOT = ICUMXA +AArch = 64 +CPU = -march=armv8-a +AS_NEON = +CC_NEON = # -mgeneral-regs-only +ALIGN = -mstrict-align + +AArch32_64 = AArch64 +BOOTDIR = AArch64_boot +OUTPUT_DIR = build/release +OBJECT_DIR = build/obj +CROSS_COMPILE ?= aarch64-elf- + +MEMORY_DEF = memory_cx_ipl.def +FILE_NAME = $(OUTPUT_DIR)/ca76_loader + +INCLUDE_DIR = -I$(BOOTDIR) -I./include -I../V4H_Cx_Loader/include + +OUTPUT_FILE = $(FILE_NAME).axf + +#Object file +OBJ_FILE_BOOT = \ + $(OBJECT_DIR)/boot_mon.o \ + $(OBJECT_DIR)/stack.o + +SRC_FILE := \ + main.c \ + common/string.c \ + common/log/log.c \ + common/log/scif.c \ + common/timer/generic_timer.c \ + loader/loader_main_common.c \ + image_load/image_load.c + +SRC_FILE += \ + ip/emmc/emmc_boot.c \ + ip/emmc/emmc_cmd.c \ + ip/emmc/emmc_init.c \ + ip/emmc/emmc_interrupt.c \ + ip/emmc/emmc_mount.c \ + ip/emmc/emmc_multiboot.c \ + ip/emmc/emmc_read.c \ + ip/emmc/emmc_utility.c + +ifeq (${BOOT_MODE},SECURE) +SRC_FILE += secure/secure_boot.c \ + secure/src/comm_drv/icum_d_comm_pe.c \ + secure/src/icumif_lib/r_icumif.c \ + secure/shared/src/mem_info_def.c \ + secure/user_api/user_icumif_api.c + +INCLUDE_DIR += -Isecure/src/comm_drv -Isecure/src/icumif_lib \ + -Isecure/icumif -Isecure/include -Isecure/user_api \ + -Isecure/shared/src +endif + +ifeq ("$(DCACHE)", "1") + OBJ_FILE_BOOT += $(OBJECT_DIR)/d_armasm.o + SRC_FILE += vmsatable.c +endif + +ifeq ("$(BOOT)", "WRITER_WITH_CERT") + SRC_FILE += cert_param.c +endif + +################################################### +# Process access protection flag +# 0:Disable 1:Enable +ifndef ACC_PROT_ENABLE +ACC_PROT_ENABLE := 0 +$(eval $(call add_define,ACC_PROT_ENABLE)) +else + ifeq (${ACC_PROT_ENABLE},0) + $(eval $(call add_define,ACC_PROT_ENABLE)) + else ifeq (${ACC_PROT_ENABLE},1) + $(eval $(call add_define,ACC_PROT_ENABLE)) + else + $(error "Error:ACC_PROT_ENABLE=${ACC_PROT_ENABLE} is not supported.") + endif +endif + +# Debug build +DEBUG:=0 + +# Process DEBUG flag +$(eval $(call assert_boolean,DEBUG)) +$(eval $(call add_define,DEBUG)) +ifeq (${DEBUG},0) + $(eval $(call add_define,NDEBUG)) + CFLAGS += -Os +else + CFLAGS += -g +endif + +# timing measurement +ifeq ("$(MEASURE_TIME)", "") + MEASURE_TIME = 0 +else + $(eval $(call add_define,MEASURE_TIME)) + # Set log level to Error, so we dont waste time with unnecessary prints + LOG_LEVEL := 1 + SRC_FILE += \ + common/scmt_checkpoint.c \ + common/timer/scmt.c +endif + +ifneq ("$(BE_QUIET)", "") + $(eval $(call add_define,BE_QUIET)) +endif + +# Process OPTEE_LOAD_ENABLE flag +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef OPTEE_LOAD_ENABLE + OPTEE_LOAD_ENABLE := 1 + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else + ifeq (${OPTEE_LOAD_ENABLE},0) + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else ifeq (${OPTEE_LOAD_ENABLE},1) + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else + $(error "Error:OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.") + endif + endif +endif + +# Process BL2_LOAD_ENABLE flag +ifeq (${LSI},V4H) + ifndef BL2_LOAD_ENABLE + BL2_LOAD_ENABLE := 1 + $(eval $(call add_define,BL2_LOAD_ENABLE)) + else + ifeq (${BL2_LOAD_ENABLE},0) + $(eval $(call add_define,BL2_LOAD_ENABLE)) + else ifeq (${BL2_LOAD_ENABLE},1) + $(eval $(call add_define,BL2_LOAD_ENABLE)) + else + $(error "Error:BL2_LOAD_ENABLE=${BL2_LOAD_ENABLE} is not supported.") + endif + endif +endif + +# Process QNX_OS_LOAD_ENABLE flag +ifeq (${LSI},V4H) + ifndef QNX_OS_LOAD_ENABLE + QNX_OS_LOAD_ENABLE := 1 + $(eval $(call add_define,QNX_OS_LOAD_ENABLE)) + else + ifeq (${QNX_OS_LOAD_ENABLE},0) + $(eval $(call add_define,QNX_OS_LOAD_ENABLE)) + else ifeq (${QNX_OS_LOAD_ENABLE},1) + $(eval $(call add_define,QNX_OS_LOAD_ENABLE)) + else + $(error "Error:QNX_OS_LOAD_ENABLE=${QNX_OS_LOAD_ENABLE} is not supported.") + endif + endif +endif + +# Process LOG_LEVEL +ifndef LOG_LEVEL +LOG_LEVEL := 2 +endif +$(eval $(call add_define,LOG_LEVEL)) + +################################################### +#C compiler +CC = $(CROSS_COMPILE)gcc +#Assembler +AS = $(CROSS_COMPILE)as +#Linker +LD = $(CROSS_COMPILE)ld +#Liblary +AR = $(CROSS_COMPILE)ar +#Object dump +OBJDMP = $(CROSS_COMPILE)objdump +#Object copy +OBJCOPY = $(CROSS_COMPILE)objcopy +#clean +CL = rm -rf + +OBJ_FILE := $(addprefix $(OBJECT_DIR)/,$(patsubst %.c,%.o,$(SRC_FILE))) + +#Dependency File +DEPEND_FILE = $(patsubst %.lib, ,$(OBJ_FILE:%.o=%.d)) + +CFLAGS += -ffreestanding -Wall \ + -Wmissing-include-dirs \ + -std=c99 -c \ + -D__CX_IPL__ \ + $(DEFINES) + +LDFLAGS = --fatal-warnings -O1 -lm + +BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__ + +LIBS = -L$(subst libc.a, ,$(shell $(CC) -print-file-name=libc.a 2> /dev/null)) -lc +LIBS += -L$(subst libgcc.a, ,$(shell $(CC) -print-libgcc-file-name 2> /dev/null)) -lgcc + +################################################### +# Suffixes +.SUFFIXES : .s .c .o + +################################################### +# Command + +.PHONY: all +all: $(OBJECT_DIR) $(OUTPUT_DIR) $(OBJ_FILE_BOOT) $(OBJ_FILE) $(OUTPUT_FILE) + +#------------------------------------------ +# Make Directory +#------------------------------------------ +$(OBJECT_DIR): + -mkdir -p "$(OBJECT_DIR)" + +$(OUTPUT_DIR): + -mkdir -p "$(OUTPUT_DIR)" + +#------------------------------------------ +# Compile +#------------------------------------------ +$(OBJECT_DIR)/%.o:$(BOOTDIR)/%.s + $(V)$(AS) -g $(AS_NEON) --MD $(patsubst %.o,%.d,$@) \ + $(INCLUDE_DIR) $< -o $@ --defsym $(AArch32_64)=0 + +$(OBJECT_DIR)/%.o:%.c + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + $(V)$(CC) $(ALIGN) $(CPU) $(CC_NEON) -MMD -MP -c \ + $(INCLUDE_DIR) $< -o $@ -D$(AArch32_64)=0 $(DEFINES) $(CFLAGS) + +#------------------------------------------ +# Linker +#------------------------------------------ +$(OUTPUT_FILE): $(OBJ_FILE_BOOT) $(OBJ_FILE) $(MEMORY_DEF) + @echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' | \ + $(CC) $(CFLAGS) -xc - -o $(OBJECT_DIR)/build_message.o + + $(V)$(LD) $(OBJ_FILE_BOOT) $(OBJ_FILE) $(OBJECT_DIR)/build_message.o \ + -T '$(MEMORY_DEF)' \ + -o '$(OUTPUT_FILE)' \ + $(LDFLAGS) \ + -Map '$(FILE_NAME).map' \ + -static \ + $(LIBS) + + $(V)$(OBJCOPY) -O srec --srec-forceS3 "$(OUTPUT_FILE)" "$(FILE_NAME).srec" + $(V)$(OBJCOPY) -O binary "$(OUTPUT_FILE)" "$(FILE_NAME).bin" + $(V)$(OBJDMP) -d -S "$(OUTPUT_FILE)" > "$(FILE_NAME)_disasm.txt" + @chmod 644 $(FILE_NAME).* + +ifneq ("$(V)", "") + @echo "Build complete: $(OUTPUT_FILE)" + @echo "Output files:" + @echo " - $(FILE_NAME).srec" +endif + +.PHONY: clean +clean: + @$(CL) $(OBJECT_DIR)/* $(OUTPUT_DIR)/* + +distclean: clean + @$(CL) build + +-include $(DEPEND_FILE) diff --git a/IPL/Customer/Mobis/ca76_loader/cert_param.c b/IPL/Customer/Mobis/ca76_loader/cert_param.c new file mode 100644 index 0000000..80bdfb9 --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/cert_param.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +/* 0xE6300400 */ +const unsigned int __attribute__ ((section (".boot_param"))) boot_param = 0x00000000; +/* 0xE630048C */ +const unsigned int __attribute__ ((section (".cert_offset"))) reserved = 0x00000000; +/* 0xE63005D4 */ +const unsigned int __attribute__ ((section (".cert_addr"))) cert_addr = 0xE6304000; +/* 0xE63006E4 */ +const unsigned int __attribute__ ((section (".cert_size"))) cert_size = 0x00001000; +/* 0xE6301154 */ +const unsigned int __attribute__ ((section (".cert_addr2"))) cert_addr2 = 0xE6304000; +/* 0xE6301264 */ +const unsigned int __attribute__ ((section (".cert_size2"))) cert_size2 = 0x00001000; diff --git a/IPL/Customer/Mobis/ca76_loader/common b/IPL/Customer/Mobis/ca76_loader/common new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/ca76_loader/image_load b/IPL/Customer/Mobis/ca76_loader/image_load new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/ca76_loader/include/bit.h b/IPL/Customer/Mobis/ca76_loader/include/bit.h new file mode 100644 index 0000000..6ca2ca5 --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/include/bit.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef BIT_H +#define BIT_H + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#endif /* BIT_H */ diff --git a/IPL/Customer/Mobis/ca76_loader/include/vmsatable.h b/IPL/Customer/Mobis/ca76_loader/include/vmsatable.h new file mode 100644 index 0000000..cf1056f --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/include/vmsatable.h @@ -0,0 +1,12 @@ +/**********************************************************/ +/* Sample program : VMSA Table Header */ +/* File Name : vmsatable.h */ +/* Copyright (C) Renesas Electronics Corp. 2015. */ +/**********************************************************/ + +#ifndef _VMSATABLE_H_ +#define _VMSATABLE_H_ + +uint32_t SetVmsaTable(void); + +#endif diff --git a/IPL/Customer/Mobis/ca76_loader/ip b/IPL/Customer/Mobis/ca76_loader/ip new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/ca76_loader/loader b/IPL/Customer/Mobis/ca76_loader/loader new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/ca76_loader/main.c b/IPL/Customer/Mobis/ca76_loader/main.c new file mode 100644 index 0000000..876f596 --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/main.c @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2018-2023 Renesas Electronics Corporation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include "d_armasm.h" + +#include +#include +#include +#include +#include +#include +#if (BOOT_MODE == SECURE) +#include "secure_boot.h" +#endif /* BOOT_MODE == SECURE */ +/* Time analysis */ +#if (1 == (MEASURE_TIME)) + #include + #include +#else + #define scmt_wait_ticks(x) + #define store_time_checkpoint(x,y) + #define print_time_checkpoints(x) +#endif +#include + +#define _SECURE_BOOT_MARK (0x41DFFFF8U) +#define IS_SECURE_BOOT NORMAL_BOOT +#define OS_LOAD_FAIL (0xBAADF00DU) + +extern const uint8_t __RO_START__[1]; +extern const uint8_t __STACKS_END__[1]; +extern const char build_message[]; + +void Main(void) +{ + uint32_t ca_load_num; /* number of load for CA program */ + uint32_t loop; + uint32_t reg; /* store register value */ + int slot = 0; + __attribute__((unused))const char *str; +#if (BOOT_MODE == SECURE) + uint32_t bootmode; /* store boot mode */ +#endif /* BOOT_MODE == SECURE */ + LOAD_INFO li[MAX_PLACED]; + +#if (RCAR_LSI != RCAR_V4H) +#error "RCAR_V4H only" +#endif +#if (1 == (MEASURE_TIME)) + scmt_module_start(); + store_time_checkpoint("loader_main", 0); +#endif +/***************************************************************************** + * Initialize Hardware + *****************************************************************************/ + /* ip_control/ip_init() */ + scif_init(); + import_mmc_drv_obj(); + store_time_checkpoint("emmc_initialize", 0); + +/***************************************************************************** + * Output boot message + *****************************************************************************/ + NOTICE("CA76 Loader Program Rev.%s\n", IPL_VERSION); + NOTICE("%s\n", build_message); + + /* Get PRR */ + reg = mem_read32(PRR); + switch (reg & PRR_PRODUCT_MASK) { + case PRR_PRODUCT_V4H: + str = "V4H"; + break; + default: + str = "unknown"; + break; + } + NOTICE("PRR is R-Car %s Ver.%d.%d\n", str, + ((int)(reg & PRR_MAJOR_MASK) >> PRR_MAJOR_SHIFT) + + PRR_MAJOR_OFFSET, (int)(reg & PRR_MINOR_MASK)); + store_time_checkpoint("init_done", 0); + +/***************************************************************************** + * Load Certficate + *****************************************************************************/ + + /* Load content certificate */ + ca_load_num = mem_read32(CONTENT_CERT_DEST_ADDR); + + /* Get load information */ + load_init(li, ca_load_num); + +#if (BOOT_MODE == SECURE) + secureboot_init(); + + /* LCS judgement for secure boot */ + bootmode = judge_bootmode(); + + if (NORMAL_BOOT != bootmode) + { + /* Content cert certification */ + secureboot_verify(li, CA_OPTIONAL_ID, CA_OPTIONAL_ID + ca_load_num); + store_time_checkpoint("verify_cert_done", 0); +#ifdef MOBIS_PRK3 + /* because of SECURE_BOOT == 0x0, + we use NORMAL_BOOT as secure boot flag */ + mem_write32(_SECURE_BOOT_MARK, IS_SECURE_BOOT); +#endif + } +#endif /* BOOT_MODE == SECURE */ + +/***************************************************************************** + * Load CA Program#2--#8 + *****************************************************************************/ + reg = mem_read32(AB_INFO_FLAG_ADDR); + if (reg & AB_INFO_SELECT_2nd) + slot = 1; + NOTICE("slot: %d\n", slot); + + load_update_part_num(li, ca_load_num, slot); + + /* Start loading CA Program#n image */ + for (loop = 0U; loop < ca_load_num; loop++) + { +#ifdef MOBIS_PRK3 + if (loop == (CA_BL2_ID - CA_OPTIONAL_ID)) + continue; +#endif + /* Loading start */ + load_image(&li[CA_OPTIONAL_ID + loop]); + store_time_checkpoint("load_CA_#_done", li[CA_OPTIONAL_ID + loop].image_size); + +#if (BOOT_MODE == SECURE) + /* Decryption image and Image certification */ + if (NORMAL_BOOT != bootmode) + { +#ifdef MOBIS_PRK3 + if (loop == (CA_QNX_OS_ID - CA_OPTIONAL_ID)) { + int ret = secureboot_image(&li[CA_OPTIONAL_ID + loop], 0); + if (ret != 0) { + ERROR("secureboot_image failed for %s\n", li[CA_OPTIONAL_ID + loop].name); + mem_write32(_SECURE_BOOT_MARK, OS_LOAD_FAIL); + } + } else +#endif + secureboot_image(&li[CA_OPTIONAL_ID + loop], 1); + store_time_checkpoint("verify_CA_#_done", 0); + } +#endif /* BOOT_MODE == SECURE */ + } + + /* Set Secure Monitor parameter */ + smoni_set_param(li[CA_OPTIONAL_ID].boot_addr, /* BL31 */ + li[CA_OPTIONAL_ID + 1U].boot_addr, /* U-Boot */ + li[CA_OPTIONAL_ID + 2U].boot_addr); /* TEE-OS */ + +/***************************************************************************** + * Exit Hardware + *****************************************************************************/ + EMMC_ERROR_CODE result = EMMC_ERR; + + result = emmc_terminate(); + if(EMMC_SUCCESS != result) + { + ERROR("ip_release error (emmc_terminate).\n"); + panic; + } + + NOTICE("Load finish.(CA76 Loader)\n"); +/***************************************************************************** + * Jump to BL31 + *****************************************************************************/ + void (*bl31_func)(void); + + bl31_func = (void (*)(void))(uintptr_t)li[CA_OPTIONAL_ID].boot_addr; + store_time_checkpoint("Jump to BL31", 0); + print_time_checkpoints(); +#if !defined(BE_QUIET) && (LOG_LEVEL < LOG_NOTICE) + log_printf("%s\n", build_message); +#if (BOOT_MODE == SECURE) + if (NORMAL_BOOT != bootmode) { + log_printf("Secure boot(CA76 Loader)\n"); + } else { + log_printf("Normal boot(CA76 Loader)\n"); + } +#else + log_printf("Boot(CA76 Loader)\n"); +#endif +#endif + bl31_func(); /* Jump to BL31 */ +} diff --git a/IPL/Customer/Mobis/ca76_loader/memory_cx_ipl.def b/IPL/Customer/Mobis/ca76_loader/memory_cx_ipl.def new file mode 100644 index 0000000..a5f5c3b --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/memory_cx_ipl.def @@ -0,0 +1,62 @@ +MEMORY { + RAM (rwxa): ORIGIN = 0x41D00000, LENGTH = 0x000F8000 + MMU_CPU0 : ORIGIN = 0x41DF8000, LENGTH = 16K + SHARED_RAM (rwa): ORIGIN = 0x41C00000, LENGTH = 0x0000C000 + SHARED_SDRAM (rwa): ORIGIN = 0x41E00000, LENGTH = 0x00200000 +} + +SECTIONS +{ + .text : { + __RO_START__ = .; + *(.text*) + *(.rodata*) + . = NEXT(64); + __RO_END__ = .; + } > RAM + + .data : { + __DATA_START__ = .; + *(.data) + . = NEXT(64); + __DATA_END__ = .; + } > RAM + + __DATA_SIZE__ = SIZEOF(.data); + + .bss.SHARED_TOP : { + __SHARED_TOP_START__ = .; + *(.bss.SHARED_TOP) + *(.bss.SHARED_LCS) + *(.bss.SHARED_CMAC) + *(.bss.SHARED_HASH) + . = NEXT(0x00200000); + __SHARED__END__ = .; + } > SHARED_SDRAM + + .SHARED_RAM : { + __FWRAM_START__ = .; + . += 0; + . = NEXT(0x0000C000); + __FWRAM_END__ = .; + } > SHARED_RAM + + .bss : { + __BSS_START__ = .; + *(.bss) + *(COMMON) + . = NEXT(64); + __BSS_END__ = .; + } > RAM + + stacks (NOLOAD) : ALIGN(64) { + __STACKS_START__ = .; + KEEP(*(writer_stack)) + __STACKS_END__ = .; + } > RAM + + __BSS_SIZE__ = SIZEOF(.bss); +} + + MMU_BASE_CPU0 = ORIGIN(MMU_CPU0); + diff --git a/IPL/Customer/Mobis/ca76_loader/mk.sh b/IPL/Customer/Mobis/ca76_loader/mk.sh new file mode 100644 index 0000000..acf2c3a --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/mk.sh @@ -0,0 +1,50 @@ +#!/bin/bash +set -e +set -o pipefail +export CROSS_COMPILE=`pwd`/../gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf/bin/aarch64-none-elf- +export LANG=C + +_no_clean=0 +_loglevel=1 +_secure="SECURE" +_build_param="" +_default_b="LSI=V4H FORCE_115200=1 EMMC_TRANS_MODE=HS400 \ +OPTEE_LOAD_ENABLE=1 \ +BL2_LOAD_ENABLE=1 \ +QNX_OS_LOAD_ENABLE=1 \ +" +_echo="@" +while getopts "sl:pvcqh" opt; do + case $opt in + s) _secure="NORMAL" + ;; + l) _loglevel=$OPTARG + ;; + p) _build_param="${_build_param} MEASURE_TIME=1" + ;; + v) _echo="" + ;; + c) _no_clean=1 + ;; + q) _build_param="${_build_param} BE_QUIET=1" + ;; + h) + echo "usage: $0 [option]" + echo " -s toggle boot_mode (default: $_secure)" + echo " -l set loglevel (default: $_loglevel)" + echo " -p enable MEASURE_TIME" + echo " -q be quiet" + echo "" + echo " -c do not clean before build" + echo " -v build verbosely" + exit 0 + esac +done +shift $((OPTIND-1)) + +if [ $_no_clean -ne 1 ]; then + make clean +fi +BUILD_PARAM="${BUILD_PARAM} ${_build_param} LOG_LEVEL=$_loglevel" + +make ${_default_b} ${BUILD_PARAM} BOOT_MODE=$_secure V=$_echo $* diff --git a/IPL/Customer/Mobis/ca76_loader/secure b/IPL/Customer/Mobis/ca76_loader/secure new file mode 100644 index 0000000..e69de29 diff --git a/IPL/Customer/Mobis/ca76_loader/vmsatable.c b/IPL/Customer/Mobis/ca76_loader/vmsatable.c new file mode 100644 index 0000000..62c06b9 --- /dev/null +++ b/IPL/Customer/Mobis/ca76_loader/vmsatable.c @@ -0,0 +1,284 @@ +/**********************************************************/ +/* Sample program : VMSA Table Generate */ +/* File Name : vmsatable.c */ +/* Copyright (C) Renesas Electronics Corp. 2015. */ +/**********************************************************/ + +// #include "common.h" +#include +#include "vmsatable.h" +#include "d_armasm.h" + +#ifdef AArch64 +extern const char MMU_BASE_CPU0[]; +#endif +#ifdef AArch32 +#define MMU_BASE_CPU0 0xE6300000 +#endif + +#define TBL_SIZE 4096 +#define TBL_NUM (TBL_SIZE/8) + +#define Lvl1VmsaTbl ((uintptr_t)MMU_BASE_CPU0+0x0000) // +0kB +#define Lvl2VmsaTbl ((uintptr_t)MMU_BASE_CPU0+0x1000) // +4kB +#define Lvl3VmsaTbl ((uintptr_t)MMU_BASE_CPU0+0x2000) // +8kB + +#define Lvl1StartAddr (0x0000000000) +#define Lvl1BlockSize (0x0040000000) // 1GB +#define Lvl1BlockShift (30) // BIT30 +#define Lvl2StartAddr (0x00C0000000) +#define Lvl2BlockSize (0x0000200000) // 2MB +#define Lvl2BlockShift (21) // BIT21 +#define Lvl3StartAddr (0x00E6200000) +#define Lvl3BlockSize (0x0000001000) // 4KB +#define Lvl3BlockShift (12) // BIT12 + +#define BIT47_12 0x0000FFFFFFFFF000 + +typedef struct vmsaTable{ + uint64_t vAddr; + uint64_t pAddr; + uint64_t unit; + uint64_t upperAttr; + uint64_t lowerAttr; +}vmsaTable; + + +//------------------------------------------------------------------ +// Referenced: DDI0487A_f_armv8_arm.pdf +// D4.4 VMSAv8-64 translation table format descriptors +//------------------------------------------------------------------ + +#define ATTR_TBL 0x444444FF0C080400 // MAIR_EL1 +// // [63:56]Attr7=0x44 : ----------------- (Blank) +// // [55:48]Attr6=0x44 : ----------------- (Blank) +// // [47:40]Attr5=0x44 : NORMAL_NON_CACHEABLE Normal Memory Non-Cacheable +// // [39:32]Attr4=0x77 : NORMAL_WRITE_BACK Normal Memory Write-back transient +// // [31:24]Attr3=0x0C : DEVICE_GRE_MEM Device-GRE memory +// // [23:16]Attr2=0x08 : DEVICE_NGRE_MEM Device-nGRE memory +// // [15: 8]Attr1=0x04 : DEVICE_NGNRE_MEM Device-nGnRE memory +// // [ 7: 0]Attr0=0x00 : DEVICE_NGNRNE_MEM Device-nGnRnE memory + +// CPU0 VMSA table Level1 (4kB) +// Virtual address == Physical Address +const vmsaTable ArmVmsaTblLvl1Cpu0ForDDR4ch[] = { + // [MEM]Memory Address ...BIT[1:0]=01 + // [TBL]Next Level Table Address ...BIT[1:0]=11 + // Virtual Address Physical Address BLOCK Upper Lower Attr + // (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0] + // Next Level Table (1GBxN) [63:52] [11:00] [1:0][2:1] [2:0] + { 0x0000000000, 0x0000000000, 1, 0x000, 0x411 }, // [MEM]CS0/1,PCIe 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x0040000000, 0x0040000000, 1, 0x000, 0x411 }, // [MEM]DRAM 1st 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x0080000000, 0x0080000000, 1, 0x000, 0x411 }, // [MEM]DRAM 2nd 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x00C0000000, Lvl2VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 1GB 0 0 00 00 0 000 11 (Next Level Table) + { 0x0400000000, 0x0400000000, 4, 0x000, 0x411 }, // [MEM]DDR0 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient) + { 0x0500000000, 0x0500000000, 4, 0x000, 0x411 }, // [MEM]DDR1 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient) + { 0x0600000000, 0x0600000000, 4, 0x000, 0x411 }, // [MEM]DDR2 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient) + { 0x0700000000, 0x0700000000, 4, 0x000, 0x411 }, // [MEM]DDR3 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient) + { 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ---------- +}; + +// CPU0 VMSA table Level1 (4kB) +// Virtual address == Physical Address +const vmsaTable ArmVmsaTblLvl1Cpu0ForDDR2ch[] = { + // [MEM]Memory Address ...BIT[1:0]=01 + // [TBL]Next Level Table Address ...BIT[1:0]=11 + // Virtual Address Physical Address BLOCK Upper Lower Attr + // (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0] + // Next Level Table (1GBxN) [63:52] [11:00] [1:0][2:1] [2:0] + { 0x0000000000, 0x0000000000, 1, 0x000, 0x411 }, // [MEM]CS0/1,PCIe 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x0040000000, 0x0040000000, 1, 0x000, 0x411 }, // [MEM]DRAM 1st 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x0080000000, 0x0080000000, 1, 0x000, 0x411 }, // [MEM]DRAM 2nd 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x00C0000000, Lvl2VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 1GB 0 0 00 00 0 000 11 (Next Level Table) + { 0x0400000000, 0x0400000000, 4, 0x000, 0x411 }, // [MEM]DDR0 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient) + { 0x0600000000, 0x0600000000, 4, 0x000, 0x411 }, // [MEM]DDR2 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient) + { 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ---------- +}; + +// CPU0 VMSA table Level1 (4kB) +// Virtual address == Physical Address +const vmsaTable ArmVmsaTblLvl1Cpu0ForDDR1ch[] = { + // [MEM]Memory Address ...BIT[1:0]=01 + // [TBL]Next Level Table Address ...BIT[1:0]=11 + // Virtual Address Physical Address BLOCK Upper Lower Attr + // (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0] + // Next Level Table (1GBxN) [63:52] [11:00] [1:0][2:1] [2:0] + { 0x0000000000, 0x0000000000, 1, 0x000, 0x411 }, // [MEM]CS0/1,PCIe 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x0040000000, 0x0040000000, 1, 0x000, 0x411 }, // [MEM]DRAM 1st 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x0080000000, 0x0080000000, 1, 0x000, 0x411 }, // [MEM]DRAM 2nd 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x00C0000000, Lvl2VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 1GB 0 0 00 00 0 000 11 (Next Level Table) + { 0x0400000000, 0x0400000000, 4, 0x000, 0x411 }, // [MEM]DDR0 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient) + { 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ---------- +}; + +// CPU0 VMSA table Level2 (4kB) +// Virtual address == Physical Address +const vmsaTable ArmVmsaTblLvl2Cpu0[] = { + // [MEM]Memory Address ...BIT[1:0]=01 + // [TBL]Next Level Table Address ...BIT[1:0]=11 + // Virtual Address Physical Address BLOCK Upper Lower Attr + // (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0] + // Next Level Table (2MBxN) [63:52] [11:00] [1:0][2:1] [2:0] + { 0x00E6200000, Lvl3VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 2MB 0 0 00 00 0 000 11 (Next Level Table) + { 0x00EB200000, 0x00EB200000, 1, 0x000, 0x411 }, // [MEM]RT-SRAM 2MB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) @V3U + { 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ---------- +}; + +#ifdef SYSTEM_DEF_FALCON +// CPU0 VMSA table Level3 (4kB) @V3U CPUボード到ç€å¾Œã«ä¸Šã®vmsaTable ArmVmsaTblLvl3Cpu0[]ã¨å…¥ã‚Œæ›¿ãˆ +// Virtual address == Physical Address +const vmsaTable ArmVmsaTblLvl3Cpu0[] = { + // [INV]Invalid ...BIT[1:0]=x0 + // [RES]Reserved ...BIT[1:0]=01 + // [MEM]Memory Address ...BIT[1:0]=11 <-- Select + // Virtual Address Physical Address BLOCK Upper Lower Attr + // (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0] + // Next Level Table (4KBxN) [63:52] [11:00] [1:0][2:1] [2:0] + { 0x00E6200000, 0x00E6200000, 256, 0x000, 0x403 }, // [MEM]IPs 1MB 0 1 00 00 0 000 11 (Device-nGnRnE memory) + { 0x00E6300000, 0x00E6300000, 256, 0x000, 0x413 }, // [MEM]SystemRAM 1MB 0 1 00 00 0 100 11 (Normal Memory Write-back transient) @V3U + { 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ---------- +}; + +#else +// CPU0 VMSA table Level3 (4kB) @V3H +// Virtual address == Physical Address +const vmsaTable ArmVmsaTblLvl3Cpu0[] = { + // [INV]Invalid ...BIT[1:0]=x0 + // [RES]Reserved ...BIT[1:0]=01 + // [MEM]Memory Address ...BIT[1:0]=11 <-- Select + // Virtual Address Physical Address BLOCK Upper Lower Attr + // (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0] + // Next Level Table (4KBxN) [63:52] [11:00] [1:0][2:1] [2:0] + { 0x00E6200000, 0x00E6200000, 256, 0x000, 0x403 }, // [MEM]IPs 1MB 0 1 00 00 0 000 11 (Device-nGnRnE memory) + { 0x00E6300000, 0x00E6300000, 48, 0x000, 0x413 }, // [MEM]SystemRAM 192KB 0 1 00 00 0 100 11 (Normal Memory Write-back transient) + { 0x00E6330000, 0x00E6330000, 48, 0x000, 0x413 }, // [MEM]SystemRAM 192KB 0 1 00 00 0 100 11 (Normal Memory Write-back transient) + { 0x00E6360000, 0x00E6360000, 160, 0x000, 0x403 }, // [MEM]SystemRAM 640KB 0 1 00 00 0 000 11 (Device-nGnRnE memory) + { 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ---------- +}; +#endif + +static void MakeVmsaTable(uint64_t *vmsaTblSadd, vmsaTable *vmsaSrcTbl, uint64_t startAddr, uint64_t blockShift); + +uint32_t SetVmsaTable(void) +{ + uint64_t *vmsaTblSadd; + vmsaTable *vmsaSrcTbl; + uint64_t startAddr; + uint64_t blockShift; + + // TCR_EL3, Translation Control Register (EL3) + // [31] Reserved-1: 1 + // [30:29] Reserved-0: 0 + // + // When ARMv8.2-TTPBHA is implemented + // [28] HWU62 : 0 :Bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. + // [27] HWU61 : 0 :Bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. + // [26] HWU60 : 0 :Bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. + // [25] HWU59 : 0 :Bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. + // -The Effective value of this field is 0 if the value of TCR_EL3.HPD is 0. + // -This field resets to an architecturally UNKNOWN value. + // [24] HPD : 0 :Hierarchical Permission Disables. + // Otherwise + // [28:24] Reserved-0: 00000 + // + // [23] Reserved-1: 1 + // When ARMv8.1-TTHM is implemented + // [22] HD : 0 :Hardware management of dirty state in stage 1 translations from EL3. + // [21] HA : 0 :Hardware Access flag update in stage 1 translations from EL3. + // Otherwise + // [22:21] Reserved-0: 00 + // + // [20] TBI : 0 : Top Byte used in the address calculation. + // [19] Reserved-0: 0 + // [18:16] PS : 001 : Physical Address Size 000=32bit, 001=36bit, 010=40bit, 011=42bit, 100=44bit, 101=48bit + // [15:14] TG0 : 00 : translation table 00=4KB, 01=64KB, 10=16KB + // [13:12] SH0 : 10 : translation table memory 00=Non-shareable, 10=Outer Shareable, 11=Inner Shareable + // [11:10] ORGN0 : 01 : Outer 01=Write-Back Write-Allocate Cacheable + // [09:08] IRGN0 : 01 : Inner 01=Write-Back Write-Allocate Cacheable + // [07:06] Reserved : 00 + // [05:00] T0SZ : 011100 : The region size is 2^(64-T0SZ) byte. 2^(64-28)=2^36=0x10_0000_0000 + WriteTCR_EL3(0x8081251C); + WriteMAIR_EL3(ATTR_TBL); + WriteTTBR0_EL3((uint64_t)Lvl1VmsaTbl); // ASID=0 +#ifdef SYSTEM_DEF_FALCON + // VMSA Table Level1 for Main + vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR4ch; +#else + // VMSA Table Level1 for Main +// if( CHK_H3 && (!CHK_H3N) ){ vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR4ch; } // 4ch : H3 +// else if( CHK_M3 ){ vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR2ch; } // 2ch : M3 +// else if( CHK_H3N ){ vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR2ch; } // 2ch : H3N +// else { vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR1ch; } // 1ch : M3N,V3H,V3M,D3,E3 +#endif + vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR4ch; + + vmsaTblSadd = (uint64_t*)Lvl1VmsaTbl; + startAddr = Lvl1StartAddr; + blockShift = Lvl1BlockShift; + MakeVmsaTable(vmsaTblSadd, vmsaSrcTbl, startAddr, blockShift); + + // VMSA Table Level2 for IPs + vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl2Cpu0; + vmsaTblSadd = (uint64_t*)Lvl2VmsaTbl; + startAddr = Lvl2StartAddr; + blockShift = Lvl2BlockShift; + MakeVmsaTable(vmsaTblSadd, vmsaSrcTbl, startAddr, blockShift); + + // VMSA Table Level3 for IPs + vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl3Cpu0; + vmsaTblSadd = (uint64_t*)Lvl3VmsaTbl; + startAddr = Lvl3StartAddr; + blockShift = Lvl3BlockShift; + MakeVmsaTable(vmsaTblSadd, vmsaSrcTbl, startAddr, blockShift); + + return 0; +} + +static void MakeVmsaTable(uint64_t *vmsaTblSadd, vmsaTable *vmsaSrcTbl, uint64_t startAddr, uint64_t blockShift) +{ + uint32_t i,j; + uint64_t setData; + uint64_t *setAddr; + uint64_t upperAttr; // Attribute fields for VMSAv8-64 ([63:52]) + uint64_t lowerAttr; // Attribute fields for VMSAv8-64 ([11:0]) + uint64_t virAdd; + uint64_t phyAdd; + uint64_t block; + uint64_t blockSize; + + blockSize = (1<>(blockShift-3))); + setData = vmsaSrcTbl[i].upperAttr<<52; // [63:52] + setData |= phyAdd; // [47:12] + setData |= vmsaSrcTbl[i].lowerAttr; // [11:00] + + block = vmsaSrcTbl[i].unit; + for(j=0; j disabled) + STR R1, [R0] +.endif + + +.IF CACHE_MODE == ENABLE +;#################################################################################################### +;##### enable I cache +;#################################################################################################### + +CACHE_ENABLE: + MRC p15, 0, R1, c1, c0, 0 ;# Read System Control Register configuration data + ORR R1, R1, #0x1 <<12 ;# instruction cache enable + MCR p15, 0, r0, c7, c5, 0 ;# Invalidate entire instruction cache + MCR p15, 0, R1, c1, c0, 0 ;# enabled instruction cache + ISB + B CACHE_ENABLE_END +.ENDIF + +CACHE_ENABLE_END: + + /* clear bss section */ + mov r0, #0x0 + ldr r1, =__BSS_START__ + ldr r2, =__BSS_SIZE__ +bss_loop: + subs r2, r2, #4 + bcc bss_end + str r0, [r1, +r2] + b bss_loop +bss_end: + +.ifdef Area0Boot + /* copy data section */ + ldr r0, =__DATA_COPY_START__ + ldr r1, =__DATA_START__ + ldr r2, =__DATA_SIZE__ +data_loop: + subs r2, r2, #4 + bcc data_end + ldr r3, [r0, +r2] + str r3, [r1, +r2] + b data_loop +data_end: +.endif + + BL InitScif + +;#################################################################################################### +;#### go to main +;#################################################################################################### +Jmp_MAIN_C: + BL Main + + .END diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/AArch32_boot/stack.s b/IPL/SDK/v3h/src/Dummy_CA53_Program/AArch32_boot/stack.s new file mode 100644 index 0000000..a450de9 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/AArch32_boot/stack.s @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + + + .section writer_stack, "aw", %nobits + .align 5 +stacks: + .space (8*1024), 0 + + .end diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/AArch64_boot/boot_mon.h b/IPL/SDK/v3h/src/Dummy_CA53_Program/AArch64_boot/boot_mon.h new file mode 100644 index 0000000..8b3c7ae --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/AArch64_boot/boot_mon.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +;#RWDT +;#R-CarH3 77. RCLK Watchdog Timer +.EQU RWDT_RWTCNT , 0xE6020000 ;#RCLK watchdog timer counter +.EQU RWDT_RWTCSRA , 0xE6020004 ;#RCLK watchdog timer control/status register A +.EQU RWDT_RWTCSRB , 0xE6020008 ;#RCLK watchdog timer control/status register B + +;#SystemWDT +;#R-CarH3 78. System Watchdog Timer +.EQU SYSWDT_WTCNT , 0xE6030000 ;#watchdog timer counter +.EQU SYSWDT_WTCSRA , 0xE6030004 ;#watchdog timer control/status register A +.EQU SYSWDT_WTCSRB , 0xE6030008 ;#watchdog timer control/status register B + +.EQU PRR , 0xFFF00044 ;#Product Register diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/AArch64_boot/boot_mon.s b/IPL/SDK/v3h/src/Dummy_CA53_Program/AArch64_boot/boot_mon.s new file mode 100644 index 0000000..27e9448 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/AArch64_boot/boot_mon.s @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +;# W0-W30 : 32bit Register (W30=Link Register) +;# X0-X30 : 64bit Register (X30=Link Register) +;# WZR : 32bit Zero Register +;# XZR : 64bit Zero Register +;# WSP : 32bit Stack Pointer +;# SP : 64bit Stack Pointer + + .INCLUDE "boot_mon.h" + .ALIGN 4 + +;# Initialize registers +Register_init: + LDR X0, =0 + LDR X1, =0 + LDR X2, =0 + LDR X3, =0 + LDR X4, =0 + LDR X5, =0 + LDR X6, =0 + LDR X7, =0 + LDR X8, =0 + LDR X9, =0 + LDR X10, =0 + LDR X11, =0 + LDR X12, =0 + LDR X13, =0 + LDR X14, =0 + LDR X15, =0 + LDR X16, =0 + LDR X17, =0 + LDR X18, =0 + LDR X19, =0 + LDR X20, =0 + LDR X21, =0 + LDR X22, =0 + LDR X23, =0 + LDR X24, =0 + LDR X25, =0 + LDR X26, =0 + LDR X27, =0 + LDR X28, =0 + LDR X29, =0 + LDR X30, =0 + +Set_EnableRAM: + LDR X0, =0xE67F0018 + LDR W1, =0x00000001 ;#Enable DRAM/SECRAM/PUBRAM + STR W1, [X0] + +;# Loader + LDR x0, =__STACKS_END__ + MSR SP_EL0,x0 + MSR SP_EL1,x0 + MSR SP_EL2,x0 + MOV sp,x0 + MSR ELR_EL1,x0 + MSR ELR_EL2,x0 + MSR ELR_EL3,x0 + MSR SPSR_EL1,x0 + MSR SPSR_EL2,x0 + MSR SPSR_EL3,x0 + + +;# Board Initialize +.ifdef Area0Boot + +Init_set_WDT: + LDR W0, =RWDT_RWTCSRA + LDR W1, =0xA5A5A500 ;#Timer disabled + STR W1, [X0] + +Init_set_SYSWDT: + LDR W0, =SYSWDT_WTCSRA + LDR W1, =0xA5A5A500 ;#Timer disabled (Enable -> disabled) + STR W1, [X0] + +.endif + + + +;# Enable cache +;# mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el3 + orr x0, x0, #(0x1 << 12) + orr x0, x0, #(0x1 << 1) + orr x0, x0, #(0x1 << 3) + msr sctlr_el3, x0 + isb + + + /* clear bss section */ + mov X0, #0x0 + ldr X1, =__BSS_START__ + ldr X2, =__BSS_SIZE__ +bss_loop: + subs X2, X2, #4 + bcc bss_end + str W0, [X1, X2] + b bss_loop +bss_end: + +.ifdef Area0Boot + /* copy data section */ + ldr X0, =__DATA_COPY_START__ + ldr X1, =__DATA_START__ + ldr X2, =__DATA_SIZE__ +data_loop: + subs X2, X2, #4 + bcc data_end + ldr W3, [X0, X2] + str W3, [X1, X2] + b data_loop +.endif + +data_end: + + BL InitScif + + BL Main + + .END + diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/AArch64_boot/stack.s b/IPL/SDK/v3h/src/Dummy_CA53_Program/AArch64_boot/stack.s new file mode 100644 index 0000000..a450de9 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/AArch64_boot/stack.s @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + + + .section writer_stack, "aw", %nobits + .align 5 +stacks: + .space (8*1024), 0 + + .end diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/LICENSE.md b/IPL/SDK/v3h/src/Dummy_CA53_Program/LICENSE.md new file mode 100644 index 0000000..af0ee77 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/LICENSE.md @@ -0,0 +1 @@ +Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/cert_param.c b/IPL/SDK/v3h/src/Dummy_CA53_Program/cert_param.c new file mode 100644 index 0000000..80bdfb9 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/cert_param.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +/* 0xE6300400 */ +const unsigned int __attribute__ ((section (".boot_param"))) boot_param = 0x00000000; +/* 0xE630048C */ +const unsigned int __attribute__ ((section (".cert_offset"))) reserved = 0x00000000; +/* 0xE63005D4 */ +const unsigned int __attribute__ ((section (".cert_addr"))) cert_addr = 0xE6304000; +/* 0xE63006E4 */ +const unsigned int __attribute__ ((section (".cert_size"))) cert_size = 0x00001000; +/* 0xE6301154 */ +const unsigned int __attribute__ ((section (".cert_addr2"))) cert_addr2 = 0xE6304000; +/* 0xE6301264 */ +const unsigned int __attribute__ ((section (".cert_size2"))) cert_size2 = 0x00001000; diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/common.c b/IPL/SDK/v3h/src/Dummy_CA53_Program/common.c new file mode 100644 index 0000000..5459bb3 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/common.c @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#include "types.h" +#include "common.h" +#include "devdrv.h" + +__attribute__((aligned(32))) uint8_t gCOMMAND_Area[COMMAND_BUFFER_SIZE]; + +/************************************************************************/ +/*NAME : PutMes */ +/************************************************************************/ +int32_t PutMess(const char *const mess[]) +{ + int32_t i=0; + while(mess[i]){ + PutStr(mess[i],ENB_RTN); + i++; + } + return(0); +} + +/************************************************************************/ +/*NAME : PutStr */ +/************************************************************************/ +int32_t PutStr(const char *str,char rtn) +{ + while(*str){ + PutChar(*str); + str++; + } + if(rtn == 1){ + PutChar(CR_CODE); + PutChar(LF_CODE); + } + return(0); + +} + + +/************************************************************************/ +/*NAME : Hex2Ascii */ +/************************************************************************/ +uint32_t Hex2Ascii(int32_t hexdata,char *str,int32_t *chcnt) +{ + + long i; + char ch; + + for( i = 7; i >= 0; i-- ) { + ch = (char)(hexdata & 0x0F); + if( ch > 9 ) + ch += 7; + ch += 0x30; + hexdata >>= 4; + + *(str + i) = ch; + } + *(str + 8) = '\0'; + *chcnt = 8; + + return 0U; +} + + +uint32_t Hex2DecAscii(int32_t hexdata,char *str,int32_t *chcnt) +{ + char Count; + char countstart; + uint32_t Compdata; + + unsigned char dataB; + uint32_t dataL; + uint32_t i; + + Count = 0; + countstart = 0x0; + dataB = 0; + dataL = 10; + while( dataL > 0 ){ + Compdata = 1; + i = 1; + while( i < dataL ){ + Compdata *= 10; + i++; + } + while( hexdata >= Compdata ){ + hexdata -= Compdata; + dataB++; + countstart = 1; + } + if( countstart == 1 ){ + *(str++) = dataB + '0'; + Count++; + } + dataB = 0; + dataL--; + } + + if(Count==0){ + *str = '0'; + str++; + Count++; + } + *str = '\0'; + *chcnt = Count; + return(0); + +} + + +/************************************************************************/ + +void ChgLtl2Lrg(char *str) +{ + while(*str!=0){ + if(('a' <= *str)&&(*str<='z')) + *str -= 0x20; + str++; + } +} +char HexAscii2Data(unsigned char *buf,uint32_t *data) +{ + char chCnt; + uint32_t tmpData; + *data = 0; + chCnt = 0; + + ChgLtl2Lrg(buf); + + if(*buf=='@') return(3); + while(*buf){ + if(('0'<= *buf)&&(*buf<='9')){ + tmpData = (uint32_t)(*buf - '0'); + *data <<= 4; + *data |= tmpData; + }else if(('A'<= *buf)&&(*buf<='F')){ + tmpData = (uint32_t)(*buf - 55); + *data <<= 4; + *data |= tmpData; + }else{ + return(1); + } + buf++; + chCnt++; + if(chCnt>(SIZE_32BIT*2)) return(1); + } + return(0); +} + +char HexAscii2Data_64(unsigned char *buf,uintptr_t *data) +{ + char chCnt; + uintptr_t tmpData; + *data = 0; + chCnt = 0; + + ChgLtl2Lrg(buf); + + if(*buf=='@') return(3); + while(*buf){ + if(('0'<= *buf)&&(*buf<='9')){ + tmpData = (uintptr_t)(*buf - '0'); + *data <<= 4; + *data |= tmpData; + }else if(('A'<= *buf)&&(*buf<='F')){ + tmpData = (uintptr_t)(*buf - 55); + *data <<= 4; + *data |= tmpData; + }else{ + return(1); + } + buf++; + chCnt++; + if(chCnt>(CPU_BYTE_SIZE*2)) return(1); + } + return(0); +} + + + +char Data2HexAscii(uint32_t data,char *buf,char size) +{ + char loopCnt,i; + uint32_t tmpData; + switch(size){ + case SIZE_8BIT: + data <<= (SIZE_32BIT*8-8); + loopCnt=2; + break; + case SIZE_16BIT: + data <<= (SIZE_32BIT*8-16); + loopCnt=4; + break; + case SIZE_32BIT: + data <<= (SIZE_32BIT*8-32); + loopCnt=8; + break; + } + for(i=0;i> (SIZE_32BIT*8-4)); + if(tmpData < 0x0a){ /* case 1 to 9 */ + *buf = (char)(tmpData + '0'); + }else{ /* case A to F */ + *buf = (char)(tmpData + 55); + } + data <<= 4; + } + *buf = 0; + return(0); +} + +char Data2HexAscii_64(uintptr_t data,char *buf,char size) +{ + char loopCnt,i; + uintptr_t tmpData; + switch(size){ + case SIZE_8BIT: + data <<= (CPU_BYTE_SIZE*8-8); + loopCnt=2; + break; + case SIZE_16BIT: + data <<= (CPU_BYTE_SIZE*8-16); + loopCnt=4; + break; + case SIZE_32BIT: + data <<= (CPU_BYTE_SIZE*8-32); + loopCnt=8; + break; +#ifdef AArch64 + case SIZE_64BIT: + data <<= (CPU_BYTE_SIZE*8-64); + loopCnt=16; + break; +#endif + } + for(i=0;i> (CPU_BYTE_SIZE*8-4)); + if(tmpData < 0x0a){ /* case 1 to 9 */ + *buf = (char)(tmpData + '0'); + }else{ /* case A to F */ + *buf = (char)(tmpData + 55); + } + data <<= 4; + } + *buf = 0; + return(0); +} + +void SoftDelay(uint32_t loop) +{ + uint32_t i; + for(i=0;i + + +#ifdef AArch64 +//typedef uint64_t uintptr_t; +#define CPU_BYTE_SIZE SIZE_64BIT +#endif + +#ifdef AArch32 +//typedef uint32_t uintptr_t; +#define CPU_BYTE_SIZE SIZE_32BIT +#endif + + +#define DIS_RTN 0 /* Disable Return */ +#define ENB_RTN 1 /* Enable Return */ +#define OK 0x1 + +#ifndef NULL +#define NULL 0x0 +#endif + +#define INT_CODE 0x25 /* "%" */ +#define BS_CODE 0x08 /* "BS" */ +#define CR_CODE 0x0d /* "CR" */ +#define SP_CODE 0x20 /* "LF" */ +#define LF_CODE 0x0a /* "LF" */ + +#define SIZE_8BIT 1 // Old name : BYTE_SIZE +#define SIZE_16BIT 2 // Old name : WORD_SIZE +#define SIZE_32BIT 4 // Old name : LONG_SIZE +#define SIZE_64BIT 8 // New + +#define COMMAND_BUFFER_SIZE 1024 + + +/**************************** + Module Proto Type * +****************************/ +int32_t PutMess(const char *const mess[]); +int32_t PutStr(const char *str,char rtn); +uint32_t Hex2Ascii(int32_t hexdata,char *str,int32_t *chcnt); +uint32_t Hex2DecAscii(int32_t hexdata,char *str,int32_t *chcnt); +void ChgLtl2Lrg(char *str); +char HexAscii2Data(unsigned char *buf,uint32_t *data); +char HexAscii2Data_64(unsigned char *buf,uintptr_t *data); +char Data2HexAscii(uint32_t data,char *buf,char size); +char Data2HexAscii_64(uintptr_t data,char *buf,char size); +void SoftDelay(uint32_t roop); + +#endif diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/include/devdrv.h b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/devdrv.h new file mode 100644 index 0000000..b6906c5 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/devdrv.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef DEVDRV_H +#define DEVDRV_H + +int32_t PutChar(char outChar); +int32_t WaitPutCharSendEnd(void); + +#endif /* DEVDRV_H */ diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/include/init_scif.h b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/init_scif.h new file mode 100644 index 0000000..4a87d81 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/init_scif.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef INITSCIF_H +#define INITSCIF_H + +void InitScif(void); + +#endif /* INITSCIF_H */ diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/include/main.h b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/main.h new file mode 100644 index 0000000..1cc16c4 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/main.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef MAIN_H +#define MAIN_H + +void Main(void); + +#endif /* MAIN_H */ diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/include/reg_rcargen3.h b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/reg_rcargen3.h new file mode 100644 index 0000000..322fa7b --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/reg_rcargen3.h @@ -0,0 +1,590 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef REG_RCARGEN3_H +#define REG_RCARGEN3_H + +//CPG +#define CPG_CPGWPCR 0xE6150904 // R/W 32 CPG Write Protect Control Register +#define CPG_CPGWPR 0xE6150900 // R/W 32 CPG Write Protect Register +#define CPG_FRQCRB 0xE6150004 // R/W 32 Frequency control register B +#define CPG_FRQCRC 0xE61500E0 // R/W 32 Frequency control register C +#define CPG_PLLECR 0xE61500D0 // R/W 32 PLL Enable Control Register +#define CPG_PLL0CR 0xE61500D8 // R/W 32 PLL0 control register +#define CPG_PLL2CR 0xE615002C // R/W 32 PLL2 control register +#define CPG_PLL3CR 0xE61500DC // R/W 32 PLL2 control register +#define CPG_PLL0STPCR 0xE61500F0 // R/W 32 PLL0 Stop Condition Register +#define CPG_PLL2STPCR 0xE61500F8 // R/W 32 PLL2 Stop Condition Register +#define CPG_PLL3STPCR 0xE61500FC // R/W 32 PLL3 Stop Condition Register +#define CPG_PLL4STPCR 0xE61501F8 // R/W 32 PLL4 Stop Condition Register +#define CPG_SD0CKCR 0xE6150074 // R/W 32 SD-IF0 clock frequency control register +#define CPG_SD1CKCR 0xE6150078 // R/W 32 SD-IF1 clock frequency control register +#define CPG_SD2CKCR 0xE6150268 // R/W 32 SD-IF2 clock frequency control register +#define CPG_SD3CKCR 0xE615026C // R/W 32 SD-IF3 clock frequency control register +#define CPG_RPCCKCR 0xE6150238 // R/W 32 RPC clock frequency control register +#define CPG_SSPSRCCKCR 0xE6150248 // R/W 32 SSPSRC clock frequency control register +#define CPG_SSPRSCKCR 0xE615024C // R/W 32 SSPRS clock frequency control register +#define CPG_CANFDCKCR 0xE6150244 // R/W 32 CAN-FD clock frequency control register +#define CPG_MSOCKCR 0xE6150014 // R/W 32 MSIOF clock frequency control register +#define CPG_HDMICKCR 0xE6150250 // R/W 32 HDMI-IF clock frequency control register +#define CPG_CSI0CKCR 0xE615000C // R/W 32 CSI0 clock frequency control register +#define CPG_CSIREFCKCR 0xE6150034 // R/W 32 CSIREF clock frequency control register +#define CPG_RCKCR 0xE6150240 // R/W 32 RCLK frequency control register +#define CPG_DVFSCR0 0xE6150058 // R/W 32 DVFS control register 0 +#define CPG_DVFSCR1 0xE615005C // R/W 32 DVFS control register 1 +#define CPG_FSAPBR 0xE6150700 // R/W 32 Functional safety of APB bus interface register +#define CPG_FSCLKCSR 0xE6150704 // R/W 32 Functional safety of clocks control/status register +#define CPG_FSCNTCHKH0 0xE6150710 // R/W 32 Functional safety of clocks counter check H register 0 +#define CPG_FSCNTCHKH1 0xE6150714 // R/W 32 Functional safety of clocks counter check H register 1 +#define CPG_FSCNTCHKH2 0xE6150718 // R/W 32 Functional safety of clocks counter check H register 2 +#define CPG_FSCNTCHKH3 0xE615071C // R/W 32 Functional safety of clocks counter check H register 3 +#define CPG_FSCNTCHKH4 0xE6150720 // R/W 32 Functional safety of clocks counter check H register 4 +#define CPG_FSCNTCHKH5 0xE6150724 // R/W 32 Functional safety of clocks counter check H register 5 +#define CPG_FSCNTCHKH6 0xE6150728 // R/W 32 Functional safety of clocks counter check H register 6 +#define CPG_FSCNTCHKL0 0xE6150730 // R/W 32 Functional safety of clocks counter check L register 0 +#define CPG_FSCNTCHKL1 0xE6150734 // R/W 32 Functional safety of clocks counter check L register 1 +#define CPG_FSCNTCHKL2 0xE6150738 // R/W 32 Functional safety of clocks counter check L register 2 +#define CPG_FSCNTCHKL3 0xE615073C // R/W 32 Functional safety of clocks counter check L register 3 +#define CPG_FSCNTCHKL4 0xE6150740 // R/W 32 Functional safety of clocks counter check L register 4 +#define CPG_FSCNTCHKL5 0xE6150744 // R/W 32 Functional safety of clocks counter check L register 5 +#define CPG_FSCNTCHKL6 0xE6150748 // R/W 32 Functional safety of clocks counter check L register 6 +#define CPG_FSCNTMON0 0xE6150750 // R 32 Functional safety of clocks monitor register 0 +#define CPG_FSCNTMON1 0xE6150754 // R 32 Functional safety of clocks monitor register 1 +#define CPG_FSCNTMON2 0xE6150758 // R 32 Functional safety of clocks monitor register 2 +#define CPG_FSCNTMON3 0xE615075C // R 32 Functional safety of clocks monitor register 3 +#define CPG_FSCNTMON4 0xE6150760 // R 32 Functional safety of clocks monitor register 4 +#define CPG_FSCNTMON5 0xE6150764 // R 32 Functional safety of clocks monitor register 5 +#define CPG_FSCNTMON6 0xE6150768 // R 32 Functional safety of clocks monitor register 6 +#define CPG_FSRCHKRA0 0xE6150A00 // R 32 Functional safety reset check register A 0 +#define CPG_FSRCHKRA1 0xE6150A04 // R 32 Functional safety reset check register A 1 +#define CPG_FSRCHKRA2 0xE6150A08 // R 32 Functional safety reset check register A 2 +#define CPG_FSRCHKRA3 0xE6150A0C // R 32 Functional safety reset check register A 3 +#define CPG_FSRCHKRA4 0xE6150A10 // R 32 Functional safety reset check register A 4 +#define CPG_FSRCHKRA5 0xE6150A14 // R 32 Functional safety reset check register A 5 +#define CPG_FSRCHKRA6 0xE6150A18 // R 32 Functional safety reset check register A 6 +#define CPG_FSRCHKRA7 0xE6150A1C // R 32 Functional safety reset check register A 7 +#define CPG_FSRCHKRA8 0xE6150A20 // R 32 Functional safety reset check register A 8 +#define CPG_FSRCHKRA9 0xE6150A24 // R 32 Functional safety reset check register A 9 +#define CPG_FSRCHKRA10 0xE6150A28 // R 32 Functional safety reset check register A 10 +#define CPG_FSRCHKRA11 0xE6150A2C // R 32 Functional safety reset check register A 11 +#define CPG_FSRCHKRA12 0xE6150A30 // R 32 Functional safety reset check register A 12 +#define CPG_FSRCHKRA13 0xE6150A34 // R 32 Functional safety reset check register A 13 +#define CPG_FSRCHKRA14 0xE6150A38 // R 32 Functional safety reset check register A 14 +#define CPG_FSRCHKRA15 0xE6150A3C // R 32 Functional safety reset check register A 15 +#define CPG_FSRCHKRA16 0xE6150B50 // R 32 Functional safety reset check register A 16 +#define CPG_FSRCHKRA17 0xE6150B54 // R 32 Functional safety reset check register A 17 +#define CPG_FSRCHKRA18 0xE6150B58 // R 32 Functional safety reset check register A 18 +#define CPG_FSRCHKRB0 0xE6150A30 // R 32 Functional safety reset check register B 0 +#define CPG_FSRCHKRB1 0xE6150A34 // R 32 Functional safety reset check register B 1 +#define CPG_FSRCHKRB2 0xE6150A38 // R 32 Functional safety reset check register B 2 +#define CPG_FSRCHKRB3 0xE6150A3C // R 32 Functional safety reset check register B 3 +#define CPG_FSRCHKRB4 0xE6150A40 // R 32 Functional safety reset check register B 4 +#define CPG_FSRCHKRB5 0xE6150A44 // R 32 Functional safety reset check register B 5 +#define CPG_FSRCHKRB6 0xE6150A48 // R 32 Functional safety reset check register B 6 +#define CPG_FSRCHKRB7 0xE6150A4C // R 32 Functional safety reset check register B 7 +#define CPG_FSRCHKRB8 0xE6150A50 // R 32 Functional safety reset check register B 8 +#define CPG_FSRCHKRB9 0xE6150A54 // R 32 Functional safety reset check register B 9 +#define CPG_FSRCHKRB10 0xE6150A58 // R 32 Functional safety reset check register B 10 +#define CPG_FSRCHKRB11 0xE6150A5C // R 32 Functional safety reset check register B 11 +#define CPG_FSRCHKRB13 0xE6150A74 // R 32 Functional safety reset check register B 13 +#define CPG_FSRCHKSETR0 0xE6150A60 // W 32 Functional safety reset check set register 0 +#define CPG_FSRCHKSETR1 0xE6150A64 // W 32 Functional safety reset check set register 1 +#define CPG_FSRCHKSETR2 0xE6150A68 // W 32 Functional safety reset check set register 2 +#define CPG_FSRCHKSETR3 0xE6150A6C // W 32 Functional safety reset check set register 3 +#define CPG_FSRCHKSETR4 0xE6150A70 // W 32 Functional safety reset check set register 4 +#define CPG_FSRCHKSETR5 0xE6150A74 // W 32 Functional safety reset check set register 5 +#define CPG_FSRCHKSETR6 0xE6150A78 // W 32 Functional safety reset check set register 6 +#define CPG_FSRCHKSETR7 0xE6150A7C // W 32 Functional safety reset check set register 7 +#define CPG_FSRCHKSETR8 0xE6150A80 // W 32 Functional safety reset check set register 8 +#define CPG_FSRCHKSETR9 0xE6150A84 // W 32 Functional safety reset check set register 9 +#define CPG_FSRCHKSETR10 0xE6150A88 // W 32 Functional safety reset check set register 10 +#define CPG_FSRCHKSETR11 0xE6150A8C // W 32 Functional safety reset check set register 11 +#define CPG_FSRCHKSETR12 0xE6150AB0 // W 32 Functional safety reset check set register 12 +#define CPG_FSRCHKSETR13 0xE6150AB4 // W 32 Functional safety reset check set register 13 +#define CPG_FSRCHKSETR14 0xE6150AB8 // W 32 Functional safety reset check set register 14 +#define CPG_FSRCHKSETR15 0xE6150ABC // W 32 Functional safety reset check set register 15 +#define CPG_FSRCHKSETR16 0xE6150B60 // W 32 Functional safety reset check set register 16 +#define CPG_FSRCHKSETR17 0xE6150B64 // W 32 Functional safety reset check set register 17 +#define CPG_FSRCHKSETR18 0xE6150B68 // W 32 Functional safety reset check set register 18 +#define CPG_FSRCHKCLRR0 0xE6150A90 // W 32 Functional safety reset check clear register 0 +#define CPG_FSRCHKCLRR1 0xE6150A94 // W 32 Functional safety reset check clear register 1 +#define CPG_FSRCHKCLRR2 0xE6150A98 // W 32 Functional safety reset check clear register 2 +#define CPG_FSRCHKCLRR3 0xE6150A9C // W 32 Functional safety reset check clear register 3 +#define CPG_FSRCHKCLRR4 0xE6150AA0 // W 32 Functional safety reset check clear register 4 +#define CPG_FSRCHKCLRR5 0xE6150AA4 // W 32 Functional safety reset check clear register 5 +#define CPG_FSRCHKCLRR6 0xE6150AA8 // W 32 Functional safety reset check clear register 6 +#define CPG_FSRCHKCLRR7 0xE6150AAC // W 32 Functional safety reset check clear register 7 +#define CPG_FSRCHKCLRR8 0xE6150AB0 // W 32 Functional safety reset check clear register 8 +#define CPG_FSRCHKCLRR9 0xE6150AB4 // W 32 Functional safety reset check clear register 9 +#define CPG_FSRCHKCLRR10 0xE6150AB8 // W 32 Functional safety reset check clear register 10 +#define CPG_FSRCHKCLRR11 0xE6150ABC // W 32 Functional safety reset check clear register 11 +#define CPG_FSRCHKCLRR12 0xE6150AF0 // W 32 Functional safety reset check clear register 12 +#define CPG_FSRCHKCLRR13 0xE6150AF4 // W 32 Functional safety reset check clear register 13 +#define CPG_FSRCHKCLRR14 0xE6150AF8 // W 32 Functional safety reset check clear register 14 +#define CPG_FSRCHKCLRR15 0xE6150AFC // W 32 Functional safety reset check clear register 15 +#define CPG_FSRCHKCLRR16 0xE6150B70 // W 32 Functional safety reset check clear register 16 +#define CPG_FSRCHKCLRR17 0xE6150B74 // W 32 Functional safety reset check clear register 17 +#define CPG_FSRCHKCLRR18 0xE6150B78 // W 32 Functional safety reset check clear register 18 +#define CPG_FSSEQCHKR 0xE6150AF0 // R 32 Functional safety Power on sequence Check Register +#define CPG_FSSEQCHKCSR 0xE6150AF4 // R/W 32 Functional safety Power on sequence Check Control/Status Register + + +//GPIO +#define GPIO_IOINTSEL0 0xE6050000 // R/W 32 General IO/interrupt switching register 0 +#define GPIO_INOUTSEL0 0xE6050004 // R/W 32 General input/output switching register 0 +#define GPIO_OUTDT0 0xE6050008 // R/W 32 General output register 0 +#define GPIO_INDT0 0xE605000C // R 32 General input register 0 +#define GPIO_INTDT0 0xE6050010 // R 32 Interrupt display register 0 +#define GPIO_INTCLR0 0xE6050014 // R/W 32 Interrupt clear register 0 +#define GPIO_INTMSK0 0xE6050018 // R/W 32 Interrupt mask register 0 +#define GPIO_MSKCLR0 0xE605001C // R/W 32 Interrupt mask clear register 0 +#define GPIO_POSNEG0 0xE6050020 // R/W 32 Positive/negative logic select register 0 +#define GPIO_EDGLEVEL0 0xE6050024 // R/W 32 Edge/level select register 0 +#define GPIO_FILONOFF0 0xE6050028 // R/W 32 Chattering prevention on/off register 0 +#define GPIO_INTMSKS0 0xE6050038 // R/W 32 Interrupt sub mask register 0 +#define GPIO_MSKCLRS0 0xE605003C // R/W 32 Interrupt sub mask clear register 0 +#define GPIO_OUTDTSEL0 0xE6050040 // R/W 32 Output data select register 0 +#define GPIO_OUTDTH0 0xE6050044 // R/W 32 Output data high register 0 +#define GPIO_OUTDTL0 0xE6050048 // R/W 32 Output data low register 0 +#define GPIO_BOTHEDGE0 0xE605004C // R/W 32 One edge/both edge select register 0 +#define GPIO_IOINTSEL1 0xE6051000 // R/W 32 General IO/interrupt switching register 1 +#define GPIO_INOUTSEL1 0xE6051004 // R/W 32 General input/output switching register 1 +#define GPIO_OUTDT1 0xE6051008 // R/W 32 General output register 1 +#define GPIO_INDT1 0xE605100C // R 32 General input register 1 +#define GPIO_INTDT1 0xE6051010 // R 32 Interrupt display register 1 +#define GPIO_INTCLR1 0xE6051014 // R/W 32 Interrupt clear register 1 +#define GPIO_INTMSK1 0xE6051018 // R/W 32 Interrupt mask register 1 +#define GPIO_MSKCLR1 0xE605101C // R/W 32 Interrupt mask clear register 1 +#define GPIO_POSNEG1 0xE6051020 // R/W 32 Positive/negative logic select register 1 +#define GPIO_EDGLEVEL1 0xE6051024 // R/W 32 Edge/level select register 1 +#define GPIO_FILONOFF1 0xE6051028 // R/W 32 Chattering prevention on/off register 1 +#define GPIO_INTMSKS1 0xE6051038 // R/W 32 Interrupt sub mask register 1 +#define GPIO_MSKCLRS1 0xE605103C // R/W 32 Interrupt sub mask clear register 1 +#define GPIO_OUTDTSEL1 0xE6051040 // R/W 32 Output data select register 1 +#define GPIO_OUTDTH1 0xE6051044 // R/W 32 Output data high register 1 +#define GPIO_OUTDTL1 0xE6051048 // R/W 32 Output data low register 1 +#define GPIO_BOTHEDGE1 0xE605104C // R/W 32 One edge/both edge select register 1 +#define GPIO_IOINTSEL2 0xE6052000 // R/W 32 General IO/interrupt switching register 2 +#define GPIO_INOUTSEL2 0xE6052004 // R/W 32 General input/output switching register 2 +#define GPIO_OUTDT2 0xE6052008 // R/W 32 General output register 2 +#define GPIO_INDT2 0xE605200C // R 32 General input register 2 +#define GPIO_INTDT2 0xE6052010 // R 32 Interrupt display register 2 +#define GPIO_INTCLR2 0xE6052014 // R/W 32 Interrupt clear register 2 +#define GPIO_INTMSK2 0xE6052018 // R/W 32 Interrupt mask register 2 +#define GPIO_MSKCLR2 0xE605201C // R/W 32 Interrupt mask clear register 2 +#define GPIO_POSNEG2 0xE6052020 // R/W 32 Positive/negative logic select register 2 +#define GPIO_EDGLEVEL2 0xE6052024 // R/W 32 Edge/level select register 2 +#define GPIO_FILONOFF2 0xE6052028 // R/W 32 Chattering prevention on/off register 2 +#define GPIO_INTMSKS2 0xE6052038 // R/W 32 Interrupt sub mask register 2 +#define GPIO_MSKCLRS2 0xE605203C // R/W 32 Interrupt sub mask clear register 2 +#define GPIO_OUTDTSEL2 0xE6052040 // R/W 32 Output data select register 2 +#define GPIO_OUTDTH2 0xE6052044 // R/W 32 Output data high register 2 +#define GPIO_OUTDTL2 0xE6052048 // R/W 32 Output data low register 2 +#define GPIO_BOTHEDGE2 0xE605204C // R/W 32 One edge/both edge select register 2 +#define GPIO_IOINTSEL3 0xE6053000 // R/W 32 General IO/interrupt switching register 3 +#define GPIO_INOUTSEL3 0xE6053004 // R/W 32 General input/output switching register 3 +#define GPIO_OUTDT3 0xE6053008 // R/W 32 General output register 3 +#define GPIO_INDT3 0xE605300C // R 32 General input register 3 +#define GPIO_INTDT3 0xE6053010 // R 32 Interrupt display register 3 +#define GPIO_INTCLR3 0xE6053014 // R/W 32 Interrupt clear register 3 +#define GPIO_INTMSK3 0xE6053018 // R/W 32 Interrupt mask register 3 +#define GPIO_MSKCLR3 0xE605301C // R/W 32 Interrupt mask clear register 3 +#define GPIO_POSNEG3 0xE6053020 // R/W 32 Positive/negative logic select register 3 +#define GPIO_EDGLEVEL3 0xE6053024 // R/W 32 Edge/level select register 3 +#define GPIO_FILONOFF3 0xE6053028 // R/W 32 Chattering prevention on/off register 3 +#define GPIO_INTMSKS3 0xE6053038 // R/W 32 Interrupt sub mask register 3 +#define GPIO_MSKCLRS3 0xE605303C // R/W 32 Interrupt sub mask clear register 3 +#define GPIO_OUTDTSEL3 0xE6053040 // R/W 32 Output data select register 3 +#define GPIO_OUTDTH3 0xE6053044 // R/W 32 Output data high register 3 +#define GPIO_OUTDTL3 0xE6053048 // R/W 32 Output data low register 3 +#define GPIO_BOTHEDGE3 0xE605304C // R/W 32 One edge/both edge select register 3 +#define GPIO_IOINTSEL4 0xE6054000 // R/W 32 General IO/interrupt switching register 4 +#define GPIO_INOUTSEL4 0xE6054004 // R/W 32 General input/output switching register 4 +#define GPIO_OUTDT4 0xE6054008 // R/W 32 General output register 4 +#define GPIO_INDT4 0xE605400C // R 32 General input register 4 +#define GPIO_INTDT4 0xE6054010 // R 32 Interrupt display register 4 +#define GPIO_INTCLR4 0xE6054014 // R/W 32 Interrupt clear register 4 +#define GPIO_INTMSK4 0xE6054018 // R/W 32 Interrupt mask register 4 +#define GPIO_MSKCLR4 0xE605401C // R/W 32 Interrupt mask clear register 4 +#define GPIO_POSNEG4 0xE6054020 // R/W 32 Positive/negative logic select register 4 +#define GPIO_EDGLEVEL4 0xE6054024 // R/W 32 Edge/level select register 4 +#define GPIO_FILONOFF4 0xE6054028 // R/W 32 Chattering prevention on/off register 4 +#define GPIO_INTMSKS4 0xE6054038 // R/W 32 Interrupt sub mask register 4 +#define GPIO_MSKCLRS4 0xE605403C // R/W 32 Interrupt sub mask clear register 4 +#define GPIO_OUTDTSEL4 0xE6054040 // R/W 32 Output data select register 4 +#define GPIO_OUTDTH4 0xE6054044 // R/W 32 Output data high register 4 +#define GPIO_OUTDTL4 0xE6054048 // R/W 32 Output data low register 4 +#define GPIO_BOTHEDGE4 0xE605404C // R/W 32 One edge/both edge select register 4 +#define GPIO_IOINTSEL5 0xE6055000 // R/W 32 General IO/interrupt switching register 5 +#define GPIO_INOUTSEL5 0xE6055004 // R/W 32 General input/output switching register 5 +#define GPIO_OUTDT5 0xE6055008 // R/W 32 General output register 5 +#define GPIO_INDT5 0xE605500C // R 32 General input register 5 +#define GPIO_INTDT5 0xE6055010 // R 32 Interrupt display register 5 +#define GPIO_INTCLR5 0xE6055014 // R/W 32 Interrupt clear register 5 +#define GPIO_INTMSK5 0xE6055018 // R/W 32 Interrupt mask register 5 +#define GPIO_MSKCLR5 0xE605501C // R/W 32 Interrupt mask clear register 5 +#define GPIO_POSNEG5 0xE6055020 // R/W 32 Positive/negative logic select register 5 +#define GPIO_EDGLEVEL5 0xE6055024 // R/W 32 Edge/level select register 5 +#define GPIO_FILONOFF5 0xE6055028 // R/W 32 Chattering prevention on/off register 5 +#define GPIO_INTMSKS5 0xE6055038 // R/W 32 Interrupt sub mask register 5 +#define GPIO_MSKCLRS5 0xE605503C // R/W 32 Interrupt sub mask clear register 5 +#define GPIO_OUTDTSEL5 0xE6055040 // R/W 32 Output data select register 5 +#define GPIO_OUTDTH5 0xE6055044 // R/W 32 Output data high register 5 +#define GPIO_OUTDTL5 0xE6055048 // R/W 32 Output data low register 5 +#define GPIO_BOTHEDGE5 0xE605504C // R/W 32 One edge/both edge select register 5 +#define GPIO_IOINTSEL6 0xE6055400 // R/W 32 General IO/interrupt switching register 6 +#define GPIO_INOUTSEL6 0xE6055404 // R/W 32 General input/output switching register 6 +#define GPIO_OUTDT6 0xE6055408 // R/W 32 General output register 6 +#define GPIO_INDT6 0xE605540C // R 32 General input register 6 +#define GPIO_INTDT6 0xE6055410 // R 32 Interrupt display register 6 +#define GPIO_INTCLR6 0xE6055414 // R/W 32 Interrupt clear register 6 +#define GPIO_INTMSK6 0xE6055418 // R/W 32 Interrupt mask register 6 +#define GPIO_MSKCLR6 0xE605541C // R/W 32 Interrupt mask clear register 6 +#define GPIO_POSNEG6 0xE6055420 // R/W 32 Positive/negative logic select register 6 +#define GPIO_EDGLEVEL6 0xE6055424 // R/W 32 Edge/level select register 6 +#define GPIO_FILONOFF6 0xE6055428 // R/W 32 Chattering prevention on/off register 6 +#define GPIO_INTMSKS6 0xE6055438 // R/W 32 Interrupt sub mask register 6 +#define GPIO_MSKCLRS6 0xE605543C // R/W 32 Interrupt sub mask clear register 6 +#define GPIO_OUTDTSEL6 0xE6055440 // R/W 32 Output data select register 6 +#define GPIO_OUTDTH6 0xE6055444 // R/W 32 Output data high register 6 +#define GPIO_OUTDTL6 0xE6055448 // R/W 32 Output data low register 6 +#define GPIO_BOTHEDGE6 0xE605544C // R/W 32 One edge/both edge select register 6 +#define GPIO_IOINTSEL7 0xE6055800 // R/W 32 General IO/interrupt switching register 7 +#define GPIO_INOUTSEL7 0xE6055804 // R/W 32 General input/output switching register 7 +#define GPIO_OUTDT7 0xE6055808 // R/W 32 General output register 7 +#define GPIO_INDT7 0xE605580C // R 32 General input register 7 +#define GPIO_INTDT7 0xE6055810 // R 32 Interrupt display register 7 +#define GPIO_INTCLR7 0xE6055814 // R/W 32 Interrupt clear register 7 +#define GPIO_INTMSK7 0xE6055818 // R/W 32 Interrupt mask register 7 +#define GPIO_MSKCLR7 0xE605581C // R/W 32 Interrupt mask clear register 7 +#define GPIO_POSNEG7 0xE6055820 // R/W 32 Positive/negative logic select register 7 +#define GPIO_EDGLEVEL7 0xE6055824 // R/W 32 Edge/level select register 7 +#define GPIO_FILONOFF7 0xE6055828 // R/W 32 Chattering prevention on/off register 7 +#define GPIO_INTMSKS7 0xE6055838 // R/W 32 Interrupt sub mask register 7 +#define GPIO_MSKCLRS7 0xE605583C // R/W 32 Interrupt sub mask clear register 7 +#define GPIO_OUTDTSEL7 0xE6055840 // R/W 32 Output data select register 7 +#define GPIO_OUTDTH7 0xE6055844 // R/W 32 Output data high register 7 +#define GPIO_OUTDTL7 0xE6055848 // R/W 32 Output data low register 7 +#define GPIO_BOTHEDGE7 0xE605584C // R/W 32 One edge/both edge select register 7 + + +//LBSC.h +#define LBSC_CS0CTRL 0xEE220200 // R/W 32 Area 0 control register +#define LBSC_CS1CTRL 0xEE220204 // R/W 32 Area 1 control register +#define LBSC_CSWCR0 0xEE220230 // R/W 32 Area 0 RD/WE pulse control register +#define LBSC_CSWCR1 0xEE220234 // R/W 32 Area 1 RD/WE pulse control register +#define LBSC_CSPWCR0 0xEE220280 // R/W 32 Area 0 external wait control register +#define LBSC_CSPWCR1 0xEE220284 // R/W 32 Area 1 external wait control register +#define LBSC_EXWTSYNC 0xEE2202A0 // R/W 32 External wait input control register +#define LBSC_CS0BSTCTL 0xEE2202B0 // R/W 32 Area 0 burst control register +#define LBSC_CS0BTPH 0xEE2202B4 // R/W 32 Area 0 burst pitch set register +#define LBSC_CS1GDST 0xEE2202C0 // R/W 32 Area 1 guard setting register +#define LBSC_BCINTSR 0xEE220330 // R 32 BSC interrupt source status register +#define LBSC_BCINTCR 0xEE220334 // -/WC1 32 BSC interrupt source clear register +#define LBSC_BCINTMR 0xEE220338 // R/W 32 BSC interrupt enable register +#define LBSC_EXWTSTS 0xEE220344 // R 32 External wait status register +#define LBSC_EXBCT 0xEE2203C0 // R/W 32 EX-BUS wait timeout detection base counter register +#define LBSC_EXTCT 0xEE2203C4 // R/W 32 EX-BUS wait timeout detection counter register +#define LBSC_EXTSR 0xEE220010 // R/WC1 32 EX-BUS wait timeout detection access source indication register +#define LBSC_EXTADR 0xEE220014 // R/W 32 EX-BUS wait timeout detection address indication register + + +//MSTPRST +#define CPG_MSTPSR0 0xE6150030 // R 32 Module stop status register 0 +#define CPG_MSTPSR1 0xE6150038 // R 32 Module stop status register 1 +#define CPG_MSTPSR2 0xE6150040 // R 32 Module stop status register 2 +#define CPG_MSTPSR3 0xE6150048 // R 32 Module stop status register 3 +#define CPG_MSTPSR4 0xE615004C // R 32 Module stop status register 4 +#define CPG_MSTPSR5 0xE615003C // R 32 Module stop status register 5 +#define CPG_MSTPSR6 0xE61501C0 // R 32 Module stop status register 6 +#define CPG_MSTPSR7 0xE61501C4 // R 32 Module stop status register 7 +#define CPG_MSTPSR8 0xE61509A0 // R 32 Module stop status register 8 +#define CPG_MSTPSR9 0xE61509A4 // R 32 Module stop status register 9 +#define CPG_MSTPSR10 0xE61509A8 // R 32 Module stop status register 10 +#define CPG_MSTPSR11 0xE61509AC // R 32 Module stop status register 11 +#define CPG_RMSTPCR0 0xE6150110 // R/W 32 Realtime module stop control register 0 +#define CPG_RMSTPCR1 0xE6150114 // R/W 32 Realtime module stop control register 1 +#define CPG_RMSTPCR2 0xE6150118 // R/W 32 Realtime module stop control register 2 +#define CPG_RMSTPCR3 0xE615011C // R/W 32 Realtime module stop control register 3 +#define CPG_RMSTPCR4 0xE6150120 // R/W 32 Realtime module stop control register 4 +#define CPG_RMSTPCR5 0xE6150124 // R/W 32 Realtime module stop control register 5 +#define CPG_RMSTPCR6 0xE6150128 // R/W 32 Realtime module stop control register 6 +#define CPG_RMSTPCR7 0xE615012C // R/W 32 Realtime module stop control register 7 +#define CPG_RMSTPCR8 0xE6150980 // R/W 32 Realtime module stop control register 8 +#define CPG_RMSTPCR9 0xE6150984 // R/W 32 Realtime module stop control register 9 +#define CPG_RMSTPCR10 0xE6150988 // R/W 32 Realtime module stop control register 10 +#define CPG_RMSTPCR11 0xE615098C // R/W 32 Realtime module stop control register 11 +#define CPG_SMSTPCR0 0xE6150130 // R/W 32 System module stop control register 0 +#define CPG_SMSTPCR1 0xE6150134 // R/W 32 System module stop control register 1 +#define CPG_SMSTPCR2 0xE6150138 // R/W 32 System module stop control register 2 +#define CPG_SMSTPCR3 0xE615013C // R/W 32 System module stop control register 3 +#define CPG_SMSTPCR4 0xE6150140 // R/W 32 System module stop control register 4 +#define CPG_SMSTPCR5 0xE6150144 // R/W 32 System module stop control register 5 +#define CPG_SMSTPCR6 0xE6150148 // R/W 32 System module stop control register 6 +#define CPG_SMSTPCR7 0xE615014C // R/W 32 System module stop control register 7 +#define CPG_SMSTPCR8 0xE6150990 // R/W 32 System module stop control register 8 +#define CPG_SMSTPCR9 0xE6150994 // R/W 32 System module stop control register 9 +#define CPG_SMSTPCR10 0xE6150998 // R/W 32 System module stop control register 10 +#define CPG_SMSTPCR11 0xE615099C // R/W 32 System module stop control register 11 +#define CPG_SRCR0 0xE61500A0 // R/W 32 Software reset register 0 +#define CPG_SRCR1 0xE61500A8 // R/W 32 Software reset register 1 +#define CPG_SRCR2 0xE61500B0 // R/W 32 Software reset register 2 +#define CPG_SRCR3 0xE61500B8 // R/W 32 Software reset register 3 +#define CPG_SRCR4 0xE61500BC // R/W 32 Software reset register 4 +#define CPG_SRCR5 0xE61500C4 // R/W 32 Software reset register 5 +#define CPG_SRCR6 0xE61501C8 // R/W 32 Software reset register 6 +#define CPG_SRCR7 0xE61501CC // R/W 32 Software reset register 7 +#define CPG_SRCR8 0xE6150920 // R/W 32 Software reset register 8 +#define CPG_SRCR9 0xE6150924 // R/W 32 Software reset register 9 +#define CPG_SRCR10 0xE6150928 // R/W 32 Software reset register 10 +#define CPG_SRCR11 0xE615092C // R/W 32 Software reset register 11 +#define CPG_SRSTCLR0 0xE6150940 // W 32 Software reset clearing register 0 +#define CPG_SRSTCLR1 0xE6150944 // W 32 Software reset clearing register 1 +#define CPG_SRSTCLR2 0xE6150948 // W 32 Software reset clearing register 2 +#define CPG_SRSTCLR3 0xE615094C // W 32 Software reset clearing register 3 +#define CPG_SRSTCLR4 0xE6150950 // W 32 Software reset clearing register 4 +#define CPG_SRSTCLR5 0xE6150954 // W 32 Software reset clearing register 5 +#define CPG_SRSTCLR6 0xE6150958 // W 32 Software reset clearing register 6 +#define CPG_SRSTCLR7 0xE615095C // W 32 Software reset clearing register 7 +#define CPG_SRSTCLR8 0xE6150960 // W 32 Software reset clearing register 8 +#define CPG_SRSTCLR9 0xE6150964 // W 32 Software reset clearing register 9 +#define CPG_SRSTCLR10 0xE6150968 // W 32 Software reset clearing register 10 +#define CPG_SRSTCLR11 0xE615096C // W 32 Software reset clearing register 11 +#define CPG_SAMSTPCR0 0xE6150C20 // R/W 32 Safety Module Stop Control Register 0 +#define CPG_SAMSTPCR1 0xE6150C24 // R/W 32 Safety Module Stop Control Register 1 +#define CPG_SAMSTPCR2 0xE6150C28 // R/W 32 Safety Module Stop Control Register 2 +#define CPG_SAMSTPCR3 0xE6150C2C // R/W 32 Safety Module Stop Control Register 3 +#define CPG_SAMSTPCR4 0xE6150C30 // R/W 32 Safety Module Stop Control Register 4 +#define CPG_SAMSTPCR5 0xE6150C34 // R/W 32 Safety Module Stop Control Register 5 +#define CPG_SAMSTPCR6 0xE6150C38 // R/W 32 Safety Module Stop Control Register 6 +#define CPG_SAMSTPCR7 0xE6150C3C // R/W 32 Safety Module Stop Control Register 7 +#define CPG_SAMSTPCR8 0xE6150C40 // R/W 32 Safety Module Stop Control Register 8 +#define CPG_SAMSTPCR9 0xE6150C44 // R/W 32 Safety Module Stop Control Register 9 +#define CPG_SAMSTPCR10 0xE6150C48 // R/W 32 Safety Module Stop Control Register 10 +#define CPG_SAMSTPCR11 0xE6150C4C // R/W 32 Safety Module Stop Control Register 11 +#define CPG_SASRSTECR0 0xE6150C80 // R/W 32 Safety Software Reset Access Enable Control Register 0 +#define CPG_SASRSTECR1 0xE6150C84 // R/W 32 Safety Software Reset Access Enable Control Register 1 +#define CPG_SASRSTECR2 0xE6150C88 // R/W 32 Safety Software Reset Access Enable Control Register 2 +#define CPG_SASRSTECR3 0xE6150C8C // R/W 32 Safety Software Reset Access Enable Control Register 3 +#define CPG_SASRSTECR4 0xE6150C90 // R/W 32 Safety Software Reset Access Enable Control Register 4 +#define CPG_SASRSTECR5 0xE6150C94 // R/W 32 Safety Software Reset Access Enable Control Register 5 +#define CPG_SASRSTECR6 0xE6150C98 // R/W 32 Safety Software Reset Access Enable Control Register 6 +#define CPG_SASRSTECR7 0xE6150C9C // R/W 32 Safety Software Reset Access Enable Control Register 7 +#define CPG_SASRSTECR8 0xE6150CA0 // R/W 32 Safety Software Reset Access Enable Control Register 8 +#define CPG_SASRSTECR9 0xE6150CA4 // R/W 32 Safety Software Reset Access Enable Control Register 9 +#define CPG_SASRSTECR10 0xE6150CA8 // R/W 32 Safety Software Reset Access Enable Control Register 10 +#define CPG_SASRSTECR11 0xE6150CAC // R/W 32 Safety Software Reset Access Enable Control Register 11 +#define CPG_SAPTCSR 0xE6150C00 // R/W 32 Safety Protect Control/Status Register +#define CPG_SAERMIDR 0xE6150C04 // R 32 Safety Error Master ID Register +#define CPG_SAERADR 0xE6150C08 // R 32 Safety Error Address Regsiter + + + +//PFC +#define PFC_PMMR 0xE6060000 // R/W 32 LSI Multiplexed Pin Setting Mask Register +#define PFC_GPSR0 0xE6060100 // R/W 32 GPIO/Peripheral Function Select register 0 +#define PFC_GPSR1 0xE6060104 // R/W 32 GPIO/Peripheral Function Select register 1 +#define PFC_GPSR2 0xE6060108 // R/W 32 GPIO/Peripheral_Function Select register 2 +#define PFC_GPSR3 0xE606010C // R/W 32 GPIO/Peripheral Function Select register 3 +#define PFC_GPSR4 0xE6060110 // R/W 32 GPIO/Peripheral Function Select register 4 +#define PFC_GPSR5 0xE6060114 // R/W 32 GPIO/Peripheral Function Select register 5 +#define PFC_GPSR6 0xE6060118 // R/W 32 GPIO/Peripheral Function Select register 6 +#define PFC_GPSR7 0xE606011C // R/W 32 GPIO/Peripheral Function Select register 7 +#define PFC_IPSR0 0xE6060200 // R/W 32 Peripheral Function Select register 0 +#define PFC_IPSR1 0xE6060204 // R/W 32 Peripheral Function Select register 1 +#define PFC_IPSR2 0xE6060208 // R/W 32 Peripheral Function Select register 2 +#define PFC_IPSR3 0xE606020C // R/W 32 Peripheral Function Select register 3 +#define PFC_IPSR4 0xE6060210 // R/W 32 Peripheral Function Select register 4 +#define PFC_IPSR5 0xE6060214 // R/W 32 Peripheral Function Select register 5 +#define PFC_IPSR6 0xE6060218 // R/W 32 Peripheral Function Select register 6 +#define PFC_IPSR7 0xE606021C // R/W 32 Peripheral Function Select register 7 +#define PFC_IPSR8 0xE6060220 // R/W 32 Peripheral Function Select register 8 +#define PFC_IPSR9 0xE6060224 // R/W 32 Peripheral Function Select register 9 +#define PFC_IPSR10 0xE6060228 // R/W 32 Peripheral Function Select register 10 +#define PFC_IPSR11 0xE606022C // R/W 32 Peripheral Function Select register 11 +#define PFC_IPSR12 0xE6060230 // R/W 32 Peripheral Function Select register 12 +#define PFC_IPSR13 0xE6060234 // R/W 32 Peripheral Function Select register 13 +#define PFC_IPSR14 0xE6060238 // R/W 32 Peripheral Function Select register 14 +#define PFC_IPSR15 0xE606023C // R/W 32 Peripheral Function Select register 15 +#define PFC_IPSR16 0xE6060240 // R/W 32 Peripheral Function Select register 16 +#define PFC_IPSR17 0xE6060244 // R/W 32 Peripheral Function Select register 17 +#define PFC_IPSR18 0xE6060248 // R/W 32 Peripheral Function Select register 18 +#define PFC_DRVCTRL0 0xE6060300 // R/W 32 DRV control register0 +#define PFC_DRVCTRL1 0xE6060304 // R/W 32 DRV control register1 +#define PFC_DRVCTRL2 0xE6060308 // R/W 32 DRV control register2 +#define PFC_DRVCTRL3 0xE606030C // R/W 32 DRV control register3 +#define PFC_DRVCTRL4 0xE6060310 // R/W 32 DRV control register4 +#define PFC_DRVCTRL5 0xE6060314 // R/W 32 DRV control register5 +#define PFC_DRVCTRL6 0xE6060318 // R/W 32 DRV control register6 +#define PFC_DRVCTRL7 0xE606031C // R/W 32 DRV control register7 +#define PFC_DRVCTRL8 0xE6060320 // R/W 32 DRV control register8 +#define PFC_DRVCTRL9 0xE6060324 // R/W 32 DRV control register9 +#define PFC_DRVCTRL10 0xE6060328 // R/W 32 DRV control register10 +#define PFC_DRVCTRL11 0xE606032C // R/W 32 DRV control register11 +#define PFC_DRVCTRL12 0xE6060330 // R/W 32 DRV control register12 +#define PFC_DRVCTRL13 0xE6060334 // R/W 32 DRV control register13 +#define PFC_DRVCTRL14 0xE6060338 // R/W 32 DRV control register14 +#define PFC_DRVCTRL15 0xE606033C // R/W 32 DRV control register15 +#define PFC_DRVCTRL16 0xE6060340 // R/W 32 DRV control register16 +#define PFC_DRVCTRL17 0xE6060344 // R/W 32 DRV control register17 +#define PFC_DRVCTRL18 0xE6060348 // R/W 32 DRV control register18 +#define PFC_DRVCTRL19 0xE606034C // R/W 32 DRV control register19 +#define PFC_DRVCTRL20 0xE6060350 // R/W 32 DRV control register20 +#define PFC_DRVCTRL21 0xE6060354 // R/W 32 DRV control register21 +#define PFC_DRVCTRL22 0xE6060358 // R/W 32 DRV control register22 +#define PFC_DRVCTRL23 0xE606035C // R/W 32 DRV control register23 +#define PFC_DRVCTRL24 0xE6060360 // R/W 32 DRV control register24 +#define PFC_POCCTRL0 0xE6060380 // R/W 32 POC control register0 +#define PFC_TDSELCTRL0 0xE60603C0 // R/W 32 TDSEL control register0 +#define PFC_IOCTRL 0xE60603E0 // R/W 32 IO cell control for IICDVFS +#define PFC_FUSEMON 0xE60603E4 // R 32 Fuse Monitor register0 +#define PFC_PUEN0 0xE6060400 // R/W 32 LSI pin pull-enable register 0 +#define PFC_PUEN1 0xE6060404 // R/W 32 LSI pin pull-enable register 1 +#define PFC_PUEN2 0xE6060408 // R/W 32 LSI pin pull-enable register 2 +#define PFC_PUEN3 0xE606040C // R/W 32 LSI pin pull-enable register 3 +#define PFC_PUEN4 0xE6060410 // R/W 32 LSI pin pull-enable register 4 +#define PFC_PUEN5 0xE6060414 // R/W 32 LSI pin pull-enable register 5 +#define PFC_PUEN6 0xE6060418 // R/W 32 LSI pin pull-enable register 6 +#define PFC_PUD0 0xE6060440 // R/W 32 LSI pin pull-up/down control register 0 +#define PFC_PUD1 0xE6060444 // R/W 32 LSI pin pull-up/down control register 1 +#define PFC_PUD2 0xE6060448 // R/W 32 LSI pin pull-up/down control register 2 +#define PFC_PUD3 0xE606044C // R/W 32 LSI pin pull-up/down control register 3 +#define PFC_PUD4 0xE6060450 // R/W 32 LSI pin pull-up/down control register 4 +#define PFC_PUD5 0xE6060454 // R/W 32 LSI pin pull-up/down control register 5 +#define PFC_PUD6 0xE6060458 // R/W 32 LSI pin pull-up/down control register 6 +#define PFC_MOD_SEL0 0xE6060500 // R/W 32 Module select register 0 +#define PFC_MOD_SEL1 0xE6060504 // R/W 32 Module select register 1 +#define PFC_MOD_SEL2 0xE6060508 // R/W 32 Module select register 2 + +//V3M +#define PFC_IOCTRL30 0xE6060380 // R/W 32 MPOC control register 0 +#define PFC_IOCTRL31 0xE6060384 // R/W 32 MPOC control register 0 +#define PFC_IOCTRL32 0xE6060388 // R/W 32 MPOC control register 0 +#define PFC_IOCTRL40 0xE60603C0 // R/W 32 MPOC control register 0 + + +//RST +#define RST_MODEMR 0xE6160060 // R 32 Mode Monitor Register +#define RST_CA57RESCNT 0xE6160040 // R/W 32 CA57 Reset Control Register +#define RST_CA53RESCNT 0xE6160044 // R/W 32 CA53 Reset Control Register +#define RST_WDTRSTCR 0xE6160054 // R/W 32 Watchdog Timer Reset Control Register +#define RST_RSTOUTCR 0xE6160058 // R/W 32 PRESETOUT# Control Register +#define RST_SBAR 0xE6160010 // R/W 32 SYS Boot Address Register +#define RST_SBAR2 0xE6160014 // R/W 32 SYS Boot Address Register2 +#define RST_CA53BAR 0xE6160030 // R/W 32 CA53 Boot Address Register +#define RST_CA53BAR2 0xE6160034 // R/W 32 CA53 Boot Address Register2 +#define RST_CA57BAR 0xE6160020 // R/W 32 CA57 Boot Address Register +#define RST_CA57BAR2 0xE6160024 // R/W 32 CA57 Boot Address Register2 +#define RST_CR7BAR 0xE6160070 // R/W 32 CR7 Boot Address Register +#define RST_CR7BAR2 0xE6160074 // R/W 32 CR7 Boot Address Register2 +#define RST_CA57CPU0BARH 0xE61600C0 // R/W 32 CA57 CPU0 Boot Address Register for 64-bit mode H +#define RST_CA57CPU0BARL 0xE61600C4 // R/W 32 CA57 CPU0 Boot Address Register for 64-bit mode L +#define RST_CA57CPU1BARH 0xE61600D0 // R/W 32 CA57 CPU1 Boot Address Register for 64-bit mode H +#define RST_CA57CPU1BARL 0xE61600D4 // R/W 32 CA57 CPU1 Boot Address Register for 64-bit mode L +#define RST_CA57CPU2BARH 0xE61600E0 // R/W 32 CA57 CPU2 Boot Address Register for 64-bit mode H +#define RST_CA57CPU2BARL 0xE61600E4 // R/W 32 CA57 CPU2 Boot Address Register for 64-bit mode L +#define RST_CA57CPU3BARH 0xE61600F0 // R/W 32 CA57 CPU3 Boot Address Register for 64-bit mode H +#define RST_CA57CPU3BARL 0xE61600F4 // R/W 32 CA57 CPU3 Boot Address Register for 64-bit mode L +#define RST_CA53CPU0BARH 0xE6160080 // R/W 32 CA53 CPU0 Boot Address Register for 64-bit mode H +#define RST_CA53CPU0BARL 0xE6160084 // R/W 32 CA53 CPU0 Boot Address Register for 64-bit mode L +#define RST_CA53CPU1BARH 0xE6160090 // R/W 32 CA53 CPU1 Boot Address Register for 64-bit mode H +#define RST_CA53CPU1BARL 0xE6160094 // R/W 32 CA53 CPU1 Boot Address Register for 64-bit mode L +#define RST_CA53CPU2BARH 0xE61600A0 // R/W 32 CA53 CPU2 Boot Address Register for 64-bit mode H +#define RST_CA53CPU2BARL 0xE61600A4 // R/W 32 CA53 CPU2 Boot Address Register for 64-bit mode L +#define RST_CA53CPU3BARH 0xE61600B0 // R/W 32 CA53 CPU3 Boot Address Register for 64-bit mode H +#define RST_CA53CPU3BARL 0xE61600B4 // R/W 32 CA53 CPU3 Boot Address Register for 64-bit mode L +#define RST_APBSFTYCHKR 0xE616005C // R/W 32 APB bus Safety Check Register +#define RST_STBCHR0 0xE6160100 // R/W 32 Standby Flag Register 0 +#define RST_STBCHR1 0xE6160104 // R/W 32 Standby Flag Register 1 +#define RST_STBCHR2 0xE6160108 // R/W 32 Standby Flag Register 2 +#define RST_STBCHR3 0xE616010C // R/W 32 Standby Flag Register 3 +#define RST_STBCHR4 0xE6160120 // R/W 32 Standby Flag Register 4 +#define RST_STBCHR5 0xE6160124 // R/W 32 Standby Flag Register 5 +#define RST_STBCHR6 0xE6160128 // R/W 32 Standby Flag Register 6 +#define RST_STBCHR7 0xE616012C // R/W 32 Standby Flag Register 7 +#define RST_SRESCR 0xE6160110 // R/W 32 Soft Power On Reset Control Register +#define RST_RRSTFR 0xE6160114 // R/W 32 RT Reset Flag Register +#define RST_SRSTFR 0xE6160118 // R/W 32 SYS Reset Flag Register +#define RST_SCPTCSR 0xE6160180 // R/W 32 Secure Protect Control/Status Register +#define RST_SCERMIDR 0xE6160184 // R 32 Secure Error Master ID Register +#define RST_SCERADR 0xE6160188 // R 32 Secure Error Address Register +#define RST_SAPTCSR 0xE6160190 // R/W 32 Safety Protect Control/Status Register +#define RST_SAERMIDR 0xE6160194 // R 32 Safety Error Master ID Register +#define RST_SAERADR 0xE6160198 // R 32 Safety Error Address Register + +#define MODEMR_BOOT_CPU_MASK (0x000000C0U) +#define MODEMR_BOOT_CPU_CR7 (0x000000C0U) +#define MODEMR_BOOT_CPU_CA57 (0x00000000U) +#define MODEMR_BOOT_CPU_CA53 (0x00000040U) +#define MODEMR_BOOT_DEV_MASK (0x0000001EU) +#define MODEMR_BOOT_DEV_HYPERFLASH160 (0x00000004U) +#define MODEMR_BOOT_DEV_HYPERFLASH80 (0x00000006U) +#define MODEMR_BOOT_DEV_QSPI_FLASH40 (0x00000008U) +#define MODEMR_BOOT_DEV_QSPI_FLASH80 (0x0000000CU) +#define MODEMR_BOOT_DEV_OCTAL_FLASH (0x0000000EU) +#define MODEMR_BOOT_DEV_EMMC_25X1 (0x0000000AU) +#define MODEMR_BOOT_DEV_EMMC_50X8 (0x0000001AU) +#define MODEMR_BOOT_DEV_SCIF_DOWNLOAD (0x0000001EU) +#define MODEMR_BOOT_DEV_USB_DOWNLOAD (0x0000001CU) +#define MODEMR_BOOT_PLL_MASK (0x00006000U) +#define MODEMR_BOOT_PLL_SHIFT (13U) + + +// +#define MFIS_SOFTMDR (0xE6260600U) + + +//SCIF0 +#define SCIF0_SCSMR 0xE6E60000 // R/W 16 Serial mode register +#define SCIF0_SCBRR 0xE6E60004 // R/W 8 Bit rate register +#define SCIF0_SCSCR 0xE6E60008 // R/W 16 Serial control register +#define SCIF0_SCFTDR 0xE6E6000C // W 8 Transmit FIFO data register +#define SCIF0_SCFSR 0xE6E60010 // R/W 16 Serial status register +#define SCIF0_SCFRDR 0xE6E60014 // R 8 Receive FIFO data register +#define SCIF0_SCFCR 0xE6E60018 // R/W 16 FIFO control register +#define SCIF0_SCFDR 0xE6E6001C // R 16 FIFO data count register +#define SCIF0_SCSPTR 0xE6E60020 // R/W 16 Serial port register +#define SCIF0_SCLSR 0xE6E60024 // R/W 16 Line status register +#define SCIF0_DL 0xE6E60030 // R/W 16 Frequency division register +#define SCIF0_CKS 0xE6E60034 // R/W 16 Clock Select register + + +//SCIF2 +#define SCIF2_SCSMR 0xE6E88000 // R/W 16 Serial mode register +#define SCIF2_SCBRR 0xE6E88004 // R/W 8 Bit rate register +#define SCIF2_SCSCR 0xE6E88008 // R/W 16 Serial control register +#define SCIF2_SCFTDR 0xE6E8800C // W 8 Transmit FIFO data register +#define SCIF2_SCFSR 0xE6E88010 // R/W 16 Serial status register +#define SCIF2_SCFRDR 0xE6E88014 // R 8 Receive FIFO data register +#define SCIF2_SCFCR 0xE6E88018 // R/W 16 FIFO control register +#define SCIF2_SCFDR 0xE6E8801C // R 16 FIFO data count register +#define SCIF2_SCSPTR 0xE6E88020 // R/W 16 Serial port register +#define SCIF2_SCLSR 0xE6E88024 // R/W 16 Line status register +#define SCIF2_DL 0xE6E88030 // R/W 16 Frequency division register +#define SCIF2_CKS 0xE6E88034 // R/W 16 Clock Select register + + +/* Appendix A. */ +#define PRR (0xFFF00044) /* Product Register */ +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) +#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */ +#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ +#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */ +#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */ +#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */ +#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */ +#define PRR_PRODUCT_V3H (0x00005600U) +#define PRR_CUT_10 (0x00U) +#define PRR_CUT_11 (0x01U) +#define PRR_CUT_20 (0x10U) +#define PRR_CUT_30 (0x20U) +#define PRR_CUT_MAJOR_MASK (0x000000F0U) +#define PRR_CUT_MINOR_MASK (0x0000000FU) +#define PRR_PRODUCT_SHIFT (8U) +#define PRR_MAJOR_SHIFT (4U) +#define PRR_MINOR_SHIFT (0U) +#define PRR_MAJOR_OFFSET (1U) + +#endif /* REG_RCARGEN3_H */ diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/include/scifdrv0.h b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/scifdrv0.h new file mode 100644 index 0000000..31af5d2 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/scifdrv0.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef SCIFDRV0_H +#define SCIFDRV0_H + +int32_t PutCharSCIF0(char outChar); +void PowerOnScif0(void); +void WaitPutScif0SendEnd(void); +void InitScif0_SCIFCLK(void); + +#endif /* SCIFDRV0_H */ diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/include/scifdrv0_v3h.h b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/scifdrv0_v3h.h new file mode 100644 index 0000000..152310b --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/scifdrv0_v3h.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef SCIFDRV0_V3H_H +#define SCIFDRV0_V3H_H + +int32_t PutCharSCIF0_v3h(char outChar); +void PowerOnScif0_v3h(void); +void WaitPutScif0_v3h_SendEnd(void); +void InitScif0_v3h_SCIFCLK(void); + +#endif /* SCIFDRV0_V3H_H */ diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/include/scifdrv2.h b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/scifdrv2.h new file mode 100644 index 0000000..582caf2 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/scifdrv2.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef SCIFDRV2_H +#define SCIFDRV2_H + +int32_t PutCharSCIF2(char outChar); +void PowerOnScif2(void); +void WaitPutScif2SendEnd(void); +void InitScif2_SCIFCLK(void); +void InitScif2_SCIFCLK_D3(void); + +#endif /* SCIFDRV2_H */ diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/include/types.h b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/types.h new file mode 100644 index 0000000..c7f91b8 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/include/types.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef TYPES_H +#define TYPES_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +/**************************************************************************** + * File Name: types.h + * Contents : Types Define + ****************************************************************************/ + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef SUCCESS +#define SUCCESS 0UL +#endif + +#ifndef YES +#define YES 1 +#endif + +#ifndef NO +#define NO 0 +#endif + +#ifndef NULL +#define NULL (void *)0UL +#endif + +#define PFAR /**/ +#define FFAR /**/ + +typedef signed char BYTE; +typedef signed short WORD; +typedef signed long DWORD; + +#if 0 +typedef unsigned long uint32; +typedef long int32; +typedef unsigned short uint16; +typedef short int16; +typedef unsigned char uint8; +typedef char int8; +typedef unsigned int uint; +typedef unsigned char bool8; +typedef unsigned long long uint64; + +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef signed long int32_t; +typedef unsigned long uint32_t; +typedef unsigned long long int uint64_t; +#endif + +typedef signed char B; /* signed 8-bit integer */ +typedef long W; /* signed 32-bit integer */ +typedef unsigned char UB; /* unsigned 8-bit integer */ +typedef unsigned long UW; /* unsigned 32-bit integer */ + +typedef short H; /* signed 16-bit integer */ +typedef unsigned short UH; /* unsigned 16-bit integer */ + +typedef int INT; +typedef unsigned int UINT; + +typedef INT BOOL; + +typedef void (FFAR *FP)(); +typedef INT FN; +typedef INT ID; +typedef INT BOOL_ID; +typedef INT HNO; +typedef INT RNO; +typedef INT RDVNO; +typedef UINT RDVPTN; +typedef UINT ATR; +typedef UINT MODE; +typedef INT ER; +typedef INT PRI; +typedef ER ER_ID; +typedef UINT STAT; +typedef INT ER_UINT; +typedef UINT TEXPTN; +typedef UINT FLGPTN; +typedef UINT INHNO; +typedef UINT INTNO; + +typedef unsigned long SIZE; +typedef W TMO; +typedef W DLYTIME; +typedef DLYTIME RELTIM; +typedef void PFAR *VP; +typedef VP VP_INT; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/init_scif.c b/IPL/SDK/v3h/src/Dummy_CA53_Program/init_scif.c new file mode 100644 index 0000000..28d37e1 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/init_scif.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + + +#include "reg_rcargen3.h" +#include "common.h" +#include "scifdrv0.h" +#include "scifdrv0_v3h.h" +#include "scifdrv2.h" +#include "init_scif.h" + + + +void InitScif(void) +{ + uint32_t product; + + product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; + switch (product) { + case PRR_PRODUCT_H3: /* H3, M3 and M3N setting values are same */ + case PRR_PRODUCT_M3: + case PRR_PRODUCT_M3N: + InitScif2_SCIFCLK(); + break; + case PRR_PRODUCT_D3: + InitScif2_SCIFCLK_D3(); + break; + case PRR_PRODUCT_V3M: + InitScif0_SCIFCLK(); + break; + case PRR_PRODUCT_V3H: +// InitScif0_v3h_SCIFCLK(); + break; + default: + break; + } +} diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/main.c b/IPL/SDK/v3h/src/Dummy_CA53_Program/main.c new file mode 100644 index 0000000..7b5d50b --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/main.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#include +#include "common.h" +#include "main.h" +#include "devdrv.h" + + + +static void StartMess(void); + +void Main(void) +{ + volatile uint32_t i; + + for (i = 0; i < 0x00600000U; i++) { + ; + } + + StartMess(); + + while(1) { + __asm__ volatile ("wfi"); + } +} + + +static void StartMess(void) +{ + PutStr(" ",1); + PutStr("Dummy CA53 Program",1); + PutStr("Dummy CA53 Program boot end",1); +} + + diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/makefile b/IPL/SDK/v3h/src/Dummy_CA53_Program/makefile new file mode 100644 index 0000000..6c175b1 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/makefile @@ -0,0 +1,169 @@ +# +# Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. +# + +#/* Select BOOT("CR7"or"ICUMXA")************************* +ifeq ("$(BOOT)", "") +BOOT = ICUMXA +endif + +#/* Select AArch("64"or"32" )*************************************************** +ifeq ("$(AArch)", "") +AArch = 64 +endif + +#CPU +ifeq ("$(AArch)", "64") +CPU = -march=armv8-a +endif +ifeq ("$(AArch)", "32") +CPU = -mcpu=cortex-r7 +endif + +ifeq ("$(AArch)", "32") + THUMB = -marm + AS_NEON = + CC_NEON = + ALIGN = -mno-unaligned-access +endif +ifeq ("$(AArch)", "64") + THUMB = + AS_NEON = + CC_NEON = -mgeneral-regs-only + ALIGN = -mstrict-align +endif + +ifeq ("$(AArch)", "32") + AArch32_64 = AArch32 + BOOTDIR = AArch32_boot + OUTPUT_DIR = AArch32_output + OBJECT_DIR = AArch32_obj + CROSS_COMPILE ?= arm-eabi- +endif +ifeq ("$(AArch)", "64") + AArch32_64 = AArch64 + BOOTDIR = AArch64_boot + OUTPUT_DIR = AArch64_output + OBJECT_DIR = AArch64_obj + CROSS_COMPILE ?= aarch64-elf- +endif + +ifeq ("$(BOOT)", "CR7") +# BOOT_DEF = Writer + MEMORY_DEF = memory_cr7.def + FILE_NAME = $(OUTPUT_DIR)/AArch$(AArch)_Dummy_CA53_Program$(FILENAME_ADD) +endif + +ifeq ("$(BOOT)", "ICUMXA") +# BOOT_DEF = Writer + MEMORY_DEF = memory_icumxa.def + FILE_NAME = $(OUTPUT_DIR)/AArch$(AArch)_Dummy_CA53_Program$(FILENAME_ADD) +endif + +LIBS = -L$(subst libc.a, ,$(shell $(CC) -print-file-name=libc.a 2> /dev/null)) -lc +LIBS += -L$(subst libgcc.a, ,$(shell $(CC) -print-libgcc-file-name 2> /dev/null)) -lgcc + +INCLUDE_DIR = include + +OUTPUT_FILE = $(FILE_NAME).axf + +#Object file +OBJ_FILE_BOOT = \ + $(OBJECT_DIR)/boot_mon.o \ + $(OBJECT_DIR)/stack.o + +SRC_FILE := \ + main.c \ + init_scif.c \ + scifdrv0.c \ + scifdrv0_v3h.c \ + scifdrv2.c \ + devdrv.c \ + common.c + + +ifeq ("$(BOOT)", "WRITER_WITH_CERT") + SRC_FILE += cert_param.c +endif + +OBJ_FILE := $(addprefix $(OBJECT_DIR)/,$(patsubst %.c,%.o,$(SRC_FILE))) + +#Dependency File +DEPEND_FILE = $(patsubst %.lib, ,$(OBJ_FILE:%.o=%.d)) + +################################################### +#C compiler +CC = $(CROSS_COMPILE)gcc +#Assembler +AS = $(CROSS_COMPILE)as +#Linker +LD = $(CROSS_COMPILE)ld +#Liblary +AR = $(CROSS_COMPILE)ar +#Object dump +OBJDMP = $(CROSS_COMPILE)objdump +#Object copy +OBJCOPY = $(CROSS_COMPILE)objcopy + +#clean +CL = rm -rf + +################################################### +# Suffixes +.SUFFIXES : .s .c .o + +################################################### +# Command + +.PHONY: all +all: $(OBJECT_DIR) $(OUTPUT_DIR) $(OBJ_FILE_BOOT) $(OBJ_FILE) $(OUTPUT_FILE) + +#------------------------------------------ +# Make Directory +#------------------------------------------ +$(OBJECT_DIR): + -mkdir "$(OBJECT_DIR)" + +$(OUTPUT_DIR): + -mkdir "$(OUTPUT_DIR)" + +#------------------------------------------ +# Compile +#------------------------------------------ +$(OBJECT_DIR)/%.o:$(BOOTDIR)/%.s + $(AS) -g $(CPU) $(AS_NEON) --MD $(patsubst %.o,%.d,$@) -I $(BOOTDIR) -I $(INCLUDE_DIR) $< -o $@ --defsym $(AArch32_64)=0 + +$(OBJECT_DIR)/%.o:%.c + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + $(CC) -g -Os $(ALIGN) $(CPU) $(CC_NEON) $(THUMB) -MMD -MP -c -I $(BOOTDIR) -I $(INCLUDE_DIR) $< -o $@ -D$(AArch32_64)=0 $(CFLAGS) + +#------------------------------------------ +# Linker +#------------------------------------------ +$(OUTPUT_FILE): $(OBJ_FILE_BOOT) $(OBJ_FILE) $(MEMORY_DEF) + $(LD) $(OBJ_FILE_BOOT) $(OBJ_FILE) \ + -T '$(MEMORY_DEF)' \ + -o '$(OUTPUT_FILE)' \ + -Map '$(FILE_NAME).map' \ + -static \ + $(LIBS) + +# Make SREC file + $(OBJCOPY) -O srec --srec-forceS3 "$(OUTPUT_FILE)" "$(FILE_NAME).srec" + +# Make Binary file + $(OBJCOPY) -O binary "$(OUTPUT_FILE)" "$(FILE_NAME).bin" + +# Dis assemble + $(OBJDMP) -d -S "$(OUTPUT_FILE)" > "$(FILE_NAME)_disasm.txt" + +# Time Stamp + @echo ========== %date% %time% ========== + @echo ========== !!! Compile Complete !!! ========== + + +.PHONY: clean +clean: + $(CL) $(OBJECT_DIR)/* $(OUTPUT_DIR)/* + +-include $(DEPEND_FILE) diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/memory_cr7.def b/IPL/SDK/v3h/src/Dummy_CA53_Program/memory_cr7.def new file mode 100644 index 0000000..8a9297e --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/memory_cr7.def @@ -0,0 +1,38 @@ +MEMORY { + RAM (rwxa): ORIGIN = 0x44000000, LENGTH = 0x00014000 +} + +SECTIONS +{ + .text : { + *(.text*) + *(.rodata*) + . = NEXT(64); + __RO_END__ = .; + } > RAM + + .data : { + __DATA_START__ = .; + *(.data) + . = NEXT(64); + __DATA_END__ = .; + } > RAM + + __DATA_SIZE__ = SIZEOF(.data); + + .bss : { + __BSS_START__ = .; + *(.bss) + *(COMMON) + . = NEXT(64); + __BSS_END__ = .; + } > RAM + + stacks (NOLOAD) : ALIGN(64) { + __STACKS_START__ = .; + KEEP(*(writer_stack)) + __STACKS_END__ = .; + } > RAM + + __BSS_SIZE__ = SIZEOF(.bss); +} diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/memory_icumxa.def b/IPL/SDK/v3h/src/Dummy_CA53_Program/memory_icumxa.def new file mode 100644 index 0000000..87c822c --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/memory_icumxa.def @@ -0,0 +1,38 @@ +MEMORY { + RAM (rwxa): ORIGIN = 0x46400000, LENGTH = 0x00014000 +} + +SECTIONS +{ + .text : { + *(.text*) + *(.rodata*) + . = NEXT(64); + __RO_END__ = .; + } > RAM + + .data : { + __DATA_START__ = .; + *(.data) + . = NEXT(64); + __DATA_END__ = .; + } > RAM + + __DATA_SIZE__ = SIZEOF(.data); + + .bss : { + __BSS_START__ = .; + *(.bss) + *(COMMON) + . = NEXT(64); + __BSS_END__ = .; + } > RAM + + stacks (NOLOAD) : ALIGN(64) { + __STACKS_START__ = .; + KEEP(*(writer_stack)) + __STACKS_END__ = .; + } > RAM + + __BSS_SIZE__ = SIZEOF(.bss); +} diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/scifdrv0.c b/IPL/SDK/v3h/src/Dummy_CA53_Program/scifdrv0.c new file mode 100644 index 0000000..1a7bcaf --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/scifdrv0.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#include "common.h" +#include "scifdrv0.h" +#include "bit.h" +#include "reg_rcargen3.h" + + +////////////////////////////////////////////////////////////////////////////////// +// // +// Debug Seirial(SCIF0) // +// // +////////////////////////////////////////////////////////////////////////////////// +int32_t PutCharSCIF0(char outChar) +{ + while(!(0x60 & *((volatile uint16_t*)SCIF0_SCFSR) )); + *((volatile uint8_t*)SCIF0_SCFTDR) = outChar; + *((volatile uint16_t*)SCIF0_SCFSR) &= ~0x60; /* TEND,TDFE clear */ + return(0); +} + +void PowerOnScif0(void) +{ + uint32_t dataL; + + dataL = *((volatile uint32_t*)CPG_MSTPSR2); + if(dataL & BIT7){ // case SCIF0 + dataL &= ~BIT7; + *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; + *((volatile uint32_t*)CPG_SMSTPCR2) = dataL; + while( BIT7 & *((volatile uint32_t*)CPG_MSTPSR2) ); // wait bit=0 + } +} + +void WaitPutScif0SendEnd(void) +{ + uint16_t dataW; + uint32_t loop; + + loop=1; + while(loop){ + dataW = *((volatile uint16_t*)SCIF0_SCFSR); + if(dataW & BIT6) loop = 0; + } +} + +void InitScif0PinFunction(void) +{ + uint32_t dataL; + + /* SCIF0 */ + dataL = *((volatile uint32_t*)PFC_IPSR7); + dataL &= ~(0x0FF00000); + dataL |= 0x04400000; /* IPSR7[27:24]=4'b0100, IPSR7[23:20]=4'b0100 */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_IPSR7) = dataL; + + dataL = *((volatile uint32_t*)PFC_GPSR4); + dataL |= 0x00000030; /* GPSR4[5],GPSR4[4] */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_GPSR4) = dataL; +} + +void InitScif0_SCIFCLK(void) +{ + uint16_t dataW; + + PowerOnScif0(); + + InitScif0PinFunction(); + + dataW = *((volatile uint16_t*)SCIF0_SCLSR); /* dummy read */ + *((volatile uint16_t*)SCIF0_SCLSR) = 0x0000; /* clear ORER bit */ + *((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear all error bit */ + + *((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/ + *((volatile uint16_t*)SCIF0_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */ + *((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */ + + *((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */ + *((volatile uint16_t*)SCIF0_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, Po/1 */ + SoftDelay(100); + *((volatile uint8_t*)SCIF0_SCBRR) = 0x11; /* 115200bps@66MHz */ + SoftDelay(100); + *((volatile uint16_t*)SCIF0_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */ + *((volatile uint16_t*)SCIF0_SCSCR) = 0x0030; /* enable TE, RE; SC_CLK=input */ + + SoftDelay(100); +} diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/scifdrv0_v3h.c b/IPL/SDK/v3h/src/Dummy_CA53_Program/scifdrv0_v3h.c new file mode 100644 index 0000000..aa3d2af --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/scifdrv0_v3h.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#include "common.h" +#include "scifdrv0.h" +#include "bit.h" +#include "reg_rcargen3.h" + + +////////////////////////////////////////////////////////////////////////////////// +// // +// Debug Seirial(SCIF0) // +// // +////////////////////////////////////////////////////////////////////////////////// +int32_t PutCharSCIF0_v3h(char outChar) +{ + while(!(0x60 & *((volatile uint16_t*)SCIF0_SCFSR) )); + *((volatile uint8_t*)SCIF0_SCFTDR) = outChar; + *((volatile uint16_t*)SCIF0_SCFSR) &= ~0x60; /* TEND,TDFE clear */ + return(0); +} + +void PowerOnScif0_v3h(void) +{ + uint32_t dataL; + + dataL = *((volatile uint32_t*)CPG_MSTPSR2); + if(dataL & BIT7){ // case SCIF0 + dataL &= ~BIT7; + *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; + *((volatile uint32_t*)CPG_SMSTPCR2) = dataL; + while( BIT7 & *((volatile uint32_t*)CPG_MSTPSR2) ); // wait bit=0 + } +} + +void WaitPutScif0_v3h_SendEnd(void) +{ + uint16_t dataW; + uint32_t loop; + + loop=1; + while(loop){ + dataW = *((volatile uint16_t*)SCIF0_SCFSR); + if(dataW & BIT6) loop = 0; + } +} + +void InitScif0_v3h_PinFunction(void) +{ + uint32_t dataL; + + /* SCIF0 */ + dataL = *((volatile uint32_t*)PFC_IPSR7); + dataL &= ~(0x0FF00000); + dataL |= 0x04400000; /* IPSR7[27:24]=4'b0100, IPSR7[23:20]=4'b0100 */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_IPSR7) = dataL; + + dataL = *((volatile uint32_t*)PFC_GPSR4); + dataL |= 0x00000030; /* GPSR4[5],GPSR4[4] */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_GPSR4) = dataL; +} + +void InitScif0_v3h_SCIFCLK(void) +{ + uint16_t dataW; + + PowerOnScif0_v3h(); + + InitScif0_v3h_PinFunction(); + + dataW = *((volatile uint16_t*)SCIF0_SCLSR); /* dummy read */ + *((volatile uint16_t*)SCIF0_SCLSR) = 0x0000; /* clear ORER bit */ + *((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear all error bit */ + + *((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/ + *((volatile uint16_t*)SCIF0_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */ + *((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */ + + *((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */ + *((volatile uint16_t*)SCIF0_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, Po/1 */ + SoftDelay(100); + *((volatile uint8_t*)SCIF0_SCBRR) = 0x11; /* 115200bps@66MHz */ + SoftDelay(100); + *((volatile uint16_t*)SCIF0_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */ + *((volatile uint16_t*)SCIF0_SCSCR) = 0x0030; /* enable TE, RE; SC_CLK=input */ + + SoftDelay(100); +} diff --git a/IPL/SDK/v3h/src/Dummy_CA53_Program/scifdrv2.c b/IPL/SDK/v3h/src/Dummy_CA53_Program/scifdrv2.c new file mode 100644 index 0000000..6e087dd --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_CA53_Program/scifdrv2.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#include "common.h" +#include "scifdrv2.h" +#include "bit.h" +#include "reg_rcargen3.h" + + +////////////////////////////////////////////////////////////////////////////////// +// // +// Debug Seirial(SCIF2) // +// // +////////////////////////////////////////////////////////////////////////////////// +int32_t PutCharSCIF2(char outChar) +{ + while(!(0x60 & *((volatile uint16_t*)SCIF2_SCFSR) )); + *((volatile unsigned char*)SCIF2_SCFTDR) = outChar; + *((volatile uint16_t*)SCIF2_SCFSR) &= ~0x60; /* TEND,TDFE clear */ + return(0); +} + +void PowerOnScif2(void) +{ + uint32_t dataL; + + dataL = *((volatile uint32_t*)CPG_MSTPSR3); + if(dataL & BIT10){ // case SCIF2(IrDA) Standby + dataL &= ~BIT10; + *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; + *((volatile uint32_t*)CPG_SMSTPCR3) = dataL; + while( BIT10 & *((volatile uint32_t*)CPG_MSTPSR3) ); // wait bit=0 + } +} + +void WaitPutScif2SendEnd(void) +{ + uint16_t dataW; + uint32_t loop; + + loop=1; + while(loop){ + dataW = *((volatile uint16_t*)SCIF2_SCFSR); + if(dataW & BIT6) loop = 0; + } +} + +void InitScif2PinFunction(void) +{ + uint32_t dataL; + + /* SCIF2 */ + dataL = *((volatile uint32_t*)PFC_IPSR13); + dataL &= ~0x000000FF; /* IP13[7:4]=4'b0000, IP13[3:0]=4'b0000 */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_IPSR13) = dataL; + + dataL = *((volatile uint32_t*)PFC_GPSR5); + dataL |= 0x00000C00; /* GP5[11],GP5[10] */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_GPSR5) = dataL; +} + +void InitScif2_SCIFCLK(void) +{ + uint16_t dataW; + uint32_t prr; + + PowerOnScif2(); + + InitScif2PinFunction(); + + dataW = *((volatile uint16_t*)SCIF2_SCLSR); /* dummy read */ + *((volatile uint16_t*)SCIF2_SCLSR) = 0x0000; /* clear ORER bit */ + *((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear all error bit */ + + *((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/ + *((volatile uint16_t*)SCIF2_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */ + *((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */ + + *((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */ + *((volatile uint16_t*)SCIF2_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, Po/1 */ + SoftDelay(100); + +#ifdef Writer + *((volatile uint8_t*)SCIF2_SCBRR) = 0x11; /* 115200bps@66MHz */ +#else /* Writer */ + prr = *((volatile uint32_t*)PRR); + prr &= (PRR_PRODUCT_MASK | PRR_CUT_MASK); + + if (prr == PRR_PRODUCT_H3 | PRR_CUT_10) { + *((volatile uint8_t*)SCIF2_SCBRR) = 0x08; /* 115200bps@33MHz */ + } else { + *((volatile uint8_t*)SCIF2_SCBRR) = 0x11; /* 115200bps@66MHz */ + } +#endif /* Writer */ + + SoftDelay(100); + *((volatile uint16_t*)SCIF2_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */ + *((volatile uint16_t*)SCIF2_SCSCR) = 0x0030; /* enable TE, RE; SC_CLK=input */ + + SoftDelay(100); +} + +void InitScif2PinFunction_D3(void) +{ + uint32_t dataL; + + /* SCIF2 */ + dataL = *((volatile uint32_t*)PFC_IPSR12); + dataL &= ~0x00000F00U; /* IP12[11:8]=4'b0000 */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_IPSR12) = dataL; + + dataL = *((volatile uint32_t*)PFC_GPSR4); + dataL |= 0x0C000000U; /* GP4[27],GP4[26] */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_GPSR4) = dataL; + +} + +void InitScif2_SCIFCLK_D3(void) +{ + uint16_t dataW; + uint32_t md; + uint32_t sscg; + + PowerOnScif2(); + + InitScif2PinFunction_D3(); + + md = *((volatile uint32_t*)RST_MODEMR); + sscg = (md & 0x00001000) >> 12; + + dataW = *((volatile uint16_t*)SCIF2_SCLSR); /* dummy read */ + *((volatile uint16_t*)SCIF2_SCLSR) = 0x0000; /* clear ORER bit */ + *((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear all error bit */ + + *((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/ + *((volatile uint16_t*)SCIF2_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */ + *((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */ + + *((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */ + *((volatile uint16_t*)SCIF2_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, S3D4/1 */ + SoftDelay(100); + + if(sscg == 0x0){ //MD12=0 (SSCG off) : S3D4C=66.6MHz + *((volatile uint8_t*)SCIF2_SCBRR) = 0x11; /* 115200 bit-rate */ + } + else if(sscg == 0x1){ //MD12=1 (SSCG on) : S3D4C=62.5MHz + *((volatile uint8_t*)SCIF2_SCBRR) = 0x10; /* 115200 bit-rate */ + } + SoftDelay(100); + *((volatile uint16_t*)SCIF2_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */ + *((volatile uint16_t*)SCIF2_SCSCR) = 0x0030; /* enable TE, RE; SCK pin is not used */ + SoftDelay(100); +} diff --git a/IPL/SDK/v3h/src/Dummy_FW/Makefile b/IPL/SDK/v3h/src/Dummy_FW/Makefile new file mode 100644 index 0000000..7dbcb25 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/Makefile @@ -0,0 +1,126 @@ +# ****************************************************************************** +# * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. +# * +# * DESCRIPTION : makefile for Dummy FW +# ****************************************************************************** + +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +INCLUDE_DIR = -Iinclude + +OUTDIR := build + +#output file name +FILE_NAME = dummy_fw + +OUTPUT_FILE = $(FILE_NAME).elf + + +#object file name +OBJ_FILE = common/mem_io.o \ + common/scif.o \ + common/log.o \ + common/micro_wait.o \ + common/remap.o \ + fw/dummy_fw_main.o \ + fw/dummy_fw.o \ + fw/vecttbl.o + + + + +#linker script name +MEMORY_DEF = fw/dummy_fw.ld + + +################################################### + +# Debug build +DEBUG:=0 + +# Process DEBUG flag +$(eval $(call assert_boolean,DEBUG)) +$(eval $(call add_define,DEBUG)) +ifeq (${DEBUG},0) + $(eval $(call add_define,NDEBUG)) +ASFLAGS += -G -dwarf2 +CFLAGS += -G -dwarf2 -Ogeneral +else +ASFLAGS += -G -dwarf2 +CFLAGS += -G -dwarf2 -Odebug +endif + + + +################################################### + +OUTDIR_REL := $(OUTDIR)/release +OUTDIR_OBJ := $(OUTDIR)/obj + +OBJ_FILE := $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o) + + +CC = cxrh850 +AS = cxrh850 +LD = cxrh850 +OC = gsrec +OD = gdump + +ASFLAGS += -asm="-preprocess_assembly_files" \ + -asm="-nostartfiles" \ + -D__ASSEMBLY \ + $(INCLUDE_DIR) $(DEFINES) + +CFLAGS += -nostartfiles \ + -c99 \ + $(INCLUDE_DIR) $(DEFINES) + +LDFLAGS = -nostartfiles + +BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__ + +################################################### +.SUFFIXES : .s .c .o + +################################################### +# command + +.PHONY: all +all: $(OUTPUT_FILE) + +################################################### +# Linker +################################################### +$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE) + @echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' > $(OUTDIR_OBJ)/build_message.c + @$(CC) $(CFLAGS) -o $(OUTDIR_OBJ)/build_message.o -c $(OUTDIR_OBJ)/build_message.c + + @$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \ + -T $(MEMORY_DEF) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE) \ + $(LDFLAGS) \ + -map=$(OUTDIR_REL)/$(FILE_NAME).map + + @$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).srec + @$(OD) -full -ytext $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE) -o $(OUTDIR_REL)/$(OUTPUT_FILE:%.elf=%.bin) + + +################################################### +# Compile +################################################### + +$(OUTDIR_OBJ)/%.o:%.c + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + @$(CC) $(CFLAGS) -o $@ -c $< + +$(OUTDIR_OBJ)/%.o:%.S + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + @$(AS) $(ASFLAGS) -o $@ -c $< + + +.PHONY: clean +clean: + @rm -rf $(OUTDIR) diff --git a/IPL/SDK/v3h/src/Dummy_FW/common/log.c b/IPL/SDK/v3h/src/Dummy_FW/common/log.c new file mode 100644 index 0000000..e857dfb --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/common/log.c @@ -0,0 +1,34 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Log driver + ******************************************************************************/ + +#include +#include +#include +#include + +void local_printf(const char *fmt, ...) +{ + va_list ap; + static char buffer[1024]; + int32_t num; + uint32_t loop; + + va_start(ap, fmt); + num = vsprintf(buffer, fmt, ap); + va_end(ap); + + if (0 < num) { + for (loop = 0; loop < num; loop++) { + (void)console_putc(buffer[loop]); + if (buffer[loop] == '\n') { + (void)console_putc('\r'); + } + } + } else { + panic(); + } +} + diff --git a/IPL/SDK/v3h/src/Dummy_FW/common/mem_io.c b/IPL/SDK/v3h/src/Dummy_FW/common/mem_io.c new file mode 100644 index 0000000..397be39 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/common/mem_io.c @@ -0,0 +1,48 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : memory access driver + ******************************************************************************/ + +#include + +void mem_write8(uintptr_t addr, uint8_t data) +{ + *(volatile uint8_t*)addr = data; +} +uint8_t mem_read8(uintptr_t addr) +{ + return (*(volatile uint8_t*)addr); +} + +void mem_write16(uintptr_t addr, uint16_t data) +{ + *(volatile uint16_t*)addr = data; +} +uint16_t mem_read16(uintptr_t addr) +{ + return (*(volatile uint16_t*)addr); +} + +void mem_write32(uintptr_t addr, uint32_t data) +{ + *(volatile uint32_t*)addr = data; +} +uint32_t mem_read32(uintptr_t addr) +{ + return (*(volatile uint32_t*)addr); +} + +void mem_write64(uintptr_t addr, uint64_t data) +{ + *(volatile uint64_t*)addr = data; +} +uint64_t mem_read64(uintptr_t addr) +{ + return (*(volatile uint64_t*)addr); +} + +void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set) +{ + mem_write32(addr, (mem_read32(addr) & ~clr) | set); +} diff --git a/IPL/SDK/v3h/src/Dummy_FW/common/micro_wait.c b/IPL/SDK/v3h/src/Dummy_FW/common/micro_wait.c new file mode 100644 index 0000000..9fd8659 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/common/micro_wait.c @@ -0,0 +1,72 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Time wait driver + ******************************************************************************/ + +#include +#include + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + +#define INTICUOSTM0 (*(volatile uint16_t*)0xFFFEEA14U) +#define INTCR_RF (1U <<12) + +#define OSTM0_BASE (0xFFFEE000UL) +#define OSTM0CMP (*(volatile uint32_t*)(OSTM0_BASE)) +#define OSTM0CNT (*(volatile uint32_t*)(OSTM0_BASE + 0x4UL)) +#define OSTM0TE (*(volatile uint8_t*)(OSTM0_BASE + 0x10UL)) +#define OSTM0TS (*(volatile uint8_t*)(OSTM0_BASE + 0x14UL)) +#define OSTM0TT (*(volatile uint8_t*)(OSTM0_BASE + 0x18UL)) +#define OSTM0CTL (*(volatile uint8_t*)(OSTM0_BASE + 0x20L)) +#define OSTM0EMU (*(volatile uint32_t*)(OSTM0_BASE + 0x24L)) + +#define OSTM0TS_TS (1U) /* b0:1: Start */ +#define OSTM0TT_TT (1U) /* b0:1: Stop */ +#define OSTM0TE_TE (1U) /* b0:1: Counter enabled */ +#define OSTM0CMP_MICRO_VALUE (0x190UL) /* PCLK=400MHz(400=0x190 = 1us) */ + +#define OSTM0CTL_MD10 (0x2U) /* b1:1: Free-run compare mode(Start:0 Counting Direction:up) */ + /* b0:0: Interrupts when counting starts are enabled */ + +/************************************************************************************************/ +/* Prototypes */ +/************************************************************************************************/ +static void start_microtimer(uint32_t val); +static void stop_microtimer(void); + +static void start_microtimer(uint32_t val) +{ + OSTM0TT = OSTM0TT_TT; + OSTM0CMP = val; + OSTM0CTL = OSTM0CTL_MD10; + OSTM0TS = OSTM0TS_TS; +} + +static void stop_microtimer(void) +{ + OSTM0TT = OSTM0TT_TT; +} + +void micro_wait(uint32_t count_us) +{ + uint32_t val; + + if (count_us == 0) { + return; + } + val = count_us * OSTM0CMP_MICRO_VALUE; + start_microtimer(val); + + while (1) { + if (INTICUOSTM0 & INTCR_RF) { + INTICUOSTM0 &= (uint16_t)(~INTCR_RF); + stop_microtimer(); + break; + } + + } +} + diff --git a/IPL/SDK/v3h/src/Dummy_FW/common/remap.c b/IPL/SDK/v3h/src/Dummy_FW/common/remap.c new file mode 100644 index 0000000..5b9f6f4 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/common/remap.c @@ -0,0 +1,171 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : remap driver + ******************************************************************************/ + +#include +#include +#include +#include +#include + + +typedef struct { + uint8_t number; + uint32_t address; +}REMAP_ADDRESS_TABLE; + +#define REMAP_TBL_MAX (sizeof(remap_tbl)/sizeof(remap_tbl[0])) + +static REMAP_ADDRESS_TABLE remap_tbl[] = { + [0] = {0xFF, 0x00000000U}, + [1] = {0xFF, 0x00000000U}, + [2] = {0xFF, 0x00000000U}, + [3] = {0xFF, 0x00000000U}, + [4] = {0xFF, 0x00000000U}, + [5] = {0xFF, 0x00000000U}, + [6] = {6, 0xE7200000U}, + [7] = {7, 0xE6400000U}, + [8] = {8, 0xFFC10000U}, + [9] = {9, 0xE6E00000U}, + [10] = {10, 0xFFC10000U}, + [11] = {11, 0xEE200000U}, + [12] = {12, 0xE6200000U}, + [13] = {13, 0xE6000000U}, + [14] = {14, 0xE6600000U}, + [15] = {15, 0xEB200000U}, +}; + +void remap_write_SICREMAP2M(uint32_t num, uint32_t value) +{ + /* Write-Protected Register Write Procedure */ + do { + mem_write32(ICUMX_PROT0PCMD, PROTCMD_START); + mem_write32(SICREMAP2M(num), value); + mem_write32(SICREMAP2M(num), ~value); + mem_write32(SICREMAP2M(num), value); + } while (mem_read32(ICUMX_PROT0PS) == PROTS0ERR); +} + +uint32_t remap_register(uint32_t addr, uint32_t size, uint32_t *remap_addr) +{ + uint32_t loop; + uint32_t loop2; + uint32_t map_num; + uint32_t set_addr; + + for (loop = 0; loop < REMAP_TBL_MAX; ++loop) { + if (0xFF == remap_tbl[loop].number) { + map_num = (addr & REMAP_2M_MASK) + size; + map_num = (map_num + REMAP_2M_MASK) + / (1 << REMAP_2M_BITS); + for (loop2 = 0; loop2 < map_num; ++loop2) { + if (0xFF != remap_tbl[loop].number) { + break; + } + } + if (map_num <= loop2) { + break; + } + } + } + + if (REMAP_TBL_MAX <= loop) { + return 2; + } + + __asm__ __volatile__ ("SYNCM"); + + set_addr = addr & ~REMAP_2M_MASK; + for (loop2 = loop; loop2 < (map_num + loop); ++loop2) { + remap_tbl[loop2].address = set_addr; + remap_tbl[loop2].number = loop; + remap_write_SICREMAP2M(loop2, set_addr); + set_addr += (1 << REMAP_2M_BITS); + } + + __asm__ __volatile__ ("SYNCM"); + + *remap_addr = ICU_REMAP_CALC(loop); + *remap_addr += addr & REMAP_2M_MASK; + return 0; +} + +uint32_t remap_unregister(uint32_t remap_addr) +{ + uint32_t loop; + uint32_t loop2; + uint32_t remove_num; + + for (loop = 0; loop < REMAP_TBL_MAX; ++loop) { + if ((0xFF != remap_tbl[loop].number) + && ((ICU_REMAP_CALC(loop) <= remap_addr) + && (remap_addr < ICU_REMAP_CALC(loop+1)))) { + break; + } + } + + if (REMAP_TBL_MAX <= loop) { + return 1; + } + __asm__ __volatile__ ("SYNCM"); + + remove_num = remap_tbl[loop].number; + for (loop2 = remove_num; loop2 < REMAP_TBL_MAX; ++loop2) { + if (remap_tbl[loop2].number != remove_num) { + break; + } + remap_tbl[loop2].address = 0; + remap_tbl[loop2].number = 0xFF; + remap_write_SICREMAP2M(loop2, ICU_REMAP_CALC(loop2)); + } + + __asm__ __volatile__ ("SYNCM"); + return 0; +} + +uint32_t remap_get_phys_addr(uint32_t remap_addr) +{ + uint32_t phys_addr; + uint32_t reg; + + if ((ICU_REMAP0 > remap_addr) + || (ICU_REMAP_CALC(REMAP_REG_MAX) <= remap_addr)) { + ERROR("remap address Error\n"); + panic(); + } + + phys_addr = remap_addr - ICU_REMAP0; + phys_addr >>= REMAP_2M_BITS; + reg = SICREMAP2M(phys_addr); + reg = mem_read32(reg); + phys_addr = reg + (remap_addr & REMAP_2M_MASK); + + return phys_addr; +} + +uint32_t remap_get_remap_addr(uint32_t phys_addr) +{ + uint32_t remap_addr; + uint32_t reg; + uint32_t loop; + + for (loop = 0; loop < REMAP_REG_MAX; loop++) { + reg = mem_read32(SICREMAP2M(loop)); + if ((reg <= phys_addr) + && (phys_addr <= (reg + REMAP_2M_MASK))) { + break; + } + } + + if (REMAP_REG_MAX <= loop) { + ERROR("remap address Error\n"); + panic(); + } + + remap_addr = ICU_REMAP_CALC(loop); + remap_addr += phys_addr - reg; + + return remap_addr; +} diff --git a/IPL/SDK/v3h/src/Dummy_FW/common/scif.c b/IPL/SDK/v3h/src/Dummy_FW/common/scif.c new file mode 100644 index 0000000..1a69642 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/common/scif.c @@ -0,0 +1,62 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : SCIF driver + ******************************************************************************/ + +#include +#include +#include +#include +#include +#include + +void scif_init(void) +{ + volatile uint16_t reg; + + mem_write16(SCIF_SCSMRIR, 0x0000U); /* SCIF channel0 as SCIF */ + + reg = mem_read16(SCIF_SCLSR); /* dummy read */ + mem_write16(SCIF_SCLSR, 0x0000U); /* clear ORER bit */ + mem_write16(SCIF_SCFSR, 0x0000U); /* clear all error bit */ + + mem_write16(SCIF_SCSCR, 0x0000U); /* clear SCR.TE & SCR.RE*/ + mem_write16(SCIF_SCFCR, 0x0006U); /* reset tx-fifo, reset rx-fifo. */ + + mem_write16(SCIF_SCSCR, 0x0000U); /* internal clock, SC_CLK pin unused for output pin */ + mem_write16(SCIF_SCSMR, 0x0000U); /* 8bit data, no-parity, 1 stop, Po/1 */ +// micro_wait(10U); /* 10us */ + mem_write16(SCIF_SCBRR, 0x11U); /* Pclk(66MHz)/1, 115.2kBps*/ + /* N = 66/(66/2*115200)*10^4-1 =17=> 0x11 */ +// micro_wait(10U); /* 10us */ + mem_write16(SCIF_SCFCR, 0x0000U); /* reset-off tx-fifo, rx-fifo. */ + mem_write16(SCIF_SCSCR, 0x0030U); /* enable TE, RE; SC_CLK=no output */ +// micro_wait(10U); /* 10us */ +} + +void console_puts(char *str,char rtn) +{ + while (*str) { + console_putc(*str); + str++; + } + + if(rtn == 1){ + console_putc(CR_CODE); + console_putc(LF_CODE); + } +} + +void console_putc(uint8_t outchar) +{ + uint16_t reg; + + while (!(0x60U & mem_read16(SCIF_SCFSR))) { + } + + mem_write8(SCIF_SCFTDR, outchar); + reg = mem_read16(SCIF_SCFSR); + reg &= ~0x60U; /* TEND,TDFE clear */ + mem_write16(SCIF_SCFSR, reg); +} diff --git a/IPL/SDK/v3h/src/Dummy_FW/fw/dummy_fw.S b/IPL/SDK/v3h/src/Dummy_FW/fw/dummy_fw.S new file mode 100644 index 0000000..474ebed --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/fw/dummy_fw.S @@ -0,0 +1,57 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Dummy FW start code + ******************************************************************************/ + + .global code_start + .global _dummy_fw_main + .global ___ghsend_RT_stack /* RT-SRAM stack Logical end address */ + + .section ".text" + .align 2 +code_start: + + mov r0, r1 + mov r0, r2 + mov r0, r3 + mov r0, r4 + mov r0, r5 + mov r0, r6 + mov r0, r7 + mov r0, r8 + mov r0, r9 + mov r0, r10 + mov r0, r11 + mov r0, r12 + mov r0, r13 + mov r0, r14 + mov r0, r15 + mov r0, r16 + mov r0, r17 + mov r0, r18 + mov r0, r19 + mov r0, r20 + mov r0, r21 + mov r0, r22 + mov r0, r23 + mov r0, r24 + mov r0, r25 + mov r0, r26 + mov r0, r27 + mov r0, r28 + mov r0, r29 + ldsr r0, 0, 0 + ldsr r0, 16, 0 + + mov ___ghsend_RT_stack, sp + + jarl _dummy_fw_main, lp + + jmp [r10] + nop + halt + + + + diff --git a/IPL/SDK/v3h/src/Dummy_FW/fw/dummy_fw.ld b/IPL/SDK/v3h/src/Dummy_FW/fw/dummy_fw.ld new file mode 100644 index 0000000..4a69563 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/fw/dummy_fw.ld @@ -0,0 +1,76 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Dummy FW linker directive + ******************************************************************************/ + +DEFAULTS { + remap_addr = 0xFDE00000 //remap15 address(target address = 0xEB200000) + remap_size = 1M //RT-SRAM size + rt_sram_addr = 0xEB200000 //RT-SRAM address +// fw_size = 110K //Dummy FW size + fw_size = 93K //Dummy FW size + fw_rom_size = 89K + fw_stack_size = 4K //Dummy FW stack size + + fw_addr = 0xFDEB4000 //Dummy FW start address + fw_stack_addr = fw_addr + fw_rom_size //Dummy FW stack address + + fw_phy_addr = 0xEB2B4000 //Dummy FW physical start address + fw_phy_stack_addr = fw_phy_addr + fw_rom_size //Dummy FW physical stack address + +} +MEMORY +{ + fw_start : ORIGIN = fw_addr, LENGTH = fw_rom_size //Dummy FW ROM(Start address) + stack : ORIGIN = fw_stack_addr, LENGTH = fw_stack_size//Dummy FW stack + fw_phys_start : ORIGIN = fw_phy_addr, LENGTH = fw_rom_size //Dummy FW(RT-SRAM) +} + +// +// Program layout for starting in ROM, copying data to RAM, +// and continuing to execute out of ROM. +// +SECTIONS +{ +// +// ROM SECTIONS(Remap) +// +// Place .text into fast_memory. Fail if it does not fit. + .reset ALIGN(4) : > fw_start + .EIINTTBL_ICU ALIGN(4) : > . + .version ALIGN(1024) :{*(.version)} > . + .text ALIGN(4) : > . + .data ALIGN(4) : > . + .rosdata ALIGN(4) : > . + .rodata ALIGN(4) : > . + .bss ALIGN(4) : > . + .sdata ALIGN(4) : > . + .tdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +// .note.renesas ALIGN(4) : > . +// .linfix ALIGN(4) : > . +// .gstackfix ALIGN(4) : > . + +// ROM mirror SECTIONS(RT-SRAM) + .ROM_NOCOPY.reset ROM_NOCOPY(.reset) ALIGN(4) : > fw_phys_start + .ROM_NOCOPY.EIINTTBL_ICU ROM_NOCOPY(.EIINTTBL_ICU) ALIGN(4) : > . + .ROM_NOCOPY.version ROM_NOCOPY(.version) ALIGN(1024) : > . + .ROM_NOCOPY.text ROM_NOCOPY(.text) ALIGN(4) : > . + .ROM_NOCOPY.data ROM_NOCOPY(.data) ALIGN(4) : > . + .ROM_NOCOPY.rosdata ROM_NOCOPY(.rosdata) ALIGN(4) : > . + .ROM_NOCOPY.rodata ROM_NOCOPY(.rodata) ALIGN(4) : > . + .ROM_NOCOPY.bss ROM_NOCOPY(.bss) ALIGN(4) : > . + .ROM_NOCOPY.sdata ROM_NOCOPY(.sdata) ALIGN(4) : > . + .ROM_NOCOPY.tdata ROM_NOCOPY(.tdata) ALIGN(4) : > . + .ROM_NOCOPY.sdabase ROM_NOCOPY(.sdabase) ALIGN(4) : > . + .ROM_NOCOPY.secinfo ROM_NOCOPY(.secinfo) ALIGN(4) : > . + + +// +// RAM SECTIONS +// + + .RT.stack ALIGN(4) PAD(fw_stack_size) ABS : > stack +} diff --git a/IPL/SDK/v3h/src/Dummy_FW/fw/dummy_fw_main.c b/IPL/SDK/v3h/src/Dummy_FW/fw/dummy_fw_main.c new file mode 100644 index 0000000..971730c --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/fw/dummy_fw_main.c @@ -0,0 +1,36 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : dummy fw main function + ******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Global */ +extern const char build_message[]; + +static void boot_message(void); + + +uint32_t dummy_fw_main(void) +{ + scif_init(); + boot_message(); + while(1); +} + +static void boot_message(void) +{ + /* boot message */ + console_puts("",1); + console_puts("Dummy FW Program",1); + console_puts("Dummy FW Program boot end",1); +} diff --git a/IPL/SDK/v3h/src/Dummy_FW/fw/vecttbl.S b/IPL/SDK/v3h/src/Dummy_FW/fw/vecttbl.S new file mode 100644 index 0000000..952e7ff --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/fw/vecttbl.S @@ -0,0 +1,98 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Dummy FW vector table + ******************************************************************************/ + + .global code_start + + .section ".reset" + .align 512 + .align 16 +_start: + jr32 code_start //RESET + .align 16 + jr32 _Dummy //SYSERR + .align 16 + jr32 _Dummy //HVTRAP + .align 16 + jr32 _Dummy //FETRAP + .align 16 + jr32 _Dummy //TRAP0 + .align 16 + jr32 _Dummy //TRAP1 + .align 16 + jr32 _Dummy //RIE + .align 16 + jr32 _Dummy //FPP/FPI + .align 16 + jr32 _Dummy //UCPOP + .align 16 + jr32 _Dummy //MIP/MDP + .align 16 + jr32 _Dummy //PIE + .align 16 + jr32 _Dummy //Debug + .align 16 + jr32 _Dummy //MAE + .align 16 + jr32 _Dummy //(R.F.U) + .align 16 + jr32 _Dummy //FENMI + .align 16 + jr32 _Dummy //FEINT + .align 16 + jr32 _Dummy //INTn(priority0) + .align 16 + jr32 _Dummy //INTn(priority1) + .align 16 + jr32 _Dummy //INTn(priority2) + .align 16 + jr32 _Dummy //INTn(priority3) + .align 16 + jr32 _Dummy //INTn(priority4) + .align 16 + jr32 _Dummy //INTn(priority5) + .align 16 + jr32 _Dummy //INTn(priority6) + .align 16 + jr32 _Dummy //INTn(priority7) + .align 16 + jr32 _Dummy //INTn(priority8) + .align 16 + jr32 _Dummy //INTn(priority9) + .align 16 + jr32 _Dummy //INTn(priority10) + .align 16 + jr32 _Dummy //INTn(priority11) + .align 16 + jr32 _Dummy //INTn(priority12) + .align 16 + jr32 _Dummy //INTn(priority13) + .align 16 + jr32 _Dummy //INTn(priority14) + .align 16 + jr32 _Dummy //INTn(priority15) + + .section ".EIINTTBL_ICU", const + .align 512 + .rept 7 + .word _Dummy_EI //INTn + .endr + .word _Dummy_EI //OSTM0 + .rept 20 + .word _Dummy_EI //INTn + .endr + .word _Dummy_EI //_Dummy + .word _Dummy_EI //_Dummy + .rept 98 + .word _Dummy_EI //INTn + .endr + + .section ".text" + .align 2 +_Dummy: + br _Dummy + +_Dummy_EI: + br _Dummy_EI diff --git a/IPL/SDK/v3h/src/Dummy_FW/include/dummy_fw_main.h b/IPL/SDK/v3h/src/Dummy_FW/include/dummy_fw_main.h new file mode 100644 index 0000000..c95421a --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/include/dummy_fw_main.h @@ -0,0 +1,16 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Dummy FW main header + ******************************************************************************/ + +#ifndef DUMMY_FW_MAIN_H_ +#define DUMMY_FW_MAIN_H_ + +/* define */ +#define VERSION "1.0.0" + +/* prototype */ +uint32_t dummy_fw_main(void); + +#endif /* DUMMY_FW_MAIN_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_FW/include/log.h b/IPL/SDK/v3h/src/Dummy_FW/include/log.h new file mode 100644 index 0000000..1af9fa4 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/include/log.h @@ -0,0 +1,64 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Log driver header + ******************************************************************************/ + +#ifndef LOG_H__ +#define LOG_H__ + +#include +#include + +#define LOG_NONE (0) +#define LOG_ERROR (1) +#define LOG_NOTICE (2) +#define LOG_WARNING (3) +#define LOG_INFO (4) +#define LOG_VERBOSE (5) + +#ifndef LOG_LEVEL + #define LOG_LEVEL (LOG_WARNING) +#endif + +#if LOG_LEVEL >= LOG_VERBOSE +# define VERBOSE(...) local_printf("V:" __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + +#if LOG_LEVEL >= LOG_INFO +# define INFO(...) local_printf("I:" __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_WARNING +# define WARN(...) local_printf("W:" __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_ERROR +# define ERROR(...) local_printf("E:" __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_NOTICE +# define NOTICE(...) local_printf("N:" __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#define panic(...) \ + do { \ + local_printf("P:%s[%d]\n", __func__, __LINE__); \ + while(1); \ + } while (0) + +#define FORCE(...) local_printf(__VA_ARGS__) + +void local_printf(const char *fmt, ...); + +#endif /* LOG_H__ */ diff --git a/IPL/SDK/v3h/src/Dummy_FW/include/mem_io.h b/IPL/SDK/v3h/src/Dummy_FW/include/mem_io.h new file mode 100644 index 0000000..b306d21 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/include/mem_io.h @@ -0,0 +1,29 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Memory access driver header + ******************************************************************************/ +#ifndef MEM_IO_H_ +#define MEM_IO_H_ + +#include + +/* Prototype */ +void mem_write8(uintptr_t addr, uint8_t data); +uint8_t mem_read8(uintptr_t addr); +void mem_write16(uintptr_t addr, uint16_t data); +uint16_t mem_read16(uintptr_t addr); +void mem_write32(uintptr_t addr, uint32_t data); +uint32_t mem_read32(uintptr_t addr); +void mem_write64(uintptr_t addr, uint64_t data); +uint64_t mem_read64(uintptr_t addr); +void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set); + +#if defined(__RH850G3K__) +#define mmio_write_32(a,b) mem_write32(a,b) +#define mmio_read_32(a) mem_read32(a) +#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c) +#endif + + +#endif /* MEM_IO_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_FW/include/micro_wait.h b/IPL/SDK/v3h/src/Dummy_FW/include/micro_wait.h new file mode 100644 index 0000000..c5b9acc --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/include/micro_wait.h @@ -0,0 +1,18 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Time wait driver header + ******************************************************************************/ + +#ifndef MICRO_WAIT_H_ +#define MICRO_WAIT_H_ + +#include + +/* Define */ + +/* Prototype */ +void micro_wait(uint32_t count_us); + + +#endif /* MICRO_WAIT_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_FW/include/rcar_def.h b/IPL/SDK/v3h/src/Dummy_FW/include/rcar_def.h new file mode 100644 index 0000000..1c404c5 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/include/rcar_def.h @@ -0,0 +1,31 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : R-Car common header + ******************************************************************************/ + +#ifndef RCAR_DEF_H_ +#define RCAR_DEF_H_ + +#include "remap_register.h" + +/* Product Register */ +#define PRR (BASE_PRR_ADDR) /* PRR register */ +#define PRR_PRODUCT_MASK (0x00007F00U) /* Product mask */ +#define PRR_CUT_MASK (0x000000FFU) /* Cut Number bit mask */ +#define PRR_MAJOR_MASK (0x000000F0U) /* Major bit mask */ +#define PRR_MINOR_MASK (0x0000000FU) /* Minor bit mask */ +#define PRR_PRODUCT_SHIFT (8U) /* PRR bit shift */ +#define PRR_MAJOR_SHIFT (4U) /* Major bit shift */ +#define PRR_MINOR_SHIFT (0U) /* Minor bit shift */ +#define PRR_MAJOR_OFFSET (1U) + +#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */ +#define PRR_PRODUCT_10 (0x00U) + +#define RCAR_PRR (PRR) /* PRR register */ +#define RCAR_PRODUCT_MASK (PRR_PRODUCT_MASK) /* Product mask */ +#define RCAR_PRODUCT_V3H (PRR_PRODUCT_V3H) /* R-Car V3H */ + +#endif /* RCAR_DEF_H_ */ + diff --git a/IPL/SDK/v3h/src/Dummy_FW/include/remap.h b/IPL/SDK/v3h/src/Dummy_FW/include/remap.h new file mode 100644 index 0000000..38df3fb --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/include/remap.h @@ -0,0 +1,20 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : remap driver header + ******************************************************************************/ +#ifndef REMAP_H_ +#define REMAP_H_ + +#define REMAP_SIZE_MIN (2*1024*1024) +#define REMAP_ALIGN_MASK (~((1 << 21) - 1)) + +void remap_write_SICREMAP2M(uint32_t num, uint32_t value); + +uint32_t remap_get_phys_addr(uint32_t remap_addr); +uint32_t remap_get_remap_addr(uint32_t phys_addr); + +uint32_t remap_register(uint32_t addr, uint32_t size, uint32_t *remap_addr); +uint32_t remap_unregister(uint32_t remap_addr); + +#endif /* REMAP_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_FW/include/remap_register.h b/IPL/SDK/v3h/src/Dummy_FW/include/remap_register.h new file mode 100644 index 0000000..b8c87cb --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/include/remap_register.h @@ -0,0 +1,193 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : remap register header + ******************************************************************************/ + +#ifndef REMAP_REGISTER_H_ +#define REMAP_REGISTER_H_ + + +#define REMAP_BASE (0xFF1FC400U) + +#define REMAP_2M_BITS (21U) +#define REMAP_2M_MASK ((1 << REMAP_2M_BITS) - 1U) + +#define REMAP_REG_MAX (16U) +#define SICREMAP2M(a) (REMAP_BASE + ((a) * (0x4U))) + +#define ICUMX_PROT0PCMD (0xFFFEE090U) +#define ICUMX_PROT0PS (0xFFFEE094U) +#define PROTCMD_START (0x000000A5U) +#define PROTS0ERR (0x00000001U) + +/* REMAP setting */ +/* Remap ID(0 -- 15) */ +#define ICU_REMAP_NUM_RTRAM (15U) /* RTRAM */ +#define ICU_REMAP_NUM_CC (14U) /* CC63S */ +#define ICU_REMAP_NUM_PFC (13U) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */ +#define ICU_REMAP_NUM_MFIS (12U) /* MFIS */ +#define ICU_REMAP_NUM_RPC (11U) /* RPC */ +#define ICU_REMAP_NUM_RTDMAC (10U) /* RT-DMAC0 */ +#define ICU_REMAP_NUM_SCIF (9U) /* SCIF */ +#define ICU_REMAP_NUM_MMC (8U) /* MMC */ +#define ICU_REMAP_NUM_HSCIF (7U) /* HSCIF */ +#define ICU_REMAP_NUM_DMAC (6U) /* SYS-DMAC0 */ +#define ICU_REMAP_NUM_PRR (5U) /* PRR */ +#define ICU_REMAP_NUM_RTACT (4U) /* RT-ACT */ + +/* SICREMAP2M15 */ +#define ICU_REMAP_RTRAM (0xEB200000U) /* RTRAM */ +/* SICREMAP2M14 */ +#define ICU_REMAP_CC (0xE6600000U) /* CC63S,System DMA */ +/* SICREMAP2M13 */ +#define ICU_REMAP_PFC (0xE6000000U) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */ +/* SICREMAP2M12 */ +#define ICU_REMAP_MFIS (0xE6200000U) /* MFIS */ +/* SICREMAP2M11 */ +#define ICU_REMAP_RPC (0xEE200000U) /* RPC */ +/* SICREMAP2M10 */ +#define ICU_REMAP_SCIF (0xE6E00000U) /* SCIF */ +/* SICREMAP2M9 */ +#define ICU_REMAP_MMC (0xEE000000U) /* MMC */ +/* SICREMAP2M8 */ +#define ICU_REMAP_RTDMAC (0xFFC00000U) /* RT-DMAC0 */ +/* SICREMAP2M7 */ +#define ICU_REMAP_HSCIF (0xE6400000U) /* HSCIF */ +/* SICREMAP2M6 */ +#define ICU_REMAP_DMAC (0xE7200000U) /* SYS-DMAC0 */ +/* SICREMAP2M5 */ +#define ICU_REMAP_PRR (0xFFE00000U) /* PRR */ +/* SICREMAP2M4 */ +#define ICU_REMAP_RTACT (0xFFC00000U) /* RT-ACT */ + +#define ICU_REMAP15_BASE (ICU_REMAP_RTRAM) /* RTRAM */ +#define ICU_REMAP14_BASE (ICU_REMAP_CC) /* CC63S */ +#define ICU_REMAP13_BASE (ICU_REMAP_PFC) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */ +#define ICU_REMAP12_BASE (ICU_REMAP_MFIS) /* MFIS */ +#define ICU_REMAP11_BASE (ICU_REMAP_RPC) /* RPC */ +#define ICU_REMAP10_BASE (ICU_REMAP_RTDMAC) /* RT-DMAC0 */ +#define ICU_REMAP9_BASE (ICU_REMAP_SCIF) /* SCIF */ +#define ICU_REMAP8_BASE (ICU_REMAP_MMC) /* MMC */ +#define ICU_REMAP7_BASE (ICU_REMAP_HSCIF) /* HSCIF */ +#define ICU_REMAP6_BASE (ICU_REMAP_DMAC) /* SYS-DMAC0 */ +#define ICU_REMAP5_BASE (ICU_REMAP_PRR) /* PRR,INTC,RT-SRAM protection*/ +#define ICU_REMAP4_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP3_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP2_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP1_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP0_BASE (0x00000000U) /* Reserved */ + +/* Base address offset of each register after remap */ +/* REMAP15(0xEB200000U) */ +/* RT-SRAM */ +#define ICU_REMAP_OFFSET_RTRAM (0x000000U) + +/* REMAP14(0xE6600000U) */ +#define ICU_REMAP_OFFSET_CC63S (0x000000U) +#define ICU_REMAP_OFFSET_AXI (0x184000U) /* (0xE6784000U) */ +#define ICU_REMAP_OFFSET_DBSC (0x190000U) /* (0xE6790000U) */ +#define ICU_REMAP_OFFSET_MSTAT (0x1e0000U) /* (0xE67e0000U) */ +#define ICU_REMAP_OFFSET_QOS (0x1F0000U) /* (0xE67F0000U) */ + +/* REMAP13(0xE6000000U) */ +/* GPIO */ +#define ICU_REMAP_OFFSET_GPIO0 (0x050000U) +#define ICU_REMAP_OFFSET_GPIO1 (0x051000U) +#define ICU_REMAP_OFFSET_GPIO2 (0x052000U) +#define ICU_REMAP_OFFSET_GPIO3 (0x053000U) +#define ICU_REMAP_OFFSET_GPIO4 (0x054000U) +#define ICU_REMAP_OFFSET_GPIO5 (0x055000U) +/* PFC */ +#define ICU_REMAP_OFFSET_PFC (0x060000U) +/* LIFEC */ +#define ICU_REMAP_OFFSET_LIFEC (0x110000U) +/* CPGA */ +#define ICU_REMAP_OFFSET_CPGA (0x150000U) +/* RESET */ +#define ICU_REMAP_OFFSET_RESET (0x160000U) +/* SYSC */ +#define ICU_REMAP_OFFSET_SYSC (0x180000U) +/* THS1 */ +#define ICU_REMAP_OFFSET_THS1 (0x198000U) /* (0xE6198000U) */ + +/* REMAP12(0xE6200000U) */ +/* MFIS */ +#define ICU_REMAP_OFFSET_MFIS (0x060000U) + +/* REMAP11(0xEE200000U) */ +/*RPC*/ +#define ICU_REMAP_OFFSET_RPC (0x000000U) + +/* REMAP10(0xFFC00000U) */ +/* RT-DMA */ +#define ICU_REMAP_OFFSET_RTDMA (0x010000U) + +/* REMAP9(0xE6E00000U) */ +/*SCIF*/ +#define ICU_REMAP_OFFSET_SCIF0 (0x060000U) + +/* REMAP8(0xEE000000U) */ +/* SDHI2/MMC0 */ +#define ICU_REMAP_OFFSET_SDHI (0x140000U) + +/* REMAP7(0xE6400000U) */ +/* HSCIF */ +#define ICU_REMAP_OFFSET_HSCIF0 (0x140000U) + +/* REMAP6(0xE7200000U) */ +/* SYS-DMAC */ +#define ICU_REMAP_OFFSET_SYSDMAC (0x100000U) + +/* REMAP5(0xFFE00000U) */ +/* PRR */ +#define ICU_REMAP_OFFSET_PRR (0x100044U) + +/* REMAP4(0xFFE00000U) */ +/* RT-ACT */ +#define ICU_REMAP_OFFSET_RTACT (0x050800U) + +/* Calculate the base address of each register after remapping */ +#define ICU_REMAP0 (0xFC000000U) +#define ICU_REMAP_CALC( val ) (ICU_REMAP0 + (val * 0x200000U)) + +/* REMAP15(0xEB200000U) */ +#define BASE_RTRAM_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTRAM) + ICU_REMAP_OFFSET_RTRAM) +/* REMAP14(0xE6600000U) */ +#define BASE_AXI_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_AXI) +#define BASE_DBSC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_DBSC) +#define BASE_MSTAT_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_MSTAT) +#define BASE_QOS_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_QOS) +/* REMAP13(0xE6000000U) */ +#define BASE_GPIO_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_GPIO0) +#define BASE_PFC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_PFC) +#define BASE_LIFEC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_LIFEC) +#define BASE_CPG_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_CPGA) +#define BASE_RESET_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_RESET) +#define BASE_SYSC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_SYSC) +#define BASE_THS1_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_THS1) +/* REMAP12(0xE6200000U) */ +#define BASE_MFIS_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_MFIS) + ICU_REMAP_OFFSET_MFIS) +/* REMAP11(0xEE200000U) */ +#define BASE_RPC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RPC) + ICU_REMAP_OFFSET_RPC) +/* REMAP10(0xFFC00000U) */ +#define BASE_RTDMA_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMA) +/* REMAP9(0xE6E00000U) */ +#define BASE_SCIF_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF0) +/* REMAP8(0xEE000000U) */ +#define BASE_MMC0_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_MMC) + ICU_REMAP_OFFSET_SDHI) +/* REMAP7(0xE6400000U) */ +#define BASE_HSCIF_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_HSCIF) + ICU_REMAP_OFFSET_HSCIF0) +/* REMAP6(0xE7200000U) */ +#define BASE_DMA_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_DMAC) + ICU_REMAP_OFFSET_SYSDMAC) +/* REMAP5(0xFFE00000U) */ +#define BASE_PRR_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PRR) + ICU_REMAP_OFFSET_PRR) +/* REMAP4(0xFFE00000U) */ +#define BASE_RTACT_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTACT) + ICU_REMAP_OFFSET_RTACT) + +/* MFIS */ +#define MFIS_MFISSOFTMDR (BASE_MFIS_ADDR + 0x0600U) /* SOFTMD register */ +#define MFIS_MFISBTSTSR (BASE_MFIS_ADDR + 0x0604U) /* (0xE6260604U) */ +#define MFIS_MFISWACNTR (BASE_MFIS_ADDR + 0x0904U) /* (0xE6260904U) */ /* Write Access Control Register */ + +#endif /* REMAP_REGISTER_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_FW/include/rst_register.h b/IPL/SDK/v3h/src/Dummy_FW/include/rst_register.h new file mode 100644 index 0000000..d2f9e0d --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/include/rst_register.h @@ -0,0 +1,49 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : RST register header + ******************************************************************************/ + +#ifndef RST_REGISTER_H_ +#define RST_REGISTER_H_ + +#include + +#define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */ +#define RST_WDTRSTCR (RST_BASE + 0x0054U) +#define RST_CR7BAR (RST_BASE + 0x0070U) +#define RST_CR7BAR_BAREN ((uint32_t)1U << 4) +#define WDTRSTCR_PASSWORD (0xA55A0000U) +#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U) + +#define RST_ICUMXBAR (RST_BASE + 0x0078U) +#define RST_ICUMXBAR_BAREN ((uint32_t)1U << 4) + + +#define RST_MODEMR (RST_BASE + 0x0060U) /* Mode pin register */ +#define RST_MODEMR_A (RST_BASE + 0x0060U) /* Mode pin register for Assembly language */ +#define RST_MODEMR2 (RST_BASE + 0x0068U) /* Mode Monitor Register2 */ +#define RST_CA57RESCNT (RST_BASE + 0x0040U) /* Reset control register for A57 */ +#define RST_CA53RESCNT (RST_BASE + 0x0044U) /* Reset control register for A53 */ + +#define RST_CA57CPU0BARL (RST_BASE + 0x00C4U) +#define RST_CA57CPU0BARH (RST_BASE + 0x00C0U) +#define RST_CA53CPU0BARL (RST_BASE + 0x0084U) +#define RST_CA53CPU0BARH (RST_BASE + 0x0080U) + +#define MODEMR_BOOT_CPU_MASK (0x000000C0U) +#define MODEMR_BOOT_CPU_CR7 (0x000000C0U) +#define MODEMR_BOOT_CPU_CA57 (0x00000000U) +#define MODEMR_BOOT_CPU_CA53 (0x00000040U) +#define MODEMR_BOOT_DEV_MASK (0x0000001EU) +#define MODEMR_BOOT_DEV_HYPERFLASH160 (0x00000004U) +#define MODEMR_BOOT_DEV_HYPERFLASH80 (0x00000006U) +#define MODEMR_BOOT_DEV_QSPI_FLASH40 (0x00000008U) +#define MODEMR_BOOT_DEV_QSPI_FLASH80 (0x0000000CU) +#define MODEMR_BOOT_DEV_OCTAL_FLASH (0x0000000EU) +#define MODEMR_BOOT_DEV_EMMC_25X1 (0x0000000AU) +#define MODEMR_BOOT_DEV_EMMC_50X8 (0x0000001AU) +#define MODEMR_BOOT_DEV_SCIF_DOWNLOAD (0x0000001EU) +#define MODEMR_BOOT_DEV_USB_DOWNLOAD (0x0000001CU) + +#endif /* RST_REGISTER_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_FW/include/scif.h b/IPL/SDK/v3h/src/Dummy_FW/include/scif.h new file mode 100644 index 0000000..5a94ed4 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/include/scif.h @@ -0,0 +1,25 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : SCIF driver header + ******************************************************************************/ + +#ifndef SCIF_H_ +#define SCIF_H_ + +/* Define */ +#define PFC_GPSR_SCIF_MASK (0x00000030UL) /* SCIF0/HSCIF0_B RX/TX */ +#define PFC_GPSR_SCIF_VAL (0x00000030UL) /* SCIF0/HSCIF0_B RX/TX */ +#define PFC_IPSR_SCIF_MASK (0x0FF00000UL) /* SCIF0 RX/TX */ +#define PFC_IPSR_SCIF_VAL (0x04400000UL) /* SCIF0 RX/TX */ +#define BIT7 (uint32_t)(1U << 7U) /* Module Stop 2 bit7(SCIF0) */ + +#define CR_CODE (0x0DU) +#define LF_CODE (0x0AU) + +/* Prototype */ +void scif_init(void); +void console_puts(char* str,char rtn); +void console_putc(uint8_t outchar); + +#endif /* SCIF_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_FW/include/scif_register.h b/IPL/SDK/v3h/src/Dummy_FW/include/scif_register.h new file mode 100644 index 0000000..16c3d93 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_FW/include/scif_register.h @@ -0,0 +1,58 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : SCIF register header + ******************************************************************************/ + + +#ifndef SCIF_REGISTER_H_ +#define SCIF_REGISTER_H_ + +#include + +/* SCIF0 base address */ +/* 0xE6E60000 */ +#define SCIF0_BASE (BASE_SCIF_ADDR) + +#define SCIF_SCSMR (SCIF0_BASE + 0x00U) /* 16 Serial mode register */ +#define SCIF_SCBRR (SCIF0_BASE + 0x04U) /* 8 Bit rate register */ +#define SCIF_SCSCR (SCIF0_BASE + 0x08U) /* 16 Serial control register */ +#define SCIF_SCFTDR (SCIF0_BASE + 0x0CU) /* 8 Transmit FIFO data register */ +#define SCIF_SCFSR (SCIF0_BASE + 0x10U) /* 16 Serial status register */ +#define SCIF_SCFRDR (SCIF0_BASE + 0x14U) /* 8 Receive FIFO data register */ +#define SCIF_SCFCR (SCIF0_BASE + 0x18U) /* 16 FIFO control register */ +#define SCIF_SCFDR (SCIF0_BASE + 0x1CU) /* 16 FIFO data count register */ +#define SCIF_SCSPTR (SCIF0_BASE + 0x20U) /* 16 Serial port register */ +#define SCIF_SCLSR (SCIF0_BASE + 0x24U) /* 16 Line status register */ +#define SCIF_DL (SCIF0_BASE + 0x30U) /* 16 Frequency division register */ +#define SCIF_CKS (SCIF0_BASE + 0x34U) /* 16 Clock Select register */ +#define SCIF_SCFER (SCIF0_BASE + 0x44U) /* 16 FIFO error count register */ +#define SCIF_SCSMRIR (SCIF0_BASE + 0x40U) /* 16 Serial mode register */ + + +/*HSCIF0 base address*/ +/* 0xE6540000 */ +#define HSCIF_BASE (BASE_HSCIF_ADDR) + +#define HSCIF_HSSMR (HSCIF_BASE + 0x00U) /* 16 Serial mode register */ +#define HSCIF_HSBRR (HSCIF_BASE + 0x04U) /* 8 Bit rate register */ +#define HSCIF_HSSCR (HSCIF_BASE + 0x08U) /* 16 Serial control register */ +#define HSCIF_HSFTDR (HSCIF_BASE + 0x0CU) /* 8 Transmit FIFO data register */ +#define HSCIF_HSFSR (HSCIF_BASE + 0x10U) /* 16 Serial status register */ +#define HSCIF_HSFRDR (HSCIF_BASE + 0x14U) /* 8 Receive FIFO data register */ +#define HSCIF_HSFCR (HSCIF_BASE + 0x18U) /* 16 FIFO control register */ +#define HSCIF_HSFDR (HSCIF_BASE + 0x1CU) /* 16 FIFO data count register */ +#define HSCIF_HSSPTR (HSCIF_BASE + 0x20U) /* 16 Serial port register */ +#define HSCIF_HSLSR (HSCIF_BASE + 0x24U) /* 16 Line status register */ + +#define HSCIF_HSSRR (HSCIF_BASE + 0x40U) /* 16 Sampling rate register */ +#define HSCIF_HSRER (HSCIF_BASE + 0x44U) /* 16 Serial error register */ +#define HSCIF_HSRTGR (HSCIF_BASE + 0x50U) /* 16 RTS output active trigger register */ +#define HSCIF_HSRTRGR (HSCIF_BASE + 0x54U) /* 16 Receive FIFO data count trigger register */ +#define HSCIF_HSTTRGR (HSCIF_BASE + 0x58U) /* 16 Transmit FIFO data count trigger register */ + +#define HSCIF_DL (HSCIF_BASE + 0x30U) /* 16 Frequency division register */ +#define HSCIF_CKS (HSCIF_BASE + 0x34U) /* 16 Clock Select register */ + + +#endif /* SCIF_REGISTER_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/Makefile b/IPL/SDK/v3h/src/Dummy_RTOS/Makefile new file mode 100644 index 0000000..58d1a0a --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/Makefile @@ -0,0 +1,112 @@ +# +# Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. +# + +################################################### +# makefile +################################################### + +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +INCLUDE_DIR = -Iinclude + +#output file name +FILE_NAME = dummy_rtos + +OUTPUT_FILE = $(FILE_NAME).elf + +OUTPUT_DIR = output +OBJECT_DIR = obj + +#object file name +OBJ_FILE = common/scif.o \ + common/div.o \ + rtos/rtos.o \ + rtos/rtos_main.o + +#linker script name +MEMORY_DEF = rtos/rtos.ld.S + +################################################### +# Process LOG_LEVEL flag +ifndef LOG_LEVEL +LOG_LEVEL := 20 +endif +$(eval $(call add_define,LOG_LEVEL)) + +################################################### + +CC = $(CROSS_COMPILE)gcc +CPP = ${CROSS_COMPILE}cpp +AS = ${CROSS_COMPILE}gcc +AR = ${CROSS_COMPILE}ar +LD = $(CROSS_COMPILE)ld +OC = ${CROSS_COMPILE}objcopy +OD = ${CROSS_COMPILE}objdump + +ASFLAGS = -marm -march=armv7-r \ + -nostdinc -ffreestanding -Wa,--fatal-warnings \ + -Werror -Wmissing-include-dirs \ + -c -D__ASSEMBLY \ + $(INCLUDE_DIR) $(DEFINES) + +CFLAGS = -marm -march=armv7-r \ + -nostdinc -ffreestanding -Wall \ + -Werror -Wmissing-include-dirs \ + -std=c99 -c -Os \ + -ffunction-sections -fdata-sections \ + $(INCLUDE_DIR) $(DEFINES) + +CFLAGS += -g +ASFLAGS += -g -Wa,--gdwarf-2 + +LDFLAGS = --fatal-warnings -O1 --gc-sections + +################################################### +.SUFFIXES : .s .c .o + +################################################### +# command + +.PHONY: all +all: $(OBJECT_DIR) $(OUTPUT_DIR) $(OUTPUT_FILE) +################################################### +# Make Directory +################################################### +$(OBJECT_DIR): + mkdir -p $(OBJECT_DIR) + +$(OUTPUT_DIR): + mkdir -p $(OUTPUT_DIR) + +################################################### +# Linker +################################################### +$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE) + $(LD) $(OBJ_FILE) \ + -T $(MEMORY_DEF) \ + -o $(OUTPUT_FILE) \ + $(LDFLAGS) \ + -Map $(FILE_NAME).map + + $(OC) -O srec --srec-forceS3 $(OUTPUT_FILE) $(FILE_NAME).srec + $(OC) -O binary $(OUTPUT_FILE) $(FILE_NAME).bin + $(OD) -dx $(OUTPUT_FILE) > $(FILE_NAME).dump + + +################################################### +# Compile +################################################### + +%.o:../%.c + $(CC) $(CFLAGS) -o $@ $< + +%.o:../%.s + $(AS) $(ASFLAGS) -o $@ $< + + +.PHONY: clean +clean: + $(RM) $(OBJ_FILE) $(OUTPUT_FILE) $(FILE_NAME).* diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/common/div.s b/IPL/SDK/v3h/src/Dummy_RTOS/common/div.s new file mode 100644 index 0000000..a209b14 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/common/div.s @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + + .global __aeabi_uidivmod + +/***************************************************************************** + * input: + * r0: divided + * r1: divisor + * + * output + * r0: quot + * r1: rem + *****************************************************************************/ + +__aeabi_uidivmod: + push {r4, r5} + mov r4, #0 + mov r5, #1 + + clz r2, r1 + mov r3, r1, LSL r2 +1: + cmp r3, r0 + subls r0, r0, r3 + addls r4, r5, LSL r2 + + lsr r3, r3, #1 + subs r2, r2, #1 + bpl 1b + + mov r1, r0 + mov r0, r4 + + pop {r4, r5} + bx lr + + .end diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/common/scif.c b/IPL/SDK/v3h/src/Dummy_RTOS/common/scif.c new file mode 100644 index 0000000..0e61d86 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/common/scif.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#include +#include + + +/************************************************************************/ +/*NAME : PutStr */ +/************************************************************************/ +void PutStr(const char *str,char rtn) +{ + while(*str){ + PutChar(*str); + str++; + } + if(rtn == 1){ + PutChar(CR_CODE); + PutChar(LF_CODE); + } +} + +void PutChar(char outChar) +{ + while(!(0x60 & *((volatile uint16_t*)SCIF0_SCFSR) )); + *((volatile uint8_t*)SCIF0_SCFTDR) = outChar; + *((volatile uint16_t*)SCIF0_SCFSR) &= ~0x60; /* TEND,TDFE clear */ +} diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/debug.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/debug.h new file mode 100644 index 0000000..44c5d8e --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/debug.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +#include + +/* The log output macros print output to the console. These macros produce + * compiled log output only if the LOG_LEVEL defined in the makefile (or the + * make command line) is greater or equal than the level required for that + * type of log output. + * The format expected is the same as for printf(). For example: + * INFO("Info %s.\n", "message") -> INFO: Info message. + * WARN("Warning %s.\n", "message") -> WARNING: Warning message. + */ + +#define LOG_LEVEL_NONE 0 +#define LOG_LEVEL_ERROR 10 +#define LOG_LEVEL_NOTICE 20 +#define LOG_LEVEL_WARNING 30 +#define LOG_LEVEL_INFO 40 +#define LOG_LEVEL_VERBOSE 50 + + +#if LOG_LEVEL >= LOG_LEVEL_NOTICE +# define NOTICE(...) tf_printf("NOTICE: " __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_ERROR +# define ERROR(...) tf_printf("ERROR: " __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_WARNING +# define WARN(...) tf_printf("WARNING: " __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_INFO +# define INFO(...) tf_printf("INFO: " __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE +# define VERBOSE(...) tf_printf("VERBOSE: " __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + + +void __dead2 do_panic(void); +#define panic() do_panic() + +void tf_printf(const char *fmt, ...) __printflike(1, 2); + +#endif /* __DEBUG_H__ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/machine/_stdint.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/machine/_stdint.h new file mode 100644 index 0000000..e36c659 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/machine/_stdint.h @@ -0,0 +1,164 @@ +/*- + * Copyright (c) 2001, 2002 Mike Barcroft + * Copyright (c) 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Klaus Klein. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE__STDINT_H_ +#define _MACHINE__STDINT_H_ + +#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) + +#define INT8_C(c) (c) +#define INT16_C(c) (c) +#define INT32_C(c) (c) +#define INT64_C(c) (c ## L) + +#define UINT8_C(c) (c) +#define UINT16_C(c) (c) +#define UINT32_C(c) (c ## U) +#define UINT64_C(c) (c ## UL) + +#define INTMAX_C(c) INT64_C(c) +#define UINTMAX_C(c) UINT64_C(c) + +#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */ + +#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) + +/* + * ISO/IEC 9899:1999 + * 7.18.2.1 Limits of exact-width integer types + */ +/* Minimum values of exact-width signed integer types. */ +#define INT8_MIN (-0x7f-1) +#define INT16_MIN (-0x7fff-1) +#define INT32_MIN (-0x7fffffff-1) +#define INT64_MIN (-0x7fffffffffffffffL-1) + +/* Maximum values of exact-width signed integer types. */ +#define INT8_MAX 0x7f +#define INT16_MAX 0x7fff +#define INT32_MAX 0x7fffffff +#define INT64_MAX 0x7fffffffffffffffL + +/* Maximum values of exact-width unsigned integer types. */ +#define UINT8_MAX 0xff +#define UINT16_MAX 0xffff +#define UINT32_MAX 0xffffffffU +#define UINT64_MAX 0xffffffffffffffffUL + +/* + * ISO/IEC 9899:1999 + * 7.18.2.2 Limits of minimum-width integer types + */ +/* Minimum values of minimum-width signed integer types. */ +#define INT_LEAST8_MIN INT8_MIN +#define INT_LEAST16_MIN INT16_MIN +#define INT_LEAST32_MIN INT32_MIN +#define INT_LEAST64_MIN INT64_MIN + +/* Maximum values of minimum-width signed integer types. */ +#define INT_LEAST8_MAX INT8_MAX +#define INT_LEAST16_MAX INT16_MAX +#define INT_LEAST32_MAX INT32_MAX +#define INT_LEAST64_MAX INT64_MAX + +/* Maximum values of minimum-width unsigned integer types. */ +#define UINT_LEAST8_MAX UINT8_MAX +#define UINT_LEAST16_MAX UINT16_MAX +#define UINT_LEAST32_MAX UINT32_MAX +#define UINT_LEAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.3 Limits of fastest minimum-width integer types + */ +/* Minimum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MIN INT32_MIN +#define INT_FAST16_MIN INT32_MIN +#define INT_FAST32_MIN INT32_MIN +#define INT_FAST64_MIN INT64_MIN + +/* Maximum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MAX INT32_MAX +#define INT_FAST16_MAX INT32_MAX +#define INT_FAST32_MAX INT32_MAX +#define INT_FAST64_MAX INT64_MAX + +/* Maximum values of fastest minimum-width unsigned integer types. */ +#define UINT_FAST8_MAX UINT32_MAX +#define UINT_FAST16_MAX UINT32_MAX +#define UINT_FAST32_MAX UINT32_MAX +#define UINT_FAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.4 Limits of integer types capable of holding object pointers + */ +#define INTPTR_MIN INT64_MIN +#define INTPTR_MAX INT64_MAX +#define UINTPTR_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.5 Limits of greatest-width integer types + */ +#define INTMAX_MIN INT64_MIN +#define INTMAX_MAX INT64_MAX +#define UINTMAX_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.3 Limits of other integer types + */ +/* Limits of ptrdiff_t. */ +#define PTRDIFF_MIN INT64_MIN +#define PTRDIFF_MAX INT64_MAX + +/* Limits of sig_atomic_t. */ +#define SIG_ATOMIC_MIN INT32_MIN +#define SIG_ATOMIC_MAX INT32_MAX + +/* Limit of size_t. */ +#define SIZE_MAX UINT64_MAX + +#ifndef WCHAR_MIN /* Also possibly defined in */ +/* Limits of wchar_t. */ +#define WCHAR_MIN INT32_MIN +#define WCHAR_MAX INT32_MAX +#endif + +/* Limits of wint_t. */ +#define WINT_MIN INT32_MIN +#define WINT_MAX INT32_MAX + +#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ + +#endif /* !_MACHINE__STDINT_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/machine/_types.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/machine/_types.h new file mode 100644 index 0000000..0f1e14e --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/machine/_types.h @@ -0,0 +1,110 @@ +/*- + * Copyright (c) 2002 Mike Barcroft + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * From: @(#)ansi.h 8.2 (Berkeley) 1/4/94 + * From: @(#)types.h 8.3 (Berkeley) 1/5/94 + * $FreeBSD$ + */ + +#ifndef _MACHINE__TYPES_H_ +#define _MACHINE__TYPES_H_ + +#ifndef _SYS_CDEFS_H_ +#error this file needs sys/cdefs.h as a prerequisite +#endif + +/* + * Basic types upon which most other types are built. + */ +typedef __signed char __int8_t; +typedef unsigned char __uint8_t; +typedef short __int16_t; +typedef unsigned short __uint16_t; +typedef int __int32_t; +typedef unsigned int __uint32_t; +typedef long long __int64_t; +typedef unsigned long long __uint64_t; + +/* + * Standard type definitions. + */ +typedef __int32_t __clock_t; /* clock()... */ +typedef __int32_t __critical_t; +typedef double __double_t; +typedef float __float_t; +typedef __int32_t __intfptr_t; +typedef __int32_t __intmax_t; +typedef __int32_t __intptr_t; +typedef __int32_t __int_fast8_t; +typedef __int32_t __int_fast16_t; +typedef __int32_t __int_fast32_t; +typedef __int32_t __int_fast64_t; +typedef __int8_t __int_least8_t; +typedef __int16_t __int_least16_t; +typedef __int32_t __int_least32_t; +typedef __int64_t __int_least64_t; +typedef __int32_t __ptrdiff_t; /* ptr1 - ptr2 */ +typedef __int32_t __register_t; +typedef __int32_t __segsz_t; /* segment size (in pages) */ +typedef __uint32_t __size_t; /* sizeof() */ +typedef __int32_t __ssize_t; /* byte count or error */ +typedef __int32_t __time_t; /* time()... */ +typedef __uint32_t __uintfptr_t; +typedef __uint64_t __uintmax_t; +typedef __uint32_t __uintptr_t; +typedef __uint32_t __uint_fast8_t; +typedef __uint32_t __uint_fast16_t; +typedef __uint32_t __uint_fast32_t; +typedef __uint64_t __uint_fast64_t; +typedef __uint8_t __uint_least8_t; +typedef __uint16_t __uint_least16_t; +typedef __uint32_t __uint_least32_t; +typedef __uint64_t __uint_least64_t; +typedef __uint32_t __u_register_t; +typedef __uint32_t __vm_offset_t; +typedef __int32_t __vm_ooffset_t; +typedef __uint32_t __vm_paddr_t; +typedef __uint32_t __vm_pindex_t; +typedef __uint32_t __vm_size_t; + +/* + * Unusual type definitions. + */ +#ifdef __GNUCLIKE_BUILTIN_VARARGS +typedef __builtin_va_list __va_list; /* internally known to gcc */ +#else +typedef char * __va_list; +#endif /* __GNUCLIKE_BUILTIN_VARARGS */ +#if defined(__GNUCLIKE_BUILTIN_VAALIST) && !defined(__GNUC_VA_LIST) \ + && !defined(__NO_GNUC_VA_LIST) +#define __GNUC_VA_LIST +typedef __va_list __gnuc_va_list; /* compatibility w/GNU headers*/ +#endif + +#endif /* !_MACHINE__TYPES_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/mmio.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/mmio.h new file mode 100644 index 0000000..842f760 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/mmio.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef __MMIO_H__ +#define __MMIO_H__ + +#include + +static inline void mmio_write_8(uintptr_t addr, uint8_t value) +{ + *(volatile uint8_t* )addr = value; +} + +static inline uint8_t mmio_read_8(uintptr_t addr) +{ + return *(volatile uint8_t *)addr; +} + +static inline void mmio_write_16(uintptr_t addr, uint16_t value) +{ + *(volatile uint16_t *)addr = value; +} + +static inline uint16_t mmio_read_16(uintptr_t addr) +{ + return *(volatile uint16_t *)addr; +} + +static inline void mmio_write_32(uintptr_t addr, uint32_t value) +{ + *(volatile uint32_t *)addr = value; +} + +static inline uint32_t mmio_read_32(uintptr_t addr) +{ + return *(volatile uint32_t *)addr; +} + +static inline void mmio_write_64(uintptr_t addr, uint64_t value) +{ + *(volatile uint64_t *)addr = value; +} + +static inline uint64_t mmio_read_64(uintptr_t addr) +{ + return *(volatile uint64_t *)addr; +} + +#endif /* __MMIO_H__ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/reg_rcar_gen3.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/reg_rcar_gen3.h new file mode 100644 index 0000000..7d5116e --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/reg_rcar_gen3.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef __H_REG_RCAR_GEN3_ +#define __H_REG_RCAR_GEN3_ + +/*********************** RCarGen3_MFI *************************/ +#define MFISSOFTMDR 0xE6260600 //SOFTMD register +#define MFISSHESTSR 0xE6260604 //SHE status register + +/*********************** RCarGen3_LIFEC *************************/ +#define LIFEC_CC_LCS 0xE6110028 // cc_lcs Life cycle state read + +/*********************** RCarGen3_RST *************************/ +#define RST_MODEMR 0xE6160060 // Mode Monitor Register + +/*********************** RCarGen3_DMA *************************/ +#define DMA_DMAOR 0xE6700060 //DMA operation register (for west channel) +#define DMA_CHCLR 0xE6700080 //DMA channel clear register (for west channel) +#define DMA_SAR0 0xE6708000 //DMA source address register +#define DMA_DAR0 0xE6708004 //DMA destination address register +#define DMA_TCR0 0xE6708008 //DMA transfer count register +#define DMA_CHCR0 0xE670800C //DMA channel control register +#define DMA_DMARS0 0xE6708040 //DMA extended resource register + +/*********************** RCarGen3_RPC/QSPI *************************/ +//RPC/QSPI + +#define RPC_BASE 0xEE200000 +#define RPC_CMNCR (RPC_BASE + 0x0000) // +//#define RPC_DRCR (RPC_BASE + 0x000C) // +//#define RPC_DRCMR (RPC_BASE + 0x0010) // +//#define RPC_DRENR (RPC_BASE + 0x001C) // +#define RPC_SMCR (RPC_BASE + 0x0020) // +#define RPC_SMCMR (RPC_BASE + 0x0024) // +#define RPC_SMENR (RPC_BASE + 0x0030) // +#define RPC_CMNSR (RPC_BASE + 0x0048) // +//#define RPC_DRDMCR (RPC_BASE + 0x0058) // +//#define RPC_DRDRENR (RPC_BASE + 0x005C) // +//#define RPC_PHY_OFFSET1 (RPC_BASE + 0x0080) // +#define RPC_PHY_INT (RPC_BASE + 0x0088) // + + +/*********************** RCarH3_PFC *************************/ +// 5 . PFC + +#define PFC_BASE 0xE6060000 +#define RCarH3_PFC_PMMR (PFC_BASE + 0x0000) // LSI Multiplexed Pin Setting Mask Register +#define RCarH3_PFC_GPSR5 (PFC_BASE + 0x0114) // GPIO/peripheral function select register 5 +#define RCarH3_PFC_IPSR12 (PFC_BASE + 0x0230) // Peripheral function select register 12 +#define RCarH3_PFC_MOD_SEL1 (PFC_BASE + 0x0504) // Module select register 1 + + + +/*********************** RCarH3_SCIF ****************************************************/ +// 51 . Serial Communication Interface with FIFO (SCIF) +/* H3 SCIF2 */ +#define H3_SCIF2_BASE 0xE6E88000 + +#define RCarH3_SCIF2_SCSMR (H3_SCIF2_BASE + 0x00) // 16 Serial mode register +#define RCarH3_SCIF2_SCBRR (H3_SCIF2_BASE + 0x04) // 8 Bit rate register +#define RCarH3_SCIF2_SCSCR (H3_SCIF2_BASE + 0x08) // 16 Serial control register +#define RCarH3_SCIF2_SCFTDR (H3_SCIF2_BASE + 0x0C) // 8 Transmit FIFO data register +#define RCarH3_SCIF2_SCFSR (H3_SCIF2_BASE + 0x10) // 16 Serial status register +#define RCarH3_SCIF2_SCFRDR (H3_SCIF2_BASE + 0x14) // 8 Receive FIFO data register +#define RCarH3_SCIF2_SCFCR (H3_SCIF2_BASE + 0x18) // 16 FIFO control register +#define RCarH3_SCIF2_SCFDR (H3_SCIF2_BASE + 0x1C) // 16 FIFO data count register +#define RCarH3_SCIF2_SCSPTR (H3_SCIF2_BASE + 0x20) // 16 Serial port register +#define RCarH3_SCIF2_SCLSR (H3_SCIF2_BASE + 0x24) // 16 Line status register +#define RCarH3_SCIF2_DL (H3_SCIF2_BASE + 0x30) // 16 Frequency division register +#define RCarH3_SCIF2_CKS (H3_SCIF2_BASE + 0x34) // 16 Clock Select register +#define RCarH3_SCIF2_SCFER (H3_SCIF2_BASE + 0x44) // 16 FIFO error count register + +#define RCarH3_SCIF2_SCSMRIR (H3_SCIF2_BASE + 0x40) // 16 Serial mode register + + + +/*********************** RCarH3_CPG_Module Standby, Software Reset *************************/ +// 7A . Module Standby, Software Reset + +#define H3_CPG_MSTPRST_BASE 0xE6150000 + +#define RCarH3_CPG_MSTPSR3 (H3_CPG_MSTPRST_BASE+0x0048) // Module stop status register 3 +#define RCarH3_CPG_SMSTPCR3 (H3_CPG_MSTPRST_BASE+0x013C) // System module stop control register 3 +//#define RCarH3_CPG_SRCR3 (H3_CPG_MSTPRST_BASE+0x00B8) // Software reset register 3 + +#define RCarH3_CPG_CPGWPCR (H3_CPG_MSTPRST_BASE+0x0904) // CPG Write Protect Control Register +#define RCarH3_CPG_CPGWPR (H3_CPG_MSTPRST_BASE+0x0900) // CPG Write Protect Register + + + +#endif /* __H_REG_RCAR_GEN3_ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/scif.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/scif.h new file mode 100644 index 0000000..ba4ef40 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/scif.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef __SCIF_H__ +#define __SCIF_H__ + + +//SCIF0 +#define SCIF0_SCSMR 0xE6E60000 // R/W 16 Serial mode register +#define SCIF0_SCBRR 0xE6E60004 // R/W 8 Bit rate register +#define SCIF0_SCSCR 0xE6E60008 // R/W 16 Serial control register +#define SCIF0_SCFTDR 0xE6E6000C // W 8 Transmit FIFO data register +#define SCIF0_SCFSR 0xE6E60010 // R/W 16 Serial status register +#define SCIF0_SCFRDR 0xE6E60014 // R 8 Receive FIFO data register +#define SCIF0_SCFCR 0xE6E60018 // R/W 16 FIFO control register +#define SCIF0_SCFDR 0xE6E6001C // R 16 FIFO data count register +#define SCIF0_SCSPTR 0xE6E60020 // R/W 16 Serial port register +#define SCIF0_SCLSR 0xE6E60024 // R/W 16 Line status register +#define SCIF0_DL 0xE6E60030 // R/W 16 Frequency division register +#define SCIF0_CKS 0xE6E60034 // R/W 16 Clock Select register + +#define CR_CODE (0x0DU) +#define LF_CODE (0x0AU) + +void PutStr(const char *str,char rtn); +void PutChar(char outChar); + + +#endif /* __SCIF_H__ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/stdarg.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/stdarg.h new file mode 100644 index 0000000..c315dfc --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/stdarg.h @@ -0,0 +1,75 @@ +/*- + * Copyright (c) 2002 David E. O'Brien. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_STDARG_H_ +#define _MACHINE_STDARG_H_ + +#include +#include + +#ifndef _VA_LIST_DECLARED +#define _VA_LIST_DECLARED +typedef __va_list va_list; +#endif + +#ifdef __GNUCLIKE_BUILTIN_STDARG + +#define va_start(ap, last) \ + __builtin_va_start((ap), (last)) + +#define va_arg(ap, type) \ + __builtin_va_arg((ap), type) + +#define __va_copy(dest, src) \ + __builtin_va_copy((dest), (src)) + +#if __ISO_C_VISIBLE >= 1999 +#define va_copy(dest, src) \ + __va_copy(dest, src) +#endif + +#define va_end(ap) \ + __builtin_va_end(ap) + +#elif defined(lint) +/* Provide a fake implementation for lint's benefit */ +#define __va_size(type) \ + (((sizeof(type) + sizeof(long) - 1) / sizeof(long)) * sizeof(long)) +#define va_start(ap, last) \ + ((ap) = (va_list)&(last) + __va_size(last)) +#define va_arg(ap, type) \ + (*(type *)((ap) += __va_size(type), (ap) - __va_size(type))) +#define va_end(ap) + +#else +#error this file needs to be ported to your compiler +#endif + +#endif /* !_MACHINE_STDARG_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/stddef.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/stddef.h new file mode 100644 index 0000000..ea88214 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/stddef.h @@ -0,0 +1,64 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stddef.h 8.1 (Berkeley) 6/2/93 + * + * $FreeBSD$ + */ + +#ifndef _STDDEF_H_ +#define _STDDEF_H_ + +#include +#include +#include + +typedef __ptrdiff_t ptrdiff_t; + +#if __BSD_VISIBLE +#ifndef _RUNE_T_DECLARED +typedef __rune_t rune_t; +#define _RUNE_T_DECLARED +#endif +#endif + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#ifndef __cplusplus +#ifndef _WCHAR_T_DECLARED +typedef __wchar_t wchar_t; +#define _WCHAR_T_DECLARED +#endif +#endif + +#define offsetof(type, member) __offsetof(type, member) + +#endif /* _STDDEF_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/stdint.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/stdint.h new file mode 100644 index 0000000..aa5ac81 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/stdint.h @@ -0,0 +1,74 @@ +/*- + * Copyright (c) 2001 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS_STDINT_H_ +#define _SYS_STDINT_H_ + +#include +#include + +#include +#include + +typedef __int_least8_t int_least8_t; +typedef __int_least16_t int_least16_t; +typedef __int_least32_t int_least32_t; +typedef __int_least64_t int_least64_t; + +typedef __uint_least8_t uint_least8_t; +typedef __uint_least16_t uint_least16_t; +typedef __uint_least32_t uint_least32_t; +typedef __uint_least64_t uint_least64_t; + +typedef __int_fast8_t int_fast8_t; +typedef __int_fast16_t int_fast16_t; +typedef __int_fast32_t int_fast32_t; +typedef __int_fast64_t int_fast64_t; + +typedef __uint_fast8_t uint_fast8_t; +typedef __uint_fast16_t uint_fast16_t; +typedef __uint_fast32_t uint_fast32_t; +typedef __uint_fast64_t uint_fast64_t; + +#ifndef _INTMAX_T_DECLARED +typedef __intmax_t intmax_t; +#define _INTMAX_T_DECLARED +#endif +#ifndef _UINTMAX_T_DECLARED +typedef __uintmax_t uintmax_t; +#define _UINTMAX_T_DECLARED +#endif + +/* GNU and Darwin define this and people seem to think it's portable */ +#if defined(UINTPTR_MAX) && defined(UINT64_MAX) && (UINTPTR_MAX == UINT64_MAX) +#define __WORDSIZE 64 +#else +#define __WORDSIZE 32 +#endif + +#endif /* !_SYS_STDINT_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/stdio.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/stdio.h new file mode 100644 index 0000000..57e5c7f --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/stdio.h @@ -0,0 +1,78 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stdio.h 8.5 (Berkeley) 4/29/95 + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2013-2014, ARM Limited and Contributors. + * All rights reserved. + */ + + +#ifndef _STDIO_H_ +#define _STDIO_H_ + +#include +#include +#include + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#ifndef _SSIZE_T_DECLARED +#define _SSIZE_T_DECLARED +typedef __ssize_t ssize_t; +#endif + +#define EOF (-1) + +int printf(const char * __restrict, ...) __printflike(1, 2); +int putchar(int); +int puts(const char *); +int sprintf(char * __restrict, const char * __restrict, ...) + __printflike(2, 3); +int vsprintf(char * __restrict, const char * __restrict, + __va_list) __printflike(2, 0); + +int sscanf(const char *__restrict, char const *__restrict, ...); + +#if __ISO_C_VISIBLE >= 1999 +int snprintf(char * __restrict, size_t, const char * __restrict, + ...) __printflike(3, 4); +int vsnprintf(char * __restrict, size_t, const char * __restrict, + __va_list) __printflike(3, 0); +#endif + +#endif /* !_STDIO_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/string.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/string.h new file mode 100644 index 0000000..61e8102 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/string.h @@ -0,0 +1,66 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)string.h 8.1 (Berkeley) 6/2/93 + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2013-2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include +#include +#include + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +__BEGIN_DECLS + +void *memchr(const void *, int, size_t) __pure; +int memcmp(const void *, const void *, size_t) __pure; +void *memcpy(void * __restrict, const void * __restrict, size_t); +void *memmove(void *, const void *, size_t); +void *memset(void *, int, size_t); + +char *strchr(const char *, int) __pure; +int strcmp(const char *, const char *) __pure; +size_t strlen(const char *) __pure; +int strncmp(const char *, const char *, size_t) __pure; +int strcasecmp(const char *, const char *); + +__END_DECLS + +#endif /* _STRING_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/sys/_null.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/sys/_null.h new file mode 100644 index 0000000..92706c6 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/sys/_null.h @@ -0,0 +1,47 @@ +/*- + * Copyright (c) 2003 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef NULL + +#if !defined(__cplusplus) +#define NULL ((void *)0) +#else +#if __cplusplus >= 201103L +#define NULL nullptr +#elif defined(__GNUG__) && defined(__GNUC__) && __GNUC__ >= 4 +#define NULL __null +#else +#if defined(__LP64__) +#define NULL (0L) +#else +#define NULL 0 +#endif /* __LP64__ */ +#endif /* __GNUG__ */ +#endif /* !__cplusplus */ + +#endif diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/sys/_stdint.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/sys/_stdint.h new file mode 100644 index 0000000..d0f9249 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/sys/_stdint.h @@ -0,0 +1,82 @@ +/*- + * Copyright (c) 2011 David E. O'Brien + * Copyright (c) 2001 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS__STDINT_H_ +#define _SYS__STDINT_H_ + +#ifndef _INT8_T_DECLARED +typedef __int8_t int8_t; +#define _INT8_T_DECLARED +#endif + +#ifndef _INT16_T_DECLARED +typedef __int16_t int16_t; +#define _INT16_T_DECLARED +#endif + +#ifndef _INT32_T_DECLARED +typedef __int32_t int32_t; +#define _INT32_T_DECLARED +#endif + +#ifndef _INT64_T_DECLARED +typedef __int64_t int64_t; +#define _INT64_T_DECLARED +#endif + +#ifndef _UINT8_T_DECLARED +typedef __uint8_t uint8_t; +#define _UINT8_T_DECLARED +#endif + +#ifndef _UINT16_T_DECLARED +typedef __uint16_t uint16_t; +#define _UINT16_T_DECLARED +#endif + +#ifndef _UINT32_T_DECLARED +typedef __uint32_t uint32_t; +#define _UINT32_T_DECLARED +#endif + +#ifndef _UINT64_T_DECLARED +typedef __uint64_t uint64_t; +#define _UINT64_T_DECLARED +#endif + +#ifndef _INTPTR_T_DECLARED +typedef __intptr_t intptr_t; +#define _INTPTR_T_DECLARED +#endif +#ifndef _UINTPTR_T_DECLARED +typedef __uintptr_t uintptr_t; +#define _UINTPTR_T_DECLARED +#endif + +#endif /* !_SYS__STDINT_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/sys/_types.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/sys/_types.h new file mode 100644 index 0000000..1afeaea --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/sys/_types.h @@ -0,0 +1,106 @@ +/*- + * Copyright (c) 2002 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS__TYPES_H_ +#define _SYS__TYPES_H_ + +#include +#include + +/* + * Standard type definitions. + */ +typedef __uint32_t __blksize_t; /* file block size */ +typedef __int64_t __blkcnt_t; /* file block count */ +typedef __int32_t __clockid_t; /* clock_gettime()... */ +typedef __uint32_t __cap_rights_t; /* capability rights */ +typedef __uint32_t __fflags_t; /* file flags */ +typedef __uint32_t __fsblkcnt_t; +typedef __uint32_t __fsfilcnt_t; +typedef __uint32_t __gid_t; +typedef __int32_t __id_t; /* can hold a gid_t, pid_t, or uid_t */ +typedef __uint32_t __ino_t; /* inode number */ +typedef long __key_t; /* IPC key (for Sys V IPC) */ +typedef __int32_t __lwpid_t; /* Thread ID (a.k.a. LWP) */ +typedef __uint16_t __mode_t; /* permissions */ +typedef int __accmode_t; /* access permissions */ +typedef int __nl_item; +typedef __uint16_t __nlink_t; /* link count */ +typedef __int32_t __off_t; /* file offset */ +typedef __int32_t __pid_t; /* process [group] */ +typedef __int32_t __rlim_t; /* resource limit - intentionally */ + /* signed, because of legacy code */ + /* that uses -1 for RLIM_INFINITY */ +typedef __uint8_t __sa_family_t; +typedef __uint32_t __socklen_t; +typedef long __suseconds_t; /* microseconds (signed) */ +typedef struct __timer *__timer_t; /* timer_gettime()... */ +typedef struct __mq *__mqd_t; /* mq_open()... */ +typedef __uint32_t __uid_t; +typedef unsigned int __useconds_t; /* microseconds (unsigned) */ +typedef int __cpuwhich_t; /* which parameter for cpuset. */ +typedef int __cpulevel_t; /* level parameter for cpuset. */ +typedef int __cpusetid_t; /* cpuset identifier. */ + +/* + * Unusual type definitions. + */ +/* + * rune_t is declared to be an ``int'' instead of the more natural + * ``unsigned long'' or ``long''. Two things are happening here. It is not + * unsigned so that EOF (-1) can be naturally assigned to it and used. Also, + * it looks like 10646 will be a 31 bit standard. This means that if your + * ints cannot hold 32 bits, you will be in trouble. The reason an int was + * chosen over a long is that the is*() and to*() routines take ints (says + * ANSI C), but they use __ct_rune_t instead of int. + * + * NOTE: rune_t is not covered by ANSI nor other standards, and should not + * be instantiated outside of lib/libc/locale. Use wchar_t. wchar_t and + * rune_t must be the same type. Also, wint_t must be no narrower than + * wchar_t, and should be able to hold all members of the largest + * character set plus one extra value (WEOF), and must be at least 16 bits. + */ +typedef int __ct_rune_t; /* arg type for ctype funcs */ +typedef __ct_rune_t __rune_t; /* rune_t (see above) */ +typedef __ct_rune_t __wchar_t; /* wchar_t (see above) */ +typedef __ct_rune_t __wint_t; /* wint_t (see above) */ + +typedef __uint32_t __dev_t; /* device number */ + +typedef __uint32_t __fixpt_t; /* fixed point number */ + +/* + * mbstate_t is an opaque object to keep conversion state during multibyte + * stream conversions. + */ +typedef union { + char __mbstate8[128]; + __int64_t _mbstateL; /* for alignment */ +} __mbstate_t; + +#endif /* !_SYS__TYPES_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/include/sys/cdefs.h b/IPL/SDK/v3h/src/Dummy_RTOS/include/sys/cdefs.h new file mode 100644 index 0000000..16fb151 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/include/sys/cdefs.h @@ -0,0 +1,686 @@ +/*- + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Berkeley Software Design, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)cdefs.h 8.8 (Berkeley) 1/9/95 + * $FreeBSD$ + */ + +#ifndef _SYS_CDEFS_H_ +#define _SYS_CDEFS_H_ + +#if defined(__cplusplus) +#define __BEGIN_DECLS extern "C" { +#define __END_DECLS } +#else +#define __BEGIN_DECLS +#define __END_DECLS +#endif + +/* + * This code has been put in place to help reduce the addition of + * compiler specific defines in FreeBSD code. It helps to aid in + * having a compiler-agnostic source tree. + */ + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) + +#if __GNUC__ >= 3 || defined(__INTEL_COMPILER) +#define __GNUCLIKE_ASM 3 +#define __GNUCLIKE_MATH_BUILTIN_CONSTANTS +#else +#define __GNUCLIKE_ASM 2 +#endif +#define __GNUCLIKE___TYPEOF 1 +#define __GNUCLIKE___OFFSETOF 1 +#define __GNUCLIKE___SECTION 1 + +#ifndef __INTEL_COMPILER +# define __GNUCLIKE_CTOR_SECTION_HANDLING 1 +#endif + +#define __GNUCLIKE_BUILTIN_CONSTANT_P 1 +# if defined(__INTEL_COMPILER) && defined(__cplusplus) \ + && __INTEL_COMPILER < 800 +# undef __GNUCLIKE_BUILTIN_CONSTANT_P +# endif + +#if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3) && !defined(__INTEL_COMPILER) +# define __GNUCLIKE_BUILTIN_VARARGS 1 +# define __GNUCLIKE_BUILTIN_STDARG 1 +# define __GNUCLIKE_BUILTIN_VAALIST 1 +#endif + +#if defined(__GNUC__) +# define __GNUC_VA_LIST_COMPATIBILITY 1 +#endif + +#ifndef __INTEL_COMPILER +# define __GNUCLIKE_BUILTIN_NEXT_ARG 1 +# define __GNUCLIKE_MATH_BUILTIN_RELOPS +#endif + +#define __GNUCLIKE_BUILTIN_MEMCPY 1 + +/* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */ +#define __CC_SUPPORTS_INLINE 1 +#define __CC_SUPPORTS___INLINE 1 +#define __CC_SUPPORTS___INLINE__ 1 + +#define __CC_SUPPORTS___FUNC__ 1 +#define __CC_SUPPORTS_WARNING 1 + +#define __CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */ + +#define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1 + +#endif /* __GNUC__ || __INTEL_COMPILER */ + +/* + * Macro to test if we're using a specific version of gcc or later. + */ +#if defined(__GNUC__) && !defined(__INTEL_COMPILER) +#define __GNUC_PREREQ__(ma, mi) \ + (__GNUC__ > (ma) || __GNUC__ == (ma) && __GNUC_MINOR__ >= (mi)) +#else +#define __GNUC_PREREQ__(ma, mi) 0 +#endif + +/* + * The __CONCAT macro is used to concatenate parts of symbol names, e.g. + * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. + * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI + * mode -- there must be no spaces between its arguments, and for nested + * __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also + * concatenate double-quoted strings produced by the __STRING macro, but + * this only works with ANSI C. + * + * __XSTRING is like __STRING, but it expands any macros in its argument + * first. It is only available with ANSI C. + */ +#if defined(__STDC__) || defined(__cplusplus) +#define __P(protos) protos /* full-blown ANSI C */ +#define __CONCAT1(x,y) x ## y +#define __CONCAT(x,y) __CONCAT1(x,y) +#define __STRING(x) #x /* stringify without expanding x */ +#define __XSTRING(x) __STRING(x) /* expand x, then stringify */ + +#define __const const /* define reserved names to standard */ +#define __signed signed +#define __volatile volatile +#if defined(__cplusplus) +#define __inline inline /* convert to C++ keyword */ +#else +#if !(defined(__CC_SUPPORTS___INLINE)) +#define __inline /* delete GCC keyword */ +#endif /* ! __CC_SUPPORTS___INLINE */ +#endif /* !__cplusplus */ + +#else /* !(__STDC__ || __cplusplus) */ +#define __P(protos) () /* traditional C preprocessor */ +#define __CONCAT(x,y) x/**/y +#define __STRING(x) "x" + +#if !defined(__CC_SUPPORTS___INLINE) +#define __const /* delete pseudo-ANSI C keywords */ +#define __inline +#define __signed +#define __volatile +/* + * In non-ANSI C environments, new programs will want ANSI-only C keywords + * deleted from the program and old programs will want them left alone. + * When using a compiler other than gcc, programs using the ANSI C keywords + * const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS. + * When using "gcc -traditional", we assume that this is the intent; if + * __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone. + */ +#ifndef NO_ANSI_KEYWORDS +#define const /* delete ANSI C keywords */ +#define inline +#define signed +#define volatile +#endif /* !NO_ANSI_KEYWORDS */ +#endif /* !__CC_SUPPORTS___INLINE */ +#endif /* !(__STDC__ || __cplusplus) */ + +/* + * Compiler-dependent macros to help declare dead (non-returning) and + * pure (no side effects) functions, and unused variables. They are + * null except for versions of gcc that are known to support the features + * properly (old versions of gcc-2 supported the dead and pure features + * in a different (wrong) way). If we do not provide an implementation + * for a given compiler, let the compile fail if it is told to use + * a feature that we cannot live without. + */ +#ifdef lint +#define __dead2 +#define __pure2 +#define __unused +#define __packed +#define __aligned(x) +#define __section(x) +#else +#if !__GNUC_PREREQ__(2, 5) && !defined(__INTEL_COMPILER) +#define __dead2 +#define __pure2 +#define __unused +#endif +#if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 && !defined(__INTEL_COMPILER) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused +/* XXX Find out what to do for __packed, __aligned and __section */ +#endif +#if __GNUC_PREREQ__(2, 7) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) +#endif +#if defined(__INTEL_COMPILER) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) +#endif +#endif + +#if !__GNUC_PREREQ__(2, 95) +#define __alignof(x) __offsetof(struct { char __a; x __b; }, __b) +#endif + +/* + * Keywords added in C11. + */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define _Alignas(e) alignas(e) +#define _Alignof(e) alignof(e) +#define _Noreturn [[noreturn]] +#define _Static_assert(e, s) static_assert(e, s) +/* FIXME: change this to thread_local when clang in base supports it */ +#define _Thread_local __thread +#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +/* Do nothing. They are language keywords. */ +#else +/* Not supported. Implement them using our versions. */ +#define _Alignas(x) __aligned(x) +#define _Alignof(x) __alignof(x) +#define _Noreturn __dead2 +#define _Thread_local __thread +#ifdef __COUNTER__ +#define _Static_assert(x, y) __Static_assert(x, __COUNTER__) +#define __Static_assert(x, y) ___Static_assert(x, y) +#define ___Static_assert(x, y) typedef char __assert_ ## y[(x) ? 1 : -1] +#else +#define _Static_assert(x, y) struct __hack +#endif +#endif + +/* + * Emulation of C11 _Generic(). Unlike the previously defined C11 + * keywords, it is not possible to implement this using exactly the same + * syntax. Therefore implement something similar under the name + * __generic(). Unlike _Generic(), this macro can only distinguish + * between a single type, so it requires nested invocations to + * distinguish multiple cases. + */ + +#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +#define __generic(expr, t, yes, no) \ + _Generic(expr, t: yes, default: no) +#elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus) +#define __generic(expr, t, yes, no) \ + __builtin_choose_expr( \ + __builtin_types_compatible_p(__typeof(expr), t), yes, no) +#endif + +#if __GNUC_PREREQ__(2, 96) +#define __malloc_like __attribute__((__malloc__)) +#define __pure __attribute__((__pure__)) +#else +#define __malloc_like +#define __pure +#endif + +#if __GNUC_PREREQ__(3, 1) || (defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 800) +#define __always_inline __attribute__((__always_inline__)) +#else +#define __always_inline +#endif + +#if __GNUC_PREREQ__(3, 1) +#define __noinline __attribute__ ((__noinline__)) +#else +#define __noinline +#endif + +#if __GNUC_PREREQ__(3, 3) +#define __nonnull(x) __attribute__((__nonnull__(x))) +#else +#define __nonnull(x) +#endif + +#if __GNUC_PREREQ__(3, 4) +#define __fastcall __attribute__((__fastcall__)) +#else +#define __fastcall +#endif + +#if __GNUC_PREREQ__(4, 1) +#define __returns_twice __attribute__((__returns_twice__)) +#else +#define __returns_twice +#endif + +/* XXX: should use `#if __STDC_VERSION__ < 199901'. */ +#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER) +#define __func__ NULL +#endif + +#if (defined(__INTEL_COMPILER) || (defined(__GNUC__) && __GNUC__ >= 2)) && !defined(__STRICT_ANSI__) || __STDC_VERSION__ >= 199901 +#define __LONG_LONG_SUPPORTED +#endif + +/* C++11 exposes a load of C99 stuff */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define __LONG_LONG_SUPPORTED +#ifndef __STDC_LIMIT_MACROS +#define __STDC_LIMIT_MACROS +#endif +#ifndef __STDC_CONSTANT_MACROS +#define __STDC_CONSTANT_MACROS +#endif +#endif + +/* + * GCC 2.95 provides `__restrict' as an extension to C90 to support the + * C99-specific `restrict' type qualifier. We happen to use `__restrict' as + * a way to define the `restrict' type qualifier without disturbing older + * software that is unaware of C99 keywords. + */ +#if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95) +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901 || defined(lint) +#define __restrict +#else +#define __restrict restrict +#endif +#endif + +/* + * GNU C version 2.96 adds explicit branch prediction so that + * the CPU back-end can hint the processor and also so that + * code blocks can be reordered such that the predicted path + * sees a more linear flow, thus improving cache behavior, etc. + * + * The following two macros provide us with a way to utilize this + * compiler feature. Use __predict_true() if you expect the expression + * to evaluate to true, and __predict_false() if you expect the + * expression to evaluate to false. + * + * A few notes about usage: + * + * * Generally, __predict_false() error condition checks (unless + * you have some _strong_ reason to do otherwise, in which case + * document it), and/or __predict_true() `no-error' condition + * checks, assuming you want to optimize for the no-error case. + * + * * Other than that, if you don't know the likelihood of a test + * succeeding from empirical or other `hard' evidence, don't + * make predictions. + * + * * These are meant to be used in places that are run `a lot'. + * It is wasteful to make predictions in code that is run + * seldomly (e.g. at subsystem initialization time) as the + * basic block reordering that this affects can often generate + * larger code. + */ +#if __GNUC_PREREQ__(2, 96) +#define __predict_true(exp) __builtin_expect((exp), 1) +#define __predict_false(exp) __builtin_expect((exp), 0) +#else +#define __predict_true(exp) (exp) +#define __predict_false(exp) (exp) +#endif + +#if __GNUC_PREREQ__(4, 2) +#define __hidden __attribute__((__visibility__("hidden"))) +#define __exported __attribute__((__visibility__("default"))) +#else +#define __hidden +#define __exported +#endif + +/* + * We define this here since , , and + * require it. + */ +#if __GNUC_PREREQ__(4, 1) +#define __offsetof(type, field) __builtin_offsetof(type, field) +#else +#ifndef __cplusplus +#define __offsetof(type, field) \ + ((__size_t)(__uintptr_t)((const volatile void *)&((type *)0)->field)) +#else +#define __offsetof(type, field) \ + (__offsetof__ (reinterpret_cast <__size_t> \ + (&reinterpret_cast \ + (static_cast (0)->field)))) +#endif +#endif +#define __rangeof(type, start, end) \ + (__offsetof(type, end) - __offsetof(type, start)) + +/* + * Given the pointer x to the member m of the struct s, return + * a pointer to the containing structure. When using GCC, we first + * assign pointer x to a local variable, to check that its type is + * compatible with member m. + */ +#if __GNUC_PREREQ__(3, 1) +#define __containerof(x, s, m) ({ \ + const volatile __typeof(((s *)0)->m) *__x = (x); \ + __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\ +}) +#else +#define __containerof(x, s, m) \ + __DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m)) +#endif + +/* + * Compiler-dependent macros to declare that functions take printf-like + * or scanf-like arguments. They are null except for versions of gcc + * that are known to support the features properly (old versions of gcc-2 + * didn't permit keeping the keywords out of the application namespace). + */ +#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER) +#define __printflike(fmtarg, firstvararg) +#define __scanflike(fmtarg, firstvararg) +#define __format_arg(fmtarg) +#define __strfmonlike(fmtarg, firstvararg) +#define __strftimelike(fmtarg, firstvararg) +#else +#define __printflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf__, fmtarg, firstvararg))) +#define __scanflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__scanf__, fmtarg, firstvararg))) +#define __format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg))) +#define __strfmonlike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strfmon__, fmtarg, firstvararg))) +#define __strftimelike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strftime__, fmtarg, firstvararg))) +#endif + +/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */ +#if __FreeBSD_cc_version >= 300001 && defined(__GNUC__) && !defined(__INTEL_COMPILER) +#define __printf0like(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf0__, fmtarg, firstvararg))) +#else +#define __printf0like(fmtarg, firstvararg) +#endif + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) +#ifndef __INTEL_COMPILER +#define __strong_reference(sym,aliassym) \ + extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym))) +#endif +#ifdef __STDC__ +#define __weak_reference(sym,alias) \ + __asm__(".weak " #alias); \ + __asm__(".equ " #alias ", " #sym) +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning." #sym); \ + __asm__(".asciz \"" msg "\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@" #verid) +#define __sym_default(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@@" #verid) +#else +#define __weak_reference(sym,alias) \ + __asm__(".weak alias"); \ + __asm__(".equ alias, sym") +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning.sym"); \ + __asm__(".asciz \"msg\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver impl, sym@verid") +#define __sym_default(impl,sym,verid) \ + __asm__(".symver impl, sym@@verid") +#endif /* __STDC__ */ +#endif /* __GNUC__ || __INTEL_COMPILER */ + +#define __GLOBL1(sym) __asm__(".globl " #sym) +#define __GLOBL(sym) __GLOBL1(sym) + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) +#define __IDSTRING(name,string) __asm__(".ident\t\"" string "\"") +#else +/* + * The following definition might not work well if used in header files, + * but it should be better than nothing. If you want a "do nothing" + * version, then it should generate some harmless declaration, such as: + * #define __IDSTRING(name,string) struct __hack + */ +#define __IDSTRING(name,string) static const char name[] __unused = string +#endif + +/* + * Embed the rcs id of a source file in the resulting library. Note that in + * more recent ELF binutils, we use .ident allowing the ID to be stripped. + * Usage: + * __FBSDID("$FreeBSD$"); + */ +#ifndef __FBSDID +#if !defined(lint) && !defined(STRIP_FBSDID) +#define __FBSDID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __FBSDID(s) struct __hack +#endif +#endif + +#ifndef __RCSID +#ifndef NO__RCSID +#define __RCSID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __RCSID(s) struct __hack +#endif +#endif + +#ifndef __RCSID_SOURCE +#ifndef NO__RCSID_SOURCE +#define __RCSID_SOURCE(s) __IDSTRING(__CONCAT(__rcsid_source_,__LINE__),s) +#else +#define __RCSID_SOURCE(s) struct __hack +#endif +#endif + +#ifndef __SCCSID +#ifndef NO__SCCSID +#define __SCCSID(s) __IDSTRING(__CONCAT(__sccsid_,__LINE__),s) +#else +#define __SCCSID(s) struct __hack +#endif +#endif + +#ifndef __COPYRIGHT +#ifndef NO__COPYRIGHT +#define __COPYRIGHT(s) __IDSTRING(__CONCAT(__copyright_,__LINE__),s) +#else +#define __COPYRIGHT(s) struct __hack +#endif +#endif + +#ifndef __DECONST +#define __DECONST(type, var) ((type)(__uintptr_t)(const void *)(var)) +#endif + +#ifndef __DEVOLATILE +#define __DEVOLATILE(type, var) ((type)(__uintptr_t)(volatile void *)(var)) +#endif + +#ifndef __DEQUALIFY +#define __DEQUALIFY(type, var) ((type)(__uintptr_t)(const volatile void *)(var)) +#endif + +/*- + * The following definitions are an extension of the behavior originally + * implemented in , but with a different level of granularity. + * POSIX.1 requires that the macros we test be defined before any standard + * header file is included. + * + * Here's a quick run-down of the versions: + * defined(_POSIX_SOURCE) 1003.1-1988 + * _POSIX_C_SOURCE == 1 1003.1-1990 + * _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option + * _POSIX_C_SOURCE == 199309 1003.1b-1993 + * _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995, + * and the omnibus ISO/IEC 9945-1: 1996 + * _POSIX_C_SOURCE == 200112 1003.1-2001 + * _POSIX_C_SOURCE == 200809 1003.1-2008 + * + * In addition, the X/Open Portability Guide, which is now the Single UNIX + * Specification, defines a feature-test macro which indicates the version of + * that specification, and which subsumes _POSIX_C_SOURCE. + * + * Our macros begin with two underscores to avoid namespace screwage. + */ + +/* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 1 +#undef _POSIX_C_SOURCE /* Probably illegal, but beyond caring now. */ +#define _POSIX_C_SOURCE 199009 +#endif + +/* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 2 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199209 +#endif + +/* Deal with various X/Open Portability Guides and Single UNIX Spec. */ +#ifdef _XOPEN_SOURCE +#if _XOPEN_SOURCE - 0 >= 700 +#define __XSI_VISIBLE 700 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809 +#elif _XOPEN_SOURCE - 0 >= 600 +#define __XSI_VISIBLE 600 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200112 +#elif _XOPEN_SOURCE - 0 >= 500 +#define __XSI_VISIBLE 500 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199506 +#endif +#endif + +/* + * Deal with all versions of POSIX. The ordering relative to the tests above is + * important. + */ +#if defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE) +#define _POSIX_C_SOURCE 198808 +#endif +#ifdef _POSIX_C_SOURCE +#if _POSIX_C_SOURCE >= 200809 +#define __POSIX_VISIBLE 200809 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 200112 +#define __POSIX_VISIBLE 200112 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 199506 +#define __POSIX_VISIBLE 199506 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199309 +#define __POSIX_VISIBLE 199309 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199209 +#define __POSIX_VISIBLE 199209 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199009 +#define __POSIX_VISIBLE 199009 +#define __ISO_C_VISIBLE 1990 +#else +#define __POSIX_VISIBLE 198808 +#define __ISO_C_VISIBLE 0 +#endif /* _POSIX_C_SOURCE */ +#else +/*- + * Deal with _ANSI_SOURCE: + * If it is defined, and no other compilation environment is explicitly + * requested, then define our internal feature-test macros to zero. This + * makes no difference to the preprocessor (undefined symbols in preprocessing + * expressions are defined to have value zero), but makes it more convenient for + * a test program to print out the values. + * + * If a program mistakenly defines _ANSI_SOURCE and some other macro such as + * _POSIX_C_SOURCE, we will assume that it wants the broader compilation + * environment (and in fact we will never get here). + */ +#if defined(_ANSI_SOURCE) /* Hide almost everything. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1990 +#elif defined(_C99_SOURCE) /* Localism to specify strict C99 env. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1999 +#else /* Default environment: show everything. */ +#define __POSIX_VISIBLE 200809 +#define __XSI_VISIBLE 700 +#define __BSD_VISIBLE 1 +#define __ISO_C_VISIBLE 1999 +#endif +#endif + +#ifndef __has_feature +#define __has_feature(x) 0 +#endif +#ifndef __has_include +#define __has_include(x) 0 +#endif +#ifndef __has_builtin +#define __has_builtin(x) 0 +#endif + +#if defined(__mips) || defined(__powerpc64__) || defined(__arm__) +#define __NO_TLS 1 +#endif + +#endif /* !_SYS_CDEFS_H_ */ diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/rtos/rtos.ld.S b/IPL/SDK/v3h/src/Dummy_RTOS/rtos/rtos.ld.S new file mode 100644 index 0000000..05232ba --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/rtos/rtos.ld.S @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + + +OUTPUT_FORMAT("elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(Vector) + +MEMORY { + RAM (rwxa): ORIGIN = 0xEB200000, LENGTH = 0x000C0000 +} + + +SECTIONS +{ + . = 0xEB200000; + ASSERT(. == ALIGN(4096), + "CR7 dummy rtos address is not aligned on a page boundary.") + + ro . : { + __RO_START__ = .; + *rtos.o(.text*) + *rtos_main.o(.text*) + . = NEXT(32768); + *(.text*) + *(.rodata*) + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as + * read-only, executable. No RW data from the next section must + * creep in. Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + . = NEXT(16384); + __RO_END__ = .; + } >RAM + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + + stacks (NOLOAD) : ALIGN(16) { + __STACKS_START__ = .; + KEEP(*(tzfw_normal_stacks)) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } >RAM + + __BSS_SIZE__ = SIZEOF(.bss); + + ASSERT(. <= 0xEB2FE800, "CR7 dummy rtos has exceeded its limit.") +} diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/rtos/rtos.s b/IPL/SDK/v3h/src/Dummy_RTOS/rtos/rtos.s new file mode 100644 index 0000000..a4e92bf --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/rtos/rtos.s @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + + +#define DRAM_BASE (0x40000000) +#define SYSRAM_BASE (0xE6300000) +#define DTCM_BASE (0xEB020000) + +#define STACK_BASE_ABT (DTCM_BASE | 0x7080) +#define STACK_BASE_UND (DTCM_BASE | 0x7100) +#define STACK_BASE_FIQ (DTCM_BASE | 0x7180) +#define STACK_BASE_IRQ (DTCM_BASE | 0x7200) +#define STACK_BASE_SVC (DTCM_BASE | 0x8000) + + + .global Vector + .global Start + .local rtos_stacks + +/***************************************************************************** + * Vector table + *****************************************************************************/ + .align 5 + +Vector: + b Start /* Reset */ + b Undef /* Undefined Instruction */ + b SWI /* Supervisor Call */ + b PAbort /* Prefetch Abort */ + b DAbort /* Data Abort */ + nop /* Not used */ + b IRQ /* IRQ interrupt */ + b FIQ /* FIQ interrupt */ + + +/***************************************************************************** + * Reset Hander + *****************************************************************************/ +Start: + /* initialize registers*/ + mov r0, #0 + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 + mov r8, #0 + mov r9, #0 + mov r10, #0 + mov r11, #0 + mov r12, #0 + mov lr, #0 + + /* CR7_CONFIGURE_MPU */ +;# region 0: all memory with r/w access for everyone + MOV r0,#0 + MCR p15,0,r0,c6,c2,0 ;# region number + MOV r0,#0x0 ;# base address + MCR p15,0,r0,c6,c1,0 ;# D-side base addr + MCR p15,0,r0,c6,c1,1 ;# I-side base addr + MOV r0,#0x3E|0x1 ;# 4GB, all memory + MCR p15,0,r0,c6,c1,2 ;# D-side size & enable + MCR p15,0,r0,c6,c1,3 ;# I-side size & enable + LDR r0,=(0x300|0x00B|0x004) ;# 0x00B + MCR p15,0,r0,c6,c1,4 ;# D-side access control + MCR p15,0,r0,c6,c1,5 ;# I-side access control + +;# region 1: Peripheral (0xE0000000~0xFFFFFFFF) + MOV r0,#1 + MCR p15,0,r0,c6,c2,0 ;# region number + MOV r0,#0xE0000000 ;# base address + MCR p15,0,r0,c6,c1,0 ;# D-side base addr + MCR p15,0,r0,c6,c1,1 ;# I-side base addr + MOV r0,#0x38 | 0x1 ;# 512MB, all memory + MCR p15,0,r0,c6,c1,2 ;# D-side size & enable + MCR p15,0,r0,c6,c1,3 ;# I-side size & enable + LDR r0,=0x300|0x001|0x004 ;# 0x001 + MCR p15,0,r0,c6,c1,4 ;# D-side access control + MCR p15,0,r0,c6,c1,5 ;# I-side access control + +;# region 2: SecureRAM (0xEB200000) + MOV r0,#2 + MCR p15,0,r0,c6,c2,0 ;# region number +;# LDR r0, =0xE6300000 ;# base address + LDR r0, =0xEB200000 ;# base address + MCR p15,0,r0,c6,c1,0 ;# D-side base addr + MCR p15,0,r0,c6,c1,1 ;# I-side base addr +;# MOV r0,#REGION_SIZE_512KB | 0x1 ; 512KB, all memory + MOV r0,#0x26 | 0x1 ;# 1MB, all memory + MCR p15,0,r0,c6,c1,2 ;# D-side size & enable + MCR p15,0,r0,c6,c1,3 ;# I-side size & enable + LDR r0,=0x300 | 0x00B | 0x004 ;# 0x00B + MCR p15,0,r0,c6,c1,4 ;# D-side access control + MCR p15,0,r0,c6,c1,5 ;# I-side access control + +;# region 3: TCM (0xEB000000) + MOV r0,#3 + MCR p15,0,r0,c6,c2,0 ;# region number + LDR r0, =0xEB000000 ;# base address + MCR p15,0,r0,c6,c1,0 ;# D-side base addr + MCR p15,0,r0,c6,c1,1 ;# I-side base addr + MOV r0,#0x1E | 0x1 ;# 64KB, all memory + MCR p15,0,r0,c6,c1,2 ;# D-side size & enable + MCR p15,0,r0,c6,c1,3 ;# I-side size & enable + LDR r0,=0x300 | 0x00B | 0x004 ;# 0x00B + MCR p15,0,r0,c6,c1,4 ;# D-side access control + MCR p15,0,r0,c6,c1,5 ;# I-side access control + +;# region 4: SecureROM (0xEB100000) + MOV r0,#4 + MCR p15,0,r0,c6,c2,0 ;# region number + LDR r0, =0xEB100000 ;# base address + MCR p15,0,r0,c6,c1,0 ;# D-side base addr + MCR p15,0,r0,c6,c1,1 ;# I-side base addr + MOV r0,#0x22 | 0x1 ;# 256KB, all memory + MCR p15,0,r0,c6,c1,2 ;# D-side size & enable + MCR p15,0,r0,c6,c1,3 ;# I-side size & enable + LDR r0,=0x300 | 0x00B | 0x004 ;# 0x00B + MCR p15,0,r0,c6,c1,4 ;# D-side access control + MCR p15,0,r0,c6,c1,5 ;# I-side access control + +;#CR7_SET_MPU_ON + MRC p15, 0, r0, c1, c0, 0 + ORR r0, r0, #0x00000001 + DSB + MCR p15, 0, r0, c1, c0, 0 + ISB + + LDR PC, =STACK_INIT + +STACK_INIT: + /* stack initialize */ + ldr r0, =__STACKS_END__ + + msr CPSR_c, #(0x17 | 0x80 | 0x40) /* ABT */ + mov sp, r0 /* STACK_BASE_ABT */ + + msr CPSR_c, #(0x1B | 0x80 | 0x40) /* UND */ + sub r0, r0, #0x80 /* STACK_BASE_UND */ + mov sp, r0 + + msr CPSR_c, #(0x11 | 0x80 | 0x40) /* FIQ */ + sub r0, r0, #0x80 /* STACK_BASE_FIQ */ + mov sp, r0 + + msr CPSR_c, #(0x12 | 0x80 | 0x40) /* IRQ */ + sub r0, r0, #0x80 /* STACK_BASE_IRQ */ + mov sp, r0 + + msr CPSR_c, #(0x13 | 0x80 | 0x40) /* SVC */ + sub r0, r0, #0x80 /* STACK_BASE_SVC */ + mov sp, r0 + + + /* Loader Main */ + BL rtos_main + +NO_BOOT: + nop +1: + wfe + b 1b + + +/***************************************************************************** + * Exception Handers + *****************************************************************************/ + + /* Undefined Instruction */ +Undef: + nop +1: + wfe + b 1b + + /* Supervisor Call */ +SWI: + nop +1: + wfe + b 1b + + /* Prefetch Abort */ +PAbort: + nop +1: + wfe + b 1b + + /* Data Abort */ +DAbort: + nop +1: + wfe + b 1b + + /* IRQ interrupt */ +IRQ: + nop +1: + wfe + b 1b + + /* FIQ interrupt */ +FIQ: + nop +1: + wfe + b 1b + + +/***************************************************************************** + * Define stack + *****************************************************************************/ + .section tzfw_normal_stacks, "aw" + .align 6 + +rtos_stacks: + .space 4 * 1024 + + .end diff --git a/IPL/SDK/v3h/src/Dummy_RTOS/rtos/rtos_main.c b/IPL/SDK/v3h/src/Dummy_RTOS/rtos/rtos_main.c new file mode 100644 index 0000000..b06a1d4 --- /dev/null +++ b/IPL/SDK/v3h/src/Dummy_RTOS/rtos/rtos_main.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + + +#include +#include "scif.h" + + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Unions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Structs */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Globals */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Macros */ +/************************************************************************************************/ +#define MIDR_PN_SHIFT (0x4U) +#define MIDR_PN_MASK (0X0FFFU) +#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT) +#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT) +#define MIDR_CR7 (0x0C17U << MIDR_PN_SHIFT) + +#define RCAR_PRR (0xFFF00044U) /* Product register */ +#define RCAR_PRODUCT_MASK (0x00007F00U) +#define RCAR_CUT_MASK (0x000000FFU) +#define RCAR_PRODUCT_H3 (0x00004F00U) +#define RCAR_PRODUCT_M3 (0x00005200U) +#define RCAR_CUT_ES10 (0x00000000U) +#define RCAR_CUT_ES11 (0x00000001U) +#define RCAR_MAJOR_MASK (0x000000F0U) +#define RCAR_MINOR_MASK (0x0000000FU) +#define RCAR_PRODUCT_SHIFT (8U) +#define RCAR_MAJOR_SHIFT (4U) +#define RCAR_MINOR_SHIFT (0U) +#define RCAR_MAJOR_OFFSET (1U) + + +/************************************************************************************************/ +/* Prototypes */ +/************************************************************************************************/ +uint32_t rtos_main(void); + + +uint32_t rtos_main(void) +{ + volatile uint32_t i; + for (i = 0; i < 0x00300000U; i++) { + }; + + PutStr(" ",1); + PutStr("Dummy RTOS Program",1); + PutStr("Dummy RTOS Program boot end",1); + + return 0U; +} diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/.gitignore b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/.gitignore new file mode 100644 index 0000000..5c39a00 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/.gitignore @@ -0,0 +1 @@ +build_message.c \ No newline at end of file diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/Makefile b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/Makefile new file mode 100644 index 0000000..37d5b42 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/Makefile @@ -0,0 +1,318 @@ +# ****************************************************************************** +# * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. +# * +# * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +# * +# * This software is provided as reference/sample code under the license +# * agreement between Renesas Electronics Corporation and licensee (the +# * "License Agreement") and shall be treated as specified in the License +# * Agreement. +# * These instructions, statements, and software are the confidential +# * information of Renesas Electronics Corporation. They must be used and +# * modified solely for the purpose for which it was furnished by Renesas +# * Electronics Corporation. All or part of these instructions, statements and +# * software must not be reproduced nor disclosed to any third party in any +# * form, unless permitted by the License Agreement. +# * +# * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND +# * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +# * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. +# * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, +# * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +# * DAMAGE. +# ****************************************************************************** + +# ****************************************************************************** +# * DESCRIPTION : makefile for Loader +# ****************************************************************************** + +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +INCLUDE_DIR = -Iinclude + +OUTDIR := build + +#output file name +FILE_NAME = icumxa_loader +FILE_NAME_SA0 = bootparam_sa0 +FILE_NAME_SA6 = cert_header_sa6 + +OUTPUT_FILE = $(FILE_NAME).elf +OUTPUT_FILE_SA0 = $(FILE_NAME_SA0).elf +OUTPUT_FILE_SA6 = $(FILE_NAME_SA6).elf + +#object file name +OBJ_FILE = common/mem_io/mem_io.o \ + common/log/log.o \ + common/log/scif.o \ + common/timer/micro_wait.o \ + image_load/image_load.o \ + ip/axi-bus_edcint/edcinten.o \ + ip/ip_control.o \ + ip/cpg/cpg.o \ + ip/pfc/pfc.o \ + ip/qos/qos.o \ + ip/dma/dma.o \ + ip/rpc/rpc.o \ + ip/mfis/mfis.o \ + ip/wdt/wdt.o \ + protect/acc_prot.o \ + protect/lifec/acc_prot_lifec.o \ + protect/memory/acc_prot_memory.o\ + loader/loader_main.o \ + loader/loader.o \ + loader/cpu_on.o \ + remap/remap.o \ + rom_api/rom_api.o + + +OBJ_FILE_SA0 = tools/dummy_create/sa0.o +OBJ_FILE_SA6 = tools/dummy_create/sa6.o + +#linker script name +MEMORY_DEF = loader/icumxa_loader.ld +MEMORY_DEF_SA0 = tools/dummy_create/sa0.ld +MEMORY_DEF_SA6 = tools/dummy_create/sa6.ld + +################################################### + +# Debug build +DEBUG:=0 + +# Process DEBUG flag +$(eval $(call assert_boolean,DEBUG)) +$(eval $(call add_define,DEBUG)) +ifeq (${DEBUG},0) + $(eval $(call add_define,NDEBUG)) +ASFLAGS += -G -dwarf2 +CFLAGS += -G -dwarf2 -Ogeneral +else +ASFLAGS += -G -dwarf2 +CFLAGS += -G -dwarf2 -Odebug +endif + +# Process RCAR_SECURE_BOOT flag +ifndef RCAR_SECURE_BOOT +RCAR_SECURE_BOOT := 1 +endif +$(eval $(call add_define,RCAR_SECURE_BOOT)) + +# Process LOG_LEVEL +ifndef LOG_LEVEL +LOG_LEVEL := 2 +endif +$(eval $(call add_define,LOG_LEVEL)) + +# Process ACC_PROT_ENABLE flag +ifndef ACC_PROT_ENABLE +ACC_PROT_ENABLE := 1 +endif +$(eval $(call add_define,ACC_PROT_ENABLE)) + +# Process RCAR_DRAM_SPLIT flag +ifndef RCAR_DRAM_SPLIT +RCAR_DRAM_SPLIT := 0 +endif +$(eval $(call add_define,RCAR_DRAM_SPLIT)) + +# Process RCAR_DRAM_LPDDR4_MEMCONF flag +ifndef RCAR_DRAM_LPDDR4_MEMCONF +RCAR_DRAM_LPDDR4_MEMCONF :=1 +endif +$(eval $(call add_define,RCAR_DRAM_LPDDR4_MEMCONF)) + +# Process RCAR_DRAM_CHANNEL flag +ifndef RCAR_DRAM_CHANNEL +RCAR_DRAM_CHANNEL :=1 +endif +$(eval $(call add_define,RCAR_DRAM_CHANNEL)) + +# Process RCAR_REWT_TRAINING flag +ifndef RCAR_REWT_TRAINING +RCAR_REWT_TRAINING := 1 +endif +$(eval $(call add_define,RCAR_REWT_TRAINING)) + +# Process RCAR_DDR_REG_CHECK flag +ifndef RCAR_DDR_REG_CHECK +RCAR_DDR_REG_CHECK :=0 +endif +$(eval $(call add_define,RCAR_DDR_REG_CHECK)) + + + +################################################### +# pass SecureMonitor parametor +################################################### +# Process CA53_PROG1_SMONI flag +ifndef CA53_PROG1_IS_SMONI +CA53_PROG1_IS_SMONI := 1 +endif +$(eval $(call add_define,CA53_PROG1_IS_SMONI)) + +ifeq (${CA53_PROG1_IS_SMONI},1) + # STag_Smoni_EntrypointInfo parametor + ifndef CA53_PROG2_ATTR + CA53_PROG2_ATTR := 0x00000001 + endif + + ifndef CA53_PROG2_PC + CA53_PROG2_PC := 0x0000000050000000 + endif + + ifndef CA53_PROG2_SPSR + CA53_PROG2_SPSR := 0x00000000000003C5 + endif + + ifndef CA53_PROG2_ARG0 + CA53_PROG2_ARG0 := 0x0000000000000000 + endif + + ifndef CA53_PROG2_ARG1 + CA53_PROG2_ARG1 := 0x0000000000000000 + endif + + ifndef CA53_PROG2_ARG2 + CA53_PROG2_ARG2 := 0x0000000000000000 + endif + + ifndef CA53_PROG2_ARG3 + CA53_PROG2_ARG3 := 0x0000000000000000 + endif + + ifndef CA53_PROG2_ARG4 + CA53_PROG2_ARG4 := 0x0000000000000000 + endif + + ifndef CA53_PROG2_ARG5 + CA53_PROG2_ARG5 := 0x0000000000000000 + endif + + ifndef CA53_PROG2_ARG6 + CA53_PROG2_ARG6 := 0x0000000000000000 + endif + + ifndef CA53_PROG2_ARG7 + CA53_PROG2_ARG7 := 0x0000000000000000 + endif + + + $(eval $(call add_define,SMONI_ATTR)) + $(eval $(call add_define,CA53_PROG2_ATTR)) + $(eval $(call add_define,CA53_PROG2_PC)) + $(eval $(call add_define,CA53_PROG2_SPSR)) + $(eval $(call add_define,CA53_PROG2_ARG0)) + $(eval $(call add_define,CA53_PROG2_ARG1)) + $(eval $(call add_define,CA53_PROG2_ARG2)) + $(eval $(call add_define,CA53_PROG2_ARG3)) + $(eval $(call add_define,CA53_PROG2_ARG4)) + $(eval $(call add_define,CA53_PROG2_ARG5)) + $(eval $(call add_define,CA53_PROG2_ARG6)) + $(eval $(call add_define,CA53_PROG2_ARG7)) +endif + +include ip/ddr/ddr.mk + +################################################### + +OUTDIR_REL := $(OUTDIR)/release +OUTDIR_OBJ := $(OUTDIR)/obj + +OBJ_FILE := $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o) +OBJ_FILE_SA0 := $(OBJ_FILE_SA0:%.o=$(OUTDIR_OBJ)/%.o) +OBJ_FILE_SA6 := $(OBJ_FILE_SA6:%.o=$(OUTDIR_OBJ)/%.o) + +CC = cxrh850 +AS = cxrh850 +LD = cxrh850 +OC = gsrec +OD = gdump + +ASFLAGS += -asm="-preprocess_assembly_files" \ + -asm="-nostartfiles" \ + -D__ASSEMBLY \ + $(INCLUDE_DIR) $(DEFINES) + +CFLAGS += -nostartfiles \ + -c99 \ + $(INCLUDE_DIR) $(DEFINES) + + #-nostdlib + +LDFLAGS = -nostartfiles +#LDFLAGS += -llib8bit_s32.a -llib8bit_u16.a +#LDFLAGS += -v -llibansi.a -llibarch.a -llibstartup.a +#-nostdlib + +BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__ + +################################################### +.SUFFIXES : .s .c .o + +################################################### +# command + +.PHONY: all +all: $(OUTPUT_FILE) $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA6) + +################################################### +# Linker +################################################### +$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE) + @echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' > $(OUTDIR_OBJ)/build_message.c + @$(CC) $(CFLAGS) -o $(OUTDIR_OBJ)/build_message.o -c $(OUTDIR_OBJ)/build_message.c + + @$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \ + -T $(MEMORY_DEF) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE) \ + $(LDFLAGS) \ + -map=$(OUTDIR_REL)/$(FILE_NAME).map + + @$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).srec + @$(OD) -full -ysec $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE) -o $(OUTDIR_REL)/$(OUTPUT_FILE:%.elf=%.bin) + +$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0) + @$(LD) $(OBJ_FILE_SA0) \ + -T $(MEMORY_DEF_SA0) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) \ + -map=$(OUTDIR_REL)/$(FILE_NAME_SA0).map \ + -nostdlib + + @$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) > $(OUTDIR_REL)/$(FILE_NAME_SA0).srec + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0:%.elf=%.bin) + +$(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6) + @$(LD) $(OBJ_FILE_SA6) \ + -T $(MEMORY_DEF_SA6) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA6) \ + -map=$(OUTDIR_REL)/$(FILE_NAME_SA6).map \ + -nostdlib + + @$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA6) > $(OUTDIR_REL)/$(FILE_NAME_SA6).srec + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA6) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA6:%.elf=%.bin) + + + +################################################### +# Compile +################################################### + +$(OUTDIR_OBJ)/%.o:%.c + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + @$(CC) $(CFLAGS) -o $@ -c $< + +$(OUTDIR_OBJ)/%.o:%.S + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + @$(AS) $(ASFLAGS) -o $@ -c $< + + +.PHONY: clean +clean: + @rm -rf $(OUTDIR) diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/common/log/log.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/common/log/log.c new file mode 100644 index 0000000..c3fc49d --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/common/log/log.c @@ -0,0 +1,84 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Log driver + ******************************************************************************/ +/****************************************************************************** + * @file log.c + * - Version : 0.01 + * @brief Log driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include + +#define VSPRINTF_OK (0) + +void local_printf(const char *fmt, ...) +{ + va_list ap; + static char s_buffer[1024]; + int32_t num; + uint32_t loop; + + /* Convert all arguments to one string */ + va_start(ap, fmt); + num = vsprintf(s_buffer, fmt, ap); + va_end(ap); + + /* String output */ + if (VSPRINTF_OK <= num) + { + for (loop = 0U; loop < num; loop++) + { + (void)console_putc((uint8_t)s_buffer[loop]); + /* If the outputted character is LF, output CR */ + if (s_buffer[loop] == '\n') + { + (void)console_putc((uint8_t)'\r'); + } + } + } + else + { + while(1) + { + /* loop due to error detection. */ + } + } +} +/* End of function local_printf(const char *fmt, ...) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/common/log/scif.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/common/log/scif.c new file mode 100644 index 0000000..0544e47 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/common/log/scif.c @@ -0,0 +1,191 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : SCIF driver + ******************************************************************************/ +/****************************************************************************** + * @file scif.c + * - Version : 0.01 + * @brief 1. Initial setting of SCIF. + * 2. Log output function. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Define */ +#define SCIF_SCSCR_TE_EN (uint16_t)((uint16_t)1U << 5U) +#define SCIF_SCSCR_RE_EN (uint16_t)((uint16_t)1U << 4U) +#define SCIF_SCSCR_CKE_MASK (uint16_t)((uint16_t)3U << 0U) +#define SCIF_SCSCR_INIT_DATA (uint16_t)(SCIF_SCSCR_TE_EN | SCIF_SCSCR_RE_EN) +#define SCIF_SCSCR_HW_INIT (uint16_t)(0x0000U) + +#define SCIF_SCFCR_TFRST_EN (uint16_t)((uint16_t)1U << 2U) +#define SCIF_SCFCR_RFRS_EN (uint16_t)((uint16_t)1U << 1U) +#define SCIF_SCFCR_RESET_FIFO (uint16_t)(SCIF_SCFCR_TFRST_EN | SCIF_SCFCR_RFRS_EN) +#define SCIF_SCFCR_INIT_DATA (uint16_t)(0x0000U) + +#define SCIF_SCFSR_TEND (uint16_t)((uint16_t)1U << 6U) +#define SCIF_SCFSR_TDFE (uint16_t)((uint16_t)1U << 5U) +#define TRANS_END_CHECK (uint16_t)(SCIF_SCFSR_TEND | SCIF_SCFSR_TDFE) +#define SCIF_SCFSR_INIT_DATA (uint16_t)(0x0000U) + +#define SCIF_SCLSR_INIT_DATA (uint16_t)(0x0000U) + +#define SCIF_SCSMR_INIT_DATA (uint16_t)(0x0000U) + +#define SCIF_SCBRR_115200BPS (uint8_t)(0x11U) +#define SCIF_SCBRR_INIT_DATA (SCIF_SCBRR_115200BPS) +#define SCIF_SCBRR_HW_INIT (uint8_t)(0xFFU) + +#define CPG_MSTPSR2_SCIF0 (((uint32_t)1U) << 7U) +#define CPG_MSTPSR2_SCIF0_ENABLE (((uint32_t)0U) << 7U) + +#define GPSR4_SDA2 ((uint32_t)1U << 5U) +#define GPSR4_SCL2 ((uint32_t)1U << 4U) +#define IPSR_24 ((uint32_t)4U << 24U) +#define IPSR_20 ((uint32_t)4U << 20U) +#define PFC_GPSR_SCIF_MASK (uint32_t)(0x00000030U) /* SCIF0/HSCIF0_B RX/TX */ +#define PFC_GPSR_SCIF_VAL (uint32_t)(GPSR4_SDA2 | GPSR4_SCL2) /* SCIF0/HSCIF0_B RX/TX */ +#define PFC_IPSR_SCIF_MASK (uint32_t)(0x0FF00000U) /* SCIF0 RX/TX */ +#define PFC_IPSR_SCIF_VAL (uint32_t)(IPSR_24 | IPSR_20) /* SCIF0 RX/TX */ + +static void scif0_module_start(void); +static void scif0_pfc_init(void); +static void scif0_console_init(void); + +static void scif0_module_start(void) +{ + uint32_t reg; + + reg = mem_read32(CPG_MSTPSR2); + /* If supply of clock to SCIF0 is stopped */ + if ((CPG_MSTPSR2_SCIF0 & reg) != CPG_MSTPSR2_SCIF0_ENABLE) { + /* Supply of clock to SCIF0 is start */ + mem_write32((uintptr_t)CPG_CPGWPR, CPG_MSTPSR2_SCIF0); /* write protect */ + cpg_reg_write(CPG_SCMSTPCR2, CPG_MSTPSR2, ~(CPG_MSTPSR2_SCIF0)); + } +} +/* End of function scif0_module_start(void) */ + +static void scif0_pfc_init(void) +{ + uint32_t reg; + + /* Set RX / TX of SCIF 0. */ + reg = mem_read32(PFC_IPSR7); + reg &= (~(PFC_IPSR_SCIF_MASK)); + reg |= PFC_IPSR_SCIF_VAL; + pfc_reg_write(PFC_IPSR7, reg); + + reg = mem_read32(PFC_GPSR4); + reg &= (~(PFC_GPSR_SCIF_MASK)); + reg |= PFC_GPSR_SCIF_VAL; + pfc_reg_write(PFC_GPSR4, reg); +} +/* End of function scif0_pfc_init(void) */ + +static void scif0_console_init(void) +{ + volatile uint16_t reg; + + /* clear SCR.TE & SCR.RE*/ + mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + mem_write16(SCIF_SCFCR, SCIF_SCFCR_RESET_FIFO); + + /* clear ORER bit */ + mem_write16(SCIF_SCLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(SCIF_SCFSR, SCIF_SCFSR_INIT_DATA); + + /* internal clock, SC_CLK pin unused for output pin */ + mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT); + /* 8bit data, no-parity, 1 stop, Po/1 */ + mem_write16(SCIF_SCSMR, SCIF_SCSMR_INIT_DATA); + /* Pclk(66MHz)/1, 115.2kBps*/ + /* N = 66/(66/2*115200)*10^4-1 =17=> 0x11 */ + mem_write16(SCIF_SCBRR, SCIF_SCBRR_115200BPS); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + mem_write16(SCIF_SCFCR, SCIF_SCFCR_INIT_DATA); + /* enable TE, RE; SC_CLK=no output */ + mem_write16(SCIF_SCSCR, SCIF_SCSCR_INIT_DATA); +} +/* End of function scif0_console_init(void) */ + +void scif_init(void) +{ + scif0_module_start(); + scif0_pfc_init(); + scif0_console_init(); +} +/* End of function scif_init(void) */ + +void scif_release(void) +{ + /* set HW initial value */ + mem_write16(SCIF_SCFCR, SCIF_SCFCR_INIT_DATA); + mem_write16(SCIF_SCBRR, SCIF_SCBRR_HW_INIT); + mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT); +} +/* End of function scif_release(void) */ + +void console_putc(uint8_t outchar) +{ + uint16_t reg; + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK)) + { + ; + } + + mem_write8(SCIF_SCFTDR, outchar); /* Transfer one character */ + reg = mem_read16(SCIF_SCFSR); + reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */ + mem_write16(SCIF_SCFSR, reg); +} +/* End of function console_putc(uint8_t outchar) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/common/mem_io/mem_io.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/common/mem_io/mem_io.c new file mode 100644 index 0000000..e8ef25d --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/common/mem_io/mem_io.c @@ -0,0 +1,92 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : memory access driver + ******************************************************************************/ + /****************************************************************************** + * @file mem_io.c + * - Version : 0.01 + * @brief Memory access driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include +#include + +void mem_write8(uintptr_t addr, uint8_t data) +{ + *(volatile uint8_t*)addr = data; +} +/* End of function mem_write8(uintptr_t addr, uint8_t data) */ + +uint8_t mem_read8(uintptr_t addr) +{ + return (*(volatile uint8_t*)addr); +} +/* End of function mem_read8(uintptr_t addr) */ + +void mem_write16(uintptr_t addr, uint16_t data) +{ + *(volatile uint16_t*)addr = data; +} +/* End of function mem_write16(uintptr_t addr, uint16_t data) */ + +uint16_t mem_read16(uintptr_t addr) +{ + return (*(volatile uint16_t*)addr); +} +/* End of function mem_read16(uintptr_t addr) */ + +void mem_write32(uintptr_t addr, uint32_t data) +{ + *(volatile uint32_t*)addr = data; +} +/* End of function mem_write32(uintptr_t addr, uint32_t data) */ + +uint32_t mem_read32(uintptr_t addr) +{ + return (*(volatile uint32_t*)addr); +} +/* End of function mem_read32(uintptr_t addr) */ + +void mem_write64(uintptr_t addr, uint64_t data) +{ + *(volatile uint64_t*)addr = data; +} +/* End of function mem_write64(uintptr_t addr, uint64_t data) */ + +void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set) +{ + mem_write32(addr, (mem_read32(addr) & ~clr) | set); +} +/* End of function mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/common/timer/micro_wait.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/common/timer/micro_wait.c new file mode 100644 index 0000000..61cb399 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/common/timer/micro_wait.c @@ -0,0 +1,107 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Time wait driver + ******************************************************************************/ +/****************************************************************************** + * @file micro_wait.c + * - Version : 0.01 + * @brief Wait of micro second + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + +#define INTICUOSTM0 (0xFFFEEA14U) +#define INTCR_RF (uint16_t)((uint16_t)1U << 12U) +#define INTCR_RF_NO_REQ (uint16_t)((uint16_t)0U << 12U) + +#define OSTM0_BASE (0xFFFEE000U) +#define OSTM0CMP (OSTM0_BASE) +#define OSTM0CNT (OSTM0_BASE + 0x0004U) +#define OSTM0TE (OSTM0_BASE + 0x0010U) +#define OSTM0TS (OSTM0_BASE + 0x0014U) +#define OSTM0TT (OSTM0_BASE + 0x0018U) +#define OSTM0CTL (OSTM0_BASE + 0x0020U) +#define OSTM0EMU (OSTM0_BASE + 0x0024U) + +#define OSTM0TS_TS (uint8_t)(0x01U) /* b0:1: Start */ +#define OSTM0TT_TT (uint8_t)(0x01U) /* b0:1: Stop */ +#define OSTM0TE_TE (uint8_t)(0x01U) /* b0:1: Counter enabled */ +#define OSTM0CMP_MICRO_VALUE (0x00000190U) /* PCLK=400MHz(400=0x190 = 1us) */ + +#define OSTM0CTL_MD10 (uint8_t)(0x02U) /* b1:1: Free-run compare mode(Start:0 Counting Direction:up) */ + /* b0:0: Interrupts when counting starts are enabled */ + +#define MAX_MICRO_WAIT (10737418U) /* 0xFFFFFFFF / 400 */ + +void micro_wait(uint32_t count_us) +{ + uint32_t val; + uint16_t reg; + + if (count_us != 0U) + { + /* When the timer count is an argument that exceeds 0xFFFFFFFF */ + if(MAX_MICRO_WAIT < count_us) + { + count_us = MAX_MICRO_WAIT; + } + val = count_us * OSTM0CMP_MICRO_VALUE; + /* timer start */ + mem_write8(OSTM0TT, OSTM0TT_TT); + mem_write32(OSTM0CMP, val); + mem_write8(OSTM0CTL, OSTM0CTL_MD10); + mem_write8(OSTM0TS, OSTM0TS_TS); + + while (1) + { + reg = mem_read16(INTICUOSTM0); + if ((reg & (INTCR_RF)) != INTCR_RF_NO_REQ) + { + /* timer stop */ + reg = (reg & (uint16_t)(~(INTCR_RF))); + mem_write16(INTICUOSTM0, reg); + mem_write8(OSTM0TT, OSTM0TT_TT); + break; + } + } + } +} +/* End of function micro_wait(uint32_t count_us) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/image_load/image_load.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/image_load/image_load.c new file mode 100644 index 0000000..d3ae31d --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/image_load/image_load.c @@ -0,0 +1,355 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file image_load.c + * - Version : 0.01 + * @brief Access protection setting driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +/* indelude */ +#include +#include +#include +#include +#include +#include +#include +#include + + +#define KEY_SIZE_FLG_MSK (0x00000003U) +#define KEY_SIZE_BIT_SHIFT (21U) +#define CERT_INFO_FLG_OFFSET (0x0000000CU) +#define KEY_SIZE_3072 (0x00000001U) +#define KEY_SIZE_2048 (0x00000000U) +#define NUM_OF_ALWAYS_LOAD_IMAGE (2U) +#define WORD_TO_BYTE (4U) +#define ERROR_PARAM (0U) +#define NOT_OVERLAP_FLAG (0U) +#define OVERLAP_FLAG (1U) + + +static void check_load_area(uint32_t dst, uint32_t src, uint32_t len); +static void get_info_from_cert(uint32_t cert_addr, uint32_t *size, + uintptr_t *dest_addr); + +void load_key_cert(void) +{ + uint32_t phys_dst; + + phys_dst = remap_get_phys_addr(KEY_CERT_DEST_ADDR); + /* Load key cert */ + load_start(phys_dst, RTSRAM_BASE + KEY_CERT_SRC_OFFSET, KEY_CERT_SIZE); + + NOTICE( + "======== key cert info ========\n" + "destination address:0x%08x\n" + "physical destination address:0x%08x\n" + "source address:0x%08x\n" + "size:0x%08x\n", KEY_CERT_DEST_ADDR, phys_dst, + RTSRAM_BASE + KEY_CERT_SRC_OFFSET, KEY_CERT_SIZE); + + + /* End loading key cert */ + load_end(); +} +/* End of function load_key_cert(void) */ + +uint32_t load_content_cert(void) +{ + uint32_t load_num; + uint32_t phys_dst; + uint32_t loop; + + /* Get physical address of transfer destination. */ + phys_dst = remap_get_phys_addr(CONTENT_CERT_DEST_ADDR); + /* Load content cert header */ + load_start(phys_dst, FLASH_CONTENT_CERT_ADDR, CONTENT_CERT_INFO_SIZE); + + NOTICE( + "======== content cert info ========\n" + "destination address:0x%08x\n" + "physical destination address:0x%08x\n" + "source address:0x%08x\n" + "size:0x%08x\n", CONTENT_CERT_DEST_ADDR, phys_dst, + FLASH_CONTENT_CERT_ADDR, CONTENT_CERT_INFO_SIZE); + + + /* End loading cert header */ + load_end(); + + load_num = mem_read32(CONTENT_CERT_DEST_ADDR); + + + /* Check number of image load. + In case of number of image load is 0, error of transfer parameter. + In case of number of image loads is higher than 8, + the transfer parameter error. */ + if ((load_num == 0U) || (load_num > CA53_MAX_IMAGE)) { + ERROR("Content cert info 'load image num' fault.\n"); + ERROR("load image num = %d\n",load_num); + panic; + } + + /* Load content cert of all images. */ + for(loop = 0; loop < (NUM_OF_ALWAYS_LOAD_IMAGE + load_num); loop++) + { + load_start((phys_dst + CONTENT_CERT_DST_OFFSET(loop)), + (FLASH_CONTENT_CERT_ADDR + CONTENT_CERT_SRC_OFFSET(loop)), + CONTENT_CERT_DST_SIZE); + + /* End loading content cert */ + load_end(); + } + + NOTICE( + "======== content cert ========\n" + "address:0x%08x size:0x%08x\n", + (CONTENT_CERT_DEST_ADDR + CONTENT_CERT_INFO_SIZE), + (CONTENT_CERT_DST_SIZE * (NUM_OF_ALWAYS_LOAD_IMAGE + load_num))); + + return load_num; +} +/* End of function load_content_cert(void) */ + +uint32_t load_image(uint32_t cert_addr, uint32_t flash_src_offset, + const char *name) +{ + uint32_t load_addr; + uint32_t flash_image_addr; + uint32_t size; + + /* Get transfer parameter of image from a content certificate. */ + flash_image_addr = (FLASH_BASE + mem_read32(flash_src_offset)); + get_info_from_cert(cert_addr, &size, &load_addr); + + NOTICE("======== %s image load info ========\n" + "load address \t= 0x%08x\n" "image size \t= 0x%08x\n" + "source address \t= 0x%08x\n", + name, load_addr, size, flash_image_addr); + + /* Check transfer range of image. */ + check_load_area(load_addr, flash_image_addr, size); + + /* Image load start. */ + load_start(load_addr, flash_image_addr, size); + + return load_addr; +} +/* End of function load_image(uint32_t cert_addr, uint32_t flash_src_offset, const char *name) */ + +static void check_load_area(uint32_t dst, uint32_t src, uint32_t len) +{ + uint32_t src_end; + uint32_t dst_end; + uint32_t overlap; + uint32_t loop; + static uint32_t s_num = 0U; + + /* The memory range of destination. */ + const ADDRESS_RANGE add_list[] = { + [TARGET_MEM_DRAM] = {DRAM_BASE, DRAM_END}, + [TARGET_MEM_RTSRAM] = {RTSRAM_BASE, RTSRAM_END} + }; + + static ADDRESS_RANGE s_placed_image[MAX_PLACED] = { + [0] = {IPL_TOP, IPL_END}, /* Overwrite after RTOS range check. */ + [1] = {0U,0U}, + [2] = {0U,0U}, + [3] = {0U,0U}, + [4] = {0U,0U}, + [5] = {0U,0U}, + [6] = {0U,0U}, + [7] = {0U,0U}, + [8] = {0U,0U}, + [9] = {0U,0U} + }; + + /* Check image size */ + if (len == 0U) + { + ERROR("image size error\n"); + panic; + } + + /* Check whether source is overflow */ + if (src > (UINT32_MAX - len)) + { + ERROR("1:overflow is occurred at source\n"); + ERROR("1:source address = 0x%x image size = 0x%x\n", src, len); + panic; + } else { + src_end = src + len - 1U; + } + if (src_end < src) + { + ERROR("2:overflow is occurred at source\n"); + ERROR("2:source address = 0x%x image size = 0x%x\n", src, len); + panic; + } + + /* Check whether destination is overflow */ + if (dst > (UINT32_MAX - len)) + { + ERROR("1:overflow is occurred at destination\n"); + ERROR("1:destination address = 0x%x image size = 0x%x\n", dst, + len); + panic; + } + else + { + dst_end = dst + len - 1U; + } + if (dst_end < dst) + { + ERROR("2:overflow is occurred at destination\n"); + ERROR("2:destination address = 0x%x image size = 0x%x\n", dst, + len); + panic; + } + + /* Check source address range. */ + if ((src < FLASH_BASE) || (FLASH_END < src_end)) + { + ERROR("check load area (source address)\n"); + ERROR("source address = 0x%x image size = 0x%x\n", src, len); + panic; + } + + /* Check destination address range. */ + if ((add_list[1].topadd <= dst) + && (dst_end <= add_list[1].endadd)) + { + /* check RT-SRAM */ + } + else if ((add_list[0].topadd <= dst) + && (dst_end <= add_list[0].endadd)) + { + /* check SDRAM */ + } + else + { + ERROR("check_load_area (destination address)\n"); + ERROR("destination address = 0x%x image size = 0x%x\n", dst, + len); + panic; + } + + /* Check there are no overlaps the image that will be loaded and + the images that have already loaded. */ + overlap = NOT_OVERLAP_FLAG; + loop = 0U; + do + { + /* check overlap */ + if ((dst >= s_placed_image[loop].topadd) + && (dst <= s_placed_image[loop].endadd)) + { + overlap = OVERLAP_FLAG; + } + else if ((dst_end >= s_placed_image[loop].topadd) + && (dst_end <= s_placed_image[loop].endadd)) + { + overlap = OVERLAP_FLAG; + } + else if ((dst < s_placed_image[loop].topadd) + && (s_placed_image[loop].endadd < dst_end)) + { + overlap = OVERLAP_FLAG; + } + else + { + loop++; + } + } while ((loop < s_num) && (overlap == NOT_OVERLAP_FLAG)); + + /* Check the overlap flag. + Parameter error if overwrite occurred. + Otherwise, add parameters of the image to be loaded into + Placed_image. */ + if (overlap == NOT_OVERLAP_FLAG) { + s_placed_image[s_num].topadd = dst; + s_placed_image[s_num].endadd = dst_end; + INFO("[0x%x] topadd = 0x%x endadd = 0x%x\n", s_num, + placed_image[s_num].topadd, placed_image[s_num].endadd); + s_num++; + } else { + ERROR("check_load_area (overlap)\n"); + ERROR("destination address = 0x%x image size = 0x%x\n", dst, + len); + ERROR("overlapped image is [%x]\n", loop); + ERROR("top address = 0x%x end address = 0x%x\n", + s_placed_image[loop].topadd, s_placed_image[loop].endadd); + panic; + } +} +/* End of function check_load_area(uint32_t dst, uint32_t src, uint32_t len) */ + +static void get_info_from_cert(uint32_t cert_addr, uint32_t *size, + uintptr_t *dest_addr) +{ + uint32_t val; + uint32_t certInfo1; + uintptr_t pSize; + uintptr_t pDestL; + + /* Get key length of content certificate. */ + val = mem_read32((uintptr_t)cert_addr + CERT_INFO_FLG_OFFSET); + certInfo1 = (val >> KEY_SIZE_BIT_SHIFT) & KEY_SIZE_FLG_MSK; + + /* Get the transfer address and transfer size from + the certificate in accordance with the key length. */ + if (KEY_SIZE_3072 == certInfo1) { /* key size = 3072 */ + pSize = cert_addr + CERT_INFO_SIZE_OFFSET1; + *size = mem_read32(pSize) * WORD_TO_BYTE; + pDestL = cert_addr + CERT_INFO_DST_OFFSET1; + *dest_addr = (uintptr_t)mem_read32(pDestL); + } + else if (KEY_SIZE_2048 == certInfo1) /* key size = 2048 */ + { + pSize = cert_addr + CERT_INFO_SIZE_OFFSET; + *size = mem_read32(pSize) * WORD_TO_BYTE; + pDestL = cert_addr + CERT_INFO_DST_OFFSET; + *dest_addr = (uintptr_t)mem_read32(pDestL); + } + else + { + *size = ERROR_PARAM; + *dest_addr = ERROR_PARAM; + } +} +/* End of function get_info_from_cert(uint32_t cert_addr, uint32_t *size, uintptr_t *dest_addr) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/acc_prot.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/acc_prot.h new file mode 100644 index 0000000..5506d30 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/acc_prot.h @@ -0,0 +1,39 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Access Protection header + ******************************************************************************/ +#ifndef ACC_PROT_H_ +#define ACC_PROT_H_ + + +/* Prototype */ +void acc_prot_init(void); + +#endif /* ACC_PROT_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/acc_prot_lifec.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/acc_prot_lifec.h new file mode 100644 index 0000000..bddb7b5 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/acc_prot_lifec.h @@ -0,0 +1,57 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : LifeC Access Protection header + ******************************************************************************/ + +#ifndef ACC_PROT_LIFEC_H__ +#define ACC_PROT_LIFEC_H__ + +#include + +typedef struct { + uintptr_t address; + uint32_t value; +} LIFEC_SETTING_TABLE; + +void acc_prot_lifec(void); + +#define LIFEC_GROUP3 (3U) +#define LIFEC_GROUP2 (2U) +#define LIFEC_GROUP1 (1U) +#define LIFEC_GROUP0 (0U) +#define LIFEC_PUBLIC (0U) + +#define LIFEC_REG_TGT(RegNo, Bits) (((uint32_t)(RegNo) << 16U) | (uint32_t)(Bits)) + +#define LIFEC_TGT_M_ICUMX LIFEC_REG_TGT(3U, 13U) + +void lifec_set_master_grp(uint32_t target, uint32_t sec_grp, uint32_t safe_grp); + +#endif /* ACC_PROT_LIFEC_H__ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/acc_prot_memory.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/acc_prot_memory.h new file mode 100644 index 0000000..52992bd --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/acc_prot_memory.h @@ -0,0 +1,131 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Memory Access Protection header + ******************************************************************************/ +#ifndef ACC_PROT_MEMORY_H_ +#define ACC_PROT_MEMORY_H_ + +#include +#include + +#define SECDIVnD_BASE (0xFFE90000U) +#define SECDIVnD(base, a) ((uint32_t)(base) + (0x0004U * (uint32_t)(a))) +#define SECCTRnD(base, a) ((uint32_t)(base) + (0x0004U * (uint32_t)(a)) + 0x0040U) + +#define SPTDIVCRn_BASE (BASE_AXI_ADDR + 0x0500U)/* 0xE6784500U */ +#define SPTDIVCR(a) ((SPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a))) +#define SPTCR(a) ((SPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a)) + 0x40U) + +#define DPTDIVCRn_BASE (BASE_AXI_ADDR + 0x0400U)/* 0xE6784400U */ +#define DPTDIVCR(a) ((DPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a))) +#define DPTCR(a) ((DPTDIVCRn_BASE) + (0x0004U * (uint32_t)(a)) + 0x40U) + +#define PROT_GRP0_R_ (uint8_t)(1U << 7U) +#define PROT_GRP0__W (uint8_t)(1U << 3U) +#define PROT_GRP0_RW (PROT_GRP0_R | PROT_GRP0_W) +#define PROT_GRP1_R_ (uint8_t)(1U << 6U) +#define PROT_GRP1__W (uint8_t)(1U << 2U) +#define PROT_GRP1_RW (PROT_GRP1_R | PROT_GRP1_W) +#define PROT_GRP2_R_ (uint8_t)(1U << 5U) +#define PROT_GRP2__W (uint8_t)(1U << 1U) +#define PROT_GRP2_RW (PROT_GRP2_R | PROT_GRP2_W) +#define PROT_GRP3_R_ (uint8_t)(1U << 4U) +#define PROT_GRP3__W (uint8_t)(1U << 0U) +#define PROT_GRP3_RW (PROT_GRP3_R | PROT_GRP3_W) + +#define PROT_GRP_ALL (PROT_GRP0__W | PROT_GRP1__W | PROT_GRP2__W | PROT_GRP3__W) +/* 3210 */ +#define R_NNNN (PROT_GRP3_R_ | PROT_GRP2_R_ | PROT_GRP1_R_ | PROT_GRP0_R_) +#define R_NNNY (PROT_GRP3_R_ | PROT_GRP2_R_ | PROT_GRP1_R_ ) +#define R_NNYN (PROT_GRP3_R_ | PROT_GRP2_R_ | PROT_GRP0_R_) +#define R_NNYY (PROT_GRP3_R_ | PROT_GRP2_R_ ) +#define R_NYNN (PROT_GRP3_R_ | PROT_GRP1_R_ | PROT_GRP0_R_) +#define R_NYNY (PROT_GRP3_R_ | PROT_GRP1_R_ ) +#define R_NYYN (PROT_GRP3_R_ | PROT_GRP0_R_) +#define R_NYYY (PROT_GRP3_R_ ) +#define R_YNNN ( PROT_GRP2_R_ | PROT_GRP1_R_ | PROT_GRP0_R_) +#define R_YNNY ( PROT_GRP2_R_ | PROT_GRP1_R_ | ) +#define R_YNYN ( PROT_GRP2_R_ | PROT_GRP0_R_) +#define R_YNYY ( PROT_GRP2_R_ ) +#define R_YYNN ( PROT_GRP1_R_ | PROT_GRP0_R_) +#define R_YYNY ( PROT_GRP1_R_ ) +#define R_YYYN ( PROT_GRP0_R_) +#define R_YYYY ( 0U ) +/* 3210 */ +#define W_NNNN (PROT_GRP3__W | PROT_GRP2__W | PROT_GRP1__W | PROT_GRP0__W) +#define W_NNNY (PROT_GRP3__W | PROT_GRP2__W | PROT_GRP1__W ) +#define W_NNYN (PROT_GRP3__W | PROT_GRP2__W | PROT_GRP0__W) +#define W_NNYY (PROT_GRP3__W | PROT_GRP2__W ) +#define W_NYNN (PROT_GRP3__W | PROT_GRP1__W | PROT_GRP0__W) +#define W_NYNY (PROT_GRP3__W | PROT_GRP1__W ) +#define W_NYYN (PROT_GRP3__W | PROT_GRP0__W) +#define W_NYYY (PROT_GRP3__W ) +#define W_YNNN ( PROT_GRP2__W | PROT_GRP1__W | PROT_GRP0__W) +#define W_YNNY ( PROT_GRP2__W | PROT_GRP1__W | ) +#define W_YNYN ( PROT_GRP2__W | PROT_GRP0__W) +#define W_YNYY ( PROT_GRP2__W ) +#define W_YYNN ( PROT_GRP1__W | PROT_GRP0__W) +#define W_YYNY ( PROT_GRP1__W ) +#define W_YYYN ( PROT_GRP0__W) +#define W_YYYY ( 0U ) + +#define RT_SRAM_ADDR_END (0x000FF000U) +#define SYSTEM_RAM_ADDR_END (0xFFFFF000U) +#define DRAM_ADDR_END (0x0000002FFFFF0000ULL) + + +typedef struct { + uint8_t reg_sec; + uint8_t reg_saf; + uint8_t acc_sec; + uint8_t acc_saf; +}RAM_GROUP; + +typedef struct { + uint32_t addr_off; /* RT_SRAM_PROT[0] is must be 0x00000000 */ + RAM_GROUP prot; +}RT_SRAM_PROT; + +typedef struct { + uint32_t addr; /* SYSTEM_RAM_PROT[0] is must be 0xE6300000 */ + RAM_GROUP prot; +}SYSTEM_RAM_PROT; + + +typedef struct { + uint64_t addr; /* DRAM_PROT[0] is must be 0x00000040_00000000 */ + RAM_GROUP prot; +}DRAM_PROT; + +void acc_prot_rt_sram(void); +void acc_prot_system_ram(void); +void acc_prot_dram(void); + +#endif /* ACC_PROT_LIFEC_H__ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/axi_register.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/axi_register.h new file mode 100644 index 0000000..ff02603 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/axi_register.h @@ -0,0 +1,119 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : AXI-Bus register header + ******************************************************************************/ + +#ifndef AXI_REGISTER_H_ +#define AXI_REGISTER_H_ + +#include + +/* AXI base address */ +#define AXI_BASE (BASE_AXI_ADDR) + +/* SDRAM protection */ +#define DPTDIVCR0 (AXI_BASE + 0x4400U) /* AXI dram protected area division 0 */ +#define DPTDIVCR1 (AXI_BASE + 0x4404U) /* AXI dram protected area division 1 */ +#define DPTDIVCR2 (AXI_BASE + 0x4408U) /* AXI dram protected area division 2 */ +#define DPTDIVCR3 (AXI_BASE + 0x440CU) /* AXI dram protected area division 3 */ +#define DPTDIVCR4 (AXI_BASE + 0x4410U) /* AXI dram protected area division 4 */ +#define DPTDIVCR5 (AXI_BASE + 0x4414U) /* AXI dram protected area division 5 */ +#define DPTDIVCR6 (AXI_BASE + 0x4418U) /* AXI dram protected area division 6 */ +#define DPTDIVCR7 (AXI_BASE + 0x441CU) /* AXI dram protected area division 7 */ +#define DPTDIVCR8 (AXI_BASE + 0x4420U) /* AXI dram protected area division 8 */ +#define DPTDIVCR9 (AXI_BASE + 0x4424U) /* AXI dram protected area division 9 */ +#define DPTDIVCR10 (AXI_BASE + 0x4428U) /* AXI dram protected area division 10 */ +#define DPTDIVCR11 (AXI_BASE + 0x442CU) /* AXI dram protected area division 11 */ +#define DPTDIVCR12 (AXI_BASE + 0x4430U) /* AXI dram protected area division 12 */ +#define DPTDIVCR13 (AXI_BASE + 0x4434U) /* AXI dram protected area division 13 */ +#define DPTDIVCR14 (AXI_BASE + 0x4438U) /* AXI dram protected area division 14 */ + +#define DPTCR0 (AXI_BASE + 0x4440U) /* AXI dram protected area setting 0 */ +#define DPTCR1 (AXI_BASE + 0x4444U) /* AXI dram protected area setting 1 */ +#define DPTCR2 (AXI_BASE + 0x4448U) /* AXI dram protected area setting 2 */ +#define DPTCR3 (AXI_BASE + 0x444CU) /* AXI dram protected area setting 3 */ +#define DPTCR4 (AXI_BASE + 0x4450U) /* AXI dram protected area setting 4 */ +#define DPTCR5 (AXI_BASE + 0x4454U) /* AXI dram protected area setting 5 */ +#define DPTCR6 (AXI_BASE + 0x4458U) /* AXI dram protected area setting 6 */ +#define DPTCR7 (AXI_BASE + 0x445CU) /* AXI dram protected area setting 7 */ +#define DPTCR8 (AXI_BASE + 0x4460U) /* AXI dram protected area setting 8 */ +#define DPTCR9 (AXI_BASE + 0x4464U) /* AXI dram protected area setting 9 */ +#define DPTCR10 (AXI_BASE + 0x4468U) /* AXI dram protected area setting 10 */ +#define DPTCR11 (AXI_BASE + 0x446CU) /* AXI dram protected area setting 11 */ +#define DPTCR12 (AXI_BASE + 0x4470U) /* AXI dram protected area setting 12 */ +#define DPTCR13 (AXI_BASE + 0x4474U) /* AXI dram protected area setting 13 */ +#define DPTCR14 (AXI_BASE + 0x4478U) /* AXI dram protected area setting 14 */ +#define DPTCR15 (AXI_BASE + 0x447CU) /* AXI dram protected area setting 15 */ + +/* System RAM protection */ +#define SPTDIVCR0 (AXI_BASE + 0x4500U) /* AXI system ram protected area division 0 */ +#define SPTDIVCR1 (AXI_BASE + 0x4504U) /* AXI system ram protected area division 1 */ +#define SPTDIVCR2 (AXI_BASE + 0x4508U) /* AXI system ram protected area division 2 */ +#define SPTDIVCR3 (AXI_BASE + 0x450CU) /* AXI system ram protected area division 3 */ +#define SPTDIVCR4 (AXI_BASE + 0x4510U) /* AXI system ram protected area division 4 */ +#define SPTDIVCR5 (AXI_BASE + 0x4514U) /* AXI system ram protected area division 5 */ +#define SPTDIVCR6 (AXI_BASE + 0x4518U) /* AXI system ram protected area division 6 */ +#define SPTDIVCR7 (AXI_BASE + 0x451CU) /* AXI system ram protected area division 7 */ +#define SPTDIVCR8 (AXI_BASE + 0x4520U) /* AXI system ram protected area division 8 */ +#define SPTDIVCR9 (AXI_BASE + 0x4524U) /* AXI system ram protected area division 9 */ +#define SPTDIVCR10 (AXI_BASE + 0x4528U) /* AXI system ram protected area division 10 */ +#define SPTDIVCR11 (AXI_BASE + 0x452CU) /* AXI system ram protected area division 11 */ +#define SPTDIVCR12 (AXI_BASE + 0x4530U) /* AXI system ram protected area division 12 */ +#define SPTDIVCR13 (AXI_BASE + 0x4534U) /* AXI system ram protected area division 13 */ +#define SPTDIVCR14 (AXI_BASE + 0x4538U) /* AXI system ram protected area division 14 */ + +#define SPTCR0 (AXI_BASE + 0x4540U) /* AXI system ram protected area setting 0 */ +#define SPTCR1 (AXI_BASE + 0x4544U) /* AXI system ram protected area setting 1 */ +#define SPTCR2 (AXI_BASE + 0x4548U) /* AXI system ram protected area setting 2 */ +#define SPTCR3 (AXI_BASE + 0x454CU) /* AXI system ram protected area setting 3 */ +#define SPTCR4 (AXI_BASE + 0x4550U) /* AXI system ram protected area setting 4 */ +#define SPTCR5 (AXI_BASE + 0x4554U) /* AXI system ram protected area setting 5 */ +#define SPTCR6 (AXI_BASE + 0x4558U) /* AXI system ram protected area setting 6 */ +#define SPTCR7 (AXI_BASE + 0x455CU) /* AXI system ram protected area setting 7 */ +#define SPTCR8 (AXI_BASE + 0x4560U) /* AXI system ram protected area setting 8 */ +#define SPTCR9 (AXI_BASE + 0x4564U) /* AXI system ram protected area setting 9 */ +#define SPTCR10 (AXI_BASE + 0x4568U) /* AXI system ram protected area setting 10 */ +#define SPTCR11 (AXI_BASE + 0x456CU) /* AXI system ram protected area setting 11 */ +#define SPTCR12 (AXI_BASE + 0x4570U) /* AXI system ram protected area setting 12 */ +#define SPTCR13 (AXI_BASE + 0x4574U) /* AXI system ram protected area setting 13 */ +#define SPTCR14 (AXI_BASE + 0x4578U) /* AXI system ram protected area setting 14 */ +#define SPTCR15 (AXI_BASE + 0x457CU) /* AXI system ram protected area setting 15 */ + +#define EDCINTEN0 (0xFF840040U) /* EDC Interrupt Enable Register 0 */ +#define EDCINTEN1 (0xFF840044U) /* EDC Interrupt Enable Register 1 */ +#define EDCINTEN2 (0xFF840048U) /* EDC Interrupt Enable Register 2 */ +#define EDCINTEN3 (0xFF84004CU) /* EDC Interrupt Enable Register 3 */ +#define EDCINTEN5 (0xFF8401C0U) /* EDC Interrupt Enable Register 5 */ +#define EDCINTEN6 (0xFF8401C4U) /* EDC Interrupt Enable Register 6 */ +#define EDCINTEN7 (0xFF8401C8U) /* EDC Interrupt Enable Register 8 */ + +#define EDC_CFG (0xFFE90110U) /* EDC Error control Register(RT-SRAM) V3H_2 */ + +#endif /* AXI_REGISTER_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/cpg.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/cpg.h new file mode 100644 index 0000000..1a310dc --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/cpg.h @@ -0,0 +1,42 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : CPG driver header + ******************************************************************************/ +#ifndef CPG_H_ +#define CPG_H_ + +#include + +/* Prototype */ +void cpg_init(void); +void cpg_release(void); +void cpg_reg_write(uintptr_t mstpcr, uintptr_t mstpsr, uint32_t data); + +#endif /* CPG_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/cpg_register.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/cpg_register.h new file mode 100644 index 0000000..62103b0 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/cpg_register.h @@ -0,0 +1,125 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : CPG register header + ******************************************************************************/ + +#ifndef CPG_REGISTER_H__ +#define CPG_REGISTER_H__ + +#include + +/* CPG base address */ +/* 0xE6150000 */ +#define CPG_BASE (BASE_CPG_ADDR) + +/* CPG write protect */ +#define CPG_CPGWPR (CPG_BASE + 0x0900U) +/* CPG write protect control */ +#define CPG_CPGWPCR (CPG_BASE + 0x0904U) + +#define CPG_MSTPSR0 (CPG_BASE + 0x0030U) /* Module stop status register 0 */ +#define CPG_MSTPSR1 (CPG_BASE + 0x0038U) /* Module stop status register 1 */ +#define CPG_MSTPSR2 (CPG_BASE + 0x0040U) /* Module stop status register 2 */ +#define CPG_MSTPSR3 (CPG_BASE + 0x0048U) /* Module stop status register 3 */ +#define CPG_MSTPSR4 (CPG_BASE + 0x004CU) /* Module stop status register 4 */ +#define CPG_MSTPSR5 (CPG_BASE + 0x003CU) /* Module stop status register 5 */ +#define CPG_MSTPSR6 (CPG_BASE + 0x01C0U) /* Module stop status register 6 */ +#define CPG_MSTPSR7 (CPG_BASE + 0x01C4U) /* Module stop status register 7 */ +#define CPG_MSTPSR8 (CPG_BASE + 0x09A0U) /* Module stop status register 8 */ +#define CPG_MSTPSR9 (CPG_BASE + 0x09A4U) /* Module stop status register 9 */ +#define CPG_MSTPSR10 (CPG_BASE + 0x09A8U) /* Module stop status register 10 */ +#define CPG_MSTPSR11 (CPG_BASE + 0x09ACU) /* Module stop status register 11 */ + +/* CPG (Realtime) registers */ +#define CPG_RMSTPCR0 (CPG_BASE + 0x0110U) /* Realtime Module Stop Control Register 0 */ +#define CPG_RMSTPCR1 (CPG_BASE + 0x0114U) /* Realtime Module Stop Control Register 1 */ +#define CPG_RMSTPCR2 (CPG_BASE + 0x0118U) /* Realtime Module Stop Control Register 2 */ +#define CPG_RMSTPCR3 (CPG_BASE + 0x011CU) /* Realtime Module Stop Control Register 3 */ +#define CPG_RMSTPCR4 (CPG_BASE + 0x0120U) /* Realtime Module Stop Control Register 4 */ +#define CPG_RMSTPCR5 (CPG_BASE + 0x0124U) /* Realtime Module Stop Control Register 5 */ +#define CPG_RMSTPCR6 (CPG_BASE + 0x0128U) /* Realtime Module Stop Control Register 6 */ +#define CPG_RMSTPCR7 (CPG_BASE + 0x012CU) /* Realtime Module Stop Control Register 7 */ +#define CPG_RMSTPCR8 (CPG_BASE + 0x0980U) /* Realtime Module Stop Control Register 8 */ +#define CPG_RMSTPCR9 (CPG_BASE + 0x0984U) /* Realtime Module Stop Control Register 9 */ +#define CPG_RMSTPCR10 (CPG_BASE + 0x0988U) /* Realtime Module Stop Control Register 10 */ +#define CPG_RMSTPCR11 (CPG_BASE + 0x098CU) /* Realtime Module Stop Control Register 11 */ + +/* CPG (System) registers */ +#define CPG_SMSTPCR0 (CPG_BASE + 0x0130U) /* System Module Stop Control Register 0 */ +#define CPG_SMSTPCR1 (CPG_BASE + 0x0134U) /* System Module Stop Control Register 1 */ +#define CPG_SMSTPCR2 (CPG_BASE + 0x0138U) /* System Module Stop Control Register 2 */ +#define CPG_SMSTPCR3 (CPG_BASE + 0x013CU) /* System Module Stop Control Register 3 */ +#define CPG_SMSTPCR4 (CPG_BASE + 0x0140U) /* System Module Stop Control Register 4 */ +#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U) /* System Module Stop Control Register 5 */ +#define CPG_SMSTPCR6 (CPG_BASE + 0x0148U) /* System Module Stop Control Register 6 */ +#define CPG_SMSTPCR7 (CPG_BASE + 0x014CU) /* System Module Stop Control Register 7 */ +#define CPG_SMSTPCR8 (CPG_BASE + 0x0990U) /* System Module Stop Control Register 8 */ +#define CPG_SMSTPCR9 (CPG_BASE + 0x0994U) /* System Module Stop Control Register 9 */ +#define CPG_SMSTPCR10 (CPG_BASE + 0x0998U) /* System Module Stop Control Register 10 */ +#define CPG_SMSTPCR11 (CPG_BASE + 0x099CU) /* System Module Stop Control Register 11 */ + +/* CPG (SECURITY) registers */ +#define CPG_SCMSTPCR0 (CPG_BASE + 0x0B20U) /* Secure Module Stop Control Register 0 */ +#define CPG_SCMSTPCR1 (CPG_BASE + 0x0B24U) /* Secure Module Stop Control Register 1 */ +#define CPG_SCMSTPCR2 (CPG_BASE + 0x0B28U) /* Secure Module Stop Control Register 2 */ +#define CPG_SCMSTPCR3 (CPG_BASE + 0x0B2CU) /* Secure Module Stop Control Register 3 */ +#define CPG_SCMSTPCR4 (CPG_BASE + 0x0B30U) /* Secure Module Stop Control Register 4 */ +#define CPG_SCMSTPCR5 (CPG_BASE + 0x0B34U) /* Secure Module Stop Control Register 5 */ +#define CPG_SCMSTPCR6 (CPG_BASE + 0x0B38U) /* Secure Module Stop Control Register 6 */ +#define CPG_SCMSTPCR7 (CPG_BASE + 0x0B3CU) /* Secure Module Stop Control Register 7 */ +#define CPG_SCMSTPCR8 (CPG_BASE + 0x0B40U) /* Secure Module Stop Control Register 8 */ +#define CPG_SCMSTPCR9 (CPG_BASE + 0x0B44U) /* Secure Module Stop Control Register 9 */ +#define CPG_SCMSTPCR10 (CPG_BASE + 0x0B48U) /* Secure Module Stop Control Register 10 */ +#define CPG_SCMSTPCR11 (CPG_BASE + 0x0B4CU) /* Secure Module Stop Control Register 11 */ + +/* CPG (SAFETY) registers */ +#define CPG_SAMSTPCR0 (CPG_BASE + 0x0C20U) /* Safety Module Stop Control Register 0 */ +#define CPG_SAMSTPCR1 (CPG_BASE + 0x0C24U) /* Safety Module Stop Control Register 1 */ +#define CPG_SAMSTPCR2 (CPG_BASE + 0x0C28U) /* Safety Module Stop Control Register 2 */ +#define CPG_SAMSTPCR3 (CPG_BASE + 0x0C2CU) /* Safety Module Stop Control Register 3 */ +#define CPG_SAMSTPCR4 (CPG_BASE + 0x0C30U) /* Safety Module Stop Control Register 4 */ +#define CPG_SAMSTPCR5 (CPG_BASE + 0x0C34U) /* Safety Module Stop Control Register 5 */ +#define CPG_SAMSTPCR6 (CPG_BASE + 0x0C38U) /* Safety Module Stop Control Register 6 */ +#define CPG_SAMSTPCR7 (CPG_BASE + 0x0C3CU) /* Safety Module Stop Control Register 7 */ +#define CPG_SAMSTPCR8 (CPG_BASE + 0x0C40U) /* Safety Module Stop Control Register 8 */ +#define CPG_SAMSTPCR9 (CPG_BASE + 0x0C44U) /* Safety Module Stop Control Register 9 */ +#define CPG_SAMSTPCR10 (CPG_BASE + 0x0C48U) /* Safety Module Stop Control Register 10 */ +#define CPG_SAMSTPCR11 (CPG_BASE + 0x0C4CU) /* Safety Module Stop Control Register 11 */ + +#define CPG_SRSTCLR2 (CPG_BASE + 0x0948U) /* Software Reset Clearing Register 2 */ + +/* APMU */ +#define APMU_CA53WUPCR (CPG_BASE + 0x1010U) /* Wake-up control register for A53 */ +#define APMU_CR7PSTR (CPG_BASE + 0x3040U) /* Wake-up control register for A53 */ + +/* IMP core */ +#define ASTPOFFR (CPG_BASE + 0x0278U) /* Automatic Module clock stop function off register */ + +#endif /* CPG_REGISTER_H__ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/cpu_on.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/cpu_on.h new file mode 100644 index 0000000..1bdc889 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/cpu_on.h @@ -0,0 +1,45 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Power management driver header + ******************************************************************************/ + +#ifndef CPU_ON_H__ +#define CPU_ON_H__ + +#define RCAR_PWR_TARGET_CR7 (0U) +#define RCAR_PWR_TARGET_CA53 (1U) + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void arm_cpu_set_address(uint32_t target, uint32_t boot_addr); +void arm_cpu_on(uint32_t target, uint32_t boot_addr); + +#endif /* CPU_ON_H__ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/dma.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/dma.h new file mode 100644 index 0000000..7e0e64b --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/dma.h @@ -0,0 +1,46 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : DMA driver header + ******************************************************************************/ + +#ifndef DMA_DRIVER_H__ +#define DMA_DRIVER_H__ + +#include + +#define DMACH (0U) +#define BIT21 (1U << 21U) + +void dma_init(void); +void load_start(uint32_t dst, uint32_t src, uint32_t len); +void load_end(void); +void dma_release(void); + +#endif /* DMA_DRIVER_H__ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/dma_register.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/dma_register.h new file mode 100644 index 0000000..2489e31 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/dma_register.h @@ -0,0 +1,54 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : DMA register header + ******************************************************************************/ + +#ifndef DMA_REGISTER_H_ +#define DMA_REGISTER_H_ + +#include + +#define DMACH (0U) +#define BIT21 (1U << 21U) + +/* RT-DMAC0(foe RPC) */ +#define RTDMA_BASE (BASE_RTDMA_ADDR) + +#define DMA_RDMOR (RTDMA_BASE + 0x0060U) /* DMA operation register */ +#define DMA_RDMSEC (RTDMA_BASE + 0x0030U) +#define DMA_RDMCHCLR (RTDMA_BASE + 0x0080U) /* DMA channel clear register */ + +#define DMA_RDMSAR(a) (RTDMA_BASE + 0x8000U + ((uint32_t)(a) * 0x0080U)) +#define DMA_RDMDAR(a) (RTDMA_BASE + 0x8004U + ((uint32_t)(a) * 0x0080U)) +#define DMA_RDMTCR(a) (RTDMA_BASE + 0x8008U + ((uint32_t)(a) * 0x0080U)) +#define DMA_RDMCHCR(a) (RTDMA_BASE + 0x800CU + ((uint32_t)(a) * 0x0080U)) +#define DMA_RDMRS(a) (RTDMA_BASE + 0x8040U + ((uint32_t)(a) * 0x0080U)) + +#endif /* DMA_REGISTER_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/edcinten.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/edcinten.h new file mode 100644 index 0000000..79b5221 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/edcinten.h @@ -0,0 +1,39 @@ +/******************************************************************************* + * Copyright (c) 2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : EDC's control header + ******************************************************************************/ +#ifndef EDCINTEN_H_ +#define EDCINTEN_H_ + + +/* Prototype */ +void edc_init(void); + +#endif /* EDCINTEN_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/image_load.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/image_load.h new file mode 100644 index 0000000..313b25e --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/image_load.h @@ -0,0 +1,118 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function header + ******************************************************************************/ + +#ifndef LOAD_IMAGE_H_ +#define LOAD_IMAGE_H_ + +/* define */ +/* Flash address */ +#define FLASH_BASE (0x08000000U) +#define FLASH_SIZE (0x04000000U) +#define FLASH_END ((FLASH_BASE + FLASH_SIZE) - 1U) +/* DRAM address */ +#define DRAM_BASE (0x40000000U) +#define DRAM_SIZE (0x80000000U) +#define DRAM_END ((DRAM_BASE + DRAM_SIZE) - 1U) +/* RT-SRAM */ +#define RTSRAM_BASE (0xEB200000U) +#define RTSRAM_SIZE ((1024U-18U)*1024U) +#define RTSRAM_END ((RTSRAM_BASE + RTSRAM_SIZE) - 1U) +/* ICUMXA Loader */ +#define IPL_TOP (0xEB2D8000U) +#define IPL_END (0xEB2FFFFFU) + +/* Flash address of content certificate */ +#define CONTENT_CERT_SA (6U) /* Content Cert SA6 */ +#define SA_SIZE (0x00040000U) +#define FLASH_CONTENT_CERT_ADDR (uint32_t)(FLASH_BASE + (SA_SIZE * CONTENT_CERT_SA)) /* FLASH Base + SA6 offset */ + +/* Certificate logical address */ +extern char __ghsbegin_key_load[]; +extern char __ghsbegin_cert_load[]; + +#define KEY_CERT_DEST_ADDR (uint32_t)(&__ghsbegin_key_load[0]) +#define CONTENT_CERT_DEST_ADDR (uint32_t)(&__ghsbegin_cert_load[0]) + +/* Certificate size */ +#define KEY_CERT_SRC_OFFSET (0x00000F00U) +#define KEY_CERT_SIZE (0x00000400U) /* Key cert size */ +#define CONTENT_CERT_INFO_SIZE (0x00000400U) /* CA53 program num */ +#define CONTENT_CERT_SRC_OFFSET(x) (CONTENT_CERT_INFO_SIZE + ((uint32_t)(x) * CONTENT_CERT_SEC_SIZE)) /* content cert src offsett */ +#define CONTENT_CERT_DST_OFFSET(x) (CONTENT_CERT_INFO_SIZE + ((uint32_t)(x) * CONTENT_CERT_DST_SIZE)) /* content cert dst offset */ +#define CONTENT_CERT_SEC_SIZE (0x00000800U) /* content cert src size */ +#define CONTENT_CERT_DST_SIZE (0x00000400U) /* content cert dst size */ + +/* Load ID */ +#define SECURE_FW_ID (0U) +#define RTOS_ID (1U) +#define CA53_PROGRAM_ID (2U) + +/* Number of Max loading image */ +#define CA53_MAX_IMAGE (8U) /* CA53 program MAX image num */ +#define MAX_PLACED (10U) + +/* Cert Info Source Address Offset */ +#define SRC_ADDR_OFFSET(x) (((uint32_t)(x) * 0x10U) + 0x08U) + +#define TARGET_MEM_DRAM (0U) +#define TARGET_MEM_RTSRAM (1U) + +/* get info from cert address offset */ +#define CERT_INFO_SIZE_OFFSET (0x00000264U) /* Offset Type1 */ +#define CERT_INFO_DST_OFFSET (0x00000154U) /* Offset Type1 */ +#define CERT_INFO_SIZE_OFFSET1 (0x00000364U) /* Offset Type2 */ +#define CERT_INFO_DST_OFFSET1 (0x000001D4U) /* Offset Type2 */ + + +/* struct */ +/* load address range */ +typedef struct { + uint32_t topadd; + uint32_t endadd; +} ADDRESS_RANGE; + +/* load info */ +typedef struct{ + const char *name; /* store load image name */ + uint32_t boot_addr; /* store boot address of image */ + uint32_t cert_addr; /* store content cert address */ + uint32_t src_addr; /* store source address */ +} LOAD_INFO; + + +/* Prototype */ +void load_key_cert(void); +uint32_t load_content_cert(void); +uint32_t load_image(uint32_t cert_addr, uint32_t flash_src_offset, + const char *name); +#endif /* LOAD_IMAGE_H_ */ + diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/ip_control.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/ip_control.h new file mode 100644 index 0000000..102c864 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/ip_control.h @@ -0,0 +1,40 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : IP's control header + ******************************************************************************/ +#ifndef IP_CONTROL_H_ +#define IP_CONTROL_H_ + + +/* Prototype */ +void ip_init(void); +void ip_release(void); + +#endif /* IP_CONTROL_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/lifec_register.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/lifec_register.h new file mode 100644 index 0000000..3bb2780 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/lifec_register.h @@ -0,0 +1,307 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : LifeC register header + ******************************************************************************/ + +#ifndef LIFEC_REGISTER_H__ +#define LIFEC_REGISTER_H__ + +#include +/* LIFEC0 (SECURITY) registers */ + +/* LIFEC0 (SECURITY) base address */ +#define LIFEC_SEC_BASE (BASE_LIFEC_ADDR) + +/* Security attribute setting for master ports */ +#define LIFEC_SEC_SRC (LIFEC_SEC_BASE + 0x0008U) +/* Security attribute setting for slave ports 0 */ +#define LIFEC_SEC_SEL0 (LIFEC_SEC_BASE + 0x0030U) +/* Security attribute setting for slave ports 1 */ +#define LIFEC_SEC_SEL1 (LIFEC_SEC_BASE + 0x0034U) +/* Security attribute setting for slave ports 2 */ +#define LIFEC_SEC_SEL2 (LIFEC_SEC_BASE + 0x0038U) +/* Security attribute setting for slave ports 3 */ +#define LIFEC_SEC_SEL3 (LIFEC_SEC_BASE + 0x003CU) +/* Security attribute setting for slave ports 4 */ +#define LIFEC_SEC_SEL4 (LIFEC_SEC_BASE + 0x0058U) +/* Security attribute setting for slave ports 5 */ +#define LIFEC_SEC_SEL5 (LIFEC_SEC_BASE + 0x005CU) +/* Security attribute setting for slave ports 6 */ +#define LIFEC_SEC_SEL6 (LIFEC_SEC_BASE + 0x0060U) +/* Security attribute setting for slave ports 7 */ +#define LIFEC_SEC_SEL7 (LIFEC_SEC_BASE + 0x0064U) +/* Security attribute setting for slave ports 8 */ +#define LIFEC_SEC_SEL8 (LIFEC_SEC_BASE + 0x0068U) +/* Security attribute setting for slave ports 9 */ +#define LIFEC_SEC_SEL9 (LIFEC_SEC_BASE + 0x006CU) +/* Security attribute setting for slave ports 10 */ +#define LIFEC_SEC_SEL10 (LIFEC_SEC_BASE + 0x0070U) +/* Security attribute setting for slave ports 11 */ +#define LIFEC_SEC_SEL11 (LIFEC_SEC_BASE + 0x0074U) +/* Security attribute setting for slave ports 12 */ +#define LIFEC_SEC_SEL12 (LIFEC_SEC_BASE + 0x0078U) +/* Security attribute setting for slave ports 13 */ +#define LIFEC_SEC_SEL13 (LIFEC_SEC_BASE + 0x007CU) +/* Security attribute setting for slave ports 14 */ +#define LIFEC_SEC_SEL14 (LIFEC_SEC_BASE + 0x0080U) +/* Security attribute setting for slave ports 15 */ +#define LIFEC_SEC_SEL15 (LIFEC_SEC_BASE + 0x0084U) +/* Security group 0 attribute setting for master ports 0 */ +#define LIFEC_SEC_GRP0CR0 (LIFEC_SEC_BASE + 0x0138U) +/* Security group 1 attribute setting for master ports 0 */ +#define LIFEC_SEC_GRP1CR0 (LIFEC_SEC_BASE + 0x013CU) +/* Security group 0 attribute setting for master ports 1 */ +#define LIFEC_SEC_GRP0CR1 (LIFEC_SEC_BASE + 0x0140U) +/* Security group 1 attribute setting for master ports 1 */ +#define LIFEC_SEC_GRP1CR1 (LIFEC_SEC_BASE + 0x0144U) +/* Security group 0 attribute setting for master ports 2 */ +#define LIFEC_SEC_GRP0CR2 (LIFEC_SEC_BASE + 0x0148U) +/* Security group 1 attribute setting for master ports 2 */ +#define LIFEC_SEC_GRP1CR2 (LIFEC_SEC_BASE + 0x014CU) +/* Security group 0 attribute setting for master ports 3 */ +#define LIFEC_SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U) +/* Security group 1 attribute setting for master ports 3 */ +#define LIFEC_SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U) +/* Security group 0 attribute setting for slave ports 0 */ +#define LIFEC_SEC_GRP0COND0 (LIFEC_SEC_BASE + 0x0158U) +/* Security group 1 attribute setting for slave ports 0 */ +#define LIFEC_SEC_GRP1COND0 (LIFEC_SEC_BASE + 0x015CU) +/* Security group 0 attribute setting for slave ports 1 */ +#define LIFEC_SEC_GRP0COND1 (LIFEC_SEC_BASE + 0x0160U) +/* Security group 1 attribute setting for slave ports 1 */ +#define LIFEC_SEC_GRP1COND1 (LIFEC_SEC_BASE + 0x0164U) +/* Security group 0 attribute setting for slave ports 2 */ +#define LIFEC_SEC_GRP0COND2 (LIFEC_SEC_BASE + 0x0168U) +/* Security group 1 attribute setting for slave ports 2 */ +#define LIFEC_SEC_GRP1COND2 (LIFEC_SEC_BASE + 0x016CU) +/* Security group 0 attribute setting for slave ports 3 */ +#define LIFEC_SEC_GRP0COND3 (LIFEC_SEC_BASE + 0x0170U) +/* Security group 1 attribute setting for slave ports 3 */ +#define LIFEC_SEC_GRP1COND3 (LIFEC_SEC_BASE + 0x0174U) +/* Security group 0 attribute setting for slave ports 4 */ +#define LIFEC_SEC_GRP0COND4 (LIFEC_SEC_BASE + 0x0178U) +/* Security group 1 attribute setting for slave ports 4 */ +#define LIFEC_SEC_GRP1COND4 (LIFEC_SEC_BASE + 0x017CU) +/* Security group 0 attribute setting for slave ports 5 */ +#define LIFEC_SEC_GRP0COND5 (LIFEC_SEC_BASE + 0x0180U) +/* Security group 1 attribute setting for slave ports 5 */ +#define LIFEC_SEC_GRP1COND5 (LIFEC_SEC_BASE + 0x0184U) +/* Security group 0 attribute setting for slave ports 6 */ +#define LIFEC_SEC_GRP0COND6 (LIFEC_SEC_BASE + 0x0188U) +/* Security group 1 attribute setting for slave ports 6 */ +#define LIFEC_SEC_GRP1COND6 (LIFEC_SEC_BASE + 0x018CU) +/* Security group 0 attribute setting for slave ports 7 */ +#define LIFEC_SEC_GRP0COND7 (LIFEC_SEC_BASE + 0x0190U) +/* Security group 1 attribute setting for slave ports 7 */ +#define LIFEC_SEC_GRP1COND7 (LIFEC_SEC_BASE + 0x0194U) +/* Security group 0 attribute setting for slave ports 8 */ +#define LIFEC_SEC_GRP0COND8 (LIFEC_SEC_BASE + 0x0198U) +/* Security group 1 attribute setting for slave ports 8 */ +#define LIFEC_SEC_GRP1COND8 (LIFEC_SEC_BASE + 0x019CU) +/* Security group 0 attribute setting for slave ports 9 */ +#define LIFEC_SEC_GRP0COND9 (LIFEC_SEC_BASE + 0x01A0U) +/* Security group 1 attribute setting for slave ports 9 */ +#define LIFEC_SEC_GRP1COND9 (LIFEC_SEC_BASE + 0x01A4U) +/* Security group 0 attribute setting for slave ports 10 */ +#define LIFEC_SEC_GRP0COND10 (LIFEC_SEC_BASE + 0x01A8U) +/* Security group 1 attribute setting for slave ports 10 */ +#define LIFEC_SEC_GRP1COND10 (LIFEC_SEC_BASE + 0x01ACU) +/* Security group 0 attribute setting for slave ports 11 */ +#define LIFEC_SEC_GRP0COND11 (LIFEC_SEC_BASE + 0x01B0U) +/* Security group 1 attribute setting for slave ports 11 */ +#define LIFEC_SEC_GRP1COND11 (LIFEC_SEC_BASE + 0x01B4U) +/* Security group 0 attribute setting for slave ports 12 */ +#define LIFEC_SEC_GRP0COND12 (LIFEC_SEC_BASE + 0x01B8U) +/* Security group 1 attribute setting for slave ports 12 */ +#define LIFEC_SEC_GRP1COND12 (LIFEC_SEC_BASE + 0x01BCU) +/* Security group 0 attribute setting for slave ports 13 */ +#define LIFEC_SEC_GRP0COND13 (LIFEC_SEC_BASE + 0x01C0U) +/* Security group 1 attribute setting for slave ports 13 */ +#define LIFEC_SEC_GRP1COND13 (LIFEC_SEC_BASE + 0x01C4U) +/* Security group 0 attribute setting for slave ports 14 */ +#define LIFEC_SEC_GRP0COND14 (LIFEC_SEC_BASE + 0x01C8U) +/* Security group 1 attribute setting for slave ports 14 */ +#define LIFEC_SEC_GRP1COND14 (LIFEC_SEC_BASE + 0x01CCU) +/* Security group 0 attribute setting for slave ports 15 */ +#define LIFEC_SEC_GRP0COND15 (LIFEC_SEC_BASE + 0x01D0U) +/* Security group 1 attribute setting for slave ports 15 */ +#define LIFEC_SEC_GRP1COND15 (LIFEC_SEC_BASE + 0x01D4U) +/* Security write protection attribute setting for slave ports 0 */ +#define LIFEC_SEC_READONLY0 (LIFEC_SEC_BASE + 0x01D8U) +/* Security write protection attribute setting for slave ports 1 */ +#define LIFEC_SEC_READONLY1 (LIFEC_SEC_BASE + 0x01DCU) +/* Security write protection attribute setting for slave ports 2 */ +#define LIFEC_SEC_READONLY2 (LIFEC_SEC_BASE + 0x01E0U) +/* Security write protection attribute setting for slave ports 3 */ +#define LIFEC_SEC_READONLY3 (LIFEC_SEC_BASE + 0x01E4U) +/* Security write protection attribute setting for slave ports 4 */ +#define LIFEC_SEC_READONLY4 (LIFEC_SEC_BASE + 0x01E8U) +/* Security write protection attribute setting for slave ports 5 */ +#define LIFEC_SEC_READONLY5 (LIFEC_SEC_BASE + 0x01ECU) +/* Security write protection attribute setting for slave ports 6 */ +#define LIFEC_SEC_READONLY6 (LIFEC_SEC_BASE + 0x01F0U) +/* Security write protection attribute setting for slave ports 7 */ +#define LIFEC_SEC_READONLY7 (LIFEC_SEC_BASE + 0x01F4U) +/* Security write protection attribute setting for slave ports 8 */ +#define LIFEC_SEC_READONLY8 (LIFEC_SEC_BASE + 0x01F8U) +/* Security write protection attribute setting for slave ports 9 */ +#define LIFEC_SEC_READONLY9 (LIFEC_SEC_BASE + 0x01FCU) +/* Security write protection attribute setting for slave ports 10 */ +#define LIFEC_SEC_READONLY10 (LIFEC_SEC_BASE + 0x0200U) +/* Security write protection attribute setting for slave ports 11 */ +#define LIFEC_SEC_READONLY11 (LIFEC_SEC_BASE + 0x0204U) +/* Security write protection attribute setting for slave ports 12 */ +#define LIFEC_SEC_READONLY12 (LIFEC_SEC_BASE + 0x0208U) +/* Security write protection attribute setting for slave ports 13 */ +#define LIFEC_SEC_READONLY13 (LIFEC_SEC_BASE + 0x020CU) +/* Security write protection attribute setting for slave ports 14 */ +#define LIFEC_SEC_READONLY14 (LIFEC_SEC_BASE + 0x0210U) +/* Security write protection attribute setting for slave ports 15 */ +#define LIFEC_SEC_READONLY15 (LIFEC_SEC_BASE + 0x0214U) + +/* LIFEC1 (SAFETY) registers */ + +/* LIFEC1 (SAFETY) base address */ +#define LIFEC_SAFE_BASE (LIFEC_SEC_BASE + 0x00010000U) + +/* Safety group 0 attribute setting for master ports 0 */ +#define LIFEC_SAFE_GRP0CR0 (LIFEC_SAFE_BASE + 0x0138U) +/* Safety group 1 attribute setting for master ports 0 */ +#define LIFEC_SAFE_GRP1CR0 (LIFEC_SAFE_BASE + 0x013CU) +/* Safety group 0 attribute setting for master ports 1 */ +#define LIFEC_SAFE_GRP0CR1 (LIFEC_SAFE_BASE + 0x0140U) +/* Safety group 1 attribute setting for master ports 1 */ +#define LIFEC_SAFE_GRP1CR1 (LIFEC_SAFE_BASE + 0x0144U) +/* Safety group 0 attribute setting for master ports 2 */ +#define LIFEC_SAFE_GRP0CR2 (LIFEC_SAFE_BASE + 0x0148U) +/* Safety group 1 attribute setting for master ports 2 */ +#define LIFEC_SAFE_GRP1CR2 (LIFEC_SAFE_BASE + 0x014CU) +/* Safety group 0 attribute setting for master ports 3 */ +#define LIFEC_SAFE_GRP0CR3 (LIFEC_SAFE_BASE + 0x0150U) +/* Safety group 1 attribute setting for master ports 3 */ +#define LIFEC_SAFE_GRP1CR3 (LIFEC_SAFE_BASE + 0x0154U) +/* Safety group 0 attribute setting for slave ports 0 */ +#define LIFEC_SAFE_GRP0COND0 (LIFEC_SAFE_BASE + 0x0158U) +/* Safety group 1 attribute setting for slave ports 0 */ +#define LIFEC_SAFE_GRP1COND0 (LIFEC_SAFE_BASE + 0x015CU) +/* Safety group 0 attribute setting for slave ports 1 */ +#define LIFEC_SAFE_GRP0COND1 (LIFEC_SAFE_BASE + 0x0160U) +/* Safety group 1 attribute setting for slave ports 1 */ +#define LIFEC_SAFE_GRP1COND1 (LIFEC_SAFE_BASE + 0x0164U) +/* Safety group 0 attribute setting for slave ports 2 */ +#define LIFEC_SAFE_GRP0COND2 (LIFEC_SAFE_BASE + 0x0168U) +/* Safety group 1 attribute setting for slave ports 2 */ +#define LIFEC_SAFE_GRP1COND2 (LIFEC_SAFE_BASE + 0x016CU) +/* Safety group 0 attribute setting for slave ports 3 */ +#define LIFEC_SAFE_GRP0COND3 (LIFEC_SAFE_BASE + 0x0170U) +/* Safety group 1 attribute setting for slave ports 3 */ +#define LIFEC_SAFE_GRP1COND3 (LIFEC_SAFE_BASE + 0x0174U) +/* Safety group 0 attribute setting for slave ports 4 */ +#define LIFEC_SAFE_GRP0COND4 (LIFEC_SAFE_BASE + 0x0178U) +/* Safety group 1 attribute setting for slave ports 4 */ +#define LIFEC_SAFE_GRP1COND4 (LIFEC_SAFE_BASE + 0x017CU) +/* Safety group 0 attribute setting for slave ports 5 */ +#define LIFEC_SAFE_GRP0COND5 (LIFEC_SAFE_BASE + 0x0180U) +/* Safety group 1 attribute setting for slave ports 5 */ +#define LIFEC_SAFE_GRP1COND5 (LIFEC_SAFE_BASE + 0x0184U) +/* Safety group 0 attribute setting for slave ports 6 */ +#define LIFEC_SAFE_GRP0COND6 (LIFEC_SAFE_BASE + 0x0188U) +/* Safety group 1 attribute setting for slave ports 6 */ +#define LIFEC_SAFE_GRP1COND6 (LIFEC_SAFE_BASE + 0x018CU) +/* Safety group 0 attribute setting for slave ports 7 */ +#define LIFEC_SAFE_GRP0COND7 (LIFEC_SAFE_BASE + 0x0190U) +/* Safety group 1 attribute setting for slave ports 7 */ +#define LIFEC_SAFE_GRP1COND7 (LIFEC_SAFE_BASE + 0x0194U) +/* Safety group 0 attribute setting for slave ports 8 */ +#define LIFEC_SAFE_GRP0COND8 (LIFEC_SAFE_BASE + 0x0198U) +/* Safety group 1 attribute setting for slave ports 8 */ +#define LIFEC_SAFE_GRP1COND8 (LIFEC_SAFE_BASE + 0x019CU) +/* Safety group 0 attribute setting for slave ports 9 */ +#define LIFEC_SAFE_GRP0COND9 (LIFEC_SAFE_BASE + 0x01A0U) +/* Safety group 1 attribute setting for slave ports 9 */ +#define LIFEC_SAFE_GRP1COND9 (LIFEC_SAFE_BASE + 0x01A4U) +/* Safety group 0 attribute setting for slave ports 10 */ +#define LIFEC_SAFE_GRP0COND10 (LIFEC_SAFE_BASE + 0x01A8U) +/* Safety group 1 attribute setting for slave ports 10 */ +#define LIFEC_SAFE_GRP1COND10 (LIFEC_SAFE_BASE + 0x01ACU) +/* Safety group 0 attribute setting for slave ports 11 */ +#define LIFEC_SAFE_GRP0COND11 (LIFEC_SAFE_BASE + 0x01B0U) +/* Safety group 1 attribute setting for slave ports 11 */ +#define LIFEC_SAFE_GRP1COND11 (LIFEC_SAFE_BASE + 0x01B4U) +/* Safety group 0 attribute setting for slave ports 12 */ +#define LIFEC_SAFE_GRP0COND12 (LIFEC_SAFE_BASE + 0x01B8U) +/* Safety group 1 attribute setting for slave ports 12 */ +#define LIFEC_SAFE_GRP1COND12 (LIFEC_SAFE_BASE + 0x01BCU) +/* Safety group 0 attribute setting for slave ports 13 */ +#define LIFEC_SAFE_GRP0COND13 (LIFEC_SAFE_BASE + 0x01C0U) +/* Safety group 1 attribute setting for slave ports 13 */ +#define LIFEC_SAFE_GRP1COND13 (LIFEC_SAFE_BASE + 0x01C4U) +/* Safety group 0 attribute setting for slave ports 14 */ +#define LIFEC_SAFE_GRP0COND14 (LIFEC_SAFE_BASE + 0x01C8U) +/* Safety group 1 attribute setting for slave ports 14 */ +#define LIFEC_SAFE_GRP1COND14 (LIFEC_SAFE_BASE + 0x01CCU) +/* Safety group 0 attribute setting for slave ports 15 */ +#define LIFEC_SAFE_GRP0COND15 (LIFEC_SAFE_BASE + 0x01D0U) +/* Safety group 1 attribute setting for slave ports 15 */ +#define LIFEC_SAFE_GRP1COND15 (LIFEC_SAFE_BASE + 0x01D4U) +/* Safety write protection attribute setting for slave ports 0 */ +#define LIFEC_SAFE_READONLY0 (LIFEC_SAFE_BASE + 0x01D8U) +/* Safety write protection attribute setting for slave ports 1 */ +#define LIFEC_SAFE_READONLY1 (LIFEC_SAFE_BASE + 0x01DCU) +/* Safety write protection attribute setting for slave ports 2 */ +#define LIFEC_SAFE_READONLY2 (LIFEC_SAFE_BASE + 0x01E0U) +/* Safety write protection attribute setting for slave ports 3 */ +#define LIFEC_SAFE_READONLY3 (LIFEC_SAFE_BASE + 0x01E4U) +/* Safety write protection attribute setting for slave ports 4 */ +#define LIFEC_SAFE_READONLY4 (LIFEC_SAFE_BASE + 0x01E8U) +/* Safety write protection attribute setting for slave ports 5 */ +#define LIFEC_SAFE_READONLY5 (LIFEC_SAFE_BASE + 0x01ECU) +/* Safety write protection attribute setting for slave ports 6 */ +#define LIFEC_SAFE_READONLY6 (LIFEC_SAFE_BASE + 0x01F0U) +/* Safety write protection attribute setting for slave ports 7 */ +#define LIFEC_SAFE_READONLY7 (LIFEC_SAFE_BASE + 0x01F4U) +/* Safety write protection attribute setting for slave ports 8 */ +#define LIFEC_SAFE_READONLY8 (LIFEC_SAFE_BASE + 0x01F8U) +/* Safety write protection attribute setting for slave ports 9 */ +#define LIFEC_SAFE_READONLY9 (LIFEC_SAFE_BASE + 0x01FCU) +/* Safety write protection attribute setting for slave ports 10 */ +#define LIFEC_SAFE_READONLY10 (LIFEC_SAFE_BASE + 0x0200U) +/* Safety write protection attribute setting for slave ports 11 */ +#define LIFEC_SAFE_READONLY11 (LIFEC_SAFE_BASE + 0x0204U) +/* Safety write protection attribute setting for slave ports 12 */ +#define LIFEC_SAFE_READONLY12 (LIFEC_SAFE_BASE + 0x0208U) +/* Safety write protection attribute setting for slave ports 13 */ +#define LIFEC_SAFE_READONLY13 (LIFEC_SAFE_BASE + 0x020CU) +/* Safety write protection attribute setting for slave ports 14 */ +#define LIFEC_SAFE_READONLY14 (LIFEC_SAFE_BASE + 0x0210U) +/* Safety write protection attribute setting for slave ports 15 */ +#define LIFEC_SAFE_READONLY15 (LIFEC_SAFE_BASE + 0x0214U) + +#endif /* LIFEC_REGISTER_H__ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/loader_main.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/loader_main.h new file mode 100644 index 0000000..8177ef7 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/loader_main.h @@ -0,0 +1,45 @@ +/******************************************************************************* + * Copyright (c) 2018-2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main header + ******************************************************************************/ + +#ifndef LOADER_MAIN_H_ +#define LOADER_MAIN_H_ + +/* define */ +#define IPL_VERSION "2.0.5" + +/* Global */ +extern const char build_message[]; + +/* prototype */ +uint32_t loader_main(void); + +#endif /* LOAD_MAIN_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/log.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/log.h new file mode 100644 index 0000000..3a3d9e2 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/log.h @@ -0,0 +1,85 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Log driver header + ******************************************************************************/ + +#ifndef LOG_H__ +#define LOG_H__ + +#include + +#define LOG_NONE (0) +#define LOG_ERROR (1) +#define LOG_NOTICE (2) +#define LOG_WARNING (3) +#define LOG_INFO (4) +#define LOG_VERBOSE (5) + +#if LOG_LEVEL >= LOG_VERBOSE +# define VERBOSE(...) local_printf("V:" __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + +#if LOG_LEVEL >= LOG_INFO +# define INFO(...) local_printf("I:" __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_WARNING +# define WARN(...) local_printf("W:" __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_ERROR +# define ERROR(...) local_printf("E:" __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_NOTICE +# define NOTICE(...) local_printf("N:" __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#define panic \ + do { \ + local_printf("P:%s\n", __func__); \ + while(1){} \ + } while (0) + +#define FORCE(...) local_printf(__VA_ARGS__) + +void local_printf(const char *fmt, ...); + +#endif /* LOG_H__ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/mem_io.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/mem_io.h new file mode 100644 index 0000000..b5e8838 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/mem_io.h @@ -0,0 +1,54 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Memory access driver header + ******************************************************************************/ +#ifndef MEM_IO_H_ +#define MEM_IO_H_ + +#include + +/* Prototype */ +void mem_write8(uintptr_t addr, uint8_t data); +uint8_t mem_read8(uintptr_t addr); +void mem_write16(uintptr_t addr, uint16_t data); +uint16_t mem_read16(uintptr_t addr); +void mem_write32(uintptr_t addr, uint32_t data); +uint32_t mem_read32(uintptr_t addr); +void mem_write64(uintptr_t addr, uint64_t data); +void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set); + +#if defined(__RH850G3K__) +#define mmio_write_32(a,b) mem_write32(a,b) +#define mmio_read_32(a) mem_read32(a) +#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c) +#endif + + +#endif /* MEM_IO_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/mfis.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/mfis.h new file mode 100644 index 0000000..3240716 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/mfis.h @@ -0,0 +1,49 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MFIS driver header + ******************************************************************************/ + +#ifndef MFIS_H__ +#define MFIS_H__ + +#include + +#define MFIS_PROT_CODEVALUE (0xACCE0000U) +#define MFISWPCNTR_WPD_BIT (((uint32_t)1U) << 0U) + +typedef struct { + uintptr_t address; + uint32_t value; +} MFIS_SETTING_TABLE; + + +void mfis_init(void); + +#endif /* MFIS_H__ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/mfis_register.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/mfis_register.h new file mode 100644 index 0000000..46c492e --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/mfis_register.h @@ -0,0 +1,76 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MFIS register header + ******************************************************************************/ + +#ifndef MFIS_REGISTER_H_ +#define MFIS_REGISTER_H_ + +#include + +/* MFIS */ +#define MFIS_BASE (BASE_MFIS_ADDR) + +#define MFIS_MFIERRCTLR0 (MFIS_BASE + 0x0200U) +#define MFIS_MFIERRCTLR1 (MFIS_BASE + 0x0204U) +#define MFIS_MFIERRCTLR2 (MFIS_BASE + 0x0208U) +#define MFIS_MFIERRCTLR3 (MFIS_BASE + 0x020CU) +#define MFIS_MFIERRCTLR4 (MFIS_BASE + 0x0210U) +#define MFIS_MFIERRCTLR5 (MFIS_BASE + 0x0214U) +#define MFIS_MFIERRCTLR6 (MFIS_BASE + 0x0218U) +#define MFIS_MFIERRCTLR7 (MFIS_BASE + 0x0260U) +#define MFIS_MFIERRCTLR8 (MFIS_BASE + 0x026CU) +#define MFIS_MFIERRCTLR9 (MFIS_BASE + 0x0804U) +#define MFIS_MFIERRCTLR10 (MFIS_BASE + 0x0808U) +#define MFIS_MFIERRCTLR11 (MFIS_BASE + 0x080CU) +#define MFIS_MFIERRCTLR12 (MFIS_BASE + 0x0908U) +#define MFIS_MFIERRCTLR13 (MFIS_BASE + 0x0918U) + +#define MFIS_MFIERRTGTR0 (MFIS_BASE + 0x0280U) +#define MFIS_MFIERRTGTR1 (MFIS_BASE + 0x0284U) +#define MFIS_MFIERRTGTR2 (MFIS_BASE + 0x0288U) +#define MFIS_MFIERRTGTR3 (MFIS_BASE + 0x028CU) +#define MFIS_MFIERRTGTR4 (MFIS_BASE + 0x0290U) +#define MFIS_MFIERRTGTR5 (MFIS_BASE + 0x0294U) +#define MFIS_MFIERRTGTR6 (MFIS_BASE + 0x025CU) +#define MFIS_MFIERRTGTR7 (MFIS_BASE + 0x0268U) +#define MFIS_MFIERRTGTR8 (MFIS_BASE + 0x0274U) +#define MFIS_MFIERRTGTR9 (MFIS_BASE + 0x081CU) +#define MFIS_MFIERRTGTR10 (MFIS_BASE + 0x0820U) +#define MFIS_MFIERRTGTR11 (MFIS_BASE + 0x0824U) +#define MFIS_MFIERRTGTR12 (MFIS_BASE + 0x0910U) +#define MFIS_MFIERRTGTR13 (MFIS_BASE + 0x0920U) + +#define MFIS_MFISBTSTSR (MFIS_BASE + 0x0604U) +#define MFIS_MFIEXTRQMSKCNTR (MFIS_BASE + 0x08A0U) +#define MFIS_MFISWPCNTR (MFIS_BASE + 0x0900U) +#define MFIS_MFISWACNTR (MFIS_BASE + 0x0904U) + +#endif /* MFIS_REGISTER_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/micro_wait.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/micro_wait.h new file mode 100644 index 0000000..d4a91c6 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/micro_wait.h @@ -0,0 +1,44 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Time wait driver header + ******************************************************************************/ + +#ifndef MICRO_WAIT_H_ +#define MICRO_WAIT_H_ + +#include + +/* Define */ + +/* Prototype */ +void micro_wait(uint32_t count_us); + + +#endif /* MICRO_WAIT_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/pfc.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/pfc.h new file mode 100644 index 0000000..0ccdb6f --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/pfc.h @@ -0,0 +1,41 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : PFC driver header + ******************************************************************************/ + +#ifndef PFC_H__ +#define PFC_H__ + +#include + +void pfc_init(void); +void pfc_reg_write(uintptr_t addr, uint32_t data); + +#endif /* PFC_H__ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/pfc_register.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/pfc_register.h new file mode 100644 index 0000000..42994db --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/pfc_register.h @@ -0,0 +1,207 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : PFC register header + ******************************************************************************/ + + +#ifndef PFC_REGISTER_H__ +#define PFC_REGISTER_H__ + +#include + +/* GPIO base address */ +/* 0xE6050000 */ +#define GPIO_BASE (BASE_GPIO_ADDR) + +/* GPIO registers */ +#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U) +#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U) +#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U) +#define GPIO_INDT0 (GPIO_BASE + 0x000CU) +#define GPIO_INTDT0 (GPIO_BASE + 0x0010U) +#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U) +#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U) +#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU) +#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U) +#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U) +#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U) +#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U) +#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU) +#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U) +#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U) +#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U) +#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU) +#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U) +#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U) +#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U) +#define GPIO_INDT1 (GPIO_BASE + 0x100CU) +#define GPIO_INTDT1 (GPIO_BASE + 0x1010U) +#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U) +#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U) +#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU) +#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U) +#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U) +#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U) +#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U) +#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU) +#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U) +#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U) +#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U) +#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU) +#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U) +#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U) +#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U) +#define GPIO_INDT2 (GPIO_BASE + 0x200CU) +#define GPIO_INTDT2 (GPIO_BASE + 0x2010U) +#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U) +#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U) +#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU) +#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U) +#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U) +#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U) +#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U) +#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU) +#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U) +#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U) +#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U) +#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU) +#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U) +#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U) +#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U) +#define GPIO_INDT3 (GPIO_BASE + 0x300CU) +#define GPIO_INTDT3 (GPIO_BASE + 0x3010U) +#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U) +#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U) +#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU) +#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U) +#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U) +#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U) +#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U) +#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU) +#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U) +#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U) +#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U) +#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU) +#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U) +#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U) +#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U) +#define GPIO_INDT4 (GPIO_BASE + 0x400CU) +#define GPIO_INTDT4 (GPIO_BASE + 0x4010U) +#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U) +#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U) +#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU) +#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U) +#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U) +#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U) +#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U) +#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU) +#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U) +#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U) +#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U) +#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU) +#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U) +#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U) +#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U) +#define GPIO_INDT5 (GPIO_BASE + 0x500CU) +#define GPIO_INTDT5 (GPIO_BASE + 0x5010U) +#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U) +#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U) +#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU) +#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U) +#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U) +#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U) +#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U) +#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU) +#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U) +#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U) +#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U) +#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU) + +/* Pin functon base address */ +/* 0xE6060000 */ +#define PFC_BASE (BASE_PFC_ADDR) + +/* Pin functon registers */ +#define PFC_PMMR (PFC_BASE + 0x0000U) +#define PFC_GPSR0 (PFC_BASE + 0x0100U) +#define PFC_GPSR1 (PFC_BASE + 0x0104U) +#define PFC_GPSR2 (PFC_BASE + 0x0108U) +#define PFC_GPSR3 (PFC_BASE + 0x010CU) +#define PFC_GPSR4 (PFC_BASE + 0x0110U) +#define PFC_GPSR5 (PFC_BASE + 0x0114U) +#define PFC_IPSR0 (PFC_BASE + 0x0200U) +#define PFC_IPSR1 (PFC_BASE + 0x0204U) +#define PFC_IPSR2 (PFC_BASE + 0x0208U) +#define PFC_IPSR3 (PFC_BASE + 0x020CU) +#define PFC_IPSR4 (PFC_BASE + 0x0210U) +#define PFC_IPSR5 (PFC_BASE + 0x0214U) +#define PFC_IPSR6 (PFC_BASE + 0x0218U) +#define PFC_IPSR7 (PFC_BASE + 0x021CU) +#define PFC_IPSR8 (PFC_BASE + 0x0220U) +#define PFC_IPSR9 (PFC_BASE + 0x0224U) +#define PFC_IPSR10 (PFC_BASE + 0x0228U) +#define PFC_IOCTRL0 (PFC_BASE + 0x0300U) +#define PFC_IOCTRL1 (PFC_BASE + 0x0304U) +#define PFC_IOCTRL2 (PFC_BASE + 0x0308U) +#define PFC_IOCTRL3 (PFC_BASE + 0x030CU) +#define PFC_IOCTRL4 (PFC_BASE + 0x0310U) +#define PFC_IOCTRL5 (PFC_BASE + 0x0314U) +#define PFC_IOCTRL6 (PFC_BASE + 0x0318U) +#define PFC_IOCTRL7 (PFC_BASE + 0x031CU) +#define PFC_IOCTRL8 (PFC_BASE + 0x0320U) +#define PFC_IOCTRL9 (PFC_BASE + 0x0324U) +#define PFC_IOCTRL10 (PFC_BASE + 0x0328U) +#define PFC_IOCTRL11 (PFC_BASE + 0x032CU) +#define PFC_IOCTRL12 (PFC_BASE + 0x0330U) +#define PFC_IOCTRL13 (PFC_BASE + 0x0334U) +#define PFC_IOCTRL14 (PFC_BASE + 0x0338U) +#define PFC_IOCTRL15 (PFC_BASE + 0x033CU) +#define PFC_IOCTRL16 (PFC_BASE + 0x0340U) +#define PFC_IOCTRL17 (PFC_BASE + 0x0344U) +#define PFC_IOCTRL18 (PFC_BASE + 0x0348U) +#define PFC_IOCTRL19 (PFC_BASE + 0x034CU) +#define PFC_IOCTRL30 (PFC_BASE + 0x0380U) +#define PFC_IOCTRL31 (PFC_BASE + 0x0384U) +#define PFC_IOCTRL32 (PFC_BASE + 0x0388U) +#define PFC_IOCTRL33 (PFC_BASE + 0x038CU) +#define PFC_IOCTRL40 (PFC_BASE + 0x03C0U) +#define PFC_TSREG (PFC_BASE + 0x03E4U) +#define PFC_PUEN0 (PFC_BASE + 0x0400U) +#define PFC_PUEN1 (PFC_BASE + 0x0404U) +#define PFC_PUEN2 (PFC_BASE + 0x0408U) +#define PFC_PUEN3 (PFC_BASE + 0x040CU) +#define PFC_PUEN4 (PFC_BASE + 0x0410U) +#define PFC_PUD0 (PFC_BASE + 0x0440U) +#define PFC_PUD1 (PFC_BASE + 0x0444U) +#define PFC_PUD2 (PFC_BASE + 0x0448U) +#define PFC_PUD3 (PFC_BASE + 0x044CU) +#define PFC_PUD4 (PFC_BASE + 0x0450U) +#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U) +#endif /* PFC_REGISTER_H__ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/qos.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/qos.h new file mode 100644 index 0000000..b236b2a --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/qos.h @@ -0,0 +1,38 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : QoS driver header + ******************************************************************************/ + +#ifndef QOS_INIT_H_ +#define QOS_INIT_H_ + +extern void qos_init(void); + +#endif /* QOS_INIT_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/qos_mstat.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/qos_mstat.h new file mode 100644 index 0000000..000e5c6 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/qos_mstat.h @@ -0,0 +1,152 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : QoS MSTAT table header + ******************************************************************************/ + +#ifndef QOS_MSTAT_H_ +#define QOS_MSTAT_H_ + +typedef struct{ + uint16_t offset; + uint64_t mstat_fix; + uint64_t mstat_be; +} QOS_MSTAT_SETTING_TABLE; + + +const QOS_MSTAT_SETTING_TABLE mstat_v2_tbl[] = { + {0x0278U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0298U, 0x000000000000FFFFULL, 0x0000000000000000ULL}, + {0x0320U, 0x000C04080000FFFFULL, 0x0000000000000000ULL}, + {0x0328U, 0x000C04080000FFFFULL, 0x0000000000000000ULL} +}; + +const QOS_MSTAT_SETTING_TABLE mstat_tbl[] = { + {0x0000U, 0x000C00000000FFFFULL, 0x00100200063FFC01ULL}, + {0x0008U, 0x000C00000000FFFFULL, 0x00100200063FFC01ULL}, + {0x0010U, 0x000C00000000FFFFULL, 0x00100200063FFC01ULL}, + {0x0018U, 0x000C00000000FFFFULL, 0x00100200063FFC01ULL}, + {0x0020U, 0x001408280000FFFFULL, 0x0000000000000000ULL}, + {0x0028U, 0x000C04320000FFFFULL, 0x0000000000000000ULL}, + {0x0030U, 0x001004040000FFFFULL, 0x0000000000000000ULL}, + {0x0038U, 0x001004080000FFFFULL, 0x0000000000000000ULL}, + {0x0040U, 0x001004080000FFFFULL, 0x0000000000000000ULL}, + {0x0048U, 0x000000000000FFFFULL, 0x0000000000000000ULL}, + {0x0050U, 0x001004280000FFFFULL, 0x0000000000000000ULL}, + {0x0058U, 0x001004280000FFFFULL, 0x0000000000000000ULL}, + {0x0060U, 0x000000000000FFFFULL, 0x0000000000000000ULL}, + {0x0068U, 0x001404300000FFFFULL, 0x0000000000000000ULL}, + {0x0070U, 0x001004080000FFFFULL, 0x0000000000000000ULL}, + {0x0078U, 0x001004080000FFFFULL, 0x0000000000000000ULL}, + {0x0080U, 0x001004080000FFFFULL, 0x0000000000000000ULL}, + {0x0088U, 0x000000000000FFFFULL, 0x0000000000000000ULL}, + {0x0090U, 0x001004140000FFFFULL, 0x0000000000000000ULL}, + {0x0098U, 0x001004140000FFFFULL, 0x0000000000000000ULL}, + {0x00A0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x00A8U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x00B0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x00B8U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x00C0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x00C8U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x00D0U, 0x001404010000FFFFULL, 0x0000000000000000ULL}, + {0x00D8U, 0x000000000000FFFFULL, 0x00100040063FFC01ULL}, + {0x00E0U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL}, + {0x00E8U, 0x000C04010000FFFFULL, 0x00100040063FFC01ULL}, + {0x00F0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x00F8U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x0100U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x0108U, 0x000C04010000FFFFULL, 0x0000000000000000ULL}, + {0x0110U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x0118U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL}, + {0x0120U, 0x000C04010000FFFFULL, 0x00100040063FFC01ULL}, + {0x0128U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x0130U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x0138U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x0140U, 0x000C04010000FFFFULL, 0x00100200063FFC01ULL}, + {0x0148U, 0x000C04010000FFFFULL, 0x00100200063FFC01ULL}, + {0x0150U, 0x000000000000FFFFULL, 0x00100040063FFC01ULL}, + {0x0158U, 0x001404010000FFFFULL, 0x0000000000000000ULL}, + {0x0160U, 0x001404280000FFFFULL, 0x0000000000000000ULL}, + {0x0168U, 0x001404280000FFFFULL, 0x0000000000000000ULL}, + {0x0170U, 0x001408280000FFFFULL, 0x0000000000000000ULL}, + {0x0178U, 0x001408280000FFFFULL, 0x0000000000000000ULL}, + {0x0180U, 0x001408280000FFFFULL, 0x0000000000000000ULL}, + {0x0188U, 0x000C08200000FFFFULL, 0x0000000000000000ULL}, + {0x0190U, 0x001004140000FFFFULL, 0x0000000000000000ULL}, + {0x0198U, 0x001004140000FFFFULL, 0x0000000000000000ULL}, + {0x01A0U, 0x000000000000FFFFULL, 0x0000000000000000ULL}, + {0x01A8U, 0x000000000000FFFFULL, 0x0000000000000000ULL}, + {0x01B0U, 0x000000000000FFFFULL, 0x0000000000000000ULL}, + {0x01B8U, 0x000C00000000FFFFULL, 0x0000000000000000ULL}, + {0x01C0U, 0x001404010000FFFFULL, 0x0000000000000000ULL}, + {0x01C8U, 0x001004080000FFFFULL, 0x0000000000000000ULL}, + {0x01D0U, 0x001004080000FFFFULL, 0x0000000000000000ULL}, + {0x01D8U, 0x001004080000FFFFULL, 0x0000000000000000ULL}, + {0x01E0U, 0x0010043F0000FFFFULL, 0x0000000000000000ULL}, + {0x01E8U, 0x001004080000FFFFULL, 0x0000000000000000ULL}, + {0x01F0U, 0x0010043F0000FFFFULL, 0x0000000000000000ULL}, + {0x01F8U, 0x001004080000FFFFULL, 0x0000000000000000ULL}, + {0x0200U, 0x001004080000FFFFULL, 0x0000000000000000ULL}, + {0x0208U, 0x0010043F0000FFFFULL, 0x0000000000000000ULL}, + {0x0210U, 0x000000000000FFFFULL, 0x0000000000000000ULL}, + {0x0218U, 0x0010043F0000FFFFULL, 0x0000000000000000ULL}, + {0x0220U, 0x000000000000FFFFULL, 0x0000000000000000ULL}, + {0x0228U, 0x001404010000FFFFULL, 0x0000000000000000ULL}, + {0x0230U, 0x001404010000FFFFULL, 0x0000000000000000ULL}, + {0x0238U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL}, + {0x0240U, 0x000000000000FFFFULL, 0x0000000000000000ULL}, + {0x0248U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL}, + {0x0250U, 0x000000000000FFFFULL, 0x0000000000000000ULL}, + {0x0258U, 0x001400000000FFFFULL, 0x0000000000000000ULL}, + {0x0260U, 0x001400000000FFFFULL, 0x0000000000000000ULL}, + {0x0268U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL}, + {0x0270U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x0278U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x0280U, 0x000C04010000FFFFULL, 0x00100080063FFC01ULL}, + {0x0288U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL}, + {0x0290U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL}, + {0x0298U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL}, + {0x02A0U, 0x000C04010000FFFFULL, 0x00100020063FFC01ULL}, + {0x02A8U, 0x000C04010000FFFFULL, 0x00100060063FFC01ULL}, + {0x02B0U, 0x000C04010000FFFFULL, 0x00100100063FFC01ULL}, + {0x02B8U, 0x001404010000FFFFULL, 0x0000000000000000ULL}, + {0x02C0U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL}, + {0x02C8U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL}, + {0x02D0U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL}, + {0x02D8U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL}, + {0x02E0U, 0x000000000000FFFFULL, 0x00100020063FFC01ULL}, + {0x02E8U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL}, + {0x02F0U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL}, + {0x02F8U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL}, + {0x0300U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL}, + {0x0308U, 0x000000000000FFFFULL, 0x00100080063FFC01ULL}, + {0x0310U, 0x000000000000FFFFULL, 0x00100100063FFC01ULL}, + {0x0318U, 0x001404010000FFFFULL, 0x0000000000000000ULL} +}; +#endif /* QOS_MSTAT_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/qos_qoswt.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/qos_qoswt.h new file mode 100644 index 0000000..73fd57b --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/qos_qoswt.h @@ -0,0 +1,146 @@ +/******************************************************************************* + * Copyright (c) 2019-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : QoS Write Training table header + ******************************************************************************/ + +#ifndef QOS_QOSWT_H_ +#define QOS_QOSWT_H_ + +typedef struct{ + uint16_t offset; + uint64_t qoswt_fix; + uint64_t qoswt_be; +} QOS_QOSWT_SETTING_TABLE; + +const QOS_QOSWT_SETTING_TABLE qoswt_tbl[] = { + {0x0800U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0808U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0810U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0818U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0820U, 0x001404200000FFFFULL, 0x0000000000000000ULL}, + {0x0828U, 0x000C04320000FFFFULL, 0x0000000000000000ULL}, + {0x0830U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0838U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0840U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0848U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0850U, 0x001004200000FFFFULL, 0x0000000000000000ULL}, + {0x0858U, 0x001004200000FFFFULL, 0x0000000000000000ULL}, + {0x0860U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0868U, 0x001404300000C010ULL, 0x0000000000000000ULL}, + {0x0870U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0878U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0880U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0888U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0890U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0898U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x08A0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x08A8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x08B0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x08B8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x08C0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x08C8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x08D0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x08D8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x08E0U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL}, + {0x08E8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x08F0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x08F8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0900U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0908U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0910U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0918U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0920U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0928U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0930U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0938U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0940U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0948U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0950U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0958U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0960U, 0x001404200000FFFFULL, 0x0000000000000000ULL}, + {0x0968U, 0x001404200000FFFFULL, 0x0000000000000000ULL}, + {0x0970U, 0x001404200000FFFFULL, 0x0000000000000000ULL}, + {0x0978U, 0x001404200000FFFFULL, 0x0000000000000000ULL}, + {0x0980U, 0x001404200000FFFFULL, 0x0000000000000000ULL}, + {0x0988U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0990U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0998U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x09A0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x09A8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x09B0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x09B8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x09C0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x09C8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x09D0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x09D8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x09E0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x09E8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x09F0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x09F8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A00U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A08U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A10U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A18U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A20U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A28U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A30U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A38U, 0x000C040A0000FFFFULL, 0x0000000000000000ULL}, + {0x0A40U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A48U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A50U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A58U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A60U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A68U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A70U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A78U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A80U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A88U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A90U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0A98U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0AA0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0AA8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0AB0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0AB8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0AC0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0AC8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0AD0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0AD8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0AE0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0AE8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0AF0U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0AF8U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0B00U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0B08U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0B10U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0B18U, 0x0000000000000000ULL, 0x0000000000000000ULL}, + {0x0B20U, 0x0000000000000000ULL, 0x0000000000000000ULL}, /* Ver.2.x only */ + {0x0B28U, 0x0000000000000000ULL, 0x0000000000000000ULL} /* Ver.2.x only */ +}; +#endif /* QOS_QOSWT_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rcar_def.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rcar_def.h new file mode 100644 index 0000000..ccee432 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rcar_def.h @@ -0,0 +1,55 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : R-Car common header + ******************************************************************************/ + +#ifndef RCAR_DEF_H_ +#define RCAR_DEF_H_ + +#include "remap_register.h" + +/* Product Register */ +#define PRR (BASE_PRR_ADDR) /* PRR register */ +#define PRR_PRODUCT_MASK (0x00007F00U) /* Product mask */ +#define PRR_CUT_MASK (0x000000FFU) /* Cut Number bit mask */ +#define PRR_MAJOR_MASK (0x000000F0U) /* Major bit mask */ +#define PRR_MINOR_MASK (0x0000000FU) /* Minor bit mask */ +#define PRR_PRODUCT_SHIFT (8U) /* PRR bit shift */ +#define PRR_MAJOR_SHIFT (4U) /* Major bit shift */ +#define PRR_MINOR_SHIFT (0U) /* Minor bit shift */ +#define PRR_MAJOR_OFFSET (1U) + +#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */ +#define PRR_PRODUCT_10 (0x00000000U) +#define PRR_PRODUCT_11 (0x00000001U) +#define PRR_PRODUCT_20 (0x00000010U) + +#endif /* RCAR_DEF_H_ */ + diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/remap.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/remap.h new file mode 100644 index 0000000..deb9ef9 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/remap.h @@ -0,0 +1,40 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : remap driver header + ******************************************************************************/ +#ifndef REMAP_H_ +#define REMAP_H_ + +uint32_t remap_get_phys_addr(uint32_t remap_addr); +uint32_t remap_get_remap_addr(uint32_t phys_addr); +void remap_register(uint32_t addr, uint32_t size, uint32_t *remap_addr); +void remap_unregister(uint32_t remap_addr); + +#endif /* REMAP_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/remap_register.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/remap_register.h new file mode 100644 index 0000000..f45f9a5 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/remap_register.h @@ -0,0 +1,208 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : remap register header + ******************************************************************************/ + +#ifndef REMAP_REGISTER_H_ +#define REMAP_REGISTER_H_ + + +#define REMAP_BASE (0xFF1FC400U) + +#define SICREMAP2M(a) (REMAP_BASE + ((uint32_t)(a) * (0x0004U))) + +#define ICUMX_PROT0PCMD (0xFFFEE090U) +#define ICUMX_PROT0PS (0xFFFEE094U) +#define PROTCMD_START (0xA5U) +#define PROTS0ERR (0x01U) + +/* REMAP setting */ +/* Remap ID(0 -- 15) */ +#define ICU_REMAP_NUM_RTRAM (15U) /* RTRAM */ +#define ICU_REMAP_NUM_CC (14U) /* CC63S */ +#define ICU_REMAP_NUM_PFC (13U) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */ +#define ICU_REMAP_NUM_MFIS (12U) /* MFIS */ +#define ICU_REMAP_NUM_RPC (11U) /* RPC */ +#define ICU_REMAP_NUM_RTDMAC (10U) /* RT-DMAC0 */ +#define ICU_REMAP_NUM_SCIF (9U) /* SCIF */ +#define ICU_REMAP_NUM_MMC (8U) /* MMC */ +#define ICU_REMAP_NUM_HSCIF (7U) /* HSCIF */ +#define ICU_REMAP_NUM_DMAC (6U) /* SYS-DMAC0 */ +#define ICU_REMAP_NUM_PRR (0U) /* PRR Register */ + +/* SICREMAP2M15 */ +#define ICU_REMAP_RTSRAM (0xEB200000U) /* RT-SRAM */ +/* SICREMAP2M14 */ +#define ICU_REMAP_CC (0xE6600000U) /* CC63S,System DMA */ +/* SICREMAP2M13 */ +#define ICU_REMAP_PFC (0xE6000000U) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */ +/* SICREMAP2M12 */ +#define ICU_REMAP_MFIS (0xE6200000U) /* MFIS */ +/* SICREMAP2M11 */ +#define ICU_REMAP_RPC (0xEE200000U) /* RPC */ +/* SICREMAP2M10 */ +#define ICU_REMAP_SCIF (0xE6E00000U) /* SCIF */ +/* SICREMAP2M9 */ +#define ICU_REMAP_MMC (0xEE000000U) /* MMC */ +/* SICREMAP2M8 */ +#define ICU_REMAP_RTDMAC (0xFFC00000U) /* RT-DMAC0 */ +/* SICREMAP2M7 */ +#define ICU_REMAP_HSCIF (0xE6400000U) /* HSCIF */ +/* SICREMAP2M6 */ +#define ICU_REMAP_DMAC (0xE7200000U) /* SYS-DMAC0 */ +/* SICREMAP2M0 */ +#define ICU_REMAP_PRR (0xFFE00000U) /* PRR register */ + + +#define ICU_REMAP15_BASE (ICU_REMAP_RTRAM) /* RTRAM */ +#define ICU_REMAP14_BASE (ICU_REMAP_CC) /* CC63S */ +#define ICU_REMAP13_BASE (ICU_REMAP_PFC) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */ +#define ICU_REMAP12_BASE (ICU_REMAP_MFIS) /* MFIS */ +#define ICU_REMAP11_BASE (ICU_REMAP_RPC) /* RPC */ +#define ICU_REMAP10_BASE (ICU_REMAP_RTDMAC) /* RT-DMAC0 */ +#define ICU_REMAP9_BASE (ICU_REMAP_SCIF) /* SCIF */ +#define ICU_REMAP8_BASE (ICU_REMAP_MMC) /* MMC */ +#define ICU_REMAP7_BASE (ICU_REMAP_HSCIF) /* HSCIF */ +#define ICU_REMAP6_BASE (ICU_REMAP_DMAC) /* SYS-DMAC0 */ +#define ICU_REMAP5_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP4_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP3_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP2_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP1_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP0_BASE (ICU_REMAP_PRR) /* PRR,INTC,RT-SRAM protection */ + +/* Base address offset of each register after remap */ +/* REMAP15(0xEB200000U) */ +/* RT-SRAM */ +#define ICU_REMAP_OFFSET_RTSRAM (0x00000000U) + +/* REMAP14(0xE6600000U) */ +#define ICU_REMAP_OFFSET_CC63S (0x00000000U) +#define ICU_REMAP_OFFSET_AXI (0x00184000U) /* (0xE6784000U) */ +#define ICU_REMAP_OFFSET_DBSC (0x00190000U) /* (0xE6790000U) */ +#define ICU_REMAP_OFFSET_MSTAT (0x001e0000U) /* (0xE67e0000U) */ +#define ICU_REMAP_OFFSET_QOS (0x001F0000U) /* (0xE67F0000U) */ + +/* REMAP13(0xE6000000U) */ +/* GPIO */ +#define ICU_REMAP_OFFSET_GPIO0 (0x00050000U) +#define ICU_REMAP_OFFSET_GPIO1 (0x00051000U) +#define ICU_REMAP_OFFSET_GPIO2 (0x00052000U) +#define ICU_REMAP_OFFSET_GPIO3 (0x00053000U) +#define ICU_REMAP_OFFSET_GPIO4 (0x00054000U) +#define ICU_REMAP_OFFSET_GPIO5 (0x00055000U) +/* PFC */ +#define ICU_REMAP_OFFSET_PFC (0x00060000U) +/* LIFEC */ +#define ICU_REMAP_OFFSET_LIFEC (0x00110000U) +/* CPGA */ +#define ICU_REMAP_OFFSET_CPGA (0x00150000U) +/* RESET */ +#define ICU_REMAP_OFFSET_RESET (0x00160000U) +/* SYSC */ +#define ICU_REMAP_OFFSET_SYSC (0x00180000U) +/* THS1 */ +#define ICU_REMAP_OFFSET_THS1 (0x00198000U) /* (0xE6198000U) */ + +/* REMAP12(0xE6200000U) */ +/* MFIS */ +#define ICU_REMAP_OFFSET_MFIS (0x00060000U) + +/* REMAP11(0xEE200000U) */ +/*RPC*/ +#define ICU_REMAP_OFFSET_RPC (0x00000000U) + +/* REMAP10(0xFFC00000U) */ +/* RT-DMA */ +#define ICU_REMAP_OFFSET_RTDMA (0x00010000U) +#define ICU_REMAP_OFFSET_RTACT (0x00050800U) + +/* REMAP9(0xE6E00000U) */ +/*SCIF*/ +#define ICU_REMAP_OFFSET_SCIF0 (0x00060000U) + +/* REMAP8(0xEE000000U) */ +/* SDHI2/MMC0 */ +#define ICU_REMAP_OFFSET_SDHI (0x00140000U) + +/* REMAP7(0xE6400000U) */ +/* HSCIF */ +#define ICU_REMAP_OFFSET_HSCIF0 (0x00140000U) + +/* REMAP6(0xE7200000U) */ +/* SYS-DMAC */ +#define ICU_REMAP_OFFSET_SYSDMAC (0x00100000U) + +/* REMAP0(0xFFE00000U) */ +/* RT-SRAM Register */ +#define ICU_REMAP_OFFSET_RTSRAM_REG (0x00090000U) +/* PRR */ +#define ICU_REMAP_OFFSET_PRR (0x00100044U) + + +/* Calculate the base address of each register after remapping */ +#define ICU_REMAP0 (0xFC000000U) +#define ICU_REMAP_CALC(val) (ICU_REMAP0 + ((uint32_t)(val) * 0x00200000U)) + +/* REMAP15(0xEB200000U) */ +#define BASE_RTSRAM_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTRAM) + ICU_REMAP_OFFSET_RTSRAM) +/* REMAP14(0xE6600000U) */ +#define BASE_AXI_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_AXI) +#define BASE_DBSC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_DBSC) +#define BASE_MSTAT_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_MSTAT) +#define BASE_QOS_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_QOS) +/* REMAP13(0xE6000000U) */ +#define BASE_GPIO_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_GPIO0) +#define BASE_PFC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_PFC) +#define BASE_LIFEC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_LIFEC) +#define BASE_CPG_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_CPGA) +#define BASE_RESET_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_RESET) +#define BASE_SYSC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_SYSC) +#define BASE_THS1_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_THS1) +/* REMAP12(0xE6200000U) */ +#define BASE_MFIS_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_MFIS) + ICU_REMAP_OFFSET_MFIS) +/* REMAP11(0xEE200000U) */ +#define BASE_RPC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RPC) + ICU_REMAP_OFFSET_RPC) +/* REMAP10(0xFFC00000U) */ +#define BASE_RTDMA_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMA) +#define BASE_RTACT_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTACT) +/* REMAP9(0xE6E00000U) */ +#define BASE_SCIF_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF0) +/* REMAP8(0xEE000000U) */ +#define BASE_MMC0_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_MMC) + ICU_REMAP_OFFSET_SDHI) +/* REMAP7(0xE6400000U) */ +#define BASE_HSCIF_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_HSCIF) + ICU_REMAP_OFFSET_HSCIF0) +/* REMAP6(0xE7200000U) */ +#define BASE_DMA_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_DMAC) + ICU_REMAP_OFFSET_SYSDMAC) +/* REMAP0(0xFFE00000U) */ +#define BASE_RTSRAM_REG_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PRR) + ICU_REMAP_OFFSET_RTSRAM_REG) +#define BASE_PRR_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PRR) + ICU_REMAP_OFFSET_PRR) + +#endif /* REMAP_REGISTER_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rom_api.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rom_api.h new file mode 100644 index 0000000..5ff4e9b --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rom_api.h @@ -0,0 +1,72 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : boot ROM API header + ******************************************************************************/ +#ifndef ROM_API_H__ +#define ROM_API_H__ + +#include +#include + +#define SBROM_OK (0x00000000U) +#define SBROM_ILLEGAL_INPUT_PARAM_ERR (0x0B000001U) +#define SBROM_ILLEGAL_OEM_HASH_VALUE_ERR (0x0B000008U) +#define SBROM_ILLEGAL_LCS_FOR_OPERATION_ERR (0x0B000010U) +#define SBROM_HASH_NOT_PROGRAMMED_ERR (0x0B000100U) +#define SBROM_PUB_KEY_HASH_VALIDATION_FAILURE (0xF1000006U) +#define SBROM_RSA_SIG_VERIFICATION_FAILED (0xF1000007U) + +#define GETLCS_OK (0x00000000U) +#define LCS_CM (0x00000000U) /* CM */ +#define LCS_DM (0x00000001U) /* DM */ +#define LCS_SD (0x00000003U) /* SD */ +#define LCS_SE (0x00000005U) /* SE */ +#define LCS_FA (0x00000007U) /* FA */ + +/* Certificate Logical address */ +#define LOGICAL_BOOT_KEY_ADDR (uint32_t)(KEY_CERT_DEST_ADDR) +#define LOGICAL_CONTENT_CERT_ADDR(x) (uint32_t)(CONTENT_CERT_DEST_ADDR + CONTENT_CERT_INFO_SIZE + CERT_OFFSET(x)) +#define CERT_OFFSET(x) (uint32_t)((uint32_t)(x) * CONTENT_CERT_DST_SIZE) + +/* BOOTROM API address for V3H */ +#define ROM_SECUREBOOT_API_V3H (0x01104400U) +#define ROM_GET_LCS_V3H (0x01104418U) + +typedef uint32_t (*ROM_SECURE_BOOT_API)(uint32_t *pKeyCert, + uint32_t *pContentCert, + void *param); +typedef uint32_t (*ROM_GETLCS_API)(uint32_t *pLcs); + +uint32_t ROM_SecureBootAPI(uint32_t *pContentCert); +uint32_t ROM_GetLcs(uint32_t *pLcs); + +extern uint32_t rom_api_wrap(uint32_t a, uint32_t b, uint32_t c, uint32_t d); + +#endif /* ROM_API_H__ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rpc.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rpc.h new file mode 100644 index 0000000..7bbd257 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rpc.h @@ -0,0 +1,42 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RPC driver header + ******************************************************************************/ + +#ifndef RPC_H__ +#define RPC_H__ + +#include + +void rpc_init(void); +void rpc_release(void); +void rpc_end_state_check(void); + +#endif /* RPC_H__ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rpc_register.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rpc_register.h new file mode 100644 index 0000000..f52fc91 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rpc_register.h @@ -0,0 +1,67 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RPC register header + ******************************************************************************/ + +#ifndef RPC_REGISTER_H_ +#define RPC_REGISTER_H_ + + +#include + +/* RPC base address */ +/* 0xEE200000 */ +#define RPC_BASE (BASE_RPC_ADDR) + +#define RPC_CMNCR (RPC_BASE + 0x0000U) /* Common control register */ +#define RPC_SSLDR (RPC_BASE + 0x0004U) /* SSL delay register */ +#define RPC_DRCR (RPC_BASE + 0x000CU) /* Data read control register */ +#define RPC_DRCMR (RPC_BASE + 0x0010U) /* Data read command setting register */ +#define RPC_DREAR (RPC_BASE + 0x0014U) /* Data read extended address register */ +#define RPC_DRENR (RPC_BASE + 0x001CU) /* Data read enable setting register */ +#define RPC_SMCR (RPC_BASE + 0x0020U) /* Manual mode control register */ +#define RPC_SMCMR (RPC_BASE + 0x0024U) /* Manual mode command setting register */ +#define RPC_SMADR (RPC_BASE + 0x0028U) /* Manual mode address setting register */ +#define RPC_SMOPR (RPC_BASE + 0x002CU) /* Manual mode option setting register */ +#define RPC_SMENR (RPC_BASE + 0x0030U) /* Manual mode enable setting register */ +#define RPC_SMRDR0 (RPC_BASE + 0x0038U) /* Manual mode read data register 0 */ +#define RPC_SMRDR1 (RPC_BASE + 0x003CU) /* Manual mode read data register 1 */ +#define RPC_SMWDR0 (RPC_BASE + 0x0040U) /* Manual mode write data register 0 */ +#define RPC_CMNSR (RPC_BASE + 0x0048U) /* Common status register */ +#define RPC_DRDMCR (RPC_BASE + 0x0058U) /* Data read dummy cycle setting register */ +#define RPC_DRDRENR (RPC_BASE + 0x005CU) /* Data read DDR enable register */ +#define RPC_SMDMCR (RPC_BASE + 0x0060U) /* Manual mode dummy cycle setting register */ +#define RPC_SMDRENR (RPC_BASE + 0x0064U) /* Manual mode DDR enable registerv */ +#define RPC_PHYCNT (RPC_BASE + 0x007CU) /* PHY control register */ +#define RPC_OFFSET1 (RPC_BASE + 0x0080U) /* DDR operation */ +#define RPC_OFFSET2 (RPC_BASE + 0x0084U) /* */ +#define RPC_PHYINT (RPC_BASE + 0x0088U) /* PHY interrupt register */ +#define RPC_SEC_CONF (RPC_BASE + 0x00B8U) /* Secure configuration register */ +#endif /* RPC_REGISTER_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rst_register.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rst_register.h new file mode 100644 index 0000000..deed130 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rst_register.h @@ -0,0 +1,53 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RST register header + ******************************************************************************/ + +#ifndef RST_REGISTER_H_ +#define RST_REGISTER_H_ + +#include + +#define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */ +#define RST_WDTRSTCR (RST_BASE + 0x0054U) +#define RST_CR7BAR (RST_BASE + 0x0070U) +#define RST_CR7BAR2 (RST_BASE + 0x0074U) +#define RST_CR7BAR_BAREN ((uint32_t)1U << 4U) +#define RST_CR7BAR2_VLD ((uint32_t)1U << 0U) + +#define RST_ICUMXBAR (RST_BASE + 0x0078U) +#define RST_ICUMXBAR_BAREN ((uint32_t)1U << 4U) + +#define RST_MODEMR (RST_BASE + 0x0060U) /* Mode pin register */ +#define RST_CA53RESCNT (RST_BASE + 0x0044U) /* Reset control register for A53 */ +#define RST_CA53CPU0BARL (RST_BASE + 0x0084U) +#define RST_CA53CPU0BARH (RST_BASE + 0x0080U) + +#endif /* RST_REGISTER_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rtsram_register.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rtsram_register.h new file mode 100644 index 0000000..713fb3c --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/rtsram_register.h @@ -0,0 +1,76 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-SRAM register header + ******************************************************************************/ + +#ifndef RTSRAM_REGISTER_H_ +#define RTSRAM_REGISTER_H_ + +#include + +/* AXI base address */ +#define RTSRAM_REG__BASE (BASE_RTSRAM_REG_ADDR) + + +/* RT-SRAM protection */ +#define SECDIV0D (RTSRAM_REG__BASE + 0x0000U) /* RT-SRAM protected area division 0 */ +#define SECDIV1D (RTSRAM_REG__BASE + 0x0004U) /* RT-SRAM protected area division 1 */ +#define SECDIV2D (RTSRAM_REG__BASE + 0x0008U) /* RT-SRAM protected area division 2 */ +#define SECDIV3D (RTSRAM_REG__BASE + 0x000CU) /* RT-SRAM protected area division 3 */ +#define SECDIV4D (RTSRAM_REG__BASE + 0x0010U) /* RT-SRAM protected area division 4 */ +#define SECDIV5D (RTSRAM_REG__BASE + 0x0014U) /* RT-SRAM protected area division 5 */ +#define SECDIV6D (RTSRAM_REG__BASE + 0x0018U) /* RT-SRAM protected area division 6 */ +#define SECDIV7D (RTSRAM_REG__BASE + 0x001CU) /* RT-SRAM protected area division 7 */ +#define SECDIV8D (RTSRAM_REG__BASE + 0x0020U) /* RT-SRAM protected area division 8 */ +#define SECDIV9D (RTSRAM_REG__BASE + 0x0024U) /* RT-SRAM protected area division 9 */ +#define SECDIV10D (RTSRAM_REG__BASE + 0x0028U) /* RT-SRAM protected area division 10 */ +#define SECDIV11D (RTSRAM_REG__BASE + 0x002CU) /* RT-SRAM protected area division 11 */ +#define SECDIV12D (RTSRAM_REG__BASE + 0x0030U) /* RT-SRAM protected area division 12 */ +#define SECDIV13D (RTSRAM_REG__BASE + 0x0034U) /* RT-SRAM protected area division 13 */ +#define SECDIV14D (RTSRAM_REG__BASE + 0x0038U) /* RT-SRAM protected area division 14 */ + +#define SECCTR0D (RTSRAM_REG__BASE + 0x0040U) /* RT-SRAM protected area setting 0 */ +#define SECCTR1D (RTSRAM_REG__BASE + 0x0044U) /* RT-SRAM protected area setting 1 */ +#define SECCTR2D (RTSRAM_REG__BASE + 0x0048U) /* RT-SRAM protected area setting 2 */ +#define SECCTR3D (RTSRAM_REG__BASE + 0x004CU) /* RT-SRAM protected area setting 3 */ +#define SECCTR4D (RTSRAM_REG__BASE + 0x0050U) /* RT-SRAM protected area setting 4 */ +#define SECCTR5D (RTSRAM_REG__BASE + 0x0054U) /* RT-SRAM protected area setting 5 */ +#define SECCTR6D (RTSRAM_REG__BASE + 0x0058U) /* RT-SRAM protected area setting 6 */ +#define SECCTR7D (RTSRAM_REG__BASE + 0x005CU) /* RT-SRAM protected area setting 7 */ +#define SECCTR8D (RTSRAM_REG__BASE + 0x0060U) /* RT-SRAM protected area setting 8 */ +#define SECCTR9D (RTSRAM_REG__BASE + 0x0064U) /* RT-SRAM protected area setting 9 */ +#define SECCTR10D (RTSRAM_REG__BASE + 0x0068U) /* RT-SRAM protected area setting 10 */ +#define SECCTR11D (RTSRAM_REG__BASE + 0x006CU) /* RT-SRAM protected area setting 11 */ +#define SECCTR12D (RTSRAM_REG__BASE + 0x0070U) /* RT-SRAM protected area setting 12 */ +#define SECCTR13D (RTSRAM_REG__BASE + 0x0074U) /* RT-SRAM protected area setting 13 */ +#define SECCTR14D (RTSRAM_REG__BASE + 0x0078U) /* RT-SRAM protected area setting 14 */ +#define SECCTR15D (RTSRAM_REG__BASE + 0x007CU) /* RT-SRAM protected area setting 15 */ + +#endif /* RTSRAM_REGISTER_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/scif.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/scif.h new file mode 100644 index 0000000..2b4e831 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/scif.h @@ -0,0 +1,41 @@ +/******************************************************************************* + * Copyright (c) 2018-2019 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : SCIF driver header + ******************************************************************************/ + +#ifndef SCIF_H_ +#define SCIF_H_ + +/* Prototype */ +void scif_init(void); +void console_putc(uint8_t outchar); +void scif_release(void); + +#endif /* SCIF_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/scif_register.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/scif_register.h new file mode 100644 index 0000000..3894597 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/scif_register.h @@ -0,0 +1,56 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : SCIF register header + ******************************************************************************/ + + +#ifndef SCIF_REGISTER_H_ +#define SCIF_REGISTER_H_ + +#include + +/* SCIF0 base address */ +/* 0xE6E60000 */ +#define SCIF0_BASE (BASE_SCIF_ADDR) + +#define SCIF_SCSMR (SCIF0_BASE + 0x0000U) /* 16 Serial mode register */ +#define SCIF_SCBRR (SCIF0_BASE + 0x0004U) /* 8 Bit rate register */ +#define SCIF_SCSCR (SCIF0_BASE + 0x0008U) /* 16 Serial control register */ +#define SCIF_SCFTDR (SCIF0_BASE + 0x000CU) /* 8 Transmit FIFO data register */ +#define SCIF_SCFSR (SCIF0_BASE + 0x0010U) /* 16 Serial status register */ +#define SCIF_SCFRDR (SCIF0_BASE + 0x0014U) /* 8 Receive FIFO data register */ +#define SCIF_SCFCR (SCIF0_BASE + 0x0018U) /* 16 FIFO control register */ +#define SCIF_SCFDR (SCIF0_BASE + 0x001CU) /* 16 FIFO data count register */ +#define SCIF_SCSPTR (SCIF0_BASE + 0x0020U) /* 16 Serial port register */ +#define SCIF_SCLSR (SCIF0_BASE + 0x0024U) /* 16 Line status register */ +#define SCIF_DL (SCIF0_BASE + 0x0030U) /* 16 Frequency division register */ +#define SCIF_CKS (SCIF0_BASE + 0x0034U) /* 16 Clock Select register */ + +#endif /* SCIF_REGISTER_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/sysc_register.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/sysc_register.h new file mode 100644 index 0000000..4242a53 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/sysc_register.h @@ -0,0 +1,54 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : SYSC register header + ******************************************************************************/ + +#ifndef SYSC_REGISTER_H_ +#define SYSC_REGISTER_H_ + +#include "mem_io.h" +#include "remap_register.h" + +#define SYSC_BASE (BASE_SYSC_ADDR) /* (0xE6180000U) */ + +#define SYSC_PWRSR3 (SYSC_BASE + 0x0140U) /* Power status register CA53-SCU */ +#define SYSC_PWRSR7 (SYSC_BASE + 0x0240U) /* Power status register 7 (CR7) */ +#define SYSC_SYSCIER (SYSC_BASE + 0x000CU) /* Interrupt enable register */ +#define SYSC_SYSCIMR (SYSC_BASE + 0x0010U) /* Interrupt mask register */ +#define SYSC_SYSCSR (SYSC_BASE + 0x0000U) /* SYSC status register */ +#define SYSC_PWRONCR3 (SYSC_BASE + 0x014CU) /* Power resume control register CA53-SCU */ +#define SYSC_PWRONCR7 (SYSC_BASE + 0x024CU) /* Power resume control register 7 (CR7) */ +#define SYSC_PWRER3 (SYSC_BASE + 0x0154U) /* Power shutoff/resume error register CA53-SCU */ +#define SYSC_PWRER7 (SYSC_BASE + 0x0254U) /* Power shutoff/resume error register 7 (CR7) */ +#define SYSC_SYSCISR (SYSC_BASE + 0x0004U) /* Interrupt status register */ +#define SYSC_SYSCISCR (SYSC_BASE + 0x0008U) /* Interrupt status clear register */ +#define SYSC_WUPMSKCA53 (SYSC_BASE + 0x0018U) /* Wake-up mask register for A53 */ + +#endif /* SYSC_REGISTER_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/wdt.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/wdt.h new file mode 100644 index 0000000..ddd6200 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/include/wdt.h @@ -0,0 +1,40 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : window watchdog timer function header + ******************************************************************************/ + +#ifndef WDT_H__ +#define WDT_H__ + + +void wdt_init(void); +void wdt_restart(void); + +#endif /* WDT_H__ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/axi-bus_edcint/edcinten.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/axi-bus_edcint/edcinten.c new file mode 100644 index 0000000..4e4b354 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/axi-bus_edcint/edcinten.c @@ -0,0 +1,97 @@ +/******************************************************************************* + * Copyright (c) 2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : EDC's control function + ******************************************************************************/ +/****************************************************************************** + * @file edcinten.c + * - Version : 0.01 + * @brief Initial setting controller. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 18.08.2021 0.01 First Release + *****************************************************************************/ +#include +#include +#include +#include + +/* define */ +#define EDC_BIT_24 (((uint32_t)1U) << 24U) +#define EDC_BIT_0 (((uint32_t)1U) << 0U) +#define EDC_EDCINTEN0_VALID_ALL (0xFC04EFFFU) +#define EDC_EDCINTEN1_VALID_ALL (0xFDFBE000U) +#define EDC_EDCINTEN2_VALID_ALL (0xDFFFFFFCU) +#define EDC_EDCINTEN3_VALID_ALL (0x7C57FFBFU) +#define EDC_EDCINTEN5_VALID_ALL (0xFFFFFFFFU) +#define EDC_EDCINTEN6_VALID_ALL (0xC0FE3BF1U) +#define EDC_EDCINTEN7_VALID_ALL (0x000007FFU) + + +void edc_init(void) +{ + uint32_t reg; + + /* 4.3.16 EDC for RT-SRAM AXI Interface */ + reg = mem_read32(EDCINTEN5); + reg |= (uint32_t)EDC_BIT_24; + mem_write32(EDCINTEN5, reg); + + /* 4.3.23 EDC for RT-SRAM */ + reg = mem_read32(EDC_CFG); + reg |= (uint32_t)EDC_BIT_0; + mem_write32(EDC_CFG, reg); + + /* 4.3.4 EDC for AXI-bus */ + reg = mem_read32(EDCINTEN0); + reg |= (uint32_t)EDC_EDCINTEN0_VALID_ALL; + mem_write32(EDCINTEN0, reg); + reg = mem_read32(EDCINTEN1); + reg |= (uint32_t)EDC_EDCINTEN1_VALID_ALL; + mem_write32(EDCINTEN1, reg); + reg = mem_read32(EDCINTEN2); + reg |= (uint32_t)EDC_EDCINTEN2_VALID_ALL; + mem_write32(EDCINTEN2, reg); + reg = mem_read32(EDCINTEN3); + reg |= (uint32_t)EDC_EDCINTEN3_VALID_ALL; + mem_write32(EDCINTEN3, reg); + reg = mem_read32(EDCINTEN5); + reg |= (uint32_t)EDC_EDCINTEN5_VALID_ALL; + mem_write32(EDCINTEN5, reg); + reg = mem_read32(EDCINTEN6); + reg |= (uint32_t)EDC_EDCINTEN6_VALID_ALL; + mem_write32(EDCINTEN6, reg); + reg = mem_read32(EDCINTEN7); + reg |= (uint32_t)EDC_EDCINTEN7_VALID_ALL; + mem_write32(EDCINTEN7, reg); + +} +/* End of function edc_init(void) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/cpg/cpg.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/cpg/cpg.c new file mode 100644 index 0000000..328e864 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/cpg/cpg.c @@ -0,0 +1,323 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : CPG initialize + ******************************************************************************/ + /****************************************************************************** + * @file cpg.c + * - Version : 0.03 + * @brief Initial setting process of CPG. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + * : 13.04.2021 0.02 Added processing to disable automatic module + * clock stop function + * : 06.07.2021 0.03 Update setting value of module stop register + *****************************************************************************/ + +#include +#include +#include +#include + +/* CPG write protect value */ +#define CPGWPCR_PASSWORD (0xA5A50000U) +#define CPGWPCR_WPE ((uint32_t)1U << 0U) +#define CPGWPCR_WPE_VALID (0U) + +/* CPG module standby defineation */ +/* define */ +#define CPG_MSTPSR0_RTDMAC0 (((uint32_t)1U) << 21U) +#define CPG_MSTPSR0_RTDMAC0_FAILURE_DETCTION (((uint32_t)1U) << 17U) +#define CPG_MSTPSR0_RTDMAC1 (((uint32_t)1U) << 16U) +#define CPG_MSTPSR1_IVCP1E (((uint32_t)1U) << 27U) +#define CPG_MSTPSR1_TMU0 (((uint32_t)1U) << 25U) +#define CPG_MSTPSR1_TMU1 (((uint32_t)1U) << 24U) +#define CPG_MSTPSR1_TMU2 (((uint32_t)1U) << 23U) +#define CPG_MSTPSR1_TMU3 (((uint32_t)1U) << 22U) +#define CPG_MSTPSR1_TMU4 (((uint32_t)1U) << 21U) +#define CPG_MSTPSR1_KCRC0 (((uint32_t)1U) << 14U) +#define CPG_MSTPSR1_KCRC1 (((uint32_t)1U) << 13U) +#define CPG_MSTPSR1_KCRC2 (((uint32_t)1U) << 11U) +#define CPG_MSTPSR1_KCRC3 (((uint32_t)1U) << 10U) +#define CPG_MSTPSR1_DOF (((uint32_t)1U) << 2U) +#define CPG_MSTPSR1_STV (((uint32_t)1U) << 1U) +#define CPG_MSTPSR2_SYS_DMAC1 (((uint32_t)1U) << 18U) +#define CPG_MSTPSR2_SYS_DMAC2 (((uint32_t)1U) << 17U) +#define CPG_MSTPSR2_RTSRAM (((uint32_t)1U) << 15U) +#define CPG_MSTPSR2_MFIS (((uint32_t)1U) << 13U) +#define CPG_MSTPSR2_MSIOF0 (((uint32_t)1U) << 11U) +#define CPG_MSTPSR2_MSIOF1 (((uint32_t)1U) << 10U) +#define CPG_MSTPSR2_MSIOF2 (((uint32_t)1U) << 9U) +#define CPG_MSTPSR2_MSIOF3 (((uint32_t)1U) << 8U) +#define CPG_MSTPSR2_SCIF0 (((uint32_t)1U) << 7U) +#define CPG_MSTPSR2_SCIF1 (((uint32_t)1U) << 6U) +#define CPG_MSTPSR2_SCIF3 (((uint32_t)1U) << 4U) +#define CPG_MSTPSR2_SCIF4 (((uint32_t)1U) << 3U) +#define CPG_MSTPSR3_CRC2 (((uint32_t)1U) << 23U) +#define CPG_MSTPSR3_CRC3 (((uint32_t)1U) << 22U) +#define CPG_MSTPSR3_PCIEC0 (((uint32_t)1U) << 19U) +#define CPG_MSTPSR3_IPC (((uint32_t)1U) << 15U) +#define CPG_MSTPSR3_SD_IF (((uint32_t)1U) << 14U) +#define CPG_MSTPSR3_CRC0 (((uint32_t)1U) << 7U) +#define CPG_MSTPSR3_CRC1 (((uint32_t)1U) << 6U) +#define CPG_MSTPSR3_TPU0 (((uint32_t)1U) << 4U) +#define CPG_MSTPSR3_CMT0 (((uint32_t)1U) << 3U) +#define CPG_MSTPSR3_CMT1 (((uint32_t)1U) << 2U) +#define CPG_MSTPSR3_CMT2 (((uint32_t)1U) << 1U) +#define CPG_MSTPSR3_CMT3 (((uint32_t)1U) << 0U) +#define CPG_MSTPSR4_SUCMT (((uint32_t)1U) << 31U) +#define CPG_MSTPSR4_RWDT (((uint32_t)1U) << 2U) +#define CPG_MSTPSR5_IMP_OCV2 (((uint32_t)1U) << 31U) +#define CPG_MSTPSR5_IMP_OCV3 (((uint32_t)1U) << 29U) +#define CPG_MSTPSR5_IMP_OCV4 (((uint32_t)1U) << 28U) +#define CPG_MSTPSR5_IMPDMA0 (((uint32_t)1U) << 27U) +#define CPG_MSTPSR5_IMPDMA1 (((uint32_t)1U) << 26U) +#define CPG_MSTPSR5_IMPPSC0 (((uint32_t)1U) << 25U) +#define CPG_MSTPSR5_IMPPSC1 (((uint32_t)1U) << 24U) +#define CPG_MSTPSR5_PWM (((uint32_t)1U) << 23U) +#define CPG_MSTPSR5_THS_TSC (((uint32_t)1U) << 22U) +#define CPG_MSTPSR5_IMP4 (((uint32_t)1U) << 21U) +#define CPG_MSTPSR5_HSCIF0 (((uint32_t)1U) << 20U) +#define CPG_MSTPSR5_HSCIF1 (((uint32_t)1U) << 19U) +#define CPG_MSTPSR5_HSCIF2 (((uint32_t)1U) << 18U) +#define CPG_MSTPSR5_HSCIF3 (((uint32_t)1U) << 17U) +#define CPG_MSTPSR5_FLEXRAY (((uint32_t)1U) << 5U) +#define CPG_MSTPSR5_SIMP (((uint32_t)1U) << 0U) +#define CPG_MSTPSR6_VIN8 (((uint32_t)1U) << 28U) +#define CPG_MSTPSR6_VIN9 (((uint32_t)1U) << 27U) +#define CPG_MSTPSR6_VIN10 (((uint32_t)1U) << 25U) +#define CPG_MSTPSR6_VSP (((uint32_t)1U) << 23U) +#define CPG_MSTPSR6_VIN11 (((uint32_t)1U) << 18U) +#define CPG_MSTPSR6_VIN12 (((uint32_t)1U) << 12U) +#define CPG_MSTPSR6_VIN13 (((uint32_t)1U) << 8U) +#define CPG_MSTPSR6_VIN14 (((uint32_t)1U) << 5U) +#define CPG_MSTPSR6_VIN15 (((uint32_t)1U) << 4U) +#define CPG_MSTPSR6_FCPVD0 (((uint32_t)1U) << 3U) +#define CPG_MSTPSR7_LVDS_IF (((uint32_t)1U) << 27U) +#define CPG_MSTPSR7_DU0 (((uint32_t)1U) << 24U) +#define CPG_MSTPSR7_CSI40 (((uint32_t)1U) << 16U) +#define CPG_MSTPSR7_CSI41 (((uint32_t)1U) << 15U) +#define CPG_MSTPSR7_IMR_LX44 (((uint32_t)1U) << 7U) +#define CPG_MSTPSR7_IMR_LX45 (((uint32_t)1U) << 6U) +#define CPG_MSTPSR8_IMPCNN (((uint32_t)1U) << 31U) +#define CPG_MSTPSR8_IMPRAM (((uint32_t)1U) << 30U) +#define CPG_MSTPSR8_IMP_OCV0 (((uint32_t)1U) << 29U) +#define CPG_MSTPSR8_IMP_OCV1 (((uint32_t)1U) << 28U) +#define CPG_MSTPSR8_IMP0 (((uint32_t)1U) << 27U) +#define CPG_MSTPSR8_IMP1 (((uint32_t)1U) << 26U) +#define CPG_MSTPSR8_IMP2 (((uint32_t)1U) << 25U) +#define CPG_MSTPSR8_IMP3 (((uint32_t)1U) << 24U) +#define CPG_MSTPSR8_IMR_LX40 (((uint32_t)1U) << 23U) +#define CPG_MSTPSR8_IMR_LX41 (((uint32_t)1U) << 22U) +#define CPG_MSTPSR8_IMR_LX42 (((uint32_t)1U) << 21U) +#define CPG_MSTPSR8_IMR_LX43 (((uint32_t)1U) << 20U) +#define CPG_MSTPSR8_ISP0 (((uint32_t)1U) << 17U) +#define CPG_MSTPSR8_ISP1 (((uint32_t)1U) << 14U) +#define CPG_MSTPSR8_GIGABIT_ETEERNET (((uint32_t)1U) << 13U) +#define CPG_MSTPSR8_EAVB_IF (((uint32_t)1U) << 12U) +#define CPG_MSTPSR8_VIN0 (((uint32_t)1U) << 11U) +#define CPG_MSTPSR8_VIN1 (((uint32_t)1U) << 10U) +#define CPG_MSTPSR8_VIN2 (((uint32_t)1U) << 9U) +#define CPG_MSTPSR8_VIN3 (((uint32_t)1U) << 8U) +#define CPG_MSTPSR8_VIN4 (((uint32_t)1U) << 7U) +#define CPG_MSTPSR8_VIN5 (((uint32_t)1U) << 6U) +#define CPG_MSTPSR8_VIN6 (((uint32_t)1U) << 5U) +#define CPG_MSTPSR8_VIN7 (((uint32_t)1U) << 4U) +#define CPG_MSTPSR9_I2C_IF0 (((uint32_t)1U) << 31U) +#define CPG_MSTPSR9_I2C_IF1 (((uint32_t)1U) << 30U) +#define CPG_MSTPSR9_I2C_IF2 (((uint32_t)1U) << 29U) +#define CPG_MSTPSR9_I2C_IF3 (((uint32_t)1U) << 28U) +#define CPG_MSTPSR9_I2C_IF4 (((uint32_t)1U) << 27U) +#define CPG_MSTPSR9_I2C_IF5 (((uint32_t)1U) << 19U) +#define CPG_MSTPSR9_RPC_IF (((uint32_t)1U) << 17U) +#define CPG_MSTPSR9_CAN_FD (((uint32_t)1U) << 14U) +#define CPG_MSTPSR9_GPIO0 (((uint32_t)1U) << 12U) +#define CPG_MSTPSR9_GPIO1 (((uint32_t)1U) << 11U) +#define CPG_MSTPSR9_GPIO2 (((uint32_t)1U) << 10U) +#define CPG_MSTPSR9_GPIO3 (((uint32_t)1U) << 9U) +#define CPG_MSTPSR9_GPIO4 (((uint32_t)1U) << 8U) +#define CPG_MSTPSR9_GPIO5 (((uint32_t)1U) << 7U) +#define CPG_MSTPSR9_SPIF (((uint32_t)1U) << 2U) +#define CPG_MSTPSR10_ACF0 (((uint32_t)1U) << 4U) +#define CPG_MSTPSR10_ACF1 (((uint32_t)1U) << 3U) +#define CPG_MSTPSR10_ACF2 (((uint32_t)1U) << 2U) +#define CPG_MSTPSR10_ACF3 (((uint32_t)1U) << 1U) +#define CPG_MSTPSR10_ACF4 (((uint32_t)1U) << 0U) + +/* define for ASTPOFFR register */ +#define IMP0_A_DISABLE (((uint32_t)1U) << 12U) +#define IMP1_A_DISABLE (((uint32_t)1U) << 13U) +#define IMP2_A_DISABLE (((uint32_t)1U) << 14U) +#define IMP3_A_DISABLE (((uint32_t)1U) << 15U) +#define IMP4_A_DISABLE (((uint32_t)1U) << 16U) +#define IMP5_A_DISABLE (((uint32_t)1U) << 17U) + +void cpg_init(void) +{ + uint32_t reg; + + /* Release CPG write protect */ + if((mem_read32(CPG_CPGWPCR) & CPGWPCR_WPE) != CPGWPCR_WPE_VALID) + { + mem_write32(CPG_CPGWPR, ~(uint32_t)(CPGWPCR_PASSWORD)); + mem_write32(CPG_CPGWPCR, CPGWPCR_PASSWORD); + + /* bit in WPE = 0? */ + while ((mem_read32(CPG_CPGWPCR) & CPGWPCR_WPE) != CPGWPCR_WPE_VALID) + { + ; + } + } + + /* Initialize CPG (Realtime) registers. */ + /* RMSTPCR0 not set */ + /* RMSTPCR1 */ + reg = mem_read32(CPG_RMSTPCR1); + reg &= ~(uint32_t)(CPG_MSTPSR1_TMU0 + | CPG_MSTPSR1_TMU4); + cpg_reg_write(CPG_RMSTPCR1, CPG_MSTPSR1, reg); + /* RMSTPCR2 not set */ + /* RMSTPCR3 */ + reg = mem_read32(CPG_RMSTPCR3); + reg &= ~(uint32_t)(CPG_MSTPSR3_CRC2 + | CPG_MSTPSR3_CRC0 + | CPG_MSTPSR3_CRC1 + | CPG_MSTPSR3_CMT1 + | CPG_MSTPSR3_CMT2); + cpg_reg_write(CPG_RMSTPCR3, CPG_MSTPSR3, reg); + /* RMSTPCR4 not set */ + /* RMSTPCR5 */ + reg = mem_read32(CPG_RMSTPCR5); + reg &= ~(uint32_t)(CPG_MSTPSR5_FLEXRAY); + reg |= (uint32_t)(CPG_MSTPSR5_IMP_OCV2 + | CPG_MSTPSR5_IMP_OCV3 + | CPG_MSTPSR5_IMP_OCV4 + | CPG_MSTPSR5_IMPDMA0 + | CPG_MSTPSR5_IMPDMA1 + | CPG_MSTPSR5_IMPPSC0 + | CPG_MSTPSR5_IMPPSC1 + | CPG_MSTPSR5_IMP4 + | CPG_MSTPSR5_SIMP); + cpg_reg_write(CPG_RMSTPCR5, CPG_MSTPSR5, reg); + /* RMSTPCR6 not set */ + /* RMSTPCR7 not set */ + /* RMSTPCR8 */ + reg = mem_read32(CPG_RMSTPCR8); + reg &= ~(uint32_t)(CPG_MSTPSR8_EAVB_IF); + reg |= (uint32_t)(CPG_MSTPSR8_IMPCNN + | CPG_MSTPSR8_IMPRAM + | CPG_MSTPSR8_IMP_OCV0 + | CPG_MSTPSR8_IMP_OCV1 + | CPG_MSTPSR8_IMP0 + | CPG_MSTPSR8_IMP1 + | CPG_MSTPSR8_IMP2 + | CPG_MSTPSR8_IMP3); + cpg_reg_write(CPG_RMSTPCR8, CPG_MSTPSR8, reg); + /* RMSTPCR9 */ + reg = mem_read32(CPG_RMSTPCR9); + reg &= ~(uint32_t)(CPG_MSTPSR9_CAN_FD); + cpg_reg_write(CPG_RMSTPCR9, CPG_MSTPSR9, reg); + /* RMSTPCR10 not set */ + /* RMSTPCR11 not set */ + + /* Initialize CPG (System) registers. */ + /* SMSTPCR0 not set */ + /* SMSTPCR1 */ + reg = mem_read32(CPG_SMSTPCR1); + reg &= ~(uint32_t)(CPG_MSTPSR1_IVCP1E + | CPG_MSTPSR1_TMU0); + cpg_reg_write(CPG_SMSTPCR1, CPG_MSTPSR1, reg); + /* SMSTPCR2 not set */ + /* SMSTPCR3 not set */ + /* SMSTPCR4 not set */ + /* SMSTPCR5 not set */ + /* SMSTPCR6 not set */ + /* SMSTPCR7 */ + reg = mem_read32(CPG_SMSTPCR7); + reg &= ~(uint32_t)(CPG_MSTPSR7_IMR_LX44 | CPG_MSTPSR7_IMR_LX45); + cpg_reg_write(CPG_SMSTPCR7, CPG_MSTPSR7, reg); + /* SMSTPCR8 not set */ + /* SMSTPCR9 not set */ + /* SMSTPCR10 not set */ + /* SMSTPCR11 not set */ + + /* Initialize CPG (SECURITY) registers. */ + /* SCMSTPCR0 not set */ + /* SCMSTPCR1 not set */ + /* SCMSTPCR2 not set */ + /* SCMSTPCR3 not set */ + /* SCMSTPCR4 not set */ + /* SCMSTPCR5 not set */ + /* SCMSTPCR6 not set */ + /* SCMSTPCR7 not set */ + /* SCMSTPCR8 not set */ + /* SCMSTPCR9 */ + reg = mem_read32(CPG_SCMSTPCR9); + reg &= ~(uint32_t)(CPG_MSTPSR9_RPC_IF); + cpg_reg_write(CPG_SCMSTPCR9, CPG_MSTPSR9, reg); + /* SCMSTPCR10 not set */ + /* SCMSTPCR11 not set */ + + /* Initialize CPG (SAFETY) registers. */ + /* SAMSTPCR0 not set */ + /* SAMSTPCR1 not set */ + /* SAMSTPCR2 not set */ + /* SAMSTPCR3 not set */ + /* SAMSTPCR4 not set */ + /* SAMSTPCR5 not set */ + /* SAMSTPCR6 not set */ + /* SAMSTPCR7 not set */ + /* SAMSTPCR8 not set */ + /* SAMSTPCR9 not set */ + /* SAMSTPCR10 not set */ + /* SAMSTPCR11 not set */ + + /* Disable automatic module clock stop function */ + reg = mem_read32(PRR); + if ((reg & PRR_CUT_MASK) < PRR_PRODUCT_20) { + reg = mem_read32(ASTPOFFR); + reg |= (IMP0_A_DISABLE | IMP1_A_DISABLE | IMP2_A_DISABLE | + IMP3_A_DISABLE | IMP4_A_DISABLE | IMP5_A_DISABLE); + mem_write32(ASTPOFFR, reg); + } +} +/* End of function cpg_init(void) */ + +void cpg_reg_write(uintptr_t mstpcr, uintptr_t mstpsr, uint32_t data) +{ + mem_write32(mstpcr, data); + while ((mem_read32(mstpsr) & ~(uint32_t)(data)) != 0U) + { + /* Loop to wait for confirmation that changes to "MSTPCRn" are reflected in "MSTPSRn". */ + } +} +/* End of function cpg_reg_write(uintptr_t mstpcr, uintptr_t mstpsr, uint32_t data) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram.c new file mode 100644 index 0000000..e3f797b --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram.c @@ -0,0 +1,4209 @@ +/* + * Copyright (c) 2015-2022, Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#include +#include +#include + +#include "ddr_regdef.h" +#include "init_dram_tbl_h3.h" +#include "init_dram_tbl_m3.h" +#include "init_dram_tbl_h3ver2.h" +#include "init_dram_tbl_m3n.h" +#include "boot_init_dram_regdef.h" +#include "boot_init_dram.h" +#include "dram_sub_func.h" +#include "micro_wait.h" + +#define DDR_BACKUPMODE +#define FATAL_MSG(x) NOTICE(x) + +/******************************************************************************* + * variables + ******************************************************************************/ +#ifdef RCAR_DDR_FIXED_LSI_TYPE +#ifndef RCAR_AUTO + #define RCAR_AUTO 99 + #define RCAR_H3 0 + #define RCAR_M3 1 + #define RCAR_M3N 2 + #define RCAR_E3 3 /* NON */ + #define RCAR_H3N 4 + + #define RCAR_CUT_10 0 + #define RCAR_CUT_11 1 + #define RCAR_CUT_20 10 + #define RCAR_CUT_30 20 +#endif +#ifndef RCAR_LSI + #define RCAR_LSI RCAR_AUTO +#endif +#if (RCAR_LSI == RCAR_AUTO) + static uint32_t Prr_Product; + static uint32_t Prr_Cut; +#else + #if (RCAR_LSI == RCAR_H3) + static const uint32_t Prr_Product = PRR_PRODUCT_H3; + #elif (RCAR_LSI == RCAR_M3) + static const uint32_t Prr_Product = PRR_PRODUCT_M3; + #elif (RCAR_LSI == RCAR_M3N) + static const uint32_t Prr_Product = PRR_PRODUCT_M3N; + #elif (RCAR_LSI == RCAR_H3N) + static const uint32_t Prr_Product = PRR_PRODUCT_H3; + #endif /* RCAR_LSI */ + + #ifndef RCAR_LSI_CUT + static uint32_t Prr_Cut; + #else /* RCAR_LSI_CUT */ + #if (RCAR_LSI_CUT == RCAR_CUT_10) + static const uint32_t Prr_Cut = PRR_PRODUCT_10; + #elif (RCAR_LSI_CUT == RCAR_CUT_11) + static const uint32_t Prr_Cut = PRR_PRODUCT_11; + #elif (RCAR_LSI_CUT == RCAR_CUT_20) + static const uint32_t Prr_Cut = PRR_PRODUCT_20; + #elif (RCAR_LSI_CUT == RCAR_CUT_30) + static const uint32_t Prr_Cut = PRR_PRODUCT_30; + #endif /* RCAR_LSI_CUT */ + #endif /* RCAR_LSI_CUT */ +#endif /* RCAR_AUTO_NON */ +#else /* RCAR_DDR_FIXED_LSI_TYPE */ + static uint32_t Prr_Product; + static uint32_t Prr_Cut; +#endif /* RCAR_DDR_FIXED_LSI_TYPE */ + +char *pRCAR_DDR_VERSION; +uint32_t _cnf_BOARDTYPE; +static const uint32_t *pDDR_REGDEF_TBL; +static uint32_t brd_clk; +static uint32_t brd_clkdiv; +static uint32_t brd_clkdiva; +static uint32_t ddr_mbps; +static uint32_t ddr_mbpsdiv; +static uint32_t ddr_tccd; +static uint32_t ddr_phycaslice; +static const struct _boardcnf *Boardcnf; +static uint32_t ddr_phyvalid; +static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; +static uint32_t ch_have_this_cs[CS_CNT]__attribute__ ((aligned(64))); +static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT*2][9]; +static uint32_t max_density; +static uint32_t ddr0800_mul; +static uint32_t ddr_mul; +static uint32_t DDR_PHY_SLICE_REGSET_OFS; +static uint32_t DDR_PHY_ADR_V_REGSET_OFS; +static uint32_t DDR_PHY_ADR_I_REGSET_OFS; +static uint32_t DDR_PHY_ADR_G_REGSET_OFS; +static uint32_t DDR_PI_REGSET_OFS; +static uint32_t DDR_PHY_SLICE_REGSET_SIZE; +static uint32_t DDR_PHY_ADR_V_REGSET_SIZE; +static uint32_t DDR_PHY_ADR_I_REGSET_SIZE; +static uint32_t DDR_PHY_ADR_G_REGSET_SIZE; +static uint32_t DDR_PI_REGSET_SIZE; +static uint32_t DDR_PHY_SLICE_REGSET_NUM; +static uint32_t DDR_PHY_ADR_V_REGSET_NUM; +static uint32_t DDR_PHY_ADR_I_REGSET_NUM; +static uint32_t DDR_PHY_ADR_G_REGSET_NUM; +static uint32_t DDR_PI_REGSET_NUM; +static uint32_t DDR_PHY_ADR_I_NUM; +#define DDR_PHY_REGSET_MAX 128 +#define DDR_PI_REGSET_MAX 320 +static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX]; +static uint32_t Pll3Mode; +static uint32_t loop_max; +#ifdef DDR_BACKUPMODE +uint32_t ddrBackup; +/* #define DDR_BACKUPMODE_HALF //for Half channel(ch0, 1 only) */ +#endif + +#ifdef ddr_qos_init_setting /* only for non qos_init */ +#define OPERATING_FREQ (400U) /* Mhz */ +#define BASE_SUB_SLOT_NUM (0x6U) +#define SUB_SLOT_CYCLE (0x7EU) /* 126 */ +#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ) /* unit:ns */ + +uint32_t get_refperiod(void) +{ + return (uint32_t)QOSWT_WTSET0_CYCLE; +} +#else /* ddr_qos_init_setting // only for non qos_init */ +extern uint32_t get_refperiod(void); +#endif /* ddr_qos_init_setting // only for non qos_init */ + +#define _reg_PHY_RX_CAL_X_NUM 11 +static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = { + _reg_PHY_RX_CAL_DQ0, + _reg_PHY_RX_CAL_DQ1, + _reg_PHY_RX_CAL_DQ2, + _reg_PHY_RX_CAL_DQ3, + _reg_PHY_RX_CAL_DQ4, + _reg_PHY_RX_CAL_DQ5, + _reg_PHY_RX_CAL_DQ6, + _reg_PHY_RX_CAL_DQ7, + _reg_PHY_RX_CAL_DM, + _reg_PHY_RX_CAL_DQS, + _reg_PHY_RX_CAL_FDBK +}; + +#define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10 +static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY[_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = { + _reg_PHY_CLK_WRDQ0_SLAVE_DELAY, + _reg_PHY_CLK_WRDQ1_SLAVE_DELAY, + _reg_PHY_CLK_WRDQ2_SLAVE_DELAY, + _reg_PHY_CLK_WRDQ3_SLAVE_DELAY, + _reg_PHY_CLK_WRDQ4_SLAVE_DELAY, + _reg_PHY_CLK_WRDQ5_SLAVE_DELAY, + _reg_PHY_CLK_WRDQ6_SLAVE_DELAY, + _reg_PHY_CLK_WRDQ7_SLAVE_DELAY, + _reg_PHY_CLK_WRDM_SLAVE_DELAY, + _reg_PHY_CLK_WRDQS_SLAVE_DELAY +}; + +#define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9 +static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = { + _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY, + _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY +}; + +#define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9 +static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = { + _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY, + _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY +}; + +#define _reg_PHY_PAD_TERM_X_NUM 8 +static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = { + _reg_PHY_PAD_FDBK_TERM, + _reg_PHY_PAD_DATA_TERM, + _reg_PHY_PAD_DQS_TERM, + _reg_PHY_PAD_ADDR_TERM, + _reg_PHY_PAD_CLK_TERM, + _reg_PHY_PAD_CKE_TERM, + _reg_PHY_PAD_RST_TERM, + _reg_PHY_PAD_CS_TERM +}; + +#define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10 +static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X[_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = { + _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY, + _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY, + _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY, + _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY, + _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY, + _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY, + + _reg_PHY_GRP_SLAVE_DELAY_0, + _reg_PHY_GRP_SLAVE_DELAY_1, + _reg_PHY_GRP_SLAVE_DELAY_2, + _reg_PHY_GRP_SLAVE_DELAY_3 +}; + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static inline uint32_t vch_nxt(uint32_t pos); +static void cpg_write_32(uint32_t a, uint32_t v); +static void pll3_control(uint32_t high); +static inline void dsb_sev(void); +static void wait_dbcmd(void); +static void send_dbcmd(uint32_t cmd); +static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd); +static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata); +static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata); +static inline uint32_t ddr_regdef(uint32_t _regdef); +static inline uint32_t ddr_regdef_adr(uint32_t _regdef); +static inline uint32_t ddr_regdef_lsb(uint32_t _regdef); +static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, uint32_t val); +static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef); +static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val); +static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); +static void ddr_setval_ach(uint32_t regdef, uint32_t val); +static void ddr_setval_ach_as(uint32_t regdef, uint32_t val); +static uint32_t ddr_getval(uint32_t ch, uint32_t regdef); +static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p); +static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p); +static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size); +static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val); +static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef); +static uint32_t ddrphy_regif_chk(void); +static inline void ddrphy_regif_idle(void); +static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps, uint16_t cyc); +static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint16_t *js2); +static int16_t _f_scale_adj(int16_t ps); +static void ddrtbl_load(void); +static void ddr_config_sub(void); +static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz); +static void ddr_config_sub_h3v1x(void); +static void ddr_config(void); +static void dbsc_regset(void); +static void dbsc_regset_post(void); +static uint32_t dfi_init_start(void); +static void change_lpddr4_en(uint32_t mode); +static uint32_t set_term_code(void); +static void ddr_register_set(void); +static inline uint32_t wait_freqchgreq(uint32_t assert); +static inline void set_freqchgack(uint32_t assert); +static inline void set_dfifrequency(uint32_t freq); +static uint32_t pll3_freq(uint32_t on); +static void update_dly(void); +static uint32_t pi_training_go(void); +static uint32_t init_ddr(void); +static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick); +static uint32_t wdqdm_man1(void); +static uint32_t wdqdm_man(void); +static uint32_t rdqdm_man1(void); +static uint32_t rdqdm_man(void); + +static int32_t _find_change(uint64_t val, uint32_t dir); +static uint32_t _rx_offset_cal_updn(uint32_t code); +static uint32_t rx_offset_cal(void); +static uint32_t rx_offset_cal_hw(void); +static void adjust_rddqs_latency(void); +static void adjust_wpath_latency(void); + +struct DdrtData { + int32_t init_temp; /* Initial Temperature (do) */ + uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */ + uint32_t tcomp_cal[4]; /* Temperature compensated io-code (4 is for H3) */ +}; +struct DdrtData tcal; + +static void pvtcode_update(void); +static void pvtcode_update2(void); +static void ddr_padcal_tcompensate_getinit(uint32_t override); + +/******************************************************************************* + * load board configuration + ******************************************************************************/ +#include "boot_init_dram_config.c" + +#ifndef DDR_FAST_INIT +static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; +static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; +static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9]; +static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; +static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2]; +static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn); +static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn); + +static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; +static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; +static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9]; +static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; +static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; +static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn); +static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn); +#endif /* DDR_FAST_INIT */ + +/******************************************************************************* + * macro for channel selection loop + ******************************************************************************/ +static inline uint32_t vch_nxt(uint32_t pos) +{ + uint32_t posn; + + for (posn = pos; posn < DRAM_CH_CNT; posn++) { + if (ddr_phyvalid & (1U << posn)) + break; + } + return posn; +} + +#define foreach_vch(ch) \ +for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1)) + +#define foreach_ech(ch) \ +for (ch = 0; ch < DRAM_CH_CNT; ch++) + +/******************************************************************************* + * Printing functions + ******************************************************************************/ +#define MSG_LF(...) + +/******************************************************************************* + * clock settings, reset control + ******************************************************************************/ +static void cpg_write_32(uint32_t a, uint32_t v) +{ + mmio_write_32(CPG_CPGWPR, ~v); + mmio_write_32(a, v); +} + +static void pll3_control(uint32_t high) +{ + uint32_t dataL, dataDIV, dataMUL, tmpDIV; + + if (high) { + tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) / (brd_clk * ddr_mul) / 2; + dataMUL = (((ddr_mul * tmpDIV) - 1) << 24); + Pll3Mode = 1; + loop_max = 2; + } else { + tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) / (brd_clk * ddr0800_mul) / 2; + dataMUL = (((ddr0800_mul * tmpDIV) - 1) << 24); + Pll3Mode = 0; + loop_max = 8; + } + switch (tmpDIV) { + case 1: + dataDIV = 0; + break; + case 2: + dataDIV = 2; + break; + case 3: + dataDIV = 3; + break; + case 4: + dataDIV = 4; + break; + default: + dataDIV = 6; + dataMUL = (dataMUL * tmpDIV) / 3; + break; + } + dataMUL = dataMUL | (brd_clkdiva << 7); + + /* PLL3 disable */ + dataL = (~CPG_PLLECR_PLL3E_BIT) & mmio_read_32(CPG_PLLECR); + cpg_write_32(CPG_PLLECR, dataL); + (void)mmio_read_32(CPG_PLLECR); + dsb_sev(); + + if ((Prr_Product == PRR_PRODUCT_M3) || ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_20))) { + /* PLL3 DIV resetting(Lowest value:3) */ + dataL = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + cpg_write_32(CPG_FRQCRD, dataL); + dsb_sev(); + + /* zb3 clk stop */ + dataL = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR); + cpg_write_32(CPG_ZB3CKCR, dataL); + dsb_sev(); + + /* PLL3 enable */ + dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); + cpg_write_32(CPG_PLLECR, dataL); + dsb_sev(); + + do { + dataL = mmio_read_32(CPG_PLLECR); + } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); + dsb_sev(); + + /* PLL3 DIV resetting (Highest value:0) */ + dataL = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + cpg_write_32(CPG_FRQCRD, dataL); + dsb_sev(); + + /* DIV SET KICK */ + dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); + cpg_write_32(CPG_FRQCRB, dataL); + dsb_sev(); + + /* PLL3 multiplie set */ + cpg_write_32(CPG_PLL3CR, dataMUL); + dsb_sev(); + + do { + dataL = mmio_read_32(CPG_PLLECR); + } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); + dsb_sev(); + + /* PLL3 DIV resetting(Target value) */ + dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + cpg_write_32(CPG_FRQCRD, dataL); + dsb_sev(); + + /* DIV SET KICK */ + dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); + cpg_write_32(CPG_FRQCRB, dataL); + dsb_sev(); + + do { + dataL = mmio_read_32(CPG_PLLECR); + } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); + dsb_sev(); + + /* zb3 clk start */ + dataL = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR); + cpg_write_32(CPG_ZB3CKCR, dataL); + dsb_sev(); + + } else { /* H3Ver.3.0/M3N/V3H */ + + /* PLL3 multiplie set */ + cpg_write_32(CPG_PLL3CR, dataMUL); + (void)mmio_read_32(CPG_PLL3CR); + dsb_sev(); + + /* PLL3 DIV set(Target value) */ + dataL = (dataDIV << 16) | dataDIV | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD)); + cpg_write_32(CPG_FRQCRD, dataL); + + /* DIV SET KICK */ + dataL = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB); + cpg_write_32(CPG_FRQCRB, dataL); + (void)mmio_read_32(CPG_FRQCRB); + dsb_sev(); + + /* PLL3 enable */ + dataL = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR); + cpg_write_32(CPG_PLLECR, dataL); + (void)mmio_read_32(CPG_PLLECR); + dsb_sev(); + + do { + dataL = mmio_read_32(CPG_PLLECR); + } while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0); + (void)mmio_read_32(CPG_PLLECR); + dsb_sev(); + } +} + +/******************************************************************************* + * barrier + ******************************************************************************/ +static inline void dsb_sev(void) +{ +#if defined(__RH850G3K__) + __asm__ __volatile__ ("SYNCP"); +#else + __asm__ __volatile__ ("dsb sy"); +#endif +} + +/******************************************************************************* + * DDR memory register access + ******************************************************************************/ +static void wait_dbcmd(void) +{ + uint32_t dataL; + + /* dummy read */ + dataL = mmio_read_32(DBSC_DBCMD); + dsb_sev(); + while (1) { + /* wait DBCMD 1 = busy, 0 = ready */ + dataL = mmio_read_32(DBSC_DBWAIT); + dsb_sev(); + if ((dataL & 0x00000001) == 0x00) + break; + } +} + +static void send_dbcmd(uint32_t cmd) +{ + /* dummy read */ + wait_dbcmd(); + mmio_write_32(DBSC_DBCMD, cmd); + (void)mmio_read_32(DBSC_DBCMD); + dsb_sev(); +} + +static void dbwait_loop(uint32_t wait_loop) +{ + uint32_t i; + + for (i = 0; wait_loop> i; i++) + wait_dbcmd(); +} + +/******************************************************************************* + * DDRPHY register access (raw) + ******************************************************************************/ +static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd) +{ + uint32_t val; + uint32_t loop; + + val = 0; + if ((Prr_Product != PRR_PRODUCT_M3N) && (Prr_Product != PRR_PRODUCT_V3H)) { + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + dsb_sev(); + + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + dsb_sev(); + dsb_sev(); + + for (loop = 0; loop < loop_max; loop++) { + val = mmio_read_32(DBSC_DBPDRGD(phyno)); + dsb_sev(); + } + (void)val; + } else { + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00004000); + (void)mmio_read_32(DBSC_DBPDRGA(phyno)); + dsb_sev(); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x0000C000)) + dsb_sev(); + val = mmio_read_32(DBSC_DBPDRGA(phyno)); + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + dsb_sev(); + dsb_sev(); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + dsb_sev(); + + dsb_sev(); + val = mmio_read_32(DBSC_DBPDRGD(phyno)); + dsb_sev(); + (void)val; + } + return val; +} + +static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) +{ + uint32_t val; + uint32_t loop; + + if ((Prr_Product != PRR_PRODUCT_M3N) && (Prr_Product != PRR_PRODUCT_V3H)) { + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + dsb_sev(); + for (loop = 0; loop < loop_max; loop++) { + val = mmio_read_32(DBSC_DBPDRGA(phyno)); + dsb_sev(); + } + mmio_write_32(DBSC_DBPDRGD(phyno), regdata); + dsb_sev(); + + for (loop = 0; loop < loop_max; loop++) { + val = mmio_read_32(DBSC_DBPDRGD(phyno)); + dsb_sev(); + } + } else { + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + (void)mmio_read_32(DBSC_DBPDRGA(phyno)); + dsb_sev(); + + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + dsb_sev(); + dsb_sev(); + + mmio_write_32(DBSC_DBPDRGD(phyno), regdata); + (void)mmio_read_32(DBSC_DBPDRGD(phyno)); + dsb_sev(); + + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x00008000)) + dsb_sev(); + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000); + + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + dsb_sev(); + dsb_sev(); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + } + (void)val; +} + +static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) +{ + uint32_t ch; + uint32_t val; + uint32_t loop; + + if ((Prr_Product != PRR_PRODUCT_M3N) && (Prr_Product != PRR_PRODUCT_V3H)) { + foreach_vch(ch) { + mmio_write_32(DBSC_DBPDRGA(ch), regadd); + dsb_sev(); + } + + foreach_vch(ch) { + mmio_write_32(DBSC_DBPDRGD(ch), regdata); + dsb_sev(); + } + + for (loop = 0; loop < loop_max; loop++) { + val = mmio_read_32(DBSC_DBPDRGD(0)); + dsb_sev(); + } + (void)val; + } else { + foreach_vch(ch) { + reg_ddrphy_write(ch, regadd, regdata); + dsb_sev(); + } + } +} + +static inline void ddrphy_regif_idle(void) +{ + uint32_t val; + + val = reg_ddrphy_read(0, ddr_regdef_adr(_reg_PI_INT_STATUS)); + dsb_sev(); + (void)val; +} + +/******************************************************************************* + * DDRPHY register access (field modify) + ******************************************************************************/ +static inline uint32_t ddr_regdef(uint32_t _regdef) +{ + return pDDR_REGDEF_TBL[_regdef]; +} + +static inline uint32_t ddr_regdef_adr(uint32_t _regdef) +{ + return DDR_REGDEF_ADR(pDDR_REGDEF_TBL[_regdef]); +} + +static inline uint32_t ddr_regdef_lsb(uint32_t _regdef) +{ + return DDR_REGDEF_LSB(pDDR_REGDEF_TBL[_regdef]); +} + +static inline uint32_t ddr_regdef_len(uint32_t _regdef) +{ + return DDR_REGDEF_LEN(pDDR_REGDEF_TBL[_regdef]); +} + +static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + uint32_t regdef; + + regdef = ddr_regdef(_regdef); + adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20) + msk = 0xffffffff; + else + msk = ((1U << len) - 1) << lsb; + + tmp = reg_ddrphy_read(ch, adr); + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + reg_ddrphy_write(ch, adr, tmp); +} + +static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + uint32_t regdef; + + regdef = ddr_regdef(_regdef); + adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice; + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20) + msk = 0xffffffff; + else + msk = ((1U << len) - 1); + + tmp = reg_ddrphy_read(ch, adr); + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) +{ + ddr_setval_s(ch, 0, regdef, val); +} + +static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val) +{ + uint32_t ch; + + foreach_vch(ch) + ddr_setval_s(ch, slice, regdef, val); +} + +static void ddr_setval_ach(uint32_t regdef, uint32_t val) +{ + ddr_setval_ach_s(0, regdef, val); +} + +static void ddr_setval_ach_as(uint32_t regdef, uint32_t val) +{ + uint32_t slice; + + for (slice = 0; slice < SLICE_CNT; slice++) + ddr_setval_ach_s(slice, regdef, val); +} + +static uint32_t ddr_getval(uint32_t ch, uint32_t regdef) +{ + return ddr_getval_s(ch, 0, regdef); +} + +static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p) +{ + uint32_t ch; + + foreach_vch(ch) + p[ch] = ddr_getval_s(ch, 0, regdef); + return p[0]; +} + +static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p) +{ + uint32_t ch, slice; + uint32_t *pp; + + pp = p; + foreach_vch(ch) + for (slice = 0; slice < SLICE_CNT; slice++) + *pp++ = ddr_getval_s(ch, slice, regdef); + return p[0]; +} + +/******************************************************************************* + * handling functions for setteing ddrphy value table + ******************************************************************************/ +static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size) +{ + uint32_t i; + + for (i = 0; i < size; i++) + to[i] = from[i]; +} + +static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + uint32_t adrmsk; + uint32_t regdef; + + regdef = ddr_regdef(_regdef); + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20) + msk = 0xffffffff; + else + msk = ((1U << len) - 1) << lsb; + + if (adr < 0x400) + adrmsk = 0xff; + else + adrmsk = 0x7f; + + tmp = tbl[adr & adrmsk]; + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + tbl[adr & adrmsk] = tmp; +} + +static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + uint32_t adrmsk; + uint32_t regdef; + + regdef = ddr_regdef(_regdef); + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20) + msk = 0xffffffff; + else + msk = ((1U << len) - 1); + + if (adr < 0x400) + adrmsk = 0xff; + else + adrmsk = 0x7f; + + tmp = tbl[adr & adrmsk]; + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +/******************************************************************************* + * DDRPHY register access handling + ******************************************************************************/ +static uint32_t ddrphy_regif_chk(void) +{ + uint32_t tmp_ach[DRAM_CH_CNT]; + uint32_t ch; + uint32_t err; + uint32_t PI_VERSION_CODE; + + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + || (Prr_Product == PRR_PRODUCT_M3)) + PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */ + else + PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */ + + ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach); + err = 0; + foreach_vch(ch) { + if (tmp_ach[ch] != PI_VERSION_CODE) + err = 1; + } + return err; +} + +/******************************************************************************* + * functions and parameters for timing setting + ******************************************************************************/ +struct _jedec_spec1 { + uint16_t fx3; + uint8_t RLwoDBI; + uint8_t RLwDBI; + uint8_t WL; + uint8_t nWR; + uint8_t nRTP; + uint8_t ODTLon; + uint8_t MR1; + uint8_t MR2; +}; +#define JS1_USABLEC_SPEC_LO 2 +#define JS1_USABLEC_SPEC_HI 5 +#define JS1_FREQ_TBL_NUM 8 +#define JS1_MR1(f) (0x04 | ((f) << 4)) +#define JS1_MR2(f) (0x00 | ((f) << 3) | (f)) +const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { + { 800, 6, 6, 4, 6, 8, 0, JS1_MR1(0), JS1_MR2(0)|0x40 }, /* 533.333Mbps */ + { 1600, 10, 12, 8, 10, 8, 0, JS1_MR1(1), JS1_MR2(1)|0x40 }, /* 1066.666Mbps */ + { 2400, 14, 16, 12, 16, 8, 6, JS1_MR1(2), JS1_MR2(2)|0x40 }, /* 1600.000Mbps */ + { 3200, 20, 22, 10, 20, 8, 4, JS1_MR1(3), JS1_MR2(3) }, /* 2133.333Mbps */ + { 4000, 24, 28, 12, 24, 10, 4, JS1_MR1(4), JS1_MR2(4) }, /* 2666.666Mbps */ + { 4800, 28, 32, 14, 30, 12, 6, JS1_MR1(5), JS1_MR2(5) }, /* 3200.000Mbps */ + { 5600, 32, 36, 16, 34, 14, 6, JS1_MR1(6), JS1_MR2(6) }, /* 3733.333Mbps */ + { 6400, 36, 40, 18, 40, 16, 8, JS1_MR1(7), JS1_MR2(7) } /* 4266.666Mbps */ +}; + +struct _jedec_spec2 { + uint16_t ps; + uint16_t cyc; +}; + +#define JS2_tSR 0 +#define JS2_tXP 1 +#define JS2_tRTP 2 +#define JS2_tRCD 3 +#define JS2_tRPpb 4 +#define JS2_tRPab 5 +#define JS2_tRAS 6 +#define JS2_tWR 7 +#define JS2_tWTR 8 +#define JS2_tRRD 9 +#define JS2_tPPD 10 +#define JS2_tFAW 11 +#define JS2_tDQSCK 12 +#define JS2_tCKEHCMD 13 +#define JS2_tCKELCMD 14 +#define JS2_tCKELPD 15 +#define JS2_tMRR 16 +#define JS2_tMRW 17 +#define JS2_tMRD 18 +#define JS2_tZQCALns 19 +#define JS2_tZQLAT 20 +#define JS2_tIEdly 21 +#define JS2_tODTon_min 22 +#define JS2_TBLCNT 23 + +#define JS2_tRCpb (JS2_TBLCNT) +#define JS2_tRCab (JS2_TBLCNT + 1) +#define JS2_tRFCab (JS2_TBLCNT + 2) +#define JS2_CNT (JS2_TBLCNT + 3) + +#ifndef JS2_DERATE +#define JS2_DERATE 0 +#endif +const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { + { +/*tSR */ { 15000, 3 }, +/*tXP */ { 7500, 3 }, +/*tRTP */ { 7500, 8 }, +/*tRCD */ { 18000, 4 }, +/*tRPpb */ { 18000, 3 }, +/*tRPab */ { 21000, 3 }, +/*tRAS */ { 42000, 3 }, +/*tWR */ { 18000, 4 }, +/*tWTR */ { 10000, 8 }, +/*tRRD */ { 10000, 4 }, +/*tPPD */ { 0, 0 }, +/*tFAW */ { 40000, 0 }, +/*tDQSCK*/ { 3500, 0 }, +/*tCKEHCMD*/ { 7500, 3 }, +/*tCKELCMD*/ { 7500, 3 }, +/*tCKELPD*/ { 7500, 3 }, +/*tMRR*/ { 0, 8 }, +/*tMRW*/ { 10000, 10 }, +/*tMRD*/ { 14000, 10 }, +/*tZQCALns*/ {1000*10, 0 }, +/*tZQLAT*/ { 30000, 10 }, +/*tIEdly*/ { 12500, 0 }, +/*tODTon_min*/ { 1500, 0 } + }, { +/*tSR */ { 15000, 3 }, +/*tXP */ { 7500, 3 }, +/*tRTP */ { 7500, 8 }, +/*tRCD */ { 19875, 4 }, +/*tRPpb */ { 19875, 3 }, +/*tRPab */ { 22875, 3 }, +/*tRAS */ { 43875, 3 }, +/*tWR */ { 18000, 4 }, +/*tWTR */ { 10000, 8 }, +/*tRRD */ { 11875, 4 }, +/*tPPD */ { 0, 0 }, +/*tFAW */ { 40000, 0 }, +/*tDQSCK*/ { 3600, 0 }, +/*tCKEHCMD*/ { 7500, 3 }, +/*tCKELCMD*/ { 7500, 3 }, +/*tCKELPD*/ { 7500, 3 }, +/*tMRR*/ { 0, 8 }, +/*tMRW*/ { 10000, 10 }, +/*tMRD*/ { 14000, 10 }, +/*tZQCALns*/ {1000*10, 0 }, +/*tZQLAT*/ { 30000, 10 }, +/*tIEdly*/ { 12500, 0 }, +/*tODTon_min*/ { 1500, 0 } + } +}; + +const uint16_t jedec_spec2_tRFC_ab[7] = { +/* 4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non) */ + 130, 180, 180, 280, 280, 560, 560 +}; + +static uint32_t js1_ind; +static uint16_t js2[JS2_CNT]; +static uint8_t RL; +static uint8_t WL; + +static uint16_t _f_scale(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint32_t ps, uint16_t cyc) +{ + uint32_t tmp; + uint32_t div; + + tmp = (((uint32_t)(ps) + 9) / 10) * ddr_mbps; + div = tmp / (200000 * ddr_mbpsdiv); + if (tmp != (div * 200000 * ddr_mbpsdiv)) + div = div + 1; + + if (div > cyc) + return (uint16_t)div; + return cyc; +} + +static void _f_scale_js2(uint32_t ddr_mbps, uint32_t ddr_mbpsdiv, uint16_t *js2) +{ + int i; + + for (i = 0; i < JS2_TBLCNT; i++) { + js2[i] = _f_scale(ddr_mbps, ddr_mbpsdiv, + 1UL*jedec_spec2[JS2_DERATE][i].ps, + jedec_spec2[JS2_DERATE][i].cyc); + } + + js2[JS2_tRCpb] = js2[JS2_tRAS] + js2[JS2_tRPpb]; + js2[JS2_tRCab] = js2[JS2_tRAS] + js2[JS2_tRPab]; +} + +/* scaler for DELAY value */ +static int16_t _f_scale_adj(int16_t ps) +{ + int32_t tmp; + + tmp = (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps / (int32_t)ddr_mbpsdiv; + tmp = (int32_t)tmp / (int32_t)15625; + + return (int16_t)tmp; +} + +const uint32_t _reg_PI_MR1_DATA_Fx_CSx[2][CSAB_CNT] = { + { + _reg_PI_MR1_DATA_F0_0, + _reg_PI_MR1_DATA_F0_1, + _reg_PI_MR1_DATA_F0_2, + _reg_PI_MR1_DATA_F0_3 + }, + { + _reg_PI_MR1_DATA_F1_0, + _reg_PI_MR1_DATA_F1_1, + _reg_PI_MR1_DATA_F1_2, + _reg_PI_MR1_DATA_F1_3 + } +}; + +const uint32_t _reg_PI_MR2_DATA_Fx_CSx[2][CSAB_CNT] = { + { + _reg_PI_MR2_DATA_F0_0, + _reg_PI_MR2_DATA_F0_1, + _reg_PI_MR2_DATA_F0_2, + _reg_PI_MR2_DATA_F0_3 + }, + { + _reg_PI_MR2_DATA_F1_0, + _reg_PI_MR2_DATA_F1_1, + _reg_PI_MR2_DATA_F1_2, + _reg_PI_MR2_DATA_F1_3 + } +}; + +const uint32_t _reg_PI_MR3_DATA_Fx_CSx[2][CSAB_CNT] = { + { + _reg_PI_MR3_DATA_F0_0, + _reg_PI_MR3_DATA_F0_1, + _reg_PI_MR3_DATA_F0_2, + _reg_PI_MR3_DATA_F0_3 + }, + { + _reg_PI_MR3_DATA_F1_0, + _reg_PI_MR3_DATA_F1_1, + _reg_PI_MR3_DATA_F1_2, + _reg_PI_MR3_DATA_F1_3 + } +}; + +const uint32_t _reg_PI_MR11_DATA_Fx_CSx[2][CSAB_CNT] = { + { + _reg_PI_MR11_DATA_F0_0, + _reg_PI_MR11_DATA_F0_1, + _reg_PI_MR11_DATA_F0_2, + _reg_PI_MR11_DATA_F0_3 + }, + { + _reg_PI_MR11_DATA_F1_0, + _reg_PI_MR11_DATA_F1_1, + _reg_PI_MR11_DATA_F1_2, + _reg_PI_MR11_DATA_F1_3 + } +}; + +const uint32_t _reg_PI_MR12_DATA_Fx_CSx[2][CSAB_CNT] = { + { + _reg_PI_MR12_DATA_F0_0, + _reg_PI_MR12_DATA_F0_1, + _reg_PI_MR12_DATA_F0_2, + _reg_PI_MR12_DATA_F0_3 + }, + { + _reg_PI_MR12_DATA_F1_0, + _reg_PI_MR12_DATA_F1_1, + _reg_PI_MR12_DATA_F1_2, + _reg_PI_MR12_DATA_F1_3 + } +}; + +const uint32_t _reg_PI_MR14_DATA_Fx_CSx[2][CSAB_CNT] = { + { + _reg_PI_MR14_DATA_F0_0, + _reg_PI_MR14_DATA_F0_1, + _reg_PI_MR14_DATA_F0_2, + _reg_PI_MR14_DATA_F0_3 + }, + { + _reg_PI_MR14_DATA_F1_0, + _reg_PI_MR14_DATA_F1_1, + _reg_PI_MR14_DATA_F1_2, + _reg_PI_MR14_DATA_F1_3 + } +}; + +/******************************************************************************* + * regif pll w/a ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA ) + *******************************************************************************/ +static void regif_pll_wa(void) +{ + uint32_t ch; + + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + /* PLL setting for PHY : H3 Ver.1.x */ + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), (0x0064U << ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), + ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL)); + + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), + ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_PLL_CTRL)); + + } else { + /* PLL setting for PHY : M3-W/M3-N/V3H/H3 Ver.2.0 or later */ + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT), (0x5064U << ddr_regdef_lsb(_reg_PHY_PLL_WAIT))); + + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), + (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL_TOP) << 16) | + ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL)); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), + ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL_CA)); + + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL), + (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) | + ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_PLL_CTRL)); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_TOP_PLL_CTRL), + ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_TOP_PLL_CTRL)); + if (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_LOW_FREQ_SEL)) { + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_LOW_FREQ_SEL), + _cnf_DDR_PHY_ADR_G_REGSET[0x7f & ddr_regdef_adr(_reg_PHY_LP4_BOOT_LOW_FREQ_SEL)]); + } + } + + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS), + _cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS]); + + /* protect register interface */ + ddrphy_regif_idle(); + pll3_control(0); + + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + /* non */ + } else { + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN), (0x01U << ddr_regdef_lsb(_reg_PHY_DLL_RST_EN))); + ddrphy_regif_idle(); + } + + /*********************************************************************** + * init start + ***********************************************************************/ + /* dbdficnt0: + * dfi_dram_clk_disable = 1 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start = 0 + */ + foreach_vch(ch) + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); + (void)mmio_read_32(DBSC_DBDFICNT(ch)); + dsb_sev(); + + /* dbdficnt0: + * dfi_dram_clk_disable = 1 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start = 1 + */ + foreach_vch(ch) + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); + (void)mmio_read_32(DBSC_DBDFICNT(ch)); + dsb_sev(); + + foreach_ech(ch) + if (((Boardcnf->phyvalid) & (1U << ch))) + while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f) + ; + dsb_sev(); +} + +/******************************************************************************* + * load table data into DDR registers + ******************************************************************************/ +static void ddrtbl_load(void) +{ + uint32_t i; + uint32_t slice; + uint32_t csab; + uint32_t adr; + uint32_t dataL; + uint32_t tmp[3]; + uint16_t dataS; + + /*********************************************************************** + * TIMING REGISTERS + ***********************************************************************/ + /* search jedec_spec1 index */ + for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) { + if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) + break; + } + if (i > JS1_USABLEC_SPEC_HI) + js1_ind = JS1_USABLEC_SPEC_HI; + else + js1_ind = i; + + if (Boardcnf->dbi_en) + RL = js1[js1_ind].RLwDBI; + else + RL = js1[js1_ind].RLwoDBI; + + WL = js1[js1_ind].WL; + + /* calculate jedec_spec2 */ + _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); + + /*********************************************************************** + * PREPARE TBL + ***********************************************************************/ + if (Prr_Product == PRR_PRODUCT_H3) { + if (Prr_Cut <= PRR_PRODUCT_11) { + /* H3 Ver.1.x */ + _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, + DDR_PHY_SLICE_REGSET_H3, DDR_PHY_SLICE_REGSET_NUM_H3); + _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, + DDR_PHY_ADR_V_REGSET_H3, DDR_PHY_ADR_V_REGSET_NUM_H3); + _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, + DDR_PHY_ADR_I_REGSET_H3, DDR_PHY_ADR_I_REGSET_NUM_H3); + _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, + DDR_PHY_ADR_G_REGSET_H3, DDR_PHY_ADR_G_REGSET_NUM_H3); + _tblcopy(_cnf_DDR_PI_REGSET, + DDR_PI_REGSET_H3, DDR_PI_REGSET_NUM_H3); + + DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_H3; + DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_H3; + DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_H3; + DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_H3; + DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3; + DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_H3; + DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_H3; + DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_H3; + DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_H3; + DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3; + DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_H3; + DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_H3; + DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_H3; + DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_H3; + DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3; + + DDR_PHY_ADR_I_NUM = 1; + } else { + /* H3 Ver.2.0 or later */ + _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, + DDR_PHY_SLICE_REGSET_H3VER2, DDR_PHY_SLICE_REGSET_NUM_H3VER2); + _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, + DDR_PHY_ADR_V_REGSET_H3VER2, DDR_PHY_ADR_V_REGSET_NUM_H3VER2); + _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, + DDR_PHY_ADR_G_REGSET_H3VER2, DDR_PHY_ADR_G_REGSET_NUM_H3VER2); + _tblcopy(_cnf_DDR_PI_REGSET, + DDR_PI_REGSET_H3VER2, DDR_PI_REGSET_NUM_H3VER2); + + DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_H3VER2; + DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_H3VER2; + DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_H3VER2; + DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3VER2; + DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_H3VER2; + DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_H3VER2; + DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_H3VER2; + DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3VER2; + DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_H3VER2; + DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_H3VER2; + DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_H3VER2; + DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3VER2; + + DDR_PHY_ADR_I_NUM = 0; + } + } else if (Prr_Product == PRR_PRODUCT_M3) { + /* M3-W */ + _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, + DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3); + _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, + DDR_PHY_ADR_V_REGSET_M3, DDR_PHY_ADR_V_REGSET_NUM_M3); + _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, + DDR_PHY_ADR_I_REGSET_M3, DDR_PHY_ADR_I_REGSET_NUM_M3); + _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, + DDR_PHY_ADR_G_REGSET_M3, DDR_PHY_ADR_G_REGSET_NUM_M3); + _tblcopy(_cnf_DDR_PI_REGSET, + DDR_PI_REGSET_M3, DDR_PI_REGSET_NUM_M3); + + DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3; + DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3; + DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3; + DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3; + DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3; + DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3; + DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3; + DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3; + DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3; + DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3; + DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3; + DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3; + DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3; + DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3; + DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3; + + DDR_PHY_ADR_I_NUM = 2; + } else { + /* M3-N/V3H */ + _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, + DDR_PHY_SLICE_REGSET_M3N, DDR_PHY_SLICE_REGSET_NUM_M3N); + _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, + DDR_PHY_ADR_V_REGSET_M3N, DDR_PHY_ADR_V_REGSET_NUM_M3N); + _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, + DDR_PHY_ADR_I_REGSET_M3N, DDR_PHY_ADR_I_REGSET_NUM_M3N); + _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, + DDR_PHY_ADR_G_REGSET_M3N, DDR_PHY_ADR_G_REGSET_NUM_M3N); + _tblcopy(_cnf_DDR_PI_REGSET, + DDR_PI_REGSET_M3N, DDR_PI_REGSET_NUM_M3N); + + DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3N; + DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3N; + DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3N; + DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3N; + DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3N; + DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3N; + DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3N; + DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3N; + DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3N; + DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3N; + DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3N; + DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3N; + DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3N; + DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3N; + DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3N; + + DDR_PHY_ADR_I_NUM = 2; + } + + /*********************************************************************** + * PLL CODE CHANGE + ***********************************************************************/ + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) { + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL, 0x1142); + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_LP4_BOOT_PLL_CTRL, 0x1142); + } + + /*********************************************************************** + * on fly gate adjust + ***********************************************************************/ + if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10)) + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_ON_FLY_GATE_ADJUST_EN, 0x00); + + /*********************************************************************** + * Adjust PI parameters + ***********************************************************************/ +#ifdef _def_LPDDR4_ODT + for (i = 0; i < 2; i++) { + for (csab = 0; csab < CSAB_CNT; csab++) + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_Fx_CSx[i][csab], _def_LPDDR4_ODT); + } +#endif /* _def_LPDDR4_ODT */ + +#ifdef _def_LPDDR4_VREFCA + for (i = 0; i < 2; i++) { + for (csab = 0; csab < CSAB_CNT; csab++) + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_Fx_CSx[i][csab], _def_LPDDR4_VREFCA); + } +#endif /* _def_LPDDR4_VREFCA */ + if ((Prr_Product == PRR_PRODUCT_M3N) || (Prr_Product == PRR_PRODUCT_V3H)) { + js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U; + if (js2[JS2_tIEdly] > (RL)) + js2[JS2_tIEdly] = RL; + } else if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) { + js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U; + } else if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0); + } + + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) + || (Prr_Product == PRR_PRODUCT_M3N) || (Prr_Product == PRR_PRODUCT_V3H)) { + if ((js2[JS2_tIEdly]) >= 0x1e) + dataS = 0x1e; + else + dataS = js2[JS2_tIEdly]; + } else { + if ((js2[JS2_tIEdly]) >= 0x0e) + dataS = 0x0e; + else + dataS = js2[JS2_tIEdly]; + } + + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS); + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY, (dataS - 2)); + if ((Prr_Product == PRR_PRODUCT_M3N) || (Prr_Product == PRR_PRODUCT_V3H)) + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_OE_DLY, (dataS - 2)); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS); + + if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) + dataL = WL - 1; + else + dataL = WL; + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, dataL - 2); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, dataL); + + if (Boardcnf->dbi_en) { + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, 0x01); + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WDQLVL_DATADM_MASK, 0x000); + } else { + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE, 0x00); + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WDQLVL_DATADM_MASK, 0x100); + } + + tmp[0] = js1[js1_ind].MR1; + tmp[1] = js1[js1_ind].MR2; + dataL = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0); + if (Boardcnf->dbi_en) + tmp[2] = dataL | 0xc0; + else + tmp[2] = dataL & (~0xc0); + + for (i = 0; i < 2; i++) { + for (csab = 0; csab < CSAB_CNT; csab++) { + ddrtbl_setval(_cnf_DDR_PI_REGSET, + _reg_PI_MR1_DATA_Fx_CSx[i][csab], tmp[0]); + ddrtbl_setval(_cnf_DDR_PI_REGSET, + _reg_PI_MR2_DATA_Fx_CSx[i][csab], tmp[1]); + ddrtbl_setval(_cnf_DDR_PI_REGSET, + _reg_PI_MR3_DATA_Fx_CSx[i][csab], tmp[2]); + } + } + + /*********************************************************************** + * DDRPHY INT START + ***********************************************************************/ + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + /* non */ + } else { + regif_pll_wa(); + dbwait_loop(5); + } + + /*********************************************************************** + * FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) + ***********************************************************************/ + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), + (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); + ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01); + + /*********************************************************************** + * SET DATA SLICE TABLE + ***********************************************************************/ + for (slice = 0; slice < SLICE_CNT; slice++) { + adr = DDR_PHY_SLICE_REGSET_OFS + DDR_PHY_SLICE_REGSET_SIZE * slice; + for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM; i++) + reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_SLICE_REGSET[i]); + } + + /*********************************************************************** + * SET ADR SLICE TABLE + ***********************************************************************/ + adr = DDR_PHY_ADR_V_REGSET_OFS; + for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) + reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); + + if (((Prr_Product == PRR_PRODUCT_M3) || (Prr_Product == PRR_PRODUCT_M3N)) && + ((0x00ffffff & (uint32_t)((Boardcnf->ch[0].ca_swap) >> 40)) != 0x00)) { + adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE; + for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) + reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_ADR_DISABLE, 0x02); + DDR_PHY_ADR_I_NUM -= 1; + ddr_phycaslice = 1; + +#ifndef _def_LPDDR4_ODT + for (i = 0; i < 2; i++) { + for (csab = 0; csab < CSAB_CNT; csab++) + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_Fx_CSx[i][csab], 0x66); + } +#endif /* _def_LPDDR4_ODT */ + } else { + ddr_phycaslice = 0; + } + + if (DDR_PHY_ADR_I_NUM > 0) { + for (slice = 0; slice < DDR_PHY_ADR_I_NUM; slice++) { + adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE * slice; + for (i = 0; i < DDR_PHY_ADR_I_REGSET_NUM; i++) + reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_I_REGSET[i]); + } + } + + /*********************************************************************** + * SET ADRCTRL SLICE TABLE + ***********************************************************************/ + adr = DDR_PHY_ADR_G_REGSET_OFS; + for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) + reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]); + + /*********************************************************************** + * SET PI REGISTERS + ***********************************************************************/ + adr = DDR_PI_REGSET_OFS; + for (i = 0; i < DDR_PI_REGSET_NUM; i++) + reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]); +} + +/******************************************************************************* + * CONFIGURE DDR REGISTERS + ******************************************************************************/ +static void ddr_config_sub(void) +{ + uint32_t i; + uint32_t ch, slice; + uint32_t dataL; + uint32_t tmp; + uint8_t high_byte[SLICE_CNT]; + const uint32_t _par_CALVL_DEVICE_MAP = 1; + + foreach_vch(ch) { + /*********************************************************************** + * BOARD SETTINGS (DQ, DM, VREF_DRIVING) + ***********************************************************************/ + for (slice = 0; slice < SLICE_CNT; slice++) { + high_byte[slice] = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) % 2; + ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0, Boardcnf->ch[ch].dq_swap[slice]); + ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1, Boardcnf->ch[ch].dm_swap[slice]); + if (high_byte[slice]) { + /* HIGHER 16 BYTE */ + ddr_setval_s(ch, slice, _reg_PHY_CALVL_VREF_DRIVING_SLICE, 0x00); + } else { + /* LOWER 16 BYTE */ + ddr_setval_s(ch, slice, _reg_PHY_CALVL_VREF_DRIVING_SLICE, 0x01); + } + } + + /*********************************************************************** + * BOARD SETTINGS (CA, ADDR_SEL) + ***********************************************************************/ + dataL = (0x00ffffff & (uint32_t)(Boardcnf->ch[ch].ca_swap)) | 0x00888888; + + /* --- ADR_CALVL_SWIZZLE --- */ + if (Prr_Product == PRR_PRODUCT_M3) { + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); + ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); + } else { + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); + ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); + } + + /* --- ADR_ADDR_SEL --- */ + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) { + dataL = 0x00FFFFFF & (uint32_t)(Boardcnf->ch[ch].ca_swap); + } else { + dataL = 0; + tmp = (uint32_t)(Boardcnf->ch[ch].ca_swap); + for (i = 0; i < 6; i++) { + dataL |= ((tmp & 0x0f) << (i * 5)); + tmp = tmp >> 4; + } + } + ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, dataL); + if (ddr_phycaslice == 1) { + /* ----------- adr slice2 swap ----------- */ + tmp = (uint32_t)((Boardcnf->ch[ch].ca_swap) >> 40); + dataL = (tmp & 0x00ffffff) | 0x00888888; + + /* --- ADR_CALVL_SWIZZLE --- */ + if (Prr_Product == PRR_PRODUCT_M3) { + ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL); + ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); + ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0_1, dataL); + ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); + ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); + } else { + ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE0, dataL); + ddr_setval_s(ch, 2, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000); + ddr_setval_s(ch, 2, _reg_PHY_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); + } + + /* --- ADR_ADDR_SEL --- */ + dataL = 0; + for (i = 0; i < 6; i++) { + dataL |= ((tmp & 0x0f) << (i * 5)); + tmp = tmp >> 4; + } + + ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, dataL); + } + + /*********************************************************************** + * BOARD SETTINGS (BYTE_ORDER_SEL) + ***********************************************************************/ + if (Prr_Product == PRR_PRODUCT_M3) { + /* --- DATA_BYTE_SWAP --- */ + dataL = 0; + tmp = Boardcnf->ch[ch].dqs_swap; + for (i = 0; i < 4; i++) { + dataL |= ((tmp & 0x03) << (i * 2)); + tmp = tmp >> 4; + } + } else { + /* --- DATA_BYTE_SWAP --- */ + dataL = Boardcnf->ch[ch].dqs_swap; + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01); + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0, (dataL) & 0x0f); + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1, (dataL >> 4 * 1) & 0x0f); + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2, (dataL >> 4 * 2) & 0x0f); + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3, (dataL >> 4 * 3) & 0x0f); + + ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00); + } + ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, dataL); + } +} + +static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz) +{ + uint32_t slice; + uint32_t tmp; + uint32_t tgt; + + if (ddr_csn / 2) + tgt = 3; + else + tgt = 1; + + for (slice = 0; slice < SLICE_CNT; slice++) { + tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + if (tgt == tmp) + break; + } + tmp = 0x00FFFFFF & (uint32_t)(Boardcnf->ch[ch].ca_swap); + if (slice % 2) + tmp |= 0x00888888; + *p_swz = tmp; +} + +static void ddr_config_sub_h3v1x(void) +{ + uint32_t ch, slice; + uint32_t dataL; + uint32_t tmp; + uint8_t high_byte[SLICE_CNT]; + uint32_t ca_swizzle; + uint32_t ca; + uint32_t csmap; + uint32_t o_inv; + uint32_t inv; + uint32_t bit_soc; + uint32_t bit_mem; + uint32_t j; + + const uint8_t o_mr15 = 0x55; + const uint8_t o_mr20 = 0x55; + const uint16_t o_mr32_mr40 = 0x5a3c; + + foreach_vch(ch) { + /*********************************************************************** + * BOARD SETTINGS (DQ, DM, VREF_DRIVING) + ***********************************************************************/ + csmap = 0; + for (slice = 0; slice < SLICE_CNT; slice++) { + tmp = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + high_byte[slice] = tmp % 2; + if ((tmp == 1) && (slice >= 2)) + csmap |= 0x05; + if ((tmp == 3) && (slice >= 2)) + csmap |= 0x50; + ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING, Boardcnf->ch[ch].dq_swap[slice]); + if (high_byte[slice]) { + /* HIGHER 16 BYTE */ + ddr_setval_s(ch, slice, _reg_PHY_CALVL_VREF_DRIVING_SLICE, 0x00); + } else { + /* LOWER 16 BYTE */ + ddr_setval_s(ch, slice, _reg_PHY_CALVL_VREF_DRIVING_SLICE, 0x01); + } + } + /*********************************************************************** + * BOARD SETTINGS (CA, ADDR_SEL) + ***********************************************************************/ + ca = 0x00FFFFFF & (uint32_t)(Boardcnf->ch[ch].ca_swap); + ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca); + ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap); + + get_ca_swizzle(ch, 0, &ca_swizzle); + + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, ca_swizzle); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, 0x00000000); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000); + ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 0x01); + + for (slice = 0; slice < SLICE_CNT; slice++) { + ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_NUM, 0x01); + ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_START, 0x08); + + if (high_byte[slice]) + o_inv = o_mr20; + else + o_inv = o_mr15; + + tmp = Boardcnf->ch[ch].dq_swap[slice]; + inv = 0; + j = 0; + for (bit_soc = 0; bit_soc < 8; bit_soc++) { + bit_mem = (tmp >> (4 * bit_soc)) & 0x0f; + j |= (1U << bit_mem); + if (o_inv & (1U << bit_mem)) + inv |= (1U << bit_soc); + } + dataL = o_mr32_mr40; + if (!high_byte[slice]) + dataL |= (inv << 24); + if (high_byte[slice]) + dataL |= (inv << 16); + ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8, dataL); + } + } +} + +static void ddr_config(void) +{ + int32_t i; + uint32_t ch, slice; + uint32_t dataL; + uint32_t tmp; + int8_t _adj; + int16_t adj; + uint32_t dq; + union { + uint32_t ui32[4]; + uint8_t ui8[16]; + } patt; + uint16_t patm; + + /*********************************************************************** + * configure ddrphy registers + ***********************************************************************/ + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + ddr_config_sub_h3v1x(); + else + ddr_config_sub(); /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */ + + /*********************************************************************** + * WDQ_USER_PATT + ***********************************************************************/ + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + patm = 0; + for (i = 0; i < 16; i++) { + tmp = Boardcnf->ch[ch].wdqlvl_patt[i]; + patt.ui8[i] = tmp & 0xff; + if (tmp & 0x100) + patm |= (1U << i); + } + ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0, patt.ui32[0]); + ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1, patt.ui32[1]); + ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2, patt.ui32[2]); + ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3, patt.ui32[3]); + ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm); + } + } + + /*********************************************************************** + * CACS DLY + ***********************************************************************/ + dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U); + foreach_vch(ch) { + for (i = 0; i < (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i++) { + adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]); + ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], dataL + adj); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), + _cnf_DDR_PHY_ADR_V_REGSET[ddr_regdef_adr(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - DDR_PHY_ADR_V_REGSET_OFS]); + } + for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { + adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]); + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], dataL + adj); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]), + _cnf_DDR_PHY_ADR_G_REGSET[ddr_regdef_adr(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - DDR_PHY_ADR_G_REGSET_OFS]); + } + if (ddr_phycaslice == 1) { + for (i = 0; i < 6; i++) { + adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); + ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], dataL + adj); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) + 0x0100, + _cnf_DDR_PHY_ADR_V_REGSET[ddr_regdef_adr(_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) - DDR_PHY_ADR_V_REGSET_OFS]); + } + } + } + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), + (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); + + /*********************************************************************** + * WDQDM DLY + ***********************************************************************/ + dataL = Boardcnf->dqdm_dly_w; + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + for (i = 0; i <= 8; i++) { + dq = slice * 8 + i; + if (i == 8) + _adj = Boardcnf->ch[ch].dm_adj_w[slice]; + else + _adj = Boardcnf->ch[ch].dq_adj_w[dq]; + adj = _f_scale_adj(_adj); + ddr_setval_s(ch, slice, + _reg_PHY_CLK_WRX_SLAVE_DELAY[i], + dataL + adj + ); + } + } + } + + /*********************************************************************** + * RDQDM DLY + ***********************************************************************/ + dataL = Boardcnf->dqdm_dly_r; + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + for (i = 0; i <= 8; i++) { + dq = slice * 8 + i; + if (i == 8) + _adj = Boardcnf->ch[ch].dm_adj_r[slice]; + else + _adj = Boardcnf->ch[ch].dq_adj_r[dq]; + adj = _f_scale_adj(_adj); + ddr_setval_s(ch, slice, + _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], + dataL + adj + ); + ddr_setval_s(ch, slice, + _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], + dataL + adj + ); + } + } + } +} + +/******************************************************************************* + * DBSC register setting functions + ******************************************************************************/ +static void dbsc_regset_pre(void) +{ + uint32_t ch, csab; + uint32_t dataL; + + /*********************************************************************** + * PRIMARY SETTINGS + ***********************************************************************/ + /* LPDDR4, BL = 16, DFI interface */ + mmio_write_32(DBSC_DBKIND, 0x0000000a); + mmio_write_32(DBSC_DBBL, 0x00000002); + mmio_write_32(DBSC_DBPHYCONF0, 0x00000001); + + /* FREQRATIO=2 */ + mmio_write_32(DBSC_DBSYSCONF1, 0x00000002); + + /* Chanel map (H3 Ver.1.x) */ + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + mmio_write_32(DBSC_DBSCHCNT1, 0x00001010); + + /* DRAM SIZE REGISTER: + * set all ranks as density=0(4Gb) for PHY initialization + */ + foreach_vch(ch) + for (csab = 0; csab < 4; csab++) + mmio_write_32(DBSC_DBMEMCONF(ch, csab), DBMEMCONF_REGD(0)); + + if (Prr_Product == PRR_PRODUCT_M3) { + dataL = 0xe4e4e4e4; + foreach_ech(ch) { + if ((ddr_phyvalid & (1U << ch))) + dataL = (dataL & (~(0x000000FF << (ch*8)))) + | (((Boardcnf->ch[ch].dqs_swap & 0x0003) + | ((Boardcnf->ch[ch].dqs_swap & 0x0030) >> 2) + | ((Boardcnf->ch[ch].dqs_swap & 0x0300) >> 4) + | ((Boardcnf->ch[ch].dqs_swap & 0x3000) >> 6)) << (ch*8)); + } + mmio_write_32(DBSC_DBBSWAP, dataL); + } +} + +static void dbsc_regset(void) +{ + int32_t i; + uint32_t ch; + uint32_t dataL; + uint32_t dataL2; + uint32_t tmp[4]; + + /* RFC */ + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_20) && (max_density == 0)) { + js2[JS2_tRFCab] = _f_scale(ddr_mbps, ddr_mbpsdiv, + 1UL*jedec_spec2_tRFC_ab[1] * 1000, 0); + } else { + js2[JS2_tRFCab] = _f_scale(ddr_mbps, ddr_mbpsdiv, + 1UL*jedec_spec2_tRFC_ab[max_density] * 1000, 0); + } + + /* DBTR0.CL : RL */ + mmio_write_32(DBSC_DBTR(0), RL); + + /* DBTR1.CWL : WL */ + mmio_write_32(DBSC_DBTR(1), WL); + + /* DBTR2.AL : 0 */ + mmio_write_32(DBSC_DBTR(2), 0); + + /* DBTR3.TRCD: tRCD */ + mmio_write_32(DBSC_DBTR(3), js2[JS2_tRCD]); + + /* DBTR4.TRPA, TRP: tRPab, tRPpb */ + mmio_write_32(DBSC_DBTR(4), (js2[JS2_tRPab] << 16) | js2[JS2_tRPpb]); + + /* DBTR5.TRC : use tRCpb */ + mmio_write_32(DBSC_DBTR(5), js2[JS2_tRCpb]); + + /* DBTR6.TRAS : tRAS */ + mmio_write_32(DBSC_DBTR(6), js2[JS2_tRAS]); + + /* DBTR7.TRRD : tRRD */ + mmio_write_32(DBSC_DBTR(7), (js2[JS2_tRRD] << 16) | js2[JS2_tRRD]); + + /* DBTR8.TFAW : tFAW */ + mmio_write_32(DBSC_DBTR(8), js2[JS2_tFAW]); + + /* DBTR9.TRDPR : tRTP */ + mmio_write_32(DBSC_DBTR(9), js2[JS2_tRTP]); + + /* DBTR10.TWR : nWR */ + mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nWR); + + /* DBTR11.TRDWR : RL + BL / 2 + Rounddown(tRPST) + PHY_ODTLoff - ODTLon + tDQSCK - tODTon,min + PCB delay (out+in) + tPHY_ODToff */ + mmio_write_32(DBSC_DBTR(11), + RL + (16 / 2) + 1 + 2 - js1[js1_ind].ODTLon + js2[JS2_tDQSCK] - js2[JS2_tODTon_min] + _f_scale(ddr_mbps, ddr_mbpsdiv, 1300, 0)); + + /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */ + dataL = WL + 1 + (16 / 2) + js2[JS2_tWTR]; + mmio_write_32(DBSC_DBTR(12), (dataL << 16) | dataL); + + /* DBTR13.TRFCAB : tRFCab */ + mmio_write_32(DBSC_DBTR(13), + (js2[JS2_tRFCab])); + + /* DBTR14.TCKEHDLL, tCKEH : tCKEHCMD, tCKEHCMD */ + mmio_write_32(DBSC_DBTR(14), + (js2[JS2_tCKEHCMD] << 16) | (js2[JS2_tCKEHCMD])); + + /* DBTR15.TCKESR, TCKEL : tSR, tCKELPD */ + mmio_write_32(DBSC_DBTR(15), + (js2[JS2_tSR] << 16) | (js2[JS2_tCKELPD])); + + /* DBTR16 */ + /* WDQL : tphy_wrlat + tphy_wrdata */ + tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1); + /* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0 + * tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0 + */ + tmp[1] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1); + /* DQL : tphy_rdlat + trdata_en */ + /* it is not important for dbsc */ + tmp[2] = RL + 16; + /* DQIENLTNCY : trdata_en */ + tmp[3] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1; + mmio_write_32(DBSC_DBTR(16), + (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR24 */ + /* WRCSLAT = WRLAT -5 */ + tmp[0] -= 5; + /* WRCSGAP = 5 */ + tmp[1] = 5; + /* RDCSLAT = RDLAT_ADJ +2 */ + if (Prr_Product == PRR_PRODUCT_M3) + tmp[2] = tmp[3]; + else + tmp[2] = tmp[3] + 2; + /* RDCSGAP = 6 */ + if (Prr_Product == PRR_PRODUCT_M3) + tmp[3] = 4; + else + tmp[3] = 6; + mmio_write_32(DBSC_DBTR(24), + (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR17.TMODRD, TMOD, TRDMR: tMRR, tMRD, (0) */ + mmio_write_32(DBSC_DBTR(17), (js2[JS2_tMRR] << 24) | (js2[JS2_tMRD] << 16)); + + /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */ + mmio_write_32(DBSC_DBTR(18), 0); + + /* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */ + mmio_write_32(DBSC_DBTR(19), 0); + + /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */ + dataL = js2[JS2_tRFCab] + js2[JS2_tCKEHCMD]; + mmio_write_32(DBSC_DBTR(20), (dataL << 16) | dataL); + + /* DBTR21.TCCD */ + /* DBTR23.TCCD */ + /* H3 Ver.1.0 cannot use TBTR23 feature */ + if (ddr_tccd == 8 && + !((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_10)) + ) { + dataL = 8; + mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); + mmio_write_32(DBSC_DBTR(23), 0x00000002); + } else if (ddr_tccd <= 11) { + dataL = 11; + mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); + mmio_write_32(DBSC_DBTR(23), 0x00000000); + } else { + dataL = ddr_tccd; + mmio_write_32(DBSC_DBTR(21), (dataL << 16) | dataL); + mmio_write_32(DBSC_DBTR(23), 0x00000000); + } + + /* DBTR22.ZQLAT : */ + dataL = js2[JS2_tZQCALns]*100; /* 1000 * 1000 ps */ + dataL = (dataL << 16) | (js2[JS2_tZQLAT] + 24 + 20); + mmio_write_32(DBSC_DBTR(22), dataL); + + /* DBTR25 : do not use in LPDDR4 */ + mmio_write_32(DBSC_DBTR(25), 0); + + /* DBRNK : */ + /* + * DBSC_DBRNK2 rkrr + * DBSC_DBRNK3 rkrw + * DBSC_DBRNK4 rkwr + * DBSC_DBRNK5 rkww + */ + #define _par_DBRNK_VAL (0x7007) + + for (i = 0; i < 4; i++) { + dataL = (_par_DBRNK_VAL >> (i * 4)) & 0x0f; + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11) && (i == 0)) + dataL += 1; + dataL2 = 0; + foreach_vch(ch) { + dataL2 = dataL2 | (dataL << (4 * ch)); + } + mmio_write_32(DBSC_DBRNK(2 + i), dataL2); + } + mmio_write_32(DBSC_DBADJ0, 0x00000000); + + /*********************************************************************** + * timing registers for Scheduler + ***********************************************************************/ + /* SCFCTST0 */ + /* SCFCTST0 ACT-ACT */ + tmp[3] = 1UL * js2[JS2_tRCpb] * 800 * ddr_mbpsdiv / ddr_mbps; + /* SCFCTST0 RDA-ACT */ + tmp[2] = 1UL * ((16 / 2) + js2[JS2_tRTP] - 8 + js2[JS2_tRPpb]) * 800 * ddr_mbpsdiv / ddr_mbps; + /* SCFCTST0 WRA-ACT */ + tmp[1] = 1UL * (WL + 1 + (16 / 2) + js1[js1_ind].nWR) * 800 * ddr_mbpsdiv / ddr_mbps; + /* SCFCTST0 PRE-ACT */ + tmp[0] = 1UL * js2[JS2_tRPpb]; + mmio_write_32(DBSC_SCFCTST0, (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* SCFCTST1 */ + /* SCFCTST1 RD-WR */ + tmp[3] = 1UL * (mmio_read_32(DBSC_DBTR(11)) & 0xff) * 800 * ddr_mbpsdiv / ddr_mbps; + /* SCFCTST1 WR-RD */ + tmp[2] = 1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv / ddr_mbps; + /* SCFCTST1 ACT-RD/WR */ + tmp[1] = 1UL * js2[JS2_tRCD] * 800 * ddr_mbpsdiv / ddr_mbps; + /* SCFCTST1 ASYNCOFS */ + tmp[0] = 12; + mmio_write_32(DBSC_SCFCTST1, (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBSCHRW1 */ + /* DBSCHRW1 SCTRFCAB */ + tmp[0] = 1UL * js2[JS2_tRFCab] * 800 * ddr_mbpsdiv / ddr_mbps; + dataL = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16) + + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) + + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7; + if (tmp[0] < dataL) + tmp[0] = dataL; + if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) { + mmio_write_32(DBSC_DBSCHRW1, tmp[0] + + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) + * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps - 3); + } else { + mmio_write_32(DBSC_DBSCHRW1, tmp[0] + + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) + * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) / ddr_mbps); + } + + /*********************************************************************** + * QOS and CAM + ***********************************************************************/ +#ifdef ddr_qos_init_setting /* only for non qos_init */ + /* wbkwait(0004), wbkmdhi(4, 2), wbkmdlo(1, 8) */ + mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218); + /* 0(fillunit), 8(dirtymax), 4(dirtymin) */ + mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4); + /* stop_tolerance */ + mmio_write_32(DBSC_DBSCHRW0, 0x22421111); + /* rd-wr/wr-rd toggle priority */ + mmio_write_32(DBSC_SCFCTST2, 0x012F1123); + mmio_write_32(DBSC_DBSCHSZ0, 0x00000001); + mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037); + + /* QoS Settings */ + mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U); + mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U); + mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U); + mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U); + mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U); + mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U); + mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U); + mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U); + mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U); + mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U); + mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U); + mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U); + mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U); + mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U); + mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U); + mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U); + mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U); + mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U); + mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U); + mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U); + mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U); + mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U); + mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U); + mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U); + mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U); + mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U); + mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U); + mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U); + + mmio_write_32(QOSCTRL_RAEN, 0x00000001U); +#endif /* ddr_qos_init_setting */ + /* H3 Ver.1.1 need to set monitor function */ + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_11)) + mmio_write_32(DBSC_DBMONCONF4, 0x00700000); + + if (Prr_Product == PRR_PRODUCT_H3) { + if (Prr_Cut == PRR_PRODUCT_10) { + /* resrdis, simple mode, sc off */ + mmio_write_32(DBSC_DBBCAMDIS, 0x00000007); + } else if (Prr_Cut == PRR_PRODUCT_11) { + /* resrdis, simple mode */ + mmio_write_32(DBSC_DBBCAMDIS, 0x00000005); + } else if (Prr_Cut < PRR_PRODUCT_30) { + /* H3 Ver.2.0 */ + /* resrdis */ + mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); + } else {/* H3 Ver.3.0(include H3N) */ + /* exprespque */ + mmio_write_32(DBSC_DBBCAMDIS, 0x00000010); + } + } else { /* M3-W/M3-N/V3H */ + /* resrdis */ + mmio_write_32(DBSC_DBBCAMDIS, 0x00000001); + } +} + +static void dbsc_regset_post(void) +{ + uint32_t ch, cs; + uint32_t dataL; + uint32_t slice, rdlat_max, rdlat_min; + + rdlat_max = 0; + rdlat_min = 0xffff; + foreach_vch(ch) { + for (cs = 0; cs < CS_CNT; cs++) { + if ((ch_have_this_cs[cs] & (1U << ch)) != 0) { + for (slice = 0; slice < SLICE_CNT; slice++) { + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); + dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_LATENCY_ADJUST); + if (dataL > rdlat_max) + rdlat_max = dataL; + if (dataL < rdlat_min) + rdlat_min = dataL; + } + } + } + } + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) { +#if RCAR_DRAM_SPLIT == 2 + if (Boardcnf->phyvalid == 0x05) { + mmio_write_32(DBSC_DBTR(24), + ((rdlat_max) << 24) + ((rdlat_min) << 16) + mmio_read_32(DBSC_DBTR(24))); + } else { + mmio_write_32(DBSC_DBTR(24), + ((rdlat_max * 2 - rdlat_min + 4) << 24) + ((rdlat_min + 2) << 16) + mmio_read_32(DBSC_DBTR(24))); + } +#else /*RCAR_DRAM_SPLIT == 2 */ + mmio_write_32(DBSC_DBTR(24), + ((rdlat_max * 2 - rdlat_min + 4) << 24) + ((rdlat_min + 2) << 16) + mmio_read_32(DBSC_DBTR(24))); +#endif /*RCAR_DRAM_SPLIT == 2 */ + } else { + mmio_write_32(DBSC_DBTR(24), + ((rdlat_max + 2) << 24) + ((rdlat_max + 2) << 16) + mmio_read_32(DBSC_DBTR(24))); + } + + /* set ddr density information */ + foreach_ech(ch) { + for (cs = 0; cs < CS_CNT; cs++) { + if (ddr_density[ch][cs] == 0xff) + mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00); + else + mmio_write_32(DBSC_DBMEMCONF(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs])); + } + mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000); + mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000); + } + + mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010); + + /* set DBI */ + if (Boardcnf->dbi_en) + mmio_write_32(DBSC_DBDBICNT, 0x00000003); + + /* H3 Ver.2.0 or later/M3-N/V3H DBI wa */ + if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) + || (Prr_Product == PRR_PRODUCT_M3N) || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en)) + reg_ddrphy_write_a(0x00001010, 0x01000000); + + /* set REFCYCLE */ + dataL = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv; + mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (dataL & 0x0000ffff)); + mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS); + +#if RCAR_REWT_TRAINING != 0 + /* Periodic-WriteDQ Training seeting */ + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10))) { + /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ + } else { + /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */ + mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000); + + ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04); + ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0F); + ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50); + ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300); + + ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP, ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WDQLVL_CS_MAP)); + ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f); + ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); + ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01); + ddr_setval_ach(_reg_PI_TREF_F0, 0x0000); + ddr_setval_ach(_reg_PI_TREF_F1, 0x0000); + ddr_setval_ach(_reg_PI_TREF_F2, 0x0000); + + if (Prr_Product == PRR_PRODUCT_M3) + ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02); + else + ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02); + ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01); + + /* DFI_PHYMSTR_ACK , WTmode setting */ + mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011); /* DFI_PHYMSTR_ACK: WTmode = b'01 */ + } +#endif /* RCAR_REWT_TRAINING */ + /* periodic dram zqcal enable */ + mmio_write_32(DBSC_DBCALCNF, 0x01000010); + + /* periodic phy ctrl update enable */ + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) { + /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ + } else { +#if RCAR_DRAM_SPLIT == 2 + if ((Prr_Product == PRR_PRODUCT_H3) && (Boardcnf->phyvalid == 0x05)) + mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001); + else + mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); +#else /* RCAR_DRAM_SPLIT == 2 */ + mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001); +#endif /* RCAR_DRAM_SPLIT == 2 */ + } + +#ifdef DDR_BACKUPMODE + /* SRX */ + if (ddrBackup == DRAM_BOOT_STATUS_WARM) { +#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0, 1 only) */ + NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n"); + send_dbcmd(0x0A040001); + if (Prr_Product == PRR_PRODUCT_H3) + send_dbcmd(0x0A140001); +#else /* DDR_BACKUPMODE_HALF */ /* for All channels */ + send_dbcmd(0x0A840001); +#endif /* DDR_BACKUPMODE_HALF */ + } +#endif /* DDR_BACKUPMODE */ + /* set Auto Refresh */ + mmio_write_32(DBSC_DBRFEN, 0x00000001); + +#if RCAR_REWT_TRAINING != 0 + /* Periodic WriteDQ Traning */ + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10))) { + /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */ + } else { + /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */ + ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100); + } +#endif /* RCAR_REWT_TRAINING */ + + /* dram access enable */ + mmio_write_32(DBSC_DBACEN, 0x00000001); + + MSG_LF("dbsc_regset_post(done)"); +} + +/******************************************************************************* + * DFI_INIT_START + ******************************************************************************/ +static uint32_t dfi_init_start(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + const uint32_t RETRY_MAX = 0x10000; + + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + + /*********************************************************************** + * PLL3 Disable + ***********************************************************************/ + /* protect register interface */ + ddrphy_regif_idle(); + + pll3_control(0); + + /*********************************************************************** + * init start + ***********************************************************************/ + /* dbdficnt0: + * dfi_dram_clk_disable = 1 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start = 0 + */ + foreach_vch(ch) + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10); + dsb_sev(); + + /* dbdficnt0: + * dfi_dram_clk_disable = 1 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start = 1 + */ + foreach_vch(ch) + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11); + dsb_sev(); + + } else { + ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02); + dsb_sev(); + ddrphy_regif_idle(); + } + + /* dll_rst negate */ + foreach_vch(ch) + mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01); + (void)mmio_read_32(DBSC_DBPDCNT3(ch)); + dsb_sev(); + + /*********************************************************************** + * wait init_complete + ***********************************************************************/ + phytrainingok = 0; + retry = 0; + while (retry++ < RETRY_MAX) { + foreach_vch(ch) { + dataL = mmio_read_32(DBSC_DBDFISTAT(ch)); + if (dataL & 0x00000001) + phytrainingok |= (1U << ch); + } + dsb_sev(); + if (phytrainingok == ddr_phyvalid) + break; + if ((retry % 256) == 0) + ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); + } + + /*********************************************************************** + * all ch ok? + ***********************************************************************/ + if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) + return 0xff; + /* dbdficnt0: + * dfi_dram_clk_disable = 0 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start = 0 + */ + foreach_vch(ch) + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010); + (void)mmio_read_32(DBSC_DBDFICNT(ch)); + dsb_sev(); + + return 0; +} + +/******************************************************************************* + * drivablity setting : CMOS MODE ON/OFF + ******************************************************************************/ +static void change_lpddr4_en(uint32_t mode) +{ + uint32_t ch; + uint32_t i; + uint32_t dataL; + const uint32_t _reg_PHY_PAD_DRIVE_X[3] = { + _reg_PHY_PAD_ADDR_DRIVE, + _reg_PHY_PAD_CLK_DRIVE, + _reg_PHY_PAD_CS_DRIVE + }; + + foreach_vch(ch) { + for (i = 0; i < 3; i++) { + dataL = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]); + if (mode) + dataL |= (1U << 14); + else + dataL &= ~(1U << 14); + ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], dataL); + } + } +} + +/******************************************************************************* + * drivablity setting + ******************************************************************************/ +static uint32_t set_term_code(void) +{ + int32_t i; + uint32_t ch, index; + uint32_t dataL; + uint32_t chip_id[2]; + uint32_t term_code; + uint32_t override; + uint32_t pvtr; + uint32_t pvtp; + uint32_t pvtn; + + term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_DATA_TERM); + override = 0; + for (i = 0; i < 2; i++) + chip_id[i] = mmio_read_32(LIFEC_CHIPID(i)); + + index = 0; + while (1) { + if (TermcodeBySample[index][0] == 0xffffffff) + break; + if ((TermcodeBySample[index][0] == chip_id[0]) + && (TermcodeBySample[index][1] == chip_id[1])) { + term_code = TermcodeBySample[index][2]; + override = 1; + break; + } + index++; + } + + if (override) { + for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { + dataL = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_TERM_X[index]); + dataL = (dataL & 0xfffe0000) | term_code; + ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], dataL); + } + } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10)) { + /* non */ + } else { + ddr_setval_ach(_reg_PHY_PAD_TERM_X[0], + (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000)); + ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01); + ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01); + foreach_vch(ch) { + do { + dataL = ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); + } while (!(dataL & 0x00800000)); + } + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + foreach_vch(ch) { + dataL = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]); + pvtr = (dataL >> 12) & 0x1f; + pvtr += 8; + if (pvtr > 0x1f) + pvtr = 0x1f; + dataL = ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0); + pvtn = (dataL >> 6) & 0x03f; + pvtp = (dataL >> 0) & 0x03f; + + for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { + dataL = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_TERM_X[index]); + dataL = (dataL & 0xfffe0000) | (pvtr << 12) | (pvtn << 6) | (pvtp); + ddr_setval(ch, _reg_PHY_PAD_TERM_X[index], dataL); + } + } + } else { /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */ + foreach_vch(ch) { + for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) { + dataL = ddr_getval(ch, _reg_PHY_PAD_TERM_X[index]); + ddr_setval(ch, _reg_PHY_PAD_TERM_X[index], (dataL & 0xFFFE0FFF) | 0x00015000); + } + } + } + } + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + /* non */ + } else { + ddr_padcal_tcompensate_getinit(override); + } + return 0; +} + +/******************************************************************************* + * DDR mode register setting + ******************************************************************************/ +static void ddr_register_set(void) +{ + int32_t fspwp; + uint32_t tmp; + + for (fspwp = 1; fspwp >= 0; fspwp--) { + /* MR13, fspwp */ + send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6)); + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR1_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840100 | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR2_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840200 | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840300 | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840b00 | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840c00 | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR14_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840e00 | tmp); + /* MR22 */ + send_dbcmd(0x0e841616); + + /* ZQCAL start */ + send_dbcmd(0x0d84004F); + + /* ZQLAT */ + send_dbcmd(0x0d840051); + } + /* MR13, fspwp */ + send_dbcmd(0x0e840d08); +} + +/******************************************************************************* + * Training handshake functions + ******************************************************************************/ +static inline uint32_t wait_freqchgreq(uint32_t assert) +{ + uint32_t dataL; + uint32_t count; + uint32_t ch; + + count = 100000; + + /* H3 Ver.1.x cannot see frqchg_req */ + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + return 0; + + if (assert) { + do { + dataL = 1; + foreach_vch(ch) { + dataL &= mmio_read_32(DBSC_DBPDSTAT(ch)); + } + count = count - 1; + } while (((dataL & 0x01) != 0x01) & (count != 0)); + } else { + do { + dataL = 0; + foreach_vch(ch) { + dataL |= mmio_read_32(DBSC_DBPDSTAT(ch)); + } + count = count - 1; + } while (((dataL & 0x01) != 0x00) & (count != 0)); + } + + return (count == 0); +} + +static inline void set_freqchgack(uint32_t assert) +{ + uint32_t ch; + uint32_t dataL; + + if (assert) + dataL = 0x0CF20000; + else + dataL = 0x00000000; + + foreach_vch(ch) + mmio_write_32(DBSC_DBPDCNT2(ch), dataL); +} + +static inline void set_dfifrequency(uint32_t freq) +{ + uint32_t ch; + + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + foreach_vch(ch) + mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq); + } else { + foreach_vch(ch) { + mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24, (freq << 24)); + } + } + (void)mmio_read_32(DBSC_DBDFICNT(ch)); + dsb_sev(); +} + +static uint32_t pll3_freq(uint32_t on) +{ + uint32_t timeout; + + timeout = wait_freqchgreq(1); + + if ((!((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11))) && (on)) { + if (((1600U * ddr_mbpsdiv) < ddr_mbps) || (Prr_Product == PRR_PRODUCT_M3)){ + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 0x01421142U); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), 0x00000142U); + } else { + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL), 0x03421342U); + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA), 0x00000342U); + } + } + + if (timeout) + return 1; + + pll3_control(on); + set_dfifrequency(on); + + set_freqchgack(1); + timeout = wait_freqchgreq(0); + set_freqchgack(0); + + if (timeout) { + FATAL_MSG("Time out[2]\n"); + return 1; + } + return 0; +} + +/******************************************************************************* + * update dly + ******************************************************************************/ +static void update_dly(void) +{ + ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01); + ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01); +} + +/******************************************************************************* + * training by pi + ******************************************************************************/ +static uint32_t pi_training_go(void) +{ + uint32_t flag; + uint32_t dataL; + uint32_t retry; + const uint32_t RETRY_MAX = 4096*16; + uint32_t ch; + + uint32_t mst_ch; + uint32_t cur_frq; + uint32_t complete; + uint32_t frqchg_req; + + /* ********************************************************************* */ + + /*********************************************************************** + * pi_start + ***********************************************************************/ + ddr_setval_ach(_reg_PI_START, 0x01); + foreach_vch(ch) + ddr_getval(ch, _reg_PI_INT_STATUS); + + /* set dfi_phymstr_ack = 1 */ + mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001); + (void)mmio_read_32(DBSC_DBDFIPMSTRCNF); + dsb_sev(); + + /*********************************************************************** + * wait pi_int_status[0] + ***********************************************************************/ + mst_ch = 0; + flag = 0; + complete = 0; + cur_frq = 0; + retry = RETRY_MAX; + do { + frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01; + + /* H3 Ver.1.x cannot see frqchg_req */ + if ((Prr_Product == PRR_PRODUCT_H3) + && (Prr_Cut <= PRR_PRODUCT_11)) { + if ((retry % 4096) == 1) + frqchg_req = 1; + else + frqchg_req = 0; + } + + if (frqchg_req) { + if (cur_frq) { + /* Low frequency */ + flag = pll3_freq(0); + cur_frq = 0; + } else { + /* High frequency */ + flag = pll3_freq(1); + cur_frq = 1; + } + if (flag) + break; + } else { + if (cur_frq) { + foreach_vch(ch) { + if (complete & (1U << ch)) + continue; + dataL = ddr_getval(ch, _reg_PI_INT_STATUS); + if (dataL & 0x01) + complete |= (1U << ch); + } + if (complete == ddr_phyvalid) + break; + } + } + } while (--retry); + foreach_vch(ch) { + /* dummy read */ + dataL = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0); + dataL = ddr_getval(ch, _reg_PI_INT_STATUS); + ddr_setval(ch, _reg_PI_INT_ACK, dataL); + } + if (ddrphy_regif_chk()) + return 0xfd; + return complete; +} + +/******************************************************************************* + * Initialize ddr + ******************************************************************************/ +static uint32_t init_ddr(void) +{ + int32_t i; + uint32_t dataL; + uint32_t phytrainingok; + uint32_t ch, slice; + uint32_t err; + int16_t adj; + + MSG_LF("init_ddr:0\n"); + +#ifdef DDR_BACKUPMODE + dram_get_boot_status(&ddrBackup); +#endif + + /*********************************************************************** + * unlock phy + ***********************************************************************/ + /* Unlock DDRPHY register(AGAIN) */ + foreach_vch(ch) + mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A); + (void)mmio_read_32(DBSC_DBPDLK(ch)); + dsb_sev(); + + if ((((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) + || (Prr_Product == PRR_PRODUCT_M3N) || (Prr_Product == PRR_PRODUCT_V3H)) && (Boardcnf->dbi_en)) + reg_ddrphy_write_a(0x00001010, 0x01000001); + else + reg_ddrphy_write_a(0x00001010, 0x00000001); + /*********************************************************************** + * dbsc register pre-setting + ***********************************************************************/ + dbsc_regset_pre(); + + /*********************************************************************** + * load ddrphy registers + ***********************************************************************/ + ddrtbl_load(); + + /*********************************************************************** + * configure ddrphy registers + ***********************************************************************/ + ddr_config(); + + /*********************************************************************** + * dfi_reset assert + ***********************************************************************/ + foreach_vch(ch) + mmio_write_32(DBSC_DBPDCNT0(ch), 0x01); + (void)mmio_read_32(DBSC_DBPDCNT0(ch)); + dsb_sev(); + + /*********************************************************************** + * dbsc register set + ***********************************************************************/ + dbsc_regset(); + MSG_LF("init_ddr:1\n"); + + /*********************************************************************** + * dfi_reset negate + ***********************************************************************/ + foreach_vch(ch) + mmio_write_32(DBSC_DBPDCNT0(ch), 0x00); + (void)mmio_read_32(DBSC_DBPDCNT0(ch)); + dsb_sev(); + + /*********************************************************************** + * dfi_init_start (start ddrphy) + ***********************************************************************/ + err = dfi_init_start(); + if (err) + return INITDRAM_ERR_I; + MSG_LF("init_ddr:2\n"); + + /*********************************************************************** + * ddr backupmode end + ***********************************************************************/ +#ifdef DDR_BACKUPMODE + if (ddrBackup) + NOTICE("[WARM_BOOT]\n"); + else + NOTICE("[COLD_BOOT]\n"); + err = dram_update_boot_status(ddrBackup); + + if (err) { + NOTICE("[BOOT_STATUS_UPDATE_ERROR]\n"); + return INITDRAM_ERR_I; + } +#endif + MSG_LF("init_ddr:3\n"); + + /*********************************************************************** + * override term code after dfi_init_complete + ***********************************************************************/ + err = set_term_code(); + if (err) + return INITDRAM_ERR_I; + MSG_LF("init_ddr:4\n"); + + /*********************************************************************** + * rx offset calibration + ***********************************************************************/ + if ((Prr_Cut > PRR_PRODUCT_11) || (Prr_Product == PRR_PRODUCT_M3N) || (Prr_Product == PRR_PRODUCT_V3H)) + err = rx_offset_cal_hw(); + else + err = rx_offset_cal(); + if (err) + return INITDRAM_ERR_O; + MSG_LF("init_ddr:5\n"); + + /* Dummy PDE */ + send_dbcmd(0x08840000); + + /* PDX */ + send_dbcmd(0x08840001); + + /*********************************************************************** + * check register i/f is alive + ***********************************************************************/ + err = ddrphy_regif_chk(); + if (err) + return INITDRAM_ERR_O; + MSG_LF("init_ddr:6\n"); + + /*********************************************************************** + * phy initialize end + ***********************************************************************/ + + /*********************************************************************** + * setup DDR mode registers + ***********************************************************************/ + /* CMOS MODE */ + change_lpddr4_en(0); + + /* MRS */ + ddr_register_set(); + + /*********************************************************************** + * Thermal sensor setting + ***********************************************************************/ + /* THCTR Bit6: PONM = 0 , Bit0: THSST = 1 */ + dataL = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001; + mmio_write_32(THS1_THCTR, dataL); + + /* LPDDR4 MODE */ + change_lpddr4_en(1); + + MSG_LF("init_ddr:7\n"); + + /*********************************************************************** + * mask CS_MAP if RANKx is not found + ***********************************************************************/ + foreach_vch(ch) { + dataL = ddr_getval(ch, _reg_PI_CS_MAP); + if (!(ch_have_this_cs[1] & (1U << ch))) + dataL = dataL & 0x05; + ddr_setval(ch, _reg_PI_CS_MAP, dataL); + } + + /*********************************************************************** + * exec pi_training + ***********************************************************************/ + reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), (0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN))); + ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00); + + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01); + } else { + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, ((ch_have_this_cs[1]) >> ch) & 0x01); + } + } + + phytrainingok = pi_training_go(); + + if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) + return INITDRAM_ERR_T | phytrainingok; + + MSG_LF("init_ddr:8\n"); + + /*********************************************************************** + * CACS DLY ADJUST + ***********************************************************************/ + dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj); + foreach_vch(ch) { + for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) { + adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]); + ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], + dataL + adj + ); + } + if (ddr_phycaslice == 1) { + for (i = 0; i < 6; i++) { + adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]); + ddr_setval_s(ch, 2, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i], + dataL + adj + ); + } + } + } + update_dly(); + MSG_LF("init_ddr:9\n"); + + /*********************************************************************** + * H3 fix rd latency to avoid bug in elasitic buffe + ***********************************************************************/ + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + adjust_rddqs_latency(); + + /*********************************************************************** + * Adjust Write path latency + ***********************************************************************/ + if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) + adjust_wpath_latency(); + + /*********************************************************************** + * RDQLVL Training + ***********************************************************************/ + if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) + ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01); + + err = rdqdm_man(); + + if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0x00) + ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00); + + if (err) + return INITDRAM_ERR_T; + update_dly(); + MSG_LF("init_ddr:10\n"); + + /*********************************************************************** + * WDQLVL Training + ***********************************************************************/ + err = wdqdm_man(); + if (err) + return INITDRAM_ERR_T; + update_dly(); + MSG_LF("init_ddr:11\n"); + + /*********************************************************************** + * training complete, setup dbsc + ***********************************************************************/ + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) + || (Prr_Product == PRR_PRODUCT_M3N) || (Prr_Product == PRR_PRODUCT_V3H)) { + ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00); + ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00); + } + + dbsc_regset_post(); + MSG_LF("init_ddr:12\n"); + + return phytrainingok; +} + +/******************************************************************************* + * SW LEVELING COMMON + ******************************************************************************/ +static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick) +{ + uint32_t ch; + uint32_t dataL; + uint32_t retry; + uint32_t waiting; + uint32_t err; + + const uint32_t RETRY_MAX = 0x1000; + + err = 0; + /* set EXIT -> OP_DONE is cleared */ + ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); + + /* kick */ + foreach_vch(ch) { + if (ch_have_this_cs[ddr_csn % 2] & (1U << ch)) { + ddr_setval(ch, reg_cs, ddr_csn); + ddr_setval(ch, reg_kick, 0x01); + } + } + foreach_vch(ch) { + /*PREPARE ADDR REGISTER (for SWLVL_OP_DONE)*/ + ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); + } + waiting = ch_have_this_cs[ddr_csn % 2]; + dsb_sev(); + retry = RETRY_MAX; + do { + foreach_vch(ch) { + if (!(waiting & (1U << ch))) + continue; + dataL = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE); + if (dataL & 0x01) + waiting &= ~(1U << ch); + } + retry--; + } while ((waiting) && (retry > 0)); + if (retry == 0) + err = 1; + + dsb_sev(); + /* set EXIT -> OP_DONE is cleared */ + ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01); + dsb_sev(); + + return err; +} + +/******************************************************************************* + * WDQ TRAINING + ******************************************************************************/ +#ifndef DDR_FAST_INIT +static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn) +{ + int32_t i, k; + uint32_t cs, slice; + uint32_t dataL; + + /*********************************************************************** + * clr of training results buffer + ***********************************************************************/ + cs = ddr_csn % 2; + dataL = Boardcnf->dqdm_dly_w; + for (slice = 0; slice < SLICE_CNT; slice++) { + k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) + continue; + for (i = 0; i <= 8; i++) { + if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) + wdqdm_dly[ch][cs][slice][i] = wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; + else + wdqdm_dly[ch][cs][slice][i] = dataL; + wdqdm_le[ch][cs][slice][i] = 0; + wdqdm_te[ch][cs][slice][i] = 0; + } + wdqdm_st[ch][cs][slice] = 0; + wdqdm_win[ch][cs][slice] = 0; + } +} + +static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn) +{ + int32_t i, k; + uint32_t cs, slice; + uint32_t dataL; + uint32_t err; + const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0; + + int32_t min_win; + int32_t win; + int8_t _adj; + int16_t adj; + uint32_t dq; + + /*********************************************************************** + * analysis of training results + ***********************************************************************/ + err = 0; + for (slice = 0; slice < SLICE_CNT; slice += 1) { + k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) + continue; + cs = ddr_csn % 2; + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); + for (i = 0; i < 9; i++) { + dq = slice * 8 + i; + if (i == 8) + _adj = Boardcnf->ch[ch].dm_adj_w[slice]; + else + _adj = Boardcnf->ch[ch].dq_adj_w[dq]; + adj = _f_scale_adj(_adj); + + dataL = ddr_getval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj; + ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i], dataL); + wdqdm_dly[ch][cs][slice][i] = dataL; + } + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00); + dataL = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS); + wdqdm_st[ch][cs][slice] = dataL; + min_win = INT_LEAST32_MAX; + for (i = 0; i <= 8; i++) { + ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT, i); + + dataL = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS); + wdqdm_te[ch][cs][slice][i] = dataL; + dataL = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS); + wdqdm_le[ch][cs][slice][i] = dataL; + win = (int32_t)wdqdm_te[ch][cs][slice][i] - wdqdm_le[ch][cs][slice][i]; + if (min_win > win) + min_win = win; + if (dataL >= _par_WDQLVL_RETRY_THRES) + err = 2; + } + wdqdm_win[ch][cs][slice] = min_win; + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x01); + else + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, ((ch_have_this_cs[1]) >> ch) & 0x01); + } + return err; +} +#endif /* DDR_FAST_INIT */ + +static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore) +{ + uint32_t i; + uint32_t ch, slice; + uint32_t tgt_cs, src_cs; + uint32_t tmp_r; + + /*********************************************************************** + * copy of training results + ***********************************************************************/ + foreach_vch(ch) { + for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) { + for (slice = 0; slice < SLICE_CNT; slice++) { + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, tgt_cs); + src_cs = ddr_csn % 2; + if (!(ch_have_this_cs[1] & (1U << ch))) + src_cs = 0; + for (i = 0; i <= 4; i += 4) { + if (restore) + tmp_r = rdqdm_dly[ch][tgt_cs][slice][i]; + else + tmp_r = rdqdm_dly[ch][src_cs][slice][i]; + ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], tmp_r); + } + } + } + } +} + +static uint32_t wdqdm_man1(void) +{ + int32_t k; + uint32_t ch, cs, slice; + uint32_t ddr_csn; + uint32_t dataL; + uint32_t err; + uint32_t high_dq[DRAM_CH_CNT]; + uint32_t mr14_csab0_bak[DRAM_CH_CNT]; +#ifndef DDR_FAST_INIT + uint32_t err_flg; +#endif /* DDR_FAST_INIT */ + + /*********************************************************************** + * manual execution of training + ***********************************************************************/ + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + foreach_vch(ch) { + high_dq[ch] = 0; + for (slice = 0; slice < SLICE_CNT; slice++) { + k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + if (k >= 2) + high_dq[ch] |= (1U << slice); + } + ddr_setval(ch, _reg_PI_16BIT_DRAM_CONNECT, 0x00); + } + } + err = 0; + /* CLEAR PREV RESULT */ + for (cs = 0; cs < CS_CNT; cs++) { + ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs); + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) + || (Prr_Product == PRR_PRODUCT_M3N) || (Prr_Product == PRR_PRODUCT_V3H)) { + ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS, 0x01); + } else { + ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS, 0x01); + } + } + ddrphy_regif_idle(); + +#ifndef DDR_FAST_INIT + err_flg = 0; +#endif /* DDR_FAST_INIT */ + + for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + foreach_vch(ch) { + dataL = mmio_read_32(DBSC_DBDFICNT(ch)); + dataL &= ~(0x00ffU << 16); + + if (ddr_csn >= 2) + k = (high_dq[ch] ^ 0x0f); + else + k = high_dq[ch]; + dataL |= (k << 16); + mmio_write_32(DBSC_DBDFICNT(ch), dataL); + ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k); + } + } + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut == PRR_PRODUCT_10))) { + wdqdm_cp(ddr_csn, 0); + } + + foreach_vch(ch) { + dataL = ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn]); + ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0], dataL); + } + + /* KICK WDQLVL */ + err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ); + if (err) + goto err_exit; + + if (ddr_csn == 0) + foreach_vch(ch) { + mr14_csab0_bak[ch] = ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0]); + } + else + foreach_vch(ch) { + ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][0], mr14_csab0_bak[ch]); + } +#ifndef DDR_FAST_INIT + foreach_vch(ch) { + if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) { + wdqdm_clr1(ch, ddr_csn); + continue; + } + err = wdqdm_ana1(ch, ddr_csn); + if (err) + err_flg |= (1U << (ddr_csn * 4 + ch)); + ddrphy_regif_idle(); + } +#else /* DDR_FAST_INIT */ +#endif /* DDR_FAST_INIT */ + } +err_exit: +#ifndef DDR_FAST_INIT + err |= err_flg; +#endif /* DDR_FAST_INIT */ + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01); + foreach_vch(ch) { + dataL = mmio_read_32(DBSC_DBDFICNT(ch)); + dataL &= ~(0x00ffU << 16); + mmio_write_32(DBSC_DBDFICNT(ch), dataL); + ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00); + } + } + return err; +} + +static uint32_t wdqdm_man(void) +{ + uint32_t err, retry_cnt; + uint32_t ch, ddr_csn, mr14_bkup[4][4]; + uint32_t dataL; + const uint32_t retry_max = 0x10; + + dataL = RL + js2[JS2_tDQSCK] + (16 / 2) + 1 - WL + 2 + 2 + 19; + if ((mmio_read_32(DBSC_DBTR(11)) & 0xFF) > dataL) + dataL = (mmio_read_32(DBSC_DBTR(11)) & 0xFF); + ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, dataL); + + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) + || (Prr_Product == PRR_PRODUCT_M3N) || (Prr_Product == PRR_PRODUCT_V3H)) { + ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0, (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); + ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1, (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); + } else { + ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR, (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10); + } + ddr_setval_ach(_reg_PI_TRFC_F0, (mmio_read_32(DBSC_DBTR(13)) & 0x1FF)); + ddr_setval_ach(_reg_PI_TRFC_F1, (mmio_read_32(DBSC_DBTR(13)) & 0x1FF)); + + retry_cnt = 0; + err = 0; + do { + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + err = wdqdm_man1(); + } else { + ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01); + ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x01); + if ((Prr_Product == PRR_PRODUCT_M3N) || (Prr_Product == PRR_PRODUCT_V3H)) + ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x0C); + else + ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C); + dsb_sev(); + err = wdqdm_man1(); + foreach_vch(ch) { + for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { + mr14_bkup[ch][ddr_csn] = ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn]); + dsb_sev(); + } + } + + if ((Prr_Product == PRR_PRODUCT_M3N) || (Prr_Product == PRR_PRODUCT_V3H)) + ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x04); + else + ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04); + pvtcode_update(); + err = wdqdm_man1(); + foreach_vch(ch) { + for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { + mr14_bkup[ch][ddr_csn] = (mr14_bkup[ch][ddr_csn] + ddr_getval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn])) / 2; + ddr_setval(ch, _reg_PI_MR14_DATA_Fx_CSx[1][ddr_csn], mr14_bkup[ch][ddr_csn]); + } + } + + ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x00); + if ((Prr_Product == PRR_PRODUCT_M3N) || (Prr_Product == PRR_PRODUCT_V3H)) { + ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1, 0x00); + ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1, 0x00); + ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, 0x00); + } else { + ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x00); + ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_START_POINT, 0x00); + ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT, 0x00); + } + ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE, 0x00); + + pvtcode_update2(); + err = wdqdm_man1(); + ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00); + } + } while (err && (++retry_cnt < retry_max)); + + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_10))) { + wdqdm_cp(0, 1); + } + + return (retry_cnt >= retry_max); +} + +/******************************************************************************* + * RDQ TRAINING + ******************************************************************************/ +#ifndef DDR_FAST_INIT +static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn) +{ + int32_t i, k; + uint32_t cs, slice; + uint32_t dataL; + + /*********************************************************************** + * clr of training results buffer + ***********************************************************************/ + cs = ddr_csn % 2; + dataL = Boardcnf->dqdm_dly_r; + for (slice = 0; slice < SLICE_CNT; slice++) { + k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) + continue; + for (i = 0; i <= 8; i++) { + if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) { + rdqdm_dly[ch][cs][slice][i] = + rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i]; + rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = + rdqdm_dly[ch][CS_CNT - 1 - cs][slice + SLICE_CNT][i]; + } else { + rdqdm_dly[ch][cs][slice][i] = dataL; + rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL; + } + rdqdm_le[ch][cs][slice][i] = 0; + rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0; + rdqdm_te[ch][cs][slice][i] = 0; + rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0; + rdqdm_nw[ch][cs][slice][i] = 0; + rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0; + } + rdqdm_st[ch][cs][slice] = 0; + rdqdm_win[ch][cs][slice] = 0; + } +} + +static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn) +{ + int32_t i, k; + uint32_t cs, slice; + uint32_t dataL; + uint32_t err; + int8_t _adj; + int16_t adj; + uint32_t dq; + int32_t min_win; + int32_t win; + uint32_t rdq_status_obs_select; + + /*********************************************************************** + * analysis of training results + ***********************************************************************/ + err = 0; + for (slice = 0; slice < SLICE_CNT; slice++) { + k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f; + if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) + continue; + + cs = ddr_csn % 2; + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); + ddrphy_regif_idle(); + + ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX); + ddrphy_regif_idle(); + + for (i = 0; i <= 8; i++) { + dq = slice * 8 + i; + if (i == 8) + _adj = Boardcnf->ch[ch].dm_adj_r[slice]; + else + _adj = Boardcnf->ch[ch].dq_adj_r[dq]; + + adj = _f_scale_adj(_adj); + + dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; + ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], dataL); + rdqdm_dly[ch][cs][slice][i] = dataL; + + dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; + ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], dataL); + rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = dataL; + } + min_win = INT_LEAST32_MAX; + for (i = 0; i <= 8; i++) { + dataL = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS); + rdqdm_st[ch][cs][slice] = dataL; + rdqdm_st[ch][cs][slice + SLICE_CNT] = dataL; + /* k : rise/fall */ + for (k = 0; k < 2; k++) { + if (i == 8) + rdq_status_obs_select = 16 + 8 * k; + else + rdq_status_obs_select = i + 8 * k; + ddr_setval_s(ch, slice, _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT, rdq_status_obs_select); + + dataL = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] = dataL; + + dataL = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] = dataL; + + dataL = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS); + rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] = dataL; + + win = (int32_t)rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] - rdqdm_le[ch][cs][slice + SLICE_CNT * k][i]; + if (i != 8) { + if (min_win > win) + min_win = win; + } + } + } + rdqdm_win[ch][cs][slice] = min_win; + if (min_win <= 0) + err = 2; + } + return(err); +} +#endif /* DDR_FAST_INIT */ + +static uint32_t rdqdm_man1(void) +{ + uint32_t ch; + uint32_t ddr_csn; +#ifdef DDR_FAST_INIT + uint32_t slice; + uint32_t i, adj, dataL; +#endif /* DDR_FAST_INIT */ + uint32_t err; + + /*********************************************************************** + * manual execution of training + ***********************************************************************/ + err = 0; + + for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) { + /* KICK RDQLVL */ + err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ); + if (err) + goto err_exit; +#ifndef DDR_FAST_INIT + foreach_vch(ch) { + if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) { + rdqdm_clr1(ch, ddr_csn); + ddrphy_regif_idle(); + continue; + } + err = rdqdm_ana1(ch, ddr_csn); + ddrphy_regif_idle(); + if (err) + goto err_exit; + } +#else /* DDR_FAST_INIT */ + foreach_vch(ch) { + if (ch_have_this_cs[ddr_csn] & (1U << ch)) { + for (slice = 0; slice < SLICE_CNT; slice++) { + if (ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS) != 0x0D00FFFF) { + err = (1U << ch) | (0x10U << slice); + goto err_exit; + } + } + } + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_10))) { + for (slice = 0; slice < SLICE_CNT; slice++) { + for (i = 0; i <= 8; i++) { + if (i == 8) + adj = _f_scale_adj(Boardcnf->ch[ch].dm_adj_r[slice]); + else + adj = _f_scale_adj(Boardcnf->ch[ch].dq_adj_r[slice * 8 + i]); + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn); + dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj; + ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], dataL); + rdqdm_dly[ch][ddr_csn][slice][i] = dataL; + rdqdm_dly[ch][ddr_csn | 1][slice][i] = dataL; + + dataL = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj; + ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], dataL); + rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = dataL; + rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = dataL; + } + } + } + } + ddrphy_regif_idle(); + +#endif /* DDR_FAST_INIT */ + } + +err_exit: + return err; +} + +static uint32_t rdqdm_man(void) +{ + uint32_t err, retry_cnt; + const uint32_t retry_max = 0x01; + + ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, + 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQ_TSEL_ENABLE)); + ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, + 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQS_TSEL_ENABLE)); + ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, + 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQ_TSEL_SELECT)); + ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, + 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQS_TSEL_SELECT)); + + retry_cnt = 0; + do { + err = rdqdm_man1(); + ddrphy_regif_idle(); + } while (err && (++retry_cnt < retry_max)); + ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE, + ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQ_TSEL_ENABLE)); + ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE, + ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQS_TSEL_ENABLE)); + ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT, + ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQ_TSEL_SELECT)); + ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT, + ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DQS_TSEL_SELECT)); + + return (retry_cnt >= retry_max); +} + +/******************************************************************************* + * rx offset calibration + ******************************************************************************/ +static int32_t _find_change(uint64_t val, uint32_t dir) +{ + int32_t i; + uint32_t startval; + uint32_t curval; + const int32_t VAL_END = 0x3f; + + if (dir == 0) { + startval = (val & 0x01); + for (i = 1; i <= VAL_END; i++) { + curval = (val >> i) & 0x01; + if (curval != startval) + return(i); + } + return(VAL_END); + } else { + startval = (val >> dir) & 0x01; + for (i = dir - 1; i >= 0; i--) { + curval = (val >> i) & 0x01; + if (curval != startval) + return(i); + } + return 0; + } +} + +static uint32_t _rx_offset_cal_updn(uint32_t code) +{ + const uint32_t CODE_MAX = 0x40; + uint32_t tmp; + + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + if (code == 0) + tmp = (1U << 6) | (CODE_MAX - 1); + else if (code <= 0x20) + tmp = ((CODE_MAX - 1 - (0x20 - code) * 2) << 6) | (CODE_MAX - 1); + else + tmp = ((CODE_MAX - 1) << 6) | (CODE_MAX - 1 - (code - 0x20) * 2); + } else { + if (code == 0) + tmp = (1U << 6) | (CODE_MAX - 1); + else + tmp = (code << 6) | (CODE_MAX - code); + } + return tmp; +} + +static uint32_t rx_offset_cal(void) +{ + uint32_t index; + uint32_t code; + const uint32_t CODE_MAX = 0x40; + const uint32_t CODE_STEP = 2; + uint32_t ch, slice; + uint32_t tmp; + uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; + uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM]; + uint64_t tmpval; + int32_t lsb, msb; + + ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01); + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) + val[ch][slice][index] = 0; + } + } + + for (code = 0; code < (CODE_MAX / CODE_STEP); code++) { + tmp = _rx_offset_cal_updn(code * CODE_STEP); + for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) + ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp); + dsb_sev(); + ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as); + + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + tmp = tmp_ach_as[ch][slice]; + for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) { + if (tmp & (1U << index)) + val[ch][slice][index] |= (1ULL << code); + else + val[ch][slice][index] &= ~(1ULL << code); + } + } + } + } + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) { + tmpval = val[ch][slice][index]; + lsb = _find_change(tmpval, 0); + msb = _find_change(tmpval, (CODE_MAX / CODE_STEP) - 1); + tmp = (lsb + msb) >> 1; + + tmp = _rx_offset_cal_updn(tmp * CODE_STEP); + ddr_setval_s(ch, slice, _reg_PHY_RX_CAL_X[index], tmp); + } + } + } + ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); + + return 0; +} + +static uint32_t rx_offset_cal_hw(void) +{ + uint32_t ch, slice; + uint32_t retry; + uint32_t complete; + uint32_t tmp; + uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT]; + + ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00); + ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00); + ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f); + + retry = 0; + while (retry < 4096) { + if ((retry & 0xff) == 0) + ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01); + + foreach_vch(ch) + for (slice = 0; slice < SLICE_CNT; slice++) + tmp_ach_as[ch][slice] = ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]); + + complete = 1; + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + tmp = tmp_ach_as[ch][slice]; + tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f); + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11)) + || (Prr_Product == PRR_PRODUCT_M3N) || (Prr_Product == PRR_PRODUCT_V3H)) { + if (tmp != 0x3E) + complete = 0; + } else { + if (tmp != 0x40) + complete = 0; + } + } + } + if (complete) + break; + + retry++; + } + + return (complete == 0); +} + +/******************************************************************************* + * adjust rddqs latency + ******************************************************************************/ +static void adjust_rddqs_latency(void) +{ + uint32_t ch, slice; + uint32_t dly; + uint32_t maxlatx2; + uint32_t tmp; + uint32_t rdlat_adjx2[SLICE_CNT]; + + foreach_vch(ch) { + maxlatx2 = 0; + for (slice = 0; slice < SLICE_CNT; slice++) { + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, 0x00); + + dly = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_GATE_SLAVE_DELAY); + tmp = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_LATENCY_ADJUST); + /* note gate_slave_delay[9] is always 0 */ + tmp = (tmp << 1) + (dly >> 8); + rdlat_adjx2[slice] = tmp; + if (maxlatx2 < tmp) + maxlatx2 = tmp; + } + maxlatx2 = ((maxlatx2 + 1) >> 1) << 1; + for (slice = 0; slice < SLICE_CNT; slice++) { + tmp = maxlatx2 - rdlat_adjx2[slice]; + tmp = (tmp >> 1); + if (tmp) { + ddr_setval_s(ch, slice, _reg_PHY_RPTR_UPDATE, + ddr_getval_s(ch, slice, _reg_PHY_RPTR_UPDATE) + 1); + } + } + } +} + +/******************************************************************************* + * adjust wpath latency + ******************************************************************************/ +static void adjust_wpath_latency(void) +{ + uint32_t ch, cs, slice; + uint32_t dly; + uint32_t wpath_add; + const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180; + + foreach_vch(ch) { + for (slice = 0; slice < SLICE_CNT; slice += 1) { + for (cs = 0; cs < CS_CNT; cs++) { + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs); + ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX); + dly = ddr_getval_s(ch, slice, _reg_PHY_CLK_WRDQS_SLAVE_DELAY); + if (dly <= _par_EARLY_THRESHOLD_VAL) + continue; + wpath_add = ddr_getval_s(ch, slice, _reg_PHY_WRITE_PATH_LAT_ADD); + ddr_setval_s(ch, slice, _reg_PHY_WRITE_PATH_LAT_ADD, wpath_add - 1); + } + } + } +} + +/******************************************************************************* + * DDR Initialize entry + ******************************************************************************/ +int32_t InitDram(void) +{ + uint32_t ch, cs; + uint32_t dataL; + uint32_t bus_mbps, bus_mbpsdiv; + uint32_t tmp_tccd; + uint32_t failcount; + + /*********************************************************************** + * Thermal sensor setting + ***********************************************************************/ + dataL = mmio_read_32(CPG_MSTPSR5); + if (dataL & (1 << 22)) { /* case THS/TSC Standby */ + dataL &= ~(1 << 22); + cpg_write_32(CPG_SMSTPCR5, dataL); + while ((1 << 22) & mmio_read_32(CPG_MSTPSR5)) /* wait bit = 0 */ + ; + } + + /* THCTR Bit6: PONM = 0 , Bit0: THSST = 0 */ + dataL = mmio_read_32(THS1_THCTR); + if (dataL & 0x00000040U) + dataL = dataL & 0xFFFFFFBEU; + else + dataL = dataL | 0x00000001U; + mmio_write_32(THS1_THCTR, dataL); + + /*********************************************************************** + * Judge product and cut + ***********************************************************************/ +#ifdef RCAR_DDR_FIXED_LSI_TYPE +#if (RCAR_LSI == RCAR_AUTO) + Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; +#else /* RCAR_LSI */ +#ifndef RCAR_LSI_CUT + Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; +#endif /* RCAR_LSI_CUT */ +#endif /* RCAR_LSI */ +#else /* RCAR_DDR_FIXED_LSI_TYPE */ + Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; +#endif /* RCAR_DDR_FIXED_LSI_TYPE */ + + if (Prr_Product == PRR_PRODUCT_H3) { + if (Prr_Cut <= PRR_PRODUCT_11) + pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[0][0]; + else + pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[2][0]; + } else if (Prr_Product == PRR_PRODUCT_M3) { + pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[1][0]; + } else if ((Prr_Product == PRR_PRODUCT_M3N) || (Prr_Product == PRR_PRODUCT_V3H)) { + pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[3][0]; + } else { + FATAL_MSG("DDR:Unknown Product\n"); + return 0xff; + } + + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) { + /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ + } else { + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + } + + /*********************************************************************** + * Judge board type + ***********************************************************************/ + _cnf_BOARDTYPE = boardcnf_get_brd_type(); + if (_cnf_BOARDTYPE >= BOARDNUM) { + FATAL_MSG("DDR:Unknown Board\n"); + return 0xff; + } + Boardcnf = (const struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE]; + +/* RCAR_DRAM_SPLIT_2CH (2U) */ +#if RCAR_DRAM_SPLIT == 2 + /*********************************************************************** + * H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split + ***********************************************************************/ + if ((Prr_Product == PRR_PRODUCT_H3) && (Boardcnf->phyvalid == 0x05)) { + mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006); + ddr_phyvalid = 0x03; + } else { + ddr_phyvalid = Boardcnf->phyvalid; + } +#else//RCAR_DRAM_SPLIT_2CH + ddr_phyvalid = Boardcnf->phyvalid; +#endif//RCAR_DRAM_SPLIT_2CH + + max_density = 0; + + for (cs = 0; cs < CS_CNT; cs++) + ch_have_this_cs[cs] = 0; + + foreach_ech(ch) { + for (cs = 0; cs < CS_CNT; cs++) + ddr_density[ch][cs] = 0xff; + } + + foreach_vch(ch) { + for (cs = 0; cs < CS_CNT; cs++) { + dataL = Boardcnf->ch[ch].ddr_density[cs]; + ddr_density[ch][cs] = dataL; + + if (dataL == 0xff) + continue; + if (dataL > max_density) + max_density = dataL; + if ((cs == 1) && (Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + continue; + ch_have_this_cs[cs] |= (1U << ch); + } + } + + /*********************************************************************** + * Judge board clock frequency (in MHz) + ***********************************************************************/ + boardcnf_get_brd_clk(_cnf_BOARDTYPE, &brd_clk, &brd_clkdiv); + if ((brd_clk / brd_clkdiv) > 25) + brd_clkdiva = 1; + else + brd_clkdiva = 0; + + /*********************************************************************** + * Judge ddr operating frequency clock(in Mbps) + ***********************************************************************/ + boardcnf_get_ddr_mbps(_cnf_BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv); + + ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); + + ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1)); + + /*********************************************************************** + * Adjust tccd + ***********************************************************************/ + dataL = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13; + bus_mbps = 0; + bus_mbpsdiv = 0; + switch (dataL) { + case 0: + bus_mbps = brd_clk * 0x60 * 2; + bus_mbpsdiv = brd_clkdiv * 1; + break; + case 1: + bus_mbps = brd_clk * 0x50 * 2; + bus_mbpsdiv = brd_clkdiv * 1; + break; + case 2: + bus_mbps = brd_clk * 0x40 * 2; + bus_mbpsdiv = brd_clkdiv * 1; + break; + case 3: + bus_mbps = brd_clk * 0x60 * 2; + bus_mbpsdiv = brd_clkdiv * 2; + break; + default: + bus_mbps = brd_clk * 0x60 * 2; + bus_mbpsdiv = brd_clkdiv * 2; + break; + } + tmp_tccd = CLK_DIV(ddr_mbps * 8, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv); + if (8 * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv) + tmp_tccd = tmp_tccd + 1; + + if (tmp_tccd < 8) + ddr_tccd = 8; + else + ddr_tccd = tmp_tccd; + + NOTICE("DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); + + MSG_LF("Start\n"); + + /*********************************************************************** + * PLL Setting + ***********************************************************************/ + pll3_control(1); + + /*********************************************************************** + * initialize DDR + ***********************************************************************/ + dataL = init_ddr(); + if (dataL == ddr_phyvalid) + failcount = 0; + else + failcount = 1; + + foreach_vch(ch) + mmio_write_32(DBSC_DBPDLK(ch), 0x00000000); + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) { + /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ + } else { + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); + } + + if (failcount == 0) + return INITDRAM_OK; + else + return INITDRAM_NG; +} + +void pvtcode_update(void) +{ + uint32_t ch; + uint32_t dataL; + uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init; + int32_t pvtp_tmp, pvtn_tmp; + + foreach_vch(ch) { + pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0) >> 6; + pvtp_init = (tcal.tcomp_cal[ch] & 0x03F) >> 0; + + if (8912 * pvtp_init > 44230) + pvtp_tmp = (5000 + 8912 * pvtp_init - 44230) / 10000; + else + pvtp_tmp = -((-(5000 + 8912 * pvtp_init - 44230)) / 10000); + pvtn_tmp = (5000 + 5776 * pvtn_init + 30280) / 10000; + + pvtn[ch] = pvtn_tmp + pvtn_init; + pvtp[ch] = pvtp_tmp + pvtp_init; + + if (pvtn[ch] > 63) { + pvtn[ch] = 63; + pvtp[ch] = (pvtp_tmp) * (63 - 6 * pvtn_tmp - pvtn_init) / (pvtn_tmp) + 6 * pvtp_tmp + pvtp_init; + } + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + dataL = pvtp[ch] | (pvtn[ch] << 6) | (tcal.tcomp_cal[ch] & 0xfffff000); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), dataL | 0x00020000); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), dataL); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), dataL); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), dataL); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), dataL); + } else { + dataL = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000; + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), dataL | 0x00020000); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), dataL); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), dataL); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), dataL); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), dataL); + } + } +} + +void pvtcode_update2(void) +{ + uint32_t ch; + + foreach_vch(ch) { + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM), tcal.init_cal[ch] | 0x00020000); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM), tcal.init_cal[ch]); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM), tcal.init_cal[ch]); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM), tcal.init_cal[ch]); + reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM), tcal.init_cal[ch]); + } +} + +void ddr_padcal_tcompensate_getinit(uint32_t override) +{ + uint32_t ch; + uint32_t dataL; + uint32_t pvtp, pvtn; + + tcal.init_temp = 0; + for (ch = 0; ch < 4; ch++) { + tcal.init_cal[ch] = 0; + tcal.tcomp_cal[ch] = 0; + } + + foreach_vch(ch) { + tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); + tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]); + } + + if (!override) { + dataL = mmio_read_32(THS1_TEMP); + if (dataL < 2800) + tcal.init_temp = (143 * (int32_t)dataL - 359000) / 1000; + else + tcal.init_temp = (121 * (int32_t)dataL - 296300) / 1000; + + foreach_vch(ch) { + pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F; + pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F; + if ((int32_t)pvtp > ((tcal.init_temp * 29 - 3625) / 1000)) + pvtp = (int32_t)pvtp + ((3625 - tcal.init_temp * 29) / 1000); + else + pvtp = 0; + + if ((int32_t)pvtn > ((tcal.init_temp * 54 - 6750) / 1000)) + pvtn = (int32_t)pvtn + ((6750 - tcal.init_temp * 54) / 1000); + else + pvtn = 0; + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + tcal.init_cal[ch] = (tcal.init_cal[ch] & 0xfffff000) | (pvtn << 6) | (pvtp); + else + tcal.init_cal[ch] = 0x00015000 | (pvtn << 6) | (pvtp); + } + tcal.init_temp = 125; + } +} + +#ifndef ddr_qos_init_setting +/* for QoS init */ +uint8_t get_boardcnf_phyvalid(void) +{ + return ddr_phyvalid; +} +#endif /* ddr_qos_init_setting */ + +/******************************************************************************* + * END + ******************************************************************************/ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram.h new file mode 100644 index 0000000..e0722d9 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef __BOOT_INIT_DRAM_ +#define __BOOT_INIT_DRAM_ + +extern int32_t InitDram(void); +extern int32_t InitDram_regcheck(void); +#define INITDRAM_OK (0) +#define INITDRAM_NG (0xffffffff) +#define INITDRAM_ERR_I (0xffffffff) +#define INITDRAM_ERR_O (0xfffffffe) +#define INITDRAM_ERR_T (0xfffffff0) + +#endif /* __BOOT_INIT_DRAM_*/ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram_config.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram_config.c new file mode 100644 index 0000000..702d015 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram_config.c @@ -0,0 +1,1967 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +/******************************************************************************* + * NUMBER OF BOARD CONFIGRATION + * PLEASE DEFINE + ******************************************************************************/ +#define BOARDNUM 22 +/******************************************************************************* + * PLEASE SET board number or board judge function + ******************************************************************************/ +#define BOARD_JUDGE_AUTO +#ifdef BOARD_JUDGE_AUTO +static uint32_t _board_judge(void); +static uint32_t boardcnf_get_brd_type(void) +{ + return _board_judge(); +} +#else /* BOARD_JUDGE_AUTO */ +static uint32_t boardcnf_get_brd_type(void) +{ + return 1; +} +#endif /* BOARD_JUDGE_AUTO */ + +/******************************************************************************* + * Set DRAM ODT , VREFca , Derating condtition + ******************************************************************************/ +/* #define _def_LPDDR4_ODT 0x36 // MR11 */ +/* #define _def_LPDDR4_ODT 0x66 // MR11 */ +/* #define _def_LPDDR4_VREFCA 0x11 // MR12 */ +/* #define JS2_DERATE 1 // 1: Temperature Derating */ +#define DDR_FAST_INIT + +/******************************************************************************* + * BOARD CONFIGRATION + * PLEASE DEFINE boardcnfs[] + ******************************************************************************/ +struct _boardcnf_ch { + /*0x00... 4Gbit/die ( 2Gb/channel) + *0x01... 6Gbit/die ( 3Gb/channel) + *0x02... 8Gbit/die ( 4Gb/channel) or 4Gb/die (4Gb/channel) + *0x03...12Gbit/die ( 6Gb/channel) or 6Gb/die (6Gb/channel) + *0x04...16Gbit/die ( 8Gb/channel) or 8Gb/die (8Gb/channel) +//non: *0x05...24Gbit/die (12Gb/channel) +//non: *0x06...32Gbit/die (16Gb/channel) + *0xff...NO_MEMORY + */ + uint8_t ddr_density[CS_CNT]; + /* SoC caX([15][14]....[3][2][1][0]) -> MEM caY: */ + uint64_t ca_swap; + /* SoC dqsX([3][2][1][0]) -> MEM dqsY: */ + uint16_t dqs_swap; + /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ + uint32_t dq_swap[SLICE_CNT]; + /* SoC dm -> MEM dqY/dm: (8 means DM) */ + uint8_t dm_swap[SLICE_CNT]; + /* write traing pattern + * (DM,DQ7,....DQ0) x BL16 + */ + uint16_t wdqlvl_patt[16]; + /* delay adjustment is ps */ + int8_t cacs_adj[16]; + int8_t dm_adj_w[SLICE_CNT]; + int8_t dq_adj_w[SLICE_CNT*8]; + int8_t dm_adj_r[SLICE_CNT]; + int8_t dq_adj_r[SLICE_CNT*8]; +}; + +struct _boardcnf { + /* ch in use */ + uint8_t phyvalid; + /* use dbi mode */ + uint8_t dbi_en; + /* default CA/CS delay value */ + uint16_t cacs_dly; + /* default CA/CS delay adjust value in ps */ + int16_t cacs_dly_adj; + /* default DQ/DM delay value for write */ + uint16_t dqdm_dly_w; + /* default DQ/DM delay value for read */ + uint16_t dqdm_dly_r; + struct _boardcnf_ch ch[DRAM_CH_CNT]; +}; +/* write traing pattern + * (DM,DQ7,....DQ0) x BL16 + */ +#define WDQLVL_PAT {\ + 0x00AA,\ + 0x0055,\ + 0x00AA,\ + 0x0155,\ + 0x01CC,\ + 0x0133,\ + 0x00CC,\ + 0x0033,\ + 0x00F0,\ + 0x010F,\ + 0x01F0,\ + 0x010F,\ + 0x00F0,\ + 0x00F0,\ + 0x000F,\ + 0x010F} + +static const struct _boardcnf boardcnfs[BOARDNUM] = { +/* + * boardcnf[0] RENESAS SALVATOR-X board with M3-W/SIP + */ +{ + 0x03, /* phyvalid */ + 0x01, /* dbi_en */ + 0x02c0, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x70612543, 0x43251670, 0x45326170, 0x10672534 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x01327654, 0x34526107, 0x35421670, 0x70615324 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[1] RENESAS KRIEK board with M3-W/SoC + */ +{ + 0x03, /* phyvalid */ + 0x01, /* dbi_en */ + 0x02c0, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00345201, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00302154, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[2] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 1rank) + */ +{ + 0x0f, /* phyvalid */ + 0x00, /* dbi_en */ + 0x0300, /* cacs_dly */ + -320, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x3210, +/*dq_swap[]*/ { 0x20741365, 0x34256107, 0x57460321, 0x70614532 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x3102, +/*dq_swap[]*/ { 0x23547610, 0x34526107, 0x67452310, 0x32106754 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[2]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x0213, +/*dq_swap[]*/ { 0x30216754, 0x67453210, 0x70165243, 0x07162345 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[3]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x0213, +/*dq_swap[]*/ { 0x01327654, 0x70615432, 0x54760123, 0x07162345 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[3] RENESAS Starter Kit board with M3-W/SIP(8Gbit 1rank) + */ +{ + 0x03, /* phyvalid */ + 0x01, /* dbi_en */ + 0x02c0, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, /* M3-W/SIP(8Gbit 1rank) */ +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x70612543, 0x43251670, 0x45326170, 0x10672534 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, /* M3-W/SIP(8Gbit 1rank) */ +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x01327654, 0x34526107, 0x35421670, 0x70615324 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[4] RENESAS SALVATOR-M(1rank) board with H3 Ver.1.x/SoC + */ +{ + 0x0f, /* phyvalid */ + 0x00, /* dbi_en */ + 0x02c0, /* cacs_dly */ + -320, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00315024, +/*dqs_swap*/ 0x3120, +/*dq_swap[]*/ { 0x30671254, 0x26541037, 0x17054623, 0x12307645 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00025143, +/*dqs_swap*/ 0x3210, +/*dq_swap[]*/ { 0x70613542, 0x16245307, 0x30712645, 0x21706354 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[2]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00523104, +/*dqs_swap*/ 0x2301, +/*dq_swap[]*/ { 0x70613542, 0x16245307, 0x30712645, 0x21706354 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[3]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00153402, +/*dqs_swap*/ 0x2031, +/*dq_swap[]*/ { 0x30671254, 0x26541037, 0x17054623, 0x12307645 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[5] RENESAS KRIEK-1rank board with M3-W/SoC + */ +{ + 0x03, /* phyvalid */ + 0x01, /* dbi_en */ + 0x02c0, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00345201, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00302154, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[6] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 2rank) + */ +{ + 0x0f, /* phyvalid */ + 0x00, /* dbi_en */ + 0x0300, /* cacs_dly */ + -320, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x3210, +/*dq_swap[]*/ { 0x20741365, 0x34256107, 0x57460321, 0x70614532 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x3102, +/*dq_swap[]*/ { 0x23547610, 0x34526107, 0x67452310, 0x32106754 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[2]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x0213, +/*dq_swap[]*/ { 0x30216754, 0x67453210, 0x70165243, 0x07162345 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[3]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x0213, +/*dq_swap[]*/ { 0x01327654, 0x70615432, 0x54760123, 0x07162345 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[7] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 1rank) + */ +{ + 0x0f, /* phyvalid */ + 0x01, /* dbi_en */ + 0x0300, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x70631425, 0x34527016, 0x43527610, 0x32104567 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00105432, +/*dqs_swap*/ 0x3210, +/*dq_swap[]*/ { 0x43256107, 0x07162354, 0x10234567, 0x01235467 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[2]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2301, +/*dq_swap[]*/ { 0x01327654, 0x02316457, 0x10234567, 0x01325467 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[3]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2301, +/*dq_swap[]*/ { 0x12034765, 0x23105467, 0x23017645, 0x32106745 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[8] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(8Gbit 2rank) + */ +{ +#if RCAR_DRAM_CHANNEL == 5 + 0x05, /* phyvalid */ +#else /* RCAR_DRAM_CHANNEL!=5 */ + 0x0f, /* phyvalid */ +#endif /* RCAR_DRAM_CHANNEL */ + 0x01, /* dbi_en */ + 0x0300, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x70631425, 0x34527016, 0x43527610, 0x32104567 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +#if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2)) +/*ch[1]*/ { /* copy from ch[2] (for DRAM_SPLIT_2CH) */ +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2301, +/*dq_swap[]*/ { 0x01327654, 0x02316457, 0x10234567, 0x01325467 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +#else /* (RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2) */ +/*ch[1]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00105432, +/*dqs_swap*/ 0x3210, +/*dq_swap[]*/ { 0x43256107, 0x07162354, 0x10234567, 0x01235467 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +#endif /* (RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2) */ +/*ch[2]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2301, +/*dq_swap[]*/ { 0x01327654, 0x02316457, 0x10234567, 0x01325467 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[3]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2301, +/*dq_swap[]*/ { 0x12034765, 0x23105467, 0x23017645, 0x32106745 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[9] RENESAS SALVATOR-MS(1rank) board with H3 Ver.2.0 or later/SoC + */ +{ + 0x0f, /* phyvalid */ + 0x01, /* dbi_en */ + 0x0300, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x3210, +/*dq_swap[]*/ { 0x27645310, 0x75346210, 0x53467210, 0x23674510 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2301, +/*dq_swap[]*/ { 0x23764510, 0x43257610, 0x43752610, 0x37652401 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ /* { 0, 0, 0, 0, 0, 0, 0, 0, */ +/*cacs_adj*/ { -128, -128, -128, -128, -128, -128, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[2]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00452103, +/*dqs_swap*/ 0x3210, +/*dq_swap[]*/ { 0x32764510, 0x43257610, 0x43752610, 0x26573401 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[3]*/ { +/*ddr_density[]*/ { 0x02, 0xff }, +/*ca_swap*/ 0x00520413, +/*dqs_swap*/ 0x2301, +/*dq_swap[]*/ { 0x47652301, 0x75346210, 0x53467210, 0x32674501 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ /* { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, */ +/*cacs_adj*/ { 30, 30, 30, 30, 30, 30, 30, 30, + 30, 30 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[10] RENESAS Kriek(2rank) board with M3-N/SoC + */ +{ + 0x01, /* phyvalid */ + 0x01, /* dbi_en */ + 0x0300, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00345201, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[11] RENESAS SALVATOR-X board with M3-N/SIP(8Gbit 2rank) + */ +{ + 0x01, /* phyvalid */ + 0x01, /* dbi_en */ + 0x0300, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +#if (RCAR_DRAM_LPDDR4_MEMCONF == 2) +/*ddr_density[]*/ { 0x04, 0x04 }, +#else +/*ddr_density[]*/ { 0x02, 0x02 }, +#endif +/*ca_swap*/ 0x00342501, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x10672534, 0x43257106, 0x34527601, 0x71605243 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[12] RENESAS CONDOR board with V3H/SoC + */ +{ + 0x01, /* phyvalid */ + 0x01, /* dbi_en */ + 0x0300, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*//* { 0x00, 0x00 }, */ +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00501342, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x70562134, 0x34526071, 0x23147506, 0x12430567 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[13] RENESAS KRIEK board with PM3/SoC + */ +{ + 0x05, /* phyvalid */ + 0x00, /* dbi_en */ + 0x02c0, /* cacs_dly */ + -320, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00345201, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { /* for DRAM_SPLIT_2CH */ +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00302154, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[2]*/ { /* for DRAM_SPLIT_NON */ +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00302154, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[3]*/ { /* Dummy */ +/*ddr_density[]*/ { 0xff, 0xff }, +/*ca_swap*/ 0, +/*dqs_swap*/ 0, +/*dq_swap[]*/ { 0, 0, 0, 0 }, +/*dm_swap[]*/ { 0, 0, 0, 0 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[14] RENESAS SALVATOR-X board with H3 Ver.2.0 or later/SIP(16Gbit 1rank) + */ +{ +#if RCAR_DRAM_CHANNEL == 5 + 0x05, /* phyvalid */ +#else /* RCAR_DRAM_CHANNEL!=5 */ + 0x0f, /* phyvalid */ +#endif /* RCAR_DRAM_CHANNEL */ + 0x01, /* dbi_en */ + 0x0300, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x04, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x70631425, 0x34527016, 0x43527610, 0x32104567 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +#if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2)) +/*ch[1]*/ { /* copy from ch[2] (for DRAM_SPLIT_2CH) */ +/*ddr_density[]*/ { 0x04, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2301, +/*dq_swap[]*/ { 0x01327654, 0x02316457, 0x10234567, 0x01325467 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +#else /* (RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2) */ +/*ch[1]*/ { +/*ddr_density[]*/ { 0x04, 0xff }, +/*ca_swap*/ 0x00105432, +/*dqs_swap*/ 0x3210, +/*dq_swap[]*/ { 0x43256107, 0x07162354, 0x10234567, 0x01235467 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +#endif /* (RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2) */ +/*ch[2]*/ { +/*ddr_density[]*/ { 0x04, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2301, +/*dq_swap[]*/ { 0x01327654, 0x02316457, 0x10234567, 0x01325467 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[3]*/ { +/*ddr_density[]*/ { 0x04, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2301, +/*dq_swap[]*/ { 0x12034765, 0x23105467, 0x23017645, 0x32106745 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[15] RENESAS KRIEK board with H3N + */ +{ + 0x05, /* phyvalid */ + 0x01, /* dbi_en */ + 0x0300, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00345201, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x01672543, 0x45367012, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { /* for DRAM_SPLIT_2CH */ +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00302154, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[2]*/ { /* for DRAM_SPLIT_NON */ +/*ddr_density[]*/ { 0x02, 0x02 }, +/*ca_swap*/ 0x00302154, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[3]*/ { /* Dummy */ +/*ddr_density[]*/ { 0xff, 0xff }, +/*ca_swap*/ 0, +/*dqs_swap*/ 0, +/*dq_swap[]*/ { 0, 0, 0, 0 }, +/*dm_swap[]*/ { 0, 0, 0, 0 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC + */ +{ + 0x03, /* phyvalid */ + 0x01, /* dbi_en */ + 0x0320, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x04, 0x04 }, +/*ca_swap*/ 0x520314FFFF523041, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234}, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { +/*ddr_density[]*/ { 0x04, 0x04 }, +/*ca_swap*/ 0x314250FFFF312405, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC + */ +{ + 0x01, /* phyvalid */ + 0x01, /* dbi_en */ + 0x0300, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x04, 0x04 }, +/*ca_swap*/ 0x520314FFFF523041, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234}, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[18] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 2rank) + */ +{ + 0x03, /* phyvalid */ + 0x01, /* dbi_en */ + 0x02c0, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x04, 0x04 }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x70612543, 0x43251670, 0x45326170, 0x10672534 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { +/*ddr_density[]*/ { 0x04, 0x04 }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x01327654, 0x34526107, 0x35421670, 0x70615324 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[19] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 1rank) + */ +{ + 0x03, /* phyvalid */ + 0x01, /* dbi_en */ + 0x02c0, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x04, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x70612543, 0x43251670, 0x45326170, 0x10672534 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { +/*ddr_density[]*/ { 0x04, 0xff }, +/*ca_swap*/ 0x00543210, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x01327654, 0x34526107, 0x35421670, 0x70615324 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[20] RENESAS KRIEK 16Gbit/2rank/2ch board with M3-W/SoC + */ +{ + 0x03, /* phyvalid */ + 0x01, /* dbi_en */ + 0x02c0, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x04, 0x04 }, +/*ca_swap*/ 0x00345201, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { +/*ddr_density[]*/ { 0x04, 0x04 }, +/*ca_swap*/ 0x00302154, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +}, +/* + * boardcnf[21] RENESAS KRIEK 16Gbit/1rank/2ch board with M3-W/SoC + */ +{ + 0x03, /* phyvalid */ + 0x01, /* dbi_en */ + 0x02c0, /* cacs_dly */ + 0, /* cacs_dly_adj */ + 0x0300, /* dqdm_dly_w */ + 0x00a0, /* dqdm_dly_r */ + { +/*ch[0]*/ { +/*ddr_density[]*/ { 0x04, 0xff }, +/*ca_swap*/ 0x00345201, +/*dqs_swap*/ 0x3201, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + }, +/*ch[1]*/ { +/*ddr_density[]*/ { 0x04, 0xff }, +/*ca_swap*/ 0x00302154, +/*dqs_swap*/ 0x2310, +/*dq_swap[]*/ { 0x01672543, 0x45361207, 0x45632107, 0x60715234 }, +/*dm_swap[]*/ { 0x08, 0x08, 0x08, 0x08 }, +/*wdqlvl_patt[]*/ WDQLVL_PAT, +/*cacs_adj*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0 }, +/*dm_adj_w*/ { 0, 0, 0, 0 }, +/*dqdm_adj_w*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 }, +/*dm_adj_r*/ { 0, 0, 0, 0 }, +/*dqdm_adj_r*/ { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 } + } + } +} +}; + +/******************************************************************************* + * EXTAL CLOCK DEFINITION + * PLEASE DEFINE HOW TO JUDGE BOARD CLK + ******************************************************************************/ +/* + * RENESAS SALVATOR/KRIEK BOARD EXAMPLE + * judge by md14/md13 + * + * 16.66MHz CLK,DIV= 50,3 (md14,md13==0,0) + * 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1) + * 25.00MHz CLK,DIV= 75,3 (md14,md13==1,0) + * 16.66MHz CLK,DIV= 50,3 (md14,md13==1,1) // only for H3 Ver.1.0 + * 33.33MHz CLK,DIV=100,3 (md14,md13==1,1) + */ +void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) +{ + uint32_t md; + + if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut == PRR_PRODUCT_10)) { + *clk = 50; + *div = 3; + } else { + md = (mmio_read_32(RST_MODEMR) >> 13) & 0x3; + switch (md) { + case 0x0: + *clk = 50; + *div = 3; + break; + case 0x1: + *clk = 60; + *div = 3; + break; + case 0x2: + *clk = 75; + *div = 3; + break; + case 0x3: + *clk = 100; + *div = 3; + break; + } + } + (void)brd; +} + +/******************************************************************************* + * DDR MBPS TARGET + * PLEASE DEFINE HOW TO JUDGE DDR BPS + ******************************************************************************/ +/* + * DDRxxxx (judge_ by md19,17) : 0 + * DDR3200 (md19,17==0,0) : 3200 + * DDR2800 (md19,17==0,1) : 2800 + * DDR2400 (md19,17==1,0) : 2400 + * DDR1600 (md19,17==1,1) : 1600 + */ +void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div) +{ + uint32_t md; + + if (Prr_Product == PRR_PRODUCT_V3H) { + md = (mmio_read_32(RST_MODEMR) >> 19) & 0x01; + switch (md) { + case 0x0: + *mbps = 3200; + *div = 1; + break; + case 0x1: + *mbps = 1600; + *div = 1; + break; + } + } else { + md = (mmio_read_32(RST_MODEMR) >> 17) & 0x05; + md = (md | (md >> 1)) & 0x03; + switch (md) { + case 0x0: + *mbps = 3200; + *div = 1; + break; + case 0x1: + *mbps = 2800; + *div = 1; + break; + case 0x2: + *mbps = 2400; + *div = 1; + break; + case 0x3: + *mbps = 1600; + *div = 1; + break; + } + } + (void)brd; +} + +/******************************************************************************* + * REFRESH TARGET DEFINITION + * PLEASE DEFINE _def_REFPERIOD (in ns) + ******************************************************************************/ +/* WARN: do not modify in this IPL version */ +/* #define _def_REFPERIOD 1890 */ + +/******************************************************************************* + * PREDEFINED TERM CODE by chip id + ******************************************************************************/ +#define M3_SAMPLE_TT_A84 0xB866CC10, 0x3B250421 +#define M3_SAMPLE_TT_A85 0xB866CC10, 0x3AA50421 +#define M3_SAMPLE_TT_A86 0xB866CC10, 0x3AA48421 +#define M3_SAMPLE_FF_B45 0xB866CC10, 0x3AB00C21 +#define M3_SAMPLE_FF_B49 0xB866CC10, 0x39B10C21 +#define M3_SAMPLE_FF_B56 0xB866CC10, 0x3AAF8C21 +#define M3_SAMPLE_SS_E24 0xB866CC10, 0x3BA39421 +#define M3_SAMPLE_SS_E28 0xB866CC10, 0x3C231421 +#define M3_SAMPLE_SS_E32 0xB866CC10, 0x3C241421 +static const uint32_t TermcodeBySample[20][3] = { + { M3_SAMPLE_TT_A84, 0x000158D5 }, + { M3_SAMPLE_TT_A85, 0x00015955 }, + { M3_SAMPLE_TT_A86, 0x00015955 }, + { M3_SAMPLE_FF_B45, 0x00015690 }, + { M3_SAMPLE_FF_B49, 0x00015753 }, + { M3_SAMPLE_FF_B56, 0x00015793 }, + { M3_SAMPLE_SS_E24, 0x00015996 }, + { M3_SAMPLE_SS_E28, 0x000159D7 }, + { M3_SAMPLE_SS_E32, 0x00015997 }, + { 0xFFFFFFFF, 0xFFFFFFFF, 0x0001554F } +}; +#ifdef BOARD_JUDGE_AUTO +/******************************************************************************* + * SAMPLE board detect function + ******************************************************************************/ +#if defined(__RH850G3K__) +#define PFC_BASE (BASE_PFC_ADDR) +#define GPIO_BASE (BASE_GPIO_ADDR) +#else +#define PFC_BASE (0xE6060000U) +#define GPIO_BASE (0xE6050000U) +#endif +/* R/W 32 LSI Multiplexed Pin Setting Mask Register */ +#define PFC_PMMR (PFC_BASE + 0x0000U) +/* R/W 32 LSI pin pull-enable register 5 */ +#define PFC_PUEN5 (PFC_BASE + 0x0414U) +/* R/W 32 LSI pin pull-enable register 6 */ +#define PFC_PUEN6 (PFC_BASE + 0x0418U) +/* R/W 32 LSI pin pull-up/down control register 5 */ +#define PFC_PUD5 (PFC_BASE + 0x0454U) +/* R/W 32 LSI pin pull-up/down control register 6 */ +#define PFC_PUD6 (PFC_BASE + 0x0458U) +/* R 32 General input register 5 */ +#define GPIO_INDT5 (GPIO_BASE + 0x500CU) +/* R 32 General input register 6 */ +#define GPIO_INDT6 (GPIO_BASE + 0x540CU) + +#define BIT25 (1U << 25) +#define BIT22 (1U << 22) +#define BIT15 (1U << 15) +#define BIT0 (1U) +#define GPIO_GPSR6 (PFC_BASE + 0x0118U) + +#if (RCAR_GEN3_ULCB == 0) +static void pfc_write_and_poll(uint32_t a, uint32_t v) +{ + mmio_write_32(PFC_PMMR, ~v); + v = ~mmio_read_32(PFC_PMMR); + mmio_write_32(a, v); + while (v != mmio_read_32(a)) + ; + dsb_sev(); +} +#endif + +#ifndef RCAR_GEN3_ULCB +#define RCAR_GEN3_ULCB 0 +#endif + +#if (RCAR_GEN3_ULCB == 0) /* non Starter Kit */ +/* + * Connect = return 0 + * Open = return 1 + */ +static uint32_t opencheck_SSI_WS6(void) +{ + uint32_t dataL, down, up; + uint32_t gpsr6_bak; + uint32_t puen5_bak; + uint32_t pud5_bak; + + gpsr6_bak = mmio_read_32(GPIO_GPSR6); + puen5_bak = mmio_read_32(PFC_PUEN5); + pud5_bak = mmio_read_32(PFC_PUD5); + dsb_sev(); + + dataL = (gpsr6_bak & ~BIT15); + pfc_write_and_poll(GPIO_GPSR6, dataL); + + /* Pull-Up/Down Enable (PUEN5[22]=1) */ + dataL = puen5_bak; + dataL |= (BIT22); + pfc_write_and_poll(PFC_PUEN5, dataL); + + /* Pull-Down-Enable (PUD5[22]=0, PUEN5[22]=1) */ + dataL = pud5_bak; + dataL &= ~(BIT22); + pfc_write_and_poll(PFC_PUD5, dataL); + /* GPSR6[15]=SSI_WS6 */ + micro_wait(10); + down = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1; + dsb_sev(); + + /* Pull-Up-Enable (PUD5[22]=1, PUEN5[22]=1) */ + dataL = pud5_bak; + dataL |= (BIT22); + pfc_write_and_poll(PFC_PUD5, dataL); + /* GPSR6[15]=SSI_WS6 */ + micro_wait(10); + up = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1; + + dsb_sev(); + + pfc_write_and_poll(GPIO_GPSR6, gpsr6_bak); + pfc_write_and_poll(PFC_PUEN5, puen5_bak); + pfc_write_and_poll(PFC_PUD5, pud5_bak); + + /* Compare */ + if (down == up) { + /* Same = Connect */ + return 0; + } else { + /* Diff = Open */ + return 1; + } +} + +#endif /* (RCAR_GEN3_ULCB == 0) */ + +static uint32_t _board_judge(void) +{ + uint32_t brd; + +#if (RCAR_GEN3_ULCB == 1) + /* Starter Kit */ + if (Prr_Product == PRR_PRODUCT_H3) { + if (Prr_Cut <= PRR_PRODUCT_11) { + /* RENESAS Starter Kit(H3 Ver.1.x/SIP) board */ + brd = 2; + } else { + /* RENESAS Starter Kit(H3 Ver.2.0 or later/SIP) board */ +#if (RCAR_DRAM_LPDDR4_MEMCONF == 0) + brd = 7; /* 8Gbit/1rank */ +#else + brd = 8; /* 8Gbit/2rank */ +#endif + } + } else if (Prr_Product == PRR_PRODUCT_M3) { + if (Prr_Cut >= PRR_PRODUCT_30) { + /* RENESAS Starter Kit (M3-W Ver.3.0/SIP) */ + brd = 18; + } else { + /* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */ + brd = 3; + } + } else { + /* RENESAS Starter Kit(M3-N/SIP) board */ + brd = 11; + } +#else /* not (RCAR_GEN3_ULCB == 1) */ + uint32_t usb2_ovc_open; + + usb2_ovc_open = opencheck_SSI_WS6(); + + /* RENESAS Eva-board */ + brd = 99; + if (Prr_Product == PRR_PRODUCT_V3H) { + /* RENESAS Condor board */ + brd = 12; + } else if (usb2_ovc_open) { + if (Prr_Product == PRR_PRODUCT_M3N) { + /* RENESAS Kriek board with M3-N */ + brd = 10; + } else if (Prr_Product == PRR_PRODUCT_M3) { + /* RENESAS Kriek board with M3-W */ + brd = 1; + } else if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) { + /* RENESAS Kriek board with PM3 */ + brd = 13; + } else if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_20)) { + /* RENESAS Kriek board with H3N */ + brd = 15; + } + } else { + if (Prr_Product == PRR_PRODUCT_H3) { + if (Prr_Cut <= PRR_PRODUCT_11) { + /* RENESAS SALVATOR-X (H3 Ver.1.x/SIP) */ + brd = 2; + } else if (Prr_Cut < PRR_PRODUCT_30) { + /* RENESAS SALVATOR-X (H3 Ver.2.0/SIP) */ + brd = 7; /* 8Gbit/1rank */ + } else { + /* RENESAS SALVATOR-X (H3 Ver.3.0/SIP) */ +#if (RCAR_DRAM_LPDDR4_MEMCONF == 0) + brd = 7; /* 8Gbit/1rank */ +#else + brd = 8; /* 8Gbit/2rank */ + /* brd = 14; 16Gbit/1rank */ +#endif + } + } else if (Prr_Product == PRR_PRODUCT_M3N) { + /* RENESAS SALVATOR-X (M3-N/SIP) */ + brd = 11; + } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut <= PRR_PRODUCT_20)) { + /* RENESAS SALVATOR-X (M3-W/SIP) */ + brd = 0; + } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) { + /* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */ + brd = 19; + } else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) { + /* RENESAS SALVATOR-X (M3-W Ver.3.0/SIP) */ + brd = 18; + } + } +#endif /* (RCAR_GEN3_ULCB == 1) */ + + return brd; +} +#endif diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram_regcheck.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram_regcheck.c new file mode 100644 index 0000000..e5d221e --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram_regcheck.c @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#include +#include +#include + +#include "boot_init_dram.c" +#include "init_dram_tbl_chk.h" + +int32_t InitDram_regcheck(void) +{ + int32_t err; + + uint32_t i; + uint32_t phytype, dataL, ch, slice; + + err = 0; + + if (Prr_Product == PRR_PRODUCT_H3) { + if (Prr_Cut <= PRR_PRODUCT_11) { + phytype = 0; + } else { + phytype = 2; + } + } else if (Prr_Product == PRR_PRODUCT_M3) { + phytype = 1; + } else { + phytype = 3; + } + + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) { + /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ + } else { + mmio_write_32(DBSC_DBSYSCNT0, 0x00001234); + } + + /* Unlock DDRPHY register */ + foreach_vch(ch) + mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A); + dsb_sev(); + + for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM; i++) { + if (DDR_PHY_SLICE_REGCHK[phytype][i/32] & (1U << (i%32))) { + foreach_vch(ch) { + for (slice = 0; slice < 4; slice++) { + dataL = reg_ddrphy_read(ch, i + DDR_PHY_SLICE_REGSET_OFS + DDR_PHY_SLICE_REGSET_SIZE * slice); + if (dataL != _cnf_DDR_PHY_SLICE_REGSET[i]) { + ERROR("PHY REG ch%d(data slice)[0x%04x] = 0x%08x -> 0x%08x\n", + ch, i+DDR_PHY_SLICE_REGSET_OFS + DDR_PHY_SLICE_REGSET_SIZE * slice, + _cnf_DDR_PHY_SLICE_REGSET[i], dataL); + err = 1; + } + } + } + } + } + + for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { + if (DDR_PHY_ADR_V_REGCHK[phytype][i/32] & (1U << (i%32))) { + foreach_vch(ch) { + dataL = reg_ddrphy_read(ch, i + DDR_PHY_ADR_V_REGSET_OFS); + if (dataL != _cnf_DDR_PHY_ADR_V_REGSET[i]) { + ERROR("PHY REG ch%d(addr slice)[0x%04x] = 0x%08x -> 0x%08x\n", + ch, i+DDR_PHY_ADR_V_REGSET_OFS, + _cnf_DDR_PHY_ADR_V_REGSET[i], dataL); + err = 1; + } + } + } + } + +// for (i = 0; i < DDR_PHY_ADR_I_REGSET_NUM; i++) { +// if (DDR_PHY_ADR_I_REGCHK[phytype][i/32] & (1U << (i%32))) { +// foreach_vch(ch) { +// dataL = reg_ddrphy_read(ch, i + DDR_PHY_ADR_I_REGSET_OFS); +// if (dataL != _cnf_DDR_PHY_ADR_I_REGSET[i]) { +// ERROR("PHY REG ch%d(addr slice)[0x%04x] = 0x%08x -> 0x%08x\n", +// ch, i+DDR_PHY_ADR_I_REGSET_OFS, +// _cnf_DDR_PHY_ADR_I_REGSET[i], dataL); +// err = 1; +// } +// } +// } +// } + + for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) { + if (DDR_PHY_ADR_G_REGCHK[phytype][i/32] & (1U << (i%32))) { + foreach_vch(ch) { + dataL = reg_ddrphy_read(ch, i + DDR_PHY_ADR_G_REGSET_OFS); + if (dataL != _cnf_DDR_PHY_ADR_G_REGSET[i]) { + ERROR("PHY REG ch%d(addr slice)[0x%04x] = 0x%08x -> 0x%08x\n", + ch, i+DDR_PHY_ADR_G_REGSET_OFS, + _cnf_DDR_PHY_ADR_G_REGSET[i], dataL); + err = 1; + } + } + } + } + + for (i = 0; i < DDR_PI_REGSET_NUM; i++) { + if (DDR_PI_REGCHK[phytype][i/32] & (1U << (i%32))) { + foreach_vch(ch) { + dataL = reg_ddrphy_read(ch, i + DDR_PI_REGSET_OFS); + if (dataL != _cnf_DDR_PI_REGSET[i]) { + ERROR("PI REG ch%d[0x%04x] = 0x%08x -> 0x%08x\n", + ch, i+DDR_PI_REGSET_OFS, + _cnf_DDR_PI_REGSET[i], dataL); + err = 1; + } + } + } + } + + foreach_vch(ch) + mmio_write_32(DBSC_DBPDLK(ch), 0x00000000); + + if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) + || ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30))) { + /* non : H3 Ver.1.x/M3-W Ver.1.x not support */ + } else { + mmio_write_32(DBSC_DBSYSCNT0, 0x00000000); + } + + return err; +} diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram_regdef.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram_regdef.h new file mode 100644 index 0000000..4dce6cb --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/boot_init_dram_regdef.h @@ -0,0 +1,369 @@ +/* + * Copyright (c) 2015-2022, Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#include "remap_register.h" +#else +#include +#include +#endif + +#define RCAR_DDR_VERSION "rev.0.42" +#define DRAM_CH_CNT 0x04 +#define SLICE_CNT 0x04 +#define CS_CNT 0x02 +/* order : CS0A, CS0B, CS1A, CS1B */ +#define CSAB_CNT (CS_CNT * 2) +/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */ +#define CHAB_CNT (DRAM_CH_CNT * 2) + +/* for pll setting */ +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) +#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb))) + +/* for ddr deisity setting */ +#define DBMEMCONF_REG(d3, row, bank, col, dw) (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw)) +#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (29 - 3 - 10 - 2), 3, 10, 2)) +#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) + +/* refresh mode */ +#define DBSC_REFINTS 0x0 /* 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. */ + +/* system registers */ +#if defined(__RH850G3K__) +#define CPG_BASE (BASE_CPG_ADDR) +#else +#define CPG_BASE (0xE6150000U) +#endif +#define CPG_FRQCRB (CPG_BASE + 0x0004U) + +#define CPG_PLLECR (CPG_BASE + 0x00D0U) +#define CPG_MSTPSR5 (CPG_BASE + 0x003CU) /* R 32 Module stop status register 5 */ +#define CPG_SRCR4 (CPG_BASE + 0x00BCU) +#define CPG_PLL3CR (CPG_BASE + 0x00DCU) +#define CPG_ZB3CKCR (CPG_BASE + 0x0380U) +#define CPG_FRQCRD (CPG_BASE + 0x00E4U) +#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U) /* R/W 32 System module stop control register 5 */ +#define CPG_CPGWPR (CPG_BASE + 0x0900U) +#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U) + +#define CPG_FRQCRB_KICK_BIT (1U<<31) +#define CPG_PLLECR_PLL3E_BIT (1U<<3) +#define CPG_PLLECR_PLL3ST_BIT (1U<<11) +#define CPG_ZB3CKCR_ZB3ST_BIT (1U<<11) + +#if defined(__RH850G3K__) +#define RST_BASE (BASE_RESET_ADDR) +#else +#define RST_BASE (0xE6160000U) +#endif +#define RST_MODEMR (RST_BASE + 0x0060U) + +/* chip_id and calibration code */ +#if defined(__RH850G3K__) +#define LIFEC_CHIPID(x) (BASE_LIFEC_ADDR + 0x40U + (x) * 4) +#else +#define LIFEC_CHIPID(x) (0xE6110040U+(x)*4) +#endif + +/* Product Register */ +#if defined(__RH850G3K__) +#define PRR (BASE_PRR_ADDR) +#else +#define PRR (0xFFF00044U) +#endif +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) +#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */ +#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3-W */ +#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3-N */ +#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */ +#define PRR_PRODUCT_10 (0x00U) /* Ver.1.0 */ +#define PRR_PRODUCT_11 (0x01U) /* Ver.1.1 */ +#define PRR_PRODUCT_20 (0x10U) /* Ver.2.0 */ +#define PRR_PRODUCT_30 (0x20U) /* Ver.3.0 */ + +/* DBSC registers */ +#define DBSC_DBSYSCONF1 (DBSC_BASE + 0x0004U) +#define DBSC_DBPHYCONF0 (DBSC_BASE + 0x0010U) +#define DBSC_DBKIND (DBSC_BASE + 0x0020U) + +#define DBSC_DBMEMCONF(ch, cs) (DBSC_DBMEMCONF_0_0 + 0x10U * ch + 0x04U * cs) +#define DBSC_DBMEMCONF_0_0 (DBSC_BASE + 0x0030U) +#define DBSC_DBMEMCONF_0_1 (DBSC_BASE + 0x0034U) +#define DBSC_DBMEMCONF_0_2 (DBSC_BASE + 0x0038U) +#define DBSC_DBMEMCONF_0_3 (DBSC_BASE + 0x003CU) +#define DBSC_DBMEMCONF_1_2 (DBSC_BASE + 0x0048U) +#define DBSC_DBMEMCONF_1_3 (DBSC_BASE + 0x004CU) +#define DBSC_DBMEMCONF_1_0 (DBSC_BASE + 0x0040U) +#define DBSC_DBMEMCONF_1_1 (DBSC_BASE + 0x0044U) +#define DBSC_DBMEMCONF_2_0 (DBSC_BASE + 0x0050U) +#define DBSC_DBMEMCONF_2_1 (DBSC_BASE + 0x0054U) +#define DBSC_DBMEMCONF_2_2 (DBSC_BASE + 0x0058U) +#define DBSC_DBMEMCONF_2_3 (DBSC_BASE + 0x005CU) +#define DBSC_DBMEMCONF_3_0 (DBSC_BASE + 0x0060U) +#define DBSC_DBMEMCONF_3_1 (DBSC_BASE + 0x0064U) +#define DBSC_DBMEMCONF_3_2 (DBSC_BASE + 0x0068U) +#define DBSC_DBMEMCONF_3_3 (DBSC_BASE + 0x006CU) + +#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U) + +#define DBSC_DBACEN (DBSC_BASE + 0x0200U) +#define DBSC_DBRFEN (DBSC_BASE + 0x0204U) +#define DBSC_DBCMD (DBSC_BASE + 0x0208U) +#define DBSC_DBWAIT (DBSC_BASE + 0x0210U) +#define DBSC_DBSYSCTRL0 (DBSC_BASE + 0x0280U) + +#define DBSC_DBTR(x) (DBSC_DBTR0 + 0x04U * (x)) +#define DBSC_DBTR0 (DBSC_BASE + 0x0300U) +#define DBSC_DBTR1 (DBSC_BASE + 0x0304U) +#define DBSC_DBTR3 (DBSC_BASE + 0x030CU) +#define DBSC_DBTR4 (DBSC_BASE + 0x0310U) +#define DBSC_DBTR5 (DBSC_BASE + 0x0314U) +#define DBSC_DBTR6 (DBSC_BASE + 0x0318U) +#define DBSC_DBTR7 (DBSC_BASE + 0x031CU) +#define DBSC_DBTR8 (DBSC_BASE + 0x0320U) +#define DBSC_DBTR9 (DBSC_BASE + 0x0324U) +#define DBSC_DBTR10 (DBSC_BASE + 0x0328U) +#define DBSC_DBTR11 (DBSC_BASE + 0x032CU) +#define DBSC_DBTR12 (DBSC_BASE + 0x0330U) +#define DBSC_DBTR13 (DBSC_BASE + 0x0334U) +#define DBSC_DBTR14 (DBSC_BASE + 0x0338U) +#define DBSC_DBTR15 (DBSC_BASE + 0x033CU) +#define DBSC_DBTR16 (DBSC_BASE + 0x0340U) +#define DBSC_DBTR17 (DBSC_BASE + 0x0344U) +#define DBSC_DBTR18 (DBSC_BASE + 0x0348U) +#define DBSC_DBTR19 (DBSC_BASE + 0x034CU) +#define DBSC_DBTR20 (DBSC_BASE + 0x0350U) +#define DBSC_DBTR21 (DBSC_BASE + 0x0354U) +#define DBSC_DBTR22 (DBSC_BASE + 0x0358U) +#define DBSC_DBTR23 (DBSC_BASE + 0x035CU) +#define DBSC_DBTR24 (DBSC_BASE + 0x0360U) +#define DBSC_DBTR25 (DBSC_BASE + 0x0364U) +#define DBSC_DBTR26 (DBSC_BASE + 0x0368U) + +#define DBSC_DBBL (DBSC_BASE + 0x0400U) +#define DBSC_DBRFCNF1 (DBSC_BASE + 0x0414U) +#define DBSC_DBRFCNF2 (DBSC_BASE + 0x0418U) +#define DBSC_DBTSPCNF (DBSC_BASE + 0x0420U) +#define DBSC_DBCALCNF (DBSC_BASE + 0x0424U) +#define DBSC_DBRNK(x) ((DBSC_BASE + 0x0430U) + 0x04U * (x)) +#define DBSC_DBRNK2 (DBSC_BASE + 0x0438U) +#define DBSC_DBRNK3 (DBSC_BASE + 0x043CU) +#define DBSC_DBRNK4 (DBSC_BASE + 0x0440U) +#define DBSC_DBRNK5 (DBSC_BASE + 0x0444U) +#define DBSC_DBODT(x) ((DBSC_BASE + 0x0460U) + 0x04U * (x)) + +#define DBSC_DBADJ0 (DBSC_BASE + 0x0500U) +#define DBSC_DBDBICNT (DBSC_BASE + 0x0518U) +#define DBSC_DBDFIPMSTRCNF (DBSC_BASE + 0x0520U) +#define DBSC_DBDFICUPDCNF (DBSC_BASE + 0x052CU) + +#define DBSC_DBDFISTAT(ch) ((DBSC_BASE + 0x0600U) + 0x40U * (ch)) +#define DBSC_DBDFISTAT_0 (DBSC_BASE + 0x0600U) +#define DBSC_DBDFISTAT_1 (DBSC_BASE + 0x0640U) +#define DBSC_DBDFISTAT_2 (DBSC_BASE + 0x0680U) +#define DBSC_DBDFISTAT_3 (DBSC_BASE + 0x06C0U) + +#define DBSC_DBDFICNT(ch) ((DBSC_BASE + 0x0604U) + 0x40U * (ch)) +#define DBSC_DBDFICNT_0 (DBSC_BASE + 0x0604U) +#define DBSC_DBDFICNT_1 (DBSC_BASE + 0x0644U) +#define DBSC_DBDFICNT_2 (DBSC_BASE + 0x0684U) +#define DBSC_DBDFICNT_3 (DBSC_BASE + 0x06C4U) + +#define DBSC_DBPDCNT0(ch) ((DBSC_BASE + 0x0610U) + 0x40U * (ch)) +#define DBSC_DBPDCNT0_0 (DBSC_BASE + 0x0610U) +#define DBSC_DBPDCNT0_1 (DBSC_BASE + 0x0650U) +#define DBSC_DBPDCNT0_2 (DBSC_BASE + 0x0690U) +#define DBSC_DBPDCNT0_3 (DBSC_BASE + 0x06D0U) + +#define DBSC_DBPDCNT1(ch) ((DBSC_BASE + 0x0614U) + 0x40U * (ch)) +#define DBSC_DBPDCNT1_0 (DBSC_BASE + 0x0614U) +#define DBSC_DBPDCNT1_1 (DBSC_BASE + 0x0654U) +#define DBSC_DBPDCNT1_2 (DBSC_BASE + 0x0694U) +#define DBSC_DBPDCNT1_3 (DBSC_BASE + 0x06D4U) + +#define DBSC_DBPDCNT2(ch) ((DBSC_BASE + 0x0618U) + 0x40U * (ch)) +#define DBSC_DBPDCNT2_0 (DBSC_BASE + 0x0618U) +#define DBSC_DBPDCNT2_1 (DBSC_BASE + 0x0658U) +#define DBSC_DBPDCNT2_2 (DBSC_BASE + 0x0698U) +#define DBSC_DBPDCNT2_3 (DBSC_BASE + 0x06D8U) + +#define DBSC_DBPDCNT3(ch) ((DBSC_BASE + 0x061CU) + 0x40U * (ch)) +#define DBSC_DBPDCNT3_0 (DBSC_BASE + 0x061CU) +#define DBSC_DBPDCNT3_1 (DBSC_BASE + 0x065CU) +#define DBSC_DBPDCNT3_2 (DBSC_BASE + 0x069CU) +#define DBSC_DBPDCNT3_3 (DBSC_BASE + 0x06DCU) + +#define DBSC_DBPDLK(ch) ((DBSC_BASE + 0x0620U) + 0x40U * (ch)) +#define DBSC_DBPDLK_0 (DBSC_BASE + 0x0620U) +#define DBSC_DBPDLK_1 (DBSC_BASE + 0x0660U) +#define DBSC_DBPDLK_2 (DBSC_BASE + 0x06a0U) +#define DBSC_DBPDLK_3 (DBSC_BASE + 0x06e0U) + +#define DBSC_DBPDRGA(ch) ((DBSC_BASE + 0x0624U) + 0x40U * (ch)) +#define DBSC_DBPDRGD(ch) ((DBSC_BASE + 0x0628U) + 0x40U * (ch)) +#define DBSC_DBPDRGA_0 (DBSC_BASE + 0x0624U) +#define DBSC_DBPDRGD_0 (DBSC_BASE + 0x0628U) +#define DBSC_DBPDRGA_1 (DBSC_BASE + 0x0664U) +#define DBSC_DBPDRGD_1 (DBSC_BASE + 0x0668U) +#define DBSC_DBPDRGA_2 (DBSC_BASE + 0x06A4U) +#define DBSC_DBPDRGD_2 (DBSC_BASE + 0x06A8U) +#define DBSC_DBPDRGA_3 (DBSC_BASE + 0x06E4U) +#define DBSC_DBPDRGD_3 (DBSC_BASE + 0x06E8U) + +#define DBSC_DBPDSTAT(ch) ((DBSC_BASE + 0x0630U) + 0x40U * (ch)) +#define DBSC_DBPDSTAT_0 (DBSC_BASE + 0x0630U) +#define DBSC_DBPDSTAT_1 (DBSC_BASE + 0x0670U) +#define DBSC_DBPDSTAT_2 (DBSC_BASE + 0x06B0U) +#define DBSC_DBPDSTAT_3 (DBSC_BASE + 0x06F0U) + +#define DBSC_DBBUS0CNF0 (DBSC_BASE + 0x0800U) +#define DBSC_DBBUS0CNF1 (DBSC_BASE + 0x0804U) + +#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) +#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) +#define DBSC_DBBSWAP (DBSC_BASE + 0x09F0U) +#define DBSC_DBBCAMDIS (DBSC_BASE + 0x09FCU) +#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) +#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U) +#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) +#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U) + +#define DBSC_DBSCHQOS_0(x) ((DBSC_BASE + 0x1030U) + 0x10U * (x)) +#define DBSC_DBSCHQOS_1(x) ((DBSC_BASE + 0x1034U) + 0x10U * (x)) +#define DBSC_DBSCHQOS_2(x) ((DBSC_BASE + 0x1038U) + 0x10U * (x)) +#define DBSC_DBSCHQOS_3(x) ((DBSC_BASE + 0x103CU) + 0x10U * (x)) + +#define DBSC_DBSCTR0 (DBSC_BASE + 0x1700U) +#define DBSC_DBSCTR1 (DBSC_BASE + 0x1708U) +#define DBSC_DBSCHRW2 (DBSC_BASE + 0x170CU) + +#define DBSC_SCFCTST01(x) ((DBSC_BASE + 0x1700U) + 0x08U * (x)) +#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U) +#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U) +#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) + +#define DBSC_DBMRRDR(chab) ((DBSC_BASE + 0x1800U) + 0x04U * (chab)) +#define DBSC_DBMRRDR_0 (DBSC_BASE + 0x1800U) +#define DBSC_DBMRRDR_1 (DBSC_BASE + 0x1804U) +#define DBSC_DBMRRDR_2 (DBSC_BASE + 0x1808U) +#define DBSC_DBMRRDR_3 (DBSC_BASE + 0x180CU) +#define DBSC_DBMRRDR_4 (DBSC_BASE + 0x1810U) +#define DBSC_DBMRRDR_5 (DBSC_BASE + 0x1814U) +#define DBSC_DBMRRDR_6 (DBSC_BASE + 0x1818U) +#define DBSC_DBMRRDR_7 (DBSC_BASE + 0x181CU) + +#define DBSC_DBMEMSWAPCONF0 (DBSC_BASE + 0x2000U) + +#define DBSC_DBMONCONF4 (DBSC_BASE + 0x3010U) + +#define DBSC_PLL_LOCK(ch) ((DBSC_BASE + 0x4054U) + 0x100U * (ch)) +#define DBSC_PLL_LOCK_0 (DBSC_BASE + 0x4054U) +#define DBSC_PLL_LOCK_1 (DBSC_BASE + 0x4154U) +#define DBSC_PLL_LOCK_2 (DBSC_BASE + 0x4254U) +#define DBSC_PLL_LOCK_3 (DBSC_BASE + 0x4354U) + +/* STAT registers */ +#if defined(__RH850G3K__) +#define MSTAT_BASE (BASE_MSTAT_ADDR + 0x8000U) +#else +#define MSTAT_BASE (0xE67E8000U) +#endif +#define MSTAT_SL_INIT (MSTAT_BASE + 0x0000U) +#define MSTAT_REF_ARS (MSTAT_BASE + 0x0004U) +#define MSTATQ_STATQC (MSTAT_BASE + 0x0008U) +#define MSTATQ_WTENABLE (MSTAT_BASE + 0x0030U) +#define MSTATQ_WTREFRESH (MSTAT_BASE + 0x0034U) +#define MSTATQ_WTSETTING0 (MSTAT_BASE + 0x0038U) +#define MSTATQ_WTSETTING1 (MSTAT_BASE + 0x003CU) + +#if defined(__RH850G3K__) +#define QOS_BASE1 (BASE_QOS_ADDR) +#else +#define QOS_BASE1 (0xE67F0000U) +#endif +#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U) +#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U) +#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U) +#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U) +#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U) +#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U) +#define QOSCTRL_EC (QOS_BASE1 + 0x003CU) +#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U) +#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U) +#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U) +#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U) +#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U) + +/* other module */ +#if defined(__RH850G3K__) +#define THS1_BASE (BASE_THS1_ADDR) +#else +#define THS1_BASE (0xE6198000U) +#endif +#define THS1_THCTR (THS1_BASE + 0x0020) +#define THS1_TEMP (THS1_BASE + 0x0028) + +#if defined(__RH850G3K__) +#define DBSC_BASE (BASE_DBSC_ADDR) +#else +#define DBSC_BASE (0xE6790000U) +#endif +#define DBSC_DBSCHQOS00 (DBSC_BASE + 0x1030U) +#define DBSC_DBSCHQOS01 (DBSC_BASE + 0x1034U) +#define DBSC_DBSCHQOS02 (DBSC_BASE + 0x1038U) +#define DBSC_DBSCHQOS03 (DBSC_BASE + 0x103CU) +#define DBSC_DBSCHQOS40 (DBSC_BASE + 0x1070U) +#define DBSC_DBSCHQOS41 (DBSC_BASE + 0x1074U) +#define DBSC_DBSCHQOS42 (DBSC_BASE + 0x1078U) +#define DBSC_DBSCHQOS43 (DBSC_BASE + 0x107CU) +#define DBSC_DBSCHQOS90 (DBSC_BASE + 0x10C0U) +#define DBSC_DBSCHQOS91 (DBSC_BASE + 0x10C4U) +#define DBSC_DBSCHQOS92 (DBSC_BASE + 0x10C8U) +#define DBSC_DBSCHQOS93 (DBSC_BASE + 0x10CCU) +#define DBSC_DBSCHQOS120 (DBSC_BASE + 0x10F0U) +#define DBSC_DBSCHQOS121 (DBSC_BASE + 0x10F4U) +#define DBSC_DBSCHQOS122 (DBSC_BASE + 0x10F8U) +#define DBSC_DBSCHQOS123 (DBSC_BASE + 0x10FCU) +#define DBSC_DBSCHQOS130 (DBSC_BASE + 0x1100U) +#define DBSC_DBSCHQOS131 (DBSC_BASE + 0x1104U) +#define DBSC_DBSCHQOS132 (DBSC_BASE + 0x1108U) +#define DBSC_DBSCHQOS133 (DBSC_BASE + 0x110CU) +#define DBSC_DBSCHQOS140 (DBSC_BASE + 0x1110U) +#define DBSC_DBSCHQOS141 (DBSC_BASE + 0x1114U) +#define DBSC_DBSCHQOS142 (DBSC_BASE + 0x1118U) +#define DBSC_DBSCHQOS143 (DBSC_BASE + 0x111CU) +#define DBSC_DBSCHQOS150 (DBSC_BASE + 0x1120U) +#define DBSC_DBSCHQOS151 (DBSC_BASE + 0x1124U) +#define DBSC_DBSCHQOS152 (DBSC_BASE + 0x1128U) +#define DBSC_DBSCHQOS153 (DBSC_BASE + 0x112CU) diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/ddr.mk b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/ddr.mk new file mode 100644 index 0000000..f353a38 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/ddr.mk @@ -0,0 +1,31 @@ +# +# Copyright (c) 2015-2019, Renesas Electronics Corporation All rights reserved. +# +# RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY +# +# This software is provided as reference/sample code under the license +# agreement between Renesas Electronics Corporation and licensee (the +# "License Agreement") and shall be treated as specified in the License +# Agreement. +# These instructions, statements, and software are the confidential +# information of Renesas Electronics Corporation. They must be used and +# modified solely for the purpose for which it was furnished by Renesas +# Electronics Corporation. All or part of these instructions, statements and +# software must not be reproduced nor disclosed to any third party in any +# form, unless permitted by the License Agreement. +# +# THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +# SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. +# IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, +# INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +# DAMAGE. +# + +OBJ_FILE += ip/ddr/dram_sub_func.o +OBJ_FILE += ip/ddr/boot_init_dram_regcheck.o + diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/ddr_regdef.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/ddr_regdef.h new file mode 100644 index 0000000..1b3b470 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/ddr_regdef.h @@ -0,0 +1,5908 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#define _reg_PHY_DQ_DM_SWIZZLE0 0x00000000U +#define _reg_PHY_DQ_DM_SWIZZLE1 0x00000001U +#define _reg_PHY_CLK_WR_BYPASS_SLAVE_DELAY 0x00000002U +#define _reg_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY 0x00000003U +#define _reg_PHY_BYPASS_TWO_CYC_PREAMBLE 0x00000004U +#define _reg_PHY_CLK_BYPASS_OVERRIDE 0x00000005U +#define _reg_PHY_SW_WRDQ0_SHIFT 0x00000006U +#define _reg_PHY_SW_WRDQ1_SHIFT 0x00000007U +#define _reg_PHY_SW_WRDQ2_SHIFT 0x00000008U +#define _reg_PHY_SW_WRDQ3_SHIFT 0x00000009U +#define _reg_PHY_SW_WRDQ4_SHIFT 0x0000000aU +#define _reg_PHY_SW_WRDQ5_SHIFT 0x0000000bU +#define _reg_PHY_SW_WRDQ6_SHIFT 0x0000000cU +#define _reg_PHY_SW_WRDQ7_SHIFT 0x0000000dU +#define _reg_PHY_SW_WRDM_SHIFT 0x0000000eU +#define _reg_PHY_SW_WRDQS_SHIFT 0x0000000fU +#define _reg_PHY_DQ_TSEL_ENABLE 0x00000010U +#define _reg_PHY_DQ_TSEL_SELECT 0x00000011U +#define _reg_PHY_DQS_TSEL_ENABLE 0x00000012U +#define _reg_PHY_DQS_TSEL_SELECT 0x00000013U +#define _reg_PHY_TWO_CYC_PREAMBLE 0x00000014U +#define _reg_PHY_DBI_MODE 0x00000015U +#define _reg_PHY_PER_RANK_CS_MAP 0x00000016U +#define _reg_PHY_PER_CS_TRAINING_MULTICAST_EN 0x00000017U +#define _reg_PHY_PER_CS_TRAINING_INDEX 0x00000018U +#define _reg_PHY_LP4_BOOT_RDDATA_EN_IE_DLY 0x00000019U +#define _reg_PHY_LP4_BOOT_RDDATA_EN_DLY 0x0000001aU +#define _reg_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY 0x0000001bU +#define _reg_PHY_LP4_BOOT_RPTR_UPDATE 0x0000001cU +#define _reg_PHY_LP4_BOOT_RDDQS_GATE_SLAVE_DELAY 0x0000001dU +#define _reg_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST 0x0000001eU +#define _reg_PHY_LP4_BOOT_WRPATH_GATE_DISABLE 0x0000001fU +#define _reg_PHY_LP4_BOOT_RDDATA_EN_OE_DLY 0x00000020U +#define _reg_PHY_LPBK_CONTROL 0x00000021U +#define _reg_PHY_LPBK_DFX_TIMEOUT_EN 0x00000022U +#define _reg_PHY_AUTO_TIMING_MARGIN_CONTROL 0x00000023U +#define _reg_PHY_AUTO_TIMING_MARGIN_OBS 0x00000024U +#define _reg_PHY_SLICE_PWR_RDC_DISABLE 0x00000025U +#define _reg_PHY_PRBS_PATTERN_START 0x00000026U +#define _reg_PHY_PRBS_PATTERN_MASK 0x00000027U +#define _reg_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY 0x00000028U +#define _reg_PHY_GATE_ERROR_DELAY_SELECT 0x00000029U +#define _reg_SC_PHY_SNAP_OBS_REGS 0x0000002aU +#define _reg_PHY_LPDDR 0x0000002bU +#define _reg_PHY_LPDDR_TYPE 0x0000002cU +#define _reg_PHY_GATE_SMPL1_SLAVE_DELAY 0x0000002dU +#define _reg_PHY_GATE_SMPL2_SLAVE_DELAY 0x0000002eU +#define _reg_ON_FLY_GATE_ADJUST_EN 0x0000002fU +#define _reg_PHY_GATE_TRACKING_OBS 0x00000030U +#define _reg_PHY_DFI40_POLARITY 0x00000031U +#define _reg_PHY_LP4_PST_AMBLE 0x00000032U +#define _reg_PHY_RDLVL_PATT8 0x00000033U +#define _reg_PHY_RDLVL_PATT9 0x00000034U +#define _reg_PHY_RDLVL_PATT10 0x00000035U +#define _reg_PHY_RDLVL_PATT11 0x00000036U +#define _reg_PHY_LP4_RDLVL_PATT8 0x00000037U +#define _reg_PHY_LP4_RDLVL_PATT9 0x00000038U +#define _reg_PHY_LP4_RDLVL_PATT10 0x00000039U +#define _reg_PHY_LP4_RDLVL_PATT11 0x0000003aU +#define _reg_PHY_SLAVE_LOOP_CNT_UPDATE 0x0000003bU +#define _reg_PHY_SW_FIFO_PTR_RST_DISABLE 0x0000003cU +#define _reg_PHY_MASTER_DLY_LOCK_OBS_SELECT 0x0000003dU +#define _reg_PHY_RDDQ_ENC_OBS_SELECT 0x0000003eU +#define _reg_PHY_RDDQS_DQ_ENC_OBS_SELECT 0x0000003fU +#define _reg_PHY_WR_ENC_OBS_SELECT 0x00000040U +#define _reg_PHY_WR_SHIFT_OBS_SELECT 0x00000041U +#define _reg_PHY_FIFO_PTR_OBS_SELECT 0x00000042U +#define _reg_PHY_LVL_DEBUG_MODE 0x00000043U +#define _reg_SC_PHY_LVL_DEBUG_CONT 0x00000044U +#define _reg_PHY_WRLVL_CAPTURE_CNT 0x00000045U +#define _reg_PHY_WRLVL_UPDT_WAIT_CNT 0x00000046U +#define _reg_PHY_WRLVL_DQ_MASK 0x00000047U +#define _reg_PHY_GTLVL_CAPTURE_CNT 0x00000048U +#define _reg_PHY_GTLVL_UPDT_WAIT_CNT 0x00000049U +#define _reg_PHY_RDLVL_CAPTURE_CNT 0x0000004aU +#define _reg_PHY_RDLVL_UPDT_WAIT_CNT 0x0000004bU +#define _reg_PHY_RDLVL_OP_MODE 0x0000004cU +#define _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x0000004dU +#define _reg_PHY_RDLVL_DATA_MASK 0x0000004eU +#define _reg_PHY_RDLVL_DATA_SWIZZLE 0x0000004fU +#define _reg_PHY_WDQLVL_BURST_CNT 0x00000050U +#define _reg_PHY_WDQLVL_PATT 0x00000051U +#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET 0x00000052U +#define _reg_PHY_WDQLVL_UPDT_WAIT_CNT 0x00000053U +#define _reg_PHY_WDQLVL_DQDM_OBS_SELECT 0x00000054U +#define _reg_PHY_WDQLVL_QTR_DLY_STEP 0x00000055U +#define _reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS 0x00000056U +#define _reg_PHY_WDQLVL_CLR_PREV_RESULTS 0x00000057U +#define _reg_PHY_WDQLVL_DATADM_MASK 0x00000058U +#define _reg_PHY_USER_PATT0 0x00000059U +#define _reg_PHY_USER_PATT1 0x0000005aU +#define _reg_PHY_USER_PATT2 0x0000005bU +#define _reg_PHY_USER_PATT3 0x0000005cU +#define _reg_PHY_USER_PATT4 0x0000005dU +#define _reg_PHY_DQ_SWIZZLING 0x0000005eU +#define _reg_PHY_CALVL_VREF_DRIVING_SLICE 0x0000005fU +#define _reg_SC_PHY_MANUAL_CLEAR 0x00000060U +#define _reg_PHY_FIFO_PTR_OBS 0x00000061U +#define _reg_PHY_LPBK_RESULT_OBS 0x00000062U +#define _reg_PHY_LPBK_ERROR_COUNT_OBS 0x00000063U +#define _reg_PHY_MASTER_DLY_LOCK_OBS 0x00000064U +#define _reg_PHY_RDDQ_SLV_DLY_ENC_OBS 0x00000065U +#define _reg_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS 0x00000066U +#define _reg_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS 0x00000067U +#define _reg_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS 0x00000068U +#define _reg_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS 0x00000069U +#define _reg_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS 0x0000006aU +#define _reg_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS 0x0000006bU +#define _reg_PHY_WR_ADDER_SLV_DLY_ENC_OBS 0x0000006cU +#define _reg_PHY_WR_SHIFT_OBS 0x0000006dU +#define _reg_PHY_WRLVL_HARD0_DELAY_OBS 0x0000006eU +#define _reg_PHY_WRLVL_HARD1_DELAY_OBS 0x0000006fU +#define _reg_PHY_WRLVL_STATUS_OBS 0x00000070U +#define _reg_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS 0x00000071U +#define _reg_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS 0x00000072U +#define _reg_PHY_WRLVL_ERROR_OBS 0x00000073U +#define _reg_PHY_GTLVL_HARD0_DELAY_OBS 0x00000074U +#define _reg_PHY_GTLVL_HARD1_DELAY_OBS 0x00000075U +#define _reg_PHY_GTLVL_STATUS_OBS 0x00000076U +#define _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x00000077U +#define _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x00000078U +#define _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS 0x00000079U +#define _reg_PHY_RDLVL_STATUS_OBS 0x0000007aU +#define _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS 0x0000007bU +#define _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS 0x0000007cU +#define _reg_PHY_WDQLVL_STATUS_OBS 0x0000007dU +#define _reg_PHY_DDL_MODE 0x0000007eU +#define _reg_PHY_DDL_TEST_OBS 0x0000007fU +#define _reg_PHY_DDL_TEST_MSTR_DLY_OBS 0x00000080U +#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD 0x00000081U +#define _reg_PHY_LP4_WDQS_OE_EXTEND 0x00000082U +#define _reg_SC_PHY_RX_CAL_START 0x00000083U +#define _reg_PHY_RX_CAL_OVERRIDE 0x00000084U +#define _reg_PHY_RX_CAL_SAMPLE_WAIT 0x00000085U +#define _reg_PHY_RX_CAL_DQ0 0x00000086U +#define _reg_PHY_RX_CAL_DQ1 0x00000087U +#define _reg_PHY_RX_CAL_DQ2 0x00000088U +#define _reg_PHY_RX_CAL_DQ3 0x00000089U +#define _reg_PHY_RX_CAL_DQ4 0x0000008aU +#define _reg_PHY_RX_CAL_DQ5 0x0000008bU +#define _reg_PHY_RX_CAL_DQ6 0x0000008cU +#define _reg_PHY_RX_CAL_DQ7 0x0000008dU +#define _reg_PHY_RX_CAL_DM 0x0000008eU +#define _reg_PHY_RX_CAL_DQS 0x0000008fU +#define _reg_PHY_RX_CAL_FDBK 0x00000090U +#define _reg_PHY_RX_CAL_OBS 0x00000091U +#define _reg_PHY_RX_CAL_LOCK_OBS 0x00000092U +#define _reg_PHY_RX_CAL_DISABLE 0x00000093U +#define _reg_PHY_CLK_WRDQ0_SLAVE_DELAY 0x00000094U +#define _reg_PHY_CLK_WRDQ1_SLAVE_DELAY 0x00000095U +#define _reg_PHY_CLK_WRDQ2_SLAVE_DELAY 0x00000096U +#define _reg_PHY_CLK_WRDQ3_SLAVE_DELAY 0x00000097U +#define _reg_PHY_CLK_WRDQ4_SLAVE_DELAY 0x00000098U +#define _reg_PHY_CLK_WRDQ5_SLAVE_DELAY 0x00000099U +#define _reg_PHY_CLK_WRDQ6_SLAVE_DELAY 0x0000009aU +#define _reg_PHY_CLK_WRDQ7_SLAVE_DELAY 0x0000009bU +#define _reg_PHY_CLK_WRDM_SLAVE_DELAY 0x0000009cU +#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY 0x0000009dU +#define _reg_PHY_WRLVL_THRESHOLD_ADJUST 0x0000009eU +#define _reg_PHY_RDDQ0_SLAVE_DELAY 0x0000009fU +#define _reg_PHY_RDDQ1_SLAVE_DELAY 0x000000a0U +#define _reg_PHY_RDDQ2_SLAVE_DELAY 0x000000a1U +#define _reg_PHY_RDDQ3_SLAVE_DELAY 0x000000a2U +#define _reg_PHY_RDDQ4_SLAVE_DELAY 0x000000a3U +#define _reg_PHY_RDDQ5_SLAVE_DELAY 0x000000a4U +#define _reg_PHY_RDDQ6_SLAVE_DELAY 0x000000a5U +#define _reg_PHY_RDDQ7_SLAVE_DELAY 0x000000a6U +#define _reg_PHY_RDDM_SLAVE_DELAY 0x000000a7U +#define _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY 0x000000a8U +#define _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY 0x000000a9U +#define _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY 0x000000aaU +#define _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY 0x000000abU +#define _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY 0x000000acU +#define _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY 0x000000adU +#define _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY 0x000000aeU +#define _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY 0x000000afU +#define _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY 0x000000b0U +#define _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY 0x000000b1U +#define _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY 0x000000b2U +#define _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY 0x000000b3U +#define _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY 0x000000b4U +#define _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY 0x000000b5U +#define _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY 0x000000b6U +#define _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY 0x000000b7U +#define _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY 0x000000b8U +#define _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY 0x000000b9U +#define _reg_PHY_RDDQS_GATE_SLAVE_DELAY 0x000000baU +#define _reg_PHY_RDDQS_LATENCY_ADJUST 0x000000bbU +#define _reg_PHY_WRITE_PATH_LAT_ADD 0x000000bcU +#define _reg_PHY_WRLVL_DELAY_EARLY_THRESHOLD 0x000000bdU +#define _reg_PHY_WRLVL_DELAY_PERIOD_THRESHOLD 0x000000beU +#define _reg_PHY_WRLVL_EARLY_FORCE_ZERO 0x000000bfU +#define _reg_PHY_GTLVL_RDDQS_SLV_DLY_START 0x000000c0U +#define _reg_PHY_GTLVL_LAT_ADJ_START 0x000000c1U +#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_START 0x000000c2U +#define _reg_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START 0x000000c3U +#define _reg_PHY_FDBK_PWR_CTRL 0x000000c4U +#define _reg_PHY_DQ_OE_TIMING 0x000000c5U +#define _reg_PHY_DQ_TSEL_RD_TIMING 0x000000c6U +#define _reg_PHY_DQ_TSEL_WR_TIMING 0x000000c7U +#define _reg_PHY_DQS_OE_TIMING 0x000000c8U +#define _reg_PHY_DQS_TSEL_RD_TIMING 0x000000c9U +#define _reg_PHY_DQS_OE_RD_TIMING 0x000000caU +#define _reg_PHY_DQS_TSEL_WR_TIMING 0x000000cbU +#define _reg_PHY_PER_CS_TRAINING_EN 0x000000ccU +#define _reg_PHY_DQ_IE_TIMING 0x000000cdU +#define _reg_PHY_DQS_IE_TIMING 0x000000ceU +#define _reg_PHY_RDDATA_EN_IE_DLY 0x000000cfU +#define _reg_PHY_IE_MODE 0x000000d0U +#define _reg_PHY_RDDATA_EN_DLY 0x000000d1U +#define _reg_PHY_RDDATA_EN_TSEL_DLY 0x000000d2U +#define _reg_PHY_RDDATA_EN_OE_DLY 0x000000d3U +#define _reg_PHY_SW_MASTER_MODE 0x000000d4U +#define _reg_PHY_MASTER_DELAY_START 0x000000d5U +#define _reg_PHY_MASTER_DELAY_STEP 0x000000d6U +#define _reg_PHY_MASTER_DELAY_WAIT 0x000000d7U +#define _reg_PHY_MASTER_DELAY_HALF_MEASURE 0x000000d8U +#define _reg_PHY_RPTR_UPDATE 0x000000d9U +#define _reg_PHY_WRLVL_DLY_STEP 0x000000daU +#define _reg_PHY_WRLVL_RESP_WAIT_CNT 0x000000dbU +#define _reg_PHY_GTLVL_DLY_STEP 0x000000dcU +#define _reg_PHY_GTLVL_RESP_WAIT_CNT 0x000000ddU +#define _reg_PHY_GTLVL_BACK_STEP 0x000000deU +#define _reg_PHY_GTLVL_FINAL_STEP 0x000000dfU +#define _reg_PHY_WDQLVL_DLY_STEP 0x000000e0U +#define _reg_PHY_TOGGLE_PRE_SUPPORT 0x000000e1U +#define _reg_PHY_RDLVL_DLY_STEP 0x000000e2U +#define _reg_PHY_WRPATH_GATE_DISABLE 0x000000e3U +#define _reg_PHY_WRPATH_GATE_TIMING 0x000000e4U +#define _reg_PHY_ADR0_SW_WRADDR_SHIFT 0x000000e5U +#define _reg_PHY_ADR1_SW_WRADDR_SHIFT 0x000000e6U +#define _reg_PHY_ADR2_SW_WRADDR_SHIFT 0x000000e7U +#define _reg_PHY_ADR3_SW_WRADDR_SHIFT 0x000000e8U +#define _reg_PHY_ADR4_SW_WRADDR_SHIFT 0x000000e9U +#define _reg_PHY_ADR5_SW_WRADDR_SHIFT 0x000000eaU +#define _reg_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY 0x000000ebU +#define _reg_PHY_ADR_CLK_BYPASS_OVERRIDE 0x000000ecU +#define _reg_SC_PHY_ADR_MANUAL_CLEAR 0x000000edU +#define _reg_PHY_ADR_LPBK_RESULT_OBS 0x000000eeU +#define _reg_PHY_ADR_LPBK_ERROR_COUNT_OBS 0x000000efU +#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT 0x000000f0U +#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS 0x000000f1U +#define _reg_PHY_ADR_BASE_SLV_DLY_ENC_OBS 0x000000f2U +#define _reg_PHY_ADR_ADDER_SLV_DLY_ENC_OBS 0x000000f3U +#define _reg_PHY_ADR_SLAVE_LOOP_CNT_UPDATE 0x000000f4U +#define _reg_PHY_ADR_SLV_DLY_ENC_OBS_SELECT 0x000000f5U +#define _reg_SC_PHY_ADR_SNAP_OBS_REGS 0x000000f6U +#define _reg_PHY_ADR_TSEL_ENABLE 0x000000f7U +#define _reg_PHY_ADR_LPBK_CONTROL 0x000000f8U +#define _reg_PHY_ADR_PRBS_PATTERN_START 0x000000f9U +#define _reg_PHY_ADR_PRBS_PATTERN_MASK 0x000000faU +#define _reg_PHY_ADR_PWR_RDC_DISABLE 0x000000fbU +#define _reg_PHY_ADR_TYPE 0x000000fcU +#define _reg_PHY_ADR_WRADDR_SHIFT_OBS 0x000000fdU +#define _reg_PHY_ADR_IE_MODE 0x000000feU +#define _reg_PHY_ADR_DDL_MODE 0x000000ffU +#define _reg_PHY_ADR_DDL_TEST_OBS 0x00000100U +#define _reg_PHY_ADR_DDL_TEST_MSTR_DLY_OBS 0x00000101U +#define _reg_PHY_ADR_CALVL_START 0x00000102U +#define _reg_PHY_ADR_CALVL_COARSE_DLY 0x00000103U +#define _reg_PHY_ADR_CALVL_QTR 0x00000104U +#define _reg_PHY_ADR_CALVL_SWIZZLE0 0x00000105U +#define _reg_PHY_ADR_CALVL_SWIZZLE1 0x00000106U +#define _reg_PHY_ADR_CALVL_SWIZZLE0_0 0x00000107U +#define _reg_PHY_ADR_CALVL_SWIZZLE1_0 0x00000108U +#define _reg_PHY_ADR_CALVL_SWIZZLE0_1 0x00000109U +#define _reg_PHY_ADR_CALVL_SWIZZLE1_1 0x0000010aU +#define _reg_PHY_ADR_CALVL_DEVICE_MAP 0x0000010bU +#define _reg_PHY_ADR_CALVL_RANK_CTRL 0x0000010cU +#define _reg_PHY_ADR_CALVL_NUM_PATTERNS 0x0000010dU +#define _reg_PHY_ADR_CALVL_CAPTURE_CNT 0x0000010eU +#define _reg_PHY_ADR_CALVL_RESP_WAIT_CNT 0x0000010fU +#define _reg_PHY_ADR_CALVL_DEBUG_MODE 0x00000110U +#define _reg_SC_PHY_ADR_CALVL_DEBUG_CONT 0x00000111U +#define _reg_SC_PHY_ADR_CALVL_ERROR_CLR 0x00000112U +#define _reg_PHY_ADR_CALVL_OBS_SELECT 0x00000113U +#define _reg_PHY_ADR_CALVL_OBS0 0x00000114U +#define _reg_PHY_ADR_CALVL_OBS1 0x00000115U +#define _reg_PHY_ADR_CALVL_RESULT 0x00000116U +#define _reg_PHY_ADR_CALVL_FG_0 0x00000117U +#define _reg_PHY_ADR_CALVL_BG_0 0x00000118U +#define _reg_PHY_ADR_CALVL_FG_1 0x00000119U +#define _reg_PHY_ADR_CALVL_BG_1 0x0000011aU +#define _reg_PHY_ADR_CALVL_FG_2 0x0000011bU +#define _reg_PHY_ADR_CALVL_BG_2 0x0000011cU +#define _reg_PHY_ADR_CALVL_FG_3 0x0000011dU +#define _reg_PHY_ADR_CALVL_BG_3 0x0000011eU +#define _reg_PHY_ADR_ADDR_SEL 0x0000011fU +#define _reg_PHY_ADR_LP4_BOOT_SLV_DELAY 0x00000120U +#define _reg_PHY_ADR_BIT_MASK 0x00000121U +#define _reg_PHY_ADR_SEG_MASK 0x00000122U +#define _reg_PHY_ADR_CALVL_TRAIN_MASK 0x00000123U +#define _reg_PHY_ADR_CSLVL_TRAIN_MASK 0x00000124U +#define _reg_PHY_ADR_SW_TXIO_CTRL 0x00000125U +#define _reg_PHY_ADR_TSEL_SELECT 0x00000126U +#define _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY 0x00000127U +#define _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY 0x00000128U +#define _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY 0x00000129U +#define _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY 0x0000012aU +#define _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY 0x0000012bU +#define _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY 0x0000012cU +#define _reg_PHY_ADR_SW_MASTER_MODE 0x0000012dU +#define _reg_PHY_ADR_MASTER_DELAY_START 0x0000012eU +#define _reg_PHY_ADR_MASTER_DELAY_STEP 0x0000012fU +#define _reg_PHY_ADR_MASTER_DELAY_WAIT 0x00000130U +#define _reg_PHY_ADR_MASTER_DELAY_HALF_MEASURE 0x00000131U +#define _reg_PHY_ADR_CALVL_DLY_STEP 0x00000132U +#define _reg_PHY_FREQ_SEL 0x00000133U +#define _reg_PHY_FREQ_SEL_FROM_REGIF 0x00000134U +#define _reg_PHY_FREQ_SEL_MULTICAST_EN 0x00000135U +#define _reg_PHY_FREQ_SEL_INDEX 0x00000136U +#define _reg_PHY_SW_GRP_SHIFT_0 0x00000137U +#define _reg_PHY_SW_GRP_SHIFT_1 0x00000138U +#define _reg_PHY_SW_GRP_SHIFT_2 0x00000139U +#define _reg_PHY_SW_GRP_SHIFT_3 0x0000013aU +#define _reg_PHY_GRP_BYPASS_SLAVE_DELAY 0x0000013bU +#define _reg_PHY_SW_GRP_BYPASS_SHIFT 0x0000013cU +#define _reg_PHY_GRP_BYPASS_OVERRIDE 0x0000013dU +#define _reg_SC_PHY_MANUAL_UPDATE 0x0000013eU +#define _reg_SC_PHY_MANUAL_UPDATE_PHYUPD_ENABLE 0x0000013fU +#define _reg_PHY_LP4_BOOT_DISABLE 0x00000140U +#define _reg_PHY_CSLVL_ENABLE 0x00000141U +#define _reg_PHY_CSLVL_CS_MAP 0x00000142U +#define _reg_PHY_CSLVL_START 0x00000143U +#define _reg_PHY_CSLVL_QTR 0x00000144U +#define _reg_PHY_CSLVL_COARSE_CHK 0x00000145U +#define _reg_PHY_CSLVL_CAPTURE_CNT 0x00000146U +#define _reg_PHY_CSLVL_COARSE_DLY 0x00000147U +#define _reg_PHY_CSLVL_COARSE_CAPTURE_CNT 0x00000148U +#define _reg_PHY_CSLVL_DEBUG_MODE 0x00000149U +#define _reg_SC_PHY_CSLVL_DEBUG_CONT 0x0000014aU +#define _reg_SC_PHY_CSLVL_ERROR_CLR 0x0000014bU +#define _reg_PHY_CSLVL_OBS0 0x0000014cU +#define _reg_PHY_CSLVL_OBS1 0x0000014dU +#define _reg_PHY_CALVL_CS_MAP 0x0000014eU +#define _reg_PHY_GRP_SLV_DLY_ENC_OBS_SELECT 0x0000014fU +#define _reg_PHY_GRP_SHIFT_OBS_SELECT 0x00000150U +#define _reg_PHY_GRP_SLV_DLY_ENC_OBS 0x00000151U +#define _reg_PHY_GRP_SHIFT_OBS 0x00000152U +#define _reg_PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE 0x00000153U +#define _reg_PHY_ADRCTL_SNAP_OBS_REGS 0x00000154U +#define _reg_PHY_DFI_PHYUPD_TYPE 0x00000155U +#define _reg_PHY_ADRCTL_LPDDR 0x00000156U +#define _reg_PHY_LP4_ACTIVE 0x00000157U +#define _reg_PHY_LPDDR3_CS 0x00000158U +#define _reg_PHY_CALVL_RESULT_MASK 0x00000159U +#define _reg_SC_PHY_UPDATE_CLK_CAL_VALUES 0x0000015aU +#define _reg_PHY_SW_TXIO_CTRL_0 0x0000015bU +#define _reg_PHY_SW_TXIO_CTRL_1 0x0000015cU +#define _reg_PHY_SW_TXIO_CTRL_2 0x0000015dU +#define _reg_PHY_SW_TXIO_CTRL_3 0x0000015eU +#define _reg_PHY_MEMCLK_SW_TXIO_CTRL 0x0000015fU +#define _reg_PHY_CA_SW_TXPWR_CTRL 0x00000160U +#define _reg_PHY_MEMCLK_SW_TXPWR_CTRL 0x00000161U +#define _reg_PHY_USER_DEF_REG_AC_0 0x00000162U +#define _reg_PHY_USER_DEF_REG_AC_1 0x00000163U +#define _reg_PHY_USER_DEF_REG_AC_2 0x00000164U +#define _reg_PHY_USER_DEF_REG_AC_3 0x00000165U +#define _reg_PHY_UPDATE_CLK_CAL_VALUES 0x00000166U +#define _reg_PHY_CONTINUOUS_CLK_CAL_UPDATE 0x00000167U +#define _reg_PHY_PLL_CTRL 0x00000168U +#define _reg_PHY_PLL_CTRL_TOP 0x00000169U +#define _reg_PHY_PLL_CTRL_CA 0x0000016aU +#define _reg_PHY_PLL_BYPASS 0x0000016bU +#define _reg_PHY_LOW_FREQ_SEL 0x0000016cU +#define _reg_PHY_PAD_VREF_CTRL_DQ_0 0x0000016dU +#define _reg_PHY_PAD_VREF_CTRL_DQ_1 0x0000016eU +#define _reg_PHY_PAD_VREF_CTRL_DQ_2 0x0000016fU +#define _reg_PHY_PAD_VREF_CTRL_DQ_3 0x00000170U +#define _reg_PHY_PAD_VREF_CTRL_AC 0x00000171U +#define _reg_PHY_CSLVL_DLY_STEP 0x00000172U +#define _reg_PHY_SET_DFI_INPUT_0 0x00000173U +#define _reg_PHY_SET_DFI_INPUT_1 0x00000174U +#define _reg_PHY_SET_DFI_INPUT_2 0x00000175U +#define _reg_PHY_SET_DFI_INPUT_3 0x00000176U +#define _reg_PHY_GRP_SLAVE_DELAY_0 0x00000177U +#define _reg_PHY_GRP_SLAVE_DELAY_1 0x00000178U +#define _reg_PHY_GRP_SLAVE_DELAY_2 0x00000179U +#define _reg_PHY_GRP_SLAVE_DELAY_3 0x0000017aU +#define _reg_PHY_CS_ACS_ALLOCATION_0 0x0000017bU +#define _reg_PHY_CS_ACS_ALLOCATION_1 0x0000017cU +#define _reg_PHY_CS_ACS_ALLOCATION_2 0x0000017dU +#define _reg_PHY_CS_ACS_ALLOCATION_3 0x0000017eU +#define _reg_PHY_LP4_BOOT_PLL_CTRL 0x0000017fU +#define _reg_PHY_LP4_BOOT_PLL_CTRL_CA 0x00000180U +#define _reg_PHY_LP4_BOOT_TOP_PLL_CTRL 0x00000181U +#define _reg_PHY_PLL_CTRL_OVERRIDE 0x00000182U +#define _reg_PHY_PLL_WAIT 0x00000183U +#define _reg_PHY_PLL_WAIT_TOP 0x00000184U +#define _reg_PHY_PLL_OBS_0 0x00000185U +#define _reg_PHY_PLL_OBS_1 0x00000186U +#define _reg_PHY_PLL_OBS_2 0x00000187U +#define _reg_PHY_PLL_OBS_3 0x00000188U +#define _reg_PHY_PLL_OBS_4 0x00000189U +#define _reg_PHY_PLL_TESTOUT_SEL 0x0000018aU +#define _reg_PHY_TCKSRE_WAIT 0x0000018bU +#define _reg_PHY_LP4_BOOT_LOW_FREQ_SEL 0x0000018cU +#define _reg_PHY_LP_WAKEUP 0x0000018dU +#define _reg_PHY_LS_IDLE_EN 0x0000018eU +#define _reg_PHY_LP_CTRLUPD_CNTR_CFG 0x0000018fU +#define _reg_PHY_TDFI_PHY_WRDELAY 0x00000190U +#define _reg_PHY_PAD_FDBK_DRIVE 0x00000191U +#define _reg_PHY_PAD_DATA_DRIVE 0x00000192U +#define _reg_PHY_PAD_DQS_DRIVE 0x00000193U +#define _reg_PHY_PAD_ADDR_DRIVE 0x00000194U +#define _reg_PHY_PAD_CLK_DRIVE 0x00000195U +#define _reg_PHY_PAD_FDBK_TERM 0x00000196U +#define _reg_PHY_PAD_DATA_TERM 0x00000197U +#define _reg_PHY_PAD_DQS_TERM 0x00000198U +#define _reg_PHY_PAD_ADDR_TERM 0x00000199U +#define _reg_PHY_PAD_CLK_TERM 0x0000019aU +#define _reg_PHY_PAD_CKE_DRIVE 0x0000019bU +#define _reg_PHY_PAD_CKE_TERM 0x0000019cU +#define _reg_PHY_PAD_RST_DRIVE 0x0000019dU +#define _reg_PHY_PAD_RST_TERM 0x0000019eU +#define _reg_PHY_PAD_CS_DRIVE 0x0000019fU +#define _reg_PHY_PAD_CS_TERM 0x000001a0U +#define _reg_PHY_PAD_ODT_DRIVE 0x000001a1U +#define _reg_PHY_PAD_ODT_TERM 0x000001a2U +#define _reg_PHY_ADRCTL_RX_CAL 0x000001a3U +#define _reg_PHY_ADRCTL_LP3_RX_CAL 0x000001a4U +#define _reg_PHY_TST_CLK_PAD_CTRL 0x000001a5U +#define _reg_PHY_TST_CLK_PAD_CTRL2 0x000001a6U +#define _reg_PHY_CAL_MODE_0 0x000001a7U +#define _reg_PHY_CAL_CLEAR_0 0x000001a8U +#define _reg_PHY_CAL_START_0 0x000001a9U +#define _reg_PHY_CAL_INTERVAL_COUNT_0 0x000001aaU +#define _reg_PHY_CAL_SAMPLE_WAIT_0 0x000001abU +#define _reg_PHY_LP4_BOOT_CAL_CLK_SELECT_0 0x000001acU +#define _reg_PHY_CAL_CLK_SELECT_0 0x000001adU +#define _reg_PHY_CAL_RESULT_OBS_0 0x000001aeU +#define _reg_PHY_CAL_RESULT2_OBS_0 0x000001afU +#define _reg_PHY_CAL_CPTR_CNT_0 0x000001b0U +#define _reg_PHY_CAL_SETTLING_PRD_0 0x000001b1U +#define _reg_PHY_CAL_PU_FINE_ADJ_0 0x000001b2U +#define _reg_PHY_CAL_PD_FINE_ADJ_0 0x000001b3U +#define _reg_PHY_CAL_RCV_FINE_ADJ_0 0x000001b4U +#define _reg_PHY_CAL_DBG_CFG_0 0x000001b5U +#define _reg_SC_PHY_PAD_DBG_CONT_0 0x000001b6U +#define _reg_PHY_CAL_RESULT3_OBS_0 0x000001b7U +#define _reg_PHY_ADRCTL_PVT_MAP_0 0x000001b8U +#define _reg_PHY_CAL_SLOPE_ADJ_0 0x000001b9U +#define _reg_PHY_CAL_SLOPE_ADJ_PASS2_0 0x000001baU +#define _reg_PHY_CAL_TWO_PASS_CFG_0 0x000001bbU +#define _reg_PHY_CAL_SW_CAL_CFG_0 0x000001bcU +#define _reg_PHY_CAL_RANGE_MIN_0 0x000001bdU +#define _reg_PHY_CAL_RANGE_MAX_0 0x000001beU +#define _reg_PHY_PAD_ATB_CTRL 0x000001bfU +#define _reg_PHY_ADRCTL_MANUAL_UPDATE 0x000001c0U +#define _reg_PHY_AC_LPBK_ERR_CLEAR 0x000001c1U +#define _reg_PHY_AC_LPBK_OBS_SELECT 0x000001c2U +#define _reg_PHY_AC_LPBK_ENABLE 0x000001c3U +#define _reg_PHY_AC_LPBK_CONTROL 0x000001c4U +#define _reg_PHY_AC_PRBS_PATTERN_START 0x000001c5U +#define _reg_PHY_AC_PRBS_PATTERN_MASK 0x000001c6U +#define _reg_PHY_AC_LPBK_RESULT_OBS 0x000001c7U +#define _reg_PHY_AC_CLK_LPBK_OBS_SELECT 0x000001c8U +#define _reg_PHY_AC_CLK_LPBK_ENABLE 0x000001c9U +#define _reg_PHY_AC_CLK_LPBK_CONTROL 0x000001caU +#define _reg_PHY_AC_CLK_LPBK_RESULT_OBS 0x000001cbU +#define _reg_PHY_AC_PWR_RDC_DISABLE 0x000001ccU +#define _reg_PHY_DATA_BYTE_ORDER_SEL 0x000001cdU +#define _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH 0x000001ceU +#define _reg_PHY_LPDDR4_CONNECT 0x000001cfU +#define _reg_PHY_CALVL_DEVICE_MAP 0x000001d0U +#define _reg_PHY_ADR_DISABLE 0x000001d1U +#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL 0x000001d2U +#define _reg_PHY_CS_DLY_UPT_PER_AC_SLICE 0x000001d3U +#define _reg_PHY_DDL_AC_ENABLE 0x000001d4U +#define _reg_PHY_DDL_AC_MODE 0x000001d5U +#define _reg_PHY_PAD_BACKGROUND_CAL 0x000001d6U +#define _reg_PHY_INIT_UPDATE_CONFIG 0x000001d7U +#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD_AC 0x000001d8U +#define _reg_PHY_DLL_RST_EN 0x000001d9U +#define _reg_PHY_AC_INIT_COMPLETE_OBS 0x000001daU +#define _reg_PHY_DS_INIT_COMPLETE_OBS 0x000001dbU +#define _reg_PHY_UPDATE_MASK 0x000001dcU +#define _reg_PHY_PLL_SWITCH_CNT 0x000001ddU +#define _reg_PI_START 0x000001deU +#define _reg_PI_DRAM_CLASS 0x000001dfU +#define _reg_PI_VERSION 0x000001e0U +#define _reg_PI_NORMAL_LVL_SEQ 0x000001e1U +#define _reg_PI_INIT_LVL_EN 0x000001e2U +#define _reg_PI_NOTCARE_PHYUPD 0x000001e3U +#define _reg_PI_ONBUS_MBIST 0x000001e4U +#define _reg_PI_TCMD_GAP 0x000001e5U +#define _reg_PI_MASTER_ACK_DURATION_MIN 0x000001e6U +#define _reg_PI_DFI_VERSION 0x000001e7U +#define _reg_PI_TDFI_PHYMSTR_TYPE0 0x000001e8U +#define _reg_PI_TDFI_PHYMSTR_TYPE1 0x000001e9U +#define _reg_PI_TDFI_PHYMSTR_TYPE2 0x000001eaU +#define _reg_PI_TDFI_PHYMSTR_TYPE3 0x000001ebU +#define _reg_PI_DFI_PHYMSTR_TYPE 0x000001ecU +#define _reg_PI_DFI_PHYMSTR_CS_STATE_R 0x000001edU +#define _reg_PI_DFI_PHYMSTR_STATE_SEL_R 0x000001eeU +#define _reg_PI_TDFI_PHYMSTR_MAX_F0 0x000001efU +#define _reg_PI_TDFI_PHYMSTR_RESP_F0 0x000001f0U +#define _reg_PI_TDFI_PHYMSTR_MAX_F1 0x000001f1U +#define _reg_PI_TDFI_PHYMSTR_RESP_F1 0x000001f2U +#define _reg_PI_TDFI_PHYMSTR_MAX_F2 0x000001f3U +#define _reg_PI_TDFI_PHYMSTR_RESP_F2 0x000001f4U +#define _reg_PI_TDFI_PHYUPD_RESP_F0 0x000001f5U +#define _reg_PI_TDFI_PHYUPD_TYPE0_F0 0x000001f6U +#define _reg_PI_TDFI_PHYUPD_TYPE1_F0 0x000001f7U +#define _reg_PI_TDFI_PHYUPD_TYPE2_F0 0x000001f8U +#define _reg_PI_TDFI_PHYUPD_TYPE3_F0 0x000001f9U +#define _reg_PI_TDFI_PHYUPD_RESP_F1 0x000001faU +#define _reg_PI_TDFI_PHYUPD_TYPE0_F1 0x000001fbU +#define _reg_PI_TDFI_PHYUPD_TYPE1_F1 0x000001fcU +#define _reg_PI_TDFI_PHYUPD_TYPE2_F1 0x000001fdU +#define _reg_PI_TDFI_PHYUPD_TYPE3_F1 0x000001feU +#define _reg_PI_TDFI_PHYUPD_RESP_F2 0x000001ffU +#define _reg_PI_TDFI_PHYUPD_TYPE0_F2 0x00000200U +#define _reg_PI_TDFI_PHYUPD_TYPE1_F2 0x00000201U +#define _reg_PI_TDFI_PHYUPD_TYPE2_F2 0x00000202U +#define _reg_PI_TDFI_PHYUPD_TYPE3_F2 0x00000203U +#define _reg_PI_CONTROL_ERROR_STATUS 0x00000204U +#define _reg_PI_EXIT_AFTER_INIT_CALVL 0x00000205U +#define _reg_PI_FREQ_MAP 0x00000206U +#define _reg_PI_INIT_WORK_FREQ 0x00000207U +#define _reg_PI_INIT_DFS_CALVL_ONLY 0x00000208U +#define _reg_PI_POWER_ON_SEQ_BYPASS_ARRAY 0x00000209U +#define _reg_PI_POWER_ON_SEQ_END_ARRAY 0x0000020aU +#define _reg_PI_SEQ1_PAT 0x0000020bU +#define _reg_PI_SEQ1_PAT_MASK 0x0000020cU +#define _reg_PI_SEQ2_PAT 0x0000020dU +#define _reg_PI_SEQ2_PAT_MASK 0x0000020eU +#define _reg_PI_SEQ3_PAT 0x0000020fU +#define _reg_PI_SEQ3_PAT_MASK 0x00000210U +#define _reg_PI_SEQ4_PAT 0x00000211U +#define _reg_PI_SEQ4_PAT_MASK 0x00000212U +#define _reg_PI_SEQ5_PAT 0x00000213U +#define _reg_PI_SEQ5_PAT_MASK 0x00000214U +#define _reg_PI_SEQ6_PAT 0x00000215U +#define _reg_PI_SEQ6_PAT_MASK 0x00000216U +#define _reg_PI_SEQ7_PAT 0x00000217U +#define _reg_PI_SEQ7_PAT_MASK 0x00000218U +#define _reg_PI_SEQ8_PAT 0x00000219U +#define _reg_PI_SEQ8_PAT_MASK 0x0000021aU +#define _reg_PI_WDT_DISABLE 0x0000021bU +#define _reg_PI_SW_RST_N 0x0000021cU +#define _reg_RESERVED_R0 0x0000021dU +#define _reg_PI_CS_MAP 0x0000021eU +#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F0 0x0000021fU +#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F1 0x00000220U +#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x00000221U +#define _reg_PI_TMRR 0x00000222U +#define _reg_PI_WRLAT_F0 0x00000223U +#define _reg_PI_ADDITIVE_LAT_F0 0x00000224U +#define _reg_PI_CASLAT_LIN_F0 0x00000225U +#define _reg_PI_WRLAT_F1 0x00000226U +#define _reg_PI_ADDITIVE_LAT_F1 0x00000227U +#define _reg_PI_CASLAT_LIN_F1 0x00000228U +#define _reg_PI_WRLAT_F2 0x00000229U +#define _reg_PI_ADDITIVE_LAT_F2 0x0000022aU +#define _reg_PI_CASLAT_LIN_F2 0x0000022bU +#define _reg_PI_PREAMBLE_SUPPORT 0x0000022cU +#define _reg_PI_AREFRESH 0x0000022dU +#define _reg_PI_MCAREF_FORWARD_ONLY 0x0000022eU +#define _reg_PI_TRFC_F0 0x0000022fU +#define _reg_PI_TREF_F0 0x00000230U +#define _reg_PI_TRFC_F1 0x00000231U +#define _reg_PI_TREF_F1 0x00000232U +#define _reg_PI_TRFC_F2 0x00000233U +#define _reg_PI_TREF_F2 0x00000234U +#define _reg_RESERVED_H3VER2 0x00000235U +#define _reg_PI_TREF_INTERVAL 0x00000236U +#define _reg_PI_FREQ_CHANGE_REG_COPY 0x00000237U +#define _reg_PI_FREQ_SEL_FROM_REGIF 0x00000238U +#define _reg_PI_SWLVL_LOAD 0x00000239U +#define _reg_PI_SWLVL_OP_DONE 0x0000023aU +#define _reg_PI_SW_WRLVL_RESP_0 0x0000023bU +#define _reg_PI_SW_WRLVL_RESP_1 0x0000023cU +#define _reg_PI_SW_WRLVL_RESP_2 0x0000023dU +#define _reg_PI_SW_WRLVL_RESP_3 0x0000023eU +#define _reg_PI_SW_RDLVL_RESP_0 0x0000023fU +#define _reg_PI_SW_RDLVL_RESP_1 0x00000240U +#define _reg_PI_SW_RDLVL_RESP_2 0x00000241U +#define _reg_PI_SW_RDLVL_RESP_3 0x00000242U +#define _reg_PI_SW_CALVL_RESP_0 0x00000243U +#define _reg_PI_SW_LEVELING_MODE 0x00000244U +#define _reg_PI_SWLVL_START 0x00000245U +#define _reg_PI_SWLVL_EXIT 0x00000246U +#define _reg_PI_SWLVL_WR_SLICE_0 0x00000247U +#define _reg_PI_SWLVL_RD_SLICE_0 0x00000248U +#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_0 0x00000249U +#define _reg_PI_SW_WDQLVL_RESP_0 0x0000024aU +#define _reg_PI_SWLVL_WR_SLICE_1 0x0000024bU +#define _reg_PI_SWLVL_RD_SLICE_1 0x0000024cU +#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_1 0x0000024dU +#define _reg_PI_SW_WDQLVL_RESP_1 0x0000024eU +#define _reg_PI_SWLVL_WR_SLICE_2 0x0000024fU +#define _reg_PI_SWLVL_RD_SLICE_2 0x00000250U +#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_2 0x00000251U +#define _reg_PI_SW_WDQLVL_RESP_2 0x00000252U +#define _reg_PI_SWLVL_WR_SLICE_3 0x00000253U +#define _reg_PI_SWLVL_RD_SLICE_3 0x00000254U +#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_3 0x00000255U +#define _reg_PI_SW_WDQLVL_RESP_3 0x00000256U +#define _reg_PI_SW_WDQLVL_VREF 0x00000257U +#define _reg_PI_SWLVL_SM2_START 0x00000258U +#define _reg_PI_SWLVL_SM2_WR 0x00000259U +#define _reg_PI_SWLVL_SM2_RD 0x0000025aU +#define _reg_PI_SEQUENTIAL_LVL_REQ 0x0000025bU +#define _reg_PI_DFS_PERIOD_EN 0x0000025cU +#define _reg_PI_SRE_PERIOD_EN 0x0000025dU +#define _reg_PI_DFI40_POLARITY 0x0000025eU +#define _reg_PI_16BIT_DRAM_CONNECT 0x0000025fU +#define _reg_PI_TDFI_CTRL_DELAY_F0 0x00000260U +#define _reg_PI_TDFI_CTRL_DELAY_F1 0x00000261U +#define _reg_PI_TDFI_CTRL_DELAY_F2 0x00000262U +#define _reg_PI_WRLVL_REQ 0x00000263U +#define _reg_PI_WRLVL_CS 0x00000264U +#define _reg_PI_WLDQSEN 0x00000265U +#define _reg_PI_WLMRD 0x00000266U +#define _reg_PI_WRLVL_EN_F0 0x00000267U +#define _reg_PI_WRLVL_EN_F1 0x00000268U +#define _reg_PI_WRLVL_EN_F2 0x00000269U +#define _reg_PI_WRLVL_EN 0x0000026aU +#define _reg_PI_WRLVL_INTERVAL 0x0000026bU +#define _reg_PI_WRLVL_PERIODIC 0x0000026cU +#define _reg_PI_WRLVL_ON_SREF_EXIT 0x0000026dU +#define _reg_PI_WRLVL_DISABLE_DFS 0x0000026eU +#define _reg_PI_WRLVL_RESP_MASK 0x0000026fU +#define _reg_PI_WRLVL_ROTATE 0x00000270U +#define _reg_PI_WRLVL_CS_MAP 0x00000271U +#define _reg_PI_WRLVL_ERROR_STATUS 0x00000272U +#define _reg_PI_TDFI_WRLVL_EN 0x00000273U +#define _reg_PI_TDFI_WRLVL_WW_F0 0x00000274U +#define _reg_PI_TDFI_WRLVL_WW_F1 0x00000275U +#define _reg_PI_TDFI_WRLVL_WW_F2 0x00000276U +#define _reg_PI_TDFI_WRLVL_WW 0x00000277U +#define _reg_PI_TDFI_WRLVL_RESP 0x00000278U +#define _reg_PI_TDFI_WRLVL_MAX 0x00000279U +#define _reg_PI_WRLVL_STROBE_NUM 0x0000027aU +#define _reg_PI_WRLVL_MRR_DQ_RETURN_HIZ 0x0000027bU +#define _reg_PI_WRLVL_EN_DEASSERT_2_MRR 0x0000027cU +#define _reg_PI_TODTL_2CMD_F0 0x0000027dU +#define _reg_PI_ODT_EN_F0 0x0000027eU +#define _reg_PI_TODTL_2CMD_F1 0x0000027fU +#define _reg_PI_ODT_EN_F1 0x00000280U +#define _reg_PI_TODTL_2CMD_F2 0x00000281U +#define _reg_PI_ODT_EN_F2 0x00000282U +#define _reg_PI_TODTH_WR 0x00000283U +#define _reg_PI_TODTH_RD 0x00000284U +#define _reg_PI_ODT_RD_MAP_CS0 0x00000285U +#define _reg_PI_ODT_WR_MAP_CS0 0x00000286U +#define _reg_PI_ODT_RD_MAP_CS1 0x00000287U +#define _reg_PI_ODT_WR_MAP_CS1 0x00000288U +#define _reg_PI_ODT_RD_MAP_CS2 0x00000289U +#define _reg_PI_ODT_WR_MAP_CS2 0x0000028aU +#define _reg_PI_ODT_RD_MAP_CS3 0x0000028bU +#define _reg_PI_ODT_WR_MAP_CS3 0x0000028cU +#define _reg_PI_EN_ODT_ASSERT_EXCEPT_RD 0x0000028dU +#define _reg_PI_ODTLON_F0 0x0000028eU +#define _reg_PI_TODTON_MIN_F0 0x0000028fU +#define _reg_PI_ODTLON_F1 0x00000290U +#define _reg_PI_TODTON_MIN_F1 0x00000291U +#define _reg_PI_ODTLON_F2 0x00000292U +#define _reg_PI_TODTON_MIN_F2 0x00000293U +#define _reg_PI_WR_TO_ODTH_F0 0x00000294U +#define _reg_PI_WR_TO_ODTH_F1 0x00000295U +#define _reg_PI_WR_TO_ODTH_F2 0x00000296U +#define _reg_PI_RD_TO_ODTH_F0 0x00000297U +#define _reg_PI_RD_TO_ODTH_F1 0x00000298U +#define _reg_PI_RD_TO_ODTH_F2 0x00000299U +#define _reg_PI_ADDRESS_MIRRORING 0x0000029aU +#define _reg_PI_RDLVL_REQ 0x0000029bU +#define _reg_PI_RDLVL_GATE_REQ 0x0000029cU +#define _reg_PI_RDLVL_CS 0x0000029dU +#define _reg_PI_RDLVL_PAT_0 0x0000029eU +#define _reg_PI_RDLVL_PAT_1 0x0000029fU +#define _reg_PI_RDLVL_PAT_2 0x000002a0U +#define _reg_PI_RDLVL_PAT_3 0x000002a1U +#define _reg_PI_RDLVL_PAT_4 0x000002a2U +#define _reg_PI_RDLVL_PAT_5 0x000002a3U +#define _reg_PI_RDLVL_PAT_6 0x000002a4U +#define _reg_PI_RDLVL_PAT_7 0x000002a5U +#define _reg_PI_RDLVL_SEQ_EN 0x000002a6U +#define _reg_PI_RDLVL_GATE_SEQ_EN 0x000002a7U +#define _reg_PI_RDLVL_PERIODIC 0x000002a8U +#define _reg_PI_RDLVL_ON_SREF_EXIT 0x000002a9U +#define _reg_PI_RDLVL_DISABLE_DFS 0x000002aaU +#define _reg_PI_RDLVL_GATE_PERIODIC 0x000002abU +#define _reg_PI_RDLVL_GATE_ON_SREF_EXIT 0x000002acU +#define _reg_PI_RDLVL_GATE_DISABLE_DFS 0x000002adU +#define _reg_RESERVED_R1 0x000002aeU +#define _reg_PI_RDLVL_ROTATE 0x000002afU +#define _reg_PI_RDLVL_GATE_ROTATE 0x000002b0U +#define _reg_PI_RDLVL_CS_MAP 0x000002b1U +#define _reg_PI_RDLVL_GATE_CS_MAP 0x000002b2U +#define _reg_PI_TDFI_RDLVL_RR 0x000002b3U +#define _reg_PI_TDFI_RDLVL_RESP 0x000002b4U +#define _reg_PI_RDLVL_RESP_MASK 0x000002b5U +#define _reg_PI_TDFI_RDLVL_EN 0x000002b6U +#define _reg_PI_RDLVL_EN_F0 0x000002b7U +#define _reg_PI_RDLVL_GATE_EN_F0 0x000002b8U +#define _reg_PI_RDLVL_EN_F1 0x000002b9U +#define _reg_PI_RDLVL_GATE_EN_F1 0x000002baU +#define _reg_PI_RDLVL_EN_F2 0x000002bbU +#define _reg_PI_RDLVL_GATE_EN_F2 0x000002bcU +#define _reg_PI_RDLVL_EN 0x000002bdU +#define _reg_PI_RDLVL_GATE_EN 0x000002beU +#define _reg_PI_TDFI_RDLVL_MAX 0x000002bfU +#define _reg_PI_RDLVL_ERROR_STATUS 0x000002c0U +#define _reg_PI_RDLVL_INTERVAL 0x000002c1U +#define _reg_PI_RDLVL_GATE_INTERVAL 0x000002c2U +#define _reg_PI_RDLVL_PATTERN_START 0x000002c3U +#define _reg_PI_RDLVL_PATTERN_NUM 0x000002c4U +#define _reg_PI_RDLVL_STROBE_NUM 0x000002c5U +#define _reg_PI_RDLVL_GATE_STROBE_NUM 0x000002c6U +#define _reg_PI_LPDDR4_RDLVL_PATTERN_8 0x000002c7U +#define _reg_PI_LPDDR4_RDLVL_PATTERN_9 0x000002c8U +#define _reg_PI_LPDDR4_RDLVL_PATTERN_10 0x000002c9U +#define _reg_PI_LPDDR4_RDLVL_PATTERN_11 0x000002caU +#define _reg_PI_RD_PREAMBLE_TRAINING_EN 0x000002cbU +#define _reg_PI_REG_DIMM_ENABLE 0x000002ccU +#define _reg_PI_RDLAT_ADJ_F0 0x000002cdU +#define _reg_PI_RDLAT_ADJ_F1 0x000002ceU +#define _reg_PI_RDLAT_ADJ_F2 0x000002cfU +#define _reg_PI_TDFI_RDDATA_EN 0x000002d0U +#define _reg_PI_WRLAT_ADJ_F0 0x000002d1U +#define _reg_PI_WRLAT_ADJ_F1 0x000002d2U +#define _reg_PI_WRLAT_ADJ_F2 0x000002d3U +#define _reg_PI_TDFI_PHY_WRLAT 0x000002d4U +#define _reg_PI_TDFI_WRCSLAT_F0 0x000002d5U +#define _reg_PI_TDFI_WRCSLAT_F1 0x000002d6U +#define _reg_PI_TDFI_WRCSLAT_F2 0x000002d7U +#define _reg_PI_TDFI_RDCSLAT_F0 0x000002d8U +#define _reg_PI_TDFI_RDCSLAT_F1 0x000002d9U +#define _reg_PI_TDFI_RDCSLAT_F2 0x000002daU +#define _reg_PI_TDFI_PHY_WRDATA_F0 0x000002dbU +#define _reg_PI_TDFI_PHY_WRDATA_F1 0x000002dcU +#define _reg_PI_TDFI_PHY_WRDATA_F2 0x000002ddU +#define _reg_PI_TDFI_PHY_WRDATA 0x000002deU +#define _reg_PI_CALVL_REQ 0x000002dfU +#define _reg_PI_CALVL_CS 0x000002e0U +#define _reg_RESERVED_R2 0x000002e1U +#define _reg_RESERVED_R3 0x000002e2U +#define _reg_PI_CALVL_SEQ_EN 0x000002e3U +#define _reg_PI_CALVL_PERIODIC 0x000002e4U +#define _reg_PI_CALVL_ON_SREF_EXIT 0x000002e5U +#define _reg_PI_CALVL_DISABLE_DFS 0x000002e6U +#define _reg_PI_CALVL_ROTATE 0x000002e7U +#define _reg_PI_CALVL_CS_MAP 0x000002e8U +#define _reg_PI_TDFI_CALVL_EN 0x000002e9U +#define _reg_PI_TDFI_CALVL_CC_F0 0x000002eaU +#define _reg_PI_TDFI_CALVL_CAPTURE_F0 0x000002ebU +#define _reg_PI_TDFI_CALVL_CC_F1 0x000002ecU +#define _reg_PI_TDFI_CALVL_CAPTURE_F1 0x000002edU +#define _reg_PI_TDFI_CALVL_CC_F2 0x000002eeU +#define _reg_PI_TDFI_CALVL_CAPTURE_F2 0x000002efU +#define _reg_PI_TDFI_CALVL_RESP 0x000002f0U +#define _reg_PI_TDFI_CALVL_MAX 0x000002f1U +#define _reg_PI_CALVL_RESP_MASK 0x000002f2U +#define _reg_PI_CALVL_EN_F0 0x000002f3U +#define _reg_PI_CALVL_EN_F1 0x000002f4U +#define _reg_PI_CALVL_EN_F2 0x000002f5U +#define _reg_PI_CALVL_EN 0x000002f6U +#define _reg_PI_CALVL_ERROR_STATUS 0x000002f7U +#define _reg_PI_CALVL_INTERVAL 0x000002f8U +#define _reg_PI_TCACKEL 0x000002f9U +#define _reg_PI_TCAMRD 0x000002faU +#define _reg_PI_TCACKEH 0x000002fbU +#define _reg_PI_TMRZ_F0 0x000002fcU +#define _reg_PI_TCAENT_F0 0x000002fdU +#define _reg_PI_TMRZ_F1 0x000002feU +#define _reg_PI_TCAENT_F1 0x000002ffU +#define _reg_PI_TMRZ_F2 0x00000300U +#define _reg_PI_TCAENT_F2 0x00000301U +#define _reg_PI_TCAEXT 0x00000302U +#define _reg_PI_CA_TRAIN_VREF_EN 0x00000303U +#define _reg_PI_TDFI_CACSCA_F0 0x00000304U +#define _reg_PI_TDFI_CASEL_F0 0x00000305U +#define _reg_PI_TVREF_SHORT_F0 0x00000306U +#define _reg_PI_TVREF_LONG_F0 0x00000307U +#define _reg_PI_TDFI_CACSCA_F1 0x00000308U +#define _reg_PI_TDFI_CASEL_F1 0x00000309U +#define _reg_PI_TVREF_SHORT_F1 0x0000030aU +#define _reg_PI_TVREF_LONG_F1 0x0000030bU +#define _reg_PI_TDFI_CACSCA_F2 0x0000030cU +#define _reg_PI_TDFI_CASEL_F2 0x0000030dU +#define _reg_PI_TVREF_SHORT_F2 0x0000030eU +#define _reg_PI_TVREF_LONG_F2 0x0000030fU +#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F0 0x00000310U +#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F0 0x00000311U +#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F1 0x00000312U +#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F1 0x00000313U +#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F2 0x00000314U +#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x00000315U +#define _reg_PI_CALVL_VREF_INITIAL_START_POINT 0x00000316U +#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT 0x00000317U +#define _reg_PI_CALVL_VREF_INITIAL_STEPSIZE 0x00000318U +#define _reg_PI_CALVL_VREF_NORMAL_STEPSIZE 0x00000319U +#define _reg_PI_CALVL_VREF_DELTA_F0 0x0000031aU +#define _reg_PI_CALVL_VREF_DELTA_F1 0x0000031bU +#define _reg_PI_CALVL_VREF_DELTA_F2 0x0000031cU +#define _reg_PI_CALVL_VREF_DELTA 0x0000031dU +#define _reg_PI_TDFI_INIT_START_MIN 0x0000031eU +#define _reg_PI_TDFI_INIT_COMPLETE_MIN 0x0000031fU +#define _reg_PI_TDFI_CALVL_STROBE_F0 0x00000320U +#define _reg_PI_TXP_F0 0x00000321U +#define _reg_PI_TMRWCKEL_F0 0x00000322U +#define _reg_PI_TCKELCK_F0 0x00000323U +#define _reg_PI_TDFI_CALVL_STROBE_F1 0x00000324U +#define _reg_PI_TXP_F1 0x00000325U +#define _reg_PI_TMRWCKEL_F1 0x00000326U +#define _reg_PI_TCKELCK_F1 0x00000327U +#define _reg_PI_TDFI_CALVL_STROBE_F2 0x00000328U +#define _reg_PI_TXP_F2 0x00000329U +#define _reg_PI_TMRWCKEL_F2 0x0000032aU +#define _reg_PI_TCKELCK_F2 0x0000032bU +#define _reg_PI_TCKCKEH 0x0000032cU +#define _reg_PI_CALVL_STROBE_NUM 0x0000032dU +#define _reg_PI_SW_CA_TRAIN_VREF 0x0000032eU +#define _reg_PI_TDFI_INIT_START_F0 0x0000032fU +#define _reg_PI_TDFI_INIT_COMPLETE_F0 0x00000330U +#define _reg_PI_TDFI_INIT_START_F1 0x00000331U +#define _reg_PI_TDFI_INIT_COMPLETE_F1 0x00000332U +#define _reg_PI_TDFI_INIT_START_F2 0x00000333U +#define _reg_PI_TDFI_INIT_COMPLETE_F2 0x00000334U +#define _reg_PI_CLKDISABLE_2_INIT_START 0x00000335U +#define _reg_PI_INIT_STARTORCOMPLETE_2_CLKDISABLE 0x00000336U +#define _reg_PI_DRAM_CLK_DISABLE_DEASSERT_SEL 0x00000337U +#define _reg_PI_REFRESH_BETWEEN_SEGMENT_DISABLE 0x00000338U +#define _reg_PI_TCKEHDQS_F0 0x00000339U +#define _reg_PI_TCKEHDQS_F1 0x0000033aU +#define _reg_PI_TCKEHDQS_F2 0x0000033bU +#define _reg_PI_MC_DFS_PI_SET_VREF_ENABLE 0x0000033cU +#define _reg_PI_WDQLVL_VREF_EN 0x0000033dU +#define _reg_PI_WDQLVL_BST_NUM 0x0000033eU +#define _reg_PI_TDFI_WDQLVL_WR_F0 0x0000033fU +#define _reg_PI_TDFI_WDQLVL_WR_F1 0x00000340U +#define _reg_PI_TDFI_WDQLVL_WR_F2 0x00000341U +#define _reg_PI_TDFI_WDQLVL_WR 0x00000342U +#define _reg_PI_TDFI_WDQLVL_RW 0x00000343U +#define _reg_PI_WDQLVL_RESP_MASK 0x00000344U +#define _reg_PI_WDQLVL_ROTATE 0x00000345U +#define _reg_PI_WDQLVL_CS_MAP 0x00000346U +#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x00000347U +#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x00000348U +#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x00000349U +#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x0000034aU +#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x0000034bU +#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x0000034cU +#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT 0x0000034dU +#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT 0x0000034eU +#define _reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE 0x0000034fU +#define _reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE 0x00000350U +#define _reg_PI_WDQLVL_VREF_DELTA_F0 0x00000351U +#define _reg_PI_WDQLVL_VREF_DELTA_F1 0x00000352U +#define _reg_PI_WDQLVL_VREF_DELTA_F2 0x00000353U +#define _reg_PI_WDQLVL_VREF_DELTA 0x00000354U +#define _reg_PI_WDQLVL_PERIODIC 0x00000355U +#define _reg_PI_WDQLVL_REQ 0x00000356U +#define _reg_PI_WDQLVL_CS 0x00000357U +#define _reg_PI_TDFI_WDQLVL_EN 0x00000358U +#define _reg_PI_TDFI_WDQLVL_RESP 0x00000359U +#define _reg_PI_TDFI_WDQLVL_MAX 0x0000035aU +#define _reg_PI_WDQLVL_INTERVAL 0x0000035bU +#define _reg_PI_WDQLVL_EN_F0 0x0000035cU +#define _reg_PI_WDQLVL_EN_F1 0x0000035dU +#define _reg_PI_WDQLVL_EN_F2 0x0000035eU +#define _reg_PI_WDQLVL_EN 0x0000035fU +#define _reg_PI_WDQLVL_ON_SREF_EXIT 0x00000360U +#define _reg_PI_WDQLVL_DISABLE_DFS 0x00000361U +#define _reg_PI_WDQLVL_ERROR_STATUS 0x00000362U +#define _reg_PI_MR1_DATA_F0_0 0x00000363U +#define _reg_PI_MR2_DATA_F0_0 0x00000364U +#define _reg_PI_MR3_DATA_F0_0 0x00000365U +#define _reg_PI_MR11_DATA_F0_0 0x00000366U +#define _reg_PI_MR12_DATA_F0_0 0x00000367U +#define _reg_PI_MR14_DATA_F0_0 0x00000368U +#define _reg_PI_MR22_DATA_F0_0 0x00000369U +#define _reg_PI_MR1_DATA_F1_0 0x0000036aU +#define _reg_PI_MR2_DATA_F1_0 0x0000036bU +#define _reg_PI_MR3_DATA_F1_0 0x0000036cU +#define _reg_PI_MR11_DATA_F1_0 0x0000036dU +#define _reg_PI_MR12_DATA_F1_0 0x0000036eU +#define _reg_PI_MR14_DATA_F1_0 0x0000036fU +#define _reg_PI_MR22_DATA_F1_0 0x00000370U +#define _reg_PI_MR1_DATA_F2_0 0x00000371U +#define _reg_PI_MR2_DATA_F2_0 0x00000372U +#define _reg_PI_MR3_DATA_F2_0 0x00000373U +#define _reg_PI_MR11_DATA_F2_0 0x00000374U +#define _reg_PI_MR12_DATA_F2_0 0x00000375U +#define _reg_PI_MR14_DATA_F2_0 0x00000376U +#define _reg_PI_MR22_DATA_F2_0 0x00000377U +#define _reg_PI_MR13_DATA_0 0x00000378U +#define _reg_PI_MR1_DATA_F0_1 0x00000379U +#define _reg_PI_MR2_DATA_F0_1 0x0000037aU +#define _reg_PI_MR3_DATA_F0_1 0x0000037bU +#define _reg_PI_MR11_DATA_F0_1 0x0000037cU +#define _reg_PI_MR12_DATA_F0_1 0x0000037dU +#define _reg_PI_MR14_DATA_F0_1 0x0000037eU +#define _reg_PI_MR22_DATA_F0_1 0x0000037fU +#define _reg_PI_MR1_DATA_F1_1 0x00000380U +#define _reg_PI_MR2_DATA_F1_1 0x00000381U +#define _reg_PI_MR3_DATA_F1_1 0x00000382U +#define _reg_PI_MR11_DATA_F1_1 0x00000383U +#define _reg_PI_MR12_DATA_F1_1 0x00000384U +#define _reg_PI_MR14_DATA_F1_1 0x00000385U +#define _reg_PI_MR22_DATA_F1_1 0x00000386U +#define _reg_PI_MR1_DATA_F2_1 0x00000387U +#define _reg_PI_MR2_DATA_F2_1 0x00000388U +#define _reg_PI_MR3_DATA_F2_1 0x00000389U +#define _reg_PI_MR11_DATA_F2_1 0x0000038aU +#define _reg_PI_MR12_DATA_F2_1 0x0000038bU +#define _reg_PI_MR14_DATA_F2_1 0x0000038cU +#define _reg_PI_MR22_DATA_F2_1 0x0000038dU +#define _reg_PI_MR13_DATA_1 0x0000038eU +#define _reg_PI_MR1_DATA_F0_2 0x0000038fU +#define _reg_PI_MR2_DATA_F0_2 0x00000390U +#define _reg_PI_MR3_DATA_F0_2 0x00000391U +#define _reg_PI_MR11_DATA_F0_2 0x00000392U +#define _reg_PI_MR12_DATA_F0_2 0x00000393U +#define _reg_PI_MR14_DATA_F0_2 0x00000394U +#define _reg_PI_MR22_DATA_F0_2 0x00000395U +#define _reg_PI_MR1_DATA_F1_2 0x00000396U +#define _reg_PI_MR2_DATA_F1_2 0x00000397U +#define _reg_PI_MR3_DATA_F1_2 0x00000398U +#define _reg_PI_MR11_DATA_F1_2 0x00000399U +#define _reg_PI_MR12_DATA_F1_2 0x0000039aU +#define _reg_PI_MR14_DATA_F1_2 0x0000039bU +#define _reg_PI_MR22_DATA_F1_2 0x0000039cU +#define _reg_PI_MR1_DATA_F2_2 0x0000039dU +#define _reg_PI_MR2_DATA_F2_2 0x0000039eU +#define _reg_PI_MR3_DATA_F2_2 0x0000039fU +#define _reg_PI_MR11_DATA_F2_2 0x000003a0U +#define _reg_PI_MR12_DATA_F2_2 0x000003a1U +#define _reg_PI_MR14_DATA_F2_2 0x000003a2U +#define _reg_PI_MR22_DATA_F2_2 0x000003a3U +#define _reg_PI_MR13_DATA_2 0x000003a4U +#define _reg_PI_MR1_DATA_F0_3 0x000003a5U +#define _reg_PI_MR2_DATA_F0_3 0x000003a6U +#define _reg_PI_MR3_DATA_F0_3 0x000003a7U +#define _reg_PI_MR11_DATA_F0_3 0x000003a8U +#define _reg_PI_MR12_DATA_F0_3 0x000003a9U +#define _reg_PI_MR14_DATA_F0_3 0x000003aaU +#define _reg_PI_MR22_DATA_F0_3 0x000003abU +#define _reg_PI_MR1_DATA_F1_3 0x000003acU +#define _reg_PI_MR2_DATA_F1_3 0x000003adU +#define _reg_PI_MR3_DATA_F1_3 0x000003aeU +#define _reg_PI_MR11_DATA_F1_3 0x000003afU +#define _reg_PI_MR12_DATA_F1_3 0x000003b0U +#define _reg_PI_MR14_DATA_F1_3 0x000003b1U +#define _reg_PI_MR22_DATA_F1_3 0x000003b2U +#define _reg_PI_MR1_DATA_F2_3 0x000003b3U +#define _reg_PI_MR2_DATA_F2_3 0x000003b4U +#define _reg_PI_MR3_DATA_F2_3 0x000003b5U +#define _reg_PI_MR11_DATA_F2_3 0x000003b6U +#define _reg_PI_MR12_DATA_F2_3 0x000003b7U +#define _reg_PI_MR14_DATA_F2_3 0x000003b8U +#define _reg_PI_MR22_DATA_F2_3 0x000003b9U +#define _reg_PI_MR13_DATA_3 0x000003baU +#define _reg_PI_BANK_DIFF 0x000003bbU +#define _reg_PI_ROW_DIFF 0x000003bcU +#define _reg_PI_TFC_F0 0x000003bdU +#define _reg_PI_TFC_F1 0x000003beU +#define _reg_PI_TFC_F2 0x000003bfU +#define _reg_PI_TCCD 0x000003c0U +#define _reg_PI_TRTP_F0 0x000003c1U +#define _reg_PI_TRP_F0 0x000003c2U +#define _reg_PI_TRCD_F0 0x000003c3U +#define _reg_PI_TWTR_F0 0x000003c4U +#define _reg_PI_TWR_F0 0x000003c5U +#define _reg_PI_TRAS_MAX_F0 0x000003c6U +#define _reg_PI_TRAS_MIN_F0 0x000003c7U +#define _reg_PI_TDQSCK_MAX_F0 0x000003c8U +#define _reg_PI_TCCDMW_F0 0x000003c9U +#define _reg_PI_TSR_F0 0x000003caU +#define _reg_PI_TMRD_F0 0x000003cbU +#define _reg_PI_TMRW_F0 0x000003ccU +#define _reg_PI_TMOD_F0 0x000003cdU +#define _reg_PI_TRTP_F1 0x000003ceU +#define _reg_PI_TRP_F1 0x000003cfU +#define _reg_PI_TRCD_F1 0x000003d0U +#define _reg_PI_TWTR_F1 0x000003d1U +#define _reg_PI_TWR_F1 0x000003d2U +#define _reg_PI_TRAS_MAX_F1 0x000003d3U +#define _reg_PI_TRAS_MIN_F1 0x000003d4U +#define _reg_PI_TDQSCK_MAX_F1 0x000003d5U +#define _reg_PI_TCCDMW_F1 0x000003d6U +#define _reg_PI_TSR_F1 0x000003d7U +#define _reg_PI_TMRD_F1 0x000003d8U +#define _reg_PI_TMRW_F1 0x000003d9U +#define _reg_PI_TMOD_F1 0x000003daU +#define _reg_PI_TRTP_F2 0x000003dbU +#define _reg_PI_TRP_F2 0x000003dcU +#define _reg_PI_TRCD_F2 0x000003ddU +#define _reg_PI_TWTR_F2 0x000003deU +#define _reg_PI_TWR_F2 0x000003dfU +#define _reg_PI_TRAS_MAX_F2 0x000003e0U +#define _reg_PI_TRAS_MIN_F2 0x000003e1U +#define _reg_PI_TDQSCK_MAX_F2 0x000003e2U +#define _reg_PI_TCCDMW_F2 0x000003e3U +#define _reg_PI_TSR_F2 0x000003e4U +#define _reg_PI_TMRD_F2 0x000003e5U +#define _reg_PI_TMRW_F2 0x000003e6U +#define _reg_PI_TMOD_F2 0x000003e7U +#define _reg_RESERVED_R4 0x000003e8U +#define _reg_RESERVED_R5 0x000003e9U +#define _reg_RESERVED_R6 0x000003eaU +#define _reg_RESERVED_R7 0x000003ebU +#define _reg_RESERVED_R8 0x000003ecU +#define _reg_RESERVED_R9 0x000003edU +#define _reg_RESERVED_R10 0x000003eeU +#define _reg_RESERVED_R11 0x000003efU +#define _reg_RESERVED_R12 0x000003f0U +#define _reg_RESERVED_R13 0x000003f1U +#define _reg_RESERVED_R14 0x000003f2U +#define _reg_RESERVED_R15 0x000003f3U +#define _reg_RESERVED_R16 0x000003f4U +#define _reg_RESERVED_R17 0x000003f5U +#define _reg_RESERVED_R18 0x000003f6U +#define _reg_RESERVED_R19 0x000003f7U +#define _reg_RESERVED_R20 0x000003f8U +#define _reg_RESERVED_R21 0x000003f9U +#define _reg_RESERVED_R22 0x000003faU +#define _reg_RESERVED_R23 0x000003fbU +#define _reg_PI_INT_STATUS 0x000003fcU +#define _reg_PI_INT_ACK 0x000003fdU +#define _reg_PI_INT_MASK 0x000003feU +#define _reg_PI_BIST_EXP_DATA_P0 0x000003ffU +#define _reg_PI_BIST_EXP_DATA_P1 0x00000400U +#define _reg_PI_BIST_EXP_DATA_P2 0x00000401U +#define _reg_PI_BIST_EXP_DATA_P3 0x00000402U +#define _reg_PI_BIST_FAIL_DATA_P0 0x00000403U +#define _reg_PI_BIST_FAIL_DATA_P1 0x00000404U +#define _reg_PI_BIST_FAIL_DATA_P2 0x00000405U +#define _reg_PI_BIST_FAIL_DATA_P3 0x00000406U +#define _reg_PI_BIST_FAIL_ADDR_P0 0x00000407U +#define _reg_PI_BIST_FAIL_ADDR_P1 0x00000408U +#define _reg_PI_BSTLEN 0x00000409U +#define _reg_PI_LONG_COUNT_MASK 0x0000040aU +#define _reg_PI_CMD_SWAP_EN 0x0000040bU +#define _reg_PI_CKE_MUX_0 0x0000040cU +#define _reg_PI_CKE_MUX_1 0x0000040dU +#define _reg_PI_CKE_MUX_2 0x0000040eU +#define _reg_PI_CKE_MUX_3 0x0000040fU +#define _reg_PI_CS_MUX_0 0x00000410U +#define _reg_PI_CS_MUX_1 0x00000411U +#define _reg_PI_CS_MUX_2 0x00000412U +#define _reg_PI_CS_MUX_3 0x00000413U +#define _reg_PI_RAS_N_MUX 0x00000414U +#define _reg_PI_CAS_N_MUX 0x00000415U +#define _reg_PI_WE_N_MUX 0x00000416U +#define _reg_PI_BANK_MUX_0 0x00000417U +#define _reg_PI_BANK_MUX_1 0x00000418U +#define _reg_PI_BANK_MUX_2 0x00000419U +#define _reg_PI_ODT_MUX_0 0x0000041aU +#define _reg_PI_ODT_MUX_1 0x0000041bU +#define _reg_PI_ODT_MUX_2 0x0000041cU +#define _reg_PI_ODT_MUX_3 0x0000041dU +#define _reg_PI_RESET_N_MUX_0 0x0000041eU +#define _reg_PI_RESET_N_MUX_1 0x0000041fU +#define _reg_PI_RESET_N_MUX_2 0x00000420U +#define _reg_PI_RESET_N_MUX_3 0x00000421U +#define _reg_PI_DATA_BYTE_SWAP_EN 0x00000422U +#define _reg_PI_DATA_BYTE_SWAP_SLICE0 0x00000423U +#define _reg_PI_DATA_BYTE_SWAP_SLICE1 0x00000424U +#define _reg_PI_DATA_BYTE_SWAP_SLICE2 0x00000425U +#define _reg_PI_DATA_BYTE_SWAP_SLICE3 0x00000426U +#define _reg_PI_CTRLUPD_REQ_PER_AREF_EN 0x00000427U +#define _reg_PI_TDFI_CTRLUPD_MIN 0x00000428U +#define _reg_PI_TDFI_CTRLUPD_MAX_F0 0x00000429U +#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F0 0x0000042aU +#define _reg_PI_TDFI_CTRLUPD_MAX_F1 0x0000042bU +#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F1 0x0000042cU +#define _reg_PI_TDFI_CTRLUPD_MAX_F2 0x0000042dU +#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F2 0x0000042eU +#define _reg_PI_UPDATE_ERROR_STATUS 0x0000042fU +#define _reg_PI_BIST_GO 0x00000430U +#define _reg_PI_BIST_RESULT 0x00000431U +#define _reg_PI_ADDR_SPACE 0x00000432U +#define _reg_PI_BIST_DATA_CHECK 0x00000433U +#define _reg_PI_BIST_ADDR_CHECK 0x00000434U +#define _reg_PI_BIST_START_ADDRESS_P0 0x00000435U +#define _reg_PI_BIST_START_ADDRESS_P1 0x00000436U +#define _reg_PI_BIST_DATA_MASK_P0 0x00000437U +#define _reg_PI_BIST_DATA_MASK_P1 0x00000438U +#define _reg_PI_BIST_ERR_COUNT 0x00000439U +#define _reg_PI_BIST_ERR_STOP 0x0000043aU +#define _reg_PI_BIST_ADDR_MASK_0_P0 0x0000043bU +#define _reg_PI_BIST_ADDR_MASK_0_P1 0x0000043cU +#define _reg_PI_BIST_ADDR_MASK_1_P0 0x0000043dU +#define _reg_PI_BIST_ADDR_MASK_1_P1 0x0000043eU +#define _reg_PI_BIST_ADDR_MASK_2_P0 0x0000043fU +#define _reg_PI_BIST_ADDR_MASK_2_P1 0x00000440U +#define _reg_PI_BIST_ADDR_MASK_3_P0 0x00000441U +#define _reg_PI_BIST_ADDR_MASK_3_P1 0x00000442U +#define _reg_PI_BIST_ADDR_MASK_4_P0 0x00000443U +#define _reg_PI_BIST_ADDR_MASK_4_P1 0x00000444U +#define _reg_PI_BIST_ADDR_MASK_5_P0 0x00000445U +#define _reg_PI_BIST_ADDR_MASK_5_P1 0x00000446U +#define _reg_PI_BIST_ADDR_MASK_6_P0 0x00000447U +#define _reg_PI_BIST_ADDR_MASK_6_P1 0x00000448U +#define _reg_PI_BIST_ADDR_MASK_7_P0 0x00000449U +#define _reg_PI_BIST_ADDR_MASK_7_P1 0x0000044aU +#define _reg_PI_BIST_ADDR_MASK_8_P0 0x0000044bU +#define _reg_PI_BIST_ADDR_MASK_8_P1 0x0000044cU +#define _reg_PI_BIST_ADDR_MASK_9_P0 0x0000044dU +#define _reg_PI_BIST_ADDR_MASK_9_P1 0x0000044eU +#define _reg_PI_BIST_MODE 0x0000044fU +#define _reg_PI_BIST_ADDR_MODE 0x00000450U +#define _reg_PI_BIST_PAT_MODE 0x00000451U +#define _reg_PI_BIST_USER_PAT_P0 0x00000452U +#define _reg_PI_BIST_USER_PAT_P1 0x00000453U +#define _reg_PI_BIST_USER_PAT_P2 0x00000454U +#define _reg_PI_BIST_USER_PAT_P3 0x00000455U +#define _reg_PI_BIST_PAT_NUM 0x00000456U +#define _reg_PI_BIST_STAGE_0 0x00000457U +#define _reg_PI_BIST_STAGE_1 0x00000458U +#define _reg_PI_BIST_STAGE_2 0x00000459U +#define _reg_PI_BIST_STAGE_3 0x0000045aU +#define _reg_PI_BIST_STAGE_4 0x0000045bU +#define _reg_PI_BIST_STAGE_5 0x0000045cU +#define _reg_PI_BIST_STAGE_6 0x0000045dU +#define _reg_PI_BIST_STAGE_7 0x0000045eU +#define _reg_PI_COL_DIFF 0x0000045fU +#define _reg_PI_SELF_REFRESH_EN 0x00000460U +#define _reg_PI_TXSR_F0 0x00000461U +#define _reg_PI_TXSR_F1 0x00000462U +#define _reg_PI_TXSR_F2 0x00000463U +#define _reg_PI_MONITOR_SRC_SEL_0 0x00000464U +#define _reg_PI_MONITOR_CAP_SEL_0 0x00000465U +#define _reg_PI_MONITOR_0 0x00000466U +#define _reg_PI_MONITOR_SRC_SEL_1 0x00000467U +#define _reg_PI_MONITOR_CAP_SEL_1 0x00000468U +#define _reg_PI_MONITOR_1 0x00000469U +#define _reg_PI_MONITOR_SRC_SEL_2 0x0000046aU +#define _reg_PI_MONITOR_CAP_SEL_2 0x0000046bU +#define _reg_PI_MONITOR_2 0x0000046cU +#define _reg_PI_MONITOR_SRC_SEL_3 0x0000046dU +#define _reg_PI_MONITOR_CAP_SEL_3 0x0000046eU +#define _reg_PI_MONITOR_3 0x0000046fU +#define _reg_PI_MONITOR_SRC_SEL_4 0x00000470U +#define _reg_PI_MONITOR_CAP_SEL_4 0x00000471U +#define _reg_PI_MONITOR_4 0x00000472U +#define _reg_PI_MONITOR_SRC_SEL_5 0x00000473U +#define _reg_PI_MONITOR_CAP_SEL_5 0x00000474U +#define _reg_PI_MONITOR_5 0x00000475U +#define _reg_PI_MONITOR_SRC_SEL_6 0x00000476U +#define _reg_PI_MONITOR_CAP_SEL_6 0x00000477U +#define _reg_PI_MONITOR_6 0x00000478U +#define _reg_PI_MONITOR_SRC_SEL_7 0x00000479U +#define _reg_PI_MONITOR_CAP_SEL_7 0x0000047aU +#define _reg_PI_MONITOR_7 0x0000047bU +#define _reg_PI_MONITOR_STROBE 0x0000047cU +#define _reg_PI_DLL_LOCK 0x0000047dU +#define _reg_PI_FREQ_NUMBER_STATUS 0x0000047eU +#define _reg_RESERVED_R24 0x0000047fU +#define _reg_PI_PHYMSTR_TYPE 0x00000480U +#define _reg_PI_POWER_REDUC_EN 0x00000481U +#define _reg_RESERVED_R25 0x00000482U +#define _reg_RESERVED_R26 0x00000483U +#define _reg_RESERVED_R27 0x00000484U +#define _reg_RESERVED_R28 0x00000485U +#define _reg_RESERVED_R29 0x00000486U +#define _reg_RESERVED_R30 0x00000487U +#define _reg_RESERVED_R31 0x00000488U +#define _reg_RESERVED_R32 0x00000489U +#define _reg_RESERVED_R33 0x0000048aU +#define _reg_RESERVED_R34 0x0000048bU +#define _reg_RESERVED_R35 0x0000048cU +#define _reg_RESERVED_R36 0x0000048dU +#define _reg_RESERVED_R37 0x0000048eU +#define _reg_RESERVED_R38 0x0000048fU +#define _reg_RESERVED_R39 0x00000490U +#define _reg_PI_WRLVL_MAX_STROBE_PEND 0x00000491U +#define _reg_PI_TSDO_F0 0x00000492U +#define _reg_PI_TSDO_F1 0x00000493U +#define _reg_PI_TSDO_F2 0x00000494U + +#define DDR_REGDEF_ADR(regdef) ((regdef)&0xffff) +#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff) +#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff) + +static const uint32_t DDR_REGDEF_TBL[4][1173] = { + { +/*0000*/ 0xffffffffU, +/*0001*/ 0xffffffffU, +/*0002*/ 0x000b0400U, +/*0003*/ 0xffffffffU, +/*0004*/ 0xffffffffU, +/*0005*/ 0x10010400U, +/*0006*/ 0x18050400U, +/*0007*/ 0x00050401U, +/*0008*/ 0x08050401U, +/*0009*/ 0x10050401U, +/*000a*/ 0x18050401U, +/*000b*/ 0x00050402U, +/*000c*/ 0x08050402U, +/*000d*/ 0x10050402U, +/*000e*/ 0x18050402U, +/*000f*/ 0x00040403U, +/*0010*/ 0x08030403U, +/*0011*/ 0x00180404U, +/*0012*/ 0x18030404U, +/*0013*/ 0x00180405U, +/*0014*/ 0x18020405U, +/*0015*/ 0x00010406U, +/*0016*/ 0x08020406U, +/*0017*/ 0x10010406U, +/*0018*/ 0x18010406U, +/*0019*/ 0x00020407U, +/*001a*/ 0x08040407U, +/*001b*/ 0x10040407U, +/*001c*/ 0x18040407U, +/*001d*/ 0x000a0408U, +/*001e*/ 0x10040408U, +/*001f*/ 0xffffffffU, +/*0020*/ 0xffffffffU, +/*0021*/ 0x18070408U, +/*0022*/ 0xffffffffU, +/*0023*/ 0xffffffffU, +/*0024*/ 0xffffffffU, +/*0025*/ 0xffffffffU, +/*0026*/ 0xffffffffU, +/*0027*/ 0xffffffffU, +/*0028*/ 0x000a0409U, +/*0029*/ 0x10040409U, +/*002a*/ 0x18010409U, +/*002b*/ 0x0001040aU, +/*002c*/ 0x0802040aU, +/*002d*/ 0x1009040aU, +/*002e*/ 0x0009040bU, +/*002f*/ 0x1002040bU, +/*0030*/ 0x0020040cU, +/*0031*/ 0xffffffffU, +/*0032*/ 0x0001040dU, +/*0033*/ 0xffffffffU, +/*0034*/ 0xffffffffU, +/*0035*/ 0xffffffffU, +/*0036*/ 0xffffffffU, +/*0037*/ 0x0020040eU, +/*0038*/ 0x0020040fU, +/*0039*/ 0x00200410U, +/*003a*/ 0x00200411U, +/*003b*/ 0x00030412U, +/*003c*/ 0x08010412U, +/*003d*/ 0x10030412U, +/*003e*/ 0x18030412U, +/*003f*/ 0x00040413U, +/*0040*/ 0x08040413U, +/*0041*/ 0x10040413U, +/*0042*/ 0x18040413U, +/*0043*/ 0x00010414U, +/*0044*/ 0x08010414U, +/*0045*/ 0x10060414U, +/*0046*/ 0x18040414U, +/*0047*/ 0xffffffffU, +/*0048*/ 0x00060415U, +/*0049*/ 0x08040415U, +/*004a*/ 0x10060415U, +/*004b*/ 0x18040415U, +/*004c*/ 0x00020416U, +/*004d*/ 0x08050416U, +/*004e*/ 0x10080416U, +/*004f*/ 0x00200417U, +/*0050*/ 0x00060418U, +/*0051*/ 0x08030418U, +/*0052*/ 0x100b0418U, +/*0053*/ 0x00040419U, +/*0054*/ 0x08040419U, +/*0055*/ 0x10040419U, +/*0056*/ 0xffffffffU, +/*0057*/ 0x18010419U, +/*0058*/ 0x0009041aU, +/*0059*/ 0x0020041bU, +/*005a*/ 0x0020041cU, +/*005b*/ 0x0020041dU, +/*005c*/ 0x0020041eU, +/*005d*/ 0x0010041fU, +/*005e*/ 0x00200420U, +/*005f*/ 0x00010421U, +/*0060*/ 0x08060421U, +/*0061*/ 0x10080421U, +/*0062*/ 0x00200422U, +/*0063*/ 0xffffffffU, +/*0064*/ 0x000a0423U, +/*0065*/ 0x10060423U, +/*0066*/ 0x18070423U, +/*0067*/ 0x00080424U, +/*0068*/ 0x08080424U, +/*0069*/ 0x100a0424U, +/*006a*/ 0x00070425U, +/*006b*/ 0x08080425U, +/*006c*/ 0x10080425U, +/*006d*/ 0x18030425U, +/*006e*/ 0x000a0426U, +/*006f*/ 0x100a0426U, +/*0070*/ 0x00110427U, +/*0071*/ 0x00090428U, +/*0072*/ 0x10090428U, +/*0073*/ 0x00100429U, +/*0074*/ 0x100e0429U, +/*0075*/ 0x000e042aU, +/*0076*/ 0x100c042aU, +/*0077*/ 0x000a042bU, +/*0078*/ 0x100a042bU, +/*0079*/ 0x0002042cU, +/*007a*/ 0x0020042dU, +/*007b*/ 0x000b042eU, +/*007c*/ 0x100b042eU, +/*007d*/ 0x0020042fU, +/*007e*/ 0x00120430U, +/*007f*/ 0x00200431U, +/*0080*/ 0x00200432U, +/*0081*/ 0xffffffffU, +/*0082*/ 0xffffffffU, +/*0083*/ 0x00010433U, +/*0084*/ 0x08010433U, +/*0085*/ 0x10080433U, +/*0086*/ 0x000c0434U, +/*0087*/ 0x100c0434U, +/*0088*/ 0x000c0435U, +/*0089*/ 0x100c0435U, +/*008a*/ 0x000c0436U, +/*008b*/ 0x100c0436U, +/*008c*/ 0x000c0437U, +/*008d*/ 0x100c0437U, +/*008e*/ 0x000c0438U, +/*008f*/ 0x100c0438U, +/*0090*/ 0x000c0439U, +/*0091*/ 0x100b0439U, +/*0092*/ 0xffffffffU, +/*0093*/ 0xffffffffU, +/*0094*/ 0x000b043aU, +/*0095*/ 0x100b043aU, +/*0096*/ 0x000b043bU, +/*0097*/ 0x100b043bU, +/*0098*/ 0x000b043cU, +/*0099*/ 0x100b043cU, +/*009a*/ 0x000b043dU, +/*009b*/ 0x100b043dU, +/*009c*/ 0x000b043eU, +/*009d*/ 0x100a043eU, +/*009e*/ 0xffffffffU, +/*009f*/ 0x000a043fU, +/*00a0*/ 0x100a043fU, +/*00a1*/ 0x000a0440U, +/*00a2*/ 0x100a0440U, +/*00a3*/ 0x000a0441U, +/*00a4*/ 0x100a0441U, +/*00a5*/ 0x000a0442U, +/*00a6*/ 0x100a0442U, +/*00a7*/ 0xffffffffU, +/*00a8*/ 0x000a0443U, +/*00a9*/ 0x100a0443U, +/*00aa*/ 0x000a0444U, +/*00ab*/ 0x100a0444U, +/*00ac*/ 0x000a0445U, +/*00ad*/ 0x100a0445U, +/*00ae*/ 0x000a0446U, +/*00af*/ 0x100a0446U, +/*00b0*/ 0x000a0447U, +/*00b1*/ 0x100a0447U, +/*00b2*/ 0x000a0448U, +/*00b3*/ 0x100a0448U, +/*00b4*/ 0x000a0449U, +/*00b5*/ 0x100a0449U, +/*00b6*/ 0x000a044aU, +/*00b7*/ 0x100a044aU, +/*00b8*/ 0x000a044bU, +/*00b9*/ 0x100a044bU, +/*00ba*/ 0x000a044cU, +/*00bb*/ 0x1004044cU, +/*00bc*/ 0x1803044cU, +/*00bd*/ 0x000a044dU, +/*00be*/ 0x100a044dU, +/*00bf*/ 0x0001044eU, +/*00c0*/ 0x080a044eU, +/*00c1*/ 0x1804044eU, +/*00c2*/ 0x000b044fU, +/*00c3*/ 0x100a044fU, +/*00c4*/ 0xffffffffU, +/*00c5*/ 0x00080450U, +/*00c6*/ 0x08080450U, +/*00c7*/ 0x10080450U, +/*00c8*/ 0x18080450U, +/*00c9*/ 0x00080451U, +/*00ca*/ 0xffffffffU, +/*00cb*/ 0x08080451U, +/*00cc*/ 0x10010451U, +/*00cd*/ 0x18080451U, +/*00ce*/ 0x00080452U, +/*00cf*/ 0x08020452U, +/*00d0*/ 0x10020452U, +/*00d1*/ 0x18040452U, +/*00d2*/ 0x00040453U, +/*00d3*/ 0xffffffffU, +/*00d4*/ 0x08040453U, +/*00d5*/ 0x100a0453U, +/*00d6*/ 0x00060454U, +/*00d7*/ 0x08080454U, +/*00d8*/ 0xffffffffU, +/*00d9*/ 0x10040454U, +/*00da*/ 0x18040454U, +/*00db*/ 0x00050455U, +/*00dc*/ 0x08040455U, +/*00dd*/ 0x10050455U, +/*00de*/ 0x000a0456U, +/*00df*/ 0x100a0456U, +/*00e0*/ 0x00080457U, +/*00e1*/ 0xffffffffU, +/*00e2*/ 0x08040457U, +/*00e3*/ 0xffffffffU, +/*00e4*/ 0xffffffffU, +/*00e5*/ 0x00050600U, +/*00e6*/ 0x08050600U, +/*00e7*/ 0x10050600U, +/*00e8*/ 0x18050600U, +/*00e9*/ 0x00050601U, +/*00ea*/ 0x08050601U, +/*00eb*/ 0x100b0601U, +/*00ec*/ 0x00010602U, +/*00ed*/ 0x08030602U, +/*00ee*/ 0x00200603U, +/*00ef*/ 0xffffffffU, +/*00f0*/ 0x00030604U, +/*00f1*/ 0x080a0604U, +/*00f2*/ 0xffffffffU, +/*00f3*/ 0xffffffffU, +/*00f4*/ 0x18030604U, +/*00f5*/ 0x00030605U, +/*00f6*/ 0x08010605U, +/*00f7*/ 0x10010605U, +/*00f8*/ 0x18060605U, +/*00f9*/ 0xffffffffU, +/*00fa*/ 0xffffffffU, +/*00fb*/ 0xffffffffU, +/*00fc*/ 0x00020606U, +/*00fd*/ 0x08030606U, +/*00fe*/ 0x10010606U, +/*00ff*/ 0x000f0607U, +/*0100*/ 0x00200608U, +/*0101*/ 0x00200609U, +/*0102*/ 0x000b060aU, +/*0103*/ 0x100b060aU, +/*0104*/ 0x000b060bU, +/*0105*/ 0xffffffffU, +/*0106*/ 0xffffffffU, +/*0107*/ 0x0018060cU, +/*0108*/ 0x0018060dU, +/*0109*/ 0x0018060eU, +/*010a*/ 0x0018060fU, +/*010b*/ 0x1804060fU, +/*010c*/ 0x00050610U, +/*010d*/ 0x08020610U, +/*010e*/ 0x10040610U, +/*010f*/ 0x18040610U, +/*0110*/ 0x00010611U, +/*0111*/ 0x08010611U, +/*0112*/ 0x10010611U, +/*0113*/ 0x18030611U, +/*0114*/ 0x00200612U, +/*0115*/ 0x00200613U, +/*0116*/ 0x00010614U, +/*0117*/ 0x08140614U, +/*0118*/ 0x00140615U, +/*0119*/ 0x00140616U, +/*011a*/ 0x00140617U, +/*011b*/ 0x00140618U, +/*011c*/ 0x00140619U, +/*011d*/ 0x0014061aU, +/*011e*/ 0x0014061bU, +/*011f*/ 0x0018061cU, +/*0120*/ 0x000a061dU, +/*0121*/ 0x1006061dU, +/*0122*/ 0x1806061dU, +/*0123*/ 0x0006061eU, +/*0124*/ 0xffffffffU, +/*0125*/ 0xffffffffU, +/*0126*/ 0x0008061fU, +/*0127*/ 0x080b061fU, +/*0128*/ 0x000b0620U, +/*0129*/ 0x100b0620U, +/*012a*/ 0x000b0621U, +/*012b*/ 0x100b0621U, +/*012c*/ 0x000b0622U, +/*012d*/ 0x10040622U, +/*012e*/ 0x000a0623U, +/*012f*/ 0x10060623U, +/*0130*/ 0x18080623U, +/*0131*/ 0xffffffffU, +/*0132*/ 0x00040624U, +/*0133*/ 0xffffffffU, +/*0134*/ 0xffffffffU, +/*0135*/ 0x00010700U, +/*0136*/ 0x08020700U, +/*0137*/ 0x10050700U, +/*0138*/ 0x18050700U, +/*0139*/ 0x00050701U, +/*013a*/ 0x08050701U, +/*013b*/ 0x100b0701U, +/*013c*/ 0x00050702U, +/*013d*/ 0x08010702U, +/*013e*/ 0x10010702U, +/*013f*/ 0xffffffffU, +/*0140*/ 0x18010702U, +/*0141*/ 0x00010703U, +/*0142*/ 0x08040703U, +/*0143*/ 0x100b0703U, +/*0144*/ 0x000b0704U, +/*0145*/ 0xffffffffU, +/*0146*/ 0x10040704U, +/*0147*/ 0x000b0705U, +/*0148*/ 0x10040705U, +/*0149*/ 0x18010705U, +/*014a*/ 0x00010706U, +/*014b*/ 0x08010706U, +/*014c*/ 0x00200707U, +/*014d*/ 0x00200708U, +/*014e*/ 0x00080709U, +/*014f*/ 0x080a0709U, +/*0150*/ 0x18050709U, +/*0151*/ 0x000a070aU, +/*0152*/ 0x1003070aU, +/*0153*/ 0x1803070aU, +/*0154*/ 0x0001070bU, +/*0155*/ 0x0802070bU, +/*0156*/ 0x1001070bU, +/*0157*/ 0x1801070bU, +/*0158*/ 0x0001070cU, +/*0159*/ 0x0802070cU, +/*015a*/ 0xffffffffU, +/*015b*/ 0xffffffffU, +/*015c*/ 0xffffffffU, +/*015d*/ 0xffffffffU, +/*015e*/ 0xffffffffU, +/*015f*/ 0xffffffffU, +/*0160*/ 0xffffffffU, +/*0161*/ 0xffffffffU, +/*0162*/ 0xffffffffU, +/*0163*/ 0xffffffffU, +/*0164*/ 0xffffffffU, +/*0165*/ 0xffffffffU, +/*0166*/ 0x1001070cU, +/*0167*/ 0x1801070cU, +/*0168*/ 0x000d070dU, +/*0169*/ 0xffffffffU, +/*016a*/ 0xffffffffU, +/*016b*/ 0x0005070eU, +/*016c*/ 0x0001070fU, +/*016d*/ 0x080e070fU, +/*016e*/ 0x000e0710U, +/*016f*/ 0x100e0710U, +/*0170*/ 0x000e0711U, +/*0171*/ 0x100e0711U, +/*0172*/ 0x00040712U, +/*0173*/ 0xffffffffU, +/*0174*/ 0xffffffffU, +/*0175*/ 0xffffffffU, +/*0176*/ 0xffffffffU, +/*0177*/ 0x080b0712U, +/*0178*/ 0x000b0713U, +/*0179*/ 0x100b0713U, +/*017a*/ 0x000b0714U, +/*017b*/ 0xffffffffU, +/*017c*/ 0xffffffffU, +/*017d*/ 0xffffffffU, +/*017e*/ 0xffffffffU, +/*017f*/ 0x000d0715U, +/*0180*/ 0xffffffffU, +/*0181*/ 0xffffffffU, +/*0182*/ 0x10100715U, +/*0183*/ 0x00080716U, +/*0184*/ 0xffffffffU, +/*0185*/ 0x08100716U, +/*0186*/ 0x00100717U, +/*0187*/ 0x10100717U, +/*0188*/ 0x00100718U, +/*0189*/ 0x10100718U, +/*018a*/ 0x00030719U, +/*018b*/ 0x08040719U, +/*018c*/ 0x10010719U, +/*018d*/ 0x18040719U, +/*018e*/ 0xffffffffU, +/*018f*/ 0xffffffffU, +/*0190*/ 0x0001071aU, +/*0191*/ 0x0812071aU, +/*0192*/ 0x000a071bU, +/*0193*/ 0x100c071bU, +/*0194*/ 0x0012071cU, +/*0195*/ 0x0014071dU, +/*0196*/ 0x0012071eU, +/*0197*/ 0x0011071fU, +/*0198*/ 0x00110720U, +/*0199*/ 0x00120721U, +/*019a*/ 0x00120722U, +/*019b*/ 0x00120723U, +/*019c*/ 0x00120724U, +/*019d*/ 0x00120725U, +/*019e*/ 0x00120726U, +/*019f*/ 0x00120727U, +/*01a0*/ 0x00120728U, +/*01a1*/ 0xffffffffU, +/*01a2*/ 0xffffffffU, +/*01a3*/ 0x00190729U, +/*01a4*/ 0x0019072aU, +/*01a5*/ 0x0020072bU, +/*01a6*/ 0x0017072cU, +/*01a7*/ 0x1808072cU, +/*01a8*/ 0x0001072dU, +/*01a9*/ 0x0801072dU, +/*01aa*/ 0x0020072eU, +/*01ab*/ 0x0008072fU, +/*01ac*/ 0xffffffffU, +/*01ad*/ 0x0803072fU, +/*01ae*/ 0x00180730U, +/*01af*/ 0x00180731U, +/*01b0*/ 0xffffffffU, +/*01b1*/ 0xffffffffU, +/*01b2*/ 0xffffffffU, +/*01b3*/ 0xffffffffU, +/*01b4*/ 0xffffffffU, +/*01b5*/ 0xffffffffU, +/*01b6*/ 0xffffffffU, +/*01b7*/ 0xffffffffU, +/*01b8*/ 0xffffffffU, +/*01b9*/ 0xffffffffU, +/*01ba*/ 0xffffffffU, +/*01bb*/ 0xffffffffU, +/*01bc*/ 0xffffffffU, +/*01bd*/ 0xffffffffU, +/*01be*/ 0xffffffffU, +/*01bf*/ 0x00100732U, +/*01c0*/ 0x10010732U, +/*01c1*/ 0x18010732U, +/*01c2*/ 0x00050733U, +/*01c3*/ 0x00200734U, +/*01c4*/ 0x00090735U, +/*01c5*/ 0xffffffffU, +/*01c6*/ 0xffffffffU, +/*01c7*/ 0x00200736U, +/*01c8*/ 0x00040737U, +/*01c9*/ 0x08100737U, +/*01ca*/ 0x18060737U, +/*01cb*/ 0x00100738U, +/*01cc*/ 0xffffffffU, +/*01cd*/ 0xffffffffU, +/*01ce*/ 0xffffffffU, +/*01cf*/ 0xffffffffU, +/*01d0*/ 0xffffffffU, +/*01d1*/ 0xffffffffU, +/*01d2*/ 0xffffffffU, +/*01d3*/ 0xffffffffU, +/*01d4*/ 0x00200739U, +/*01d5*/ 0x000b073aU, +/*01d6*/ 0xffffffffU, +/*01d7*/ 0xffffffffU, +/*01d8*/ 0xffffffffU, +/*01d9*/ 0xffffffffU, +/*01da*/ 0xffffffffU, +/*01db*/ 0xffffffffU, +/*01dc*/ 0xffffffffU, +/*01dd*/ 0xffffffffU, +/*01de*/ 0x00010200U, +/*01df*/ 0x08040200U, +/*01e0*/ 0x10100200U, +/*01e1*/ 0x00010201U, +/*01e2*/ 0x08010201U, +/*01e3*/ 0xffffffffU, +/*01e4*/ 0xffffffffU, +/*01e5*/ 0x10100201U, +/*01e6*/ 0xffffffffU, +/*01e7*/ 0xffffffffU, +/*01e8*/ 0xffffffffU, +/*01e9*/ 0xffffffffU, +/*01ea*/ 0xffffffffU, +/*01eb*/ 0xffffffffU, +/*01ec*/ 0xffffffffU, +/*01ed*/ 0xffffffffU, +/*01ee*/ 0xffffffffU, +/*01ef*/ 0x00200202U, +/*01f0*/ 0x00100203U, +/*01f1*/ 0x00200204U, +/*01f2*/ 0x00100205U, +/*01f3*/ 0x00200206U, +/*01f4*/ 0x00100207U, +/*01f5*/ 0x10100207U, +/*01f6*/ 0x00200208U, +/*01f7*/ 0x00200209U, +/*01f8*/ 0x0020020aU, +/*01f9*/ 0x0020020bU, +/*01fa*/ 0x0010020cU, +/*01fb*/ 0x0020020dU, +/*01fc*/ 0x0020020eU, +/*01fd*/ 0x0020020fU, +/*01fe*/ 0x00200210U, +/*01ff*/ 0x00100211U, +/*0200*/ 0x00200212U, +/*0201*/ 0x00200213U, +/*0202*/ 0x00200214U, +/*0203*/ 0x00200215U, +/*0204*/ 0x00090216U, +/*0205*/ 0x10010216U, +/*0206*/ 0x00200217U, +/*0207*/ 0x00050218U, +/*0208*/ 0x08010218U, +/*0209*/ 0x10080218U, +/*020a*/ 0x18080218U, +/*020b*/ 0x001c0219U, +/*020c*/ 0x001c021aU, +/*020d*/ 0x001c021bU, +/*020e*/ 0x001c021cU, +/*020f*/ 0x001c021dU, +/*0210*/ 0x001c021eU, +/*0211*/ 0x001c021fU, +/*0212*/ 0x001c0220U, +/*0213*/ 0x001c0221U, +/*0214*/ 0x001c0222U, +/*0215*/ 0x001c0223U, +/*0216*/ 0x001c0224U, +/*0217*/ 0x001c0225U, +/*0218*/ 0x001c0226U, +/*0219*/ 0x001c0227U, +/*021a*/ 0x001c0228U, +/*021b*/ 0x00010229U, +/*021c*/ 0x08010229U, +/*021d*/ 0x10010229U, +/*021e*/ 0x18040229U, +/*021f*/ 0x0008022aU, +/*0220*/ 0x0808022aU, +/*0221*/ 0x1008022aU, +/*0222*/ 0x1804022aU, +/*0223*/ 0x0006022bU, +/*0224*/ 0xffffffffU, +/*0225*/ 0x0807022bU, +/*0226*/ 0x1006022bU, +/*0227*/ 0xffffffffU, +/*0228*/ 0x1807022bU, +/*0229*/ 0x0006022cU, +/*022a*/ 0xffffffffU, +/*022b*/ 0x0807022cU, +/*022c*/ 0x1002022cU, +/*022d*/ 0x1801022cU, +/*022e*/ 0xffffffffU, +/*022f*/ 0x000a022dU, +/*0230*/ 0x1010022dU, +/*0231*/ 0x000a022eU, +/*0232*/ 0x1010022eU, +/*0233*/ 0x000a022fU, +/*0234*/ 0x1010022fU, +/*0235*/ 0xffffffffU, +/*0236*/ 0x00100230U, +/*0237*/ 0xffffffffU, +/*0238*/ 0xffffffffU, +/*0239*/ 0x10010230U, +/*023a*/ 0x18010230U, +/*023b*/ 0x00010231U, +/*023c*/ 0x08010231U, +/*023d*/ 0x10010231U, +/*023e*/ 0x18010231U, +/*023f*/ 0x00020232U, +/*0240*/ 0x08020232U, +/*0241*/ 0x10020232U, +/*0242*/ 0x18020232U, +/*0243*/ 0x00020233U, +/*0244*/ 0x08030233U, +/*0245*/ 0x10010233U, +/*0246*/ 0x18010233U, +/*0247*/ 0x00010234U, +/*0248*/ 0x08010234U, +/*0249*/ 0xffffffffU, +/*024a*/ 0x10020234U, +/*024b*/ 0x18010234U, +/*024c*/ 0x00010235U, +/*024d*/ 0xffffffffU, +/*024e*/ 0x08020235U, +/*024f*/ 0x10010235U, +/*0250*/ 0x18010235U, +/*0251*/ 0xffffffffU, +/*0252*/ 0x00020236U, +/*0253*/ 0x08010236U, +/*0254*/ 0x10010236U, +/*0255*/ 0xffffffffU, +/*0256*/ 0x18020236U, +/*0257*/ 0x00070237U, +/*0258*/ 0x08010237U, +/*0259*/ 0x10010237U, +/*025a*/ 0x18010237U, +/*025b*/ 0x00010238U, +/*025c*/ 0x08010238U, +/*025d*/ 0x10010238U, +/*025e*/ 0xffffffffU, +/*025f*/ 0x18010238U, +/*0260*/ 0x00040239U, +/*0261*/ 0x08040239U, +/*0262*/ 0x10040239U, +/*0263*/ 0x18010239U, +/*0264*/ 0x0002023aU, +/*0265*/ 0x0806023aU, +/*0266*/ 0x1006023aU, +/*0267*/ 0xffffffffU, +/*0268*/ 0xffffffffU, +/*0269*/ 0xffffffffU, +/*026a*/ 0x1802023aU, +/*026b*/ 0x0010023bU, +/*026c*/ 0x1001023bU, +/*026d*/ 0x1801023bU, +/*026e*/ 0xffffffffU, +/*026f*/ 0x0004023cU, +/*0270*/ 0x0801023cU, +/*0271*/ 0x1004023cU, +/*0272*/ 0x1802023cU, +/*0273*/ 0x0008023dU, +/*0274*/ 0xffffffffU, +/*0275*/ 0xffffffffU, +/*0276*/ 0xffffffffU, +/*0277*/ 0x080a023dU, +/*0278*/ 0x0020023eU, +/*0279*/ 0x0020023fU, +/*027a*/ 0x00050240U, +/*027b*/ 0x08010240U, +/*027c*/ 0x10050240U, +/*027d*/ 0x18080240U, +/*027e*/ 0x00010241U, +/*027f*/ 0x08080241U, +/*0280*/ 0x10010241U, +/*0281*/ 0x18080241U, +/*0282*/ 0x00010242U, +/*0283*/ 0x08040242U, +/*0284*/ 0x10040242U, +/*0285*/ 0x18040242U, +/*0286*/ 0x00040243U, +/*0287*/ 0x08040243U, +/*0288*/ 0x10040243U, +/*0289*/ 0x18040243U, +/*028a*/ 0x00040244U, +/*028b*/ 0x08040244U, +/*028c*/ 0x10040244U, +/*028d*/ 0x18010244U, +/*028e*/ 0x00040245U, +/*028f*/ 0x08040245U, +/*0290*/ 0x10040245U, +/*0291*/ 0x18040245U, +/*0292*/ 0x00040246U, +/*0293*/ 0x08040246U, +/*0294*/ 0x10060246U, +/*0295*/ 0x18060246U, +/*0296*/ 0x00060247U, +/*0297*/ 0x08060247U, +/*0298*/ 0x10060247U, +/*0299*/ 0x18060247U, +/*029a*/ 0xffffffffU, +/*029b*/ 0x00010248U, +/*029c*/ 0x08010248U, +/*029d*/ 0x10020248U, +/*029e*/ 0xffffffffU, +/*029f*/ 0xffffffffU, +/*02a0*/ 0xffffffffU, +/*02a1*/ 0xffffffffU, +/*02a2*/ 0xffffffffU, +/*02a3*/ 0xffffffffU, +/*02a4*/ 0xffffffffU, +/*02a5*/ 0xffffffffU, +/*02a6*/ 0x18040248U, +/*02a7*/ 0x00040249U, +/*02a8*/ 0x08010249U, +/*02a9*/ 0x10010249U, +/*02aa*/ 0xffffffffU, +/*02ab*/ 0x18010249U, +/*02ac*/ 0x0001024aU, +/*02ad*/ 0xffffffffU, +/*02ae*/ 0x0801024aU, +/*02af*/ 0x1001024aU, +/*02b0*/ 0x1801024aU, +/*02b1*/ 0x0004024bU, +/*02b2*/ 0x0804024bU, +/*02b3*/ 0x100a024bU, +/*02b4*/ 0x0020024cU, +/*02b5*/ 0x0004024dU, +/*02b6*/ 0x0808024dU, +/*02b7*/ 0xffffffffU, +/*02b8*/ 0xffffffffU, +/*02b9*/ 0xffffffffU, +/*02ba*/ 0xffffffffU, +/*02bb*/ 0xffffffffU, +/*02bc*/ 0xffffffffU, +/*02bd*/ 0x1002024dU, +/*02be*/ 0x1802024dU, +/*02bf*/ 0x0020024eU, +/*02c0*/ 0x0002024fU, +/*02c1*/ 0x0810024fU, +/*02c2*/ 0x00100250U, +/*02c3*/ 0x10040250U, +/*02c4*/ 0x18040250U, +/*02c5*/ 0x00050251U, +/*02c6*/ 0x08050251U, +/*02c7*/ 0xffffffffU, +/*02c8*/ 0xffffffffU, +/*02c9*/ 0xffffffffU, +/*02ca*/ 0xffffffffU, +/*02cb*/ 0x10010251U, +/*02cc*/ 0x18010251U, +/*02cd*/ 0x00070252U, +/*02ce*/ 0x08070252U, +/*02cf*/ 0x10070252U, +/*02d0*/ 0x18070252U, +/*02d1*/ 0x00070253U, +/*02d2*/ 0x08070253U, +/*02d3*/ 0x10070253U, +/*02d4*/ 0x18070253U, +/*02d5*/ 0x00070254U, +/*02d6*/ 0x08070254U, +/*02d7*/ 0x10070254U, +/*02d8*/ 0xffffffffU, +/*02d9*/ 0xffffffffU, +/*02da*/ 0xffffffffU, +/*02db*/ 0xffffffffU, +/*02dc*/ 0xffffffffU, +/*02dd*/ 0xffffffffU, +/*02de*/ 0x18030254U, +/*02df*/ 0x00010255U, +/*02e0*/ 0x08020255U, +/*02e1*/ 0x10010255U, +/*02e2*/ 0x18040255U, +/*02e3*/ 0x00020256U, +/*02e4*/ 0x08010256U, +/*02e5*/ 0x10010256U, +/*02e6*/ 0xffffffffU, +/*02e7*/ 0x18010256U, +/*02e8*/ 0x00040257U, +/*02e9*/ 0x08080257U, +/*02ea*/ 0x100a0257U, +/*02eb*/ 0x000a0258U, +/*02ec*/ 0x100a0258U, +/*02ed*/ 0x000a0259U, +/*02ee*/ 0x100a0259U, +/*02ef*/ 0x000a025aU, +/*02f0*/ 0x0020025bU, +/*02f1*/ 0x0020025cU, +/*02f2*/ 0x0001025dU, +/*02f3*/ 0xffffffffU, +/*02f4*/ 0xffffffffU, +/*02f5*/ 0xffffffffU, +/*02f6*/ 0x0802025dU, +/*02f7*/ 0x1002025dU, +/*02f8*/ 0x0010025eU, +/*02f9*/ 0x1005025eU, +/*02fa*/ 0x1806025eU, +/*02fb*/ 0x0005025fU, +/*02fc*/ 0x0805025fU, +/*02fd*/ 0x100e025fU, +/*02fe*/ 0x00050260U, +/*02ff*/ 0x080e0260U, +/*0300*/ 0x18050260U, +/*0301*/ 0x000e0261U, +/*0302*/ 0x10050261U, +/*0303*/ 0x18010261U, +/*0304*/ 0x00050262U, +/*0305*/ 0x08050262U, +/*0306*/ 0x100a0262U, +/*0307*/ 0x000a0263U, +/*0308*/ 0x10050263U, +/*0309*/ 0x18050263U, +/*030a*/ 0x000a0264U, +/*030b*/ 0x100a0264U, +/*030c*/ 0x00050265U, +/*030d*/ 0x08050265U, +/*030e*/ 0x100a0265U, +/*030f*/ 0x000a0266U, +/*0310*/ 0xffffffffU, +/*0311*/ 0xffffffffU, +/*0312*/ 0xffffffffU, +/*0313*/ 0xffffffffU, +/*0314*/ 0xffffffffU, +/*0315*/ 0xffffffffU, +/*0316*/ 0x10070266U, +/*0317*/ 0x18070266U, +/*0318*/ 0x00040267U, +/*0319*/ 0x08040267U, +/*031a*/ 0xffffffffU, +/*031b*/ 0xffffffffU, +/*031c*/ 0xffffffffU, +/*031d*/ 0x10040267U, +/*031e*/ 0x18080267U, +/*031f*/ 0x00080268U, +/*0320*/ 0x08040268U, +/*0321*/ 0xffffffffU, +/*0322*/ 0xffffffffU, +/*0323*/ 0xffffffffU, +/*0324*/ 0x10040268U, +/*0325*/ 0xffffffffU, +/*0326*/ 0xffffffffU, +/*0327*/ 0xffffffffU, +/*0328*/ 0x18040268U, +/*0329*/ 0xffffffffU, +/*032a*/ 0xffffffffU, +/*032b*/ 0xffffffffU, +/*032c*/ 0x00040269U, +/*032d*/ 0x08050269U, +/*032e*/ 0x10070269U, +/*032f*/ 0x18080269U, +/*0330*/ 0x0010026aU, +/*0331*/ 0x1008026aU, +/*0332*/ 0x0010026bU, +/*0333*/ 0x1008026bU, +/*0334*/ 0x0010026cU, +/*0335*/ 0x1008026cU, +/*0336*/ 0x1808026cU, +/*0337*/ 0x0001026dU, +/*0338*/ 0x0801026dU, +/*0339*/ 0x1006026dU, +/*033a*/ 0x1806026dU, +/*033b*/ 0x0006026eU, +/*033c*/ 0xffffffffU, +/*033d*/ 0x0801026eU, +/*033e*/ 0x1003026eU, +/*033f*/ 0xffffffffU, +/*0340*/ 0xffffffffU, +/*0341*/ 0xffffffffU, +/*0342*/ 0x000a026fU, +/*0343*/ 0x100a026fU, +/*0344*/ 0x00040270U, +/*0345*/ 0x08010270U, +/*0346*/ 0x10040270U, +/*0347*/ 0xffffffffU, +/*0348*/ 0xffffffffU, +/*0349*/ 0xffffffffU, +/*034a*/ 0xffffffffU, +/*034b*/ 0xffffffffU, +/*034c*/ 0xffffffffU, +/*034d*/ 0x18070270U, +/*034e*/ 0x00070271U, +/*034f*/ 0x08050271U, +/*0350*/ 0x10050271U, +/*0351*/ 0xffffffffU, +/*0352*/ 0xffffffffU, +/*0353*/ 0xffffffffU, +/*0354*/ 0x18040271U, +/*0355*/ 0x00010272U, +/*0356*/ 0x08010272U, +/*0357*/ 0x10020272U, +/*0358*/ 0x18080272U, +/*0359*/ 0x00200273U, +/*035a*/ 0x00200274U, +/*035b*/ 0x00100275U, +/*035c*/ 0xffffffffU, +/*035d*/ 0xffffffffU, +/*035e*/ 0xffffffffU, +/*035f*/ 0x10020275U, +/*0360*/ 0x18010275U, +/*0361*/ 0xffffffffU, +/*0362*/ 0x00020276U, +/*0363*/ 0x08080276U, +/*0364*/ 0x10080276U, +/*0365*/ 0x18080276U, +/*0366*/ 0x00080277U, +/*0367*/ 0x08080277U, +/*0368*/ 0x10080277U, +/*0369*/ 0xffffffffU, +/*036a*/ 0x18080277U, +/*036b*/ 0x00080278U, +/*036c*/ 0x08080278U, +/*036d*/ 0x10080278U, +/*036e*/ 0x18080278U, +/*036f*/ 0x00080279U, +/*0370*/ 0xffffffffU, +/*0371*/ 0x08080279U, +/*0372*/ 0x10080279U, +/*0373*/ 0x18080279U, +/*0374*/ 0x0008027aU, +/*0375*/ 0x0808027aU, +/*0376*/ 0x1008027aU, +/*0377*/ 0xffffffffU, +/*0378*/ 0x1808027aU, +/*0379*/ 0x0008027bU, +/*037a*/ 0x0808027bU, +/*037b*/ 0x1008027bU, +/*037c*/ 0x1808027bU, +/*037d*/ 0x0008027cU, +/*037e*/ 0x0808027cU, +/*037f*/ 0xffffffffU, +/*0380*/ 0x1008027cU, +/*0381*/ 0x1808027cU, +/*0382*/ 0x0008027dU, +/*0383*/ 0x0808027dU, +/*0384*/ 0x1008027dU, +/*0385*/ 0x1808027dU, +/*0386*/ 0xffffffffU, +/*0387*/ 0x0008027eU, +/*0388*/ 0x0808027eU, +/*0389*/ 0x1008027eU, +/*038a*/ 0x1808027eU, +/*038b*/ 0x0008027fU, +/*038c*/ 0x0808027fU, +/*038d*/ 0xffffffffU, +/*038e*/ 0x1008027fU, +/*038f*/ 0x1808027fU, +/*0390*/ 0x00080280U, +/*0391*/ 0x08080280U, +/*0392*/ 0x10080280U, +/*0393*/ 0x18080280U, +/*0394*/ 0x00080281U, +/*0395*/ 0xffffffffU, +/*0396*/ 0x08080281U, +/*0397*/ 0x10080281U, +/*0398*/ 0x18080281U, +/*0399*/ 0x00080282U, +/*039a*/ 0x08080282U, +/*039b*/ 0x10080282U, +/*039c*/ 0xffffffffU, +/*039d*/ 0x18080282U, +/*039e*/ 0x00080283U, +/*039f*/ 0x08080283U, +/*03a0*/ 0x10080283U, +/*03a1*/ 0x18080283U, +/*03a2*/ 0x00080284U, +/*03a3*/ 0xffffffffU, +/*03a4*/ 0x08080284U, +/*03a5*/ 0x10080284U, +/*03a6*/ 0x18080284U, +/*03a7*/ 0x00080285U, +/*03a8*/ 0x08080285U, +/*03a9*/ 0x10080285U, +/*03aa*/ 0x18080285U, +/*03ab*/ 0xffffffffU, +/*03ac*/ 0x00080286U, +/*03ad*/ 0x08080286U, +/*03ae*/ 0x10080286U, +/*03af*/ 0x18080286U, +/*03b0*/ 0x00080287U, +/*03b1*/ 0x08080287U, +/*03b2*/ 0xffffffffU, +/*03b3*/ 0x10080287U, +/*03b4*/ 0x18080287U, +/*03b5*/ 0x00080288U, +/*03b6*/ 0x08080288U, +/*03b7*/ 0x10080288U, +/*03b8*/ 0x18080288U, +/*03b9*/ 0xffffffffU, +/*03ba*/ 0x00080289U, +/*03bb*/ 0x08020289U, +/*03bc*/ 0x10030289U, +/*03bd*/ 0x000a028aU, +/*03be*/ 0x100a028aU, +/*03bf*/ 0x000a028bU, +/*03c0*/ 0x1005028bU, +/*03c1*/ 0x1804028bU, +/*03c2*/ 0x0008028cU, +/*03c3*/ 0x0808028cU, +/*03c4*/ 0x1006028cU, +/*03c5*/ 0x1806028cU, +/*03c6*/ 0x0011028dU, +/*03c7*/ 0x1808028dU, +/*03c8*/ 0x0004028eU, +/*03c9*/ 0x0806028eU, +/*03ca*/ 0xffffffffU, +/*03cb*/ 0x1006028eU, +/*03cc*/ 0x1808028eU, +/*03cd*/ 0xffffffffU, +/*03ce*/ 0x0004028fU, +/*03cf*/ 0x0808028fU, +/*03d0*/ 0x1008028fU, +/*03d1*/ 0x1806028fU, +/*03d2*/ 0x00060290U, +/*03d3*/ 0x08110290U, +/*03d4*/ 0x00080291U, +/*03d5*/ 0x08040291U, +/*03d6*/ 0x10060291U, +/*03d7*/ 0xffffffffU, +/*03d8*/ 0x18060291U, +/*03d9*/ 0x00080292U, +/*03da*/ 0xffffffffU, +/*03db*/ 0x08040292U, +/*03dc*/ 0x10080292U, +/*03dd*/ 0x18080292U, +/*03de*/ 0x00060293U, +/*03df*/ 0x08060293U, +/*03e0*/ 0x00110294U, +/*03e1*/ 0x18080294U, +/*03e2*/ 0x00040295U, +/*03e3*/ 0x08060295U, +/*03e4*/ 0xffffffffU, +/*03e5*/ 0x10060295U, +/*03e6*/ 0x18080295U, +/*03e7*/ 0xffffffffU, +/*03e8*/ 0x00040296U, +/*03e9*/ 0x08040296U, +/*03ea*/ 0x10040296U, +/*03eb*/ 0x18040296U, +/*03ec*/ 0x00040297U, +/*03ed*/ 0x08040297U, +/*03ee*/ 0x10040297U, +/*03ef*/ 0x18040297U, +/*03f0*/ 0x00040298U, +/*03f1*/ 0x08040298U, +/*03f2*/ 0x10040298U, +/*03f3*/ 0x18040298U, +/*03f4*/ 0x00040299U, +/*03f5*/ 0x08040299U, +/*03f6*/ 0x10040299U, +/*03f7*/ 0x18040299U, +/*03f8*/ 0x0004029aU, +/*03f9*/ 0x0804029aU, +/*03fa*/ 0x1004029aU, +/*03fb*/ 0x1804029aU, +/*03fc*/ 0x0011029bU, +/*03fd*/ 0x0010029cU, +/*03fe*/ 0x0011029dU, +/*03ff*/ 0x0020029eU, +/*0400*/ 0x0020029fU, +/*0401*/ 0x002002a0U, +/*0402*/ 0x002002a1U, +/*0403*/ 0x002002a2U, +/*0404*/ 0x002002a3U, +/*0405*/ 0x002002a4U, +/*0406*/ 0x002002a5U, +/*0407*/ 0x002002a6U, +/*0408*/ 0x000202a7U, +/*0409*/ 0x080502a7U, +/*040a*/ 0x100502a7U, +/*040b*/ 0xffffffffU, +/*040c*/ 0xffffffffU, +/*040d*/ 0xffffffffU, +/*040e*/ 0xffffffffU, +/*040f*/ 0xffffffffU, +/*0410*/ 0xffffffffU, +/*0411*/ 0xffffffffU, +/*0412*/ 0xffffffffU, +/*0413*/ 0xffffffffU, +/*0414*/ 0xffffffffU, +/*0415*/ 0xffffffffU, +/*0416*/ 0xffffffffU, +/*0417*/ 0xffffffffU, +/*0418*/ 0xffffffffU, +/*0419*/ 0xffffffffU, +/*041a*/ 0xffffffffU, +/*041b*/ 0xffffffffU, +/*041c*/ 0xffffffffU, +/*041d*/ 0xffffffffU, +/*041e*/ 0xffffffffU, +/*041f*/ 0xffffffffU, +/*0420*/ 0xffffffffU, +/*0421*/ 0xffffffffU, +/*0422*/ 0xffffffffU, +/*0423*/ 0xffffffffU, +/*0424*/ 0xffffffffU, +/*0425*/ 0xffffffffU, +/*0426*/ 0xffffffffU, +/*0427*/ 0x180102a7U, +/*0428*/ 0x000402a8U, +/*0429*/ 0x081002a8U, +/*042a*/ 0x002002a9U, +/*042b*/ 0x001002aaU, +/*042c*/ 0x002002abU, +/*042d*/ 0x001002acU, +/*042e*/ 0x002002adU, +/*042f*/ 0x000702aeU, +/*0430*/ 0x080102aeU, +/*0431*/ 0x100202aeU, +/*0432*/ 0x180602aeU, +/*0433*/ 0x000102afU, +/*0434*/ 0x080102afU, +/*0435*/ 0x002002b0U, +/*0436*/ 0x000202b1U, +/*0437*/ 0x002002b2U, +/*0438*/ 0x002002b3U, +/*0439*/ 0xffffffffU, +/*043a*/ 0xffffffffU, +/*043b*/ 0xffffffffU, +/*043c*/ 0xffffffffU, +/*043d*/ 0xffffffffU, +/*043e*/ 0xffffffffU, +/*043f*/ 0xffffffffU, +/*0440*/ 0xffffffffU, +/*0441*/ 0xffffffffU, +/*0442*/ 0xffffffffU, +/*0443*/ 0xffffffffU, +/*0444*/ 0xffffffffU, +/*0445*/ 0xffffffffU, +/*0446*/ 0xffffffffU, +/*0447*/ 0xffffffffU, +/*0448*/ 0xffffffffU, +/*0449*/ 0xffffffffU, +/*044a*/ 0xffffffffU, +/*044b*/ 0xffffffffU, +/*044c*/ 0xffffffffU, +/*044d*/ 0xffffffffU, +/*044e*/ 0xffffffffU, +/*044f*/ 0xffffffffU, +/*0450*/ 0xffffffffU, +/*0451*/ 0xffffffffU, +/*0452*/ 0xffffffffU, +/*0453*/ 0xffffffffU, +/*0454*/ 0xffffffffU, +/*0455*/ 0xffffffffU, +/*0456*/ 0xffffffffU, +/*0457*/ 0xffffffffU, +/*0458*/ 0xffffffffU, +/*0459*/ 0xffffffffU, +/*045a*/ 0xffffffffU, +/*045b*/ 0xffffffffU, +/*045c*/ 0xffffffffU, +/*045d*/ 0xffffffffU, +/*045e*/ 0xffffffffU, +/*045f*/ 0x000402b4U, +/*0460*/ 0xffffffffU, +/*0461*/ 0xffffffffU, +/*0462*/ 0xffffffffU, +/*0463*/ 0xffffffffU, +/*0464*/ 0xffffffffU, +/*0465*/ 0xffffffffU, +/*0466*/ 0xffffffffU, +/*0467*/ 0xffffffffU, +/*0468*/ 0xffffffffU, +/*0469*/ 0xffffffffU, +/*046a*/ 0xffffffffU, +/*046b*/ 0xffffffffU, +/*046c*/ 0xffffffffU, +/*046d*/ 0xffffffffU, +/*046e*/ 0xffffffffU, +/*046f*/ 0xffffffffU, +/*0470*/ 0xffffffffU, +/*0471*/ 0xffffffffU, +/*0472*/ 0xffffffffU, +/*0473*/ 0xffffffffU, +/*0474*/ 0xffffffffU, +/*0475*/ 0xffffffffU, +/*0476*/ 0xffffffffU, +/*0477*/ 0xffffffffU, +/*0478*/ 0xffffffffU, +/*0479*/ 0xffffffffU, +/*047a*/ 0xffffffffU, +/*047b*/ 0xffffffffU, +/*047c*/ 0xffffffffU, +/*047d*/ 0xffffffffU, +/*047e*/ 0xffffffffU, +/*047f*/ 0xffffffffU, +/*0480*/ 0xffffffffU, +/*0481*/ 0xffffffffU, +/*0482*/ 0xffffffffU, +/*0483*/ 0xffffffffU, +/*0484*/ 0xffffffffU, +/*0485*/ 0xffffffffU, +/*0486*/ 0xffffffffU, +/*0487*/ 0xffffffffU, +/*0488*/ 0xffffffffU, +/*0489*/ 0xffffffffU, +/*048a*/ 0xffffffffU, +/*048b*/ 0xffffffffU, +/*048c*/ 0xffffffffU, +/*048d*/ 0xffffffffU, +/*048e*/ 0xffffffffU, +/*048f*/ 0xffffffffU, +/*0490*/ 0xffffffffU, +/*0491*/ 0xffffffffU, +/*0492*/ 0xffffffffU, +/*0493*/ 0xffffffffU, +/*0494*/ 0xffffffffU, + }, + { +/*0000*/ 0x00200800U, +/*0001*/ 0x00040801U, +/*0002*/ 0x080b0801U, +/*0003*/ 0xffffffffU, +/*0004*/ 0xffffffffU, +/*0005*/ 0x18010801U, +/*0006*/ 0x00050802U, +/*0007*/ 0x08050802U, +/*0008*/ 0x10050802U, +/*0009*/ 0x18050802U, +/*000a*/ 0x00050803U, +/*000b*/ 0x08050803U, +/*000c*/ 0x10050803U, +/*000d*/ 0x18050803U, +/*000e*/ 0x00050804U, +/*000f*/ 0x08040804U, +/*0010*/ 0x10030804U, +/*0011*/ 0x00180805U, +/*0012*/ 0x18030805U, +/*0013*/ 0x00180806U, +/*0014*/ 0x18020806U, +/*0015*/ 0x00010807U, +/*0016*/ 0x08020807U, +/*0017*/ 0x10010807U, +/*0018*/ 0x18010807U, +/*0019*/ 0x00020808U, +/*001a*/ 0x08040808U, +/*001b*/ 0x10040808U, +/*001c*/ 0x18040808U, +/*001d*/ 0x000a0809U, +/*001e*/ 0x10040809U, +/*001f*/ 0xffffffffU, +/*0020*/ 0xffffffffU, +/*0021*/ 0x18070809U, +/*0022*/ 0xffffffffU, +/*0023*/ 0xffffffffU, +/*0024*/ 0xffffffffU, +/*0025*/ 0xffffffffU, +/*0026*/ 0xffffffffU, +/*0027*/ 0xffffffffU, +/*0028*/ 0x000a080aU, +/*0029*/ 0x1005080aU, +/*002a*/ 0x1801080aU, +/*002b*/ 0x0001080bU, +/*002c*/ 0x0802080bU, +/*002d*/ 0x1009080bU, +/*002e*/ 0x0009080cU, +/*002f*/ 0x1002080cU, +/*0030*/ 0x0020080dU, +/*0031*/ 0xffffffffU, +/*0032*/ 0x0001080eU, +/*0033*/ 0xffffffffU, +/*0034*/ 0xffffffffU, +/*0035*/ 0xffffffffU, +/*0036*/ 0xffffffffU, +/*0037*/ 0x0020080fU, +/*0038*/ 0x00200810U, +/*0039*/ 0x00200811U, +/*003a*/ 0x00200812U, +/*003b*/ 0x00030813U, +/*003c*/ 0x08010813U, +/*003d*/ 0x10030813U, +/*003e*/ 0x18030813U, +/*003f*/ 0x00040814U, +/*0040*/ 0x08040814U, +/*0041*/ 0x10040814U, +/*0042*/ 0x18040814U, +/*0043*/ 0x00010815U, +/*0044*/ 0x08010815U, +/*0045*/ 0x10060815U, +/*0046*/ 0x18040815U, +/*0047*/ 0xffffffffU, +/*0048*/ 0x00060816U, +/*0049*/ 0x08040816U, +/*004a*/ 0x10060816U, +/*004b*/ 0x18040816U, +/*004c*/ 0x00020817U, +/*004d*/ 0x08050817U, +/*004e*/ 0x10080817U, +/*004f*/ 0x00200818U, +/*0050*/ 0x00060819U, +/*0051*/ 0x08030819U, +/*0052*/ 0x100b0819U, +/*0053*/ 0x0004081aU, +/*0054*/ 0x0804081aU, +/*0055*/ 0x1004081aU, +/*0056*/ 0xffffffffU, +/*0057*/ 0x1801081aU, +/*0058*/ 0x0009081bU, +/*0059*/ 0x0020081cU, +/*005a*/ 0x0020081dU, +/*005b*/ 0x0020081eU, +/*005c*/ 0x0020081fU, +/*005d*/ 0x00100820U, +/*005e*/ 0xffffffffU, +/*005f*/ 0x10010820U, +/*0060*/ 0x18060820U, +/*0061*/ 0x00080821U, +/*0062*/ 0x00200822U, +/*0063*/ 0xffffffffU, +/*0064*/ 0x000a0823U, +/*0065*/ 0x10060823U, +/*0066*/ 0x18070823U, +/*0067*/ 0x00080824U, +/*0068*/ 0x08080824U, +/*0069*/ 0x100a0824U, +/*006a*/ 0x00070825U, +/*006b*/ 0x08080825U, +/*006c*/ 0x10080825U, +/*006d*/ 0x18030825U, +/*006e*/ 0x000a0826U, +/*006f*/ 0x100a0826U, +/*0070*/ 0x00110827U, +/*0071*/ 0x00090828U, +/*0072*/ 0x10090828U, +/*0073*/ 0x00100829U, +/*0074*/ 0x100e0829U, +/*0075*/ 0x000e082aU, +/*0076*/ 0x100c082aU, +/*0077*/ 0x000a082bU, +/*0078*/ 0x100a082bU, +/*0079*/ 0x0002082cU, +/*007a*/ 0x0020082dU, +/*007b*/ 0x000b082eU, +/*007c*/ 0x100b082eU, +/*007d*/ 0x0020082fU, +/*007e*/ 0x00120830U, +/*007f*/ 0x00200831U, +/*0080*/ 0x00200832U, +/*0081*/ 0xffffffffU, +/*0082*/ 0xffffffffU, +/*0083*/ 0x00010833U, +/*0084*/ 0x08010833U, +/*0085*/ 0x10080833U, +/*0086*/ 0x000c0834U, +/*0087*/ 0x100c0834U, +/*0088*/ 0x000c0835U, +/*0089*/ 0x100c0835U, +/*008a*/ 0x000c0836U, +/*008b*/ 0x100c0836U, +/*008c*/ 0x000c0837U, +/*008d*/ 0x100c0837U, +/*008e*/ 0x000c0838U, +/*008f*/ 0x100c0838U, +/*0090*/ 0x000c0839U, +/*0091*/ 0x100b0839U, +/*0092*/ 0xffffffffU, +/*0093*/ 0xffffffffU, +/*0094*/ 0x000b083aU, +/*0095*/ 0x100b083aU, +/*0096*/ 0x000b083bU, +/*0097*/ 0x100b083bU, +/*0098*/ 0x000b083cU, +/*0099*/ 0x100b083cU, +/*009a*/ 0x000b083dU, +/*009b*/ 0x100b083dU, +/*009c*/ 0x000b083eU, +/*009d*/ 0x100a083eU, +/*009e*/ 0xffffffffU, +/*009f*/ 0x000a083fU, +/*00a0*/ 0x100a083fU, +/*00a1*/ 0x000a0840U, +/*00a2*/ 0x100a0840U, +/*00a3*/ 0x000a0841U, +/*00a4*/ 0x100a0841U, +/*00a5*/ 0x000a0842U, +/*00a6*/ 0x100a0842U, +/*00a7*/ 0x000a0843U, +/*00a8*/ 0x100a0843U, +/*00a9*/ 0x000a0844U, +/*00aa*/ 0x100a0844U, +/*00ab*/ 0x000a0845U, +/*00ac*/ 0x100a0845U, +/*00ad*/ 0x000a0846U, +/*00ae*/ 0x100a0846U, +/*00af*/ 0x000a0847U, +/*00b0*/ 0x100a0847U, +/*00b1*/ 0x000a0848U, +/*00b2*/ 0x100a0848U, +/*00b3*/ 0x000a0849U, +/*00b4*/ 0x100a0849U, +/*00b5*/ 0x000a084aU, +/*00b6*/ 0x100a084aU, +/*00b7*/ 0x000a084bU, +/*00b8*/ 0x100a084bU, +/*00b9*/ 0x000a084cU, +/*00ba*/ 0x100a084cU, +/*00bb*/ 0x0004084dU, +/*00bc*/ 0x0803084dU, +/*00bd*/ 0x100a084dU, +/*00be*/ 0x000a084eU, +/*00bf*/ 0x1001084eU, +/*00c0*/ 0x000a084fU, +/*00c1*/ 0x1004084fU, +/*00c2*/ 0x000b0850U, +/*00c3*/ 0x100a0850U, +/*00c4*/ 0xffffffffU, +/*00c5*/ 0x00080851U, +/*00c6*/ 0x08080851U, +/*00c7*/ 0x10080851U, +/*00c8*/ 0x18080851U, +/*00c9*/ 0x00080852U, +/*00ca*/ 0xffffffffU, +/*00cb*/ 0x08080852U, +/*00cc*/ 0x10010852U, +/*00cd*/ 0x18080852U, +/*00ce*/ 0x00080853U, +/*00cf*/ 0x08020853U, +/*00d0*/ 0x10020853U, +/*00d1*/ 0x18040853U, +/*00d2*/ 0x00040854U, +/*00d3*/ 0xffffffffU, +/*00d4*/ 0x08040854U, +/*00d5*/ 0x100a0854U, +/*00d6*/ 0x00060855U, +/*00d7*/ 0x08080855U, +/*00d8*/ 0xffffffffU, +/*00d9*/ 0x10040855U, +/*00da*/ 0x18040855U, +/*00db*/ 0x00050856U, +/*00dc*/ 0x08040856U, +/*00dd*/ 0x10050856U, +/*00de*/ 0x000a0857U, +/*00df*/ 0x100a0857U, +/*00e0*/ 0x00080858U, +/*00e1*/ 0xffffffffU, +/*00e2*/ 0x08040858U, +/*00e3*/ 0xffffffffU, +/*00e4*/ 0xffffffffU, +/*00e5*/ 0x00050a00U, +/*00e6*/ 0x08050a00U, +/*00e7*/ 0x10050a00U, +/*00e8*/ 0x18050a00U, +/*00e9*/ 0x00050a01U, +/*00ea*/ 0x08050a01U, +/*00eb*/ 0x100b0a01U, +/*00ec*/ 0x00010a02U, +/*00ed*/ 0x08030a02U, +/*00ee*/ 0x00200a03U, +/*00ef*/ 0xffffffffU, +/*00f0*/ 0x00030a04U, +/*00f1*/ 0x080a0a04U, +/*00f2*/ 0xffffffffU, +/*00f3*/ 0xffffffffU, +/*00f4*/ 0x18030a04U, +/*00f5*/ 0x00030a05U, +/*00f6*/ 0x08010a05U, +/*00f7*/ 0x10010a05U, +/*00f8*/ 0x18060a05U, +/*00f9*/ 0xffffffffU, +/*00fa*/ 0xffffffffU, +/*00fb*/ 0xffffffffU, +/*00fc*/ 0x00020a06U, +/*00fd*/ 0x08030a06U, +/*00fe*/ 0x10010a06U, +/*00ff*/ 0x000f0a07U, +/*0100*/ 0x00200a08U, +/*0101*/ 0x00200a09U, +/*0102*/ 0x000b0a0aU, +/*0103*/ 0x100b0a0aU, +/*0104*/ 0x000b0a0bU, +/*0105*/ 0xffffffffU, +/*0106*/ 0xffffffffU, +/*0107*/ 0x00180a0cU, +/*0108*/ 0x00180a0dU, +/*0109*/ 0x00180a0eU, +/*010a*/ 0x00180a0fU, +/*010b*/ 0x18040a0fU, +/*010c*/ 0x00020a10U, +/*010d*/ 0x08020a10U, +/*010e*/ 0x10040a10U, +/*010f*/ 0x18040a10U, +/*0110*/ 0x00010a11U, +/*0111*/ 0x08010a11U, +/*0112*/ 0x10010a11U, +/*0113*/ 0x18030a11U, +/*0114*/ 0x00200a12U, +/*0115*/ 0x00200a13U, +/*0116*/ 0xffffffffU, +/*0117*/ 0x00140a14U, +/*0118*/ 0x00140a15U, +/*0119*/ 0x00140a16U, +/*011a*/ 0x00140a17U, +/*011b*/ 0x00140a18U, +/*011c*/ 0x00140a19U, +/*011d*/ 0x00140a1aU, +/*011e*/ 0x00140a1bU, +/*011f*/ 0x001e0a1cU, +/*0120*/ 0x000a0a1dU, +/*0121*/ 0x10060a1dU, +/*0122*/ 0x18060a1dU, +/*0123*/ 0x00060a1eU, +/*0124*/ 0xffffffffU, +/*0125*/ 0x08060a1eU, +/*0126*/ 0x00080a1fU, +/*0127*/ 0x080b0a1fU, +/*0128*/ 0x000b0a20U, +/*0129*/ 0x100b0a20U, +/*012a*/ 0x000b0a21U, +/*012b*/ 0x100b0a21U, +/*012c*/ 0x000b0a22U, +/*012d*/ 0x10040a22U, +/*012e*/ 0x000a0a23U, +/*012f*/ 0x10060a23U, +/*0130*/ 0x18080a23U, +/*0131*/ 0xffffffffU, +/*0132*/ 0x00040a24U, +/*0133*/ 0xffffffffU, +/*0134*/ 0xffffffffU, +/*0135*/ 0x00010b80U, +/*0136*/ 0x08020b80U, +/*0137*/ 0x10050b80U, +/*0138*/ 0x18050b80U, +/*0139*/ 0x00050b81U, +/*013a*/ 0x08050b81U, +/*013b*/ 0x100b0b81U, +/*013c*/ 0x00050b82U, +/*013d*/ 0x08010b82U, +/*013e*/ 0x10010b82U, +/*013f*/ 0xffffffffU, +/*0140*/ 0x18010b82U, +/*0141*/ 0x00010b83U, +/*0142*/ 0x08040b83U, +/*0143*/ 0x100b0b83U, +/*0144*/ 0x000b0b84U, +/*0145*/ 0xffffffffU, +/*0146*/ 0x10040b84U, +/*0147*/ 0x000b0b85U, +/*0148*/ 0x10040b85U, +/*0149*/ 0x18010b85U, +/*014a*/ 0x00010b86U, +/*014b*/ 0x08010b86U, +/*014c*/ 0x00200b87U, +/*014d*/ 0x00200b88U, +/*014e*/ 0x00080b89U, +/*014f*/ 0x080a0b89U, +/*0150*/ 0x18050b89U, +/*0151*/ 0x000a0b8aU, +/*0152*/ 0x10030b8aU, +/*0153*/ 0x18030b8aU, +/*0154*/ 0x00010b8bU, +/*0155*/ 0x08020b8bU, +/*0156*/ 0x10010b8bU, +/*0157*/ 0x18010b8bU, +/*0158*/ 0x00010b8cU, +/*0159*/ 0x08030b8cU, +/*015a*/ 0xffffffffU, +/*015b*/ 0x10040b8cU, +/*015c*/ 0x18040b8cU, +/*015d*/ 0x00040b8dU, +/*015e*/ 0x08040b8dU, +/*015f*/ 0xffffffffU, +/*0160*/ 0xffffffffU, +/*0161*/ 0xffffffffU, +/*0162*/ 0xffffffffU, +/*0163*/ 0xffffffffU, +/*0164*/ 0xffffffffU, +/*0165*/ 0xffffffffU, +/*0166*/ 0xffffffffU, +/*0167*/ 0xffffffffU, +/*0168*/ 0x000d0b8eU, +/*0169*/ 0x100d0b8eU, +/*016a*/ 0x000d0b8fU, +/*016b*/ 0x00050b90U, +/*016c*/ 0x00010b91U, +/*016d*/ 0x080e0b91U, +/*016e*/ 0x000e0b92U, +/*016f*/ 0x100e0b92U, +/*0170*/ 0x000e0b93U, +/*0171*/ 0x100e0b93U, +/*0172*/ 0x00040b94U, +/*0173*/ 0x08040b94U, +/*0174*/ 0x10040b94U, +/*0175*/ 0x18040b94U, +/*0176*/ 0x00040b95U, +/*0177*/ 0x080b0b95U, +/*0178*/ 0x000b0b96U, +/*0179*/ 0x100b0b96U, +/*017a*/ 0x000b0b97U, +/*017b*/ 0xffffffffU, +/*017c*/ 0xffffffffU, +/*017d*/ 0xffffffffU, +/*017e*/ 0xffffffffU, +/*017f*/ 0x000d0b98U, +/*0180*/ 0x100d0b98U, +/*0181*/ 0x000d0b99U, +/*0182*/ 0x10100b99U, +/*0183*/ 0x10080b8dU, +/*0184*/ 0x18080b8dU, +/*0185*/ 0x00100b9aU, +/*0186*/ 0x10100b9aU, +/*0187*/ 0x00100b9bU, +/*0188*/ 0x10100b9bU, +/*0189*/ 0x00100b9cU, +/*018a*/ 0x10030b9cU, +/*018b*/ 0x18040b9cU, +/*018c*/ 0x00010b9dU, +/*018d*/ 0x08040b9dU, +/*018e*/ 0xffffffffU, +/*018f*/ 0xffffffffU, +/*0190*/ 0x10010b9dU, +/*0191*/ 0x00140b9eU, +/*0192*/ 0x000a0b9fU, +/*0193*/ 0x100c0b9fU, +/*0194*/ 0x00120ba0U, +/*0195*/ 0x00140ba1U, +/*0196*/ 0x00120ba2U, +/*0197*/ 0x00110ba3U, +/*0198*/ 0x00110ba4U, +/*0199*/ 0x00120ba5U, +/*019a*/ 0x00120ba6U, +/*019b*/ 0x00120ba7U, +/*019c*/ 0x00120ba8U, +/*019d*/ 0x00120ba9U, +/*019e*/ 0x00120baaU, +/*019f*/ 0x00120babU, +/*01a0*/ 0x00120bacU, +/*01a1*/ 0xffffffffU, +/*01a2*/ 0xffffffffU, +/*01a3*/ 0x00190badU, +/*01a4*/ 0x00190baeU, +/*01a5*/ 0x00200bafU, +/*01a6*/ 0x00170bb0U, +/*01a7*/ 0x18080bb0U, +/*01a8*/ 0x00010bb1U, +/*01a9*/ 0x08010bb1U, +/*01aa*/ 0x00200bb2U, +/*01ab*/ 0x00080bb3U, +/*01ac*/ 0xffffffffU, +/*01ad*/ 0x08030bb3U, +/*01ae*/ 0x00180bb4U, +/*01af*/ 0x00180bb5U, +/*01b0*/ 0xffffffffU, +/*01b1*/ 0xffffffffU, +/*01b2*/ 0xffffffffU, +/*01b3*/ 0xffffffffU, +/*01b4*/ 0xffffffffU, +/*01b5*/ 0xffffffffU, +/*01b6*/ 0xffffffffU, +/*01b7*/ 0xffffffffU, +/*01b8*/ 0xffffffffU, +/*01b9*/ 0xffffffffU, +/*01ba*/ 0xffffffffU, +/*01bb*/ 0xffffffffU, +/*01bc*/ 0xffffffffU, +/*01bd*/ 0xffffffffU, +/*01be*/ 0xffffffffU, +/*01bf*/ 0x00100bb6U, +/*01c0*/ 0x10010bb6U, +/*01c1*/ 0x18010bb6U, +/*01c2*/ 0x00050bb7U, +/*01c3*/ 0x00200bb8U, +/*01c4*/ 0x00090bb9U, +/*01c5*/ 0xffffffffU, +/*01c6*/ 0xffffffffU, +/*01c7*/ 0x00200bbaU, +/*01c8*/ 0x00040bbbU, +/*01c9*/ 0x08100bbbU, +/*01ca*/ 0x18060bbbU, +/*01cb*/ 0x00100bbcU, +/*01cc*/ 0xffffffffU, +/*01cd*/ 0x10080bbcU, +/*01ce*/ 0xffffffffU, +/*01cf*/ 0xffffffffU, +/*01d0*/ 0xffffffffU, +/*01d1*/ 0x18030bbcU, +/*01d2*/ 0x00020bbdU, +/*01d3*/ 0xffffffffU, +/*01d4*/ 0x00200bbeU, +/*01d5*/ 0x000b0bbfU, +/*01d6*/ 0xffffffffU, +/*01d7*/ 0xffffffffU, +/*01d8*/ 0xffffffffU, +/*01d9*/ 0x10020bbfU, +/*01da*/ 0xffffffffU, +/*01db*/ 0xffffffffU, +/*01dc*/ 0xffffffffU, +/*01dd*/ 0xffffffffU, +/*01de*/ 0x00010200U, +/*01df*/ 0x08040200U, +/*01e0*/ 0x10100200U, +/*01e1*/ 0x00010201U, +/*01e2*/ 0x08010201U, +/*01e3*/ 0xffffffffU, +/*01e4*/ 0xffffffffU, +/*01e5*/ 0x10100201U, +/*01e6*/ 0xffffffffU, +/*01e7*/ 0xffffffffU, +/*01e8*/ 0xffffffffU, +/*01e9*/ 0xffffffffU, +/*01ea*/ 0xffffffffU, +/*01eb*/ 0xffffffffU, +/*01ec*/ 0xffffffffU, +/*01ed*/ 0xffffffffU, +/*01ee*/ 0xffffffffU, +/*01ef*/ 0x00200202U, +/*01f0*/ 0x00100203U, +/*01f1*/ 0x00200204U, +/*01f2*/ 0x00100205U, +/*01f3*/ 0x00200206U, +/*01f4*/ 0x00100207U, +/*01f5*/ 0x10100207U, +/*01f6*/ 0x00200208U, +/*01f7*/ 0x00200209U, +/*01f8*/ 0x0020020aU, +/*01f9*/ 0x0020020bU, +/*01fa*/ 0x0010020cU, +/*01fb*/ 0x0020020dU, +/*01fc*/ 0x0020020eU, +/*01fd*/ 0x0020020fU, +/*01fe*/ 0x00200210U, +/*01ff*/ 0x00100211U, +/*0200*/ 0x00200212U, +/*0201*/ 0x00200213U, +/*0202*/ 0x00200214U, +/*0203*/ 0x00200215U, +/*0204*/ 0x00090216U, +/*0205*/ 0x10010216U, +/*0206*/ 0x00200217U, +/*0207*/ 0x00050218U, +/*0208*/ 0x08010218U, +/*0209*/ 0x10080218U, +/*020a*/ 0x18080218U, +/*020b*/ 0x001e0219U, +/*020c*/ 0x001e021aU, +/*020d*/ 0x001e021bU, +/*020e*/ 0x001e021cU, +/*020f*/ 0x001e021dU, +/*0210*/ 0x001e021eU, +/*0211*/ 0x001e021fU, +/*0212*/ 0x001e0220U, +/*0213*/ 0x001e0221U, +/*0214*/ 0x001e0222U, +/*0215*/ 0x001e0223U, +/*0216*/ 0x001e0224U, +/*0217*/ 0x001e0225U, +/*0218*/ 0x001e0226U, +/*0219*/ 0x001e0227U, +/*021a*/ 0x001e0228U, +/*021b*/ 0x00010229U, +/*021c*/ 0x08010229U, +/*021d*/ 0x10010229U, +/*021e*/ 0x18040229U, +/*021f*/ 0x0008022aU, +/*0220*/ 0x0808022aU, +/*0221*/ 0x1008022aU, +/*0222*/ 0x1804022aU, +/*0223*/ 0x0005022bU, +/*0224*/ 0x0806022bU, +/*0225*/ 0x1007022bU, +/*0226*/ 0x1805022bU, +/*0227*/ 0x0006022cU, +/*0228*/ 0x0807022cU, +/*0229*/ 0x1005022cU, +/*022a*/ 0x1806022cU, +/*022b*/ 0x0007022dU, +/*022c*/ 0x0802022dU, +/*022d*/ 0x1001022dU, +/*022e*/ 0xffffffffU, +/*022f*/ 0x000a022eU, +/*0230*/ 0x1010022eU, +/*0231*/ 0x000a022fU, +/*0232*/ 0x1010022fU, +/*0233*/ 0x000a0230U, +/*0234*/ 0x10100230U, +/*0235*/ 0xffffffffU, +/*0236*/ 0x00100231U, +/*0237*/ 0xffffffffU, +/*0238*/ 0xffffffffU, +/*0239*/ 0x10010231U, +/*023a*/ 0x18010231U, +/*023b*/ 0x00010232U, +/*023c*/ 0x08010232U, +/*023d*/ 0x10010232U, +/*023e*/ 0x18010232U, +/*023f*/ 0x00020233U, +/*0240*/ 0x08020233U, +/*0241*/ 0x10020233U, +/*0242*/ 0x18020233U, +/*0243*/ 0x00020234U, +/*0244*/ 0x08030234U, +/*0245*/ 0x10010234U, +/*0246*/ 0x18010234U, +/*0247*/ 0x00010235U, +/*0248*/ 0x08010235U, +/*0249*/ 0xffffffffU, +/*024a*/ 0x10020235U, +/*024b*/ 0x18010235U, +/*024c*/ 0x00010236U, +/*024d*/ 0xffffffffU, +/*024e*/ 0x08020236U, +/*024f*/ 0x10010236U, +/*0250*/ 0x18010236U, +/*0251*/ 0xffffffffU, +/*0252*/ 0x00020237U, +/*0253*/ 0x08010237U, +/*0254*/ 0x10010237U, +/*0255*/ 0xffffffffU, +/*0256*/ 0x18020237U, +/*0257*/ 0x00070238U, +/*0258*/ 0x08010238U, +/*0259*/ 0x10010238U, +/*025a*/ 0x18010238U, +/*025b*/ 0x00010239U, +/*025c*/ 0x08010239U, +/*025d*/ 0x10010239U, +/*025e*/ 0xffffffffU, +/*025f*/ 0x18010239U, +/*0260*/ 0x0004023aU, +/*0261*/ 0x0804023aU, +/*0262*/ 0x1004023aU, +/*0263*/ 0x1801023aU, +/*0264*/ 0x0002023bU, +/*0265*/ 0x0806023bU, +/*0266*/ 0x1006023bU, +/*0267*/ 0xffffffffU, +/*0268*/ 0xffffffffU, +/*0269*/ 0xffffffffU, +/*026a*/ 0x1802023bU, +/*026b*/ 0x0010023cU, +/*026c*/ 0x1001023cU, +/*026d*/ 0x1801023cU, +/*026e*/ 0xffffffffU, +/*026f*/ 0x0004023dU, +/*0270*/ 0x0801023dU, +/*0271*/ 0x1004023dU, +/*0272*/ 0x1802023dU, +/*0273*/ 0x0008023eU, +/*0274*/ 0xffffffffU, +/*0275*/ 0xffffffffU, +/*0276*/ 0xffffffffU, +/*0277*/ 0x080a023eU, +/*0278*/ 0x0020023fU, +/*0279*/ 0x00200240U, +/*027a*/ 0x00050241U, +/*027b*/ 0x08010241U, +/*027c*/ 0x10050241U, +/*027d*/ 0x18080241U, +/*027e*/ 0x00010242U, +/*027f*/ 0x08080242U, +/*0280*/ 0x10010242U, +/*0281*/ 0x18080242U, +/*0282*/ 0x00010243U, +/*0283*/ 0x08040243U, +/*0284*/ 0x10040243U, +/*0285*/ 0x18040243U, +/*0286*/ 0x00040244U, +/*0287*/ 0x08040244U, +/*0288*/ 0x10040244U, +/*0289*/ 0x18040244U, +/*028a*/ 0x00040245U, +/*028b*/ 0x08040245U, +/*028c*/ 0x10040245U, +/*028d*/ 0x18010245U, +/*028e*/ 0x00040246U, +/*028f*/ 0x08040246U, +/*0290*/ 0x10040246U, +/*0291*/ 0x18040246U, +/*0292*/ 0x00040247U, +/*0293*/ 0x08040247U, +/*0294*/ 0x10060247U, +/*0295*/ 0x18060247U, +/*0296*/ 0x00060248U, +/*0297*/ 0x08060248U, +/*0298*/ 0x10060248U, +/*0299*/ 0x18060248U, +/*029a*/ 0x00040249U, +/*029b*/ 0x08010249U, +/*029c*/ 0x10010249U, +/*029d*/ 0x18020249U, +/*029e*/ 0xffffffffU, +/*029f*/ 0xffffffffU, +/*02a0*/ 0xffffffffU, +/*02a1*/ 0xffffffffU, +/*02a2*/ 0xffffffffU, +/*02a3*/ 0xffffffffU, +/*02a4*/ 0xffffffffU, +/*02a5*/ 0xffffffffU, +/*02a6*/ 0x0004024aU, +/*02a7*/ 0x0804024aU, +/*02a8*/ 0x1001024aU, +/*02a9*/ 0x1801024aU, +/*02aa*/ 0xffffffffU, +/*02ab*/ 0x0001024bU, +/*02ac*/ 0x0801024bU, +/*02ad*/ 0xffffffffU, +/*02ae*/ 0x1001024bU, +/*02af*/ 0x1801024bU, +/*02b0*/ 0x0001024cU, +/*02b1*/ 0x0804024cU, +/*02b2*/ 0x1004024cU, +/*02b3*/ 0x000a024dU, +/*02b4*/ 0x0020024eU, +/*02b5*/ 0x0004024fU, +/*02b6*/ 0x0808024fU, +/*02b7*/ 0xffffffffU, +/*02b8*/ 0xffffffffU, +/*02b9*/ 0xffffffffU, +/*02ba*/ 0xffffffffU, +/*02bb*/ 0xffffffffU, +/*02bc*/ 0xffffffffU, +/*02bd*/ 0x1002024fU, +/*02be*/ 0x1802024fU, +/*02bf*/ 0x00200250U, +/*02c0*/ 0x00020251U, +/*02c1*/ 0x08100251U, +/*02c2*/ 0x00100252U, +/*02c3*/ 0x10040252U, +/*02c4*/ 0x18040252U, +/*02c5*/ 0x00050253U, +/*02c6*/ 0x08050253U, +/*02c7*/ 0xffffffffU, +/*02c8*/ 0xffffffffU, +/*02c9*/ 0xffffffffU, +/*02ca*/ 0xffffffffU, +/*02cb*/ 0x10010253U, +/*02cc*/ 0x18010253U, +/*02cd*/ 0x00080254U, +/*02ce*/ 0x08080254U, +/*02cf*/ 0x10080254U, +/*02d0*/ 0x18080254U, +/*02d1*/ 0x00080255U, +/*02d2*/ 0x08080255U, +/*02d3*/ 0x10080255U, +/*02d4*/ 0x18080255U, +/*02d5*/ 0x00080256U, +/*02d6*/ 0x08080256U, +/*02d7*/ 0x10080256U, +/*02d8*/ 0xffffffffU, +/*02d9*/ 0xffffffffU, +/*02da*/ 0xffffffffU, +/*02db*/ 0xffffffffU, +/*02dc*/ 0xffffffffU, +/*02dd*/ 0xffffffffU, +/*02de*/ 0x18030256U, +/*02df*/ 0x00010257U, +/*02e0*/ 0x08020257U, +/*02e1*/ 0x10010257U, +/*02e2*/ 0x18040257U, +/*02e3*/ 0x00020258U, +/*02e4*/ 0x08010258U, +/*02e5*/ 0x10010258U, +/*02e6*/ 0xffffffffU, +/*02e7*/ 0x18010258U, +/*02e8*/ 0x00040259U, +/*02e9*/ 0x08080259U, +/*02ea*/ 0x100a0259U, +/*02eb*/ 0x000a025aU, +/*02ec*/ 0x100a025aU, +/*02ed*/ 0x000a025bU, +/*02ee*/ 0x100a025bU, +/*02ef*/ 0x000a025cU, +/*02f0*/ 0x0020025dU, +/*02f1*/ 0x0020025eU, +/*02f2*/ 0x0001025fU, +/*02f3*/ 0xffffffffU, +/*02f4*/ 0xffffffffU, +/*02f5*/ 0xffffffffU, +/*02f6*/ 0x0802025fU, +/*02f7*/ 0x1002025fU, +/*02f8*/ 0x00100260U, +/*02f9*/ 0x10050260U, +/*02fa*/ 0x18060260U, +/*02fb*/ 0x00050261U, +/*02fc*/ 0x08050261U, +/*02fd*/ 0x100e0261U, +/*02fe*/ 0x00050262U, +/*02ff*/ 0x080e0262U, +/*0300*/ 0x18050262U, +/*0301*/ 0x000e0263U, +/*0302*/ 0x10050263U, +/*0303*/ 0x18010263U, +/*0304*/ 0x00050264U, +/*0305*/ 0x08050264U, +/*0306*/ 0x100a0264U, +/*0307*/ 0x000a0265U, +/*0308*/ 0x10050265U, +/*0309*/ 0x18050265U, +/*030a*/ 0x000a0266U, +/*030b*/ 0x100a0266U, +/*030c*/ 0x00050267U, +/*030d*/ 0x08050267U, +/*030e*/ 0x100a0267U, +/*030f*/ 0x000a0268U, +/*0310*/ 0xffffffffU, +/*0311*/ 0xffffffffU, +/*0312*/ 0xffffffffU, +/*0313*/ 0xffffffffU, +/*0314*/ 0xffffffffU, +/*0315*/ 0xffffffffU, +/*0316*/ 0x10070268U, +/*0317*/ 0x18070268U, +/*0318*/ 0x00040269U, +/*0319*/ 0x08040269U, +/*031a*/ 0xffffffffU, +/*031b*/ 0xffffffffU, +/*031c*/ 0xffffffffU, +/*031d*/ 0x10040269U, +/*031e*/ 0x18080269U, +/*031f*/ 0x0008026aU, +/*0320*/ 0x0804026aU, +/*0321*/ 0xffffffffU, +/*0322*/ 0xffffffffU, +/*0323*/ 0xffffffffU, +/*0324*/ 0x1004026aU, +/*0325*/ 0xffffffffU, +/*0326*/ 0xffffffffU, +/*0327*/ 0xffffffffU, +/*0328*/ 0x1804026aU, +/*0329*/ 0xffffffffU, +/*032a*/ 0xffffffffU, +/*032b*/ 0xffffffffU, +/*032c*/ 0x0004026bU, +/*032d*/ 0x0805026bU, +/*032e*/ 0x1007026bU, +/*032f*/ 0x1808026bU, +/*0330*/ 0x0010026cU, +/*0331*/ 0x1008026cU, +/*0332*/ 0x0010026dU, +/*0333*/ 0x1008026dU, +/*0334*/ 0x0010026eU, +/*0335*/ 0x1008026eU, +/*0336*/ 0x1808026eU, +/*0337*/ 0x0001026fU, +/*0338*/ 0x0801026fU, +/*0339*/ 0x1006026fU, +/*033a*/ 0x1806026fU, +/*033b*/ 0x00060270U, +/*033c*/ 0xffffffffU, +/*033d*/ 0x08010270U, +/*033e*/ 0x10030270U, +/*033f*/ 0xffffffffU, +/*0340*/ 0xffffffffU, +/*0341*/ 0xffffffffU, +/*0342*/ 0x000a0271U, +/*0343*/ 0x100a0271U, +/*0344*/ 0x00040272U, +/*0345*/ 0x08010272U, +/*0346*/ 0x10040272U, +/*0347*/ 0xffffffffU, +/*0348*/ 0xffffffffU, +/*0349*/ 0xffffffffU, +/*034a*/ 0xffffffffU, +/*034b*/ 0xffffffffU, +/*034c*/ 0xffffffffU, +/*034d*/ 0x18070272U, +/*034e*/ 0x00070273U, +/*034f*/ 0x08050273U, +/*0350*/ 0x10050273U, +/*0351*/ 0xffffffffU, +/*0352*/ 0xffffffffU, +/*0353*/ 0xffffffffU, +/*0354*/ 0x18040273U, +/*0355*/ 0x00010274U, +/*0356*/ 0x08010274U, +/*0357*/ 0x10020274U, +/*0358*/ 0x18080274U, +/*0359*/ 0x00200275U, +/*035a*/ 0x00200276U, +/*035b*/ 0x00100277U, +/*035c*/ 0xffffffffU, +/*035d*/ 0xffffffffU, +/*035e*/ 0xffffffffU, +/*035f*/ 0x10020277U, +/*0360*/ 0x18010277U, +/*0361*/ 0xffffffffU, +/*0362*/ 0x00020278U, +/*0363*/ 0x08100278U, +/*0364*/ 0x00100279U, +/*0365*/ 0x10100279U, +/*0366*/ 0x0008027aU, +/*0367*/ 0x0808027aU, +/*0368*/ 0x1008027aU, +/*0369*/ 0xffffffffU, +/*036a*/ 0x0010027bU, +/*036b*/ 0x1010027bU, +/*036c*/ 0x0010027cU, +/*036d*/ 0x1008027cU, +/*036e*/ 0x1808027cU, +/*036f*/ 0x0008027dU, +/*0370*/ 0xffffffffU, +/*0371*/ 0x0810027dU, +/*0372*/ 0x0010027eU, +/*0373*/ 0x1010027eU, +/*0374*/ 0x0008027fU, +/*0375*/ 0x0808027fU, +/*0376*/ 0x1008027fU, +/*0377*/ 0xffffffffU, +/*0378*/ 0x1808027fU, +/*0379*/ 0x00100280U, +/*037a*/ 0x10100280U, +/*037b*/ 0x00100281U, +/*037c*/ 0x10080281U, +/*037d*/ 0x18080281U, +/*037e*/ 0x00080282U, +/*037f*/ 0xffffffffU, +/*0380*/ 0x08100282U, +/*0381*/ 0x00100283U, +/*0382*/ 0x10100283U, +/*0383*/ 0x00080284U, +/*0384*/ 0x08080284U, +/*0385*/ 0x10080284U, +/*0386*/ 0xffffffffU, +/*0387*/ 0x00100285U, +/*0388*/ 0x10100285U, +/*0389*/ 0x00100286U, +/*038a*/ 0x10080286U, +/*038b*/ 0x18080286U, +/*038c*/ 0x00080287U, +/*038d*/ 0xffffffffU, +/*038e*/ 0x08080287U, +/*038f*/ 0x10100287U, +/*0390*/ 0x00100288U, +/*0391*/ 0x10100288U, +/*0392*/ 0x00080289U, +/*0393*/ 0x08080289U, +/*0394*/ 0x10080289U, +/*0395*/ 0xffffffffU, +/*0396*/ 0x0010028aU, +/*0397*/ 0x1010028aU, +/*0398*/ 0x0010028bU, +/*0399*/ 0x1008028bU, +/*039a*/ 0x1808028bU, +/*039b*/ 0x0008028cU, +/*039c*/ 0xffffffffU, +/*039d*/ 0x0810028cU, +/*039e*/ 0x0010028dU, +/*039f*/ 0x1010028dU, +/*03a0*/ 0x0008028eU, +/*03a1*/ 0x0808028eU, +/*03a2*/ 0x1008028eU, +/*03a3*/ 0xffffffffU, +/*03a4*/ 0x1808028eU, +/*03a5*/ 0x0010028fU, +/*03a6*/ 0x1010028fU, +/*03a7*/ 0x00100290U, +/*03a8*/ 0x10080290U, +/*03a9*/ 0x18080290U, +/*03aa*/ 0x00080291U, +/*03ab*/ 0xffffffffU, +/*03ac*/ 0x08100291U, +/*03ad*/ 0x00100292U, +/*03ae*/ 0x10100292U, +/*03af*/ 0x00080293U, +/*03b0*/ 0x08080293U, +/*03b1*/ 0x10080293U, +/*03b2*/ 0xffffffffU, +/*03b3*/ 0x00100294U, +/*03b4*/ 0x10100294U, +/*03b5*/ 0x00100295U, +/*03b6*/ 0x10080295U, +/*03b7*/ 0x18080295U, +/*03b8*/ 0x00080296U, +/*03b9*/ 0xffffffffU, +/*03ba*/ 0x08080296U, +/*03bb*/ 0x10020296U, +/*03bc*/ 0x18030296U, +/*03bd*/ 0x000a0297U, +/*03be*/ 0x100a0297U, +/*03bf*/ 0x000a0298U, +/*03c0*/ 0x10050298U, +/*03c1*/ 0x18040298U, +/*03c2*/ 0x00080299U, +/*03c3*/ 0x08080299U, +/*03c4*/ 0x10060299U, +/*03c5*/ 0x18060299U, +/*03c6*/ 0x0011029aU, +/*03c7*/ 0x1808029aU, +/*03c8*/ 0x0004029bU, +/*03c9*/ 0x0806029bU, +/*03ca*/ 0xffffffffU, +/*03cb*/ 0x1006029bU, +/*03cc*/ 0x1808029bU, +/*03cd*/ 0x0008029cU, +/*03ce*/ 0x0804029cU, +/*03cf*/ 0x1008029cU, +/*03d0*/ 0x1808029cU, +/*03d1*/ 0x0006029dU, +/*03d2*/ 0x0806029dU, +/*03d3*/ 0x0011029eU, +/*03d4*/ 0x1808029eU, +/*03d5*/ 0x0004029fU, +/*03d6*/ 0x0806029fU, +/*03d7*/ 0xffffffffU, +/*03d8*/ 0x1006029fU, +/*03d9*/ 0x1808029fU, +/*03da*/ 0x000802a0U, +/*03db*/ 0x080402a0U, +/*03dc*/ 0x100802a0U, +/*03dd*/ 0x180802a0U, +/*03de*/ 0x000602a1U, +/*03df*/ 0x080602a1U, +/*03e0*/ 0x001102a2U, +/*03e1*/ 0x180802a2U, +/*03e2*/ 0x000402a3U, +/*03e3*/ 0x080602a3U, +/*03e4*/ 0xffffffffU, +/*03e5*/ 0x100602a3U, +/*03e6*/ 0x180802a3U, +/*03e7*/ 0x000802a4U, +/*03e8*/ 0x080402a4U, +/*03e9*/ 0x100402a4U, +/*03ea*/ 0x180402a4U, +/*03eb*/ 0x000402a5U, +/*03ec*/ 0x080402a5U, +/*03ed*/ 0x100402a5U, +/*03ee*/ 0x180402a5U, +/*03ef*/ 0x000402a6U, +/*03f0*/ 0x080402a6U, +/*03f1*/ 0x100402a6U, +/*03f2*/ 0x180402a6U, +/*03f3*/ 0x000402a7U, +/*03f4*/ 0x080402a7U, +/*03f5*/ 0x100402a7U, +/*03f6*/ 0x180402a7U, +/*03f7*/ 0x000402a8U, +/*03f8*/ 0x080402a8U, +/*03f9*/ 0x100402a8U, +/*03fa*/ 0x180402a8U, +/*03fb*/ 0x000402a9U, +/*03fc*/ 0x081202a9U, +/*03fd*/ 0x001102aaU, +/*03fe*/ 0x001202abU, +/*03ff*/ 0x002002acU, +/*0400*/ 0x002002adU, +/*0401*/ 0x002002aeU, +/*0402*/ 0x002002afU, +/*0403*/ 0x002002b0U, +/*0404*/ 0x002002b1U, +/*0405*/ 0x002002b2U, +/*0406*/ 0x002002b3U, +/*0407*/ 0x002002b4U, +/*0408*/ 0x000302b5U, +/*0409*/ 0x080502b5U, +/*040a*/ 0x100502b5U, +/*040b*/ 0x180102b5U, +/*040c*/ 0x000502b6U, +/*040d*/ 0x080502b6U, +/*040e*/ 0x100502b6U, +/*040f*/ 0x180502b6U, +/*0410*/ 0x000502b7U, +/*0411*/ 0x080502b7U, +/*0412*/ 0x100502b7U, +/*0413*/ 0x180502b7U, +/*0414*/ 0x000502b8U, +/*0415*/ 0x080502b8U, +/*0416*/ 0x100502b8U, +/*0417*/ 0x180502b8U, +/*0418*/ 0x000502b9U, +/*0419*/ 0x080502b9U, +/*041a*/ 0x100502b9U, +/*041b*/ 0x180502b9U, +/*041c*/ 0x000502baU, +/*041d*/ 0x080502baU, +/*041e*/ 0x100502baU, +/*041f*/ 0x180502baU, +/*0420*/ 0x000502bbU, +/*0421*/ 0x080502bbU, +/*0422*/ 0x100102bbU, +/*0423*/ 0x180202bbU, +/*0424*/ 0x000202bcU, +/*0425*/ 0x080202bcU, +/*0426*/ 0x100202bcU, +/*0427*/ 0x180102bcU, +/*0428*/ 0x000402bdU, +/*0429*/ 0x081002bdU, +/*042a*/ 0x002002beU, +/*042b*/ 0x001002bfU, +/*042c*/ 0x002002c0U, +/*042d*/ 0x001002c1U, +/*042e*/ 0x002002c2U, +/*042f*/ 0x000702c3U, +/*0430*/ 0x080102c3U, +/*0431*/ 0x100202c3U, +/*0432*/ 0x180602c3U, +/*0433*/ 0x000102c4U, +/*0434*/ 0x080102c4U, +/*0435*/ 0x002002c5U, +/*0436*/ 0x000302c6U, +/*0437*/ 0x002002c7U, +/*0438*/ 0x002002c8U, +/*0439*/ 0xffffffffU, +/*043a*/ 0xffffffffU, +/*043b*/ 0xffffffffU, +/*043c*/ 0xffffffffU, +/*043d*/ 0xffffffffU, +/*043e*/ 0xffffffffU, +/*043f*/ 0xffffffffU, +/*0440*/ 0xffffffffU, +/*0441*/ 0xffffffffU, +/*0442*/ 0xffffffffU, +/*0443*/ 0xffffffffU, +/*0444*/ 0xffffffffU, +/*0445*/ 0xffffffffU, +/*0446*/ 0xffffffffU, +/*0447*/ 0xffffffffU, +/*0448*/ 0xffffffffU, +/*0449*/ 0xffffffffU, +/*044a*/ 0xffffffffU, +/*044b*/ 0xffffffffU, +/*044c*/ 0xffffffffU, +/*044d*/ 0xffffffffU, +/*044e*/ 0xffffffffU, +/*044f*/ 0xffffffffU, +/*0450*/ 0xffffffffU, +/*0451*/ 0xffffffffU, +/*0452*/ 0xffffffffU, +/*0453*/ 0xffffffffU, +/*0454*/ 0xffffffffU, +/*0455*/ 0xffffffffU, +/*0456*/ 0xffffffffU, +/*0457*/ 0xffffffffU, +/*0458*/ 0xffffffffU, +/*0459*/ 0xffffffffU, +/*045a*/ 0xffffffffU, +/*045b*/ 0xffffffffU, +/*045c*/ 0xffffffffU, +/*045d*/ 0xffffffffU, +/*045e*/ 0xffffffffU, +/*045f*/ 0x000402c9U, +/*0460*/ 0xffffffffU, +/*0461*/ 0xffffffffU, +/*0462*/ 0xffffffffU, +/*0463*/ 0xffffffffU, +/*0464*/ 0xffffffffU, +/*0465*/ 0xffffffffU, +/*0466*/ 0xffffffffU, +/*0467*/ 0xffffffffU, +/*0468*/ 0xffffffffU, +/*0469*/ 0xffffffffU, +/*046a*/ 0xffffffffU, +/*046b*/ 0xffffffffU, +/*046c*/ 0xffffffffU, +/*046d*/ 0xffffffffU, +/*046e*/ 0xffffffffU, +/*046f*/ 0xffffffffU, +/*0470*/ 0xffffffffU, +/*0471*/ 0xffffffffU, +/*0472*/ 0xffffffffU, +/*0473*/ 0xffffffffU, +/*0474*/ 0xffffffffU, +/*0475*/ 0xffffffffU, +/*0476*/ 0xffffffffU, +/*0477*/ 0xffffffffU, +/*0478*/ 0xffffffffU, +/*0479*/ 0xffffffffU, +/*047a*/ 0xffffffffU, +/*047b*/ 0xffffffffU, +/*047c*/ 0xffffffffU, +/*047d*/ 0xffffffffU, +/*047e*/ 0xffffffffU, +/*047f*/ 0xffffffffU, +/*0480*/ 0xffffffffU, +/*0481*/ 0xffffffffU, +/*0482*/ 0xffffffffU, +/*0483*/ 0xffffffffU, +/*0484*/ 0xffffffffU, +/*0485*/ 0xffffffffU, +/*0486*/ 0xffffffffU, +/*0487*/ 0xffffffffU, +/*0488*/ 0xffffffffU, +/*0489*/ 0xffffffffU, +/*048a*/ 0xffffffffU, +/*048b*/ 0xffffffffU, +/*048c*/ 0xffffffffU, +/*048d*/ 0xffffffffU, +/*048e*/ 0xffffffffU, +/*048f*/ 0xffffffffU, +/*0490*/ 0xffffffffU, +/*0491*/ 0xffffffffU, +/*0492*/ 0xffffffffU, +/*0493*/ 0xffffffffU, +/*0494*/ 0xffffffffU, + }, + { +/*0000*/ 0x00200400U, +/*0001*/ 0x00040401U, +/*0002*/ 0x080b0401U, +/*0003*/ 0x000a0402U, +/*0004*/ 0x10020402U, +/*0005*/ 0x18010402U, +/*0006*/ 0x00050403U, +/*0007*/ 0x08050403U, +/*0008*/ 0x10050403U, +/*0009*/ 0x18050403U, +/*000a*/ 0x00050404U, +/*000b*/ 0x08050404U, +/*000c*/ 0x10050404U, +/*000d*/ 0x18050404U, +/*000e*/ 0x00050405U, +/*000f*/ 0x08040405U, +/*0010*/ 0x10030405U, +/*0011*/ 0x00180406U, +/*0012*/ 0x18030406U, +/*0013*/ 0x00180407U, +/*0014*/ 0x18020407U, +/*0015*/ 0x00010408U, +/*0016*/ 0x08020408U, +/*0017*/ 0x10010408U, +/*0018*/ 0x18010408U, +/*0019*/ 0x00020409U, +/*001a*/ 0x08040409U, +/*001b*/ 0x10040409U, +/*001c*/ 0x18040409U, +/*001d*/ 0xffffffffU, +/*001e*/ 0x0004040aU, +/*001f*/ 0xffffffffU, +/*0020*/ 0xffffffffU, +/*0021*/ 0x0809040aU, +/*0022*/ 0x1801040aU, +/*0023*/ 0x0020040bU, +/*0024*/ 0x001c040cU, +/*0025*/ 0x0001040dU, +/*0026*/ 0x0807040dU, +/*0027*/ 0x1009040dU, +/*0028*/ 0x000a040eU, +/*0029*/ 0x1005040eU, +/*002a*/ 0x1801040eU, +/*002b*/ 0x1001040fU, +/*002c*/ 0x1802040fU, +/*002d*/ 0x0009040fU, +/*002e*/ 0x00090410U, +/*002f*/ 0x10020410U, +/*0030*/ 0x00200411U, +/*0031*/ 0x00010412U, +/*0032*/ 0x08020412U, +/*0033*/ 0xffffffffU, +/*0034*/ 0xffffffffU, +/*0035*/ 0xffffffffU, +/*0036*/ 0xffffffffU, +/*0037*/ 0x00200413U, +/*0038*/ 0x00200414U, +/*0039*/ 0x00200415U, +/*003a*/ 0x00200416U, +/*003b*/ 0x00030417U, +/*003c*/ 0x08010417U, +/*003d*/ 0x10040417U, +/*003e*/ 0x18030417U, +/*003f*/ 0x00040418U, +/*0040*/ 0x08040418U, +/*0041*/ 0x10040418U, +/*0042*/ 0x18040418U, +/*0043*/ 0x00010419U, +/*0044*/ 0x08010419U, +/*0045*/ 0x10060419U, +/*0046*/ 0x18040419U, +/*0047*/ 0xffffffffU, +/*0048*/ 0x0006041aU, +/*0049*/ 0x0804041aU, +/*004a*/ 0x1006041aU, +/*004b*/ 0x1804041aU, +/*004c*/ 0x0002041bU, +/*004d*/ 0x0805041bU, +/*004e*/ 0x1008041bU, +/*004f*/ 0xffffffffU, +/*0050*/ 0x1806041bU, +/*0051*/ 0x0003041cU, +/*0052*/ 0x080b041cU, +/*0053*/ 0x1804041cU, +/*0054*/ 0x0004041dU, +/*0055*/ 0x0804041dU, +/*0056*/ 0x1001041dU, +/*0057*/ 0xffffffffU, +/*0058*/ 0x0009041eU, +/*0059*/ 0x0020041fU, +/*005a*/ 0x00200420U, +/*005b*/ 0x00200421U, +/*005c*/ 0x00200422U, +/*005d*/ 0x00100423U, +/*005e*/ 0xffffffffU, +/*005f*/ 0x10010423U, +/*0060*/ 0x18060423U, +/*0061*/ 0x00080424U, +/*0062*/ 0x00200425U, +/*0063*/ 0x00100426U, +/*0064*/ 0x100a0426U, +/*0065*/ 0x00060427U, +/*0066*/ 0x08070427U, +/*0067*/ 0x10080427U, +/*0068*/ 0x18080427U, +/*0069*/ 0x000a0428U, +/*006a*/ 0x10070428U, +/*006b*/ 0x18080428U, +/*006c*/ 0x00080429U, +/*006d*/ 0x08030429U, +/*006e*/ 0x100a0429U, +/*006f*/ 0x000a042aU, +/*0070*/ 0x0011042bU, +/*0071*/ 0x0009042cU, +/*0072*/ 0x1009042cU, +/*0073*/ 0x0010042dU, +/*0074*/ 0x100e042dU, +/*0075*/ 0x000e042eU, +/*0076*/ 0x0012042fU, +/*0077*/ 0x000a0430U, +/*0078*/ 0x100a0430U, +/*0079*/ 0x00020431U, +/*007a*/ 0x00200432U, +/*007b*/ 0x000b0433U, +/*007c*/ 0x100b0433U, +/*007d*/ 0x00200434U, +/*007e*/ 0x00120435U, +/*007f*/ 0x00200436U, +/*0080*/ 0x00200437U, +/*0081*/ 0x00080438U, +/*0082*/ 0x08010438U, +/*0083*/ 0x10010438U, +/*0084*/ 0x18010438U, +/*0085*/ 0x00080439U, +/*0086*/ 0x080c0439U, +/*0087*/ 0x000c043aU, +/*0088*/ 0x100c043aU, +/*0089*/ 0x000c043bU, +/*008a*/ 0x100c043bU, +/*008b*/ 0x000c043cU, +/*008c*/ 0x100c043cU, +/*008d*/ 0x000c043dU, +/*008e*/ 0x100c043dU, +/*008f*/ 0x000c043eU, +/*0090*/ 0x100c043eU, +/*0091*/ 0x000b043fU, +/*0092*/ 0x1009043fU, +/*0093*/ 0x00010440U, +/*0094*/ 0x000b0441U, +/*0095*/ 0x100b0441U, +/*0096*/ 0x000b0442U, +/*0097*/ 0x100b0442U, +/*0098*/ 0x000b0443U, +/*0099*/ 0x100b0443U, +/*009a*/ 0x000b0444U, +/*009b*/ 0x100b0444U, +/*009c*/ 0x000b0445U, +/*009d*/ 0x100a0445U, +/*009e*/ 0x00020446U, +/*009f*/ 0x080a0446U, +/*00a0*/ 0x000a0447U, +/*00a1*/ 0x100a0447U, +/*00a2*/ 0x000a0448U, +/*00a3*/ 0x100a0448U, +/*00a4*/ 0x000a0449U, +/*00a5*/ 0x100a0449U, +/*00a6*/ 0x000a044aU, +/*00a7*/ 0x100a044aU, +/*00a8*/ 0x000a044bU, +/*00a9*/ 0x100a044bU, +/*00aa*/ 0x000a044cU, +/*00ab*/ 0x100a044cU, +/*00ac*/ 0x000a044dU, +/*00ad*/ 0x100a044dU, +/*00ae*/ 0x000a044eU, +/*00af*/ 0x100a044eU, +/*00b0*/ 0x000a044fU, +/*00b1*/ 0x100a044fU, +/*00b2*/ 0x000a0450U, +/*00b3*/ 0x100a0450U, +/*00b4*/ 0x000a0451U, +/*00b5*/ 0x100a0451U, +/*00b6*/ 0x000a0452U, +/*00b7*/ 0x100a0452U, +/*00b8*/ 0x000a0453U, +/*00b9*/ 0x100a0453U, +/*00ba*/ 0x000a0454U, +/*00bb*/ 0x10040454U, +/*00bc*/ 0x18030454U, +/*00bd*/ 0x000a0455U, +/*00be*/ 0x100a0455U, +/*00bf*/ 0x00010456U, +/*00c0*/ 0x080a0456U, +/*00c1*/ 0x18040456U, +/*00c2*/ 0x000b0457U, +/*00c3*/ 0x100a0457U, +/*00c4*/ 0x00030458U, +/*00c5*/ 0x00080459U, +/*00c6*/ 0x08080459U, +/*00c7*/ 0x10080459U, +/*00c8*/ 0x18080459U, +/*00c9*/ 0x0008045aU, +/*00ca*/ 0xffffffffU, +/*00cb*/ 0x0808045aU, +/*00cc*/ 0x1001045aU, +/*00cd*/ 0x1808045aU, +/*00ce*/ 0x0008045bU, +/*00cf*/ 0x0802045bU, +/*00d0*/ 0x1002045bU, +/*00d1*/ 0x1805045bU, +/*00d2*/ 0x0005045cU, +/*00d3*/ 0xffffffffU, +/*00d4*/ 0x0804045cU, +/*00d5*/ 0x100a045cU, +/*00d6*/ 0x0006045dU, +/*00d7*/ 0x0808045dU, +/*00d8*/ 0x1008045dU, +/*00d9*/ 0x1804045dU, +/*00da*/ 0x0004045eU, +/*00db*/ 0x0805045eU, +/*00dc*/ 0x1004045eU, +/*00dd*/ 0x1805045eU, +/*00de*/ 0x000a045fU, +/*00df*/ 0x100a045fU, +/*00e0*/ 0x00080460U, +/*00e1*/ 0xffffffffU, +/*00e2*/ 0x08040460U, +/*00e3*/ 0xffffffffU, +/*00e4*/ 0xffffffffU, +/*00e5*/ 0x00050600U, +/*00e6*/ 0x08050600U, +/*00e7*/ 0x10050600U, +/*00e8*/ 0x18050600U, +/*00e9*/ 0x00050601U, +/*00ea*/ 0x08050601U, +/*00eb*/ 0x100b0601U, +/*00ec*/ 0x00010602U, +/*00ed*/ 0x08030602U, +/*00ee*/ 0x00200603U, +/*00ef*/ 0x00100604U, +/*00f0*/ 0x10040604U, +/*00f1*/ 0x000a0605U, +/*00f2*/ 0x10090605U, +/*00f3*/ 0x00080606U, +/*00f4*/ 0x08030606U, +/*00f5*/ 0x10030606U, +/*00f6*/ 0x18010606U, +/*00f7*/ 0x00010607U, +/*00f8*/ 0x08070607U, +/*00f9*/ 0x10070607U, +/*00fa*/ 0x18050607U, +/*00fb*/ 0x00010608U, +/*00fc*/ 0x08020608U, +/*00fd*/ 0x10030608U, +/*00fe*/ 0x18010608U, +/*00ff*/ 0x000f0609U, +/*0100*/ 0x0020060aU, +/*0101*/ 0x0020060bU, +/*0102*/ 0x000b060cU, +/*0103*/ 0x100b060cU, +/*0104*/ 0x000b060dU, +/*0105*/ 0x0018060eU, +/*0106*/ 0x0018060fU, +/*0107*/ 0xffffffffU, +/*0108*/ 0xffffffffU, +/*0109*/ 0xffffffffU, +/*010a*/ 0xffffffffU, +/*010b*/ 0xffffffffU, +/*010c*/ 0x1802060fU, +/*010d*/ 0x00020610U, +/*010e*/ 0x08040610U, +/*010f*/ 0x10040610U, +/*0110*/ 0x18010610U, +/*0111*/ 0x00010611U, +/*0112*/ 0x08010611U, +/*0113*/ 0x10030611U, +/*0114*/ 0x00200612U, +/*0115*/ 0x00200613U, +/*0116*/ 0xffffffffU, +/*0117*/ 0x00140614U, +/*0118*/ 0x00140615U, +/*0119*/ 0x00140616U, +/*011a*/ 0x00140617U, +/*011b*/ 0x00140618U, +/*011c*/ 0x00140619U, +/*011d*/ 0x0014061aU, +/*011e*/ 0x0014061bU, +/*011f*/ 0x0018061cU, +/*0120*/ 0x000a061dU, +/*0121*/ 0x1006061dU, +/*0122*/ 0x1806061dU, +/*0123*/ 0x0006061eU, +/*0124*/ 0xffffffffU, +/*0125*/ 0x0806061eU, +/*0126*/ 0x0008061fU, +/*0127*/ 0x080b061fU, +/*0128*/ 0x000b0620U, +/*0129*/ 0x100b0620U, +/*012a*/ 0x000b0621U, +/*012b*/ 0x100b0621U, +/*012c*/ 0x000b0622U, +/*012d*/ 0x10040622U, +/*012e*/ 0x000a0623U, +/*012f*/ 0x10060623U, +/*0130*/ 0x18080623U, +/*0131*/ 0x00080624U, +/*0132*/ 0x08040624U, +/*0133*/ 0x00020680U, +/*0134*/ 0x00010681U, +/*0135*/ 0x08010681U, +/*0136*/ 0x10020681U, +/*0137*/ 0x18050681U, +/*0138*/ 0x00050682U, +/*0139*/ 0x08050682U, +/*013a*/ 0x10050682U, +/*013b*/ 0x000b0683U, +/*013c*/ 0x10050683U, +/*013d*/ 0x18010683U, +/*013e*/ 0x00010684U, +/*013f*/ 0xffffffffU, +/*0140*/ 0x08010684U, +/*0141*/ 0x10010684U, +/*0142*/ 0x18040684U, +/*0143*/ 0x000b0685U, +/*0144*/ 0x100b0685U, +/*0145*/ 0x000b0686U, +/*0146*/ 0x10040686U, +/*0147*/ 0x000b0687U, +/*0148*/ 0x10040687U, +/*0149*/ 0x18010687U, +/*014a*/ 0x00010688U, +/*014b*/ 0x08010688U, +/*014c*/ 0x00200689U, +/*014d*/ 0x0020068aU, +/*014e*/ 0x0008068bU, +/*014f*/ 0x080a068bU, +/*0150*/ 0x1805068bU, +/*0151*/ 0x000a068cU, +/*0152*/ 0x1003068cU, +/*0153*/ 0x1803068cU, +/*0154*/ 0x0001068dU, +/*0155*/ 0x0802068dU, +/*0156*/ 0x1001068dU, +/*0157*/ 0x1801068dU, +/*0158*/ 0x0001068eU, +/*0159*/ 0x0802068eU, +/*015a*/ 0x1001068eU, +/*015b*/ 0x0004068fU, +/*015c*/ 0x0804068fU, +/*015d*/ 0x1004068fU, +/*015e*/ 0x1804068fU, +/*015f*/ 0x00010690U, +/*0160*/ 0x08010690U, +/*0161*/ 0x10010690U, +/*0162*/ 0x00200691U, +/*0163*/ 0x00200692U, +/*0164*/ 0x00200693U, +/*0165*/ 0x00200694U, +/*0166*/ 0xffffffffU, +/*0167*/ 0x1801068eU, +/*0168*/ 0x000d0696U, +/*0169*/ 0x100d0696U, +/*016a*/ 0x000d0697U, +/*016b*/ 0x00050698U, +/*016c*/ 0x00010699U, +/*016d*/ 0x080e0699U, +/*016e*/ 0x000e069aU, +/*016f*/ 0x100e069aU, +/*0170*/ 0x000e069bU, +/*0171*/ 0x100e069bU, +/*0172*/ 0x0004069cU, +/*0173*/ 0x0804069cU, +/*0174*/ 0x1004069cU, +/*0175*/ 0x1804069cU, +/*0176*/ 0x0004069dU, +/*0177*/ 0x080b069dU, +/*0178*/ 0x000b069eU, +/*0179*/ 0x100b069eU, +/*017a*/ 0x000b069fU, +/*017b*/ 0xffffffffU, +/*017c*/ 0xffffffffU, +/*017d*/ 0xffffffffU, +/*017e*/ 0xffffffffU, +/*017f*/ 0x000d06a0U, +/*0180*/ 0x100d06a0U, +/*0181*/ 0x000d06a1U, +/*0182*/ 0x101006a1U, +/*0183*/ 0x00080695U, +/*0184*/ 0x08080695U, +/*0185*/ 0x001006a2U, +/*0186*/ 0x101006a2U, +/*0187*/ 0x001006a3U, +/*0188*/ 0x101006a3U, +/*0189*/ 0x001006a4U, +/*018a*/ 0x100306a4U, +/*018b*/ 0x180406a4U, +/*018c*/ 0x000106a5U, +/*018d*/ 0x080806a5U, +/*018e*/ 0x100106a5U, +/*018f*/ 0x180506a5U, +/*0190*/ 0x000106a6U, +/*0191*/ 0x081406a6U, +/*0192*/ 0x000a06a7U, +/*0193*/ 0x100c06a7U, +/*0194*/ 0x001206a8U, +/*0195*/ 0x001406a9U, +/*0196*/ 0x001206aaU, +/*0197*/ 0x001106abU, +/*0198*/ 0x001106acU, +/*0199*/ 0x001206adU, +/*019a*/ 0x001206aeU, +/*019b*/ 0x001206afU, +/*019c*/ 0x001206b0U, +/*019d*/ 0x001206b1U, +/*019e*/ 0x001206b2U, +/*019f*/ 0x001206b3U, +/*01a0*/ 0x001206b4U, +/*01a1*/ 0x001206b5U, +/*01a2*/ 0x001206b6U, +/*01a3*/ 0x000e06b7U, +/*01a4*/ 0x100d06b7U, +/*01a5*/ 0x002006b8U, +/*01a6*/ 0x001706b9U, +/*01a7*/ 0x000906baU, +/*01a8*/ 0x100106baU, +/*01a9*/ 0x180106baU, +/*01aa*/ 0x002006bbU, +/*01ab*/ 0x000806bcU, +/*01ac*/ 0x080306bcU, +/*01ad*/ 0x100306bcU, +/*01ae*/ 0x001806bdU, +/*01af*/ 0x001806beU, +/*01b0*/ 0x180706beU, +/*01b1*/ 0x000506bfU, +/*01b2*/ 0x080806bfU, +/*01b3*/ 0x100806bfU, +/*01b4*/ 0x180806bfU, +/*01b5*/ 0x000106c0U, +/*01b6*/ 0x080106c0U, +/*01b7*/ 0x002006c1U, +/*01b8*/ 0xffffffffU, +/*01b9*/ 0xffffffffU, +/*01ba*/ 0xffffffffU, +/*01bb*/ 0xffffffffU, +/*01bc*/ 0xffffffffU, +/*01bd*/ 0xffffffffU, +/*01be*/ 0xffffffffU, +/*01bf*/ 0x001006c2U, +/*01c0*/ 0x100106c2U, +/*01c1*/ 0x180106c2U, +/*01c2*/ 0x000206c3U, +/*01c3*/ 0x080406c3U, +/*01c4*/ 0x100906c3U, +/*01c5*/ 0x000706c4U, +/*01c6*/ 0x080406c4U, +/*01c7*/ 0x002006c5U, +/*01c8*/ 0x000106c6U, +/*01c9*/ 0x080206c6U, +/*01ca*/ 0x100606c6U, +/*01cb*/ 0x001006c7U, +/*01cc*/ 0x100106c7U, +/*01cd*/ 0x002006c8U, +/*01ce*/ 0x000806c9U, +/*01cf*/ 0x080106c9U, +/*01d0*/ 0x100506c9U, +/*01d1*/ 0xffffffffU, +/*01d2*/ 0x180206c9U, +/*01d3*/ 0x000106caU, +/*01d4*/ 0x002006cbU, +/*01d5*/ 0x000b06ccU, +/*01d6*/ 0x100106ccU, +/*01d7*/ 0x180306ccU, +/*01d8*/ 0x000806cdU, +/*01d9*/ 0x080206cdU, +/*01da*/ 0x100c06cdU, +/*01db*/ 0x000406ceU, +/*01dc*/ 0x080106ceU, +/*01dd*/ 0xffffffffU, +/*01de*/ 0x00010200U, +/*01df*/ 0x08040200U, +/*01e0*/ 0x10100200U, +/*01e1*/ 0x00010201U, +/*01e2*/ 0x08010201U, +/*01e3*/ 0x10010201U, +/*01e4*/ 0xffffffffU, +/*01e5*/ 0x00100202U, +/*01e6*/ 0x10080202U, +/*01e7*/ 0xffffffffU, +/*01e8*/ 0xffffffffU, +/*01e9*/ 0xffffffffU, +/*01ea*/ 0xffffffffU, +/*01eb*/ 0xffffffffU, +/*01ec*/ 0xffffffffU, +/*01ed*/ 0xffffffffU, +/*01ee*/ 0xffffffffU, +/*01ef*/ 0x00200203U, +/*01f0*/ 0x00100204U, +/*01f1*/ 0x00200205U, +/*01f2*/ 0x00100206U, +/*01f3*/ 0x00200207U, +/*01f4*/ 0x00100208U, +/*01f5*/ 0x00140209U, +/*01f6*/ 0x0020020aU, +/*01f7*/ 0x0020020bU, +/*01f8*/ 0x0020020cU, +/*01f9*/ 0x0020020dU, +/*01fa*/ 0x0014020eU, +/*01fb*/ 0x0020020fU, +/*01fc*/ 0x00200210U, +/*01fd*/ 0x00200211U, +/*01fe*/ 0x00200212U, +/*01ff*/ 0x00140213U, +/*0200*/ 0x00200214U, +/*0201*/ 0x00200215U, +/*0202*/ 0x00200216U, +/*0203*/ 0x00200217U, +/*0204*/ 0x00090218U, +/*0205*/ 0x10010218U, +/*0206*/ 0x00200219U, +/*0207*/ 0x0005021aU, +/*0208*/ 0x0801021aU, +/*0209*/ 0x1008021aU, +/*020a*/ 0x1808021aU, +/*020b*/ 0x001c021bU, +/*020c*/ 0x001c021cU, +/*020d*/ 0x001c021dU, +/*020e*/ 0x001c021eU, +/*020f*/ 0x001c021fU, +/*0210*/ 0x001c0220U, +/*0211*/ 0x001c0221U, +/*0212*/ 0x001c0222U, +/*0213*/ 0x001c0223U, +/*0214*/ 0x001c0224U, +/*0215*/ 0x001c0225U, +/*0216*/ 0x001c0226U, +/*0217*/ 0x001c0227U, +/*0218*/ 0x001c0228U, +/*0219*/ 0x001c0229U, +/*021a*/ 0x001c022aU, +/*021b*/ 0x0001022bU, +/*021c*/ 0x0801022bU, +/*021d*/ 0x1001022bU, +/*021e*/ 0x1804022bU, +/*021f*/ 0x0008022cU, +/*0220*/ 0x0808022cU, +/*0221*/ 0x1008022cU, +/*0222*/ 0x1804022cU, +/*0223*/ 0x0007022dU, +/*0224*/ 0xffffffffU, +/*0225*/ 0x0807022dU, +/*0226*/ 0x1007022dU, +/*0227*/ 0xffffffffU, +/*0228*/ 0x1807022dU, +/*0229*/ 0x0007022eU, +/*022a*/ 0xffffffffU, +/*022b*/ 0x0807022eU, +/*022c*/ 0x1002022eU, +/*022d*/ 0x1801022eU, +/*022e*/ 0x0001022fU, +/*022f*/ 0x080a022fU, +/*0230*/ 0x00140230U, +/*0231*/ 0x000a0231U, +/*0232*/ 0x00140232U, +/*0233*/ 0x000a0233U, +/*0234*/ 0x00140234U, +/*0235*/ 0x18010234U, +/*0236*/ 0x00100235U, +/*0237*/ 0x10050235U, +/*0238*/ 0x18010235U, +/*0239*/ 0x00010236U, +/*023a*/ 0x08010236U, +/*023b*/ 0x10010236U, +/*023c*/ 0x18010236U, +/*023d*/ 0x00010237U, +/*023e*/ 0x08010237U, +/*023f*/ 0x10020237U, +/*0240*/ 0x18020237U, +/*0241*/ 0x00020238U, +/*0242*/ 0x08020238U, +/*0243*/ 0x10020238U, +/*0244*/ 0x18030238U, +/*0245*/ 0x00010239U, +/*0246*/ 0x08010239U, +/*0247*/ 0x10010239U, +/*0248*/ 0x18010239U, +/*0249*/ 0xffffffffU, +/*024a*/ 0x0002023aU, +/*024b*/ 0x0801023aU, +/*024c*/ 0x1001023aU, +/*024d*/ 0xffffffffU, +/*024e*/ 0x1802023aU, +/*024f*/ 0x0001023bU, +/*0250*/ 0x0801023bU, +/*0251*/ 0xffffffffU, +/*0252*/ 0x1002023bU, +/*0253*/ 0x1801023bU, +/*0254*/ 0x0001023cU, +/*0255*/ 0xffffffffU, +/*0256*/ 0x0802023cU, +/*0257*/ 0x1007023cU, +/*0258*/ 0x1801023cU, +/*0259*/ 0x0001023dU, +/*025a*/ 0x0801023dU, +/*025b*/ 0x1001023dU, +/*025c*/ 0x1801023dU, +/*025d*/ 0x0001023eU, +/*025e*/ 0x0801023eU, +/*025f*/ 0x1001023eU, +/*0260*/ 0x1804023eU, +/*0261*/ 0x0004023fU, +/*0262*/ 0x0804023fU, +/*0263*/ 0x1001023fU, +/*0264*/ 0x1802023fU, +/*0265*/ 0x00060240U, +/*0266*/ 0x08060240U, +/*0267*/ 0x10020240U, +/*0268*/ 0x18020240U, +/*0269*/ 0x00020241U, +/*026a*/ 0xffffffffU, +/*026b*/ 0x08100241U, +/*026c*/ 0x18010241U, +/*026d*/ 0x00010242U, +/*026e*/ 0x08010242U, +/*026f*/ 0x10040242U, +/*0270*/ 0x18010242U, +/*0271*/ 0x00040243U, +/*0272*/ 0x08020243U, +/*0273*/ 0x10080243U, +/*0274*/ 0xffffffffU, +/*0275*/ 0xffffffffU, +/*0276*/ 0xffffffffU, +/*0277*/ 0x000a0244U, +/*0278*/ 0x00200245U, +/*0279*/ 0x00200246U, +/*027a*/ 0x00050247U, +/*027b*/ 0x08010247U, +/*027c*/ 0x10050247U, +/*027d*/ 0x18080247U, +/*027e*/ 0x00010248U, +/*027f*/ 0x08080248U, +/*0280*/ 0x10010248U, +/*0281*/ 0x18080248U, +/*0282*/ 0x00010249U, +/*0283*/ 0x08040249U, +/*0284*/ 0x10040249U, +/*0285*/ 0x18040249U, +/*0286*/ 0x0004024aU, +/*0287*/ 0x0804024aU, +/*0288*/ 0x1004024aU, +/*0289*/ 0x1804024aU, +/*028a*/ 0x0004024bU, +/*028b*/ 0x0804024bU, +/*028c*/ 0x1004024bU, +/*028d*/ 0x1801024bU, +/*028e*/ 0x0004024cU, +/*028f*/ 0x0804024cU, +/*0290*/ 0x1004024cU, +/*0291*/ 0x1804024cU, +/*0292*/ 0x0004024dU, +/*0293*/ 0x0804024dU, +/*0294*/ 0x1006024dU, +/*0295*/ 0x1806024dU, +/*0296*/ 0x0006024eU, +/*0297*/ 0x0806024eU, +/*0298*/ 0x1006024eU, +/*0299*/ 0x1806024eU, +/*029a*/ 0xffffffffU, +/*029b*/ 0x0001024fU, +/*029c*/ 0x0801024fU, +/*029d*/ 0x1002024fU, +/*029e*/ 0xffffffffU, +/*029f*/ 0xffffffffU, +/*02a0*/ 0xffffffffU, +/*02a1*/ 0xffffffffU, +/*02a2*/ 0xffffffffU, +/*02a3*/ 0xffffffffU, +/*02a4*/ 0xffffffffU, +/*02a5*/ 0xffffffffU, +/*02a6*/ 0x1804024fU, +/*02a7*/ 0x00040250U, +/*02a8*/ 0x08010250U, +/*02a9*/ 0x10010250U, +/*02aa*/ 0x18010250U, +/*02ab*/ 0x00010251U, +/*02ac*/ 0x08010251U, +/*02ad*/ 0x10010251U, +/*02ae*/ 0x18010251U, +/*02af*/ 0x00010252U, +/*02b0*/ 0x08010252U, +/*02b1*/ 0x10040252U, +/*02b2*/ 0x18040252U, +/*02b3*/ 0x000a0253U, +/*02b4*/ 0x00200254U, +/*02b5*/ 0x00040255U, +/*02b6*/ 0x08080255U, +/*02b7*/ 0x10020255U, +/*02b8*/ 0x18020255U, +/*02b9*/ 0x00020256U, +/*02ba*/ 0x08020256U, +/*02bb*/ 0x10020256U, +/*02bc*/ 0x18020256U, +/*02bd*/ 0xffffffffU, +/*02be*/ 0xffffffffU, +/*02bf*/ 0x00200257U, +/*02c0*/ 0x00020258U, +/*02c1*/ 0x08100258U, +/*02c2*/ 0x00100259U, +/*02c3*/ 0x10040259U, +/*02c4*/ 0x18040259U, +/*02c5*/ 0x0005025aU, +/*02c6*/ 0x0805025aU, +/*02c7*/ 0x0020025bU, +/*02c8*/ 0x0020025cU, +/*02c9*/ 0x0020025dU, +/*02ca*/ 0x0020025eU, +/*02cb*/ 0x0001025fU, +/*02cc*/ 0x0801025fU, +/*02cd*/ 0x1007025fU, +/*02ce*/ 0x1807025fU, +/*02cf*/ 0x00070260U, +/*02d0*/ 0x08070260U, +/*02d1*/ 0x10070260U, +/*02d2*/ 0x18070260U, +/*02d3*/ 0x00070261U, +/*02d4*/ 0x08070261U, +/*02d5*/ 0x10070261U, +/*02d6*/ 0x18070261U, +/*02d7*/ 0x00070262U, +/*02d8*/ 0x08070262U, +/*02d9*/ 0x10070262U, +/*02da*/ 0x18070262U, +/*02db*/ 0x00030263U, +/*02dc*/ 0x08030263U, +/*02dd*/ 0x10030263U, +/*02de*/ 0xffffffffU, +/*02df*/ 0x18010263U, +/*02e0*/ 0x00020264U, +/*02e1*/ 0x08010264U, +/*02e2*/ 0x10040264U, +/*02e3*/ 0x18020264U, +/*02e4*/ 0x00010265U, +/*02e5*/ 0x08010265U, +/*02e6*/ 0x10010265U, +/*02e7*/ 0x18010265U, +/*02e8*/ 0x00040266U, +/*02e9*/ 0x08080266U, +/*02ea*/ 0x100a0266U, +/*02eb*/ 0x000a0267U, +/*02ec*/ 0x100a0267U, +/*02ed*/ 0x000a0268U, +/*02ee*/ 0x100a0268U, +/*02ef*/ 0x000a0269U, +/*02f0*/ 0x0020026aU, +/*02f1*/ 0x0020026bU, +/*02f2*/ 0x0001026cU, +/*02f3*/ 0x0802026cU, +/*02f4*/ 0x1002026cU, +/*02f5*/ 0x1802026cU, +/*02f6*/ 0xffffffffU, +/*02f7*/ 0x0002026dU, +/*02f8*/ 0x0810026dU, +/*02f9*/ 0x1805026dU, +/*02fa*/ 0x0006026eU, +/*02fb*/ 0x0805026eU, +/*02fc*/ 0x1005026eU, +/*02fd*/ 0x000e026fU, +/*02fe*/ 0x1005026fU, +/*02ff*/ 0x000e0270U, +/*0300*/ 0x10050270U, +/*0301*/ 0x000e0271U, +/*0302*/ 0x10050271U, +/*0303*/ 0x18010271U, +/*0304*/ 0x00050272U, +/*0305*/ 0x08050272U, +/*0306*/ 0x100a0272U, +/*0307*/ 0x000a0273U, +/*0308*/ 0x10050273U, +/*0309*/ 0x18050273U, +/*030a*/ 0x000a0274U, +/*030b*/ 0x100a0274U, +/*030c*/ 0x00050275U, +/*030d*/ 0x08050275U, +/*030e*/ 0x100a0275U, +/*030f*/ 0x000a0276U, +/*0310*/ 0xffffffffU, +/*0311*/ 0xffffffffU, +/*0312*/ 0xffffffffU, +/*0313*/ 0xffffffffU, +/*0314*/ 0xffffffffU, +/*0315*/ 0xffffffffU, +/*0316*/ 0x10070276U, +/*0317*/ 0x18070276U, +/*0318*/ 0x00040277U, +/*0319*/ 0x08040277U, +/*031a*/ 0xffffffffU, +/*031b*/ 0xffffffffU, +/*031c*/ 0xffffffffU, +/*031d*/ 0x10040277U, +/*031e*/ 0x18080277U, +/*031f*/ 0x00080278U, +/*0320*/ 0x08040278U, +/*0321*/ 0xffffffffU, +/*0322*/ 0xffffffffU, +/*0323*/ 0xffffffffU, +/*0324*/ 0x10040278U, +/*0325*/ 0xffffffffU, +/*0326*/ 0xffffffffU, +/*0327*/ 0xffffffffU, +/*0328*/ 0x18040278U, +/*0329*/ 0xffffffffU, +/*032a*/ 0xffffffffU, +/*032b*/ 0xffffffffU, +/*032c*/ 0x00040279U, +/*032d*/ 0x08050279U, +/*032e*/ 0x10070279U, +/*032f*/ 0x18080279U, +/*0330*/ 0x0010027aU, +/*0331*/ 0x1008027aU, +/*0332*/ 0x0010027bU, +/*0333*/ 0x1008027bU, +/*0334*/ 0x0010027cU, +/*0335*/ 0x1008027cU, +/*0336*/ 0x1808027cU, +/*0337*/ 0x0001027dU, +/*0338*/ 0x0801027dU, +/*0339*/ 0x1006027dU, +/*033a*/ 0x1806027dU, +/*033b*/ 0x0006027eU, +/*033c*/ 0x0801027eU, +/*033d*/ 0x1001027eU, +/*033e*/ 0x1803027eU, +/*033f*/ 0x000a027fU, +/*0340*/ 0x100a027fU, +/*0341*/ 0x000a0280U, +/*0342*/ 0xffffffffU, +/*0343*/ 0x100a0280U, +/*0344*/ 0x00040281U, +/*0345*/ 0x08010281U, +/*0346*/ 0x10040281U, +/*0347*/ 0xffffffffU, +/*0348*/ 0xffffffffU, +/*0349*/ 0xffffffffU, +/*034a*/ 0xffffffffU, +/*034b*/ 0xffffffffU, +/*034c*/ 0xffffffffU, +/*034d*/ 0x18070281U, +/*034e*/ 0x00070282U, +/*034f*/ 0x08050282U, +/*0350*/ 0x10050282U, +/*0351*/ 0xffffffffU, +/*0352*/ 0xffffffffU, +/*0353*/ 0xffffffffU, +/*0354*/ 0x18040282U, +/*0355*/ 0x00010283U, +/*0356*/ 0x08010283U, +/*0357*/ 0x10020283U, +/*0358*/ 0x18080283U, +/*0359*/ 0x00200284U, +/*035a*/ 0x00200285U, +/*035b*/ 0x00100286U, +/*035c*/ 0x10020286U, +/*035d*/ 0x18020286U, +/*035e*/ 0x00020287U, +/*035f*/ 0xffffffffU, +/*0360*/ 0x08010287U, +/*0361*/ 0x10010287U, +/*0362*/ 0x18020287U, +/*0363*/ 0x00080288U, +/*0364*/ 0x08080288U, +/*0365*/ 0x10080288U, +/*0366*/ 0x18080288U, +/*0367*/ 0x00080289U, +/*0368*/ 0x08080289U, +/*0369*/ 0xffffffffU, +/*036a*/ 0x10080289U, +/*036b*/ 0x18080289U, +/*036c*/ 0x0008028aU, +/*036d*/ 0x0808028aU, +/*036e*/ 0x1008028aU, +/*036f*/ 0x1808028aU, +/*0370*/ 0xffffffffU, +/*0371*/ 0x0008028bU, +/*0372*/ 0x0808028bU, +/*0373*/ 0x1008028bU, +/*0374*/ 0x1808028bU, +/*0375*/ 0x0008028cU, +/*0376*/ 0x0808028cU, +/*0377*/ 0xffffffffU, +/*0378*/ 0x1008028cU, +/*0379*/ 0x1808028cU, +/*037a*/ 0x0008028dU, +/*037b*/ 0x0808028dU, +/*037c*/ 0x1008028dU, +/*037d*/ 0x1808028dU, +/*037e*/ 0x0008028eU, +/*037f*/ 0xffffffffU, +/*0380*/ 0x0808028eU, +/*0381*/ 0x1008028eU, +/*0382*/ 0x1808028eU, +/*0383*/ 0x0008028fU, +/*0384*/ 0x0808028fU, +/*0385*/ 0x1008028fU, +/*0386*/ 0xffffffffU, +/*0387*/ 0x1808028fU, +/*0388*/ 0x00080290U, +/*0389*/ 0x08080290U, +/*038a*/ 0x10080290U, +/*038b*/ 0x18080290U, +/*038c*/ 0x00080291U, +/*038d*/ 0xffffffffU, +/*038e*/ 0x08080291U, +/*038f*/ 0x10080291U, +/*0390*/ 0x18080291U, +/*0391*/ 0x00080292U, +/*0392*/ 0x08080292U, +/*0393*/ 0x10080292U, +/*0394*/ 0x18080292U, +/*0395*/ 0xffffffffU, +/*0396*/ 0x00080293U, +/*0397*/ 0x08080293U, +/*0398*/ 0x10080293U, +/*0399*/ 0x18080293U, +/*039a*/ 0x00080294U, +/*039b*/ 0x08080294U, +/*039c*/ 0xffffffffU, +/*039d*/ 0x10080294U, +/*039e*/ 0x18080294U, +/*039f*/ 0x00080295U, +/*03a0*/ 0x08080295U, +/*03a1*/ 0x10080295U, +/*03a2*/ 0x18080295U, +/*03a3*/ 0xffffffffU, +/*03a4*/ 0x00080296U, +/*03a5*/ 0x08080296U, +/*03a6*/ 0x10080296U, +/*03a7*/ 0x18080296U, +/*03a8*/ 0x00080297U, +/*03a9*/ 0x08080297U, +/*03aa*/ 0x10080297U, +/*03ab*/ 0xffffffffU, +/*03ac*/ 0x18080297U, +/*03ad*/ 0x00080298U, +/*03ae*/ 0x08080298U, +/*03af*/ 0x10080298U, +/*03b0*/ 0x18080298U, +/*03b1*/ 0x00080299U, +/*03b2*/ 0xffffffffU, +/*03b3*/ 0x08080299U, +/*03b4*/ 0x10080299U, +/*03b5*/ 0x18080299U, +/*03b6*/ 0x0008029aU, +/*03b7*/ 0x0808029aU, +/*03b8*/ 0x1008029aU, +/*03b9*/ 0xffffffffU, +/*03ba*/ 0x1808029aU, +/*03bb*/ 0x0002029bU, +/*03bc*/ 0x0803029bU, +/*03bd*/ 0x100a029bU, +/*03be*/ 0x000a029cU, +/*03bf*/ 0x100a029cU, +/*03c0*/ 0x0005029dU, +/*03c1*/ 0x0808029dU, +/*03c2*/ 0x1008029dU, +/*03c3*/ 0x1808029dU, +/*03c4*/ 0x0006029eU, +/*03c5*/ 0x0806029eU, +/*03c6*/ 0x0011029fU, +/*03c7*/ 0x1808029fU, +/*03c8*/ 0x000402a0U, +/*03c9*/ 0x080602a0U, +/*03ca*/ 0xffffffffU, +/*03cb*/ 0x100602a0U, +/*03cc*/ 0x180802a0U, +/*03cd*/ 0xffffffffU, +/*03ce*/ 0x000802a1U, +/*03cf*/ 0x080802a1U, +/*03d0*/ 0x100802a1U, +/*03d1*/ 0x180602a1U, +/*03d2*/ 0x000602a2U, +/*03d3*/ 0x081102a2U, +/*03d4*/ 0x000802a3U, +/*03d5*/ 0x080402a3U, +/*03d6*/ 0x100602a3U, +/*03d7*/ 0xffffffffU, +/*03d8*/ 0x180602a3U, +/*03d9*/ 0x000802a4U, +/*03da*/ 0xffffffffU, +/*03db*/ 0x080802a4U, +/*03dc*/ 0x100802a4U, +/*03dd*/ 0x180802a4U, +/*03de*/ 0x000602a5U, +/*03df*/ 0x080602a5U, +/*03e0*/ 0x001102a6U, +/*03e1*/ 0x180802a6U, +/*03e2*/ 0x000402a7U, +/*03e3*/ 0x080602a7U, +/*03e4*/ 0xffffffffU, +/*03e5*/ 0x100602a7U, +/*03e6*/ 0x180802a7U, +/*03e7*/ 0xffffffffU, +/*03e8*/ 0x000402a8U, +/*03e9*/ 0x080402a8U, +/*03ea*/ 0x100402a8U, +/*03eb*/ 0x180402a8U, +/*03ec*/ 0x000402a9U, +/*03ed*/ 0x080402a9U, +/*03ee*/ 0x100402a9U, +/*03ef*/ 0x180402a9U, +/*03f0*/ 0x000402aaU, +/*03f1*/ 0x080402aaU, +/*03f2*/ 0x100402aaU, +/*03f3*/ 0x180402aaU, +/*03f4*/ 0x000402abU, +/*03f5*/ 0x080402abU, +/*03f6*/ 0x100402abU, +/*03f7*/ 0x180402abU, +/*03f8*/ 0x000402acU, +/*03f9*/ 0x080402acU, +/*03fa*/ 0x100402acU, +/*03fb*/ 0x180402acU, +/*03fc*/ 0x001202adU, +/*03fd*/ 0x001102aeU, +/*03fe*/ 0x001202afU, +/*03ff*/ 0x002002b0U, +/*0400*/ 0x002002b1U, +/*0401*/ 0x002002b2U, +/*0402*/ 0x002002b3U, +/*0403*/ 0x002002b4U, +/*0404*/ 0x002002b5U, +/*0405*/ 0x002002b6U, +/*0406*/ 0x002002b7U, +/*0407*/ 0x002002b8U, +/*0408*/ 0x000202b9U, +/*0409*/ 0x080502b9U, +/*040a*/ 0x100502b9U, +/*040b*/ 0x180102b9U, +/*040c*/ 0x000402baU, +/*040d*/ 0x080402baU, +/*040e*/ 0x100402baU, +/*040f*/ 0x180402baU, +/*0410*/ 0x000402bbU, +/*0411*/ 0x080402bbU, +/*0412*/ 0x100402bbU, +/*0413*/ 0x180402bbU, +/*0414*/ 0xffffffffU, +/*0415*/ 0xffffffffU, +/*0416*/ 0xffffffffU, +/*0417*/ 0xffffffffU, +/*0418*/ 0xffffffffU, +/*0419*/ 0xffffffffU, +/*041a*/ 0x000402bcU, +/*041b*/ 0x080402bcU, +/*041c*/ 0x100402bcU, +/*041d*/ 0x180402bcU, +/*041e*/ 0x000402bdU, +/*041f*/ 0x080402bdU, +/*0420*/ 0x100402bdU, +/*0421*/ 0x180402bdU, +/*0422*/ 0x000102beU, +/*0423*/ 0x080202beU, +/*0424*/ 0x100202beU, +/*0425*/ 0x180202beU, +/*0426*/ 0x000202bfU, +/*0427*/ 0x080102bfU, +/*0428*/ 0x100402bfU, +/*0429*/ 0x001002c0U, +/*042a*/ 0x002002c1U, +/*042b*/ 0x001002c2U, +/*042c*/ 0x002002c3U, +/*042d*/ 0x001002c4U, +/*042e*/ 0x002002c5U, +/*042f*/ 0x000702c6U, +/*0430*/ 0x080102c6U, +/*0431*/ 0x100202c6U, +/*0432*/ 0x180602c6U, +/*0433*/ 0x000102c7U, +/*0434*/ 0x080102c7U, +/*0435*/ 0x002002c8U, +/*0436*/ 0x000202c9U, +/*0437*/ 0x002002caU, +/*0438*/ 0x002002cbU, +/*0439*/ 0x000c02ccU, +/*043a*/ 0x100c02ccU, +/*043b*/ 0x002002cdU, +/*043c*/ 0x000302ceU, +/*043d*/ 0x002002cfU, +/*043e*/ 0x000302d0U, +/*043f*/ 0x002002d1U, +/*0440*/ 0x000302d2U, +/*0441*/ 0x002002d3U, +/*0442*/ 0x000302d4U, +/*0443*/ 0x002002d5U, +/*0444*/ 0x000302d6U, +/*0445*/ 0x002002d7U, +/*0446*/ 0x000302d8U, +/*0447*/ 0x002002d9U, +/*0448*/ 0x000302daU, +/*0449*/ 0x002002dbU, +/*044a*/ 0x000302dcU, +/*044b*/ 0x002002ddU, +/*044c*/ 0x000302deU, +/*044d*/ 0x002002dfU, +/*044e*/ 0x000302e0U, +/*044f*/ 0x080302e0U, +/*0450*/ 0x100202e0U, +/*0451*/ 0x180202e0U, +/*0452*/ 0x002002e1U, +/*0453*/ 0x002002e2U, +/*0454*/ 0x002002e3U, +/*0455*/ 0x002002e4U, +/*0456*/ 0x000402e5U, +/*0457*/ 0x001e02e6U, +/*0458*/ 0x001e02e7U, +/*0459*/ 0x001e02e8U, +/*045a*/ 0x001e02e9U, +/*045b*/ 0x001e02eaU, +/*045c*/ 0x001e02ebU, +/*045d*/ 0x001e02ecU, +/*045e*/ 0x001e02edU, +/*045f*/ 0x000402eeU, +/*0460*/ 0xffffffffU, +/*0461*/ 0xffffffffU, +/*0462*/ 0xffffffffU, +/*0463*/ 0xffffffffU, +/*0464*/ 0x080402eeU, +/*0465*/ 0x100102eeU, +/*0466*/ 0x180802eeU, +/*0467*/ 0x000402efU, +/*0468*/ 0x080102efU, +/*0469*/ 0x100802efU, +/*046a*/ 0x180402efU, +/*046b*/ 0x000102f0U, +/*046c*/ 0x080802f0U, +/*046d*/ 0x100402f0U, +/*046e*/ 0x180102f0U, +/*046f*/ 0x000802f1U, +/*0470*/ 0x080402f1U, +/*0471*/ 0x100102f1U, +/*0472*/ 0x180802f1U, +/*0473*/ 0x000402f2U, +/*0474*/ 0x080102f2U, +/*0475*/ 0x100802f2U, +/*0476*/ 0x180402f2U, +/*0477*/ 0x000102f3U, +/*0478*/ 0x080802f3U, +/*0479*/ 0x100402f3U, +/*047a*/ 0x180102f3U, +/*047b*/ 0x000802f4U, +/*047c*/ 0x080802f4U, +/*047d*/ 0x100102f4U, +/*047e*/ 0x180502f4U, +/*047f*/ 0xffffffffU, +/*0480*/ 0xffffffffU, +/*0481*/ 0xffffffffU, +/*0482*/ 0xffffffffU, +/*0483*/ 0xffffffffU, +/*0484*/ 0xffffffffU, +/*0485*/ 0xffffffffU, +/*0486*/ 0xffffffffU, +/*0487*/ 0xffffffffU, +/*0488*/ 0xffffffffU, +/*0489*/ 0xffffffffU, +/*048a*/ 0xffffffffU, +/*048b*/ 0xffffffffU, +/*048c*/ 0xffffffffU, +/*048d*/ 0xffffffffU, +/*048e*/ 0xffffffffU, +/*048f*/ 0xffffffffU, +/*0490*/ 0xffffffffU, +/*0491*/ 0xffffffffU, +/*0492*/ 0xffffffffU, +/*0493*/ 0xffffffffU, +/*0494*/ 0xffffffffU, + }, + { +/*0000*/ 0x00200800U, +/*0001*/ 0x00040801U, +/*0002*/ 0x080b0801U, +/*0003*/ 0x000a0802U, +/*0004*/ 0x10020802U, +/*0005*/ 0x18010802U, +/*0006*/ 0x00060803U, +/*0007*/ 0x08060803U, +/*0008*/ 0x10060803U, +/*0009*/ 0x18060803U, +/*000a*/ 0x00060804U, +/*000b*/ 0x08060804U, +/*000c*/ 0x10050804U, +/*000d*/ 0x18060804U, +/*000e*/ 0x00060805U, +/*000f*/ 0x08040805U, +/*0010*/ 0x10030805U, +/*0011*/ 0x00180806U, +/*0012*/ 0x18030806U, +/*0013*/ 0x00180807U, +/*0014*/ 0x18020807U, +/*0015*/ 0x0801085eU, +/*0016*/ 0x00020808U, +/*0017*/ 0x08010808U, +/*0018*/ 0x10010808U, +/*0019*/ 0x18020808U, +/*001a*/ 0x00050809U, +/*001b*/ 0x08050809U, +/*001c*/ 0x10040809U, +/*001d*/ 0xffffffffU, +/*001e*/ 0x18040809U, +/*001f*/ 0x0002080aU, +/*0020*/ 0x0805080aU, +/*0021*/ 0x1009080aU, +/*0022*/ 0x0001080bU, +/*0023*/ 0x0020080cU, +/*0024*/ 0x001c080dU, +/*0025*/ 0x0001080eU, +/*0026*/ 0x0807080eU, +/*0027*/ 0x1009080eU, +/*0028*/ 0x000a080fU, +/*0029*/ 0x1005080fU, +/*002a*/ 0x1801080fU, +/*002b*/ 0x10010810U, +/*002c*/ 0x18020810U, +/*002d*/ 0x00090810U, +/*002e*/ 0x00090811U, +/*002f*/ 0x10020811U, +/*0030*/ 0x00200812U, +/*0031*/ 0x00010813U, +/*0032*/ 0x08020813U, +/*0033*/ 0x00200814U, +/*0034*/ 0x00200815U, +/*0035*/ 0x00200816U, +/*0036*/ 0x00200817U, +/*0037*/ 0xffffffffU, +/*0038*/ 0xffffffffU, +/*0039*/ 0xffffffffU, +/*003a*/ 0xffffffffU, +/*003b*/ 0x00030818U, +/*003c*/ 0x08010818U, +/*003d*/ 0x10040818U, +/*003e*/ 0x18030818U, +/*003f*/ 0x00040819U, +/*0040*/ 0x08040819U, +/*0041*/ 0x10040819U, +/*0042*/ 0x18040819U, +/*0043*/ 0x0001081aU, +/*0044*/ 0x0801081aU, +/*0045*/ 0x1006081aU, +/*0046*/ 0x1804081aU, +/*0047*/ 0x0008081bU, +/*0048*/ 0x0806081bU, +/*0049*/ 0x1004081bU, +/*004a*/ 0x1806081bU, +/*004b*/ 0x0004081cU, +/*004c*/ 0x0802081cU, +/*004d*/ 0x1005081cU, +/*004e*/ 0x1808081cU, +/*004f*/ 0xffffffffU, +/*0050*/ 0x0006081dU, +/*0051*/ 0x0803081dU, +/*0052*/ 0x100b081dU, +/*0053*/ 0x0004081eU, +/*0054*/ 0x0804081eU, +/*0055*/ 0x1004081eU, +/*0056*/ 0x1801081eU, +/*0057*/ 0xffffffffU, +/*0058*/ 0x0009081fU, +/*0059*/ 0x00200820U, +/*005a*/ 0x00200821U, +/*005b*/ 0x00200822U, +/*005c*/ 0x00200823U, +/*005d*/ 0x00100824U, +/*005e*/ 0xffffffffU, +/*005f*/ 0x10010824U, +/*0060*/ 0x18060824U, +/*0061*/ 0x00080825U, +/*0062*/ 0x00200826U, +/*0063*/ 0x00100827U, +/*0064*/ 0x100b0827U, +/*0065*/ 0x00070828U, +/*0066*/ 0x08070828U, +/*0067*/ 0x10090828U, +/*0068*/ 0x00090829U, +/*0069*/ 0x100b0829U, +/*006a*/ 0x0007082aU, +/*006b*/ 0x0808082aU, +/*006c*/ 0x1009082aU, +/*006d*/ 0x0003082bU, +/*006e*/ 0x080a082bU, +/*006f*/ 0x000a082cU, +/*0070*/ 0x0011082dU, +/*0071*/ 0x000a082eU, +/*0072*/ 0x100a082eU, +/*0073*/ 0x0010082fU, +/*0074*/ 0x100e082fU, +/*0075*/ 0x000e0830U, +/*0076*/ 0x00120831U, +/*0077*/ 0x000a0832U, +/*0078*/ 0x100a0832U, +/*0079*/ 0x00020833U, +/*007a*/ 0x00200834U, +/*007b*/ 0x000b0835U, +/*007c*/ 0x100b0835U, +/*007d*/ 0x00200836U, +/*007e*/ 0x00130837U, +/*007f*/ 0x00200838U, +/*0080*/ 0x00200839U, +/*0081*/ 0x0008083aU, +/*0082*/ 0x0801083aU, +/*0083*/ 0x1001083aU, +/*0084*/ 0x1801083aU, +/*0085*/ 0x0008083bU, +/*0086*/ 0x080c083bU, +/*0087*/ 0x000c083cU, +/*0088*/ 0x100c083cU, +/*0089*/ 0x000c083dU, +/*008a*/ 0x100c083dU, +/*008b*/ 0x000c083eU, +/*008c*/ 0x100c083eU, +/*008d*/ 0x000c083fU, +/*008e*/ 0x100c083fU, +/*008f*/ 0x000c0840U, +/*0090*/ 0x100c0840U, +/*0091*/ 0x000b0841U, +/*0092*/ 0x10090841U, +/*0093*/ 0x00010842U, +/*0094*/ 0x000b0843U, +/*0095*/ 0x100b0843U, +/*0096*/ 0x000b0844U, +/*0097*/ 0x100b0844U, +/*0098*/ 0x000b0845U, +/*0099*/ 0x100b0845U, +/*009a*/ 0x000b0846U, +/*009b*/ 0x100b0846U, +/*009c*/ 0x000b0847U, +/*009d*/ 0x100a0847U, +/*009e*/ 0x00020848U, +/*009f*/ 0x080a0848U, +/*00a0*/ 0x000a0849U, +/*00a1*/ 0x100a0849U, +/*00a2*/ 0x000a084aU, +/*00a3*/ 0x100a084aU, +/*00a4*/ 0x000a084bU, +/*00a5*/ 0x100a084bU, +/*00a6*/ 0x000a084cU, +/*00a7*/ 0x100a084cU, +/*00a8*/ 0x000a084dU, +/*00a9*/ 0x100a084dU, +/*00aa*/ 0x000a084eU, +/*00ab*/ 0x100a084eU, +/*00ac*/ 0x000a084fU, +/*00ad*/ 0x100a084fU, +/*00ae*/ 0x000a0850U, +/*00af*/ 0x100a0850U, +/*00b0*/ 0x000a0851U, +/*00b1*/ 0x100a0851U, +/*00b2*/ 0x000a0852U, +/*00b3*/ 0x100a0852U, +/*00b4*/ 0x000a0853U, +/*00b5*/ 0x100a0853U, +/*00b6*/ 0x000a0854U, +/*00b7*/ 0x100a0854U, +/*00b8*/ 0x000a0855U, +/*00b9*/ 0x100a0855U, +/*00ba*/ 0x000a0856U, +/*00bb*/ 0x10040856U, +/*00bc*/ 0x18030856U, +/*00bd*/ 0x000a0857U, +/*00be*/ 0x100a0857U, +/*00bf*/ 0x00010858U, +/*00c0*/ 0x080a0858U, +/*00c1*/ 0x18040858U, +/*00c2*/ 0x000b0859U, +/*00c3*/ 0x100a0859U, +/*00c4*/ 0x0003085aU, +/*00c5*/ 0x0008085bU, +/*00c6*/ 0x0808085bU, +/*00c7*/ 0x1008085bU, +/*00c8*/ 0x1808085bU, +/*00c9*/ 0x0008085cU, +/*00ca*/ 0x0808085cU, +/*00cb*/ 0x1008085cU, +/*00cc*/ 0x1801085cU, +/*00cd*/ 0x0008085dU, +/*00ce*/ 0x0808085dU, +/*00cf*/ 0x1002085dU, +/*00d0*/ 0x1802085dU, +/*00d1*/ 0x0005085eU, +/*00d2*/ 0x1005085eU, +/*00d3*/ 0x1805085eU, +/*00d4*/ 0x0004085fU, +/*00d5*/ 0x080b085fU, +/*00d6*/ 0x1806085fU, +/*00d7*/ 0x00080860U, +/*00d8*/ 0x08080860U, +/*00d9*/ 0x10040860U, +/*00da*/ 0x18040860U, +/*00db*/ 0x00060861U, +/*00dc*/ 0x08040861U, +/*00dd*/ 0x10050861U, +/*00de*/ 0x000a0862U, +/*00df*/ 0x100a0862U, +/*00e0*/ 0x00080863U, +/*00e1*/ 0x08010863U, +/*00e2*/ 0x10040863U, +/*00e3*/ 0x00020864U, +/*00e4*/ 0x08030864U, +/*00e5*/ 0x00050a00U, +/*00e6*/ 0x08050a00U, +/*00e7*/ 0x10050a00U, +/*00e8*/ 0x18050a00U, +/*00e9*/ 0x00050a01U, +/*00ea*/ 0x08050a01U, +/*00eb*/ 0x100b0a01U, +/*00ec*/ 0x00010a02U, +/*00ed*/ 0x08030a02U, +/*00ee*/ 0x00200a03U, +/*00ef*/ 0x00100a04U, +/*00f0*/ 0x10040a04U, +/*00f1*/ 0x000b0a05U, +/*00f2*/ 0x10070a05U, +/*00f3*/ 0x00090a06U, +/*00f4*/ 0x10030a06U, +/*00f5*/ 0x18030a06U, +/*00f6*/ 0x00010a07U, +/*00f7*/ 0x08010a07U, +/*00f8*/ 0x10070a07U, +/*00f9*/ 0x18070a07U, +/*00fa*/ 0x00050a08U, +/*00fb*/ 0x08010a08U, +/*00fc*/ 0x10020a08U, +/*00fd*/ 0x18030a08U, +/*00fe*/ 0x00010a09U, +/*00ff*/ 0x080f0a09U, +/*0100*/ 0x00200a0aU, +/*0101*/ 0x00200a0bU, +/*0102*/ 0x000b0a0cU, +/*0103*/ 0x100b0a0cU, +/*0104*/ 0x000b0a0dU, +/*0105*/ 0x00180a0eU, +/*0106*/ 0x00180a0fU, +/*0107*/ 0xffffffffU, +/*0108*/ 0xffffffffU, +/*0109*/ 0xffffffffU, +/*010a*/ 0xffffffffU, +/*010b*/ 0xffffffffU, +/*010c*/ 0x18020a0fU, +/*010d*/ 0x00020a10U, +/*010e*/ 0x08040a10U, +/*010f*/ 0x10040a10U, +/*0110*/ 0x18010a10U, +/*0111*/ 0x00010a11U, +/*0112*/ 0x08010a11U, +/*0113*/ 0x10030a11U, +/*0114*/ 0x00200a12U, +/*0115*/ 0x00200a13U, +/*0116*/ 0xffffffffU, +/*0117*/ 0x00140a14U, +/*0118*/ 0x00140a15U, +/*0119*/ 0x00140a16U, +/*011a*/ 0x00140a17U, +/*011b*/ 0x00140a18U, +/*011c*/ 0x00140a19U, +/*011d*/ 0x00140a1aU, +/*011e*/ 0x00140a1bU, +/*011f*/ 0x001e0a1cU, +/*0120*/ 0x000a0a1dU, +/*0121*/ 0x10060a1dU, +/*0122*/ 0x18060a1dU, +/*0123*/ 0x00060a1eU, +/*0124*/ 0x08060a1eU, +/*0125*/ 0x10060a1eU, +/*0126*/ 0x00080a1fU, +/*0127*/ 0x080b0a1fU, +/*0128*/ 0x000b0a20U, +/*0129*/ 0x100b0a20U, +/*012a*/ 0x000b0a21U, +/*012b*/ 0x100b0a21U, +/*012c*/ 0x000b0a22U, +/*012d*/ 0x10040a22U, +/*012e*/ 0x000b0a23U, +/*012f*/ 0x10060a23U, +/*0130*/ 0x18080a23U, +/*0131*/ 0x00080a24U, +/*0132*/ 0x08040a24U, +/*0133*/ 0x00020b80U, +/*0134*/ 0x00010b81U, +/*0135*/ 0x08010b81U, +/*0136*/ 0x10020b81U, +/*0137*/ 0x18050b81U, +/*0138*/ 0x00050b82U, +/*0139*/ 0x08050b82U, +/*013a*/ 0x10050b82U, +/*013b*/ 0x000b0b83U, +/*013c*/ 0x10050b83U, +/*013d*/ 0x18010b83U, +/*013e*/ 0x00010b84U, +/*013f*/ 0x08010b84U, +/*0140*/ 0x10010b84U, +/*0141*/ 0x18010b84U, +/*0142*/ 0x00040b85U, +/*0143*/ 0x080b0b85U, +/*0144*/ 0x000b0b86U, +/*0145*/ 0x100b0b86U, +/*0146*/ 0x00040b87U, +/*0147*/ 0x080b0b87U, +/*0148*/ 0x18040b87U, +/*0149*/ 0x00010b88U, +/*014a*/ 0x08010b88U, +/*014b*/ 0x10010b88U, +/*014c*/ 0x00200b89U, +/*014d*/ 0x00200b8aU, +/*014e*/ 0x00080b8bU, +/*014f*/ 0x080a0b8bU, +/*0150*/ 0x18050b8bU, +/*0151*/ 0x000b0b8cU, +/*0152*/ 0x10030b8cU, +/*0153*/ 0x18030b8cU, +/*0154*/ 0x00010b8dU, +/*0155*/ 0x08020b8dU, +/*0156*/ 0x10010b8dU, +/*0157*/ 0x18010b8dU, +/*0158*/ 0x00010b8eU, +/*0159*/ 0xffffffffU, +/*015a*/ 0x08010b8eU, +/*015b*/ 0x18040b8eU, +/*015c*/ 0x00040b8fU, +/*015d*/ 0x08040b8fU, +/*015e*/ 0x10040b8fU, +/*015f*/ 0x18010b8fU, +/*0160*/ 0x00010b90U, +/*0161*/ 0x08010b90U, +/*0162*/ 0x00200b91U, +/*0163*/ 0x00200b92U, +/*0164*/ 0x00200b93U, +/*0165*/ 0x00200b94U, +/*0166*/ 0xffffffffU, +/*0167*/ 0x10010b8eU, +/*0168*/ 0x000d0b96U, +/*0169*/ 0x100d0b96U, +/*016a*/ 0x000d0b97U, +/*016b*/ 0x00050b98U, +/*016c*/ 0x00010b99U, +/*016d*/ 0x080e0b99U, +/*016e*/ 0x000e0b9aU, +/*016f*/ 0x100e0b9aU, +/*0170*/ 0x000e0b9bU, +/*0171*/ 0x100e0b9bU, +/*0172*/ 0x00040b9cU, +/*0173*/ 0x08040b9cU, +/*0174*/ 0x10040b9cU, +/*0175*/ 0x18040b9cU, +/*0176*/ 0x00040b9dU, +/*0177*/ 0x080b0b9dU, +/*0178*/ 0x000b0b9eU, +/*0179*/ 0x100b0b9eU, +/*017a*/ 0x000b0b9fU, +/*017b*/ 0x00040ba0U, +/*017c*/ 0x08040ba0U, +/*017d*/ 0x10040ba0U, +/*017e*/ 0x18040ba0U, +/*017f*/ 0x000d0ba1U, +/*0180*/ 0x100d0ba1U, +/*0181*/ 0x000d0ba2U, +/*0182*/ 0x10100ba2U, +/*0183*/ 0x00080b95U, +/*0184*/ 0x08080b95U, +/*0185*/ 0x00100ba3U, +/*0186*/ 0x10100ba3U, +/*0187*/ 0x00100ba4U, +/*0188*/ 0x10100ba4U, +/*0189*/ 0x00100ba5U, +/*018a*/ 0x10030ba5U, +/*018b*/ 0x18040ba5U, +/*018c*/ 0x00010ba6U, +/*018d*/ 0x08080ba6U, +/*018e*/ 0x10010ba6U, +/*018f*/ 0x000a0ba7U, +/*0190*/ 0x10010ba7U, +/*0191*/ 0x00140ba8U, +/*0192*/ 0x000b0ba9U, +/*0193*/ 0x100c0ba9U, +/*0194*/ 0x00120baaU, +/*0195*/ 0x00140babU, +/*0196*/ 0x00120bacU, +/*0197*/ 0x00110badU, +/*0198*/ 0x00110baeU, +/*0199*/ 0x00120bafU, +/*019a*/ 0x00120bb0U, +/*019b*/ 0x00120bb1U, +/*019c*/ 0x00120bb2U, +/*019d*/ 0x00120bb3U, +/*019e*/ 0x00120bb4U, +/*019f*/ 0x00120bb5U, +/*01a0*/ 0x00120bb6U, +/*01a1*/ 0x00120bb7U, +/*01a2*/ 0x00120bb8U, +/*01a3*/ 0x000e0bb9U, +/*01a4*/ 0x100d0bb9U, +/*01a5*/ 0x00200bbaU, +/*01a6*/ 0x00170bbbU, +/*01a7*/ 0x000d0bbcU, +/*01a8*/ 0x10010bbcU, +/*01a9*/ 0x18010bbcU, +/*01aa*/ 0x00200bbdU, +/*01ab*/ 0x00080bbeU, +/*01ac*/ 0x08030bbeU, +/*01ad*/ 0x10030bbeU, +/*01ae*/ 0x00180bbfU, +/*01af*/ 0x00180bc0U, +/*01b0*/ 0x18070bc0U, +/*01b1*/ 0x00070bc1U, +/*01b2*/ 0x08080bc1U, +/*01b3*/ 0x10080bc1U, +/*01b4*/ 0x18080bc1U, +/*01b5*/ 0x00010bc2U, +/*01b6*/ 0x08010bc2U, +/*01b7*/ 0x00200bc3U, +/*01b8*/ 0x00070bc4U, +/*01b9*/ 0x08140bc4U, +/*01ba*/ 0x00140bc5U, +/*01bb*/ 0x00190bc6U, +/*01bc*/ 0x00170bc7U, +/*01bd*/ 0x00110bc8U, +/*01be*/ 0x00110bc9U, +/*01bf*/ 0x00100bcaU, +/*01c0*/ 0x10010bcaU, +/*01c1*/ 0x18010bcaU, +/*01c2*/ 0x00020bcbU, +/*01c3*/ 0x08040bcbU, +/*01c4*/ 0x10090bcbU, +/*01c5*/ 0x00070bccU, +/*01c6*/ 0x08040bccU, +/*01c7*/ 0x00200bcdU, +/*01c8*/ 0x00010bceU, +/*01c9*/ 0x08020bceU, +/*01ca*/ 0x10060bceU, +/*01cb*/ 0x00100bcfU, +/*01cc*/ 0x10010bcfU, +/*01cd*/ 0x00200bd0U, +/*01ce*/ 0x00080bd1U, +/*01cf*/ 0x08010bd1U, +/*01d0*/ 0x10050bd1U, +/*01d1*/ 0x18030bd1U, +/*01d2*/ 0x00020bd2U, +/*01d3*/ 0xffffffffU, +/*01d4*/ 0x00200bd3U, +/*01d5*/ 0x000b0bd4U, +/*01d6*/ 0xffffffffU, +/*01d7*/ 0x10030bd4U, +/*01d8*/ 0x18080bd4U, +/*01d9*/ 0x00020bd5U, +/*01da*/ 0x080c0bd5U, +/*01db*/ 0x18040bd5U, +/*01dc*/ 0x00010bd6U, +/*01dd*/ 0x08050bd6U, +/*01de*/ 0x00010200U, +/*01df*/ 0x08040200U, +/*01e0*/ 0x10100200U, +/*01e1*/ 0x00010201U, +/*01e2*/ 0x08010201U, +/*01e3*/ 0x10010201U, +/*01e4*/ 0x18010201U, +/*01e5*/ 0x00100202U, +/*01e6*/ 0x10080202U, +/*01e7*/ 0x18010202U, +/*01e8*/ 0x00200203U, +/*01e9*/ 0x00200204U, +/*01ea*/ 0x00200205U, +/*01eb*/ 0x00200206U, +/*01ec*/ 0x00020207U, +/*01ed*/ 0x08010207U, +/*01ee*/ 0x10010207U, +/*01ef*/ 0x00200208U, +/*01f0*/ 0x00140209U, +/*01f1*/ 0x0020020aU, +/*01f2*/ 0x0014020bU, +/*01f3*/ 0x0020020cU, +/*01f4*/ 0x0014020dU, +/*01f5*/ 0x0014020eU, +/*01f6*/ 0x0020020fU, +/*01f7*/ 0x00200210U, +/*01f8*/ 0x00200211U, +/*01f9*/ 0x00200212U, +/*01fa*/ 0x00140213U, +/*01fb*/ 0x00200214U, +/*01fc*/ 0x00200215U, +/*01fd*/ 0x00200216U, +/*01fe*/ 0x00200217U, +/*01ff*/ 0x00140218U, +/*0200*/ 0x00200219U, +/*0201*/ 0x0020021aU, +/*0202*/ 0x0020021bU, +/*0203*/ 0x0020021cU, +/*0204*/ 0x0009021dU, +/*0205*/ 0x1001021dU, +/*0206*/ 0x0020021eU, +/*0207*/ 0x0005021fU, +/*0208*/ 0x0801021fU, +/*0209*/ 0x1008021fU, +/*020a*/ 0x1808021fU, +/*020b*/ 0x001e0220U, +/*020c*/ 0x001e0221U, +/*020d*/ 0x001e0222U, +/*020e*/ 0x001e0223U, +/*020f*/ 0x001e0224U, +/*0210*/ 0x001e0225U, +/*0211*/ 0x001e0226U, +/*0212*/ 0x001e0227U, +/*0213*/ 0x001e0228U, +/*0214*/ 0x001e0229U, +/*0215*/ 0x001e022aU, +/*0216*/ 0x001e022bU, +/*0217*/ 0x001e022cU, +/*0218*/ 0x001e022dU, +/*0219*/ 0x001e022eU, +/*021a*/ 0x001e022fU, +/*021b*/ 0x00010230U, +/*021c*/ 0x08010230U, +/*021d*/ 0x10010230U, +/*021e*/ 0x18040230U, +/*021f*/ 0x00080231U, +/*0220*/ 0x08080231U, +/*0221*/ 0x10080231U, +/*0222*/ 0x18040231U, +/*0223*/ 0x00070232U, +/*0224*/ 0x08060232U, +/*0225*/ 0x10070232U, +/*0226*/ 0x18070232U, +/*0227*/ 0x00060233U, +/*0228*/ 0x08070233U, +/*0229*/ 0x10070233U, +/*022a*/ 0x18060233U, +/*022b*/ 0x00070234U, +/*022c*/ 0x08020234U, +/*022d*/ 0x10010234U, +/*022e*/ 0x18010234U, +/*022f*/ 0x000a0235U, +/*0230*/ 0x00140236U, +/*0231*/ 0x000a0237U, +/*0232*/ 0x00140238U, +/*0233*/ 0x000a0239U, +/*0234*/ 0x0014023aU, +/*0235*/ 0xffffffffU, +/*0236*/ 0xffffffffU, +/*0237*/ 0x0005023bU, +/*0238*/ 0x0001023cU, +/*0239*/ 0x1001023cU, +/*023a*/ 0x1801023cU, +/*023b*/ 0x0001023dU, +/*023c*/ 0x0801023dU, +/*023d*/ 0x1001023dU, +/*023e*/ 0x1801023dU, +/*023f*/ 0x0002023eU, +/*0240*/ 0x0802023eU, +/*0241*/ 0x1002023eU, +/*0242*/ 0x1802023eU, +/*0243*/ 0x0002023fU, +/*0244*/ 0x0803023fU, +/*0245*/ 0x1001023fU, +/*0246*/ 0x1801023fU, +/*0247*/ 0x00010240U, +/*0248*/ 0x08010240U, +/*0249*/ 0x10010240U, +/*024a*/ 0x18020240U, +/*024b*/ 0x00010241U, +/*024c*/ 0x08010241U, +/*024d*/ 0x10010241U, +/*024e*/ 0x18020241U, +/*024f*/ 0x00010242U, +/*0250*/ 0x08010242U, +/*0251*/ 0x10010242U, +/*0252*/ 0x18020242U, +/*0253*/ 0x00010243U, +/*0254*/ 0x08010243U, +/*0255*/ 0x10010243U, +/*0256*/ 0x18020243U, +/*0257*/ 0xffffffffU, +/*0258*/ 0x00010244U, +/*0259*/ 0x08010244U, +/*025a*/ 0x10010244U, +/*025b*/ 0x18010244U, +/*025c*/ 0x00010245U, +/*025d*/ 0x08010245U, +/*025e*/ 0x10010245U, +/*025f*/ 0x18010245U, +/*0260*/ 0x00040246U, +/*0261*/ 0x08040246U, +/*0262*/ 0x10040246U, +/*0263*/ 0x18010246U, +/*0264*/ 0x00020247U, +/*0265*/ 0x08060247U, +/*0266*/ 0x10060247U, +/*0267*/ 0x18020247U, +/*0268*/ 0x00020248U, +/*0269*/ 0x08020248U, +/*026a*/ 0xffffffffU, +/*026b*/ 0x10100248U, +/*026c*/ 0x00010249U, +/*026d*/ 0x08010249U, +/*026e*/ 0x10010249U, +/*026f*/ 0x18040249U, +/*0270*/ 0x0001024aU, +/*0271*/ 0x0804024aU, +/*0272*/ 0x1003024aU, +/*0273*/ 0x1808024aU, +/*0274*/ 0x000a024bU, +/*0275*/ 0x100a024bU, +/*0276*/ 0x000a024cU, +/*0277*/ 0xffffffffU, +/*0278*/ 0x0020024dU, +/*0279*/ 0x0020024eU, +/*027a*/ 0x0005024fU, +/*027b*/ 0x1801023aU, +/*027c*/ 0x0805023cU, +/*027d*/ 0x0808024fU, +/*027e*/ 0x1001024fU, +/*027f*/ 0x1808024fU, +/*0280*/ 0x00010250U, +/*0281*/ 0x08080250U, +/*0282*/ 0x10010250U, +/*0283*/ 0x18040250U, +/*0284*/ 0x00040251U, +/*0285*/ 0x08040251U, +/*0286*/ 0x10040251U, +/*0287*/ 0x18040251U, +/*0288*/ 0x00040252U, +/*0289*/ 0x08040252U, +/*028a*/ 0x10040252U, +/*028b*/ 0x18040252U, +/*028c*/ 0x00040253U, +/*028d*/ 0x08010253U, +/*028e*/ 0x10040253U, +/*028f*/ 0x18040253U, +/*0290*/ 0x00040254U, +/*0291*/ 0x08040254U, +/*0292*/ 0x10040254U, +/*0293*/ 0x18040254U, +/*0294*/ 0x00060255U, +/*0295*/ 0x08060255U, +/*0296*/ 0x10060255U, +/*0297*/ 0x18060255U, +/*0298*/ 0x00060256U, +/*0299*/ 0x08060256U, +/*029a*/ 0x10040256U, +/*029b*/ 0x18010256U, +/*029c*/ 0x00010257U, +/*029d*/ 0x08020257U, +/*029e*/ 0x00200258U, +/*029f*/ 0x00200259U, +/*02a0*/ 0x0020025aU, +/*02a1*/ 0x0020025bU, +/*02a2*/ 0x0020025cU, +/*02a3*/ 0x0020025dU, +/*02a4*/ 0x0020025eU, +/*02a5*/ 0x0020025fU, +/*02a6*/ 0x00040260U, +/*02a7*/ 0x08040260U, +/*02a8*/ 0x10010260U, +/*02a9*/ 0x18010260U, +/*02aa*/ 0x00010261U, +/*02ab*/ 0x08010261U, +/*02ac*/ 0x10010261U, +/*02ad*/ 0x18010261U, +/*02ae*/ 0x00010262U, +/*02af*/ 0x08010262U, +/*02b0*/ 0x10010262U, +/*02b1*/ 0x18040262U, +/*02b2*/ 0x00040263U, +/*02b3*/ 0x080a0263U, +/*02b4*/ 0x00200264U, +/*02b5*/ 0x00040265U, +/*02b6*/ 0x08080265U, +/*02b7*/ 0x10020265U, +/*02b8*/ 0x18020265U, +/*02b9*/ 0x00020266U, +/*02ba*/ 0x08020266U, +/*02bb*/ 0x10020266U, +/*02bc*/ 0x18020266U, +/*02bd*/ 0xffffffffU, +/*02be*/ 0xffffffffU, +/*02bf*/ 0x00200267U, +/*02c0*/ 0x00030268U, +/*02c1*/ 0x08100268U, +/*02c2*/ 0x00100269U, +/*02c3*/ 0x10040269U, +/*02c4*/ 0x18040269U, +/*02c5*/ 0x0005026aU, +/*02c6*/ 0x0805026aU, +/*02c7*/ 0xffffffffU, +/*02c8*/ 0xffffffffU, +/*02c9*/ 0xffffffffU, +/*02ca*/ 0xffffffffU, +/*02cb*/ 0x1001026aU, +/*02cc*/ 0x1801026aU, +/*02cd*/ 0x0008026bU, +/*02ce*/ 0x0808026bU, +/*02cf*/ 0x1008026bU, +/*02d0*/ 0x1808026bU, +/*02d1*/ 0x0008026cU, +/*02d2*/ 0x0808026cU, +/*02d3*/ 0x1008026cU, +/*02d4*/ 0x1808026cU, +/*02d5*/ 0x0008026dU, +/*02d6*/ 0x0808026dU, +/*02d7*/ 0x1008026dU, +/*02d8*/ 0x1808026dU, +/*02d9*/ 0x0008026eU, +/*02da*/ 0x0808026eU, +/*02db*/ 0x1003026eU, +/*02dc*/ 0x1803026eU, +/*02dd*/ 0x0003026fU, +/*02de*/ 0xffffffffU, +/*02df*/ 0x0801026fU, +/*02e0*/ 0x1002026fU, +/*02e1*/ 0x1801026fU, +/*02e2*/ 0x00040270U, +/*02e3*/ 0x08020270U, +/*02e4*/ 0x10010270U, +/*02e5*/ 0x18010270U, +/*02e6*/ 0x00010271U, +/*02e7*/ 0x08010271U, +/*02e8*/ 0x10040271U, +/*02e9*/ 0x18080271U, +/*02ea*/ 0x000a0272U, +/*02eb*/ 0x100a0272U, +/*02ec*/ 0x000a0273U, +/*02ed*/ 0x100a0273U, +/*02ee*/ 0x000a0274U, +/*02ef*/ 0x100a0274U, +/*02f0*/ 0x00200275U, +/*02f1*/ 0x00200276U, +/*02f2*/ 0x00010277U, +/*02f3*/ 0x08020277U, +/*02f4*/ 0x10020277U, +/*02f5*/ 0x18020277U, +/*02f6*/ 0xffffffffU, +/*02f7*/ 0x00020278U, +/*02f8*/ 0x08100278U, +/*02f9*/ 0x18050278U, +/*02fa*/ 0x00060279U, +/*02fb*/ 0x08050279U, +/*02fc*/ 0x10050279U, +/*02fd*/ 0x000e027aU, +/*02fe*/ 0x1005027aU, +/*02ff*/ 0x000e027bU, +/*0300*/ 0x1005027bU, +/*0301*/ 0x000e027cU, +/*0302*/ 0x1005027cU, +/*0303*/ 0x1801027cU, +/*0304*/ 0x0005027dU, +/*0305*/ 0x0805027dU, +/*0306*/ 0x100a027dU, +/*0307*/ 0x000a027eU, +/*0308*/ 0x1005027eU, +/*0309*/ 0x1805027eU, +/*030a*/ 0x000a027fU, +/*030b*/ 0x100a027fU, +/*030c*/ 0x00050280U, +/*030d*/ 0x08050280U, +/*030e*/ 0x100a0280U, +/*030f*/ 0x000a0281U, +/*0310*/ 0x10070281U, +/*0311*/ 0x18070281U, +/*0312*/ 0x00070282U, +/*0313*/ 0x08070282U, +/*0314*/ 0x10070282U, +/*0315*/ 0x18070282U, +/*0316*/ 0xffffffffU, +/*0317*/ 0xffffffffU, +/*0318*/ 0x00040283U, +/*0319*/ 0x08040283U, +/*031a*/ 0x10040283U, +/*031b*/ 0x18040283U, +/*031c*/ 0x00040284U, +/*031d*/ 0xffffffffU, +/*031e*/ 0x08080284U, +/*031f*/ 0x10080284U, +/*0320*/ 0x18040284U, +/*0321*/ 0x00050285U, +/*0322*/ 0x08080285U, +/*0323*/ 0x10050285U, +/*0324*/ 0x18040285U, +/*0325*/ 0x00050286U, +/*0326*/ 0x08080286U, +/*0327*/ 0x10050286U, +/*0328*/ 0x18040286U, +/*0329*/ 0x00050287U, +/*032a*/ 0x08080287U, +/*032b*/ 0x10050287U, +/*032c*/ 0x18040287U, +/*032d*/ 0x00050288U, +/*032e*/ 0x08070288U, +/*032f*/ 0x10080288U, +/*0330*/ 0x00100289U, +/*0331*/ 0x10080289U, +/*0332*/ 0x0010028aU, +/*0333*/ 0x1008028aU, +/*0334*/ 0x0010028bU, +/*0335*/ 0x1008028bU, +/*0336*/ 0x1808028bU, +/*0337*/ 0x0001028cU, +/*0338*/ 0x0801028cU, +/*0339*/ 0x1006028cU, +/*033a*/ 0x1806028cU, +/*033b*/ 0x0006028dU, +/*033c*/ 0x0801028dU, +/*033d*/ 0x1001028dU, +/*033e*/ 0x1803028dU, +/*033f*/ 0x000a028eU, +/*0340*/ 0x100a028eU, +/*0341*/ 0x000a028fU, +/*0342*/ 0xffffffffU, +/*0343*/ 0x100a028fU, +/*0344*/ 0x00040290U, +/*0345*/ 0x08010290U, +/*0346*/ 0x10040290U, +/*0347*/ 0x18070290U, +/*0348*/ 0x00070291U, +/*0349*/ 0x08070291U, +/*034a*/ 0x10070291U, +/*034b*/ 0x18070291U, +/*034c*/ 0x00070292U, +/*034d*/ 0xffffffffU, +/*034e*/ 0xffffffffU, +/*034f*/ 0x08050292U, +/*0350*/ 0x10050292U, +/*0351*/ 0x18040292U, +/*0352*/ 0x00040293U, +/*0353*/ 0x08040293U, +/*0354*/ 0xffffffffU, +/*0355*/ 0x10010293U, +/*0356*/ 0x18010293U, +/*0357*/ 0x00020294U, +/*0358*/ 0x08080294U, +/*0359*/ 0x00200295U, +/*035a*/ 0x00200296U, +/*035b*/ 0x00100297U, +/*035c*/ 0x10020297U, +/*035d*/ 0x18020297U, +/*035e*/ 0x00020298U, +/*035f*/ 0xffffffffU, +/*0360*/ 0x08010298U, +/*0361*/ 0x10010298U, +/*0362*/ 0x18020298U, +/*0363*/ 0x00100299U, +/*0364*/ 0x10100299U, +/*0365*/ 0x0010029aU, +/*0366*/ 0x1008029aU, +/*0367*/ 0x1808029aU, +/*0368*/ 0x0008029bU, +/*0369*/ 0x0808029bU, +/*036a*/ 0x1010029bU, +/*036b*/ 0x0010029cU, +/*036c*/ 0x1010029cU, +/*036d*/ 0x0008029dU, +/*036e*/ 0x0808029dU, +/*036f*/ 0x1008029dU, +/*0370*/ 0x1808029dU, +/*0371*/ 0x0010029eU, +/*0372*/ 0x1010029eU, +/*0373*/ 0x0010029fU, +/*0374*/ 0x1008029fU, +/*0375*/ 0x1808029fU, +/*0376*/ 0x000802a0U, +/*0377*/ 0x080802a0U, +/*0378*/ 0x100802a0U, +/*0379*/ 0x001002a1U, +/*037a*/ 0x101002a1U, +/*037b*/ 0x001002a2U, +/*037c*/ 0x100802a2U, +/*037d*/ 0x180802a2U, +/*037e*/ 0x000802a3U, +/*037f*/ 0x080802a3U, +/*0380*/ 0x101002a3U, +/*0381*/ 0x001002a4U, +/*0382*/ 0x101002a4U, +/*0383*/ 0x000802a5U, +/*0384*/ 0x080802a5U, +/*0385*/ 0x100802a5U, +/*0386*/ 0x180802a5U, +/*0387*/ 0x001002a6U, +/*0388*/ 0x101002a6U, +/*0389*/ 0x001002a7U, +/*038a*/ 0x100802a7U, +/*038b*/ 0x180802a7U, +/*038c*/ 0x000802a8U, +/*038d*/ 0x080802a8U, +/*038e*/ 0x100802a8U, +/*038f*/ 0x001002a9U, +/*0390*/ 0x101002a9U, +/*0391*/ 0x001002aaU, +/*0392*/ 0x100802aaU, +/*0393*/ 0x180802aaU, +/*0394*/ 0x000802abU, +/*0395*/ 0x080802abU, +/*0396*/ 0x101002abU, +/*0397*/ 0x001002acU, +/*0398*/ 0x101002acU, +/*0399*/ 0x000802adU, +/*039a*/ 0x080802adU, +/*039b*/ 0x100802adU, +/*039c*/ 0x180802adU, +/*039d*/ 0x001002aeU, +/*039e*/ 0x101002aeU, +/*039f*/ 0x001002afU, +/*03a0*/ 0x100802afU, +/*03a1*/ 0x180802afU, +/*03a2*/ 0x000802b0U, +/*03a3*/ 0x080802b0U, +/*03a4*/ 0x100802b0U, +/*03a5*/ 0x001002b1U, +/*03a6*/ 0x101002b1U, +/*03a7*/ 0x001002b2U, +/*03a8*/ 0x100802b2U, +/*03a9*/ 0x180802b2U, +/*03aa*/ 0x000802b3U, +/*03ab*/ 0x080802b3U, +/*03ac*/ 0x101002b3U, +/*03ad*/ 0x001002b4U, +/*03ae*/ 0x101002b4U, +/*03af*/ 0x000802b5U, +/*03b0*/ 0x080802b5U, +/*03b1*/ 0x100802b5U, +/*03b2*/ 0x180802b5U, +/*03b3*/ 0x001002b6U, +/*03b4*/ 0x101002b6U, +/*03b5*/ 0x001002b7U, +/*03b6*/ 0x100802b7U, +/*03b7*/ 0x180802b7U, +/*03b8*/ 0x000802b8U, +/*03b9*/ 0x080802b8U, +/*03ba*/ 0x100802b8U, +/*03bb*/ 0x180202b8U, +/*03bc*/ 0x000302b9U, +/*03bd*/ 0x080a02b9U, +/*03be*/ 0x000a02baU, +/*03bf*/ 0x100a02baU, +/*03c0*/ 0x000502bbU, +/*03c1*/ 0x080802bbU, +/*03c2*/ 0x100802bbU, +/*03c3*/ 0x180802bbU, +/*03c4*/ 0x000602bcU, +/*03c5*/ 0x080602bcU, +/*03c6*/ 0x001102bdU, +/*03c7*/ 0x180802bdU, +/*03c8*/ 0x000402beU, +/*03c9*/ 0x080602beU, +/*03ca*/ 0x100802beU, +/*03cb*/ 0x180802beU, +/*03cc*/ 0x000802bfU, +/*03cd*/ 0x080802bfU, +/*03ce*/ 0x100802bfU, +/*03cf*/ 0x180802bfU, +/*03d0*/ 0x000802c0U, +/*03d1*/ 0x080602c0U, +/*03d2*/ 0x100602c0U, +/*03d3*/ 0x001102c1U, +/*03d4*/ 0x180802c1U, +/*03d5*/ 0x000402c2U, +/*03d6*/ 0x080602c2U, +/*03d7*/ 0x100802c2U, +/*03d8*/ 0x180802c2U, +/*03d9*/ 0x000802c3U, +/*03da*/ 0x080802c3U, +/*03db*/ 0x100802c3U, +/*03dc*/ 0x180802c3U, +/*03dd*/ 0x000802c4U, +/*03de*/ 0x080602c4U, +/*03df*/ 0x100602c4U, +/*03e0*/ 0x001102c5U, +/*03e1*/ 0x180802c5U, +/*03e2*/ 0x000402c6U, +/*03e3*/ 0x080602c6U, +/*03e4*/ 0x100802c6U, +/*03e5*/ 0x180802c6U, +/*03e6*/ 0x000802c7U, +/*03e7*/ 0x080802c7U, +/*03e8*/ 0x100402c7U, +/*03e9*/ 0x180402c7U, +/*03ea*/ 0x000402c8U, +/*03eb*/ 0x080402c8U, +/*03ec*/ 0x100402c8U, +/*03ed*/ 0x180402c8U, +/*03ee*/ 0x000402c9U, +/*03ef*/ 0x080402c9U, +/*03f0*/ 0x100402c9U, +/*03f1*/ 0x180402c9U, +/*03f2*/ 0x000402caU, +/*03f3*/ 0x080402caU, +/*03f4*/ 0x100402caU, +/*03f5*/ 0x180402caU, +/*03f6*/ 0x000402cbU, +/*03f7*/ 0x080402cbU, +/*03f8*/ 0x100402cbU, +/*03f9*/ 0x180402cbU, +/*03fa*/ 0x000402ccU, +/*03fb*/ 0x080402ccU, +/*03fc*/ 0x001702cdU, +/*03fd*/ 0x001602ceU, +/*03fe*/ 0x001702cfU, +/*03ff*/ 0x002002d0U, +/*0400*/ 0x002002d1U, +/*0401*/ 0x002002d2U, +/*0402*/ 0x002002d3U, +/*0403*/ 0x002002d4U, +/*0404*/ 0x002002d5U, +/*0405*/ 0x002002d6U, +/*0406*/ 0x002002d7U, +/*0407*/ 0x002002d8U, +/*0408*/ 0x000202d9U, +/*0409*/ 0x080502d9U, +/*040a*/ 0x100502d9U, +/*040b*/ 0x180102d9U, +/*040c*/ 0x000502daU, +/*040d*/ 0x080502daU, +/*040e*/ 0x100502daU, +/*040f*/ 0x180502daU, +/*0410*/ 0x000502dbU, +/*0411*/ 0x080502dbU, +/*0412*/ 0x100502dbU, +/*0413*/ 0x180502dbU, +/*0414*/ 0x000502dcU, +/*0415*/ 0x080502dcU, +/*0416*/ 0x100502dcU, +/*0417*/ 0x180502dcU, +/*0418*/ 0x000502ddU, +/*0419*/ 0x080502ddU, +/*041a*/ 0x100502ddU, +/*041b*/ 0x180502ddU, +/*041c*/ 0x000502deU, +/*041d*/ 0x080502deU, +/*041e*/ 0x100502deU, +/*041f*/ 0x180502deU, +/*0420*/ 0x000502dfU, +/*0421*/ 0x080502dfU, +/*0422*/ 0x100102dfU, +/*0423*/ 0x180202dfU, +/*0424*/ 0x000202e0U, +/*0425*/ 0x080202e0U, +/*0426*/ 0x100202e0U, +/*0427*/ 0x180102e0U, +/*0428*/ 0x000802e1U, +/*0429*/ 0x081502e1U, +/*042a*/ 0x002002e2U, +/*042b*/ 0x001502e3U, +/*042c*/ 0x002002e4U, +/*042d*/ 0x001502e5U, +/*042e*/ 0x002002e6U, +/*042f*/ 0x000702e7U, +/*0430*/ 0x080102e7U, +/*0431*/ 0x100202e7U, +/*0432*/ 0x180602e7U, +/*0433*/ 0x000102e8U, +/*0434*/ 0x080102e8U, +/*0435*/ 0x002002e9U, +/*0436*/ 0x000202eaU, +/*0437*/ 0x002002ebU, +/*0438*/ 0x002002ecU, +/*0439*/ 0x000c02edU, +/*043a*/ 0x100c02edU, +/*043b*/ 0x002002eeU, +/*043c*/ 0x000302efU, +/*043d*/ 0x002002f0U, +/*043e*/ 0x000302f1U, +/*043f*/ 0x002002f2U, +/*0440*/ 0x000302f3U, +/*0441*/ 0x002002f4U, +/*0442*/ 0x000302f5U, +/*0443*/ 0x002002f6U, +/*0444*/ 0x000302f7U, +/*0445*/ 0x002002f8U, +/*0446*/ 0x000302f9U, +/*0447*/ 0x002002faU, +/*0448*/ 0x000302fbU, +/*0449*/ 0x002002fcU, +/*044a*/ 0x000302fdU, +/*044b*/ 0x002002feU, +/*044c*/ 0x000302ffU, +/*044d*/ 0x00200300U, +/*044e*/ 0x00030301U, +/*044f*/ 0x08030301U, +/*0450*/ 0x10020301U, +/*0451*/ 0x18020301U, +/*0452*/ 0x00200302U, +/*0453*/ 0x00200303U, +/*0454*/ 0x00200304U, +/*0455*/ 0x00200305U, +/*0456*/ 0x00040306U, +/*0457*/ 0x001e0307U, +/*0458*/ 0x001e0308U, +/*0459*/ 0x001e0309U, +/*045a*/ 0x001e030aU, +/*045b*/ 0x001e030bU, +/*045c*/ 0x001e030cU, +/*045d*/ 0x001e030dU, +/*045e*/ 0x001e030eU, +/*045f*/ 0x0004030fU, +/*0460*/ 0x0801030fU, +/*0461*/ 0x1010030fU, +/*0462*/ 0x00100310U, +/*0463*/ 0x10100310U, +/*0464*/ 0x00040311U, +/*0465*/ 0x08010311U, +/*0466*/ 0x10080311U, +/*0467*/ 0x18040311U, +/*0468*/ 0x00010312U, +/*0469*/ 0x08080312U, +/*046a*/ 0x10040312U, +/*046b*/ 0x18010312U, +/*046c*/ 0x00080313U, +/*046d*/ 0x08040313U, +/*046e*/ 0x10010313U, +/*046f*/ 0x18080313U, +/*0470*/ 0x00040314U, +/*0471*/ 0x08010314U, +/*0472*/ 0x10080314U, +/*0473*/ 0x18040314U, +/*0474*/ 0x00010315U, +/*0475*/ 0x08080315U, +/*0476*/ 0x10040315U, +/*0477*/ 0x18010315U, +/*0478*/ 0x00080316U, +/*0479*/ 0x08040316U, +/*047a*/ 0x10010316U, +/*047b*/ 0x18080316U, +/*047c*/ 0x00080317U, +/*047d*/ 0x00010318U, +/*047e*/ 0x08050318U, +/*047f*/ 0x10010318U, +/*0480*/ 0x18020318U, +/*0481*/ 0x00010319U, +/*0482*/ 0x08010319U, +/*0483*/ 0x10010319U, +/*0484*/ 0x18010319U, +/*0485*/ 0x0001031aU, +/*0486*/ 0x0801031aU, +/*0487*/ 0x1001031aU, +/*0488*/ 0x1801031aU, +/*0489*/ 0x0001031bU, +/*048a*/ 0x0801031bU, +/*048b*/ 0x1001031bU, +/*048c*/ 0x1801031bU, +/*048d*/ 0x0001031cU, +/*048e*/ 0x0801031cU, +/*048f*/ 0x1001031cU, +/*0490*/ 0x1801031cU, +/*0491*/ 0x0008031dU, +/*0492*/ 0x0808031dU, +/*0493*/ 0x1008031dU, +/*0494*/ 0x1808031dU, + } +}; diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/dram_sub_func.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/dram_sub_func.c new file mode 100644 index 0000000..da71243 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/dram_sub_func.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2015-2018, Renesas Electronics Corporation All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#include +#include "dram_sub_func.h" + +void dram_get_boot_status(uint32_t *status) +{ + *status = DRAM_BOOT_STATUS_COLD; +} + +int32_t dram_update_boot_status(uint32_t status) +{ + int32_t ret = 0; + return ret; +} diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/dram_sub_func.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/dram_sub_func.h new file mode 100644 index 0000000..db3f9b1 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/dram_sub_func.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#ifndef DRAM_SUB_FUNC_H_ +#define DRAM_SUB_FUNC_H_ + +#define DRAM_BOOT_STATUS_COLD (0U) +#define DRAM_BOOT_STATUS_WARM (1U) + +#define DRAM_UPDATE_STATUS_ERR (-1) + +void dram_get_boot_status(uint32_t *status); +int32_t dram_update_boot_status(uint32_t status); + +#endif /* DRAM_SUB_FUNC_H_ */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_chk.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_chk.h new file mode 100644 index 0000000..4fff79a --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_chk.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +static const uint32_t DDR_PHY_SLICE_REGCHK[4][4] = { +{/* H3 Ver.1.x */ + /* 0400-0457 */ + /* 0400-041f */ 0xF9BFBFBF, + /* 0420-043f */ 0x800F0138, + /* 0440-045f */ 0x00E2E007, + /* 0460-047f */ 0x00000000 +} +, +{/* M3-W */ + /* 0800-0858 */ + /* 0800-081f */ 0xF17FFF7E, + /* 0820-083f */ 0x8007013A, + /* 0840-085f */ 0x00F8C007, + /* 0860-087f */ 0x00000000 +} +, +{/* H3 (other) */ + /* 0400-0460 */ + /* 0400-041f */ 0x87FFEEFE, + /* 0420-043f */ 0x81E011D7, + /* 0440-045f */ 0xE16007C1, + /* 0460-047f */ 0x00000000 +} +, +{/* M3-N/V3H */ + /* 0800-0864 */ + /* 0800-081f */ 0x0FFFDEFE, + /* 0820-083f */ 0x078047AF, + /* 0840-085f */ 0xA5801F06, + /* 0860-087f */ 0x00000017 +} +}; + +static const uint32_t DDR_PHY_ADR_V_REGCHK[4][2] = { +{/* H3 Ver.1.x */ + /* 0600-0624 */ + /* 0600-061f */ 0x6FF7AFF7, + /* 0620-063f */ 0x00000018, +} +, +{/* M3-W */ + /* 0a00-0a24 */ + /* 0a00-0a1f */ 0x6FF7AFF7, + /* 0a20-0a3f */ 0x00000018, +} +, +{/* H3 (other) */ + /* 0600-0624 */ + /* 0600-061f */ 0x6FF7BFF7, + /* 0620-063f */ 0x00000018, +} +, +{/* M3-N/V3H */ + /* 0a00-0a24 */ + /* 0a00-0a1f */ 0x6FFFBFF7, + /* 0a20-0a3f */ 0x00000018, +} +}; + +static const uint32_t DDR_PHY_ADR_G_REGCHK[4][3] = { +{/* H3 Ver.1.x*/ + /* 0700-073a */ + /* 0700-071f */ 0x3E03DCFF, + /* 0720-073f */ 0x07FCFEA8, + /* 0740-075f */ 0x00000000, +} +, +{/* M3-W */ + /* 0b80-0bbf */ + /* 0b80-0b9f */ 0xE31FFFFE, + /* 0ba0-0bbf */ 0x6FCFEA83, + /* 0bc0-0bdf */ 0x00002000, +} +, +{/* H3 (other) */ + /* 0680-06ce */ + /* 0680-069f */ 0x1FFFFFFD, + /* 06a0-06bf */ 0x9FAA83E3, + /* 06c0-06df */ 0x00001CFD, +} +, +{/* M3-N/V3H */ + /* 0b80-0bd6 */ + /* 0b80-0b9f */ 0x1FFFFDFF, + /* 0ba0-0bbf */ 0x6EAA0FC7, + /* 0bc0-0bdf */ 0x005CDFF6, +} +}; + + +static const uint32_t DDR_PI_REGCHK[4][9] = { +{/* H3 Ver.1.x */ + /* 0200-02b4 */ + /* 0200-021f */ 0xFFFFFFFE, + /* 0220-023f */ 0xFFFF15FF, + /* 0240-025f */ 0xFFF2DEFF, + /* 0260-027f */ 0x403B7FFF, + /* 0280-029f */ 0xF7FFFD88, + /* 02a0-02bf */ 0x001FBEFF, + /* 02c0-02df */ 0x00000000, + /* 02e0-02ff */ 0x00000000, + /* 0300-031f */ 0x00000000, +} +, +{/* M3-W */ + /* 0800-02c9 */ + /* 0200-021f */ 0xFFBFFFFE, + /* 0220-023f */ 0xFFFC35FF, + /* 0240-025f */ 0xFFCF7DFF, + /* 0260-027f */ 0x4060FFFF, + /* 0280-029f */ 0xFFB02060, + /* 02a0-02bf */ 0xDFDFFDFF, + /* 02c0-02df */ 0x000003F7, + /* 02e0-02ff */ 0x00000000, + /* 0300-031f */ 0x00000000, +} +, +{/* H3 (other)*/ + /* 0200-02f4 */ + /* 0200-021f */ 0xFEFFFFFE, + /* 0220-023f */ 0xFFA057FF, + /* 0240-025f */ 0x7FBF7FFF, + /* 0260-027f */ 0x3FFFFFFC, + /* 0280-029f */ 0xF82108B0, + /* 02a0-02bf */ 0x3DFFDFFF, + /* 02c0-02df */ 0xFFFFFFBF, + /* 02e0-02ff */ 0x000FFFFF, + /* 0300-031f */ 0x00000000, +} +, +{/* M3-N/V3H */ + /* 0200-031d */ + /* 0200-021f */ 0xDFFFFFFE, + /* 0220-023f */ 0xE81AFFFF, + /* 0240-025f */ 0xFF7FFFFF, + /* 0260-027f */ 0xFFFFE7BF, + /* 0280-029f */ 0xC1601FFF, + /* 02a0-02bf */ 0xFEC0C0C0, + /* 02c0-02df */ 0x7DFFDFFF, + /* 02e0-02ff */ 0xFFFFFF7E, + /* 0300-031f */ 0x3EB5FFFF, +} +}; + diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_h3.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_h3.h new file mode 100644 index 0000000..467d43a --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_h3.h @@ -0,0 +1,462 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#define DDR_PHY_SLICE_REGSET_OFS_H3 0x0400 +#define DDR_PHY_ADR_V_REGSET_OFS_H3 0x0600 +#define DDR_PHY_ADR_I_REGSET_OFS_H3 0x0680 +#define DDR_PHY_ADR_G_REGSET_OFS_H3 0x0700 +#define DDR_PI_REGSET_OFS_H3 0x0200 + +#define DDR_PHY_SLICE_REGSET_SIZE_H3 0x80 +#define DDR_PHY_ADR_V_REGSET_SIZE_H3 0x80 +#define DDR_PHY_ADR_I_REGSET_SIZE_H3 0x80 +#define DDR_PHY_ADR_G_REGSET_SIZE_H3 0x80 +#define DDR_PI_REGSET_SIZE_H3 0x100 + +#define DDR_PHY_SLICE_REGSET_NUM_H3 88 +#define DDR_PHY_ADR_V_REGSET_NUM_H3 37 +#define DDR_PHY_ADR_I_REGSET_NUM_H3 37 +#define DDR_PHY_ADR_G_REGSET_NUM_H3 59 +#define DDR_PI_REGSET_NUM_H3 181 + +static const uint32_t DDR_PHY_SLICE_REGSET_H3[DDR_PHY_SLICE_REGSET_NUM_H3] = { +/*0400*/ 0x000004f0, +/*0401*/ 0x00000000, +/*0402*/ 0x00000000, +/*0403*/ 0x00000100, +/*0404*/ 0x01003c0c, +/*0405*/ 0x02003c0c, +/*0406*/ 0x00010300, +/*0407*/ 0x04000100, +/*0408*/ 0x00000300, +/*0409*/ 0x000700c0, +/*040a*/ 0x00b00201, +/*040b*/ 0x00000020, +/*040c*/ 0x00000000, +/*040d*/ 0x00000000, +/*040e*/ 0x00000000, +/*040f*/ 0x00000000, +/*0410*/ 0x00000000, +/*0411*/ 0x00000000, +/*0412*/ 0x00000000, +/*0413*/ 0x09000000, +/*0414*/ 0x04080000, +/*0415*/ 0x04080400, +/*0416*/ 0x00000000, +/*0417*/ 0x32103210, +/*0418*/ 0x00800708, +/*0419*/ 0x000f000c, +/*041a*/ 0x00000100, +/*041b*/ 0x55aa55aa, +/*041c*/ 0x33cc33cc, +/*041d*/ 0x0ff00ff0, +/*041e*/ 0x0f0ff0f0, +/*041f*/ 0x00008e38, +/*0420*/ 0x76543210, +/*0421*/ 0x00000001, +/*0422*/ 0x00000000, +/*0423*/ 0x00000000, +/*0424*/ 0x00000000, +/*0425*/ 0x00000000, +/*0426*/ 0x00000000, +/*0427*/ 0x00000000, +/*0428*/ 0x00000000, +/*0429*/ 0x00000000, +/*042a*/ 0x00000000, +/*042b*/ 0x00000000, +/*042c*/ 0x00000000, +/*042d*/ 0x00000000, +/*042e*/ 0x00000000, +/*042f*/ 0x00000000, +/*0430*/ 0x00000000, +/*0431*/ 0x00000000, +/*0432*/ 0x00000000, +/*0433*/ 0x00200000, +/*0434*/ 0x08200820, +/*0435*/ 0x08200820, +/*0436*/ 0x08200820, +/*0437*/ 0x08200820, +/*0438*/ 0x08200820, +/*0439*/ 0x00000820, +/*043a*/ 0x03000300, +/*043b*/ 0x03000300, +/*043c*/ 0x03000300, +/*043d*/ 0x03000300, +/*043e*/ 0x00000300, +/*043f*/ 0x00000000, +/*0440*/ 0x00000000, +/*0441*/ 0x00000000, +/*0442*/ 0x00000000, +/*0443*/ 0x00a000a0, +/*0444*/ 0x00a000a0, +/*0445*/ 0x00a000a0, +/*0446*/ 0x00a000a0, +/*0447*/ 0x00a000a0, +/*0448*/ 0x00a000a0, +/*0449*/ 0x00a000a0, +/*044a*/ 0x00a000a0, +/*044b*/ 0x00a000a0, +/*044c*/ 0x01040109, +/*044d*/ 0x00000200, +/*044e*/ 0x01000000, +/*044f*/ 0x00000200, +/*0450*/ 0x4041a151, +/*0451*/ 0xc00141a0, +/*0452*/ 0x0e0100c0, +/*0453*/ 0x0010000c, +/*0454*/ 0x0c064208, +/*0455*/ 0x000f0c18, +/*0456*/ 0x00e00140, +/*0457*/ 0x00000c20 +}; + +static const uint32_t DDR_PHY_ADR_V_REGSET_H3[DDR_PHY_ADR_V_REGSET_NUM_H3] = { +/*0600*/ 0x00000000, +/*0601*/ 0x00000000, +/*0602*/ 0x00000000, +/*0603*/ 0x00000000, +/*0604*/ 0x00000000, +/*0605*/ 0x00000000, +/*0606*/ 0x00000002, +/*0607*/ 0x00000000, +/*0608*/ 0x00000000, +/*0609*/ 0x00000000, +/*060a*/ 0x00400320, +/*060b*/ 0x00000040, +/*060c*/ 0x00dcba98, +/*060d*/ 0x00000000, +/*060e*/ 0x00dcba98, +/*060f*/ 0x01000000, +/*0610*/ 0x00020003, +/*0611*/ 0x00000000, +/*0612*/ 0x00000000, +/*0613*/ 0x00000000, +/*0614*/ 0x00002a01, +/*0615*/ 0x00000015, +/*0616*/ 0x00000015, +/*0617*/ 0x0000002a, +/*0618*/ 0x00000033, +/*0619*/ 0x0000000c, +/*061a*/ 0x0000000c, +/*061b*/ 0x00000033, +/*061c*/ 0x00418820, +/*061d*/ 0x003f0000, +/*061e*/ 0x0000003f, +/*061f*/ 0x0002006e, +/*0620*/ 0x02000200, +/*0621*/ 0x02000200, +/*0622*/ 0x00000200, +/*0623*/ 0x42080010, +/*0624*/ 0x00000003 +}; + +static const uint32_t DDR_PHY_ADR_I_REGSET_H3[DDR_PHY_ADR_I_REGSET_NUM_H3] = { +/*0680*/ 0x04040404, +/*0681*/ 0x00000404, +/*0682*/ 0x00000000, +/*0683*/ 0x00000000, +/*0684*/ 0x00000000, +/*0685*/ 0x00000000, +/*0686*/ 0x00000002, +/*0687*/ 0x00000000, +/*0688*/ 0x00000000, +/*0689*/ 0x00000000, +/*068a*/ 0x00400320, +/*068b*/ 0x00000040, +/*068c*/ 0x00000000, +/*068d*/ 0x00000000, +/*068e*/ 0x00000000, +/*068f*/ 0x01000000, +/*0690*/ 0x00020003, +/*0691*/ 0x00000000, +/*0692*/ 0x00000000, +/*0693*/ 0x00000000, +/*0694*/ 0x00002a01, +/*0695*/ 0x00000015, +/*0696*/ 0x00000015, +/*0697*/ 0x0000002a, +/*0698*/ 0x00000033, +/*0699*/ 0x0000000c, +/*069a*/ 0x0000000c, +/*069b*/ 0x00000033, +/*069c*/ 0x00000000, +/*069d*/ 0x00000000, +/*069e*/ 0x00000000, +/*069f*/ 0x0002006e, +/*06a0*/ 0x02000200, +/*06a1*/ 0x02000200, +/*06a2*/ 0x00000200, +/*06a3*/ 0x42080010, +/*06a4*/ 0x00000003 +}; + +static const uint32_t DDR_PHY_ADR_G_REGSET_H3[DDR_PHY_ADR_G_REGSET_NUM_H3] = { +/*0700*/ 0x00000001, +/*0701*/ 0x00000000, +/*0702*/ 0x00000005, +/*0703*/ 0x04000f00, +/*0704*/ 0x00020080, +/*0705*/ 0x00020055, +/*0706*/ 0x00000000, +/*0707*/ 0x00000000, +/*0708*/ 0x00000000, +/*0709*/ 0x00000050, +/*070a*/ 0x00000000, +/*070b*/ 0x01010100, +/*070c*/ 0x00000200, +/*070d*/ 0x00001102, +/*070e*/ 0x00000000, +/*070f*/ 0x000f1f00, +/*0710*/ 0x0f1f0f1f, +/*0711*/ 0x0f1f0f1f, +/*0712*/ 0x00020003, +/*0713*/ 0x02000200, +/*0714*/ 0x00000200, +/*0715*/ 0x00001102, +/*0716*/ 0x00000064, +/*0717*/ 0x00000000, +/*0718*/ 0x00000000, +/*0719*/ 0x00000502, +/*071a*/ 0x027f6e00, +/*071b*/ 0x007f007f, +/*071c*/ 0x00007f3c, +/*071d*/ 0x00047f6e, +/*071e*/ 0x0003154f, +/*071f*/ 0x0001154f, +/*0720*/ 0x0001154f, +/*0721*/ 0x0001154f, +/*0722*/ 0x0001154f, +/*0723*/ 0x00003fee, +/*0724*/ 0x0001154f, +/*0725*/ 0x00003fee, +/*0726*/ 0x0001154f, +/*0727*/ 0x00007f3c, +/*0728*/ 0x0001154f, +/*0729*/ 0x00000000, +/*072a*/ 0x00000000, +/*072b*/ 0x00000000, +/*072c*/ 0x65000000, +/*072d*/ 0x00000000, +/*072e*/ 0x00000000, +/*072f*/ 0x00000201, +/*0730*/ 0x00000000, +/*0731*/ 0x00000000, +/*0732*/ 0x00000000, +/*0733*/ 0x00000000, +/*0734*/ 0x00000000, +/*0735*/ 0x00000000, +/*0736*/ 0x00000000, +/*0737*/ 0x00000000, +/*0738*/ 0x00000000, +/*0739*/ 0x00000000, +/*073a*/ 0x00000000 +}; + +static const uint32_t DDR_PI_REGSET_H3[DDR_PI_REGSET_NUM_H3] = { +/*0200*/ 0x00000b00, +/*0201*/ 0x00000100, +/*0202*/ 0x00000000, +/*0203*/ 0x0000ffff, +/*0204*/ 0x00000000, +/*0205*/ 0x0000ffff, +/*0206*/ 0x00000000, +/*0207*/ 0x304cffff, +/*0208*/ 0x00000200, +/*0209*/ 0x00000200, +/*020a*/ 0x00000200, +/*020b*/ 0x00000200, +/*020c*/ 0x0000304c, +/*020d*/ 0x00000200, +/*020e*/ 0x00000200, +/*020f*/ 0x00000200, +/*0210*/ 0x00000200, +/*0211*/ 0x0000304c, +/*0212*/ 0x00000200, +/*0213*/ 0x00000200, +/*0214*/ 0x00000200, +/*0215*/ 0x00000200, +/*0216*/ 0x00010000, +/*0217*/ 0x00000003, +/*0218*/ 0x01000001, +/*0219*/ 0x00000000, +/*021a*/ 0x00000000, +/*021b*/ 0x00000000, +/*021c*/ 0x00000000, +/*021d*/ 0x00000000, +/*021e*/ 0x00000000, +/*021f*/ 0x00000000, +/*0220*/ 0x00000000, +/*0221*/ 0x00000000, +/*0222*/ 0x00000000, +/*0223*/ 0x00000000, +/*0224*/ 0x00000000, +/*0225*/ 0x00000000, +/*0226*/ 0x00000000, +/*0227*/ 0x00000000, +/*0228*/ 0x00000000, +/*0229*/ 0x0f000101, +/*022a*/ 0x08492d25, +/*022b*/ 0x500e0c04, +/*022c*/ 0x0002500e, +/*022d*/ 0x00460003, +/*022e*/ 0x182600cf, +/*022f*/ 0x182600cf, +/*0230*/ 0x00000005, +/*0231*/ 0x00000000, +/*0232*/ 0x00000000, +/*0233*/ 0x00000000, +/*0234*/ 0x00000000, +/*0235*/ 0x00000000, +/*0236*/ 0x00000000, +/*0237*/ 0x00000000, +/*0238*/ 0x01000000, +/*0239*/ 0x00040404, +/*023a*/ 0x01280a00, +/*023b*/ 0x00000000, +/*023c*/ 0x000f0000, +/*023d*/ 0x00001803, +/*023e*/ 0x00000000, +/*023f*/ 0x00000000, +/*0240*/ 0x00060002, +/*0241*/ 0x00010001, +/*0242*/ 0x01000101, +/*0243*/ 0x04020201, +/*0244*/ 0x00080804, +/*0245*/ 0x00000000, +/*0246*/ 0x08030000, +/*0247*/ 0x15150408, +/*0248*/ 0x00000000, +/*0249*/ 0x00000000, +/*024a*/ 0x00000000, +/*024b*/ 0x001e0f0f, +/*024c*/ 0x00000000, +/*024d*/ 0x01000300, +/*024e*/ 0x00000000, +/*024f*/ 0x00000000, +/*0250*/ 0x01000000, +/*0251*/ 0x00010101, +/*0252*/ 0x000e0e0e, +/*0253*/ 0x000c0c0c, +/*0254*/ 0x02060601, +/*0255*/ 0x00000000, +/*0256*/ 0x00000003, +/*0257*/ 0x00181703, +/*0258*/ 0x00280006, +/*0259*/ 0x00280016, +/*025a*/ 0x00000016, +/*025b*/ 0x00000000, +/*025c*/ 0x00000000, +/*025d*/ 0x00000000, +/*025e*/ 0x140a0000, +/*025f*/ 0x0005010a, +/*0260*/ 0x03018d03, +/*0261*/ 0x000a018d, +/*0262*/ 0x00060100, +/*0263*/ 0x01000006, +/*0264*/ 0x018e018e, +/*0265*/ 0x018e0100, +/*0266*/ 0x1111018e, +/*0267*/ 0x10010204, +/*0268*/ 0x09090650, +/*0269*/ 0x20110202, +/*026a*/ 0x00201000, +/*026b*/ 0x00201000, +/*026c*/ 0x04041000, +/*026d*/ 0x18020100, +/*026e*/ 0x00010118, +/*026f*/ 0x004b004a, +/*0270*/ 0x050f0000, +/*0271*/ 0x0c01021e, +/*0272*/ 0x34000000, +/*0273*/ 0x00000000, +/*0274*/ 0x00000000, +/*0275*/ 0x00000000, +/*0276*/ 0x312ed400, +/*0277*/ 0xd4111132, +/*0278*/ 0x1132312e, +/*0279*/ 0x312ed411, +/*027a*/ 0x00111132, +/*027b*/ 0x32312ed4, +/*027c*/ 0x2ed41111, +/*027d*/ 0x11113231, +/*027e*/ 0x32312ed4, +/*027f*/ 0xd4001111, +/*0280*/ 0x1132312e, +/*0281*/ 0x312ed411, +/*0282*/ 0xd4111132, +/*0283*/ 0x1132312e, +/*0284*/ 0x2ed40011, +/*0285*/ 0x11113231, +/*0286*/ 0x32312ed4, +/*0287*/ 0x2ed41111, +/*0288*/ 0x11113231, +/*0289*/ 0x00020000, +/*028a*/ 0x018d018d, +/*028b*/ 0x0c08018d, +/*028c*/ 0x1f121d22, +/*028d*/ 0x4301b344, +/*028e*/ 0x10172006, +/*028f*/ 0x121d220c, +/*0290*/ 0x01b3441f, +/*0291*/ 0x17200643, +/*0292*/ 0x1d220c10, +/*0293*/ 0x00001f12, +/*0294*/ 0x4301b344, +/*0295*/ 0x10172006, +/*0296*/ 0x00020002, +/*0297*/ 0x00020002, +/*0298*/ 0x00020002, +/*0299*/ 0x00020002, +/*029a*/ 0x00020002, +/*029b*/ 0x00000000, +/*029c*/ 0x00000000, +/*029d*/ 0x00000000, +/*029e*/ 0x00000000, +/*029f*/ 0x00000000, +/*02a0*/ 0x00000000, +/*02a1*/ 0x00000000, +/*02a2*/ 0x00000000, +/*02a3*/ 0x00000000, +/*02a4*/ 0x00000000, +/*02a5*/ 0x00000000, +/*02a6*/ 0x00000000, +/*02a7*/ 0x01000400, +/*02a8*/ 0x00304c00, +/*02a9*/ 0x0001e2f8, +/*02aa*/ 0x0000304c, +/*02ab*/ 0x0001e2f8, +/*02ac*/ 0x0000304c, +/*02ad*/ 0x0001e2f8, +/*02ae*/ 0x08000000, +/*02af*/ 0x00000100, +/*02b0*/ 0x00000000, +/*02b1*/ 0x00000000, +/*02b2*/ 0x00000000, +/*02b3*/ 0x00000000, +/*02b4*/ 0x00000002 +}; diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_h3ver2.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_h3ver2.h new file mode 100644 index 0000000..9e23b3b --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_h3ver2.h @@ -0,0 +1,555 @@ +/* + * Copyright (c) 2015-2022, Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#define DDR_PHY_SLICE_REGSET_OFS_H3VER2 0x0400 +#define DDR_PHY_ADR_V_REGSET_OFS_H3VER2 0x0600 +#define DDR_PHY_ADR_I_REGSET_OFS_H3VER2 0x0640 +#define DDR_PHY_ADR_G_REGSET_OFS_H3VER2 0x0680 +#define DDR_PI_REGSET_OFS_H3VER2 0x0200 + +#define DDR_PHY_SLICE_REGSET_SIZE_H3VER2 0x80 +#define DDR_PHY_ADR_V_REGSET_SIZE_H3VER2 0x40 +#define DDR_PHY_ADR_I_REGSET_SIZE_H3VER2 0x40 +#define DDR_PHY_ADR_G_REGSET_SIZE_H3VER2 0x80 +#define DDR_PI_REGSET_SIZE_H3VER2 0x100 + +#define DDR_PHY_SLICE_REGSET_NUM_H3VER2 97 +#define DDR_PHY_ADR_V_REGSET_NUM_H3VER2 37 +#define DDR_PHY_ADR_I_REGSET_NUM_H3VER2 37 +#define DDR_PHY_ADR_G_REGSET_NUM_H3VER2 79 +#define DDR_PI_REGSET_NUM_H3VER2 245 + +static const uint32_t DDR_PHY_SLICE_REGSET_H3VER2[DDR_PHY_SLICE_REGSET_NUM_H3VER2] = { +/*0400*/ 0x76543210, +/*0401*/ 0x0004f008, +/*0402*/ 0x00020133, +/*0403*/ 0x00000000, +/*0404*/ 0x00000000, +/*0405*/ 0x00010000, +/*0406*/ 0x016e6e0e, +/*0407*/ 0x026e6e0e, +/*0408*/ 0x00010300, +/*0409*/ 0x04000100, +/*040a*/ 0x01000000, +/*040b*/ 0x00000000, +/*040c*/ 0x00000000, +/*040d*/ 0x00000100, +/*040e*/ 0x001700c0, +/*040f*/ 0x020100b0, +/*0410*/ 0x00030020, +/*0411*/ 0x00000000, +/*0412*/ 0x00000000, +/*0413*/ 0x00000000, +/*0414*/ 0x00000000, +/*0415*/ 0x00000000, +/*0416*/ 0x00000000, +/*0417*/ 0x00000000, +/*0418*/ 0x09000000, +/*0419*/ 0x04080000, +/*041a*/ 0x04080400, +/*041b*/ 0x08000000, +/*041c*/ 0x0c008007, +/*041d*/ 0x00000f00, +/*041e*/ 0x00000100, +/*041f*/ 0x55aa55aa, +/*0420*/ 0x33cc33cc, +/*0421*/ 0x0ff00ff0, +/*0422*/ 0x0f0ff0f0, +/*0423*/ 0x00018e38, +/*0424*/ 0x00000000, +/*0425*/ 0x00000000, +/*0426*/ 0x00000000, +/*0427*/ 0x00000000, +/*0428*/ 0x00000000, +/*0429*/ 0x00000000, +/*042a*/ 0x00000000, +/*042b*/ 0x00000000, +/*042c*/ 0x00000000, +/*042d*/ 0x00000000, +/*042e*/ 0x00000000, +/*042f*/ 0x00000000, +/*0430*/ 0x00000000, +/*0431*/ 0x00000000, +/*0432*/ 0x00000000, +/*0433*/ 0x00000000, +/*0434*/ 0x00000000, +/*0435*/ 0x00000000, +/*0436*/ 0x00000000, +/*0437*/ 0x00000000, +/*0438*/ 0x00000104, +/*0439*/ 0x00082020, +/*043a*/ 0x08200820, +/*043b*/ 0x08200820, +/*043c*/ 0x08200820, +/*043d*/ 0x08200820, +/*043e*/ 0x08200820, +/*043f*/ 0x00000000, +/*0440*/ 0x00000000, +/*0441*/ 0x03000300, +/*0442*/ 0x03000300, +/*0443*/ 0x03000300, +/*0444*/ 0x03000300, +/*0445*/ 0x00000300, +/*0446*/ 0x00000000, +/*0447*/ 0x00000000, +/*0448*/ 0x00000000, +/*0449*/ 0x00000000, +/*044a*/ 0x00000000, +/*044b*/ 0x00a000a0, +/*044c*/ 0x00a000a0, +/*044d*/ 0x00a000a0, +/*044e*/ 0x00a000a0, +/*044f*/ 0x00a000a0, +/*0450*/ 0x00a000a0, +/*0451*/ 0x00a000a0, +/*0452*/ 0x00a000a0, +/*0453*/ 0x00a000a0, +/*0454*/ 0x01040109, +/*0455*/ 0x00000200, +/*0456*/ 0x01000000, +/*0457*/ 0x00000200, +/*0458*/ 0x00000004, +/*0459*/ 0x4041a151, +/*045a*/ 0xc00141a0, +/*045b*/ 0x0e0000c0, +/*045c*/ 0x0010000c, +/*045d*/ 0x063e4208, +/*045e*/ 0x0f0c180c, +/*045f*/ 0x00e00140, +/*0460*/ 0x00000c20 +}; + +static const uint32_t DDR_PHY_ADR_V_REGSET_H3VER2[DDR_PHY_ADR_V_REGSET_NUM_H3VER2] = { +/*0600*/ 0x00000000, +/*0601*/ 0x00000000, +/*0602*/ 0x00000000, +/*0603*/ 0x00000000, +/*0604*/ 0x00000000, +/*0605*/ 0x00000000, +/*0606*/ 0x00000000, +/*0607*/ 0x00010000, +/*0608*/ 0x00000200, +/*0609*/ 0x00000000, +/*060a*/ 0x00000000, +/*060b*/ 0x00000000, +/*060c*/ 0x00400320, +/*060d*/ 0x00000040, +/*060e*/ 0x00dcba98, +/*060f*/ 0x03000000, +/*0610*/ 0x00000200, +/*0611*/ 0x00000000, +/*0612*/ 0x00000000, +/*0613*/ 0x00000000, +/*0614*/ 0x0000002a, +/*0615*/ 0x00000015, +/*0616*/ 0x00000015, +/*0617*/ 0x0000002a, +/*0618*/ 0x00000033, +/*0619*/ 0x0000000c, +/*061a*/ 0x0000000c, +/*061b*/ 0x00000033, +/*061c*/ 0x00418820, +/*061d*/ 0x003f0000, +/*061e*/ 0x0000003f, +/*061f*/ 0x0002c06e, +/*0620*/ 0x02c002c0, +/*0621*/ 0x02c002c0, +/*0622*/ 0x000002c0, +/*0623*/ 0x42080010, +/*0624*/ 0x0000033e +}; + +static const uint32_t DDR_PHY_ADR_I_REGSET_H3VER2[DDR_PHY_ADR_I_REGSET_NUM_H3VER2] = { +/*0640*/ 0x00000000, +/*0641*/ 0x00000000, +/*0642*/ 0x00000000, +/*0643*/ 0x00000000, +/*0644*/ 0x00000000, +/*0645*/ 0x00000000, +/*0646*/ 0x00000000, +/*0647*/ 0x00000000, +/*0648*/ 0x00000000, +/*0649*/ 0x00000000, +/*064a*/ 0x00000000, +/*064b*/ 0x00000000, +/*064c*/ 0x00000000, +/*064d*/ 0x00000000, +/*064e*/ 0x00000000, +/*064f*/ 0x00000000, +/*0650*/ 0x00000000, +/*0651*/ 0x00000000, +/*0652*/ 0x00000000, +/*0653*/ 0x00000000, +/*0654*/ 0x00000000, +/*0655*/ 0x00000000, +/*0656*/ 0x00000000, +/*0657*/ 0x00000000, +/*0658*/ 0x00000000, +/*0659*/ 0x00000000, +/*065a*/ 0x00000000, +/*065b*/ 0x00000000, +/*065c*/ 0x00000000, +/*065d*/ 0x00000000, +/*065e*/ 0x00000000, +/*065f*/ 0x00000000, +/*0660*/ 0x00000000, +/*0661*/ 0x00000000, +/*0662*/ 0x00000000, +/*0663*/ 0x00000000, +/*0664*/ 0x00000000 +}; + +static const uint32_t DDR_PHY_ADR_G_REGSET_H3VER2[DDR_PHY_ADR_G_REGSET_NUM_H3VER2] = { +/*0680*/ 0x00000000, +/*0681*/ 0x00000100, +/*0682*/ 0x00000000, +/*0683*/ 0x00050000, +/*0684*/ 0x0f000000, +/*0685*/ 0x00800400, +/*0686*/ 0x00020032, +/*0687*/ 0x00020055, +/*0688*/ 0x00000000, +/*0689*/ 0x00000000, +/*068a*/ 0x00000000, +/*068b*/ 0x00000050, +/*068c*/ 0x00000000, +/*068d*/ 0x01010100, +/*068e*/ 0x01000200, +/*068f*/ 0x00000000, +/*0690*/ 0x00010100, +/*0691*/ 0x00000000, +/*0692*/ 0x00000000, +/*0693*/ 0x00000000, +/*0694*/ 0x00000000, +/*0695*/ 0x00005064, +/*0696*/ 0x05421542, +/*0697*/ 0x00000542, +/*0698*/ 0x00000000, +/*0699*/ 0x000f1100, +/*069a*/ 0x0f110f11, +/*069b*/ 0x09000f11, +/*069c*/ 0x00000003, +/*069d*/ 0x0002c000, +/*069e*/ 0x02c002c0, +/*069f*/ 0x000002c0, +/*06a0*/ 0x05421542, +/*06a1*/ 0x00000542, +/*06a2*/ 0x00000000, +/*06a3*/ 0x00000000, +/*06a4*/ 0x05020000, +/*06a5*/ 0x14000001, +/*06a6*/ 0x027f6e00, +/*06a7*/ 0x047f027f, +/*06a8*/ 0x00027f6e, +/*06a9*/ 0x00047f6e, +/*06aa*/ 0x0003554f, +/*06ab*/ 0x0001554f, +/*06ac*/ 0x0001554f, +/*06ad*/ 0x0001554f, +/*06ae*/ 0x0001554f, +/*06af*/ 0x00003fee, +/*06b0*/ 0x0001554f, +/*06b1*/ 0x00003fee, +/*06b2*/ 0x0001554f, +/*06b3*/ 0x00027f6e, +/*06b4*/ 0x0001554f, +/*06b5*/ 0x00004011, +/*06b6*/ 0x00004410, +/*06b7*/ 0x00000000, +/*06b8*/ 0x00000000, +/*06b9*/ 0x00000000, +/*06ba*/ 0x00000065, +/*06bb*/ 0x00000000, +/*06bc*/ 0x00020201, +/*06bd*/ 0x00000000, +/*06be*/ 0x03000000, +/*06bf*/ 0x00000008, +/*06c0*/ 0x00000000, +/*06c1*/ 0x00000000, +/*06c2*/ 0x00000000, +/*06c3*/ 0x00000000, +/*06c4*/ 0x00000001, +/*06c5*/ 0x00000000, +/*06c6*/ 0x00000000, +/*06c7*/ 0x00000000, +/*06c8*/ 0x000000e4, +/*06c9*/ 0x00010198, +/*06ca*/ 0x00000000, +/*06cb*/ 0x00000000, +/*06cc*/ 0x07010000, +/*06cd*/ 0x00000104, +/*06ce*/ 0x00000000 +}; + +static const uint32_t DDR_PI_REGSET_H3VER2[DDR_PI_REGSET_NUM_H3VER2] = { +/*0200*/ 0x00000b00, +/*0201*/ 0x00000100, +/*0202*/ 0x00640000, +/*0203*/ 0x00000000, +/*0204*/ 0x0000ffff, +/*0205*/ 0x00000000, +/*0206*/ 0x0000ffff, +/*0207*/ 0x00000000, +/*0208*/ 0x0000ffff, +/*0209*/ 0x0000304c, +/*020a*/ 0x00000200, +/*020b*/ 0x00000200, +/*020c*/ 0x00000200, +/*020d*/ 0x00000200, +/*020e*/ 0x0000304c, +/*020f*/ 0x00000200, +/*0210*/ 0x00000200, +/*0211*/ 0x00000200, +/*0212*/ 0x00000200, +/*0213*/ 0x0000304c, +/*0214*/ 0x00000200, +/*0215*/ 0x00000200, +/*0216*/ 0x00000200, +/*0217*/ 0x00000200, +/*0218*/ 0x00010000, +/*0219*/ 0x00000003, +/*021a*/ 0x01000001, +/*021b*/ 0x00000000, +/*021c*/ 0x00000000, +/*021d*/ 0x00000000, +/*021e*/ 0x00000000, +/*021f*/ 0x00000000, +/*0220*/ 0x00000000, +/*0221*/ 0x00000000, +/*0222*/ 0x00000000, +/*0223*/ 0x00000000, +/*0224*/ 0x00000000, +/*0225*/ 0x00000000, +/*0226*/ 0x00000000, +/*0227*/ 0x00000000, +/*0228*/ 0x00000000, +/*0229*/ 0x00000000, +/*022a*/ 0x00000000, +/*022b*/ 0x0f000101, +/*022c*/ 0x08492d25, +/*022d*/ 0x500e0c04, +/*022e*/ 0x0002500e, +/*022f*/ 0x00000301, +/*0230*/ 0x00000046, +/*0231*/ 0x000000cf, +/*0232*/ 0x00001826, +/*0233*/ 0x000000cf, +/*0234*/ 0x00001826, +/*0235*/ 0x00000005, +/*0236*/ 0x00000000, +/*0237*/ 0x00000000, +/*0238*/ 0x00000000, +/*0239*/ 0x00000000, +/*023a*/ 0x00000000, +/*023b*/ 0x00000000, +/*023c*/ 0x00000000, +/*023d*/ 0x00000000, +/*023e*/ 0x04010000, +/*023f*/ 0x00000404, +/*0240*/ 0x0101280a, +/*0241*/ 0x00000000, +/*0242*/ 0x00000000, +/*0243*/ 0x0003000f, +/*0244*/ 0x00000018, +/*0245*/ 0x00000000, +/*0246*/ 0x00000000, +/*0247*/ 0x00060002, +/*0248*/ 0x00010001, +/*0249*/ 0x01000101, +/*024a*/ 0x04020201, +/*024b*/ 0x00080804, +/*024c*/ 0x00000000, +/*024d*/ 0x08030000, +/*024e*/ 0x15150408, +/*024f*/ 0x00000000, +/*0250*/ 0x00000000, +/*0251*/ 0x00000000, +/*0252*/ 0x0f0f0000, +/*0253*/ 0x0000001e, +/*0254*/ 0x00000000, +/*0255*/ 0x01000300, +/*0256*/ 0x00000100, +/*0257*/ 0x00000000, +/*0258*/ 0x00000000, +/*0259*/ 0x01000000, +/*025a*/ 0x00000101, +/*025b*/ 0x55555a5a, +/*025c*/ 0x55555a5a, +/*025d*/ 0x55555a5a, +/*025e*/ 0x55555a5a, +/*025f*/ 0x0e0e0001, +/*0260*/ 0x0c0c000e, +/*0261*/ 0x0601000c, +/*0262*/ 0x17170106, +/*0263*/ 0x00020202, +/*0264*/ 0x03000000, +/*0265*/ 0x00000000, +/*0266*/ 0x00181703, +/*0267*/ 0x00280006, +/*0268*/ 0x00280016, +/*0269*/ 0x00000016, +/*026a*/ 0x00000000, +/*026b*/ 0x00000000, +/*026c*/ 0x00000000, +/*026d*/ 0x0a000000, +/*026e*/ 0x00010a14, +/*026f*/ 0x00030005, +/*0270*/ 0x0003018d, +/*0271*/ 0x000a018d, +/*0272*/ 0x00060100, +/*0273*/ 0x01000006, +/*0274*/ 0x018e018e, +/*0275*/ 0x018e0100, +/*0276*/ 0x1111018e, +/*0277*/ 0x10010204, +/*0278*/ 0x09090650, +/*0279*/ 0xff110202, +/*027a*/ 0x00ff1000, +/*027b*/ 0x00ff1000, +/*027c*/ 0x04041000, +/*027d*/ 0x18020100, +/*027e*/ 0x01010018, +/*027f*/ 0x004a004a, +/*0280*/ 0x004b004a, +/*0281*/ 0x050f0000, +/*0282*/ 0x0c01021e, +/*0283*/ 0x34000000, +/*0284*/ 0x00000000, +/*0285*/ 0x00000000, +/*0286*/ 0x00000000, +/*0287*/ 0x00000000, +/*0288*/ 0x36312ed4, +/*0289*/ 0x2ed41111, +/*028a*/ 0x11113631, +/*028b*/ 0x36312ed4, +/*028c*/ 0xd4001111, +/*028d*/ 0x1136312e, +/*028e*/ 0x312ed411, +/*028f*/ 0xd4111136, +/*0290*/ 0x1136312e, +/*0291*/ 0x2ed40011, +/*0292*/ 0x11113631, +/*0293*/ 0x36312ed4, +/*0294*/ 0x2ed41111, +/*0295*/ 0x11113631, +/*0296*/ 0x312ed400, +/*0297*/ 0xd4111136, +/*0298*/ 0x1136312e, +/*0299*/ 0x312ed411, +/*029a*/ 0x00111136, +/*029b*/ 0x018d0200, +/*029c*/ 0x018d018d, +/*029d*/ 0x1d220c08, +/*029e*/ 0x00001f12, +/*029f*/ 0x4301b344, +/*02a0*/ 0x10172006, +/*02a1*/ 0x121d220c, +/*02a2*/ 0x01b3441f, +/*02a3*/ 0x17200643, +/*02a4*/ 0x1d220c10, +/*02a5*/ 0x00001f12, +/*02a6*/ 0x4301b344, +/*02a7*/ 0x10172006, +/*02a8*/ 0x00020002, +/*02a9*/ 0x00020002, +/*02aa*/ 0x00020002, +/*02ab*/ 0x00020002, +/*02ac*/ 0x00020002, +/*02ad*/ 0x00000000, +/*02ae*/ 0x00000000, +/*02af*/ 0x00000000, +/*02b0*/ 0x00000000, +/*02b1*/ 0x00000000, +/*02b2*/ 0x00000000, +/*02b3*/ 0x00000000, +/*02b4*/ 0x00000000, +/*02b5*/ 0x00000000, +/*02b6*/ 0x00000000, +/*02b7*/ 0x00000000, +/*02b8*/ 0x00000000, +/*02b9*/ 0x00000400, +/*02ba*/ 0x05040302, +/*02bb*/ 0x01000f0e, +/*02bc*/ 0x07060504, +/*02bd*/ 0x03020100, +/*02be*/ 0x02010000, +/*02bf*/ 0x00000103, +/*02c0*/ 0x0000304c, +/*02c1*/ 0x0001e2f8, +/*02c2*/ 0x0000304c, +/*02c3*/ 0x0001e2f8, +/*02c4*/ 0x0000304c, +/*02c5*/ 0x0001e2f8, +/*02c6*/ 0x08000000, +/*02c7*/ 0x00000100, +/*02c8*/ 0x00000000, +/*02c9*/ 0x00000000, +/*02ca*/ 0x00000000, +/*02cb*/ 0x00000000, +/*02cc*/ 0x00010000, +/*02cd*/ 0x00000000, +/*02ce*/ 0x00000000, +/*02cf*/ 0x00000000, +/*02d0*/ 0x00000000, +/*02d1*/ 0x00000000, +/*02d2*/ 0x00000000, +/*02d3*/ 0x00000000, +/*02d4*/ 0x00000000, +/*02d5*/ 0x00000000, +/*02d6*/ 0x00000000, +/*02d7*/ 0x00000000, +/*02d8*/ 0x00000000, +/*02d9*/ 0x00000000, +/*02da*/ 0x00000000, +/*02db*/ 0x00000000, +/*02dc*/ 0x00000000, +/*02dd*/ 0x00000000, +/*02de*/ 0x00000000, +/*02df*/ 0x00000000, +/*02e0*/ 0x00000000, +/*02e1*/ 0x00000000, +/*02e2*/ 0x00000000, +/*02e3*/ 0x00000000, +/*02e4*/ 0x00000000, +/*02e5*/ 0x00000000, +/*02e6*/ 0x00000000, +/*02e7*/ 0x00000000, +/*02e8*/ 0x00000000, +/*02e9*/ 0x00000000, +/*02ea*/ 0x00000000, +/*02eb*/ 0x00000000, +/*02ec*/ 0x00000000, +/*02ed*/ 0x00000000, +/*02ee*/ 0x00000002, +/*02ef*/ 0x00000000, +/*02f0*/ 0x00000000, +/*02f1*/ 0x00000000, +/*02f2*/ 0x00000000, +/*02f3*/ 0x00000000, +/*02f4*/ 0x00000000 +}; diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_m3.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_m3.h new file mode 100644 index 0000000..9a8b94f --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_m3.h @@ -0,0 +1,489 @@ +/* + * Copyright (c) 2015-2022, Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#define DDR_PHY_SLICE_REGSET_OFS_M3 0x0800 +#define DDR_PHY_ADR_V_REGSET_OFS_M3 0x0a00 +#define DDR_PHY_ADR_I_REGSET_OFS_M3 0x0a80 +#define DDR_PHY_ADR_G_REGSET_OFS_M3 0x0b80 +#define DDR_PI_REGSET_OFS_M3 0x0200 + +#define DDR_PHY_SLICE_REGSET_SIZE_M3 0x80 +#define DDR_PHY_ADR_V_REGSET_SIZE_M3 0x80 +#define DDR_PHY_ADR_I_REGSET_SIZE_M3 0x80 +#define DDR_PHY_ADR_G_REGSET_SIZE_M3 0x80 +#define DDR_PI_REGSET_SIZE_M3 0x100 + +#define DDR_PHY_SLICE_REGSET_NUM_M3 89 +#define DDR_PHY_ADR_V_REGSET_NUM_M3 37 +#define DDR_PHY_ADR_I_REGSET_NUM_M3 37 +#define DDR_PHY_ADR_G_REGSET_NUM_M3 64 +#define DDR_PI_REGSET_NUM_M3 202 + +static const uint32_t DDR_PHY_SLICE_REGSET_M3[DDR_PHY_SLICE_REGSET_NUM_M3] = { +/*0800*/ 0x76543210, +/*0801*/ 0x0004f008, +/*0802*/ 0x00000000, +/*0803*/ 0x00000000, +/*0804*/ 0x00010000, +/*0805*/ 0x036e6e0e, +/*0806*/ 0x026e6e0e, +/*0807*/ 0x00010300, +/*0808*/ 0x04000100, +/*0809*/ 0x00000300, +/*080a*/ 0x001700c0, +/*080b*/ 0x00b00201, +/*080c*/ 0x00030020, +/*080d*/ 0x00000000, +/*080e*/ 0x00000000, +/*080f*/ 0x00000000, +/*0810*/ 0x00000000, +/*0811*/ 0x00000000, +/*0812*/ 0x00000000, +/*0813*/ 0x00000000, +/*0814*/ 0x09000000, +/*0815*/ 0x04080000, +/*0816*/ 0x04080400, +/*0817*/ 0x00000000, +/*0818*/ 0x32103210, +/*0819*/ 0x00800708, +/*081a*/ 0x000f000c, +/*081b*/ 0x00000100, +/*081c*/ 0x55aa55aa, +/*081d*/ 0x33cc33cc, +/*081e*/ 0x0ff00ff0, +/*081f*/ 0x0f0ff0f0, +/*0820*/ 0x00018e38, +/*0821*/ 0x00000000, +/*0822*/ 0x00000000, +/*0823*/ 0x00000000, +/*0824*/ 0x00000000, +/*0825*/ 0x00000000, +/*0826*/ 0x00000000, +/*0827*/ 0x00000000, +/*0828*/ 0x00000000, +/*0829*/ 0x00000000, +/*082a*/ 0x00000000, +/*082b*/ 0x00000000, +/*082c*/ 0x00000000, +/*082d*/ 0x00000000, +/*082e*/ 0x00000000, +/*082f*/ 0x00000000, +/*0830*/ 0x00000000, +/*0831*/ 0x00000000, +/*0832*/ 0x00000000, +/*0833*/ 0x00200000, +/*0834*/ 0x08200820, +/*0835*/ 0x08200820, +/*0836*/ 0x08200820, +/*0837*/ 0x08200820, +/*0838*/ 0x08200820, +/*0839*/ 0x00000820, +/*083a*/ 0x03000300, +/*083b*/ 0x03000300, +/*083c*/ 0x03000300, +/*083d*/ 0x03000300, +/*083e*/ 0x00000300, +/*083f*/ 0x00000000, +/*0840*/ 0x00000000, +/*0841*/ 0x00000000, +/*0842*/ 0x00000000, +/*0843*/ 0x00a00000, +/*0844*/ 0x00a000a0, +/*0845*/ 0x00a000a0, +/*0846*/ 0x00a000a0, +/*0847*/ 0x00a000a0, +/*0848*/ 0x00a000a0, +/*0849*/ 0x00a000a0, +/*084a*/ 0x00a000a0, +/*084b*/ 0x00a000a0, +/*084c*/ 0x010900a0, +/*084d*/ 0x02000104, +/*084e*/ 0x00000000, +/*084f*/ 0x00010000, +/*0850*/ 0x00000200, +/*0851*/ 0x4041a151, +/*0852*/ 0xc00141a0, +/*0853*/ 0x0e0100c0, +/*0854*/ 0x0010000c, +/*0855*/ 0x0c064208, +/*0856*/ 0x000f0c18, +/*0857*/ 0x00e00140, +/*0858*/ 0x00000c20 +}; + +static const uint32_t DDR_PHY_ADR_V_REGSET_M3[DDR_PHY_ADR_V_REGSET_NUM_M3] = { +/*0a00*/ 0x00000000, +/*0a01*/ 0x00000000, +/*0a02*/ 0x00000000, +/*0a03*/ 0x00000000, +/*0a04*/ 0x00000000, +/*0a05*/ 0x00000000, +/*0a06*/ 0x00000002, +/*0a07*/ 0x00000000, +/*0a08*/ 0x00000000, +/*0a09*/ 0x00000000, +/*0a0a*/ 0x00400320, +/*0a0b*/ 0x00000040, +/*0a0c*/ 0x00dcba98, +/*0a0d*/ 0x00000000, +/*0a0e*/ 0x00dcba98, +/*0a0f*/ 0x01000000, +/*0a10*/ 0x00020003, +/*0a11*/ 0x00000000, +/*0a12*/ 0x00000000, +/*0a13*/ 0x00000000, +/*0a14*/ 0x0000002a, +/*0a15*/ 0x00000015, +/*0a16*/ 0x00000015, +/*0a17*/ 0x0000002a, +/*0a18*/ 0x00000033, +/*0a19*/ 0x0000000c, +/*0a1a*/ 0x0000000c, +/*0a1b*/ 0x00000033, +/*0a1c*/ 0x0a418820, +/*0a1d*/ 0x003f0000, +/*0a1e*/ 0x0000003f, +/*0a1f*/ 0x0002c06e, +/*0a20*/ 0x02c002c0, +/*0a21*/ 0x02c002c0, +/*0a22*/ 0x000002c0, +/*0a23*/ 0x42080010, +/*0a24*/ 0x00000003 +}; + +static const uint32_t DDR_PHY_ADR_I_REGSET_M3[DDR_PHY_ADR_I_REGSET_NUM_M3] = { +/*0a80*/ 0x04040404, +/*0a81*/ 0x00000404, +/*0a82*/ 0x00000000, +/*0a83*/ 0x00000000, +/*0a84*/ 0x00000000, +/*0a85*/ 0x00000000, +/*0a86*/ 0x00000002, +/*0a87*/ 0x00000000, +/*0a88*/ 0x00000000, +/*0a89*/ 0x00000000, +/*0a8a*/ 0x00400320, +/*0a8b*/ 0x00000040, +/*0a8c*/ 0x00000000, +/*0a8d*/ 0x00000000, +/*0a8e*/ 0x00000000, +/*0a8f*/ 0x01000000, +/*0a90*/ 0x00020003, +/*0a91*/ 0x00000000, +/*0a92*/ 0x00000000, +/*0a93*/ 0x00000000, +/*0a94*/ 0x0000002a, +/*0a95*/ 0x00000015, +/*0a96*/ 0x00000015, +/*0a97*/ 0x0000002a, +/*0a98*/ 0x00000033, +/*0a99*/ 0x0000000c, +/*0a9a*/ 0x0000000c, +/*0a9b*/ 0x00000033, +/*0a9c*/ 0x00000000, +/*0a9d*/ 0x00000000, +/*0a9e*/ 0x00000000, +/*0a9f*/ 0x0002c06e, +/*0aa0*/ 0x02c002c0, +/*0aa1*/ 0x02c002c0, +/*0aa2*/ 0x000002c0, +/*0aa3*/ 0x42080010, +/*0aa4*/ 0x00000003 +}; + +static const uint32_t DDR_PHY_ADR_G_REGSET_M3[DDR_PHY_ADR_G_REGSET_NUM_M3] = { +/*0b80*/ 0x00000001, +/*0b81*/ 0x00000000, +/*0b82*/ 0x00000005, +/*0b83*/ 0x04000f00, +/*0b84*/ 0x00020080, +/*0b85*/ 0x00020055, +/*0b86*/ 0x00000000, +/*0b87*/ 0x00000000, +/*0b88*/ 0x00000000, +/*0b89*/ 0x00000050, +/*0b8a*/ 0x00000000, +/*0b8b*/ 0x01010100, +/*0b8c*/ 0x00000600, +/*0b8d*/ 0x50640000, +/*0b8e*/ 0x03421342, +/*0b8f*/ 0x00000342, +/*0b90*/ 0x00000000, +/*0b91*/ 0x000f1600, +/*0b92*/ 0x0f160f16, +/*0b93*/ 0x0f160f16, +/*0b94*/ 0x00000003, +/*0b95*/ 0x0002c000, +/*0b96*/ 0x02c002c0, +/*0b97*/ 0x000002c0, +/*0b98*/ 0x03421342, +/*0b99*/ 0x00000342, +/*0b9a*/ 0x00000000, +/*0b9b*/ 0x00000000, +/*0b9c*/ 0x05020000, +/*0b9d*/ 0x00000000, +/*0b9e*/ 0x00027f6e, +/*0b9f*/ 0x047f027f, +/*0ba0*/ 0x00027f6e, +/*0ba1*/ 0x00047f6e, +/*0ba2*/ 0x0003554f, +/*0ba3*/ 0x0001554f, +/*0ba4*/ 0x0001554f, +/*0ba5*/ 0x0001554f, +/*0ba6*/ 0x0001554f, +/*0ba7*/ 0x00003fee, +/*0ba8*/ 0x0001554f, +/*0ba9*/ 0x00003fee, +/*0baa*/ 0x0001554f, +/*0bab*/ 0x00027f6e, +/*0bac*/ 0x0001554f, +/*0bad*/ 0x00000000, +/*0bae*/ 0x00000000, +/*0baf*/ 0x00000000, +/*0bb0*/ 0x65000000, +/*0bb1*/ 0x00000000, +/*0bb2*/ 0x00000000, +/*0bb3*/ 0x00000201, +/*0bb4*/ 0x00000000, +/*0bb5*/ 0x00000000, +/*0bb6*/ 0x00000000, +/*0bb7*/ 0x00000000, +/*0bb8*/ 0x00000000, +/*0bb9*/ 0x00000000, +/*0bba*/ 0x00000000, +/*0bbb*/ 0x00000000, +/*0bbc*/ 0x06e40000, +/*0bbd*/ 0x00000000, +/*0bbe*/ 0x00000000, +/*0bbf*/ 0x00010000 +}; + +static const uint32_t DDR_PI_REGSET_M3[DDR_PI_REGSET_NUM_M3] = { +/*0200*/ 0x00000b00, +/*0201*/ 0x00000100, +/*0202*/ 0x00000000, +/*0203*/ 0x0000ffff, +/*0204*/ 0x00000000, +/*0205*/ 0x0000ffff, +/*0206*/ 0x00000000, +/*0207*/ 0x304cffff, +/*0208*/ 0x00000200, +/*0209*/ 0x00000200, +/*020a*/ 0x00000200, +/*020b*/ 0x00000200, +/*020c*/ 0x0000304c, +/*020d*/ 0x00000200, +/*020e*/ 0x00000200, +/*020f*/ 0x00000200, +/*0210*/ 0x00000200, +/*0211*/ 0x0000304c, +/*0212*/ 0x00000200, +/*0213*/ 0x00000200, +/*0214*/ 0x00000200, +/*0215*/ 0x00000200, +/*0216*/ 0x00010000, +/*0217*/ 0x00000003, +/*0218*/ 0x01000001, +/*0219*/ 0x00000000, +/*021a*/ 0x00000000, +/*021b*/ 0x00000000, +/*021c*/ 0x00000000, +/*021d*/ 0x00000000, +/*021e*/ 0x00000000, +/*021f*/ 0x00000000, +/*0220*/ 0x00000000, +/*0221*/ 0x00000000, +/*0222*/ 0x00000000, +/*0223*/ 0x00000000, +/*0224*/ 0x00000000, +/*0225*/ 0x00000000, +/*0226*/ 0x00000000, +/*0227*/ 0x00000000, +/*0228*/ 0x00000000, +/*0229*/ 0x0f000101, +/*022a*/ 0x08492d25, +/*022b*/ 0x0e0c0004, +/*022c*/ 0x000e5000, +/*022d*/ 0x00000250, +/*022e*/ 0x00460003, +/*022f*/ 0x182600cf, +/*0230*/ 0x182600cf, +/*0231*/ 0x00000005, +/*0232*/ 0x00000000, +/*0233*/ 0x00000000, +/*0234*/ 0x00000000, +/*0235*/ 0x00000000, +/*0236*/ 0x00000000, +/*0237*/ 0x00000000, +/*0238*/ 0x00000000, +/*0239*/ 0x01000000, +/*023a*/ 0x00040404, +/*023b*/ 0x01280a00, +/*023c*/ 0x00000000, +/*023d*/ 0x000f0000, +/*023e*/ 0x00001803, +/*023f*/ 0x00000000, +/*0240*/ 0x00000000, +/*0241*/ 0x00060002, +/*0242*/ 0x00010001, +/*0243*/ 0x01000101, +/*0244*/ 0x04020201, +/*0245*/ 0x00080804, +/*0246*/ 0x00000000, +/*0247*/ 0x08030000, +/*0248*/ 0x15150408, +/*0249*/ 0x00000000, +/*024a*/ 0x00000000, +/*024b*/ 0x00000000, +/*024c*/ 0x000f0f00, +/*024d*/ 0x0000001e, +/*024e*/ 0x00000000, +/*024f*/ 0x01000300, +/*0250*/ 0x00000000, +/*0251*/ 0x00000000, +/*0252*/ 0x01000000, +/*0253*/ 0x00010101, +/*0254*/ 0x000e0e0e, +/*0255*/ 0x000c0c0c, +/*0256*/ 0x02060601, +/*0257*/ 0x00000000, +/*0258*/ 0x00000003, +/*0259*/ 0x00181703, +/*025a*/ 0x00280006, +/*025b*/ 0x00280016, +/*025c*/ 0x00000016, +/*025d*/ 0x00000000, +/*025e*/ 0x00000000, +/*025f*/ 0x00000000, +/*0260*/ 0x140a0000, +/*0261*/ 0x0005010a, +/*0262*/ 0x03018d03, +/*0263*/ 0x000a018d, +/*0264*/ 0x00060100, +/*0265*/ 0x01000006, +/*0266*/ 0x018e018e, +/*0267*/ 0x018e0100, +/*0268*/ 0x1111018e, +/*0269*/ 0x10010204, +/*026a*/ 0x09090650, +/*026b*/ 0x20110202, +/*026c*/ 0x00201000, +/*026d*/ 0x00201000, +/*026e*/ 0x04041000, +/*026f*/ 0x18020100, +/*0270*/ 0x00010118, +/*0271*/ 0x004b004a, +/*0272*/ 0x050f0000, +/*0273*/ 0x0c01021e, +/*0274*/ 0x34000000, +/*0275*/ 0x00000000, +/*0276*/ 0x00000000, +/*0277*/ 0x00000000, +/*0278*/ 0x0000d400, +/*0279*/ 0x0031002e, +/*027a*/ 0x00111136, +/*027b*/ 0x002e00d4, +/*027c*/ 0x11360031, +/*027d*/ 0x0000d411, +/*027e*/ 0x0031002e, +/*027f*/ 0x00111136, +/*0280*/ 0x002e00d4, +/*0281*/ 0x11360031, +/*0282*/ 0x0000d411, +/*0283*/ 0x0031002e, +/*0284*/ 0x00111136, +/*0285*/ 0x002e00d4, +/*0286*/ 0x11360031, +/*0287*/ 0x00d40011, +/*0288*/ 0x0031002e, +/*0289*/ 0x00111136, +/*028a*/ 0x002e00d4, +/*028b*/ 0x11360031, +/*028c*/ 0x0000d411, +/*028d*/ 0x0031002e, +/*028e*/ 0x00111136, +/*028f*/ 0x002e00d4, +/*0290*/ 0x11360031, +/*0291*/ 0x0000d411, +/*0292*/ 0x0031002e, +/*0293*/ 0x00111136, +/*0294*/ 0x002e00d4, +/*0295*/ 0x11360031, +/*0296*/ 0x02000011, +/*0297*/ 0x018d018d, +/*0298*/ 0x0c08018d, +/*0299*/ 0x1f121d22, +/*029a*/ 0x4301b344, +/*029b*/ 0x10172006, +/*029c*/ 0x1d220c10, +/*029d*/ 0x00001f12, +/*029e*/ 0x4301b344, +/*029f*/ 0x10172006, +/*02a0*/ 0x1d220c10, +/*02a1*/ 0x00001f12, +/*02a2*/ 0x4301b344, +/*02a3*/ 0x10172006, +/*02a4*/ 0x02000210, +/*02a5*/ 0x02000200, +/*02a6*/ 0x02000200, +/*02a7*/ 0x02000200, +/*02a8*/ 0x02000200, +/*02a9*/ 0x00000000, +/*02aa*/ 0x00000000, +/*02ab*/ 0x00000000, +/*02ac*/ 0x00000000, +/*02ad*/ 0x00000000, +/*02ae*/ 0x00000000, +/*02af*/ 0x00000000, +/*02b0*/ 0x00000000, +/*02b1*/ 0x00000000, +/*02b2*/ 0x00000000, +/*02b3*/ 0x00000000, +/*02b4*/ 0x00000000, +/*02b5*/ 0x00000400, +/*02b6*/ 0x15141312, +/*02b7*/ 0x11100f0e, +/*02b8*/ 0x080b0c0d, +/*02b9*/ 0x05040a09, +/*02ba*/ 0x01000706, +/*02bb*/ 0x00000302, +/*02bc*/ 0x01030201, +/*02bd*/ 0x00304c00, +/*02be*/ 0x0001e2f8, +/*02bf*/ 0x0000304c, +/*02c0*/ 0x0001e2f8, +/*02c1*/ 0x0000304c, +/*02c2*/ 0x0001e2f8, +/*02c3*/ 0x08000000, +/*02c4*/ 0x00000100, +/*02c5*/ 0x00000000, +/*02c6*/ 0x00000000, +/*02c7*/ 0x00000000, +/*02c8*/ 0x00000000, +/*02c9*/ 0x00000002 +}; diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_m3n.h b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_m3n.h new file mode 100644 index 0000000..a840e0c --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ddr/init_dram_tbl_m3n.h @@ -0,0 +1,608 @@ +/* + * Copyright (c) 2015-2022, Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + */ + +#define DDR_PHY_SLICE_REGSET_OFS_M3N 0x0800 +#define DDR_PHY_ADR_V_REGSET_OFS_M3N 0x0a00 +#define DDR_PHY_ADR_I_REGSET_OFS_M3N 0x0a80 +#define DDR_PHY_ADR_G_REGSET_OFS_M3N 0x0b80 +#define DDR_PI_REGSET_OFS_M3N 0x0200 + +#define DDR_PHY_SLICE_REGSET_SIZE_M3N 0x80 +#define DDR_PHY_ADR_V_REGSET_SIZE_M3N 0x80 +#define DDR_PHY_ADR_I_REGSET_SIZE_M3N 0x80 +#define DDR_PHY_ADR_G_REGSET_SIZE_M3N 0x80 +#define DDR_PI_REGSET_SIZE_M3N 0x100 + +#define DDR_PHY_SLICE_REGSET_NUM_M3N 101 +#define DDR_PHY_ADR_V_REGSET_NUM_M3N 37 +#define DDR_PHY_ADR_I_REGSET_NUM_M3N 37 +#define DDR_PHY_ADR_G_REGSET_NUM_M3N 87 +#define DDR_PI_REGSET_NUM_M3N 286 + +static const uint32_t DDR_PHY_SLICE_REGSET_M3N[DDR_PHY_SLICE_REGSET_NUM_M3N] = { +/*0800*/ 0x76543210, +/*0801*/ 0x0004f008, +/*0802*/ 0x00020200, +/*0803*/ 0x00000000, +/*0804*/ 0x00000000, +/*0805*/ 0x00010000, +/*0806*/ 0x036e6e0e, +/*0807*/ 0x026e6e0e, +/*0808*/ 0x00000103, +/*0809*/ 0x00040001, +/*080a*/ 0x00000103, +/*080b*/ 0x00000001, +/*080c*/ 0x00000000, +/*080d*/ 0x00000000, +/*080e*/ 0x00000100, +/*080f*/ 0x001800c0, +/*0810*/ 0x020100b0, +/*0811*/ 0x00030020, +/*0812*/ 0x00000000, +/*0813*/ 0x00000000, +/*0814*/ 0x0000aaaa, +/*0815*/ 0x00005555, +/*0816*/ 0x0000b5b5, +/*0817*/ 0x00004a4a, +/*0818*/ 0x00000000, +/*0819*/ 0x09000000, +/*081a*/ 0x04080000, +/*081b*/ 0x08040000, +/*081c*/ 0x00000004, +/*081d*/ 0x00800710, +/*081e*/ 0x000f000c, +/*081f*/ 0x00000100, +/*0820*/ 0x55aa55aa, +/*0821*/ 0x33cc33cc, +/*0822*/ 0x0ff00ff0, +/*0823*/ 0x0f0ff0f0, +/*0824*/ 0x00018e38, +/*0825*/ 0x00000000, +/*0826*/ 0x00000000, +/*0827*/ 0x00000000, +/*0828*/ 0x00000000, +/*0829*/ 0x00000000, +/*082a*/ 0x00000000, +/*082b*/ 0x00000000, +/*082c*/ 0x00000000, +/*082d*/ 0x00000000, +/*082e*/ 0x00000000, +/*082f*/ 0x00000000, +/*0830*/ 0x00000000, +/*0831*/ 0x00000000, +/*0832*/ 0x00000000, +/*0833*/ 0x00000000, +/*0834*/ 0x00000000, +/*0835*/ 0x00000000, +/*0836*/ 0x00000000, +/*0837*/ 0x00000000, +/*0838*/ 0x00000000, +/*0839*/ 0x00000000, +/*083a*/ 0x00000104, +/*083b*/ 0x00082020, +/*083c*/ 0x08200820, +/*083d*/ 0x08200820, +/*083e*/ 0x08200820, +/*083f*/ 0x08200820, +/*0840*/ 0x08200820, +/*0841*/ 0x00000000, +/*0842*/ 0x00000000, +/*0843*/ 0x03000300, +/*0844*/ 0x03000300, +/*0845*/ 0x03000300, +/*0846*/ 0x03000300, +/*0847*/ 0x00000300, +/*0848*/ 0x00000000, +/*0849*/ 0x00000000, +/*084a*/ 0x00000000, +/*084b*/ 0x00000000, +/*084c*/ 0x00000000, +/*084d*/ 0x00a000a0, +/*084e*/ 0x00a000a0, +/*084f*/ 0x00a000a0, +/*0850*/ 0x00a000a0, +/*0851*/ 0x00a000a0, +/*0852*/ 0x00a000a0, +/*0853*/ 0x00a000a0, +/*0854*/ 0x00a000a0, +/*0855*/ 0x00a000a0, +/*0856*/ 0x01040119, +/*0857*/ 0x00000200, +/*0858*/ 0x01000000, +/*0859*/ 0x00000200, +/*085a*/ 0x00000004, +/*085b*/ 0x4041a151, +/*085c*/ 0x0141a0a0, +/*085d*/ 0x0000c0c0, +/*085e*/ 0x0e0c000e, +/*085f*/ 0x10001000, +/*0860*/ 0x0c073e42, +/*0861*/ 0x000f0c28, +/*0862*/ 0x00e00140, +/*0863*/ 0x000c0020, +/*0864*/ 0x00000203 +}; + +static const uint32_t DDR_PHY_ADR_V_REGSET_M3N[DDR_PHY_ADR_V_REGSET_NUM_M3N] = { +/*0a00*/ 0x00000000, +/*0a01*/ 0x00000000, +/*0a02*/ 0x00000000, +/*0a03*/ 0x00000000, +/*0a04*/ 0x00000000, +/*0a05*/ 0x00000000, +/*0a06*/ 0x00000000, +/*0a07*/ 0x01000000, +/*0a08*/ 0x00020000, +/*0a09*/ 0x00000000, +/*0a0a*/ 0x00000000, +/*0a0b*/ 0x00000000, +/*0a0c*/ 0x00400000, +/*0a0d*/ 0x00000080, +/*0a0e*/ 0x00dcba98, +/*0a0f*/ 0x03000000, +/*0a10*/ 0x00000200, +/*0a11*/ 0x00000000, +/*0a12*/ 0x00000000, +/*0a13*/ 0x00000000, +/*0a14*/ 0x0000002a, +/*0a15*/ 0x00000015, +/*0a16*/ 0x00000015, +/*0a17*/ 0x0000002a, +/*0a18*/ 0x00000033, +/*0a19*/ 0x0000000c, +/*0a1a*/ 0x0000000c, +/*0a1b*/ 0x00000033, +/*0a1c*/ 0x0a418820, +/*0a1d*/ 0x003f0000, +/*0a1e*/ 0x0000013f, +/*0a1f*/ 0x0002c06e, +/*0a20*/ 0x02c002c0, +/*0a21*/ 0x02c002c0, +/*0a22*/ 0x000002c0, +/*0a23*/ 0x42080010, +/*0a24*/ 0x0000033e +}; + +static const uint32_t DDR_PHY_ADR_I_REGSET_M3N[DDR_PHY_ADR_I_REGSET_NUM_M3N] = { +/*0a80*/ 0x00000000, +/*0a81*/ 0x00000000, +/*0a82*/ 0x00000000, +/*0a83*/ 0x00000000, +/*0a84*/ 0x00000000, +/*0a85*/ 0x00000000, +/*0a86*/ 0x00000000, +/*0a87*/ 0x01000000, +/*0a88*/ 0x00020000, +/*0a89*/ 0x00000000, +/*0a8a*/ 0x00000000, +/*0a8b*/ 0x00000000, +/*0a8c*/ 0x00400000, +/*0a8d*/ 0x00000080, +/*0a8e*/ 0x00000000, +/*0a8f*/ 0x03000000, +/*0a90*/ 0x00000200, +/*0a91*/ 0x00000000, +/*0a92*/ 0x00000000, +/*0a93*/ 0x00000000, +/*0a94*/ 0x0000002a, +/*0a95*/ 0x00000015, +/*0a96*/ 0x00000015, +/*0a97*/ 0x0000002a, +/*0a98*/ 0x00000033, +/*0a99*/ 0x0000000c, +/*0a9a*/ 0x0000000c, +/*0a9b*/ 0x00000033, +/*0a9c*/ 0x00000000, +/*0a9d*/ 0x00000000, +/*0a9e*/ 0x00000000, +/*0a9f*/ 0x0002c06e, +/*0aa0*/ 0x02c002c0, +/*0aa1*/ 0x02c002c0, +/*0aa2*/ 0x000002c0, +/*0aa3*/ 0x42080010, +/*0aa4*/ 0x0000033e +}; + +static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = { +/*0b80*/ 0x00000000, +/*0b81*/ 0x00000100, +/*0b82*/ 0x00000000, +/*0b83*/ 0x00050000, +/*0b84*/ 0x00000000, +/*0b85*/ 0x0004000f, +/*0b86*/ 0x00280080, +/*0b87*/ 0x02005502, +/*0b88*/ 0x00000000, +/*0b89*/ 0x00000000, +/*0b8a*/ 0x00000000, +/*0b8b*/ 0x00000050, +/*0b8c*/ 0x00000000, +/*0b8d*/ 0x01010100, +/*0b8e*/ 0x00010000, +/*0b8f*/ 0x00000000, +/*0b90*/ 0x00000101, +/*0b91*/ 0x00000000, +/*0b92*/ 0x00000000, +/*0b93*/ 0x00000000, +/*0b94*/ 0x00000000, +/*0b95*/ 0x00005064, +/*0b96*/ 0x05421542, +/*0b97*/ 0x00000542, +/*0b98*/ 0x00000000, +/*0b99*/ 0x000f1600, +/*0b9a*/ 0x0f160f16, +/*0b9b*/ 0x0f160f16, +/*0b9c*/ 0x00000003, +/*0b9d*/ 0x0002c000, +/*0b9e*/ 0x02c002c0, +/*0b9f*/ 0x000002c0, +/*0ba0*/ 0x08040201, +/*0ba1*/ 0x05421542, +/*0ba2*/ 0x00000542, +/*0ba3*/ 0x00000000, +/*0ba4*/ 0x00000000, +/*0ba5*/ 0x05030000, +/*0ba6*/ 0x00010701, +/*0ba7*/ 0x00000014, +/*0ba8*/ 0x00027f6e, +/*0ba9*/ 0x047f027f, +/*0baa*/ 0x00027f6e, +/*0bab*/ 0x00047f6e, +/*0bac*/ 0x0003554f, +/*0bad*/ 0x0001554f, +/*0bae*/ 0x0001554f, +/*0baf*/ 0x0001554f, +/*0bb0*/ 0x0001554f, +/*0bb1*/ 0x00003fee, +/*0bb2*/ 0x0001554f, +/*0bb3*/ 0x00003fee, +/*0bb4*/ 0x0001554f, +/*0bb5*/ 0x00027f6e, +/*0bb6*/ 0x0001554f, +/*0bb7*/ 0x00004011, +/*0bb8*/ 0x00004410, +/*0bb9*/ 0x00000000, +/*0bba*/ 0x00000000, +/*0bbb*/ 0x00000000, +/*0bbc*/ 0x00000265, +/*0bbd*/ 0x00000000, +/*0bbe*/ 0x00040401, +/*0bbf*/ 0x00000000, +/*0bc0*/ 0x03000000, +/*0bc1*/ 0x00000020, +/*0bc2*/ 0x00000000, +/*0bc3*/ 0x00000000, +/*0bc4*/ 0x04102006, +/*0bc5*/ 0x00041020, +/*0bc6*/ 0x01c98c98, +/*0bc7*/ 0x00400000, +/*0bc8*/ 0x00000000, +/*0bc9*/ 0x0001ffff, +/*0bca*/ 0x00000000, +/*0bcb*/ 0x00000000, +/*0bcc*/ 0x00000001, +/*0bcd*/ 0x00000000, +/*0bce*/ 0x00000000, +/*0bcf*/ 0x00000000, +/*0bd0*/ 0x76543210, +/*0bd1*/ 0x06010198, +/*0bd2*/ 0x00000000, +/*0bd3*/ 0x00000000, +/*0bd4*/ 0x04070000, +/*0bd5*/ 0x00000001, +/*0bd6*/ 0x00000f00 +}; + +static const uint32_t DDR_PI_REGSET_M3N[DDR_PI_REGSET_NUM_M3N] = { +/*0200*/ 0x00000b00, +/*0201*/ 0x00000101, +/*0202*/ 0x01640000, +/*0203*/ 0x00000014, +/*0204*/ 0x00000014, +/*0205*/ 0x00000014, +/*0206*/ 0x00000014, +/*0207*/ 0x00000000, +/*0208*/ 0x00000000, +/*0209*/ 0x0000ffff, +/*020a*/ 0x00000000, +/*020b*/ 0x0000ffff, +/*020c*/ 0x00000000, +/*020d*/ 0x0000ffff, +/*020e*/ 0x0000304c, +/*020f*/ 0x00000200, +/*0210*/ 0x00000200, +/*0211*/ 0x00000200, +/*0212*/ 0x00000200, +/*0213*/ 0x0000304c, +/*0214*/ 0x00000200, +/*0215*/ 0x00000200, +/*0216*/ 0x00000200, +/*0217*/ 0x00000200, +/*0218*/ 0x0000304c, +/*0219*/ 0x00000200, +/*021a*/ 0x00000200, +/*021b*/ 0x00000200, +/*021c*/ 0x00000200, +/*021d*/ 0x00010000, +/*021e*/ 0x00000003, +/*021f*/ 0x01000001, +/*0220*/ 0x00000000, +/*0221*/ 0x00000000, +/*0222*/ 0x00000000, +/*0223*/ 0x00000000, +/*0224*/ 0x00000000, +/*0225*/ 0x00000000, +/*0226*/ 0x00000000, +/*0227*/ 0x00000000, +/*0228*/ 0x00000000, +/*0229*/ 0x00000000, +/*022a*/ 0x00000000, +/*022b*/ 0x00000000, +/*022c*/ 0x00000000, +/*022d*/ 0x00000000, +/*022e*/ 0x00000000, +/*022f*/ 0x00000000, +/*0230*/ 0x0f000101, +/*0231*/ 0x084d3129, +/*0232*/ 0x0e0c0004, +/*0233*/ 0x000e5000, +/*0234*/ 0x01000250, +/*0235*/ 0x00000003, +/*0236*/ 0x00000046, +/*0237*/ 0x000000cf, +/*0238*/ 0x00001826, +/*0239*/ 0x000000cf, +/*023a*/ 0x00001826, +/*023b*/ 0x00000000, +/*023c*/ 0x00000000, +/*023d*/ 0x00000000, +/*023e*/ 0x00000000, +/*023f*/ 0x00000000, +/*0240*/ 0x00000000, +/*0241*/ 0x00000000, +/*0242*/ 0x00000000, +/*0243*/ 0x00000000, +/*0244*/ 0x00000000, +/*0245*/ 0x01000000, +/*0246*/ 0x00040404, +/*0247*/ 0x01280a00, +/*0248*/ 0x00000001, +/*0249*/ 0x00000000, +/*024a*/ 0x03000f00, +/*024b*/ 0x00200020, +/*024c*/ 0x00000020, +/*024d*/ 0x00000000, +/*024e*/ 0x00000000, +/*024f*/ 0x00010002, +/*0250*/ 0x01010001, +/*0251*/ 0x02010100, +/*0252*/ 0x08040402, +/*0253*/ 0x00000008, +/*0254*/ 0x00000000, +/*0255*/ 0x04080803, +/*0256*/ 0x00001515, +/*0257*/ 0x00000000, +/*0258*/ 0x000000aa, +/*0259*/ 0x00000055, +/*025a*/ 0x000000b5, +/*025b*/ 0x0000004a, +/*025c*/ 0x00000056, +/*025d*/ 0x000000a9, +/*025e*/ 0x000000a9, +/*025f*/ 0x000000b5, +/*0260*/ 0x00000000, +/*0261*/ 0x00000000, +/*0262*/ 0x0f000000, +/*0263*/ 0x00001e0f, +/*0264*/ 0x000007d0, +/*0265*/ 0x01000300, +/*0266*/ 0x00000100, +/*0267*/ 0x00000000, +/*0268*/ 0x00000000, +/*0269*/ 0x01000000, +/*026a*/ 0x00010101, +/*026b*/ 0x000e0e0e, +/*026c*/ 0x000c0c0c, +/*026d*/ 0x01060601, +/*026e*/ 0x04041717, +/*026f*/ 0x00000004, +/*0270*/ 0x00000300, +/*0271*/ 0x17030000, +/*0272*/ 0x00060018, +/*0273*/ 0x00160028, +/*0274*/ 0x00160028, +/*0275*/ 0x00000000, +/*0276*/ 0x00000000, +/*0277*/ 0x00000000, +/*0278*/ 0x0a000000, +/*0279*/ 0x00010a14, +/*027a*/ 0x00030005, +/*027b*/ 0x0003018d, +/*027c*/ 0x000a018d, +/*027d*/ 0x00060100, +/*027e*/ 0x01000006, +/*027f*/ 0x018e018e, +/*0280*/ 0x018e0100, +/*0281*/ 0x1e1a018e, +/*0282*/ 0x1e1a1e1a, +/*0283*/ 0x01010204, +/*0284*/ 0x06501001, +/*0285*/ 0x090d0a07, +/*0286*/ 0x090d0a07, +/*0287*/ 0x0811180f, +/*0288*/ 0x00ff1102, +/*0289*/ 0x00ff1000, +/*028a*/ 0x00ff1000, +/*028b*/ 0x04041000, +/*028c*/ 0x18020100, +/*028d*/ 0x01010018, +/*028e*/ 0x005f005f, +/*028f*/ 0x005f005f, +/*0290*/ 0x050f0000, +/*0291*/ 0x051e051e, +/*0292*/ 0x0c01021e, +/*0293*/ 0x00000c0c, +/*0294*/ 0x00003400, +/*0295*/ 0x00000000, +/*0296*/ 0x00000000, +/*0297*/ 0x00000000, +/*0298*/ 0x00000000, +/*0299*/ 0x002e00d4, +/*029a*/ 0x11360031, +/*029b*/ 0x00d41611, +/*029c*/ 0x0031002e, +/*029d*/ 0x16111136, +/*029e*/ 0x002e00d4, +/*029f*/ 0x11360031, +/*02a0*/ 0x00001611, +/*02a1*/ 0x002e00d4, +/*02a2*/ 0x11360031, +/*02a3*/ 0x00d41611, +/*02a4*/ 0x0031002e, +/*02a5*/ 0x16111136, +/*02a6*/ 0x002e00d4, +/*02a7*/ 0x11360031, +/*02a8*/ 0x00001611, +/*02a9*/ 0x002e00d4, +/*02aa*/ 0x11360031, +/*02ab*/ 0x00d41611, +/*02ac*/ 0x0031002e, +/*02ad*/ 0x16111136, +/*02ae*/ 0x002e00d4, +/*02af*/ 0x11360031, +/*02b0*/ 0x00001611, +/*02b1*/ 0x002e00d4, +/*02b2*/ 0x11360031, +/*02b3*/ 0x00d41611, +/*02b4*/ 0x0031002e, +/*02b5*/ 0x16111136, +/*02b6*/ 0x002e00d4, +/*02b7*/ 0x11360031, +/*02b8*/ 0x00001611, +/*02b9*/ 0x00018d00, +/*02ba*/ 0x018d018d, +/*02bb*/ 0x1d220c08, +/*02bc*/ 0x00001f12, +/*02bd*/ 0x4301b344, +/*02be*/ 0x17032006, +/*02bf*/ 0x220c1010, +/*02c0*/ 0x001f121d, +/*02c1*/ 0x4301b344, +/*02c2*/ 0x17062006, +/*02c3*/ 0x220c1010, +/*02c4*/ 0x001f121d, +/*02c5*/ 0x4301b344, +/*02c6*/ 0x17182006, +/*02c7*/ 0x00021010, +/*02c8*/ 0x00020002, +/*02c9*/ 0x00020002, +/*02ca*/ 0x00020002, +/*02cb*/ 0x00020002, +/*02cc*/ 0x00000002, +/*02cd*/ 0x00000000, +/*02ce*/ 0x00000000, +/*02cf*/ 0x00000000, +/*02d0*/ 0x00000000, +/*02d1*/ 0x00000000, +/*02d2*/ 0x00000000, +/*02d3*/ 0x00000000, +/*02d4*/ 0x00000000, +/*02d5*/ 0x00000000, +/*02d6*/ 0x00000000, +/*02d7*/ 0x00000000, +/*02d8*/ 0x00000000, +/*02d9*/ 0x00000400, +/*02da*/ 0x15141312, +/*02db*/ 0x11100f0e, +/*02dc*/ 0x080b0c0d, +/*02dd*/ 0x05040a09, +/*02de*/ 0x01000706, +/*02df*/ 0x00000302, +/*02e0*/ 0x01030201, +/*02e1*/ 0x00304c08, +/*02e2*/ 0x0001e2f8, +/*02e3*/ 0x0000304c, +/*02e4*/ 0x0001e2f8, +/*02e5*/ 0x0000304c, +/*02e6*/ 0x0001e2f8, +/*02e7*/ 0x08000000, +/*02e8*/ 0x00000100, +/*02e9*/ 0x00000000, +/*02ea*/ 0x00000000, +/*02eb*/ 0x00000000, +/*02ec*/ 0x00000000, +/*02ed*/ 0x00010000, +/*02ee*/ 0x00000000, +/*02ef*/ 0x00000000, +/*02f0*/ 0x00000000, +/*02f1*/ 0x00000000, +/*02f2*/ 0x00000000, +/*02f3*/ 0x00000000, +/*02f4*/ 0x00000000, +/*02f5*/ 0x00000000, +/*02f6*/ 0x00000000, +/*02f7*/ 0x00000000, +/*02f8*/ 0x00000000, +/*02f9*/ 0x00000000, +/*02fa*/ 0x00000000, +/*02fb*/ 0x00000000, +/*02fc*/ 0x00000000, +/*02fd*/ 0x00000000, +/*02fe*/ 0x00000000, +/*02ff*/ 0x00000000, +/*0300*/ 0x00000000, +/*0301*/ 0x00000000, +/*0302*/ 0x00000000, +/*0303*/ 0x00000000, +/*0304*/ 0x00000000, +/*0305*/ 0x00000000, +/*0306*/ 0x00000000, +/*0307*/ 0x00000000, +/*0308*/ 0x00000000, +/*0309*/ 0x00000000, +/*030a*/ 0x00000000, +/*030b*/ 0x00000000, +/*030c*/ 0x00000000, +/*030d*/ 0x00000000, +/*030e*/ 0x00000000, +/*030f*/ 0x00050002, +/*0310*/ 0x015c0057, +/*0311*/ 0x01000100, +/*0312*/ 0x01020001, +/*0313*/ 0x00010300, +/*0314*/ 0x05000104, +/*0315*/ 0x01060001, +/*0316*/ 0x00010700, +/*0317*/ 0x00000000, +/*0318*/ 0x00000000, +/*0319*/ 0x00000001, +/*031a*/ 0x00000000, +/*031b*/ 0x00000000, +/*031c*/ 0x00000000, +/*031d*/ 0x20080101 +}; diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/dma/dma.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/dma/dma.c new file mode 100644 index 0000000..69f0d3e --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/dma/dma.c @@ -0,0 +1,142 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : DMA driver + ******************************************************************************/ +/****************************************************************************** + * @file dma.c + * - Version : 0.01 + * @brief DMA driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define RDMOR_INIT (uint16_t)(0x0301U) +#define RDMOR_HW_INIT (uint16_t)(0x0000U) +#define RDMTCR_CNT_SHIFT (6U) +#define RDMCHCR_TRN_MODE (0x00105409U) +#define RDMCHCR_TE_BIT (0x00000002U) +#define TE_FLAG (0x00000000U) +#define RDMCHCR_CAE_BIT (0x80000000U) +#define RDMCHCR_CAE_BIT_NOERROR (0x00000000U) + +/* fraction mask for 64-byte units */ +#define FRACTION_MASK_64_BYTE (0x0000003FU) +/* fraction mask for 256-byte units */ +#define FRACTION_MASK_256_BYTE (0x000000FFU) + +void dma_init(void) +{ + uint32_t reg; + + /* DMA channel clear */ + mem_write32(DMA_RDMCHCLR, ((uint32_t)1U << DMACH)); + + /* DMA operation */ + mem_write16(DMA_RDMOR, RDMOR_INIT); + /* DMA secure control register */ + reg = mem_read32(DMA_RDMSEC); + reg |= ((uint32_t)1U << DMACH); + mem_write32(DMA_RDMSEC, reg); +} +/* End of function dma_init(void) */ + +void load_start(uint32_t dst, uint32_t src, uint32_t len) +{ + if (((dst & FRACTION_MASK_64_BYTE) != 0U) || ((src & FRACTION_MASK_64_BYTE) != 0U)) + { + /* dst or src are not 64-bit alignment. */ + ERROR("not 64-bit alignment in DMA transfer\n"); + panic; + } + + /* round up 256 byte alignment */ + len += FRACTION_MASK_256_BYTE; + len &= (~(uint32_t)(FRACTION_MASK_256_BYTE)); + + /* DMA destination address */ + mem_write32(DMA_RDMDAR(DMACH), dst); + /* DMA source address */ + mem_write32(DMA_RDMSAR(DMACH), src); + /* DMA 64bytes-unit transfer count */ + mem_write32(DMA_RDMTCR(DMACH), (len >> RDMTCR_CNT_SHIFT)); + /* DMA channel control */ + mem_write32(DMA_RDMCHCR(DMACH), RDMCHCR_TRN_MODE); +} +/* End of function load_start(uint32_t dst, uint32_t src, uint32_t len) */ + +void load_end(void) +{ + /* Check end of DMA transfer. */ + do + { + /* Reset the timer count of the Window Watchdog Timer. */ + wdt_restart(); + + /* Check error of DMA transfer */ + if ((mem_read32(DMA_RDMCHCR(DMACH)) & RDMCHCR_CAE_BIT) != RDMCHCR_CAE_BIT_NOERROR) + { + ERROR("DMA - Channel Address Error\n"); + panic; + } + } while ((mem_read32(DMA_RDMCHCR(DMACH)) & RDMCHCR_TE_BIT) == TE_FLAG); + + /* DMA channel clear */ + mem_write32(DMA_RDMCHCLR, ((uint32_t)1U << DMACH)); + + rpc_end_state_check(); +} +/* End of function load_end(void) */ + +void dma_release(void) +{ + uint32_t reg; + + /* DMA channel clear */ + mem_write32(DMA_RDMCHCLR, ((uint32_t)1U << DMACH)); + reg = mem_read32(DMA_RDMSEC); + reg &= (~((uint32_t)1U << DMACH)); + mem_write32(DMA_RDMSEC, reg); +} +/* End of function dma_release(void) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ip_control.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ip_control.c new file mode 100644 index 0000000..6d0b968 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/ip_control.c @@ -0,0 +1,69 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : IP's control function + ******************************************************************************/ +/****************************************************************************** + * @file ip_control.c + * - Version : 0.01 + * @brief Initial setting controller. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +void ip_init(void) +{ + scif_init(); + cpg_init(); + pfc_init(); + dma_init(); + rpc_init(); + mfis_init(); + edc_init(); +} +/* End of function ip_init(void) */ + +void ip_release(void) +{ + rpc_release(); + dma_release(); + scif_release(); +} +/* End of function ip_release(void) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/mfis/mfis.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/mfis/mfis.c new file mode 100644 index 0000000..125c20d --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/mfis/mfis.c @@ -0,0 +1,99 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MFIS driver + ******************************************************************************/ +/****************************************************************************** + * @file mfis.c + * - Version : 0.01 + * @brief Initial setting process of MFIS. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ +#include /* for uint32_t */ +#include +#include +#include +#include + +#define MFIS_EXTRQHLDCNTR_TIMER_COUNT (0x80000001U) + +void mfis_init(void) +{ + uint32_t loop; + const MFIS_SETTING_TABLE mfis_tbl[] = { + /* address value */ + { MFIS_MFIERRCTLR0 , 0xBFFBFB70U }, + { MFIS_MFIERRCTLR1 , 0x3607FFE8U }, + { MFIS_MFIERRCTLR2 , 0xFFFFFFFFU }, + { MFIS_MFIERRCTLR3 , 0x9FFFFFFFU }, + { MFIS_MFIERRCTLR4 , 0x13B9E8FFU }, + { MFIS_MFIERRCTLR5 , 0x00000000U }, + { MFIS_MFIERRCTLR6 , 0x00000000U }, + { MFIS_MFIERRCTLR7 , 0xFFFF6D7FU }, + { MFIS_MFIERRCTLR8 , 0x01FF0FFFU }, + { MFIS_MFIERRCTLR9 , 0xFF00175FU }, + { MFIS_MFIERRCTLR10 , 0x00000000U }, + { MFIS_MFIERRCTLR11 , 0x00000000U }, + { MFIS_MFIERRCTLR12 , 0x2550780FU }, + { MFIS_MFIERRCTLR13 , 0x00003F7FU }, + + { MFIS_MFIERRTGTR0 , 0x8F080000U }, + { MFIS_MFIERRTGTR1 , 0x00000400U }, + { MFIS_MFIERRTGTR2 , 0x00000000U }, + { MFIS_MFIERRTGTR3 , 0x00000000U }, + { MFIS_MFIERRTGTR4 , 0x02000000U }, + { MFIS_MFIERRTGTR5 , 0x00000000U }, + { MFIS_MFIERRTGTR6 , 0x00000000U }, + { MFIS_MFIERRTGTR7 , 0x02AA002AU }, + { MFIS_MFIERRTGTR8 , 0x007F00A0U }, + { MFIS_MFIERRTGTR9 , 0xFD000000U }, + { MFIS_MFIERRTGTR10 , 0x00000000U }, + { MFIS_MFIERRTGTR11 , 0x00000000U }, + { MFIS_MFIERRTGTR12 , 0x00000000U }, + { MFIS_MFIERRTGTR13 , 0x00000000U } + }; + + /* removed write protection of MFIS */ + mem_write32(MFIS_MFISWPCNTR, (MFIS_PROT_CODEVALUE | MFISWPCNTR_WPD_BIT)); + + /* sets the error detection enable / disable and * + * the output destination of the detected error */ + for (loop = 0U; loop < (sizeof(mfis_tbl) / sizeof(mfis_tbl[0])); loop++) + { + mem_write32(mfis_tbl[loop].address, mfis_tbl[loop].value); + } + + /* setting for controlling time that error request is holded */ + mem_write32(MFIS_MFIEXTRQMSKCNTR, MFIS_EXTRQHLDCNTR_TIMER_COUNT); +} +/* End of function mfis_init(void) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/pfc/pfc.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/pfc/pfc.c new file mode 100644 index 0000000..52bedde --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/pfc/pfc.c @@ -0,0 +1,1047 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : PFC driver + ******************************************************************************/ + /****************************************************************************** + * @file pfc.c + * - Version : 0.01 + * @brief Initial setting process of PFC. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include /* for uint32_t */ +#include +#include +#include + + +#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) +#define GPSR0_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) +#define GPSR0_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) +#define GPSR0_DU_EXHSYNC_DU_HSYNC_A ((uint32_t)0U << 19U) +#define GPSR0_DU_DOTCLKOUT ((uint32_t)1U << 18U) +#define GPSR0_DU_DB7 ((uint32_t)1U << 17U) +#define GPSR0_DU_DB6 ((uint32_t)1U << 16U) +#define GPSR0_DU_DB5 ((uint32_t)1U << 15U) +#define GPSR0_DU_DB4 ((uint32_t)1U << 14U) +#define GPSR0_DU_DB3 ((uint32_t)1U << 13U) +#define GPSR0_DU_DB2 ((uint32_t)1U << 12U) +#define GPSR0_DU_DG7 ((uint32_t)1U << 11U) +#define GPSR0_DU_DG6 ((uint32_t)1U << 10U) +#define GPSR0_DU_DG5 ((uint32_t)1U << 9U) +#define GPSR0_DU_DG4 ((uint32_t)1U << 8U) +#define GPSR0_DU_DG3 ((uint32_t)1U << 7U) +#define GPSR0_DU_DG2 ((uint32_t)1U << 6U) +#define GPSR0_DU_DR7 ((uint32_t)1U << 5U) +#define GPSR0_DU_DR6 ((uint32_t)1U << 4U) +#define GPSR0_DU_DR5 ((uint32_t)1U << 3U) +#define GPSR0_DU_DR4 ((uint32_t)1U << 2U) +#define GPSR0_DU_DR3 ((uint32_t)1U << 1U) +#define GPSR0_DU_DR2 ((uint32_t)1U << 0U) +#define GPSR1_DIGRF_CLKOUT ((uint32_t)1U << 27U) +#define GPSR1_DIGRF_CLKIN ((uint32_t)1U << 26U) +#define GPSR1_CANFD_CLK_A ((uint32_t)1U << 25U) +#define GPSR1_CANFD1_RX ((uint32_t)1U << 24U) +#define GPSR1_CANFD1_TX ((uint32_t)1U << 23U) +#define GPSR1_CANFD0_RX_A ((uint32_t)1U << 22U) +#define GPSR1_CANFD0_TX_A ((uint32_t)1U << 21U) +#define GPSR1_AVB_AVTP_CAPTURE ((uint32_t)1U << 20U) +#define GPSR1_AVB_AVTP_MATCH ((uint32_t)1U << 19U) +#define GPSR1_AVB_LINK ((uint32_t)1U << 18U) +#define GPSR1_AVB_PHY_INT ((uint32_t)1U << 17U) +#define GPSR1_AVB_MAGIC ((uint32_t)1U << 16U) +#define GPSR1_AVB_MDC ((uint32_t)1U << 15U) +#define GPSR1_AVB_MDIO ((uint32_t)1U << 14U) +#define GPSR1_AVB_TXCREFCLK ((uint32_t)1U << 13U) +#define GPSR1_AVB_TD3 ((uint32_t)1U << 12U) +#define GPSR1_AVB_TD2 ((uint32_t)1U << 11U) +#define GPSR1_AVB_TD1 ((uint32_t)1U << 10U) +#define GPSR1_AVB_TD0 ((uint32_t)1U << 9U) +#define GPSR1_AVB_TXC ((uint32_t)1U << 8U) +#define GPSR1_AVB_TX_CTL ((uint32_t)1U << 7U) +#define GPSR1_AVB_RD3 ((uint32_t)1U << 6U) +#define GPSR1_AVB_RD2 ((uint32_t)1U << 5U) +#define GPSR1_AVB_RD1 ((uint32_t)1U << 4U) +#define GPSR1_AVB_RD0 ((uint32_t)1U << 3U) +#define GPSR1_AVB_RXC ((uint32_t)1U << 2U) +#define GPSR1_AVB_RX_CTL ((uint32_t)1U << 1U) +#define GPSR1_IRQ0 ((uint32_t)1U << 0U) +#define GPSR2_FSO_TOE ((uint32_t)1U << 29U) +#define GPSR2_FSO_CFE_1 ((uint32_t)1U << 28U) +#define GPSR2_FSO_CFE_0 ((uint32_t)1U << 27U) +#define GPSR2_SDA3 ((uint32_t)1U << 26U) +#define GPSR2_SCL3 ((uint32_t)1U << 25U) +#define GPSR2_MSIOF0_SS2 ((uint32_t)1U << 24U) +#define GPSR2_MSIOF0_SS1 ((uint32_t)1U << 23U) +#define GPSR2_MSIOF0_SYNC ((uint32_t)1U << 22U) +#define GPSR2_MSIOF0_SCK ((uint32_t)1U << 21U) +#define GPSR2_MSIOF0_TXD ((uint32_t)1U << 20U) +#define GPSR2_MSIOF0_RXD ((uint32_t)1U << 19U) +#define GPSR2_IRQ5 ((uint32_t)1U << 18U) +#define GPSR2_IRQ4 ((uint32_t)1U << 17U) +#define GPSR2_VI0_FIELD ((uint32_t)1U << 16U) +#define GPSR2_VI0_DATA11 ((uint32_t)1U << 15U) +#define GPSR2_VI0_DATA10 ((uint32_t)1U << 14U) +#define GPSR2_VI0_DATA9 ((uint32_t)1U << 13U) +#define GPSR2_VI0_DATA8 ((uint32_t)1U << 12U) +#define GPSR2_VI0_DATA7 ((uint32_t)1U << 11U) +#define GPSR2_VI0_DATA6 ((uint32_t)1U << 10U) +#define GPSR2_VI0_DATA5 ((uint32_t)1U << 9U) +#define GPSR2_VI0_DATA4 ((uint32_t)1U << 8U) +#define GPSR2_VI0_DATA3 ((uint32_t)1U << 7U) +#define GPSR2_VI0_DATA2 ((uint32_t)1U << 6U) +#define GPSR2_VI0_DATA1 ((uint32_t)1U << 5U) +#define GPSR2_VI0_DATA0 ((uint32_t)1U << 4U) +#define GPSR2_VI0_VSYNC ((uint32_t)1U << 3U) +#define GPSR2_VI0_HSYNC ((uint32_t)1U << 2U) +#define GPSR2_VI0_CLKENB ((uint32_t)1U << 1U) +#define GPSR2_VI0_CLK ((uint32_t)1U << 0U) +#define GPSR3_VI1_FIELD ((uint32_t)1U << 16U) +#define GPSR3_VI1_DATA11 ((uint32_t)1U << 15U) +#define GPSR3_VI1_DATA10 ((uint32_t)1U << 14U) +#define GPSR3_VI1_DATA9 ((uint32_t)1U << 13U) +#define GPSR3_VI1_DATA8 ((uint32_t)1U << 12U) +#define GPSR3_VI1_DATA7 ((uint32_t)1U << 11U) +#define GPSR3_VI1_DATA6 ((uint32_t)1U << 10U) +#define GPSR3_VI1_DATA5 ((uint32_t)1U << 9U) +#define GPSR3_VI1_DATA4 ((uint32_t)1U << 8U) +#define GPSR3_VI1_DATA3 ((uint32_t)1U << 7U) +#define GPSR3_VI1_DATA2 ((uint32_t)1U << 6U) +#define GPSR3_VI1_DATA1 ((uint32_t)1U << 5U) +#define GPSR3_VI1_DATA0 ((uint32_t)1U << 4U) +#define GPSR3_VI1_VSYNC ((uint32_t)1U << 3U) +#define GPSR3_VI1_HSYNC ((uint32_t)1U << 2U) +#define GPSR3_VI1_CLKENB ((uint32_t)1U << 1U) +#define GPSR3_VI1_CLK ((uint32_t)1U << 0U) +#define GPSR4_GETHER_LINK_A ((uint32_t)1U << 24U) +#define GPSR4_GETHER_PHY_INT_A ((uint32_t)1U << 23U) +#define GPSR4_GETHER_MAGIC ((uint32_t)1U << 22U) +#define GPSR4_GETHER_MDC_A ((uint32_t)1U << 21U) +#define GPSR4_GETHER_MDIO_A ((uint32_t)1U << 20U) +#define GPSR4_GETHER_TXCREFCLK_MEGA ((uint32_t)1U << 19U) +#define GPSR4_GETHER_TXCREFCLK ((uint32_t)1U << 18U) +#define GPSR4_GETHER_TD3 ((uint32_t)1U << 17U) +#define GPSR4_GETHER_TD2 ((uint32_t)1U << 16U) +#define GPSR4_GETHER_TD1 ((uint32_t)1U << 15U) +#define GPSR4_GETHER_TD0 ((uint32_t)1U << 14U) +#define GPSR4_GETHER_TXC ((uint32_t)1U << 13U) +#define GPSR4_GETHER_TX_CTL ((uint32_t)1U << 12U) +#define GPSR4_GETHER_RD3 ((uint32_t)1U << 11U) +#define GPSR4_GETHER_RD2 ((uint32_t)1U << 10U) +#define GPSR4_GETHER_RD1 ((uint32_t)1U << 9U) +#define GPSR4_GETHER_RD0 ((uint32_t)1U << 8U) +#define GPSR4_GETHER_RXC ((uint32_t)1U << 7U) +#define GPSR4_GETHER_RX_CTL ((uint32_t)1U << 6U) +#define GPSR4_SDA2 ((uint32_t)1U << 5U) +#define GPSR4_SCL2 ((uint32_t)1U << 4U) +#define GPSR4_SDA1 ((uint32_t)1U << 3U) +#define GPSR4_SCL1 ((uint32_t)1U << 2U) +#define GPSR4_SDA0 ((uint32_t)1U << 1U) +#define GPSR4_SCL0 ((uint32_t)1U << 0U) +#define GPSR5_RPC_INT ((uint32_t)1U << 14U) +#define GPSR5_RPC_WP ((uint32_t)1U << 13U) +#define GPSR5_RPC_RESET ((uint32_t)1U << 12U) +#define GPSR5_QSPI1_SSL ((uint32_t)1U << 11U) +#define GPSR5_QSPI1_IO3 ((uint32_t)1U << 10U) +#define GPSR5_QSPI1_IO2 ((uint32_t)1U << 9U) +#define GPSR5_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) +#define GPSR5_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) +#define GPSR5_QSPI1_SPCLK ((uint32_t)1U << 6U) +#define GPSR5_QSPI0_SSL ((uint32_t)1U << 5U) +#define GPSR5_QSPI0_IO3 ((uint32_t)1U << 4U) +#define GPSR5_QSPI0_IO2 ((uint32_t)1U << 3U) +#define GPSR5_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) +#define GPSR5_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) +#define GPSR5_QSPI0_SPCLK ((uint32_t)1U << 0U) + +/* Macro to calculate the set value of IPSR.(for bit31:28) */ +#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) +/* Macro to calculate the set value of IPSR.(for bit27:24) */ +#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) +/* Macro to calculate the set value of IPSR.(for bit23:20) */ +#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) +/* Macro to calculate the set value of IPSR.(for bit19:16) */ +#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) +/* Macro to calculate the set value of IPSR.(for bit15:12) */ +#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) +/* Macro to calculate the set value of IPSR.(for bit11:8) */ +#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) +/* Macro to calculate the set value of IPSR.(for bit7:4) */ +#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) +/* Macro to calculate the set value of IPSR.(for bit3:0) */ +#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) + +#define IOCTRL0_MASK (0x00000000U) +#define IOCTRL1_MASK (0x00000000U) +#define IOCTRL2_MASK (0x00000000U) +#define IOCTRL3_MASK (0x00000000U) +#define IOCTRL4_MASK (0x00000000U) +#define IOCTRL5_MASK (0x00000000U) +#define IOCTRL6_MASK (0x00000000U) +#define IOCTRL7_MASK (0x00000000U) +#define IOCTRL8_MASK (0x00000000U) +#define IOCTRL9_MASK (0x00000000U) +#define IOCTRL10_MASK (0x00000000U) +#define IOCTRL11_MASK (0x00000000U) +#define IOCTRL12_MASK (0x00000000U) +#define IOCTRL13_MASK (0x00000000U) +#define IOCTRL14_MASK (0x00000000U) +#define IOCTRL15_MASK (0x00000000U) +#define IOCTRL16_MASK (0x00000000U) +#define IOCTRL17_MASK (0x00000000U) +#define IOCTRL18_MASK (0x00000000U) +#define IOCTRL19_MASK (0x00000000U) + +#define IOCTRL0_DRV3_GETHER_DR2 ((uint32_t)1U << 30U) +#define IOCTRL0_DRV2_GETHER_DR2 ((uint32_t)1U << 29U) +#define IOCTRL0_DRV1_GETHER_DR2 ((uint32_t)1U << 28U) +#define IOCTRL0_DRV3_GETHER_DR3 ((uint32_t)1U << 26U) +#define IOCTRL0_DRV2_GETHER_DR3 ((uint32_t)1U << 25U) +#define IOCTRL0_DRV1_GETHER_DR3 ((uint32_t)1U << 24U) +#define IOCTRL0_DRV3_GETHER_DR4 ((uint32_t)1U << 22U) +#define IOCTRL0_DRV2_GETHER_DR4 ((uint32_t)1U << 21U) +#define IOCTRL0_DRV1_GETHER_DR4 ((uint32_t)1U << 20U) +#define IOCTRL0_DRV3_GETHER_DR5 ((uint32_t)1U << 18U) +#define IOCTRL0_DRV2_GETHER_DR5 ((uint32_t)1U << 17U) +#define IOCTRL0_DRV1_GETHER_DR5 ((uint32_t)1U << 16U) +#define IOCTRL0_DRV3_GETHER_DR6 ((uint32_t)1U << 14U) +#define IOCTRL0_DRV2_GETHER_DR6 ((uint32_t)1U << 13U) +#define IOCTRL0_DRV1_GETHER_DR6 ((uint32_t)1U << 12U) +#define IOCTRL0_DRV3_GETHER_DR7 ((uint32_t)1U << 10U) +#define IOCTRL0_DRV2_GETHER_DR7 ((uint32_t)1U << 9U) +#define IOCTRL0_DRV1_GETHER_DR7 ((uint32_t)1U << 8U) +#define IOCTRL0_DRV3_GETHER_DG2 ((uint32_t)1U << 6U) +#define IOCTRL0_DRV2_GETHER_DG2 ((uint32_t)1U << 5U) +#define IOCTRL0_DRV1_GETHER_DG2 ((uint32_t)1U << 4U) +#define IOCTRL0_DRV3_GETHER_DG3 ((uint32_t)1U << 2U) +#define IOCTRL0_DRV2_GETHER_DG3 ((uint32_t)1U << 1U) +#define IOCTRL0_DRV1_GETHER_DG3 ((uint32_t)1U << 0U) +#define IOCTRL1_DRV3_GETHER_DG4 ((uint32_t)1U << 30U) +#define IOCTRL1_DRV2_GETHER_DG4 ((uint32_t)1U << 29U) +#define IOCTRL1_DRV1_GETHER_DG4 ((uint32_t)1U << 28U) +#define IOCTRL1_DRV3_GETHER_DG5 ((uint32_t)1U << 26U) +#define IOCTRL1_DRV2_GETHER_DG5 ((uint32_t)1U << 25U) +#define IOCTRL1_DRV1_GETHER_DG5 ((uint32_t)1U << 24U) +#define IOCTRL1_DRV3_GETHER_DG6 ((uint32_t)1U << 22U) +#define IOCTRL1_DRV2_GETHER_DG6 ((uint32_t)1U << 21U) +#define IOCTRL1_DRV1_GETHER_DG6 ((uint32_t)1U << 20U) +#define IOCTRL1_DRV3_GETHER_DG7 ((uint32_t)1U << 18U) +#define IOCTRL1_DRV2_GETHER_DG7 ((uint32_t)1U << 17U) +#define IOCTRL1_DRV1_GETHER_DG7 ((uint32_t)1U << 16U) +#define IOCTRL1_DRV3_GETHER_DB2 ((uint32_t)1U << 14U) +#define IOCTRL1_DRV2_GETHER_DB2 ((uint32_t)1U << 13U) +#define IOCTRL1_DRV1_GETHER_DB2 ((uint32_t)1U << 12U) +#define IOCTRL1_DRV3_GETHER_DB3 ((uint32_t)1U << 10U) +#define IOCTRL1_DRV2_GETHER_DB3 ((uint32_t)1U << 9U) +#define IOCTRL1_DRV1_GETHER_DB3 ((uint32_t)1U << 8U) +#define IOCTRL1_DRV3_GETHER_DB4 ((uint32_t)1U << 6U) +#define IOCTRL1_DRV2_GETHER_DB4 ((uint32_t)1U << 5U) +#define IOCTRL1_DRV1_GETHER_DB4 ((uint32_t)1U << 4U) +#define IOCTRL1_DRV3_GETHER_DB5 ((uint32_t)1U << 2U) +#define IOCTRL1_DRV2_GETHER_DB5 ((uint32_t)1U << 1U) +#define IOCTRL1_DRV1_GETHER_DB5 ((uint32_t)1U << 0U) +#define IOCTRL2_DRV3_GETHER_DB6 ((uint32_t)1U << 30U) +#define IOCTRL2_DRV2_GETHER_DB6 ((uint32_t)1U << 29U) +#define IOCTRL2_DRV1_GETHER_DB6 ((uint32_t)1U << 28U) +#define IOCTRL2_DRV3_GETHER_DB7 ((uint32_t)1U << 26U) +#define IOCTRL2_DRV2_GETHER_DB7 ((uint32_t)1U << 25U) +#define IOCTRL2_DRV1_GETHER_DB7 ((uint32_t)1U << 24U) +#define IOCTRL2_DRV3_DU_DOTCLKOUT ((uint32_t)1U << 22U) +#define IOCTRL2_DRV2_DU_DOTCLKOUT ((uint32_t)1U << 21U) +#define IOCTRL2_DRV1_DU_DOTCLKOUT ((uint32_t)1U << 20U) +#define IOCTRL2_DRV3_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 18U) +#define IOCTRL2_DRV2_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 17U) +#define IOCTRL2_DRV1_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 16U) +#define IOCTRL2_DRV3_DU_EXHSYNC_DU_VSYNC ((uint32_t)1U << 14U) +#define IOCTRL2_DRV2_DU_EXHSYNC_DU_VSYNC ((uint32_t)1U << 13U) +#define IOCTRL2_DRV1_DU_EXHSYNC_DU_VSYNC ((uint32_t)1U << 12U) +#define IOCTRL2_DRV3_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 10U) +#define IOCTRL2_DRV2_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 9U) +#define IOCTRL2_DRV1_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 8U) +#define IOCTRL3_DRV2_DU_DOTCLKIN ((uint32_t)1U << 29U) +#define IOCTRL3_DRV1_DU_DOTCLKIN ((uint32_t)1U << 28U) +#define IOCTRL3_DRV3_PRESETOUT ((uint32_t)1U << 22U) +#define IOCTRL3_DRV2_PRESETOUT ((uint32_t)1U << 21U) +#define IOCTRL3_DRV1_PRESETOUT ((uint32_t)1U << 20U) +#define IOCTRL3_DRV2_FSCLKST ((uint32_t)1U << 1U) +#define IOCTRL3_DRV1_FSCLKST ((uint32_t)1U << 0U) +#define IOCTRL4_DRV2_FSCLKST2 ((uint32_t)1U << 29U) +#define IOCTRL4_DRV1_FSCLKST2 ((uint32_t)1U << 28U) +#define IOCTRL4_DRV3_IRQ0 ((uint32_t)1U << 22U) +#define IOCTRL4_DRV2_IRQ0 ((uint32_t)1U << 21U) +#define IOCTRL4_DRV1_IRQ0 ((uint32_t)1U << 20U) +#define IOCTRL4_DRV2_DCUTMS ((uint32_t)1U << 9U) +#define IOCTRL4_DRV1_DCUTMS ((uint32_t)1U << 8U) +#define IOCTRL4_DRV2_DCUTDO_LPDO ((uint32_t)1U << 1U) +#define IOCTRL4_DRV1_DCUTDO_LPDO ((uint32_t)1U << 0U) +#define IOCTRL5_DRV2_DCURDY_LPDCLKOUT ((uint32_t)1U << 29U) +#define IOCTRL5_DRV1_DCURDY_LPDCLKOUT ((uint32_t)1U << 28U) +#define IOCTRL5_DRV3_VI0_CLK ((uint32_t)1U << 26U) +#define IOCTRL5_DRV2_VI0_CLK ((uint32_t)1U << 25U) +#define IOCTRL5_DRV1_VI0_CLK ((uint32_t)1U << 24U) +#define IOCTRL5_DRV3_VI0_CLKENB ((uint32_t)1U << 22U) +#define IOCTRL5_DRV2_VI0_CLKENB ((uint32_t)1U << 21U) +#define IOCTRL5_DRV1_VI0_CLKENB ((uint32_t)1U << 20U) +#define IOCTRL5_DRV3_VI0_HSYNC ((uint32_t)1U << 18U) +#define IOCTRL5_DRV2_VI0_HSYNC ((uint32_t)1U << 17U) +#define IOCTRL5_DRV1_VI0_HSYNC ((uint32_t)1U << 16U) +#define IOCTRL5_DRV3_VI0_VSYNC ((uint32_t)1U << 14U) +#define IOCTRL5_DRV2_VI0_VSYNC ((uint32_t)1U << 13U) +#define IOCTRL5_DRV1_VI0_VSYNC ((uint32_t)1U << 12U) +#define IOCTRL5_DRV3_VI0_DATA0 ((uint32_t)1U << 10U) +#define IOCTRL5_DRV2_VI0_DATA0 ((uint32_t)1U << 9U) +#define IOCTRL5_DRV1_VI0_DATA0 ((uint32_t)1U << 8U) +#define IOCTRL5_DRV3_VI0_DATA1 ((uint32_t)1U << 6U) +#define IOCTRL5_DRV2_VI0_DATA1 ((uint32_t)1U << 5U) +#define IOCTRL5_DRV1_VI0_DATA1 ((uint32_t)1U << 4U) +#define IOCTRL5_DRV3_VI0_DATA2 ((uint32_t)1U << 2U) +#define IOCTRL5_DRV2_VI0_DATA2 ((uint32_t)1U << 1U) +#define IOCTRL5_DRV1_VI0_DATA2 ((uint32_t)1U << 0U) +#define IOCTRL6_DRV3_VI0_DATA3 ((uint32_t)1U << 30U) +#define IOCTRL6_DRV2_VI0_DATA3 ((uint32_t)1U << 29U) +#define IOCTRL6_DRV1_VI0_DATA3 ((uint32_t)1U << 28U) +#define IOCTRL6_DRV3_VI0_DATA4 ((uint32_t)1U << 26U) +#define IOCTRL6_DRV2_VI0_DATA4 ((uint32_t)1U << 25U) +#define IOCTRL6_DRV1_VI0_DATA4 ((uint32_t)1U << 24U) +#define IOCTRL6_DRV3_VI0_DATA5 ((uint32_t)1U << 22U) +#define IOCTRL6_DRV2_VI0_DATA5 ((uint32_t)1U << 21U) +#define IOCTRL6_DRV1_VI0_DATA5 ((uint32_t)1U << 20U) +#define IOCTRL6_DRV3_VI0_DATA6 ((uint32_t)1U << 18U) +#define IOCTRL6_DRV2_VI0_DATA6 ((uint32_t)1U << 17U) +#define IOCTRL6_DRV1_VI0_DATA6 ((uint32_t)1U << 16U) +#define IOCTRL6_DRV3_VI0_DATA7 ((uint32_t)1U << 14U) +#define IOCTRL6_DRV2_VI0_DATA7 ((uint32_t)1U << 13U) +#define IOCTRL6_DRV1_VI0_DATA7 ((uint32_t)1U << 12U) +#define IOCTRL6_DRV3_VI0_DATA8 ((uint32_t)1U << 10U) +#define IOCTRL6_DRV2_VI0_DATA8 ((uint32_t)1U << 9U) +#define IOCTRL6_DRV1_VI0_DATA8 ((uint32_t)1U << 8U) +#define IOCTRL6_DRV3_VI0_DATA9 ((uint32_t)1U << 6U) +#define IOCTRL6_DRV2_VI0_DATA9 ((uint32_t)1U << 5U) +#define IOCTRL6_DRV1_VI0_DATA9 ((uint32_t)1U << 4U) +#define IOCTRL6_DRV3_VI0_DATA10 ((uint32_t)1U << 2U) +#define IOCTRL6_DRV2_VI0_DATA10 ((uint32_t)1U << 1U) +#define IOCTRL6_DRV1_VI0_DATA10 ((uint32_t)1U << 0U) +#define IOCTRL7_DRV3_VI0_DATA11 ((uint32_t)1U << 30U) +#define IOCTRL7_DRV2_VI0_DATA11 ((uint32_t)1U << 29U) +#define IOCTRL7_DRV1_VI0_DATA11 ((uint32_t)1U << 28U) +#define IOCTRL7_DRV3_VI0_FIELD ((uint32_t)1U << 26U) +#define IOCTRL7_DRV2_VI0_FIELD ((uint32_t)1U << 25U) +#define IOCTRL7_DRV1_VI0_FIELD ((uint32_t)1U << 24U) +#define IOCTRL7_DRV3_VI1_CLK ((uint32_t)1U << 22U) +#define IOCTRL7_DRV2_VI1_CLK ((uint32_t)1U << 21U) +#define IOCTRL7_DRV1_VI1_CLK ((uint32_t)1U << 20U) +#define IOCTRL7_DRV3_VI1_CLKENB ((uint32_t)1U << 18U) +#define IOCTRL7_DRV2_VI1_CLKENB ((uint32_t)1U << 17U) +#define IOCTRL7_DRV1_VI1_CLKENB ((uint32_t)1U << 16U) +#define IOCTRL7_DRV3_VI1_HSYNC ((uint32_t)1U << 14U) +#define IOCTRL7_DRV2_VI1_HSYNC ((uint32_t)1U << 13U) +#define IOCTRL7_DRV1_VI1_HSYNC ((uint32_t)1U << 12U) +#define IOCTRL7_DRV3_VI1_VSYNC ((uint32_t)1U << 10U) +#define IOCTRL7_DRV2_VI1_VSYNC ((uint32_t)1U << 9U) +#define IOCTRL7_DRV1_VI1_VSYNC ((uint32_t)1U << 8U) +#define IOCTRL7_DRV3_VI1_DATA0 ((uint32_t)1U << 6U) +#define IOCTRL7_DRV2_VI1_DATA0 ((uint32_t)1U << 5U) +#define IOCTRL7_DRV1_VI1_DATA0 ((uint32_t)1U << 4U) +#define IOCTRL7_DRV3_VI1_DATA1 ((uint32_t)1U << 2U) +#define IOCTRL7_DRV2_VI1_DATA1 ((uint32_t)1U << 1U) +#define IOCTRL7_DRV1_VI1_DATA1 ((uint32_t)1U << 0U) +#define IOCTRL8_DRV3_VI1_DATA2 ((uint32_t)1U << 30U) +#define IOCTRL8_DRV2_VI1_DATA2 ((uint32_t)1U << 29U) +#define IOCTRL8_DRV1_VI1_DATA2 ((uint32_t)1U << 28U) +#define IOCTRL8_DRV3_VI1_DATA3 ((uint32_t)1U << 26U) +#define IOCTRL8_DRV2_VI1_DATA3 ((uint32_t)1U << 25U) +#define IOCTRL8_DRV1_VI1_DATA3 ((uint32_t)1U << 24U) +#define IOCTRL8_DRV3_VI1_DATA4 ((uint32_t)1U << 22U) +#define IOCTRL8_DRV2_VI1_DATA4 ((uint32_t)1U << 21U) +#define IOCTRL8_DRV1_VI1_DATA4 ((uint32_t)1U << 20U) +#define IOCTRL8_DRV3_VI1_DATA5 ((uint32_t)1U << 18U) +#define IOCTRL8_DRV2_VI1_DATA5 ((uint32_t)1U << 17U) +#define IOCTRL8_DRV1_VI1_DATA5 ((uint32_t)1U << 16U) +#define IOCTRL8_DRV3_VI1_DATA6 ((uint32_t)1U << 14U) +#define IOCTRL8_DRV2_VI1_DATA6 ((uint32_t)1U << 13U) +#define IOCTRL8_DRV1_VI1_DATA6 ((uint32_t)1U << 12U) +#define IOCTRL8_DRV3_VI1_DATA7 ((uint32_t)1U << 10U) +#define IOCTRL8_DRV2_VI1_DATA7 ((uint32_t)1U << 9U) +#define IOCTRL8_DRV1_VI1_DATA7 ((uint32_t)1U << 8U) +#define IOCTRL8_DRV3_VI1_DATA8 ((uint32_t)1U << 6U) +#define IOCTRL8_DRV2_VI1_DATA8 ((uint32_t)1U << 5U) +#define IOCTRL8_DRV1_VI1_DATA8 ((uint32_t)1U << 4U) +#define IOCTRL8_DRV3_VI1_DATA9 ((uint32_t)1U << 2U) +#define IOCTRL8_DRV2_VI1_DATA9 ((uint32_t)1U << 1U) +#define IOCTRL8_DRV1_VI1_DATA9 ((uint32_t)1U << 0U) +#define IOCTRL9_DRV3_VI1_DATA10 ((uint32_t)1U << 30U) +#define IOCTRL9_DRV2_VI1_DATA10 ((uint32_t)1U << 29U) +#define IOCTRL9_DRV1_VI1_DATA10 ((uint32_t)1U << 28U) +#define IOCTRL9_DRV3_VI1_DATA11 ((uint32_t)1U << 26U) +#define IOCTRL9_DRV2_VI1_DATA11 ((uint32_t)1U << 25U) +#define IOCTRL9_DRV1_VI1_DATA11 ((uint32_t)1U << 24U) +#define IOCTRL9_DRV3_VI1_FIELD ((uint32_t)1U << 22U) +#define IOCTRL9_DRV2_VI1_FIELD ((uint32_t)1U << 21U) +#define IOCTRL9_DRV1_VI1_FIELD ((uint32_t)1U << 20U) +#define IOCTRL9_DRV3_VI1_SCL0 ((uint32_t)1U << 18U) +#define IOCTRL9_DRV2_VI1_SCL0 ((uint32_t)1U << 17U) +#define IOCTRL9_DRV1_VI1_SCL0 ((uint32_t)1U << 16U) +#define IOCTRL9_DRV3_VI1_SDA0 ((uint32_t)1U << 14U) +#define IOCTRL9_DRV2_VI1_SDA0 ((uint32_t)1U << 13U) +#define IOCTRL9_DRV1_VI1_SDA0 ((uint32_t)1U << 12U) +#define IOCTRL9_DRV3_VI1_SCL1 ((uint32_t)1U << 10U) +#define IOCTRL9_DRV2_VI1_SCL1 ((uint32_t)1U << 9U) +#define IOCTRL9_DRV1_VI1_SCL1 ((uint32_t)1U << 8U) +#define IOCTRL9_DRV3_VI1_SDA1 ((uint32_t)1U << 6U) +#define IOCTRL9_DRV2_VI1_SDA1 ((uint32_t)1U << 5U) +#define IOCTRL9_DRV1_VI1_SDA1 ((uint32_t)1U << 4U) +#define IOCTRL9_DRV3_VI1_SCL2 ((uint32_t)1U << 2U) +#define IOCTRL9_DRV2_VI1_SCL2 ((uint32_t)1U << 1U) +#define IOCTRL9_DRV1_VI1_SCL2 ((uint32_t)1U << 0U) +#define IOCTRL10_DRV3_VI1_SDA2 ((uint32_t)1U << 30U) +#define IOCTRL10_DRV2_VI1_SDA2 ((uint32_t)1U << 29U) +#define IOCTRL10_DRV1_VI1_SDA2 ((uint32_t)1U << 28U) +#define IOCTRL10_DRV3_AVB_RX_CTL ((uint32_t)1U << 26U) +#define IOCTRL10_DRV2_AVB_RX_CTL ((uint32_t)1U << 25U) +#define IOCTRL10_DRV1_AVB_RX_CTL ((uint32_t)1U << 24U) +#define IOCTRL10_DRV3_AVB_RX_RXC ((uint32_t)1U << 22U) +#define IOCTRL10_DRV2_AVB_RX_RXC ((uint32_t)1U << 21U) +#define IOCTRL10_DRV1_AVB_RX_RXC ((uint32_t)1U << 20U) +#define IOCTRL10_DRV3_AVB_RX_RD0 ((uint32_t)1U << 18U) +#define IOCTRL10_DRV2_AVB_RX_RD0 ((uint32_t)1U << 17U) +#define IOCTRL10_DRV1_AVB_RX_RD0 ((uint32_t)1U << 16U) +#define IOCTRL10_DRV3_AVB_RX_RD1 ((uint32_t)1U << 14U) +#define IOCTRL10_DRV2_AVB_RX_RD1 ((uint32_t)1U << 13U) +#define IOCTRL10_DRV1_AVB_RX_RD1 ((uint32_t)1U << 12U) +#define IOCTRL10_DRV3_AVB_RX_RD2 ((uint32_t)1U << 10U) +#define IOCTRL10_DRV2_AVB_RX_RD2 ((uint32_t)1U << 9U) +#define IOCTRL10_DRV1_AVB_RX_RD2 ((uint32_t)1U << 8U) +#define IOCTRL10_DRV3_AVB_RX_RD3 ((uint32_t)1U << 6U) +#define IOCTRL10_DRV2_AVB_RX_RD3 ((uint32_t)1U << 5U) +#define IOCTRL10_DRV1_AVB_RX_RD3 ((uint32_t)1U << 4U) +#define IOCTRL10_DRV3_AVB_TX_CTL ((uint32_t)1U << 2U) +#define IOCTRL10_DRV2_AVB_TX_CTL ((uint32_t)1U << 1U) +#define IOCTRL10_DRV1_AVB_TX_CTL ((uint32_t)1U << 0U) +#define IOCTRL11_DRV3_AVB_TXC ((uint32_t)1U << 30U) +#define IOCTRL11_DRV2_AVB_TXC ((uint32_t)1U << 29U) +#define IOCTRL11_DRV1_AVB_TXC ((uint32_t)1U << 28U) +#define IOCTRL11_DRV3_AVB_TD0 ((uint32_t)1U << 26U) +#define IOCTRL11_DRV2_AVB_TD0 ((uint32_t)1U << 25U) +#define IOCTRL11_DRV1_AVB_TD0 ((uint32_t)1U << 24U) +#define IOCTRL11_DRV3_AVB_TD1 ((uint32_t)1U << 22U) +#define IOCTRL11_DRV2_AVB_TD1 ((uint32_t)1U << 21U) +#define IOCTRL11_DRV1_AVB_TD1 ((uint32_t)1U << 20U) +#define IOCTRL11_DRV3_AVB_TD2 ((uint32_t)1U << 18U) +#define IOCTRL11_DRV2_AVB_TD2 ((uint32_t)1U << 17U) +#define IOCTRL11_DRV1_AVB_TD2 ((uint32_t)1U << 16U) +#define IOCTRL11_DRV3_AVB_TD3 ((uint32_t)1U << 14U) +#define IOCTRL11_DRV2_AVB_TD3 ((uint32_t)1U << 13U) +#define IOCTRL11_DRV1_AVB_TD3 ((uint32_t)1U << 12U) +#define IOCTRL11_DRV3_AVB_TXCREFCLK ((uint32_t)1U << 10U) +#define IOCTRL11_DRV2_AVB_TXCREFCLK ((uint32_t)1U << 9U) +#define IOCTRL11_DRV1_AVB_TXCREFCLK ((uint32_t)1U << 8U) +#define IOCTRL11_DRV3_AVB_MDIO ((uint32_t)1U << 6U) +#define IOCTRL11_DRV2_AVB_MDIO ((uint32_t)1U << 5U) +#define IOCTRL11_DRV1_AVB_MDIO ((uint32_t)1U << 4U) +#define IOCTRL11_DRV3_AVB_MDC ((uint32_t)1U << 2U) +#define IOCTRL11_DRV2_AVB_MDC ((uint32_t)1U << 1U) +#define IOCTRL11_DRV1_AVB_MDC ((uint32_t)1U << 0U) +#define IOCTRL12_DRV3_AVB_MAGIC ((uint32_t)1U << 30U) +#define IOCTRL12_DRV2_AVB_MAGIC ((uint32_t)1U << 29U) +#define IOCTRL12_DRV1_AVB_MAGIC ((uint32_t)1U << 28U) +#define IOCTRL12_DRV3_AVB_PHY_INT ((uint32_t)1U << 26U) +#define IOCTRL12_DRV2_AVB_PHY_INT ((uint32_t)1U << 25U) +#define IOCTRL12_DRV1_AVB_PHY_INT ((uint32_t)1U << 24U) +#define IOCTRL12_DRV3_AVB_LINK ((uint32_t)1U << 22U) +#define IOCTRL12_DRV2_AVB_LINK ((uint32_t)1U << 21U) +#define IOCTRL12_DRV1_AVB_LINK ((uint32_t)1U << 20U) +#define IOCTRL12_DRV3_AVB_AVTP_MATCH ((uint32_t)1U << 18U) +#define IOCTRL12_DRV2_AVB_AVTP_MATCH ((uint32_t)1U << 17U) +#define IOCTRL12_DRV1_AVB_AVTP_MATCH ((uint32_t)1U << 16U) +#define IOCTRL12_DRV3_AVB_AVTP_CAPTURE ((uint32_t)1U << 14U) +#define IOCTRL12_DRV2_AVB_AVTP_CAPTURE ((uint32_t)1U << 13U) +#define IOCTRL12_DRV1_AVB_AVTP_CAPTURE ((uint32_t)1U << 12U) +#define IOCTRL12_DRV3_GETHER_RX_CTL ((uint32_t)1U << 10U) +#define IOCTRL12_DRV2_GETHER_RX_CTL ((uint32_t)1U << 9U) +#define IOCTRL12_DRV1_GETHER_RX_CTL ((uint32_t)1U << 8U) +#define IOCTRL12_DRV3_GETHER_RXC ((uint32_t)1U << 6U) +#define IOCTRL12_DRV2_GETHER_RXC ((uint32_t)1U << 5U) +#define IOCTRL12_DRV1_GETHER_RXC ((uint32_t)1U << 4U) +#define IOCTRL12_DRV3_GETHER_RD0 ((uint32_t)1U << 2U) +#define IOCTRL12_DRV2_GETHER_RD0 ((uint32_t)1U << 1U) +#define IOCTRL12_DRV1_GETHER_RD0 ((uint32_t)1U << 0U) +#define IOCTRL13_DRV3_GETHER_RD1 ((uint32_t)1U << 30U) +#define IOCTRL13_DRV2_GETHER_RD1 ((uint32_t)1U << 29U) +#define IOCTRL13_DRV1_GETHER_RD1 ((uint32_t)1U << 28U) +#define IOCTRL13_DRV3_GETHER_RD2 ((uint32_t)1U << 26U) +#define IOCTRL13_DRV2_GETHER_RD2 ((uint32_t)1U << 25U) +#define IOCTRL13_DRV1_GETHER_RD2 ((uint32_t)1U << 24U) +#define IOCTRL13_DRV3_GETHER_RD3 ((uint32_t)1U << 22U) +#define IOCTRL13_DRV2_GETHER_RD3 ((uint32_t)1U << 21U) +#define IOCTRL13_DRV1_GETHER_RD3 ((uint32_t)1U << 20U) +#define IOCTRL13_DRV3_GETHER_TX_CTL ((uint32_t)1U << 18U) +#define IOCTRL13_DRV2_GETHER_TX_CTL ((uint32_t)1U << 17U) +#define IOCTRL13_DRV1_GETHER_TX_CTL ((uint32_t)1U << 16U) +#define IOCTRL13_DRV3_GETHER_TXC ((uint32_t)1U << 14U) +#define IOCTRL13_DRV2_GETHER_TXC ((uint32_t)1U << 13U) +#define IOCTRL13_DRV1_GETHER_TXC ((uint32_t)1U << 12U) +#define IOCTRL13_DRV3_GETHER_TD0 ((uint32_t)1U << 10U) +#define IOCTRL13_DRV2_GETHER_TD0 ((uint32_t)1U << 9U) +#define IOCTRL13_DRV1_GETHER_TD0 ((uint32_t)1U << 8U) +#define IOCTRL13_DRV3_GETHER_TD1 ((uint32_t)1U << 6U) +#define IOCTRL13_DRV2_GETHER_TD1 ((uint32_t)1U << 5U) +#define IOCTRL13_DRV1_GETHER_TD1 ((uint32_t)1U << 4U) +#define IOCTRL13_DRV3_GETHER_TD2 ((uint32_t)1U << 2U) +#define IOCTRL13_DRV2_GETHER_TD2 ((uint32_t)1U << 1U) +#define IOCTRL13_DRV1_GETHER_TD2 ((uint32_t)1U << 0U) +#define IOCTRL13_DRV3_GETHER_TD3 ((uint32_t)1U << 30U) +#define IOCTRL13_DRV2_GETHER_TD3 ((uint32_t)1U << 29U) +#define IOCTRL13_DRV1_GETHER_TD3 ((uint32_t)1U << 28U) +#define IOCTRL14_DRV3_GETHER_TXCREFCLK ((uint32_t)1U << 26U) +#define IOCTRL14_DRV2_GETHER_TXCREFCLK ((uint32_t)1U << 25U) +#define IOCTRL14_DRV1_GETHER_TXCREFCLK ((uint32_t)1U << 24U) +#define IOCTRL14_DRV3_GETHER_TXCREFCLK_MEGA ((uint32_t)1U << 22U) +#define IOCTRL14_DRV2_GETHER_TXCREFCLK_MEGA ((uint32_t)1U << 21U) +#define IOCTRL14_DRV1_GETHER_TXCREFCLK_MEGA ((uint32_t)1U << 20U) +#define IOCTRL14_DRV3_GETHER_MDIO ((uint32_t)1U << 18U) +#define IOCTRL14_DRV2_GETHER_MDIO ((uint32_t)1U << 17U) +#define IOCTRL14_DRV1_GETHER_MDIO ((uint32_t)1U << 16U) +#define IOCTRL14_DRV3_GETHER_MDC ((uint32_t)1U << 14U) +#define IOCTRL14_DRV2_GETHER_MDC ((uint32_t)1U << 13U) +#define IOCTRL14_DRV1_GETHER_MDC ((uint32_t)1U << 12U) +#define IOCTRL14_DRV3_GETHER_MAGIC ((uint32_t)1U << 10U) +#define IOCTRL14_DRV2_GETHER_MAGIC ((uint32_t)1U << 9U) +#define IOCTRL14_DRV1_GETHER_MAGIC ((uint32_t)1U << 8U) +#define IOCTRL14_DRV3_GETHER_PHY_INT ((uint32_t)1U << 6U) +#define IOCTRL14_DRV2_GETHER_PHY_INT ((uint32_t)1U << 5U) +#define IOCTRL14_DRV1_GETHER_PHY_INT ((uint32_t)1U << 4U) +#define IOCTRL14_DRV3_GETHER_LINK ((uint32_t)1U << 2U) +#define IOCTRL14_DRV2_GETHER_LINK ((uint32_t)1U << 1U) +#define IOCTRL14_DRV1_GETHER_LINK ((uint32_t)1U << 0U) +#define IOCTRL15_DRV3_CANFD0_TX ((uint32_t)1U << 30U) +#define IOCTRL15_DRV2_CANFD0_TX ((uint32_t)1U << 29U) +#define IOCTRL15_DRV1_CANFD0_TX ((uint32_t)1U << 28U) +#define IOCTRL15_DRV3_CANFD0_RX ((uint32_t)1U << 26U) +#define IOCTRL15_DRV2_CANFD0_RX ((uint32_t)1U << 25U) +#define IOCTRL15_DRV1_CANFD0_RX ((uint32_t)1U << 24U) +#define IOCTRL15_DRV3_CANFD1_TX ((uint32_t)1U << 22U) +#define IOCTRL15_DRV2_CANFD1_TX ((uint32_t)1U << 21U) +#define IOCTRL15_DRV1_CANFD1_TX ((uint32_t)1U << 20U) +#define IOCTRL15_DRV3_CANFD1_RX ((uint32_t)1U << 18U) +#define IOCTRL15_DRV2_CANFD1_RX ((uint32_t)1U << 17U) +#define IOCTRL15_DRV1_CANFD1_RX ((uint32_t)1U << 16U) +#define IOCTRL15_DRV3_CAN_CLK ((uint32_t)1U << 14U) +#define IOCTRL15_DRV2_CAN_CLK ((uint32_t)1U << 13U) +#define IOCTRL15_DRV1_CAN_CLK ((uint32_t)1U << 12U) +#define IOCTRL15_DRV2_QSPI0_SPCLK ((uint32_t)1U << 9U) +#define IOCTRL15_DRV1_QSPI0_SPCLK ((uint32_t)1U << 8U) +#define IOCTRL15_DRV2_QSPI0_MOSI_IO0 ((uint32_t)1U << 5U) +#define IOCTRL15_DRV1_QSPI0_MOSI_IO0 ((uint32_t)1U << 4U) +#define IOCTRL15_DRV2_QSPI0_MOSI_IO1 ((uint32_t)1U << 1U) +#define IOCTRL15_DRV1_QSPI0_MOSI_IO1 ((uint32_t)1U << 0U) +#define IOCTRL16_DRV2_QSPI0_MOSI_IO2 ((uint32_t)1U << 29U) +#define IOCTRL16_DRV1_QSPI0_MOSI_IO2 ((uint32_t)1U << 28U) +#define IOCTRL16_DRV2_QSPI0_MOSI_IO3 ((uint32_t)1U << 25U) +#define IOCTRL16_DRV1_QSPI0_MOSI_IO3 ((uint32_t)1U << 24U) +#define IOCTRL16_DRV2_QSPI0_SSL ((uint32_t)1U << 21U) +#define IOCTRL16_DRV1_QSPI0_SSL ((uint32_t)1U << 20U) +#define IOCTRL16_DRV2_QSPI1_SPCLK ((uint32_t)1U << 17U) +#define IOCTRL16_DRV1_QSPI1_SPCLK ((uint32_t)1U << 16U) +#define IOCTRL16_DRV2_QSPI1_MOSI_IO0 ((uint32_t)1U << 13U) +#define IOCTRL16_DRV1_QSPI1_MOSI_IO0 ((uint32_t)1U << 12U) +#define IOCTRL16_DRV2_QSPI1_MOSI_IO1 ((uint32_t)1U << 9U) +#define IOCTRL16_DRV1_QSPI1_MOSI_IO1 ((uint32_t)1U << 8U) +#define IOCTRL16_DRV2_QSPI1_IO2 ((uint32_t)1U << 5U) +#define IOCTRL16_DRV1_QSPI1_IO2 ((uint32_t)1U << 4U) +#define IOCTRL16_DRV2_QSPI1_IO3 ((uint32_t)1U << 1U) +#define IOCTRL16_DRV1_QSPI1_IO3 ((uint32_t)1U << 0U) +#define IOCTRL17_DRV2_QSPI1_SSL ((uint32_t)1U << 29U) +#define IOCTRL17_DRV1_QSPI1_SSL ((uint32_t)1U << 28U) +#define IOCTRL17_DRV2_QSPI1_RPC_RESET ((uint32_t)1U << 25U) +#define IOCTRL17_DRV1_QSPI1_RPC_RESET ((uint32_t)1U << 24U) +#define IOCTRL17_DRV2_RPC_WP ((uint32_t)1U << 21U) +#define IOCTRL17_DRV1_RPC_WP ((uint32_t)1U << 20U) +#define IOCTRL17_DRV2_RPC_INT ((uint32_t)1U << 17U) +#define IOCTRL17_DRV1_RPC_INT ((uint32_t)1U << 16U) +#define IOCTRL17_DRV2_DIGRF_CLKIN ((uint32_t)1U << 13U) +#define IOCTRL17_DRV1_DIGRF_CLKIN ((uint32_t)1U << 12U) +#define IOCTRL17_DRV2_DIGRF_CLKOUT ((uint32_t)1U << 9U) +#define IOCTRL17_DRV1_DIGRF_CLKOUT ((uint32_t)1U << 8U) +#define IOCTRL17_DRV2_RPC_IRQ4 ((uint32_t)1U << 5U) +#define IOCTRL17_DRV1_RPC_IRQ4 ((uint32_t)1U << 4U) +#define IOCTRL17_DRV2_RPC_IRQ5 ((uint32_t)1U << 1U) +#define IOCTRL17_DRV1_RPC_IRQ5 ((uint32_t)1U << 0U) +#define IOCTRL18_DRV3_SCL3 ((uint32_t)1U << 30U) +#define IOCTRL18_DRV2_SCL3 ((uint32_t)1U << 29U) +#define IOCTRL18_DRV1_SCL3 ((uint32_t)1U << 28U) +#define IOCTRL18_DRV3_SDA3 ((uint32_t)1U << 26U) +#define IOCTRL18_DRV2_SDA3 ((uint32_t)1U << 25U) +#define IOCTRL18_DRV1_SDA3 ((uint32_t)1U << 24U) +#define IOCTRL18_DRV3_MSIOF0_RXD ((uint32_t)1U << 22U) +#define IOCTRL18_DRV2_MSIOF0_RXD ((uint32_t)1U << 21U) +#define IOCTRL18_DRV1_MSIOF0_RXD ((uint32_t)1U << 20U) +#define IOCTRL18_DRV3_MSIOF0_TXD ((uint32_t)1U << 18U) +#define IOCTRL18_DRV2_MSIOF0_TXD ((uint32_t)1U << 17U) +#define IOCTRL18_DRV1_MSIOF0_TXD ((uint32_t)1U << 16U) +#define IOCTRL18_DRV3_MSIOF0_SCK ((uint32_t)1U << 14U) +#define IOCTRL18_DRV2_MSIOF0_SCK ((uint32_t)1U << 13U) +#define IOCTRL18_DRV1_MSIOF0_SCK ((uint32_t)1U << 12U) +#define IOCTRL18_DRV3_MSIOF0_SYNC ((uint32_t)1U << 10U) +#define IOCTRL18_DRV2_MSIOF0_SYNC ((uint32_t)1U << 9U) +#define IOCTRL18_DRV1_MSIOF0_SYNC ((uint32_t)1U << 8U) +#define IOCTRL18_DRV3_MSIOF0_SS1 ((uint32_t)1U << 6U) +#define IOCTRL18_DRV2_MSIOF0_SS1 ((uint32_t)1U << 5U) +#define IOCTRL18_DRV1_MSIOF0_SS1 ((uint32_t)1U << 4U) +#define IOCTRL18_DRV3_MSIOF0_SS2 ((uint32_t)1U << 2U) +#define IOCTRL18_DRV2_MSIOF0_SS2 ((uint32_t)1U << 1U) +#define IOCTRL18_DRV1_MSIOF0_SS2 ((uint32_t)1U << 0U) +#define IOCTRL19_DRV3_FSO_CFE_0 ((uint32_t)1U << 30U) +#define IOCTRL19_DRV2_FSO_CFE_0 ((uint32_t)1U << 29U) +#define IOCTRL19_DRV1_FSO_CFE_0 ((uint32_t)1U << 28U) +#define IOCTRL19_DRV3_FSO_CFE_1 ((uint32_t)1U << 26U) +#define IOCTRL19_DRV2_FSO_CFE_1 ((uint32_t)1U << 25U) +#define IOCTRL19_DRV1_FSO_CFE_1 ((uint32_t)1U << 24U) +#define IOCTRL19_DRV3_FSO_TOE ((uint32_t)1U << 22U) +#define IOCTRL19_DRV2_FSO_TOE ((uint32_t)1U << 21U) +#define IOCTRL19_DRV1_FSO_TOE ((uint32_t)1U << 20U) + +#define IOCTRL30_POC_VI0_DATA5 ((uint32_t)1U << 31U) +#define IOCTRL30_POC_VI0_DATA4 ((uint32_t)1U << 30U) +#define IOCTRL30_POC_VI0_DATA3 ((uint32_t)1U << 29U) +#define IOCTRL30_POC_VI0_DATA2 ((uint32_t)1U << 28U) +#define IOCTRL30_POC_VI0_DATA1 ((uint32_t)1U << 27U) +#define IOCTRL30_POC_VI0_DATA0 ((uint32_t)1U << 26U) +#define IOCTRL30_POC_VI0_VSYNC_N ((uint32_t)1U << 25U) +#define IOCTRL30_POC_VI0_HSYNC_N ((uint32_t)1U << 24U) +#define IOCTRL30_POC_VI0_CLKENB ((uint32_t)1U << 23U) +#define IOCTRL30_POC_VI0_CLK ((uint32_t)1U << 22U) +#define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) +#define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) +#define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) +#define IOCTRL30_POC_DU_DOTCLKOUT ((uint32_t)1U << 18U) +#define IOCTRL30_POC_DU_DB7 ((uint32_t)1U << 17U) +#define IOCTRL30_POC_DU_DB6 ((uint32_t)1U << 16U) +#define IOCTRL30_POC_DU_DB5 ((uint32_t)1U << 15U) +#define IOCTRL30_POC_DU_DB4 ((uint32_t)1U << 14U) +#define IOCTRL30_POC_DU_DB3 ((uint32_t)1U << 13U) +#define IOCTRL30_POC_DU_DB2 ((uint32_t)1U << 12U) +#define IOCTRL30_POC_DU_DG7 ((uint32_t)1U << 11U) +#define IOCTRL30_POC_DU_DG6 ((uint32_t)1U << 10U) +#define IOCTRL30_POC_DU_DG5 ((uint32_t)1U << 9U) +#define IOCTRL30_POC_DU_DG4 ((uint32_t)1U << 8U) +#define IOCTRL30_POC_DU_DG3 ((uint32_t)1U << 7U) +#define IOCTRL30_POC_DU_DG2 ((uint32_t)1U << 6U) +#define IOCTRL30_POC_DU_DR7 ((uint32_t)1U << 5U) +#define IOCTRL30_POC_DU_DR6 ((uint32_t)1U << 4U) +#define IOCTRL30_POC_DU_DR5 ((uint32_t)1U << 3U) +#define IOCTRL30_POC_DU_DR4 ((uint32_t)1U << 2U) +#define IOCTRL30_POC_DU_DR3 ((uint32_t)1U << 1U) +#define IOCTRL30_POC_DU_DR2 ((uint32_t)1U << 0U) + +#define IOCTRL31_POC_MSIOF0_SS2 ((uint32_t)1U << 31U) +#define IOCTRL31_POC_MSIOF0_SS1 ((uint32_t)1U << 30U) +#define IOCTRL31_POC_MSIOF0_SYNC ((uint32_t)1U << 29U) +#define IOCTRL31_POC_MSIOF0_SCK ((uint32_t)1U << 28U) +#define IOCTRL31_POC_MSIOF0_TXD ((uint32_t)1U << 27U) +#define IOCTRL31_POC_MSIOF0_RXD ((uint32_t)1U << 26U) +#define IOCTRL31_POC_MSIOF0_IRQ5 ((uint32_t)1U << 25U) +#define IOCTRL31_POC_MSIOF0_IRQ4 ((uint32_t)1U << 24U) +#define IOCTRL31_POC_VI1_FIELD ((uint32_t)1U << 23U) +#define IOCTRL31_POC_VI1_DATA11 ((uint32_t)1U << 22U) +#define IOCTRL31_POC_VI1_DATA10 ((uint32_t)1U << 21U) +#define IOCTRL31_POC_VI1_DATA9 ((uint32_t)1U << 20U) +#define IOCTRL31_POC_VI1_DATA8 ((uint32_t)1U << 19U) +#define IOCTRL31_POC_VI1_DATA7 ((uint32_t)1U << 18U) +#define IOCTRL31_POC_VI1_DATA6 ((uint32_t)1U << 17U) +#define IOCTRL31_POC_VI1_DATA5 ((uint32_t)1U << 16U) +#define IOCTRL31_POC_VI1_DATA4 ((uint32_t)1U << 15U) +#define IOCTRL31_POC_VI1_DATA3 ((uint32_t)1U << 14U) +#define IOCTRL31_POC_VI1_DATA2 ((uint32_t)1U << 13U) +#define IOCTRL31_POC_VI1_DATA1 ((uint32_t)1U << 12U) +#define IOCTRL31_POC_VI1_DATA0 ((uint32_t)1U << 11U) +#define IOCTRL31_POC_VI1_VSYNC ((uint32_t)1U << 10U) +#define IOCTRL31_POC_VI1_HSYNC ((uint32_t)1U << 9U) +#define IOCTRL31_POC_VI1_CLKENB ((uint32_t)1U << 8U) +#define IOCTRL31_POC_VI1_CLK ((uint32_t)1U << 7U) +#define IOCTRL31_POC_VI0_FIELD ((uint32_t)1U << 6U) +#define IOCTRL31_POC_VI0_DATA11 ((uint32_t)1U << 5U) +#define IOCTRL31_POC_VI0_DATA10 ((uint32_t)1U << 4U) +#define IOCTRL31_POC_VI0_DATA9 ((uint32_t)1U << 3U) +#define IOCTRL31_POC_VI0_DATA8 ((uint32_t)1U << 2U) +#define IOCTRL31_POC_VI0_DATA7 ((uint32_t)1U << 1U) +#define IOCTRL31_POC_VI0_DATA6 ((uint32_t)1U << 0U) +#define IOCTRL32_POC_FSO_TOE ((uint32_t)1U << 4U) +#define IOCTRL32_POC_FSO_CFE_1 ((uint32_t)1U << 3U) +#define IOCTRL32_POC_FSO_CFE_0 ((uint32_t)1U << 2U) +#define IOCTRL32_POC_SDA3 ((uint32_t)1U << 1U) +#define IOCTRL32_POC_SCL3 ((uint32_t)1U << 0U) +#define IOCTRL40_SD0TDSEL1 ((uint32_t)1U << 1U) +#define IOCTRL40_SD0TDSEL0 ((uint32_t)1U << 0U) + +#define MOD_sel_canfd0_A ((uint32_t)0U << 11U) +#define MOD_sel_canfd0_B ((uint32_t)1U << 11U) +#define MOD_sel_gether_A ((uint32_t)0U << 10U) +#define MOD_sel_gether_B ((uint32_t)1U << 10U) +#define MOD_sel_hscif0_A ((uint32_t)0U << 9U) +#define MOD_sel_hscif0_B ((uint32_t)1U << 9U) +#define MOD_sel_pwm0_A ((uint32_t)0U << 8U) +#define MOD_sel_pwm0_B ((uint32_t)1U << 8U) +#define MOD_sel_pwm1_A ((uint32_t)0U << 7U) +#define MOD_sel_pwm1_B ((uint32_t)1U << 7U) +#define MOD_sel_pwm2_A ((uint32_t)0U << 6U) +#define MOD_sel_pwm2_B ((uint32_t)1U << 6U) +#define MOD_sel_pwm3_A ((uint32_t)0U << 5U) +#define MOD_sel_pwm3_B ((uint32_t)1U << 5U) +#define MOD_sel_pwm4_A ((uint32_t)0U << 4U) +#define MOD_sel_pwm4_B ((uint32_t)1U << 4U) +#define MOD_sel_rsp_A ((uint32_t)0U << 2U) +#define MOD_sel_rsp_B ((uint32_t)1U << 2U) +#define MOD_sel_scif1_A ((uint32_t)0U << 1U) +#define MOD_sel_scif1_B ((uint32_t)1U << 1U) +#define MOD_sel_tmu_A ((uint32_t)0U << 0U) +#define MOD_sel_tmu_B ((uint32_t)1U << 0U) + + + +void pfc_init(void) +{ + /* Initialize module select */ + pfc_reg_write(PFC_MOD_SEL0, MOD_sel_canfd0_A + | MOD_sel_gether_A + | MOD_sel_hscif0_B + | MOD_sel_pwm0_A + | MOD_sel_pwm1_A + | MOD_sel_pwm2_A + | MOD_sel_pwm3_A + | MOD_sel_pwm4_A + | MOD_sel_rsp_A + | MOD_sel_scif1_A + | MOD_sel_tmu_A); + + /* Initialize peripheral function select */ + pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(4) + | IPSR_24_FUNC(4) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(4) + | IPSR_24_FUNC(4) + | IPSR_20_FUNC(4) + | IPSR_16_FUNC(4) + | IPSR_12_FUNC(4) + | IPSR_8_FUNC(4) + | IPSR_4_FUNC(4) + | IPSR_0_FUNC(4)); + pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) + | IPSR_24_FUNC(4) + | IPSR_20_FUNC(4) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(4)); + pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(4) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + + /* Initialize GPIO/perihperal function select */ + pfc_reg_write(PFC_GPSR0, 0x00000000); + + pfc_reg_write(PFC_GPSR1, GPSR1_DIGRF_CLKOUT + | GPSR1_DIGRF_CLKIN + | GPSR1_CANFD_CLK_A + | GPSR1_CANFD0_RX_A + | GPSR1_CANFD0_TX_A + | GPSR1_AVB_LINK + | GPSR1_AVB_PHY_INT + | GPSR1_AVB_MDC + | GPSR1_AVB_MDIO + | GPSR1_AVB_TXCREFCLK + | GPSR1_AVB_TD3 + | GPSR1_AVB_TD2 + | GPSR1_AVB_TD1 + | GPSR1_AVB_TD0 + | GPSR1_AVB_TXC + | GPSR1_AVB_TX_CTL + | GPSR1_AVB_RD3 + | GPSR1_AVB_RD2 + | GPSR1_AVB_RD1 + | GPSR1_AVB_RD0 + | GPSR1_AVB_RXC + | GPSR1_AVB_RX_CTL + | GPSR1_IRQ0); + + pfc_reg_write(PFC_GPSR2, 0x00000000); + + pfc_reg_write(PFC_GPSR3, GPSR3_VI1_FIELD + | GPSR3_VI1_DATA11 + | GPSR3_VI1_DATA10 + | GPSR3_VI1_DATA9 + | GPSR3_VI1_DATA8 + | GPSR3_VI1_DATA7 + | GPSR3_VI1_DATA6 + | GPSR3_VI1_DATA5 + | GPSR3_VI1_DATA4 + | GPSR3_VI1_DATA3 + | GPSR3_VI1_DATA2); + + pfc_reg_write(PFC_GPSR4, GPSR4_GETHER_LINK_A + | GPSR4_GETHER_PHY_INT_A + | GPSR4_GETHER_MDC_A + | GPSR4_GETHER_MDIO_A + | GPSR4_GETHER_TXCREFCLK_MEGA + | GPSR4_GETHER_TXCREFCLK + | GPSR4_GETHER_TD3 + | GPSR4_GETHER_TD2 + | GPSR4_GETHER_TD1 + | GPSR4_GETHER_TD0 + | GPSR4_GETHER_TXC + | GPSR4_GETHER_TX_CTL + | GPSR4_GETHER_RD3 + | GPSR4_GETHER_RD2 + | GPSR4_GETHER_RD1 + | GPSR4_GETHER_RD0 + | GPSR4_GETHER_RXC + | GPSR4_GETHER_RX_CTL + | GPSR4_SDA2 + | GPSR4_SCL2 + | GPSR4_SDA1 + | GPSR4_SCL1 + | GPSR4_SDA0 + | GPSR4_SCL0); + + pfc_reg_write(PFC_GPSR5, GPSR5_QSPI1_SSL + | GPSR5_QSPI1_IO3 + | GPSR5_QSPI1_IO2 + | GPSR5_QSPI1_MISO_IO1 + | GPSR5_QSPI1_MOSI_IO0 + | GPSR5_QSPI1_SPCLK + | GPSR5_QSPI0_SSL + | GPSR5_QSPI0_IO3 + | GPSR5_QSPI0_IO2 + | GPSR5_QSPI0_MISO_IO1 + | GPSR5_QSPI0_MOSI_IO0 + | GPSR5_QSPI0_SPCLK); + + /* Initialize POC Control */ + pfc_reg_write(PFC_IOCTRL30, IOCTRL30_POC_VI0_DATA5 + | IOCTRL30_POC_VI0_DATA4 + | IOCTRL30_POC_VI0_DATA3 + | IOCTRL30_POC_VI0_DATA2 + | IOCTRL30_POC_VI0_DATA1 + | IOCTRL30_POC_VI0_DATA0 + | IOCTRL30_POC_VI0_VSYNC_N + | IOCTRL30_POC_VI0_HSYNC_N + | IOCTRL30_POC_VI0_CLKENB + | IOCTRL30_POC_VI0_CLK + | IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE + | IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC + | IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC + | IOCTRL30_POC_DU_DOTCLKOUT + | IOCTRL30_POC_DU_DB7 + | IOCTRL30_POC_DU_DB6 + | IOCTRL30_POC_DU_DB5 + | IOCTRL30_POC_DU_DB4 + | IOCTRL30_POC_DU_DB3 + | IOCTRL30_POC_DU_DB2 + | IOCTRL30_POC_DU_DG7 + | IOCTRL30_POC_DU_DG6 + | IOCTRL30_POC_DU_DG5 + | IOCTRL30_POC_DU_DG4 + | IOCTRL30_POC_DU_DG3 + | IOCTRL30_POC_DU_DG2 + | IOCTRL30_POC_DU_DR7 + | IOCTRL30_POC_DU_DR6 + | IOCTRL30_POC_DU_DR5 + | IOCTRL30_POC_DU_DR4 + | IOCTRL30_POC_DU_DR3 + | IOCTRL30_POC_DU_DR2); + + pfc_reg_write(PFC_IOCTRL31, IOCTRL31_POC_MSIOF0_SS2 + | IOCTRL31_POC_MSIOF0_SS1 + | IOCTRL31_POC_MSIOF0_SYNC + | IOCTRL31_POC_MSIOF0_SCK + | IOCTRL31_POC_MSIOF0_TXD + | IOCTRL31_POC_MSIOF0_RXD + | IOCTRL31_POC_MSIOF0_IRQ5 + | IOCTRL31_POC_MSIOF0_IRQ4 + | IOCTRL31_POC_VI1_FIELD + | IOCTRL31_POC_VI1_DATA11 + | IOCTRL31_POC_VI1_DATA10 + | IOCTRL31_POC_VI1_DATA9 + | IOCTRL31_POC_VI1_DATA8 + | IOCTRL31_POC_VI1_DATA7 + | IOCTRL31_POC_VI1_DATA6 + | IOCTRL31_POC_VI1_DATA5 + | IOCTRL31_POC_VI1_DATA4 + | IOCTRL31_POC_VI1_DATA3 + | IOCTRL31_POC_VI1_DATA2 + | IOCTRL31_POC_VI1_DATA1 + | IOCTRL31_POC_VI1_DATA0 + | IOCTRL31_POC_VI1_VSYNC + | IOCTRL31_POC_VI1_HSYNC + | IOCTRL31_POC_VI1_CLKENB + | IOCTRL31_POC_VI1_CLK + | IOCTRL31_POC_VI0_FIELD + | IOCTRL31_POC_VI0_DATA11 + | IOCTRL31_POC_VI0_DATA10 + | IOCTRL31_POC_VI0_DATA9 + | IOCTRL31_POC_VI0_DATA8 + | IOCTRL31_POC_VI0_DATA7 + | IOCTRL31_POC_VI0_DATA6 + | IOCTRL31_POC_VI0_DATA6); + + pfc_reg_write(PFC_IOCTRL32, IOCTRL32_POC_FSO_TOE + | IOCTRL32_POC_FSO_CFE_1 + | IOCTRL32_POC_FSO_CFE_0 + | IOCTRL32_POC_SDA3 + | IOCTRL32_POC_SCL3); + + pfc_reg_write(PFC_IOCTRL33,0x00000000); + + pfc_reg_write(PFC_IOCTRL40,0x00000000); + + /* Initialize LSI pin pull-up/down control */ + pfc_reg_write(PFC_PUD0,0x80000000U); + pfc_reg_write(PFC_PUD1,0x1B01C77CU); + pfc_reg_write(PFC_PUD2,0x00000000U); + pfc_reg_write(PFC_PUD3,0x0F800008U); + pfc_reg_write(PFC_PUD4,0x03807C00U); + + /* Initialize LSI pin pull-enable register */ + pfc_reg_write(PFC_PUEN0,0x00000700U); + pfc_reg_write(PFC_PUEN1,0x7E01C700U); + pfc_reg_write(PFC_PUEN2,0x003F0000U); + pfc_reg_write(PFC_PUEN3,0x07000000U); + pfc_reg_write(PFC_PUEN4,0x0381E800U); + + /* Initialize positive/negative logic select */ + mem_write32(GPIO_POSNEG0, 0x00000000U); + mem_write32(GPIO_POSNEG1, 0x00000000U); + mem_write32(GPIO_POSNEG2, 0x00000000U); + mem_write32(GPIO_POSNEG3, 0x00000000U); + mem_write32(GPIO_POSNEG4, 0x00000000U); + mem_write32(GPIO_POSNEG5, 0x00000000U); + + /* Initialize general IO/interrupt switching */ + mem_write32(GPIO_IOINTSEL0, 0x00000000U); + mem_write32(GPIO_IOINTSEL1, 0x00000000U); + mem_write32(GPIO_IOINTSEL2, 0x00000000U); + mem_write32(GPIO_IOINTSEL3, 0x00000000U); + mem_write32(GPIO_IOINTSEL4, 0x00000000U); + mem_write32(GPIO_IOINTSEL5, 0x00000000U); + + /* Initialize general output register */ + mem_write32(GPIO_OUTDT0, 0x00000000U); + mem_write32(GPIO_OUTDT1, 0x00010000U); + mem_write32(GPIO_OUTDT2, 0x00000000U); + mem_write32(GPIO_OUTDT3, 0x00000000U); + mem_write32(GPIO_OUTDT4, 0x00400000U); + mem_write32(GPIO_OUTDT5, 0x00007000U); + + /* Initialize general input/output switching */ + mem_write32(GPIO_INOUTSEL0, 0x00000000U); + mem_write32(GPIO_INOUTSEL1, 0x00010000U); + mem_write32(GPIO_INOUTSEL2, 0x00000000U); + mem_write32(GPIO_INOUTSEL3, 0x00000000U); + mem_write32(GPIO_INOUTSEL4, 0x00400000U); + mem_write32(GPIO_INOUTSEL5, 0x00007000U); +} +/* End of function pfc_init(void) */ + +void pfc_reg_write(uintptr_t addr, uint32_t data) +{ + mem_write32((uintptr_t)PFC_PMMR, ~data); + mem_write32(addr, data); +} +/* End of function pfc_reg_write(uintptr_t addr, uint32_t data) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/qos/qos.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/qos/qos.c new file mode 100644 index 0000000..e54e4b3 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/qos/qos.c @@ -0,0 +1,327 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : QoS initialize function + ******************************************************************************/ +/****************************************************************************** + * @file qos.c + * - Version : 0.02 + * @brief Initial setting process of QoS. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + * : 17.08.2020 0.02 Update QoS setting(rev0.10) + *****************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include +#include +#include +#else +#include +#endif +#include +#include +#include +#include +#include /* V3H: PRR */ + + +#define RCAR_QOS_VERSION "rev.0.11" + +#define RCAR_REWT_TRAINING_DISABLE (0U) +#define RCAR_REWT_TRAINING_ENABLE (1U) + + +#if defined(__RH850G3K__) +#define DBSC_BASE (BASE_DBSC_ADDR) +#else +#define DBSC_BASE (0xE6790000U) +#endif +#define DBSC_SYSCNT0 (DBSC_BASE + 0x0100U) +#define DBSC_SYSCNT1 (DBSC_BASE + 0x0104U) +#define DBSC_AXARB (DBSC_BASE + 0x0800U) +#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U) +#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) +#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) +#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU) +#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) +#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) +#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U) +#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) +#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) +#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) +#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) +#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) +#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) +#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) +#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) +#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) +#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) +#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) +#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) +#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) +#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) +#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) +#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) +#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) +#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) +#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) +#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) +#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) +#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) +#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) +#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U) +#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U) +#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) + + +#if defined(__RH850G3K__) +#define MSTAT_BASE (BASE_MSTAT_ADDR) +#else +#define MSTAT_BASE (0xE67E0000U) +#endif +#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U) +#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U) +#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U) +#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U) +#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U) +#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U) +#define MSTAT_STATQC (MSTAT_BASE + 0x8008U) +#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE +#define QOSWT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0800U) +#define QOSWT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1800U) +#define QOSWT_BE_QOS_BANK0 (MSTAT_BASE + 0x2800U) +#define QOSWT_BE_QOS_BANK1 (MSTAT_BASE + 0x3800U) +#define QOSWT_WTEN (MSTAT_BASE + 0x8030U) +#define QOSWT_WTREF (MSTAT_BASE + 0x8034U) +#define QOSWT_WTSET0 (MSTAT_BASE + 0x8038U) +#define QOSWT_WTSET1 (MSTAT_BASE + 0x803CU) +#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + +#if defined(__RH850G3K__) +#define RALLOC_BASE (BASE_QOS_ADDR) +#else +#define RALLOC_BASE (0xE67F0000U) +#endif +#define RALLOC_RAS (RALLOC_BASE + 0x0000U) +#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U) +#define RALLOC_RAEN (RALLOC_BASE + 0x0018U) +#define RALLOC_REGGD (RALLOC_BASE + 0x0020U) +#define RALLOC_DANN_LOW (RALLOC_BASE + 0x0030U) +#define RALLOC_DANN_HIGH (RALLOC_BASE + 0x0034U) +#define RALLOC_DANT (RALLOC_BASE + 0x0038U) +#define RALLOC_EC (RALLOC_BASE + 0x003CU) +#define RALLOC_EMS_LOW (RALLOC_BASE + 0x0040U) +#define RALLOC_EMS_HIGH (RALLOC_BASE + 0x0044U) +#define RALLOC_FSS (RALLOC_BASE + 0x0048U) +#define RALLOC_INSFC (RALLOC_BASE + 0x0050U) +#define RALLOC_BERR (RALLOC_BASE + 0x0054U) +#define RALLOC_EARLYR (RALLOC_BASE + 0x0060U) +#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U) + + +#if defined(__RH850G3K__) +#define RT_ACT_BASE (BASE_RTACT_ADDR) +#else +#define RT_ACT_BASE (0xFFC50800U) +#endif +#define RT_ACT0 (RT_ACT_BASE + 0x0000U) +#define RT_ACT1 (RT_ACT_BASE + 0x1000U) + +#define CPU_ACT_BASE (0xF1300800U) +#define CPU_ACT_REMAP_SIZE (0x00040010U) +#define CPU_ACT1_OFFSET (0x00040000U) + + +#define OPERATING_FREQ (400U) /* MHz */ +#define BASE_SUB_SLOT_NUM (0x6U) +#define SUB_SLOT_CYCLE (0x7EU) /* 126 */ + +#define QOSWT_WTSET0_CYCLE ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ) /* unit:ns */ + +/* Calculating the number of array */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + + +static void dbsc_setting(void) +{ + /* DBSC CAM, Scheduling Setting */ + mem_write32(DBSC_SYSCNT0, 0x00001234U); + mem_write32(DBSC_DBCAM0CNF1, 0x00043218U); /* dbcam0cnf1 */ + mem_write32(DBSC_DBCAM0CNF2, 0x000000F4U); /* dbcam0cnf2 */ + mem_write32(DBSC_DBCAM0CNF3, 0x00000000U); /* dbcam0cnf3 */ + mem_write32(DBSC_DBSCHCNT0, 0x000F0037U); /* dbschcnt0 */ + mem_write32(DBSC_DBSCHSZ0, 0x00000001U); /* dbschsz0 */ + mem_write32(DBSC_DBSCHRW0, 0x22421111U); /* dbschrw0 */ + mem_write32(DBSC_SCFCTST2, 0x012F1123U); + + /* DBSC QoS Setting */ + mem_write32(DBSC_DBSCHQOS_0_0, 0x00000F00U); + mem_write32(DBSC_DBSCHQOS_0_1, 0x00000B00U); + mem_write32(DBSC_DBSCHQOS_0_2, 0x00000000U); + mem_write32(DBSC_DBSCHQOS_0_3, 0x00000000U); + mem_write32(DBSC_DBSCHQOS_4_0, 0x00000300U); + mem_write32(DBSC_DBSCHQOS_4_1, 0x000002F0U); + mem_write32(DBSC_DBSCHQOS_4_2, 0x00000200U); + mem_write32(DBSC_DBSCHQOS_4_3, 0x00000100U); + mem_write32(DBSC_DBSCHQOS_9_0, 0x00000100U); + mem_write32(DBSC_DBSCHQOS_9_1, 0x000000F0U); + mem_write32(DBSC_DBSCHQOS_9_2, 0x000000A0U); + mem_write32(DBSC_DBSCHQOS_9_3, 0x00000040U); + mem_write32(DBSC_DBSCHQOS_12_0, 0x00000040U); + mem_write32(DBSC_DBSCHQOS_12_1, 0x00000030U); + mem_write32(DBSC_DBSCHQOS_12_2, 0x00000020U); + mem_write32(DBSC_DBSCHQOS_12_3, 0x00000010U); + mem_write32(DBSC_DBSCHQOS_13_0, 0x00000100U); + mem_write32(DBSC_DBSCHQOS_13_1, 0x000000F0U); + mem_write32(DBSC_DBSCHQOS_13_2, 0x000000A0U); + mem_write32(DBSC_DBSCHQOS_13_3, 0x00000040U); + mem_write32(DBSC_DBSCHQOS_14_0, 0x000000C0U); + mem_write32(DBSC_DBSCHQOS_14_1, 0x000000B0U); + mem_write32(DBSC_DBSCHQOS_14_2, 0x00000080U); + mem_write32(DBSC_DBSCHQOS_14_3, 0x00000040U); + mem_write32(DBSC_DBSCHQOS_15_0, 0x00000040U); + mem_write32(DBSC_DBSCHQOS_15_1, 0x00000030U); + mem_write32(DBSC_DBSCHQOS_15_2, 0x00000020U); + mem_write32(DBSC_DBSCHQOS_15_3, 0x00000010U); + + mem_write32(DBSC_SYSCNT0, 0x00000000U); +} +/* End of function dbsc_setting(void) */ + +void qos_init(void) +{ + uint32_t i; + uint32_t remap_addr; + uint32_t prr_major_ver; + uint32_t qoswt_tablenum; + + /* Setting the register of DBSC4 for QoS initialize */ + dbsc_setting(); + + NOTICE("QoS setting(%s)\n", RCAR_QOS_VERSION); + NOTICE("DRAM refresh interval 1.89 usec\n"); + +#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE + NOTICE("Periodic Write DQ Training\n"); +#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + + /* Resource Alloc setting */ + mem_write32(RALLOC_RAS, 0x00000028U); + mem_write32(RALLOC_DANN_LOW, 0x02020201U); + mem_write32(RALLOC_DANN_HIGH, 0x04020000U); + mem_write32(RALLOC_DANT, 0x00100804U); + mem_write32(RALLOC_FSS, 0x0000000AU); + mem_write32(RALLOC_INSFC, 0x06330001U); + mem_write32(RALLOC_RACNT0, 0x00050003U); + + /* QoS MSTAT setting */ + mem_write32(MSTAT_SL_INIT, 0x0305007DU); + mem_write32(MSTAT_REF_ARS, 0x00780000U); + for (i = 0U; i < ARRAY_SIZE(mstat_tbl); i++) + { + mem_write64(MSTAT_FIX_QOS_BANK0 + mstat_tbl[i].offset, + mstat_tbl[i].mstat_fix); + mem_write64(MSTAT_FIX_QOS_BANK1 + mstat_tbl[i].offset, + mstat_tbl[i].mstat_fix); + mem_write64(MSTAT_BE_QOS_BANK0 + mstat_tbl[i].offset, + mstat_tbl[i].mstat_be); + mem_write64(MSTAT_BE_QOS_BANK1 + mstat_tbl[i].offset, + mstat_tbl[i].mstat_be); + } + /* V3H */ + prr_major_ver = mem_read32(PRR) & PRR_MAJOR_MASK; + if(prr_major_ver != 0U) /* Not Ver.1.x */ + { + for (i = 0U; i < ARRAY_SIZE(mstat_v2_tbl); i++) + { + mem_write64(MSTAT_FIX_QOS_BANK0 + mstat_v2_tbl[i].offset, + mstat_v2_tbl[i].mstat_fix); + mem_write64(MSTAT_BE_QOS_BANK0 + mstat_v2_tbl[i].offset, + mstat_v2_tbl[i].mstat_be); + } + } + +#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE + qoswt_tablenum = ARRAY_SIZE(qoswt_tbl); + if(prr_major_ver == 0U) /* Ver.1.x */ + { + qoswt_tablenum -= 2U; + } + for (i = 0U; i < qoswt_tablenum; i++) + { + mem_write64(MSTAT_FIX_QOS_BANK0 + qoswt_tbl[i].offset, + qoswt_tbl[i].qoswt_fix); + mem_write64(MSTAT_FIX_QOS_BANK1 + qoswt_tbl[i].offset, + qoswt_tbl[i].qoswt_fix); + mem_write64(MSTAT_BE_QOS_BANK0 + qoswt_tbl[i].offset, + qoswt_tbl[i].qoswt_be); + mem_write64(MSTAT_BE_QOS_BANK1 + qoswt_tbl[i].offset, + qoswt_tbl[i].qoswt_be); + } +#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + + /* RT bus Leaf setting */ + mem_write32(RT_ACT0, 0x00000000U); + mem_write32(RT_ACT1, 0x00000000U); + + /* CPU bus Leaf setting */ + remap_register(CPU_ACT_BASE, CPU_ACT_REMAP_SIZE, &remap_addr); + mem_write32(remap_addr, 0x00000003U); + mem_write32((remap_addr + CPU_ACT1_OFFSET), 0x00000003U); + remap_unregister(remap_addr); + + /* QoS SRAM setting */ + mem_write32(RALLOC_RAEN, 0x00000001U); +#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE + mem_write32(QOSWT_WTREF, 0x02080208U); + mem_write32(QOSWT_WTSET0, 0x2955040BU); + mem_write32(QOSWT_WTSET1, 0x2955040BU); + mem_write32(QOSWT_WTEN, 0x00000001U); +#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + mem_write32(MSTAT_STATQC, 0x00000001U); +} +/* End of function qos_init(void) */ + +uint32_t get_refperiod(void) +{ + return QOSWT_WTSET0_CYCLE; +} +/* End of function get_refperiod(void) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/rpc/rpc.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/rpc/rpc.c new file mode 100644 index 0000000..b8b75fc --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/rpc/rpc.c @@ -0,0 +1,116 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RPC driver + ******************************************************************************/ +/****************************************************************************** + * @file rpc.c + * - Version : 0.01 + * @brief Initial setting process of RPC. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include + +#define RPC_PHYCNT_CAL ((uint32_t)1U << 31U) +#define RPC_PHYCNT_STRTIM ((uint32_t)0x7U << 15U) +#define RPC_DRCR_RCF ((uint32_t)1U << 9U) +#define RPC_DRCMR_CMD_MASK (0x00FF0000U) +#define RPC_DRCMR_READ_32BIT_ADDR ((uint32_t)0x13U << 16U) +#define RPC_DRCMR_HW_INIT (0x00030000U) +#define RPC_DREAR_EAC_EXT_ADDR_25BIT ((uint32_t)0x1U << 0U) +#define RPC_DREAR_HW_INIT (0x00000000U) +#define RPC_DRENR_CDE_ENABLE ((uint32_t)0x1U << 14U) +#define RPC_DRENR_ADE_MASK (0x00000F00U) +#define RPC_DRENR_ADE_32BIT_ADDR ((uint32_t)0xFU << 8U) +#define RPC_DRENR_HW_INIT (0x00004700U) +#define CMNSR_TEND (0x00000001U) + +void rpc_init(void) +{ + uint32_t reg; + + /* check the transfer end flag */ + rpc_end_state_check(); + + /* For the initial setting flow of RPC, see Figure 62.12 in */ + /* "R-Car Series, 3rd Generation User's Manual". */ + /* This RPC setting is for S25FS512S device */ + /* A register that does not set a value expects */ + /* the initial value of HW. */ + + /* PHY calibration */ + reg = mem_read32(RPC_PHYCNT); + reg |= RPC_PHYCNT_STRTIM; + mem_write32(RPC_PHYCNT, reg); + reg |= RPC_PHYCNT_CAL; + mem_write32(RPC_PHYCNT, reg); + /* Read cache Flash */ + reg = mem_read32(RPC_DRCR); + mem_write32(RPC_DRCR, (reg | RPC_DRCR_RCF)); + /* 32bit address read command*/ + mem_write32(RPC_DRCMR, RPC_DRCMR_READ_32BIT_ADDR); + /* Extended external address valid range is [25:0]*/ + mem_write32(RPC_DREAR, RPC_DREAR_EAC_EXT_ADDR_25BIT); + /* output command is 32bit width */ + mem_write32(RPC_DRENR, + ( RPC_DRENR_CDE_ENABLE | RPC_DRENR_ADE_32BIT_ADDR)); +} +/* End of function rpc_init(void) */ + +void rpc_release(void) +{ + uint32_t reg; + + /* RPC restore to initial value of HW. */ + reg = mem_read32(RPC_DRCR); + mem_write32(RPC_DRCR, (reg | RPC_DRCR_RCF)); + mem_write32(RPC_DRCMR, RPC_DRCMR_HW_INIT); + mem_write32(RPC_DREAR, RPC_DREAR_HW_INIT); + mem_write32(RPC_DRENR, RPC_DRENR_HW_INIT); +} +/* End of function rpc_release(void) */ + +void rpc_end_state_check(void) +{ + /* Wait until RPC data transfer is completed */ + while ((mem_read32(RPC_CMNSR) & CMNSR_TEND) != 1U) + { + ; + } +} +/* End of function rpc_end_state_check(void) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/wdt/wdt.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/wdt/wdt.c new file mode 100644 index 0000000..286c64d --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/ip/wdt/wdt.c @@ -0,0 +1,96 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : window watchdog timer driver + ******************************************************************************/ +/****************************************************************************** + * @file wdt.c + * - Version : 0.01 + * @brief Window Watchdog Timer driver + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include + + +#define ICUMX_WDTA0_BASE (0xFFFEE080U) /* Watchdog Timer base */ +#define ICUMX_WDTA0WDTE (ICUMX_WDTA0_BASE) +#define ICUMX_WDTA0EVAC (ICUMX_WDTA0_BASE+0x0004U) +#define ICUMX_WDTA0REF (ICUMX_WDTA0_BASE+0x0008U) +#define ICUMX_WDTA0MD (ICUMX_WDTA0_BASE+0x000CU) + + +#define WDTA0MD_WDTA0WIE (uint8_t)(1U<<3U) /* Enables the 75% interrupt request INTWDTA0 */ +#define WDTA0MD_WDTA0ERM (uint8_t)(1U<<2U) /* 0:NMI request mode 1:Reset mode */ +#define WDTA0MD_WDTA0WS10 (3U) /* 11B: window-open period is 100% */ + +/* overflow time setting */ +#define WDT_11MS (uint8_t)(0x00U) +#define WDT_23MS (uint8_t)(0x01U) +#define WDT_46MS (uint8_t)(0x02U) +#define WDT_93MS (uint8_t)(0x03U) +#define WDT_187MS (uint8_t)(0x04U) +#define WDT_374MS (uint8_t)(0x05U) +#define WDT_749MS (uint8_t)(0x06U) +#define WDT_1498MS (uint8_t)(0x07U) + +/* Activation code */ +#define WDT_ACT_CODE (0xACU) + + +/* Initialization Window Watchdog Timer */ +void wdt_init(void) +{ + uint8_t wdta_val; + + /* This API is executed before copying a part of Loader to Local RAM. */ + /* Therefore, this API can not use the Memory mapped I/O API. */ + /* When reading or writing memory, execute the same processing as */ + /* Memory mapped I/O API in this function. */ + wdta_val = (WDTA0MD_WDTA0ERM /* NMI request mode */ + | WDTA0MD_WDTA0WIE /* Enables the 75% interrupt request INTWDTA0 */ + | WDTA0MD_WDTA0WS10 + | (uint8_t)(WDT_187MS << 4U)); /* overflow interval time */ + *(volatile uint8_t*)ICUMX_WDTA0MD = wdta_val; +} +/* End of function wdt_init(void) */ + +void wdt_restart(void) +{ + uint8_t reg; + reg = mem_read8(ICUMX_WDTA0REF); + mem_write8(ICUMX_WDTA0EVAC, (WDT_ACT_CODE - reg)); +} +/* End of function wdt_restart(void) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/loader/cpu_on.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/loader/cpu_on.c new file mode 100644 index 0000000..dfd1589 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/loader/cpu_on.c @@ -0,0 +1,197 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Power management driver + ******************************************************************************/ +/****************************************************************************** + * @file cpu_on.c + * - Version : 0.01 + * @brief Boot process of ARM CPU. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define BIT_CA53_SCU ((uint32_t)1U << 21U) +#define BIT_CR7 ((uint32_t)1U << 13U) +#define REQ_RESUME ((uint32_t)1U << 1U) +#define NOT_REQ_RESUME ((uint32_t)0U << 1U) +#define SYSC_STATUS_PWRDOWN ((uint32_t)1U << 0U) +#define SYSC_STATUS_PWRUP ((uint32_t)1U << 4U) +#define APMU_STATUS_PWRUP ((uint32_t)3U << 0U) +#define CPG_SRSTCLR2_CR7 ((uint32_t)1U << 22U) + +#define RST_UPPER_VALUE ((uint32_t)0x5A5A0000U); + +#define CA53_CORE_NUM (0U) +#define CA53_CORE_NUM_MAX (3U) +#define CA53_CORE_WAKEUP_COMP (0U) +#define CR7_CORE_STANDBY (0x00000003U) +#define CR7_CORE_RUNMODE (0x00000000U) +#define PWRONCR_PWRUP_START (0x00000001U) +#define PWRER_ERR (0x00000001U) +#define PWRER_NOT_ERR (0x00000000U) +#define PWR_RESUME_COMP (0U) +#define SYSC_NOT_PWRDOWN_FLAG (0x00000000U) + +static void domain_power_on(uint32_t target); + +void arm_cpu_set_address(uint32_t target, uint32_t boot_addr) +{ + if(RCAR_PWR_TARGET_CR7 == target) + { + /* CR7 Boot address set */ + lifec_set_master_grp(LIFEC_TGT_M_ICUMX, LIFEC_PUBLIC, + LIFEC_GROUP3); + mem_write32(RST_CR7BAR2, (uint32_t)(boot_addr | RST_CR7BAR2_VLD)); + mem_write32(RST_CR7BAR2, (uint32_t)(boot_addr + | RST_CR7BAR2_VLD | RST_CR7BAR_BAREN)); + } + else + { + /* CA53 Boot address set */ + mem_write32(RST_CA53CPU0BARL, boot_addr); + mem_write32(RST_CA53CPU0BARH, 0x00000000U); + } +} +/* End of function arm_cpu_set_address(uint32_t target, uint32_t boot_addr) */ + +void arm_cpu_on(uint32_t target, uint32_t boot_addr) +{ + uint32_t res_data; + + if(RCAR_PWR_TARGET_CR7 == target) + { + /* CR7 power supply */ + domain_power_on(target); + /* Wait until Power ON */ + do + { + res_data = mem_read32(SYSC_PWRSR7); + }while(((uint32_t)(SYSC_STATUS_PWRUP) & res_data) + != (uint32_t)(SYSC_STATUS_PWRUP)); + + do + { + res_data = mem_read32(APMU_CR7PSTR); + }while(((uint32_t)APMU_STATUS_PWRUP & res_data) + != CR7_CORE_RUNMODE); + /* CR7 reset */ + mem_write32(CPG_SRSTCLR2, CPG_SRSTCLR2_CR7); + } + else + { + /* CA53 SCU power supply */ + domain_power_on(target); + /* CA53 Boot address set */ + arm_cpu_set_address(target, boot_addr); + /* CA53 core0 power supply */ + mem_write32(APMU_CA53WUPCR, ((uint32_t)1U << CA53_CORE_NUM)); + /* Wait until CA53 core0 power on */ + do + { + res_data = mem_read32(APMU_CA53WUPCR); + }while(((uint32_t)((uint32_t)1U << CA53_CORE_NUM) & res_data) + != CA53_CORE_WAKEUP_COMP); + /* CA53 core0 reset */ + res_data = mem_read32(RST_CA53RESCNT) | RST_UPPER_VALUE; + mem_write32(RST_CA53RESCNT, (res_data & + (~((uint32_t)1U << (CA53_CORE_NUM_MAX - CA53_CORE_NUM))))); + } +} +/* End of function arm_cpu_on(uint32_t target, uint32_t boot_addr) */ + +static void domain_power_on(uint32_t target) +{ + const uint32_t reg_SYSCIER = SYSC_SYSCIER; + const uint32_t reg_SYSCIMR = SYSC_SYSCIMR; + const uint32_t reg_SYSCSR = SYSC_SYSCSR; + const uint32_t reg_SYSCISR = SYSC_SYSCISR; + const uint32_t reg_SYSCISCR = SYSC_SYSCISCR; + uint32_t reg_PWRONCR; + uint32_t reg_PWRSR; + uint32_t reg_PWRER; + uint32_t reg_SYSC_bit; + + if(RCAR_PWR_TARGET_CR7 == target) + { + reg_PWRONCR = SYSC_PWRONCR7; + reg_PWRSR = SYSC_PWRSR7; + reg_PWRER = SYSC_PWRER7; + reg_SYSC_bit = (uint32_t)BIT_CR7; + } + else + { + reg_PWRONCR = SYSC_PWRONCR3; + reg_PWRSR = SYSC_PWRSR3; + reg_PWRER = SYSC_PWRER3; + reg_SYSC_bit = (uint32_t)BIT_CA53_SCU; + } + + if ((mem_read32(reg_PWRSR) & (uint32_t)(SYSC_STATUS_PWRDOWN)) + != SYSC_NOT_PWRDOWN_FLAG) + { + /* Enable status update interrupt */ + mem_write32(reg_SYSCIER, + (mem_read32(reg_SYSCIER) | reg_SYSC_bit)); + mem_write32(reg_SYSCIMR, + (mem_read32(reg_SYSCIMR) | reg_SYSC_bit)); + do + { + /* Wait until it is ready to accept the power resume request of the CPU */ + while ((mem_read32(reg_SYSCSR) & + (uint32_t)(REQ_RESUME)) == NOT_REQ_RESUME) + { + ; + } + /* Set the power resume of CPU */ + mem_write32(reg_PWRONCR, PWRONCR_PWRUP_START); + } while ((mem_read32(reg_PWRER) & PWRER_ERR) != PWRER_NOT_ERR); + + /* Wait until power resume processing is completed */ + while ((mem_read32(reg_SYSCISR) & reg_SYSC_bit) == PWR_RESUME_COMP) + { + ; + } + /* Clear the status of SYSCISR */ + mem_write32(reg_SYSCISCR, reg_SYSC_bit); + } +} +/* End of function domain_power_on(uint32_t target) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/loader/icumxa_loader.ld b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/loader/icumxa_loader.ld new file mode 100644 index 0000000..5f4fdd8 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/loader/icumxa_loader.ld @@ -0,0 +1,147 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader linker directive + ******************************************************************************/ + +DEFAULTS { +//Memory + remap_addr = 0xFDE00000 //remap15 address(target address = 0xEB200000) + remap_size = 1M //RT-SRAM size + + rt_sram_addr = 0xEB200000 //RT-SRAM address + local_ram_addr = 0xfedf0000 //LRAM address + local_ram_size = 64K //LRAM size + + rom_size = 128K //ICUMXA Loader rom size + ram_size = 32K //ICUMXA Loader local_ram size + +//No override area + key_cert_size = 1K + stack_size = 6K //ICUMXA Loader stack size + content_cert_size = 11K //content cert size(cert info 1K + content cert(10) * 2K) + + icumx_start_address_offset = remap_size - 32K - rom_size + ipl_top_addr = rt_sram_addr + icumx_start_address_offset + + stack_addr_offset = remap_size - stack_size + key_addr_offset = stack_addr_offset - key_cert_size + cert_addr_offset = key_addr_offset - content_cert_size + + code_fetch_remap = 0x1200000 + icumx_start_address_offset // 0xEB200000 - 0xEA000000 + ipl start address offset +} +MEMORY +{ + rom : ORIGIN = code_fetch_remap, LENGTH = rom_size //ICUMXA Loader ROM(CFREMAP) + + cert_load : ORIGIN = remap_addr + cert_addr_offset, LENGTH = content_cert_size // + key_load : ORIGIN = remap_addr + key_addr_offset, LENGTH = key_cert_size // + stack : ORIGIN = remap_addr + stack_addr_offset, LENGTH = stack_size // ICUMXA Loader stack + + local_ram : ORIGIN = local_ram_addr, LENGTH = ram_size // Local RAM + local_stack : ORIGIN = local_ram_addr + local_ram_size - stack_size, LENGTH = stack_size // Local RAM stack + + rom_phys : ORIGIN = rt_sram_addr + icumx_start_address_offset, LENGTH = rom_size //ICUMXA Loader(RT-SRAM) +} + +// +// Program layout for starting in ROM, copying data to RAM, +// and continuing to execute out of ROM. +// +SECTIONS +{ +// +// ROM SECTIONS(Remap) +// +// Place .text into fast_memory. Fail if it does not fit. + .reset ALIGN(4) : > rom + .version ALIGN(1024) :{*(.version)} > . + .text_1st ALIGN(4) : { + dram_sub_func.o(.text) + boot_init_dram_regcheck.o(.text) + pfc.o(.text) + qos.o(.text) + mfis.o(.text) + acc_prot_lifec.o(.text) + acc_prot_memory.o(.text) + acc_prot.o(.text) + } > . + .rodata_1st ALIGN(4) : { + boot_init_dram_regcheck.o(.rodata) + qos.o(.rodata) + mfis.o(.rodata) + acc_prot_lifec.o(.rodata) + acc_prot_memory.o(.rodata) + } > . + .dst_local_ram_start ALIGN(512) : > local_ram + .EIINTTBL_ICU ALIGN(512) : > . + .text ALIGN(4) : > . + .rosdata ALIGN(4) : > . + .rodata ALIGN(4) : > . + .secinfo ALIGN(4) : > . + .data ALIGN(4) : > . + .dst_local_ram_end : > . +// .note.renesas ALIGN(4) : > . +// .linfix ALIGN(4) : > . +// .gstackfix ALIGN(4) : > . + +// ROM mirror SECTIONS(RT-SRAM) + _start = ipl_top_addr; + .ROM_NOCOPY.reset ROM_NOCOPY(.reset) ALIGN(4) : > rom_phys + .ROM_NOCOPY.version ROM_NOCOPY(.version) ALIGN(1024) : > . + .ROM_NOCOPY.text_1st ROM_NOCOPY(.text_1st) ALIGN(4) : > . + .ROM_NOCOPY.rodata_1st ROM_NOCOPY(.rodata_1st) ALIGN(4) : > . + .src_local_ram_start ALIGN(512) : > . + .ROM_NOCOPY.EIINTTBL_ICU ROM_NOCOPY(.EIINTTBL_ICU) ALIGN(4) : > . + .ROM_NOCOPY.text ROM_NOCOPY(.text) ALIGN(4) : > . + .ROM_NOCOPY.rosdata ROM_NOCOPY(.rosdata) ALIGN(4) : > . + .ROM_NOCOPY.rodata ROM_NOCOPY(.rodata) ALIGN(4) : > . + .ROM_NOCOPY.secinfo ROM_NOCOPY(.secinfo) ALIGN(4) : > . + .ROM_NOCOPY.data ROM_NOCOPY(.data) ALIGN(4) : > . + +// +// RAM SECTIONS +// + .top.local.ram : > local_ram + .bss ALIGN(4) : > . + .sdata : > . + .tdata : > . + .sdabase ALIGN(4) : > . + .ICU.stack ALIGN(4) PAD(stack_size) ABS : > local_stack + .end.local.ram : > . + + .top_stack : > stack + .RT.stack ALIGN(4) PAD(stack_size) ABS : > . + .end_stack : > . + + .cert_load ALIGN(4) PAD(content_cert_size) : > cert_load + .key_load ALIGN(4) PAD(key_cert_size) : > key_load + + +} diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/loader/loader.S b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/loader/loader.S new file mode 100644 index 0000000..61a04ee --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/loader/loader.S @@ -0,0 +1,138 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader start code + ******************************************************************************/ + + .global code_start + .global _loader_main + .global _wdt_init + .global ___ghsend_ICU_stack /* LRAM stack Hardware end address */ + .global ___ghsend_RT_stack /* RT-SRAM stack Logical end address */ + + .section ".reset", "ax" + .align 2 +code_start: +//; initialize registers +//# +//#_start_icu: + mov code_start_2, r1 + jmp r1 +code_start_2: + mov r0, r1 + mov r0, r2 + mov r0, r3 + mov r0, r4 + mov r0, r5 + mov r0, r6 + mov r0, r7 + mov r0, r8 + mov r0, r9 + mov r0, r10 + mov r0, r11 + mov r0, r12 + mov r0, r13 + mov r0, r14 + mov r0, r15 + mov r0, r16 + mov r0, r17 + mov r0, r18 + mov r0, r19 + mov r0, r20 + mov r0, r21 + mov r0, r22 + mov r0, r23 + mov r0, r24 + mov r0, r25 + mov r0, r26 + mov r0, r27 + mov r0, r28 + mov r0, r29 + ldsr r0, 0, 0 + ldsr r0, 16, 0 + +//clear stack area of BootROM + mov ___ghsbegin_top_stack, r6 + mov ___ghsbegin_end_stack, r7 +stack_clear: + st.dw r0, 0[r6] + addi 8, r6, r6 + cmp r7, r6 + bl stack_clear + +//RAM clear + mov ___ghsbegin_top_local_ram, r6 + mov ___ghsbegin_end_local_ram, r7 + mov r0, r1 +loop_clear: + st.dw r0, 0[r6] + addi 8, r6, r6 + cmp r7, r6 + bl loop_clear + +//set global pointer + mov ___ghsbegin_sdabase, gp +//set stack pointer + mov ___ghsend_RT_stack, sp + +// *************** +// RAM CODE COPY +// *************** + mov ___ghsbegin_dst_local_ram_start, r6 + mov ___ghsend_dst_local_ram_end, r7 + mov ___ghsbegin_src_local_ram_start, r8 + mov 0xEA000000, r9 + sub r9, r8 +loop_code_copy: + ld.dw 0[r8], r10 + st.dw r10, 0[r6] + addi 8, r6, r6 + addi 8, r8, r8 + cmp r7, r6 + bl loop_code_copy + +//ICUMXA Watchdog Timer initialize + jarl _wdt_init, lp + + mov local_ram_main, r1 + mov _loader_main, r2 + jmp r1 +.section ".text" +local_ram_main: + + + jarl [r2], lp + + jmp [r10] + nop + halt + + + + diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/loader/loader_main.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/loader/loader_main.c new file mode 100644 index 0000000..6fd5e3c --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/loader/loader_main.c @@ -0,0 +1,529 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main function + ******************************************************************************/ +/****************************************************************************** + * @file loader_main.c + * - Version : 0.01 + * @brief 1. IP initialization. + * 2. DMA transfer the binary image from Flash to RAM. + * 3. Authentication of the transferred image. + * 4. Boot CR52 and CA76 core. + * 5. Release of used resources. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Provided code */ +#include "../ip/ddr/boot_init_dram.h" + + +#define SECURE_BOOT (1U) +#define NORMALE_BOOT (0U) +#define RST_MODEMR_MD5 (0x00000020U) +#define PRR_DUMMY_REMAP_SIZE (0x00000100U) +#define SMONI_REMAP_SIZE (0x00022300U) + +#define SMONI_IPL_PARAM_OFFSET (0x00022200U) +#define SMONI_EP_INFO_OFFSET (SMONI_IPL_PARAM_OFFSET + 0x0030U) + +#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U) +#define WDTRSTCR_PASSWORD (0xA55A0000U) + +/* struct */ +typedef struct{ + uint8_t uctype; + uint8_t ucversion; + uint16_t ussize; + uint32_t uiattr; + uint32_t psecmonimageinfo_low; + uint32_t psecmonimageinfo_high; + uint32_t psecoptepinfo_low; + uint32_t psecoptepinfo_high; + uint32_t psecoptimageinfo_low; + uint32_t psecoptimageinfo_high; + uint32_t pnonsecepinfo_low; + uint32_t pnonsecepinfo_high; + uint32_t pnonsecimageinfo_low; + uint32_t pnonsecimageinfo_high; +}st_smoni_iplparams_t; + +typedef struct{ + uint8_t uctype; + uint8_t ucversion; + uint16_t ussize; + uint32_t uiattr; + uint32_t ulpc_low; + uint32_t ulpc_high; + uint32_t ulspsr_low; + uint32_t ulspsr_high; + uint32_t ularg0_low; + uint32_t ularg0_high; + uint32_t ularg1_low; + uint32_t ularg1_high; + uint32_t ularg2_low; + uint32_t ularg2_high; + uint32_t ularg3_low; + uint32_t ularg3_high; + uint32_t ularg4_low; + uint32_t ularg4_high; + uint32_t ularg5_low; + uint32_t ularg5_high; + uint32_t ularg6_low; + uint32_t ularg6_high; + uint32_t ularg7_low; + uint32_t ularg7_high; +}st_smoni_entrypointinfo_t; + +/* prototype */ +static uint32_t judge_bootmode(uint32_t lcs); +static void smoni_set_param(uint32_t smoni_entry_point); + +uint32_t loader_main(void) +{ + uint32_t reg; /* store register value */ + uint32_t ret; /* store return value */ + int32_t result; /* store result of ddr_init() */ + uint32_t ca53_load_num; /* number of load for CA53 program */ + uint32_t lcs; /* store LCS state */ + uint32_t remap_addr; /* store PRR logical address */ + uint32_t is_verify; + uint32_t loop; + __attribute__((__unused__)) const char *str; + __attribute__((__unused__)) const char *product_v3h = "V3H"; + __attribute__((__unused__)) const char *unknown = "unknown"; + const char *lcs_name[] = { + [LCS_CM] = "CM", + [LCS_DM] = "DM", + [LCS_SD] = "SD", + [LCS_SE] = "SE", + [LCS_FA] = "FA", + }; + + LOAD_INFO li[MAX_PLACED]; + + +/***************************************************************************** + * Initialize Hardware + *****************************************************************************/ + /* IP initialize */ + ip_init(); + + /* Set the PRR register to the remap spece */ + remap_register(ICU_REMAP_PRR, PRR_DUMMY_REMAP_SIZE, &remap_addr); + + /* Unmask the detection of RWDT overflow */ + reg = mem_read32(RST_WDTRSTCR); + reg &= ~WDTRSTCR_RWDT_RSTMSK; + reg |= WDTRSTCR_PASSWORD; + mem_write32(RST_WDTRSTCR, reg); + +/***************************************************************************** + * Output boot message + *****************************************************************************/ + NOTICE("ICUMXA Loader Rev.%s\n", IPL_VERSION); + + NOTICE("%s\n", build_message); + + /* Get PRR */ + reg = mem_read32(PRR); + switch (reg & PRR_PRODUCT_MASK) + { + case PRR_PRODUCT_V3H: + { + str = product_v3h; + break; + } + default: + { + str = unknown; + break; + } + } + NOTICE("PRR is R-Car %s Ver%d.%d\n", str, + ((reg & PRR_MAJOR_MASK) >> PRR_MAJOR_SHIFT) + PRR_MAJOR_OFFSET, + (reg & PRR_MINOR_MASK)); + + /* Get LCS state */ + reg = ROM_GetLcs(&lcs); + str = unknown; + if (reg == GETLCS_OK) + { + if (NULL != lcs_name[lcs]) + { + str = lcs_name[lcs]; + } + } + NOTICE("LCM state is %s\n", str); + +#if ACC_PROT_ENABLE + NOTICE("Access Protection Enable.\n"); +#endif + +/***************************************************************************** + * Load Certficate from QSPI + *****************************************************************************/ + /* LCS judgement for secure boot */ + is_verify = judge_bootmode(lcs); + + /* Load key certificate */ + load_key_cert(); + + /* Load content certificate */ + ca53_load_num = load_content_cert(); + +/***************************************************************************** + * Load RTOS from QSPI + *****************************************************************************/ + /* Load RTOS from Flash */ + li[RTOS_ID].name = "RTOS"; + li[RTOS_ID].cert_addr = LOGICAL_CONTENT_CERT_ADDR(RTOS_ID); + li[RTOS_ID].src_addr = CONTENT_CERT_DEST_ADDR + + SRC_ADDR_OFFSET(RTOS_ID); + + /* Loading start */ + li[RTOS_ID].boot_addr = load_image(li[RTOS_ID].cert_addr, + li[RTOS_ID].src_addr, li[RTOS_ID].name); + + /* DDR initialize */ + result = InitDram(); + if (INITDRAM_OK != result) + { + ERROR("Failed to DRAM initialize (%d).\n", result); + panic; + } + +#if RCAR_DDR_REG_CHECK + /* initialized reg check */ + result = InitDram_regcheck(); + + if (result != 0) + { + ERROR("Failed to DDRPHY REG check (%d).\n", result); + /* + * User need to implement what IPL should do + * if InitDram_regcheck() is failed. + */ + } + else + { + NOTICE("DDRPHY REG check is OK (%d).\n", result); + } +#endif + + /* QoS configuration */ + qos_init(); + + /* finish loading RTOS */ + load_end(); + + +/***************************************************************************** + * Load CA53 Program#1 from QSPI + *****************************************************************************/ + /* Load CA53 Program#1 from Flash */ + li[CA53_PROGRAM_ID].name = "CA53 Program"; + li[CA53_PROGRAM_ID].cert_addr = LOGICAL_CONTENT_CERT_ADDR(CA53_PROGRAM_ID); + li[CA53_PROGRAM_ID].src_addr = CONTENT_CERT_DEST_ADDR + + SRC_ADDR_OFFSET(CA53_PROGRAM_ID); + + /* Loading start */ + li[CA53_PROGRAM_ID].boot_addr = load_image( + li[CA53_PROGRAM_ID].cert_addr, + li[CA53_PROGRAM_ID].src_addr, li[CA53_PROGRAM_ID].name); + + /* Authenticate of RTOS */ + if (NORMALE_BOOT != is_verify) + { + ret = ROM_SecureBootAPI((uint32_t *)li[RTOS_ID].cert_addr); + if (SBROM_OK != ret) + { + ERROR("%s image Verification Failed!!!(0x%x)\n", + li[RTOS_ID].name, ret); + panic; + } + } + + /* CR7 Boot address set */ + arm_cpu_set_address(RCAR_PWR_TARGET_CR7, li[RTOS_ID].boot_addr); + + /* Access Protection Setting */ + acc_prot_init(); + + /* boot CR7 */ + arm_cpu_on(RCAR_PWR_TARGET_CR7, 0U/* not use */); + + /* finish loading CA53 Program#1 */ + load_end(); + +/***************************************************************************** + * Load CA53 Program#2--#8 from QSPI + *****************************************************************************/ + /* Load CA53 Program#n from Flash */ + for (loop = 1; loop < ca53_load_num; loop++) + { + li[CA53_PROGRAM_ID + loop].name = "CA53 Program"; + li[CA53_PROGRAM_ID + loop].cert_addr = + LOGICAL_CONTENT_CERT_ADDR(CA53_PROGRAM_ID + loop); + li[CA53_PROGRAM_ID + loop].src_addr = CONTENT_CERT_DEST_ADDR + + SRC_ADDR_OFFSET(CA53_PROGRAM_ID + loop); + + /* Loading start */ + li[CA53_PROGRAM_ID + loop].boot_addr = load_image( + li[CA53_PROGRAM_ID + loop].cert_addr, + li[CA53_PROGRAM_ID + loop].src_addr, + li[CA53_PROGRAM_ID + loop].name); + + /* Authenticate of CA53 Program#n-1 */ + if (NORMALE_BOOT != is_verify) + { + ret = ROM_SecureBootAPI( + (uint32_t *)li[CA53_PROGRAM_ID + (loop - 1U)].cert_addr); + if (SBROM_OK != ret) + { + ERROR("%s image Verification Failed!!!(0x%x)\n", + li[CA53_PROGRAM_ID + (loop - 1U)].name, + ret); + panic; + } + } + + /* finish loading CA53 Program#n */ + load_end(); + } + +/***************************************************************************** + * Load Secure Firmware from QSPI + *****************************************************************************/ + /* Load Secure Firmware from Flash */ + li[SECURE_FW_ID].name = "SecureFW"; + li[SECURE_FW_ID].cert_addr = LOGICAL_CONTENT_CERT_ADDR(SECURE_FW_ID); + li[SECURE_FW_ID].src_addr = CONTENT_CERT_DEST_ADDR + + SRC_ADDR_OFFSET(SECURE_FW_ID); + + /* Loading start */ + li[SECURE_FW_ID].boot_addr = load_image(li[SECURE_FW_ID].cert_addr, + li[SECURE_FW_ID].src_addr, li[SECURE_FW_ID].name); + + /* Authenticate of CA53 Program#n */ + if (NORMALE_BOOT != is_verify) + { + ret = ROM_SecureBootAPI( + (uint32_t *)li[CA53_PROGRAM_ID + (ca53_load_num - 1U)].cert_addr); + if (SBROM_OK != ret) + { + ERROR("%s image Verification Failed!!!(0x%x)\n", + li[CA53_PROGRAM_ID + (ca53_load_num - 1U)].name, + ret); + panic; + } + } + + /* Set Secure Monitor parameter */ + smoni_set_param(li[CA53_PROGRAM_ID].boot_addr); + + /* boot CA53 */ + arm_cpu_on(RCAR_PWR_TARGET_CA53, li[CA53_PROGRAM_ID].boot_addr); + + /* finish loading Secure Firmware */ + load_end(); + + /* Authenticate of Secure Firmware */ + if (NORMALE_BOOT != is_verify) + { + ret = ROM_SecureBootAPI((uint32_t *)li[SECURE_FW_ID].cert_addr); + if (SBROM_OK != ret) + { + ERROR("%s image Verification Failed!!!(0x%x)\n", + li[SECURE_FW_ID].name, ret); + panic; + } + } + + /* Release the PRR register on the remap space. */ + remap_unregister(remap_addr); + /* Set Hardware Initial value to IP. */ + ip_release(); + + wdt_restart(); + + return remap_get_remap_addr(li[SECURE_FW_ID].boot_addr); +} +/* End of function loader_main(void) */ + +static uint32_t judge_bootmode(uint32_t lcs) +{ + uint32_t md; + uint32_t is_verify; + + /* LCS Status check */ + if((lcs != LCS_CM) + && (lcs != LCS_DM) + && (lcs != LCS_SD) + && (lcs != LCS_SE) + && (lcs != LCS_FA)) + { + ERROR("LCS state error." + "LCS = 0x%x", lcs); + panic; + } + + md = (mem_read32(RST_MODEMR) & RST_MODEMR_MD5) >> 5U; + if (lcs == LCS_SE) + { + /* LCS=SE => Secure boot */ + is_verify = SECURE_BOOT; + } + else if ((lcs != LCS_SD) && (md == 0U)) + { + /* LCS=CM/DM/FA and MD5=0 => Secure boot */ + is_verify = SECURE_BOOT; + } + else + { + /* LCS=SD or MD5=1 => Normal boot */ + is_verify = NORMALE_BOOT; + } + if (NORMALE_BOOT != is_verify) + { + NOTICE("Secure boot(ICUMX)\n"); + } + else + { + NOTICE("Normal boot(ICUMX)\n"); + } + + return is_verify; +} +/* End of function judge_bootmode(uint32_t lcs) */ + +static void smoni_set_param(uint32_t smoni_entry_point) +{ +#if CA53_PROG1_IS_SMONI + uint32_t mapped_addr; + st_smoni_iplparams_t *smoni_ipl_param; + st_smoni_entrypointinfo_t *smoni_ep_info; + + remap_register(smoni_entry_point, SMONI_REMAP_SIZE, &mapped_addr); + + /* set struct address */ + smoni_ipl_param = (st_smoni_iplparams_t *) + (mapped_addr + SMONI_IPL_PARAM_OFFSET); + smoni_ep_info = (st_smoni_entrypointinfo_t *) + (mapped_addr + SMONI_EP_INFO_OFFSET); + + /* set parameter */ + smoni_ipl_param->uctype = 0x03U; + smoni_ipl_param->ucversion = 0x01U; + smoni_ipl_param->ussize = 0x0030U; + smoni_ipl_param->uiattr = 0x00000000U; + smoni_ipl_param->psecmonimageinfo_low = 0x00000000U; + smoni_ipl_param->psecmonimageinfo_high = 0x00000000U; + smoni_ipl_param->psecoptepinfo_low = 0x00000000U; + smoni_ipl_param->psecoptepinfo_high = 0x00000000U; + smoni_ipl_param->psecoptimageinfo_low = 0x00000000U; + smoni_ipl_param->psecoptimageinfo_high = 0x00000000U; + smoni_ipl_param->pnonsecepinfo_low = + remap_get_phys_addr((uint32_t)smoni_ep_info); + smoni_ipl_param->pnonsecepinfo_high = 0x00000000U; + smoni_ipl_param->pnonsecimageinfo_low = 0x00000000U; + smoni_ipl_param->pnonsecimageinfo_high = 0x00000000U; + + smoni_ep_info->uctype = 0x01U; + smoni_ep_info->ucversion = 0x01U; + smoni_ep_info->ussize = 0x0058U; + smoni_ep_info->uiattr = (uint32_t)CA53_PROG2_ATTR; + smoni_ep_info->ulpc_low = + (uint32_t)((uint64_t)CA53_PROG2_PC & 0xFFFFFFFFU); + smoni_ep_info->ulpc_high = + (uint32_t)(((uint64_t)CA53_PROG2_PC >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ulspsr_low = + (uint32_t)((uint64_t)CA53_PROG2_SPSR & 0xFFFFFFFFU); + smoni_ep_info->ulspsr_high = + (uint32_t)(((uint64_t)CA53_PROG2_SPSR >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg0_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG0 & 0xFFFFFFFFU); + smoni_ep_info->ularg0_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG0 >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg1_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG1 & 0xFFFFFFFFU); + smoni_ep_info->ularg1_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG1 >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg2_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG2 & 0xFFFFFFFFU); + smoni_ep_info->ularg2_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG2 >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg3_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG3 & 0xFFFFFFFFU); + smoni_ep_info->ularg3_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG3 >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg4_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG4 & 0xFFFFFFFFU); + smoni_ep_info->ularg4_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG4 >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg5_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG5 & 0xFFFFFFFFU); + smoni_ep_info->ularg5_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG5 >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg6_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG6 & 0xFFFFFFFFU); + smoni_ep_info->ularg6_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG6 >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg7_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG7 & 0xFFFFFFFFU); + smoni_ep_info->ularg7_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG7 >> 32U) & 0xFFFFFFFFU); + + remap_unregister(mapped_addr); +#endif /* CA53_PROG1_IS_SMONI */ +} +/* End of function smoni_set_param(uint32_t smoni_entry_point) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/protect/acc_prot.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/protect/acc_prot.c new file mode 100644 index 0000000..b58e78c --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/protect/acc_prot.c @@ -0,0 +1,60 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Access Protection function + ******************************************************************************/ +/****************************************************************************** + * @file acc_prot.c + * - Version : 0.01 + * @brief Access protection setting driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include + + + +void acc_prot_init(void) +{ +#if ACC_PROT_ENABLE + /* LifeC setting */ + acc_prot_lifec(); + /* memory protection setting */ + acc_prot_rt_sram(); + acc_prot_system_ram(); + acc_prot_dram(); +#endif +} +/* End of function acc_prot_init(void) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/protect/lifec/acc_prot_lifec.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/protect/lifec/acc_prot_lifec.c new file mode 100644 index 0000000..313e29e --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/protect/lifec/acc_prot_lifec.c @@ -0,0 +1,253 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : LifeC Access Protection function + ******************************************************************************/ + /****************************************************************************** + * @file acc_prot_lifec.c + * - Version : 0.01 + * @brief Access protection setting of LifeC. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include /* for uint32_t */ +#include +#include +#include +#include + +#define REG_BITS_MASK (0x000000FFU) + + +void acc_prot_lifec(void) +{ + uint32_t loop; + const LIFEC_SETTING_TABLE lifec_reg_tbl[] = { + { LIFEC_SEC_GRP0CR2 , 0x00000000U }, + { LIFEC_SEC_GRP1CR2 , 0x00000000U }, + { LIFEC_SAFE_GRP0CR2 , 0x00000000U }, + { LIFEC_SAFE_GRP1CR2 , 0x00000000U }, + + { LIFEC_SEC_GRP0CR0 , 0x00000000U }, + { LIFEC_SEC_GRP1CR0 , 0x00000000U }, + { LIFEC_SAFE_GRP0CR0 , 0x00000000U }, + { LIFEC_SAFE_GRP1CR0 , 0x00000000U }, + + { LIFEC_SEC_GRP0CR1 , 0x00000000U }, + { LIFEC_SEC_GRP1CR1 , 0x00000000U }, + { LIFEC_SAFE_GRP0CR1 , 0x00000000U }, + { LIFEC_SAFE_GRP1CR1 , 0x00000000U }, + + { LIFEC_SEC_GRP0CR3 , 0x00000000U }, + { LIFEC_SEC_GRP1CR3 , 0x00000000U }, + { LIFEC_SAFE_GRP0CR3 , 0x00000000U }, + { LIFEC_SAFE_GRP1CR3 , 0x00000000U }, + + { LIFEC_SEC_SEL0 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND0 , 0x00000000U }, + { LIFEC_SEC_GRP1COND0 , 0x00000000U }, + { LIFEC_SEC_READONLY0 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND0 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND0 , 0x00000000U }, + { LIFEC_SAFE_READONLY0 , 0x00000000U }, + + { LIFEC_SEC_SEL1 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND1 , 0x00000000U }, + { LIFEC_SEC_GRP1COND1 , 0x00000000U }, + { LIFEC_SEC_READONLY1 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND1 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND1 , 0x00000000U }, + { LIFEC_SAFE_READONLY1 , 0x00000000U }, + + { LIFEC_SEC_SEL2 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND2 , 0x00000000U }, + { LIFEC_SEC_GRP1COND2 , 0x00000000U }, + { LIFEC_SEC_READONLY2 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND2 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND2 , 0x00000000U }, + { LIFEC_SAFE_READONLY2 , 0x00000000U }, + + { LIFEC_SEC_SEL3 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND3 , 0x00000000U }, + { LIFEC_SEC_GRP1COND3 , 0x00000000U }, + { LIFEC_SEC_READONLY3 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND3 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND3 , 0x00000000U }, + { LIFEC_SAFE_READONLY3 , 0x00000000U }, + + { LIFEC_SEC_SEL4 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND4 , 0x00000000U }, + { LIFEC_SEC_GRP1COND4 , 0x00000000U }, + { LIFEC_SEC_READONLY4 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND4 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND4 , 0x00000000U }, + { LIFEC_SAFE_READONLY4 , 0x00000000U }, + + { LIFEC_SEC_SEL5 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND5 , 0x00000000U }, + { LIFEC_SEC_GRP1COND5 , 0x00000000U }, + { LIFEC_SEC_READONLY5 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND5 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND5 , 0x00000000U }, + { LIFEC_SAFE_READONLY5 , 0x00000000U }, + + { LIFEC_SEC_SEL6 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND6 , 0x00000000U }, + { LIFEC_SEC_GRP1COND6 , 0x00000000U }, + { LIFEC_SEC_READONLY6 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND6 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND6 , 0x00000000U }, + { LIFEC_SAFE_READONLY6 , 0x00000000U }, + + { LIFEC_SEC_SEL7 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND7 , 0x00000000U }, + { LIFEC_SEC_GRP1COND7 , 0x00000000U }, + { LIFEC_SEC_READONLY7 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND7 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND7 , 0x00000000U }, + { LIFEC_SAFE_READONLY7 , 0x00000000U }, + + { LIFEC_SEC_SEL8 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND8 , 0x00000000U }, + { LIFEC_SEC_GRP1COND8 , 0x00000000U }, + { LIFEC_SEC_READONLY8 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND8 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND8 , 0x00000000U }, + { LIFEC_SAFE_READONLY8 , 0x00000000U }, + + { LIFEC_SEC_SEL9 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND9 , 0x00000000U }, + { LIFEC_SEC_GRP1COND9 , 0x00000000U }, + { LIFEC_SEC_READONLY9 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND9 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND9 , 0x00000000U }, + { LIFEC_SAFE_READONLY9 , 0x00000000U }, + + { LIFEC_SEC_SEL10 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND10 , 0x00000000U }, + { LIFEC_SEC_GRP1COND10 , 0x00000000U }, + { LIFEC_SEC_READONLY10 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND10 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND10 , 0x00000000U }, + { LIFEC_SAFE_READONLY10 , 0x00000000U }, + + { LIFEC_SEC_SEL11 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND11 , 0x00000000U }, + { LIFEC_SEC_GRP1COND11 , 0x00000000U }, + { LIFEC_SEC_READONLY11 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND11 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND11 , 0x00000000U }, + { LIFEC_SAFE_READONLY11 , 0x00000000U }, + + { LIFEC_SEC_SEL12 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND12 , 0x00000000U }, + { LIFEC_SEC_GRP1COND12 , 0x00000000U }, + { LIFEC_SEC_READONLY12 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND12 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND12 , 0x00000000U }, + { LIFEC_SAFE_READONLY12 , 0x00000000U }, + + { LIFEC_SEC_SEL13 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND13 , 0x00000000U }, + { LIFEC_SEC_GRP1COND13 , 0x00000000U }, + { LIFEC_SEC_READONLY13 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND13 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND13 , 0x00000000U }, + { LIFEC_SAFE_READONLY13 , 0x00000000U }, + + { LIFEC_SEC_SEL14 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND14 , 0x00000000U }, + { LIFEC_SEC_GRP1COND14 , 0x00000000U }, + { LIFEC_SEC_READONLY14 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND14 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND14 , 0x00000000U }, + { LIFEC_SAFE_READONLY14 , 0x00000000U }, + + { LIFEC_SEC_SEL15 , 0xFFFFFFFFU }, + { LIFEC_SEC_GRP0COND15 , 0x00000000U }, + { LIFEC_SEC_GRP1COND15 , 0x00000000U }, + { LIFEC_SEC_READONLY15 , 0x00000000U }, + { LIFEC_SAFE_GRP0COND15 , 0x00000000U }, + { LIFEC_SAFE_GRP1COND15 , 0x00000000U }, + { LIFEC_SAFE_READONLY15 , 0x00000000U }, + }; + + for (loop = 0U; + loop < (sizeof(lifec_reg_tbl) / sizeof(lifec_reg_tbl[0])); + loop++) + { + mem_write32(lifec_reg_tbl[loop].address, lifec_reg_tbl[loop].value); + } + + (void)mem_read32(LIFEC_SEC_SRC); /* dummy read */ +} +/* End of function acc_prot_lifec(void) */ + +void lifec_set_master_grp(uint32_t target, uint32_t sec_grp, uint32_t safe_grp) +{ + uint32_t reg_off; + uint32_t reg_bits; + + const uint32_t sec_master_reg[][2] = + { + [0] = {LIFEC_SEC_GRP0CR0, LIFEC_SEC_GRP1CR0}, + [1] = {LIFEC_SEC_GRP0CR1, LIFEC_SEC_GRP1CR1}, + [2] = {LIFEC_SEC_GRP0CR2, LIFEC_SEC_GRP1CR2}, + [3] = {LIFEC_SEC_GRP0CR3, LIFEC_SEC_GRP1CR3}, + }; + + const uint32_t safe_master_reg[][2] = + { + [0] = {LIFEC_SAFE_GRP0CR0, LIFEC_SAFE_GRP1CR0}, + [1] = {LIFEC_SAFE_GRP0CR1, LIFEC_SAFE_GRP1CR1}, + [2] = {LIFEC_SAFE_GRP0CR2, LIFEC_SAFE_GRP1CR2}, + [3] = {LIFEC_SAFE_GRP0CR3, LIFEC_SAFE_GRP1CR3}, + }; + + /* Calculate the setting target */ + reg_off = target >> 16U; + reg_bits = target & REG_BITS_MASK; + + /* Set security access group */ + mem_bitclrset32(sec_master_reg[reg_off][0], ((uint32_t)1U << reg_bits), + ((uint32_t)(sec_grp & 0x1U) << reg_bits)); + mem_bitclrset32(sec_master_reg[reg_off][1], ((uint32_t)1U << reg_bits), + ((uint32_t)(sec_grp & 0x2U) << (reg_bits - 1U))); + + /* Set safety access group */ + mem_bitclrset32(safe_master_reg[reg_off][0], ((uint32_t)1U << reg_bits), + ((uint32_t)(safe_grp & 0x1U) << reg_bits)); + mem_bitclrset32(safe_master_reg[reg_off][1], ((uint32_t)1U << reg_bits), + ((uint32_t)(safe_grp & 0x2U) << (reg_bits - 1U))); +} +/* End of function lifec_set_master_grp(uint32_t target, uint32_t sec_grp, uint32_t safe_grp) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/protect/memory/acc_prot_memory.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/protect/memory/acc_prot_memory.c new file mode 100644 index 0000000..16ddafe --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/protect/memory/acc_prot_memory.c @@ -0,0 +1,228 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : memory protection function + ******************************************************************************/ + /****************************************************************************** + * @file acc_prot_memory.c + * - Version : 0.01 + * @brief Access protection setting of memory. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +#define RT_SRAM_ADDR_OFFSET_MASK (0x000FF000U) +#define SYSTEM_RAM_ADDR_MASK (0xFFFFF000U) +#define SDRAM_ADDR_MASK (0x0000002FFFFF0000UL) + +#define READ_SET_VAL_MASK ((uint8_t)(0xF0U)) +#define WRITE_SET_VAL_MASK ((uint8_t)(0x0FU)) + +void acc_prot_rt_sram(void) +{ + uint32_t loop; + uint32_t mapped_addr; + uint32_t reg; + + RT_SRAM_PROT rt_sram_prot_data[16] = { + /* | | register | access | */ + /* | address | sec safety | security safety | */ + [0] = {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [1] = {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [2] = {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [3] = {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [4] = {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [5] = {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [6] = {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [7] = {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [8] = {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [9] = {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [10]= {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [11]= {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [12]= {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [13]= {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [14]= {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [15]= {RT_SRAM_ADDR_END,{W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + }; + + mapped_addr = remap_get_remap_addr(SECDIVnD_BASE); + + INFO("RT-SRAM Protection setting...\n"); + + /* Set division address register. */ + for (loop = 0U; loop < 15U; ++loop) + { + reg = ((uint32_t)(rt_sram_prot_data[loop].prot.reg_sec) << 24U); + reg |= ((uint32_t)(rt_sram_prot_data[loop].prot.reg_saf) << 28U); + reg |= ((uint32_t)(rt_sram_prot_data[loop + 1U].addr_off + & RT_SRAM_ADDR_END) >> 12U); + mem_write32(SECDIVnD(mapped_addr, loop), reg); + } + + /* Set division area protection register. */ + for (loop = 0U; loop < 16U; ++loop) + { + reg = ((uint32_t)(rt_sram_prot_data[loop].prot.reg_sec) << 24U); + reg |= ((uint32_t)(rt_sram_prot_data[loop].prot.reg_saf) << 28U); + reg |= ((uint32_t)(rt_sram_prot_data[loop].prot.acc_sec + & (uint32_t)(READ_SET_VAL_MASK)) << 4U); /* Secure read */ + reg |= ((uint32_t)(rt_sram_prot_data[loop].prot.acc_sec + & (uint32_t)(WRITE_SET_VAL_MASK))); /* Secure write */ + reg |= ((uint32_t)(rt_sram_prot_data[loop].prot.acc_saf + & (uint32_t)(READ_SET_VAL_MASK)) << 8U); /* Safety read */ + reg |= ((uint32_t)(rt_sram_prot_data[loop].prot.acc_saf + & (uint32_t)(WRITE_SET_VAL_MASK)) << 4U); /* Safety write */ + mem_write32(SECCTRnD(mapped_addr, loop), reg); + } +} +/* End of function acc_prot_rt_sram(void) */ + + +void acc_prot_system_ram(void) +{ + uint32_t loop; + uint32_t reg; + + SYSTEM_RAM_PROT system_ram_prot_data[16] = { + /* | | register | access | */ + /* | address | sec safety | security safety | */ + [0] = {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [1] = {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [2] = {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [3] = {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [4] = {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [5] = {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [6] = {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [7] = {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [8] = {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [9] = {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [10]= {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [11]= {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [12]= {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [13]= {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [14]= {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [15]= {SYSTEM_RAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + }; + + INFO("System RAM Protection setting...\n"); + + /* Set division address register. */ + for (loop = 0U; loop < 15U; ++loop) + { + reg = ((uint32_t)(system_ram_prot_data[loop].prot.reg_sec) << 24U); + reg |= ((uint32_t)(system_ram_prot_data[loop].prot.reg_saf) << 28U); + reg |= ((uint32_t)(system_ram_prot_data[loop + 1U].addr + & SYSTEM_RAM_ADDR_END) >> 12U); + mem_write32(SPTDIVCR(loop), reg); + } + + /* Set division area protection register. */ + for (loop = 0U; loop < 16U; ++loop) + { + reg = ((uint32_t)(system_ram_prot_data[loop].prot.reg_sec) << 24U); + reg |= ((uint32_t)(system_ram_prot_data[loop].prot.reg_saf) << 28U); + reg |= ((uint32_t)(system_ram_prot_data[loop].prot.acc_sec + & (uint32_t)(READ_SET_VAL_MASK)) << 4U); /* Secure read */ + reg |= ((uint32_t)(system_ram_prot_data[loop].prot.acc_sec + & (uint32_t)(WRITE_SET_VAL_MASK))); /* Secure write */ + reg |= ((uint32_t)(system_ram_prot_data[loop].prot.acc_saf + & (uint32_t)(READ_SET_VAL_MASK)) << 8U); /* Safety read */ + reg |= ((uint32_t)(system_ram_prot_data[loop].prot.acc_saf + & (uint32_t)(WRITE_SET_VAL_MASK)) << 4U); /* Safety write */ + mem_write32(SPTCR(loop), reg); + } +} +/* End of function acc_prot_system_ram(void) */ + + +void acc_prot_dram(void) +{ + uint32_t loop; + uint32_t reg; + + DRAM_PROT dram_prot_data[16] = { + /* | | register | access | */ + /* | address | sec safety | security safety | */ + [0] = {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [1] = {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [2] = {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [3] = {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [4] = {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [5] = {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [6] = {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [7] = {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [8] = {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [9] = {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [10]= {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [11]= {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [12]= {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [13]= {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [14]= {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + [15]= {DRAM_ADDR_END, {W_YYYY,W_YYYY, R_YYYY | W_YYYY, R_YYYY | W_YYYY}}, + }; + + INFO("DRAM Protection setting...\n"); + + /* Set division address register. */ + for (loop = 0U; loop < 15U; ++loop) + { + reg = ((uint32_t)(dram_prot_data[loop].prot.reg_sec) << 24U); + reg |= ((uint32_t)(dram_prot_data[loop].prot.reg_saf) << 28U); + reg |= (uint32_t)((dram_prot_data[loop + 1U].addr & DRAM_ADDR_END) >> 16U); + mem_write32(DPTDIVCR(loop), reg); + } + + /* Set division area protection register. */ + for (loop = 0U; loop < 16U; ++loop) + { + reg = ((uint32_t)(dram_prot_data[loop].prot.reg_sec) << 24U); + reg |= ((uint32_t)(dram_prot_data[loop].prot.reg_saf) << 28U); + reg |= ((uint32_t)(dram_prot_data[loop].prot.acc_sec + & (uint32_t)(READ_SET_VAL_MASK)) << 4U); /* Secure read */ + reg |= ((uint32_t)(dram_prot_data[loop].prot.acc_sec + & (uint32_t)(WRITE_SET_VAL_MASK))); /* Secure write */ + reg |= ((uint32_t)(dram_prot_data[loop].prot.acc_saf + & (uint32_t)(READ_SET_VAL_MASK)) << 8U); /* Safety read */ + reg |= ((uint32_t)(dram_prot_data[loop].prot.acc_saf + & (uint32_t)(WRITE_SET_VAL_MASK)) << 4U); /* Safety write */ + mem_write32(DPTCR(loop), reg); + } +} +/* End of function acc_prot_dram(void) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/remap/remap.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/remap/remap.c new file mode 100644 index 0000000..e02c12e --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/remap/remap.c @@ -0,0 +1,284 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : remap driver + ******************************************************************************/ +/****************************************************************************** + * @file acc_prot.c + * - Version : 0.01 + * @brief 1. Setting of SIC REMAP AREA. + * 2. Release of SIC REMAP AREA. + * 3. Calculation of logical address. + * 4. Calculation of physical address. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include + +/* Range of SICREMAP2M register */ +#define REMAP_REG_MAX (16U) + +#define REMAP_2M_BITS (21U) +#define REMAP_2M_SIZE ((uint32_t)1U << REMAP_2M_BITS) +#define REMAP_2M_MASK (REMAP_2M_SIZE - 1U) +#define REMAP_TBL_MAX (sizeof(s_remap_tbl)/sizeof(s_remap_tbl[0])) +#define REMAP_UNUSED (uint8_t)(0xFFU) + +typedef struct { + uint8_t number; + uint32_t address; +}st_remap_address_table_t; + +/* Remap management table */ +static st_remap_address_table_t s_remap_tbl[] = { + [0] = {REMAP_UNUSED, 0x00000000U}, + [1] = {REMAP_UNUSED, 0x00000000U}, + [2] = {REMAP_UNUSED, 0x00000000U}, + [3] = {REMAP_UNUSED, 0x00000000U}, + [4] = {REMAP_UNUSED, 0x00000000U}, + [5] = {REMAP_UNUSED, 0x00000000U}, + [6] = {6, 0xE7200000U}, + [7] = {7, 0xE6400000U}, + [8] = {8, 0xFFC10000U}, + [9] = {9, 0xE6E00000U}, + [10] = {10, 0xFFC10000U}, + [11] = {11, 0xEE200000U}, + [12] = {12, 0xE6200000U}, + [13] = {13, 0xE6000000U}, + [14] = {14, 0xE6600000U}, + [15] = {15, 0xEB200000U}, +}; + +static void remap_reg_write(uint32_t num, uint32_t value); + +static void remap_reg_write(uint32_t num, uint32_t value) +{ + /* Specific write Procedure for Write-Protected Register. */ + do + { + mem_write32(ICUMX_PROT0PCMD, PROTCMD_START); + mem_write32(SICREMAP2M(num), value); + mem_write32(SICREMAP2M(num), ~value); + mem_write32(SICREMAP2M(num), value); + } while (mem_read32(ICUMX_PROT0PS) == PROTS0ERR); +} +/* End of function remap_reg_write(uint32_t num, uint32_t value) */ + +void remap_register(uint32_t addr, uint32_t size, uint32_t *remap_addr) +{ + uint32_t loop; + uint32_t loop2; + uint32_t map_num; + uint32_t set_addr; + + /* size parameter check */ + if(size == 0U) + { + ERROR("Remap address size error.\n"); + panic; + } + + /* Calculate the number to be registered in the remap space */ + map_num = (addr & REMAP_2M_MASK) + size; + if((map_num % REMAP_2M_SIZE) == 0U) + { + map_num = (map_num / REMAP_2M_SIZE); + } + else + { + map_num = (map_num / REMAP_2M_SIZE) + 1U; + } + + /* Check unused area in order from the top of + the remap management table. */ + for (loop = 0U; loop < REMAP_TBL_MAX; ++loop) + { + if (REMAP_UNUSED == s_remap_tbl[loop].number) + { + /* Judge whether it is possible to secure a necessary + size for remapping in the unused area. */ + for (loop2 = loop; loop2 < (map_num + loop); ++loop2) + { + if (REMAP_UNUSED != s_remap_tbl[loop2].number) + { + break; + } + } + if ((map_num + loop) <= loop2) + { + break; + } + } + } + + /* When necessary area can not be secured */ + if (REMAP_TBL_MAX <= loop) + { + ERROR("There is no space in the logical address area.\n"); + panic; + } + + __asm__ __volatile__ ("SYNCM"); + + /* Set remap area */ + set_addr = addr & ~REMAP_2M_MASK; + for (loop2 = loop; loop2 < (map_num + loop); ++loop2) + { + /* Update the table managing the remap space */ + s_remap_tbl[loop2].address = set_addr; + s_remap_tbl[loop2].number = (uint8_t)loop; + /* Set SICREMAP register */ + remap_reg_write(loop2, set_addr); + set_addr += REMAP_2M_SIZE; + INFO("s_remap_tbl[%d].number = 0x%x\n",loop,s_remap_tbl[loop2].number); + INFO("s_remap_tbl[%d].address = 0x%x\n",loop,s_remap_tbl[loop2].address); + } + + __asm__ __volatile__ ("SYNCM"); + + /* Calculating the logical address of the + address received as an argument */ + *remap_addr = ICU_REMAP_CALC(loop); + *remap_addr += addr & REMAP_2M_MASK; +} +/* End of function remap_register(uint32_t addr, uint32_t size, uint32_t *remap_addr) */ + +void remap_unregister(uint32_t remap_addr) +{ + uint32_t loop; + uint32_t loop2; + uint32_t remove_num; + + /* Is the remap space where the address of the argument is used? */ + for (loop = 0U; loop < REMAP_TBL_MAX; ++loop) + { + INFO("s_remap_tbl[%d].number = 0x%x\n",loop,s_remap_tbl[loop].number); + if ((REMAP_UNUSED != s_remap_tbl[loop].number) + && ((ICU_REMAP_CALC(loop) <= remap_addr) + && (remap_addr < ICU_REMAP_CALC(loop + 1U)))) + { + break; + } + } + + /* When an area to release can not be found */ + if (REMAP_TBL_MAX <= loop) + { + ERROR("Not registered in the logical address.\n" + "remap address = 0x%x\n",remap_addr); + panic; + } + __asm__ __volatile__ ("SYNCM"); + + /* release remap area */ + remove_num = s_remap_tbl[loop].number; + for (loop2 = remove_num; loop2 < REMAP_TBL_MAX; ++loop2) + { + if (s_remap_tbl[loop2].number != remove_num) + { + break; + } + /* Update the table managing the remap space */ + s_remap_tbl[loop2].address = 0U; + s_remap_tbl[loop2].number = REMAP_UNUSED; + /* Release SICREMAP register */ + remap_reg_write(loop2, ICU_REMAP_CALC(loop2)); + } + + __asm__ __volatile__ ("SYNCM"); +} +/* End of function remap_unregister(uint32_t remap_addr) */ + +uint32_t remap_get_phys_addr(uint32_t remap_addr) +{ + uint32_t phys_addr; + uint32_t reg; + + /* It checks whether the argument is within the range + of the logical address. */ + if ((ICU_REMAP0 > remap_addr) + || (ICU_REMAP_CALC(REMAP_REG_MAX) <= remap_addr)) + { + ERROR("Address convert error.\n" + "source address = 0x%x\n",remap_addr); + panic; + } + + /* Calculate the physical address of the argument */ + phys_addr = remap_addr - ICU_REMAP0; + phys_addr >>= REMAP_2M_BITS; + reg = SICREMAP2M(phys_addr); + reg = mem_read32(reg); + phys_addr = reg + (remap_addr & REMAP_2M_MASK); + + return phys_addr; +} +/* End of function remap_get_phys_addr(uint32_t remap_addr) */ + +uint32_t remap_get_remap_addr(uint32_t phys_addr) +{ + uint32_t remap_addr; + uint32_t reg; + uint32_t loop; + + /* It checks whether the argument is within the range + of the physical address registered in SICREMAP. */ + for (loop = 0U; loop < REMAP_REG_MAX; loop++) + { + reg = mem_read32(SICREMAP2M(loop)); + if ((reg <= phys_addr) + && (phys_addr <= (reg + REMAP_2M_MASK))) + { + break; + } + } + + /* argument value is not used in the remap area. */ + if (REMAP_REG_MAX <= loop) + { + ERROR("Address convert error.\n" + "source address = 0x%x\n",phys_addr); + panic; + } + + /* Calculate the logical address of the argument */ + remap_addr = ICU_REMAP_CALC(loop); + remap_addr += phys_addr - reg; + + return remap_addr; +} +/* End of function remap_get_remap_addr(uint32_t phys_addr) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/rom_api/rom_api.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/rom_api/rom_api.c new file mode 100644 index 0000000..ce17552 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/rom_api/rom_api.c @@ -0,0 +1,75 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : boot ROM API + ******************************************************************************/ +/****************************************************************************** + * @file rom_api.c + * - Version : 0.01 + * @brief 1.Call ROM_SecureBootAPI. + * 2.Call ROM_GetLcsAPI. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + + + +uint32_t ROM_SecureBootAPI(uint32_t *pContentCert) +{ + /* Secure Boot API address */ + static const uintptr_t s_rom_secureboot_api_addr = ROM_SECUREBOOT_API_V3H; + ROM_SECURE_BOOT_API func; + + func = (ROM_SECURE_BOOT_API)s_rom_secureboot_api_addr; + + return func((uint32_t *)LOGICAL_BOOT_KEY_ADDR, pContentCert, (void *)0U); +} +/* End of function ROM_SecureBootAPI(uint32_t *pContentCert) */ + +uint32_t ROM_GetLcs(uint32_t *pLcs) +{ + /* Get LCS stete API address */ + static const uintptr_t s_rom_getlcs_addr = ROM_GET_LCS_V3H; + ROM_GETLCS_API func; + + func = (ROM_GETLCS_API)s_rom_getlcs_addr; + + return func(pLcs); +} +/* End of function ROM_GetLcs(uint32_t *pLcs) */ diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/rom_api/rom_api_wrap.S b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/rom_api/rom_api_wrap.S new file mode 100644 index 0000000..242a547 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/rom_api/rom_api_wrap.S @@ -0,0 +1,49 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : boot ROM call wapper + ******************************************************************************/ + + .global _rom_api_wrap + +_rom_api_wrap: + +/* save r20 register */ + add -8, sp + st.w lp, 4[sp] + st.w r20, 0[sp] + + jarl [r9], lp + +/* restore r20 register */ + ld.w 4[sp], lp + ld.w 0[sp], r20 + add 8, sp + + jmp [lp] diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/tools/dummy_create/sa0.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/tools/dummy_create/sa0.c new file mode 100644 index 0000000..97b15e8 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/tools/dummy_create/sa0.c @@ -0,0 +1,61 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 0(0x00000) + ******************************************************************************/ + +#include + +#define BOOT_PARAM (0x00000101U) +#define CERT_MAGIC (0xE291F358U) +#define LOADER_ADDR (0xEB2D8000U) +#define LOADER_SIZE (128U * 1024U / 4U) + +/* SA0 */ +/* boot parameter */ +__attribute__ ((section(".sa0_boot"))) const uint32_t boot[] = { + [0] = BOOT_PARAM, + [1] = 0xFFFFFFFFU, +}; + + +/* A-side contents Key (0x3000) */ +__attribute__ ((section(".sa0_content_a"))) const uint32_t content_a[872 / 4] = { + [0x000 / 4] = CERT_MAGIC, /* magic */ + [0x00C / 4] = 0x00000000U, /* magic */ + [0x154 / 4] = LOADER_ADDR, /* address */ + [0x264 / 4] = LOADER_SIZE, /* size */ +}; +/* B-side contents Key (0x4000)*/ +__attribute__ ((section(".sa0_content_b"))) const uint32_t content_b[872 / 4] = { + [0x000 / 4] = CERT_MAGIC, /* magic */ + [0x00C / 4] = 0x00000000U, /* magic */ + [0x154 / 4] = LOADER_ADDR, /* address */ + [0x264 / 4] = LOADER_SIZE, /* size */ +}; diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/tools/dummy_create/sa0.ld b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/tools/dummy_create/sa0.ld new file mode 100644 index 0000000..4e57165 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/tools/dummy_create/sa0.ld @@ -0,0 +1,60 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 0(0x00000) linker directive + ******************************************************************************/ +DEFAULTS { + dummy_addr = 0xEB200000 + dummy_size = 1M + +} +MEMORY +{ + dram : ORIGIN = dummy_addr, LENGTH = dummy_size +} +SECTIONS +{ +// +// Dummy Certificate +// + .sa0 ALIGN(16) : { + _start=0; + *(.sa0_boot) _boot=0; + .=0x3000; + *(.sa0_content_a) _content_a=.; + .=0x4000; + *(.sa0_content_b) _content_b=.; + } > dram + + .sdata : > . + .tdata : > . + .rosdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +} \ No newline at end of file diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/tools/dummy_create/sa6.c b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/tools/dummy_create/sa6.c new file mode 100644 index 0000000..a528a91 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/tools/dummy_create/sa6.c @@ -0,0 +1,185 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 6(0x180000) + ******************************************************************************/ + +#include + +/* CA53 program load num */ +#define CA53_IMAGE_NUM (0x00000002U) +/* Source address on flash for Secure FW */ +#define SECURE_FW_SRC_ADDRESS (0x000C0000U) +/* Reserved */ +#define SECURE_FW_PARTITION (0x00000000U) +/* Source address on flash for RTOS */ +#define RTOS_SRC_ADDRESS (0x001C0000U) +/* Reserved */ +#define RTOS_PARTITION (0x00000000U) +/* Source address on flash for CA53 program(1) */ +#define CA53_PROG_01_SRC_ADDRESS (0x002C0000U) +/* Reserved */ +#define CA53_PROG_01_PARTITION (0x00000000U) +/* ----------- customized ----------- */ +/* Reserved */ +#define CA53_PROG_02_SRC_ADDRESS (0x00840000U) +#define CA53_PROG_02_PARTITION (0x00000000U) +/* Reserved */ +#define CA53_PROG_03_SRC_ADDRESS (0x00000000U) +#define CA53_PROG_03_PARTITION (0x00000000U) +/* Reserved */ +#define CA53_PROG_04_SRC_ADDRESS (0x00000000U) +#define CA53_PROG_04_PARTITION (0x00000000U) +/* Reserved */ +#define CA53_PROG_05_SRC_ADDRESS (0x00000000U) +#define CA53_PROG_05_PARTITION (0x00000000U) +/* Reserved */ +#define CA53_PROG_06_SRC_ADDRESS (0x00000000U) +#define CA53_PROG_06_PARTITION (0x00000000U) +/* Reserved */ +#define CA53_PROG_07_SRC_ADDRESS (0x00000000U) +#define CA53_PROG_07_PARTITION (0x00000000U) +/* Reserved */ +#define CA53_PROG_08_SRC_ADDRESS (0x00000000U) +#define CA53_PROG_08_PARTITION (0x00000000U) +/* ----------- customized ----------- */ + + +/* Destination address for Secure FW */ +#define SECURE_FW_ADDRESS (0xEB2B4000U) +#define SECURE_FW_ADDRESSH (0x00000000U) +/* Destination size for Secure FW */ +#define SECURE_FW_DST_SIZE (0x00011200U) +/* Destination address for RTOS */ +#define RTOS_ADDRESS (0xEB200000U) +#define RTOS_ADDRESSH (0x00000000U) +/* Destination size for RTOS */ +#define RTOS_DST_SIZE (0x0002D000U) +/* Destination address for CA53 program(1) */ +#define CA53_PROG_01_ADDRESS (0x46400000U) +#define CA53_PROG_01_ADDRESSH (0x00000000U) +/* Destination size for CA53 program(1) */ +#define CA53_PROG_01_SIZE (0x00020000U) /* 512KiB/4 */ +/* ----------- customized ----------- */ +/* Reserved */ +#define CA53_PROG_02_ADDRESS (0x50000000U) +#define CA53_PROG_02_ADDRESSH (0x00000000U) +#define CA53_PROG_02_SIZE (0x00040000U) /* 1MiB/4 */ +/* Reserved */ +#define CA53_PROG_03_ADDRESS (0x00000000U) +#define CA53_PROG_03_ADDRESSH (0x00000000U) +#define CA53_PROG_03_SIZE (0x00000000U) +/* Reserved */ +#define CA53_PROG_04_ADDRESS (0x00000000U) +#define CA53_PROG_04_ADDRESSH (0x00000000U) +#define CA53_PROG_04_SIZE (0x00000000U) +/* Reserved */ +#define CA53_PROG_05_ADDRESS (0x00000000U) +#define CA53_PROG_05_ADDRESSH (0x00000000U) +#define CA53_PROG_05_SIZE (0x00000000U) +/* Reserved */ +#define CA53_PROG_06_ADDRESS (0x00000000U) +#define CA53_PROG_06_ADDRESSH (0x00000000U) +#define CA53_PROG_06_SIZE (0x00000000U) +/* Reserved */ +#define CA53_PROG_07_ADDRESS (0x00000000U) +#define CA53_PROG_07_ADDRESSH (0x00000000U) +#define CA53_PROG_07_SIZE (0x00000000U) +/* Reserved */ +#define CA53_PROG_08_ADDRESS (0x00000000U) +#define CA53_PROG_08_ADDRESSH (0x00000000U) +#define CA53_PROG_08_SIZE (0x00000000U) +/* ----------- customized ----------- */ + +/* sa6 */ +__attribute__ ((section (".sa6_top"))) const uint32_t top_cert[1024 / 4] = { + [0x0000 / 4] = CA53_IMAGE_NUM, + [0x0008 / 4] = SECURE_FW_SRC_ADDRESS, + [0x0010 / 4] = SECURE_FW_PARTITION, + [0x0018 / 4] = RTOS_SRC_ADDRESS, + [0x0020 / 4] = RTOS_PARTITION, + [0x0028 / 4] = CA53_PROG_01_SRC_ADDRESS, + [0x0030 / 4] = CA53_PROG_01_PARTITION, + [0x0038 / 4] = CA53_PROG_02_SRC_ADDRESS, + [0x0040 / 4] = CA53_PROG_02_PARTITION, + [0x0048 / 4] = CA53_PROG_03_SRC_ADDRESS, + [0x0050 / 4] = CA53_PROG_03_PARTITION, + [0x0058 / 4] = CA53_PROG_04_SRC_ADDRESS, + [0x0060 / 4] = CA53_PROG_04_PARTITION, + [0x0068 / 4] = CA53_PROG_05_SRC_ADDRESS, + [0x0070 / 4] = CA53_PROG_05_PARTITION, + [0x0078 / 4] = CA53_PROG_06_SRC_ADDRESS, + [0x0080 / 4] = CA53_PROG_06_PARTITION, + [0x0088 / 4] = CA53_PROG_07_SRC_ADDRESS, + [0x0090 / 4] = CA53_PROG_07_PARTITION, + [0x0098 / 4] = CA53_PROG_08_SRC_ADDRESS, + [0x00A0 / 4] = CA53_PROG_08_PARTITION, +}; +__attribute__ ((section (".sa6_firm"))) const uint32_t firm_cert[2048 / 4] = { + [0x0154 / 4] = SECURE_FW_ADDRESS, + [0x0264 / 4] = SECURE_FW_DST_SIZE, +}; +__attribute__ ((section (".sa6_rtos"))) const uint32_t rtos_cert[2048 / 4] = { + [0x0154 / 4] = RTOS_ADDRESS, + [0x0264 / 4] = RTOS_DST_SIZE, +}; +__attribute__ ((section (".sa6_ca53_01"))) const uint32_t ca53_01_cert[2048 / 4] = { + [0x0154 / 4] = CA53_PROG_01_ADDRESS, + [0x0264 / 4] = CA53_PROG_01_SIZE, +}; + +__attribute__ ((section (".sa6_ca53_02"))) const uint32_t ca53_02_cert[2048 / 4] = { + [0x0154 / 4] = CA53_PROG_02_ADDRESS, + [0x0264 / 4] = CA53_PROG_02_SIZE, +}; +__attribute__ ((section (".sa6_ca53_03"))) const uint32_t ca53_03_cert[2048 / 4] = { + [0x0154 / 4] = CA53_PROG_03_ADDRESS, + [0x0264 / 4] = CA53_PROG_03_SIZE, +}; +__attribute__ ((section (".sa6_ca53_04"))) const uint32_t ca53_04_cert[2048 / 4] = { + [0x0154 / 4] = CA53_PROG_04_ADDRESS, + [0x0264 / 4] = CA53_PROG_04_SIZE, +}; +__attribute__ ((section (".sa6_ca53_05"))) const uint32_t ca53_05_cert[2048 / 4] = { + [0x0154 / 4] = CA53_PROG_05_ADDRESS, + [0x0264 / 4] = CA53_PROG_05_SIZE, +}; +__attribute__ ((section (".sa6_ca53_06"))) const uint32_t ca53_06_cert[2048 / 4] = { + [0x0154 / 4] = CA53_PROG_06_ADDRESS, + [0x0264 / 4] = CA53_PROG_06_SIZE, +}; +__attribute__ ((section (".sa6_ca53_07"))) const uint32_t ca53_07_cert[2048 / 4] = { + [0x0154 / 4] = CA53_PROG_07_ADDRESS, + [0x0264 / 4] = CA53_PROG_07_SIZE, +}; +__attribute__ ((section (".sa6_ca53_08"))) const uint32_t ca53_08_cert[2048 / 4] = { + [0x0154 / 4] = CA53_PROG_08_ADDRESS, + [0x0264 / 4] = CA53_PROG_08_SIZE, +}; + diff --git a/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/tools/dummy_create/sa6.ld b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/tools/dummy_create/sa6.ld new file mode 100644 index 0000000..945c765 --- /dev/null +++ b/IPL/SDK/v3h/src/V3H_ICUMXA_Loader/tools/dummy_create/sa6.ld @@ -0,0 +1,65 @@ +/******************************************************************************* + * Copyright (c) 2018-2021 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 6(0x180000) linker directive + ******************************************************************************/ +DEFAULTS { + dummy_addr = 0xEB200000 + + dummy_size = 1M + +} +MEMORY +{ + dram : ORIGIN = dummy_addr, LENGTH = dummy_size +} +SECTIONS +{ +// +// Dummy Certificate +// + _start = dummy_addr; + .sa6_top ALIGN(1024) : > dram + .sa6_firm ALIGN(1024) : > . + .sa6_rtos ALIGN(1024) : > . + .sa6_ca53_01 ALIGN(1024) : > . + .sa6_ca53_02 ALIGN(1024) : > . + .sa6_ca53_03 ALIGN(1024) : > . + .sa6_ca53_04 ALIGN(1024) : > . + .sa6_ca53_05 ALIGN(1024) : > . + .sa6_ca53_06 ALIGN(1024) : > . + .sa6_ca53_07 ALIGN(1024) : > . + .sa6_ca53_08 ALIGN(1024) : > . + + .sdata : > . + .tdata : > . + .rosdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/Makefile b/IPL/SDK/v3m/src/Dummy_BL33/Makefile new file mode 100644 index 0000000..850a15e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/Makefile @@ -0,0 +1,724 @@ +# +# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# Trusted Firmware Version +# +VERSION_MAJOR := 1 +VERSION_MINOR := 1 + +# +# Default values for build configurations +# + +# Build verbosity +V := 0 +# Debug build +DEBUG := 0 +# Build platform +DEFAULT_PLAT := fvp +PLAT := ${DEFAULT_PLAT} +# SPD choice +SPD := none +# Base commit to perform code check on +BASE_COMMIT := origin/master +# NS timer register save and restore +NS_TIMER_SWITCH := 0 +# By default, Bl1 acts as the reset handler, not BL31 +RESET_TO_BL31 := 0 +# Include FP registers in cpu context +CTX_INCLUDE_FPREGS := 0 +# Determine the version of ARM GIC architecture to use for interrupt management +# in EL3. The platform port can change this value if needed. +ARM_GIC_ARCH := 2 +# Determine the version of ARM CCI product used in the platform. The platform +# port can change this value if needed. +ARM_CCI_PRODUCT_ID := 400 +# Flag used to indicate if ASM_ASSERTION should be enabled for the build. +# This defaults to being present in DEBUG builds only. +ASM_ASSERTION := ${DEBUG} +# Build option to choose whether Trusted firmware uses Coherent memory or not. +USE_COHERENT_MEM := 1 +# Flag used to choose the power state format viz Extended State-ID or the Original +# format. +PSCI_EXTENDED_STATE_ID := 0 +# Default FIP file name +FIP_NAME := fip.bin +# By default, use the -pedantic option in the gcc command line +DISABLE_PEDANTIC := 0 +# Flags to generate the Chain of Trust +GENERATE_COT := 0 +CREATE_KEYS := 1 +SAVE_KEYS := 0 +# Flags to build TF with Trusted Boot support +TRUSTED_BOARD_BOOT := 0 +# By default, consider that the platform's reset address is not programmable. +# The platform Makefile is free to override this value. +PROGRAMMABLE_RESET_ADDRESS := 0 +# Build flag to warn about usage of deprecated platform and framework APIs +WARN_DEPRECATED := 0 + +# Checkpatch ignores +CHECK_IGNORE = --ignore COMPLEX_MACRO \ + --ignore GERRIT_CHANGE_ID \ + --ignore GIT_COMMIT_ID + +CHECKPATCH_ARGS = --no-tree --no-signoff ${CHECK_IGNORE} +CHECKCODE_ARGS = --no-patch --no-tree --no-signoff ${CHECK_IGNORE} +# Do not check the coding style on C library files +CHECK_PATHS = $(shell ls -I include -I lib) \ + $(addprefix include/,$(shell ls -I stdlib include)) \ + $(addprefix lib/,$(shell ls -I stdlib lib)) + +ifeq (${V},0) + Q=@ + CHECKCODE_ARGS += --no-summary --terse +else + Q= +endif +export Q + +ifneq (${DEBUG}, 0) + BUILD_TYPE := debug + # Use LOG_LEVEL_INFO by default for debug builds + LOG_LEVEL := 40 +else + BUILD_TYPE := release + # Use LOG_LEVEL_NOTICE by default for release builds + LOG_LEVEL := 20 +endif + +# Default build string (git branch and commit) +ifeq (${BUILD_STRING},) + BUILD_STRING := $(shell git log -n 1 --pretty=format:"%h") +endif + +VERSION_STRING := v${VERSION_MAJOR}.${VERSION_MINOR}(${BUILD_TYPE}):${BUILD_STRING} + +BL_COMMON_SOURCES := common/bl_common.c \ + common/tf_printf.c \ + common/aarch64/debug.S \ + lib/aarch64/cache_helpers.S \ + lib/aarch64/misc_helpers.S \ + lib/aarch64/xlat_helpers.c \ + lib/stdlib/std.c \ + plat/common/aarch64/platform_helpers.S + +BUILD_BASE := ./build +BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${BUILD_TYPE} + +PLAT_MAKEFILE := platform.mk +# Generate the platforms list by recursively searching for all directories +# under /plat containing a PLAT_MAKEFILE. Append each platform with a `|` +# char and strip out the final '|'. +PLATFORMS := $(shell find plat/ -name '${PLAT_MAKEFILE}' -print0 | \ + sed -r 's%[^\x00]*\/([^/]*)\/${PLAT_MAKEFILE}\x00%\1|%g' | \ + sed -r 's/\|$$//') +SPDS := $(shell ls -I none services/spd) + +# Convenience function for adding build definitions +# $(eval $(call add_define,FOO)) will have: +# -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +# Convenience function for verifying option has a boolean value +# $(eval $(call assert_boolean,FOO)) will assert FOO is 0 or 1 +define assert_boolean +$(and $(patsubst 0,,$(value $(1))),$(patsubst 1,,$(value $(1))),$(error $(1) must be boolean)) +endef + +ifeq (${PLAT},) + $(error "Error: Unknown platform. Please use PLAT= to specify the platform") +endif +PLAT_MAKEFILE_FULL := $(shell find plat/ -wholename '*/${PLAT}/${PLAT_MAKEFILE}') +ifeq ($(PLAT_MAKEFILE_FULL),) + $(error "Error: Invalid platform. The following platforms are available: ${PLATFORMS}") +endif + +all: msg_start + +msg_start: + @echo "Building ${PLAT}" + +include ${PLAT_MAKEFILE_FULL} + +# If the platform has not defined ENABLE_PLAT_COMPAT, then enable it by default +ifndef ENABLE_PLAT_COMPAT +ENABLE_PLAT_COMPAT := 1 +endif + +# Include the platform compatibility helpers for PSCI +ifneq (${ENABLE_PLAT_COMPAT}, 0) +include plat/compat/plat_compat.mk +endif + +# Include the CPU specific operations makefile. By default all CPU errata +# workarounds and CPU specifc optimisations are disabled. This can be +# overridden by the platform. +include lib/cpus/cpu-ops.mk + +ifdef BL1_SOURCES +NEED_BL1 := yes +include bl1/bl1.mk +endif + +ifdef BL2_SOURCES +NEED_BL2 := yes +include bl2/bl2.mk +# Using the ARM Trusted Firmware BL2 implies that a BL3-3 image also need to be supplied for the FIP. +# This flag can be overridden by the platform. +#NEED_BL33 ?= yes +endif + +ifdef BL31_SOURCES +NEED_BL31 := yes +include bl31/bl31.mk +endif + +# Include SPD Makefile if one has been specified +ifneq (${SPD},none) + # We expect to locate an spd.mk under the specified SPD directory + SPD_MAKE := $(shell m="services/spd/${SPD}/${SPD}.mk"; [ -f "$$m" ] && echo "$$m") + + ifeq (${SPD_MAKE},) + $(error Error: No services/spd/${SPD}/${SPD}.mk located) + endif + $(info Including ${SPD_MAKE}) + include ${SPD_MAKE} + + # If there's BL3-2 companion for the chosen SPD, and the SPD wants to build the + # BL3-2 from source, we expect that the SPD's Makefile would set NEED_BL32 + # variable to "yes". In case the BL3-2 is a binary which needs to be included in + # fip, then the NEED_BL32 needs to be set and BL3-2 would need to point to the bin. +endif + +ifdef BL33_SOURCES +NEED_BL33 := yes +include bl33/bl33.mk +endif + +.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool fip certtool +.SUFFIXES: + +INCLUDES += -Iinclude/bl31 \ + -Iinclude/bl31/services \ + -Iinclude/common \ + -Iinclude/drivers \ + -Iinclude/drivers/arm \ + -Iinclude/drivers/auth \ + -Iinclude/drivers/io \ + -Iinclude/drivers/ti/uart \ + -Iinclude/lib \ + -Iinclude/lib/aarch64 \ + -Iinclude/lib/cpus/aarch64 \ + -Iinclude/plat/common \ + -Iinclude/stdlib \ + -Iinclude/stdlib/sys \ + ${PLAT_INCLUDES} \ + ${SPD_INCLUDES} + +# Process DEBUG flag +$(eval $(call assert_boolean,DEBUG)) +$(eval $(call add_define,DEBUG)) +ifeq (${DEBUG},0) + $(eval $(call add_define,NDEBUG)) +CFLAGS += -g +ASFLAGS += -g -Wa,--gdwarf-2 +else +CFLAGS += -g +ASFLAGS += -g -Wa,--gdwarf-2 +endif + +# Process PLAT flag +$(eval $(call add_define,PLAT_${PLAT})) + +# Process NS_TIMER_SWITCH flag +$(eval $(call assert_boolean,NS_TIMER_SWITCH)) +$(eval $(call add_define,NS_TIMER_SWITCH)) + +# Process RESET_TO_BL31 flag +$(eval $(call assert_boolean,RESET_TO_BL31)) +$(eval $(call add_define,RESET_TO_BL31)) + +# Process CTX_INCLUDE_FPREGS flag +$(eval $(call assert_boolean,CTX_INCLUDE_FPREGS)) +$(eval $(call add_define,CTX_INCLUDE_FPREGS)) + +# Process ARM_GIC_ARCH flag +$(eval $(call add_define,ARM_GIC_ARCH)) + +# Process ARM_CCI_PRODUCT_ID flag +$(eval $(call add_define,ARM_CCI_PRODUCT_ID)) + +# Process ASM_ASSERTION flag +$(eval $(call assert_boolean,ASM_ASSERTION)) +$(eval $(call add_define,ASM_ASSERTION)) + +# Process LOG_LEVEL flag +$(eval $(call add_define,LOG_LEVEL)) + +# Process USE_COHERENT_MEM flag +$(eval $(call assert_boolean,USE_COHERENT_MEM)) +$(eval $(call add_define,USE_COHERENT_MEM)) + +# Process PSCI_EXTENDED_STATE_ID flag +$(eval $(call assert_boolean,PSCI_EXTENDED_STATE_ID)) +$(eval $(call add_define,PSCI_EXTENDED_STATE_ID)) + +# Process Generate CoT flags +$(eval $(call assert_boolean,GENERATE_COT)) +$(eval $(call assert_boolean,CREATE_KEYS)) +$(eval $(call assert_boolean,SAVE_KEYS)) + +# Process TRUSTED_BOARD_BOOT flag +$(eval $(call assert_boolean,TRUSTED_BOARD_BOOT)) +$(eval $(call add_define,TRUSTED_BOARD_BOOT)) + +# Process PROGRAMMABLE_RESET_ADDRESS flag +$(eval $(call assert_boolean,PROGRAMMABLE_RESET_ADDRESS)) +$(eval $(call add_define,PROGRAMMABLE_RESET_ADDRESS)) + +# Process ENABLE_PLAT_COMPAT flag +$(eval $(call assert_boolean,ENABLE_PLAT_COMPAT)) +$(eval $(call add_define,ENABLE_PLAT_COMPAT)) + +# Process WARN_DEPRECATED flag +$(eval $(call assert_boolean,WARN_DEPRECATED)) +$(eval $(call add_define,WARN_DEPRECATED)) + +ASFLAGS += -nostdinc -ffreestanding -Wa,--fatal-warnings \ + -Werror -Wmissing-include-dirs \ + -mgeneral-regs-only -D__ASSEMBLY__ \ + ${DEFINES} ${INCLUDES} +CFLAGS += -nostdinc -ffreestanding -Wall \ + -Werror -Wmissing-include-dirs \ + -mgeneral-regs-only -std=c99 -c -Os \ + ${DEFINES} ${INCLUDES} +CFLAGS += -ffunction-sections -fdata-sections + +LDFLAGS += --fatal-warnings -O1 +LDFLAGS += --gc-sections + + +CC := ${CROSS_COMPILE}gcc +CPP := ${CROSS_COMPILE}cpp +AS := ${CROSS_COMPILE}gcc +AR := ${CROSS_COMPILE}ar +LD := ${CROSS_COMPILE}ld +OC := ${CROSS_COMPILE}objcopy +OD := ${CROSS_COMPILE}objdump +NM := ${CROSS_COMPILE}nm +PP := ${CROSS_COMPILE}gcc -E ${CFLAGS} + +# Variables for use with Firmware Image Package +FIPTOOLPATH ?= tools/fip_create +FIPTOOL ?= ${FIPTOOLPATH}/fip_create +fiptool: ${FIPTOOL} +fip: ${BUILD_PLAT}/${FIP_NAME} + +# Variables for use with Certificate Generation Tool +CRTTOOLPATH ?= tools/cert_create +CRTTOOL ?= ${CRTTOOLPATH}/cert_create +certtool: ${CRTTOOL} + +# Dummy Image Create +DUMMYTOOLPATH ?= tools/dummy_create +DUMMYTOOL ?= ${DUMMYTOOLPATH}/dummy_create +dummytool: ${DUMMYTOOL} + +# CoT generation tool default parameters +TRUSTED_KEY_CERT := ${BUILD_PLAT}/trusted_key.crt + +# Pass the private keys to the CoT generation tool in the command line +# If CREATE_KEYS is set, the '-n' option will be added, indicating the tool to create new keys +ifneq (${GENERATE_COT},0) + $(eval CERTS := yes) + + $(eval FIP_DEPS += certificates) + $(eval FIP_ARGS += --trusted-key-cert ${TRUSTED_KEY_CERT}) + + ifneq (${CREATE_KEYS},0) + $(eval CRT_ARGS += -n) + ifneq (${SAVE_KEYS},0) + $(eval CRT_ARGS += -k) + endif + endif + $(eval CRT_ARGS += $(if ${ROT_KEY}, --rot-key ${ROT_KEY})) + $(eval CRT_ARGS += $(if ${TRUSTED_WORLD_KEY}, --trusted-world-key ${TRUSTED_WORLD_KEY})) + $(eval CRT_ARGS += $(if ${NON_TRUSTED_WORLD_KEY}, --non-trusted-world-key ${NON_TRUSTED_WORLD_KEY})) + $(eval CRT_ARGS += --trusted-key-cert ${TRUSTED_KEY_CERT}) + $(eval CRT_ARGS += $(if ${KEY_ALG}, --key-alg ${KEY_ALG})) +endif + +# Check if -pedantic option should be used +ifeq (${DISABLE_PEDANTIC},0) + CFLAGS += -pedantic +endif + +locate-checkpatch: +ifndef CHECKPATCH + $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/script/checkpatch.pl") +else +ifeq (,$(wildcard ${CHECKPATCH})) + $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/script/checkpatch.pl") +endif +endif + +clean: + @echo " CLEAN" + ${Q}rm -rf ${BUILD_PLAT} + ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean + ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean + ${Q}${MAKE} -C ${DUMMYTOOLPATH} clean + +realclean distclean: + @echo " REALCLEAN" + ${Q}rm -rf ${BUILD_BASE} + ${Q}rm -f ${CURDIR}/cscope.* + ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean + ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean + ${Q}${MAKE} -C ${DUMMYTOOLPATH} clean + +checkcodebase: locate-checkpatch + @echo " CHECKING STYLE" + @if test -d .git ; then \ + git ls-files | grep -v stdlib | while read GIT_FILE ; do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ; done ; \ + else \ + find . -type f -not -iwholename "*.git*" -not -iwholename "*build*" -not -iwholename "*stdlib*" -exec ${CHECKPATCH} ${CHECKCODE_ARGS} -f {} \; ; \ + fi + +checkpatch: locate-checkpatch + @echo " CHECKING STYLE" + ${Q}git log -p ${BASE_COMMIT}..HEAD -- ${CHECK_PATHS} | ${CHECKPATCH} ${CHECKPATCH_ARGS} - || true + +.PHONY: ${CRTTOOL} +${CRTTOOL}: + ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} + @echo + @echo "Built $@ successfully" + @echo + +.PHONY: ${FIPTOOL} +${FIPTOOL}: + ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} + +.PHONY: ${DUMMYTOOL} +${DUMMYTOOL}: + ${Q}${MAKE} -C ${DUMMYTOOLPATH} + +define match_goals +$(strip $(foreach goal,$(1),$(filter $(goal),$(MAKECMDGOALS)))) +endef + +# List of rules that involve building things +BUILD_TARGETS := all bl1 bl2 bl31 bl32 bl33 fip + +# Does the list of goals specified on the command line include a build target? +ifneq ($(call match_goals,${BUILD_TARGETS}),) +IS_ANYTHING_TO_BUILD := 1 +endif + +define MAKE_C + +$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2)))) +$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ))) + +$(OBJ) : $(2) + @echo " CC $$<" + $$(Q)$$(CC) $$(CFLAGS) -DIMAGE_BL$(3) -c $$< -o $$@ + + +$(PREREQUISITES) : $(2) + @echo " DEPS $$@" + @mkdir -p $(1) + $$(Q)$$(CC) $$(CFLAGS) -M -MT $(OBJ) -MF $$@ $$< + +ifdef IS_ANYTHING_TO_BUILD +-include $(PREREQUISITES) +endif + +endef + + +define MAKE_S + +$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2)))) +$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ))) + +$(OBJ) : $(2) + @echo " AS $$<" + $$(Q)$$(AS) $$(ASFLAGS) -DIMAGE_BL$(3) -c $$< -o $$@ + +$(PREREQUISITES) : $(2) + @echo " DEPS $$@" + @mkdir -p $(1) + $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(OBJ) -MF $$@ $$< + +ifdef IS_ANYTHING_TO_BUILD +-include $(PREREQUISITES) +endif + +endef + + +define MAKE_LD + +$(eval PREREQUISITES := $(1).d) + +$(1) : $(2) + @echo " PP $$<" + $$(Q)$$(AS) $$(ASFLAGS) -P -E -D__LINKER__ -o $$@ $$< + +$(PREREQUISITES) : $(2) + @echo " DEPS $$@" + @mkdir -p $$(dir $$@) + $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(1) -MF $$@ $$< + +ifdef IS_ANYTHING_TO_BUILD +-include $(PREREQUISITES) +endif + +endef + + +define MAKE_OBJS + $(eval C_OBJS := $(filter %.c,$(2))) + $(eval REMAIN := $(filter-out %.c,$(2))) + $(eval $(foreach obj,$(C_OBJS),$(call MAKE_C,$(1),$(obj),$(3)))) + + $(eval S_OBJS := $(filter %.S,$(REMAIN))) + $(eval REMAIN := $(filter-out %.S,$(REMAIN))) + $(eval $(foreach obj,$(S_OBJS),$(call MAKE_S,$(1),$(obj),$(3)))) + + $(and $(REMAIN),$(error Unexpected source files present: $(REMAIN))) +endef + + +# NOTE: The line continuation '\' is required in the next define otherwise we +# end up with a line-feed characer at the end of the last c filename. +# Also bare this issue in mind if extending the list of supported filetypes. +define SOURCES_TO_OBJS + $(notdir $(patsubst %.c,%.o,$(filter %.c,$(1)))) \ + $(notdir $(patsubst %.S,%.o,$(filter %.S,$(1)))) +endef + + +# MAKE_TOOL_ARGS macro defines the command line arguments for the FIP and CRT +# tools at each BL stage. Arguments: +# $(1) = BL stage (2, 30, 31, 32, 33) +# $(2) = Binary file +# $(3) = In FIP (false if empty) +# $(4) = Create certificates (false if empty) +# $(5) = Create key certificate (false if empty) +# $(6) = Private key (optional) +define MAKE_TOOL_ARGS + +$(eval FIP_DEPS += $(if $3,$(2),)) +$(eval FIP_ARGS += $(if $3,--bl$(1) $(2),)) +$(eval FIP_ARGS += $(if $4,--bl$(1)-cert $(BUILD_PLAT)/bl$(1).crt)) +$(eval FIP_ARGS += $(if $4,$(if $5,--bl$(1)-key-cert $(BUILD_PLAT)/bl$(1)_key.crt))) + +$(eval CRT_DEPS += $(if $4,$(2),)) +$(eval CRT_ARGS += $(if $4,--bl$(1) $(2))) +$(eval CRT_ARGS += $(if $4,$(if $6,--bl$(1)-key $(6)))) +$(eval CRT_ARGS += $(if $4,--bl$(1)-cert $(BUILD_PLAT)/bl$(1).crt)) +$(eval CRT_ARGS += $(if $4,$(if $5,--bl$(1)-key-cert $(BUILD_PLAT)/bl$(1)_key.crt))) + +endef + + +# MAKE_BL macro defines the targets and options to build each BL image. +# Arguments: +# $(1) = BL stage (2, 30, 31, 32, 33) +# $(2) = In FIP (false if empty) +# $(3) = Create certificates (false if empty) +# $(4) = Create key certificate (false if empty) +# $(5) = Private key (optional) +define MAKE_BL + $(eval BUILD_DIR := ${BUILD_PLAT}/bl$(1)) + $(eval SOURCES := $(BL$(1)_SOURCES) $(BL_COMMON_SOURCES) $(PLAT_BL_COMMON_SOURCES)) + $(eval OBJS := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES)))) + $(eval LINKERFILE := $(BUILD_DIR)/bl$(1).ld) + $(eval MAPFILE := $(BUILD_DIR)/bl$(1).map) + $(eval ELF := $(BUILD_DIR)/bl$(1).elf) + $(eval DUMP := $(BUILD_DIR)/bl$(1).dump) + $(eval BIN := $(BUILD_PLAT)/bl$(1).bin) + $(eval SREC := $(BUILD_PLAT)/bl$(1).srec) + + $(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES),$(1))) + $(eval $(call MAKE_LD,$(LINKERFILE),$(BL$(1)_LINKERFILE))) + +$(BUILD_DIR) : + $$(Q)mkdir -p "$$@" + +$(ELF) : $(OBJS) $(LINKERFILE) + @echo " LD $$@" + @echo 'const char build_message[] = "Built : "__TIME__", "__DATE__; \ + const char version_string[] = "${VERSION_STRING}";' | \ + $$(CC) $$(CFLAGS) -xc - -o $(BUILD_DIR)/build_message.o + $$(Q)$$(LD) -o $$@ $$(LDFLAGS) -Map=$(MAPFILE) --script $(LINKERFILE) \ + $(BUILD_DIR)/build_message.o $(OBJS) + +$(DUMP) : $(ELF) + @echo " OD $$@" + $${Q}$${OD} -dx $$< > $$@ + +$(BIN) : $(ELF) + @echo " BIN $$@" + $$(Q)$$(OC) -O binary $$< $$@ + @echo + @echo "Built $$@ successfully" + @echo + +$(SREC) : $(ELF) + @echo " SREC $$@" + $$(Q)$$(OC) -O srec $$< $$@ + +.PHONY : bl$(1) +bl$(1) : $(BUILD_DIR) $(SREC) $(BIN) $(DUMP) + +all : bl$(1) + +$(eval $(call MAKE_TOOL_ARGS,$(1),$(BIN),$(2),$(3),$(4),$(5))) + +endef + + +ifeq (${NEED_BL1},yes) +$(eval $(call MAKE_BL,1)) +endif + +ifeq (${NEED_BL2},yes) +$(if ${BL2}, $(eval $(call MAKE_TOOL_ARGS,2,${BL2},in_fip,${CERTS})),\ + $(eval $(call MAKE_BL,2,in_fip,${CERTS}))) +endif + +ifeq (${NEED_BL31},yes) +BL31_SOURCES += ${SPD_SOURCES} +$(if ${BL31}, $(eval $(call MAKE_TOOL_ARGS,31,${BL31},in_fip,${CERTS},${CERTS},${BL31_KEY})),\ + $(eval $(call MAKE_BL,31,in_fip,${CERTS},${CERTS},${BL31_KEY}))) +endif + +ifeq (${NEED_BL32},yes) +$(if ${BL32}, $(eval $(call MAKE_TOOL_ARGS,32,${BL32},in_fip,${CERTS},${CERTS},${BL32_KEY})),\ + $(eval $(call MAKE_BL,32,in_fip,${CERTS},${CERTS},${BL32_KEY}))) +endif + +ifeq (${NEED_BL30},yes) +$(if ${BL30}, $(eval $(call MAKE_TOOL_ARGS,30,${BL30},in_fip,${CERTS},${CERTS},${BL30_KEY}))) + +# If BL3-0 is needed by the platform then 'BL30' variable must be defined. +check_bl30: + $(if ${BL30},,$(error "To build a FIP for platform ${PLAT}, please set BL30 to point to the SCP firmware")) +else + +# If BL3-0 is not needed by the platform but the user still specified the path +# to a BL3-0 image then warn him that it will be ignored. +check_bl30: + $(if ${BL30},$(warning "BL3-0 is not supported on platform ${PLAT}, it will just be ignored"),) +endif + +ifeq (${NEED_BL33},yes) +$(if ${BL33}, $(eval $(call MAKE_TOOL_ARGS,33,${BL33},in_fip,${CERTS},${CERTS},${BL33_KEY})),\ + $(eval $(call MAKE_BL,33,in_fip,${CERTS},${CERTS},${BL33_KEY}))) +endif +#$(if ${BL33}, $(eval $(call MAKE_TOOL_ARGS,33,${BL33},in_fip,${CERTS},${CERTS},${BL33_KEY}))) + +# If BL3-3 is needed by the platform then 'BL33' variable must be defined. +#check_bl33: +# $(if ${BL33},,$(error "To build a FIP, please set BL33 to point to the Normal World binary, eg: BL33=../uefi/FVP_AARCH64_EFI.fd")) +#else + +# If BL3-3 is not needed by the platform but the user still specified the path +# to a BL3-3 image then warn him that it will be ignored. +#check_bl33: +# $(if ${BL33},$(warning "BL3-3 is not supported on platform ${PLAT}, it will just be ignored"),) +#endif + +# Add the dependency on the certificates +ifneq (${GENERATE_COT},0) + fip: certificates +endif + +certificates: ${CRT_DEPS} ${CRTTOOL} check_bl30 check_bl33 + ${Q}${CRTTOOL} ${CRT_ARGS} + @echo + @echo "Built $@ successfully" + @echo "Certificates can be found in ${BUILD_PLAT}" + @echo + +${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} ${FIPTOOL} check_bl30 check_bl33 + ${Q}${FIPTOOL} --dump \ + ${FIP_ARGS} \ + $@ + @echo + @echo "Built $@ successfully" + @echo + + +cscope: + @echo " CSCOPE" + ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files + ${Q}cscope -b -q -k + +help: + @echo "usage: ${MAKE} PLAT=<${PLATFORMS}> [OPTIONS] [TARGET]" + @echo "" + @echo "PLAT is used to specify which platform you wish to build." + @echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}" + @echo "" + @echo "Please refer to the User Guide for a list of all supported options." + @echo "Note that the build system doesn't track dependencies for build " + @echo "options. Therefore, if any of the build options are changed " + @echo "from a previous build, a clean build must be performed." + @echo "" + @echo "Supported Targets:" + @echo " all Build all individual bootloader binaries" + @echo " bl1 Build the BL1 binary" + @echo " bl2 Build the BL2 binary" + @echo " bl31 Build the BL3-1 binary" + @echo " bl32 Build the BL3-2 binary" + @echo " fip Build the Firmware Image Package (FIP)" + @echo " checkcodebase Check the coding style of the entire source tree" + @echo " checkpatch Check the coding style on changes in the current" + @echo " branch against BASE_COMMIT (default origin/master)" + @echo " clean Clean the build for the selected platform" + @echo " cscope Generate cscope index" + @echo " distclean Remove all build artifacts for all platforms" + @echo " certtool Build the Certificate generation tool" + @echo " fiptool Build the Firmware Image Package(FIP) creation tool" + @echo "" + @echo "Note: most build targets require PLAT to be set to a specific platform." + @echo "" + @echo "example: build all targets for the FVP platform:" + @echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all" diff --git a/IPL/SDK/v3m/src/Dummy_BL33/acknowledgements.md b/IPL/SDK/v3m/src/Dummy_BL33/acknowledgements.md new file mode 100644 index 0000000..3ffefc7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/acknowledgements.md @@ -0,0 +1,11 @@ +Contributor Acknowledgements +============================ + +Companies +--------- +Linaro Limited + +NVIDIA Corporation + +Individuals +----------- diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl1/aarch64/bl1_arch_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/bl1/aarch64/bl1_arch_setup.c new file mode 100644 index 0000000..6a3f062 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl1/aarch64/bl1_arch_setup.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/******************************************************************************* + * Function that does the first bit of architectural setup that affects + * execution in the non-secure address space. + ******************************************************************************/ +void bl1_arch_setup(void) +{ + /* Set the next EL to be AArch64 */ + write_scr_el3(SCR_RES1_BITS | SCR_RW_BIT); +} + +/******************************************************************************* + * Set the Secure EL1 required architectural state + ******************************************************************************/ +void bl1_arch_next_el_setup(void) +{ + unsigned long next_sctlr; + + /* Use the same endianness than the current BL */ + next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT); + + /* Set SCTLR Secure EL1 */ + next_sctlr |= SCTLR_EL1_RES1; + + write_sctlr_el1(next_sctlr); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl1/aarch64/bl1_entrypoint.S b/IPL/SDK/v3m/src/Dummy_BL33/bl1/aarch64/bl1_entrypoint.S new file mode 100644 index 0000000..4fc5291 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl1/aarch64/bl1_entrypoint.S @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl bl1_entrypoint + + + /* ----------------------------------------------------- + * bl1_entrypoint() is the entry point into the trusted + * firmware code when a cpu is released from warm or + * cold reset. + * ----------------------------------------------------- + */ + +func bl1_entrypoint + /* --------------------------------------------------------------------- + * If the reset address is programmable then bl1_entrypoint() is + * executed only on the cold boot path. Therefore, we can skip the warm + * boot mailbox mechanism. + * --------------------------------------------------------------------- + */ + el3_entrypoint_common \ + _set_endian=1 \ + _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ + _secondary_cold_boot=1 \ + _init_memory=1 \ + _init_c_runtime=1 \ + _exception_vectors=bl1_exceptions + + /* --------------------------------------------- + * Architectural init. can be generic e.g. + * enabling stack alignment and platform spec- + * ific e.g. MMU & page table setup as per the + * platform memory map. Perform the latter here + * and the former in bl1_main. + * --------------------------------------------- + */ + bl bl1_early_platform_setup + bl bl1_plat_arch_setup + + /* -------------------------------------------------- + * Initialize platform and jump to our c-entry point + * for this type of reset. Panic if it returns + * -------------------------------------------------- + */ + bl bl1_main +panic: + b panic +endfunc bl1_entrypoint diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl1/aarch64/bl1_exceptions.S b/IPL/SDK/v3m/src/Dummy_BL33/bl1/aarch64/bl1_exceptions.S new file mode 100644 index 0000000..1ca3a6c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl1/aarch64/bl1_exceptions.S @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + .globl bl1_exceptions + + .section .vectors, "ax"; .align 11 + + /* ----------------------------------------------------- + * Very simple stackless exception handlers used by BL1. + * ----------------------------------------------------- + */ + .align 7 +bl1_exceptions: + /* ----------------------------------------------------- + * Current EL with SP0 : 0x0 - 0x200 + * ----------------------------------------------------- + */ +SynchronousExceptionSP0: + mov x0, #SYNC_EXCEPTION_SP_EL0 + bl plat_report_exception + b SynchronousExceptionSP0 + check_vector_size SynchronousExceptionSP0 + + .align 7 +IrqSP0: + mov x0, #IRQ_SP_EL0 + bl plat_report_exception + b IrqSP0 + check_vector_size IrqSP0 + + .align 7 +FiqSP0: + mov x0, #FIQ_SP_EL0 + bl plat_report_exception + b FiqSP0 + check_vector_size FiqSP0 + + .align 7 +SErrorSP0: + mov x0, #SERROR_SP_EL0 + bl plat_report_exception + b SErrorSP0 + check_vector_size SErrorSP0 + + /* ----------------------------------------------------- + * Current EL with SPx: 0x200 - 0x400 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionSPx: + mov x0, #SYNC_EXCEPTION_SP_ELX + bl plat_report_exception + b SynchronousExceptionSPx + check_vector_size SynchronousExceptionSPx + + .align 7 +IrqSPx: + mov x0, #IRQ_SP_ELX + bl plat_report_exception + b IrqSPx + check_vector_size IrqSPx + + .align 7 +FiqSPx: + mov x0, #FIQ_SP_ELX + bl plat_report_exception + b FiqSPx + check_vector_size FiqSPx + + .align 7 +SErrorSPx: + mov x0, #SERROR_SP_ELX + bl plat_report_exception + b SErrorSPx + check_vector_size SErrorSPx + + /* ----------------------------------------------------- + * Lower EL using AArch64 : 0x400 - 0x600 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionA64: + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + /* ------------------------------------------------ + * Only a single SMC exception from BL2 to ask + * BL1 to pass EL3 control to BL31 is expected + * here. + * It expects X0 with RUN_IMAGE SMC function id + * X1 with address of a entry_point_info_t structure + * describing the BL3-1 entrypoint + * ------------------------------------------------ + */ + mov x19, x0 + mov x20, x1 + + mrs x0, esr_el3 + ubfx x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH + cmp x1, #EC_AARCH64_SMC + b.ne panic + + mov x0, #RUN_IMAGE + cmp x19, x0 + b.ne panic + + mov x0, x20 + bl display_boot_progress + + ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] + msr elr_el3, x0 + msr spsr_el3, x1 + ubfx x0, x1, #MODE_EL_SHIFT, #2 + cmp x0, #MODE_EL3 + b.ne panic + + bl disable_mmu_icache_el3 + tlbi alle3 + + ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] + ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] + ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] + ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] + eret +panic: + mov x0, #SYNC_EXCEPTION_AARCH64 + bl plat_report_exception + + wfi + b panic + check_vector_size SynchronousExceptionA64 + + .align 7 +IrqA64: + mov x0, #IRQ_AARCH64 + bl plat_report_exception + b IrqA64 + check_vector_size IrqA64 + + .align 7 +FiqA64: + mov x0, #FIQ_AARCH64 + bl plat_report_exception + b FiqA64 + check_vector_size FiqA64 + + .align 7 +SErrorA64: + mov x0, #SERROR_AARCH64 + bl plat_report_exception + b SErrorA64 + check_vector_size SErrorA64 + + /* ----------------------------------------------------- + * Lower EL using AArch32 : 0x600 - 0x800 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionA32: + mov x0, #SYNC_EXCEPTION_AARCH32 + bl plat_report_exception + b SynchronousExceptionA32 + check_vector_size SynchronousExceptionA32 + + .align 7 +IrqA32: + mov x0, #IRQ_AARCH32 + bl plat_report_exception + b IrqA32 + check_vector_size IrqA32 + + .align 7 +FiqA32: + mov x0, #FIQ_AARCH32 + bl plat_report_exception + b FiqA32 + check_vector_size FiqA32 + + .align 7 +SErrorA32: + mov x0, #SERROR_AARCH32 + bl plat_report_exception + b SErrorA32 + check_vector_size SErrorA32 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl1/bl1.ld.S b/IPL/SDK/v3m/src/Dummy_BL33/bl1/bl1.ld.S new file mode 100644 index 0000000..df9a799 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl1/bl1.ld.S @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) +OUTPUT_ARCH(PLATFORM_LINKER_ARCH) +ENTRY(bl1_entrypoint) + +MEMORY { + ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE + RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE +} + +SECTIONS +{ + . = BL1_RO_BASE; + ASSERT(. == ALIGN(4096), + "BL1_RO_BASE address is not aligned on a page boundary.") + + ro . : { + __RO_START__ = .; + *bl1_entrypoint.o(.text*) + *(.text*) + *(.rodata*) + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __PARSER_LIB_DESCS_START__ = .; + KEEP(*(.img_parser_lib_descs)) + __PARSER_LIB_DESCS_END__ = .; + + /* + * Ensure 8-byte alignment for cpu_ops so that its fields are also + * aligned. Also ensure cpu_ops inclusion. + */ + . = ALIGN(8); + __CPU_OPS_START__ = .; + KEEP(*(cpu_ops)) + __CPU_OPS_END__ = .; + + *(.vectors) + __RO_END__ = .; + } >ROM + + ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, + "cpu_ops not defined for this platform.") + + /* + * The .data section gets copied from ROM to RAM at runtime. + * Its LMA must be 16-byte aligned. + * Its VMA must be page-aligned as it marks the first read/write page. + */ + . = BL1_RW_BASE; + ASSERT(. == ALIGN(4096), + "BL1_RW_BASE address is not aligned on a page boundary.") + .data . : ALIGN(16) { + __DATA_RAM_START__ = .; + *(.data*) + __DATA_RAM_END__ = .; + } >RAM AT>ROM + + stacks . (NOLOAD) : { + __STACKS_START__ = .; + *(tzfw_normal_stacks) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss : ALIGN(16) { + __BSS_START__ = .; + *(.bss*) + *(COMMON) + __BSS_END__ = .; + } >RAM + + /* + * The xlat_table section is for full, aligned page tables (4K). + * Removing them from .bss avoids forcing 4K alignment on + * the .bss section and eliminates the unecessary zero init + */ + xlat_table (NOLOAD) : { + *(xlat_table) + } >RAM + +#if USE_COHERENT_MEM + /* + * The base address of the coherent memory section must be page-aligned (4K) + * to guarantee that the coherent data are stored on their own pages and + * are not mixed with normal data. This is required to set up the correct + * memory attributes for the coherent data page tables. + */ + coherent_ram (NOLOAD) : ALIGN(4096) { + __COHERENT_RAM_START__ = .; + *(tzfw_coherent_mem) + __COHERENT_RAM_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked + * as device memory. No other unexpected data must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __COHERENT_RAM_END__ = .; + } >RAM +#endif + + __BL1_RAM_START__ = ADDR(.data); + __BL1_RAM_END__ = .; + + __DATA_ROM_START__ = LOADADDR(.data); + __DATA_SIZE__ = SIZEOF(.data); + /* + * The .data section is the last PROGBITS section so its end marks the end + * of the read-only part of BL1's binary. + */ + ASSERT(__DATA_ROM_START__ + __DATA_SIZE__ <= BL1_RO_LIMIT, + "BL1's RO section has exceeded its limit.") + + __BSS_SIZE__ = SIZEOF(.bss); + +#if USE_COHERENT_MEM + __COHERENT_RAM_UNALIGNED_SIZE__ = + __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; +#endif + + ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl1/bl1.mk b/IPL/SDK/v3m/src/Dummy_BL33/bl1/bl1.mk new file mode 100644 index 0000000..8e73bef --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl1/bl1.mk @@ -0,0 +1,37 @@ +# +# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +BL1_SOURCES += bl1/bl1_main.c \ + bl1/aarch64/bl1_arch_setup.c \ + bl1/aarch64/bl1_entrypoint.S \ + bl1/aarch64/bl1_exceptions.S \ + lib/cpus/aarch64/cpu_helpers.S + +BL1_LINKERFILE := bl1/bl1.ld.S diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl1/bl1_main.c b/IPL/SDK/v3m/src/Dummy_BL33/bl1/bl1_main.c new file mode 100644 index 0000000..dad64e2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl1/bl1_main.c @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "bl1_private.h" + +/******************************************************************************* + * Runs BL2 from the given entry point. It results in dropping the + * exception level + ******************************************************************************/ +static void __dead2 bl1_run_bl2(entry_point_info_t *bl2_ep) +{ + /* Check bl2 security state is expected as secure */ + assert(GET_SECURITY_STATE(bl2_ep->h.attr) == SECURE); + /* Check NS Bit is also set as secure */ + assert(!(read_scr_el3() & SCR_NS_BIT)); + + bl1_arch_next_el_setup(); + + /* Tell next EL what we want done */ + bl2_ep->args.arg0 = RUN_IMAGE; + + write_spsr_el3(bl2_ep->spsr); + write_elr_el3(bl2_ep->pc); + + eret(bl2_ep->args.arg0, + bl2_ep->args.arg1, + bl2_ep->args.arg2, + bl2_ep->args.arg3, + bl2_ep->args.arg4, + bl2_ep->args.arg5, + bl2_ep->args.arg6, + bl2_ep->args.arg7); +} + +/******************************************************************************* + * The next function has a weak definition. Platform specific code can override + * it if it wishes to. + ******************************************************************************/ +#pragma weak bl1_init_bl2_mem_layout + +/******************************************************************************* + * Function that takes a memory layout into which BL2 has been loaded and + * populates a new memory layout for BL2 that ensures that BL1's data sections + * resident in secure RAM are not visible to BL2. + ******************************************************************************/ +void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, + meminfo_t *bl2_mem_layout) +{ + const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; + + assert(bl1_mem_layout != NULL); + assert(bl2_mem_layout != NULL); + + /* Check that BL1's memory is lying outside of the free memory */ + assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) || + (BL1_RAM_BASE >= bl1_mem_layout->free_base + bl1_mem_layout->free_size)); + + /* Remove BL1 RW data from the scope of memory visible to BL2 */ + *bl2_mem_layout = *bl1_mem_layout; + reserve_mem(&bl2_mem_layout->total_base, + &bl2_mem_layout->total_size, + BL1_RAM_BASE, + bl1_size); + + flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); +} + +/******************************************************************************* + * Function to perform late architectural and platform specific initialization. + * It also locates and loads the BL2 raw binary image in the trusted DRAM. Only + * called by the primary cpu after a cold boot. + * TODO: Add support for alternative image load mechanism e.g using virtio/elf + * loader etc. + ******************************************************************************/ +void bl1_main(void) +{ + /* Announce our arrival */ + NOTICE(FIRMWARE_WELCOME_STR); + NOTICE("BL1: %s\n", version_string); + NOTICE("BL1: %s\n", build_message); + + INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT); + + image_info_t bl2_image_info = { {0} }; + entry_point_info_t bl2_ep = { {0} }; + meminfo_t *bl1_tzram_layout; + meminfo_t *bl2_tzram_layout = 0x0; + int err; + +#if DEBUG + unsigned long val; + /* + * Ensure that MMU/Caches and coherency are turned on + */ + val = read_sctlr_el3(); + assert(val & SCTLR_M_BIT); + assert(val & SCTLR_C_BIT); + assert(val & SCTLR_I_BIT); + /* + * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the + * provided platform value + */ + val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; + /* + * If CWG is zero, then no CWG information is available but we can + * at least check the platform value is less than the architectural + * maximum. + */ + if (val != 0) + assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); + else + assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); +#endif + + /* Perform remaining generic architectural setup from EL3 */ + bl1_arch_setup(); + + /* Perform platform setup in BL1. */ + bl1_platform_setup(); + + SET_PARAM_HEAD(&bl2_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0); + SET_PARAM_HEAD(&bl2_ep, PARAM_EP, VERSION_1, 0); + + /* Find out how much free trusted ram remains after BL1 load */ + bl1_tzram_layout = bl1_plat_sec_mem_layout(); + + INFO("BL1: Loading BL2\n"); + +#if TRUSTED_BOARD_BOOT + /* Initialize authentication module */ + auth_mod_init(); +#endif /* TRUSTED_BOARD_BOOT */ + + /* Load the BL2 image */ + err = load_auth_image(bl1_tzram_layout, + BL2_IMAGE_ID, + BL2_BASE, + &bl2_image_info, + &bl2_ep); + + if (err) { + /* + * TODO: print failure to load BL2 but also add a tzwdog timer + * which will reset the system eventually. + */ + ERROR("Failed to load BL2 firmware.\n"); + panic(); + } + + /* + * Create a new layout of memory for BL2 as seen by BL1 i.e. + * tell it the amount of total and free memory available. + * This layout is created at the first free address visible + * to BL2. BL2 will read the memory layout before using its + * memory for other purposes. + */ + bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base; + bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout); + + bl1_plat_set_bl2_ep_info(&bl2_image_info, &bl2_ep); + bl2_ep.args.arg1 = (unsigned long)bl2_tzram_layout; + NOTICE("BL1: Booting BL2\n"); + INFO("BL1: BL2 address = 0x%llx\n", + (unsigned long long) bl2_ep.pc); + INFO("BL1: BL2 spsr = 0x%x\n", bl2_ep.spsr); + VERBOSE("BL1: BL2 memory layout address = 0x%llx\n", + (unsigned long long) bl2_tzram_layout); + + bl1_run_bl2(&bl2_ep); + + return; +} + +/******************************************************************************* + * Temporary function to print the fact that BL2 has done its job and BL31 is + * about to be loaded. This is needed as long as printfs cannot be used + ******************************************************************************/ +void display_boot_progress(entry_point_info_t *bl31_ep_info) +{ + NOTICE("BL1: Booting BL3-1\n"); + INFO("BL1: BL3-1 address = 0x%llx\n", + (unsigned long long)bl31_ep_info->pc); + INFO("BL1: BL3-1 spsr = 0x%llx\n", + (unsigned long long)bl31_ep_info->spsr); + INFO("BL1: BL3-1 params address = 0x%llx\n", + (unsigned long long)bl31_ep_info->args.arg0); + INFO("BL1: BL3-1 plat params address = 0x%llx\n", + (unsigned long long)bl31_ep_info->args.arg1); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl1/bl1_private.h b/IPL/SDK/v3m/src/Dummy_BL33/bl1/bl1_private.h new file mode 100644 index 0000000..0a8fc45 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl1/bl1_private.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BL1_PRIVATE_H__ +#define __BL1_PRIVATE_H__ + +/******************************************************************************* + * Declarations of linker defined symbols which will tell us where BL1 lives + * in Trusted RAM + ******************************************************************************/ +extern uint64_t __BL1_RAM_START__; +extern uint64_t __BL1_RAM_END__; +#define BL1_RAM_BASE (uint64_t)(&__BL1_RAM_START__) +#define BL1_RAM_LIMIT (uint64_t)(&__BL1_RAM_END__) + +/****************************************** + * Function prototypes + *****************************************/ +void bl1_arch_setup(void); +void bl1_arch_next_el_setup(void); + +#endif /* __BL1_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl2/aarch64/bl2_arch_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/bl2/aarch64/bl2_arch_setup.c new file mode 100644 index 0000000..0eafd15 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl2/aarch64/bl2_arch_setup.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/******************************************************************************* + * Place holder function to perform any S-EL1 specific architectural setup. At + * the moment there is nothing to do. + ******************************************************************************/ +void bl2_arch_setup(void) +{ + /* Give access to FP/SIMD registers */ + write_cpacr(CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE)); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl2/aarch64/bl2_entrypoint.S b/IPL/SDK/v3m/src/Dummy_BL33/bl2/aarch64/bl2_entrypoint.S new file mode 100644 index 0000000..1d26229 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl2/aarch64/bl2_entrypoint.S @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + + .globl bl2_entrypoint + + + +func bl2_entrypoint + /*--------------------------------------------- + * Store the extents of the tzram available to + * BL2 for future use. Use the opcode param to + * allow implement other functions if needed. + * --------------------------------------------- + */ + mov x20, x0 + mov x21, x1 + + /* --------------------------------------------- + * Set the exception vector to something sane. + * --------------------------------------------- + */ + adr x0, early_exceptions + msr vbar_el1, x0 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT + + /* --------------------------------------------- + * Enable the instruction cache, stack pointer + * and data access alignment checks + * --------------------------------------------- + */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el1 + orr x0, x0, x1 + msr sctlr_el1, x0 + isb + + /* --------------------------------------------- + * Check the opcodes out of paranoia. + * --------------------------------------------- + */ + mov x0, #RUN_IMAGE + cmp x0, x20 + b.ne _panic + + /* --------------------------------------------- + * Invalidate the RW memory used by the BL2 + * image. This includes the data and NOBITS + * sections. This is done to safeguard against + * possible corruption of this memory by dirty + * cache lines in a system cache as a result of + * use by an earlier boot loader stage. + * --------------------------------------------- + */ + adr x0, __RW_START__ + adr x1, __RW_END__ + sub x1, x1, x0 + bl inv_dcache_range + + /* --------------------------------------------- + * Zero out NOBITS sections. There are 2 of them: + * - the .bss section; + * - the coherent memory section. + * --------------------------------------------- + */ + ldr x0, =__BSS_START__ + ldr x1, =__BSS_SIZE__ + bl zeromem16 + +#if USE_COHERENT_MEM + ldr x0, =__COHERENT_RAM_START__ + ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ + bl zeromem16 +#endif + + /* -------------------------------------------- + * Allocate a stack whose memory will be marked + * as Normal-IS-WBWA when the MMU is enabled. + * There is no risk of reading stale stack + * memory after enabling the MMU as only the + * primary cpu is running at the moment. + * -------------------------------------------- + */ + bl plat_set_my_stack + + /* --------------------------------------------- + * Perform early platform setup & platform + * specific early arch. setup e.g. mmu setup + * --------------------------------------------- + */ + mov x0, x21 + bl bl2_early_platform_setup + bl bl2_plat_arch_setup + + /* --------------------------------------------- + * Jump to main function. + * --------------------------------------------- + */ + bl bl2_main +_panic: + b _panic +endfunc bl2_entrypoint diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl2/bl2.ld.S b/IPL/SDK/v3m/src/Dummy_BL33/bl2/bl2.ld.S new file mode 100644 index 0000000..ed99a3d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl2/bl2.ld.S @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) +OUTPUT_ARCH(PLATFORM_LINKER_ARCH) +#if PLAT_rcar +ENTRY(bl2_reset) +#else +ENTRY(bl2_entrypoint) +#endif + +MEMORY { + RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE +} + + +SECTIONS +{ + . = BL2_BASE; + ASSERT(. == ALIGN(4096), + "BL2_BASE address is not aligned on a page boundary.") + + ro . : { + __RO_START__ = .; +#if PLAT_rcar + *bl2_reset.o(.text*) +#endif + *bl2_entrypoint.o(.text*) +#if PLAT_rcar + . = NEXT(ALIGN_VERSION); + *rcar_common.o(.version*) +#endif + *(.text*) + *(.rodata*) + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __PARSER_LIB_DESCS_START__ = .; + KEEP(*(.img_parser_lib_descs)) + __PARSER_LIB_DESCS_END__ = .; + + *(.vectors) + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as + * read-only, executable. No RW data from the next section must + * creep in. Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __RO_END__ = .; + } >RAM + + /* + * Define a linker symbol to mark start of the RW memory area for this + * image. + */ + __RW_START__ = . ; + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + + stacks (NOLOAD) : { + __STACKS_START__ = .; + *(tzfw_normal_stacks) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } >RAM + + /* + * The xlat_table section is for full, aligned page tables (4K). + * Removing them from .bss avoids forcing 4K alignment on + * the .bss section and eliminates the unecessary zero init + */ + xlat_table (NOLOAD) : { + *(xlat_table) + } >RAM + +#if USE_COHERENT_MEM + /* + * The base address of the coherent memory section must be page-aligned (4K) + * to guarantee that the coherent data are stored on their own pages and + * are not mixed with normal data. This is required to set up the correct + * memory attributes for the coherent data page tables. + */ + coherent_ram (NOLOAD) : ALIGN(4096) { + __COHERENT_RAM_START__ = .; + *(tzfw_coherent_mem) + __COHERENT_RAM_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked + * as device memory. No other unexpected data must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __COHERENT_RAM_END__ = .; + } >RAM +#endif + + /* + * Define a linker symbol to mark end of the RW memory area for this + * image. + */ + __RW_END__ = .; + __BL2_END__ = .; + + __BSS_SIZE__ = SIZEOF(.bss); + +#if USE_COHERENT_MEM + __COHERENT_RAM_UNALIGNED_SIZE__ = + __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; +#endif + + ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl2/bl2.mk b/IPL/SDK/v3m/src/Dummy_BL33/bl2/bl2.mk new file mode 100644 index 0000000..1e82078 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl2/bl2.mk @@ -0,0 +1,37 @@ +# +# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +BL2_SOURCES += bl2/bl2_main.c \ + bl2/aarch64/bl2_entrypoint.S \ + bl2/aarch64/bl2_arch_setup.c \ + common/aarch64/early_exceptions.S \ + lib/locks/exclusive/spinlock.S + +BL2_LINKERFILE := bl2/bl2.ld.S diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl2/bl2_main.c b/IPL/SDK/v3m/src/Dummy_BL33/bl2/bl2_main.c new file mode 100644 index 0000000..71940a6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl2/bl2_main.c @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "bl2_private.h" + +/******************************************************************************* + * Load the BL3-0 image if there's one. + * If a platform does not want to attempt to load BL3-0 image it must leave + * BL30_BASE undefined. + * Return 0 on success or if there's no BL3-0 image to load, a negative error + * code otherwise. + ******************************************************************************/ +static int load_bl30(void) +{ + int e = 0; +#ifdef BL30_BASE + meminfo_t bl30_mem_info; + image_info_t bl30_image_info; + + /* + * It is up to the platform to specify where BL3-0 should be loaded if + * it exists. It could create space in the secure sram or point to a + * completely different memory. + * + * The entry point information is not relevant in this case as the AP + * won't execute the BL3-0 image. + */ + INFO("BL2: Loading BL3-0\n"); + bl2_plat_get_bl30_meminfo(&bl30_mem_info); + bl30_image_info.h.version = VERSION_1; + e = load_auth_image(&bl30_mem_info, + BL30_IMAGE_ID, + BL30_BASE, + &bl30_image_info, + NULL); + + if (e == 0) { + /* The subsequent handling of BL3-0 is platform specific */ + e = bl2_plat_handle_bl30(&bl30_image_info); + if (e) { + ERROR("Failure in platform-specific handling of BL3-0 image.\n"); + } + } +#endif /* BL30_BASE */ + + return e; +} + +/******************************************************************************* + * Load the BL3-1 image. + * The bl2_to_bl31_params and bl31_ep_info params will be updated with the + * relevant BL3-1 information. + * Return 0 on success, a negative error code otherwise. + ******************************************************************************/ +static int load_bl31(bl31_params_t *bl2_to_bl31_params, + entry_point_info_t *bl31_ep_info) +{ + meminfo_t *bl2_tzram_layout; + int e; + + INFO("BL2: Loading BL3-1\n"); + assert(bl2_to_bl31_params != NULL); + assert(bl31_ep_info != NULL); + + /* Find out how much free trusted ram remains after BL2 load */ + bl2_tzram_layout = bl2_plat_sec_mem_layout(); + + /* Set the X0 parameter to BL3-1 */ + bl31_ep_info->args.arg0 = (unsigned long)bl2_to_bl31_params; + + /* Load the BL3-1 image */ + e = load_auth_image(bl2_tzram_layout, + BL31_IMAGE_ID, + BL31_BASE, + bl2_to_bl31_params->bl31_image_info, + bl31_ep_info); + + if (e == 0) { + bl2_plat_set_bl31_ep_info(bl2_to_bl31_params->bl31_image_info, + bl31_ep_info); + } + + return e; +} + +/******************************************************************************* + * Load the BL3-2 image if there's one. + * The bl2_to_bl31_params param will be updated with the relevant BL3-2 + * information. + * If a platform does not want to attempt to load BL3-2 image it must leave + * BL32_BASE undefined. + * Return 0 on success or if there's no BL3-2 image to load, a negative error + * code otherwise. + ******************************************************************************/ +static int load_bl32(bl31_params_t *bl2_to_bl31_params) +{ + int e = 0; +#ifdef BL32_BASE + meminfo_t bl32_mem_info; + + INFO("BL2: Loading BL3-2\n"); + assert(bl2_to_bl31_params != NULL); + + /* + * It is up to the platform to specify where BL3-2 should be loaded if + * it exists. It could create space in the secure sram or point to a + * completely different memory. + */ + bl2_plat_get_bl32_meminfo(&bl32_mem_info); + e = load_auth_image(&bl32_mem_info, + BL32_IMAGE_ID, + BL32_BASE, + bl2_to_bl31_params->bl32_image_info, + bl2_to_bl31_params->bl32_ep_info); + + if (e == 0) { + bl2_plat_set_bl32_ep_info( + bl2_to_bl31_params->bl32_image_info, + bl2_to_bl31_params->bl32_ep_info); + } +#endif /* BL32_BASE */ + + return e; +} + +/******************************************************************************* + * Load the BL3-3 image. + * The bl2_to_bl31_params param will be updated with the relevant BL3-3 + * information. + * Return 0 on success, a negative error code otherwise. + ******************************************************************************/ +static int load_bl33(bl31_params_t *bl2_to_bl31_params) +{ + meminfo_t bl33_mem_info; + int e; + + INFO("BL2: Loading BL3-3\n"); + assert(bl2_to_bl31_params != NULL); + + bl2_plat_get_bl33_meminfo(&bl33_mem_info); + + /* Load the BL3-3 image in non-secure memory provided by the platform */ + e = load_auth_image(&bl33_mem_info, + BL33_IMAGE_ID, + plat_get_ns_image_entrypoint(), + bl2_to_bl31_params->bl33_image_info, + bl2_to_bl31_params->bl33_ep_info); + + if (e == 0) { + bl2_plat_set_bl33_ep_info(bl2_to_bl31_params->bl33_image_info, + bl2_to_bl31_params->bl33_ep_info); + } + + return e; +} + +/******************************************************************************* + * The only thing to do in BL2 is to load further images and pass control to + * BL3-1. The memory occupied by BL2 will be reclaimed by BL3-x stages. BL2 runs + * entirely in S-EL1. + ******************************************************************************/ +void bl2_main(void) +{ + bl31_params_t *bl2_to_bl31_params; + entry_point_info_t *bl31_ep_info; + int e; + + NOTICE("BL2: %s\n", version_string); + NOTICE("BL2: %s\n", build_message); + + /* Perform remaining generic architectural setup in S-EL1 */ + bl2_arch_setup(); + +#if TRUSTED_BOARD_BOOT + /* Initialize authentication module */ + auth_mod_init(); +#endif /* TRUSTED_BOARD_BOOT */ + + /* + * Load the subsequent bootloader images + */ + e = load_bl30(); + if (e) { + ERROR("Failed to load BL3-0 (%i)\n", e); + panic(); + } + + /* Perform platform setup in BL2 after loading BL3-0 */ + bl2_platform_setup(); + + /* + * Get a pointer to the memory the platform has set aside to pass + * information to BL3-1. + */ + bl2_to_bl31_params = bl2_plat_get_bl31_params(); + bl31_ep_info = bl2_plat_get_bl31_ep_info(); + + e = load_bl31(bl2_to_bl31_params, bl31_ep_info); + if (e) { + ERROR("Failed to load BL3-1 (%i)\n", e); + panic(); + } + + e = load_bl32(bl2_to_bl31_params); + if (e) { + if (e == LOAD_AUTH_ERR) { + ERROR("Failed to authenticate BL3-2\n"); + panic(); + } else { + WARN("Failed to load BL3-2 (%i)\n", e); + } + } + + e = load_bl33(bl2_to_bl31_params); + if (e) { + ERROR("Failed to load BL3-3 (%i)\n", e); + panic(); + } + + /* Flush the params to be passed to memory */ + bl2_plat_flush_bl31_params(); + + /* + * Run BL3-1 via an SMC to BL1. Information on how to pass control to + * the BL3-2 (if present) and BL3-3 software images will be passed to + * BL3-1 as an argument. + */ + smc(RUN_IMAGE, (unsigned long)bl31_ep_info, 0, 0, 0, 0, 0, 0); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl2/bl2_private.h b/IPL/SDK/v3m/src/Dummy_BL33/bl2/bl2_private.h new file mode 100644 index 0000000..022d1e9 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl2/bl2_private.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BL2_PRIVATE_H__ +#define __BL2_PRIVATE_H__ + +/****************************************** + * Function prototypes + *****************************************/ +void bl2_arch_setup(void); + +#endif /* __BL2_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/bl31_arch_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/bl31_arch_setup.c new file mode 100644 index 0000000..edf1018 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/bl31_arch_setup.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * This duplicates what the primary cpu did after a cold boot in BL1. The same + * needs to be done when a cpu is hotplugged in. This function could also over- + * ride any EL3 setup done by BL1 as this code resides in rw memory. + ******************************************************************************/ +void bl31_arch_setup(void) +{ + /* Set the RES1 bits in the SCR_EL3 */ + write_scr_el3(SCR_RES1_BITS); + + /* Program the counter frequency */ + write_cntfrq_el0(plat_get_syscnt_freq()); + + /* Initialize the cpu_ops pointer. */ + init_cpu_ops(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/bl31_entrypoint.S b/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/bl31_entrypoint.S new file mode 100644 index 0000000..eee0cad --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/bl31_entrypoint.S @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .globl bl31_entrypoint + + + /* ----------------------------------------------------- + * bl31_entrypoint() is the cold boot entrypoint, + * executed only by the primary cpu. + * ----------------------------------------------------- + */ + +func bl31_entrypoint +#if !RESET_TO_BL31 + /* --------------------------------------------------------------- + * Preceding bootloader has populated x0 with a pointer to a + * 'bl31_params' structure & x1 with a pointer to platform + * specific structure + * --------------------------------------------------------------- + */ + mov x20, x0 + mov x21, x1 + + /* --------------------------------------------------------------------- + * For !RESET_TO_BL31 systems, only the primary CPU ever reaches + * bl31_entrypoint() during the cold boot flow, so the cold/warm boot + * and primary/secondary CPU logic should not be executed in this case. + * + * Also, assume that the previous bootloader has already set up the CPU + * endianness and has initialised the memory. + * --------------------------------------------------------------------- + */ +#if PLAT_rcar + el3_entrypoint_common \ + _set_endian=0 \ + _warm_boot_mailbox=1 \ + _secondary_cold_boot=1 \ + _init_memory=1 \ + _init_c_runtime=1 \ + _exception_vectors=runtime_exceptions +#else + el3_entrypoint_common \ + _set_endian=0 \ + _warm_boot_mailbox=0 \ + _secondary_cold_boot=0 \ + _init_memory=0 \ + _init_c_runtime=1 \ + _exception_vectors=runtime_exceptions +#endif + + /* --------------------------------------------------------------------- + * Relay the previous bootloader's arguments to the platform layer + * --------------------------------------------------------------------- + */ + mov x0, x20 + mov x1, x21 +#else + /* --------------------------------------------------------------------- + * For RESET_TO_BL31 systems which have a programmable reset address, + * bl31_entrypoint() is executed only on the cold boot path so we can + * skip the warm boot mailbox mechanism. + * --------------------------------------------------------------------- + */ + el3_entrypoint_common \ + _set_endian=1 \ + _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ + _secondary_cold_boot=1 \ + _init_memory=1 \ + _init_c_runtime=1 \ + _exception_vectors=runtime_exceptions + + /* --------------------------------------------------------------------- + * For RESET_TO_BL31 systems, BL3-1 is the first bootloader to run so + * there's no argument to relay from a previous bootloader. Zero the + * arguments passed to the platform layer to reflect that. + * --------------------------------------------------------------------- + */ + mov x0, 0 + mov x1, 0 +#endif /* RESET_TO_BL31 */ + + /* --------------------------------------------- + * Perform platform specific early arch. setup + * --------------------------------------------- + */ + bl bl31_early_platform_setup + bl bl31_plat_arch_setup + + /* --------------------------------------------- + * Jump to main function. + * --------------------------------------------- + */ + bl bl31_main + + /* ------------------------------------------------------------- + * Clean the .data & .bss sections to main memory. This ensures + * that any global data which was initialised by the primary CPU + * is visible to secondary CPUs before they enable their data + * caches and participate in coherency. + * ------------------------------------------------------------- + */ + adr x0, __DATA_START__ + adr x1, __DATA_END__ + sub x1, x1, x0 + bl clean_dcache_range + + adr x0, __BSS_START__ + adr x1, __BSS_END__ + sub x1, x1, x0 + bl clean_dcache_range + + b el3_exit +endfunc bl31_entrypoint diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/context.S b/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/context.S new file mode 100644 index 0000000..70a1e5d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/context.S @@ -0,0 +1,305 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/* ----------------------------------------------------- + * The following function strictly follows the AArch64 + * PCS to use x9-x17 (temporary caller-saved registers) + * to save EL1 system register context. It assumes that + * 'x0' is pointing to a 'el1_sys_regs' structure where + * the register context will be saved. + * ----------------------------------------------------- + */ + .global el1_sysregs_context_save +func el1_sysregs_context_save + + mrs x9, spsr_el1 + mrs x10, elr_el1 + stp x9, x10, [x0, #CTX_SPSR_EL1] + + mrs x11, spsr_abt + mrs x12, spsr_und + stp x11, x12, [x0, #CTX_SPSR_ABT] + + mrs x13, spsr_irq + mrs x14, spsr_fiq + stp x13, x14, [x0, #CTX_SPSR_IRQ] + + mrs x15, sctlr_el1 + mrs x16, actlr_el1 + stp x15, x16, [x0, #CTX_SCTLR_EL1] + + mrs x17, cpacr_el1 + mrs x9, csselr_el1 + stp x17, x9, [x0, #CTX_CPACR_EL1] + + mrs x10, sp_el1 + mrs x11, esr_el1 + stp x10, x11, [x0, #CTX_SP_EL1] + + mrs x12, ttbr0_el1 + mrs x13, ttbr1_el1 + stp x12, x13, [x0, #CTX_TTBR0_EL1] + + mrs x14, mair_el1 + mrs x15, amair_el1 + stp x14, x15, [x0, #CTX_MAIR_EL1] + + mrs x16, tcr_el1 + mrs x17, tpidr_el1 + stp x16, x17, [x0, #CTX_TCR_EL1] + + mrs x9, tpidr_el0 + mrs x10, tpidrro_el0 + stp x9, x10, [x0, #CTX_TPIDR_EL0] + + mrs x11, dacr32_el2 + mrs x12, ifsr32_el2 + stp x11, x12, [x0, #CTX_DACR32_EL2] + + mrs x13, par_el1 + mrs x14, far_el1 + stp x13, x14, [x0, #CTX_PAR_EL1] + + mrs x15, afsr0_el1 + mrs x16, afsr1_el1 + stp x15, x16, [x0, #CTX_AFSR0_EL1] + + mrs x17, contextidr_el1 + mrs x9, vbar_el1 + stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] + + /* Save NS timer registers if the build has instructed so */ +#if NS_TIMER_SWITCH + mrs x10, cntp_ctl_el0 + mrs x11, cntp_cval_el0 + stp x10, x11, [x0, #CTX_CNTP_CTL_EL0] + + mrs x12, cntv_ctl_el0 + mrs x13, cntv_cval_el0 + stp x12, x13, [x0, #CTX_CNTV_CTL_EL0] + + mrs x14, cntkctl_el1 + str x14, [x0, #CTX_CNTKCTL_EL1] +#endif + + mrs x15, fpexc32_el2 + str x15, [x0, #CTX_FP_FPEXC32_EL2] + + ret +endfunc el1_sysregs_context_save + +/* ----------------------------------------------------- + * The following function strictly follows the AArch64 + * PCS to use x9-x17 (temporary caller-saved registers) + * to restore EL1 system register context. It assumes + * that 'x0' is pointing to a 'el1_sys_regs' structure + * from where the register context will be restored + * ----------------------------------------------------- + */ + .global el1_sysregs_context_restore +func el1_sysregs_context_restore + + ldp x9, x10, [x0, #CTX_SPSR_EL1] + msr spsr_el1, x9 + msr elr_el1, x10 + + ldp x11, x12, [x0, #CTX_SPSR_ABT] + msr spsr_abt, x11 + msr spsr_und, x12 + + ldp x13, x14, [x0, #CTX_SPSR_IRQ] + msr spsr_irq, x13 + msr spsr_fiq, x14 + + ldp x15, x16, [x0, #CTX_SCTLR_EL1] + msr sctlr_el1, x15 + msr actlr_el1, x16 + + ldp x17, x9, [x0, #CTX_CPACR_EL1] + msr cpacr_el1, x17 + msr csselr_el1, x9 + + ldp x10, x11, [x0, #CTX_SP_EL1] + msr sp_el1, x10 + msr esr_el1, x11 + + ldp x12, x13, [x0, #CTX_TTBR0_EL1] + msr ttbr0_el1, x12 + msr ttbr1_el1, x13 + + ldp x14, x15, [x0, #CTX_MAIR_EL1] + msr mair_el1, x14 + msr amair_el1, x15 + + ldp x16, x17, [x0, #CTX_TCR_EL1] + msr tcr_el1, x16 + msr tpidr_el1, x17 + + ldp x9, x10, [x0, #CTX_TPIDR_EL0] + msr tpidr_el0, x9 + msr tpidrro_el0, x10 + + ldp x11, x12, [x0, #CTX_DACR32_EL2] + msr dacr32_el2, x11 + msr ifsr32_el2, x12 + + ldp x13, x14, [x0, #CTX_PAR_EL1] + msr par_el1, x13 + msr far_el1, x14 + + ldp x15, x16, [x0, #CTX_AFSR0_EL1] + msr afsr0_el1, x15 + msr afsr1_el1, x16 + + ldp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] + msr contextidr_el1, x17 + msr vbar_el1, x9 + + /* Restore NS timer registers if the build has instructed so */ +#if NS_TIMER_SWITCH + ldp x10, x11, [x0, #CTX_CNTP_CTL_EL0] + msr cntp_ctl_el0, x10 + msr cntp_cval_el0, x11 + + ldp x12, x13, [x0, #CTX_CNTV_CTL_EL0] + msr cntv_ctl_el0, x12 + msr cntv_cval_el0, x13 + + ldr x14, [x0, #CTX_CNTKCTL_EL1] + msr cntkctl_el1, x14 +#endif + + ldr x15, [x0, #CTX_FP_FPEXC32_EL2] + msr fpexc32_el2, x15 + + /* No explict ISB required here as ERET covers it */ + + ret +endfunc el1_sysregs_context_restore + +/* ----------------------------------------------------- + * The following function follows the aapcs_64 strictly + * to use x9-x17 (temporary caller-saved registers + * according to AArch64 PCS) to save floating point + * register context. It assumes that 'x0' is pointing to + * a 'fp_regs' structure where the register context will + * be saved. + * + * Access to VFP registers will trap if CPTR_EL3.TFP is + * set. However currently we don't use VFP registers + * nor set traps in Trusted Firmware, and assume it's + * cleared + * + * TODO: Revisit when VFP is used in secure world + * ----------------------------------------------------- + */ +#if CTX_INCLUDE_FPREGS + .global fpregs_context_save +func fpregs_context_save + stp q0, q1, [x0, #CTX_FP_Q0] + stp q2, q3, [x0, #CTX_FP_Q2] + stp q4, q5, [x0, #CTX_FP_Q4] + stp q6, q7, [x0, #CTX_FP_Q6] + stp q8, q9, [x0, #CTX_FP_Q8] + stp q10, q11, [x0, #CTX_FP_Q10] + stp q12, q13, [x0, #CTX_FP_Q12] + stp q14, q15, [x0, #CTX_FP_Q14] + stp q16, q17, [x0, #CTX_FP_Q16] + stp q18, q19, [x0, #CTX_FP_Q18] + stp q20, q21, [x0, #CTX_FP_Q20] + stp q22, q23, [x0, #CTX_FP_Q22] + stp q24, q25, [x0, #CTX_FP_Q24] + stp q26, q27, [x0, #CTX_FP_Q26] + stp q28, q29, [x0, #CTX_FP_Q28] + stp q30, q31, [x0, #CTX_FP_Q30] + + mrs x9, fpsr + str x9, [x0, #CTX_FP_FPSR] + + mrs x10, fpcr + str x10, [x0, #CTX_FP_FPCR] + + ret +endfunc fpregs_context_save + +/* ----------------------------------------------------- + * The following function follows the aapcs_64 strictly + * to use x9-x17 (temporary caller-saved registers + * according to AArch64 PCS) to restore floating point + * register context. It assumes that 'x0' is pointing to + * a 'fp_regs' structure from where the register context + * will be restored. + * + * Access to VFP registers will trap if CPTR_EL3.TFP is + * set. However currently we don't use VFP registers + * nor set traps in Trusted Firmware, and assume it's + * cleared + * + * TODO: Revisit when VFP is used in secure world + * ----------------------------------------------------- + */ + .global fpregs_context_restore +func fpregs_context_restore + ldp q0, q1, [x0, #CTX_FP_Q0] + ldp q2, q3, [x0, #CTX_FP_Q2] + ldp q4, q5, [x0, #CTX_FP_Q4] + ldp q6, q7, [x0, #CTX_FP_Q6] + ldp q8, q9, [x0, #CTX_FP_Q8] + ldp q10, q11, [x0, #CTX_FP_Q10] + ldp q12, q13, [x0, #CTX_FP_Q12] + ldp q14, q15, [x0, #CTX_FP_Q14] + ldp q16, q17, [x0, #CTX_FP_Q16] + ldp q18, q19, [x0, #CTX_FP_Q18] + ldp q20, q21, [x0, #CTX_FP_Q20] + ldp q22, q23, [x0, #CTX_FP_Q22] + ldp q24, q25, [x0, #CTX_FP_Q24] + ldp q26, q27, [x0, #CTX_FP_Q26] + ldp q28, q29, [x0, #CTX_FP_Q28] + ldp q30, q31, [x0, #CTX_FP_Q30] + + ldr x9, [x0, #CTX_FP_FPSR] + msr fpsr, x9 + + str x10, [x0, #CTX_FP_FPCR] + msr fpcr, x10 + + /* + * No explict ISB required here as ERET to + * swtich to secure EL1 or non-secure world + * covers it + */ + + ret +endfunc fpregs_context_restore +#endif /* CTX_INCLUDE_FPREGS */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/cpu_data.S b/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/cpu_data.S new file mode 100644 index 0000000..0842825 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/cpu_data.S @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +.globl init_cpu_data_ptr +.globl _cpu_data_by_index + +/* ----------------------------------------------------------------- + * void init_cpu_data_ptr(void) + * + * Initialise the TPIDR_EL3 register to refer to the cpu_data_t + * for the calling CPU. This must be called before cm_get_cpu_data() + * + * This can be called without a valid stack. It assumes that + * plat_my_core_pos() does not clobber register x10. + * clobbers: x0, x1, x10 + * ----------------------------------------------------------------- + */ +func init_cpu_data_ptr + mov x10, x30 + bl plat_my_core_pos + bl _cpu_data_by_index + msr tpidr_el3, x0 + ret x10 +endfunc init_cpu_data_ptr + +/* ----------------------------------------------------------------- + * cpu_data_t *_cpu_data_by_index(uint32_t cpu_index) + * + * Return the cpu_data structure for the CPU with given linear index + * + * This can be called without a valid stack. + * clobbers: x0, x1 + * ----------------------------------------------------------------- + */ +func _cpu_data_by_index + adr x1, percpu_data + add x0, x1, x0, LSL #CPU_DATA_LOG2SIZE + ret +endfunc _cpu_data_by_index diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/crash_reporting.S b/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/crash_reporting.S new file mode 100644 index 0000000..7edbbf2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/crash_reporting.S @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include + + .globl report_unhandled_exception + .globl report_unhandled_interrupt + .globl el3_panic + +#if CRASH_REPORTING +#define REG_SIZE 0x8 + + /* ------------------------------------------------------ + * The below section deals with dumping the system state + * when an unhandled exception is taken in EL3. + * The layout and the names of the registers which will + * be dumped during a unhandled exception is given below. + * ------------------------------------------------------ + */ +.section .rodata.crash_prints, "aS" +print_spacer: + .asciz " =\t\t0x" + +gp_regs: + .asciz "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\ + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",\ + "x16", "x17", "x18", "x19", "x20", "x21", "x22",\ + "x23", "x24", "x25", "x26", "x27", "x28", "x29", "" +el3_sys_regs: + .asciz "scr_el3", "sctlr_el3", "cptr_el3", "tcr_el3",\ + "daif", "mair_el3", "spsr_el3", "elr_el3", "ttbr0_el3",\ + "esr_el3", "far_el3", "" + +non_el3_sys_regs: + .asciz "spsr_el1", "elr_el1", "spsr_abt", "spsr_und",\ + "spsr_irq", "spsr_fiq", "sctlr_el1", "actlr_el1", "cpacr_el1",\ + "csselr_el1", "sp_el1", "esr_el1", "ttbr0_el1", "ttbr1_el1",\ + "mair_el1", "amair_el1", "tcr_el1", "tpidr_el1", "tpidr_el0",\ + "tpidrro_el0", "dacr32_el2", "ifsr32_el2", "par_el1",\ + "mpidr_el1", "afsr0_el1", "afsr1_el1", "contextidr_el1",\ + "vbar_el1", "cntp_ctl_el0", "cntp_cval_el0", "cntv_ctl_el0",\ + "cntv_cval_el0", "cntkctl_el1", "fpexc32_el2", "sp_el0", "" + +panic_msg: + .asciz "PANIC in EL3 at x30 = 0x" +excpt_msg: + .asciz "Unhandled Exception in EL3.\nx30 =\t\t0x" +intr_excpt_msg: + .asciz "Unhandled Interrupt Exception in EL3.\nx30 =\t\t0x" + + /* + * Helper function to print newline to console. + */ +func print_newline + mov x0, '\n' + b plat_crash_console_putc +endfunc print_newline + + /* + * Helper function to print from crash buf. + * The print loop is controlled by the buf size and + * ascii reg name list which is passed in x6. The + * function returns the crash buf address in x0. + * Clobbers : x0 - x7, sp + */ +func size_controlled_print + /* Save the lr */ + mov sp, x30 + /* load the crash buf address */ + mrs x7, tpidr_el3 +test_size_list: + /* Calculate x5 always as it will be clobbered by asm_print_hex */ + mrs x5, tpidr_el3 + add x5, x5, #CPU_DATA_CRASH_BUF_SIZE + /* Test whether we have reached end of crash buf */ + cmp x7, x5 + b.eq exit_size_print + ldrb w4, [x6] + /* Test whether we are at end of list */ + cbz w4, exit_size_print + mov x4, x6 + /* asm_print_str updates x4 to point to next entry in list */ + bl asm_print_str + /* update x6 with the updated list pointer */ + mov x6, x4 + adr x4, print_spacer + bl asm_print_str + ldr x4, [x7], #REG_SIZE + bl asm_print_hex + bl print_newline + b test_size_list +exit_size_print: + mov x30, sp + ret +endfunc size_controlled_print + + /* + * Helper function to store x8 - x15 registers to + * the crash buf. The system registers values are + * copied to x8 to x15 by the caller which are then + * copied to the crash buf by this function. + * x0 points to the crash buf. It then calls + * size_controlled_print to print to console. + * Clobbers : x0 - x7, sp + */ +func str_in_crash_buf_print + /* restore the crash buf address in x0 */ + mrs x0, tpidr_el3 + stp x8, x9, [x0] + stp x10, x11, [x0, #REG_SIZE * 2] + stp x12, x13, [x0, #REG_SIZE * 4] + stp x14, x15, [x0, #REG_SIZE * 6] + b size_controlled_print +endfunc str_in_crash_buf_print + + /* ------------------------------------------------------ + * This macro calculates the offset to crash buf from + * cpu_data and stores it in tpidr_el3. It also saves x0 + * and x1 in the crash buf by using sp as a temporary + * register. + * ------------------------------------------------------ + */ + .macro prepare_crash_buf_save_x0_x1 + /* we can corrupt this reg to free up x0 */ + mov sp, x0 + /* tpidr_el3 contains the address to cpu_data structure */ + mrs x0, tpidr_el3 + /* Calculate the Crash buffer offset in cpu_data */ + add x0, x0, #CPU_DATA_CRASH_BUF_OFFSET + /* Store crash buffer address in tpidr_el3 */ + msr tpidr_el3, x0 + str x1, [x0, #REG_SIZE] + mov x1, sp + str x1, [x0] + .endm + + /* ----------------------------------------------------- + * This function allows to report a crash (if crash + * reporting is enabled) when an unhandled exception + * occurs. It prints the CPU state via the crash console + * making use of the crash buf. This function will + * not return. + * ----------------------------------------------------- + */ +func report_unhandled_exception + prepare_crash_buf_save_x0_x1 + adr x0, excpt_msg + mov sp, x0 + /* This call will not return */ + b do_crash_reporting +endfunc report_unhandled_exception + + + /* ----------------------------------------------------- + * This function allows to report a crash (if crash + * reporting is enabled) when an unhandled interrupt + * occurs. It prints the CPU state via the crash console + * making use of the crash buf. This function will + * not return. + * ----------------------------------------------------- + */ +func report_unhandled_interrupt + prepare_crash_buf_save_x0_x1 + adr x0, intr_excpt_msg + mov sp, x0 + /* This call will not return */ + b do_crash_reporting +endfunc report_unhandled_interrupt + + /* ----------------------------------------------------- + * This function allows to report a crash (if crash + * reporting is enabled) when panic() is invoked from + * C Runtime. It prints the CPU state via the crash + * console making use of the crash buf. This function + * will not return. + * ----------------------------------------------------- + */ +func el3_panic + msr spsel, #1 + prepare_crash_buf_save_x0_x1 + adr x0, panic_msg + mov sp, x0 + /* This call will not return */ + b do_crash_reporting +endfunc el3_panic + + /* ------------------------------------------------------------ + * The common crash reporting functionality. It requires x0 + * and x1 has already been stored in crash buf, sp points to + * crash message and tpidr_el3 contains the crash buf address. + * The function does the following: + * - Retrieve the crash buffer from tpidr_el3 + * - Store x2 to x6 in the crash buffer + * - Initialise the crash console. + * - Print the crash message by using the address in sp. + * - Print x30 value to the crash console. + * - Print x0 - x7 from the crash buf to the crash console. + * - Print x8 - x29 (in groups of 8 registers) using the + * crash buf to the crash console. + * - Print el3 sys regs (in groups of 8 registers) using the + * crash buf to the crash console. + * - Print non el3 sys regs (in groups of 8 registers) using + * the crash buf to the crash console. + * ------------------------------------------------------------ + */ +func do_crash_reporting + /* Retrieve the crash buf from tpidr_el3 */ + mrs x0, tpidr_el3 + /* Store x2 - x6, x30 in the crash buffer */ + stp x2, x3, [x0, #REG_SIZE * 2] + stp x4, x5, [x0, #REG_SIZE * 4] + stp x6, x30, [x0, #REG_SIZE * 6] + /* Initialize the crash console */ + bl plat_crash_console_init + /* Verify the console is initialized */ + cbz x0, crash_panic + /* Print the crash message. sp points to the crash message */ + mov x4, sp + bl asm_print_str + /* load the crash buf address */ + mrs x0, tpidr_el3 + /* report x30 first from the crash buf */ + ldr x4, [x0, #REG_SIZE * 7] + bl asm_print_hex + bl print_newline + /* Load the crash buf address */ + mrs x0, tpidr_el3 + /* Now mov x7 into crash buf */ + str x7, [x0, #REG_SIZE * 7] + + /* Report x0 - x29 values stored in crash buf*/ + /* Store the ascii list pointer in x6 */ + adr x6, gp_regs + /* Print x0 to x7 from the crash buf */ + bl size_controlled_print + /* Store x8 - x15 in crash buf and print */ + bl str_in_crash_buf_print + /* Load the crash buf address */ + mrs x0, tpidr_el3 + /* Store the rest of gp regs and print */ + stp x16, x17, [x0] + stp x18, x19, [x0, #REG_SIZE * 2] + stp x20, x21, [x0, #REG_SIZE * 4] + stp x22, x23, [x0, #REG_SIZE * 6] + bl size_controlled_print + /* Load the crash buf address */ + mrs x0, tpidr_el3 + stp x24, x25, [x0] + stp x26, x27, [x0, #REG_SIZE * 2] + stp x28, x29, [x0, #REG_SIZE * 4] + bl size_controlled_print + + /* Print the el3 sys registers */ + adr x6, el3_sys_regs + mrs x8, scr_el3 + mrs x9, sctlr_el3 + mrs x10, cptr_el3 + mrs x11, tcr_el3 + mrs x12, daif + mrs x13, mair_el3 + mrs x14, spsr_el3 + mrs x15, elr_el3 + bl str_in_crash_buf_print + mrs x8, ttbr0_el3 + mrs x9, esr_el3 + mrs x10, far_el3 + bl str_in_crash_buf_print + + /* Print the non el3 sys registers */ + adr x6, non_el3_sys_regs + mrs x8, spsr_el1 + mrs x9, elr_el1 + mrs x10, spsr_abt + mrs x11, spsr_und + mrs x12, spsr_irq + mrs x13, spsr_fiq + mrs x14, sctlr_el1 + mrs x15, actlr_el1 + bl str_in_crash_buf_print + mrs x8, cpacr_el1 + mrs x9, csselr_el1 + mrs x10, sp_el1 + mrs x11, esr_el1 + mrs x12, ttbr0_el1 + mrs x13, ttbr1_el1 + mrs x14, mair_el1 + mrs x15, amair_el1 + bl str_in_crash_buf_print + mrs x8, tcr_el1 + mrs x9, tpidr_el1 + mrs x10, tpidr_el0 + mrs x11, tpidrro_el0 + mrs x12, dacr32_el2 + mrs x13, ifsr32_el2 + mrs x14, par_el1 + mrs x15, mpidr_el1 + bl str_in_crash_buf_print + mrs x8, afsr0_el1 + mrs x9, afsr1_el1 + mrs x10, contextidr_el1 + mrs x11, vbar_el1 + mrs x12, cntp_ctl_el0 + mrs x13, cntp_cval_el0 + mrs x14, cntv_ctl_el0 + mrs x15, cntv_cval_el0 + bl str_in_crash_buf_print + mrs x8, cntkctl_el1 + mrs x9, fpexc32_el2 + mrs x10, sp_el0 + bl str_in_crash_buf_print + + /* Get the cpu specific registers to report */ + bl do_cpu_reg_dump + bl str_in_crash_buf_print + + /* Print the gic registers */ + plat_print_gic_regs + + /* Print the interconnect registers */ + plat_print_interconnect_regs + + /* Done reporting */ + b crash_panic +endfunc do_crash_reporting + +#else /* CRASH_REPORTING */ +func report_unhandled_exception +report_unhandled_interrupt: + b crash_panic +endfunc report_unhandled_exception +#endif /* CRASH_REPORING */ + + +func crash_panic + b crash_panic +endfunc crash_panic \ No newline at end of file diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/runtime_exceptions.S b/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/runtime_exceptions.S new file mode 100644 index 0000000..bbc7f1b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl31/aarch64/runtime_exceptions.S @@ -0,0 +1,539 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + + .globl runtime_exceptions + .globl el3_exit + + /* ----------------------------------------------------- + * Handle SMC exceptions separately from other sync. + * exceptions. + * ----------------------------------------------------- + */ + .macro handle_sync_exception + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + mrs x30, esr_el3 + ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH + + cmp x30, #EC_AARCH32_SMC + b.eq smc_handler32 + + cmp x30, #EC_AARCH64_SMC + b.eq smc_handler64 + + /* ----------------------------------------------------- + * The following code handles any synchronous exception + * that is not an SMC. + * ----------------------------------------------------- + */ + + bl report_unhandled_exception + .endm + + + /* ----------------------------------------------------- + * This macro handles FIQ or IRQ interrupts i.e. EL3, + * S-EL1 and NS interrupts. + * ----------------------------------------------------- + */ + .macro handle_interrupt_exception label + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + bl save_gp_registers + + /* + * Save the EL3 system registers needed to return from + * this exception. + */ + mrs x0, spsr_el3 + mrs x1, elr_el3 + stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] + + /* Switch to the runtime stack i.e. SP_EL0 */ + ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] + mov x20, sp + msr spsel, #0 + mov sp, x2 + + /* + * Find out whether this is a valid interrupt type. If the + * interrupt controller reports a spurious interrupt then + * return to where we came from. + */ + bl plat_ic_get_pending_interrupt_type + cmp x0, #INTR_TYPE_INVAL + b.eq interrupt_exit_\label + + /* + * Get the registered handler for this interrupt type. A + * NULL return value could be 'cause of the following + * conditions: + * + * a. An interrupt of a type was routed correctly but a + * handler for its type was not registered. + * + * b. An interrupt of a type was not routed correctly so + * a handler for its type was not registered. + * + * c. An interrupt of a type was routed correctly to EL3, + * but was deasserted before its pending state could + * be read. Another interrupt of a different type pended + * at the same time and its type was reported as pending + * instead. However, a handler for this type was not + * registered. + * + * a. and b. can only happen due to a programming error. + * The occurrence of c. could be beyond the control of + * Trusted Firmware. It makes sense to return from this + * exception instead of reporting an error. + */ + bl get_interrupt_type_handler + cbz x0, interrupt_exit_\label + mov x21, x0 + + mov x0, #INTR_ID_UNAVAILABLE +#if IMF_READ_INTERRUPT_ID + /* + * Read the id of the highest priority pending interrupt. If + * no interrupt is asserted then return to where we came from. + */ + mov x19, #INTR_ID_UNAVAILABLE + bl plat_ic_get_pending_interrupt_id + cmp x19, x0 + b.eq interrupt_exit_\label +#endif + + /* Set the current security state in the 'flags' parameter */ + mrs x2, scr_el3 + ubfx x1, x2, #0, #1 + + /* Restore the reference to the 'handle' i.e. SP_EL3 */ + mov x2, x20 + + /* x3 will point to a cookie (not used now) */ + mov x3, xzr + + /* Call the interrupt type handler */ + blr x21 + +interrupt_exit_\label: + /* Return from exception, possibly in a different security state */ + b el3_exit + + .endm + + + .macro save_x18_to_x29_sp_el0 + stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] + stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] + stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] + stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] + stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] + stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] + mrs x18, sp_el0 + str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] + .endm + + .section .vectors, "ax"; .align 11 + .align 7 +runtime_exceptions: + /* ----------------------------------------------------- + * Current EL with _sp_el0 : 0x0 - 0x200 + * ----------------------------------------------------- + */ +sync_exception_sp_el0: + /* ----------------------------------------------------- + * We don't expect any synchronous exceptions from EL3 + * ----------------------------------------------------- + */ + bl report_unhandled_exception + check_vector_size sync_exception_sp_el0 + + .align 7 + /* ----------------------------------------------------- + * EL3 code is non-reentrant. Any asynchronous exception + * is a serious error. Loop infinitely. + * ----------------------------------------------------- + */ +irq_sp_el0: + bl report_unhandled_interrupt + check_vector_size irq_sp_el0 + + .align 7 +fiq_sp_el0: + bl report_unhandled_interrupt + check_vector_size fiq_sp_el0 + + .align 7 +serror_sp_el0: + bl report_unhandled_exception + check_vector_size serror_sp_el0 + + /* ----------------------------------------------------- + * Current EL with SPx: 0x200 - 0x400 + * ----------------------------------------------------- + */ + .align 7 +sync_exception_sp_elx: + /* ----------------------------------------------------- + * This exception will trigger if anything went wrong + * during a previous exception entry or exit or while + * handling an earlier unexpected synchronous exception. + * There is a high probability that SP_EL3 is corrupted. + * ----------------------------------------------------- + */ + bl report_unhandled_exception + check_vector_size sync_exception_sp_elx + + .align 7 +irq_sp_elx: + bl report_unhandled_interrupt + check_vector_size irq_sp_elx + + .align 7 +fiq_sp_elx: + bl report_unhandled_interrupt + check_vector_size fiq_sp_elx + + .align 7 +serror_sp_elx: + bl report_unhandled_exception + check_vector_size serror_sp_elx + + /* ----------------------------------------------------- + * Lower EL using AArch64 : 0x400 - 0x600 + * ----------------------------------------------------- + */ + .align 7 +sync_exception_aarch64: + /* ----------------------------------------------------- + * This exception vector will be the entry point for + * SMCs and traps that are unhandled at lower ELs most + * commonly. SP_EL3 should point to a valid cpu context + * where the general purpose and system register state + * can be saved. + * ----------------------------------------------------- + */ + handle_sync_exception + check_vector_size sync_exception_aarch64 + + .align 7 + /* ----------------------------------------------------- + * Asynchronous exceptions from lower ELs are not + * currently supported. Report their occurrence. + * ----------------------------------------------------- + */ +irq_aarch64: + handle_interrupt_exception irq_aarch64 + check_vector_size irq_aarch64 + + .align 7 +fiq_aarch64: + handle_interrupt_exception fiq_aarch64 + check_vector_size fiq_aarch64 + + .align 7 +serror_aarch64: + bl report_unhandled_exception + check_vector_size serror_aarch64 + + /* ----------------------------------------------------- + * Lower EL using AArch32 : 0x600 - 0x800 + * ----------------------------------------------------- + */ + .align 7 +sync_exception_aarch32: + /* ----------------------------------------------------- + * This exception vector will be the entry point for + * SMCs and traps that are unhandled at lower ELs most + * commonly. SP_EL3 should point to a valid cpu context + * where the general purpose and system register state + * can be saved. + * ----------------------------------------------------- + */ + handle_sync_exception + check_vector_size sync_exception_aarch32 + + .align 7 + /* ----------------------------------------------------- + * Asynchronous exceptions from lower ELs are not + * currently supported. Report their occurrence. + * ----------------------------------------------------- + */ +irq_aarch32: + handle_interrupt_exception irq_aarch32 + check_vector_size irq_aarch32 + + .align 7 +fiq_aarch32: + handle_interrupt_exception fiq_aarch32 + check_vector_size fiq_aarch32 + + .align 7 +serror_aarch32: + bl report_unhandled_exception + check_vector_size serror_aarch32 + + .align 7 + + /* ----------------------------------------------------- + * The following code handles secure monitor calls. + * Depending upon the execution state from where the SMC + * has been invoked, it frees some general purpose + * registers to perform the remaining tasks. They + * involve finding the runtime service handler that is + * the target of the SMC & switching to runtime stacks + * (SP_EL0) before calling the handler. + * + * Note that x30 has been explicitly saved and can be + * used here + * ----------------------------------------------------- + */ +func smc_handler +smc_handler32: + /* Check whether aarch32 issued an SMC64 */ + tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited + + /* ----------------------------------------------------- + * Since we're are coming from aarch32, x8-x18 need to + * be saved as per SMC32 calling convention. If a lower + * EL in aarch64 is making an SMC32 call then it must + * have saved x8-x17 already therein. + * ----------------------------------------------------- + */ + stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] + stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] + stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] + stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] + stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] + + /* x4-x7, x18, sp_el0 are saved below */ + +smc_handler64: + /* ----------------------------------------------------- + * Populate the parameters for the SMC handler. We + * already have x0-x4 in place. x5 will point to a + * cookie (not used now). x6 will point to the context + * structure (SP_EL3) and x7 will contain flags we need + * to pass to the handler Hence save x5-x7. Note that x4 + * only needs to be preserved for AArch32 callers but we + * do it for AArch64 callers as well for convenience + * ----------------------------------------------------- + */ + stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] + + /* Save rest of the gpregs and sp_el0*/ + save_x18_to_x29_sp_el0 + + mov x5, xzr + mov x6, sp + + /* Get the unique owning entity number */ + ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH + ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH + orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH + + adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) + + /* Load descriptor index from array of indices */ + adr x14, rt_svc_descs_indices + ldrb w15, [x14, x16] + + /* ----------------------------------------------------- + * Restore the saved C runtime stack value which will + * become the new SP_EL0 i.e. EL3 runtime stack. It was + * saved in the 'cpu_context' structure prior to the last + * ERET from EL3. + * ----------------------------------------------------- + */ + ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] + + /* + * Any index greater than 127 is invalid. Check bit 7 for + * a valid index + */ + tbnz w15, 7, smc_unknown + + /* Switch to SP_EL0 */ + msr spsel, #0 + + /* ----------------------------------------------------- + * Get the descriptor using the index + * x11 = (base + off), x15 = index + * + * handler = (base + off) + (index << log2(size)) + * ----------------------------------------------------- + */ + lsl w10, w15, #RT_SVC_SIZE_LOG2 + ldr x15, [x11, w10, uxtw] + + /* ----------------------------------------------------- + * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there + * is a world switch during SMC handling. + * TODO: Revisit if all system registers can be saved + * later. + * ----------------------------------------------------- + */ + mrs x16, spsr_el3 + mrs x17, elr_el3 + mrs x18, scr_el3 + stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] + str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] + + /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ + bfi x7, x18, #0, #1 + + mov sp, x12 + + /* ----------------------------------------------------- + * Call the Secure Monitor Call handler and then drop + * directly into el3_exit() which will program any + * remaining architectural state prior to issuing the + * ERET to the desired lower EL. + * ----------------------------------------------------- + */ +#if DEBUG + cbz x15, rt_svc_fw_critical_error +#endif + blr x15 + + /* ----------------------------------------------------- + * This routine assumes that the SP_EL3 is pointing to + * a valid context structure from where the gp regs and + * other special registers can be retrieved. + * + * Keep it in the same section as smc_handler as this + * function uses a fall-through to el3_exit + * ----------------------------------------------------- + */ +el3_exit: ; .type el3_exit, %function + /* ----------------------------------------------------- + * Save the current SP_EL0 i.e. the EL3 runtime stack + * which will be used for handling the next SMC. Then + * switch to SP_EL3 + * ----------------------------------------------------- + */ + mov x17, sp + msr spsel, #1 + str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] + + /* ----------------------------------------------------- + * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET + * ----------------------------------------------------- + */ + ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] + ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] + msr scr_el3, x18 + msr spsr_el3, x16 + msr elr_el3, x17 + + /* Restore saved general purpose registers and return */ + b restore_gp_registers_eret + +smc_unknown: + /* + * Here we restore x4-x18 regardless of where we came from. AArch32 + * callers will find the registers contents unchanged, but AArch64 + * callers will find the registers modified (with stale earlier NS + * content). Either way, we aren't leaking any secure information + * through them + */ + mov w0, #SMC_UNK + b restore_gp_registers_callee_eret + +smc_prohibited: + ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + mov w0, #SMC_UNK + eret + +rt_svc_fw_critical_error: + msr spsel, #1 /* Switch to SP_ELx */ + bl report_unhandled_exception +endfunc smc_handler + + /* ----------------------------------------------------- + * The following functions are used to saved and restore + * all the general pupose registers. Ideally we would + * only save and restore the callee saved registers when + * a world switch occurs but that type of implementation + * is more complex. So currently we will always save and + * restore these registers on entry and exit of EL3. + * These are not macros to ensure their invocation fits + * within the 32 instructions per exception vector. + * ----------------------------------------------------- + */ +func save_gp_registers + stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] + stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] + stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] + stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] + stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] + stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] + save_x18_to_x29_sp_el0 + ret +endfunc save_gp_registers + +func restore_gp_registers_eret + ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + +restore_gp_registers_callee_eret: + ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] + ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] + ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] + ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] + ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] + ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] + ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] + ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] + ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] + ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] + ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] + ldp x30, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + msr sp_el0, x17 + ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] + eret +endfunc restore_gp_registers_eret diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl31/bl31.ld.S b/IPL/SDK/v3m/src/Dummy_BL33/bl31/bl31.ld.S new file mode 100644 index 0000000..47084fc --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl31/bl31.ld.S @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) +OUTPUT_ARCH(PLATFORM_LINKER_ARCH) +ENTRY(bl31_entrypoint) + + +MEMORY { + RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE +} + + +SECTIONS +{ + . = BL31_BASE; + ASSERT(. == ALIGN(4096), + "BL31_BASE address is not aligned on a page boundary.") + + ro . : { + __RO_START__ = .; + *bl31_entrypoint.o(.text*) +#if PLAT_rcar + . = NEXT(ALIGN_VERSION); + *rcar_common.o(.version*) +#endif + *(.text*) + *(.rodata*) + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __RT_SVC_DESCS_START__ = .; + KEEP(*(rt_svc_descs)) + __RT_SVC_DESCS_END__ = .; + + /* + * Ensure 8-byte alignment for cpu_ops so that its fields are also + * aligned. Also ensure cpu_ops inclusion. + */ + . = ALIGN(8); + __CPU_OPS_START__ = .; + KEEP(*(cpu_ops)) + __CPU_OPS_END__ = .; + + *(.vectors) + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as read-only, + * executable. No RW data from the next section must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __RO_END__ = .; + } >RAM + + ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, + "cpu_ops not defined for this platform.") + + /* + * Define a linker symbol to mark start of the RW memory area for this + * image. + */ + __RW_START__ = . ; + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + +#ifdef BL31_PROGBITS_LIMIT + ASSERT(. <= BL31_PROGBITS_LIMIT, "BL3-1 progbits has exceeded its limit.") +#endif + + stacks (NOLOAD) : { + __STACKS_START__ = .; + *(tzfw_normal_stacks) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss (NOLOAD) : ALIGN(16) { + __BSS_START__ = .; + *(.bss*) + *(COMMON) +#if !USE_COHERENT_MEM + /* + * Bakery locks are stored in normal .bss memory + * + * Each lock's data is spread across multiple cache lines, one per CPU, + * but multiple locks can share the same cache line. + * The compiler will allocate enough memory for one CPU's bakery locks, + * the remaining cache lines are allocated by the linker script + */ + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __BAKERY_LOCK_START__ = .; + *(bakery_lock) + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); + . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); + __BAKERY_LOCK_END__ = .; +#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE + ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, + "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); +#endif +#endif + __BSS_END__ = .; + } >RAM + + /* + * The xlat_table section is for full, aligned page tables (4K). + * Removing them from .bss avoids forcing 4K alignment on + * the .bss section and eliminates the unecessary zero init + */ + xlat_table (NOLOAD) : { + *(xlat_table) + } >RAM + +#if USE_COHERENT_MEM + /* + * The base address of the coherent memory section must be page-aligned (4K) + * to guarantee that the coherent data are stored on their own pages and + * are not mixed with normal data. This is required to set up the correct + * memory attributes for the coherent data page tables. + */ + coherent_ram (NOLOAD) : ALIGN(4096) { + __COHERENT_RAM_START__ = .; + /* + * Bakery locks are stored in coherent memory + * + * Each lock's data is contiguous and fully allocated by the compiler + */ + *(bakery_lock) + *(tzfw_coherent_mem) + __COHERENT_RAM_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked + * as device memory. No other unexpected data must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __COHERENT_RAM_END__ = .; + } >RAM +#endif + + /* + * Define a linker symbol to mark end of the RW memory area for this + * image. + */ + __RW_END__ = .; + __BL31_END__ = .; + + __BSS_SIZE__ = SIZEOF(.bss); +#if USE_COHERENT_MEM + __COHERENT_RAM_UNALIGNED_SIZE__ = + __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; +#endif + + ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.") +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl31/bl31.mk b/IPL/SDK/v3m/src/Dummy_BL33/bl31/bl31.mk new file mode 100644 index 0000000..04e1542 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl31/bl31.mk @@ -0,0 +1,77 @@ +# +# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +BL31_SOURCES += bl31/bl31_main.c \ + bl31/context_mgmt.c \ + bl31/cpu_data_array.c \ + bl31/runtime_svc.c \ + bl31/interrupt_mgmt.c \ + bl31/aarch64/bl31_arch_setup.c \ + bl31/aarch64/bl31_entrypoint.S \ + bl31/aarch64/context.S \ + bl31/aarch64/cpu_data.S \ + bl31/aarch64/runtime_exceptions.S \ + bl31/aarch64/crash_reporting.S \ + lib/cpus/aarch64/cpu_helpers.S \ + lib/locks/exclusive/spinlock.S \ + services/std_svc/std_svc_setup.c \ + services/std_svc/psci/psci_off.c \ + services/std_svc/psci/psci_on.c \ + services/std_svc/psci/psci_suspend.c \ + services/std_svc/psci/psci_common.c \ + services/std_svc/psci/psci_entry.S \ + services/std_svc/psci/psci_helpers.S \ + services/std_svc/psci/psci_main.c \ + services/std_svc/psci/psci_setup.c \ + services/std_svc/psci/psci_system_off.c + +ifeq (${USE_COHERENT_MEM}, 1) +BL31_SOURCES += lib/locks/bakery/bakery_lock_coherent.c +else +BL31_SOURCES += lib/locks/bakery/bakery_lock_normal.c +endif + +BL31_LINKERFILE := bl31/bl31.ld.S + +# Flag used by the generic interrupt management framework to determine if +# upon the assertion of an interrupt, it should pass the interrupt id or not +IMF_READ_INTERRUPT_ID := 0 + +$(eval $(call assert_boolean,IMF_READ_INTERRUPT_ID)) +$(eval $(call add_define,IMF_READ_INTERRUPT_ID)) + +# Flag used to inidicate if Crash reporting via console should be included +# in BL3-1. This defaults to being present in DEBUG builds only +ifndef CRASH_REPORTING +CRASH_REPORTING := $(DEBUG) +endif + +$(eval $(call assert_boolean,CRASH_REPORTING)) +$(eval $(call add_define,CRASH_REPORTING)) diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl31/bl31_main.c b/IPL/SDK/v3m/src/Dummy_BL33/bl31/bl31_main.c new file mode 100644 index 0000000..a244a5c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl31/bl31_main.c @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * This function pointer is used to initialise the BL32 image. It's initialized + * by SPD calling bl31_register_bl32_init after setting up all things necessary + * for SP execution. In cases where both SPD and SP are absent, or when SPD + * finds it impossible to execute SP, this pointer is left as NULL + ******************************************************************************/ +static int32_t (*bl32_init)(void); + +/******************************************************************************* + * Variable to indicate whether next image to execute after BL31 is BL33 + * (non-secure & default) or BL32 (secure). + ******************************************************************************/ +static uint32_t next_image_type = NON_SECURE; + +/******************************************************************************* + * Simple function to initialise all BL31 helper libraries. + ******************************************************************************/ +void bl31_lib_init(void) +{ + cm_init(); +} + +/******************************************************************************* + * BL31 is responsible for setting up the runtime services for the primary cpu + * before passing control to the bootloader or an Operating System. This + * function calls runtime_svc_init() which initializes all registered runtime + * services. The run time services would setup enough context for the core to + * swtich to the next exception level. When this function returns, the core will + * switch to the programmed exception level via. an ERET. + ******************************************************************************/ +void bl31_main(void) +{ + NOTICE("BL3-1: %s\n", version_string); + NOTICE("BL3-1: %s\n", build_message); + + /* Perform remaining generic architectural setup from EL3 */ + bl31_arch_setup(); + + /* Perform platform setup in BL1 */ + bl31_platform_setup(); + + /* Initialise helper libraries */ + bl31_lib_init(); + + /* Initialize the runtime services e.g. psci */ + INFO("BL3-1: Initializing runtime services\n"); + runtime_svc_init(); + + /* + * All the cold boot actions on the primary cpu are done. We now need to + * decide which is the next image (BL32 or BL33) and how to execute it. + * If the SPD runtime service is present, it would want to pass control + * to BL32 first in S-EL1. In that case, SPD would have registered a + * function to intialize bl32 where it takes responsibility of entering + * S-EL1 and returning control back to bl31_main. Once this is done we + * can prepare entry into BL33 as normal. + */ + + /* + * If SPD had registerd an init hook, invoke it. + */ + if (bl32_init) { + INFO("BL3-1: Initializing BL3-2\n"); + (*bl32_init)(); + } + /* + * We are ready to enter the next EL. Prepare entry into the image + * corresponding to the desired security state after the next ERET. + */ + bl31_prepare_next_image_entry(); +} + +/******************************************************************************* + * Accessor functions to help runtime services decide which image should be + * executed after BL31. This is BL33 or the non-secure bootloader image by + * default but the Secure payload dispatcher could override this by requesting + * an entry into BL32 (Secure payload) first. If it does so then it should use + * the same API to program an entry into BL33 once BL32 initialisation is + * complete. + ******************************************************************************/ +void bl31_set_next_image_type(uint32_t security_state) +{ + assert(sec_state_is_valid(security_state)); + next_image_type = security_state; +} + +uint32_t bl31_get_next_image_type(void) +{ + return next_image_type; +} + +/******************************************************************************* + * This function programs EL3 registers and performs other setup to enable entry + * into the next image after BL31 at the next ERET. + ******************************************************************************/ +void bl31_prepare_next_image_entry(void) +{ + entry_point_info_t *next_image_info; + uint32_t image_type; + + /* Determine which image to execute next */ + image_type = bl31_get_next_image_type(); + + /* Program EL3 registers to enable entry into the next EL */ + next_image_info = bl31_plat_get_next_image_ep_info(image_type); + assert(next_image_info); + assert(image_type == GET_SECURITY_STATE(next_image_info->h.attr)); + + INFO("BL3-1: Preparing for EL3 exit to %s world\n", + (image_type == SECURE) ? "secure" : "normal"); + INFO("BL3-1: Next image address = 0x%llx\n", + (unsigned long long) next_image_info->pc); + INFO("BL3-1: Next image spsr = 0x%x\n", next_image_info->spsr); + cm_init_my_context(next_image_info); + cm_prepare_el3_exit(image_type); +} + +/******************************************************************************* + * This function initializes the pointer to BL32 init function. This is expected + * to be called by the SPD after it finishes all its initialization + ******************************************************************************/ +void bl31_register_bl32_init(int32_t (*func)(void)) +{ + bl32_init = func; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl31/context_mgmt.c b/IPL/SDK/v3m/src/Dummy_BL33/bl31/context_mgmt.c new file mode 100644 index 0000000..a0fd1b6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl31/context_mgmt.c @@ -0,0 +1,456 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/******************************************************************************* + * Context management library initialisation routine. This library is used by + * runtime services to share pointers to 'cpu_context' structures for the secure + * and non-secure states. Management of the structures and their associated + * memory is not done by the context management library e.g. the PSCI service + * manages the cpu context used for entry from and exit to the non-secure state. + * The Secure payload dispatcher service manages the context(s) corresponding to + * the secure state. It also uses this library to get access to the non-secure + * state cpu context pointers. + * Lastly, this library provides the api to make SP_EL3 point to the cpu context + * which will used for programming an entry into a lower EL. The same context + * will used to save state upon exception entry from that EL. + ******************************************************************************/ +void cm_init(void) +{ + /* + * The context management library has only global data to intialize, but + * that will be done when the BSS is zeroed out + */ +} + +/******************************************************************************* + * This function returns a pointer to the most recent 'cpu_context' structure + * for the CPU identified by `cpu_idx` that was set as the context for the + * specified security state. NULL is returned if no such structure has been + * specified. + ******************************************************************************/ +void *cm_get_context_by_index(unsigned int cpu_idx, + unsigned int security_state) +{ + assert(sec_state_is_valid(security_state)); + + return get_cpu_data_by_index(cpu_idx, cpu_context[security_state]); +} + +/******************************************************************************* + * This function sets the pointer to the current 'cpu_context' structure for the + * specified security state for the CPU identified by CPU index. + ******************************************************************************/ +void cm_set_context_by_index(unsigned int cpu_idx, void *context, + unsigned int security_state) +{ + assert(sec_state_is_valid(security_state)); + + set_cpu_data_by_index(cpu_idx, cpu_context[security_state], context); +} + +/******************************************************************************* + * This function returns a pointer to the most recent 'cpu_context' structure + * for the CPU identified by MPIDR that was set as the context for the specified + * security state. NULL is returned if no such structure has been specified. + ******************************************************************************/ +void *cm_get_context_by_mpidr(uint64_t mpidr, uint32_t security_state) +{ + assert(sec_state_is_valid(security_state)); + + return cm_get_context_by_index(platform_get_core_pos(mpidr), security_state); +} + +/******************************************************************************* + * This function sets the pointer to the current 'cpu_context' structure for the + * specified security state for the CPU identified by MPIDR + ******************************************************************************/ +void cm_set_context_by_mpidr(uint64_t mpidr, void *context, uint32_t security_state) +{ + assert(sec_state_is_valid(security_state)); + + cm_set_context_by_index(platform_get_core_pos(mpidr), + context, security_state); +} + +/******************************************************************************* + * This function is used to program the context that's used for exception + * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for + * the required security state + ******************************************************************************/ +static inline void cm_set_next_context(void *context) +{ +#if DEBUG + uint64_t sp_mode; + + /* + * Check that this function is called with SP_EL0 as the stack + * pointer + */ + __asm__ volatile("mrs %0, SPSel\n" + : "=r" (sp_mode)); + + assert(sp_mode == MODE_SP_EL0); +#endif + + __asm__ volatile("msr spsel, #1\n" + "mov sp, %0\n" + "msr spsel, #0\n" + : : "r" (context)); +} + +/******************************************************************************* + * The following function initializes the cpu_context 'ctx' for + * first use, and sets the initial entrypoint state as specified by the + * entry_point_info structure. + * + * The security state to initialize is determined by the SECURE attribute + * of the entry_point_info. The function returns a pointer to the initialized + * context and sets this as the next context to return to. + * + * The EE and ST attributes are used to configure the endianess and secure + * timer availability for the new execution context. + * + * To prepare the register state for entry call cm_prepare_el3_exit() and + * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to + * cm_e1_sysreg_context_restore(). + ******************************************************************************/ +static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) +{ + unsigned int security_state; + uint32_t scr_el3; + el3_state_t *state; + gp_regs_t *gp_regs; + unsigned long sctlr_elx; + + assert(ctx); + + security_state = GET_SECURITY_STATE(ep->h.attr); + + /* Clear any residual register values from the context */ + memset(ctx, 0, sizeof(*ctx)); + + /* + * Base the context SCR on the current value, adjust for entry point + * specific requirements and set trap bits from the IMF + * TODO: provide the base/global SCR bits using another mechanism? + */ + scr_el3 = read_scr(); + scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | + SCR_ST_BIT | SCR_HCE_BIT); + + if (security_state != SECURE) + scr_el3 |= SCR_NS_BIT; + + if (GET_RW(ep->spsr) == MODE_RW_64) + scr_el3 |= SCR_RW_BIT; + + if (EP_GET_ST(ep->h.attr)) + scr_el3 |= SCR_ST_BIT; + + scr_el3 |= get_scr_el3_from_routing_model(security_state); + + /* + * Set up SCTLR_ELx for the target exception level: + * EE bit is taken from the entrpoint attributes + * M, C and I bits must be zero (as required by PSCI specification) + * + * The target exception level is based on the spsr mode requested. + * If execution is requested to EL2 or hyp mode, HVC is enabled + * via SCR_EL3.HCE. + * + * Always compute the SCTLR_EL1 value and save in the cpu_context + * - the EL2 registers are set up by cm_preapre_ns_entry() as they + * are not part of the stored cpu_context + * + * TODO: In debug builds the spsr should be validated and checked + * against the CPU support, security state, endianess and pc + */ + sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; + if (GET_RW(ep->spsr) == MODE_RW_64) + sctlr_elx |= SCTLR_EL1_RES1; + else + sctlr_elx |= SCTLR_AARCH32_EL1_RES1; + write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); + + if ((GET_RW(ep->spsr) == MODE_RW_64 + && GET_EL(ep->spsr) == MODE_EL2) + || (GET_RW(ep->spsr) != MODE_RW_64 + && GET_M32(ep->spsr) == MODE32_hyp)) { + scr_el3 |= SCR_HCE_BIT; + } + + /* Populate EL3 state so that we've the right context before doing ERET */ + state = get_el3state_ctx(ctx); + write_ctx_reg(state, CTX_SCR_EL3, scr_el3); + write_ctx_reg(state, CTX_ELR_EL3, ep->pc); + write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); + + /* + * Store the X0-X7 value from the entrypoint into the context + * Use memcpy as we are in control of the layout of the structures + */ + gp_regs = get_gpregs_ctx(ctx); + memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); +} + +/******************************************************************************* + * The following function initializes the cpu_context for a CPU specified by + * its `cpu_idx` for first use, and sets the initial entrypoint state as + * specified by the entry_point_info structure. + ******************************************************************************/ +void cm_init_context_by_index(unsigned int cpu_idx, + const entry_point_info_t *ep) +{ + cpu_context_t *ctx; + ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); + cm_init_context_common(ctx, ep); +} + +/******************************************************************************* + * The following function initializes the cpu_context for the current CPU + * for first use, and sets the initial entrypoint state as specified by the + * entry_point_info structure. + ******************************************************************************/ +void cm_init_my_context(const entry_point_info_t *ep) +{ + cpu_context_t *ctx; + ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); + cm_init_context_common(ctx, ep); +} + +/******************************************************************************* + * The following function provides a compatibility function for SPDs using the + * existing cm library routines. This function is expected to be invoked for + * initializing the cpu_context for the CPU specified by MPIDR for first use. + ******************************************************************************/ +void cm_init_context(unsigned long mpidr, const entry_point_info_t *ep) +{ + if ((mpidr & MPIDR_AFFINITY_MASK) == + (read_mpidr_el1() & MPIDR_AFFINITY_MASK)) + cm_init_my_context(ep); + else + cm_init_context_by_index(platform_get_core_pos(mpidr), ep); +} + +/******************************************************************************* + * Prepare the CPU system registers for first entry into secure or normal world + * + * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized + * If execution is requested to non-secure EL1 or svc mode, and the CPU supports + * EL2 then EL2 is disabled by configuring all necessary EL2 registers. + * For all entries, the EL1 registers are initialized from the cpu_context + ******************************************************************************/ +void cm_prepare_el3_exit(uint32_t security_state) +{ + uint32_t sctlr_elx, scr_el3, cptr_el2; + cpu_context_t *ctx = cm_get_context(security_state); + + assert(ctx); + + if (security_state == NON_SECURE) { + scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); + if (scr_el3 & SCR_HCE_BIT) { + /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ + sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), + CTX_SCTLR_EL1); + sctlr_elx &= ~SCTLR_EE_BIT; + sctlr_elx |= SCTLR_EL2_RES1; + write_sctlr_el2(sctlr_elx); + } else if (read_id_aa64pfr0_el1() & + (ID_AA64PFR0_ELX_MASK << ID_AA64PFR0_EL2_SHIFT)) { + /* EL2 present but unused, need to disable safely */ + + /* HCR_EL2 = 0, except RW bit set to match SCR_EL3 */ + write_hcr_el2((scr_el3 & SCR_RW_BIT) ? HCR_RW_BIT : 0); + + /* SCTLR_EL2 : can be ignored when bypassing */ + + /* CPTR_EL2 : disable all traps TCPAC, TTA, TFP */ + cptr_el2 = read_cptr_el2(); + cptr_el2 &= ~(TCPAC_BIT | TTA_BIT | TFP_BIT); + write_cptr_el2(cptr_el2); + + /* Enable EL1 access to timer */ + write_cnthctl_el2(EL1PCEN_BIT | EL1PCTEN_BIT); + + /* Reset CNTVOFF_EL2 */ + write_cntvoff_el2(0); + + /* Set VPIDR, VMPIDR to match MIDR, MPIDR */ + write_vpidr_el2(read_midr_el1()); + write_vmpidr_el2(read_mpidr_el1()); + } + } + + el1_sysregs_context_restore(get_sysregs_ctx(ctx)); + + cm_set_next_context(ctx); +} + +/******************************************************************************* + * The next four functions are used by runtime services to save and restore + * EL1 context on the 'cpu_context' structure for the specified security + * state. + ******************************************************************************/ +void cm_el1_sysregs_context_save(uint32_t security_state) +{ + cpu_context_t *ctx; + + ctx = cm_get_context(security_state); + assert(ctx); + + el1_sysregs_context_save(get_sysregs_ctx(ctx)); +} + +void cm_el1_sysregs_context_restore(uint32_t security_state) +{ + cpu_context_t *ctx; + + ctx = cm_get_context(security_state); + assert(ctx); + + el1_sysregs_context_restore(get_sysregs_ctx(ctx)); +} + +/******************************************************************************* + * This function populates ELR_EL3 member of 'cpu_context' pertaining to the + * given security state with the given entrypoint + ******************************************************************************/ +void cm_set_elr_el3(uint32_t security_state, uint64_t entrypoint) +{ + cpu_context_t *ctx; + el3_state_t *state; + + ctx = cm_get_context(security_state); + assert(ctx); + + /* Populate EL3 state so that ERET jumps to the correct entry */ + state = get_el3state_ctx(ctx); + write_ctx_reg(state, CTX_ELR_EL3, entrypoint); +} + +/******************************************************************************* + * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' + * pertaining to the given security state + ******************************************************************************/ +void cm_set_elr_spsr_el3(uint32_t security_state, + uint64_t entrypoint, uint32_t spsr) +{ + cpu_context_t *ctx; + el3_state_t *state; + + ctx = cm_get_context(security_state); + assert(ctx); + + /* Populate EL3 state so that ERET jumps to the correct entry */ + state = get_el3state_ctx(ctx); + write_ctx_reg(state, CTX_ELR_EL3, entrypoint); + write_ctx_reg(state, CTX_SPSR_EL3, spsr); +} + +/******************************************************************************* + * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' + * pertaining to the given security state using the value and bit position + * specified in the parameters. It preserves all other bits. + ******************************************************************************/ +void cm_write_scr_el3_bit(uint32_t security_state, + uint32_t bit_pos, + uint32_t value) +{ + cpu_context_t *ctx; + el3_state_t *state; + uint32_t scr_el3; + + ctx = cm_get_context(security_state); + assert(ctx); + + /* Ensure that the bit position is a valid one */ + assert((1 << bit_pos) & SCR_VALID_BIT_MASK); + + /* Ensure that the 'value' is only a bit wide */ + assert(value <= 1); + + /* + * Get the SCR_EL3 value from the cpu context, clear the desired bit + * and set it to its new value. + */ + state = get_el3state_ctx(ctx); + scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); + scr_el3 &= ~(1 << bit_pos); + scr_el3 |= value << bit_pos; + write_ctx_reg(state, CTX_SCR_EL3, scr_el3); +} + +/******************************************************************************* + * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the + * given security state. + ******************************************************************************/ +uint32_t cm_get_scr_el3(uint32_t security_state) +{ + cpu_context_t *ctx; + el3_state_t *state; + + ctx = cm_get_context(security_state); + assert(ctx); + + /* Populate EL3 state so that ERET jumps to the correct entry */ + state = get_el3state_ctx(ctx); + return read_ctx_reg(state, CTX_SCR_EL3); +} + +/******************************************************************************* + * This function is used to program the context that's used for exception + * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for + * the required security state + ******************************************************************************/ +void cm_set_next_eret_context(uint32_t security_state) +{ + cpu_context_t *ctx; + + ctx = cm_get_context(security_state); + assert(ctx); + + cm_set_next_context(ctx); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl31/cpu_data_array.c b/IPL/SDK/v3m/src/Dummy_BL33/bl31/cpu_data_array.c new file mode 100644 index 0000000..4cba118 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl31/cpu_data_array.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/* The per_cpu_ptr_cache_t space allocation */ +cpu_data_t percpu_data[PLATFORM_CORE_COUNT]; diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl31/interrupt_mgmt.c b/IPL/SDK/v3m/src/Dummy_BL33/bl31/interrupt_mgmt.c new file mode 100644 index 0000000..5478902 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl31/interrupt_mgmt.c @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Local structure and corresponding array to keep track of the state of the + * registered interrupt handlers for each interrupt type. + * The field descriptions are: + * + * 'flags' : Bit[0], Routing model for this interrupt type when execution is + * not in EL3 in the secure state. '1' implies that this + * interrupt will be routed to EL3. '0' implies that this + * interrupt will be routed to the current exception level. + * + * Bit[1], Routing model for this interrupt type when execution is + * not in EL3 in the non-secure state. '1' implies that this + * interrupt will be routed to EL3. '0' implies that this + * interrupt will be routed to the current exception level. + * + * All other bits are reserved and SBZ. + * + * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the + * value of the SCR_EL3.IRQ or FIQ bit for each security state. + * There are two instances of this field corresponding to the + * two security states. + ******************************************************************************/ +typedef struct intr_type_desc { + interrupt_type_handler_t handler; + uint32_t flags; + uint32_t scr_el3[2]; +} intr_type_desc_t; + +static intr_type_desc_t intr_type_descs[MAX_INTR_TYPES]; + +/******************************************************************************* + * This function validates the interrupt type. EL3 interrupts are currently not + * supported. + ******************************************************************************/ +static int32_t validate_interrupt_type(uint32_t type) +{ + if (type == INTR_TYPE_EL3) + return -ENOTSUP; + + if (type != INTR_TYPE_S_EL1 && type != INTR_TYPE_NS) + return -EINVAL; + + return 0; +} + +/******************************************************************************* +* This function validates the routing model for this type of interrupt + ******************************************************************************/ +static int32_t validate_routing_model(uint32_t type, uint32_t flags) +{ + flags >>= INTR_RM_FLAGS_SHIFT; + flags &= INTR_RM_FLAGS_MASK; + + if (type == INTR_TYPE_S_EL1) + return validate_sel1_interrupt_rm(flags); + + if (type == INTR_TYPE_NS) + return validate_ns_interrupt_rm(flags); + + return -EINVAL; +} + +/******************************************************************************* + * This function returns the cached copy of the SCR_EL3 which contains the + * routing model (expressed through the IRQ and FIQ bits) for a security state + * which was stored through a call to 'set_routing_model()' earlier. + ******************************************************************************/ +uint32_t get_scr_el3_from_routing_model(uint32_t security_state) +{ + uint32_t scr_el3; + + assert(sec_state_is_valid(security_state)); + scr_el3 = intr_type_descs[INTR_TYPE_NS].scr_el3[security_state]; + scr_el3 |= intr_type_descs[INTR_TYPE_S_EL1].scr_el3[security_state]; + scr_el3 |= intr_type_descs[INTR_TYPE_EL3].scr_el3[security_state]; + return scr_el3; +} + +/******************************************************************************* + * This function uses the 'interrupt_type_flags' parameter to obtain the value + * of the trap bit (IRQ/FIQ) in the SCR_EL3 for a security state for this + * interrupt type. It uses it to update the SCR_EL3 in the cpu context and the + * 'intr_type_desc' for that security state. + ******************************************************************************/ +static void set_scr_el3_from_rm(uint32_t type, + uint32_t interrupt_type_flags, + uint32_t security_state) +{ + uint32_t flag, bit_pos; + + flag = get_interrupt_rm_flag(interrupt_type_flags, security_state); + bit_pos = plat_interrupt_type_to_line(type, security_state); + intr_type_descs[type].scr_el3[security_state] = flag << bit_pos; + cm_write_scr_el3_bit(security_state, bit_pos, flag); +} + +/******************************************************************************* + * This function validates the routing model specified in the 'flags' and + * updates internal data structures to reflect the new routing model. It also + * updates the copy of SCR_EL3 for each security state with the new routing + * model in the 'cpu_context' structure for this cpu. + ******************************************************************************/ +int32_t set_routing_model(uint32_t type, uint32_t flags) +{ + int32_t rc; + + rc = validate_interrupt_type(type); + if (rc) + return rc; + + rc = validate_routing_model(type, flags); + if (rc) + return rc; + + /* Update the routing model in internal data structures */ + intr_type_descs[type].flags = flags; + set_scr_el3_from_rm(type, flags, SECURE); + set_scr_el3_from_rm(type, flags, NON_SECURE); + + return 0; +} + +/****************************************************************************** + * This function disables the routing model of interrupt 'type' from the + * specified 'security_state' on the local core. The disable is in effect + * till the core powers down or till the next enable for that interrupt + * type. + *****************************************************************************/ +int disable_intr_rm_local(uint32_t type, uint32_t security_state) +{ + uint32_t bit_pos, flag; + + assert(intr_type_descs[type].handler); + + flag = get_interrupt_rm_flag(INTR_DEFAULT_RM, security_state); + + bit_pos = plat_interrupt_type_to_line(type, security_state); + cm_write_scr_el3_bit(security_state, bit_pos, flag); + + return 0; +} + +/****************************************************************************** + * This function enables the routing model of interrupt 'type' from the + * specified 'security_state' on the local core. + *****************************************************************************/ +int enable_intr_rm_local(uint32_t type, uint32_t security_state) +{ + uint32_t bit_pos, flag; + + assert(intr_type_descs[type].handler); + + flag = get_interrupt_rm_flag(intr_type_descs[type].flags, + security_state); + + bit_pos = plat_interrupt_type_to_line(type, security_state); + cm_write_scr_el3_bit(security_state, bit_pos, flag); + + return 0; +} + +/******************************************************************************* + * This function registers a handler for the 'type' of interrupt specified. It + * also validates the routing model specified in the 'flags' for this type of + * interrupt. + ******************************************************************************/ +int32_t register_interrupt_type_handler(uint32_t type, + interrupt_type_handler_t handler, + uint32_t flags) +{ + int32_t rc; + + /* Validate the 'handler' parameter */ + if (!handler) + return -EINVAL; + + /* Validate the 'flags' parameter */ + if (flags & INTR_TYPE_FLAGS_MASK) + return -EINVAL; + + /* Check if a handler has already been registered */ + if (intr_type_descs[type].handler) + return -EALREADY; + + rc = set_routing_model(type, flags); + if (rc) + return rc; + + /* Save the handler */ + intr_type_descs[type].handler = handler; + + return 0; +} + +/******************************************************************************* + * This function is called when an interrupt is generated and returns the + * handler for the interrupt type (if registered). It returns NULL if the + * interrupt type is not supported or its handler has not been registered. + ******************************************************************************/ +interrupt_type_handler_t get_interrupt_type_handler(uint32_t type) +{ + if (validate_interrupt_type(type)) + return NULL; + + return intr_type_descs[type].handler; +} + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl31/runtime_svc.c b/IPL/SDK/v3m/src/Dummy_BL33/bl31/runtime_svc.c new file mode 100644 index 0000000..fd64c82 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl31/runtime_svc.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +/******************************************************************************* + * The 'rt_svc_descs' array holds the runtime service descriptors exported by + * services by placing them in the 'rt_svc_descs' linker section. + * The 'rt_svc_descs_indices' array holds the index of a descriptor in the + * 'rt_svc_descs' array. When an SMC arrives, the OEN[29:24] bits and the call + * type[31] bit in the function id are combined to get an index into the + * 'rt_svc_descs_indices' array. This gives the index of the descriptor in the + * 'rt_svc_descs' array which contains the SMC handler. + ******************************************************************************/ +#define RT_SVC_DESCS_START ((uint64_t) (&__RT_SVC_DESCS_START__)) +#define RT_SVC_DESCS_END ((uint64_t) (&__RT_SVC_DESCS_END__)) +uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; +static rt_svc_desc_t *rt_svc_descs; + +/******************************************************************************* + * Simple routine to sanity check a runtime service descriptor before using it + ******************************************************************************/ +static int32_t validate_rt_svc_desc(rt_svc_desc_t *desc) +{ + if (desc == NULL) + return -EINVAL; + + if (desc->start_oen > desc->end_oen) + return -EINVAL; + + if (desc->end_oen >= OEN_LIMIT) + return -EINVAL; + + if (desc->call_type != SMC_TYPE_FAST && desc->call_type != SMC_TYPE_STD) + return -EINVAL; + + /* A runtime service having no init or handle function doesn't make sense */ + if (desc->init == NULL && desc->handle == NULL) + return -EINVAL; + + return 0; +} + +/******************************************************************************* + * This function calls the initialisation routine in the descriptor exported by + * a runtime service. Once a descriptor has been validated, its start & end + * owning entity numbers and the call type are combined to form a unique oen. + * The unique oen is used as an index into the 'rt_svc_descs_indices' array. + * The index of the runtime service descriptor is stored at this index. + ******************************************************************************/ +void runtime_svc_init(void) +{ + int32_t rc = 0; + uint32_t index, start_idx, end_idx; + uint64_t rt_svc_descs_num; + + /* If no runtime services are implemented then simply bail out */ + rt_svc_descs_num = RT_SVC_DESCS_END - RT_SVC_DESCS_START; + rt_svc_descs_num /= sizeof(rt_svc_desc_t); + if (rt_svc_descs_num == 0) + return; + + /* Initialise internal variables to invalid state */ + memset(rt_svc_descs_indices, -1, sizeof(rt_svc_descs_indices)); + + rt_svc_descs = (rt_svc_desc_t *) RT_SVC_DESCS_START; + for (index = 0; index < rt_svc_descs_num; index++) { + + /* + * An invalid descriptor is an error condition since it is + * difficult to predict the system behaviour in the absence + * of this service. + */ + rc = validate_rt_svc_desc(&rt_svc_descs[index]); + if (rc) { + ERROR("Invalid runtime service descriptor 0x%lx (%s)\n", + (uintptr_t) &rt_svc_descs[index], + rt_svc_descs[index].name); + goto error; + } + + /* + * The runtime service may have seperate rt_svc_desc_t + * for its fast smc and standard smc. Since the service itself + * need to be initialized only once, only one of them will have + * an initialisation routine defined. Call the initialisation + * routine for this runtime service, if it is defined. + */ + if (rt_svc_descs[index].init) { + rc = rt_svc_descs[index].init(); + if (rc) { + ERROR("Error initializing runtime service %s\n", + rt_svc_descs[index].name); + continue; + } + } + + /* + * Fill the indices corresponding to the start and end + * owning entity numbers with the index of the + * descriptor which will handle the SMCs for this owning + * entity range. + */ + start_idx = get_unique_oen(rt_svc_descs[index].start_oen, + rt_svc_descs[index].call_type); + end_idx = get_unique_oen(rt_svc_descs[index].end_oen, + rt_svc_descs[index].call_type); + + for (; start_idx <= end_idx; start_idx++) + rt_svc_descs_indices[start_idx] = index; + } + + return; +error: + panic(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/aarch64/tsp_entrypoint.S b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/aarch64/tsp_entrypoint.S new file mode 100644 index 0000000..9732ff2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/aarch64/tsp_entrypoint.S @@ -0,0 +1,424 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "../tsp_private.h" + + + .globl tsp_entrypoint + .globl tsp_vector_table + + + + /* --------------------------------------------- + * Populate the params in x0-x7 from the pointer + * to the smc args structure in x0. + * --------------------------------------------- + */ + .macro restore_args_call_smc + ldp x6, x7, [x0, #TSP_ARG6] + ldp x4, x5, [x0, #TSP_ARG4] + ldp x2, x3, [x0, #TSP_ARG2] + ldp x0, x1, [x0, #TSP_ARG0] + smc #0 + .endm + + .macro save_eret_context reg1 reg2 + mrs \reg1, elr_el1 + mrs \reg2, spsr_el1 + stp \reg1, \reg2, [sp, #-0x10]! + stp x30, x18, [sp, #-0x10]! + .endm + + .macro restore_eret_context reg1 reg2 + ldp x30, x18, [sp], #0x10 + ldp \reg1, \reg2, [sp], #0x10 + msr elr_el1, \reg1 + msr spsr_el1, \reg2 + .endm + + .section .text, "ax" + .align 3 + +func tsp_entrypoint + + /* --------------------------------------------- + * Set the exception vector to something sane. + * --------------------------------------------- + */ + adr x0, tsp_exceptions + msr vbar_el1, x0 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT + + /* --------------------------------------------- + * Enable the instruction cache, stack pointer + * and data access alignment checks + * --------------------------------------------- + */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el1 + orr x0, x0, x1 + msr sctlr_el1, x0 + isb + + /* --------------------------------------------- + * Invalidate the RW memory used by the BL32 + * image. This includes the data and NOBITS + * sections. This is done to safeguard against + * possible corruption of this memory by dirty + * cache lines in a system cache as a result of + * use by an earlier boot loader stage. + * --------------------------------------------- + */ + adr x0, __RW_START__ + adr x1, __RW_END__ + sub x1, x1, x0 + bl inv_dcache_range + + /* --------------------------------------------- + * Zero out NOBITS sections. There are 2 of them: + * - the .bss section; + * - the coherent memory section. + * --------------------------------------------- + */ + ldr x0, =__BSS_START__ + ldr x1, =__BSS_SIZE__ + bl zeromem16 + +#if USE_COHERENT_MEM + ldr x0, =__COHERENT_RAM_START__ + ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ + bl zeromem16 +#endif + + /* -------------------------------------------- + * Allocate a stack whose memory will be marked + * as Normal-IS-WBWA when the MMU is enabled. + * There is no risk of reading stale stack + * memory after enabling the MMU as only the + * primary cpu is running at the moment. + * -------------------------------------------- + */ + bl plat_set_my_stack + + /* --------------------------------------------- + * Perform early platform setup & platform + * specific early arch. setup e.g. mmu setup + * --------------------------------------------- + */ + bl tsp_early_platform_setup + bl tsp_plat_arch_setup + + /* --------------------------------------------- + * Jump to main function. + * --------------------------------------------- + */ + bl tsp_main + + /* --------------------------------------------- + * Tell TSPD that we are done initialising + * --------------------------------------------- + */ + mov x1, x0 + mov x0, #TSP_ENTRY_DONE + smc #0 + +tsp_entrypoint_panic: + b tsp_entrypoint_panic +endfunc tsp_entrypoint + + + /* ------------------------------------------- + * Table of entrypoint vectors provided to the + * TSPD for the various entrypoints + * ------------------------------------------- + */ +func tsp_vector_table + b tsp_std_smc_entry + b tsp_fast_smc_entry + b tsp_cpu_on_entry + b tsp_cpu_off_entry + b tsp_cpu_resume_entry + b tsp_cpu_suspend_entry + b tsp_fiq_entry + b tsp_system_off_entry + b tsp_system_reset_entry +endfunc tsp_vector_table + + /*--------------------------------------------- + * This entrypoint is used by the TSPD when this + * cpu is to be turned off through a CPU_OFF + * psci call to ask the TSP to perform any + * bookeeping necessary. In the current + * implementation, the TSPD expects the TSP to + * re-initialise its state so nothing is done + * here except for acknowledging the request. + * --------------------------------------------- + */ +func tsp_cpu_off_entry + bl tsp_cpu_off_main + restore_args_call_smc +endfunc tsp_cpu_off_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD when the + * system is about to be switched off (through + * a SYSTEM_OFF psci call) to ask the TSP to + * perform any necessary bookkeeping. + * --------------------------------------------- + */ +func tsp_system_off_entry + bl tsp_system_off_main + restore_args_call_smc +endfunc tsp_system_off_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD when the + * system is about to be reset (through a + * SYSTEM_RESET psci call) to ask the TSP to + * perform any necessary bookkeeping. + * --------------------------------------------- + */ +func tsp_system_reset_entry + bl tsp_system_reset_main + restore_args_call_smc +endfunc tsp_system_reset_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD when this + * cpu is turned on using a CPU_ON psci call to + * ask the TSP to initialise itself i.e. setup + * the mmu, stacks etc. Minimal architectural + * state will be initialised by the TSPD when + * this function is entered i.e. Caches and MMU + * will be turned off, the execution state + * will be aarch64 and exceptions masked. + * --------------------------------------------- + */ +func tsp_cpu_on_entry + /* --------------------------------------------- + * Set the exception vector to something sane. + * --------------------------------------------- + */ + adr x0, tsp_exceptions + msr vbar_el1, x0 + isb + + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + /* --------------------------------------------- + * Enable the instruction cache, stack pointer + * and data access alignment checks + * --------------------------------------------- + */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el1 + orr x0, x0, x1 + msr sctlr_el1, x0 + isb + + /* -------------------------------------------- + * Give ourselves a stack whose memory will be + * marked as Normal-IS-WBWA when the MMU is + * enabled. + * -------------------------------------------- + */ + bl plat_set_my_stack + + /* -------------------------------------------- + * Enable the MMU with the DCache disabled. It + * is safe to use stacks allocated in normal + * memory as a result. All memory accesses are + * marked nGnRnE when the MMU is disabled. So + * all the stack writes will make it to memory. + * All memory accesses are marked Non-cacheable + * when the MMU is enabled but D$ is disabled. + * So used stack memory is guaranteed to be + * visible immediately after the MMU is enabled + * Enabling the DCache at the same time as the + * MMU can lead to speculatively fetched and + * possibly stale stack memory being read from + * other caches. This can lead to coherency + * issues. + * -------------------------------------------- + */ + mov x0, #DISABLE_DCACHE + bl bl32_plat_enable_mmu + + /* --------------------------------------------- + * Enable the Data cache now that the MMU has + * been enabled. The stack has been unwound. It + * will be written first before being read. This + * will invalidate any stale cache lines resi- + * -dent in other caches. We assume that + * interconnect coherency has been enabled for + * this cluster by EL3 firmware. + * --------------------------------------------- + */ + mrs x0, sctlr_el1 + orr x0, x0, #SCTLR_C_BIT + msr sctlr_el1, x0 + isb + + /* --------------------------------------------- + * Enter C runtime to perform any remaining + * book keeping + * --------------------------------------------- + */ + bl tsp_cpu_on_main + restore_args_call_smc + + /* Should never reach here */ +tsp_cpu_on_entry_panic: + b tsp_cpu_on_entry_panic +endfunc tsp_cpu_on_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD when this + * cpu is to be suspended through a CPU_SUSPEND + * psci call to ask the TSP to perform any + * bookeeping necessary. In the current + * implementation, the TSPD saves and restores + * the EL1 state. + * --------------------------------------------- + */ +func tsp_cpu_suspend_entry + bl tsp_cpu_suspend_main + restore_args_call_smc +endfunc tsp_cpu_suspend_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD to pass + * control for handling a pending S-EL1 FIQ. + * 'x0' contains a magic number which indicates + * this. TSPD expects control to be handed back + * at the end of FIQ processing. This is done + * through an SMC. The handover agreement is: + * + * 1. PSTATE.DAIF are set upon entry. 'x1' has + * the ELR_EL3 from the non-secure state. + * 2. TSP has to preserve the callee saved + * general purpose registers, SP_EL1/EL0 and + * LR. + * 3. TSP has to preserve the system and vfp + * registers (if applicable). + * 4. TSP can use 'x0-x18' to enable its C + * runtime. + * 5. TSP returns to TSPD using an SMC with + * 'x0' = TSP_HANDLED_S_EL1_FIQ + * --------------------------------------------- + */ +func tsp_fiq_entry +#if DEBUG + mov x2, #(TSP_HANDLE_FIQ_AND_RETURN & ~0xffff) + movk x2, #(TSP_HANDLE_FIQ_AND_RETURN & 0xffff) + cmp x0, x2 + b.ne tsp_fiq_entry_panic +#endif + /*--------------------------------------------- + * Save any previous context needed to perform + * an exception return from S-EL1 e.g. context + * from a previous IRQ. Update statistics and + * handle the FIQ before returning to the TSPD. + * IRQ/FIQs are not enabled since that will + * complicate the implementation. Execution + * will be transferred back to the normal world + * in any case. A non-zero return value from the + * fiq handler is an error. + * --------------------------------------------- + */ + save_eret_context x2 x3 + bl tsp_update_sync_fiq_stats + bl tsp_fiq_handler + cbnz x0, tsp_fiq_entry_panic + restore_eret_context x2 x3 + mov x0, #(TSP_HANDLED_S_EL1_FIQ & ~0xffff) + movk x0, #(TSP_HANDLED_S_EL1_FIQ & 0xffff) + smc #0 + +tsp_fiq_entry_panic: + b tsp_fiq_entry_panic +endfunc tsp_fiq_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD when this + * cpu resumes execution after an earlier + * CPU_SUSPEND psci call to ask the TSP to + * restore its saved context. In the current + * implementation, the TSPD saves and restores + * EL1 state so nothing is done here apart from + * acknowledging the request. + * --------------------------------------------- + */ +func tsp_cpu_resume_entry + bl tsp_cpu_resume_main + restore_args_call_smc +tsp_cpu_resume_panic: + b tsp_cpu_resume_panic +endfunc tsp_cpu_resume_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD to ask + * the TSP to service a fast smc request. + * --------------------------------------------- + */ +func tsp_fast_smc_entry + bl tsp_smc_handler + restore_args_call_smc +tsp_fast_smc_entry_panic: + b tsp_fast_smc_entry_panic +endfunc tsp_fast_smc_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD to ask + * the TSP to service a std smc request. + * We will enable preemption during execution + * of tsp_smc_handler. + * --------------------------------------------- + */ +func tsp_std_smc_entry + msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT + bl tsp_smc_handler + msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT + restore_args_call_smc +tsp_std_smc_entry_panic: + b tsp_std_smc_entry_panic +endfunc tsp_std_smc_entry diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/aarch64/tsp_exceptions.S b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/aarch64/tsp_exceptions.S new file mode 100644 index 0000000..4c0d436 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/aarch64/tsp_exceptions.S @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + + /* ---------------------------------------------------- + * The caller-saved registers x0-x18 and LR are saved + * here. + * ---------------------------------------------------- + */ + +#define SCRATCH_REG_SIZE #(20 * 8) + + .macro save_caller_regs_and_lr + sub sp, sp, SCRATCH_REG_SIZE + stp x0, x1, [sp] + stp x2, x3, [sp, #0x10] + stp x4, x5, [sp, #0x20] + stp x6, x7, [sp, #0x30] + stp x8, x9, [sp, #0x40] + stp x10, x11, [sp, #0x50] + stp x12, x13, [sp, #0x60] + stp x14, x15, [sp, #0x70] + stp x16, x17, [sp, #0x80] + stp x18, x30, [sp, #0x90] + .endm + + .macro restore_caller_regs_and_lr + ldp x0, x1, [sp] + ldp x2, x3, [sp, #0x10] + ldp x4, x5, [sp, #0x20] + ldp x6, x7, [sp, #0x30] + ldp x8, x9, [sp, #0x40] + ldp x10, x11, [sp, #0x50] + ldp x12, x13, [sp, #0x60] + ldp x14, x15, [sp, #0x70] + ldp x16, x17, [sp, #0x80] + ldp x18, x30, [sp, #0x90] + add sp, sp, SCRATCH_REG_SIZE + .endm + + .globl tsp_exceptions + + /* ----------------------------------------------------- + * TSP exception handlers. + * ----------------------------------------------------- + */ + .section .vectors, "ax"; .align 11 + + .align 7 +tsp_exceptions: + /* ----------------------------------------------------- + * Current EL with _sp_el0 : 0x0 - 0x180. No exceptions + * are expected and treated as irrecoverable errors. + * ----------------------------------------------------- + */ +sync_exception_sp_el0: + wfi + b sync_exception_sp_el0 + check_vector_size sync_exception_sp_el0 + + .align 7 + +irq_sp_el0: + b irq_sp_el0 + check_vector_size irq_sp_el0 + + .align 7 +fiq_sp_el0: + b fiq_sp_el0 + check_vector_size fiq_sp_el0 + + .align 7 +serror_sp_el0: + b serror_sp_el0 + check_vector_size serror_sp_el0 + + + /* ----------------------------------------------------- + * Current EL with SPx: 0x200 - 0x380. Only IRQs/FIQs + * are expected and handled + * ----------------------------------------------------- + */ + .align 7 +sync_exception_sp_elx: + wfi + b sync_exception_sp_elx + check_vector_size sync_exception_sp_elx + + .align 7 +irq_sp_elx: + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + save_caller_regs_and_lr + /* We just update some statistics in the handler */ + bl tsp_irq_received + /* Hand over control to the normal world to handle the IRQ */ + smc #0 + /* The resume std smc starts from here */ + restore_caller_regs_and_lr + eret + check_vector_size irq_sp_elx + + .align 7 +fiq_sp_elx: + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + save_caller_regs_and_lr + bl tsp_fiq_handler + cbz x0, fiq_sp_elx_done + + /* + * This FIQ was not targetted to S-EL1 so send it to + * the monitor and wait for execution to resume. + */ + smc #0 +fiq_sp_elx_done: + restore_caller_regs_and_lr + eret + check_vector_size fiq_sp_elx + + .align 7 +serror_sp_elx: + b serror_sp_elx + check_vector_size serror_sp_elx + + + /* ----------------------------------------------------- + * Lower EL using AArch64 : 0x400 - 0x580. No exceptions + * are handled since TSP does not implement a lower EL + * ----------------------------------------------------- + */ + .align 7 +sync_exception_aarch64: + wfi + b sync_exception_aarch64 + check_vector_size sync_exception_aarch64 + + .align 7 +irq_aarch64: + b irq_aarch64 + check_vector_size irq_aarch64 + + .align 7 +fiq_aarch64: + b fiq_aarch64 + check_vector_size fiq_aarch64 + + .align 7 +serror_aarch64: + b serror_aarch64 + check_vector_size serror_aarch64 + + + /* ----------------------------------------------------- + * Lower EL using AArch32 : 0x600 - 0x780. No exceptions + * handled since the TSP does not implement a lower EL. + * ----------------------------------------------------- + */ + .align 7 +sync_exception_aarch32: + wfi + b sync_exception_aarch32 + check_vector_size sync_exception_aarch32 + + .align 7 +irq_aarch32: + b irq_aarch32 + check_vector_size irq_aarch32 + + .align 7 +fiq_aarch32: + b fiq_aarch32 + check_vector_size fiq_aarch32 + + .align 7 +serror_aarch32: + b serror_aarch32 + check_vector_size serror_aarch32 + .align 7 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/aarch64/tsp_request.S b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/aarch64/tsp_request.S new file mode 100644 index 0000000..e30acf6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/aarch64/tsp_request.S @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl tsp_get_magic + + +/* + * This function raises an SMC to retrieve arguments from secure + * monitor/dispatcher, saves the returned arguments the array received in x0, + * and then returns to the caller + */ +func tsp_get_magic + /* Save address to stack */ + stp x0, xzr, [sp, #-16]! + + /* Load arguments */ + ldr w0, _tsp_fid_get_magic + + /* Raise SMC */ + smc #0 + + /* Restore address from stack */ + ldp x4, xzr, [sp], #16 + + /* Store returned arguments to the array */ + stp x0, x1, [x4, #0] + + ret +endfunc tsp_get_magic + + .align 2 +_tsp_fid_get_magic: + .word TSP_GET_ARGS diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp.ld.S b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp.ld.S new file mode 100644 index 0000000..41c4b4a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp.ld.S @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) +OUTPUT_ARCH(PLATFORM_LINKER_ARCH) +ENTRY(tsp_entrypoint) + + +MEMORY { + RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE +} + + +SECTIONS +{ + . = BL32_BASE; + ASSERT(. == ALIGN(4096), + "BL32_BASE address is not aligned on a page boundary.") + + ro . : { + __RO_START__ = .; + *tsp_entrypoint.o(.text*) + *(.text*) + *(.rodata*) + *(.vectors) + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as + * read-only, executable. No RW data from the next section must + * creep in. Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __RO_END__ = .; + } >RAM + + /* + * Define a linker symbol to mark start of the RW memory area for this + * image. + */ + __RW_START__ = . ; + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + +#ifdef TSP_PROGBITS_LIMIT + ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.") +#endif + + stacks (NOLOAD) : { + __STACKS_START__ = .; + *(tzfw_normal_stacks) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } >RAM + + /* + * The xlat_table section is for full, aligned page tables (4K). + * Removing them from .bss avoids forcing 4K alignment on + * the .bss section and eliminates the unecessary zero init + */ + xlat_table (NOLOAD) : { + *(xlat_table) + } >RAM + +#if USE_COHERENT_MEM + /* + * The base address of the coherent memory section must be page-aligned (4K) + * to guarantee that the coherent data are stored on their own pages and + * are not mixed with normal data. This is required to set up the correct + * memory attributes for the coherent data page tables. + */ + coherent_ram (NOLOAD) : ALIGN(4096) { + __COHERENT_RAM_START__ = .; + *(tzfw_coherent_mem) + __COHERENT_RAM_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked + * as device memory. No other unexpected data must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __COHERENT_RAM_END__ = .; + } >RAM +#endif + + /* + * Define a linker symbol to mark the end of the RW memory area for this + * image. + */ + __RW_END__ = .; + __BL32_END__ = .; + + __BSS_SIZE__ = SIZEOF(.bss); +#if USE_COHERENT_MEM + __COHERENT_RAM_UNALIGNED_SIZE__ = + __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; +#endif + + ASSERT(. <= BL32_LIMIT, "BL3-2 image has exceeded its limit.") +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp.mk b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp.mk new file mode 100644 index 0000000..aeda31a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp.mk @@ -0,0 +1,60 @@ +# +# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +INCLUDES += -Iinclude/bl32/tsp + +BL32_SOURCES += bl32/tsp/tsp_main.c \ + bl32/tsp/aarch64/tsp_entrypoint.S \ + bl32/tsp/aarch64/tsp_exceptions.S \ + bl32/tsp/aarch64/tsp_request.S \ + bl32/tsp/tsp_interrupt.c \ + bl32/tsp/tsp_timer.c \ + common/aarch64/early_exceptions.S \ + lib/locks/exclusive/spinlock.S + +BL32_LINKERFILE := bl32/tsp/tsp.ld.S + +# This flag determines if the TSPD initializes BL3-2 in tspd_init() (synchronous +# method) or configures BL3-1 to pass control to BL3-2 instead of BL3-3 +# (asynchronous method). +TSP_INIT_ASYNC := 0 + +$(eval $(call assert_boolean,TSP_INIT_ASYNC)) +$(eval $(call add_define,TSP_INIT_ASYNC)) + +# Include the platform-specific TSP Makefile +# If no platform-specific TSP Makefile exists, it means TSP is not supported +# on this platform. +TSP_PLAT_MAKEFILE := $(shell find plat/ -wholename '*/${PLAT}/tsp/tsp-${PLAT}.mk') +ifeq (,$(wildcard ${TSP_PLAT_MAKEFILE})) + $(error TSP is not supported on platform ${PLAT}) +else + include ${TSP_PLAT_MAKEFILE} +endif diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp_interrupt.c b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp_interrupt.c new file mode 100644 index 0000000..139642d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp_interrupt.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "tsp_private.h" + +/******************************************************************************* + * This function updates the TSP statistics for FIQs handled synchronously i.e + * the ones that have been handed over by the TSPD. It also keeps count of the + * number of times control was passed back to the TSPD after handling an FIQ. + * In the future it will be possible that the TSPD hands over an FIQ to the TSP + * but does not expect it to return execution. This statistic will be useful to + * distinguish between these two models of synchronous FIQ handling. + * The 'elr_el3' parameter contains the address of the instruction in normal + * world where this FIQ was generated. + ******************************************************************************/ +void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3) +{ + uint32_t linear_id = plat_my_core_pos(); + + tsp_stats[linear_id].sync_fiq_count++; + if (type == TSP_HANDLE_FIQ_AND_RETURN) + tsp_stats[linear_id].sync_fiq_ret_count++; + +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + spin_lock(&console_lock); + VERBOSE("TSP: cpu 0x%lx sync fiq request from 0x%lx\n", + read_mpidr(), elr_el3); + VERBOSE("TSP: cpu 0x%lx: %d sync fiq requests, %d sync fiq returns\n", + read_mpidr(), + tsp_stats[linear_id].sync_fiq_count, + tsp_stats[linear_id].sync_fiq_ret_count); + spin_unlock(&console_lock); +#endif +} + +/******************************************************************************* + * TSP FIQ handler called as a part of both synchronous and asynchronous + * handling of FIQ interrupts. It returns 0 upon successfully handling a S-EL1 + * FIQ and treats all other FIQs as EL3 interrupts. It assumes that the GIC + * architecture version in v2.0 and the secure physical timer interrupt is the + * only S-EL1 interrupt that it needs to handle. + ******************************************************************************/ +int32_t tsp_fiq_handler(void) +{ + uint32_t linear_id = plat_my_core_pos(), id; + + /* + * Get the highest priority pending interrupt id and see if it is the + * secure physical generic timer interrupt in which case, handle it. + * Otherwise throw this interrupt at the EL3 firmware. + */ + id = plat_ic_get_pending_interrupt_id(); + + /* TSP can only handle the secure physical timer interrupt */ + if (id != TSP_IRQ_SEC_PHY_TIMER) + return TSP_EL3_FIQ; + + /* + * Handle the interrupt. Also sanity check if it has been preempted by + * another secure interrupt through an assertion. + */ + id = plat_ic_acknowledge_interrupt(); + assert(id == TSP_IRQ_SEC_PHY_TIMER); + tsp_generic_timer_handler(); + plat_ic_end_of_interrupt(id); + + /* Update the statistics and print some messages */ + tsp_stats[linear_id].fiq_count++; +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + spin_lock(&console_lock); + VERBOSE("TSP: cpu 0x%lx handled fiq %d\n", + read_mpidr(), id); + VERBOSE("TSP: cpu 0x%lx: %d fiq requests\n", + read_mpidr(), tsp_stats[linear_id].fiq_count); + spin_unlock(&console_lock); +#endif + return 0; +} + +int32_t tsp_irq_received(void) +{ + uint32_t linear_id = plat_my_core_pos(); + + tsp_stats[linear_id].irq_count++; +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + spin_lock(&console_lock); + VERBOSE("TSP: cpu 0x%lx received irq\n", read_mpidr()); + VERBOSE("TSP: cpu 0x%lx: %d irq requests\n", + read_mpidr(), tsp_stats[linear_id].irq_count); + spin_unlock(&console_lock); +#endif + return TSP_PREEMPTED; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp_main.c b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp_main.c new file mode 100644 index 0000000..359b9e1 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp_main.c @@ -0,0 +1,419 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "tsp_private.h" + + +/******************************************************************************* + * Lock to control access to the console + ******************************************************************************/ +spinlock_t console_lock; + +/******************************************************************************* + * Per cpu data structure to populate parameters for an SMC in C code and use + * a pointer to this structure in assembler code to populate x0-x7 + ******************************************************************************/ +static tsp_args_t tsp_smc_args[PLATFORM_CORE_COUNT]; + +/******************************************************************************* + * Per cpu data structure to keep track of TSP activity + ******************************************************************************/ +work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; + +/******************************************************************************* + * The BL32 memory footprint starts with an RO sections and ends + * with the linker symbol __BL32_END__. Use it to find the memory size + ******************************************************************************/ +#define BL32_TOTAL_BASE (unsigned long)(&__RO_START__) + +#define BL32_TOTAL_LIMIT (unsigned long)(&__BL32_END__) + +static tsp_args_t *set_smc_args(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id; + tsp_args_t *pcpu_smc_args; + + /* + * Return to Secure Monitor by raising an SMC. The results of the + * service are passed as an arguments to the SMC + */ + linear_id = plat_my_core_pos(); + pcpu_smc_args = &tsp_smc_args[linear_id]; + write_sp_arg(pcpu_smc_args, TSP_ARG0, arg0); + write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1); + write_sp_arg(pcpu_smc_args, TSP_ARG2, arg2); + write_sp_arg(pcpu_smc_args, TSP_ARG3, arg3); + write_sp_arg(pcpu_smc_args, TSP_ARG4, arg4); + write_sp_arg(pcpu_smc_args, TSP_ARG5, arg5); + write_sp_arg(pcpu_smc_args, TSP_ARG6, arg6); + write_sp_arg(pcpu_smc_args, TSP_ARG7, arg7); + + return pcpu_smc_args; +} + +/******************************************************************************* + * TSP main entry point where it gets the opportunity to initialize its secure + * state/applications. Once the state is initialized, it must return to the + * SPD with a pointer to the 'tsp_vector_table' jump table. + ******************************************************************************/ +uint64_t tsp_main(void) +{ + NOTICE("TSP: %s\n", version_string); + NOTICE("TSP: %s\n", build_message); + INFO("TSP: Total memory base : 0x%lx\n", BL32_TOTAL_BASE); + INFO("TSP: Total memory size : 0x%lx bytes\n", + BL32_TOTAL_LIMIT - BL32_TOTAL_BASE); + + uint32_t linear_id = plat_my_core_pos(); + + /* Initialize the platform */ + tsp_platform_setup(); + + /* Initialize secure/applications state here */ + tsp_generic_timer_start(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_on_count++; + +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_on_count); + spin_unlock(&console_lock); +#endif + return (uint64_t) &tsp_vector_table; +} + +/******************************************************************************* + * This function performs any remaining book keeping in the test secure payload + * after this cpu's architectural state has been setup in response to an earlier + * psci cpu_on request. + ******************************************************************************/ +tsp_args_t *tsp_cpu_on_main(void) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* Initialize secure/applications state here */ + tsp_generic_timer_start(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_on_count++; + +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); + INFO("TSP: cpu 0x%lx turned on\n", read_mpidr()); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_on_count); + spin_unlock(&console_lock); +#endif + /* Indicate to the SPD that we have completed turned ourselves on */ + return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * This function performs any remaining book keeping in the test secure payload + * before this cpu is turned off in response to a psci cpu_off request. + ******************************************************************************/ +tsp_args_t *tsp_cpu_off_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* + * This cpu is being turned off, so disable the timer to prevent the + * secure timer interrupt from interfering with power down. A pending + * interrupt will be lost but we do not care as we are turning off. + */ + tsp_generic_timer_stop(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_off_count++; + +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); + INFO("TSP: cpu 0x%lx off request\n", read_mpidr()); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_off_count); + spin_unlock(&console_lock); +#endif + + /* Indicate to the SPD that we have completed this request */ + return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * This function performs any book keeping in the test secure payload before + * this cpu's architectural state is saved in response to an earlier psci + * cpu_suspend request. + ******************************************************************************/ +tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* + * Save the time context and disable it to prevent the secure timer + * interrupt from interfering with wakeup from the suspend state. + */ + tsp_generic_timer_save(); + tsp_generic_timer_stop(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_suspend_count++; + +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_suspend_count); + spin_unlock(&console_lock); +#endif + + /* Indicate to the SPD that we have completed this request */ + return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * This function performs any book keeping in the test secure payload after this + * cpu's architectural state has been restored after wakeup from an earlier psci + * cpu_suspend request. + ******************************************************************************/ +tsp_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* Restore the generic timer context */ + tsp_generic_timer_restore(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_resume_count++; + +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); + INFO("TSP: cpu 0x%lx resumed. maximum off power level %ld\n", + read_mpidr(), max_off_pwrlvl); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_suspend_count); + spin_unlock(&console_lock); +#endif + /* Indicate to the SPD that we have completed this request */ + return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * This function performs any remaining bookkeeping in the test secure payload + * before the system is switched off (in response to a psci SYSTEM_OFF request) + ******************************************************************************/ +tsp_args_t *tsp_system_off_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); + INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", read_mpidr()); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count); + spin_unlock(&console_lock); +#endif + + /* Indicate to the SPD that we have completed this request */ + return set_smc_args(TSP_SYSTEM_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * This function performs any remaining bookkeeping in the test secure payload + * before the system is reset (in response to a psci SYSTEM_RESET request) + ******************************************************************************/ +tsp_args_t *tsp_system_reset_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); + INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", read_mpidr()); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count); + spin_unlock(&console_lock); +#endif + + /* Indicate to the SPD that we have completed this request */ + return set_smc_args(TSP_SYSTEM_RESET_DONE, 0, 0, 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * TSP fast smc handler. The secure monitor jumps to this function by + * doing the ERET after populating X0-X7 registers. The arguments are received + * in the function arguments in order. Once the service is rendered, this + * function returns to Secure Monitor by raising SMC. + ******************************************************************************/ +tsp_args_t *tsp_smc_handler(uint64_t func, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint64_t results[2]; + uint64_t service_args[2]; + uint32_t linear_id = plat_my_core_pos(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + + INFO("TSP: cpu 0x%lx received %s smc 0x%lx\n", read_mpidr(), + ((func >> 31) & 1) == 1 ? "fast" : "standard", + func); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count); + + /* Render secure services and obtain results here */ + results[0] = arg1; + results[1] = arg2; + + /* + * Request a service back from dispatcher/secure monitor. This call + * return and thereafter resume exectuion + */ + tsp_get_magic(service_args); + + /* Determine the function to perform based on the function ID */ + switch (TSP_BARE_FID(func)) { + case TSP_ADD: + results[0] += service_args[0]; + results[1] += service_args[1]; + break; + case TSP_SUB: + results[0] -= service_args[0]; + results[1] -= service_args[1]; + break; + case TSP_MUL: + results[0] *= service_args[0]; + results[1] *= service_args[1]; + break; + case TSP_DIV: + results[0] /= service_args[0] ? service_args[0] : 1; + results[1] /= service_args[1] ? service_args[1] : 1; + break; + default: + break; + } + + return set_smc_args(func, 0, + results[0], + results[1], + 0, 0, 0, 0); +} + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp_private.h b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp_private.h new file mode 100644 index 0000000..39fb5f6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp_private.h @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TSP_PRIVATE_H__ +#define __TSP_PRIVATE_H__ + +/* Definitions to help the assembler access the SMC/ERET args structure */ +#define TSP_ARGS_SIZE 0x40 +#define TSP_ARG0 0x0 +#define TSP_ARG1 0x8 +#define TSP_ARG2 0x10 +#define TSP_ARG3 0x18 +#define TSP_ARG4 0x20 +#define TSP_ARG5 0x28 +#define TSP_ARG6 0x30 +#define TSP_ARG7 0x38 +#define TSP_ARGS_END 0x40 + + +#ifndef __ASSEMBLY__ + +#include +#include /* For CACHE_WRITEBACK_GRANULE */ +#include +#include +#include + + +typedef struct work_statistics { + uint32_t fiq_count; /* Number of FIQs on this cpu */ + uint32_t irq_count; /* Number of IRQs on this cpu */ + uint32_t sync_fiq_count; /* Number of sync. fiqs on this cpu */ + uint32_t sync_fiq_ret_count; /* Number of fiq returns on this cpu */ + uint32_t smc_count; /* Number of returns on this cpu */ + uint32_t eret_count; /* Number of entries on this cpu */ + uint32_t cpu_on_count; /* Number of cpu on requests */ + uint32_t cpu_off_count; /* Number of cpu off requests */ + uint32_t cpu_suspend_count; /* Number of cpu suspend requests */ + uint32_t cpu_resume_count; /* Number of cpu resume requests */ +} __aligned(CACHE_WRITEBACK_GRANULE) work_statistics_t; + +typedef struct tsp_args { + uint64_t _regs[TSP_ARGS_END >> 3]; +} __aligned(CACHE_WRITEBACK_GRANULE) tsp_args_t; + +/* Macros to access members of the above structure using their offsets */ +#define read_sp_arg(args, offset) ((args)->_regs[offset >> 3]) +#define write_sp_arg(args, offset, val) (((args)->_regs[offset >> 3]) \ + = val) +/* + * Ensure that the assembler's view of the size of the tsp_args is the + * same as the compilers + */ +CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args_t), assert_sp_args_size_mismatch); + +void tsp_get_magic(uint64_t args[4]); + +tsp_args_t *tsp_cpu_resume_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +tsp_args_t *tsp_cpu_on_main(void); +tsp_args_t *tsp_cpu_off_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); + +/* Generic Timer functions */ +void tsp_generic_timer_start(void); +void tsp_generic_timer_handler(void); +void tsp_generic_timer_stop(void); +void tsp_generic_timer_save(void); +void tsp_generic_timer_restore(void); + +/* FIQ management functions */ +void tsp_update_sync_fiq_stats(uint32_t type, uint64_t elr_el3); + + +/* Data structure to keep track of TSP statistics */ +extern spinlock_t console_lock; +extern work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; + +/* Vector table of jumps */ +extern tsp_vectors_t tsp_vector_table; + + +#endif /* __ASSEMBLY__ */ + +#endif /* __TSP_PRIVATE_H__ */ + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp_timer.c b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp_timer.c new file mode 100644 index 0000000..7ca8734 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl32/tsp/tsp_timer.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include "tsp_private.h" + +/******************************************************************************* + * Data structure to keep track of per-cpu secure generic timer context across + * power management operations. + ******************************************************************************/ +typedef struct timer_context { + uint64_t cval; + uint32_t ctl; +} timer_context_t; + +static timer_context_t pcpu_timer_context[PLATFORM_CORE_COUNT]; + +/******************************************************************************* + * This function initializes the generic timer to fire every 0.5 second + ******************************************************************************/ +void tsp_generic_timer_start(void) +{ + uint64_t cval; + uint32_t ctl = 0; + + /* The timer will fire every 0.5 second */ + cval = read_cntpct_el0() + (read_cntfrq_el0() >> 1); + write_cntps_cval_el1(cval); + + /* Enable the secure physical timer */ + set_cntp_ctl_enable(ctl); + write_cntps_ctl_el1(ctl); +} + +/******************************************************************************* + * This function deasserts the timer interrupt and sets it up again + ******************************************************************************/ +void tsp_generic_timer_handler(void) +{ + /* Ensure that the timer did assert the interrupt */ + assert(get_cntp_ctl_istatus(read_cntps_ctl_el1())); + + /* + * Disable the timer and reprogram it. The barriers ensure that there is + * no reordering of instructions around the reprogramming code. + */ + isb(); + write_cntps_ctl_el1(0); + tsp_generic_timer_start(); + isb(); +} + +/******************************************************************************* + * This function deasserts the timer interrupt prior to cpu power down + ******************************************************************************/ +void tsp_generic_timer_stop(void) +{ + /* Disable the timer */ + write_cntps_ctl_el1(0); +} + +/******************************************************************************* + * This function saves the timer context prior to cpu suspension + ******************************************************************************/ +void tsp_generic_timer_save(void) +{ + uint32_t linear_id = plat_my_core_pos(); + + pcpu_timer_context[linear_id].cval = read_cntps_cval_el1(); + pcpu_timer_context[linear_id].ctl = read_cntps_ctl_el1(); + flush_dcache_range((uint64_t) &pcpu_timer_context[linear_id], + sizeof(pcpu_timer_context[linear_id])); +} + +/******************************************************************************* + * This function restores the timer context post cpu resummption + ******************************************************************************/ +void tsp_generic_timer_restore(void) +{ + uint32_t linear_id = plat_my_core_pos(); + + write_cntps_cval_el1(pcpu_timer_context[linear_id].cval); + write_cntps_ctl_el1(pcpu_timer_context[linear_id].ctl); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl33/aarch64/bl33_entrypoint.S b/IPL/SDK/v3m/src/Dummy_BL33/bl33/aarch64/bl33_entrypoint.S new file mode 100644 index 0000000..b1b32aa --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl33/aarch64/bl33_entrypoint.S @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .globl bl33_entrypoint + + + /* ----------------------------------------------------- + * bl31_entrypoint() is the cold boot entrypoint, + * executed only by the primary cpu. + * ----------------------------------------------------- + */ + +func bl33_entrypoint + mov x0, #0 + mov x1, #0 + mov x2, #0 + mov x3, #0 + mov x4, #0 + mov x5, #0 + mov x6, #0 + mov x7, #0 + mov x8, #0 + mov x9, #0 + mov x10, #0 + mov x11, #0 + mov x12, #0 + mov x13, #0 + mov x14, #0 + mov x15, #0 + mov x16, #0 + mov x17, #0 + mov x18, #0 + mov x19, #0 + mov x20, #0 + mov x21, #0 + mov x22, #0 + mov x23, #0 + mov x24, #0 + mov x25, #0 + mov x26, #0 + mov x27, #0 + mov x28, #0 + mov x29, #0 + mov x30, #0 + + /* --------------------------------------------- + * Set the exception vector to something sane. + * --------------------------------------------- + */ + adr x0, runtime_exceptions + msr vbar_el1, x0 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT + + /* --------------------------------------------- + * Enable the instruction cache, stack pointer + * and data access alignment checks + * --------------------------------------------- + */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el1 + orr x0, x0, x1 + msr sctlr_el1, x0 + isb + + /* --------------------------------------------- + * Invalidate the RW memory used by the BL2 + * image. This includes the data and NOBITS + * sections. This is done to safeguard against + * possible corruption of this memory by dirty + * cache lines in a system cache as a result of + * use by an earlier boot loader stage. + * --------------------------------------------- + */ + adr x0, __RW_START__ + adr x1, __RW_END__ + sub x1, x1, x0 + bl inv_dcache_range + + /* --------------------------------------------- + * Zero out NOBITS sections. There are 2 of them: + * - the .bss section; + * - the coherent memory section. + * --------------------------------------------- + */ + ldr x0, =__BSS_START__ + ldr x1, =__BSS_SIZE__ + bl zeromem16 + +#if USE_COHERENT_MEM + ldr x0, =__COHERENT_RAM_START__ + ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ + bl zeromem16 +#endif + + /* -------------------------------------------- + * Allocate a stack whose memory will be marked + * as Normal-IS-WBWA when the MMU is enabled. + * There is no risk of reading stale stack + * memory after enabling the MMU as only the + * primary cpu is running at the moment. + * -------------------------------------------- + */ + bl plat_set_my_stack + + /* --------------------------------------------- + * Perform platform specific early arch. setup + * --------------------------------------------- + */ + bl bl33_early_platform_setup + bl bl33_plat_arch_setup + + /* --------------------------------------------- + * Jump to main function. + * --------------------------------------------- + */ + bl bl33_main + + /* ------------------------------------------------------------- + * Clean the .data & .bss sections to main memory. This ensures + * that any global data which was initialised by the primary CPU + * is visible to secondary CPUs before they enable their data + * caches and participate in coherency. + * ------------------------------------------------------------- + */ + adr x0, __DATA_START__ + adr x1, __DATA_END__ + sub x1, x1, x0 + bl clean_dcache_range + + adr x0, __BSS_START__ + adr x1, __BSS_END__ + sub x1, x1, x0 + bl clean_dcache_range + + nop +1: + wfe + b 1b +_panic: + wfe + b _panic +endfunc bl33_entrypoint diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl33/aarch64/crash_reporting.S b/IPL/SDK/v3m/src/Dummy_BL33/bl33/aarch64/crash_reporting.S new file mode 100644 index 0000000..7edbbf2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl33/aarch64/crash_reporting.S @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include + + .globl report_unhandled_exception + .globl report_unhandled_interrupt + .globl el3_panic + +#if CRASH_REPORTING +#define REG_SIZE 0x8 + + /* ------------------------------------------------------ + * The below section deals with dumping the system state + * when an unhandled exception is taken in EL3. + * The layout and the names of the registers which will + * be dumped during a unhandled exception is given below. + * ------------------------------------------------------ + */ +.section .rodata.crash_prints, "aS" +print_spacer: + .asciz " =\t\t0x" + +gp_regs: + .asciz "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\ + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",\ + "x16", "x17", "x18", "x19", "x20", "x21", "x22",\ + "x23", "x24", "x25", "x26", "x27", "x28", "x29", "" +el3_sys_regs: + .asciz "scr_el3", "sctlr_el3", "cptr_el3", "tcr_el3",\ + "daif", "mair_el3", "spsr_el3", "elr_el3", "ttbr0_el3",\ + "esr_el3", "far_el3", "" + +non_el3_sys_regs: + .asciz "spsr_el1", "elr_el1", "spsr_abt", "spsr_und",\ + "spsr_irq", "spsr_fiq", "sctlr_el1", "actlr_el1", "cpacr_el1",\ + "csselr_el1", "sp_el1", "esr_el1", "ttbr0_el1", "ttbr1_el1",\ + "mair_el1", "amair_el1", "tcr_el1", "tpidr_el1", "tpidr_el0",\ + "tpidrro_el0", "dacr32_el2", "ifsr32_el2", "par_el1",\ + "mpidr_el1", "afsr0_el1", "afsr1_el1", "contextidr_el1",\ + "vbar_el1", "cntp_ctl_el0", "cntp_cval_el0", "cntv_ctl_el0",\ + "cntv_cval_el0", "cntkctl_el1", "fpexc32_el2", "sp_el0", "" + +panic_msg: + .asciz "PANIC in EL3 at x30 = 0x" +excpt_msg: + .asciz "Unhandled Exception in EL3.\nx30 =\t\t0x" +intr_excpt_msg: + .asciz "Unhandled Interrupt Exception in EL3.\nx30 =\t\t0x" + + /* + * Helper function to print newline to console. + */ +func print_newline + mov x0, '\n' + b plat_crash_console_putc +endfunc print_newline + + /* + * Helper function to print from crash buf. + * The print loop is controlled by the buf size and + * ascii reg name list which is passed in x6. The + * function returns the crash buf address in x0. + * Clobbers : x0 - x7, sp + */ +func size_controlled_print + /* Save the lr */ + mov sp, x30 + /* load the crash buf address */ + mrs x7, tpidr_el3 +test_size_list: + /* Calculate x5 always as it will be clobbered by asm_print_hex */ + mrs x5, tpidr_el3 + add x5, x5, #CPU_DATA_CRASH_BUF_SIZE + /* Test whether we have reached end of crash buf */ + cmp x7, x5 + b.eq exit_size_print + ldrb w4, [x6] + /* Test whether we are at end of list */ + cbz w4, exit_size_print + mov x4, x6 + /* asm_print_str updates x4 to point to next entry in list */ + bl asm_print_str + /* update x6 with the updated list pointer */ + mov x6, x4 + adr x4, print_spacer + bl asm_print_str + ldr x4, [x7], #REG_SIZE + bl asm_print_hex + bl print_newline + b test_size_list +exit_size_print: + mov x30, sp + ret +endfunc size_controlled_print + + /* + * Helper function to store x8 - x15 registers to + * the crash buf. The system registers values are + * copied to x8 to x15 by the caller which are then + * copied to the crash buf by this function. + * x0 points to the crash buf. It then calls + * size_controlled_print to print to console. + * Clobbers : x0 - x7, sp + */ +func str_in_crash_buf_print + /* restore the crash buf address in x0 */ + mrs x0, tpidr_el3 + stp x8, x9, [x0] + stp x10, x11, [x0, #REG_SIZE * 2] + stp x12, x13, [x0, #REG_SIZE * 4] + stp x14, x15, [x0, #REG_SIZE * 6] + b size_controlled_print +endfunc str_in_crash_buf_print + + /* ------------------------------------------------------ + * This macro calculates the offset to crash buf from + * cpu_data and stores it in tpidr_el3. It also saves x0 + * and x1 in the crash buf by using sp as a temporary + * register. + * ------------------------------------------------------ + */ + .macro prepare_crash_buf_save_x0_x1 + /* we can corrupt this reg to free up x0 */ + mov sp, x0 + /* tpidr_el3 contains the address to cpu_data structure */ + mrs x0, tpidr_el3 + /* Calculate the Crash buffer offset in cpu_data */ + add x0, x0, #CPU_DATA_CRASH_BUF_OFFSET + /* Store crash buffer address in tpidr_el3 */ + msr tpidr_el3, x0 + str x1, [x0, #REG_SIZE] + mov x1, sp + str x1, [x0] + .endm + + /* ----------------------------------------------------- + * This function allows to report a crash (if crash + * reporting is enabled) when an unhandled exception + * occurs. It prints the CPU state via the crash console + * making use of the crash buf. This function will + * not return. + * ----------------------------------------------------- + */ +func report_unhandled_exception + prepare_crash_buf_save_x0_x1 + adr x0, excpt_msg + mov sp, x0 + /* This call will not return */ + b do_crash_reporting +endfunc report_unhandled_exception + + + /* ----------------------------------------------------- + * This function allows to report a crash (if crash + * reporting is enabled) when an unhandled interrupt + * occurs. It prints the CPU state via the crash console + * making use of the crash buf. This function will + * not return. + * ----------------------------------------------------- + */ +func report_unhandled_interrupt + prepare_crash_buf_save_x0_x1 + adr x0, intr_excpt_msg + mov sp, x0 + /* This call will not return */ + b do_crash_reporting +endfunc report_unhandled_interrupt + + /* ----------------------------------------------------- + * This function allows to report a crash (if crash + * reporting is enabled) when panic() is invoked from + * C Runtime. It prints the CPU state via the crash + * console making use of the crash buf. This function + * will not return. + * ----------------------------------------------------- + */ +func el3_panic + msr spsel, #1 + prepare_crash_buf_save_x0_x1 + adr x0, panic_msg + mov sp, x0 + /* This call will not return */ + b do_crash_reporting +endfunc el3_panic + + /* ------------------------------------------------------------ + * The common crash reporting functionality. It requires x0 + * and x1 has already been stored in crash buf, sp points to + * crash message and tpidr_el3 contains the crash buf address. + * The function does the following: + * - Retrieve the crash buffer from tpidr_el3 + * - Store x2 to x6 in the crash buffer + * - Initialise the crash console. + * - Print the crash message by using the address in sp. + * - Print x30 value to the crash console. + * - Print x0 - x7 from the crash buf to the crash console. + * - Print x8 - x29 (in groups of 8 registers) using the + * crash buf to the crash console. + * - Print el3 sys regs (in groups of 8 registers) using the + * crash buf to the crash console. + * - Print non el3 sys regs (in groups of 8 registers) using + * the crash buf to the crash console. + * ------------------------------------------------------------ + */ +func do_crash_reporting + /* Retrieve the crash buf from tpidr_el3 */ + mrs x0, tpidr_el3 + /* Store x2 - x6, x30 in the crash buffer */ + stp x2, x3, [x0, #REG_SIZE * 2] + stp x4, x5, [x0, #REG_SIZE * 4] + stp x6, x30, [x0, #REG_SIZE * 6] + /* Initialize the crash console */ + bl plat_crash_console_init + /* Verify the console is initialized */ + cbz x0, crash_panic + /* Print the crash message. sp points to the crash message */ + mov x4, sp + bl asm_print_str + /* load the crash buf address */ + mrs x0, tpidr_el3 + /* report x30 first from the crash buf */ + ldr x4, [x0, #REG_SIZE * 7] + bl asm_print_hex + bl print_newline + /* Load the crash buf address */ + mrs x0, tpidr_el3 + /* Now mov x7 into crash buf */ + str x7, [x0, #REG_SIZE * 7] + + /* Report x0 - x29 values stored in crash buf*/ + /* Store the ascii list pointer in x6 */ + adr x6, gp_regs + /* Print x0 to x7 from the crash buf */ + bl size_controlled_print + /* Store x8 - x15 in crash buf and print */ + bl str_in_crash_buf_print + /* Load the crash buf address */ + mrs x0, tpidr_el3 + /* Store the rest of gp regs and print */ + stp x16, x17, [x0] + stp x18, x19, [x0, #REG_SIZE * 2] + stp x20, x21, [x0, #REG_SIZE * 4] + stp x22, x23, [x0, #REG_SIZE * 6] + bl size_controlled_print + /* Load the crash buf address */ + mrs x0, tpidr_el3 + stp x24, x25, [x0] + stp x26, x27, [x0, #REG_SIZE * 2] + stp x28, x29, [x0, #REG_SIZE * 4] + bl size_controlled_print + + /* Print the el3 sys registers */ + adr x6, el3_sys_regs + mrs x8, scr_el3 + mrs x9, sctlr_el3 + mrs x10, cptr_el3 + mrs x11, tcr_el3 + mrs x12, daif + mrs x13, mair_el3 + mrs x14, spsr_el3 + mrs x15, elr_el3 + bl str_in_crash_buf_print + mrs x8, ttbr0_el3 + mrs x9, esr_el3 + mrs x10, far_el3 + bl str_in_crash_buf_print + + /* Print the non el3 sys registers */ + adr x6, non_el3_sys_regs + mrs x8, spsr_el1 + mrs x9, elr_el1 + mrs x10, spsr_abt + mrs x11, spsr_und + mrs x12, spsr_irq + mrs x13, spsr_fiq + mrs x14, sctlr_el1 + mrs x15, actlr_el1 + bl str_in_crash_buf_print + mrs x8, cpacr_el1 + mrs x9, csselr_el1 + mrs x10, sp_el1 + mrs x11, esr_el1 + mrs x12, ttbr0_el1 + mrs x13, ttbr1_el1 + mrs x14, mair_el1 + mrs x15, amair_el1 + bl str_in_crash_buf_print + mrs x8, tcr_el1 + mrs x9, tpidr_el1 + mrs x10, tpidr_el0 + mrs x11, tpidrro_el0 + mrs x12, dacr32_el2 + mrs x13, ifsr32_el2 + mrs x14, par_el1 + mrs x15, mpidr_el1 + bl str_in_crash_buf_print + mrs x8, afsr0_el1 + mrs x9, afsr1_el1 + mrs x10, contextidr_el1 + mrs x11, vbar_el1 + mrs x12, cntp_ctl_el0 + mrs x13, cntp_cval_el0 + mrs x14, cntv_ctl_el0 + mrs x15, cntv_cval_el0 + bl str_in_crash_buf_print + mrs x8, cntkctl_el1 + mrs x9, fpexc32_el2 + mrs x10, sp_el0 + bl str_in_crash_buf_print + + /* Get the cpu specific registers to report */ + bl do_cpu_reg_dump + bl str_in_crash_buf_print + + /* Print the gic registers */ + plat_print_gic_regs + + /* Print the interconnect registers */ + plat_print_interconnect_regs + + /* Done reporting */ + b crash_panic +endfunc do_crash_reporting + +#else /* CRASH_REPORTING */ +func report_unhandled_exception +report_unhandled_interrupt: + b crash_panic +endfunc report_unhandled_exception +#endif /* CRASH_REPORING */ + + +func crash_panic + b crash_panic +endfunc crash_panic \ No newline at end of file diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl33/aarch64/runtime_exceptions.S b/IPL/SDK/v3m/src/Dummy_BL33/bl33/aarch64/runtime_exceptions.S new file mode 100644 index 0000000..bbc7f1b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl33/aarch64/runtime_exceptions.S @@ -0,0 +1,539 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + + .globl runtime_exceptions + .globl el3_exit + + /* ----------------------------------------------------- + * Handle SMC exceptions separately from other sync. + * exceptions. + * ----------------------------------------------------- + */ + .macro handle_sync_exception + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + mrs x30, esr_el3 + ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH + + cmp x30, #EC_AARCH32_SMC + b.eq smc_handler32 + + cmp x30, #EC_AARCH64_SMC + b.eq smc_handler64 + + /* ----------------------------------------------------- + * The following code handles any synchronous exception + * that is not an SMC. + * ----------------------------------------------------- + */ + + bl report_unhandled_exception + .endm + + + /* ----------------------------------------------------- + * This macro handles FIQ or IRQ interrupts i.e. EL3, + * S-EL1 and NS interrupts. + * ----------------------------------------------------- + */ + .macro handle_interrupt_exception label + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + bl save_gp_registers + + /* + * Save the EL3 system registers needed to return from + * this exception. + */ + mrs x0, spsr_el3 + mrs x1, elr_el3 + stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] + + /* Switch to the runtime stack i.e. SP_EL0 */ + ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] + mov x20, sp + msr spsel, #0 + mov sp, x2 + + /* + * Find out whether this is a valid interrupt type. If the + * interrupt controller reports a spurious interrupt then + * return to where we came from. + */ + bl plat_ic_get_pending_interrupt_type + cmp x0, #INTR_TYPE_INVAL + b.eq interrupt_exit_\label + + /* + * Get the registered handler for this interrupt type. A + * NULL return value could be 'cause of the following + * conditions: + * + * a. An interrupt of a type was routed correctly but a + * handler for its type was not registered. + * + * b. An interrupt of a type was not routed correctly so + * a handler for its type was not registered. + * + * c. An interrupt of a type was routed correctly to EL3, + * but was deasserted before its pending state could + * be read. Another interrupt of a different type pended + * at the same time and its type was reported as pending + * instead. However, a handler for this type was not + * registered. + * + * a. and b. can only happen due to a programming error. + * The occurrence of c. could be beyond the control of + * Trusted Firmware. It makes sense to return from this + * exception instead of reporting an error. + */ + bl get_interrupt_type_handler + cbz x0, interrupt_exit_\label + mov x21, x0 + + mov x0, #INTR_ID_UNAVAILABLE +#if IMF_READ_INTERRUPT_ID + /* + * Read the id of the highest priority pending interrupt. If + * no interrupt is asserted then return to where we came from. + */ + mov x19, #INTR_ID_UNAVAILABLE + bl plat_ic_get_pending_interrupt_id + cmp x19, x0 + b.eq interrupt_exit_\label +#endif + + /* Set the current security state in the 'flags' parameter */ + mrs x2, scr_el3 + ubfx x1, x2, #0, #1 + + /* Restore the reference to the 'handle' i.e. SP_EL3 */ + mov x2, x20 + + /* x3 will point to a cookie (not used now) */ + mov x3, xzr + + /* Call the interrupt type handler */ + blr x21 + +interrupt_exit_\label: + /* Return from exception, possibly in a different security state */ + b el3_exit + + .endm + + + .macro save_x18_to_x29_sp_el0 + stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] + stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] + stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] + stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] + stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] + stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] + mrs x18, sp_el0 + str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] + .endm + + .section .vectors, "ax"; .align 11 + .align 7 +runtime_exceptions: + /* ----------------------------------------------------- + * Current EL with _sp_el0 : 0x0 - 0x200 + * ----------------------------------------------------- + */ +sync_exception_sp_el0: + /* ----------------------------------------------------- + * We don't expect any synchronous exceptions from EL3 + * ----------------------------------------------------- + */ + bl report_unhandled_exception + check_vector_size sync_exception_sp_el0 + + .align 7 + /* ----------------------------------------------------- + * EL3 code is non-reentrant. Any asynchronous exception + * is a serious error. Loop infinitely. + * ----------------------------------------------------- + */ +irq_sp_el0: + bl report_unhandled_interrupt + check_vector_size irq_sp_el0 + + .align 7 +fiq_sp_el0: + bl report_unhandled_interrupt + check_vector_size fiq_sp_el0 + + .align 7 +serror_sp_el0: + bl report_unhandled_exception + check_vector_size serror_sp_el0 + + /* ----------------------------------------------------- + * Current EL with SPx: 0x200 - 0x400 + * ----------------------------------------------------- + */ + .align 7 +sync_exception_sp_elx: + /* ----------------------------------------------------- + * This exception will trigger if anything went wrong + * during a previous exception entry or exit or while + * handling an earlier unexpected synchronous exception. + * There is a high probability that SP_EL3 is corrupted. + * ----------------------------------------------------- + */ + bl report_unhandled_exception + check_vector_size sync_exception_sp_elx + + .align 7 +irq_sp_elx: + bl report_unhandled_interrupt + check_vector_size irq_sp_elx + + .align 7 +fiq_sp_elx: + bl report_unhandled_interrupt + check_vector_size fiq_sp_elx + + .align 7 +serror_sp_elx: + bl report_unhandled_exception + check_vector_size serror_sp_elx + + /* ----------------------------------------------------- + * Lower EL using AArch64 : 0x400 - 0x600 + * ----------------------------------------------------- + */ + .align 7 +sync_exception_aarch64: + /* ----------------------------------------------------- + * This exception vector will be the entry point for + * SMCs and traps that are unhandled at lower ELs most + * commonly. SP_EL3 should point to a valid cpu context + * where the general purpose and system register state + * can be saved. + * ----------------------------------------------------- + */ + handle_sync_exception + check_vector_size sync_exception_aarch64 + + .align 7 + /* ----------------------------------------------------- + * Asynchronous exceptions from lower ELs are not + * currently supported. Report their occurrence. + * ----------------------------------------------------- + */ +irq_aarch64: + handle_interrupt_exception irq_aarch64 + check_vector_size irq_aarch64 + + .align 7 +fiq_aarch64: + handle_interrupt_exception fiq_aarch64 + check_vector_size fiq_aarch64 + + .align 7 +serror_aarch64: + bl report_unhandled_exception + check_vector_size serror_aarch64 + + /* ----------------------------------------------------- + * Lower EL using AArch32 : 0x600 - 0x800 + * ----------------------------------------------------- + */ + .align 7 +sync_exception_aarch32: + /* ----------------------------------------------------- + * This exception vector will be the entry point for + * SMCs and traps that are unhandled at lower ELs most + * commonly. SP_EL3 should point to a valid cpu context + * where the general purpose and system register state + * can be saved. + * ----------------------------------------------------- + */ + handle_sync_exception + check_vector_size sync_exception_aarch32 + + .align 7 + /* ----------------------------------------------------- + * Asynchronous exceptions from lower ELs are not + * currently supported. Report their occurrence. + * ----------------------------------------------------- + */ +irq_aarch32: + handle_interrupt_exception irq_aarch32 + check_vector_size irq_aarch32 + + .align 7 +fiq_aarch32: + handle_interrupt_exception fiq_aarch32 + check_vector_size fiq_aarch32 + + .align 7 +serror_aarch32: + bl report_unhandled_exception + check_vector_size serror_aarch32 + + .align 7 + + /* ----------------------------------------------------- + * The following code handles secure monitor calls. + * Depending upon the execution state from where the SMC + * has been invoked, it frees some general purpose + * registers to perform the remaining tasks. They + * involve finding the runtime service handler that is + * the target of the SMC & switching to runtime stacks + * (SP_EL0) before calling the handler. + * + * Note that x30 has been explicitly saved and can be + * used here + * ----------------------------------------------------- + */ +func smc_handler +smc_handler32: + /* Check whether aarch32 issued an SMC64 */ + tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited + + /* ----------------------------------------------------- + * Since we're are coming from aarch32, x8-x18 need to + * be saved as per SMC32 calling convention. If a lower + * EL in aarch64 is making an SMC32 call then it must + * have saved x8-x17 already therein. + * ----------------------------------------------------- + */ + stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] + stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] + stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] + stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] + stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] + + /* x4-x7, x18, sp_el0 are saved below */ + +smc_handler64: + /* ----------------------------------------------------- + * Populate the parameters for the SMC handler. We + * already have x0-x4 in place. x5 will point to a + * cookie (not used now). x6 will point to the context + * structure (SP_EL3) and x7 will contain flags we need + * to pass to the handler Hence save x5-x7. Note that x4 + * only needs to be preserved for AArch32 callers but we + * do it for AArch64 callers as well for convenience + * ----------------------------------------------------- + */ + stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] + + /* Save rest of the gpregs and sp_el0*/ + save_x18_to_x29_sp_el0 + + mov x5, xzr + mov x6, sp + + /* Get the unique owning entity number */ + ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH + ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH + orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH + + adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) + + /* Load descriptor index from array of indices */ + adr x14, rt_svc_descs_indices + ldrb w15, [x14, x16] + + /* ----------------------------------------------------- + * Restore the saved C runtime stack value which will + * become the new SP_EL0 i.e. EL3 runtime stack. It was + * saved in the 'cpu_context' structure prior to the last + * ERET from EL3. + * ----------------------------------------------------- + */ + ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] + + /* + * Any index greater than 127 is invalid. Check bit 7 for + * a valid index + */ + tbnz w15, 7, smc_unknown + + /* Switch to SP_EL0 */ + msr spsel, #0 + + /* ----------------------------------------------------- + * Get the descriptor using the index + * x11 = (base + off), x15 = index + * + * handler = (base + off) + (index << log2(size)) + * ----------------------------------------------------- + */ + lsl w10, w15, #RT_SVC_SIZE_LOG2 + ldr x15, [x11, w10, uxtw] + + /* ----------------------------------------------------- + * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there + * is a world switch during SMC handling. + * TODO: Revisit if all system registers can be saved + * later. + * ----------------------------------------------------- + */ + mrs x16, spsr_el3 + mrs x17, elr_el3 + mrs x18, scr_el3 + stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] + str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] + + /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ + bfi x7, x18, #0, #1 + + mov sp, x12 + + /* ----------------------------------------------------- + * Call the Secure Monitor Call handler and then drop + * directly into el3_exit() which will program any + * remaining architectural state prior to issuing the + * ERET to the desired lower EL. + * ----------------------------------------------------- + */ +#if DEBUG + cbz x15, rt_svc_fw_critical_error +#endif + blr x15 + + /* ----------------------------------------------------- + * This routine assumes that the SP_EL3 is pointing to + * a valid context structure from where the gp regs and + * other special registers can be retrieved. + * + * Keep it in the same section as smc_handler as this + * function uses a fall-through to el3_exit + * ----------------------------------------------------- + */ +el3_exit: ; .type el3_exit, %function + /* ----------------------------------------------------- + * Save the current SP_EL0 i.e. the EL3 runtime stack + * which will be used for handling the next SMC. Then + * switch to SP_EL3 + * ----------------------------------------------------- + */ + mov x17, sp + msr spsel, #1 + str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] + + /* ----------------------------------------------------- + * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET + * ----------------------------------------------------- + */ + ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] + ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] + msr scr_el3, x18 + msr spsr_el3, x16 + msr elr_el3, x17 + + /* Restore saved general purpose registers and return */ + b restore_gp_registers_eret + +smc_unknown: + /* + * Here we restore x4-x18 regardless of where we came from. AArch32 + * callers will find the registers contents unchanged, but AArch64 + * callers will find the registers modified (with stale earlier NS + * content). Either way, we aren't leaking any secure information + * through them + */ + mov w0, #SMC_UNK + b restore_gp_registers_callee_eret + +smc_prohibited: + ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + mov w0, #SMC_UNK + eret + +rt_svc_fw_critical_error: + msr spsel, #1 /* Switch to SP_ELx */ + bl report_unhandled_exception +endfunc smc_handler + + /* ----------------------------------------------------- + * The following functions are used to saved and restore + * all the general pupose registers. Ideally we would + * only save and restore the callee saved registers when + * a world switch occurs but that type of implementation + * is more complex. So currently we will always save and + * restore these registers on entry and exit of EL3. + * These are not macros to ensure their invocation fits + * within the 32 instructions per exception vector. + * ----------------------------------------------------- + */ +func save_gp_registers + stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] + stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] + stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] + stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] + stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] + stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] + save_x18_to_x29_sp_el0 + ret +endfunc save_gp_registers + +func restore_gp_registers_eret + ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + +restore_gp_registers_callee_eret: + ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] + ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] + ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] + ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] + ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] + ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] + ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] + ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] + ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] + ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] + ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] + ldp x30, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + msr sp_el0, x17 + ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] + eret +endfunc restore_gp_registers_eret diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl33/bl33.ld.S b/IPL/SDK/v3m/src/Dummy_BL33/bl33/bl33.ld.S new file mode 100644 index 0000000..ef456d4 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl33/bl33.ld.S @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) +OUTPUT_ARCH(PLATFORM_LINKER_ARCH) +ENTRY(bl33_entrypoint) + + +MEMORY { + RAM (rwx): ORIGIN = BL33_BASE, LENGTH = BL33_LIMIT - BL33_BASE +} + + +SECTIONS +{ + . = BL33_BASE; + ASSERT(. == ALIGN(4096), + "BL33_BASE address is not aligned on a page boundary.") + + ro . : { + __RO_START__ = .; + *bl33_entrypoint.o(.text*) +#if PLAT_rcar + . = NEXT(ALIGN_VERSION); + *rcar_common.o(.version*) +#endif + *(.text*) + *(.rodata*) + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __RT_SVC_DESCS_START__ = .; + KEEP(*(rt_svc_descs)) + __RT_SVC_DESCS_END__ = .; + + /* + * Ensure 8-byte alignment for cpu_ops so that its fields are also + * aligned. Also ensure cpu_ops inclusion. + */ + . = ALIGN(8); + __CPU_OPS_START__ = .; + KEEP(*(cpu_ops)) + __CPU_OPS_END__ = .; + + *(.vectors) + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as read-only, + * executable. No RW data from the next section must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __RO_END__ = .; + } >RAM + + ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, + "cpu_ops not defined for this platform.") + + /* + * Define a linker symbol to mark start of the RW memory area for this + * image. + */ + __RW_START__ = . ; + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + +#ifdef BL33_PROGBITS_LIMIT + ASSERT(. <= BL33_PROGBITS_LIMIT, "BL3-3 progbits has exceeded its limit.") +#endif + + stacks (NOLOAD) : { + __STACKS_START__ = .; + *(tzfw_normal_stacks) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss (NOLOAD) : ALIGN(16) { + __BSS_START__ = .; + *(.bss*) + *(COMMON) +#if !USE_COHERENT_MEM + /* + * Bakery locks are stored in normal .bss memory + * + * Each lock's data is spread across multiple cache lines, one per CPU, + * but multiple locks can share the same cache line. + * The compiler will allocate enough memory for one CPU's bakery locks, + * the remaining cache lines are allocated by the linker script + */ + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __BAKERY_LOCK_START__ = .; + *(bakery_lock) + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); + . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); + __BAKERY_LOCK_END__ = .; +#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE + ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, + "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); +#endif +#endif + __BSS_END__ = .; + } >RAM + + /* + * The xlat_table section is for full, aligned page tables (4K). + * Removing them from .bss avoids forcing 4K alignment on + * the .bss section and eliminates the unecessary zero init + */ + xlat_table (NOLOAD) : { + *(xlat_table) + } >RAM + +#if USE_COHERENT_MEM + /* + * The base address of the coherent memory section must be page-aligned (4K) + * to guarantee that the coherent data are stored on their own pages and + * are not mixed with normal data. This is required to set up the correct + * memory attributes for the coherent data page tables. + */ + coherent_ram (NOLOAD) : ALIGN(4096) { + __COHERENT_RAM_START__ = .; + /* + * Bakery locks are stored in coherent memory + * + * Each lock's data is contiguous and fully allocated by the compiler + */ + *(bakery_lock) + *(tzfw_coherent_mem) + __COHERENT_RAM_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked + * as device memory. No other unexpected data must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __COHERENT_RAM_END__ = .; + } >RAM +#endif + + /* + * Define a linker symbol to mark end of the RW memory area for this + * image. + */ + __RW_END__ = .; + __BL33_END__ = .; + + __BSS_SIZE__ = SIZEOF(.bss); +#if USE_COHERENT_MEM + __COHERENT_RAM_UNALIGNED_SIZE__ = + __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; +#endif + + ASSERT(. <= BL33_LIMIT, "BL3-3 image has exceeded its limit.") +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl33/bl33.mk b/IPL/SDK/v3m/src/Dummy_BL33/bl33/bl33.mk new file mode 100644 index 0000000..94e9936 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl33/bl33.mk @@ -0,0 +1,55 @@ +# +# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +BL33_SOURCES += bl33/bl33_main.c \ + bl33/runtime_svc.c \ + bl33/interrupt_mgmt.c \ + bl33/aarch64/bl33_entrypoint.S \ + bl33/aarch64/runtime_exceptions.S \ + bl33/aarch64/crash_reporting.S \ + lib/cpus/aarch64/cpu_helpers.S + +BL33_LINKERFILE := bl33/bl33.ld.S + +# Flag used by the generic interrupt management framework to determine if +# upon the assertion of an interrupt, it should pass the interrupt id or not +IMF_READ_INTERRUPT_ID := 0 + +$(eval $(call assert_boolean,IMF_READ_INTERRUPT_ID)) +$(eval $(call add_define,IMF_READ_INTERRUPT_ID)) + +# Flag used to inidicate if Crash reporting via console should be included +# in BL3-1. This defaults to being present in DEBUG builds only +ifndef CRASH_REPORTING +CRASH_REPORTING := $(DEBUG) +endif + +$(eval $(call assert_boolean,CRASH_REPORTING)) +$(eval $(call add_define,CRASH_REPORTING)) diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl33/bl33_main.c b/IPL/SDK/v3m/src/Dummy_BL33/bl33/bl33_main.c new file mode 100644 index 0000000..03bf007 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl33/bl33_main.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/******************************************************************************* + * BL31 is responsible for setting up the runtime services for the primary cpu + * before passing control to the bootloader or an Operating System. This + * function calls runtime_svc_init() which initializes all registered runtime + * services. The run time services would setup enough context for the core to + * swtich to the next exception level. When this function returns, the core will + * switch to the programmed exception level via. an ERET. + ******************************************************************************/ +void bl33_main(void) +{ + NOTICE("BL3-3: %s\n", version_string); + NOTICE("BL3-3: %s\n", build_message); + + NOTICE("BL3-3: Dummy BL33 end\n"); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl33/interrupt_mgmt.c b/IPL/SDK/v3m/src/Dummy_BL33/bl33/interrupt_mgmt.c new file mode 100644 index 0000000..5478902 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl33/interrupt_mgmt.c @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Local structure and corresponding array to keep track of the state of the + * registered interrupt handlers for each interrupt type. + * The field descriptions are: + * + * 'flags' : Bit[0], Routing model for this interrupt type when execution is + * not in EL3 in the secure state. '1' implies that this + * interrupt will be routed to EL3. '0' implies that this + * interrupt will be routed to the current exception level. + * + * Bit[1], Routing model for this interrupt type when execution is + * not in EL3 in the non-secure state. '1' implies that this + * interrupt will be routed to EL3. '0' implies that this + * interrupt will be routed to the current exception level. + * + * All other bits are reserved and SBZ. + * + * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the + * value of the SCR_EL3.IRQ or FIQ bit for each security state. + * There are two instances of this field corresponding to the + * two security states. + ******************************************************************************/ +typedef struct intr_type_desc { + interrupt_type_handler_t handler; + uint32_t flags; + uint32_t scr_el3[2]; +} intr_type_desc_t; + +static intr_type_desc_t intr_type_descs[MAX_INTR_TYPES]; + +/******************************************************************************* + * This function validates the interrupt type. EL3 interrupts are currently not + * supported. + ******************************************************************************/ +static int32_t validate_interrupt_type(uint32_t type) +{ + if (type == INTR_TYPE_EL3) + return -ENOTSUP; + + if (type != INTR_TYPE_S_EL1 && type != INTR_TYPE_NS) + return -EINVAL; + + return 0; +} + +/******************************************************************************* +* This function validates the routing model for this type of interrupt + ******************************************************************************/ +static int32_t validate_routing_model(uint32_t type, uint32_t flags) +{ + flags >>= INTR_RM_FLAGS_SHIFT; + flags &= INTR_RM_FLAGS_MASK; + + if (type == INTR_TYPE_S_EL1) + return validate_sel1_interrupt_rm(flags); + + if (type == INTR_TYPE_NS) + return validate_ns_interrupt_rm(flags); + + return -EINVAL; +} + +/******************************************************************************* + * This function returns the cached copy of the SCR_EL3 which contains the + * routing model (expressed through the IRQ and FIQ bits) for a security state + * which was stored through a call to 'set_routing_model()' earlier. + ******************************************************************************/ +uint32_t get_scr_el3_from_routing_model(uint32_t security_state) +{ + uint32_t scr_el3; + + assert(sec_state_is_valid(security_state)); + scr_el3 = intr_type_descs[INTR_TYPE_NS].scr_el3[security_state]; + scr_el3 |= intr_type_descs[INTR_TYPE_S_EL1].scr_el3[security_state]; + scr_el3 |= intr_type_descs[INTR_TYPE_EL3].scr_el3[security_state]; + return scr_el3; +} + +/******************************************************************************* + * This function uses the 'interrupt_type_flags' parameter to obtain the value + * of the trap bit (IRQ/FIQ) in the SCR_EL3 for a security state for this + * interrupt type. It uses it to update the SCR_EL3 in the cpu context and the + * 'intr_type_desc' for that security state. + ******************************************************************************/ +static void set_scr_el3_from_rm(uint32_t type, + uint32_t interrupt_type_flags, + uint32_t security_state) +{ + uint32_t flag, bit_pos; + + flag = get_interrupt_rm_flag(interrupt_type_flags, security_state); + bit_pos = plat_interrupt_type_to_line(type, security_state); + intr_type_descs[type].scr_el3[security_state] = flag << bit_pos; + cm_write_scr_el3_bit(security_state, bit_pos, flag); +} + +/******************************************************************************* + * This function validates the routing model specified in the 'flags' and + * updates internal data structures to reflect the new routing model. It also + * updates the copy of SCR_EL3 for each security state with the new routing + * model in the 'cpu_context' structure for this cpu. + ******************************************************************************/ +int32_t set_routing_model(uint32_t type, uint32_t flags) +{ + int32_t rc; + + rc = validate_interrupt_type(type); + if (rc) + return rc; + + rc = validate_routing_model(type, flags); + if (rc) + return rc; + + /* Update the routing model in internal data structures */ + intr_type_descs[type].flags = flags; + set_scr_el3_from_rm(type, flags, SECURE); + set_scr_el3_from_rm(type, flags, NON_SECURE); + + return 0; +} + +/****************************************************************************** + * This function disables the routing model of interrupt 'type' from the + * specified 'security_state' on the local core. The disable is in effect + * till the core powers down or till the next enable for that interrupt + * type. + *****************************************************************************/ +int disable_intr_rm_local(uint32_t type, uint32_t security_state) +{ + uint32_t bit_pos, flag; + + assert(intr_type_descs[type].handler); + + flag = get_interrupt_rm_flag(INTR_DEFAULT_RM, security_state); + + bit_pos = plat_interrupt_type_to_line(type, security_state); + cm_write_scr_el3_bit(security_state, bit_pos, flag); + + return 0; +} + +/****************************************************************************** + * This function enables the routing model of interrupt 'type' from the + * specified 'security_state' on the local core. + *****************************************************************************/ +int enable_intr_rm_local(uint32_t type, uint32_t security_state) +{ + uint32_t bit_pos, flag; + + assert(intr_type_descs[type].handler); + + flag = get_interrupt_rm_flag(intr_type_descs[type].flags, + security_state); + + bit_pos = plat_interrupt_type_to_line(type, security_state); + cm_write_scr_el3_bit(security_state, bit_pos, flag); + + return 0; +} + +/******************************************************************************* + * This function registers a handler for the 'type' of interrupt specified. It + * also validates the routing model specified in the 'flags' for this type of + * interrupt. + ******************************************************************************/ +int32_t register_interrupt_type_handler(uint32_t type, + interrupt_type_handler_t handler, + uint32_t flags) +{ + int32_t rc; + + /* Validate the 'handler' parameter */ + if (!handler) + return -EINVAL; + + /* Validate the 'flags' parameter */ + if (flags & INTR_TYPE_FLAGS_MASK) + return -EINVAL; + + /* Check if a handler has already been registered */ + if (intr_type_descs[type].handler) + return -EALREADY; + + rc = set_routing_model(type, flags); + if (rc) + return rc; + + /* Save the handler */ + intr_type_descs[type].handler = handler; + + return 0; +} + +/******************************************************************************* + * This function is called when an interrupt is generated and returns the + * handler for the interrupt type (if registered). It returns NULL if the + * interrupt type is not supported or its handler has not been registered. + ******************************************************************************/ +interrupt_type_handler_t get_interrupt_type_handler(uint32_t type) +{ + if (validate_interrupt_type(type)) + return NULL; + + return intr_type_descs[type].handler; +} + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/bl33/runtime_svc.c b/IPL/SDK/v3m/src/Dummy_BL33/bl33/runtime_svc.c new file mode 100644 index 0000000..fd64c82 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/bl33/runtime_svc.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +/******************************************************************************* + * The 'rt_svc_descs' array holds the runtime service descriptors exported by + * services by placing them in the 'rt_svc_descs' linker section. + * The 'rt_svc_descs_indices' array holds the index of a descriptor in the + * 'rt_svc_descs' array. When an SMC arrives, the OEN[29:24] bits and the call + * type[31] bit in the function id are combined to get an index into the + * 'rt_svc_descs_indices' array. This gives the index of the descriptor in the + * 'rt_svc_descs' array which contains the SMC handler. + ******************************************************************************/ +#define RT_SVC_DESCS_START ((uint64_t) (&__RT_SVC_DESCS_START__)) +#define RT_SVC_DESCS_END ((uint64_t) (&__RT_SVC_DESCS_END__)) +uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; +static rt_svc_desc_t *rt_svc_descs; + +/******************************************************************************* + * Simple routine to sanity check a runtime service descriptor before using it + ******************************************************************************/ +static int32_t validate_rt_svc_desc(rt_svc_desc_t *desc) +{ + if (desc == NULL) + return -EINVAL; + + if (desc->start_oen > desc->end_oen) + return -EINVAL; + + if (desc->end_oen >= OEN_LIMIT) + return -EINVAL; + + if (desc->call_type != SMC_TYPE_FAST && desc->call_type != SMC_TYPE_STD) + return -EINVAL; + + /* A runtime service having no init or handle function doesn't make sense */ + if (desc->init == NULL && desc->handle == NULL) + return -EINVAL; + + return 0; +} + +/******************************************************************************* + * This function calls the initialisation routine in the descriptor exported by + * a runtime service. Once a descriptor has been validated, its start & end + * owning entity numbers and the call type are combined to form a unique oen. + * The unique oen is used as an index into the 'rt_svc_descs_indices' array. + * The index of the runtime service descriptor is stored at this index. + ******************************************************************************/ +void runtime_svc_init(void) +{ + int32_t rc = 0; + uint32_t index, start_idx, end_idx; + uint64_t rt_svc_descs_num; + + /* If no runtime services are implemented then simply bail out */ + rt_svc_descs_num = RT_SVC_DESCS_END - RT_SVC_DESCS_START; + rt_svc_descs_num /= sizeof(rt_svc_desc_t); + if (rt_svc_descs_num == 0) + return; + + /* Initialise internal variables to invalid state */ + memset(rt_svc_descs_indices, -1, sizeof(rt_svc_descs_indices)); + + rt_svc_descs = (rt_svc_desc_t *) RT_SVC_DESCS_START; + for (index = 0; index < rt_svc_descs_num; index++) { + + /* + * An invalid descriptor is an error condition since it is + * difficult to predict the system behaviour in the absence + * of this service. + */ + rc = validate_rt_svc_desc(&rt_svc_descs[index]); + if (rc) { + ERROR("Invalid runtime service descriptor 0x%lx (%s)\n", + (uintptr_t) &rt_svc_descs[index], + rt_svc_descs[index].name); + goto error; + } + + /* + * The runtime service may have seperate rt_svc_desc_t + * for its fast smc and standard smc. Since the service itself + * need to be initialized only once, only one of them will have + * an initialisation routine defined. Call the initialisation + * routine for this runtime service, if it is defined. + */ + if (rt_svc_descs[index].init) { + rc = rt_svc_descs[index].init(); + if (rc) { + ERROR("Error initializing runtime service %s\n", + rt_svc_descs[index].name); + continue; + } + } + + /* + * Fill the indices corresponding to the start and end + * owning entity numbers with the index of the + * descriptor which will handle the SMCs for this owning + * entity range. + */ + start_idx = get_unique_oen(rt_svc_descs[index].start_oen, + rt_svc_descs[index].call_type); + end_idx = get_unique_oen(rt_svc_descs[index].end_oen, + rt_svc_descs[index].call_type); + + for (; start_idx <= end_idx; start_idx++) + rt_svc_descs_indices[start_idx] = index; + } + + return; +error: + panic(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/common/aarch64/debug.S b/IPL/SDK/v3m/src/Dummy_BL33/common/aarch64/debug.S new file mode 100644 index 0000000..b3caafb --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/common/aarch64/debug.S @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl asm_print_str + .globl asm_print_hex + .globl asm_assert + .globl do_panic + +/* Since the max decimal input number is 65536 */ +#define MAX_DEC_DIVISOR 10000 +/* The offset to add to get ascii for numerals '0 - 9' */ +#define ASCII_OFFSET_NUM 0x30 + +#if ASM_ASSERTION +.section .rodata.assert_str, "aS" +assert_msg1: + .asciz "ASSERT: File " +assert_msg2: + .asciz " Line " + + /* + * This macro is intended to be used to print the + * line number in decimal. Used by asm_assert macro. + * The max number expected is 65536. + * In: x4 = the decimal to print. + * Clobber: x30, x0, x1, x2, x5, x6 + */ + .macro asm_print_line_dec + mov x6, #10 /* Divide by 10 after every loop iteration */ + mov x5, #MAX_DEC_DIVISOR +dec_print_loop: + udiv x0, x4, x5 /* Get the quotient */ + msub x4, x0, x5, x4 /* Find the remainder */ + add x0, x0, #ASCII_OFFSET_NUM /* Convert to ascii */ + bl plat_crash_console_putc + udiv x5, x5, x6 /* Reduce divisor */ + cbnz x5, dec_print_loop + .endm + + +/* --------------------------------------------------------------------------- + * Assertion support in assembly. + * The below function helps to support assertions in assembly where we do not + * have a C runtime stack. Arguments to the function are : + * x0 - File name + * x1 - Line no + * Clobber list : x30, x0, x1, x2, x3, x4, x5, x6. + * --------------------------------------------------------------------------- + */ +func asm_assert + mov x5, x0 + mov x6, x1 + /* Ensure the console is initialized */ + bl plat_crash_console_init + /* Check if the console is initialized */ + cbz x0, _assert_loop + /* The console is initialized */ + adr x4, assert_msg1 + bl asm_print_str + mov x4, x5 + bl asm_print_str + adr x4, assert_msg2 + bl asm_print_str + /* Check if line number higher than max permitted */ + tst x6, #~0xffff + b.ne _assert_loop + mov x4, x6 + asm_print_line_dec +_assert_loop: + b _assert_loop +endfunc asm_assert +#endif + +/* + * This function prints a string from address in x4. + * In: x4 = pointer to string. + * Clobber: x30, x0, x1, x2, x3 + */ +func asm_print_str + mov x3, x30 +1: + ldrb w0, [x4], #0x1 + cbz x0, 2f + bl plat_crash_console_putc + b 1b +2: + ret x3 +endfunc asm_print_str + +/* + * This function prints a hexadecimal number in x4. + * In: x4 = the hexadecimal to print. + * Clobber: x30, x0, x5, x1, x2, x3 + */ +func asm_print_hex + mov x3, x30 + mov x5, #64 /* No of bits to convert to ascii */ +1: + sub x5, x5, #4 + lsrv x0, x4, x5 + and x0, x0, #0xf + cmp x0, #0xA + b.lo 2f + /* Add by 0x27 in addition to ASCII_OFFSET_NUM + * to get ascii for characters 'a - f'. + */ + add x0, x0, #0x27 +2: + add x0, x0, #ASCII_OFFSET_NUM + bl plat_crash_console_putc + cbnz x5, 1b + ret x3 +endfunc asm_print_hex + + /*********************************************************** + * The common implementation of do_panic for all BL stages + ***********************************************************/ + +.section .rodata.panic_str, "aS" + panic_msg: .asciz "PANIC at PC : 0x" + +/* --------------------------------------------------------------------------- + * do_panic assumes that it is invoked from a C Runtime Environment ie a + * valid stack exists. This call will not return. + * Clobber list : if CRASH_REPORTING is not enabled then x30, x0 - x6 + * --------------------------------------------------------------------------- + */ + +/* This is for the non el3 BL stages to compile through */ + .weak el3_panic + +func do_panic +#if CRASH_REPORTING + str x0, [sp, #-0x10]! + mrs x0, currentel + ubfx x0, x0, #2, #2 + cmp x0, #0x3 + ldr x0, [sp], #0x10 + b.eq el3_panic +#endif + +panic_common: +/* + * el3_panic will be redefined by the BL31 + * crash reporting mechanism (if enabled) + */ +el3_panic: + mov x6, x30 + bl plat_crash_console_init + /* Check if the console is initialized */ + cbz x0, _panic_loop + /* The console is initialized */ + adr x4, panic_msg + bl asm_print_str + mov x4, x6 + /* The panic location is lr -4 */ + sub x4, x4, #4 + bl asm_print_hex +_panic_loop: + b _panic_loop +endfunc do_panic + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/common/aarch64/early_exceptions.S b/IPL/SDK/v3m/src/Dummy_BL33/common/aarch64/early_exceptions.S new file mode 100644 index 0000000..90f5421 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/common/aarch64/early_exceptions.S @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl early_exceptions + + .section .vectors, "ax"; .align 11 + + /* ----------------------------------------------------- + * Very simple stackless exception handlers used by BL2 + * and BL3-1 bootloader stages. BL3-1 uses them before + * stacks are setup. BL2 uses them throughout. + * ----------------------------------------------------- + */ + .align 7 +early_exceptions: + /* ----------------------------------------------------- + * Current EL with SP0 : 0x0 - 0x180 + * ----------------------------------------------------- + */ +SynchronousExceptionSP0: + mov x0, #SYNC_EXCEPTION_SP_EL0 + bl plat_report_exception + b SynchronousExceptionSP0 + check_vector_size SynchronousExceptionSP0 + + .align 7 +IrqSP0: + mov x0, #IRQ_SP_EL0 + bl plat_report_exception + b IrqSP0 + check_vector_size IrqSP0 + + .align 7 +FiqSP0: + mov x0, #FIQ_SP_EL0 + bl plat_report_exception + b FiqSP0 + check_vector_size FiqSP0 + + .align 7 +SErrorSP0: + mov x0, #SERROR_SP_EL0 + bl plat_report_exception + b SErrorSP0 + check_vector_size SErrorSP0 + + /* ----------------------------------------------------- + * Current EL with SPx: 0x200 - 0x380 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionSPx: + mov x0, #SYNC_EXCEPTION_SP_ELX + bl plat_report_exception + b SynchronousExceptionSPx + check_vector_size SynchronousExceptionSPx + + .align 7 +IrqSPx: + mov x0, #IRQ_SP_ELX + bl plat_report_exception + b IrqSPx + check_vector_size IrqSPx + + .align 7 +FiqSPx: + mov x0, #FIQ_SP_ELX + bl plat_report_exception + b FiqSPx + check_vector_size FiqSPx + + .align 7 +SErrorSPx: + mov x0, #SERROR_SP_ELX + bl plat_report_exception + b SErrorSPx + check_vector_size SErrorSPx + + /* ----------------------------------------------------- + * Lower EL using AArch64 : 0x400 - 0x580 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionA64: + mov x0, #SYNC_EXCEPTION_AARCH64 + bl plat_report_exception + b SynchronousExceptionA64 + check_vector_size SynchronousExceptionA64 + + .align 7 +IrqA64: + mov x0, #IRQ_AARCH64 + bl plat_report_exception + b IrqA64 + check_vector_size IrqA64 + + .align 7 +FiqA64: + mov x0, #FIQ_AARCH64 + bl plat_report_exception + b FiqA64 + check_vector_size FiqA64 + + .align 7 +SErrorA64: + mov x0, #SERROR_AARCH64 + bl plat_report_exception + b SErrorA64 + check_vector_size SErrorA64 + + /* ----------------------------------------------------- + * Lower EL using AArch32 : 0x0 - 0x180 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionA32: + mov x0, #SYNC_EXCEPTION_AARCH32 + bl plat_report_exception + b SynchronousExceptionA32 + check_vector_size SynchronousExceptionA32 + + .align 7 +IrqA32: + mov x0, #IRQ_AARCH32 + bl plat_report_exception + b IrqA32 + check_vector_size IrqA32 + + .align 7 +FiqA32: + mov x0, #FIQ_AARCH32 + bl plat_report_exception + b FiqA32 + check_vector_size FiqA32 + + .align 7 +SErrorA32: + mov x0, #SERROR_AARCH32 + bl plat_report_exception + b SErrorA32 + check_vector_size SErrorA32 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/common/bl_common.c b/IPL/SDK/v3m/src/Dummy_BL33/common/bl_common.c new file mode 100644 index 0000000..73c615e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/common/bl_common.c @@ -0,0 +1,354 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +unsigned long page_align(unsigned long value, unsigned dir) +{ + unsigned long page_size = 1 << FOUR_KB_SHIFT; + + /* Round up the limit to the next page boundary */ + if (value & (page_size - 1)) { + value &= ~(page_size - 1); + if (dir == UP) + value += page_size; + } + + return value; +} + +static inline unsigned int is_page_aligned (unsigned long addr) { + const unsigned long page_size = 1 << FOUR_KB_SHIFT; + + return (addr & (page_size - 1)) == 0; +} + +/****************************************************************************** + * Determine whether the memory region delimited by 'addr' and 'size' is free, + * given the extents of free memory. + * Return 1 if it is free, 0 otherwise. + *****************************************************************************/ +static int is_mem_free(uint64_t free_base, size_t free_size, + uint64_t addr, size_t size) +{ + return (addr >= free_base) && (addr + size <= free_base + free_size); +} + +/****************************************************************************** + * Inside a given memory region, determine whether a sub-region of memory is + * closer from the top or the bottom of the encompassing region. Return the + * size of the smallest chunk of free memory surrounding the sub-region in + * 'small_chunk_size'. + *****************************************************************************/ +static unsigned int choose_mem_pos(uint64_t mem_start, uint64_t mem_end, + uint64_t submem_start, uint64_t submem_end, + size_t *small_chunk_size) +{ + size_t top_chunk_size, bottom_chunk_size; + + assert(mem_start <= submem_start); + assert(submem_start <= submem_end); + assert(submem_end <= mem_end); + assert(small_chunk_size != NULL); + + top_chunk_size = mem_end - submem_end; + bottom_chunk_size = submem_start - mem_start; + + if (top_chunk_size < bottom_chunk_size) { + *small_chunk_size = top_chunk_size; + return TOP; + } else { + *small_chunk_size = bottom_chunk_size; + return BOTTOM; + } +} + +/****************************************************************************** + * Reserve the memory region delimited by 'addr' and 'size'. The extents of free + * memory are passed in 'free_base' and 'free_size' and they will be updated to + * reflect the memory usage. + * The caller must ensure the memory to reserve is free. + *****************************************************************************/ +void reserve_mem(uint64_t *free_base, size_t *free_size, + uint64_t addr, size_t size) +{ + size_t discard_size; + size_t reserved_size; + unsigned int pos; + + assert(free_base != NULL); + assert(free_size != NULL); + assert(is_mem_free(*free_base, *free_size, addr, size)); + + pos = choose_mem_pos(*free_base, *free_base + *free_size, + addr, addr + size, + &discard_size); + + reserved_size = size + discard_size; + *free_size -= reserved_size; + + if (pos == BOTTOM) + *free_base = addr + size; + + VERBOSE("Reserved 0x%lx bytes (discarded 0x%lx bytes %s)\n", + reserved_size, discard_size, + pos == TOP ? "above" : "below"); +} + +static void dump_load_info(unsigned long image_load_addr, + unsigned long image_size, + const meminfo_t *mem_layout) +{ + INFO("Trying to load image at address 0x%lx, size = 0x%lx\n", + image_load_addr, image_size); + INFO("Current memory layout:\n"); + INFO(" total region = [0x%lx, 0x%lx]\n", mem_layout->total_base, + mem_layout->total_base + mem_layout->total_size); + INFO(" free region = [0x%lx, 0x%lx]\n", mem_layout->free_base, + mem_layout->free_base + mem_layout->free_size); +} + +/* Generic function to return the size of an image */ +unsigned long image_size(unsigned int image_id) +{ + uintptr_t dev_handle; + uintptr_t image_handle; + uintptr_t image_spec; + size_t image_size = 0; + int io_result = IO_FAIL; + + /* Obtain a reference to the image by querying the platform layer */ + io_result = plat_get_image_source(image_id, &dev_handle, &image_spec); + if (io_result != IO_SUCCESS) { + WARN("Failed to obtain reference to image id=%u (%i)\n", + image_id, io_result); + return 0; + } + + /* Attempt to access the image */ + io_result = io_open(dev_handle, image_spec, &image_handle); + if (io_result != IO_SUCCESS) { + WARN("Failed to access image id=%u (%i)\n", + image_id, io_result); + return 0; + } + + /* Find the size of the image */ + io_result = io_size(image_handle, &image_size); + if ((io_result != IO_SUCCESS) || (image_size == 0)) { + WARN("Failed to determine the size of the image id=%u (%i)\n", + image_id, io_result); + } + io_result = io_close(image_handle); + /* Ignore improbable/unrecoverable error in 'close' */ + + /* TODO: Consider maintaining open device connection from this + * bootloader stage + */ + io_result = io_dev_close(dev_handle); + /* Ignore improbable/unrecoverable error in 'dev_close' */ + + return image_size; +} + +/******************************************************************************* + * Generic function to load an image at a specific address given a name and + * extents of free memory. It updates the memory layout if the load is + * successful, as well as the image information and the entry point information. + * The caller might pass a NULL pointer for the entry point if it is not + * interested in this information, e.g. because the image just needs to be + * loaded in memory but won't ever be executed. + * Returns 0 on success, a negative error code otherwise. + ******************************************************************************/ +int load_image(meminfo_t *mem_layout, + unsigned int image_id, + uintptr_t image_base, + image_info_t *image_data, + entry_point_info_t *entry_point_info) +{ + uintptr_t dev_handle; + uintptr_t image_handle; + uintptr_t image_spec; + size_t image_size; + size_t bytes_read; + int io_result = IO_FAIL; + + assert(mem_layout != NULL); + assert(image_data != NULL); + assert(image_data->h.version >= VERSION_1); + + /* Obtain a reference to the image by querying the platform layer */ + io_result = plat_get_image_source(image_id, &dev_handle, &image_spec); + if (io_result != IO_SUCCESS) { + WARN("Failed to obtain reference to image id=%u (%i)\n", + image_id, io_result); + return io_result; + } + + /* Attempt to access the image */ + io_result = io_open(dev_handle, image_spec, &image_handle); + if (io_result != IO_SUCCESS) { + WARN("Failed to access image id=%u (%i)\n", + image_id, io_result); + return io_result; + } + + INFO("Loading image id=%u at address 0x%lx\n", image_id, image_base); + + /* Find the size of the image */ + io_result = io_size(image_handle, &image_size); + if ((io_result != IO_SUCCESS) || (image_size == 0)) { + WARN("Failed to determine the size of the image id=%u (%i)\n", + image_id, io_result); + goto exit; + } + + /* Check that the memory where the image will be loaded is free */ + if (!is_mem_free(mem_layout->free_base, mem_layout->free_size, + image_base, image_size)) { + WARN("Failed to reserve memory: 0x%lx - 0x%lx\n", + image_base, image_base + image_size); + dump_load_info(image_base, image_size, mem_layout); + io_result = -ENOMEM; + goto exit; + } + + /* We have enough space so load the image now */ + /* TODO: Consider whether to try to recover/retry a partially successful read */ + io_result = io_read(image_handle, image_base, image_size, &bytes_read); + if ((io_result != IO_SUCCESS) || (bytes_read < image_size)) { + WARN("Failed to load image id=%u (%i)\n", image_id, io_result); + goto exit; + } + + /* + * Update the memory usage info. + * This is done after the actual loading so that it is not updated when + * the load is unsuccessful. + * If the caller does not provide an entry point, bypass the memory + * reservation. + */ + if (entry_point_info != NULL) { + reserve_mem(&mem_layout->free_base, &mem_layout->free_size, + image_base, image_size); + } else { + INFO("Skip reserving memory: 0x%lx - 0x%lx\n", + image_base, image_base + image_size); + } + + image_data->image_base = image_base; + image_data->image_size = image_size; + + if (entry_point_info != NULL) + entry_point_info->pc = image_base; + + /* + * File has been successfully loaded. + * Flush the image in TZRAM so that the next EL can see it. + */ + flush_dcache_range(image_base, image_size); + + INFO("Image id=%u loaded: 0x%lx - 0x%lx\n", image_id, image_base, + image_base + image_size); + +exit: + io_close(image_handle); + /* Ignore improbable/unrecoverable error in 'close' */ + + /* TODO: Consider maintaining open device connection from this bootloader stage */ + io_dev_close(dev_handle); + /* Ignore improbable/unrecoverable error in 'dev_close' */ + + return io_result; +} + +/******************************************************************************* + * Generic function to load and authenticate an image. The image is actually + * loaded by calling the 'load_image()' function. In addition, this function + * uses recursion to authenticate the parent images up to the root of trust. + ******************************************************************************/ +int load_auth_image(meminfo_t *mem_layout, + unsigned int image_id, + uintptr_t image_base, + image_info_t *image_data, + entry_point_info_t *entry_point_info) +{ + int rc; + +#if TRUSTED_BOARD_BOOT + unsigned int parent_id; + + /* Use recursion to authenticate parent images */ + rc = auth_mod_get_parent_id(image_id, &parent_id); + if (rc == 0) { + rc = load_auth_image(mem_layout, parent_id, image_base, + image_data, NULL); + if (rc != LOAD_SUCCESS) { + return rc; + } + } +#endif /* TRUSTED_BOARD_BOOT */ + + /* Load the image */ + rc = load_image(mem_layout, image_id, image_base, image_data, + entry_point_info); + if (rc != IO_SUCCESS) { + return LOAD_ERR; + } + +#if TRUSTED_BOARD_BOOT + /* Authenticate it */ + rc = auth_mod_verify_img(image_id, + (void *)image_data->image_base, + image_data->image_size); + if (rc != 0) { + memset((void *)image_data->image_base, 0x00, + image_data->image_size); + flush_dcache_range(image_data->image_base, + image_data->image_size); + return LOAD_AUTH_ERR; + } + + /* After working with data, invalidate the data cache */ + inv_dcache_range(image_data->image_base, + (size_t)image_data->image_size); +#endif /* TRUSTED_BOARD_BOOT */ + + return LOAD_SUCCESS; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/common/tf_printf.c b/IPL/SDK/v3m/src/Dummy_BL33/common/tf_printf.c new file mode 100644 index 0000000..45b756f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/common/tf_printf.c @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +#if (IMAGE_BL31 && PLAT_rcar) +extern void rcar_set_log_time(void); +#endif +/*********************************************************** + * The tf_printf implementation for all BL stages + ***********************************************************/ +static void unsigned_num_print(unsigned long int unum, unsigned int radix) +{ + /* Just need enough space to store 64 bit decimal integer */ + unsigned char num_buf[20]; + int i = 0, rem; + + do { + rem = unum % radix; + if (rem < 0xa) + num_buf[i++] = '0' + rem; + else + num_buf[i++] = 'a' + (rem - 0xa); + } while (unum /= radix); + + while (--i >= 0) + putchar(num_buf[i]); +} + +static void string_print(const char *str) +{ + while (*str) + putchar(*str++); +} + +/******************************************************************* + * Reduced format print for Trusted firmware. + * The following formats are supported by this print + * %x - 32 bit hexadecimal format + * %llx and %lx -64 bit hexadecimal format + * %s - string format + * %d or %i - signed 32 bit decimal format + * %u - unsigned 32 bit decimal format + * %ld and %lld - signed 64 bit decimal format + * %lu and %llu - unsigned 64 bit decimal format + * Exits on all other formats. + *******************************************************************/ + +void tf_printf(const char *fmt, ...) +{ + va_list args; + int bit64; + int64_t num; + uint64_t unum; + char *str; + +#if (IMAGE_BL31 && PLAT_rcar) + rcar_set_log_time(); +#endif + + va_start(args, fmt); + while (*fmt) { + bit64 = 0; + + if (*fmt == '%') { + fmt++; + /* Check the format specifier */ +loop: + switch (*fmt) { + case 'i': /* Fall through to next one */ + case 'd': + if (bit64) + num = va_arg(args, int64_t); + else + num = va_arg(args, int32_t); + + if (num < 0) { + putchar('-'); + unum = (unsigned long int)-num; + } else + unum = (unsigned long int)num; + + unsigned_num_print(unum, 10); + break; + case 's': + str = va_arg(args, char *); + string_print(str); + break; + case 'x': + if (bit64) + unum = va_arg(args, uint64_t); + else + unum = va_arg(args, uint32_t); + + unsigned_num_print(unum, 16); + break; + case 'l': + bit64 = 1; + fmt++; + goto loop; + case 'u': + if (bit64) + unum = va_arg(args, uint64_t); + else + unum = va_arg(args, uint32_t); + + unsigned_num_print(unum, 10); + break; + default: + /* Exit on any other format specifier */ + goto exit; + } + fmt++; + continue; + } + putchar(*fmt++); + } +exit: + va_end(args); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/contributing.md b/IPL/SDK/v3m/src/Dummy_BL33/contributing.md new file mode 100644 index 0000000..6b24fb5 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/contributing.md @@ -0,0 +1,121 @@ +Contributing to ARM Trusted Firmware +==================================== + +Before you start contributing to this project you must sign the ARM +Contributor License Agreement (CLA). + +Individuals who want to contribute their own work must sign and return an +Individual CLA. Companies that want to contribute must sign and return a +Corporate CLA if their employees' intellectual property has been assigned to +the employer. Copies of the CLAs are available from the [contributing page] of +the ARM website. + +For this project, ARM also requires the GitHub account name(s) associated with +each individual contributor or the designated employees of corporate +contributors. Only contributions originating from these accounts will be +considered covered by the CLA. To avoid delay, you should provide the Github +account name(s) at the same time as the signed CLA. + +ARM reserves the right to not accept a contribution. This may be for technical, +commercial or legal reasons. + + +Getting Started +--------------- + +* Make sure you have a [GitHub account]. +* Create an [issue] for your work if one does not already exist. This gives + everyone visibility of whether others are working on something similar. ARM + licensees may contact ARM directly via their partner managers instead if + they prefer. + * Note that the [issue] tracker for this project is in a separate + [issue tracking repository]. Please follow the guidelines in that + repository. + * If you intend to include Third Party IP in your contribution, please + raise a separate [issue] for this and ensure that the changes that + include Third Party IP are made on a separate topic branch. +* [Fork][] [arm-trusted-firmware][] on GitHub. +* Clone the fork to your own machine. +* Create a local topic branch based on the [arm-trusted-firmware][] `master` + branch. + + +Making Changes +-------------- + +* Make commits of logical units. See these general [Git guidelines] for + contributing to a project. +* Follow the [Linux coding style]; this style is enforced for the ARM Trusted + Firmware project (style errors only, not warnings). + * Use the checkpatch.pl script provided with the Linux source tree. A + Makefile target is provided for convenience (see section 2 in the + [User Guide]). +* Keep the commits on topic. If you need to fix another bug or make another + enhancement, please create a separate [issue] and address it on a separate + topic branch. +* Avoid long commit series. If you do have a long series, consider whether + some commits should be squashed together or addressed in a separate topic. +* Make sure your commit messages are in the proper format. If a commit fixes + a GitHub [issue], include a reference (e.g. + "fixes arm-software/tf-issues#45"); this ensures the [issue] is + [automatically closed] when merged into the [arm-trusted-firmware] `master` + branch. +* Where appropriate, please update the documentation. + * Consider whether the [User Guide], [Porting Guide], [Firmware Design] or + other in-source documentation needs updating. + * If this is your first contribution, you may add your name or your + company name to the [Acknowledgements] file. + * For topics with multiple commits, you should make all documentation + changes (and nothing else) in the last commit of the series. Otherwise, + include the documentation changes within the single commit. +* Please test your changes. As a minimum, ensure UEFI boots to the shell on + the Foundation FVP. See the "[Running the software]" section of the + [User Guide] for more information. + + +Submitting Changes +------------------ + +* Ensure we have your signed CLA. +* Push your local changes to your fork of the repository. +* Submit a [pull request] to the [arm-trusted-firmware] `integration` branch. + * The changes in the [pull request] will then undergo further review and + testing. Any review comments will be made as comments on the [pull + request]. This may require you to do some rework. +* When the changes are accepted, ARM will integrate them. + * Typically, ARM will merge the [pull request] into the `integration` + branch within the GitHub UI, creating a merge commit. + * Please avoid creating merge commits in the [pull request] itself. + * If the [pull request] is not based on a recent commit, ARM may rebase + it onto the `master` branch first, or ask you to do this. + * If the [pull request] cannot be automatically merged, ARM will ask you + to rebase it onto the `master` branch. + * After final integration testing, ARM will push your merge commit to the + `master` branch. If a problem is found at this stage, the merge commit + will be removed from the `integration` branch and ARM will ask you to + create a new pull request to resolve the problem. + * Please do not delete your topic branch until it is safely merged into + the `master` branch. + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved._ + + +[User Guide]: ./docs/user-guide.md +[Running the software]: ./docs/user-guide.md#6--running-the-software +[Porting Guide]: ./docs/porting-guide.md +[Firmware Design]: ./docs/firmware-design.md +[Acknowledgements]: ./acknowledgements.md "Contributor acknowledgements" + +[contributing page]: http://www.arm.com/community/open-source-contributing.php +[GitHub account]: https://github.com/signup/free +[Fork]: https://help.github.com/articles/fork-a-repo +[issue tracking repository]: https://github.com/ARM-software/tf-issues +[issue]: https://github.com/ARM-software/tf-issues/issues +[pull request]: https://help.github.com/articles/using-pull-requests +[automatically closed]: https://help.github.com/articles/closing-issues-via-commit-messages +[Git guidelines]: http://git-scm.com/book/ch5-2.html +[Linux coding style]: https://www.kernel.org/doc/Documentation/CodingStyle +[arm-trusted-firmware]: https://github.com/ARM-software/arm-trusted-firmware diff --git a/IPL/SDK/v3m/src/Dummy_BL33/docs/auth-framework.md b/IPL/SDK/v3m/src/Dummy_BL33/docs/auth-framework.md new file mode 100644 index 0000000..488fa26 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/docs/auth-framework.md @@ -0,0 +1,918 @@ +Abstracting a Chain of Trust +============================ + +Contents : + +1. [Introduction](#1--introduction) +2. [Framework design](#2--framework-design) +3. [Specifying a Chain of Trust](#3--specifying-a-chain-of-trust) +4. [Implementation example](#4--implementation-example) + + +1. Introduction +---------------- + +The aim of this document is to describe the authentication framework implemented +in the Trusted Firmware. This framework fulfills the following requirements: + +1. It should be possible for a platform port to specify the Chain of Trust in + terms of certificate hierarchy and the mechanisms used to verify a + particular image/certificate. + +2. The framework should distinguish between: + + - The mechanism used to encode and transport information, e.g. DER encoded + X.509v3 certificates to ferry Subject Public Keys, hashes and non-volatile + counters. + + - The mechanism used to verify the transported information i.e. the + cryptographic libraries. + +The framework has been designed following a modular approach illustrated in the +next diagram: + +``` + +---------------+---------------+------------+ + | Trusted | Trusted | Trusted | + | Firmware | Firmware | Firmware | + | Generic | IO Framework | Platform | + | Code i.e. | (IO) | Port | + | BL1/BL2 (GEN) | | (PP) | + +---------------+---------------+------------+ + ^ ^ ^ + | | | + v v v + +-----------+ +-----------+ +-----------+ + | | | | | Image | + | Crypto | | Auth | | Parser | + | Module |<->| Module |<->| Module | + | (CM) | | (AM) | | (IPM) | + | | | | | | + +-----------+ +-----------+ +-----------+ + ^ ^ + | | + v v + +----------------+ +-----------------+ + | Cryptographic | | Image Parser | + | Libraries (CL) | | Libraries (IPL) | + +----------------+ +-----------------+ + | | + | | + | | + v v + +-----------------+ + | Misc. Libs e.g. | + | ASN.1 decoder | + | | + +-----------------+ + + DIAGRAM 1. +``` + +This document describes the inner details of the authentication framework and +the abstraction mechanisms available to specify a Chain of Trust. + + +2. Framework design +-------------------- + +This section describes some aspects of the framework design and the rationale +behind them. These aspects are key to verify a Chain of Trust. + +### 2.1 Chain of Trust + +A CoT is basically a sequence of authentication images which usually starts with +a root of trust and culminates in a single data image. The following diagram +illustrates how this maps to a CoT for the BL3-1 image described in the +TBBR-Client specification. + +``` + +------------------+ +-------------------+ + | ROTPK/ROTPK Hash |------>| Trusted Key | + +------------------+ | Certificate | + | (Auth Image) | + /+-------------------+ + / | + / | + / | + / | + L v + +------------------+ +-------------------+ + | Trusted World |------>| BL3-1 Key | + | Public Key | | Certificate | + +------------------+ | (Auth Image) | + +-------------------+ + / | + / | + / | + / | + / v + +------------------+ L +-------------------+ + | BL3-1 Content |------>| BL3-1 Content | + | Certificate PK | | Certificate | + +------------------+ | (Auth Image) | + +-------------------+ + / | + / | + / | + / | + / v + +------------------+ L +-------------------+ + | BL3-1 Hash |------>| BL3-1 Image | + | | | (Data Image) | + +------------------+ | | + +-------------------+ + + DIAGRAM 2. +``` + +The root of trust is usually a public key (ROTPK) that has been burnt in the +platform and cannot be modified. + +### 2.2 Image types + +Images in a CoT are categorised as authentication and data images. An +authentication image contains information to authenticate a data image or +another authentication image. A data image is usually a boot loader binary, but +it could be any other data that requires authentication. + +### 2.3 Component responsibilities + +For every image in a Chain of Trust, the following high level operations are +performed to verify it: + +1. Allocate memory for the image either statically or at runtime. + +2. Identify the image and load it in the allocated memory. + +3. Check the integrity of the image as per its type. + +4. Authenticate the image as per the cryptographic algorithms used. + +5. If the image is an authentication image, extract the information that will + be used to authenticate the next image in the CoT. + +In Diagram 1, each component is responsible for one or more of these operations. +The responsibilities are briefly described below. + + +#### 2.2.1 TF Generic code and IO framework (GEN/IO) + +These components are responsible for initiating the authentication process for a +particular image in BL1 or BL2. For each BL image that requires authentication, +the Generic code asks recursively the Authentication module what is the parent +image until either an authenticated image or the ROT is reached. Then the +Generic code calls the IO framewotk to load the image and calls the +Authentication module to authenticate it, following the CoT from ROT to Image. + + +#### 2.2.2 TF Platform Port (PP) + +The platform is responsible for: + +1. Specifying the CoT for each image that needs to be authenticated. Details of + how a CoT can be specified by the platform are explained later. The platform + also specifies the authentication methods and the parsing method used for + each image. + +2. Statically allocating memory for each parameter in each image which is + used for verifying the CoT, e.g. memory for public keys, hashes etc. + +3. Providing the ROTPK or a hash of it. + +4. Providing additional information to the IPM to enable it to identify and + extract authentication parameters contained in an image, e.g. if the + parameters are stored as X509v3 extensions, the corresponding OID must be + provided. + +5. Fulfill any other memory requirements of the IPM and the CM (not currently + described in this document). + +6. Export functions to verify an image which uses an authentication method that + cannot be interpreted by the CM, e.g. if an image has to be verified using a + NV counter, then the value of the counter to compare with can only be + provided by the platform. + +7. Export a custom IPM if a proprietary image format is being used (described + later). + + +#### 2.2.3 Authentication Module (AM) + +It is responsible for: + +1. Providing the necessary abstraction mechanisms to describe a CoT. Amongst + other things, the authentication and image parsing methods must be specified + by the PP in the CoT. + +2. Verifying the CoT passed by GEN by utilising functionality exported by the + PP, IPM and CM. + +3. Tracking which images have been verified. In case an image is a part of + multiple CoTs then it should be verified only once e.g. the Trusted World + Key Certificate in the TBBR-Client spec. contains information to verify + BL3-0, BL3-1, BL3-2 each of which have a separate CoT. (This responsibility + has not been described in this document but should be trivial to implement). + +4. Reusing memory meant for a data image to verify authentication images e.g. + in the CoT described in Diagram 2, each certificate can be loaded and + verified in the memory reserved by the platform for the BL3-1 image. By the + time BL3-1 (the data image) is loaded, all information to authenticate it + will have been extracted from the parent image i.e. BL3-1 content + certificate. It is assumed that the size of an authentication image will + never exceed the size of a data image. It should be possible to verify this + at build time using asserts. + + +#### 2.2.4 Cryptographic Module (CM) + +The CM is responsible for providing an API to: + +1. Verify a digital signature. +2. Verify a hash. + +The CM does not include any cryptography related code, but it relies on an +external library to perform the cryptographic operations. A Crypto-Library (CL) +linking the CM and the external library must be implemented. The following +functions must be provided by the CL: + +``` +void (*init)(void); +int (*verify_signature)(void *data_ptr, unsigned int data_len, + void *sig_ptr, unsigned int sig_len, + void *sig_alg, unsigned int sig_alg_len, + void *pk_ptr, unsigned int pk_len); +int (*verify_hash)(void *data_ptr, unsigned int data_len, + void *digest_info_ptr, unsigned int digest_info_len); +``` + +These functions are registered in the CM using the macro: +``` +REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash); +``` + +`_name` must be a string containing the name of the CL. This name is used for +debugging purposes. + +#### 2.2.5 Image Parser Module (IPM) + +The IPM is responsible for: + +1. Checking the integrity of each image loaded by the IO framework. +2. Extracting parameters used for authenticating an image based upon a + description provided by the platform in the CoT descriptor. + +Images may have different formats (for example, authentication images could be +x509v3 certificates, signed ELF files or any other platform specific format). +The IPM allows to register an Image Parser Library (IPL) for every image format +used in the CoT. This library must implement the specific methods to parse the +image. The IPM obtains the image format from the CoT and calls the right IPL to +check the image integrity and extract the authentication parameters. + +See Section "Describing the image parsing methods" for more details about the +mechanism the IPM provides to define and register IPLs. + + +### 2.3 Authentication methods + +The AM supports the following authentication methods: + +1. Hash +2. Digital signature + +The platform may specify these methods in the CoT in case it decides to define +a custom CoT instead of reusing a predefined one. + +If a data image uses multiple methods, then all the methods must be a part of +the same CoT. The number and type of parameters are method specific. These +parameters should be obtained from the parent image using the IPM. + +1. Hash + + Parameters: + + 1. A pointer to data to hash + 2. Length of the data + 4. A pointer to the hash + 5. Length of the hash + + The hash will be represented by the DER encoding of the following ASN.1 + type: + + ``` + DigestInfo ::= SEQUENCE { + digestAlgorithm DigestAlgorithmIdentifier, + digest Digest + } + ``` + + This ASN.1 structure makes it possible to remove any assumption about the + type of hash algorithm used as this information accompanies the hash. This + should allow the Cryptography Library (CL) to support multiple hash + algorithm implementations. + +2. Digital Signature + + Parameters: + + 1. A pointer to data to sign + 2. Length of the data + 3. Public Key Algorithm + 4. Public Key value + 5. Digital Signature Algorithm + 6. Digital Signature value + + The Public Key parameters will be represented by the DER encoding of the + following ASN.1 type: + + ``` + SubjectPublicKeyInfo ::= SEQUENCE { + algorithm AlgorithmIdentifier{PUBLIC-KEY,{PublicKeyAlgorithms}}, + subjectPublicKey BIT STRING } + ``` + + The Digital Signature Algorithm will be represented by the DER encoding of + the following ASN.1 types. + + ``` + AlgorithmIdentifier {ALGORITHM:IOSet } ::= SEQUENCE { + algorithm ALGORITHM.&id({IOSet}), + parameters ALGORITHM.&Type({IOSet}{@algorithm}) OPTIONAL + } + ``` + + The digital signature will be represented by: + ``` + signature ::= BIT STRING + ``` + +The authentication framework will use the image descriptor to extract all the +information related to authentication. + + +3. Specifying a Chain of Trust +------------------------------- + +A CoT can be described as a set of image descriptors linked together in a +particular order. The order dictates the sequence in which they must be +verified. Each image has a set of properties which allow the AM to verify it. +These properties are described below. + +The PP is responsible for defining a single or multiple CoTs for a data image. +Unless otherwise specified, the data structures described in the following +sections are populated by the PP statically. + + +### 3.1 Describing the image parsing methods + +The parsing method refers to the format of a particular image. For example, an +authentication image that represents a certificate could be in the X.509v3 +format. A data image that represents a boot loader stage could be in raw binary +or ELF format. The IPM supports three parsing methods. An image has to use one +of the three methods described below. An IPL is responsible for interpreting a +single parsing method. There has to be one IPL for every method used by the +platform. + +1. Raw format: This format is effectively a nop as an image using this method + is treated as being in raw binary format e.g. boot loader images used by ARM + TF. This method should only be used by data images. + +2. X509V3 method: This method uses industry standards like X.509 to represent + PKI certificates (authentication images). It is expected that open source + libraries will be available which can be used to parse an image represented + by this method. Such libraries can be used to write the corresponding IPL + e.g. the X.509 parsing library code in PolarSSL. + +3. Platform defined method: This method caters for platform specific + proprietary standards to represent authentication or data images. For + example, The signature of a data image could be appended to the data image + raw binary. A header could be prepended to the combined blob to specify the + extents of each component. The platform will have to implement the + corresponding IPL to interpret such a format. + +The following enum can be used to define these three methods. + +``` +typedef enum img_type_enum { + IMG_RAW, /* Binary image */ + IMG_PLAT, /* Platform specific format */ + IMG_CERT, /* X509v3 certificate */ + IMG_MAX_TYPES, +} img_type_t; +``` + +An IPL must provide functions with the following prototypes: + +``` +void init(void); +int check_integrity(void *img, unsigned int img_len); +int get_auth_param(const auth_param_type_desc_t *type_desc, + void *img, unsigned int img_len, + void **param, unsigned int *param_len); +``` + +An IPL for each type must be registered using the following macro: + +``` +REGISTER_IMG_PARSER_LIB(_type, _name, _init, _check_int, _get_param) +``` + +* `_type`: one of the types described above. +* `_name`: a string containing the IPL name for debugging purposes. +* `_init`: initialization function pointer. +* `_check_int`: check image integrity function pointer. +* `_get_param`: extract authentication parameter funcion pointer. + +The `init()` function will be used to initialize the IPL. + +The `check_integrity()` function is passed a pointer to the memory where the +image has been loaded by the IO framework and the image length. It should ensure +that the image is in the format corresponding to the parsing method and has not +been tampered with. For example, RFC-2459 describes a validation sequence for an +X.509 certificate. + +The `get_auth_param()` function is passed a parameter descriptor containing +information about the parameter (`type_desc` and `cookie`) to identify and +extract the data corresponding to that parameter from an image. This data will +be used to verify either the current or the next image in the CoT sequence. + +Each image in the CoT will specify the parsing method it uses. This information +will be used by the IPM to find the right parser descriptor for the image. + + +### 3.2 Describing the authentication method(s) + +As part of the CoT, each image has to specify one or more authentication methods +which will be used to verify it. As described in the Section "Authentication +methods", there are three methods supported by the AM. + +``` +typedef enum { + AUTH_METHOD_NONE, + AUTH_METHOD_HASH, + AUTH_METHOD_SIG, + AUTH_METHOD_NUM +} auth_method_type_t; +``` + +The AM defines the type of each parameter used by an authentication method. It +uses this information to: + +1. Specify to the `get_auth_param()` function exported by the IPM, which + parameter should be extracted from an image. + +2. Correctly marshall the parameters while calling the verification function + exported by the CM and PP. + +3. Extract authentication parameters from a parent image in order to verify a + child image e.g. to verify the certificate image, the public key has to be + obtained from the parent image. + +``` +typedef enum { + AUTH_PARAM_NONE, + AUTH_PARAM_RAW_DATA, /* Raw image data */ + AUTH_PARAM_SIG, /* The image signature */ + AUTH_PARAM_SIG_ALG, /* The image signature algorithm */ + AUTH_PARAM_HASH, /* A hash (including the algorithm) */ + AUTH_PARAM_PUB_KEY, /* A public key */ +} auth_param_type_t; +``` + +The AM defines the following structure to identify an authentication parameter +required to verify an image. + +``` +typedef struct auth_param_type_desc_s { + auth_param_type_t type; + void *cookie; +} auth_param_type_desc_t; +``` + +`cookie` is used by the platform to specify additional information to the IPM +which enables it to uniquely identify the parameter that should be extracted +from an image. For example, the hash of a BL3-x image in its corresponding +content certificate is stored in an X509v3 custom extension field. An extension +field can only be identified using an OID. In this case, the `cookie` could +contain the pointer to the OID defined by the platform for the hash extension +field while the `type` field could be set to `AUTH_PARAM_HASH`. A value of 0 for +the `cookie` field means that it is not used. + +For each method, the AM defines a structure with the parameters required to +verify the image. + +``` +/* + * Parameters for authentication by hash matching + */ +typedef struct auth_method_param_hash_s { + auth_param_type_desc_t *data; /* Data to hash */ + auth_param_type_desc_t *hash; /* Hash to match with */ +} auth_method_param_hash_t; + +/* + * Parameters for authentication by signature + */ +typedef struct auth_method_param_sig_s { + auth_param_type_desc_t *pk; /* Public key */ + auth_param_type_desc_t *sig; /* Signature to check */ + auth_param_type_desc_t *alg; /* Signature algorithm */ + auth_param_type_desc_t *tbs; /* Data signed */ +} auth_method_param_sig_t; + +``` + +The AM defines the following structure to describe an authentication method for +verifying an image + +``` +/* + * Authentication method descriptor + */ +typedef struct auth_method_desc_s { + auth_method_type_t type; + union { + auth_method_param_hash_t hash; + auth_method_param_sig_t sig; + } param; +} auth_method_desc_t; +``` + +Using the method type specified in the `type` field, the AM finds out what field +needs to access within the `param` union. + +### 3.3 Storing Authentication parameters + +A parameter described by `auth_param_type_desc_t` to verify an image could be +obtained from either the image itself or its parent image. The memory allocated +for loading the parent image will be reused for loading the child image. Hence +parameters which are obtained from the parent for verifying a child image need +to have memory allocated for them separately where they can be stored. This +memory must be statically allocated by the platform port. + +The AM defines the following structure to store the data corresponding to an +authentication parameter. + +``` +typedef struct auth_param_data_desc_s { + void *auth_param_ptr; + unsigned int auth_param_len; +} auth_param_data_desc_t; +``` + +The `auth_param_ptr` field is initialized by the platform. The `auth_param_len` +field is used to specify the length of the data in the memory. + +For parameters that can be obtained from the child image itself, the IPM is +responsible for populating the `auth_param_ptr` and `auth_param_len` fields +while executing the `img_get_auth_param()` function. + +The AM defines the following structure to enable an image to describe the +parameters that should be extracted from it and used to verify the next image +(child) in a CoT. + +``` +typedef struct auth_param_desc_s { + auth_param_type_desc_t type_desc; + auth_param_data_desc_t data; +} auth_param_desc_t; +``` + +### 3.4 Describing an image in a CoT + +An image in a CoT is a consolidation of the following aspects of a CoT described +above. + +1. A unique identifier specified by the platform which allows the IO framework + to locate the image in a FIP and load it in the memory reserved for the data + image in the CoT. + +2. A parsing method which is used by the AM to find the appropriate IPM. + +3. Authentication methods and their parameters as described in the previous + section. These are used to verify the current image. + +4. Parameters which are used to verify the next image in the current CoT. These + parameters are specified only by authentication images and can be extracted + from the current image once it has been verified. + +The following data structure describes an image in a CoT. +``` +typedef struct auth_img_desc_s { + unsigned int img_id; + const struct auth_img_desc_s *parent; + img_type_t img_type; + auth_method_desc_t img_auth_methods[AUTH_METHOD_NUM]; + auth_param_desc_t authenticated_data[COT_MAX_VERIFIED_PARAMS]; +} auth_img_desc_t; +``` +A CoT is defined as an array of `auth_image_desc_t` structures linked together +by the `parent` field. Those nodes with no parent must be authenticated using +the ROTPK stored in the platform. + + +4. Implementation example +-------------------------- + +This section is a detailed guide explaining a trusted boot implementation using +the authentication framework. This example corresponds to the Applicative +Functional Mode (AFM) as specified in the TBBR-Client document. It is +recommended to read this guide along with the source code. + +### 4.1 The TBBR CoT + +The CoT can be found in `drivers/auth/tbbr/tbbr_cot.c`. This CoT consists of an +array of image descriptors and it is registered in the framework using the macro +`REGISTER_COT(cot_desc)`, where 'cot_desc' must be the name of the array +(passing a pointer or any other type of indirection will cause the registration +process to fail). + +The number of images participating in the boot process depends on the CoT. There +is, however, a minimum set of images that are mandatory in the Trusted Firmware +and thus all CoTs must present: + +* `BL2` +* `BL3-0` (platform specific) +* `BL3-1` +* `BL3-2` (optional) +* `BL3-3` + +The TBBR specifies the additional certificates that must accompany these images +for a proper authentication. Details about the TBBR CoT may be found in the +[Trusted Board Boot] document. + +Following the [Platform Porting Guide], a platform must provide unique +identifiers for all the images and certificates that will be loaded during the +boot process. If a platform is using the TBBR as a reference for trusted boot, +these identifiers can be obtained from `include/common/tbbr/tbbr_img_def.h`. +ARM platforms include this file in `include/plat/arm/common/arm_def.h`. Other +platforms may also include this file or provide their own identifiers. + +**Important**: the authentication module uses these identifiers to index the +CoT array, so the descriptors location in the array must match the identifiers. + +Each image descriptor must specify: + +* `img_id`: the corresponding image unique identifier defined by the platform. +* `img_type`: the image parser module uses the image type to call the proper + parsing library to check the image integrity and extract the required + authentication parameters. Three types of images are currently supported: + * `IMG_RAW`: image is a raw binary. No parsing functions are available, + other than reading the whole image. + * `IMG_PLAT`: image format is platform specific. The platform may use this + type for custom images not directly supported by the authentication + framework. + * `IMG_CERT`: image is an x509v3 certificate. +* `parent`: pointer to the parent image descriptor. The parent will contain + the information required to authenticate the current image. If the parent + is NULL, the authentication parameters will be obtained from the platform + (i.e. the BL2 and Trusted Key certificates are signed with the ROT private + key, whose public part is stored in the platform). +* `img_auth_methods`: this array defines the authentication methods that must + be checked to consider an image authenticated. Each method consists of a + type and a list of parameter descriptors. A parameter descriptor consists of + a type and a cookie which will point to specific information required to + extract that parameter from the image (i.e. if the parameter is stored in an + x509v3 extension, the cookie will point to the extension OID). Depending on + the method type, a different number of parameters must be specified. + Supported methods are: + * `AUTH_METHOD_HASH`: the hash of the image must match the hash extracted + from the parent image. The following parameter descriptors must be + specified: + * `data`: data to be hashed (obtained from current image) + * `hash`: reference hash (obtained from parent image) + * `AUTH_METHOD_SIG`: the image (usually a certificate) must be signed with + the private key whose public part is extracted from the parent image (or + the platform if the parent is NULL). The following parameter descriptors + must be specified: + * `pk`: the public key (obtained from parent image) + * `sig`: the digital signature (obtained from current image) + * `alg`: the signature algorithm used (obtained from current image) + * `data`: the data to be signed (obtained from current image) +* `authenticated_data`: this array indicates what authentication parameters + must be extracted from an image once it has been authenticated. Each + parameter consists of a parameter descriptor and the buffer address/size + to store the parameter. The CoT is responsible for allocating the required + memory to store the parameters. + +In the `tbbr_cot.c` file, a set of buffers are allocated to store the parameters +extracted from the certificates. In the case of the TBBR CoT, these parameters +are hashes and public keys. In DER format, an RSA-2048 public key requires 294 +bytes, and a hash requires 51 bytes. Depending on the CoT and the authentication +process, some of the buffers may be reused at different stages during the boot. + +Next in that file, the parameter descriptors are defined. These descriptors will +be used to extract the parameter data from the corresponding image. + +#### 4.1.1 Example: the BL3-1 Chain of Trust + +Four image descriptors form the BL3-1 Chain of Trust: + +``` +[TRUSTED_KEY_CERT_ID] = { + .img_id = TRUSTED_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = NULL, + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &subject_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &tz_world_pk, + .data = { + .ptr = (void *)plat_tz_world_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + }, + [1] = { + .type_desc = &ntz_world_pk, + .data = { + .ptr = (void *)plat_ntz_world_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + } + } +}, +[BL31_KEY_CERT_ID] = { + .img_id = BL31_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[TRUSTED_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &tz_world_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &bl31_content_pk, + .data = { + .ptr = (void *)plat_content_pk, + .len = (unsigned int)PK_DER_LEN + } + } + } +}, +[BL31_CERT_ID] = { + .img_id = BL31_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[BL31_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &bl31_content_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &bl31_hash, + .data = { + .ptr = (void *)plat_bl31_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } +}, +[BL31_IMAGE_ID] = { + .img_id = BL31_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[BL31_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &bl31_hash, + } + } + } +} +``` +The **Trusted Key certificate** is signed with the ROT private key and contains +the Trusted World public key and the Non-Trusted World public key as x509v3 +extensions. This must be specified in the image descriptor using the +`img_auth_methods` and `authenticated_data` arrays, respectively. + +The Trusted Key certificate is authenticated by checking its digital signature +using the ROTPK. Four parameters are required to check a signature: the public +key, the algorithm, the signature and the data that has been signed. Therefore, +four parameter descriptors must be specified with the authentication method: + +* `subject_pk`: parameter descriptor of type `AUTH_PARAM_PUB_KEY`. This type + is used to extract a public key from the parent image. If the cookie is an + OID, the key is extracted from the corresponding x509v3 extension. If the + cookie is NULL, the subject public key is retrieved. In this case, because + the parent image is NULL, the public key is obtained from the platform + (this key will be the ROTPK). +* `sig`: parameter descriptor of type `AUTH_PARAM_SIG`. It is used to extract + the signature from the certificate. +* `sig_alg`: parameter descriptor of type `AUTH_PARAM_SIG`. It is used to + extract the signature algorithm from the certificate. +* `raw_data`: parameter descriptor of type `AUTH_PARAM_RAW_DATA`. It is used + to extract the data to be signed from the certificate. + +Once the signature has been checked and the certificate authenticated, the +Trusted World public key needs to be extracted from the certificate. A new entry +is created in the `authenticated_data` array for that purpose. In that entry, +the corresponding parameter descriptor must be specified along with the buffer +address to store the parameter value. In this case, the `tz_world_pk` descriptor +is used to extract the public key from an x509v3 extension with OID +`TZ_WORLD_PK_OID`. The BL3-1 key certificate will use this descriptor as +parameter in the signature authentication method. The key is stored in the +`plat_tz_world_pk_buf` buffer. + +The **BL3-1 Key certificate** is authenticated by checking its digital signature +using the Trusted World public key obtained previously from the Trusted Key +certificate. In the image descriptor, we specify a single authentication method +by signature whose public key is the `tz_world_pk`. Once this certificate has +been authenticated, we have to extract the BL3-1 public key, stored in the +extension specified by `bl31_content_pk`. This key will be copied to the +`plat_content_pk` buffer. + +The **BL3-1 certificate** is authenticated by checking its digital signature +using the BL3-1 public key obtained previously from the BL3-1 Key certificate. +We specify the authentication method using `bl31_content_pk` as public key. +After authentication, we need to extract the BL3-1 hash, stored in the extension +specified by `bl31_hash`. This hash will be copied to the `plat_bl31_hash_buf` +buffer. + +The **BL3-1 image** is authenticated by calculating its hash and matching it +with the hash obtained from the BL3-1 certificate. The image descriptor contains +a single authentication method by hash. The parameters to the hash method are +the reference hash, `bl31_hash`, and the data to be hashed. In this case, it is +the whole image, so we specify `raw_data`. + +### 4.2 The image parser library + +The image parser module relies on libraries to check the image integrity and +extract the authentication parameters. The number and type of parser libraries +depend on the images used in the CoT. Raw images do not need a library, so +only an x509v3 library is required for the TBBR CoT. + +ARM platforms will use an x509v3 library based on mbedTLS. This library may be +found in `drivers/auth/mbedtls/mbedtls_x509_parser.c`. It exports three +functions: + +``` +void init(void); +int check_integrity(void *img, unsigned int img_len); +int get_auth_param(const auth_param_type_desc_t *type_desc, + void *img, unsigned int img_len, + void **param, unsigned int *param_len); +``` + +The library is registered in the framework using the macro +`REGISTER_IMG_PARSER_LIB()`. Each time the image parser module needs to access +an image of type `IMG_CERT`, it will call the corresponding function exported +in this file. + +The build system must be updated to include the corresponding library and +mbedTLS sources. ARM platforms use the `arm_common.mk` file to pull the sources. + +### 4.3 The cryptographic library + +The cryptographic module relies on a library to perform the required operations, +i.e. verify a hash or a digital signature. ARM platforms will use a library +based on mbedTLS, which can be found in `drivers/auth/mbedtls/mbedtls_crypto.c`. +This library is registered in the authentication framework using the macro +`REGISTER_CRYPTO_LIB()` and exports three functions: + +``` +void init(void); +int verify_signature(void *data_ptr, unsigned int data_len, + void *sig_ptr, unsigned int sig_len, + void *sig_alg, unsigned int sig_alg_len, + void *pk_ptr, unsigned int pk_len); +int verify_hash(void *data_ptr, unsigned int data_len, + void *digest_info_ptr, unsigned int digest_info_len); +``` + +The key algorithm (rsa, ecdsa) must be specified in the build system using the +`MBEDTLS_KEY_ALG` variable, so the Makefile can include the corresponding +sources in the build. + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2015, ARM Limited and Contributors. All rights reserved._ + + +[Trusted Board Boot]: ./trusted-board-boot.md +[Platform Porting Guide]: ./porting-guide.md diff --git a/IPL/SDK/v3m/src/Dummy_BL33/docs/change-log.md b/IPL/SDK/v3m/src/Dummy_BL33/docs/change-log.md new file mode 100644 index 0000000..c7b5508 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/docs/change-log.md @@ -0,0 +1,710 @@ +ARM Trusted Firmware - version 1.1 +================================== + +New features +------------ + +* A prototype implementation of Trusted Board Boot has been added. Boot + loader images are verified by BL1 and BL2 during the cold boot path. BL1 and + BL2 use the PolarSSL SSL library to verify certificates and images. The + OpenSSL library is used to create the X.509 certificates. Support has been + added to `fip_create` tool to package the certificates in a FIP. + +* Support for calling CPU and platform specific reset handlers upon entry into + BL3-1 during the cold and warm boot paths has been added. This happens after + another Boot ROM `reset_handler()` has already run. This enables a developer + to perform additional actions or undo actions already performed during the + first call of the reset handlers e.g. apply additional errata workarounds. + +* Support has been added to demonstrate routing of IRQs to EL3 instead of + S-EL1 when execution is in secure world. + +* The PSCI implementation now conforms to version 1.0 of the PSCI + specification. All the mandatory APIs and selected optional APIs are + supported. In particular, support for the `PSCI_FEATURES` API has been + added. A capability variable is constructed during initialization by + examining the `plat_pm_ops` and `spd_pm_ops` exported by the platform and + the Secure Payload Dispatcher. This is used by the PSCI FEATURES function + to determine which PSCI APIs are supported by the platform. + +* Improvements have been made to the PSCI code as follows. + + * The code has been refactored to remove redundant parameters from + internal functions. + + * Changes have been made to the code for PSCI `CPU_SUSPEND`, `CPU_ON` and + `CPU_OFF` calls to facilitate an early return to the caller in case a + failure condition is detected. For example, a PSCI `CPU_SUSPEND` call + returns `SUCCESS` to the caller if a pending interrupt is detected early + in the code path. + + * Optional platform APIs have been added to validate the `power_state` and + `entrypoint` parameters early in PSCI `CPU_ON` and `CPU_SUSPEND` code + paths. + + * PSCI migrate APIs have been reworked to invoke the SPD hook to determine + the type of Trusted OS and the CPU it is resident on (if + applicable). Also, during a PSCI `MIGRATE` call, the SPD hook to migrate + the Trusted OS is invoked. + +* It is now possible to build Trusted Firmware without marking at least an + extra page of memory as coherent. The build flag `USE_COHERENT_MEM` can be + used to choose between the two implementations. This has been made possible + through these changes. + + * An implementation of Bakery locks, where the locks are not allocated in + coherent memory has been added. + + * Memory which was previously marked as coherent is now kept coherent + through the use of software cache maintenance operations. + + Approximately, 4K worth of memory is saved for each boot loader stage when + `USE_COHERENT_MEM=0`. Enabling this option increases the latencies + associated with acquire and release of locks. It also requires changes to + the platform ports. + +* It is now possible to specify the name of the FIP at build time by defining + the `FIP_NAME` variable. + +* Issues with depedencies on the 'fiptool' makefile target have been + rectified. The `fip_create` tool is now rebuilt whenever its source files + change. + +* The BL3-1 runtime console is now also used as the crash console. The crash + console is changed to SoC UART0 (UART2) from the previous FPGA UART0 (UART0) + on Juno. In FVP, it is changed from UART0 to UART1. + +* CPU errata workarounds are applied only when the revision and part number + match. This behaviour has been made consistent across the debug and release + builds. The debug build additionally prints a warning if a mismatch is + detected. + +* It is now possible to issue cache maintenance operations by set/way for a + particular level of data cache. Levels 1-3 are currently supported. + +* The following improvements have been made to the FVP port. + + * The build option `FVP_SHARED_DATA_LOCATION` which allowed relocation of + shared data into the Trusted DRAM has been deprecated. Shared data is + now always located at the base of Trusted SRAM. + + * BL2 Translation tables have been updated to map only the region of + DRAM which is accessible to normal world. This is the region of the 2GB + DDR-DRAM memory at 0x80000000 excluding the top 16MB. The top 16MB is + accessible to only the secure world. + + * BL3-2 can now reside in the top 16MB of DRAM which is accessible only to + the secure world. This can be done by setting the build flag + `FVP_TSP_RAM_LOCATION` to the value `dram`. + +* Separate transation tables are created for each boot loader image. The + `IMAGE_BLx` build options are used to do this. This allows each stage to + create mappings only for areas in the memory map that it needs. + +* A Secure Payload Dispatcher (OPTEED) for the OP-TEE Trusted OS has been + added. Details of using it with ARM Trusted Firmware can be found in + [OP-TEE Dispatcher] + + + +Issues resolved since last release +---------------------------------- + +* The Juno port has been aligned with the FVP port as follows. + + * Support for reclaiming all BL1 RW memory and BL2 memory by overlaying + the BL3-1/BL3-2 NOBITS sections on top of them has been added to the + Juno port. + + * The top 16MB of the 2GB DDR-DRAM memory at 0x80000000 is configured + using the TZC-400 controller to be accessible only to the secure world. + + * The ARM GIC driver is used to configure the GIC-400 instead of using a + GIC driver private to the Juno port. + + * PSCI `CPU_SUSPEND` calls that target a standby state are now supported. + + * The TZC-400 driver is used to configure the controller instead of direct + accesses to the registers. + +* The Linux kernel version referred to in the user guide has DVFS and HMP + support enabled. + +* DS-5 v5.19 did not detect Version 5.8 of the Cortex-A57-A53 Base FVPs in + CADI server mode. This issue is not seen with DS-5 v5.20 and Version 6.2 of + the Cortex-A57-A53 Base FVPs. + + +Known issues +------------ + +* The Trusted Board Boot implementation is a prototype. There are issues with + the modularity and scalability of the design. Support for a Trusted + Watchdog, firmware update mechanism, recovery images and Trusted debug is + absent. These issues will be addressed in future releases. + +* The FVP and Juno ports do not use the hash of the ROTPK stored in the + Trusted Key Storage registers to verify the ROTPK in the + `plat_match_rotpk()` function. This prevents the correct establishment of + the Chain of Trust at the first step in the Trusted Board Boot process. + +* The version of the AEMv8 Base FVP used in this release resets the model + instead of terminating its execution in response to a shutdown request using + the PSCI `SYSTEM_OFF` API. This issue will be fixed in a future version of + the model. + +* GICv3 support is experimental. There are known issues with GICv3 + initialization in the ARM Trusted Firmware. + +* While this version greatly reduces the on-chip RAM requirements, there are + further RAM usage enhancements that could be made. + +* The firmware design documentation for the Test Secure-EL1 Payload (TSP) and + its dispatcher (TSPD) is incomplete. Similarly for the PSCI section. + +* The Juno-specific firmware design documentation is incomplete. + + +ARM Trusted Firmware - version 1.0 +================================== + +New features +------------ + +* It is now possible to map higher physical addresses using non-flat virtual + to physical address mappings in the MMU setup. + +* Wider use is now made of the per-CPU data cache in BL3-1 to store: + + * Pointers to the non-secure and secure security state contexts. + + * A pointer to the CPU-specific operations. + + * A pointer to PSCI specific information (for example the current power + state). + + * A crash reporting buffer. + +* The following RAM usage improvements result in a BL3-1 RAM usage reduction + from 96KB to 56KB (for FVP with TSPD), and a total RAM usage reduction + across all images from 208KB to 88KB, compared to the previous release. + + * Removed the separate `early_exception` vectors from BL3-1 (2KB code size + saving). + + * Removed NSRAM from the FVP memory map, allowing the removal of one + (4KB) translation table. + + * Eliminated the internal `psci_suspend_context` array, saving 2KB. + + * Correctly dimensioned the PSCI `aff_map_node` array, saving 1.5KB in the + FVP port. + + * Removed calling CPU mpidr from the bakery lock API, saving 160 bytes. + + * Removed current CPU mpidr from PSCI common code, saving 160 bytes. + + * Inlined the mmio accessor functions, saving 360 bytes. + + * Fully reclaimed all BL1 RW memory and BL2 memory on the FVP port by + overlaying the BL3-1/BL3-2 NOBITS sections on top of these at runtime. + + * Made storing the FP register context optional, saving 0.5KB per context + (8KB on the FVP port, with TSPD enabled and running on 8 CPUs). + + * Implemented a leaner `tf_printf()` function, allowing the stack to be + greatly reduced. + + * Removed coherent stacks from the codebase. Stacks allocated in normal + memory are now used before and after the MMU is enabled. This saves 768 + bytes per CPU in BL3-1. + + * Reworked the crash reporting in BL3-1 to use less stack. + + * Optimized the EL3 register state stored in the `cpu_context` structure + so that registers that do not change during normal execution are + re-initialized each time during cold/warm boot, rather than restored + from memory. This saves about 1.2KB. + + * As a result of some of the above, reduced the runtime stack size in all + BL images. For BL3-1, this saves 1KB per CPU. + +* PSCI SMC handler improvements to correctly handle calls from secure states + and from AArch32. + +* CPU contexts are now initialized from the `entry_point_info`. BL3-1 fully + determines the exception level to use for the non-trusted firmware (BL3-3) + based on the SPSR value provided by the BL2 platform code (or otherwise + provided to BL3-1). This allows platform code to directly run non-trusted + firmware payloads at either EL2 or EL1 without requiring an EL2 stub or OS + loader. + +* Code refactoring improvements: + + * Refactored `fvp_config` into a common platform header. + + * Refactored the fvp gic code to be a generic driver that no longer has an + explicit dependency on platform code. + + * Refactored the CCI-400 driver to not have dependency on platform code. + + * Simplified the IO driver so it's no longer necessary to call `io_init()` + and moved all the IO storage framework code to one place. + + * Simplified the interface the the TZC-400 driver. + + * Clarified the platform porting interface to the TSP. + + * Reworked the TSPD setup code to support the alternate BL3-2 + intialization flow where BL3-1 generic code hands control to BL3-2, + rather than expecting the TSPD to hand control directly to BL3-2. + + * Considerable rework to PSCI generic code to support CPU specific + operations. + +* Improved console log output, by: + + * Adding the concept of debug log levels. + + * Rationalizing the existing debug messages and adding new ones. + + * Printing out the version of each BL stage at runtime. + + * Adding support for printing console output from assembler code, + including when a crash occurs before the C runtime is initialized. + +* Moved up to the latest versions of the FVPs, toolchain, EDK2, kernel, Linaro + file system and DS-5. + +* On the FVP port, made the use of the Trusted DRAM region optional at build + time (off by default). Normal platforms will not have such a "ready-to-use" + DRAM area so it is not a good example to use it. + +* Added support for PSCI `SYSTEM_OFF` and `SYSTEM_RESET` APIs. + +* Added support for CPU specific reset sequences, power down sequences and + register dumping during crash reporting. The CPU specific reset sequences + include support for errata workarounds. + +* Merged the Juno port into the master branch. Added support for CPU hotplug + and CPU idle. Updated the user guide to describe how to build and run on the + Juno platform. + + +Issues resolved since last release +---------------------------------- + +* Removed the concept of top/bottom image loading. The image loader now + automatically detects the position of the image inside the current memory + layout and updates the layout to minimize fragementation. This resolves the + image loader limitations of previously releases. There are currently no + plans to support dynamic image loading. + +* CPU idle now works on the publicized version of the Foundation FVP. + +* All known issues relating to the compiler version used have now been + resolved. This TF version uses Linaro toolchain 14.07 (based on GCC 4.9). + + +Known issues +------------ + +* GICv3 support is experimental. The Linux kernel patches to support this are + not widely available. There are known issues with GICv3 initialization in + the ARM Trusted Firmware. + +* While this version greatly reduces the on-chip RAM requirements, there are + further RAM usage enhancements that could be made. + +* The firmware design documentation for the Test Secure-EL1 Payload (TSP) and + its dispatcher (TSPD) is incomplete. Similarly for the PSCI section. + +* The Juno-specific firmware design documentation is incomplete. + +* Some recent enhancements to the FVP port have not yet been translated into + the Juno port. These will be tracked via the tf-issues project. + +* The Linux kernel version referred to in the user guide has DVFS and HMP + support disabled due to some known instabilities at the time of this + release. A future kernel version will re-enable these features. + +* DS-5 v5.19 does not detect Version 5.8 of the Cortex-A57-A53 Base FVPs in + CADI server mode. This is because the `` reported by the FVP in + this version has changed. For example, for the Cortex-A57x4-A53x4 Base FVP, + the `` reported by the FVP is `FVP_Base_Cortex_A57x4_A53x4`, while + DS-5 expects it to be `FVP_Base_A57x4_A53x4`. + + The temporary fix to this problem is to change the name of the FVP in + `sw/debugger/configdb/Boards/ARM FVP/Base_A57x4_A53x4/cadi_config.xml`. + Change the following line: + + System Generator:FVP_Base_A57x4_A53x4 + to + System Generator:FVP_Base_Cortex-A57x4_A53x4 + + A similar change can be made to the other Cortex-A57-A53 Base FVP variants. + + +ARM Trusted Firmware - version 0.4 +================================== + +New features +------------ + +* Makefile improvements: + + * Improved dependency checking when building. + + * Removed `dump` target (build now always produces dump files). + + * Enabled platform ports to optionally make use of parts of the Trusted + Firmware (e.g. BL3-1 only), rather than being forced to use all parts. + Also made the `fip` target optional. + + * Specified the full path to source files and removed use of the `vpath` + keyword. + +* Provided translation table library code for potential re-use by platforms + other than the FVPs. + +* Moved architectural timer setup to platform-specific code. + +* Added standby state support to PSCI cpu_suspend implementation. + +* SRAM usage improvements: + + * Started using the `-ffunction-sections`, `-fdata-sections` and + `--gc-sections` compiler/linker options to remove unused code and data + from the images. Previously, all common functions were being built into + all binary images, whether or not they were actually used. + + * Placed all assembler functions in their own section to allow more unused + functions to be removed from images. + + * Updated BL1 and BL2 to use a single coherent stack each, rather than one + per CPU. + + * Changed variables that were unnecessarily declared and initialized as + non-const (i.e. in the .data section) so they are either uninitialized + (zero init) or const. + +* Moved the Test Secure-EL1 Payload (BL3-2) to execute in Trusted SRAM by + default. The option for it to run in Trusted DRAM remains. + +* Implemented a TrustZone Address Space Controller (TZC-400) driver. A + default configuration is provided for the Base FVPs. This means the model + parameter `-C bp.secure_memory=1` is now supported. + +* Started saving the PSCI cpu_suspend 'power_state' parameter prior to + suspending a CPU. This allows platforms that implement multiple power-down + states at the same affinity level to identify a specific state. + +* Refactored the entire codebase to reduce the amount of nesting in header + files and to make the use of system/user includes more consistent. Also + split platform.h to separate out the platform porting declarations from the + required platform porting definitions and the definitions/declarations + specific to the platform port. + +* Optimized the data cache clean/invalidate operations. + +* Improved the BL3-1 unhandled exception handling and reporting. Unhandled + exceptions now result in a dump of registers to the console. + +* Major rework to the handover interface between BL stages, in particular the + interface to BL3-1. The interface now conforms to a specification and is + more future proof. + +* Added support for optionally making the BL3-1 entrypoint a reset handler + (instead of BL1). This allows platforms with an alternative image loading + architecture to re-use BL3-1 with fewer modifications to generic code. + +* Reserved some DDR DRAM for secure use on FVP platforms to avoid future + compatibility problems with non-secure software. + +* Added support for secure interrupts targeting the Secure-EL1 Payload (SP) + (using GICv2 routing only). Demonstrated this working by adding an interrupt + target and supporting test code to the TSP. Also demonstrated non-secure + interrupt handling during TSP processing. + + +Issues resolved since last release +---------------------------------- + +* Now support use of the model parameter `-C bp.secure_memory=1` in the Base + FVPs (see **New features**). + +* Support for secure world interrupt handling now available (see **New + features**). + +* Made enough SRAM savings (see **New features**) to enable the Test Secure-EL1 + Payload (BL3-2) to execute in Trusted SRAM by default. + +* The tested filesystem used for this release (Linaro AArch64 OpenEmbedded + 14.04) now correctly reports progress in the console. + +* Improved the Makefile structure to make it easier to separate out parts of + the Trusted Firmware for re-use in platform ports. Also, improved target + dependency checking. + + +Known issues +------------ + +* GICv3 support is experimental. The Linux kernel patches to support this are + not widely available. There are known issues with GICv3 initialization in + the ARM Trusted Firmware. + +* Dynamic image loading is not available yet. The current image loader + implementation (used to load BL2 and all subsequent images) has some + limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead + to loading errors, even if the images should theoretically fit in memory. + +* The ARM Trusted Firmware still uses too much on-chip Trusted SRAM. A number + of RAM usage enhancements have been identified to rectify this situation. + +* CPU idle does not work on the advertised version of the Foundation FVP. + Some FVP fixes are required that are not available externally at the time + of writing. This can be worked around by disabling CPU idle in the Linux + kernel. + +* Various bugs in ARM Trusted Firmware, UEFI and the Linux kernel have been + observed when using Linaro toolchain versions later than 13.11. Although + most of these have been fixed, some remain at the time of writing. These + mainly seem to relate to a subtle change in the way the compiler converts + between 64-bit and 32-bit values (e.g. during casting operations), which + reveals previously hidden bugs in client code. + +* The firmware design documentation for the Test Secure-EL1 Payload (TSP) and + its dispatcher (TSPD) is incomplete. Similarly for the PSCI section. + + +ARM Trusted Firmware - version 0.3 +================================== + +New features +------------ + +* Support for Foundation FVP Version 2.0 added. + The documented UEFI configuration disables some devices that are unavailable + in the Foundation FVP, including MMC and CLCD. The resultant UEFI binary can + be used on the AEMv8 and Cortex-A57-A53 Base FVPs, as well as the Foundation + FVP. + + NOTE: The software will not work on Version 1.0 of the Foundation FVP. + +* Enabled third party contributions. Added a new contributing.md containing + instructions for how to contribute and updated copyright text in all files + to acknowledge contributors. + +* The PSCI CPU_SUSPEND API has been stabilised to the extent where it can be + used for entry into power down states with the following restrictions: + - Entry into standby states is not supported. + - The API is only supported on the AEMv8 and Cortex-A57-A53 Base FVPs. + +* The PSCI AFFINITY_INFO api has undergone limited testing on the Base FVPs to + allow experimental use. + +* Required C library and runtime header files are now included locally in ARM + Trusted Firmware instead of depending on the toolchain standard include + paths. The local implementation has been cleaned up and reduced in scope. + +* Added I/O abstraction framework, primarily to allow generic code to load + images in a platform-independent way. The existing image loading code has + been reworked to use the new framework. Semi-hosting and NOR flash I/O + drivers are provided. + +* Introduced Firmware Image Package (FIP) handling code and tools. A FIP + combines multiple firmware images with a Table of Contents (ToC) into a + single binary image. The new FIP driver is another type of I/O driver. The + Makefile builds a FIP by default and the FVP platform code expect to load a + FIP from NOR flash, although some support for image loading using semi- + hosting is retained. + + NOTE: Building a FIP by default is a non-backwards-compatible change. + + NOTE: Generic BL2 code now loads a BL3-3 (non-trusted firmware) image into + DRAM instead of expecting this to be pre-loaded at known location. This is + also a non-backwards-compatible change. + + NOTE: Some non-trusted firmware (e.g. UEFI) will need to be rebuilt so that + it knows the new location to execute from and no longer needs to copy + particular code modules to DRAM itself. + +* Reworked BL2 to BL3-1 handover interface. A new composite structure + (bl31_args) holds the superset of information that needs to be passed from + BL2 to BL3-1, including information on how handover execution control to + BL3-2 (if present) and BL3-3 (non-trusted firmware). + +* Added library support for CPU context management, allowing the saving and + restoring of + - Shared system registers between Secure-EL1 and EL1. + - VFP registers. + - Essential EL3 system registers. + +* Added a framework for implementing EL3 runtime services. Reworked the PSCI + implementation to be one such runtime service. + +* Reworked the exception handling logic, making use of both SP_EL0 and SP_EL3 + stack pointers for determining the type of exception, managing general + purpose and system register context on exception entry/exit, and handling + SMCs. SMCs are directed to the correct EL3 runtime service. + +* Added support for a Test Secure-EL1 Payload (TSP) and a corresponding + Dispatcher (TSPD), which is loaded as an EL3 runtime service. The TSPD + implements Secure Monitor functionality such as world switching and + EL1 context management, and is responsible for communication with the TSP. + NOTE: The TSPD does not yet contain support for secure world interrupts. + NOTE: The TSP/TSPD is not built by default. + + +Issues resolved since last release +---------------------------------- + +* Support has been added for switching context between secure and normal + worlds in EL3. + +* PSCI API calls `AFFINITY_INFO` & `PSCI_VERSION` have now been tested (to + a limited extent). + +* The ARM Trusted Firmware build artifacts are now placed in the `./build` + directory and sub-directories instead of being placed in the root of the + project. + +* The ARM Trusted Firmware is now free from build warnings. Build warnings + are now treated as errors. + +* The ARM Trusted Firmware now provides C library support locally within the + project to maintain compatibility between toolchains/systems. + +* The PSCI locking code has been reworked so it no longer takes locks in an + incorrect sequence. + +* The RAM-disk method of loading a Linux file-system has been confirmed to + work with the ARM Trusted Firmware and Linux kernel version (based on + version 3.13) used in this release, for both Foundation and Base FVPs. + + +Known issues +------------ + +The following is a list of issues which are expected to be fixed in the future +releases of the ARM Trusted Firmware. + +* The TrustZone Address Space Controller (TZC-400) is not being programmed + yet. Use of model parameter `-C bp.secure_memory=1` is not supported. + +* No support yet for secure world interrupt handling. + +* GICv3 support is experimental. The Linux kernel patches to support this are + not widely available. There are known issues with GICv3 initialization in + the ARM Trusted Firmware. + +* Dynamic image loading is not available yet. The current image loader + implementation (used to load BL2 and all subsequent images) has some + limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead + to loading errors, even if the images should theoretically fit in memory. + +* The ARM Trusted Firmware uses too much on-chip Trusted SRAM. Currently the + Test Secure-EL1 Payload (BL3-2) executes in Trusted DRAM since there is not + enough SRAM. A number of RAM usage enhancements have been identified to + rectify this situation. + +* CPU idle does not work on the advertised version of the Foundation FVP. + Some FVP fixes are required that are not available externally at the time + of writing. + +* Various bugs in ARM Trusted Firmware, UEFI and the Linux kernel have been + observed when using Linaro toolchain versions later than 13.11. Although + most of these have been fixed, some remain at the time of writing. These + mainly seem to relate to a subtle change in the way the compiler converts + between 64-bit and 32-bit values (e.g. during casting operations), which + reveals previously hidden bugs in client code. + +* The tested filesystem used for this release (Linaro AArch64 OpenEmbedded + 14.01) does not report progress correctly in the console. It only seems to + produce error output, not standard output. It otherwise appears to function + correctly. Other filesystem versions on the same software stack do not + exhibit the problem. + +* The Makefile structure doesn't make it easy to separate out parts of the + Trusted Firmware for re-use in platform ports, for example if only BL3-1 is + required in a platform port. Also, dependency checking in the Makefile is + flawed. + +* The firmware design documentation for the Test Secure-EL1 Payload (TSP) and + its dispatcher (TSPD) is incomplete. Similarly for the PSCI section. + + +ARM Trusted Firmware - version 0.2 +================================== + +New features +------------ + +* First source release. + +* Code for the PSCI suspend feature is supplied, although this is not enabled + by default since there are known issues (see below). + + +Issues resolved since last release +---------------------------------- + +* The "psci" nodes in the FDTs provided in this release now fully comply + with the recommendations made in the PSCI specification. + + +Known issues +------------ + +The following is a list of issues which are expected to be fixed in the future +releases of the ARM Trusted Firmware. + +* The TrustZone Address Space Controller (TZC-400) is not being programmed + yet. Use of model parameter `-C bp.secure_memory=1` is not supported. + +* No support yet for secure world interrupt handling or for switching context + between secure and normal worlds in EL3. + +* GICv3 support is experimental. The Linux kernel patches to support this are + not widely available. There are known issues with GICv3 initialization in + the ARM Trusted Firmware. + +* Dynamic image loading is not available yet. The current image loader + implementation (used to load BL2 and all subsequent images) has some + limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead + to loading errors, even if the images should theoretically fit in memory. + +* Although support for PSCI `CPU_SUSPEND` is present, it is not yet stable + and ready for use. + +* PSCI API calls `AFFINITY_INFO` & `PSCI_VERSION` are implemented but have not + been tested. + +* The ARM Trusted Firmware make files result in all build artifacts being + placed in the root of the project. These should be placed in appropriate + sub-directories. + +* The compilation of ARM Trusted Firmware is not free from compilation + warnings. Some of these warnings have not been investigated yet so they + could mask real bugs. + +* The ARM Trusted Firmware currently uses toolchain/system include files like + stdio.h. It should provide versions of these within the project to maintain + compatibility between toolchains/systems. + +* The PSCI code takes some locks in an incorrect sequence. This may cause + problems with suspend and hotplug in certain conditions. + +* The Linux kernel used in this release is based on version 3.12-rc4. Using + this kernel with the ARM Trusted Firmware fails to start the file-system as + a RAM-disk. It fails to execute user-space `init` from the RAM-disk. As an + alternative, the VirtioBlock mechanism can be used to provide a file-system + to the kernel. + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved._ + +[OP-TEE Dispatcher]: ./optee-dispatcher.md diff --git a/IPL/SDK/v3m/src/Dummy_BL33/docs/cpu-specific-build-macros.md b/IPL/SDK/v3m/src/Dummy_BL33/docs/cpu-specific-build-macros.md new file mode 100644 index 0000000..d9b7108 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/docs/cpu-specific-build-macros.md @@ -0,0 +1,79 @@ +ARM CPU Specific Build Macros +============================= + +Contents +-------- + +1. [Introduction](#1--introduction) +2. [CPU Errata Workarounds](#2--cpu-errata-workarounds) +3. [CPU Specific optimizations](#3--cpu-specific-optimizations) + + +1. Introduction +---------------- + +This document describes the various build options present in the CPU specific +operations framework to enable errata workarounds and to enable optimizations +for a specific CPU on a platform. + +2. CPU Errata Workarounds +-------------------------- + +ARM Trusted Firmware exports a series of build flags which control the +errata workarounds that are applied to each CPU by the reset handler. The +errata details can be found in the CPU specific errata documents published +by ARM. The errata workarounds are implemented for a particular revision +or a set of processor revisions. This is checked by reset handler at runtime. +Each errata workaround is identified by its `ID` as specified in the processor's +errata notice document. The format of the define used to enable/disable the +errata is `ERRATA__` where the `Processor name` +is either `A57` for the `Cortex_A57` CPU or `A53` for `Cortex_A53` CPU. + +All workarounds are disabled by default. The platform is reponsible for +enabling these workarounds according to its requirement by defining the +errata workaround build flags in the platform specific makefile. In case +these workarounds are enabled for the wrong CPU revision then the errata +workaround is not applied. In the DEBUG build, this is indicated by +printing a warning to the crash console. + +In the current implementation, a platform which has more than 1 variant +with different revisions of a processor has no runtime mechanism available +for it to specify which errata workarounds should be enabled or not. + +The value of the build flags are 0 by default, that is, disabled. Any other +value will enable it. + +For Cortex-A53, following errata build flags are defined : + +* `ERRATA_A53_826319`: This applies errata 826319 workaround to Cortex-A53 + CPU. This needs to be enabled only for revision <= r0p2 of the CPU. + +* `ERRATA_A53_836870`: This applies errata 836870 workaround to Cortex-A53 + CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From + r0p4 and onwards, this errata is enabled by default. + +For Cortex-A57, following errata build flags are defined : + +* `ERRATA_A57_806969`: This applies errata 806969 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision r0p0 of the CPU. + +* `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision r0p0 of the CPU. + +3. CPU Specific optimizations +------------------------------ + +This section describes some of the optimizations allowed by the CPU micro +architecture that can be enabled by the platform as desired. + +* `SKIP_A57_L1_FLUSH_PWR_DWN`: This flag enables an optimization in the + Cortex-A57 cluster power down sequence by not flushing the Level 1 data + cache. The L1 data cache and the L2 unified cache are inclusive. A flush + of the L2 by set/way flushes any dirty lines from the L1 as well. This + is a known safe deviation from the Cortex-A57 TRM defined power down + sequence. Each Cortex-A57 based platform must make its own decision on + whether to use the optimization. + +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2014, ARM Limited and Contributors. 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b/IPL/SDK/v3m/src/Dummy_BL33/docs/firmware-design.md @@ -0,0 +1,1771 @@ +ARM Trusted Firmware Design +=========================== + +Contents : + +1. [Introduction](#1--introduction) +2. [Cold boot](#2--cold-boot) +3. [EL3 runtime services framework](#3--el3-runtime-services-framework) +4. [Power State Coordination Interface](#4--power-state-coordination-interface) +5. [Secure-EL1 Payloads and Dispatchers](#5--secure-el1-payloads-and-dispatchers) +6. [Crash Reporting in BL3-1](#6--crash-reporting-in-bl3-1) +7. [Guidelines for Reset Handlers](#7--guidelines-for-reset-handlers) +8. [CPU specific operations framework](#8--cpu-specific-operations-framework) +9. [Memory layout of BL images](#9-memory-layout-of-bl-images) +10. [Firmware Image Package (FIP)](#10--firmware-image-package-fip) +11. [Use of coherent memory in Trusted Firmware](#11--use-of-coherent-memory-in-trusted-firmware) +12. [Code Structure](#12--code-structure) +13. [References](#13--references) + + +1. Introduction +---------------- + +The ARM Trusted Firmware implements a subset of the Trusted Board Boot +Requirements (TBBR) Platform Design Document (PDD) [1] for ARM reference +platforms. The TBB sequence starts when the platform is powered on and runs up +to the stage where it hands-off control to firmware running in the normal +world in DRAM. This is the cold boot path. + +The ARM Trusted Firmware also implements the Power State Coordination Interface +([PSCI]) PDD [2] as a runtime service. PSCI is the interface from normal world +software to firmware implementing power management use-cases (for example, +secondary CPU boot, hotplug and idle). Normal world software can access ARM +Trusted Firmware runtime services via the ARM SMC (Secure Monitor Call) +instruction. The SMC instruction must be used as mandated by the [SMC Calling +Convention PDD][SMCCC] [3]. + +The ARM Trusted Firmware implements a framework for configuring and managing +interrupts generated in either security state. The details of the interrupt +management framework and its design can be found in [ARM Trusted +Firmware Interrupt Management Design guide][INTRG] [4]. + +2. Cold boot +------------- + +The cold boot path starts when the platform is physically turned on. One of +the CPUs released from reset is chosen as the primary CPU, and the remaining +CPUs are considered secondary CPUs. The primary CPU is chosen through +platform-specific means. The cold boot path is mainly executed by the primary +CPU, other than essential CPU initialization executed by all CPUs. The +secondary CPUs are kept in a safe platform-specific state until the primary +CPU has performed enough initialization to boot them. + +The cold boot path in this implementation of the ARM Trusted Firmware is divided +into five steps (in order of execution): + +* Boot Loader stage 1 (BL1) _AP Trusted ROM_ +* Boot Loader stage 2 (BL2) _Trusted Boot Firmware_ +* Boot Loader stage 3-1 (BL3-1) _EL3 Runtime Firmware_ +* Boot Loader stage 3-2 (BL3-2) _Secure-EL1 Payload_ (optional) +* Boot Loader stage 3-3 (BL3-3) _Non-trusted Firmware_ + +ARM development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a +combination of the following types of memory regions. Each bootloader stage uses +one or more of these memory regions. + +* Regions accessible from both non-secure and secure states. For example, + non-trusted SRAM, ROM and DRAM. +* Regions accessible from only the secure state. For example, trusted SRAM and + ROM. The FVPs also implement the trusted DRAM which is statically + configured. Additionally, the Base FVPs and Juno development platform + configure the TrustZone Controller (TZC) to create a region in the DRAM + which is accessible only from the secure state. + + +The sections below provide the following details: + +* initialization and execution of the first three stages during cold boot +* specification of the BL3-1 entrypoint requirements for use by alternative + Trusted Boot Firmware in place of the provided BL1 and BL2 +* changes in BL3-1 behavior when using the `RESET_TO_BL31` option which + allows BL3-1 to run without BL1 and BL2 + + +### BL1 + +This stage begins execution from the platform's reset vector at EL3. The reset +address is platform dependent but it is usually located in a Trusted ROM area. +The BL1 data section is copied to trusted SRAM at runtime. + +On the ARM development platforms, BL1 code starts execution from the reset +vector defined by the constant `BL1_RO_BASE`. The BL1 data section is copied +to the top of trusted SRAM as defined by the constant `BL1_RW_BASE`. + +The functionality implemented by this stage is as follows. + +#### Determination of boot path + +Whenever a CPU is released from reset, BL1 needs to distinguish between a warm +boot and a cold boot. This is done using platform-specific mechanisms (see the +`platform_get_entrypoint()` function in the [Porting Guide]). In the case of a +warm boot, a CPU is expected to continue execution from a seperate +entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe +platform-specific state (see the `plat_secondary_cold_boot_setup()` function in +the [Porting Guide]) while the primary CPU executes the remaining cold boot path +as described in the following sections. + +#### Architectural initialization + +BL1 performs minimal architectural initialization as follows. + +* Exception vectors + + BL1 sets up simple exception vectors for both synchronous and asynchronous + exceptions. The default behavior upon receiving an exception is to populate + a status code in the general purpose register `X0` and call the + `plat_report_exception()` function (see the [Porting Guide]). The status + code is one of: + + 0x0 : Synchronous exception from Current EL with SP_EL0 + 0x1 : IRQ exception from Current EL with SP_EL0 + 0x2 : FIQ exception from Current EL with SP_EL0 + 0x3 : System Error exception from Current EL with SP_EL0 + 0x4 : Synchronous exception from Current EL with SP_ELx + 0x5 : IRQ exception from Current EL with SP_ELx + 0x6 : FIQ exception from Current EL with SP_ELx + 0x7 : System Error exception from Current EL with SP_ELx + 0x8 : Synchronous exception from Lower EL using aarch64 + 0x9 : IRQ exception from Lower EL using aarch64 + 0xa : FIQ exception from Lower EL using aarch64 + 0xb : System Error exception from Lower EL using aarch64 + 0xc : Synchronous exception from Lower EL using aarch32 + 0xd : IRQ exception from Lower EL using aarch32 + 0xe : FIQ exception from Lower EL using aarch32 + 0xf : System Error exception from Lower EL using aarch32 + + The `plat_report_exception()` implementation on the ARM FVP port programs + the Versatile Express System LED register in the following format to + indicate the occurence of an unexpected exception: + + SYS_LED[0] - Security state (Secure=0/Non-Secure=1) + SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) + SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value + of the status code + + A write to the LED register reflects in the System LEDs (S6LED0..7) in the + CLCD window of the FVP. + + BL1 does not expect to receive any exceptions other than the SMC exception. + For the latter, BL1 installs a simple stub. The stub expects to receive + only a single type of SMC (determined by its function ID in the general + purpose register `X0`). This SMC is raised by BL2 to make BL1 pass control + to BL3-1 (loaded by BL2) at EL3. Any other SMC leads to an assertion + failure. + +* CPU initialization + + BL1 calls the `reset_handler()` function which in turn calls the CPU + specific reset handler function (see the section: "CPU specific operations + framework"). + +* MMU setup + + BL1 sets up EL3 memory translation by creating page tables to cover the + first 4GB of physical address space. This covers all the memories and + peripherals needed by BL1. + +* Control register setup + - `SCTLR_EL3`. Instruction cache is enabled by setting the `SCTLR_EL3.I` + bit. Alignment and stack alignment checking is enabled by setting the + `SCTLR_EL3.A` and `SCTLR_EL3.SA` bits. Exception endianness is set to + little-endian by clearing the `SCTLR_EL3.EE` bit. + + - `SCR_EL3`. The register width of the next lower exception level is set to + AArch64 by setting the `SCR.RW` bit. + + - `CPTR_EL3`. Accesses to the `CPACR_EL1` register from EL1 or EL2, or the + `CPTR_EL2` register from EL2 are configured to not trap to EL3 by + clearing the `CPTR_EL3.TCPAC` bit. Access to the trace functionality is + configured not to trap to EL3 by clearing the `CPTR_EL3.TTA` bit. + Instructions that access the registers associated with Floating Point + and Advanced SIMD execution are configured to not trap to EL3 by + clearing the `CPTR_EL3.TFP` bit. + +#### Platform initialization + +BL1 enables issuing of snoop and DVM (Distributed Virtual Memory) requests to +the CCI slave interface corresponding to the cluster that includes the +primary CPU. BL1 also initializes a UART (PL011 console), which enables access +to the `printf` family of functions in BL1. + +#### BL2 image load and execution + +BL1 execution continues as follows: + +1. BL1 determines the amount of free trusted SRAM memory available by + calculating the extent of its own data section, which also resides in + trusted SRAM. BL1 loads a BL2 raw binary image from platform storage, at a + platform-specific base address. If the BL2 image file is not present or if + there is not enough free trusted SRAM the following error message is + printed: + + "Failed to load boot loader stage 2 (BL2) firmware." + + If the load is successful, BL1 updates the limits of the remaining free + trusted SRAM. It also populates information about the amount of trusted + SRAM used by the BL2 image. The exact load location of the image is + provided as a base address in the platform header. Further description of + the memory layout can be found later in this document. + +2. BL1 prints the following string from the primary CPU to indicate successful + execution of the BL1 stage: + + "Booting trusted firmware boot loader stage 1" + +3. BL1 passes control to the BL2 image at Secure EL1, starting from its load + address. + +4. BL1 also passes information about the amount of trusted SRAM used and + available for use. This information is populated at a platform-specific + memory address. + + +### BL2 + +BL1 loads and passes control to BL2 at Secure-EL1. BL2 is linked against and +loaded at a platform-specific base address (more information can be found later +in this document). The functionality implemented by BL2 is as follows. + +#### Architectural initialization + +BL2 performs minimal architectural initialization required for subsequent +stages of the ARM Trusted Firmware and normal world software. It sets up +Secure EL1 memory translation by creating page tables to address the first 4GB +of the physical address space in a similar way to BL1. EL1 and EL0 are given +access to Floating Point & Advanced SIMD registers by clearing the `CPACR.FPEN` +bits. + +#### Platform initialization + +BL2 copies the information regarding the trusted SRAM populated by BL1 using a +platform-specific mechanism. It calculates the limits of DRAM (main memory) +to determine whether there is enough space to load the BL3-3 image. A platform +defined base address is used to specify the load address for the BL3-1 image. +It also defines the extents of memory available for use by the BL3-2 image. +BL2 also initializes a UART (PL011 console), which enables access to the +`printf` family of functions in BL2. Platform security is initialized to allow +access to controlled components. The storage abstraction layer is initialized +which is used to load further bootloader images. + +#### BL3-0 (System Control Processor Firmware) image load + +Some systems have a separate System Control Processor (SCP) for power, clock, +reset and system control. BL2 loads the optional BL3-0 image from platform +storage into a platform-specific region of secure memory. The subsequent +handling of BL3-0 is platform specific. For example, on the Juno ARM development +platform port the image is transferred into SCP's internal memory using the Boot +Over MHU (BOM) protocol after being loaded in the trusted SRAM memory. The SCP +executes BL3-0 and signals to the Application Processor (AP) for BL2 execution +to continue. + +#### BL3-1 (EL3 Runtime Firmware) image load + +BL2 loads the BL3-1 image from platform storage into a platform-specific address +in trusted SRAM. If there is not enough memory to load the image or image is +missing it leads to an assertion failure. If the BL3-1 image loads successfully, +BL2 updates the amount of trusted SRAM used and available for use by BL3-1. +This information is populated at a platform-specific memory address. + +#### BL3-2 (Secure-EL1 Payload) image load + +BL2 loads the optional BL3-2 image from platform storage into a platform- +specific region of secure memory. The image executes in the secure world. BL2 +relies on BL3-1 to pass control to the BL3-2 image, if present. Hence, BL2 +populates a platform-specific area of memory with the entrypoint/load-address +of the BL3-2 image. The value of the Saved Processor Status Register (`SPSR`) +for entry into BL3-2 is not determined by BL2, it is initialized by the +Secure-EL1 Payload Dispatcher (see later) within BL3-1, which is responsible for +managing interaction with BL3-2. This information is passed to BL3-1. + +#### BL3-3 (Non-trusted Firmware) image load + +BL2 loads the BL3-3 image (e.g. UEFI or other test or boot software) from +platform storage into non-secure memory as defined by the platform. + +BL2 relies on BL3-1 to pass control to BL3-3 once secure state initialization is +complete. Hence, BL2 populates a platform-specific area of memory with the +entrypoint and Saved Program Status Register (`SPSR`) of the normal world +software image. The entrypoint is the load address of the BL3-3 image. The +`SPSR` is determined as specified in Section 5.13 of the [PSCI PDD] [PSCI]. This +information is passed to BL3-1. + +#### BL3-1 (EL3 Runtime Firmware) execution + +BL2 execution continues as follows: + +1. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the + BL3-1 entrypoint. The exception is handled by the SMC exception handler + installed by BL1. + +2. BL1 turns off the MMU and flushes the caches. It clears the + `SCTLR_EL3.M/I/C` bits, flushes the data cache to the point of coherency + and invalidates the TLBs. + +3. BL1 passes control to BL3-1 at the specified entrypoint at EL3. + + +### BL3-1 + +The image for this stage is loaded by BL2 and BL1 passes control to BL3-1 at +EL3. BL3-1 executes solely in trusted SRAM. BL3-1 is linked against and +loaded at a platform-specific base address (more information can be found later +in this document). The functionality implemented by BL3-1 is as follows. + +#### Architectural initialization + +Currently, BL3-1 performs a similar architectural initialization to BL1 as +far as system register settings are concerned. Since BL1 code resides in ROM, +architectural initialization in BL3-1 allows override of any previous +initialization done by BL1. BL3-1 creates page tables to address the first +4GB of physical address space and initializes the MMU accordingly. It initializes +a buffer of frequently used pointers, called per-CPU pointer cache, in memory for +faster access. Currently the per-CPU pointer cache contains only the pointer +to crash stack. It then replaces the exception vectors populated by BL1 with its +own. BL3-1 exception vectors implement more elaborate support for +handling SMCs since this is the only mechanism to access the runtime services +implemented by BL3-1 (PSCI for example). BL3-1 checks each SMC for validity as +specified by the [SMC calling convention PDD][SMCCC] before passing control to +the required SMC handler routine. BL3-1 programs the `CNTFRQ_EL0` register with +the clock frequency of the system counter, which is provided by the platform. + +#### Platform initialization + +BL3-1 performs detailed platform initialization, which enables normal world +software to function correctly. It also retrieves entrypoint information for +the BL3-3 image loaded by BL2 from the platform defined memory address populated +by BL2. It enables issuing of snoop and DVM (Distributed Virtual Memory) +requests to the CCI slave interface corresponding to the cluster that includes +the primary CPU. BL3-1 also initializes a UART (PL011 console), which enables +access to the `printf` family of functions in BL3-1. It enables the system +level implementation of the generic timer through the memory mapped interface. + +* GICv2 initialization: + + - Enable group0 interrupts in the GIC CPU interface. + - Configure group0 interrupts to be asserted as FIQs. + - Disable the legacy interrupt bypass mechanism. + - Configure the priority mask register to allow interrupts of all + priorities to be signaled to the CPU interface. + - Mark SGIs 8-15 and the other secure interrupts on the platform + as group0 (secure). + - Target all secure SPIs to CPU0. + - Enable these group0 interrupts in the GIC distributor. + - Configure all other interrupts as group1 (non-secure). + - Enable signaling of group0 interrupts in the GIC distributor. + +* GICv3 initialization: + + If a GICv3 implementation is available in the platform, BL3-1 initializes + the GICv3 in GICv2 emulation mode with settings as described for GICv2 + above. + +* Power management initialization: + + BL3-1 implements a state machine to track CPU and cluster state. The state + can be one of `OFF`, `ON_PENDING`, `SUSPEND` or `ON`. All secondary CPUs are + initially in the `OFF` state. The cluster that the primary CPU belongs to is + `ON`; any other cluster is `OFF`. BL3-1 initializes the data structures that + implement the state machine, including the locks that protect them. BL3-1 + accesses the state of a CPU or cluster immediately after reset and before + the data cache is enabled in the warm boot path. It is not currently + possible to use 'exclusive' based spinlocks, therefore BL3-1 uses locks + based on Lamport's Bakery algorithm instead. BL3-1 allocates these locks in + device memory by default. + +* Runtime services initialization: + + The runtime service framework and its initialization is described in the + "EL3 runtime services framework" section below. + + Details about the PSCI service are provided in the "Power State Coordination + Interface" section below. + +* BL3-2 (Secure-EL1 Payload) image initialization + + If a BL3-2 image is present then there must be a matching Secure-EL1 Payload + Dispatcher (SPD) service (see later for details). During initialization + that service must register a function to carry out initialization of BL3-2 + once the runtime services are fully initialized. BL3-1 invokes such a + registered function to initialize BL3-2 before running BL3-3. + + Details on BL3-2 initialization and the SPD's role are described in the + "Secure-EL1 Payloads and Dispatchers" section below. + +* BL3-3 (Non-trusted Firmware) execution + + BL3-1 initializes the EL2 or EL1 processor context for normal-world cold + boot, ensuring that no secure state information finds its way into the + non-secure execution state. BL3-1 uses the entrypoint information provided + by BL2 to jump to the Non-trusted firmware image (BL3-3) at the highest + available Exception Level (EL2 if available, otherwise EL1). + + +### Using alternative Trusted Boot Firmware in place of BL1 and BL2 + +Some platforms have existing implementations of Trusted Boot Firmware that +would like to use ARM Trusted Firmware BL3-1 for the EL3 Runtime Firmware. To +enable this firmware architecture it is important to provide a fully documented +and stable interface between the Trusted Boot Firmware and BL3-1. + +Future changes to the BL3-1 interface will be done in a backwards compatible +way, and this enables these firmware components to be independently enhanced/ +updated to develop and exploit new functionality. + +#### Required CPU state when calling `bl31_entrypoint()` during cold boot + +This function must only be called by the primary CPU. + +On entry to this function the calling primary CPU must be executing in AArch64 +EL3, little-endian data access, and all interrupt sources masked: + + PSTATE.EL = 3 + PSTATE.RW = 1 + PSTATE.DAIF = 0xf + SCTLR_EL3.EE = 0 + +X0 and X1 can be used to pass information from the Trusted Boot Firmware to the +platform code in BL3-1: + + X0 : Reserved for common Trusted Firmware information + X1 : Platform specific information + +BL3-1 zero-init sections (e.g. `.bss`) should not contain valid data on entry, +these will be zero filled prior to invoking platform setup code. + +##### Use of the X0 and X1 parameters + +The parameters are platform specific and passed from `bl31_entrypoint()` to +`bl31_early_platform_setup()`. The value of these parameters is never directly +used by the common BL3-1 code. + +The convention is that `X0` conveys information regarding the BL3-1, BL3-2 and +BL3-3 images from the Trusted Boot firmware and `X1` can be used for other +platform specific purpose. This convention allows platforms which use ARM +Trusted Firmware's BL1 and BL2 images to transfer additional platform specific +information from Secure Boot without conflicting with future evolution of the +Trusted Firmware using `X0` to pass a `bl31_params` structure. + +BL3-1 common and SPD initialization code depends on image and entrypoint +information about BL3-3 and BL3-2, which is provided via BL3-1 platform APIs. +This information is required until the start of execution of BL3-3. This +information can be provided in a platform defined manner, e.g. compiled into +the platform code in BL3-1, or provided in a platform defined memory location +by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the +Cold boot Initialization parameters. This data may need to be cleaned out of +the CPU caches if it is provided by an earlier boot stage and then accessed by +BL3-1 platform code before the caches are enabled. + +ARM Trusted Firmware's BL2 implementation passes a `bl31_params` structure in +`X0` and the ARM development platforms interpret this in the BL3-1 platform +code. + +##### MMU, Data caches & Coherency + +BL3-1 does not depend on the enabled state of the MMU, data caches or +interconnect coherency on entry to `bl31_entrypoint()`. If these are disabled +on entry, these should be enabled during `bl31_plat_arch_setup()`. + +##### Data structures used in the BL3-1 cold boot interface + +These structures are designed to support compatibility and independent +evolution of the structures and the firmware images. For example, a version of +BL3-1 that can interpret the BL3-x image information from different versions of +BL2, a platform that uses an extended entry_point_info structure to convey +additional register information to BL3-1, or a ELF image loader that can convey +more details about the firmware images. + +To support these scenarios the structures are versioned and sized, which enables +BL3-1 to detect which information is present and respond appropriately. The +`param_header` is defined to capture this information: + + typedef struct param_header { + uint8_t type; /* type of the structure */ + uint8_t version; /* version of this structure */ + uint16_t size; /* size of this structure in bytes */ + uint32_t attr; /* attributes: unused bits SBZ */ + } param_header_t; + +The structures using this format are `entry_point_info`, `image_info` and +`bl31_params`. The code that allocates and populates these structures must set +the header fields appropriately, and the `SET_PARAM_HEAD()` a macro is defined +to simplify this action. + +#### Required CPU state for BL3-1 Warm boot initialization + +When requesting a CPU power-on, or suspending a running CPU, ARM Trusted +Firmware provides the platform power management code with a Warm boot +initialization entry-point, to be invoked by the CPU immediately after the +reset handler. On entry to the Warm boot initialization function the calling +CPU must be in AArch64 EL3, little-endian data access and all interrupt sources +masked: + + PSTATE.EL = 3 + PSTATE.RW = 1 + PSTATE.DAIF = 0xf + SCTLR_EL3.EE = 0 + +The PSCI implementation will initialize the processor state and ensure that the +platform power management code is then invoked as required to initialize all +necessary system, cluster and CPU resources. + + +### Using BL3-1 as the CPU reset vector + +On some platforms the runtime firmware (BL3-x images) for the application +processors are loaded by trusted firmware running on a secure system processor +on the SoC, rather than by BL1 and BL2 running on the primary application +processor. For this type of SoC it is desirable for the application processor +to always reset to BL3-1 which eliminates the need for BL1 and BL2. + +ARM Trusted Firmware provides a build-time option `RESET_TO_BL31` that includes +some additional logic in the BL3-1 entrypoint to support this use case. + +In this configuration, the platform's Trusted Boot Firmware must ensure that +BL3-1 is loaded to its runtime address, which must match the CPU's RVBAR reset +vector address, before the application processor is powered on. Additionally, +platform software is responsible for loading the other BL3-x images required and +providing entry point information for them to BL3-1. Loading these images might +be done by the Trusted Boot Firmware or by platform code in BL3-1. + +The ARM FVP port supports the `RESET_TO_BL31` configuration, in which case the +`bl31.bin` image must be loaded to its run address in Trusted SRAM and all CPU +reset vectors be changed from the default `0x0` to this run address. See the +[User Guide] for details of running the FVP models in this way. + +This configuration requires some additions and changes in the BL3-1 +functionality: + +#### Determination of boot path + +In this configuration, BL3-1 uses the same reset framework and code as the one +described for BL1 above. On a warm boot a CPU is directed to the PSCI +implementation via a platform defined mechanism. On a cold boot, the platform +must place any secondary CPUs into a safe state while the primary CPU executes +a modified BL3-1 initialization, as described below. + +#### Platform initialization + +In this configuration, when the CPU resets to BL3-1 there are no parameters +that can be passed in registers by previous boot stages. Instead, the platform +code in BL3-1 needs to know, or be able to determine, the location of the BL3-2 +(if required) and BL3-3 images and provide this information in response to the +`bl31_plat_get_next_image_ep_info()` function. + +As the first image to execute in this configuration BL3-1 must also ensure that +any security initialisation, for example programming a TrustZone address space +controller, is carried out during early platform initialisation. + + +3. EL3 runtime services framework +---------------------------------- + +Software executing in the non-secure state and in the secure state at exception +levels lower than EL3 will request runtime services using the Secure Monitor +Call (SMC) instruction. These requests will follow the convention described in +the SMC Calling Convention PDD ([SMCCC]). The [SMCCC] assigns function +identifiers to each SMC request and describes how arguments are passed and +returned. + +The EL3 runtime services framework enables the development of services by +different providers that can be easily integrated into final product firmware. +The following sections describe the framework which facilitates the +registration, initialization and use of runtime services in EL3 Runtime +Firmware (BL3-1). + +The design of the runtime services depends heavily on the concepts and +definitions described in the [SMCCC], in particular SMC Function IDs, Owning +Entity Numbers (OEN), Fast and Standard calls, and the SMC32 and SMC64 calling +conventions. Please refer to that document for more detailed explanation of +these terms. + +The following runtime services are expected to be implemented first. They have +not all been instantiated in the current implementation. + +1. Standard service calls + + This service is for management of the entire system. The Power State + Coordination Interface ([PSCI]) is the first set of standard service calls + defined by ARM (see PSCI section later). + + NOTE: Currently this service is called PSCI since there are no other + defined standard service calls. + +2. Secure-EL1 Payload Dispatcher service + + If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then + it also requires a _Secure Monitor_ at EL3 to switch the EL1 processor + context between the normal world (EL1/EL2) and trusted world (Secure-EL1). + The Secure Monitor will make these world switches in response to SMCs. The + [SMCCC] provides for such SMCs with the Trusted OS Call and Trusted + Application Call OEN ranges. + + The interface between the EL3 Runtime Firmware and the Secure-EL1 Payload is + not defined by the [SMCCC] or any other standard. As a result, each + Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime + service - within ARM Trusted Firmware this service is referred to as the + Secure-EL1 Payload Dispatcher (SPD). + + ARM Trusted Firmware provides a Test Secure-EL1 Payload (TSP) and its + associated Dispatcher (TSPD). Details of SPD design and TSP/TSPD operation + are described in the "Secure-EL1 Payloads and Dispatchers" section below. + +3. CPU implementation service + + This service will provide an interface to CPU implementation specific + services for a given platform e.g. access to processor errata workarounds. + This service is currently unimplemented. + +Additional services for ARM Architecture, SiP and OEM calls can be implemented. +Each implemented service handles a range of SMC function identifiers as +described in the [SMCCC]. + + +### Registration + +A runtime service is registered using the `DECLARE_RT_SVC()` macro, specifying +the name of the service, the range of OENs covered, the type of service and +initialization and call handler functions. This macro instantiates a `const +struct rt_svc_desc` for the service with these details (see `runtime_svc.h`). +This structure is allocated in a special ELF section `rt_svc_descs`, enabling +the framework to find all service descriptors included into BL3-1. + +The specific service for a SMC Function is selected based on the OEN and call +type of the Function ID, and the framework uses that information in the service +descriptor to identify the handler for the SMC Call. + +The service descriptors do not include information to identify the precise set +of SMC function identifiers supported by this service implementation, the +security state from which such calls are valid nor the capability to support +64-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately +to these aspects of a SMC call is the responsibility of the service +implementation, the framework is focused on integration of services from +different providers and minimizing the time taken by the framework before the +service handler is invoked. + +Details of the parameters, requirements and behavior of the initialization and +call handling functions are provided in the following sections. + + +### Initialization + +`runtime_svc_init()` in `runtime_svc.c` initializes the runtime services +framework running on the primary CPU during cold boot as part of the BL3-1 +initialization. This happens prior to initializing a Trusted OS and running +Normal world boot firmware that might in turn use these services. +Initialization involves validating each of the declared runtime service +descriptors, calling the service initialization function and populating the +index used for runtime lookup of the service. + +The BL3-1 linker script collects all of the declared service descriptors into a +single array and defines symbols that allow the framework to locate and traverse +the array, and determine its size. + +The framework does basic validation of each descriptor to halt firmware +initialization if service declaration errors are detected. The framework does +not check descriptors for the following error conditions, and may behave in an +unpredictable manner under such scenarios: + +1. Overlapping OEN ranges +2. Multiple descriptors for the same range of OENs and `call_type` +3. Incorrect range of owning entity numbers for a given `call_type` + +Once validated, the service `init()` callback is invoked. This function carries +out any essential EL3 initialization before servicing requests. The `init()` +function is only invoked on the primary CPU during cold boot. If the service +uses per-CPU data this must either be initialized for all CPUs during this call, +or be done lazily when a CPU first issues an SMC call to that service. If +`init()` returns anything other than `0`, this is treated as an initialization +error and the service is ignored: this does not cause the firmware to halt. + +The OEN and call type fields present in the SMC Function ID cover a total of +128 distinct services, but in practice a single descriptor can cover a range of +OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a +service handler, the framework uses an array of 128 indices that map every +distinct OEN/call-type combination either to one of the declared services or to +indicate the service is not handled. This `rt_svc_descs_indices[]` array is +populated for all of the OENs covered by a service after the service `init()` +function has reported success. So a service that fails to initialize will never +have it's `handle()` function invoked. + +The following figure shows how the `rt_svc_descs_indices[]` index maps the SMC +Function ID call type and OEN onto a specific service handler in the +`rt_svc_descs[]` array. + +![Image 1](diagrams/rt-svc-descs-layout.png?raw=true) + + +### Handling an SMC + +When the EL3 runtime services framework receives a Secure Monitor Call, the SMC +Function ID is passed in W0 from the lower exception level (as per the +[SMCCC]). If the calling register width is AArch32, it is invalid to invoke an +SMC Function which indicates the SMC64 calling convention: such calls are +ignored and return the Unknown SMC Function Identifier result code `0xFFFFFFFF` +in R0/X0. + +Bit[31] (fast/standard call) and bits[29:24] (owning entity number) of the SMC +Function ID are combined to index into the `rt_svc_descs_indices[]` array. The +resulting value might indicate a service that has no handler, in this case the +framework will also report an Unknown SMC Function ID. Otherwise, the value is +used as a further index into the `rt_svc_descs[]` array to locate the required +service and handler. + +The service's `handle()` callback is provided with five of the SMC parameters +directly, the others are saved into memory for retrieval (if needed) by the +handler. The handler is also provided with an opaque `handle` for use with the +supporting library for parameter retrieval, setting return values and context +manipulation; and with `flags` indicating the security state of the caller. The +framework finally sets up the execution stack for the handler, and invokes the +services `handle()` function. + +On return from the handler the result registers are populated in X0-X3 before +restoring the stack and CPU state and returning from the original SMC. + + +4. Power State Coordination Interface +-------------------------------------- + +TODO: Provide design walkthrough of PSCI implementation. + +The PSCI v1.0 specification categorizes APIs as optional and mandatory. All the +mandatory APIs in PSCI v1.0 and all the APIs in PSCI v0.2 draft specification +[Power State Coordination Interface PDD] [PSCI] are implemented. The table lists +the PSCI v1.0 APIs and their support in generic code. + +An API implementation might have a dependency on platform code e.g. CPU_SUSPEND +requires the platform to export a part of the implementation. Hence the level +of support of the mandatory APIs depends upon the support exported by the +platform port as well. The Juno and FVP (all variants) platforms export all the +required support. + +| PSCI v1.0 API |Supported| Comments | +|:----------------------|:--------|:------------------------------------------| +|`PSCI_VERSION` | Yes | The version returned is 1.0 | +|`CPU_SUSPEND` | Yes* | The original `power_state` format is used | +|`CPU_OFF` | Yes* | | +|`CPU_ON` | Yes* | | +|`AFFINITY_INFO` | Yes | | +|`MIGRATE` | Yes** | | +|`MIGRATE_INFO_TYPE` | Yes** | | +|`MIGRATE_INFO_CPU` | Yes** | | +|`SYSTEM_OFF` | Yes* | | +|`SYSTEM_RESET` | Yes* | | +|`PSCI_FEATURES` | Yes | | +|`CPU_FREEZE` | No | | +|`CPU_DEFAULT_SUSPEND` | No | | +|`CPU_HW_STATE` | No | | +|`SYSTEM_SUSPEND` | Yes* | | +|`PSCI_SET_SUSPEND_MODE`| No | | +|`PSCI_STAT_RESIDENCY` | No | | +|`PSCI_STAT_COUNT` | No | | + +*Note : These PSCI APIs require platform power management hooks to be +registered with the generic PSCI code to be supported. + +**Note : These PSCI APIs require appropriate Secure Payload Dispatcher +hooks to be registered with the generic PSCI code to be supported. + + +5. Secure-EL1 Payloads and Dispatchers +--------------------------------------- + +On a production system that includes a Trusted OS running in Secure-EL1/EL0, +the Trusted OS is coupled with a companion runtime service in the BL3-1 +firmware. This service is responsible for the initialisation of the Trusted +OS and all communications with it. The Trusted OS is the BL3-2 stage of the +boot flow in ARM Trusted Firmware. The firmware will attempt to locate, load +and execute a BL3-2 image. + +ARM Trusted Firmware uses a more general term for the BL3-2 software that runs +at Secure-EL1 - the _Secure-EL1 Payload_ - as it is not always a Trusted OS. + +The ARM Trusted Firmware provides a Test Secure-EL1 Payload (TSP) and a Test +Secure-EL1 Payload Dispatcher (TSPD) service as an example of how a Trusted OS +is supported on a production system using the Runtime Services Framework. On +such a system, the Test BL3-2 image and service are replaced by the Trusted OS +and its dispatcher service. The ARM Trusted Firmware build system expects that +the dispatcher will define the build flag `NEED_BL32` to enable it to include +the BL3-2 in the build either as a binary or to compile from source depending +on whether the `BL32` build option is specified or not. + +The TSP runs in Secure-EL1. It is designed to demonstrate synchronous +communication with the normal-world software running in EL1/EL2. Communication +is initiated by the normal-world software + +* either directly through a Fast SMC (as defined in the [SMCCC]) + +* or indirectly through a [PSCI] SMC. The [PSCI] implementation in turn + informs the TSPD about the requested power management operation. This allows + the TSP to prepare for or respond to the power state change + +The TSPD service is responsible for. + +* Initializing the TSP + +* Routing requests and responses between the secure and the non-secure + states during the two types of communications just described + +### Initializing a BL3-2 Image + +The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing +the BL3-2 image. It needs access to the information passed by BL2 to BL3-1 to do +so. This is provided by: + + entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); + +which returns a reference to the `entry_point_info` structure corresponding to +the image which will be run in the specified security state. The SPD uses this +API to get entry point information for the SECURE image, BL3-2. + +In the absence of a BL3-2 image, BL3-1 passes control to the normal world +bootloader image (BL3-3). When the BL3-2 image is present, it is typical +that the SPD wants control to be passed to BL3-2 first and then later to BL3-3. + +To do this the SPD has to register a BL3-2 initialization function during +initialization of the SPD service. The BL3-2 initialization function has this +prototype: + + int32_t init(); + +and is registered using the `bl31_register_bl32_init()` function. + +Trusted Firmware supports two approaches for the SPD to pass control to BL3-2 +before returning through EL3 and running the non-trusted firmware (BL3-3): + +1. In the BL3-2 setup function, use `bl31_set_next_image_type()` to + request that the exit from `bl31_main()` is to the BL3-2 entrypoint in + Secure-EL1. BL3-1 will exit to BL3-2 using the asynchronous method by + calling bl31_prepare_next_image_entry() and el3_exit(). + + When the BL3-2 has completed initialization at Secure-EL1, it returns to + BL3-1 by issuing an SMC, using a Function ID allocated to the SPD. On + receipt of this SMC, the SPD service handler should switch the CPU context + from trusted to normal world and use the `bl31_set_next_image_type()` and + `bl31_prepare_next_image_entry()` functions to set up the initial return to + the normal world firmware BL3-3. On return from the handler the framework + will exit to EL2 and run BL3-3. + +2. The BL3-2 setup function registers a initialization function using + `bl31_register_bl32_init()` which provides a SPD-defined mechanism to + invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL3-2 + entrypoint. + NOTE: The Test SPD service included with the Trusted Firmware provides one + implementation of such a mechanism. + + On completion BL3-2 returns control to BL3-1 via a SMC, and on receipt the + SPD service handler invokes the synchronous call return mechanism to return + to the BL3-2 initialization function. On return from this function, + `bl31_main()` will set up the return to the normal world firmware BL3-3 and + continue the boot process in the normal world. + + +6. Crash Reporting in BL3-1 +---------------------------- + +BL3-1 implements a scheme for reporting the processor state when an unhandled +exception is encountered. The reporting mechanism attempts to preserve all the +register contents and report it via a dedicated UART (PL011 console). BL3-1 +reports the general purpose, EL3, Secure EL1 and some EL2 state registers. + +A dedicated per-CPU crash stack is maintained by BL3-1 and this is retrieved via +the per-CPU pointer cache. The implementation attempts to minimise the memory +required for this feature. The file `crash_reporting.S` contains the +implementation for crash reporting. + +The sample crash output is shown below. + + x0 :0x000000004F00007C + x1 :0x0000000007FFFFFF + x2 :0x0000000004014D50 + x3 :0x0000000000000000 + x4 :0x0000000088007998 + x5 :0x00000000001343AC + x6 :0x0000000000000016 + x7 :0x00000000000B8A38 + x8 :0x00000000001343AC + x9 :0x00000000000101A8 + x10 :0x0000000000000002 + x11 :0x000000000000011C + x12 :0x00000000FEFDC644 + x13 :0x00000000FED93FFC + x14 :0x0000000000247950 + x15 :0x00000000000007A2 + x16 :0x00000000000007A4 + x17 :0x0000000000247950 + x18 :0x0000000000000000 + x19 :0x00000000FFFFFFFF + x20 :0x0000000004014D50 + x21 :0x000000000400A38C + x22 :0x0000000000247950 + x23 :0x0000000000000010 + x24 :0x0000000000000024 + x25 :0x00000000FEFDC868 + x26 :0x00000000FEFDC86A + x27 :0x00000000019EDEDC + x28 :0x000000000A7CFDAA + x29 :0x0000000004010780 + x30 :0x000000000400F004 + scr_el3 :0x0000000000000D3D + sctlr_el3 :0x0000000000C8181F + cptr_el3 :0x0000000000000000 + tcr_el3 :0x0000000080803520 + daif :0x00000000000003C0 + mair_el3 :0x00000000000004FF + spsr_el3 :0x00000000800003CC + elr_el3 :0x000000000400C0CC + ttbr0_el3 :0x00000000040172A0 + esr_el3 :0x0000000096000210 + sp_el3 :0x0000000004014D50 + far_el3 :0x000000004F00007C + spsr_el1 :0x0000000000000000 + elr_el1 :0x0000000000000000 + spsr_abt :0x0000000000000000 + spsr_und :0x0000000000000000 + spsr_irq :0x0000000000000000 + spsr_fiq :0x0000000000000000 + sctlr_el1 :0x0000000030C81807 + actlr_el1 :0x0000000000000000 + cpacr_el1 :0x0000000000300000 + csselr_el1 :0x0000000000000002 + sp_el1 :0x0000000004028800 + esr_el1 :0x0000000000000000 + ttbr0_el1 :0x000000000402C200 + ttbr1_el1 :0x0000000000000000 + mair_el1 :0x00000000000004FF + amair_el1 :0x0000000000000000 + tcr_el1 :0x0000000000003520 + tpidr_el1 :0x0000000000000000 + tpidr_el0 :0x0000000000000000 + tpidrro_el0 :0x0000000000000000 + dacr32_el2 :0x0000000000000000 + ifsr32_el2 :0x0000000000000000 + par_el1 :0x0000000000000000 + far_el1 :0x0000000000000000 + afsr0_el1 :0x0000000000000000 + afsr1_el1 :0x0000000000000000 + contextidr_el1 :0x0000000000000000 + vbar_el1 :0x0000000004027000 + cntp_ctl_el0 :0x0000000000000000 + cntp_cval_el0 :0x0000000000000000 + cntv_ctl_el0 :0x0000000000000000 + cntv_cval_el0 :0x0000000000000000 + cntkctl_el1 :0x0000000000000000 + fpexc32_el2 :0x0000000004000700 + sp_el0 :0x0000000004010780 + +7. Guidelines for Reset Handlers +--------------------------------- + +Trusted Firmware implements a framework that allows CPU and platform ports to +perform actions very early after a CPU is released from reset in both the cold +and warm boot paths. This is done by calling the `reset_handler()` function in +both the BL1 and BL3-1 images. It in turn calls the platform and CPU specific +reset handling functions. + +Details for implementing a CPU specific reset handler can be found in +Section 8. Details for implementing a platform specific reset handler can be +found in the [Porting Guide](see the `plat_reset_handler()` function). + +When adding functionality to a reset handler, keep in mind that if a different +reset handling behavior is required between the first and the subsequent +invocations of the reset handling code, this should be detected at runtime. +In other words, the reset handler should be able to detect whether an action has +already been performed and act as appropriate. Possible courses of actions are, +e.g. skip the action the second time, or undo/redo it. + +8. CPU specific operations framework +----------------------------- + +Certain aspects of the ARMv8 architecture are implementation defined, +that is, certain behaviours are not architecturally defined, but must be defined +and documented by individual processor implementations. The ARM Trusted +Firmware implements a framework which categorises the common implementation +defined behaviours and allows a processor to export its implementation of that +behaviour. The categories are: + +1. Processor specific reset sequence. + +2. Processor specific power down sequences. + +3. Processor specific register dumping as a part of crash reporting. + +Each of the above categories fulfils a different requirement. + +1. allows any processor specific initialization before the caches and MMU + are turned on, like implementation of errata workarounds, entry into + the intra-cluster coherency domain etc. + +2. allows each processor to implement the power down sequence mandated in + its Technical Reference Manual (TRM). + +3. allows a processor to provide additional information to the developer + in the event of a crash, for example Cortex-A53 has registers which + can expose the data cache contents. + +Please note that only 2. is mandated by the TRM. + +The CPU specific operations framework scales to accommodate a large number of +different CPUs during power down and reset handling. The platform can specify +any CPU optimization it wants to enable for each CPU. It can also specify +the CPU errata workarounds to be applied for each CPU type during reset +handling by defining CPU errata compile time macros. Details on these macros +can be found in the [cpu-specific-build-macros.md][CPUBM] file. + +The CPU specific operations framework depends on the `cpu_ops` structure which +needs to be exported for each type of CPU in the platform. It is defined in +`include/lib/cpus/aarch64/cpu_macros.S` and has the following fields : `midr`, +`reset_func()`, `core_pwr_dwn()`, `cluster_pwr_dwn()` and `cpu_reg_dump()`. + +The CPU specific files in `lib/cpus` export a `cpu_ops` data structure with +suitable handlers for that CPU. For example, `lib/cpus/cortex_a53.S` exports +the `cpu_ops` for Cortex-A53 CPU. According to the platform configuration, +these CPU specific files must must be included in the build by the platform +makefile. The generic CPU specific operations framework code exists in +`lib/cpus/aarch64/cpu_helpers.S`. + +### CPU specific Reset Handling + +After a reset, the state of the CPU when it calls generic reset handler is: +MMU turned off, both instruction and data caches turned off and not part +of any coherency domain. + +The BL entrypoint code first invokes the `plat_reset_handler()` to allow +the platform to perform any system initialization required and any system +errata workarounds that needs to be applied. The `get_cpu_ops_ptr()` reads +the current CPU midr, finds the matching `cpu_ops` entry in the `cpu_ops` +array and returns it. Note that only the part number and implementer fields +in midr are used to find the matching `cpu_ops` entry. The `reset_func()` in +the returned `cpu_ops` is then invoked which executes the required reset +handling for that CPU and also any errata workarounds enabled by the platform. +This function must preserve the values of general purpose registers x20 to x29. + +Refer to Section "Guidelines for Reset Handlers" for general guidelines +regarding placement of code in a reset handler. + +### CPU specific power down sequence + +During the BL3-1 initialization sequence, the pointer to the matching `cpu_ops` +entry is stored in per-CPU data by `init_cpu_ops()` so that it can be quickly +retrieved during power down sequences. + +The PSCI service, upon receiving a power down request, determines the highest +affinity level at which to execute power down sequence for a particular CPU and +invokes the corresponding 'prepare' power down handler in the CPU specific +operations framework. For example, when a CPU executes a power down for affinity +level 0, the `prepare_core_pwr_dwn()` retrieves the `cpu_ops` pointer from the +per-CPU data and the corresponding `core_pwr_dwn()` is invoked. Similarly when +a CPU executes power down at affinity level 1, the `prepare_cluster_pwr_dwn()` +retrieves the `cpu_ops` pointer and the corresponding `cluster_pwr_dwn()` is +invoked. + +At runtime the platform hooks for power down are invoked by the PSCI service to +perform platform specific operations during a power down sequence, for example +turning off CCI coherency during a cluster power down. + +### CPU specific register reporting during crash + +If the crash reporting is enabled in BL3-1, when a crash occurs, the crash +reporting framework calls `do_cpu_reg_dump` which retrieves the matching +`cpu_ops` using `get_cpu_ops_ptr()` function. The `cpu_reg_dump()` in +`cpu_ops` is invoked, which then returns the CPU specific register values to +be reported and a pointer to the ASCII list of register names in a format +expected by the crash reporting framework. + + +9. Memory layout of BL images +----------------------------- + +Each bootloader image can be divided in 2 parts: + + * the static contents of the image. These are data actually stored in the + binary on the disk. In the ELF terminology, they are called `PROGBITS` + sections; + + * the run-time contents of the image. These are data that don't occupy any + space in the binary on the disk. The ELF binary just contains some + metadata indicating where these data will be stored at run-time and the + corresponding sections need to be allocated and initialized at run-time. + In the ELF terminology, they are called `NOBITS` sections. + +All PROGBITS sections are grouped together at the beginning of the image, +followed by all NOBITS sections. This is true for all Trusted Firmware images +and it is governed by the linker scripts. This ensures that the raw binary +images are as small as possible. If a NOBITS section would sneak in between +PROGBITS sections then the resulting binary file would contain a bunch of zero +bytes at the location of this NOBITS section, making the image unnecessarily +bigger. Smaller images allow faster loading from the FIP to the main memory. + +### Linker scripts and symbols + +Each bootloader stage image layout is described by its own linker script. The +linker scripts export some symbols into the program symbol table. Their values +correspond to particular addresses. The trusted firmware code can refer to these +symbols to figure out the image memory layout. + +Linker symbols follow the following naming convention in the trusted firmware. + +* `__

_START__` + + Start address of a given section named `
`. + +* `__
_END__` + + End address of a given section named `
`. If there is an alignment + constraint on the section's end address then `__
_END__` corresponds + to the end address of the section's actual contents, rounded up to the right + boundary. Refer to the value of `__
_UNALIGNED_END__` to know the + actual end address of the section's contents. + +* `__
_UNALIGNED_END__` + + End address of a given section named `
` without any padding or + rounding up due to some alignment constraint. + +* `__
_SIZE__` + + Size (in bytes) of a given section named `
`. If there is an + alignment constraint on the section's end address then `__
_SIZE__` + corresponds to the size of the section's actual contents, rounded up to the + right boundary. In other words, `__
_SIZE__ = __
_END__ - + _
_START__`. Refer to the value of `__
_UNALIGNED_SIZE__` + to know the actual size of the section's contents. + +* `__
_UNALIGNED_SIZE__` + + Size (in bytes) of a given section named `
` without any padding or + rounding up due to some alignment constraint. In other words, + `__
_UNALIGNED_SIZE__ = __
_UNALIGNED_END__ - + __
_START__`. + +Some of the linker symbols are mandatory as the trusted firmware code relies on +them to be defined. They are listed in the following subsections. Some of them +must be provided for each bootloader stage and some are specific to a given +bootloader stage. + +The linker scripts define some extra, optional symbols. They are not actually +used by any code but they help in understanding the bootloader images' memory +layout as they are easy to spot in the link map files. + +#### Common linker symbols + +Early setup code needs to know the extents of the BSS section to zero-initialise +it before executing any C code. The following linker symbols are defined for +this purpose: + +* `__BSS_START__` This address must be aligned on a 16-byte boundary. +* `__BSS_SIZE__` + +Similarly, the coherent memory section (if enabled) must be zero-initialised. +Also, the MMU setup code needs to know the extents of this section to set the +right memory attributes for it. The following linker symbols are defined for +this purpose: + +* `__COHERENT_RAM_START__` This address must be aligned on a page-size boundary. +* `__COHERENT_RAM_END__` This address must be aligned on a page-size boundary. +* `__COHERENT_RAM_UNALIGNED_SIZE__` + +#### BL1's linker symbols + +BL1's early setup code needs to know the extents of the .data section to +relocate it from ROM to RAM before executing any C code. The following linker +symbols are defined for this purpose: + +* `__DATA_ROM_START__` This address must be aligned on a 16-byte boundary. +* `__DATA_RAM_START__` This address must be aligned on a 16-byte boundary. +* `__DATA_SIZE__` + +BL1's platform setup code needs to know the extents of its read-write data +region to figure out its memory layout. The following linker symbols are defined +for this purpose: + +* `__BL1_RAM_START__` This is the start address of BL1 RW data. +* `__BL1_RAM_END__` This is the end address of BL1 RW data. + +#### BL2's, BL3-1's and TSP's linker symbols + +BL2, BL3-1 and TSP need to know the extents of their read-only section to set +the right memory attributes for this memory region in their MMU setup code. The +following linker symbols are defined for this purpose: + +* `__RO_START__` +* `__RO_END__` + +### How to choose the right base addresses for each bootloader stage image + +There is currently no support for dynamic image loading in the Trusted Firmware. +This means that all bootloader images need to be linked against their ultimate +runtime locations and the base addresses of each image must be chosen carefully +such that images don't overlap each other in an undesired way. As the code +grows, the base addresses might need adjustments to cope with the new memory +layout. + +The memory layout is completely specific to the platform and so there is no +general recipe for choosing the right base addresses for each bootloader image. +However, there are tools to aid in understanding the memory layout. These are +the link map files: `build///bl/bl.map`, with `` +being the stage bootloader. They provide a detailed view of the memory usage of +each image. Among other useful information, they provide the end address of +each image. + +* `bl1.map` link map file provides `__BL1_RAM_END__` address. +* `bl2.map` link map file provides `__BL2_END__` address. +* `bl31.map` link map file provides `__BL31_END__` address. +* `bl32.map` link map file provides `__BL32_END__` address. + +For each bootloader image, the platform code must provide its start address +as well as a limit address that it must not overstep. The latter is used in the +linker scripts to check that the image doesn't grow past that address. If that +happens, the linker will issue a message similar to the following: + + aarch64-none-elf-ld: BLx has exceeded its limit. + +Additionally, if the platform memory layout implies some image overlaying like +on FVP, BL3-1 and TSP need to know the limit address that their PROGBITS +sections must not overstep. The platform code must provide those. + + +#### Memory layout on ARM development platforms + +The following list describes the memory layout on the ARM development platforms: + +* A 4KB page of shared memory is used for communication between Trusted + Firmware and the platform's power controller. This is located at the base of + Trusted SRAM. The amount of Trusted SRAM available to load the bootloader + images is reduced by the size of the shared memory. + + The shared memory is used to store the entrypoint mailboxes for each CPU. + On Juno, this is also used for the MHU payload when passing messages to and + from the SCP. + +* On FVP, BL1 is originally sitting in the Trusted ROM at address `0x0`. On + Juno, BL1 resides in flash memory at address `0x0BEC0000`. BL1 read-write + data are relocated to the top of Trusted SRAM at runtime. + +* BL3-1 is loaded at the top of the Trusted SRAM, such that its NOBITS + sections will overwrite BL1 R/W data. This implies that BL1 global variables + remain valid only until execution reaches the BL3-1 entry point during + a cold boot. + +* BL2 is loaded below BL3-1. + +* On Juno, BL3-0 is loaded temporarily into the BL3-1 memory region and + transfered to the SCP before being overwritten by BL3-1. + +* BL3-2 can be loaded in one of the following locations: + + * Trusted SRAM + * Trusted DRAM (FVP only) + * Secure region of DRAM (top 16MB of DRAM configured by the TrustZone + controller) + +When BL3-2 is loaded into Trusted SRAM, its NOBITS sections are allowed to +overlay BL2. This memory layout is designed to give the BL3-2 image as much +memory as possible when it is loaded into Trusted SRAM. + +The location of the BL3-2 image will result in different memory maps. This is +illustrated for both FVP and Juno in the following diagrams, using the TSP as +an example. + +Note: Loading the BL3-2 image in TZC secured DRAM doesn't change the memory +layout of the other images in Trusted SRAM. + +**FVP with TSP in Trusted SRAM (default option):** + + Trusted SRAM + 0x04040000 +----------+ loaded by BL2 ------------------ + | BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS | + |----------| <<<<<<<<<<<<< |----------------| + | | <<<<<<<<<<<<< | BL3-1 PROGBITS | + |----------| ------------------ + | BL2 | <<<<<<<<<<<<< | BL3-2 NOBITS | + |----------| <<<<<<<<<<<<< |----------------| + | | <<<<<<<<<<<<< | BL3-2 PROGBITS | + 0x04001000 +----------+ ------------------ + | Shared | + 0x04000000 +----------+ + + Trusted ROM + 0x04000000 +----------+ + | BL1 (ro) | + 0x00000000 +----------+ + + +**FVP with TSP in Trusted DRAM:** + + Trusted DRAM + 0x08000000 +----------+ + | BL3-2 | + 0x06000000 +----------+ + + Trusted SRAM + 0x04040000 +----------+ loaded by BL2 ------------------ + | BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS | + |----------| <<<<<<<<<<<<< |----------------| + | | <<<<<<<<<<<<< | BL3-1 PROGBITS | + |----------| ------------------ + | BL2 | + |----------| + | | + 0x04001000 +----------+ + | Shared | + 0x04000000 +----------+ + + Trusted ROM + 0x04000000 +----------+ + | BL1 (ro) | + 0x00000000 +----------+ + +**FVP with TSP in TZC-Secured DRAM:** + + DRAM + 0xffffffff +----------+ + | BL3-2 | (secure) + 0xff000000 +----------+ + | | + : : (non-secure) + | | + 0x80000000 +----------+ + + Trusted SRAM + 0x04040000 +----------+ loaded by BL2 ------------------ + | BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS | + |----------| <<<<<<<<<<<<< |----------------| + | | <<<<<<<<<<<<< | BL3-1 PROGBITS | + |----------| ------------------ + | BL2 | + |----------| + | | + 0x04001000 +----------+ + | Shared | + 0x04000000 +----------+ + + Trusted ROM + 0x04000000 +----------+ + | BL1 (ro) | + 0x00000000 +----------+ + + +**Juno with BL3-2 in Trusted SRAM (default option):** + + Flash0 + 0x0C000000 +----------+ + : : + 0x0BED0000 |----------| + | BL1 (ro) | + 0x0BEC0000 |----------| + : : + 0x08000000 +----------+ BL3-1 is loaded + after BL3-0 has + Trusted SRAM been sent to SCP + 0x04040000 +----------+ loaded by BL2 ------------------ + | BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS | + |----------| <<<<<<<<<<<<< |----------------| + | BL3-0 | <<<<<<<<<<<<< | BL3-1 PROGBITS | + |----------| ------------------ + | BL2 | <<<<<<<<<<<<< | BL3-2 NOBITS | + |----------| <<<<<<<<<<<<< |----------------| + | | <<<<<<<<<<<<< | BL3-2 PROGBITS | + 0x04001000 +----------+ ------------------ + | MHU | + 0x04000000 +----------+ + + +**Juno with BL3-2 in TZC-secured DRAM:** + + DRAM + 0xFFE00000 +----------+ + | BL3-2 | (secure) + 0xFF000000 |----------| + | | + : : (non-secure) + | | + 0x80000000 +----------+ + + Flash0 + 0x0C000000 +----------+ + : : + 0x0BED0000 |----------| + | BL1 (ro) | + 0x0BEC0000 |----------| + : : + 0x08000000 +----------+ BL3-1 is loaded + after BL3-0 has + Trusted SRAM been sent to SCP + 0x04040000 +----------+ loaded by BL2 ------------------ + | BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS | + |----------| <<<<<<<<<<<<< |----------------| + | BL3-0 | <<<<<<<<<<<<< | BL3-1 PROGBITS | + |----------| ------------------ + | BL2 | + |----------| + | | + 0x04001000 +----------+ + | MHU | + 0x04000000 +----------+ + + +10. Firmware Image Package (FIP) +--------------------------------- + +Using a Firmware Image Package (FIP) allows for packing bootloader images (and +potentially other payloads) into a single archive that can be loaded by the ARM +Trusted Firmware from non-volatile platform storage. A driver to load images +from a FIP has been added to the storage layer and allows a package to be read +from supported platform storage. A tool to create Firmware Image Packages is +also provided and described below. + +### Firmware Image Package layout + +The FIP layout consists of a table of contents (ToC) followed by payload data. +The ToC itself has a header followed by one or more table entries. The ToC is +terminated by an end marker entry. All ToC entries describe some payload data +that has been appended to the end of the binary package. With the information +provided in the ToC entry the corresponding payload data can be retrieved. + + ------------------ + | ToC Header | + |----------------| + | ToC Entry 0 | + |----------------| + | ToC Entry 1 | + |----------------| + | ToC End Marker | + |----------------| + | | + | Data 0 | + | | + |----------------| + | | + | Data 1 | + | | + ------------------ + +The ToC header and entry formats are described in the header file +`include/firmware_image_package.h`. This file is used by both the tool and the +ARM Trusted firmware. + +The ToC header has the following fields: + `name`: The name of the ToC. This is currently used to validate the header. + `serial_number`: A non-zero number provided by the creation tool + `flags`: Flags associated with this data. None are yet defined. + +A ToC entry has the following fields: + `uuid`: All files are referred to by a pre-defined Universally Unique + IDentifier [UUID] . The UUIDs are defined in + `include/firmware_image_package`. The platform translates the requested + image name into the corresponding UUID when accessing the package. + `offset_address`: The offset address at which the corresponding payload data + can be found. The offset is calculated from the ToC base address. + `size`: The size of the corresponding payload data in bytes. + `flags`: Flags associated with this entry. Non are yet defined. + +### Firmware Image Package creation tool + +The FIP creation tool can be used to pack specified images into a binary package +that can be loaded by the ARM Trusted Firmware from platform storage. The tool +currently only supports packing bootloader images. Additional image definitions +can be added to the tool as required. + +The tool can be found in `tools/fip_create`. + +### Loading from a Firmware Image Package (FIP) + +The Firmware Image Package (FIP) driver can load images from a binary package on +non-volatile platform storage. For the ARM development platforms, this is +currently NOR FLASH. + +Bootloader images are loaded according to the platform policy as specified by +the function `plat_get_image_source()`. For the ARM development platforms, this +means the platform will attempt to load images from a Firmware Image Package +located at the start of NOR FLASH0. + +The ARM development platforms' policy is to only allow loading of a known set of +images. The platform policy can be modified to allow additional images. + + +11. Use of coherent memory in Trusted Firmware +---------------------------------------------- + +There might be loss of coherency when physical memory with mismatched +shareability, cacheability and memory attributes is accessed by multiple CPUs +(refer to section B2.9 of [ARM ARM] for more details). This possibility occurs +in Trusted Firmware during power up/down sequences when coherency, MMU and +caches are turned on/off incrementally. + +Trusted Firmware defines coherent memory as a region of memory with Device +nGnRE attributes in the translation tables. The translation granule size in +Trusted Firmware is 4KB. This is the smallest possible size of the coherent +memory region. + +By default, all data structures which are susceptible to accesses with +mismatched attributes from various CPUs are allocated in a coherent memory +region (refer to section 2.1 of [Porting Guide]). The coherent memory region +accesses are Outer Shareable, non-cacheable and they can be accessed +with the Device nGnRE attributes when the MMU is turned on. Hence, at the +expense of at least an extra page of memory, Trusted Firmware is able to work +around coherency issues due to mismatched memory attributes. + +The alternative to the above approach is to allocate the susceptible data +structures in Normal WriteBack WriteAllocate Inner shareable memory. This +approach requires the data structures to be designed so that it is possible to +work around the issue of mismatched memory attributes by performing software +cache maintenance on them. + +### Disabling the use of coherent memory in Trusted Firmware + +It might be desirable to avoid the cost of allocating coherent memory on +platforms which are memory constrained. Trusted Firmware enables inclusion of +coherent memory in firmware images through the build flag `USE_COHERENT_MEM`. +This flag is enabled by default. It can be disabled to choose the second +approach described above. + +The below sections analyze the data structures allocated in the coherent memory +region and the changes required to allocate them in normal memory. + +### Coherent memory usage in PSCI implementation + +The `psci_non_cpu_pd_nodes` data structure stores the platform's power domain +tree information for state management of power domains. By default, this data +structure is allocated in the coherent memory region in the Trusted Firmware +because it can be accessed by multple CPUs, either with caches enabled or +disabled. + +typedef struct non_cpu_pwr_domain_node { + /* + * Index of the first CPU power domain node level 0 which has this node + * as its parent. + */ + unsigned int cpu_start_idx; + + /* + * Number of CPU power domains which are siblings of the domain indexed + * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx + * -> cpu_start_idx + ncpus' have this node as their parent. + */ + unsigned int ncpus; + + /* + * Index of the parent power domain node. + * TODO: Figure out whether to whether using pointer is more efficient. + */ + unsigned int parent_node; + + plat_local_state_t local_state; + + unsigned char level; + + /* For indexing the psci_lock array*/ + unsigned char lock_index; +} non_cpu_pd_node_t; + +In order to move this data structure to normal memory, the use of each of its +fields must be analyzed. Fields like `cpu_start_idx`, `ncpus`, `parent_node` +`level` and `lock_index` are only written once during cold boot. Hence removing +them from coherent memory involves only doing a clean and invalidate of the +cache lines after these fields are written. + +The field `local_state` can be concurrently accessed by multiple CPUs in +different cache states. A Lamport's Bakery lock `psci_locks` is used to ensure +mutual exlusion to this field and a clean and invalidate is needed after it +is written. + +### Bakery lock data + +The bakery lock data structure `bakery_lock_t` is allocated in coherent memory +and is accessed by multiple CPUs with mismatched attributes. `bakery_lock_t` is +defined as follows: + + typedef struct bakery_lock { + /* + * The lock_data is a bit-field of 2 members: + * Bit[0] : choosing. This field is set when the CPU is + * choosing its bakery number. + * Bits[1 - 15] : number. This is the bakery number allocated. + */ + volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; + } bakery_lock_t; + +It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU +fields can be read by all CPUs but only written to by the owning CPU. + +Depending upon the data cache line size, the per-CPU fields of the +`bakery_lock_t` structure for multiple CPUs may exist on a single cache line. +These per-CPU fields can be read and written during lock contention by multiple +CPUs with mismatched memory attributes. Since these fields are a part of the +lock implementation, they do not have access to any other locking primitive to +safeguard against the resulting coherency issues. As a result, simple software +cache maintenance is not enough to allocate them in coherent memory. Consider +the following example. + +CPU0 updates its per-CPU field with data cache enabled. This write updates a +local cache line which contains a copy of the fields for other CPUs as well. Now +CPU1 updates its per-CPU field of the `bakery_lock_t` structure with data cache +disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of +its field in any other cache line in the system. This operation will invalidate +the update made by CPU0 as well. + +To use bakery locks when `USE_COHERENT_MEM` is disabled, the lock data structure +has been redesigned. The changes utilise the characteristic of Lamport's Bakery +algorithm mentioned earlier. The bakery_lock structure only allocates the memory +for a single CPU. The macro `DEFINE_BAKERY_LOCK` allocates all the bakery locks +needed for a CPU into a section `bakery_lock`. The linker allocates the memory +for other cores by using the total size allocated for the bakery_lock section +and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to +perform software cache maintenance on the lock data structure without running +into coherency issues associated with mismatched attributes. + +The bakery lock data structure `bakery_info_t` is defined for use when +`USE_COHERENT_MEM` is disabled as follows: + + typedef struct bakery_info { + /* + * The lock_data is a bit-field of 2 members: + * Bit[0] : choosing. This field is set when the CPU is + * choosing its bakery number. + * Bits[1 - 15] : number. This is the bakery number allocated. + */ + volatile uint16_t lock_data; + } bakery_info_t; + +The `bakery_info_t` represents a single per-CPU field of one lock and +the combination of corresponding `bakery_info_t` structures for all CPUs in the +system represents the complete bakery lock. The view in memory for a system +with n bakery locks are: + + bakery_lock section start + |----------------| + | `bakery_info_t`| <-- Lock_0 per-CPU field + | Lock_0 | for CPU0 + |----------------| + | `bakery_info_t`| <-- Lock_1 per-CPU field + | Lock_1 | for CPU0 + |----------------| + | .... | + |----------------| + | `bakery_info_t`| <-- Lock_N per-CPU field + | Lock_N | for CPU0 + ------------------ + | XXXXX | + | Padding to | + | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate + | Granule | continuous memory for remaining CPUs. + ------------------ + | `bakery_info_t`| <-- Lock_0 per-CPU field + | Lock_0 | for CPU1 + |----------------| + | `bakery_info_t`| <-- Lock_1 per-CPU field + | Lock_1 | for CPU1 + |----------------| + | .... | + |----------------| + | `bakery_info_t`| <-- Lock_N per-CPU field + | Lock_N | for CPU1 + ------------------ + | XXXXX | + | Padding to | + | next Cache WB | + | Granule | + ------------------ + +Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an +operation on Lock_N, the corresponding `bakery_info_t` in both CPU0 and CPU1 +`bakery_lock` section need to be fetched and appropriate cache operations need +to be performed for each access. + +On ARM Platforms, bakery locks are used in psci (`psci_locks`) and power controller +driver (`arm_lock`). + + +### Non Functional Impact of removing coherent memory + +Removal of the coherent memory region leads to the additional software overhead +of performing cache maintenance for the affected data structures. However, since +the memory where the data structures are allocated is cacheable, the overhead is +mostly mitigated by an increase in performance. + +There is however a performance impact for bakery locks, due to: +* Additional cache maintenance operations, and +* Multiple cache line reads for each lock operation, since the bakery locks + for each CPU are distributed across different cache lines. + +The implementation has been optimized to mimimize this additional overhead. +Measurements indicate that when bakery locks are allocated in Normal memory, the +minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas +in Device memory the same is 2 micro seconds. The measurements were done on the +Juno ARM development platform. + +As mentioned earlier, almost a page of memory can be saved by disabling +`USE_COHERENT_MEM`. Each platform needs to consider these trade-offs to decide +whether coherent memory should be used. If a platform disables +`USE_COHERENT_MEM` and needs to use bakery locks in the porting layer, it can +optionally define macro `PLAT_PERCPU_BAKERY_LOCK_SIZE` (see the [Porting +Guide]). Refer to the reference platform code for examples. + +12. Code Structure +------------------- + +Trusted Firmware code is logically divided between the three boot loader +stages mentioned in the previous sections. The code is also divided into the +following categories (present as directories in the source code): + +* **Platform specific.** Choice of architecture specific code depends upon + the platform. +* **Common code.** This is platform and architecture agnostic code. +* **Library code.** This code comprises of functionality commonly used by all + other code. +* **Stage specific.** Code specific to a boot stage. +* **Drivers.** +* **Services.** EL3 runtime services, e.g. PSCI or SPD. Specific SPD services + reside in the `services/spd` directory (e.g. `services/spd/tspd`). + +Each boot loader stage uses code from one or more of the above mentioned +categories. Based upon the above, the code layout looks like this: + + Directory Used by BL1? Used by BL2? Used by BL3-1? + bl1 Yes No No + bl2 No Yes No + bl31 No No Yes + plat Yes Yes Yes + drivers Yes No Yes + common Yes Yes Yes + lib Yes Yes Yes + services No No Yes + +The build system provides a non configurable build option IMAGE_BLx for each +boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be +defined by the build system. This enables the Trusted Firmware to compile +certain code only for specific boot loader stages + +All assembler files have the `.S` extension. The linker source files for each +boot stage have the extension `.ld.S`. These are processed by GCC to create the +linker scripts which have the extension `.ld`. + +FDTs provide a description of the hardware platform and are used by the Linux +kernel at boot time. These can be found in the `fdts` directory. + + +13. References +--------------- + +1. Trusted Board Boot Requirements CLIENT PDD (ARM DEN 0006B-5). Available + under NDA through your ARM account representative. + +2. [Power State Coordination Interface PDD (ARM DEN 0022B.b)][PSCI]. + +3. [SMC Calling Convention PDD (ARM DEN 0028A)][SMCCC]. + +4. [ARM Trusted Firmware Interrupt Management Design guide][INTRG]. + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved._ + +[ARM ARM]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.e/index.html "ARMv8-A Reference Manual (ARM DDI0487A.E)" +[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)" +[SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)" +[UUID]: https://tools.ietf.org/rfc/rfc4122.txt "A Universally Unique IDentifier (UUID) URN Namespace" +[User Guide]: ./user-guide.md +[Porting Guide]: ./porting-guide.md +[INTRG]: ./interrupt-framework-design.md +[CPUBM]: ./cpu-specific-build-macros.md.md diff --git a/IPL/SDK/v3m/src/Dummy_BL33/docs/interrupt-framework-design.md b/IPL/SDK/v3m/src/Dummy_BL33/docs/interrupt-framework-design.md new file mode 100644 index 0000000..cee29a3 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/docs/interrupt-framework-design.md @@ -0,0 +1,850 @@ +ARM Trusted Firmware Interrupt Management Design guide +====================================================== + +Contents : + +1. [Introduction](#1-introduction) + * [Assumptions](#11-assumptions) + * [Concepts](#12-concepts) + - [Interrupt Types](#121-interrupt-types) + - [Routing Model](#122-routing-model) + - [Valid Routing Models](#123-valid-routing-models) + + [Secure-EL1 Interrupts](#1231-secure-el1-interrupts) + + [Non-secure Interrupts](#1232-non-secure-interrupts) + - [Mapping of Interrupt Type to Signal](#124-mapping-of-interrupt-type-to-signal) + +2. [Interrupt Management](#2-interrupt-management) + * [Software Components](#21-software-components) + * [Interrupt Registration](#22-interrupt-registration) + - [EL3 Runtime Firmware](#221-el3-runtime-firmware) + - [Secure Payload Dispatcher](#222-secure-payload-dispatcher) + + [Test Secure Payload Dispatcher behavior](#2221-test-secure-payload-dispatcher-behavior) + - [Secure Payload](#223-secure-payload) + + [Secure Payload IHF design w.r.t Secure-EL1 interrupts](#2231-secure-payload-ihf-design-wrt-secure-el1-interrupts) + + [Secure Payload IHF design w.r.t Non-secure interrupts](#2232-secure-payload-ihf-design-wrt-non-secure-interrupts) + + [Test Secure Payload behavior](#2233-test-secure-payload-behavior) + * [Interrupt Handling](#23-interrupt-handling) + - [EL3 Runtime Firmware](#231-el3-runtime-firmware) + - [Secure Payload Dispatcher](#232-secure-payload-dispatcher) + + [Interrupt Entry](#2321-interrupt-entry) + + [Interrupt Exit](#2322-interrupt-exit) + + [Test Secure Payload Dispatcher behavior](#2323-test-secure-payload-dispatcher-behavior) + - [Secure Payload](#233-secure-payload) + + [Test Secure Payload behavior](#2331-test-secure-payload-behavior) + + +1. Introduction +---------------- +This document describes the design of the Interrupt management framework in ARM +Trusted Firmware. This section briefly describes the requirements from this +framework. It also briefly explains some concepts and assumptions. They will +help in understanding the implementation of the framework explained in +subsequent sections. + +This framework is responsible for managing interrupts routed to EL3. It also +allows EL3 software to configure the interrupt routing behavior. Its main +objective is to implement the following two requirements. + +1. It should be possible to route interrupts meant to be handled by secure + software (Secure interrupts) to EL3, when execution is in non-secure state + (normal world). The framework should then take care of handing control of + the interrupt to either software in EL3 or Secure-EL1 depending upon the + software configuration and the GIC implementation. This requirement ensures + that secure interrupts are under the control of the secure software with + respect to their delivery and handling without the possibility of + intervention from non-secure software. + +2. It should be possible to route interrupts meant to be handled by + non-secure software (Non-secure interrupts) to the last executed exception + level in the normal world when the execution is in secure world at + exception levels lower than EL3. This could be done with or without the + knowledge of software executing in Secure-EL1/Secure-EL0. The choice of + approach should be governed by the secure software. This requirement + ensures that non-secure software is able to execute in tandem with the + secure software without overriding it. + +### 1.1 Assumptions +The framework makes the following assumptions to simplify its implementation. + +1. All secure interrupts are handled in Secure-EL1. They can be delivered to + Secure-EL1 via EL3 but they cannot be handled in EL3. It will be possible + to extend the framework to handle secure interrupts in EL3 in the future. + +2. Interrupt exceptions (`PSTATE.I` and `F` bits) are masked during execution + in EL3. + +### 1.2 Concepts + +#### 1.2.1 Interrupt types +The framework categorises an interrupt to be one of the following depending upon +the exception level(s) it is handled in. + +1. Secure EL1 interrupt. This type of interrupt can be routed to EL3 or + Secure-EL1 depending upon the security state of the current execution + context. It is always handled in Secure-EL1. + +2. Non-secure interrupt. This type of interrupt can be routed to EL3, + Secure-EL1, Non-secure EL1 or EL2 depending upon the security state of the + current execution context. It is always handled in either Non-secure EL1 + or EL2. + +3. EL3 interrupt. This type of interrupt can be routed to EL3 or Secure-EL1 + depending upon the security state of the current execution context. It is + always handled in EL3. + +In the current implementation of the framework, all secure interrupts are +treated as Secure EL1 interrupts. It will be possible for EL3 software to +configure a secure interrupt as an EL3 interrupt in future implementations. The +following constants define the various interrupt types in the framework +implementation. + + #define INTR_TYPE_S_EL1 0 + #define INTR_TYPE_EL3 1 + #define INTR_TYPE_NS 2 + + +#### 1.2.2 Routing model +A type of interrupt can be either generated as an FIQ or an IRQ. The target +exception level of an interrupt type is configured through the FIQ and IRQ bits +in the Secure Configuration Register at EL3 (`SCR_EL3.FIQ` and `SCR_EL3.IRQ` +bits). When `SCR_EL3.FIQ`=1, FIQs are routed to EL3. Otherwise they are routed +to the First Exception Level (FEL) capable of handling interrupts. When +`SCR_EL3.IRQ`=1, IRQs are routed to EL3. Otherwise they are routed to the +FEL. This register is configured independently by EL3 software for each security +state prior to entry into a lower exception level in that security state. + +A routing model for a type of interrupt (generated as FIQ or IRQ) is defined as +its target exception level for each security state. It is represented by a +single bit for each security state. A value of `0` means that the interrupt +should be routed to the FEL. A value of `1` means that the interrupt should be +routed to EL3. A routing model is applicable only when execution is not in EL3. + +The default routing model for an interrupt type is to route it to the FEL in +either security state. + +#### 1.2.3 Valid routing models +The framework considers certain routing models for each type of interrupt to be +incorrect as they conflict with the requirements mentioned in Section 1. The +following sub-sections describe all the possible routing models and specify +which ones are valid or invalid. Only the Secure-EL1 and Non-secure interrupt +types are considered as EL3 interrupts are currently unsupported (See 1.1). The +terminology used in the following sub-sections is explained below. + +1. __CSS__. Current Security State. `0` when secure and `1` when non-secure + +2. __TEL3__. Target Exception Level 3. `0` when targeted to the FEL. `1` when + targeted to EL3. + + +##### 1.2.3.1 Secure-EL1 interrupts + +1. __CSS=0, TEL3=0__. Interrupt is routed to the FEL when execution is in + secure state. This is a valid routing model as secure software is in + control of handling secure interrupts. + +2. __CSS=0, TEL3=1__. Interrupt is routed to EL3 when execution is in secure + state. This is a valid routing model as secure software in EL3 can + handover the interrupt to Secure-EL1 for handling. + +3. __CSS=1, TEL3=0__. Interrupt is routed to the FEL when execution is in + non-secure state. This is an invalid routing model as a secure interrupt + is not visible to the secure software which violates the motivation behind + the ARM Security Extensions. + +4. __CSS=1, TEL3=1__. Interrupt is routed to EL3 when execution is in + non-secure state. This is a valid routing model as secure software in EL3 + can handover the interrupt to Secure-EL1 for handling. + + +##### 1.2.3.2 Non-secure interrupts + +1. __CSS=0, TEL3=0__. Interrupt is routed to the FEL when execution is in + secure state. This allows the secure software to trap non-secure + interrupts, perform its bookeeping and hand the interrupt to the + non-secure software through EL3. This is a valid routing model as secure + software is in control of how its execution is pre-empted by non-secure + interrupts. + +2. __CSS=0, TEL3=1__. Interrupt is routed to EL3 when execution is in secure + state. This is a valid routing model as secure software in EL3 can save + the state of software in Secure-EL1/Secure-EL0 before handing the + interrupt to non-secure software. This model requires additional + coordination between Secure-EL1 and EL3 software to ensure that the + former's state is correctly saved by the latter. + +3. __CSS=1, TEL3=0__. Interrupt is routed to FEL when execution is in + non-secure state. This is an valid routing model as a non-secure interrupt + is handled by non-secure software. + +4. __CSS=1, TEL3=1__. Interrupt is routed to EL3 when execution is in + non-secure state. This is an invalid routing model as there is no valid + reason to route the interrupt to EL3 software and then hand it back to + non-secure software for handling. + + +#### 1.2.4 Mapping of interrupt type to signal +The framework is meant to work with any interrupt controller implemented by a +platform. A interrupt controller could generate a type of interrupt as either an +FIQ or IRQ signal to the CPU depending upon the current security state.The +mapping between the type and signal is known only to the platform. The framework +uses this information to determine whether the IRQ or the FIQ bit should be +programmed in `SCR_EL3` while applying the routing model for a type of +interrupt. The platform provides this information through the +`plat_interrupt_type_to_line()` API (described in the [Porting +Guide]). For example, on the FVP port when the platform uses an ARM GICv2 +interrupt controller, Secure-EL1 interrupts are signalled through the FIQ signal +while Non-secure interrupts are signalled through the IRQ signal. This applies +when execution is in either security state. + + +2. Interrupt management +----------------------- +The following sections describe how interrupts are managed by the interrupt +handling framework. This entails: + +1. Providing an interface to allow registration of a handler and specification + of the routing model for a type of interrupt. + +2. Implementing support to hand control of an interrupt type to its registered + handler when the interrupt is generated. + +Both aspects of interrupt management involve various components in the secure +software stack spanning from EL3 to Secure-EL1. These components are described +in the section 2.1. The framework stores information associated with each type +of interrupt in the following data structure. + +``` +typedef struct intr_type_desc { + interrupt_type_handler_t handler; + uint32_t flags; + uint32_t scr_el3[2]; +} intr_type_desc_t; +``` + +The `flags` field stores the routing model for the interrupt type in +bits[1:0]. Bit[0] stores the routing model when execution is in the secure +state. Bit[1] stores the routing model when execution is in the non-secure +state. As mentioned in Section 1.2.2, a value of `0` implies that the interrupt +should be targeted to the FEL. A value of `1` implies that it should be targeted +to EL3. The remaining bits are reserved and SBZ. The helper macro +`set_interrupt_rm_flag()` should be used to set the bits in the `flags` +parameter. + +The `scr_el3[2]` field also stores the routing model but as a mapping of the +model in the `flags` field to the corresponding bit in the `SCR_EL3` for each +security state. + +The framework also depends upon the platform port to configure the interrupt +controller to distinguish between secure and non-secure interrupts. The platform +is expected to be aware of the secure devices present in the system and their +associated interrupt numbers. It should configure the interrupt controller to +enable the secure interrupts, ensure that their priority is always higher than +the non-secure interrupts and target them to the primary CPU. It should also +export the interface described in the [Porting Guide] to enable +handling of interrupts. + +In the remainder of this document, for the sake of simplicity it is assumed that +the FIQ signal is used to generate Secure-EL1 interrupts and the IRQ signal is +used to generate non-secure interrupts in either security state. + +### 2.1 Software components +Roles and responsibilities for interrupt management are sub-divided between the +following components of software running in EL3 and Secure-EL1. Each component is +briefly described below. + +1. EL3 Runtime Firmware. This component is common to all ports of the ARM + Trusted Firmware. + +2. Secure Payload Dispatcher (SPD) service. This service interfaces with the + Secure Payload (SP) software which runs in exception levels lower than EL3 + i.e. Secure-EL1/Secure-EL0. It is responsible for switching execution + between software running in secure and non-secure states at exception + levels lower than EL3. A switch is triggered by a Secure Monitor Call from + either state. It uses the APIs exported by the Context management library + to implement this functionality. Switching execution between the two + security states is a requirement for interrupt management as well. This + results in a significant dependency on the SPD service. ARM Trusted + firmware implements an example Test Secure Payload Dispatcher (TSPD) + service. + + An SPD service plugs into the EL3 runtime firmware and could be common to + some ports of the ARM Trusted Firmware. + +3. Secure Payload (SP). On a production system, the Secure Payload corresponds + to a Secure OS which runs in Secure-EL1/Secure-EL0. It interfaces with the + SPD service to manage communication with non-secure software. ARM Trusted + Firmware implements an example secure payload called Test Secure Payload + (TSP) which runs only in Secure-EL1. + + A Secure payload implementation could be common to some ports of the ARM + Trusted Firmware just like the SPD service. + + +### 2.2 Interrupt registration +This section describes in detail the role of each software component (see 2.1) +during the registration of a handler for an interrupt type. + + +#### 2.2.1 EL3 runtime firmware +This component declares the following prototype for a handler of an interrupt type. + + typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, + uint32_t flags, + void *handle, + void *cookie); + +The value of the `id` parameter depends upon the definition of the +`IMF_READ_INTERRUPT_ID` build time flag. When the flag is defined, `id` contains +the number of the highest priority pending interrupt of the type that this +handler was registered for. When the flag is not defined `id` contains +`INTR_ID_UNAVAILABLE`. + +The `flags` parameter contains miscellaneous information as follows. + +1. Security state, bit[0]. This bit indicates the security state of the lower + exception level when the interrupt was generated. A value of `1` means + that it was in the non-secure state. A value of `0` indicates that it was + in the secure state. This bit can be used by the handler to ensure that + interrupt was generated and routed as per the routing model specified + during registration. + +2. Reserved, bits[31:1]. The remaining bits are reserved for future use. + +The `handle` parameter points to the `cpu_context` structure of the current CPU +for the security state specified in the `flags` parameter. + +Once the handler routine completes, execution will return to either the secure +or non-secure state. The handler routine should return a pointer to +`cpu_context` structure of the current CPU for the the target security state. It +should treat all error conditions as critical errors and take appropriate action +within its implementation e.g. use assertion failures. + +The runtime firmware provides the following API for registering a handler for a +particular type of interrupt. A Secure Payload Dispatcher service should use +this API to register a handler for Secure-EL1 and optionally for non-secure +interrupts. This API also requires the caller to specify the routing model for +the type of interrupt. + + int32_t register_interrupt_type_handler(uint32_t type, + interrupt_type_handler handler, + uint64_t flags); + + +The `type` parameter can be one of the three interrupt types listed above i.e. +`INTR_TYPE_S_EL1`, `INTR_TYPE_NS` & `INTR_TYPE_EL3` (currently unimplemented). +The `flags` parameter is as described in Section 2. + +The function will return `0` upon a successful registration. It will return +`-EALREADY` in case a handler for the interrupt type has already been +registered. If the `type` is unrecognised or the `flags` or the `handler` are +invalid it will return `-EINVAL`. It will return `-ENOTSUP` if the specified +`type` is not supported by the framework i.e. `INTR_TYPE_EL3`. + +Interrupt routing is governed by the configuration of the `SCR_EL3.FIQ/IRQ` bits +prior to entry into a lower exception level in either security state. The +context management library maintains a copy of the `SCR_EL3` system register for +each security state in the `cpu_context` structure of each CPU. It exports the +following APIs to let EL3 Runtime Firmware program and retrieve the routing +model for each security state for the current CPU. The value of `SCR_EL3` stored +in the `cpu_context` is used by the `el3_exit()` function to program the +`SCR_EL3` register prior to returning from the EL3 exception level. + + uint32_t cm_get_scr_el3(uint32_t security_state); + void cm_write_scr_el3_bit(uint32_t security_state, + uint32_t bit_pos, + uint32_t value); + +`cm_get_scr_el3()` returns the value of the `SCR_EL3` register for the specified +security state of the current CPU. `cm_write_scr_el3()` writes a `0` or `1` to +the bit specified by `bit_pos`. `register_interrupt_type_handler()` invokes +`set_routing_model()` API which programs the `SCR_EL3` according to the routing +model using the `cm_get_scr_el3()` and `cm_write_scr_el3_bit()` APIs. + +It is worth noting that in the current implementation of the framework, the EL3 +runtime firmware is responsible for programming the routing model. The SPD is +responsible for ensuring that the routing model has been adhered to upon +receiving an interrupt. + +#### 2.2.2 Secure payload dispatcher +A SPD service is responsible for determining and maintaining the interrupt +routing model supported by itself and the Secure Payload. It is also responsible +for ferrying interrupts between secure and non-secure software depending upon +the routing model. It could determine the routing model at build time or at +runtime. It must use this information to register a handler for each interrupt +type using the `register_interrupt_type_handler()` API in EL3 runtime firmware. + +If the routing model is not known to the SPD service at build time, then it must +be provided by the SP as the result of its initialisation. The SPD should +program the routing model only after SP initialisation has completed e.g. in the +SPD initialisation function pointed to by the `bl32_init` variable. + +The SPD should determine the mechanism to pass control to the Secure Payload +after receiving an interrupt from the EL3 runtime firmware. This information +could either be provided to the SPD service at build time or by the SP at +runtime. + +#### 2.2.2.1 Test secure payload dispatcher behavior +The TSPD only handles Secure-EL1 interrupts and is provided with the following +routing model at build time. + +* Secure-EL1 interrupts are routed to EL3 when execution is in non-secure + state and are routed to the FEL when execution is in the secure state + i.e __CSS=0, TEL3=0__ & __CSS=1, TEL3=1__ for Secure-EL1 interrupts + +* The default routing model is used for non-secure interrupts i.e they are + routed to the FEL in either security state i.e __CSS=0, TEL3=0__ & + __CSS=1, TEL3=0__ for Non-secure interrupts + +It performs the following actions in the `tspd_init()` function to fulfill the +requirements mentioned earlier. + +1. It passes control to the Test Secure Payload to perform its + initialisation. The TSP provides the address of the vector table + `tsp_vectors` in the SP which also includes the handler for Secure-EL1 + interrupts in the `fiq_entry` field. The TSPD passes control to the TSP at + this address when it receives a Secure-EL1 interrupt. + + The handover agreement between the TSP and the TSPD requires that the TSPD + masks all interrupts (`PSTATE.DAIF` bits) when it calls + `tsp_fiq_entry()`. The TSP has to preserve the callee saved general + purpose, SP_EL1/Secure-EL0, LR, VFP and system registers. It can use + `x0-x18` to enable its C runtime. + +2. The TSPD implements a handler function for Secure-EL1 interrupts. It + registers it with the EL3 runtime firmware using the + `register_interrupt_type_handler()` API as follows + + /* Forward declaration */ + interrupt_type_handler tspd_secure_el1_interrupt_handler; + int32_t rc, flags = 0; + set_interrupt_rm_flag(flags, NON_SECURE); + rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, + tspd_secure_el1_interrupt_handler, + flags); + assert(rc == 0); + +#### 2.2.3 Secure payload +A Secure Payload must implement an interrupt handling framework at Secure-EL1 +(Secure-EL1 IHF) to support its chosen interrupt routing model. Secure payload +execution will alternate between the below cases. + +1. In the code where IRQ, FIQ or both interrupts are enabled, if an interrupt + type is targeted to the FEL, then it will be routed to the Secure-EL1 + exception vector table. This is defined as the asynchronous model of + handling interrupts. This mode applies to both Secure-EL1 and non-secure + interrupts. + +2. In the code where both interrupts are disabled, if an interrupt type is + targeted to the FEL, then execution will eventually migrate to the + non-secure state. Any non-secure interrupts will be handled as described + in the routing model where __CSS=1 and TEL3=0__. Secure-EL1 interrupts + will be routed to EL3 (as per the routing model where __CSS=1 and + TEL3=1__) where the SPD service will hand them to the SP. This is defined + as the synchronous mode of handling interrupts. + +The interrupt handling framework implemented by the SP should support one or +both these interrupt handling models depending upon the chosen routing model. + +The following list briefly describes how the choice of a valid routing model +(See 1.2.3) effects the implementation of the Secure-EL1 IHF. If the choice of +the interrupt routing model is not known to the SPD service at compile time, +then the SP should pass this information to the SPD service at runtime during +its initialisation phase. + +As mentioned earlier, it is assumed that the FIQ signal is used to generate +Secure-EL1 interrupts and the IRQ signal is used to generate non-secure +interrupts in either security state. + +##### 2.2.3.1 Secure payload IHF design w.r.t secure-EL1 interrupts +1. __CSS=0, TEL3=0__. If `PSTATE.F=0`, Secure-EL1 interrupts will be + trigerred at one of the Secure-EL1 FIQ exception vectors. The Secure-EL1 + IHF should implement support for handling FIQ interrupts asynchronously. + + If `PSTATE.F=1` then Secure-EL1 interrupts will be handled as per the + synchronous interrupt handling model. The SP could implement this scenario + by exporting a seperate entrypoint for Secure-EL1 interrupts to the SPD + service during the registration phase. The SPD service would also need to + know the state of the system, general purpose and the `PSTATE` registers + in which it should arrange to return execution to the SP. The SP should + provide this information in an implementation defined way during the + registration phase if it is not known to the SPD service at build time. + +2. __CSS=1, TEL3=1__. Interrupts are routed to EL3 when execution is in + non-secure state. They should be handled through the synchronous interrupt + handling model as described in 1. above. + +3. __CSS=0, TEL3=1__. Secure interrupts are routed to EL3 when execution is in + secure state. They will not be visible to the SP. The `PSTATE.F` bit in + Secure-EL1/Secure-EL0 will not mask FIQs. The EL3 runtime firmware will + call the handler registered by the SPD service for Secure-EL1 + interrupts. Secure-EL1 IHF should then handle all Secure-EL1 interrupt + through the synchronous interrupt handling model described in 1. above. + + +##### 2.2.3.2 Secure payload IHF design w.r.t non-secure interrupts +1. __CSS=0, TEL3=0__. If `PSTATE.I=0`, non-secure interrupts will be + trigerred at one of the Secure-EL1 IRQ exception vectors . The Secure-EL1 + IHF should co-ordinate with the SPD service to transfer execution to the + non-secure state where the interrupt should be handled e.g the SP could + allocate a function identifier to issue a SMC64 or SMC32 to the SPD + service which indicates that the SP execution has been pre-empted by a + non-secure interrupt. If this function identifier is not known to the SPD + service at compile time then the SP could provide it during the + registration phase. + + If `PSTATE.I=1` then the non-secure interrupt will pend until execution + resumes in the non-secure state. + +2. __CSS=0, TEL3=1__. Non-secure interrupts are routed to EL3. They will not + be visible to the SP. The `PSTATE.I` bit in Secure-EL1/Secure-EL0 will + have not effect. The SPD service should register a non-secure interrupt + handler which should save the SP state correctly and resume execution in + the non-secure state where the interrupt will be handled. The Secure-EL1 + IHF does not need to take any action. + +3. __CSS=1, TEL3=0__. Non-secure interrupts are handled in the FEL in + non-secure state (EL1/EL2) and are not visible to the SP. This routing + model does not affect the SP behavior. + + +A Secure Payload must also ensure that all Secure-EL1 interrupts are correctly +configured at the interrupt controller by the platform port of the EL3 runtime +firmware. It should configure any additional Secure-EL1 interrupts which the EL3 +runtime firmware is not aware of through its platform port. + +#### 2.2.3.3 Test secure payload behavior +The routing model for Secure-EL1 and non-secure interrupts chosen by the TSP is +described in Section 2.2.2. It is known to the TSPD service at build time. + +The TSP implements an entrypoint (`tsp_fiq_entry()`) for handling Secure-EL1 +interrupts taken in non-secure state and routed through the TSPD service +(synchronous handling model). It passes the reference to this entrypoint via +`tsp_vectors` to the TSPD service. + +The TSP also replaces the default exception vector table referenced through the +`early_exceptions` variable, with a vector table capable of handling FIQ and IRQ +exceptions taken at the same (Secure-EL1) exception level. This table is +referenced through the `tsp_exceptions` variable and programmed into the +VBAR_EL1. It caters for the asynchronous handling model. + +The TSP also programs the Secure Physical Timer in the ARM Generic Timer block +to raise a periodic interrupt (every half a second) for the purpose of testing +interrupt management across all the software components listed in 2.1 + + +### 2.3 Interrupt handling +This section describes in detail the role of each software component (see +Section 2.1) in handling an interrupt of a particular type. + +#### 2.3.1 EL3 runtime firmware +The EL3 runtime firmware populates the IRQ and FIQ exception vectors referenced +by the `runtime_exceptions` variable as follows. + +1. IRQ and FIQ exceptions taken from the current exception level with + `SP_EL0` or `SP_EL3` are reported as irrecoverable error conditions. As + mentioned earlier, EL3 runtime firmware always executes with the + `PSTATE.I` and `PSTATE.F` bits set. + +2. The following text describes how the IRQ and FIQ exceptions taken from a + lower exception level using AArch64 or AArch32 are handled. + +When an interrupt is generated, the vector for each interrupt type is +responsible for: + +1. Saving the entire general purpose register context (x0-x30) immediately + upon exception entry. The registers are saved in the per-cpu `cpu_context` + data structure referenced by the `SP_EL3`register. + +2. Saving the `ELR_EL3`, `SP_EL0` and `SPSR_EL3` system registers in the + per-cpu `cpu_context` data structure referenced by the `SP_EL3` register. + +3. Switching to the C runtime stack by restoring the `CTX_RUNTIME_SP` value + from the per-cpu `cpu_context` data structure in `SP_EL0` and + executing the `msr spsel, #0` instruction. + +4. Determining the type of interrupt. Secure-EL1 interrupts will be signalled + at the FIQ vector. Non-secure interrupts will be signalled at the IRQ + vector. The platform should implement the following API to determine the + type of the pending interrupt. + + uint32_t plat_ic_get_interrupt_type(void); + + It should return either `INTR_TYPE_S_EL1` or `INTR_TYPE_NS`. + +5. Determining the handler for the type of interrupt that has been generated. + The following API has been added for this purpose. + + interrupt_type_handler get_interrupt_type_handler(uint32_t interrupt_type); + + It returns the reference to the registered handler for this interrupt + type. The `handler` is retrieved from the `intr_type_desc_t` structure as + described in Section 2. `NULL` is returned if no handler has been + registered for this type of interrupt. This scenario is reported as an + irrecoverable error condition. + +6. Calling the registered handler function for the interrupt type generated. + The firmware also determines the interrupt id if the IMF_READ_INTERRUPT_ID + build time flag is set. The id is set to `INTR_ID_UNAVAILABLE` if the flag + is not set. The id along with the current security state and a reference to + the `cpu_context_t` structure for the current security state are passed to + the handler function as its arguments. + + The handler function returns a reference to the per-cpu `cpu_context_t` + structure for the target security state. + +7. Calling `el3_exit()` to return from EL3 into a lower exception level in + the security state determined by the handler routine. The `el3_exit()` + function is responsible for restoring the register context from the + `cpu_context_t` data structure for the target security state. + + +#### 2.3.2 Secure payload dispatcher + +##### 2.3.2.1 Interrupt entry +The SPD service begins handling an interrupt when the EL3 runtime firmware calls +the handler function for that type of interrupt. The SPD service is responsible +for the following: + +1. Validating the interrupt. This involves ensuring that the interrupt was + generating according to the interrupt routing model specified by the SPD + service during registration. It should use the interrupt id and the + security state of the exception level (passed in the `flags` parameter of + the handler) where the interrupt was taken from to determine this. If the + interrupt is not recognised then the handler should treat it as an + irrecoverable error condition. + + A SPD service can register a handler for Secure-EL1 and/or Non-secure + interrupts. The following text describes further error scenarios keeping + this in mind: + + 1. __SPD service has registered a handler for Non-secure interrupts__: + When an interrupt is received by the handler, it could check its id + to ensure it has been configured as a non-secure interrupt at the + interrupt controller. A secure interrupt should never be handed to + the non-secure interrupt handler. A non-secure interrupt should + never be routed to EL3 when execution is in non-secure state. The + handler could check the security state flag to ensure this. + + 2. __SPD service has registered a handler for Secure-EL1 interrupts__: + When an interrupt is received by the handler, it could check its id + to ensure it has been configured as a secure interrupt at the + interrupt controller. A non-secure interrupt should never be handed + to the secure interrupt handler. A routing model could be chosen + where Secure-EL1 interrupts are routed to S-EL1 instead of EL3 when + execution is in secure state. If the handler receives a Secure-EL1 + interrupt it should check which security state has the interrupt + originated from. A Secure-EL1 interrupt generated when execution is in + secure state would be invalid in this routing model. The handler could + use the security state flag to check this. + + The SPD service should use the platform API: + `plat_ic_get_interrupt_type()` to determine the type of interrupt for the + specified id. + +2. Determining whether the security state of the exception level for handling + the interrupt is the same as the security state of the exception level + where the interrupt was generated. This depends upon the routing model and + type of the interrupt. The SPD should use this information to determine if + a context switch is required. The following two cases would require a + context switch from secure to non-secure or vice-versa. + + 1. A Secure-EL1 interrupt taken from the non-secure state should be + routed to the Secure Payload. + + 2. A non-secure interrupt taken from the secure state should be routed + to the last known non-secure exception level. + + The SPD service must save the system register context of the current + security state. It must then restore the system register context of the + target security state. It should use the `cm_set_next_eret_context()` API + to ensure that the next `cpu_context` to be restored is of the target + security state. + + If the target state is secure then execution should be handed to the SP as + per the synchronous interrupt handling model it implements. A Secure-EL1 + interrupt can be routed to EL3 while execution is in the SP. This implies + that SP execution can be preempted while handling an interrupt by a + another higher priority Secure-EL1 interrupt (or a EL3 interrupt in the + future). The SPD service should manage secure interrupt priorities before + handing control to the SP to prevent this type of preemption which can + leave the system in an inconsistent state. + +3. Setting the return value of the handler to the per-cpu `cpu_context` if + the interrupt has been successfully validated and ready to be handled at a + lower exception level. + +The routing model allows non-secure interrupts to be taken to Secure-EL1 when in +secure state. The SPD service and the SP should implement a mechanism for +routing these interrupts to the last known exception level in the non-secure +state. The former should save the SP context, restore the non-secure context and +arrange for entry into the non-secure state so that the interrupt can be +handled. + +##### 2.3.2.2 Interrupt exit +When the Secure Payload has finished handling a Secure-EL1 interrupt, it could +return control back to the SPD service through a SMC32 or SMC64. The SPD service +should handle this secure monitor call so that execution resumes in the +exception level and the security state from where the Secure-EL1 interrupt was +originally taken. + +##### 2.3.2.3 Test secure payload dispatcher behavior +The example TSPD service registers a handler for Secure-EL1 interrupts taken +from the non-secure state. Its handler `tspd_secure_el1_interrupt_handler()` +takes the following actions upon being invoked. + +1. It uses the `id` parameter to query the interrupt controller to ensure + that the interrupt is a Secure-EL1 interrupt. It asserts if this is not + the case. + +2. It uses the security state provided in the `flags` parameter to ensure + that the secure interrupt originated from the non-secure state. It asserts + if this is not the case. + +3. It saves the system register context for the non-secure state by calling + `cm_el1_sysregs_context_save(NON_SECURE);`. + +4. It sets the `ELR_EL3` system register to `tsp_fiq_entry` and sets the + `SPSR_EL3.DAIF` bits in the secure CPU context. It sets `x0` to + `TSP_HANDLE_FIQ_AND_RETURN`. If the TSP was in the middle of handling a + standard SMC, then the `ELR_EL3` and `SPSR_EL3` registers in the secure CPU + context are saved first. + +5. It restores the system register context for the secure state by calling + `cm_el1_sysregs_context_restore(SECURE);`. + +6. It ensures that the secure CPU context is used to program the next + exception return from EL3 by calling `cm_set_next_eret_context(SECURE);`. + +7. It returns the per-cpu `cpu_context` to indicate that the interrupt can + now be handled by the SP. `x1` is written with the value of `elr_el3` + register for the non-secure state. This information is used by the SP for + debugging purposes. + +The figure below describes how the interrupt handling is implemented by the TSPD +when a Secure-EL1 interrupt is generated when execution is in the non-secure +state. + +![Image 1](diagrams/sec-int-handling.png?raw=true) + +The TSP issues an SMC with `TSP_HANDLED_S_EL1_FIQ` as the function identifier to +signal completion of interrupt handling. + +The TSP issues an SMC with `TSP_PREEMPTED` as the function identifier to signal +generation of a non-secure interrupt in Secure-EL1. + +The TSPD service takes the following actions in `tspd_smc_handler()` function +upon receiving an SMC with `TSP_HANDLED_S_EL1_FIQ` and `TSP_PREEMPTED` as the +function identifiers: + +1. It ensures that the call originated from the secure state otherwise + execution returns to the non-secure state with `SMC_UNK` in `x0`. + +2. If the function identifier is `TSP_HANDLED_S_EL1_FIQ`, it restores the + saved `ELR_EL3` and `SPSR_EL3` system registers back to the secure CPU + context (see step 4 above) in case the TSP had been preempted by a non + secure interrupt earlier. It does not save the secure context since the + TSP is expected to preserve it (see Section 2.2.2.1) + +3. If the function identifier is `TSP_PREEMPTED`, it saves the system + register context for the secure state by calling + `cm_el1_sysregs_context_save(SECURE)`. + +4. It restores the system register context for the non-secure state by + calling `cm_el1_sysregs_context_restore(NON_SECURE)`. It sets `x0` to + `SMC_PREEMPTED` if the incoming function identifier is + `TSP_PREEMPTED`. The Normal World is expected to resume the TSP after the + non-secure interrupt handling by issuing an SMC with `TSP_FID_RESUME` as + the function identifier. + +5. It ensures that the non-secure CPU context is used to program the next + exception return from EL3 by calling + `cm_set_next_eret_context(NON_SECURE)`. + +6. `tspd_smc_handler()` returns a reference to the non-secure `cpu_context` + as the return value. + +As mentioned in 4. above, if a non-secure interrupt preempts the TSP execution +then the non-secure software issues an SMC with `TSP_FID_RESUME` as the function +identifier to resume TSP execution. The TSPD service takes the following actions +in `tspd_smc_handler()` function upon receiving this SMC: + +1. It ensures that the call originated from the non secure state. An + assertion is raised otherwise. + +2. Checks whether the TSP needs a resume i.e check if it was preempted. It + then saves the system register context for the non-secure state by calling + `cm_el1_sysregs_context_save(NON_SECURE)`. + +3. Restores the secure context by calling + `cm_el1_sysregs_context_restore(SECURE)` + +4. It ensures that the secure CPU context is used to program the next + exception return from EL3 by calling `cm_set_next_eret_context(SECURE)`. + +5. `tspd_smc_handler()` returns a reference to the secure `cpu_context` as the + return value. + +The figure below describes how the TSP/TSPD handle a non-secure interrupt when +it is generated during execution in the TSP with `PSTATE.I` = 0. + +![Image 2](diagrams/non-sec-int-handling.png?raw=true) + + +#### 2.3.3 Secure payload +The SP should implement one or both of the synchronous and asynchronous +interrupt handling models depending upon the interrupt routing model it has +chosen (as described in 2.2.3). + +In the synchronous model, it should begin handling a Secure-EL1 interrupt after +receiving control from the SPD service at an entrypoint agreed upon during build +time or during the registration phase. Before handling the interrupt, the SP +should save any Secure-EL1 system register context which is needed for resuming +normal execution in the SP later e.g. `SPSR_EL1, `ELR_EL1`. After handling the +interrupt, the SP could return control back to the exception level and security +state where the interrupt was originally taken from. The SP should use an SMC32 +or SMC64 to ask the SPD service to do this. + +In the asynchronous model, the Secure Payload is responsible for handling +non-secure and Secure-EL1 interrupts at the IRQ and FIQ vectors in its exception +vector table when `PSTATE.I` and `PSTATE.F` bits are 0. As described earlier, +when a non-secure interrupt is generated, the SP should coordinate with the SPD +service to pass control back to the non-secure state in the last known exception +level. This will allow the non-secure interrupt to be handled in the non-secure +state. + +##### 2.3.3.1 Test secure payload behavior +The TSPD hands control of a Secure-EL1 interrupt to the TSP at the +`tsp_fiq_entry()`. The TSP handles the interrupt while ensuring that the +handover agreement described in Section 2.2.2.1 is maintained. It updates some +statistics by calling `tsp_update_sync_fiq_stats()`. It then calls +`tsp_fiq_handler()` which. + +1. Checks whether the interrupt is the secure physical timer interrupt. It + uses the platform API `plat_ic_get_pending_interrupt_id()` to get the + interrupt number. + +2. Handles the interrupt by acknowledging it using the + `plat_ic_acknowledge_interrupt()` platform API, calling + `tsp_generic_timer_handler()` to reprogram the secure physical generic + timer and calling the `plat_ic_end_of_interrupt()` platform API to signal + end of interrupt processing. + +The TSP passes control back to the TSPD by issuing an SMC64 with +`TSP_HANDLED_S_EL1_FIQ` as the function identifier. + +The TSP handles interrupts under the asynchronous model as follows. + +1. Secure-EL1 interrupts are handled by calling the `tsp_fiq_handler()` + function. The function has been described above. + +2. Non-secure interrupts are handled by issuing an SMC64 with `TSP_PREEMPTED` + as the function identifier. Execution resumes at the instruction that + follows this SMC instruction when the TSPD hands control to the TSP in + response to an SMC with `TSP_FID_RESUME` as the function identifier from + the non-secure state (see section 2.3.2.1). + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._ + +[Porting Guide]: ./porting-guide.md diff --git a/IPL/SDK/v3m/src/Dummy_BL33/docs/plat/nvidia-tegra.md b/IPL/SDK/v3m/src/Dummy_BL33/docs/plat/nvidia-tegra.md new file mode 100644 index 0000000..b29532c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/docs/plat/nvidia-tegra.md @@ -0,0 +1,70 @@ +Tegra SoCs - Overview +====================== + +* T210 +------- + +T210 has Quad ARM® Cortex®-A57 cores in a switched configuration with a +companion set of quad ARM Cortex-A53 cores. The Cortex-A57 and A53 cores +support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code +including legacy ARMv7 applications. The Cortex-A57 processors each have +48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared +Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction +and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache. + +* T132 +------- + +Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is +fully ARMv8 architecture compatible. Each of the two Denver cores +implements a 7-way superscalar microarchitecture (up to 7 concurrent +micro-ops can be executed per clock), and includes a 128KB 4-way L1 +instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2 +cache, which services both cores. + +Denver implements an innovative process called Dynamic Code Optimization, +which optimizes frequently used software routines at runtime into dense, +highly tuned microcode-equivalent routines. These are stored in a +dedicated, 128MB main-memory-based optimization cache. After being read +into the instruction cache, the optimized micro-ops are executed, +re-fetched and executed from the instruction cache as long as needed and +capacity allows. + +Effectively, this reduces the need to re-optimize the software routines. +Instead of using hardware to extract the instruction-level parallelism +(ILP) inherent in the code, Denver extracts the ILP once via software +techniques, and then executes those routines repeatedly, thus amortizing +the cost of ILP extraction over the many execution instances. + +Denver also features new low latency power-state transitions, in addition +to extensive power-gating and dynamic voltage and clock scaling based on +workloads. + +Directory structure +==================== + +* plat/nvidia/tegra/common - Common code for all Tegra SoCs +* plat/nvidia/tegra/soc/txxx - Chip specific code + +Trusted OS dispatcher +===================== +Tegra supports multiple Trusted OS', Trusted Little Kernel (TLK) being one of +them. In order to include the 'tlkd' dispatcher in the image, pass 'SPD=tlkd' +on the command line while preparing a bl31 image. This allows other Trusted OS +vendors to use the upstream code and include their dispatchers in the image +without changing any makefiles. + +Preparing the BL31 image to run on Tegra SoCs +=================================================== +'CROSS_COMPILE=/bin/aarch64-none-elf- make PLAT=tegra \ +TARGET_SOC= SPD= bl31' + +Platforms wanting to use different TZDRAM_BASE, can add 'TZDRAM_BASE=' +to the build command line. + +Power Management +================ +The PSCI implementation expects each platform to expose the 'power state' +parameter to be used during the 'SYSTEM SUSPEND' call. The state-id field +is implementation defined on Tegra SoCs and is preferably defined by +tegra_def.h. diff --git a/IPL/SDK/v3m/src/Dummy_BL33/docs/platform-migration-guide.md b/IPL/SDK/v3m/src/Dummy_BL33/docs/platform-migration-guide.md new file mode 100644 index 0000000..f6790ef --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/docs/platform-migration-guide.md @@ -0,0 +1,575 @@ +Guide to migrate to new Platform porting interface +================================================== + +Contents +-------- + +1. [Introduction](#1--introduction) +2. [Platform API modification due to PSCI framework changes](#2--platform-api-modification-due-to-psci-framework-changes) + * [Power domain topology framework platform API modifications](#21-power-domain-topology-framework-platform-api-modifications) + * [Composite power state framework platform API modifications](#22-composite-power-state-framework-platform-api-modifications) + * [Miscellaneous modifications](#23-miscellaneous-modifications) +3. [Compatibility layer](#3--compatibility-layer) +4. [Deprecated Platform API](#4--deprecated-platform-api) + +- - - - - - - - - - - - - - - - - - + + +1. Introduction +---------------- + +The PSCI implementation in Trusted Firmware has undergone a redesign because of +three requirements that the PSCI 1.0 specification introduced : + +* Removing the framework assumption about the structure of the MPIDR, and + its relation to the power topology enables support for deeper and more + complex hierarchies. + +* Reworking the power state coordination implementation in the framework + to support the more detailed PSCI 1.0 requirements and reduce platform + port complexity + +* Enable the use of the extended power_state parameter and the larger StateID + field + +The PSCI 1.0 implementation introduces new frameworks to fulfill the above +requirements. These framework changes mean that the platform porting API must +also be modified. This document is a guide to assist migration of the existing +platform ports to the new platform API. + +This document describes the new platform API and compares it with the +deprecated API. It also describes the compatibility layer that enables the +existing platform ports to work with the PSCI 1.0 implementation. The +deprecated platform API is documented for reference. + + +2. Platform API modification due to PSCI framework changes +----------------------------------------------------------- + +This section describes changes to the platform APIs. + + +2.1 Power domain topology framework platform API modifications +-------------------------------------------------------------- + +This removes the assumption in the PSCI implementation that MPIDR +based affinity instances map directly to power domains. A power domain, as +described in section 4.2 of [PSCI], could contain a core or a logical group +of cores (a cluster) which share some state on which power management +operations can be performed. The existing affinity instance based APIs +`plat_get_aff_count()` and `plat_get_aff_state()` are deprecated. The new +platform interfaces that are introduced for this framework are: + +* `plat_core_pos_by_mpidr()` +* `plat_my_core_pos()` +* `plat_get_power_domain_tree_desc()` + +`plat_my_core_pos()` and `plat_core_pos_by_mpidr()` are mandatory +and are meant to replace the existing `platform_get_core_pos()` API. +The description of these APIs can be found in the [Porting Guide][my_core_pos]. +These are used by the power domain topology framework such that: + +1. The generic PSCI code does not generate MPIDRs or use them to query the + platform about the number of power domains at a particular power level. The + `plat_get_power_domain_tree_desc()` provides a description of the power + domain tree on the SoC through a pointer to the byte array containing the + power domain topology tree description data structure. + +2. The linear indices returned by `plat_core_pos_by_mpidr()` and + `plat_my_core_pos()` are used to retrieve core power domain nodes from + the power domain tree. These core indices are unique for a core and it is a + number between `0` and `PLATFORM_CORE_COUNT - 1`. The platform can choose + to implement a static mapping between `MPIDR` and core index or implement + a dynamic mapping, choosing to skip the unavailable/unused cores to compact + the core indices. + +In addition, the platforms must define the macros `PLAT_NUM_PWR_DOMAINS` and +`PLAT_MAX_PWR_LVL` which replace the macros `PLAT_NUM_AFFS` and +`PLATFORM_MAX_AFFLVL` respectively. On platforms where the affinity instances +correspond to power domains, the values of new macros remain the same as the +old ones. + +More details on the power domain topology description and its platform +interface can be found in [psci pd tree]. + + +2.2 Composite power state framework platform API modifications +-------------------------------------------------------------- + +The state-ID field in the power-state parameter of a CPU_SUSPEND call can be +used to describe the composite power states specific to a platform. The existing +PSCI state coordination had the limitation that it operates on a run/off +granularity of power states and it did not interpret the state-ID field. This +was acceptable as the specification requirement in PSCI 0.2 and the framework's +approach to coordination only required maintaining a reference +count of the number of cores that have requested the cluster to remain powered. + +In the PSCI 1.0 specification, this approach is non optimal. If composite +power states are used, the PSCI implementation cannot make global +decisions about state coordination required because it does not understand the +platform specific states. + +The PSCI 1.0 implementation now defines a generic representation of the +power-state parameter : + + typedef struct psci_power_state { + plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + 1]; + } psci_power_state_t; + + +`pwr_domain_state` is an array where each index corresponds to a power level. +Each entry in the array contains the local power state the power domain at +that power level could enter. The meaning of the local power state value is +platform defined, and can vary between levels in a single platform. The PSCI +implementation constraints the values only so that it can classify the state +as RUN, RETENTION or OFF as required by the specification: + +1. Zero means RUN + +2. All OFF state values at all levels must be higher than all + RETENTION state values at all levels + +The platform is required to define the macros `PLAT_MAX_RET_STATE` and +`PLAT_MAX_OFF_STATE` to the framework. The requirement for these macros can +be found in the [Porting Guide]. + +The PSCI 1.0 implementation adds support to involve the platform in state +coordination. This enables the platform to decide the final target state. +During a request to place a power domain in a low power state, the platform +is passed an array of requested `plat_local_state_t` for that power domain by +each core within it through the `plat_get_target_pwr_state()` API. This API +coordinates amongst these requested states to determine a target +`plat_local_state_t` for that power domain. A default weak implementation of +this API is provided in the platform layer which returns the minimum of the +requested local states back to the PSCI state coordination. More details +of `plat_get_target_pwr_state()` API can be found in the +[Porting Guide][get_target_pwr_state]. + +The PSCI Generic implementation expects platform ports to populate the handlers +for the `plat_psci_ops` structure which is declared as : + + typedef struct plat_psci_ops { + void (*cpu_standby)(plat_local_state_t cpu_state); + int (*pwr_domain_on)(u_register_t mpidr); + void (*pwr_domain_off)(const psci_power_state_t *target_state); + void (*pwr_domain_suspend)(const psci_power_state_t *target_state); + void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); + void (*pwr_domain_suspend_finish)( + const psci_power_state_t *target_state); + void (*system_off)(void) __dead2; + void (*system_reset)(void) __dead2; + int (*validate_power_state)(unsigned int power_state, + psci_power_state_t *req_state); + int (*validate_ns_entrypoint)(unsigned long ns_entrypoint); + void (*get_sys_suspend_power_state)( + psci_power_state_t *req_state); + } plat_psci_ops_t; + +The description of these handlers can be found in the [Porting Guide][psci_ops]. +The previous `plat_pm_ops` structure is deprecated. Compared with the previous +handlers, the major differences are: + +* Difference in parameters + +The PSCI 1.0 implementation depends on the `validate_power_state` handler to +convert the power-state parameter (possibly encoding a composite power state) +passed in a PSCI `CPU_SUSPEND` to the `psci_power_state` format. This handler +is now mandatory for PSCI `CPU_SUSPEND` support. + +The `plat_psci_ops` handlers, `pwr_domain_off` and `pwr_domain_suspend`, are +passed the target local state for each affected power domain. The platform +must execute operations specific to these target states. Similarly, +`pwr_domain_on_finish` and `pwr_domain_suspend_finish` are passed the local +states of the affected power domains before wakeup. The platform +must execute actions to restore these power domains from these specific +local states. + +* Difference in invocation + +Whereas the power management handlers in `plat_pm_ops` used to be invoked +for each affinity level till the target affinity level, the new handlers +are only invoked once. The `target_state` encodes the target low power +state or the low power state woken up from for each affected power domain. + +* Difference in semantics + +Although the previous `suspend` handlers could be used for power down as well +as retention at different affinity levels, the new handlers make this support +explicit. The `pwr_domain_suspend` can be used to specify powerdown and +retention at various power domain levels subject to the conditions mentioned +in section 4.2.1 of [PSCI] + +Unlike the previous `standby` handler, the `cpu_standby()` handler is only used +as a fast path for placing a core power domain into a standby or retention +state. + +The below diagram shows the sequence of a PSCI SUSPEND call and the interaction +with the platform layer depicting the exchange of data between PSCI Generic +layer and the platform layer. + +![Image 1](diagrams/psci-suspend-sequence.png?raw=true) + +Refer [plat/arm/board/fvp/fvp_pm.c] for the implementation details of +these handlers for the FVP. The commit 38dce70f51fb83b27958ba3e2ad15f5635cb1061 +demonstrates the migration of ARM reference platforms to the new platform API. + + +2.3 Miscellaneous modifications +------------------------------- + +In addition to the framework changes, unification of warm reset entry points on +wakeup from low power modes has led to a change in the platform API. In the +earlier implementation, the warm reset entry used to be programmed into the +mailboxes by the 'ON' and 'SUSPEND' power management hooks. In the PSCI 1.0 +implementation, this information is not required, because it can figure that +out by querying affinity info state whether to execute the 'suspend_finisher` +or 'on_finisher'. + +As a result, the warm reset entry point must be programmed only once. The +`plat_setup_psci_ops()` API takes the secure entry point as an +additional parameter to enable the platforms to configure their mailbox. The +plat_psci_ops handlers `pwr_domain_on` and `pwr_domain_suspend` no longer take +the warm reset entry point as a parameter. + +Also, some platform APIs which took `MPIDR` as an argument were only ever +invoked to perform actions specific to the caller core which makes the argument +redundant. Therefore the platform APIs `plat_get_my_entrypoint()`, +`plat_is_my_cpu_primary()`, `plat_set_my_stack()` and +`plat_get_my_stack()` are defined which are meant to be invoked only for +operations on the current caller core instead of `platform_get_entrypoint()`, +`platform_is_primary_cpu()`, `platform_set_stack()` and `platform_get_stack()`. + + +3. Compatibility layer +---------------------- + +To ease the migration of the platform ports to the new porting interface, +a compatibility layer is introduced that essentially implements a glue layer +between the old platform API and the new API. The build flag +`ENABLE_PLAT_COMPAT` (enabled by default), specifies whether to enable this +layer or not. A platform port which has migrated to the new API can disable +this flag within the platform specific makefile. + +The compatibility layer works on the assumption that the onus of +state coordination, in case multiple low power states are supported, +is with the platform. The generic PSCI implementation only takes into +account whether the suspend request is power down or not. This corresponds +with the behavior of the PSCI implementation before the introduction of +new frameworks. Also, it assumes that the affinity levels of the platform +correspond directly to the power domain levels. + +The compatibility layer dynamically constructs the new topology +description array by querying the platform using `plat_get_aff_count()` +and `plat_get_aff_state()` APIs. The linear index returned by +`platform_get_core_pos()` is used as the core index for the cores. The +higher level (non-core) power domain nodes must know the cores contained +within its domain. It does so by storing the core index of first core +within it and number of core indexes following it. This means that core +indices returned by `platform_get_core_pos()` for cores within a particular +power domain must be consecutive. We expect that this is the case for most +platform ports including ARM reference platforms. + +The old PSCI helpers like `psci_get_suspend_powerstate()`, +`psci_get_suspend_stateid()`, `psci_get_suspend_stateid_by_mpidr()`, +`psci_get_max_phys_off_afflvl()` and `psci_get_suspend_afflvl()` are also +implemented for the compatibility layer. This allows the existing +platform ports to work with the new PSCI frameworks without significant +rework. + + +4. Deprecated Platform API +--------------------------- + +This section documents the deprecated platform porting API. + +## Common mandatory modifications + +The mandatory macros to be defined by the platform port in `platform_def.h` + +* **#define : PLATFORM_NUM_AFFS** + + Defines the total number of nodes in the affinity hierarchy at all affinity + levels used by the platform. + +* **#define : PLATFORM_MAX_AFFLVL** + + Defines the maximum affinity level that the power management operations + should apply to. ARMv8-A has support for four affinity levels. It is likely + that hardware will implement fewer affinity levels. This macro allows the + PSCI implementation to consider only those affinity levels in the system + that the platform implements. For example, the Base AEM FVP implements two + clusters with a configurable number of cores. It reports the maximum + affinity level as 1, resulting in PSCI power control up to the cluster + level. + +The following functions must be implemented by the platform port to enable +the reset vector code to perform the required tasks. + +### Function : platform_get_entrypoint() [mandatory] + + Argument : unsigned long + Return : unsigned long + +This function is called with the `SCTLR.M` and `SCTLR.C` bits disabled. The core +is identified by its `MPIDR`, which is passed as the argument. The function is +responsible for distinguishing between a warm and cold reset using platform- +specific means. If it is a warm reset, it returns the entrypoint into the +BL3-1 image that the core must jump to. If it is a cold reset, this function +must return zero. + +This function is also responsible for implementing a platform-specific mechanism +to handle the condition where the core has been warm reset but there is no +entrypoint to jump to. + +This function does not follow the Procedure Call Standard used by the +Application Binary Interface for the ARM 64-bit architecture. The caller should +not assume that callee saved registers are preserved across a call to this +function. + +### Function : platform_is_primary_cpu() [mandatory] + + Argument : unsigned long + Return : unsigned int + +This function identifies a core by its `MPIDR`, which is passed as the argument, +to determine whether this core is the primary core or a secondary core. A return +value of zero indicates that the core is not the primary core, while a non-zero +return value indicates that the core is the primary core. + +## Common optional modifications + +### Function : platform_get_core_pos() + + Argument : unsigned long + Return : int + +A platform may need to convert the `MPIDR` of a core to an absolute number, which +can be used as a core-specific linear index into blocks of memory (for example +while allocating per-core stacks). This routine contains a simple mechanism +to perform this conversion, using the assumption that each cluster contains a +maximum of four cores: + + linear index = cpu_id + (cluster_id * 4) + + cpu_id = 8-bit value in MPIDR at affinity level 0 + cluster_id = 8-bit value in MPIDR at affinity level 1 + + +### Function : platform_set_stack() + + Argument : unsigned long + Return : void + +This function sets the current stack pointer to the normal memory stack that +has been allocated for the core specified by MPIDR. For BL images that only +require a stack for the primary core the parameter is ignored. The size of +the stack allocated to each core is specified by the platform defined constant +`PLATFORM_STACK_SIZE`. + +Common implementations of this function for the UP and MP BL images are +provided in [plat/common/aarch64/platform_up_stack.S] and +[plat/common/aarch64/platform_mp_stack.S] + + +### Function : platform_get_stack() + + Argument : unsigned long + Return : unsigned long + +This function returns the base address of the normal memory stack that +has been allocated for the core specificed by MPIDR. For BL images that only +require a stack for the primary core the parameter is ignored. The size of +the stack allocated to each core is specified by the platform defined constant +`PLATFORM_STACK_SIZE`. + +Common implementations of this function for the UP and MP BL images are +provided in [plat/common/aarch64/platform_up_stack.S] and +[plat/common/aarch64/platform_mp_stack.S] + + +## Modifications for Power State Coordination Interface (in BL3-1) + +The following functions must be implemented to initialize PSCI functionality in +the ARM Trusted Firmware. + + +### Function : plat_get_aff_count() [mandatory] + + Argument : unsigned int, unsigned long + Return : unsigned int + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initializations in `bl31_plat_arch_setup()`. It is only +called by the primary core. + +This function is called by the PSCI initialization code to detect the system +topology. Its purpose is to return the number of affinity instances implemented +at a given `affinity level` (specified by the first argument) and a given +`MPIDR` (specified by the second argument). For example, on a dual-cluster +system where first cluster implements two cores and the second cluster +implements four cores, a call to this function with an `MPIDR` corresponding +to the first cluster (`0x0`) and affinity level 0, would return 2. A call +to this function with an `MPIDR` corresponding to the second cluster (`0x100`) +and affinity level 0, would return 4. + + +### Function : plat_get_aff_state() [mandatory] + + Argument : unsigned int, unsigned long + Return : unsigned int + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initializations in `bl31_plat_arch_setup()`. It is only +called by the primary core. + +This function is called by the PSCI initialization code. Its purpose is to +return the state of an affinity instance. The affinity instance is determined by +the affinity ID at a given `affinity level` (specified by the first argument) +and an `MPIDR` (specified by the second argument). The state can be one of +`PSCI_AFF_PRESENT` or `PSCI_AFF_ABSENT`. The latter state is used to cater for +system topologies where certain affinity instances are unimplemented. For +example, consider a platform that implements a single cluster with four cores and +another core implemented directly on the interconnect with the cluster. The +`MPIDR`s of the cluster would range from `0x0-0x3`. The `MPIDR` of the single +core is 0x100 to indicate that it does not belong to cluster 0. Cluster 1 +is missing but needs to be accounted for to reach this single core in the +topology tree. Therefore it is marked as `PSCI_AFF_ABSENT`. + + +### Function : platform_setup_pm() [mandatory] + + Argument : const plat_pm_ops ** + Return : int + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initializations in `bl31_plat_arch_setup()`. It is only +called by the primary core. + +This function is called by PSCI initialization code. Its purpose is to export +handler routines for platform-specific power management actions by populating +the passed pointer with a pointer to the private `plat_pm_ops` structure of +BL3-1. + +A description of each member of this structure is given below. A platform port +is expected to implement these handlers if the corresponding PSCI operation +is to be supported and these handlers are expected to succeed if the return +type is `void`. + +#### plat_pm_ops.affinst_standby() + +Perform the platform-specific setup to enter the standby state indicated by the +passed argument. The generic code expects the handler to succeed. + +#### plat_pm_ops.affinst_on() + +Perform the platform specific setup to power on an affinity instance, specified +by the `MPIDR` (first argument) and `affinity level` (third argument). The +`state` (fourth argument) contains the current state of that affinity instance +(ON or OFF). This is useful to determine whether any action must be taken. For +example, while powering on a core, the cluster that contains this core might +already be in the ON state. The platform decides what actions must be taken to +transition from the current state to the target state (indicated by the power +management operation). The generic code expects the platform to return +E_SUCCESS on success or E_INTERN_FAIL for any failure. + +#### plat_pm_ops.affinst_off() + +Perform the platform specific setup to power off an affinity instance of the +calling core. It is called by the PSCI `CPU_OFF` API implementation. + +The `affinity level` (first argument) and `state` (second argument) have +a similar meaning as described in the `affinst_on()` operation. They +identify the affinity instance on which the call is made and its +current state. This gives the platform port an indication of the +state transition it must make to perform the requested action. For example, if +the calling core is the last powered on core in the cluster, after powering down +affinity level 0 (the core), the platform port should power down affinity +level 1 (the cluster) as well. The generic code expects the handler to succeed. + +#### plat_pm_ops.affinst_suspend() + +Perform the platform specific setup to power off an affinity instance of the +calling core. It is called by the PSCI `CPU_SUSPEND` API and `SYSTEM_SUSPEND` +API implementation + +The `affinity level` (second argument) and `state` (third argument) have a +similar meaning as described in the `affinst_on()` operation. They are used to +identify the affinity instance on which the call is made and its current state. +This gives the platform port an indication of the state transition it must +make to perform the requested action. For example, if the calling core is the +last powered on core in the cluster, after powering down affinity level 0 +(the core), the platform port should power down affinity level 1 (the cluster) +as well. + +The difference between turning an affinity instance off and suspending it +is that in the former case, the affinity instance is expected to re-initialize +its state when it is next powered on (see `affinst_on_finish()`). In the latter +case, the affinity instance is expected to save enough state so that it can +resume execution by restoring this state when it is powered on (see +`affinst_suspend_finish()`).The generic code expects the handler to succeed. + +#### plat_pm_ops.affinst_on_finish() + +This function is called by the PSCI implementation after the calling core is +powered on and released from reset in response to an earlier PSCI `CPU_ON` call. +It performs the platform-specific setup required to initialize enough state for +this core to enter the Normal world and also provide secure runtime firmware +services. + +The `affinity level` (first argument) and `state` (second argument) have a +similar meaning as described in the previous operations. The generic code +expects the handler to succeed. + +#### plat_pm_ops.affinst_suspend_finish() + +This function is called by the PSCI implementation after the calling core is +powered on and released from reset in response to an asynchronous wakeup +event, for example a timer interrupt that was programmed by the core during the +`CPU_SUSPEND` call or `SYSTEM_SUSPEND` call. It performs the platform-specific +setup required to restore the saved state for this core to resume execution +in the Normal world and also provide secure runtime firmware services. + +The `affinity level` (first argument) and `state` (second argument) have a +similar meaning as described in the previous operations. The generic code +expects the platform to succeed. + +#### plat_pm_ops.validate_power_state() + +This function is called by the PSCI implementation during the `CPU_SUSPEND` +call to validate the `power_state` parameter of the PSCI API. If the +`power_state` is known to be invalid, the platform must return +PSCI_E_INVALID_PARAMS as an error, which is propagated back to the Normal +world PSCI client. + +#### plat_pm_ops.validate_ns_entrypoint() + +This function is called by the PSCI implementation during the `CPU_SUSPEND`, +`SYSTEM_SUSPEND` and `CPU_ON` calls to validate the Non-secure `entry_point` +parameter passed by the Normal world. If the `entry_point` is known to be +invalid, the platform must return PSCI_E_INVALID_PARAMS as an error, which is +propagated back to the Normal world PSCI client. + +#### plat_pm_ops.get_sys_suspend_power_state() + +This function is called by the PSCI implementation during the `SYSTEM_SUSPEND` +call to return the `power_state` parameter. This allows the platform to encode +the appropriate State-ID field within the `power_state` parameter which can be +utilized in `affinst_suspend()` to suspend to system affinity level. The +`power_state` parameter should be in the same format as specified by the +PSCI specification for the CPU_SUSPEND API. + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2015, ARM Limited and Contributors. All rights reserved._ + + +[Porting Guide]: porting-guide.md +[Power Domain Topology Design]: psci-pd-tree.md +[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf +[psci pd tree]: psci-pd-tree.md +[my_core_pos]: porting-guide.md#function--plat_my_core_pos +[get_target_pwr_state]: porting-guide.md#function--plat_get_target_pwr_state-optional +[psci_ops]: porting-guide.md#function--plat_setup_psci_ops-mandatory +[plat/arm/board/fvp/fvp_pm.c]: ../plat/arm/board/fvp/fvp_pm.c +[plat/common/aarch64/platform_mp_stack.S]: ../plat/common/aarch64/platform_mp_stack.S +[plat/common/aarch64/platform_up_stack.S]: ../plat/common/aarch64/platform_up_stack.S diff --git a/IPL/SDK/v3m/src/Dummy_BL33/docs/porting-guide.md b/IPL/SDK/v3m/src/Dummy_BL33/docs/porting-guide.md new file mode 100644 index 0000000..50d36ea --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/docs/porting-guide.md @@ -0,0 +1,1680 @@ +ARM Trusted Firmware Porting Guide +================================== + +Contents +-------- + +1. [Introduction](#1--introduction) +2. [Common Modifications](#2--common-modifications) + * [Common mandatory modifications](#21-common-mandatory-modifications) + * [Handling reset](#22-handling-reset) + * [Common mandatory modifications](#23-common-mandatory-modifications) + * [Common optional modifications](#24-common-optional-modifications) +3. [Boot Loader stage specific modifications](#3--modifications-specific-to-a-boot-loader-stage) + * [Boot Loader stage 1 (BL1)](#31-boot-loader-stage-1-bl1) + * [Boot Loader stage 2 (BL2)](#32-boot-loader-stage-2-bl2) + * [Boot Loader stage 3-1 (BL3-1)](#32-boot-loader-stage-3-1-bl3-1) + * [PSCI implementation (in BL3-1)](#33-power-state-coordination-interface-in-bl3-1) + * [Interrupt Management framework (in BL3-1)](#34--interrupt-management-framework-in-bl3-1) + * [Crash Reporting mechanism (in BL3-1)](#35--crash-reporting-mechanism-in-bl3-1) +4. [Build flags](#4--build-flags) +5. [C Library](#5--c-library) +6. [Storage abstraction layer](#6--storage-abstraction-layer) + +- - - - - - - - - - - - - - - - - - + +1. Introduction +---------------- + +Please note that this document has been updated for the new platform API +as required by the PSCI v1.0 implementation. Please refer to the +[Migration Guide] for the previous platform API. + +Porting the ARM Trusted Firmware to a new platform involves making some +mandatory and optional modifications for both the cold and warm boot paths. +Modifications consist of: + +* Implementing a platform-specific function or variable, +* Setting up the execution context in a certain way, or +* Defining certain constants (for example #defines). + +The platform-specific functions and variables are declared in +[include/plat/common/platform.h]. The firmware provides a default implementation +of variables and functions to fulfill the optional requirements. These +implementations are all weakly defined; they are provided to ease the porting +effort. Each platform port can override them with its own implementation if the +default implementation is inadequate. + +Platform ports that want to be aligned with standard ARM platforms (for example +FVP and Juno) may also use [include/plat/arm/common/plat_arm.h] and the +corresponding source files in `plat/arm/common/`. These provide standard +implementations for some of the required platform porting functions. However, +using these functions requires the platform port to implement additional +ARM standard platform porting functions. These additional functions are not +documented here. + +Some modifications are common to all Boot Loader (BL) stages. Section 2 +discusses these in detail. The subsequent sections discuss the remaining +modifications for each BL stage in detail. + +This document should be read in conjunction with the ARM Trusted Firmware +[User Guide]. + + +2. Common modifications +------------------------ + +This section covers the modifications that should be made by the platform for +each BL stage to correctly port the firmware stack. They are categorized as +either mandatory or optional. + + +2.1 Common mandatory modifications +---------------------------------- +A platform port must enable the Memory Management Unit (MMU) with identity +mapped page tables, and enable both the instruction and data caches for each BL +stage. In ARM standard platforms, each BL stage configures the MMU in +the platform-specific architecture setup function, `blX_plat_arch_setup()`. + +If the build option `USE_COHERENT_MEM` is enabled, each platform can allocate a +block of identity mapped secure memory with Device-nGnRE attributes aligned to +page boundary (4K) for each BL stage. All sections which allocate coherent +memory are grouped under `coherent_ram`. For ex: Bakery locks are placed in a +section identified by name `bakery_lock` inside `coherent_ram` so that its +possible for the firmware to place variables in it using the following C code +directive: + + __attribute__ ((section("bakery_lock"))) + +Or alternatively the following assembler code directive: + + .section bakery_lock + +The `coherent_ram` section is a sum of all sections like `bakery_lock` which are +used to allocate any data structures that are accessed both when a CPU is +executing with its MMU and caches enabled, and when it's running with its MMU +and caches disabled. Examples are given below. + +The following variables, functions and constants must be defined by the platform +for the firmware to work correctly. + + +### File : platform_def.h [mandatory] + +Each platform must ensure that a header file of this name is in the system +include path with the following constants defined. This may require updating the +list of `PLAT_INCLUDES` in the `platform.mk` file. In the ARM development +platforms, this file is found in `plat/arm/board//include/`. + +Platform ports may optionally use the file [include/plat/common/common_def.h], +which provides typical values for some of the constants below. These values are +likely to be suitable for all platform ports. + +Platform ports that want to be aligned with standard ARM platforms (for example +FVP and Juno) may also use [include/plat/arm/common/arm_def.h], which provides +standard values for some of the constants below. However, this requires the +platform port to define additional platform porting constants in +`platform_def.h`. These additional constants are not documented here. + +* **#define : PLATFORM_LINKER_FORMAT** + + Defines the linker format used by the platform, for example + `elf64-littleaarch64`. + +* **#define : PLATFORM_LINKER_ARCH** + + Defines the processor architecture for the linker by the platform, for + example `aarch64`. + +* **#define : PLATFORM_STACK_SIZE** + + Defines the normal stack memory available to each CPU. This constant is used + by [plat/common/aarch64/platform_mp_stack.S] and + [plat/common/aarch64/platform_up_stack.S]. + +* **define : CACHE_WRITEBACK_GRANULE** + + Defines the size in bits of the largest cache line across all the cache + levels in the platform. + +* **#define : FIRMWARE_WELCOME_STR** + + Defines the character string printed by BL1 upon entry into the `bl1_main()` + function. + +* **#define : PLATFORM_CORE_COUNT** + + Defines the total number of CPUs implemented by the platform across all + clusters in the system. + +* **#define : PLAT_NUM_PWR_DOMAINS** + + Defines the total number of nodes in the power domain topology + tree at all the power domain levels used by the platform. + This macro is used by the PSCI implementation to allocate + data structures to represent power domain topology. + +* **#define : PLAT_MAX_PWR_LVL** + + Defines the maximum power domain level that the power management operations + should apply to. More often, but not always, the power domain level + corresponds to affinity level. This macro allows the PSCI implementation + to know the highest power domain level that it should consider for power + management operations in the system that the platform implements. For + example, the Base AEM FVP implements two clusters with a configurable + number of CPUs and it reports the maximum power domain level as 1. + +* **#define : PLAT_MAX_OFF_STATE** + + Defines the local power state corresponding to the deepest power down + possible at every power domain level in the platform. The local power + states for each level may be sparsely allocated between 0 and this value + with 0 being reserved for the RUN state. The PSCI implementation uses this + value to initialize the local power states of the power domain nodes and + to specify the requested power state for a PSCI_CPU_OFF call. + +* **#define : PLAT_MAX_RET_STATE** + + Defines the local power state corresponding to the deepest retention state + possible at every power domain level in the platform. This macro should be + a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the + PSCI implementation to distuiguish between retention and power down local + power states within PSCI_CPU_SUSPEND call. + +* **#define : BL1_RO_BASE** + + Defines the base address in secure ROM where BL1 originally lives. Must be + aligned on a page-size boundary. + +* **#define : BL1_RO_LIMIT** + + Defines the maximum address in secure ROM that BL1's actual content (i.e. + excluding any data section allocated at runtime) can occupy. + +* **#define : BL1_RW_BASE** + + Defines the base address in secure RAM where BL1's read-write data will live + at runtime. Must be aligned on a page-size boundary. + +* **#define : BL1_RW_LIMIT** + + Defines the maximum address in secure RAM that BL1's read-write data can + occupy at runtime. + +* **#define : BL2_BASE** + + Defines the base address in secure RAM where BL1 loads the BL2 binary image. + Must be aligned on a page-size boundary. + +* **#define : BL2_LIMIT** + + Defines the maximum address in secure RAM that the BL2 image can occupy. + +* **#define : BL31_BASE** + + Defines the base address in secure RAM where BL2 loads the BL3-1 binary + image. Must be aligned on a page-size boundary. + +* **#define : BL31_LIMIT** + + Defines the maximum address in secure RAM that the BL3-1 image can occupy. + +* **#define : NS_IMAGE_OFFSET** + + Defines the base address in non-secure DRAM where BL2 loads the BL3-3 binary + image. Must be aligned on a page-size boundary. + +For every image, the platform must define individual identifiers that will be +used by BL1 or BL2 to load the corresponding image into memory from non-volatile +storage. For the sake of performance, integer numbers will be used as +identifiers. The platform will use those identifiers to return the relevant +information about the image to be loaded (file handler, load address, +authentication information, etc.). The following image identifiers are +mandatory: + +* **#define : BL2_IMAGE_ID** + + BL2 image identifier, used by BL1 to load BL2. + +* **#define : BL31_IMAGE_ID** + + BL3-1 image identifier, used by BL2 to load BL3-1. + +* **#define : BL33_IMAGE_ID** + + BL3-3 image identifier, used by BL2 to load BL3-3. + +If Trusted Board Boot is enabled, the following certificate identifiers must +also be defined: + +* **#define : BL2_CERT_ID** + + BL2 content certificate identifier, used by BL1 to load the BL2 content + certificate. + +* **#define : TRUSTED_KEY_CERT_ID** + + Trusted key certificate identifier, used by BL2 to load the trusted key + certificate. + +* **#define : BL31_KEY_CERT_ID** + + BL3-1 key certificate identifier, used by BL2 to load the BL3-1 key + certificate. + +* **#define : BL31_CERT_ID** + + BL3-1 content certificate identifier, used by BL2 to load the BL3-1 content + certificate. + +* **#define : BL33_KEY_CERT_ID** + + BL3-3 key certificate identifier, used by BL2 to load the BL3-3 key + certificate. + +* **#define : BL33_CERT_ID** + + BL3-3 content certificate identifier, used by BL2 to load the BL3-3 content + certificate. + +If a BL3-0 image is supported by the platform, the following constants must +also be defined: + +* **#define : BL30_IMAGE_ID** + + BL3-0 image identifier, used by BL2 to load BL3-0 into secure memory from + platform storage before being transfered to the SCP. + +* **#define : BL30_KEY_CERT_ID** + + BL3-0 key certificate identifier, used by BL2 to load the BL3-0 key + certificate (mandatory when Trusted Board Boot is enabled). + +* **#define : BL30_CERT_ID** + + BL3-0 content certificate identifier, used by BL2 to load the BL3-0 content + certificate (mandatory when Trusted Board Boot is enabled). + +If a BL3-2 image is supported by the platform, the following constants must +also be defined: + +* **#define : BL32_IMAGE_ID** + + BL3-2 image identifier, used by BL2 to load BL3-2. + +* **#define : BL32_KEY_CERT_ID** + + BL3-2 key certificate identifier, used by BL2 to load the BL3-2 key + certificate (mandatory when Trusted Board Boot is enabled). + +* **#define : BL32_CERT_ID** + + BL3-2 content certificate identifier, used by BL2 to load the BL3-2 content + certificate (mandatory when Trusted Board Boot is enabled). + +* **#define : BL32_BASE** + + Defines the base address in secure memory where BL2 loads the BL3-2 binary + image. Must be aligned on a page-size boundary. + +* **#define : BL32_LIMIT** + + Defines the maximum address that the BL3-2 image can occupy. + +If the Test Secure-EL1 Payload (TSP) instantiation of BL3-2 is supported by the +platform, the following constants must also be defined: + +* **#define : TSP_SEC_MEM_BASE** + + Defines the base address of the secure memory used by the TSP image on the + platform. This must be at the same address or below `BL32_BASE`. + +* **#define : TSP_SEC_MEM_SIZE** + + Defines the size of the secure memory used by the BL3-2 image on the + platform. `TSP_SEC_MEM_BASE` and `TSP_SEC_MEM_SIZE` must fully accomodate + the memory required by the BL3-2 image, defined by `BL32_BASE` and + `BL32_LIMIT`. + +* **#define : TSP_IRQ_SEC_PHY_TIMER** + + Defines the ID of the secure physical generic timer interrupt used by the + TSP's interrupt handling code. + +If the platform port uses the translation table library code, the following +constant must also be defined: + +* **#define : MAX_XLAT_TABLES** + + Defines the maximum number of translation tables that are allocated by the + translation table library code. To minimize the amount of runtime memory + used, choose the smallest value needed to map the required virtual addresses + for each BL stage. + +If the platform port uses the IO storage framework, the following constants +must also be defined: + +* **#define : MAX_IO_DEVICES** + + Defines the maximum number of registered IO devices. Attempting to register + more devices than this value using `io_register_device()` will fail with + IO_RESOURCES_EXHAUSTED. + +* **#define : MAX_IO_HANDLES** + + Defines the maximum number of open IO handles. Attempting to open more IO + entities than this value using `io_open()` will fail with + IO_RESOURCES_EXHAUSTED. + +If the platform needs to allocate data within the per-cpu data framework in +BL3-1, it should define the following macro. Currently this is only required if +the platform decides not to use the coherent memory section by undefining the +USE_COHERENT_MEM build flag. In this case, the framework allocates the required +memory within the the per-cpu data to minimize wastage. + +* **#define : PLAT_PCPU_DATA_SIZE** + + Defines the memory (in bytes) to be reserved within the per-cpu data + structure for use by the platform layer. + +The following constants are optional. They should be defined when the platform +memory layout implies some image overlaying like in ARM standard platforms. + +* **#define : BL31_PROGBITS_LIMIT** + + Defines the maximum address in secure RAM that the BL3-1's progbits sections + can occupy. + +* **#define : TSP_PROGBITS_LIMIT** + + Defines the maximum address that the TSP's progbits sections can occupy. + +### File : plat_macros.S [mandatory] + +Each platform must ensure a file of this name is in the system include path with +the following macro defined. In the ARM development platforms, this file is +found in `plat/arm/board//include/plat_macros.S`. + +* **Macro : plat_print_gic_regs** + + This macro allows the crash reporting routine to print GIC registers + in case of an unhandled exception in BL3-1. This aids in debugging and + this macro can be defined to be empty in case GIC register reporting is + not desired. + +* **Macro : plat_print_interconnect_regs** + + This macro allows the crash reporting routine to print interconnect + registers in case of an unhandled exception in BL3-1. This aids in debugging + and this macro can be defined to be empty in case interconnect register + reporting is not desired. In ARM standard platforms, the CCI snoop + control registers are reported. + + +2.2 Handling Reset +------------------ + +BL1 by default implements the reset vector where execution starts from a cold +or warm boot. BL3-1 can be optionally set as a reset vector using the +RESET_TO_BL31 make variable. + +For each CPU, the reset vector code is responsible for the following tasks: + +1. Distinguishing between a cold boot and a warm boot. + +2. In the case of a cold boot and the CPU being a secondary CPU, ensuring that + the CPU is placed in a platform-specific state until the primary CPU + performs the necessary steps to remove it from this state. + +3. In the case of a warm boot, ensuring that the CPU jumps to a platform- + specific address in the BL3-1 image in the same processor mode as it was + when released from reset. + +The following functions need to be implemented by the platform port to enable +reset vector code to perform the above tasks. + + +### Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] + + Argument : void + Return : unsigned long + +This function is called with the called with the MMU and caches disabled +(`SCTLR_EL3.M` = 0 and `SCTLR_EL3.C` = 0). The function is responsible for +distinguishing between a warm and cold reset for the current CPU using +platform-specific means. If it's a warm reset, then it returns the warm +reset entrypoint point provided to `plat_setup_psci_ops()` during +BL3-1 initialization. If it's a cold reset then this function must return zero. + +This function does not follow the Procedure Call Standard used by the +Application Binary Interface for the ARM 64-bit architecture. The caller should +not assume that callee saved registers are preserved across a call to this +function. + +This function fulfills requirement 1 and 3 listed above. + +Note that for platforms that support programming the reset address, it is +expected that a CPU will start executing code directly at the right address, +both on a cold and warm reset. In this case, there is no need to identify the +type of reset nor to query the warm reset entrypoint. Therefore, implementing +this function is not required on such platforms. + + +### Function : plat_secondary_cold_boot_setup() [mandatory] + + Argument : void + +This function is called with the MMU and data caches disabled. It is responsible +for placing the executing secondary CPU in a platform-specific state until the +primary CPU performs the necessary actions to bring it out of that state and +allow entry into the OS. This function must not return. + +In the ARM FVP port, each secondary CPU powers itself off. The primary CPU is +responsible for powering up the secondary CPU when normal world software +requires them. + +This function fulfills requirement 2 above. + + +### Function : plat_is_my_cpu_primary() [mandatory] + + Argument : void + Return : unsigned int + +This function identifies whether the current CPU is the primary CPU or a +secondary CPU. A return value of zero indicates that the CPU is not the +primary CPU, while a non-zero return value indicates that the CPU is the +primary CPU. + + +### Function : platform_mem_init() [mandatory] + + Argument : void + Return : void + +This function is called before any access to data is made by the firmware, in +order to carry out any essential memory initialization. + + +### Function: plat_get_rotpk_info() + + Argument : void *, void **, unsigned int *, unsigned int * + Return : int + +This function is mandatory when Trusted Board Boot is enabled. It returns a +pointer to the ROTPK stored in the platform (or a hash of it) and its length. +The ROTPK must be encoded in DER format according to the following ASN.1 +structure: + + AlgorithmIdentifier ::= SEQUENCE { + algorithm OBJECT IDENTIFIER, + parameters ANY DEFINED BY algorithm OPTIONAL + } + + SubjectPublicKeyInfo ::= SEQUENCE { + algorithm AlgorithmIdentifier, + subjectPublicKey BIT STRING + } + +In case the function returns a hash of the key: + + DigestInfo ::= SEQUENCE { + digestAlgorithm AlgorithmIdentifier, + digest OCTET STRING + } + +The function returns 0 on success. Any other value means the ROTPK could not be +retrieved from the platform. The function also reports extra information related +to the ROTPK in the flags parameter. + + +2.3 Common mandatory modifications +--------------------------------- + +The following functions are mandatory functions which need to be implemented +by the platform port. + +### Function : plat_my_core_pos() + + Argument : void + Return : unsigned int + +This funtion returns the index of the calling CPU which is used as a +CPU-specific linear index into blocks of memory (for example while allocating +per-CPU stacks). This function will be invoked very early in the +initialization sequence which mandates that this function should be +implemented in assembly and should not rely on the avalability of a C +runtime environment. + +This function plays a crucial role in the power domain topology framework in +PSCI and details of this can be found in [Power Domain Topology Design]. + +### Function : plat_core_pos_by_mpidr() + + Argument : u_register_t + Return : int + +This function validates the `MPIDR` of a CPU and converts it to an index, +which can be used as a CPU-specific linear index into blocks of memory. In +case the `MPIDR` is invalid, this function returns -1. This function will only +be invoked by BL3-1 after the power domain topology is initialized and can +utilize the C runtime environment. For further details about how ARM Trusted +Firmware represents the power domain topology and how this relates to the +linear CPU index, please refer [Power Domain Topology Design]. + + + +2.4 Common optional modifications +--------------------------------- + +The following are helper functions implemented by the firmware that perform +common platform-specific tasks. A platform may choose to override these +definitions. + +### Function : plat_set_my_stack() + + Argument : void + Return : void + +This function sets the current stack pointer to the normal memory stack that +has been allocated for the current CPU. For BL images that only require a +stack for the primary CPU, the UP version of the function is used. The size +of the stack allocated to each CPU is specified by the platform defined +constant `PLATFORM_STACK_SIZE`. + +Common implementations of this function for the UP and MP BL images are +provided in [plat/common/aarch64/platform_up_stack.S] and +[plat/common/aarch64/platform_mp_stack.S] + + +### Function : plat_get_my_stack() + + Argument : void + Return : unsigned long + +This function returns the base address of the normal memory stack that +has been allocated for the current CPU. For BL images that only require a +stack for the primary CPU, the UP version of the function is used. The size +of the stack allocated to each CPU is specified by the platform defined +constant `PLATFORM_STACK_SIZE`. + +Common implementations of this function for the UP and MP BL images are +provided in [plat/common/aarch64/platform_up_stack.S] and +[plat/common/aarch64/platform_mp_stack.S] + + +### Function : plat_report_exception() + + Argument : unsigned int + Return : void + +A platform may need to report various information about its status when an +exception is taken, for example the current exception level, the CPU security +state (secure/non-secure), the exception type, and so on. This function is +called in the following circumstances: + +* In BL1, whenever an exception is taken. +* In BL2, whenever an exception is taken. + +The default implementation doesn't do anything, to avoid making assumptions +about the way the platform displays its status information. + +This function receives the exception type as its argument. Possible values for +exceptions types are listed in the [include/runtime_svc.h] header file. Note +that these constants are not related to any architectural exception code; they +are just an ARM Trusted Firmware convention. + + +### Function : plat_reset_handler() + + Argument : void + Return : void + +A platform may need to do additional initialization after reset. This function +allows the platform to do the platform specific intializations. Platform +specific errata workarounds could also be implemented here. The api should +preserve the values of callee saved registers x19 to x29. + +The default implementation doesn't do anything. If a platform needs to override +the default implementation, refer to the [Firmware Design] for general +guidelines. + +### Function : plat_disable_acp() + + Argument : void + Return : void + +This api allows a platform to disable the Accelerator Coherency Port (if +present) during a cluster power down sequence. The default weak implementation +doesn't do anything. Since this api is called during the power down sequence, +it has restrictions for stack usage and it can use the registers x0 - x17 as +scratch registers. It should preserve the value in x18 register as it is used +by the caller to store the return address. + + +3. Modifications specific to a Boot Loader stage +------------------------------------------------- + +3.1 Boot Loader Stage 1 (BL1) +----------------------------- + +BL1 implements the reset vector where execution starts from after a cold or +warm boot. For each CPU, BL1 is responsible for the following tasks: + +1. Handling the reset as described in section 2.2 + +2. In the case of a cold boot and the CPU being the primary CPU, ensuring that + only this CPU executes the remaining BL1 code, including loading and passing + control to the BL2 stage. + +3. Loading the BL2 image from non-volatile storage into secure memory at the + address specified by the platform defined constant `BL2_BASE`. + +4. Populating a `meminfo` structure with the following information in memory, + accessible by BL2 immediately upon entry. + + meminfo.total_base = Base address of secure RAM visible to BL2 + meminfo.total_size = Size of secure RAM visible to BL2 + meminfo.free_base = Base address of secure RAM available for + allocation to BL2 + meminfo.free_size = Size of secure RAM available for allocation to BL2 + + BL1 places this `meminfo` structure at the beginning of the free memory + available for its use. Since BL1 cannot allocate memory dynamically at the + moment, its free memory will be available for BL2's use as-is. However, this + means that BL2 must read the `meminfo` structure before it starts using its + free memory (this is discussed in Section 3.2). + + In future releases of the ARM Trusted Firmware it will be possible for + the platform to decide where it wants to place the `meminfo` structure for + BL2. + + BL1 implements the `bl1_init_bl2_mem_layout()` function to populate the + BL2 `meminfo` structure. The platform may override this implementation, for + example if the platform wants to restrict the amount of memory visible to + BL2. Details of how to do this are given below. + +The following functions need to be implemented by the platform port to enable +BL1 to perform the above tasks. + + +### Function : bl1_early_platform_setup() [mandatory] + + Argument : void + Return : void + +This function executes with the MMU and data caches disabled. It is only called +by the primary CPU. + +In ARM standard platforms, this function initializes the console and enables +snoop requests into the primary CPU's cluster. + +### Function : bl1_plat_arch_setup() [mandatory] + + Argument : void + Return : void + +This function performs any platform-specific and architectural setup that the +platform requires. Platform-specific setup might include configuration of +memory controllers and the interconnect. + +In ARM standard platforms, this function enables the MMU. + +This function helps fulfill requirement 2 above. + + +### Function : bl1_platform_setup() [mandatory] + + Argument : void + Return : void + +This function executes with the MMU and data caches enabled. It is responsible +for performing any remaining platform-specific setup that can occur after the +MMU and data cache have been enabled. + +In ARM standard platforms, this function initializes the storage abstraction +layer used to load the next bootloader image. + +This function helps fulfill requirement 3 above. + + +### Function : bl1_plat_sec_mem_layout() [mandatory] + + Argument : void + Return : meminfo * + +This function should only be called on the cold boot path. It executes with the +MMU and data caches enabled. The pointer returned by this function must point to +a `meminfo` structure containing the extents and availability of secure RAM for +the BL1 stage. + + meminfo.total_base = Base address of secure RAM visible to BL1 + meminfo.total_size = Size of secure RAM visible to BL1 + meminfo.free_base = Base address of secure RAM available for allocation + to BL1 + meminfo.free_size = Size of secure RAM available for allocation to BL1 + +This information is used by BL1 to load the BL2 image in secure RAM. BL1 also +populates a similar structure to tell BL2 the extents of memory available for +its own use. + +This function helps fulfill requirement 3 above. + + +### Function : bl1_init_bl2_mem_layout() [optional] + + Argument : meminfo *, meminfo *, unsigned int, unsigned long + Return : void + +BL1 needs to tell the next stage the amount of secure RAM available +for it to use. This information is populated in a `meminfo` +structure. + +Depending upon where BL2 has been loaded in secure RAM (determined by +`BL2_BASE`), BL1 calculates the amount of free memory available for BL2 to use. +BL1 also ensures that its data sections resident in secure RAM are not visible +to BL2. An illustration of how this is done in ARM standard platforms is given +in the **Memory layout on ARM development platforms** section in the +[Firmware Design]. + + +### Function : bl1_plat_set_bl2_ep_info() [mandatory] + + Argument : image_info *, entry_point_info * + Return : void + +This function is called after loading BL2 image and it can be used to overwrite +the entry point set by loader and also set the security state and SPSR which +represents the entry point system state for BL2. + + +3.2 Boot Loader Stage 2 (BL2) +----------------------------- + +The BL2 stage is executed only by the primary CPU, which is determined in BL1 +using the `platform_is_primary_cpu()` function. BL1 passed control to BL2 at +`BL2_BASE`. BL2 executes in Secure EL1 and is responsible for: + +1. (Optional) Loading the BL3-0 binary image (if present) from platform + provided non-volatile storage. To load the BL3-0 image, BL2 makes use of + the `meminfo` returned by the `bl2_plat_get_bl30_meminfo()` function. + The platform also defines the address in memory where BL3-0 is loaded + through the optional constant `BL30_BASE`. BL2 uses this information + to determine if there is enough memory to load the BL3-0 image. + Subsequent handling of the BL3-0 image is platform-specific and is + implemented in the `bl2_plat_handle_bl30()` function. + If `BL30_BASE` is not defined then this step is not performed. + +2. Loading the BL3-1 binary image into secure RAM from non-volatile storage. To + load the BL3-1 image, BL2 makes use of the `meminfo` structure passed to it + by BL1. This structure allows BL2 to calculate how much secure RAM is + available for its use. The platform also defines the address in secure RAM + where BL3-1 is loaded through the constant `BL31_BASE`. BL2 uses this + information to determine if there is enough memory to load the BL3-1 image. + +3. (Optional) Loading the BL3-2 binary image (if present) from platform + provided non-volatile storage. To load the BL3-2 image, BL2 makes use of + the `meminfo` returned by the `bl2_plat_get_bl32_meminfo()` function. + The platform also defines the address in memory where BL3-2 is loaded + through the optional constant `BL32_BASE`. BL2 uses this information + to determine if there is enough memory to load the BL3-2 image. + If `BL32_BASE` is not defined then this and the next step is not performed. + +4. (Optional) Arranging to pass control to the BL3-2 image (if present) that + has been pre-loaded at `BL32_BASE`. BL2 populates an `entry_point_info` + structure in memory provided by the platform with information about how + BL3-1 should pass control to the BL3-2 image. + +5. Loading the normal world BL3-3 binary image into non-secure DRAM from + platform storage and arranging for BL3-1 to pass control to this image. This + address is determined using the `plat_get_ns_image_entrypoint()` function + described below. + +6. BL2 populates an `entry_point_info` structure in memory provided by the + platform with information about how BL3-1 should pass control to the + other BL images. + +The following functions must be implemented by the platform port to enable BL2 +to perform the above tasks. + + +### Function : bl2_early_platform_setup() [mandatory] + + Argument : meminfo * + Return : void + +This function executes with the MMU and data caches disabled. It is only called +by the primary CPU. The arguments to this function is the address of the +`meminfo` structure populated by BL1. + +The platform must copy the contents of the `meminfo` structure into a private +variable as the original memory may be subsequently overwritten by BL2. The +copied structure is made available to all BL2 code through the +`bl2_plat_sec_mem_layout()` function. + +In ARM standard platforms, this function also initializes the storage +abstraction layer used to load further bootloader images. It is necessary to do +this early on platforms with a BL3-0 image, since the later `bl2_platform_setup` +must be done after BL3-0 is loaded. + + +### Function : bl2_plat_arch_setup() [mandatory] + + Argument : void + Return : void + +This function executes with the MMU and data caches disabled. It is only called +by the primary CPU. + +The purpose of this function is to perform any architectural initialization +that varies across platforms, for example enabling the MMU (since the memory +map differs across platforms). + + +### Function : bl2_platform_setup() [mandatory] + + Argument : void + Return : void + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initialization in `bl2_plat_arch_setup()`. It is only +called by the primary CPU. + +The purpose of this function is to perform any platform initialization +specific to BL2. + +In ARM standard platforms, this function performs security setup, including +configuration of the TrustZone controller to allow non-secure masters access +to most of DRAM. Part of DRAM is reserved for secure world use. + + +### Function : bl2_plat_sec_mem_layout() [mandatory] + + Argument : void + Return : meminfo * + +This function should only be called on the cold boot path. It may execute with +the MMU and data caches enabled if the platform port does the necessary +initialization in `bl2_plat_arch_setup()`. It is only called by the primary CPU. + +The purpose of this function is to return a pointer to a `meminfo` structure +populated with the extents of secure RAM available for BL2 to use. See +`bl2_early_platform_setup()` above. + + +### Function : bl2_plat_get_bl30_meminfo() [mandatory] + + Argument : meminfo * + Return : void + +This function is used to get the memory limits where BL2 can load the +BL3-0 image. The meminfo provided by this is used by load_image() to +validate whether the BL3-0 image can be loaded within the given +memory from the given base. + + +### Function : bl2_plat_handle_bl30() [mandatory] + + Argument : image_info * + Return : int + +This function is called after loading BL3-0 image and it is used to perform any +platform-specific actions required to handle the SCP firmware. Typically it +transfers the image into SCP memory using a platform-specific protocol and waits +until SCP executes it and signals to the Application Processor (AP) for BL2 +execution to continue. + +This function returns 0 on success, a negative error code otherwise. + + +### Function : bl2_plat_get_bl31_params() [mandatory] + + Argument : void + Return : bl31_params * + +BL2 platform code needs to return a pointer to a `bl31_params` structure it +will use for passing information to BL3-1. The `bl31_params` structure carries +the following information. + - Header describing the version information for interpreting the bl31_param + structure + - Information about executing the BL3-3 image in the `bl33_ep_info` field + - Information about executing the BL3-2 image in the `bl32_ep_info` field + - Information about the type and extents of BL3-1 image in the + `bl31_image_info` field + - Information about the type and extents of BL3-2 image in the + `bl32_image_info` field + - Information about the type and extents of BL3-3 image in the + `bl33_image_info` field + +The memory pointed by this structure and its sub-structures should be +accessible from BL3-1 initialisation code. BL3-1 might choose to copy the +necessary content, or maintain the structures until BL3-3 is initialised. + + +### Funtion : bl2_plat_get_bl31_ep_info() [mandatory] + + Argument : void + Return : entry_point_info * + +BL2 platform code returns a pointer which is used to populate the entry point +information for BL3-1 entry point. The location pointed by it should be +accessible from BL1 while processing the synchronous exception to run to BL3-1. + +In ARM standard platforms this is allocated inside a bl2_to_bl31_params_mem +structure in BL2 memory. + + +### Function : bl2_plat_set_bl31_ep_info() [mandatory] + + Argument : image_info *, entry_point_info * + Return : void + +This function is called after loading BL3-1 image and it can be used to +overwrite the entry point set by loader and also set the security state +and SPSR which represents the entry point system state for BL3-1. + + +### Function : bl2_plat_set_bl32_ep_info() [mandatory] + + Argument : image_info *, entry_point_info * + Return : void + +This function is called after loading BL3-2 image and it can be used to +overwrite the entry point set by loader and also set the security state +and SPSR which represents the entry point system state for BL3-2. + + +### Function : bl2_plat_set_bl33_ep_info() [mandatory] + + Argument : image_info *, entry_point_info * + Return : void + +This function is called after loading BL3-3 image and it can be used to +overwrite the entry point set by loader and also set the security state +and SPSR which represents the entry point system state for BL3-3. + + +### Function : bl2_plat_get_bl32_meminfo() [mandatory] + + Argument : meminfo * + Return : void + +This function is used to get the memory limits where BL2 can load the +BL3-2 image. The meminfo provided by this is used by load_image() to +validate whether the BL3-2 image can be loaded with in the given +memory from the given base. + +### Function : bl2_plat_get_bl33_meminfo() [mandatory] + + Argument : meminfo * + Return : void + +This function is used to get the memory limits where BL2 can load the +BL3-3 image. The meminfo provided by this is used by load_image() to +validate whether the BL3-3 image can be loaded with in the given +memory from the given base. + +### Function : bl2_plat_flush_bl31_params() [mandatory] + + Argument : void + Return : void + +Once BL2 has populated all the structures that needs to be read by BL1 +and BL3-1 including the bl31_params structures and its sub-structures, +the bl31_ep_info structure and any platform specific data. It flushes +all these data to the main memory so that it is available when we jump to +later Bootloader stages with MMU off + +### Function : plat_get_ns_image_entrypoint() [mandatory] + + Argument : void + Return : unsigned long + +As previously described, BL2 is responsible for arranging for control to be +passed to a normal world BL image through BL3-1. This function returns the +entrypoint of that image, which BL3-1 uses to jump to it. + +BL2 is responsible for loading the normal world BL3-3 image (e.g. UEFI). + + +3.2 Boot Loader Stage 3-1 (BL3-1) +--------------------------------- + +During cold boot, the BL3-1 stage is executed only by the primary CPU. This is +determined in BL1 using the `platform_is_primary_cpu()` function. BL1 passes +control to BL3-1 at `BL31_BASE`. During warm boot, BL3-1 is executed by all +CPUs. BL3-1 executes at EL3 and is responsible for: + +1. Re-initializing all architectural and platform state. Although BL1 performs + some of this initialization, BL3-1 remains resident in EL3 and must ensure + that EL3 architectural and platform state is completely initialized. It + should make no assumptions about the system state when it receives control. + +2. Passing control to a normal world BL image, pre-loaded at a platform- + specific address by BL2. BL3-1 uses the `entry_point_info` structure that BL2 + populated in memory to do this. + +3. Providing runtime firmware services. Currently, BL3-1 only implements a + subset of the Power State Coordination Interface (PSCI) API as a runtime + service. See Section 3.3 below for details of porting the PSCI + implementation. + +4. Optionally passing control to the BL3-2 image, pre-loaded at a platform- + specific address by BL2. BL3-1 exports a set of apis that allow runtime + services to specify the security state in which the next image should be + executed and run the corresponding image. BL3-1 uses the `entry_point_info` + structure populated by BL2 to do this. + +If BL3-1 is a reset vector, It also needs to handle the reset as specified in +section 2.2 before the tasks described above. + +The following functions must be implemented by the platform port to enable BL3-1 +to perform the above tasks. + + +### Function : bl31_early_platform_setup() [mandatory] + + Argument : bl31_params *, void * + Return : void + +This function executes with the MMU and data caches disabled. It is only called +by the primary CPU. The arguments to this function are: + +* The address of the `bl31_params` structure populated by BL2. +* An opaque pointer that the platform may use as needed. + +The platform can copy the contents of the `bl31_params` structure and its +sub-structures into private variables if the original memory may be +subsequently overwritten by BL3-1 and similarly the `void *` pointing +to the platform data also needs to be saved. + +In ARM standard platforms, BL2 passes a pointer to a `bl31_params` structure +in BL2 memory. BL3-1 copies the information in this pointer to internal data +structures. + + +### Function : bl31_plat_arch_setup() [mandatory] + + Argument : void + Return : void + +This function executes with the MMU and data caches disabled. It is only called +by the primary CPU. + +The purpose of this function is to perform any architectural initialization +that varies across platforms, for example enabling the MMU (since the memory +map differs across platforms). + + +### Function : bl31_platform_setup() [mandatory] + + Argument : void + Return : void + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initialization in `bl31_plat_arch_setup()`. It is only +called by the primary CPU. + +The purpose of this function is to complete platform initialization so that both +BL3-1 runtime services and normal world software can function correctly. + +In ARM standard platforms, this function does the following: +* Initializes the generic interrupt controller. +* Enables system-level implementation of the generic timer counter. +* Grants access to the system counter timer module +* Initializes the power controller device +* Detects the system topology. + + +### Function : bl31_get_next_image_info() [mandatory] + + Argument : unsigned int + Return : entry_point_info * + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initializations in `bl31_plat_arch_setup()`. + +This function is called by `bl31_main()` to retrieve information provided by +BL2 for the next image in the security state specified by the argument. BL3-1 +uses this information to pass control to that image in the specified security +state. This function must return a pointer to the `entry_point_info` structure +(that was copied during `bl31_early_platform_setup()`) if the image exists. It +should return NULL otherwise. + +### Function : plat_get_syscnt_freq() [mandatory] + + Argument : void + Return : uint64_t + +This function is used by the architecture setup code to retrieve the counter +frequency for the CPU's generic timer. This value will be programmed into the +`CNTFRQ_EL0` register. In ARM standard platforms, it returns the base frequency +of the system counter, which is retrieved from the first entry in the frequency +modes table. + + +### #define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] + + When `USE_COHERENT_MEM = 0`, this constant defines the total memory (in + bytes) aligned to the cache line boundary that should be allocated per-cpu to + accommodate all the bakery locks. + + If this constant is not defined when `USE_COHERENT_MEM = 0`, the linker + calculates the size of the `bakery_lock` input section, aligns it to the + nearest `CACHE_WRITEBACK_GRANULE`, multiplies it with `PLATFORM_CORE_COUNT` + and stores the result in a linker symbol. This constant prevents a platform + from relying on the linker and provide a more efficient mechanism for + accessing per-cpu bakery lock information. + + If this constant is defined and its value is not equal to the value + calculated by the linker then a link time assertion is raised. A compile time + assertion is raised if the value of the constant is not aligned to the cache + line boundary. + +3.3 Power State Coordination Interface (in BL3-1) +------------------------------------------------ + +The ARM Trusted Firmware's implementation of the PSCI API is based around the +concept of a _power domain_. A _power domain_ is a CPU or a logical group of +CPUs which share some state on which power management operations can be +performed as specified by [PSCI]. Each CPU in the system is assigned a cpu +index which is a unique number between `0` and `PLATFORM_CORE_COUNT - 1`. +The _power domains_ are arranged in a hierarchial tree structure and +each _power domain_ can be identified in a system by the cpu index of any CPU +that is part of that domain and a _power domain level_. A processing element +(for example, a CPU) is at level 0. If the _power domain_ node above a CPU is +a logical grouping of CPUs that share some state, then level 1 is that group +of CPUs (for example, a cluster), and level 2 is a group of clusters +(for example, the system). More details on the power domain topology and its +organization can be found in [Power Domain Topology Design]. + +BL3-1's platform initialization code exports a pointer to the platform-specific +power management operations required for the PSCI implementation to function +correctly. This information is populated in the `plat_psci_ops` structure. The +PSCI implementation calls members of the `plat_psci_ops` structure for performing +power management operations on the power domains. For example, the target +CPU is specified by its `MPIDR` in a PSCI `CPU_ON` call. The `pwr_domain_on()` +handler (if present) is called for the CPU power domain. + +The `power-state` parameter of a PSCI `CPU_SUSPEND` call can be used to +describe composite power states specific to a platform. The PSCI implementation +defines a generic representation of the power-state parameter viz which is an +array of local power states where each index corresponds to a power domain +level. Each entry contains the local power state the power domain at that power +level could enter. It depends on the `validate_power_state()` handler to +convert the power-state parameter (possibly encoding a composite power state) +passed in a PSCI `CPU_SUSPEND` call to this representation. + +The following functions must be implemented to initialize PSCI functionality in +the ARM Trusted Firmware. + + +### Function : plat_get_target_pwr_state() [optional] + + Argument : unsigned int, const plat_local_state_t *, unsigned int + Return : plat_local_state_t + +The PSCI generic code uses this function to let the platform participate in +state coordination during a power management operation. The function is passed +a pointer to an array of platform specific local power state `states` (second +argument) which contains the requested power state for each CPU at a particular +power domain level `lvl` (first argument) within the power domain. The function +is expected to traverse this array of upto `ncpus` (third argument) and return +a coordinated target power state by the comparing all the requested power +states. The target power state should not be deeper than any of the requested +power states. + +A weak definition of this API is provided by default wherein it assumes +that the platform assigns a local state value in order of increasing depth +of the power state i.e. for two power states X & Y, if X < Y +then X represents a shallower power state than Y. As a result, the +coordinated target local power state for a power domain will be the minimum +of the requested local power state values. + + +### Function : plat_get_power_domain_tree_desc() [mandatory] + + Argument : void + Return : const unsigned char * + +This function returns a pointer to the byte array containing the power domain +topology tree description. The format and method to construct this array are +described in [Power Domain Topology Design]. The BL3-1 PSCI initilization code +requires this array to be described by the platform, either statically or +dynamically, to initialize the power domain topology tree. In case the array +is populated dynamically, then plat_core_pos_by_mpidr() and +plat_my_core_pos() should also be implemented suitably so that the topology +tree description matches the CPU indices returned by these APIs. These APIs +together form the platform interface for the PSCI topology framework. + + +## Function : plat_setup_psci_ops() [mandatory] + + Argument : uintptr_t, const plat_psci_ops ** + Return : int + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initializations in `bl31_plat_arch_setup()`. It is only +called by the primary CPU. + +This function is called by PSCI initialization code. Its purpose is to let +the platform layer know about the warm boot entrypoint through the +`sec_entrypoint` (first argument) and to export handler routines for +platform-specific psci power management actions by populating the passed +pointer with a pointer to BL3-1's private `plat_psci_ops` structure. + +A description of each member of this structure is given below. Please refer to +the ARM FVP specific implementation of these handlers in +[plat/arm/board/fvp/fvp_pm.c] as an example. For each PSCI function that the +platform wants to support, the associated operation or operations in this +structure must be provided and implemented (Refer section 4 of +[Firmware Design] for the PSCI API supported in Trusted Firmware). To disable +a PSCI function in a platform port, the operation should be removed from this +structure instead of providing an empty implementation. + +#### plat_psci_ops.cpu_standby() + +Perform the platform-specific actions to enter the standby state for a cpu +indicated by the passed argument. This provides a fast path for CPU standby +wherein overheads of PSCI state management and lock acquistion is avoided. +For this handler to be invoked by the PSCI `CPU_SUSPEND` API implementation, +the suspend state type specified in the `power-state` parameter should be +STANDBY and the target power domain level specified should be the CPU. The +handler should put the CPU into a low power retention state (usually by +issuing a wfi instruction) and ensure that it can be woken up from that +state by a normal interrupt. The generic code expects the handler to succeed. + +#### plat_psci_ops.pwr_domain_on() + +Perform the platform specific actions to power on a CPU, specified +by the `MPIDR` (first argument). The generic code expects the platform to +return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. + +#### plat_psci_ops.pwr_domain_off() + +Perform the platform specific actions to prepare to power off the calling CPU +and its higher parent power domain levels as indicated by the `target_state` +(first argument). It is called by the PSCI `CPU_OFF` API implementation. + +The `target_state` encodes the platform coordinated target local power states +for the CPU power domain and its parent power domain levels. The handler +needs to perform power management operation corresponding to the local state +at each power level. + +For this handler, the local power state for the CPU power domain will be a +power down state where as it could be either power down, retention or run state +for the higher power domain levels depending on the result of state +coordination. The generic code expects the handler to succeed. + +#### plat_psci_ops.pwr_domain_suspend() + +Perform the platform specific actions to prepare to suspend the calling +CPU and its higher parent power domain levels as indicated by the +`target_state` (first argument). It is called by the PSCI `CPU_SUSPEND` +API implementation. + +The `target_state` has a similar meaning as described in +the `pwr_domain_off()` operation. It encodes the platform coordinated +target local power states for the CPU power domain and its parent +power domain levels. The handler needs to perform power management operation +corresponding to the local state at each power level. The generic code +expects the handler to succeed. + +The difference between turning a power domain off versus suspending it +is that in the former case, the power domain is expected to re-initialize +its state when it is next powered on (see `pwr_domain_on_finish()`). In the +latter case, the power domain is expected to save enough state so that it can +resume execution by restoring this state when its powered on (see +`pwr_domain_suspend_finish()`). + +#### plat_psci_ops.pwr_domain_on_finish() + +This function is called by the PSCI implementation after the calling CPU is +powered on and released from reset in response to an earlier PSCI `CPU_ON` call. +It performs the platform-specific setup required to initialize enough state for +this CPU to enter the normal world and also provide secure runtime firmware +services. + +The `target_state` (first argument) is the prior state of the power domains +immediately before the CPU was turned on. It indicates which power domains +above the CPU might require initialization due to having previously been in +low power states. The generic code expects the handler to succeed. + +#### plat_psci_ops.pwr_domain_suspend_finish() + +This function is called by the PSCI implementation after the calling CPU is +powered on and released from reset in response to an asynchronous wakeup +event, for example a timer interrupt that was programmed by the CPU during the +`CPU_SUSPEND` call or `SYSTEM_SUSPEND` call. It performs the platform-specific +setup required to restore the saved state for this CPU to resume execution +in the normal world and also provide secure runtime firmware services. + +The `target_state` (first argument) has a similar meaning as described in +the `pwr_domain_on_finish()` operation. The generic code expects the platform +to succeed. + +#### plat_psci_ops.validate_power_state() + +This function is called by the PSCI implementation during the `CPU_SUSPEND` +call to validate the `power_state` parameter of the PSCI API and if valid, +populate it in `req_state` (second argument) array as power domain level +specific local states. If the `power_state` is invalid, the platform must +return PSCI_E_INVALID_PARAMS as error, which is propagated back to the +normal world PSCI client. + +#### plat_psci_ops.validate_ns_entrypoint() + +This function is called by the PSCI implementation during the `CPU_SUSPEND`, +`SYSTEM_SUSPEND` and `CPU_ON` calls to validate the non-secure `entry_point` +parameter passed by the normal world. If the `entry_point` is invalid, +the platform must return PSCI_E_INVALID_ADDRESS as error, which is +propagated back to the normal world PSCI client. + +#### plat_psci_ops.get_sys_suspend_power_state() + +This function is called by the PSCI implementation during the `SYSTEM_SUSPEND` +call to get the `req_state` parameter from platform which encodes the power +domain level specific local states to suspend to system affinity level. The +`req_state` will be utilized to do the PSCI state coordination and +`pwr_domain_suspend()` will be invoked with the coordinated target state to +enter system suspend. + + +3.4 Interrupt Management framework (in BL3-1) +---------------------------------------------- +BL3-1 implements an Interrupt Management Framework (IMF) to manage interrupts +generated in either security state and targeted to EL1 or EL2 in the non-secure +state or EL3/S-EL1 in the secure state. The design of this framework is +described in the [IMF Design Guide] + +A platform should export the following APIs to support the IMF. The following +text briefly describes each api and its implementation in ARM standard +platforms. The API implementation depends upon the type of interrupt controller +present in the platform. ARM standard platforms implements an ARM Generic +Interrupt Controller (ARM GIC) as per the version 2.0 of the +[ARM GIC Architecture Specification]. + +### Function : plat_interrupt_type_to_line() [mandatory] + + Argument : uint32_t, uint32_t + Return : uint32_t + +The ARM processor signals an interrupt exception either through the IRQ or FIQ +interrupt line. The specific line that is signaled depends on how the interrupt +controller (IC) reports different interrupt types from an execution context in +either security state. The IMF uses this API to determine which interrupt line +the platform IC uses to signal each type of interrupt supported by the framework +from a given security state. + +The first parameter will be one of the `INTR_TYPE_*` values (see [IMF Design +Guide]) indicating the target type of the interrupt, the second parameter is the +security state of the originating execution context. The return result is the +bit position in the `SCR_EL3` register of the respective interrupt trap: IRQ=1, +FIQ=2. + +ARM standard platforms configure the ARM GIC to signal S-EL1 interrupts +as FIQs and Non-secure interrupts as IRQs from either security state. + + +### Function : plat_ic_get_pending_interrupt_type() [mandatory] + + Argument : void + Return : uint32_t + +This API returns the type of the highest priority pending interrupt at the +platform IC. The IMF uses the interrupt type to retrieve the corresponding +handler function. `INTR_TYPE_INVAL` is returned when there is no interrupt +pending. The valid interrupt types that can be returned are `INTR_TYPE_EL3`, +`INTR_TYPE_S_EL1` and `INTR_TYPE_NS`. + +ARM standard platforms read the _Highest Priority Pending Interrupt +Register_ (`GICC_HPPIR`) to determine the id of the pending interrupt. The type +of interrupt depends upon the id value as follows. + +1. id < 1022 is reported as a S-EL1 interrupt +2. id = 1022 is reported as a Non-secure interrupt. +3. id = 1023 is reported as an invalid interrupt type. + + +### Function : plat_ic_get_pending_interrupt_id() [mandatory] + + Argument : void + Return : uint32_t + +This API returns the id of the highest priority pending interrupt at the +platform IC. The IMF passes the id returned by this API to the registered +handler for the pending interrupt if the `IMF_READ_INTERRUPT_ID` build time flag +is set. INTR_ID_UNAVAILABLE is returned when there is no interrupt pending. + +ARM standard platforms read the _Highest Priority Pending Interrupt +Register_ (`GICC_HPPIR`) to determine the id of the pending interrupt. The id +that is returned by API depends upon the value of the id read from the interrupt +controller as follows. + +1. id < 1022. id is returned as is. +2. id = 1022. The _Aliased Highest Priority Pending Interrupt Register_ + (`GICC_AHPPIR`) is read to determine the id of the non-secure interrupt. This + id is returned by the API. +3. id = 1023. `INTR_ID_UNAVAILABLE` is returned. + + +### Function : plat_ic_acknowledge_interrupt() [mandatory] + + Argument : void + Return : uint32_t + +This API is used by the CPU to indicate to the platform IC that processing of +the highest pending interrupt has begun. It should return the id of the +interrupt which is being processed. + +This function in ARM standard platforms reads the _Interrupt Acknowledge +Register_ (`GICC_IAR`). This changes the state of the highest priority pending +interrupt from pending to active in the interrupt controller. It returns the +value read from the `GICC_IAR`. This value is the id of the interrupt whose +state has been changed. + +The TSP uses this API to start processing of the secure physical timer +interrupt. + + +### Function : plat_ic_end_of_interrupt() [mandatory] + + Argument : uint32_t + Return : void + +This API is used by the CPU to indicate to the platform IC that processing of +the interrupt corresponding to the id (passed as the parameter) has +finished. The id should be the same as the id returned by the +`plat_ic_acknowledge_interrupt()` API. + +ARM standard platforms write the id to the _End of Interrupt Register_ +(`GICC_EOIR`). This deactivates the corresponding interrupt in the interrupt +controller. + +The TSP uses this API to finish processing of the secure physical timer +interrupt. + + +### Function : plat_ic_get_interrupt_type() [mandatory] + + Argument : uint32_t + Return : uint32_t + +This API returns the type of the interrupt id passed as the parameter. +`INTR_TYPE_INVAL` is returned if the id is invalid. If the id is valid, a valid +interrupt type (one of `INTR_TYPE_EL3`, `INTR_TYPE_S_EL1` and `INTR_TYPE_NS`) is +returned depending upon how the interrupt has been configured by the platform +IC. + +This function in ARM standard platforms configures S-EL1 interrupts +as Group0 interrupts and Non-secure interrupts as Group1 interrupts. It reads +the group value corresponding to the interrupt id from the relevant _Interrupt +Group Register_ (`GICD_IGROUPRn`). It uses the group value to determine the +type of interrupt. + + +3.5 Crash Reporting mechanism (in BL3-1) +---------------------------------------------- +BL3-1 implements a crash reporting mechanism which prints the various registers +of the CPU to enable quick crash analysis and debugging. It requires that a +console is designated as the crash console by the platform which will be used to +print the register dump. + +The following functions must be implemented by the platform if it wants crash +reporting mechanism in BL3-1. The functions are implemented in assembly so that +they can be invoked without a C Runtime stack. + +### Function : plat_crash_console_init + + Argument : void + Return : int + +This API is used by the crash reporting mechanism to initialize the crash +console. It should only use the general purpose registers x0 to x2 to do the +initialization and returns 1 on success. + +### Function : plat_crash_console_putc + + Argument : int + Return : int + +This API is used by the crash reporting mechanism to print a character on the +designated crash console. It should only use general purpose registers x1 and +x2 to do its work. The parameter and the return value are in general purpose +register x0. + +4. Build flags +--------------- + +* **ENABLE_PLAT_COMPAT** + All the platforms ports conforming to this API specification should define + the build flag `ENABLE_PLAT_COMPAT` to 0 as the compatibility layer should + be disabled. For more details on compatibility layer, refer + [Migration Guide]. + +There are some build flags which can be defined by the platform to control +inclusion or exclusion of certain BL stages from the FIP image. These flags +need to be defined in the platform makefile which will get included by the +build system. + +* **NEED_BL30** + This flag if defined by the platform mandates that a BL3-0 binary should + be included in the FIP image. The path to the BL3-0 binary can be specified + by the `BL30` build option (see build options in the [User Guide]). + +* **NEED_BL33** + By default, this flag is defined `yes` by the build system and `BL33` + build option should be supplied as a build option. The platform has the option + of excluding the BL3-3 image in the `fip` image by defining this flag to + `no`. + +5. C Library +------------- + +To avoid subtle toolchain behavioral dependencies, the header files provided +by the compiler are not used. The software is built with the `-nostdinc` flag +to ensure no headers are included from the toolchain inadvertently. Instead the +required headers are included in the ARM Trusted Firmware source tree. The +library only contains those C library definitions required by the local +implementation. If more functionality is required, the needed library functions +will need to be added to the local implementation. + +Versions of [FreeBSD] headers can be found in `include/stdlib`. Some of these +headers have been cut down in order to simplify the implementation. In order to +minimize changes to the header files, the [FreeBSD] layout has been maintained. +The generic C library definitions can be found in `include/stdlib` with more +system and machine specific declarations in `include/stdlib/sys` and +`include/stdlib/machine`. + +The local C library implementations can be found in `lib/stdlib`. In order to +extend the C library these files may need to be modified. It is recommended to +use a release version of [FreeBSD] as a starting point. + +The C library header files in the [FreeBSD] source tree are located in the +`include` and `sys/sys` directories. [FreeBSD] machine specific definitions +can be found in the `sys/` directories. These files define things +like 'the size of a pointer' and 'the range of an integer'. Since an AArch64 +port for [FreeBSD] does not yet exist, the machine specific definitions are +based on existing machine types with similar properties (for example SPARC64). + +Where possible, C library function implementations were taken from [FreeBSD] +as found in the `lib/libc` directory. + +A copy of the [FreeBSD] sources can be downloaded with `git`. + + git clone git://github.com/freebsd/freebsd.git -b origin/release/9.2.0 + + +6. Storage abstraction layer +----------------------------- + +In order to improve platform independence and portability an storage abstraction +layer is used to load data from non-volatile platform storage. + +Each platform should register devices and their drivers via the Storage layer. +These drivers then need to be initialized by bootloader phases as +required in their respective `blx_platform_setup()` functions. Currently +storage access is only required by BL1 and BL2 phases. The `load_image()` +function uses the storage layer to access non-volatile platform storage. + +It is mandatory to implement at least one storage driver. For the ARM +development platforms the Firmware Image Package (FIP) driver is provided as +the default means to load data from storage (see the "Firmware Image Package" +section in the [User Guide]). The storage layer is described in the header file +`include/drivers/io/io_storage.h`. The implementation of the common library +is in `drivers/io/io_storage.c` and the driver files are located in +`drivers/io/`. + +Each IO driver must provide `io_dev_*` structures, as described in +`drivers/io/io_driver.h`. These are returned via a mandatory registration +function that is called on platform initialization. The semi-hosting driver +implementation in `io_semihosting.c` can be used as an example. + +The Storage layer provides mechanisms to initialize storage devices before +IO operations are called. The basic operations supported by the layer +include `open()`, `close()`, `read()`, `write()`, `size()` and `seek()`. +Drivers do not have to implement all operations, but each platform must +provide at least one driver for a device capable of supporting generic +operations such as loading a bootloader image. + +The current implementation only allows for known images to be loaded by the +firmware. These images are specified by using their identifiers, as defined in +[include/plat/common/platform_def.h] (or a separate header file included from +there). The platform layer (`plat_get_image_source()`) then returns a reference +to a device and a driver-specific `spec` which will be understood by the driver +to allow access to the image data. + +The layer is designed in such a way that is it possible to chain drivers with +other drivers. For example, file-system drivers may be implemented on top of +physical block devices, both represented by IO devices with corresponding +drivers. In such a case, the file-system "binding" with the block device may +be deferred until the file-system device is initialised. + +The abstraction currently depends on structures being statically allocated +by the drivers and callers, as the system does not yet provide a means of +dynamically allocating memory. This may also have the affect of limiting the +amount of open resources per driver. + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved._ + + +[ARM GIC Architecture Specification]: http://arminfo.emea.arm.com/help/topic/com.arm.doc.ihi0048b/IHI0048B_gic_architecture_specification.pdf +[IMF Design Guide]: interrupt-framework-design.md +[User Guide]: user-guide.md +[FreeBSD]: http://www.freebsd.org +[Firmware Design]: firmware-design.md +[Power Domain Topology Design]: psci-pd-tree.md +[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf +[Migration Guide]: platform-migration-guide.md + +[plat/common/aarch64/platform_mp_stack.S]: ../plat/common/aarch64/platform_mp_stack.S +[plat/common/aarch64/platform_up_stack.S]: ../plat/common/aarch64/platform_up_stack.S +[plat/arm/board/fvp/fvp_pm.c]: ../plat/arm/board/fvp/fvp_pm.c +[include/runtime_svc.h]: ../include/runtime_svc.h +[include/plat/arm/common/arm_def.h]: ../include/plat/arm/common/arm_def.h +[include/plat/common/common_def.h]: ../include/plat/common/common_def.h +[include/plat/common/platform.h]: ../include/plat/common/platform.h +[include/plat/arm/common/plat_arm.h]: ../include/plat/arm/common/plat_arm.h] diff --git a/IPL/SDK/v3m/src/Dummy_BL33/docs/psci-pd-tree.md b/IPL/SDK/v3m/src/Dummy_BL33/docs/psci-pd-tree.md new file mode 100644 index 0000000..6ae686d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/docs/psci-pd-tree.md @@ -0,0 +1,295 @@ +------------ +Requirements +------------ + +1. A platform must export the `plat_get_aff_count()` and + `plat_get_aff_state()` APIs to enable the generic PSCI code to + populate a tree that describes the hierarchy of power domains in the + system. This approach is inflexible because a change to the topology + requires a change in the code. + + It would be much simpler for the platform to describe its power domain tree + in a data structure. + +2. The generic PSCI code generates MPIDRs in order to populate the power domain + tree. It also uses an MPIDR to find a node in the tree. The assumption that + a platform will use exactly the same MPIDRs as generated by the generic PSCI + code is not scalable. The use of an MPIDR also restricts the number of + levels in the power domain tree to four. + + Therefore, there is a need to decouple allocation of MPIDRs from the + mechanism used to populate the power domain topology tree. + +3. The current arrangement of the power domain tree requires a binary search + over the sibling nodes at a particular level to find a specified power + domain node. During a power management operation, the tree is traversed from + a 'start' to an 'end' power level. The binary search is required to find the + node at each level. The natural way to perform this traversal is to + start from a leaf node and follow the parent node pointer to reach the end + level. + + Therefore, there is a need to define data structures that implement the tree in + a way which facilitates such a traversal. + +4. The attributes of a core power domain differ from the attributes of power + domains at higher levels. For example, only a core power domain can be identified + using an MPIDR. There is no requirement to perform state coordination while + performing a power management operation on the core power domain. + + Therefore, there is a need to implement the tree in a way which facilitates this + distinction between a leaf and non-leaf node and any associated + optimizations. + + +------ +Design +------ + +### Describing a power domain tree + +To fulfill requirement 1., the existing platform APIs +`plat_get_aff_count()` and `plat_get_aff_state()` have been +removed. A platform must define an array of unsigned chars such that: + +1. The first entry in the array specifies the number of power domains at the + highest power level implemented in the platform. This caters for platforms + where the power domain tree does not have a single root node, for example, + the FVP has two cluster power domains at the highest level (1). + +2. Each subsequent entry corresponds to a power domain and contains the number + of power domains that are its direct children. + +3. The size of the array minus the first entry will be equal to the number of + non-leaf power domains. + +4. The value in each entry in the array is used to find the number of entries + to consider at the next level. The sum of the values (number of children) of + all the entries at a level specifies the number of entries in the array for + the next level. + +The following example power domain topology tree will be used to describe the +above text further. The leaf and non-leaf nodes in this tree have been numbered +separately. + +``` + +-+ + |0| + +-+ + / \ + / \ + / \ + / \ + / \ + / \ + / \ + / \ + / \ + / \ + +-+ +-+ + |1| |2| + +-+ +-+ + / \ / \ + / \ / \ + / \ / \ + / \ / \ + +-+ +-+ +-+ +-+ + |3| |4| |5| |6| + +-+ +-+ +-+ +-+ + +---+-----+ +----+----| +----+----+ +----+-----+-----+ + | | | | | | | | | | | | | + | | | | | | | | | | | | | + v v v v v v v v v v v v v + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +--+ +--+ +--+ + |0| |1| |2| |3| |4| |5| |6| |7| |8| |9| |10| |11| |12| + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +--+ +--+ +--+ +``` + + +This tree is defined by the platform as the array described above as follows: + +``` + #define PLAT_NUM_POWER_DOMAINS 20 + #define PLATFORM_CORE_COUNT 13 + #define PSCI_NUM_NON_CPU_PWR_DOMAINS \ + (PLAT_NUM_POWER_DOMAINS - PLATFORM_CORE_COUNT) + + unsigned char plat_power_domain_tree_desc[] = { 1, 2, 2, 2, 3, 3, 3, 4}; +``` + +### Removing assumptions about MPIDRs used in a platform + +To fulfill requirement 2., it is assumed that the platform assigns a +unique number (core index) between `0` and `PLAT_CORE_COUNT - 1` to each core +power domain. MPIDRs could be allocated in any manner and will not be used to +populate the tree. + +`plat_core_pos_by_mpidr(mpidr)` will return the core index for the core +corresponding to the MPIDR. It will return an error (-1) if an MPIDR is passed +which is not allocated or corresponds to an absent core. The semantics of this +platform API have changed since it is required to validate the passed MPIDR. It +has been made a mandatory API as a result. + +Another mandatory API, `plat_my_core_pos()` has been added to return the core +index for the calling core. This API provides a more lightweight mechanism to get +the index since there is no need to validate the MPIDR of the calling core. + +The platform should assign the core indices (as illustrated in the diagram above) +such that, if the core nodes are numbered from left to right, then the index +for a core domain will be the same as the index returned by + `plat_core_pos_by_mpidr()` or `plat_my_core_pos()` for that core. This +relationship allows the core nodes to be allocated in a separate array +(requirement 4.) during `psci_setup()` in such an order that the index of the +core in the array is the same as the return value from these APIs. + +#### Dealing with holes in MPIDR allocation + +For platforms where the number of allocated MPIDRs is equal to the number of +core power domains, for example, Juno and FVPs, the logic to convert an MPIDR to +a core index should remain unchanged. Both Juno and FVP use a simple collision +proof hash function to do this. + +It is possible that on some platforms, the allocation of MPIDRs is not +contiguous or certain cores have been disabled. This essentially means that the +MPIDRs have been sparsely allocated, that is, the size of the range of MPIDRs +used by the platform is not equal to the number of core power domains. + +The platform could adopt one of the following approaches to deal with this +scenario: + +1. Implement more complex logic to convert a valid MPIDR to a core index while + maintaining the relationship described earlier. This means that the power + domain tree descriptor will not describe any core power domains which are + disabled or absent. Entries will not be allocated in the tree for these + domains. + +2. Treat unallocated MPIDRs and disabled cores as absent but still describe them + in the power domain descriptor, that is, the number of core nodes described + is equal to the size of the range of MPIDRs allocated. This approach will + lead to memory wastage since entries will be allocated in the tree but will + allow use of a simpler logic to convert an MPIDR to a core index. + + +### Traversing through and distinguishing between core and non-core power domains + +To fulfill requirement 3 and 4, separate data structures have been defined +to represent leaf and non-leaf power domain nodes in the tree. + +``` +/******************************************************************************* + * The following two data structures implement the power domain tree. The tree + * is used to track the state of all the nodes i.e. power domain instances + * described by the platform. The tree consists of nodes that describe CPU power + * domains i.e. leaf nodes and all other power domains which are parents of a + * CPU power domain i.e. non-leaf nodes. + ******************************************************************************/ +typedef struct non_cpu_pwr_domain_node { + /* + * Index of the first CPU power domain node level 0 which has this node + * as its parent. + */ + unsigned int cpu_start_idx; + + /* + * Number of CPU power domains which are siblings of the domain indexed + * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx + * -> cpu_start_idx + ncpus' have this node as their parent. + */ + unsigned int ncpus; + + /* Index of the parent power domain node */ + unsigned int parent_node; + + ----- +} non_cpu_pd_node_t; + +typedef struct cpu_pwr_domain_node { + unsigned long mpidr; + + /* Index of the parent power domain node */ + unsigned int parent_node; + + ----- +} cpu_pd_node_t; +``` + +The power domain tree is implemented as a combination of the following data +structures. + +``` +non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; +cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; +``` + +### Populating the power domain tree + +The `populate_power_domain_tree()` function in `psci_setup.c` implements the +algorithm to parse the power domain descriptor exported by the platform to +populate the two arrays. It is essentially a breadth-first-search. The nodes for +each level starting from the root are laid out one after another in the +`psci_non_cpu_pd_nodes` and `psci_cpu_pd_nodes` arrays as follows: + +``` +psci_non_cpu_pd_nodes -> [[Level 3 nodes][Level 2 nodes][Level 1 nodes]] +psci_cpu_pd_nodes -> [Level 0 nodes] +``` + +For the example power domain tree illustrated above, the `psci_cpu_pd_nodes` +will be populated as follows. The value in each entry is the index of the parent +node. Other fields have been ignored for simplicity. + +``` + +-------------+ ^ + CPU0 | 3 | | + +-------------+ | + CPU1 | 3 | | + +-------------+ | + CPU2 | 3 | | + +-------------+ | + CPU3 | 4 | | + +-------------+ | + CPU4 | 4 | | + +-------------+ | + CPU5 | 4 | | PLATFORM_CORE_COUNT + +-------------+ | + CPU6 | 5 | | + +-------------+ | + CPU7 | 5 | | + +-------------+ | + CPU8 | 5 | | + +-------------+ | + CPU9 | 6 | | + +-------------+ | + CPU10 | 6 | | + +-------------+ | + CPU11 | 6 | | + +-------------+ | + CPU12 | 6 | v + +-------------+ +``` + +The `psci_non_cpu_pd_nodes` array will be populated as follows. The value in +each entry is the index of the parent node. + +``` + +-------------+ ^ + PD0 | -1 | | + +-------------+ | + PD1 | 0 | | + +-------------+ | + PD2 | 0 | | + +-------------+ | + PD3 | 1 | | PLAT_NUM_POWER_DOMAINS - + +-------------+ | PLATFORM_CORE_COUNT + PD4 | 1 | | + +-------------+ | + PD5 | 2 | | + +-------------+ | + PD6 | 2 | | + +-------------+ v +``` + +Each core can find its node in the `psci_cpu_pd_nodes` array using the +`plat_my_core_pos()` function. When a core is turned on, the normal world +provides an MPIDR. The `plat_core_pos_by_mpidr()` function is used to validate +the MPIDR before using it to find the corresponding core node. The non-core power +domain nodes do not need to be identified. diff --git a/IPL/SDK/v3m/src/Dummy_BL33/docs/rt-svc-writers-guide.md b/IPL/SDK/v3m/src/Dummy_BL33/docs/rt-svc-writers-guide.md new file mode 100644 index 0000000..13f5310 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/docs/rt-svc-writers-guide.md @@ -0,0 +1,309 @@ +EL3 Runtime Service Writers Guide for ARM Trusted Firmware +========================================================== + +Contents +-------- + +1. [Introduction](#1--introduction) +2. [Owning Entities, Call Types and Function IDs](#2--owning-entities-call-types-and-function-ids) +3. [Getting started](#3--getting-started) +4. [Registering a runtime service](#4--registering-a-runtime-service) +5. [Initializing a runtime service](#5-initializing-a-runtime-service) +6. [Handling runtime service requests](#6--handling-runtime-service-requests) +7. [Services that contain multiple sub-services](#7--services-that-contain-multiple-sub-services) +8. [Secure-EL1 Payload Dispatcher service (SPD)](#8--secure-el1-payload-dispatcher-service-spd) + +- - - - - - - - - - - - - - - - - - + +1. Introduction +---------------- + +This document describes how to add a runtime service to the EL3 Runtime +Firmware component of ARM Trusted Firmware (BL3-1). + +Software executing in the normal world and in the trusted world at exception +levels lower than EL3 will request runtime services using the Secure Monitor +Call (SMC) instruction. These requests will follow the convention described in +the SMC Calling Convention PDD ([SMCCC]). The [SMCCC] assigns function +identifiers to each SMC request and describes how arguments are passed and +results are returned. + +SMC Functions are grouped together based on the implementor of the service, for +example a subset of the Function IDs are designated as "OEM Calls" (see [SMCCC] +for full details). The EL3 runtime services framework in BL3-1 enables the +independent implementation of services for each group, which are then compiled +into the BL3-1 image. This simplifies the integration of common software from +ARM to support [PSCI], Secure Monitor for a Trusted OS and SoC specific +software. The common runtime services framework ensures that SMC Functions are +dispatched to their respective service implementation - the [Firmware Design] +provides details of how this is achieved. + +The interface and operation of the runtime services depends heavily on the +concepts and definitions described in the [SMCCC], in particular SMC Function +IDs, Owning Entity Numbers (OEN), Fast and Standard calls, and the SMC32 and +SMC64 calling conventions. Please refer to that document for a full explanation +of these terms. + + +2. Owning Entities, Call Types and Function IDs +------------------------------------------------ + +The SMC Function Identifier includes a OEN field. These values and their +meaning are described in [SMCCC] and summarized in table 1 below. Some entities +are allocated a range of of OENs. The OEN must be interpreted in conjunction +with the SMC call type, which is either _Fast_ or _Standard_. Fast calls are +uninterruptible whereas Standard calls can be pre-empted. The majority of +Owning Entities only have allocated ranges for Fast calls: Standard calls are +reserved exclusively for Trusted OS providers or for interoperability with +legacy 32-bit software that predates the [SMCCC]. + + Type OEN Service + Fast 0 ARM Architecture calls + Fast 1 CPU Service calls + Fast 2 SiP Service calls + Fast 3 OEM Service calls + Fast 4 Standard Service calls + Fast 5-47 Reserved for future use + Fast 48-49 Trusted Application calls + Fast 50-63 Trusted OS calls + + Std 0- 1 Reserved for existing ARMv7 calls + Std 2-63 Trusted OS Standard Calls + +_Table 1: Service types and their corresponding Owning Entity Numbers_ + +Each individual entity can allocate the valid identifiers within the entity +range as they need - it is not necessary to coordinate with other entities of +the same type. For example, two SoC providers can use the same Function ID +within the SiP Service calls OEN range to mean different things - as these +calls should be specific to the SoC. The Standard Runtime Calls OEN is used for +services defined by ARM standards, such as [PSCI]. + +The SMC Function ID also indicates whether the call has followed the SMC32 +calling convention, where all parameters are 32-bit, or the SMC64 calling +convention, where the parameters are 64-bit. The framework identifies and +rejects invalid calls that use the SMC64 calling convention but that originate +from an AArch32 caller. + +The EL3 runtime services framework uses the call type and OEN to identify a +specific handler for each SMC call, but it is expected that an individual +handler will be responsible for all SMC Functions within a given service type. + + +3. Getting started +------------------- + +ARM Trusted Firmware has a [`services`] directory in the source tree under which +each owning entity can place the implementation of its runtime service. The +[PSCI] implementation is located here in the [`services/std_svc/psci`] +directory. + +Runtime service sources will need to include the [`runtime_svc.h`] header file. + + +4. Registering a runtime service +--------------------------------- + +A runtime service is registered using the `DECLARE_RT_SVC()` macro, specifying +the name of the service, the range of OENs covered, the type of service and +initialization and call handler functions. + + #define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) + +* `_name` is used to identify the data structure declared by this macro, and + is also used for diagnostic purposes + +* `_start` and `_end` values must be based on the `OEN_*` values defined in + [`runtime_svc.h`] + +* `_type` must be one of `SMC_TYPE_FAST` or `SMC_TYPE_STD` + +* `_setup` is the initialization function with the `rt_svc_init` signature: + + typedef int32_t (*rt_svc_init)(void); + +* `_smch` is the SMC handler function with the `rt_svc_handle` signature: + + typedef uint64_t (*rt_svc_handle)(uint32_t smc_fid, + uint64_t x1, uint64_t x2, + uint64_t x3, uint64_t x4, + void *reserved, + void *handle, + uint64_t flags); + +Details of the requirements and behavior of the two callbacks is provided in +the following sections. + +During initialization the services framework validates each declared service +to ensure that the following conditions are met: + +1. The `_start` OEN is not greater than the `_end` OEN +2. The `_end` OEN does not exceed the maximum OEN value (63) +3. The `_type` is one of `SMC_TYPE_FAST` or `SMC_TYPE_STD` +4. `_setup` and `_smch` routines have been specified + +[`std_svc_setup.c`] provides an example of registering a runtime service: + + /* Register Standard Service Calls as runtime service */ + DECLARE_RT_SVC( + std_svc, + OEN_STD_START, + OEN_STD_END, + SMC_TYPE_FAST, + std_svc_setup, + std_svc_smc_handler + ); + + +5. Initializing a runtime service +--------------------------------- + +Runtime services are initialized once, during cold boot, by the primary CPU +after platform and architectural initialization is complete. The framework +performs basic validation of the declared service before calling +the service initialization function (`_setup` in the declaration). This +function must carry out any essential EL3 initialization prior to receiving a +SMC Function call via the handler function. + +On success, the initialization function must return `0`. Any other return value +will cause the framework to issue a diagnostic: + + Error initializing runtime service + +and then ignore the service - the system will continue to boot but SMC calls +will not be passed to the service handler and instead return the _Unknown SMC +Function ID_ result `0xFFFFFFFF`. + +If the system must not be allowed to proceed without the service, the +initialization function must itself cause the firmware boot to be halted. + +If the service uses per-CPU data this must either be initialized for all CPUs +during this call, or be done lazily when a CPU first issues an SMC call to that +service. + + +6. Handling runtime service requests +------------------------------------- + +SMC calls for a service are forwarded by the framework to the service's SMC +handler function (`_smch` in the service declaration). This function must have +the following signature: + + typedef uint64_t (*rt_svc_handle)(uint32_t smc_fid, + uint64_t x1, uint64_t x2, + uint64_t x3, uint64_t x4, + void *reserved, + void *handle, + uint64_t flags); + +The handler is responsible for: + +1. Determining that `smc_fid` is a valid and supported SMC Function ID, + otherwise completing the request with the _Unknown SMC Function ID_: + + SMC_RET1(handle, SMC_UNK); + +2. Determining if the requested function is valid for the calling security + state. SMC Calls can be made from both the normal and trusted worlds and + the framework will forward all calls to the service handler. + + The `flags` parameter to this function indicates the caller security state + in bit[0], where a value of `1` indicates a non-secure caller. The + `is_caller_secure(flags)` and `is_caller_non_secure(flags)` can be used to + test this condition. + + If invalid, the request should be completed with: + + SMC_RET1(handle, SMC_UNK); + +3. Truncating parameters for calls made using the SMC32 calling convention. + Such calls can be determined by checking the CC field in bit[30] of the + `smc_fid` parameter, for example by using: + + if (GET_SMC_CC(smc_fid) == SMC_32) ... + + For such calls, the upper bits of the parameters x1-x4 and the saved + parameters X5-X7 are UNDEFINED and must be explicitly ignored by the + handler. This can be done by truncating the values to a suitable 32-bit + integer type before use, for example by ensuring that functions defined + to handle individual SMC Functions use appropriate 32-bit parameters. + +4. Providing the service requested by the SMC Function, utilizing the + immediate parameters x1-x4 and/or the additional saved parameters X5-X7. + The latter can be retrieved using the `SMC_GET_GP(handle, ref)` function, + supplying the appropriate `CTX_GPREG_Xn` reference, e.g. + + uint64_t x6 = SMC_GET_GP(handle, CTX_GPREG_X6); + +5. Implementing the standard SMC32 Functions that provide information about + the implementation of the service. These are the Call Count, Implementor + UID and Revision Details for each service documented in section 6 of the + [SMCCC]. + + The ARM Trusted Firmware expects owning entities to follow this + recommendation. + +5. Returning the result to the caller. The [SMCCC] allows for up to 256 bits + of return value in SMC64 using X0-X3 and 128 bits in SMC32 using W0-W3. The + framework provides a family of macros to set the multi-register return + value and complete the handler: + + SMC_RET1(handle, x0); + SMC_RET2(handle, x0, x1); + SMC_RET3(handle, x0, x1, x2); + SMC_RET4(handle, x0, x1, x2, x3); + +The `reserved` parameter to the handler is reserved for future use and can be +ignored. The value returned by a SMC handler is also reserved for future use - +completion of the handler function must always be via one of the `SMC_RETn()` +macros. + +NOTE: The PSCI and Test Secure-EL1 Payload Dispatcher services do not follow +all of the above requirements yet. + + +7. Services that contain multiple sub-services +----------------------------------------------- + +It is possible that a single owning entity implements multiple sub-services. For +example, the Standard calls service handles `0x84000000`-`0x8400FFFF` and +`0xC4000000`-`0xC400FFFF` functions. Within that range, the [PSCI] service +handles the `0x84000000`-`0x8400001F` and `0xC4000000`-`0xC400001F` functions. +In that respect, [PSCI] is a 'sub-service' of the Standard calls service. In +future, there could be additional such sub-services in the Standard calls +service which perform independent functions. + +In this situation it may be valuable to introduce a second level framework to +enable independent implementation of sub-services. Such a framework might look +very similar to the current runtime services framework, but using a different +part of the SMC Function ID to identify the sub-service. Trusted Firmware does +not provide such a framework at present. + + +8. Secure-EL1 Payload Dispatcher service (SPD) +----------------------------------------------- + +Services that handle SMC Functions targeting a Trusted OS, Trusted Application, +or other Secure-EL1 Payload are special. These services need to manage the +Secure-EL1 context, provide the _Secure Monitor_ functionality of switching +between the normal and secure worlds, deliver SMC Calls through to Secure-EL1 +and generally manage the Secure-EL1 Payload through CPU power-state transitions. + +TODO: Provide details of the additional work required to implement a SPD and +the BL3-1 support for these services. Or a reference to the document that will +provide this information.... + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._ + + +[Firmware Design]: ./firmware-design.md + +[`services`]: ../services +[`services/std_svc/psci`]: ../services/std_svc/psci +[`std_svc_setup.c`]: ../services/std_svc/std_svc_setup.c +[`runtime_svc.h`]: ../include/runtime_svc.h +[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)" +[SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)" diff --git a/IPL/SDK/v3m/src/Dummy_BL33/docs/spd/optee-dispatcher.md b/IPL/SDK/v3m/src/Dummy_BL33/docs/spd/optee-dispatcher.md new file mode 100644 index 0000000..c154f6b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/docs/spd/optee-dispatcher.md @@ -0,0 +1,13 @@ +OP-TEE Dispatcher +================= + +[OP-TEE OS] is a Trusted OS running as Secure EL1. + +To build and execute [OP-TEE OS] follow the instructions at +[ARM Trusted Firmware with OP-TEE] [OP-TEE OS] + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._ + +[OP-TEE OS]: http://github.com/OP-TEE/optee_os/tree/master/documentation/arm_trusted_firmware.md diff --git a/IPL/SDK/v3m/src/Dummy_BL33/docs/spd/tlk-dispatcher.md b/IPL/SDK/v3m/src/Dummy_BL33/docs/spd/tlk-dispatcher.md new file mode 100644 index 0000000..40c8344 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/docs/spd/tlk-dispatcher.md @@ -0,0 +1,70 @@ +Trusted Little Kernel (TLK) Dispatcher +======================================= +TLK dispatcher adds support for NVIDIA's Trusted Little Kernel (TLK) to work +with the Trusted Firmware. TLK-D can be compiled by including it in the +platform's makefile. TLK is primarily meant to work with Tegra SoCs, so until +Trusted Firmware starts supporting Tegra, the dispatcher code can only be +compiled for other platforms. + +In order to compile TLK-D, we need a BL32 image to be present. Since, TLKD +just needs to compile, any BL32 image would do. To use TLK as the BL32, please +refer to the "Build TLK" section. + +Once a BL32 is ready, TLKD can be included in the image by adding "SPD=tlkd" +to the build command. + +Trusted Little Kernel (TLK) +=========================== +TLK is a Trusted OS running as Secure EL1. It is a Free Open Source Software +(FOSS) release of the NVIDIA® Trusted Little Kernel (TLK) technology, which +extends technology made available with the development of the Little Kernel (LK). +You can download the LK modular embedded preemptive kernel for use on ARM, +x86, and AVR32 systems from https://github.com/travisg/lk + +NVIDIA implemented its Trusted Little Kernel (TLK) technology, designed as a +free and open-source trusted execution environment (OTE). + +TLK features include: + +• Small, pre-emptive kernel +• Supports multi-threading, IPCs, and thread scheduling +• Added TrustZone features +• Added Secure Storage +• Under MIT/FreeBSD license + +NVIDIA extensions to Little Kernel (LK) include: + +• User mode +• Address-space separation for TAs +• TLK Client Application (CA) library +• TLK TA library +• Crypto library (encrypt/decrypt, key handling) via OpenSSL +• Linux kernel driver +• Cortex A9/A15 support +• Power Management +• TrustZone memory carve-out (reconfigurable) +• Page table management +• Debugging support over UART (USB planned) + +TLK is hosted by NVIDIA on http://nv-tegra.nvidia.com under the +3rdparty/ote_partner/tlk.git repository. Detailed information about +TLK and OTE can be found in the Tegra_BSP_for_Android_TLK_FOSS_Reference.pdf +manual located under the "documentation" directory_. + +Build TLK +========= +To build and execute TLK, follow the instructions from "Building a TLK Device" +section from Tegra_BSP_for_Android_TLK_FOSS_Reference.pdf manual. + +Input parameters to TLK +======================= +TLK expects the TZDRAM size and a structure containing the boot arguments. BL2 +passes this information to the EL3 software as members of the bl32_ep_info +struct, where bl32_ep_info is part of bl31_params_t (passed by BL2 in X0) + +Example: +-------- + bl32_ep_info->args.arg0 = TZDRAM size available for BL32 + bl32_ep_info->args.arg1 = unused (used only on ARMv7) + bl32_ep_info->args.arg2 = pointer to boot args + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/docs/trusted-board-boot.md b/IPL/SDK/v3m/src/Dummy_BL33/docs/trusted-board-boot.md new file mode 100644 index 0000000..1cfa843 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/docs/trusted-board-boot.md @@ -0,0 +1,249 @@ +Trusted Board Boot Design Guide +=============================== + +Contents : + +1. [Introduction](#1--introduction) +2. [Chain of Trust](#2--chain-of-trust) +3. [Trusted Board Boot Sequence](#3--trusted-board-boot-sequence) +4. [Authentication Framework](#4--authentication-framework) +5. [Certificate Generation Tool](#5--certificate-generation-tool) + + +1. Introduction +---------------- + +The Trusted Board Boot (TBB) feature prevents malicious firmware from running on +the platform by authenticating all firmware images up to and including the +normal world bootloader. It does this by establishing a Chain of Trust using +Public-Key-Cryptography Standards (PKCS). + +This document describes the design of the ARM Trusted Firmware TBB +implementation. The current implementation is a proof of concept; future +versions will provide stronger architectural interfaces and implement the +missing functionality required in a production TBB-enabled system. + + +2. Chain of Trust +------------------ + +A Chain of Trust (CoT) starts with a set of implicitly trusted components. On +the ARM development platforms, these components are: + +* A SHA-256 hash of the Root of Trust Public Key (ROTPK). It is stored in the + trusted root-key storage registers. + +* The BL1 image, on the assumption that it resides in ROM so cannot be + tampered with. + +The remaining components in the CoT are either certificates or boot loader +images. The certificates follow the [X.509 v3] standard. This standard +enables adding custom extensions to the certificates, which are used to store +essential information to establish the CoT. + +In the TBB CoT all certificates are self-signed. There is no need for a +Certificate Authority (CA) because the CoT is not established by verifying the +validity of a certificate's issuer but by the content of the certificate +extensions. To sign the certificates, the PKCS#1 SHA-256 with RSA Encryption +signature scheme is used with a RSA key length of 2048 bits. Future version of +Trusted Firmware will support additional cryptographic algorithms. + +The certificates are categorised as "Key" and "Content" certificates. Key +certificates are used to verify public keys which have been used to sign content +certificates. Content certificates are used to store the hash of a boot loader +image. An image can be authenticated by calculating its hash and matching it +with the hash extracted from the content certificate. The SHA-256 function is +used to calculate all hashes. The public keys and hashes are included as +non-standard extension fields in the [X.509 v3] certificates. + +The keys used to establish the CoT are: + +* **Root of trust key** + + The private part of this key is used to sign the BL2 content certificate and + the trusted key certificate. The public part is the ROTPK. + +* **Trusted world key** + + The private part is used to sign the key certificates corresponding to the + secure world images (BL3-0, BL3-1 and BL3-2). The public part is stored in + one of the extension fields in the trusted world certificate. + +* **Non-trusted world key** + + The private part is used to sign the key certificate corresponding to the + non secure world image (BL3-3). The public part is stored in one of the + extension fields in the trusted world certificate. + +* **BL3-X keys** + + For each of BL3-0, BL3-1, BL3-2 and BL3-3, the private part is used to sign + the content certificate for the BL3-X image. The public part is stored in + one of the extension fields in the corresponding key certificate. + +The following images are included in the CoT: + +* BL1 +* BL2 +* BL3-0 (optional) +* BL3-1 +* BL3-3 +* BL3-2 (optional) + +The following certificates are used to authenticate the images. + +* **BL2 content certificate** + + It is self-signed with the private part of the ROT key. It contains a hash + of the BL2 image. + +* **Trusted key certificate** + + It is self-signed with the private part of the ROT key. It contains the + public part of the trusted world key and the public part of the non-trusted + world key. + +* **BL3-0 key certificate** + + It is self-signed with the trusted world key. It contains the public part of + the BL3-0 key. + +* **BL3-0 content certificate** + + It is self-signed with the BL3-0 key. It contains a hash of the BL3-0 image. + +* **BL3-1 key certificate** + + It is self-signed with the trusted world key. It contains the public part of + the BL3-1 key. + +* **BL3-1 content certificate** + + It is self-signed with the BL3-1 key. It contains a hash of the BL3-1 image. + +* **BL3-2 key certificate** + + It is self-signed with the trusted world key. It contains the public part of + the BL3-2 key. + +* **BL3-2 content certificate** + + It is self-signed with the BL3-2 key. It contains a hash of the BL3-2 image. + +* **BL3-3 key certificate** + + It is self-signed with the non-trusted world key. It contains the public + part of the BL3-3 key. + +* **BL3-3 content certificate** + + It is self-signed with the BL3-3 key. It contains a hash of the BL3-3 image. + +The BL3-0 and BL3-2 certificates are optional, but they must be present if the +corresponding BL3-0 or BL3-2 images are present. + + +3. Trusted Board Boot Sequence +------------------------------- + +The CoT is verified through the following sequence of steps. The system panics +if any of the steps fail. + +* BL1 loads and verifies the BL2 content certificate. The issuer public key is + read from the verified certificate. A hash of that key is calculated and + compared with the hash of the ROTPK read from the trusted root-key storage + registers. If they match, the BL2 hash is read from the certificate. + + Note: the matching operation is platform specific and is currently + unimplemented on the ARM development platforms. + +* BL1 loads the BL2 image. Its hash is calculated and compared with the hash + read from the certificate. Control is transferred to the BL2 image if all + the comparisons succeed. + +* BL2 loads and verifies the trusted key certificate. The issuer public key is + read from the verified certificate. A hash of that key is calculated and + compared with the hash of the ROTPK read from the trusted root-key storage + registers. If the comparison succeeds, BL2 reads and saves the trusted and + non-trusted world public keys from the verified certificate. + +The next two steps are executed for each of the BL3-0, BL3-1 & BL3-2 images. The +steps for the optional BL3-0 and BL3-2 images are skipped if these images are +not present. + +* BL2 loads and verifies the BL3-x key certificate. The certificate signature + is verified using the trusted world public key. If the signature + verification succeeds, BL2 reads and saves the BL3-x public key from the + certificate. + +* BL2 loads and verifies the BL3-x content certificate. The signature is + verified using the BL3-x public key. If the signature verification succeeds, + BL2 reads and saves the BL3-x image hash from the certificate. + +The next two steps are executed only for the BL3-3 image. + +* BL2 loads and verifies the BL3-3 key certificate. If the signature + verification succeeds, BL2 reads and saves the BL3-3 public key from the + certificate. + +* BL2 loads and verifies the BL3-3 content certificate. If the signature + verification succeeds, BL2 reads and saves the BL3-3 image hash from the + certificate. + +The next step is executed for all the boot loader images. + +* BL2 calculates the hash of each image. It compares it with the hash obtained + from the corresponding content certificate. The image authentication succeeds + if the hashes match. + +The Trusted Board Boot implementation spans both generic and platform-specific +BL1 and BL2 code, and in tool code on the host build machine. The feature is +enabled through use of specific build flags as described in the [User Guide]. + +On the host machine, a tool generates the certificates, which are included in +the FIP along with the boot loader images. These certificates are loaded in +Trusted SRAM using the IO storage framework. They are then verified by an +Authentication module included in the Trusted Firmware. + +The mechanism used for generating the FIP and the Authentication module are +described in the following sections. + + +4. Authentication Framework +---------------------------- + +The authentication framework included in the Trusted Firmware provides support +to implement the desired trusted boot sequence. ARM platforms use this framework +to implement the boot requirements specified in the TBBR-client document. + +More information about the authentication framework can be found in the +[Auth Framework] document. + + +5. Certificate Generation Tool +------------------------------- + +The `cert_create` tool is built and runs on the host machine as part of the +Trusted Firmware build process when `GENERATE_COT=1`. It takes the boot loader +images and keys as inputs (keys must be in PEM format) and generates the +certificates (in DER format) required to establish the CoT. New keys can be +generated by the tool in case they are not provided. The certificates are then +passed as inputs to the `fip_create` tool for creating the FIP. + +The certificates are also stored individually in the in the output build +directory. + +The tool resides in the `tools/cert_create` directory. It uses OpenSSL SSL +library version 1.0.1 or later to generate the X.509 certificates. Instructions +for building and using the tool can be found in the [User Guide]. + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2015, ARM Limited and Contributors. All rights reserved._ + + +[X.509 v3]: http://www.ietf.org/rfc/rfc5280.txt +[X.690]: http://www.itu.int/ITU-T/studygroups/com17/languages/X.690-0207.pdf +[Auth Framework]: auth-framework.md +[User Guide]: user-guide.md diff --git a/IPL/SDK/v3m/src/Dummy_BL33/docs/user-guide.md b/IPL/SDK/v3m/src/Dummy_BL33/docs/user-guide.md new file mode 100644 index 0000000..8f271cf --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/docs/user-guide.md @@ -0,0 +1,1101 @@ +ARM Trusted Firmware User Guide +=============================== + +Contents : + +1. [Introduction](#1--introduction) +2. [Host machine requirements](#2--host-machine-requirements) +3. [Tools](#3--tools) +4. [Getting the Trusted Firmware source code](#4--getting-the-trusted-firmware-source-code) +5. [Building the Trusted Firmware](#5--building-the-trusted-firmware) +6. [Building the rest of the software stack](#6--building-the-rest-of-the-software-stack) +7. [Preparing the images to run on FVP](#7--preparing-the-images-to-run-on-fvp) +8. [Running the software on FVP](#8--running-the-software-on-fvp) +9. [Running the software on Juno](#9--running-the-software-on-juno) + + +1. Introduction +---------------- + +This document describes how to build ARM Trusted Firmware and run it with a +tested set of other software components using defined configurations on the Juno +ARM development platform and ARM Fixed Virtual Platform (FVP) models. It is +possible to use other software components, configurations and platforms but that +is outside the scope of this document. + +This document should be used in conjunction with the [Firmware Design] and the +[Linaro release notes][Linaro releases]. + + +2. Host machine requirements +----------------------------- + +The minimum recommended machine specification for building the software and +running the FVP models is a dual-core processor running at 2GHz with 12GB of +RAM. For best performance, use a machine with a quad-core processor running at +2.6GHz with 16GB of RAM. + +The software has been tested on Ubuntu 14.04 LTS (64-bit). Packages used for +building the software were installed from that distribution unless otherwise +specified. + +3. Tools +--------- + +In addition to the prerequisite tools listed on the +[Linaro release notes][Linaro releases], the following tools are needed to use +the ARM Trusted Firmware: + +* `device-tree-compiler` package for building the Flattened Device Tree (FDT) + source files (`.dts` files) provided with this software. + +* `libssl-dev` package to build the certificate generation tool when support + for Trusted Board Boot is needed. + +* (Optional) For debugging, ARM [Development Studio 5 (DS-5)][DS-5] v5.21. + + +4. Getting the Trusted Firmware source code +-------------------------------------------- + +The Trusted Firmware source code can be obtained as part of the standard Linaro +releases, which provide a full software stack, including the Trusted Firmware, +normal world firmware, Linux kernel and device tree, file system as well as any +additional micro-controller firmware required by the platform. Please follow the +instructions on the [Linaro release notes][Linaro releases], section 2.2 +"Downloading the software sources" and section 2.3 "Downloading the filesystem +binaries". + +Note: Both the LSK kernel or the latest tracking kernel can be used along the +ARM Trusted Firmware, choose the one that best suits your needs. + +The Trusted Firmware source code can then be found in the `arm-tf/` directory. +This is the full git repository cloned from Github. The revision checked out by +the `repo` tool is indicated by the manifest file. Depending on the manifest +file you're using, this might not be the latest development version. To +synchronize your copy of the repository and get the latest updates, use the +following commands: + + # Change to the Trusted Firmware directory. + cd arm-tf + + # Download the latest code from Github. + git fetch github + + # Update your working copy to the latest master. + # This command will create a local branch master that tracks the remote + # branch master from Github. + git checkout --track github/master + + +Alternatively, the Trusted Firmware source code can be fetched on its own +from GitHub: + + git clone https://github.com/ARM-software/arm-trusted-firmware.git + +However, the rest of this document assumes that you got the Trusted Firmware +as part of the Linaro release. + + +5. Building the Trusted Firmware +--------------------------------- + +To build the Trusted Firmware images, change to the root directory of the +Trusted Firmware source tree and follow these steps: + +1. Set the compiler path, specify a Non-trusted Firmware image (BL3-3) and + a valid platform, and then build: + + CROSS_COMPILE=/bin/aarch64-linux-gnu- \ + BL33=/ \ + make PLAT= all fip + + If `PLAT` is not specified, `fvp` is assumed by default. See the "Summary of + build options" for more information on available build options. + + The BL3-3 image corresponds to the software that is executed after switching + to the non-secure world. UEFI can be used as the BL3-3 image. Refer to the + "Building the rest of the software stack" section below. + + The TSP (Test Secure Payload), corresponding to the BL3-2 image, is not + compiled in by default. Refer to the "Building the Test Secure Payload" + section below. + + By default this produces a release version of the build. To produce a debug + version instead, refer to the "Debugging options" section below. + + The build process creates products in a `build` directory tree, building + the objects and binaries for each boot loader stage in separate + sub-directories. The following boot loader binary files are created from + the corresponding ELF files: + + * `build///bl1.bin` + * `build///bl2.bin` + * `build///bl31.bin` + + where `` is the name of the chosen platform and `` is + either `debug` or `release`. A Firmare Image Package (FIP) will be created + as part of the build. It contains all boot loader images except for + `bl1.bin`. + + * `build///fip.bin` + + For more information on FIPs, see the "Firmware Image Package" section in + the [Firmware Design]. + +2. (Optional) Some platforms may require a BL3-0 image to boot. This image can + be included in the FIP when building the Trusted Firmware by specifying the + `BL30` build option: + + BL30=/ + +3. Output binary files `bl1.bin` and `fip.bin` are both required to boot the + system. How these files are used is platform specific. Refer to the + platform documentation on how to use the firmware images. + +4. (Optional) Build products for a specific build variant can be removed using: + + make DEBUG= PLAT= clean + + ... where `` is `0` or `1`, as specified when building. + + The build tree can be removed completely using: + + make realclean + +5. (Optional) Path to binary for certain BL stages (BL2, BL3-1 and BL3-2) can be + provided by specifying the BLx=/ where BLx is the BL stage. + This will bypass the build of the BL component from source, but will include + the specified binary in the final FIP image. Please note that BL3-2 will be + included in the build, only if the `SPD` build option is specified. + + For example, specifying BL2=/ in the build option, will + skip compilation of BL2 source in trusted firmware, but include the BL2 + binary specified in the final FIP image. + +### Summary of build options + +ARM Trusted Firmware build system supports the following build options. Unless +mentioned otherwise, these options are expected to be specified at the build +command line and are not to be modified in any component makefiles. Note that +the build system doesn't track dependency for build options. Therefore, if any +of the build options are changed from a previous build, a clean build must be +performed. + +#### Common build options + +* `BL30`: Path to BL3-0 image in the host file system. This image is optional. + If a BL3-0 image is present then this option must be passed for the `fip` + target. + +* `BL33`: Path to BL3-3 image in the host file system. This is mandatory for + `fip` target in case the BL2 from ARM Trusted Firmware is used. + +* `BL2`: This is an optional build option which specifies the path to BL2 + image for the `fip` target. In this case, the BL2 in the ARM Trusted + Firmware will not be built. + +* `BL31`: This is an optional build option which specifies the path to + BL3-1 image for the `fip` target. In this case, the BL3-1 in the ARM + Trusted Firmware will not be built. + +* `BL32`: This is an optional build option which specifies the path to + BL3-2 image for the `fip` target. In this case, the BL3-2 in the ARM + Trusted Firmware will not be built. + +* `FIP_NAME`: This is an optional build option which specifies the FIP + filename for the `fip` target. Default is `fip.bin`. + +* `CROSS_COMPILE`: Prefix to toolchain binaries. Please refer to examples in + this document for usage. + +* `DEBUG`: Chooses between a debug and release build. It can take either 0 + (release) or 1 (debug) as values. 0 is the default. + +* `LOG_LEVEL`: Chooses the log level, which controls the amount of console log + output compiled into the build. This should be one of the following: + + 0 (LOG_LEVEL_NONE) + 10 (LOG_LEVEL_NOTICE) + 20 (LOG_LEVEL_ERROR) + 30 (LOG_LEVEL_WARNING) + 40 (LOG_LEVEL_INFO) + 50 (LOG_LEVEL_VERBOSE) + + All log output up to and including the log level is compiled into the build. + The default value is 40 in debug builds and 20 in release builds. + +* `NS_TIMER_SWITCH`: Enable save and restore for non-secure timer register + contents upon world switch. It can take either 0 (don't save and restore) or + 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it + wants the timer registers to be saved and restored. + +* `PLAT`: Choose a platform to build ARM Trusted Firmware for. The chosen + platform name must be subdirectory of any depth under `plat/`, and must + contain a platform makefile named `platform.mk`. + +* `SPD`: Choose a Secure Payload Dispatcher component to be built into the + Trusted Firmware. The value should be the path to the directory containing + the SPD source, relative to `services/spd/`; the directory is expected to + contain a makefile called `.mk`. + +* `V`: Verbose build. If assigned anything other than 0, the build commands + are printed. Default is 0. + +* `ARM_GIC_ARCH`: Choice of ARM GIC architecture version used by the ARM GIC + driver for implementing the platform GIC API. This API is used + by the interrupt management framework. Default is 2 (that is, version 2.0). + +* `ARM_CCI_PRODUCT_ID`: Choice of ARM CCI product used by the platform. This + is used to determine the number of valid slave interfaces available in the + ARM CCI driver. Default is 400 (that is, CCI-400). + +* `IMF_READ_INTERRUPT_ID`: Boolean flag used by the interrupt management + framework to enable passing of the interrupt id to its handler. The id is + read using a platform GIC API. `INTR_ID_UNAVAILABLE` is passed instead if + this option set to 0. Default is 0. + +* `RESET_TO_BL31`: Enable BL3-1 entrypoint as the CPU reset vector instead + of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 + entrypoint) or 1 (CPU reset to BL3-1 entrypoint). + The default value is 0. + +* `CRASH_REPORTING`: A non-zero value enables a console dump of processor + register state when an unexpected exception occurs during execution of + BL3-1. This option defaults to the value of `DEBUG` - i.e. by default + this is only enabled for a debug build of the firmware. + +* `ASM_ASSERTION`: This flag determines whether the assertion checks within + assembly source files are enabled or not. This option defaults to the + value of `DEBUG` - that is, by default this is only enabled for a debug + build of the firmware. + +* `TSP_INIT_ASYNC`: Choose BL3-2 initialization method as asynchronous or + synchronous, (see "Initializing a BL3-2 Image" section in [Firmware + Design]). It can take the value 0 (BL3-2 is initialized using + synchronous method) or 1 (BL3-2 is initialized using asynchronous method). + Default is 0. + +* `USE_COHERENT_MEM`: This flag determines whether to include the coherent + memory region in the BL memory map or not (see "Use of Coherent memory in + Trusted Firmware" section in [Firmware Design]). It can take the value 1 + (Coherent memory region is included) or 0 (Coherent memory region is + excluded). Default is 1. + +* `TSPD_ROUTE_IRQ_TO_EL3`: A non zero value enables the routing model + for non-secure interrupts in which they are routed to EL3 (TSPD). The + default model (when the value is 0) is to route non-secure interrupts + to S-EL1 (TSP). + +* `TRUSTED_BOARD_BOOT`: Boolean flag to include support for the Trusted Board + Boot feature. When set to '1', BL1 and BL2 images include support to load + and verify the certificates and images in a FIP. The default value is '0'. + Generation and inclusion of certificates in the FIP depends upon the value + of the `GENERATE_COT` option. + +* `GENERATE_COT`: Boolean flag used to build and execute the `cert_create` + tool to create certificates as per the Chain of Trust described in + [Trusted Board Boot]. The build system then calls the `fip_create` tool to + include the certificates in the FIP. Default value is '0'. + + Specify `TRUSTED_BOARD_BOOT=1` and `GENERATE_COT=1` to include support for + the Trusted Board Boot Sequence in the BL1 and BL2 images and the FIP. + + Note that if `TRUSTED_BOARD_BOOT=0` and `GENERATE_COT=1`, the BL1 and BL2 + images will not include support for Trusted Board Boot. The FIP will still + include the key and content certificates. This FIP can be used to verify the + Chain of Trust on the host machine through other mechanisms. + + Note that if `TRUSTED_BOARD_BOOT=1` and `GENERATE_COT=0`, the BL1 and BL2 + images will include support for Trusted Board Boot, but the FIP will not + include the key and content certificates, causing a boot failure. + +* `CREATE_KEYS`: This option is used when `GENERATE_COT=1`. It tells the + certificate generation tool to create new keys in case no valid keys are + present or specified. Allowed options are '0' or '1'. Default is '1'. + +* `SAVE_KEYS`: This option is used when `GENERATE_COT=1`. It tells the + certificate generation tool to save the keys used to establish the Chain of + Trust. Allowed options are '0' or '1'. Default is '0' (do not save). + + Note: This option depends on 'CREATE_KEYS' to be enabled. If the keys + already exist in disk, they will be overwritten without further notice. + +* `ROT_KEY`: This option is used when `GENERATE_COT=1`. It specifies the + file that contains the ROT private key in PEM format. If `SAVE_KEYS=1`, this + file name will be used to save the key. + +* `TRUSTED_WORLD_KEY`: This option is used when `GENERATE_COT=1`. It + specifies the file that contains the Trusted World private key in PEM + format. If `SAVE_KEYS=1`, this file name will be used to save the key. + +* `NON_TRUSTED_WORLD_KEY`: This option is used when `GENERATE_COT=1`. It + specifies the file that contains the Non-Trusted World private key in PEM + format. If `SAVE_KEYS=1`, this file name will be used to save the key. + +* `BL30_KEY`: This option is used when `GENERATE_COT=1`. It specifies the + file that contains the BL3-0 private key in PEM format. If `SAVE_KEYS=1`, + this file name will be used to save the key. + +* `BL31_KEY`: This option is used when `GENERATE_COT=1`. It specifies the + file that contains the BL3-1 private key in PEM format. If `SAVE_KEYS=1`, + this file name will be used to save the key. + +* `BL32_KEY`: This option is used when `GENERATE_COT=1`. It specifies the + file that contains the BL3-2 private key in PEM format. If `SAVE_KEYS=1`, + this file name will be used to save the key. + +* `BL33_KEY`: This option is used when `GENERATE_COT=1`. It specifies the + file that contains the BL3-3 private key in PEM format. If `SAVE_KEYS=1`, + this file name will be used to save the key. + +* `PROGRAMMABLE_RESET_ADDRESS`: This option indicates whether the reset + vector address can be programmed or is fixed on the platform. It can take + either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a + programmable reset address, it is expected that a CPU will start executing + code directly at the right address, both on a cold and warm reset. In this + case, there is no need to identify the entrypoint on boot and this has + implication for `plat_get_my_entrypoint()` platform porting interface. + (see the [Porting Guide] for details) + +* `PSCI_EXTENDED_STATE_ID`: As per PSCI1.0 Specification, there are 2 formats + possible for the PSCI power-state parameter viz original and extended + State-ID formats. This flag if set to 1, configures the generic PSCI layer + to use the extended format. The default value of this flag is 0, which + means by default the original power-state format is used by the PSCI + implementation. This flag should be specified by the platform makefile + and it governs the return value of PSCI_FEATURES API for CPU_SUSPEND + smc function id. + +* `WARN_DEPRECATED`: This option decides whether to warn the usage of + deprecated platform APIs and context management helpers within Trusted + Firmware. It can take the value 1 (warn the use of deprecated APIs) or + 0. The default is 0. + +#### ARM development platform specific build options + +* `ARM_TSP_RAM_LOCATION`: location of the TSP binary. Options: + - `tsram` : Trusted SRAM (default option) + - `tdram` : Trusted DRAM (if available) + - `dram` : Secure region in DRAM (configured by the TrustZone controller) + +For a better understanding of these options, the ARM development platform memory +map is explained in the [Firmware Design]. + +* `ARM_ROTPK_LOCATION`: used when `TRUSTED_BOARD_BOOT=1`. It specifies the + location of the ROTPK hash returned by the function `plat_get_rotpk_info()` + for ARM platforms. Depending on the selected option, the proper private key + must be specified using the `ROT_KEY` option when building the Trusted + Firmware. This private key will be used by the certificate generation tool + to sign the BL2 and Trusted Key certificates. Available options for + `ARM_ROTPK_LOCATION` are: + + - `regs` : return the ROTPK hash stored in the Trusted root-key storage + registers. The private key corresponding to this ROTPK hash is not + currently available. + - `devel_rsa` : return a development public key hash embedded in the BL1 + and BL2 binaries. This hash has been obtained from the RSA public key + `arm_rotpk_rsa.der`, located in `plat/arm/board/common/rotpk`. To use + this option, `arm_rotprivk_rsa.pem` must be specified as `ROT_KEY` when + creating the certificates. + +* `ARM_RECOM_STATE_ID_ENC`: The PSCI1.0 specification recommends an encoding + for the construction of composite state-ID in the power-state parameter. + The existing PSCI clients currently do not support this encoding of + State-ID yet. Hence this flag is used to configure whether to use the + recommended State-ID encoding or not. The default value of this flag is 0, + in which case the platform is configured to expect NULL in the State-ID + field of power-state parameter. + +#### ARM CSS platform specific build options + +* `CSS_DETECT_PRE_1_7_0_SCP`: Boolean flag to detect SCP version + incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards + compatible change to the MTL protocol, used for AP/SCP communication. + Trusted Firmware no longer supports earlier SCP versions. If this option is + set to 1 then Trusted Firmware will detect if an earlier version is in use. + Default is 1. + + +### Creating a Firmware Image Package + +FIPs are automatically created as part of the build instructions described in +the previous section. It is also possible to independently build the FIP +creation tool and FIPs if required. To do this, follow these steps: + +Build the tool: + + make -C tools/fip_create + +It is recommended to remove the build artifacts before rebuilding: + + make -C tools/fip_create clean + +Create a Firmware package that contains existing BL2 and BL3-1 images: + + # fip_create --help to print usage information + # fip_create [--dump to show result] + ./tools/fip_create/fip_create fip.bin --dump \ + --bl2 build//debug/bl2.bin --bl31 build//debug/bl31.bin + + Firmware Image Package ToC: + --------------------------- + - Trusted Boot Firmware BL2: offset=0x88, size=0x81E8 + file: 'build//debug/bl2.bin' + - EL3 Runtime Firmware BL3-1: offset=0x8270, size=0xC218 + file: 'build//debug/bl31.bin' + --------------------------- + Creating "fip.bin" + +View the contents of an existing Firmware package: + + ./tools/fip_create/fip_create fip.bin --dump + + Firmware Image Package ToC: + --------------------------- + - Trusted Boot Firmware BL2: offset=0x88, size=0x81E8 + - EL3 Runtime Firmware BL3-1: offset=0x8270, size=0xC218 + --------------------------- + +Existing package entries can be individially updated: + + # Change the BL2 from Debug to Release version + ./tools/fip_create/fip_create fip.bin --dump \ + --bl2 build//release/bl2.bin + + Firmware Image Package ToC: + --------------------------- + - Trusted Boot Firmware BL2: offset=0x88, size=0x7240 + file: 'build//release/bl2.bin' + - EL3 Runtime Firmware BL3-1: offset=0x72C8, size=0xC218 + --------------------------- + Updating "fip.bin" + + +### Debugging options + +To compile a debug version and make the build more verbose use + + CROSS_COMPILE=/bin/aarch64-linux-gnu- \ + BL33=/ \ + make PLAT= DEBUG=1 V=1 all fip + +AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for +example DS-5) might not support this and may need an older version of DWARF +symbols to be emitted by GCC. This can be achieved by using the +`-gdwarf-` flag, with the version being set to 2 or 3. Setting the +version to 2 is recommended for DS-5 versions older than 5.16. + +When debugging logic problems it might also be useful to disable all compiler +optimizations by using `-O0`. + +NOTE: Using `-O0` could cause output images to be larger and base addresses +might need to be recalculated (see the **Memory layout on ARM development +platforms** section in the [Firmware Design]). + +Extra debug options can be passed to the build system by setting `CFLAGS`: + + CFLAGS='-O0 -gdwarf-2' \ + CROSS_COMPILE=/bin/aarch64-linux-gnu- \ + BL33=/ \ + make PLAT= DEBUG=1 V=1 all fip + + +### Building the Test Secure Payload + +The TSP is coupled with a companion runtime service in the BL3-1 firmware, +called the TSPD. Therefore, if you intend to use the TSP, the BL3-1 image +must be recompiled as well. For more information on SPs and SPDs, see the +"Secure-EL1 Payloads and Dispatchers" section in the [Firmware Design]. + +First clean the Trusted Firmware build directory to get rid of any previous +BL3-1 binary. Then to build the TSP image and include it into the FIP use: + + CROSS_COMPILE=/bin/aarch64-linux-gnu- \ + BL33=/ \ + make PLAT= SPD=tspd all fip + +An additional boot loader binary file is created in the `build` directory: + +* `build///bl32.bin` + +The FIP will now contain the additional BL3-2 image. Here is an example +output from an FVP build in release mode including BL3-2 and using +FVP_AARCH64_EFI.fd as BL3-3 image: + + Firmware Image Package ToC: + --------------------------- + - Trusted Boot Firmware BL2: offset=0xD8, size=0x6000 + file: './build/fvp/release/bl2.bin' + - EL3 Runtime Firmware BL3-1: offset=0x60D8, size=0x9000 + file: './build/fvp/release/bl31.bin' + - Secure Payload BL3-2 (Trusted OS): offset=0xF0D8, size=0x3000 + file: './build/fvp/release/bl32.bin' + - Non-Trusted Firmware BL3-3: offset=0x120D8, size=0x280000 + file: '../FVP_AARCH64_EFI.fd' + --------------------------- + Creating "build/fvp/release/fip.bin" + + +### Building the Certificate Generation Tool + +The `cert_create` tool can be built separately through the following commands: + + $ cd tools/cert_create + $ make PLAT= [DEBUG=1] [V=1] + +`DEBUG=1` builds the tool in debug mode. `V=1` makes the build process more +verbose. The following command should be used to obtain help about the tool: + + $ ./cert_create -h + +The `cert_create` tool is automatically built with the `fip` target when +`GENERATE_COT=1`. + + +### Building a FIP image with support for Trusted Board Boot + +The Trusted Board Boot feature is described in [Trusted Board Boot]. The +following steps should be followed to build a FIP image with support for this +feature. + +1. Fulfill the dependencies of the `mbedtls` cryptographic and image parser + modules by checking out the tag `mbedtls-1.3.11` from the + [mbedTLS Repository]. + + The `drivers/auth/mbedtls/mbedtls_*.mk` files contain the list of mbedTLS + source files the modules depend upon. + `include/drivers/auth/mbedtls/mbedtls_config.h` contains the configuration + options required to build the mbedTLS sources. + + Note that the mbedTLS library is licensed under the GNU GPL version 2 + or later license. Using mbedTLS source code will affect the licensing of + Trusted Firmware binaries that are built using this library. + +2. Ensure that the following command line variables are set while invoking + `make` to build Trusted Firmware: + + * `MBEDTLS_DIR=` + * `TRUSTED_BOARD_BOOT=1` + * `GENERATE_COT=1` + + In the case of ARM platforms, the location of the ROTPK hash must also be + specified at build time. Two locations are currently supported (see + `ARM_ROTPK_LOCATION` build option): + + * `ARM_ROTPK_LOCATION=regs`: the ROTPK hash is obtained from the Trusted + root-key storage registers present in the platform. On Juno, this + registers are read-only. On FVP Base and Cortex models, the registers + are read-only, but the value can be specified using the command line + option `bp.trusted_key_storage.public_key` when launching the model. + On both Juno and FVP models, the default value corresponds to an + ECDSA-SECP256R1 public key hash, whose private part is not currently + available. + + * `ARM_ROTPK_LOCATION=devel_rsa`: use the ROTPK hash that is hardcoded + in the ARM platform port. The private/public RSA key pair may be + found in `plat/arm/board/common/rotpk`. + + Example of command line using RSA development keys: + + CROSS_COMPILE=/bin/aarch64-linux-gnu- \ + BL33=/ \ + MBEDTLS_DIR= \ + make PLAT= TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \ + ARM_ROTPK_LOCATION=devel_rsa \ + ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ + all fip + + The result of this build will be the bl1.bin and the fip.bin binaries, with + the difference that the FIP will include the certificates corresponding to + the Chain of Trust described in the TBBR-client document. These certificates + can also be found in the output build directory. + + +### Checking source code style + +When making changes to the source for submission to the project, the source +must be in compliance with the Linux style guide, and to assist with this check +the project Makefile contains two targets, which both utilise the +`checkpatch.pl` script that ships with the Linux source tree. + +To check the entire source tree, you must first download a copy of +`checkpatch.pl` (or the full Linux source), set the `CHECKPATCH` environment +variable to point to the script and build the target checkcodebase: + + make CHECKPATCH=/linux/scripts/checkpatch.pl checkcodebase + +To just check the style on the files that differ between your local branch and +the remote master, use: + + make CHECKPATCH=/linux/scripts/checkpatch.pl checkpatch + +If you wish to check your patch against something other than the remote master, +set the `BASE_COMMIT` variable to your desired branch. By default, `BASE_COMMIT` +is set to `origin/master`. + + +6. Building the rest of the software stack +------------------------------------------- + +The Linaro release provides a set of scripts that automate the process of +building all components of the software stack. However, the scripts only support +a limited number of Trusted Firmware build options. Therefore, it is recommended +to modify these scripts to build all components except Trusted Firmware, and +build Trusted Firmware separately as described in the section "Building the +Trusted Firmware" above. + +The instructions below are targeted at an OpenEmbedded filesystem. + +1. To exclude Trusted Firmware from the automated build process, edit the + variant file `build-scripts/variants/-oe`, where `` + is either `fvp` or `juno`. Add the following lines at the end of the file: + + # Disable ARM Trusted Firmware build + ARM_TF_BUILD_ENABLED=0 + +2. Launch the build script: + + CROSS_COMPILE=aarch64-linux-gnu- \ + build-scripts/build-all.sh -oe + +### Preparing the Firmware Image Package + +The EDK2 binary should be specified as `BL33` in the `make` command line when +building the Trusted Firmware. See the "Building the Trusted Firmware" section +above. The EDK2 binary for use with the ARM Trusted Firmware can be found here: + + uefi/edk2/Build/ArmVExpress-FVP-AArch64-Minimal/DEBUG_GCC49/FV/FVP_AARCH64_EFI.fd [for FVP] + uefi/edk2/Build/ArmJuno/DEBUG_GCC49/FV/BL33_AP_UEFI.fd [for Juno] + +### Building an alternative EDK2 + +* By default, EDK2 is built in debug mode. To build a release version instead, + change the following line in the variant file: + + UEFI_BUILD_MODE=DEBUG + + into: + + UEFI_BUILD_MODE=RELEASE + +* On FVP, if legacy GICv2 locations are used, the EDK2 platform makefile must + be updated. This is required as EDK2 does not support probing for the GIC + location. To do this, first clean the EDK2 build directory: + + build-scripts/build-uefi.sh fvp-oe clean + + Then edit the following file: + + uefi/edk2/ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.mak + + and add the following build flag into the `EDK2_MACROS` variable: + + -D ARM_FVP_LEGACY_GICV2_LOCATION=1 + + Then rebuild everything as described above in step 2. + + Finally rebuild the Trusted Firmware to generate a new FIP using the + instructions in the "Building the Trusted Firmware" section. + + +7. Preparing the images to run on FVP +-------------------------------------- + +### Obtaining the Flattened Device Trees + +Depending on the FVP configuration and Linux configuration used, different +FDT files are required. FDTs for the Foundation and Base FVPs can be found in +the Trusted Firmware source directory under `fdts/`. The Foundation FVP has a +subset of the Base FVP components. For example, the Foundation FVP lacks CLCD +and MMC support, and has only one CPU cluster. + +Note: It is not recommended to use the FDTs built along the kernel because not +all FDTs are available from there. + +* `fvp-base-gicv2-psci.dtb` + + (Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with + Base memory map configuration. + +* `fvp-base-gicv2legacy-psci.dtb` + + For use with AEMv8 Base FVP with legacy VE GIC memory map configuration. + +* `fvp-base-gicv3-psci.dtb` + + For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base memory map + configuration and Linux GICv3 support. + +* `fvp-foundation-gicv2-psci.dtb` + + (Default) For use with Foundation FVP with Base memory map configuration. + +* `fvp-foundation-gicv2legacy-psci.dtb` + + For use with Foundation FVP with legacy VE GIC memory map configuration. + +* `fvp-foundation-gicv3-psci.dtb` + + For use with Foundation FVP with Base memory map configuration and Linux + GICv3 support. + +Copy the chosen FDT blob as `fdt.dtb` to the directory from which the FVP +is launched. Alternatively a symbolic link may be used. + +### Preparing the kernel image + +Copy the kernel image file `linux/arch/arm64/boot/Image` to the directory from +which the FVP is launched. Alternatively a symbolic link may be used. + + +8. Running the software on FVP +------------------------------- + +This version of the ARM Trusted Firmware has been tested on the following ARM +FVPs (64-bit versions only). + +* `Foundation_Platform` (Version 9.1, Build 9.1.33) +* `FVP_Base_AEMv8A-AEMv8A` (Version 6.2, Build 0.8.6202) +* `FVP_Base_Cortex-A57x4-A53x4` (Version 6.2, Build 0.8.6202) +* `FVP_Base_Cortex-A57x1-A53x1` (Version 6.2, Build 0.8.6202) +* `FVP_Base_Cortex-A57x2-A53x4` (Version 6.2, Build 0.8.6202) + +NOTE: The build numbers quoted above are those reported by launching the FVP +with the `--version` parameter. + +NOTE: The software will not work on Version 1.0 of the Foundation FVP. +The commands below would report an `unhandled argument` error in this case. + +NOTE: The Foundation FVP does not provide a debugger interface. + +Please refer to the FVP documentation for a detailed description of the model +parameter options. A brief description of the important ones that affect the +ARM Trusted Firmware and normal world software behavior is provided below. + +The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be +downloaded for free from [ARM's website][ARM FVP website]. + + +### Running on the Foundation FVP with reset to BL1 entrypoint + +The following `Foundation_Platform` parameters should be used to boot Linux with +4 CPUs using the ARM Trusted Firmware. + + /Foundation_Platform \ + --cores=4 \ + --secure-memory \ + --visualization \ + --gicv3 \ + --data="/"@0x0 \ + --data="/"@0x08000000 \ + --data="/"@0x83000000 \ + --data="/"@0x80080000 \ + --block-device="/" + +1. The `--data=""@0x...` parameters are used to load + binaries into memory. + + * BL1 is loaded at the start of the Trusted ROM. + * The Firmware Image Package is loaded at the start of NOR FLASH0. + * The Linux kernel image and device tree are loaded in DRAM. + +2. The `--block-device` parameter is used to specify the path to the file + system image provided to Linux via VirtioBlock. Note that it must point to + the real file and that a symbolic link to this file cannot be used with the + FVP. + +The default use-case for the Foundation FVP is to enable the GICv3 device in +the model but use the GICv2 FDT, in order for Linux to drive the GIC in GICv2 +emulation mode. + +### Notes regarding Base FVP configuration options + +Please refer to these notes in the subsequent "Running on the Base FVP" +sections. + +1. The `-C bp.flashloader0.fname` parameter is used to load a Firmware Image + Package at the start of NOR FLASH0 (see the "Building the Trusted Firmware" + section above). + +2. Using `cache_state_modelled=1` makes booting very slow. The software will + still work (and run much faster) without this option but this will hide any + cache maintenance defects in the software. + +3. The `-C bp.virtioblockdevice.image_path` parameter is used to specify the + path to the file system image provided to Linux via VirtioBlock. Note that + it must point to the real file and that a symbolic link to this file cannot + be used with the FVP. Ensure that the FVP doesn't output any error messages. + If the following error message is displayed: + + ERROR: BlockDevice: Failed to open "/"! + + then make sure the path to the file-system image in the model parameter is + correct and that read permission is correctly set on the file-system image + file. + +4. Setting the `-C bp.secure_memory` parameter to `1` is only supported on + Base FVP versions 5.4 and newer. Setting this parameter to `0` is also + supported. The `-C bp.tzc_400.diagnostics=1` parameter is optional. It + instructs the FVP to provide some helpful information if a secure memory + violation occurs. + +5. The `--data=""@` parameter is + used to load images into Base FVP memory. The base addresses used should + match the image base addresses used while linking the images. This parameter + is used to load the Linux kernel image and device tree into DRAM. + +6. This and the following notes only apply when the firmware is built with + the `RESET_TO_BL31` option. + + The `--data=""@` + parameter is needed to load the individual bootloader images in memory. + BL32 image is only needed if BL31 has been built to expect a Secure-EL1 + Payload. + +7. The `-C cluster.cpu.RVBAR=@` parameter, where + X and Y are the cluster and CPU numbers respectively, is used to set the + reset vector for each core. + +8. Changing the default value of `FVP_SHARED_DATA_LOCATION` will also require + changing the value of + `--data=""@` and + `-C cluster.cpu.RVBAR=@`, to the new value of + `BL31_BASE`. + +9. Changing the default value of `FVP_TSP_RAM_LOCATION` will also require + changing the value of + `--data=""@` to the new value of + `BL32_BASE`. + + +### Running on the AEMv8 Base FVP with reset to BL1 entrypoint + +Please read "Notes regarding Base FVP configuration options" section above for +information about some of the options to run the software. + +The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux +with 8 CPUs using the ARM Trusted Firmware. + + /FVP_Base_AEMv8A-AEMv8A \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cluster0.NUM_CORES=4 \ + -C cluster1.NUM_CORES=4 \ + -C cache_state_modelled=1 \ + -C bp.secureflashloader.fname="/" \ + -C bp.flashloader0.fname="/" \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + +### Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint + +Please read "Notes regarding Base FVP configuration options" section above for +information about some of the options to run the software. + +The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to +boot Linux with 8 CPUs using the ARM Trusted Firmware. + + /FVP_Base_Cortex-A57x4-A53x4 \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cache_state_modelled=1 \ + -C bp.secureflashloader.fname="/" \ + -C bp.flashloader0.fname="/" \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + +### Running on the AEMv8 Base FVP with reset to BL3-1 entrypoint + +Please read "Notes regarding Base FVP configuration options" section above for +information about some of the options to run the software. + +The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux +with 8 CPUs using the ARM Trusted Firmware. + + /FVP_Base_AEMv8A-AEMv8A \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cluster0.NUM_CORES=4 \ + -C cluster1.NUM_CORES=4 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.RVBAR=0x04023000 \ + -C cluster0.cpu1.RVBAR=0x04023000 \ + -C cluster0.cpu2.RVBAR=0x04023000 \ + -C cluster0.cpu3.RVBAR=0x04023000 \ + -C cluster1.cpu0.RVBAR=0x04023000 \ + -C cluster1.cpu1.RVBAR=0x04023000 \ + -C cluster1.cpu2.RVBAR=0x04023000 \ + -C cluster1.cpu3.RVBAR=0x04023000 \ + --data cluster0.cpu0="/"@0x04023000 \ + --data cluster0.cpu0="/"@0x04001000 \ + --data cluster0.cpu0="/"@0x88000000 \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + +### Running on the Cortex-A57-A53 Base FVP with reset to BL3-1 entrypoint + +Please read "Notes regarding Base FVP configuration options" section above for +information about some of the options to run the software. + +The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to +boot Linux with 8 CPUs using the ARM Trusted Firmware. + + /FVP_Base_Cortex-A57x4-A53x4 \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.RVBARADDR=0x04023000 \ + -C cluster0.cpu1.RVBARADDR=0x04023000 \ + -C cluster0.cpu2.RVBARADDR=0x04023000 \ + -C cluster0.cpu3.RVBARADDR=0x04023000 \ + -C cluster1.cpu0.RVBARADDR=0x04023000 \ + -C cluster1.cpu1.RVBARADDR=0x04023000 \ + -C cluster1.cpu2.RVBARADDR=0x04023000 \ + -C cluster1.cpu3.RVBARADDR=0x04023000 \ + --data cluster0.cpu0="/"@0x04023000 \ + --data cluster0.cpu0="/"@0x04001000 \ + --data cluster0.cpu0="/"@0x88000000 \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + +### Configuring the GICv2 memory map + +The Base FVP models support GICv2 with the default model parameters at the +following addresses. The Foundation FVP also supports these addresses when +configured for GICv3 in GICv2 emulation mode. + + GICv2 Distributor Interface 0x2f000000 + GICv2 CPU Interface 0x2c000000 + GICv2 Virtual CPU Interface 0x2c010000 + GICv2 Hypervisor Interface 0x2c02f000 + +The AEMv8 Base FVP can be configured to support GICv2 at addresses +corresponding to the legacy (Versatile Express) memory map as follows. These are +the default addresses when using the Foundation FVP in GICv2 mode. + + GICv2 Distributor Interface 0x2c001000 + GICv2 CPU Interface 0x2c002000 + GICv2 Virtual CPU Interface 0x2c004000 + GICv2 Hypervisor Interface 0x2c006000 + +The choice of memory map is reflected in the build variant field (bits[15:12]) +in the `SYS_ID` register (Offset `0x0`) in the Versatile Express System +registers memory map (`0x1c010000`). + +* `SYS_ID.Build[15:12]` + + `0x1` corresponds to the presence of the Base GIC memory map. This is the + default value on the Base FVPs. + +* `SYS_ID.Build[15:12]` + + `0x0` corresponds to the presence of the Legacy VE GIC memory map. This is + the default value on the Foundation FVP. + +This register can be configured as described in the following sections. + +NOTE: If the legacy VE GIC memory map is used, then the corresponding FDT and +BL3-3 images should be used. + +#### Configuring AEMv8 Foundation FVP GIC for legacy VE memory map + +The following parameters configure the Foundation FVP to use GICv2 with the +legacy VE memory map: + + /Foundation_Platform \ + --cores=4 \ + --secure-memory \ + --visualization \ + --no-gicv3 \ + --data="/"@0x0 \ + --data="/"@0x8000000 \ + --block-device="/" + +Explicit configuration of the `SYS_ID` register is not required. + +#### Configuring AEMv8 Base FVP GIC for legacy VE memory map + +The following parameters configure the AEMv8 Base FVP to use GICv2 with the +legacy VE memory map. They must added to the parameters described in the +"Running on the AEMv8 Base FVP" section above: + + -C cluster0.gic.GICD-offset=0x1000 \ + -C cluster0.gic.GICC-offset=0x2000 \ + -C cluster0.gic.GICH-offset=0x4000 \ + -C cluster0.gic.GICH-other-CPU-offset=0x5000 \ + -C cluster0.gic.GICV-offset=0x6000 \ + -C cluster0.gic.PERIPH-size=0x8000 \ + -C cluster1.gic.GICD-offset=0x1000 \ + -C cluster1.gic.GICC-offset=0x2000 \ + -C cluster1.gic.GICH-offset=0x4000 \ + -C cluster1.gic.GICH-other-CPU-offset=0x5000 \ + -C cluster1.gic.GICV-offset=0x6000 \ + -C cluster1.gic.PERIPH-size=0x8000 \ + -C gic_distributor.GICD-alias=0x2c001000 \ + -C gicv3.gicv2-only=1 \ + -C bp.variant=0x0 + +The `bp.variant` parameter corresponds to the build variant field of the +`SYS_ID` register. Setting this to `0x0` allows the ARM Trusted Firmware to +detect the legacy VE memory map while configuring the GIC. + + +9. Running the software on Juno +-------------------------------- + +This version of the ARM Trusted Firmware has been tested on Juno r0 and Juno r1. + +To execute the versions of software components on Juno referred to in this +document, the latest Juno board recovery image must be installed. If you +have an earlier version installed or are unsure which version is installed, +follow the recovery image update instructions in the [Juno Software Guide] +on the [ARM Connected Community] website. The latest Juno board recovery image +can be obtained from [Linaro releases], see section 2.7 "Using prebuilt +binaries". + +### Preparing Trusted Firmware images + +The Juno platform requires a BL0 and a BL30 image to boot up. The BL0 image +contains the ROM firmware that runs on the SCP (System Control Processor), +whereas the BL30 image contains the SCP Runtime firmware. Both images are +embedded within the Juno board recovery image, these are the files `bl0.bin` +and `bl30.bin`. + +The BL30 file must be part of the FIP image. Therefore, its path must be +supplied using the `BL30` variable on the command line when building the +FIP. Please refer to the section "Building the Trusted Firmware". + +After building Trusted Firmware, the files `bl1.bin` and `fip.bin` need copying +to the `SOFTWARE/` directory as explained in the [Juno Software Guide]. + +### Other Juno software information + +Please refer to the [Juno Software Guide] to: + +* Install and run the Juno binaries on the board +* Obtain any other Juno software information + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved._ + + +[Firmware Design]: firmware-design.md +[Linaro releases]: http://releases.linaro.org/15.06/members/arm/platforms +[ARM FVP website]: http://www.arm.com/fvp +[ARM Connected Community]: http://community.arm.com +[Juno Software Guide]: http://community.arm.com/docs/DOC-8396 +[DS-5]: http://www.arm.com/products/tools/software-tools/ds-5/index.php +[mbedTLS Repository]: https://github.com/ARMmbed/mbedtls.git +[Porting Guide]: ./porting-guide.md +[Trusted Board Boot]: trusted-board-boot.md diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/cci/cci.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/cci/cci.c new file mode 100644 index 0000000..2e773a9 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/cci/cci.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +static uintptr_t g_cci_base; +static unsigned int g_max_master_id; +static const int *g_cci_slave_if_map; + +#if DEBUG +static int validate_cci_map(const int *map) +{ + unsigned int valid_cci_map = 0; + int slave_if_id; + int i; + + /* Validate the map */ + for (i = 0; i <= g_max_master_id; i++) { + slave_if_id = map[i]; + + if (slave_if_id < 0) + continue; + + if (slave_if_id >= CCI_SLAVE_INTERFACE_COUNT) { + tf_printf("Slave interface ID is invalid\n"); + return 0; + } + + if (valid_cci_map & (1 << slave_if_id)) { + tf_printf("Multiple masters are assigned same" + " slave interface ID\n"); + return 0; + } + valid_cci_map |= 1 << slave_if_id; + } + + if (!valid_cci_map) { + tf_printf("No master is assigned a valid slave interface\n"); + return 0; + } + + return 1; +} +#endif /* DEBUG */ + +void cci_init(uintptr_t cci_base, + const int *map, + unsigned int num_cci_masters) +{ + assert(map); + assert(cci_base); + + g_cci_base = cci_base; + + /* + * Master Id's are assigned from zero, So in an array of size n + * the max master id is (n - 1). + */ + g_max_master_id = num_cci_masters - 1; + + assert(validate_cci_map(map)); + g_cci_slave_if_map = map; +} + +void cci_enable_snoop_dvm_reqs(unsigned int master_id) +{ + int slave_if_id; + + assert(g_cci_base); + assert(master_id <= g_max_master_id); + + slave_if_id = g_cci_slave_if_map[master_id]; + assert((slave_if_id < CCI_SLAVE_INTERFACE_COUNT) && (slave_if_id >= 0)); + + /* + * Enable Snoops and DVM messages, no need for Read/Modify/Write as + * rest of bits are write ignore + */ + mmio_write_32(g_cci_base + + SLAVE_IFACE_OFFSET(slave_if_id) + + SNOOP_CTRL_REG, DVM_EN_BIT | SNOOP_EN_BIT); + + /* Wait for the dust to settle down */ + while (mmio_read_32(g_cci_base + STATUS_REG) & CHANGE_PENDING_BIT) + ; +} + +void cci_disable_snoop_dvm_reqs(unsigned int master_id) +{ + int slave_if_id; + + assert(g_cci_base); + assert(master_id <= g_max_master_id); + + slave_if_id = g_cci_slave_if_map[master_id]; + assert((slave_if_id < CCI_SLAVE_INTERFACE_COUNT) && (slave_if_id >= 0)); + + /* + * Disable Snoops and DVM messages, no need for Read/Modify/Write as + * rest of bits are write ignore. + */ + mmio_write_32(g_cci_base + + SLAVE_IFACE_OFFSET(slave_if_id) + + SNOOP_CTRL_REG, ~(DVM_EN_BIT | SNOOP_EN_BIT)); + + /* Wait for the dust to settle down */ + while (mmio_read_32(g_cci_base + STATUS_REG) & CHANGE_PENDING_BIT) + ; +} + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/cci400/cci400.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/cci400/cci400.c new file mode 100644 index 0000000..242e1fa --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/cci400/cci400.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#define MAX_CLUSTERS 2 + +static uintptr_t cci_base_addr; +static unsigned int cci_cluster_ix_to_iface[MAX_CLUSTERS]; + + +void cci_init(uintptr_t cci_base, + int slave_iface3_cluster_ix, + int slave_iface4_cluster_ix) +{ + /* + * Check the passed arguments are valid. The cluster indices must be + * less than MAX_CLUSTERS, not the same as each other and at least one + * of them must be refer to a valid cluster index. + */ + assert(cci_base); + assert(slave_iface3_cluster_ix < MAX_CLUSTERS); + assert(slave_iface4_cluster_ix < MAX_CLUSTERS); + assert(slave_iface3_cluster_ix != slave_iface4_cluster_ix); + assert((slave_iface3_cluster_ix >= 0) || + (slave_iface3_cluster_ix >= 0)); + + WARN("Please migrate to common cci driver, This driver will be" \ + " deprecated in future\n"); + + cci_base_addr = cci_base; + if (slave_iface3_cluster_ix >= 0) + cci_cluster_ix_to_iface[slave_iface3_cluster_ix] = + SLAVE_IFACE3_OFFSET; + if (slave_iface4_cluster_ix >= 0) + cci_cluster_ix_to_iface[slave_iface4_cluster_ix] = + SLAVE_IFACE4_OFFSET; +} + +static inline unsigned long get_slave_iface_base(unsigned long mpidr) +{ + /* + * We assume the TF topology code allocates affinity instances + * consecutively from zero. + * It is a programming error if this is called without initializing + * the slave interface to use for this cluster. + */ + unsigned int cluster_id = + (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + + assert(cluster_id < MAX_CLUSTERS); + assert(cci_cluster_ix_to_iface[cluster_id] != 0); + + return cci_base_addr + cci_cluster_ix_to_iface[cluster_id]; +} + +void cci_enable_cluster_coherency(unsigned long mpidr) +{ + assert(cci_base_addr); + /* Enable Snoops and DVM messages */ + mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG, + DVM_EN_BIT | SNOOP_EN_BIT); + + /* Wait for the dust to settle down */ + while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT) + ; +} + +void cci_disable_cluster_coherency(unsigned long mpidr) +{ + assert(cci_base_addr); + /* Disable Snoops and DVM messages */ + mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG, + ~(DVM_EN_BIT | SNOOP_EN_BIT)); + + /* Wait for the dust to settle down */ + while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT) + ; +} + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/ccn/ccn.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/ccn/ccn.c new file mode 100644 index 0000000..aef891b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/ccn/ccn.c @@ -0,0 +1,530 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ccn_private.h" + +static const ccn_desc_t *ccn_plat_desc; +#if IMAGE_BL31 +DEFINE_BAKERY_LOCK(ccn_lock); +#endif + +/******************************************************************************* + * This function takes the base address of the CCN's programmer's view (PV), a + * region ID of one of the 256 regions (0-255) and a register offset within the + * region. It converts the first two parameters into a base address and uses it + * to read the register at the offset. + ******************************************************************************/ +static inline unsigned long long ccn_reg_read(uintptr_t periphbase, + unsigned int region_id, + unsigned int register_offset) +{ + uintptr_t region_base; + + assert(periphbase); + assert(region_id < REGION_ID_LIMIT); + + region_base = periphbase + region_id_to_base(region_id); + return mmio_read_64(region_base + register_offset); +} + +/******************************************************************************* + * This function takes the base address of the CCN's programmer's view (PV), a + * region ID of one of the 256 regions (0-255), a register offset within the + * region and a value. It converts the first two parameters into a base address + * and uses it to write the value in the register at the offset. + ******************************************************************************/ +static inline void ccn_reg_write(uintptr_t periphbase, + unsigned int region_id, + unsigned int register_offset, + unsigned long long value) +{ + uintptr_t region_base; + + assert(periphbase); + assert(region_id < REGION_ID_LIMIT); + + region_base = periphbase + region_id_to_base(region_id); + mmio_write_64(region_base + register_offset, value); +} + +#if DEBUG + +typedef struct rn_info { + unsigned char node_desc[MAX_RN_NODES]; + } rn_info_t; + +/******************************************************************************* + * This function takes the base address of the CCN's programmer's view (PV) and + * the node ID of a Request Node (RN-D or RN-I). It returns the maximum number + * of master interfaces resident on that node. This number is equal to the least + * significant two bits of the node type ID + 1. + ******************************************************************************/ +static unsigned int ccn_get_rni_mcount(uintptr_t periphbase, + unsigned int rn_id) +{ + unsigned int rn_type_id; + + /* Use the node id to find the type of RN-I/D node */ + rn_type_id = get_node_type(ccn_reg_read(periphbase, + rn_id + RNI_REGION_ID_START, + REGION_ID_OFFSET)); + + /* Return the number master interfaces based on node type */ + return rn_type_id_to_master_cnt(rn_type_id); +} + +/******************************************************************************* + * This function reads the CCN registers to find the following information about + * the ACE/ACELite/ACELite+DVM/CHI interfaces resident on the various types of + * Request Nodes (RN-Fs, RN-Is and RN-Ds) in the system: + * + * 1. The total number of such interfaces that this CCN IP supports. This is the + * cumulative number of interfaces across all Request node types. It is + * passed back as the return value of this function. + * + * 2. The maximum number of interfaces of a type resident on a Request node of + * one of the three types. This information is populated in the 'info' + * array provided by the caller as described next. + * + * The array has 64 entries. Each entry corresponds to a Request node. The + * Miscellaneous node's programmer's view has RN-F, RN-I and RN-D ID + * registers. For each RN-I and RN-D ID indicated as being present in these + * registers, its identification register (offset 0xFF00) is read. This + * register specifies the maximum number of master interfaces the node + * supports. For RN-Fs it is assumed that there can be only a single fully + * coherent master resident on each node. The counts for each type of node + * are use to populate the array entry at the index corresponding to the node + * ID i.e. rn_info[node ID] = + ******************************************************************************/ +static unsigned int ccn_get_rn_master_info(uintptr_t periphbase, + rn_info_t *info) +{ + unsigned int num_masters = 0; + rn_types_t rn_type; + + assert (info); + + for (rn_type = RN_TYPE_RNF; rn_type < NUM_RN_TYPES; rn_type++) { + unsigned int mn_reg_off, node_id; + unsigned long long rn_bitmap; + + /* + * RN-F, RN-I, RN-D node registers in the MN region occupy + * contiguous 16 byte apart offsets. + */ + mn_reg_off = MN_RNF_NODEID_OFFSET + (rn_type << 4); + rn_bitmap = ccn_reg_read(periphbase, MN_REGION_ID, mn_reg_off); + + FOR_EACH_PRESENT_NODE_ID(node_id, rn_bitmap) { + unsigned int node_mcount; + + /* + * A RN-F does not have a node type since it does not + * export a programmer's interface. It can only have a + * single fully coherent master residing on it. If the + * offset of the MN(Miscellaneous Node) register points + * to a RN-I/D node then the master count is set to the + * maximum number of master interfaces that can possibly + * reside on the node. + */ + node_mcount = (mn_reg_off == MN_RNF_NODEID_OFFSET ? 1 : + ccn_get_rni_mcount(periphbase, node_id)); + + /* + * Use this value to increment the maximum possible + * master interfaces in the system. + */ + num_masters += node_mcount; + + /* + * Update the entry in 'info' for this node ID with + * the maximum number of masters than can sit on + * it. This information will be used to validate the + * node information passed by the platform later. + */ + info->node_desc[node_id] = node_mcount; + } + } + + return num_masters; +} + +/******************************************************************************* + * This function validates parameters passed by the platform (in a debug build). + * It collects information about the maximum number of master interfaces that: + * a) the CCN IP can accommodate and + * b) can exist on each Request node. + * It compares this with the information provided by the platform to determine + * the validity of the latter. + ******************************************************************************/ +static void ccn_validate_plat_params(const ccn_desc_t *plat_desc) +{ + unsigned int master_id, num_rn_masters; + rn_info_t info = { {0} }; + + assert(plat_desc); + assert(plat_desc->periphbase); + assert(plat_desc->master_to_rn_id_map); + assert(plat_desc->num_masters); + assert(plat_desc->num_masters < CCN_MAX_RN_MASTERS); + + /* + * Find the number and properties of fully coherent, IO coherent and IO + * coherent + DVM master interfaces + */ + num_rn_masters = ccn_get_rn_master_info(plat_desc->periphbase, &info); + assert(plat_desc->num_masters < num_rn_masters); + + /* + * Iterate through the Request nodes specified by the platform. + * Decrement the count of the masters in the 'info' array for each + * Request node encountered. If the count would drop below 0 then the + * platform's view of this aspect of CCN configuration is incorrect. + */ + for (master_id = 0; master_id < plat_desc->num_masters; master_id++) { + unsigned int node_id; + + node_id = plat_desc->master_to_rn_id_map[master_id]; + assert(node_id < MAX_RN_NODES); + assert(info.node_desc[node_id]); + info.node_desc[node_id]--; + } +} +#endif /* DEBUG */ + +/******************************************************************************* + * This function validates parameters passed by the platform (in a debug build) + * and initialises its internal data structures. A lock is required to prevent + * simultaneous CCN operations at runtime (only BL31) to add and remove Request + * nodes from coherency. + ******************************************************************************/ +void ccn_init(const ccn_desc_t *plat_desc) +{ +#if DEBUG + ccn_validate_plat_params(plat_desc); +#endif + + ccn_plat_desc = plat_desc; +} + +/******************************************************************************* + * This function converts a bit map of master interface IDs to a bit map of the + * Request node IDs that they reside on. + ******************************************************************************/ +static unsigned long long ccn_master_to_rn_id_map(unsigned long long master_map) +{ + unsigned long long rn_id_map = 0; + unsigned int node_id, iface_id; + + assert(master_map); + assert(ccn_plat_desc); + + FOR_EACH_PRESENT_MASTER_INTERFACE(iface_id, master_map) { + + /* Convert the master ID into the node ID */ + node_id = ccn_plat_desc->master_to_rn_id_map[iface_id]; + + /* Set the bit corresponding to this node ID */ + rn_id_map |= (1UL << node_id); + } + + return rn_id_map; +} + +/******************************************************************************* + * This function executes the necessary operations to add or remove Request node + * IDs specified in the 'rn_id_map' bitmap from the snoop/DVM domains specified + * in the 'hn_id_map'. The 'region_id' specifies the ID of the first HN-F/HN-I + * on which the operation should be performed. 'op_reg_offset' specifies the + * type of operation (add/remove). 'stat_reg_offset' specifies the register + * which should be polled to determine if the operation has completed or not. + ******************************************************************************/ +static void ccn_snoop_dvm_do_op(unsigned long long rn_id_map, + unsigned long long hn_id_map, + unsigned int region_id, + unsigned int op_reg_offset, + unsigned int stat_reg_offset) +{ + unsigned int start_region_id; + + assert(ccn_plat_desc); + assert(ccn_plat_desc->periphbase); + +#if IMAGE_BL31 + bakery_lock_get(&ccn_lock); +#endif + start_region_id = region_id; + FOR_EACH_PRESENT_REGION_ID(start_region_id, hn_id_map) { + ccn_reg_write(ccn_plat_desc->periphbase, + start_region_id, + op_reg_offset, + rn_id_map); + } + + start_region_id = region_id; + + FOR_EACH_PRESENT_REGION_ID(start_region_id, hn_id_map) { + WAIT_FOR_DOMAIN_CTRL_OP_COMPLETION(start_region_id, + stat_reg_offset, + op_reg_offset, + rn_id_map); + } + +#if IMAGE_BL31 + bakery_lock_release(&ccn_lock); +#endif +} + +/******************************************************************************* + * This function reads the bitmap of Home nodes on the basis of the + * 'mn_hn_id_reg_offset' parameter from the Miscellaneous node's (MN) + * programmer's view. The MN has a register which carries the bitmap of present + * Home nodes of each type i.e. HN-Fs, HN-Is & HN-Ds. It calls + * 'ccn_snoop_dvm_do_op()' with this information to perform the actual + * operation. + ******************************************************************************/ +static void ccn_snoop_dvm_domain_common(unsigned long long rn_id_map, + unsigned int hn_op_reg_offset, + unsigned int hn_stat_reg_offset, + unsigned int mn_hn_id_reg_offset, + unsigned int hn_region_id) +{ + unsigned long long mn_hn_id_map; + + assert(ccn_plat_desc); + assert(ccn_plat_desc->periphbase); + + mn_hn_id_map = ccn_reg_read(ccn_plat_desc->periphbase, + MN_REGION_ID, + mn_hn_id_reg_offset); + ccn_snoop_dvm_do_op(rn_id_map, + mn_hn_id_map, + hn_region_id, + hn_op_reg_offset, + hn_stat_reg_offset); +} + +/******************************************************************************* + * The following functions provide the boot and runtime API to the platform for + * adding and removing master interfaces from the snoop/DVM domains. A bitmap of + * master interfaces IDs is passed as a parameter. It is converted into a bitmap + * of Request node IDs using the mapping provided by the platform while + * initialising the driver. + * For example, consider a dual cluster system where the clusters have values 0 + * & 1 in the affinity level 1 field of their respective MPIDRs. While + * initialising this driver, the platform provides the mapping between each + * cluster and the corresponding Request node. To add or remove a cluster from + * the snoop and dvm domain, the bit position corresponding to the cluster ID + * should be set in the 'master_iface_map' i.e. to remove both clusters the + * bitmap would equal 0x11. + ******************************************************************************/ +void ccn_enter_snoop_dvm_domain(unsigned long long master_iface_map) +{ + unsigned long long rn_id_map; + + rn_id_map = ccn_master_to_rn_id_map(master_iface_map); + ccn_snoop_dvm_domain_common(rn_id_map, + HNF_SDC_SET_OFFSET, + HNF_SDC_STAT_OFFSET, + MN_HNF_NODEID_OFFSET, + HNF_REGION_ID_START); + + ccn_snoop_dvm_domain_common(rn_id_map, + MN_DDC_SET_OFF, + MN_DDC_STAT_OFFSET, + MN_HNI_NODEID_OFFSET, + MN_REGION_ID); +} + +void ccn_exit_snoop_dvm_domain(unsigned long long master_iface_map) +{ + unsigned long long rn_id_map; + + rn_id_map = ccn_master_to_rn_id_map(master_iface_map); + ccn_snoop_dvm_domain_common(rn_id_map, + HNF_SDC_CLR_OFFSET, + HNF_SDC_STAT_OFFSET, + MN_HNF_NODEID_OFFSET, + HNF_REGION_ID_START); + + ccn_snoop_dvm_domain_common(rn_id_map, + MN_DDC_CLR_OFFSET, + MN_DDC_STAT_OFFSET, + MN_HNI_NODEID_OFFSET, + MN_REGION_ID); +} + +void ccn_enter_dvm_domain(unsigned long long master_iface_map) +{ + unsigned long long rn_id_map; + + rn_id_map = ccn_master_to_rn_id_map(master_iface_map); + ccn_snoop_dvm_domain_common(rn_id_map, + MN_DDC_SET_OFF, + MN_DDC_STAT_OFFSET, + MN_HNI_NODEID_OFFSET, + MN_REGION_ID); +} + +void ccn_exit_dvm_domain(unsigned long long master_iface_map) +{ + unsigned long long rn_id_map; + + rn_id_map = ccn_master_to_rn_id_map(master_iface_map); + ccn_snoop_dvm_domain_common(rn_id_map, + MN_DDC_CLR_OFFSET, + MN_DDC_STAT_OFFSET, + MN_HNI_NODEID_OFFSET, + MN_REGION_ID); +} + +/******************************************************************************* + * This function returns the run mode of all the L3 cache partitions in the + * system. The state is expected to be one of NO_L3, SF_ONLY, L3_HAM or + * L3_FAM. Instead of comparing the states reported by all HN-Fs, the state of + * the first present HN-F node is reported. Since the driver does not export an + * interface to program them seperately, there is no reason to perform this + * check. An HN-F could report that the L3 cache is transitioning from one mode + * to another e.g. HNF_PM_NOL3_2_SFONLY. In this case, the function waits for + * the transition to complete and reports the final state. + ******************************************************************************/ +unsigned int ccn_get_l3_run_mode(void) +{ + unsigned long long hnf_pstate_stat; + + assert(ccn_plat_desc); + assert(ccn_plat_desc->periphbase); + + /* + * Wait for a L3 cache paritition to enter any run mode. The pstate + * parameter is read from an HN-F P-state status register. A non-zero + * value in bits[1:0] means that the cache is transitioning to a run + * mode. + */ + do { + hnf_pstate_stat = ccn_reg_read(ccn_plat_desc->periphbase, + HNF_REGION_ID_START, + HNF_PSTATE_STAT_OFFSET); + } while (hnf_pstate_stat & 0x3); + + return PSTATE_TO_RUN_MODE(hnf_pstate_stat); +} + +/******************************************************************************* + * This function sets the run mode of all the L3 cache partitions in the + * system to one of NO_L3, SF_ONLY, L3_HAM or L3_FAM depending upon the state + * specified by the 'mode' argument. + ******************************************************************************/ +void ccn_set_l3_run_mode(unsigned int mode) +{ + unsigned long long mn_hnf_id_map, hnf_pstate_stat; + unsigned int region_id; + + assert(ccn_plat_desc); + assert(ccn_plat_desc->periphbase); + assert(mode <= CCN_L3_RUN_MODE_FAM); + + mn_hnf_id_map = ccn_reg_read(ccn_plat_desc->periphbase, + MN_REGION_ID, + MN_HNF_NODEID_OFFSET); + region_id = HNF_REGION_ID_START; + + /* Program the desired run mode */ + FOR_EACH_PRESENT_REGION_ID(region_id, mn_hnf_id_map) { + ccn_reg_write(ccn_plat_desc->periphbase, + region_id, + HNF_PSTATE_REQ_OFFSET, + mode); + } + + /* Wait for the caches to transition to the run mode */ + region_id = HNF_REGION_ID_START; + FOR_EACH_PRESENT_REGION_ID(region_id, mn_hnf_id_map) { + /* + * Wait for a L3 cache paritition to enter a target run + * mode. The pstate parameter is read from an HN-F P-state + * status register. + */ + do { + hnf_pstate_stat = ccn_reg_read(ccn_plat_desc->periphbase, + region_id, + HNF_PSTATE_STAT_OFFSET); + } while (((hnf_pstate_stat & HNF_PSTATE_MASK) >> 2) != mode); + } +} + +/******************************************************************************* + * This function configures system address map and provides option to enable the + * 3SN striping mode of Slave node operation. The Slave node IDs and the Top + * Address bit1 and bit0 are provided as parameters to this function. This + * configuration is needed only if network contains a single SN-F or 3 SN-F and + * must be completed before the first request by the system to normal memory. + ******************************************************************************/ +void ccn_program_sys_addrmap(unsigned int sn0_id, + unsigned int sn1_id, + unsigned int sn2_id, + unsigned int top_addr_bit0, + unsigned int top_addr_bit1, + unsigned char three_sn_en) +{ + unsigned long long mn_hnf_id_map, hnf_sam_ctrl_value; + unsigned int region_id; + + assert(ccn_plat_desc); + assert(ccn_plat_desc->periphbase); + + mn_hnf_id_map = ccn_reg_read(ccn_plat_desc->periphbase, + MN_REGION_ID, + MN_HNF_NODEID_OFFSET); + region_id = HNF_REGION_ID_START; + hnf_sam_ctrl_value = MAKE_HNF_SAM_CTRL_VALUE(sn0_id, + sn1_id, + sn2_id, + top_addr_bit0, + top_addr_bit1, + three_sn_en); + + FOR_EACH_PRESENT_REGION_ID(region_id, mn_hnf_id_map) { + + /* Program the SAM control register */ + ccn_reg_write(ccn_plat_desc->periphbase, + region_id, + HNF_SAM_CTRL_OFFSET, + hnf_sam_ctrl_value); + } + +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/ccn/ccn_private.h b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/ccn/ccn_private.h new file mode 100644 index 0000000..e92e870 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/ccn/ccn_private.h @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCN_PRIVATE_H__ +#define __CCN_PRIVATE_H__ + +/* + * A CCN implementation can have a maximum of 64 Request nodes with node IDs + * from 0-63. These IDs are split across the three types of Request nodes + * i.e. RN-F, RN-D and RN-I. + */ +#define MAX_RN_NODES 64 + +/* Enum used to loop through the 3 types of Request nodes */ +typedef enum rn_types { + RN_TYPE_RNF = 0, + RN_TYPE_RNI, + RN_TYPE_RND, + NUM_RN_TYPES +} rn_types_t; + +/* Macro to convert a region id to its base address */ +#define region_id_to_base(id) ((id) << 16) + +/* + * Macro to calculate the number of master interfaces resident on a RN-I/RN-D. + * Value of first two bits of the RN-I/D node type + 1 == Maximum number of + * ACE-Lite or ACE-Lite+DVM interfaces supported on this node. E.g. + * + * 0x14 : RN-I with 1 ACE-Lite interface + * 0x15 : RN-I with 2 ACE-Lite interfaces + * 0x16 : RN-I with 3 ACE-Lite interfaces + */ +#define rn_type_id_to_master_cnt(id) (((id) & 0x3) + 1) + +/* + * Constants used to identify a region in the programmer's view. These are + * common for all regions. + */ +#define REGION_ID_LIMIT 256 +#define REGION_ID_OFFSET 0xFF00 + +#define REGION_NODE_ID_SHIFT 8 +#define REGION_NODE_ID_MASK 0x7f +#define get_node_id(id_reg) (((id_reg) >> REGION_NODE_ID_SHIFT) \ + & REGION_NODE_ID_MASK) + +#define REGION_NODE_TYPE_SHIFT 0 +#define REGION_NODE_TYPE_MASK 0x1f +#define get_node_type(id_reg) (((id_reg) >> REGION_NODE_TYPE_SHIFT) \ + & REGION_NODE_TYPE_MASK) + +/* Common offsets of registers to enter or exit a snoop/dvm domain */ +#define DOMAIN_CTRL_STAT_OFFSET 0x0200 +#define DOMAIN_CTRL_SET_OFFSET 0x0210 +#define DOMAIN_CTRL_CLR_OFFSET 0x0220 + +/* + * Thess macros are used to determine if an operation to add or remove a Request + * node from the snoop/dvm domain has completed. 'rn_id_map' is a bit map of + * nodes. It was used to program the SET or CLEAR control register. The type of + * register is specified by 'op_reg_offset'. 'status_reg' is the bit map of + * nodes currently present in the snoop/dvm domain. 'rn_id_map' and 'status_reg' + * are logically ANDed and the result it stored back in the 'status_reg'. There + * are two outcomes of this operation: + * + * 1. If the DOMAIN_CTRL_SET_OFFSET register was programmed, then the set bits in + * 'rn_id_map' should appear in 'status_reg' when the operation completes. So + * after the AND operation, at some point of time 'status_reg' should equal + * 'rn_id_map'. + * + * 2. If the DOMAIN_CTRL_CLR_OFFSET register was programmed, then the set bits in + * 'rn_id_map' should disappear in 'status_reg' when the operation + * completes. So after the AND operation, at some point of time 'status_reg' + * should equal 0. + */ +#define WAIT_FOR_DOMAIN_CTRL_OP_COMPLETION(region_id, stat_reg_offset, \ + op_reg_offset, rn_id_map) \ + { \ + uint64_t status_reg; \ + do { \ + status_reg = ccn_reg_read((ccn_plat_desc->periphbase), \ + (region_id), \ + (stat_reg_offset)); \ + status_reg &= (rn_id_map); \ + } while ((op_reg_offset) == DOMAIN_CTRL_SET_OFFSET ? \ + (rn_id_map) != status_reg : status_reg); \ + } + +/* + * Region ID of the Miscellaneous Node is always 0 as its located at the base of + * the programmer's view. + */ +#define MN_REGION_ID 0 + +#define MN_REGION_ID_START 0 +#define DEBUG_REGION_ID_START 1 +#define HNI_REGION_ID_START 8 +#define SBSX_REGION_ID_START 16 +#define HNF_REGION_ID_START 32 +#define XP_REGION_ID_START 64 +#define RNI_REGION_ID_START 128 + +/* Selected register offsets from the base of a HNF region */ +#define HNF_CFG_CTRL_OFFSET 0x0000 +#define HNF_SAM_CTRL_OFFSET 0x0008 +#define HNF_PSTATE_REQ_OFFSET 0x0010 +#define HNF_PSTATE_STAT_OFFSET 0x0018 +#define HNF_SDC_STAT_OFFSET DOMAIN_CTRL_STAT_OFFSET +#define HNF_SDC_SET_OFFSET DOMAIN_CTRL_SET_OFFSET +#define HNF_SDC_CLR_OFFSET DOMAIN_CTRL_CLR_OFFSET +#define HNF_AUX_CTRL_OFFSET 0x0500 + +/* Selected register offsets from the base of a MN region */ +#define MN_SAR_OFFSET 0x0000 +#define MN_RNF_NODEID_OFFSET 0x0180 +#define MN_RNI_NODEID_OFFSET 0x0190 +#define MN_RND_NODEID_OFFSET 0x01A0 +#define MN_HNF_NODEID_OFFSET 0x01B0 +#define MN_HNI_NODEID_OFFSET 0x01C0 +#define MN_SN_NODEID_OFFSET 0x01D0 +#define MN_DDC_STAT_OFFSET DOMAIN_CTRL_STAT_OFFSET +#define MN_DDC_SET_OFF DOMAIN_CTRL_SET_OFFSET +#define MN_DDC_CLR_OFFSET DOMAIN_CTRL_CLR_OFFSET +#define MN_ID_OFFSET REGION_ID_OFFSET + +/* HNF System Address Map register bit masks and shifts */ +#define HNF_SAM_CTRL_SN_ID_MASK 0x7f +#define HNF_SAM_CTRL_SN0_ID_SHIFT 0 +#define HNF_SAM_CTRL_SN1_ID_SHIFT 8 +#define HNF_SAM_CTRL_SN2_ID_SHIFT 16 + +#define HNF_SAM_CTRL_TAB0_MASK 0x3fUL +#define HNF_SAM_CTRL_TAB0_SHIFT 48 +#define HNF_SAM_CTRL_TAB1_MASK 0x3fUL +#define HNF_SAM_CTRL_TAB1_SHIFT 56 + +#define HNF_SAM_CTRL_3SN_ENB_SHIFT 32 +#define HNF_SAM_CTRL_3SN_ENB_MASK 0x01UL + +/* + * Macro to create a value suitable for programming into a HNF SAM Control + * register for enabling 3SN striping. + */ +#define MAKE_HNF_SAM_CTRL_VALUE(sn0, sn1, sn2, tab0, tab1, three_sn_en) \ + ((((sn0) & HNF_SAM_CTRL_SN_ID_MASK) << HNF_SAM_CTRL_SN0_ID_SHIFT) | \ + (((sn1) & HNF_SAM_CTRL_SN_ID_MASK) << HNF_SAM_CTRL_SN1_ID_SHIFT) | \ + (((sn2) & HNF_SAM_CTRL_SN_ID_MASK) << HNF_SAM_CTRL_SN2_ID_SHIFT) | \ + (((tab0) & HNF_SAM_CTRL_TAB0_MASK) << HNF_SAM_CTRL_TAB0_SHIFT) | \ + (((tab1) & HNF_SAM_CTRL_TAB1_MASK) << HNF_SAM_CTRL_TAB1_SHIFT) | \ + (((three_sn_en) & HNF_SAM_CTRL_3SN_ENB_MASK) << HNF_SAM_CTRL_3SN_ENB_SHIFT)) + +/* Mask to read the power state value from an HN-F P-state register */ +#define HNF_PSTATE_MASK 0xf + +/* Macro to extract the run mode from a p-state value */ +#define PSTATE_TO_RUN_MODE(pstate) (((pstate) & HNF_PSTATE_MASK) >> 2) + +/* + * Helper macro that iterates through a given bit map. In each iteration, + * it returns the position of the set bit. + * It can be used by other utility macros to iterates through all nodes + * or masters given a bit map of them. + */ +#define FOR_EACH_BIT(bit_pos, bit_map) \ + for (bit_pos = __builtin_ctzll(bit_map); \ + bit_map; \ + bit_map &= ~(1UL << bit_pos), \ + bit_pos = __builtin_ctzll(bit_map)) + +/* + * Utility macro that iterates through a bit map of node IDs. In each + * iteration, it returns the ID of the next present node in the bit map. Node + * ID of a present node == Position of set bit == Number of zeroes trailing the + * bit. + */ +#define FOR_EACH_PRESENT_NODE_ID(node_id, bit_map) \ + FOR_EACH_BIT(node_id, bit_map) + +/* + * Helper function to return number of set bits in bitmap + */ +static inline unsigned int count_set_bits(uint64_t bitmap) +{ + unsigned int count = 0; + + for (; bitmap; bitmap &= bitmap - 1) + ++count; + + return count; +} + +/* + * Utility macro that iterates through a bit map of node IDs. In each iteration, + * it returns the ID of the next present region corresponding to a node present + * in the bit map. Region ID of a present node is in between passed region id + * and region id + number of set bits in the bitmap i.e. the number of present + * nodes. + */ +#define FOR_EACH_PRESENT_REGION_ID(region_id, bit_map) \ + for (unsigned long long region_id_limit = count_set_bits(bit_map) \ + + region_id; \ + region_id < region_id_limit; \ + region_id++) + +/* + * Same macro as FOR_EACH_PRESENT_NODE, but renamed to indicate it traverses + * through a bit map of master interfaces. + */ +#define FOR_EACH_PRESENT_MASTER_INTERFACE(iface_id, bit_map) \ + FOR_EACH_BIT(iface_id, bit_map) +#endif /* __CCN_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/gic/arm_gic.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/gic/arm_gic.c new file mode 100644 index 0000000..ecd5a93 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/gic/arm_gic.c @@ -0,0 +1,455 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Value used to initialize Non-Secure IRQ priorities four at a time */ +#define GICD_IPRIORITYR_DEF_VAL \ + (GIC_HIGHEST_NS_PRIORITY | \ + (GIC_HIGHEST_NS_PRIORITY << 8) | \ + (GIC_HIGHEST_NS_PRIORITY << 16) | \ + (GIC_HIGHEST_NS_PRIORITY << 24)) + +static uintptr_t g_gicc_base; +static uintptr_t g_gicd_base; +static uintptr_t g_gicr_base; +static const unsigned int *g_irq_sec_ptr; +static unsigned int g_num_irqs; + + +/******************************************************************************* + * This function does some minimal GICv3 configuration. The Firmware itself does + * not fully support GICv3 at this time and relies on GICv2 emulation as + * provided by GICv3. This function allows software (like Linux) in later stages + * to use full GICv3 features. + ******************************************************************************/ +static void gicv3_cpuif_setup(void) +{ + unsigned int val; + uintptr_t base; + + /* + * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep + * bit set. In order to allow interrupts to get routed to the CPU we + * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep + * to clear (GICv3 Architecture specification 5.4.23). + * GICR_WAKER is NOT banked per CPU, compute the correct base address + * per CPU. + */ + assert(g_gicr_base); + base = gicv3_get_rdist(g_gicr_base, read_mpidr()); + if (base == (uintptr_t)NULL) { + /* No re-distributor base address. This interface cannot be + * configured. + */ + panic(); + } + + val = gicr_read_waker(base); + + val &= ~WAKER_PS; + gicr_write_waker(base, val); + dsb(); + + /* We need to wait for ChildrenAsleep to clear. */ + val = gicr_read_waker(base); + while (val & WAKER_CA) + val = gicr_read_waker(base); + + val = read_icc_sre_el3(); + write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE); + isb(); +} + +/******************************************************************************* + * This function does some minimal GICv3 configuration when cores go + * down. + ******************************************************************************/ +static void gicv3_cpuif_deactivate(void) +{ + unsigned int val; + uintptr_t base; + + /* + * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and + * wait for GICR_WAKER.ChildrenAsleep to get set. + * (GICv3 Architecture specification 5.4.23). + * GICR_WAKER is NOT banked per CPU, compute the correct base address + * per CPU. + */ + assert(g_gicr_base); + base = gicv3_get_rdist(g_gicr_base, read_mpidr()); + if (base == (uintptr_t)NULL) { + /* No re-distributor base address. This interface cannot be + * configured. + */ + panic(); + } + + val = gicr_read_waker(base); + val |= WAKER_PS; + gicr_write_waker(base, val); + dsb(); + + /* We need to wait for ChildrenAsleep to set. */ + val = gicr_read_waker(base); + while ((val & WAKER_CA) == 0) + val = gicr_read_waker(base); +} + + +/******************************************************************************* + * Enable secure interrupts and use FIQs to route them. Disable legacy bypass + * and set the priority mask register to allow all interrupts to trickle in. + ******************************************************************************/ +void arm_gic_cpuif_setup(void) +{ + unsigned int val; + + assert(g_gicc_base); + val = gicc_read_iidr(g_gicc_base); + + /* + * If GICv3 we need to do a bit of additional setup. We want to + * allow default GICv2 behaviour but allow the next stage to + * enable full gicv3 features. + */ + if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) + gicv3_cpuif_setup(); + + val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0; + val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; + + gicc_write_pmr(g_gicc_base, GIC_PRI_MASK); + gicc_write_ctlr(g_gicc_base, val); +} + +/******************************************************************************* + * Place the cpu interface in a state where it can never make a cpu exit wfi as + * as result of an asserted interrupt. This is critical for powering down a cpu + ******************************************************************************/ +void arm_gic_cpuif_deactivate(void) +{ + unsigned int val; + + /* Disable secure, non-secure interrupts and disable their bypass */ + assert(g_gicc_base); + val = gicc_read_ctlr(g_gicc_base); + val &= ~(ENABLE_GRP0 | ENABLE_GRP1); + val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; + val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; + gicc_write_ctlr(g_gicc_base, val); + + val = gicc_read_iidr(g_gicc_base); + + /* + * If GICv3 we need to do a bit of additional setup. Make sure the + * RDIST is put to sleep. + */ + if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) + gicv3_cpuif_deactivate(); +} + +/******************************************************************************* + * Per cpu gic distributor setup which will be done by all cpus after a cold + * boot/hotplug. This marks out the secure interrupts & enables them. + ******************************************************************************/ +void arm_gic_pcpu_distif_setup(void) +{ + unsigned int index, irq_num, sec_ppi_sgi_mask; + + assert(g_gicd_base); + + /* Setup PPI priorities doing four at a time */ + for (index = 0; index < 32; index += 4) { + gicd_write_ipriorityr(g_gicd_base, index, + GICD_IPRIORITYR_DEF_VAL); + } + + assert(g_irq_sec_ptr); + sec_ppi_sgi_mask = 0; + for (index = 0; index < g_num_irqs; index++) { + irq_num = g_irq_sec_ptr[index]; + if (irq_num < MIN_SPI_ID) { + /* We have an SGI or a PPI. They are Group0 at reset */ + sec_ppi_sgi_mask |= 1U << irq_num; + gicd_set_ipriorityr(g_gicd_base, irq_num, + GIC_HIGHEST_SEC_PRIORITY); + gicd_set_isenabler(g_gicd_base, irq_num); + } + } + + /* + * Invert the bitmask to create a mask for non-secure PPIs and + * SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will + * update the GICR_IGROUPR0 as well in case we are running on a GICv3 + * system. This is critical if GICD_CTLR.ARE_NS=1. + */ + gicd_write_igroupr(g_gicd_base, 0, ~sec_ppi_sgi_mask); +} + +/******************************************************************************* + * Get the current CPU bit mask from GICD_ITARGETSR0 + ******************************************************************************/ +static unsigned int arm_gic_get_cpuif_id(void) +{ + unsigned int val; + + val = gicd_read_itargetsr(g_gicd_base, 0); + return val & GIC_TARGET_CPU_MASK; +} + +/******************************************************************************* + * Global gic distributor setup which will be done by the primary cpu after a + * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It + * then enables the secure GIC distributor interface. + ******************************************************************************/ +static void arm_gic_distif_setup(void) +{ + unsigned int num_ints, ctlr, index, irq_num; + uint8_t target_cpu; + + /* Disable the distributor before going further */ + assert(g_gicd_base); + ctlr = gicd_read_ctlr(g_gicd_base); + ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1); + gicd_write_ctlr(g_gicd_base, ctlr); + + /* + * Mark out non-secure SPI interrupts. The number of interrupts is + * calculated as 32 * (IT_LINES + 1). We do 32 at a time. + */ + num_ints = gicd_read_typer(g_gicd_base) & IT_LINES_NO_MASK; + num_ints = (num_ints + 1) << 5; + for (index = MIN_SPI_ID; index < num_ints; index += 32) + gicd_write_igroupr(g_gicd_base, index, ~0); + + /* Setup SPI priorities doing four at a time */ + for (index = MIN_SPI_ID; index < num_ints; index += 4) { + gicd_write_ipriorityr(g_gicd_base, index, + GICD_IPRIORITYR_DEF_VAL); + } + + /* Read the target CPU mask */ + target_cpu = arm_gic_get_cpuif_id(); + + /* Configure SPI secure interrupts now */ + assert(g_irq_sec_ptr); + for (index = 0; index < g_num_irqs; index++) { + irq_num = g_irq_sec_ptr[index]; + if (irq_num >= MIN_SPI_ID) { + /* We have an SPI */ + gicd_clr_igroupr(g_gicd_base, irq_num); + gicd_set_ipriorityr(g_gicd_base, irq_num, + GIC_HIGHEST_SEC_PRIORITY); + gicd_set_itargetsr(g_gicd_base, irq_num, target_cpu); + gicd_set_isenabler(g_gicd_base, irq_num); + } + } + + /* + * Configure the SGI and PPI. This is done in a separated function + * because each CPU is responsible for initializing its own private + * interrupts. + */ + arm_gic_pcpu_distif_setup(); + + gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0); +} + +/******************************************************************************* + * Initialize the ARM GIC driver with the provided platform inputs +******************************************************************************/ +void arm_gic_init(uintptr_t gicc_base, + uintptr_t gicd_base, + uintptr_t gicr_base, + const unsigned int *irq_sec_ptr, + unsigned int num_irqs) +{ + unsigned int val; + + assert(gicc_base); + assert(gicd_base); + assert(irq_sec_ptr); + + g_gicc_base = gicc_base; + g_gicd_base = gicd_base; + + val = gicc_read_iidr(g_gicc_base); + + if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) { + assert(gicr_base); + g_gicr_base = gicr_base; + } + + g_irq_sec_ptr = irq_sec_ptr; + g_num_irqs = num_irqs; +} + +/******************************************************************************* + * Setup the ARM GIC CPU and distributor interfaces. +******************************************************************************/ +void arm_gic_setup(void) +{ + arm_gic_cpuif_setup(); + arm_gic_distif_setup(); +} + +/******************************************************************************* + * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. + * The interrupt controller knows which pin/line it uses to signal a type of + * interrupt. This function provides a common implementation of + * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use + * across platforms. It lets the interrupt management framework determine + * for a type of interrupt and security state, which line should be used in the + * SCR_EL3 to control its routing to EL3. The interrupt line is represented as + * the bit position of the IRQ or FIQ bit in the SCR_EL3. + ******************************************************************************/ +uint32_t arm_gic_interrupt_type_to_line(uint32_t type, + uint32_t security_state) +{ + assert(type == INTR_TYPE_S_EL1 || + type == INTR_TYPE_EL3 || + type == INTR_TYPE_NS); + + assert(sec_state_is_valid(security_state)); + + /* + * We ignore the security state parameter under the assumption that + * both normal and secure worlds are using ARM GICv2. This parameter + * will be used when the secure world starts using GICv3. + */ +#if ARM_GIC_ARCH == 2 + return gicv2_interrupt_type_to_line(g_gicc_base, type); +#else +#error "Invalid ARM GIC architecture version specified for platform port" +#endif /* ARM_GIC_ARCH */ +} + +#if ARM_GIC_ARCH == 2 +/******************************************************************************* + * This function returns the type of the highest priority pending interrupt at + * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no + * interrupt pending. + ******************************************************************************/ +uint32_t arm_gic_get_pending_interrupt_type(void) +{ + uint32_t id; + + assert(g_gicc_base); + id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK; + + /* Assume that all secure interrupts are S-EL1 interrupts */ + if (id < 1022) + return INTR_TYPE_S_EL1; + + if (id == GIC_SPURIOUS_INTERRUPT) + return INTR_TYPE_INVAL; + + return INTR_TYPE_NS; +} + +/******************************************************************************* + * This function returns the id of the highest priority pending interrupt at + * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no + * interrupt pending. + ******************************************************************************/ +uint32_t arm_gic_get_pending_interrupt_id(void) +{ + uint32_t id; + + assert(g_gicc_base); + id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK; + + if (id < 1022) + return id; + + if (id == 1023) + return INTR_ID_UNAVAILABLE; + + /* + * Find out which non-secure interrupt it is under the assumption that + * the GICC_CTLR.AckCtl bit is 0. + */ + return gicc_read_ahppir(g_gicc_base) & INT_ID_MASK; +} + +/******************************************************************************* + * This functions reads the GIC cpu interface Interrupt Acknowledge register + * to start handling the pending interrupt. It returns the contents of the IAR. + ******************************************************************************/ +uint32_t arm_gic_acknowledge_interrupt(void) +{ + assert(g_gicc_base); + return gicc_read_IAR(g_gicc_base); +} + +/******************************************************************************* + * This functions writes the GIC cpu interface End Of Interrupt register with + * the passed value to finish handling the active interrupt + ******************************************************************************/ +void arm_gic_end_of_interrupt(uint32_t id) +{ + assert(g_gicc_base); + gicc_write_EOIR(g_gicc_base, id); +} + +/******************************************************************************* + * This function returns the type of the interrupt id depending upon the group + * this interrupt has been configured under by the interrupt controller i.e. + * group0 or group1. + ******************************************************************************/ +uint32_t arm_gic_get_interrupt_type(uint32_t id) +{ + uint32_t group; + + assert(g_gicd_base); + group = gicd_get_igroupr(g_gicd_base, id); + + /* Assume that all secure interrupts are S-EL1 interrupts */ + if (group == GRP0) + return INTR_TYPE_S_EL1; + else + return INTR_TYPE_NS; +} + +#else +#error "Invalid ARM GIC architecture version specified for platform port" +#endif /* ARM_GIC_ARCH */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/gic/gic_v2.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/gic/gic_v2.c new file mode 100644 index 0000000..dc5dc08 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/gic/gic_v2.c @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/******************************************************************************* + * GIC Distributor interface accessors for reading entire registers + ******************************************************************************/ + +unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> IGROUPR_SHIFT; + return mmio_read_32(base + GICD_IGROUPR + (n << 2)); +} + +unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ISENABLER_SHIFT; + return mmio_read_32(base + GICD_ISENABLER + (n << 2)); +} + +unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICENABLER_SHIFT; + return mmio_read_32(base + GICD_ICENABLER + (n << 2)); +} + +unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ISPENDR_SHIFT; + return mmio_read_32(base + GICD_ISPENDR + (n << 2)); +} + +unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICPENDR_SHIFT; + return mmio_read_32(base + GICD_ICPENDR + (n << 2)); +} + +unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ISACTIVER_SHIFT; + return mmio_read_32(base + GICD_ISACTIVER + (n << 2)); +} + +unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICACTIVER_SHIFT; + return mmio_read_32(base + GICD_ICACTIVER + (n << 2)); +} + +unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> IPRIORITYR_SHIFT; + return mmio_read_32(base + GICD_IPRIORITYR + (n << 2)); +} + +unsigned int gicd_read_itargetsr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ITARGETSR_SHIFT; + return mmio_read_32(base + GICD_ITARGETSR + (n << 2)); +} + +unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICFGR_SHIFT; + return mmio_read_32(base + GICD_ICFGR + (n << 2)); +} + +unsigned int gicd_read_cpendsgir(uintptr_t base, unsigned int id) +{ + unsigned n = id >> CPENDSGIR_SHIFT; + return mmio_read_32(base + GICD_CPENDSGIR + (n << 2)); +} + +unsigned int gicd_read_spendsgir(uintptr_t base, unsigned int id) +{ + unsigned n = id >> SPENDSGIR_SHIFT; + return mmio_read_32(base + GICD_SPENDSGIR + (n << 2)); +} + +/******************************************************************************* + * GIC Distributor interface accessors for writing entire registers + ******************************************************************************/ + +void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> IGROUPR_SHIFT; + mmio_write_32(base + GICD_IGROUPR + (n << 2), val); +} + +void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISENABLER_SHIFT; + mmio_write_32(base + GICD_ISENABLER + (n << 2), val); +} + +void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICENABLER_SHIFT; + mmio_write_32(base + GICD_ICENABLER + (n << 2), val); +} + +void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISPENDR_SHIFT; + mmio_write_32(base + GICD_ISPENDR + (n << 2), val); +} + +void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICPENDR_SHIFT; + mmio_write_32(base + GICD_ICPENDR + (n << 2), val); +} + +void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISACTIVER_SHIFT; + mmio_write_32(base + GICD_ISACTIVER + (n << 2), val); +} + +void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICACTIVER_SHIFT; + mmio_write_32(base + GICD_ICACTIVER + (n << 2), val); +} + +void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> IPRIORITYR_SHIFT; + mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val); +} + +void gicd_write_itargetsr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ITARGETSR_SHIFT; + mmio_write_32(base + GICD_ITARGETSR + (n << 2), val); +} + +void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICFGR_SHIFT; + mmio_write_32(base + GICD_ICFGR + (n << 2), val); +} + +void gicd_write_cpendsgir(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> CPENDSGIR_SHIFT; + mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val); +} + +void gicd_write_spendsgir(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> SPENDSGIR_SHIFT; + mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val); +} + +/******************************************************************************* + * GIC Distributor interface accessors for individual interrupt manipulation + ******************************************************************************/ +unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + return (reg_val >> bit_num) & 0x1; +} + +void gicd_set_igroupr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + gicd_write_igroupr(base, id, reg_val | (1 << bit_num)); +} + +void gicd_clr_igroupr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num)); +} + +void gicd_set_isenabler(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); + + gicd_write_isenabler(base, id, (1 << bit_num)); +} + +void gicd_set_icenabler(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1); + + gicd_write_icenabler(base, id, (1 << bit_num)); +} + +void gicd_set_ispendr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1); + + gicd_write_ispendr(base, id, (1 << bit_num)); +} + +void gicd_set_icpendr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1); + + gicd_write_icpendr(base, id, (1 << bit_num)); +} + +void gicd_set_isactiver(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1); + + gicd_write_isactiver(base, id, (1 << bit_num)); +} + +void gicd_set_icactiver(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1); + + gicd_write_icactiver(base, id, (1 << bit_num)); +} + +/* + * Make sure that the interrupt's group is set before expecting + * this function to do its job correctly. + */ +void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) +{ + unsigned int reg = base + GICD_IPRIORITYR + (id & ~3); + unsigned int shift = (id & 3) << 3; + unsigned int reg_val = mmio_read_32(reg); + + /* + * Enforce ARM recommendation to manage priority values such + * that group1 interrupts always have a lower priority than + * group0 interrupts. + * Note, lower numerical values are higher priorities so the comparison + * checks below are reversed from what might be expected. + */ + assert(gicd_get_igroupr(base, id) == GRP1 ? + pri >= GIC_HIGHEST_NS_PRIORITY && + pri <= GIC_LOWEST_NS_PRIORITY : + pri >= GIC_HIGHEST_SEC_PRIORITY && + pri <= GIC_LOWEST_SEC_PRIORITY); + + reg_val &= ~(GIC_PRI_MASK << shift); + reg_val |= (pri & GIC_PRI_MASK) << shift; + mmio_write_32(reg, reg_val); +} + +void gicd_set_itargetsr(uintptr_t base, unsigned int id, unsigned int target) +{ + unsigned byte_off = id & ((1 << ITARGETSR_SHIFT) - 1); + unsigned int reg_val = gicd_read_itargetsr(base, id); + + gicd_write_itargetsr(base, id, reg_val | (target << (byte_off << 3))); +} + +/******************************************************************************* + * This function allows the interrupt management framework to determine (through + * the platform) which interrupt line (IRQ/FIQ) to use for an interrupt type to + * route it to EL3. The interrupt line is represented as the bit position of the + * IRQ or FIQ bit in the SCR_EL3. + ******************************************************************************/ +uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type) +{ + uint32_t gicc_ctlr; + + /* Non-secure interrupts are signalled on the IRQ line always */ + if (type == INTR_TYPE_NS) + return __builtin_ctz(SCR_IRQ_BIT); + + /* + * Secure interrupts are signalled using the IRQ line if the FIQ_EN + * bit is not set else they are signalled using the FIQ line. + */ + gicc_ctlr = gicc_read_ctlr(cpuif_base); + if (gicc_ctlr & FIQ_EN) + return __builtin_ctz(SCR_FIQ_BIT); + else + return __builtin_ctz(SCR_IRQ_BIT); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/gic/gic_v3.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/gic/gic_v3.c new file mode 100644 index 0000000..f429662 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/gic/gic_v3.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr) +{ + uint32_t cpu_aff, gicr_aff; + uint64_t gicr_typer; + uintptr_t addr; + + /* Construct the affinity as used by GICv3. MPIDR and GIC affinity level + * mask is the same. + */ + cpu_aff = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF0_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF1_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF2_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF3_SHIFT; + + addr = gicr_base; + do { + gicr_typer = gicr_read_typer(addr); + + gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) & + GICR_TYPER_AFF_MASK; + if (cpu_aff == gicr_aff) { + /* Disable this print for now as it appears every time + * when using PSCI CPU_SUSPEND. + * TODO: Print this only the first time for each CPU. + * INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at 0x%lx\n", + * mpidr, addr); + */ + return addr; + } + + /* TODO: + * For GICv4 we need to adjust the Base address based on + * GICR_TYPER.VLPIS + */ + addr += (1 << GICR_PCPUBASE_SHIFT); + + } while (!(gicr_typer & GICR_TYPER_LAST)); + + /* If we get here we did not find a match. */ + ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr); + return (uintptr_t)NULL; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/pl011/pl011_console.S b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/pl011/pl011_console.S new file mode 100644 index 0000000..ea41e5d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/pl011/pl011_console.S @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +/* + * Pull in generic functions to provide backwards compatibility for + * platform makefiles + */ +#include "../../console/console.S" + + + .globl console_core_init + .globl console_core_putc + .globl console_core_getc + + + /* ----------------------------------------------- + * int console_core_init(uintptr_t base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * Out: return 1 on success else 0 on error + * Clobber list : x1, x2 + * ----------------------------------------------- + */ +func console_core_init + /* Check the input base address */ + cbz x0, core_init_fail + /* Check baud rate and uart clock for sanity */ + cbz w1, core_init_fail + cbz w2, core_init_fail + /* Program the baudrate */ + /* Divisor = (Uart clock * 4) / baudrate */ + lsl w1, w1, #2 + udiv w2, w1, w2 + /* IBRD = Divisor >> 6 */ + lsr w1, w2, #6 + /* Write the IBRD */ + str w1, [x0, #UARTIBRD] + /* FBRD = Divisor & 0x3F */ + and w1, w2, #0x3f + /* Write the FBRD */ + str w1, [x0, #UARTFBRD] + mov w1, #PL011_LINE_CONTROL + str w1, [x0, #UARTLCR_H] + /* Clear any pending errors */ + str wzr, [x0, #UARTECR] + /* Enable tx, rx, and uart overall */ + mov w1, #(PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN) + str w1, [x0, #UARTCR] + mov w0, #1 + ret +core_init_fail: + mov w0, wzr + ret +endfunc console_core_init + + /* -------------------------------------------------------- + * int console_core_putc(int c, uintptr_t base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_core_putc + /* Check the input parameter */ + cbz x1, putc_error + /* Prepend '\r' to '\n' */ + cmp w0, #0xA + b.ne 2f +1: + /* Check if the transmit FIFO is full */ + ldr w2, [x1, #UARTFR] + tbnz w2, #PL011_UARTFR_TXFF_BIT, 1b + mov w2, #0xD + str w2, [x1, #UARTDR] +2: + /* Check if the transmit FIFO is full */ + ldr w2, [x1, #UARTFR] + tbnz w2, #PL011_UARTFR_TXFF_BIT, 2b + str w0, [x1, #UARTDR] + ret +putc_error: + mov w0, #-1 + ret +endfunc console_core_putc + + /* --------------------------------------------- + * int console_core_getc(uintptr_t base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * In : x0 - console base address + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_getc + cbz x0, getc_error +1: + /* Check if the receive FIFO is empty */ + ldr w1, [x0, #UARTFR] + tbnz w1, #PL011_UARTFR_RXFE_BIT, 1b + ldr w1, [x0, #UARTDR] + mov w0, w1 + ret +getc_error: + mov w0, #-1 + ret +endfunc console_core_getc diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/sp804/sp804_delay_timer.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/sp804/sp804_delay_timer.c new file mode 100644 index 0000000..78940bf --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/sp804/sp804_delay_timer.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +uintptr_t sp804_base_addr; + +#define SP804_TIMER1_LOAD (sp804_base_addr + 0x000) +#define SP804_TIMER1_VALUE (sp804_base_addr + 0x004) +#define SP804_TIMER1_CONTROL (sp804_base_addr + 0x008) +#define SP804_TIMER1_BGLOAD (sp804_base_addr + 0x018) + +#define TIMER_CTRL_ONESHOT (1 << 0) +#define TIMER_CTRL_32BIT (1 << 1) +#define TIMER_CTRL_DIV1 (0 << 2) +#define TIMER_CTRL_DIV16 (1 << 2) +#define TIMER_CTRL_DIV256 (2 << 2) +#define TIMER_CTRL_IE (1 << 5) +#define TIMER_CTRL_PERIODIC (1 << 6) +#define TIMER_CTRL_ENABLE (1 << 7) + +/******************************************************************** + * The SP804 timer delay function + ********************************************************************/ +uint32_t sp804_get_timer_value(void) +{ + return mmio_read_32(SP804_TIMER1_VALUE); +} + +/******************************************************************** + * Initialize the 1st timer in the SP804 dual timer with a base + * address and a timer ops + ********************************************************************/ +void sp804_timer_ops_init(uintptr_t base_addr, const timer_ops_t *ops) +{ + assert(base_addr != 0); + assert(ops != 0 && ops->get_timer_value == sp804_get_timer_value); + + sp804_base_addr = base_addr; + timer_init(ops); + + /* disable timer1 */ + mmio_write_32(SP804_TIMER1_CONTROL, 0); + mmio_write_32(SP804_TIMER1_LOAD, UINT32_MAX); + mmio_write_32(SP804_TIMER1_VALUE, UINT32_MAX); + + /* enable as a free running 32-bit counter */ + mmio_write_32(SP804_TIMER1_CONTROL, + TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/tzc400/tzc400.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/tzc400/tzc400.c new file mode 100644 index 0000000..4b72a2b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/arm/tzc400/tzc400.c @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/* + * Implementation defined values used to validate inputs later. + * Filters : max of 4 ; 0 to 3 + * Regions : max of 9 ; 0 to 8 + * Address width : Values between 32 to 64 + */ +typedef struct tzc_instance { + uintptr_t base; + uint8_t addr_width; + uint8_t num_filters; + uint8_t num_regions; +} tzc_instance_t; + +tzc_instance_t tzc; + + +static inline uint32_t tzc_read_build_config(uintptr_t base) +{ + return mmio_read_32(base + BUILD_CONFIG_OFF); +} + +static inline uint32_t tzc_read_gate_keeper(uintptr_t base) +{ + return mmio_read_32(base + GATE_KEEPER_OFF); +} + +static inline void tzc_write_gate_keeper(uintptr_t base, uint32_t val) +{ + mmio_write_32(base + GATE_KEEPER_OFF, val); +} + +static inline void tzc_write_action(uintptr_t base, tzc_action_t action) +{ + mmio_write_32(base + ACTION_OFF, action); +} + +static inline void tzc_write_region_base_low(uintptr_t base, + uint32_t region, + uint32_t val) +{ + mmio_write_32(base + REGION_BASE_LOW_OFF + + REGION_NUM_OFF(region), val); +} + +static inline void tzc_write_region_base_high(uintptr_t base, + uint32_t region, + uint32_t val) +{ + mmio_write_32(base + REGION_BASE_HIGH_OFF + + REGION_NUM_OFF(region), val); +} + +static inline void tzc_write_region_top_low(uintptr_t base, + uint32_t region, + uint32_t val) +{ + mmio_write_32(base + REGION_TOP_LOW_OFF + + REGION_NUM_OFF(region), val); +} + +static inline void tzc_write_region_top_high(uintptr_t base, + uint32_t region, + uint32_t val) +{ + mmio_write_32(base + REGION_TOP_HIGH_OFF + + REGION_NUM_OFF(region), val); +} + +static inline void tzc_write_region_attributes(uintptr_t base, + uint32_t region, + uint32_t val) +{ + mmio_write_32(base + REGION_ATTRIBUTES_OFF + + REGION_NUM_OFF(region), val); +} + +static inline void tzc_write_region_id_access(uintptr_t base, + uint32_t region, + uint32_t val) +{ + mmio_write_32(base + REGION_ID_ACCESS_OFF + + REGION_NUM_OFF(region), val); +} + +static uint32_t tzc_read_component_id(uintptr_t base) +{ + uint32_t id; + + id = mmio_read_8(base + CID0_OFF); + id |= (mmio_read_8(base + CID1_OFF) << 8); + id |= (mmio_read_8(base + CID2_OFF) << 16); + id |= (mmio_read_8(base + CID3_OFF) << 24); + + return id; +} + +static uint32_t tzc_get_gate_keeper(uintptr_t base, uint8_t filter) +{ + uint32_t tmp; + + tmp = (tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) & + GATE_KEEPER_OS_MASK; + + return (tmp >> filter) & GATE_KEEPER_FILTER_MASK; +} + +/* This function is not MP safe. */ +static void tzc_set_gate_keeper(uintptr_t base, uint8_t filter, uint32_t val) +{ + uint32_t tmp; + + /* Upper half is current state. Lower half is requested state. */ + tmp = (tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) & + GATE_KEEPER_OS_MASK; + + if (val) + tmp |= (1 << filter); + else + tmp &= ~(1 << filter); + + tzc_write_gate_keeper(base, (tmp & GATE_KEEPER_OR_MASK) << + GATE_KEEPER_OR_SHIFT); + + /* Wait here until we see the change reflected in the TZC status. */ + while (((tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) & + GATE_KEEPER_OS_MASK) != tmp) + ; +} + + +void tzc_init(uintptr_t base) +{ + uint32_t tzc_id, tzc_build; + + assert(base); + tzc.base = base; + + /* + * We expect to see a tzc400. Check component ID. The TZC-400 TRM shows + * component ID is expected to be "0xB105F00D". + */ + tzc_id = tzc_read_component_id(tzc.base); + if (tzc_id != TZC400_COMPONENT_ID) { + ERROR("TZC : Wrong device ID (0x%x).\n", tzc_id); + panic(); + } + + /* Save values we will use later. */ + tzc_build = tzc_read_build_config(tzc.base); + tzc.num_filters = ((tzc_build >> BUILD_CONFIG_NF_SHIFT) & + BUILD_CONFIG_NF_MASK) + 1; + tzc.addr_width = ((tzc_build >> BUILD_CONFIG_AW_SHIFT) & + BUILD_CONFIG_AW_MASK) + 1; + tzc.num_regions = ((tzc_build >> BUILD_CONFIG_NR_SHIFT) & + BUILD_CONFIG_NR_MASK) + 1; +} + +/* + * `tzc_configure_region0` is used to program region 0 into the TrustZone + * controller. Region 0 covers the whole address space that is not mapped + * to any other region, and is enabled on all filters; this cannot be + * changed. This function only changes the access permissions. + */ +void tzc_configure_region0(tzc_region_attributes_t sec_attr, + uint32_t ns_device_access) +{ + assert(tzc.base); + + VERBOSE("TZC : Configuring region 0 (sec_attr=0x%x, ns_devs=0x%x)\n", + sec_attr, ns_device_access); + + assert(sec_attr <= TZC_REGION_S_RDWR); + + /* Set secure attributes on region 0 */ + tzc_write_region_attributes(tzc.base, 0, + sec_attr << REG_ATTR_SEC_SHIFT); + + /* + * Specify which non-secure devices have permission to access + * region 0. + */ + tzc_write_region_id_access(tzc.base, 0, ns_device_access); +} + + +/* + * `tzc_configure_region` is used to program regions into the TrustZone + * controller. A region can be associated with more than one filter. The + * associated filters are passed in as a bitmap (bit0 = filter0). + * NOTE: + * Region 0 is special; it is preferable to use tzc_configure_region0 + * for this region (see comment for that function). + */ +void tzc_configure_region(uint32_t filters, + uint8_t region, + uint64_t region_base, + uint64_t region_top, + tzc_region_attributes_t sec_attr, + uint32_t ns_device_access) +{ + assert(tzc.base); + + VERBOSE("TZC : Configuring region (filters=0x%x, region=%d, ...\n", + filters, region); + VERBOSE("TZC : ... base=0x%lx, top=0x%lx, ...\n", + region_base, region_top); + VERBOSE("TZC : ... sec_attr=0x%x, ns_devs=0x%x)\n", + sec_attr, ns_device_access); + + /* Do range checks on filters and regions. */ + assert(((filters >> tzc.num_filters) == 0) && + (region < tzc.num_regions)); + + /* + * Do address range check based on TZC configuration. A 64bit address is + * the max and expected case. + */ + assert(((region_top <= (UINT64_MAX >> (64 - tzc.addr_width))) && + (region_base < region_top))); + + /* region_base and (region_top + 1) must be 4KB aligned */ + assert(((region_base | (region_top + 1)) & (4096 - 1)) == 0); + + assert(sec_attr <= TZC_REGION_S_RDWR); + + /* + * Inputs look ok, start programming registers. + * All the address registers are 32 bits wide and have a LOW and HIGH + * component used to construct a up to a 64bit address. + */ + tzc_write_region_base_low(tzc.base, region, + (uint32_t)(region_base)); + tzc_write_region_base_high(tzc.base, region, + (uint32_t)(region_base >> 32)); + + tzc_write_region_top_low(tzc.base, region, + (uint32_t)(region_top)); + tzc_write_region_top_high(tzc.base, region, + (uint32_t)(region_top >> 32)); + + /* Assign the region to a filter and set secure attributes */ + tzc_write_region_attributes(tzc.base, region, + (sec_attr << REG_ATTR_SEC_SHIFT) | filters); + + /* + * Specify which non-secure devices have permission to access this + * region. + */ + tzc_write_region_id_access(tzc.base, region, ns_device_access); +} + + +void tzc_set_action(tzc_action_t action) +{ + assert(tzc.base); + + /* + * - Currently no handler is provided to trap an error via interrupt + * or exception. + * - The interrupt action has not been tested. + */ + tzc_write_action(tzc.base, action); +} + + +void tzc_enable_filters(void) +{ + uint32_t state; + uint32_t filter; + + assert(tzc.base); + + for (filter = 0; filter < tzc.num_filters; filter++) { + state = tzc_get_gate_keeper(tzc.base, filter); + if (state) { + /* The TZC filter is already configured. Changing the + * programmer's view in an active system can cause + * unpredictable behavior therefore panic for now rather + * than try to determine whether this is safe in this + * instance. See: + * http://infocenter.arm.com/help/index.jsp?\ + * topic=/com.arm.doc.ddi0504c/CJHHECBF.html */ + ERROR("TZC : Filter %d Gatekeeper already enabled.\n", + filter); + panic(); + } + tzc_set_gate_keeper(tzc.base, filter, 1); + } +} + + +void tzc_disable_filters(void) +{ + uint32_t filter; + + assert(tzc.base); + + /* + * We don't do the same state check as above as the Gatekeepers are + * disabled after reset. + */ + for (filter = 0; filter < tzc.num_filters; filter++) + tzc_set_gate_keeper(tzc.base, filter, 0); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/auth_mod.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/auth_mod.c new file mode 100644 index 0000000..bdd3c5a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/auth_mod.c @@ -0,0 +1,348 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define return_if_error(rc) \ + do { \ + if (rc != 0) { \ + return rc; \ + } \ + } while (0) + +/* Pointer to CoT */ +extern const auth_img_desc_t *const cot_desc_ptr; +extern unsigned int auth_img_flags[]; + +static int cmp_auth_param_type_desc(const auth_param_type_desc_t *a, + const auth_param_type_desc_t *b) +{ + if ((a->type == b->type) && (a->cookie == b->cookie)) { + return 0; + } + return 1; +} + +/* + * This function obtains the requested authentication parameter data from the + * information extracted from the parent image after its authentication. + */ +static int auth_get_param(const auth_param_type_desc_t *param_type_desc, + const auth_img_desc_t *img_desc, + void **param, unsigned int *len) +{ + int i; + + for (i = 0 ; i < COT_MAX_VERIFIED_PARAMS ; i++) { + if (0 == cmp_auth_param_type_desc(param_type_desc, + img_desc->authenticated_data[i].type_desc)) { + *param = img_desc->authenticated_data[i].data.ptr; + *len = img_desc->authenticated_data[i].data.len; + return 0; + } + } + + return 1; +} + +/* + * Authenticate an image by matching the data hash + * + * This function implements 'AUTH_METHOD_HASH'. To authenticate an image using + * this method, the image must contain: + * + * - The data to calculate the hash from + * + * The parent image must contain: + * + * - The hash to be matched with (including hash algorithm) + * + * For a successful authentication, both hashes must match. The function calls + * the crypto-module to check this matching. + * + * Parameters: + * param: parameters to perform the hash authentication + * img_desc: pointer to image descriptor so we can know the image type + * and parent image + * img: pointer to image in memory + * img_len: length of image (in bytes) + * + * Return: + * 0 = success, Otherwise = error + */ +static int auth_hash(const auth_method_param_hash_t *param, + const auth_img_desc_t *img_desc, + void *img, unsigned int img_len) +{ + void *data_ptr, *hash_der_ptr; + unsigned int data_len, hash_der_len; + int rc = 0; + + /* Get the hash from the parent image. This hash will be DER encoded + * and contain the hash algorithm */ + rc = auth_get_param(param->hash, img_desc->parent, + &hash_der_ptr, &hash_der_len); + return_if_error(rc); + + /* Get the data to be hashed from the current image */ + rc = img_parser_get_auth_param(img_desc->img_type, param->data, + img, img_len, &data_ptr, &data_len); + return_if_error(rc); + + /* Ask the crypto module to verify this hash */ + rc = crypto_mod_verify_hash(data_ptr, data_len, + hash_der_ptr, hash_der_len); + + return rc; +} + +/* + * Authenticate by digital signature + * + * This function implements 'AUTH_METHOD_SIG'. To authenticate an image using + * this method, the image must contain: + * + * - Data to be signed + * - Signature + * - Signature algorithm + * + * We rely on the image parser module to extract this data from the image. + * The parent image must contain: + * + * - Public key (or a hash of it) + * + * If the parent image contains only a hash of the key, we will try to obtain + * the public key from the image itself (i.e. self-signed certificates). In that + * case, the signature verification is considered just an integrity check and + * the authentication is established by calculating the hash of the key and + * comparing it with the hash obtained from the parent. + * + * If the image has no parent (NULL), it means it has to be authenticated using + * the ROTPK stored in the platform. Again, this ROTPK could be the key itself + * or a hash of it. + * + * Return: 0 = success, Otherwise = error + */ +static int auth_signature(const auth_method_param_sig_t *param, + const auth_img_desc_t *img_desc, + void *img, unsigned int img_len) +{ + void *data_ptr, *pk_ptr, *pk_hash_ptr, *sig_ptr, *sig_alg_ptr; + unsigned int data_len, pk_len, pk_hash_len, sig_len, sig_alg_len; + unsigned int flags = 0; + int rc = 0; + + /* Get the data to be signed from current image */ + rc = img_parser_get_auth_param(img_desc->img_type, param->data, + img, img_len, &data_ptr, &data_len); + return_if_error(rc); + + /* Get the signature from current image */ + rc = img_parser_get_auth_param(img_desc->img_type, param->sig, + img, img_len, &sig_ptr, &sig_len); + return_if_error(rc); + + /* Get the signature algorithm from current image */ + rc = img_parser_get_auth_param(img_desc->img_type, param->alg, + img, img_len, &sig_alg_ptr, &sig_alg_len); + return_if_error(rc); + + /* Get the public key from the parent. If there is no parent (NULL), + * the certificate has been signed with the ROTPK, so we have to get + * the PK from the platform */ + if (img_desc->parent) { + rc = auth_get_param(param->pk, img_desc->parent, + &pk_ptr, &pk_len); + } else { + rc = plat_get_rotpk_info(param->pk->cookie, &pk_ptr, &pk_len, + &flags); + } + return_if_error(rc); + + /* If the PK is a hash of the key, retrieve the key from the image */ + if (flags & ROTPK_IS_HASH) { + pk_hash_ptr = pk_ptr; + pk_hash_len = pk_len; + rc = img_parser_get_auth_param(img_desc->img_type, + param->pk, img, img_len, + &pk_ptr, &pk_len); + return_if_error(rc); + + /* Ask the crypto module to verify the signature */ + rc = crypto_mod_verify_signature(data_ptr, data_len, + sig_ptr, sig_len, + sig_alg_ptr, sig_alg_len, + pk_ptr, pk_len); + return_if_error(rc); + + /* Ask the crypto-module to verify the key hash */ + rc = crypto_mod_verify_hash(pk_ptr, pk_len, + pk_hash_ptr, pk_hash_len); + } else { + /* Ask the crypto module to verify the signature */ + rc = crypto_mod_verify_signature(data_ptr, data_len, + sig_ptr, sig_len, + sig_alg_ptr, sig_alg_len, + pk_ptr, pk_len); + } + + return rc; +} + +/* + * Return the parent id in the output parameter '*parent_id' + * + * Return value: + * 0 = Image has parent, 1 = Image has no parent or parent is authenticated + */ +int auth_mod_get_parent_id(unsigned int img_id, unsigned int *parent_id) +{ + const auth_img_desc_t *img_desc = NULL; + + assert(parent_id != NULL); + + /* Get the image descriptor */ + img_desc = &cot_desc_ptr[img_id]; + + /* Check if the image has no parent (ROT) */ + if (img_desc->parent == NULL) { + *parent_id = 0; + return 1; + } + + /* Check if the parent has already been authenticated */ + if (auth_img_flags[img_desc->parent->img_id] & IMG_FLAG_AUTHENTICATED) { + *parent_id = 0; + return 1; + } + + *parent_id = img_desc->parent->img_id; + return 0; +} + +/* + * Initialize the different modules in the authentication framework + */ +void auth_mod_init(void) +{ + /* Check we have a valid CoT registered */ + assert(cot_desc_ptr != NULL); + + /* Crypto module */ + crypto_mod_init(); + + /* Image parser module */ + img_parser_init(); +} + +/* + * Authenticate a certificate/image + * + * Return: 0 = success, Otherwise = error + */ +int auth_mod_verify_img(unsigned int img_id, + void *img_ptr, + unsigned int img_len) +{ + const auth_img_desc_t *img_desc = NULL; + const auth_method_desc_t *auth_method = NULL; + void *param_ptr; + unsigned int param_len; + int rc, i; + + /* Get the image descriptor from the chain of trust */ + img_desc = &cot_desc_ptr[img_id]; + + /* Ask the parser to check the image integrity */ + rc = img_parser_check_integrity(img_desc->img_type, img_ptr, img_len); + return_if_error(rc); + + /* Authenticate the image using the methods indicated in the image + * descriptor. */ + for (i = 0 ; i < AUTH_METHOD_NUM ; i++) { + auth_method = &img_desc->img_auth_methods[i]; + switch (auth_method->type) { + case AUTH_METHOD_NONE: + rc = 0; + break; + case AUTH_METHOD_HASH: + rc = auth_hash(&auth_method->param.hash, + img_desc, img_ptr, img_len); + break; + case AUTH_METHOD_SIG: + rc = auth_signature(&auth_method->param.sig, + img_desc, img_ptr, img_len); + break; + default: + /* Unknown authentication method */ + rc = 1; + break; + } + return_if_error(rc); + } + + /* Extract the parameters indicated in the image descriptor to + * authenticate the children images. */ + for (i = 0 ; i < COT_MAX_VERIFIED_PARAMS ; i++) { + if (img_desc->authenticated_data[i].type_desc == NULL) { + continue; + } + + /* Get the parameter from the image parser module */ + rc = img_parser_get_auth_param(img_desc->img_type, + img_desc->authenticated_data[i].type_desc, + img_ptr, img_len, ¶m_ptr, ¶m_len); + return_if_error(rc); + + /* Check parameter size */ + if (param_len > img_desc->authenticated_data[i].data.len) { + return 1; + } + + /* Copy the parameter for later use */ + memcpy((void *)img_desc->authenticated_data[i].data.ptr, + (void *)param_ptr, param_len); + } + + /* Mark image as authenticated */ + auth_img_flags[img_desc->img_id] |= IMG_FLAG_AUTHENTICATED; + + return 0; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/crypto_mod.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/crypto_mod.c new file mode 100644 index 0000000..b432e6a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/crypto_mod.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/* Variable exported by the crypto library through REGISTER_CRYPTO_LIB() */ +extern const crypto_lib_desc_t crypto_lib_desc; + +/* + * The crypto module is responsible for verifying digital signatures and hashes. + * It relies on a crypto library to perform the cryptographic operations. + * + * The crypto module itself does not impose any specific format on signatures, + * signature algorithm, keys or hashes, but most cryptographic libraries will + * take the parameters as the following DER encoded ASN.1 structures: + * + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL + * } + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm AlgorithmIdentifier, + * digest OCTET STRING + * } + * + * SubjectPublicKeyInfo ::= SEQUENCE { + * algorithm AlgorithmIdentifier, + * subjectPublicKey BIT STRING + * } + * + * SignatureAlgorithm ::= AlgorithmIdentifier + * + * SignatureValue ::= BIT STRING + */ + +/* + * Perform some static checking and call the library initialization function + */ +void crypto_mod_init(void) +{ + assert(crypto_lib_desc.name != NULL); + assert(crypto_lib_desc.init != NULL); + assert(crypto_lib_desc.verify_signature != NULL); + assert(crypto_lib_desc.verify_hash != NULL); + + /* Initialize the cryptographic library */ + crypto_lib_desc.init(); + INFO("Using crypto library '%s'\n", crypto_lib_desc.name); +} + +/* + * Function to verify a digital signature + * + * Parameters: + * + * data_ptr, data_len: signed data + * sig_ptr, sig_len: the digital signature + * sig_alg_ptr, sig_alg_len: the digital signature algorithm + * pk_ptr, pk_len: the public key + */ +int crypto_mod_verify_signature(void *data_ptr, unsigned int data_len, + void *sig_ptr, unsigned int sig_len, + void *sig_alg_ptr, unsigned int sig_alg_len, + void *pk_ptr, unsigned int pk_len) +{ + assert(data_ptr != NULL); + assert(data_len != 0); + assert(sig_ptr != NULL); + assert(sig_len != 0); + assert(sig_alg_ptr != NULL); + assert(sig_alg_len != 0); + assert(pk_ptr != NULL); + assert(pk_len != 0); + + return crypto_lib_desc.verify_signature(data_ptr, data_len, + sig_ptr, sig_len, + sig_alg_ptr, sig_alg_len, + pk_ptr, pk_len); +} + +/* + * Verify a hash by comparison + * + * Parameters: + * + * data_ptr, data_len: data to be hashed + * digest_info_ptr, digest_info_len: hash to be compared + */ +int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, + void *digest_info_ptr, unsigned int digest_info_len) +{ + assert(data_ptr != NULL); + assert(data_len != 0); + assert(digest_info_ptr != NULL); + assert(digest_info_len != 0); + + return crypto_lib_desc.verify_hash(data_ptr, data_len, + digest_info_ptr, digest_info_len); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/img_parser_mod.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/img_parser_mod.c new file mode 100644 index 0000000..c8cbe34 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/img_parser_mod.c @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +extern uintptr_t __PARSER_LIB_DESCS_START__; +extern uintptr_t __PARSER_LIB_DESCS_END__; +#define PARSER_LIB_DESCS_START ((uintptr_t) (&__PARSER_LIB_DESCS_START__)) +#define PARSER_LIB_DESCS_END ((uintptr_t) (&__PARSER_LIB_DESCS_END__)) +static unsigned int parser_lib_indices[IMG_MAX_TYPES]; +static img_parser_lib_desc_t *parser_lib_descs; + +#define INVALID_IDX UINT_MAX + +static void validate_desc(img_parser_lib_desc_t *desc) +{ + assert(desc != NULL); + assert(desc->init != NULL); + assert(desc->name != NULL); + assert(desc->check_integrity != NULL); + assert(desc->get_auth_param != NULL); +} + +void img_parser_init(void) +{ + unsigned int index, mod_num; + + /* Initialise internal variables to invalid state */ + for (index = 0; index < IMG_MAX_TYPES; index++) { + parser_lib_indices[index] = INVALID_IDX; + } + + /* Calculate how many image parsers are registered. At least one parser + * must be present */ + mod_num = PARSER_LIB_DESCS_END - PARSER_LIB_DESCS_START; + mod_num /= sizeof(img_parser_lib_desc_t); + assert(mod_num > 0); + + parser_lib_descs = (img_parser_lib_desc_t *) PARSER_LIB_DESCS_START; + for (index = 0; index < mod_num; index++) { + + /* Check that the image parser library descriptor is valid */ + validate_desc(&parser_lib_descs[index]); + + /* Initialize image parser */ + parser_lib_descs[index].init(); + + /* Ensure only one parser is registered for each image type */ + assert(parser_lib_indices[parser_lib_descs[index].img_type] == + INVALID_IDX); + + /* Keep the index of this hash calculator */ + parser_lib_indices[parser_lib_descs[index].img_type] = index; + } +} + +int img_parser_check_integrity(img_type_t img_type, + void *img_ptr, unsigned int img_len) +{ + unsigned int idx; + + assert(img_ptr != NULL); + assert(img_len != 0); + + /* No integrity checks on raw images */ + if (img_type == IMG_RAW) { + return IMG_PARSER_OK; + } + + /* Find the index of the required image parser */ + idx = parser_lib_indices[img_type]; + assert(idx != INVALID_IDX); + + /* Call the function to check the image integrity */ + return parser_lib_descs[idx].check_integrity(img_ptr, img_len); +} + +/* + * Extract an authentication parameter from an image + * + * Parameters: + * img_type: image type (certificate, raw image, etc) + * type_desc: provides info to obtain the parameter + * img_ptr: pointer to image data + * img_len: image length + * param_ptr: [out] stores a pointer to the parameter + * param_len: [out] stores the length of the parameter + */ +int img_parser_get_auth_param(img_type_t img_type, + const auth_param_type_desc_t *type_desc, + void *img_ptr, unsigned int img_len, + void **param_ptr, unsigned int *param_len) +{ + unsigned int idx; + + assert(type_desc != NULL); + assert(img_ptr != NULL); + assert(img_len != 0); + assert(param_ptr != NULL); + assert(param_len != NULL); + + /* In a raw image we can only get the data itself */ + if (img_type == IMG_RAW) { + assert(type_desc->type == AUTH_PARAM_RAW_DATA); + *param_ptr = img_ptr; + *param_len = img_len; + return IMG_PARSER_OK; + } + + /* Find the index of the required image parser library */ + idx = parser_lib_indices[img_type]; + assert(idx != INVALID_IDX); + + /* Call the function to obtain the parameter */ + return parser_lib_descs[idx].get_auth_param(type_desc, img_ptr, img_len, + param_ptr, param_len); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_common.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_common.c new file mode 100644 index 0000000..2978260 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_common.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* mbedTLS headers */ +#include + +/* + * mbedTLS heap + */ +#if (MBEDTLS_KEY_ALG_ID == MBEDTLS_ECDSA) +#define MBEDTLS_HEAP_SIZE (14*1024) +#elif (MBEDTLS_KEY_ALG_ID == MBEDTLS_RSA) +#define MBEDTLS_HEAP_SIZE (8*1024) +#endif +static unsigned char heap[MBEDTLS_HEAP_SIZE]; + +/* + * mbedTLS initialization function + * + * Return: 0 = success, Otherwise = error + */ +void mbedtls_init(void) +{ + static int ready; + int rc; + + if (!ready) { + /* Initialize the mbedTLS heap */ + rc = memory_buffer_alloc_init(heap, MBEDTLS_HEAP_SIZE); + if (rc == 0) { + ready = 1; + } else { + assert(0); + } + } +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_common.mk b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_common.mk new file mode 100644 index 0000000..b71bbc9 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_common.mk @@ -0,0 +1,60 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +ifneq (${MBEDTLS_COMMON_MK},1) +MBEDTLS_COMMON_MK := 1 + +# MBEDTLS_DIR must be set to the mbedTLS main directory (it must contain +# the 'include' and 'library' subdirectories). +ifeq (${MBEDTLS_DIR},) + $(error Error: MBEDTLS_DIR not set) +endif + +INCLUDES += -I${MBEDTLS_DIR}/include \ + -Iinclude/drivers/auth/mbedtls + +# Specify mbedTLS configuration file +POLARSSL_CONFIG_FILE := "" +$(eval $(call add_define,POLARSSL_CONFIG_FILE)) + +MBEDTLS_COMMON_SOURCES := drivers/auth/mbedtls/mbedtls_common.c \ + $(addprefix ${MBEDTLS_DIR}/library/, \ + asn1parse.c \ + asn1write.c \ + memory_buffer_alloc.c \ + oid.c \ + platform.c \ + ) + +BL1_SOURCES += ${MBEDTLS_COMMON_SOURCES} +BL2_SOURCES += ${MBEDTLS_COMMON_SOURCES} +DISABLE_PEDANTIC := 1 + +endif diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_crypto.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_crypto.c new file mode 100644 index 0000000..f69f930 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_crypto.c @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include +#include +#include + +/* mbedTLS headers */ +#include +#include +#include +#include + +#define LIB_NAME "mbedTLS" + +/* + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL + * } + * + * SubjectPublicKeyInfo ::= SEQUENCE { + * algorithm AlgorithmIdentifier, + * subjectPublicKey BIT STRING + * } + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm AlgorithmIdentifier, + * digest OCTET STRING + * } + */ + +/* + * Initialize the library and export the descriptor + */ +static void init(void) +{ + /* Initialize mbedTLS */ + mbedtls_init(); +} + +/* + * Verify a signature. + * + * Parameters are passed using the DER encoding format following the ASN.1 + * structures detailed above. + */ +static int verify_signature(void *data_ptr, unsigned int data_len, + void *sig_ptr, unsigned int sig_len, + void *sig_alg, unsigned int sig_alg_len, + void *pk_ptr, unsigned int pk_len) +{ + asn1_buf sig_oid, sig_params; + asn1_buf signature; + md_type_t md_alg; + pk_type_t pk_alg; + pk_context pk; + int rc; + void *sig_opts = NULL; + const md_info_t *md_info; + unsigned char *p, *end; + unsigned char hash[POLARSSL_MD_MAX_SIZE]; + + /* Get pointers to signature OID and parameters */ + p = (unsigned char *)sig_alg; + end = (unsigned char *)(p + sig_alg_len); + rc = asn1_get_alg(&p, end, &sig_oid, &sig_params); + if (rc != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + /* Get the actual signature algorithm (MD + PK) */ + rc = oid_get_sig_alg(&sig_oid, &md_alg, &pk_alg); + if (rc != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + /* Parse the public key */ + pk_init(&pk); + p = (unsigned char *)pk_ptr; + end = (unsigned char *)(p + pk_len); + rc = pk_parse_subpubkey(&p, end, &pk); + if (rc != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + /* Get the signature (bitstring) */ + p = (unsigned char *)sig_ptr; + end = (unsigned char *)(p + sig_len); + signature.tag = *p; + rc = asn1_get_bitstring_null(&p, end, &signature.len); + if (rc != 0) { + rc = CRYPTO_ERR_SIGNATURE; + goto end; + } + signature.p = p; + + /* Calculate the hash of the data */ + md_info = md_info_from_type(md_alg); + if (md_info == NULL) { + rc = CRYPTO_ERR_SIGNATURE; + goto end; + } + p = (unsigned char *)data_ptr; + rc = md(md_info, p, data_len, hash); + if (rc != 0) { + rc = CRYPTO_ERR_SIGNATURE; + goto end; + } + + /* Verify the signature */ + rc = pk_verify_ext(pk_alg, sig_opts, &pk, md_alg, hash, + md_info->size, signature.p, signature.len); + if (rc != 0) { + rc = CRYPTO_ERR_SIGNATURE; + goto end; + } + + /* Signature verification success */ + rc = CRYPTO_SUCCESS; + +end: + pk_free(&pk); + return rc; +} + +/* + * Match a hash + * + * Digest info is passed in DER format following the ASN.1 structure detailed + * above. + */ +static int verify_hash(void *data_ptr, unsigned int data_len, + void *digest_info_ptr, unsigned int digest_info_len) +{ + asn1_buf hash_oid, params; + md_type_t md_alg; + const md_info_t *md_info; + unsigned char *p, *end, *hash; + unsigned char data_hash[POLARSSL_MD_MAX_SIZE]; + size_t len; + int rc; + + /* Digest info should be an ASN1_SEQUENCE */ + p = (unsigned char *)digest_info_ptr; + end = (unsigned char *)(digest_info_ptr + digest_info_len); + rc = asn1_get_tag(&p, end, &len, ASN1_CONSTRUCTED | ASN1_SEQUENCE); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + /* Get the hash algorithm */ + rc = asn1_get_alg(&p, end, &hash_oid, ¶ms); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + rc = oid_get_md_alg(&hash_oid, &md_alg); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + md_info = md_info_from_type(md_alg); + if (md_info == NULL) { + return CRYPTO_ERR_HASH; + } + + /* Hash should be octet string type */ + rc = asn1_get_tag(&p, end, &len, ASN1_OCTET_STRING); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + /* Length of hash must match the algorithm's size */ + if (len != md_info->size) { + return CRYPTO_ERR_HASH; + } + hash = p; + + /* Calculate the hash of the data */ + p = (unsigned char *)data_ptr; + rc = md(md_info, p, data_len, data_hash); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + /* Compare values */ + rc = memcmp(data_hash, hash, md_info->size); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + return CRYPTO_SUCCESS; +} + +/* + * Register crypto library descriptor + */ +REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash); diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_crypto.mk b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_crypto.mk new file mode 100644 index 0000000..67d2eb4 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_crypto.mk @@ -0,0 +1,72 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +include drivers/auth/mbedtls/mbedtls_common.mk + +# The platform may define the variable 'MBEDTLS_KEY_ALG' to select the key +# algorithm to use. Default algorithm is ECDSA. +ifeq (${MBEDTLS_KEY_ALG},) + MBEDTLS_KEY_ALG := rsa +endif + +MBEDTLS_CRYPTO_SOURCES := drivers/auth/mbedtls/mbedtls_crypto.c \ + $(addprefix ${MBEDTLS_DIR}/library/, \ + bignum.c \ + md.c \ + md_wrap.c \ + pk.c \ + pk_wrap.c \ + pkparse.c \ + pkwrite.c \ + sha256.c \ + ) + +# Key algorithm specific files +ifeq (${MBEDTLS_KEY_ALG},ecdsa) + MBEDTLS_CRYPTO_SOURCES += $(addprefix ${MBEDTLS_DIR}/library/, \ + ecdsa.c \ + ecp_curves.c \ + ecp.c \ + ) + MBEDTLS_KEY_ALG_ID := MBEDTLS_ECDSA +else ifeq (${MBEDTLS_KEY_ALG},rsa) + MBEDTLS_CRYPTO_SOURCES += $(addprefix ${MBEDTLS_DIR}/library/, \ + rsa.c \ + ) + MBEDTLS_KEY_ALG_ID := MBEDTLS_RSA +else + $(error "MBEDTLS_KEY_ALG=${MBEDTLS_KEY_ALG} not supported on mbedTLS") +endif + +# mbedTLS libraries rely on this define to build correctly +$(eval $(call add_define,MBEDTLS_KEY_ALG_ID)) + +BL1_SOURCES += ${MBEDTLS_CRYPTO_SOURCES} +BL2_SOURCES += ${MBEDTLS_CRYPTO_SOURCES} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_x509.mk b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_x509.mk new file mode 100644 index 0000000..3f9420d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_x509.mk @@ -0,0 +1,40 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +include drivers/auth/mbedtls/mbedtls_common.mk + +MBEDTLS_X509_SOURCES := drivers/auth/mbedtls/mbedtls_x509_parser.c \ + $(addprefix ${MBEDTLS_DIR}/library/, \ + x509.c \ + x509_crt.c \ + ) + +BL1_SOURCES += ${MBEDTLS_X509_SOURCES} +BL2_SOURCES += ${MBEDTLS_X509_SOURCES} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_x509_parser.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_x509_parser.c new file mode 100644 index 0000000..a8605ce --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/mbedtls/mbedtls_x509_parser.c @@ -0,0 +1,438 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * X509 parser based on PolarSSL + * + * This module implements functions to check the integrity of a X509v3 + * certificate ASN.1 structure and extract authentication parameters from the + * extensions field, such as an image hash or a public key. + */ + +#include +#include +#include +#include +#include +#include + +/* mbedTLS headers */ +#include +#include +#include + +/* Maximum OID string length ("a.b.c.d.e.f ...") */ +#define MAX_OID_STR_LEN 64 + +#define LIB_NAME "mbedTLS X509v3" + +/* Temporary variables to speed up the authentication parameters search. These + * variables are assigned once during the integrity check and used any time an + * authentication parameter is requested, so we do not have to parse the image + * again */ +static asn1_buf tbs; +static asn1_buf v3_ext; +static asn1_buf pk; +static asn1_buf sig_alg; +static asn1_buf signature; + +/* + * Get X509v3 extension + * + * Global variable 'v3_ext' must point to the extensions region + * in the certificate. No need to check for errors since the image has passed + * the integrity check. + */ +static int get_ext(const char *oid, void **ext, unsigned int *ext_len) +{ + int oid_len; + size_t len; + unsigned char *end_ext_data, *end_ext_octet; + unsigned char *p; + const unsigned char *end; + char oid_str[MAX_OID_STR_LEN]; + asn1_buf extn_oid; + int is_critical; + + assert(oid != NULL); + + p = v3_ext.p; + end = v3_ext.p + v3_ext.len; + + asn1_get_tag(&p, end, &len, ASN1_CONSTRUCTED | ASN1_SEQUENCE); + + while (p < end) { + memset(&extn_oid, 0x0, sizeof(extn_oid)); + is_critical = 0; /* DEFAULT FALSE */ + + asn1_get_tag(&p, end, &len, ASN1_CONSTRUCTED | ASN1_SEQUENCE); + end_ext_data = p + len; + + /* Get extension ID */ + extn_oid.tag = *p; + asn1_get_tag(&p, end, &extn_oid.len, ASN1_OID); + extn_oid.p = p; + p += extn_oid.len; + + /* Get optional critical */ + asn1_get_bool(&p, end_ext_data, &is_critical); + + /* Extension data */ + asn1_get_tag(&p, end_ext_data, &len, ASN1_OCTET_STRING); + end_ext_octet = p + len; + + /* Detect requested extension */ + oid_len = oid_get_numeric_string(oid_str, + MAX_OID_STR_LEN, &extn_oid); + if (oid_len == POLARSSL_ERR_OID_BUF_TOO_SMALL) { + return IMG_PARSER_ERR; + } + if ((oid_len == strlen(oid_str)) && !strcmp(oid, oid_str)) { + *ext = (void *)p; + *ext_len = (unsigned int)len; + return IMG_PARSER_OK; + } + + /* Next */ + p = end_ext_octet; + } + + return IMG_PARSER_ERR_NOT_FOUND; +} + + +/* + * Check the integrity of the certificate ASN.1 structure. + * Extract the relevant data that will be used later during authentication. + */ +static int cert_parse(void *img, unsigned int img_len) +{ + int ret, is_critical; + size_t len; + unsigned char *p, *end, *crt_end; + asn1_buf sig_alg1, sig_alg2; + + p = (unsigned char *)img; + len = img_len; + end = p + len; + + /* + * Certificate ::= SEQUENCE { + * tbsCertificate TBSCertificate, + * signatureAlgorithm AlgorithmIdentifier, + * signatureValue BIT STRING } + */ + ret = asn1_get_tag(&p, end, &len, ASN1_CONSTRUCTED | ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + + if (len > (size_t)(end - p)) { + return IMG_PARSER_ERR_FORMAT; + } + crt_end = p + len; + + /* + * TBSCertificate ::= SEQUENCE { + */ + tbs.p = p; + ret = asn1_get_tag(&p, end, &len, ASN1_CONSTRUCTED | ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + end = p + len; + tbs.len = end - tbs.p; + + /* + * Version ::= INTEGER { v1(0), v2(1), v3(2) } + */ + ret = asn1_get_tag(&p, end, &len, + ASN1_CONTEXT_SPECIFIC | ASN1_CONSTRUCTED | 0); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + p += len; + + /* + * CertificateSerialNumber ::= INTEGER + */ + ret = asn1_get_tag(&p, end, &len, ASN1_INTEGER); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + p += len; + + /* + * signature AlgorithmIdentifier + */ + sig_alg1.p = p; + ret = asn1_get_tag(&p, end, &len, ASN1_CONSTRUCTED | ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + if ((end - p) < 1) { + return IMG_PARSER_ERR_FORMAT; + } + sig_alg1.len = (p + len) - sig_alg1.p; + p += len; + + /* + * issuer Name + */ + ret = asn1_get_tag(&p, end, &len, ASN1_CONSTRUCTED | ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + p += len; + + /* + * Validity ::= SEQUENCE { + * notBefore Time, + * notAfter Time } + * + */ + ret = asn1_get_tag(&p, end, &len, ASN1_CONSTRUCTED | ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + p += len; + + /* + * subject Name + */ + ret = asn1_get_tag(&p, end, &len, ASN1_CONSTRUCTED | ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + p += len; + + /* + * SubjectPublicKeyInfo + */ + pk.p = p; + ret = asn1_get_tag(&p, end, &len, ASN1_CONSTRUCTED | ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + pk.len = (p + len) - pk.p; + p += len; + + /* + * issuerUniqueID [1] IMPLICIT UniqueIdentifier OPTIONAL, + */ + ret = asn1_get_tag(&p, end, &len, + ASN1_CONTEXT_SPECIFIC | ASN1_CONSTRUCTED | 1); + if (ret != 0) { + if (ret != POLARSSL_ERR_ASN1_UNEXPECTED_TAG) { + return IMG_PARSER_ERR_FORMAT; + } + } else { + p += len; + } + + /* + * subjectUniqueID [2] IMPLICIT UniqueIdentifier OPTIONAL, + */ + ret = asn1_get_tag(&p, end, &len, + ASN1_CONTEXT_SPECIFIC | ASN1_CONSTRUCTED | 2); + if (ret != 0) { + if (ret != POLARSSL_ERR_ASN1_UNEXPECTED_TAG) { + return IMG_PARSER_ERR_FORMAT; + } + } else { + p += len; + } + + /* + * extensions [3] EXPLICIT Extensions OPTIONAL + */ + ret = asn1_get_tag(&p, end, &len, + ASN1_CONTEXT_SPECIFIC | ASN1_CONSTRUCTED | 3); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + + /* + * Extensions ::= SEQUENCE SIZE (1..MAX) OF Extension + */ + v3_ext.p = p; + ret = asn1_get_tag(&p, end, &len, ASN1_CONSTRUCTED | ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + v3_ext.len = (p + len) - v3_ext.p; + + /* + * Check extensions integrity + */ + while (p < end) { + ret = asn1_get_tag(&p, end, &len, + ASN1_CONSTRUCTED | ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + + /* Get extension ID */ + ret = asn1_get_tag(&p, end, &len, ASN1_OID); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + p += len; + + /* Get optional critical */ + ret = asn1_get_bool(&p, end, &is_critical); + if ((ret != 0) && (ret != POLARSSL_ERR_ASN1_UNEXPECTED_TAG)) { + return IMG_PARSER_ERR_FORMAT; + } + + /* Data should be octet string type */ + ret = asn1_get_tag(&p, end, &len, ASN1_OCTET_STRING); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + p += len; + } + + if (p != end) { + return IMG_PARSER_ERR_FORMAT; + } + + end = crt_end; + + /* + * } + * -- end of TBSCertificate + * + * signatureAlgorithm AlgorithmIdentifier + */ + sig_alg2.p = p; + ret = asn1_get_tag(&p, end, &len, ASN1_CONSTRUCTED | ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + if ((end - p) < 1) { + return IMG_PARSER_ERR_FORMAT; + } + sig_alg2.len = (p + len) - sig_alg2.p; + p += len; + + /* Compare both signature algorithms */ + if (sig_alg1.len != sig_alg2.len) { + return IMG_PARSER_ERR_FORMAT; + } + if (0 != memcmp(sig_alg1.p, sig_alg2.p, sig_alg1.len)) { + return IMG_PARSER_ERR_FORMAT; + } + memcpy(&sig_alg, &sig_alg1, sizeof(sig_alg)); + + /* + * signatureValue BIT STRING + */ + signature.p = p; + ret = asn1_get_tag(&p, end, &len, ASN1_BIT_STRING); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + signature.len = (p + len) - signature.p; + p += len; + + /* Check certificate length */ + if (p != end) { + return IMG_PARSER_ERR_FORMAT; + } + + return IMG_PARSER_OK; +} + + +/* Exported functions */ + +static void init(void) +{ + mbedtls_init(); +} + +static int check_integrity(void *img, unsigned int img_len) +{ + return cert_parse(img, img_len); +} + +/* + * Extract an authentication parameter from an X509v3 certificate + */ +static int get_auth_param(const auth_param_type_desc_t *type_desc, + void *img, unsigned int img_len, + void **param, unsigned int *param_len) +{ + int rc = IMG_PARSER_OK; + + /* We do not use img because the check_integrity function has already + * extracted the relevant data (v3_ext, pk, sig_alg, etc) */ + + switch (type_desc->type) { + case AUTH_PARAM_RAW_DATA: + /* Data to be signed */ + *param = (void *)tbs.p; + *param_len = (unsigned int)tbs.len; + break; + case AUTH_PARAM_HASH: + /* All these parameters are included as X509v3 extensions */ + rc = get_ext(type_desc->cookie, param, param_len); + break; + case AUTH_PARAM_PUB_KEY: + if (type_desc->cookie != 0) { + /* Get public key from extension */ + rc = get_ext(type_desc->cookie, param, param_len); + } else { + /* Get the subject public key */ + *param = (void *)pk.p; + *param_len = (unsigned int)pk.len; + } + break; + case AUTH_PARAM_SIG_ALG: + /* Get the certificate signature algorithm */ + *param = (void *)sig_alg.p; + *param_len = (unsigned int)sig_alg.len; + break; + case AUTH_PARAM_SIG: + /* Get the certificate signature */ + *param = (void *)signature.p; + *param_len = (unsigned int)signature.len; + break; + default: + rc = IMG_PARSER_ERR_NOT_FOUND; + break; + } + + return rc; +} + +REGISTER_IMG_PARSER_LIB(IMG_CERT, LIB_NAME, init, \ + check_integrity, get_auth_param); diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/tbbr/tbbr_cot.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/tbbr/tbbr_cot.c new file mode 100644 index 0000000..79a8965 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/auth/tbbr/tbbr_cot.c @@ -0,0 +1,445 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +/* + * Maximum key and hash sizes (in DER format) + */ +#define PK_DER_LEN 294 +#define HASH_DER_LEN 51 + +/* + * The platform must allocate buffers to store the authentication parameters + * extracted from the certificates. In this case, because of the way the CoT is + * established, we can reuse some of the buffers on different stages + */ +static unsigned char plat_bl2_hash_buf[HASH_DER_LEN]; +static unsigned char plat_bl30_hash_buf[HASH_DER_LEN]; +static unsigned char plat_bl31_hash_buf[HASH_DER_LEN]; +static unsigned char plat_bl32_hash_buf[HASH_DER_LEN]; +static unsigned char plat_bl33_hash_buf[HASH_DER_LEN]; +static unsigned char plat_tz_world_pk_buf[PK_DER_LEN]; +static unsigned char plat_ntz_world_pk_buf[PK_DER_LEN]; +static unsigned char plat_content_pk[PK_DER_LEN]; + +/* + * Parameter type descriptors + */ +static auth_param_type_desc_t subject_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, 0); +static auth_param_type_desc_t sig = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_SIG, 0); +static auth_param_type_desc_t sig_alg = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_SIG_ALG, 0); +static auth_param_type_desc_t raw_data = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_RAW_DATA, 0); + +static auth_param_type_desc_t tz_world_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, TZ_WORLD_PK_OID); +static auth_param_type_desc_t ntz_world_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, NTZ_WORLD_PK_OID); + +static auth_param_type_desc_t bl30_content_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, BL30_CONTENT_CERT_PK_OID); +static auth_param_type_desc_t bl31_content_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, BL31_CONTENT_CERT_PK_OID); +static auth_param_type_desc_t bl32_content_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, BL32_CONTENT_CERT_PK_OID); +static auth_param_type_desc_t bl33_content_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, BL33_CONTENT_CERT_PK_OID); + +static auth_param_type_desc_t bl2_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, BL2_HASH_OID); +static auth_param_type_desc_t bl30_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, BL30_HASH_OID); +static auth_param_type_desc_t bl31_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, BL31_HASH_OID); +static auth_param_type_desc_t bl32_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, BL32_HASH_OID); +static auth_param_type_desc_t bl33_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, BL33_HASH_OID); + +/* + * TBBR Chain of trust definition + */ +static const auth_img_desc_t cot_desc[] = { + /* + * BL2 + */ + [BL2_CERT_ID] = { + .img_id = BL2_CERT_ID, + .img_type = IMG_CERT, + .parent = NULL, + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &subject_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &bl2_hash, + .data = { + .ptr = (void *)plat_bl2_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } + }, + [BL2_IMAGE_ID] = { + .img_id = BL2_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[BL2_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &bl2_hash, + } + } + } + }, + /* + * Trusted key certificate + */ + [TRUSTED_KEY_CERT_ID] = { + .img_id = TRUSTED_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = NULL, + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &subject_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &tz_world_pk, + .data = { + .ptr = (void *)plat_tz_world_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + }, + [1] = { + .type_desc = &ntz_world_pk, + .data = { + .ptr = (void *)plat_ntz_world_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + } + } + }, + /* + * BL3-0 + */ + [BL30_KEY_CERT_ID] = { + .img_id = BL30_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[TRUSTED_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &tz_world_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &bl30_content_pk, + .data = { + .ptr = (void *)plat_content_pk, + .len = (unsigned int)PK_DER_LEN + } + } + } + }, + [BL30_CERT_ID] = { + .img_id = BL30_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[BL30_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &bl30_content_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &bl30_hash, + .data = { + .ptr = (void *)plat_bl30_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } + }, + [BL30_IMAGE_ID] = { + .img_id = BL30_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[BL30_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &bl30_hash, + } + } + } + }, + /* + * BL3-1 + */ + [BL31_KEY_CERT_ID] = { + .img_id = BL31_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[TRUSTED_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &tz_world_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &bl31_content_pk, + .data = { + .ptr = (void *)plat_content_pk, + .len = (unsigned int)PK_DER_LEN + } + } + } + }, + [BL31_CERT_ID] = { + .img_id = BL31_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[BL31_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &bl31_content_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &bl31_hash, + .data = { + .ptr = (void *)plat_bl31_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } + }, + [BL31_IMAGE_ID] = { + .img_id = BL31_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[BL31_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &bl31_hash, + } + } + } + }, + /* + * BL3-2 + */ + [BL32_KEY_CERT_ID] = { + .img_id = BL32_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[TRUSTED_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &tz_world_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &bl32_content_pk, + .data = { + .ptr = (void *)plat_content_pk, + .len = (unsigned int)PK_DER_LEN + } + } + } + }, + [BL32_CERT_ID] = { + .img_id = BL32_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[BL32_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &bl32_content_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &bl32_hash, + .data = { + .ptr = (void *)plat_bl32_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } + }, + [BL32_IMAGE_ID] = { + .img_id = BL32_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[BL32_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &bl32_hash, + } + } + } + }, + /* + * BL3-3 + */ + [BL33_KEY_CERT_ID] = { + .img_id = BL33_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[TRUSTED_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &ntz_world_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &bl33_content_pk, + .data = { + .ptr = (void *)plat_content_pk, + .len = (unsigned int)PK_DER_LEN + } + } + } + }, + [BL33_CERT_ID] = { + .img_id = BL33_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[BL33_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &bl33_content_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &bl33_hash, + .data = { + .ptr = (void *)plat_bl33_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } + }, + [BL33_IMAGE_ID] = { + .img_id = BL33_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[BL33_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &bl33_hash, + } + } + } + } +}; + +/* Register the CoT in the authentication module */ +REGISTER_COT(cot_desc); diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/console/console.S b/IPL/SDK/v3m/src/Dummy_BL33/drivers/console/console.S new file mode 100644 index 0000000..d966f0d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/console/console.S @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include + + .globl console_init + .globl console_putc + .globl console_getc + + /* + * The console base is in the data section and not in .bss + * even though it is zero-init. In particular, this allows + * the console functions to start using this variable before + * the runtime memory is initialized for images which do not + * need to copy the .data section from ROM to RAM. + */ +.section .data.console_base ; .align 3 + console_base: .quad 0x0 + + /* ----------------------------------------------- + * int console_init(uintptr_t base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. It saves + * the console base to the data section. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * out: return 1 on success else 0 on error + * Clobber list : x1 - x3 + * ----------------------------------------------- + */ +func console_init + /* Check the input base address */ + cbz x0, init_fail + adrp x3, console_base + str x0, [x3, :lo12:console_base] + b console_core_init +init_fail: + ret +endfunc console_init + + /* --------------------------------------------- + * int console_putc(int c) + * Function to output a character over the + * console. It returns the character printed on + * success or -1 on error. + * In : x0 - character to be printed + * Out : return -1 on error else return character. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func console_putc + adrp x2, console_base + ldr x1, [x2, :lo12:console_base] + b console_core_putc +endfunc console_putc + + /* --------------------------------------------- + * int console_getc(void) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_getc + adrp x1, console_base + ldr x0, [x1, :lo12:console_base] + b console_core_getc +endfunc console_getc diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/console/skeleton_console.S b/IPL/SDK/v3m/src/Dummy_BL33/drivers/console/skeleton_console.S new file mode 100644 index 0000000..083d3c7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/console/skeleton_console.S @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include + + /* + * This file contains a skeleton console implementation that can + * be used as basis for a real console implementation by platforms + * that do not contain PL011 hardware. + */ + + .globl console_core_init + .globl console_core_putc + .globl console_core_getc + + /* ----------------------------------------------- + * int console_core_init(uintptr_t base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * Out: return 1 on success else 0 on error + * Clobber list : x1, x2 + * ----------------------------------------------- + */ +func console_core_init + /* Check the input base address */ + cbz x0, core_init_fail + /* Check baud rate and uart clock for sanity */ + cbz w1, core_init_fail + cbz w2, core_init_fail + /* Insert implementation here */ + mov w0, #1 + ret +core_init_fail: + mov w0, wzr + ret +endfunc console_core_init + + /* -------------------------------------------------------- + * int console_core_putc(int c, uintptr_t base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_core_putc + /* Check the input parameter */ + cbz x1, putc_error + /* Insert implementation here */ + ret +putc_error: + mov w0, #-1 + ret +endfunc console_core_putc + + /* --------------------------------------------- + * int console_core_getc(uintptr_t base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * In : x0 - console base address + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_getc + cbz x0, getc_error + /* Insert implementation here */ + ret +getc_error: + mov w0, #-1 + ret +endfunc console_core_getc diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/delay_timer/delay_timer.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/delay_timer/delay_timer.c new file mode 100644 index 0000000..0bee876 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/delay_timer/delay_timer.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/*********************************************************** + * The delay timer implementation + ***********************************************************/ +static const timer_ops_t *ops; + +/*********************************************************** + * Delay for the given number of microseconds. The driver must + * be initialized before calling this function. + ***********************************************************/ +void udelay(uint32_t usec) +{ + assert(ops != 0 && + (ops->clk_mult != 0) && + (ops->clk_div != 0) && + (ops->get_timer_value != 0)); + + uint32_t start, cnt, delta, delta_us; + + /* counter is decreasing */ + start = ops->get_timer_value(); + do { + cnt = ops->get_timer_value(); + if (cnt > start) { + delta = UINT32_MAX - cnt; + delta += start; + } else + delta = start - cnt; + delta_us = (delta * ops->clk_mult) / ops->clk_div; + } while (delta_us < usec); +} + +/*********************************************************** + * Delay for the given number of milliseconds. The driver must + * be initialized before calling this function. + ***********************************************************/ +void mdelay(uint32_t msec) +{ + udelay(msec*1000); +} + +/*********************************************************** + * Initialize the timer. The fields in the provided timer + * ops pointer must be valid. + ***********************************************************/ +void timer_init(const timer_ops_t *ops_ptr) +{ + assert(ops_ptr != 0 && + (ops_ptr->clk_mult != 0) && + (ops_ptr->clk_div != 0) && + (ops_ptr->get_timer_value != 0)); + + ops = ops_ptr; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/io/io_fip.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/io/io_fip.c new file mode 100644 index 0000000..5a8a294 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/io/io_fip.c @@ -0,0 +1,376 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Useful for printing UUIDs when debugging.*/ +#define PRINT_UUID2(x) \ + "%08x-%04hx-%04hx-%02hhx%02hhx-%02hhx%02hhx%02hhx%02hhx%02hhx%02hhx", \ + x.time_low, x.time_mid, x.time_hi_and_version, \ + x.clock_seq_hi_and_reserved, x.clock_seq_low, \ + x.node[0], x.node[1], x.node[2], x.node[3], \ + x.node[4], x.node[5] + +typedef struct { + /* Put file_pos above the struct to allow {0} on static init. + * It is a workaround for a known bug in GCC + * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119 + */ + unsigned int file_pos; + fip_toc_entry_t entry; +} file_state_t; + +static const uuid_t uuid_null = {0}; +static file_state_t current_file = {0}; +static uintptr_t backend_dev_handle; +static uintptr_t backend_image_spec; + + +/* Firmware Image Package driver functions */ +static int fip_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); +static int fip_file_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); +static int fip_file_len(io_entity_t *entity, size_t *length); +static int fip_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read); +static int fip_file_close(io_entity_t *entity); +static int fip_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params); +static int fip_dev_close(io_dev_info_t *dev_info); + + +/* Return 0 for equal uuids. */ +static inline int compare_uuids(const uuid_t *uuid1, const uuid_t *uuid2) +{ + return memcmp(uuid1, uuid2, sizeof(uuid_t)); +} + + +/* TODO: We could check version numbers or do a package checksum? */ +static inline int is_valid_header(fip_toc_header_t *header) +{ + if ((header->name == TOC_HEADER_NAME) && (header->serial_number != 0)) { + return 1; + } else { + return 0; + } +} + + +/* Identify the device type as a virtual driver */ +io_type_t device_type_fip(void) +{ + return IO_TYPE_FIRMWARE_IMAGE_PACKAGE; +} + + +static const io_dev_connector_t fip_dev_connector = { + .dev_open = fip_dev_open +}; + + +static const io_dev_funcs_t fip_dev_funcs = { + .type = device_type_fip, + .open = fip_file_open, + .seek = NULL, + .size = fip_file_len, + .read = fip_file_read, + .write = NULL, + .close = fip_file_close, + .dev_init = fip_dev_init, + .dev_close = fip_dev_close, +}; + + +/* No state associated with this device so structure can be const */ +static const io_dev_info_t fip_dev_info = { + .funcs = &fip_dev_funcs, + .info = (uintptr_t)NULL +}; + + +/* Open a connection to the FIP device */ +static int fip_dev_open(const uintptr_t dev_spec __attribute__((unused)), + io_dev_info_t **dev_info) +{ + assert(dev_info != NULL); + *dev_info = (io_dev_info_t *)&fip_dev_info; /* cast away const */ + + return IO_SUCCESS; +} + + +/* Do some basic package checks. */ +static int fip_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params) +{ + int result = IO_FAIL; + unsigned int image_id = (unsigned int)init_params; + uintptr_t backend_handle; + fip_toc_header_t header; + size_t bytes_read; + + /* Obtain a reference to the image by querying the platform layer */ + result = plat_get_image_source(image_id, &backend_dev_handle, + &backend_image_spec); + if (result != IO_SUCCESS) { + WARN("Failed to obtain reference to image id=%u (%i)\n", + image_id, result); + result = IO_FAIL; + goto fip_dev_init_exit; + } + + /* Attempt to access the FIP image */ + result = io_open(backend_dev_handle, backend_image_spec, + &backend_handle); + if (result != IO_SUCCESS) { + WARN("Failed to access image id=%u (%i)\n", image_id, result); + result = IO_FAIL; + goto fip_dev_init_exit; + } + + result = io_read(backend_handle, (uintptr_t)&header, sizeof(header), + &bytes_read); + if (result == IO_SUCCESS) { + if (!is_valid_header(&header)) { + WARN("Firmware Image Package header check failed.\n"); + result = IO_FAIL; + } else { + VERBOSE("FIP header looks OK.\n"); + } + } + + io_close(backend_handle); + + fip_dev_init_exit: + return result; +} + +/* Close a connection to the FIP device */ +static int fip_dev_close(io_dev_info_t *dev_info) +{ + /* TODO: Consider tracking open files and cleaning them up here */ + + /* Clear the backend. */ + backend_dev_handle = (uintptr_t)NULL; + backend_image_spec = (uintptr_t)NULL; + + return IO_SUCCESS; +} + + +/* Open a file for access from package. */ +static int fip_file_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity) +{ + int result = IO_FAIL; + uintptr_t backend_handle; + const io_uuid_spec_t *uuid_spec = (io_uuid_spec_t *)spec; + size_t bytes_read; + int found_file = 0; + + assert(uuid_spec != NULL); + assert(entity != NULL); + + /* Can only have one file open at a time for the moment. We need to + * track state like file cursor position. We know the header lives at + * offset zero, so this entry should never be zero for an active file. + * When the system supports dynamic memory allocation we can allow more + * than one open file at a time if needed. + */ + if (current_file.entry.offset_address != 0) { + WARN("fip_file_open : Only one open file at a time.\n"); + return IO_RESOURCES_EXHAUSTED; + } + + /* Attempt to access the FIP image */ + result = io_open(backend_dev_handle, backend_image_spec, + &backend_handle); + if (result != IO_SUCCESS) { + WARN("Failed to open Firmware Image Package (%i)\n", result); + result = IO_FAIL; + goto fip_file_open_exit; + } + + /* Seek past the FIP header into the Table of Contents */ + result = io_seek(backend_handle, IO_SEEK_SET, sizeof(fip_toc_header_t)); + if (result != IO_SUCCESS) { + WARN("fip_file_open: failed to seek\n"); + result = IO_FAIL; + goto fip_file_open_close; + } + + found_file = 0; + do { + result = io_read(backend_handle, + (uintptr_t)¤t_file.entry, + sizeof(current_file.entry), + &bytes_read); + if (result == IO_SUCCESS) { + if (compare_uuids(¤t_file.entry.uuid, + &uuid_spec->uuid) == 0) { + found_file = 1; + break; + } + } else { + WARN("Failed to read FIP (%i)\n", result); + goto fip_file_open_close; + } + } while (compare_uuids(¤t_file.entry.uuid, &uuid_null) != 0); + + if (found_file == 1) { + /* All fine. Update entity info with file state and return. Set + * the file position to 0. The 'current_file.entry' holds the + * base and size of the file. + */ + current_file.file_pos = 0; + entity->info = (uintptr_t)¤t_file; + } else { + /* Did not find the file in the FIP. */ + current_file.entry.offset_address = 0; + result = IO_FAIL; + } + + fip_file_open_close: + io_close(backend_handle); + + fip_file_open_exit: + return result; +} + + +/* Return the size of a file in package */ +static int fip_file_len(io_entity_t *entity, size_t *length) +{ + assert(entity != NULL); + assert(length != NULL); + + *length = ((file_state_t *)entity->info)->entry.size; + + return IO_SUCCESS; +} + + +/* Read data from a file in package */ +static int fip_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read) +{ + int result = IO_FAIL; + file_state_t *fp; + size_t file_offset; + size_t bytes_read; + uintptr_t backend_handle; + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_read != NULL); + assert(entity->info != (uintptr_t)NULL); + + /* Open the backend, attempt to access the blob image */ + result = io_open(backend_dev_handle, backend_image_spec, + &backend_handle); + if (result != IO_SUCCESS) { + WARN("Failed to open FIP (%i)\n", result); + result = IO_FAIL; + goto fip_file_read_exit; + } + + fp = (file_state_t *)entity->info; + + /* Seek to the position in the FIP where the payload lives */ + file_offset = fp->entry.offset_address + fp->file_pos; + result = io_seek(backend_handle, IO_SEEK_SET, file_offset); + if (result != IO_SUCCESS) { + WARN("fip_file_read: failed to seek\n"); + result = IO_FAIL; + goto fip_file_read_close; + } + + result = io_read(backend_handle, buffer, length, &bytes_read); + if (result != IO_SUCCESS) { + /* We cannot read our data. Fail. */ + WARN("Failed to read payload (%i)\n", result); + result = IO_FAIL; + goto fip_file_read_close; + } else { + /* Set caller length and new file position. */ + *length_read = bytes_read; + fp->file_pos += bytes_read; + } + +/* Close the backend. */ + fip_file_read_close: + io_close(backend_handle); + + fip_file_read_exit: + return result; +} + + +/* Close a file in package */ +static int fip_file_close(io_entity_t *entity) +{ + /* Clear our current file pointer. + * If we had malloc() we would free() here. + */ + if (current_file.entry.offset_address != 0) { + memset(¤t_file, 0, sizeof(current_file)); + } + + /* Clear the Entity info. */ + entity->info = 0; + + return IO_SUCCESS; +} + +/* Exported functions */ + +/* Register the Firmware Image Package driver with the IO abstraction */ +int register_io_dev_fip(const io_dev_connector_t **dev_con) +{ + int result = IO_FAIL; + assert(dev_con != NULL); + + result = io_register_device(&fip_dev_info); + if (result == IO_SUCCESS) + *dev_con = &fip_dev_connector; + + return result; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/io/io_memmap.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/io/io_memmap.c new file mode 100644 index 0000000..fc06fbb --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/io/io_memmap.c @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/* As we need to be able to keep state for seek, only one file can be open + * at a time. Make this a structure and point to the entity->info. When we + * can malloc memory we can change this to support more open files. + */ +typedef struct { + /* Use the 'in_use' flag as any value for base and file_pos could be + * valid. + */ + int in_use; + uintptr_t base; + size_t file_pos; +} file_state_t; + +static file_state_t current_file = {0}; + +/* Identify the device type as memmap */ +io_type_t device_type_memmap(void) +{ + return IO_TYPE_MEMMAP; +} + +/* Memmap device functions */ +static int memmap_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); +static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); +static int memmap_block_seek(io_entity_t *entity, int mode, + ssize_t offset); +static int memmap_block_read(io_entity_t *entity, uintptr_t buffer, + size_t length, size_t *length_read); +static int memmap_block_write(io_entity_t *entity, const uintptr_t buffer, + size_t length, size_t *length_written); +static int memmap_block_close(io_entity_t *entity); +static int memmap_dev_close(io_dev_info_t *dev_info); + + +static const io_dev_connector_t memmap_dev_connector = { + .dev_open = memmap_dev_open +}; + + +static const io_dev_funcs_t memmap_dev_funcs = { + .type = device_type_memmap, + .open = memmap_block_open, + .seek = memmap_block_seek, + .size = NULL, + .read = memmap_block_read, + .write = memmap_block_write, + .close = memmap_block_close, + .dev_init = NULL, + .dev_close = memmap_dev_close, +}; + + +/* No state associated with this device so structure can be const */ +static const io_dev_info_t memmap_dev_info = { + .funcs = &memmap_dev_funcs, + .info = (uintptr_t)NULL +}; + + +/* Open a connection to the memmap device */ +static int memmap_dev_open(const uintptr_t dev_spec __attribute__((unused)), + io_dev_info_t **dev_info) +{ + assert(dev_info != NULL); + *dev_info = (io_dev_info_t *)&memmap_dev_info; /* cast away const */ + + return IO_SUCCESS; +} + + + +/* Close a connection to the memmap device */ +static int memmap_dev_close(io_dev_info_t *dev_info) +{ + /* NOP */ + /* TODO: Consider tracking open files and cleaning them up here */ + return IO_SUCCESS; +} + + +/* Open a file on the memmap device */ +/* TODO: Can we do any sensible limit checks on requested memory */ +static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity) +{ + int result = IO_FAIL; + const io_block_spec_t *block_spec = (io_block_spec_t *)spec; + + /* Since we need to track open state for seek() we only allow one open + * spec at a time. When we have dynamic memory we can malloc and set + * entity->info. + */ + if (current_file.in_use == 0) { + assert(block_spec != NULL); + assert(entity != NULL); + + current_file.in_use = 1; + current_file.base = block_spec->offset; + /* File cursor offset for seek and incremental reads etc. */ + current_file.file_pos = 0; + entity->info = (uintptr_t)¤t_file; + result = IO_SUCCESS; + } else { + WARN("A Memmap device is already active. Close first.\n"); + result = IO_RESOURCES_EXHAUSTED; + } + + return result; +} + + +/* Seek to a particular file offset on the memmap device */ +static int memmap_block_seek(io_entity_t *entity, int mode, ssize_t offset) +{ + int result = IO_FAIL; + + /* We only support IO_SEEK_SET for the moment. */ + if (mode == IO_SEEK_SET) { + assert(entity != NULL); + + /* TODO: can we do some basic limit checks on seek? */ + ((file_state_t *)entity->info)->file_pos = offset; + result = IO_SUCCESS; + } else { + result = IO_FAIL; + } + + return result; +} + + +/* Read data from a file on the memmap device */ +static int memmap_block_read(io_entity_t *entity, uintptr_t buffer, + size_t length, size_t *length_read) +{ + file_state_t *fp; + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_read != NULL); + + fp = (file_state_t *)entity->info; + + memcpy((void *)buffer, (void *)(fp->base + fp->file_pos), length); + + *length_read = length; + /* advance the file 'cursor' for incremental reads */ + fp->file_pos += length; + + return IO_SUCCESS; +} + + +/* Write data to a file on the memmap device */ +static int memmap_block_write(io_entity_t *entity, const uintptr_t buffer, + size_t length, size_t *length_written) +{ + file_state_t *fp; + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_written != NULL); + + fp = (file_state_t *)entity->info; + + memcpy((void *)(fp->base + fp->file_pos), (void *)buffer, length); + + *length_written = length; + + /* advance the file 'cursor' for incremental writes */ + fp->file_pos += length; + + return IO_SUCCESS; +} + + +/* Close a file on the memmap device */ +static int memmap_block_close(io_entity_t *entity) +{ + assert(entity != NULL); + + entity->info = 0; + + /* This would be a mem free() if we had malloc.*/ + memset((void *)¤t_file, 0, sizeof(current_file)); + + return IO_SUCCESS; +} + + +/* Exported functions */ + +/* Register the memmap driver with the IO abstraction */ +int register_io_dev_memmap(const io_dev_connector_t **dev_con) +{ + int result = IO_FAIL; + assert(dev_con != NULL); + + result = io_register_device(&memmap_dev_info); + if (result == IO_SUCCESS) + *dev_con = &memmap_dev_connector; + + return result; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/io/io_semihosting.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/io/io_semihosting.c new file mode 100644 index 0000000..8e62be1 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/io/io_semihosting.c @@ -0,0 +1,236 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + + +/* Identify the device type as semihosting */ +static io_type_t device_type_sh(void) +{ + return IO_TYPE_SEMIHOSTING; +} + + +/* Semi-hosting functions, device info and handle */ + +static int sh_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); +static int sh_file_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); +static int sh_file_seek(io_entity_t *entity, int mode, ssize_t offset); +static int sh_file_len(io_entity_t *entity, size_t *length); +static int sh_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read); +static int sh_file_write(io_entity_t *entity, const uintptr_t buffer, + size_t length, size_t *length_written); +static int sh_file_close(io_entity_t *entity); + +static const io_dev_connector_t sh_dev_connector = { + .dev_open = sh_dev_open +}; + + +static const io_dev_funcs_t sh_dev_funcs = { + .type = device_type_sh, + .open = sh_file_open, + .seek = sh_file_seek, + .size = sh_file_len, + .read = sh_file_read, + .write = sh_file_write, + .close = sh_file_close, + .dev_init = NULL, /* NOP */ + .dev_close = NULL, /* NOP */ +}; + + +/* No state associated with this device so structure can be const */ +static const io_dev_info_t sh_dev_info = { + .funcs = &sh_dev_funcs, + .info = (uintptr_t)NULL +}; + + +/* Open a connection to the semi-hosting device */ +static int sh_dev_open(const uintptr_t dev_spec __unused, + io_dev_info_t **dev_info) +{ + int result = IO_SUCCESS; + assert(dev_info != NULL); + *dev_info = (io_dev_info_t *)&sh_dev_info; /* cast away const */ + return result; +} + + +/* Open a file on the semi-hosting device */ +static int sh_file_open(io_dev_info_t *dev_info __attribute__((unused)), + const uintptr_t spec, io_entity_t *entity) +{ + int result = IO_FAIL; + long sh_result = -1; + const io_file_spec_t *file_spec = (const io_file_spec_t *)spec; + + assert(file_spec != NULL); + assert(entity != NULL); + + sh_result = semihosting_file_open(file_spec->path, file_spec->mode); + + if (sh_result > 0) { + entity->info = (uintptr_t)sh_result; + result = IO_SUCCESS; + } else { + result = IO_FAIL; + } + return result; +} + + +/* Seek to a particular file offset on the semi-hosting device */ +static int sh_file_seek(io_entity_t *entity, int mode, ssize_t offset) +{ + int result = IO_FAIL; + long file_handle, sh_result; + + assert(entity != NULL); + + file_handle = (long)entity->info; + + sh_result = semihosting_file_seek(file_handle, offset); + + result = (sh_result == 0) ? IO_SUCCESS : IO_FAIL; + + return result; +} + + +/* Return the size of a file on the semi-hosting device */ +static int sh_file_len(io_entity_t *entity, size_t *length) +{ + int result = IO_FAIL; + + assert(entity != NULL); + assert(length != NULL); + + long sh_handle = (long)entity->info; + long sh_result = semihosting_file_length(sh_handle); + + if (sh_result >= 0) { + result = IO_SUCCESS; + *length = (size_t)sh_result; + } + + return result; +} + + +/* Read data from a file on the semi-hosting device */ +static int sh_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read) +{ + int result = IO_FAIL; + long sh_result = -1; + size_t bytes = length; + long file_handle; + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_read != NULL); + + file_handle = (long)entity->info; + + sh_result = semihosting_file_read(file_handle, &bytes, buffer); + + if (sh_result >= 0) { + *length_read = (bytes != length) ? bytes : length; + result = IO_SUCCESS; + } else + result = IO_FAIL; + + return result; +} + + +/* Write data to a file on the semi-hosting device */ +static int sh_file_write(io_entity_t *entity, const uintptr_t buffer, + size_t length, size_t *length_written) +{ + long sh_result = -1; + long file_handle; + size_t bytes = length; + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_written != NULL); + + file_handle = (long)entity->info; + + sh_result = semihosting_file_write(file_handle, &bytes, buffer); + + *length_written = length - bytes; + + return (sh_result == 0) ? IO_SUCCESS : IO_FAIL; +} + + +/* Close a file on the semi-hosting device */ +static int sh_file_close(io_entity_t *entity) +{ + int result = IO_FAIL; + long sh_result = -1; + long file_handle; + + assert(entity != NULL); + + file_handle = (long)entity->info; + + sh_result = semihosting_file_close(file_handle); + + result = (sh_result >= 0) ? IO_SUCCESS : IO_FAIL; + + return result; +} + + +/* Exported functions */ + +/* Register the semi-hosting driver with the IO abstraction */ +int register_io_dev_sh(const io_dev_connector_t **dev_con) +{ + int result = IO_FAIL; + assert(dev_con != NULL); + + result = io_register_device(&sh_dev_info); + if (result == IO_SUCCESS) + *dev_con = &sh_dev_connector; + + return result; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/io/io_storage.c b/IPL/SDK/v3m/src/Dummy_BL33/drivers/io/io_storage.c new file mode 100644 index 0000000..a3a8186 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/io/io_storage.c @@ -0,0 +1,373 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + + +/* Storage for a fixed maximum number of IO entities, definable by platform */ +static io_entity_t entity_pool[MAX_IO_HANDLES]; + +/* Simple way of tracking used storage - each entry is NULL or a pointer to an + * entity */ +static io_entity_t *entity_map[MAX_IO_HANDLES]; + +/* Track number of allocated entities */ +static unsigned int entity_count; + +/* Array of fixed maximum of registered devices, definable by platform */ +static const io_dev_info_t *devices[MAX_IO_DEVICES]; + +/* Number of currently registered devices */ +static unsigned int dev_count; + + +#if DEBUG /* Extra validation functions only used in debug builds */ + +/* Return a boolean value indicating whether a device connector is valid */ +static int is_valid_dev_connector(const io_dev_connector_t *dev_con) +{ + int result = (dev_con != NULL) && (dev_con->dev_open != NULL); + return result; +} + + +/* Return a boolean value indicating whether a device handle is valid */ +static int is_valid_dev(const uintptr_t dev_handle) +{ + const io_dev_info_t *dev = (io_dev_info_t *)dev_handle; + int result = (dev != NULL) && (dev->funcs != NULL) && + (dev->funcs->type != NULL) && + (dev->funcs->type() < IO_TYPE_MAX); + return result; +} + + +/* Return a boolean value indicating whether an IO entity is valid */ +static int is_valid_entity(const uintptr_t handle) +{ + const io_entity_t *entity = (io_entity_t *)handle; + int result = (entity != NULL) && + (is_valid_dev((uintptr_t)entity->dev_handle)); + return result; +} + + +/* Return a boolean value indicating whether a seek mode is valid */ +static int is_valid_seek_mode(io_seek_mode_t mode) +{ + return ((mode != IO_SEEK_INVALID) && (mode < IO_SEEK_MAX)); +} + +#endif /* End of debug-only validation functions */ + + +/* Open a connection to a specific device */ +static int dev_open(const io_dev_connector_t *dev_con, const uintptr_t dev_spec, + io_dev_info_t **dev_info) +{ + int result = IO_FAIL; + assert(dev_info != NULL); + assert(is_valid_dev_connector(dev_con)); + + result = dev_con->dev_open(dev_spec, dev_info); + return result; +} + + +/* Set a handle to track an entity */ +static void set_handle(uintptr_t *handle, io_entity_t *entity) +{ + assert(handle != NULL); + *handle = (uintptr_t)entity; +} + + +/* Locate an entity in the pool, specified by address */ +static int find_first_entity(const io_entity_t *entity, unsigned int *index_out) +{ + int result = IO_FAIL; + for (int index = 0; index < MAX_IO_HANDLES; ++index) { + if (entity_map[index] == entity) { + result = IO_SUCCESS; + *index_out = index; + break; + } + } + return result; +} + + +/* Allocate an entity from the pool and return a pointer to it */ +static int allocate_entity(io_entity_t **entity) +{ + int result = IO_FAIL; + assert(entity != NULL); + + if (entity_count < MAX_IO_HANDLES) { + unsigned int index = 0; + result = find_first_entity(NULL, &index); + assert(result == IO_SUCCESS); + *entity = entity_map[index] = &entity_pool[index]; + ++entity_count; + } else + result = IO_RESOURCES_EXHAUSTED; + + return result; +} + + +/* Release an entity back to the pool */ +static int free_entity(const io_entity_t *entity) +{ + int result = IO_FAIL; + unsigned int index = 0; + assert(entity != NULL); + + result = find_first_entity(entity, &index); + if (result == IO_SUCCESS) { + entity_map[index] = NULL; + --entity_count; + } + + return result; +} + + +/* Exported API */ + +/* Register a device driver */ +int io_register_device(const io_dev_info_t *dev_info) +{ + int result = IO_FAIL; + assert(dev_info != NULL); + + if (dev_count < MAX_IO_DEVICES) { + devices[dev_count] = dev_info; + dev_count++; + result = IO_SUCCESS; + } else { + result = IO_RESOURCES_EXHAUSTED; + } + + return result; +} + + +/* Open a connection to an IO device */ +int io_dev_open(const io_dev_connector_t *dev_con, const uintptr_t dev_spec, + uintptr_t *handle) +{ + int result = IO_FAIL; + assert(handle != NULL); + + result = dev_open(dev_con, dev_spec, (io_dev_info_t **)handle); + return result; +} + + +/* Initialise an IO device explicitly - to permit lazy initialisation or + * re-initialisation */ +int io_dev_init(uintptr_t dev_handle, const uintptr_t init_params) +{ + int result = IO_FAIL; + assert(dev_handle != (uintptr_t)NULL); + assert(is_valid_dev(dev_handle)); + + io_dev_info_t *dev = (io_dev_info_t *)dev_handle; + + if (dev->funcs->dev_init != NULL) { + result = dev->funcs->dev_init(dev, init_params); + } else { + /* Absence of registered function implies NOP here */ + result = IO_SUCCESS; + } + return result; +} + + +/* TODO: Consider whether an explicit "shutdown" API should be included */ + +/* Close a connection to a device */ +int io_dev_close(uintptr_t dev_handle) +{ + int result = IO_FAIL; + assert(dev_handle != (uintptr_t)NULL); + assert(is_valid_dev(dev_handle)); + + io_dev_info_t *dev = (io_dev_info_t *)dev_handle; + + if (dev->funcs->dev_close != NULL) { + result = dev->funcs->dev_close(dev); + } else { + /* Absence of registered function implies NOP here */ + result = IO_SUCCESS; + } + + return result; +} + + +/* Synchronous operations */ + + +/* Open an IO entity */ +int io_open(uintptr_t dev_handle, const uintptr_t spec, uintptr_t *handle) +{ + int result = IO_FAIL; + assert((spec != (uintptr_t)NULL) && (handle != NULL)); + assert(is_valid_dev(dev_handle)); + + io_dev_info_t *dev = (io_dev_info_t *)dev_handle; + io_entity_t *entity; + + result = allocate_entity(&entity); + + if (result == IO_SUCCESS) { + assert(dev->funcs->open != NULL); + result = dev->funcs->open(dev, spec, entity); + + if (result == IO_SUCCESS) { + entity->dev_handle = dev; + set_handle(handle, entity); + } else + free_entity(entity); + } + return result; +} + + +/* Seek to a specific position in an IO entity */ +int io_seek(uintptr_t handle, io_seek_mode_t mode, ssize_t offset) +{ + int result = IO_FAIL; + assert(is_valid_entity(handle) && is_valid_seek_mode(mode)); + + io_entity_t *entity = (io_entity_t *)handle; + + io_dev_info_t *dev = entity->dev_handle; + + if (dev->funcs->seek != NULL) + result = dev->funcs->seek(entity, mode, offset); + else + result = IO_NOT_SUPPORTED; + + return result; +} + + +/* Determine the length of an IO entity */ +int io_size(uintptr_t handle, size_t *length) +{ + int result = IO_FAIL; + assert(is_valid_entity(handle) && (length != NULL)); + + io_entity_t *entity = (io_entity_t *)handle; + + io_dev_info_t *dev = entity->dev_handle; + + if (dev->funcs->size != NULL) + result = dev->funcs->size(entity, length); + else + result = IO_NOT_SUPPORTED; + + return result; +} + + +/* Read data from an IO entity */ +int io_read(uintptr_t handle, + uintptr_t buffer, + size_t length, + size_t *length_read) +{ + int result = IO_FAIL; + assert(is_valid_entity(handle) && (buffer != (uintptr_t)NULL)); + + io_entity_t *entity = (io_entity_t *)handle; + + io_dev_info_t *dev = entity->dev_handle; + + if (dev->funcs->read != NULL) + result = dev->funcs->read(entity, buffer, length, length_read); + else + result = IO_NOT_SUPPORTED; + + return result; +} + + +/* Write data to an IO entity */ +int io_write(uintptr_t handle, + const uintptr_t buffer, + size_t length, + size_t *length_written) +{ + int result = IO_FAIL; + assert(is_valid_entity(handle) && (buffer != (uintptr_t)NULL)); + + io_entity_t *entity = (io_entity_t *)handle; + + io_dev_info_t *dev = entity->dev_handle; + + if (dev->funcs->write != NULL) { + result = dev->funcs->write(entity, buffer, length, + length_written); + } else + result = IO_NOT_SUPPORTED; + + return result; +} + + +/* Close an IO entity */ +int io_close(uintptr_t handle) +{ + int result = IO_FAIL; + assert(is_valid_entity(handle)); + + io_entity_t *entity = (io_entity_t *)handle; + + io_dev_info_t *dev = entity->dev_handle; + + if (dev->funcs->close != NULL) + result = dev->funcs->close(entity); + else { + /* Absence of registered function implies NOP here */ + result = IO_SUCCESS; + } + /* Ignore improbable free_entity failure */ + (void)free_entity(entity); + + return result; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/drivers/ti/uart/16550_console.S b/IPL/SDK/v3m/src/Dummy_BL33/drivers/ti/uart/16550_console.S new file mode 100644 index 0000000..ebb4615 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/drivers/ti/uart/16550_console.S @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .globl console_core_init + .globl console_core_putc + .globl console_core_getc + + /* ----------------------------------------------- + * int console_core_init(unsigned long base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * Out: return 1 on success + * Clobber list : x1, x2, x3 + * ----------------------------------------------- + */ +func console_core_init + /* Check the input base address */ + cbz x0, init_fail + /* Check baud rate and uart clock for sanity */ + cbz w1, init_fail + cbz w2, init_fail + + /* Program the baudrate */ + /* Divisor = Uart clock / (16 * baudrate) */ + lsl w2, w2, #4 + udiv w2, w1, w2 + and w1, w2, #0xff /* w1 = DLL */ + lsr w2, w2, #8 + and w2, w2, #0xff /* w2 = DLLM */ + ldr w3, [x0, #UARTLCR] + orr w3, w3, #UARTLCR_DLAB + str w3, [x0, #UARTLCR] /* enable DLL, DLLM programming */ + str w1, [x0, #UARTDLL] /* program DLL */ + str w2, [x0, #UARTDLLM] /* program DLLM */ + mov w2, #~UARTLCR_DLAB + and w3, w3, w2 + str w3, [x0, #UARTLCR] /* disable DLL, DLLM programming */ + + /* 8n1 */ + mov w3, #3 + str w3, [x0, #UARTLCR] + /* no interrupt */ + mov w3, #0 + str w3, [x0, #UARTIER] + /* enable fifo, DMA */ + mov w3, #(UARTFCR_FIFOEN | UARTFCR_DMAEN) + str w3, [x0, #UARTFCR] + /* DTR + RTS */ + mov w3, #3 + str w3, [x0, #UARTMCR] + mov w0, #1 +init_fail: + ret +endfunc console_core_init + + /* -------------------------------------------------------- + * int console_core_putc(int c, unsigned int base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_core_putc + /* Check the input parameter */ + cbz x1, putc_error + + /* Prepend '\r' to '\n' */ + cmp w0, #0xA + b.ne 2f + /* Check if the transmit FIFO is full */ +1: ldr w2, [x1, #UARTLSR] + and w2, w2, #(UARTLSR_TEMT | UARTLSR_THRE) + cmp w2, #(UARTLSR_TEMT | UARTLSR_THRE) + b.ne 1b + mov w2, #0xD /* '\r' */ + str w2, [x1, #UARTTX] + ldr w2, [x1, #UARTFCR] + orr w2, w2, #UARTFCR_TXCLR + str w2, [x1, #UARTFCR] + + /* Check if the transmit FIFO is full */ +2: ldr w2, [x1, #UARTLSR] + and w2, w2, #(UARTLSR_TEMT | UARTLSR_THRE) + cmp w2, #(UARTLSR_TEMT | UARTLSR_THRE) + b.ne 2b + str w0, [x1, #UARTTX] + ldr w2, [x1, #UARTFCR] + orr w2, w2, #UARTFCR_TXCLR + str w2, [x1, #UARTFCR] + ret +putc_error: + mov w0, #-1 + ret +endfunc console_core_putc + + /* --------------------------------------------- + * int console_core_getc(void) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * In : w0 - console base address + * Out : return -1 on error else return character. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_getc + /* Check if the receive FIFO is empty */ +1: ldr w1, [x0, #UARTLSR] + tbz w1, #UARTLSR_RDR, 1b + ldr w0, [x0, #UARTRX] + ret +getc_error: + mov w0, #-1 + ret +endfunc console_core_getc diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-base-gicv2-psci.dtb b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-base-gicv2-psci.dtb new file mode 100644 index 0000000000000000000000000000000000000000..89318c1874f35951c1ee93c7ca6c219808045294 GIT binary patch literal 10151 zcmbtaOONDM6~3-cngj@wK=Xd2na*Pp+L@~A>7;`QRHkPpj505xVMLIikP{Kq5aNLhK-7AB7zYKp=tG5x(zSU)S+ecQZAyRONHdckj91 zJ@?#4+4aW<{`)s$9{-gw=Ih2h(#HK1J`dsZAU?Pj_KaEi3#D89;^o=fZQsti0Q>#K zF5I}bd^RYfsvPZ~!Dlfj($(Ez?r#wjCECx6s4Q(kmb(WZa-dJApM=~}dZ*I8aA#CT z88nM~K@!8Wcw^nu_&j&IOt(&_qw!8uY>k3qa5^3h^X;Iww%V?))03bW_u9`=r7LNd zboPuGUWPF{fQ$WK!AD|FyWe@LEio6R{ZzMBSiFw) zcgi%>`rxhRSmdua$6_Bi+v0~~_Zsl~l>P>E=7jJI^GP+-b@{`_7R8N+vVI!mR!%16 zI4bPu5E~UyrMPx~Qng{*0nQ}BrE$tN-W9lklYfn`&Eoe~xGiHjRm~j9X;J$;gwqE! zeh4SV@;FW|wk#v%;z1Jmd?a6{K47siQIM9HR>NIKMxrbjE?Yj;;TG_(=h9eAb+%^BbI+ z^LuViuD|ngLiq+K>UEqtb^~&p=gcP#o%o)Y6W1u$Ci7{!W+6_Uwq%sU=jC*_`9vPB zP0B9Mxo&}zWR%0_<#f0CggM#ZL|u)YWYpbqVm*H59Xqb=u1&^B?+0EQrK94Yx4}~a zF2GV2<-8LXqe*PbZe6-X3$EAf?Y>*~ZmPTVH_osd7n6MKhofv?YjVjHFlN>1 zW?7`w%5I$A;&#MqnO|({!|)a2&XS1X3B7jE#*gF2I8&EcjN>#apx`3@AU@M|->*?( z7=XHs2aI{o`TdBJvDVjito$Vi~77 zPEuRdiPiQ0BrukDI^*H`w-1r=s4p%MRl~MN&^bVrjeg|%6uv7P{mS(@d{?&WCINId ztP}QPKvZ3b9{cM!G3Gz6it@%jqm6rh1N$$Ponp-qa@}TScNp&)V;>wwS!3*r!(6;z zl8faWMp@Tm-yB9+W89k@MpF;SL>v|uB(bc1@v5zT?vc{Ok zuAWM1SdIC(!YJ!{pHLWOjeSyKlr_dF;@VTw1y*A|tuV^E9-lk7dXzQBbGXAOYmC#+ zVQMPEYRu;qMp@VUg2E_k>|upb*4VPbC~NGC3ZtyClM17(u@!|;*4QHoqpYz<6-HTO zk133@#vWG~WsRLu7-fw;p)krCds1PPiFxXA4pg@md%rHq`mD*d5@gSI!cIrR-1H|7?Tm4J!>X?M50jhSGwIH&(qhfUEDq!SXyAv*D7;C?)qPu) zL!Z6O%bs>P)=cjm4Cj{*@yW7e!L`%*;=Vv#cofkP)jEy|%W!?ZV;<(j*&fQX9^zto z9OBdQ;QFq4P**(Gx;Je|=I3DtkM*$LYaR`sjtBdwc~BP~Gmk?7;9^;>v-T{TZUu4@ zYEGWYpPUgHbEoSw5xKcD5piRd<=ZO{$|BnCwWr5dsn5NnnZLFmE3rQIZsf1z8MisH z;pY9blF{E5QTDCkBl*A_b~^Kcy7V9J!*SBHIS(T)maF?-<~U*7XQc&>`eBqLu8ieE zFZPi+>mjZ!jxpoQyURoDXRRfhCk8(Xkb)-2xB58+UXB~{-o>&F@g4aEfl^V{X2qxw zxufK+lIydu8~2BlZ}ywI^g9T`xYs`84(yFS=Slla=eRz@yXrIB3Sr( zZ{_iv(|fQp(Ws-1x?iquxVM&OhttORW{U1T?YbvE>bydX*N^QVPq)+lxfnCAj^ctd zT5IXW%NJide_`{|i_QF!F&941+$A4o&nzFez8w~u|I6pL7ccCWjt{mOd1`(5yyHmE z@?lmS6(8h&Yl&^n%sv39=UG1W%bfZ6FzaUda1`GspZW#Se0(??XZdgx-zT5?rPF+T zn7OljkT-YFXK#S_cJkPXzQs?SKUlZh>&NAftP1rW;^vq0@}xP-l|F9gO8(?Z`(1IxjO}%fUbohcT_^ZUa+W8?TljFz*ZcI5 zdsUc(gI=djwnnV-gh%3I)++uQndRVO;c|@;bvDGSwZt|L$u+i(b*^>kTQ^>Ko}O{h z#=d+*G^^9^%bXChszQO}?Z(A89`(0);Ku1|`ozxGVZJZgGOKACk64?&;S1+3J_VTV z2Y;8*xA>RyJWh6#Bp8nh_lit>aI!7dkS`@+s<}sNH}v_XH8$OE|6Jj3C>`e3FQ%BB z@!UR*ICxy=s0*hw3?WK8E4Vk#m#cV$J&d;xIo{U1-b5WaD~w9yAw5}N%;|U}TD7k>ZucPktDz73fd%U}%bc^>XC{L&)rEJr`g6Q{GE)NMZ} z`|{t0HVn8}hRF^)9`36uggU&mFWG%yqc8pO z@*spi*E`T}f(9KL{g{oLzHXUu-8 zbUv$L*eZVuUxLh)!|5B9?DX@{cNBgVGTN-mzYLid%frvYcQ2gn-?)7B-1+{Mt5+^w zxqkkoOV4kfKUbFlpM}BoiGAI;T)4+XU3#eEwR0eSN)SrrOi%Q)Od=-K)8Cbllu=V|PE3Au-`7 z&4Y2gl|*Lx5-1OfC>xuVU@+jHd3^pxD$Pn6zZz9?85MDmw2i&vA<V>b_=DJbf4q z4BqYa%So9>nUzPwq1Z;5!OygQKH7^4+NhwVXiU_g?cxCMIK%~(wIHcpdz9l*ZdYag z|D|&5gKdyjm9R!dS$N>%A%Cgs&3A$f|FAHFXg3a{{`eq| z43;$b3lJ2?0<`?;pC}NEX|QZ?lwQ9FD3~zHvvz^By z^?uK+Sc8nM6n89b@o?a?Kxy{!N=So!)q`F9*uxm)d2(QwOJ-6={XrVoK5b2gLv(4n zInb$6IT~pk7Ngx!GS+sqahN?w_JV`bN8)f-uAc$AwZ4c4+s%KV`Svlx>Tr^UpcK90 zOUTg_lyb-H; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU4:cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU5:cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU6:cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU7:cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, + <0x0 0x2c000000 0 0x2000>, + <0x0 0x2c010000 0 0x2000>, + <0x0 0x2c02F000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "rtsm_ve-motherboard.dtsi" + }; + + panels { + panel@0 { + compatible = "panel"; + mode = "XVGA"; + refresh = <60>; + xres = <1024>; + yres = <768>; + pixclock = <15748>; + left_margin = <152>; + right_margin = <48>; + upper_margin = <23>; + lower_margin = <3>; + hsync_len = <104>; + vsync_len = <4>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + }; +}; diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-base-gicv2legacy-psci.dtb b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-base-gicv2legacy-psci.dtb new file mode 100644 index 0000000000000000000000000000000000000000..0d176201d72dcaf4d40573220e9750ecb03dac0e GIT binary patch literal 10151 zcmbtaOOG5^6~5Jz3<(gN!0>*=c=B+lphiTr>Fv4e)TuZ=NZH|CKx?k90QgzG_EC<{BrEdQ0%E&i~0_IAgwlP*AhKXn&w zTswX?D5J`b^3UK}42pDRdzkwh)Cm*q=0#MN){u7h;35Y4bo>d>EyZ^#-V3)zWt4%l zdM`*~couK0dkWWcr^@lN z)coMB=2+yfH^*WZdbY)jWA_^L_bL7j@XQIp7v_^{sB8QE#unzrgRP$ixuugyIgScD zI@FDdsA62ZKdsuZ?Lf~YLD72BwZ1FrhMxFq{pzg#-b!z6ET*cN12HXXpZj3?fY$GW ziLpEklZ!2F#4a8rkzbC3@pK;0=I5MlDnBH?WfDcXFOg(yj^UDgnfidl#*lZe6)v7{ zR%?Od{|Ft|569mIJy85VL34~My~p|eLB%r;Pu zF}eQEiwX7(Oyui0b?gS@FwdD!96IqmFD9;0u1)6Cbj?DXI&H})r=J(oQS*s7T$`j_ zo^#y-CdnwLpBK|n^9ggZfr-2tJISb{Vq!gB^Ntg0t(b( z3p?+a)lnp}<8EELMG4Al_IBSbdpFfx`Wt81jf+V>_QO#&E=EZb6}>JFBS>JiCO(R) zvIb(m9!I-=&{^|0<4_JBPV}ruY#Xj0&w+LE;G8{S)glAwU8(dvhk3;vS*!bsISvz+ z2jzFg^yF?T`HK0T=GoSV;VZcr~$e*!w%JD%}y{o4h}c+`apMAfkE5qJ(zC8HlHpTch?qhBeX!*3<4ZW2Hz z!#ZIL1ET7J^w?jAi8234Wy%}-j5hB1E#$vaa*{Ph&~=-Y-067NI`+ZoNNXMY;&d)v z5J{n((~;Ko*f*ymt##a+oQ|~Cxp@h(>=#Xxou+UW2OsC`esq69l<#eRAj(OsA zq_qxluXUug4s*ZOk=8n_1+|W}*71Dq+9R!XOarG=DFNy9dD_vs-bW#H^+;>o$CQq= z)-jD;J(bds8uM|bBdzOwLg`3r-6xffwAOKoxc1a^fz+5!D;;TFkMA8^JN0g4V z);+3pq_yrbr6a9%k1HK%tvji7q_yq|r6a9%PbwX0>OA#22drC*z26jNeO6_BWgpzG zUNNm~cT+#_m?Ny~XtS}V5(3wGZBE>?@+uTx%A~vyFJM`JhyzFVG$C~NAgW>%0K0awn6kI!U(1z>tUE?sv z&h}u>dgzYdIvnhy#z9_i%)AbT0)@6* zXYE-s-3a6))SNt(KRF{Z=8o5AB4TrABI=DfF27#6R~FG`PaYZCB9i*tOPcv>4Qavp z*t?Oxl4soJM24I9uZl*0Thy{|6&}e4=Aq-64|QI`eK<~fHs_&0pj7n}FQbH|4l_DjbH+l;)m z-hbY4q-XIkD-Mbea=*32HfLrZ6sYG}JoU$%`S397X7O+o-zT2>1JQhVI2&j2a1`Gs zp8BKHe0Z3-vv`mz<0ah{`rh`yS;W;{>Z9O?;&n}5u}a}QMF5KSDn+uboww%T%BiQ#M~q%?2WSih!uF=xqdl(ICHj^?B)_>vO~yTfiHb} zr>Szi!YW5S_+V*_=X+x1Nplt}ecXwa_=%PBBVomi?R5@bw^k2bC-@{eixcB5c(~^4 zefq$?DonybuTv*mBUX9BBk>_?6`w|CF}PT`wUZHbGQ_L3#5VWIHMWg)u65~KH(q$2 zo>3@cU%nxn<>~ijCZDXTU_g1>aWRfZ{S6+tar&CRv9ooU?~B%EB~9ZIYtuJ;;oQZy z0JHtza~XY$e>uQCHL)`l1 zR3~RVw@)Ju@{X3gU`oRfq_ne)d*gh$f>+qXcypiQZH?f&ZB_+-Ae+AOE1=i(WxhOJft-piv{J+ri9WU!4F0FUvR`UyxQRVatnAgv}u6V}m zXNu>$8iuX%x9}yaeYx|c$v(O%X7QTDoZ2!jPtLM)5uUx%y z@yhk{FI{?m{rtJw26z?**Dqe~_Rp@LGeTUvwk~S%@fh^+`jzXK`j^(vUB7VM2z~a2 zmn;F{jrFUSubu2XF|BhFb+UD+`s>eM>#wb?bP&2lgp@XtIxpOH$lT*j|P6K4oeCuUD^~t|!HiGP?zY`C}TV~m|VewdcG#TfUv7g~p_sK=bWuhLzzY3jry5 z#g~wyDKO=h*~PEf<4+#%O7~3?4afa7C^qBF6!GR(&7hM};WP=8)-hYu Zrbw7=2?@?*T@z+w%(Eab%|@P^{{v&e(zpNs literal 0 HcmV?d00001 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-base-gicv2legacy-psci.dts b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-base-gicv2legacy-psci.dts new file mode 100644 index 0000000..58d3159 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-base-gicv2legacy-psci.dts @@ -0,0 +1,319 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { +}; + +/ { + model = "FVP Base"; + compatible = "arm,vfp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU4:cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU5:cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU6:cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU7:cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2c001000 0 0x1000>, + <0x0 0x2c002000 0 0x1000>, + <0x0 0x2c004000 0 0x2000>, + <0x0 0x2c006000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "rtsm_ve-motherboard.dtsi" + }; + + panels { + panel@0 { + compatible = "panel"; + mode = "XVGA"; + refresh = <60>; + xres = <1024>; + yres = <768>; + pixclock = <15748>; + left_margin = <152>; + right_margin = <48>; + upper_margin = <23>; + lower_margin = <3>; + hsync_len = <104>; + vsync_len = <4>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + }; +}; diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-base-gicv3-psci.dtb b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-base-gicv3-psci.dtb new file mode 100644 index 0000000000000000000000000000000000000000..f1dc75eeb8b7cac39a82f0f5db655473a4dbd501 GIT binary patch literal 10779 zcmbtaO^h5z6|UYTCJqis2>-v17lLDLXJ=-;$p*zR@!AenY{v=4LWr>H>FL>RwtKqM zJ+nWN5Jt&~6DP!hNN|P&H#l+1frtyINZdf;0Fi(kKm-W^-}kDjyJn_$$!tpM>3Xle zdiB+-S3li7zrFWAe^Kh(CzMiOR_fuO;eHm^1Gw(Tg|wJK-)HU)f0#UdoBFldMd(km z?8@z%r!NL&WN_4f9M_4UNSAj9x!+@%2+@9CL}jUg#JvX>Inbt+&mh0x$ZaEg;dWL= zLrA*Z3z8U?#Tx6b;JUCj{c9CGE2A z<#${+n5ldH9oOy6)cxu^t{YZ$=^rmI!tQ7?4z7*N&8_wHbYt2YZ^P+_ki`&AlLb1T#lkbd!J=l5gCED857^Z z#Wr+1C}$8Lx#cwvly_#!X{V~cI$M61Dc2ay$ux5)rxUKt22SsF%Nsb|?Upxi;(W6G z7G7~biTrXDjOsWi=4DPNXZ*##WfDcXFP@}t?!zVVP}_h;`;hnVn>_vW6EoMXe}4%b z*9R-Vj(p#de~0`J9QjS;?{Va}jO_Z>e>eO*z3Ny#;OG6_X%GAs|K!Nvck(qyCcpPN zGWk)qzNY`W;<>udZ$k%&_<(&AU&8OZ>(pvJ#?zz!Y$89zm3Ox@Hq;UKVccoQdzH#Cp8u9Xqb=woUqpGC2vaG)lALpu5gf020)Kr7z#sWmJjo zv|X3(P=mw`73uCfa;wgGVmBUQH!jBc$PcsOsK}BeD!QFP-HNu!bxYR3tvK{|^@KBA zy@yd|`^@s=8+F+N>)Y`|R-P^F_|=?VW)YI+RQWhht37np8uA z=x9gMNAYWPv@7Y8_%%9n69-xy_b5qph*K9?na7qBef~WI<&Awt8z-oL)zLFsadh-m z+opUPL)pc!PtzFcTnzg-jj{ejktE`$G1R$s=!0ntbuNbc<}`*n7sIu88bh6n;ZROv zoZ&^OUX!LVcAXLcelVwJ>`>>n#rT`HL!FDk_|0Ibb1_(BW-!#b7_2=r80uUM*UD)= z)VUaj;WWkxO_bK}2t+VH58&?F`2gf;JJh+D2OBWdxfo8fX*Rb$`__Q5o+M`sdk2PSZbM5e*%(NZqTnyh2O=GBYFIIv2ClfT7OCe6|5Yos0Qg1BN;m z!!y;ipQ&>(pKriW=VHz_V5oC3k2GMYb1~-{Fw_y_Ij`Ix+C9$uX;E^U6Pe>C=ZjtQ z8gO~HllpmE9b>;ln-hB#Ow0c14U(YT?zXD8eQX?wdj#WeqJ3Y$DjdWnN2JDLe$~(Q z#tCvWd9&wuzXF~r*}Haemg#mTnkJ5G&}6#=LW#t3?x)sQnU>*l5)7YchwZkwdD0$9nFz9cd4^^Rb#pC>oa=V z3*>}3IeDzTGr)1}u(EsBBsY83WVuqO<<~0@$|Bn8w(7?Msb4)8*m>(~AS%4ssn&@+$w9dDW>NBIN?lXPPxz4kn zX-j-y`+kyrpXjaOkf!9Yb_j>|`jLL8mun7;3vxhP)w^Mi1;>$NZ4>!X{}ArfOC;fL zd7o3i;1Q&f*O6zSu^eqw{jz<-ec{yXaB3g#r0CvbwtHfuiYxed?a2P|^k4VS`j~Nb z7?%gh<(cbOpTB%%%h0A3kZ!^0Dh%lW+bnpQ(>y?3e2wY%}uZp?ThM zq-XgsDh~4xVt?Tj+nkwwC_p_=^Qk_#&By1SMm`+Hcgd&vh&LY}&c<2)a1`GqpX$Tl ze0&(WvwRRY$LF)x$G25^bx7M{r-~n}+pV>u;zw46Y7epV%i6K=OxAX;OZ@Ehv#rD8 zN7m6IbV1A2BxRYwV4({s;;(?_9quKb$!iPU+1h8p;kKdj-D6x;u@D zb;EV~edC1xj^xUd<}6q8oaRdYfo=1Q*5&#*4Q@IxrIw#yZ!W2w2Wl? za#f2W)9!O5DNG?C=k3PDD9$!}JaFUmRlf<_pkDc;Y92x3`AJt`Y*0K9E z$M!8;l!a3ohR8}gOSn%wA1&iE#30^kINnygevUeFR>(@kAuVZJjOhtmJ^)f$`E21g zkU2+r89y%k(fd}EFaG+kzc)IrJ+C9rL=472pXXr?!!IpT&wlYN%Q&$z`$<{)iNCwx z0j>p6$~jt-`~<+_iVOM4NeXxEtMR`4hefPt9N#rf+DSDCdM4X1+LBWO?qaLl9*_Fj z-q1t=aeOB=Y0H98faKaj%tt&hgoWadLD-;nytmN9koR%bZ`nz$O^&=aY#Lf24 zfJ{Btmh7s~)0TUAc`%HUQflaYJq|nroRD%U7H)^l-@gI!BrdkewdtRF*em(py2#3l zh^q^))c8f7LVoDT^f!mn*jrpeo-3l2ZJCuXplsVIe;Rqloh^S3c_zxRvv~W;#m(E- zpS^T>^Tx9`uHLwH`T1*4ZCt)oVGx^(-?(-4dS~v|PRf@MNSzqD59h>F2%%h>sXM=(0vLSB@jT8s?_$64Z%Ryqkhn1r&*V_vJ zWMwS)poKR&x)K)IXc!*&`1%v=$0Og7(|G8EcHFmsBp#0Um-Fplh`;%$ezY5h(dOtN zj}+Eq*bC5m%L26g`ky@LbnO-Gg(4Vk;a@_Iy84=1D@&D@vGbi*$!i{eP(&||$x6uw zIe$1#d-yh4+rodh@c*rHXHq4e;9ETX`C0zq)eD9@{$AW4ZL1}1T+`F}Y&^=xBY%jm zex=&V(| z19Yk0>}b>xIXGz?7TIo=j9fk1XwnDCUT{$Q2pFC+?7NX_?<(T{*5tn)&1;k8!FU*g zQuLxPBZj6Rl-p__zv_TLdAu*(S4lJ&ZKgr76%SPrZ*5lsIvEwVB+2$_VY@sShMNig cC%IeYm{Ggp5}YwRDjbe5zk<9}y*yX{12fDJpa1{> literal 0 HcmV?d00001 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-base-gicv3-psci.dts b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-base-gicv3-psci.dts new file mode 100644 index 0000000..da090f5 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-base-gicv3-psci.dts @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { +}; + +/ { + model = "FVP Base"; + compatible = "arm,vfp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU4:cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU5:cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU6:cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU7:cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, // GICD + <0x0 0x2f100000 0 0x200000>, // GICR + <0x0 0x2c000000 0 0x2000>, // GICC + <0x0 0x2c010000 0 0x2000>, // GICH + <0x0 0x2c02f000 0 0x2000>; // GICV + interrupts = <1 9 4>; + + its: its@2f020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x2f020000 0x0 0x20000>; // GITS + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 0 0 4>, + <0 0 1 &gic 0 0 0 1 4>, + <0 0 2 &gic 0 0 0 2 4>, + <0 0 3 &gic 0 0 0 3 4>, + <0 0 4 &gic 0 0 0 4 4>, + <0 0 5 &gic 0 0 0 5 4>, + <0 0 6 &gic 0 0 0 6 4>, + <0 0 7 &gic 0 0 0 7 4>, + <0 0 8 &gic 0 0 0 8 4>, + <0 0 9 &gic 0 0 0 9 4>, + <0 0 10 &gic 0 0 0 10 4>, + <0 0 11 &gic 0 0 0 11 4>, + <0 0 12 &gic 0 0 0 12 4>, + <0 0 13 &gic 0 0 0 13 4>, + <0 0 14 &gic 0 0 0 14 4>, + <0 0 15 &gic 0 0 0 15 4>, + <0 0 16 &gic 0 0 0 16 4>, + <0 0 17 &gic 0 0 0 17 4>, + <0 0 18 &gic 0 0 0 18 4>, + <0 0 19 &gic 0 0 0 19 4>, + <0 0 20 &gic 0 0 0 20 4>, + <0 0 21 &gic 0 0 0 21 4>, + <0 0 22 &gic 0 0 0 22 4>, + <0 0 23 &gic 0 0 0 23 4>, + <0 0 24 &gic 0 0 0 24 4>, + <0 0 25 &gic 0 0 0 25 4>, + <0 0 26 &gic 0 0 0 26 4>, + <0 0 27 &gic 0 0 0 27 4>, + <0 0 28 &gic 0 0 0 28 4>, + <0 0 29 &gic 0 0 0 29 4>, + <0 0 30 &gic 0 0 0 30 4>, + <0 0 31 &gic 0 0 0 31 4>, + <0 0 32 &gic 0 0 0 32 4>, + <0 0 33 &gic 0 0 0 33 4>, + <0 0 34 &gic 0 0 0 34 4>, + <0 0 35 &gic 0 0 0 35 4>, + <0 0 36 &gic 0 0 0 36 4>, + <0 0 37 &gic 0 0 0 37 4>, + <0 0 38 &gic 0 0 0 38 4>, + <0 0 39 &gic 0 0 0 39 4>, + <0 0 40 &gic 0 0 0 40 4>, + <0 0 41 &gic 0 0 0 41 4>, + <0 0 42 &gic 0 0 0 42 4>; + + /include/ "rtsm_ve-motherboard-no_psci.dtsi" + }; + + panels { + panel@0 { + compatible = "panel"; + mode = "XVGA"; + refresh = <60>; + xres = <1024>; + yres = <768>; + pixclock = <15748>; + left_margin = <152>; + right_margin = <48>; + upper_margin = <23>; + lower_margin = <3>; + hsync_len = <104>; + vsync_len = <4>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + }; +}; diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv2-psci.dtb b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv2-psci.dtb new file mode 100644 index 0000000000000000000000000000000000000000..e45791813acf9562a198dd8ba4fc24c772867e92 GIT binary patch literal 7520 zcmbtZOONG76)rcECJls1fba;9G~Ee=(RJqD+XpsVAJ1(@b7xAjea`u+PJMOi z;d1%UkNxNG&VBa#&bil|d+HrLpTqS8uE%j9?feS%A5yx*8&lvPciq+cKG-i4d-aWP z?Y~;Ci)GZNWg)qVJ%wvGs`JU}vT1IRl@pLKc= z-z=NN*FijpvJ{@h8_QnB^~%*IKfaom?aib<_eV0AnDEpoJE*tk{rTtYCr_uu7hC|2_bK1k%^HYhrDAVWXy&@$v z*57OLm*w$ZiXq&!}wlrCiRH3jY56%_oo52SxzCJ#G+sWkghi>j^TmA$a=d0@PL0%gD zACTFe4iDIWyGDP1r~9`0*oF_oPipAvbKn>JbEwa~2k37`2fw{{23<;%lk%m^OJmLW zEyn#FT!sxS?(>JV>`9eGyBg=zvBL~ZC#A!Un zw&tYsYFkd^V>waweTg`Y$Mx2nw7uJM;yAUOsP~-4b7^Z%+TLwBA^(UI^}he|Brogp z#Wk*=NPr|S`aihrF`C4-ujA+rEl6+q$D?=r({)d2Z(3lbs@GK;#%0mgWtJuNV!j$` z@jjnLQ5myX%i82DjAk!}CuuB;vYM`o#n+*+eFdtv+t$|Ek{)8~KAq#+;WtT5s{lzy1O@rryOox;E3UmHIzs>wn4DAEK{WuH)y| ziz`2-35hI*wrL$*of3PtQ+3^!P)7=W#M`Ql@`PNDMqCiX;HSiKF~7zbqU@D4#)w(R z>1{$to)hbp7*~0}4&D`CAg40(=wIVY4=>}Qe;NID~hXhb< zoad4l5K|Un!1gL9#{B0#r`*|Q)N$$eu>Z!`DfS#8_jPu5#rU)s+n^X_i?J<=X}n;P z#C(cTw&mD1#VA{h?=QtDTTJIA%<_)27`sBtnQmcL*}Eymy^Sr$_pV};Eyi)87-fqg z?mb4?Vwn3qM%iLm3wn&Q#kil+`Y2nB!$2`JBw!uBHB`3cJ_4hbqinH{8jP~VIE=NN z8Pc#i_oTrn+j1W_7-frn!eEpw#wnupndt(nbDuI8Wm}HlWLl20#kg-$jIzZz{S-4( z5mtOu8jP|n_c?=6w%F4KqinH#gHg8F=M6^LVh0AJY_UUwQMTAK2BU1TXAMT#VqY*A zWs7~$V3aNPoWUqt>`MltY_Tf_qf9I?pSn3 z)^*f5T2tZLzxNV;aTiIum`|qjVfVxOIX`!syoo1SR9v6MvzgyW6XTl9@wUSSvm0f! zvz{1FmL(L#*{%5t`OP;WGj(O%?kYV?mSLQg@h!Ep>>nl95RW1#zN|Rbnc!W7;42sS zWLb`Nu5ZeNYbkZ%Q70=Dn<3YW1wNGr*I>(oy5Vs&zvV-+Jr8#W zuEaOiNXuj7Q+e<`VR=v&9vjCi^y>3+ZSwoS{5X=`!+5}T{$wA)n5%C05#*-(2;$D| z%ROk$n>smJOouI>l;`?88tb9Y$U-a+-WYGJ%^!VvpDy@ohqJx^hRn8gd}KWEy`?(G z19fRX+{bOU@M9iEBiB+v7ONGR@<;(96IDeq|~!zU*rqhj<6&Y-_Q@*E-_%+wf#@9{j77N)rx)(U2_y6ZPP&d@U6L^^J&TNda-J$b?45S@{KQTQ znVm9EacXO4c{kQOuJW3N52jInV$GS}lPh<(oAIL$UY0BQlPm2H#1%7kF?(tBE!_7r z)`_Egt`pq(Zt}!>A$;)c*9r2&sCT}fAZ)JyXNjZ~-<{QnrsglCW zQHxmj&mh(fgu)U-BDB1mX%*I_&=s|9D;3>cZD!s zk|I72aj=q{rEO^RJS{@hkuEhumKN)?Np&+S@E5`@lhZU#ZnWoB;xN46FG5h11!#rC zj|RkI2$m0y(fd=&A)<|w{dBmhlOL>EzpJC-1V26Ga4Rg<`7zG<1|RrugMT;8t+7d( z&MysryefZp4!vVf!pr5lt=4T=;MlBjCskUSgH(6u4bq{KU8(u(!^EP_K=>&bGJ1I$ s*X3!MwbmY;U1*Q8+tGOwqNBNM>A#b79@XjcWc&xS+g46i>mqjl16$~nA^-pY literal 0 HcmV?d00001 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv2-psci.dts b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv2-psci.dts new file mode 100644 index 0000000..5f93daa --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv2-psci.dts @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { +}; + +/ { + model = "FVP Foundation"; + compatible = "arm,fvp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, + <0x0 0x2c000000 0 0x2000>, + <0x0 0x2c010000 0 0x2000>, + <0x0 0x2c02F000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "fvp-foundation-motherboard.dtsi" + }; +}; diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv2legacy-psci.dtb b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv2legacy-psci.dtb new file mode 100644 index 0000000000000000000000000000000000000000..ac7555d91ec1dc00d75f0fe190746308a8cc9635 GIT binary patch literal 7520 zcmbtZOOGT+5zZRcg9k8U1Lk2K9%gJXt1eG>kBxVc4J}JpTtFPa2P8DEsji+WZM~?f zo}IA}USzm&;=loM;DY!8aNq}6TtV_5Fc-uHi34y1zAv((I%<1ZZSSU3oe}Y6Mt&Lj z?5aOM_Mg8y_t`g`bKh|8sdtb+hvx}AkK;kw`W5Uyq;!WrOo7kt`c>=uVBaP7+Uwum zd#zj+^QcYBLP`^R3eR>_=cC1W6`n**;;5V_7ge1!jTCb%cMT7D(68$IkhhFJ>GU8z zE1Sf(K|F}E6rRN!>mK5H<*><54)d}-OX`y{s^^Dkxu{N~+0kg+rNd=Zx3lq0s;J@H zW!y#`kT?gZ|9wrF15)?`BLViv1a^c z!|@JwVM7tA^8w@%OT_*B2Cd$Xc^G`!tGx|l7(8vphHbK3h@3I9JQz1}u)GGGhI4FV zPP(o((cp$1hLvvc8<% z;0}reNXlaTgI$l&B(^=BM|WsJddp{z-toEXa_MhcV5h2=RU5`-(bi>_CG~8Ije63x z;(b1gsxoJ>m$k`77)@RbPt#a7Wi{Oti*G|?`wCQz2V=bNVX;9BzSZF~%D|JQt%`GEb1sv$mM9jg|Yf6aXc)qF@`92C5S;{u<2^UzDLkGKph$Sk@QLYb~gHz^cnniwl0$Z zs*USh5(8rDLJZhn<;0l(+?SMJ_8Dzl`#tQxF?NbQN63Afon0~J7Gob2qiiwuMKO&R zOp;hmG0L_c`=%IWi}CzYjIzaaUBWD9oW(d4TF(p%i^|4SvTa43K z>zOGHt8-5pjIyowaf4B|*e47|*Q!6;koy1^(D3(Q|#sJa&izpER$t#YqneB~V0zu%+tX&zP+ z_W=7k+8peuaP7~%g#WmUq@7Ji<0+56)g6oLbGyl#c$7uO%}G3&_=_~TaZl!a+v0}V z%`)2APK=y&2?cR>Yx+Wd_9kSeuCCi&q!-CNjI%PnrFPc+qm)|3qX>#GD~^38co!k~ z$`w9Ymvf!_oATgZN?mx=$pY0T%4B06Zuiw0e6b$-=6PJh>N%ZhDU( z?%baI2F+ztC#N&HW{<@r^|}8J=6dK0vIOgcH|85#^Y>xz(*=L+aQ64#klDA6kIV<2 zTdH$DP?!G0ecWa=3dK@QNre!=AdRcLSUs(!_FUMNvArvl48t?NiFik$WtTt_eULfp5^MB{iZJc zzUw90pwCq{#uAseB3JjBJzMpeZN)I~enUU#yTpKf*Zx1j{AB!h#$LV#xLG${_s>- z=R>3ALw&&sf_+Kmw2UkYGUqx~ez-er z?f8YA6tX&Ho#L&nUFF?e@3_h_3m;5_@x-1pz9(1SZr9^SAABrV@+Vi?ABZbf>}>MV z)#HqP;^?0H1aH3UJh5L0ALRW$L4Md(wsx+H*Lhmw#Ixgf%D64_fRM$Ve0umdGxy7bGM#x z)9?M-;4d2;=B@AW2Tzd4F*5OUfP8S~jqoaJk)B?0{2Z zdhu38byBqMAeztlaVg{(+qi=!eKYCgCaKdX8#|xl;w$>J%a2@++iN*@c*lI)ESoAR zyj(68V#9YW9P`Ijc{{0Tqk@)_mZ(G9^(Edbi3?1zDC=G|HEmh>9fRLvI>#Z{MtN5W z^Cc7Rb_Kc`>Taq5@wb+&no?ss;T-3=AmTceEQE`fo9`bT4ESC8R-t(<|;JXdJ-88p` zCh0o=Y53Qx@^$CHJN6{JTrS&c*@gvPn>FsVN=x%1)g5?)45$=WYQFetVNquw{1OZq vy*!QU^1RGiYmY9jv`5+P=&}hh(7d(u|C4kb)#?0n_yx1OR*n|SB6j}+{q2+a literal 0 HcmV?d00001 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv2legacy-psci.dts b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv2legacy-psci.dts new file mode 100644 index 0000000..4238b33 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv2legacy-psci.dts @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { +}; + +/ { + model = "FVP Foundation"; + compatible = "arm,fvp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2c001000 0 0x1000>, + <0x0 0x2c002000 0 0x1000>, + <0x0 0x2c004000 0 0x2000>, + <0x0 0x2c006000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "fvp-foundation-motherboard.dtsi" + }; +}; diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv3-psci.dtb b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv3-psci.dtb new file mode 100644 index 0000000000000000000000000000000000000000..f3e0c5d3aa0b47bdb278d044f3f010b382336eab GIT binary patch literal 8148 zcmbtZ&yVCr6)ty@VHa4E@cYMx3^V))t9GWlXJI#pKnsb814xk&IUvE}?sm^uYqyQ< zo}CFoED9%191u4oIP(v1;=~2z!hs7HByK1YChBG8-<>if|THv7vAlpBH6ZRRS}_J&A`rXxGaJ$Pbh} zc5*O3&8yh9!SWzV6Id2&tb2s#<)bQ_9c6ia8ke&?Di=pdzAR3n>G5#n($P99>*?qv zil|}RW!w;sCgys0bwFRFPWJ+OT^L|%MOeK>w`Bt92m^x~uu zq=xtPcdBeog_jq<-yDnLC!1q&j&fq9{duu=L)p|naAn>e$BrogHq4^J=F@dm$EEc? z%knaIg0J@@0NI9Z2j$L?E^m3Dd_v1@KUkl0tEqp?(#`UxAp151mn_matm>$4=hRhT z-r&?#zLvgJX&e`!uqF?#1@V1r0~*^N-#>GCa{9GfTfQ&9g^ugd%YQ(Aq2xa!{|hC* zh5Vk9-*&R?tMzU8IQ#;;$~_cB&4awi!S{>2HaK z4BM3x`Djke+p&b7I`ev0PQJgpa-yF#C&~?{&RW`)lke}YoPgipM7bHiEY9-sVtShq z5(!0u<@i6aWmJi7-_N7_)F3ffAYHjHuVxRF{w6C#s&ZY_;XGf}WuB&SIh`!qR;EW(>{OL&bwjzn|Kq+c&EpnYleEym6a(6NnOzm6Yp$?Y2u*uLkJj3 z+Wvgk<-yvnO2giR@VjR5!juNm`S;RpSDR378g=n-Ee z@A?#EPyOq!fU9<=lj!!i=^1hF$J4Zb%eEh4Ua=m_oBrJRF;z%p(fF-t!?pQPb0Aoj zQ5KWS@dg)+Pw+$60`2+nV|zSz`SEKxy}=?R%c=2kku@>5<6o56Nlg3RzqIg0JhadB zG9I7jJoWi6yS$7ej$;tTN3uq$BrCAX&fLl2GJlXQ%g;faYobXA@V+tIBgh;eM}X~0 z`Y?W-j&>wn$FI|QzI341F{VhOLsVU4WgUA?^!ZO6lrQ!fZR}D1OQmPF;i&XY+pfHe zp{z0DOI4p)>NJLZ?AoDDW0>z^sM8qwpo^hSW4O0=G1O@cV{aEjoyKq|yBIaRD77)E zi}7(v0QkY0-m*iTZj1A;Ylk|G;Z*2i)bv29F^Dl+80xeg#GWk-bsEE1*=>tDjo~!x zV${?`Y5V_41o!hS-rCN4A$RRir!nvA!BD3$TxMN6YU!cWm=E+|sMB_MKI__{PGdgQ zgP~4ixWv15)UrpZF(2u{P^axMZg%bXSc)P^AH#1KL!Gw6@Y2PokRx`U>%mZ`?R>lk zL!HJv--Dq}WA=M6)M?BodN9;!%s~%^I*mE(!BD3$pX|XG_V{Y_ds3Rs&*AWn9PlG=AOlS+ulF4jU@YL5c5`K71z_r&>q~{bF!Sx{`U9-1L&f`TmPxJX*uV>xg399u+7OXz+%Mnk5H{pUW z^w=bqx9~8&J09k3Cku}tY2V(DmH68+kJA*ziVLmSt5VkEdiXcq^e@NS&qM4@ zgTT%cgFh&kf+i|vcM4{h95<{5Iy#y+wZV|K^XZjphC*s8M zrE!8M@@<~nlgNj0!^a8Ah$@4i&tGRri4RD3W;`Td$7pXntR2qoJ&PG;S&~B(``HASHyq4N9(*N$J)F?Vp?OuqdqRen>+ zP!GP&A3Q-epW`KV4)NYR-{CrOnVj@&xlOy@Lml=TdrE~v8@38-i@n{j6$*gGQWriM z`~Z2zY9`BNeJ z4X0+FX9YfT&eGVlm%>F<#;e*KMvDbMY=%5LROYZsUXNYAipwNQN5;N!pci@K-p3}x zsXSj8eE+ypt*atl*?hiSiVojY`Dp}=loz;g6fD+Al)5{}s?G}=^7zruSqMQZ%3LK( z_;@wH2yx>UpC@&w8jK9AoD-!nZ_x zPps~4s>Bog=VY(^<%{E?wP-one7>%Wbses7y;_-*BFQy@L#vR16nN!0S$G>LDAO-C wq=a;4mdwliEKh5#kIsAbQF<@Bs6q^|UN=J@7s_ODvia5A9g~O4^=fYZ2g;Sr^8f$< literal 0 HcmV?d00001 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv3-psci.dts b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv3-psci.dts new file mode 100644 index 0000000..daad1fb --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-gicv3-psci.dts @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { +}; + +/ { + model = "FVP Foundation"; + compatible = "arm,fvp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, // GICD + <0x0 0x2f100000 0 0x200000>, // GICR + <0x0 0x2c000000 0 0x2000>, // GICC + <0x0 0x2c010000 0 0x2000>, // GICH + <0x0 0x2c02f000 0 0x2000>; // GICV + interrupts = <1 9 4>; + + its: its@2f020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x2f020000 0x0 0x20000>; // GITS + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 0 0 4>, + <0 0 1 &gic 0 0 0 1 4>, + <0 0 2 &gic 0 0 0 2 4>, + <0 0 3 &gic 0 0 0 3 4>, + <0 0 4 &gic 0 0 0 4 4>, + <0 0 5 &gic 0 0 0 5 4>, + <0 0 6 &gic 0 0 0 6 4>, + <0 0 7 &gic 0 0 0 7 4>, + <0 0 8 &gic 0 0 0 8 4>, + <0 0 9 &gic 0 0 0 9 4>, + <0 0 10 &gic 0 0 0 10 4>, + <0 0 11 &gic 0 0 0 11 4>, + <0 0 12 &gic 0 0 0 12 4>, + <0 0 13 &gic 0 0 0 13 4>, + <0 0 14 &gic 0 0 0 14 4>, + <0 0 15 &gic 0 0 0 15 4>, + <0 0 16 &gic 0 0 0 16 4>, + <0 0 17 &gic 0 0 0 17 4>, + <0 0 18 &gic 0 0 0 18 4>, + <0 0 19 &gic 0 0 0 19 4>, + <0 0 20 &gic 0 0 0 20 4>, + <0 0 21 &gic 0 0 0 21 4>, + <0 0 22 &gic 0 0 0 22 4>, + <0 0 23 &gic 0 0 0 23 4>, + <0 0 24 &gic 0 0 0 24 4>, + <0 0 25 &gic 0 0 0 25 4>, + <0 0 26 &gic 0 0 0 26 4>, + <0 0 27 &gic 0 0 0 27 4>, + <0 0 28 &gic 0 0 0 28 4>, + <0 0 29 &gic 0 0 0 29 4>, + <0 0 30 &gic 0 0 0 30 4>, + <0 0 31 &gic 0 0 0 31 4>, + <0 0 32 &gic 0 0 0 32 4>, + <0 0 33 &gic 0 0 0 33 4>, + <0 0 34 &gic 0 0 0 34 4>, + <0 0 35 &gic 0 0 0 35 4>, + <0 0 36 &gic 0 0 0 36 4>, + <0 0 37 &gic 0 0 0 37 4>, + <0 0 38 &gic 0 0 0 38 4>, + <0 0 39 &gic 0 0 0 39 4>, + <0 0 40 &gic 0 0 0 40 4>, + <0 0 41 &gic 0 0 0 41 4>, + <0 0 42 &gic 0 0 0 42 4>; + + /include/ "fvp-foundation-motherboard-no_psci.dtsi" + }; +}; diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-motherboard-no_psci.dtsi b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-motherboard-no_psci.dtsi new file mode 100644 index 0000000..fd41c8a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-motherboard-no_psci.dtsi @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + motherboard { + arm,v2m-memory-map = "rs1"; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + ethernet@2,02000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + virtio_block@0130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x1000>; + interrupts = <0x2a>; + }; + }; + + v2m_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + + mcc { + compatible = "arm,vexpress,config-bus", "simple-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + reset@0 { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga@0 { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown@0 { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot@0 { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode@0 { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-motherboard.dtsi b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-motherboard.dtsi new file mode 100644 index 0000000..9d29e48 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/fdts/fvp-foundation-motherboard.dtsi @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + motherboard { + arm,v2m-memory-map = "rs1"; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + ethernet@2,02000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + virtio_block@0130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x1000>; + interrupts = <0x2a>; + }; + }; + + v2m_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + + mcc { + compatible = "arm,vexpress,config-bus", "simple-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + /* + * Not supported in FVP models + * + * reset@0 { + * compatible = "arm,vexpress-reset"; + * arm,vexpress-sysreg,func = <5 0>; + * }; + */ + + muxfpga@0 { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + /* + * Not used - Superseded by PSCI sys_poweroff + * + * shutdown@0 { + * compatible = "arm,vexpress-shutdown"; + * arm,vexpress-sysreg,func = <8 0>; + * }; + */ + + /* + * Not used - Superseded by PSCI sys_reset + * + * reboot@0 { + * compatible = "arm,vexpress-reboot"; + * arm,vexpress-sysreg,func = <9 0>; + * }; + */ + + dvimode@0 { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/rtsm_ve-motherboard-no_psci.dtsi b/IPL/SDK/v3m/src/Dummy_BL33/fdts/rtsm_ve-motherboard-no_psci.dtsi new file mode 100644 index 0000000..7ba575e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/fdts/rtsm_ve-motherboard-no_psci.dtsi @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + motherboard { + arm,v2m-memory-map = "rs1"; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; + }; + + vram@2,00000000 { + compatible = "arm,vexpress-vram"; + reg = <2 0x00000000 0x00800000>; + }; + + ethernet@2,02000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + + aaci@040000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + mmci@050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9 10>; + cd-gpios = <&v2m_sysreg 0 0>; + wp-gpios = <&v2m_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; + clock-names = "clcdclk", "apb_pclk"; + mode = "XVGA"; + use_dma = <0>; + framebuffer = <0x18000000 0x00180000>; + }; + + virtio_block@0130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x1000>; + interrupts = <0x2a>; + }; + }; + + v2m_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + mcc { + compatible = "arm,vexpress,config-bus", "simple-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + v2m_oscclk1: osc@1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + reset@0 { + compatible = "arm,vexpress-reset"; + arm,vexpress-sysreg,func = <5 0>; + }; + + muxfpga@0 { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + shutdown@0 { + compatible = "arm,vexpress-shutdown"; + arm,vexpress-sysreg,func = <8 0>; + }; + + reboot@0 { + compatible = "arm,vexpress-reboot"; + arm,vexpress-sysreg,func = <9 0>; + }; + + dvimode@0 { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; diff --git a/IPL/SDK/v3m/src/Dummy_BL33/fdts/rtsm_ve-motherboard.dtsi b/IPL/SDK/v3m/src/Dummy_BL33/fdts/rtsm_ve-motherboard.dtsi new file mode 100644 index 0000000..6aa40ff --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/fdts/rtsm_ve-motherboard.dtsi @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + motherboard { + arm,v2m-memory-map = "rs1"; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; + }; + + vram@2,00000000 { + compatible = "arm,vexpress-vram"; + reg = <2 0x00000000 0x00800000>; + }; + + ethernet@2,02000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + + aaci@040000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + mmci@050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9 10>; + cd-gpios = <&v2m_sysreg 0 0>; + wp-gpios = <&v2m_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; + clock-names = "clcdclk", "apb_pclk"; + mode = "XVGA"; + use_dma = <0>; + framebuffer = <0x18000000 0x00180000>; + }; + + virtio_block@0130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x1000>; + interrupts = <0x2a>; + }; + }; + + v2m_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + mcc { + compatible = "arm,vexpress,config-bus", "simple-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + v2m_oscclk1: osc@1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + /* + * Not supported in FVP models + * + * reset@0 { + * compatible = "arm,vexpress-reset"; + * arm,vexpress-sysreg,func = <5 0>; + * }; + */ + + muxfpga@0 { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + /* + * Not used - Superseded by PSCI sys_poweroff + * + * shutdown@0 { + * compatible = "arm,vexpress-shutdown"; + * arm,vexpress-sysreg,func = <8 0>; + * }; + */ + + /* + * Not used - Superseded by PSCI sys_reset + * + * reboot@0 { + * compatible = "arm,vexpress-reboot"; + * arm,vexpress-sysreg,func = <9 0>; + * }; + */ + + dvimode@0 { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/bl31.h b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/bl31.h new file mode 100644 index 0000000..96867b0 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/bl31.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BL31_H__ +#define __BL31_H__ + +#include + +/******************************************************************************* + * Function prototypes + ******************************************************************************/ +void bl31_arch_setup(void); +void bl31_next_el_arch_setup(uint32_t security_state); +void bl31_set_next_image_type(uint32_t type); +uint32_t bl31_get_next_image_type(void); +void bl31_prepare_next_image_entry(void); +void bl31_register_bl32_init(int32_t (*)(void)); + +#endif /* __BL31_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/context.h b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/context.h new file mode 100644 index 0000000..0dfebe0 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/context.h @@ -0,0 +1,341 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CONTEXT_H__ +#define __CONTEXT_H__ + +/******************************************************************************* + * Constants that allow assembler code to access members of and the 'gp_regs' + * structure at their correct offsets. + ******************************************************************************/ +#define CTX_GPREGS_OFFSET 0x0 +#define CTX_GPREG_X0 0x0 +#define CTX_GPREG_X1 0x8 +#define CTX_GPREG_X2 0x10 +#define CTX_GPREG_X3 0x18 +#define CTX_GPREG_X4 0x20 +#define CTX_GPREG_X5 0x28 +#define CTX_GPREG_X6 0x30 +#define CTX_GPREG_X7 0x38 +#define CTX_GPREG_X8 0x40 +#define CTX_GPREG_X9 0x48 +#define CTX_GPREG_X10 0x50 +#define CTX_GPREG_X11 0x58 +#define CTX_GPREG_X12 0x60 +#define CTX_GPREG_X13 0x68 +#define CTX_GPREG_X14 0x70 +#define CTX_GPREG_X15 0x78 +#define CTX_GPREG_X16 0x80 +#define CTX_GPREG_X17 0x88 +#define CTX_GPREG_X18 0x90 +#define CTX_GPREG_X19 0x98 +#define CTX_GPREG_X20 0xa0 +#define CTX_GPREG_X21 0xa8 +#define CTX_GPREG_X22 0xb0 +#define CTX_GPREG_X23 0xb8 +#define CTX_GPREG_X24 0xc0 +#define CTX_GPREG_X25 0xc8 +#define CTX_GPREG_X26 0xd0 +#define CTX_GPREG_X27 0xd8 +#define CTX_GPREG_X28 0xe0 +#define CTX_GPREG_X29 0xe8 +#define CTX_GPREG_LR 0xf0 +#define CTX_GPREG_SP_EL0 0xf8 +#define CTX_GPREGS_END 0x100 + +/******************************************************************************* + * Constants that allow assembler code to access members of and the 'el3_state' + * structure at their correct offsets. Note that some of the registers are only + * 32-bits wide but are stored as 64-bit values for convenience + ******************************************************************************/ +#define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) +#define CTX_SCR_EL3 0x0 +#define CTX_RUNTIME_SP 0x8 +#define CTX_SPSR_EL3 0x10 +#define CTX_ELR_EL3 0x18 +#define CTX_EL3STATE_END 0x20 + +/******************************************************************************* + * Constants that allow assembler code to access members of and the + * 'el1_sys_regs' structure at their correct offsets. Note that some of the + * registers are only 32-bits wide but are stored as 64-bit values for + * convenience + ******************************************************************************/ +#define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) +#define CTX_SPSR_EL1 0x0 +#define CTX_ELR_EL1 0x8 +#define CTX_SPSR_ABT 0x10 +#define CTX_SPSR_UND 0x18 +#define CTX_SPSR_IRQ 0x20 +#define CTX_SPSR_FIQ 0x28 +#define CTX_SCTLR_EL1 0x30 +#define CTX_ACTLR_EL1 0x38 +#define CTX_CPACR_EL1 0x40 +#define CTX_CSSELR_EL1 0x48 +#define CTX_SP_EL1 0x50 +#define CTX_ESR_EL1 0x58 +#define CTX_TTBR0_EL1 0x60 +#define CTX_TTBR1_EL1 0x68 +#define CTX_MAIR_EL1 0x70 +#define CTX_AMAIR_EL1 0x78 +#define CTX_TCR_EL1 0x80 +#define CTX_TPIDR_EL1 0x88 +#define CTX_TPIDR_EL0 0x90 +#define CTX_TPIDRRO_EL0 0x98 +#define CTX_DACR32_EL2 0xa0 +#define CTX_IFSR32_EL2 0xa8 +#define CTX_PAR_EL1 0xb0 +#define CTX_FAR_EL1 0xb8 +#define CTX_AFSR0_EL1 0xc0 +#define CTX_AFSR1_EL1 0xc8 +#define CTX_CONTEXTIDR_EL1 0xd0 +#define CTX_VBAR_EL1 0xd8 +/* + * If the timer registers aren't saved and restored, we don't have to reserve + * space for them in the context + */ +#if NS_TIMER_SWITCH +#define CTX_CNTP_CTL_EL0 0xe0 +#define CTX_CNTP_CVAL_EL0 0xe8 +#define CTX_CNTV_CTL_EL0 0xf0 +#define CTX_CNTV_CVAL_EL0 0xf8 +#define CTX_CNTKCTL_EL1 0x100 +#define CTX_FP_FPEXC32_EL2 0x108 +#define CTX_SYSREGS_END 0x110 +#else +#define CTX_FP_FPEXC32_EL2 0xe0 +#define CTX_SYSREGS_END 0xf0 +#endif + +/******************************************************************************* + * Constants that allow assembler code to access members of and the 'fp_regs' + * structure at their correct offsets. + ******************************************************************************/ +#if CTX_INCLUDE_FPREGS +#define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) +#define CTX_FP_Q0 0x0 +#define CTX_FP_Q1 0x10 +#define CTX_FP_Q2 0x20 +#define CTX_FP_Q3 0x30 +#define CTX_FP_Q4 0x40 +#define CTX_FP_Q5 0x50 +#define CTX_FP_Q6 0x60 +#define CTX_FP_Q7 0x70 +#define CTX_FP_Q8 0x80 +#define CTX_FP_Q9 0x90 +#define CTX_FP_Q10 0xa0 +#define CTX_FP_Q11 0xb0 +#define CTX_FP_Q12 0xc0 +#define CTX_FP_Q13 0xd0 +#define CTX_FP_Q14 0xe0 +#define CTX_FP_Q15 0xf0 +#define CTX_FP_Q16 0x100 +#define CTX_FP_Q17 0x110 +#define CTX_FP_Q18 0x120 +#define CTX_FP_Q19 0x130 +#define CTX_FP_Q20 0x140 +#define CTX_FP_Q21 0x150 +#define CTX_FP_Q22 0x160 +#define CTX_FP_Q23 0x170 +#define CTX_FP_Q24 0x180 +#define CTX_FP_Q25 0x190 +#define CTX_FP_Q26 0x1a0 +#define CTX_FP_Q27 0x1b0 +#define CTX_FP_Q28 0x1c0 +#define CTX_FP_Q29 0x1d0 +#define CTX_FP_Q30 0x1e0 +#define CTX_FP_Q31 0x1f0 +#define CTX_FP_FPSR 0x200 +#define CTX_FP_FPCR 0x208 +#define CTX_FPREGS_END 0x210 +#endif + +#ifndef __ASSEMBLY__ + +#include +#include /* for CACHE_WRITEBACK_GRANULE */ +#include + +/* + * Common constants to help define the 'cpu_context' structure and its + * members below. + */ +#define DWORD_SHIFT 3 +#define DEFINE_REG_STRUCT(name, num_regs) \ + typedef struct name { \ + uint64_t _regs[num_regs]; \ + } __aligned(16) name##_t + +/* Constants to determine the size of individual context structures */ +#define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) +#define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT) +#if CTX_INCLUDE_FPREGS +#define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) +#endif +#define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) + +/* + * AArch64 general purpose register context structure. Usually x0-x18, + * lr are saved as the compiler is expected to preserve the remaining + * callee saved registers if used by the C runtime and the assembler + * does not touch the remaining. But in case of world switch during + * exception handling, we need to save the callee registers too. + */ +DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); + +/* + * AArch64 EL1 system register context structure for preserving the + * architectural state during switches from one security state to + * another in EL1. + */ +DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL); + +/* + * AArch64 floating point register context structure for preserving + * the floating point state during switches from one security state to + * another. + */ +#if CTX_INCLUDE_FPREGS +DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); +#endif + +/* + * Miscellaneous registers used by EL3 firmware to maintain its state + * across exception entries and exits + */ +DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); + +/* + * Macros to access members of any of the above structures using their + * offsets + */ +#define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> DWORD_SHIFT]) +#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> DWORD_SHIFT]) \ + = val) + +/* + * Top-level context structure which is used by EL3 firmware to + * preserve the state of a core at EL1 in one of the two security + * states and save enough EL3 meta data to be able to return to that + * EL and security state. The context management library will be used + * to ensure that SP_EL3 always points to an instance of this + * structure at exception entry and exit. Each instance will + * correspond to either the secure or the non-secure state. + */ +typedef struct cpu_context { + gp_regs_t gpregs_ctx; + el3_state_t el3state_ctx; + el1_sys_regs_t sysregs_ctx; +#if CTX_INCLUDE_FPREGS + fp_regs_t fpregs_ctx; +#endif +} cpu_context_t; + +/* Macros to access members of the 'cpu_context_t' structure */ +#define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) +#if CTX_INCLUDE_FPREGS +#define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) +#endif +#define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx) +#define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) + +/* + * Compile time assertions related to the 'cpu_context' structure to + * ensure that the assembler and the compiler view of the offsets of + * the structure members is the same. + */ +CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \ + assert_core_context_gp_offset_mismatch); +CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \ + assert_core_context_sys_offset_mismatch); +#if CTX_INCLUDE_FPREGS +CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \ + assert_core_context_fp_offset_mismatch); +#endif +CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \ + assert_core_context_el3state_offset_mismatch); + +/* + * Helper macro to set the general purpose registers that correspond to + * parameters in an aapcs_64 call i.e. x0-x7 + */ +#define set_aapcs_args0(ctx, x0) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ + } while (0); +#define set_aapcs_args1(ctx, x0, x1) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ + set_aapcs_args0(ctx, x0); \ + } while (0); +#define set_aapcs_args2(ctx, x0, x1, x2) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ + set_aapcs_args1(ctx, x0, x1); \ + } while (0); +#define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ + set_aapcs_args2(ctx, x0, x1, x2); \ + } while (0); +#define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ + set_aapcs_args3(ctx, x0, x1, x2, x3); \ + } while (0); +#define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ + set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ + } while (0); +#define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ + set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ + } while (0); +#define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ + set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ + } while (0); + +/******************************************************************************* + * Function prototypes + ******************************************************************************/ +void el1_sysregs_context_save(el1_sys_regs_t *regs); +void el1_sysregs_context_restore(el1_sys_regs_t *regs); +#if CTX_INCLUDE_FPREGS +void fpregs_context_save(fp_regs_t *regs); +void fpregs_context_restore(fp_regs_t *regs); +#endif + + +#undef CTX_SYSREG_ALL +#if CTX_INCLUDE_FPREGS +#undef CTX_FPREG_ALL +#endif +#undef CTX_GPREG_ALL +#undef CTX_EL3STATE_ALL + +#endif /* __ASSEMBLY__ */ + +#endif /* __CONTEXT_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/context_mgmt.h b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/context_mgmt.h new file mode 100644 index 0000000..1ef4076 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/context_mgmt.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CM_H__ +#define __CM_H__ + +#include +#include +#include + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct entry_point_info; + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void cm_init(void); +void *cm_get_context_by_mpidr(uint64_t mpidr, + uint32_t security_state) __warn_deprecated; +static inline void *cm_get_context(uint32_t security_state); +void cm_set_context_by_mpidr(uint64_t mpidr, + void *context, + uint32_t security_state) __warn_deprecated; +void *cm_get_context_by_index(unsigned int cpu_idx, + unsigned int security_state); +void cm_set_context_by_index(unsigned int cpu_idx, + void *context, + unsigned int security_state); +static inline void cm_set_context(void *context, uint32_t security_state); +void cm_init_context(uint64_t mpidr, + const struct entry_point_info *ep) __warn_deprecated; +void cm_init_my_context(const struct entry_point_info *ep); +void cm_init_context_by_index(unsigned int cpu_idx, + const struct entry_point_info *ep); +void cm_prepare_el3_exit(uint32_t security_state); +void cm_el1_sysregs_context_save(uint32_t security_state); +void cm_el1_sysregs_context_restore(uint32_t security_state); +void cm_set_elr_el3(uint32_t security_state, uint64_t entrypoint); +void cm_set_elr_spsr_el3(uint32_t security_state, + uint64_t entrypoint, uint32_t spsr); +void cm_write_scr_el3_bit(uint32_t security_state, + uint32_t bit_pos, + uint32_t value); +void cm_set_next_eret_context(uint32_t security_state); +uint32_t cm_get_scr_el3(uint32_t security_state); + +/* Inline definitions */ + +/******************************************************************************* + * This function returns a pointer to the most recent 'cpu_context' structure + * for the calling CPU that was set as the context for the specified security + * state. NULL is returned if no such structure has been specified. + ******************************************************************************/ +void *cm_get_context(uint32_t security_state) +{ + assert(security_state <= NON_SECURE); + + return get_cpu_data(cpu_context[security_state]); +} + +/******************************************************************************* + * This function sets the pointer to the current 'cpu_context' structure for the + * specified security state for the calling CPU + ******************************************************************************/ +void cm_set_context(void *context, uint32_t security_state) +{ + assert(security_state <= NON_SECURE); + + set_cpu_data(cpu_context[security_state], context); +} + + +#endif /* __CM_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/cpu_data.h b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/cpu_data.h new file mode 100644 index 0000000..2b506c7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/cpu_data.h @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CPU_DATA_H__ +#define __CPU_DATA_H__ + +/* Offsets for the cpu_data structure */ +#define CPU_DATA_CRASH_BUF_OFFSET 0x18 +#if CRASH_REPORTING +#define CPU_DATA_LOG2SIZE 7 +#else +#define CPU_DATA_LOG2SIZE 6 +#endif +/* need enough space in crash buffer to save 8 registers */ +#define CPU_DATA_CRASH_BUF_SIZE 64 +#define CPU_DATA_CPU_OPS_PTR 0x10 + +#ifndef __ASSEMBLY__ + +#include +#include +#include +#include +#include + +/* Offsets for the cpu_data structure */ +#define CPU_DATA_PSCI_LOCK_OFFSET __builtin_offsetof\ + (cpu_data_t, psci_svc_cpu_data.pcpu_bakery_info) + +#if PLAT_PCPU_DATA_SIZE +#define CPU_DATA_PLAT_PCPU_OFFSET __builtin_offsetof\ + (cpu_data_t, platform_cpu_data) +#endif + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ + +/******************************************************************************* + * Cache of frequently used per-cpu data: + * Pointers to non-secure and secure security state contexts + * Address of the crash stack + * It is aligned to the cache line boundary to allow efficient concurrent + * manipulation of these pointers on different cpus + * + * TODO: Add other commonly used variables to this (tf_issues#90) + * + * The data structure and the _cpu_data accessors should not be used directly + * by components that have per-cpu members. The member access macros should be + * used for this. + ******************************************************************************/ +typedef struct cpu_data { + void *cpu_context[2]; + uint64_t cpu_ops_ptr; +#if CRASH_REPORTING + uint64_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3]; +#endif + struct psci_cpu_data psci_svc_cpu_data; +#if PLAT_PCPU_DATA_SIZE + uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE]; +#endif +} __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t; + +#if CRASH_REPORTING +/* verify assembler offsets match data structures */ +CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof + (cpu_data_t, crash_buf), + assert_cpu_data_crash_stack_offset_mismatch); +#endif + +CASSERT((1 << CPU_DATA_LOG2SIZE) == sizeof(cpu_data_t), + assert_cpu_data_log2size_mismatch); + +CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof + (cpu_data_t, cpu_ops_ptr), + assert_cpu_data_cpu_ops_ptr_offset_mismatch); + +struct cpu_data *_cpu_data_by_index(uint32_t cpu_index); + +/* Return the cpu_data structure for the current CPU. */ +static inline struct cpu_data *_cpu_data(void) +{ + return (cpu_data_t *)read_tpidr_el3(); +} + + +/************************************************************************** + * APIs for initialising and accessing per-cpu data + *************************************************************************/ + +void init_cpu_data_ptr(void); +void init_cpu_ops(void); + +#define get_cpu_data(_m) _cpu_data()->_m +#define set_cpu_data(_m, _v) _cpu_data()->_m = _v +#define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m +#define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = _v + +#define flush_cpu_data(_m) flush_dcache_range((uint64_t) \ + &(_cpu_data()->_m), \ + sizeof(_cpu_data()->_m)) +#define inv_cpu_data(_m) inv_dcache_range((uint64_t) \ + &(_cpu_data()->_m), \ + sizeof(_cpu_data()->_m)) +#define flush_cpu_data_by_index(_ix, _m) \ + flush_dcache_range((uint64_t) \ + &(_cpu_data_by_index(_ix)->_m), \ + sizeof(_cpu_data_by_index(_ix)->_m)) + + +#endif /* __ASSEMBLY__ */ +#endif /* __CPU_DATA_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/interrupt_mgmt.h b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/interrupt_mgmt.h new file mode 100644 index 0000000..e07ddf8 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/interrupt_mgmt.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __INTERRUPT_MGMT_H__ +#define __INTERRUPT_MGMT_H__ + +#include + +/******************************************************************************* + * Constants for the types of interrupts recognised by the IM framework + ******************************************************************************/ +#define INTR_TYPE_S_EL1 0 +#define INTR_TYPE_EL3 1 +#define INTR_TYPE_NS 2 +#define MAX_INTR_TYPES 3 +#define INTR_TYPE_INVAL MAX_INTR_TYPES +/* + * Constant passed to the interrupt handler in the 'id' field when the + * framework does not read the gic registers to determine the interrupt id. + */ +#define INTR_ID_UNAVAILABLE 0xFFFFFFFF + + +/******************************************************************************* + * Mask for _both_ the routing model bits in the 'flags' parameter and + * constants to define the valid routing models for each supported interrupt + * type + ******************************************************************************/ +#define INTR_RM_FLAGS_SHIFT 0x0 +#define INTR_RM_FLAGS_MASK 0x3 +/* Routed to EL3 from NS. Taken to S-EL1 from Secure */ +#define INTR_SEL1_VALID_RM0 0x2 +/* Routed to EL3 from NS and Secure */ +#define INTR_SEL1_VALID_RM1 0x3 +/* Routed to EL1/EL2 from NS and to S-EL1 from Secure */ +#define INTR_NS_VALID_RM0 0x0 +/* Routed to EL1/EL2 from NS and to EL3 from Secure */ +#define INTR_NS_VALID_RM1 0x1 +/* This is the default routing model */ +#define INTR_DEFAULT_RM 0x0 + +/******************************************************************************* + * Constants for the _individual_ routing model bits in the 'flags' field for + * each interrupt type and mask to validate the 'flags' parameter while + * registering an interrupt handler + ******************************************************************************/ +#define INTR_TYPE_FLAGS_MASK 0xFFFFFFFC + +#define INTR_RM_FROM_SEC_SHIFT SECURE /* BIT[0] */ +#define INTR_RM_FROM_NS_SHIFT NON_SECURE /* BIT[1] */ +#define INTR_RM_FROM_FLAG_MASK 1 +#define get_interrupt_rm_flag(flag, ss) (((flag >> INTR_RM_FLAGS_SHIFT) >> ss) \ + & INTR_RM_FROM_FLAG_MASK) +#define set_interrupt_rm_flag(flag, ss) (flag |= 1 << ss) +#define clr_interrupt_rm_flag(flag, ss) (flag &= ~(1 << ss)) + + +/******************************************************************************* + * Macros to validate the routing model bits in the 'flags' for a type + * of interrupt. If the model does not match one of the valid masks + * -EINVAL is returned. + ******************************************************************************/ +#define validate_sel1_interrupt_rm(x) (x == INTR_SEL1_VALID_RM0 ? 0 : \ + (x == INTR_SEL1_VALID_RM1 ? 0 :\ + -EINVAL)) + +#define validate_ns_interrupt_rm(x) (x == INTR_NS_VALID_RM0 ? 0 : \ + (x == INTR_NS_VALID_RM1 ? 0 :\ + -EINVAL)) + +/******************************************************************************* + * Macros to set the 'flags' parameter passed to an interrupt type handler. Only + * the flag to indicate the security state when the exception was generated is + * supported. + ******************************************************************************/ +#define INTR_SRC_SS_FLAG_SHIFT 0 /* BIT[0] */ +#define INTR_SRC_SS_FLAG_MASK 1 +#define set_interrupt_src_ss(flag, val) (flag |= val << INTR_SRC_SS_FLAG_SHIFT) +#define clr_interrupt_src_ss(flag) (flag &= ~(1 << INTR_SRC_SS_FLAG_SHIFT)) +#define get_interrupt_src_ss(flag) ((flag >> INTR_SRC_SS_FLAG_SHIFT) & \ + INTR_SRC_SS_FLAG_MASK) + +#ifndef __ASSEMBLY__ + +/* Prototype for defining a handler for an interrupt type */ +typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, + uint32_t flags, + void *handle, + void *cookie); + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +uint32_t get_scr_el3_from_routing_model(uint32_t security_state); +int32_t set_routing_model(uint32_t type, uint32_t flags); +int32_t register_interrupt_type_handler(uint32_t type, + interrupt_type_handler_t handler, + uint32_t flags); +interrupt_type_handler_t get_interrupt_type_handler(uint32_t interrupt_type); +int disable_intr_rm_local(uint32_t type, uint32_t security_state); +int enable_intr_rm_local(uint32_t type, uint32_t security_state); + +#endif /*__ASSEMBLY__*/ +#endif /* __INTERRUPT_MGMT_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/runtime_svc.h b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/runtime_svc.h new file mode 100644 index 0000000..f112418 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/runtime_svc.h @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __RUNTIME_SVC_H__ +#define __RUNTIME_SVC_H__ + +/******************************************************************************* + * Bit definitions inside the function id as per the SMC calling convention + ******************************************************************************/ +#define FUNCID_TYPE_SHIFT 31 +#define FUNCID_CC_SHIFT 30 +#define FUNCID_OEN_SHIFT 24 +#define FUNCID_NUM_SHIFT 0 + +#define FUNCID_TYPE_MASK 0x1 +#define FUNCID_CC_MASK 0x1 +#define FUNCID_OEN_MASK 0x3f +#define FUNCID_NUM_MASK 0xffff + +#define FUNCID_TYPE_WIDTH 1 +#define FUNCID_CC_WIDTH 1 +#define FUNCID_OEN_WIDTH 6 +#define FUNCID_NUM_WIDTH 16 + +#define GET_SMC_CC(id) ((id >> FUNCID_CC_SHIFT) & \ + FUNCID_CC_MASK) +#define GET_SMC_TYPE(id) ((id >> FUNCID_TYPE_SHIFT) & \ + FUNCID_TYPE_MASK) + +#define SMC_64 1 +#define SMC_32 0 +#define SMC_UNK 0xffffffff +#define SMC_TYPE_FAST 1 +#define SMC_TYPE_STD 0 +#define SMC_PREEMPTED 0xfffffffe +/******************************************************************************* + * Owning entity number definitions inside the function id as per the SMC + * calling convention + ******************************************************************************/ +#define OEN_ARM_START 0 +#define OEN_ARM_END 0 +#define OEN_CPU_START 1 +#define OEN_CPU_END 1 +#define OEN_SIP_START 2 +#define OEN_SIP_END 2 +#define OEN_OEM_START 3 +#define OEN_OEM_END 3 +#define OEN_STD_START 4 /* Standard Calls */ +#define OEN_STD_END 4 +#define OEN_TAP_START 48 /* Trusted Applications */ +#define OEN_TAP_END 49 +#define OEN_TOS_START 50 /* Trusted OS */ +#define OEN_TOS_END 63 +#define OEN_LIMIT 64 + +/******************************************************************************* + * Constants to indicate type of exception to the common exception handler. + ******************************************************************************/ +#define SYNC_EXCEPTION_SP_EL0 0x0 +#define IRQ_SP_EL0 0x1 +#define FIQ_SP_EL0 0x2 +#define SERROR_SP_EL0 0x3 +#define SYNC_EXCEPTION_SP_ELX 0x4 +#define IRQ_SP_ELX 0x5 +#define FIQ_SP_ELX 0x6 +#define SERROR_SP_ELX 0x7 +#define SYNC_EXCEPTION_AARCH64 0x8 +#define IRQ_AARCH64 0x9 +#define FIQ_AARCH64 0xa +#define SERROR_AARCH64 0xb +#define SYNC_EXCEPTION_AARCH32 0xc +#define IRQ_AARCH32 0xd +#define FIQ_AARCH32 0xe +#define SERROR_AARCH32 0xf + +/******************************************************************************* + * Structure definition, typedefs & constants for the runtime service framework + ******************************************************************************/ + +/* + * Constants to allow the assembler access a runtime service + * descriptor + */ +#define RT_SVC_SIZE_LOG2 5 +#define SIZEOF_RT_SVC_DESC (1 << RT_SVC_SIZE_LOG2) +#define RT_SVC_DESC_INIT 16 +#define RT_SVC_DESC_HANDLE 24 + +/* + * The function identifier has 6 bits for the owning entity number and + * single bit for the type of smc call. When taken together these + * values limit the maximum number of runtime services to 128. + */ +#define MAX_RT_SVCS 128 + +#ifndef __ASSEMBLY__ + +#include +#include +#include + +/* Various flags passed to SMC handlers */ +#define SMC_FROM_SECURE (0 << 0) +#define SMC_FROM_NON_SECURE (1 << 0) + +#define is_caller_non_secure(_f) (!!(_f & SMC_FROM_NON_SECURE)) +#define is_caller_secure(_f) (!(is_caller_non_secure(_f))) + +/* Prototype for runtime service initializing function */ +typedef int32_t (*rt_svc_init_t)(void); + +/* Convenience macros to return from SMC handler */ +#define SMC_RET0(_h) { \ + return (uint64_t) (_h); \ +} +#define SMC_RET1(_h, _x0) { \ + write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X0, (_x0)); \ + SMC_RET0(_h); \ +} +#define SMC_RET2(_h, _x0, _x1) { \ + write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X1, (_x1)); \ + SMC_RET1(_h, (_x0)); \ +} +#define SMC_RET3(_h, _x0, _x1, _x2) { \ + write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X2, (_x2)); \ + SMC_RET2(_h, (_x0), (_x1)); \ +} +#define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \ + write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X3, (_x3)); \ + SMC_RET3(_h, (_x0), (_x1), (_x2)); \ +} + + +/* + * Convenience macros to access general purpose registers using handle provided + * to SMC handler. These takes the offset values defined in context.h + */ +#define SMC_GET_GP(_h, _g) \ + read_ctx_reg(get_gpregs_ctx(_h), (_g)); +#define SMC_SET_GP(_h, _g, _v) \ + write_ctx_reg(get_gpregs_ctx(_h), (_g), (_v)); + +/* + * Convenience macros to access EL3 context registers using handle provided to + * SMC handler. These takes the offset values defined in context.h + */ +#define SMC_GET_EL3(_h, _e) \ + read_ctx_reg(get_el3state_ctx(_h), (_e)); +#define SMC_SET_EL3(_h, _e, _v) \ + write_ctx_reg(get_el3state_ctx(_h), (_e), (_v)); + +/* The macro below is used to identify a Standard Service SMC call */ +#define is_std_svc_call(_fid) ((((_fid) >> FUNCID_OEN_SHIFT) & \ + FUNCID_OEN_MASK) == OEN_STD_START) + +/* The macro below is used to identify a valid Fast SMC call */ +#define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & 0xff)) && \ + (GET_SMC_TYPE(_fid) == SMC_TYPE_FAST)) + +/* + * Prototype for runtime service SMC handler function. x0 (SMC Function ID) to + * x4 are as passed by the caller. Rest of the arguments to SMC and the context + * can be accessed using the handle pointer. The cookie parameter is reserved + * for future use + */ +typedef uint64_t (*rt_svc_handle_t)(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags); +typedef struct rt_svc_desc { + uint8_t start_oen; + uint8_t end_oen; + uint8_t call_type; + const char *name; + rt_svc_init_t init; + rt_svc_handle_t handle; +} rt_svc_desc_t; + +/* + * Convenience macro to declare a service descriptor + */ +#define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) \ + static const rt_svc_desc_t __svc_desc_ ## _name \ + __attribute__ ((section("rt_svc_descs"), used)) = { \ + _start, \ + _end, \ + _type, \ + #_name, \ + _setup, \ + _smch } + +/* + * Compile time assertions related to the 'rt_svc_desc' structure to: + * 1. ensure that the assembler and the compiler view of the size + * of the structure are the same. + * 2. ensure that the assembler and the compiler see the initialisation + * routine at the same offset. + * 3. ensure that the assembler and the compiler see the handler + * routine at the same offset. + */ +CASSERT((sizeof(rt_svc_desc_t) == SIZEOF_RT_SVC_DESC), \ + assert_sizeof_rt_svc_desc_mismatch); +CASSERT(RT_SVC_DESC_INIT == __builtin_offsetof(rt_svc_desc_t, init), \ + assert_rt_svc_desc_init_offset_mismatch); +CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle), \ + assert_rt_svc_desc_handle_offset_mismatch); + + +/* + * This macro combines the call type and the owning entity number corresponding + * to a runtime service to generate a unique owning entity number. This unique + * oen is used to access an entry in the 'rt_svc_descs_indices' array. The entry + * contains the index of the service descriptor in the 'rt_svc_descs' array. + */ +#define get_unique_oen(oen, call_type) ((oen & FUNCID_OEN_MASK) | \ + ((call_type & FUNCID_TYPE_MASK) \ + << FUNCID_OEN_WIDTH)) + + +/* + * Macro to define UUID for services. Apart from defining and initializing a + * uuid_t structure, this macro verifies that the first word of the defined UUID + * does not equal SMC_UNK. This is to ensure that the caller won't mistake the + * returned UUID in x0 for an invalid SMC error return + */ +#define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \ + _n0, _n1, _n2, _n3, _n4, _n5) \ + CASSERT(_tl != SMC_UNK, invalid_svc_uuid);\ + static const uuid_t _name = { \ + _tl, _tm, _th, _cl, _ch, \ + { _n0, _n1, _n2, _n3, _n4, _n5 } \ + } + +/* Return a UUID in the SMC return registers */ +#define SMC_UUID_RET(_h, _uuid) \ + SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \ + ((const uint32_t *) &(_uuid))[1], \ + ((const uint32_t *) &(_uuid))[2], \ + ((const uint32_t *) &(_uuid))[3]) + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void runtime_svc_init(void); +extern uint64_t __RT_SVC_DESCS_START__; +extern uint64_t __RT_SVC_DESCS_END__; +void init_crash_reporting(void); + +#endif /*__ASSEMBLY__*/ +#endif /* __RUNTIME_SVC_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/services/psci.h b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/services/psci.h new file mode 100644 index 0000000..6298a40 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/services/psci.h @@ -0,0 +1,330 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PSCI_H__ +#define __PSCI_H__ + +#include +#include /* for PLAT_NUM_PWR_DOMAINS */ +#if ENABLE_PLAT_COMPAT +#include +#endif + +/******************************************************************************* + * Number of power domains whose state this psci imp. can track + ******************************************************************************/ +#ifdef PLAT_NUM_PWR_DOMAINS +#define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS +#else +#define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT) +#endif + +#define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ + PLATFORM_CORE_COUNT) + +/* This is the power level corresponding to a CPU */ +#define PSCI_CPU_PWR_LVL 0 + +/* + * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND + * uses the old power_state parameter format which has 2 bits to specify the + * power level, this constant is defined to be 3. + */ +#define PSCI_MAX_PWR_LVL 3 + +/******************************************************************************* + * Defines for runtime services func ids + ******************************************************************************/ +#define PSCI_VERSION 0x84000000 +#define PSCI_CPU_SUSPEND_AARCH32 0x84000001 +#define PSCI_CPU_SUSPEND_AARCH64 0xc4000001 +#define PSCI_CPU_OFF 0x84000002 +#define PSCI_CPU_ON_AARCH32 0x84000003 +#define PSCI_CPU_ON_AARCH64 0xc4000003 +#define PSCI_AFFINITY_INFO_AARCH32 0x84000004 +#define PSCI_AFFINITY_INFO_AARCH64 0xc4000004 +#define PSCI_MIG_AARCH32 0x84000005 +#define PSCI_MIG_AARCH64 0xc4000005 +#define PSCI_MIG_INFO_TYPE 0x84000006 +#define PSCI_MIG_INFO_UP_CPU_AARCH32 0x84000007 +#define PSCI_MIG_INFO_UP_CPU_AARCH64 0xc4000007 +#define PSCI_SYSTEM_OFF 0x84000008 +#define PSCI_SYSTEM_RESET 0x84000009 +#define PSCI_FEATURES 0x8400000A +#define PSCI_SYSTEM_SUSPEND_AARCH32 0x8400000E +#define PSCI_SYSTEM_SUSPEND_AARCH64 0xc400000E + +/* Macro to help build the psci capabilities bitfield */ +#define define_psci_cap(x) (1 << (x & 0x1f)) + +/* + * Number of PSCI calls (above) implemented + */ +#define PSCI_NUM_CALLS 18 + +/******************************************************************************* + * PSCI Migrate and friends + ******************************************************************************/ +#define PSCI_TOS_UP_MIG_CAP 0 +#define PSCI_TOS_NOT_UP_MIG_CAP 1 +#define PSCI_TOS_NOT_PRESENT_MP 2 + +/******************************************************************************* + * PSCI CPU_SUSPEND 'power_state' parameter specific defines + ******************************************************************************/ +#define PSTATE_ID_SHIFT 0 + +#if PSCI_EXTENDED_STATE_ID +#define PSTATE_VALID_MASK 0xB0000000 +#define PSTATE_TYPE_SHIFT 30 +#define PSTATE_ID_MASK 0xfffffff +#else +#define PSTATE_VALID_MASK 0xFCFE0000 +#define PSTATE_TYPE_SHIFT 16 +#define PSTATE_PWR_LVL_SHIFT 24 +#define PSTATE_ID_MASK 0xffff +#define PSTATE_PWR_LVL_MASK 0x3 + +#define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \ + PSTATE_PWR_LVL_MASK) +#define psci_make_powerstate(state_id, type, pwrlvl) \ + (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\ + (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\ + (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT) +#endif /* __PSCI_EXTENDED_STATE_ID__ */ + +#define PSTATE_TYPE_STANDBY 0x0 +#define PSTATE_TYPE_POWERDOWN 0x1 +#define PSTATE_TYPE_MASK 0x1 + +#define psci_get_pstate_id(pstate) (((pstate) >> PSTATE_ID_SHIFT) & \ + PSTATE_ID_MASK) +#define psci_get_pstate_type(pstate) (((pstate) >> PSTATE_TYPE_SHIFT) & \ + PSTATE_TYPE_MASK) +#define psci_check_power_state(pstate) ((pstate) & PSTATE_VALID_MASK) + +/******************************************************************************* + * PSCI CPU_FEATURES feature flag specific defines + ******************************************************************************/ +/* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */ +#define FF_PSTATE_SHIFT 1 +#define FF_PSTATE_ORIG 0 +#define FF_PSTATE_EXTENDED 1 +#if PSCI_EXTENDED_STATE_ID +#define FF_PSTATE FF_PSTATE_EXTENDED +#else +#define FF_PSTATE FF_PSTATE_ORIG +#endif + +/* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */ +#define FF_MODE_SUPPORT_SHIFT 0 +#define FF_SUPPORTS_OS_INIT_MODE 1 + +/******************************************************************************* + * PSCI version + ******************************************************************************/ +#define PSCI_MAJOR_VER (1 << 16) +#define PSCI_MINOR_VER 0x0 + +/******************************************************************************* + * PSCI error codes + ******************************************************************************/ +#define PSCI_E_SUCCESS 0 +#define PSCI_E_NOT_SUPPORTED -1 +#define PSCI_E_INVALID_PARAMS -2 +#define PSCI_E_DENIED -3 +#define PSCI_E_ALREADY_ON -4 +#define PSCI_E_ON_PENDING -5 +#define PSCI_E_INTERN_FAIL -6 +#define PSCI_E_NOT_PRESENT -7 +#define PSCI_E_DISABLED -8 +#define PSCI_E_INVALID_ADDRESS -9 + +#define PSCI_INVALID_MPIDR ~((u_register_t)0) + +#ifndef __ASSEMBLY__ + +#include +#include + +/* + * These are the states reported by the PSCI_AFFINITY_INFO API for the specified + * CPU. The definitions of these states can be found in Section 5.7.1 in the + * PSCI specification (ARM DEN 0022C). + */ +typedef enum { + AFF_STATE_ON = 0, + AFF_STATE_OFF = 1, + AFF_STATE_ON_PENDING = 2 +} aff_info_state_t; + +/* + * Macro to represent invalid affinity level within PSCI. + */ +#define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + 1) + +/* + * Type for representing the local power state at a particular level. + */ +typedef uint8_t plat_local_state_t; + +/* The local state macro used to represent RUN state. */ +#define PSCI_LOCAL_STATE_RUN 0 + +/* + * Macro to test whether the plat_local_state is RUN state + */ +#define is_local_state_run(plat_local_state) \ + ((plat_local_state) == PSCI_LOCAL_STATE_RUN) + +/* + * Macro to test whether the plat_local_state is RETENTION state + */ +#define is_local_state_retn(plat_local_state) \ + (((plat_local_state) > PSCI_LOCAL_STATE_RUN) && \ + ((plat_local_state) <= PLAT_MAX_RET_STATE)) + +/* + * Macro to test whether the plat_local_state is OFF state + */ +#define is_local_state_off(plat_local_state) \ + (((plat_local_state) > PLAT_MAX_RET_STATE) && \ + ((plat_local_state) <= PLAT_MAX_OFF_STATE)) + +/***************************************************************************** + * This data structure defines the representation of the power state parameter + * for its exchange between the generic PSCI code and the platform port. For + * example, it is used by the platform port to specify the requested power + * states during a power management operation. It is used by the generic code to + * inform the platform about the target power states that each level should + * enter. + ****************************************************************************/ +typedef struct psci_power_state { + /* + * The pwr_domain_state[] stores the local power state at each level + * for the CPU. + */ + plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + 1]; +} psci_power_state_t; + +/******************************************************************************* + * Structure used to store per-cpu information relevant to the PSCI service. + * It is populated in the per-cpu data array. In return we get a guarantee that + * this information will not reside on a cache line shared with another cpu. + ******************************************************************************/ +typedef struct psci_cpu_data { + /* State as seen by PSCI Affinity Info API */ + aff_info_state_t aff_info_state; + + /* + * Highest power level which takes part in a power management + * operation. + */ + unsigned char target_pwrlvl; + + /* The local power state of this CPU */ + plat_local_state_t local_state; +} psci_cpu_data_t; + +/******************************************************************************* + * Structure populated by platform specific code to export routines which + * perform common low level pm functions + ******************************************************************************/ +typedef struct plat_psci_ops { + void (*cpu_standby)(plat_local_state_t cpu_state); + int (*pwr_domain_on)(u_register_t mpidr); + void (*pwr_domain_off)(const psci_power_state_t *target_state); + void (*pwr_domain_suspend)(const psci_power_state_t *target_state); + void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); + void (*pwr_domain_suspend_finish)( + const psci_power_state_t *target_state); + void (*system_off)(void) __dead2; + void (*system_reset)(void) __dead2; + int (*validate_power_state)(unsigned int power_state, + psci_power_state_t *req_state); + int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint); + void (*get_sys_suspend_power_state)( + psci_power_state_t *req_state); +} plat_psci_ops_t; + +/******************************************************************************* + * Optional structure populated by the Secure Payload Dispatcher to be given a + * chance to perform any bookkeeping before PSCI executes a power mgmt. + * operation. It also allows PSCI to determine certain properties of the SP e.g. + * migrate capability etc. + ******************************************************************************/ +typedef struct spd_pm_ops { + void (*svc_on)(uint64_t target_cpu); + int32_t (*svc_off)(uint64_t __unused); + void (*svc_suspend)(uint64_t max_off_pwrlvl); + void (*svc_on_finish)(uint64_t __unused); + void (*svc_suspend_finish)(uint64_t max_off_pwrlvl); + int32_t (*svc_migrate)(uint64_t from_cpu, uint64_t to_cpu); + int32_t (*svc_migrate_info)(uint64_t *resident_cpu); + void (*svc_system_off)(void); + void (*svc_system_reset)(void); +} spd_pm_ops_t; + +/******************************************************************************* + * Function & Data prototypes + ******************************************************************************/ +unsigned int psci_version(void); +int psci_cpu_on(u_register_t target_cpu, + uintptr_t entrypoint, + u_register_t context_id); +int psci_cpu_suspend(unsigned int power_state, + uintptr_t entrypoint, + u_register_t context_id); +int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id); +int psci_cpu_off(void); +int psci_affinity_info(u_register_t target_affinity, + unsigned int lowest_affinity_level); +int psci_migrate(u_register_t target_cpu); +int psci_migrate_info_type(void); +long psci_migrate_info_up_cpu(void); +int psci_features(unsigned int psci_fid); +void __dead2 psci_power_down_wfi(void); +void psci_entrypoint(void); +void psci_register_spd_pm_hook(const spd_pm_ops_t *); +uint64_t psci_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags); + +/* PSCI setup function */ +int psci_setup(void); + +#endif /*__ASSEMBLY__*/ + +#endif /* __PSCI_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/services/psci_compat.h b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/services/psci_compat.h new file mode 100644 index 0000000..24bd8dc --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/services/psci_compat.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PSCI_COMPAT_H__ +#define __PSCI_COMPAT_H__ + +#include +#include + +#ifndef __ASSEMBLY__ +/* + * The below declarations are to enable compatibility for the platform ports + * using the old platform interface and psci helpers. + */ +#define PLAT_MAX_PWR_LVL PLATFORM_MAX_AFFLVL +#define PLAT_NUM_PWR_DOMAINS PLATFORM_NUM_AFFS + +/******************************************************************************* + * PSCI affinity related constants. An affinity instance could + * be present or absent physically to cater for asymmetric topologies. + ******************************************************************************/ +#define PSCI_AFF_ABSENT 0x0 +#define PSCI_AFF_PRESENT 0x1 + +#define PSCI_STATE_ON 0x0 +#define PSCI_STATE_OFF 0x1 +#define PSCI_STATE_ON_PENDING 0x2 +#define PSCI_STATE_SUSPEND 0x3 + +/* + * Using the compatibility platform interfaces means that the local states + * used in psci_power_state_t need to only convey whether its power down + * or standby state. The onus is on the platform port to do the right thing + * including the state coordination in case multiple power down states are + * involved. Hence if we assume 3 generic states viz, run, standby and + * power down, we can assign 1 and 2 to standby and power down respectively. + */ +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE 2 + +/* + * Macro to represent invalid affinity level within PSCI. + */ +#define PSCI_INVALID_DATA -1 + +#define psci_get_pstate_afflvl(pstate) psci_get_pstate_pwrlvl(pstate) + +/* + * This array stores the 'power_state' requests of each CPU during + * CPU_SUSPEND and SYSTEM_SUSPEND which will be populated by the + * compatibility layer when appropriate platform hooks are invoked. + */ +extern unsigned int psci_power_state_compat[PLATFORM_CORE_COUNT]; + +/******************************************************************************* + * Structure populated by platform specific code to export routines which + * perform common low level pm functions + ******************************************************************************/ +typedef struct plat_pm_ops { + void (*affinst_standby)(unsigned int power_state); + int (*affinst_on)(unsigned long mpidr, + unsigned long sec_entrypoint, + unsigned int afflvl, + unsigned int state); + void (*affinst_off)(unsigned int afflvl, unsigned int state); + void (*affinst_suspend)(unsigned long sec_entrypoint, + unsigned int afflvl, + unsigned int state); + void (*affinst_on_finish)(unsigned int afflvl, unsigned int state); + void (*affinst_suspend_finish)(unsigned int afflvl, + unsigned int state); + void (*system_off)(void) __dead2; + void (*system_reset)(void) __dead2; + int (*validate_power_state)(unsigned int power_state); + int (*validate_ns_entrypoint)(unsigned long ns_entrypoint); + unsigned int (*get_sys_suspend_power_state)(void); +} plat_pm_ops_t; + +/******************************************************************************* + * Function & Data prototypes to enable compatibility for older platform ports + ******************************************************************************/ +int psci_get_suspend_stateid_by_mpidr(unsigned long); +int psci_get_suspend_stateid(void); +int psci_get_suspend_powerstate(void); +unsigned int psci_get_max_phys_off_afflvl(void); +int psci_get_suspend_afflvl(void); + +#endif /* ____ASSEMBLY__ */ +#endif /* __PSCI_COMPAT_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/services/std_svc.h b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/services/std_svc.h new file mode 100644 index 0000000..cbd5b62 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/bl31/services/std_svc.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __STD_SVC_H__ +#define __STD_SVC_H__ + +/* SMC function IDs for Standard Service queries */ + +#define ARM_STD_SVC_CALL_COUNT 0x8400ff00 +#define ARM_STD_SVC_UID 0x8400ff01 +/* 0x8400ff02 is reserved */ +#define ARM_STD_SVC_VERSION 0x8400ff03 + +/* ARM Standard Service Calls version numbers */ +#define STD_SVC_VERSION_MAJOR 0x0 +#define STD_SVC_VERSION_MINOR 0x1 + +/* The macros below are used to identify PSCI calls from the SMC function ID */ +#define PSCI_FID_MASK 0xffe0u +#define PSCI_FID_VALUE 0u +#define is_psci_fid(_fid) \ + (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) + +#endif /* __STD_SVC_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/bl32/payloads/tlk.h b/IPL/SDK/v3m/src/Dummy_BL33/include/bl32/payloads/tlk.h new file mode 100644 index 0000000..6ce1eb6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/bl32/payloads/tlk.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TLK_H__ +#define __TLK_H__ + +/* + * Generate function IDs for the Trusted OS/Apps + */ +#define TLK_TOS_STD_FID(fid) ((fid) | 0x72000000 | (0 << 31)) +#define TLK_TA_STD_FID(fid) ((fid) | 0x70000000 | (0 << 31)) + +/* + * Trusted OS specific function IDs + */ +#define TLK_REGISTER_LOGBUF TLK_TOS_STD_FID(0x1) +#define TLK_REGISTER_REQBUF TLK_TOS_STD_FID(0x2) +#define TLK_RESUME_FID TLK_TOS_STD_FID(0x100) +#define TLK_SYSTEM_SUSPEND TLK_TOS_STD_FID(0xE001) +#define TLK_SYSTEM_RESUME TLK_TOS_STD_FID(0xE002) +#define TLK_SYSTEM_OFF TLK_TOS_STD_FID(0xE003) + +/* + * SMC function IDs that TLK uses to signal various forms of completions + * to the secure payload dispatcher. + */ +#define TLK_REQUEST_DONE (0x32000001 | (1 << 31)) +#define TLK_PREEMPTED (0x32000002 | (1 << 31)) +#define TLK_ENTRY_DONE (0x32000003 | (1 << 31)) +#define TLK_VA_TRANSLATE (0x32000004 | (1 << 31)) +#define TLK_SUSPEND_DONE (0x32000005 | (1 << 31)) +#define TLK_RESUME_DONE (0x32000006 | (1 << 31)) +#define TLK_SYSTEM_OFF_DONE (0x32000007 | (1 << 31)) + +/* + * Trusted Application specific function IDs + */ +#define TLK_OPEN_TA_SESSION TLK_TA_STD_FID(0x1) +#define TLK_CLOSE_TA_SESSION TLK_TA_STD_FID(0x2) +#define TLK_TA_LAUNCH_OP TLK_TA_STD_FID(0x3) +#define TLK_TA_SEND_EVENT TLK_TA_STD_FID(0x4) + +/* + * Total number of function IDs implemented for services offered to NS clients. + */ +#define TLK_NUM_FID 7 + +/* TLK implementation version numbers */ +#define TLK_VERSION_MAJOR 0x0 /* Major version */ +#define TLK_VERSION_MINOR 0x1 /* Minor version */ + +/* + * Standard Trusted OS Function IDs that fall under Trusted OS call range + * according to SMC calling convention + */ +#define TOS_CALL_COUNT 0xbf00ff00 /* Number of calls implemented */ +#define TOS_UID 0xbf00ff01 /* Implementation UID */ +#define TOS_CALL_VERSION 0xbf00ff03 /* Trusted OS Call Version */ + +#endif /* __TLK_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/bl32/tsp/platform_tsp.h b/IPL/SDK/v3m/src/Dummy_BL33/include/bl32/tsp/platform_tsp.h new file mode 100644 index 0000000..f6f7391 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/bl32/tsp/platform_tsp.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_TSP_H__ + + +/******************************************************************************* + * Mandatory TSP functions (only if platform contains a TSP) + ******************************************************************************/ +void tsp_early_platform_setup(void); +void tsp_plat_arch_setup(void); +void tsp_platform_setup(void); + + +#define __PLATFORM_H__ + +#endif diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/bl32/tsp/tsp.h b/IPL/SDK/v3m/src/Dummy_BL33/include/bl32/tsp/tsp.h new file mode 100644 index 0000000..c6578b7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/bl32/tsp/tsp.h @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TSP_H__ +#define __TSP_H__ + +/* + * SMC function IDs that TSP uses to signal various forms of completions + * to the secure payload dispatcher. + */ +#define TSP_ENTRY_DONE 0xf2000000 +#define TSP_ON_DONE 0xf2000001 +#define TSP_OFF_DONE 0xf2000002 +#define TSP_SUSPEND_DONE 0xf2000003 +#define TSP_RESUME_DONE 0xf2000004 +#define TSP_PREEMPTED 0xf2000005 +#define TSP_SYSTEM_OFF_DONE 0xf2000008 +#define TSP_SYSTEM_RESET_DONE 0xf2000009 + +/* + * Function identifiers to handle FIQs through the synchronous handling model. + * If the TSP was previously interrupted then control has to be returned to + * the TSPD after handling the interrupt else execution can remain in the TSP. + */ +#define TSP_HANDLED_S_EL1_FIQ 0xf2000006 +#define TSP_EL3_FIQ 0xf2000007 + +/* SMC function ID that TSP uses to request service from secure monitor */ +#define TSP_GET_ARGS 0xf2001000 + +/* + * Identifiers for various TSP services. Corresponding function IDs (whether + * fast or standard) are generated by macros defined below + */ +#define TSP_ADD 0x2000 +#define TSP_SUB 0x2001 +#define TSP_MUL 0x2002 +#define TSP_DIV 0x2003 +#define TSP_HANDLE_FIQ_AND_RETURN 0x2004 + +/* + * Generate function IDs for TSP services to be used in SMC calls, by + * appropriately setting bit 31 to differentiate standard and fast SMC calls + */ +#define TSP_STD_FID(fid) ((fid) | 0x72000000 | (0 << 31)) +#define TSP_FAST_FID(fid) ((fid) | 0x72000000 | (1 << 31)) + +/* SMC function ID to request a previously preempted std smc */ +#define TSP_FID_RESUME TSP_STD_FID(0x3000) + +/* + * Identify a TSP service from function ID filtering the last 16 bits from the + * SMC function ID + */ +#define TSP_BARE_FID(fid) ((fid) & 0xffff) + +/* + * Total number of function IDs implemented for services offered to NS clients. + * The function IDs are defined above + */ +#define TSP_NUM_FID 0x4 + +/* TSP implementation version numbers */ +#define TSP_VERSION_MAJOR 0x0 /* Major version */ +#define TSP_VERSION_MINOR 0x1 /* Minor version */ + +/* + * Standard Trusted OS Function IDs that fall under Trusted OS call range + * according to SMC calling convention + */ +#define TOS_CALL_COUNT 0xbf00ff00 /* Number of calls implemented */ +#define TOS_UID 0xbf00ff01 /* Implementation UID */ +/* 0xbf00ff02 is reserved */ +#define TOS_CALL_VERSION 0xbf00ff03 /* Trusted OS Call Version */ + + +#ifndef __ASSEMBLY__ + +#include + + +typedef uint32_t tsp_vector_isn_t; + +typedef struct tsp_vectors { + tsp_vector_isn_t std_smc_entry; + tsp_vector_isn_t fast_smc_entry; + tsp_vector_isn_t cpu_on_entry; + tsp_vector_isn_t cpu_off_entry; + tsp_vector_isn_t cpu_resume_entry; + tsp_vector_isn_t cpu_suspend_entry; + tsp_vector_isn_t fiq_entry; + tsp_vector_isn_t system_off_entry; + tsp_vector_isn_t system_reset_entry; +} tsp_vectors_t; + + +#endif /* __ASSEMBLY__ */ + +#endif /* __TSP_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/common/asm_macros.S b/IPL/SDK/v3m/src/Dummy_BL33/include/common/asm_macros.S new file mode 100644 index 0000000..128259f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/common/asm_macros.S @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ASM_MACROS_S__ +#define __ASM_MACROS_S__ + +#include + + + .macro func_prologue + stp x29, x30, [sp, #-0x10]! + mov x29,sp + .endm + + .macro func_epilogue + ldp x29, x30, [sp], #0x10 + .endm + + + .macro dcache_line_size reg, tmp + mrs \tmp, ctr_el0 + ubfx \tmp, \tmp, #16, #4 + mov \reg, #4 + lsl \reg, \reg, \tmp + .endm + + + .macro icache_line_size reg, tmp + mrs \tmp, ctr_el0 + and \tmp, \tmp, #0xf + mov \reg, #4 + lsl \reg, \reg, \tmp + .endm + + + .macro smc_check label + mrs x0, esr_el3 + ubfx x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH + cmp x0, #EC_AARCH64_SMC + b.ne $label + .endm + + + /* + * This macro verifies that the a given vector doesn't exceed the + * architectural limit of 32 instructions. This is meant to be placed + * immedately after the last instruction in the vector. It takes the + * vector entry as the parameter + */ + .macro check_vector_size since + .if (. - \since) > (32 * 4) + .error "Vector exceeds 32 instructions" + .endif + .endm + + /* + * This macro is used to create a function label and place the + * code into a separate text section based on the function name + * to enable elimination of unused code during linking + */ + .macro func _name + .section .text.\_name, "ax" + .type \_name, %function + .func \_name + \_name: + .endm + + /* + * This macro is used to mark the end of a function. + */ + .macro endfunc _name + .endfunc + .size \_name, . - \_name + .endm + + /* + * Theses macros are used to create function labels for deprecated + * APIs. If WARN_DEPRECATED is non zero, the callers of these APIs + * will fail to link and cause build failure. + */ +#if WARN_DEPRECATED + .macro func_deprecated _name + func deprecated\_name + .endm + + .macro endfunc_deprecated _name + endfunc deprecated\_name + .endm +#else + .macro func_deprecated _name + func \_name + .endm + + .macro endfunc_deprecated _name + endfunc \_name + .endm +#endif + + /* + * This macro declares an array of 1 or more stacks, properly + * aligned and in the requested section + */ +#define STACK_ALIGN 6 + + .macro declare_stack _name, _section, _size, _count + .if ((\_size & ((1 << STACK_ALIGN) - 1)) <> 0) + .error "Stack size not correctly aligned" + .endif + .section \_section, "aw", %nobits + .align STACK_ALIGN + \_name: + .space ((\_count) * (\_size)), 0 + .endm + +#if ENABLE_PLAT_COMPAT + /* + * This macro calculates the base address of an MP stack using the + * platform_get_core_pos() index, the name of the stack storage and + * the size of each stack + * In: X0 = MPIDR of CPU whose stack is wanted + * Out: X0 = physical address of stack base + * Clobber: X30, X1, X2 + */ + .macro get_mp_stack _name, _size + bl platform_get_core_pos + ldr x2, =(\_name + \_size) + mov x1, #\_size + madd x0, x0, x1, x2 + .endm +#endif + + /* + * This macro calculates the base address of the current CPU's MP stack + * using the plat_my_core_pos() index, the name of the stack storage + * and the size of each stack + * Out: X0 = physical address of stack base + * Clobber: X30, X1, X2 + */ + .macro get_my_mp_stack _name, _size + bl plat_my_core_pos + ldr x2, =(\_name + \_size) + mov x1, #\_size + madd x0, x0, x1, x2 + .endm + + /* + * This macro calculates the base address of a UP stack using the + * name of the stack storage and the size of the stack + * Out: X0 = physical address of stack base + */ + .macro get_up_stack _name, _size + ldr x0, =(\_name + \_size) + .endm + + /* + * Helper macro to generate the best mov/movk combinations according + * the value to be moved. The 16 bits from '_shift' are tested and + * if not zero, they are moved into '_reg' without affecting + * other bits. + */ + .macro _mov_imm16 _reg, _val, _shift + .if (\_val >> \_shift) & 0xffff + .if (\_val & (1 << \_shift - 1)) + movk \_reg, (\_val >> \_shift) & 0xffff, LSL \_shift + .else + mov \_reg, \_val & (0xffff << \_shift) + .endif + .endif + .endm + + /* + * Helper macro to load arbitrary values into 32 or 64-bit registers + * which generates the best mov/movk combinations. Many base addresses + * are 64KB aligned the macro will eliminate updating bits 15:0 in + * that case + */ + .macro mov_imm _reg, _val + .if (\_val) == 0 + mov \_reg, #0 + .else + _mov_imm16 \_reg, (\_val), 0 + _mov_imm16 \_reg, (\_val), 16 + _mov_imm16 \_reg, (\_val), 32 + _mov_imm16 \_reg, (\_val), 48 + .endif + .endm + +#endif /* __ASM_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/common/assert_macros.S b/IPL/SDK/v3m/src/Dummy_BL33/include/common/assert_macros.S new file mode 100644 index 0000000..cb6c78b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/common/assert_macros.S @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ASSERT_MACROS_S__ +#define __ASSERT_MACROS_S__ + + /* + * Assembler macro to enable asm_assert. Use this macro wherever + * assert is required in assembly. Please note that the macro makes + * use of label '300' to provide the logic and the caller + * should make sure that this label is not used to branch prior + * to calling this macro. + */ +#define ASM_ASSERT(_cc) \ +.ifndef .L_assert_filename ;\ + .pushsection .rodata.str1.1, "aS" ;\ + .L_assert_filename: ;\ + .string __FILE__ ;\ + .popsection ;\ +.endif ;\ + b._cc 300f ;\ + adr x0, .L_assert_filename ;\ + mov x1, __LINE__ ;\ + b asm_assert ;\ +300: + +#endif /* __ASSERT_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/common/bl_common.h b/IPL/SDK/v3m/src/Dummy_BL33/include/common/bl_common.h new file mode 100644 index 0000000..164377f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/common/bl_common.h @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BL_COMMON_H__ +#define __BL_COMMON_H__ + +#define SECURE 0x0 +#define NON_SECURE 0x1 +#define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE)) + +#define UP 1 +#define DOWN 0 + +/******************************************************************************* + * Constants to identify the location of a memory region in a given memory + * layout. +******************************************************************************/ +#define TOP 0x1 +#define BOTTOM !TOP + +/****************************************************************************** + * Opcode passed in x0 to tell next EL that we want to run an image. + * Corresponds to the function ID of the only SMC that the BL1 exception + * handlers service. That's why the chosen value is the first function ID of + * the ARM SMC64 range. + *****************************************************************************/ +#define RUN_IMAGE 0xC0000000 + +/******************************************************************************* + * Constants that allow assembler code to access members of and the + * 'entry_point_info' structure at their correct offsets. + ******************************************************************************/ +#define ENTRY_POINT_INFO_PC_OFFSET 0x08 +#define ENTRY_POINT_INFO_ARGS_OFFSET 0x18 + +#define PARAM_EP_SECURITY_MASK 0x1 +#define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK) +#define SET_SECURITY_STATE(x, security) \ + ((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security)) + +#define EP_EE_MASK 0x2 +#define EP_EE_LITTLE 0x0 +#define EP_EE_BIG 0x2 +#define EP_GET_EE(x) (x & EP_EE_MASK) +#define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee)) + +#define EP_ST_MASK 0x4 +#define EP_ST_DISABLE 0x0 +#define EP_ST_ENABLE 0x4 +#define EP_GET_ST(x) (x & EP_ST_MASK) +#define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) + +#define PARAM_EP 0x01 +#define PARAM_IMAGE_BINARY 0x02 +#define PARAM_BL31 0x03 + +#define VERSION_1 0x01 + +#define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \ + (_p)->h.type = (uint8_t)(_type); \ + (_p)->h.version = (uint8_t)(_ver); \ + (_p)->h.size = (uint16_t)sizeof(*_p); \ + (_p)->h.attr = (uint32_t)(_attr) ; \ + } while (0) + +#ifndef __ASSEMBLY__ +#include /* For __dead2 */ +#include +#include +#include + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/* + * Declarations of linker defined symbols to help determine memory layout of + * BL images + */ +extern unsigned long __RO_START__; +extern unsigned long __RO_END__; +#if IMAGE_BL2 +extern unsigned long __BL2_END__; +#elif IMAGE_BL31 +extern unsigned long __BL31_END__; +#elif IMAGE_BL32 +extern unsigned long __BL32_END__; +#endif /* IMAGE_BLX */ + +#if USE_COHERENT_MEM +extern unsigned long __COHERENT_RAM_START__; +extern unsigned long __COHERENT_RAM_END__; +#endif + + +/******************************************************************************* + * Structure used for telling the next BL how much of a particular type of + * memory is available for its use and how much is already used. + ******************************************************************************/ +typedef struct meminfo { + uint64_t total_base; + size_t total_size; + uint64_t free_base; + size_t free_size; +} meminfo_t; + +typedef struct aapcs64_params { + unsigned long arg0; + unsigned long arg1; + unsigned long arg2; + unsigned long arg3; + unsigned long arg4; + unsigned long arg5; + unsigned long arg6; + unsigned long arg7; +} aapcs64_params_t; + +/*************************************************************************** + * This structure provides version information and the size of the + * structure, attributes for the structure it represents + ***************************************************************************/ +typedef struct param_header { + uint8_t type; /* type of the structure */ + uint8_t version; /* version of this structure */ + uint16_t size; /* size of this structure in bytes */ + uint32_t attr; /* attributes: unused bits SBZ */ +} param_header_t; + +/***************************************************************************** + * This structure represents the superset of information needed while + * switching exception levels. The only two mechanisms to do so are + * ERET & SMC. Security state is indicated using bit zero of header + * attribute + * NOTE: BL1 expects entrypoint followed by spsr while processing + * SMC to jump to BL31 from the start of entry_point_info + *****************************************************************************/ +typedef struct entry_point_info { + param_header_t h; + uintptr_t pc; + uint32_t spsr; + aapcs64_params_t args; +} entry_point_info_t; + +/***************************************************************************** + * Image info binary provides information from the image loader that + * can be used by the firmware to manage available trusted RAM. + * More advanced firmware image formats can provide additional + * information that enables optimization or greater flexibility in the + * common firmware code + *****************************************************************************/ +typedef struct image_info { + param_header_t h; + uintptr_t image_base; /* physical address of base of image */ + uint32_t image_size; /* bytes read from image file */ +} image_info_t; + +/******************************************************************************* + * This structure represents the superset of information that can be passed to + * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be + * populated only if BL2 detects its presence. A pointer to a structure of this + * type should be passed in X0 to BL3-1's cold boot entrypoint. + * + * Use of this structure and the X0 parameter is not mandatory: the BL3-1 + * platform code can use other mechanisms to provide the necessary information + * about BL3-2 and BL3-3 to the common and SPD code. + * + * BL3-1 image information is mandatory if this structure is used. If either of + * the optional BL3-2 and BL3-3 image information is not provided, this is + * indicated by the respective image_info pointers being zero. + ******************************************************************************/ +typedef struct bl31_params { + param_header_t h; + image_info_t *bl31_image_info; + entry_point_info_t *bl32_ep_info; + image_info_t *bl32_image_info; + entry_point_info_t *bl33_ep_info; + image_info_t *bl33_image_info; +} bl31_params_t; + +/* + * load_auth_image() return values + */ +enum { + LOAD_SUCCESS, /* Load + authentication success */ + LOAD_ERR, /* Load error */ + LOAD_AUTH_ERR /* Authentication error */ +}; + + +/* + * Compile time assertions related to the 'entry_point_info' structure to + * ensure that the assembler and the compiler view of the offsets of + * the structure members is the same. + */ +CASSERT(ENTRY_POINT_INFO_PC_OFFSET == + __builtin_offsetof(entry_point_info_t, pc), \ + assert_BL31_pc_offset_mismatch); + +CASSERT(ENTRY_POINT_INFO_ARGS_OFFSET == \ + __builtin_offsetof(entry_point_info_t, args), \ + assert_BL31_args_offset_mismatch); + +CASSERT(sizeof(unsigned long) == + __builtin_offsetof(entry_point_info_t, spsr) - \ + __builtin_offsetof(entry_point_info_t, pc), \ + assert_entrypoint_and_spsr_should_be_adjacent); + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +unsigned long page_align(unsigned long, unsigned); +unsigned long image_size(unsigned int image_id); +int load_image(meminfo_t *mem_layout, + unsigned int image_id, + uintptr_t image_base, + image_info_t *image_data, + entry_point_info_t *entry_point_info); +int load_auth_image(meminfo_t *mem_layout, + unsigned int image_name, + uintptr_t image_base, + image_info_t *image_data, + entry_point_info_t *entry_point_info); +extern const char build_message[]; +extern const char version_string[]; + +void reserve_mem(uint64_t *free_base, size_t *free_size, + uint64_t addr, size_t size); + +#endif /*__ASSEMBLY__*/ + +#endif /* __BL_COMMON_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/common/debug.h b/IPL/SDK/v3m/src/Dummy_BL33/include/common/debug.h new file mode 100644 index 0000000..d198c32 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/common/debug.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +#include + +/* The log output macros print output to the console. These macros produce + * compiled log output only if the LOG_LEVEL defined in the makefile (or the + * make command line) is greater or equal than the level required for that + * type of log output. + * The format expected is the same as for printf(). For example: + * INFO("Info %s.\n", "message") -> INFO: Info message. + * WARN("Warning %s.\n", "message") -> WARNING: Warning message. + */ + +#define LOG_LEVEL_NONE 0 +#define LOG_LEVEL_ERROR 10 +#define LOG_LEVEL_NOTICE 20 +#define LOG_LEVEL_WARNING 30 +#define LOG_LEVEL_INFO 40 +#define LOG_LEVEL_VERBOSE 50 + + +#if LOG_LEVEL >= LOG_LEVEL_NOTICE +# define NOTICE(...) tf_printf("NOTICE: " __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_ERROR +# define ERROR(...) tf_printf("ERROR: " __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_WARNING +# define WARN(...) tf_printf("WARNING: " __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_INFO +# define INFO(...) tf_printf("INFO: " __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE +# define VERBOSE(...) tf_printf("VERBOSE: " __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + + +void __dead2 do_panic(void); +#define panic() do_panic() + +void tf_printf(const char *fmt, ...) __printflike(1, 2); + +#endif /* __DEBUG_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/common/el3_common_macros.S b/IPL/SDK/v3m/src/Dummy_BL33/include/common/el3_common_macros.S new file mode 100644 index 0000000..87e172e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/common/el3_common_macros.S @@ -0,0 +1,268 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __EL3_COMMON_MACROS_S__ +#define __EL3_COMMON_MACROS_S__ + +#include +#include + + /* + * Helper macro to initialise EL3 registers we care about. + */ + .macro el3_arch_init_common _exception_vectors + /* --------------------------------------------------------------------- + * Enable the instruction cache, stack pointer and data access alignment + * checks + * --------------------------------------------------------------------- + */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el3 + orr x0, x0, x1 + msr sctlr_el3, x0 + isb + +#if IMAGE_BL31 + /* --------------------------------------------------------------------- + * Initialise the per-cpu cache pointer to the CPU. + * This is done early to enable crash reporting to have access to crash + * stack. Since crash reporting depends on cpu_data to report the + * unhandled exception, not doing so can lead to recursive exceptions + * due to a NULL TPIDR_EL3. + * --------------------------------------------------------------------- + */ + bl init_cpu_data_ptr +#endif /* IMAGE_BL31 */ + + /* --------------------------------------------------------------------- + * Set the exception vectors. + * --------------------------------------------------------------------- + */ + adr x0, \_exception_vectors + msr vbar_el3, x0 + isb + + /* --------------------------------------------------------------------- + * Enable the SError interrupt now that the exception vectors have been + * setup. + * --------------------------------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT + + /* --------------------------------------------------------------------- + * The initial state of the Architectural feature trap register + * (CPTR_EL3) is unknown and it must be set to a known state. All + * feature traps are disabled. Some bits in this register are marked as + * reserved and should not be modified. + * + * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 + * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. + * + * CPTR_EL3.TTA: This causes access to the Trace functionality to trap + * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register + * access to trace functionality is not supported, this bit is RES0. + * + * CPTR_EL3.TFP: This causes instructions that access the registers + * associated with Floating Point and Advanced SIMD execution to trap + * to EL3 when executed from any exception level, unless trapped to EL1 + * or EL2. + * --------------------------------------------------------------------- + */ + mrs x0, cptr_el3 + bic w0, w0, #TCPAC_BIT + bic w0, w0, #TTA_BIT + bic w0, w0, #TFP_BIT + msr cptr_el3, x0 + .endm + +/* ----------------------------------------------------------------------------- + * This is the super set of actions that need to be performed during a cold boot + * or a warm boot in EL3. This code is shared by BL1 and BL3-1. + * + * This macro will always perform reset handling, architectural initialisations + * and stack setup. The rest of the actions are optional because they might not + * be needed, depending on the context in which this macro is called. This is + * why this macro is parameterised ; each parameter allows to enable/disable + * some actions. + * + * _set_endian: + * Whether the macro needs to configure the endianness of data accesses. + * + * _warm_boot_mailbox: + * Whether the macro needs to detect the type of boot (cold/warm). The + * detection is based on the platform entrypoint address : if it is zero + * then it is a cold boot, otherwise it is a warm boot. In the latter case, + * this macro jumps on the platform entrypoint address. + * + * _secondary_cold_boot: + * Whether the macro needs to identify the CPU that is calling it: primary + * CPU or secondary CPU. The primary CPU will be allowed to carry on with + * the platform initialisations, while the secondaries will be put in a + * platform-specific state in the meantime. + * + * If the caller knows this macro will only be called by the primary CPU + * then this parameter can be defined to 0 to skip this step. + * + * _init_memory: + * Whether the macro needs to initialise the memory. + * + * _init_c_runtime: + * Whether the macro needs to initialise the C runtime environment. + * + * _exception_vectors: + * Address of the exception vectors to program in the VBAR_EL3 register. + * ----------------------------------------------------------------------------- + */ + .macro el3_entrypoint_common \ + _set_endian, _warm_boot_mailbox, _secondary_cold_boot, \ + _init_memory, _init_c_runtime, _exception_vectors + + .if \_set_endian + /* ------------------------------------------------------------- + * Set the CPU endianness before doing anything that might + * involve memory reads or writes. + * ------------------------------------------------------------- + */ + mrs x0, sctlr_el3 + bic x0, x0, #SCTLR_EE_BIT + msr sctlr_el3, x0 + isb + .endif /* _set_endian */ + + .if \_warm_boot_mailbox + /* ------------------------------------------------------------- + * This code will be executed for both warm and cold resets. + * Now is the time to distinguish between the two. + * Query the platform entrypoint address and if it is not zero + * then it means it is a warm boot so jump to this address. + * ------------------------------------------------------------- + */ + bl plat_get_my_entrypoint + cbz x0, do_cold_boot + br x0 + + do_cold_boot: + .endif /* _warm_boot_mailbox */ + + .if \_secondary_cold_boot + /* ------------------------------------------------------------- + * It is a cold boot. + * The primary CPU will set up the platform while the + * secondaries are placed in a platform-specific state until the + * primary CPU performs the necessary actions to bring them out + * of that state and allows entry into the OS. + * ------------------------------------------------------------- + */ + bl plat_is_my_cpu_primary + cbnz w0, do_primary_cold_boot + + /* This is a cold boot on a secondary CPU */ + bl plat_secondary_cold_boot_setup + /* plat_secondary_cold_boot_setup() is not supposed to return */ + secondary_panic: + b secondary_panic + + do_primary_cold_boot: + .endif /* _secondary_cold_boot */ + + /* --------------------------------------------------------------------- + * Perform any processor specific actions upon reset e.g. cache, TLB + * invalidations etc. + * --------------------------------------------------------------------- + */ + bl reset_handler + + el3_arch_init_common \_exception_vectors + + .if \_init_memory + bl platform_mem_init + .endif /* _init_memory */ + + /* --------------------------------------------------------------------- + * Init C runtime environment: + * - Zero-initialise the NOBITS sections. There are 2 of them: + * - the .bss section; + * - the coherent memory section (if any). + * - Relocate the data section from ROM to RAM, if required. + * --------------------------------------------------------------------- + */ + .if \_init_c_runtime +#if IMAGE_BL31 + /* ------------------------------------------------------------- + * Invalidate the RW memory used by the BL31 image. This + * includes the data and NOBITS sections. This is done to + * safeguard against possible corruption of this memory by + * dirty cache lines in a system cache as a result of use by + * an earlier boot loader stage. + * ------------------------------------------------------------- + */ + adr x0, __RW_START__ + adr x1, __RW_END__ + sub x1, x1, x0 + bl inv_dcache_range +#endif /* IMAGE_BL31 */ + + ldr x0, =__BSS_START__ + ldr x1, =__BSS_SIZE__ + bl zeromem16 + +#if USE_COHERENT_MEM + ldr x0, =__COHERENT_RAM_START__ + ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ + bl zeromem16 +#endif + +#if IMAGE_BL1 + ldr x0, =__DATA_RAM_START__ + ldr x1, =__DATA_ROM_START__ + ldr x2, =__DATA_SIZE__ + bl memcpy16 +#endif + .endif /* _init_c_runtime */ + +#if IMAGE_BL31 + /* --------------------------------------------------------------------- + * Use SP_EL0 for the C runtime stack. + * --------------------------------------------------------------------- + */ + msr spsel, #0 +#endif /* IMAGE_BL31 */ + + /* --------------------------------------------------------------------- + * Allocate a stack whose memory will be marked as Normal-IS-WBWA when + * the MMU is enabled. There is no risk of reading stale stack memory + * after enabling the MMU as only the primary CPU is running at the + * moment. + * --------------------------------------------------------------------- + */ + bl plat_set_my_stack + .endm + +#endif /* __EL3_COMMON_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/common/firmware_image_package.h b/IPL/SDK/v3m/src/Dummy_BL33/include/common/firmware_image_package.h new file mode 100644 index 0000000..8fb669e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/common/firmware_image_package.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FIRMWARE_IMAGE_PACKAGE_H__ +#define __FIRMWARE_IMAGE_PACKAGE_H__ + +#include +#include + +/* This is used as a signature to validate the blob header */ +#define TOC_HEADER_NAME 0xAA640001 + + +/* ToC Entry UUIDs */ +#define UUID_TRUSTED_BOOT_FIRMWARE_BL2 \ + {0x0becf95f, 0x224d, 0x4d3e, 0xa5, 0x44, {0xc3, 0x9d, 0x81, 0xc7, 0x3f, 0x0a} } +#define UUID_SCP_FIRMWARE_BL30 \ + {0x3dfd6697, 0xbe89, 0x49e8, 0xae, 0x5d, {0x78, 0xa1, 0x40, 0x60, 0x82, 0x13} } +#define UUID_EL3_RUNTIME_FIRMWARE_BL31 \ + {0x6d08d447, 0xfe4c, 0x4698, 0x9b, 0x95, {0x29, 0x50, 0xcb, 0xbd, 0x5a, 0x00} } +#define UUID_SECURE_PAYLOAD_BL32 \ + {0x89e1d005, 0xdc53, 0x4713, 0x8d, 0x2b, {0x50, 0x0a, 0x4b, 0x7a, 0x3e, 0x38} } +#define UUID_NON_TRUSTED_FIRMWARE_BL33 \ + {0xa7eed0d6, 0xeafc, 0x4bd5, 0x97, 0x82, {0x99, 0x34, 0xf2, 0x34, 0xb6, 0xe4} } +/* Key certificates */ +#define UUID_ROT_KEY_CERT \ + {0x721d2d86, 0x60f8, 0x11e4, 0x92, 0x0b, {0x8b, 0xe7, 0x62, 0x16, 0x0f, 0x24} } +#define UUID_TRUSTED_KEY_CERT \ + {0x90e87e82, 0x60f8, 0x11e4, 0xa1, 0xb4, {0x77, 0x7a, 0x21, 0xb4, 0xf9, 0x4c} } +#define UUID_NON_TRUSTED_WORLD_KEY_CERT \ + {0x3d87671c, 0x635f, 0x11e4, 0x97, 0x8d, {0x27, 0xc0, 0xc7, 0x14, 0x8a, 0xbd} } +#define UUID_SCP_FIRMWARE_BL30_KEY_CERT \ + {0xa1214202, 0x60f8, 0x11e4, 0x8d, 0x9b, {0xf3, 0x3c, 0x0e, 0x15, 0xa0, 0x14} } +#define UUID_EL3_RUNTIME_FIRMWARE_BL31_KEY_CERT \ + {0xccbeb88a, 0x60f9, 0x11e4, 0x9a, 0xd0, {0xeb, 0x48, 0x22, 0xd8, 0xdc, 0xf8} } +#define UUID_SECURE_PAYLOAD_BL32_KEY_CERT \ + {0x03d67794, 0x60fb, 0x11e4, 0x85, 0xdd, {0xb7, 0x10, 0x5b, 0x8c, 0xee, 0x04} } +#define UUID_NON_TRUSTED_FIRMWARE_BL33_KEY_CERT \ + {0x2a83d58a, 0x60fb, 0x11e4, 0x8a, 0xaf, {0xdf, 0x30, 0xbb, 0xc4, 0x98, 0x59} } +/* Content certificates */ +#define UUID_TRUSTED_BOOT_FIRMWARE_BL2_CERT \ + {0xea69e2d6, 0x635d, 0x11e4, 0x8d, 0x8c, {0x9f, 0xba, 0xbe, 0x99, 0x56, 0xa5} } +#define UUID_SCP_FIRMWARE_BL30_CERT \ + {0x046fbe44, 0x635e, 0x11e4, 0xb2, 0x8b, {0x73, 0xd8, 0xea, 0xae, 0x96, 0x56} } +#define UUID_EL3_RUNTIME_FIRMWARE_BL31_CERT \ + {0x200cb2e2, 0x635e, 0x11e4, 0x9c, 0xe8, {0xab, 0xcc, 0xf9, 0x2b, 0xb6, 0x66} } +#define UUID_SECURE_PAYLOAD_BL32_CERT \ + {0x11449fa4, 0x635e, 0x11e4, 0x87, 0x28, {0x3f, 0x05, 0x72, 0x2a, 0xf3, 0x3d} } +#define UUID_NON_TRUSTED_FIRMWARE_BL33_CERT \ + {0xf3c1c48e, 0x635d, 0x11e4, 0xa7, 0xa9, {0x87, 0xee, 0x40, 0xb2, 0x3f, 0xa7} } + +typedef struct fip_toc_header { + uint32_t name; + uint32_t serial_number; + uint64_t flags; +} fip_toc_header_t; + +typedef struct fip_toc_entry { + uuid_t uuid; + uint64_t offset_address; + uint64_t size; + uint64_t flags; +} fip_toc_entry_t; + +#endif /* __FIRMWARE_IMAGE_PACKAGE_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/common/tbbr/cot_def.h b/IPL/SDK/v3m/src/Dummy_BL33/include/common/tbbr/cot_def.h new file mode 100644 index 0000000..d6dca4a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/common/tbbr/cot_def.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __COT_DEF_H__ +#define __COT_DEF_H__ + +/* TBBR CoT definitions */ + +#define COT_MAX_VERIFIED_PARAMS 4 + +#endif /* __COT_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/common/tbbr/tbbr_img_def.h b/IPL/SDK/v3m/src/Dummy_BL33/include/common/tbbr/tbbr_img_def.h new file mode 100644 index 0000000..c43c395 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/common/tbbr/tbbr_img_def.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TBBR_IMG_DEF_H__ +#define __TBBR_IMG_DEF_H__ + +/* Firmware Image Package */ +#define FIP_IMAGE_ID 0 + +/* Trusted Boot Firmware BL2 */ +#define BL2_IMAGE_ID 1 + +/* SCP Firmware BL3-0 */ +#define BL30_IMAGE_ID 2 + +/* EL3 Runtime Firmware BL31 */ +#define BL31_IMAGE_ID 3 + +/* Secure Payload BL32 (Trusted OS) */ +#define BL32_IMAGE_ID 4 + +/* Non-Trusted Firmware BL33 */ +#define BL33_IMAGE_ID 5 + +/* Certificates */ +#define BL2_CERT_ID 6 +#define TRUSTED_KEY_CERT_ID 7 + +#define BL30_KEY_CERT_ID 8 +#define BL31_KEY_CERT_ID 9 +#define BL32_KEY_CERT_ID 10 +#define BL33_KEY_CERT_ID 11 + +#define BL30_CERT_ID 12 +#define BL31_CERT_ID 13 +#define BL32_CERT_ID 14 +#define BL33_CERT_ID 15 + +#endif /* __TBBR_IMG_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/arm_gic.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/arm_gic.h new file mode 100644 index 0000000..5752d8f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/arm_gic.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARM_GIC_H__ +#define __ARM_GIC_H__ + +#include + +/******************************************************************************* + * Function declarations + ******************************************************************************/ +void arm_gic_init(uintptr_t gicc_base, + uintptr_t gicd_base, + uintptr_t gicr_base, + const unsigned int *irq_sec_ptr, + unsigned int num_irqs); +void arm_gic_setup(void); +void arm_gic_cpuif_deactivate(void); +void arm_gic_cpuif_setup(void); +void arm_gic_pcpu_distif_setup(void); + +uint32_t arm_gic_interrupt_type_to_line(uint32_t type, + uint32_t security_state); +uint32_t arm_gic_get_pending_interrupt_type(void); +uint32_t arm_gic_get_pending_interrupt_id(void); +uint32_t arm_gic_acknowledge_interrupt(void); +void arm_gic_end_of_interrupt(uint32_t id); +uint32_t arm_gic_get_interrupt_type(uint32_t id); + +#endif /* __GIC_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/cci.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/cci.h new file mode 100644 index 0000000..1145f91 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/cci.h @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCI_H__ +#define __CCI_H__ + +/* Slave interface offsets from PERIPHBASE */ +#define SLAVE_IFACE6_OFFSET 0x7000 +#define SLAVE_IFACE5_OFFSET 0x6000 +#define SLAVE_IFACE4_OFFSET 0x5000 +#define SLAVE_IFACE3_OFFSET 0x4000 +#define SLAVE_IFACE2_OFFSET 0x3000 +#define SLAVE_IFACE1_OFFSET 0x2000 +#define SLAVE_IFACE0_OFFSET 0x1000 +#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \ + (0x1000 * (index))) + +/* Slave interface event and count register offsets from PERIPHBASE */ +#define EVENT_SELECT7_OFFSET 0x80000 +#define EVENT_SELECT6_OFFSET 0x70000 +#define EVENT_SELECT5_OFFSET 0x60000 +#define EVENT_SELECT4_OFFSET 0x50000 +#define EVENT_SELECT3_OFFSET 0x40000 +#define EVENT_SELECT2_OFFSET 0x30000 +#define EVENT_SELECT1_OFFSET 0x20000 +#define EVENT_SELECT0_OFFSET 0x10000 +#define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \ + (0x10000 * (index))) + +/* Control and ID register offsets */ +#define CTRL_OVERRIDE_REG 0x0 +#define SECURE_ACCESS_REG 0x8 +#define STATUS_REG 0xc +#define IMPRECISE_ERR_REG 0x10 +#define PERFMON_CTRL_REG 0x100 +#define IFACE_MON_CTRL_REG 0x104 + +/* Component and peripheral ID registers */ +#define PERIPHERAL_ID0 0xFE0 +#define PERIPHERAL_ID1 0xFE4 +#define PERIPHERAL_ID2 0xFE8 +#define PERIPHERAL_ID3 0xFEC +#define PERIPHERAL_ID4 0xFD0 +#define PERIPHERAL_ID5 0xFD4 +#define PERIPHERAL_ID6 0xFD8 +#define PERIPHERAL_ID7 0xFDC + +#define COMPONENT_ID0 0xFF0 +#define COMPONENT_ID1 0xFF4 +#define COMPONENT_ID2 0xFF8 +#define COMPONENT_ID3 0xFFC +#define COMPONENT_ID4 0x1000 +#define COMPONENT_ID5 0x1004 +#define COMPONENT_ID6 0x1008 +#define COMPONENT_ID7 0x100C + +/* Slave interface register offsets */ +#define SNOOP_CTRL_REG 0x0 +#define SH_OVERRIDE_REG 0x4 +#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100 +#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104 +#define MAX_OT_REG 0x110 + +/* Snoop Control register bit definitions */ +#define DVM_EN_BIT (1 << 1) +#define SNOOP_EN_BIT (1 << 0) +#define SUPPORT_SNOOPS (1 << 30) +#define SUPPORT_DVM (1 << 31) + +/* Status register bit definitions */ +#define CHANGE_PENDING_BIT (1 << 0) + +/* Event and count register offsets */ +#define EVENT_SELECT_REG 0x0 +#define EVENT_COUNT_REG 0x4 +#define COUNT_CNTRL_REG 0x8 +#define COUNT_OVERFLOW_REG 0xC + +/* Slave interface monitor registers */ +#define INT_MON_REG_SI0 0x90000 +#define INT_MON_REG_SI1 0x90004 +#define INT_MON_REG_SI2 0x90008 +#define INT_MON_REG_SI3 0x9000C +#define INT_MON_REG_SI4 0x90010 +#define INT_MON_REG_SI5 0x90014 +#define INT_MON_REG_SI6 0x90018 + +/* Master interface monitor registers */ +#define INT_MON_REG_MI0 0x90100 +#define INT_MON_REG_MI1 0x90104 +#define INT_MON_REG_MI2 0x90108 +#define INT_MON_REG_MI3 0x9010c +#define INT_MON_REG_MI4 0x90110 +#define INT_MON_REG_MI5 0x90114 + +#define SLAVE_IF_UNUSED -1 + +#if ARM_CCI_PRODUCT_ID == 400 + #define CCI_SLAVE_INTERFACE_COUNT 5 +#elif ARM_CCI_PRODUCT_ID == 500 + #define CCI_SLAVE_INTERFACE_COUNT 7 +#else + #error "Invalid CCI product or CCI not supported" +#endif + +#ifndef __ASSEMBLY__ + +#include + +/* Function declarations */ + +/* + * The ARM CCI driver needs the following: + * 1. Base address of the CCI-500/CCI-400 + * 2. An array of map between AMBA 4 master ids and ACE/ACE lite slave + * interfaces. + * 3. Size of the array. + * + * SLAVE_IF_UNUSED should be used in the map to represent no AMBA 4 master exists + * for that interface. + */ +void cci_init(uintptr_t cci_base, + const int *map, + unsigned int num_cci_masters); + +void cci_enable_snoop_dvm_reqs(unsigned int master_id); +void cci_disable_snoop_dvm_reqs(unsigned int master_id); + +#endif /* __ASSEMBLY__ */ +#endif /* __CCI_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/cci400.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/cci400.h new file mode 100644 index 0000000..620221a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/cci400.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCI_400_H__ +#define __CCI_400_H__ + +/* Slave interface offsets from PERIPHBASE */ +#define SLAVE_IFACE4_OFFSET 0x5000 +#define SLAVE_IFACE3_OFFSET 0x4000 +#define SLAVE_IFACE2_OFFSET 0x3000 +#define SLAVE_IFACE1_OFFSET 0x2000 +#define SLAVE_IFACE0_OFFSET 0x1000 +#define SLAVE_IFACE_OFFSET(index) SLAVE_IFACE0_OFFSET + \ + (0x1000 * (index)) + +/* Control and ID register offsets */ +#define CTRL_OVERRIDE_REG 0x0 +#define SPEC_CTRL_REG 0x4 +#define SECURE_ACCESS_REG 0x8 +#define STATUS_REG 0xc +#define IMPRECISE_ERR_REG 0x10 +#define PERFMON_CTRL_REG 0x100 + +/* Slave interface register offsets */ +#define SNOOP_CTRL_REG 0x0 +#define SH_OVERRIDE_REG 0x4 +#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100 +#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104 +#define QOS_CTRL_REG 0x10c +#define MAX_OT_REG 0x110 +#define TARGET_LATENCY_REG 0x130 +#define LATENCY_REGULATION_REG 0x134 +#define QOS_RANGE_REG 0x138 + +/* Snoop Control register bit definitions */ +#define DVM_EN_BIT (1 << 1) +#define SNOOP_EN_BIT (1 << 0) + +/* Status register bit definitions */ +#define CHANGE_PENDING_BIT (1 << 0) + +#ifndef __ASSEMBLY__ + +#include + +/* Function declarations */ + +/* + * The CCI-400 driver must be initialized with the base address of the + * CCI-400 device in the platform memory map, and the cluster indices for + * the CCI-400 slave interfaces 3 and 4 respectively. These are the fully + * coherent ACE slave interfaces of CCI-400. + * The cluster indices must either be 0 or 1, corresponding to the level 1 + * affinity instance of the mpidr representing the cluster. A negative cluster + * index indicates that no cluster is present on that slave interface. + */ +void cci_init(uintptr_t cci_base, + int slave_iface3_cluster_ix, + int slave_iface4_cluster_ix); + +void cci_enable_cluster_coherency(unsigned long mpidr); +void cci_disable_cluster_coherency(unsigned long mpidr); + +#endif /* __ASSEMBLY__ */ +#endif /* __CCI_400_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/ccn.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/ccn.h new file mode 100644 index 0000000..2361596 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/ccn.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCN_H__ +#define __CCN_H__ + +/* + * This macro defines the maximum number of master interfaces that reside on + * Request nodes which the CCN driver can accommodate. The driver APIs to add + * and remove Request nodes from snoop/dvm domains take a bit map of master + * interfaces as inputs. The largest C data type that can be used is a 64-bit + * unsigned integer. Hence the value of 64. The platform will have to ensure + * that the master interfaces are numbered from 0-63. + */ +#define CCN_MAX_RN_MASTERS 64 + +/* + * The following constants define the various run modes that the platform can + * request the CCN driver to place the L3 cache in. These map to the + * programmable P-State values in a HN-F P-state register. + */ +#define CCN_L3_RUN_MODE_NOL3 0x0 /* HNF_PM_NOL3 */ +#define CCN_L3_RUN_MODE_SFONLY 0x1 /* HNF_PM_SFONLY */ +#define CCN_L3_RUN_MODE_HAM 0x2 /* HNF_PM_HALF */ +#define CCN_L3_RUN_MODE_FAM 0x3 /* HNF_PM_FULL */ + +/* + * The following macro takes the value returned from a read of a HN-F P-state + * status register and returns the retention state value. + */ +#define CCN_GET_RETENTION_STATE(pstate) ((pstate >> 4) & 0x3) + +/* + * The following macro takes the value returned from a read of a HN-F P-state + * status register and returns the run state value. + */ +#define CCN_GET_RUN_STATE(pstate) (pstate & 0xf) + +#ifndef __ASSEMBLY__ +#include + +/* + * This structure describes some of the implementation defined attributes of the + * CCN IP. It is used by the platform port to specify these attributes in order + * to initialise the CCN driver. The attributes are described below. + * + * 1. The 'num_masters' field specifies the total number of master interfaces + * resident on Request nodes. + * + * 2. The 'master_to_rn_id_map' field is a ponter to an array in which each + * index corresponds to a master interface and its value corresponds to the + * Request node on which the master interface resides. + * This field is not simply defined as an array of size CCN_MAX_RN_MASTERS. + * In reality, a platform will have much fewer master * interfaces than + * CCN_MAX_RN_MASTERS. With an array of this size, it would also have to + * set the unused entries to a suitable value. Zeroing the array would not + * be enough since 0 is also a valid node id. Hence, such an array is not + * used. + * + * 3. The 'periphbase' field is the base address of the programmer's view of the + * CCN IP. + */ +typedef struct ccn_desc { + unsigned int num_masters; + const unsigned char *master_to_rn_id_map; + uintptr_t periphbase; +} ccn_desc_t; + + +void ccn_init(const ccn_desc_t *plat_ccn_desc); +void ccn_enter_snoop_dvm_domain(unsigned long long master_iface_map); +void ccn_exit_snoop_dvm_domain(unsigned long long master_iface_map); +void ccn_enter_dvm_domain(unsigned long long master_iface_map); +void ccn_exit_dvm_domain(unsigned long long master_iface_map); +void ccn_set_l3_run_mode(unsigned int mode); +void ccn_program_sys_addrmap(unsigned int sn0_id, + unsigned int sn1_id, + unsigned int sn2_id, + unsigned int top_addr_bit0, + unsigned int top_addr_bit1, + unsigned char three_sn_en); +unsigned int ccn_get_l3_run_mode(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __CCN_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/gic_v2.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/gic_v2.h new file mode 100644 index 0000000..ce9311e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/gic_v2.h @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GIC_V2_H__ +#define __GIC_V2_H__ + + +#define GIC400_NUM_SPIS 480 +#define MAX_PPIS 14 +#define MAX_SGIS 16 + +#define MIN_SGI_ID 0 +#define MIN_PPI_ID 16 +#define MIN_SPI_ID 32 + +#define GRP0 0 +#define GRP1 1 +#define GIC_PRI_MASK 0xff +#define GIC_HIGHEST_SEC_PRIORITY 0 +#define GIC_LOWEST_SEC_PRIORITY 127 +#define GIC_HIGHEST_NS_PRIORITY 128 +#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ +#define GIC_SPURIOUS_INTERRUPT 1023 +#define GIC_TARGET_CPU_MASK 0xff + +#define ENABLE_GRP0 (1 << 0) +#define ENABLE_GRP1 (1 << 1) + +/* Distributor interface definitions */ +#define GICD_CTLR 0x0 +#define GICD_TYPER 0x4 +#define GICD_IGROUPR 0x80 +#define GICD_ISENABLER 0x100 +#define GICD_ICENABLER 0x180 +#define GICD_ISPENDR 0x200 +#define GICD_ICPENDR 0x280 +#define GICD_ISACTIVER 0x300 +#define GICD_ICACTIVER 0x380 +#define GICD_IPRIORITYR 0x400 +#define GICD_ITARGETSR 0x800 +#define GICD_ICFGR 0xC00 +#define GICD_SGIR 0xF00 +#define GICD_CPENDSGIR 0xF10 +#define GICD_SPENDSGIR 0xF20 + +#define IGROUPR_SHIFT 5 +#define ISENABLER_SHIFT 5 +#define ICENABLER_SHIFT ISENABLER_SHIFT +#define ISPENDR_SHIFT 5 +#define ICPENDR_SHIFT ISPENDR_SHIFT +#define ISACTIVER_SHIFT 5 +#define ICACTIVER_SHIFT ISACTIVER_SHIFT +#define IPRIORITYR_SHIFT 2 +#define ITARGETSR_SHIFT 2 +#define ICFGR_SHIFT 4 +#define CPENDSGIR_SHIFT 2 +#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT + +/* GICD_TYPER bit definitions */ +#define IT_LINES_NO_MASK 0x1f + +/* Physical CPU Interface registers */ +#define GICC_CTLR 0x0 +#define GICC_PMR 0x4 +#define GICC_BPR 0x8 +#define GICC_IAR 0xC +#define GICC_EOIR 0x10 +#define GICC_RPR 0x14 +#define GICC_HPPIR 0x18 +#define GICC_AHPPIR 0x28 +#define GICC_IIDR 0xFC +#define GICC_DIR 0x1000 +#define GICC_PRIODROP GICC_EOIR + +/* Common CPU Interface definitions */ +#define INT_ID_MASK 0x3ff + +/* GICC_CTLR bit definitions */ +#define EOI_MODE_NS (1 << 10) +#define EOI_MODE_S (1 << 9) +#define IRQ_BYP_DIS_GRP1 (1 << 8) +#define FIQ_BYP_DIS_GRP1 (1 << 7) +#define IRQ_BYP_DIS_GRP0 (1 << 6) +#define FIQ_BYP_DIS_GRP0 (1 << 5) +#define CBPR (1 << 4) +#define FIQ_EN (1 << 3) +#define ACK_CTL (1 << 2) + +/* GICC_IIDR bit masks and shifts */ +#define GICC_IIDR_PID_SHIFT 20 +#define GICC_IIDR_ARCH_SHIFT 16 +#define GICC_IIDR_REV_SHIFT 12 +#define GICC_IIDR_IMP_SHIFT 0 + +#define GICC_IIDR_PID_MASK 0xfff +#define GICC_IIDR_ARCH_MASK 0xf +#define GICC_IIDR_REV_MASK 0xf +#define GICC_IIDR_IMP_MASK 0xfff + +/* HYP view virtual CPU Interface registers */ +#define GICH_CTL 0x0 +#define GICH_VTR 0x4 +#define GICH_ELRSR0 0x30 +#define GICH_ELRSR1 0x34 +#define GICH_APR0 0xF0 +#define GICH_LR_BASE 0x100 + +/* Virtual CPU Interface registers */ +#define GICV_CTL 0x0 +#define GICV_PRIMASK 0x4 +#define GICV_BP 0x8 +#define GICV_INTACK 0xC +#define GICV_EOI 0x10 +#define GICV_RUNNINGPRI 0x14 +#define GICV_HIGHESTPEND 0x18 +#define GICV_DEACTIVATE 0x1000 + +#ifndef __ASSEMBLY__ + +#include +#include + +/******************************************************************************* + * GIC Distributor function prototypes + ******************************************************************************/ + +unsigned int gicd_read_igroupr(uintptr_t, unsigned int); +unsigned int gicd_read_isenabler(uintptr_t, unsigned int); +unsigned int gicd_read_icenabler(uintptr_t, unsigned int); +unsigned int gicd_read_ispendr(uintptr_t, unsigned int); +unsigned int gicd_read_icpendr(uintptr_t, unsigned int); +unsigned int gicd_read_isactiver(uintptr_t, unsigned int); +unsigned int gicd_read_icactiver(uintptr_t, unsigned int); +unsigned int gicd_read_ipriorityr(uintptr_t, unsigned int); +unsigned int gicd_read_itargetsr(uintptr_t, unsigned int); +unsigned int gicd_read_icfgr(uintptr_t, unsigned int); +unsigned int gicd_read_cpendsgir(uintptr_t, unsigned int); +unsigned int gicd_read_spendsgir(uintptr_t, unsigned int); +void gicd_write_igroupr(uintptr_t, unsigned int, unsigned int); +void gicd_write_isenabler(uintptr_t, unsigned int, unsigned int); +void gicd_write_icenabler(uintptr_t, unsigned int, unsigned int); +void gicd_write_ispendr(uintptr_t, unsigned int, unsigned int); +void gicd_write_icpendr(uintptr_t, unsigned int, unsigned int); +void gicd_write_isactiver(uintptr_t, unsigned int, unsigned int); +void gicd_write_icactiver(uintptr_t, unsigned int, unsigned int); +void gicd_write_ipriorityr(uintptr_t, unsigned int, unsigned int); +void gicd_write_itargetsr(uintptr_t, unsigned int, unsigned int); +void gicd_write_icfgr(uintptr_t, unsigned int, unsigned int); +void gicd_write_cpendsgir(uintptr_t, unsigned int, unsigned int); +void gicd_write_spendsgir(uintptr_t, unsigned int, unsigned int); +unsigned int gicd_get_igroupr(uintptr_t, unsigned int); +void gicd_set_igroupr(uintptr_t, unsigned int); +void gicd_clr_igroupr(uintptr_t, unsigned int); +void gicd_set_isenabler(uintptr_t, unsigned int); +void gicd_set_icenabler(uintptr_t, unsigned int); +void gicd_set_ispendr(uintptr_t, unsigned int); +void gicd_set_icpendr(uintptr_t, unsigned int); +void gicd_set_isactiver(uintptr_t, unsigned int); +void gicd_set_icactiver(uintptr_t, unsigned int); +void gicd_set_ipriorityr(uintptr_t, unsigned int, unsigned int); +void gicd_set_itargetsr(uintptr_t, unsigned int, unsigned int); + + +/******************************************************************************* + * GIC Distributor interface accessors for reading entire registers + ******************************************************************************/ + +static inline unsigned int gicd_read_ctlr(uintptr_t base) +{ + return mmio_read_32(base + GICD_CTLR); +} + +static inline unsigned int gicd_read_typer(uintptr_t base) +{ + return mmio_read_32(base + GICD_TYPER); +} + +static inline unsigned int gicd_read_sgir(uintptr_t base) +{ + return mmio_read_32(base + GICD_SGIR); +} + + +/******************************************************************************* + * GIC Distributor interface accessors for writing entire registers + ******************************************************************************/ + +static inline void gicd_write_ctlr(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICD_CTLR, val); +} + +static inline void gicd_write_sgir(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICD_SGIR, val); +} + + +/******************************************************************************* + * GIC CPU interface accessors for reading entire registers + ******************************************************************************/ + +static inline unsigned int gicc_read_ctlr(uintptr_t base) +{ + return mmio_read_32(base + GICC_CTLR); +} + +static inline unsigned int gicc_read_pmr(uintptr_t base) +{ + return mmio_read_32(base + GICC_PMR); +} + +static inline unsigned int gicc_read_BPR(uintptr_t base) +{ + return mmio_read_32(base + GICC_BPR); +} + +static inline unsigned int gicc_read_IAR(uintptr_t base) +{ + return mmio_read_32(base + GICC_IAR); +} + +static inline unsigned int gicc_read_EOIR(uintptr_t base) +{ + return mmio_read_32(base + GICC_EOIR); +} + +static inline unsigned int gicc_read_hppir(uintptr_t base) +{ + return mmio_read_32(base + GICC_HPPIR); +} + +static inline unsigned int gicc_read_ahppir(uintptr_t base) +{ + return mmio_read_32(base + GICC_AHPPIR); +} + +static inline unsigned int gicc_read_dir(uintptr_t base) +{ + return mmio_read_32(base + GICC_DIR); +} + +static inline unsigned int gicc_read_iidr(uintptr_t base) +{ + return mmio_read_32(base + GICC_IIDR); +} + + +/******************************************************************************* + * GIC CPU interface accessors for writing entire registers + ******************************************************************************/ + +static inline void gicc_write_ctlr(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_CTLR, val); +} + +static inline void gicc_write_pmr(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_PMR, val); +} + +static inline void gicc_write_BPR(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_BPR, val); +} + + +static inline void gicc_write_IAR(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_IAR, val); +} + +static inline void gicc_write_EOIR(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_EOIR, val); +} + +static inline void gicc_write_hppir(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_HPPIR, val); +} + +static inline void gicc_write_dir(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_DIR, val); +} + +/******************************************************************************* + * Prototype of function to map an interrupt type to the interrupt line used to + * signal it. + ******************************************************************************/ +uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type); + +#endif /*__ASSEMBLY__*/ + +#endif /* __GIC_V2_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/gic_v3.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/gic_v3.h new file mode 100644 index 0000000..c410626 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/gic_v3.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GIC_V3_H__ +#define __GIC_V3_H__ + +#include +#include + + +/* GICv3 Re-distributor interface registers & shifts */ +#define GICR_PCPUBASE_SHIFT 0x11 +#define GICR_TYPER 0x08 +#define GICR_WAKER 0x14 + +/* GICR_WAKER bit definitions */ +#define WAKER_CA (1UL << 2) +#define WAKER_PS (1UL << 1) + +/* GICR_TYPER bit definitions */ +#define GICR_TYPER_AFF_SHIFT 32 +#define GICR_TYPER_AFF_MASK 0xffffffff +#define GICR_TYPER_LAST (1UL << 4) + +/* GICv3 ICC_SRE register bit definitions*/ +#define ICC_SRE_EN (1UL << 3) +#define ICC_SRE_SRE (1UL << 0) + +/******************************************************************************* + * GICv3 defintions + ******************************************************************************/ +#define GICV3_AFFLVL_MASK 0xff +#define GICV3_AFF0_SHIFT 0 +#define GICV3_AFF1_SHIFT 8 +#define GICV3_AFF2_SHIFT 16 +#define GICV3_AFF3_SHIFT 24 +#define GICV3_AFFINITY_MASK 0xffffffff + +/******************************************************************************* + * Function prototypes + ******************************************************************************/ +uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr); + +/******************************************************************************* + * GIC Redistributor interface accessors + ******************************************************************************/ +static inline uint32_t gicr_read_waker(uintptr_t base) +{ + return mmio_read_32(base + GICR_WAKER); +} + +static inline void gicr_write_waker(uintptr_t base, uint32_t val) +{ + mmio_write_32(base + GICR_WAKER, val); +} + +static inline uint64_t gicr_read_typer(uintptr_t base) +{ + return mmio_read_64(base + GICR_TYPER); +} + + +#endif /* __GIC_V3_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/nic_400.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/nic_400.h new file mode 100644 index 0000000..1031662 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/nic_400.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NIC_400_H__ +#define __NIC_400_H__ + +/* + * Address of slave 'n' security setting in the NIC-400 address region + * control + */ +#define NIC400_ADDR_CTRL_SECURITY_REG(n) (0x8 + (n) * 4) + +#endif /* __NIC_400_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/pl011.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/pl011.h new file mode 100644 index 0000000..7c4df62 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/pl011.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PL011_H__ +#define __PL011_H__ + +/* PL011 Registers */ +#define UARTDR 0x000 +#define UARTRSR 0x004 +#define UARTECR 0x004 +#define UARTFR 0x018 +#define UARTILPR 0x020 +#define UARTIBRD 0x024 +#define UARTFBRD 0x028 +#define UARTLCR_H 0x02C +#define UARTCR 0x030 +#define UARTIFLS 0x034 +#define UARTIMSC 0x038 +#define UARTRIS 0x03C +#define UARTMIS 0x040 +#define UARTICR 0x044 +#define UARTDMACR 0x048 + +/* Data status bits */ +#define UART_DATA_ERROR_MASK 0x0F00 + +/* Status reg bits */ +#define UART_STATUS_ERROR_MASK 0x0F + +/* Flag reg bits */ +#define PL011_UARTFR_RI (1 << 8) /* Ring indicator */ +#define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */ +#define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */ +#define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */ +#define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */ +#define PL011_UARTFR_BUSY (1 << 3) /* UART busy */ +#define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */ +#define PL011_UARTFR_DSR (1 << 1) /* Data set ready */ +#define PL011_UARTFR_CTS (1 << 0) /* Clear to send */ + +#define PL011_UARTFR_TXFF_BIT 5 /* Transmit FIFO full bit in UARTFR register */ +#define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in UARTFR register */ + +/* Control reg bits */ +#define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */ +#define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */ +#define PL011_UARTCR_RTS (1 << 11) /* Request to send */ +#define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */ +#define PL011_UARTCR_RXE (1 << 9) /* Receive enable */ +#define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */ +#define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */ +#define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */ + +#if !defined(PL011_LINE_CONTROL) +/* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */ +#define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8) +#endif + +/* Line Control Register Bits */ +#define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */ +#define PL011_UARTLCR_H_WLEN_8 (3 << 5) +#define PL011_UARTLCR_H_WLEN_7 (2 << 5) +#define PL011_UARTLCR_H_WLEN_6 (1 << 5) +#define PL011_UARTLCR_H_WLEN_5 (0 << 5) +#define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */ +#define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */ +#define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */ +#define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */ +#define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */ + +#endif /* __PL011_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/sp804_delay_timer.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/sp804_delay_timer.h new file mode 100644 index 0000000..1531e5a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/sp804_delay_timer.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SP804_DELAY_TIMER_H__ +#define __SP804_DELAY_TIMER_H__ + +#include +#include + + +uint32_t sp804_get_timer_value(void); + +void sp804_timer_ops_init(uintptr_t base_addr, const timer_ops_t *ops); + +#define sp804_timer_init(base_addr, clk_mult, clk_div) \ + do { \ + static const timer_ops_t sp804_timer_ops = { \ + sp804_get_timer_value, \ + (clk_mult), \ + (clk_div) \ + }; \ + sp804_timer_ops_init((base_addr), &sp804_timer_ops); \ + } while (0) + +#endif /* __SP804_DELAY_TIMER_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/tzc400.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/tzc400.h new file mode 100644 index 0000000..a5312c4 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/arm/tzc400.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TZC400_H__ +#define __TZC400_H__ + + +#define BUILD_CONFIG_OFF 0x000 +#define ACTION_OFF 0x004 +#define GATE_KEEPER_OFF 0x008 +#define SPECULATION_CTRL_OFF 0x00c +#define INT_STATUS 0x010 +#define INT_CLEAR 0x014 + +#define FAIL_ADDRESS_LOW_OFF 0x020 +#define FAIL_ADDRESS_HIGH_OFF 0x024 +#define FAIL_CONTROL_OFF 0x028 +#define FAIL_ID 0x02c + +#define REGION_BASE_LOW_OFF 0x100 +#define REGION_BASE_HIGH_OFF 0x104 +#define REGION_TOP_LOW_OFF 0x108 +#define REGION_TOP_HIGH_OFF 0x10c +#define REGION_ATTRIBUTES_OFF 0x110 +#define REGION_ID_ACCESS_OFF 0x114 +#define REGION_NUM_OFF(region) (0x20 * region) + +/* ID Registers */ +#define PID0_OFF 0xfe0 +#define PID1_OFF 0xfe4 +#define PID2_OFF 0xfe8 +#define PID3_OFF 0xfec +#define PID4_OFF 0xfd0 +#define PID5_OFF 0xfd4 +#define PID6_OFF 0xfd8 +#define PID7_OFF 0xfdc +#define CID0_OFF 0xff0 +#define CID1_OFF 0xff4 +#define CID2_OFF 0xff8 +#define CID3_OFF 0xffc + +#define BUILD_CONFIG_NF_SHIFT 24 +#define BUILD_CONFIG_NF_MASK 0x3 +#define BUILD_CONFIG_AW_SHIFT 8 +#define BUILD_CONFIG_AW_MASK 0x3f +#define BUILD_CONFIG_NR_SHIFT 0 +#define BUILD_CONFIG_NR_MASK 0x1f + +/* Not describing the case where regions 1 to 8 overlap */ +#define ACTION_RV_SHIFT 0 +#define ACTION_RV_MASK 0x3 +#define ACTION_RV_LOWOK 0x0 +#define ACTION_RV_LOWERR 0x1 +#define ACTION_RV_HIGHOK 0x2 +#define ACTION_RV_HIGHERR 0x3 + +/* + * Number of gate keepers is implementation defined. But we know the max for + * this device is 4. Get implementation details from BUILD_CONFIG. + */ +#define GATE_KEEPER_OS_SHIFT 16 +#define GATE_KEEPER_OS_MASK 0xf +#define GATE_KEEPER_OR_SHIFT 0 +#define GATE_KEEPER_OR_MASK 0xf +#define GATE_KEEPER_FILTER_MASK 0x1 + +/* Speculation is enabled by default. */ +#define SPECULATION_CTRL_WRITE_DISABLE (1 << 1) +#define SPECULATION_CTRL_READ_DISABLE (1 << 0) + +/* Max number of filters allowed is 4. */ +#define INT_STATUS_OVERLAP_SHIFT 16 +#define INT_STATUS_OVERLAP_MASK 0xf +#define INT_STATUS_OVERRUN_SHIFT 8 +#define INT_STATUS_OVERRUN_MASK 0xf +#define INT_STATUS_STATUS_SHIFT 0 +#define INT_STATUS_STATUS_MASK 0xf + +#define INT_CLEAR_CLEAR_SHIFT 0 +#define INT_CLEAR_CLEAR_MASK 0xf + +#define FAIL_CONTROL_DIR_SHIFT (1 << 24) +#define FAIL_CONTROL_DIR_READ 0x0 +#define FAIL_CONTROL_DIR_WRITE 0x1 +#define FAIL_CONTROL_NS_SHIFT (1 << 21) +#define FAIL_CONTROL_NS_SECURE 0x0 +#define FAIL_CONTROL_NS_NONSECURE 0x1 +#define FAIL_CONTROL_PRIV_SHIFT (1 << 20) +#define FAIL_CONTROL_PRIV_PRIV 0x0 +#define FAIL_CONTROL_PRIV_UNPRIV 0x1 + +/* + * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. + * Platform should provide the value on initialisation. + */ +#define FAIL_ID_VNET_SHIFT 24 +#define FAIL_ID_VNET_MASK 0xf +#define FAIL_ID_ID_SHIFT 0 + +/* Used along with 'tzc_region_attributes_t' below */ +#define REG_ATTR_SEC_SHIFT 30 +#define REG_ATTR_F_EN_SHIFT 0 +#define REG_ATTR_F_EN_MASK 0xf +#define REG_ATTR_FILTER_BIT(x) ((1 << x) << REG_ATTR_F_EN_SHIFT) +#define REG_ATTR_FILTER_BIT_ALL (REG_ATTR_F_EN_MASK << \ + REG_ATTR_F_EN_SHIFT) + +#define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16 +#define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0 +#define REGION_ID_ACCESS_NSAID_ID_MASK 0xf + + +/* Macros for setting Region ID access permissions based on NSAID */ +#define TZC_REGION_ACCESS_RD(id) \ + ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ + REGION_ID_ACCESS_NSAID_RD_EN_SHIFT) +#define TZC_REGION_ACCESS_WR(id) \ + ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ + REGION_ID_ACCESS_NSAID_WR_EN_SHIFT) +#define TZC_REGION_ACCESS_RDWR(id) \ + (TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id)) + +#define TZC400_COMPONENT_ID 0xb105f00d + + +#ifndef __ASSEMBLY__ + +#include + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ + +/* + * What type of action is expected when an access violation occurs. + * The memory requested is zeroed. But we can also raise and event to + * let the system know it happened. + * We can raise an interrupt(INT) and/or cause an exception(ERR). + * TZC_ACTION_NONE - No interrupt, no Exception + * TZC_ACTION_ERR - No interrupt, raise exception -> sync external + * data abort + * TZC_ACTION_INT - Raise interrupt, no exception + * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync + * external data abort + */ +typedef enum { + TZC_ACTION_NONE = 0, + TZC_ACTION_ERR = 1, + TZC_ACTION_INT = 2, + TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) +} tzc_action_t; + +/* + * Controls secure access to a region. If not enabled secure access is not + * allowed to region. + */ +typedef enum { + TZC_REGION_S_NONE = 0, + TZC_REGION_S_RD = 1, + TZC_REGION_S_WR = 2, + TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR) +} tzc_region_attributes_t; + + +void tzc_init(uintptr_t base); +void tzc_configure_region0(tzc_region_attributes_t sec_attr, + uint32_t ns_device_access); +void tzc_configure_region(uint32_t filters, + uint8_t region, + uint64_t region_base, + uint64_t region_top, + tzc_region_attributes_t sec_attr, + uint32_t ns_device_access); +void tzc_enable_filters(void); +void tzc_disable_filters(void); +void tzc_set_action(tzc_action_t action); + +#endif /* __ASSEMBLY__ */ + +#endif /* __TZC400__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/auth_common.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/auth_common.h new file mode 100644 index 0000000..52a895e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/auth_common.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AUTH_COMMON_H__ +#define __AUTH_COMMON_H__ + +/* + * Authentication framework common types + */ + +/* + * Type of parameters that can be extracted from an image and + * used for authentication + */ +typedef enum auth_param_type_enum { + AUTH_PARAM_NONE, + AUTH_PARAM_RAW_DATA, /* Raw image data */ + AUTH_PARAM_SIG, /* The image signature */ + AUTH_PARAM_SIG_ALG, /* The image signature algorithm */ + AUTH_PARAM_HASH, /* A hash (including the algorithm) */ + AUTH_PARAM_PUB_KEY, /* A public key */ +} auth_param_type_t; + +/* + * Defines an authentication parameter. The cookie will be interpreted by the + * image parser module. + */ +typedef struct auth_param_type_desc_s { + auth_param_type_t type; + void *cookie; +} auth_param_type_desc_t; + +/* + * Store a pointer to the authentication parameter and its length + */ +typedef struct auth_param_data_desc_s { + void *ptr; + unsigned int len; +} auth_param_data_desc_t; + +/* + * Authentication parameter descriptor, including type and value + */ +typedef struct auth_param_desc_s { + auth_param_type_desc_t *type_desc; + auth_param_data_desc_t data; +} auth_param_desc_t; + +/* + * The method type defines how an image is authenticated + */ +typedef enum auth_method_type_enum { + AUTH_METHOD_NONE = 0, + AUTH_METHOD_HASH, /* Authenticate by hash matching */ + AUTH_METHOD_SIG, /* Authenticate by PK operation */ + AUTH_METHOD_NUM /* Number of methods */ +} auth_method_type_t; + +/* + * Parameters for authentication by hash matching + */ +typedef struct auth_method_param_hash_s { + auth_param_type_desc_t *data; /* Data to hash */ + auth_param_type_desc_t *hash; /* Hash to match with */ +} auth_method_param_hash_t; + +/* + * Parameters for authentication by signature + */ +typedef struct auth_method_param_sig_s { + auth_param_type_desc_t *pk; /* Public key */ + auth_param_type_desc_t *sig; /* Signature to check */ + auth_param_type_desc_t *alg; /* Signature algorithm */ + auth_param_type_desc_t *data; /* Data signed */ +} auth_method_param_sig_t; + +/* + * Parameters for authentication by NV counter + */ +typedef struct auth_method_param_nv_ctr_s { + auth_param_type_desc_t *nv_ctr; /* NV counter value */ +} auth_method_param_nv_ctr_t; + +/* + * Authentication method descriptor + */ +typedef struct auth_method_desc_s { + auth_method_type_t type; + union { + auth_method_param_hash_t hash; + auth_method_param_sig_t sig; + auth_method_param_nv_ctr_t nv_ctr; + } param; +} auth_method_desc_t; + +/* + * Helper macro to define an authentication parameter type descriptor + */ +#define AUTH_PARAM_TYPE_DESC(_type, _cookie) \ + { \ + .type = _type, \ + .cookie = (void *)_cookie \ + } + +/* + * Helper macro to define an authentication parameter data descriptor + */ +#define AUTH_PARAM_DATA_DESC(_ptr, _len) \ + { \ + .ptr = (void *)_ptr, \ + .len = (unsigned int)_len \ + } + +#endif /* __AUTH_COMMON_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/auth_mod.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/auth_mod.h new file mode 100644 index 0000000..0f19b5c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/auth_mod.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AUTH_MOD_H__ +#define __AUTH_MOD_H__ + +#if TRUSTED_BOARD_BOOT + +#include +#include +#include + +/* + * Image flags + */ +#define IMG_FLAG_AUTHENTICATED (1 << 0) + + +/* + * Authentication image descriptor + */ +typedef struct auth_img_desc_s { + unsigned int img_id; + const struct auth_img_desc_s *parent; + img_type_t img_type; + auth_method_desc_t img_auth_methods[AUTH_METHOD_NUM]; + auth_param_desc_t authenticated_data[COT_MAX_VERIFIED_PARAMS]; +} auth_img_desc_t; + +/* Public functions */ +void auth_mod_init(void); +int auth_mod_get_parent_id(unsigned int img_id, unsigned int *parent_id); +int auth_mod_verify_img(unsigned int img_id, + void *img_ptr, + unsigned int img_len); + +/* Macro to register a CoT defined as an array of auth_img_desc_t */ +#define REGISTER_COT(_cot) \ + const auth_img_desc_t *const cot_desc_ptr = \ + (const auth_img_desc_t *const)&_cot[0]; \ + unsigned int auth_img_flags[sizeof(_cot)/sizeof(_cot[0])]; + +#endif /* TRUSTED_BOARD_BOOT */ + +#endif /* __AUTH_MOD_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/crypto_mod.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/crypto_mod.h new file mode 100644 index 0000000..5a55624 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/crypto_mod.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CRYPTO_MOD_H__ +#define __CRYPTO_MOD_H__ + +/* Return values */ +enum crypto_ret_value { + CRYPTO_SUCCESS = 0, + CRYPTO_ERR_INIT, + CRYPTO_ERR_HASH, + CRYPTO_ERR_SIGNATURE, + CRYPTO_ERR_UNKNOWN +}; + +/* + * Cryptographic library descriptor + */ +typedef struct crypto_lib_desc_s { + const char *name; + + /* Initialize library. This function is not expected to fail. All errors + * must be handled inside the function, asserting or panicing in case of + * a non-recoverable error */ + void (*init)(void); + + /* Verify a digital signature. Return one of the + * 'enum crypto_ret_value' options */ + int (*verify_signature)(void *data_ptr, unsigned int data_len, + void *sig_ptr, unsigned int sig_len, + void *sig_alg, unsigned int sig_alg_len, + void *pk_ptr, unsigned int pk_len); + + /* Verify a hash. Return one of the 'enum crypto_ret_value' options */ + int (*verify_hash)(void *data_ptr, unsigned int data_len, + void *digest_info_ptr, unsigned int digest_info_len); +} crypto_lib_desc_t; + +/* Public functions */ +void crypto_mod_init(void); +int crypto_mod_verify_signature(void *data_ptr, unsigned int data_len, + void *sig_ptr, unsigned int sig_len, + void *sig_alg, unsigned int sig_alg_len, + void *pk_ptr, unsigned int pk_len); +int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, + void *digest_info_ptr, unsigned int digest_info_len); + +/* Macro to register a cryptographic library */ +#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash) \ + const crypto_lib_desc_t crypto_lib_desc = { \ + .name = _name, \ + .init = _init, \ + .verify_signature = _verify_signature, \ + .verify_hash = _verify_hash \ + } + +#endif /* __CRYPTO_MOD_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/img_parser_mod.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/img_parser_mod.h new file mode 100644 index 0000000..d80e0fb --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/img_parser_mod.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IMG_PARSER_MOD_H__ +#define __IMG_PARSER_MOD_H__ + +#include + +/* + * Return values + */ +enum img_parser_ret_value { + IMG_PARSER_OK, + IMG_PARSER_ERR, /* Parser internal error */ + IMG_PARSER_ERR_FORMAT, /* Malformed image */ + IMG_PARSER_ERR_NOT_FOUND /* Authentication data not found */ +}; + +/* + * Image types. A parser should be instantiated and registered for each type + */ +typedef enum img_type_enum { + IMG_RAW, /* Binary image */ + IMG_PLAT, /* Platform specific format */ + IMG_CERT, /* X509v3 certificate */ + IMG_MAX_TYPES, +} img_type_t; + +/* Image parser library structure */ +typedef struct img_parser_lib_desc_s { + img_type_t img_type; + const char *name; + + void (*init)(void); + int (*check_integrity)(void *img, unsigned int img_len); + int (*get_auth_param)(const auth_param_type_desc_t *type_desc, + void *img, unsigned int img_len, + void **param, unsigned int *param_len); +} img_parser_lib_desc_t; + +/* Exported functions */ +void img_parser_init(void); +int img_parser_check_integrity(img_type_t img_type, + void *img, unsigned int img_len); +int img_parser_get_auth_param(img_type_t img_type, + const auth_param_type_desc_t *type_desc, + void *img, unsigned int img_len, + void **param_ptr, unsigned int *param_len); + +/* Macro to register an image parser library */ +#define REGISTER_IMG_PARSER_LIB(_type, _name, _init, _check_int, _get_param) \ + static const img_parser_lib_desc_t __img_parser_lib_desc_##_type \ + __attribute__ ((section(".img_parser_lib_descs"), used)) = { \ + .img_type = _type, \ + .name = _name, \ + .init = _init, \ + .check_integrity = _check_int, \ + .get_auth_param = _get_param \ + } + +#endif /* __IMG_PARSER_MOD_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/mbedtls/mbedtls_common.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/mbedtls/mbedtls_common.h new file mode 100644 index 0000000..eb22e8a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/mbedtls/mbedtls_common.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MBEDTLS_COMMON_H__ +#define __MBEDTLS_COMMON_H__ + +void mbedtls_init(void); + +#endif /* __MBEDTLS_COMMON_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/mbedtls/mbedtls_config.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/mbedtls/mbedtls_config.h new file mode 100644 index 0000000..8a000f0 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/auth/mbedtls/mbedtls_config.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MBEDTLS_CONFIG_H__ +#define __MBEDTLS_CONFIG_H__ + +/* + * Key algorithms currently supported on mbedTLS libraries + */ +#define MBEDTLS_RSA 1 +#define MBEDTLS_ECDSA 2 + +/* + * Configuration file to build PolarSSL with the required features for + * Trusted Boot + */ + +#define POLARSSL_PLATFORM_MEMORY +#define POLARSSL_PLATFORM_NO_STD_FUNCTIONS + +#define POLARSSL_PKCS1_V15 +#define POLARSSL_PKCS1_V21 + +#define POLARSSL_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION +#define POLARSSL_X509_CHECK_KEY_USAGE +#define POLARSSL_X509_CHECK_EXTENDED_KEY_USAGE + +#define POLARSSL_ASN1_PARSE_C +#define POLARSSL_ASN1_WRITE_C + +#define POLARSSL_BASE64_C +#define POLARSSL_BIGNUM_C + +#define POLARSSL_ERROR_C +#define POLARSSL_MD_C + +#define POLARSSL_MEMORY_BUFFER_ALLOC_C +#define POLARSSL_OID_C + +#define POLARSSL_PK_C +#define POLARSSL_PK_PARSE_C +#define POLARSSL_PK_WRITE_C + +#define POLARSSL_PLATFORM_C + +#if (MBEDTLS_KEY_ALG_ID == MBEDTLS_ECDSA) +#define POLARSSL_ECDSA_C +#define POLARSSL_ECP_C +#define POLARSSL_ECP_DP_SECP256R1_ENABLED +#elif (MBEDTLS_KEY_ALG_ID == MBEDTLS_RSA) +#define POLARSSL_RSA_C +#endif + +#define POLARSSL_SHA256_C + +#define POLARSSL_VERSION_C + +#define POLARSSL_X509_USE_C +#define POLARSSL_X509_CRT_PARSE_C + +/* MPI / BIGNUM options */ +#define POLARSSL_MPI_WINDOW_SIZE 2 +#define POLARSSL_MPI_MAX_SIZE 256 + +/* Memory buffer allocator options */ +#define POLARSSL_MEMORY_ALIGN_MULTIPLE 8 + +#include "polarssl/check_config.h" + +/* System headers required to build mbedTLS with the current configuration */ +#include + +#endif /* __MBEDTLS_CONFIG_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/console.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/console.h new file mode 100644 index 0000000..d374157 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/console.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CONSOLE_H__ +#define __CONSOLE_H__ + +#include + +int console_init(uintptr_t base_addr, + unsigned int uart_clk, unsigned int baud_rate); +int console_putc(int c); +int console_getc(void); + +#endif /* __CONSOLE_H__ */ + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/delay_timer.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/delay_timer.h new file mode 100644 index 0000000..4f3bdc8 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/delay_timer.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DELAY_TIMER_H__ +#define __DELAY_TIMER_H__ + +#include + +/******************************************************************** + * A simple timer driver providing synchronous delay functionality. + * The driver must be initialized with a structure that provides a + * function pointer to return the timer value and a clock + * multiplier/divider. The ratio of the multiplier and the divider is + * the clock frequency in MHz. + ********************************************************************/ + +typedef struct timer_ops { + uint32_t (*get_timer_value)(void); + uint32_t clk_mult; + uint32_t clk_div; +} timer_ops_t; + +void mdelay(uint32_t msec); +void udelay(uint32_t usec); +void timer_init(const timer_ops_t *ops); + + +#endif /* __DELAY_TIMER_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_driver.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_driver.h new file mode 100644 index 0000000..adb38b0 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_driver.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_DRIVER_H__ +#define __IO_DRIVER_H__ + +#include +#include + + +/* Generic IO entity structure,representing an accessible IO construct on the + * device, such as a file */ +typedef struct io_entity { + struct io_dev_info *dev_handle; + uintptr_t info; +} io_entity_t; + + +/* Device info structure, providing device-specific functions and a means of + * adding driver-specific state */ +typedef struct io_dev_info { + const struct io_dev_funcs *funcs; + uintptr_t info; +} io_dev_info_t; + + +/* Structure used to create a connection to a type of device */ +typedef struct io_dev_connector { + /* dev_open opens a connection to a particular device driver */ + int (*dev_open)(const uintptr_t dev_spec, io_dev_info_t **dev_info); +} io_dev_connector_t; + + +/* Structure to hold device driver function pointers */ +typedef struct io_dev_funcs { + io_type_t (*type)(void); + int (*open)(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); + int (*seek)(io_entity_t *entity, int mode, ssize_t offset); + int (*size)(io_entity_t *entity, size_t *length); + int (*read)(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read); + int (*write)(io_entity_t *entity, const uintptr_t buffer, + size_t length, size_t *length_written); + int (*close)(io_entity_t *entity); + int (*dev_init)(io_dev_info_t *dev_info, const uintptr_t init_params); + int (*dev_close)(io_dev_info_t *dev_info); +} io_dev_funcs_t; + + +/* Operations intended to be performed during platform initialisation */ + +/* Register an IO device */ +int io_register_device(const io_dev_info_t *dev_info); + +#endif /* __IO_DRIVER_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_fip.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_fip.h new file mode 100644 index 0000000..90b2fd0 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_fip.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2014 ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_FIP_H__ +#define __IO_FIP_H__ + +struct io_dev_connector; + +int register_io_dev_fip(const struct io_dev_connector **dev_con); + +#endif /* __IO_FIP_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_memmap.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_memmap.h new file mode 100644 index 0000000..7ee60fe --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_memmap.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_MEMMAP_H__ +#define __IO_MEMMAP_H__ + +struct io_dev_connector; + +int register_io_dev_memmap(const struct io_dev_connector **dev_con); + +#endif /* __IO_MEMMAP_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_semihosting.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_semihosting.h new file mode 100644 index 0000000..8902a6f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_semihosting.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_SH_H__ +#define __IO_SH_H__ + +struct io_dev_connector; + +int register_io_dev_sh(const struct io_dev_connector **dev_con); + +#endif /* __IO_SH_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_storage.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_storage.h new file mode 100644 index 0000000..e98dcd0 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/io/io_storage.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_H__ +#define __IO_H__ + +#include +#include /* For ssize_t */ +#include + + +/* Device type which can be used to enable policy decisions about which device + * to access */ +typedef enum { + IO_TYPE_INVALID, + IO_TYPE_SEMIHOSTING, + IO_TYPE_MEMMAP, + IO_TYPE_FIRMWARE_IMAGE_PACKAGE, + IO_TYPE_MAX +} io_type_t; + + +/* Modes used when seeking data on a supported device */ +typedef enum { + IO_SEEK_INVALID, + IO_SEEK_SET, + IO_SEEK_END, + IO_SEEK_CUR, + IO_SEEK_MAX +} io_seek_mode_t; + + +/* Connector type, providing a means of identifying a device to open */ +struct io_dev_connector; + + +/* File specification - used to refer to data on a device supporting file-like + * entities */ +typedef struct io_file_spec { + const char *path; + unsigned int mode; +} io_file_spec_t; + +/* UUID specification - used to refer to data accessed using UUIDs (i.e. FIP + * images) */ +typedef struct io_uuid_spec { + const uuid_t uuid; +} io_uuid_spec_t; + +/* Block specification - used to refer to data on a device supporting + * block-like entities */ +typedef struct io_block_spec { + size_t offset; + size_t length; +} io_block_spec_t; + + +/* Access modes used when accessing data on a device */ +#define IO_MODE_INVALID (0) +#define IO_MODE_RO (1 << 0) +#define IO_MODE_RW (1 << 1) + + +/* Return codes reported by 'io_*' APIs */ +#define IO_SUCCESS (0) +#define IO_FAIL (-1) +#define IO_NOT_SUPPORTED (-2) +#define IO_RESOURCES_EXHAUSTED (-3) + + +/* Open a connection to a device */ +int io_dev_open(const struct io_dev_connector *dev_con, + const uintptr_t dev_spec, + uintptr_t *dev_handle); + + +/* Initialise a device explicitly - to permit lazy initialisation or + * re-initialisation */ +int io_dev_init(uintptr_t dev_handle, const uintptr_t init_params); + +/* TODO: Consider whether an explicit "shutdown" API should be included */ + +/* Close a connection to a device */ +int io_dev_close(uintptr_t dev_handle); + + +/* Synchronous operations */ +int io_open(uintptr_t dev_handle, const uintptr_t spec, uintptr_t *handle); + +int io_seek(uintptr_t handle, io_seek_mode_t mode, ssize_t offset); + +int io_size(uintptr_t handle, size_t *length); + +int io_read(uintptr_t handle, uintptr_t buffer, size_t length, + size_t *length_read); + +int io_write(uintptr_t handle, const uintptr_t buffer, size_t length, + size_t *length_written); + +int io_close(uintptr_t handle); + + +#endif /* __IO_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/ti/uart/uart_16550.h b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/ti/uart/uart_16550.h new file mode 100644 index 0000000..2c814ef --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/drivers/ti/uart/uart_16550.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __UART_16550_H__ +#define __UART_16550_H__ + +/* UART16550 Registers */ +#define UARTTX 0x0 +#define UARTRX 0x0 +#define UARTDLL 0x0 +#define UARTIER 0x4 +#define UARTDLLM 0x4 +#define UARTIIR 0x8 +#define UARTFCR 0x8 +#define UARTLCR 0xc +#define UARTMCR 0x10 +#define UARTLSR 0x14 +#define UARTMSR 0x18 +#define UARTSPR 0x1c +#define UARTCSR 0x20 +#define UARTRXFIFOCFG 0x24 +#define UARTMIE 0x28 +#define UARTVNDR 0x2c +#define UARTASR 0x3c + +/* FIFO Control Register bits */ +#define UARTFCR_FIFOMD_16450 (0 << 6) +#define UARTFCR_FIFOMD_16550 (1 << 6) +#define UARTFCR_RXTRIG_1 (0 << 6) +#define UARTFCR_RXTRIG_4 (1 << 6) +#define UARTFCR_RXTRIG_8 (2 << 6) +#define UARTFCR_RXTRIG_16 (3 << 6) +#define UARTFCR_TXTRIG_1 (0 << 4) +#define UARTFCR_TXTRIG_4 (1 << 4) +#define UARTFCR_TXTRIG_8 (2 << 4) +#define UARTFCR_TXTRIG_16 (3 << 4) +#define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */ +#define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */ +#define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */ +#define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */ + +/* Line Control Register bits */ +#define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */ +#define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */ +#define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */ +#define UARTLCR_EVEN (1 << 4) /* Even Parity Format */ +#define UARTLCR_PAR (1 << 3) /* Parity */ +#define UARTLCR_STOP (1 << 2) /* Stop Bit */ +#define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */ +#define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */ +#define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */ +#define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */ + +/* Line Status Register bits */ +#define UARTLSR_RXFIFOEMT (1 << 9) /* Rx Fifo Empty */ +#define UARTLSR_TXFIFOFULL (1 << 8) /* Tx Fifo Full */ +#define UARTLSR_RXFIFOERR (1 << 7) /* Rx Fifo Error */ +#define UARTLSR_TEMT (1 << 6) /* Tx Shift Register Empty */ +#define UARTLSR_THRE (1 << 5) /* Tx Holding Register Empty */ +#define UARTLSR_BRK (1 << 4) /* Break Condition Detected */ +#define UARTLSR_FERR (1 << 3) /* Framing Error */ +#define UARTLSR_PERR (1 << 3) /* Parity Error */ +#define UARTLSR_OVRF (1 << 2) /* Rx Overrun Error */ +#define UARTLSR_RDR (1 << 2) /* Rx Data Ready */ + +#endif /* __UART_16550_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/lib/aarch64/arch.h b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/aarch64/arch.h new file mode 100644 index 0000000..912643d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/aarch64/arch.h @@ -0,0 +1,467 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_H__ +#define __ARCH_H__ + + +/******************************************************************************* + * MIDR bit definitions + ******************************************************************************/ +#define MIDR_IMPL_MASK 0xff +#define MIDR_IMPL_SHIFT 0x18 +#define MIDR_VAR_SHIFT 20 +#define MIDR_VAR_BITS 4 +#define MIDR_REV_SHIFT 0 +#define MIDR_REV_BITS 4 +#define MIDR_PN_MASK 0xfff +#define MIDR_PN_SHIFT 0x4 + +/******************************************************************************* + * MPIDR macros + ******************************************************************************/ +#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK +#define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS +#define MPIDR_AFFINITY_BITS 8 +#define MPIDR_AFFLVL_MASK 0xff +#define MPIDR_AFF0_SHIFT 0 +#define MPIDR_AFF1_SHIFT 8 +#define MPIDR_AFF2_SHIFT 16 +#define MPIDR_AFF3_SHIFT 32 +#define MPIDR_AFFINITY_MASK 0xff00ffffff +#define MPIDR_AFFLVL_SHIFT 3 +#define MPIDR_AFFLVL0 0 +#define MPIDR_AFFLVL1 1 +#define MPIDR_AFFLVL2 2 +#define MPIDR_AFFLVL3 3 +#define MPIDR_AFFLVL0_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL1_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL2_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL3_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) +/* + * The MPIDR_MAX_AFFLVL count starts from 0. Take care to + * add one while using this macro to define array sizes. + * TODO: Support only the first 3 affinity levels for now. + */ +#define MPIDR_MAX_AFFLVL 2 + +/* Constant to highlight the assumption that MPIDR allocation starts from 0 */ +#define FIRST_MPIDR 0 + +/******************************************************************************* + * Definitions for CPU system register interface to GICv3 + ******************************************************************************/ +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 +#define ICC_PMR_EL1 S3_0_C4_C6_0 + +/******************************************************************************* + * Generic timer memory mapped registers & offsets + ******************************************************************************/ +#define CNTCR_OFF 0x000 +#define CNTFID_OFF 0x020 + +#define CNTCR_EN (1 << 0) +#define CNTCR_HDBG (1 << 1) +#define CNTCR_FCREQ(x) ((x) << 8) + +/******************************************************************************* + * System register bit definitions + ******************************************************************************/ +/* CLIDR definitions */ +#define LOUIS_SHIFT 21 +#define LOC_SHIFT 24 +#define CLIDR_FIELD_WIDTH 3 + +/* CSSELR definitions */ +#define LEVEL_SHIFT 1 + +/* D$ set/way op type defines */ +#define DCISW 0x0 +#define DCCISW 0x1 +#define DCCSW 0x2 + +/* ID_AA64PFR0_EL1 definitions */ +#define ID_AA64PFR0_EL0_SHIFT 0 +#define ID_AA64PFR0_EL1_SHIFT 4 +#define ID_AA64PFR0_EL2_SHIFT 8 +#define ID_AA64PFR0_EL3_SHIFT 12 +#define ID_AA64PFR0_ELX_MASK 0xf + +/* ID_PFR1_EL1 definitions */ +#define ID_PFR1_VIRTEXT_SHIFT 12 +#define ID_PFR1_VIRTEXT_MASK 0xf +#define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \ + & ID_PFR1_VIRTEXT_MASK) + +/* SCTLR definitions */ +#define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ + (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \ + (1 << 4)) + +#define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ + (1 << 11)) +#define SCTLR_AARCH32_EL1_RES1 \ + ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \ + (1 << 3)) + +#define SCTLR_M_BIT (1 << 0) +#define SCTLR_A_BIT (1 << 1) +#define SCTLR_C_BIT (1 << 2) +#define SCTLR_SA_BIT (1 << 3) +#define SCTLR_I_BIT (1 << 12) +#define SCTLR_WXN_BIT (1 << 19) +#define SCTLR_EE_BIT (1 << 25) + +/* CPACR_El1 definitions */ +#define CPACR_EL1_FPEN(x) (x << 20) +#define CPACR_EL1_FP_TRAP_EL0 0x1 +#define CPACR_EL1_FP_TRAP_ALL 0x2 +#define CPACR_EL1_FP_TRAP_NONE 0x3 + +/* SCR definitions */ +#define SCR_RES1_BITS ((1 << 4) | (1 << 5)) +#define SCR_TWE_BIT (1 << 13) +#define SCR_TWI_BIT (1 << 12) +#define SCR_ST_BIT (1 << 11) +#define SCR_RW_BIT (1 << 10) +#define SCR_SIF_BIT (1 << 9) +#define SCR_HCE_BIT (1 << 8) +#define SCR_SMD_BIT (1 << 7) +#define SCR_EA_BIT (1 << 3) +#define SCR_FIQ_BIT (1 << 2) +#define SCR_IRQ_BIT (1 << 1) +#define SCR_NS_BIT (1 << 0) +#define SCR_VALID_BIT_MASK 0x2f8f + +/* HCR definitions */ +#define HCR_RW_BIT (1ull << 31) +#define HCR_AMO_BIT (1 << 5) +#define HCR_IMO_BIT (1 << 4) +#define HCR_FMO_BIT (1 << 3) + +/* CNTHCTL_EL2 definitions */ +#define EVNTEN_BIT (1 << 2) +#define EL1PCEN_BIT (1 << 1) +#define EL1PCTEN_BIT (1 << 0) + +/* CNTKCTL_EL1 definitions */ +#define EL0PTEN_BIT (1 << 9) +#define EL0VTEN_BIT (1 << 8) +#define EL0PCTEN_BIT (1 << 0) +#define EL0VCTEN_BIT (1 << 1) +#define EVNTEN_BIT (1 << 2) +#define EVNTDIR_BIT (1 << 3) +#define EVNTI_SHIFT 4 +#define EVNTI_MASK 0xf + +/* CPTR_EL3 definitions */ +#define TCPAC_BIT (1 << 31) +#define TTA_BIT (1 << 20) +#define TFP_BIT (1 << 10) + +/* CPSR/SPSR definitions */ +#define DAIF_FIQ_BIT (1 << 0) +#define DAIF_IRQ_BIT (1 << 1) +#define DAIF_ABT_BIT (1 << 2) +#define DAIF_DBG_BIT (1 << 3) +#define SPSR_DAIF_SHIFT 6 +#define SPSR_DAIF_MASK 0xf + +#define SPSR_AIF_SHIFT 6 +#define SPSR_AIF_MASK 0x7 + +#define SPSR_E_SHIFT 9 +#define SPSR_E_MASK 0x1 +#define SPSR_E_LITTLE 0x0 +#define SPSR_E_BIG 0x1 + +#define SPSR_T_SHIFT 5 +#define SPSR_T_MASK 0x1 +#define SPSR_T_ARM 0x0 +#define SPSR_T_THUMB 0x1 + +#define DISABLE_ALL_EXCEPTIONS \ + (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) + + +/* + * TCR defintions + */ +#define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23)) +#define TCR_EL1_IPS_SHIFT 32 +#define TCR_EL3_PS_SHIFT 16 + +/* (internal) physical address size bits in EL3/EL1 */ +#define TCR_PS_BITS_4GB (0x0) +#define TCR_PS_BITS_64GB (0x1) +#define TCR_PS_BITS_1TB (0x2) +#define TCR_PS_BITS_4TB (0x3) +#define TCR_PS_BITS_16TB (0x4) +#define TCR_PS_BITS_256TB (0x5) + +#define ADDR_MASK_48_TO_63 0xFFFF000000000000UL +#define ADDR_MASK_44_TO_47 0x0000F00000000000UL +#define ADDR_MASK_42_TO_43 0x00000C0000000000UL +#define ADDR_MASK_40_TO_41 0x0000030000000000UL +#define ADDR_MASK_36_TO_39 0x000000F000000000UL +#define ADDR_MASK_32_TO_35 0x0000000F00000000UL + +#define TCR_RGN_INNER_NC (0x0 << 8) +#define TCR_RGN_INNER_WBA (0x1 << 8) +#define TCR_RGN_INNER_WT (0x2 << 8) +#define TCR_RGN_INNER_WBNA (0x3 << 8) + +#define TCR_RGN_OUTER_NC (0x0 << 10) +#define TCR_RGN_OUTER_WBA (0x1 << 10) +#define TCR_RGN_OUTER_WT (0x2 << 10) +#define TCR_RGN_OUTER_WBNA (0x3 << 10) + +#define TCR_SH_NON_SHAREABLE (0x0 << 12) +#define TCR_SH_OUTER_SHAREABLE (0x2 << 12) +#define TCR_SH_INNER_SHAREABLE (0x3 << 12) + +#define MODE_SP_SHIFT 0x0 +#define MODE_SP_MASK 0x1 +#define MODE_SP_EL0 0x0 +#define MODE_SP_ELX 0x1 + +#define MODE_RW_SHIFT 0x4 +#define MODE_RW_MASK 0x1 +#define MODE_RW_64 0x0 +#define MODE_RW_32 0x1 + +#define MODE_EL_SHIFT 0x2 +#define MODE_EL_MASK 0x3 +#define MODE_EL3 0x3 +#define MODE_EL2 0x2 +#define MODE_EL1 0x1 +#define MODE_EL0 0x0 + +#define MODE32_SHIFT 0 +#define MODE32_MASK 0xf +#define MODE32_usr 0x0 +#define MODE32_fiq 0x1 +#define MODE32_irq 0x2 +#define MODE32_svc 0x3 +#define MODE32_mon 0x6 +#define MODE32_abt 0x7 +#define MODE32_hyp 0xa +#define MODE32_und 0xb +#define MODE32_sys 0xf + +#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) +#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) +#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) +#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) + +#define SPSR_64(el, sp, daif) \ + (MODE_RW_64 << MODE_RW_SHIFT | \ + ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \ + ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \ + ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT) + +#define SPSR_MODE32(mode, isa, endian, aif) \ + (MODE_RW_32 << MODE_RW_SHIFT | \ + ((mode) & MODE32_MASK) << MODE32_SHIFT | \ + ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ + ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ + ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) + +/* + * CTR_EL0 definitions + */ +#define CTR_CWG_SHIFT 24 +#define CTR_CWG_MASK 0xf +#define CTR_ERG_SHIFT 20 +#define CTR_ERG_MASK 0xf +#define CTR_DMINLINE_SHIFT 16 +#define CTR_DMINLINE_MASK 0xf +#define CTR_L1IP_SHIFT 14 +#define CTR_L1IP_MASK 0x3 +#define CTR_IMINLINE_SHIFT 0 +#define CTR_IMINLINE_MASK 0xf + +#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */ +#define SIZE_FROM_LOG2_WORDS(n) (4 << (n)) + + +/* Physical timer control register bit fields shifts and masks */ +#define CNTP_CTL_ENABLE_SHIFT 0 +#define CNTP_CTL_IMASK_SHIFT 1 +#define CNTP_CTL_ISTATUS_SHIFT 2 + +#define CNTP_CTL_ENABLE_MASK 1 +#define CNTP_CTL_IMASK_MASK 1 +#define CNTP_CTL_ISTATUS_MASK 1 + +#define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \ + CNTP_CTL_ENABLE_MASK) +#define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \ + CNTP_CTL_IMASK_MASK) +#define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \ + CNTP_CTL_ISTATUS_MASK) + +#define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT) +#define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT) + +#define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT)) +#define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT)) + +/* Miscellaneous MMU related constants */ +#define NUM_2MB_IN_GB (1 << 9) +#define NUM_4K_IN_2MB (1 << 9) +#define NUM_GB_IN_4GB (1 << 2) + +#define TWO_MB_SHIFT 21 +#define ONE_GB_SHIFT 30 +#define FOUR_KB_SHIFT 12 + +#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) +#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) +#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) + +#define INVALID_DESC 0x0 +#define BLOCK_DESC 0x1 +#define TABLE_DESC 0x3 + +#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT +#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT +#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT + +#define LEVEL1 1 +#define LEVEL2 2 +#define LEVEL3 3 + +#define XN (1ull << 2) +#define PXN (1ull << 1) +#define CONT_HINT (1ull << 0) + +#define UPPER_ATTRS(x) (x & 0x7) << 52 +#define NON_GLOBAL (1 << 9) +#define ACCESS_FLAG (1 << 8) +#define NSH (0x0 << 6) +#define OSH (0x2 << 6) +#define ISH (0x3 << 6) + +#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT +#define PAGE_SIZE (1 << PAGE_SIZE_SHIFT) +#define PAGE_SIZE_MASK (PAGE_SIZE - 1) +#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0) + +#define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */ +#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT) + +#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT +#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT) + +/* Values for number of entries in each MMU translation table */ +#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) +#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT) +#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1) + +/* Values to convert a memory address to an index into a translation table */ +#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT +#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) +#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) + +/* + * AP[1] bit is ignored by hardware and is + * treated as if it is One in EL2/EL3 + */ +#define AP_RO (0x1 << 5) +#define AP_RW (0x0 << 5) + +#define NS (0x1 << 3) +#define ATTR_SO_INDEX 0x2 +#define ATTR_DEVICE_INDEX 0x1 +#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0 +#define LOWER_ATTRS(x) (((x) & 0xfff) << 2) +#define ATTR_SO (0x0) +#define ATTR_DEVICE (0x4) +#define ATTR_IWBWA_OWBWA_NTR (0xff) +#define MAIR_ATTR_SET(attr, index) (attr << (index << 3)) + +/* Exception Syndrome register bits and bobs */ +#define ESR_EC_SHIFT 26 +#define ESR_EC_MASK 0x3f +#define ESR_EC_LENGTH 6 +#define EC_UNKNOWN 0x0 +#define EC_WFE_WFI 0x1 +#define EC_AARCH32_CP15_MRC_MCR 0x3 +#define EC_AARCH32_CP15_MRRC_MCRR 0x4 +#define EC_AARCH32_CP14_MRC_MCR 0x5 +#define EC_AARCH32_CP14_LDC_STC 0x6 +#define EC_FP_SIMD 0x7 +#define EC_AARCH32_CP10_MRC 0x8 +#define EC_AARCH32_CP14_MRRC_MCRR 0xc +#define EC_ILLEGAL 0xe +#define EC_AARCH32_SVC 0x11 +#define EC_AARCH32_HVC 0x12 +#define EC_AARCH32_SMC 0x13 +#define EC_AARCH64_SVC 0x15 +#define EC_AARCH64_HVC 0x16 +#define EC_AARCH64_SMC 0x17 +#define EC_AARCH64_SYS 0x18 +#define EC_IABORT_LOWER_EL 0x20 +#define EC_IABORT_CUR_EL 0x21 +#define EC_PC_ALIGN 0x22 +#define EC_DABORT_LOWER_EL 0x24 +#define EC_DABORT_CUR_EL 0x25 +#define EC_SP_ALIGN 0x26 +#define EC_AARCH32_FP 0x28 +#define EC_AARCH64_FP 0x2c +#define EC_SERROR 0x2f + +#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK + +/******************************************************************************* + * Definitions of register offsets and fields in the CNTCTLBase Frame of the + * system level implementation of the Generic Timer. + ******************************************************************************/ +#define CNTNSAR 0x4 +#define CNTNSAR_NS_SHIFT(x) x + +#define CNTACR_BASE(x) (0x40 + (x << 2)) +#define CNTACR_RPCT_SHIFT 0x0 +#define CNTACR_RVCT_SHIFT 0x1 +#define CNTACR_RFRQ_SHIFT 0x2 +#define CNTACR_RVOFF_SHIFT 0x3 +#define CNTACR_RWVT_SHIFT 0x4 +#define CNTACR_RWPT_SHIFT 0x5 + +#endif /* __ARCH_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/lib/aarch64/arch_helpers.h b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/aarch64/arch_helpers.h new file mode 100644 index 0000000..d01ea31 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/aarch64/arch_helpers.h @@ -0,0 +1,320 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_HELPERS_H__ +#define __ARCH_HELPERS_H__ + +#include /* for additional register definitions */ +#include /* For __dead2 */ +#include + +/********************************************************************** + * Macros which create inline functions to read or write CPU system + * registers + *********************************************************************/ + +#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ +static inline uint64_t read_ ## _name(void) \ +{ \ + uint64_t v; \ + __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ + return v; \ +} + +#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ +static inline void write_ ## _name(uint64_t v) \ +{ \ + __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ +} + +#define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \ +static inline void write_ ## _name(const uint64_t v) \ +{ \ + __asm__ volatile ("msr " #_reg_name ", %0" : : "i" (v)); \ +} + +/* Define read function for system register */ +#define DEFINE_SYSREG_READ_FUNC(_name) \ + _DEFINE_SYSREG_READ_FUNC(_name, _name) + +/* Define read & write function for system register */ +#define DEFINE_SYSREG_RW_FUNCS(_name) \ + _DEFINE_SYSREG_READ_FUNC(_name, _name) \ + _DEFINE_SYSREG_WRITE_FUNC(_name, _name) + +/* Define read & write function for renamed system register */ +#define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ + _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ + _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) + +/* Define write function for special system registers */ +#define DEFINE_SYSREG_WRITE_CONST_FUNC(_name) \ + _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _name) + + +/********************************************************************** + * Macros to create inline functions for system instructions + *********************************************************************/ + +/* Define function for simple system instruction */ +#define DEFINE_SYSOP_FUNC(_op) \ +static inline void _op(void) \ +{ \ + __asm__ (#_op); \ +} + +/* Define function for system instruction with type specifier */ +#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ +static inline void _op ## _type(void) \ +{ \ + __asm__ (#_op " " #_type); \ +} + +/* Define function for system instruction with register parameter */ +#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ +static inline void _op ## _type(uint64_t v) \ +{ \ + __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ +} + +/******************************************************************************* + * Aarch64 translation tables manipulation helper prototypes +******************************************************************************/ +uint64_t create_table_desc(uint64_t *next_table_ptr); +uint64_t create_block_desc(uint64_t desc, uint64_t addr, uint32_t level); +uint64_t create_device_block(uint64_t output_addr, uint32_t level, uint32_t ns); +uint64_t create_romem_block(uint64_t output_addr, uint32_t level, uint32_t ns); +uint64_t create_rwmem_block(uint64_t output_addr, uint32_t level, uint32_t ns); + +/******************************************************************************* + * TLB maintenance accessor prototypes + ******************************************************************************/ +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) +DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) + +/******************************************************************************* + * Cache maintenance accessor prototypes + ******************************************************************************/ +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) + +/******************************************************************************* + * Address translation accessor prototypes + ******************************************************************************/ +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r) +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w) +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r) +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w) + +void flush_dcache_range(uint64_t, uint64_t); +void clean_dcache_range(uint64_t, uint64_t); +void inv_dcache_range(uint64_t, uint64_t); +void dcsw_op_louis(uint32_t); +void dcsw_op_all(uint32_t); + +void disable_mmu_el3(void); +void disable_mmu_icache_el3(void); + +/******************************************************************************* + * Misc. accessor prototypes + ******************************************************************************/ + +DEFINE_SYSREG_WRITE_CONST_FUNC(daifset) +DEFINE_SYSREG_WRITE_CONST_FUNC(daifclr) + +#define enable_irq() write_daifclr(DAIF_IRQ_BIT) +#define enable_fiq() write_daifclr(DAIF_FIQ_BIT) +#define enable_serror() write_daifclr(DAIF_ABT_BIT) +#define enable_debug_exceptions() write_daifclr(DAIF_DBG_BIT) +#define disable_irq() write_daifset(DAIF_IRQ_BIT) +#define disable_fiq() write_daifset(DAIF_FIQ_BIT) +#define disable_serror() write_daifset(DAIF_ABT_BIT) +#define disable_debug_exceptions() write_daifset(DAIF_DBG_BIT) + +DEFINE_SYSREG_READ_FUNC(par_el1) +DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) +DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) +DEFINE_SYSREG_READ_FUNC(CurrentEl) +DEFINE_SYSREG_RW_FUNCS(daif) +DEFINE_SYSREG_RW_FUNCS(spsr_el1) +DEFINE_SYSREG_RW_FUNCS(spsr_el2) +DEFINE_SYSREG_RW_FUNCS(spsr_el3) +DEFINE_SYSREG_RW_FUNCS(elr_el1) +DEFINE_SYSREG_RW_FUNCS(elr_el2) +DEFINE_SYSREG_RW_FUNCS(elr_el3) + +DEFINE_SYSOP_FUNC(wfi) +DEFINE_SYSOP_FUNC(wfe) +DEFINE_SYSOP_FUNC(sev) +DEFINE_SYSOP_TYPE_FUNC(dsb, sy) +DEFINE_SYSOP_TYPE_FUNC(dmb, sy) +DEFINE_SYSOP_TYPE_FUNC(dsb, ish) +DEFINE_SYSOP_TYPE_FUNC(dmb, ish) +DEFINE_SYSOP_FUNC(isb) + +uint32_t get_afflvl_shift(uint32_t); +uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t); + + +void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); +void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); + +/******************************************************************************* + * System register accessor prototypes + ******************************************************************************/ +DEFINE_SYSREG_READ_FUNC(midr_el1) +DEFINE_SYSREG_READ_FUNC(mpidr_el1) + +DEFINE_SYSREG_RW_FUNCS(scr_el3) +DEFINE_SYSREG_RW_FUNCS(hcr_el2) + +DEFINE_SYSREG_RW_FUNCS(vbar_el1) +DEFINE_SYSREG_RW_FUNCS(vbar_el2) +DEFINE_SYSREG_RW_FUNCS(vbar_el3) + +DEFINE_SYSREG_RW_FUNCS(sctlr_el1) +DEFINE_SYSREG_RW_FUNCS(sctlr_el2) +DEFINE_SYSREG_RW_FUNCS(sctlr_el3) + +DEFINE_SYSREG_RW_FUNCS(actlr_el1) +DEFINE_SYSREG_RW_FUNCS(actlr_el2) +DEFINE_SYSREG_RW_FUNCS(actlr_el3) + +DEFINE_SYSREG_RW_FUNCS(esr_el1) +DEFINE_SYSREG_RW_FUNCS(esr_el2) +DEFINE_SYSREG_RW_FUNCS(esr_el3) + +DEFINE_SYSREG_RW_FUNCS(afsr0_el1) +DEFINE_SYSREG_RW_FUNCS(afsr0_el2) +DEFINE_SYSREG_RW_FUNCS(afsr0_el3) + +DEFINE_SYSREG_RW_FUNCS(afsr1_el1) +DEFINE_SYSREG_RW_FUNCS(afsr1_el2) +DEFINE_SYSREG_RW_FUNCS(afsr1_el3) + +DEFINE_SYSREG_RW_FUNCS(far_el1) +DEFINE_SYSREG_RW_FUNCS(far_el2) +DEFINE_SYSREG_RW_FUNCS(far_el3) + +DEFINE_SYSREG_RW_FUNCS(mair_el1) +DEFINE_SYSREG_RW_FUNCS(mair_el2) +DEFINE_SYSREG_RW_FUNCS(mair_el3) + +DEFINE_SYSREG_RW_FUNCS(amair_el1) +DEFINE_SYSREG_RW_FUNCS(amair_el2) +DEFINE_SYSREG_RW_FUNCS(amair_el3) + +DEFINE_SYSREG_READ_FUNC(rvbar_el1) +DEFINE_SYSREG_READ_FUNC(rvbar_el2) +DEFINE_SYSREG_READ_FUNC(rvbar_el3) + +DEFINE_SYSREG_RW_FUNCS(rmr_el1) +DEFINE_SYSREG_RW_FUNCS(rmr_el2) +DEFINE_SYSREG_RW_FUNCS(rmr_el3) + +DEFINE_SYSREG_RW_FUNCS(tcr_el1) +DEFINE_SYSREG_RW_FUNCS(tcr_el2) +DEFINE_SYSREG_RW_FUNCS(tcr_el3) + +DEFINE_SYSREG_RW_FUNCS(ttbr0_el1) +DEFINE_SYSREG_RW_FUNCS(ttbr0_el2) +DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) + +DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) + +DEFINE_SYSREG_RW_FUNCS(cptr_el2) +DEFINE_SYSREG_RW_FUNCS(cptr_el3) + +DEFINE_SYSREG_RW_FUNCS(cpacr_el1) +DEFINE_SYSREG_RW_FUNCS(cntfrq_el0) +DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1) +DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1) +DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1) +DEFINE_SYSREG_READ_FUNC(cntpct_el0) +DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) + +DEFINE_SYSREG_RW_FUNCS(tpidr_el3) + +DEFINE_SYSREG_RW_FUNCS(cntvoff_el2) + +DEFINE_SYSREG_RW_FUNCS(vpidr_el2) +DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) + +DEFINE_SYSREG_READ_FUNC(isr_el1) + +DEFINE_SYSREG_READ_FUNC(ctr_el0) + +/* GICv3 System Registers */ + +DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) +DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) + + +#define IS_IN_EL(x) \ + (GET_EL(read_CurrentEl()) == MODE_EL##x) + +#define IS_IN_EL1() IS_IN_EL(1) +#define IS_IN_EL3() IS_IN_EL(3) + +/* Previously defined accesor functions with incomplete register names */ + +#define read_current_el() read_CurrentEl() + +#define dsb() dsbsy() + +#define read_midr() read_midr_el1() + +#define read_mpidr() read_mpidr_el1() + +#define read_scr() read_scr_el3() +#define write_scr(_v) write_scr_el3(_v) + +#define read_hcr() read_hcr_el2() +#define write_hcr(_v) write_hcr_el2(_v) + +#define read_cpacr() read_cpacr_el1() +#define write_cpacr(_v) write_cpacr_el1(_v) + +#endif /* __ARCH_HELPERS_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/lib/aarch64/xlat_tables.h b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/aarch64/xlat_tables.h new file mode 100644 index 0000000..0b5dbdf --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/aarch64/xlat_tables.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __XLAT_TABLES_H__ +#define __XLAT_TABLES_H__ + + +/* + * Flags to override default values used to program system registers while + * enabling the MMU. + */ +#define DISABLE_DCACHE (1 << 0) + +#ifndef __ASSEMBLY__ +#include + +/* Helper macro to define entries for mmap_region_t. It creates + * identity mappings for each region. + */ +#define MAP_REGION_FLAT(adr, sz, attr) MAP_REGION(adr, adr, sz, attr) + +/* Helper macro to define entries for mmap_region_t. It allows to + * re-map address mappings from 'pa' to 'va' for each region. + */ +#define MAP_REGION(pa, va, sz, attr) {(pa), (va), (sz), (attr)} + +/* + * Flags for building up memory mapping attributes. + * These are organised so that a clear bit gives a more restrictive mapping + * that a set bit, that way a bitwise-and two sets of attributes will never give + * an attribute which has greater access rights that any of the original + * attributes. + */ +typedef enum { + MT_DEVICE = 0 << 0, + MT_MEMORY = 1 << 0, + + MT_RO = 0 << 1, + MT_RW = 1 << 1, + + MT_SECURE = 0 << 2, + MT_NS = 1 << 2 +} mmap_attr_t; + +/* + * Structure for specifying a single region of memory. + */ +typedef struct mmap_region { + unsigned long base_pa; + unsigned long base_va; + unsigned long size; + mmap_attr_t attr; +} mmap_region_t; + +void mmap_add_region(unsigned long base_pa, unsigned long base_va, + unsigned long size, unsigned attr); +void mmap_add(const mmap_region_t *mm); + +void init_xlat_tables(void); + +void enable_mmu_el1(uint32_t flags); +void enable_mmu_el3(uint32_t flags); + +#endif /*__ASSEMBLY__*/ +#endif /* __XLAT_TABLES_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/lib/bakery_lock.h b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/bakery_lock.h new file mode 100644 index 0000000..86adb9c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/bakery_lock.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BAKERY_LOCK_H__ +#define __BAKERY_LOCK_H__ + +#include + +#define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT + +#ifndef __ASSEMBLY__ +#include + +/***************************************************************************** + * Internal helper macros used by the bakery lock implementation. + ****************************************************************************/ +/* Convert a ticket to priority */ +#define PRIORITY(t, pos) (((t) << 8) | (pos)) + +#define CHOOSING_TICKET 0x1 +#define CHOSEN_TICKET 0x0 + +#define bakery_is_choosing(info) (info & 0x1) +#define bakery_ticket_number(info) ((info >> 1) & 0x7FFF) +#define make_bakery_data(choosing, number) \ + (((choosing & 0x1) | (number << 1)) & 0xFFFF) + +/***************************************************************************** + * External bakery lock interface. + ****************************************************************************/ +#if USE_COHERENT_MEM +/* + * Bakery locks are stored in coherent memory + * + * Each lock's data is contiguous and fully allocated by the compiler + */ + +typedef struct bakery_lock { + /* + * The lock_data is a bit-field of 2 members: + * Bit[0] : choosing. This field is set when the CPU is + * choosing its bakery number. + * Bits[1 - 15] : number. This is the bakery number allocated. + */ + volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; +} bakery_lock_t; + +#else +/* + * Bakery locks are stored in normal .bss memory + * + * Each lock's data is spread across multiple cache lines, one per CPU, + * but multiple locks can share the same cache line. + * The compiler will allocate enough memory for one CPU's bakery locks, + * the remaining cache lines are allocated by the linker script + */ + +typedef struct bakery_info { + /* + * The lock_data is a bit-field of 2 members: + * Bit[0] : choosing. This field is set when the CPU is + * choosing its bakery number. + * Bits[1 - 15] : number. This is the bakery number allocated. + */ + volatile uint16_t lock_data; +} bakery_info_t; + +typedef bakery_info_t bakery_lock_t; + +#endif /* __USE_COHERENT_MEM__ */ + +inline void bakery_lock_init(bakery_lock_t *bakery) {} +void bakery_lock_get(bakery_lock_t *bakery); +void bakery_lock_release(bakery_lock_t *bakery); + +#define DEFINE_BAKERY_LOCK(_name) bakery_lock_t _name \ + __attribute__ ((section("bakery_lock"))) + +#define DECLARE_BAKERY_LOCK(_name) extern bakery_lock_t _name + + +#endif /* __ASSEMBLY__ */ +#endif /* __BAKERY_LOCK_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cassert.h b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cassert.h new file mode 100644 index 0000000..0e5529d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cassert.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CASSERT_H__ +#define __CASSERT_H__ + +/******************************************************************************* + * Macro to flag a compile time assertion. It uses the preprocessor to generate + * an invalid C construct if 'cond' evaluates to false. + * The following compilation error is triggered if the assertion fails: + * "error: size of array 'msg' is negative" + ******************************************************************************/ +#define CASSERT(cond, msg) typedef char msg[(cond) ? 1 : -1] + +#endif /* __CASSERT_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/aem_generic.h b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/aem_generic.h new file mode 100644 index 0000000..2f701d1 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/aem_generic.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AEM_GENERIC_H__ +#define __AEM_GENERIC_H__ + +/* BASE AEM midr for revision 0 */ +#define BASE_AEM_MIDR 0x410FD0F0 + +/* Foundation AEM midr for revision 0 */ +#define FOUNDATION_AEM_MIDR 0x410FD000 + + +#endif /* __AEM_GENERIC_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/cortex_a53.h b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/cortex_a53.h new file mode 100644 index 0000000..169d8f4 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/cortex_a53.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CORTEX_A53_H__ +#define __CORTEX_A53_H__ + +/* Cortex-A53 midr for revision 0 */ +#define CORTEX_A53_MIDR 0x410FD030 + +/* Retention timer tick definitions */ +#define RETENTION_ENTRY_TICKS_2 0x1 +#define RETENTION_ENTRY_TICKS_8 0x2 +#define RETENTION_ENTRY_TICKS_32 0x3 +#define RETENTION_ENTRY_TICKS_64 0x4 +#define RETENTION_ENTRY_TICKS_128 0x5 +#define RETENTION_ENTRY_TICKS_256 0x6 +#define RETENTION_ENTRY_TICKS_512 0x7 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ + +#define CPUECTLR_SMP_BIT (1 << 6) + +#define CPUECTLR_CPU_RET_CTRL_SHIFT 0 +#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) + +#define CPUECTLR_FPU_RET_CTRL_SHIFT 3 +#define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ + +#define CPUACTLR_DTAH (1 << 24) + +/******************************************************************************* + * L2 Auxiliary Control register specific definitions. + ******************************************************************************/ +#define L2ACTLR_EL1 S3_1_C15_C0_0 /* Instruction def. */ + +#define L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) +#define L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) + +/******************************************************************************* + * L2 Extended Control register specific definitions. + ******************************************************************************/ +#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */ + +#define L2ECTLR_RET_CTRL_SHIFT 0 +#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) + +#endif /* __CORTEX_A53_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/cortex_a57.h b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/cortex_a57.h new file mode 100644 index 0000000..c81259c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/cortex_a57.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CORTEX_A57_H__ +#define __CORTEX_A57_H__ + +/* Cortex-A57 midr for revision 0 */ +#define CORTEX_A57_MIDR 0x410FD070 + +/* Retention timer tick definitions */ +#define RETENTION_ENTRY_TICKS_2 0x1 +#define RETENTION_ENTRY_TICKS_8 0x2 +#define RETENTION_ENTRY_TICKS_32 0x3 +#define RETENTION_ENTRY_TICKS_64 0x4 +#define RETENTION_ENTRY_TICKS_128 0x5 +#define RETENTION_ENTRY_TICKS_256 0x6 +#define RETENTION_ENTRY_TICKS_512 0x7 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ + +#define CPUECTLR_SMP_BIT (1 << 6) +#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) +#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) +#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) + +#define CPUECTLR_CPU_RET_CTRL_SHIFT 0 +#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ + +#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) +#define CPUACTLR_DCC_AS_DCCI (1 << 44) + +/******************************************************************************* + * L2 Control register specific definitions. + ******************************************************************************/ +#define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */ + +#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 +#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 + +#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 + +/******************************************************************************* + * L2 Extended Control register specific definitions. + ******************************************************************************/ +#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */ + +#define L2ECTLR_RET_CTRL_SHIFT 0 +#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) + +#endif /* __CORTEX_A57_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/cortex_a72.h b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/cortex_a72.h new file mode 100644 index 0000000..bb32f9b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/cortex_a72.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CORTEX_A72_H__ +#define __CORTEX_A72_H__ + +/* Cortex-A72 midr for revision 0 */ +#define CORTEX_A72_MIDR 0x410FD080 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ + +#define CPUECTLR_SMP_BIT (1 << 6) +#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) +#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) +#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ + +#define CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56) +#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) +#define CPUACTLR_DCC_AS_DCCI (1 << 44) + +/******************************************************************************* + * L2 Control register specific definitions. + ******************************************************************************/ +#define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */ + +#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 +#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 + +#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 + +#endif /* __CORTEX_A72_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/cpu_macros.S b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/cpu_macros.S new file mode 100644 index 0000000..72c35fb --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/cpu_macros.S @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __CPU_MACROS_S__ +#define __CPU_MACROS_S__ + +#include + +#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ + (MIDR_PN_MASK << MIDR_PN_SHIFT) + + /* + * Define the offsets to the fields in cpu_ops structure. + */ + .struct 0 +CPU_MIDR: /* cpu_ops midr */ + .space 8 +/* Reset fn is needed in BL at reset vector */ +#if IMAGE_BL1 || IMAGE_BL31 +CPU_RESET_FUNC: /* cpu_ops reset_func */ + .space 8 +#endif +#if IMAGE_BL31 /* The power down core and cluster is needed only in BL3-1 */ +CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */ + .space 8 +CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */ + .space 8 +#endif +#if (IMAGE_BL31 && CRASH_REPORTING) +CPU_REG_DUMP: /* cpu specific register dump for crash reporting */ + .space 8 +#endif +CPU_OPS_SIZE = . + + /* + * Convenience macro to declare cpu_ops structure. + * Make sure the structure fields are as per the offsets + * defined above. + */ + .macro declare_cpu_ops _name:req, _midr:req, _noresetfunc = 0 + .section cpu_ops, "a"; .align 3 + .type cpu_ops_\_name, %object + .quad \_midr +#if IMAGE_BL1 || IMAGE_BL31 + .if \_noresetfunc + .quad 0 + .else + .quad \_name\()_reset_func + .endif +#endif +#if IMAGE_BL31 + .quad \_name\()_core_pwr_dwn + .quad \_name\()_cluster_pwr_dwn +#endif +#if (IMAGE_BL31 && CRASH_REPORTING) + .quad \_name\()_cpu_reg_dump +#endif + .endm + +#endif /* __CPU_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/denver.h b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/denver.h new file mode 100644 index 0000000..c7bee80 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/cpus/aarch64/denver.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DENVER_H__ +#define __DENVER_H__ + +/* MIDR for Denver v1.0 */ +#define DENVER_1_0_MIDR 0x4E0F0000 + +/* CPU state ids - implementation defined */ +#define DENVER_CPU_STATE_POWER_DOWN 0x3 + +#endif /* __DENVER_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/lib/mmio.h b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/mmio.h new file mode 100644 index 0000000..19f798f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/mmio.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MMIO_H__ +#define __MMIO_H__ + +#include + +static inline void mmio_write_8(uintptr_t addr, uint8_t value) +{ + *(volatile uint8_t*)addr = value; +} + +static inline uint8_t mmio_read_8(uintptr_t addr) +{ + return *(volatile uint8_t*)addr; +} + +static inline void mmio_write_16(uintptr_t addr, uint16_t value) +{ + *(volatile uint16_t*)addr = value; +} + +static inline uint16_t mmio_read_16(uintptr_t addr) +{ + return *(volatile uint16_t*)addr; +} + +static inline void mmio_write_32(uintptr_t addr, uint32_t value) +{ + *(volatile uint32_t*)addr = value; +} + +static inline uint32_t mmio_read_32(uintptr_t addr) +{ + return *(volatile uint32_t*)addr; +} + +static inline void mmio_write_64(uintptr_t addr, uint64_t value) +{ + *(volatile uint64_t*)addr = value; +} + +static inline uint64_t mmio_read_64(uintptr_t addr) +{ + return *(volatile uint64_t*)addr; +} + +static inline void mmio_clrbits_32(uintptr_t addr, uint32_t clear) +{ + mmio_write_32(addr, mmio_read_32(addr) & ~clear); +} + +static inline void mmio_setbits_32(uintptr_t addr, uint32_t set) +{ + mmio_write_32(addr, mmio_read_32(addr) | set); +} + +static inline void mmio_clrsetbits_32(uintptr_t addr, + uint32_t clear, + uint32_t set) +{ + mmio_write_32(addr, (mmio_read_32(addr) & ~clear) | set); +} + +#endif /* __MMIO_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/lib/semihosting.h b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/semihosting.h new file mode 100644 index 0000000..b4eecc5 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/semihosting.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SEMIHOSTING_H__ +#define __SEMIHOSTING_H__ + +#include +#include /* For ssize_t */ + + +#define SEMIHOSTING_SYS_OPEN 0x01 +#define SEMIHOSTING_SYS_CLOSE 0x02 +#define SEMIHOSTING_SYS_WRITE0 0x04 +#define SEMIHOSTING_SYS_WRITEC 0x03 +#define SEMIHOSTING_SYS_WRITE 0x05 +#define SEMIHOSTING_SYS_READ 0x06 +#define SEMIHOSTING_SYS_READC 0x07 +#define SEMIHOSTING_SYS_SEEK 0x0A +#define SEMIHOSTING_SYS_FLEN 0x0C +#define SEMIHOSTING_SYS_REMOVE 0x0E +#define SEMIHOSTING_SYS_SYSTEM 0x12 +#define SEMIHOSTING_SYS_ERRNO 0x13 + +#define FOPEN_MODE_R 0x0 +#define FOPEN_MODE_RB 0x1 +#define FOPEN_MODE_RPLUS 0x2 +#define FOPEN_MODE_RPLUSB 0x3 +#define FOPEN_MODE_W 0x4 +#define FOPEN_MODE_WB 0x5 +#define FOPEN_MODE_WPLUS 0x6 +#define FOPEN_MODE_WPLUSB 0x7 +#define FOPEN_MODE_A 0x8 +#define FOPEN_MODE_AB 0x9 +#define FOPEN_MODE_APLUS 0xa +#define FOPEN_MODE_APLUSB 0xb + +long semihosting_connection_supported(void); +long semihosting_file_open(const char *file_name, size_t mode); +long semihosting_file_seek(long file_handle, ssize_t offset); +long semihosting_file_read(long file_handle, size_t *length, uintptr_t buffer); +long semihosting_file_write(long file_handle, + size_t *length, + const uintptr_t buffer); +long semihosting_file_close(long file_handle); +long semihosting_file_length(long file_handle); +long semihosting_system(char *command_line); +long semihosting_get_flen(const char *file_name); +long semihosting_download_file(const char *file_name, + size_t buf_size, + uintptr_t buf); +void semihosting_write_char(char character); +void semihosting_write_string(char *string); +char semihosting_read_char(void); + +#endif /* __SEMIHOSTING_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/lib/spinlock.h b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/spinlock.h new file mode 100644 index 0000000..cb0bc3e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/lib/spinlock.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SPINLOCK_H__ +#define __SPINLOCK_H__ + +typedef struct spinlock { + volatile unsigned int lock; +} spinlock_t; + +void spin_lock(spinlock_t *lock); +void spin_unlock(spinlock_t *lock); + +#endif /* __SPINLOCK_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/board/common/board_arm_def.h b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/board/common/board_arm_def.h new file mode 100644 index 0000000..3abf235 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/board/common/board_arm_def.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __BOARD_ARM_DEF_H__ +#define __BOARD_ARM_DEF_H__ + +#include + + +/* + * Required platform porting definitions common to all ARM + * development platforms + */ + +/* Size of cacheable stacks */ +#if DEBUG_XLAT_TABLE +# define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL1 +#if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE 0x1000 +#else +# define PLATFORM_STACK_SIZE 0x440 +#endif +#elif IMAGE_BL2 +# if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE 0x1000 +# else +# define PLATFORM_STACK_SIZE 0x400 +# endif +#elif IMAGE_BL31 +# define PLATFORM_STACK_SIZE 0x400 +#elif IMAGE_BL32 +# define PLATFORM_STACK_SIZE 0x440 +#endif + +/* + * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the + * plat_arm_mmap array defined for each BL stage. + */ +#if IMAGE_BL1 +# if PLAT_fvp +# define PLAT_ARM_MMAP_ENTRIES 7 +# else +# define PLAT_ARM_MMAP_ENTRIES 6 +# endif +#endif +#if IMAGE_BL2 +# if PLAT_fvp +# define PLAT_ARM_MMAP_ENTRIES 9 +# else +# define PLAT_ARM_MMAP_ENTRIES 8 +# endif +#endif +#if IMAGE_BL31 +#define PLAT_ARM_MMAP_ENTRIES 5 +#endif +#if IMAGE_BL32 +#define PLAT_ARM_MMAP_ENTRIES 4 +#endif + +/* + * Platform specific page table and MMU setup constants + */ +#if IMAGE_BL1 +# if PLAT_juno +# define MAX_XLAT_TABLES 2 +# else +# define MAX_XLAT_TABLES 3 +# endif /* PLAT_ */ +#elif IMAGE_BL2 +# if PLAT_juno +# define MAX_XLAT_TABLES 3 +# else +# define MAX_XLAT_TABLES 4 +# endif /* PLAT_ */ +#elif IMAGE_BL31 +# define MAX_XLAT_TABLES 2 +#elif IMAGE_BL32 +# if ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID +# define MAX_XLAT_TABLES 3 +# else +# define MAX_XLAT_TABLES 2 +# endif +#endif + + +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ + +#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE +#define PLAT_ARM_FIP_MAX_SIZE V2M_FLASH0_SIZE + + +#endif /* __BOARD_ARM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/board/common/board_arm_oid.h b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/board/common/board_arm_oid.h new file mode 100644 index 0000000..92a9bd1 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/board/common/board_arm_oid.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BOARD_ARM_OID_H__ +#define __BOARD_ARM_OID_H__ + +/* + * This is the list of the different extensions containing relevant information + * to establish the chain of trust. + * + * The OIDs shown here are just an example. Real OIDs should be obtained from + * the ITU-T. + */ + +/* Non-volatile counter extensions */ +#define TZ_FW_NVCOUNTER_OID "1.2.3.1" +#define NTZ_FW_NVCOUNTER_OID "1.2.3.2" + +/* BL2 extensions */ +#define BL2_HASH_OID "1.2.3.3" + +/* Trusted Key extensions */ +#define TZ_WORLD_PK_OID "1.2.3.4" +#define NTZ_WORLD_PK_OID "1.2.3.5" + +/* BL3-1 extensions */ +#define BL31_CONTENT_CERT_PK_OID "1.2.3.6" +#define BL31_HASH_OID "1.2.3.7" + +/* BL3-0 extensions */ +#define BL30_CONTENT_CERT_PK_OID "1.2.3.8" +#define BL30_HASH_OID "1.2.3.9" + +/* BL3-2 extensions */ +#define BL32_CONTENT_CERT_PK_OID "1.2.3.10" +#define BL32_HASH_OID "1.2.3.11" + +/* BL3-3 extensions */ +#define BL33_CONTENT_CERT_PK_OID "1.2.3.12" +#define BL33_HASH_OID "1.2.3.13" + + +#endif /* __BOARD_ARM_OID_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/board/common/board_css_def.h b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/board/common/board_css_def.h new file mode 100644 index 0000000..2e32b41 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/board/common/board_css_def.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BOARD_CSS_DEF_H__ +#define __BOARD_CSS_DEF_H__ + +#include +#include +#include + +/* + * Definitions common to all ARM CSS-based development platforms + */ + +/* Platform ID address */ +#define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0 + +/* Platform ID related accessors */ +#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f +#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0 +#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00 +#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8 +#define BOARD_CSS_PLAT_TYPE_RTL 0x00 +#define BOARD_CSS_PLAT_TYPE_FPGA 0x01 +#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02 +#define BOARD_CSS_PLAT_TYPE_FVP 0x03 + +#ifndef __ASSEMBLY__ + +#include + +#define BOARD_CSS_GET_PLAT_TYPE(addr) \ + ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ + >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) + +#endif /* __ASSEMBLY__ */ + + +/* + * Required platform porting definitions common to all ARM CSS-based + * development platforms + */ + +#define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x180000000) + +/* UART related constants */ +#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ + +#define PLAT_ARM_CRASH_UART_BASE SOC_CSS_UART1_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ + +#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE +#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ + + +#endif /* __BOARD_CSS_DEF_H__ */ + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/board/common/v2m_def.h b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/board/common/v2m_def.h new file mode 100644 index 0000000..7a4ef5a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/board/common/v2m_def.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __V2M_DEF_H__ +#define __V2M_DEF_H__ + +#include + + +/* V2M motherboard system registers & offsets */ +#define V2M_SYSREGS_BASE 0x1c010000 +#define V2M_SYS_ID 0x0 +#define V2M_SYS_SWITCH 0x4 +#define V2M_SYS_LED 0x8 +#define V2M_SYS_CFGDATA 0xa0 +#define V2M_SYS_CFGCTRL 0xa4 +#define V2M_SYS_CFGSTATUS 0xa8 + +#define V2M_CFGCTRL_START (1 << 31) +#define V2M_CFGCTRL_RW (1 << 30) +#define V2M_CFGCTRL_FUNC_SHIFT 20 +#define V2M_CFGCTRL_FUNC(fn) (fn << V2M_CFGCTRL_FUNC_SHIFT) +#define V2M_FUNC_CLK_GEN 0x01 +#define V2M_FUNC_TEMP 0x04 +#define V2M_FUNC_DB_RESET 0x05 +#define V2M_FUNC_SCC_CFG 0x06 +#define V2M_FUNC_SHUTDOWN 0x08 +#define V2M_FUNC_REBOOT 0x09 + +/* + * V2M sysled bit definitions. The values written to this + * register are defined in arch.h & runtime_svc.h. Only + * used by the primary cpu to diagnose any cold boot issues. + * + * SYS_LED[0] - Security state (S=0/NS=1) + * SYS_LED[2:1] - Exception Level (EL3-EL0) + * SYS_LED[7:3] - Exception Class (Sync/Async & origin) + * + */ +#define V2M_SYS_LED_SS_SHIFT 0x0 +#define V2M_SYS_LED_EL_SHIFT 0x1 +#define V2M_SYS_LED_EC_SHIFT 0x3 + +#define V2M_SYS_LED_SS_MASK 0x1 +#define V2M_SYS_LED_EL_MASK 0x3 +#define V2M_SYS_LED_EC_MASK 0x1f + +/* V2M sysid register bits */ +#define V2M_SYS_ID_REV_SHIFT 28 +#define V2M_SYS_ID_HBI_SHIFT 16 +#define V2M_SYS_ID_BLD_SHIFT 12 +#define V2M_SYS_ID_ARCH_SHIFT 8 +#define V2M_SYS_ID_FPGA_SHIFT 0 + +#define V2M_SYS_ID_REV_MASK 0xf +#define V2M_SYS_ID_HBI_MASK 0xfff +#define V2M_SYS_ID_BLD_MASK 0xf +#define V2M_SYS_ID_ARCH_MASK 0xf +#define V2M_SYS_ID_FPGA_MASK 0xff + +#define V2M_SYS_ID_BLD_LENGTH 4 + + +/* NOR Flash */ +#define V2M_FLASH0_BASE 0x08000000 +#define V2M_FLASH0_SIZE 0x04000000 + +#define V2M_IOFPGA_BASE 0x1c000000 +#define V2M_IOFPGA_SIZE 0x03000000 + +/* PL011 UART related constants */ +#define V2M_IOFPGA_UART0_BASE 0x1c090000 +#define V2M_IOFPGA_UART1_BASE 0x1c0a0000 +#define V2M_IOFPGA_UART2_BASE 0x1c0b0000 +#define V2M_IOFPGA_UART3_BASE 0x1c0c0000 + +#define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000 +#define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000 +#define V2M_IOFPGA_UART2_CLK_IN_HZ 24000000 +#define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000 + +/* SP804 timer related constants */ +#define V2M_SP804_TIMER0_BASE 0x1C110000 +#define V2M_SP804_TIMER1_BASE 0x1C120000 + +#define V2M_MAP_FLASH0 MAP_REGION_FLAT(V2M_FLASH0_BASE,\ + V2M_FLASH0_SIZE, \ + MT_MEMORY | MT_RO | MT_SECURE) + +#define V2M_MAP_IOFPGA MAP_REGION_FLAT(V2M_IOFPGA_BASE,\ + V2M_IOFPGA_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + + + +#endif /* __V2M_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/common/aarch64/arm_macros.S b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/common/aarch64/arm_macros.S new file mode 100644 index 0000000..594b096 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/common/aarch64/arm_macros.S @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ARM_MACROS_S__ +#define __ARM_MACROS_S__ + +#include +#include +#include + +.section .rodata.gic_reg_name, "aS" +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ + " Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below utility macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL3-1 on ARM standard platforms. + * Expects: GICD base in x16, GICC base in x17 + * Clobbers: x0 - x10, sp + * --------------------------------------------- + */ + .macro arm_print_gic_regs + /* Load the gicc reg list to x6 */ + adr x6, gicc_regs + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + .endm + + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* ------------------------------------------------ + * The below required platform porting macro prints + * out relevant interconnect registers whenever an + * unhandled exception is taken in BL3-1. + * Clobbers: x0 - x9, sp + * ------------------------------------------------ + */ + .macro plat_print_interconnect_regs + adr x6, cci_iface_regs + /* Store in x7 the base address of the first interface */ + mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX)) + ldr w8, [x7, #SNOOP_CTRL_REG] + /* Store in x7 the base address of the second interface */ + mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX)) + ldr w9, [x7, #SNOOP_CTRL_REG] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + .endm + + +#endif /* __ARM_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/common/arm_config.h b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/common/arm_config.h new file mode 100644 index 0000000..0b16127 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/common/arm_config.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ARM_CONFIG_H__ +#define __ARM_CONFIG_H__ + +#include + +enum arm_config_flags { + /* Whether Base memory map is in use */ + ARM_CONFIG_BASE_MMAP = 0x1, + /* Whether CCI should be enabled */ + ARM_CONFIG_HAS_CCI = 0x2, + /* Whether TZC should be configured */ + ARM_CONFIG_HAS_TZC = 0x4 +}; + +typedef struct arm_config { + uintptr_t gicd_base; + uintptr_t gicc_base; + uintptr_t gich_base; + uintptr_t gicv_base; + unsigned int max_aff0; + unsigned int max_aff1; + unsigned long flags; +} arm_config_t; + + +/* If used, arm_config must be defined and populated in the platform port */ +extern arm_config_t arm_config; + +static inline const arm_config_t *get_arm_config(void) +{ + return &arm_config; +} + + +#endif /* __ARM_CONFIG_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/common/arm_def.h b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/common/arm_def.h new file mode 100644 index 0000000..c236970 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/common/arm_def.h @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ARM_DEF_H__ +#define __ARM_DEF_H__ + +#include +#include +#include +#include +#include + + +/****************************************************************************** + * Definitions common to all ARM standard platforms + *****************************************************************************/ + +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + +#define ARM_CLUSTER_COUNT 2ull + +#define ARM_CACHE_WRITEBACK_SHIFT 6 + +/* + * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The + * power levels have a 1:1 mapping with the MPIDR affinity levels. + */ +#define ARM_PWR_LVL0 MPIDR_AFFLVL0 +#define ARM_PWR_LVL1 MPIDR_AFFLVL1 + +/* + * Macros for local power states in ARM platforms encoded by State-ID field + * within the power-state parameter. + */ +/* Local power state for power domains in Run state. */ +#define ARM_LOCAL_STATE_RUN 0 +/* Local power state for retention. Valid only for CPU power domains */ +#define ARM_LOCAL_STATE_RET 1 +/* Local power state for OFF/power-down. Valid for CPU and cluster power + domains */ +#define ARM_LOCAL_STATE_OFF 2 + +/* Memory location options for TSP */ +#define ARM_TRUSTED_SRAM_ID 0 +#define ARM_TRUSTED_DRAM_ID 1 +#define ARM_DRAM_ID 2 + +/* The first 4KB of Trusted SRAM are used as shared memory */ +#define ARM_TRUSTED_SRAM_BASE 0x04000000 +#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE +#define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ + +/* The remaining Trusted SRAM is used to load the BL images */ +#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ + ARM_SHARED_RAM_SIZE) +#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ + ARM_SHARED_RAM_SIZE) + +/* + * The top 16MB of DRAM1 is configured as secure access only using the TZC + * - SCP TZC DRAM: If present, DRAM reserved for SCP use + * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use + */ +#define ARM_TZC_DRAM1_SIZE MAKE_ULL(0x01000000) + +#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - \ + ARM_SCP_TZC_DRAM1_SIZE) +#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE +#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ + ARM_SCP_TZC_DRAM1_SIZE - 1) + +#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - \ + ARM_TZC_DRAM1_SIZE) +#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ + ARM_SCP_TZC_DRAM1_SIZE) +#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE - 1) + + +#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE +#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ + ARM_TZC_DRAM1_SIZE) +#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ + ARM_NS_DRAM1_SIZE - 1) + +#define ARM_DRAM1_BASE MAKE_ULL(0x80000000) +#define ARM_DRAM1_SIZE MAKE_ULL(0x80000000) +#define ARM_DRAM1_END (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - 1) + +#define ARM_DRAM2_BASE MAKE_ULL(0x880000000) +#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE +#define ARM_DRAM2_END (ARM_DRAM2_BASE + \ + ARM_DRAM2_SIZE - 1) + +#define ARM_IRQ_SEC_PHY_TIMER 29 + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +#define ARM_SHARED_RAM_ATTR ((PLAT_ARM_SHARED_RAM_CACHED ? \ + MT_MEMORY : MT_DEVICE) \ + | MT_RW | MT_SECURE) + +#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + ARM_SHARED_RAM_BASE, \ + ARM_SHARED_RAM_SIZE, \ + ARM_SHARED_RAM_ATTR) + +#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + ARM_NS_DRAM1_BASE, \ + ARM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ + TSP_SEC_MEM_BASE, \ + TSP_SEC_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + + +/* + * The number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#if USE_COHERENT_MEM +#define ARM_BL_REGIONS 3 +#else +#define ARM_BL_REGIONS 2 +#endif + +#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ + ARM_BL_REGIONS) + +/* Memory mapped Generic timer interfaces */ +#define ARM_SYS_CNTCTL_BASE 0x2a430000 +#define ARM_SYS_CNTREAD_BASE 0x2a800000 +#define ARM_SYS_TIMCTL_BASE 0x2a810000 + +#define ARM_CONSOLE_BAUDRATE 115200 + +/****************************************************************************** + * Required platform porting definitions common to all ARM standard platforms + *****************************************************************************/ + +#define ADDR_SPACE_SIZE (1ull << 32) + +#define PLAT_NUM_PWR_DOMAINS (ARM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) +#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 + +/* + * This macro defines the deepest retention state possible. A higher state + * id will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF + + +#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER0_CORE_COUNT + \ + PLAT_ARM_CLUSTER1_CORE_COUNT) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) + + +/******************************************************************************* + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + ******************************************************************************/ +#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE +#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ + + PLAT_ARM_TRUSTED_ROM_SIZE) +/* + * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using + * the current BL1 RW debug size plus a little space for growth. + */ +#if TRUSTED_BOARD_BOOT +#define BL1_RW_BASE (ARM_BL_RAM_BASE + \ + ARM_BL_RAM_SIZE - \ + 0x9000) +#else +#define BL1_RW_BASE (ARM_BL_RAM_BASE + \ + ARM_BL_RAM_SIZE - \ + 0x6000) +#endif +#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) + +/******************************************************************************* + * BL2 specific defines. + ******************************************************************************/ +/* + * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug + * size plus a little space for growth. + */ +#if TRUSTED_BOARD_BOOT +#define BL2_BASE (BL31_BASE - 0x1D000) +#else +#define BL2_BASE (BL31_BASE - 0xC000) +#endif +#define BL2_LIMIT BL31_BASE + +/******************************************************************************* + * BL3-1 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the + * current BL3-1 debug size plus a little space for growth. + */ +#define BL31_BASE (ARM_BL_RAM_BASE + \ + ARM_BL_RAM_SIZE - \ + 0x1D000) +#define BL31_PROGBITS_LIMIT BL1_RW_BASE +#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) + +/******************************************************************************* + * BL3-2 specific defines. + ******************************************************************************/ +/* + * On ARM standard platforms, the TSP can execute from Trusted SRAM, + * Trusted DRAM (if available) or the DRAM region secured by the TrustZone + * controller. + */ +#if ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID +# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE +# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE +# define TSP_PROGBITS_LIMIT BL2_BASE +# define BL32_BASE ARM_BL_RAM_BASE +# define BL32_LIMIT BL31_BASE +#elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID +# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE +# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE +# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE +# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ + + (1 << 21)) +#elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID +# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE +# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE +# define BL32_BASE ARM_AP_TZC_DRAM1_BASE +# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE) +#else +# error "Unsupported ARM_TSP_RAM_LOCATION_ID value" +#endif + +/* + * ID of the secure physical generic timer interrupt used by the TSP. + */ +#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER + + +/* + * One cache line needed for bakery locks on ARM platforms + */ +#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) + + +#endif /* __ARM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/common/plat_arm.h b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/common/plat_arm.h new file mode 100644 index 0000000..ad41f4f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/common/plat_arm.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __PLAT_ARM_H__ +#define __PLAT_ARM_H__ + +#include +#include +#include +#include +#include + + +/* + * Extern declarations common to ARM standard platforms + */ +extern const mmap_region_t plat_arm_mmap[]; + +#define ARM_CASSERT_MMAP \ + CASSERT((ARRAY_SIZE(plat_arm_mmap) + ARM_BL_REGIONS) \ + <= MAX_MMAP_REGIONS, \ + assert_max_mmap_regions); + +/* + * Utility functions common to ARM standard platforms + */ + +void arm_configure_mmu_el1(unsigned long total_base, + unsigned long total_size, + unsigned long ro_start, + unsigned long ro_limit +#if USE_COHERENT_MEM + , unsigned long coh_start, + unsigned long coh_limit +#endif +); +void arm_configure_mmu_el3(unsigned long total_base, + unsigned long total_size, + unsigned long ro_start, + unsigned long ro_limit +#if USE_COHERENT_MEM + , unsigned long coh_start, + unsigned long coh_limit +#endif +); + +#if IMAGE_BL31 +/* + * Use this macro to instantiate lock before it is used in below + * arm_lock_xxx() macros + */ +#define ARM_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_lock); + +/* + * These are wrapper macros to the Coherent Memory Bakery Lock API. + */ +#define arm_lock_init() bakery_lock_init(&arm_lock) +#define arm_lock_get() bakery_lock_get(&arm_lock) +#define arm_lock_release() bakery_lock_release(&arm_lock) + +#else + +/* + * Empty macros for all other BL stages other than BL3-1 + */ +#define ARM_INSTANTIATE_LOCK +#define arm_lock_init() +#define arm_lock_get() +#define arm_lock_release() + +#endif /* IMAGE_BL31 */ + +#if ARM_RECOM_STATE_ID_ENC +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define ARM_LOCAL_PSTATE_WIDTH 4 +#define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) + +/* Macros to construct the composite power state */ + +/* Make composite power state parameter till power level 0 */ +#if PSCI_EXTENDED_STATE_ID + +#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) +#else +#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) +#endif /* __PSCI_EXTENDED_STATE_ID__ */ + +/* Make composite power state parameter till power level 1 */ +#define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ + arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) + +#endif /* __ARM_RECOM_STATE_ID_ENC__ */ + + +/* CCI utility functions */ +void arm_cci_init(void); + +/* IO storage utility functions */ +void arm_io_setup(void); + +/* Security utility functions */ +void arm_tzc_setup(void); + +/* PM utility functions */ +int arm_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state); +int arm_validate_ns_entrypoint(uintptr_t entrypoint); + +/* Topology utility function */ +int arm_check_mpidr(u_register_t mpidr); + +/* BL1 utility functions */ +void arm_bl1_early_platform_setup(void); +void arm_bl1_platform_setup(void); +void arm_bl1_plat_arch_setup(void); + +/* BL2 utility functions */ +void arm_bl2_early_platform_setup(meminfo_t *mem_layout); +void arm_bl2_platform_setup(void); +void arm_bl2_plat_arch_setup(void); +uint32_t arm_get_spsr_for_bl32_entry(void); +uint32_t arm_get_spsr_for_bl33_entry(void); + +/* BL3-1 utility functions */ +void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2); +void arm_bl31_platform_setup(void); +void arm_bl31_plat_arch_setup(void); + +/* TSP utility functions */ +void arm_tsp_early_platform_setup(void); + + +/* + * Mandatory functions required in ARM standard platforms + */ +void plat_arm_gic_init(void); +void plat_arm_security_setup(void); +void plat_arm_pwrc_setup(void); + +/* + * Optional functions required in ARM standard platforms + */ +void plat_arm_io_setup(void); +int plat_arm_get_alt_image_source( + unsigned int image_id, + uintptr_t *dev_handle, + uintptr_t *image_spec); +unsigned int plat_arm_calc_core_pos(u_register_t mpidr); + + +#endif /* __PLAT_ARM_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/css/common/aarch64/css_macros.S b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/css/common/aarch64/css_macros.S new file mode 100644 index 0000000..2a26eb7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/css/common/aarch64/css_macros.S @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __CSS_MACROS_S__ +#define __CSS_MACROS_S__ + +#include +#include + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC registers whenever an + * unhandled exception is taken in BL3-1. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_print_gic_regs + mov_imm x16, PLAT_CSS_GICD_BASE + mov_imm x17, PLAT_CSS_GICC_BASE + arm_print_gic_regs + .endm + + +#endif /* __CSS_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/css/common/css_def.h b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/css/common/css_def.h new file mode 100644 index 0000000..38ff9dd --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/css/common/css_def.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CSS_DEF_H__ +#define __CSS_DEF_H__ + +#include +#include + +/************************************************************************* + * Definitions common to all ARM Compute SubSystems (CSS) + *************************************************************************/ +#define MHU_PAYLOAD_CACHED 0 + +#define TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE + +#define NSROM_BASE 0x1f000000 +#define NSROM_SIZE 0x00001000 + +/* Following covers CSS Peripherals excluding NSROM and NSRAM */ +#define CSS_DEVICE_BASE 0x20000000 +#define CSS_DEVICE_SIZE 0x0e000000 +#define MHU_BASE 0x2b1f0000 + +#define NSRAM_BASE 0x2e000000 +#define NSRAM_SIZE 0x00008000 + +/* The slave_bootsecure controls access to GPU, DMC and CS. */ +#define CSS_NIC400_SLAVE_BOOTSECURE 8 + +/* Interrupt handling constants */ +#define CSS_IRQ_MHU 69 +#define CSS_IRQ_GPU_SMMU_0 71 +#define CSS_IRQ_TZC 80 +#define CSS_IRQ_TZ_WDOG 86 +#define CSS_IRQ_SEC_SYS_TIMER 91 + +/* + * SCP <=> AP boot configuration + * + * The SCP/AP boot configuration is a 32-bit word located at a known offset from + * the start of the Trusted SRAM. Part of this configuration is which CPU is the + * primary, according to the shift and mask definitions below. + * + * Note that the value stored at this address is only valid at boot time, before + * the BL3-0 image is transferred to SCP. + */ +#define SCP_BOOT_CFG_ADDR (ARM_TRUSTED_SRAM_BASE + 0x80) +#define PRIMARY_CPU_SHIFT 8 +#define PRIMARY_CPU_BIT_WIDTH 4 + +/* + * Base address of the first memory region used for communication between AP + * and SCP. Used by the BOM and SCPI protocols. + * + * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which + * means the SCP/AP configuration data gets overwritten when the AP initiates + * communication with the SCP. + */ +#define SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) + +#define CSS_MAP_DEVICE MAP_REGION_FLAT( \ + CSS_DEVICE_BASE, \ + CSS_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + + +/************************************************************************* + * Required platform porting definitions common to all + * ARM Compute SubSystems (CSS) + ************************************************************************/ + +/* + * Load address of BL3-0 in CSS platform ports + * BL3-0 is loaded to the same place as BL3-1. Once BL3-0 is transferred to the + * SCP, it is discarded and BL3-1 is loaded over the top. + */ +#define BL30_BASE BL31_BASE + +#define PLAT_ARM_SHARED_RAM_CACHED MHU_PAYLOAD_CACHED + +/* Load address of Non-Secure Image for CSS platform ports */ +#define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000 + +/* TZC related constants */ +#define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT_ALL +#define PLAT_ARM_TZC_BASE 0x2a4a0000 + +/* System timer related constants */ +#define PLAT_ARM_NSTIMER_FRAME_ID 1 + +#endif /* __CSS_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/soc/common/soc_css.h b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/soc/common/soc_css.h new file mode 100644 index 0000000..5f97cde --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/soc/common/soc_css.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SOC_CSS_H__ +#define __SOC_CSS_H__ + +/* + * Utility functions for ARM CSS SoCs + */ +void soc_css_init_nic400(void); +void soc_css_init_pcie(void); + +static inline void soc_css_security_setup(void) +{ + soc_css_init_nic400(); + soc_css_init_pcie(); +} + + +#endif /* __SOC_CSS_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/soc/common/soc_css_def.h b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/soc/common/soc_css_def.h new file mode 100644 index 0000000..428df4d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/arm/soc/common/soc_css_def.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SOC_CSS_DEF_H__ +#define __SOC_CSS_DEF_H__ + +#include +#include + + +/* + * Definitions common to all ARM CSS SoCs + */ + +/* Following covers ARM CSS SoC Peripherals and PCIe expansion area */ +#define SOC_CSS_DEVICE_BASE 0x40000000 +#define SOC_CSS_DEVICE_SIZE 0x40000000 +#define SOC_CSS_PCIE_CONTROL_BASE 0x7ff20000 + +/* PL011 UART related constants */ +#define SOC_CSS_UART0_BASE 0x7ff80000 +#define SOC_CSS_UART1_BASE 0x7ff70000 + +#define SOC_CSS_UART0_CLK_IN_HZ 7273800 +#define SOC_CSS_UART1_CLK_IN_HZ 7273800 + +/* SoC NIC-400 Global Programmers View (GPV) */ +#define SOC_CSS_NIC400_BASE 0x7fd00000 + +#define SOC_CSS_NIC400_USB_EHCI 0 +#define SOC_CSS_NIC400_TLX_MASTER 1 +#define SOC_CSS_NIC400_USB_OHCI 2 +#define SOC_CSS_NIC400_PL354_SMC 3 +/* + * The apb4_bridge controls access to: + * - the PCIe configuration registers + * - the MMU units for USB, HDLCD and DMA + */ +#define SOC_CSS_NIC400_APB4_BRIDGE 4 + +/* Keys */ +#define SOC_KEYS_BASE 0x7fe80000 +#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) +#define TZ_PUB_KEY_HASH_SIZE 32 +#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) +#define HU_KEY_SIZE 16 +#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) +#define END_KEY_SIZE 32 + +#define SOC_CSS_MAP_DEVICE MAP_REGION_FLAT( \ + SOC_CSS_DEVICE_BASE, \ + SOC_CSS_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + + +/* + * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. + */ +#define SOC_CSS_NIC400_BOOTSEC_BRIDGE 5 +#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12) + +/* + * Required platform porting definitions common to all ARM CSS SoCs + */ + +/* 2MB used for SCP DDR retraining */ +#define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x00200000) + + +#endif /* __SOC_CSS_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/plat/common/common_def.h b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/common/common_def.h new file mode 100644 index 0000000..077080d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/common/common_def.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __COMMON_DEF_H__ +#define __COMMON_DEF_H__ + +/****************************************************************************** + * Required platform porting definitions that are expected to be common to + * all platforms + *****************************************************************************/ + +/* + * Platform binary types for linking + */ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + + +/* + * Generic platform constants + */ +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" + +/* + * Some of the platform porting definitions use the 'ull' suffix in order to + * avoid subtle integer overflow errors due to implicit integer type promotion + * when working with 32-bit values. + * + * The TSP linker script includes some of these definitions to define the BL3-2 + * memory map, but the GNU LD does not support the 'ull' suffix, causing the + * build process to fail. To solve this problem, the auxiliary macro MAKE_ULL(x) + * will add the 'ull' suffix only when the macro __LINKER__ is not defined + * (__LINKER__ is defined in the command line to preprocess the linker script). + * Constants in the linker script will not have the 'ull' suffix, but this is + * not a problem since the linker evaluates all constant expressions to 64 bit + * (assuming the target architecture is 64 bit). + */ +#ifndef __LINKER__ + #define MAKE_ULL(x) x##ull +#else + #define MAKE_ULL(x) x +#endif + +/* + * Macros to wrap declarations of deprecated APIs within Trusted Firmware. + * The callers of these APIs will continue to compile as long as the build + * flag WARN_DEPRECATED is zero. Else the compiler will emit a warning + * when the callers of these APIs are compiled. + */ +#if WARN_DEPRECATED +#define __warn_deprecated __attribute__ ((deprecated)) +#else +#define __warn_deprecated +#endif + +#endif /* __COMMON_DEF_H__ */ + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/plat/common/platform.h b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/common/platform.h new file mode 100644 index 0000000..8071f39 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/plat/common/platform.h @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ + +#include +#include +#include + + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct meminfo; +struct image_info; +struct entry_point_info; +struct bl31_params; + +/******************************************************************************* + * plat_get_rotpk_info() flags + ******************************************************************************/ +#define ROTPK_IS_HASH (1 << 0) + +/******************************************************************************* + * Function declarations + ******************************************************************************/ +/******************************************************************************* + * Mandatory common functions + ******************************************************************************/ +uint64_t plat_get_syscnt_freq(void); +int plat_get_image_source(unsigned int image_id, + uintptr_t *dev_handle, + uintptr_t *image_spec); +unsigned long plat_get_ns_image_entrypoint(void); +unsigned int plat_my_core_pos(void); +int plat_core_pos_by_mpidr(u_register_t mpidr); + +/******************************************************************************* + * Mandatory interrupt management functions + ******************************************************************************/ +uint32_t plat_ic_get_pending_interrupt_id(void); +uint32_t plat_ic_get_pending_interrupt_type(void); +uint32_t plat_ic_acknowledge_interrupt(void); +uint32_t plat_ic_get_interrupt_type(uint32_t id); +void plat_ic_end_of_interrupt(uint32_t id); +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state); + +/******************************************************************************* + * Optional common functions (may be overridden) + ******************************************************************************/ +unsigned long plat_get_my_stack(void); +void plat_report_exception(unsigned long); +int plat_crash_console_init(void); +int plat_crash_console_putc(int c); + +/******************************************************************************* + * Mandatory BL1 functions + ******************************************************************************/ +void bl1_early_platform_setup(void); +void bl1_plat_arch_setup(void); +void bl1_platform_setup(void); +struct meminfo *bl1_plat_sec_mem_layout(void); + +/* + * This function allows the platform to change the entrypoint information for + * BL2, after BL1 has loaded BL2 into memory but before BL2 is executed. + */ +void bl1_plat_set_bl2_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/******************************************************************************* + * Optional BL1 functions (may be overridden) + ******************************************************************************/ +void bl1_init_bl2_mem_layout(const struct meminfo *bl1_mem_layout, + struct meminfo *bl2_mem_layout); + +/******************************************************************************* + * Mandatory BL2 functions + ******************************************************************************/ +void bl2_early_platform_setup(struct meminfo *mem_layout); +void bl2_plat_arch_setup(void); +void bl2_platform_setup(void); +struct meminfo *bl2_plat_sec_mem_layout(void); + +/* + * This function returns a pointer to the shared memory that the platform has + * kept aside to pass trusted firmware related information that BL3-1 + * could need + */ +struct bl31_params *bl2_plat_get_bl31_params(void); + +/* + * This function returns a pointer to the shared memory that the platform + * has kept to point to entry point information of BL31 to BL2 + */ +struct entry_point_info *bl2_plat_get_bl31_ep_info(void); + +/* + * This function flushes to main memory all the params that are + * passed to BL3-1 + */ +void bl2_plat_flush_bl31_params(void); + +/* + * The next 2 functions allow the platform to change the entrypoint information + * for the mandatory 3rd level BL images, BL3-1 and BL3-3. This is done after + * BL2 has loaded those images into memory but before BL3-1 is executed. + */ +void bl2_plat_set_bl31_ep_info(struct image_info *image, + struct entry_point_info *ep); + +void bl2_plat_set_bl33_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* Gets the memory layout for BL3-3 */ +void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); + +/******************************************************************************* + * Conditionally mandatory BL2 functions: must be implemented if BL3-0 image + * is supported + ******************************************************************************/ +/* Gets the memory layout for BL3-0 */ +void bl2_plat_get_bl30_meminfo(struct meminfo *mem_info); + +/* + * This function is called after loading BL3-0 image and it is used to perform + * any platform-specific actions required to handle the SCP firmware. + */ +int bl2_plat_handle_bl30(struct image_info *bl30_image_info); + +/******************************************************************************* + * Conditionally mandatory BL2 functions: must be implemented if BL3-2 image + * is supported + ******************************************************************************/ +void bl2_plat_set_bl32_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* Gets the memory layout for BL3-2 */ +void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); + +/******************************************************************************* + * Optional BL2 functions (may be overridden) + ******************************************************************************/ + +/******************************************************************************* + * Mandatory BL3-1 functions + ******************************************************************************/ +void bl31_early_platform_setup(struct bl31_params *from_bl2, + void *plat_params_from_bl2); +void bl31_plat_arch_setup(void); +void bl31_platform_setup(void); +struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type); + +/******************************************************************************* + * Mandatory PSCI functions (BL3-1) + ******************************************************************************/ +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const struct plat_psci_ops **); +const unsigned char *plat_get_power_domain_tree_desc(void); + +/******************************************************************************* + * Optional PSCI functions (BL3-1). + ******************************************************************************/ +plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, + const plat_local_state_t *states, + unsigned int ncpu); + +/******************************************************************************* + * Optional BL3-1 functions (may be overridden) + ******************************************************************************/ +void bl31_plat_enable_mmu(uint32_t flags); + +/******************************************************************************* + * Optional BL3-2 functions (may be overridden) + ******************************************************************************/ +void bl32_plat_enable_mmu(uint32_t flags); + +/******************************************************************************* + * Trusted Board Boot functions + ******************************************************************************/ +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags); + +#if ENABLE_PLAT_COMPAT +/* + * The below declarations are to enable compatibility for the platform ports + * using the old platform interface. + */ + +/******************************************************************************* + * Optional common functions (may be overridden) + ******************************************************************************/ +unsigned int platform_get_core_pos(unsigned long mpidr); + +/******************************************************************************* + * Mandatory PSCI Compatibility functions (BL3-1) + ******************************************************************************/ +int platform_setup_pm(const plat_pm_ops_t **); + +unsigned int plat_get_aff_count(unsigned int, unsigned long); +unsigned int plat_get_aff_state(unsigned int, unsigned long); +#else +/* + * The below function enable Trusted Firmware components like SPDs which + * haven't migrated to the new platform API to compile on platforms which + * have the compatibility layer disabled. + */ +unsigned int platform_get_core_pos(unsigned long mpidr) __warn_deprecated; + +#endif /* __ENABLE_PLAT_COMPAT__ */ +#endif /* __PLATFORM_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/assert.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/assert.h new file mode 100644 index 0000000..5621f8c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/assert.h @@ -0,0 +1,63 @@ +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)assert.h 8.2 (Berkeley) 1/21/94 + * $FreeBSD$ + */ + +#include + +/* + * Unlike other ANSI header files, may usefully be included + * multiple times, with and without NDEBUG defined. + */ + +#undef assert +#undef _assert + +#ifdef NDEBUG +#define assert(e) ((void)0) +#define _assert(e) ((void)0) +#else +#define _assert(e) assert(e) + +#define assert(e) ((e) ? (void)0 : __assert(__func__, __FILE__, \ + __LINE__, #e)) +#endif /* NDEBUG */ + +#ifndef _ASSERT_H_ +#define _ASSERT_H_ +__BEGIN_DECLS +void __assert(const char *, const char *, int, const char *) __dead2; +__END_DECLS +#endif /* !_ASSERT_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/inttypes.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/inttypes.h new file mode 100644 index 0000000..269f3e7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/inttypes.h @@ -0,0 +1,52 @@ +/*- + * Copyright (c) 2001 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _INTTYPES_H_ +#define _INTTYPES_H_ + +#include +#include + +typedef struct { + intmax_t quot; /* Quotient. */ + intmax_t rem; /* Remainder. */ +} imaxdiv_t; + +__BEGIN_DECLS +#ifdef _XLOCALE_H_ +#include +#endif +intmax_t imaxabs(intmax_t) __pure2; +imaxdiv_t imaxdiv(intmax_t, intmax_t) __pure2; + +intmax_t strtoimax(const char *__restrict, char **__restrict, int); +uintmax_t strtoumax(const char *__restrict, char **__restrict, int); + +__END_DECLS + +#endif /* !_INTTYPES_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/machine/_inttypes.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/machine/_inttypes.h new file mode 100644 index 0000000..8dd07d6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/machine/_inttypes.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_INTTYPES_H_ +#define _MACHINE_INTTYPES_H_ + +/* + * Trusted Firmware does not depend on any definitions in this file. Content + * will be added as needed. + */ + +#endif /* !_MACHINE_INTTYPES_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/machine/_limits.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/machine/_limits.h new file mode 100644 index 0000000..49a768b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/machine/_limits.h @@ -0,0 +1,85 @@ +/*- + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)limits.h 8.3 (Berkeley) 1/4/94 + * $FreeBSD$ + */ + +#ifndef _MACHINE__LIMITS_H_ +#define _MACHINE__LIMITS_H_ + +/* + * According to ANSI (section 2.2.4.2), the values below must be usable by + * #if preprocessing directives. Additionally, the expression must have the + * same type as would an expression that is an object of the corresponding + * type converted according to the integral promotions. The subtraction for + * INT_MIN, etc., is so the value is not unsigned; e.g., 0x80000000 is an + * unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2). + */ + +#define __CHAR_BIT 8 /* number of bits in a char */ + +#define __SCHAR_MAX 0x7f /* max value for a signed char */ +#define __SCHAR_MIN (-0x7f-1) /* min value for a signed char */ + +#define __UCHAR_MAX 0xff /* max value for an unsigned char */ + +#define __USHRT_MAX 0xffff /* max value for an unsigned short */ +#define __SHRT_MAX 0x7fff /* max value for a short */ +#define __SHRT_MIN (-0x7fff-1) /* min value for a short */ + +#define __UINT_MAX 0xffffffff /* max value for an unsigned int */ +#define __INT_MAX 0x7fffffff /* max value for an int */ +#define __INT_MIN (-0x7fffffff-1) /* min value for an int */ + +#define __ULONG_MAX 0xffffffffffffffff /* max for an unsigned long */ +#define __LONG_MAX 0x7fffffffffffffff /* max for a long */ +#define __LONG_MIN (-0x7fffffffffffffff-1) /* min for a long */ + +/* Long longs have the same size but not the same type as longs. */ + /* max for an unsigned long long */ +#define __ULLONG_MAX 0xffffffffffffffffULL +#define __LLONG_MAX 0x7fffffffffffffffLL /* max for a long long */ +#define __LLONG_MIN (-0x7fffffffffffffffLL-1) /* min for a long long */ + +#define __SSIZE_MAX __LONG_MAX /* max value for a ssize_t */ + +#define __SIZE_T_MAX __ULONG_MAX /* max value for a size_t */ + +#define __OFF_MAX __LONG_MAX /* max value for an off_t */ +#define __OFF_MIN __LONG_MIN /* min value for an off_t */ + +/* Quads and longs are the same size. Ensure they stay in sync. */ +#define __UQUAD_MAX (__ULONG_MAX) /* max value for a uquad_t */ +#define __QUAD_MAX (__LONG_MAX) /* max value for a quad_t */ +#define __QUAD_MIN (__LONG_MIN) /* min value for a quad_t */ + +#define __LONG_BIT 64 +#define __WORD_BIT 32 + +/* Minimum signal stack size. */ +#define __MINSIGSTKSZ (1024 * 4) + +#endif /* !_MACHINE__LIMITS_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/machine/_stdint.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/machine/_stdint.h new file mode 100644 index 0000000..e36c659 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/machine/_stdint.h @@ -0,0 +1,164 @@ +/*- + * Copyright (c) 2001, 2002 Mike Barcroft + * Copyright (c) 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Klaus Klein. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE__STDINT_H_ +#define _MACHINE__STDINT_H_ + +#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) + +#define INT8_C(c) (c) +#define INT16_C(c) (c) +#define INT32_C(c) (c) +#define INT64_C(c) (c ## L) + +#define UINT8_C(c) (c) +#define UINT16_C(c) (c) +#define UINT32_C(c) (c ## U) +#define UINT64_C(c) (c ## UL) + +#define INTMAX_C(c) INT64_C(c) +#define UINTMAX_C(c) UINT64_C(c) + +#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */ + +#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) + +/* + * ISO/IEC 9899:1999 + * 7.18.2.1 Limits of exact-width integer types + */ +/* Minimum values of exact-width signed integer types. */ +#define INT8_MIN (-0x7f-1) +#define INT16_MIN (-0x7fff-1) +#define INT32_MIN (-0x7fffffff-1) +#define INT64_MIN (-0x7fffffffffffffffL-1) + +/* Maximum values of exact-width signed integer types. */ +#define INT8_MAX 0x7f +#define INT16_MAX 0x7fff +#define INT32_MAX 0x7fffffff +#define INT64_MAX 0x7fffffffffffffffL + +/* Maximum values of exact-width unsigned integer types. */ +#define UINT8_MAX 0xff +#define UINT16_MAX 0xffff +#define UINT32_MAX 0xffffffffU +#define UINT64_MAX 0xffffffffffffffffUL + +/* + * ISO/IEC 9899:1999 + * 7.18.2.2 Limits of minimum-width integer types + */ +/* Minimum values of minimum-width signed integer types. */ +#define INT_LEAST8_MIN INT8_MIN +#define INT_LEAST16_MIN INT16_MIN +#define INT_LEAST32_MIN INT32_MIN +#define INT_LEAST64_MIN INT64_MIN + +/* Maximum values of minimum-width signed integer types. */ +#define INT_LEAST8_MAX INT8_MAX +#define INT_LEAST16_MAX INT16_MAX +#define INT_LEAST32_MAX INT32_MAX +#define INT_LEAST64_MAX INT64_MAX + +/* Maximum values of minimum-width unsigned integer types. */ +#define UINT_LEAST8_MAX UINT8_MAX +#define UINT_LEAST16_MAX UINT16_MAX +#define UINT_LEAST32_MAX UINT32_MAX +#define UINT_LEAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.3 Limits of fastest minimum-width integer types + */ +/* Minimum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MIN INT32_MIN +#define INT_FAST16_MIN INT32_MIN +#define INT_FAST32_MIN INT32_MIN +#define INT_FAST64_MIN INT64_MIN + +/* Maximum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MAX INT32_MAX +#define INT_FAST16_MAX INT32_MAX +#define INT_FAST32_MAX INT32_MAX +#define INT_FAST64_MAX INT64_MAX + +/* Maximum values of fastest minimum-width unsigned integer types. */ +#define UINT_FAST8_MAX UINT32_MAX +#define UINT_FAST16_MAX UINT32_MAX +#define UINT_FAST32_MAX UINT32_MAX +#define UINT_FAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.4 Limits of integer types capable of holding object pointers + */ +#define INTPTR_MIN INT64_MIN +#define INTPTR_MAX INT64_MAX +#define UINTPTR_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.5 Limits of greatest-width integer types + */ +#define INTMAX_MIN INT64_MIN +#define INTMAX_MAX INT64_MAX +#define UINTMAX_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.3 Limits of other integer types + */ +/* Limits of ptrdiff_t. */ +#define PTRDIFF_MIN INT64_MIN +#define PTRDIFF_MAX INT64_MAX + +/* Limits of sig_atomic_t. */ +#define SIG_ATOMIC_MIN INT32_MIN +#define SIG_ATOMIC_MAX INT32_MAX + +/* Limit of size_t. */ +#define SIZE_MAX UINT64_MAX + +#ifndef WCHAR_MIN /* Also possibly defined in */ +/* Limits of wchar_t. */ +#define WCHAR_MIN INT32_MIN +#define WCHAR_MAX INT32_MAX +#endif + +/* Limits of wint_t. */ +#define WINT_MIN INT32_MIN +#define WINT_MAX INT32_MAX + +#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ + +#endif /* !_MACHINE__STDINT_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/machine/_types.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/machine/_types.h new file mode 100644 index 0000000..7e993c4 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/machine/_types.h @@ -0,0 +1,110 @@ +/*- + * Copyright (c) 2002 Mike Barcroft + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * From: @(#)ansi.h 8.2 (Berkeley) 1/4/94 + * From: @(#)types.h 8.3 (Berkeley) 1/5/94 + * $FreeBSD$ + */ + +#ifndef _MACHINE__TYPES_H_ +#define _MACHINE__TYPES_H_ + +#ifndef _SYS_CDEFS_H_ +#error this file needs sys/cdefs.h as a prerequisite +#endif + +/* + * Basic types upon which most other types are built. + */ +typedef __signed char __int8_t; +typedef unsigned char __uint8_t; +typedef short __int16_t; +typedef unsigned short __uint16_t; +typedef int __int32_t; +typedef unsigned int __uint32_t; +typedef long __int64_t; +typedef unsigned long __uint64_t; + +/* + * Standard type definitions. + */ +typedef __int32_t __clock_t; /* clock()... */ +typedef __int64_t __critical_t; +typedef double __double_t; +typedef float __float_t; +typedef __int64_t __intfptr_t; +typedef __int64_t __intmax_t; +typedef __int64_t __intptr_t; +typedef __int32_t __int_fast8_t; +typedef __int32_t __int_fast16_t; +typedef __int32_t __int_fast32_t; +typedef __int64_t __int_fast64_t; +typedef __int8_t __int_least8_t; +typedef __int16_t __int_least16_t; +typedef __int32_t __int_least32_t; +typedef __int64_t __int_least64_t; +typedef __int64_t __ptrdiff_t; /* ptr1 - ptr2 */ +typedef __int64_t __register_t; +typedef __int64_t __segsz_t; /* segment size (in pages) */ +typedef __uint64_t __size_t; /* sizeof() */ +typedef __int64_t __ssize_t; /* byte count or error */ +typedef __int64_t __time_t; /* time()... */ +typedef __uint64_t __uintfptr_t; +typedef __uint64_t __uintmax_t; +typedef __uint64_t __uintptr_t; +typedef __uint32_t __uint_fast8_t; +typedef __uint32_t __uint_fast16_t; +typedef __uint32_t __uint_fast32_t; +typedef __uint64_t __uint_fast64_t; +typedef __uint8_t __uint_least8_t; +typedef __uint16_t __uint_least16_t; +typedef __uint32_t __uint_least32_t; +typedef __uint64_t __uint_least64_t; +typedef __uint64_t __u_register_t; +typedef __uint64_t __vm_offset_t; +typedef __int64_t __vm_ooffset_t; +typedef __uint64_t __vm_paddr_t; +typedef __uint64_t __vm_pindex_t; +typedef __uint64_t __vm_size_t; + +/* + * Unusual type definitions. + */ +#ifdef __GNUCLIKE_BUILTIN_VARARGS +typedef __builtin_va_list __va_list; /* internally known to gcc */ +#else +typedef char * __va_list; +#endif /* __GNUCLIKE_BUILTIN_VARARGS */ +#if defined(__GNUCLIKE_BUILTIN_VAALIST) && !defined(__GNUC_VA_LIST) \ + && !defined(__NO_GNUC_VA_LIST) +#define __GNUC_VA_LIST +typedef __va_list __gnuc_va_list; /* compatibility w/GNU headers*/ +#endif + +#endif /* !_MACHINE__TYPES_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/stddef.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/stddef.h new file mode 100644 index 0000000..ea88214 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/stddef.h @@ -0,0 +1,64 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stddef.h 8.1 (Berkeley) 6/2/93 + * + * $FreeBSD$ + */ + +#ifndef _STDDEF_H_ +#define _STDDEF_H_ + +#include +#include +#include + +typedef __ptrdiff_t ptrdiff_t; + +#if __BSD_VISIBLE +#ifndef _RUNE_T_DECLARED +typedef __rune_t rune_t; +#define _RUNE_T_DECLARED +#endif +#endif + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#ifndef __cplusplus +#ifndef _WCHAR_T_DECLARED +typedef __wchar_t wchar_t; +#define _WCHAR_T_DECLARED +#endif +#endif + +#define offsetof(type, member) __offsetof(type, member) + +#endif /* _STDDEF_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/stdio.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/stdio.h new file mode 100644 index 0000000..57e5c7f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/stdio.h @@ -0,0 +1,78 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stdio.h 8.5 (Berkeley) 4/29/95 + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2013-2014, ARM Limited and Contributors. + * All rights reserved. + */ + + +#ifndef _STDIO_H_ +#define _STDIO_H_ + +#include +#include +#include + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#ifndef _SSIZE_T_DECLARED +#define _SSIZE_T_DECLARED +typedef __ssize_t ssize_t; +#endif + +#define EOF (-1) + +int printf(const char * __restrict, ...) __printflike(1, 2); +int putchar(int); +int puts(const char *); +int sprintf(char * __restrict, const char * __restrict, ...) + __printflike(2, 3); +int vsprintf(char * __restrict, const char * __restrict, + __va_list) __printflike(2, 0); + +int sscanf(const char *__restrict, char const *__restrict, ...); + +#if __ISO_C_VISIBLE >= 1999 +int snprintf(char * __restrict, size_t, const char * __restrict, + ...) __printflike(3, 4); +int vsnprintf(char * __restrict, size_t, const char * __restrict, + __va_list) __printflike(3, 0); +#endif + +#endif /* !_STDIO_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/stdlib.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/stdlib.h new file mode 100644 index 0000000..b1ac1bf --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/stdlib.h @@ -0,0 +1,313 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stdlib.h 8.5 (Berkeley) 5/19/95 + * $FreeBSD$ + */ + +#ifndef _STDLIB_H_ +#define _STDLIB_H_ + +#include +#include +#include + +#if __BSD_VISIBLE +#ifndef _RUNE_T_DECLARED +typedef __rune_t rune_t; +#define _RUNE_T_DECLARED +#endif +#endif + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +typedef struct { + int quot; /* quotient */ + int rem; /* remainder */ +} div_t; + +typedef struct { + long quot; + long rem; +} ldiv_t; + +#define EXIT_FAILURE 1 +#define EXIT_SUCCESS 0 + +#define RAND_MAX 0x7ffffffd + +__BEGIN_DECLS +#ifdef _XLOCALE_H_ +#include +#endif +extern int __mb_cur_max; +extern int ___mb_cur_max(void); +#define MB_CUR_MAX (___mb_cur_max()) + +_Noreturn void abort(void); +int abs(int) __pure2; +int atexit(void (*)(void)); +double atof(const char *); +int atoi(const char *); +long atol(const char *); +void *bsearch(const void *, const void *, size_t, + size_t, int (*)(const void *, const void *)); +void *calloc(size_t, size_t) __malloc_like; +div_t div(int, int) __pure2; +_Noreturn void exit(int); +void free(void *); +char *getenv(const char *); +long labs(long) __pure2; +ldiv_t ldiv(long, long) __pure2; +void *malloc(size_t) __malloc_like; +int mblen(const char *, size_t); +void qsort(void *, size_t, size_t, + int (*)(const void *, const void *)); +int rand(void); +void *realloc(void *, size_t); +void srand(unsigned); +double strtod(const char *__restrict, char **__restrict); +float strtof(const char *__restrict, char **__restrict); +long strtol(const char *__restrict, char **__restrict, int); +long double + strtold(const char *__restrict, char **__restrict); +unsigned long + strtoul(const char *__restrict, char **__restrict, int); +int system(const char *); + +/* + * Functions added in C99 which we make conditionally available in the + * BSD^C89 namespace if the compiler supports `long long'. + * The #if test is more complicated than it ought to be because + * __BSD_VISIBLE implies __ISO_C_VISIBLE == 1999 *even if* `long long' + * is not supported in the compilation environment (which therefore means + * that it can't really be ISO C99). + * + * (The only other extension made by C99 in thie header is _Exit().) + */ +#if __ISO_C_VISIBLE >= 1999 +#ifdef __LONG_LONG_SUPPORTED +/* LONGLONG */ +typedef struct { + long long quot; + long long rem; +} lldiv_t; + +/* LONGLONG */ +long long + atoll(const char *); +/* LONGLONG */ +long long + llabs(long long) __pure2; +/* LONGLONG */ +lldiv_t lldiv(long long, long long) __pure2; +/* LONGLONG */ +long long + strtoll(const char *__restrict, char **__restrict, int); +/* LONGLONG */ +unsigned long long + strtoull(const char *__restrict, char **__restrict, int); +#endif /* __LONG_LONG_SUPPORTED */ + +_Noreturn void _Exit(int); +#endif /* __ISO_C_VISIBLE >= 1999 */ + +/* + * If we're in a mode greater than C99, expose C11 functions. + */ +#if __ISO_C_VISIBLE >= 2011 || __cplusplus >= 201103L +void *aligned_alloc(size_t, size_t) __malloc_like; +int at_quick_exit(void (*)(void)); +_Noreturn void + quick_exit(int); +#endif /* __ISO_C_VISIBLE >= 2011 */ +/* + * Extensions made by POSIX relative to C. + */ +#if __POSIX_VISIBLE >= 199506 || __XSI_VISIBLE +char *realpath(const char *__restrict, char *__restrict); +#endif +#if __POSIX_VISIBLE >= 199506 +int rand_r(unsigned *); /* (TSF) */ +#endif +#if __POSIX_VISIBLE >= 200112 +int posix_memalign(void **, size_t, size_t); /* (ADV) */ +int setenv(const char *, const char *, int); +int unsetenv(const char *); +#endif + +#if __POSIX_VISIBLE >= 200809 || __XSI_VISIBLE +int getsubopt(char **, char *const *, char **); +#ifndef _MKDTEMP_DECLARED +char *mkdtemp(char *); +#define _MKDTEMP_DECLARED +#endif +#ifndef _MKSTEMP_DECLARED +int mkstemp(char *); +#define _MKSTEMP_DECLARED +#endif +#endif /* __POSIX_VISIBLE >= 200809 || __XSI_VISIBLE */ + +/* + * The only changes to the XSI namespace in revision 6 were the deletion + * of the ttyslot() and valloc() functions, which FreeBSD never declared + * in this header. For revision 7, ecvt(), fcvt(), and gcvt(), which + * FreeBSD also does not have, and mktemp(), are to be deleted. + */ +#if __XSI_VISIBLE +/* XXX XSI requires pollution from here. We'd rather not. */ +long a64l(const char *); +double drand48(void); +/* char *ecvt(double, int, int * __restrict, int * __restrict); */ +double erand48(unsigned short[3]); +/* char *fcvt(double, int, int * __restrict, int * __restrict); */ +/* char *gcvt(double, int, int * __restrict, int * __restrict); */ +int grantpt(int); +char *initstate(unsigned long /* XSI requires u_int */, char *, long); +long jrand48(unsigned short[3]); +char *l64a(long); +void lcong48(unsigned short[7]); +long lrand48(void); +#if !defined(_MKTEMP_DECLARED) && (__BSD_VISIBLE || __XSI_VISIBLE <= 600) +char *mktemp(char *); +#define _MKTEMP_DECLARED +#endif +long mrand48(void); +long nrand48(unsigned short[3]); +int posix_openpt(int); +char *ptsname(int); +int putenv(char *); +long random(void); +unsigned short + *seed48(unsigned short[3]); +#ifndef _SETKEY_DECLARED +int setkey(const char *); +#define _SETKEY_DECLARED +#endif +char *setstate(/* const */ char *); +void srand48(long); +void srandom(unsigned long); +int unlockpt(int); +#endif /* __XSI_VISIBLE */ + +#if __BSD_VISIBLE +extern const char *malloc_conf; +extern void (*malloc_message)(void *, const char *); + +/* + * The alloca() function can't be implemented in C, and on some + * platforms it can't be implemented at all as a callable function. + * The GNU C compiler provides a built-in alloca() which we can use; + * in all other cases, provide a prototype, mainly to pacify various + * incarnations of lint. On platforms where alloca() is not in libc, + * programs which use it will fail to link when compiled with non-GNU + * compilers. + */ +#if __GNUC__ >= 2 || defined(__INTEL_COMPILER) +#undef alloca /* some GNU bits try to get cute and define this on their own */ +#define alloca(sz) __builtin_alloca(sz) +#elif defined(lint) +void *alloca(size_t); +#endif + +void abort2(const char *, int, void **) __dead2; +__uint32_t + arc4random(void); +void arc4random_addrandom(unsigned char *, int); +void arc4random_buf(void *, size_t); +void arc4random_stir(void); +__uint32_t + arc4random_uniform(__uint32_t); +#ifdef __BLOCKS__ +int atexit_b(void (^)(void)); +void *bsearch_b(const void *, const void *, size_t, + size_t, int (^)(const void *, const void *)); +#endif +char *getbsize(int *, long *); + /* getcap(3) functions */ +char *cgetcap(char *, const char *, int); +int cgetclose(void); +int cgetent(char **, char **, const char *); +int cgetfirst(char **, char **); +int cgetmatch(const char *, const char *); +int cgetnext(char **, char **); +int cgetnum(char *, const char *, long *); +int cgetset(const char *); +int cgetstr(char *, const char *, char **); +int cgetustr(char *, const char *, char **); + +int daemon(int, int); +char *devname(__dev_t, __mode_t); +char *devname_r(__dev_t, __mode_t, char *, int); +char *fdevname(int); +char *fdevname_r(int, char *, int); +int getloadavg(double [], int); +const char * + getprogname(void); + +int heapsort(void *, size_t, size_t, int (*)(const void *, const void *)); +#ifdef __BLOCKS__ +int heapsort_b(void *, size_t, size_t, int (^)(const void *, const void *)); +void qsort_b(void *, size_t, size_t, + int (^)(const void *, const void *)); +#endif +int l64a_r(long, char *, int); +int mergesort(void *, size_t, size_t, int (*)(const void *, const void *)); +#ifdef __BLOCKS__ +int mergesort_b(void *, size_t, size_t, int (^)(const void *, const void *)); +#endif +int mkostemp(char *, int); +int mkostemps(char *, int, int); +void qsort_r(void *, size_t, size_t, void *, + int (*)(void *, const void *, const void *)); +int radixsort(const unsigned char **, int, const unsigned char *, + unsigned); +void *reallocf(void *, size_t); +int rpmatch(const char *); +void setprogname(const char *); +int sradixsort(const unsigned char **, int, const unsigned char *, + unsigned); +void sranddev(void); +void srandomdev(void); +long long + strtonum(const char *, long long, long long, const char **); + +/* Deprecated interfaces, to be removed in FreeBSD 6.0. */ +__int64_t + strtoq(const char *, char **, int); +__uint64_t + strtouq(const char *, char **, int); + +extern char *suboptarg; /* getsubopt(3) external variable */ +#endif /* __BSD_VISIBLE */ +__END_DECLS + +#endif /* !_STDLIB_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/string.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/string.h new file mode 100644 index 0000000..61e8102 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/string.h @@ -0,0 +1,66 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)string.h 8.1 (Berkeley) 6/2/93 + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2013-2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include +#include +#include + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +__BEGIN_DECLS + +void *memchr(const void *, int, size_t) __pure; +int memcmp(const void *, const void *, size_t) __pure; +void *memcpy(void * __restrict, const void * __restrict, size_t); +void *memmove(void *, const void *, size_t); +void *memset(void *, int, size_t); + +char *strchr(const char *, int) __pure; +int strcmp(const char *, const char *) __pure; +size_t strlen(const char *) __pure; +int strncmp(const char *, const char *, size_t) __pure; +int strcasecmp(const char *, const char *); + +__END_DECLS + +#endif /* _STRING_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/strings.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/strings.h new file mode 100644 index 0000000..2210df0 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/strings.h @@ -0,0 +1,71 @@ +/*- + * Copyright (c) 2002 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _STRINGS_H_ +#define _STRINGS_H_ + +#include +#include + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +__BEGIN_DECLS +#if __BSD_VISIBLE || __POSIX_VISIBLE <= 200112 +int bcmp(const void *, const void *, size_t) __pure; /* LEGACY */ +void bcopy(const void *, void *, size_t); /* LEGACY */ +void bzero(void *, size_t); /* LEGACY */ +#endif +#if __BSD_VISIBLE +void explicit_bzero(void *, size_t); +#endif +#if __XSI_VISIBLE +int ffs(int) __pure2; +#endif +#if __BSD_VISIBLE +int ffsl(long) __pure2; +int ffsll(long long) __pure2; +int fls(int) __pure2; +int flsl(long) __pure2; +int flsll(long long) __pure2; +#endif +#if __BSD_VISIBLE || __POSIX_VISIBLE <= 200112 +char *index(const char *, int) __pure; /* LEGACY */ +char *rindex(const char *, int) __pure; /* LEGACY */ +#endif +int strcasecmp(const char *, const char *) __pure; +int strncasecmp(const char *, const char *, size_t) __pure; + +#if __POSIX_VISIBLE >= 200809 || defined(_XLOCALE_H_) +#include +#endif +__END_DECLS + +#endif /* _STRINGS_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/_null.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/_null.h new file mode 100644 index 0000000..92706c6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/_null.h @@ -0,0 +1,47 @@ +/*- + * Copyright (c) 2003 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef NULL + +#if !defined(__cplusplus) +#define NULL ((void *)0) +#else +#if __cplusplus >= 201103L +#define NULL nullptr +#elif defined(__GNUG__) && defined(__GNUC__) && __GNUC__ >= 4 +#define NULL __null +#else +#if defined(__LP64__) +#define NULL (0L) +#else +#define NULL 0 +#endif /* __LP64__ */ +#endif /* __GNUG__ */ +#endif /* !__cplusplus */ + +#endif diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/_stdint.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/_stdint.h new file mode 100644 index 0000000..d0f9249 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/_stdint.h @@ -0,0 +1,82 @@ +/*- + * Copyright (c) 2011 David E. O'Brien + * Copyright (c) 2001 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS__STDINT_H_ +#define _SYS__STDINT_H_ + +#ifndef _INT8_T_DECLARED +typedef __int8_t int8_t; +#define _INT8_T_DECLARED +#endif + +#ifndef _INT16_T_DECLARED +typedef __int16_t int16_t; +#define _INT16_T_DECLARED +#endif + +#ifndef _INT32_T_DECLARED +typedef __int32_t int32_t; +#define _INT32_T_DECLARED +#endif + +#ifndef _INT64_T_DECLARED +typedef __int64_t int64_t; +#define _INT64_T_DECLARED +#endif + +#ifndef _UINT8_T_DECLARED +typedef __uint8_t uint8_t; +#define _UINT8_T_DECLARED +#endif + +#ifndef _UINT16_T_DECLARED +typedef __uint16_t uint16_t; +#define _UINT16_T_DECLARED +#endif + +#ifndef _UINT32_T_DECLARED +typedef __uint32_t uint32_t; +#define _UINT32_T_DECLARED +#endif + +#ifndef _UINT64_T_DECLARED +typedef __uint64_t uint64_t; +#define _UINT64_T_DECLARED +#endif + +#ifndef _INTPTR_T_DECLARED +typedef __intptr_t intptr_t; +#define _INTPTR_T_DECLARED +#endif +#ifndef _UINTPTR_T_DECLARED +typedef __uintptr_t uintptr_t; +#define _UINTPTR_T_DECLARED +#endif + +#endif /* !_SYS__STDINT_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/_timespec.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/_timespec.h new file mode 100644 index 0000000..d51559c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/_timespec.h @@ -0,0 +1,49 @@ +/*- + * Copyright (c) 1982, 1986, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)time.h 8.5 (Berkeley) 5/4/95 + * from: FreeBSD: src/sys/sys/time.h,v 1.43 2000/03/20 14:09:05 phk Exp + * $FreeBSD$ + */ + +#ifndef _SYS__TIMESPEC_H_ +#define _SYS__TIMESPEC_H_ + +#include + +#ifndef _TIME_T_DECLARED +typedef __time_t time_t; +#define _TIME_T_DECLARED +#endif + +struct timespec { + time_t tv_sec; /* seconds */ + long tv_nsec; /* and nanoseconds */ +}; + +#endif /* !_SYS__TIMESPEC_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/_types.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/_types.h new file mode 100644 index 0000000..c59afd3 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/_types.h @@ -0,0 +1,106 @@ +/*- + * Copyright (c) 2002 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS__TYPES_H_ +#define _SYS__TYPES_H_ + +#include +#include + +/* + * Standard type definitions. + */ +typedef __uint32_t __blksize_t; /* file block size */ +typedef __int64_t __blkcnt_t; /* file block count */ +typedef __int32_t __clockid_t; /* clock_gettime()... */ +typedef __uint64_t __cap_rights_t; /* capability rights */ +typedef __uint32_t __fflags_t; /* file flags */ +typedef __uint64_t __fsblkcnt_t; +typedef __uint64_t __fsfilcnt_t; +typedef __uint32_t __gid_t; +typedef __int64_t __id_t; /* can hold a gid_t, pid_t, or uid_t */ +typedef __uint32_t __ino_t; /* inode number */ +typedef long __key_t; /* IPC key (for Sys V IPC) */ +typedef __int32_t __lwpid_t; /* Thread ID (a.k.a. LWP) */ +typedef __uint16_t __mode_t; /* permissions */ +typedef int __accmode_t; /* access permissions */ +typedef int __nl_item; +typedef __uint16_t __nlink_t; /* link count */ +typedef __int64_t __off_t; /* file offset */ +typedef __int32_t __pid_t; /* process [group] */ +typedef __int64_t __rlim_t; /* resource limit - intentionally */ + /* signed, because of legacy code */ + /* that uses -1 for RLIM_INFINITY */ +typedef __uint8_t __sa_family_t; +typedef __uint32_t __socklen_t; +typedef long __suseconds_t; /* microseconds (signed) */ +typedef struct __timer *__timer_t; /* timer_gettime()... */ +typedef struct __mq *__mqd_t; /* mq_open()... */ +typedef __uint32_t __uid_t; +typedef unsigned int __useconds_t; /* microseconds (unsigned) */ +typedef int __cpuwhich_t; /* which parameter for cpuset. */ +typedef int __cpulevel_t; /* level parameter for cpuset. */ +typedef int __cpusetid_t; /* cpuset identifier. */ + +/* + * Unusual type definitions. + */ +/* + * rune_t is declared to be an ``int'' instead of the more natural + * ``unsigned long'' or ``long''. Two things are happening here. It is not + * unsigned so that EOF (-1) can be naturally assigned to it and used. Also, + * it looks like 10646 will be a 31 bit standard. This means that if your + * ints cannot hold 32 bits, you will be in trouble. The reason an int was + * chosen over a long is that the is*() and to*() routines take ints (says + * ANSI C), but they use __ct_rune_t instead of int. + * + * NOTE: rune_t is not covered by ANSI nor other standards, and should not + * be instantiated outside of lib/libc/locale. Use wchar_t. wchar_t and + * rune_t must be the same type. Also, wint_t must be no narrower than + * wchar_t, and should be able to hold all members of the largest + * character set plus one extra value (WEOF), and must be at least 16 bits. + */ +typedef int __ct_rune_t; /* arg type for ctype funcs */ +typedef __ct_rune_t __rune_t; /* rune_t (see above) */ +typedef __ct_rune_t __wchar_t; /* wchar_t (see above) */ +typedef __ct_rune_t __wint_t; /* wint_t (see above) */ + +typedef __uint32_t __dev_t; /* device number */ + +typedef __uint32_t __fixpt_t; /* fixed point number */ + +/* + * mbstate_t is an opaque object to keep conversion state during multibyte + * stream conversions. + */ +typedef union { + char __mbstate8[128]; + __int64_t _mbstateL; /* for alignment */ +} __mbstate_t; + +#endif /* !_SYS__TYPES_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/cdefs.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/cdefs.h new file mode 100644 index 0000000..16fb151 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/cdefs.h @@ -0,0 +1,686 @@ +/*- + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Berkeley Software Design, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)cdefs.h 8.8 (Berkeley) 1/9/95 + * $FreeBSD$ + */ + +#ifndef _SYS_CDEFS_H_ +#define _SYS_CDEFS_H_ + +#if defined(__cplusplus) +#define __BEGIN_DECLS extern "C" { +#define __END_DECLS } +#else +#define __BEGIN_DECLS +#define __END_DECLS +#endif + +/* + * This code has been put in place to help reduce the addition of + * compiler specific defines in FreeBSD code. It helps to aid in + * having a compiler-agnostic source tree. + */ + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) + +#if __GNUC__ >= 3 || defined(__INTEL_COMPILER) +#define __GNUCLIKE_ASM 3 +#define __GNUCLIKE_MATH_BUILTIN_CONSTANTS +#else +#define __GNUCLIKE_ASM 2 +#endif +#define __GNUCLIKE___TYPEOF 1 +#define __GNUCLIKE___OFFSETOF 1 +#define __GNUCLIKE___SECTION 1 + +#ifndef __INTEL_COMPILER +# define __GNUCLIKE_CTOR_SECTION_HANDLING 1 +#endif + +#define __GNUCLIKE_BUILTIN_CONSTANT_P 1 +# if defined(__INTEL_COMPILER) && defined(__cplusplus) \ + && __INTEL_COMPILER < 800 +# undef __GNUCLIKE_BUILTIN_CONSTANT_P +# endif + +#if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3) && !defined(__INTEL_COMPILER) +# define __GNUCLIKE_BUILTIN_VARARGS 1 +# define __GNUCLIKE_BUILTIN_STDARG 1 +# define __GNUCLIKE_BUILTIN_VAALIST 1 +#endif + +#if defined(__GNUC__) +# define __GNUC_VA_LIST_COMPATIBILITY 1 +#endif + +#ifndef __INTEL_COMPILER +# define __GNUCLIKE_BUILTIN_NEXT_ARG 1 +# define __GNUCLIKE_MATH_BUILTIN_RELOPS +#endif + +#define __GNUCLIKE_BUILTIN_MEMCPY 1 + +/* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */ +#define __CC_SUPPORTS_INLINE 1 +#define __CC_SUPPORTS___INLINE 1 +#define __CC_SUPPORTS___INLINE__ 1 + +#define __CC_SUPPORTS___FUNC__ 1 +#define __CC_SUPPORTS_WARNING 1 + +#define __CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */ + +#define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1 + +#endif /* __GNUC__ || __INTEL_COMPILER */ + +/* + * Macro to test if we're using a specific version of gcc or later. + */ +#if defined(__GNUC__) && !defined(__INTEL_COMPILER) +#define __GNUC_PREREQ__(ma, mi) \ + (__GNUC__ > (ma) || __GNUC__ == (ma) && __GNUC_MINOR__ >= (mi)) +#else +#define __GNUC_PREREQ__(ma, mi) 0 +#endif + +/* + * The __CONCAT macro is used to concatenate parts of symbol names, e.g. + * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. + * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI + * mode -- there must be no spaces between its arguments, and for nested + * __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also + * concatenate double-quoted strings produced by the __STRING macro, but + * this only works with ANSI C. + * + * __XSTRING is like __STRING, but it expands any macros in its argument + * first. It is only available with ANSI C. + */ +#if defined(__STDC__) || defined(__cplusplus) +#define __P(protos) protos /* full-blown ANSI C */ +#define __CONCAT1(x,y) x ## y +#define __CONCAT(x,y) __CONCAT1(x,y) +#define __STRING(x) #x /* stringify without expanding x */ +#define __XSTRING(x) __STRING(x) /* expand x, then stringify */ + +#define __const const /* define reserved names to standard */ +#define __signed signed +#define __volatile volatile +#if defined(__cplusplus) +#define __inline inline /* convert to C++ keyword */ +#else +#if !(defined(__CC_SUPPORTS___INLINE)) +#define __inline /* delete GCC keyword */ +#endif /* ! __CC_SUPPORTS___INLINE */ +#endif /* !__cplusplus */ + +#else /* !(__STDC__ || __cplusplus) */ +#define __P(protos) () /* traditional C preprocessor */ +#define __CONCAT(x,y) x/**/y +#define __STRING(x) "x" + +#if !defined(__CC_SUPPORTS___INLINE) +#define __const /* delete pseudo-ANSI C keywords */ +#define __inline +#define __signed +#define __volatile +/* + * In non-ANSI C environments, new programs will want ANSI-only C keywords + * deleted from the program and old programs will want them left alone. + * When using a compiler other than gcc, programs using the ANSI C keywords + * const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS. + * When using "gcc -traditional", we assume that this is the intent; if + * __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone. + */ +#ifndef NO_ANSI_KEYWORDS +#define const /* delete ANSI C keywords */ +#define inline +#define signed +#define volatile +#endif /* !NO_ANSI_KEYWORDS */ +#endif /* !__CC_SUPPORTS___INLINE */ +#endif /* !(__STDC__ || __cplusplus) */ + +/* + * Compiler-dependent macros to help declare dead (non-returning) and + * pure (no side effects) functions, and unused variables. They are + * null except for versions of gcc that are known to support the features + * properly (old versions of gcc-2 supported the dead and pure features + * in a different (wrong) way). If we do not provide an implementation + * for a given compiler, let the compile fail if it is told to use + * a feature that we cannot live without. + */ +#ifdef lint +#define __dead2 +#define __pure2 +#define __unused +#define __packed +#define __aligned(x) +#define __section(x) +#else +#if !__GNUC_PREREQ__(2, 5) && !defined(__INTEL_COMPILER) +#define __dead2 +#define __pure2 +#define __unused +#endif +#if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 && !defined(__INTEL_COMPILER) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused +/* XXX Find out what to do for __packed, __aligned and __section */ +#endif +#if __GNUC_PREREQ__(2, 7) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) +#endif +#if defined(__INTEL_COMPILER) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) +#endif +#endif + +#if !__GNUC_PREREQ__(2, 95) +#define __alignof(x) __offsetof(struct { char __a; x __b; }, __b) +#endif + +/* + * Keywords added in C11. + */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define _Alignas(e) alignas(e) +#define _Alignof(e) alignof(e) +#define _Noreturn [[noreturn]] +#define _Static_assert(e, s) static_assert(e, s) +/* FIXME: change this to thread_local when clang in base supports it */ +#define _Thread_local __thread +#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +/* Do nothing. They are language keywords. */ +#else +/* Not supported. Implement them using our versions. */ +#define _Alignas(x) __aligned(x) +#define _Alignof(x) __alignof(x) +#define _Noreturn __dead2 +#define _Thread_local __thread +#ifdef __COUNTER__ +#define _Static_assert(x, y) __Static_assert(x, __COUNTER__) +#define __Static_assert(x, y) ___Static_assert(x, y) +#define ___Static_assert(x, y) typedef char __assert_ ## y[(x) ? 1 : -1] +#else +#define _Static_assert(x, y) struct __hack +#endif +#endif + +/* + * Emulation of C11 _Generic(). Unlike the previously defined C11 + * keywords, it is not possible to implement this using exactly the same + * syntax. Therefore implement something similar under the name + * __generic(). Unlike _Generic(), this macro can only distinguish + * between a single type, so it requires nested invocations to + * distinguish multiple cases. + */ + +#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +#define __generic(expr, t, yes, no) \ + _Generic(expr, t: yes, default: no) +#elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus) +#define __generic(expr, t, yes, no) \ + __builtin_choose_expr( \ + __builtin_types_compatible_p(__typeof(expr), t), yes, no) +#endif + +#if __GNUC_PREREQ__(2, 96) +#define __malloc_like __attribute__((__malloc__)) +#define __pure __attribute__((__pure__)) +#else +#define __malloc_like +#define __pure +#endif + +#if __GNUC_PREREQ__(3, 1) || (defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 800) +#define __always_inline __attribute__((__always_inline__)) +#else +#define __always_inline +#endif + +#if __GNUC_PREREQ__(3, 1) +#define __noinline __attribute__ ((__noinline__)) +#else +#define __noinline +#endif + +#if __GNUC_PREREQ__(3, 3) +#define __nonnull(x) __attribute__((__nonnull__(x))) +#else +#define __nonnull(x) +#endif + +#if __GNUC_PREREQ__(3, 4) +#define __fastcall __attribute__((__fastcall__)) +#else +#define __fastcall +#endif + +#if __GNUC_PREREQ__(4, 1) +#define __returns_twice __attribute__((__returns_twice__)) +#else +#define __returns_twice +#endif + +/* XXX: should use `#if __STDC_VERSION__ < 199901'. */ +#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER) +#define __func__ NULL +#endif + +#if (defined(__INTEL_COMPILER) || (defined(__GNUC__) && __GNUC__ >= 2)) && !defined(__STRICT_ANSI__) || __STDC_VERSION__ >= 199901 +#define __LONG_LONG_SUPPORTED +#endif + +/* C++11 exposes a load of C99 stuff */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define __LONG_LONG_SUPPORTED +#ifndef __STDC_LIMIT_MACROS +#define __STDC_LIMIT_MACROS +#endif +#ifndef __STDC_CONSTANT_MACROS +#define __STDC_CONSTANT_MACROS +#endif +#endif + +/* + * GCC 2.95 provides `__restrict' as an extension to C90 to support the + * C99-specific `restrict' type qualifier. We happen to use `__restrict' as + * a way to define the `restrict' type qualifier without disturbing older + * software that is unaware of C99 keywords. + */ +#if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95) +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901 || defined(lint) +#define __restrict +#else +#define __restrict restrict +#endif +#endif + +/* + * GNU C version 2.96 adds explicit branch prediction so that + * the CPU back-end can hint the processor and also so that + * code blocks can be reordered such that the predicted path + * sees a more linear flow, thus improving cache behavior, etc. + * + * The following two macros provide us with a way to utilize this + * compiler feature. Use __predict_true() if you expect the expression + * to evaluate to true, and __predict_false() if you expect the + * expression to evaluate to false. + * + * A few notes about usage: + * + * * Generally, __predict_false() error condition checks (unless + * you have some _strong_ reason to do otherwise, in which case + * document it), and/or __predict_true() `no-error' condition + * checks, assuming you want to optimize for the no-error case. + * + * * Other than that, if you don't know the likelihood of a test + * succeeding from empirical or other `hard' evidence, don't + * make predictions. + * + * * These are meant to be used in places that are run `a lot'. + * It is wasteful to make predictions in code that is run + * seldomly (e.g. at subsystem initialization time) as the + * basic block reordering that this affects can often generate + * larger code. + */ +#if __GNUC_PREREQ__(2, 96) +#define __predict_true(exp) __builtin_expect((exp), 1) +#define __predict_false(exp) __builtin_expect((exp), 0) +#else +#define __predict_true(exp) (exp) +#define __predict_false(exp) (exp) +#endif + +#if __GNUC_PREREQ__(4, 2) +#define __hidden __attribute__((__visibility__("hidden"))) +#define __exported __attribute__((__visibility__("default"))) +#else +#define __hidden +#define __exported +#endif + +/* + * We define this here since , , and + * require it. + */ +#if __GNUC_PREREQ__(4, 1) +#define __offsetof(type, field) __builtin_offsetof(type, field) +#else +#ifndef __cplusplus +#define __offsetof(type, field) \ + ((__size_t)(__uintptr_t)((const volatile void *)&((type *)0)->field)) +#else +#define __offsetof(type, field) \ + (__offsetof__ (reinterpret_cast <__size_t> \ + (&reinterpret_cast \ + (static_cast (0)->field)))) +#endif +#endif +#define __rangeof(type, start, end) \ + (__offsetof(type, end) - __offsetof(type, start)) + +/* + * Given the pointer x to the member m of the struct s, return + * a pointer to the containing structure. When using GCC, we first + * assign pointer x to a local variable, to check that its type is + * compatible with member m. + */ +#if __GNUC_PREREQ__(3, 1) +#define __containerof(x, s, m) ({ \ + const volatile __typeof(((s *)0)->m) *__x = (x); \ + __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\ +}) +#else +#define __containerof(x, s, m) \ + __DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m)) +#endif + +/* + * Compiler-dependent macros to declare that functions take printf-like + * or scanf-like arguments. They are null except for versions of gcc + * that are known to support the features properly (old versions of gcc-2 + * didn't permit keeping the keywords out of the application namespace). + */ +#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER) +#define __printflike(fmtarg, firstvararg) +#define __scanflike(fmtarg, firstvararg) +#define __format_arg(fmtarg) +#define __strfmonlike(fmtarg, firstvararg) +#define __strftimelike(fmtarg, firstvararg) +#else +#define __printflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf__, fmtarg, firstvararg))) +#define __scanflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__scanf__, fmtarg, firstvararg))) +#define __format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg))) +#define __strfmonlike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strfmon__, fmtarg, firstvararg))) +#define __strftimelike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strftime__, fmtarg, firstvararg))) +#endif + +/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */ +#if __FreeBSD_cc_version >= 300001 && defined(__GNUC__) && !defined(__INTEL_COMPILER) +#define __printf0like(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf0__, fmtarg, firstvararg))) +#else +#define __printf0like(fmtarg, firstvararg) +#endif + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) +#ifndef __INTEL_COMPILER +#define __strong_reference(sym,aliassym) \ + extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym))) +#endif +#ifdef __STDC__ +#define __weak_reference(sym,alias) \ + __asm__(".weak " #alias); \ + __asm__(".equ " #alias ", " #sym) +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning." #sym); \ + __asm__(".asciz \"" msg "\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@" #verid) +#define __sym_default(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@@" #verid) +#else +#define __weak_reference(sym,alias) \ + __asm__(".weak alias"); \ + __asm__(".equ alias, sym") +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning.sym"); \ + __asm__(".asciz \"msg\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver impl, sym@verid") +#define __sym_default(impl,sym,verid) \ + __asm__(".symver impl, sym@@verid") +#endif /* __STDC__ */ +#endif /* __GNUC__ || __INTEL_COMPILER */ + +#define __GLOBL1(sym) __asm__(".globl " #sym) +#define __GLOBL(sym) __GLOBL1(sym) + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) +#define __IDSTRING(name,string) __asm__(".ident\t\"" string "\"") +#else +/* + * The following definition might not work well if used in header files, + * but it should be better than nothing. If you want a "do nothing" + * version, then it should generate some harmless declaration, such as: + * #define __IDSTRING(name,string) struct __hack + */ +#define __IDSTRING(name,string) static const char name[] __unused = string +#endif + +/* + * Embed the rcs id of a source file in the resulting library. Note that in + * more recent ELF binutils, we use .ident allowing the ID to be stripped. + * Usage: + * __FBSDID("$FreeBSD$"); + */ +#ifndef __FBSDID +#if !defined(lint) && !defined(STRIP_FBSDID) +#define __FBSDID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __FBSDID(s) struct __hack +#endif +#endif + +#ifndef __RCSID +#ifndef NO__RCSID +#define __RCSID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __RCSID(s) struct __hack +#endif +#endif + +#ifndef __RCSID_SOURCE +#ifndef NO__RCSID_SOURCE +#define __RCSID_SOURCE(s) __IDSTRING(__CONCAT(__rcsid_source_,__LINE__),s) +#else +#define __RCSID_SOURCE(s) struct __hack +#endif +#endif + +#ifndef __SCCSID +#ifndef NO__SCCSID +#define __SCCSID(s) __IDSTRING(__CONCAT(__sccsid_,__LINE__),s) +#else +#define __SCCSID(s) struct __hack +#endif +#endif + +#ifndef __COPYRIGHT +#ifndef NO__COPYRIGHT +#define __COPYRIGHT(s) __IDSTRING(__CONCAT(__copyright_,__LINE__),s) +#else +#define __COPYRIGHT(s) struct __hack +#endif +#endif + +#ifndef __DECONST +#define __DECONST(type, var) ((type)(__uintptr_t)(const void *)(var)) +#endif + +#ifndef __DEVOLATILE +#define __DEVOLATILE(type, var) ((type)(__uintptr_t)(volatile void *)(var)) +#endif + +#ifndef __DEQUALIFY +#define __DEQUALIFY(type, var) ((type)(__uintptr_t)(const volatile void *)(var)) +#endif + +/*- + * The following definitions are an extension of the behavior originally + * implemented in , but with a different level of granularity. + * POSIX.1 requires that the macros we test be defined before any standard + * header file is included. + * + * Here's a quick run-down of the versions: + * defined(_POSIX_SOURCE) 1003.1-1988 + * _POSIX_C_SOURCE == 1 1003.1-1990 + * _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option + * _POSIX_C_SOURCE == 199309 1003.1b-1993 + * _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995, + * and the omnibus ISO/IEC 9945-1: 1996 + * _POSIX_C_SOURCE == 200112 1003.1-2001 + * _POSIX_C_SOURCE == 200809 1003.1-2008 + * + * In addition, the X/Open Portability Guide, which is now the Single UNIX + * Specification, defines a feature-test macro which indicates the version of + * that specification, and which subsumes _POSIX_C_SOURCE. + * + * Our macros begin with two underscores to avoid namespace screwage. + */ + +/* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 1 +#undef _POSIX_C_SOURCE /* Probably illegal, but beyond caring now. */ +#define _POSIX_C_SOURCE 199009 +#endif + +/* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 2 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199209 +#endif + +/* Deal with various X/Open Portability Guides and Single UNIX Spec. */ +#ifdef _XOPEN_SOURCE +#if _XOPEN_SOURCE - 0 >= 700 +#define __XSI_VISIBLE 700 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809 +#elif _XOPEN_SOURCE - 0 >= 600 +#define __XSI_VISIBLE 600 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200112 +#elif _XOPEN_SOURCE - 0 >= 500 +#define __XSI_VISIBLE 500 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199506 +#endif +#endif + +/* + * Deal with all versions of POSIX. The ordering relative to the tests above is + * important. + */ +#if defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE) +#define _POSIX_C_SOURCE 198808 +#endif +#ifdef _POSIX_C_SOURCE +#if _POSIX_C_SOURCE >= 200809 +#define __POSIX_VISIBLE 200809 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 200112 +#define __POSIX_VISIBLE 200112 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 199506 +#define __POSIX_VISIBLE 199506 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199309 +#define __POSIX_VISIBLE 199309 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199209 +#define __POSIX_VISIBLE 199209 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199009 +#define __POSIX_VISIBLE 199009 +#define __ISO_C_VISIBLE 1990 +#else +#define __POSIX_VISIBLE 198808 +#define __ISO_C_VISIBLE 0 +#endif /* _POSIX_C_SOURCE */ +#else +/*- + * Deal with _ANSI_SOURCE: + * If it is defined, and no other compilation environment is explicitly + * requested, then define our internal feature-test macros to zero. This + * makes no difference to the preprocessor (undefined symbols in preprocessing + * expressions are defined to have value zero), but makes it more convenient for + * a test program to print out the values. + * + * If a program mistakenly defines _ANSI_SOURCE and some other macro such as + * _POSIX_C_SOURCE, we will assume that it wants the broader compilation + * environment (and in fact we will never get here). + */ +#if defined(_ANSI_SOURCE) /* Hide almost everything. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1990 +#elif defined(_C99_SOURCE) /* Localism to specify strict C99 env. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1999 +#else /* Default environment: show everything. */ +#define __POSIX_VISIBLE 200809 +#define __XSI_VISIBLE 700 +#define __BSD_VISIBLE 1 +#define __ISO_C_VISIBLE 1999 +#endif +#endif + +#ifndef __has_feature +#define __has_feature(x) 0 +#endif +#ifndef __has_include +#define __has_include(x) 0 +#endif +#ifndef __has_builtin +#define __has_builtin(x) 0 +#endif + +#if defined(__mips) || defined(__powerpc64__) || defined(__arm__) +#define __NO_TLS 1 +#endif + +#endif /* !_SYS_CDEFS_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/ctype.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/ctype.h new file mode 100644 index 0000000..f2758b7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/ctype.h @@ -0,0 +1,59 @@ +/*- + * Copyright (c) 1982, 1988, 1991, 1993 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2009-2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#ifndef _SYS_CTYPE_H_ +#define _SYS_CTYPE_H_ + +#define isspace(c) ((c) == ' ' || ((c) >= '\t' && (c) <= '\r')) +#define isascii(c) (((c) & ~0x7f) == 0) +#define isupper(c) ((c) >= 'A' && (c) <= 'Z') +#define islower(c) ((c) >= 'a' && (c) <= 'z') +#define isalpha(c) (isupper(c) || islower(c)) +#define isdigit(c) ((c) >= '0' && (c) <= '9') +#define isxdigit(c) (isdigit(c) \ + || ((c) >= 'A' && (c) <= 'F') \ + || ((c) >= 'a' && (c) <= 'f')) +#define isprint(c) ((c) >= ' ' && (c) <= '~') + +#define toupper(c) ((c) - 0x20 * (((c) >= 'a') && ((c) <= 'z'))) +#define tolower(c) ((c) + 0x20 * (((c) >= 'A') && ((c) <= 'Z'))) + +#endif /* !_SYS_CTYPE_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/errno.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/errno.h new file mode 100644 index 0000000..f595514 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/errno.h @@ -0,0 +1,193 @@ +/*- + * Copyright (c) 1982, 1986, 1989, 1993 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)errno.h 8.5 (Berkeley) 1/21/94 + * $FreeBSD$ + */ + +#ifndef _SYS_ERRNO_H_ +#define _SYS_ERRNO_H_ + +#ifndef _KERNEL +#include +__BEGIN_DECLS +int * __error(void); +__END_DECLS +#define errno (* __error()) +#endif + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* Input/output error */ +#define ENXIO 6 /* Device not configured */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file descriptor */ +#define ECHILD 10 /* No child processes */ +#define EDEADLK 11 /* Resource deadlock avoided */ + /* 11 was EAGAIN */ +#define ENOMEM 12 /* Cannot allocate memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#ifndef _POSIX_SOURCE +#define ENOTBLK 15 /* Block device required */ +#endif +#define EBUSY 16 /* Device busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* Operation not supported by device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* Too many open files in system */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Inappropriate ioctl for device */ +#ifndef _POSIX_SOURCE +#define ETXTBSY 26 /* Text file busy */ +#endif +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only filesystem */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ + +/* math software */ +#define EDOM 33 /* Numerical argument out of domain */ +#define ERANGE 34 /* Result too large */ + +/* non-blocking and interrupt i/o */ +#define EAGAIN 35 /* Resource temporarily unavailable */ +#ifndef _POSIX_SOURCE +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define EINPROGRESS 36 /* Operation now in progress */ +#define EALREADY 37 /* Operation already in progress */ + +/* ipc/network software -- argument errors */ +#define ENOTSOCK 38 /* Socket operation on non-socket */ +#define EDESTADDRREQ 39 /* Destination address required */ +#define EMSGSIZE 40 /* Message too long */ +#define EPROTOTYPE 41 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 42 /* Protocol not available */ +#define EPROTONOSUPPORT 43 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 44 /* Socket type not supported */ +#define EOPNOTSUPP 45 /* Operation not supported */ +#define ENOTSUP EOPNOTSUPP /* Operation not supported */ +#define EPFNOSUPPORT 46 /* Protocol family not supported */ +#define EAFNOSUPPORT 47 /* Address family not supported by protocol family */ +#define EADDRINUSE 48 /* Address already in use */ +#define EADDRNOTAVAIL 49 /* Can't assign requested address */ + +/* ipc/network software -- operational errors */ +#define ENETDOWN 50 /* Network is down */ +#define ENETUNREACH 51 /* Network is unreachable */ +#define ENETRESET 52 /* Network dropped connection on reset */ +#define ECONNABORTED 53 /* Software caused connection abort */ +#define ECONNRESET 54 /* Connection reset by peer */ +#define ENOBUFS 55 /* No buffer space available */ +#define EISCONN 56 /* Socket is already connected */ +#define ENOTCONN 57 /* Socket is not connected */ +#define ESHUTDOWN 58 /* Can't send after socket shutdown */ +#define ETOOMANYREFS 59 /* Too many references: can't splice */ +#define ETIMEDOUT 60 /* Operation timed out */ +#define ECONNREFUSED 61 /* Connection refused */ + +#define ELOOP 62 /* Too many levels of symbolic links */ +#endif /* _POSIX_SOURCE */ +#define ENAMETOOLONG 63 /* File name too long */ + +/* should be rearranged */ +#ifndef _POSIX_SOURCE +#define EHOSTDOWN 64 /* Host is down */ +#define EHOSTUNREACH 65 /* No route to host */ +#endif /* _POSIX_SOURCE */ +#define ENOTEMPTY 66 /* Directory not empty */ + +/* quotas & mush */ +#ifndef _POSIX_SOURCE +#define EPROCLIM 67 /* Too many processes */ +#define EUSERS 68 /* Too many users */ +#define EDQUOT 69 /* Disc quota exceeded */ + +/* Network File System */ +#define ESTALE 70 /* Stale NFS file handle */ +#define EREMOTE 71 /* Too many levels of remote in path */ +#define EBADRPC 72 /* RPC struct is bad */ +#define ERPCMISMATCH 73 /* RPC version wrong */ +#define EPROGUNAVAIL 74 /* RPC prog. not avail */ +#define EPROGMISMATCH 75 /* Program version wrong */ +#define EPROCUNAVAIL 76 /* Bad procedure for program */ +#endif /* _POSIX_SOURCE */ + +#define ENOLCK 77 /* No locks available */ +#define ENOSYS 78 /* Function not implemented */ + +#ifndef _POSIX_SOURCE +#define EFTYPE 79 /* Inappropriate file type or format */ +#define EAUTH 80 /* Authentication error */ +#define ENEEDAUTH 81 /* Need authenticator */ +#define EIDRM 82 /* Identifier removed */ +#define ENOMSG 83 /* No message of desired type */ +#define EOVERFLOW 84 /* Value too large to be stored in data type */ +#define ECANCELED 85 /* Operation canceled */ +#define EILSEQ 86 /* Illegal byte sequence */ +#define ENOATTR 87 /* Attribute not found */ + +#define EDOOFUS 88 /* Programming error */ +#endif /* _POSIX_SOURCE */ + +#define EBADMSG 89 /* Bad message */ +#define EMULTIHOP 90 /* Multihop attempted */ +#define ENOLINK 91 /* Link has been severed */ +#define EPROTO 92 /* Protocol error */ + +#ifndef _POSIX_SOURCE +#define ENOTCAPABLE 93 /* Capabilities insufficient */ +#define ECAPMODE 94 /* Not permitted in capability mode */ +#endif /* _POSIX_SOURCE */ + +#ifndef _POSIX_SOURCE +#define ELAST 94 /* Must be equal largest errno */ +#endif /* _POSIX_SOURCE */ + +#ifdef _KERNEL +/* pseudo-errors returned inside kernel to modify return to process */ +#define ERESTART (-1) /* restart syscall */ +#define EJUSTRETURN (-2) /* don't modify regs, just return */ +#define ENOIOCTL (-3) /* ioctl not handled by this layer */ +#define EDIRIOCTL (-4) /* do direct ioctl in GEOM */ +#endif + +#endif diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/limits.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/limits.h new file mode 100644 index 0000000..c56a337 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/limits.h @@ -0,0 +1,100 @@ +/*- + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS_LIMITS_H_ +#define _SYS_LIMITS_H_ + +#include +#include + +#define CHAR_BIT __CHAR_BIT /* number of bits in a char */ + +#define SCHAR_MAX __SCHAR_MAX /* max value for a signed char */ +#define SCHAR_MIN __SCHAR_MIN /* min value for a signed char */ + +#define UCHAR_MAX __UCHAR_MAX /* max value for an unsigned char */ + +#ifdef __CHAR_UNSIGNED__ +#define CHAR_MAX UCHAR_MAX /* max value for a char */ +#define CHAR_MIN 0 /* min value for a char */ +#else +#define CHAR_MAX SCHAR_MAX +#define CHAR_MIN SCHAR_MIN +#endif + +#define USHRT_MAX __USHRT_MAX /* max value for an unsigned short */ +#define SHRT_MAX __SHRT_MAX /* max value for a short */ +#define SHRT_MIN __SHRT_MIN /* min value for a short */ + +#define UINT_MAX __UINT_MAX /* max value for an unsigned int */ +#define INT_MAX __INT_MAX /* max value for an int */ +#define INT_MIN __INT_MIN /* min value for an int */ + +#define ULONG_MAX __ULONG_MAX /* max for an unsigned long */ +#define LONG_MAX __LONG_MAX /* max for a long */ +#define LONG_MIN __LONG_MIN /* min for a long */ + +#ifdef __LONG_LONG_SUPPORTED +#define ULLONG_MAX __ULLONG_MAX /* max for an unsigned long long */ +#define LLONG_MAX __LLONG_MAX /* max for a long long */ +#define LLONG_MIN __LLONG_MIN /* min for a long long */ +#endif + +#if __POSIX_VISIBLE || __XSI_VISIBLE +#define SSIZE_MAX __SSIZE_MAX /* max value for an ssize_t */ +#endif + +#if __POSIX_VISIBLE >= 200112 || __XSI_VISIBLE +#define SIZE_T_MAX __SIZE_T_MAX /* max value for a size_t */ + +#define OFF_MAX __OFF_MAX /* max value for an off_t */ +#define OFF_MIN __OFF_MIN /* min value for an off_t */ +#endif + +#if __BSD_VISIBLE +#define GID_MAX UINT_MAX /* max value for a gid_t */ +#define UID_MAX UINT_MAX /* max value for a uid_t */ + +#define UQUAD_MAX (__UQUAD_MAX) /* max value for a uquad_t */ +#define QUAD_MAX (__QUAD_MAX) /* max value for a quad_t */ +#define QUAD_MIN (__QUAD_MIN) /* min value for a quad_t */ +#endif + +#if __XSI_VISIBLE || __POSIX_VISIBLE >= 200809 +#define LONG_BIT __LONG_BIT +#define WORD_BIT __WORD_BIT +#endif + +#if __POSIX_VISIBLE +#define MQ_PRIO_MAX 64 +#endif + +#endif /* !_SYS_LIMITS_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/stdarg.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/stdarg.h new file mode 100644 index 0000000..c315dfc --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/stdarg.h @@ -0,0 +1,75 @@ +/*- + * Copyright (c) 2002 David E. O'Brien. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_STDARG_H_ +#define _MACHINE_STDARG_H_ + +#include +#include + +#ifndef _VA_LIST_DECLARED +#define _VA_LIST_DECLARED +typedef __va_list va_list; +#endif + +#ifdef __GNUCLIKE_BUILTIN_STDARG + +#define va_start(ap, last) \ + __builtin_va_start((ap), (last)) + +#define va_arg(ap, type) \ + __builtin_va_arg((ap), type) + +#define __va_copy(dest, src) \ + __builtin_va_copy((dest), (src)) + +#if __ISO_C_VISIBLE >= 1999 +#define va_copy(dest, src) \ + __va_copy(dest, src) +#endif + +#define va_end(ap) \ + __builtin_va_end(ap) + +#elif defined(lint) +/* Provide a fake implementation for lint's benefit */ +#define __va_size(type) \ + (((sizeof(type) + sizeof(long) - 1) / sizeof(long)) * sizeof(long)) +#define va_start(ap, last) \ + ((ap) = (va_list)&(last) + __va_size(last)) +#define va_arg(ap, type) \ + (*(type *)((ap) += __va_size(type), (ap) - __va_size(type))) +#define va_end(ap) + +#else +#error this file needs to be ported to your compiler +#endif + +#endif /* !_MACHINE_STDARG_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/stdint.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/stdint.h new file mode 100644 index 0000000..aa5ac81 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/stdint.h @@ -0,0 +1,74 @@ +/*- + * Copyright (c) 2001 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS_STDINT_H_ +#define _SYS_STDINT_H_ + +#include +#include + +#include +#include + +typedef __int_least8_t int_least8_t; +typedef __int_least16_t int_least16_t; +typedef __int_least32_t int_least32_t; +typedef __int_least64_t int_least64_t; + +typedef __uint_least8_t uint_least8_t; +typedef __uint_least16_t uint_least16_t; +typedef __uint_least32_t uint_least32_t; +typedef __uint_least64_t uint_least64_t; + +typedef __int_fast8_t int_fast8_t; +typedef __int_fast16_t int_fast16_t; +typedef __int_fast32_t int_fast32_t; +typedef __int_fast64_t int_fast64_t; + +typedef __uint_fast8_t uint_fast8_t; +typedef __uint_fast16_t uint_fast16_t; +typedef __uint_fast32_t uint_fast32_t; +typedef __uint_fast64_t uint_fast64_t; + +#ifndef _INTMAX_T_DECLARED +typedef __intmax_t intmax_t; +#define _INTMAX_T_DECLARED +#endif +#ifndef _UINTMAX_T_DECLARED +typedef __uintmax_t uintmax_t; +#define _UINTMAX_T_DECLARED +#endif + +/* GNU and Darwin define this and people seem to think it's portable */ +#if defined(UINTPTR_MAX) && defined(UINT64_MAX) && (UINTPTR_MAX == UINT64_MAX) +#define __WORDSIZE 64 +#else +#define __WORDSIZE 32 +#endif + +#endif /* !_SYS_STDINT_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/timespec.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/timespec.h new file mode 100644 index 0000000..2505cef --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/timespec.h @@ -0,0 +1,63 @@ +/*- + * Copyright (c) 1982, 1986, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)time.h 8.5 (Berkeley) 5/4/95 + * from: FreeBSD: src/sys/sys/time.h,v 1.43 2000/03/20 14:09:05 phk Exp + * $FreeBSD$ + */ + +#ifndef _SYS_TIMESPEC_H_ +#define _SYS_TIMESPEC_H_ + +#include +#include + +#if __BSD_VISIBLE +#define TIMEVAL_TO_TIMESPEC(tv, ts) \ + do { \ + (ts)->tv_sec = (tv)->tv_sec; \ + (ts)->tv_nsec = (tv)->tv_usec * 1000; \ + } while (0) +#define TIMESPEC_TO_TIMEVAL(tv, ts) \ + do { \ + (tv)->tv_sec = (ts)->tv_sec; \ + (tv)->tv_usec = (ts)->tv_nsec / 1000; \ + } while (0) + +#endif /* __BSD_VISIBLE */ + +/* + * Structure defined by POSIX.1b to be like a itimerval, but with + * timespecs. Used in the timer_*() system calls. + */ +struct itimerspec { + struct timespec it_interval; + struct timespec it_value; +}; + +#endif /* _SYS_TIMESPEC_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/types.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/types.h new file mode 100644 index 0000000..ae2ea33 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/types.h @@ -0,0 +1,245 @@ +/*- + * Copyright (c) 1982, 1986, 1991, 1993, 1994 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)types.h 8.6 (Berkeley) 2/19/95 + * $FreeBSD$ + */ + +#ifndef _SYS_TYPES_H_ +#define _SYS_TYPES_H_ + +#include + +/* Machine type dependent parameters. */ +#include + +#if __BSD_VISIBLE +typedef unsigned char u_char; +typedef unsigned short u_short; +typedef unsigned int u_int; +typedef unsigned long u_long; +#ifndef _KERNEL +typedef unsigned short ushort; /* Sys V compatibility */ +typedef unsigned int uint; /* Sys V compatibility */ +#endif +#endif + +/* + * XXX POSIX sized integrals that should appear only in . + */ +#include + +typedef __uint8_t u_int8_t; /* unsigned integrals (deprecated) */ +typedef __uint16_t u_int16_t; +typedef __uint32_t u_int32_t; +typedef __uint64_t u_int64_t; + +typedef __uint64_t u_quad_t; /* quads (deprecated) */ +typedef __int64_t quad_t; +typedef quad_t *qaddr_t; + +typedef char *caddr_t; /* core address */ +typedef const char *c_caddr_t; /* core address, pointer to const */ + +#ifndef _BLKSIZE_T_DECLARED +typedef __blksize_t blksize_t; +#define _BLKSIZE_T_DECLARED +#endif + +typedef __cpuwhich_t cpuwhich_t; +typedef __cpulevel_t cpulevel_t; +typedef __cpusetid_t cpusetid_t; + +#ifndef _BLKCNT_T_DECLARED +typedef __blkcnt_t blkcnt_t; +#define _BLKCNT_T_DECLARED +#endif + +#ifndef _CLOCK_T_DECLARED +typedef __clock_t clock_t; +#define _CLOCK_T_DECLARED +#endif + +#ifndef _CLOCKID_T_DECLARED +typedef __clockid_t clockid_t; +#define _CLOCKID_T_DECLARED +#endif + +typedef __critical_t critical_t; /* Critical section value */ +typedef __int64_t daddr_t; /* disk address */ + +#ifndef _DEV_T_DECLARED +typedef __dev_t dev_t; /* device number or struct cdev */ +#define _DEV_T_DECLARED +#endif + +#ifndef _FFLAGS_T_DECLARED +typedef __fflags_t fflags_t; /* file flags */ +#define _FFLAGS_T_DECLARED +#endif + +typedef __fixpt_t fixpt_t; /* fixed point number */ + +#ifndef _FSBLKCNT_T_DECLARED /* for statvfs() */ +typedef __fsblkcnt_t fsblkcnt_t; +typedef __fsfilcnt_t fsfilcnt_t; +#define _FSBLKCNT_T_DECLARED +#endif + +#ifndef _GID_T_DECLARED +typedef __gid_t gid_t; /* group id */ +#define _GID_T_DECLARED +#endif + +#ifndef _IN_ADDR_T_DECLARED +typedef __uint32_t in_addr_t; /* base type for internet address */ +#define _IN_ADDR_T_DECLARED +#endif + +#ifndef _IN_PORT_T_DECLARED +typedef __uint16_t in_port_t; +#define _IN_PORT_T_DECLARED +#endif + +#ifndef _ID_T_DECLARED +typedef __id_t id_t; /* can hold a uid_t or pid_t */ +#define _ID_T_DECLARED +#endif + +#ifndef _INO_T_DECLARED +typedef __ino_t ino_t; /* inode number */ +#define _INO_T_DECLARED +#endif + +#ifndef _KEY_T_DECLARED +typedef __key_t key_t; /* IPC key (for Sys V IPC) */ +#define _KEY_T_DECLARED +#endif + +#ifndef _LWPID_T_DECLARED +typedef __lwpid_t lwpid_t; /* Thread ID (a.k.a. LWP) */ +#define _LWPID_T_DECLARED +#endif + +#ifndef _MODE_T_DECLARED +typedef __mode_t mode_t; /* permissions */ +#define _MODE_T_DECLARED +#endif + +#ifndef _ACCMODE_T_DECLARED +typedef __accmode_t accmode_t; /* access permissions */ +#define _ACCMODE_T_DECLARED +#endif + +#ifndef _NLINK_T_DECLARED +typedef __nlink_t nlink_t; /* link count */ +#define _NLINK_T_DECLARED +#endif + +#ifndef _OFF_T_DECLARED +typedef __off_t off_t; /* file offset */ +#define _OFF_T_DECLARED +#endif + +#ifndef _PID_T_DECLARED +typedef __pid_t pid_t; /* process id */ +#define _PID_T_DECLARED +#endif + +typedef __register_t register_t; + +#ifndef _RLIM_T_DECLARED +typedef __rlim_t rlim_t; /* resource limit */ +#define _RLIM_T_DECLARED +#endif + +typedef __int64_t sbintime_t; + +typedef __segsz_t segsz_t; /* segment size (in pages) */ + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#ifndef _SSIZE_T_DECLARED +typedef __ssize_t ssize_t; +#define _SSIZE_T_DECLARED +#endif + +#ifndef _SUSECONDS_T_DECLARED +typedef __suseconds_t suseconds_t; /* microseconds (signed) */ +#define _SUSECONDS_T_DECLARED +#endif + +#ifndef _TIME_T_DECLARED +typedef __time_t time_t; +#define _TIME_T_DECLARED +#endif + +#ifndef _TIMER_T_DECLARED +typedef __timer_t timer_t; +#define _TIMER_T_DECLARED +#endif + +#ifndef _MQD_T_DECLARED +typedef __mqd_t mqd_t; +#define _MQD_T_DECLARED +#endif + +typedef __u_register_t u_register_t; + +#ifndef _UID_T_DECLARED +typedef __uid_t uid_t; /* user id */ +#define _UID_T_DECLARED +#endif + +#ifndef _USECONDS_T_DECLARED +typedef __useconds_t useconds_t; /* microseconds (unsigned) */ +#define _USECONDS_T_DECLARED +#endif + +#ifndef _CAP_RIGHTS_T_DECLARED +#define _CAP_RIGHTS_T_DECLARED +struct cap_rights; + +typedef struct cap_rights cap_rights_t; +#endif + +typedef __vm_offset_t vm_offset_t; +typedef __vm_ooffset_t vm_ooffset_t; +typedef __vm_paddr_t vm_paddr_t; +typedef __vm_pindex_t vm_pindex_t; +typedef __vm_size_t vm_size_t; + +#endif /* !_SYS_TYPES_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/uuid.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/uuid.h new file mode 100644 index 0000000..5c4767b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/sys/uuid.h @@ -0,0 +1,61 @@ +/*- + * Copyright (c) 2002 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#ifndef _SYS_UUID_H_ +#define _SYS_UUID_H_ + +#include + +/* Length of a node address (an IEEE 802 address). */ +#define _UUID_NODE_LEN 6 + +/* + * See also: + * http://www.opengroup.org/dce/info/draft-leach-uuids-guids-01.txt + * http://www.opengroup.org/onlinepubs/009629399/apdxa.htm + * + * A DCE 1.1 compatible source representation of UUIDs. + */ +struct uuid { + uint32_t time_low; + uint16_t time_mid; + uint16_t time_hi_and_version; + uint8_t clock_seq_hi_and_reserved; + uint8_t clock_seq_low; + uint8_t node[_UUID_NODE_LEN]; +}; + +/* XXX namespace pollution? */ +typedef struct uuid uuid_t; + +#endif /* _SYS_UUID_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/time.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/time.h new file mode 100644 index 0000000..08200cf --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/time.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 1989, 1993 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)time.h 8.3 (Berkeley) 1/21/94 + */ + +/* + * $FreeBSD$ + */ + +#ifndef _TIME_H_ +#define _TIME_H_ + +#include +#include +#include + +#if __POSIX_VISIBLE > 0 && __POSIX_VISIBLE < 200112 || __BSD_VISIBLE +/* + * Frequency of the clock ticks reported by times(). Deprecated - use + * sysconf(_SC_CLK_TCK) instead. (Removed in 1003.1-2001.) + */ +#define CLK_TCK 128 +#endif + +/* Frequency of the clock ticks reported by clock(). */ +#define CLOCKS_PER_SEC 128 + +#ifndef _CLOCK_T_DECLARED +typedef __clock_t clock_t; +#define _CLOCK_T_DECLARED +#endif + +#ifndef _TIME_T_DECLARED +typedef __time_t time_t; +#define _TIME_T_DECLARED +#endif + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#if __POSIX_VISIBLE >= 199309 +/* + * New in POSIX 1003.1b-1993. + */ +#ifndef _CLOCKID_T_DECLARED +typedef __clockid_t clockid_t; +#define _CLOCKID_T_DECLARED +#endif + +#ifndef _TIMER_T_DECLARED +typedef __timer_t timer_t; +#define _TIMER_T_DECLARED +#endif + +#include +#endif /* __POSIX_VISIBLE >= 199309 */ + +#if __POSIX_VISIBLE >= 200112 +#ifndef _PID_T_DECLARED +typedef __pid_t pid_t; +#define _PID_T_DECLARED +#endif +#endif + +/* These macros are also in sys/time.h. */ +#if !defined(CLOCK_REALTIME) && __POSIX_VISIBLE >= 200112 +#define CLOCK_REALTIME 0 +#ifdef __BSD_VISIBLE +#define CLOCK_VIRTUAL 1 +#define CLOCK_PROF 2 +#endif +#define CLOCK_MONOTONIC 4 +#define CLOCK_UPTIME 5 /* FreeBSD-specific. */ +#define CLOCK_UPTIME_PRECISE 7 /* FreeBSD-specific. */ +#define CLOCK_UPTIME_FAST 8 /* FreeBSD-specific. */ +#define CLOCK_REALTIME_PRECISE 9 /* FreeBSD-specific. */ +#define CLOCK_REALTIME_FAST 10 /* FreeBSD-specific. */ +#define CLOCK_MONOTONIC_PRECISE 11 /* FreeBSD-specific. */ +#define CLOCK_MONOTONIC_FAST 12 /* FreeBSD-specific. */ +#define CLOCK_SECOND 13 /* FreeBSD-specific. */ +#define CLOCK_THREAD_CPUTIME_ID 14 +#define CLOCK_PROCESS_CPUTIME_ID 15 +#endif /* !defined(CLOCK_REALTIME) && __POSIX_VISIBLE >= 200112 */ + +#if !defined(TIMER_ABSTIME) && __POSIX_VISIBLE >= 200112 +#if __BSD_VISIBLE +#define TIMER_RELTIME 0x0 /* relative timer */ +#endif +#define TIMER_ABSTIME 0x1 /* absolute timer */ +#endif /* !defined(TIMER_ABSTIME) && __POSIX_VISIBLE >= 200112 */ + +struct tm { + int tm_sec; /* seconds after the minute [0-60] */ + int tm_min; /* minutes after the hour [0-59] */ + int tm_hour; /* hours since midnight [0-23] */ + int tm_mday; /* day of the month [1-31] */ + int tm_mon; /* months since January [0-11] */ + int tm_year; /* years since 1900 */ + int tm_wday; /* days since Sunday [0-6] */ + int tm_yday; /* days since January 1 [0-365] */ + int tm_isdst; /* Daylight Savings Time flag */ + long tm_gmtoff; /* offset from UTC in seconds */ + char *tm_zone; /* timezone abbreviation */ +}; + +#if __POSIX_VISIBLE +extern char *tzname[]; +#endif + +__BEGIN_DECLS +char *asctime(const struct tm *); +clock_t clock(void); +char *ctime(const time_t *); +double difftime(time_t, time_t); +/* XXX missing: getdate() */ +struct tm *gmtime(const time_t *); +struct tm *localtime(const time_t *); +time_t mktime(struct tm *); +size_t strftime(char *__restrict, size_t, const char *__restrict, + const struct tm *__restrict); +time_t time(time_t *); +#if __POSIX_VISIBLE >= 200112 +struct sigevent; +int timer_create(clockid_t, struct sigevent *__restrict, timer_t *__restrict); +int timer_delete(timer_t); +int timer_gettime(timer_t, struct itimerspec *); +int timer_getoverrun(timer_t); +int timer_settime(timer_t, int, const struct itimerspec *__restrict, + struct itimerspec *__restrict); +#endif +#if __POSIX_VISIBLE +void tzset(void); +#endif + +#if __POSIX_VISIBLE >= 199309 +int clock_getres(clockid_t, struct timespec *); +int clock_gettime(clockid_t, struct timespec *); +int clock_settime(clockid_t, const struct timespec *); +/* XXX missing: clock_nanosleep() */ +int nanosleep(const struct timespec *, struct timespec *); +#endif /* __POSIX_VISIBLE >= 199309 */ + +#if __POSIX_VISIBLE >= 200112 +int clock_getcpuclockid(pid_t, clockid_t *); +#endif + +#if __POSIX_VISIBLE >= 199506 +char *asctime_r(const struct tm *, char *); +char *ctime_r(const time_t *, char *); +struct tm *gmtime_r(const time_t *, struct tm *); +struct tm *localtime_r(const time_t *, struct tm *); +#endif + +#if __XSI_VISIBLE +char *strptime(const char *__restrict, const char *__restrict, + struct tm *__restrict); +#endif + +#if __BSD_VISIBLE +char *timezone(int, int); /* XXX XSI conflict */ +void tzsetwall(void); +time_t timelocal(struct tm * const); +time_t timegm(struct tm * const); +#endif /* __BSD_VISIBLE */ + +#if __POSIX_VISIBLE >= 200809 || defined(_XLOCALE_H_) +#include +#endif +__END_DECLS + +#endif /* !_TIME_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/xlocale/_strings.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/xlocale/_strings.h new file mode 100644 index 0000000..da1cff3 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/xlocale/_strings.h @@ -0,0 +1,48 @@ +/*- + * Copyright (c) 2011, 2012 The FreeBSD Foundation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _LOCALE_T_DEFINED +#define _LOCALE_T_DEFINED +typedef struct _xlocale *locale_t; +#endif + +/* + * This file is included from both strings.h and xlocale.h. We need to expose + * the declarations unconditionally if we are included from xlocale.h, but only + * if we are in POSIX2008 mode if included from string.h. + */ + +#ifndef _XLOCALE_STRINGS1_H +#define _XLOCALE_STRINGS1_H + +/* + * POSIX2008 functions + */ +int strcasecmp_l(const char *, const char *, locale_t); +int strncasecmp_l(const char *, const char *, size_t, locale_t); +#endif /* _XLOCALE_STRINGS1_H */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/xlocale/_time.h b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/xlocale/_time.h new file mode 100644 index 0000000..6da49a4 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/include/stdlib/xlocale/_time.h @@ -0,0 +1,58 @@ +/*- + * Copyright (c) 2011, 2012 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by David Chisnall under sponsorship from + * the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _LOCALE_T_DEFINED +#define _LOCALE_T_DEFINED +typedef struct _xlocale *locale_t; +#endif + +/* + * This file is included from both locale.h and xlocale.h. We need to expose + * the declarations unconditionally if we are included from xlocale.h, but only + * if we are in POSIX2008 mode if included from locale.h. + */ +#ifndef _XLOCALE_LOCALE1_H +#define _XLOCALE_LOCALE1_H + +size_t strftime_l(char *__restrict, size_t, const char *__restrict, + const struct tm *__restrict, locale_t) __strftimelike(3, 0); + +#endif /* _XLOCALE_LOCALE1_H */ + +#ifdef _XLOCALE_H_ +#ifndef _XLOCALE_LOCALE2_H +#define _XLOCALE_LOCALE2_H + +char *strptime_l(const char *__restrict, const char *__restrict, + struct tm *__restrict, locale_t); + +#endif /* _XLOCALE_LOCALE2_H */ +#endif /* _XLOCALE_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/aarch64/cache_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/lib/aarch64/cache_helpers.S new file mode 100644 index 0000000..476b906 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/aarch64/cache_helpers.S @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl flush_dcache_range + .globl clean_dcache_range + .globl inv_dcache_range + .globl dcsw_op_louis + .globl dcsw_op_all + .globl dcsw_op_level1 + .globl dcsw_op_level2 + .globl dcsw_op_level3 + +/* + * This macro can be used for implementing various data cache operations `op` + */ +.macro do_dcache_maintenance_by_mva op + dcache_line_size x2, x3 + add x1, x0, x1 + sub x3, x2, #1 + bic x0, x0, x3 +loop_\op: + dc \op, x0 + add x0, x0, x2 + cmp x0, x1 + b.lo loop_\op + dsb sy + ret +.endm + /* ------------------------------------------ + * Clean+Invalidate from base address till + * size. 'x0' = addr, 'x1' = size + * ------------------------------------------ + */ +func flush_dcache_range + do_dcache_maintenance_by_mva civac +endfunc flush_dcache_range + + /* ------------------------------------------ + * Clean from base address till size. + * 'x0' = addr, 'x1' = size + * ------------------------------------------ + */ +func clean_dcache_range + do_dcache_maintenance_by_mva cvac +endfunc clean_dcache_range + + /* ------------------------------------------ + * Invalidate from base address till + * size. 'x0' = addr, 'x1' = size + * ------------------------------------------ + */ +func inv_dcache_range + do_dcache_maintenance_by_mva ivac +endfunc inv_dcache_range + + + /* --------------------------------------------------------------- + * Data cache operations by set/way to the level specified + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * x3: The last cache level to operate on + * x9: clidr_el1 + * x10: The cache level to begin operation from + * and will carry out the operation on each data cache from level 0 + * to the level in x3 in sequence + * + * The dcsw_op macro sets up the x3 and x9 parameters based on + * clidr_el1 cache information before invoking the main function + * --------------------------------------------------------------- + */ + + .macro dcsw_op shift, fw, ls + mrs x9, clidr_el1 + ubfx x3, x9, \shift, \fw + lsl x3, x3, \ls + mov x10, xzr + b do_dcsw_op + .endm + +func do_dcsw_op + cbz x3, exit + adr x14, dcsw_loop_table // compute inner loop address + add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions + mov x0, x9 + mov w8, #1 +loop1: + add x2, x10, x10, lsr #1 // work out 3x current cache level + lsr x1, x0, x2 // extract cache type bits from clidr + and x1, x1, #7 // mask the bits for current cache only + cmp x1, #2 // see what cache we have at this level + b.lt level_done // nothing to do if no cache or icache + + msr csselr_el1, x10 // select current cache level in csselr + isb // isb to sych the new cssr&csidr + mrs x1, ccsidr_el1 // read the new ccsidr + and x2, x1, #7 // extract the length of the cache lines + add x2, x2, #4 // add 4 (line length offset) + ubfx x4, x1, #3, #10 // maximum way number + clz w5, w4 // bit position of way size increment + lsl w9, w4, w5 // w9 = aligned max way number + lsl w16, w8, w5 // w16 = way number loop decrement + orr w9, w10, w9 // w9 = combine way and cache number + ubfx w6, w1, #13, #15 // w6 = max set number + lsl w17, w8, w2 // w17 = set number loop decrement + dsb sy // barrier before we start this level + br x14 // jump to DC operation specific loop + + .macro dcsw_loop _op +loop2_\_op: + lsl w7, w6, w2 // w7 = aligned max set number + +loop3_\_op: + orr w11, w9, w7 // combine cache, way and set number + dc \_op, x11 + subs w7, w7, w17 // decrement set number + b.ge loop3_\_op + + subs x9, x9, x16 // decrement way number + b.ge loop2_\_op + + b level_done + .endm + +level_done: + add x10, x10, #2 // increment cache number + cmp x3, x10 + b.gt loop1 + msr csselr_el1, xzr // select cache level 0 in csselr + dsb sy // barrier to complete final cache operation + isb +exit: + ret +endfunc do_dcsw_op + +dcsw_loop_table: + dcsw_loop isw + dcsw_loop cisw + dcsw_loop csw + + +func dcsw_op_louis + dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT +endfunc dcsw_op_louis + + +func dcsw_op_all + dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT +endfunc dcsw_op_all + + /* --------------------------------------------------------------- + * Helper macro for data cache operations by set/way for the + * level specified + * --------------------------------------------------------------- + */ + .macro dcsw_op_level level + mrs x9, clidr_el1 + mov x3, \level + sub x10, x3, #2 + b do_dcsw_op + .endm + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 1 cache + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level1 + dcsw_op_level #(1 << LEVEL_SHIFT) +endfunc dcsw_op_level1 + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 2 cache + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level2 + dcsw_op_level #(2 << LEVEL_SHIFT) +endfunc dcsw_op_level2 + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 3 cache + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level3 + dcsw_op_level #(3 << LEVEL_SHIFT) +endfunc dcsw_op_level3 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/aarch64/misc_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/lib/aarch64/misc_helpers.S new file mode 100644 index 0000000..e7c246e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/aarch64/misc_helpers.S @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .globl get_afflvl_shift + .globl mpidr_mask_lower_afflvls + .globl eret + .globl smc + + .globl zeromem16 + .globl memcpy16 + + .globl disable_mmu_el3 + .globl disable_mmu_icache_el3 + +#if SUPPORT_VFP + .globl enable_vfp +#endif + +func get_afflvl_shift + cmp x0, #3 + cinc x0, x0, eq + mov x1, #MPIDR_AFFLVL_SHIFT + lsl x0, x0, x1 + ret +endfunc get_afflvl_shift + +func mpidr_mask_lower_afflvls + cmp x1, #3 + cinc x1, x1, eq + mov x2, #MPIDR_AFFLVL_SHIFT + lsl x2, x1, x2 + lsr x0, x0, x2 + lsl x0, x0, x2 + ret +endfunc mpidr_mask_lower_afflvls + + +func eret + eret +endfunc eret + + +func smc + smc #0 +endfunc smc + +/* ----------------------------------------------------------------------- + * void zeromem16(void *mem, unsigned int length); + * + * Initialise a memory region to 0. + * The memory address must be 16-byte aligned. + * ----------------------------------------------------------------------- + */ +func zeromem16 +#if ASM_ASSERTION + tst x0, #0xf + ASM_ASSERT(eq) +#endif + add x2, x0, x1 +/* zero 16 bytes at a time */ +z_loop16: + sub x3, x2, x0 + cmp x3, #16 + b.lt z_loop1 + stp xzr, xzr, [x0], #16 + b z_loop16 +/* zero byte per byte */ +z_loop1: + cmp x0, x2 + b.eq z_end + strb wzr, [x0], #1 + b z_loop1 +z_end: + ret +endfunc zeromem16 + + +/* -------------------------------------------------------------------------- + * void memcpy16(void *dest, const void *src, unsigned int length) + * + * Copy length bytes from memory area src to memory area dest. + * The memory areas should not overlap. + * Destination and source addresses must be 16-byte aligned. + * -------------------------------------------------------------------------- + */ +func memcpy16 +#if ASM_ASSERTION + orr x3, x0, x1 + tst x3, #0xf + ASM_ASSERT(eq) +#endif +/* copy 16 bytes at a time */ +m_loop16: + cmp x2, #16 + b.lt m_loop1 + ldp x3, x4, [x1], #16 + stp x3, x4, [x0], #16 + sub x2, x2, #16 + b m_loop16 +/* copy byte per byte */ +m_loop1: + cbz x2, m_end + ldrb w3, [x1], #1 + strb w3, [x0], #1 + subs x2, x2, #1 + b.ne m_loop1 +m_end: + ret +endfunc memcpy16 + +/* --------------------------------------------------------------------------- + * Disable the MMU at EL3 + * --------------------------------------------------------------------------- + */ + +func disable_mmu_el3 + mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT) +do_disable_mmu: + mrs x0, sctlr_el3 + bic x0, x0, x1 + msr sctlr_el3, x0 + isb // ensure MMU is off + dsb sy + ret +endfunc disable_mmu_el3 + + +func disable_mmu_icache_el3 + mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) + b do_disable_mmu +endfunc disable_mmu_icache_el3 + +/* --------------------------------------------------------------------------- + * Enable the use of VFP at EL3 + * --------------------------------------------------------------------------- + */ +#if SUPPORT_VFP +func enable_vfp + mrs x0, cpacr_el1 + orr x0, x0, #CPACR_VFP_BITS + msr cpacr_el1, x0 + mrs x0, cptr_el3 + mov x1, #AARCH64_CPTR_TFP + bic x0, x0, x1 + msr cptr_el3, x0 + isb + ret +endfunc enable_vfp +#endif diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/aarch64/xlat_helpers.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/aarch64/xlat_helpers.c new file mode 100644 index 0000000..d401ffc --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/aarch64/xlat_helpers.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/******************************************************************************* + * Helper to create a level 1/2 table descriptor which points to a level 2/3 + * table. + ******************************************************************************/ +unsigned long create_table_desc(unsigned long *next_table_ptr) +{ + unsigned long desc = (unsigned long) next_table_ptr; + + /* Clear the last 12 bits */ + desc >>= FOUR_KB_SHIFT; + desc <<= FOUR_KB_SHIFT; + + desc |= TABLE_DESC; + + return desc; +} + +/******************************************************************************* + * Helper to create a level 1/2/3 block descriptor which maps the va to addr + ******************************************************************************/ +unsigned long create_block_desc(unsigned long desc, + unsigned long addr, + unsigned int level) +{ + switch (level) { + case LEVEL1: + desc |= (addr << FIRST_LEVEL_DESC_N) | BLOCK_DESC; + break; + case LEVEL2: + desc |= (addr << SECOND_LEVEL_DESC_N) | BLOCK_DESC; + break; + case LEVEL3: + desc |= (addr << THIRD_LEVEL_DESC_N) | TABLE_DESC; + break; + default: + assert(0); + } + + return desc; +} + +/******************************************************************************* + * Helper to create a level 1/2/3 block descriptor which maps the va to output_ + * addr with Device nGnRE attributes. + ******************************************************************************/ +unsigned long create_device_block(unsigned long output_addr, + unsigned int level, + unsigned int ns) +{ + unsigned long upper_attrs, lower_attrs, desc; + + lower_attrs = LOWER_ATTRS(ACCESS_FLAG | OSH | AP_RW); + lower_attrs |= LOWER_ATTRS(ns | ATTR_DEVICE_INDEX); + upper_attrs = UPPER_ATTRS(XN); + desc = upper_attrs | lower_attrs; + + return create_block_desc(desc, output_addr, level); +} + +/******************************************************************************* + * Helper to create a level 1/2/3 block descriptor which maps the va to output_ + * addr with inner-shareable normal wbwa read-only memory attributes. + ******************************************************************************/ +unsigned long create_romem_block(unsigned long output_addr, + unsigned int level, + unsigned int ns) +{ + unsigned long upper_attrs, lower_attrs, desc; + + lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RO); + lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX); + upper_attrs = UPPER_ATTRS(0ull); + desc = upper_attrs | lower_attrs; + + return create_block_desc(desc, output_addr, level); +} + +/******************************************************************************* + * Helper to create a level 1/2/3 block descriptor which maps the va to output_ + * addr with inner-shareable normal wbwa read-write memory attributes. + ******************************************************************************/ +unsigned long create_rwmem_block(unsigned long output_addr, + unsigned int level, + unsigned int ns) +{ + unsigned long upper_attrs, lower_attrs, desc; + + lower_attrs = LOWER_ATTRS(ACCESS_FLAG | ISH | AP_RW); + lower_attrs |= LOWER_ATTRS(ns | ATTR_IWBWA_OWBWA_NTR_INDEX); + upper_attrs = UPPER_ATTRS(XN); + desc = upper_attrs | lower_attrs; + + return create_block_desc(desc, output_addr, level); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/aarch64/xlat_tables.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/aarch64/xlat_tables.c new file mode 100644 index 0000000..fa1a03d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/aarch64/xlat_tables.c @@ -0,0 +1,352 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +#ifndef DEBUG_XLAT_TABLE +#define DEBUG_XLAT_TABLE 0 +#endif + +#if DEBUG_XLAT_TABLE +#define debug_print(...) printf(__VA_ARGS__) +#else +#define debug_print(...) ((void)0) +#endif + +CASSERT(ADDR_SPACE_SIZE > 0, assert_valid_addr_space_size); + +#define UNSET_DESC ~0ul + +#define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) + +static uint64_t l1_xlation_table[NUM_L1_ENTRIES] +__aligned(NUM_L1_ENTRIES * sizeof(uint64_t)); + +static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] +__aligned(XLAT_TABLE_SIZE) __attribute__((section("xlat_table"))); + +static unsigned next_xlat; +static unsigned long max_pa; +static unsigned long max_va; +static unsigned long tcr_ps_bits; + +/* + * Array of all memory regions stored in order of ascending base address. + * The list is terminated by the first entry with size == 0. + */ +static mmap_region_t mmap[MAX_MMAP_REGIONS + 1]; + + +static void print_mmap(void) +{ +#if DEBUG_XLAT_TABLE + debug_print("mmap:\n"); + mmap_region_t *mm = mmap; + while (mm->size) { + debug_print(" %010lx %010lx %10lx %x\n", mm->base_va, + mm->base_pa, mm->size, mm->attr); + ++mm; + }; + debug_print("\n"); +#endif +} + +void mmap_add_region(unsigned long base_pa, unsigned long base_va, + unsigned long size, unsigned attr) +{ + mmap_region_t *mm = mmap; + mmap_region_t *mm_last = mm + ARRAY_SIZE(mmap) - 1; + unsigned long pa_end = base_pa + size - 1; + unsigned long va_end = base_va + size - 1; + + assert(IS_PAGE_ALIGNED(base_pa)); + assert(IS_PAGE_ALIGNED(base_va)); + assert(IS_PAGE_ALIGNED(size)); + + if (!size) + return; + + /* Find correct place in mmap to insert new region */ + while (mm->base_va < base_va && mm->size) + ++mm; + + /* Make room for new region by moving other regions up by one place */ + memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm); + + /* Check we haven't lost the empty sentinal from the end of the array */ + assert(mm_last->size == 0); + + mm->base_pa = base_pa; + mm->base_va = base_va; + mm->size = size; + mm->attr = attr; + + if (pa_end > max_pa) + max_pa = pa_end; + if (va_end > max_va) + max_va = va_end; +} + +void mmap_add(const mmap_region_t *mm) +{ + while (mm->size) { + mmap_add_region(mm->base_pa, mm->base_va, mm->size, mm->attr); + ++mm; + } +} + +static unsigned long mmap_desc(unsigned attr, unsigned long addr_pa, + unsigned level) +{ + unsigned long desc = addr_pa; + + desc |= level == 3 ? TABLE_DESC : BLOCK_DESC; + + desc |= attr & MT_NS ? LOWER_ATTRS(NS) : 0; + + desc |= attr & MT_RW ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO); + + desc |= LOWER_ATTRS(ACCESS_FLAG); + + if (attr & MT_MEMORY) { + desc |= LOWER_ATTRS(ATTR_IWBWA_OWBWA_NTR_INDEX | ISH); + if (attr & MT_RW) + desc |= UPPER_ATTRS(XN); + } else { + desc |= LOWER_ATTRS(ATTR_DEVICE_INDEX | OSH); + desc |= UPPER_ATTRS(XN); + } + + debug_print(attr & MT_MEMORY ? "MEM" : "DEV"); + debug_print(attr & MT_RW ? "-RW" : "-RO"); + debug_print(attr & MT_NS ? "-NS" : "-S"); + + return desc; +} + +static int mmap_region_attr(mmap_region_t *mm, unsigned long base_va, + unsigned long size) +{ + int attr = mm->attr; + + for (;;) { + ++mm; + + if (!mm->size) + return attr; /* Reached end of list */ + + if (mm->base_va >= base_va + size) + return attr; /* Next region is after area so end */ + + if (mm->base_va + mm->size <= base_va) + continue; /* Next region has already been overtaken */ + + if ((mm->attr & attr) == attr) + continue; /* Region doesn't override attribs so skip */ + + attr &= mm->attr; + + if (mm->base_va > base_va || + mm->base_va + mm->size < base_va + size) + return -1; /* Region doesn't fully cover our area */ + } +} + +static mmap_region_t *init_xlation_table(mmap_region_t *mm, + unsigned long base_va, + unsigned long *table, unsigned level) +{ + unsigned level_size_shift = L1_XLAT_ADDRESS_SHIFT - (level - 1) * + XLAT_TABLE_ENTRIES_SHIFT; + unsigned level_size = 1 << level_size_shift; + unsigned long level_index_mask = XLAT_TABLE_ENTRIES_MASK << level_size_shift; + + assert(level <= 3); + + debug_print("New xlat table:\n"); + + do { + unsigned long desc = UNSET_DESC; + + if (mm->base_va + mm->size <= base_va) { + /* Area now after the region so skip it */ + ++mm; + continue; + } + + debug_print(" %010lx %8lx " + 6 - 2 * level, base_va, + level_size); + + if (mm->base_va >= base_va + level_size) { + /* Next region is after area so nothing to map yet */ + desc = INVALID_DESC; + } else if (mm->base_va <= base_va && mm->base_va + mm->size >= + base_va + level_size) { + /* Next region covers all of area */ + int attr = mmap_region_attr(mm, base_va, level_size); + if (attr >= 0) + desc = mmap_desc(attr, + base_va - mm->base_va + mm->base_pa, + level); + } + /* else Next region only partially covers area, so need */ + + if (desc == UNSET_DESC) { + /* Area not covered by a region so need finer table */ + unsigned long *new_table = xlat_tables[next_xlat++]; + assert(next_xlat <= MAX_XLAT_TABLES); + desc = TABLE_DESC | (unsigned long)new_table; + + /* Recurse to fill in new table */ + mm = init_xlation_table(mm, base_va, + new_table, level+1); + } + + debug_print("\n"); + + *table++ = desc; + base_va += level_size; + } while (mm->size && (base_va & level_index_mask)); + + return mm; +} + +static unsigned int calc_physical_addr_size_bits(unsigned long max_addr) +{ + /* Physical address can't exceed 48 bits */ + assert((max_addr & ADDR_MASK_48_TO_63) == 0); + + /* 48 bits address */ + if (max_addr & ADDR_MASK_44_TO_47) + return TCR_PS_BITS_256TB; + + /* 44 bits address */ + if (max_addr & ADDR_MASK_42_TO_43) + return TCR_PS_BITS_16TB; + + /* 42 bits address */ + if (max_addr & ADDR_MASK_40_TO_41) + return TCR_PS_BITS_4TB; + + /* 40 bits address */ + if (max_addr & ADDR_MASK_36_TO_39) + return TCR_PS_BITS_1TB; + + /* 36 bits address */ + if (max_addr & ADDR_MASK_32_TO_35) + return TCR_PS_BITS_64GB; + + return TCR_PS_BITS_4GB; +} + +void init_xlat_tables(void) +{ + print_mmap(); + init_xlation_table(mmap, 0, l1_xlation_table, 1); + tcr_ps_bits = calc_physical_addr_size_bits(max_pa); + assert(max_va < ADDR_SPACE_SIZE); +} + +/******************************************************************************* + * Macro generating the code for the function enabling the MMU in the given + * exception level, assuming that the pagetables have already been created. + * + * _el: Exception level at which the function will run + * _tcr_extra: Extra bits to set in the TCR register. This mask will + * be OR'ed with the default TCR value. + * _tlbi_fct: Function to invalidate the TLBs at the current + * exception level + ******************************************************************************/ +#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \ + void enable_mmu_el##_el(uint32_t flags) \ + { \ + uint64_t mair, tcr, ttbr; \ + uint32_t sctlr; \ + \ + assert(IS_IN_EL(_el)); \ + assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \ + \ + /* Set attributes in the right indices of the MAIR */ \ + mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \ + mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \ + ATTR_IWBWA_OWBWA_NTR_INDEX); \ + write_mair_el##_el(mair); \ + \ + /* Invalidate TLBs at the current exception level */ \ + _tlbi_fct(); \ + \ + /* Set TCR bits as well. */ \ + /* Inner & outer WBWA & shareable + T0SZ = 32 */ \ + tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \ + TCR_RGN_INNER_WBA | \ + (64 - __builtin_ctzl(ADDR_SPACE_SIZE)); \ + tcr |= _tcr_extra; \ + write_tcr_el##_el(tcr); \ + \ + /* Set TTBR bits as well */ \ + ttbr = (uint64_t) l1_xlation_table; \ + write_ttbr0_el##_el(ttbr); \ + \ + /* Ensure all translation table writes have drained */ \ + /* into memory, the TLB invalidation is complete, */ \ + /* and translation register writes are committed */ \ + /* before enabling the MMU */ \ + dsb(); \ + isb(); \ + \ + sctlr = read_sctlr_el##_el(); \ + sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \ + \ + if (flags & DISABLE_DCACHE) \ + sctlr &= ~SCTLR_C_BIT; \ + else \ + sctlr |= SCTLR_C_BIT; \ + \ + write_sctlr_el##_el(sctlr); \ + \ + /* Ensure the MMU enable takes effect immediately */ \ + isb(); \ + } + +/* Define EL1 and EL3 variants of the function enabling the MMU */ +DEFINE_ENABLE_MMU_EL(1, + (tcr_ps_bits << TCR_EL1_IPS_SHIFT), + tlbivmalle1) +DEFINE_ENABLE_MMU_EL(3, + TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT), + tlbialle3) diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/aem_generic.S b/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/aem_generic.S new file mode 100644 index 0000000..0ab5253 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/aem_generic.S @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include + +func aem_generic_core_pwr_dwn + /* --------------------------------------------- + * Disable the Data Cache. + * --------------------------------------------- + */ + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + + mov x0, #DCCISW + + /* --------------------------------------------- + * Flush L1 cache to PoU. + * --------------------------------------------- + */ + b dcsw_op_louis +endfunc aem_generic_core_pwr_dwn + + +func aem_generic_cluster_pwr_dwn + /* --------------------------------------------- + * Disable the Data Cache. + * --------------------------------------------- + */ + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + + /* --------------------------------------------- + * Flush L1 and L2 caches to PoC. + * --------------------------------------------- + */ + mov x0, #DCCISW + b dcsw_op_all +endfunc aem_generic_cluster_pwr_dwn + + /* --------------------------------------------- + * This function provides cpu specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.aem_generic_regs, "aS" +aem_generic_regs: /* The ascii list of register names to be reported */ + .asciz "" /* no registers to report */ + +func aem_generic_cpu_reg_dump + adr x6, aem_generic_regs + ret +endfunc aem_generic_cpu_reg_dump + + +/* cpu_ops for Base AEM FVP */ +declare_cpu_ops aem_generic, BASE_AEM_MIDR, 1 + +/* cpu_ops for Foundation FVP */ +declare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, 1 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/cortex_a53.S b/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/cortex_a53.S new file mode 100644 index 0000000..e4b94e8 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/cortex_a53.S @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include + + /* --------------------------------------------- + * Disable L1 data cache and unified L2 cache + * --------------------------------------------- + */ +func cortex_a53_disable_dcache + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + ret +endfunc cortex_a53_disable_dcache + + /* --------------------------------------------- + * Disable intra-cluster coherency + * --------------------------------------------- + */ +func cortex_a53_disable_smp + mrs x0, CPUECTLR_EL1 + bic x0, x0, #CPUECTLR_SMP_BIT + msr CPUECTLR_EL1, x0 + isb + dsb sy + ret +endfunc cortex_a53_disable_smp + + /* -------------------------------------------------- + * Errata Workaround for Cortex A53 Errata #826319. + * This applies only to revision <= r0p2 of Cortex A53. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * -------------------------------------------------- + */ +func errata_a53_826319_wa + /* + * Compare x0 against revision r0p2 + */ + cmp x0, #2 + b.ls apply_826319 +#if DEBUG + b print_revision_warning +#else + ret +#endif +apply_826319: + mrs x1, L2ACTLR_EL1 + bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN + orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH + msr L2ACTLR_EL1, x1 + ret +endfunc errata_a53_826319_wa + + /* -------------------------------------------------- + * Errata Workaround for Cortex A53 Errata #836870. + * This applies only to revision <= r0p3 of Cortex A53. + * From r0p4 and onwards, this errata is enabled by + * default. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * -------------------------------------------------- + */ +func errata_a53_836870_wa + /* + * Compare x0 against revision r0p3 + */ + cmp x0, #3 + b.ls apply_836870 +#if DEBUG + b print_revision_warning +#else + ret +#endif +apply_836870: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_DTAH + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a53_836870_wa + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A53. + * Clobbers: x0-x5, x15, x19, x30 + * ------------------------------------------------- + */ +func cortex_a53_reset_func + mov x19, x30 + mrs x0, midr_el1 + + /* + * Extract the variant[20:23] and revision[0:3] from x0 + * and pack it in x15[0:7] as variant[4:7] and revision[0:3]. + * First extract x0[16:23] to x15[0:7] and zero fill the rest. + * Then extract x0[0:3] into x15[0:3] retaining other bits. + */ + ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), \ + #(MIDR_REV_BITS + MIDR_VAR_BITS) + bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS + +#if ERRATA_A53_826319 + mov x0, x15 + bl errata_a53_826319_wa +#endif + +#if ERRATA_A53_836870 + mov x0, x15 + bl errata_a53_836870_wa +#endif + + /* --------------------------------------------- + * As a bare minimum enable the SMP bit if it is + * not already set. + * --------------------------------------------- + */ + mrs x0, CPUECTLR_EL1 + tst x0, #CPUECTLR_SMP_BIT + b.ne skip_smp_setup + orr x0, x0, #CPUECTLR_SMP_BIT + msr CPUECTLR_EL1, x0 +skip_smp_setup: + isb + ret x19 +endfunc cortex_a53_reset_func + +func cortex_a53_core_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a53_disable_dcache + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a53_disable_smp +endfunc cortex_a53_core_pwr_dwn + +func cortex_a53_cluster_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a53_disable_dcache + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Disable the optional ACP. + * --------------------------------------------- + */ + bl plat_disable_acp + + /* --------------------------------------------- + * Flush L2 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level2 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a53_disable_smp +endfunc cortex_a53_cluster_pwr_dwn + + /* --------------------------------------------- + * This function provides cortex_a53 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a53_regs, "aS" +cortex_a53_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a53_cpu_reg_dump + adr x6, cortex_a53_regs + mrs x8, CPUECTLR_EL1 + ret +endfunc cortex_a53_cpu_reg_dump + +declare_cpu_ops cortex_a53, CORTEX_A53_MIDR diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/cortex_a57.S b/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/cortex_a57.S new file mode 100644 index 0000000..05799d6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/cortex_a57.S @@ -0,0 +1,313 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include + + /* --------------------------------------------- + * Disable L1 data cache and unified L2 cache + * --------------------------------------------- + */ +func cortex_a57_disable_dcache + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + ret +endfunc cortex_a57_disable_dcache + + /* --------------------------------------------- + * Disable all types of L2 prefetches. + * --------------------------------------------- + */ +func cortex_a57_disable_l2_prefetch + mrs x0, CPUECTLR_EL1 + orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT + mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK + orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK + bic x0, x0, x1 + msr CPUECTLR_EL1, x0 + isb + dsb ish + ret +endfunc cortex_a57_disable_l2_prefetch + + /* --------------------------------------------- + * Disable intra-cluster coherency + * --------------------------------------------- + */ +func cortex_a57_disable_smp + mrs x0, CPUECTLR_EL1 + bic x0, x0, #CPUECTLR_SMP_BIT + msr CPUECTLR_EL1, x0 + ret +endfunc cortex_a57_disable_smp + + /* --------------------------------------------- + * Disable debug interfaces + * --------------------------------------------- + */ +func cortex_a57_disable_ext_debug + mov x0, #1 + msr osdlr_el1, x0 + isb + dsb sy + ret +endfunc cortex_a57_disable_ext_debug + + /* -------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #806969. + * This applies only to revision r0p0 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * -------------------------------------------------- + */ +func errata_a57_806969_wa + /* + * Compare x0 against revision r0p0 + */ + cbz x0, apply_806969 +#if DEBUG + b print_revision_warning +#else + ret +#endif +apply_806969: + /* + * Test if errata has already been applied in an earlier + * invocation of the reset handler and does not need to + * be applied again. + */ + mrs x1, CPUACTLR_EL1 + tst x1, #CPUACTLR_NO_ALLOC_WBWA + b.ne skip_806969 + orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA + msr CPUACTLR_EL1, x1 +skip_806969: + ret +endfunc errata_a57_806969_wa + + + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #813420. + * This applies only to revision r0p0 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_813420_wa + /* + * Compare x0 against revision r0p0 + */ + cbz x0, apply_813420 +#if DEBUG + b print_revision_warning +#else + ret +#endif +apply_813420: + /* + * Test if errata has already been applied in an earlier + * invocation of the reset handler and does not need to + * be applied again. + */ + mrs x1, CPUACTLR_EL1 + tst x1, #CPUACTLR_DCC_AS_DCCI + b.ne skip_813420 + orr x1, x1, #CPUACTLR_DCC_AS_DCCI + msr CPUACTLR_EL1, x1 +skip_813420: + ret +endfunc errata_a57_813420_wa + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A57. + * Clobbers: x0-x5, x15, x19, x30 + * ------------------------------------------------- + */ +func cortex_a57_reset_func + mov x19, x30 + mrs x0, midr_el1 + + /* + * Extract the variant[20:23] and revision[0:3] from x0 + * and pack it in x15[0:7] as variant[4:7] and revision[0:3]. + * First extract x0[16:23] to x15[0:7] and zero fill the rest. + * Then extract x0[0:3] into x15[0:3] retaining other bits. + */ + ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), #(MIDR_REV_BITS + MIDR_VAR_BITS) + bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS + +#if ERRATA_A57_806969 + mov x0, x15 + bl errata_a57_806969_wa +#endif + +#if ERRATA_A57_813420 + mov x0, x15 + bl errata_a57_813420_wa +#endif + + /* --------------------------------------------- + * As a bare minimum enable the SMP bit if it is + * not already set. + * --------------------------------------------- + */ + mrs x0, CPUECTLR_EL1 + tst x0, #CPUECTLR_SMP_BIT + b.ne skip_smp_setup + orr x0, x0, #CPUECTLR_SMP_BIT + msr CPUECTLR_EL1, x0 +skip_smp_setup: + isb + ret x19 +endfunc cortex_a57_reset_func + + /* ---------------------------------------------------- + * The CPU Ops core power down function for Cortex-A57. + * ---------------------------------------------------- + */ +func cortex_a57_core_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a57_disable_dcache + + /* --------------------------------------------- + * Disable the L2 prefetches. + * --------------------------------------------- + */ + bl cortex_a57_disable_l2_prefetch + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + bl cortex_a57_disable_smp + + /* --------------------------------------------- + * Force the debug interfaces to be quiescent + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a57_disable_ext_debug +endfunc cortex_a57_core_pwr_dwn + + /* ------------------------------------------------------- + * The CPU Ops cluster power down function for Cortex-A57. + * ------------------------------------------------------- + */ +func cortex_a57_cluster_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a57_disable_dcache + + /* --------------------------------------------- + * Disable the L2 prefetches. + * --------------------------------------------- + */ + bl cortex_a57_disable_l2_prefetch + +#if !SKIP_A57_L1_FLUSH_PWR_DWN + /* ------------------------------------------------- + * Flush the L1 caches. + * ------------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 +#endif + /* --------------------------------------------- + * Disable the optional ACP. + * --------------------------------------------- + */ + bl plat_disable_acp + + /* ------------------------------------------------- + * Flush the L2 caches. + * ------------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level2 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + bl cortex_a57_disable_smp + + /* --------------------------------------------- + * Force the debug interfaces to be quiescent + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a57_disable_ext_debug +endfunc cortex_a57_cluster_pwr_dwn + + /* --------------------------------------------- + * This function provides cortex_a57 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a57_regs, "aS" +cortex_a57_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a57_cpu_reg_dump + adr x6, cortex_a57_regs + mrs x8, CPUECTLR_EL1 + ret +endfunc cortex_a57_cpu_reg_dump + + +declare_cpu_ops cortex_a57, CORTEX_A57_MIDR diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/cortex_a72.S b/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/cortex_a72.S new file mode 100644 index 0000000..eb37f2c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/cortex_a72.S @@ -0,0 +1,243 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include + + /* --------------------------------------------- + * Disable L1 data cache and unified L2 cache + * --------------------------------------------- + */ +func cortex_a72_disable_dcache + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + ret +endfunc cortex_a72_disable_dcache + + /* --------------------------------------------- + * Disable all types of L2 prefetches. + * --------------------------------------------- + */ +func cortex_a72_disable_l2_prefetch + mrs x0, CPUECTLR_EL1 + orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT + mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK + orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK + bic x0, x0, x1 + msr CPUECTLR_EL1, x0 + isb + ret +endfunc cortex_a72_disable_l2_prefetch + + /* --------------------------------------------- + * Disable the load-store hardware prefetcher. + * --------------------------------------------- + */ +func cortex_a72_disable_hw_prefetcher + mrs x0, CPUACTLR_EL1 + orr x0, x0, #CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH + msr CPUACTLR_EL1, x0 + isb + dsb ish + ret +endfunc cortex_a72_disable_hw_prefetcher + + /* --------------------------------------------- + * Disable intra-cluster coherency + * --------------------------------------------- + */ +func cortex_a72_disable_smp + mrs x0, CPUECTLR_EL1 + bic x0, x0, #CPUECTLR_SMP_BIT + msr CPUECTLR_EL1, x0 + ret +endfunc cortex_a72_disable_smp + + /* --------------------------------------------- + * Disable debug interfaces + * --------------------------------------------- + */ +func cortex_a72_disable_ext_debug + mov x0, #1 + msr osdlr_el1, x0 + isb + dsb sy + ret +endfunc cortex_a72_disable_ext_debug + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A72. + * ------------------------------------------------- + */ +func cortex_a72_reset_func + /* --------------------------------------------- + * As a bare minimum enable the SMP bit. + * --------------------------------------------- + */ + mrs x0, CPUECTLR_EL1 + orr x0, x0, #CPUECTLR_SMP_BIT + msr CPUECTLR_EL1, x0 + isb + ret +endfunc cortex_a72_reset_func + + /* ---------------------------------------------------- + * The CPU Ops core power down function for Cortex-A72. + * ---------------------------------------------------- + */ +func cortex_a72_core_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a72_disable_dcache + + /* --------------------------------------------- + * Disable the L2 prefetches. + * --------------------------------------------- + */ + bl cortex_a72_disable_l2_prefetch + + /* --------------------------------------------- + * Disable the load-store hardware prefetcher. + * --------------------------------------------- + */ + bl cortex_a72_disable_hw_prefetcher + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + bl cortex_a72_disable_smp + + /* --------------------------------------------- + * Force the debug interfaces to be quiescent + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a72_disable_ext_debug +endfunc cortex_a72_core_pwr_dwn + + /* ------------------------------------------------------- + * The CPU Ops cluster power down function for Cortex-A72. + * ------------------------------------------------------- + */ +func cortex_a72_cluster_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a72_disable_dcache + + /* --------------------------------------------- + * Disable the L2 prefetches. + * --------------------------------------------- + */ + bl cortex_a72_disable_l2_prefetch + + /* --------------------------------------------- + * Disable the load-store hardware prefetcher. + * --------------------------------------------- + */ + bl cortex_a72_disable_hw_prefetcher + +#if !SKIP_A72_L1_FLUSH_PWR_DWN + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 +#endif + + /* --------------------------------------------- + * Disable the optional ACP. + * --------------------------------------------- + */ + bl plat_disable_acp + + /* ------------------------------------------------- + * Flush the L2 caches. + * ------------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level2 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + bl cortex_a72_disable_smp + + /* --------------------------------------------- + * Force the debug interfaces to be quiescent + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a72_disable_ext_debug +endfunc cortex_a72_cluster_pwr_dwn + + /* --------------------------------------------- + * This function provides cortex_a72 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a72_regs, "aS" +cortex_a72_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a72_cpu_reg_dump + adr x6, cortex_a72_regs + mrs x8, CPUECTLR_EL1 + ret +endfunc cortex_a72_cpu_reg_dump + + +declare_cpu_ops cortex_a72, CORTEX_A72_MIDR diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/cpu_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/cpu_helpers.S new file mode 100644 index 0000000..e8a1392 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/cpu_helpers.S @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#if IMAGE_BL31 +#include +#endif + + /* Reset fn is needed in BL at reset vector */ +#if IMAGE_BL1 || IMAGE_BL31 + /* + * The reset handler common to all platforms. After a matching + * cpu_ops structure entry is found, the correponding reset_handler + * in the cpu_ops is invoked. + * Clobbers: x0 - x19, x30 + */ + .globl reset_handler +func reset_handler + mov x19, x30 + + /* The plat_reset_handler can clobber x0 - x18, x30 */ + bl plat_reset_handler + + /* Get the matching cpu_ops pointer */ + bl get_cpu_ops_ptr +#if ASM_ASSERTION + cmp x0, #0 + ASM_ASSERT(ne) +#endif + + /* Get the cpu_ops reset handler */ + ldr x2, [x0, #CPU_RESET_FUNC] + mov x30, x19 + cbz x2, 1f + + /* The cpu_ops reset handler can clobber x0 - x19, x30 */ + br x2 +1: + ret +endfunc reset_handler + +#endif /* IMAGE_BL1 || IMAGE_BL31 */ + +#if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */ + /* + * The prepare core power down function for all platforms. After + * the cpu_ops pointer is retrieved from cpu_data, the corresponding + * pwr_dwn_core in the cpu_ops is invoked. + */ + .globl prepare_core_pwr_dwn +func prepare_core_pwr_dwn + mrs x1, tpidr_el3 + ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR] +#if ASM_ASSERTION + cmp x0, #0 + ASM_ASSERT(ne) +#endif + + /* Get the cpu_ops core_pwr_dwn handler */ + ldr x1, [x0, #CPU_PWR_DWN_CORE] + br x1 +endfunc prepare_core_pwr_dwn + + /* + * The prepare cluster power down function for all platforms. After + * the cpu_ops pointer is retrieved from cpu_data, the corresponding + * pwr_dwn_cluster in the cpu_ops is invoked. + */ + .globl prepare_cluster_pwr_dwn +func prepare_cluster_pwr_dwn + mrs x1, tpidr_el3 + ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR] +#if ASM_ASSERTION + cmp x0, #0 + ASM_ASSERT(ne) +#endif + + /* Get the cpu_ops cluster_pwr_dwn handler */ + ldr x1, [x0, #CPU_PWR_DWN_CLUSTER] + br x1 +endfunc prepare_cluster_pwr_dwn + + + /* + * Initializes the cpu_ops_ptr if not already initialized + * in cpu_data. This can be called without a runtime stack, but may + * only be called after the MMU is enabled. + * clobbers: x0 - x6, x10 + */ + .globl init_cpu_ops +func init_cpu_ops + mrs x6, tpidr_el3 + ldr x0, [x6, #CPU_DATA_CPU_OPS_PTR] + cbnz x0, 1f + mov x10, x30 + bl get_cpu_ops_ptr +#if ASM_ASSERTION + cmp x0, #0 + ASM_ASSERT(ne) +#endif + str x0, [x6, #CPU_DATA_CPU_OPS_PTR]! + mov x30, x10 +1: + ret +endfunc init_cpu_ops +#endif /* IMAGE_BL31 */ + +#if IMAGE_BL31 && CRASH_REPORTING + /* + * The cpu specific registers which need to be reported in a crash + * are reported via cpu_ops cpu_reg_dump function. After a matching + * cpu_ops structure entry is found, the correponding cpu_reg_dump + * in the cpu_ops is invoked. + */ + .globl do_cpu_reg_dump +func do_cpu_reg_dump + mov x16, x30 + + /* Get the matching cpu_ops pointer */ + bl get_cpu_ops_ptr + cbz x0, 1f + + /* Get the cpu_ops cpu_reg_dump */ + ldr x2, [x0, #CPU_REG_DUMP] + cbz x2, 1f + blr x2 +1: + mov x30, x16 + ret +endfunc do_cpu_reg_dump +#endif + + /* + * The below function returns the cpu_ops structure matching the + * midr of the core. It reads the MIDR_EL1 and finds the matching + * entry in cpu_ops entries. Only the implementation and part number + * are used to match the entries. + * Return : + * x0 - The matching cpu_ops pointer on Success + * x0 - 0 on failure. + * Clobbers : x0 - x5 + */ + .globl get_cpu_ops_ptr +func get_cpu_ops_ptr + /* Get the cpu_ops start and end locations */ + adr x4, (__CPU_OPS_START__ + CPU_MIDR) + adr x5, (__CPU_OPS_END__ + CPU_MIDR) + + /* Initialize the return parameter */ + mov x0, #0 + + /* Read the MIDR_EL1 */ + mrs x2, midr_el1 + mov_imm x3, CPU_IMPL_PN_MASK + + /* Retain only the implementation and part number using mask */ + and w2, w2, w3 +1: + /* Check if we have reached end of list */ + cmp x4, x5 + b.eq error_exit + + /* load the midr from the cpu_ops */ + ldr x1, [x4], #CPU_OPS_SIZE + and w1, w1, w3 + + /* Check if midr matches to midr of this core */ + cmp w1, w2 + b.ne 1b + + /* Subtract the increment and offset to get the cpu-ops pointer */ + sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR) +error_exit: + ret +endfunc get_cpu_ops_ptr + +#if DEBUG + /* + * This function prints a warning message to the crash console + * if the CPU revision/part number does not match the errata + * workaround enabled in the build. + * Clobber: x30, x0 - x5 + */ +.section .rodata.rev_warn_str, "aS" +rev_warn_str: + .asciz "Warning: Skipping Errata workaround for non matching CPU revision number.\n" + + .globl print_revision_warning +func print_revision_warning + mov x5, x30 + /* Ensure the console is initialized */ + bl plat_crash_console_init + /* Check if the console is initialized */ + cbz x0, 1f + /* The console is initialized */ + adr x4, rev_warn_str + bl asm_print_str +1: + ret x5 +endfunc print_revision_warning +#endif + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/denver.S b/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/denver.S new file mode 100644 index 0000000..bce0573 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/aarch64/denver.S @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + + /* --------------------------------------------- + * Disable debug interfaces + * --------------------------------------------- + */ +func denver_disable_ext_debug + mov x0, #1 + msr osdlr_el1, x0 + isb + dsb sy + ret +endfunc denver_disable_ext_debug + + /* ---------------------------------------------------- + * Enable dynamic code optimizer (DCO) + * ---------------------------------------------------- + */ +func denver_enable_dco + mrs x0, mpidr_el1 + and x0, x0, #0xF + mov x1, #1 + lsl x1, x1, x0 + msr s3_0_c15_c0_2, x1 + isb + ret +endfunc denver_enable_dco + + /* ---------------------------------------------------- + * Disable dynamic code optimizer (DCO) + * ---------------------------------------------------- + */ +func denver_disable_dco + + /* turn off background work */ + mrs x0, mpidr_el1 + and x0, x0, #0xF + mov x1, #1 + lsl x1, x1, x0 + lsl x2, x1, #16 + msr s3_0_c15_c0_2, x2 + isb + + /* wait till the background work turns off */ +1: mrs x2, s3_0_c15_c0_2 + lsr x2, x2, #32 + and w2, w2, 0xFFFF + and x2, x2, x1 + cbnz x2, 1b + + ret +endfunc denver_disable_dco + + /* ------------------------------------------------- + * The CPU Ops reset function for Denver. + * ------------------------------------------------- + */ +func denver_reset_func + + mov x19, x30 + + /* ---------------------------------------------------- + * Enable dynamic code optimizer (DCO) + * ---------------------------------------------------- + */ + bl denver_enable_dco + + ret x19 +endfunc denver_reset_func + + /* ---------------------------------------------------- + * The CPU Ops core power down function for Denver. + * ---------------------------------------------------- + */ +func denver_core_pwr_dwn + + mov x19, x30 + + /* ---------------------------------------------------- + * We enter the 'core power gated with ARM state not + * retained' power state during CPU power down. We let + * DCO know that we expect to enter this power state + * by writing to the ACTLR_EL1 register. + * ---------------------------------------------------- + */ + mov x0, #DENVER_CPU_STATE_POWER_DOWN + msr actlr_el1, x0 + + /* --------------------------------------------- + * Force DCO to be quiescent + * --------------------------------------------- + */ + bl denver_disable_dco + + /* --------------------------------------------- + * Force the debug interfaces to be quiescent + * --------------------------------------------- + */ + bl denver_disable_ext_debug + + ret x19 +endfunc denver_core_pwr_dwn + + /* ------------------------------------------------------- + * The CPU Ops cluster power down function for Denver. + * ------------------------------------------------------- + */ +func denver_cluster_pwr_dwn + ret +endfunc denver_cluster_pwr_dwn + + /* --------------------------------------------- + * This function provides Denver specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.denver_regs, "aS" +denver_regs: /* The ascii list of register names to be reported */ + .asciz "actlr_el1", "" + +func denver_cpu_reg_dump + adr x6, denver_regs + mrs x8, ACTLR_EL1 + ret +endfunc denver_cpu_reg_dump + +declare_cpu_ops denver, DENVER_1_0_MIDR diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/cpu-ops.mk b/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/cpu-ops.mk new file mode 100644 index 0000000..a872360 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/cpus/cpu-ops.mk @@ -0,0 +1,74 @@ +# +# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# Cortex A57 specific optimisation to skip L1 cache flush when +# cluster is powered down. +SKIP_A57_L1_FLUSH_PWR_DWN ?=0 + +# Process SKIP_A57_L1_FLUSH_PWR_DWN flag +$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) +$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) + + +# CPU Errata Build flags. These should be enabled by the +# platform if the errata needs to be applied. + +# Flag to apply errata 826319 during reset. This errata applies only to +# revision <= r0p2 of the Cortex A53 cpu. +ERRATA_A53_826319 ?=0 + +# Flag to apply errata 836870 during reset. This errata applies only to +# revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this +# errata is enabled by default. +ERRATA_A53_836870 ?=0 + +# Flag to apply errata 806969 during reset. This errata applies only to +# revision r0p0 of the Cortex A57 cpu. +ERRATA_A57_806969 ?=0 + +# Flag to apply errata 813420 during reset. This errata applies only to +# revision r0p0 of the Cortex A57 cpu. +ERRATA_A57_813420 ?=0 + +# Process ERRATA_A53_826319 flag +$(eval $(call assert_boolean,ERRATA_A53_826319)) +$(eval $(call add_define,ERRATA_A53_826319)) + +# Process ERRATA_A53_836870 flag +$(eval $(call assert_boolean,ERRATA_A53_836870)) +$(eval $(call add_define,ERRATA_A53_836870)) + +# Process ERRATA_A57_806969 flag +$(eval $(call assert_boolean,ERRATA_A57_806969)) +$(eval $(call add_define,ERRATA_A57_806969)) + +# Process ERRATA_A57_813420 flag +$(eval $(call assert_boolean,ERRATA_A57_813420)) +$(eval $(call add_define,ERRATA_A57_813420)) diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/locks/bakery/bakery_lock_coherent.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/locks/bakery/bakery_lock_coherent.c new file mode 100644 index 0000000..f221222 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/locks/bakery/bakery_lock_coherent.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* + * Functions in this file implement Bakery Algorithm for mutual exclusion with the + * bakery lock data structures in coherent memory. + * + * ARM architecture offers a family of exclusive access instructions to + * efficiently implement mutual exclusion with hardware support. However, as + * well as depending on external hardware, the these instructions have defined + * behavior only on certain memory types (cacheable and Normal memory in + * particular; see ARMv8 Architecture Reference Manual section B2.10). Use cases + * in trusted firmware are such that mutual exclusion implementation cannot + * expect that accesses to the lock have the specific type required by the + * architecture for these primitives to function (for example, not all + * contenders may have address translation enabled). + * + * This implementation does not use mutual exclusion primitives. It expects + * memory regions where the locks reside to be fully ordered and coherent + * (either by disabling address translation, or by assigning proper attributes + * when translation is enabled). + * + * Note that the ARM architecture guarantees single-copy atomicity for aligned + * accesses regardless of status of address translation. + */ + +#define assert_bakery_entry_valid(entry, bakery) do { \ + assert(bakery); \ + assert(entry < BAKERY_LOCK_MAX_CPUS); \ +} while (0) + +/* Obtain a ticket for a given CPU */ +static unsigned int bakery_get_ticket(bakery_lock_t *bakery, unsigned int me) +{ + unsigned int my_ticket, their_ticket; + unsigned int they; + + /* Prevent recursive acquisition */ + assert(!bakery_ticket_number(bakery->lock_data[me])); + + /* + * Flag that we're busy getting our ticket. All CPUs are iterated in the + * order of their ordinal position to decide the maximum ticket value + * observed so far. Our priority is set to be greater than the maximum + * observed priority + * + * Note that it's possible that more than one contender gets the same + * ticket value. That's OK as the lock is acquired based on the priority + * value, not the ticket value alone. + */ + my_ticket = 0; + bakery->lock_data[me] = make_bakery_data(CHOOSING_TICKET, my_ticket); + for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { + their_ticket = bakery_ticket_number(bakery->lock_data[they]); + if (their_ticket > my_ticket) + my_ticket = their_ticket; + } + + /* + * Compute ticket; then signal to other contenders waiting for us to + * finish calculating our ticket value that we're done + */ + ++my_ticket; + bakery->lock_data[me] = make_bakery_data(CHOSEN_TICKET, my_ticket); + + return my_ticket; +} + + +/* + * Acquire bakery lock + * + * Contending CPUs need first obtain a non-zero ticket and then calculate + * priority value. A contending CPU iterate over all other CPUs in the platform, + * which may be contending for the same lock, in the order of their ordinal + * position (CPU0, CPU1 and so on). A non-contending CPU will have its ticket + * (and priority) value as 0. The contending CPU compares its priority with that + * of others'. The CPU with the highest priority (lowest numerical value) + * acquires the lock + */ +void bakery_lock_get(bakery_lock_t *bakery) +{ + unsigned int they, me; + unsigned int my_ticket, my_prio, their_ticket; + unsigned int their_bakery_data; + + me = plat_my_core_pos(); + + assert_bakery_entry_valid(me, bakery); + + /* Get a ticket */ + my_ticket = bakery_get_ticket(bakery, me); + + /* + * Now that we got our ticket, compute our priority value, then compare + * with that of others, and proceed to acquire the lock + */ + my_prio = PRIORITY(my_ticket, me); + for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { + if (me == they) + continue; + + /* Wait for the contender to get their ticket */ + do { + their_bakery_data = bakery->lock_data[they]; + } while (bakery_is_choosing(their_bakery_data)); + + /* + * If the other party is a contender, they'll have non-zero + * (valid) ticket value. If they do, compare priorities + */ + their_ticket = bakery_ticket_number(their_bakery_data); + if (their_ticket && (PRIORITY(their_ticket, they) < my_prio)) { + /* + * They have higher priority (lower value). Wait for + * their ticket value to change (either release the lock + * to have it dropped to 0; or drop and probably content + * again for the same lock to have an even higher value) + */ + do { + wfe(); + } while (their_ticket == + bakery_ticket_number(bakery->lock_data[they])); + } + } + /* Lock acquired */ +} + + +/* Release the lock and signal contenders */ +void bakery_lock_release(bakery_lock_t *bakery) +{ + unsigned int me = plat_my_core_pos(); + + assert_bakery_entry_valid(me, bakery); + assert(bakery_ticket_number(bakery->lock_data[me])); + + /* + * Release lock by resetting ticket. Then signal other + * waiting contenders + */ + bakery->lock_data[me] = 0; + dsb(); + sev(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/locks/bakery/bakery_lock_normal.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/locks/bakery/bakery_lock_normal.c new file mode 100644 index 0000000..45b870b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/locks/bakery/bakery_lock_normal.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* + * Functions in this file implement Bakery Algorithm for mutual exclusion with the + * bakery lock data structures in cacheable and Normal memory. + * + * ARM architecture offers a family of exclusive access instructions to + * efficiently implement mutual exclusion with hardware support. However, as + * well as depending on external hardware, these instructions have defined + * behavior only on certain memory types (cacheable and Normal memory in + * particular; see ARMv8 Architecture Reference Manual section B2.10). Use cases + * in trusted firmware are such that mutual exclusion implementation cannot + * expect that accesses to the lock have the specific type required by the + * architecture for these primitives to function (for example, not all + * contenders may have address translation enabled). + * + * This implementation does not use mutual exclusion primitives. It expects + * memory regions where the locks reside to be cacheable and Normal. + * + * Note that the ARM architecture guarantees single-copy atomicity for aligned + * accesses regardless of status of address translation. + */ + +#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE +/* + * Verify that the platform defined value for the per-cpu space for bakery locks is + * a multiple of the cache line size, to prevent multiple CPUs writing to the same + * bakery lock cache line + * + * Using this value, if provided, rather than the linker generated value results in + * more efficient code + */ +CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \ + PLAT_PERCPU_BAKERY_LOCK_SIZE_not_cacheline_multiple); +#define PERCPU_BAKERY_LOCK_SIZE (PLAT_PERCPU_BAKERY_LOCK_SIZE) +#else +/* + * Use the linker defined symbol which has evaluated the size reqiurement. + * This is not as efficient as using a platform defined constant + */ +extern void *__PERCPU_BAKERY_LOCK_SIZE__; +#define PERCPU_BAKERY_LOCK_SIZE ((uintptr_t)&__PERCPU_BAKERY_LOCK_SIZE__) +#endif + +#define get_bakery_info(cpu_ix, lock) \ + (bakery_info_t *)((uintptr_t)lock + cpu_ix * PERCPU_BAKERY_LOCK_SIZE) + +#define write_cache_op(addr, cached) \ + do { \ + (cached ? dccvac((uint64_t)addr) :\ + dcivac((uint64_t)addr));\ + dsbish();\ + } while (0) + +#define read_cache_op(addr, cached) if (cached) \ + dccivac((uint64_t)addr) + +static unsigned int bakery_get_ticket(bakery_lock_t *lock, + unsigned int me, int is_cached) +{ + unsigned int my_ticket, their_ticket; + unsigned int they; + bakery_info_t *my_bakery_info, *their_bakery_info; + + /* + * Obtain a reference to the bakery information for this cpu and ensure + * it is not NULL. + */ + my_bakery_info = get_bakery_info(me, lock); + assert(my_bakery_info); + + /* + * Prevent recursive acquisition. + * Since lock data is written to and cleaned by the owning cpu, it + * doesn't require any cache operations prior to reading the lock data. + */ + assert(!bakery_ticket_number(my_bakery_info->lock_data)); + + /* + * Tell other contenders that we are through the bakery doorway i.e. + * going to allocate a ticket for this cpu. + */ + my_ticket = 0; + my_bakery_info->lock_data = make_bakery_data(CHOOSING_TICKET, my_ticket); + + write_cache_op(my_bakery_info, is_cached); + + /* + * Iterate through the bakery information of each contender to allocate + * the highest ticket number for this cpu. + */ + for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { + if (me == they) + continue; + + /* + * Get a reference to the other contender's bakery info and + * ensure that a stale copy is not read. + */ + their_bakery_info = get_bakery_info(they, lock); + assert(their_bakery_info); + + read_cache_op(their_bakery_info, is_cached); + + /* + * Update this cpu's ticket number if a higher ticket number is + * seen + */ + their_ticket = bakery_ticket_number(their_bakery_info->lock_data); + if (their_ticket > my_ticket) + my_ticket = their_ticket; + } + + /* + * Compute ticket; then signal to other contenders waiting for us to + * finish calculating our ticket value that we're done + */ + ++my_ticket; + my_bakery_info->lock_data = make_bakery_data(CHOSEN_TICKET, my_ticket); + + write_cache_op(my_bakery_info, is_cached); + + return my_ticket; +} + +void bakery_lock_get(bakery_lock_t *lock) +{ + unsigned int they, me, is_cached; + unsigned int my_ticket, my_prio, their_ticket; + bakery_info_t *their_bakery_info; + unsigned int their_bakery_data; + + me = plat_my_core_pos(); + + is_cached = read_sctlr_el3() & SCTLR_C_BIT; + + /* Get a ticket */ + my_ticket = bakery_get_ticket(lock, me, is_cached); + + /* + * Now that we got our ticket, compute our priority value, then compare + * with that of others, and proceed to acquire the lock + */ + my_prio = PRIORITY(my_ticket, me); + for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { + if (me == they) + continue; + + /* + * Get a reference to the other contender's bakery info and + * ensure that a stale copy is not read. + */ + their_bakery_info = get_bakery_info(they, lock); + assert(their_bakery_info); + + /* Wait for the contender to get their ticket */ + do { + read_cache_op(their_bakery_info, is_cached); + their_bakery_data = their_bakery_info->lock_data; + } while (bakery_is_choosing(their_bakery_data)); + + /* + * If the other party is a contender, they'll have non-zero + * (valid) ticket value. If they do, compare priorities + */ + their_ticket = bakery_ticket_number(their_bakery_data); + if (their_ticket && (PRIORITY(their_ticket, they) < my_prio)) { + /* + * They have higher priority (lower value). Wait for + * their ticket value to change (either release the lock + * to have it dropped to 0; or drop and probably content + * again for the same lock to have an even higher value) + */ + do { + wfe(); + read_cache_op(their_bakery_info, is_cached); + } while (their_ticket + == bakery_ticket_number(their_bakery_info->lock_data)); + } + } + /* Lock acquired */ +} + +void bakery_lock_release(bakery_lock_t *lock) +{ + bakery_info_t *my_bakery_info; + unsigned int is_cached = read_sctlr_el3() & SCTLR_C_BIT; + + my_bakery_info = get_bakery_info(plat_my_core_pos(), lock); + assert(bakery_ticket_number(my_bakery_info->lock_data)); + + my_bakery_info->lock_data = 0; + write_cache_op(my_bakery_info, is_cached); + sev(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/locks/exclusive/spinlock.S b/IPL/SDK/v3m/src/Dummy_BL33/lib/locks/exclusive/spinlock.S new file mode 100644 index 0000000..772f14e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/locks/exclusive/spinlock.S @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + + .globl spin_lock + .globl spin_unlock + + +func spin_lock + mov w2, #1 + sevl +l1: wfe +l2: ldaxr w1, [x0] + cbnz w1, l1 + stxr w1, w2, [x0] + cbnz w1, l2 + ret +endfunc spin_lock + + +func spin_unlock + stlr wzr, [x0] + ret +endfunc spin_unlock diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/semihosting/aarch64/semihosting_call.S b/IPL/SDK/v3m/src/Dummy_BL33/lib/semihosting/aarch64/semihosting_call.S new file mode 100644 index 0000000..9fa8141 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/semihosting/aarch64/semihosting_call.S @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + + .globl semihosting_call + +func semihosting_call + hlt #0xf000 + ret +endfunc semihosting_call diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/semihosting/semihosting.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/semihosting/semihosting.c new file mode 100644 index 0000000..b4f53d2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/semihosting/semihosting.c @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#ifndef SEMIHOSTING_SUPPORTED +#define SEMIHOSTING_SUPPORTED 1 +#endif + +long semihosting_call(unsigned long operation, + void *system_block_address); + +typedef struct { + const char *file_name; + unsigned long mode; + size_t name_length; +} smh_file_open_block_t; + +typedef struct { + long handle; + uintptr_t buffer; + size_t length; +} smh_file_read_write_block_t; + +typedef struct { + long handle; + ssize_t location; +} smh_file_seek_block_t; + +typedef struct { + char *command_line; + size_t command_length; +} smh_system_block_t; + +long semihosting_connection_supported(void) +{ + return SEMIHOSTING_SUPPORTED; +} + +long semihosting_file_open(const char *file_name, size_t mode) +{ + smh_file_open_block_t open_block; + + open_block.file_name = file_name; + open_block.mode = mode; + open_block.name_length = strlen(file_name); + + return semihosting_call(SEMIHOSTING_SYS_OPEN, + (void *) &open_block); +} + +long semihosting_file_seek(long file_handle, ssize_t offset) +{ + smh_file_seek_block_t seek_block; + long result; + + seek_block.handle = file_handle; + seek_block.location = offset; + + result = semihosting_call(SEMIHOSTING_SYS_SEEK, + (void *) &seek_block); + + if (result) + result = semihosting_call(SEMIHOSTING_SYS_ERRNO, 0); + + return result; +} + +long semihosting_file_read(long file_handle, size_t *length, uintptr_t buffer) +{ + smh_file_read_write_block_t read_block; + long result = -EINVAL; + + if ((length == NULL) || (buffer == (uintptr_t)NULL)) + return result; + + read_block.handle = file_handle; + read_block.buffer = buffer; + read_block.length = *length; + + result = semihosting_call(SEMIHOSTING_SYS_READ, + (void *) &read_block); + + if (result == *length) { + return -EINVAL; + } else if (result < *length) { + *length -= result; + return 0; + } else + return result; +} + +long semihosting_file_write(long file_handle, + size_t *length, + const uintptr_t buffer) +{ + smh_file_read_write_block_t write_block; + long result = -EINVAL; + + if ((length == NULL) || (buffer == (uintptr_t)NULL)) + return -EINVAL; + + write_block.handle = file_handle; + write_block.buffer = (uintptr_t)buffer; /* cast away const */ + write_block.length = *length; + + result = semihosting_call(SEMIHOSTING_SYS_WRITE, + (void *) &write_block); + + *length = result; + + return (result == 0) ? 0 : -EINVAL; +} + +long semihosting_file_close(long file_handle) +{ + return semihosting_call(SEMIHOSTING_SYS_CLOSE, + (void *) &file_handle); +} + +long semihosting_file_length(long file_handle) +{ + return semihosting_call(SEMIHOSTING_SYS_FLEN, + (void *) &file_handle); +} + +char semihosting_read_char(void) +{ + return semihosting_call(SEMIHOSTING_SYS_READC, NULL); +} + +void semihosting_write_char(char character) +{ + semihosting_call(SEMIHOSTING_SYS_WRITEC, (void *) &character); +} + +void semihosting_write_string(char *string) +{ + semihosting_call(SEMIHOSTING_SYS_WRITE0, (void *) string); +} + +long semihosting_system(char *command_line) +{ + smh_system_block_t system_block; + + system_block.command_line = command_line; + system_block.command_length = strlen(command_line); + + return semihosting_call(SEMIHOSTING_SYS_SYSTEM, + (void *) &system_block); +} + +long semihosting_get_flen(const char *file_name) +{ + long file_handle; + size_t length; + + assert(semihosting_connection_supported()); + + file_handle = semihosting_file_open(file_name, FOPEN_MODE_RB); + if (file_handle == -1) + return file_handle; + + /* Find the length of the file */ + length = semihosting_file_length(file_handle); + + return semihosting_file_close(file_handle) ? -1 : length; +} + +long semihosting_download_file(const char *file_name, + size_t buf_size, + uintptr_t buf) +{ + long ret = -EINVAL; + size_t length; + long file_handle; + + /* Null pointer check */ + if (!buf) + return ret; + + assert(semihosting_connection_supported()); + + file_handle = semihosting_file_open(file_name, FOPEN_MODE_RB); + if (file_handle == -1) + return ret; + + /* Find the actual length of the file */ + length = semihosting_file_length(file_handle); + if (length == -1) + goto semihosting_fail; + + /* Signal error if we do not have enough space for the file */ + if (length > buf_size) + goto semihosting_fail; + + /* + * A successful read will return 0 in which case we pass back + * the actual number of bytes read. Else we pass a negative + * value indicating an error. + */ + ret = semihosting_file_read(file_handle, &length, buf); + if (ret) + goto semihosting_fail; + else + ret = length; + +semihosting_fail: + semihosting_file_close(file_handle); + return ret; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/abort.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/abort.c new file mode 100644 index 0000000..862bf9c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/abort.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* + * This is a basic implementation. This could be improved. + */ +void abort (void) +{ + ERROR("ABORT\n"); + panic(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/assert.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/assert.c new file mode 100644 index 0000000..90a1afe --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/assert.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* + * This is a basic implementation. This could be improved. + */ +void __assert (const char *function, const char *file, unsigned int line, + const char *assertion) +{ + tf_printf("ASSERT: %s <%d> : %s\n", function, line, assertion); + while(1); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/exit.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/exit.c new file mode 100644 index 0000000..3e77591 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/exit.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +void exit(int v) +{ + ERROR("EXIT\n"); + panic(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/mem.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/mem.c new file mode 100644 index 0000000..f1f335a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/mem.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include /* size_t */ + +/* + * Fill @count bytes of memory pointed to by @dst with @val + */ +void *memset(void *dst, int val, size_t count) +{ + char *ptr = dst; + + while (count--) + *ptr++ = val; + + return dst; +} + +/* + * Compare @len bytes of @s1 and @s2 + */ +int memcmp(const void *s1, const void *s2, size_t len) +{ + const char *s = s1; + const char *d = s2; + char dc; + char sc; + + while (len--) { + sc = *s++; + dc = *d++; + if (sc - dc) + return (sc - dc); + } + + return 0; +} + +/* + * Copy @len bytes from @src to @dst + */ +void *memcpy(void *dst, const void *src, size_t len) +{ + const char *s = src; + char *d = dst; + + while (len--) + *d++ = *s++; + + return dst; +} + +/* + * Move @len bytes from @src to @dst + */ +void *memmove(void *dst, const void *src, size_t len) +{ + /* + * The following test makes use of unsigned arithmetic overflow to + * more efficiently test the condition !(src <= dst && dst < str+len). + * It also avoids the situation where the more explicit test would give + * incorrect results were the calculation str+len to overflow (though + * that issue is probably moot as such usage is probably undefined + * behaviour and a bug anyway. + */ + if ((size_t)dst - (size_t)src >= len) { + /* destination not in source data, so can safely use memcpy */ + return memcpy(dst, src, len); + } else { + /* copy backwards... */ + const char *end = dst; + const char *s = (const char *)src + len; + char *d = (char *)dst + len; + while (d != end) + *--d = *--s; + } + return dst; +} + +/* + * Scan @len bytes of @src for value @c + */ +void *memchr(const void *src, int c, size_t len) +{ + const char *s = src; + + while (len--) { + if (*s == c) + return (void *) s; + s++; + } + + return NULL; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/printf.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/printf.c new file mode 100644 index 0000000..323ec0f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/printf.c @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/* Choose max of 128 chars for now. */ +#define PRINT_BUFFER_SIZE 128 +int printf(const char *fmt, ...) +{ + va_list args; + char buf[PRINT_BUFFER_SIZE]; + int count; + + va_start(args, fmt); + vsnprintf(buf, sizeof(buf) - 1, fmt, args); + va_end(args); + + /* Use putchar directly as 'puts()' adds a newline. */ + buf[PRINT_BUFFER_SIZE - 1] = '\0'; + count = 0; + while (buf[count]) + { + if (putchar(buf[count]) != EOF) { + count++; + } else { + count = EOF; + break; + } + } + + return count; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/putchar.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/putchar.c new file mode 100644 index 0000000..85e4fbd --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/putchar.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/* Putchar() should either return the character printed or EOF in case of error. + * Our current console_putc() function assumes success and returns the + * character. Write all other printing functions in terms of putchar(), if + * possible, so they all benefit when this is improved. + */ +int putchar(int c) +{ + int res; + if (console_putc((unsigned char)c) >= 0) + res = c; + else + res = EOF; + + return res; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/puts.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/puts.c new file mode 100644 index 0000000..ca88fc5 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/puts.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +int puts(const char *s) +{ + int count = 0; + while(*s) + { + if (putchar(*s++) != EOF) { + count++; + } else { + count = EOF; + break; + } + } + + /* According to the puts(3) manpage, the function should write a + * trailing newline. + */ + if ((count != EOF) && (putchar('\n') != EOF)) + count++; + else + count = EOF; + + return count; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/sscanf.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/sscanf.c new file mode 100644 index 0000000..e9f5c4a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/sscanf.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* + * TODO: This is not a real implementation of the sscanf() function. It just + * returns the number of expected arguments based on the number of '%' found + * in the format string. + */ +int +sscanf(const char *__restrict str, char const *__restrict fmt, ...) +{ + int ret = 0; + + while (*fmt != '\0') { + if (*fmt++ == '%') { + ret++; + } + } + + return ret; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/std.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/std.c new file mode 100644 index 0000000..5f6ef75 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/std.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +/* Include the various implemented functions */ +#include "abort.c" +#include "assert.c" +#include "exit.c" +#include "mem.c" +#include "printf.c" +#include "putchar.c" +#include "puts.c" +#include "sscanf.c" +#include "strchr.c" +#include "strcmp.c" +#include "strlen.c" +#include "strncmp.c" +#include "subr_prf.c" diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/strchr.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/strchr.c new file mode 100644 index 0000000..4247dcd --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/strchr.c @@ -0,0 +1,52 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Portions copyright (c) 2013-2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#include +#include +#include + +char * +strchr(const char *p, int ch) +{ + char c; + + c = ch; + for (;; ++p) { + if (*p == c) + return ((char *)p); + if (*p == '\0') + return (NULL); + } + /* NOTREACHED */ +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/strcmp.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/strcmp.c new file mode 100644 index 0000000..bb86e0f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/strcmp.c @@ -0,0 +1,66 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Portions copyright (c) 2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#include +#include +#include + +/* + * Compare strings. + */ +int +strcmp(const char *s1, const char *s2) +{ + while (*s1 == *s2++) + if (*s1++ == '\0') + return 0; + return *(const unsigned char *)s1 - *(const unsigned char *)(s2 - 1); +} + +int +strcasecmp(const char *s1, const char *s2) +{ + const unsigned char *us1 = (const unsigned char *)s1; + const unsigned char *us2 = (const unsigned char *)s2; + + while (tolower(*us1) == tolower(*us2)) { + if (*us1++ == '\0') + return 0; + us2++; + } + return tolower(*us1) - tolower(*us2); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/strlen.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/strlen.c new file mode 100644 index 0000000..23c3d39 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/strlen.c @@ -0,0 +1,44 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Portions copyright (c) 2009-2014, ARM Limited and Contributors. All rights reserved. + */ + +#include + +size_t +strlen(str) + const char *str; +{ + register const char *s; + + for (s = str; *s; ++s); + return(s - str); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/strncmp.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/strncmp.c new file mode 100644 index 0000000..f45f4a2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/strncmp.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 1989, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Portions copyright (c) 2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#include +#include + +int +strncmp(const char *s1, const char *s2, size_t n) +{ + + if (n == 0) + return 0; + do { + if (*s1 != *s2++) + return (*(const unsigned char *)s1 - + *(const unsigned char *)(s2 - 1)); + if (*s1++ == '\0') + break; + } while (--n != 0); + return 0; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/subr_prf.c b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/subr_prf.c new file mode 100644 index 0000000..c103562 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/lib/stdlib/subr_prf.c @@ -0,0 +1,548 @@ +/*- + * Copyright (c) 1986, 1988, 1991, 1993 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)subr_prf.c 8.3 (Berkeley) 1/21/94 + */ + +/* + * Portions copyright (c) 2009-2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +typedef unsigned char u_char; +typedef unsigned int u_int; +typedef int64_t quad_t; +typedef uint64_t u_quad_t; +typedef unsigned long u_long; +typedef unsigned short u_short; + +static inline int imax(int a, int b) { return (a > b ? a : b); } + +/* + * Note that stdarg.h and the ANSI style va_start macro is used for both + * ANSI and traditional C compilers. + */ + +#define TOCONS 0x01 +#define TOTTY 0x02 +#define TOLOG 0x04 + +/* Max number conversion buffer length: a u_quad_t in base 2, plus NUL byte. */ +#define MAXNBUF (sizeof(intmax_t) * 8 + 1) + +struct putchar_arg { + int flags; + int pri; + struct tty *tty; + char *p_bufr; + size_t n_bufr; + char *p_next; + size_t remain; +}; + +struct snprintf_arg { + char *str; + size_t remain; +}; + +extern int log_open; + +static char *ksprintn(char *nbuf, uintmax_t num, int base, int *len, int upper); +static void snprintf_func(int ch, void *arg); +static int kvprintf(char const *fmt, void (*func)(int, void*), void *arg, int radix, va_list ap); + +int vsnprintf(char *str, size_t size, const char *format, va_list ap); + +static char const hex2ascii_data[] = "0123456789abcdefghijklmnopqrstuvwxyz"; +#define hex2ascii(hex) (hex2ascii_data[hex]) + +/* + * Scaled down version of sprintf(3). + */ +int +sprintf(char *buf, const char *cfmt, ...) +{ + int retval; + va_list ap; + + va_start(ap, cfmt); + retval = kvprintf(cfmt, NULL, (void *)buf, 10, ap); + buf[retval] = '\0'; + va_end(ap); + return (retval); +} + +/* + * Scaled down version of vsprintf(3). + */ +int +vsprintf(char *buf, const char *cfmt, va_list ap) +{ + int retval; + + retval = kvprintf(cfmt, NULL, (void *)buf, 10, ap); + buf[retval] = '\0'; + return (retval); +} + +/* + * Scaled down version of snprintf(3). + */ +int +snprintf(char *str, size_t size, const char *format, ...) +{ + int retval; + va_list ap; + + va_start(ap, format); + retval = vsnprintf(str, size, format, ap); + va_end(ap); + return(retval); +} + +/* + * Scaled down version of vsnprintf(3). + */ +int +vsnprintf(char *str, size_t size, const char *format, va_list ap) +{ + struct snprintf_arg info; + int retval; + + info.str = str; + info.remain = size; + retval = kvprintf(format, snprintf_func, &info, 10, ap); + if (info.remain >= 1) + *info.str++ = '\0'; + return (retval); +} + +static void +snprintf_func(int ch, void *arg) +{ + struct snprintf_arg *const info = arg; + + if (info->remain >= 2) { + *info->str++ = ch; + info->remain--; + } +} + + +/* + * Kernel version which takes radix argument vsnprintf(3). + */ +int +vsnrprintf(char *str, size_t size, int radix, const char *format, va_list ap) +{ + struct snprintf_arg info; + int retval; + + info.str = str; + info.remain = size; + retval = kvprintf(format, snprintf_func, &info, radix, ap); + if (info.remain >= 1) + *info.str++ = '\0'; + return (retval); +} + + +/* + * Put a NUL-terminated ASCII number (base <= 36) in a buffer in reverse + * order; return an optional length and a pointer to the last character + * written in the buffer (i.e., the first character of the string). + * The buffer pointed to by `nbuf' must have length >= MAXNBUF. + */ +static char * +ksprintn(char *nbuf, uintmax_t num, int base, int *lenp, int upper) +{ + char *p, c; + + p = nbuf; + *p = '\0'; + do { + c = hex2ascii(num % base); + *++p = upper ? toupper(c) : c; + } while (num /= base); + if (lenp) + *lenp = p - nbuf; + return (p); +} + +/* + * Scaled down version of printf(3). + * + * Two additional formats: + * + * The format %b is supported to decode error registers. + * Its usage is: + * + * printf("reg=%b\n", regval, "*"); + * + * where is the output base expressed as a control character, e.g. + * \10 gives octal; \20 gives hex. Each arg is a sequence of characters, + * the first of which gives the bit number to be inspected (origin 1), and + * the next characters (up to a control character, i.e. a character <= 32), + * give the name of the register. Thus: + * + * kvprintf("reg=%b\n", 3, "\10\2BITTWO\1BITONE\n"); + * + * would produce output: + * + * reg=3 + * + * XXX: %D -- Hexdump, takes pointer and separator string: + * ("%6D", ptr, ":") -> XX:XX:XX:XX:XX:XX + * ("%*D", len, ptr, " " -> XX XX XX XX ... + */ +int +kvprintf(char const *fmt, void (*func)(int, void*), void *arg, int radix, va_list ap) +{ +#define PCHAR(c) {int cc=(c); if (func) (*func)(cc,arg); else *d++ = cc; retval++; } + char nbuf[MAXNBUF]; + char *d; + const char *p, *percent, *q; + u_char *up; + int ch, n; + uintmax_t num; + int base, lflag, qflag, tmp, width, ladjust, sharpflag, neg, sign, dot; + int cflag, hflag, jflag, tflag, zflag; + int dwidth, upper; + char padc; + int stop = 0, retval = 0; + + num = 0; + if (!func) + d = (char *) arg; + else + d = NULL; + + if (fmt == NULL) + fmt = "(fmt null)\n"; + + if (radix < 2 || radix > 36) + radix = 10; + + for (;;) { + padc = ' '; + width = 0; + while ((ch = (u_char)*fmt++) != '%' || stop) { + if (ch == '\0') + return (retval); + PCHAR(ch); + } + percent = fmt - 1; + qflag = 0; lflag = 0; ladjust = 0; sharpflag = 0; neg = 0; + sign = 0; dot = 0; dwidth = 0; upper = 0; + cflag = 0; hflag = 0; jflag = 0; tflag = 0; zflag = 0; +reswitch: switch (ch = (u_char)*fmt++) { + case '.': + dot = 1; + goto reswitch; + case '#': + sharpflag = 1; + goto reswitch; + case '+': + sign = 1; + goto reswitch; + case '-': + ladjust = 1; + goto reswitch; + case '%': + PCHAR(ch); + break; + case '*': + if (!dot) { + width = va_arg(ap, int); + if (width < 0) { + ladjust = !ladjust; + width = -width; + } + } else { + dwidth = va_arg(ap, int); + } + goto reswitch; + case '0': + if (!dot) { + padc = '0'; + goto reswitch; + } + case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + for (n = 0;; ++fmt) { + n = n * 10 + ch - '0'; + ch = *fmt; + if (ch < '0' || ch > '9') + break; + } + if (dot) + dwidth = n; + else + width = n; + goto reswitch; + case 'b': + num = (u_int)va_arg(ap, int); + p = va_arg(ap, char *); + for (q = ksprintn(nbuf, num, *p++, NULL, 0); *q;) + PCHAR(*q--); + + if (num == 0) + break; + + for (tmp = 0; *p;) { + n = *p++; + if (num & (1 << (n - 1))) { + PCHAR(tmp ? ',' : '<'); + for (; (n = *p) > ' '; ++p) + PCHAR(n); + tmp = 1; + } else + for (; *p > ' '; ++p) + continue; + } + if (tmp) + PCHAR('>'); + break; + case 'c': + PCHAR(va_arg(ap, int)); + break; + case 'D': + up = va_arg(ap, u_char *); + p = va_arg(ap, char *); + if (!width) + width = 16; + while(width--) { + PCHAR(hex2ascii(*up >> 4)); + PCHAR(hex2ascii(*up & 0x0f)); + up++; + if (width) + for (q=p;*q;q++) + PCHAR(*q); + } + break; + case 'd': + case 'i': + base = 10; + sign = 1; + goto handle_sign; + case 'h': + if (hflag) { + hflag = 0; + cflag = 1; + } else + hflag = 1; + goto reswitch; + case 'j': + jflag = 1; + goto reswitch; + case 'l': + if (lflag) { + lflag = 0; + qflag = 1; + } else + lflag = 1; + goto reswitch; + case 'n': + if (jflag) + *(va_arg(ap, intmax_t *)) = retval; + else if (qflag) + *(va_arg(ap, quad_t *)) = retval; + else if (lflag) + *(va_arg(ap, long *)) = retval; + else if (zflag) + *(va_arg(ap, size_t *)) = retval; + else if (hflag) + *(va_arg(ap, short *)) = retval; + else if (cflag) + *(va_arg(ap, char *)) = retval; + else + *(va_arg(ap, int *)) = retval; + break; + case 'o': + base = 8; + goto handle_nosign; + case 'p': + base = 16; + sharpflag = (width == 0); + sign = 0; + num = (uintptr_t)va_arg(ap, void *); + goto number; + case 'q': + qflag = 1; + goto reswitch; + case 'r': + base = radix; + if (sign) + goto handle_sign; + goto handle_nosign; + case 's': + p = va_arg(ap, char *); + if (p == NULL) + p = "(null)"; + if (!dot) + n = strlen (p); + else + for (n = 0; n < dwidth && p[n]; n++) + continue; + + width -= n; + + if (!ladjust && width > 0) + while (width--) + PCHAR(padc); + while (n--) + PCHAR(*p++); + if (ladjust && width > 0) + while (width--) + PCHAR(padc); + break; + case 't': + tflag = 1; + goto reswitch; + case 'u': + base = 10; + goto handle_nosign; + case 'X': + upper = 1; + case 'x': + base = 16; + goto handle_nosign; + case 'y': + base = 16; + sign = 1; + goto handle_sign; + case 'z': + zflag = 1; + goto reswitch; +handle_nosign: + sign = 0; + if (jflag) + num = va_arg(ap, uintmax_t); + else if (qflag) + num = va_arg(ap, u_quad_t); + else if (tflag) + num = va_arg(ap, ptrdiff_t); + else if (lflag) + num = va_arg(ap, u_long); + else if (zflag) + num = va_arg(ap, size_t); + else if (hflag) + num = (u_short)va_arg(ap, int); + else if (cflag) + num = (u_char)va_arg(ap, int); + else + num = va_arg(ap, u_int); + goto number; +handle_sign: + if (jflag) + num = va_arg(ap, intmax_t); + else if (qflag) + num = va_arg(ap, quad_t); + else if (tflag) + num = va_arg(ap, ptrdiff_t); + else if (lflag) + num = va_arg(ap, long); + else if (zflag) + num = va_arg(ap, ssize_t); + else if (hflag) + num = (short)va_arg(ap, int); + else if (cflag) + num = (char)va_arg(ap, int); + else + num = va_arg(ap, int); +number: + if (sign && (intmax_t)num < 0) { + neg = 1; + num = -(intmax_t)num; + } + p = ksprintn(nbuf, num, base, &n, upper); + tmp = 0; + if (sharpflag && num != 0) { + if (base == 8) + tmp++; + else if (base == 16) + tmp += 2; + } + if (neg) + tmp++; + + if (!ladjust && padc == '0') + dwidth = width - tmp; + width -= tmp + imax(dwidth, n); + dwidth -= n; + if (!ladjust) + while (width-- > 0) + PCHAR(' '); + if (neg) + PCHAR('-'); + if (sharpflag && num != 0) { + if (base == 8) { + PCHAR('0'); + } else if (base == 16) { + PCHAR('0'); + PCHAR('x'); + } + } + while (dwidth-- > 0) + PCHAR('0'); + + while (*p) + PCHAR(*p--); + + if (ladjust) + while (width-- > 0) + PCHAR(' '); + + break; + default: + while (percent < fmt) + PCHAR(*percent++); + /* + * Since we ignore an formatting argument it is no + * longer safe to obey the remaining formatting + * arguments as the arguments will no longer match + * the format specs. + */ + stop = 1; + break; + } + } +#undef PCHAR +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/license.md b/IPL/SDK/v3m/src/Dummy_BL33/license.md new file mode 100644 index 0000000..941b741 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/license.md @@ -0,0 +1,26 @@ +Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + +* Neither the name of ARM nor the names of its contributors may be used to + endorse or promote products derived from this software without specific prior + written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/aarch64/board_arm_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/aarch64/board_arm_helpers.S new file mode 100644 index 0000000..80c5759 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/aarch64/board_arm_helpers.S @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + + .globl plat_report_exception + + + /* --------------------------------------------- + * void plat_report_exception(unsigned int type) + * Function to report an unhandled exception + * with platform-specific means. + * On FVP platform, it updates the LEDs + * to indicate where we are + * --------------------------------------------- + */ +func plat_report_exception + mrs x1, CurrentEl + lsr x1, x1, #MODE_EL_SHIFT + lsl x1, x1, #V2M_SYS_LED_EL_SHIFT + lsl x0, x0, #V2M_SYS_LED_EC_SHIFT + mov x2, #(SECURE << V2M_SYS_LED_SS_SHIFT) + orr x0, x0, x2 + orr x0, x0, x1 + mov x1, #V2M_SYSREGS_BASE + add x1, x1, #V2M_SYS_LED + str w0, [x1] + ret +endfunc plat_report_exception diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/board_arm_trusted_boot.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/board_arm_trusted_boot.c new file mode 100644 index 0000000..103aafb --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/board_arm_trusted_boot.c @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/* Weak definition may be overridden in specific platform */ +#pragma weak plat_match_rotpk + +/* SHA256 algorithm */ +#define SHA256_BYTES 32 + +/* ROTPK locations */ +#define ARM_ROTPK_REGS_ID 1 +#define ARM_ROTPK_DEVEL_RSA_ID 2 + +#if !ARM_ROTPK_LOCATION_ID + #error "ARM_ROTPK_LOCATION_ID not defined" +#endif + +static const unsigned char rotpk_hash_hdr[] = \ + "\x30\x31\x30\x0D\x06\x09\x60\x86\x48" \ + "\x01\x65\x03\x04\x02\x01\x05\x00\x04\x20"; +static const unsigned int rotpk_hash_hdr_len = sizeof(rotpk_hash_hdr) - 1; +static unsigned char rotpk_hash_der[sizeof(rotpk_hash_hdr) - 1 + SHA256_BYTES]; + +#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) +static const unsigned char arm_devel_rotpk_hash[] = \ + "\xB0\xF3\x82\x09\x12\x97\xD8\x3A" \ + "\x37\x7A\x72\x47\x1B\xEC\x32\x73" \ + "\xE9\x92\x32\xE2\x49\x59\xF6\x5E" \ + "\x8B\x4A\x4A\x46\xD8\x22\x9A\xDA"; +#endif + +/* + * Return the ROTPK hash in the following ASN.1 structure in DER format: + * + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL + * } + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm AlgorithmIdentifier, + * digest OCTET STRING + * } + */ +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + uint8_t *dst; + + assert(key_ptr != NULL); + assert(key_len != NULL); + assert(flags != NULL); + + /* Copy the DER header */ + memcpy(rotpk_hash_der, rotpk_hash_hdr, rotpk_hash_hdr_len); + dst = (uint8_t *)&rotpk_hash_der[rotpk_hash_hdr_len]; + +#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) + memcpy(dst, arm_devel_rotpk_hash, SHA256_BYTES); +#elif (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID) + uint32_t *src, tmp; + unsigned int words, i; + + /* + * Append the hash from Trusted Root-Key Storage registers. The hash has + * not been written linearly into the registers, so we have to do a bit + * of byte swapping: + * + * 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C + * +---------------------------------------------------------------+ + * | Reg0 | Reg1 | Reg2 | Reg3 | Reg4 | Reg5 | Reg6 | Reg7 | + * +---------------------------------------------------------------+ + * | ... ... | | ... ... | + * | +--------------------+ | +-------+ + * | | | | + * +----------------------------+ +----------------------------+ + * | | | | + * +-------+ | +--------------------+ | + * | | | | + * v v v v + * +---------------------------------------------------------------+ + * | | | + * +---------------------------------------------------------------+ + * 0 15 16 31 + * + * Additionally, we have to access the registers in 32-bit words + */ + words = SHA256_BYTES >> 3; + + /* Swap bytes 0-15 (first four registers) */ + src = (uint32_t *)TZ_PUB_KEY_HASH_BASE; + for (i = 0 ; i < words ; i++) { + tmp = src[words - 1 - i]; + /* Words are read in little endian */ + *dst++ = (uint8_t)((tmp >> 24) & 0xFF); + *dst++ = (uint8_t)((tmp >> 16) & 0xFF); + *dst++ = (uint8_t)((tmp >> 8) & 0xFF); + *dst++ = (uint8_t)(tmp & 0xFF); + } + + /* Swap bytes 16-31 (last four registers) */ + src = (uint32_t *)(TZ_PUB_KEY_HASH_BASE + SHA256_BYTES / 2); + for (i = 0 ; i < words ; i++) { + tmp = src[words - 1 - i]; + *dst++ = (uint8_t)((tmp >> 24) & 0xFF); + *dst++ = (uint8_t)((tmp >> 16) & 0xFF); + *dst++ = (uint8_t)((tmp >> 8) & 0xFF); + *dst++ = (uint8_t)(tmp & 0xFF); + } +#endif /* (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) */ + + *key_ptr = (void *)rotpk_hash_der; + *key_len = (unsigned int)sizeof(rotpk_hash_der); + *flags = ROTPK_IS_HASH; + return 0; +} + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/board_common.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/board_common.mk new file mode 100644 index 0000000..bec49ed --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/board_common.mk @@ -0,0 +1,55 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +PLAT_INCLUDES += -Iinclude/plat/arm/board/common/ + +PLAT_BL_COMMON_SOURCES += drivers/arm/pl011/pl011_console.S \ + plat/arm/board/common/aarch64/board_arm_helpers.S + +#BL1_SOURCES += + +#BL2_SOURCES += + +#BL31_SOURCES += + +ifneq (${TRUSTED_BOARD_BOOT},0) + # ROTPK hash location + ifeq (${ARM_ROTPK_LOCATION}, regs) + ARM_ROTPK_LOCATION_ID = ARM_ROTPK_REGS_ID + else ifeq (${ARM_ROTPK_LOCATION}, devel_rsa) + ARM_ROTPK_LOCATION_ID = ARM_ROTPK_DEVEL_RSA_ID + else + $(error "Unsupported ARM_ROTPK_LOCATION value") + endif + $(eval $(call add_define,ARM_ROTPK_LOCATION_ID)) + + BL1_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c + BL2_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c +endif diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/board_css.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/board_css.mk new file mode 100644 index 0000000..67e794e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/board_css.mk @@ -0,0 +1,33 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +PLAT_BL_COMMON_SOURCES += plat/arm/board/common/board_css_common.c + +include plat/arm/board/common/board_common.mk diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/board_css_common.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/board_css_common.c new file mode 100644 index 0000000..3bb3dd6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/board_css_common.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + +/* + * Table of regions for different BL stages to map using the MMU. + * This doesn't include Trusted RAM as the 'mem_layout' argument passed to + * arm_configure_mmu_elx() will give the available subset of that, + */ +#if IMAGE_BL1 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_FLASH0, + V2M_MAP_IOFPGA, + CSS_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, + {0} +}; +#endif +#if IMAGE_BL2 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_FLASH0, + V2M_MAP_IOFPGA, + CSS_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, + ARM_MAP_NS_DRAM1, + ARM_MAP_TSP_SEC_MEM, + {0} +}; +#endif +#if IMAGE_BL31 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_IOFPGA, + CSS_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, + {0} +}; +#endif +#if IMAGE_BL32 +const mmap_region_t plat_arm_mmap[] = { + V2M_MAP_IOFPGA, + CSS_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, + {0} +}; +#endif + +ARM_CASSERT_MMAP + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/rotpk/arm_rotpk_rsa.der b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/rotpk/arm_rotpk_rsa.der new file mode 100644 index 0000000000000000000000000000000000000000..661f8998df780e571477691d8d53c2bbec19ae16 GIT binary patch literal 294 zcmV+>0ondAf&n5h4F(A+hDe6@4FLfG1potr0S^E$f&mHwf&l>l%Pe5kjbqdYd49(h zmc30RPOOIJw{hdeR14=69K9(T!9RMo0;;Pv#Mw4!Y~p3Zo3Xz=s8%M+{R9EJtUgpS z%6VS9vIXh}Sn_nb;q-^V844d}2X};np&al3C|T#jXniIiL+e&!^EoltD^aPuPtf+> zmE2!j!R?T5>?o0b7wveE^kApN$4^l0T@yMXD{#eOdk7(AI?aMsjCx0`iRh(BNHN(R zM&*Tun4smrrfR(hwp99JrTKdtiAy*L70s{d60nnC)o&W#< literal 0 HcmV?d00001 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem new file mode 100644 index 0000000..71410ec --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem @@ -0,0 +1,28 @@ +-----BEGIN PRIVATE KEY----- +MIIEvAIBADANBgkqhkiG9w0BAQEFAASCBKYwggSiAgEAAoIBAQDLLGDVjWPUB3l+ +xxaWvU0kTqyG5rdx48VUC+cUHL0pGsE/erYCqqs2xNk2aWziZcObsb89qFYmy/0E +AbqsPlQyynleu7IF6gZY8nS64fSHwBkKH2YHd4SDoRzv/yhZ58NofSYgQ+tWY/M5 +MdgrUam8T9D23pXcX1vB7ZBv7CiRfhfteJD0YKfEx09Q7V0TOiErcMVhewghZTrN +glaMekesieilSEgx2R1G5YWGmKDlwKZqvQfkkldhB499Wk3Krja5VgQQ8my+9jts +gD6+DqNNx9R+p0nU8tK8zzCo53SPZN+8XEdozEBM+IPMy0A1BGDKs6QXnwPKHVr6 +0a8hVxDTAgMBAAECggEAfwsc8ewbhDW4TwIGqfNtDUr0rtYN13VpqohW0ki2L8G/ +HQaKUViO/wxQFqoNn/OqQO0AfHmKhXAAokTCiXngBHJ/OjF7vB7+IRhazZEE6u2/ +uoivr/OYNQbFpXyTqsQ1eFzpPju6KKcPK7BzT4Mc89ek/vloFAi8w6LdMl8lbvOg +LBWqX+5A+UQoenPUTvYM4U22YNcEAWubkpsYAmViiWiac+a+uPRk39aKyfOedDNu ++ty9MtCwekivoUTfP/1+O+jFlDnPMJUOEkBmcBqxseYYAHu7blBpdHxYpAItC2pv +YwJJSvsE+HLBLPk177Jahg7sOUqcP0F/X+T65yuvIQKBgQDxdjXdJT5K8j7rG2fv +2bvF2H1GPaHaTYRk0EGI2Ql6Nn+ddfeCE6gaT7aPPgg87wAhNu93coFuYHw0p/sc +ZkXMJ+BmlstPV555cWXmwcxZLsni0fOXrt4YxwWkZwmh74m0NVM/cSFw56PU0oj1 +yDNeq3fgmsJocmuNTe1eG9qA7QKBgQDXaAGrNA5Xel5mqqMYTHHQWI6l2uzdNtt7 +eDn3K9+Eh3ywTqrwP845MAjKDU2Lq61I6t2H89dEifHq823VIcLCHd9BF04MrAH7 +qDPzrmPP2iB9g+YFmGBKe+K0HFE1t1KrTlo9VV6ZAC6RJNLAgwD4kvfIVYNkCGwe ++hoZBdhgvwKBgBrOsPQ4ak4PzwRzKnrqhXpVqrLdrNZ7vLMkm+IBlpfG7SwiKLR8 +UjF5oB8PGAML1cvaOYPdZplGhQOjkrF4eU9NLhC1tSS96Y46FMIlyfYsx6UzAgRZ +GbdOgUXbWqpr2bH0KaXlfXz3eqzqIuKGs41TJB//jo3iBibN/AhytzORAoGAeGov +5KDpE4XYl9Pz8HVremjG9Xh4yQENmOwQm1fvT4rd7UFM1ZkVk2qCv1DIdLe32vdQ +d9ucDzh+ADWsxGRnF1TTpPN+Mh9FzISu5h4qtdreJsxBHgecbIbsqHrb+wdMM29N +itPaWfV8Eq9fETcqp8qgsWD8XkNHDdoKFMrrtskCgYAoSt/Je1D3ZE/3HEjez7bq +fenS3J6KG2SEn2PNFn+R0R5vBo4DaV/cQysKh44GD2+sh0QDyh6nuWJufyhPzROP +DU6DCLbwNePj/yaGuzi36oLt6bBgfPWCiJY7jIdK8DmTLW25m7fRtCC5pxZlSzgl +KBf7R6cbaTvaFe05Y2FJXA== +-----END PRIVATE KEY----- diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/aarch64/fvp_common.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/aarch64/fvp_common.c new file mode 100644 index 0000000..58b646a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/aarch64/fvp_common.c @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../fvp_def.h" + +/******************************************************************************* + * arm_config holds the characteristics of the differences between the three FVP + * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot + * at each boot stage by the primary before enabling the MMU (to allow cci + * configuration) & used thereafter. Each BL will have its own copy to allow + * independent operation. + ******************************************************************************/ +arm_config_t arm_config; + +#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ + DEVICE0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ + DEVICE1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ + DEVICE2_SIZE, \ + MT_DEVICE | MT_RO | MT_SECURE) + + +/* + * Table of regions for various BL stages to map using the MMU. + * This doesn't include TZRAM as the 'mem_layout' argument passed to + * arm_configure_mmu_elx() will give the available subset of that, + */ +#if IMAGE_BL1 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_FLASH0, + V2M_MAP_IOFPGA, + MAP_DEVICE0, + MAP_DEVICE1, + MAP_DEVICE2, + {0} +}; +#endif +#if IMAGE_BL2 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_FLASH0, + V2M_MAP_IOFPGA, + MAP_DEVICE0, + MAP_DEVICE1, + MAP_DEVICE2, + ARM_MAP_NS_DRAM1, + ARM_MAP_TSP_SEC_MEM, + {0} +}; +#endif +#if IMAGE_BL31 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_IOFPGA, + MAP_DEVICE0, + MAP_DEVICE1, + {0} +}; +#endif +#if IMAGE_BL32 +const mmap_region_t plat_arm_mmap[] = { + V2M_MAP_IOFPGA, + MAP_DEVICE0, + MAP_DEVICE1, + {0} +}; +#endif + +ARM_CASSERT_MMAP + + +#if IMAGE_BL31 || IMAGE_BL32 +/* Array of secure interrupts to be configured by the gic driver */ +const unsigned int irq_sec_array[] = { + ARM_IRQ_SEC_PHY_TIMER, + ARM_IRQ_SEC_SGI_0, + ARM_IRQ_SEC_SGI_1, + ARM_IRQ_SEC_SGI_2, + ARM_IRQ_SEC_SGI_3, + ARM_IRQ_SEC_SGI_4, + ARM_IRQ_SEC_SGI_5, + ARM_IRQ_SEC_SGI_6, + ARM_IRQ_SEC_SGI_7, + FVP_IRQ_TZ_WDOG, + FVP_IRQ_SEC_SYS_TIMER +}; + +void plat_arm_gic_init(void) +{ + arm_gic_init(arm_config.gicc_base, + arm_config.gicd_base, + BASE_GICR_BASE, + irq_sec_array, + ARRAY_SIZE(irq_sec_array)); +} + +#endif + +/******************************************************************************* + * A single boot loader stack is expected to work on both the Foundation FVP + * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The + * SYS_ID register provides a mechanism for detecting the differences between + * these platforms. This information is stored in a per-BL array to allow the + * code to take the correct path.Per BL platform configuration. + ******************************************************************************/ +void fvp_config_setup(void) +{ + unsigned int rev, hbi, bld, arch, sys_id; + + sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); + rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; + hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; + bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; + arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; + + if (arch != ARCH_MODEL) { + ERROR("This firmware is for FVP models\n"); + panic(); + } + + /* + * The build field in the SYS_ID tells which variant of the GIC + * memory is implemented by the model. + */ + switch (bld) { + case BLD_GIC_VE_MMAP: + arm_config.gicd_base = VE_GICD_BASE; + arm_config.gicc_base = VE_GICC_BASE; + arm_config.gich_base = VE_GICH_BASE; + arm_config.gicv_base = VE_GICV_BASE; + break; + case BLD_GIC_A53A57_MMAP: + arm_config.gicd_base = BASE_GICD_BASE; + arm_config.gicc_base = BASE_GICC_BASE; + arm_config.gich_base = BASE_GICH_BASE; + arm_config.gicv_base = BASE_GICV_BASE; + break; + default: + ERROR("Unsupported board build %x\n", bld); + panic(); + } + + /* + * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 + * for the Foundation FVP. + */ + switch (hbi) { + case HBI_FOUNDATION_FVP: + arm_config.max_aff0 = 4; + arm_config.max_aff1 = 1; + arm_config.flags = 0; + + /* + * Check for supported revisions of Foundation FVP + * Allow future revisions to run but emit warning diagnostic + */ + switch (rev) { + case REV_FOUNDATION_FVP_V2_0: + case REV_FOUNDATION_FVP_V2_1: + case REV_FOUNDATION_FVP_v9_1: + break; + default: + WARN("Unrecognized Foundation FVP revision %x\n", rev); + break; + } + break; + case HBI_BASE_FVP: + arm_config.max_aff0 = 4; + arm_config.max_aff1 = 2; + arm_config.flags |= ARM_CONFIG_BASE_MMAP | + ARM_CONFIG_HAS_CCI | ARM_CONFIG_HAS_TZC; + + /* + * Check for supported revisions + * Allow future revisions to run but emit warning diagnostic + */ + switch (rev) { + case REV_BASE_FVP_V0: + break; + default: + WARN("Unrecognized Base FVP revision %x\n", rev); + break; + } + break; + default: + ERROR("Unsupported board HBI number 0x%x\n", hbi); + panic(); + } +} + + +void fvp_cci_init(void) +{ + /* + * Initialize CCI-400 driver + */ + if (arm_config.flags & ARM_CONFIG_HAS_CCI) + arm_cci_init(); +} + +void fvp_cci_enable(void) +{ + if (arm_config.flags & ARM_CONFIG_HAS_CCI) + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); +} + +void fvp_cci_disable(void) +{ + if (arm_config.flags & ARM_CONFIG_HAS_CCI) + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/aarch64/fvp_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/aarch64/fvp_helpers.S new file mode 100644 index 0000000..42e5b70 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/aarch64/fvp_helpers.S @@ -0,0 +1,170 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "../drivers/pwrc/fvp_pwrc.h" +#include "../fvp_def.h" + + .globl plat_secondary_cold_boot_setup + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + + .macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res + ldr \x_tmp, =V2M_SYSREGS_BASE + V2M_SYS_ID + ldr \w_tmp, [\x_tmp] + ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH + cmp \w_tmp, #BLD_GIC_VE_MMAP + csel \res, \param1, \param2, eq + .endm + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * TODO: Should we read the PSYS register to make sure + * that the request has gone through. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* --------------------------------------------- + * Power down this cpu. + * TODO: Do we need to worry about powering the + * cluster down as well here. That will need + * locks which we won't have unless an elf- + * loader zeroes out the zi section. + * --------------------------------------------- + */ + mrs x0, mpidr_el1 + ldr x1, =PWRC_BASE + str w0, [x1, #PPOFFR_OFF] + + /* --------------------------------------------- + * Deactivate the gic cpu interface as well + * --------------------------------------------- + */ + ldr x0, =VE_GICC_BASE + ldr x1, =BASE_GICC_BASE + fvp_choose_gicmmap x0, x1, x2, w2, x1 + mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1) + orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0) + str w0, [x1, #GICC_CTLR] + + /* --------------------------------------------- + * There is no sane reason to come out of this + * wfi so panic if we do. This cpu will be pow- + * ered on and reset by the cpu_on pm api + * --------------------------------------------- + */ + dsb sy + wfi +cb_panic: + b cb_panic +endfunc plat_secondary_cold_boot_setup + + /* --------------------------------------------------------------------- + * unsigned long plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and warm + * boot. On FVP, this information can be queried from the power + * controller. The Power Control SYS Status Register (PSYSR) indicates + * the wake-up reason for the CPU. + * + * For a cold boot, return 0. + * For a warm boot, read the mailbox and return the address it contains. + * + * TODO: PSYSR is a common register and should be + * accessed using locks. Since its not possible + * to use locks immediately after a cold reset + * we are relying on the fact that after a cold + * reset all cpus will read the same WK field + * --------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + /* --------------------------------------------------------------------- + * When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC + * WakeRequest signal" then it is a warm boot. + * --------------------------------------------------------------------- + */ + mrs x2, mpidr_el1 + ldr x1, =PWRC_BASE + str w2, [x1, #PSYSR_OFF] + ldr w2, [x1, #PSYSR_OFF] + ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH + cmp w2, #WKUP_PPONR + beq warm_reset + cmp w2, #WKUP_GICREQ + beq warm_reset + + /* Cold reset */ + mov x0, #0 + ret + +warm_reset: + /* --------------------------------------------------------------------- + * A mailbox is maintained in the trusted SRAM. It is flushed out of the + * caches after every update using normal memory so it is safe to read + * it here with SO attributes. + * --------------------------------------------------------------------- + */ + mov_imm x0, MBOX_BASE + ldr x0, [x0] + cbz x0, _panic + ret + + /* --------------------------------------------------------------------- + * The power controller indicates this is a warm reset but the mailbox + * is empty. This should never happen! + * --------------------------------------------------------------------- + */ +_panic: + b _panic +endfunc plat_get_my_entrypoint + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #FVP_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c new file mode 100644 index 0000000..e004281 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "../../fvp_def.h" +#include "../../fvp_private.h" +#include "fvp_pwrc.h" + +/* + * TODO: Someday there will be a generic power controller api. At the moment + * each platform has its own pwrc so just exporting functions is fine. + */ +ARM_INSTANTIATE_LOCK + +unsigned int fvp_pwrc_get_cpu_wkr(unsigned long mpidr) +{ + return PSYSR_WK(fvp_pwrc_read_psysr(mpidr)); +} + +unsigned int fvp_pwrc_read_psysr(unsigned long mpidr) +{ + unsigned int rc; + arm_lock_get(); + mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr); + rc = mmio_read_32(PWRC_BASE + PSYSR_OFF); + arm_lock_release(); + return rc; +} + +void fvp_pwrc_write_pponr(unsigned long mpidr) +{ + arm_lock_get(); + mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr); + arm_lock_release(); +} + +void fvp_pwrc_write_ppoffr(unsigned long mpidr) +{ + arm_lock_get(); + mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr); + arm_lock_release(); +} + +void fvp_pwrc_set_wen(unsigned long mpidr) +{ + arm_lock_get(); + mmio_write_32(PWRC_BASE + PWKUPR_OFF, + (unsigned int) (PWKUPR_WEN | mpidr)); + arm_lock_release(); +} + +void fvp_pwrc_clr_wen(unsigned long mpidr) +{ + arm_lock_get(); + mmio_write_32(PWRC_BASE + PWKUPR_OFF, + (unsigned int) mpidr); + arm_lock_release(); +} + +void fvp_pwrc_write_pcoffr(unsigned long mpidr) +{ + arm_lock_get(); + mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr); + arm_lock_release(); +} + +/* Nothing else to do here apart from initializing the lock */ +void plat_arm_pwrc_setup(void) +{ + arm_lock_init(); +} + + + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h new file mode 100644 index 0000000..3dc9aad --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FVP_PWRC_H__ +#define __FVP_PWRC_H__ + +/* FVP Power controller register offset etc */ +#define PPOFFR_OFF 0x0 +#define PPONR_OFF 0x4 +#define PCOFFR_OFF 0x8 +#define PWKUPR_OFF 0xc +#define PSYSR_OFF 0x10 + +#define PWKUPR_WEN (1ull << 31) + +#define PSYSR_AFF_L2 (1 << 31) +#define PSYSR_AFF_L1 (1 << 30) +#define PSYSR_AFF_L0 (1 << 29) +#define PSYSR_WEN (1 << 28) +#define PSYSR_PC (1 << 27) +#define PSYSR_PP (1 << 26) + +#define PSYSR_WK_SHIFT 24 +#define PSYSR_WK_WIDTH 0x2 +#define PSYSR_WK_MASK ((1 << PSYSR_WK_WIDTH) - 1) +#define PSYSR_WK(x) (x >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK + +#define WKUP_COLD 0x0 +#define WKUP_RESET 0x1 +#define WKUP_PPONR 0x2 +#define WKUP_GICREQ 0x3 + +#define PSYSR_INVALID 0xffffffff + +#ifndef __ASSEMBLY__ + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void fvp_pwrc_write_pcoffr(unsigned long); +void fvp_pwrc_write_ppoffr(unsigned long); +void fvp_pwrc_write_pponr(unsigned long); +void fvp_pwrc_set_wen(unsigned long); +void fvp_pwrc_clr_wen(unsigned long); +unsigned int fvp_pwrc_read_psysr(unsigned long); +unsigned int fvp_pwrc_get_cpu_wkr(unsigned long); + +#endif /*__ASSEMBLY__*/ + +#endif /* __FVP_PWRC_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_bl1_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_bl1_setup.c new file mode 100644 index 0000000..33712d1 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_bl1_setup.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "fvp_private.h" + + +/******************************************************************************* + * Perform any BL1 specific platform actions. + ******************************************************************************/ +void bl1_early_platform_setup(void) +{ + arm_bl1_early_platform_setup(); + + /* Initialize the platform config for future decision making */ + fvp_config_setup(); + + /* + * Initialize CCI for this cluster during cold boot. + * No need for locks as no other CPU is active. + */ + fvp_cci_init(); + /* + * Enable CCI coherency for the primary CPU's cluster. + */ + fvp_cci_enable(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_bl2_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_bl2_setup.c new file mode 100644 index 0000000..b1cdef4 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_bl2_setup.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "fvp_def.h" +#include "fvp_private.h" + + +void bl2_early_platform_setup(meminfo_t *mem_layout) +{ + arm_bl2_early_platform_setup(mem_layout); + + /* Initialize the platform config for future decision making */ + fvp_config_setup(); +} + +void bl2_platform_setup(void) +{ + arm_bl2_platform_setup(); + + /* Initialize delay timer driver using SP804 dual timer 0 */ + sp804_timer_init(V2M_SP804_TIMER0_BASE, + SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_bl31_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_bl31_setup.c new file mode 100644 index 0000000..f29af64 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_bl31_setup.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "fvp_private.h" + + +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +{ + arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2); + + /* Initialize the platform config for future decision making */ + fvp_config_setup(); + + /* + * Initialize CCI for this cluster during cold boot. + * No need for locks as no other CPU is active. + */ + fvp_cci_init(); + + /* + * Enable CCI coherency for the primary CPU's cluster. + * Earlier bootloader stages might already do this (e.g. Trusted + * Firmware's BL1 does it) but we can't assume so. There is no harm in + * executing this code twice anyway. + * FVP PSCI code will enable coherency for other clusters. + */ + fvp_cci_enable(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_def.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_def.h new file mode 100644 index 0000000..9a9eebf --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_def.h @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FVP_DEF_H__ +#define __FVP_DEF_H__ + +#include + + +#define FVP_MAX_CPUS_PER_CLUSTER 4 + +#define FVP_PRIMARY_CPU 0x0 + +/******************************************************************************* + * FVP memory map related constants + ******************************************************************************/ + +#define FLASH1_BASE 0x0c000000 +#define FLASH1_SIZE 0x04000000 + +#define PSRAM_BASE 0x14000000 +#define PSRAM_SIZE 0x04000000 + +#define VRAM_BASE 0x18000000 +#define VRAM_SIZE 0x02000000 + +/* Aggregate of all devices in the first GB */ +#define DEVICE0_BASE 0x20000000 +#define DEVICE0_SIZE 0x0c200000 + +#define DEVICE1_BASE 0x2f000000 +#define DEVICE1_SIZE 0x200000 + +/* Devices in the second GB */ +#define DEVICE2_BASE 0x7fe00000 +#define DEVICE2_SIZE 0x00200000 + +#define NSRAM_BASE 0x2e000000 +#define NSRAM_SIZE 0x10000 + +#define PCIE_EXP_BASE 0x40000000 +#define TZRNG_BASE 0x7fe60000 +#define TZNVCTR_BASE 0x7fe70000 + +/* Keys */ +#define SOC_KEYS_BASE 0x7fe80000 +#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) +#define TZ_PUB_KEY_HASH_SIZE 32 +#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) +#define HU_KEY_SIZE 16 +#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) +#define END_KEY_SIZE 32 + +/* Constants to distinguish FVP type */ +#define HBI_BASE_FVP 0x020 +#define REV_BASE_FVP_V0 0x0 + +#define HBI_FOUNDATION_FVP 0x010 +#define REV_FOUNDATION_FVP_V2_0 0x0 +#define REV_FOUNDATION_FVP_V2_1 0x1 +#define REV_FOUNDATION_FVP_v9_1 0x2 + +#define BLD_GIC_VE_MMAP 0x0 +#define BLD_GIC_A53A57_MMAP 0x1 + +#define ARCH_MODEL 0x1 + +/* FVP Power controller base address*/ +#define PWRC_BASE 0x1c100000 + +/* FVP SP804 timer frequency is 35 MHz*/ +#define SP804_TIMER_CLKMULT 35 +#define SP804_TIMER_CLKDIV 1 + +/******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ +/* VE compatible GIC memory map */ +#define VE_GICD_BASE 0x2c001000 +#define VE_GICC_BASE 0x2c002000 +#define VE_GICH_BASE 0x2c004000 +#define VE_GICV_BASE 0x2c006000 + +/* Base FVP compatible GIC memory map */ +#define BASE_GICD_BASE 0x2f000000 +#define BASE_GICR_BASE 0x2f100000 +#define BASE_GICC_BASE 0x2c000000 +#define BASE_GICH_BASE 0x2c010000 +#define BASE_GICV_BASE 0x2c02f000 + +#define FVP_IRQ_TZ_WDOG 56 +#define FVP_IRQ_SEC_SYS_TIMER 57 + + +/******************************************************************************* + * TrustZone address space controller related constants + ******************************************************************************/ + +/* NSAIDs used by devices in TZC filter 0 on FVP */ +#define FVP_NSAID_DEFAULT 0 +#define FVP_NSAID_PCI 1 +#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ +#define FVP_NSAID_AP 9 /* Application Processors */ +#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ + +/* NSAIDs used by devices in TZC filter 2 on FVP */ +#define FVP_NSAID_HDLCD0 2 +#define FVP_NSAID_CLCD 7 + +/******************************************************************************* + * Shared Data + ******************************************************************************/ + +/* Entrypoint mailboxes */ +#define MBOX_BASE ARM_SHARED_RAM_BASE + + +#endif /* __FVP_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_io_storage.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_io_storage.c new file mode 100644 index 0000000..e9d847f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_io_storage.c @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include /* For FOPEN_MODE_... */ + +/* Semihosting filenames */ +#define BL2_IMAGE_NAME "bl2.bin" +#define BL31_IMAGE_NAME "bl31.bin" +#define BL32_IMAGE_NAME "bl32.bin" +#define BL33_IMAGE_NAME "bl33.bin" + +#if TRUSTED_BOARD_BOOT +#define BL2_CERT_NAME "bl2.crt" +#define TRUSTED_KEY_CERT_NAME "trusted_key.crt" +#define BL31_KEY_CERT_NAME "bl31_key.crt" +#define BL32_KEY_CERT_NAME "bl32_key.crt" +#define BL33_KEY_CERT_NAME "bl33_key.crt" +#define BL31_CERT_NAME "bl31.crt" +#define BL32_CERT_NAME "bl32.crt" +#define BL33_CERT_NAME "bl33.crt" +#endif /* TRUSTED_BOARD_BOOT */ + +/* IO devices */ +static const io_dev_connector_t *sh_dev_con; +static uintptr_t sh_dev_handle; + +static const io_file_spec_t sh_file_spec[] = { + [BL2_IMAGE_ID] = { + .path = BL2_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, + [BL31_IMAGE_ID] = { + .path = BL31_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, + [BL32_IMAGE_ID] = { + .path = BL32_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, + [BL33_IMAGE_ID] = { + .path = BL33_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, +#if TRUSTED_BOARD_BOOT + [BL2_CERT_ID] = { + .path = BL2_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [TRUSTED_KEY_CERT_ID] = { + .path = TRUSTED_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [BL31_KEY_CERT_ID] = { + .path = BL31_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [BL32_KEY_CERT_ID] = { + .path = BL32_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [BL33_KEY_CERT_ID] = { + .path = BL33_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [BL31_CERT_ID] = { + .path = BL31_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [BL32_CERT_ID] = { + .path = BL32_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [BL33_CERT_ID] = { + .path = BL33_CERT_NAME, + .mode = FOPEN_MODE_RB + }, +#endif /* TRUSTED_BOARD_BOOT */ +}; + + +static int open_semihosting(const uintptr_t spec) +{ + int result = IO_FAIL; + uintptr_t local_image_handle; + + /* See if the file exists on semi-hosting.*/ + result = io_dev_init(sh_dev_handle, (uintptr_t)NULL); + if (result == IO_SUCCESS) { + result = io_open(sh_dev_handle, spec, &local_image_handle); + if (result == IO_SUCCESS) { + VERBOSE("Using Semi-hosting IO\n"); + io_close(local_image_handle); + } + } + return result; +} + +void plat_arm_io_setup(void) +{ + int io_result; + + arm_io_setup(); + + /* Register the additional IO devices on this platform */ + io_result = register_io_dev_sh(&sh_dev_con); + assert(io_result == IO_SUCCESS); + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(sh_dev_con, (uintptr_t)NULL, &sh_dev_handle); + assert(io_result == IO_SUCCESS); + + /* Ignore improbable errors in release builds */ + (void)io_result; +} + +/* + * FVP provides semihosting as an alternative to load images + */ +int plat_arm_get_alt_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result = open_semihosting((const uintptr_t)&sh_file_spec[image_id]); + if (result == IO_SUCCESS) { + *dev_handle = sh_dev_handle; + *image_spec = (uintptr_t)&sh_file_spec[image_id]; + } + + return result; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_pm.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_pm.c new file mode 100644 index 0000000..9d6ab9c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_pm.c @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "drivers/pwrc/fvp_pwrc.h" +#include "fvp_def.h" +#include "fvp_private.h" + + +#if ARM_RECOM_STATE_ID_ENC +/* + * The table storing the valid idle power states. Ensure that the + * array entries are populated in ascending order of state-id to + * enable us to use binary search during power state validation. + * The table must be terminated by a NULL entry. + */ +const unsigned int arm_pm_idle_states[] = { + /* State-id - 0x01 */ + arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, + ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), + /* State-id - 0x02 */ + arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, + ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), + /* State-id - 0x22 */ + arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, + ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), + 0, +}; +#endif + +/******************************************************************************* + * Private FVP function to program the mailbox for a cpu before it is released + * from reset. + ******************************************************************************/ +static void fvp_program_mailbox(uintptr_t address) +{ + uintptr_t *mailbox = (void *) MBOX_BASE; + *mailbox = address; + flush_dcache_range((uintptr_t) mailbox, sizeof(*mailbox)); +} + +/******************************************************************************* + * Function which implements the common FVP specific operations to power down a + * cpu in response to a CPU_OFF or CPU_SUSPEND request. + ******************************************************************************/ +static void fvp_cpu_pwrdwn_common(void) +{ + /* Prevent interrupts from spuriously waking up this cpu */ + arm_gic_cpuif_deactivate(); + + /* Program the power controller to power off this cpu. */ + fvp_pwrc_write_ppoffr(read_mpidr_el1()); +} + +/******************************************************************************* + * Function which implements the common FVP specific operations to power down a + * cluster in response to a CPU_OFF or CPU_SUSPEND request. + ******************************************************************************/ +static void fvp_cluster_pwrdwn_common(void) +{ + uint64_t mpidr = read_mpidr_el1(); + + /* Disable coherency if this cluster is to be turned off */ + fvp_cci_disable(); + + /* Program the power controller to turn the cluster off */ + fvp_pwrc_write_pcoffr(mpidr); +} + +/******************************************************************************* + * FVP handler called when a CPU is about to enter standby. + ******************************************************************************/ +void fvp_cpu_standby(plat_local_state_t cpu_state) +{ + + assert(cpu_state == ARM_LOCAL_STATE_RET); + + /* + * Enter standby state + * dsb is good practice before using wfi to enter low power states + */ + dsb(); + wfi(); +} + +/******************************************************************************* + * FVP handler called when a power domain is about to be turned on. The + * mpidr determines the CPU to be turned on. + ******************************************************************************/ +int fvp_pwr_domain_on(u_register_t mpidr) +{ + int rc = PSCI_E_SUCCESS; + unsigned int psysr; + + /* + * Ensure that we do not cancel an inflight power off request + * for the target cpu. That would leave it in a zombie wfi. + * Wait for it to power off, program the jump address for the + * target cpu and then program the power controller to turn + * that cpu on + */ + do { + psysr = fvp_pwrc_read_psysr(mpidr); + } while (psysr & PSYSR_AFF_L0); + + fvp_pwrc_write_pponr(mpidr); + return rc; +} + +/******************************************************************************* + * FVP handler called when a power domain is about to be turned off. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void fvp_pwr_domain_off(const psci_power_state_t *target_state) +{ + assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_OFF); + + /* + * If execution reaches this stage then this power domain will be + * suspended. Perform at least the cpu specific actions followed + * by the cluster specific operations if applicable. + */ + fvp_cpu_pwrdwn_common(); + + if (target_state->pwr_domain_state[ARM_PWR_LVL1] == + ARM_LOCAL_STATE_OFF) + fvp_cluster_pwrdwn_common(); + +} + +/******************************************************************************* + * FVP handler called when a power domain is about to be suspended. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + unsigned long mpidr; + + /* + * FVP has retention only at cpu level. Just return + * as nothing is to be done for retention. + */ + if (target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_RET) + return; + + assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_OFF); + + /* Get the mpidr for this cpu */ + mpidr = read_mpidr_el1(); + + /* Program the power controller to enable wakeup interrupts. */ + fvp_pwrc_set_wen(mpidr); + + /* Perform the common cpu specific operations */ + fvp_cpu_pwrdwn_common(); + + /* Perform the common cluster specific operations */ + if (target_state->pwr_domain_state[ARM_PWR_LVL1] == + ARM_LOCAL_STATE_OFF) + fvp_cluster_pwrdwn_common(); +} + +/******************************************************************************* + * FVP handler called when a power domain has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. + ******************************************************************************/ +void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + unsigned long mpidr; + + assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_OFF); + + /* Get the mpidr for this cpu */ + mpidr = read_mpidr_el1(); + + /* Perform the common cluster specific operations */ + if (target_state->pwr_domain_state[ARM_PWR_LVL1] == + ARM_LOCAL_STATE_OFF) { + /* + * This CPU might have woken up whilst the cluster was + * attempting to power down. In this case the FVP power + * controller will have a pending cluster power off request + * which needs to be cleared by writing to the PPONR register. + * This prevents the power controller from interpreting a + * subsequent entry of this cpu into a simple wfi as a power + * down request. + */ + fvp_pwrc_write_pponr(mpidr); + + /* Enable coherency if this cluster was off */ + fvp_cci_enable(); + } + + /* + * Clear PWKUPR.WEN bit to ensure interrupts do not interfere + * with a cpu power down unless the bit is set again + */ + fvp_pwrc_clr_wen(mpidr); + + /* Enable the gic cpu interface */ + arm_gic_cpuif_setup(); + + /* TODO: This setup is needed only after a cold boot */ + arm_gic_pcpu_distif_setup(); +} + +/******************************************************************************* + * FVP handler called when a power domain has just been powered on after + * having been suspended earlier. The target_state encodes the low power state + * that each level has woken up from. + * TODO: At the moment we reuse the on finisher and reinitialize the secure + * context. Need to implement a separate suspend finisher. + ******************************************************************************/ +void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ + /* + * Nothing to be done on waking up from retention from CPU level. + */ + if (target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_RET) + return; + + fvp_pwr_domain_on_finish(target_state); +} + +/******************************************************************************* + * FVP handlers to shutdown/reboot the system + ******************************************************************************/ +static void __dead2 fvp_system_off(void) +{ + /* Write the System Configuration Control Register */ + mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, + V2M_CFGCTRL_START | + V2M_CFGCTRL_RW | + V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); + wfi(); + ERROR("FVP System Off: operation not handled.\n"); + panic(); +} + +static void __dead2 fvp_system_reset(void) +{ + /* Write the System Configuration Control Register */ + mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, + V2M_CFGCTRL_START | + V2M_CFGCTRL_RW | + V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); + wfi(); + ERROR("FVP System Reset: operation not handled.\n"); + panic(); +} + +/******************************************************************************* + * Export the platform handlers to enable psci to invoke them + ******************************************************************************/ +static const plat_psci_ops_t fvp_plat_psci_ops = { + .cpu_standby = fvp_cpu_standby, + .pwr_domain_on = fvp_pwr_domain_on, + .pwr_domain_off = fvp_pwr_domain_off, + .pwr_domain_suspend = fvp_pwr_domain_suspend, + .pwr_domain_on_finish = fvp_pwr_domain_on_finish, + .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, + .system_off = fvp_system_off, + .system_reset = fvp_system_reset, + .validate_power_state = arm_validate_power_state, + .validate_ns_entrypoint = arm_validate_ns_entrypoint +}; + +/******************************************************************************* + * Export the platform specific psci ops & initialize the fvp power controller + ******************************************************************************/ +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + *psci_ops = &fvp_plat_psci_ops; + + /* Program the jump address */ + fvp_program_mailbox(sec_entrypoint); + return 0; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_private.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_private.h new file mode 100644 index 0000000..e88a45e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_private.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FVP_PRIVATE_H__ +#define __FVP_PRIVATE_H__ + +#include + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ + +void fvp_config_setup(void); + +void fvp_cci_init(void); +void fvp_cci_enable(void); +void fvp_cci_disable(void); + + +#endif /* __FVP_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_security.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_security.c new file mode 100644 index 0000000..0cf8450 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_security.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/* + * We assume that all security programming is done by the primary core. + */ +void plat_arm_security_setup(void) +{ + /* + * The Base FVP has a TrustZone address space controller, the Foundation + * FVP does not. Trying to program the device on the foundation FVP will + * cause an abort. + * + * If the platform had additional peripheral specific security + * configurations, those would be configured here. + */ + + if (get_arm_config()->flags & ARM_CONFIG_HAS_TZC) + arm_tzc_setup(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_topology.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_topology.c new file mode 100644 index 0000000..a212eda --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/fvp_topology.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "drivers/pwrc/fvp_pwrc.h" + +/* + * The FVP power domain tree does not have a single system level power domain + * i.e. a single root node. The first entry in the power domain descriptor + * specifies the number of power domains at the highest power level. For the FVP + * this is 2 i.e. the number of cluster power domains. + */ +#define FVP_PWR_DOMAINS_AT_MAX_PWR_LVL ARM_CLUSTER_COUNT + +/* The FVP power domain tree descriptor */ +const unsigned char arm_power_domain_tree_desc[] = { + /* No of root nodes */ + FVP_PWR_DOMAINS_AT_MAX_PWR_LVL, + /* No of children for the first node */ + PLAT_ARM_CLUSTER0_CORE_COUNT, + /* No of children for the second node */ + PLAT_ARM_CLUSTER1_CORE_COUNT +}; + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + if (arm_check_mpidr(mpidr) == -1) + return -1; + + if (fvp_pwrc_read_psysr(mpidr) == PSYSR_INVALID) + return -1; + + return plat_arm_calc_core_pos(mpidr); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/include/plat_macros.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/include/plat_macros.S new file mode 100644 index 0000000..2feffbe --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/include/plat_macros.S @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __PLAT_MACROS_S__ +#define __PLAT_MACROS_S__ + +#include +#include +#include "../fvp_def.h" + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC registers whenever an + * unhandled exception is taken in BL3-1. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_print_gic_regs + /* + * Detect if we're using the base memory map or + * the legacy VE memory map + */ + mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID) + ldr w16, [x0] + /* Extract BLD (12th - 15th bits) from the SYS_ID */ + ubfx x16, x16, #V2M_SYS_ID_BLD_SHIFT, #4 + /* Check if VE mmap */ + cmp w16, #BLD_GIC_VE_MMAP + b.eq use_ve_mmap + /* Check if Cortex-A53/A57 mmap */ + cmp w16, #BLD_GIC_A53A57_MMAP + b.ne exit_print_gic_regs + mov_imm x17, BASE_GICC_BASE + mov_imm x16, BASE_GICD_BASE + b print_gicc_regs +use_ve_mmap: + mov_imm x17, VE_GICC_BASE + mov_imm x16, VE_GICD_BASE +print_gicc_regs: + arm_print_gic_regs + .endm + +#endif /* __PLAT_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/include/platform_def.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/include/platform_def.h new file mode 100644 index 0000000..155216a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/include/platform_def.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include +#include +#include +#include +#include +#include "../fvp_def.h" + + +/* + * Most platform porting definitions provided by included headers + */ + +/* + * Required ARM standard platform porting definitions + */ +#define PLAT_ARM_CLUSTER0_CORE_COUNT 4 +#define PLAT_ARM_CLUSTER1_CORE_COUNT 4 + +#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 +#define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ + +#define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000 +#define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ + +/* No SCP in FVP */ +#define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x0) + +#define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x780000000) + +#define PLAT_ARM_SHARED_RAM_CACHED 1 + +/* + * Load address of BL3-3 for this platform port + */ +#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000) + + +/* + * PL011 related constants + */ +#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ + +#define PLAT_ARM_CRASH_UART_BASE V2M_IOFPGA_UART1_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ + +#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE +#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ + +/* CCI related constants */ +#define PLAT_ARM_CCI_BASE 0x2c090000 +#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 +#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 + +/* System timer related constants */ +#define PLAT_ARM_NSTIMER_FRAME_ID 1 + +/* TrustZone controller related constants + * + * Currently only filters 0 and 2 are connected on Base FVP. + * Filter 0 : CPU clusters (no access to DRAM by default) + * Filter 1 : not connected + * Filter 2 : LCDs (access to VRAM allowed by default) + * Filter 3 : not connected + * Programming unconnected filters will have no effect at the + * moment. These filter could, however, be connected in future. + * So care should be taken not to configure the unused filters. + * + * Allow only non-secure access to all DRAM to supported devices. + * Give access to the CPUs and Virtio. Some devices + * would normally use the default ID so allow that too. + */ +#define PLAT_ARM_TZC_BASE 0x2a4a0000 +#define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT(0) + +#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ + TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ + TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ + TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ + TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ + TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) + + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/include/platform_oid.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/include/platform_oid.h new file mode 100644 index 0000000..1e44cf7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/include/platform_oid.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "../../../../../include/plat/arm/board/common/board_arm_oid.h" + +/* + * Required platform OIDs + * (Provided by included header) + */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/platform.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/platform.mk new file mode 100644 index 0000000..51b718e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/platform.mk @@ -0,0 +1,69 @@ +# +# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +PLAT_INCLUDES := -Iplat/arm/board/fvp/include + + +PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/aarch64/fvp_common.c + +BL1_SOURCES += drivers/io/io_semihosting.c \ + lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + lib/semihosting/semihosting.c \ + lib/semihosting/aarch64/semihosting_call.S \ + plat/arm/board/fvp/aarch64/fvp_helpers.S \ + plat/arm/board/fvp/fvp_bl1_setup.c \ + plat/arm/board/fvp/fvp_io_storage.c + +BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c \ + drivers/io/io_semihosting.c \ + drivers/delay_timer/delay_timer.c \ + lib/semihosting/semihosting.c \ + lib/semihosting/aarch64/semihosting_call.S \ + plat/arm/board/fvp/fvp_bl2_setup.c \ + plat/arm/board/fvp/fvp_io_storage.c \ + plat/arm/board/fvp/fvp_security.c + +BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + plat/arm/board/fvp/fvp_bl31_setup.c \ + plat/arm/board/fvp/fvp_pm.c \ + plat/arm/board/fvp/fvp_security.c \ + plat/arm/board/fvp/fvp_topology.c \ + plat/arm/board/fvp/aarch64/fvp_helpers.S \ + plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c + +# Disable the PSCI platform compatibility layer +ENABLE_PLAT_COMPAT := 0 + +include plat/arm/board/common/board_common.mk +include plat/arm/common/arm_common.mk diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/tsp/fvp_tsp_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/tsp/fvp_tsp_setup.c new file mode 100644 index 0000000..64246db --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/tsp/fvp_tsp_setup.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "../fvp_private.h" + +void tsp_early_platform_setup(void) +{ + arm_tsp_early_platform_setup(); + + /* Initialize the platform config for future decision making */ + fvp_config_setup(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/tsp/tsp-fvp.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/tsp/tsp-fvp.mk new file mode 100644 index 0000000..99db2f4 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/fvp/tsp/tsp-fvp.mk @@ -0,0 +1,36 @@ +# +# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# TSP source files specific to FVP platform +BL32_SOURCES += plat/arm/board/fvp/fvp_topology.c \ + plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c \ + plat/arm/board/fvp/tsp/fvp_tsp_setup.c + +include plat/arm/common/tsp/arm_tsp.mk diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/aarch64/juno_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/aarch64/juno_helpers.S new file mode 100644 index 0000000..ce41bae --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/aarch64/juno_helpers.S @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "../juno_def.h" + + + .globl plat_reset_handler + + + /* -------------------------------------------------------------------- + * void plat_reset_handler(void); + * + * For Juno r0: + * - Implement workaround for defect id 831273 by enabling an event + * stream every 65536 cycles. + * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 + * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 + * + * For Juno r1: + * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 + * Note that: + * - The default value for the L2 Tag RAM latency for Cortex-A57 is + * suitable. + * - Defect #831273 doesn't affect Juno r1. + * -------------------------------------------------------------------- + */ +func plat_reset_handler + /* -------------------------------------------------------------------- + * Determine whether this code is running on Juno r0 or Juno r1. + * Keep this information in x2. + * -------------------------------------------------------------------- + */ + /* Read the V2M SYS_ID register */ + mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID) + ldr w1, [x0] + /* Extract board revision from the SYS_ID */ + ubfx x1, x1, #V2M_SYS_ID_REV_SHIFT, #4 + /* + * On Juno R0: x2 := REV_JUNO_R0 - 1 = 0 + * On Juno R1: x2 := REV_JUNO_R1 - 1 = 1 + */ + sub x2, x1, #1 + + /* -------------------------------------------------------------------- + * Determine whether this code is executed on a Cortex-A53 or on a + * Cortex-A57 core. + * -------------------------------------------------------------------- + */ + mrs x0, midr_el1 + ubfx x1, x0, MIDR_PN_SHIFT, #12 + cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK) + b.eq A57 + + /* Nothing needs to be done for the Cortex-A53 on Juno r1 */ + cbz x2, apply_831273 + ret + +A57: + /* -------------------------------------------------------------------- + * Cortex-A57 specific settings + * -------------------------------------------------------------------- + */ + + /* Change the L2 Data RAM latency to 3 cycles */ + mov x0, #L2_DATA_RAM_LATENCY_3_CYCLES + cbnz x2, apply_l2_ram_latencies + /* On Juno r0, also change the L2 Tag RAM latency to 3 cycles */ + orr x0, x0, #(L2_TAG_RAM_LATENCY_3_CYCLES << \ + L2CTLR_TAG_RAM_LATENCY_SHIFT) +apply_l2_ram_latencies: + msr L2CTLR_EL1, x0 + + /* Juno r1 doesn't suffer from defect #831273 */ + cbnz x2, ret + +apply_831273: + /* -------------------------------------------------------------------- + * On Juno r0, enable the event stream every 65536 cycles + * -------------------------------------------------------------------- + */ + mov x0, #(0xf << EVNTI_SHIFT) + orr x0, x0, #EVNTEN_BIT + msr CNTKCTL_EL1, x0 +ret: + isb + ret +endfunc plat_reset_handler diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/include/plat_macros.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/include/plat_macros.S new file mode 100644 index 0000000..db0c1d2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/include/plat_macros.S @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __PLAT_MACROS_S__ +#define __PLAT_MACROS_S__ + +#include + +/* + * Required platform porting macros + * (Provided by included headers) + */ + + +#endif /* __PLAT_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/include/platform_def.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/include/platform_def.h new file mode 100644 index 0000000..ba93254 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/include/platform_def.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../juno_def.h" + + +/* + * Most platform porting definitions provided by included headers + */ + +/* + * Required ARM standard platform porting definitions + */ +#define PLAT_ARM_CLUSTER0_CORE_COUNT 2 +#define PLAT_ARM_CLUSTER1_CORE_COUNT 4 + +/* Use the bypass address */ +#define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET + +/* + * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB + * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of + * flash + */ +#if TRUSTED_BOARD_BOOT +#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 +#else +#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 +#endif /* TRUSTED_BOARD_BOOT */ + + +/* CCI related constants */ +#define PLAT_ARM_CCI_BASE 0x2c090000 +#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 +#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 + +/* TZC related constants */ +#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) + +/* + * Required ARM CSS based platform porting definitions + */ + +/* GIC related constants (no GICR in GIC-400) */ +#define PLAT_CSS_GICD_BASE 0x2c010000 +#define PLAT_CSS_GICR_BASE 0x0 +#define PLAT_CSS_GICC_BASE 0x2c02f000 +#define PLAT_CSS_GICH_BASE 0x2c04f000 +#define PLAT_CSS_GICV_BASE 0x2c06f000 + +#define PLAT_CSS_IRQ_SEC_LIST CSS_IRQ_MHU, \ + CSS_IRQ_GPU_SMMU_0, \ + CSS_IRQ_TZC, \ + CSS_IRQ_TZ_WDOG, \ + CSS_IRQ_SEC_SYS_TIMER, \ + JUNO_IRQ_DMA_SMMU, \ + JUNO_IRQ_HDLCD0_SMMU, \ + JUNO_IRQ_HDLCD1_SMMU, \ + JUNO_IRQ_USB_SMMU, \ + JUNO_IRQ_THIN_LINKS_SMMU, \ + JUNO_IRQ_SEC_I2C, \ + JUNO_IRQ_GPU_SMMU_1, \ + JUNO_IRQ_ETR_SMMU + +/* + * Required ARM CSS SoC based platform porting definitions + */ + +/* CSS SoC NIC-400 Global Programmers View (GPV) */ +#define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 + + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/include/platform_oid.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/include/platform_oid.h new file mode 100644 index 0000000..1e44cf7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/include/platform_oid.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "../../../../../include/plat/arm/board/common/board_arm_oid.h" + +/* + * Required platform OIDs + * (Provided by included header) + */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/juno_def.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/juno_def.h new file mode 100644 index 0000000..143cf00 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/juno_def.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __JUNO_DEF_H__ +#define __JUNO_DEF_H__ + + +/******************************************************************************* + * Juno memory map related constants + ******************************************************************************/ + +/* Board revisions */ +#define REV_JUNO_R0 0x1 /* Rev B */ +#define REV_JUNO_R1 0x2 /* Rev C */ + +/* Bypass offset from start of NOR flash */ +#define BL1_ROM_BYPASS_OFFSET 0x03EC0000 + +#define EMMC_BASE 0x0c000000 +#define EMMC_SIZE 0x04000000 + +#define PSRAM_BASE 0x14000000 +#define PSRAM_SIZE 0x02000000 + + +/******************************************************************************* + * TZC-400 related constants + ******************************************************************************/ +#define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */ +#define TZC400_NSAID_PCIE 1 +#define TZC400_NSAID_HDLCD0 2 +#define TZC400_NSAID_HDLCD1 3 +#define TZC400_NSAID_USB 4 +#define TZC400_NSAID_DMA330 5 +#define TZC400_NSAID_THINLINKS 6 +#define TZC400_NSAID_AP 9 +#define TZC400_NSAID_GPU 10 +#define TZC400_NSAID_SCP 11 +#define TZC400_NSAID_CORESIGHT 12 + +/******************************************************************************* + * MMU-401 related constants + ******************************************************************************/ +#define MMU401_SSD_OFFSET 0x4000 +#define MMU401_DMA330_BASE 0x7fb00000 + +/******************************************************************************* + * Interrupt handling constants + ******************************************************************************/ +#define JUNO_IRQ_DMA_SMMU 126 +#define JUNO_IRQ_HDLCD0_SMMU 128 +#define JUNO_IRQ_HDLCD1_SMMU 130 +#define JUNO_IRQ_USB_SMMU 132 +#define JUNO_IRQ_THIN_LINKS_SMMU 134 +#define JUNO_IRQ_SEC_I2C 137 +#define JUNO_IRQ_GPU_SMMU_1 73 +#define JUNO_IRQ_ETR_SMMU 75 + +#endif /* __JUNO_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/juno_security.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/juno_security.c new file mode 100644 index 0000000..f9386ca --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/juno_security.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "juno_def.h" + + +/******************************************************************************* + * Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs + * assigned to Non-Secure except some for the DMA-330. Assign those back to the + * Non-Secure world as well, otherwise EL1 may end up erroneously generating + * (untranslated) Secure transactions if it turns the SMMU on. + ******************************************************************************/ +static void init_mmu401(void) +{ + uint32_t reg = mmio_read_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET); + reg |= 0x1FF; + mmio_write_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET, reg); +} + +/******************************************************************************* + * Program CSS-NIC400 to allow non-secure access to some CSS regions. + ******************************************************************************/ +static void css_init_nic400(void) +{ + /* Note: This is the NIC-400 device on the CSS */ + mmio_write_32(PLAT_SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE), + ~0); +} + +/******************************************************************************* + * Initialize the secure environment. + ******************************************************************************/ +void plat_arm_security_setup(void) +{ + /* Initialize the TrustZone Controller */ + arm_tzc_setup(); + /* Do ARM CSS internal NIC setup */ + css_init_nic400(); + /* Do ARM CSS SoC security setup */ + soc_css_security_setup(); + /* Initialize the SMMU SSD tables*/ + init_mmu401(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/platform.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/platform.mk new file mode 100644 index 0000000..b80cfb3 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/platform.mk @@ -0,0 +1,61 @@ +# +# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +PLAT_INCLUDES := -Iplat/arm/board/juno/include + +PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/aarch64/juno_helpers.S + +BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S + +BL2_SOURCES += plat/arm/board/juno/juno_security.c \ + +BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S + +# Enable workarounds for selected Cortex-A57 erratas. +ERRATA_A57_806969 := 0 +ERRATA_A57_813420 := 1 + +# Enable option to skip L1 data cache flush during the Cortex-A57 cluster +# power down sequence +SKIP_A57_L1_FLUSH_PWR_DWN := 1 + +# Disable the PSCI platform compatibility layer +ENABLE_PLAT_COMPAT := 0 + +include plat/arm/board/common/board_css.mk +include plat/arm/common/arm_common.mk +include plat/arm/soc/common/soc_css.mk +include plat/arm/css/common/css_common.mk + +ifeq (${KEY_ALG},ecdsa) + $(error "ECDSA key algorithm is not fully supported on Juno.") +endif diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/tsp/tsp-juno.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/tsp/tsp-juno.mk new file mode 100644 index 0000000..bb67012 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/board/juno/tsp/tsp-juno.mk @@ -0,0 +1,33 @@ +# +# Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +BL32_SOURCES += plat/arm/css/common/css_topology.c + +include plat/arm/common/tsp/arm_tsp.mk diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/aarch64/arm_common.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/aarch64/arm_common.c new file mode 100644 index 0000000..48b4ac8 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/aarch64/arm_common.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include + + +static const int cci_map[] = { + PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX, + PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX +}; + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak plat_get_ns_image_entrypoint + + +/******************************************************************************* + * Macro generating the code for the function setting up the pagetables as per + * the platform memory map & initialize the mmu, for the given exception level + ******************************************************************************/ +#if USE_COHERENT_MEM +#define DEFINE_CONFIGURE_MMU_EL(_el) \ + void arm_configure_mmu_el##_el(unsigned long total_base, \ + unsigned long total_size, \ + unsigned long ro_start, \ + unsigned long ro_limit, \ + unsigned long coh_start, \ + unsigned long coh_limit) \ + { \ + mmap_add_region(total_base, total_base, \ + total_size, \ + MT_MEMORY | MT_RW | MT_SECURE); \ + mmap_add_region(ro_start, ro_start, \ + ro_limit - ro_start, \ + MT_MEMORY | MT_RO | MT_SECURE); \ + mmap_add_region(coh_start, coh_start, \ + coh_limit - coh_start, \ + MT_DEVICE | MT_RW | MT_SECURE); \ + mmap_add(plat_arm_mmap); \ + init_xlat_tables(); \ + \ + enable_mmu_el##_el(0); \ + } +#else +#define DEFINE_CONFIGURE_MMU_EL(_el) \ + void arm_configure_mmu_el##_el(unsigned long total_base, \ + unsigned long total_size, \ + unsigned long ro_start, \ + unsigned long ro_limit) \ + { \ + mmap_add_region(total_base, total_base, \ + total_size, \ + MT_MEMORY | MT_RW | MT_SECURE); \ + mmap_add_region(ro_start, ro_start, \ + ro_limit - ro_start, \ + MT_MEMORY | MT_RO | MT_SECURE); \ + mmap_add(plat_arm_mmap); \ + init_xlat_tables(); \ + \ + enable_mmu_el##_el(0); \ + } +#endif + +/* Define EL1 and EL3 variants of the function initialising the MMU */ +DEFINE_CONFIGURE_MMU_EL(1) +DEFINE_CONFIGURE_MMU_EL(3) + + +unsigned long plat_get_ns_image_entrypoint(void) +{ + return PLAT_ARM_NS_IMAGE_OFFSET; +} + +/******************************************************************************* + * Gets SPSR for BL32 entry + ******************************************************************************/ +uint32_t arm_get_spsr_for_bl32_entry(void) +{ + /* + * The Secure Payload Dispatcher service is responsible for + * setting the SPSR prior to entry into the BL3-2 image. + */ + return 0; +} + +/******************************************************************************* + * Gets SPSR for BL33 entry + ******************************************************************************/ +uint32_t arm_get_spsr_for_bl33_entry(void) +{ + unsigned long el_status; + unsigned int mode; + uint32_t spsr; + + /* Figure out what mode we enter the non-secure world in */ + el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; + el_status &= ID_AA64PFR0_ELX_MASK; + + mode = (el_status) ? MODE_EL2 : MODE_EL1; + + /* + * TODO: Consider the possibility of specifying the SPSR in + * the FIP ToC and allowing the platform to have a say as + * well. + */ + spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + return spsr; +} + + +void arm_cci_init(void) +{ + cci_init(PLAT_ARM_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/aarch64/arm_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/aarch64/arm_helpers.S new file mode 100644 index 0000000..87179da --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/aarch64/arm_helpers.S @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + + .weak plat_arm_calc_core_pos + .weak plat_my_core_pos + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl platform_mem_init + + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void) + * This function uses the plat_arm_calc_core_pos() + * definition to get the index of the calling CPU. + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_arm_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_arm_calc_core_pos(uint64_t mpidr) + * Helper function to calculate the core position. + * With this function: CorePos = (ClusterId * 4) + + * CoreId + * ----------------------------------------------------- + */ +func plat_arm_calc_core_pos + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc plat_arm_calc_core_pos + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0, x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, PLAT_ARM_CRASH_UART_BASE + mov_imm x1, PLAT_ARM_CRASH_UART_CLK_IN_HZ + mov_imm x2, ARM_CONSOLE_BAUDRATE + b console_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, PLAT_ARM_CRASH_UART_BASE + b console_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------------------------------- + * We don't need to carry out any memory initialization on ARM + * platforms. The Secure RAM is accessible straight away. + * --------------------------------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_bl1_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_bl1_setup.c new file mode 100644 index 0000000..6970aa3 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_bl1_setup.c @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "../../bl1/bl1_private.h" + + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ +#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif + + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak bl1_early_platform_setup +#pragma weak bl1_plat_arch_setup +#pragma weak bl1_platform_setup +#pragma weak bl1_plat_sec_mem_layout +#pragma weak bl1_plat_set_bl2_ep_info + + +/* Data structure which holds the extents of the trusted SRAM for BL1*/ +static meminfo_t bl1_tzram_layout; + +meminfo_t *bl1_plat_sec_mem_layout(void) +{ + return &bl1_tzram_layout; +} + +/******************************************************************************* + * BL1 specific platform actions shared between ARM standard platforms. + ******************************************************************************/ +void arm_bl1_early_platform_setup(void) +{ + const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; + + /* Initialize the console to provide early debug support */ + console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE); + + /* Allow BL1 to see the whole Trusted RAM */ + bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; + bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; + + /* Calculate how much RAM BL1 is using and how much remains free */ + bl1_tzram_layout.free_base = ARM_BL_RAM_BASE; + bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE; + reserve_mem(&bl1_tzram_layout.free_base, + &bl1_tzram_layout.free_size, + BL1_RAM_BASE, + bl1_size); +} + +void bl1_early_platform_setup(void) +{ + arm_bl1_early_platform_setup(); + + /* + * Initialize CCI for this cluster during cold boot. + * No need for locks as no other CPU is active. + */ + arm_cci_init(); + /* + * Enable CCI coherency for the primary CPU's cluster. + */ + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); +} + +/****************************************************************************** + * Perform the very early platform specific architecture setup shared between + * ARM standard platforms. This only does basic initialization. Later + * architectural setup (bl1_arch_setup()) does not do anything platform + * specific. + *****************************************************************************/ +void arm_bl1_plat_arch_setup(void) +{ + arm_configure_mmu_el3(bl1_tzram_layout.total_base, + bl1_tzram_layout.total_size, + BL1_RO_BASE, + BL1_RO_LIMIT +#if USE_COHERENT_MEM + , BL1_COHERENT_RAM_BASE, + BL1_COHERENT_RAM_LIMIT +#endif + ); +} + +void bl1_plat_arch_setup(void) +{ + arm_bl1_plat_arch_setup(); +} + +/* + * Perform the platform specific architecture setup shared between + * ARM standard platforms. + */ +void arm_bl1_platform_setup(void) +{ + /* Initialise the IO layer and register platform IO devices */ + plat_arm_io_setup(); +} + +void bl1_platform_setup(void) +{ + arm_bl1_platform_setup(); +} + +/******************************************************************************* + * Before calling this function BL2 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL2 and set SPSR and security state. + * On ARM standard platforms we only set the security state of the entrypoint + ******************************************************************************/ +void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image, + entry_point_info_t *bl2_ep) +{ + SET_SECURITY_STATE(bl2_ep->h.attr, SECURE); + bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_bl2_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_bl2_setup.c new file mode 100644 index 0000000..a44ec1d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_bl2_setup.c @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + + +/* + * The next 2 constants identify the extents of the code & RO data region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. + */ +#define BL2_RO_BASE (unsigned long)(&__RO_START__) +#define BL2_RO_LIMIT (unsigned long)(&__RO_END__) + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ +#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif + +/* Data structure which holds the extents of the trusted SRAM for BL2 */ +static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); + + +/******************************************************************************* + * This structure represents the superset of information that is passed to + * BL3-1, e.g. while passing control to it from BL2, bl31_params + * and other platform specific params + ******************************************************************************/ +typedef struct bl2_to_bl31_params_mem { + bl31_params_t bl31_params; + image_info_t bl31_image_info; + image_info_t bl32_image_info; + image_info_t bl33_image_info; + entry_point_info_t bl33_ep_info; + entry_point_info_t bl32_ep_info; + entry_point_info_t bl31_ep_info; +} bl2_to_bl31_params_mem_t; + + +static bl2_to_bl31_params_mem_t bl31_params_mem; + + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak bl2_early_platform_setup +#pragma weak bl2_platform_setup +#pragma weak bl2_plat_arch_setup +#pragma weak bl2_plat_sec_mem_layout +#pragma weak bl2_plat_get_bl31_params +#pragma weak bl2_plat_get_bl31_ep_info +#pragma weak bl2_plat_flush_bl31_params +#pragma weak bl2_plat_set_bl31_ep_info +#pragma weak bl2_plat_get_bl30_meminfo +#pragma weak bl2_plat_get_bl32_meminfo +#pragma weak bl2_plat_set_bl32_ep_info +#pragma weak bl2_plat_get_bl33_meminfo +#pragma weak bl2_plat_set_bl33_ep_info + + +meminfo_t *bl2_plat_sec_mem_layout(void) +{ + return &bl2_tzram_layout; +} + +/******************************************************************************* + * This function assigns a pointer to the memory that the platform has kept + * aside to pass platform specific and trusted firmware related information + * to BL31. This memory is allocated by allocating memory to + * bl2_to_bl31_params_mem_t structure which is a superset of all the + * structure whose information is passed to BL31 + * NOTE: This function should be called only once and should be done + * before generating params to BL31 + ******************************************************************************/ +bl31_params_t *bl2_plat_get_bl31_params(void) +{ + bl31_params_t *bl2_to_bl31_params; + + /* + * Initialise the memory for all the arguments that needs to + * be passed to BL3-1 + */ + memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); + + /* Assign memory for TF related information */ + bl2_to_bl31_params = &bl31_params_mem.bl31_params; + SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); + + /* Fill BL3-1 related information */ + bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, + VERSION_1, 0); + + /* Fill BL3-2 related information if it exists */ +#if BL32_BASE + bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, + VERSION_1, 0); + bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, + VERSION_1, 0); +#endif + + /* Fill BL3-3 related information */ + bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, + PARAM_EP, VERSION_1, 0); + + /* BL3-3 expects to receive the primary CPU MPID (through x0) */ + bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); + + bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, + VERSION_1, 0); + + return bl2_to_bl31_params; +} + +/* Flush the TF params and the TF plat params */ +void bl2_plat_flush_bl31_params(void) +{ + flush_dcache_range((unsigned long)&bl31_params_mem, + sizeof(bl2_to_bl31_params_mem_t)); +} + +/******************************************************************************* + * This function returns a pointer to the shared memory that the platform + * has kept to point to entry point information of BL31 to BL2 + ******************************************************************************/ +struct entry_point_info *bl2_plat_get_bl31_ep_info(void) +{ +#if DEBUG + bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL; +#endif + + return &bl31_params_mem.bl31_ep_info; +} + +/******************************************************************************* + * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 + * in x0. This memory layout is sitting at the base of the free trusted SRAM. + * Copy it to a safe location before its reclaimed by later BL2 functionality. + ******************************************************************************/ +void arm_bl2_early_platform_setup(meminfo_t *mem_layout) +{ + /* Initialize the console to provide early debug support */ + console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE); + + /* Setup the BL2 memory layout */ + bl2_tzram_layout = *mem_layout; + + /* Initialise the IO layer and register platform IO devices */ + plat_arm_io_setup(); +} + +void bl2_early_platform_setup(meminfo_t *mem_layout) +{ + arm_bl2_early_platform_setup(mem_layout); +} + +/* + * Perform ARM standard platform setup. + */ +void arm_bl2_platform_setup(void) +{ + /* Initialize the secure environment */ + plat_arm_security_setup(); +} + +void bl2_platform_setup(void) +{ + arm_bl2_platform_setup(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only initializes the mmu in a quick and dirty way. + ******************************************************************************/ +void arm_bl2_plat_arch_setup(void) +{ + arm_configure_mmu_el1(bl2_tzram_layout.total_base, + bl2_tzram_layout.total_size, + BL2_RO_BASE, + BL2_RO_LIMIT +#if USE_COHERENT_MEM + , BL2_COHERENT_RAM_BASE, + BL2_COHERENT_RAM_LIMIT +#endif + ); +} + +void bl2_plat_arch_setup(void) +{ + arm_bl2_plat_arch_setup(); +} + +/******************************************************************************* + * Populate the extents of memory available for loading BL3-0 (if used), + * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. + ******************************************************************************/ +void bl2_plat_get_bl30_meminfo(meminfo_t *bl30_meminfo) +{ + *bl30_meminfo = bl2_tzram_layout; +} + +/******************************************************************************* + * Before calling this function BL3-1 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL3-1 and set SPSR and security state. + * On ARM standard platforms we only set the security state of the entrypoint + ******************************************************************************/ +void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, + entry_point_info_t *bl31_ep_info) +{ + SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); + bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); +} + + +/******************************************************************************* + * Before calling this function BL3-2 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL3-2 and set SPSR and security state. + * On ARM standard platforms we only set the security state of the entrypoint + ******************************************************************************/ +void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, + entry_point_info_t *bl32_ep_info) +{ + SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); + bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); +} + +/******************************************************************************* + * Before calling this function BL3-3 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL3-3 and set SPSR and security state. + * On ARM standard platforms we only set the security state of the entrypoint + ******************************************************************************/ +void bl2_plat_set_bl33_ep_info(image_info_t *image, + entry_point_info_t *bl33_ep_info) +{ + + SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); + bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); +} + +/******************************************************************************* + * Populate the extents of memory available for loading BL32 + ******************************************************************************/ +void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) +{ + /* + * Populate the extents of memory available for loading BL32. + */ + bl32_meminfo->total_base = BL32_BASE; + bl32_meminfo->free_base = BL32_BASE; + bl32_meminfo->total_size = + (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; + bl32_meminfo->free_size = + (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; +} + + +/******************************************************************************* + * Populate the extents of memory available for loading BL33 + ******************************************************************************/ +void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) +{ + bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; + bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; + bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; + bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_bl31_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_bl31_setup.c new file mode 100644 index 0000000..899463e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_bl31_setup.c @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/* + * The next 3 constants identify the extents of the code, RO data region and the + * limit of the BL3-1 image. These addresses are used by the MMU setup code and + * therefore they must be page-aligned. It is the responsibility of the linker + * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_RO_BASE (unsigned long)(&__RO_START__) +#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +#define BL31_END (unsigned long)(&__BL31_END__) + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif + +/* + * Placeholder variables for copying the arguments that have been passed to + * BL3-1 from BL2. + */ +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak bl31_early_platform_setup +#pragma weak bl31_platform_setup +#pragma weak bl31_plat_arch_setup +#pragma weak bl31_plat_get_next_image_ep_info +#pragma weak plat_get_syscnt_freq + + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for the + * security state specified. BL3-3 corresponds to the non-secure image type + * while BL3-2 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + assert(sec_state_is_valid(type)); + next_image_info = (type == NON_SECURE) + ? &bl33_image_ep_info : &bl32_image_ep_info; + /* + * None of the images on the ARM development platforms can have 0x0 + * as the entrypoint + */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +/******************************************************************************* + * Perform any BL3-1 early platform setup common to ARM standard platforms. + * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 + * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be + * done before the MMU is initialized so that the memory layout can be used + * while creating page tables. BL2 has flushed this information to memory, so + * we are guaranteed to pick up good data. + ******************************************************************************/ +void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +{ + /* Initialize the console to provide early debug support */ + console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE); + +#if RESET_TO_BL31 + /* There are no parameters from BL2 if BL3-1 is a reset vector */ + assert(from_bl2 == NULL); + assert(plat_params_from_bl2 == NULL); + + /* Populate entry point information for BL3-2 and BL3-3 */ + SET_PARAM_HEAD(&bl32_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); + + SET_PARAM_HEAD(&bl33_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + /* + * Tell BL3-1 where the non-trusted software image + * is located and the entry state information + */ + bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); + bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + +#else + /* + * Check params passed from BL2 should not be NULL, + */ + assert(from_bl2 != NULL); + assert(from_bl2->h.type == PARAM_BL31); + assert(from_bl2->h.version >= VERSION_1); + /* + * In debug builds, we pass a special value in 'plat_params_from_bl2' + * to verify platform parameters from BL2 to BL3-1. + * In release builds, it's not used. + */ + assert(((unsigned long long)plat_params_from_bl2) == + ARM_BL31_PLAT_PARAM_VAL); + + /* + * Copy BL3-2 and BL3-3 entry point information. + * They are stored in Secure RAM, in BL2's address space. + */ + bl32_image_ep_info = *from_bl2->bl32_ep_info; + bl33_image_ep_info = *from_bl2->bl33_ep_info; +#endif +} + +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +{ + arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2); + + /* + * Initialize CCI for this cluster during cold boot. + * No need for locks as no other CPU is active. + */ + arm_cci_init(); + + /* + * Enable CCI coherency for the primary CPU's cluster. + * Earlier bootloader stages might already do this (e.g. Trusted + * Firmware's BL1 does it) but we can't assume so. There is no harm in + * executing this code twice anyway. + * Platform specific PSCI code will enable coherency for other + * clusters. + */ + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); +} + +/******************************************************************************* + * Perform any BL3-1 platform setup common to ARM standard platforms + ******************************************************************************/ +void arm_bl31_platform_setup(void) +{ + unsigned int reg_val; + + /* Initialize the gic cpu and distributor interfaces */ + plat_arm_gic_init(); + arm_gic_setup(); + +#if RESET_TO_BL31 + /* + * Do initial security configuration to allow DRAM/device access + * (if earlier BL has not already done so). + */ + plat_arm_security_setup(); + +#endif /* RESET_TO_BL31 */ + + /* Enable and initialize the System level generic timer */ + mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, + CNTCR_FCREQ(0) | CNTCR_EN); + + /* Allow access to the System counter timer module */ + reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); + reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); + reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); + mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); + + reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); + mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); + + /* Initialize power controller before setting up topology */ + plat_arm_pwrc_setup(); +} + +void bl31_platform_setup(void) +{ + arm_bl31_platform_setup(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the mmu in a quick and dirty way. + ******************************************************************************/ +void arm_bl31_plat_arch_setup(void) +{ + arm_configure_mmu_el3(BL31_RO_BASE, + (BL31_END - BL31_RO_BASE), + BL31_RO_BASE, + BL31_RO_LIMIT +#if USE_COHERENT_MEM + , BL31_COHERENT_RAM_BASE, + BL31_COHERENT_RAM_LIMIT +#endif + ); +} + +void bl31_plat_arch_setup(void) +{ + arm_bl31_plat_arch_setup(); +} + +uint64_t plat_get_syscnt_freq(void) +{ + uint64_t counter_base_frequency; + + /* Read the frequency from Frequency modes table */ + counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); + + /* The first entry of the frequency modes table must not be 0 */ + if (counter_base_frequency == 0) + panic(); + + return counter_base_frequency; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_common.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_common.mk new file mode 100644 index 0000000..eb5ae11 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_common.mk @@ -0,0 +1,134 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# On ARM standard platorms, the TSP can execute from Trusted SRAM, Trusted +# DRAM (if available) or the TZC secured area of DRAM. +# Trusted SRAM is the default. + +ARM_TSP_RAM_LOCATION := tsram +ifeq (${ARM_TSP_RAM_LOCATION}, tsram) + ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_SRAM_ID +else ifeq (${ARM_TSP_RAM_LOCATION}, tdram) + ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_DRAM_ID +else ifeq (${ARM_TSP_RAM_LOCATION}, dram) + ARM_TSP_RAM_LOCATION_ID = ARM_DRAM_ID +else + $(error "Unsupported ARM_TSP_RAM_LOCATION value") +endif + +# Process flags +$(eval $(call add_define,ARM_TSP_RAM_LOCATION_ID)) + +# For the original power-state parameter format, the State-ID can be encoded +# according to the recommended encoding or zero. This flag determines which +# State-ID encoding to be parsed. +ARM_RECOM_STATE_ID_ENC := 0 + +# If the PSCI_EXTENDED_STATE_ID is set, then the recommended state ID need to +# be used. Else throw a build error. +ifeq (${PSCI_EXTENDED_STATE_ID}, 1) + ifeq (${ARM_RECOM_STATE_ID_ENC}, 0) + $(error "Incompatible STATE_ID build option specified") + endif +endif + +# Process ARM_RECOM_STATE_ID_ENC flag +$(eval $(call assert_boolean,ARM_RECOM_STATE_ID_ENC)) +$(eval $(call add_define,ARM_RECOM_STATE_ID_ENC)) + +PLAT_INCLUDES += -Iinclude/common/tbbr \ + -Iinclude/plat/arm/common \ + -Iinclude/plat/arm/common/aarch64 + + +PLAT_BL_COMMON_SOURCES += lib/aarch64/xlat_tables.c \ + plat/arm/common/aarch64/arm_common.c \ + plat/arm/common/aarch64/arm_helpers.S \ + plat/common/aarch64/plat_common.c + +BL1_SOURCES += drivers/arm/cci/cci.c \ + drivers/arm/ccn/ccn.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + drivers/io/io_storage.c \ + plat/arm/common/arm_bl1_setup.c \ + plat/arm/common/arm_io_storage.c \ + plat/common/aarch64/platform_up_stack.S + +BL2_SOURCES += drivers/arm/tzc400/tzc400.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + drivers/io/io_storage.c \ + plat/arm/common/arm_bl2_setup.c \ + plat/arm/common/arm_io_storage.c \ + plat/arm/common/arm_security.c \ + plat/common/aarch64/platform_up_stack.S + +BL31_SOURCES += drivers/arm/cci/cci.c \ + drivers/arm/ccn/ccn.c \ + drivers/arm/gic/arm_gic.c \ + drivers/arm/gic/gic_v2.c \ + drivers/arm/gic/gic_v3.c \ + drivers/arm/tzc400/tzc400.c \ + plat/arm/common/arm_bl31_setup.c \ + plat/arm/common/arm_pm.c \ + plat/arm/common/arm_security.c \ + plat/arm/common/arm_topology.c \ + plat/common/plat_gic.c \ + plat/common/aarch64/platform_mp_stack.S \ + plat/common/aarch64/plat_psci_common.c + +ifneq (${TRUSTED_BOARD_BOOT},0) + + # By default, ARM platforms use RSA keys + KEY_ALG := rsa + + # Include common TBB sources + AUTH_SOURCES := drivers/auth/auth_mod.c \ + drivers/auth/crypto_mod.c \ + drivers/auth/img_parser_mod.c \ + drivers/auth/tbbr/tbbr_cot.c \ + + BL1_SOURCES += ${AUTH_SOURCES} + BL2_SOURCES += ${AUTH_SOURCES} + + MBEDTLS_KEY_ALG := ${KEY_ALG} + + # We expect to locate the *.mk files under the directories specified below + CRYPTO_LIB_MK := drivers/auth/mbedtls/mbedtls_crypto.mk + IMG_PARSER_LIB_MK := drivers/auth/mbedtls/mbedtls_x509.mk + + $(info Including ${CRYPTO_LIB_MK}) + include ${CRYPTO_LIB_MK} + + $(info Including ${IMG_PARSER_LIB_MK}) + include ${IMG_PARSER_LIB_MK} + +endif diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_io_storage.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_io_storage.c new file mode 100644 index 0000000..8488f12 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_io_storage.c @@ -0,0 +1,310 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include /* For ARRAY_SIZE */ +#include +#include +#include +#include +#include +#include +#include +#include + +/* IO devices */ +static const io_dev_connector_t *fip_dev_con; +static uintptr_t fip_dev_handle; +static const io_dev_connector_t *memmap_dev_con; +static uintptr_t memmap_dev_handle; + +static const io_block_spec_t fip_block_spec = { + .offset = PLAT_ARM_FIP_BASE, + .length = PLAT_ARM_FIP_MAX_SIZE +}; + +static const io_uuid_spec_t bl2_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, +}; + +static const io_uuid_spec_t bl30_uuid_spec = { + .uuid = UUID_SCP_FIRMWARE_BL30, +}; + +static const io_uuid_spec_t bl31_uuid_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, +}; + +static const io_uuid_spec_t bl32_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32, +}; + +static const io_uuid_spec_t bl33_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, +}; + +#if TRUSTED_BOARD_BOOT +static const io_uuid_spec_t bl2_cert_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2_CERT, +}; + +static const io_uuid_spec_t trusted_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_KEY_CERT, +}; + +static const io_uuid_spec_t bl30_key_cert_uuid_spec = { + .uuid = UUID_SCP_FIRMWARE_BL30_KEY_CERT, +}; + +static const io_uuid_spec_t bl31_key_cert_uuid_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31_KEY_CERT, +}; + +static const io_uuid_spec_t bl32_key_cert_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_KEY_CERT, +}; + +static const io_uuid_spec_t bl33_key_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33_KEY_CERT, +}; + +static const io_uuid_spec_t bl30_cert_uuid_spec = { + .uuid = UUID_SCP_FIRMWARE_BL30_CERT, +}; + +static const io_uuid_spec_t bl31_cert_uuid_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31_CERT, +}; + +static const io_uuid_spec_t bl32_cert_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_CERT, +}; + +static const io_uuid_spec_t bl33_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33_CERT, +}; +#endif /* TRUSTED_BOARD_BOOT */ + + +static int open_fip(const uintptr_t spec); +static int open_memmap(const uintptr_t spec); + +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int (*check)(const uintptr_t spec); +}; + +/* By default, ARM platforms load images from the FIP */ +static const struct plat_io_policy policies[] = { + [FIP_IMAGE_ID] = { + &memmap_dev_handle, + (uintptr_t)&fip_block_spec, + open_memmap + }, + [BL2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl2_uuid_spec, + open_fip + }, + [BL30_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl30_uuid_spec, + open_fip + }, + [BL31_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl31_uuid_spec, + open_fip + }, + [BL32_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_uuid_spec, + open_fip + }, + [BL33_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl33_uuid_spec, + open_fip + }, +#if TRUSTED_BOARD_BOOT + [BL2_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl2_cert_uuid_spec, + open_fip + }, + [TRUSTED_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&trusted_key_cert_uuid_spec, + open_fip + }, + [BL30_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl30_key_cert_uuid_spec, + open_fip + }, + [BL31_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl31_key_cert_uuid_spec, + open_fip + }, + [BL32_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_key_cert_uuid_spec, + open_fip + }, + [BL33_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl33_key_cert_uuid_spec, + open_fip + }, + [BL30_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl30_cert_uuid_spec, + open_fip + }, + [BL31_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl31_cert_uuid_spec, + open_fip + }, + [BL32_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_cert_uuid_spec, + open_fip + }, + [BL33_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl33_cert_uuid_spec, + open_fip + }, +#endif /* TRUSTED_BOARD_BOOT */ +}; + + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak plat_arm_io_setup +#pragma weak plat_arm_get_alt_image_source + + +static int open_fip(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + /* See if a Firmware Image Package is available */ + result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); + if (result == IO_SUCCESS) { + result = io_open(fip_dev_handle, spec, &local_image_handle); + if (result == IO_SUCCESS) { + VERBOSE("Using FIP\n"); + io_close(local_image_handle); + } + } + return result; +} + + +static int open_memmap(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); + if (result == IO_SUCCESS) { + result = io_open(memmap_dev_handle, spec, &local_image_handle); + if (result == IO_SUCCESS) { + VERBOSE("Using Memmap\n"); + io_close(local_image_handle); + } + } + return result; +} + + +void arm_io_setup(void) +{ + int io_result; + + io_result = register_io_dev_fip(&fip_dev_con); + assert(io_result == IO_SUCCESS); + + io_result = register_io_dev_memmap(&memmap_dev_con); + assert(io_result == IO_SUCCESS); + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, + &fip_dev_handle); + assert(io_result == IO_SUCCESS); + + io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, + &memmap_dev_handle); + assert(io_result == IO_SUCCESS); + + /* Ignore improbable errors in release builds */ + (void)io_result; +} + +void plat_arm_io_setup(void) +{ + arm_io_setup(); +} + +int plat_arm_get_alt_image_source( + unsigned int image_id __attribute__((unused)), + uintptr_t *dev_handle __attribute__((unused)), + uintptr_t *image_spec __attribute__((unused))) +{ + /* By default do not try an alternative */ + return IO_FAIL; +} + +/* Return an IO device handle and specification which can be used to access + * an image. Use this to enforce platform load policy */ +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result = IO_FAIL; + const struct plat_io_policy *policy; + + assert(image_id < ARRAY_SIZE(policies)); + + policy = &policies[image_id]; + result = policy->check(policy->image_spec); + if (result == IO_SUCCESS) { + *image_spec = policy->image_spec; + *dev_handle = *(policy->dev_handle); + } else { + VERBOSE("Trying alternative IO\n"); + result = plat_arm_get_alt_image_source(image_id, dev_handle, + image_spec); + } + + return result; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_pm.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_pm.c new file mode 100644 index 0000000..b225170 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_pm.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#if ARM_RECOM_STATE_ID_ENC +extern unsigned int arm_pm_idle_states[]; +#endif /* __ARM_RECOM_STATE_ID_ENC__ */ + + +#if !ARM_RECOM_STATE_ID_ENC +/******************************************************************************* + * ARM standard platform handler called to check the validity of the power state + * parameter. + ******************************************************************************/ +int arm_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int pstate = psci_get_pstate_type(power_state); + int pwr_lvl = psci_get_pstate_pwrlvl(power_state); + int i; + + assert(req_state); + + if (pwr_lvl > PLAT_MAX_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + /* Sanity check the requested state */ + if (pstate == PSTATE_TYPE_STANDBY) { + /* + * It's possible to enter standby only on power level 0 + * Ignore any other power level. + */ + if (pwr_lvl != ARM_PWR_LVL0) + return PSCI_E_INVALID_PARAMS; + + req_state->pwr_domain_state[ARM_PWR_LVL0] = + ARM_LOCAL_STATE_RET; + } else { + for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++) + req_state->pwr_domain_state[i] = + ARM_LOCAL_STATE_OFF; + } + + /* + * We expect the 'state id' to be zero. + */ + if (psci_get_pstate_id(power_state)) + return PSCI_E_INVALID_PARAMS; + + return PSCI_E_SUCCESS; +} + +#else +/******************************************************************************* + * ARM standard platform handler called to check the validity of the power + * state parameter. The power state parameter has to be a composite power + * state. + ******************************************************************************/ +int arm_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + unsigned int state_id; + int i; + + assert(req_state); + + /* + * Currently we are using a linear search for finding the matching + * entry in the idle power state array. This can be made a binary + * search if the number of entries justify the additional complexity. + */ + for (i = 0; !!arm_pm_idle_states[i]; i++) { + if (power_state == arm_pm_idle_states[i]) + break; + } + + /* Return error if entry not found in the idle state array */ + if (!arm_pm_idle_states[i]) + return PSCI_E_INVALID_PARAMS; + + i = 0; + state_id = psci_get_pstate_id(power_state); + + /* Parse the State ID and populate the state info parameter */ + while (state_id) { + req_state->pwr_domain_state[i++] = state_id & + ARM_LOCAL_PSTATE_MASK; + state_id >>= ARM_LOCAL_PSTATE_WIDTH; + } + + return PSCI_E_SUCCESS; +} +#endif /* __ARM_RECOM_STATE_ID_ENC__ */ + +/******************************************************************************* + * ARM standard platform handler called to check the validity of the non secure + * entrypoint. + ******************************************************************************/ +int arm_validate_ns_entrypoint(uintptr_t entrypoint) +{ + /* + * Check if the non secure entrypoint lies within the non + * secure DRAM. + */ + if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < + (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) + return PSCI_E_SUCCESS; + if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < + (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) + return PSCI_E_SUCCESS; + + return PSCI_E_INVALID_ADDRESS; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_security.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_security.c new file mode 100644 index 0000000..990d8d4 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_security.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak plat_arm_security_setup + + +/******************************************************************************* + * Initialize the TrustZone Controller for ARM standard platforms. + * Configure Region 0 with no access, Region 1 with secure access only, and + * the remaining DRAM regions access from the given Non-Secure masters. + ******************************************************************************/ +void arm_tzc_setup(void) +{ + INFO("Configuring TrustZone Controller\n"); + + tzc_init(PLAT_ARM_TZC_BASE); + + /* Disable filters. */ + tzc_disable_filters(); + + /* Region 0 set to no access by default */ + tzc_configure_region0(TZC_REGION_S_NONE, 0); + + /* Region 1 set to cover Secure part of DRAM */ + tzc_configure_region(PLAT_ARM_TZC_FILTERS, 1, + ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, + TZC_REGION_S_RDWR, + 0); + + /* Region 2 set to cover Non-Secure access to 1st DRAM address range. + * Apply the same configuration to given filters in the TZC. */ + tzc_configure_region(PLAT_ARM_TZC_FILTERS, 2, + ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, + TZC_REGION_S_NONE, + PLAT_ARM_TZC_NS_DEV_ACCESS); + + /* Region 3 set to cover Non-Secure access to 2nd DRAM address range */ + tzc_configure_region(PLAT_ARM_TZC_FILTERS, 3, + ARM_DRAM2_BASE, ARM_DRAM2_END, + TZC_REGION_S_NONE, + PLAT_ARM_TZC_NS_DEV_ACCESS); + + /* + * Raise an exception if a NS device tries to access secure memory + * TODO: Add interrupt handling support. + */ + tzc_set_action(TZC_ACTION_ERR); + + /* Enable filters. */ + tzc_enable_filters(); +} + +void plat_arm_security_setup(void) +{ + arm_tzc_setup(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_topology.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_topology.c new file mode 100644 index 0000000..cb0bb9c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/arm_topology.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#define get_arm_cluster_core_count(mpidr)\ + (((mpidr) & 0x100) ? PLAT_ARM_CLUSTER1_CORE_COUNT :\ + PLAT_ARM_CLUSTER0_CORE_COUNT) + +/* The power domain tree descriptor which need to be exported by ARM platforms */ +extern const unsigned char arm_power_domain_tree_desc[]; + + +/******************************************************************************* + * This function returns the ARM default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return arm_power_domain_tree_desc; +} + +/******************************************************************************* + * This function validates an MPIDR by checking whether it falls within the + * acceptable bounds. An error code (-1) is returned if an incorrect mpidr + * is passed. + ******************************************************************************/ +int arm_check_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) + return -1; + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= ARM_CLUSTER_COUNT) + return -1; + + /* Validate cpu_id by checking whether it represents a CPU in + one of the two clusters present on the platform. */ + if (cpu_id >= get_arm_cluster_core_count(mpidr)) + return -1; + + return 0; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/tsp/arm_tsp.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/tsp/arm_tsp.mk new file mode 100644 index 0000000..f285f58 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/tsp/arm_tsp.mk @@ -0,0 +1,37 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# TSP source files common to ARM standard platforms +BL32_SOURCES += drivers/arm/gic/arm_gic.c \ + drivers/arm/gic/gic_v2.c \ + plat/arm/common/arm_topology.c \ + plat/arm/common/tsp/arm_tsp_setup.c \ + plat/common/aarch64/platform_mp_stack.S \ + plat/common/plat_gic.c diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/tsp/arm_tsp_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/tsp/arm_tsp_setup.c new file mode 100644 index 0000000..78db160 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/common/tsp/arm_tsp_setup.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + + +/* + * The next 3 constants identify the extents of the code & RO data region and + * the limit of the BL3-2 image. These addresses are used by the MMU setup code + * and therefore they must be page-aligned. It is the responsibility of the + * linker script to ensure that __RO_START__, __RO_END__ & & __BL32_END__ + * linker symbols refer to page-aligned addresses. + */ +#define BL32_RO_BASE (unsigned long)(&__RO_START__) +#define BL32_RO_LIMIT (unsigned long)(&__RO_END__) +#define BL32_END (unsigned long)(&__BL32_END__) + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ +#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif + + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak tsp_early_platform_setup +#pragma weak tsp_platform_setup +#pragma weak tsp_plat_arch_setup + + +/******************************************************************************* + * Initialize the UART + ******************************************************************************/ +void arm_tsp_early_platform_setup(void) +{ + /* + * Initialize a different console than already in use to display + * messages from TSP + */ + console_init(PLAT_ARM_TSP_UART_BASE, PLAT_ARM_TSP_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE); +} + +void tsp_early_platform_setup(void) +{ + arm_tsp_early_platform_setup(); +} + +/******************************************************************************* + * Perform platform specific setup placeholder + ******************************************************************************/ +void tsp_platform_setup(void) +{ + plat_arm_gic_init(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the MMU + ******************************************************************************/ +void tsp_plat_arch_setup(void) +{ + arm_configure_mmu_el1(BL32_RO_BASE, + (BL32_END - BL32_RO_BASE), + BL32_RO_BASE, + BL32_RO_LIMIT +#if USE_COHERENT_MEM + , BL32_COHERENT_RAM_BASE, + BL32_COHERENT_RAM_LIMIT +#endif + ); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/aarch64/css_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/aarch64/css_helpers.S new file mode 100644 index 0000000..05bd864 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/aarch64/css_helpers.S @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include + + .weak plat_secondary_cold_boot_setup + .weak plat_get_my_entrypoint + .globl plat_arm_calc_core_pos + .weak plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* todo: Implement secondary CPU cold boot setup on CSS platforms */ +cb_panic: + b cb_panic +endfunc plat_secondary_cold_boot_setup + + /* --------------------------------------------------------------------- + * unsigned long plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and a warm + * boot. On CSS platforms, this distinction is based on the contents of + * the Trusted Mailbox. It is initialised to zero by the SCP before the + * AP cores are released from reset. Therefore, a zero mailbox means + * it's a cold reset. + * + * This functions returns the contents of the mailbox, i.e.: + * - 0 for a cold boot; + * - the warm boot entrypoint for a warm boot. + * --------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + mov_imm x0, TRUSTED_MAILBOX_BASE + ldr x0, [x0] + ret +endfunc plat_get_my_entrypoint + + /* ----------------------------------------------------------- + * unsigned int plat_arm_calc_core_pos(uint64_t mpidr) + * Function to calculate the core position by + * swapping the cluster order. This is necessary in order to + * match the format of the boot information passed by the SCP + * and read in plat_is_my_cpu_primary below. + * ----------------------------------------------------------- + */ +func plat_arm_calc_core_pos + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order + add x0, x1, x0, LSR #6 + ret +endfunc plat_arm_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu (applicable ony after a cold boot) + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mov x9, x30 + bl plat_my_core_pos + ldr x1, =SCP_BOOT_CFG_ADDR + ldr x1, [x1] + ubfx x1, x1, #PRIMARY_CPU_SHIFT, #PRIMARY_CPU_BIT_WIDTH + cmp x0, x1 + cset w0, eq + ret x9 +endfunc plat_is_my_cpu_primary diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_bl2_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_bl2_setup.c new file mode 100644 index 0000000..2e423d9 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_bl2_setup.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "css_scp_bootloader.h" + +/* Weak definition may be overridden in specific CSS based platform */ +#pragma weak bl2_plat_handle_bl30 + +/******************************************************************************* + * Transfer BL3-0 from Trusted RAM using the SCP Download protocol. + * Return 0 on success, -1 otherwise. + ******************************************************************************/ +int bl2_plat_handle_bl30(image_info_t *bl30_image_info) +{ + int ret; + + INFO("BL2: Initiating BL3-0 transfer to SCP\n"); + + ret = scp_bootloader_transfer((void *)bl30_image_info->image_base, + bl30_image_info->image_size); + + if (ret == 0) + INFO("BL2: BL3-0 transferred to SCP\n"); + else + ERROR("BL2: BL3-0 transfer failure\n"); + + return ret; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_common.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_common.c new file mode 100644 index 0000000..91813f2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_common.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + +#if IMAGE_BL31 || IMAGE_BL32 + +const unsigned int irq_sec_array[] = { + PLAT_CSS_IRQ_SEC_LIST, + ARM_IRQ_SEC_PHY_TIMER, + ARM_IRQ_SEC_SGI_0, + ARM_IRQ_SEC_SGI_1, + ARM_IRQ_SEC_SGI_2, + ARM_IRQ_SEC_SGI_3, + ARM_IRQ_SEC_SGI_4, + ARM_IRQ_SEC_SGI_5, + ARM_IRQ_SEC_SGI_6, + ARM_IRQ_SEC_SGI_7 +}; + + +/* Weak definitions may be overridden in specific CSS based platform */ +#pragma weak plat_arm_gic_init + +void plat_arm_gic_init(void) +{ + arm_gic_init(PLAT_CSS_GICC_BASE, + PLAT_CSS_GICD_BASE, + PLAT_CSS_GICR_BASE, + irq_sec_array, + ARRAY_SIZE(irq_sec_array)); +} + +#endif /* IMAGE_BL31 || IMAGE_BL32 */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_common.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_common.mk new file mode 100644 index 0000000..d5c2fcb --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_common.mk @@ -0,0 +1,64 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +PLAT_INCLUDES += -Iinclude/plat/arm/css/common \ + -Iinclude/plat/arm/css/common/aarch64 + + +PLAT_BL_COMMON_SOURCES += plat/arm/css/common/aarch64/css_helpers.S \ + plat/arm/css/common/css_common.c + +#BL1_SOURCES += + +BL2_SOURCES += plat/arm/css/common/css_bl2_setup.c \ + plat/arm/css/common/css_mhu.c \ + plat/arm/css/common/css_scp_bootloader.c \ + plat/arm/css/common/css_scpi.c + +BL31_SOURCES += plat/arm/css/common/css_mhu.c \ + plat/arm/css/common/css_pm.c \ + plat/arm/css/common/css_scpi.c \ + plat/arm/css/common/css_topology.c + + +ifneq (${RESET_TO_BL31},0) + $(error "Using BL3-1 as the reset vector is not supported on CSS platforms. \ + Please set RESET_TO_BL31 to 0.") +endif + +NEED_BL30 := yes + +# Enable option to detect whether the SCP ROM firmware in use predates version +# 1.7.0 and therefore, is incompatible. +CSS_DETECT_PRE_1_7_0_SCP := 1 + +# Process CSS_DETECT_PRE_1_7_0_SCP flag +$(eval $(call assert_boolean,CSS_DETECT_PRE_1_7_0_SCP)) +$(eval $(call add_define,CSS_DETECT_PRE_1_7_0_SCP)) diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_mhu.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_mhu.c new file mode 100644 index 0000000..b1714e2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_mhu.c @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "css_mhu.h" + +/* SCP MHU secure channel registers */ +#define SCP_INTR_S_STAT 0x200 +#define SCP_INTR_S_SET 0x208 +#define SCP_INTR_S_CLEAR 0x210 + +/* CPU MHU secure channel registers */ +#define CPU_INTR_S_STAT 0x300 +#define CPU_INTR_S_SET 0x308 +#define CPU_INTR_S_CLEAR 0x310 + +ARM_INSTANTIATE_LOCK + +/* Weak definition may be overridden in specific CSS based platform */ +#pragma weak plat_arm_pwrc_setup + + +/* + * Slot 31 is reserved because the MHU hardware uses this register bit to + * indicate a non-secure access attempt. The total number of available slots is + * therefore 31 [30:0]. + */ +#define MHU_MAX_SLOT_ID 30 + +void mhu_secure_message_start(unsigned int slot_id) +{ + assert(slot_id <= MHU_MAX_SLOT_ID); + + arm_lock_get(); + + /* Make sure any previous command has finished */ + while (mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) & (1 << slot_id)) + ; +} + +void mhu_secure_message_send(unsigned int slot_id) +{ + assert(slot_id <= MHU_MAX_SLOT_ID); + assert(!(mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) & (1 << slot_id))); + + /* Send command to SCP */ + mmio_write_32(MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); +} + +uint32_t mhu_secure_message_wait(void) +{ + /* Wait for response from SCP */ + uint32_t response; + while (!(response = mmio_read_32(MHU_BASE + SCP_INTR_S_STAT))) + ; + + return response; +} + +void mhu_secure_message_end(unsigned int slot_id) +{ + assert(slot_id <= MHU_MAX_SLOT_ID); + + /* + * Clear any response we got by writing one in the relevant slot bit to + * the CLEAR register + */ + mmio_write_32(MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id); + + arm_lock_release(); +} + +void mhu_secure_init(void) +{ + arm_lock_init(); + + /* + * The STAT register resets to zero. Ensure it is in the expected state, + * as a stale or garbage value would make us think it's a message we've + * already sent. + */ + assert(mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) == 0); +} + +void plat_arm_pwrc_setup(void) +{ + mhu_secure_init(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_mhu.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_mhu.h new file mode 100644 index 0000000..2175cdf --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_mhu.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CSS_MHU_H__ +#define __CSS_MHU_H__ + +#include + +void mhu_secure_message_start(unsigned int slot_id); +void mhu_secure_message_send(unsigned int slot_id); +uint32_t mhu_secure_message_wait(void); +void mhu_secure_message_end(unsigned int slot_id); + +void mhu_secure_init(void); + +#endif /* __CSS_MHU_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_pm.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_pm.c new file mode 100644 index 0000000..cc64bf8 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_pm.c @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "css_scpi.h" + + +#if ARM_RECOM_STATE_ID_ENC +/* + * The table storing the valid idle power states. Ensure that the + * array entries are populated in ascending order of state-id to + * enable us to use binary search during power state validation. + * The table must be terminated by a NULL entry. + */ +const unsigned int arm_pm_idle_states[] = { + /* State-id - 0x01 */ + arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, + ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), + /* State-id - 0x02 */ + arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, + ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), + /* State-id - 0x22 */ + arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, + ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), + 0, +}; +#endif + +/******************************************************************************* + * Private function to program the mailbox for a cpu before it is released + * from reset. + ******************************************************************************/ +static void css_program_mailbox(uintptr_t address) +{ + uintptr_t *mailbox = (void *) TRUSTED_MAILBOX_BASE; + *mailbox = address; + flush_dcache_range((uintptr_t) mailbox, sizeof(*mailbox)); +} + +/******************************************************************************* + * Handler called when a power domain is about to be turned on. The + * level and mpidr determine the affinity instance. + ******************************************************************************/ +int css_pwr_domain_on(u_register_t mpidr) +{ + /* + * SCP takes care of powering up parent power domains so we + * only need to care about level 0 + */ + scpi_set_css_power_state(mpidr, scpi_power_on, scpi_power_on, + scpi_power_on); + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * Handler called when a power level has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. + ******************************************************************************/ +void css_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_OFF); + + /* + * Perform the common cluster specific operations i.e enable coherency + * if this cluster was off. + */ + if (target_state->pwr_domain_state[ARM_PWR_LVL1] == + ARM_LOCAL_STATE_OFF) + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); + + /* Enable the gic cpu interface */ + arm_gic_cpuif_setup(); + + /* todo: Is this setup only needed after a cold boot? */ + arm_gic_pcpu_distif_setup(); +} + +/******************************************************************************* + * Common function called while turning a cpu off or suspending it. It is called + * from css_off() or css_suspend() when these functions in turn are called for + * power domain at the highest power level which will be powered down. It + * performs the actions common to the OFF and SUSPEND calls. + ******************************************************************************/ +static void css_power_down_common(const psci_power_state_t *target_state) +{ + uint32_t cluster_state = scpi_power_on; + + /* Prevent interrupts from spuriously waking up this cpu */ + arm_gic_cpuif_deactivate(); + + /* Cluster is to be turned off, so disable coherency */ + if (target_state->pwr_domain_state[ARM_PWR_LVL1] == + ARM_LOCAL_STATE_OFF) { + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); + cluster_state = scpi_power_off; + } + + /* + * Ask the SCP to power down the appropriate components depending upon + * their state. + */ + scpi_set_css_power_state(read_mpidr_el1(), + scpi_power_off, + cluster_state, + scpi_power_on); +} + +/******************************************************************************* + * Handler called when a power domain is about to be turned off. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +static void css_pwr_domain_off(const psci_power_state_t *target_state) +{ + assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_OFF); + + css_power_down_common(target_state); +} + +/******************************************************************************* + * Handler called when a power domain is about to be suspended. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +static void css_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + /* + * Juno has retention only at cpu level. Just return + * as nothing is to be done for retention. + */ + if (target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_RET) + return; + + assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_OFF); + + css_power_down_common(target_state); +} + +/******************************************************************************* + * Handler called when a power domain has just been powered on after + * having been suspended earlier. The target_state encodes the low power state + * that each level has woken up from. + * TODO: At the moment we reuse the on finisher and reinitialize the secure + * context. Need to implement a separate suspend finisher. + ******************************************************************************/ +static void css_pwr_domain_suspend_finish( + const psci_power_state_t *target_state) +{ + /* + * Return as nothing is to be done on waking up from retention. + */ + if (target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_RET) + return; + + css_pwr_domain_on_finish(target_state); +} + +/******************************************************************************* + * Handlers to shutdown/reboot the system + ******************************************************************************/ +static void __dead2 css_system_off(void) +{ + uint32_t response; + + /* Send the power down request to the SCP */ + response = scpi_sys_power_state(scpi_system_shutdown); + + if (response != SCP_OK) { + ERROR("CSS System Off: SCP error %u.\n", response); + panic(); + } + wfi(); + ERROR("CSS System Off: operation not handled.\n"); + panic(); +} + +static void __dead2 css_system_reset(void) +{ + uint32_t response; + + /* Send the system reset request to the SCP */ + response = scpi_sys_power_state(scpi_system_reboot); + + if (response != SCP_OK) { + ERROR("CSS System Reset: SCP error %u.\n", response); + panic(); + } + wfi(); + ERROR("CSS System Reset: operation not handled.\n"); + panic(); +} + +/******************************************************************************* + * Handler called when the CPU power domain is about to enter standby. + ******************************************************************************/ +void css_cpu_standby(plat_local_state_t cpu_state) +{ + unsigned int scr; + + assert(cpu_state == ARM_LOCAL_STATE_RET); + + scr = read_scr_el3(); + /* Enable PhysicalIRQ bit for NS world to wake the CPU */ + write_scr_el3(scr | SCR_IRQ_BIT); + isb(); + dsb(); + wfi(); + + /* + * Restore SCR to the original value, synchronisation of scr_el3 is + * done by eret while el3_exit to save some execution cycles. + */ + write_scr_el3(scr); +} + +/******************************************************************************* + * Export the platform handlers to enable psci to invoke them + ******************************************************************************/ +static const plat_psci_ops_t css_ops = { + .pwr_domain_on = css_pwr_domain_on, + .pwr_domain_on_finish = css_pwr_domain_on_finish, + .pwr_domain_off = css_pwr_domain_off, + .cpu_standby = css_cpu_standby, + .pwr_domain_suspend = css_pwr_domain_suspend, + .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish, + .system_off = css_system_off, + .system_reset = css_system_reset, + .validate_power_state = arm_validate_power_state, + .validate_ns_entrypoint = arm_validate_ns_entrypoint +}; + +/******************************************************************************* + * Export the platform specific psci ops. + ******************************************************************************/ +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + *psci_ops = &css_ops; + + /* Setup mailbox with entry point. */ + css_program_mailbox(sec_entrypoint); + return 0; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_scp_bootloader.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_scp_bootloader.c new file mode 100644 index 0000000..acc7351 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_scp_bootloader.c @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "css_mhu.h" +#include "css_scp_bootloader.h" +#include "css_scpi.h" + +/* ID of the MHU slot used for the BOM protocol */ +#define BOM_MHU_SLOT_ID 0 + +/* Boot commands sent from AP -> SCP */ +#define BOOT_CMD_INFO 0x00 +#define BOOT_CMD_DATA 0x01 + +/* BOM command header */ +typedef struct { + uint32_t id : 8; + uint32_t reserved : 24; +} bom_cmd_t; + +typedef struct { + uint32_t image_size; + uint32_t checksum; +} cmd_info_payload_t; + +/* + * Unlike the SCPI protocol, the boot protocol uses the same memory region + * for both AP -> SCP and SCP -> AP transfers; define the address of this... + */ +#define BOM_SHARED_MEM SCP_COM_SHARED_MEM_BASE +#define BOM_CMD_HEADER ((bom_cmd_t *) BOM_SHARED_MEM) +#define BOM_CMD_PAYLOAD ((void *) (BOM_SHARED_MEM + sizeof(bom_cmd_t))) + +typedef struct { + /* Offset from the base address of the Trusted RAM */ + uint32_t offset; + uint32_t block_size; +} cmd_data_payload_t; + +static void scp_boot_message_start(void) +{ + mhu_secure_message_start(BOM_MHU_SLOT_ID); +} + +static void scp_boot_message_send(size_t payload_size) +{ + /* Make sure payload can be seen by SCP */ + if (MHU_PAYLOAD_CACHED) + flush_dcache_range(BOM_SHARED_MEM, + sizeof(bom_cmd_t) + payload_size); + + /* Send command to SCP */ + mhu_secure_message_send(BOM_MHU_SLOT_ID); +} + +static uint32_t scp_boot_message_wait(size_t size) +{ + uint32_t mhu_status; + + mhu_status = mhu_secure_message_wait(); + + /* Expect an SCP Boot Protocol message, reject any other protocol */ + if (mhu_status != (1 << BOM_MHU_SLOT_ID)) { + ERROR("MHU: Unexpected protocol (MHU status: 0x%x)\n", + mhu_status); + panic(); + } + + /* Make sure we see the reply from the SCP and not any stale data */ + if (MHU_PAYLOAD_CACHED) + inv_dcache_range(BOM_SHARED_MEM, size); + + return *(uint32_t *) BOM_SHARED_MEM; +} + +static void scp_boot_message_end(void) +{ + mhu_secure_message_end(BOM_MHU_SLOT_ID); +} + +int scp_bootloader_transfer(void *image, unsigned int image_size) +{ + uint32_t response; + uint32_t checksum; + cmd_info_payload_t *cmd_info_payload; + cmd_data_payload_t *cmd_data_payload; + + assert((uintptr_t) image == BL30_BASE); + + if ((image_size == 0) || (image_size % 4 != 0)) { + ERROR("Invalid size for the BL3-0 image. Must be a multiple of " + "4 bytes and not zero (current size = 0x%x)\n", + image_size); + return -1; + } + + /* Extract the checksum from the image */ + checksum = *(uint32_t *) image; + image = (char *) image + sizeof(checksum); + image_size -= sizeof(checksum); + + mhu_secure_init(); + + VERBOSE("Send info about the BL3-0 image to be transferred to SCP\n"); + + /* + * Send information about the SCP firmware image about to be transferred + * to SCP + */ + scp_boot_message_start(); + + BOM_CMD_HEADER->id = BOOT_CMD_INFO; + cmd_info_payload = BOM_CMD_PAYLOAD; + cmd_info_payload->image_size = image_size; + cmd_info_payload->checksum = checksum; + + scp_boot_message_send(sizeof(*cmd_info_payload)); +#if CSS_DETECT_PRE_1_7_0_SCP + { + const uint32_t deprecated_scp_nack_cmd = 0x404; + uint32_t mhu_status; + + VERBOSE("Detecting SCP version incompatibility\n"); + + mhu_status = mhu_secure_message_wait(); + if (mhu_status == deprecated_scp_nack_cmd) { + ERROR("Detected an incompatible version of the SCP firmware.\n"); + ERROR("Only versions from v1.7.0 onwards are supported.\n"); + ERROR("Please update the SCP firmware.\n"); + return -1; + } + + VERBOSE("SCP version looks OK\n"); + } +#endif /* CSS_DETECT_PRE_1_7_0_SCP */ + response = scp_boot_message_wait(sizeof(response)); + scp_boot_message_end(); + + if (response != 0) { + ERROR("SCP BOOT_CMD_INFO returned error %u\n", response); + return -1; + } + + VERBOSE("Transferring BL3-0 image to SCP\n"); + + /* Transfer BL3-0 image to SCP */ + scp_boot_message_start(); + + BOM_CMD_HEADER->id = BOOT_CMD_DATA; + cmd_data_payload = BOM_CMD_PAYLOAD; + cmd_data_payload->offset = (uintptr_t) image - ARM_TRUSTED_SRAM_BASE; + cmd_data_payload->block_size = image_size; + + scp_boot_message_send(sizeof(*cmd_data_payload)); + response = scp_boot_message_wait(sizeof(response)); + scp_boot_message_end(); + + if (response != 0) { + ERROR("SCP BOOT_CMD_DATA returned error %u\n", response); + return -1; + } + + VERBOSE("Waiting for SCP to signal it is ready to go on\n"); + + /* Wait for SCP to signal it's ready */ + return scpi_wait_ready(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_scp_bootloader.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_scp_bootloader.h new file mode 100644 index 0000000..07b8972 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_scp_bootloader.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CSS_SCP_BOOTLOADER_H__ +#define __CSS_SCP_BOOTLOADER_H__ + +int scp_bootloader_transfer(void *image, unsigned int image_size); + +#endif /* __CSS_SCP_BOOTLOADER_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_scpi.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_scpi.c new file mode 100644 index 0000000..0a4eafe --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_scpi.c @@ -0,0 +1,188 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "css_mhu.h" +#include "css_scpi.h" + +#define SCPI_SHARED_MEM_SCP_TO_AP SCP_COM_SHARED_MEM_BASE +#define SCPI_SHARED_MEM_AP_TO_SCP (SCP_COM_SHARED_MEM_BASE + 0x100) + +#define SCPI_CMD_HEADER_AP_TO_SCP \ + ((scpi_cmd_t *) SCPI_SHARED_MEM_AP_TO_SCP) +#define SCPI_CMD_PAYLOAD_AP_TO_SCP \ + ((void *) (SCPI_SHARED_MEM_AP_TO_SCP + sizeof(scpi_cmd_t))) + +/* ID of the MHU slot used for the SCPI protocol */ +#define SCPI_MHU_SLOT_ID 0 + +static void scpi_secure_message_start(void) +{ + mhu_secure_message_start(SCPI_MHU_SLOT_ID); +} + +static void scpi_secure_message_send(size_t payload_size) +{ + /* Make sure payload can be seen by SCP */ + if (MHU_PAYLOAD_CACHED) + flush_dcache_range(SCPI_SHARED_MEM_AP_TO_SCP, + sizeof(scpi_cmd_t) + payload_size); + + mhu_secure_message_send(SCPI_MHU_SLOT_ID); +} + +static void scpi_secure_message_receive(scpi_cmd_t *cmd) +{ + uint32_t mhu_status; + + assert(cmd != NULL); + + mhu_status = mhu_secure_message_wait(); + + /* Expect an SCPI message, reject any other protocol */ + if (mhu_status != (1 << SCPI_MHU_SLOT_ID)) { + ERROR("MHU: Unexpected protocol (MHU status: 0x%x)\n", + mhu_status); + panic(); + } + + /* Make sure we don't read stale data */ + if (MHU_PAYLOAD_CACHED) + inv_dcache_range(SCPI_SHARED_MEM_SCP_TO_AP, sizeof(*cmd)); + + memcpy(cmd, (void *) SCPI_SHARED_MEM_SCP_TO_AP, sizeof(*cmd)); +} + +static void scpi_secure_message_end(void) +{ + mhu_secure_message_end(SCPI_MHU_SLOT_ID); +} + +int scpi_wait_ready(void) +{ + scpi_cmd_t scpi_cmd; + + VERBOSE("Waiting for SCP_READY command...\n"); + + /* Get a message from the SCP */ + scpi_secure_message_start(); + scpi_secure_message_receive(&scpi_cmd); + scpi_secure_message_end(); + + /* We are expecting 'SCP Ready', produce correct error if it's not */ + scpi_status_t status = SCP_OK; + if (scpi_cmd.id != SCPI_CMD_SCP_READY) { + ERROR("Unexpected SCP command: expected command #%u, got command #%u\n", + SCPI_CMD_SCP_READY, scpi_cmd.id); + status = SCP_E_SUPPORT; + } else if (scpi_cmd.size != 0) { + ERROR("SCP_READY command has incorrect size: expected 0, got %u\n", + scpi_cmd.size); + status = SCP_E_SIZE; + } + + VERBOSE("Sending response for SCP_READY command\n"); + + /* + * Send our response back to SCP. + * We are using the same SCPI header, just update the status field. + */ + scpi_cmd.status = status; + scpi_secure_message_start(); + memcpy((void *) SCPI_SHARED_MEM_AP_TO_SCP, &scpi_cmd, sizeof(scpi_cmd)); + scpi_secure_message_send(0); + scpi_secure_message_end(); + + return status == SCP_OK ? 0 : -1; +} + +void scpi_set_css_power_state(unsigned mpidr, scpi_power_state_t cpu_state, + scpi_power_state_t cluster_state, scpi_power_state_t css_state) +{ + scpi_cmd_t *cmd; + uint32_t state = 0; + uint32_t *payload_addr; + + state |= mpidr & 0x0f; /* CPU ID */ + state |= (mpidr & 0xf00) >> 4; /* Cluster ID */ + state |= cpu_state << 8; + state |= cluster_state << 12; + state |= css_state << 16; + + scpi_secure_message_start(); + + /* Populate the command header */ + cmd = SCPI_CMD_HEADER_AP_TO_SCP; + cmd->id = SCPI_CMD_SET_CSS_POWER_STATE; + cmd->set = SCPI_SET_NORMAL; + cmd->sender = 0; + cmd->size = sizeof(state); + /* Populate the command payload */ + payload_addr = SCPI_CMD_PAYLOAD_AP_TO_SCP; + *payload_addr = state; + scpi_secure_message_send(sizeof(state)); + /* + * SCP does not reply to this command in order to avoid MHU interrupts + * from the sender, which could interfere with its power state request. + */ + + scpi_secure_message_end(); +} + +uint32_t scpi_sys_power_state(scpi_system_state_t system_state) +{ + scpi_cmd_t *cmd; + uint8_t *payload_addr; + scpi_cmd_t response; + + scpi_secure_message_start(); + + /* Populate the command header */ + cmd = SCPI_CMD_HEADER_AP_TO_SCP; + cmd->id = SCPI_CMD_SYS_POWER_STATE; + cmd->set = 0; + cmd->sender = 0; + cmd->size = sizeof(*payload_addr); + /* Populate the command payload */ + payload_addr = SCPI_CMD_PAYLOAD_AP_TO_SCP; + *payload_addr = system_state & 0xff; + scpi_secure_message_send(sizeof(*payload_addr)); + + scpi_secure_message_receive(&response); + + scpi_secure_message_end(); + + return response.status; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_scpi.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_scpi.h new file mode 100644 index 0000000..379a821 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_scpi.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CSS_SCPI_H__ +#define __CSS_SCPI_H__ + +#include +#include + +/* + * An SCPI command consists of a header and a payload. + * The following structure describes the header. It is 64-bit long. + */ +typedef struct { + /* Command ID */ + uint32_t id : 7; + /* Set ID. Identifies whether this is a standard or extended command. */ + uint32_t set : 1; + /* Sender ID to match a reply. The value is sender specific. */ + uint32_t sender : 8; + /* Size of the payload in bytes (0 – 511) */ + uint32_t size : 9; + uint32_t reserved : 7; + /* + * Status indicating the success of a command. + * See the enum below. + */ + uint32_t status; +} scpi_cmd_t; + +typedef enum { + SCPI_SET_NORMAL = 0, /* Normal SCPI commands */ + SCPI_SET_EXTENDED /* Extended SCPI commands */ +} scpi_set_t; + +enum { + SCP_OK = 0, /* Success */ + SCP_E_PARAM, /* Invalid parameter(s) */ + SCP_E_ALIGN, /* Invalid alignment */ + SCP_E_SIZE, /* Invalid size */ + SCP_E_HANDLER, /* Invalid handler or callback */ + SCP_E_ACCESS, /* Invalid access or permission denied */ + SCP_E_RANGE, /* Value out of range */ + SCP_E_TIMEOUT, /* Time out has ocurred */ + SCP_E_NOMEM, /* Invalid memory area or pointer */ + SCP_E_PWRSTATE, /* Invalid power state */ + SCP_E_SUPPORT, /* Feature not supported or disabled */ + SCPI_E_DEVICE, /* Device error */ + SCPI_E_BUSY, /* Device is busy */ +}; + +typedef uint32_t scpi_status_t; + +typedef enum { + SCPI_CMD_SCP_READY = 0x01, + SCPI_CMD_SET_CSS_POWER_STATE = 0x03, + SCPI_CMD_SYS_POWER_STATE = 0x05 +} scpi_command_t; + +typedef enum { + scpi_power_on = 0, + scpi_power_retention = 1, + scpi_power_off = 3, +} scpi_power_state_t; + +typedef enum { + scpi_system_shutdown = 0, + scpi_system_reboot = 1, + scpi_system_reset = 2 +} scpi_system_state_t; + +extern int scpi_wait_ready(void); +extern void scpi_set_css_power_state(unsigned mpidr, + scpi_power_state_t cpu_state, + scpi_power_state_t cluster_state, + scpi_power_state_t css_state); +uint32_t scpi_sys_power_state(scpi_system_state_t system_state); + + +#endif /* __CSS_SCPI_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_topology.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_topology.c new file mode 100644 index 0000000..381e786 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/css/common/css_topology.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* + * On ARM platforms, by default the cluster power level is treated as the + * highest. The first entry in the power domain descriptor specifies the + * number of cluster power domains i.e. 2. + */ +#define CSS_PWR_DOMAINS_AT_MAX_PWR_LVL ARM_CLUSTER_COUNT + +/* + * The CSS power domain tree descriptor. The cluster power domains are + * arranged so that when the PSCI generic code creates the power domain tree, + * the indices of the CPU power domain nodes it allocates match the linear + * indices returned by plat_core_pos_by_mpidr() i.e. + * CLUSTER1 CPUs are allocated indices from 0 to 3 and the higher indices for + * CLUSTER0 CPUs. + */ +const unsigned char arm_power_domain_tree_desc[] = { + /* No of root nodes */ + CSS_PWR_DOMAINS_AT_MAX_PWR_LVL, + /* No of children for the first node */ + PLAT_ARM_CLUSTER1_CORE_COUNT, + /* No of children for the second node */ + PLAT_ARM_CLUSTER0_CORE_COUNT +}; + + +/****************************************************************************** + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is + * returned in case the MPIDR is invalid. + *****************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + if (arm_check_mpidr(mpidr) == 0) + return plat_arm_calc_core_pos(mpidr); + + return -1; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/soc/common/soc_css.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/soc/common/soc_css.mk new file mode 100644 index 0000000..fd51b7f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/soc/common/soc_css.mk @@ -0,0 +1,40 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +PLAT_INCLUDES += -Iinclude/plat/arm/soc/common/ + +#PLAT_BL_COMMON_SOURCES += + + +#BL1_SOURCES += + +BL2_SOURCES += plat/arm/soc/common/soc_css_security.c + +#BL31_SOURCES += diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/soc/common/soc_css_security.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/soc/common/soc_css_security.c new file mode 100644 index 0000000..37fd37c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/arm/soc/common/soc_css_security.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +void soc_css_init_nic400(void) +{ + /* + * NIC-400 Access Control Initialization + * + * Define access privileges by setting each corresponding bit to: + * 0 = Secure access only + * 1 = Non-secure access allowed + */ + + /* + * Allow non-secure access to some SOC regions, excluding UART1, which + * remains secure. + * Note: This is the NIC-400 device on the SOC + */ + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_EHCI), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_TLX_MASTER), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_OHCI), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), + ~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1); + +} + + +#define PCIE_SECURE_REG 0x3000 +/* Mask uses REG and MEM access bits */ +#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) + +void soc_css_init_pcie(void) +{ +#if !PLAT_juno + /* + * Do not initialize PCIe in emulator environment. + * Platform ID register not supported on Juno + */ + if (BOARD_CSS_GET_PLAT_TYPE(BOARD_CSS_PLAT_ID_REG_ADDR) == + BOARD_CSS_PLAT_TYPE_EMULATOR) + return; +#endif /* PLAT_juno */ + + /* + * PCIE Root Complex Security settings to enable non-secure + * access to config registers. + */ + mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG, + PCIE_SEC_ACCESS_MASK); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/plat_common.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/plat_common.c new file mode 100644 index 0000000..a6a8476 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/plat_common.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +/* + * The following 2 platform setup functions are weakly defined. They + * provide typical implementations that may be re-used by multiple + * platforms but may also be overridden by a platform if required. + */ +#pragma weak bl31_plat_enable_mmu +#pragma weak bl32_plat_enable_mmu + +void bl31_plat_enable_mmu(uint32_t flags) +{ + enable_mmu_el3(flags); +} + +void bl32_plat_enable_mmu(uint32_t flags) +{ + enable_mmu_el1(flags); +} + +#if !ENABLE_PLAT_COMPAT +/* + * Helper function for platform_get_pos() when platform compatibility is + * disabled. This is to enable SPDs using the older platform API to continue + * to work. + */ +unsigned int platform_core_pos_helper(unsigned long mpidr) +{ + int idx = plat_core_pos_by_mpidr(mpidr); + assert(idx >= 0); + return idx; +} +#endif + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/plat_psci_common.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/plat_psci_common.c new file mode 100644 index 0000000..0748ef4 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/plat_psci_common.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +/* + * The PSCI generic code uses this API to let the platform participate in state + * coordination during a power management operation. It compares the platform + * specific local power states requested by each cpu for a given power domain + * and returns the coordinated target power state that the domain should + * enter. A platform assigns a number to a local power state. This default + * implementation assumes that the platform assigns these numbers in order of + * increasing depth of the power state i.e. for two power states X & Y, if X < Y + * then X represents a shallower power state than Y. As a result, the + * coordinated target local power state for a power domain will be the minimum + * of the requested local power states. + */ +plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, + const plat_local_state_t *states, + unsigned int ncpu) +{ + plat_local_state_t target = PLAT_MAX_OFF_STATE, temp; + + assert(ncpu); + + do { + temp = *states++; + if (temp < target) + target = temp; + } while (--ncpu); + + return target; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/platform_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/platform_helpers.S new file mode 100644 index 0000000..9f4b672 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/platform_helpers.S @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .weak plat_report_exception + .weak plat_crash_console_init + .weak plat_crash_console_putc + .weak plat_reset_handler + .weak plat_disable_acp + +#if !ENABLE_PLAT_COMPAT + .globl platform_get_core_pos + +#define MPIDR_RES_BIT_MASK 0xff000000 + + /* ------------------------------------------------------------------ + * int platform_get_core_pos(int mpidr) + * Returns the CPU index of the CPU specified by mpidr. This is + * defined when platform compatibility is disabled to enable Trusted + * Firmware components like SPD using the old platform API to work. + * This API is deprecated and it assumes that the mpidr specified is + * that of a valid and present CPU. Instead, plat_my_core_pos() + * should be used for CPU index of the current CPU and + * plat_core_pos_by_mpidr() should be used for CPU index of a + * CPU specified by its mpidr. + * ------------------------------------------------------------------ + */ +func_deprecated platform_get_core_pos + bic x0, x0, #MPIDR_RES_BIT_MASK + mrs x1, mpidr_el1 + bic x1, x1, #MPIDR_RES_BIT_MASK + cmp x0, x1 + beq plat_my_core_pos + b platform_core_pos_helper +endfunc_deprecated platform_get_core_pos +#endif + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ +func plat_report_exception + ret +endfunc plat_report_exception + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ +func plat_crash_console_init + mov x0, #0 + ret +endfunc plat_crash_console_init + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ +func plat_crash_console_putc + ret +endfunc plat_crash_console_putc + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. This function should preserve x10. + * ----------------------------------------------------- + */ +func plat_reset_handler + ret +endfunc plat_reset_handler + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. This function is allowed to use + * registers x0 - x17. + * ----------------------------------------------------- + */ +func plat_disable_acp + ret +endfunc plat_disable_acp diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/platform_mp_stack.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/platform_mp_stack.S new file mode 100644 index 0000000..c719019 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/platform_mp_stack.S @@ -0,0 +1,196 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + .local platform_normal_stacks +#if ENABLE_PLAT_COMPAT + .globl plat_get_my_stack + .globl plat_set_my_stack + .weak platform_get_stack + .weak platform_set_stack +#else + .weak plat_get_my_stack + .weak plat_set_my_stack + .globl platform_get_stack + .globl platform_set_stack +#endif /* __ENABLE_PLAT_COMPAT__ */ + +#if ENABLE_PLAT_COMPAT + /* --------------------------------------------------------------------- + * When the compatility layer is enabled, the new platform APIs + * viz plat_get_my_stack() and plat_set_my_stack() need to be + * defined using the previous APIs platform_get_stack() and + * platform_set_stack(). Also we need to provide weak definitions + * of platform_get_stack() and platform_set_stack() for the platforms + * to reuse. + * -------------------------------------------------------------------- + */ + + /* ----------------------------------------------------- + * unsigned long plat_get_my_stack () + * + * For the current CPU, this function returns the stack + * pointer for a stack allocated in device memory. + * ----------------------------------------------------- + */ +func plat_get_my_stack + mrs x0, mpidr_el1 + b platform_get_stack +endfunc plat_get_my_stack + + /* ----------------------------------------------------- + * void plat_set_my_stack () + * + * For the current CPU, this function sets the stack + * pointer to a stack allocated in normal memory. + * ----------------------------------------------------- + */ +func plat_set_my_stack + mrs x0, mpidr_el1 + b platform_set_stack +endfunc plat_set_my_stack + + /* ----------------------------------------------------- + * unsigned long platform_get_stack (unsigned long mpidr) + * + * For a given CPU, this function returns the stack + * pointer for a stack allocated in device memory. + * ----------------------------------------------------- + */ +func platform_get_stack + mov x10, x30 // lr + get_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE + ret x10 +endfunc platform_get_stack + + /* ----------------------------------------------------- + * void platform_set_stack (unsigned long mpidr) + * + * For a given CPU, this function sets the stack pointer + * to a stack allocated in normal memory. + * ----------------------------------------------------- + */ +func platform_set_stack + mov x9, x30 // lr + bl platform_get_stack + mov sp, x0 + ret x9 +endfunc platform_set_stack + +#else + /* --------------------------------------------------------------------- + * When the compatility layer is disabled, the new platform APIs + * viz plat_get_my_stack() and plat_set_my_stack() are + * supported by the platform and the previous APIs platform_get_stack() + * and platform_set_stack() are defined in terms of new APIs making use + * of the fact that they are only ever invoked for the current CPU. + * This is to enable components of Trusted Firmware like SPDs using the + * old platform APIs to continue to work. + * -------------------------------------------------------------------- + */ + + /* ------------------------------------------------------- + * unsigned long platform_get_stack (unsigned long mpidr) + * + * For the current CPU, this function returns the stack + * pointer for a stack allocated in device memory. The + * 'mpidr' should correspond to that of the current CPU. + * This function is deprecated and plat_get_my_stack() + * should be used instead. + * ------------------------------------------------------- + */ +func_deprecated platform_get_stack +#if ASM_ASSERTION + mrs x1, mpidr_el1 + cmp x0, x1 + ASM_ASSERT(eq) +#endif + b plat_get_my_stack +endfunc_deprecated platform_get_stack + + /* ----------------------------------------------------- + * void platform_set_stack (unsigned long mpidr) + * + * For the current CPU, this function sets the stack pointer + * to a stack allocated in normal memory. The + * 'mpidr' should correspond to that of the current CPU. + * This function is deprecated and plat_get_my_stack() + * should be used instead. + * ----------------------------------------------------- + */ +func_deprecated platform_set_stack +#if ASM_ASSERTION + mrs x1, mpidr_el1 + cmp x0, x1 + ASM_ASSERT(eq) +#endif + b plat_set_my_stack +endfunc_deprecated platform_set_stack + + /* ----------------------------------------------------- + * unsigned long plat_get_my_stack () + * + * For the current CPU, this function returns the stack + * pointer for a stack allocated in device memory. + * ----------------------------------------------------- + */ +func plat_get_my_stack + mov x10, x30 // lr + get_my_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE + ret x10 +endfunc plat_get_my_stack + + /* ----------------------------------------------------- + * void plat_set_my_stack () + * + * For the current CPU, this function sets the stack + * pointer to a stack allocated in normal memory. + * ----------------------------------------------------- + */ +func plat_set_my_stack + mov x9, x30 // lr + bl plat_get_my_stack + mov sp, x0 + ret x9 +endfunc plat_set_my_stack + +#endif /*__ENABLE_PLAT_COMPAT__*/ + + /* ----------------------------------------------------- + * Per-cpu stacks in normal memory. Each cpu gets a + * stack of PLATFORM_STACK_SIZE bytes. + * ----------------------------------------------------- + */ +declare_stack platform_normal_stacks, tzfw_normal_stacks, \ + PLATFORM_STACK_SIZE, PLATFORM_CORE_COUNT diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/platform_up_stack.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/platform_up_stack.S new file mode 100644 index 0000000..c01534a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/common/aarch64/platform_up_stack.S @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + + .local platform_normal_stacks + .globl plat_set_my_stack + .globl plat_get_my_stack + .globl platform_set_stack + .globl platform_get_stack + + /* ----------------------------------------------------- + * unsigned long plat_get_my_stack () + * + * For cold-boot BL images, only the primary CPU needs a + * stack. This function returns the stack pointer for a + * stack allocated in device memory. + * ----------------------------------------------------- + */ +func plat_get_my_stack + get_up_stack platform_normal_stacks, PLATFORM_STACK_SIZE + ret +endfunc plat_get_my_stack + + /* ----------------------------------------------------- + * void plat_set_my_stack () + * + * For cold-boot BL images, only the primary CPU needs a + * stack. This function sets the stack pointer to a stack + * allocated in normal memory. + * ----------------------------------------------------- + */ +func plat_set_my_stack + get_up_stack platform_normal_stacks, PLATFORM_STACK_SIZE + mov sp, x0 + ret +endfunc plat_set_my_stack + + /* ----------------------------------------------------- + * unsigned long platform_get_stack () + * + * For cold-boot BL images, only the primary CPU needs a + * stack. This function returns the stack pointer for a + * stack allocated in device memory. This function + * is deprecated. + * ----------------------------------------------------- + */ +func_deprecated platform_get_stack + b plat_get_my_stack +endfunc_deprecated platform_get_stack + + /* ----------------------------------------------------- + * void platform_set_stack () + * + * For cold-boot BL images, only the primary CPU needs a + * stack. This function sets the stack pointer to a stack + * allocated in normal memory.This function is + * deprecated. + * ----------------------------------------------------- + */ +func_deprecated platform_set_stack + b plat_set_my_stack +endfunc_deprecated platform_set_stack + + /* ----------------------------------------------------- + * Single cpu stack in normal memory. + * Used for C code during boot, PLATFORM_STACK_SIZE bytes + * are allocated + * ----------------------------------------------------- + */ +declare_stack platform_normal_stacks, tzfw_normal_stacks, \ + PLATFORM_STACK_SIZE, 1 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/common/plat_gic.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/common/plat_gic.c new file mode 100644 index 0000000..f736e55 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/common/plat_gic.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include + +/* + * The following platform GIC functions are weakly defined. They + * provide typical implementations that may be re-used by multiple + * platforms but may also be overridden by a platform if required. + */ +#pragma weak plat_ic_get_pending_interrupt_id +#pragma weak plat_ic_get_pending_interrupt_type +#pragma weak plat_ic_acknowledge_interrupt +#pragma weak plat_ic_get_interrupt_type +#pragma weak plat_ic_end_of_interrupt +#pragma weak plat_interrupt_type_to_line + +uint32_t plat_ic_get_pending_interrupt_id(void) +{ + return arm_gic_get_pending_interrupt_id(); +} + +uint32_t plat_ic_get_pending_interrupt_type(void) +{ + return arm_gic_get_pending_interrupt_type(); +} + +uint32_t plat_ic_acknowledge_interrupt(void) +{ + return arm_gic_acknowledge_interrupt(); +} + +uint32_t plat_ic_get_interrupt_type(uint32_t id) +{ + return arm_gic_get_interrupt_type(id); +} + +void plat_ic_end_of_interrupt(uint32_t id) +{ + arm_gic_end_of_interrupt(id); +} + +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state) +{ + return arm_gic_interrupt_type_to_line(type, security_state); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/compat/aarch64/plat_helpers_compat.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/compat/aarch64/plat_helpers_compat.S new file mode 100644 index 0000000..6d83d23 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/compat/aarch64/plat_helpers_compat.S @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + .globl plat_my_core_pos + .globl plat_is_my_cpu_primary + .globl plat_get_my_entrypoint + .weak platform_get_core_pos + + /* ----------------------------------------------------- + * Compatibility wrappers for new platform APIs. + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b platform_get_core_pos +endfunc plat_my_core_pos + +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + b platform_is_primary_cpu +endfunc plat_is_my_cpu_primary + +func plat_get_my_entrypoint + mrs x0, mpidr_el1 + b platform_get_entrypoint +endfunc plat_get_my_entrypoint + + /* ----------------------------------------------------- + * int platform_get_core_pos(int mpidr); + * With this function: CorePos = (ClusterId * 4) + + * CoreId + * ----------------------------------------------------- + */ +func platform_get_core_pos + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc platform_get_core_pos diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/compat/plat_compat.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/compat/plat_compat.mk new file mode 100644 index 0000000..c0c8ece --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/compat/plat_compat.mk @@ -0,0 +1,41 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +ifeq (${PSCI_EXTENDED_STATE_ID}, 1) + $(error "PSCI Compatibility mode can be enabled only if \ + PSCI_EXTENDED_STATE_ID is not set") +endif + + +PLAT_BL_COMMON_SOURCES += plat/compat/aarch64/plat_helpers_compat.S + +BL31_SOURCES += plat/common/aarch64/plat_psci_common.c \ + plat/compat/plat_pm_compat.c \ + plat/compat/plat_topology_compat.c diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/compat/plat_pm_compat.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/compat/plat_pm_compat.c new file mode 100644 index 0000000..f51bb55 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/compat/plat_pm_compat.c @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/* + * The platform hooks exported by the platform using the earlier version of + * platform interface + */ +const plat_pm_ops_t *pm_ops; + +/* + * The hooks exported by the compatibility layer + */ +static plat_psci_ops_t compat_psci_ops; + +/* + * The secure entry point to be used on warm reset. + */ +static unsigned long secure_entrypoint; + +/* + * This array stores the 'power_state' requests of each CPU during + * CPU_SUSPEND and SYSTEM_SUSPEND to support querying of state-ID + * by the platform. + */ +unsigned int psci_power_state_compat[PLATFORM_CORE_COUNT]; + +/******************************************************************************* + * The PSCI compatibility helper to parse the power state and populate the + * 'pwr_domain_state' for each power level. It is assumed that, when in + * compatibility mode, the PSCI generic layer need to know only whether the + * affinity level will be OFF or in RETENTION and if the platform supports + * multiple power down and retention states, it will be taken care within + * the platform layer. + ******************************************************************************/ +static int parse_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int i; + int pstate = psci_get_pstate_type(power_state); + int aff_lvl = psci_get_pstate_pwrlvl(power_state); + + if (aff_lvl > PLATFORM_MAX_AFFLVL) + return PSCI_E_INVALID_PARAMS; + + /* Sanity check the requested state */ + if (pstate == PSTATE_TYPE_STANDBY) { + /* + * Set the CPU local state as retention and ignore the higher + * levels. This allows the generic PSCI layer to invoke + * plat_psci_ops 'cpu_standby' hook and the compatibility + * layer invokes the 'affinst_standby' handler with the + * correct power_state parameter thus preserving the correct + * behavior. + */ + req_state->pwr_domain_state[0] = + PLAT_MAX_RET_STATE; + } else { + for (i = 0; i <= aff_lvl; i++) + req_state->pwr_domain_state[i] = + PLAT_MAX_OFF_STATE; + } + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * The PSCI compatibility helper to set the 'power_state' in + * psci_power_state_compat[] at index corresponding to the current core. + ******************************************************************************/ +static void set_psci_power_state_compat(unsigned int power_state) +{ + unsigned int my_core_pos = plat_my_core_pos(); + + psci_power_state_compat[my_core_pos] = power_state; + flush_dcache_range((uintptr_t) &psci_power_state_compat[my_core_pos], + sizeof(psci_power_state_compat[my_core_pos])); +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'validate_power_state' + * hook. + ******************************************************************************/ +static int validate_power_state_compat(unsigned int power_state, + psci_power_state_t *req_state) +{ + int rc; + assert(req_state); + + if (pm_ops->validate_power_state) { + rc = pm_ops->validate_power_state(power_state); + if (rc != PSCI_E_SUCCESS) + return rc; + } + + /* Store the 'power_state' parameter for the current CPU. */ + set_psci_power_state_compat(power_state); + + return parse_power_state(power_state, req_state); +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t + * 'get_sys_suspend_power_state' hook. + ******************************************************************************/ +void get_sys_suspend_power_state_compat(psci_power_state_t *req_state) +{ + unsigned int power_state; + assert(req_state); + + power_state = pm_ops->get_sys_suspend_power_state(); + + /* Store the 'power_state' parameter for the current CPU. */ + set_psci_power_state_compat(power_state); + + if (parse_power_state(power_state, req_state) != PSCI_E_SUCCESS) + assert(0); +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'validate_ns_entrypoint' + * hook. + ******************************************************************************/ +static int validate_ns_entrypoint_compat(uintptr_t ns_entrypoint) +{ + return pm_ops->validate_ns_entrypoint(ns_entrypoint); +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'affinst_standby' hook. + ******************************************************************************/ +static void cpu_standby_compat(plat_local_state_t cpu_state) +{ + unsigned int powerstate = psci_get_suspend_powerstate(); + + assert(powerstate != PSCI_INVALID_DATA); + + pm_ops->affinst_standby(powerstate); +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'affinst_on' hook. + ******************************************************************************/ +static int pwr_domain_on_compat(u_register_t mpidr) +{ + int level, rc; + + /* + * The new PSCI framework does not hold the locks for higher level + * power domain nodes when this hook is invoked. Hence figuring out the + * target state of the parent power domains does not make much sense. + * Hence we hard-code the state as PSCI_STATE_OFF for all the levels. + * We expect the platform to perform the necessary CPU_ON operations + * when the 'affinst_on' is invoked only for level 0. + */ + for (level = PLATFORM_MAX_AFFLVL; level >= 0; level--) { + rc = pm_ops->affinst_on((unsigned long)mpidr, secure_entrypoint, + level, PSCI_STATE_OFF); + if (rc != PSCI_E_SUCCESS) + break; + } + + return rc; +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'affinst_off' hook. + ******************************************************************************/ +static void pwr_domain_off_compat(const psci_power_state_t *target_state) +{ + int level; + unsigned int plat_state; + + for (level = 0; level <= PLATFORM_MAX_AFFLVL; level++) { + plat_state = (is_local_state_run( + target_state->pwr_domain_state[level]) ? + PSCI_STATE_ON : PSCI_STATE_OFF); + pm_ops->affinst_off(level, plat_state); + } +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'affinst_suspend' hook. + ******************************************************************************/ +static void pwr_domain_suspend_compat(const psci_power_state_t *target_state) +{ + int level; + unsigned int plat_state; + + for (level = 0; level <= psci_get_suspend_afflvl(); level++) { + plat_state = (is_local_state_run( + target_state->pwr_domain_state[level]) ? + PSCI_STATE_ON : PSCI_STATE_OFF); + pm_ops->affinst_suspend(secure_entrypoint, level, plat_state); + } +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'affinst_on_finish' + * hook. + ******************************************************************************/ +static void pwr_domain_on_finish_compat(const psci_power_state_t *target_state) +{ + int level; + unsigned int plat_state; + + for (level = PLATFORM_MAX_AFFLVL; level >= 0; level--) { + plat_state = (is_local_state_run( + target_state->pwr_domain_state[level]) ? + PSCI_STATE_ON : PSCI_STATE_OFF); + pm_ops->affinst_on_finish(level, plat_state); + } +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t + * 'affinst_suspend_finish' hook. + ******************************************************************************/ +static void pwr_domain_suspend_finish_compat( + const psci_power_state_t *target_state) +{ + int level; + unsigned int plat_state; + + for (level = psci_get_suspend_afflvl(); level >= 0; level--) { + plat_state = (is_local_state_run( + target_state->pwr_domain_state[level]) ? + PSCI_STATE_ON : PSCI_STATE_OFF); + pm_ops->affinst_suspend_finish(level, plat_state); + } +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'system_off' hook. + ******************************************************************************/ +static void __dead2 system_off_compat(void) +{ + pm_ops->system_off(); +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'system_reset' hook. + ******************************************************************************/ +static void __dead2 system_reset_compat(void) +{ + pm_ops->system_reset(); +} + +/******************************************************************************* + * Export the compatibility compat_psci_ops. The assumption made is that the + * power domains correspond to affinity instances on the platform. + ******************************************************************************/ +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + platform_setup_pm(&pm_ops); + + secure_entrypoint = (unsigned long) sec_entrypoint; + + /* + * It is compulsory for the platform ports using the new porting + * interface to export a hook to validate the power state parameter + */ + compat_psci_ops.validate_power_state = validate_power_state_compat; + + /* + * Populate the compatibility plat_psci_ops_t hooks if available + */ + if (pm_ops->validate_ns_entrypoint) + compat_psci_ops.validate_ns_entrypoint = + validate_ns_entrypoint_compat; + + if (pm_ops->affinst_standby) + compat_psci_ops.cpu_standby = cpu_standby_compat; + + if (pm_ops->affinst_on) + compat_psci_ops.pwr_domain_on = pwr_domain_on_compat; + + if (pm_ops->affinst_off) + compat_psci_ops.pwr_domain_off = pwr_domain_off_compat; + + if (pm_ops->affinst_suspend) + compat_psci_ops.pwr_domain_suspend = pwr_domain_suspend_compat; + + if (pm_ops->affinst_on_finish) + compat_psci_ops.pwr_domain_on_finish = + pwr_domain_on_finish_compat; + + if (pm_ops->affinst_suspend_finish) + compat_psci_ops.pwr_domain_suspend_finish = + pwr_domain_suspend_finish_compat; + + if (pm_ops->system_off) + compat_psci_ops.system_off = system_off_compat; + + if (pm_ops->system_reset) + compat_psci_ops.system_reset = system_reset_compat; + + if (pm_ops->get_sys_suspend_power_state) + compat_psci_ops.get_sys_suspend_power_state = + get_sys_suspend_power_state_compat; + + *psci_ops = &compat_psci_ops; + return 0; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/compat/plat_topology_compat.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/compat/plat_topology_compat.c new file mode 100644 index 0000000..f65ad9d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/compat/plat_topology_compat.c @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/* The power domain tree descriptor */ +static unsigned char power_domain_tree_desc + [PLATFORM_NUM_AFFS - PLATFORM_CORE_COUNT + 1]; + +/******************************************************************************* + * Simple routine to set the id of an affinity instance at a given level + * in the mpidr. The assumption is that the affinity level and the power + * domain level are the same. + ******************************************************************************/ +unsigned long mpidr_set_aff_inst(unsigned long mpidr, + unsigned char aff_inst, + int aff_lvl) +{ + unsigned long aff_shift; + + assert(aff_lvl <= MPIDR_AFFLVL3); + + /* + * Decide the number of bits to shift by depending upon + * the power level + */ + aff_shift = get_afflvl_shift(aff_lvl); + + /* Clear the existing power instance & set the new one*/ + mpidr &= ~((unsigned long)MPIDR_AFFLVL_MASK << aff_shift); + mpidr |= (unsigned long)aff_inst << aff_shift; + + return mpidr; +} + +/****************************************************************************** + * This function uses insertion sort to sort a given list of mpidr's in the + * ascending order of the index returned by platform_get_core_pos. + *****************************************************************************/ +void sort_mpidr_by_cpu_idx(unsigned int aff_count, unsigned long mpidr_list[]) +{ + int i, j; + unsigned long temp_mpidr; + + for (i = 1; i < aff_count; i++) { + temp_mpidr = mpidr_list[i]; + + for (j = i; + j > 0 && + platform_get_core_pos(mpidr_list[j-1]) > + platform_get_core_pos(temp_mpidr); + j--) + mpidr_list[j] = mpidr_list[j-1]; + + mpidr_list[j] = temp_mpidr; + } +} + +/******************************************************************************* + * The compatibility routine to construct the power domain tree description. + * The assumption made is that the power domains correspond to affinity + * instances on the platform. This routine's aim is to traverse to the target + * affinity level and populate the number of siblings at that level in + * 'power_domain_tree_desc' array. It uses the current affinity level to keep + * track of how many levels from the root of the tree have been traversed. + * If the current affinity level != target affinity level, then the platform + * is asked to return the number of children that each affinity instance has + * at the current affinity level. Traversal is then done for each child at the + * next lower level i.e. current affinity level - 1. + * + * The power domain description needs to be constructed in such a way that + * affinity instances containing CPUs with lower cpu indices need to be + * described first. Hence when traversing the power domain levels, the list + * of mpidrs at that power domain level is sorted in the ascending order of CPU + * indices before the lower levels are recursively described. + * + * CAUTION: This routine assumes that affinity instance ids are allocated in a + * monotonically increasing manner at each affinity level in a mpidr starting + * from 0. If the platform breaks this assumption then this code will have to + * be reworked accordingly. + ******************************************************************************/ +static unsigned int init_pwr_domain_tree_desc(unsigned long mpidr, + unsigned int affmap_idx, + int cur_afflvl, + int tgt_afflvl) +{ + unsigned int ctr, aff_count; + + /* + * Temporary list to hold the MPIDR list at a particular power domain + * level so as to sort them. + */ + unsigned long mpidr_list[PLATFORM_CORE_COUNT]; + + assert(cur_afflvl >= tgt_afflvl); + + /* + * Find the number of siblings at the current power level & + * assert if there are none 'cause then we have been invoked with + * an invalid mpidr. + */ + aff_count = plat_get_aff_count(cur_afflvl, mpidr); + assert(aff_count); + + if (tgt_afflvl < cur_afflvl) { + for (ctr = 0; ctr < aff_count; ctr++) { + mpidr_list[ctr] = mpidr_set_aff_inst(mpidr, ctr, + cur_afflvl); + } + + /* Need to sort mpidr list according to CPU index */ + sort_mpidr_by_cpu_idx(aff_count, mpidr_list); + for (ctr = 0; ctr < aff_count; ctr++) { + affmap_idx = init_pwr_domain_tree_desc(mpidr_list[ctr], + affmap_idx, + cur_afflvl - 1, + tgt_afflvl); + } + } else { + power_domain_tree_desc[affmap_idx++] = aff_count; + } + return affmap_idx; +} + + +/******************************************************************************* + * This function constructs the topology tree description at runtime + * and returns it. The assumption made is that the power domains correspond + * to affinity instances on the platform. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + int afflvl, affmap_idx; + + /* + * We assume that the platform allocates affinity instance ids from + * 0 onwards at each affinity level in the mpidr. FIRST_MPIDR = 0.0.0.0 + */ + affmap_idx = 0; + for (afflvl = PLATFORM_MAX_AFFLVL; afflvl >= MPIDR_AFFLVL0; afflvl--) { + affmap_idx = init_pwr_domain_tree_desc(FIRST_MPIDR, + affmap_idx, + PLATFORM_MAX_AFFLVL, + afflvl); + } + + assert(affmap_idx == (PLATFORM_NUM_AFFS - PLATFORM_CORE_COUNT + 1)); + + return power_domain_tree_desc; +} + +/****************************************************************************** + * The compatibility helper function for plat_core_pos_by_mpidr(). It + * validates the 'mpidr' by making sure that it is within acceptable bounds + * for the platform and queries the platform layer whether the CPU specified + * by the mpidr is present or not. If present, it returns the index of the + * core corresponding to the 'mpidr'. Else it returns -1. + *****************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned long shift, aff_inst; + int i; + + /* Ignore the Reserved bits and U bit in MPIDR */ + mpidr &= MPIDR_AFFINITY_MASK; + + /* + * Check if any affinity field higher than + * the PLATFORM_MAX_AFFLVL is set. + */ + shift = get_afflvl_shift(PLATFORM_MAX_AFFLVL + 1); + if (mpidr >> shift) + return -1; + + for (i = PLATFORM_MAX_AFFLVL; i >= 0; i--) { + shift = get_afflvl_shift(i); + aff_inst = ((mpidr & + ((unsigned long)MPIDR_AFFLVL_MASK << shift)) >> shift); + if (aff_inst >= plat_get_aff_count(i, mpidr)) + return -1; + } + + if (plat_get_aff_state(0, mpidr) == PSCI_AFF_ABSENT) + return -1; + + return platform_get_core_pos(mpidr); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/common/mtk_sip_svc.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/common/mtk_sip_svc.c new file mode 100644 index 0000000..af28080 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/common/mtk_sip_svc.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include + +/* Mediatek SiP Service UUID */ +DEFINE_SVC_UUID(mtk_sip_svc_uid, + 0xf7582ba4, 0x4262, 0x4d7d, 0x80, 0xe5, + 0x8f, 0x95, 0x05, 0x00, 0x0f, 0x3d); + +/* + * This function handles Mediatek defined SiP Calls */ +static uint64_t mediatek_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle) +{ + uint64_t ret; + + switch (smc_fid) { + case MTK_SIP_SET_AUTHORIZED_SECURE_REG: + ret = mt_sip_set_authorized_sreg((uint32_t)x1, (uint32_t)x2); + SMC_RET1(handle, ret); + + default: + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + break; + } + + SMC_RET1(handle, SMC_UNK); +} + +/* + * This function is responsible for handling all SiP calls from the NS world + */ +uint64_t sip_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + uint32_t ns; + + /* Determine which security state this SMC originated from */ + ns = is_caller_non_secure(flags); + if (!ns) + SMC_RET1(handle, SMC_UNK); + + switch (smc_fid) { + case SIP_SVC_CALL_COUNT: + /* Return the number of Mediatek SiP Service Calls. */ + SMC_RET1(handle, MTK_SIP_NUM_CALLS); + + case SIP_SVC_UID: + /* Return UID to the caller */ + SMC_UUID_RET(handle, mtk_sip_svc_uid); + + case SIP_SVC_VERSION: + /* Return the version of current implementation */ + SMC_RET2(handle, MTK_SIP_SVC_VERSION_MAJOR, + MTK_SIP_SVC_VERSION_MINOR); + + default: + return mediatek_sip_handler(smc_fid, x1, x2, x3, x4, + cookie, handle); + } +} + +/* Define a runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + mediatek_sip_svc, + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + NULL, + sip_smc_handler +); diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/common/mtk_sip_svc.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/common/mtk_sip_svc.h new file mode 100644 index 0000000..eb1c2e6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/common/mtk_sip_svc.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __PLAT_SIP_SVC_H__ +#define __PLAT_SIP_SVC_H__ + +#include + +/* SMC function IDs for SiP Service queries */ +#define SIP_SVC_CALL_COUNT 0x8200ff00 +#define SIP_SVC_UID 0x8200ff01 +/* 0x8200ff02 is reserved */ +#define SIP_SVC_VERSION 0x8200ff03 + +/* Mediatek SiP Service Calls version numbers */ +#define MTK_SIP_SVC_VERSION_MAJOR 0x0 +#define MTK_SIP_SVC_VERSION_MINOR 0x1 + +/* Number of Mediatek SiP Calls implemented */ +#define MTK_SIP_NUM_CALLS 1 + +/* Mediatek SiP Service Calls function IDs */ +#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001 + +/* Mediatek SiP Calls error code */ +enum { + MTK_SIP_E_SUCCESS = 0, + MTK_SIP_E_INVALID_PARAM = -1 +}; + +/* + * This function should be implemented in Mediatek SOC directory. It fullfills + * MTK_SIP_SET_AUTHORIZED_SECURE_REG SiP call by checking the sreg with the + * predefined secure register list, if a match was found, set val to sreg. + * + * Return MTK_SIP_E_SUCCESS on success, and MTK_SIP_E_INVALID_PARAM on failure. + */ +uint64_t mt_sip_set_authorized_sreg(uint32_t sreg, uint32_t val); + +#endif /* __PLAT_SIP_SVC_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/aarch64/plat_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/aarch64/plat_helpers.S new file mode 100644 index 0000000..99a054c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/aarch64/plat_helpers.S @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + + .globl plat_secondary_cold_boot_setup + .globl plat_report_exception + .globl platform_is_primary_cpu + .globl plat_crash_console_init + .globl plat_crash_console_putc + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* MT8173 Oak does not do cold boot for secondary CPU */ +cb_panic: + b cb_panic +endfunc plat_secondary_cold_boot_setup + +func platform_is_primary_cpu + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #MT8173_PRIMARY_CPU + cset x0, eq + ret +endfunc platform_is_primary_cpu + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0, x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, MT8173_UART0_BASE + mov_imm x1, MT8173_UART_CLOCK + mov_imm x2, MT8173_BAUDRATE + b console_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(void) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, MT8173_UART0_BASE + b console_core_putc +endfunc plat_crash_console_putc diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/aarch64/platform_common.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/aarch64/platform_common.c new file mode 100644 index 0000000..b537f7b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/aarch64/platform_common.c @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +static const int cci_map[] = { + PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX, + PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX +}; + +/* Table of regions to map using the MMU. */ +const mmap_region_t plat_mmap[] = { + /* for TF text, RO, RW */ + MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE + TZRAM2_SIZE, + MT_MEMORY | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + { 0 } + +}; + +/******************************************************************************* + * Macro generating the code for the function setting up the pagetables as per + * the platform memory map & initialize the mmu, for the given exception level + ******************************************************************************/ +#define DEFINE_CONFIGURE_MMU_EL(_el) \ + void plat_configure_mmu_el ## _el(unsigned long total_base, \ + unsigned long total_size, \ + unsigned long ro_start, \ + unsigned long ro_limit, \ + unsigned long coh_start, \ + unsigned long coh_limit) \ + { \ + mmap_add_region(total_base, total_base, \ + total_size, \ + MT_MEMORY | MT_RW | MT_SECURE); \ + mmap_add_region(ro_start, ro_start, \ + ro_limit - ro_start, \ + MT_MEMORY | MT_RO | MT_SECURE); \ + mmap_add_region(coh_start, coh_start, \ + coh_limit - coh_start, \ + MT_DEVICE | MT_RW | MT_SECURE); \ + mmap_add(plat_mmap); \ + init_xlat_tables(); \ + \ + enable_mmu_el ## _el(0); \ + } + +/* Define EL3 variants of the function initialising the MMU */ +DEFINE_CONFIGURE_MMU_EL(3) + +uint64_t plat_get_syscnt_freq(void) +{ + return SYS_COUNTER_FREQ_IN_TICKS; +} + +void plat_cci_init(void) +{ + /* Initialize CCI driver */ + cci_init(PLAT_MT_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); +} + +void plat_cci_enable(void) +{ + /* + * Enable CCI coherency for this cluster. + * No need for locks as no other cpu is active at the moment. + */ + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); +} + +void plat_cci_disable(void) +{ + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/bl31_plat_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/bl31_plat_setup.c new file mode 100644 index 0000000..03ec690 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/bl31_plat_setup.c @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Declarations of linker defined symbols which will help us find the layout + * of trusted SRAM + ******************************************************************************/ +unsigned long __RO_START__; +unsigned long __RO_END__; + +unsigned long __COHERENT_RAM_START__; +unsigned long __COHERENT_RAM_END__; + +/* + * The next 2 constants identify the extents of the code & RO data region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. + */ +#define BL31_RO_BASE (unsigned long)(&__RO_START__) +#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) + +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) + +static entry_point_info_t bl32_ep_info; +static entry_point_info_t bl33_ep_info; + +static void platform_setup_cpu(void) +{ + /* turn off all the little core's power except cpu 0 */ + mtcmos_little_cpu_off(); + + /* setup big cores */ + mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res, + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK | + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK | + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK | + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK | + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK); + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, + MP1_SW_CG_GEN); + mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl, + MP1_L2RSTDISABLE); + + /* set big cores arm64 boot mode */ + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, + MP1_CPUCFG_64BIT); + + /* set LITTLE cores arm64 boot mode */ + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, + MP0_CPUCFG_64BIT); +} + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; + + /* None of the images on this platform can have 0x0 as the entrypoint */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +/******************************************************************************* + * Perform any BL3-1 early platform setup. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they + * are lost (potentially). This needs to be done before the MMU is initialized + * so that the memory layout can be used while creating page tables. + * BL2 has flushed this information to memory, so we are guaranteed to pick up + * good data. + ******************************************************************************/ +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +{ + console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE); + + VERBOSE("bl31_setup\n"); + + assert(from_bl2 != NULL); + assert(from_bl2->h.type == PARAM_BL31); + assert(from_bl2->h.version >= VERSION_1); + + assert(((unsigned long)plat_params_from_bl2) == MT_BL31_PLAT_PARAM_VAL); + + bl32_ep_info = *from_bl2->bl32_ep_info; + bl33_ep_info = *from_bl2->bl33_ep_info; +} + +/******************************************************************************* + * Perform any BL3-1 platform setup code + ******************************************************************************/ +void bl31_platform_setup(void) +{ + platform_setup_cpu(); + + plat_delay_timer_init(); + + /* Initialize the gic cpu and distributor interfaces */ + plat_mt_gic_init(); + arm_gic_setup(); + + /* Topologies are best known to the platform. */ + mt_setup_topology(); + + /* Initialize spm at boot time */ + spm_boot_init(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the mmu in a quick and dirty way. + ******************************************************************************/ +void bl31_plat_arch_setup(void) +{ + plat_cci_init(); + plat_cci_enable(); + + plat_configure_mmu_el3(BL31_RO_BASE, + (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), + BL31_RO_BASE, + BL31_RO_LIMIT, + BL31_COHERENT_RAM_BASE, + BL31_COHERENT_RAM_LIMIT); +} + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/gpio/gpio.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/gpio/gpio.c new file mode 100644 index 0000000..20473b9 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/gpio/gpio.c @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include + +enum { + MAX_GPIO_REG_BITS = 16, +}; + +struct mt_gpio_obj { + struct gpio_regs *reg; +}; + +static struct mt_gpio_obj gpio_dat = { + .reg = (struct gpio_regs *)(GPIO_BASE), +}; + +static struct mt_gpio_obj *gpio_obj = &gpio_dat; + +struct mt_gpioext_obj { + struct gpioext_regs *reg; +}; + +static struct mt_gpioext_obj gpioext_dat = { + .reg = (struct gpioext_regs *)(GPIOEXT_BASE), +}; + +static struct mt_gpioext_obj *gpioext_obj = &gpioext_dat; + +static inline struct mt_gpio_obj *mt_get_gpio_obj(void) +{ + return gpio_obj; +} + +static inline struct mt_gpioext_obj *mt_get_gpioext_obj(void) +{ + return gpioext_obj; +} + +enum { + GPIO_PRO_DIR = 0, + GPIO_PRO_DOUT, + GPIO_PRO_DIN, + GPIO_PRO_PULLEN, + GPIO_PRO_PULLSEL, + GPIO_PRO_MODE, + GPIO_PRO_MAX, +}; + +static inline int32_t gpioext_write(uint16_t *addr, int64_t data) +{ + return pwrap_write((uint32_t)(uintptr_t)addr, data); +} + +static inline int32_t gpioext_set_bits(uint32_t bit, uint16_t *reg) +{ + return gpioext_write(reg, bit); +} + +static int32_t mt_set_gpio_chip(uint32_t pin, uint32_t property, uint32_t val) +{ + uint32_t pos = 0; + uint32_t bit = 0; + struct mt_gpio_obj *obj = mt_get_gpio_obj(); + uint16_t *reg; + uint32_t data = 0; + + if (!obj) + return -ERACCESS; + + if (pin >= GPIO_EXTEND_START) + return -ERINVAL; + + if (property >= GPIO_PRO_MAX) + return -ERINVAL; + + pos = pin / MAX_GPIO_REG_BITS; + bit = pin % MAX_GPIO_REG_BITS; + data = 1L << bit; + + switch (property) { + case GPIO_PRO_DIR: + if (val == GPIO_DIR_IN) + reg = &obj->reg->dir[pos].rst; + else + reg = &obj->reg->dir[pos].set; + break; + case GPIO_PRO_DOUT: + if (val == GPIO_OUT_ZERO) + reg = &obj->reg->dout[pos].rst; + else + reg = &obj->reg->dout[pos].set; + break; + default: + return -ERINVAL; + } + + mmio_write_16((uintptr_t)reg, data); + + return RSUCCESS; +} + +static int32_t mt_set_gpio_ext(uint32_t pin, uint32_t property, uint32_t val) +{ + uint32_t pos = 0; + uint32_t bit = 0; + struct mt_gpioext_obj *obj = mt_get_gpioext_obj(); + uint16_t *reg; + uint32_t data = 0; + int ret = 0; + + if (!obj) + return -ERACCESS; + + if (pin >= MAX_GPIO_PIN) + return -ERINVAL; + + if (property >= GPIO_PRO_MAX) + return -ERINVAL; + + pin -= GPIO_EXTEND_START; + pos = pin / MAX_GPIO_REG_BITS; + bit = pin % MAX_GPIO_REG_BITS; + + switch (property) { + case GPIO_PRO_DIR: + if (val == GPIO_DIR_IN) + reg = &obj->reg->dir[pos].rst; + else + reg = &obj->reg->dir[pos].set; + break; + case GPIO_PRO_DOUT: + if (val == GPIO_OUT_ZERO) + reg = &obj->reg->dout[pos].rst; + else + reg = &obj->reg->dout[pos].set; + break; + default: + return -ERINVAL; + } + data = (1L << bit); + ret = gpioext_set_bits(data, reg); + + return ret ? -ERWRAPPER : RSUCCESS; +} + +static void mt_gpio_pin_decrypt(uint32_t *cipher) +{ + if ((*cipher & (0x80000000)) == 0) + INFO("Pin %u decrypt warning!\n", *cipher); + *cipher &= ~(0x80000000); +} + +int32_t mt_set_gpio_out(uint32_t pin, uint32_t output) +{ + uint32_t gp = GPIO_PRO_DOUT; + + mt_gpio_pin_decrypt(&pin); + + return (pin >= GPIO_EXTEND_START) ? + mt_set_gpio_ext(pin, gp, output) : + mt_set_gpio_chip(pin, gp, output); +} + +void gpio_set(uint32_t gpio, int32_t value) +{ + mt_set_gpio_out(gpio, value); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/gpio/gpio.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/gpio/gpio.h new file mode 100644 index 0000000..ccc99e1 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/gpio/gpio.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __PLAT_DRIVER_GPIO_H__ +#define __PLAT_DRIVER_GPIO_H__ + +#include + +enum { + GPIOEXT_BASE = 0xC000, +}; + +/* Error Code No. */ +enum { + RSUCCESS = 0, + ERACCESS, + ERINVAL, + ERWRAPPER, +}; + +enum { + GPIO_UNSUPPORTED = -1, + + GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, + GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15, + GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23, + GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, GPIO31, + GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38, GPIO39, + GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46, GPIO47, + GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54, GPIO55, + GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62, GPIO63, + GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70, GPIO71, + GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78, GPIO79, + GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86, GPIO87, + GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95, + GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102, GPIO103, + GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110, GPIO111, + GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118, GPIO119, + GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126, GPIO127, + GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134, + + GPIOEXT0, GPIOEXT1, GPIOEXT2, GPIOEXT3, GPIOEXT4, GPIOEXT5, + GPIOEXT6, GPIOEXT7, GPIOEXT8, GPIOEXT9, GPIOEXT10, GPIOEXT11, + GPIOEXT12, GPIOEXT13, GPIOEXT14, GPIOEXT15, GPIOEXT16, GPIOEXT17, + GPIOEXT18, GPIOEXT19, GPIOEXT20, GPIOEXT21, GPIOEXT22, GPIOEXT23, + GPIOEXT24, GPIOEXT25, GPIOEXT26, GPIOEXT27, GPIOEXT28, GPIOEXT29, + GPIOEXT30, GPIOEXT31, GPIOEXT32, GPIOEXT33, GPIOEXT34, GPIOEXT35, + GPIOEXT36, GPIOEXT37, GPIOEXT38, GPIOEXT39, GPIOEXT40, + + GPIO_MAX +}; + +#define MAX_GPIO_PIN GPIO_MAX + +#define GPIO_EXTEND_START GPIOEXT0 + +/* GPIO DIRECTION */ +enum { + GPIO_DIR_UNSUPPORTED = -1, + GPIO_DIR_IN = 0, + GPIO_DIR_OUT = 1, + GPIO_DIR_MAX, + GPIO_DIR_DEFAULT = GPIO_DIR_IN, +}; + +/* GPIO OUTPUT */ +enum { + GPIO_OUT_UNSUPPORTED = -1, + GPIO_OUT_ZERO = 0, + GPIO_OUT_ONE = 1, + GPIO_OUT_MAX, + GPIO_OUT_DEFAULT = GPIO_OUT_ZERO, + GPIO_DATA_OUT_DEFAULT = GPIO_OUT_ZERO, /* compatible with DCT */ +}; + +struct val_regs { + uint16_t val; + uint16_t _align1; + uint16_t set; + uint16_t _align2; + uint16_t rst; + uint16_t _align3[3]; +}; + +struct gpio_regs { + struct val_regs dir[9]; /* 0x0000 ~ 0x008F: 144 bytes */ + uint8_t rsv00[112]; /* 0x0090 ~ 0x00FF: 112 bytes */ + struct val_regs pullen[9]; /* 0x0100 ~ 0x018F: 144 bytes */ + uint8_t rsv01[112]; /* 0x0190 ~ 0x01FF: 112 bytes */ + struct val_regs pullsel[9]; /* 0x0200 ~ 0x028F: 144 bytes */ + uint8_t rsv02[112]; /* 0x0290 ~ 0x02FF: 112 bytes */ + uint8_t rsv03[256]; /* 0x0300 ~ 0x03FF: 256 bytes */ + struct val_regs dout[9]; /* 0x0400 ~ 0x048F: 144 bytes */ + uint8_t rsv04[112]; /* 0x0490 ~ 0x04FF: 112 bytes */ + struct val_regs din[9]; /* 0x0500 ~ 0x058F: 114 bytes */ + uint8_t rsv05[112]; /* 0x0590 ~ 0x05FF: 112 bytes */ + struct val_regs mode[27]; /* 0x0600 ~ 0x07AF: 432 bytes */ + uint8_t rsv06[336]; /* 0x07B0 ~ 0x08FF: 336 bytes */ + struct val_regs ies[3]; /* 0x0900 ~ 0x092F: 48 bytes */ + struct val_regs smt[3]; /* 0x0930 ~ 0x095F: 48 bytes */ + uint8_t rsv07[160]; /* 0x0960 ~ 0x09FF: 160 bytes */ + struct val_regs tdsel[8]; /* 0x0A00 ~ 0x0A7F: 128 bytes */ + struct val_regs rdsel[6]; /* 0x0A80 ~ 0x0ADF: 96 bytes */ + uint8_t rsv08[32]; /* 0x0AE0 ~ 0x0AFF: 32 bytes */ + struct val_regs drv_mode[10]; /* 0x0B00 ~ 0x0B9F: 160 bytes */ + uint8_t rsv09[96]; /* 0x0BA0 ~ 0x0BFF: 96 bytes */ + struct val_regs msdc0_ctrl0; /* 0x0C00 ~ 0x0C0F: 16 bytes */ + struct val_regs msdc0_ctrl1; /* 0x0C10 ~ 0x0C1F: 16 bytes */ + struct val_regs msdc0_ctrl2; /* 0x0C20 ~ 0x0C2F: 16 bytes */ + struct val_regs msdc0_ctrl5; /* 0x0C30 ~ 0x0C3F: 16 bytes */ + struct val_regs msdc1_ctrl0; /* 0x0C40 ~ 0x0C4F: 16 bytes */ + struct val_regs msdc1_ctrl1; /* 0x0C50 ~ 0x0C5F: 16 bytes */ + struct val_regs msdc1_ctrl2; /* 0x0C60 ~ 0x0C6F: 16 bytes */ + struct val_regs msdc1_ctrl5; /* 0x0C70 ~ 0x0C7F: 16 bytes */ + struct val_regs msdc2_ctrl0; /* 0x0C80 ~ 0x0C8F: 16 bytes */ + struct val_regs msdc2_ctrl1; /* 0x0C90 ~ 0x0C9F: 16 bytes */ + struct val_regs msdc2_ctrl2; /* 0x0CA0 ~ 0x0CAF: 16 bytes */ + struct val_regs msdc2_ctrl5; /* 0x0CB0 ~ 0x0CBF: 16 bytes */ + struct val_regs msdc3_ctrl0; /* 0x0CC0 ~ 0x0CCF: 16 bytes */ + struct val_regs msdc3_ctrl1; /* 0x0CD0 ~ 0x0CDF: 16 bytes */ + struct val_regs msdc3_ctrl2; /* 0x0CE0 ~ 0x0CEF: 16 bytes */ + struct val_regs msdc3_ctrl5; /* 0x0CF0 ~ 0x0CFF: 16 bytes */ + struct val_regs msdc0_ctrl3; /* 0x0D00 ~ 0x0D0F: 16 bytes */ + struct val_regs msdc0_ctrl4; /* 0x0D10 ~ 0x0D1F: 16 bytes */ + struct val_regs msdc1_ctrl3; /* 0x0D20 ~ 0x0D2F: 16 bytes */ + struct val_regs msdc1_ctrl4; /* 0x0D30 ~ 0x0D3F: 16 bytes */ + struct val_regs msdc2_ctrl3; /* 0x0D40 ~ 0x0D4F: 16 bytes */ + struct val_regs msdc2_ctrl4; /* 0x0D50 ~ 0x0D5F: 16 bytes */ + struct val_regs msdc3_ctrl3; /* 0x0D60 ~ 0x0D6F: 16 bytes */ + struct val_regs msdc3_ctrl4; /* 0x0D70 ~ 0x0D7F: 16 bytes */ + uint8_t rsv10[64]; /* 0x0D80 ~ 0x0DBF: 64 bytes */ + struct val_regs exmd_ctrl[1]; /* 0x0DC0 ~ 0x0DCF: 16 bytes */ + uint8_t rsv11[48]; /* 0x0DD0 ~ 0x0DFF: 48 bytes */ + struct val_regs kpad_ctrl[2]; /* 0x0E00 ~ 0x0E1F: 32 bytes */ + struct val_regs hsic_ctrl[4]; /* 0x0E20 ~ 0x0E5F: 64 bytes */ +}; + +struct ext_val_regs { + uint16_t val; + uint16_t set; + uint16_t rst; + uint16_t _align; +}; + +struct gpioext_regs { + struct ext_val_regs dir[4]; /* 0x0000 ~ 0x001F: 32 bytes */ + struct ext_val_regs pullen[4]; /* 0x0020 ~ 0x003F: 32 bytes */ + struct ext_val_regs pullsel[4]; /* 0x0040 ~ 0x005F: 32 bytes */ + struct ext_val_regs dinv[4]; /* 0x0060 ~ 0x007F: 32 bytes */ + struct ext_val_regs dout[4]; /* 0x0080 ~ 0x009F: 32 bytes */ + struct ext_val_regs din[4]; /* 0x00A0 ~ 0x00BF: 32 bytes */ + struct ext_val_regs mode[10]; /* 0x00C0 ~ 0x010F: 80 bytes */ +}; + +/* GPIO Driver interface */ +void gpio_set(uint32_t gpio, int32_t value); + +#endif /* __PLAT_DRIVER_GPIO_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.c new file mode 100644 index 0000000..f7a1b07 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.c @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include + +enum { + SRAM_ISOINT_B = 1U << 6, + SRAM_CKISO = 1U << 5, + PWR_CLK_DIS = 1U << 4, + PWR_ON_2ND = 1U << 3, + PWR_ON = 1U << 2, + PWR_ISO = 1U << 1, + PWR_RST_B = 1U << 0 +}; + +enum { + L1_PDN_ACK = 1U << 8, + L1_PDN = 1U << 0 +}; + +enum { + LITTLE_CPU3 = 1U << 12, + LITTLE_CPU2 = 1U << 11, + LITTLE_CPU1 = 1U << 10, +}; + +enum { + SRAM_PDN = 0xf << 8, + DIS_SRAM_ACK = 0x1 << 12, + AUD_SRAM_ACK = 0xf << 12, +}; + +enum { + DIS_PWR_STA_MASK = 0x1 << 3, + AUD_PWR_STA_MASK = 0x1 << 24, +}; + +static void mtcmos_ctrl_little_off(unsigned int linear_id) +{ + uint32_t reg_pwr_con; + uint32_t reg_l1_pdn; + uint32_t bit_cpu; + + switch (linear_id) { + case 1: + reg_pwr_con = SPM_CA7_CPU1_PWR_CON; + reg_l1_pdn = SPM_CA7_CPU1_L1_PDN; + bit_cpu = LITTLE_CPU1; + break; + case 2: + reg_pwr_con = SPM_CA7_CPU2_PWR_CON; + reg_l1_pdn = SPM_CA7_CPU2_L1_PDN; + bit_cpu = LITTLE_CPU2; + break; + case 3: + reg_pwr_con = SPM_CA7_CPU3_PWR_CON; + reg_l1_pdn = SPM_CA7_CPU3_L1_PDN; + bit_cpu = LITTLE_CPU3; + break; + default: + /* should never come to here */ + return; + } + + /* enable register control */ + mmio_write_32(SPM_POWERON_CONFIG_SET, + (SPM_PROJECT_CODE << 16) | (1U << 0)); + + mmio_setbits_32(reg_pwr_con, PWR_ISO); + mmio_setbits_32(reg_pwr_con, SRAM_CKISO); + mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B); + mmio_setbits_32(reg_l1_pdn, L1_PDN); + + while (!(mmio_read_32(reg_l1_pdn) & L1_PDN_ACK)) + continue; + + mmio_clrbits_32(reg_pwr_con, PWR_RST_B); + mmio_setbits_32(reg_pwr_con, PWR_CLK_DIS); + mmio_clrbits_32(reg_pwr_con, PWR_ON); + mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND); + + while ((mmio_read_32(SPM_PWR_STATUS) & bit_cpu) || + (mmio_read_32(SPM_PWR_STATUS_2ND) & bit_cpu)) + continue; +} + +void mtcmos_little_cpu_off(void) +{ + /* turn off little cpu 1 - 3 */ + mtcmos_ctrl_little_off(1); + mtcmos_ctrl_little_off(2); + mtcmos_ctrl_little_off(3); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.h new file mode 100644 index 0000000..ddcda78 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MTCMOS_H__ +#define __MTCMOS_H__ + +/* + * This function will turn off all the little core's power except cpu 0. The + * cores in cluster 0 are all powered when the system power on. The System + * Power Manager (SPM) will do nothing if it found the core's power was on + * during CPU_ON psci call. + */ +void mtcmos_little_cpu_off(void); + +#endif /* __MTCMOS_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.c new file mode 100644 index 0000000..48908c7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.c @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include + +/* pmic wrap module wait_idle and read polling interval (in microseconds) */ +enum { + WAIT_IDLE_POLLING_DELAY_US = 1, + READ_POLLING_DELAY_US = 2 +}; + +static inline uint32_t wait_for_state_idle(uint32_t timeout_us, + void *wacs_register, + void *wacs_vldclr_register, + uint32_t *read_reg) +{ + uint32_t reg_rdata; + uint32_t retry; + + retry = (timeout_us + WAIT_IDLE_POLLING_DELAY_US) / + WAIT_IDLE_POLLING_DELAY_US; + + do { + udelay(WAIT_IDLE_POLLING_DELAY_US); + reg_rdata = mmio_read_32((uintptr_t)wacs_register); + /* if last read command timeout,clear vldclr bit + read command state machine:FSM_REQ-->wfdle-->WFVLDCLR; + write:FSM_REQ-->idle */ + switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & + RDATA_WACS_FSM_MASK)) { + case WACS_FSM_WFVLDCLR: + mmio_write_32((uintptr_t)wacs_vldclr_register, 1); + ERROR("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n"); + break; + case WACS_FSM_WFDLE: + ERROR("WACS_FSM = WACS_FSM_WFDLE\n"); + break; + case WACS_FSM_REQ: + ERROR("WACS_FSM = WACS_FSM_REQ\n"); + break; + case WACS_FSM_IDLE: + goto done; + default: + break; + } + + retry--; + } while (retry); + +done: + if (!retry) /* timeout */ + return E_PWR_WAIT_IDLE_TIMEOUT; + + if (read_reg) + *read_reg = reg_rdata; + return 0; +} + +static inline uint32_t wait_for_state_ready(uint32_t timeout_us, + void *wacs_register, + uint32_t *read_reg) +{ + uint32_t reg_rdata; + uint32_t retry; + + retry = (timeout_us + READ_POLLING_DELAY_US) / READ_POLLING_DELAY_US; + + do { + udelay(READ_POLLING_DELAY_US); + reg_rdata = mmio_read_32((uintptr_t)wacs_register); + + if (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) + == WACS_FSM_WFVLDCLR) + break; + + retry--; + } while (retry); + + if (!retry) { /* timeout */ + ERROR("timeout when waiting for idle\n"); + return E_PWR_WAIT_IDLE_TIMEOUT_READ; + } + + if (read_reg) + *read_reg = reg_rdata; + return 0; +} + +static int32_t pwrap_wacs2(uint32_t write, + uint32_t adr, + uint32_t wdata, + uint32_t *rdata, + uint32_t init_check) +{ + uint32_t reg_rdata = 0; + uint32_t wacs_write = 0; + uint32_t wacs_adr = 0; + uint32_t wacs_cmd = 0; + uint32_t return_value = 0; + + if (init_check) { + reg_rdata = mmio_read_32((uintptr_t)&mt8173_pwrap->wacs2_rdata); + /* Prevent someone to used pwrap before pwrap init */ + if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) & + RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { + ERROR("initialization isn't finished\n"); + return E_PWR_NOT_INIT_DONE; + } + } + reg_rdata = 0; + /* Check IDLE in advance */ + return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE, + &mt8173_pwrap->wacs2_rdata, + &mt8173_pwrap->wacs2_vldclr, + 0); + if (return_value != 0) { + ERROR("wait_for_fsm_idle fail,return_value=%d\n", return_value); + goto FAIL; + } + wacs_write = write << 31; + wacs_adr = (adr >> 1) << 16; + wacs_cmd = wacs_write | wacs_adr | wdata; + + mmio_write_32((uintptr_t)&mt8173_pwrap->wacs2_cmd, wacs_cmd); + if (write == 0) { + if (NULL == rdata) { + ERROR("rdata is a NULL pointer\n"); + return_value = E_PWR_INVALID_ARG; + goto FAIL; + } + return_value = wait_for_state_ready(TIMEOUT_READ, + &mt8173_pwrap->wacs2_rdata, + ®_rdata); + if (return_value != 0) { + ERROR("wait_for_fsm_vldclr fail,return_value=%d\n", + return_value); + goto FAIL; + } + *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT) + & RDATA_WACS_RDATA_MASK); + mmio_write_32((uintptr_t)&mt8173_pwrap->wacs2_vldclr, 1); + } +FAIL: + return return_value; +} + +/* external API for pmic_wrap user */ + +int32_t pwrap_read(uint32_t adr, uint32_t *rdata) +{ + return pwrap_wacs2(0, adr, 0, rdata, 1); +} + +int32_t pwrap_write(uint32_t adr, uint32_t wdata) +{ + return pwrap_wacs2(1, adr, wdata, 0, 1); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h new file mode 100644 index 0000000..0b20500 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PMIC_WRAP_INIT_H__ +#define __PMIC_WRAP_INIT_H__ + +/* external API */ +int32_t pwrap_read(uint32_t adr, uint32_t *rdata); +int32_t pwrap_write(uint32_t adr, uint32_t wdata); + +static struct mt8173_pmic_wrap_regs *const mt8173_pwrap = + (void *)PMIC_WRAP_BASE; + +/* timeout setting */ +enum { + TIMEOUT_RESET = 50, /* us */ + TIMEOUT_READ = 50, /* us */ + TIMEOUT_WAIT_IDLE = 50 /* us */ +}; + +/* PMIC_WRAP registers */ +struct mt8173_pmic_wrap_regs { + uint32_t mux_sel; + uint32_t wrap_en; + uint32_t dio_en; + uint32_t sidly; + uint32_t rddmy; + uint32_t si_ck_con; + uint32_t cshext_write; + uint32_t cshext_read; + uint32_t cslext_start; + uint32_t cslext_end; + uint32_t staupd_prd; + uint32_t staupd_grpen; + uint32_t reserved[4]; + uint32_t staupd_man_trig; + uint32_t staupd_sta; + uint32_t wrap_sta; + uint32_t harb_init; + uint32_t harb_hprio; + uint32_t hiprio_arb_en; + uint32_t harb_sta0; + uint32_t harb_sta1; + uint32_t man_en; + uint32_t man_cmd; + uint32_t man_rdata; + uint32_t man_vldclr; + uint32_t wacs0_en; + uint32_t init_done0; + uint32_t wacs0_cmd; + uint32_t wacs0_rdata; + uint32_t wacs0_vldclr; + uint32_t wacs1_en; + uint32_t init_done1; + uint32_t wacs1_cmd; + uint32_t wacs1_rdata; + uint32_t wacs1_vldclr; + uint32_t wacs2_en; + uint32_t init_done2; + uint32_t wacs2_cmd; + uint32_t wacs2_rdata; + uint32_t wacs2_vldclr; + uint32_t int_en; + uint32_t int_flg_raw; + uint32_t int_flg; + uint32_t int_clr; + uint32_t sig_adr; + uint32_t sig_mode; + uint32_t sig_value; + uint32_t sig_errval; + uint32_t crc_en; + uint32_t timer_en; + uint32_t timer_sta; + uint32_t wdt_unit; + uint32_t wdt_src_en; + uint32_t wdt_flg; + uint32_t debug_int_sel; + uint32_t dvfs_adr0; + uint32_t dvfs_wdata0; + uint32_t dvfs_adr1; + uint32_t dvfs_wdata1; + uint32_t dvfs_adr2; + uint32_t dvfs_wdata2; + uint32_t dvfs_adr3; + uint32_t dvfs_wdata3; + uint32_t dvfs_adr4; + uint32_t dvfs_wdata4; + uint32_t dvfs_adr5; + uint32_t dvfs_wdata5; + uint32_t dvfs_adr6; + uint32_t dvfs_wdata6; + uint32_t dvfs_adr7; + uint32_t dvfs_wdata7; + uint32_t spminf_sta; + uint32_t cipher_key_sel; + uint32_t cipher_iv_sel; + uint32_t cipher_en; + uint32_t cipher_rdy; + uint32_t cipher_mode; + uint32_t cipher_swrst; + uint32_t dcm_en; + uint32_t dcm_dbc_prd; +}; + +enum { + RDATA_WACS_RDATA_SHIFT = 0, + RDATA_WACS_FSM_SHIFT = 16, + RDATA_WACS_REQ_SHIFT = 19, + RDATA_SYNC_IDLE_SHIFT, + RDATA_INIT_DONE_SHIFT, + RDATA_SYS_IDLE_SHIFT, +}; + +enum { + RDATA_WACS_RDATA_MASK = 0xffff, + RDATA_WACS_FSM_MASK = 0x7, + RDATA_WACS_REQ_MASK = 0x1, + RDATA_SYNC_IDLE_MASK = 0x1, + RDATA_INIT_DONE_MASK = 0x1, + RDATA_SYS_IDLE_MASK = 0x1, +}; + +/* WACS_FSM */ +enum { + WACS_FSM_IDLE = 0x00, + WACS_FSM_REQ = 0x02, + WACS_FSM_WFDLE = 0x04, + WACS_FSM_WFVLDCLR = 0x06, + WACS_INIT_DONE = 0x01, + WACS_SYNC_IDLE = 0x01, + WACS_SYNC_BUSY = 0x00 +}; + +/* error information flag */ +enum { + E_PWR_INVALID_ARG = 1, + E_PWR_INVALID_RW = 2, + E_PWR_INVALID_ADDR = 3, + E_PWR_INVALID_WDAT = 4, + E_PWR_INVALID_OP_MANUAL = 5, + E_PWR_NOT_IDLE_STATE = 6, + E_PWR_NOT_INIT_DONE = 7, + E_PWR_NOT_INIT_DONE_READ = 8, + E_PWR_WAIT_IDLE_TIMEOUT = 9, + E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, + E_PWR_INIT_SIDLY_FAIL = 11, + E_PWR_RESET_TIMEOUT = 12, + E_PWR_TIMEOUT = 13, + E_PWR_INIT_RESET_SPI = 20, + E_PWR_INIT_SIDLY = 21, + E_PWR_INIT_REG_CLOCK = 22, + E_PWR_INIT_ENABLE_PMIC = 23, + E_PWR_INIT_DIO = 24, + E_PWR_INIT_CIPHER = 25, + E_PWR_INIT_WRITE_TEST = 26, + E_PWR_INIT_ENABLE_CRC = 27, + E_PWR_INIT_ENABLE_DEWRAP = 28, + E_PWR_INIT_ENABLE_EVENT = 29, + E_PWR_READ_TEST_FAIL = 30, + E_PWR_WRITE_TEST_FAIL = 31, + E_PWR_SWITCH_DIO = 32 +}; + +#endif /* __PMIC_WRAP_INIT_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/rtc/rtc.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/rtc/rtc.c new file mode 100644 index 0000000..e171863 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/rtc/rtc.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include + +/* RTC busy status polling interval and retry count */ +enum { + RTC_WRTGR_POLLING_DELAY_MS = 10, + RTC_WRTGR_POLLING_CNT = 100 +}; + +static uint16_t RTC_Read(uint32_t addr) +{ + uint32_t rdata = 0; + + pwrap_read((uint32_t)addr, &rdata); + return (uint16_t)rdata; +} + +static void RTC_Write(uint32_t addr, uint16_t data) +{ + pwrap_write((uint32_t)addr, (uint32_t)data); +} + +static inline int32_t rtc_busy_wait(void) +{ + uint64_t retry = RTC_WRTGR_POLLING_CNT; + + do { + mdelay(RTC_WRTGR_POLLING_DELAY_MS); + if (!(RTC_Read(RTC_BBPU) & RTC_BBPU_CBUSY)) + return 1; + retry--; + } while (retry); + + ERROR("[RTC] rtc cbusy time out!\n"); + return 0; +} + +static int32_t Write_trigger(void) +{ + RTC_Write(RTC_WRTGR, 1); + return rtc_busy_wait(); +} + +static int32_t Writeif_unlock(void) +{ + RTC_Write(RTC_PROT, RTC_PROT_UNLOCK1); + if (!Write_trigger()) + return 0; + RTC_Write(RTC_PROT, RTC_PROT_UNLOCK2); + if (!Write_trigger()) + return 0; + + return 1; +} + +void rtc_bbpu_power_down(void) +{ + uint16_t bbpu; + + /* pull PWRBB low */ + bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_PWREN; + if (Writeif_unlock()) { + RTC_Write(RTC_BBPU, bbpu); + if (!Write_trigger()) + assert(1); + } else { + assert(1); + } +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/rtc/rtc.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/rtc/rtc.h new file mode 100644 index 0000000..c2138cd --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/rtc/rtc.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_DRIVER_RTC_H__ +#define __PLAT_DRIVER_RTC_H__ + +/* RTC registers */ +enum { + RTC_BBPU = 0xE000, + RTC_IRQ_STA = 0xE002, + RTC_IRQ_EN = 0xE004, + RTC_CII_EN = 0xE006 +}; + +enum { + RTC_OSC32CON = 0xE026, + RTC_CON = 0xE03E, + RTC_WRTGR = 0xE03C +}; + +enum { + RTC_PDN1 = 0xE02C, + RTC_PDN2 = 0xE02E, + RTC_SPAR0 = 0xE030, + RTC_SPAR1 = 0xE032, + RTC_PROT = 0xE036, + RTC_DIFF = 0xE038, + RTC_CALI = 0xE03A +}; + +enum { + RTC_PROT_UNLOCK1 = 0x586A, + RTC_PROT_UNLOCK2 = 0x9136 +}; + +enum { + RTC_BBPU_PWREN = 1U << 0, + RTC_BBPU_BBPU = 1U << 2, + RTC_BBPU_AUTO = 1U << 3, + RTC_BBPU_CLRPKY = 1U << 4, + RTC_BBPU_RELOAD = 1U << 5, + RTC_BBPU_CBUSY = 1U << 6 +}; + +enum { + RTC_BBPU_KEY = 0x43 << 8 +}; + +void rtc_bbpu_power_down(void); + +#endif /* __PLAT_DRIVER_RTC_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm.c new file mode 100644 index 0000000..7c6d72b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm.c @@ -0,0 +1,391 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include + +/* + * System Power Manager (SPM) is a hardware module, which controls cpu or + * system power for different power scenarios using different firmware, i.e., + * - spm_hotplug.c for cpu power control in cpu hotplug flow. + * - spm_mcdi.c for cpu power control in cpu idle power saving state. + * - spm_suspend.c for system power control in system suspend scenario. + * + * This file provide utility functions common to hotplug, mcdi(idle), suspend + * power scenarios. A bakery lock (software lock) is incoporated to protect + * certain critical sections to avoid kicking different SPM firmware + * concurrently. + */ + +#define SPM_SYSCLK_SETTLE 128 /* 3.9ms */ + +#if DEBUG +static int spm_dormant_sta = CPU_DORMANT_RESET; +#endif + +DEFINE_BAKERY_LOCK(spm_lock); + +static int spm_hotplug_ready __attribute__ ((section("tzfw_coherent_mem"))); +static int spm_mcdi_ready __attribute__ ((section("tzfw_coherent_mem"))); +static int spm_suspend_ready __attribute__ ((section("tzfw_coherent_mem"))); + +void spm_lock_init(void) +{ + bakery_lock_init(&spm_lock); +} + +void spm_lock_get(void) +{ + bakery_lock_get(&spm_lock); +} + +void spm_lock_release(void) +{ + bakery_lock_release(&spm_lock); +} + +int is_mcdi_ready(void) +{ + return spm_mcdi_ready; +} + +int is_hotplug_ready(void) +{ + return spm_hotplug_ready; +} + +int is_suspend_ready(void) +{ + return spm_suspend_ready; +} + +void set_mcdi_ready(void) +{ + spm_mcdi_ready = 1; + spm_hotplug_ready = 0; + spm_suspend_ready = 0; +} + +void set_hotplug_ready(void) +{ + spm_mcdi_ready = 0; + spm_hotplug_ready = 1; + spm_suspend_ready = 0; +} + +void set_suspend_ready(void) +{ + spm_mcdi_ready = 0; + spm_hotplug_ready = 0; + spm_suspend_ready = 1; +} + +void clear_all_ready(void) +{ + spm_mcdi_ready = 0; + spm_hotplug_ready = 0; + spm_suspend_ready = 0; +} + +void spm_register_init(void) +{ + mmio_write_32(SPM_POWERON_CONFIG_SET, SPM_REGWR_CFG_KEY | SPM_REGWR_EN); + + mmio_write_32(SPM_POWER_ON_VAL0, 0); + mmio_write_32(SPM_POWER_ON_VAL1, POWER_ON_VAL1_DEF); + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); + + mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); + mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); + if (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) + WARN("PCM reset failed\n"); + + mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); + mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_EVENT_LOCK_EN | + CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | CON1_MIF_APBEN); + mmio_write_32(SPM_PCM_IM_PTR, 0); + mmio_write_32(SPM_PCM_IM_LEN, 0); + + mmio_write_32(SPM_CLK_CON, CC_SYSCLK0_EN_1 | CC_SYSCLK0_EN_0 | + CC_SYSCLK1_EN_0 | CC_SRCLKENA_MASK_0 | CC_CLKSQ1_SEL | + CC_CXO32K_RM_EN_MD2 | CC_CXO32K_RM_EN_MD1 | CC_MD32_DCM_EN); + + mmio_write_32(SPM_SLEEP_ISR_MASK, 0xff0c); + mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xc); + mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xff); + mmio_write_32(SPM_MD32_SRAM_CON, 0xff0); +} + +void spm_reset_and_init_pcm(void) +{ + unsigned int con1; + int i = 0; + + mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); + mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); + while (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) { + i++; + if (i > 1000) { + i = 0; + WARN("PCM reset failed\n"); + break; + } + } + + mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); + + con1 = mmio_read_32(SPM_PCM_CON1) & + (CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN); + mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_EVENT_LOCK_EN | + CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | + CON1_IM_NONRP_EN | CON1_MIF_APBEN); +} + +void spm_init_pcm_register(void) +{ + mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL0)); + mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R0); + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); + + mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL1)); + mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R7); + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); +} + +void spm_set_power_control(const struct pwr_ctrl *pwrctrl) +{ + mmio_write_32(SPM_AP_STANBY_CON, (!pwrctrl->md32_req_mask << 21) | + (!pwrctrl->mfg_req_mask << 17) | + (!pwrctrl->disp_req_mask << 16) | + (!!pwrctrl->mcusys_idle_mask << 7) | + (!!pwrctrl->ca15top_idle_mask << 6) | + (!!pwrctrl->ca7top_idle_mask << 5) | + (!!pwrctrl->wfi_op << 4)); + mmio_write_32(SPM_PCM_SRC_REQ, (!!pwrctrl->pcm_apsrc_req << 0)); + mmio_write_32(SPM_PCM_PASR_DPD_2, 0); + + mmio_clrsetbits_32(SPM_CLK_CON, CC_SRCLKENA_MASK_0, + (pwrctrl->srclkenai_mask ? CC_SRCLKENA_MASK_0 : 0)); + + mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, !!pwrctrl->ca15_wfi0_en); + mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, !!pwrctrl->ca15_wfi1_en); + mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, !!pwrctrl->ca15_wfi2_en); + mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, !!pwrctrl->ca15_wfi3_en); + mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, !!pwrctrl->ca7_wfi0_en); + mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, !!pwrctrl->ca7_wfi1_en); + mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, !!pwrctrl->ca7_wfi2_en); + mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, !!pwrctrl->ca7_wfi3_en); +} + +void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) +{ + unsigned int val, mask; + + if (pwrctrl->timer_val_cust == 0) + val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; + else + val = pwrctrl->timer_val_cust; + + mmio_write_32(SPM_PCM_TIMER_VAL, val); + mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY); + + if (pwrctrl->wake_src_cust == 0) + mask = pwrctrl->wake_src; + else + mask = pwrctrl->wake_src_cust; + + if (pwrctrl->syspwreq_mask) + mask &= ~WAKE_SRC_SYSPWREQ; + + mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~mask); + mmio_write_32(SPM_SLEEP_ISR_MASK, 0xfe04); +} + +void spm_get_wakeup_status(struct wake_status *wakesta) +{ + wakesta->assert_pc = mmio_read_32(SPM_PCM_REG_DATA_INI); + wakesta->r12 = mmio_read_32(SPM_PCM_REG12_DATA); + wakesta->raw_sta = mmio_read_32(SPM_SLEEP_ISR_RAW_STA); + wakesta->wake_misc = mmio_read_32(SPM_SLEEP_WAKEUP_MISC); + wakesta->timer_out = mmio_read_32(SPM_PCM_TIMER_OUT); + wakesta->r13 = mmio_read_32(SPM_PCM_REG13_DATA); + wakesta->idle_sta = mmio_read_32(SPM_SLEEP_SUBSYS_IDLE_STA); + wakesta->debug_flag = mmio_read_32(SPM_PCM_PASR_DPD_3); + wakesta->event_reg = mmio_read_32(SPM_PCM_EVENT_REG_STA); + wakesta->isr = mmio_read_32(SPM_SLEEP_ISR_STATUS); +} + +void spm_init_event_vector(const struct pcm_desc *pcmdesc) +{ + /* init event vector register */ + mmio_write_32(SPM_PCM_EVENT_VECTOR0, pcmdesc->vec0); + mmio_write_32(SPM_PCM_EVENT_VECTOR1, pcmdesc->vec1); + mmio_write_32(SPM_PCM_EVENT_VECTOR2, pcmdesc->vec2); + mmio_write_32(SPM_PCM_EVENT_VECTOR3, pcmdesc->vec3); + mmio_write_32(SPM_PCM_EVENT_VECTOR4, pcmdesc->vec4); + mmio_write_32(SPM_PCM_EVENT_VECTOR5, pcmdesc->vec5); + mmio_write_32(SPM_PCM_EVENT_VECTOR6, pcmdesc->vec6); + mmio_write_32(SPM_PCM_EVENT_VECTOR7, pcmdesc->vec7); + + /* event vector will be enabled by PCM itself */ +} + +void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc) +{ + unsigned int ptr = 0, len, con0; + + ptr = (unsigned int)(unsigned long)(pcmdesc->base); + len = pcmdesc->size - 1; + if (mmio_read_32(SPM_PCM_IM_PTR) != ptr || + mmio_read_32(SPM_PCM_IM_LEN) != len || + pcmdesc->sess > 2) { + mmio_write_32(SPM_PCM_IM_PTR, ptr); + mmio_write_32(SPM_PCM_IM_LEN, len); + } else { + mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_IM_SLAVE); + } + + /* kick IM to fetch (only toggle IM_KICK) */ + con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK); + mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_IM_KICK); + mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY); + + /* kick IM to fetch (only toggle PCM_KICK) */ + con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK); + mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_PCM_KICK); + mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY); +} + +void spm_set_sysclk_settle(void) +{ + mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE); + + INFO("settle = %u\n", mmio_read_32(SPM_CLK_SETTLE)); +} + +void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl) +{ + unsigned int con1; + + con1 = mmio_read_32(SPM_PCM_CON1) & + ~(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN); + + mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | con1); + + if (mmio_read_32(SPM_PCM_TIMER_VAL) > PCM_TIMER_MAX) + mmio_write_32(SPM_PCM_TIMER_VAL, PCM_TIMER_MAX); + + mmio_write_32(SPM_PCM_WDT_TIMER_VAL, + mmio_read_32(SPM_PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); + + mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_PCM_WDT_EN); + mmio_write_32(SPM_PCM_PASR_DPD_0, 0); + + mmio_write_32(SPM_PCM_MAS_PAUSE_MASK, 0xffffffff); + mmio_write_32(SPM_PCM_REG_DATA_INI, 0); + mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR); + + mmio_write_32(SPM_PCM_FLAGS, pwrctrl->pcm_flags); + + mmio_clrsetbits_32(SPM_CLK_CON, CC_LOCK_INFRA_DCM, + (pwrctrl->infra_dcm_lock ? CC_LOCK_INFRA_DCM : 0)); + + mmio_write_32(SPM_PCM_PWR_IO_EN, + (pwrctrl->r0_ctrl_en ? PCM_PWRIO_EN_R0 : 0) | + (pwrctrl->r7_ctrl_en ? PCM_PWRIO_EN_R7 : 0)); +} + +void spm_clean_after_wakeup(void) +{ + mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_WDT_EN, CON1_CFG_KEY); + + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); + mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, 0); + mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_TIMER_EN, CON1_CFG_KEY); + + mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~0); + mmio_write_32(SPM_SLEEP_ISR_MASK, 0xFF0C); + mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xC); + mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xFF); +} + +enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta) +{ + enum wake_reason_t wr; + int i; + + wr = WR_UNKNOWN; + + if (wakesta->assert_pc != 0) { + ERROR("PCM ASSERT AT %u, r12=0x%x, r13=0x%x, debug_flag=0x%x\n", + wakesta->assert_pc, wakesta->r12, wakesta->r13, + wakesta->debug_flag); + return WR_PCM_ASSERT; + } + + if (wakesta->r12 & WAKE_SRC_SPM_MERGE) { + if (wakesta->wake_misc & WAKE_MISC_PCM_TIMER) + wr = WR_PCM_TIMER; + if (wakesta->wake_misc & WAKE_MISC_CPU_WAKE) + wr = WR_WAKE_SRC; + } + + for (i = 1; i < 32; i++) { + if (wakesta->r12 & (1U << i)) + wr = WR_WAKE_SRC; + } + + if ((wakesta->event_reg & 0x100000) == 0) { + INFO("pcm sleep abort!\n"); + wr = WR_PCM_ABORT; + } + + INFO("timer_out = %u, r12 = 0x%x, r13 = 0x%x, debug_flag = 0x%x\n", + wakesta->timer_out, wakesta->r12, wakesta->r13, + wakesta->debug_flag); + + INFO("raw_sta = 0x%x, idle_sta = 0x%x, event_reg = 0x%x, isr = 0x%x\n", + wakesta->raw_sta, wakesta->idle_sta, wakesta->event_reg, + wakesta->isr); + + INFO("dormant state = %d\n", spm_dormant_sta); + return wr; +} + +void spm_boot_init(void) +{ + /* Only CPU0 is online during boot, initialize cpu online reserve bit */ + mmio_write_32(SPM_PCM_RESERVE, 0xFE); + spm_lock_init(); + spm_register_init(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm.h new file mode 100644 index 0000000..f1e7674 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm.h @@ -0,0 +1,356 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __SPM_H__ +#define __SPM_H__ + +#define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000) +#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010) +#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014) +#define SPM_CLK_SETTLE (SPM_BASE + 0x100) +#define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218) +#define SPM_CA7_CPU2_PWR_CON (SPM_BASE + 0x21c) +#define SPM_CA7_CPU3_PWR_CON (SPM_BASE + 0x220) +#define SPM_CA7_CPU1_L1_PDN (SPM_BASE + 0x264) +#define SPM_CA7_CPU2_L1_PDN (SPM_BASE + 0x26c) +#define SPM_CA7_CPU3_L1_PDN (SPM_BASE + 0x274) +#define SPM_MD32_SRAM_CON (SPM_BASE + 0x2c8) +#define SPM_PCM_CON0 (SPM_BASE + 0x310) +#define SPM_PCM_CON1 (SPM_BASE + 0x314) +#define SPM_PCM_IM_PTR (SPM_BASE + 0x318) +#define SPM_PCM_IM_LEN (SPM_BASE + 0x31c) +#define SPM_PCM_REG_DATA_INI (SPM_BASE + 0x320) +#define SPM_PCM_EVENT_VECTOR0 (SPM_BASE + 0x340) +#define SPM_PCM_EVENT_VECTOR1 (SPM_BASE + 0x344) +#define SPM_PCM_EVENT_VECTOR2 (SPM_BASE + 0x348) +#define SPM_PCM_EVENT_VECTOR3 (SPM_BASE + 0x34c) +#define SPM_PCM_MAS_PAUSE_MASK (SPM_BASE + 0x354) +#define SPM_PCM_PWR_IO_EN (SPM_BASE + 0x358) +#define SPM_PCM_TIMER_VAL (SPM_BASE + 0x35c) +#define SPM_PCM_TIMER_OUT (SPM_BASE + 0x360) +#define SPM_PCM_REG0_DATA (SPM_BASE + 0x380) +#define SPM_PCM_REG1_DATA (SPM_BASE + 0x384) +#define SPM_PCM_REG2_DATA (SPM_BASE + 0x388) +#define SPM_PCM_REG3_DATA (SPM_BASE + 0x38c) +#define SPM_PCM_REG4_DATA (SPM_BASE + 0x390) +#define SPM_PCM_REG5_DATA (SPM_BASE + 0x394) +#define SPM_PCM_REG6_DATA (SPM_BASE + 0x398) +#define SPM_PCM_REG7_DATA (SPM_BASE + 0x39c) +#define SPM_PCM_REG8_DATA (SPM_BASE + 0x3a0) +#define SPM_PCM_REG9_DATA (SPM_BASE + 0x3a4) +#define SPM_PCM_REG10_DATA (SPM_BASE + 0x3a8) +#define SPM_PCM_REG11_DATA (SPM_BASE + 0x3ac) +#define SPM_PCM_REG12_DATA (SPM_BASE + 0x3b0) +#define SPM_PCM_REG13_DATA (SPM_BASE + 0x3b4) +#define SPM_PCM_REG14_DATA (SPM_BASE + 0x3b8) +#define SPM_PCM_REG15_DATA (SPM_BASE + 0x3bc) +#define SPM_PCM_EVENT_REG_STA (SPM_BASE + 0x3c0) +#define SPM_PCM_FSM_STA (SPM_BASE + 0x3c4) +#define SPM_PCM_IM_HOST_RW_PTR (SPM_BASE + 0x3c8) +#define SPM_PCM_IM_HOST_RW_DAT (SPM_BASE + 0x3cc) +#define SPM_PCM_EVENT_VECTOR4 (SPM_BASE + 0x3d0) +#define SPM_PCM_EVENT_VECTOR5 (SPM_BASE + 0x3d4) +#define SPM_PCM_EVENT_VECTOR6 (SPM_BASE + 0x3d8) +#define SPM_PCM_EVENT_VECTOR7 (SPM_BASE + 0x3dc) +#define SPM_PCM_SW_INT_SET (SPM_BASE + 0x3e0) +#define SPM_PCM_SW_INT_CLEAR (SPM_BASE + 0x3e4) +#define SPM_CLK_CON (SPM_BASE + 0x400) +#define SPM_SLEEP_PTPOD2_CON (SPM_BASE + 0x408) +#define SPM_APMCU_PWRCTL (SPM_BASE + 0x600) +#define SPM_AP_DVFS_CON_SET (SPM_BASE + 0x604) +#define SPM_AP_STANBY_CON (SPM_BASE + 0x608) +#define SPM_PWR_STATUS (SPM_BASE + 0x60c) +#define SPM_PWR_STATUS_2ND (SPM_BASE + 0x610) +#define SPM_AP_BSI_REQ (SPM_BASE + 0x614) +#define SPM_SLEEP_TIMER_STA (SPM_BASE + 0x720) +#define SPM_SLEEP_WAKEUP_EVENT_MASK (SPM_BASE + 0x810) +#define SPM_SLEEP_CPU_WAKEUP_EVENT (SPM_BASE + 0x814) +#define SPM_SLEEP_MD32_WAKEUP_EVENT_MASK (SPM_BASE + 0x818) +#define SPM_PCM_WDT_TIMER_VAL (SPM_BASE + 0x824) +#define SPM_PCM_WDT_TIMER_OUT (SPM_BASE + 0x828) +#define SPM_PCM_MD32_MAILBOX (SPM_BASE + 0x830) +#define SPM_PCM_MD32_IRQ (SPM_BASE + 0x834) +#define SPM_SLEEP_ISR_MASK (SPM_BASE + 0x900) +#define SPM_SLEEP_ISR_STATUS (SPM_BASE + 0x904) +#define SPM_SLEEP_ISR_RAW_STA (SPM_BASE + 0x910) +#define SPM_SLEEP_MD32_ISR_RAW_STA (SPM_BASE + 0x914) +#define SPM_SLEEP_WAKEUP_MISC (SPM_BASE + 0x918) +#define SPM_SLEEP_BUS_PROTECT_RDY (SPM_BASE + 0x91c) +#define SPM_SLEEP_SUBSYS_IDLE_STA (SPM_BASE + 0x920) +#define SPM_PCM_RESERVE (SPM_BASE + 0xb00) +#define SPM_PCM_RESERVE2 (SPM_BASE + 0xb04) +#define SPM_PCM_FLAGS (SPM_BASE + 0xb08) +#define SPM_PCM_SRC_REQ (SPM_BASE + 0xb0c) +#define SPM_PCM_DEBUG_CON (SPM_BASE + 0xb20) +#define SPM_CA7_CPU0_IRQ_MASK (SPM_BASE + 0xb30) +#define SPM_CA7_CPU1_IRQ_MASK (SPM_BASE + 0xb34) +#define SPM_CA7_CPU2_IRQ_MASK (SPM_BASE + 0xb38) +#define SPM_CA7_CPU3_IRQ_MASK (SPM_BASE + 0xb3c) +#define SPM_CA15_CPU0_IRQ_MASK (SPM_BASE + 0xb40) +#define SPM_CA15_CPU1_IRQ_MASK (SPM_BASE + 0xb44) +#define SPM_CA15_CPU2_IRQ_MASK (SPM_BASE + 0xb48) +#define SPM_CA15_CPU3_IRQ_MASK (SPM_BASE + 0xb4c) +#define SPM_PCM_PASR_DPD_0 (SPM_BASE + 0xb60) +#define SPM_PCM_PASR_DPD_1 (SPM_BASE + 0xb64) +#define SPM_PCM_PASR_DPD_2 (SPM_BASE + 0xb68) +#define SPM_PCM_PASR_DPD_3 (SPM_BASE + 0xb6c) +#define SPM_SLEEP_CA7_WFI0_EN (SPM_BASE + 0xf00) +#define SPM_SLEEP_CA7_WFI1_EN (SPM_BASE + 0xf04) +#define SPM_SLEEP_CA7_WFI2_EN (SPM_BASE + 0xf08) +#define SPM_SLEEP_CA7_WFI3_EN (SPM_BASE + 0xf0c) +#define SPM_SLEEP_CA15_WFI0_EN (SPM_BASE + 0xf10) +#define SPM_SLEEP_CA15_WFI1_EN (SPM_BASE + 0xf14) +#define SPM_SLEEP_CA15_WFI2_EN (SPM_BASE + 0xf18) +#define SPM_SLEEP_CA15_WFI3_EN (SPM_BASE + 0xf1c) + +#define SPM_PROJECT_CODE 0xb16 + +#define SPM_REGWR_EN (1U << 0) +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +#define SPM_CPU_PDN_DIS (1U << 0) +#define SPM_INFRA_PDN_DIS (1U << 1) +#define SPM_DDRPHY_PDN_DIS (1U << 2) +#define SPM_DUALVCORE_PDN_DIS (1U << 3) +#define SPM_PASR_DIS (1U << 4) +#define SPM_DPD_DIS (1U << 5) +#define SPM_SODI_DIS (1U << 6) +#define SPM_MEMPLL_RESET (1U << 7) +#define SPM_MAINPLL_PDN_DIS (1U << 8) +#define SPM_CPU_DVS_DIS (1U << 9) +#define SPM_CPU_DORMANT (1U << 10) +#define SPM_EXT_VSEL_GPIO103 (1U << 11) +#define SPM_DDR_HIGH_SPEED (1U << 12) +#define SPM_OPT (1U << 13) + +#define POWER_ON_VAL1_DEF 0x01011820 +#define PCM_FSM_STA_DEF 0x48490 +#define PCM_END_FSM_STA_DEF 0x08490 +#define PCM_END_FSM_STA_MASK 0x3fff0 +#define PCM_HANDSHAKE_SEND1 0xbeefbeef + +#define PCM_WDT_TIMEOUT (30 * 32768) +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) + +#define CON0_PCM_KICK (1U << 0) +#define CON0_IM_KICK (1U << 1) +#define CON0_IM_SLEEP_DVS (1U << 3) +#define CON0_PCM_SW_RESET (1U << 15) +#define CON0_CFG_KEY (SPM_PROJECT_CODE << 16) + +#define CON1_IM_SLAVE (1U << 0) +#define CON1_MIF_APBEN (1U << 3) +#define CON1_PCM_TIMER_EN (1U << 5) +#define CON1_IM_NONRP_EN (1U << 6) +#define CON1_PCM_WDT_EN (1U << 8) +#define CON1_PCM_WDT_WAKE_MODE (1U << 9) +#define CON1_SPM_SRAM_SLP_B (1U << 10) +#define CON1_SPM_SRAM_ISO_B (1U << 11) +#define CON1_EVENT_LOCK_EN (1U << 12) +#define CON1_CFG_KEY (SPM_PROJECT_CODE << 16) + +#define PCM_PWRIO_EN_R0 (1U << 0) +#define PCM_PWRIO_EN_R7 (1U << 7) +#define PCM_RF_SYNC_R0 (1U << 16) +#define PCM_RF_SYNC_R2 (1U << 18) +#define PCM_RF_SYNC_R6 (1U << 22) +#define PCM_RF_SYNC_R7 (1U << 23) + +#define CC_SYSCLK0_EN_0 (1U << 0) +#define CC_SYSCLK0_EN_1 (1U << 1) +#define CC_SYSCLK1_EN_0 (1U << 2) +#define CC_SYSCLK1_EN_1 (1U << 3) +#define CC_SYSSETTLE_SEL (1U << 4) +#define CC_LOCK_INFRA_DCM (1U << 5) +#define CC_SRCLKENA_MASK_0 (1U << 6) +#define CC_CXO32K_RM_EN_MD1 (1U << 9) +#define CC_CXO32K_RM_EN_MD2 (1U << 10) +#define CC_CLKSQ1_SEL (1U << 12) +#define CC_DISABLE_DORM_PWR (1U << 14) +#define CC_MD32_DCM_EN (1U << 18) + +#define WFI_OP_AND 1 +#define WFI_OP_OR 0 + +#define WAKE_MISC_PCM_TIMER (1U << 19) +#define WAKE_MISC_CPU_WAKE (1U << 20) + +/* define WAKE_SRC_XXX */ +#define WAKE_SRC_SPM_MERGE (1 << 0) +#define WAKE_SRC_KP (1 << 2) +#define WAKE_SRC_WDT (1 << 3) +#define WAKE_SRC_GPT (1 << 4) +#define WAKE_SRC_EINT (1 << 6) +#define WAKE_SRC_LOW_BAT (1 << 9) +#define WAKE_SRC_MD32 (1 << 10) +#define WAKE_SRC_USB_CD (1 << 14) +#define WAKE_SRC_USB_PDN (1 << 15) +#define WAKE_SRC_AFE (1 << 20) +#define WAKE_SRC_THERM (1 << 21) +#define WAKE_SRC_SYSPWREQ (1 << 24) +#define WAKE_SRC_SEJ (1 << 27) +#define WAKE_SRC_ALL_MD32 (1 << 28) +#define WAKE_SRC_CPU_IRQ (1 << 29) + +enum wake_reason_t { + WR_NONE = 0, + WR_UART_BUSY = 1, + WR_PCM_ASSERT = 2, + WR_PCM_TIMER = 3, + WR_PCM_ABORT = 4, + WR_WAKE_SRC = 5, + WR_UNKNOWN = 6, +}; + +struct pwr_ctrl { + unsigned int pcm_flags; + unsigned int pcm_flags_cust; + unsigned int pcm_reserve; + unsigned int timer_val; + unsigned int timer_val_cust; + unsigned int wake_src; + unsigned int wake_src_cust; + unsigned int wake_src_md32; + unsigned short r0_ctrl_en; + unsigned short r7_ctrl_en; + unsigned short infra_dcm_lock; + unsigned short pcm_apsrc_req; + unsigned short mcusys_idle_mask; + unsigned short ca15top_idle_mask; + unsigned short ca7top_idle_mask; + unsigned short wfi_op; + unsigned short ca15_wfi0_en; + unsigned short ca15_wfi1_en; + unsigned short ca15_wfi2_en; + unsigned short ca15_wfi3_en; + unsigned short ca7_wfi0_en; + unsigned short ca7_wfi1_en; + unsigned short ca7_wfi2_en; + unsigned short ca7_wfi3_en; + unsigned short disp_req_mask; + unsigned short mfg_req_mask; + unsigned short md32_req_mask; + unsigned short syspwreq_mask; + unsigned short srclkenai_mask; +}; + +struct wake_status { + unsigned int assert_pc; + unsigned int r12; + unsigned int raw_sta; + unsigned int wake_misc; + unsigned int timer_out; + unsigned int r13; + unsigned int idle_sta; + unsigned int debug_flag; + unsigned int event_reg; + unsigned int isr; +}; + +struct pcm_desc { + const char *version; /* PCM code version */ + const unsigned int *base; /* binary array base */ + const unsigned int size; /* binary array size */ + const unsigned char sess; /* session number */ + const unsigned char replace; /* replace mode */ + + unsigned int vec0; /* event vector 0 config */ + unsigned int vec1; /* event vector 1 config */ + unsigned int vec2; /* event vector 2 config */ + unsigned int vec3; /* event vector 3 config */ + unsigned int vec4; /* event vector 4 config */ + unsigned int vec5; /* event vector 5 config */ + unsigned int vec6; /* event vector 6 config */ + unsigned int vec7; /* event vector 7 config */ +}; + +struct spm_lp_scen { + const struct pcm_desc *pcmdesc; + struct pwr_ctrl *pwrctrl; +}; + +#define EVENT_VEC(event, resume, imme, pc) \ + (((pc) << 16) | \ + (!!(imme) << 6) | \ + (!!(resume) << 5) | \ + ((event) & 0x1f)) + +#define spm_read(addr) mmio_read_32(addr) +#define spm_write(addr, val) mmio_write_32(addr, val) + +#define is_cpu_pdn(flags) (!((flags) & SPM_CPU_PDN_DIS)) +#define is_infra_pdn(flags) (!((flags) & SPM_INFRA_PDN_DIS)) +#define is_ddrphy_pdn(flags) (!((flags) & SPM_DDRPHY_PDN_DIS)) + +static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl, + unsigned int flags) +{ + flags &= ~SPM_EXT_VSEL_GPIO103; + + if (pwrctrl->pcm_flags_cust == 0) + pwrctrl->pcm_flags = flags; + else + pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust; +} + +static inline void set_pwrctrl_pcm_data(struct pwr_ctrl *pwrctrl, + unsigned int data) +{ + pwrctrl->pcm_reserve = data; +} + +void spm_reset_and_init_pcm(void); + +void spm_init_pcm_register(void); /* init r0 and r7 */ +void spm_set_power_control(const struct pwr_ctrl *pwrctrl); +void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); + +void spm_get_wakeup_status(struct wake_status *wakesta); +void spm_set_sysclk_settle(void); +void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl); +void spm_clean_after_wakeup(void); +enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta); +void spm_register_init(void); +void spm_go_to_hotplug(void); +void spm_init_event_vector(const struct pcm_desc *pcmdesc); +void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc); +void spm_set_sysclk_settle(void); +int is_mcdi_ready(void); +int is_hotplug_ready(void); +int is_suspend_ready(void); +void set_mcdi_ready(void); +void set_hotplug_ready(void); +void set_suspend_ready(void); +void clear_all_ready(void); +void spm_lock_init(void); +void spm_lock_get(void); +void spm_lock_release(void); +void spm_boot_init(void); + +#endif /* __SPM_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c new file mode 100644 index 0000000..fccd5a2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include + +/* + * System Power Manager (SPM) is a hardware module, which controls cpu or + * system power for different power scenarios using different firmware. + * This driver controls the cpu power in cpu hotplug flow. + */ + +#define PCM_HOTPLUG_VALID_MASK 0x00ff0000 +#define PCM_HOTPLUG_VALID_SHIFT 0x8 + +/********************************************************** + * PCM sequence for CPU hotplug + **********************************************************/ +static const unsigned int hotplug_binary[] = { + 0x1900001f, 0x1020020c, 0x1950001f, 0x1020020c, 0xa9400005, 0x00000001, + 0xe1000005, 0x1910001f, 0x10006720, 0x814c9001, 0xd82000e5, 0x17c07c1f, + 0x1900001f, 0x10001220, 0x1950001f, 0x10001220, 0xa15f0405, 0xe1000005, + 0x1900001f, 0x10001228, 0x1950001f, 0x10001228, 0x810f1401, 0xd8200244, + 0x17c07c1f, 0xe2e0006d, 0xe2e0002d, 0x1a00001f, 0x100062b8, 0x1910001f, + 0x100062b8, 0xa9000004, 0x00000001, 0xe2000004, 0x1910001f, 0x100062b8, + 0x81142804, 0xd8200444, 0x17c07c1f, 0xe2e0002c, 0xe2e0003c, 0xe2e0003e, + 0xe2e0003a, 0xe2e00032, 0x1910001f, 0x1000660c, 0x81079001, 0x1950001f, + 0x10006610, 0x81479401, 0xa1001404, 0xd8000584, 0x17c07c1f, 0x1900001f, + 0x10006404, 0x1950001f, 0x10006404, 0xa1568405, 0xe1000005, 0xf0000000, + 0x17c07c1f, 0x1900001f, 0x10006404, 0x1950001f, 0x10006404, 0x89400005, + 0x0000dfff, 0xe1000005, 0xe2e00036, 0xe2e0003e, 0x1910001f, 0x1000660c, + 0x81079001, 0x1950001f, 0x10006610, 0x81479401, 0x81001404, 0xd82008c4, + 0x17c07c1f, 0xe2e0002e, 0x1a00001f, 0x100062b8, 0x1910001f, 0x100062b8, + 0x89000004, 0x0000fffe, 0xe2000004, 0x1910001f, 0x100062b8, 0x81142804, + 0xd8000ae4, 0x17c07c1f, 0xe2e0006e, 0xe2e0004e, 0xe2e0004c, 0xe2e0004d, + 0x1900001f, 0x10001220, 0x1950001f, 0x10001220, 0x89400005, 0xbfffffff, + 0xe1000005, 0x1900001f, 0x10001228, 0x1950001f, 0x10001228, 0x810f1401, + 0xd8000ce4, 0x17c07c1f, 0x1900001f, 0x1020020c, 0x1950001f, 0x1020020c, + 0x89400005, 0xfffffffe, 0xe1000005, 0xf0000000, 0x17c07c1f, 0x1212841f, + 0xe2e00036, 0xe2e0003e, 0x1380201f, 0xe2e0003c, 0xe2a00000, 0x1b80001f, + 0x20000080, 0xe2e0007c, 0x1b80001f, 0x20000003, 0xe2e0005c, 0xe2e0004c, + 0xe2e0004d, 0xf0000000, 0x17c07c1f, 0xe2e0004f, 0xe2e0006f, 0xe2e0002f, + 0xe2a00001, 0x1b80001f, 0x20000080, 0xe2e0002e, 0xe2e0003e, 0xe2e00032, + 0xf0000000, 0x17c07c1f, 0x1212841f, 0xe2e00026, 0xe2e0002e, 0x1380201f, + 0x1a00001f, 0x100062b4, 0x1910001f, 0x100062b4, 0x81322804, 0xe2000004, + 0x81202804, 0xe2000004, 0x1b80001f, 0x20000034, 0x1910001f, 0x100062b4, + 0x81142804, 0xd8001404, 0x17c07c1f, 0xe2e0000e, 0xe2e0000c, 0xe2e0000d, + 0xf0000000, 0x17c07c1f, 0xe2e0002d, 0x1a00001f, 0x100062b4, 0x1910001f, + 0x100062b4, 0xa1002804, 0xe2000004, 0xa1122804, 0xe2000004, 0x1b80001f, + 0x20000080, 0x1910001f, 0x100062b4, 0x81142804, 0xd82016a4, 0x17c07c1f, + 0xe2e0002f, 0xe2e0002b, 0xe2e00023, 0x1380201f, 0xe2e00022, 0xf0000000, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x1840001f, 0x00000001, 0x1840001f, 0x00000001, + 0x1840001f, 0x00000001, 0xa1d48407, 0x1b00001f, 0x2f7be75f, 0xe8208000, + 0x10006354, 0xfffe7b47, 0xa1d10407, 0x1b80001f, 0x20000020, 0x17c07c1f, + 0x1910001f, 0x10006b00, 0x81461001, 0xb14690a1, 0xd82044e5, 0x17c07c1f, + 0x1910001f, 0x10006610, 0x81079001, 0xd80044e4, 0x17c07c1f, 0x1990001f, + 0x10006b00, 0x81421801, 0x82429801, 0x81402405, 0xd80044e5, 0x17c07c1f, + 0x1a40001f, 0x100062b0, 0x1280041f, 0xc24007a0, 0x17c07c1f, 0x1910001f, + 0x10006b00, 0x81449001, 0xd8204be5, 0x17c07c1f, 0x1910001f, 0x10006b00, + 0x81009001, 0xd8204984, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81051001, + 0xd8204be4, 0x17c07c1f, 0x1910001f, 0x10006720, 0x81489001, 0xd82046c5, + 0x17c07c1f, 0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, 0xc24010e0, + 0x17c07c1f, 0x1910001f, 0x1000660c, 0x81051001, 0x1950001f, 0x10006610, + 0x81451401, 0xa1001404, 0xd8004824, 0x17c07c1f, 0xd0004b00, 0x17c07c1f, + 0x17c07c1f, 0x1910001f, 0x10006610, 0x81051001, 0xd8004be4, 0x17c07c1f, + 0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, 0xc2400ee0, 0x17c07c1f, + 0x1910001f, 0x10006b00, 0x89000004, 0xfffffdff, 0x1940001f, 0x10006b00, + 0xe1400004, 0x17c07c1f, 0x1910001f, 0x10006b00, 0x81451001, 0xd8205305, + 0x17c07c1f, 0x1910001f, 0x10006b00, 0x81011001, 0xd82050a4, 0x17c07c1f, + 0x1910001f, 0x10006610, 0x81059001, 0xd8205304, 0x17c07c1f, 0x1910001f, + 0x10006720, 0x81491001, 0xd8204de5, 0x17c07c1f, 0x1a40001f, 0x1000621c, + 0x1a80001f, 0x1000626c, 0xc24010e0, 0x17c07c1f, 0x1910001f, 0x1000660c, + 0x81059001, 0x1950001f, 0x10006610, 0x81459401, 0xa1001404, 0xd8004f44, + 0x17c07c1f, 0xd0005220, 0x17c07c1f, 0x17c07c1f, 0x1910001f, 0x10006610, + 0x81059001, 0xd8005304, 0x17c07c1f, 0x1a40001f, 0x1000621c, 0x1a80001f, + 0x1000626c, 0xc2400ee0, 0x17c07c1f, 0x1910001f, 0x10006b00, 0x89000004, + 0xfffffbff, 0x1940001f, 0x10006b00, 0xe1400004, 0x17c07c1f, 0x1910001f, + 0x10006b00, 0x81459001, 0xd8205a25, 0x17c07c1f, 0x1910001f, 0x10006b00, + 0x81019001, 0xd82057c4, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81061001, + 0xd8205a24, 0x17c07c1f, 0x1910001f, 0x10006720, 0x81499001, 0xd8205505, + 0x17c07c1f, 0x1a40001f, 0x10006220, 0x1a80001f, 0x10006274, 0xc24010e0, + 0x17c07c1f, 0x1910001f, 0x1000660c, 0x81061001, 0x1950001f, 0x10006610, + 0x81461401, 0xa1001404, 0xd8005664, 0x17c07c1f, 0xd0005940, 0x17c07c1f, + 0x17c07c1f, 0x1910001f, 0x10006610, 0x81061001, 0xd8005a24, 0x17c07c1f, + 0x1a40001f, 0x10006220, 0x1a80001f, 0x10006274, 0xc2400ee0, 0x17c07c1f, + 0x1910001f, 0x10006b00, 0x89000004, 0xfffff7ff, 0x1940001f, 0x10006b00, + 0xe1400004, 0x17c07c1f, 0x1910001f, 0x10006b00, 0x81461001, 0xd8206185, + 0x17c07c1f, 0x1910001f, 0x10006b00, 0x81021001, 0xd8205ec4, 0x17c07c1f, + 0x1910001f, 0x10006610, 0x81081001, 0xd8206184, 0x17c07c1f, 0x1910001f, + 0x10006720, 0x814a1001, 0xd8205c25, 0x17c07c1f, 0x1a40001f, 0x100062a0, + 0x1280041f, 0xc2401540, 0x17c07c1f, 0x1910001f, 0x1000660c, 0x81081001, + 0x1950001f, 0x10006610, 0x81481401, 0xa1001404, 0xd8005d64, 0x17c07c1f, + 0xd00060a0, 0x17c07c1f, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81479001, + 0x81881001, 0x69a00006, 0x00000000, 0x81401805, 0xd8206185, 0x17c07c1f, + 0x1a40001f, 0x100062a0, 0x1280041f, 0xc2401240, 0x17c07c1f, 0x1910001f, + 0x10006b00, 0x89000004, 0xffffefff, 0x1940001f, 0x10006b00, 0xe1400004, + 0x17c07c1f, 0x1910001f, 0x10006b00, 0x81469001, 0xd82068e5, 0x17c07c1f, + 0x1910001f, 0x10006b00, 0x81029001, 0xd8206624, 0x17c07c1f, 0x1910001f, + 0x10006610, 0x81089001, 0xd82068e4, 0x17c07c1f, 0x1910001f, 0x10006720, + 0x814a9001, 0xd8206385, 0x17c07c1f, 0x1a40001f, 0x100062a4, 0x1290841f, + 0xc2401540, 0x17c07c1f, 0x1910001f, 0x1000660c, 0x81089001, 0x1950001f, + 0x10006610, 0x81489401, 0xa1001404, 0xd80064c4, 0x17c07c1f, 0xd0006800, + 0x17c07c1f, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81479001, 0x81889001, + 0x69a00006, 0x00000000, 0x81401805, 0xd82068e5, 0x17c07c1f, 0x1a40001f, + 0x100062a4, 0x1290841f, 0xc2401240, 0x17c07c1f, 0x1910001f, 0x10006b00, + 0x89000004, 0xffffdfff, 0x1940001f, 0x10006b00, 0xe1400004, 0x1910001f, + 0x10006610, 0x81479001, 0x81881001, 0x69600005, 0x00000000, 0xa1401805, + 0x81889001, 0xa1401805, 0xd8006bc5, 0x17c07c1f, 0x1910001f, 0x10006b00, + 0x81421001, 0x82429001, 0x82802405, 0xd8206bca, 0x17c07c1f, 0x1a40001f, + 0x100062b0, 0x1280041f, 0xc2400000, 0x17c07c1f, 0x1990001f, 0x10006b00, + 0x89800006, 0x00003f00, 0x69200006, 0x00000000, 0xd82041e4, 0x17c07c1f, + 0x1990001f, 0x10006320, 0x69200006, 0xbeefbeef, 0xd8006dc4, 0x17c07c1f, + 0xd00041e0, 0x17c07c1f, 0x1910001f, 0x10006358, 0x810b1001, 0xd8006dc4, + 0x17c07c1f, 0x1980001f, 0xdeaddead, 0x19c0001f, 0x01411820, 0xf0000000 +}; +static const struct pcm_desc hotplug_pcm = { + .version = "pcm_power_down_mt8173_V37", + .base = hotplug_binary, + .size = 888, + .sess = 2, + .replace = 0, +}; + +static struct pwr_ctrl hotplug_ctrl = { + .wake_src = 0, + .wake_src_md32 = 0, + .wfi_op = WFI_OP_OR, + .mcusys_idle_mask = 1, + .ca7top_idle_mask = 1, + .ca15top_idle_mask = 1, + .disp_req_mask = 1, + .mfg_req_mask = 1, + .md32_req_mask = 1, + .syspwreq_mask = 1, + .pcm_flags = 0, +}; + +static const struct spm_lp_scen spm_hotplug = { + .pcmdesc = &hotplug_pcm, + .pwrctrl = &hotplug_ctrl, +}; + +void spm_go_to_hotplug(void) +{ + const struct pcm_desc *pcmdesc = spm_hotplug.pcmdesc; + struct pwr_ctrl *pwrctrl = spm_hotplug.pwrctrl; + + set_pwrctrl_pcm_flags(pwrctrl, 0); + spm_reset_and_init_pcm(); + spm_kick_im_to_fetch(pcmdesc); + spm_set_power_control(pwrctrl); + spm_set_wakeup_event(pwrctrl); + spm_kick_pcm_to_run(pwrctrl); +} + +void spm_clear_hotplug(void) +{ + /* Inform SPM that CPU wants to program CPU_WAKEUP_EVENT and + * DISABLE_CPU_DROM */ + + mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_HANDSHAKE_SEND1); + mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); + + /* Wait SPM's response, can't use sleep api */ + while ((mmio_read_32(SPM_PCM_FSM_STA) & PCM_END_FSM_STA_MASK) + != PCM_END_FSM_STA_DEF) + ; + + /* no hotplug pcm running */ + clear_all_ready(); +} + +void spm_hotplug_on(unsigned long mpidr) +{ + unsigned long linear_id; + + linear_id = platform_get_core_pos(mpidr); + spm_lock_get(); + if (is_hotplug_ready() == 0) { + spm_mcdi_wakeup_all_cores(); + mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK); + spm_go_to_hotplug(); + set_hotplug_ready(); + } + /* turn on CPUx */ + mmio_clrsetbits_32(SPM_PCM_RESERVE, + PCM_HOTPLUG_VALID_MASK | (1 << linear_id), + 1 << (linear_id + PCM_HOTPLUG_VALID_SHIFT)); + spm_lock_release(); +} + +void spm_hotplug_off(unsigned long mpidr) +{ + unsigned long linear_id; + + linear_id = platform_get_core_pos(mpidr); + spm_lock_get(); + if (is_hotplug_ready() == 0) { + spm_mcdi_wakeup_all_cores(); + mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK); + spm_go_to_hotplug(); + set_hotplug_ready(); + } + mmio_clrsetbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK, + (1 << linear_id) | + (1 << (linear_id + PCM_HOTPLUG_VALID_SHIFT))); + spm_lock_release(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_hotplug.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_hotplug.h new file mode 100644 index 0000000..fa90ab9 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_hotplug.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __SPM_HOTPLUG_H__ +#define __SPM_HOTPLUG_H__ + +void spm_clear_hotplug(void); +void spm_hotplug_off(unsigned long mpidr); +void spm_hotplug_on(unsigned long mpidr); + +#endif /* __SPM_HOTPLUG_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c new file mode 100644 index 0000000..11f4a4a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c @@ -0,0 +1,435 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * System Power Manager (SPM) is a hardware module, which controls cpu or + * system power for different power scenarios using different firmware. + * This driver controls the cpu power in cpu idle power saving state. + */ + +#define WAKE_SRC_FOR_MCDI (WAKE_SRC_SYSPWREQ | WAKE_SRC_CPU_IRQ) +#define PCM_MCDI_HANDSHAKE_SYNC 0xbeefbeef +#define PCM_MCDI_HANDSHAKE_ACK 0xdeaddead +#define PCM_MCDI_UPDATE_INFORM 0xabcdabcd +#define PCM_MCDI_CKECK_DONE 0x12345678 +#define PCM_MCDI_ALL_CORE_AWAKE 0x0 +#define PCM_MCDI_OFFLOADED 0xaa55aa55 + +static const unsigned int mcdi_binary[] = { + 0x1212841f, 0xe2e00036, 0xe2e0003e, 0x1380201f, 0xe2e0003c, 0xe2a00000, + 0x1b80001f, 0x20000080, 0xe2e0007c, 0x1b80001f, 0x20000003, 0xe2e0005c, + 0xe2e0004c, 0xe2e0004d, 0xf0000000, 0x17c07c1f, 0xe2e0004f, 0xe2e0006f, + 0xe2e0002f, 0xe2a00001, 0x1b80001f, 0x20000080, 0xe2e0002e, 0xe2e0003e, + 0xe2e00032, 0xf0000000, 0x17c07c1f, 0x1212841f, 0xe2e00026, 0xe2e0002e, + 0x1380201f, 0x1a00001f, 0x100062b4, 0x1910001f, 0x100062b4, 0x81322804, + 0xe2000004, 0x81202804, 0xe2000004, 0x1b80001f, 0x20000034, 0x1910001f, + 0x100062b4, 0x81142804, 0xd8000524, 0x17c07c1f, 0xe2e0000e, 0xe2e0000c, + 0xe2e0000d, 0xf0000000, 0x17c07c1f, 0xe2e0002d, 0x1a00001f, 0x100062b4, + 0x1910001f, 0x100062b4, 0xa1002804, 0xe2000004, 0xa1122804, 0xe2000004, + 0x1b80001f, 0x20000080, 0x1910001f, 0x100062b4, 0x81142804, 0xd82007c4, + 0x17c07c1f, 0xe2e0002f, 0xe2e0002b, 0xe2e00023, 0x1380201f, 0xe2e00022, + 0xf0000000, 0x17c07c1f, 0x18c0001f, 0x10006b6c, 0x1910001f, 0x10006b6c, + 0xa1002804, 0xe0c00004, 0xf0000000, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x1840001f, 0x00000001, 0x11407c1f, 0xe8208000, + 0x10006b6c, 0xa0000000, 0xe8208000, 0x10006310, 0x0b160008, 0x1900001f, + 0x000f7bde, 0x1a00001f, 0x10200268, 0xe2000004, 0xe8208000, 0x10006600, + 0x00000000, 0xc2800940, 0x1280041f, 0x1b00001f, 0x21000001, 0x1b80001f, + 0xd0010000, 0xc2800940, 0x1290841f, 0x69200006, 0xbeefbeef, 0xd8204764, + 0x17c07c1f, 0xc2800940, 0x1291041f, 0x1910001f, 0x10006358, 0x810b1001, + 0xd80043e4, 0x17c07c1f, 0x1980001f, 0xdeaddead, 0x69200006, 0xabcdabcd, + 0xd82044c4, 0x17c07c1f, 0xc2800940, 0x1291841f, 0x88900001, 0x10006814, + 0x1910001f, 0x10006400, 0x81271002, 0x1880001f, 0x10006600, 0xe0800004, + 0x1910001f, 0x10006358, 0x810b1001, 0xd8004684, 0x17c07c1f, 0x1980001f, + 0x12345678, 0x60a07c05, 0x89100002, 0x10006600, 0x80801001, 0xd8007142, + 0x17c07c1f, 0xc2800940, 0x1292041f, 0x1a10001f, 0x10006720, 0x82002001, + 0x82201408, 0xd8204a08, 0x17c07c1f, 0x1a40001f, 0x10006200, 0x1a80001f, + 0x1000625c, 0xc2400200, 0x17c07c1f, 0xa1400405, 0xc2800940, 0x1292841f, + 0x1a10001f, 0x10006720, 0x8200a001, 0x82209408, 0xd8204be8, 0x17c07c1f, + 0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, 0xc2400200, 0x17c07c1f, + 0xa1508405, 0xc2800940, 0x1293041f, 0x1a10001f, 0x10006720, 0x82012001, + 0x82211408, 0xd8204dc8, 0x17c07c1f, 0x1a40001f, 0x1000621c, 0x1a80001f, + 0x1000626c, 0xc2400200, 0x17c07c1f, 0xa1510405, 0x1a10001f, 0x10006720, + 0x8201a001, 0x82219408, 0xd8204f68, 0x17c07c1f, 0x1a40001f, 0x10006220, + 0x1a80001f, 0x10006274, 0xc2400200, 0x17c07c1f, 0xa1518405, 0x1a10001f, + 0x10006720, 0x82022001, 0x82221408, 0xd82050e8, 0x17c07c1f, 0x1a40001f, + 0x100062a0, 0x1280041f, 0xc2400660, 0x17c07c1f, 0xa1520405, 0x1a10001f, + 0x10006720, 0x8202a001, 0x82229408, 0xd8205268, 0x17c07c1f, 0x1a40001f, + 0x100062a4, 0x1290841f, 0xc2400660, 0x17c07c1f, 0xa1528405, 0x1a10001f, + 0x10006720, 0x82032001, 0x82231408, 0xd82053e8, 0x17c07c1f, 0x1a40001f, + 0x100062a8, 0x1291041f, 0xc2400660, 0x17c07c1f, 0xa1530405, 0x1a10001f, + 0x10006720, 0x8203a001, 0x82239408, 0xd8205568, 0x17c07c1f, 0x1a40001f, + 0x100062ac, 0x1291841f, 0xc2400660, 0x17c07c1f, 0xa1538405, 0x1b80001f, + 0x20000208, 0xd82070cc, 0x17c07c1f, 0x81001401, 0xd8205964, 0x17c07c1f, + 0x1a10001f, 0x10006918, 0x81002001, 0xb1042081, 0xb1003081, 0xb10c3081, + 0xd8205964, 0x17c07c1f, 0x1a40001f, 0x10006200, 0x1a80001f, 0x1000625c, + 0xc2400000, 0x17c07c1f, 0x89400005, 0xfffffffe, 0xe8208000, 0x10006f00, + 0x00000000, 0xe8208000, 0x10006b30, 0x00000000, 0xe8208000, 0x100063e0, + 0x00000001, 0x81009401, 0xd8205cc4, 0x17c07c1f, 0x1a10001f, 0x10006918, + 0x8100a001, 0xb104a081, 0xb1003081, 0xd8205cc4, 0x17c07c1f, 0x1a40001f, + 0x10006218, 0x1a80001f, 0x10006264, 0xc2400000, 0x17c07c1f, 0x89400005, + 0xfffffffd, 0xe8208000, 0x10006f04, 0x00000000, 0xe8208000, 0x10006b34, + 0x00000000, 0xe8208000, 0x100063e0, 0x00000002, 0x81011401, 0xd8206024, + 0x17c07c1f, 0x1a10001f, 0x10006918, 0x81012001, 0xb1052081, 0xb1003081, + 0xd8206024, 0x17c07c1f, 0x1a40001f, 0x1000621c, 0x1a80001f, 0x1000626c, + 0xc2400000, 0x17c07c1f, 0x89400005, 0xfffffffb, 0xe8208000, 0x10006f08, + 0x00000000, 0xe8208000, 0x10006b38, 0x00000000, 0xe8208000, 0x100063e0, + 0x00000004, 0x81019401, 0xd8206384, 0x17c07c1f, 0x1a10001f, 0x10006918, + 0x8101a001, 0xb105a081, 0xb1003081, 0xd8206384, 0x17c07c1f, 0x1a40001f, + 0x10006220, 0x1a80001f, 0x10006274, 0xc2400000, 0x17c07c1f, 0x89400005, + 0xfffffff7, 0xe8208000, 0x10006f0c, 0x00000000, 0xe8208000, 0x10006b3c, + 0x00000000, 0xe8208000, 0x100063e0, 0x00000008, 0x81021401, 0xd82066c4, + 0x17c07c1f, 0x1a10001f, 0x10006918, 0x81022001, 0xb1062081, 0xb1003081, + 0xd82066c4, 0x17c07c1f, 0x1a40001f, 0x100062a0, 0x1280041f, 0xc2400360, + 0x17c07c1f, 0x89400005, 0xffffffef, 0xe8208000, 0x10006f10, 0x00000000, + 0xe8208000, 0x10006b40, 0x00000000, 0xe8208000, 0x100063e0, 0x00000010, + 0x81029401, 0xd8206a04, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8102a001, + 0xb106a081, 0xb1003081, 0xd8206a04, 0x17c07c1f, 0x1a40001f, 0x100062a4, + 0x1290841f, 0xc2400360, 0x17c07c1f, 0x89400005, 0xffffffdf, 0xe8208000, + 0x10006f14, 0x00000000, 0xe8208000, 0x10006b44, 0x00000000, 0xe8208000, + 0x100063e0, 0x00000020, 0x81031401, 0xd8206d44, 0x17c07c1f, 0x1a10001f, + 0x10006918, 0x81032001, 0xb1072081, 0xb1003081, 0xd8206d44, 0x17c07c1f, + 0x1a40001f, 0x100062a8, 0x1291041f, 0xc2400360, 0x17c07c1f, 0x89400005, + 0xffffffbf, 0xe8208000, 0x10006f18, 0x00000000, 0xe8208000, 0x10006b48, + 0x00000000, 0xe8208000, 0x100063e0, 0x00000040, 0x81039401, 0xd8207084, + 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8103a001, 0xb107a081, 0xb1003081, + 0xd8207084, 0x17c07c1f, 0x1a40001f, 0x100062ac, 0x1291841f, 0xc2400360, + 0x17c07c1f, 0x89400005, 0xffffff7f, 0xe8208000, 0x10006f1c, 0x00000000, + 0xe8208000, 0x10006b4c, 0x00000000, 0xe8208000, 0x100063e0, 0x00000080, + 0xc2800940, 0x1293841f, 0xd0004260, 0x17c07c1f, 0xc2800940, 0x1294041f, + 0xe8208000, 0x10006600, 0x00000000, 0x1ac0001f, 0x55aa55aa, 0x1940001f, + 0xaa55aa55, 0xc2800940, 0x1294841f, 0x1b80001f, 0x00001000, 0xf0000000, + 0x17c07c1f +}; + +static const struct pcm_desc mcdi_pcm = { + .version = "pcm_mcdi_v0.5_20140721_mt8173_v03.04_20150507", + .base = mcdi_binary, + .size = 919, + .sess = 2, + .replace = 0, +}; + +static struct pwr_ctrl mcdi_ctrl = { + .wake_src = WAKE_SRC_FOR_MCDI, + .wake_src_md32 = 0, + .wfi_op = WFI_OP_OR, + .mcusys_idle_mask = 1, + .ca7top_idle_mask = 1, + .ca15top_idle_mask = 1, + .disp_req_mask = 1, + .mfg_req_mask = 1, + .md32_req_mask = 1, +}; + +static const struct spm_lp_scen spm_mcdi = { + .pcmdesc = &mcdi_pcm, + .pwrctrl = &mcdi_ctrl, +}; + +void spm_mcdi_cpu_wake_up_event(int wake_up_event, int disable_dormant_power) +{ + if (((mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT) & 0x1) == 1) + && ((mmio_read_32(SPM_CLK_CON) & CC_DISABLE_DORM_PWR) == 0)) { + /* MCDI is offload? */ + INFO("%s: SPM_SLEEP_CPU_WAKEUP_EVENT:%x, SPM_CLK_CON %x", + __func__, mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT), + mmio_read_32(SPM_CLK_CON)); + return; + } + /* Inform SPM that CPU wants to program CPU_WAKEUP_EVENT and + * DISABLE_CPU_DROM */ + mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_HANDSHAKE_SYNC); + mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); + + /* Wait SPM's response, can't use sleep api */ + while (mmio_read_32(SPM_PCM_REG6_DATA) != PCM_MCDI_HANDSHAKE_ACK) + ; + + if (disable_dormant_power) { + mmio_setbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR); + while (mmio_read_32(SPM_CLK_CON) != + (mmio_read_32(SPM_CLK_CON) | CC_DISABLE_DORM_PWR)) + ; + + } else { + mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR); + while (mmio_read_32(SPM_CLK_CON) != + (mmio_read_32(SPM_CLK_CON) & ~CC_DISABLE_DORM_PWR)) + ; + } + + mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, wake_up_event); + + while (mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT) != wake_up_event) + ; + + /* Inform SPM to see updated setting */ + mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_UPDATE_INFORM); + mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); + + while (mmio_read_32(SPM_PCM_REG6_DATA) != PCM_MCDI_CKECK_DONE) + ; + /* END OF sequence */ + + mmio_write_32(SPM_PCM_REG_DATA_INI, 0x0); + mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); +} + +void spm_mcdi_wakeup_all_cores(void) +{ + if (is_mcdi_ready() == 0) + return; + + spm_mcdi_cpu_wake_up_event(1, 1); + while (mmio_read_32(SPM_PCM_REG5_DATA) != PCM_MCDI_ALL_CORE_AWAKE) + ; + spm_mcdi_cpu_wake_up_event(1, 0); + while (mmio_read_32(SPM_PCM_REG5_DATA) != PCM_MCDI_OFFLOADED) + ; + + spm_clean_after_wakeup(); + clear_all_ready(); +} + +void spm_mcdi_wfi_sel_enter(unsigned long mpidr) +{ + int core_id_val = mpidr & MPIDR_CPU_MASK; + int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; + + /* SPM WFI Select by core number */ + if (cluster_id) { + switch (core_id_val) { + case 0: + mmio_write_32(SPM_CA15_CPU0_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, 1); + break; + case 1: + mmio_write_32(SPM_CA15_CPU1_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, 1); + break; + case 2: + mmio_write_32(SPM_CA15_CPU2_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, 1); + break; + case 3: + mmio_write_32(SPM_CA15_CPU3_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, 1); + break; + default: + break; + } + } else { + switch (core_id_val) { + case 0: + mmio_write_32(SPM_CA7_CPU0_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, 1); + break; + case 1: + mmio_write_32(SPM_CA7_CPU1_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, 1); + break; + case 2: + mmio_write_32(SPM_CA7_CPU2_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, 1); + break; + case 3: + mmio_write_32(SPM_CA7_CPU3_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, 1); + break; + default: + break; + } + } +} + +void spm_mcdi_wfi_sel_leave(unsigned long mpidr) +{ + int core_id_val = mpidr & MPIDR_CPU_MASK; + int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; + + /* SPM WFI Select by core number */ + if (cluster_id) { + switch (core_id_val) { + case 0: + mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, 0); + mmio_write_32(SPM_CA15_CPU0_IRQ_MASK, 0); + break; + case 1: + mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, 0); + mmio_write_32(SPM_CA15_CPU1_IRQ_MASK, 0); + break; + case 2: + mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, 0); + mmio_write_32(SPM_CA15_CPU2_IRQ_MASK, 0); + break; + case 3: + mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, 0); + mmio_write_32(SPM_CA15_CPU3_IRQ_MASK, 0); + break; + default: + break; + } + } else { + switch (core_id_val) { + case 0: + mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, 0); + mmio_write_32(SPM_CA7_CPU0_IRQ_MASK, 0); + break; + case 1: + mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, 0); + mmio_write_32(SPM_CA7_CPU1_IRQ_MASK, 0); + break; + case 2: + mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, 0); + mmio_write_32(SPM_CA7_CPU2_IRQ_MASK, 0); + break; + case 3: + mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, 0); + mmio_write_32(SPM_CA7_CPU3_IRQ_MASK, 0); + break; + default: + break; + } + } +} + +void spm_mcdi_prepare(unsigned long mpidr) +{ + const struct pcm_desc *pcmdesc = spm_mcdi.pcmdesc; + struct pwr_ctrl *pwrctrl = spm_mcdi.pwrctrl; + + spm_lock_get(); + if (is_mcdi_ready() == 0) { + if (is_hotplug_ready() == 1) + spm_clear_hotplug(); + set_pwrctrl_pcm_flags(pwrctrl, 0); + spm_reset_and_init_pcm(); + spm_kick_im_to_fetch(pcmdesc); + spm_set_power_control(pwrctrl); + spm_set_wakeup_event(pwrctrl); + spm_kick_pcm_to_run(pwrctrl); + set_mcdi_ready(); + } + spm_mcdi_wfi_sel_enter(mpidr); + spm_lock_release(); +} + +void spm_mcdi_finish(unsigned long mpidr) +{ + unsigned long linear_id = platform_get_core_pos(mpidr); + + spm_lock_get(); + spm_mcdi_wfi_sel_leave(mpidr); + mmio_write_32(SPM_PCM_SW_INT_CLEAR, (0x1 << linear_id)); + spm_lock_release(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_mcdi.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_mcdi.h new file mode 100644 index 0000000..4df71d6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_mcdi.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __SPM_MCDI_H__ +#define __SPM_MCDI_H__ + +void spm_mcdi_wakeup_all_cores(void); +void spm_mcdi_wfi_sel_enter(unsigned long mpidr); +void spm_mcdi_wfi_sel_leave(unsigned long mpidr); +void spm_mcdi_prepare(unsigned long mpidr); +void spm_mcdi_finish(unsigned long mpidr); + +#endif /* __SPM_MCDI_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_suspend.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_suspend.c new file mode 100644 index 0000000..b4d0a60 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_suspend.c @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include + +/* + * System Power Manager (SPM) is a hardware module, which controls cpu or + * system power for different power scenarios using different firmware. + * This driver controls the system power in system suspend flow. + */ + +#define WAIT_UART_ACK_TIMES 80 /* 80 * 10us */ + +#define WAKE_SRC_FOR_SUSPEND \ + (WAKE_SRC_KP | WAKE_SRC_EINT | WAKE_SRC_MD32 | \ + WAKE_SRC_USB_CD | WAKE_SRC_USB_PDN | WAKE_SRC_THERM | \ + WAKE_SRC_SYSPWREQ | WAKE_SRC_ALL_MD32) + +#define WAKE_SRC_FOR_MD32 0 + +#define spm_is_wakesrc_invalid(wakesrc) \ + (!!((unsigned int)(wakesrc) & 0xc0003803)) + +const unsigned int spm_flags = + SPM_DUALVCORE_PDN_DIS | SPM_PASR_DIS | SPM_DPD_DIS | + SPM_CPU_DVS_DIS | SPM_OPT | SPM_INFRA_PDN_DIS; + +enum wake_reason_t spm_wake_reason = WR_NONE; + +/********************************************************** + * PCM sequence for cpu suspend + **********************************************************/ +static const unsigned int suspend_binary_ca7[] = { + 0x81f58407, 0x81f68407, 0x803a0400, 0x803a8400, 0x1b80001f, 0x20000000, + 0x80300400, 0x80318400, 0x80328400, 0xa1d28407, 0x81f20407, 0x81409801, + 0xd8000245, 0x17c07c1f, 0x18c0001f, 0x10006234, 0xc0c031a0, 0x1200041f, + 0x80310400, 0x1b80001f, 0x2000000a, 0xa0110400, 0x18c0001f, 0x100062c8, + 0xe0e00010, 0xe0e00030, 0xe0e00070, 0xe0e000f0, 0x1b80001f, 0x2000001a, + 0xe0e00ff0, 0xe8208000, 0x10006354, 0xfffe7fff, 0xe8208000, 0x10006834, + 0x00000010, 0x81f00407, 0xa1dd0407, 0x81fd0407, 0xc2803780, 0x1290041f, + 0x8880000c, 0x2f7be75f, 0xd8200642, 0x17c07c1f, 0x1b00001f, 0x7fffe7ff, + 0xd0000680, 0x17c07c1f, 0x1b00001f, 0x7ffff7ff, 0xf0000000, 0x17c07c1f, + 0x80880001, 0xd8000762, 0x17c07c1f, 0xd00027a0, 0x1200041f, 0xe8208000, + 0x10006834, 0x00000000, 0x1b00001f, 0x3fffe7ff, 0x1b80001f, 0x20000004, + 0xd820092c, 0x17c07c1f, 0xe8208000, 0x10006834, 0x00000010, 0xd00011a0, + 0x17c07c1f, 0x18c0001f, 0x10006608, 0x1910001f, 0x10006608, 0x813b0404, + 0xe0c00004, 0x1880001f, 0x10006320, 0xc0c03680, 0xe080000f, 0xd8200b23, + 0x17c07c1f, 0x1b00001f, 0x7ffff7ff, 0xd00011a0, 0x17c07c1f, 0xe080001f, + 0xe8208000, 0x10006354, 0xffffffff, 0x18c0001f, 0x100062c8, 0xe0e000f0, + 0xe0e00030, 0xe0e00000, 0x81409801, 0xd8000fe5, 0x17c07c1f, 0x18c0001f, + 0x10004094, 0x1910001f, 0x1020e374, 0xe0c00004, 0x18c0001f, 0x10004098, + 0x1910001f, 0x1020e378, 0xe0c00004, 0x18c0001f, 0x10011094, 0x1910001f, + 0x10213374, 0xe0c00004, 0x18c0001f, 0x10011098, 0x1910001f, 0x10213378, + 0xe0c00004, 0x1910001f, 0x10213378, 0x18c0001f, 0x10006234, 0xc0c03360, + 0x17c07c1f, 0xc2803780, 0x1290841f, 0xa1d20407, 0x81f28407, 0xa1d68407, + 0xa0128400, 0xa0118400, 0xa0100400, 0xa01a8400, 0xa01a0400, 0x19c0001f, + 0x001c239f, 0x1b00001f, 0x3fffefff, 0xf0000000, 0x17c07c1f, 0x808d8001, + 0xd8201422, 0x17c07c1f, 0x803d8400, 0x1b80001f, 0x2000001a, 0x80340400, + 0x17c07c1f, 0x17c07c1f, 0x80310400, 0x81fa0407, 0x81f18407, 0x81f08407, + 0xa1dc0407, 0x1b80001f, 0x200000b6, 0xd00020e0, 0x17c07c1f, 0x1880001f, + 0x20000208, 0x81411801, 0xd8001605, 0x17c07c1f, 0xe8208000, 0x1000f600, + 0xd2000000, 0x1380081f, 0x18c0001f, 0x10006240, 0xe0e00016, 0xe0e0001e, + 0xe0e0000e, 0xe0e0000f, 0x80368400, 0x1380081f, 0x80370400, 0x1380081f, + 0x80360400, 0x803e0400, 0x1380081f, 0x80380400, 0x803b0400, 0xa01d8400, + 0x1b80001f, 0x20000034, 0x803d8400, 0x1b80001f, 0x20000152, 0x803d0400, + 0x1380081f, 0x18c0001f, 0x1000f5c8, 0x1910001f, 0x1000f5c8, 0xa1000404, + 0xe0c00004, 0x18c0001f, 0x100125c8, 0x1910001f, 0x100125c8, 0xa1000404, + 0xe0c00004, 0x1910001f, 0x100125c8, 0x80340400, 0x17c07c1f, 0x17c07c1f, + 0x80310400, 0xe8208000, 0x10000044, 0x00000100, 0x1b80001f, 0x20000068, + 0x1b80001f, 0x2000000a, 0x18c0001f, 0x10006240, 0xe0e0000d, 0xd8001e65, + 0x17c07c1f, 0x18c0001f, 0x100040f4, 0x1910001f, 0x100040f4, 0xa11c8404, + 0xe0c00004, 0x1b80001f, 0x2000000a, 0x813c8404, 0xe0c00004, 0x18c0001f, + 0x100110f4, 0x1910001f, 0x100110f4, 0xa11c8404, 0xe0c00004, 0x1b80001f, + 0x2000000a, 0x813c8404, 0xe0c00004, 0x1b80001f, 0x20000100, 0x81fa0407, + 0x81f18407, 0x81f08407, 0xe8208000, 0x10006354, 0xfffe7b47, 0x18c0001f, + 0x65930003, 0xc0c03080, 0x17c07c1f, 0xa1d80407, 0xa1dc0407, 0x18c0001f, + 0x10006608, 0x1910001f, 0x10006608, 0xa11b0404, 0xe0c00004, 0xc2803780, + 0x1291041f, 0x8880000c, 0x2f7be75f, 0xd8202222, 0x17c07c1f, 0x1b00001f, + 0x3fffe7ff, 0xd0002260, 0x17c07c1f, 0x1b00001f, 0xbfffe7ff, 0xf0000000, + 0x17c07c1f, 0x1890001f, 0x10006608, 0x808b0801, 0xd8202502, 0x17c07c1f, + 0x1880001f, 0x10006320, 0xc0c03400, 0xe080000f, 0xd8002663, 0x17c07c1f, + 0xe080001f, 0xa1da0407, 0x81fc0407, 0xa0110400, 0xa0140400, 0xa01d8400, + 0xd0002fc0, 0x17c07c1f, 0x1b80001f, 0x20000fdf, 0x1890001f, 0x10006608, + 0x80c98801, 0x810a8801, 0x10918c1f, 0xa0939002, 0x8080080d, 0xd82027a2, + 0x12007c1f, 0x1b00001f, 0x3fffe7ff, 0x1b80001f, 0x20000004, 0xd800304c, + 0x17c07c1f, 0x1b00001f, 0xbfffe7ff, 0xd0003040, 0x17c07c1f, 0x81f80407, + 0x81fc0407, 0x18c0001f, 0x65930006, 0xc0c03080, 0x17c07c1f, 0x18c0001f, + 0x65930007, 0xc0c03080, 0x17c07c1f, 0x1880001f, 0x10006320, 0xc0c03400, + 0xe080000f, 0xd8002663, 0x17c07c1f, 0xe080001f, 0x18c0001f, 0x65930005, + 0xc0c03080, 0x17c07c1f, 0xa1da0407, 0xe8208000, 0x10000048, 0x00000100, + 0x1b80001f, 0x20000068, 0xa0110400, 0xa0140400, 0x18c0001f, 0x1000f5c8, + 0x1910001f, 0x1000f5c8, 0x81200404, 0xe0c00004, 0x18c0001f, 0x100125c8, + 0x1910001f, 0x100125c8, 0x81200404, 0xe0c00004, 0x1910001f, 0x100125c8, + 0xa01d0400, 0xa01b0400, 0xa0180400, 0x803d8400, 0xa01e0400, 0xa0160400, + 0xa0170400, 0xa0168400, 0x1b80001f, 0x20000104, 0x81411801, 0xd8002f85, + 0x17c07c1f, 0x18c0001f, 0x10006240, 0xc0c03360, 0x17c07c1f, 0xe8208000, + 0x1000f600, 0xd2000001, 0xd8000768, 0x17c07c1f, 0xc2803780, 0x1291841f, + 0x1b00001f, 0x7ffff7ff, 0xf0000000, 0x17c07c1f, 0x1900001f, 0x10006830, + 0xe1000003, 0x18c0001f, 0x10006834, 0xe0e00000, 0xe0e00001, 0xf0000000, + 0x17c07c1f, 0xe0f07f16, 0x1380201f, 0xe0f07f1e, 0x1380201f, 0xe0f07f0e, + 0x1b80001f, 0x20000104, 0xe0f07f0c, 0xe0f07f0d, 0xe0f07e0d, 0xe0f07c0d, + 0xe0f0780d, 0xf0000000, 0xe0f0700d, 0xe0f07f0d, 0xe0f07f0f, 0xe0f07f1e, + 0xf0000000, 0xe0f07f12, 0x11407c1f, 0x81f08407, 0x81f18407, 0x1b80001f, + 0x20000001, 0xa1d08407, 0xa1d18407, 0x1392841f, 0x812ab401, 0x80ebb401, + 0xa0c00c04, 0xd8203603, 0x17c07c1f, 0x80c01403, 0xd8203423, 0x01400405, + 0x1900001f, 0x10006814, 0xf0000000, 0xe1000003, 0xa1d00407, 0x1b80001f, + 0x20000208, 0x80ea3401, 0x1a00001f, 0x10006814, 0xf0000000, 0xe2000003, + 0x18c0001f, 0x10006b6c, 0x1910001f, 0x10006b6c, 0xa1002804, 0xf0000000, + 0xe0c00004, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x1840001f, 0x00000001, 0xa1d48407, 0x1990001f, + 0x10006b08, 0x1a50001f, 0x10006610, 0x8246a401, 0xe8208000, 0x10006b6c, + 0x00000000, 0x1b00001f, 0x2f7be75f, 0x81469801, 0xd8004305, 0x17c07c1f, + 0x1b80001f, 0xd00f0000, 0x8880000c, 0x2f7be75f, 0xd8005da2, 0x17c07c1f, + 0xd0004340, 0x17c07c1f, 0x1b80001f, 0x500f0000, 0xe8208000, 0x10006354, + 0xfffe7b47, 0xc0c06940, 0x81401801, 0xd80048e5, 0x17c07c1f, 0x81f60407, + 0x18c0001f, 0x10006200, 0xc0c05e60, 0x12807c1f, 0xe8208000, 0x1000625c, + 0x00000001, 0x1b80001f, 0x20000080, 0xc0c05e60, 0x1280041f, 0x18c0001f, + 0x10006204, 0xc0c06200, 0x1280041f, 0x18c0001f, 0x10006208, 0xc0c05e60, + 0x12807c1f, 0xe8208000, 0x10006244, 0x00000001, 0x1b80001f, 0x20000080, + 0xc0c05e60, 0x1280041f, 0x18d0001f, 0x10200200, 0x18c0001f, 0x10006290, + 0xc0c05e60, 0x1280041f, 0xe8208000, 0x10006404, 0x00003101, 0xc2803780, + 0x1292041f, 0x81469801, 0xd8204a45, 0x17c07c1f, 0x1b00001f, 0x2f7be75f, + 0x1b80001f, 0x30000004, 0x8880000c, 0x2f7be75f, 0xd8005802, 0x17c07c1f, + 0xc0c064c0, 0x17c07c1f, 0x18c0001f, 0x10006294, 0xe0f07fff, 0xe0e00fff, + 0xe0e000ff, 0x81449801, 0xd8004c85, 0x17c07c1f, 0x1a00001f, 0x10006604, + 0xe2200003, 0xc0c06580, 0x17c07c1f, 0xe2200005, 0xc0c06580, 0x17c07c1f, + 0xa1d38407, 0xa1d98407, 0x1800001f, 0x00000012, 0x1800001f, 0x00000e12, + 0x1800001f, 0x03800e12, 0x1800001f, 0x038e0e12, 0xe8208000, 0x10006310, + 0x0b1600f8, 0x1b00001f, 0xbfffe7ff, 0x1b80001f, 0x90100000, 0x80c00400, + 0xd8204fa3, 0xa1d58407, 0xa1dd8407, 0x1b00001f, 0x3fffefff, 0xd0004e60, + 0x17c07c1f, 0x1890001f, 0x100063e8, 0x88c0000c, 0x2f7be75f, 0xd80051c3, + 0x17c07c1f, 0x80c40001, 0xd8005143, 0x17c07c1f, 0x1b00001f, 0xbfffe7ff, + 0xd0005180, 0x17c07c1f, 0x1b00001f, 0x7ffff7ff, 0xd0004e60, 0x17c07c1f, + 0x80c40001, 0xd82052c3, 0x17c07c1f, 0xa1de0407, 0x1b00001f, 0x7fffe7ff, + 0xd0004e60, 0x17c07c1f, 0x18c0001f, 0x10006294, 0xe0e001fe, 0xe0e003fc, + 0xe0e007f8, 0xe0e00ff0, 0x1b80001f, 0x20000020, 0xe0f07ff0, 0xe0f07f00, + 0x81449801, 0xd80055a5, 0x17c07c1f, 0x1a00001f, 0x10006604, 0xe2200002, + 0xc0c06580, 0x17c07c1f, 0xe2200004, 0xc0c06580, 0x17c07c1f, 0x1b80001f, + 0x200016a8, 0x1800001f, 0x03800e12, 0x1b80001f, 0x20000300, 0x1800001f, + 0x00000e12, 0x1b80001f, 0x20000300, 0x1800001f, 0x00000012, 0x1b80001f, + 0x20000104, 0x10007c1f, 0x81f38407, 0x81f98407, 0x81f90407, 0x81f40407, + 0x1b80001f, 0x200016a8, 0x81401801, 0xd8005da5, 0x17c07c1f, 0xe8208000, + 0x10006404, 0x00002101, 0x18c0001f, 0x10006290, 0x1212841f, 0xc0c05fe0, + 0x12807c1f, 0xc0c05fe0, 0x1280041f, 0x18c0001f, 0x10006208, 0x1212841f, + 0xc0c05fe0, 0x12807c1f, 0xe8208000, 0x10006244, 0x00000000, 0x1b80001f, + 0x20000080, 0xc0c05fe0, 0x1280041f, 0xe8208000, 0x10200268, 0x000ffffe, + 0x18c0001f, 0x10006204, 0x1212841f, 0xc0c06340, 0x1280041f, 0x18c0001f, + 0x10006200, 0x1212841f, 0xc0c05fe0, 0x12807c1f, 0xe8208000, 0x1000625c, + 0x00000000, 0x1b80001f, 0x20000080, 0xc0c05fe0, 0x1280041f, 0x19c0001f, + 0x01411820, 0x1ac0001f, 0x55aa55aa, 0x10007c1f, 0xf0000000, 0xd8005f0a, + 0x17c07c1f, 0xe2e0004f, 0xe2e0006f, 0xe2e0002f, 0xd8205faa, 0x17c07c1f, + 0xe2e0002e, 0xe2e0003e, 0xe2e00032, 0xf0000000, 0x17c07c1f, 0xd80060aa, + 0x17c07c1f, 0xe2e00036, 0xe2e0003e, 0x1380201f, 0xe2e0003c, 0xd82061ca, + 0x17c07c1f, 0x1380201f, 0xe2e0007c, 0x1b80001f, 0x20000003, 0xe2e0005c, + 0xe2e0004c, 0xe2e0004d, 0xf0000000, 0x17c07c1f, 0xd8206309, 0x17c07c1f, + 0xe2e0000d, 0xe2e0000c, 0xe2e0001c, 0xe2e0001e, 0xe2e00016, 0xe2e00012, + 0xf0000000, 0x17c07c1f, 0xd8206489, 0x17c07c1f, 0xe2e00016, 0x1380201f, + 0xe2e0001e, 0x1380201f, 0xe2e0001c, 0x1380201f, 0xe2e0000c, 0xe2e0000d, + 0xf0000000, 0x17c07c1f, 0xa1d40407, 0x1391841f, 0xa1d90407, 0x1393041f, + 0xf0000000, 0x17c07c1f, 0x18d0001f, 0x10006604, 0x10cf8c1f, 0xd8206583, + 0x17c07c1f, 0xf0000000, 0x17c07c1f, 0xe8208000, 0x11008014, 0x00000002, + 0xe8208000, 0x11008020, 0x00000101, 0xe8208000, 0x11008004, 0x000000d0, + 0x1a00001f, 0x11008000, 0xd800684a, 0xe220005d, 0xd820686a, 0xe2200000, + 0xe2200001, 0xe8208000, 0x11008024, 0x00000001, 0x1b80001f, 0x20000424, + 0xf0000000, 0x17c07c1f, 0xa1d10407, 0x1b80001f, 0x20000020, 0xf0000000, + 0x17c07c1f +}; + +/* + * PCM binary for suspend scenario + */ +static const struct pcm_desc suspend_pcm_ca7 = { + .version = "pcm_suspend_20150805_V1", + .base = suspend_binary_ca7, + .size = 847, + .sess = 2, + .replace = 0, + .vec0 = EVENT_VEC(11, 1, 0, 0), + .vec1 = EVENT_VEC(12, 1, 0, 54), + .vec2 = EVENT_VEC(30, 1, 0, 143), + .vec3 = EVENT_VEC(31, 1, 0, 277), +}; + +/* + * SPM settings for suspend scenario + */ +static struct pwr_ctrl spm_ctrl = { + .wake_src = WAKE_SRC_FOR_SUSPEND, + .wake_src_md32 = WAKE_SRC_FOR_MD32, + .r0_ctrl_en = 1, + .r7_ctrl_en = 1, + .infra_dcm_lock = 1, + .wfi_op = WFI_OP_AND, + .pcm_apsrc_req = 0, + .ca7top_idle_mask = 0, + .ca15top_idle_mask = 0, + .mcusys_idle_mask = 0, + .disp_req_mask = 0, + .mfg_req_mask = 0, + .md32_req_mask = 1, + .srclkenai_mask = 1, + .ca7_wfi0_en = 1, + .ca7_wfi1_en = 1, + .ca7_wfi2_en = 1, + .ca7_wfi3_en = 1, + .ca15_wfi0_en = 1, + .ca15_wfi1_en = 1, + .ca15_wfi2_en = 1, + .ca15_wfi3_en = 1, +}; + +/* + * go_to_sleep_before_wfi() - trigger SPM to enter suspend scenario + */ +static void go_to_sleep_before_wfi(const unsigned int spm_flags) +{ + struct pwr_ctrl *pwrctrl; + + pwrctrl = &spm_ctrl; + + set_pwrctrl_pcm_flags(pwrctrl, spm_flags); + + spm_set_sysclk_settle(); + + INFO("sec = %u, wakesrc = 0x%x (%u)(%u)\n", + pwrctrl->timer_val, pwrctrl->wake_src, + is_cpu_pdn(pwrctrl->pcm_flags), + is_infra_pdn(pwrctrl->pcm_flags)); + + spm_reset_and_init_pcm(); + spm_init_pcm_register(); + spm_set_power_control(pwrctrl); + spm_set_wakeup_event(pwrctrl); + spm_kick_pcm_to_run(pwrctrl); + spm_init_event_vector(&suspend_pcm_ca7); + spm_kick_im_to_fetch(&suspend_pcm_ca7); +} + +/* + * go_to_sleep_after_wfi() - get wakeup reason after + * leaving suspend scenario and clean up SPM settings + */ +static enum wake_reason_t go_to_sleep_after_wfi(void) +{ + struct wake_status wakesta; + static enum wake_reason_t last_wr = WR_NONE; + + spm_get_wakeup_status(&wakesta); + spm_clean_after_wakeup(); + last_wr = spm_output_wake_reason(&wakesta); + + return last_wr; +} + +void spm_system_suspend(void) +{ + spm_lock_get(); + go_to_sleep_before_wfi(spm_flags); + set_suspend_ready(); + spm_lock_release(); +} + +void spm_system_suspend_finish(void) +{ + spm_lock_get(); + spm_wake_reason = go_to_sleep_after_wfi(); + INFO("spm_wake_reason=%d\n", spm_wake_reason); + clear_all_ready(); + spm_lock_release(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_suspend.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_suspend.h new file mode 100644 index 0000000..643713b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/spm/spm_suspend.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __SPM_SUSPEND_H__ +#define __SPM_SUSPEND_H__ + +/* cpu dormant return code */ +#define CPU_DORMANT_RESET 0 +#define CPU_DORMANT_ABORT 1 + +void spm_system_suspend(void); +void spm_system_suspend_finish(void); + +#endif /* __SPM_SUSPEND_H__*/ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.c new file mode 100644 index 0000000..63200bd --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include + +static void write_cpuxgpt(unsigned int reg_index, unsigned int value) +{ + mmio_write_32((uintptr_t)&mt8173_mcucfg->xgpt_idx, reg_index); + mmio_write_32((uintptr_t)&mt8173_mcucfg->xgpt_ctl, value); +} + +static void cpuxgpt_set_init_cnt(unsigned int countH, unsigned int countL) +{ + write_cpuxgpt(INDEX_CNT_H_INIT, countH); + /* update count when countL programmed */ + write_cpuxgpt(INDEX_CNT_L_INIT, countL); +} + +void generic_timer_backup(void) +{ + uint64_t cval; + + cval = read_cntpct_el0(); + cpuxgpt_set_init_cnt((uint32_t)(cval >> 32), + (uint32_t)(cval & 0xffffffff)); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.h new file mode 100644 index 0000000..329a250 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MT_CPUXGPT_H__ +#define __MT_CPUXGPT_H__ + +/* REG */ +#define INDEX_CNT_L_INIT 0x008 +#define INDEX_CNT_H_INIT 0x00C + +void generic_timer_backup(void); + +#endif /* __MT_CPUXGPT_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/uart/8250_console.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/uart/8250_console.S new file mode 100644 index 0000000..5b0ae6d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/uart/8250_console.S @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + + .globl console_core_init + .globl console_core_putc + .globl console_core_getc + + /* ----------------------------------------------- + * int console_core_init(unsigned long base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * Out: return 1 on success else 0 on error + * Clobber list : x1, x2, x3 + * ----------------------------------------------- + */ +func console_core_init + /* Check the input base address */ + cbz x0, core_init_fail + /* Check baud rate and uart clock for sanity */ + cbz w1, core_init_fail + cbz w2, core_init_fail + + /* Disable interrupt */ + str wzr, [x0, #UART_IER] + + /* Force DTR and RTS to high */ + mov w3, #(UART_MCR_DTR | UART_MCR_RTS) + str w3, [x0, #UART_MCR] + + /* Check high speed */ + movz w3, #:abs_g1:115200 + movk w3, #:abs_g0_nc:115200 + cmp w2, w3 + b.hi 1f + + /* Non high speed */ + lsl w2, w2, #4 + mov w3, wzr + b 2f + + /* High speed */ +1: lsl w2, w2, #2 + mov w3, #2 + + /* Set high speed UART register */ +2: str w3, [x0, #UART_HIGHSPEED] + + /* Calculate divisor */ + udiv w3, w1, w2 /* divisor = uartclk / (quot * baudrate) */ + msub w1, w3, w2, w1 /* remainder = uartclk % (quot * baudrate) */ + lsr w2, w2, #1 + cmp w1, w2 + cinc w3, w3, hs + + /* Set line configuration, access divisor latches */ + mov w1, #(UART_LCR_DLAB | UART_LCR_WLS_8) + str w1, [x0, #UART_LCR] + + /* Set the divisor */ + and w1, w3, #0xff + str w1, [x0, #UART_DLL] + lsr w1, w3, #8 + and w1, w1, #0xff + str w1, [x0, #UART_DLH] + + /* Hide the divisor latches */ + mov w1, #UART_LCR_WLS_8 + str w1, [x0, #UART_LCR] + + /* Enable FIFOs, and clear receive and transmit */ + mov w1, #(UART_FCR_FIFO_EN | UART_FCR_CLEAR_RCVR | \ + UART_FCR_CLEAR_XMIT) + str w1, [x0, #UART_FCR] + + mov w0, #1 + ret +core_init_fail: + mov w0, wzr + ret +endfunc console_core_init + + /* -------------------------------------------------------- + * int console_core_putc(int c, unsigned long base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_core_putc + /* Check the input parameter */ + cbz x1, putc_error + /* Prepend '\r' to '\n' */ + cmp w0, #0xA + b.ne 2f + + /* Check if the transmit FIFO is full */ +1: ldr w2, [x1, #UART_LSR] + and w2, w2, #UART_LSR_THRE + cbz w2, 1b + mov w2, #0xD + str w2, [x1, #UART_THR] + + /* Check if the transmit FIFO is full */ +2: ldr w2, [x1, #UART_LSR] + and w2, w2, #UART_LSR_THRE + cbz w2, 2b + str w0, [x1, #UART_THR] + ret +putc_error: + mov w0, #-1 + ret +endfunc console_core_putc + + /* --------------------------------------------- + * int console_core_getc(unsigned long base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * In : x0 - console base address + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_getc + cbz x0, getc_error + + /* Check if the receive FIFO is empty */ +1: ldr w1, [x0, #UART_LSR] + tbz w1, #UART_LSR_DR, 1b + ldr w0, [x0, #UART_RBR] + ret +getc_error: + mov w0, #-1 + ret +endfunc console_core_getc diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/uart/uart8250.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/uart/uart8250.h new file mode 100644 index 0000000..b0f5b8d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/drivers/uart/uart8250.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __UART8250_H__ +#define __UART8250_H__ + +/* UART register */ +#define UART_RBR 0x00 /* Receive buffer register */ +#define UART_DLL 0x00 /* Divisor latch lsb */ +#define UART_THR 0x00 /* Transmit holding register */ +#define UART_DLH 0x04 /* Divisor latch msb */ +#define UART_IER 0x04 /* Interrupt enable register */ +#define UART_FCR 0x08 /* FIFO control register */ +#define UART_LCR 0x0c /* Line control register */ +#define UART_MCR 0x10 /* Modem control register */ +#define UART_LSR 0x14 /* Line status register */ +#define UART_HIGHSPEED 0x24 /* High speed UART */ + +/* FCR */ +#define UART_FCR_FIFO_EN 0x01 /* enable FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /* clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* clear the XMIT FIFO */ + +/* LCR */ +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_DLAB 0x80 /* divisor latch access bit */ + +/* MCR */ +#define UART_MCR_DTR 0x01 +#define UART_MCR_RTS 0x02 + +/* LSR */ +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ + +#endif /* __UART8250_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/mcucfg.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/mcucfg.h new file mode 100644 index 0000000..d2474ac --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/mcucfg.h @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MCUCFG_H__ +#define __MCUCFG_H__ + +#include +#include + +struct mt8173_mcucfg_regs { + uint32_t mp0_ca7l_cache_config; + struct { + uint32_t mem_delsel0; + uint32_t mem_delsel1; + } mp0_cpu[4]; + uint32_t mp0_cache_mem_delsel0; + uint32_t mp0_cache_mem_delsel1; + uint32_t mp0_axi_config; + uint32_t mp0_misc_config[2]; + struct { + uint32_t rv_addr_lw; + uint32_t rv_addr_hw; + } mp0_rv_addr[4]; + uint32_t mp0_ca7l_cfg_dis; + uint32_t mp0_ca7l_clken_ctrl; + uint32_t mp0_ca7l_rst_ctrl; + uint32_t mp0_ca7l_misc_config; + uint32_t mp0_ca7l_dbg_pwr_ctrl; + uint32_t mp0_rw_rsvd0; + uint32_t mp0_rw_rsvd1; + uint32_t mp0_ro_rsvd; + uint32_t reserved0_0[100]; + uint32_t mp1_cpucfg; + uint32_t mp1_miscdbg; + uint32_t reserved0_1[13]; + uint32_t mp1_rst_ctl; + uint32_t mp1_clkenm_div; + uint32_t reserved0_2[7]; + uint32_t mp1_config_res; + uint32_t reserved0_3[13]; + struct { + uint32_t rv_addr_lw; + uint32_t rv_addr_hw; + } mp1_rv_addr[2]; + uint32_t reserved0_4[84]; + uint32_t mp0_rst_status; /* 0x400 */ + uint32_t mp0_dbg_ctrl; + uint32_t mp0_dbg_flag; + uint32_t mp0_ca7l_ir_mon; + struct { + uint32_t pc_lw; + uint32_t pc_hw; + uint32_t fp_arch32; + uint32_t sp_arch32; + uint32_t fp_arch64_lw; + uint32_t fp_arch64_hw; + uint32_t sp_arch64_lw; + uint32_t sp_arch64_hw; + } mp0_dbg_core[4]; + uint32_t dfd_ctrl; + uint32_t dfd_cnt_l; + uint32_t dfd_cnt_h; + uint32_t misccfg_mp0_rw_rsvd; + uint32_t misccfg_sec_vio_status0; + uint32_t misccfg_sec_vio_status1; + uint32_t reserved1[22]; + uint32_t misccfg_rw_rsvd; /* 0x500 */ + uint32_t mcusys_dbg_mon_sel_a; + uint32_t mcusys_dbg_mon; + uint32_t reserved2[61]; + uint32_t mcusys_config_a; /* 0x600 */ + uint32_t mcusys_config1_a; + uint32_t mcusys_gic_peribase_a; + uint32_t reserved3; + uint32_t sec_range0_start; /* 0x610 */ + uint32_t sec_range0_end; + uint32_t sec_range_enable; + uint32_t reserved4; + uint32_t int_pol_ctl[8]; /* 0x620 */ + uint32_t aclken_div; /* 0x640 */ + uint32_t pclken_div; + uint32_t l2c_sram_ctrl; + uint32_t armpll_jit_ctrl; + uint32_t cci_addrmap; /* 0x650 */ + uint32_t cci_config; + uint32_t cci_periphbase; + uint32_t cci_nevntcntovfl; + uint32_t cci_clk_ctrl; /* 0x660 */ + uint32_t cci_acel_s1_ctrl; + uint32_t bus_fabric_dcm_ctrl; + uint32_t reserved5; + uint32_t xgpt_ctl; /* 0x670 */ + uint32_t xgpt_idx; + uint32_t ptpod2_ctl0; + uint32_t ptpod2_ctl1; + uint32_t mcusys_revid; + uint32_t mcusys_rw_rsvd0; + uint32_t mcusys_rw_rsvd1; +}; + +static struct mt8173_mcucfg_regs *const mt8173_mcucfg = (void *)MCUCFG_BASE; + +/* cpu boot mode */ +enum { + MP0_CPUCFG_64BIT_SHIFT = 12, + MP1_CPUCFG_64BIT_SHIFT = 28, + MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT, + MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT +}; + +/* scu related */ +enum { + MP0_ACINACTM_SHIFT = 4, + MP1_ACINACTM_SHIFT = 0, + MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT, + MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT +}; + +enum { + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0, + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4, + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8, + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12, + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16, + + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT +}; + +enum { + MP1_AINACTS_SHIFT = 4, + MP1_AINACTS = 1 << MP1_AINACTS_SHIFT +}; + +enum { + MP1_SW_CG_GEN_SHIFT = 12, + MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT +}; + +enum { + MP1_L2RSTDISABLE_SHIFT = 14, + MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT +}; + +#endif /* __MCUCFG_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/plat_macros.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/plat_macros.S new file mode 100644 index 0000000..0e34b19 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/plat_macros.S @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +.section .rodata.gic_reg_name, "aS" +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ + " Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL3-1. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_print_gic_regs + mov_imm x16, BASE_GICD_BASE + mov_imm x17, BASE_GICC_BASE + /* Load the gicc reg list to x6 */ + adr x6, gicc_regs + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + .endm + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* ------------------------------------------------ + * The below macro prints out relevant interconnect + * registers whenever an unhandled exception is + * taken in BL3-1. + * Clobbers: x0 - x9, sp + * ------------------------------------------------ + */ + .macro plat_print_interconnect_regs + adr x6, cci_iface_regs + /* Store in x7 the base address of the first interface */ + mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX)) + ldr w8, [x7, #SNOOP_CTRL_REG] + /* Store in x7 the base address of the second interface */ + mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX)) + ldr w9, [x7, #SNOOP_CTRL_REG] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + .endm diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/platform_def.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/platform_def.h new file mode 100644 index 0000000..7759b3e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/platform_def.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#define DEBUG_XLAT_TABLE 0 + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#if DEBUG_XLAT_TABLE +#define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL1 +#define PLATFORM_STACK_SIZE 0x440 +#elif IMAGE_BL2 +#define PLATFORM_STACK_SIZE 0x400 +#elif IMAGE_BL31 +#define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL32 +#define PLATFORM_STACK_SIZE 0x440 +#endif + +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" + +#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 +#define PLATFORM_SYSTEM_COUNT 1 +#define PLATFORM_CLUSTER_COUNT 2 +#define PLATFORM_CLUSTER0_CORE_COUNT 4 +#define PLATFORM_CLUSTER1_CORE_COUNT 2 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ + PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ + PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +/* TF txet, ro, rw, internal SRAM, Size: release: 80KB, debug: 92KB */ +#define TZRAM_BASE (0x100000) +#if DEBUG +#define TZRAM_SIZE (0x20000) +#else +#define TZRAM_SIZE (0x20000) +#endif + +/* xlat_table , coherence ram, 64KB */ +#define TZRAM2_BASE (TZRAM_BASE + TZRAM_SIZE) +#define TZRAM2_SIZE (0x10000) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL3-1 debug size plus a + * little space for growth. + */ +#define BL31_BASE (TZRAM_BASE + 0x1000) +#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) +#define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define ADDR_SPACE_SIZE (1ull << 32) +#define MAX_XLAT_TABLES 4 +#define MAX_MMAP_REGIONS 16 + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/power_tracer.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/power_tracer.h new file mode 100644 index 0000000..9c35ce0 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/power_tracer.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __POWER_TRACER_H__ +#define __POWER_TRACER_H__ + +#define CPU_UP 0 +#define CPU_DOWN 1 +#define CPU_SUSPEND 2 +#define CLUSTER_UP 3 +#define CLUSTER_DOWN 4 +#define CLUSTER_SUSPEND 5 + +void trace_power_flow(unsigned long mpidr, unsigned char mode); + +#endif diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/scu.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/scu.h new file mode 100644 index 0000000..71f3929 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/include/scu.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SCU_H__ +#define __SCU_H__ + +void disable_scu(unsigned long mpidr); +void enable_scu(unsigned long mpidr); + +#endif diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/mt8173_def.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/mt8173_def.h new file mode 100644 index 0000000..ecf4cc6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/mt8173_def.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_DEF_H__ +#define __PLAT_DEF_H__ + +#define MT8173_PRIMARY_CPU 0x0 + +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define MT_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + +#define IO_PHYS (0x10000000) +#define INFRACFG_AO_BASE (IO_PHYS + 0x1000) +#define GPIO_BASE (IO_PHYS + 0x5000) +#define SPM_BASE (IO_PHYS + 0x6000) +#define RGU_BASE (IO_PHYS + 0x7000) +#define PMIC_WRAP_BASE (IO_PHYS + 0xD000) +#define MCUCFG_BASE (IO_PHYS + 0x200000) +#define TRNG_base (IO_PHYS + 0x20F000) +#define MT_GIC_BASE (IO_PHYS + 0x220000) +#define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000) + +/* Aggregate of all devices in the first GB */ +#define MTK_DEV_RNG0_BASE IO_PHYS +#define MTK_DEV_RNG0_SIZE 0x400000 +#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) +#define MTK_DEV_RNG1_SIZE 0x4000000 + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define MT8173_UART0_BASE (IO_PHYS + 0x01002000) +#define MT8173_UART1_BASE (IO_PHYS + 0x01003000) +#define MT8173_UART2_BASE (IO_PHYS + 0x01004000) +#define MT8173_UART3_BASE (IO_PHYS + 0x01005000) + +#define MT8173_BAUDRATE (115200) +#define MT8173_UART_CLOCK (26000000) + +/******************************************************************************* + * System counter frequency related constants + ******************************************************************************/ +#define SYS_COUNTER_FREQ_IN_TICKS 13000000 +#define SYS_COUNTER_FREQ_IN_MHZ 13 + +/******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ + +/* Base MTK_platform compatible GIC memory map */ +#define BASE_GICD_BASE (MT_GIC_BASE + 0x1000) +#define BASE_GICC_BASE (MT_GIC_BASE + 0x2000) +#define BASE_GICR_BASE 0 /* no GICR in GIC-400 */ +#define BASE_GICH_BASE (MT_GIC_BASE + 0x4000) +#define BASE_GICV_BASE (MT_GIC_BASE + 0x6000) +#define INT_POL_CTL0 0x10200620 + +#define GIC_PRIVATE_SIGNALS (32) + +/******************************************************************************* + * CCI-400 related constants + ******************************************************************************/ +#define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4 +#define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3 + +/******************************************************************************* + * WDT related constants + ******************************************************************************/ +#define MTK_WDT_BASE (RGU_BASE + 0) +#define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014) + +#define MTK_WDT_MODE_DUAL_MODE 0x0040 +#define MTK_WDT_MODE_IRQ 0x0008 +#define MTK_WDT_MODE_KEY 0x22000000 +#define MTK_WDT_MODE_EXTEN 0x0004 +#define MTK_WDT_SWRST_KEY 0x1209 + +/* FIQ platform related define */ +#define MT_IRQ_SEC_SGI_0 8 +#define MT_IRQ_SEC_SGI_1 9 +#define MT_IRQ_SEC_SGI_2 10 +#define MT_IRQ_SEC_SGI_3 11 +#define MT_IRQ_SEC_SGI_4 12 +#define MT_IRQ_SEC_SGI_5 13 +#define MT_IRQ_SEC_SGI_6 14 +#define MT_IRQ_SEC_SGI_7 15 + +#endif /* __PLAT_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_delay_timer.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_delay_timer.c new file mode 100644 index 0000000..cc66b80 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_delay_timer.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +static uint32_t plat_get_timer_value(void) +{ + /* Generic delay timer implementation expects the timer to be a down + * counter. We apply bitwise NOT operator to the tick values returned + * by read_cntpct_el0() to simulate the down counter. */ + return (uint32_t)(~read_cntpct_el0()); +} + +static const timer_ops_t plat_timer_ops = { + .get_timer_value = plat_get_timer_value, + .clk_mult = 1, + .clk_div = SYS_COUNTER_FREQ_IN_MHZ, +}; + +void plat_delay_timer_init(void) +{ + timer_init(&plat_timer_ops); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_mt_gic.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_mt_gic.c new file mode 100644 index 0000000..c9bdaa9 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_mt_gic.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +const unsigned int mt_irq_sec_array[] = { + MT_IRQ_SEC_SGI_0, + MT_IRQ_SEC_SGI_1, + MT_IRQ_SEC_SGI_2, + MT_IRQ_SEC_SGI_3, + MT_IRQ_SEC_SGI_4, + MT_IRQ_SEC_SGI_5, + MT_IRQ_SEC_SGI_6, + MT_IRQ_SEC_SGI_7 +}; + +void plat_mt_gic_init(void) +{ + arm_gic_init(BASE_GICC_BASE, + BASE_GICD_BASE, + BASE_GICR_BASE, + mt_irq_sec_array, + ARRAY_SIZE(mt_irq_sec_array)); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_pm.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_pm.c new file mode 100644 index 0000000..a84d031 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_pm.c @@ -0,0 +1,534 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* generic_timer_backup() */ +#include +#include +#include +#include +#include +#include +#include +#include + +struct core_context { + unsigned long timer_data[8]; + unsigned int count; + unsigned int rst; + unsigned int abt; + unsigned int brk; +}; + +struct cluster_context { + struct core_context core[PLATFORM_MAX_CPUS_PER_CLUSTER]; +}; + +/* + * Top level structure to hold the complete context of a multi cluster system + */ +struct system_context { + struct cluster_context cluster[PLATFORM_CLUSTER_COUNT]; +}; + +/* + * Top level structure which encapsulates the context of the entire system + */ +static struct system_context dormant_data[1]; + +static inline struct cluster_context *system_cluster( + struct system_context *system, + uint32_t clusterid) +{ + return &system->cluster[clusterid]; +} + +static inline struct core_context *cluster_core(struct cluster_context *cluster, + uint32_t cpuid) +{ + return &cluster->core[cpuid]; +} + +static struct cluster_context *get_cluster_data(unsigned long mpidr) +{ + uint32_t clusterid; + + clusterid = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; + + return system_cluster(dormant_data, clusterid); +} + +static struct core_context *get_core_data(unsigned long mpidr) +{ + struct cluster_context *cluster; + uint32_t cpuid; + + cluster = get_cluster_data(mpidr); + cpuid = mpidr & MPIDR_CPU_MASK; + + return cluster_core(cluster, cpuid); +} + +static void mt_save_generic_timer(unsigned long *container) +{ + uint64_t ctl; + uint64_t val; + + __asm__ volatile("mrs %x0, cntkctl_el1\n\t" + "mrs %x1, cntp_cval_el0\n\t" + "stp %x0, %x1, [%2, #0]" + : "=&r" (ctl), "=&r" (val) + : "r" (container) + : "memory"); + + __asm__ volatile("mrs %x0, cntp_tval_el0\n\t" + "mrs %x1, cntp_ctl_el0\n\t" + "stp %x0, %x1, [%2, #16]" + : "=&r" (val), "=&r" (ctl) + : "r" (container) + : "memory"); + + __asm__ volatile("mrs %x0, cntv_tval_el0\n\t" + "mrs %x1, cntv_ctl_el0\n\t" + "stp %x0, %x1, [%2, #32]" + : "=&r" (val), "=&r" (ctl) + : "r" (container) + : "memory"); +} + +static void mt_restore_generic_timer(unsigned long *container) +{ + uint64_t ctl; + uint64_t val; + + __asm__ volatile("ldp %x0, %x1, [%2, #0]\n\t" + "msr cntkctl_el1, %x0\n\t" + "msr cntp_cval_el0, %x1" + : "=&r" (ctl), "=&r" (val) + : "r" (container) + : "memory"); + + __asm__ volatile("ldp %x0, %x1, [%2, #16]\n\t" + "msr cntp_tval_el0, %x0\n\t" + "msr cntp_ctl_el0, %x1" + : "=&r" (val), "=&r" (ctl) + : "r" (container) + : "memory"); + + __asm__ volatile("ldp %x0, %x1, [%2, #32]\n\t" + "msr cntv_tval_el0, %x0\n\t" + "msr cntv_ctl_el0, %x1" + : "=&r" (val), "=&r" (ctl) + : "r" (container) + : "memory"); +} + +static inline uint64_t read_cntpctl(void) +{ + uint64_t cntpctl; + + __asm__ volatile("mrs %x0, cntp_ctl_el0" + : "=r" (cntpctl) : : "memory"); + + return cntpctl; +} + +static inline void write_cntpctl(uint64_t cntpctl) +{ + __asm__ volatile("msr cntp_ctl_el0, %x0" : : "r"(cntpctl)); +} + +static void stop_generic_timer(void) +{ + /* + * Disable the timer and mask the irq to prevent + * suprious interrupts on this cpu interface. It + * will bite us when we come back if we don't. It + * will be replayed on the inbound cluster. + */ + uint64_t cntpctl = read_cntpctl(); + + write_cntpctl(clr_cntp_ctl_enable(cntpctl)); +} + +static void mt_cpu_save(unsigned long mpidr) +{ + struct core_context *core; + + core = get_core_data(mpidr); + mt_save_generic_timer(core->timer_data); + + /* disable timer irq, and upper layer should enable it again. */ + stop_generic_timer(); +} + +static void mt_cpu_restore(unsigned long mpidr) +{ + struct core_context *core; + + core = get_core_data(mpidr); + mt_restore_generic_timer(core->timer_data); +} + +static void mt_platform_save_context(unsigned long mpidr) +{ + /* mcusys_save_context: */ + mt_cpu_save(mpidr); +} + +static void mt_platform_restore_context(unsigned long mpidr) +{ + /* mcusys_restore_context: */ + mt_cpu_restore(mpidr); +} + +/******************************************************************************* +* Private function which is used to determine if any platform actions +* should be performed for the specified affinity instance given its +* state. Nothing needs to be done if the 'state' is not off or if this is not +* the highest affinity level which will enter the 'state'. +*******************************************************************************/ +static int32_t plat_do_plat_actions(unsigned int afflvl, unsigned int state) +{ + unsigned int max_phys_off_afflvl; + + assert(afflvl <= MPIDR_AFFLVL2); + + if (state != PSCI_STATE_OFF) + return -EAGAIN; + + /* + * Find the highest affinity level which will be suspended and postpone + * all the platform specific actions until that level is hit. + */ + max_phys_off_afflvl = psci_get_max_phys_off_afflvl(); + assert(max_phys_off_afflvl != PSCI_INVALID_DATA); + if (afflvl != max_phys_off_afflvl) + return -EAGAIN; + + return 0; +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance is about to enter + * standby. + ******************************************************************************/ +static void plat_affinst_standby(unsigned int power_state) +{ + unsigned int target_afflvl; + + /* Sanity check the requested state */ + target_afflvl = psci_get_pstate_afflvl(power_state); + + /* + * It's possible to enter standby only on affinity level 0 i.e. a cpu + * on the MTK_platform. Ignore any other affinity level. + */ + if (target_afflvl == MPIDR_AFFLVL0) { + /* + * Enter standby state. dsb is good practice before using wfi + * to enter low power states. + */ + dsb(); + wfi(); + } +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance is about to be turned + * on. The level and mpidr determine the affinity instance. + ******************************************************************************/ +static int plat_affinst_on(unsigned long mpidr, + unsigned long sec_entrypoint, + unsigned int afflvl, + unsigned int state) +{ + int rc = PSCI_E_SUCCESS; + unsigned long cpu_id; + unsigned long cluster_id; + uintptr_t rv; + + /* + * It's possible to turn on only affinity level 0 i.e. a cpu + * on the MTK_platform. Ignore any other affinity level. + */ + if (afflvl != MPIDR_AFFLVL0) + return rc; + + cpu_id = mpidr & MPIDR_CPU_MASK; + cluster_id = mpidr & MPIDR_CLUSTER_MASK; + + if (cluster_id) + rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw; + else + rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw; + + mmio_write_32(rv, sec_entrypoint); + INFO("mt_on[%ld:%ld], entry %x\n", + cluster_id, cpu_id, mmio_read_32(rv)); + + spm_hotplug_on(mpidr); + + return rc; +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance is about to be turned + * off. The level and mpidr determine the affinity instance. The 'state' arg. + * allows the platform to decide whether the cluster is being turned off and + * take apt actions. + * + * CAUTION: This function is called with coherent stacks so that caches can be + * turned off, flushed and coherency disabled. There is no guarantee that caches + * will remain turned on across calls to this function as each affinity level is + * dealt with. So do not write & read global variables across calls. It will be + * wise to do flush a write to the global to prevent unpredictable results. + ******************************************************************************/ +static void plat_affinst_off(unsigned int afflvl, unsigned int state) +{ + unsigned long mpidr = read_mpidr_el1(); + + /* Determine if any platform actions need to be executed. */ + if (plat_do_plat_actions(afflvl, state) == -EAGAIN) + return; + + /* Prevent interrupts from spuriously waking up this cpu */ + arm_gic_cpuif_deactivate(); + + spm_hotplug_off(mpidr); + + trace_power_flow(mpidr, CPU_DOWN); + + if (afflvl != MPIDR_AFFLVL0) { + /* Disable coherency if this cluster is to be turned off */ + plat_cci_disable(); + + trace_power_flow(mpidr, CLUSTER_DOWN); + } +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance is about to be + * suspended. The level and mpidr determine the affinity instance. The 'state' + * arg. allows the platform to decide whether the cluster is being turned off + * and take apt actions. + * + * CAUTION: This function is called with coherent stacks so that caches can be + * turned off, flushed and coherency disabled. There is no guarantee that caches + * will remain turned on across calls to this function as each affinity level is + * dealt with. So do not write & read global variables across calls. It will be + * wise to do flush a write to the global to prevent unpredictable results. + ******************************************************************************/ +static void plat_affinst_suspend(unsigned long sec_entrypoint, + unsigned int afflvl, + unsigned int state) +{ + unsigned long mpidr = read_mpidr_el1(); + unsigned long cluster_id; + unsigned long cpu_id; + uintptr_t rv; + + /* Determine if any platform actions need to be executed. */ + if (plat_do_plat_actions(afflvl, state) == -EAGAIN) + return; + + cpu_id = mpidr & MPIDR_CPU_MASK; + cluster_id = mpidr & MPIDR_CLUSTER_MASK; + + if (cluster_id) + rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw; + else + rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw; + + mmio_write_32(rv, sec_entrypoint); + + if (afflvl == MPIDR_AFFLVL0) + spm_mcdi_prepare(mpidr); + + if (afflvl >= MPIDR_AFFLVL0) + mt_platform_save_context(mpidr); + + /* Perform the common cluster specific operations */ + if (afflvl >= MPIDR_AFFLVL1) { + /* Disable coherency if this cluster is to be turned off */ + plat_cci_disable(); + disable_scu(mpidr); + + trace_power_flow(mpidr, CLUSTER_SUSPEND); + } + + if (afflvl >= MPIDR_AFFLVL2) { + generic_timer_backup(); + spm_system_suspend(); + /* Prevent interrupts from spuriously waking up this cpu */ + arm_gic_cpuif_deactivate(); + } +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance has just been powered + * on after being turned off earlier. The level and mpidr determine the affinity + * instance. The 'state' arg. allows the platform to decide whether the cluster + * was turned off prior to wakeup and do what's necessary to setup it up + * correctly. + ******************************************************************************/ +static void plat_affinst_on_finish(unsigned int afflvl, unsigned int state) +{ + unsigned long mpidr = read_mpidr_el1(); + + /* Determine if any platform actions need to be executed. */ + if (plat_do_plat_actions(afflvl, state) == -EAGAIN) + return; + + /* Perform the common cluster specific operations */ + if (afflvl >= MPIDR_AFFLVL1) { + enable_scu(mpidr); + + /* Enable coherency if this cluster was off */ + plat_cci_enable(); + trace_power_flow(mpidr, CLUSTER_UP); + } + + /* Enable the gic cpu interface */ + arm_gic_cpuif_setup(); + arm_gic_pcpu_distif_setup(); + trace_power_flow(mpidr, CPU_UP); +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance has just been powered + * on after having been suspended earlier. The level and mpidr determine the + * affinity instance. + ******************************************************************************/ +static void plat_affinst_suspend_finish(unsigned int afflvl, unsigned int state) +{ + unsigned long mpidr = read_mpidr_el1(); + + /* Determine if any platform actions need to be executed. */ + if (plat_do_plat_actions(afflvl, state) == -EAGAIN) + return; + + if (afflvl >= MPIDR_AFFLVL2) { + /* Enable the gic cpu interface */ + arm_gic_setup(); + arm_gic_cpuif_setup(); + spm_system_suspend_finish(); + } + + /* Perform the common cluster specific operations */ + if (afflvl >= MPIDR_AFFLVL1) { + enable_scu(mpidr); + + /* Enable coherency if this cluster was off */ + plat_cci_enable(); + trace_power_flow(mpidr, CLUSTER_UP); + } + + if (afflvl >= MPIDR_AFFLVL0) + mt_platform_restore_context(mpidr); + + if (afflvl == MPIDR_AFFLVL0) + spm_mcdi_finish(mpidr); + + arm_gic_pcpu_distif_setup(); +} + +static unsigned int plat_get_sys_suspend_power_state(void) +{ + /* StateID: 0, StateType: 1(power down), PowerLevel: 2(system) */ + return psci_make_powerstate(0, 1, 2); +} + +/******************************************************************************* + * MTK handlers to shutdown/reboot the system + ******************************************************************************/ +static void __dead2 plat_system_off(void) +{ + INFO("MTK System Off\n"); + + gpio_set(GPIO120, GPIO_OUT_ZERO); + rtc_bbpu_power_down(); + + wfi(); + ERROR("MTK System Off: operation not handled.\n"); + panic(); +} + +static void __dead2 plat_system_reset(void) +{ + /* Write the System Configuration Control Register */ + INFO("MTK System Reset\n"); + + mmio_clrsetbits_32(MTK_WDT_BASE, + (MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ), + MTK_WDT_MODE_KEY); + mmio_setbits_32(MTK_WDT_BASE, (MTK_WDT_MODE_KEY | MTK_WDT_MODE_EXTEN)); + mmio_setbits_32(MTK_WDT_SWRST, MTK_WDT_SWRST_KEY); + + wfi(); + ERROR("MTK System Reset: operation not handled.\n"); + panic(); +} + +/******************************************************************************* + * Export the platform handlers to enable psci to invoke them + ******************************************************************************/ +static const plat_pm_ops_t plat_plat_pm_ops = { + .affinst_standby = plat_affinst_standby, + .affinst_on = plat_affinst_on, + .affinst_off = plat_affinst_off, + .affinst_suspend = plat_affinst_suspend, + .affinst_on_finish = plat_affinst_on_finish, + .affinst_suspend_finish = plat_affinst_suspend_finish, + .system_off = plat_system_off, + .system_reset = plat_system_reset, + .get_sys_suspend_power_state = plat_get_sys_suspend_power_state, +}; + +/******************************************************************************* + * Export the platform specific power ops & initialize the mtk_platform power + * controller + ******************************************************************************/ +int platform_setup_pm(const plat_pm_ops_t **plat_ops) +{ + *plat_ops = &plat_plat_pm_ops; + return 0; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_private.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_private.h new file mode 100644 index 0000000..bdde6a6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_private.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_PRIVATE_H__ +#define __PLAT_PRIVATE_H__ + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void plat_configure_mmu_el3(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long, + unsigned long, + unsigned long); + +void plat_cci_init(void); +void plat_cci_enable(void); +void plat_cci_disable(void); + +/* Declarations for plat_mt_gic.c */ +void plat_mt_gic_init(void); + +/* Declarations for plat_topology.c */ +int mt_setup_topology(void); + +void plat_delay_timer_init(void); + +#endif /* __PLAT_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_sip_calls.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_sip_calls.c new file mode 100644 index 0000000..92deb60 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_sip_calls.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + +/* Authorized secure register list */ +enum { + SREG_HDMI_COLOR_EN = 0x14000904 +}; + +static const uint32_t authorized_sreg[] = { + SREG_HDMI_COLOR_EN +}; + +#define authorized_sreg_cnt \ + (sizeof(authorized_sreg) / sizeof(authorized_sreg[0])) + +uint64_t mt_sip_set_authorized_sreg(uint32_t sreg, uint32_t val) +{ + uint64_t i; + + for (i = 0; i < authorized_sreg_cnt; i++) { + if (authorized_sreg[i] == sreg) { + mmio_write_32(sreg, val); + return MTK_SIP_E_SUCCESS; + } + } + + return MTK_SIP_E_INVALID_PARAM; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_topology.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_topology.c new file mode 100644 index 0000000..96598b6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/plat_topology.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr) +{ + /* Report 1 (absent) instance at levels higher that the cluster level */ + if (aff_lvl > MPIDR_AFFLVL1) + return PLATFORM_SYSTEM_COUNT; + + if (aff_lvl == MPIDR_AFFLVL1) + return PLATFORM_CLUSTER_COUNT; + + return mpidr & 0x100 ? PLATFORM_CLUSTER1_CORE_COUNT : + PLATFORM_CLUSTER0_CORE_COUNT; +} + +unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr) +{ + return aff_lvl <= MPIDR_AFFLVL2 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT; +} + +int mt_setup_topology(void) +{ + /* [TODO] Make topology configurable via SCC */ + return 0; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/platform.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/platform.mk new file mode 100644 index 0000000..30df32f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/platform.mk @@ -0,0 +1,92 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +MTK_PLAT := plat/mediatek +MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} + +PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ + -I${MTK_PLAT_SOC}/ \ + -I${MTK_PLAT_SOC}/drivers/gpio/ \ + -I${MTK_PLAT_SOC}/drivers/mtcmos/ \ + -I${MTK_PLAT_SOC}/drivers/pmic/ \ + -I${MTK_PLAT_SOC}/drivers/rtc/ \ + -I${MTK_PLAT_SOC}/drivers/spm/ \ + -I${MTK_PLAT_SOC}/drivers/timer/ \ + -I${MTK_PLAT_SOC}/drivers/uart/ \ + -I${MTK_PLAT_SOC}/include/ + +PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \ + plat/common/aarch64/plat_common.c \ + plat/common/plat_gic.c + +BL31_SOURCES += drivers/arm/cci/cci.c \ + drivers/arm/gic/arm_gic.c \ + drivers/arm/gic/gic_v2.c \ + drivers/arm/gic/gic_v3.c \ + drivers/console/console.S \ + drivers/delay_timer/delay_timer.c \ + lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + lib/cpus/aarch64/cortex_a72.S \ + plat/common/aarch64/platform_mp_stack.S \ + ${MTK_PLAT}/common/mtk_sip_svc.c \ + ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ + ${MTK_PLAT_SOC}/aarch64/platform_common.c \ + ${MTK_PLAT_SOC}/bl31_plat_setup.c \ + ${MTK_PLAT_SOC}/drivers/gpio/gpio.c \ + ${MTK_PLAT_SOC}/drivers/mtcmos/mtcmos.c \ + ${MTK_PLAT_SOC}/drivers/pmic/pmic_wrap_init.c \ + ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \ + ${MTK_PLAT_SOC}/drivers/spm/spm.c \ + ${MTK_PLAT_SOC}/drivers/spm/spm_hotplug.c \ + ${MTK_PLAT_SOC}/drivers/spm/spm_mcdi.c \ + ${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c \ + ${MTK_PLAT_SOC}/drivers/timer/mt_cpuxgpt.c \ + ${MTK_PLAT_SOC}/drivers/uart/8250_console.S \ + ${MTK_PLAT_SOC}/plat_delay_timer.c \ + ${MTK_PLAT_SOC}/plat_mt_gic.c \ + ${MTK_PLAT_SOC}/plat_pm.c \ + ${MTK_PLAT_SOC}/plat_sip_calls.c \ + ${MTK_PLAT_SOC}/plat_topology.c \ + ${MTK_PLAT_SOC}/power_tracer.c \ + ${MTK_PLAT_SOC}/scu.c + +# Flag used by the MTK_platform port to determine the version of ARM GIC +# architecture to use for interrupt management in EL3. +ARM_GIC_ARCH := 2 +$(eval $(call add_define,ARM_GIC_ARCH)) + +# Enable workarounds for selected Cortex-A53 erratas. +ERRATA_A53_826319 := 1 +ERRATA_A53_836870 := 1 + +# indicate the reset vector address can be programmed +PROGRAMMABLE_RESET_ADDRESS := 1 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/power_tracer.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/power_tracer.c new file mode 100644 index 0000000..15eb2ce --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/power_tracer.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#define trace_log(...) INFO("psci: " __VA_ARGS__) + +void trace_power_flow(unsigned long mpidr, unsigned char mode) +{ + switch (mode) { + case CPU_UP: + trace_log("core %ld:%ld ON\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, + (mpidr & MPIDR_CPU_MASK)); + break; + case CPU_DOWN: + trace_log("core %ld:%ld OFF\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, + (mpidr & MPIDR_CPU_MASK)); + break; + case CPU_SUSPEND: + trace_log("core %ld:%ld SUSPEND\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, + (mpidr & MPIDR_CPU_MASK)); + break; + case CLUSTER_UP: + trace_log("cluster %ld ON\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); + break; + case CLUSTER_DOWN: + trace_log("cluster %ld OFF\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); + break; + case CLUSTER_SUSPEND: + trace_log("cluster %ld SUSPEND\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); + break; + default: + trace_log("unknown power mode\n"); + break; + } +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/scu.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/scu.c new file mode 100644 index 0000000..88af787 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/mediatek/mt8173/scu.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +void disable_scu(unsigned long mpidr) +{ + if (mpidr & MPIDR_CLUSTER_MASK) + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, + MP1_ACINACTM); + else + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, + MP0_ACINACTM); +} + +void enable_scu(unsigned long mpidr) +{ + if (mpidr & MPIDR_CLUSTER_MASK) + mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, + MP1_ACINACTM); + else + mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, + MP0_ACINACTM); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/aarch64/tegra_helpers.S new file mode 100644 index 0000000..d9f287c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -0,0 +1,368 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include + + /* Global functions */ + .globl platform_is_primary_cpu + .globl platform_get_core_pos + .globl platform_get_entrypoint + .globl plat_secondary_cold_boot_setup + .globl platform_mem_init + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl tegra_secure_entrypoint + .globl plat_reset_handler + + /* Global variables */ + .globl sec_entry_point + .globl ns_image_entrypoint + .globl tegra_bl31_phys_base + + /* --------------------- + * Common CPU init code + * --------------------- + */ +.macro cpu_init_common + +#if ENABLE_L2_DYNAMIC_RETENTION + /* --------------------------- + * Enable processor retention + * --------------------------- + */ + mrs x0, L2ECTLR_EL1 + mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT + bic x0, x0, #L2ECTLR_RET_CTRL_MASK + orr x0, x0, x1 + msr L2ECTLR_EL1, x0 + isb +#endif + +#if ENABLE_CPU_DYNAMIC_RETENTION + mrs x0, CPUECTLR_EL1 + mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT + bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK + orr x0, x0, x1 + msr CPUECTLR_EL1, x0 + isb +#endif + +#if ENABLE_NS_L2_CPUECTRL_RW_ACCESS + /* ------------------------------------------------------- + * Enable L2 and CPU ECTLR RW access from non-secure world + * ------------------------------------------------------- + */ + mov x0, #ACTLR_EL3_ENABLE_ALL_ACCESS + msr actlr_el3, x0 + msr actlr_el2, x0 + isb +#endif + + /* -------------------------------- + * Enable the cycle count register + * -------------------------------- + */ + mrs x0, pmcr_el0 + ubfx x0, x0, #11, #5 // read PMCR.N field + mov x1, #1 + lsl x0, x1, x0 + sub x0, x0, #1 // mask of event counters + orr x0, x0, #0x80000000 // disable overflow intrs + msr pmintenclr_el1, x0 + msr pmuserenr_el0, x1 // enable user mode access + + /* ---------------------------------------------------------------- + * Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count + * register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ + * registers from EL0. + * ---------------------------------------------------------------- + */ + mrs x0, cntkctl_el1 + orr x0, x0, #EL0VCTEN_BIT + msr cntkctl_el1, x0 +.endm + + /* ----------------------------------------------------- + * int platform_is_primary_cpu(int mpidr); + * + * This function checks if this is the Primary CPU + * ----------------------------------------------------- + */ +func platform_is_primary_cpu + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #TEGRA_PRIMARY_CPU + cset x0, eq + ret +endfunc platform_is_primary_cpu + + /* ----------------------------------------------------- + * int platform_get_core_pos(int mpidr); + * + * With this function: CorePos = CoreId + * ----------------------------------------------------- + */ +func platform_get_core_pos + and x0, x0, #MPIDR_CPU_MASK + ret +endfunc platform_get_core_pos + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset. Right + * now this is a stub function. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + mov x0, #0 + ret +endfunc plat_secondary_cold_boot_setup + + /* ----------------------------------------------------- + * void platform_get_entrypoint (unsigned int mpidr); + * + * Main job of this routine is to distinguish between + * a cold and warm boot. If the sec_entry_point for + * this CPU is present, then it's a warm boot. + * + * ----------------------------------------------------- + */ +func platform_get_entrypoint + and x0, x0, #MPIDR_CPU_MASK + adr x1, sec_entry_point + ldr x0, [x1, x0, lsl #3] + ret +endfunc platform_get_entrypoint + + /* -------------------------------------------------------- + * void platform_mem_init (void); + * + * Any memory init, relocation to be done before the + * platform boots. Called very early in the boot process. + * -------------------------------------------------------- + */ +func platform_mem_init + mov x0, #0 + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0, x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, TEGRA_BOOT_UART_BASE + mov_imm x1, TEGRA_BOOT_UART_CLK_IN_HZ + mov_imm x2, TEGRA_CONSOLE_BAUDRATE + b console_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(void) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, TEGRA_BOOT_UART_BASE + b console_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------------- + * Function to handle a platform reset and store + * input parameters passed by BL2. + * --------------------------------------------------- + */ +func plat_reset_handler + + /* ----------------------------------- + * derive and save the phys_base addr + * ----------------------------------- + */ + adr x17, tegra_bl31_phys_base + ldr x18, [x17] + cbnz x18, 1f + adr x18, bl31_entrypoint + str x18, [x17] + +1: cpu_init_common + + ret +endfunc plat_reset_handler + + /* ---------------------------------------- + * Secure entrypoint function for CPU boot + * ---------------------------------------- + */ + .align 6 +func tegra_secure_entrypoint + +#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT + + /* ------------------------------------------------------- + * Invalidate BTB along with I$ to remove any stale + * entries from the branch predictor array. + * ------------------------------------------------------- + */ + mrs x0, CPUACTLR_EL1 + orr x0, x0, #1 + msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ + dsb sy + isb + ic iallu /* actual invalidate */ + dsb sy + isb + + mrs x0, CPUACTLR_EL1 + bic x0, x0, #1 + msr CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ + dsb sy + isb + + .rept 7 + nop /* wait */ + .endr + + /* ----------------------------------------------- + * Extract OSLK bit and check if it is '1'. This + * bit remains '0' for A53 on warm-resets. If '1', + * turn off regional clock gating and request warm + * reset. + * ----------------------------------------------- + */ + mrs x0, oslsr_el1 + and x0, x0, #2 + mrs x1, mpidr_el1 + bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */ + b.eq restore_oslock + mov x0, xzr + msr oslar_el1, x0 /* os lock stays 0 across warm reset */ + mov x3, #3 + movz x4, #0x8000, lsl #48 + msr CPUACTLR_EL1, x4 /* turn off RCG */ + isb + msr rmr_el3, x3 /* request warm reset */ + isb + dsb sy +1: wfi + b 1b + + /* -------------------------------------------------- + * These nops are here so that speculative execution + * won't harm us before we are done with warm reset. + * -------------------------------------------------- + */ + .rept 65 + nop + .endr + + /* -------------------------------------------------- + * Do not insert instructions here + * -------------------------------------------------- + */ +#endif + + /* -------------------------------------------------- + * Restore OS Lock bit + * -------------------------------------------------- + */ +restore_oslock: + mov x0, #1 + msr oslar_el1, x0 + + cpu_init_common + + /* --------------------------------------------------------------------- + * The initial state of the Architectural feature trap register + * (CPTR_EL3) is unknown and it must be set to a known state. All + * feature traps are disabled. Some bits in this register are marked as + * Reserved and should not be modified. + * + * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 + * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. + * CPTR_EL3.TTA: This causes access to the Trace functionality to trap + * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register + * access to trace functionality is not supported, this bit is RES0. + * CPTR_EL3.TFP: This causes instructions that access the registers + * associated with Floating Point and Advanced SIMD execution to trap + * to EL3 when executed from any exception level, unless trapped to EL1 + * or EL2. + * --------------------------------------------------------------------- + */ + mrs x1, cptr_el3 + bic w1, w1, #TCPAC_BIT + bic w1, w1, #TTA_BIT + bic w1, w1, #TFP_BIT + msr cptr_el3, x1 + + /* -------------------------------------------------- + * Get secure world's entry point and jump to it + * -------------------------------------------------- + */ + mrs x0, mpidr_el1 + bl platform_get_entrypoint + br x0 +endfunc tegra_secure_entrypoint + + .data + .align 3 + + /* -------------------------------------------------- + * Per-CPU Secure entry point - resume from suspend + * -------------------------------------------------- + */ +sec_entry_point: + .rept PLATFORM_CORE_COUNT + .quad 0 + .endr + + /* -------------------------------------------------- + * NS world's cold boot entry point + * -------------------------------------------------- + */ +ns_image_entrypoint: + .quad 0 + + /* -------------------------------------------------- + * BL31's physical base address + * -------------------------------------------------- + */ +tegra_bl31_phys_base: + .quad 0 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c new file mode 100644 index 0000000..b473dd6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CLK_RST_DEV_L_SET 0x300 +#define CLK_RST_DEV_L_CLR 0x304 +#define CLK_BPMP_RST (1 << 1) + +#define EVP_BPMP_RESET_VECTOR 0x200 + +static const uint64_t flowctrl_offset_cpu_csr[4] = { + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU0_CSR), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 8), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 16) +}; + +static const uint64_t flowctrl_offset_halt_cpu[4] = { + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU0_EVENTS), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 8), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 16) +}; + +static const uint64_t flowctrl_offset_cc4_ctrl[4] = { + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 4), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 8), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 12) +}; + +static inline void tegra_fc_cc4_ctrl(int cpu_id, uint32_t val) +{ + mmio_write_32(flowctrl_offset_cc4_ctrl[cpu_id], val); + val = mmio_read_32(flowctrl_offset_cc4_ctrl[cpu_id]); +} + +static inline void tegra_fc_cpu_csr(int cpu_id, uint32_t val) +{ + mmio_write_32(flowctrl_offset_cpu_csr[cpu_id], val); + val = mmio_read_32(flowctrl_offset_cpu_csr[cpu_id]); +} + +static inline void tegra_fc_halt_cpu(int cpu_id, uint32_t val) +{ + mmio_write_32(flowctrl_offset_halt_cpu[cpu_id], val); + val = mmio_read_32(flowctrl_offset_halt_cpu[cpu_id]); +} + +static void tegra_fc_prepare_suspend(int cpu_id, uint32_t csr) +{ + uint32_t val; + + val = FLOWCTRL_HALT_GIC_IRQ | FLOWCTRL_HALT_GIC_FIQ | + FLOWCTRL_HALT_LIC_IRQ | FLOWCTRL_HALT_LIC_FIQ | + FLOWCTRL_WAITEVENT; + tegra_fc_halt_cpu(cpu_id, val); + + val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG | + FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu_id); + tegra_fc_cpu_csr(cpu_id, val | csr); +} + +/******************************************************************************* + * Suspend the current CPU + ******************************************************************************/ +void tegra_fc_cpu_idle(uint32_t mpidr) +{ + int cpu = mpidr & MPIDR_CPU_MASK; + + VERBOSE("CPU%d powering down...\n", cpu); + tegra_fc_prepare_suspend(cpu, 0); +} + +/******************************************************************************* + * Suspend the current CPU cluster + ******************************************************************************/ +void tegra_fc_cluster_idle(uint32_t mpidr) +{ + int cpu = mpidr & MPIDR_CPU_MASK; + uint32_t val; + + VERBOSE("Entering cluster idle state...\n"); + + tegra_fc_cc4_ctrl(cpu, 0); + + /* hardware L2 flush is faster for A53 only */ + tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, + !!MPIDR_AFFLVL1_VAL(mpidr)); + + /* suspend the CPU cluster */ + val = FLOWCTRL_PG_CPU_NONCPU << FLOWCTRL_ENABLE_EXT; + tegra_fc_prepare_suspend(cpu, val); +} + +/******************************************************************************* + * Power down the current CPU cluster + ******************************************************************************/ +void tegra_fc_cluster_powerdn(uint32_t mpidr) +{ + int cpu = mpidr & MPIDR_CPU_MASK; + uint32_t val; + + VERBOSE("Entering cluster powerdn state...\n"); + + tegra_fc_cc4_ctrl(cpu, 0); + + /* hardware L2 flush is faster for A53 only */ + tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, + read_midr() == CORTEX_A53_MIDR); + + /* power down the CPU cluster */ + val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT; + tegra_fc_prepare_suspend(cpu, val); +} + +/******************************************************************************* + * Suspend the entire SoC + ******************************************************************************/ +void tegra_fc_soc_powerdn(uint32_t mpidr) +{ + int cpu = mpidr & MPIDR_CPU_MASK; + uint32_t val; + + VERBOSE("Entering SoC powerdn state...\n"); + + tegra_fc_cc4_ctrl(cpu, 0); + + tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, 1); + + val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT; + tegra_fc_prepare_suspend(cpu, val); + + /* overwrite HALT register */ + tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT); +} + +/******************************************************************************* + * Power up the CPU + ******************************************************************************/ +void tegra_fc_cpu_on(int cpu) +{ + tegra_fc_cpu_csr(cpu, FLOWCTRL_CSR_ENABLE); + tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT | FLOWCTRL_HALT_SCLK); +} + +/******************************************************************************* + * Power down the CPU + ******************************************************************************/ +void tegra_fc_cpu_off(int cpu) +{ + uint32_t val; + + /* + * Flow controller powers down the CPU during wfi. The CPU would be + * powered on when it receives any interrupt. + */ + val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG | + FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu); + tegra_fc_cpu_csr(cpu, val); + tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT); + tegra_fc_cc4_ctrl(cpu, 0); +} + +/******************************************************************************* + * Inform the BPMP that we have completed the cluster power up + ******************************************************************************/ +void tegra_fc_lock_active_cluster(void) +{ + uint32_t val; + + val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL); + val |= FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK; + tegra_fc_write_32(FLOWCTRL_BPMP_CLUSTER_CONTROL, val); + val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL); +} + +/******************************************************************************* + * Reset BPMP processor + ******************************************************************************/ +void tegra_fc_reset_bpmp(void) +{ + uint32_t val; + + /* halt BPMP */ + tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, FLOWCTRL_WAITEVENT); + + /* Assert BPMP reset */ + mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_SET, CLK_BPMP_RST); + + /* Restore reset address (stored in PMC_SCRATCH39) */ + val = tegra_pmc_read_32(PMC_SCRATCH39); + mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, val); + while (val != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR)) + ; /* wait till value reaches EVP_BPMP_RESET_VECTOR */ + + /* Wait for 2us before de-asserting the reset signal. */ + udelay(2); + + /* De-assert BPMP reset */ + mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_CLR, CLK_BPMP_RST); + + /* Un-halt BPMP */ + tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, 0); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c new file mode 100644 index 0000000..40d1bab --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +extern void zeromem16(void *mem, unsigned int length); + +#define TEGRA_GPU_RESET_REG_OFFSET 0x28c +#define GPU_RESET_BIT (1 << 24) + +/* Video Memory base and size (live values) */ +static uintptr_t video_mem_base; +static uint64_t video_mem_size; + +/* + * Init SMMU. + */ +void tegra_memctrl_setup(void) +{ + /* + * Setup the Memory controller to allow only secure accesses to + * the TZDRAM carveout + */ + INFO("Configuring SMMU\n"); + + /* allow translations for all MC engines */ + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_1_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_2_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_3_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_4_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + + tegra_mc_write_32(MC_SMMU_ASID_SECURITY_0, MC_SMMU_ASID_SECURITY); + + tegra_mc_write_32(MC_SMMU_TLB_CONFIG_0, MC_SMMU_TLB_CONFIG_0_RESET_VAL); + tegra_mc_write_32(MC_SMMU_PTC_CONFIG_0, MC_SMMU_PTC_CONFIG_0_RESET_VAL); + + /* flush PTC and TLB */ + tegra_mc_write_32(MC_SMMU_PTC_FLUSH_0, MC_SMMU_PTC_FLUSH_ALL); + (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ + tegra_mc_write_32(MC_SMMU_TLB_FLUSH_0, MC_SMMU_TLB_FLUSH_ALL); + + /* enable SMMU */ + tegra_mc_write_32(MC_SMMU_CONFIG_0, + MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE); + (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ + + /* video memory carveout */ + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, video_mem_base); + tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); +} + +/* + * Secure the BL31 DRAM aperture. + * + * phys_base = physical base of TZDRAM aperture + * size_in_bytes = size of aperture in bytes + */ +void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) +{ + /* + * Setup the Memory controller to allow only secure accesses to + * the TZDRAM carveout + */ + INFO("Configuring TrustZone DRAM Memory Carveout\n"); + + tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base); + tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); +} + +static void tegra_clear_videomem(uintptr_t non_overlap_area_start, + unsigned long long non_overlap_area_size) +{ + /* + * Perform cache maintenance to ensure that the non-overlapping area is + * zeroed out. The first invalidation of this range ensures that + * possible evictions of dirty cache lines do not interfere with the + * 'zeromem16' operation. Other CPUs could speculatively prefetch the + * main memory contents of this area between the first invalidation and + * the 'zeromem16' operation. The second invalidation ensures that any + * such cache lines are removed as well. + */ + inv_dcache_range(non_overlap_area_start, non_overlap_area_size); + zeromem16((void *)non_overlap_area_start, non_overlap_area_size); + inv_dcache_range(non_overlap_area_start, non_overlap_area_size); +} + +/* + * Program the Video Memory carveout region + * + * phys_base = physical base of aperture + * size_in_bytes = size of aperture in bytes + */ +void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) +{ + uintptr_t vmem_end_old = video_mem_base + (video_mem_size << 20); + uintptr_t vmem_end_new = phys_base + size_in_bytes; + uint32_t regval; + unsigned long long non_overlap_area_size; + + /* + * The GPU is the user of the Video Memory region. In order to + * transition to the new memory region smoothly, we program the + * new base/size ONLY if the GPU is in reset mode. + */ + regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); + if ((regval & GPU_RESET_BIT) == 0) { + ERROR("GPU not in reset! Video Memory setup failed\n"); + return; + } + + /* + * Setup the Memory controller to restrict CPU accesses to the Video + * Memory region + */ + INFO("Configuring Video Memory Carveout\n"); + + /* + * Configure Memory Controller directly for the first time. + */ + if (video_mem_base == 0) + goto done; + + /* + * Clear the old regions now being exposed. The following cases + * can occur - + * + * 1. clear whole old region (no overlap with new region) + * 2. clear old sub-region below new base + * 3. clear old sub-region above new end + */ + INFO("Cleaning previous Video Memory Carveout\n"); + + disable_mmu_el3(); + if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) { + tegra_clear_videomem(video_mem_base, video_mem_size << 20); + } else { + if (video_mem_base < phys_base) { + non_overlap_area_size = phys_base - video_mem_base; + tegra_clear_videomem(video_mem_base, non_overlap_area_size); + } + if (vmem_end_old > vmem_end_new) { + non_overlap_area_size = vmem_end_old - vmem_end_new; + tegra_clear_videomem(vmem_end_new, non_overlap_area_size); + } + } + enable_mmu_el3(0); + +done: + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, phys_base); + tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); + + /* store new values */ + video_mem_base = phys_base; + video_mem_size = size_in_bytes >> 20; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/drivers/pmc/pmc.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/drivers/pmc/pmc.c new file mode 100644 index 0000000..d48b575 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/drivers/pmc/pmc.c @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* Module IDs used during power ungate procedure */ +static const int pmc_cpu_powergate_id[4] = { + 0, /* CPU 0 */ + 9, /* CPU 1 */ + 10, /* CPU 2 */ + 11 /* CPU 3 */ +}; + +/******************************************************************************* + * Power ungate CPU to start the boot process. CPU reset vectors must be + * populated before calling this function. + ******************************************************************************/ +void tegra_pmc_cpu_on(int cpu) +{ + uint32_t val; + + /* + * Check if CPU is already power ungated + */ + val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); + if (val & (1 << pmc_cpu_powergate_id[cpu])) + return; + + /* + * The PMC deasserts the START bit when it starts the power + * ungate process. Loop till no power toggle is in progress. + */ + do { + val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); + } while (val & PMC_TOGGLE_START); + + /* + * Start the power ungate procedure + */ + val = pmc_cpu_powergate_id[cpu] | PMC_TOGGLE_START; + tegra_pmc_write_32(PMC_PWRGATE_TOGGLE, val); + + /* + * The PMC deasserts the START bit when it starts the power + * ungate process. Loop till powergate START bit is asserted. + */ + do { + val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); + } while (val & (1 << 8)); + + /* loop till the CPU is power ungated */ + do { + val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); + } while ((val & (1 << pmc_cpu_powergate_id[cpu])) == 0); +} + +/******************************************************************************* + * Setup CPU vectors for resume from deep sleep + ******************************************************************************/ +void tegra_pmc_cpu_setup(uint64_t reset_addr) +{ + uint32_t val; + + tegra_pmc_write_32(PMC_SECURE_SCRATCH34, (reset_addr & 0xFFFFFFFF) | 1); + val = reset_addr >> 32; + tegra_pmc_write_32(PMC_SECURE_SCRATCH35, val & 0x7FF); +} + +/******************************************************************************* + * Lock CPU vectors to restrict further writes + ******************************************************************************/ +void tegra_pmc_lock_cpu_vectors(void) +{ + uint32_t val; + + /* lock PMC_SECURE_SCRATCH22 */ + val = tegra_pmc_read_32(PMC_SECURE_DISABLE2); + val |= PMC_SECURE_DISABLE2_WRITE22_ON; + tegra_pmc_write_32(PMC_SECURE_DISABLE2, val); + + /* lock PMC_SECURE_SCRATCH34/35 */ + val = tegra_pmc_read_32(PMC_SECURE_DISABLE3); + val |= (PMC_SECURE_DISABLE3_WRITE34_ON | + PMC_SECURE_DISABLE3_WRITE35_ON); + tegra_pmc_write_32(PMC_SECURE_DISABLE3, val); +} + +/******************************************************************************* + * Restart the system + ******************************************************************************/ +__dead2 void tegra_pmc_system_reset(void) +{ + uint32_t reg; + + reg = tegra_pmc_read_32(PMC_CONFIG); + reg |= 0x10; /* restart */ + tegra_pmc_write_32(PMC_CONFIG, reg); + wfi(); + + ERROR("Tegra System Reset: operation not handled.\n"); + panic(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_bl31_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_bl31_setup.c new file mode 100644 index 0000000..7e2bebe --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Declarations of linker defined symbols which will help us find the layout + * of trusted SRAM + ******************************************************************************/ +extern unsigned long __RO_START__; +extern unsigned long __RO_END__; +extern unsigned long __BL31_END__; + +#if USE_COHERENT_MEM +extern unsigned long __COHERENT_RAM_START__; +extern unsigned long __COHERENT_RAM_END__; +#endif + +extern uint64_t tegra_bl31_phys_base; + +/* + * The next 3 constants identify the extents of the code, RO data region and the + * limit of the BL3-1 image. These addresses are used by the MMU setup code and + * therefore they must be page-aligned. It is the responsibility of the linker + * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_RO_BASE (unsigned long)(&__RO_START__) +#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +#define BL31_END (unsigned long)(&__BL31_END__) + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif + +static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; +static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { + .tzdram_size = (uint64_t)TZDRAM_SIZE +}; + +/******************************************************************************* + * This variable holds the non-secure image entry address + ******************************************************************************/ +extern uint64_t ns_image_entrypoint; + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + if (type == NON_SECURE) + return &bl33_image_ep_info; + + if (type == SECURE) + return &bl32_image_ep_info; + + return NULL; +} + +/******************************************************************************* + * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image + * passes this platform specific information. + ******************************************************************************/ +plat_params_from_bl2_t *bl31_get_plat_params(void) +{ + return &plat_bl31_params_from_bl2; +} + +/******************************************************************************* + * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image + * info. + ******************************************************************************/ +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +{ + plat_params_from_bl2_t *plat_params = + (plat_params_from_bl2_t *)plat_params_from_bl2; + + /* + * Configure the UART port to be used as the console + */ + console_init(TEGRA_BOOT_UART_BASE, TEGRA_BOOT_UART_CLK_IN_HZ, + TEGRA_CONSOLE_BAUDRATE); + + /* Initialise crash console */ + plat_crash_console_init(); + + /* + * Copy BL3-3, BL3-2 entry point information. + * They are stored in Secure RAM, in BL2's address space. + */ + bl33_image_ep_info = *from_bl2->bl33_ep_info; + bl32_image_ep_info = *from_bl2->bl32_ep_info; + + /* + * Parse platform specific parameters - TZDRAM aperture size + */ + if (plat_params) + plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; +} + +/******************************************************************************* + * Initialize the gic, configure the SCR. + ******************************************************************************/ +void bl31_platform_setup(void) +{ + uint32_t tmp_reg; + + /* + * Initialize delay timer + */ + tegra_delay_timer_init(); + + /* + * Setup secondary CPU POR infrastructure. + */ + plat_secondary_setup(); + + /* + * Initial Memory Controller configuration. + */ + tegra_memctrl_setup(); + + /* + * Do initial security configuration to allow DRAM/device access. + */ + tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, + plat_bl31_params_from_bl2.tzdram_size); + + /* Set the next EL to be AArch64 */ + tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; + write_scr(tmp_reg); + + /* Initialize the gic cpu and distributor interfaces */ + tegra_gic_setup(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this only intializes the mmu in a quick and dirty way. + ******************************************************************************/ +void bl31_plat_arch_setup(void) +{ + unsigned long bl31_base_pa = tegra_bl31_phys_base; + unsigned long total_base = bl31_base_pa; + unsigned long total_size = BL32_BASE - BL31_RO_BASE; + unsigned long ro_start = bl31_base_pa; + unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE; + const mmap_region_t *plat_mmio_map = NULL; +#if USE_COHERENT_MEM + unsigned long coh_start, coh_size; +#endif + + /* add memory regions */ + mmap_add_region(total_base, total_base, + total_size, + MT_MEMORY | MT_RW | MT_SECURE); + mmap_add_region(ro_start, ro_start, + ro_size, + MT_MEMORY | MT_RO | MT_SECURE); + +#if USE_COHERENT_MEM + coh_start = total_base + (BL31_COHERENT_RAM_BASE - BL31_RO_BASE); + coh_size = BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE; + + mmap_add_region(coh_start, coh_start, + coh_size, + MT_DEVICE | MT_RW | MT_SECURE); +#endif + + /* add MMIO space */ + plat_mmio_map = plat_get_mmio_map(); + if (plat_mmio_map) + mmap_add(plat_mmio_map); + else + WARN("MMIO map not available\n"); + + /* set up translation tables */ + init_xlat_tables(); + + /* enable the MMU */ + enable_mmu_el3(0); +} + +/******************************************************************************* + * Check if the given NS DRAM range is valid + ******************************************************************************/ +int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) +{ + uint64_t end = base + size_in_bytes - 1; + + /* + * Check if the NS DRAM address is valid + */ + if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) || + (base >= end)) { + ERROR("NS address is out-of-bounds!\n"); + return -EFAULT; + } + + /* + * TZDRAM aperture contains the BL31 and BL32 images, so we need + * to check if the NS DRAM range overlaps the TZDRAM aperture. + */ + if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { + ERROR("NS address overlaps TZDRAM!\n"); + return -ENOTSUP; + } + + /* valid NS address */ + return 0; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_common.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_common.mk new file mode 100644 index 0000000..e1c0d84 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_common.mk @@ -0,0 +1,63 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +CRASH_REPORTING := 1 +$(eval $(call add_define,CRASH_REPORTING)) + +ASM_ASSERTION := 1 +$(eval $(call add_define,ASM_ASSERTION)) + +USE_COHERENT_MEM := 0 + +PLAT_INCLUDES := -Iplat/nvidia/tegra/include/drivers \ + -Iplat/nvidia/tegra/include \ + -Iplat/nvidia/tegra/include/${TARGET_SOC} + +PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \ + plat/common/aarch64/plat_common.c + +COMMON_DIR := plat/nvidia/tegra/common + +BL31_SOURCES += drivers/arm/gic/gic_v2.c \ + drivers/arm/gic/gic_v3.c \ + drivers/console/console.S \ + drivers/delay_timer/delay_timer.c \ + drivers/ti/uart/16550_console.S \ + plat/common/aarch64/platform_mp_stack.S \ + ${COMMON_DIR}/aarch64/tegra_helpers.S \ + ${COMMON_DIR}/drivers/memctrl/memctrl.c \ + ${COMMON_DIR}/drivers/pmc/pmc.c \ + ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ + ${COMMON_DIR}/tegra_bl31_setup.c \ + ${COMMON_DIR}/tegra_delay_timer.c \ + ${COMMON_DIR}/tegra_gic.c \ + ${COMMON_DIR}/tegra_pm.c \ + ${COMMON_DIR}/tegra_sip_calls.c \ + ${COMMON_DIR}/tegra_topology.c diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_delay_timer.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_delay_timer.c new file mode 100644 index 0000000..e1f6ede --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_delay_timer.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +static uint32_t tegra_timerus_get_value(void) +{ + return mmio_read_32(TEGRA_TMRUS_BASE); +} + +static const timer_ops_t tegra_timer_ops = { + .get_timer_value = tegra_timerus_get_value, + .clk_mult = 1, + .clk_div = 1, +}; + +/* + * Initialise the on-chip free rolling us counter as the delay + * timer. + */ +void tegra_delay_timer_init(void) +{ + timer_init(&tegra_timer_ops); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_gic.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_gic.c new file mode 100644 index 0000000..ee12975 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_gic.c @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Value used to initialize Non-Secure IRQ priorities four at a time */ +#define GICD_IPRIORITYR_DEF_VAL \ + (GIC_HIGHEST_NS_PRIORITY | \ + (GIC_HIGHEST_NS_PRIORITY << 8) | \ + (GIC_HIGHEST_NS_PRIORITY << 16) | \ + (GIC_HIGHEST_NS_PRIORITY << 24)) + +/******************************************************************************* + * Place the cpu interface in a state where it can never make a cpu exit wfi as + * as result of an asserted interrupt. This is critical for powering down a cpu + ******************************************************************************/ +void tegra_gic_cpuif_deactivate(void) +{ + unsigned int val; + + /* Disable secure, non-secure interrupts and disable their bypass */ + val = gicc_read_ctlr(TEGRA_GICC_BASE); + val &= ~(ENABLE_GRP0 | ENABLE_GRP1); + val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; + val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; + gicc_write_ctlr(TEGRA_GICC_BASE, val); +} + +/******************************************************************************* + * Enable secure interrupts and set the priority mask register to allow all + * interrupts to trickle in. + ******************************************************************************/ +static void tegra_gic_cpuif_setup(unsigned int gicc_base) +{ + unsigned int val; + + val = ENABLE_GRP0 | ENABLE_GRP1 | FIQ_EN | FIQ_BYP_DIS_GRP0; + val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; + + gicc_write_ctlr(gicc_base, val); + gicc_write_pmr(gicc_base, GIC_PRI_MASK); +} + +/******************************************************************************* + * Per cpu gic distributor setup which will be done by all cpus after a cold + * boot/hotplug. This marks out the secure interrupts & enables them. + ******************************************************************************/ +static void tegra_gic_pcpu_distif_setup(unsigned int gicd_base) +{ + unsigned int index, sec_ppi_sgi_mask = 0; + + assert(gicd_base); + + /* Setup PPI priorities doing four at a time */ + for (index = 0; index < 32; index += 4) { + gicd_write_ipriorityr(gicd_base, index, + GICD_IPRIORITYR_DEF_VAL); + } + + /* + * Invert the bitmask to create a mask for non-secure PPIs and + * SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will + * update the GICR_IGROUPR0 as well in case we are running on a GICv3 + * system. This is critical if GICD_CTLR.ARE_NS=1. + */ + gicd_write_igroupr(gicd_base, 0, ~sec_ppi_sgi_mask); +} + +/******************************************************************************* + * Global gic distributor setup which will be done by the primary cpu after a + * cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them. + * It then enables the secure GIC distributor interface. + ******************************************************************************/ +static void tegra_gic_distif_setup(unsigned int gicd_base) +{ + unsigned int index, num_ints; + + /* + * Mark out non-secure interrupts. Calculate number of + * IGROUPR registers to consider. Will be equal to the + * number of IT_LINES + */ + num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK; + num_ints = (num_ints + 1) << 5; + for (index = MIN_SPI_ID; index < num_ints; index += 32) + gicd_write_igroupr(gicd_base, index, ~0); + + /* Setup SPI priorities doing four at a time */ + for (index = MIN_SPI_ID; index < num_ints; index += 4) { + gicd_write_ipriorityr(gicd_base, index, + GICD_IPRIORITYR_DEF_VAL); + } + + /* + * Configure the SGI and PPI. This is done in a separated function + * because each CPU is responsible for initializing its own private + * interrupts. + */ + tegra_gic_pcpu_distif_setup(gicd_base); + + /* enable distributor */ + gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1); +} + +void tegra_gic_setup(void) +{ + tegra_gic_cpuif_setup(TEGRA_GICC_BASE); + tegra_gic_distif_setup(TEGRA_GICD_BASE); +} + +/******************************************************************************* + * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. + * The interrupt controller knows which pin/line it uses to signal a type of + * interrupt. This function provides a common implementation of + * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use + * across platforms. It lets the interrupt management framework determine + * for a type of interrupt and security state, which line should be used in the + * SCR_EL3 to control its routing to EL3. The interrupt line is represented as + * the bit position of the IRQ or FIQ bit in the SCR_EL3. + ******************************************************************************/ +uint32_t tegra_gic_interrupt_type_to_line(uint32_t type, + uint32_t security_state) +{ + assert(type == INTR_TYPE_S_EL1 || + type == INTR_TYPE_EL3 || + type == INTR_TYPE_NS); + + assert(sec_state_is_valid(security_state)); + + /* + * We ignore the security state parameter under the assumption that + * both normal and secure worlds are using ARM GICv2. This parameter + * will be used when the secure world starts using GICv3. + */ +#if ARM_GIC_ARCH == 2 + return gicv2_interrupt_type_to_line(TEGRA_GICC_BASE, type); +#else +#error "Invalid ARM GIC architecture version specified for platform port" +#endif /* ARM_GIC_ARCH */ +} + +#if ARM_GIC_ARCH == 2 +/******************************************************************************* + * This function returns the type of the highest priority pending interrupt at + * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no + * interrupt pending. + ******************************************************************************/ +uint32_t tegra_gic_get_pending_interrupt_type(void) +{ + uint32_t id; + + id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK; + + /* Assume that all secure interrupts are S-EL1 interrupts */ + if (id < 1022) + return INTR_TYPE_S_EL1; + + if (id == GIC_SPURIOUS_INTERRUPT) + return INTR_TYPE_INVAL; + + return INTR_TYPE_NS; +} + +/******************************************************************************* + * This function returns the id of the highest priority pending interrupt at + * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no + * interrupt pending. + ******************************************************************************/ +uint32_t tegra_gic_get_pending_interrupt_id(void) +{ + uint32_t id; + + id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK; + + if (id < 1022) + return id; + + if (id == 1023) + return INTR_ID_UNAVAILABLE; + + /* + * Find out which non-secure interrupt it is under the assumption that + * the GICC_CTLR.AckCtl bit is 0. + */ + return gicc_read_ahppir(TEGRA_GICC_BASE) & INT_ID_MASK; +} + +/******************************************************************************* + * This functions reads the GIC cpu interface Interrupt Acknowledge register + * to start handling the pending interrupt. It returns the contents of the IAR. + ******************************************************************************/ +uint32_t tegra_gic_acknowledge_interrupt(void) +{ + return gicc_read_IAR(TEGRA_GICC_BASE); +} + +/******************************************************************************* + * This functions writes the GIC cpu interface End Of Interrupt register with + * the passed value to finish handling the active interrupt + ******************************************************************************/ +void tegra_gic_end_of_interrupt(uint32_t id) +{ + gicc_write_EOIR(TEGRA_GICC_BASE, id); +} + +/******************************************************************************* + * This function returns the type of the interrupt id depending upon the group + * this interrupt has been configured under by the interrupt controller i.e. + * group0 or group1. + ******************************************************************************/ +uint32_t tegra_gic_get_interrupt_type(uint32_t id) +{ + uint32_t group; + + group = gicd_get_igroupr(TEGRA_GICD_BASE, id); + + /* Assume that all secure interrupts are S-EL1 interrupts */ + if (group == GRP0) + return INTR_TYPE_S_EL1; + else + return INTR_TYPE_NS; +} + +#else +#error "Invalid ARM GIC architecture version specified for platform port" +#endif /* ARM_GIC_ARCH */ + +uint32_t plat_ic_get_pending_interrupt_id(void) +{ + return tegra_gic_get_pending_interrupt_id(); +} + +uint32_t plat_ic_get_pending_interrupt_type(void) +{ + return tegra_gic_get_pending_interrupt_type(); +} + +uint32_t plat_ic_acknowledge_interrupt(void) +{ + return tegra_gic_acknowledge_interrupt(); +} + +uint32_t plat_ic_get_interrupt_type(uint32_t id) +{ + return tegra_gic_get_interrupt_type(id); +} + +void plat_ic_end_of_interrupt(uint32_t id) +{ + tegra_gic_end_of_interrupt(id); +} + +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state) +{ + return tegra_gic_interrupt_type_to_line(type, security_state); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_pm.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_pm.c new file mode 100644 index 0000000..87f7240 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_pm.c @@ -0,0 +1,339 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern uint64_t tegra_bl31_phys_base; +extern uint64_t sec_entry_point[PLATFORM_CORE_COUNT]; +static int system_suspended; + +/* + * The following platform setup functions are weakly defined. They + * provide typical implementations that will be overridden by a SoC. + */ +#pragma weak tegra_soc_prepare_cpu_suspend +#pragma weak tegra_soc_prepare_cpu_on +#pragma weak tegra_soc_prepare_cpu_off +#pragma weak tegra_soc_prepare_cpu_on_finish + +int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl) +{ + return PSCI_E_NOT_SUPPORTED; +} + +int tegra_soc_prepare_cpu_on(unsigned long mpidr) +{ + return PSCI_E_SUCCESS; +} + +int tegra_soc_prepare_cpu_off(unsigned long mpidr) +{ + return PSCI_E_SUCCESS; +} + +int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr) +{ + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * Track system suspend entry. + ******************************************************************************/ +void tegra_pm_system_suspend_entry(void) +{ + system_suspended = 1; +} + +/******************************************************************************* + * Track system suspend exit. + ******************************************************************************/ +void tegra_pm_system_suspend_exit(void) +{ + system_suspended = 0; +} + +/******************************************************************************* + * Get the system suspend state. + ******************************************************************************/ +int tegra_system_suspended(void) +{ + return system_suspended; +} + +/******************************************************************************* + * Handler called when an affinity instance is about to enter standby. + ******************************************************************************/ +void tegra_affinst_standby(unsigned int power_state) +{ + /* + * Enter standby state + * dsb is good practice before using wfi to enter low power states + */ + dsb(); + wfi(); +} + +/******************************************************************************* + * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` + * call to get the `power_state` parameter. This allows the platform to encode + * the appropriate State-ID field within the `power_state` parameter which can + * be utilized in `affinst_suspend()` to suspend to system affinity level. +******************************************************************************/ +unsigned int tegra_get_sys_suspend_power_state(void) +{ + unsigned int power_state; + + power_state = psci_make_powerstate(PLAT_SYS_SUSPEND_STATE_ID, + PSTATE_TYPE_POWERDOWN, MPIDR_AFFLVL2); + + return power_state; +} + +/******************************************************************************* + * Handler called to check the validity of the power state parameter. + ******************************************************************************/ +int32_t tegra_validate_power_state(unsigned int power_state) +{ + return tegra_soc_validate_power_state(power_state); +} + +/******************************************************************************* + * Handler called when an affinity instance is about to be turned on. The + * level and mpidr determine the affinity instance. + ******************************************************************************/ +int tegra_affinst_on(unsigned long mpidr, + unsigned long sec_entrypoint, + unsigned int afflvl, + unsigned int state) +{ + int cpu = mpidr & MPIDR_CPU_MASK; + + /* + * Support individual CPU power on only. + */ + if (afflvl > MPIDR_AFFLVL0) + return PSCI_E_SUCCESS; + + /* + * Flush entrypoint variable to PoC since it will be + * accessed after a reset with the caches turned off. + */ + sec_entry_point[cpu] = sec_entrypoint; + flush_dcache_range((uint64_t)&sec_entry_point[cpu], sizeof(uint64_t)); + + return tegra_soc_prepare_cpu_on(mpidr); +} + +/******************************************************************************* + * Handler called when an affinity instance is about to be turned off. The + * level determines the affinity instance. The 'state' arg. allows the + * platform to decide whether the cluster is being turned off and take apt + * actions. + * + * CAUTION: This function is called with coherent stacks so that caches can be + * turned off, flushed and coherency disabled. There is no guarantee that caches + * will remain turned on across calls to this function as each affinity level is + * dealt with. So do not write & read global variables across calls. It will be + * wise to do flush a write to the global to prevent unpredictable results. + ******************************************************************************/ +void tegra_affinst_off(unsigned int afflvl, unsigned int state) +{ + /* + * Support individual CPU power off only. + */ + if (afflvl > MPIDR_AFFLVL0) + return; + + tegra_soc_prepare_cpu_off(read_mpidr()); +} + +/******************************************************************************* + * Handler called when an affinity instance is about to be suspended. The + * level and mpidr determine the affinity instance. The 'state' arg. allows the + * platform to decide whether the cluster is being turned off and take apt + * actions. + * + * CAUTION: This function is called with coherent stacks so that caches can be + * turned off, flushed and coherency disabled. There is no guarantee that caches + * will remain turned on across calls to this function as each affinity level is + * dealt with. So do not write & read global variables across calls. It will be + * wise to flush a write to the global variable, to prevent unpredictable + * results. + ******************************************************************************/ +void tegra_affinst_suspend(unsigned long sec_entrypoint, + unsigned int afflvl, + unsigned int state) +{ + int id = psci_get_suspend_stateid(); + int cpu = read_mpidr() & MPIDR_CPU_MASK; + + if (afflvl > PLATFORM_MAX_AFFLVL) + return; + + /* + * Flush entrypoint variable to PoC since it will be + * accessed after a reset with the caches turned off. + */ + sec_entry_point[cpu] = sec_entrypoint; + flush_dcache_range((uint64_t)&sec_entry_point[cpu], sizeof(uint64_t)); + + tegra_soc_prepare_cpu_suspend(id, afflvl); + + /* disable GICC */ + tegra_gic_cpuif_deactivate(); +} + +/******************************************************************************* + * Handler called when an affinity instance has just been powered on after + * being turned off earlier. The level determines the affinity instance. + * The 'state' arg. allows the platform to decide whether the cluster was + * turned off prior to wakeup and do what's necessary to set it up. + ******************************************************************************/ +void tegra_affinst_on_finish(unsigned int afflvl, unsigned int state) +{ + plat_params_from_bl2_t *plat_params; + + /* + * Support individual CPU power on only. + */ + if (afflvl > MPIDR_AFFLVL0) + return; + + /* + * Initialize the GIC cpu and distributor interfaces + */ + tegra_gic_setup(); + + /* + * Check if we are exiting from deep sleep. + */ + if (tegra_system_suspended()) { + + /* + * Lock scratch registers which hold the CPU vectors. + */ + tegra_pmc_lock_cpu_vectors(); + + /* + * SMMU configuration. + */ + tegra_memctrl_setup(); + + /* + * Security configuration to allow DRAM/device access. + */ + plat_params = bl31_get_plat_params(); + tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, + plat_params->tzdram_size); + } + + /* + * Reset hardware settings. + */ + tegra_soc_prepare_cpu_on_finish(read_mpidr()); +} + +/******************************************************************************* + * Handler called when an affinity instance has just been powered on after + * having been suspended earlier. The level and mpidr determine the affinity + * instance. + ******************************************************************************/ +void tegra_affinst_suspend_finish(unsigned int afflvl, unsigned int state) +{ + if (afflvl == MPIDR_AFFLVL0) + tegra_affinst_on_finish(afflvl, state); +} + +/******************************************************************************* + * Handler called when the system wants to be powered off + ******************************************************************************/ +__dead2 void tegra_system_off(void) +{ + ERROR("Tegra System Off: operation not handled.\n"); + panic(); +} + +/******************************************************************************* + * Handler called when the system wants to be restarted. + ******************************************************************************/ +__dead2 void tegra_system_reset(void) +{ + /* + * Program the PMC in order to restart the system. + */ + tegra_pmc_system_reset(); +} + +/******************************************************************************* + * Export the platform handlers to enable psci to invoke them + ******************************************************************************/ +static const plat_pm_ops_t tegra_plat_pm_ops = { + .affinst_standby = tegra_affinst_standby, + .affinst_on = tegra_affinst_on, + .affinst_off = tegra_affinst_off, + .affinst_suspend = tegra_affinst_suspend, + .affinst_on_finish = tegra_affinst_on_finish, + .affinst_suspend_finish = tegra_affinst_suspend_finish, + .system_off = tegra_system_off, + .system_reset = tegra_system_reset, + .validate_power_state = tegra_validate_power_state, + .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state +}; + +/******************************************************************************* + * Export the platform specific power ops & initialize the fvp power controller + ******************************************************************************/ +int platform_setup_pm(const plat_pm_ops_t **plat_ops) +{ + /* + * Reset hardware settings. + */ + tegra_soc_prepare_cpu_on_finish(read_mpidr()); + + /* + * Initialize PM ops struct + */ + *plat_ops = &tegra_plat_pm_ops; + + return 0; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_sip_calls.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_sip_calls.c new file mode 100644 index 0000000..de36a3c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_sip_calls.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NS_SWITCH_AARCH32 1 +#define SCR_RW_BITPOS __builtin_ctz(SCR_RW_BIT) + +/******************************************************************************* + * Tegra SiP SMCs + ******************************************************************************/ +#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 +#define TEGRA_SIP_AARCH_SWITCH 0x82000004 + +/******************************************************************************* + * SPSR settings for AARCH32/AARCH64 modes + ******************************************************************************/ +#define SPSR32 SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, \ + DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT) +#define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS) + +/******************************************************************************* + * This function is responsible for handling all SiP calls from the NS world + ******************************************************************************/ +uint64_t tegra_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + uint32_t ns; + int err; + + /* Determine which security state this SMC originated from */ + ns = is_caller_non_secure(flags); + if (!ns) + SMC_RET1(handle, SMC_UNK); + + switch (smc_fid) { + + case TEGRA_SIP_NEW_VIDEOMEM_REGION: + + /* clean up the high bits */ + x1 = (uint32_t)x1; + x2 = (uint32_t)x2; + + /* + * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) + * or falls outside of the valid DRAM range + */ + err = bl31_check_ns_address(x1, x2); + if (err) + SMC_RET1(handle, err); + + /* + * Check if Video Memory is aligned to 1MB. + */ + if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { + ERROR("Unaligned Video Memory base address!\n"); + SMC_RET1(handle, -ENOTSUP); + } + + /* new video memory carveout settings */ + tegra_memctrl_videomem_setup(x1, x2); + + SMC_RET1(handle, 0); + break; + + case TEGRA_SIP_AARCH_SWITCH: + + /* clean up the high bits */ + x1 = (uint32_t)x1; + x2 = (uint32_t)x2; + + if (!x1 || x2 > NS_SWITCH_AARCH32) { + ERROR("%s: invalid parameters\n", __func__); + SMC_RET1(handle, SMC_UNK); + } + + /* x1 = ns entry point */ + cm_set_elr_spsr_el3(NON_SECURE, x1, + (x2 == NS_SWITCH_AARCH32) ? SPSR32 : SPSR64); + + /* switch NS world mode */ + cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2); + + INFO("CPU switched to AARCH%s mode\n", + (x2 == NS_SWITCH_AARCH32) ? "32" : "64"); + SMC_RET1(handle, 0); + break; + + default: + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + break; + } + + SMC_RET1(handle, SMC_UNK); +} + +/* Define a runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + tegra_sip_fast, + + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + NULL, + tegra_sip_handler +); diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_topology.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_topology.c new file mode 100644 index 0000000..220e697 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/common/tegra_topology.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform to allow the former to detect the platform + * topology. psci queries the platform to determine how many affinity instances + * are present at a particular level for a given mpidr. + ******************************************************************************/ +unsigned int plat_get_aff_count(unsigned int aff_lvl, + unsigned long mpidr) +{ + switch (aff_lvl) { + case MPIDR_AFFLVL2: + /* Last supported affinity level */ + return 1; + + case MPIDR_AFFLVL1: + /* Return # of clusters */ + return PLATFORM_CLUSTER_COUNT; + + case MPIDR_AFFLVL0: + /* # of cpus per cluster */ + return PLATFORM_MAX_CPUS_PER_CLUSTER; + + default: + return PSCI_AFF_ABSENT; + } +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform to allow the former to detect the state of a + * affinity instance in the platform topology. psci queries the platform to + * determine whether an affinity instance is present or absent. + ******************************************************************************/ +unsigned int plat_get_aff_state(unsigned int aff_lvl, + unsigned long mpidr) +{ + return (aff_lvl <= MPIDR_AFFLVL2) ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/drivers/flowctrl.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/drivers/flowctrl.h new file mode 100644 index 0000000..8bc821d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/drivers/flowctrl.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FLOWCTRL_H__ +#define __FLOWCTRL_H__ + +#include +#include + +#define FLOWCTRL_HALT_CPU0_EVENTS 0x0 +#define FLOWCTRL_WAITEVENT (2 << 29) +#define FLOWCTRL_WAIT_FOR_INTERRUPT (4 << 29) +#define FLOWCTRL_JTAG_RESUME (1 << 28) +#define FLOWCTRL_HALT_SCLK (1 << 27) +#define FLOWCTRL_HALT_LIC_IRQ (1 << 11) +#define FLOWCTRL_HALT_LIC_FIQ (1 << 10) +#define FLOWCTRL_HALT_GIC_IRQ (1 << 9) +#define FLOWCTRL_HALT_GIC_FIQ (1 << 8) +#define FLOWCTRL_HALT_BPMP_EVENTS 0x4 +#define FLOWCTRL_CPU0_CSR 0x8 +#define FLOW_CTRL_CSR_PWR_OFF_STS (1 << 16) +#define FLOWCTRL_CSR_INTR_FLAG (1 << 15) +#define FLOWCTRL_CSR_EVENT_FLAG (1 << 14) +#define FLOWCTRL_CSR_IMMEDIATE_WAKE (1 << 3) +#define FLOWCTRL_CSR_ENABLE (1 << 0) +#define FLOWCTRL_HALT_CPU1_EVENTS 0x14 +#define FLOWCTRL_CPU1_CSR 0x18 +#define FLOWCTRL_CC4_CORE0_CTRL 0x6c +#define FLOWCTRL_WAIT_WFI_BITMAP 0x100 +#define FLOWCTRL_L2_FLUSH_CONTROL 0x94 +#define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98 +#define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1 << 2) + +#define FLOWCTRL_ENABLE_EXT 12 +#define FLOWCTRL_ENABLE_EXT_MASK 3 +#define FLOWCTRL_PG_CPU_NONCPU 0x1 +#define FLOWCTRL_TURNOFF_CPURAIL 0x2 + +static inline uint32_t tegra_fc_read_32(uint32_t off) +{ + return mmio_read_32(TEGRA_FLOWCTRL_BASE + off); +} + +static inline void tegra_fc_write_32(uint32_t off, uint32_t val) +{ + mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val); +} + +void tegra_fc_cpu_idle(uint32_t mpidr); +void tegra_fc_cluster_idle(uint32_t midr); +void tegra_fc_cluster_powerdn(uint32_t midr); +void tegra_fc_soc_powerdn(uint32_t midr); +void tegra_fc_cpu_on(int cpu); +void tegra_fc_cpu_off(int cpu); +void tegra_fc_lock_active_cluster(void); +void tegra_fc_reset_bpmp(void); + +#endif /* __FLOWCTRL_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/drivers/memctrl.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/drivers/memctrl.h new file mode 100644 index 0000000..26c8057 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/drivers/memctrl.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MEMCTRL_H__ +#define __MEMCTRL_H__ + +#include +#include + +/* SMMU registers */ +#define MC_SMMU_CONFIG_0 0x10 +#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0 +#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1 +#define MC_SMMU_TLB_CONFIG_0 0x14 +#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010 +#define MC_SMMU_PTC_CONFIG_0 0x18 +#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f +#define MC_SMMU_TLB_FLUSH_0 0x30 +#define TLB_FLUSH_VA_MATCH_ALL 0 +#define TLB_FLUSH_ASID_MATCH_DISABLE 0 +#define TLB_FLUSH_ASID_MATCH_SHIFT 31 +#define MC_SMMU_TLB_FLUSH_ALL \ + (TLB_FLUSH_VA_MATCH_ALL | \ + (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) +#define MC_SMMU_PTC_FLUSH_0 0x34 +#define MC_SMMU_PTC_FLUSH_ALL 0 +#define MC_SMMU_ASID_SECURITY_0 0x38 +#define MC_SMMU_ASID_SECURITY 0 +#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228 +#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c +#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230 +#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234 +#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 +#define MC_SMMU_TRANSLATION_ENABLE (~0) + +/* TZDRAM carveout configuration registers */ +#define MC_SECURITY_CFG0_0 0x70 +#define MC_SECURITY_CFG1_0 0x74 + +/* Video Memory carveout configuration registers */ +#define MC_VIDEO_PROTECT_BASE 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c + +static inline uint32_t tegra_mc_read_32(uint32_t off) +{ + return mmio_read_32(TEGRA_MC_BASE + off); +} + +static inline void tegra_mc_write_32(uint32_t off, uint32_t val) +{ + mmio_write_32(TEGRA_MC_BASE + off, val); +} + +void tegra_memctrl_setup(void); +void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes); +void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes); + +#endif /* __MEMCTRL_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/drivers/pmc.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/drivers/pmc.h new file mode 100644 index 0000000..c0616d0 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/drivers/pmc.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PMC_H__ +#define __PMC_H__ + +#include +#include + +#define PMC_CONFIG 0x0 +#define PMC_PWRGATE_STATUS 0x38 +#define PMC_PWRGATE_TOGGLE 0x30 +#define PMC_TOGGLE_START 0x100 +#define PMC_SCRATCH39 0x138 +#define PMC_SECURE_DISABLE2 0x2c4 +#define PMC_SECURE_DISABLE2_WRITE22_ON (1 << 28) +#define PMC_SECURE_SCRATCH22 0x338 +#define PMC_SECURE_DISABLE3 0x2d8 +#define PMC_SECURE_DISABLE3_WRITE34_ON (1 << 20) +#define PMC_SECURE_DISABLE3_WRITE35_ON (1 << 22) +#define PMC_SECURE_SCRATCH34 0x368 +#define PMC_SECURE_SCRATCH35 0x36c + +static inline uint32_t tegra_pmc_read_32(uint32_t off) +{ + return mmio_read_32(TEGRA_PMC_BASE + off); +} + +static inline void tegra_pmc_write_32(uint32_t off, uint32_t val) +{ + mmio_write_32(TEGRA_PMC_BASE + off, val); +} + +void tegra_pmc_cpu_setup(uint64_t reset_addr); +void tegra_pmc_lock_cpu_vectors(void); +void tegra_pmc_cpu_on(int cpu); +__dead2 void tegra_pmc_system_reset(void); + +#endif /* __PMC_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/plat_macros.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/plat_macros.S new file mode 100644 index 0000000..0868b41 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/plat_macros.S @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_MACROS_S__ +#define __PLAT_MACROS_S__ + +#include +#include + +.section .rodata.gic_reg_name, "aS" +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + +/* --------------------------------------------- + * The below macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL31. + * --------------------------------------------- + */ +.macro plat_print_gic_regs + mov_imm x16, TEGRA_GICC_BASE + cbz x16, 1f + /* gicc base address is now in x16 */ + adr x6, gicc_regs /* Load the gicc reg list to x6 */ + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x16, #GICC_HPPIR] + ldr w9, [x16, #GICC_AHPPIR] + ldr w10, [x16, #GICC_CTLR] + /* Store to the crash buf and print to cosole */ + bl str_in_crash_buf_print + + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +2: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq 1f + bl asm_print_hex + adr x4, spacer + bl asm_print_str + ldr x4, [x7], #8 + bl asm_print_hex + adr x4, newline + bl asm_print_str + b 2b +1: +.endm + +/* ------------------------------------------------ + * The below required platform porting macro prints + * out relevant interconnect registers whenever an + * unhandled exception is taken in BL3-1. + * ------------------------------------------------ + */ +.macro plat_print_interconnect_regs + nop +.endm + +#endif /* __PLAT_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/platform_def.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/platform_def.h new file mode 100644 index 0000000..c59e2be --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/platform_def.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include +#include + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#if DEBUG_XLAT_TABLE +#define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL31 +#define PLATFORM_STACK_SIZE 0x400 +#endif + +#define TEGRA_PRIMARY_CPU 0x0 + +#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ + PLATFORM_MAX_CPUS_PER_CLUSTER) +#define PLATFORM_NUM_AFFS (PLATFORM_CORE_COUNT + \ + PLATFORM_CLUSTER_COUNT + 1) + +/******************************************************************************* + * Platform console related constants + ******************************************************************************/ +#define TEGRA_CONSOLE_BAUDRATE 115200 +#define TEGRA_BOOT_UART_CLK_IN_HZ 408000000 + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +/* Size of trusted dram */ +#define TZDRAM_SIZE 0x00400000 +#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +#define BL31_SIZE 0x20000 +#define BL31_BASE TZDRAM_BASE +#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) +#define BL32_BASE (TZDRAM_BASE + BL31_SIZE) +#define BL32_LIMIT TZDRAM_END + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define ADDR_SPACE_SIZE (1ull << 32) +#define MAX_XLAT_TABLES 3 +#define MAX_MMAP_REGIONS 8 + +/******************************************************************************* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/t132/tegra_def.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/t132/tegra_def.h new file mode 100644 index 0000000..2fb9ed7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/t132/tegra_def.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TEGRA_DEF_H__ +#define __TEGRA_DEF_H__ + +#include + +/******************************************************************************* + * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` + * call as the `state-id` field in the 'power state' parameter. + ******************************************************************************/ +#define PLAT_SYS_SUSPEND_STATE_ID 0xD + +/******************************************************************************* + * GIC memory map + ******************************************************************************/ +#define TEGRA_GICD_BASE 0x50041000 +#define TEGRA_GICC_BASE 0x50042000 + +/******************************************************************************* + * Tegra micro-seconds timer constants + ******************************************************************************/ +#define TEGRA_TMRUS_BASE 0x60005010 + +/******************************************************************************* + * Tegra Clock and Reset Controller constants + ******************************************************************************/ +#define TEGRA_CAR_RESET_BASE 0x60006000 + +/******************************************************************************* + * Tegra Flow Controller constants + ******************************************************************************/ +#define TEGRA_FLOWCTRL_BASE 0x60007000 + +/******************************************************************************* + * Tegra Secure Boot Controller constants + ******************************************************************************/ +#define TEGRA_SB_BASE 0x6000C200 + +/******************************************************************************* + * Tegra Exception Vectors constants + ******************************************************************************/ +#define TEGRA_EVP_BASE 0x6000F000 + +/******************************************************************************* + * Tegra Power Mgmt Controller constants + ******************************************************************************/ +#define TEGRA_PMC_BASE 0x7000E400 + +/******************************************************************************* + * Tegra Memory Controller constants + ******************************************************************************/ +#define TEGRA_MC_BASE 0x70019000 + +#endif /* __TEGRA_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/t210/tegra_def.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/t210/tegra_def.h new file mode 100644 index 0000000..750e6e3 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/t210/tegra_def.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TEGRA_DEF_H__ +#define __TEGRA_DEF_H__ + +#include + +/******************************************************************************* + * Power down state IDs + ******************************************************************************/ +#define PSTATE_ID_CORE_POWERDN 7 +#define PSTATE_ID_CLUSTER_IDLE 16 +#define PSTATE_ID_CLUSTER_POWERDN 17 +#define PSTATE_ID_SOC_POWERDN 27 + +/******************************************************************************* + * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` + * call as the `state-id` field in the 'power state' parameter. + ******************************************************************************/ +#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN + +/******************************************************************************* + * Implementation defined ACTLR_EL3 bit definitions + ******************************************************************************/ +#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) +#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) +#define ACTLR_EL3_L2CTLR_BIT (1 << 4) +#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) +#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) +#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ + ACTLR_EL3_L2ECTLR_BIT | \ + ACTLR_EL3_L2CTLR_BIT | \ + ACTLR_EL3_CPUECTLR_BIT | \ + ACTLR_EL3_CPUACTLR_BIT) + +/******************************************************************************* + * GIC memory map + ******************************************************************************/ +#define TEGRA_GICD_BASE 0x50041000 +#define TEGRA_GICC_BASE 0x50042000 + +/******************************************************************************* + * Tegra Memory Select Switch Controller constants + ******************************************************************************/ +#define TEGRA_MSELECT_BASE 0x50060000 + +#define MSELECT_CONFIG 0x0 +#define ENABLE_WRAP_INCR_MASTER2_BIT (1 << 29) +#define ENABLE_WRAP_INCR_MASTER1_BIT (1 << 28) +#define ENABLE_WRAP_INCR_MASTER0_BIT (1 << 27) +#define UNSUPPORTED_TX_ERR_MASTER2_BIT (1 << 25) +#define UNSUPPORTED_TX_ERR_MASTER1_BIT (1 << 24) +#define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ + UNSUPPORTED_TX_ERR_MASTER1_BIT) +#define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ + ENABLE_WRAP_INCR_MASTER1_BIT | \ + ENABLE_WRAP_INCR_MASTER0_BIT) + +/******************************************************************************* + * Tegra micro-seconds timer constants + ******************************************************************************/ +#define TEGRA_TMRUS_BASE 0x60005010 + +/******************************************************************************* + * Tegra Clock and Reset Controller constants + ******************************************************************************/ +#define TEGRA_CAR_RESET_BASE 0x60006000 + +/******************************************************************************* + * Tegra Flow Controller constants + ******************************************************************************/ +#define TEGRA_FLOWCTRL_BASE 0x60007000 + +/******************************************************************************* + * Tegra Secure Boot Controller constants + ******************************************************************************/ +#define TEGRA_SB_BASE 0x6000C200 + +/******************************************************************************* + * Tegra Exception Vectors constants + ******************************************************************************/ +#define TEGRA_EVP_BASE 0x6000F000 + +/******************************************************************************* + * Tegra Power Mgmt Controller constants + ******************************************************************************/ +#define TEGRA_PMC_BASE 0x7000E400 + +/******************************************************************************* + * Tegra Memory Controller constants + ******************************************************************************/ +#define TEGRA_MC_BASE 0x70019000 + +#endif /* __TEGRA_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/tegra_private.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/tegra_private.h new file mode 100644 index 0000000..952e2d8 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/include/tegra_private.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TEGRA_PRIVATE_H__ +#define __TEGRA_PRIVATE_H__ + +#include +#include + +/******************************************************************************* + * Tegra DRAM memory base address + ******************************************************************************/ +#define TEGRA_DRAM_BASE 0x80000000 +#define TEGRA_DRAM_END 0x27FFFFFFF + +typedef struct plat_params_from_bl2 { + uint64_t tzdram_size; +} plat_params_from_bl2_t; + +/* Declarations for plat_psci_handlers.c */ +int32_t tegra_soc_validate_power_state(unsigned int power_state); + +/* Declarations for plat_setup.c */ +const mmap_region_t *plat_get_mmio_map(void); +uint64_t plat_get_syscnt_freq(void); + +/* Declarations for plat_secondary.c */ +void plat_secondary_setup(void); +int plat_lock_cpu_vectors(void); + +/* Declarations for tegra_gic.c */ +void tegra_gic_setup(void); +void tegra_gic_cpuif_deactivate(void); + +/* Declarations for tegra_security.c */ +void tegra_security_setup(void); +void tegra_security_setup_videomem(uintptr_t base, uint64_t size); + +/* Declarations for tegra_pm.c */ +void tegra_pm_system_suspend_entry(void); +void tegra_pm_system_suspend_exit(void); +int tegra_system_suspended(void); + +/* Declarations for tegraXXX_pm.c */ +int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); +int tegra_prepare_cpu_on_finish(unsigned long mpidr); + +/* Declarations for tegra_bl31_setup.c */ +plat_params_from_bl2_t *bl31_get_plat_params(void); +int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); + +/* Declarations for tegra_delay_timer.c */ +void tegra_delay_timer_init(void); + +#endif /* __TEGRA_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/platform.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/platform.mk new file mode 100644 index 0000000..b909335 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/platform.mk @@ -0,0 +1,37 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +SOC_DIR := plat/nvidia/tegra/soc/${TARGET_SOC} + +include plat/nvidia/tegra/common/tegra_common.mk +include ${SOC_DIR}/platform_${TARGET_SOC}.mk + +# modify BUILD_PLAT to point to SoC specific build directory +BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${TARGET_SOC}/${BUILD_TYPE} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c new file mode 100644 index 0000000..79e9f1c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Register used to clear CPU reset signals. Each CPU has two reset + * signals: CPU reset (3:0) and Core reset (19:16) + */ +#define CPU_CMPLX_RESET_CLR 0x344 +#define CPU_CORE_RESET_MASK 0x10001 + +static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; + +int32_t tegra_soc_validate_power_state(unsigned int power_state) +{ + /* Sanity check the requested afflvl */ + if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { + /* + * It's possible to enter standby only on affinity level 0 i.e. + * a cpu on Tegra. Ignore any other affinity level. + */ + if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0) + return PSCI_E_INVALID_PARAMS; + } + + /* Sanity check the requested state id */ + if (psci_get_pstate_id(power_state) != PLAT_SYS_SUSPEND_STATE_ID) { + ERROR("unsupported state id\n"); + return PSCI_E_NOT_SUPPORTED; + } + + return PSCI_E_SUCCESS; +} + +int tegra_soc_prepare_cpu_on(unsigned long mpidr) +{ + int cpu = mpidr & MPIDR_CPU_MASK; + uint32_t mask = CPU_CORE_RESET_MASK << cpu; + + if (cpu_powergate_mask[cpu] == 0) { + + /* Deassert CPU reset signals */ + mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); + + /* Power on CPU using PMC */ + tegra_pmc_cpu_on(cpu); + + /* Fill in the CPU powergate mask */ + cpu_powergate_mask[cpu] = 1; + + } else { + /* Power on CPU using Flow Controller */ + tegra_fc_cpu_on(cpu); + } + + return PSCI_E_SUCCESS; +} + +int tegra_soc_prepare_cpu_off(unsigned long mpidr) +{ + tegra_fc_cpu_off(mpidr & MPIDR_CPU_MASK); + return PSCI_E_SUCCESS; +} + +int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl) +{ + /* Nothing to be done for lower affinity levels */ + if (afflvl < MPIDR_AFFLVL2) + return PSCI_E_SUCCESS; + + /* Enter system suspend state */ + tegra_pm_system_suspend_entry(); + + /* Allow restarting CPU #1 using PMC on suspend exit */ + cpu_powergate_mask[1] = 0; + + /* Program FC to enter suspend state */ + tegra_fc_cpu_idle(read_mpidr()); + + /* Suspend DCO operations */ + write_actlr_el1(id); + + return PSCI_E_SUCCESS; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t132/plat_secondary.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t132/plat_secondary.c new file mode 100644 index 0000000..744dcb7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t132/plat_secondary.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SB_CSR 0x0 +#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1) + +/* AARCH64 CPU reset vector */ +#define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */ +#define SB_AA64_RESET_HI 0x34 /* width = 11:0 */ + +/* AARCH32 CPU reset vector */ +#define EVP_CPU_RESET_VECTOR 0x100 + +extern void tegra_secure_entrypoint(void); + +/* + * For T132, CPUs reset to AARCH32, so the reset vector is first + * armv8_trampoline which does a warm reset to AARCH64 and starts + * execution at the address in SB_AA64_RESET_LOW/SB_AA64_RESET_HI. + */ +__aligned(8) const uint32_t armv8_trampoline[] = { + 0xE3A00003, /* mov r0, #3 */ + 0xEE0C0F50, /* mcr p15, 0, r0, c12, c0, 2 */ + 0xEAFFFFFE, /* b . */ +}; + +/******************************************************************************* + * Setup secondary CPU vectors + ******************************************************************************/ +void plat_secondary_setup(void) +{ + uint32_t val; + uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint; + + /* + * For T132, CPUs reset to AARCH32, so the reset vector is first + * armv8_trampoline, which does a warm reset to AARCH64 and starts + * execution at the address in SCRATCH34/SCRATCH35. + */ + INFO("Setting up T132 CPU boot\n"); + + /* initial AARCH32 reset address */ + tegra_pmc_write_32(PMC_SECURE_SCRATCH22, + (unsigned long)&armv8_trampoline); + + /* set AARCH32 exception vector (read to flush) */ + mmio_write_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR, + (unsigned long)&armv8_trampoline); + val = mmio_read_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR); + + /* setup secondary CPU vector */ + mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW, + (reset_addr & 0xFFFFFFFF) | 1); + val = reset_addr >> 32; + mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF); + + /* configure PMC */ + tegra_pmc_cpu_setup(reset_addr); + tegra_pmc_lock_cpu_vectors(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t132/plat_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t132/plat_setup.c new file mode 100644 index 0000000..a76999c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t132/plat_setup.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/* sets of MMIO ranges setup */ +#define MMIO_RANGE_0_ADDR 0x50000000 +#define MMIO_RANGE_1_ADDR 0x60000000 +#define MMIO_RANGE_2_ADDR 0x70000000 +#define MMIO_RANGE_SIZE 0x200000 + +/* + * Table of regions to map using the MMU. + */ +static const mmap_region_t tegra_mmap[] = { + MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + {0} +}; + +/******************************************************************************* + * Set up the pagetables as per the platform memory map & initialize the MMU + ******************************************************************************/ +const mmap_region_t *plat_get_mmio_map(void) +{ + /* MMIO space */ + return tegra_mmap; +} + +uint64_t plat_get_syscnt_freq(void) +{ + return 12000000; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t132/platform_t132.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t132/platform_t132.mk new file mode 100644 index 0000000..69d6296 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t132/platform_t132.mk @@ -0,0 +1,46 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +TEGRA_BOOT_UART_BASE := 0x70006300 +$(eval $(call add_define,TEGRA_BOOT_UART_BASE)) + +TZDRAM_BASE := 0xF5C00000 +$(eval $(call add_define,TZDRAM_BASE)) + +PLATFORM_CLUSTER_COUNT := 1 +$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) + +PLATFORM_MAX_CPUS_PER_CLUSTER := 2 +$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) + +BL31_SOURCES += lib/cpus/aarch64/denver.S \ + ${SOC_DIR}/plat_psci_handlers.c \ + ${SOC_DIR}/plat_setup.c \ + ${SOC_DIR}/plat_secondary.c diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c new file mode 100644 index 0000000..57be347 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Register used to clear CPU reset signals. Each CPU has two reset + * signals: CPU reset (3:0) and Core reset (19:16). + */ +#define CPU_CMPLX_RESET_CLR 0x454 +#define CPU_CORE_RESET_MASK 0x10001 + +static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; + +int32_t tegra_soc_validate_power_state(unsigned int power_state) +{ + /* Sanity check the requested afflvl */ + if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { + /* + * It's possible to enter standby only on affinity level 0 i.e. + * a cpu on Tegra. Ignore any other affinity level. + */ + if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0) + return PSCI_E_INVALID_PARAMS; + } + + /* Sanity check the requested state id */ + switch (psci_get_pstate_id(power_state)) { + case PSTATE_ID_CORE_POWERDN: + case PSTATE_ID_CLUSTER_IDLE: + case PSTATE_ID_CLUSTER_POWERDN: + case PSTATE_ID_SOC_POWERDN: + break; + + default: + ERROR("unsupported state id\n"); + return PSCI_E_NOT_SUPPORTED; + } + + return PSCI_E_SUCCESS; +} + +int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl) +{ + /* There's nothing to be done for affinity level 1 */ + if (afflvl == MPIDR_AFFLVL1) + return PSCI_E_SUCCESS; + + switch (id) { + /* Prepare for cpu idle */ + case PSTATE_ID_CORE_POWERDN: + tegra_fc_cpu_idle(read_mpidr()); + return PSCI_E_SUCCESS; + + /* Prepare for cluster idle */ + case PSTATE_ID_CLUSTER_IDLE: + tegra_fc_cluster_idle(read_mpidr()); + return PSCI_E_SUCCESS; + + /* Prepare for cluster powerdn */ + case PSTATE_ID_CLUSTER_POWERDN: + tegra_fc_cluster_powerdn(read_mpidr()); + return PSCI_E_SUCCESS; + + /* Prepare for system idle */ + case PSTATE_ID_SOC_POWERDN: + + /* Enter system suspend state */ + tegra_pm_system_suspend_entry(); + + /* suspend the entire soc */ + tegra_fc_soc_powerdn(read_mpidr()); + + return PSCI_E_SUCCESS; + + default: + ERROR("Unknown state id (%d)\n", id); + break; + } + + return PSCI_E_NOT_SUPPORTED; +} + +int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr) +{ + uint32_t val; + + /* + * Check if we are exiting from SOC_POWERDN. + */ + if (tegra_system_suspended()) { + + /* + * Enable WRAP to INCR burst type conversions for + * incoming requests on the AXI slave ports. + */ + val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); + val &= ~ENABLE_UNSUP_TX_ERRORS; + val |= ENABLE_WRAP_TO_INCR_BURSTS; + mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); + + /* + * Restore Boot and Power Management Processor (BPMP) reset + * address and reset it. + */ + tegra_fc_reset_bpmp(); + + /* + * System resume complete. + */ + tegra_pm_system_suspend_exit(); + } + + /* + * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's + * used for power management and boot purposes. Inform the BPMP that + * we have completed the cluster power up. + */ + if (psci_get_max_phys_off_afflvl() == MPIDR_AFFLVL1) + tegra_fc_lock_active_cluster(); + + return PSCI_E_SUCCESS; +} + +int tegra_soc_prepare_cpu_on(unsigned long mpidr) +{ + int cpu = mpidr & MPIDR_CPU_MASK; + uint32_t mask = CPU_CORE_RESET_MASK << cpu; + + /* Deassert CPU reset signals */ + mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); + + /* Turn on CPU using flow controller or PMC */ + if (cpu_powergate_mask[cpu] == 0) { + tegra_pmc_cpu_on(cpu); + cpu_powergate_mask[cpu] = 1; + } else { + tegra_fc_cpu_on(cpu); + } + + return PSCI_E_SUCCESS; +} + +int tegra_soc_prepare_cpu_off(unsigned long mpidr) +{ + tegra_fc_cpu_off(mpidr & MPIDR_CPU_MASK); + return PSCI_E_SUCCESS; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t210/plat_secondary.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t210/plat_secondary.c new file mode 100644 index 0000000..b07f446 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t210/plat_secondary.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#define SB_CSR 0x0 +#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1) + +/* CPU reset vector */ +#define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */ +#define SB_AA64_RESET_HI 0x34 /* width = 11:0 */ + +extern void tegra_secure_entrypoint(void); + +/******************************************************************************* + * Setup secondary CPU vectors + ******************************************************************************/ +void plat_secondary_setup(void) +{ + uint32_t val; + uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint; + + INFO("Setting up secondary CPU boot\n"); + + /* setup secondary CPU vector */ + mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW, + (reset_addr & 0xFFFFFFFF) | 1); + val = reset_addr >> 32; + mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF); + + /* configure PMC */ + tegra_pmc_cpu_setup(reset_addr); + tegra_pmc_lock_cpu_vectors(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t210/plat_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t210/plat_setup.c new file mode 100644 index 0000000..cbe7a04 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t210/plat_setup.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/* sets of MMIO ranges setup */ +#define MMIO_RANGE_0_ADDR 0x50000000 +#define MMIO_RANGE_1_ADDR 0x60000000 +#define MMIO_RANGE_2_ADDR 0x70000000 +#define MMIO_RANGE_SIZE 0x200000 + +/* + * Table of regions to map using the MMU. + */ +static const mmap_region_t tegra_mmap[] = { + MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + {0} +}; + +/******************************************************************************* + * Set up the pagetables as per the platform memory map & initialize the MMU + ******************************************************************************/ +const mmap_region_t *plat_get_mmio_map(void) +{ + /* MMIO space */ + return tegra_mmap; +} + +/******************************************************************************* + * Handler to get the System Counter Frequency + ******************************************************************************/ +uint64_t plat_get_syscnt_freq(void) +{ + return 19200000; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t210/platform_t210.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t210/platform_t210.mk new file mode 100644 index 0000000..5001629 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/nvidia/tegra/soc/t210/platform_t210.mk @@ -0,0 +1,63 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +TEGRA_BOOT_UART_BASE := 0x70006000 +$(eval $(call add_define,TEGRA_BOOT_UART_BASE)) + +TZDRAM_BASE := 0xFDC00000 +$(eval $(call add_define,TZDRAM_BASE)) + +ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1 +$(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT)) + +ENABLE_NS_L2_CPUECTRL_RW_ACCESS := 1 +$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS)) + +ENABLE_L2_DYNAMIC_RETENTION := 1 +$(eval $(call add_define,ENABLE_L2_DYNAMIC_RETENTION)) + +ENABLE_CPU_DYNAMIC_RETENTION := 1 +$(eval $(call add_define,ENABLE_CPU_DYNAMIC_RETENTION)) + +PLATFORM_CLUSTER_COUNT := 2 +$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) + +PLATFORM_MAX_CPUS_PER_CLUSTER := 4 +$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) + +BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + ${SOC_DIR}/plat_psci_handlers.c \ + ${SOC_DIR}/plat_setup.c \ + ${SOC_DIR}/plat_secondary.c + +# Enable workarounds for selected Cortex-A53 erratas. +ERRATA_A53_826319 := 1 + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/aarch64/bl2_reset.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/aarch64/bl2_reset.S new file mode 100644 index 0000000..001ca94 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/aarch64/bl2_reset.S @@ -0,0 +1,426 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "platform_def.h" + + +#define RST_BASE (0xE6160000) +#define RST_CA53BAR2 (0x0034) +#define RST_CA57BAR2 (0x0024) +#define RST_CA53CPU0BARH (0x0080) +#define RST_CA53CPU0BARL (0x0084) +#define RST_CA53CPU1BARH (0x0090) +#define RST_CA53CPU1BARL (0x0094) +#define RST_CA53CPU2BARH (0x00A0) +#define RST_CA53CPU2BARL (0x00A4) +#define RST_CA53CPU3BARH (0x00B0) +#define RST_CA53CPU3BARL (0x00B4) +#define RST_CA57CPU0BARH (0x00C0) +#define RST_CA57CPU0BARL (0x00C4) +#define RST_CA57CPU1BARH (0x00D0) +#define RST_CA57CPU1BARL (0x00D4) +#define RST_CA57CPU2BARH (0x00E0) +#define RST_CA57CPU2BARL (0x00E4) +#define RST_CA57CPU3BARH (0x00F0) +#define RST_CA57CPU3BARL (0x00F4) + +#define RST_BAR2_MASK (0xFFFFFC00) +#define RST_BAR2_BAREN (0x00000010) +#define RST_BAR2_VLD (0x00000001) +#define RST_BAR2_SHIFT (18-10) +#define RST_CPUnBARH_SHIFT (32) +#define RST_CPUnBARH_MASK (0x000000FF) +#define RST_CPUnBARL_MASK (0xFFFFFFFC) + + + .global bl2_reset + .global bl2_secondly_reset + .global bl2_init_secondly_reset + +func bl2_reset + mov x0, #0 + mov x1, #0 + mov x2, #0 + mov x3, #0 + mov x4, #0 + mov x5, #0 + mov x6, #0 + mov x7, #0 + mov x8, #0 + mov x9, #0 + mov x10, #0 + mov x11, #0 + mov x12, #0 + mov x13, #0 + mov x14, #0 + mov x15, #0 + mov x16, #0 + mov x17, #0 + mov x18, #0 + mov x19, #0 + mov x20, #0 + mov x21, #0 + mov x22, #0 + mov x23, #0 + mov x24, #0 + mov x25, #0 + mov x26, #0 + mov x27, #0 + mov x28, #0 + mov x29, #0 + mov x30, #0 + + /* --------------------------------------------- + * Set the CPU endianness before doing anything + * that might involve memory reads or writes. + * --------------------------------------------- + */ + mrs x0, sctlr_el3 + bic x0, x0, #SCTLR_EE_BIT + msr sctlr_el3, x0 + isb + + /* --------------------------------------------- + * Set the exception vector to something sane. + * --------------------------------------------- + */ + adr x0, bl2_exceptions + msr vbar_el3, x0 + isb + + /* --------------------------------------------------------------------- + * The initial state of the Architectural feature trap register + * (CPTR_EL3) is unknown and it must be set to a known state. All + * feature traps are disabled. Some bits in this register are marked as + * Reserved and should not be modified. + * + * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 + * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. + * CPTR_EL3.TTA: This causes access to the Trace functionality to trap + * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register + * access to trace functionality is not supported, this bit is RES0. + * CPTR_EL3.TFP: This causes instructions that access the registers + * associated with Floating Point and Advanced SIMD execution to trap + * to EL3 when executed from any exception level, unless trapped to EL1 + * or EL2. + * --------------------------------------------------------------------- + */ + mrs x0, cptr_el3 + bic w0, w0, #TCPAC_BIT + bic w0, w0, #TTA_BIT + bic w0, w0, #TFP_BIT + msr cptr_el3, x0 + + /* -------------------------------------------- + * Allocate a stack whose memory will be marked + * as Normal-IS-WBWA when the MMU is enabled. + * There is no risk of reading stale stack + * memory after enabling the MMU as only the + * primary cpu is running at the moment. + * -------------------------------------------- + */ + mrs x0, mpidr_el1 + bl platform_set_stack + + mov x0, #(SCR_RES1_BITS | SCR_RW_BIT) + msr scr_el3, x0 + + bl bl2_init_secondly_reset + + ldr x0, =bl2_entrypoint + msr elr_el3, x0 + mov x1, #(DISABLE_ALL_EXCEPTIONS << SPSR_DAIF_SHIFT) | (MODE_RW_64 << MODE_RW_SHIFT) | (MODE_EL1 << MODE_EL_SHIFT) | (MODE_SP_ELX << MODE_SP_SHIFT) + msr spsr_el3, x1 + + adr x1, BL2_MEM_INFO + mov x0, #RUN_IMAGE + + eret +endfunc bl2_reset + + + .align 3 +BL2_MEM_INFO: /* meminfo_t */ + .quad BL31_BASE /* total_base */ + .quad (BL31_LIMIT - BL31_BASE) /* total_size */ + .quad BL31_BASE /* free_base */ + .quad (BL31_LIMIT - BL31_BASE) /* free_size */ + + + /* --------------------------------------------- + * initialize secondly boot + * --------------------------------------------- + */ +func bl2_init_secondly_reset + adr x0, bl2_secondly_reset + ldr x1, =RCAR_SECRAM_BASE + mov x2, #0 /* Number of copied bytes */ + mov x4, #(BL2_SECONDLY_RESET - bl2_secondly_reset) +1: + ldr w3, [x0, x2] + str w3, [x1, x2] /* copy secondly boot code */ + add x2, x2, #4 + cmp x4, x2 + b.gt 1b + + /* initialize Boot Address Registers */ + ldr x0, =RST_BASE + + ldr w1, =(RCAR_SECRAM_BASE & RST_CPUnBARL_MASK) + str w1, [x0, #RST_CA53CPU0BARL] + str wzr, [x0, #RST_CA53CPU0BARH] + str w1, [x0, #RST_CA53CPU1BARL] + str wzr, [x0, #RST_CA53CPU1BARH] + str w1, [x0, #RST_CA53CPU2BARL] + str wzr, [x0, #RST_CA53CPU2BARH] + str w1, [x0, #RST_CA53CPU3BARL] + str wzr, [x0, #RST_CA53CPU3BARH] + str w1, [x0, #RST_CA57CPU0BARL] + str wzr, [x0, #RST_CA57CPU0BARH] + str w1, [x0, #RST_CA57CPU1BARL] + str wzr, [x0, #RST_CA57CPU1BARH] + str w1, [x0, #RST_CA57CPU2BARL] + str wzr, [x0, #RST_CA57CPU2BARH] + str w1, [x0, #RST_CA57CPU3BARL] + str wzr, [x0, #RST_CA57CPU3BARH] + + ret +endfunc bl2_init_secondly_reset + + + /* --------------------------------------------- + * secondly boot + * --------------------------------------------- + */ +func bl2_secondly_reset + mrs x0, sctlr_el3 + bic x0, x0, #SCTLR_EE_BIT + msr sctlr_el3, x0 + isb + + mrs x0, cptr_el3 + bic w0, w0, #TCPAC_BIT + bic w0, w0, #TTA_BIT + bic w0, w0, #TFP_BIT + msr cptr_el3, x0 + + mov_imm x0, PARAMS_BASE /* pointer to bl31_ep_info */ + mov_imm x2, BL31_BASE + mov x1, #0x00000001 /* warm boot */ + br x2 /* jump to BL31 */ + nop + nop + nop +BL2_SECONDLY_RESET: +endfunc bl2_secondly_reset + + + + .section .vectors, "ax"; .align 11 + + /* ----------------------------------------------------- + * Very simple stackless exception handlers used by BL1. + * ----------------------------------------------------- + */ + .align 7 +bl2_exceptions: + /* ----------------------------------------------------- + * Current EL with SP0 : 0x0 - 0x200 + * ----------------------------------------------------- + */ +SynchronousExceptionSP0: + mov x0, #SYNC_EXCEPTION_SP_EL0 + bl plat_report_exception + b SynchronousExceptionSP0 + check_vector_size SynchronousExceptionSP0 + + .align 7 +IrqSP0: + mov x0, #IRQ_SP_EL0 + bl plat_report_exception + b IrqSP0 + check_vector_size IrqSP0 + + .align 7 +FiqSP0: + mov x0, #FIQ_SP_EL0 + bl plat_report_exception + b FiqSP0 + check_vector_size FiqSP0 + + .align 7 +SErrorSP0: + mov x0, #SERROR_SP_EL0 + bl plat_report_exception + b SErrorSP0 + check_vector_size SErrorSP0 + + /* ----------------------------------------------------- + * Current EL with SPx: 0x200 - 0x400 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionSPx: + mov x0, #SYNC_EXCEPTION_SP_ELX + bl plat_report_exception + b SynchronousExceptionSPx + check_vector_size SynchronousExceptionSPx + + .align 7 +IrqSPx: + mov x0, #IRQ_SP_ELX + bl plat_report_exception + b IrqSPx + check_vector_size IrqSPx + + .align 7 +FiqSPx: + mov x0, #FIQ_SP_ELX + bl plat_report_exception + b FiqSPx + check_vector_size FiqSPx + + .align 7 +SErrorSPx: + mov x0, #SERROR_SP_ELX + bl plat_report_exception + b SErrorSPx + check_vector_size SErrorSPx + + /* ----------------------------------------------------- + * Lower EL using AArch64 : 0x400 - 0x600 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionA64: + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + /* ------------------------------------------------ + * Only a single SMC exception from BL2 to ask + * BL1 to pass EL3 control to BL31 is expected + * here. + * It expects X0 with RUN_IMAGE SMC function id + * X1 with address of a entry_point_info_t structure + * describing the BL3-1 entrypoint + * ------------------------------------------------ + */ + mov x19, x0 + mov x20, x1 + + mrs x0, esr_el3 + ubfx x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH + cmp x1, #EC_AARCH64_SMC + b.ne panic + + mov x0, #RUN_IMAGE + cmp x19, x0 + b.ne panic + + mov x0, x20 + ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] + msr elr_el3, x0 + msr spsr_el3, x1 + ubfx x0, x1, #MODE_EL_SHIFT, #2 + cmp x0, #MODE_EL3 + b.ne panic + + ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] + ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] + ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] + ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] + eret + +panic: + mov x0, #SYNC_EXCEPTION_AARCH64 + bl plat_report_exception + + wfi + b panic + check_vector_size SynchronousExceptionA64 + + + .align 7 +IrqA64: + mov x0, #IRQ_AARCH64 + bl plat_report_exception + b IrqA64 + check_vector_size IrqA64 + + .align 7 +FiqA64: + mov x0, #FIQ_AARCH64 + bl plat_report_exception + b FiqA64 + check_vector_size FiqA64 + + .align 7 +SErrorA64: + mov x0, #SERROR_AARCH64 + bl plat_report_exception + b SErrorA64 + check_vector_size SErrorA64 + + /* ----------------------------------------------------- + * Lower EL using AArch32 : 0x600 - 0x800 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionA32: + mov x0, #SYNC_EXCEPTION_AARCH32 + bl plat_report_exception + b SynchronousExceptionA32 + check_vector_size SynchronousExceptionA32 + + .align 7 +IrqA32: + mov x0, #IRQ_AARCH32 + bl plat_report_exception + b IrqA32 + check_vector_size IrqA32 + + .align 7 +FiqA32: + mov x0, #FIQ_AARCH32 + bl plat_report_exception + b FiqA32 + check_vector_size FiqA32 + + .align 7 +SErrorA32: + mov x0, #SERROR_AARCH32 + bl plat_report_exception + b SErrorA32 + check_vector_size SErrorA32 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/aarch64/rcar_common.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/aarch64/rcar_common.c new file mode 100644 index 0000000..7ee1405 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/aarch64/rcar_common.c @@ -0,0 +1,272 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../rcar_def.h" +#include "../rcar_private.h" +#include "../rcar_version.h" + +const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN] + __attribute__((__section__(".version"))) = VERSION_OF_RENESAS; + +#define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \ + RCAR_SHARED_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \ + FLASH0_SIZE, \ + MT_MEMORY | MT_RO | MT_SECURE) + +#define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \ + DRAM1_NS_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_BASE, \ + BL32_LIMIT - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MAP_DEVICE_RCAR MAP_REGION_FLAT(DEVICE_RCAR_BASE, \ + DEVICE_RCAR_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_ATFW_LOG MAP_REGION_FLAT(RCAR_BL31_LOG_BASE, \ + RCAR_BL31_LOG_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/* + * Table of regions for various BL stages to map using the MMU. + * This doesn't include TZRAM as the 'mem_layout' argument passed to + * configure_mmu_elx() will give the available subset of that, + */ +#if IMAGE_BL1 +const mmap_region_t rcar_mmap[] = { + MAP_SHARED_RAM, + MAP_FLASH0, + MAP_DEVICE0, + MAP_DEVICE1, + { 0} +}; +#endif +#if IMAGE_BL2 +const mmap_region_t rcar_mmap[] = { + MAP_SHARED_RAM, + MAP_FLASH0, + MAP_DRAM1_NS, + MAP_BL32_MEM, + MAP_DEVICE_RCAR, + { 0} +}; +#endif +#if IMAGE_BL31 +const mmap_region_t rcar_mmap[] = { + MAP_SHARED_RAM, + MAP_ATFW_LOG, + MAP_DEVICE_RCAR, + { 0} +}; +#endif +#if IMAGE_BL32 +const mmap_region_t rcar_mmap[] = { + MAP_DEVICE0, + MAP_DEVICE1, + { 0} +}; +#endif +#if IMAGE_BL33 +const mmap_region_t rcar_mmap[] = { + MAP_SHARED_RAM, + MAP_ATFW_LOG, + MAP_DEVICE_RCAR, + { 0} +}; +#endif + +CASSERT(ARRAY_SIZE(rcar_mmap) + RCAR_BL_REGIONS \ + <= MAX_MMAP_REGIONS, assert_max_mmap_regions); + +/******************************************************************************* + * Macro generating the code for the function setting up the pagetables as per + * the platform memory map & initialize the mmu, for the given exception level + ******************************************************************************/ +#if USE_COHERENT_MEM +#define DEFINE_CONFIGURE_MMU_EL(_el) \ + void rcar_configure_mmu_el##_el(unsigned long total_base, \ + unsigned long total_size, \ + unsigned long ro_start, \ + unsigned long ro_limit, \ + unsigned long coh_start, \ + unsigned long coh_limit) \ + { \ + mmap_add_region(total_base, total_base, \ + total_size, \ + MT_MEMORY | MT_RW | MT_SECURE); \ + mmap_add_region(ro_start, ro_start, \ + ro_limit - ro_start, \ + MT_MEMORY | MT_RO | MT_SECURE); \ + mmap_add_region(coh_start, coh_start, \ + coh_limit - coh_start, \ + MT_DEVICE | MT_RW | MT_SECURE); \ + mmap_add(rcar_mmap); \ + init_xlat_tables(); \ + \ + enable_mmu_el##_el(0); \ + } +#else +#define DEFINE_CONFIGURE_MMU_EL(_el) \ + void rcar_configure_mmu_el##_el(unsigned long total_base, \ + unsigned long total_size, \ + unsigned long ro_start, \ + unsigned long ro_limit) \ + { \ + mmap_add_region(total_base, total_base, \ + total_size, \ + MT_MEMORY | MT_RW | MT_SECURE); \ + mmap_add_region(ro_start, ro_start, \ + ro_limit - ro_start, \ + MT_MEMORY | MT_RO | MT_SECURE); \ + mmap_add(rcar_mmap); \ + init_xlat_tables(); \ + \ + enable_mmu_el##_el(0); \ + } +#endif + +/* Define EL1 and EL3 variants of the function initialising the MMU */ +DEFINE_CONFIGURE_MMU_EL(1) +DEFINE_CONFIGURE_MMU_EL(3) + +#if (IMAGE_BL2) +extern int32_t file_to_cert(const int32_t filename, uint32_t *cert_addr); +extern void get_info_from_cert(uint64_t cert_addr, uint32_t *size, uint32_t *dest_addr); +#endif + +unsigned long plat_get_ns_image_entrypoint(void) +{ +#if (IMAGE_BL2) + int32_t ret; + uint32_t cert_addr; + uint32_t l_image_size; + uint32_t dest_addr; + ret = file_to_cert(BL33_CERT_ID, &cert_addr); + if (0 == ret) { + get_info_from_cert((uint64_t) cert_addr, &l_image_size, &dest_addr); + } else { + ERROR("%s : cert file load error", __func__); + dest_addr = NS_IMAGE_OFFSET; + } + return dest_addr; +#else + return NS_IMAGE_OFFSET; +#endif +} + +uint64_t plat_get_syscnt_freq(void) +{ + uint64_t counter_base_frequency; + + /* Read the frequency from Frequency modes table */ + counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + (uint32_t)CNTFID_OFF); + + /* The first entry of the frequency modes table must not be 0 */ + if (counter_base_frequency == 0U) { + panic(); + } + + return counter_base_frequency; +} + +/* Map of CCI masters with the slave interfaces they are connected */ +static int cci_map[] = { + CCI500_CLUSTER0_SL_IFACE_IX, + CCI500_CLUSTER1_SL_IFACE_IX +}; + +void rcar_cci_init(void) +{ + /* + * Initialize CCI-500 driver + */ + uint32_t product = mmio_read_32((uintptr_t)RCAR_PRR) + & RCAR_PRODUCT_MASK; + if (RCAR_PRODUCT_M3 == product) { + cci_map[0U] = CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3; + cci_map[1U] = CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3; + } + cci_init(RCAR_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); +} + +void rcar_cci_enable(void) +{ + cci_enable_snoop_dvm_reqs((unsigned int)MPIDR_AFFLVL1_VAL(read_mpidr())); +} + +void rcar_cci_disable(void) +{ + cci_disable_snoop_dvm_reqs((unsigned int)MPIDR_AFFLVL1_VAL(read_mpidr())); +} + +/******************************************************************************* + * Gets SPSR for BL32 entry + ******************************************************************************/ +uint32_t rcar_get_spsr_for_bl32_entry(void) +{ + /* + * The Secure Payload Dispatcher service is responsible for + * setting the SPSR prior to entry into the BL32 image. + */ + return 0U; +} + +/******************************************************************************* + * Gets SPSR for BL33 entry + ******************************************************************************/ +#define BL33_EL1 0 +#define BL33_EL2 1 + +uint32_t rcar_get_spsr_for_bl33_entry(void) +{ +#if (RCAR_BL33_EXECUTION_EL == BL33_EL1) + return (uint32_t)SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); +#elif (RCAR_BL33_EXECUTION_EL == BL33_EL2) + return (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); +#else +#error +#endif +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/aarch64/rcar_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/aarch64/rcar_helpers.S new file mode 100644 index 0000000..998c229 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/aarch64/rcar_helpers.S @@ -0,0 +1,443 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "../rcar_def.h" + + + .globl platform_get_entrypoint + .globl plat_secondary_cold_boot_setup + .globl platform_mem_init + .globl plat_report_exception + .globl platform_is_primary_cpu + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_reset_handler + .globl iciallu + + .extern platform_set_stack + .extern rcar_log_init + .extern tf_printf +#if IMAGE_BL2 + .extern bl2_swdt_exec + .extern arm_gic_acknowledge_interrupt + .extern bl2_interrupt_error_type + .extern bl2_interrupt_error_id + +#define INT_ID_MASK (0x3ff) +#endif + + .extern rcar_boot_kind_flag[data] + +.section .rodata.errorlog, "aS" +error_log_data: + .asciz "[Error log is in plat_secondary_cold_setup]","" + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs log output from the address of + * error_log_data and go to cb_panic. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* + * If timer is enabled, do not clear the freq register + */ + mrs x0, CNTP_CTL_EL0 + mov x1, #1 + and x2, x0, x1 + cbnz x2, log_output /* timer is enabled */ + /* + * Timer is disabled, then clear the freq register + */ + mov x0, #0 + msr CNTFRQ_EL0, x0 +log_output: + bl platform_set_stack /* set stack pointer */ + bl rcar_log_init /* log area initialize */ + ldr x0, =error_log_data /* argument of tf_printf function */ + bl tf_printf /* log output */ +cb_panic: + b cb_panic +endfunc plat_secondary_cold_boot_setup + + + /* ----------------------------------------------------- + * void platform_get_entrypoint (unsigned int mpid); + * + * Main job of this routine is to distinguish between + * a cold and warm boot. + * On a cold boot the secondaries first wait for the + * platform to be initialized after which they are + * hotplugged in. The primary proceeds to perform the + * platform initialization. + * On a warm boot, each cpu jumps to the address in its + * mailbox. + * + * TODO: Not a good idea to save lr in a temp reg + * ----------------------------------------------------- + */ +func platform_get_entrypoint + mov x9, x30 /* lr */ + + /* + * format of x21 + * 4 3 2 1 0 + * --------------------------------- + * | | | | | + * | reset info | boot kind | + * | | | | | + * --------------------------------- + * 00 : Usual | 00 : Cold boot + * 01 : Unusual | 01 : Warm boot + * 10 : Reserved | 10 : Reserved + * 11 : Reserved | 11 : Reserved + * + */ + + /* + * Check the reset info + */ + and x1, x21, #0x000c /* Get the reset info */ + cmp x1, #0x0008 /* Is reset info "10:Reserved" ? */ + beq el3_panic + cmp x1, #0x000c /* Is reset info "11:Reserved" ? */ + beq el3_panic + /* */ + /* Check the boot kind */ + /* */ + and x1, x21, #0x0003 /* Get the boot kind */ + cmp x1, #0x0002 /* Is boot kind "10:Reserved" ? */ + beq el3_panic + cmp x1, #0x0003 /* Is boot kind "11:Reserved" ? */ + beq el3_panic + /* */ + /* warm boot or cold boot */ + /* */ + and x1, x21, #1 /* warm boot ? */ + cmp x1, #0 /* If x1 is 0 then cold boot */ + bne warm_reset /* bit0 of x1 is 1 then warm boot */ + /* */ + /* Cold boot */ + /* */ + mov x0, #0 + b exit + +warm_reset: + /* --------------------------------------------- + * A per-cpu mailbox is maintained in the tru- + * sted SDRAM. Its flushed out of the caches + * after every update using normal memory so + * its safe to read it here with SO attributes + * --------------------------------------------- + */ + ldr x10, =MBOX_BASE /* top of mailbox address -> x10 */ + bl platform_get_core_pos /* restore cpu no to x0 as CA53=0-3, CA57=4-7 */ + lsl x0, x0, #CACHE_WRITEBACK_SHIFT /* 6bit left shift */ + /* because mailbox size is 0x40 byte per cpu */ + ldr x0, [x10, x0] /* top address of mailbox is entrypoint */ + cbz x0, _panic /* If warm boot and entrypoint is 0 then panic */ +exit: + ret x9 +_panic: b _panic +endfunc platform_get_entrypoint + + + /* ----------------------------------------------------- + * void platform_mem_init (void); + * + * Zero out the mailbox registers in the shared memory + * and set the rcar_boot_kind_flag. + * The mmu is turned off right now and only the primary can + * ever execute this code. Secondaries will read the + * mailboxes using SO accesses. + * ----------------------------------------------------- + */ +func platform_mem_init + ldr x0, =MBOX_BASE + mov w1, #PLATFORM_CORE_COUNT +loop: + str xzr, [x0], #CACHE_WRITEBACK_GRANULE + subs w1, w1, #1 + b.gt loop + /* for R-Car Gen3 */ + ldr x0, =rcar_boot_kind_flag + str w21, [x0] + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * void plat_report_exception(unsigned int type) + * Function to report an unhandled exception + * with platform-specific means. + * --------------------------------------------- + */ +func plat_report_exception + mrs x1, CurrentEl + + str w0, [x1] +#if IMAGE_BL2 + mov w1, #FIQ_SP_ELX + cmp w0, w1 + beq rep_exec_fiq_elx +/* + * Please imprement checking the other type of interrupt +*/ + b rep_exec_panic_type +rep_exec_fiq_elx: + bl arm_gic_acknowledge_interrupt + mov x2, #INT_ID_MASK + and x0, x0, x2 + mov x1, #ARM_IRQ_SEC_WDT_A + cmp x0, x1 + bne rep_exec_panic_id + mrs x0, ELR_EL1 + b bl2_swdt_exec +rep_exec_panic_type: /* interrupt type error */ + /* x0 is interrupt TYPE */ + b bl2_interrupt_error_type +rep_exec_panic_id: /* interrupt id error */ + /* x0 is interrupt ID */ + b bl2_interrupt_error_id +rep_exec_end: +#endif + ret +endfunc plat_report_exception + + /* + * Starting CPU is ... + * MD7=1 and MD6=1 of MODEMR : CortexR7 + * MD7=1 and MD6=0 of MODEMR : Reserved + * MD7=0 and MD6=1 of MODEMR : CortexA53 + * MD7=0 and MD6=0 of MODEMR : CortexA57 + * + * Information of MPIDR_EL1 + * affinity level 1(bit15-8) = 1 : CortexA53 + * affinity level 1(bit15-8) = 0 : CortexA57 + * + */ + +func platform_is_primary_cpu + /* + * Get MD6 and MD7 of MODEMR, then move MD6 to bit0 and move MD7 to bit1 of x1 + */ + ldr x1, =RCAR_MODEMR_A /* x1 <- address of MODEMR register */ + ldr x2, [x1] /* Get the data of MODEMR -> x2 */ + mov x1, #0x00c0 /* move MD6(0x0040) and MD7(0x0080) */ + and x1, x2, x1 /* Get MD6 and MD7 information -> x1 */ + lsr x1, x1, #6 /* MD6->bit0, MD7->bit1 */ + /* + * Get data of affinity level 1 of MPIDR_EL1, then move data to bit7-0 of x2 + */ + mov x2, #MPIDR_CLUSTER_MASK /* MPIDR_CLUSTER_MASK=0xFF00 -> x2 */ + and x2, x0, x2 /* Get the affinity level 1 -> x2 */ + lsr x2, x2, #MPIDR_AFFINITY_BITS /* affinity level 1 -> bit7-0 of x2 */ + /* + * Check the starting CPU by MD7 + */ + mov x3, #0x0002 /* for test the MD7 */ + and x3, x1, x3 /* MD7 information -> x3(0 or not) */ + cbnz x3, primary_check /* Starting CPU is CortexR7 */ + /* + * CA53 check + */ + mov x3, #0x0003 /* MD6 and MD7 */ + and x3, x1, x3 + cmp x3, #0x0001 /* If starting CPU is CortexA53 */ + bne checkCA57 /* is not then branch to check CA57 */ + cmp x2, #0x0001 /* If affinity level 1 is CortexA53 */ + beq primary_check /* CPU is CortexA53 */ + b platform_is_secondary /* It is secondary */ + /* + * CA57 check + */ +checkCA57: + cmp x3, #0x0000 /* If starting CPU is CortexA57 */ + bne platform_is_secondary + cmp x2, #0x0000 /* If affinity level 1 is CortexA57 */ + beq primary_check /* CPU is CortexA57 */ + /* + * This CPU is secondary + */ +platform_is_secondary: + mov x0, #0 /* This cpu is secondary */ + b primary_check_exit /* return */ +primary_check: + and x0, x0, # MPIDR_CPU_MASK /* Get the bit7-0 of MPIDR_EL1 -> x0 */ + cmp x0, #RCAR_PRIMARY_CPU /* x0 = 0 (primary CPU)? */ + cset x0, eq /* If x0 is 0 carry bit set */ +primary_check_exit: + ret +endfunc platform_is_primary_cpu + + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize log area + * --------------------------------------------- + */ +func plat_crash_console_init +#if IMAGE_BL2 + mov x0, #0 +#else + mov x1, sp + mov_imm x2, RCAR_CRASH_STACK + mov sp, x2 + str x1, [sp, #-16]! + str x30, [sp, #-16]! + bl console_core_init + ldr x30, [sp], #16 + ldr x1, [sp], #16 + mov sp, x1 +#endif + ret +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to store a character to log area + * --------------------------------------------- + */ +func plat_crash_console_putc + mov x1, sp + mov_imm x2, RCAR_CRASH_STACK + mov sp, x2 + str x1, [sp, #-16]! + str x30, [sp, #-16]! + str x3, [sp, #-16]! + str x4, [sp, #-16]! + str x5, [sp, #-16]! + bl console_core_putc + ldr x5, [sp], #16 + ldr x4, [sp], #16 + ldr x3, [sp], #16 + ldr x30, [sp], #16 + ldr x1, [sp], #16 + mov sp, x1 + ret +endfunc plat_crash_console_putc + + + /* -------------------------------------------------------------------- + * void plat_reset_handler(void); + * + * Before adding code in this function, refer to the guidelines in + * docs/firmware-design.md to determine whether the code should reside + * within the FIRST_RESET_HANDLER_CALL block or not. + * + * For R-Car H3: + * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 + * - Set the L2 Data setup latency to 1 (i.e. 1 cycles) for Cortex-A57 + * - Set the L2 Data RAM latency to 3 (i.e. 4 cycles) for Cortex-A57 + * For R-Car M3: + * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 + * - Set the L2 Data setup latency to 0 (i.e. 0 cycles) for Cortex-A57 + * - Set the L2 Data RAM latency to 3 (i.e. 4 cycles) for Cortex-A57 + * + * -------------------------------------------------------------------- + */ +func plat_reset_handler + /* -------------------------------------------------------------------- + * Determine whether this code is running on R-Car H3 or R-Car M3. + * Keep this information in x2. + * -------------------------------------------------------------------- + */ + /* + * On R-Car H3: x2 := 0 + * On R-Car M3: x2 := 1 + */ + ldr x0, =0xFFF00044 /* read PRR */ + ldr w0, [x0] + ubfx w0, w0, 8, 8 + cmp w0, #0x4F /* H3? */ + b.eq H3 + mov x2, #1 /* set R-Car M3 */ + b CHK_A5x +H3: + mov x2, #0 /* set R-Car H3 */ + /* -------------------------------------------------------------------- + * Determine whether this code is executed on a Cortex-A53 or on a + * Cortex-A57 core. + * -------------------------------------------------------------------- + */ +CHK_A5x: + mrs x0, midr_el1 + ubfx x1, x0, MIDR_PN_SHIFT, #12 + cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK) + b.eq A57 + + ret + +A57: + /* -------------------------------------------------------------------- + * Cortex-A57 specific settings + * -------------------------------------------------------------------- + */ + mrs x0, L2CTLR_EL1 /* Get data from L2CTLR_EL1 */ + /* + * On R-Car H3/M3 + * + * L2 Tag RAM latency is bit8-6 of L2CTLR_EL1 + * L2 Data RAM setup is bit5 of L2CTLR_EL1 + * L2 Data RAM latency is bit2-0 of L2CTLR_EL1 + */ + mov x1, #0x1e7 /* for clear bit of L2 RAM */ + neg x1, x1 /* ~(0x1e7) -> x1 */ + and x0, x0, x1 /* clear bit of L2 RAM -> x0 */ + orr x0, x0, #0x2 << 6 /* L2 Tag RAM latency (3 cycles) */ + cbnz x2, M3_L2 /* If M3 then L2 Data RAM setup is 0 */ + orr x0, x0, #0x1 << 5 /* L2 Data RAM setup (1 cycle) */ +M3_L2: + orr x0, x0, #0x3 /* L2 Data RAM latency (4 cycles) */ + msr L2CTLR_EL1, x0 /* Store data to L2CTLR_EL1 */ + +apply_l2_ram_latencies: + + ret +endfunc plat_reset_handler + + + /* --------------------------------------------- + * void iciallu(void) + * Instruction Cache Invalidate All to PoU + * --------------------------------------------- + */ +func iciallu + ic iallu + + ret +endfunc iciallu diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl2_cpg_init.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl2_cpg_init.c new file mode 100644 index 0000000..5b9ee0c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl2_cpg_init.c @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "rcar_def.h" +#include "bl2_cpg_register.h" +#include "bl2_cpg_init.h" + +typedef struct { + uintptr_t adr; + uint32_t val; +} reg_setting_t; + +static const reg_setting_t reg_setting[] = { + + /* CPG (SECURITY) registers */ + + /* Secure Module Stop Control Register 0 */ + {SCMSTPCR0, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 1 */ + {SCMSTPCR1, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 2 */ + {SCMSTPCR2, 0xEBFFFFFFU}, + /* Secure Module Stop Control Register 3 */ + {SCMSTPCR3, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 4 */ + {SCMSTPCR4, 0x7FFFFFFFU}, + /* Secure Module Stop Control Register 5 */ + {SCMSTPCR5, 0xBFFFFFFFU}, + /* Secure Module Stop Control Register 6 */ + {SCMSTPCR6, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 7 */ + {SCMSTPCR7, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 8 */ + {SCMSTPCR8, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 9 */ + {SCMSTPCR9, 0xFFFDFFFFU}, + /* Secure Module Stop Control Register 10 */ + {SCMSTPCR10, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 11 */ + {SCMSTPCR11, 0xFFFFFFFFU}, + /* Secure Software Reset Access Enable Control Register 0 */ + {SCSRSTECR0, 0x00000000U}, + /* Secure Software Reset Access Enable Control Register 1 */ + {SCSRSTECR1, 0x00000000U}, + /* Secure Software Reset Access Enable Control Register 2 */ + {SCSRSTECR2, 0x14000000U}, + /* Secure Software Reset Access Enable Control Register 3 */ + {SCSRSTECR3, 0x00000000U}, + /* Secure Software Reset Access Enable Control Register 4 */ + {SCSRSTECR4, 0x80000003U}, + /* Secure Software Reset Access Enable Control Register 5 */ + {SCSRSTECR5, 0x40000000U}, + /* Secure Software Reset Access Enable Control Register 6 */ + {SCSRSTECR6, 0x00000000U}, + /* Secure Software Reset Access Enable Control Register 7 */ + {SCSRSTECR7, 0x00000000U}, + /* Secure Software Reset Access Enable Control Register 8 */ + {SCSRSTECR8, 0x00000000U}, + /* Secure Software Reset Access Enable Control Register 9 */ + {SCSRSTECR9, 0x00020000U}, + /* Secure Software Reset Access Enable Control Register 10 */ + {SCSRSTECR10, 0x00000000U}, + /* Secure Software Reset Access Enable Control Register 11 */ + {SCSRSTECR11, 0x00000000U} +}; + +static const reg_setting_t reg_setting_rt[] = { + + /* CPG (REALTIME) registers */ + + /* Realtime Module Stop Control Register 0 */ + {RMSTPCR0, 0x00200000U}, + /* Realtime Module Stop Control Register 1 */ + {RMSTPCR1, 0xFFFFFFFFU}, + /* Realtime Module Stop Control Register 2 */ + {RMSTPCR2, 0x340E2FDCU}, + /* Realtime Module Stop Control Register 3 */ + {RMSTPCR3, 0xFFFFFFDFU}, + /* Realtime Module Stop Control Register 4 */ + {RMSTPCR4, 0x80000184U}, + /* Realtime Module Stop Control Register 5 */ + {RMSTPCR5, 0xC3FFFFFFU}, + /* Realtime Module Stop Control Register 6 */ + {RMSTPCR6, 0xFFFFFFFFU}, + /* Realtime Module Stop Control Register 7 */ + {RMSTPCR7, 0xFFFFFFFFU}, + /* Realtime Module Stop Control Register 8 */ + {RMSTPCR8, 0x01F1FFF4U}, + /* Realtime Module Stop Control Register 9 */ + {RMSTPCR9, 0xFFFFFFFEU}, + /* Realtime Module Stop Control Register 10 */ + {RMSTPCR10, 0xFFFEFFE0U}, + /* Realtime Module Stop Control Register 11 */ + {RMSTPCR11, 0x00000037U} +}; + +void bl2_cpg_init(void) +{ + uint32_t i; + uint32_t ie; + uint32_t modemr; + + ie = (uint32_t)(sizeof(reg_setting) / sizeof(reg_setting_t)); + + for (i = 0U; i < ie; i++) { + cpg_write(reg_setting[i].adr, reg_setting[i].val); + } + + modemr = mmio_read_32(RCAR_MODEMR); + modemr &= MODEMR_BOOT_CPU_MASK; + + + if((modemr == MODEMR_BOOT_CPU_CA57) || + (modemr == MODEMR_BOOT_CPU_CA53)) { + ie = (uint32_t)(sizeof(reg_setting_rt) / sizeof(reg_setting_t)); + + for (i = 0U; i < ie; i++) { + cpg_write(reg_setting_rt[i].adr, reg_setting_rt[i].val); + } + } +} + +void cpg_write(uintptr_t regadr, uint32_t regval) +{ + uint32_t value = (regval); + mmio_write_32((uintptr_t)CPG_CPGWPR,~value); + mmio_write_32(regadr,value); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl2_rcar_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl2_rcar_setup.c new file mode 100644 index 0000000..58d93ba --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl2_rcar_setup.c @@ -0,0 +1,646 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "rcar_def.h" +#include "rcar_private.h" +#include "io_common.h" +#include "pfc_init.h" +#include "rpc_driver.h" +#include "dma_driver.h" +#include "bl2_secure_setting.h" +#include "bl2_cpg_register.h" +#include "bl2_cpg_init.h" +#include +#include +#include "ddr/boot_init_dram.h" +#include "qos/qos_init.h" +#include "rcar_version.h" +#include "bl2_swdt.h" +#include "avs_driver.h" +#include "scif.h" + + +/* CPG write protect registers */ +/*#define CPG_CPGWPR (CPG_BASE + 0x900U)*/ +/*#define CPG_CPGWPCR (CPG_BASE + 0x904U)*/ +#define CPGWPR_PASSWORD (0x5A5AFFFFU) +#define CPGWPCR_PASSWORD (0xA5A50000U) + +/* CA5x Debug Resource control registers */ +#define CPG_CA57DBGRCR (CPG_BASE + 0x2180U) +#define CPG_CA53DBGRCR (CPG_BASE + 0x1180U) +#define DBGCPUPREN ((uint32_t)1U << 19U) +#define CPG_PLL0CR (CPG_BASE + 0x00D8U) +#define CPG_PLL2CR (CPG_BASE + 0x002CU) +#define CPG_PLL4CR (CPG_BASE + 0x01F4U) + +/* RST Registers */ +#define RST_BASE (0xE6160000U) +#define RST_WDTRSTCR (RST_BASE + 0x0054U) +#define WDTRSTCR_PASSWORD (0xA55A0000U) +#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U) + +/* IPMMUregisters */ +#define IPMMU_MM_BASE (0xE67B0000U) /* IPMMU-MM */ +#define IPMMUMM_SYSCTRL (IPMMU_MM_BASE + 0x0500U) +#define IPMMUMM_SYSAUX (IPMMU_MM_BASE + 0x0504U) + +/* MIDR */ +#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT) +#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT) + +/* MaskROM API */ +typedef uint32_t(*ROM_GETLCS_API)(uint32_t *pLcs); +#if RCAR_LSI == RCAR_H3 +#define ROM_GETLCS_API_ADDR ((ROM_GETLCS_API)0xEB10DFE0U) +#elif RCAR_LSI == RCAR_M3 +#define ROM_GETLCS_API_ADDR ((ROM_GETLCS_API)0xEB110578U) +#endif +#define LCS_CM (0x0U) +#define LCS_DM (0x1U) +#define LCS_SD (0x3U) +#define LCS_SE (0x5U) +#define LCS_FA (0x7U) + +/* R-Car Gen3 product check */ +#if RCAR_LSI == RCAR_H3 +#define TARGET_PRODUCT RCAR_PRODUCT_H3 +#define TARGET_NAME "R-Car H3" +#elif RCAR_LSI == RCAR_M3 +#define TARGET_PRODUCT RCAR_PRODUCT_M3 +#define TARGET_NAME "R-Car M3" +#endif + + +/******************************************************************************* + * Declarations of linker defined symbols which will help us find the layout + * of trusted SRAM + ******************************************************************************/ +extern unsigned long __RO_START__; +extern unsigned long __RO_END__; + +#if USE_COHERENT_MEM +extern unsigned long __COHERENT_RAM_START__; +extern unsigned long __COHERENT_RAM_END__; +#endif + +/* + * The next 2 constants identify the extents of the code & RO data region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. + */ +#define BL2_RO_BASE (unsigned long)(&__RO_START__) +#define BL2_RO_LIMIT (unsigned long)(&__RO_END__) + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ +#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif + +/* Data structure which holds the extents of the trusted SRAM for BL2 */ +static meminfo_t bl2_tzram_layout +__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE))); + +/* Assert that BL3-1 parameters fit in shared memory */ +CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t)) < + (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), + assert_bl31_params_do_not_fit_in_shared_memory); + +/******************************************************************************* + * Reference to structures which holds the arguments which need to be passed + * to BL31 + ******************************************************************************/ +static bl31_params_t *bl2_to_bl31_params; +static entry_point_info_t *bl31_ep_info; + +meminfo_t *bl2_plat_sec_mem_layout(void) +{ + return &bl2_tzram_layout; +} + +/******************************************************************************* + * This function assigns a pointer to the memory that the platform has kept + * aside to pass platform specific and trusted firmware related information + * to BL31. This memory is allocated by allocating memory to + * bl2_to_bl31_params_mem_t structure which is a superset of all the + * structure whose information is passed to BL31 + * NOTE: This function should be called only once and should be done + * before generating params to BL31 + ******************************************************************************/ +bl31_params_t *bl2_plat_get_bl31_params(void) +{ + bl2_to_bl31_params_mem_t *bl31_params_mem; + + /* + * Allocate the memory for all the arguments that needs to + * be passed to BL31 + */ + bl31_params_mem = (bl2_to_bl31_params_mem_t *)PARAMS_BASE; + memset((void *)PARAMS_BASE, 0, sizeof(bl2_to_bl31_params_mem_t)); + + /* Assign memory for TF related information */ + bl2_to_bl31_params = &bl31_params_mem->bl31_params; + SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); + + /* Fill BL31 related information */ + bl31_ep_info = &bl31_params_mem->bl31_ep_info; + bl2_to_bl31_params->bl31_image_info = &bl31_params_mem->bl31_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, + VERSION_1, 0); + + /* Fill BL32 related information if it exists */ + if (BL32_BASE) { + bl2_to_bl31_params->bl32_ep_info = + &bl31_params_mem->bl32_ep_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, + PARAM_EP, VERSION_1, 0); + bl2_to_bl31_params->bl32_image_info = + &bl31_params_mem->bl32_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, + PARAM_IMAGE_BINARY, + VERSION_1, 0); + } + + /* Fill BL33 related information */ + bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem->bl33_ep_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, + PARAM_EP, VERSION_1, 0); + bl2_to_bl31_params->bl33_image_info = &bl31_params_mem->bl33_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, + VERSION_1, 0); + + return bl2_to_bl31_params; +} + + +/******************************************************************************* + * This function returns a pointer to the shared memory that the platform + * has kept to point to entry point information of BL31 to BL2 + ******************************************************************************/ +struct entry_point_info *bl2_plat_get_bl31_ep_info(void) +{ +#if 0 +#if DEBUG + bl31_ep_info->args.arg1 = RCAR_BL31_PLAT_PARAM_VAL; +#endif +#else + bl31_ep_info->args.arg1 = 0x00000000; /* nomal boot/cold boot */ +#endif + return bl31_ep_info; +} + +#if (RCAR_LOSSY_ENABLE == 1) +/* Settings for Lossy Decompression */ +#define LOSSY_PARAMS_BASE (0x47FD7000U) + +#define AXI_DCMPAREACRA0 (0xE6784100U) +#define AXI_DCMPAREACRB0 (0xE6784104U) + +#define LOSSY_ENABLE (0x80000000U) +#define LOSSY_DISABLE (0x00000000U) + +#define LOSSY_FMT_YUVPLANAR (0x00000000U) +#define LOSSY_FMT_YUV422INTLV (0x20000000U) +#define LOSSY_FMT_ARGB8888 (0x40000000U) + +/* Settings of Entry 0 */ +#define LOSSY_ST_ADDR0 (0x54000000U) +#define LOSSY_END_ADDR0 (0x57000000U) +#define LOSSY_FMT0 LOSSY_FMT_YUVPLANAR +#define LOSSY_ENA_DIS0 LOSSY_ENABLE + +/* Settings of Entry 1 */ +#define LOSSY_ST_ADDR1 0x0 /* Undefined */ +#define LOSSY_END_ADDR1 0x0 /* Undefined */ +#define LOSSY_FMT1 LOSSY_FMT_ARGB8888 +#define LOSSY_ENA_DIS1 LOSSY_DISABLE + +/* Settings of Entry 2 */ +#define LOSSY_ST_ADDR2 0x0 /* Undefined */ +#define LOSSY_END_ADDR2 0x0 /* Undefined */ +#define LOSSY_FMT2 LOSSY_FMT_YUV422INTLV +#define LOSSY_ENA_DIS2 LOSSY_DISABLE + +typedef struct bl2_lossy_info { + uint32_t magic; + uint32_t a0; + uint32_t b0; +} bl2_lossy_info_t; + +void bl2_lossy_setting(uint32_t no, uint32_t start_addr, uint32_t end_addr, + uint32_t format, uint32_t enable) +{ + uint32_t reg; + bl2_lossy_info_t *bl2_lossy_info; + + /* Setting of the start address and format */ + reg = format | (start_addr >> 20); + mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, reg); + + /* Setting of the end address */ + mmio_write_32(AXI_DCMPAREACRB0 + 0x8 * no, + (end_addr >> 20)); + + /* Enable or Disable of Lossy setting */ + mmio_write_32(AXI_DCMPAREACRA0 + 0x8 * no, (reg | enable)); + + bl2_lossy_info = (bl2_lossy_info_t *)(LOSSY_PARAMS_BASE); + bl2_lossy_info += no; + bl2_lossy_info->magic = 0x12345678; + bl2_lossy_info->a0 = mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no); + bl2_lossy_info->b0 = mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no); + + NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, + mmio_read_32(AXI_DCMPAREACRA0 + 0x8 * no), + mmio_read_32(AXI_DCMPAREACRB0 + 0x8 * no)); +} +#endif /* #if (RCAR_LOSSY_ENABLE == 1) */ + +/******************************************************************************* + * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 + * in x0. This memory layout is sitting at the base of the free trusted SRAM. + * Copy it to a safe loaction before its reclaimed by later BL2 functionality. + ******************************************************************************/ +void bl2_early_platform_setup(meminfo_t *mem_layout) +{ + const unsigned int irq_sec_array[] = { + ARM_IRQ_SEC_WDT /* 173 */ + }; + const ROM_GETLCS_API ROM_GetLcs = ROM_GETLCS_API_ADDR; + uint32_t reg; + uint32_t lcs; + uint32_t modemr; + char msg[128]; + const char *str; + const char *cpu_ca57 = "CA57"; + const char *cpu_ca53 = "CA53"; + const char *product_h3 = "H3"; + const char *product_m3 = "M3"; + const char *lcs_cm = "CM"; + const char *lcs_dm = "DM"; + const char *lcs_sd = "SD"; + const char *lcs_secure = "SE"; + const char *lcs_fa = "FA"; + const char *unknown = "unknown"; + + modemr = mmio_read_32(RCAR_MODEMR); + modemr &= MODEMR_BOOT_CPU_MASK; + + if((modemr == MODEMR_BOOT_CPU_CA57) || + (modemr == MODEMR_BOOT_CPU_CA53)) { + /* initialize Pin Function */ + pfc_init(); + } + + /* Initialize CPG configuration */ + bl2_cpg_init(); + + /* Initialize the console to provide early debug support */ + (void)console_init(0U, 0U, 0U); + + /* GIC initialize */ + arm_gic_init(RCAR_GICC_BASE, RCAR_GICD_BASE, RCAR_GICR_BASE + ,irq_sec_array, ARRAY_SIZE(irq_sec_array)); + /* GIC setup */ + arm_gic_setup(); + + /* Enable FIQ interrupt */ + enable_fiq(); + + /* System WDT initialize */ + bl2_swdt_init(); + + bl2_avs_init(); /* Initialize AVS Settings */ + + bl2_avs_setting(); /* Proceed with separated AVS processing */ + + /* boot message */ + reg = (uint32_t)read_midr(); + switch (reg & (uint32_t)(MIDR_PN_MASK << MIDR_PN_SHIFT)) { + case MIDR_CA57: + str = cpu_ca57; + break; + case MIDR_CA53: + str = cpu_ca53; + break; + default: + str = unknown; + break; + } + (void)sprintf(msg, "BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n" + , str, version_of_renesas); + NOTICE("%s", msg); + + bl2_avs_setting(); /* Proceed with separated AVS processing */ + + /* R-Car Gen3 product display & check */ + reg = mmio_read_32(RCAR_PRR); + switch (reg & RCAR_PRODUCT_MASK) { + case RCAR_PRODUCT_H3: + str = product_h3; + break; + case RCAR_PRODUCT_M3: + str = product_m3; + break; + default: + str = unknown; + break; + } + (void)sprintf(msg, "BL2: PRR is R-Car %s ES%d.%d\n", str, + ((reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT) + + RCAR_MAJOR_OFFSET, (reg & RCAR_MINOR_MASK)); + NOTICE("%s", msg); + if((reg & RCAR_PRODUCT_MASK) != TARGET_PRODUCT) { + ERROR("BL2: This IPL has been built for the %s.\n", + TARGET_NAME); + ERROR("BL2: Please write the correct IPL to flash memory.\n"); + panic(); + } + + bl2_avs_setting(); /* Proceed with separated AVS processing */ + + reg = ROM_GetLcs(&lcs); + if (reg == 0U) { + switch (lcs) { + case LCS_CM: + str = lcs_cm; + break; + case LCS_DM: + str = lcs_dm; + break; + case LCS_SD: + str = lcs_sd; + break; + case LCS_SE: + str = lcs_secure; + break; + case LCS_FA: + str = lcs_fa; + break; + default: + str = unknown; + break; + } + } else { + str = unknown; + } + (void)sprintf(msg, "BL2: LCM state is %s\n", str); + NOTICE("%s", msg); + + bl2_avs_setting(); /* Proceed with separated AVS processing */ + + /* Setup the BL2 memory layout */ + bl2_tzram_layout = *mem_layout; + + if((modemr == MODEMR_BOOT_CPU_CA57) || + (modemr == MODEMR_BOOT_CPU_CA53)) { + /* Initialize SDRAM */ + InitDram(); + + bl2_avs_setting();/* Proceed with separated AVS processing */ + + /* initialize QoS configration */ + qos_init(); + + bl2_avs_setting(); /* Proceed with separated AVS processing */ + } + + /* Initialize RPC */ + initRPC(); + + bl2_avs_setting(); /* Proceed with separated AVS processing */ + + /* Initialize DMA */ + initDMA(); + + bl2_avs_setting(); /* Proceed with separated AVS processing */ + + /* Initialize secure configuration */ + bl2_secure_setting(); + + bl2_avs_end(); /* End of AVS Settings */ + + /* unmask the detection of RWDT overflow */ + reg = mmio_read_32(RST_WDTRSTCR); + reg &= ~WDTRSTCR_RWDT_RSTMSK; + reg |= WDTRSTCR_PASSWORD; + mmio_write_32(RST_WDTRSTCR, reg); + + /* Release CPG write protect */ + mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); + mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); + + /* CA5x debug resource control */ + mmio_write_32(CPG_CA57DBGRCR, + DBGCPUPREN | mmio_read_32(CPG_CA57DBGRCR)); + mmio_write_32(CPG_CA53DBGRCR, + DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); + + /* STA restriction check for R-Car H3 WS1.0 */ + reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); + if (reg == RCAR_PRODUCT_H3_CUT10) { + /* PLL0, PLL2, PLL4 setting */ + reg = mmio_read_32(CPG_PLL2CR); + reg &= ~((uint32_t)1U << 5U); /* bit5 = 0 */ + mmio_write_32(CPG_PLL2CR, reg); + + reg = mmio_read_32(CPG_PLL4CR); + reg &= ~((uint32_t)1U << 5U); /* bit5 = 0 */ + mmio_write_32(CPG_PLL4CR, reg); + + reg = mmio_read_32(CPG_PLL0CR); + reg &= ~((uint32_t)1U << 12U); /* bit12 = 0 */ + mmio_write_32(CPG_PLL0CR, reg); + } + +#if (RCAR_LOSSY_ENABLE == 1) + NOTICE("BL2: Lossy Decomp areas\n"); + /* Lossy setting : entry 0 */ + bl2_lossy_setting(0, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, + LOSSY_FMT0, LOSSY_ENA_DIS0); + + /* Lossy setting : entry 1 */ + bl2_lossy_setting(1, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, + LOSSY_FMT1, LOSSY_ENA_DIS1); + + /* Lossy setting : entry 2 */ + bl2_lossy_setting(2, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, + LOSSY_FMT2, LOSSY_ENA_DIS2); +#endif /* #if (RCAR_LOSSY_ENABLE == 1) */ + + /* Initialise the IO layer and register platform IO devices */ + rcar_io_setup(); +} + +/******************************************************************************* + * Perform platform specific setup. For now just initialize the memory location + * to use for passing arguments to BL31. + ******************************************************************************/ +void bl2_platform_setup(void) +{ + /* + * Do initial security configuration to allow DRAM/device access. On + * Base RCAR only DRAM security is programmable (via TrustZone), but + * other platforms might have more programmable security devices + * present. + */ + + /* IPMMU-MM setting for linux */ + mmio_write_32(IPMMUMM_SYSCTRL, 0xC0000000U); + mmio_write_32(IPMMUMM_SYSAUX, 0x01000000U); +} + +/* Flush the TF params and the TF plat params */ +void bl2_plat_flush_bl31_params(void) +{ + uint32_t val; + + /* disable the System WDT, FIQ and GIC */ + bl2_swdt_release(); + + /* Finalize a console of provide early debug support */ + console_finalize(); + + /* Disable instruction cache */ + val = (uint32_t)read_sctlr_el1(); + val &= ~((uint32_t)SCTLR_I_BIT); + write_sctlr_el1((uint64_t)val); + isb(); + + /* Invalidate instruction cache */ + iciallu(); + dsb(); + isb(); +} + + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the mmu in a quick and dirty way. + ******************************************************************************/ +void bl2_plat_arch_setup(void) +{ +#if 0 + rcar_configure_mmu_el1(bl2_tzram_layout.total_base, + bl2_tzram_layout.total_size, + BL2_RO_BASE, + BL2_RO_LIMIT +#if USE_COHERENT_MEM + , BL2_COHERENT_RAM_BASE, + BL2_COHERENT_RAM_LIMIT +#endif + ); +#endif +} + +/******************************************************************************* + * Before calling this function BL31 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL31 and set SPSR and security state. + * On RCAR we are only setting the security state, entrypoint + ******************************************************************************/ +void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, + entry_point_info_t *bl31_ep_info) +{ + SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); + bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); +} + + +/******************************************************************************* + * Before calling this function BL32 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL32 and set SPSR and security state. + * On RCAR we are only setting the security state, entrypoint + ******************************************************************************/ +void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, + entry_point_info_t *bl32_ep_info) +{ + SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); + bl32_ep_info->spsr = rcar_get_spsr_for_bl32_entry(); +} + +/******************************************************************************* + * Before calling this function BL33 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL33 and set SPSR and security state. + * On RCAR we are only setting the security state, entrypoint + ******************************************************************************/ +void bl2_plat_set_bl33_ep_info(image_info_t *image, + entry_point_info_t *bl33_ep_info) +{ + SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); + bl33_ep_info->spsr = rcar_get_spsr_for_bl33_entry(); +} + + +/******************************************************************************* + * Populate the extents of memory available for loading BL32 + ******************************************************************************/ +void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) +{ + /* + * Populate the extents of memory available for loading BL32. + */ + bl32_meminfo->total_base = BL32_BASE; + bl32_meminfo->free_base = BL32_BASE; + bl32_meminfo->total_size = BL32_BASE; + bl32_meminfo->free_size = BL32_LIMIT - BL32_BASE; +} + + +/******************************************************************************* + * Populate the extents of memory available for loading BL33 + ******************************************************************************/ +void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) +{ + bl33_meminfo->total_base = DRAM1_NS_BASE; + bl33_meminfo->total_size = DRAM1_NS_SIZE; + bl33_meminfo->free_base = DRAM1_NS_BASE; + bl33_meminfo->free_size = DRAM1_NS_SIZE; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl2_secure_setting.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl2_secure_setting.c new file mode 100644 index 0000000..9498db9 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl2_secure_setting.c @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "bl2_lifec_register.h" +#include "bl2_axi_register.h" +#include "bl2_secure_setting.h" +#include "mmio.h" + +static void lifec_security_setting(void); +static void axi_security_setting(void); + +static const struct { + uint32_t adr; + uint32_t val; +} lifec_reg_setting[] = { + + /* LIFEC0 (SECURITY) settings */ + + /* Security attribute setting for master ports */ + /* Bit 0: ARM realtime core (Cortex-R7) master port. */ + /* 0: Non-Secure */ + {SEC_SRC, 0x0000001EU}, + + /** Security attribute setting for slave ports 0 */ + /* {SEC_SEL0, 0xFFFFFFFFU},*/ + + /** Security attribute setting for slave ports 1 */ + /* {SEC_SEL1, 0xFFFFFFFFU},*/ + + /** Security attribute setting for slave ports 2 */ + /* {SEC_SEL2, 0xFFFFFFFFU},*/ + + /** Security attribute setting for slave ports 3 */ + /* Bit19: AXI-Bus (Main Memory domain AXI) slave ports. */ + /* 0: registers can be accessed from secure resource only. */ + /* Bit 9: DBSC4 register access slave ports. */ + /* 0: registers can be accessed from secure resource only. */ + {SEC_SEL3, 0xFFF7FDFFU}, + + /** Security attribute setting for slave ports 4 */ + /* {SEC_SEL4, 0xFFFFFFFFU},*/ + + /** Security attribute setting for slave ports 5 */ + /* Bit 6: Boot ROM slave ports. */ + /* 0: registers can be accessed from secure resource only. */ + {SEC_SEL5, 0xFFFFFFBFU}, + + /** Security attribute setting for slave ports 6 */ + /* Bit13: SCEG PKA (secure APB) slave ports. */ + /* 0: registers can be accessed from secure resource only. */ + /* Bit12: SCEG PKA (public APB) slave ports. */ + /* 0: registers can be accessed from secure resource only. */ + /* Bit10: SCEG Secure Core slave ports. */ + /* 0: registers can be accessed from secure resource only. */ + {SEC_SEL6, 0xFFFFCBFFU}, + + /** Security attribute setting for slave ports 7 */ + /* {SEC_SEL7, 0xFFFFFFFFU},*/ + + /** Security attribute setting for slave ports 8 */ + /* {SEC_SEL8, 0xFFFFFFFFU},*/ + + /** Security attribute setting for slave ports 9 */ + /* {SEC_SEL9, 0xFFFFFFFFU},*/ + + /** Security attribute setting for slave ports 10 */ + /* {SEC_SEL10, 0xFFFFFFFFU},*/ + + /** Security attribute setting for slave ports 11 */ + /* {SEC_SEL11, 0xFFFFFFFFU},*/ + + /** Security attribute setting for slave ports 12 */ + /* {SEC_SEL12, 0xFFFFFFFFU},*/ + + /** Security attribute setting for slave ports 13 */ + /* Bit22: RPC slave ports. */ + /* 0: registers can be accessed from secure resource only. */ + {SEC_SEL13, 0xFFBFFFFFU}, + + /** Security attribute setting for slave ports 14 */ + /* Bit27: System Timer (SCMT) slave ports. */ + /* 0: registers can be accessed from secure resource only. */ + /* Bit26: System Watchdog Timer (SWDT) slave ports. */ + /* 0: registers can be accessed from secure resource only. */ + {SEC_SEL14, 0xF3FFFFFFU}, + + /** Security attribute setting for slave ports 15 */ + /* Bit13: RST slave ports. */ + /* 0: registers can be accessed from secure resource only. */ + /* Bit 7: Life Cycle 0 slave ports. */ + /* 0: registers can be accessed from secure resource only. */ + {SEC_SEL15, 0xFFFFFF3FU}, + + /** Security group 0 attribute setting for master ports 0 */ + /** Security group 1 attribute setting for master ports 0 */ + /* {SEC_GRP0CR0, 0x00000000U},*/ + /* {SEC_GRP1CR0, 0x00000000U},*/ + + /** Security group 0 attribute setting for master ports 1 */ + /** Security group 1 attribute setting for master ports 1 */ + /* {SEC_GRP0CR1, 0x00000000U},*/ + /* {SEC_GRP1CR1, 0x00000000U},*/ + + /** Security group 0 attribute setting for master ports 2 */ + /** Security group 1 attribute setting for master ports 2 */ + /* Bit17: SCEG Secure Core master ports. */ + /* SecurityGroup3 */ + {SEC_GRP0CR2, 0x00020000U}, + {SEC_GRP1CR2, 0x00020000U}, + + /** Security group 0 attribute setting for master ports 3 */ + /** Security group 1 attribute setting for master ports 3 */ + /* {SEC_GRP0CR3, 0x00000000U},*/ + /* {SEC_GRP1CR3, 0x00000000U},*/ + + /** Security group 0 attribute setting for slave ports 0 */ + /** Security group 1 attribute setting for slave ports 0 */ + /* {SEC_GRP0COND0, 0x00000000U},*/ + /* {SEC_GRP1COND0, 0x00000000U},*/ + + /** Security group 0 attribute setting for slave ports 1 */ + /** Security group 1 attribute setting for slave ports 1 */ + /* {SEC_GRP0COND1, 0x00000000U},*/ + /* {SEC_GRP1COND1, 0x00000000U},*/ + + /** Security group 0 attribute setting for slave ports 2 */ + /** Security group 1 attribute setting for slave ports 2 */ + /* {SEC_GRP0COND2, 0x00000000U},*/ + /* {SEC_GRP1COND2, 0x00000000U},*/ + + /** Security group 0 attribute setting for slave ports 3 */ + /** Security group 1 attribute setting for slave ports 3 */ + /* Bit19: AXI-Bus (Main Memory domain AXI) slave ports. */ + /* SecurityGroup3 */ + /* Bit 9: DBSC4 register access slave ports. */ + /* SecurityGroup3 */ + {SEC_GRP0COND3, 0x00080200U}, + {SEC_GRP1COND3, 0x00080200U}, + + /** Security group 0 attribute setting for slave ports 4 */ + /** Security group 1 attribute setting for slave ports 4 */ + /* {SEC_GRP0COND4, 0x00000000U},*/ + /* {SEC_GRP1COND4, 0x00000000U},*/ + + /** Security group 0 attribute setting for slave ports 5 */ + /** Security group 1 attribute setting for slave ports 5 */ + /* Bit 6: Boot ROM slave ports. */ + /* SecurityGroup3 */ + {SEC_GRP0COND5, 0x00000040U}, + {SEC_GRP1COND5, 0x00000040U}, + + /** Security group 0 attribute setting for slave ports 6 */ + /** Security group 1 attribute setting for slave ports 6 */ + /* Bit13: SCEG PKA (secure APB) slave ports. */ + /* SecurityGroup3 */ + /* Bit12: SCEG PKA (public APB) slave ports. */ + /* SecurityGroup3 */ + /* Bit10: SCEG Secure Core slave ports. */ + /* SecurityGroup3 */ + {SEC_GRP0COND6, 0x00003400U}, + {SEC_GRP1COND6, 0x00003400U}, + + /** Security group 0 attribute setting for slave ports 7 */ + /** Security group 1 attribute setting for slave ports 7 */ + /* {SEC_GRP0COND7, 0x00000000U},*/ + /* {SEC_GRP1COND7, 0x00000000U},*/ + + /** Security group 0 attribute setting for slave ports 8 */ + /** Security group 1 attribute setting for slave ports 8 */ + /* {SEC_GRP0COND8, 0x00000000U},*/ + /* {SEC_GRP1COND8, 0x00000000U},*/ + + /** Security group 0 attribute setting for slave ports 9 */ + /** Security group 1 attribute setting for slave ports 9 */ + /* {SEC_GRP0COND9, 0x00000000U},*/ + /* {SEC_GRP1COND9, 0x00000000U},*/ + + /** Security group 0 attribute setting for slave ports 10 */ + /** Security group 1 attribute setting for slave ports 10 */ + /* {SEC_GRP0COND10, 0x00000000U},*/ + /* {SEC_GRP1COND10, 0x00000000U},*/ + + /** Security group 0 attribute setting for slave ports 11 */ + /** Security group 1 attribute setting for slave ports 11 */ + /* {SEC_GRP0COND11, 0x00000000U},*/ + /* {SEC_GRP1COND11, 0x00000000U},*/ + + /** Security group 0 attribute setting for slave ports 12 */ + /** Security group 1 attribute setting for slave ports 12 */ + /* {SEC_GRP0COND12, 0x00000000U},*/ + /* {SEC_GRP1COND12, 0x00000000U},*/ + + /** Security group 0 attribute setting for slave ports 13 */ + /** Security group 1 attribute setting for slave ports 13 */ + /* Bit22: RPC slave ports. */ + /* SecurityGroup3 */ + {SEC_GRP0COND13, 0x00400000U}, + {SEC_GRP1COND13, 0x00400000U}, + + /** Security group 0 attribute setting for slave ports 14 */ + /** Security group 1 attribute setting for slave ports 14 */ + /* Bit26: System Timer (SCMT) slave ports. */ + /* SecurityGroup3 */ + /* Bit27: System Watchdog Timer (SWDT) slave ports. */ + /* SecurityGroup3 */ + {SEC_GRP0COND14, 0x0C000000U}, + {SEC_GRP1COND14, 0x0C000000U}, + + /** Security group 0 attribute setting for slave ports 15 */ + /** Security group 1 attribute setting for slave ports 15 */ + /* Bit13: RST slave ports. */ + /* SecurityGroup3 */ + /* Bit 7: Life Cycle 0 slave ports. */ + /* SecurityGroup3 */ + /* Bit 6: TDBG (is described in Debug and Trace section) slave ports.*/ + /* SecurityGroup3 */ + {SEC_GRP0COND15, 0x000000C0U}, + {SEC_GRP1COND15, 0x000000C0U}, + + /** Security write protection attribute setting for slave ports 0 */ + /* {SEC_READONLY0, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 1 */ + /* {SEC_READONLY1, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 2 */ + /* {SEC_READONLY2, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 3 */ + /* {SEC_READONLY3, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 4 */ + /* {SEC_READONLY4, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 5 */ + /* {SEC_READONLY5, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 6 */ + /* {SEC_READONLY6, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 7 */ + /* {SEC_READONLY7, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 8 */ + /* {SEC_READONLY8, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 9 */ + /* {SEC_READONLY9, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 10 */ + /* {SEC_READONLY10, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 11 */ + /* {SEC_READONLY11, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 12 */ + /* {SEC_READONLY12, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 13 */ + /* {SEC_READONLY13, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 14 */ + /* {SEC_READONLY14, 0x00000000U},*/ + + /** Security write protection attribute setting for slave ports 15 */ + /* {SEC_READONLY15, 0x00000000U}*/ + +}; + + /* AXI settings */ +static const struct { + uint32_t adr; + uint32_t val; +} axi_reg_setting[] = { + + /* DRAM protection */ + + /* AXI dram protected area division */ + {AXI_DPTDIVCR0, 0x0E0403F0U}, + {AXI_DPTDIVCR1, 0x0E0407E0U}, + {AXI_DPTDIVCR2, 0x0E080000U}, + {AXI_DPTDIVCR3, 0x0E080000U}, + {AXI_DPTDIVCR4, 0x0E080000U}, + {AXI_DPTDIVCR5, 0x0E080000U}, + {AXI_DPTDIVCR6, 0x0E080000U}, + {AXI_DPTDIVCR7, 0x0E080000U}, + {AXI_DPTDIVCR8, 0x0E080000U}, + {AXI_DPTDIVCR9, 0x0E080000U}, + {AXI_DPTDIVCR10, 0x0E080000U}, + {AXI_DPTDIVCR11, 0x0E080000U}, + {AXI_DPTDIVCR12, 0x0E080000U}, + {AXI_DPTDIVCR13, 0x0E080000U}, + {AXI_DPTDIVCR14, 0x0E080000U}, + + /* AXI dram protected area setting */ + {AXI_DPTCR0, 0x0E000000U}, + {AXI_DPTCR1, 0x0E000E0EU}, + {AXI_DPTCR2, 0x0E000000U}, + {AXI_DPTCR3, 0x0E000000U}, + {AXI_DPTCR4, 0x0E000000U}, + {AXI_DPTCR5, 0x0E000000U}, + {AXI_DPTCR6, 0x0E000000U}, + {AXI_DPTCR7, 0x0E000000U}, + {AXI_DPTCR8, 0x0E000000U}, + {AXI_DPTCR9, 0x0E000000U}, + {AXI_DPTCR10, 0x0E000000U}, + {AXI_DPTCR11, 0x0E000000U}, + {AXI_DPTCR12, 0x0E000000U}, + {AXI_DPTCR13, 0x0E000000U}, + {AXI_DPTCR14, 0x0E000000U}, + {AXI_DPTCR15, 0x0E000000U}, + + + /* SRAM ptotection */ + + /* AXI sram protected area division */ + {AXI_SPTDIVCR0, 0x0E0E6320U}, + {AXI_SPTDIVCR1, 0x0E0E6360U}, + {AXI_SPTDIVCR2, 0x0E0E6360U}, + {AXI_SPTDIVCR3, 0x0E0E6360U}, + {AXI_SPTDIVCR4, 0x0E0E6360U}, + {AXI_SPTDIVCR5, 0x0E0E6360U}, + {AXI_SPTDIVCR6, 0x0E0E6360U}, + {AXI_SPTDIVCR7, 0x0E0E6360U}, + {AXI_SPTDIVCR8, 0x0E0E6360U}, + {AXI_SPTDIVCR9, 0x0E0E6360U}, + {AXI_SPTDIVCR10, 0x0E0E6360U}, + {AXI_SPTDIVCR11, 0x0E0E6360U}, + {AXI_SPTDIVCR12, 0x0E0E6360U}, + {AXI_SPTDIVCR13, 0x0E0E6360U}, + {AXI_SPTDIVCR14, 0x0E0E6360U}, + + /* AXI sram protected area setting */ + {AXI_SPTCR0, 0x0E000E0EU}, + {AXI_SPTCR1, 0x0E000000U}, + {AXI_SPTCR2, 0x0E000000U}, + {AXI_SPTCR3, 0x0E000000U}, + {AXI_SPTCR4, 0x0E000000U}, + {AXI_SPTCR5, 0x0E000000U}, + {AXI_SPTCR6, 0x0E000000U}, + {AXI_SPTCR7, 0x0E000000U}, + {AXI_SPTCR8, 0x0E000000U}, + {AXI_SPTCR9, 0x0E000000U}, + {AXI_SPTCR10, 0x0E000000U}, + {AXI_SPTCR11, 0x0E000000U}, + {AXI_SPTCR12, 0x0E000000U}, + {AXI_SPTCR13, 0x0E000000U}, + {AXI_SPTCR14, 0x0E000000U}, + {AXI_SPTCR15, 0x0E000000U} + +}; + +/* Port access security setting */ +static void lifec_security_setting(void) +{ + int32_t i, ie; + + i = 0; + ie = (int32_t)(sizeof(lifec_reg_setting) / sizeof(lifec_reg_setting[0])); + for (; i < ie; i++) { + mmio_write_32((uintptr_t)lifec_reg_setting[i].adr, + lifec_reg_setting[i].val); + } +} + +/* SRAM/DRAM protection setting */ +static void axi_security_setting(void) +{ + int32_t i, ie; + + i = 0; + ie = (int32_t)(sizeof(axi_reg_setting) / sizeof(axi_reg_setting[0])); + for (; i < ie; i++) { + mmio_write_32((uintptr_t)axi_reg_setting[i].adr, + axi_reg_setting[i].val); + } +} + +void bl2_secure_setting(void) +{ + lifec_security_setting(); + + axi_security_setting(); + + return; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl31_rcar_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl31_rcar_setup.c new file mode 100644 index 0000000..f8e68d2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl31_rcar_setup.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "drivers/pwrc/rcar_pwrc.h" +#include "rcar_def.h" +#include "rcar_private.h" +#include "rcar_version.h" + +#define CHECK_MD13_MD14 (0x6000U) +#define FREQ_10M (0x2000U) +#define FREQ_12_5M (0x4000U) +#define FREQ_8_33M (0x0000U) +#define FREQ_16_66M (0x6000U) + +/******************************************************************************* + * Declarations of linker defined symbols which will help us find the layout + * of trusted SRAM + ******************************************************************************/ +extern unsigned long __RO_START__; +extern unsigned long __RO_END__; +extern unsigned long __BL31_END__; + +#if USE_COHERENT_MEM +extern unsigned long __COHERENT_RAM_START__; +extern unsigned long __COHERENT_RAM_END__; +#endif + +/* + * The next 3 constants identify the extents of the code, RO data region and the + * limit of the BL3-1 image. These addresses are used by the MMU setup code and + * therefore they must be page-aligned. It is the responsibility of the linker + * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_RO_BASE (uint64_t)(&__RO_START__) +#define BL31_RO_LIMIT (uint64_t)(&__RO_END__) +#define BL31_END (uint64_t)(&__BL31_END__) + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_COHERENT_RAM_BASE (uint64_t)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (uint64_t)(&__COHERENT_RAM_END__) +#endif + +#if RESET_TO_BL31 +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; +#else +/******************************************************************************* + * Reference to structure which holds the arguments that have been passed to + * BL31 from BL2. + ******************************************************************************/ +static bl31_params_t *bl2_to_bl31_params; +#endif + +/* Array of secure interrupts to be configured by the gic driver */ +const unsigned int irq_sec_array[] = { + ARM_IRQ_SEC_PHY_TIMER, /* 29 */ + ARM_IRQ_SEC_SGI_0, /* 8 */ + ARM_IRQ_SEC_SGI_1, /* 9 */ + ARM_IRQ_SEC_SGI_2, /* 10 */ + ARM_IRQ_SEC_SGI_3, /* 11 */ + ARM_IRQ_SEC_SGI_4, /* 12 */ + ARM_IRQ_SEC_SGI_5, /* 13 */ + ARM_IRQ_SEC_SGI_6, /* 14 */ + ARM_IRQ_SEC_SGI_7, /* 15 */ + ARM_IRQ_SEC_RPC, /* 70 */ + ARM_IRQ_SEC_TIMER, /* 166 */ + ARM_IRQ_SEC_TIMER_UP, /* 171 */ + ARM_IRQ_SEC_WDT, /* 173 */ + ARM_IRQ_SEC_CRYPT, /* 102 */ + ARM_IRQ_SEC_CRYPT_SecPKA, /* 97 */ + ARM_IRQ_SEC_CRYPT_PubPKA /* 98 */ +}; + +uint32_t rcar_boot_kind_flag __attribute__((section("data"))); + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for the + * security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + assert(sec_state_is_valid(type)); + + next_image_info = + (type == NON_SECURE) ? + bl2_to_bl31_params->bl33_ep_info : + bl2_to_bl31_params->bl32_ep_info; + + /* None of the images on this platform can have 0x0 as the entrypoint */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +/******************************************************************************* + * Perform any BL31 specific platform actions. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2) before they + * are lost (potentially). This needs to be done before the MMU is initialized + * so that the memory layout can be used while creating page tables. On the RCAR + * we know that BL2 has populated the parameters. So we just use + * the reference passed in 'from_bl2' instead of copying. The 'data' parameter + * is not used since all the information is contained in 'from_bl2'. Also, BL2 + * has flushed this information to memory, so we are guaranteed to pick up good + * data + ******************************************************************************/ +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +{ + uint32_t chk_data; + uint32_t freq_data; + uint32_t product_cut = mmio_read_32((uintptr_t)RCAR_PRR) + & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); + + /* + * Set frequency data to CNTFID0 + */ + chk_data = mmio_read_32((uintptr_t)RCAR_MODEMR) & CHECK_MD13_MD14; + switch (chk_data) { + case FREQ_8_33M: + freq_data = 8333300U; /* 8.33MHz */ + break; + case FREQ_10M: + freq_data = 10000000U; /* 10MHz */ + break; + case FREQ_12_5M: + freq_data = 12500000U; /* 12.5MHz */ + break; + case FREQ_16_66M: + freq_data = 16666600U; /* 16.66MHz */ + if (product_cut == (RCAR_PRODUCT_H3 | RCAR_CUT_ES10)) { + freq_data = freq_data >> 1; + } + break; + default: + freq_data = 0U; + break; + } + mmio_write_32(RCAR_CNTC_BASE + CNTFID_OFF, freq_data); + + /* Initialize the log area to provide early debug support */ + console_init(1U, 0U, 0U); + + NOTICE("BL3-1 : Rev.%s\n",version_of_renesas); + + /* Check params passed from BL2 should not be NULL, + * We are not checking plat_params_from_bl2 as NULL as we are not + * using it on RCAR + */ + assert(from_bl2 != NULL); + assert(from_bl2->h.type == PARAM_BL31); + assert(from_bl2->h.version >= VERSION_1); + + bl2_to_bl31_params = from_bl2; + + /* + * Initialize CCI for this cluster during cold boot. + * No need for locks as no other CPU is active. + */ + rcar_cci_init(); + /* + * Enable CCI coherency for the primary CPU's cluster + * RCAR PSCI code will enable coherency for other clusters. + */ + rcar_cci_enable(); + +} + +/******************************************************************************* + * Initialize the gic, configure the CLCD and zero out variables needed by the + * secondaries to boot up correctly. + ******************************************************************************/ +void bl31_platform_setup(void) +{ + + /* Initialize the gic cpu and distributor interfaces */ + arm_gic_init(RCAR_GICC_BASE, RCAR_GICD_BASE, RCAR_GICR_BASE, + irq_sec_array, ARRAY_SIZE(irq_sec_array)); + arm_gic_setup(); + + /* Enable and initialize the System level generic timer */ + mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); + + /* Intialize the power controller */ + rcar_pwrc_setup(); + + /* Topologies are best known to the platform. */ + rcar_setup_topology(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the mmu in a quick and dirty way. + ******************************************************************************/ +void bl31_plat_arch_setup(void) +{ + rcar_configure_mmu_el3(BL31_RO_BASE, (BL31_END - BL31_RO_BASE), + BL31_RO_BASE, + BL31_RO_LIMIT +#if USE_COHERENT_MEM + , BL31_COHERENT_RAM_BASE, + BL31_COHERENT_RAM_LIMIT +#endif + ); + +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl33_rcar_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl33_rcar_setup.c new file mode 100644 index 0000000..9a3ee9c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/bl33_rcar_setup.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "drivers/pwrc/rcar_pwrc.h" +#include "rcar_def.h" +#include "rcar_private.h" +#include "rcar_version.h" + + +/* Product Register */ +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) +#define PRR_MAJOR_MASK (0x000000F0U) +#define PRR_MINOR_MASK (0x0000000FU) +#define PRR_PRODUCT_SHIFT (8U) +#define PRR_MAJOR_SHIFT (4U) +#define PRR_MINOR_SHIFT (0U) +#define PRR_MAJOR_OFFSET (1U) +#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */ +#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ +#define PRR_PRODUCT_H3_ES_1_0 (0x00004F00U) /* R-Car H3 ES1.0 */ +#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */ + +/* MIDR */ +#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT) +#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT) + + +/* Array of secure interrupts to be configured by the gic driver */ +//const unsigned int irq_sec_array[] = { +// ARM_IRQ_SEC_PHY_TIMER, /* 29 */ +// ARM_IRQ_SEC_SGI_0, /* 8 */ +// ARM_IRQ_SEC_SGI_1, /* 9 */ +// ARM_IRQ_SEC_SGI_2, /* 10 */ +// ARM_IRQ_SEC_SGI_3, /* 11 */ +// ARM_IRQ_SEC_SGI_4, /* 12 */ +// ARM_IRQ_SEC_SGI_5, /* 13 */ +// ARM_IRQ_SEC_SGI_6, /* 14 */ +// ARM_IRQ_SEC_SGI_7, /* 15 */ +// ARM_IRQ_SEC_RPC, /* 70 */ +// ARM_IRQ_SEC_TIMER, /* 166 */ +// ARM_IRQ_SEC_TIMER_UP, /* 171 */ +// ARM_IRQ_SEC_WDT, /* 173 */ +// ARM_IRQ_SEC_CRYPT, /* 102 */ +// ARM_IRQ_SEC_CRYPT_SecPKA, /* 97 */ +// ARM_IRQ_SEC_CRYPT_PubPKA, /* 98 */ +// ARM_IRQ_SEC_DMAC2_ERR, /* 448 */ +// ARM_IRQ_SEC_DMAC2_0, /* 449 */ +// ARM_IRQ_SEC_DMAC2_1, /* 450 */ +// ARM_IRQ_SEC_DMAC2_2, /* 451 */ +// ARM_IRQ_SEC_DMAC2_3, /* 452 */ +// ARM_IRQ_SEC_DMAC2_4, /* 453 */ +// ARM_IRQ_SEC_DMAC2_5, /* 454 */ +// ARM_IRQ_SEC_DMAC2_6, /* 455 */ +// ARM_IRQ_SEC_DMAC2_7, /* 456 */ +// ARM_IRQ_SEC_DMAC2_8, /* 457 */ +// ARM_IRQ_SEC_DMAC2_9, /* 458 */ +// ARM_IRQ_SEC_DMAC2_10, /* 459 */ +// ARM_IRQ_SEC_DMAC2_11, /* 460 */ +// ARM_IRQ_SEC_DMAC2_12, /* 461 */ +// ARM_IRQ_SEC_DMAC2_13, /* 462 */ +// ARM_IRQ_SEC_DMAC2_14, /* 463 */ +// ARM_IRQ_SEC_DMAC2_15 /* 429 */ +//}; + +/******************************************************************************* + * Perform any BL31 specific platform actions. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2) before they + * are lost (potentially). This needs to be done before the MMU is initialized + * so that the memory layout can be used while creating page tables. On the RCAR + * we know that BL2 has populated the parameters. So we just use + * the reference passed in 'from_bl2' instead of copying. The 'data' parameter + * is not used since all the information is contained in 'from_bl2'. Also, BL2 + * has flushed this information to memory, so we are guaranteed to pick up good + * data + ******************************************************************************/ +void bl33_early_platform_setup(void) +{ + uint32_t reg; + const char *str; + const char *cpu_ca57 = "CA57"; + const char *cpu_ca53 = "CA53"; + const char *product_h3 = "H3"; + const char *product_m3 = "M3"; + const char *product_v3m = "V3M"; + const char *unknown = "unknown"; + + /* Initialize the log area to provide early debug support */ + console_init(1U, 0U, 0U); + + /* boot message */ + reg = (uint32_t)read_midr(); + switch (reg & (MIDR_PN_MASK << MIDR_PN_SHIFT)) { + case MIDR_CA57: + str = cpu_ca57; + break; + case MIDR_CA53: + str = cpu_ca53; + break; + default: + str = unknown; + } + NOTICE("BL3-3: R-Car H3/M3/V3M Dummy BL33(%s) Rev.%s\n", + str, version_of_renesas); + + /* product version */ + reg = mmio_read_32(PRR); + switch (reg & PRR_PRODUCT_MASK) { + case PRR_PRODUCT_H3: + str = product_h3; + break; + case PRR_PRODUCT_M3: + str = product_m3; + break; + case PRR_PRODUCT_V3M: + str = product_v3m; + break; + default: + str = unknown; + } + NOTICE("BL3-3: PRR is R-Car %s Ver%d.%d\n", str, + ((reg & PRR_MAJOR_MASK) >> PRR_MAJOR_SHIFT) + PRR_MAJOR_OFFSET, + (reg & PRR_MINOR_MASK) >> PRR_MINOR_SHIFT); +} + +/******************************************************************************* + * Initialize the gic, configure the CLCD and zero out variables needed by the + * secondaries to boot up correctly. + ******************************************************************************/ +void bl33_platform_setup(void) +{ + + /* Initialize the gic cpu and distributor interfaces */ +// arm_gic_init(RCAR_GICC_BASE, RCAR_GICD_BASE, RCAR_GICR_BASE, +// irq_sec_array, ARRAY_SIZE(irq_sec_array)); +// arm_gic_setup(); + + /* Enable and initialize the System level generic timer */ +// mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); + + /* Intialize the power controller */ +// rcar_pwrc_setup(); + + /* Topologies are best known to the platform. */ +// rcar_setup_topology(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the mmu in a quick and dirty way. + ******************************************************************************/ +void bl33_plat_arch_setup(void) +{ +// rcar_configure_mmu_el3(BL31_RO_BASE, (BL31_END - BL31_RO_BASE), +// BL31_RO_BASE, +// BL31_RO_LIMIT +//#if USE_COHERENT_MEM +// , BL31_COHERENT_RAM_BASE, +// BL31_COHERENT_RAM_LIMIT +//#endif +// ); + +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/H3/ES10/boot_init_dram_h3_es10.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/H3/ES10/boot_init_dram_h3_es10.c new file mode 100644 index 0000000..328cd43 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/H3/ES10/boot_init_dram_h3_es10.c @@ -0,0 +1,3379 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "boot_init_dram_h3_es10.h" + +#include //for uint32_t +#include //for uint32_t +#include //for uint32_t +#include "init_dram_tbl_h3_es10.h" +//#include "bit.h" +//#include "reg_rcarh3.h" + + +#define RCAR_DDR_VERSION "rev.0.10" + + +/////////////////////////////////////////////////////////// +/* add start */ +#include +#define RST_BASE (0xE6160000U) +#define RST_MODEMR (RST_BASE + 0x0060U) +#define CPG_BASE (0xE6150000U) +#define CPG_PLLECR (CPG_BASE + 0x00D0U) +#define CPG_CPGWPR (CPG_BASE + 0x900U) +#define CPG_PLL3CR (CPG_BASE + 0x0DCU) +#define CPG_SRCR4 (CPG_BASE + 0x0BCU) +#define CPG_SRSTCLR4 (CPG_BASE + 0x950U) +/////////////////////////////////////////////////////////// + + +#define DDR_LVLEN 0x1e +#define DDR_FDIV 0x0 +#define DDR_FDIVA 0x0 +#define DDR_PLL3ONLY + +#define DDR_DRIVE 0x1 +#define DDR_LPDDR4_EN_OFF_FIRST 0x1 +#define DDR_LP4_BOOT_DISABLE 0x1 + +#define DDR_PAD_BOOST 0x0 +#define DDR_PAD_ADDR_CS_DRIVE 0x7f2c + +#define DDR_PVTR_ADJ 0x8 + +#define DDR_RX_CAL_MAN 0x033f + +#define DDR_MR3 0x31 +#define DDR_MR11 0x32 // 120 ohm +#define DDR_MR22 0x06 + +#define DDR_TSEL_SELECT 0x00002C0C + +#define DDR_VREF 0x0F1F + +#define DDR_PAD_CAL_WA + +#define DDR_UPDT_WA 0x1c48 +#define DDR_FREQCHG + +#define DDR_RDDQSDQ 0x0 +#define DDR_CALVLSIDE 0x2 +#define DDR_LOWDIV 0x4 +#define DDR_LOWFIX 0x17 + +#define DDR_BPGRP 0x000 +#define DDR_BPCAD 0x000 + +#define DDR_PHYVALID 0xf +#define DDR_PHYMRW 0xf + +#define DDR_TVAL0 0 +#define DDR_TVAL1 0 +#define DDR_TVAL2 0 +#define DDR_DBS_DFI_WA + +#define DDR_CAD 0x200 +#define DDR_GRP_A 0x200 +#define DDR_GRP_B 0x200 + +#define DDR_PVTCODE_0 0x10 +#define DDR_PVTCODE_1 0x20 +#define DDR_PVTCODE_2 0x20 + +#define DDR1600_CLK 0x2F // 1600 +#define DDR2400_CLK 0x47 // 2400 +#define DDR2800_CLK 0x53 // 2800 +#define DDR3200_CLK 0x5f // 3100 + +// 9/24 +#define DDR_CACS_CAPTURE_CNT 0x02 +#define DDR_CACS_RESP_WAIT_CNT 0x00 +#define DDR_CACS_CCCP 0x2816 +#define DDR_CACS_START 0x280 // 0x320 +#define DDR_CACS_QTR 0x80 // 0x40 +#define DDR_CACS_STEP 0x03 + +#define DBSC_DBSYSCONF1 0xE6790004 +#define DBSC_DBPHYCONF0 0xE6790010 // +#define DBSC_DBKIND 0xE6790020 // + +#define DBSC_DBMEMCONF_0_0 0xE6790030 +#define DBSC_DBMEMCONF_0_1 0xE6790034 +#define DBSC_DBMEMCONF_1_0 0xE6790040 +#define DBSC_DBMEMCONF_1_1 0xE6790044 +#define DBSC_DBMEMCONF_2_0 0xE6790050 +#define DBSC_DBMEMCONF_2_1 0xE6790054 +#define DBSC_DBMEMCONF_3_0 0xE6790060 +#define DBSC_DBMEMCONF_3_1 0xE6790064 + +#define DBSC_DBMEMCONF_0_2 0xE6790038 +#define DBSC_DBMEMCONF_0_3 0xE679003C +#define DBSC_DBMEMCONF_1_2 0xE6790048 +#define DBSC_DBMEMCONF_1_3 0xE679004C +#define DBSC_DBMEMCONF_2_2 0xE6790058 +#define DBSC_DBMEMCONF_2_3 0xE679005C +#define DBSC_DBMEMCONF_3_2 0xE6790068 +#define DBSC_DBMEMCONF_3_3 0xE679006C + +#define DBSC_DBSTATE0 0xE6790108 + +#define DBSC_DBACEN 0xE6790200 +#define DBSC_DBRFEN 0xE6790204 +#define DBSC_DBCMD 0xE6790208 +#define DBSC_DBWAIT 0xE6790210 //wait DBCMD 1=busy, 0=ready + +#define DBSC_DBTR0 0xE6790300 +#define DBSC_DBTR1 0xE6790304 +#define DBSC_DBTR3 0xE679030C +#define DBSC_DBTR4 0xE6790310 +#define DBSC_DBTR5 0xE6790314 +#define DBSC_DBTR6 0xE6790318 +#define DBSC_DBTR7 0xE679031C +#define DBSC_DBTR8 0xE6790320 +#define DBSC_DBTR9 0xE6790324 +#define DBSC_DBTR10 0xE6790328 +#define DBSC_DBTR11 0xE679032C +#define DBSC_DBTR12 0xE6790330 +#define DBSC_DBTR13 0xE6790334 +#define DBSC_DBTR14 0xE6790338 +#define DBSC_DBTR15 0xE679033C +#define DBSC_DBTR16 0xE6790340 +#define DBSC_DBTR17 0xE6790344 +#define DBSC_DBTR18 0xE6790348 +#define DBSC_DBTR19 0xE679034C +#define DBSC_DBTR20 0xE6790350 +#define DBSC_DBTR21 0xE6790354 +#define DBSC_DBTR22 0xE6790358 + +#define DBSC_DBBL 0xE6790400 + +#define DBSC_DBRFCNF1 0xE6790414 +#define DBSC_DBRFCNF2 0xE6790418 + +#define DBSC_DBRNK0 0xE6790430 +#define DBSC_DBRNK1 0xE6790434 +#define DBSC_DBRNK2 0xE6790438 +#define DBSC_DBRNK3 0xE679043C +#define DBSC_DBRNK4 0xE6790440 +#define DBSC_DBRNK5 0xE6790444 +#define DBSC_DBRNK6 0xE6790448 + +#define DBSC_DBADJ0 0xE6790500 +#define DBSC_DBADJ2 0xE6790508 + +#define DBSC_DBDFIPMSTRCNF 0xE6790520 + +#define DBSC_DBPDLK_0 0xE6790620 +#define DBSC_DBPDLK_1 0xE6790660 +#define DBSC_DBPDLK_2 0xE67906a0 +#define DBSC_DBPDLK_3 0xE67906e0 + +#define DBSC_INITCOMP_0 0xE6790600 +#define DBSC_INITCOMP_1 0xE6790640 +#define DBSC_INITCOMP_2 0xE6790680 +#define DBSC_INITCOMP_3 0xE67906C0 + +#define DBSC_DBDFICNT_0 0xE6790604 +#define DBSC_DBDFICNT_1 0xE6790644 +#define DBSC_DBDFICNT_2 0xE6790684 +#define DBSC_DBDFICNT_3 0xE67906C4 + +#define DBSC_DBPDCNT0_0 0xE6790610 +#define DBSC_DBPDCNT0_1 0xE6790650 +#define DBSC_DBPDCNT0_2 0xE6790690 +#define DBSC_DBPDCNT0_3 0xE67906D0 + +#define DBSC_DBPDCNT_0 0xE679061C +#define DBSC_DBPDCNT_1 0xE679065C +#define DBSC_DBPDCNT_2 0xE679069C +#define DBSC_DBPDCNT_3 0xE67906DC + +#define DBSC_DBPDRGA_0 0xE6790624 // +#define DBSC_DBPDRGD_0 0xE6790628 // +#define DBSC_DBPDRGA_1 0xE6790664 // +#define DBSC_DBPDRGD_1 0xE6790668 // +#define DBSC_DBPDRGA_2 0xE67906A4 // +#define DBSC_DBPDRGD_2 0xE67906A8 // +#define DBSC_DBPDRGA_3 0xE67906E4 // +#define DBSC_DBPDRGD_3 0xE67906E8 // + +#define DBSC_DBBUS0CNF0 0xE6790800 +#define DBSC_DBBUS0CNF1 0xE6790804 + +#define DBSC_DBCAM0CNF0 0xE6790900 +#define DBSC_DBCAM0CNF1 0xE6790904 +#define DBSC_DBCAM0CNF2 0xE6790908 +#define DBSC_DBCAM0CNF3 0xE679090C +#define DBSC_DBBCAMDIS 0xE67909FC +#define DBSC_DBSCHCNT0 0xE6791000 +#define DBSC_DBSCHCNT1 0xE6791004 +#define DBSC_DBSCHSZ0 0xE6791010 +#define DBSC_DBSCHRW0 0xE6791020 +#define DBSC_DBSCHRW1 0xE6791024 + +#define DBSC_DBSCHQOS_0_0 0xE6791030 +#define DBSC_DBSCHQOS_0_1 0xE6791034 +#define DBSC_DBSCHQOS_0_2 0xE6791038 +#define DBSC_DBSCHQOS_0_3 0xE679103C +#define DBSC_DBSCHQOS_4_0 0xE6791070 +#define DBSC_DBSCHQOS_4_1 0xE6791074 +#define DBSC_DBSCHQOS_4_2 0xE6791078 +#define DBSC_DBSCHQOS_4_3 0xE679107C +#define DBSC_DBSCHQOS_9_0 0xE67910C0 +#define DBSC_DBSCHQOS_9_1 0xE67910C4 +#define DBSC_DBSCHQOS_9_2 0xE67910C8 +#define DBSC_DBSCHQOS_9_3 0xE67910CC +#define DBSC_DBSCHQOS_13_0 0xE6791100 +#define DBSC_DBSCHQOS_13_1 0xE6791104 +#define DBSC_DBSCHQOS_13_2 0xE6791108 +#define DBSC_DBSCHQOS_13_3 0xE679110C +#define DBSC_DBSCHQOS_14_0 0xE6791110 +#define DBSC_DBSCHQOS_14_1 0xE6791114 +#define DBSC_DBSCHQOS_14_2 0xE6791118 +#define DBSC_DBSCHQOS_14_3 0xE679111C +#define DBSC_DBSCHQOS_15_0 0xE6791120 +#define DBSC_DBSCHQOS_15_1 0xE6791124 +#define DBSC_DBSCHQOS_15_2 0xE6791128 +#define DBSC_DBSCHQOS_15_3 0xE679112C + +#define DBSC_DBSCTR0 0xE6791700 +#define DBSC_DBSCTR1 0xE6791708 +#define DBSC_DBSCHRW2 0xE679170C + +#define DBSC_SCFCTST0 0xE6791700 //Schedule timing setting register 0 +#define DBSC_SCFCTST1 0xE6791708 //Schedule timing setting register 1 +#define DBSC_SCFCTST2 0xE679170C //Schedule timing setting register 2 + +#define TSREG1 0xE60603E8 // Fuse Monitor Register 1 + +#define DBSC_PLL_LOCK_0 0xE6794054 +#define DBSC_PLL_LOCK_1 0xE6794154 +#define DBSC_PLL_LOCK_2 0xE6794254 +#define DBSC_PLL_LOCK_3 0xE6794354 + +#define DBSC_FREQ_CHG_ACK_0 0xE6790618 +#define DBSC_FREQ_CHG_ACK_1 0xE6790658 +#define DBSC_FREQ_CHG_ACK_2 0xE6790698 +#define DBSC_FREQ_CHG_ACK_3 0xE67906D8 + +#define DBSC_DFI_FREQ_0 0xE6790614 +#define DBSC_DFI_FREQ_1 0xE6790654 +#define DBSC_DFI_FREQ_2 0xE6790694 +#define DBSC_DFI_FREQ_3 0xE67906D4 + + + +//////////////////////////////////////////////////////////// +// 2800: RL=28,WL=14,nWR=30,nRTP=12 +#define DDR2800_PI_MR1 0xd4 //DeviceFeature1(Post=1.5tck nWR=30 RDpre=static WRPre=2tCK BL=16 // 1 101 0100 +#define DDR2800_PI_MR2 0x2d //DeviceFeature2(0,0SetA,101=WL14,101=RL28) // 0 0 101 101 +#define DDR2800_PI_TFC 0x00c8 // xxxx +#define DDR2800_PI_TRTP 0x0B +#define DDR2800_PI_TCCD 0x08 +#define DDR2800_PI_TWR 0x1A +//#define DDR2800_PI_TWTR 0x25 +#define DDR2800_PI_TWTR 0x0E +#define DDR2800_PI_TRCD 0x1A +#define DDR2800_PI_TRP 0x1E +#define DDR2800_PI_TRAS_MIN 0x3B +#define DDR2800_PI_TRAS_MAX 0x0db60 // xxxx +#define DDR2800_PI_TMRW 0x08 // xxxx +#define DDR2800_PI_TMRD 0x0c // xxxx +#define DDR2800_PI_TCCDMW 0x20 +#define DDR2800_PI_TDQSCK_MAX 0x03 +#define DDR2800_PI_RDLAT_ADJ 0x10 //??? +#define DDR2800_PI_CASLAT_LIN 0x50 +#define DDR2800_PI_WRLAT 0x0e +#define DDR2800_PI_WRLAT_ADJ 0x0c + + +/////////////////////////////////////////////////////////// +// 2400: RL=24,WL=12,nWR=24,nRTP=10 +#define DDR2400_PI_MR1 0xc4 //DeviceFeature1(Post=1.5tck nWR=24 RDpre=static WRPre=2tCK BL=16 // 1 100 0100 +#define DDR2400_PI_MR2 0x24 //DeviceFeature2(0,0SetA,100=WL12,100=RL24) // 0 0 100 100 +#define DDR2400_PI_TFC 0x00c8 // xxxx +#define DDR2400_PI_TRTP 0x09 +#define DDR2400_PI_TCCD 0x08 +#define DDR2400_PI_TWR 0x16 +#define DDR2400_PI_TWTR 0x0c +#define DDR2400_PI_TRCD 0x16 +#define DDR2400_PI_TRP 0x1a +#define DDR2400_PI_TRAS_MIN 0x33 +#define DDR2400_PI_TRAS_MAX 0x0db60 // xxxx +#define DDR2400_PI_TMRW 0x08 // xxxx +#define DDR2400_PI_TMRD 0x0c // xxxx +#define DDR2400_PI_TCCDMW 0x20 +#define DDR2400_PI_TDQSCK_MAX 0x03 +#define DDR2400_PI_RDLAT_ADJ 0x0e +#define DDR2400_PI_CASLAT_LIN 0x50 //PI_CASLAT_LIN_F2:RW:0:7:=0x1c +#define DDR2400_PI_WRLAT 0x0c //PI_WRLAT_F2:RW:16:5:=0x08 +#define DDR2400_PI_WRLAT_ADJ 0x0a +///////////////// +#define DDR1600_PI_MR1 0xa4 //MRW DeviceFeature1(Post=1.5tck nWR=16 RDpre=static WRPre=2tCK BL=16//OK // 1 010 0100 +#define DDR1600_PI_MR2 0x52 //MRW DeviceFeature2(0,1SetB,010=WL12,010=RL14(nRTP14))// // 01 010 010 +#define DDR1600_PI_TFC 0x00c8 +#define DDR1600_PI_TRTP 0x08 +#define DDR1600_PI_TCCD 0x08 +#define DDR1600_PI_TWR 0x11 +#define DDR1600_PI_TWTR 0x0a +#define DDR1600_PI_TRCD 0x0f +#define DDR1600_PI_TRP 0x11 +#define DDR1600_PI_TRAS_MIN 0x22 +#define DDR1600_PI_TRAS_MAX 0x0db60 +#define DDR1600_PI_TMRW 0x08 //10 +#define DDR1600_PI_TMRD 0x0c +#define DDR1600_PI_TCCDMW 0x20 +#define DDR1600_PI_TDQSCK_MAX 0x3 +#define DDR1600_PI_RDLAT_ADJ 0x08 //PI_RDLAT_ADJ_F2:RW:16:8:=0x07 //try 07+2 1600 +#define DDR1600_PI_CASLAT_LIN 0x50 //PI_CASLAT_LIN_F2:RW:0:7:=0x1c +#define DDR1600_PI_WRLAT 0x0c //PI_WRLAT_F2:RW:16:5:=0x08 +#define DDR1600_PI_WRLAT_ADJ 0x0a + +////////////////////////////////////////////////////////////////// + +void InitDram_h3_es10(void); + +static void pvt_dbsc_regset(uint32_t freq); +static void pvt_manual_update(uint32_t flag); +static void set_cacs_delay(); +static void _rx_cal_code_set(uint32_t ch, uint32_t slice, uint8_t _cal_code_up[][4][16],uint8_t _cal_code_dn[][4][16]); +static void rx_cal_manual1(uint32_t chmask); +static void mode_register_set(uint32_t freq,uintptr_t phychno,uint32_t mr13_val); +static void _set_reg(uint32_t ch_mask, uint32_t regadd, uint32_t pos, uint32_t width, uint32_t val); +static void pvt_lvl_enable_set(uint32_t go); +static void pvt_freq_change_ack(uint32_t freq, uintptr_t phychno, uint32_t freq_flag); +static uint32_t pvt_pi_training_go_all_o(uint32_t freq); + +inline void PLL3_FREQ(uint32_t freq,uint32_t freq_flag); +static uint32_t pvt_pi_training_go_all(uint32_t freq); +static uint32_t pvt_pi_training(uint32_t freq); +static void WaitDBCMD(void); + +static void REG_DDRPHY_WRITE ( uintptr_t phyno, uint32_t regadd, uint32_t regdata); +static void change_lpddr4_en(uintptr_t phychno, uint32_t mode); +static void copy_csdelay(uint32_t phychno, uint32_t s_byte); +static void adjust_rddqsgatedelay(uintptr_t phychno); +static void copy_dqdelay(uintptr_t phychno, uint32_t s_byte, uint32_t d_byte); +static uint32_t pvt_pi_training_go_all_soft(uint32_t freq); + +inline void dsb_sev(void); + +static uint32_t REG_DDRPHY_READ ( uintptr_t phyno, uint32_t regadd); +static uint32_t InitDDR_0917(uint32_t freq); +//void freq2800_reg_set(); +//void freq2400_reg_set(); +static void freq1600_reg_set(); + + +uint8_t cal_code_up[4][4][16];//[11-15]are dummy +uint8_t cal_code_dn[4][4][16];//[11-15]are dummy +uint8_t fst1[4][4][16];//[11-15]are dummy +uint8_t lst0[4][4][16];//[11-15]are dummy +uint32_t val[4][4][16][4]; + +void SoftDelay(uint32_t loop) +{ + volatile uint32_t i; + for(i=0;i> 17; + + if (md == 0x0) { + NOTICE("BL2: DDR3200(%s)\n", RCAR_DDR_VERSION); + } else if (md == 0x1) { + freq = DDR2800_CLK; //MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) + NOTICE("BL2: DDR2800(%s)\n", RCAR_DDR_VERSION); + } else if (md == 0x4) { + freq = DDR2400_CLK; //MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) + NOTICE("BL2: DDR2400(%s)\n", RCAR_DDR_VERSION); + } else { + freq = DDR1600_CLK; //MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) + NOTICE("BL2: DDR1600(%s)\n", RCAR_DDR_VERSION); + } + InitDDR_0917(freq); +} + + +static void pvt_dbsc_regset(uint32_t freq) +{ + + *((volatile uint32_t*)DBSC_DBPDCNT0_0) = 0x00; + *((volatile uint32_t*)DBSC_DBPDCNT0_1) = 0x00; + *((volatile uint32_t*)DBSC_DBPDCNT0_2) = 0x00; + *((volatile uint32_t*)DBSC_DBPDCNT0_3) = 0x00; + + //LPDDR4-1600(CL14NoDBI),4GByte(8GBit x 4) + + *((volatile uint32_t*)DBSC_DBSTATE0) = 0x00000010; + *((volatile uint32_t*)DBSC_DBKIND) = 0x0000000a; //ddcg=a(lpddr4) + + *((volatile uint32_t*)DBSC_DBBL) = 0x00000002; //BL=16(lpddr4) + +//DRAM Size Registers +//Please set for 4ranks + *((volatile uint32_t*)DBSC_DBMEMCONF_0_0) = 0x0f030a02; //memconf00(ch0/rank0) 4GB + *((volatile uint32_t*)DBSC_DBMEMCONF_0_1) = 0x0f030a02; //memconf01(ch0/rank1) 4GB + *((volatile uint32_t*)DBSC_DBMEMCONF_1_0) = 0x0f030a02; //memconf10(ch1/rank0) 4GB + *((volatile uint32_t*)DBSC_DBMEMCONF_1_1) = 0x0f030a02; //memconf11(ch1/rank1) 4GB + *((volatile uint32_t*)DBSC_DBMEMCONF_2_0) = 0x0f030a02; //memconf20(ch2/rank0) 4GB + *((volatile uint32_t*)DBSC_DBMEMCONF_2_1) = 0x0f030a02; //memconf21(ch2/rank1) 4GB + *((volatile uint32_t*)DBSC_DBMEMCONF_3_0) = 0x0f030a02; //memconf30(ch3/rank0) 4GB + *((volatile uint32_t*)DBSC_DBMEMCONF_3_1) = 0x0f030a02; //memconf31(ch3/rank1) 4GB + + *((volatile uint32_t*)DBSC_DBMEMCONF_0_2) = 0x0f030a02; //memconf01(ch0/rank2) 4GB + *((volatile uint32_t*)DBSC_DBMEMCONF_0_3) = 0x0f030a02; //memconf01(ch0/rank3) 4GB + *((volatile uint32_t*)DBSC_DBMEMCONF_1_2) = 0x0f030a02; //memconf01(ch1/rank2) 4GB + *((volatile uint32_t*)DBSC_DBMEMCONF_1_3) = 0x0f030a02; //memconf01(ch1/rank3) 4GB + *((volatile uint32_t*)DBSC_DBMEMCONF_2_2) = 0x0f030a02; //memconf01(ch2/rank2) 4GB + *((volatile uint32_t*)DBSC_DBMEMCONF_2_3) = 0x0f030a02; //memconf01(ch2/rank3) 4GB + *((volatile uint32_t*)DBSC_DBMEMCONF_3_2) = 0x0f030a02; //memconf01(ch3/rank2) 4GB + *((volatile uint32_t*)DBSC_DBMEMCONF_3_3) = 0x0f030a02; //memconf01(ch3/rank3) 4GB + + *((volatile uint32_t*)DBSC_DBPHYCONF0) = 0x00000001; //phyconf0 + + if(freq>0x53) + { + // DDR3200 + *((volatile uint32_t*)DBSC_DBTR0) = 0x00000020; //dbtr0 cl=32 + *((volatile uint32_t*)DBSC_DBTR1) = 0x0000000e; //dbtr1 cwl=14 + *((volatile uint32_t*)DBSC_DBTR3) = 0x0000001d; //dbtr3 trcd=29 + *((volatile uint32_t*)DBSC_DBTR4) = 0x0022001d; //dbtr4 trpa=34 trp=29 + *((volatile uint32_t*)DBSC_DBTR5) = 0x00000060; //dbtr5 trc=102 + *((volatile uint32_t*)DBSC_DBTR6) = 0x00000044; //dbtr6 tras=68 + *((volatile uint32_t*)DBSC_DBTR7) = 0x00100010; //dbtr7 trrd_s=16 trrd=16 + *((volatile uint32_t*)DBSC_DBTR8) = 0x00000040; //dbtr8 tfaw=64 + *((volatile uint32_t*)DBSC_DBTR9) = 0x0000000c; //dbtr9 trdpr=12 + *((volatile uint32_t*)DBSC_DBTR10) = 0x0000001d; //dbtr10 twr=30 +//NG: *((volatile uint32_t*)DBSC_DBTR11) = 0x00000021; //dbtr11 trdwr=33 + *((volatile uint32_t*)DBSC_DBTR11) = 0x00000025; //dbtr11 trdwr=37 + *((volatile uint32_t*)DBSC_DBTR12) = 0x00270027; //dbtr12 twrrd_s=39 twrrd=39 + *((volatile uint32_t*)DBSC_DBTR13) = 0x00900120; //dbtr13 trfcpb=96 trfc=208 + *((volatile uint32_t*)DBSC_DBTR14) = 0x000c000c; //dbtr14 tckehdll=12 tckeh=12 + *((volatile uint32_t*)DBSC_DBTR15) = 0x001e000c; //dbtr15 tckesr=30 tckel=12 currently tckesr is TBD. + + *((volatile uint32_t*)DBSC_DBTR16) = 0x10400c0e; //dbtr16 latency? CL=32 & PHY_RDDATA_EN_DLY_X = 0e (32+2-14=20), CWL=14 & TDFI_PHY_WRDATA=2 + *((volatile uint32_t*)DBSC_DBTR17) = 0x080a0004; //dbtr17 tmodrd=8 tmod=10 trdmr=4 + *((volatile uint32_t*)DBSC_DBTR18) = 0x00000000; //dbtr18 No odt for DQ exists in LPDDR4. + *((volatile uint32_t*)DBSC_DBTR19) = 0x00000000; //dbtr19 tzqcl=0 tzqcs=0 because LPDDR4 doesn't support ZQC[SL]. + *((volatile uint32_t*)DBSC_DBTR20) = 0x012c012c; //dbtr20 txsdll=trfc+12=220 txs=220 +// *((volatile uint32_t*)DBSC_DBTR21) = 0x00080008; //dbtr21 tccd_s= 8 tccd= 8 +// *((volatile uint32_t*)DBSC_DBTR21) = 0x000C000C; //dbtr21 tccd_s=12 tccd=12 u-boot ng // for lowfreq +// *((volatile uint32_t*)DBSC_DBTR21) = 0x000d000d; //dbtr21 tccd_s=13 tccd=13 u-boot ng // for lowfreq +// *((volatile uint32_t*)DBSC_DBTR21) = 0x000e000e; //dbtr21 tccd_s=14 tccd=14 u-boot ok // for lowfreq + *((volatile uint32_t*)DBSC_DBTR21) = 0x00100010; //dbtr21 tccd_s=16 tccd=16 u-boot ok // for lowfreq + *((volatile uint32_t*)DBSC_DBTR22) = 0x06400030; //dbtr22 tzqcal=1600 tzqlat=48 + + } + else if(freq>0x47) + { + // DDR2800 + *((volatile uint32_t*)DBSC_DBTR0) = 0x0000001c; //dbtr0 cl=28 + *((volatile uint32_t*)DBSC_DBTR1) = 0x0000000e; //dbtr1 cwl=14 + *((volatile uint32_t*)DBSC_DBTR3) = 0x0000001a; //dbtr3 trcd=26 + *((volatile uint32_t*)DBSC_DBTR4) = 0x001e001a; //dbtr4 trpa=30 trp=26 +// *((volatile uint32_t*)DBSC_DBTR5) = 0x00000059; //dbtr5 trc=89 + *((volatile uint32_t*)DBSC_DBTR5) = 0x00000055; //dbtr5 trc=85 + *((volatile uint32_t*)DBSC_DBTR6) = 0x0000003b; //dbtr6 tras=59 +// *((volatile uint32_t*)DBSC_DBTR7) = 0x000e000e; //dbtr7 trrd_s=14 trrd=14 + *((volatile uint32_t*)DBSC_DBTR7) = 0x000f000f; //dbtr7 trrd_s=15 trrd=15 +// *((volatile uint32_t*)DBSC_DBTR8) = 0x00000038; //dbtr8 tfaw=56 + *((volatile uint32_t*)DBSC_DBTR8) = 0x00000039; //dbtr8 tfaw=57 +// *((volatile uint32_t*)DBSC_DBTR9) = 0x0000000b; //dbtr9 trdpr=11 + *((volatile uint32_t*)DBSC_DBTR9) = 0x0000000c; //dbtr9 trdpr=12 +// *((volatile uint32_t*)DBSC_DBTR10) = 0x0000001b; //dbtr10 twr=27 + *((volatile uint32_t*)DBSC_DBTR10) = 0x0000001E; //dbtr10 twr=30, nWR is 26, but its value is not defined in MR1.nWR +// *((volatile uint32_t*)DBSC_DBTR11) = 0x0000001e; //dbtr11 trdwr=30 +//NG: *((volatile uint32_t*)DBSC_DBTR11) = 0x00000020; //dbtr11 trdwr=32 + *((volatile uint32_t*)DBSC_DBTR11) = 0x00000022; //dbtr11 trdwr=33 +// *((volatile uint32_t*)DBSC_DBTR12) = 0x00250025; //dbtr12 twrrd_s=37 twrrd=37 + *((volatile uint32_t*)DBSC_DBTR12) = 0x00260026; //dbtr12 twrrd_s=38 twrrd=38 + *((volatile uint32_t*)DBSC_DBTR13) = 0x007f00fd; //dbtr13 trfcpb=127 trfc=253 + *((volatile uint32_t*)DBSC_DBTR14) = 0x000c000c; //dbtr14 tckehdll=12 tckeh=12 + *((volatile uint32_t*)DBSC_DBTR15) = 0x0016000b; //dbtr15 tckesr=22 tckel=11 + + *((volatile uint32_t*)DBSC_DBTR16) = 0x101f0c0e; //dbtr16 latency? CL=32 & PHY_RDDATA_EN_DLY_X = 0e (32+2-14=20), CWL=14 & TDFI_PHY_WRDATA=2 + *((volatile uint32_t*)DBSC_DBTR17) = 0x0c0f0020; //dbtr17 tmodrd=12 tmod=15 trdmr=32 + *((volatile uint32_t*)DBSC_DBTR18) = 0x00000000; //dbtr18 No odt for DQ exists in LPDDR4. + *((volatile uint32_t*)DBSC_DBTR19) = 0x00000000; //dbtr19 tzqcl=0 tzqcs=0 because LPDDR4 doesn't support ZQC[SL]. + *((volatile uint32_t*)DBSC_DBTR20) = 0x01070107; //dbtr20 txsdll=txs=tRFCab+7.5ns=263 +// *((volatile uint32_t*)DBSC_DBTR21) = 0x00080008; //dbtr21 tccd_s= 8 tccd= 8 +// *((volatile uint32_t*)DBSC_DBTR21) = 0x000b000b; //dbtr21 tccd_s=11 tccd=11 But PHY may restrict tccd+1/+2, so set it big enough. +// *((volatile uint32_t*)DBSC_DBTR21) = 0x000C000C; //dbtr21 tccd_s=12 tccd=12 u-boot ng // for lowfreq +// *((volatile uint32_t*)DBSC_DBTR21) = 0x000d000d; //dbtr21 tccd_s=16 tccd=13 u-boot ok // for lowfreq + *((volatile uint32_t*)DBSC_DBTR21) = 0x000e000e; //dbtr21 tccd_s=16 tccd=14 u-boot ok // for lowfreq +// *((volatile uint32_t*)DBSC_DBTR21) = 0x00100010; //dbtr21 tccd_s=16 tccd=16 u-boot ok // for lowfreq + *((volatile uint32_t*)DBSC_DBTR22) = 0x06400030; //dbtr22 tzqcal=1600 tzqlat=48 + + } + else if(freq>0x2f) + { + // DDR2400 + *((volatile uint32_t*)DBSC_DBTR0) = 0x00000018; //dbtr0 cl=24 + *((volatile uint32_t*)DBSC_DBTR1) = 0x0000000c; //dbtr1 cwl=12 + *((volatile uint32_t*)DBSC_DBTR3) = 0x00000016; //dbtr3 trcd=22 + *((volatile uint32_t*)DBSC_DBTR4) = 0x001a0016; //dbtr4 trpa=26 trp=22 + *((volatile uint32_t*)DBSC_DBTR5) = 0x00000049; //dbtr5 trc=73 + *((volatile uint32_t*)DBSC_DBTR6) = 0x00000033; //dbtr6 tras=51 + *((volatile uint32_t*)DBSC_DBTR7) = 0x000d000d; //dbtr7 trrd_s=13 trrd=13 + *((volatile uint32_t*)DBSC_DBTR8) = 0x00000031; //dbtr8 tfaw=49 + *((volatile uint32_t*)DBSC_DBTR9) = 0x0000000a; //dbtr9 trdpr=10 + *((volatile uint32_t*)DBSC_DBTR10) = 0x00000016; //dbtr10 twr=22 + *((volatile uint32_t*)DBSC_DBTR11) = 0x0000001c; //dbtr11 trdwr=28 PHY may have restriction of this value. + *((volatile uint32_t*)DBSC_DBTR12) = 0x00220022; //dbtr12 twrrd_s=34 twrrd=34 PHY may restriction of this value. + *((volatile uint32_t*)DBSC_DBTR13) = 0x006d00d9; //dbtr13 trfcpb=109 trfc=217 + *((volatile uint32_t*)DBSC_DBTR14) = 0x000a000a; //dbtr14 tckehdll=10 tckeh=10 + *((volatile uint32_t*)DBSC_DBTR15) = 0x0013000c; //dbtr15 tckesr=19 tckel=12 + + *((volatile uint32_t*)DBSC_DBTR16) = 0x08400a0c; //dbtr16 latency? CL=24 & PHY_RDDATA_EN_DLY_X = 0e (???), CWL=12 & TDFI_PHY_WRDATA=2 + *((volatile uint32_t*)DBSC_DBTR17) = 0x080a0004; //dbtr17 tmodrd=8 tmod=10 trdmr=4 + *((volatile uint32_t*)DBSC_DBTR18) = 0x00000000; //dbtr18 No odt for DQ exists in LPDDR4. + *((volatile uint32_t*)DBSC_DBTR19) = 0x00000000; //dbtr19 tzqcl=0 tzqcs=0 because LPDDR4 doesn't support ZQC[SL]. + *((volatile uint32_t*)DBSC_DBTR20) = 0x00e200e2; //dbtr20 txsdll=txs=tRFCab+7.5ns=226 +// *((volatile uint32_t*)DBSC_DBTR21) = 0x00080008; //dbtr21 tccd_s=8 tccd=8 +// *((volatile uint32_t*)DBSC_DBTR21) = 0x000b000b; //dbtr21 tccd_s=11 tccd=11 But PHY may restrict tccd+1/+2, so set it big enough. + *((volatile uint32_t*)DBSC_DBTR21) = 0x000C000C; //dbtr21 tccd_s=12 tccd=12 u-boot ok // for lowfreq +// *((volatile uint32_t*)DBSC_DBTR21) = 0x00100010; //dbtr21 tccd_s=16 tccd=16 u-boot ok // for lowfreq + *((volatile uint32_t*)DBSC_DBTR22) = 0x04b10025; //dbtr22 tzqcal=1201 tzqlat=37 + + } + else + { + // DDR1600 + *((volatile uint32_t*)DBSC_DBTR0) = 0x0000000e; //dbtr0 cl=14 + *((volatile uint32_t*)DBSC_DBTR1) = 0x0000000c; //dbtr1 cwl=c + *((volatile uint32_t*)DBSC_DBTR3) = 0x0000000f; //dbtr3 trcd=15 + *((volatile uint32_t*)DBSC_DBTR4) = 0x0011000f; //dbtr4 trpa=17 trp=15 + *((volatile uint32_t*)DBSC_DBTR5) = 0x00000030; //dbtr5 trc=48 + *((volatile uint32_t*)DBSC_DBTR6) = 0x00000022; //dbtr6 tras=34 + *((volatile uint32_t*)DBSC_DBTR7) = 0x00080008; //dbtr7 trrd_s=8 trrd=8 + *((volatile uint32_t*)DBSC_DBTR8) = 0x00000020; //dbtr8 tfaw=32 + *((volatile uint32_t*)DBSC_DBTR9) = 0x00000006; //dbtr9 trdpr=6 + *((volatile uint32_t*)DBSC_DBTR10) = 0x0000000f; //dbtr10 twr=15 + *((volatile uint32_t*)DBSC_DBTR11) = 0x00000011; //dbtr11 trdwr=22 + *((volatile uint32_t*)DBSC_DBTR12) = 0x001D001D; //dbtr12 twrrd_s=20 + *((volatile uint32_t*)DBSC_DBTR13) = 0x00480090; //dbtr13 trfcpb=72 trfcab=144 + *((volatile uint32_t*)DBSC_DBTR14) = 0x00060006; //dbtr14 tckehdll=6 + *((volatile uint32_t*)DBSC_DBTR15) = 0x000c0006; //dbtr15 tckesr=12 + + *((volatile uint32_t*)DBSC_DBTR16) = 0x06200a0C; //dbtr16 latency? + *((volatile uint32_t*)DBSC_DBTR17) = 0x080a0004; //dbtr17 tmodrd=8 tmod=10 trdmr=4 + *((volatile uint32_t*)DBSC_DBTR18) = 0x00000000; //dbtr18 No odt for DQ exists in LPDDR4. + *((volatile uint32_t*)DBSC_DBTR19) = 0x00000000; //dbtr19 tzqcl=0 tzqcs=0 because LPDDR4 doesn't support ZQC[SL]. + *((volatile uint32_t*)DBSC_DBTR20) = 0x00b00096; //dbtr20 txsdll=150 +// *((volatile uint32_t*)DBSC_DBTR21) = 0x00080008; //dbtr21 tccd_s=8 tccd=8 + *((volatile uint32_t*)DBSC_DBTR21) = 0x000b000b; //dbtr21 tccd_s=11 tccd=11 u-boot ok But PHY may restrict tccd+1/+2, so set it big enough. +// *((volatile uint32_t*)DBSC_DBTR21) = 0x000C000C; //dbtr21 tccd_s=12 tccd=12 u-boot ok // for lowfreq +// *((volatile uint32_t*)DBSC_DBTR21) = 0x00100010; //dbtr21 tccd_s=16 tccd=16 u-boot ok // for lowfreq + *((volatile uint32_t*)DBSC_DBTR22) = 0x03200018; //dbtr22 tzqcal=800 tzqlat=24 + } + + *((volatile uint32_t*)DBSC_DBRNK0) = 0x00000000; //dbrnk0 No odt for DQ exists in LPDDR4(N.Honda). + *((volatile uint32_t*)DBSC_DBRNK1) = 0x00000000; //dbrnk1 Don't need to set it cause we use all-rank refresh. + *((volatile uint32_t*)DBSC_DBRNK2) = 0x00008888; //dbrnk2 rkrr=8 + *((volatile uint32_t*)DBSC_DBRNK3) = 0x00008888; //dbrnk3 rkrw=8 + *((volatile uint32_t*)DBSC_DBRNK4) = 0x00008888; //dbrnk4 rkwr=8 + *((volatile uint32_t*)DBSC_DBRNK5) = 0x00008888; //dbrnk5 rkww=8 + *((volatile uint32_t*)DBSC_DBRNK6) = 0x00000000; //dbrnk6 Use ALL Rank + *((volatile uint32_t*)DBSC_DBADJ0) = 0x00000000; //dbadj0 No Optional setting + *((volatile uint32_t*)DBSC_DBADJ2) = 0x00000000; //dbadj2 No Optional setting + +//BUFCAM settings +// *((volatile uint32_t*)DBSC_DBCAM0CNF0) = 0x00000000; //dbcam0cnf0 inoen=0, actually it is not used. + *((volatile uint32_t*)DBSC_DBCAM0CNF1) = 0x00044218; //dbcam0cnf1 + *((volatile uint32_t*)DBSC_DBCAM0CNF2) = 0x000000F4; //dbcam0cnf2 +// *((volatile uint32_t*)DBSC_DBCAM0CNF3) = 0x00000003; // + *((volatile uint32_t*)DBSC_DBBCAMDIS) = 0x00000002; //Subcam Disable + *((volatile uint32_t*)DBSC_DBSCHCNT0) = 0x080F003F; //dbschcnt0 + *((volatile uint32_t*)DBSC_DBSCHCNT1) = 0x00001010; //dbschcnt1 + *((volatile uint32_t*)DBSC_DBSCHSZ0) = 0x00000001; //dbschsz0 + *((volatile uint32_t*)DBSC_DBSCHRW0) = 0xF7311111; //dbschrw0 + *((volatile uint32_t*)DBSC_DBSCHRW1) = 0x00000037; //dbschrw1 + +//QoS Settings + *((volatile uint32_t*)DBSC_DBSCHQOS_0_0) = 0x0000F000; //dbschqos00 + *((volatile uint32_t*)DBSC_DBSCHQOS_0_1) = 0x0000E000; //dbschqos01 + *((volatile uint32_t*)DBSC_DBSCHQOS_0_2) = 0x00007000; //dbschqos02 + *((volatile uint32_t*)DBSC_DBSCHQOS_0_3) = 0x00000000; //dbschqos03 + *((volatile uint32_t*)DBSC_DBSCHQOS_4_0) = 0x0000F000; //dbschqos40 + *((volatile uint32_t*)DBSC_DBSCHQOS_4_1) = 0x0000EFFF; //dbschqos41 + *((volatile uint32_t*)DBSC_DBSCHQOS_4_2) = 0x0000B000; //dbschqos42 + *((volatile uint32_t*)DBSC_DBSCHQOS_4_3) = 0x00000000; //dbschqos43 + *((volatile uint32_t*)DBSC_DBSCHQOS_9_0) = 0x0000F000; //dbschqos90 + *((volatile uint32_t*)DBSC_DBSCHQOS_9_1) = 0x0000EFFF; //dbschqos91 + *((volatile uint32_t*)DBSC_DBSCHQOS_9_2) = 0x0000D000; //dbschqos92 + *((volatile uint32_t*)DBSC_DBSCHQOS_9_3) = 0x00000000; //dbschqos93 + *((volatile uint32_t*)DBSC_DBSCHQOS_13_0) = 0x0000F000; //dbschqos130 + *((volatile uint32_t*)DBSC_DBSCHQOS_13_1) = 0x0000EFFF; //dbschqos131 + *((volatile uint32_t*)DBSC_DBSCHQOS_13_2) = 0x0000E800; //dbschqos132 + *((volatile uint32_t*)DBSC_DBSCHQOS_13_3) = 0x00007000; //dbschqos133 + *((volatile uint32_t*)DBSC_DBSCHQOS_14_0) = 0x0000F000; //dbschqos140 + *((volatile uint32_t*)DBSC_DBSCHQOS_14_1) = 0x0000EFFF; //dbschqos141 + *((volatile uint32_t*)DBSC_DBSCHQOS_14_2) = 0x0000E800; //dbschqos142 + *((volatile uint32_t*)DBSC_DBSCHQOS_14_3) = 0x00007000; //dbschqos143 + *((volatile uint32_t*)DBSC_DBSCHQOS_15_0) = 0x000007D0; //dbschqos150 + *((volatile uint32_t*)DBSC_DBSCHQOS_15_1) = 0x000007CF; //dbschqos151 + *((volatile uint32_t*)DBSC_DBSCHQOS_15_2) = 0x000005D0; //dbschqos152 + *((volatile uint32_t*)DBSC_DBSCHQOS_15_3) = 0x000003D0; //dbschqos153 + + *((volatile uint32_t*)DBSC_DBSYSCONF1) = 0x00000002; //dbsysconf1 freqratio=2. + +//Under Verification + *((volatile uint32_t*)DBSC_DBCAM0CNF1) = 0x00044218; //wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) <- independent of dram freq + *((volatile uint32_t*)DBSC_DBCAM0CNF2) = 0x00000284; //rg_scexp[15:0] 0,0(fillunit),8(dirtymax),4(dirtymin) <- independent of dram freq + + if(freq>0x53) + { + // DDR3200 + *((volatile uint32_t*)DBSC_DBSCHRW0) = 0xF7311111; //stop_tolerance, independent of dram freq + *((volatile uint32_t*)DBSC_DBSCHRW1) = 0x00000048; //[15: 8]=trfcpb/4; [ 7: 0]=trfcab/4 ; + *((volatile uint32_t*)DBSC_SCFCTST0) = 0x18030d09; //[31:24]=trc/4 ; [23:16]=trda->act/4; [15:8]=twra->act/4; [7:0]=trp/4 + *((volatile uint32_t*)DBSC_SCFCTST1) = 0x090a080c; //[31:24]=trdwr/4 ; [23:16]=twrrd/4 ; [15:8]=trcd/4 ; [7:0]=asyncofs + *((volatile uint32_t*)DBSC_SCFCTST2) = 0x111f1fff; //rd-wr/wr-rd toggle count, independent of dram freq + } + else if(freq>0x47) + { + // DDR2800 + *((volatile uint32_t*)DBSC_DBSCHRW0) = 0xF7311111; //stop_tolerance, independent of dram freq + *((volatile uint32_t*)DBSC_DBSCHRW1) = 0x00018248; //[15: 8]=trfcpb/4; [ 7: 0]=trfcab/4 ; +// *((volatile uint32_t*)DBSC_SCFCTST0) = 0x15030d09; //[31:24]=trc/4 ; [23:16]=trda->act/4; [15:8]=twra->act/4; [7:0]=trp/4 + *((volatile uint32_t*)DBSC_SCFCTST0) = 0x180b1508; //[31:24]=trc/2.5=18 ; [23:16]=trda->act/2.5=11; [15:8]=twra->act/2.5=21; [7:0]=trp/2.5=8 +// *((volatile uint32_t*)DBSC_SCFCTST1) = 0x080a070c; //[31:24]=trdwr/4 ; [23:16]=twrrd/4 ; [15:8]=trcd/4 ; [7:0]=asyncofs + *((volatile uint32_t*)DBSC_SCFCTST1) = 0x0a0b080C; //[31:24]=trdwr/2.5=9 ; [23:16]=twrrd/2.5=16 ; [15:8]=trcd/2.5=8 ; [7:0]=asyncofs + *((volatile uint32_t*)DBSC_SCFCTST2) = 0x000F0FFF; //rd-wr/wr-rd toggle count, independent of dram freq + } + else if(freq>0x2f) + { + // DDR2400 + *((volatile uint32_t*)DBSC_DBSCHRW0) = 0x22421111; //stop_tolerance, independent of dram freq + *((volatile uint32_t*)DBSC_DBSCHRW1) = 0x00180034; //[15: 8]=trfcpb/4; [ 7: 0]=trfcab/4 ; + *((volatile uint32_t*)DBSC_SCFCTST0) = 0x180B1708; //[31:24]=trc/4 ; [23:16]=trda->act/4; [15:8]=twra->act/4; [7:0]=trp/4 + *((volatile uint32_t*)DBSC_SCFCTST1) = 0x0808070C; //[31:24]=trdwr/4 ; [23:16]=twrrd/4 ; [15:8]=trcd/4 ; [7:0]=asyncofs + *((volatile uint32_t*)DBSC_SCFCTST2) = 0x012F1123; //rd-wr/wr-rd toggle count, independent of dram freq + } + else + { + *((volatile uint32_t*)DBSC_DBSCHRW0) = 0xF7311111; //stop_tolerance, independent of dram freq + *((volatile uint32_t*)DBSC_DBSCHRW1) = 0x00000024; //[15: 8]=trfcpb/4; [ 7: 0]=trfcab/4 ; + *((volatile uint32_t*)DBSC_SCFCTST0) = 0x0c020905; //[31:24]=trc/4 ; [23:16]=trda->act/4; [15:8]=twra->act/4; [7:0]=trp/4 + *((volatile uint32_t*)DBSC_SCFCTST1) = 0x0508040C; //[31:24]=trdwr/4 ; [23:16]=twrrd/4 ; [15:8]=trcd/4 ; [7:0]=asyncofs + *((volatile uint32_t*)DBSC_SCFCTST2) = 0x000F0FFF; //rd-wr/wr-rd toggle count, independent of dram freq + } +} + + +static void pvt_manual_update(uint32_t flag) +{ + if(flag&0x1) {REG_DDRPHY_WRITE(0,0x702,REG_DDRPHY_READ(0,0x702) | (1<<16));}; + if(flag&0x2) {REG_DDRPHY_WRITE(1,0x702,REG_DDRPHY_READ(1,0x702) | (1<<16));}; + if(flag&0x4) {REG_DDRPHY_WRITE(2,0x702,REG_DDRPHY_READ(2,0x702) | (1<<16));}; + if(flag&0x8) {REG_DDRPHY_WRITE(3,0x702,REG_DDRPHY_READ(3,0x702) | (1<<16));}; + + if(flag&0x10) {REG_DDRPHY_WRITE(0,0x732,REG_DDRPHY_READ(0,0x732) | (1<<16));}; + if(flag&0x20) {REG_DDRPHY_WRITE(1,0x732,REG_DDRPHY_READ(1,0x732) | (1<<16));}; + if(flag&0x40) {REG_DDRPHY_WRITE(2,0x732,REG_DDRPHY_READ(2,0x732) | (1<<16));}; + if(flag&0x80) {REG_DDRPHY_WRITE(3,0x732,REG_DDRPHY_READ(3,0x732) | (1<<16));}; +} + + +static void set_cacs_delay() +{ + uint32_t i,f,dataL; + + //FREQ_SEL_INDEX=3 (not needed? because MULTICAST_EN=1) ==> NEED!! otherwise, copy will not copy + REG_DDRPHY_WRITE (1,0x00000700,0x0301); + REG_DDRPHY_WRITE (2,0x00000700,0x0301); + REG_DDRPHY_WRITE (3,0x00000700,0x0301); + + for (i=0;i<4;i++) + { + for(f=0;f<2;f++) + { + REG_DDRPHY_WRITE(i,0x700,dataL=((REG_DDRPHY_READ(i,0x700) & 0xfffffcfe) | (f<<8)) ); + + REG_DDRPHY_WRITE(i,DDR_CA_DELAY[0][0],dataL=((DDR_CA_DELAY[0][1] & 0x000000ff) | (DDR_CAD<<8)) ); + REG_DDRPHY_WRITE(i,DDR_CA_DELAY[1][0],dataL=((DDR_CA_DELAY[1][1] & 0x00000000) | (DDR_CAD<<16) | (DDR_CAD<<0)) ); + REG_DDRPHY_WRITE(i,DDR_CA_DELAY[2][0],dataL=((DDR_CA_DELAY[2][1] & 0x00000000) | (DDR_CAD<<16) | (DDR_CAD<<0)) ); + REG_DDRPHY_WRITE(i,DDR_CA_DELAY[3][0],dataL=((DDR_CA_DELAY[3][1] & 0x000f0000) | (DDR_CAD<<0)) ); + + REG_DDRPHY_WRITE(i,DDR_CA_DELAY[0][0]+0x80,dataL=((DDR_CA_DELAY[0][1] & 0x000000ff) | (DDR_CAD<<8)) ); + REG_DDRPHY_WRITE(i,DDR_CA_DELAY[1][0]+0x80,dataL=((DDR_CA_DELAY[1][1] & 0x00000000) | (DDR_CAD<<16) | (DDR_CAD<<0)) ); + REG_DDRPHY_WRITE(i,DDR_CA_DELAY[2][0]+0x80,dataL=((DDR_CA_DELAY[2][1] & 0x00000000) | (DDR_CAD<<16) | (DDR_CAD<<0)) ); + REG_DDRPHY_WRITE(i,DDR_CA_DELAY[3][0]+0x80,dataL=((DDR_CA_DELAY[3][1] & 0x000f0000) | (DDR_CAD<<0)) ); + + REG_DDRPHY_WRITE(i,DDR_CA_DELAY[4][0],dataL=((DDR_CA_DELAY[4][1] & 0x000000ff) | (DDR_GRP_A<<8)) ); + REG_DDRPHY_WRITE(i,DDR_CA_DELAY[5][0],dataL=((DDR_CA_DELAY[5][1] & 0x00000000) | (DDR_GRP_B<<16) | (DDR_GRP_A<<0)) ); + REG_DDRPHY_WRITE(i,DDR_CA_DELAY[6][0],dataL=((DDR_CA_DELAY[6][1] & 0x00000000) | (DDR_GRP_B<<0)) ); + } + REG_DDRPHY_WRITE(i,0x700,dataL=((REG_DDRPHY_READ(i,0x700) & 0xfffffffe) | 1) ); + } + + for (i=0;i<4;i++) + { + REG_DDRPHY_WRITE(i,0x702,dataL=((REG_DDRPHY_READ(i,0x702) & 0xfeffffff) | (DDR_LP4_BOOT_DISABLE<<24) ) ); +// 0x00000601, 0x00000000, // PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0:RW:16:11:=0x0000 PHY_ADR5_SW_WRADDR_SHIFT_0:RW+:8:5:=0x00 PHY_ADR4_SW_WRADDR_SHIFT_0:RW+:0:5:=0x00 +// 0x00000681, 0x00000404, // PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1:RW:16:11:=0x0000 PHY_ADR5_SW_WRADDR_SHIFT_1:RW+:8:5:=0x04 PHY_ADR4_SW_WRADDR_SHIFT_1:RW+:0:5:=0x04 +// 0x00000701, 0x00000000, // PHY_GRP_BYPASS_SLAVE_DELAY:RW:16:11:=0x0000 PHY_SW_GRP_SHIFT_3:RW+:8:5:=0x00 PHY_SW_GRP_SHIFT_2:RW+:0:5:=0x00 + REG_DDRPHY_WRITE(i,0x601,dataL=((REG_DDRPHY_READ(i,0x601) & 0xf800ffff) | (DDR_BPCAD<<16)) ); + REG_DDRPHY_WRITE(i,0x681,dataL=((REG_DDRPHY_READ(i,0x681) & 0xf800ffff) | (DDR_BPCAD<<16)) ); + REG_DDRPHY_WRITE(i,0x701,dataL=((REG_DDRPHY_READ(i,0x701) & 0xf800ffff) | (DDR_BPGRP<<16)) ); + +// 0x00000680, 0x04040404, // PHY_ADR3_SW_WRADDR_SHIFT_1:RW+:24:5:=0x04 PHY_ADR2_SW_WRADDR_SHIFT_1:RW+:16:5:=0x04 PHY_ADR1_SW_WRADDR_SHIFT_1:RW+:8:5:=0x04 PHY_ADR0_SW_WRADDR_SHIFT_1:RW+:0:5:=0x04 +// 0x00000681, 0x00000404, // PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1:RW:16:11:=0x0000 PHY_ADR5_SW_WRADDR_SHIFT_1:RW+:8:5:=0x04 PHY_ADR4_SW_WRADDR_SHIFT_1:RW+:0:5:=0x04 + REG_DDRPHY_WRITE(i,0x680,dataL=((REG_DDRPHY_READ(i,0x680) & 0xe0e0e0e0) | 0x05050505) ); + REG_DDRPHY_WRITE(i,0x681,dataL=((REG_DDRPHY_READ(i,0x681) & 0xffffe0e0) | 0x00000505) ); + } +} + + + +static void _rx_cal_code_set(uint32_t ch, uint32_t slice, uint8_t _cal_code_up[][4][16],uint8_t _cal_code_dn[][4][16]) +{ + uint32_t i; + uint32_t code; + for(i=0;i<6;i++) + { + code=(( cal_code_up[ch][slice][i*2+1] &0x3f) <<22) + |(( cal_code_dn[ch][slice][i*2+1] &0x3f) <<16) + |(( cal_code_up[ch][slice][i*2] &0x3f) << 6) + |(( cal_code_dn[ch][slice][i*2] &0x3f) << 0); + REG_DDRPHY_WRITE(ch,0x434+i+slice*0x80,code); + } +} + +static void rx_cal_manual1(uint32_t chmask) +{ + + uint32_t ch,slice; + uint32_t index; + uint32_t trial; + + uint16_t cal_obs; + uint32_t rx_cal_val; + uint32_t NS_WA; //for backward compat + + uint32_t regadd, o_dataL,dataL; + +/* +Reports the calibration results. This parameter is only applicable if the phy_rx_cal_override_X parameter is set to fb1. +There is a phy_rx_cal_obs_X parameter for each of the slices of data sent on the DFI data bus. +? Bit [10] = Calibration result from FDBK +? Bit [9] = rx_cal_rd_dqs; Calibration result from DQS +? Bit [8] = rx_cal_rd_dm; Calibration result from DM +? Bits [7:0] = wrlvl_rd_dq; +*/ + rx_cal_val = DDR_RX_CAL_MAN&0x3f; + if(DDR_RX_CAL_MAN&0x200)NS_WA=1; + else NS_WA=0; + + for(ch=0;ch<4;ch++) + { + for(slice=0;slice<4;slice++) + { + REG_DDRPHY_WRITE(ch,0x452+0x80*slice,REG_DDRPHY_READ(ch,0x452+0x80*slice) | (1<<16)); //IE_on + REG_DDRPHY_WRITE(ch,0x433+0x80*slice,REG_DDRPHY_READ(ch,0x433+0x80*slice)|0x100); //CAL_OVERRIDE on + for(index=0;index<16;index++) + { + cal_code_up[ch][slice][index]=rx_cal_val; + cal_code_dn[ch][slice][index]=rx_cal_val; + fst1[ch][slice][index]=0xff; + lst0[ch][slice][index]=0xff; + for(trial=0;trial<128;trial+=32) + val[ch][slice][index][trial/32]=0; + } + _rx_cal_code_set(ch,slice,cal_code_up,cal_code_dn); + } + } + + for(trial=0;trial<2*rx_cal_val;trial++) + { + for(ch=0;ch<4;ch++) + { + if(!(chmask & (1<=rx_cal_val) + { + cal_code_up[ch][slice][index]=rx_cal_val; + cal_code_dn[ch][slice][index]=2*rx_cal_val-trial; + } + else + { + cal_code_up[ch][slice][index]=trial; + cal_code_dn[ch][slice][index]=rx_cal_val; + } + } + _rx_cal_code_set(ch,slice,cal_code_up,cal_code_dn); + } + } + for(ch=0;ch<4;ch++) + { + for(slice=0;slice<4;slice++) + { + cal_obs = (uint16_t)(REG_DDRPHY_READ(ch,0x439+0x80*slice)>>16); + for(index=0;index<11;index++) + { + if(cal_obs&(1<>1; + if(trial>=rx_cal_val) + { + cal_code_up[ch][slice][index]=rx_cal_val; + cal_code_dn[ch][slice][index]=2*rx_cal_val-trial; + } + else + { + cal_code_up[ch][slice][index]=trial; + cal_code_dn[ch][slice][index]=rx_cal_val; + } + } + } + _rx_cal_code_set(ch,slice,cal_code_up,cal_code_dn); + } + } + + for(ch=0;ch<4;ch++) + { + for(slice=0;slice<4;slice++) + { + REG_DDRPHY_WRITE(ch,0x452+0x80*slice,REG_DDRPHY_READ(ch,0x452+0x80*slice)&~(1<<16)); //IE_off + REG_DDRPHY_WRITE(ch,0x433+0x80*slice,REG_DDRPHY_READ(ch,0x433+0x80*slice)&~0x100); //CAL_OVERRIDE off + } + } + if(1) + { + for(ch=0;ch<4;ch++) + { + for(slice=0;slice<4;slice++) + { + for(index=0;index<11;index++) + { + regadd=0x434+0x80*slice+index/2; + o_dataL=REG_DDRPHY_READ(ch,regadd); + if(index%2)dataL=(o_dataL>>16); + else dataL=o_dataL; + dataL&=0xffff; + } + } + } + } +} + + +static void mode_register_set(uint32_t freq,uintptr_t phychno,uint32_t mr13_val) +{ + + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e040d00|(0x00100000 * phychno)|mr13_val; //MRW 13 chA rkA 0d:00 //FSPOP&FSPWP is fixed to 0, VRO off + WaitDBCMD(); + + if(freq>0x47) + { + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e0401d4|(0x00100000 * phychno); //MRW 1 DeviceFeature1(Post=1.5tck nWR=30 RDpre=static WRPre=2tCK BL=16 + } + else if (freq > 0x2f) + { + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e0401c4|(0x00100000 * phychno); //MRW 1 DeviceFeature1(Post=1.5tck nWR=24 RDpre=static WRPre=2tCK BL=16 + } + else + { + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e0401a4|(0x00100000 * phychno); //MRW 1 DeviceFeature1(Post=1.5tck nWR=16 RDpre=static WRPre=2tCK BL=16 + } + + WaitDBCMD(); + + if(freq>0x47) + { + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e04022e|(0x00100000 * phychno); //MRW 2 DeviceFeature2(0,0SetA,101=WL14,110=RL32) + } + else if (freq > 0x2f) + { + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e040224|(0x00100000 * phychno); //MRW 2 DeviceFeature2(0,0SetA,100=WL12,100=RL24) + } + else + { + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e040252|(0x00100000 * phychno); //MRW 2 DeviceFeature2(0,1SetB,010=WL12,010=RL14) + } + + + WaitDBCMD(); + + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e040300|(0x00100000 * phychno)|DDR_MR3; //MRW 3 chA rkA 03:31 + WaitDBCMD(); + + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e040b00|(0x00100000 * phychno)|DDR_MR11; //MRW 11 + WaitDBCMD(); + + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e040c11|(0x00100000 * phychno); //MRW 12 + WaitDBCMD(); + + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e040e11|(0x00100000 * phychno); //MRW 14 + WaitDBCMD(); + + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e041600|(0x00100000 * phychno)|DDR_MR22; //MRW 22 + WaitDBCMD(); +} + +static void _set_reg(uint32_t ch_mask, uint32_t regadd, uint32_t pos, uint32_t width, uint32_t val) +{ + int ch; + uint32_t dataL; + uint64_t valids; + uint64_t valids_shift; + + valids=(1ULL<0) + { + wait_count[phychno]--; + dataL = REG_DDRPHY_READ ( phychno, 0x0000029B); + if(dataL&0x1) + { + phytrainingok |= (0x1<>24)+((DDR_TVAL0>>12)&0x0f))&0x0f; + REG_DDRPHY_WRITE(phychno, 0x414 + 0x80*i, (REG_DDRPHY_READ(phychno, 0x414 + 0x80*i)&0xf0ffffff) | (j<<24)); + } + } + + if(DDR_TVAL0&0x80) + { + for(phychno=0;phychno<4;phychno++) + { +// 0x00000700, 0x00000001, // PHY_SW_GRP_SHIFT_1:RW+:24:5:=0x00 PHY_SW_GRP_SHIFT_0:RW+:16:5:=0x00 PHY_FREQ_SEL_INDEX:RW:8:2:=0x00 PHY_FREQ_SEL_MULTICAST_EN:RW_D:0:1:=0x01 + REG_DDRPHY_WRITE(phychno, 0x700, (REG_DDRPHY_READ(phychno,0x700)&0xfffffcfe) | (0x2<<8) | (0x0<<0)); + } + } + + for(phychno=0;phychno<4;phychno++) + { + int slice; + + if(DDR_PHYVALID&(1<=TR_ERR) + { + phytrainingok&=~(1< 0 + if(phytrainingok&(1<<1))*((volatile uint32_t*)DBSC_DBPDCNT_1) = 0x0000CF00; + if(phytrainingok&(1<<2))*((volatile uint32_t*)DBSC_DBPDCNT_2) = 0x0000CF00; + if(phytrainingok&(1<<3))*((volatile uint32_t*)DBSC_DBPDCNT_3) = 0x0000CF00; + dsb_sev(); + if(phytrainingok&(1<<0))*((volatile uint32_t*)DBSC_DBPDCNT_0) = 0x0000CF01; //dll_rst_n0 -> 1 + if(phytrainingok&(1<<1))*((volatile uint32_t*)DBSC_DBPDCNT_1) = 0x0000CF01; + if(phytrainingok&(1<<2))*((volatile uint32_t*)DBSC_DBPDCNT_2) = 0x0000CF01; + if(phytrainingok&(1<<3))*((volatile uint32_t*)DBSC_DBPDCNT_3) = 0x0000CF01; + + dsb_sev(); + dsb_sev(); + } + + } /////////////////////////////////////////lvlen&0x21 + + dsb_sev(); + dsb_sev(); + dsb_sev(); + + PLL3_FREQ(freq,FREQ_H); + + dsb_sev(); + dsb_sev(); + dsb_sev(); + +// for(phychno=0;phychno<4;phychno++) +// { +// if(!(phytrainingok&(1<=TE_ERR) + { + phytrainingok&=~(1<0) + { + for(phychno=0;phychno<4;phychno++) + { + if(!(phytrainingok&(1< NEED!! otherwise, copy will not copy + REG_DDRPHY_WRITE (0,0x00000700,0x0301); + REG_DDRPHY_WRITE (1,0x00000700,0x0301); + REG_DDRPHY_WRITE (2,0x00000700,0x0301); + REG_DDRPHY_WRITE (3,0x00000700,0x0301); + + copy_dqdelay(1 ,1,2); // ch1 2:0:1:3 + copy_dqdelay(1 ,3,0); + copy_dqdelay(2 ,1,3); // ch2 3:1:2:0 + copy_dqdelay(2 ,2,0); + copy_dqdelay(3 ,1,3); // ch3 3:1:2:0 + copy_dqdelay(3 ,2,0); + + + if(DDR_LVLEN&0x20) + { + if(DDR_CALVLSIDE== 0x0) + { + copy_csdelay(0,0); + copy_csdelay(1,0); + copy_csdelay(2,0); + copy_csdelay(3,0); + } + else if(DDR_CALVLSIDE== 0x1) + { + copy_csdelay(0,2); + copy_csdelay(1,2); + copy_csdelay(2,2); + copy_csdelay(3,2); + } + else + { + copy_csdelay(0,0); + copy_csdelay(1,2); + copy_csdelay(2,0); + copy_csdelay(3,0); + } + } + + if(DDR_LVLEN&0x4) + { + adjust_rddqsgatedelay(0); + adjust_rddqsgatedelay(1); + adjust_rddqsgatedelay(2); + adjust_rddqsgatedelay(3); + } + } + + return phytrainingok; +} + +static void WaitDBCMD(void) +{ + uint32_t dataL; + + while(1) + { + dataL = *((volatile uint32_t*)DBSC_DBWAIT); //wait DBCMD 1=busy, 0=ready + if((dataL & 0x00000001) == 0x0) break; + } +} + + +static void REG_DDRPHY_WRITE ( uintptr_t phyno, uint32_t regadd, uint32_t regdata) +{ + uint32_t i; + + dsb_sev(); + *((volatile uint32_t*)(DBSC_DBPDRGA_0 + 0x40 * phyno)) = regadd; + i = *((volatile uint32_t*)(DBSC_DBPDRGA_0 + 0x40 * phyno)); // + i = *((volatile uint32_t*)(DBSC_DBPDRGA_0 + 0x40 * phyno)); // + dsb_sev(); + *((volatile uint32_t*)(DBSC_DBPDRGD_0 + 0x40 * phyno)) = regdata; + i = *((volatile uint32_t*)(DBSC_DBPDRGD_0 + 0x40 * phyno)); // + i = *((volatile uint32_t*)(DBSC_DBPDRGD_0 + 0x40 * phyno)); // + dsb_sev(); + (void)i; +} + +static void change_lpddr4_en(uintptr_t phychno, uint32_t mode) +{ +/* + 0x0000071A, 0x027F6E00, // PHY_PAD_FDBK_DRIVE:RW+:8:18:=0x000411 PHY_TDFI_PHY_WRDELAY:RW:0:1:=0x00 + 0x0000071B, 0x047F027F, // PHY_PAD_DQS_DRIVE:RW+:16:12:=0x0040 PHY_PAD_DATA_DRIVE:RW+:0:10:=0x0040 + 0x0000071C, 0x00027F6E, // PHY_PAD_ADDR_DRIVE:RW+:0:18:=0x000411 // LPDDR4_EN bit 14 is it needed? + 0x0000071D, 0x00047F6E, // PHY_PAD_CLK_DRIVE:RW+:0:20:=0x000411 + 0x0000071E, 0x00030F68, // PHY_PAD_FDBK_TERM:RW+:0:18:=0x004410 //PVTP = 0x28, PVTN=0x3d, PVTr=0x10 + 0x0000071F, 0x00010F68, // PHY_PAD_DATA_TERM:RW+:0:17:=0x004410 + 0x00000720, 0x00010F68, // PHY_PAD_DQS_TERM:RW+:0:17:=0x004410 + 0x00000721, 0x00010F68, // PHY_PAD_ADDR_TERM:RW+:0:18:=0x004410 + 0x00000722, 0x00010F68, // PHY_PAD_CLK_TERM:RW+:0:18:=0x004410 + 0x00000723, 0x00027F6E, // PHY_PAD_CKE_DRIVE:RW+:0:18:=0x000411 + 0x00000724, 0x00010F68, // PHY_PAD_CKE_TERM:RW+:0:18:=0x004410 + 0x00000725, 0x00027F6E, // PHY_PAD_RST_DRIVE:RW+:0:18:=0x000411 + 0x00000726, 0x00010F68, // PHY_PAD_RST_TERM:RW+:0:18:=0x004410 + 0x00000727, 0x00027F6E, // PHY_PAD_CS_DRIVE:RW+:0:18:=0x000411 + 0x00000728, 0x00010F68, // PHY_PAD_CS_TERM:RW+:0:18:=0x004410 +*/ + + uint32_t i,from,to; + uint32_t set,clr; + uint32_t dataL; + uint32_t addr; + +#ifdef DDR_LPDDR4_EN_OFF_FIRST +#else + return; +#endif + + if(phychno>=4) + { + from=0; to=3; + } + else + { + from=phychno; to=phychno; + } + + + for(i=from;i<=to;i++) + { +#ifdef DDR_LPDDR4_EN_OFF_FIRST + set = 1ULL <<14; + clr = ~set; + + if(!mode) + { + set = 0; + }; + + addr=0x71c; REG_DDRPHY_WRITE(i,addr,dataL=((REG_DDRPHY_READ(i,addr)&clr)|set) ); + addr=0x71d; REG_DDRPHY_WRITE(i,addr,dataL=((REG_DDRPHY_READ(i,addr)&clr)|set) ); + addr=0x723; REG_DDRPHY_WRITE(i,addr,dataL=((REG_DDRPHY_READ(i,addr)&clr)|set) ); + addr=0x727; REG_DDRPHY_WRITE(i,addr,dataL=((REG_DDRPHY_READ(i,addr)&clr)|set) ); +#else + addr=0x71c; REG_DDRPHY_WRITE(i,addr,dataL=0x00027B22 ); + addr=0x71d; REG_DDRPHY_WRITE(i,addr,dataL=0x00047B22 ); + addr=0x723; REG_DDRPHY_WRITE(i,addr,dataL=0x00027B22 ); + addr=0x727; REG_DDRPHY_WRITE(i,addr,dataL=0x00027B22 ); +#endif + } + +} + +static void copy_csdelay(uint32_t phychno, uint32_t s_byte) +{ + uint32_t dataL[4]; + + dataL[0] = ((REG_DDRPHY_READ ( phychno, 0x00000712))& 0x000fff00) >> 8; + dataL[1] = ((REG_DDRPHY_READ ( phychno, 0x00000713))& 0x00000fff); + dataL[2] = ((REG_DDRPHY_READ ( phychno, 0x00000713))& 0x0fff0000) >> 16; + dataL[3] = ((REG_DDRPHY_READ ( phychno, 0x00000714))& 0x00000fff); + + REG_DDRPHY_WRITE (phychno,0x00000712,( dataL[s_byte] << 8) |((REG_DDRPHY_READ ( phychno, 0x00000712)) & 0x0ff)); + REG_DDRPHY_WRITE (phychno,0x00000713,((dataL[s_byte] << 16)| dataL[s_byte])); + REG_DDRPHY_WRITE (phychno,0x00000714, dataL[s_byte]); + +} + +static void adjust_rddqsgatedelay(uintptr_t phychno) +{ + uint32_t i; + uint32_t s_dataL; + uint32_t d_dataL; + uint32_t teL; + uint32_t leL; + uint32_t meL; + uint32_t fsL; + uint32_t latL,dlyL; + uint32_t maxlatL =0x0; + uint32_t maxdlyL =0x0; + +#ifdef DDR_DBS_DFI_WA + for(i=0;i<4;i++) + { + leL = (REG_DDRPHY_READ ( phychno, 0x00000429 + 0x80*i)>>16) & 0x3fff; + teL = (REG_DDRPHY_READ ( phychno, 0x0000042A + 0x80*i)>>0 ) & 0x3fff; + fsL = (REG_DDRPHY_READ ( phychno, 0x00000456 + 0x80*i)>>16) & 0x3ff; + meL = (leL+teL)>>1; + dlyL = (meL-fsL)&0x1ff; + latL = ((meL-fsL)>>9) & 7; + if(maxlatL < (dlyL + latL* 0x200)) + { + maxdlyL =dlyL; + maxlatL =dlyL + latL* 0x200; + } + } +#endif + + for(i=0;i<4;i++) + { + leL = (REG_DDRPHY_READ ( phychno, 0x00000429 + 0x80*i)>>16) & 0x3fff; + teL = (REG_DDRPHY_READ ( phychno, 0x0000042A + 0x80*i)>>0 ) & 0x3fff; + fsL = (REG_DDRPHY_READ ( phychno, 0x00000456 + 0x80*i)>>16 ) & 0x3ff; + meL = (leL+teL)>>1; + if(meL>9) & 7; +#ifdef DDR_DBS_DFI_WA + if((maxdlyL > 0xff) & (dlyL < 0x100)) + { + REG_DDRPHY_WRITE ( phychno, 0x0454 + 0x80*i, (REG_DDRPHY_READ ( phychno, 0x00000454 + 0x80*i) + 0x00010000)); + } +#endif + s_dataL = REG_DDRPHY_READ ( phychno, 0x0000044C + 0x80*i); + d_dataL = (s_dataL & 0xff000000) | (latL<<16) | dlyL; + REG_DDRPHY_WRITE ( phychno, 0x0000044C + 0x80*i,d_dataL); + } +} + + +static void copy_dqdelay(uintptr_t phychno, uint32_t s_byte, uint32_t d_byte) +{ + uint32_t i; + uint32_t s_dataL; + uint32_t d_dataL; + + for (i=0x43A;i<=0x43E;i++) + { + // 43A-43E:PHY_CLK_WRDQx_SLAVE_DELAY_0 + // 43F-442:PHY_RDDQx_SLAVE_DELAY_0 + // 443-44B:PHY_RDDQS_DQx_FALL_SLAVE_DELAY_0 + if(i==0x43E) + { // 43E:PHY_CLK_WRDQS_SLAVE_DELAY_0:RW+:16:10 + s_dataL = (REG_DDRPHY_READ ( phychno, i+s_byte*0x80)) & 0x0000ffff; // DM code + d_dataL = (REG_DDRPHY_READ ( phychno, i+d_byte*0x80)) & 0xffff0000; // DQS code + REG_DDRPHY_WRITE (phychno,i+d_byte*0x80,(s_dataL|d_dataL)); + } + else + { + s_dataL = REG_DDRPHY_READ ( phychno, i+s_byte*0x80); + REG_DDRPHY_WRITE (phychno,i+d_byte*0x80,s_dataL); + } + } + +} + +uint32_t pvt_pi_training_go_all_soft(uint32_t freq) +{ + uint32_t flag; + uint32_t dataL; + uint32_t phytrainingok; + uint32_t retry; + uintptr_t phychno; + + PLL3_FREQ(freq,0); + + for(phychno=0;phychno<4;phychno++) + { + //dfi_init_start negate + *((volatile uint32_t*)(DBSC_DBDFICNT_0+0x40*phychno)) = 0x00000010; + dsb_sev(); + } + + for(phychno=0;phychno<4;phychno++) + { + ////////////////////// + *((volatile uint32_t*)(DBSC_DBPDRGA_0 + 0x040 * phychno)) = 0x200; + dsb_sev(); + *((volatile uint32_t*)(DBSC_DBPDRGD_0 + 0x040 * phychno)) = 0x20410B01; + dsb_sev(); + + dsb_sev(); + dsb_sev(); + } + do { + dataL = *((volatile uint32_t*)(DBSC_PLL_LOCK_0+0x100*0)) & 0x1f; + dataL |= *((volatile uint32_t*)(DBSC_PLL_LOCK_0+0x100*1)) & 0x1f; + dataL |= *((volatile uint32_t*)(DBSC_PLL_LOCK_0+0x100*2)) & 0x1f; + dataL |= *((volatile uint32_t*)(DBSC_PLL_LOCK_0+0x100*3)) & 0x1f; + dsb_sev(); + } while(dataL); + + dsb_sev(); + dsb_sev(); + + if(!(DDR_UPDT_WA&0x2000)) + { + PLL3_FREQ(freq,2); + dsb_sev(); + dsb_sev(); + } + +// //CHANGE IMPEDANCE CODE to LP4 MODE +// change_lpddr4_en(0xf,1); + + for(phychno=0;phychno<4;phychno++) + { + //DFI FREQ + *((volatile uint32_t*)(DBSC_DFI_FREQ_0 +0x040 * phychno)) = 2; +// *((volatile uint32_t*)(DBSC_DFI_FREQ_0 +0x040 * phychno)) = 0; + dsb_sev(); + //CHG_ACK + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_0 + 0x40 * phychno)) = 0x0CF20000; + dsb_sev(); +// //CHG_ACK + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_0 + 0x40 * phychno)) = 0x0; + dsb_sev(); + + dsb_sev(); + dsb_sev(); + } + + + /////////////////////////////////////////////////////////////////////// + //unlock check + do { + dataL = *((volatile uint32_t*)(DBSC_PLL_LOCK_0+0x100*0)) & 0x1f; + dataL |= *((volatile uint32_t*)(DBSC_PLL_LOCK_0+0x100*1)) & 0x1f; + dataL |= *((volatile uint32_t*)(DBSC_PLL_LOCK_0+0x100*2)) & 0x1f; + dataL |= *((volatile uint32_t*)(DBSC_PLL_LOCK_0+0x100*3)) & 0x1f; + dsb_sev(); + } while(dataL); + + dsb_sev(); + dsb_sev(); + + PLL3_FREQ(freq,0); + + dsb_sev(); + dsb_sev(); + + for(phychno=0;phychno<4;phychno++) + { + //DFI FREQ + *((volatile uint32_t*)(DBSC_DFI_FREQ_0 +0x040 * phychno)) =0; // 0; +// *((volatile uint32_t*)(DBSC_DFI_FREQ_0 +0x040 * phychno)) =2; // 2 + //CHG_ACK + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_0 + 0x40 * phychno)) = 0x0CF20000; + //CHG_ACK + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_0 + 0x40 * phychno)) = 0x0; + + dsb_sev(); + dsb_sev(); + } + +//END:timing critical: + //unlock check + do { + dataL = *((volatile uint32_t*)(DBSC_PLL_LOCK_0+0x100*0)) & 0x1f; + dataL |= *((volatile uint32_t*)(DBSC_PLL_LOCK_0+0x100*1)) & 0x1f; + dataL |= *((volatile uint32_t*)(DBSC_PLL_LOCK_0+0x100*2)) & 0x1f; + dataL |= *((volatile uint32_t*)(DBSC_PLL_LOCK_0+0x100*3)) & 0x1f; + } while(dataL); + + dsb_sev(); + dsb_sev(); + + PLL3_FREQ(freq,2); + + dsb_sev(); + dsb_sev(); + + for(phychno=0;phychno<4;phychno++) + { + //DFI FREQ + *((volatile uint32_t*)(DBSC_DFI_FREQ_0 +0x040 * phychno)) = 2; + dsb_sev(); + //CHG_ACK + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_0 + 0x40 * phychno)) = 0x0CF20000; + dsb_sev(); + //CHG_ACK + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_0 + 0x40 * phychno)) = 0x0; + + dsb_sev(); + dsb_sev(); + } + + retry=100000; + flag=0; + while(retry>0) + { + for(phychno=0;phychno<4;phychno++) + { + if(flag & (1<0x53) + { + // // def 3200 + } + else if(freq>0x47) + { +// freq2800_reg_set(); // need more tuning + } + else if(freq>0x2f) + { +// freq2400_reg_set(); // need more tuning + } + else + { + freq1600_reg_set(); + } + + //Set PCB bit swap connection + for( i=0; i<9+5; i++ ) + { + REG_DDRPHY_WRITE(0,DDR_SIP_SWAP_CH0[i][0],DDR_SIP_SWAP_CH0[i][1]); + REG_DDRPHY_WRITE(1,DDR_SIP_SWAP_CH1[i][0],DDR_SIP_SWAP_CH1[i][1]); + REG_DDRPHY_WRITE(2,DDR_SIP_SWAP_CH2[i][0],DDR_SIP_SWAP_CH2[i][1]); + REG_DDRPHY_WRITE(3,DDR_SIP_SWAP_CH3[i][0],DDR_SIP_SWAP_CH3[i][1]); + } + + for (i=0;i<4;i++) + { + REG_DDRPHY_WRITE(i,0x40B,REG_DDRPHY_READ(i,0x40B) & (0xfffcffff)); + REG_DDRPHY_WRITE(i,0x48B,REG_DDRPHY_READ(i,0x48B) & (0xfffcffff)); + REG_DDRPHY_WRITE(i,0x50B,REG_DDRPHY_READ(i,0x50B) & (0xfffcffff)); + REG_DDRPHY_WRITE(i,0x58B,REG_DDRPHY_READ(i,0x58B) & (0xfffcffff)); + } + + if(DDR_CALVLSIDE== 0x0) + { + REG_DDRPHY_WRITE(0,0x709,((REG_DDRPHY_READ(0,0x709) & 0xffffff00) | 0x0000010)); + REG_DDRPHY_WRITE(0,0x257,((REG_DDRPHY_READ(0,0x257) & 0xfffffff0) | 0x0000001)); + + REG_DDRPHY_WRITE(1,0x709,((REG_DDRPHY_READ(1,0x709) & 0xffffff00) | 0x0000011)); + REG_DDRPHY_WRITE(1,0x257,((REG_DDRPHY_READ(1,0x257) & 0xfffffff0) | 0x0000001)); + REG_DDRPHY_WRITE(1,0x60c,0x00543210); + REG_DDRPHY_WRITE(1,0x421,((REG_DDRPHY_READ(1,0x421) & 0xfffffffe) | 0x0000001)); + REG_DDRPHY_WRITE(1,0x4a1,((REG_DDRPHY_READ(1,0x4a1) & 0xfffffffe) | 0x0000001)); + REG_DDRPHY_WRITE(1,0x521,((REG_DDRPHY_READ(1,0x521) & 0xfffffffe) | 0x0000000)); + REG_DDRPHY_WRITE(1,0x5a1,((REG_DDRPHY_READ(1,0x5a1) & 0xfffffffe) | 0x0000000)); + + REG_DDRPHY_WRITE(2,0x709,((REG_DDRPHY_READ(2,0x709) & 0xffffff00) | 0x0000000)); + REG_DDRPHY_WRITE(2,0x257,((REG_DDRPHY_READ(2,0x257) & 0xfffffff0) | 0x0000001)); + REG_DDRPHY_WRITE(2,0x60c,0x00DCBA98); + REG_DDRPHY_WRITE(2,0x421,((REG_DDRPHY_READ(2,0x421) & 0xfffffffe) | 0x0000000)); + REG_DDRPHY_WRITE(2,0x4a1,((REG_DDRPHY_READ(2,0x4a1) & 0xfffffffe) | 0x0000000)); + REG_DDRPHY_WRITE(2,0x521,((REG_DDRPHY_READ(2,0x521) & 0xfffffffe) | 0x0000001)); + REG_DDRPHY_WRITE(2,0x5a1,((REG_DDRPHY_READ(2,0x5a1) & 0xfffffffe) | 0x0000001)); + + REG_DDRPHY_WRITE(3,0x709,((REG_DDRPHY_READ(3,0x709) & 0xffffff00) | 0x0000000)); + REG_DDRPHY_WRITE(3,0x257,((REG_DDRPHY_READ(3,0x257) & 0xfffffff0) | 0x0000001)); + REG_DDRPHY_WRITE(3,0x60c,0x00DCBA98); + REG_DDRPHY_WRITE(3,0x421,((REG_DDRPHY_READ(3,0x421) & 0xfffffffe) | 0x0000000)); + REG_DDRPHY_WRITE(3,0x4a1,((REG_DDRPHY_READ(3,0x4a1) & 0xfffffffe) | 0x0000000)); + REG_DDRPHY_WRITE(3,0x521,((REG_DDRPHY_READ(3,0x521) & 0xfffffffe) | 0x0000001)); + REG_DDRPHY_WRITE(3,0x5a1,((REG_DDRPHY_READ(3,0x5a1) & 0xfffffffe) | 0x0000001)); + } + + if(DDR_CALVLSIDE== 0x1) + { + REG_DDRPHY_WRITE(0,0x709,((REG_DDRPHY_READ(0,0x709) & 0xffffff00) | 0x0000010)); + REG_DDRPHY_WRITE(0,0x257,((REG_DDRPHY_READ(0,0x257) & 0xfffffff0) | 0x0000004)); + + REG_DDRPHY_WRITE(1,0x709,((REG_DDRPHY_READ(1,0x709) & 0xffffff00) | 0x0000011)); + REG_DDRPHY_WRITE(1,0x257,((REG_DDRPHY_READ(1,0x257) & 0xfffffff0) | 0x0000004)); + REG_DDRPHY_WRITE(1,0x60c,0x00DCBA98); + REG_DDRPHY_WRITE(1,0x421,((REG_DDRPHY_READ(1,0x421) & 0xfffffffe) | 0x0000001)); + REG_DDRPHY_WRITE(1,0x4a1,((REG_DDRPHY_READ(1,0x4a1) & 0xfffffffe) | 0x0000001)); + REG_DDRPHY_WRITE(1,0x521,((REG_DDRPHY_READ(1,0x521) & 0xfffffffe) | 0x0000000)); + REG_DDRPHY_WRITE(1,0x5a1,((REG_DDRPHY_READ(1,0x5a1) & 0xfffffffe) | 0x0000000)); + + REG_DDRPHY_WRITE(2,0x709,((REG_DDRPHY_READ(2,0x709) & 0xffffff00) | 0x0000000)); + REG_DDRPHY_WRITE(2,0x257,((REG_DDRPHY_READ(2,0x257) & 0xfffffff0) | 0x0000004)); + REG_DDRPHY_WRITE(2,0x60c,0x00543210); + REG_DDRPHY_WRITE(2,0x421,((REG_DDRPHY_READ(2,0x421) & 0xfffffffe) | 0x0000000)); + REG_DDRPHY_WRITE(2,0x4a1,((REG_DDRPHY_READ(2,0x4a1) & 0xfffffffe) | 0x0000000)); + REG_DDRPHY_WRITE(2,0x521,((REG_DDRPHY_READ(2,0x521) & 0xfffffffe) | 0x0000001)); + REG_DDRPHY_WRITE(2,0x5a1,((REG_DDRPHY_READ(2,0x5a1) & 0xfffffffe) | 0x0000001)); + + REG_DDRPHY_WRITE(3,0x709,((REG_DDRPHY_READ(3,0x709) & 0xffffff00) | 0x0000000)); + REG_DDRPHY_WRITE(3,0x257,((REG_DDRPHY_READ(3,0x257) & 0xfffffff0) | 0x0000004)); + REG_DDRPHY_WRITE(3,0x60c,0x00543210); + REG_DDRPHY_WRITE(3,0x421,((REG_DDRPHY_READ(3,0x421) & 0xfffffffe) | 0x0000000)); + REG_DDRPHY_WRITE(3,0x4a1,((REG_DDRPHY_READ(3,0x4a1) & 0xfffffffe) | 0x0000000)); + REG_DDRPHY_WRITE(3,0x521,((REG_DDRPHY_READ(3,0x521) & 0xfffffffe) | 0x0000001)); + REG_DDRPHY_WRITE(3,0x5a1,((REG_DDRPHY_READ(3,0x5a1) & 0xfffffffe) | 0x0000001)); + } +#ifdef DDR_VREF + for (i=0;i<4;i++) + { + REG_DDRPHY_WRITE(i,0x70F,((REG_DDRPHY_READ(i,0x70f) & 0x000000ff)|(DDR_VREF << 8) )); + REG_DDRPHY_WRITE(i,0x710,(DDR_VREF |(DDR_VREF << 16) )); + REG_DDRPHY_WRITE(i,0x711,(DDR_VREF |(DDR_VREF << 16) )); + } +#endif + + +#ifdef DDR_PAD_BOOST + for (i=0;i<4;i++) + { + REG_DDRPHY_WRITE(i,0x71B,((REG_DDRPHY_READ(i,0x71B) & 0xfbfffdff) )); //phy_pad_dqs_drive ,phy_pad_data_drive + } +#else + for (i=0;i<4;i++) + { + REG_DDRPHY_WRITE(i,0x71B,((REG_DDRPHY_READ(i,0x71B) | 0x04000200) )); //phy_pad_dqs_drive ,phy_pad_data_drive + } +#endif + +#ifdef DDR_PAD_ADDR_CS_DRIVE + for (i=0;i<4;i++){ + REG_DDRPHY_WRITE(i,0x71C,DDR_PAD_ADDR_CS_DRIVE); //pad_addr_drive + REG_DDRPHY_WRITE(i,0x727,DDR_PAD_ADDR_CS_DRIVE); //pad_cs_drive + } +#endif + +//#define CH0B +#ifdef CH0B + // CH0 CALVL for swap + // CH0 CALVL to CS[2] ( M2 dq_h -> soc M2 dq_h ) + REG_DDRPHY_WRITE(0,0x0257,0x00181704); // PI_CALVL_CS_MAP:RW:0:4:= 0x4 + //0x0000060F, 0x01000000, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 3 + REG_DDRPHY_WRITE(0,0x060F,0x02DCBA98); +#endif + // CH1 CALVL for swap + // CH1 CALVL can be done only for CS[2] ( M2 dq_h -> soc M2 dq_h ) + REG_DDRPHY_WRITE(1,0x0257,0x00181704); // PI_CALVL_CS_MAP:RW:0:4:= 0x4 + + *((volatile uint32_t*)DBSC_DBDFIPMSTRCNF) = 0x00000001; //DFI_PHYMSTR_ACK = 1 + } // (mode==0 || mode==1|| mode==3) + + + ///////////////////////////////////////////////////////////////////////////////////////////////////////////end_of_mode1 + pvt_lvl_enable_set(0x3f); + + set_cacs_delay(); + + REG_DDRPHY_WRITE(0,0x44c,0x0004000c); + REG_DDRPHY_WRITE(0,0x4cc,0x0004000c); + REG_DDRPHY_WRITE(0,0x54c,0x00040042); + REG_DDRPHY_WRITE(0,0x5cc,0x0004004e); + REG_DDRPHY_WRITE(1,0x44c,0x0004004e); + REG_DDRPHY_WRITE(1,0x4cc,0x0004005a); + REG_DDRPHY_WRITE(1,0x54c,0x00040078); + REG_DDRPHY_WRITE(1,0x5cc,0x00040042); + REG_DDRPHY_WRITE(2,0x44c,0x00040012); + REG_DDRPHY_WRITE(2,0x4cc,0x00040066); + REG_DDRPHY_WRITE(2,0x54c,0x000301f4); + REG_DDRPHY_WRITE(2,0x5cc,0x0004004e); + REG_DDRPHY_WRITE(3,0x44c,0x0004001e); + REG_DDRPHY_WRITE(3,0x4cc,0x00040042); + REG_DDRPHY_WRITE(3,0x54c,0x00040066); + REG_DDRPHY_WRITE(3,0x5cc,0x000400c6); + +// 9/24 +//cacs_capture_cnt//cacs_resp_wait_cnt +// 0x00000257, 0x00181701, // PI_TDFI_CALVL_CC_F0:RW:16:10:=0x0018 PI_TDFI_CALVL_EN:RW:8:8:=0x17 PI_CALVL_CS_MAP:RW:0:4:=0x03 +// 0x00000258, 0x00280006, // PI_TDFI_CALVL_CC_F1:RW:16:10:=0x0028 PI_TDFI_CALVL_CAPTURE_F0:RW:0:10:=0x0006 +// 0x00000259, 0x00280016, // PI_TDFI_CALVL_CC_F2:RW:16:10:=0x0028 PI_TDFI_CALVL_CAPTURE_F1:RW:0:10:=0x0016 +// 0x0000025A, 0x00000016, // PI_TDFI_CALVL_CAPTURE_F2:RW:0:10:=0x0016 + for(ch=0;ch<4;ch++){ +// 0x00000610, 0x00020010, // PHY_ADR_CALVL_RESP_WAIT_CNT_0:RW:24:4:=0x00 PHY_ADR_CALVL_CAPTURE_CNT_0:RW:16:4:=0x02 PHY_ADR_CALVL_NUM_PATTERNS_0:RW:8:2:=0x00 PHY_ADR_CALVL_RANK_CTRL_0:RW:0:5:=0x10 +// 0x0000060A, 0x00400320, // PHY_ADR_CALVL_COARSE_DLY_0:RW:16:11:=0x0040 PHY_ADR_CALVL_START_0:RW:0:11:=0x0320 +// 0x0000060B, 0x00000040, // PHY_ADR_CALVL_QTR_0:RW:0:11:=0x0040 +// 0x00000624, 0x00000003, // PHY_ADR_CALVL_DLY_STEP_0:RW+:0:4:=0x03 + + uint32_t cc=(DDR_CACS_CCCP>>16)&0xff; + uint32_t cp=(DDR_CACS_CCCP>>0)&0xff; + + REG_DDRPHY_WRITE(ch,0x257,(REG_DDRPHY_READ(ch,0x257) & 0x0000ffff) | (cc<<16)); + REG_DDRPHY_WRITE(ch,0x258,(REG_DDRPHY_READ(ch,0x258) & 0x00000000) | (cc<<16) | cp); + REG_DDRPHY_WRITE(ch,0x259,(REG_DDRPHY_READ(ch,0x259) & 0x00000000) | (cc<<16) | cp); + REG_DDRPHY_WRITE(ch,0x25a,(REG_DDRPHY_READ(ch,0x25a) & 0x00000000) | cp); + + + for(slice=0;slice<2;slice++){ + REG_DDRPHY_WRITE(ch,0x610+0x80*slice,(REG_DDRPHY_READ(ch,0x610+0x80*slice) & 0xf0f0ffff ) + | ((DDR_CACS_RESP_WAIT_CNT&0x0f)<<24) + | ((DDR_CACS_CAPTURE_CNT&0x0f)<<16) + ); + REG_DDRPHY_WRITE(ch,0x60a+0x80*slice,(REG_DDRPHY_READ(ch,0x60a+0x80*slice) & 0xfffff000 ) + | DDR_CACS_START + ); + REG_DDRPHY_WRITE(ch,0x60b+0x80*slice,(REG_DDRPHY_READ(ch,0x60b+0x80*slice) & 0xfffff000 ) + | DDR_CACS_QTR + ); + REG_DDRPHY_WRITE(ch,0x624+0x80*slice,(REG_DDRPHY_READ(ch,0x624+0x80*slice) & 0xfffffff0 ) + | DDR_CACS_STEP + ); + } + +// 0x00000704, 0x00020040, // PHY_CSLVL_CAPTURE_CNT:RW:16:4:=0x02 PHY_CSLVL_QTR:RW:0:11:=0x0040 +// 0x00000705, 0x00020055, // PHY_CSLVL_DEBUG_MODE:RW:24:1:=0x00 PHY_CSLVL_COARSE_CAPTURE_CNT:RW:16:4:=0x02 PHY_CSLVL_COARSE_DLY:RW:0:11:=0x0055 + slice=0; + REG_DDRPHY_WRITE(ch,0x704+0x80*slice,(REG_DDRPHY_READ(ch,0x704+0x80*slice) & 0xfff0ffff) | ((DDR_CACS_CAPTURE_CNT&0x0f)<<16)); + REG_DDRPHY_WRITE(ch,0x705+0x80*slice,(REG_DDRPHY_READ(ch,0x705+0x80*slice) & 0xfff0ffff) | ((DDR_CACS_CAPTURE_CNT&0x0f)<<16)); + } +//------- + + dsb_sev(); + dsb_sev(); + dsb_sev(); + + PLL3_FREQ(freq,0); + + dsb_sev(); + dsb_sev(); + dsb_sev(); + +#ifdef DDR_PAD_CAL_WA + for(i=0;i<4;i++) + { + REG_DDRPHY_WRITE(i,0x72c,REG_DDRPHY_READ(i,0x72c)& ~(1<<24) ); //init_start_disable clear + } + + // Rx Cal IE issue w/a + for(ch=0;ch<4;ch++) + { + for(slice=0;slice<4;slice++) + { + if(DDR_TVAL2&0x1) + { + REG_DDRPHY_WRITE(ch,0x452+0x80*slice,REG_DDRPHY_READ(ch,0x452+0x80*slice) | (1<<16)); + } +// 0x00000433, 0x00200000, // PHY_RX_CAL_SAMPLE_WAIT_0:RW:16:8:=0x20 PHY_RX_CAL_OVERRIDE_0:RW:8:1:=0x00 SC_PHY_RX_CAL_START_0:WR:0:1:=0x00 + if(DDR_TVAL2&0x2) + { + REG_DDRPHY_WRITE(ch,0x433+slice*0x80,REG_DDRPHY_READ(ch,0x433+slice*0x80)|0x100); + } + else + { + REG_DDRPHY_WRITE(ch,0x433+slice*0x80,REG_DDRPHY_READ(ch,0x433+slice*0x80)&0xfffffeff); + } + } + } + dsb_sev(); +#endif + + *((volatile uint32_t*)DBSC_DBDFICNT_0) = 0x00000010; //dbdficnt0 freq_ratio = 01 (2:1)init_start =1 + *((volatile uint32_t*)DBSC_DBDFICNT_1) = 0x00000010; + *((volatile uint32_t*)DBSC_DBDFICNT_2) = 0x00000010; + *((volatile uint32_t*)DBSC_DBDFICNT_3) = 0x00000010; + dsb_sev(); + + dsb_sev(); + dsb_sev(); + + *((volatile uint32_t*)DBSC_DBDFICNT_0) = 0x00000011; //dbdficnt0 freq_ratio = 01 (2:1)init_start =1 + *((volatile uint32_t*)DBSC_DBDFICNT_1) = 0x00000011; + *((volatile uint32_t*)DBSC_DBDFICNT_2) = 0x00000011; + *((volatile uint32_t*)DBSC_DBDFICNT_3) = 0x00000011; + dsb_sev(); + + dsb_sev(); + dsb_sev(); + + *((volatile uint32_t*)DBSC_DBPDCNT_0) = 0x000000; //dll_rst_n0 -> 1 + *((volatile uint32_t*)DBSC_DBPDCNT_1) = 0x000000; + *((volatile uint32_t*)DBSC_DBPDCNT_2) = 0x000000; + *((volatile uint32_t*)DBSC_DBPDCNT_3) = 0x000000; + dsb_sev(); + + *((volatile uint32_t*)DBSC_DBPDCNT_0) = 0x0000CF00; //dll_rst_n0 -> 1 + *((volatile uint32_t*)DBSC_DBPDCNT_1) = 0x0000CF00; + *((volatile uint32_t*)DBSC_DBPDCNT_2) = 0x0000CF00; + *((volatile uint32_t*)DBSC_DBPDCNT_3) = 0x0000CF00; + dsb_sev(); + + *((volatile uint32_t*)DBSC_DBPDCNT_0) = 0x0000CF01; //dll_rst_n0 -> 1 + *((volatile uint32_t*)DBSC_DBPDCNT_1) = 0x0000CF01; + *((volatile uint32_t*)DBSC_DBPDCNT_2) = 0x0000CF01; + *((volatile uint32_t*)DBSC_DBPDCNT_3) = 0x0000CF01; + dsb_sev(); + + SoftDelay(1*1000); //wait for 1ms + + phytrainingok=0; + //Need Handshake sequence betweed DBSC and PHY + if(DDR_UPDT_WA&0x40) + { + for(ch=0;ch<4;ch++) + { + for(slice=0;slice<4;slice++) + { +// 0x00000433, 0x00200000, // PHY_RX_CAL_SAMPLE_WAIT_0:RW:16:8:=0x20 PHY_RX_CAL_OVERRIDE_0:RW:8:1:=0x00 SC_PHY_RX_CAL_START_0:WR:0:1:=0x00 + if(DDR_TVAL2&0x2) + { + REG_DDRPHY_WRITE(ch,0x433+slice*0x80,REG_DDRPHY_READ(ch,0x433+slice*0x80)|0x1|0x100); + } + else + { + REG_DDRPHY_WRITE(ch,0x433+slice*0x80,REG_DDRPHY_READ(ch,0x433+slice*0x80)|0x1); + } + } + } + dsb_sev(); + } + + j=(DDR_UPDT_WA>>24)&0xff; + k=0; + for(phychno=0;phychno<4;phychno++) + { + if(!(DDR_PHYVALID&(1<0) + { //after first init, init_start should be negated so as to wakeup pll + *((volatile uint32_t*)(DBSC_DBDFICNT_0+0x40*phychno)) = 0x00000011; //dbdficnt0 freq_ratio = 01 (2:1)init_start =1 + dsb_sev(); + *((volatile uint32_t*)(DBSC_DBDFICNT_0+0x40*phychno)) = 0x00000010; //dbdficnt0 freq_ratio = 01 (2:1)init_start =0 + dsb_sev(); +// 0x000004B3, 0x00200000, // PHY_RX_CAL_SAMPLE_WAIT_1:RW:16:8:=0x20 PHY_RX_CAL_OVERRIDE_1:RW:8:1:=0x00 SC_PHY_RX_CAL_START_1:WR:0:1:=0x00 + for(retry=0;retry<4;retry++) + { + REG_DDRPHY_WRITE(phychno,0x433+retry*0x80,REG_DDRPHY_READ(phychno,0x433+retry*0x80)|0x1); + } + } + + retry=0; + while(retry<2048) + { + dataL = *((volatile uint32_t*)(DBSC_INITCOMP_0+phychno*0x40)); //Wait for DBSC_INITCOMP_0[0] is 1 + if((dataL & 0x00000001) == 0x1) break; + retry++; + } + if(retry<2048) + { + phytrainingok|=(1<>18)& 0x03f; + pvtn_l=(dataL >>12)& 0x03f; + pvtp_h=(dataL >> 6)& 0x03f; + pvtp_l=(dataL >> 0)& 0x03f; + for( i=0; i>12)& 0x01f; + dataL=(o_dataL & 0xffe00000) | (((pvtr+DDR_PVTR_ADJ)&0x1f)<<12) | (((pvtn_h+pvtn_l)>>1)<<6) | ((pvtp_h+pvtp_l)>>1); + REG_DDRPHY_WRITE(j,DDR_PHY_DDR_PHY_PVT_OVERWITE_1600[i][0],dataL); + + dataL=REG_DDRPHY_READ(j,DDR_PHY_DDR_PHY_PVT_OVERWITE_1600[i][0]); + } + } + + for(ch=0;ch<4;ch++) + { + for(slice=0;slice<4;slice++) + { + REG_DDRPHY_WRITE(ch,0x452+0x80*slice,REG_DDRPHY_READ(ch,0x452+0x80*slice) & ~(1<<16));//PAD_PHY_IE_MODE OFF +// 0x00000433, 0x00200000, // PHY_RX_CAL_SAMPLE_WAIT_0:RW:16:8:=0x20 PHY_RX_CAL_OVERRIDE_0:RW:8:1:=0x00 SC_PHY_RX_CAL_START_0:WR:0:1:=0x00 + REG_DDRPHY_WRITE(ch,0x433+slice*0x80,REG_DDRPHY_READ(ch,0x433+slice*0x80)&0xffff0000); + } + } + + } +#endif + + if(DDR_RX_CAL_MAN&0x100) + { + rx_cal_manual1(phytrainingok); + } + + //Need Handshake sequence betweed DBSC and PHY + + if(DDR_UPDT_WA&0x2) + { + pvt_manual_update(0x0f); + } + if(DDR_UPDT_WA&0x4) + { + pvt_manual_update(0xf0); + } + + //CHANGE IMPEDANCE CODE to CMOS MODE + change_lpddr4_en(0xf,0); + + for(phychno=0;phychno<4;phychno+=1) + { + if((DDR_PHYVALID&0x0f)==0x0f) + { + phychno=0x0f; + } + else + { + if( (DDR_PHYVALID&(1< 1 + *((volatile uint32_t*)DBSC_DBPDCNT_1) = 0x0000CF00; + *((volatile uint32_t*)DBSC_DBPDCNT_2) = 0x0000CF00; + *((volatile uint32_t*)DBSC_DBPDCNT_3) = 0x0000CF00; + dsb_sev(); + + for(i=0;i<1000;i++) + { + //dummy + REG_DDRPHY_READ(0,0x229); + REG_DDRPHY_READ(1,0x229); + REG_DDRPHY_READ(2,0x229); + REG_DDRPHY_READ(3,0x229); + } + } + + if(DDR_UPDT_WA&0x10) + { + *((volatile uint32_t*)DBSC_DBDFICNT_0) = 0x00000010; //dbdficnt0 freq_ratio = 01 (2:1)init_start =1 + *((volatile uint32_t*)DBSC_DBDFICNT_1) = 0x00000010; + *((volatile uint32_t*)DBSC_DBDFICNT_2) = 0x00000010; + *((volatile uint32_t*)DBSC_DBDFICNT_3) = 0x00000010; + *((volatile uint32_t*)DBSC_DBDFICNT_0) = 0x00000011; //dbdficnt0 freq_ratio = 01 (2:1)init_start =1 + *((volatile uint32_t*)DBSC_DBDFICNT_1) = 0x00000011; + *((volatile uint32_t*)DBSC_DBDFICNT_2) = 0x00000011; + *((volatile uint32_t*)DBSC_DBDFICNT_3) = 0x00000011; + dsb_sev(); + } + + if(DDR_UPDT_WA&0x08) + { + *((volatile uint32_t*)DBSC_DBPDCNT_0) = 0x0000CF01; //dll_rst_n0 -> 1 + *((volatile uint32_t*)DBSC_DBPDCNT_1) = 0x0000CF01; + *((volatile uint32_t*)DBSC_DBPDCNT_2) = 0x0000CF01; + *((volatile uint32_t*)DBSC_DBPDCNT_3) = 0x0000CF01; + dsb_sev(); + + for(i=0;i<1000;i++){//dummy + REG_DDRPHY_READ(0,0x229); + REG_DDRPHY_READ(1,0x229); + REG_DDRPHY_READ(2,0x229); + REG_DDRPHY_READ(3,0x229); + } + } + + if(DDR_UPDT_WA&0x18) + { + for(i=0;i<1000;i++) + { + //dummy + REG_DDRPHY_READ(0,0x229); + REG_DDRPHY_READ(1,0x229); + REG_DDRPHY_READ(2,0x229); + REG_DDRPHY_READ(3,0x229); + } + } + + if(DDR_UPDT_WA&0x10) + { + *((volatile uint32_t*)DBSC_DBDFICNT_0) = 0x00000010; //dbdficnt0 freq_ratio = 01 (2:1)init_start =1 + *((volatile uint32_t*)DBSC_DBDFICNT_1) = 0x00000010; + *((volatile uint32_t*)DBSC_DBDFICNT_2) = 0x00000010; + *((volatile uint32_t*)DBSC_DBDFICNT_3) = 0x00000010; + dsb_sev(); + + //Need Handshake sequence betweed DBSC and PHY + while(1) + { + dataL = *((volatile uint32_t*)DBSC_INITCOMP_0); //Wait for DBSC_INITCOMP_0[0] is 1 + if((dataL & 0x00000001) == 0x1) break; + } + + while(1) + { + dataL = *((volatile uint32_t*)DBSC_INITCOMP_1); //Wait for DBSC_INITCOMP_1[0] is 1 + if((dataL & 0x00000001) == 0x1) break; + } + + while(1) + { + dataL = *((volatile uint32_t*)DBSC_INITCOMP_2); //Wait for DBSC_INITCOMP_2[0] is 1 + if((dataL & 0x00000001) == 0x1) break; + } + + while(1) + { + dataL = *((volatile uint32_t*)DBSC_INITCOMP_3); //Wait for DBSC_INITCOMP_3[0] is 1 + if((dataL & 0x00000001) == 0x1) break; + } + } + + *((volatile uint32_t*)DBSC_DBBUS0CNF1) = 0x70000100; //dbbus0cnf1 + *((volatile uint32_t*)DBSC_DBBUS0CNF0) = 0x18010001; //dbbus0cnf + +//Auto Refresh setting +// *((volatile uint32_t*)DBSC_DBRFCNF1) = 0x00081860; //dbrfcnf1 refpmax=8 refint=6240 + if(freq>0x53) *((volatile uint32_t*)DBSC_DBRFCNF1) = 0x00081860; //dbrfcnf1 refpmax=8 refint=6240 + else if(freq>0x47) *((volatile uint32_t*)DBSC_DBRFCNF1) = 0x00081554; //dbrfcnf1 refpmax=8 refint=5460 + else if(freq>0x2f) *((volatile uint32_t*)DBSC_DBRFCNF1) = 0x00081248; //dbrfcnf1 refpmax=8 refint=4680 + else *((volatile uint32_t*)DBSC_DBRFCNF1) = 0x00080C30; //dbrfcnf1 refpmax=8 refint=3120 + + *((volatile uint32_t*)DBSC_DBRFCNF2) = 0x00010000; //dbrfcnf2 refpmin=1 refints=0 + + *((volatile uint32_t*)DBSC_DBRFEN) = 0x00000001; //dbrfen + +//DRAM ACCESS enable + *((volatile uint32_t*)DBSC_DBACEN) = 0x00000001; //dbacen + + return phytrainingok; +} + +#if 0 +void freq2800_reg_set() +{ + uint32_t i; + + for(i=0;i<4;i++) + { + REG_DDRPHY_WRITE(i,0x22B, (DDR2800_PI_CASLAT_LIN<<24)|(DDR2800_PI_WRLAT<<16)|(DDR2800_PI_CASLAT_LIN<<8)|(DDR2800_PI_WRLAT<<0)); + REG_DDRPHY_WRITE(i,0x22C, 0x00020000|(DDR2800_PI_CASLAT_LIN<<8)|(DDR2800_PI_WRLAT<<0)); + + REG_DDRPHY_WRITE(i,0x252, (DDR2800_PI_RDLAT_ADJ<<16)|(DDR2800_PI_RDLAT_ADJ<<8)|(DDR2800_PI_RDLAT_ADJ<<0)); + REG_DDRPHY_WRITE(i,0x253, (DDR2800_PI_WRLAT_ADJ<<16)|(DDR2800_PI_WRLAT_ADJ<<8)|(DDR2800_PI_WRLAT_ADJ<<0)); + + REG_DDRPHY_WRITE(i,0x28A, (DDR2800_PI_TFC<<16)|(DDR2800_PI_TFC<<0)); + REG_DDRPHY_WRITE(i,0x28B, (DDR2800_PI_TRTP<<24)|(DDR2800_PI_TCCD<<16)|(DDR2800_PI_TFC<<0)); + REG_DDRPHY_WRITE(i,0x28C, (DDR2800_PI_TWR<<24) |(DDR2800_PI_TWTR<<16)|(DDR2800_PI_TRCD<<8)|(DDR2800_PI_TRP<<0)); + REG_DDRPHY_WRITE(i,0x28D, (DDR2800_PI_TRAS_MIN<<24)|(DDR2800_PI_TRAS_MAX<<0)); + REG_DDRPHY_WRITE(i,0x28E, (DDR2800_PI_TMRW<<24) | (DDR2800_PI_TMRD<<16)|(DDR2800_PI_TCCDMW<<8)|(DDR2800_PI_TDQSCK_MAX<<0)); + REG_DDRPHY_WRITE(i,0x28F, (DDR2800_PI_TWTR<<24) | (DDR2800_PI_TRCD<<16)|(DDR2800_PI_TRP<<8) |(DDR2800_PI_TRTP<<0)); + REG_DDRPHY_WRITE(i,0x290, (DDR2800_PI_TRAS_MAX<<8) | (DDR2800_PI_TWR<<0)); + REG_DDRPHY_WRITE(i,0x291, (DDR2800_PI_TMRD<<24) | (DDR2800_PI_TCCDMW<<16) | (DDR2800_PI_TDQSCK_MAX<<8)|(DDR2800_PI_TRAS_MIN<<0)); + REG_DDRPHY_WRITE(i,0x292, (DDR2800_PI_TRCD<<24) | (DDR2800_PI_TRP<<16) | (DDR2800_PI_TRTP<<8)|(DDR2800_PI_TMRW<<0)); + REG_DDRPHY_WRITE(i,0x293, (DDR2800_PI_TWR<<8)|(DDR2800_PI_TWTR<<0)); + REG_DDRPHY_WRITE(i,0x294, (DDR2800_PI_TRAS_MIN<<24)|(DDR2800_PI_TRAS_MAX<<0)); + REG_DDRPHY_WRITE(i,0x295, (DDR2800_PI_TMRW<<24) | (DDR2800_PI_TMRD<<16)|(DDR2800_PI_TCCDMW<<8)|(DDR2800_PI_TDQSCK_MAX<<0)); + + REG_DDRPHY_WRITE(i,0x276, (DDR_MR3 <<24)|(DDR2800_PI_MR2 <<16)|(DDR2800_PI_MR1 <<8)|0x00); + REG_DDRPHY_WRITE(i,0x277, (DDR2800_PI_MR1 <<24)|(PI_MR14<<16)|(PI_MR12<<8)|(PI_MR11<<0)); + REG_DDRPHY_WRITE(i,0x278, (PI_MR12<<24)|(PI_MR11<<16)|(DDR_MR3 <<8)|(DDR2800_PI_MR2 <<0)); + REG_DDRPHY_WRITE(i,0x279, (DDR_MR3 <<24)|(DDR2800_PI_MR2 <<16)|(DDR2800_PI_MR1 <<8)|(PI_MR14<<0)); + REG_DDRPHY_WRITE(i,0x27A, (PI_MR13<<24)|(PI_MR14<<16)|(PI_MR12<<8)|(PI_MR11<<0)); + REG_DDRPHY_WRITE(i,0x27B, (PI_MR11<<24)|(DDR_MR3 <<16)|(DDR2800_PI_MR2 <<8)|(DDR2800_PI_MR1 <<0)); + REG_DDRPHY_WRITE(i,0x27C, (DDR2800_PI_MR2 <<24)|(DDR2800_PI_MR1 <<16)|(PI_MR14<<8)|(PI_MR12<<0)); + REG_DDRPHY_WRITE(i,0x27D, (PI_MR14<<24)|(PI_MR12<<16)|(PI_MR11<<8)|(DDR_MR3 <<0)); + REG_DDRPHY_WRITE(i,0x27E, (PI_MR11<<24)|(DDR_MR3 <<16)|(DDR2800_PI_MR2 <<8)|(DDR2800_PI_MR1 <<0)); + REG_DDRPHY_WRITE(i,0x27F, (DDR2800_PI_MR1 <<24)|(PI_MR13<<16)|(PI_MR14<<8)|(PI_MR12<<0)); + REG_DDRPHY_WRITE(i,0x280, (PI_MR12<<24)|(PI_MR11<<16)|(DDR_MR3 <<8)|(DDR2800_PI_MR2 <<0)); + REG_DDRPHY_WRITE(i,0x281, (DDR_MR3 <<24)|(DDR2800_PI_MR2 <<16)|(DDR2800_PI_MR1 <<8)|(PI_MR14<<0)); + REG_DDRPHY_WRITE(i,0x282, (DDR2800_PI_MR1 <<24)|(PI_MR14<<16)|(PI_MR12<<8)|(PI_MR11<<0)); + REG_DDRPHY_WRITE(i,0x283, (PI_MR12<<24)|(PI_MR11<<16)|(DDR_MR3 <<8)|(DDR2800_PI_MR2 <<0)); + REG_DDRPHY_WRITE(i,0x284, (DDR2800_PI_MR2 <<24)|(DDR2800_PI_MR1 <<16)|(PI_MR13<<8)|(PI_MR14<<0)); + REG_DDRPHY_WRITE(i,0x285, (PI_MR14<<24)|(PI_MR12<<16)|(PI_MR11<<8)|(DDR_MR3 <<0)); + REG_DDRPHY_WRITE(i,0x286, (PI_MR11<<24)|(DDR_MR3 <<16)|(DDR2800_PI_MR2 <<8)|(DDR2800_PI_MR1 <<0)); + REG_DDRPHY_WRITE(i,0x287, (DDR2800_PI_MR2 <<24)|(DDR2800_PI_MR1 <<16)|(PI_MR14<<8)|(PI_MR12<<0)); + REG_DDRPHY_WRITE(i,0x288, (PI_MR14<<24)|(PI_MR12<<16)|(PI_MR11<<8)|(DDR_MR3 <<0)); + REG_DDRPHY_WRITE(i,0x289, 0x00020000 |(PI_MR13<<0)); + + REG_DDRPHY_WRITE(i,0x247, 0x0a0a0a05); //PI_RD_TO_ODTH_F2:RW:24:6:=0x15 PI_RD_TO_ODTH_F1:RW:16:6:=0x15 PI_RD_TO_ODTH_F0:RW:8:6:=0x04 PI_WR_TO_ODTH_F2:RW:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x254, 0x02030303); //PI_TDFI_PHY_WRDATA:RW:24:3:=0x02 PI_TDFI_WRCSLAT_F2:RW:16:7:=0x06 PI_TDFI_WRCSLAT_F1:RW:8:7:=0x06 PI_TDFI_WRCSLAT_F0:RW:0:7:=0x01 + REG_DDRPHY_WRITE(i,0x257, 0x00201701); //PI_TDFI_CALVL_CC_F0:RW:16:10:=0x0018 PI_TDFI_CALVL_EN:RW:8:8:=0x17 PI_CALVL_CS_MAP:RW:0:4:=0x03 + REG_DDRPHY_WRITE(i,0x258, 0x0020000e); //PI_TDFI_CALVL_CC_F1:RW:16:10:=0x0028 PI_TDFI_CALVL_CAPTURE_F0:RW:0:10:=0x000e + REG_DDRPHY_WRITE(i,0x259, 0x0020000e); //PI_TDFI_CALVL_CC_F2:RW:16:10:=0x0028 PI_TDFI_CALVL_CAPTURE_F1:RW:0:10:=0x000e + REG_DDRPHY_WRITE(i,0x25A, 0x0000000e); //PI_TDFI_CALVL_CAPTURE_F2:RW:0:10:=0x0016 + REG_DDRPHY_WRITE(i,0x25F, 0x00C8020A); //PI_TCAENT_F0:RW:16:14:=0x0005 PI_TMRZ_F0:RW:8:5:=0x01 PI_TCACKEH:RW:0:5:=0x0a + REG_DDRPHY_WRITE(i,0x260, 0x0200C802); //PI_TMRZ_F2:RW:24:5:=0x03 PI_TCAENT_F1:RW:8:14:=0x018d PI_TMRZ_F1:RW:0:5:=0x03 + REG_DDRPHY_WRITE(i,0x261, 0x000A00C8); //PI_CA_TRAIN_VREF_EN:RW:24:1:=0x01 PI_TCAEXT:RW:16:5:=0x0a PI_TCAENT_F2:RW:0:14:=0x018d + REG_DDRPHY_WRITE(i,0x262, 0x00C90100); //PI_TVREF_SHORT_F0:RW:16:10:=0x0006 PI_TDFI_CASEL_F0:RW:8:5:=0x01 PI_TDFI_CACSCA_F0:RW:0:5:=0x00 + REG_DDRPHY_WRITE(i,0x263, 0x010000C9); //PI_TDFI_CASEL_F1:RW:24:5:=0x01 PI_TDFI_CACSCA_F1:RW:16:5:=0x00 PI_TVREF_LONG_F0:RW:0:10:=0x0006 + REG_DDRPHY_WRITE(i,0x268, 0x07070705); //PI_TDFI_CALVL_STROBE_F2:RW:24:4:=0x09 PI_TDFI_CALVL_STROBE_F1:RW:16:4:=0x09 PI_TDFI_CALVL_STROBE_F0:RW:8:4:=0x06 PI_TDFI_INIT_COMPLETE_MIN:RW:0:8:=0x05 + REG_DDRPHY_WRITE(i,0x26D, 0x10100100); //PI_TCKEHDQS_F1:RW:24:6:=0x18 PI_TCKEHDQS_F0:RW:16:6:=0x02 PI_REFRESH_BETWEEN_SEGMENT_DISABLE:RW_D:8:1:=0x01 PI_DRAM_CLK_DISABLE_DEASSERT_SEL:RW:0:1:=0x00 + REG_DDRPHY_WRITE(i,0x26E, 0x00010110); //PI_WDQLVL_BST_NUM:RW:16:3:=0x01 PI_WDQLVL_VREF_EN:RW:8:1:=0x01 PI_TCKEHDQS_F2:RW:0:6:=0x18 + REG_DDRPHY_WRITE(i,0x2A8, 0x00185000); //PI_TDFI_CTRLUPD_MAX_F0:RW:8:16:=0x008c PI_TDFI_CTRLUPD_MIN:RD:0:4:=0x00 + REG_DDRPHY_WRITE(i,0x2A9, 0x0000f320); //PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00000578 + REG_DDRPHY_WRITE(i,0x2AA, 0x00001850); //PI_TDFI_CTRLUPD_MAX_F1:RW:0:16:=0x304c + REG_DDRPHY_WRITE(i,0x2AB, 0x0000f320); //PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x0001e2f8 + REG_DDRPHY_WRITE(i,0x2AC, 0x00001850); //PI_TDFI_CTRLUPD_MAX_F2:RW:0:16:=0x304c + REG_DDRPHY_WRITE(i,0x2AD, 0x0000f320); //PI_TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x0001e2f8 + + REG_DDRPHY_WRITE(i,0x44C, 0x00020109); //PHY_WRITE_PATH_LAT_ADD_0:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_0:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_0:RW+:0:10:=0x0109 + REG_DDRPHY_WRITE(i,0x452, 0x070000C0); //PHY_RDDATA_EN_DLY_0:RW+:24:4:=0x0e PHY_IE_MODE_0:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_0:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_0:RW+:0:8:=0xc0 + REG_DDRPHY_WRITE(i,0x453, 0x00100006); //PHY_MASTER_DELAY_START_0:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_0:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_0:RW+:0:4:=0x0c + REG_DDRPHY_WRITE(i,0x454, 0x0C054208); //PHY_WRLVL_DLY_STEP_0:RW+:24:4:=0x0c PHY_RPTR_UPDATE_0:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_0:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_0:RW+:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x4CC, 0x00020109); //PHY_WRITE_PATH_LAT_ADD_1:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_1:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_1:RW+:0:10:=0x0109 + REG_DDRPHY_WRITE(i,0x4D2, 0x070000C0); //PHY_RDDATA_EN_DLY_1:RW+:24:4:=0x0e PHY_IE_MODE_1:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_1:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_1:RW+:0:8:=0xc0 + REG_DDRPHY_WRITE(i,0x4D3, 0x00100006); //PHY_MASTER_DELAY_START_1:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_1:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_1:RW+:0:4:=0x0c + REG_DDRPHY_WRITE(i,0x4D4, 0x0C054208); //PHY_WRLVL_DLY_STEP_1:RW+:24:4:=0x0c PHY_RPTR_UPDATE_1:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_1:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_1:RW+:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x54C, 0x00020109); //PHY_WRITE_PATH_LAT_ADD_2:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_2:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_2:RW+:0:10:=0x0109 + REG_DDRPHY_WRITE(i,0x552, 0x070000C0); //PHY_RDDATA_EN_DLY_2:RW+:24:4:=0x0e PHY_IE_MODE_2:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_2:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_2:RW+:0:8:=0xc0 + REG_DDRPHY_WRITE(i,0x553, 0x00100006); //PHY_MASTER_DELAY_START_2:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_2:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_2:RW+:0:4:=0x0c + REG_DDRPHY_WRITE(i,0x554, 0x0C054208); //PHY_WRLVL_DLY_STEP_2:RW+:24:4:=0x0c PHY_RPTR_UPDATE_2:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_2:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_2:RW+:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x5CC, 0x00020109); //PHY_WRITE_PATH_LAT_ADD_3:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_3:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_3:RW+:0:10:=0x0109 + REG_DDRPHY_WRITE(i,0x5D2, 0x070000C0); //PHY_RDDATA_EN_DLY_3:RW+:24:4:=0x0e PHY_IE_MODE_3:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_3:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_3:RW+:0:8:=0xc0 + REG_DDRPHY_WRITE(i,0x5D3, 0x00100006); //PHY_MASTER_DELAY_START_3:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_3:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_3:RW+:0:4:=0x0c + REG_DDRPHY_WRITE(i,0x5D4, 0x0C054208); //PHY_WRLVL_DLY_STEP_3:RW+:24:4:=0x0c PHY_RPTR_UPDATE_3:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_3:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_3:RW+:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x719, 0x00000303); //PHY_LP_WAKEUP:RW:24:4:=0x00 PHY_LP4_BOOT_LOW_FREQ_SEL:RW:16:1:=0x01 PHY_TCKSRE_WAIT:RW:8:4:=0x05 PHY_PLL_TESTOUT_SEL:RW:0:3:=0x03 + } +} + + +void freq2400_reg_set() +{ + uint32_t i; + + for(i=0;i<4;i++) + { + REG_DDRPHY_WRITE(i,0x22B, (DDR2400_PI_CASLAT_LIN<<24)|(DDR2400_PI_WRLAT<<16)|(DDR2400_PI_CASLAT_LIN<<8)|(DDR2400_PI_WRLAT<<0)); + REG_DDRPHY_WRITE(i,0x22C, 0x00020000|(DDR2400_PI_CASLAT_LIN<<8)|(DDR2400_PI_WRLAT<<0)); + + REG_DDRPHY_WRITE(i,0x252, (DDR2400_PI_RDLAT_ADJ<<16)|(DDR2400_PI_RDLAT_ADJ<<8)|(DDR2400_PI_RDLAT_ADJ<<0)); + REG_DDRPHY_WRITE(i,0x253, (DDR2400_PI_WRLAT_ADJ<<16)|(DDR2400_PI_WRLAT_ADJ<<8)|(DDR2400_PI_WRLAT_ADJ<<0)); + + REG_DDRPHY_WRITE(i,0x28A, (DDR2400_PI_TFC<<16)|(DDR2400_PI_TFC<<0)); + REG_DDRPHY_WRITE(i,0x28B, (DDR2400_PI_TRTP<<24)|(DDR2400_PI_TCCD<<16)|(DDR2400_PI_TFC<<0)); + REG_DDRPHY_WRITE(i,0x28C, (DDR2400_PI_TWR<<24) |(DDR2400_PI_TWTR<<16)|(DDR2400_PI_TRCD<<8)|(DDR2400_PI_TRP<<0)); + REG_DDRPHY_WRITE(i,0x28D, (DDR2400_PI_TRAS_MIN<<24)|(DDR2400_PI_TRAS_MAX<<0)); + REG_DDRPHY_WRITE(i,0x28E, (DDR2400_PI_TMRW<<24) | (DDR2400_PI_TMRD<<16)|(DDR2400_PI_TCCDMW<<8)|(DDR2400_PI_TDQSCK_MAX<<0)); + REG_DDRPHY_WRITE(i,0x28F, (DDR2400_PI_TWTR<<24) | (DDR2400_PI_TRCD<<16)|(DDR2400_PI_TRP<<8) |(DDR2400_PI_TRTP<<0)); + REG_DDRPHY_WRITE(i,0x290, (DDR2400_PI_TRAS_MAX<<8) | (DDR2400_PI_TWR<<0)); + REG_DDRPHY_WRITE(i,0x291, (DDR2400_PI_TMRD<<24) | (DDR2400_PI_TCCDMW<<16) | (DDR2400_PI_TDQSCK_MAX<<8)|(DDR2400_PI_TRAS_MIN<<0)); + REG_DDRPHY_WRITE(i,0x292, (DDR2400_PI_TRCD<<24) | (DDR2400_PI_TRP<<16) | (DDR2400_PI_TRTP<<8)|(DDR2400_PI_TMRW<<0)); + REG_DDRPHY_WRITE(i,0x293, (DDR2400_PI_TWR<<8)|(DDR2400_PI_TWTR<<0)); + REG_DDRPHY_WRITE(i,0x294, (DDR2400_PI_TRAS_MIN<<24)|(DDR2400_PI_TRAS_MAX<<0)); + REG_DDRPHY_WRITE(i,0x295, (DDR2400_PI_TMRW<<24) | (DDR2400_PI_TMRD<<16)|(DDR2400_PI_TCCDMW<<8)|(DDR2400_PI_TDQSCK_MAX<<0)); + + REG_DDRPHY_WRITE(i,0x276, (DDR_MR3 <<24)|(DDR2400_PI_MR2 <<16)|(DDR2400_PI_MR1 <<8)|0x00); + REG_DDRPHY_WRITE(i,0x277, (DDR2400_PI_MR1 <<24)|(PI_MR14<<16)|(PI_MR12<<8)|(PI_MR11<<0)); + REG_DDRPHY_WRITE(i,0x278, (PI_MR12<<24)|(PI_MR11<<16)|(DDR_MR3 <<8)|(DDR2400_PI_MR2 <<0)); + REG_DDRPHY_WRITE(i,0x279, (DDR_MR3 <<24)|(DDR2400_PI_MR2 <<16)|(DDR2400_PI_MR1 <<8)|(PI_MR14<<0)); + REG_DDRPHY_WRITE(i,0x27A, (PI_MR13<<24)|(PI_MR14<<16)|(PI_MR12<<8)|(PI_MR11<<0)); + REG_DDRPHY_WRITE(i,0x27B, (PI_MR11<<24)|(DDR_MR3 <<16)|(DDR2400_PI_MR2 <<8)|(DDR2400_PI_MR1 <<0)); + REG_DDRPHY_WRITE(i,0x27C, (DDR2400_PI_MR2 <<24)|(DDR2400_PI_MR1 <<16)|(PI_MR14<<8)|(PI_MR12<<0)); + REG_DDRPHY_WRITE(i,0x27D, (PI_MR14<<24)|(PI_MR12<<16)|(PI_MR11<<8)|(DDR_MR3 <<0)); + REG_DDRPHY_WRITE(i,0x27E, (PI_MR11<<24)|(DDR_MR3 <<16)|(DDR2400_PI_MR2 <<8)|(DDR2400_PI_MR1 <<0)); + REG_DDRPHY_WRITE(i,0x27F, (DDR2400_PI_MR1 <<24)|(PI_MR13<<16)|(PI_MR14<<8)|(PI_MR12<<0)); + REG_DDRPHY_WRITE(i,0x280, (PI_MR12<<24)|(PI_MR11<<16)|(DDR_MR3 <<8)|(DDR2400_PI_MR2 <<0)); + REG_DDRPHY_WRITE(i,0x281, (DDR_MR3 <<24)|(DDR2400_PI_MR2 <<16)|(DDR2400_PI_MR1 <<8)|(PI_MR14<<0)); + REG_DDRPHY_WRITE(i,0x282, (DDR2400_PI_MR1 <<24)|(PI_MR14<<16)|(PI_MR12<<8)|(PI_MR11<<0)); + REG_DDRPHY_WRITE(i,0x283, (PI_MR12<<24)|(PI_MR11<<16)|(DDR_MR3 <<8)|(DDR2400_PI_MR2 <<0)); + REG_DDRPHY_WRITE(i,0x284, (DDR2400_PI_MR2 <<24)|(DDR2400_PI_MR1 <<16)|(PI_MR13<<8)|(PI_MR14<<0)); + REG_DDRPHY_WRITE(i,0x285, (PI_MR14<<24)|(PI_MR12<<16)|(PI_MR11<<8)|(DDR_MR3 <<0)); + REG_DDRPHY_WRITE(i,0x286, (PI_MR11<<24)|(DDR_MR3 <<16)|(DDR2400_PI_MR2 <<8)|(DDR2400_PI_MR1 <<0)); + REG_DDRPHY_WRITE(i,0x287, (DDR2400_PI_MR2 <<24)|(DDR2400_PI_MR1 <<16)|(PI_MR14<<8)|(PI_MR12<<0)); + REG_DDRPHY_WRITE(i,0x288, (PI_MR14<<24)|(PI_MR12<<16)|(PI_MR11<<8)|(DDR_MR3 <<0)); + REG_DDRPHY_WRITE(i,0x289, 0x00020000 |(PI_MR13<<0)); + + REG_DDRPHY_WRITE(i,0x247, 0x0a0a0a05); //PI_RD_TO_ODTH_F2:RW:24:6:=0x15 PI_RD_TO_ODTH_F1:RW:16:6:=0x15 PI_RD_TO_ODTH_F0:RW:8:6:=0x04 PI_WR_TO_ODTH_F2:RW:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x254, 0x02030303); //PI_TDFI_PHY_WRDATA:RW:24:3:=0x02 PI_TDFI_WRCSLAT_F2:RW:16:7:=0x06 PI_TDFI_WRCSLAT_F1:RW:8:7:=0x06 PI_TDFI_WRCSLAT_F0:RW:0:7:=0x01 + REG_DDRPHY_WRITE(i,0x257, 0x00201701); //PI_TDFI_CALVL_CC_F0:RW:16:10:=0x0018 PI_TDFI_CALVL_EN:RW:8:8:=0x17 PI_CALVL_CS_MAP:RW:0:4:=0x03 + REG_DDRPHY_WRITE(i,0x258, 0x0020000e); //PI_TDFI_CALVL_CC_F1:RW:16:10:=0x0028 PI_TDFI_CALVL_CAPTURE_F0:RW:0:10:=0x000e + REG_DDRPHY_WRITE(i,0x259, 0x0020000e); //PI_TDFI_CALVL_CC_F2:RW:16:10:=0x0028 PI_TDFI_CALVL_CAPTURE_F1:RW:0:10:=0x000e + REG_DDRPHY_WRITE(i,0x25A, 0x0000000e); //PI_TDFI_CALVL_CAPTURE_F2:RW:0:10:=0x0016 + REG_DDRPHY_WRITE(i,0x25F, 0x00C8020A); //PI_TCAENT_F0:RW:16:14:=0x0005 PI_TMRZ_F0:RW:8:5:=0x01 PI_TCACKEH:RW:0:5:=0x0a + REG_DDRPHY_WRITE(i,0x260, 0x0200C802); //PI_TMRZ_F2:RW:24:5:=0x03 PI_TCAENT_F1:RW:8:14:=0x018d PI_TMRZ_F1:RW:0:5:=0x03 + REG_DDRPHY_WRITE(i,0x261, 0x000A00C8); //PI_CA_TRAIN_VREF_EN:RW:24:1:=0x01 PI_TCAEXT:RW:16:5:=0x0a PI_TCAENT_F2:RW:0:14:=0x018d + REG_DDRPHY_WRITE(i,0x262, 0x00C90100); //PI_TVREF_SHORT_F0:RW:16:10:=0x0006 PI_TDFI_CASEL_F0:RW:8:5:=0x01 PI_TDFI_CACSCA_F0:RW:0:5:=0x00 + REG_DDRPHY_WRITE(i,0x263, 0x010000C9); //PI_TDFI_CASEL_F1:RW:24:5:=0x01 PI_TDFI_CACSCA_F1:RW:16:5:=0x00 PI_TVREF_LONG_F0:RW:0:10:=0x0006 + REG_DDRPHY_WRITE(i,0x268, 0x07070705); //PI_TDFI_CALVL_STROBE_F2:RW:24:4:=0x09 PI_TDFI_CALVL_STROBE_F1:RW:16:4:=0x09 PI_TDFI_CALVL_STROBE_F0:RW:8:4:=0x06 PI_TDFI_INIT_COMPLETE_MIN:RW:0:8:=0x05 + REG_DDRPHY_WRITE(i,0x26D, 0x10100100); //PI_TCKEHDQS_F1:RW:24:6:=0x18 PI_TCKEHDQS_F0:RW:16:6:=0x02 PI_REFRESH_BETWEEN_SEGMENT_DISABLE:RW_D:8:1:=0x01 PI_DRAM_CLK_DISABLE_DEASSERT_SEL:RW:0:1:=0x00 + REG_DDRPHY_WRITE(i,0x26E, 0x00010110); //PI_WDQLVL_BST_NUM:RW:16:3:=0x01 PI_WDQLVL_VREF_EN:RW:8:1:=0x01 PI_TCKEHDQS_F2:RW:0:6:=0x18 + REG_DDRPHY_WRITE(i,0x2A8, 0x00185000); //PI_TDFI_CTRLUPD_MAX_F0:RW:8:16:=0x008c PI_TDFI_CTRLUPD_MIN:RD:0:4:=0x00 + REG_DDRPHY_WRITE(i,0x2A9, 0x0000f320); //PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00000578 + REG_DDRPHY_WRITE(i,0x2AA, 0x00001850); //PI_TDFI_CTRLUPD_MAX_F1:RW:0:16:=0x304c + REG_DDRPHY_WRITE(i,0x2AB, 0x0000f320); //PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x0001e2f8 + REG_DDRPHY_WRITE(i,0x2AC, 0x00001850); //PI_TDFI_CTRLUPD_MAX_F2:RW:0:16:=0x304c + REG_DDRPHY_WRITE(i,0x2AD, 0x0000f320); //PI_TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x0001e2f8 + + REG_DDRPHY_WRITE(i,0x44C, 0x00020109); //PHY_WRITE_PATH_LAT_ADD_0:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_0:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_0:RW+:0:10:=0x0109 + REG_DDRPHY_WRITE(i,0x452, 0x070000C0); //PHY_RDDATA_EN_DLY_0:RW+:24:4:=0x0e PHY_IE_MODE_0:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_0:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_0:RW+:0:8:=0xc0 + REG_DDRPHY_WRITE(i,0x453, 0x00100006); //PHY_MASTER_DELAY_START_0:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_0:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_0:RW+:0:4:=0x0c + REG_DDRPHY_WRITE(i,0x454, 0x0C054208); //PHY_WRLVL_DLY_STEP_0:RW+:24:4:=0x0c PHY_RPTR_UPDATE_0:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_0:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_0:RW+:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x4CC, 0x00020109); //PHY_WRITE_PATH_LAT_ADD_1:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_1:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_1:RW+:0:10:=0x0109 + REG_DDRPHY_WRITE(i,0x4D2, 0x070000C0); //PHY_RDDATA_EN_DLY_1:RW+:24:4:=0x0e PHY_IE_MODE_1:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_1:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_1:RW+:0:8:=0xc0 + REG_DDRPHY_WRITE(i,0x4D3, 0x00100006); //PHY_MASTER_DELAY_START_1:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_1:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_1:RW+:0:4:=0x0c + REG_DDRPHY_WRITE(i,0x4D4, 0x0C054208); //PHY_WRLVL_DLY_STEP_1:RW+:24:4:=0x0c PHY_RPTR_UPDATE_1:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_1:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_1:RW+:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x54C, 0x00020109); //PHY_WRITE_PATH_LAT_ADD_2:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_2:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_2:RW+:0:10:=0x0109 + REG_DDRPHY_WRITE(i,0x552, 0x070000C0); //PHY_RDDATA_EN_DLY_2:RW+:24:4:=0x0e PHY_IE_MODE_2:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_2:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_2:RW+:0:8:=0xc0 + REG_DDRPHY_WRITE(i,0x553, 0x00100006); //PHY_MASTER_DELAY_START_2:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_2:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_2:RW+:0:4:=0x0c + REG_DDRPHY_WRITE(i,0x554, 0x0C054208); //PHY_WRLVL_DLY_STEP_2:RW+:24:4:=0x0c PHY_RPTR_UPDATE_2:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_2:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_2:RW+:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x5CC, 0x00020109); //PHY_WRITE_PATH_LAT_ADD_3:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_3:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_3:RW+:0:10:=0x0109 + REG_DDRPHY_WRITE(i,0x5D2, 0x070000C0); //PHY_RDDATA_EN_DLY_3:RW+:24:4:=0x0e PHY_IE_MODE_3:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_3:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_3:RW+:0:8:=0xc0 + REG_DDRPHY_WRITE(i,0x5D3, 0x00100006); //PHY_MASTER_DELAY_START_3:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_3:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_3:RW+:0:4:=0x0c + REG_DDRPHY_WRITE(i,0x5D4, 0x0C054208); //PHY_WRLVL_DLY_STEP_3:RW+:24:4:=0x0c PHY_RPTR_UPDATE_3:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_3:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_3:RW+:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x719, 0x00000303); //PHY_LP_WAKEUP:RW:24:4:=0x00 PHY_LP4_BOOT_LOW_FREQ_SEL:RW:16:1:=0x01 PHY_TCKSRE_WAIT:RW:8:4:=0x05 PHY_PLL_TESTOUT_SEL:RW:0:3:=0x03 + } +} +#endif + +static void freq1600_reg_set() +{ + uint32_t i; + + for(i=0;i<4;i++) + { + REG_DDRPHY_WRITE(i,0x22B, (DDR1600_PI_CASLAT_LIN<<24)|(DDR1600_PI_WRLAT<<16)|(DDR1600_PI_CASLAT_LIN<<8)|(DDR1600_PI_WRLAT<<0)); + REG_DDRPHY_WRITE(i,0x22C, 0x00020000|(DDR1600_PI_CASLAT_LIN<<8)|(DDR1600_PI_WRLAT<<0)); + + REG_DDRPHY_WRITE(i,0x252, (DDR1600_PI_RDLAT_ADJ<<16)|(DDR1600_PI_RDLAT_ADJ<<8)|(DDR1600_PI_RDLAT_ADJ<<0)); + REG_DDRPHY_WRITE(i,0x253, (DDR1600_PI_WRLAT_ADJ<<16)|(DDR1600_PI_WRLAT_ADJ<<8)|(DDR1600_PI_WRLAT_ADJ<<0)); + + REG_DDRPHY_WRITE(i,0x28A, (DDR1600_PI_TFC<<16)|(DDR1600_PI_TFC<<0)); + REG_DDRPHY_WRITE(i,0x28B, (DDR1600_PI_TRTP<<24)|(DDR1600_PI_TCCD<<16)|(DDR1600_PI_TFC<<0)); + REG_DDRPHY_WRITE(i,0x28C, (DDR1600_PI_TWR<<24) |(DDR1600_PI_TWTR<<16)|(DDR1600_PI_TRCD<<8)|(DDR1600_PI_TRP<<0)); + REG_DDRPHY_WRITE(i,0x28D, (DDR1600_PI_TRAS_MIN<<24)|(DDR1600_PI_TRAS_MAX<<0)); + REG_DDRPHY_WRITE(i,0x28E, (DDR1600_PI_TMRW<<24) | (DDR1600_PI_TMRD<<16)|(DDR1600_PI_TCCDMW<<8)|(DDR1600_PI_TDQSCK_MAX<<0)); + REG_DDRPHY_WRITE(i,0x28F, (DDR1600_PI_TWTR<<24) | (DDR1600_PI_TRCD<<16)|(DDR1600_PI_TRP<<8) |(DDR1600_PI_TRTP<<0)); + REG_DDRPHY_WRITE(i,0x290, (DDR1600_PI_TRAS_MAX<<8) | (DDR1600_PI_TWR<<0)); + REG_DDRPHY_WRITE(i,0x291, (DDR1600_PI_TMRD<<24) | (DDR1600_PI_TCCDMW<<16) | (DDR1600_PI_TDQSCK_MAX<<8)|(DDR1600_PI_TRAS_MIN<<0)); + REG_DDRPHY_WRITE(i,0x292, (DDR1600_PI_TRCD<<24) | (DDR1600_PI_TRP<<16) | (DDR1600_PI_TRTP<<8)|(DDR1600_PI_TMRW<<0)); + REG_DDRPHY_WRITE(i,0x293, (DDR1600_PI_TWR<<8)|(DDR1600_PI_TWTR<<0)); + REG_DDRPHY_WRITE(i,0x294, (DDR1600_PI_TRAS_MIN<<24)|(DDR1600_PI_TRAS_MAX<<0)); + REG_DDRPHY_WRITE(i,0x295, (DDR1600_PI_TMRW<<24) | (DDR1600_PI_TMRD<<16)|(DDR1600_PI_TCCDMW<<8)|(DDR1600_PI_TDQSCK_MAX<<0)); + + REG_DDRPHY_WRITE(i,0x276, (PI_MR3 <<24)|(DDR1600_PI_MR2 <<16)|(DDR1600_PI_MR1 <<8)|0x00); + REG_DDRPHY_WRITE(i,0x277, (DDR1600_PI_MR1 <<24)|(PI_MR14<<16)|(PI_MR12<<8)|(PI_MR11<<0)); + REG_DDRPHY_WRITE(i,0x278, (PI_MR12<<24)|(PI_MR11<<16)|(PI_MR3 <<8)|(DDR1600_PI_MR2 <<0)); + REG_DDRPHY_WRITE(i,0x279, (PI_MR3 <<24)|(DDR1600_PI_MR2 <<16)|(DDR1600_PI_MR1 <<8)|(PI_MR14<<0)); + REG_DDRPHY_WRITE(i,0x27A, (PI_MR13<<24)|(PI_MR14<<16)|(PI_MR12<<8)|(PI_MR11<<0)); + REG_DDRPHY_WRITE(i,0x27B, (PI_MR11<<24)|(PI_MR3 <<16)|(DDR1600_PI_MR2 <<8)|(DDR1600_PI_MR1 <<0)); + REG_DDRPHY_WRITE(i,0x27C, (DDR1600_PI_MR2 <<24)|(DDR1600_PI_MR1 <<16)|(PI_MR14<<8)|(PI_MR12<<0)); + REG_DDRPHY_WRITE(i,0x27D, (PI_MR14<<24)|(PI_MR12<<16)|(PI_MR11<<8)|(PI_MR3 <<0)); + REG_DDRPHY_WRITE(i,0x27E, (PI_MR11<<24)|(PI_MR3 <<16)|(DDR1600_PI_MR2 <<8)|(DDR1600_PI_MR1 <<0)); + REG_DDRPHY_WRITE(i,0x27F, (DDR1600_PI_MR1 <<24)|(PI_MR13<<16)|(PI_MR14<<8)|(PI_MR12<<0)); + REG_DDRPHY_WRITE(i,0x280, (PI_MR12<<24)|(PI_MR11<<16)|(PI_MR3 <<8)|(DDR1600_PI_MR2 <<0)); + REG_DDRPHY_WRITE(i,0x281, (PI_MR3 <<24)|(DDR1600_PI_MR2 <<16)|(DDR1600_PI_MR1 <<8)|(PI_MR14<<0)); + REG_DDRPHY_WRITE(i,0x282, (DDR1600_PI_MR1 <<24)|(PI_MR14<<16)|(PI_MR12<<8)|(PI_MR11<<0)); + REG_DDRPHY_WRITE(i,0x283, (PI_MR12<<24)|(PI_MR11<<16)|(PI_MR3 <<8)|(DDR1600_PI_MR2 <<0)); + REG_DDRPHY_WRITE(i,0x284, (DDR1600_PI_MR2 <<24)|(DDR1600_PI_MR1 <<16)|(PI_MR13<<8)|(PI_MR14<<0)); + REG_DDRPHY_WRITE(i,0x285, (PI_MR14<<24)|(PI_MR12<<16)|(PI_MR11<<8)|(PI_MR3 <<0)); + REG_DDRPHY_WRITE(i,0x286, (PI_MR11<<24)|(PI_MR3 <<16)|(DDR1600_PI_MR2 <<8)|(DDR1600_PI_MR1 <<0)); + REG_DDRPHY_WRITE(i,0x287, (DDR1600_PI_MR2 <<24)|(DDR1600_PI_MR1 <<16)|(PI_MR14<<8)|(PI_MR12<<0)); + REG_DDRPHY_WRITE(i,0x288, (PI_MR14<<24)|(PI_MR12<<16)|(PI_MR11<<8)|(PI_MR3 <<0)); + REG_DDRPHY_WRITE(i,0x289, 0x00020000 |(PI_MR13<<0)); + + REG_DDRPHY_WRITE(i,0x247, 0x0a0a0a05); //PI_RD_TO_ODTH_F2:RW:24:6:=0x15 PI_RD_TO_ODTH_F1:RW:16:6:=0x15 PI_RD_TO_ODTH_F0:RW:8:6:=0x04 PI_WR_TO_ODTH_F2:RW:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x254, 0x02030303); //PI_TDFI_PHY_WRDATA:RW:24:3:=0x02 PI_TDFI_WRCSLAT_F2:RW:16:7:=0x06 PI_TDFI_WRCSLAT_F1:RW:8:7:=0x06 PI_TDFI_WRCSLAT_F0:RW:0:7:=0x01 + REG_DDRPHY_WRITE(i,0x257, 0x00201701); //PI_TDFI_CALVL_CC_F0:RW:16:10:=0x0018 PI_TDFI_CALVL_EN:RW:8:8:=0x17 PI_CALVL_CS_MAP:RW:0:4:=0x03 + REG_DDRPHY_WRITE(i,0x258, 0x0020000e); //PI_TDFI_CALVL_CC_F1:RW:16:10:=0x0028 PI_TDFI_CALVL_CAPTURE_F0:RW:0:10:=0x000e + REG_DDRPHY_WRITE(i,0x259, 0x0020000e); //PI_TDFI_CALVL_CC_F2:RW:16:10:=0x0028 PI_TDFI_CALVL_CAPTURE_F1:RW:0:10:=0x000e + REG_DDRPHY_WRITE(i,0x25A, 0x0000000e); //PI_TDFI_CALVL_CAPTURE_F2:RW:0:10:=0x0016 + REG_DDRPHY_WRITE(i,0x25F, 0x00C8020A); //PI_TCAENT_F0:RW:16:14:=0x0005 PI_TMRZ_F0:RW:8:5:=0x01 PI_TCACKEH:RW:0:5:=0x0a + REG_DDRPHY_WRITE(i,0x260, 0x0200C802); //PI_TMRZ_F2:RW:24:5:=0x03 PI_TCAENT_F1:RW:8:14:=0x018d PI_TMRZ_F1:RW:0:5:=0x03 + REG_DDRPHY_WRITE(i,0x261, 0x000A00C8); //PI_CA_TRAIN_VREF_EN:RW:24:1:=0x01 PI_TCAEXT:RW:16:5:=0x0a PI_TCAENT_F2:RW:0:14:=0x018d + REG_DDRPHY_WRITE(i,0x262, 0x00C90100); //PI_TVREF_SHORT_F0:RW:16:10:=0x0006 PI_TDFI_CASEL_F0:RW:8:5:=0x01 PI_TDFI_CACSCA_F0:RW:0:5:=0x00 + REG_DDRPHY_WRITE(i,0x263, 0x010000C9); //PI_TDFI_CASEL_F1:RW:24:5:=0x01 PI_TDFI_CACSCA_F1:RW:16:5:=0x00 PI_TVREF_LONG_F0:RW:0:10:=0x0006 + REG_DDRPHY_WRITE(i,0x268, 0x07070705); //PI_TDFI_CALVL_STROBE_F2:RW:24:4:=0x09 PI_TDFI_CALVL_STROBE_F1:RW:16:4:=0x09 PI_TDFI_CALVL_STROBE_F0:RW:8:4:=0x06 PI_TDFI_INIT_COMPLETE_MIN:RW:0:8:=0x05 + REG_DDRPHY_WRITE(i,0x26D, 0x10100100); //PI_TCKEHDQS_F1:RW:24:6:=0x18 PI_TCKEHDQS_F0:RW:16:6:=0x02 PI_REFRESH_BETWEEN_SEGMENT_DISABLE:RW_D:8:1:=0x01 PI_DRAM_CLK_DISABLE_DEASSERT_SEL:RW:0:1:=0x00 + REG_DDRPHY_WRITE(i,0x26E, 0x00010110); //PI_WDQLVL_BST_NUM:RW:16:3:=0x01 PI_WDQLVL_VREF_EN:RW:8:1:=0x01 PI_TCKEHDQS_F2:RW:0:6:=0x18 + REG_DDRPHY_WRITE(i,0x2A8, 0x00185000); //PI_TDFI_CTRLUPD_MAX_F0:RW:8:16:=0x008c PI_TDFI_CTRLUPD_MIN:RD:0:4:=0x00 + REG_DDRPHY_WRITE(i,0x2A9, 0x0000f320); //PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00000578 + REG_DDRPHY_WRITE(i,0x2AA, 0x00001850); //PI_TDFI_CTRLUPD_MAX_F1:RW:0:16:=0x304c + REG_DDRPHY_WRITE(i,0x2AB, 0x0000f320); //PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x0001e2f8 + REG_DDRPHY_WRITE(i,0x2AC, 0x00001850); //PI_TDFI_CTRLUPD_MAX_F2:RW:0:16:=0x304c + REG_DDRPHY_WRITE(i,0x2AD, 0x0000f320); //PI_TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x0001e2f8 + + REG_DDRPHY_WRITE(i,0x44C, 0x00020109); //PHY_WRITE_PATH_LAT_ADD_0:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_0:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_0:RW+:0:10:=0x0109 + REG_DDRPHY_WRITE(i,0x452, 0x070000C0); //PHY_RDDATA_EN_DLY_0:RW+:24:4:=0x0e PHY_IE_MODE_0:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_0:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_0:RW+:0:8:=0xc0 + REG_DDRPHY_WRITE(i,0x453, 0x00100006); //PHY_MASTER_DELAY_START_0:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_0:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_0:RW+:0:4:=0x0c + REG_DDRPHY_WRITE(i,0x454, 0x0C054208); //PHY_WRLVL_DLY_STEP_0:RW+:24:4:=0x0c PHY_RPTR_UPDATE_0:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_0:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_0:RW+:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x4CC, 0x00020109); //PHY_WRITE_PATH_LAT_ADD_1:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_1:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_1:RW+:0:10:=0x0109 + REG_DDRPHY_WRITE(i,0x4D2, 0x070000C0); //PHY_RDDATA_EN_DLY_1:RW+:24:4:=0x0e PHY_IE_MODE_1:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_1:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_1:RW+:0:8:=0xc0 + REG_DDRPHY_WRITE(i,0x4D3, 0x00100006); //PHY_MASTER_DELAY_START_1:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_1:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_1:RW+:0:4:=0x0c + REG_DDRPHY_WRITE(i,0x4D4, 0x0C054208); //PHY_WRLVL_DLY_STEP_1:RW+:24:4:=0x0c PHY_RPTR_UPDATE_1:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_1:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_1:RW+:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x54C, 0x00020109); //PHY_WRITE_PATH_LAT_ADD_2:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_2:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_2:RW+:0:10:=0x0109 + REG_DDRPHY_WRITE(i,0x552, 0x070000C0); //PHY_RDDATA_EN_DLY_2:RW+:24:4:=0x0e PHY_IE_MODE_2:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_2:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_2:RW+:0:8:=0xc0 + REG_DDRPHY_WRITE(i,0x553, 0x00100006); //PHY_MASTER_DELAY_START_2:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_2:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_2:RW+:0:4:=0x0c + REG_DDRPHY_WRITE(i,0x554, 0x0C054208); //PHY_WRLVL_DLY_STEP_2:RW+:24:4:=0x0c PHY_RPTR_UPDATE_2:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_2:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_2:RW+:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x5CC, 0x00020109); //PHY_WRITE_PATH_LAT_ADD_3:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_3:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_3:RW+:0:10:=0x0109 + REG_DDRPHY_WRITE(i,0x5D2, 0x070000C0); //PHY_RDDATA_EN_DLY_3:RW+:24:4:=0x0e PHY_IE_MODE_3:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_3:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_3:RW+:0:8:=0xc0 + REG_DDRPHY_WRITE(i,0x5D3, 0x00100006); //PHY_MASTER_DELAY_START_3:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_3:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_3:RW+:0:4:=0x0c + REG_DDRPHY_WRITE(i,0x5D4, 0x0C054208); //PHY_WRLVL_DLY_STEP_3:RW+:24:4:=0x0c PHY_RPTR_UPDATE_3:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_3:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_3:RW+:0:6:=0x08 + REG_DDRPHY_WRITE(i,0x719, 0x00000303); //PHY_LP_WAKEUP:RW:24:4:=0x00 PHY_LP4_BOOT_LOW_FREQ_SEL:RW:16:1:=0x01 PHY_TCKSRE_WAIT:RW:8:4:=0x05 PHY_PLL_TESTOUT_SEL:RW:0:3:=0x03 + } +} + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/H3/ES10/boot_init_dram_h3_es10.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/H3/ES10/boot_init_dram_h3_es10.h new file mode 100644 index 0000000..d03b513 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/H3/ES10/boot_init_dram_h3_es10.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BOOT_INIT_DRAM_H3_ES10_ +#define __BOOT_INIT_DRAM_H3_ES10_ + +extern void InitDram_h3_es10(void); + +#endif /* __BOOT_INIT_DRAM_H3_ES10_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/H3/ES10/init_dram_tbl_h3_es10.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/H3/ES10/init_dram_tbl_h3_es10.h new file mode 100644 index 0000000..b6edfb5 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/H3/ES10/init_dram_tbl_h3_es10.h @@ -0,0 +1,1383 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __INIT_DRAM_TBL_H3_ES10_ +#define __INIT_DRAM_TBL_H3_ES10_ + +#define PI_WRLAT 0x0e //F2=0x0e,F1=0x0e,F0=4 +#define PI_WRLAT_ADJ 0x0c + +#define PI_TFC 0x018D +#define PI_TRTP 0x0c +#define PI_TCCD 0x08 //common for all F +#define PI_TWR 0x1f +#define PI_TWTR 0x12 +#define PI_TRCD 0x1d +#define PI_TRP 0x22 +#define PI_TRAS_MIN 0x43 +#define PI_TRAS_MAX 0x01b267 +#define PI_TMRW 0x0a +#define PI_TMRD 0x17 +#define PI_TCCDMW 0x20 +#define PI_TDQSCK_MAX 0x6 +////////////////////////////////////////////////////////////////////////////// +#define PI_MR1 0xd4 //MRW DeviceFeature1(Post=1.5tck nWR=30 RDpre=static WRPre=2tCK BL=16//OK +#define PI_MR2 0x2e //MRW DeviceFeature2(0,0SetA,101=WL14,110=RL32(nRTP14))//NG +#define PI_MR3 0x31 +#define PI_MR11 0x36 +#define PI_MR12 0x11 +#define PI_MR14 0x11 +#define PI_MR13 0x00 + +/*RDLAT*/ +#define PI_RDLAT_ADJ (0x12) //try 0e+4 OK + +/*CASLAT*/ +#define PI_CASLAT_LIN 0x50 //try OK + + +#define DDR_PHY_NUM 827 +#define DDR_PI_NUM 181 +#define DDR_PHY_PVT_OVERWRITE_NUM 8 + + +#define DDR_PHY_DRIVE_TERM_OVERWRITE_NUM (8+1+2+7+3+1) +static const uint32_t DDR_PHY_DDR_PHY_DRIVE_TERM_OVERWITE_1600[DDR_PHY_DRIVE_TERM_OVERWRITE_NUM][2] = +{ + { 0x00000404, 0x03006E02}, // PHY_DQS_TSEL_ENABLE_0:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_0:RW:0:24:=0x665555 + { 0x00000405, 0x02006E02}, // PHY_TWO_CYC_PREAMBLE_0:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_0:RW:0:24:=0x665555 + { 0x00000484, 0x03006E02}, // PHY_DQS_TSEL_ENABLE_1:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_1:RW:0:24:=0x665555 + { 0x00000485, 0x02006E02}, // PHY_TWO_CYC_PREAMBLE_1:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_1:RW:0:24:=0x665555 + { 0x00000504, 0x03006E02}, // PHY_DQS_TSEL_ENABLE_2:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_2:RW:0:24:=0x665555 + { 0x00000505, 0x02006E02}, // PHY_TWO_CYC_PREAMBLE_2:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_2:RW:0:24:=0x665555 + { 0x00000584, 0x03006E02}, // PHY_DQS_TSEL_ENABLE_3:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_3:RW:0:24:=0x665555 + { 0x00000585, 0x02006E02}, // PHY_TWO_CYC_PREAMBLE_3:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_3:RW:0:24:=0x665555 + + //CKE 27F6E(LVSTL) -> 03fee(CMOS40orm) + { 0x00000723, 0x00003fee}, // PHY_PAD_CKE_DRIVE:RW+:0:18:=0x000411 + //RST 27F6E(LVSTL) -> 03fee(CMOS40orm) + { 0x00000725, 0x00003fee}, // PHY_PAD_RST_DRIVE:RW+:0:18:=0x000411 + { 0x00000726, 0x0001154f}, // PHY_PAD_RST_TERM:RW+:0:18:=0x004410 + + // TERM 10F68(PVTR=10,PVTN=3D,PVTP=28) -> 1154f(PVTR=11,PVTN=15,PVTP=0f + { 0x0000071E, 0x0003154f}, // PHY_PAD_FDBK_TERM:RW+:0:18:=0x004410 // TSEL = ON + { 0x0000071F, 0x0001154f}, // PHY_PAD_DATA_TERM:RW+:0:17:=0x004410 + { 0x00000720, 0x0001154f}, // PHY_PAD_DQS_TERM:RW+:0:17:=0x004410 + { 0x00000721, 0x0001154f}, // PHY_PAD_ADDR_TERM:RW+:0:18:=0x004410 + { 0x00000722, 0x0001154f}, // PHY_PAD_CLK_TERM:RW+:0:18:=0x004410 + { 0x00000724, 0x0001154f}, // PHY_PAD_CKE_TERM:RW+:0:18:=0x004410 + { 0x00000728, 0x0001154f}, // PHY_PAD_CS_TERM:RW+:0:18:=0x004410 + + // VREF + { 0x0000070F, 0x000F1900}, // PHY_PAD_VREF_CTRL_DQ_0:RW+:8:14:=0x0100 PHY_LOW_FREQ_SEL:RW+:0:1:=0x00 +// { 0x0000070F, 0x000F1901}, // PHY_PAD_VREF_CTRL_DQ_0:RW+:8:14:=0x0100 PHY_LOW_FREQ_SEL:RW+:0:1:=0x01 + { 0x00000710, 0x0F190F19}, // PHY_PAD_VREF_CTRL_DQ_2:RW+:16:14:=0x0100 PHY_PAD_VREF_CTRL_DQ_1:RW+:0:14:=0x0100 + { 0x00000711, 0x0F190F19}, // PHY_PAD_VREF_CTRL_AC:RW+:16:14:=0x0100 PHY_PAD_VREF_CTRL_DQ_3:RW+:0:14:=0x0100 + // PAD CAL? + { 0x0000072C, 0x75000000}, // PHY_CAL_MODE_0:RW:24:8:=0x64 PHY_TST_CLK_PAD_CTRL2:RW:0:23:=0x000000 +}; + + +// 2015/07/20 suresh regconfig +static const uint32_t DDR_PHY_suresh[827][2] = +{ + { 0x00000400, 0x000004F0}, // PHY_SW_WRDQ0_SHIFT_0:RW:24:5:=0x00 PHY_CLK_BYPASS_OVERRIDE_0:RW:16:1:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_0:RW:0:11:=0x04f0 + { 0x00000401, 0x00000000}, // PHY_SW_WRDQ4_SHIFT_0:RW:24:5:=0x00 PHY_SW_WRDQ3_SHIFT_0:RW:16:5:=0x00 PHY_SW_WRDQ2_SHIFT_0:RW:8:5:=0x00 PHY_SW_WRDQ1_SHIFT_0:RW:0:5:=0x00 + { 0x00000402, 0x00000000}, // PHY_SW_WRDM_SHIFT_0:RW:24:5:=0x00 PHY_SW_WRDQ7_SHIFT_0:RW:16:5:=0x00 PHY_SW_WRDQ6_SHIFT_0:RW:8:5:=0x00 PHY_SW_WRDQ5_SHIFT_0:RW:0:5:=0x00 +// { 0x00000403, 0x00000100}, // PHY_DQ_TSEL_ENABLE_0:RW:8:3:=0x01 PHY_SW_WRDQS_SHIFT_0:RW:0:4:=0x00 + { 0x00000403, 0x00000300}, // PHY_DQ_TSEL_ENABLE_0:RW:8:3:=0x01 PHY_SW_WRDQS_SHIFT_0:RW:0:4:=0x00 +// { 0x00000404, 0x01CC6E0C}, // PHY_DQS_TSEL_ENABLE_0:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_0:RW:0:24:=0x665555 + { 0x00000404, 0x030e6E0E}, // PHY_DQS_TSEL_ENABLE_0:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_0:RW:0:24:=0x665555 +// { 0x00000404, 0x036e6E0E}, // PHY_DQS_TSEL_ENABLE_0:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_0:RW:0:24:=0x665555 +// { 0x00000405, 0x02CC6E0C}, // PHY_TWO_CYC_PREAMBLE_0:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_0:RW:0:24:=0x665555 + { 0x00000405, 0x020e6E0E}, // PHY_TWO_CYC_PREAMBLE_0:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_0:RW:0:24:=0x665555 +// { 0x00000405, 0x026e6E0E}, // PHY_TWO_CYC_PREAMBLE_0:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_0:RW:0:24:=0x665555 + { 0x00000406, 0x00010F00}, // PHY_PER_CS_TRAINING_INDEX_0:RW:24:1:=0x00 PHY_PER_CS_TRAINING_MULTICAST_EN_0:RW_D:16:1:=0x01 PHY_PER_RANK_CS_MAP_0:RW:8:2:=0x0f PHY_DBI_MODE_0:RW:0:1:=0x00 + { 0x00000407, 0x04000100}, // PHY_LP4_BOOT_RPTR_UPDATE_0:RW:24:4:=0x04 PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0:RW:16:4:=0x00 PHY_LP4_BOOT_RDDATA_EN_DLY_0:RW:8:4:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0:RW:0:2:=0x00 + { 0x00000408, 0x00000133}, // PHY_LPBK_CONTROL_0:RW:24:7:=0x00 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0:RW:16:4:=0x00 PHY_LP4_BOOT_RDDQS_GATE_SLAVE_DELAY_0:RW:0:10:=0x0133 + { 0x00000409, 0x000700C0}, // SC_PHY_SNAP_OBS_REGS_0:WR:24:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_0:RW:16:4:=0x07 PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0:RW:0:10:=0x00c0 + { 0x0000040A, 0x00CC0201}, // PHY_GATE_SMPL1_SLAVE_DELAY_0:RW:16:9:=0x00cc PHY_LPDDR_TYPE_0:RW:8:2:=0x02 PHY_LPDDR_0:RW:0:1:=0x01 + { 0x0000040B, 0x00030066}, // ON_FLY_GATE_ADJUST_EN_0:RW:16:2:=0x03 PHY_GATE_SMPL2_SLAVE_DELAY_0:RW:0:9:=0x0066 + { 0x0000040C, 0x00000000}, // PHY_GATE_TRACKING_OBS_0:RD:0:32:=0x00000000 + { 0x0000040D, 0x00000000}, // PHY_LP4_PST_AMBLE_0:RW:0:1:=0x00 + { 0x0000040E, 0x00000000}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 + { 0x0000040F, 0x00000000}, // PHY_LP4_RDLVL_PATT9_0:RW:0:32:=0x00000000 + { 0x00000410, 0x00000000}, // PHY_LP4_RDLVL_PATT10_0:RW:0:32:=0x00000000 + { 0x00000411, 0x00000000}, // PHY_LP4_RDLVL_PATT11_0:RW:0:32:=0x00000000 + { 0x00000412, 0x00000000}, // PHY_RDDQ_ENC_OBS_SELECT_0:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_0:RW:16:3:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_0:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_0:RW:0:3:=0x00 + { 0x00000413, 0x00000000}, // PHY_FIFO_PTR_OBS_SELECT_0:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_0:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_0:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_0:RW:0:4:=0x00 + { 0x00000414, 0x04080000}, // PHY_WRLVL_UPDT_WAIT_CNT_0:RW:24:4:=0x04 PHY_WRLVL_CAPTURE_CNT_0:RW:16:6:=0x08 SC_PHY_LVL_DEBUG_CONT_0:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_0:RW:0:1:=0x00 + { 0x00000415, 0x04080a04}, // PHY_RDLVL_UPDT_WAIT_CNT_0:RW:24:4:=0x04 PHY_RDLVL_CAPTURE_CNT_0:RW:16:6:=0x08 PHY_GTLVL_UPDT_WAIT_CNT_0:RW:8:4:=0x04 PHY_GTLVL_CAPTURE_CNT_0:RW:0:6:=0x00 + { 0x00000416, 0x00000000}, // PHY_RDLVL_DATA_MASK_0:RW:16:8:=0x00 PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0:RW:8:5:=0x00 PHY_RDLVL_OP_MODE_0:RW:0:2:=0x00 + { 0x00000417, 0x32103210}, // PHY_RDLVL_DATA_SWIZZLE_0:RW:0:32:=0x32103210 + { 0x00000418, 0x00C00208}, // PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0:RW:16:11:=0x00C0 PHY_WDQLVL_PATT_0:RW:8:3:=0x07 PHY_WDQLVL_BURST_CNT_0:RW:0:6:=0x08 + { 0x00000419, 0x0001000C}, // PHY_WDQLVL_CLR_PREV_RESULTS_0:WR:24:1:=0x00 PHY_WDQLVL_QTR_DLY_STEP_0:RW:16:4:=0x01 PHY_WDQLVL_DQDM_OBS_SELECT_0:RW:8:4:=0x00 PHY_WDQLVL_UPDT_WAIT_CNT_0:RW:0:4:=0x0c + { 0x0000041A, 0x00000100}, // PHY_WDQLVL_DATADM_MASK_0:RW:0:9:=0x0100 + { 0x0000041B, 0x55555555}, // PHY_USER_PATT0_0:RW:0:32:=0x55555555 + { 0x0000041C, 0xAAAAAAAA}, // PHY_USER_PATT1_0:RW:0:32:=0xAAAAAAAA + { 0x0000041D, 0x55555555}, // PHY_USER_PATT2_0:RW:0:32:=0x55555555 + { 0x0000041E, 0xAAAAAAAA}, // PHY_USER_PATT3_0:RW:0:32:=0xAAAAAAAA + { 0x0000041F, 0x00005555}, // PHY_USER_PATT4_0:RW:0:16:=0x5555 + { 0x00000420, 0x76543210}, // PHY_DQ_SWIZZLING_0:RW:0:32:=0x76543210 + { 0x00000421, 0x00000001}, // PHY_FIFO_PTR_OBS_0:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_0:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_0:RW:0:1:=0x01 + { 0x00000422, 0x00000000}, // PHY_LPBK_RESULT_OBS_0:RD:0:32:=0x00000000 + { 0x00000423, 0x00000000}, // PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0:RD:24:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_0:RD:16:6:=0x00 PHY_MASTER_DLY_LOCK_OBS_0:RD:0:10:=0x0000 + { 0x00000424, 0x00000000}, // PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0:RD:16:10:=0x0000 PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0:RD:8:8:=0x00 PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0:RD:0:8:=0x00 + { 0x00000425, 0x00000000}, // PHY_WR_SHIFT_OBS_0:RD:24:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_0:RD:16:8:=0x00 PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0:RD:8:8:=0x00 PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0:RD:0:7:=0x00 + { 0x00000426, 0x00000000}, // PHY_WRLVL_HARD1_DELAY_OBS_0:RD:16:10:=0x0000 PHY_WRLVL_HARD0_DELAY_OBS_0:RD:0:10:=0x0000 + { 0x00000427, 0x00000000}, // PHY_WRLVL_STATUS_OBS_0:RD:0:17:=0x000000 + { 0x00000428, 0x00000000}, // PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0:RD:16:9:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0:RD:0:9:=0x0000 + { 0x00000429, 0x00000000}, // PHY_GTLVL_HARD0_DELAY_OBS_0:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_0:RD:0:16:=0x0000 + { 0x0000042A, 0x00000000}, // PHY_GTLVL_STATUS_OBS_0:RD:16:12:=0x0000 PHY_GTLVL_HARD1_DELAY_OBS_0:RD:0:14:=0x0000 + { 0x0000042B, 0x00000000}, // PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0:RD:0:10:=0x0000 + { 0x0000042C, 0x00000000}, // PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0:RD:0:2:=0x00 + { 0x0000042D, 0x00000000}, // PHY_RDLVL_STATUS_OBS_0:RD:0:32:=0x00000000 + { 0x0000042E, 0x00000000}, // PHY_WDQLVL_DQDM_TE_DLY_OBS_0:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_0:RD:0:11:=0x0000 + { 0x0000042F, 0x00000000}, // PHY_WDQLVL_STATUS_OBS_0:RD:0:32:=0x00000000 + { 0x00000430, 0x00000000}, // PHY_DDL_MODE_0:RW:0:18:=0x000000 + { 0x00000431, 0x00000000}, // PHY_DDL_TEST_OBS_0:RD:0:32:=0x00000000 + { 0x00000432, 0x00000000}, // PHY_DDL_TEST_MSTR_DLY_OBS_0:RD:0:32:=0x00000000 + { 0x00000433, 0x00200000}, // PHY_RX_CAL_SAMPLE_WAIT_0:RW:16:8:=0x20 PHY_RX_CAL_OVERRIDE_0:RW:8:1:=0x00 SC_PHY_RX_CAL_START_0:WR:0:1:=0x00 + { 0x00000434, 0x00000000}, // PHY_RX_CAL_DQ1_0:RW+:16:12:=0x0000 PHY_RX_CAL_DQ0_0:RW+:0:12:=0x0000 + { 0x00000435, 0x00000000}, // PHY_RX_CAL_DQ3_0:RW+:16:12:=0x0000 PHY_RX_CAL_DQ2_0:RW+:0:12:=0x0000 + { 0x00000436, 0x00000000}, // PHY_RX_CAL_DQ5_0:RW+:16:12:=0x0000 PHY_RX_CAL_DQ4_0:RW+:0:12:=0x0000 + { 0x00000437, 0x00000000}, // PHY_RX_CAL_DQ7_0:RW+:16:12:=0x0000 PHY_RX_CAL_DQ6_0:RW+:0:12:=0x0000 + { 0x00000438, 0x00000000}, // PHY_RX_CAL_DQS_0:RW+:16:12:=0x0000 PHY_RX_CAL_DM_0:RW+:0:12:=0x0000 + { 0x00000439, 0x00000000}, // PHY_RX_CAL_OBS_0:RD:16:11:=0x0000 PHY_RX_CAL_FDBK_0:RW+:0:12:=0x0000 + { 0x0000043A, 0x02800280}, // PHY_CLK_WRDQ1_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_0:RW+:0:11:=0x0280 + { 0x0000043B, 0x02800280}, // PHY_CLK_WRDQ3_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_0:RW+:0:11:=0x0280 + { 0x0000043C, 0x02800280}, // PHY_CLK_WRDQ5_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_0:RW+:0:11:=0x0280 + { 0x0000043D, 0x02800280}, // PHY_CLK_WRDQ7_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_0:RW+:0:11:=0x0280 + { 0x0000043E, 0x00000280}, // PHY_CLK_WRDQS_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_0:RW+:0:11:=0x0280 + { 0x0000043F, 0x00000000}, // PHY_RDDQ1_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_0:RW+:0:10:=0x0000 + { 0x00000440, 0x00000000}, // PHY_RDDQ3_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_0:RW+:0:10:=0x0000 + { 0x00000441, 0x00000000}, // PHY_RDDQ5_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_0:RW+:0:10:=0x0000 + { 0x00000442, 0x00000000}, // PHY_RDDQ7_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_0:RW+:0:10:=0x0000 + { 0x00000443, 0x00A000A0}, // PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0:RW+:16:10:=0x00A0 PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + { 0x00000444, 0x00A000A0}, // PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0:RW+:16:10:=0x00A0 PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + { 0x00000445, 0x00A000A0}, // PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0:RW+:16:10:=0x00A0 PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + { 0x00000446, 0x00A000A0}, // PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0:RW+:16:10:=0x00A0 PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + { 0x00000447, 0x00A000A0}, // PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0:RW+:16:10:=0x00A0 PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + { 0x00000448, 0x00A000A0}, // PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0:RW+:16:10:=0x00A0 PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + { 0x00000449, 0x00A000A0}, // PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0:RW+:16:10:=0x00A0 PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + { 0x0000044A, 0x00A000A0}, // PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0:RW+:16:10:=0x00A0 PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + { 0x0000044B, 0x00A000A0}, // PHY_RDDQS_DM_FALL_SLAVE_DELAY_0:RW+:16:10:=0x00A0 PHY_RDDQS_DM_RISE_SLAVE_DELAY_0:RW+:0:10:=0x00a0 + { 0x0000044C, 0x00040109}, // PHY_WRITE_PATH_LAT_ADD_0:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_0:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_0:RW+:0:10:=0x0109 + { 0x0000044D, 0x000001D0}, // PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0:RW+:16:10:=0x0000 PHY_WRLVL_DELAY_EARLY_THRESHOLD_0:RW+:0:10:=0x01d0 + { 0x0000044E, 0x03000000}, // PHY_GTLVL_LAT_ADJ_START_0:RW+:24:4:=0x07 PHY_GTLVL_RDDQS_SLV_DLY_START_0:RW+:8:10:=0x0000 PHY_WRLVL_EARLY_FORCE_ZERO_0:RW+:0:1:=0x00 + { 0x0000044F, 0x00000200}, // PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0:RW+:16:10:=0x0000 PHY_WDQLVL_DQDM_SLV_DLY_START_0:RW+:0:11:=0x0200 +// { 0x00000450, 0x41315141}, // PHY_DQS_OE_TIMING_0:RW+:24:8:=0x41 PHY_DQ_TSEL_WR_TIMING_0:RW+:16:8:=0x31 PHY_DQ_TSEL_RD_TIMING_0:RW+:8:8:=0x51 PHY_DQ_OE_TIMING_0:RW+:0:8:=0x41 + { 0x00000450, 0x41415141}, // PHY_DQS_OE_TIMING_0:RW+:24:8:=0x41 PHY_DQ_TSEL_WR_TIMING_0:RW+:16:8:=0x31 PHY_DQ_TSEL_RD_TIMING_0:RW+:8:8:=0x51 PHY_DQ_OE_TIMING_0:RW+:0:8:=0x41 +// { 0x00000451, 0xC0013150}, // PHY_DQ_IE_TIMING_0:RW+:24:8:=0xc0 PHY_PER_CS_TRAINING_EN_0:RW+:16:1:=0x01 PHY_DQS_TSEL_WR_TIMING_0:RW+:8:8:=0x31 PHY_DQS_TSEL_RD_TIMING_0:RW+:0:8:=0x50 + { 0x00000451, 0xC0014150}, // PHY_DQ_IE_TIMING_0:RW+:24:8:=0xc0 PHY_PER_CS_TRAINING_EN_0:RW+:16:1:=0x01 PHY_DQS_TSEL_WR_TIMING_0:RW+:8:8:=0x31 PHY_DQS_TSEL_RD_TIMING_0:RW+:0:8:=0x50 + { 0x00000452, 0x0E0000C0}, // PHY_RDDATA_EN_DLY_0:RW+:24:4:=0x0e PHY_IE_MODE_0:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_0:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_0:RW+:0:8:=0xc0 + { 0x00000453, 0x0010000C}, // PHY_MASTER_DELAY_START_0:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_0:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_0:RW+:0:4:=0x0c + { 0x00000454, 0x0C064208}, // PHY_WRLVL_DLY_STEP_0:RW+:24:4:=0x0c PHY_RPTR_UPDATE_0:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_0:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_0:RW+:0:6:=0x08 + { 0x00000455, 0x000F0C18}, // PHY_GTLVL_RESP_WAIT_CNT_0:RW+:16:5:=0x0f PHY_GTLVL_DLY_STEP_0:RW+:8:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_0:RW+:0:5:=0x18 + { 0x00000456, 0x01000140}, // PHY_GTLVL_FINAL_STEP_0:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_0:RW+:0:10:=0x0140 + { 0x00000457, 0x00000C20}, // PHY_RDLVL_DLY_STEP_0:RW+:8:4:=0x0c PHY_WDQLVL_DLY_STEP_0:RW+:0:8:=0x20 + { 0x00000458, 0x00000000}, // + { 0x00000459, 0x00000000}, // + { 0x0000045A, 0x00000000}, // + { 0x0000045B, 0x00000000}, // + { 0x0000045C, 0x00000000}, // + { 0x0000045D, 0x00000000}, // + { 0x0000045E, 0x00000000}, // + { 0x0000045F, 0x00000000}, // + { 0x00000460, 0x00000000}, // + { 0x00000461, 0x00000000}, // + { 0x00000462, 0x00000000}, // + { 0x00000463, 0x00000000}, // + { 0x00000464, 0x00000000}, // + { 0x00000465, 0x00000000}, // + { 0x00000466, 0x00000000}, // + { 0x00000467, 0x00000000}, // + { 0x00000468, 0x00000000}, // + { 0x00000469, 0x00000000}, // + { 0x0000046A, 0x00000000}, // + { 0x0000046B, 0x00000000}, // + { 0x0000046C, 0x00000000}, // + { 0x0000046D, 0x00000000}, // + { 0x0000046E, 0x00000000}, // + { 0x0000046F, 0x00000000}, // + { 0x00000470, 0x00000000}, // + { 0x00000471, 0x00000000}, // + { 0x00000472, 0x00000000}, // + { 0x00000473, 0x00000000}, // + { 0x00000474, 0x00000000}, // + { 0x00000475, 0x00000000}, // + { 0x00000476, 0x00000000}, // + { 0x00000477, 0x00000000}, // + { 0x00000478, 0x00000000}, // + { 0x00000479, 0x00000000}, // + { 0x0000047A, 0x00000000}, // + { 0x0000047B, 0x00000000}, // + { 0x0000047C, 0x00000000}, // + { 0x0000047D, 0x00000000}, // + { 0x0000047E, 0x00000000}, // + { 0x0000047F, 0x00000000}, // + { 0x00000480, 0x000004F0}, // PHY_SW_WRDQ0_SHIFT_1:RW:24:5:=0x00 PHY_CLK_BYPASS_OVERRIDE_1:RW:16:1:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_1:RW:0:11:=0x04f0 + { 0x00000481, 0x00000000}, // PHY_SW_WRDQ4_SHIFT_1:RW:24:5:=0x00 PHY_SW_WRDQ3_SHIFT_1:RW:16:5:=0x00 PHY_SW_WRDQ2_SHIFT_1:RW:8:5:=0x00 PHY_SW_WRDQ1_SHIFT_1:RW:0:5:=0x00 + { 0x00000482, 0x00000000}, // PHY_SW_WRDM_SHIFT_1:RW:24:5:=0x00 PHY_SW_WRDQ7_SHIFT_1:RW:16:5:=0x00 PHY_SW_WRDQ6_SHIFT_1:RW:8:5:=0x00 PHY_SW_WRDQ5_SHIFT_1:RW:0:5:=0x00 +// { 0x00000483, 0x00000100}, // PHY_DQ_TSEL_ENABLE_1:RW:8:3:=0x01 PHY_SW_WRDQS_SHIFT_1:RW:0:4:=0x00 + { 0x00000483, 0x00000300}, // PHY_DQ_TSEL_ENABLE_1:RW:8:3:=0x01 PHY_SW_WRDQS_SHIFT_1:RW:0:4:=0x00 +// { 0x00000484, 0x01CC6E0C}, // PHY_DQS_TSEL_ENABLE_1:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_1:RW:0:24:=0x665555 + { 0x00000484, 0x030E6E0E}, // PHY_DQS_TSEL_ENABLE_1:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_1:RW:0:24:=0x665555 +// { 0x00000484, 0x036E6E0E}, // PHY_DQS_TSEL_ENABLE_1:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_1:RW:0:24:=0x665555 +// { 0x00000485, 0x02CC6E0C}, // PHY_TWO_CYC_PREAMBLE_1:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_1:RW:0:24:=0x665555 + { 0x00000485, 0x020E6E0E}, // PHY_TWO_CYC_PREAMBLE_1:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_1:RW:0:24:=0x665555 +// { 0x00000485, 0x026E6E0E}, // PHY_TWO_CYC_PREAMBLE_1:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_1:RW:0:24:=0x665555 + { 0x00000486, 0x00010F00}, // PHY_PER_CS_TRAINING_INDEX_1:RW:24:1:=0x00 PHY_PER_CS_TRAINING_MULTICAST_EN_1:RW_D:16:1:=0x01 PHY_PER_RANK_CS_MAP_1:RW:8:2:=0x0f PHY_DBI_MODE_1:RW:0:1:=0x00 + { 0x00000487, 0x04000100}, // PHY_LP4_BOOT_RPTR_UPDATE_1:RW:24:4:=0x04 PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1:RW:16:4:=0x00 PHY_LP4_BOOT_RDDATA_EN_DLY_1:RW:8:4:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1:RW:0:2:=0x00 + { 0x00000488, 0x00000133}, // PHY_LPBK_CONTROL_1:RW:24:7:=0x00 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1:RW:16:4:=0x00 PHY_LP4_BOOT_RDDQS_GATE_SLAVE_DELAY_1:RW:0:10:=0x0133 + { 0x00000489, 0x000700C0}, // SC_PHY_SNAP_OBS_REGS_1:WR:24:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_1:RW:16:4:=0x07 PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1:RW:0:10:=0x00c0 + { 0x0000048A, 0x00CC0201}, // PHY_GATE_SMPL1_SLAVE_DELAY_1:RW:16:9:=0x00cc PHY_LPDDR_TYPE_1:RW:8:2:=0x02 PHY_LPDDR_1:RW:0:1:=0x01 + { 0x0000048B, 0x00030066}, // ON_FLY_GATE_ADJUST_EN_1:RW:16:2:=0x03 PHY_GATE_SMPL2_SLAVE_DELAY_1:RW:0:9:=0x0066 + { 0x0000048C, 0x00000000}, // PHY_GATE_TRACKING_OBS_1:RD:0:32:=0x00000000 + { 0x0000048D, 0x00000000}, // PHY_LP4_PST_AMBLE_1:RW:0:1:=0x00 + { 0x0000048E, 0x00000000}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 + { 0x0000048F, 0x00000000}, // PHY_LP4_RDLVL_PATT9_1:RW:0:32:=0x00000000 + { 0x00000490, 0x00000000}, // PHY_LP4_RDLVL_PATT10_1:RW:0:32:=0x00000000 + { 0x00000491, 0x00000000}, // PHY_LP4_RDLVL_PATT11_1:RW:0:32:=0x00000000 + { 0x00000492, 0x00000000}, // PHY_RDDQ_ENC_OBS_SELECT_1:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_1:RW:16:3:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_1:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_1:RW:0:3:=0x00 + { 0x00000493, 0x00000000}, // PHY_FIFO_PTR_OBS_SELECT_1:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_1:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_1:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_1:RW:0:4:=0x00 + { 0x00000494, 0x04080000}, // PHY_WRLVL_UPDT_WAIT_CNT_1:RW:24:4:=0x04 PHY_WRLVL_CAPTURE_CNT_1:RW:16:6:=0x08 SC_PHY_LVL_DEBUG_CONT_1:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_1:RW:0:1:=0x00 + { 0x00000495, 0x04080a04}, // PHY_RDLVL_UPDT_WAIT_CNT_1:RW:24:4:=0x04 PHY_RDLVL_CAPTURE_CNT_1:RW:16:6:=0x08 PHY_GTLVL_UPDT_WAIT_CNT_1:RW:8:4:=0x04 PHY_GTLVL_CAPTURE_CNT_1:RW:0:6:=0x00 + { 0x00000496, 0x00000000}, // PHY_RDLVL_DATA_MASK_1:RW:16:8:=0x00 PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1:RW:8:5:=0x00 PHY_RDLVL_OP_MODE_1:RW:0:2:=0x00 + { 0x00000497, 0x32103210}, // PHY_RDLVL_DATA_SWIZZLE_1:RW:0:32:=0x32103210 + { 0x00000498, 0x00C00208}, // PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1:RW:16:11:=0x00C0 PHY_WDQLVL_PATT_1:RW:8:3:=0x07 PHY_WDQLVL_BURST_CNT_1:RW:0:6:=0x08 + { 0x00000499, 0x0001000C}, // PHY_WDQLVL_CLR_PREV_RESULTS_1:WR:24:1:=0x00 PHY_WDQLVL_QTR_DLY_STEP_1:RW:16:4:=0x01 PHY_WDQLVL_DQDM_OBS_SELECT_1:RW:8:4:=0x00 PHY_WDQLVL_UPDT_WAIT_CNT_1:RW:0:4:=0x0c + { 0x0000049A, 0x00000100}, // PHY_WDQLVL_DATADM_MASK_1:RW:0:9:=0x0100 + { 0x0000049B, 0x55555555}, // PHY_USER_PATT0_1:RW:0:32:=0x55555555 + { 0x0000049C, 0xAAAAAAAA}, // PHY_USER_PATT1_1:RW:0:32:=0xAAAAAAAA + { 0x0000049D, 0x55555555}, // PHY_USER_PATT2_1:RW:0:32:=0x55555555 + { 0x0000049E, 0xAAAAAAAA}, // PHY_USER_PATT3_1:RW:0:32:=0xAAAAAAAA + { 0x0000049F, 0x00005555}, // PHY_USER_PATT4_1:RW:0:16:=0x5555 + { 0x000004A0, 0x76543210}, // PHY_DQ_SWIZZLING_1:RW:0:32:=0x76543210 + { 0x000004A1, 0x00000000}, // PHY_FIFO_PTR_OBS_1:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_1:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_1:RW:0:1:=0x00 + { 0x000004A2, 0x00000000}, // PHY_LPBK_RESULT_OBS_1:RD:0:32:=0x00000000 + { 0x000004A3, 0x00000000}, // PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1:RD:24:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_1:RD:16:6:=0x00 PHY_MASTER_DLY_LOCK_OBS_1:RD:0:10:=0x0000 + { 0x000004A4, 0x00000000}, // PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1:RD:16:10:=0x0000 PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1:RD:8:8:=0x00 PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1:RD:0:8:=0x00 + { 0x000004A5, 0x00000000}, // PHY_WR_SHIFT_OBS_1:RD:24:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_1:RD:16:8:=0x00 PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1:RD:8:8:=0x00 PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1:RD:0:7:=0x00 + { 0x000004A6, 0x00000000}, // PHY_WRLVL_HARD1_DELAY_OBS_1:RD:16:10:=0x0000 PHY_WRLVL_HARD0_DELAY_OBS_1:RD:0:10:=0x0000 + { 0x000004A7, 0x00000000}, // PHY_WRLVL_STATUS_OBS_1:RD:0:17:=0x000000 + { 0x000004A8, 0x00000000}, // PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1:RD:16:9:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1:RD:0:9:=0x0000 + { 0x000004A9, 0x00000000}, // PHY_GTLVL_HARD0_DELAY_OBS_1:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_1:RD:0:16:=0x0000 + { 0x000004AA, 0x00000000}, // PHY_GTLVL_STATUS_OBS_1:RD:16:12:=0x0000 PHY_GTLVL_HARD1_DELAY_OBS_1:RD:0:14:=0x0000 + { 0x000004AB, 0x00000000}, // PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1:RD:0:10:=0x0000 + { 0x000004AC, 0x00000000}, // PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1:RD:0:2:=0x00 + { 0x000004AD, 0x00000000}, // PHY_RDLVL_STATUS_OBS_1:RD:0:32:=0x00000000 + { 0x000004AE, 0x00000000}, // PHY_WDQLVL_DQDM_TE_DLY_OBS_1:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_1:RD:0:11:=0x0000 + { 0x000004AF, 0x00000000}, // PHY_WDQLVL_STATUS_OBS_1:RD:0:32:=0x00000000 + { 0x000004B0, 0x00000000}, // PHY_DDL_MODE_1:RW:0:18:=0x000000 + { 0x000004B1, 0x00000000}, // PHY_DDL_TEST_OBS_1:RD:0:32:=0x00000000 + { 0x000004B2, 0x00000000}, // PHY_DDL_TEST_MSTR_DLY_OBS_1:RD:0:32:=0x00000000 + { 0x000004B3, 0x00200000}, // PHY_RX_CAL_SAMPLE_WAIT_1:RW:16:8:=0x20 PHY_RX_CAL_OVERRIDE_1:RW:8:1:=0x00 SC_PHY_RX_CAL_START_1:WR:0:1:=0x00 + { 0x000004B4, 0x00000000}, // PHY_RX_CAL_DQ1_1:RW+:16:12:=0x0000 PHY_RX_CAL_DQ0_1:RW+:0:12:=0x0000 + { 0x000004B5, 0x00000000}, // PHY_RX_CAL_DQ3_1:RW+:16:12:=0x0000 PHY_RX_CAL_DQ2_1:RW+:0:12:=0x0000 + { 0x000004B6, 0x00000000}, // PHY_RX_CAL_DQ5_1:RW+:16:12:=0x0000 PHY_RX_CAL_DQ4_1:RW+:0:12:=0x0000 + { 0x000004B7, 0x00000000}, // PHY_RX_CAL_DQ7_1:RW+:16:12:=0x0000 PHY_RX_CAL_DQ6_1:RW+:0:12:=0x0000 + { 0x000004B8, 0x00000000}, // PHY_RX_CAL_DQS_1:RW+:16:12:=0x0000 PHY_RX_CAL_DM_1:RW+:0:12:=0x0000 + { 0x000004B9, 0x00000000}, // PHY_RX_CAL_OBS_1:RD:16:11:=0x0000 PHY_RX_CAL_FDBK_1:RW+:0:12:=0x0000 + { 0x000004BA, 0x02800280}, // PHY_CLK_WRDQ1_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_1:RW+:0:11:=0x0280 + { 0x000004BB, 0x02800280}, // PHY_CLK_WRDQ3_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_1:RW+:0:11:=0x0280 + { 0x000004BC, 0x02800280}, // PHY_CLK_WRDQ5_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_1:RW+:0:11:=0x0280 + { 0x000004BD, 0x02800280}, // PHY_CLK_WRDQ7_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_1:RW+:0:11:=0x0280 + { 0x000004BE, 0x00000280}, // PHY_CLK_WRDQS_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_1:RW+:0:11:=0x0280 + { 0x000004BF, 0x00000000}, // PHY_RDDQ1_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_1:RW+:0:10:=0x0000 + { 0x000004C0, 0x00000000}, // PHY_RDDQ3_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_1:RW+:0:10:=0x0000 + { 0x000004C1, 0x00000000}, // PHY_RDDQ5_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_1:RW+:0:10:=0x0000 + { 0x000004C2, 0x00000000}, // PHY_RDDQ7_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_1:RW+:0:10:=0x0000 + { 0x000004C3, 0x00A000A0}, // PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1:RW+:16:10:=0x00A0 PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + { 0x000004C4, 0x00A000A0}, // PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1:RW+:16:10:=0x00A0 PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + { 0x000004C5, 0x00A000A0}, // PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1:RW+:16:10:=0x00A0 PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + { 0x000004C6, 0x00A000A0}, // PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1:RW+:16:10:=0x00A0 PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + { 0x000004C7, 0x00A000A0}, // PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1:RW+:16:10:=0x00A0 PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + { 0x000004C8, 0x00A000A0}, // PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1:RW+:16:10:=0x00A0 PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + { 0x000004C9, 0x00A000A0}, // PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1:RW+:16:10:=0x00A0 PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + { 0x000004CA, 0x00A000A0}, // PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1:RW+:16:10:=0x00A0 PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + { 0x000004CB, 0x00A000A0}, // PHY_RDDQS_DM_FALL_SLAVE_DELAY_1:RW+:16:10:=0x00A0 PHY_RDDQS_DM_RISE_SLAVE_DELAY_1:RW+:0:10:=0x00a0 + { 0x000004CC, 0x00040109}, // PHY_WRITE_PATH_LAT_ADD_1:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_1:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_1:RW+:0:10:=0x0109 + { 0x000004CD, 0x000001D0}, // PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1:RW+:16:10:=0x0000 PHY_WRLVL_DELAY_EARLY_THRESHOLD_1:RW+:0:10:=0x01d0 + { 0x000004CE, 0x03000000}, // PHY_GTLVL_LAT_ADJ_START_1:RW+:24:4:=0x07 PHY_GTLVL_RDDQS_SLV_DLY_START_1:RW+:8:10:=0x0000 PHY_WRLVL_EARLY_FORCE_ZERO_1:RW+:0:1:=0x00 + { 0x000004CF, 0x00000200}, // PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1:RW+:16:10:=0x0000 PHY_WDQLVL_DQDM_SLV_DLY_START_1:RW+:0:11:=0x0200 +// { 0x000004D0, 0x41315141}, // PHY_DQS_OE_TIMING_1:RW+:24:8:=0x41 PHY_DQ_TSEL_WR_TIMING_1:RW+:16:8:=0x31 PHY_DQ_TSEL_RD_TIMING_1:RW+:8:8:=0x51 PHY_DQ_OE_TIMING_1:RW+:0:8:=0x41 + { 0x000004D0, 0x41415141}, // PHY_DQS_OE_TIMING_1:RW+:24:8:=0x41 PHY_DQ_TSEL_WR_TIMING_1:RW+:16:8:=0x31 PHY_DQ_TSEL_RD_TIMING_1:RW+:8:8:=0x51 PHY_DQ_OE_TIMING_1:RW+:0:8:=0x41 +// { 0x000004D1, 0xC0013150}, // PHY_DQ_IE_TIMING_1:RW+:24:8:=0xc0 PHY_PER_CS_TRAINING_EN_1:RW+:16:1:=0x01 PHY_DQS_TSEL_WR_TIMING_1:RW+:8:8:=0x31 PHY_DQS_TSEL_RD_TIMING_1:RW+:0:8:=0x50 + { 0x000004D1, 0xC0014150}, // PHY_DQ_IE_TIMING_1:RW+:24:8:=0xc0 PHY_PER_CS_TRAINING_EN_1:RW+:16:1:=0x01 PHY_DQS_TSEL_WR_TIMING_1:RW+:8:8:=0x31 PHY_DQS_TSEL_RD_TIMING_1:RW+:0:8:=0x50 + { 0x000004D2, 0x0E0000C0}, // PHY_RDDATA_EN_DLY_1:RW+:24:4:=0x0e PHY_IE_MODE_1:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_1:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_1:RW+:0:8:=0xc0 + { 0x000004D3, 0x0010000C}, // PHY_MASTER_DELAY_START_1:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_1:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_1:RW+:0:4:=0x0c + { 0x000004D4, 0x0C064208}, // PHY_WRLVL_DLY_STEP_1:RW+:24:4:=0x0c PHY_RPTR_UPDATE_1:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_1:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_1:RW+:0:6:=0x08 + { 0x000004D5, 0x000F0C18}, // PHY_GTLVL_RESP_WAIT_CNT_1:RW+:16:5:=0x0f PHY_GTLVL_DLY_STEP_1:RW+:8:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_1:RW+:0:5:=0x18 + { 0x000004D6, 0x01000140}, // PHY_GTLVL_FINAL_STEP_1:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_1:RW+:0:10:=0x0140 + { 0x000004D7, 0x00000C20}, // PHY_RDLVL_DLY_STEP_1:RW+:8:4:=0x0c PHY_WDQLVL_DLY_STEP_1:RW+:0:8:=0x20 + { 0x000004D8, 0x00000000}, // + { 0x000004D9, 0x00000000}, // + { 0x000004DA, 0x00000000}, // + { 0x000004DB, 0x00000000}, // + { 0x000004DC, 0x00000000}, // + { 0x000004DD, 0x00000000}, // + { 0x000004DE, 0x00000000}, // + { 0x000004DF, 0x00000000}, // + { 0x000004E0, 0x00000000}, // + { 0x000004E1, 0x00000000}, // + { 0x000004E2, 0x00000000}, // + { 0x000004E3, 0x00000000}, // + { 0x000004E4, 0x00000000}, // + { 0x000004E5, 0x00000000}, // + { 0x000004E6, 0x00000000}, // + { 0x000004E7, 0x00000000}, // + { 0x000004E8, 0x00000000}, // + { 0x000004E9, 0x00000000}, // + { 0x000004EA, 0x00000000}, // + { 0x000004EB, 0x00000000}, // + { 0x000004EC, 0x00000000}, // + { 0x000004ED, 0x00000000}, // + { 0x000004EE, 0x00000000}, // + { 0x000004EF, 0x00000000}, // + { 0x000004F0, 0x00000000}, // + { 0x000004F1, 0x00000000}, // + { 0x000004F2, 0x00000000}, // + { 0x000004F3, 0x00000000}, // + { 0x000004F4, 0x00000000}, // + { 0x000004F5, 0x00000000}, // + { 0x000004F6, 0x00000000}, // + { 0x000004F7, 0x00000000}, // + { 0x000004F8, 0x00000000}, // + { 0x000004F9, 0x00000000}, // + { 0x000004FA, 0x00000000}, // + { 0x000004FB, 0x00000000}, // + { 0x000004FC, 0x00000000}, // + { 0x000004FD, 0x00000000}, // + { 0x000004FE, 0x00000000}, // + { 0x000004FF, 0x00000000}, // + { 0x00000500, 0x000004F0}, // PHY_SW_WRDQ0_SHIFT_2:RW:24:5:=0x00 PHY_CLK_BYPASS_OVERRIDE_2:RW:16:1:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_2:RW:0:11:=0x04f0 + { 0x00000501, 0x00000000}, // PHY_SW_WRDQ4_SHIFT_2:RW:24:5:=0x00 PHY_SW_WRDQ3_SHIFT_2:RW:16:5:=0x00 PHY_SW_WRDQ2_SHIFT_2:RW:8:5:=0x00 PHY_SW_WRDQ1_SHIFT_2:RW:0:5:=0x00 + { 0x00000502, 0x00000000}, // PHY_SW_WRDM_SHIFT_2:RW:24:5:=0x00 PHY_SW_WRDQ7_SHIFT_2:RW:16:5:=0x00 PHY_SW_WRDQ6_SHIFT_2:RW:8:5:=0x00 PHY_SW_WRDQ5_SHIFT_2:RW:0:5:=0x00 +// { 0x00000503, 0x00000100}, // PHY_DQ_TSEL_ENABLE_2:RW:8:3:=0x01 PHY_SW_WRDQS_SHIFT_2:RW:0:4:=0x00 + { 0x00000503, 0x00000300}, // PHY_DQ_TSEL_ENABLE_2:RW:8:3:=0x01 PHY_SW_WRDQS_SHIFT_2:RW:0:4:=0x00 +// { 0x00000504, 0x01CC6E0C}, // PHY_DQS_TSEL_ENABLE_2:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_2:RW:0:24:=0x665555 + { 0x00000504, 0x030E6E0E}, // PHY_DQS_TSEL_ENABLE_2:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_2:RW:0:24:=0x665555 +// { 0x00000504, 0x036E6E0E}, // PHY_DQS_TSEL_ENABLE_2:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_2:RW:0:24:=0x665555 +// { 0x00000505, 0x02CC6E0C}, // PHY_TWO_CYC_PREAMBLE_2:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_2:RW:0:24:=0x665555 + { 0x00000505, 0x020E6E0E}, // PHY_TWO_CYC_PREAMBLE_2:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_2:RW:0:24:=0x665555 +// { 0x00000505, 0x026E6E0E}, // PHY_TWO_CYC_PREAMBLE_2:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_2:RW:0:24:=0x665555 + { 0x00000506, 0x00010F00}, // PHY_PER_CS_TRAINING_INDEX_2:RW:24:1:=0x00 PHY_PER_CS_TRAINING_MULTICAST_EN_2:RW_D:16:1:=0x01 PHY_PER_RANK_CS_MAP_2:RW:8:2:=0x0f PHY_DBI_MODE_2:RW:0:1:=0x00 + { 0x00000507, 0x04000100}, // PHY_LP4_BOOT_RPTR_UPDATE_2:RW:24:4:=0x04 PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2:RW:16:4:=0x00 PHY_LP4_BOOT_RDDATA_EN_DLY_2:RW:8:4:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2:RW:0:2:=0x00 + { 0x00000508, 0x00000133}, // PHY_LPBK_CONTROL_2:RW:24:7:=0x00 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2:RW:16:4:=0x00 PHY_LP4_BOOT_RDDQS_GATE_SLAVE_DELAY_2:RW:0:10:=0x0133 + { 0x00000509, 0x000700C0}, // SC_PHY_SNAP_OBS_REGS_2:WR:24:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_2:RW:16:4:=0x07 PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2:RW:0:10:=0x00c0 + { 0x0000050A, 0x00CC0201}, // PHY_GATE_SMPL1_SLAVE_DELAY_2:RW:16:9:=0x00cc PHY_LPDDR_TYPE_2:RW:8:2:=0x02 PHY_LPDDR_2:RW:0:1:=0x01 + { 0x0000050B, 0x00030066}, // ON_FLY_GATE_ADJUST_EN_2:RW:16:2:=0x03 PHY_GATE_SMPL2_SLAVE_DELAY_2:RW:0:9:=0x0066 + { 0x0000050C, 0x00000000}, // PHY_GATE_TRACKING_OBS_2:RD:0:32:=0x00000000 + { 0x0000050D, 0x00000000}, // PHY_LP4_PST_AMBLE_2:RW:0:1:=0x00 + { 0x0000050E, 0x00000000}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 + { 0x0000050F, 0x00000000}, // PHY_LP4_RDLVL_PATT9_2:RW:0:32:=0x00000000 + { 0x00000510, 0x00000000}, // PHY_LP4_RDLVL_PATT10_2:RW:0:32:=0x00000000 + { 0x00000511, 0x00000000}, // PHY_LP4_RDLVL_PATT11_2:RW:0:32:=0x00000000 + { 0x00000512, 0x00000000}, // PHY_RDDQ_ENC_OBS_SELECT_2:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_2:RW:16:3:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_2:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_2:RW:0:3:=0x00 + { 0x00000513, 0x00000000}, // PHY_FIFO_PTR_OBS_SELECT_2:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_2:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_2:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_2:RW:0:4:=0x00 + { 0x00000514, 0x04080000}, // PHY_WRLVL_UPDT_WAIT_CNT_2:RW:24:4:=0x04 PHY_WRLVL_CAPTURE_CNT_2:RW:16:6:=0x08 SC_PHY_LVL_DEBUG_CONT_2:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_2:RW:0:1:=0x00 + { 0x00000515, 0x04080a04}, // PHY_RDLVL_UPDT_WAIT_CNT_2:RW:24:4:=0x04 PHY_RDLVL_CAPTURE_CNT_2:RW:16:6:=0x08 PHY_GTLVL_UPDT_WAIT_CNT_2:RW:8:4:=0x04 PHY_GTLVL_CAPTURE_CNT_2:RW:0:6:=0x00 + { 0x00000516, 0x00000000}, // PHY_RDLVL_DATA_MASK_2:RW:16:8:=0x00 PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2:RW:8:5:=0x00 PHY_RDLVL_OP_MODE_2:RW:0:2:=0x00 + { 0x00000517, 0x32103210}, // PHY_RDLVL_DATA_SWIZZLE_2:RW:0:32:=0x32103210 + { 0x00000518, 0x00C00208}, // PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2:RW:16:11:=0x00C0 PHY_WDQLVL_PATT_2:RW:8:3:=0x07 PHY_WDQLVL_BURST_CNT_2:RW:0:6:=0x08 + { 0x00000519, 0x0001000C}, // PHY_WDQLVL_CLR_PREV_RESULTS_2:WR:24:1:=0x00 PHY_WDQLVL_QTR_DLY_STEP_2:RW:16:4:=0x01 PHY_WDQLVL_DQDM_OBS_SELECT_2:RW:8:4:=0x00 PHY_WDQLVL_UPDT_WAIT_CNT_2:RW:0:4:=0x0c + { 0x0000051A, 0x00000100}, // PHY_WDQLVL_DATADM_MASK_2:RW:0:9:=0x0100 + { 0x0000051B, 0x55555555}, // PHY_USER_PATT0_2:RW:0:32:=0x55555555 + { 0x0000051C, 0xAAAAAAAA}, // PHY_USER_PATT1_2:RW:0:32:=0xAAAAAAAA + { 0x0000051D, 0x55555555}, // PHY_USER_PATT2_2:RW:0:32:=0x55555555 + { 0x0000051E, 0xAAAAAAAA}, // PHY_USER_PATT3_2:RW:0:32:=0xAAAAAAAA + { 0x0000051F, 0x00005555}, // PHY_USER_PATT4_2:RW:0:16:=0x5555 + { 0x00000520, 0x76543210}, // PHY_DQ_SWIZZLING_2:RW:0:32:=0x76543210 + { 0x00000521, 0x00000001}, // PHY_FIFO_PTR_OBS_2:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_2:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_2:RW:0:1:=0x01 + { 0x00000522, 0x00000000}, // PHY_LPBK_RESULT_OBS_2:RD:0:32:=0x00000000 + { 0x00000523, 0x00000000}, // PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2:RD:24:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_2:RD:16:6:=0x00 PHY_MASTER_DLY_LOCK_OBS_2:RD:0:10:=0x0000 + { 0x00000524, 0x00000000}, // PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2:RD:16:10:=0x0000 PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2:RD:8:8:=0x00 PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2:RD:0:8:=0x00 + { 0x00000525, 0x00000000}, // PHY_WR_SHIFT_OBS_2:RD:24:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_2:RD:16:8:=0x00 PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2:RD:8:8:=0x00 PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2:RD:0:7:=0x00 + { 0x00000526, 0x00000000}, // PHY_WRLVL_HARD1_DELAY_OBS_2:RD:16:10:=0x0000 PHY_WRLVL_HARD0_DELAY_OBS_2:RD:0:10:=0x0000 + { 0x00000527, 0x00000000}, // PHY_WRLVL_STATUS_OBS_2:RD:0:17:=0x000000 + { 0x00000528, 0x00000000}, // PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2:RD:16:9:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2:RD:0:9:=0x0000 + { 0x00000529, 0x00000000}, // PHY_GTLVL_HARD0_DELAY_OBS_2:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_2:RD:0:16:=0x0000 + { 0x0000052A, 0x00000000}, // PHY_GTLVL_STATUS_OBS_2:RD:16:12:=0x0000 PHY_GTLVL_HARD1_DELAY_OBS_2:RD:0:14:=0x0000 + { 0x0000052B, 0x00000000}, // PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2:RD:0:10:=0x0000 + { 0x0000052C, 0x00000000}, // PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2:RD:0:2:=0x00 + { 0x0000052D, 0x00000000}, // PHY_RDLVL_STATUS_OBS_2:RD:0:32:=0x00000000 + { 0x0000052E, 0x00000000}, // PHY_WDQLVL_DQDM_TE_DLY_OBS_2:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_2:RD:0:11:=0x0000 + { 0x0000052F, 0x00000000}, // PHY_WDQLVL_STATUS_OBS_2:RD:0:32:=0x00000000 + { 0x00000530, 0x00000000}, // PHY_DDL_MODE_2:RW:0:18:=0x000000 + { 0x00000531, 0x00000000}, // PHY_DDL_TEST_OBS_2:RD:0:32:=0x00000000 + { 0x00000532, 0x00000000}, // PHY_DDL_TEST_MSTR_DLY_OBS_2:RD:0:32:=0x00000000 + { 0x00000533, 0x00200000}, // PHY_RX_CAL_SAMPLE_WAIT_2:RW:16:8:=0x20 PHY_RX_CAL_OVERRIDE_2:RW:8:1:=0x00 SC_PHY_RX_CAL_START_2:WR:0:1:=0x00 + { 0x00000534, 0x00000000}, // PHY_RX_CAL_DQ1_2:RW+:16:12:=0x0000 PHY_RX_CAL_DQ0_2:RW+:0:12:=0x0000 + { 0x00000535, 0x00000000}, // PHY_RX_CAL_DQ3_2:RW+:16:12:=0x0000 PHY_RX_CAL_DQ2_2:RW+:0:12:=0x0000 + { 0x00000536, 0x00000000}, // PHY_RX_CAL_DQ5_2:RW+:16:12:=0x0000 PHY_RX_CAL_DQ4_2:RW+:0:12:=0x0000 + { 0x00000537, 0x00000000}, // PHY_RX_CAL_DQ7_2:RW+:16:12:=0x0000 PHY_RX_CAL_DQ6_2:RW+:0:12:=0x0000 + { 0x00000538, 0x00000000}, // PHY_RX_CAL_DQS_2:RW+:16:12:=0x0000 PHY_RX_CAL_DM_2:RW+:0:12:=0x0000 + { 0x00000539, 0x00000000}, // PHY_RX_CAL_OBS_2:RD:16:11:=0x0000 PHY_RX_CAL_FDBK_2:RW+:0:12:=0x0000 + { 0x0000053A, 0x02800280}, // PHY_CLK_WRDQ1_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_2:RW+:0:11:=0x0280 + { 0x0000053B, 0x02800280}, // PHY_CLK_WRDQ3_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_2:RW+:0:11:=0x0280 + { 0x0000053C, 0x02800280}, // PHY_CLK_WRDQ5_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_2:RW+:0:11:=0x0280 + { 0x0000053D, 0x02800280}, // PHY_CLK_WRDQ7_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_2:RW+:0:11:=0x0280 + { 0x0000053E, 0x00000280}, // PHY_CLK_WRDQS_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_2:RW+:0:11:=0x0280 + { 0x0000053F, 0x00000000}, // PHY_RDDQ1_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_2:RW+:0:10:=0x0000 + { 0x00000540, 0x00000000}, // PHY_RDDQ3_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_2:RW+:0:10:=0x0000 + { 0x00000541, 0x00000000}, // PHY_RDDQ5_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_2:RW+:0:10:=0x0000 + { 0x00000542, 0x00000000}, // PHY_RDDQ7_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_2:RW+:0:10:=0x0000 + { 0x00000543, 0x00A000A0}, // PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2:RW+:16:10:=0x00A0 PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + { 0x00000544, 0x00A000A0}, // PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2:RW+:16:10:=0x00A0 PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + { 0x00000545, 0x00A000A0}, // PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2:RW+:16:10:=0x00A0 PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + { 0x00000546, 0x00A000A0}, // PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2:RW+:16:10:=0x00A0 PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + { 0x00000547, 0x00A000A0}, // PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2:RW+:16:10:=0x00A0 PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + { 0x00000548, 0x00A000A0}, // PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2:RW+:16:10:=0x00A0 PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + { 0x00000549, 0x00A000A0}, // PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2:RW+:16:10:=0x00A0 PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + { 0x0000054A, 0x00A000A0}, // PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2:RW+:16:10:=0x00A0 PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + { 0x0000054B, 0x00A000A0}, // PHY_RDDQS_DM_FALL_SLAVE_DELAY_2:RW+:16:10:=0x00A0 PHY_RDDQS_DM_RISE_SLAVE_DELAY_2:RW+:0:10:=0x00a0 + { 0x0000054C, 0x00040109}, // PHY_WRITE_PATH_LAT_ADD_2:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_2:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_2:RW+:0:10:=0x0109 + { 0x0000054D, 0x000001D0}, // PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2:RW+:16:10:=0x0000 PHY_WRLVL_DELAY_EARLY_THRESHOLD_2:RW+:0:10:=0x01d0 + { 0x0000054E, 0x03000000}, // PHY_GTLVL_LAT_ADJ_START_2:RW+:24:4:=0x07 PHY_GTLVL_RDDQS_SLV_DLY_START_2:RW+:8:10:=0x0000 PHY_WRLVL_EARLY_FORCE_ZERO_2:RW+:0:1:=0x00 + { 0x0000054F, 0x00000200}, // PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2:RW+:16:10:=0x0000 PHY_WDQLVL_DQDM_SLV_DLY_START_2:RW+:0:11:=0x0200 +// { 0x00000550, 0x41315141}, // PHY_DQS_OE_TIMING_2:RW+:24:8:=0x41 PHY_DQ_TSEL_WR_TIMING_2:RW+:16:8:=0x31 PHY_DQ_TSEL_RD_TIMING_2:RW+:8:8:=0x51 PHY_DQ_OE_TIMING_2:RW+:0:8:=0x41 + { 0x00000550, 0x41415141}, // PHY_DQS_OE_TIMING_2:RW+:24:8:=0x41 PHY_DQ_TSEL_WR_TIMING_2:RW+:16:8:=0x31 PHY_DQ_TSEL_RD_TIMING_2:RW+:8:8:=0x51 PHY_DQ_OE_TIMING_2:RW+:0:8:=0x41 +// { 0x00000551, 0xC0013150}, // PHY_DQ_IE_TIMING_2:RW+:24:8:=0xc0 PHY_PER_CS_TRAINING_EN_2:RW+:16:1:=0x01 PHY_DQS_TSEL_WR_TIMING_2:RW+:8:8:=0x31 PHY_DQS_TSEL_RD_TIMING_2:RW+:0:8:=0x50 + { 0x00000551, 0xC0014150}, // PHY_DQ_IE_TIMING_2:RW+:24:8:=0xc0 PHY_PER_CS_TRAINING_EN_2:RW+:16:1:=0x01 PHY_DQS_TSEL_WR_TIMING_2:RW+:8:8:=0x31 PHY_DQS_TSEL_RD_TIMING_2:RW+:0:8:=0x50 + { 0x00000552, 0x0E0000C0}, // PHY_RDDATA_EN_DLY_2:RW+:24:4:=0x0e PHY_IE_MODE_2:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_2:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_2:RW+:0:8:=0xc0 + { 0x00000553, 0x0010000C}, // PHY_MASTER_DELAY_START_2:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_2:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_2:RW+:0:4:=0x0c + { 0x00000554, 0x0C064208}, // PHY_WRLVL_DLY_STEP_2:RW+:24:4:=0x0c PHY_RPTR_UPDATE_2:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_2:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_2:RW+:0:6:=0x08 + { 0x00000555, 0x000F0C18}, // PHY_GTLVL_RESP_WAIT_CNT_2:RW+:16:5:=0x0f PHY_GTLVL_DLY_STEP_2:RW+:8:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_2:RW+:0:5:=0x18 + { 0x00000556, 0x01000140}, // PHY_GTLVL_FINAL_STEP_2:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_2:RW+:0:10:=0x0140 + { 0x00000557, 0x00000C20}, // PHY_RDLVL_DLY_STEP_2:RW+:8:4:=0x0c PHY_WDQLVL_DLY_STEP_2:RW+:0:8:=0x20 + { 0x00000558, 0x00000000}, // + { 0x00000559, 0x00000000}, // + { 0x0000055A, 0x00000000}, // + { 0x0000055B, 0x00000000}, // + { 0x0000055C, 0x00000000}, // + { 0x0000055D, 0x00000000}, // + { 0x0000055E, 0x00000000}, // + { 0x0000055F, 0x00000000}, // + { 0x00000560, 0x00000000}, // + { 0x00000561, 0x00000000}, // + { 0x00000562, 0x00000000}, // + { 0x00000563, 0x00000000}, // + { 0x00000564, 0x00000000}, // + { 0x00000565, 0x00000000}, // + { 0x00000566, 0x00000000}, // + { 0x00000567, 0x00000000}, // + { 0x00000568, 0x00000000}, // + { 0x00000569, 0x00000000}, // + { 0x0000056A, 0x00000000}, // + { 0x0000056B, 0x00000000}, // + { 0x0000056C, 0x00000000}, // + { 0x0000056D, 0x00000000}, // + { 0x0000056E, 0x00000000}, // + { 0x0000056F, 0x00000000}, // + { 0x00000570, 0x00000000}, // + { 0x00000571, 0x00000000}, // + { 0x00000572, 0x00000000}, // + { 0x00000573, 0x00000000}, // + { 0x00000574, 0x00000000}, // + { 0x00000575, 0x00000000}, // + { 0x00000576, 0x00000000}, // + { 0x00000577, 0x00000000}, // + { 0x00000578, 0x00000000}, // + { 0x00000579, 0x00000000}, // + { 0x0000057A, 0x00000000}, // + { 0x0000057B, 0x00000000}, // + { 0x0000057C, 0x00000000}, // + { 0x0000057D, 0x00000000}, // + { 0x0000057E, 0x00000000}, // + { 0x0000057F, 0x00000000}, // + { 0x00000580, 0x000004F0}, // PHY_SW_WRDQ0_SHIFT_3:RW:24:5:=0x00 PHY_CLK_BYPASS_OVERRIDE_3:RW:16:1:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_3:RW:0:11:=0x04f0 + { 0x00000581, 0x00000000}, // PHY_SW_WRDQ4_SHIFT_3:RW:24:5:=0x00 PHY_SW_WRDQ3_SHIFT_3:RW:16:5:=0x00 PHY_SW_WRDQ2_SHIFT_3:RW:8:5:=0x00 PHY_SW_WRDQ1_SHIFT_3:RW:0:5:=0x00 + { 0x00000582, 0x00000000}, // PHY_SW_WRDM_SHIFT_3:RW:24:5:=0x00 PHY_SW_WRDQ7_SHIFT_3:RW:16:5:=0x00 PHY_SW_WRDQ6_SHIFT_3:RW:8:5:=0x00 PHY_SW_WRDQ5_SHIFT_3:RW:0:5:=0x00 +// { 0x00000583, 0x00000100}, // PHY_DQ_TSEL_ENABLE_3:RW:8:3:=0x01 PHY_SW_WRDQS_SHIFT_3:RW:0:4:=0x00 + { 0x00000583, 0x00000300}, // PHY_DQ_TSEL_ENABLE_3:RW:8:3:=0x01 PHY_SW_WRDQS_SHIFT_3:RW:0:4:=0x00 +// { 0x00000584, 0x01CC6E0C}, // PHY_DQS_TSEL_ENABLE_3:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_3:RW:0:24:=0x665555 + { 0x00000584, 0x030E6E0E}, // PHY_DQS_TSEL_ENABLE_3:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_3:RW:0:24:=0x665555 +// { 0x00000584, 0x036E6E0E}, // PHY_DQS_TSEL_ENABLE_3:RW:24:3:=0x01 PHY_DQ_TSEL_SELECT_3:RW:0:24:=0x665555 +// { 0x00000585, 0x02CC6E0C}, // PHY_TWO_CYC_PREAMBLE_3:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_3:RW:0:24:=0x665555 + { 0x00000585, 0x020E6E0E}, // PHY_TWO_CYC_PREAMBLE_3:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_3:RW:0:24:=0x665555 +// { 0x00000585, 0x026E6E0E}, // PHY_TWO_CYC_PREAMBLE_3:RW:24:2:=0x02 PHY_DQS_TSEL_SELECT_3:RW:0:24:=0x665555 + { 0x00000586, 0x00010F00}, // PHY_PER_CS_TRAINING_INDEX_3:RW:24:1:=0x00 PHY_PER_CS_TRAINING_MULTICAST_EN_3:RW_D:16:1:=0x01 PHY_PER_RANK_CS_MAP_3:RW:8:2:=0x0f PHY_DBI_MODE_3:RW:0:1:=0x00 + { 0x00000587, 0x04000100}, // PHY_LP4_BOOT_RPTR_UPDATE_3:RW:24:4:=0x04 PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3:RW:16:4:=0x00 PHY_LP4_BOOT_RDDATA_EN_DLY_3:RW:8:4:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3:RW:0:2:=0x00 + { 0x00000588, 0x00000133}, // PHY_LPBK_CONTROL_3:RW:24:7:=0x00 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3:RW:16:4:=0x00 PHY_LP4_BOOT_RDDQS_GATE_SLAVE_DELAY_3:RW:0:10:=0x0133 + { 0x00000589, 0x000700C0}, // SC_PHY_SNAP_OBS_REGS_3:WR:24:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_3:RW:16:4:=0x07 PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3:RW:0:10:=0x00c0 + { 0x0000058A, 0x00CC0201}, // PHY_GATE_SMPL1_SLAVE_DELAY_3:RW:16:9:=0x00cc PHY_LPDDR_TYPE_3:RW:8:2:=0x02 PHY_LPDDR_3:RW:0:1:=0x01 + { 0x0000058B, 0x00030066}, // ON_FLY_GATE_ADJUST_EN_3:RW:16:2:=0x03 PHY_GATE_SMPL2_SLAVE_DELAY_3:RW:0:9:=0x0066 + { 0x0000058C, 0x00000000}, // PHY_GATE_TRACKING_OBS_3:RD:0:32:=0x00000000 + { 0x0000058D, 0x00000000}, // PHY_LP4_PST_AMBLE_3:RW:0:1:=0x00 + { 0x0000058E, 0x00000000}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 + { 0x0000058F, 0x00000000}, // PHY_LP4_RDLVL_PATT9_3:RW:0:32:=0x00000000 + { 0x00000590, 0x00000000}, // PHY_LP4_RDLVL_PATT10_3:RW:0:32:=0x00000000 + { 0x00000591, 0x00000000}, // PHY_LP4_RDLVL_PATT11_3:RW:0:32:=0x00000000 + { 0x00000592, 0x00000000}, // PHY_RDDQ_ENC_OBS_SELECT_3:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_3:RW:16:3:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_3:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_3:RW:0:3:=0x00 + { 0x00000593, 0x00000000}, // PHY_FIFO_PTR_OBS_SELECT_3:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_3:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_3:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_3:RW:0:4:=0x00 + { 0x00000594, 0x04080000}, // PHY_WRLVL_UPDT_WAIT_CNT_3:RW:24:4:=0x04 PHY_WRLVL_CAPTURE_CNT_3:RW:16:6:=0x08 SC_PHY_LVL_DEBUG_CONT_3:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_3:RW:0:1:=0x00 + { 0x00000595, 0x04080a04}, // PHY_RDLVL_UPDT_WAIT_CNT_3:RW:24:4:=0x04 PHY_RDLVL_CAPTURE_CNT_3:RW:16:6:=0x08 PHY_GTLVL_UPDT_WAIT_CNT_3:RW:8:4:=0x04 PHY_GTLVL_CAPTURE_CNT_3:RW:0:6:=0x00 + { 0x00000596, 0x00000000}, // PHY_RDLVL_DATA_MASK_3:RW:16:8:=0x00 PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3:RW:8:5:=0x00 PHY_RDLVL_OP_MODE_3:RW:0:2:=0x00 + { 0x00000597, 0x32103210}, // PHY_RDLVL_DATA_SWIZZLE_3:RW:0:32:=0x32103210 + { 0x00000598, 0x00C00208}, // PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3:RW:16:11:=0x00C0 PHY_WDQLVL_PATT_3:RW:8:3:=0x07 PHY_WDQLVL_BURST_CNT_3:RW:0:6:=0x08 + { 0x00000599, 0x0001000C}, // PHY_WDQLVL_CLR_PREV_RESULTS_3:WR:24:1:=0x00 PHY_WDQLVL_QTR_DLY_STEP_3:RW:16:4:=0x01 PHY_WDQLVL_DQDM_OBS_SELECT_3:RW:8:4:=0x00 PHY_WDQLVL_UPDT_WAIT_CNT_3:RW:0:4:=0x0c + { 0x0000059A, 0x00000100}, // PHY_WDQLVL_DATADM_MASK_3:RW:0:9:=0x0100 + { 0x0000059B, 0x55555555}, // PHY_USER_PATT0_3:RW:0:32:=0x55555555 + { 0x0000059C, 0xAAAAAAAA}, // PHY_USER_PATT1_3:RW:0:32:=0xAAAAAAAA + { 0x0000059D, 0x55555555}, // PHY_USER_PATT2_3:RW:0:32:=0x55555555 + { 0x0000059E, 0xAAAAAAAA}, // PHY_USER_PATT3_3:RW:0:32:=0xAAAAAAAA + { 0x0000059F, 0x00005555}, // PHY_USER_PATT4_3:RW:0:16:=0x5555 + { 0x000005A0, 0x76543210}, // PHY_DQ_SWIZZLING_3:RW:0:32:=0x76543210 + { 0x000005A1, 0x00000000}, // PHY_FIFO_PTR_OBS_3:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_3:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_3:RW:0:1:=0x00 + { 0x000005A2, 0x00000000}, // PHY_LPBK_RESULT_OBS_3:RD:0:32:=0x00000000 + { 0x000005A3, 0x00000000}, // PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3:RD:24:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_3:RD:16:6:=0x00 PHY_MASTER_DLY_LOCK_OBS_3:RD:0:10:=0x0000 + { 0x000005A4, 0x00000000}, // PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3:RD:16:10:=0x0000 PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3:RD:8:8:=0x00 PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3:RD:0:8:=0x00 + { 0x000005A5, 0x00000000}, // PHY_WR_SHIFT_OBS_3:RD:24:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_3:RD:16:8:=0x00 PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3:RD:8:8:=0x00 PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3:RD:0:7:=0x00 + { 0x000005A6, 0x00000000}, // PHY_WRLVL_HARD1_DELAY_OBS_3:RD:16:10:=0x0000 PHY_WRLVL_HARD0_DELAY_OBS_3:RD:0:10:=0x0000 + { 0x000005A7, 0x00000000}, // PHY_WRLVL_STATUS_OBS_3:RD:0:17:=0x000000 + { 0x000005A8, 0x00000000}, // PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3:RD:16:9:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3:RD:0:9:=0x0000 + { 0x000005A9, 0x00000000}, // PHY_GTLVL_HARD0_DELAY_OBS_3:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_3:RD:0:16:=0x0000 + { 0x000005AA, 0x00000000}, // PHY_GTLVL_STATUS_OBS_3:RD:16:12:=0x0000 PHY_GTLVL_HARD1_DELAY_OBS_3:RD:0:14:=0x0000 + { 0x000005AB, 0x00000000}, // PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3:RD:0:10:=0x0000 + { 0x000005AC, 0x00000000}, // PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3:RD:0:2:=0x00 + { 0x000005AD, 0x00000000}, // PHY_RDLVL_STATUS_OBS_3:RD:0:32:=0x00000000 + { 0x000005AE, 0x00000000}, // PHY_WDQLVL_DQDM_TE_DLY_OBS_3:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_3:RD:0:11:=0x0000 + { 0x000005AF, 0x00000000}, // PHY_WDQLVL_STATUS_OBS_3:RD:0:32:=0x00000000 + { 0x000005B0, 0x00000000}, // PHY_DDL_MODE_3:RW:0:18:=0x000000 + { 0x000005B1, 0x00000000}, // PHY_DDL_TEST_OBS_3:RD:0:32:=0x00000000 + { 0x000005B2, 0x00000000}, // PHY_DDL_TEST_MSTR_DLY_OBS_3:RD:0:32:=0x00000000 + { 0x000005B3, 0x00200000}, // PHY_RX_CAL_SAMPLE_WAIT_3:RW:16:8:=0x20 PHY_RX_CAL_OVERRIDE_3:RW:8:1:=0x00 SC_PHY_RX_CAL_START_3:WR:0:1:=0x00 + { 0x000005B4, 0x00000000}, // PHY_RX_CAL_DQ1_3:RW+:16:12:=0x0000 PHY_RX_CAL_DQ0_3:RW+:0:12:=0x0000 + { 0x000005B5, 0x00000000}, // PHY_RX_CAL_DQ3_3:RW+:16:12:=0x0000 PHY_RX_CAL_DQ2_3:RW+:0:12:=0x0000 + { 0x000005B6, 0x00000000}, // PHY_RX_CAL_DQ5_3:RW+:16:12:=0x0000 PHY_RX_CAL_DQ4_3:RW+:0:12:=0x0000 + { 0x000005B7, 0x00000000}, // PHY_RX_CAL_DQ7_3:RW+:16:12:=0x0000 PHY_RX_CAL_DQ6_3:RW+:0:12:=0x0000 + { 0x000005B8, 0x00000000}, // PHY_RX_CAL_DQS_3:RW+:16:12:=0x0000 PHY_RX_CAL_DM_3:RW+:0:12:=0x0000 + { 0x000005B9, 0x00000000}, // PHY_RX_CAL_OBS_3:RD:16:11:=0x0000 PHY_RX_CAL_FDBK_3:RW+:0:12:=0x0000 + + { 0x000005BA, 0x02800280}, // PHY_CLK_WRDQ1_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_3:RW+:0:11:=0x0280 + { 0x000005BB, 0x02800280}, // PHY_CLK_WRDQ3_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_3:RW+:0:11:=0x0280 + { 0x000005BC, 0x02800280}, // PHY_CLK_WRDQ5_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_3:RW+:0:11:=0x0280 + { 0x000005BD, 0x02800280}, // PHY_CLK_WRDQ7_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_3:RW+:0:11:=0x0280 + { 0x000005BE, 0x00000280}, // PHY_CLK_WRDQS_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_3:RW+:0:11:=0x0280 + + { 0x000005BF, 0x00000000}, // PHY_RDDQ1_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_3:RW+:0:10:=0x0000 + { 0x000005C0, 0x00000000}, // PHY_RDDQ3_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_3:RW+:0:10:=0x0000 + { 0x000005C1, 0x00000000}, // PHY_RDDQ5_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_3:RW+:0:10:=0x0000 + { 0x000005C2, 0x00000000}, // PHY_RDDQ7_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_3:RW+:0:10:=0x0000 + { 0x000005C3, 0x00A000A0}, // PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3:RW+:16:10:=0x00A0 PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + { 0x000005C4, 0x00A000A0}, // PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3:RW+:16:10:=0x00A0 PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + { 0x000005C5, 0x00A000A0}, // PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3:RW+:16:10:=0x00A0 PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + { 0x000005C6, 0x00A000A0}, // PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3:RW+:16:10:=0x00A0 PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + { 0x000005C7, 0x00A000A0}, // PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3:RW+:16:10:=0x00A0 PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + { 0x000005C8, 0x00A000A0}, // PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3:RW+:16:10:=0x00A0 PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + { 0x000005C9, 0x00A000A0}, // PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3:RW+:16:10:=0x00A0 PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + { 0x000005CA, 0x00A000A0}, // PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3:RW+:16:10:=0x00A0 PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + { 0x000005CB, 0x00A000A0}, // PHY_RDDQS_DM_FALL_SLAVE_DELAY_3:RW+:16:10:=0x00A0 PHY_RDDQS_DM_RISE_SLAVE_DELAY_3:RW+:0:10:=0x00a0 + { 0x000005CC, 0x00040109}, // PHY_WRITE_PATH_LAT_ADD_3:RW+:24:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_3:RW+:16:4:=0x04 PHY_RDDQS_GATE_SLAVE_DELAY_3:RW+:0:10:=0x0109 + { 0x000005CD, 0x000001D0}, // PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3:RW+:16:10:=0x0000 PHY_WRLVL_DELAY_EARLY_THRESHOLD_3:RW+:0:10:=0x01d0 + { 0x000005CE, 0x03000000}, // PHY_GTLVL_LAT_ADJ_START_3:RW+:24:4:=0x07 PHY_GTLVL_RDDQS_SLV_DLY_START_3:RW+:8:10:=0x0000 PHY_WRLVL_EARLY_FORCE_ZERO_3:RW+:0:1:=0x00 + { 0x000005CF, 0x00000200}, // PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3:RW+:16:10:=0x0000 PHY_WDQLVL_DQDM_SLV_DLY_START_3:RW+:0:11:=0x0200 +// { 0x000005D0, 0x41315141}, // PHY_DQS_OE_TIMING_3:RW+:24:8:=0x41 PHY_DQ_TSEL_WR_TIMING_3:RW+:16:8:=0x31 PHY_DQ_TSEL_RD_TIMING_3:RW+:8:8:=0x51 PHY_DQ_OE_TIMING_3:RW+:0:8:=0x41 + { 0x000005D0, 0x41415141}, // PHY_DQS_OE_TIMING_3:RW+:24:8:=0x41 PHY_DQ_TSEL_WR_TIMING_3:RW+:16:8:=0x31 PHY_DQ_TSEL_RD_TIMING_3:RW+:8:8:=0x51 PHY_DQ_OE_TIMING_3:RW+:0:8:=0x41 +// { 0x000005D1, 0xC0013150}, // PHY_DQ_IE_TIMING_3:RW+:24:8:=0xc0 PHY_PER_CS_TRAINING_EN_3:RW+:16:1:=0x01 PHY_DQS_TSEL_WR_TIMING_3:RW+:8:8:=0x31 PHY_DQS_TSEL_RD_TIMING_3:RW+:0:8:=0x50 + { 0x000005D1, 0xC0014150}, // PHY_DQ_IE_TIMING_3:RW+:24:8:=0xc0 PHY_PER_CS_TRAINING_EN_3:RW+:16:1:=0x01 PHY_DQS_TSEL_WR_TIMING_3:RW+:8:8:=0x31 PHY_DQS_TSEL_RD_TIMING_3:RW+:0:8:=0x50 + { 0x000005D2, 0x0E0000C0}, // PHY_RDDATA_EN_DLY_3:RW+:24:4:=0x0e PHY_IE_MODE_3:RW+:16:2:=0x00 PHY_RDDATA_EN_IE_DLY_3:RW+:8:2:=0x00 PHY_DQS_IE_TIMING_3:RW+:0:8:=0xc0 + { 0x000005D3, 0x0010000C}, // PHY_MASTER_DELAY_START_3:RW+:16:10:=0x0010 PHY_SW_MASTER_MODE_3:RW+:8:4:=0x00 PHY_RDDATA_EN_TSEL_DLY_3:RW+:0:4:=0x0c + { 0x000005D4, 0x0C064208}, // PHY_WRLVL_DLY_STEP_3:RW+:24:4:=0x0c PHY_RPTR_UPDATE_3:RW+:16:4:=0x06 PHY_MASTER_DELAY_WAIT_3:RW+:8:8:=0x42 PHY_MASTER_DELAY_STEP_3:RW+:0:6:=0x08 + { 0x000005D5, 0x000F0C18}, // PHY_GTLVL_RESP_WAIT_CNT_3:RW+:16:5:=0x0f PHY_GTLVL_DLY_STEP_3:RW+:8:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_3:RW+:0:5:=0x18 + { 0x000005D6, 0x01000140}, // PHY_GTLVL_FINAL_STEP_3:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_3:RW+:0:10:=0x0140 + { 0x000005D7, 0x00000C20}, // PHY_RDLVL_DLY_STEP_3:RW+:8:4:=0x0c PHY_WDQLVL_DLY_STEP_3:RW+:0:8:=0x20 + { 0x000005D8, 0x00000000}, // + { 0x000005D9, 0x00000000}, // + { 0x000005DA, 0x00000000}, // + { 0x000005DB, 0x00000000}, // + { 0x000005DC, 0x00000000}, // + { 0x000005DD, 0x00000000}, // + { 0x000005DE, 0x00000000}, // + { 0x000005DF, 0x00000000}, // + { 0x000005E0, 0x00000000}, // + { 0x000005E1, 0x00000000}, // + { 0x000005E2, 0x00000000}, // + { 0x000005E3, 0x00000000}, // + { 0x000005E4, 0x00000000}, // + { 0x000005E5, 0x00000000}, // + { 0x000005E6, 0x00000000}, // + { 0x000005E7, 0x00000000}, // + { 0x000005E8, 0x00000000}, // + { 0x000005E9, 0x00000000}, // + { 0x000005EA, 0x00000000}, // + { 0x000005EB, 0x00000000}, // + { 0x000005EC, 0x00000000}, // + { 0x000005ED, 0x00000000}, // + { 0x000005EE, 0x00000000}, // + { 0x000005EF, 0x00000000}, // + { 0x000005F0, 0x00000000}, // + { 0x000005F1, 0x00000000}, // + { 0x000005F2, 0x00000000}, // + { 0x000005F3, 0x00000000}, // + { 0x000005F4, 0x00000000}, // + { 0x000005F5, 0x00000000}, // + { 0x000005F6, 0x00000000}, // + { 0x000005F7, 0x00000000}, // + { 0x000005F8, 0x00000000}, // + { 0x000005F9, 0x00000000}, // + { 0x000005FA, 0x00000000}, // + { 0x000005FB, 0x00000000}, // + { 0x000005FC, 0x00000000}, // + { 0x000005FD, 0x00000000}, // + { 0x000005FE, 0x00000000}, // + { 0x000005FF, 0x00000000}, // + { 0x00000600, 0x00000000}, // PHY_ADR3_SW_WRADDR_SHIFT_0:RW+:24:5:=0x00 PHY_ADR2_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR1_SW_WRADDR_SHIFT_0:RW+:8:5:=0x00 PHY_ADR0_SW_WRADDR_SHIFT_0:RW+:0:5:=0x00 + { 0x00000601, 0x00000000}, // PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0:RW:16:11:=0x0000 PHY_ADR5_SW_WRADDR_SHIFT_0:RW+:8:5:=0x00 PHY_ADR4_SW_WRADDR_SHIFT_0:RW+:0:5:=0x00 + { 0x00000602, 0x00000000}, // SC_PHY_ADR_MANUAL_CLEAR_0:WR:8:3:=0x00 PHY_ADR_CLK_BYPASS_OVERRIDE_0:RW:0:1:=0x00 + { 0x00000603, 0x00000000}, // PHY_ADR_LPBK_RESULT_OBS_0:RD:0:32:=0x00000000 + { 0x00000604, 0x00000000}, // PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0:RW:24:3:=0x00 PHY_ADR_MASTER_DLY_LOCK_OBS_0:RD:8:10:=0x0000 PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0:RW:0:3:=0x00 + { 0x00000605, 0x00000000}, // PHY_ADR_LPBK_CONTROL_0:RW:24:6:=0x00 PHY_ADR_TSEL_ENABLE_0:RW:16:1:=0x00 SC_PHY_ADR_SNAP_OBS_REGS_0:WR:8:1:=0x00 PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0:RW:0:3:=0x00 + { 0x00000606, 0x00000002}, // PHY_ADR_IE_MODE_0:RW:16:1:=0x00 PHY_ADR_WRADDR_SHIFT_OBS_0:RD:8:3:=0x00 PHY_ADR_TYPE_0:RW:0:2:=0x02 + { 0x00000607, 0x00000000}, // PHY_ADR_DDL_MODE_0:RW:0:15:=0x0000 + { 0x00000608, 0x00000000}, // PHY_ADR_DDL_TEST_OBS_0:RD:0:32:=0x00000000 + { 0x00000609, 0x00000000}, // PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0:RD:0:32:=0x00000000 + { 0x0000060A, 0x00400320}, // PHY_ADR_CALVL_COARSE_DLY_0:RW:16:11:=0x0040 PHY_ADR_CALVL_START_0:RW:0:11:=0x0320 + { 0x0000060B, 0x00000040}, // PHY_ADR_CALVL_QTR_0:RW:0:11:=0x0040 + { 0x0000060C, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_0_0:RW:0:24:=0xdcba98 + { 0x0000060D, 0x00000000}, // PHY_ADR_CALVL_SWIZZLE1_0_0:RW:0:24:=0x000000 + { 0x0000060E, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_1_0:RW:0:24:=0xdcba98 + { 0x0000060F, 0x01000000}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 + { 0x00000610, 0x00020010}, // PHY_ADR_CALVL_RESP_WAIT_CNT_0:RW:24:4:=0x00 PHY_ADR_CALVL_CAPTURE_CNT_0:RW:16:4:=0x02 PHY_ADR_CALVL_NUM_PATTERNS_0:RW:8:2:=0x00 PHY_ADR_CALVL_RANK_CTRL_0:RW:0:5:=0x10 + { 0x00000611, 0x00000000}, // PHY_ADR_CALVL_OBS_SELECT_0:RW:24:3:=0x00 SC_PHY_ADR_CALVL_ERROR_CLR_0:WR:16:1:=0x00 SC_PHY_ADR_CALVL_DEBUG_CONT_0:WR:8:1:=0x00 PHY_ADR_CALVL_DEBUG_MODE_0:RW:0:1:=0x00 + { 0x00000612, 0x00000000}, // PHY_ADR_CALVL_OBS0_0:RD:0:32:=0x00000000 + { 0x00000613, 0x00000000}, // PHY_ADR_CALVL_OBS1_0:RD:0:32:=0x00000000 + { 0x00000614, 0x00002A01}, // PHY_ADR_CALVL_FG_0_0:RW:8:20:=0x00002A PHY_ADR_CALVL_RESULT_0:RW:0:1:=0x01 + { 0x00000615, 0x00000015}, // PHY_ADR_CALVL_BG_0_0:RW:0:20:=0x000015 + { 0x00000616, 0x00000015}, // PHY_ADR_CALVL_FG_1_0:RW:0:20:=0x000015 + { 0x00000617, 0x0000002A}, // PHY_ADR_CALVL_BG_1_0:RW:0:20:=0x00002a + { 0x00000618, 0x00000033}, // PHY_ADR_CALVL_FG_2_0:RW:0:20:=0x000033 + { 0x00000619, 0x0000000C}, // PHY_ADR_CALVL_BG_2_0:RW:0:20:=0x00000c + { 0x0000061A, 0x0000000C}, // PHY_ADR_CALVL_FG_3_0:RW:0:20:=0x00000c + { 0x0000061B, 0x00000033}, // PHY_ADR_CALVL_BG_3_0:RW:0:20:=0x000033 + { 0x0000061C, 0x00543210}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 + { 0x0000061D, 0x003F0000}, // PHY_ADR_SEG_MASK_0:RW:24:6:=0x00 PHY_ADR_BIT_MASK_0:RW:16:6:=0x3f PHY_ADR_LP4_BOOT_SLV_DELAY_0:RW:0:10:=0x0000 + { 0x0000061E, 0x0000003F}, // PHY_ADR_CALVL_TRAIN_MASK_0:RW:0:6:=0x3f +// { 0x0000061F, 0x0003006E}, // PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x55 +// { 0x00000620, 0x03000300}, // PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 +// { 0x00000621, 0x03000300}, // PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 +// { 0x00000622, 0x00000300}, // PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 + { 0x0000061F, 0x0002c06E}, // PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x55 + { 0x00000620, 0x02c002c0}, // PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 + { 0x00000621, 0x02c002c0}, // PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 + { 0x00000622, 0x000002c0}, // PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 + { 0x00000623, 0x42080010}, // PHY_ADR_MASTER_DELAY_WAIT_0:RW+:24:8:=0x42 PHY_ADR_MASTER_DELAY_STEP_0:RW+:16:6:=0x08 PHY_ADR_MASTER_DELAY_START_0:RW+:0:10:=0x0010 + { 0x00000624, 0x00000003}, // PHY_ADR_CALVL_DLY_STEP_0:RW+:0:4:=0x03 + { 0x00000625, 0x00000000}, // + { 0x00000626, 0x00000000}, // + { 0x00000627, 0x00000000}, // + { 0x00000628, 0x00000000}, // + { 0x00000629, 0x00000000}, // + { 0x0000062A, 0x00000000}, // + { 0x0000062B, 0x00000000}, // + { 0x0000062C, 0x00000000}, // + { 0x0000062D, 0x00000000}, // + { 0x0000062E, 0x00000000}, // + { 0x0000062F, 0x00000000}, // + { 0x00000630, 0x00000000}, // + { 0x00000631, 0x00000000}, // + { 0x00000632, 0x00000000}, // + { 0x00000633, 0x00000000}, // + { 0x00000634, 0x00000000}, // + { 0x00000635, 0x00000000}, // + { 0x00000636, 0x00000000}, // + { 0x00000637, 0x00000000}, // + { 0x00000638, 0x00000000}, // + { 0x00000639, 0x00000000}, // + { 0x0000063A, 0x00000000}, // + { 0x0000063B, 0x00000000}, // + { 0x0000063C, 0x00000000}, // + { 0x0000063D, 0x00000000}, // + { 0x0000063E, 0x00000000}, // + { 0x0000063F, 0x00000000}, // + { 0x00000640, 0x00000000}, // + { 0x00000641, 0x00000000}, // + { 0x00000642, 0x00000000}, // + { 0x00000643, 0x00000000}, // + { 0x00000644, 0x00000000}, // + { 0x00000645, 0x00000000}, // + { 0x00000646, 0x00000000}, // + { 0x00000647, 0x00000000}, // + { 0x00000648, 0x00000000}, // + { 0x00000649, 0x00000000}, // + { 0x0000064A, 0x00000000}, // + { 0x0000064B, 0x00000000}, // + { 0x0000064C, 0x00000000}, // + { 0x0000064D, 0x00000000}, // + { 0x0000064E, 0x00000000}, // + { 0x0000064F, 0x00000000}, // + { 0x00000650, 0x00000000}, // + { 0x00000651, 0x00000000}, // + { 0x00000652, 0x00000000}, // + { 0x00000653, 0x00000000}, // + { 0x00000654, 0x00000000}, // + { 0x00000655, 0x00000000}, // + { 0x00000656, 0x00000000}, // + { 0x00000657, 0x00000000}, // + { 0x00000658, 0x00000000}, // + { 0x00000659, 0x00000000}, // + { 0x0000065A, 0x00000000}, // + { 0x0000065B, 0x00000000}, // + { 0x0000065C, 0x00000000}, // + { 0x0000065D, 0x00000000}, // + { 0x0000065E, 0x00000000}, // + { 0x0000065F, 0x00000000}, // + { 0x00000660, 0x00000000}, // + { 0x00000661, 0x00000000}, // + { 0x00000662, 0x00000000}, // + { 0x00000663, 0x00000000}, // + { 0x00000664, 0x00000000}, // + { 0x00000665, 0x00000000}, // + { 0x00000666, 0x00000000}, // + { 0x00000667, 0x00000000}, // + { 0x00000668, 0x00000000}, // + { 0x00000669, 0x00000000}, // + { 0x0000066A, 0x00000000}, // + { 0x0000066B, 0x00000000}, // + { 0x0000066C, 0x00000000}, // + { 0x0000066D, 0x00000000}, // + { 0x0000066E, 0x00000000}, // + { 0x0000066F, 0x00000000}, // + { 0x00000670, 0x00000000}, // + { 0x00000671, 0x00000000}, // + { 0x00000672, 0x00000000}, // + { 0x00000673, 0x00000000}, // + { 0x00000674, 0x00000000}, // + { 0x00000675, 0x00000000}, // + { 0x00000676, 0x00000000}, // + { 0x00000677, 0x00000000}, // + { 0x00000678, 0x00000000}, // + { 0x00000679, 0x00000000}, // + { 0x0000067A, 0x00000000}, // + { 0x0000067B, 0x00000000}, // + { 0x0000067C, 0x00000000}, // + { 0x0000067D, 0x00000000}, // + { 0x0000067E, 0x00000000}, // + { 0x0000067F, 0x00000000}, // + { 0x00000680, 0x04040404}, // PHY_ADR3_SW_WRADDR_SHIFT_1:RW+:24:5:=0x04 PHY_ADR2_SW_WRADDR_SHIFT_1:RW+:16:5:=0x04 PHY_ADR1_SW_WRADDR_SHIFT_1:RW+:8:5:=0x04 PHY_ADR0_SW_WRADDR_SHIFT_1:RW+:0:5:=0x04 + { 0x00000681, 0x00000404}, // PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1:RW:16:11:=0x0000 PHY_ADR5_SW_WRADDR_SHIFT_1:RW+:8:5:=0x04 PHY_ADR4_SW_WRADDR_SHIFT_1:RW+:0:5:=0x04 + { 0x00000682, 0x00000000}, // SC_PHY_ADR_MANUAL_CLEAR_1:WR:8:3:=0x00 PHY_ADR_CLK_BYPASS_OVERRIDE_1:RW:0:1:=0x00 + { 0x00000683, 0x00000000}, // PHY_ADR_LPBK_RESULT_OBS_1:RD:0:32:=0x00000000 + { 0x00000684, 0x00000000}, // PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1:RW:24:3:=0x00 PHY_ADR_MASTER_DLY_LOCK_OBS_1:RD:8:10:=0x0000 PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1:RW:0:3:=0x00 + { 0x00000685, 0x00000000}, // PHY_ADR_LPBK_CONTROL_1:RW:24:6:=0x00 PHY_ADR_TSEL_ENABLE_1:RW:16:1:=0x00 SC_PHY_ADR_SNAP_OBS_REGS_1:WR:8:1:=0x00 PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1:RW:0:3:=0x00 + { 0x00000686, 0x00000002}, // PHY_ADR_IE_MODE_1:RW:16:1:=0x00 PHY_ADR_WRADDR_SHIFT_OBS_1:RD:8:3:=0x00 PHY_ADR_TYPE_1:RW:0:2:=0x02 + { 0x00000687, 0x00000000}, // PHY_ADR_DDL_MODE_1:RW:0:15:=0x0000 + { 0x00000688, 0x00000000}, // PHY_ADR_DDL_TEST_OBS_1:RD:0:32:=0x00000000 + { 0x00000689, 0x00000000}, // PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1:RD:0:32:=0x00000000 + { 0x0000068A, 0x00400320}, // PHY_ADR_CALVL_COARSE_DLY_1:RW:16:11:=0x0040 PHY_ADR_CALVL_START_1:RW:0:11:=0x0320 + { 0x0000068B, 0x00000040}, // PHY_ADR_CALVL_QTR_1:RW:0:11:=0x0040 + { 0x0000068C, 0x00000000}, // PHY_ADR_CALVL_SWIZZLE0_0_1:RW:0:24:=0x000000 + { 0x0000068D, 0x00000000}, // PHY_ADR_CALVL_SWIZZLE1_0_1:RW:0:24:=0x000000 + { 0x0000068E, 0x00000000}, // PHY_ADR_CALVL_SWIZZLE0_1_1:RW:0:24:=0x000000 + { 0x0000068F, 0x01000000}, // PHY_ADR_CALVL_DEVICE_MAP_1:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_1:RW:0:24:=0x000000 + { 0x00000690, 0x00020010}, // PHY_ADR_CALVL_RESP_WAIT_CNT_1:RW:24:4:=0x00 PHY_ADR_CALVL_CAPTURE_CNT_1:RW:16:4:=0x02 PHY_ADR_CALVL_NUM_PATTERNS_1:RW:8:2:=0x00 PHY_ADR_CALVL_RANK_CTRL_1:RW:0:5:=0x10 + { 0x00000691, 0x00000000}, // PHY_ADR_CALVL_OBS_SELECT_1:RW:24:3:=0x00 SC_PHY_ADR_CALVL_ERROR_CLR_1:WR:16:1:=0x00 SC_PHY_ADR_CALVL_DEBUG_CONT_1:WR:8:1:=0x00 PHY_ADR_CALVL_DEBUG_MODE_1:RW:0:1:=0x00 + { 0x00000692, 0x00000000}, // PHY_ADR_CALVL_OBS0_1:RD:0:32:=0x00000000 + { 0x00000693, 0x00000000}, // PHY_ADR_CALVL_OBS1_1:RD:0:32:=0x00000000 + { 0x00000694, 0x00002A01}, // PHY_ADR_CALVL_FG_0_1:RW:8:20:=0x00002A PHY_ADR_CALVL_RESULT_1:RW:0:1:=0x01 + { 0x00000695, 0x00000015}, // PHY_ADR_CALVL_BG_0_1:RW:0:20:=0x000015 + { 0x00000696, 0x00000015}, // PHY_ADR_CALVL_FG_1_1:RW:0:20:=0x000015 + { 0x00000697, 0x0000002A}, // PHY_ADR_CALVL_BG_1_1:RW:0:20:=0x00002a + { 0x00000698, 0x00000033}, // PHY_ADR_CALVL_FG_2_1:RW:0:20:=0x000033 + { 0x00000699, 0x0000000C}, // PHY_ADR_CALVL_BG_2_1:RW:0:20:=0x00000c + { 0x0000069A, 0x0000000C}, // PHY_ADR_CALVL_FG_3_1:RW:0:20:=0x00000c + { 0x0000069B, 0x00000033}, // PHY_ADR_CALVL_BG_3_1:RW:0:20:=0x000033 + { 0x0000069C, 0x00000000}, // PHY_ADR_ADDR_SEL_1:RW:0:24:=0x000000 + { 0x0000069D, 0x00000000}, // PHY_ADR_SEG_MASK_1:RW:24:6:=0x00 PHY_ADR_BIT_MASK_1:RW:16:6:=0x00 PHY_ADR_LP4_BOOT_SLV_DELAY_1:RW:0:10:=0x0000 + { 0x0000069E, 0x00000000}, // PHY_ADR_CALVL_TRAIN_MASK_1:RW:0:6:=0x00 +// { 0x0000069F, 0x0003006E}, // PHY_ADR0_CLK_WR_SLAVE_DELAY_1:RW+:8:11:=0x0300 PHY_ADR_TSEL_SELECT_1:RW+:0:8:=0x55 +// { 0x000006A0, 0x03000300}, // PHY_ADR2_CLK_WR_SLAVE_DELAY_1:RW+:16:11:=0x0300 PHY_ADR1_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300 +// { 0x000006A1, 0x03000300}, // PHY_ADR4_CLK_WR_SLAVE_DELAY_1:RW+:16:11:=0x0300 PHY_ADR3_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300 +// { 0x000006A2, 0x00000300}, // PHY_ADR_SW_MASTER_MODE_1:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300 + { 0x0000069F, 0x0003006E}, // PHY_ADR0_CLK_WR_SLAVE_DELAY_1:RW+:8:11:=0x0300 PHY_ADR_TSEL_SELECT_1:RW+:0:8:=0x55 + { 0x000006A0, 0x03000300}, // PHY_ADR2_CLK_WR_SLAVE_DELAY_1:RW+:16:11:=0x0300 PHY_ADR1_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300 + { 0x000006A1, 0x03000300}, // PHY_ADR4_CLK_WR_SLAVE_DELAY_1:RW+:16:11:=0x0300 PHY_ADR3_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300 + { 0x000006A2, 0x00000300}, // PHY_ADR_SW_MASTER_MODE_1:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300 + { 0x000006A3, 0x42080010}, // PHY_ADR_MASTER_DELAY_WAIT_1:RW+:24:8:=0x42 PHY_ADR_MASTER_DELAY_STEP_1:RW+:16:6:=0x08 PHY_ADR_MASTER_DELAY_START_1:RW+:0:10:=0x0010 + { 0x000006A4, 0x00000003}, // PHY_ADR_CALVL_DLY_STEP_1:RW+:0:4:=0x03 + { 0x000006A5, 0x00000000}, // + { 0x000006A6, 0x00000000}, // + { 0x000006A7, 0x00000000}, // + { 0x000006A8, 0x00000000}, // + { 0x000006A9, 0x00000000}, // + { 0x000006AA, 0x00000000}, // + { 0x000006AB, 0x00000000}, // + { 0x000006AC, 0x00000000}, // + { 0x000006AD, 0x00000000}, // + { 0x000006AE, 0x00000000}, // + { 0x000006AF, 0x00000000}, // + { 0x000006B0, 0x00000000}, // + { 0x000006B1, 0x00000000}, // + { 0x000006B2, 0x00000000}, // + { 0x000006B3, 0x00000000}, // + { 0x000006B4, 0x00000000}, // + { 0x000006B5, 0x00000000}, // + { 0x000006B6, 0x00000000}, // + { 0x000006B7, 0x00000000}, // + { 0x000006B8, 0x00000000}, // + { 0x000006B9, 0x00000000}, // + { 0x000006BA, 0x00000000}, // + { 0x000006BB, 0x00000000}, // + { 0x000006BC, 0x00000000}, // + { 0x000006BD, 0x00000000}, // + { 0x000006BE, 0x00000000}, // + { 0x000006BF, 0x00000000}, // + { 0x000006C0, 0x00000000}, // + { 0x000006C1, 0x00000000}, // + { 0x000006C2, 0x00000000}, // + { 0x000006C3, 0x00000000}, // + { 0x000006C4, 0x00000000}, // + { 0x000006C5, 0x00000000}, // + { 0x000006C6, 0x00000000}, // + { 0x000006C7, 0x00000000}, // + { 0x000006C8, 0x00000000}, // + { 0x000006C9, 0x00000000}, // + { 0x000006CA, 0x00000000}, // + { 0x000006CB, 0x00000000}, // + { 0x000006CC, 0x00000000}, // + { 0x000006CD, 0x00000000}, // + { 0x000006CE, 0x00000000}, // + { 0x000006CF, 0x00000000}, // + { 0x000006D0, 0x00000000}, // + { 0x000006D1, 0x00000000}, // + { 0x000006D2, 0x00000000}, // + { 0x000006D3, 0x00000000}, // + { 0x000006D4, 0x00000000}, // + { 0x000006D5, 0x00000000}, // + { 0x000006D6, 0x00000000}, // + { 0x000006D7, 0x00000000}, // + { 0x000006D8, 0x00000000}, // + { 0x000006D9, 0x00000000}, // + { 0x000006DA, 0x00000000}, // + { 0x000006DB, 0x00000000}, // + { 0x000006DC, 0x00000000}, // + { 0x000006DD, 0x00000000}, // + { 0x000006DE, 0x00000000}, // + { 0x000006DF, 0x00000000}, // + { 0x000006E0, 0x00000000}, // + { 0x000006E1, 0x00000000}, // + { 0x000006E2, 0x00000000}, // + { 0x000006E3, 0x00000000}, // + { 0x000006E4, 0x00000000}, // + { 0x000006E5, 0x00000000}, // + { 0x000006E6, 0x00000000}, // + { 0x000006E7, 0x00000000}, // + { 0x000006E8, 0x00000000}, // + { 0x000006E9, 0x00000000}, // + { 0x000006EA, 0x00000000}, // + { 0x000006EB, 0x00000000}, // + { 0x000006EC, 0x00000000}, // + { 0x000006ED, 0x00000000}, // + { 0x000006EE, 0x00000000}, // + { 0x000006EF, 0x00000000}, // + { 0x000006F0, 0x00000000}, // + { 0x000006F1, 0x00000000}, // + { 0x000006F2, 0x00000000}, // + { 0x000006F3, 0x00000000}, // + { 0x000006F4, 0x00000000}, // + { 0x000006F5, 0x00000000}, // + { 0x000006F6, 0x00000000}, // + { 0x000006F7, 0x00000000}, // + { 0x000006F8, 0x00000000}, // + { 0x000006F9, 0x00000000}, // + { 0x000006FA, 0x00000000}, // + { 0x000006FB, 0x00000000}, // + { 0x000006FC, 0x00000000}, // + { 0x000006FD, 0x00000000}, // + { 0x000006FE, 0x00000000}, // + { 0x000006FF, 0x00000000}, // + { 0x00000700, 0x00000001}, // PHY_SW_GRP_SHIFT_1:RW+:24:5:=0x00 PHY_SW_GRP_SHIFT_0:RW+:16:5:=0x00 PHY_FREQ_SEL_INDEX:RW:8:2:=0x00 PHY_FREQ_SEL_MULTICAST_EN:RW_D:0:1:=0x01 + { 0x00000701, 0x00000000}, // PHY_GRP_BYPASS_SLAVE_DELAY:RW:16:11:=0x0000 PHY_SW_GRP_SHIFT_3:RW+:8:5:=0x00 PHY_SW_GRP_SHIFT_2:RW+:0:5:=0x00 + { 0x00000702, 0x00000005}, // PHY_LP4_BOOT_DISABLE:RW:24:1:=0x01 SC_PHY_MANUAL_UPDATE:WR:16:1:=0x00 PHY_GRP_BYPASS_OVERRIDE:RW:8:1:=0x00 PHY_SW_GRP_BYPASS_SHIFT:RW:0:5:=0x05 +// { 0x00000702, 0x01000005}, // PHY_LP4_BOOT_DISABLE:RW:24:1:=0x01 SC_PHY_MANUAL_UPDATE:WR:16:1:=0x00 PHY_GRP_BYPASS_OVERRIDE:RW:8:1:=0x00 PHY_SW_GRP_BYPASS_SHIFT:RW:0:5:=0x05 +// { 0x00000703, 0x04003100}, // PHY_CSLVL_START:RW:16:11:=0x0400 PHY_CSLVL_CS_MAP:RW:8:4:=0x31 PHY_CSLVL_ENABLE:RW:0:1:=0x01 + { 0x00000703, 0x04000300}, // PHY_CSLVL_START:RW:16:11:=0x0400 PHY_CSLVL_CS_MAP:RW:8:4:=0x31 PHY_CSLVL_ENABLE:RW:0:1:=0x01 + { 0x00000704, 0x00020040}, // PHY_CSLVL_CAPTURE_CNT:RW:16:4:=0x02 PHY_CSLVL_QTR:RW:0:11:=0x0040 + { 0x00000705, 0x00020055}, // PHY_CSLVL_DEBUG_MODE:RW:24:1:=0x00 PHY_CSLVL_COARSE_CAPTURE_CNT:RW:16:4:=0x02 PHY_CSLVL_COARSE_DLY:RW:0:11:=0x0055 + { 0x00000706, 0x00000000}, // SC_PHY_CSLVL_ERROR_CLR:WR:8:1:=0x00 SC_PHY_CSLVL_DEBUG_CONT:WR:0:1:=0x00 + { 0x00000707, 0x00000000}, // PHY_CSLVL_OBS0:RD:0:32:=0x00000000 + { 0x00000708, 0x00000000}, // PHY_CSLVL_OBS1:RD:0:32:=0x00000000 + { 0x00000709, 0x00000050}, // PHY_GRP_SHIFT_OBS_SELECT:RW:24:5:=0x00 PHY_GRP_SLV_DLY_ENC_OBS_SELECT:RW:8:10:=0x0000 PHY_CALVL_CS_MAP:RW:0:8:=0x50 + { 0x0000070A, 0x00000000}, // PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE:RW:24:3:=0x00 PHY_GRP_SHIFT_OBS:RD:16:3:=0x00 PHY_GRP_SLV_DLY_ENC_OBS:RD:0:10:=0x0000 + { 0x0000070B, 0x01010100}, // PHY_LP4_ACTIVE:RW:24:1:=0x01 PHY_ADRCTL_LPDDR:RW:16:1:=0x01 PHY_DFI_PHYUPD_TYPE:RW:8:2:=0x01 PHY_ADRCTL_SNAP_OBS_REGS:WR:0:1:=0x00 + { 0x0000070C, 0x00000000}, // PHY_CONTINUOUS_CLK_CAL_UPDATE:RW:24:1:=0x00 PHY_UPDATE_CLK_CAL_VALUES:RW:16:1:=0x00 PHY_CALVL_RESULT_MASK:RW:8:2:=0x00 PHY_LPDDR3_CS:RW_D:0:1:=0x00 + { 0x0000070D, 0x00001102}, // PHY_PLL_CTRL:RW+:0:13:=0x1102 + { 0x0000070E, 0x00000000}, // PHY_PLL_BYPASS:RW+:0:5:=0x00 + { 0x0000070F, 0x000F1900}, // PHY_PAD_VREF_CTRL_DQ_0:RW+:8:14:=0x0100 PHY_LOW_FREQ_SEL:RW+:0:1:=0x00 +// { 0x0000070F, 0x000F1901}, // PHY_PAD_VREF_CTRL_DQ_0:RW+:8:14:=0x0100 PHY_LOW_FREQ_SEL:RW+:0:1:=0x01 + { 0x00000710, 0x0F190F19}, // PHY_PAD_VREF_CTRL_DQ_2:RW+:16:14:=0x0100 PHY_PAD_VREF_CTRL_DQ_1:RW+:0:14:=0x0100 + { 0x00000711, 0x0F190F19}, // PHY_PAD_VREF_CTRL_AC:RW+:16:14:=0x0100 PHY_PAD_VREF_CTRL_DQ_3:RW+:0:14:=0x0100 +// { 0x00000712, 0x00030003}, // PHY_GRP_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_CSLVL_DLY_STEP:RW+:0:4:=0x03 +// { 0x00000713, 0x03000300}, // PHY_GRP_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP_SLAVE_DELAY_1:RW+:0:11:=0x0300 +// { 0x00000714, 0x00000300}, // PHY_GRP_SLAVE_DELAY_3:RW+:0:11:=0x0300 + { 0x00000712, 0x0002c003}, // PHY_GRP_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_CSLVL_DLY_STEP:RW+:0:4:=0x03 + { 0x00000713, 0x02c002c0}, // PHY_GRP_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP_SLAVE_DELAY_1:RW+:0:11:=0x0300 + { 0x00000714, 0x000002c0}, // PHY_GRP_SLAVE_DELAY_3:RW+:0:11:=0x0300 + { 0x00000715, 0x00001102}, // PHY_PLL_CTRL_OVERRIDE:RW:16:16:=0x0000 PHY_LP4_BOOT_PLL_CTRL:RW:0:13:=0x1b02 +// { 0x00000715, 0x00001b02}, // PHY_PLL_CTRL_OVERRIDE:RW:16:16:=0x0000 PHY_LP4_BOOT_PLL_CTRL:RW:0:13:=0x1b02 +//NG 0x00000715, 0x00001b02, // PHY_PLL_CTRL_OVERRIDE:RW:16:16:=0x0000 PHY_LP4_BOOT_PLL_CTRL:RW:0:13:=0x1b02 +// { 0x00000715, 0x00001302}, // PHY_PLL_CTRL_OVERRIDE:RW:16:16:=0x0000 PHY_LP4_BOOT_PLL_CTRL:RW:0:13:=0x1b02 + { 0x00000716, 0x000000FF}, // PHY_PLL_OBS_0:RD:8:16:=0x0000 PHY_PLL_WAIT:RW:0:8:=0x64 + { 0x00000717, 0x00000000}, // PHY_PLL_OBS_2:RD:16:16:=0x0000 PHY_PLL_OBS_1:RD:0:16:=0x0000 + { 0x00000718, 0x00000000}, // PHY_PLL_OBS_4:RD:16:16:=0x0000 PHY_PLL_OBS_3:RD:0:16:=0x0000 +// { 0x00000719, 0x00010503}, // PHY_LP_WAKEUP:RW:24:4:=0x00 PHY_LP4_BOOT_LOW_FREQ_SEL:RW:16:1:=0x01 PHY_TCKSRE_WAIT:RW:8:4:=0x05 PHY_PLL_TESTOUT_SEL:RW:0:3:=0x03 + { 0x00000719, 0x00000503}, // PHY_LP_WAKEUP:RW:24:4:=0x00 PHY_LP4_BOOT_LOW_FREQ_SEL:RW:16:1:=0x01 PHY_TCKSRE_WAIT:RW:8:4:=0x05 PHY_PLL_TESTOUT_SEL:RW:0:3:=0x03 + { 0x0000071A, 0x027F6E00}, // PHY_PAD_FDBK_DRIVE:RW+:8:18:=0x000411 PHY_TDFI_PHY_WRDELAY:RW:0:1:=0x00 + { 0x0000071B, 0x047F027F}, // PHY_PAD_DQS_DRIVE:RW+:16:12:=0x0040 PHY_PAD_DATA_DRIVE:RW+:0:10:=0x0040 + { 0x0000071C, 0x00027F6E}, // PHY_PAD_ADDR_DRIVE:RW+:0:18:=0x000411 // LPDDR4_EN bit 14 is it needed? + { 0x0000071D, 0x00047F6E}, // PHY_PAD_CLK_DRIVE:RW+:0:20:=0x000411 + { 0x0000071E, 0x00030F68}, // PHY_PAD_FDBK_TERM:RW+:0:18:=0x004410 //PVTP = 0x28, PVTN=0x3d, PVTr=0x10 + { 0x0000071F, 0x00010F68}, // PHY_PAD_DATA_TERM:RW+:0:17:=0x004410 + { 0x00000720, 0x00010F68}, // PHY_PAD_DQS_TERM:RW+:0:17:=0x004410 + { 0x00000721, 0x00010F68}, // PHY_PAD_ADDR_TERM:RW+:0:18:=0x004410 + { 0x00000722, 0x00010F68}, // PHY_PAD_CLK_TERM:RW+:0:18:=0x004410 + { 0x00000723, 0x00027F6E}, // PHY_PAD_CKE_DRIVE:RW+:0:18:=0x000411 + { 0x00000724, 0x00010F68}, // PHY_PAD_CKE_TERM:RW+:0:18:=0x004410 + { 0x00000725, 0x00027F6E}, // PHY_PAD_RST_DRIVE:RW+:0:18:=0x000411 + { 0x00000726, 0x00010F68}, // PHY_PAD_RST_TERM:RW+:0:18:=0x004410 + { 0x00000727, 0x00027F6E}, // PHY_PAD_CS_DRIVE:RW+:0:18:=0x000411 + { 0x00000728, 0x00010F68}, // PHY_PAD_CS_TERM:RW+:0:18:=0x004410 + { 0x00000729, 0x00000000}, // PHY_ADRCTL_RX_CAL:RW:0:25:=0x00000000 + { 0x0000072A, 0x00000000}, // PHY_ADRCTL_LP3_RX_CAL:RW:0:25:=0x00000000 + { 0x0000072B, 0x00000000}, // PHY_TST_CLK_PAD_CTRL:RW:0:32:=0x00000000 + { 0x0000072C, 0x65000000}, // PHY_CAL_MODE_0:RW:24:8:=0x64 PHY_TST_CLK_PAD_CTRL2:RW:0:23:=0x000000 + { 0x0000072D, 0x00000000}, // PHY_CAL_START_0:WR:8:1:=0x00 PHY_CAL_CLEAR_0:WR:0:1:=0x00 + { 0x0000072E, 0x00000000}, // PHY_CAL_INTERVAL_COUNT_0:RW:0:32:=0x00000000 + { 0x0000072F, 0x00000608}, // PHY_CAL_CLK_SELECT_0:RW:8:3:=0x01 PHY_CAL_SAMPLE_WAIT_0:RW:0:8:=0x08 + { 0x00000730, 0x00000000}, // PHY_CAL_RESULT_OBS_0:RD:0:24:=0x000000 + { 0x00000731, 0x00000000}, // PHY_CAL_RESULT2_OBS_0:RD:0:24:=0x000000 + { 0x00000732, 0x00000000}, // PHY_AC_LPBK_ERR_CLEAR:WR:24:1:=0x00 PHY_ADRCTL_MANUAL_UPDATE:WR:16:1:=0x00 PHY_PAD_ATB_CTRL:RW:0:16:=0x0000 + { 0x00000733, 0x00000000}, // PHY_AC_LPBK_OBS_SELECT:RW:0:5:=0x00 + { 0x00000734, 0x00000000}, // PHY_AC_LPBK_ENABLE:RW:0:32:=0x00000000 + { 0x00000735, 0x00000000}, // PHY_AC_LPBK_CONTROL:RW:0:9:=0x0000 + { 0x00000736, 0x00000000}, // PHY_AC_LPBK_RESULT_OBS:RD:0:32:=0x00000000 + { 0x00000737, 0x00000000}, // PHY_AC_CLK_LPBK_CONTROL:RW:24:6:=0x00 PHY_AC_CLK_LPBK_ENABLE:RW:8:16:=0x0000 PHY_AC_CLK_LPBK_OBS_SELECT:RW:0:4:=0x00 + { 0x00000738, 0x00000000}, // PHY_AC_CLK_LPBK_RESULT_OBS:RD:0:16:=0x0000 + { 0x00000739, 0x00000000}, // PHY_DDL_AC_ENABLE:RW:0:32:=0x00000000 + { 0x0000073A, 0x00000000}, // PHY_DDL_AC_MODE:RW:0:11:=0x0000 +}; + + +static const uint32_t DDR_PI_suresh[181][2] = +{ + + { 0x00000200, 0x00000B00}, // PI_VERSION:RD:16:16:=0x0000 PI_DRAM_CLASS:RW:8:4:=0x0b PI_START:RW:0:1:=0x00 + { 0x00000201, 0x00000100}, // PI_TCMD_GAP:RW:16:16:=0x0000 PI_INIT_LVL_EN:RW:8:1:=0x01 PI_NORMAL_LVL_SEQ:RW:0:1:=0x00 + { 0x00000202, 0x00000118}, // PI_TDFI_PHYMSTR_MAX_F0:RW:0:32:=0x00000118 +// { 0x00000202, 0x00006098}, // PI_TDFI_PHYMSTR_MAX_F0:RW:0:32:=0x00006098 + { 0x00000203, 0x0000008C}, // PI_TDFI_PHYMSTR_RESP_F0:RW:0:16:=0x008c +// { 0x00000203, 0x0000304C}, // PI_TDFI_PHYMSTR_RESP_F0:RW:0:16:=0x304c + { 0x00000204, 0x00006098}, // PI_TDFI_PHYMSTR_MAX_F1:RW:0:32:=0x00006098 + { 0x00000205, 0x0000304C}, // PI_TDFI_PHYMSTR_RESP_F1:RW:0:16:=0x304c + { 0x00000206, 0x00006098}, // PI_TDFI_PHYMSTR_MAX_F2:RW:0:32:=0x00006098 + { 0x00000207, 0x008C304C}, // PI_TDFI_PHYUPD_RESP_F0:RW:16:16:=0x008c PI_TDFI_PHYMSTR_RESP_F2:RW:0:16:=0x304c +// { 0x00000207, 0x304C304C}, // PI_TDFI_PHYUPD_RESP_F0:RW:16:16:=0x008c PI_TDFI_PHYMSTR_RESP_F2:RW:0:16:=0x304c + { 0x00000208, 0x00000200}, // PI_TDFI_PHYUPD_TYPE0_F0:RW:0:32:=0x00000200 + { 0x00000209, 0x00000200}, // PI_TDFI_PHYUPD_TYPE1_F0:RW:0:32:=0x00000200 + { 0x0000020A, 0x00000200}, // PI_TDFI_PHYUPD_TYPE2_F0:RW:0:32:=0x00000200 + { 0x0000020B, 0x00000200}, // PI_TDFI_PHYUPD_TYPE3_F0:RW:0:32:=0x00000200 + { 0x0000020C, 0x0000304C}, // PI_TDFI_PHYUPD_RESP_F1:RW:0:16:=0x304c + { 0x0000020D, 0x00000200}, // PI_TDFI_PHYUPD_TYPE0_F1:RW:0:32:=0x00000200 + { 0x0000020E, 0x00000200}, // PI_TDFI_PHYUPD_TYPE1_F1:RW:0:32:=0x00000200 + { 0x0000020F, 0x00000200}, // PI_TDFI_PHYUPD_TYPE2_F1:RW:0:32:=0x00000200 + { 0x00000210, 0x00000200}, // PI_TDFI_PHYUPD_TYPE3_F1:RW:0:32:=0x00000200 + { 0x00000211, 0x0000304C}, // PI_TDFI_PHYUPD_RESP_F2:RW:0:16:=0x304c + { 0x00000212, 0x00000200}, // PI_TDFI_PHYUPD_TYPE0_F2:RW:0:32:=0x00000200 + { 0x00000213, 0x00000200}, // PI_TDFI_PHYUPD_TYPE1_F2:RW:0:32:=0x00000200 + { 0x00000214, 0x00000200}, // PI_TDFI_PHYUPD_TYPE2_F2:RW:0:32:=0x00000200 + { 0x00000215, 0x00000200}, // PI_TDFI_PHYUPD_TYPE3_F2:RW:0:32:=0x00000200 + { 0x00000216, 0x00010000}, // PI_EXIT_AFTER_INIT_CALVL:RW_D:16:1:=0x01 PI_CONTROL_ERROR_STATUS:RD:0:9:=0x0000 +// { 0x00000217, 0x00000005}, // PI_FREQ_MAP:RW:0:32:=0x00000007 + { 0x00000217, 0x00000003}, // PI_FREQ_MAP:RW:0:32:=0x00000007 +// { 0x00000218, 0x01000002}, // PI_POWER_ON_SEQ_END_ARRAY:RW:24:8:=0x01 PI_POWER_ON_SEQ_BYPASS_ARRAY:RW:16:8:=0x00 PI_INIT_DFS_CALVL_ONLY:RW:8:1:=0x00 PI_INIT_WORK_FREQ:RW:0:5:=0x01 + { 0x00000218, 0x01000001}, // PI_POWER_ON_SEQ_END_ARRAY:RW:24:8:=0x01 PI_POWER_ON_SEQ_BYPASS_ARRAY:RW:16:8:=0x00 PI_INIT_DFS_CALVL_ONLY:RW:8:1:=0x00 PI_INIT_WORK_FREQ:RW:0:5:=0x01 + { 0x00000219, 0x00000000}, // PI_SEQ1_PAT:RW:0:28:=0x00000000 + { 0x0000021A, 0x00000000}, // PI_SEQ1_PAT_MASK:RW:0:28:=0x00000000 + { 0x0000021B, 0x00000000}, // PI_SEQ2_PAT:RW:0:28:=0x00000000 + { 0x0000021C, 0x00000000}, // PI_SEQ2_PAT_MASK:RW:0:28:=0x00000000 + { 0x0000021D, 0x00000000}, // PI_SEQ3_PAT:RW:0:28:=0x00000000 + { 0x0000021E, 0x00000000}, // PI_SEQ3_PAT_MASK:RW:0:28:=0x00000000 + { 0x0000021F, 0x00000000}, // PI_SEQ4_PAT:RW:0:28:=0x00000000 + { 0x00000220, 0x00000000}, // PI_SEQ4_PAT_MASK:RW:0:28:=0x00000000 + { 0x00000221, 0x00000000}, // PI_SEQ5_PAT:RW:0:28:=0x00000000 + { 0x00000222, 0x00000000}, // PI_SEQ5_PAT_MASK:RW:0:28:=0x00000000 + { 0x00000223, 0x00000000}, // PI_SEQ6_PAT:RW:0:28:=0x00000000 + { 0x00000224, 0x00000000}, // PI_SEQ6_PAT_MASK:RW:0:28:=0x00000000 + { 0x00000225, 0x00000000}, // PI_SEQ7_PAT:RW:0:28:=0x00000000 + { 0x00000226, 0x00000000}, // PI_SEQ7_PAT_MASK:RW:0:28:=0x00000000 + { 0x00000227, 0x00000000}, // PI_SEQ8_PAT:RW:0:28:=0x00000000 + { 0x00000228, 0x00000000}, // PI_SEQ8_PAT_MASK:RW:0:28:=0x00000000 +// { 0x00000229, 0x0f000101}, // PI_CS_MAP:RW:24:4:=0x0f RESERVED:RW:16:1:=0x00 PI_SW_RST_N:RW_D:8:1:=0x01 PI_WDT_DISABLE:RW_D:0:1:=0x01 +// { 0x00000229, 0x01000101}, // PI_CS_MAP:RW:24:4:=0x0f RESERVED:RW:16:1:=0x00 PI_SW_RST_N:RW_D:8:1:=0x01 PI_WDT_DISABLE:RW_D:0:1:=0x01 + { 0x00000229, 0x05000101}, // PI_CS_MAP:RW:24:4:=0x0f RESERVED:RW:16:1:=0x00 PI_SW_RST_N:RW_D:8:1:=0x01 PI_WDT_DISABLE:RW_D:0:1:=0x01 + { 0x0000022A, 0x08494925}, // PI_TMRR:RW:24:4:=0x08 PI_TDELAY_RDWR_2_BUS_IDLE_F2:RW:16:8:=0x49 PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8:=0x49 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8:=0x25 +/*--150819 + { 0x0000022B, 0x380E0C04}, // PI_CASLAT_LIN_F1:RW:24:7:=0x38 PI_WRLAT_F1:RW:16:6:=0x0e PI_CASLAT_LIN_F0:RW:8:7:=0x0c PI_WRLAT_F0:RW:0:6:=0x04 + { 0x0000022C, 0x0002500E}, // PI_AREFRESH:WR:24:1:=0x00 PI_PREAMBLE_SUPPORT:RW:16:2:=0x02 PI_CASLAT_LIN_F2:RW:8:7:=0x38 PI_WRLAT_F2:RW:0:6:=0x0e +*/ +//150819-> + { 0x0000022B, (PI_CASLAT_LIN<<24)|(PI_WRLAT<<16)|(PI_CASLAT_LIN<<8)|(PI_WRLAT<<0)}, // PI_CASLAT_LIN_F1:RW:24:7:=0x38 PI_WRLAT_F1:RW:16:6:=0x0e PI_CASLAT_LIN_F0:RW:8:7:=0x0c PI_WRLAT_F0:RW:0:6:=0x04 + { 0x0000022C, 0x00020000|(PI_CASLAT_LIN<<8)|(PI_WRLAT<<0)}, // PI_AREFRESH:WR:24:1:=0x00 PI_PREAMBLE_SUPPORT:RW:16:2:=0x02 PI_CASLAT_LIN_F2:RW:8:7:=0x38 PI_WRLAT_F2:RW:0:6:=0x0e +//<- + { 0x0000022D, 0x00460003}, // PI_TREF_F0:RW:16:16:=0x0046 PI_TRFC_F0:RW:0:10:=0x0003 + { 0x0000022E, 0x182600CF}, // PI_TREF_F1:RW:16:16:=0x1826 PI_TRFC_F1:RW:0:10:=0x00cf + { 0x0000022F, 0x182600CF}, // PI_TREF_F2:RW:16:16:=0x1826 PI_TRFC_F2:RW:0:10:=0x00cf + { 0x00000230, 0x00000005}, // PI_SWLVL_OP_DONE:RD:24:1:=0x00 PI_SWLVL_LOAD:WR:16:1:=0x00 PI_TREF_INTERVAL:RW:0:16:=0x0005 + { 0x00000231, 0x00000000}, // PI_SW_WRLVL_RESP_3:RD:24:1:=0x00 PI_SW_WRLVL_RESP_2:RD:16:1:=0x00 PI_SW_WRLVL_RESP_1:RD:8:1:=0x00 PI_SW_WRLVL_RESP_0:RD:0:1:=0x00 + { 0x00000232, 0x00000000}, // PI_SW_RDLVL_RESP_3:RD:24:2:=0x00 PI_SW_RDLVL_RESP_2:RD:16:2:=0x00 PI_SW_RDLVL_RESP_1:RD:8:2:=0x00 PI_SW_RDLVL_RESP_0:RD:0:2:=0x00 + { 0x00000233, 0x00000000}, // PI_SWLVL_EXIT:WR:24:1:=0x00 PI_SWLVL_START:WR:16:1:=0x00 PI_SW_LEVELING_MODE:RW:8:3:=0x00 PI_SW_CALVL_RESP_0:RD:0:2:=0x00 + { 0x00000234, 0x00000000}, // PI_SWLVL_WR_SLICE_1:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_0:RD:16:2:=0x00 PI_SWLVL_RD_SLICE_0:WR:8:1:=0x00 PI_SWLVL_WR_SLICE_0:WR:0:1:=0x00 + { 0x00000235, 0x00000000}, // PI_SWLVL_RD_SLICE_2:WR:24:1:=0x00 PI_SWLVL_WR_SLICE_2:WR:16:1:=0x00 PI_SW_WDQLVL_RESP_1:RD:8:2:=0x00 PI_SWLVL_RD_SLICE_1:WR:0:1:=0x00 + { 0x00000236, 0x00000000}, // PI_SW_WDQLVL_RESP_3:RD:24:2:=0x00 PI_SWLVL_RD_SLICE_3:WR:16:1:=0x00 PI_SWLVL_WR_SLICE_3:WR:8:1:=0x00 PI_SW_WDQLVL_RESP_2:RD:0:2:=0x00 + { 0x00000237, 0x00000000}, // PI_SWLVL_SM2_RD:WR:24:1:=0x00 PI_SWLVL_SM2_WR:WR:16:1:=0x00 PI_SWLVL_SM2_START:WR:8:1:=0x00 PI_SW_WDQLVL_VREF:RW:0:7:=0x00 + { 0x00000238, 0x01000000}, // PI_16BIT_DRAM_CONNECT:RW_D:24:1:=0x01 PI_SRE_PERIOD_EN:RW:16:1:=0x00 PI_DFS_PERIOD_EN:RW:8:1:=0x00 PI_SEQUENTIAL_LVL_REQ:WR:0:1:=0x00 + { 0x00000239, 0x00040404}, // PI_WRLVL_REQ:WR:24:1:=0x00 PI_TDFI_CTRL_DELAY_F2:RW_D:16:4:=0x04 PI_TDFI_CTRL_DELAY_F1:RW_D:8:4:=0x04 PI_TDFI_CTRL_DELAY_F0:RW_D:0:4:=0x04 + { 0x0000023A, 0x01280A00}, // PI_WRLVL_EN:RW:24:2:=0x01 PI_WLMRD:RW:16:6:=0x28 PI_WLDQSEN:RW:8:6:=0x0a PI_WRLVL_CS:RW:0:2:=0x00 + { 0x0000023B, 0x00000000}, // PI_WRLVL_ON_SREF_EXIT:RW:24:1:=0x00 PI_WRLVL_PERIODIC:RW:16:1:=0x00 PI_WRLVL_INTERVAL:RW:0:16:=0x0000 +// { 0x0000023C, 0x00030000}, // PI_WRLVL_ERROR_STATUS:RD:24:2:=0x00 PI_WRLVL_CS_MAP:RW:16:4:=0x03 PI_WRLVL_ROTATE:RW:8:1:=0x00 PI_WRLVL_RESP_MASK:RW:0:4:=0x00 + { 0x0000023C, 0x00010000}, // PI_WRLVL_ERROR_STATUS:RD:24:2:=0x00 PI_WRLVL_CS_MAP:RW:16:4:=0x03 PI_WRLVL_ROTATE:RW:8:1:=0x00 PI_WRLVL_RESP_MASK:RW:0:4:=0x00 + { 0x0000023D, 0x00001440}, // PI_TDFI_WRLVL_WW:RW:8:10:=0x0014 PI_TDFI_WRLVL_EN:RW:0:8:=0x03 + { 0x0000023E, 0x00000000}, // PI_TDFI_WRLVL_RESP:RW:0:32:=0x00000000 + { 0x0000023F, 0x00000000}, // PI_TDFI_WRLVL_MAX:RW:0:32:=0x00000000 + { 0x00000240, 0x00060102}, // PI_TODTL_2CMD_F0:RW:24:8:=0x00 PI_WRLVL_EN_DEASSERT_2_MRR:RW:16:5:=0x06 PI_WRLVL_MRR_DQ_RETURN_HIZ:RW:8:1:=0x01 PI_WRLVL_STROBE_NUM:RW:0:5:=0x02 + { 0x00000241, 0x00010001}, // PI_TODTL_2CMD_F2:RW:24:8:=0x00 PI_ODT_EN_F1:RW:16:1:=0x01 PI_TODTL_2CMD_F1:RW:8:8:=0x00 PI_ODT_EN_F0:RW:0:1:=0x01 + { 0x00000242, 0x01000101}, // PI_ODT_RD_MAP_CS0:RW:24:4:=0x01 PI_TODTH_RD:RW:16:4:=0x00 PI_TODTH_WR:RW:8:4:=0x01 PI_ODT_EN_F2:RW:0:1:=0x01 + { 0x00000243, 0x04020201}, // PI_ODT_RD_MAP_CS2:RW:24:4:=0x04 PI_ODT_WR_MAP_CS1:RW:16:4:=0x02 PI_ODT_RD_MAP_CS1:RW:8:4:=0x02 PI_ODT_WR_MAP_CS0:RW:0:4:=0x01 + { 0x00000244, 0x00080804}, // PI_EN_ODT_ASSERT_EXCEPT_RD:RW:24:1:=0x00 PI_ODT_WR_MAP_CS3:RW:16:4:=0x08 PI_ODT_RD_MAP_CS3:RW:8:4:=0x08 PI_ODT_WR_MAP_CS2:RW:0:4:=0x04 + { 0x00000245, 0x00000000}, // PI_TODTON_MIN_F1:RW:24:4:=0x00 PI_ODTLON_F1:RW:16:4:=0x00 PI_TODTON_MIN_F0:RW:8:4:=0x00 PI_ODTLON_F0:RW:0:4:=0x00 + { 0x00000246, 0x08030000}, // PI_WR_TO_ODTH_F1:RW:24:6:=0x08 PI_WR_TO_ODTH_F0:RW:16:6:=0x03 PI_TODTON_MIN_F2:RW:8:4:=0x00 PI_ODTLON_F2:RW:0:4:=0x00 + { 0x00000247, 0x15150408}, // PI_RD_TO_ODTH_F2:RW:24:6:=0x15 PI_RD_TO_ODTH_F1:RW:16:6:=0x15 PI_RD_TO_ODTH_F0:RW:8:6:=0x04 PI_WR_TO_ODTH_F2:RW:0:6:=0x08 + { 0x00000248, 0x00000000}, // PI_RDLVL_SEQ_EN:RW:24:4:=0x00 PI_RDLVL_CS:RW:16:2:=0x00 PI_RDLVL_GATE_REQ:WR:8:1:=0x00 PI_RDLVL_REQ:WR:0:1:=0x00 + { 0x00000249, 0x00000000}, // PI_RDLVL_GATE_PERIODIC:RW:24:1:=0x00 PI_RDLVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_RDLVL_PERIODIC:RW:8:1:=0x00 PI_RDLVL_GATE_SEQ_EN:RW:0:4:=0x00 + { 0x0000024A, 0x00000000}, // PI_RDLVL_GATE_ROTATE:RW:24:1:=0x00 PI_RDLVL_ROTATE:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 PI_RDLVL_GATE_ON_SREF_EXIT:RW:0:1:=0x00 +// { 0x0000024B, 0x001E0303}, // PI_TDFI_RDLVL_RR:RW:16:10:=0x001e PI_RDLVL_GATE_CS_MAP:RW:8:4:=0x03 PI_RDLVL_CS_MAP:RW:0:4:=0x03 + { 0x0000024B, 0x001E0101}, // PI_TDFI_RDLVL_RR:RW:16:10:=0x001e PI_RDLVL_GATE_CS_MAP:RW:8:4:=0x03 PI_RDLVL_CS_MAP:RW:0:4:=0x03 + { 0x0000024C, 0x00000000}, // PI_TDFI_RDLVL_RESP:RW:0:32:=0x00000000 +// { 0x0000024D, 0x01010300}, // PI_RDLVL_GATE_EN:RW:24:2:=0x01 PI_RDLVL_EN:RW:16:2:=0x01 PI_TDFI_RDLVL_EN:RW:8:8:=0x03 PI_RDLVL_RESP_MASK:RW:0:4:=0x00 +// { 0x0000024D, 0x01000300}, // PI_RDLVL_GATE_EN:RW:24:2:=0x01 PI_RDLVL_EN:RW:16:2:=0x01 PI_TDFI_RDLVL_EN:RW:8:8:=0x03 PI_RDLVL_RESP_MASK:RW:0:4:=0x00 + { 0x0000024D, 0x01000100}, // PI_RDLVL_GATE_EN:RW:24:2:=0x01 PI_RDLVL_EN:RW:16:2:=0x01 PI_TDFI_RDLVL_EN:RW:8:8:=0x03 PI_RDLVL_RESP_MASK:RW:0:4:=0x00 + { 0x0000024E, 0x00000000}, // PI_TDFI_RDLVL_MAX:RW:0:32:=0x00000000 + { 0x0000024F, 0x00000000}, // PI_RDLVL_INTERVAL:RW:8:16:=0x0000 PI_RDLVL_ERROR_STATUS:RD:0:2:=0x00 + { 0x00000250, 0x01000000}, // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 + { 0x00000251, 0x00010101}, // PI_REG_DIMM_ENABLE:RW:24:1:=0x00 PI_RD_PREAMBLE_TRAINING_EN:RW:16:1:=0x01 PI_RDLVL_GATE_STROBE_NUM:RW:8:5:=0x01 PI_RDLVL_STROBE_NUM:RW:0:5:=0x01 +/*--150819 + { 0x00000252, 0x000E0E05}, // PI_TDFI_RDDATA_EN:RD:24:7:=0x00 PI_RDLAT_ADJ_F2:RW:16:7:=0x0e PI_RDLAT_ADJ_F1:RW:8:7:=0x0e PI_RDLAT_ADJ_F0:RW:0:7:=0x05 + { 0x00000253, 0x000C0C02}, // PI_TDFI_PHY_WRLAT:RD:24:7:=0x00 PI_WRLAT_ADJ_F2:RW:16:7:=0x0c PI_WRLAT_ADJ_F1:RW:8:7:=0x0c PI_WRLAT_ADJ_F0:RW:0:7:=0x02 +*/ +//150819-> + { 0x00000252, (PI_RDLAT_ADJ<<16)|(PI_RDLAT_ADJ<<8)|(PI_RDLAT_ADJ<<0)}, // PI_TDFI_RDDATA_EN:RD:24:7:=0x00 PI_RDLAT_ADJ_F2:RW:16:7:=0x0e PI_RDLAT_ADJ_F1:RW:8:7:=0x0e PI_RDLAT_ADJ_F0:RW:0:7:=0x05 + { 0x00000253, (PI_WRLAT_ADJ<<16)|(PI_WRLAT_ADJ<<8)|(PI_WRLAT_ADJ<<0)}, // PI_TDFI_PHY_WRLAT:RD:24:7:=0x00 PI_WRLAT_ADJ_F2:RW:16:7:=0x0c PI_WRLAT_ADJ_F1:RW:8:7:=0x0c PI_WRLAT_ADJ_F0:RW:0:7:=0x02 +//<- + { 0x00000254, 0x02060601}, // PI_TDFI_PHY_WRDATA:RW:24:3:=0x02 PI_TDFI_WRCSLAT_F2:RW:16:7:=0x06 PI_TDFI_WRCSLAT_F1:RW:8:7:=0x06 PI_TDFI_WRCSLAT_F0:RW:0:7:=0x01 + { 0x00000255, 0x00000000}, // RESERVED:RW:24:4:=0x00 RESERVED:RW:16:1:=0x00 PI_CALVL_CS:RW:8:2:=0x00 PI_CALVL_REQ:WR:0:1:=0x00 + { 0x00000256, 0x00000003}, // PI_CALVL_ROTATE:RW:24:1:=0x00 PI_CALVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_CALVL_PERIODIC:RW:8:1:=0x00 PI_CALVL_SEQ_EN:RW:0:2:=0x03 +// { 0x00000257, 0x00181703}, // PI_TDFI_CALVL_CC_F0:RW:16:10:=0x0018 PI_TDFI_CALVL_EN:RW:8:8:=0x17 PI_CALVL_CS_MAP:RW:0:4:=0x03 + { 0x00000257, 0x00181701}, // PI_TDFI_CALVL_CC_F0:RW:16:10:=0x0018 PI_TDFI_CALVL_EN:RW:8:8:=0x17 PI_CALVL_CS_MAP:RW:0:4:=0x03 + { 0x00000258, 0x00280006}, // PI_TDFI_CALVL_CC_F1:RW:16:10:=0x0028 PI_TDFI_CALVL_CAPTURE_F0:RW:0:10:=0x0006 + { 0x00000259, 0x00280016}, // PI_TDFI_CALVL_CC_F2:RW:16:10:=0x0028 PI_TDFI_CALVL_CAPTURE_F1:RW:0:10:=0x0016 + { 0x0000025A, 0x00000016}, // PI_TDFI_CALVL_CAPTURE_F2:RW:0:10:=0x0016 + { 0x0000025B, 0x00000000}, // PI_TDFI_CALVL_RESP:RW:0:32:=0x00000000 + { 0x0000025C, 0x00000000}, // PI_TDFI_CALVL_MAX:RW:0:32:=0x00000000 + { 0x0000025D, 0x00000000}, // PI_CALVL_ERROR_STATUS:RD:16:2:=0x00 PI_CALVL_EN:RW:8:2:=0x01 PI_CALVL_RESP_MASK:RW:0:1:=0x00 + { 0x0000025E, 0x140A0000}, // PI_TCAMRD:RW:24:6:=0x14 PI_TCACKEL:RW:16:5:=0x0a PI_CALVL_INTERVAL:RW:0:16:=0x0000 + { 0x0000025F, 0x00FF010A}, // PI_TCAENT_F0:RW:16:14:=0x0005 PI_TMRZ_F0:RW:8:5:=0x01 PI_TCACKEH:RW:0:5:=0x0a + { 0x00000260, 0x03018D03}, // PI_TMRZ_F2:RW:24:5:=0x03 PI_TCAENT_F1:RW:8:14:=0x018d PI_TMRZ_F1:RW:0:5:=0x03 + { 0x00000261, 0x000A018D}, // PI_CA_TRAIN_VREF_EN:RW:24:1:=0x01 PI_TCAEXT:RW:16:5:=0x0a PI_TCAENT_F2:RW:0:14:=0x018d + { 0x00000262, 0x00060100}, // PI_TVREF_SHORT_F0:RW:16:10:=0x0006 PI_TDFI_CASEL_F0:RW:8:5:=0x01 PI_TDFI_CACSCA_F0:RW:0:5:=0x00 + { 0x00000263, 0x01000006}, // PI_TDFI_CASEL_F1:RW:24:5:=0x01 PI_TDFI_CACSCA_F1:RW:16:5:=0x00 PI_TVREF_LONG_F0:RW:0:10:=0x0006 + { 0x00000264, 0x018E018E}, // PI_TVREF_LONG_F1:RW:16:10:=0x018e PI_TVREF_SHORT_F1:RW:0:10:=0x018e + { 0x00000265, 0x018E0100}, // PI_TVREF_SHORT_F2:RW:16:10:=0x018e PI_TDFI_CASEL_F2:RW:8:5:=0x01 PI_TDFI_CACSCA_F2:RW:0:5:=0x00 + { 0x00000266, 0x0F0F018E}, // PI_CALVL_VREF_INITIAL_STOP_POINT:RW:24:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT:RW:16:7:=0x1a PI_TVREF_LONG_F2:RW:0:10:=0x018e + { 0x00000267, 0x10010204}, // PI_TDFI_INIT_START_MIN:RW:24:8:=0x10 PI_CALVL_VREF_DELTA:RW:16:4:=0x01 PI_CALVL_VREF_NORMAL_STEPSIZE:RW:8:4:=0x02 PI_CALVL_VREF_INITIAL_STEPSIZE:RW:0:4:=0x04 + { 0x00000268, 0x09090605}, // PI_TDFI_CALVL_STROBE_F2:RW:24:4:=0x09 PI_TDFI_CALVL_STROBE_F1:RW:16:4:=0x09 PI_TDFI_CALVL_STROBE_F0:RW:8:4:=0x06 PI_TDFI_INIT_COMPLETE_MIN:RW:0:8:=0x05 +// { 0x00000268, 0x090906ff}, // PI_TDFI_CALVL_STROBE_F2:RW:24:4:=0x09 PI_TDFI_CALVL_STROBE_F1:RW:16:4:=0x09 PI_TDFI_CALVL_STROBE_F0:RW:8:4:=0x06 PI_TDFI_INIT_COMPLETE_MIN:RW:0:8:=0x05 + { 0x00000269, 0x20000202}, // PI_TDFI_INIT_START_F0:RW:24:8:=0x20 PI_SW_CA_TRAIN_VREF:RW:16:7:=0x00 PI_CALVL_STROBE_NUM:RW:8:5:=0x02 PI_TCKCKEH:RW:0:4:=0x02 + { 0x0000026A, 0x00201000}, // PI_TDFI_INIT_START_F1:RW:16:8:=0x20 PI_TDFI_INIT_COMPLETE_F0:RW:0:16:=0x1000 + { 0x0000026B, 0x00201000}, // PI_TDFI_INIT_START_F2:RW:16:8:=0x20 PI_TDFI_INIT_COMPLETE_F1:RW:0:16:=0x1000 + { 0x0000026C, 0x04041000}, // PI_INIT_STARTORCOMPLETE_2_CLKDISABLE:RW:24:8:=0x04 PI_CLKDISABLE_2_INIT_START:RW:16:8:=0x04 PI_TDFI_INIT_COMPLETE_F2:RW:0:16:=0x1000 + { 0x0000026D, 0x18020100}, // PI_TCKEHDQS_F1:RW:24:6:=0x18 PI_TCKEHDQS_F0:RW:16:6:=0x02 PI_REFRESH_BETWEEN_SEGMENT_DISABLE:RW_D:8:1:=0x01 PI_DRAM_CLK_DISABLE_DEASSERT_SEL:RW:0:1:=0x00 + { 0x0000026E, 0x00010118}, // PI_WDQLVL_BST_NUM:RW:16:3:=0x01 PI_WDQLVL_VREF_EN:RW:8:1:=0x01 PI_TCKEHDQS_F2:RW:0:6:=0x18 + { 0x0000026F, 0x004B004A}, // PI_TDFI_WDQLVL_RW:RW:16:10:=0x004b PI_TDFI_WDQLVL_WR:RW:0:10:=0x004a +// { 0x00000270, 0x0F010000}, // PI_WDQLVL_VREF_INITIAL_START_POINT:RW:24:7:=0x1a PI_WDQLVL_CS_MAP:RW:16:4:=0x01 PI_WDQLVL_ROTATE:RW:8:1:=0x00 PI_WDQLVL_RESP_MASK:RW:0:4:=0x00 + { 0x00000270, 0x0F050000}, // PI_WDQLVL_VREF_INITIAL_START_POINT:RW:24:7:=0x1a PI_WDQLVL_CS_MAP:RW:16:4:=0x01 PI_WDQLVL_ROTATE:RW:8:1:=0x00 PI_WDQLVL_RESP_MASK:RW:0:4:=0x00 + { 0x00000271, 0x0102040F}, // PI_WDQLVL_VREF_DELTA:RW:24:4:=0x01 PI_WDQLVL_VREF_NORMAL_STEPSIZE:RW:16:5:=0x02 PI_WDQLVL_VREF_INITIAL_STEPSIZE:RW:8:5:=0x04 PI_WDQLVL_VREF_INITIAL_STOP_POINT:RW:0:7:=0x1e + { 0x00000272, 0x34000000}, // PI_TDFI_WDQLVL_EN:RW:24:8:=0x34 PI_WDQLVL_CS:RW:16:2:=0x00 PI_WDQLVL_REQ:WR:8:1:=0x00 PI_WDQLVL_PERIODIC:RW:0:1:=0x00 + { 0x00000273, 0x00000000}, // PI_TDFI_WDQLVL_RESP:RW:0:32:=0x00000000 + { 0x00000274, 0x00000000}, // PI_TDFI_WDQLVL_MAX:RW:0:32:=0x00000000 + { 0x00000275, 0x00010000}, // PI_WDQLVL_ON_SREF_EXIT:RW:24:1:=0x00 PI_WDQLVL_EN:RW:16:2:=0x01 PI_WDQLVL_INTERVAL:RW:0:16:=0x0000 + +// 150819 : + { 0x00000276, (PI_MR3 <<24)|(PI_MR2 <<16)|(PI_MR1 <<8)|0x00}, // PI_MR3_DATA_F0_0:RW+:24:8:=0x31 PI_MR2_DATA_F0_0:RW+:16:8:=0x00 PI_MR1_DATA_F0_0:RW+:8:8:=0x00 PI_WDQLVL_ERROR_STATUS:RD:0:2:=0x00 + { 0x00000277, (PI_MR1 <<24)|(PI_MR14<<16)|(PI_MR12<<8)|(PI_MR11<<0)}, // PI_MR1_DATA_F1_0:RW+:24:8:=0x50 PI_MR14_DATA_F0_0:RW+:16:8:=0x11 PI_MR12_DATA_F0_0:RW+:8:8:=0x11 PI_MR11_DATA_F0_0:RW+:0:8:=0x00 + { 0x00000278, (PI_MR12<<24)|(PI_MR11<<16)|(PI_MR3 <<8)|(PI_MR2 <<0)}, // PI_MR12_DATA_F1_0:RW+:24:8:=0x11 PI_MR11_DATA_F1_0:RW+:16:8:=0x00 PI_MR3_DATA_F1_0:RW+:8:8:=0x31 PI_MR2_DATA_F1_0:RW+:0:8:=0x2d + { 0x00000279, (PI_MR3 <<24)|(PI_MR2 <<16)|(PI_MR1 <<8)|(PI_MR14<<0)}, // PI_MR3_DATA_F2_0:RW+:24:8:=0x31 PI_MR2_DATA_F2_0:RW+:16:8:=0x2d PI_MR1_DATA_F2_0:RW+:8:8:=0x50 PI_MR14_DATA_F1_0:RW+:0:8:=0x11 + { 0x0000027A, (PI_MR13<<24)|(PI_MR14<<16)|(PI_MR12<<8)|(PI_MR11<<0)}, // PI_MR13_DATA_0:RW+:24:8:=0x00 PI_MR14_DATA_F2_0:RW+:16:8:=0x11 PI_MR12_DATA_F2_0:RW+:8:8:=0x11 PI_MR11_DATA_F2_0:RW+:0:8:=0x00 + { 0x0000027B, (PI_MR11<<24)|(PI_MR3 <<16)|(PI_MR2 <<8)|(PI_MR1 <<0)}, // PI_MR11_DATA_F0_1:RW+:24:8:=0x00 PI_MR3_DATA_F0_1:RW+:16:8:=0x31 PI_MR2_DATA_F0_1:RW+:8:8:=0x00 PI_MR1_DATA_F0_1:RW+:0:8:=0x00 + { 0x0000027C, (PI_MR2 <<24)|(PI_MR1 <<16)|(PI_MR14<<8)|(PI_MR12<<0)}, // PI_MR2_DATA_F1_1:RW+:24:8:=0x2d PI_MR1_DATA_F1_1:RW+:16:8:=0x50 PI_MR14_DATA_F0_1:RW+:8:8:=0x11 PI_MR12_DATA_F0_1:RW+:0:8:=0x11 + { 0x0000027D, (PI_MR14<<24)|(PI_MR12<<16)|(PI_MR11<<8)|(PI_MR3 <<0)}, // PI_MR14_DATA_F1_1:RW+:24:8:=0x11 PI_MR12_DATA_F1_1:RW+:16:8:=0x11 PI_MR11_DATA_F1_1:RW+:8:8:=0x00 PI_MR3_DATA_F1_1:RW+:0:8:=0x31 + { 0x0000027E, (PI_MR11<<24)|(PI_MR3 <<16)|(PI_MR2 <<8)|(PI_MR1 <<0)}, // PI_MR11_DATA_F2_1:RW+:24:8:=0x00 PI_MR3_DATA_F2_1:RW+:16:8:=0x31 PI_MR2_DATA_F2_1:RW+:8:8:=0x2d PI_MR1_DATA_F2_1:RW+:0:8:=0x50 + { 0x0000027F, (PI_MR1 <<24)|(PI_MR13<<16)|(PI_MR14<<8)|(PI_MR12<<0)}, // PI_MR1_DATA_F0_2:RW+:24:8:=0x00 PI_MR13_DATA_1:RW+:16:8:=0x00 PI_MR14_DATA_F2_1:RW+:8:8:=0x11 PI_MR12_DATA_F2_1:RW+:0:8:=0x11 + { 0x00000280, (PI_MR12<<24)|(PI_MR11<<16)|(PI_MR3 <<8)|(PI_MR2 <<0)}, // PI_MR12_DATA_F0_2:RW+:24:8:=0x11 PI_MR11_DATA_F0_2:RW+:16:8:=0x00 PI_MR3_DATA_F0_2:RW+:8:8:=0x31 PI_MR2_DATA_F0_2:RW+:0:8:=0x00 + { 0x00000281, (PI_MR3 <<24)|(PI_MR2 <<16)|(PI_MR1 <<8)|(PI_MR14<<0)}, // PI_MR3_DATA_F1_2:RW+:24:8:=0x31 PI_MR2_DATA_F1_2:RW+:16:8:=0x2d PI_MR1_DATA_F1_2:RW+:8:8:=0x50 PI_MR14_DATA_F0_2:RW+:0:8:=0x11 + { 0x00000282, (PI_MR1 <<24)|(PI_MR14<<16)|(PI_MR12<<8)|(PI_MR11<<0)}, // PI_MR1_DATA_F2_2:RW+:24:8:=0x50 PI_MR14_DATA_F1_2:RW+:16:8:=0x11 PI_MR12_DATA_F1_2:RW+:8:8:=0x11 PI_MR11_DATA_F1_2:RW+:0:8:=0x00 + { 0x00000283, (PI_MR12<<24)|(PI_MR11<<16)|(PI_MR3 <<8)|(PI_MR2 <<0)}, // PI_MR12_DATA_F2_2:RW+:24:8:=0x11 PI_MR11_DATA_F2_2:RW+:16:8:=0x00 PI_MR3_DATA_F2_2:RW+:8:8:=0x31 PI_MR2_DATA_F2_2:RW+:0:8:=0x2d + { 0x00000284, (PI_MR2 <<24)|(PI_MR1 <<16)|(PI_MR13<<8)|(PI_MR14<<0)}, // PI_MR2_DATA_F0_3:RW+:24:8:=0x00 PI_MR1_DATA_F0_3:RW+:16:8:=0x00 PI_MR13_DATA_2:RW+:8:8:=0x00 PI_MR14_DATA_F2_2:RW+:0:8:=0x11 + { 0x00000285, (PI_MR14<<24)|(PI_MR12<<16)|(PI_MR11<<8)|(PI_MR3 <<0)}, // PI_MR14_DATA_F0_3:RW+:24:8:=0x11 PI_MR12_DATA_F0_3:RW+:16:8:=0x11 PI_MR11_DATA_F0_3:RW+:8:8:=0x00 PI_MR3_DATA_F0_3:RW+:0:8:=0x31 + { 0x00000286, (PI_MR11<<24)|(PI_MR3 <<16)|(PI_MR2 <<8)|(PI_MR1 <<0)}, // PI_MR11_DATA_F1_3:RW+:24:8:=0x00 PI_MR3_DATA_F1_3:RW+:16:8:=0x31 PI_MR2_DATA_F1_3:RW+:8:8:=0x2d PI_MR1_DATA_F1_3:RW+:0:8:=0x50 + { 0x00000287, (PI_MR2 <<24)|(PI_MR1 <<16)|(PI_MR14<<8)|(PI_MR12<<0)}, // PI_MR2_DATA_F2_3:RW+:24:8:=0x2d PI_MR1_DATA_F2_3:RW+:16:8:=0x50 PI_MR14_DATA_F1_3:RW+:8:8:=0x11 PI_MR12_DATA_F1_3:RW+:0:8:=0x11 + { 0x00000288, (PI_MR14<<24)|(PI_MR12<<16)|(PI_MR11<<8)|(PI_MR3 <<0)}, // PI_MR14_DATA_F2_3:RW+:24:8:=0x11 PI_MR12_DATA_F2_3:RW+:16:8:=0x11 PI_MR11_DATA_F2_3:RW+:8:8:=0x00 PI_MR3_DATA_F2_3:RW+:0:8:=0x31 + { 0x00000289, 0x00020000 |(PI_MR13<<0)}, // PI_ROW_DIFF:RW:16:3:=0x02 PI_BANK_DIFF:RW:8:2:=0x00 PI_MR13_DATA_3:RW+:0:8:=0x00 + +//150819-> //F0-F2 have same value + { 0x0000028A, (PI_TFC<<16)|(PI_TFC<<0)}, // PI_TFC_F1:RW:16:10:=0x018d PI_TFC_F0:RW:0:10:=0x0005 + { 0x0000028B, (PI_TRTP<<24)|(PI_TCCD<<16)|(PI_TFC<<0)}, // PI_TRTP_F0:RW:24:4:=0x08 PI_TCCD:RW:16:5:=0x08 PI_TFC_F2:RW:0:10:=0x018d + { 0x0000028C, (PI_TWR<<24) |(PI_TWTR<<16)|(PI_TRCD<<8)|(PI_TRP<<0)}, // PI_TWR_F0:RW:24:6:=0x04 PI_TWTR_F0:RW:16:6:=0x06 PI_TRCD_F0:RW:8:8:=0x04 PI_TRP_F0:RW:0:8:=0x03 + { 0x0000028D, (PI_TRAS_MIN<<24)|(PI_TRAS_MAX<<0)}, // PI_TRAS_MIN_F0:RW:24:8:=0x03 PI_TRAS_MAX_F0:RW:0:17:=0x000578 + { 0x0000028E, (PI_TMRW<<24) | (PI_TMRD<<16)|(PI_TCCDMW<<8)|(PI_TDQSCK_MAX<<0)}, // PI_TMRW_F0:RW:24:8:=0x0a PI_TMRD_F0:RW:16:6:=0x0a PI_TCCDMW_F0:RW:8:6:=0x20 PI_TDQSCK_MAX_F0:RW:0:4:=0x01 + { 0x0000028F, (PI_TWTR<<24) | (PI_TRCD<<16)|(PI_TRP<<8) |(PI_TRTP<<0)}, // PI_TWTR_F1:RW:24:6:=0x12 PI_TRCD_F1:RW:16:8:=0x1d PI_TRP_F1:RW:8:8:=0x22 PI_TRTP_F1:RW:0:4:=0x0c + { 0x00000290, (PI_TRAS_MAX<<8) | (PI_TWR<<0)}, // PI_TRAS_MAX_F1:RW:8:17:=0x01b207 PI_TWR_F1:RW:0:6:=0x1f + { 0x00000291, (PI_TMRD<<24) | (PI_TCCDMW<<16) | (PI_TDQSCK_MAX<<8)|(PI_TRAS_MIN<<0)}, // PI_TMRD_F1:RW:24:6:=0x17 PI_TCCDMW_F1:RW:16:6:=0x20 PI_TDQSCK_MAX_F1:RW:8:4:=0x06 PI_TRAS_MIN_F1:RW:0:8:=0x43 + { 0x00000292, (PI_TRCD<<24) | (PI_TRP<<16) | (PI_TRTP<<8)|(PI_TMRW<<0)}, // PI_TRCD_F2:RW:24:8:=0x1d PI_TRP_F2:RW:16:8:=0x22 PI_TRTP_F2:RW:8:4:=0x0c PI_TMRW_F1:RW:0:8:=0x0a + { 0x00000293, (PI_TWR<<8)|(PI_TWTR<<0)}, // PI_TWR_F2:RW:8:6:=0x1f PI_TWTR_F2:RW:0:6:=0x12 + { 0x00000294, (PI_TRAS_MIN<<24)|(PI_TRAS_MAX<<0)}, // PI_TRAS_MIN_F2:RW:24:8:=0x43 PI_TRAS_MAX_F2:RW:0:17:=0x01b207 + { 0x00000295, (PI_TMRW<<24) | (PI_TMRD<<16)|(PI_TCCDMW<<8)|(PI_TDQSCK_MAX<<0)}, // PI_TMRW_F2:RW:24:8:=0x0a PI_TMRD_F2:RW:16:6:=0x17 PI_TCCDMW_F2:RW:8:6:=0x20 PI_TDQSCK_MAX_F2:RW:0:4:=0x06 +//<- + { 0x00000296, 0x00020002}, // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02 + { 0x00000297, 0x00020002}, // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02 + { 0x00000298, 0x00020002}, // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02 + { 0x00000299, 0x00020002}, // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02 + { 0x0000029A, 0x00020002}, // RESERVED:RW_D:24:4:=0x00 RESERVED:RW_D:16:4:=0x02 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x02 + { 0x0000029B, 0x00000000}, // PI_INT_STATUS:RD:0:17:=0x000000 + { 0x0000029C, 0x00000000}, // PI_INT_ACK:WR:0:16:=0x0000 + { 0x0000029D, 0x00000000}, // PI_INT_MASK:RW:0:17:=0x000000 + { 0x0000029E, 0x00000000}, // PI_BIST_EXP_DATA:RD:0:128:=0x00000000 + { 0x0000029F, 0x00000000}, // PI_BIST_EXP_DATA:RD:0:128:=0x00000000 + { 0x000002A0, 0x00000000}, // PI_BIST_EXP_DATA:RD:0:128:=0x00000000 + { 0x000002A1, 0x00000000}, // PI_BIST_EXP_DATA:RD:0:128:=0x00000000 + { 0x000002A2, 0x00000000}, // PI_BIST_FAIL_DATA:RD:0:128:=0x00000000 + { 0x000002A3, 0x00000000}, // PI_BIST_FAIL_DATA:RD:0:128:=0x00000000 + { 0x000002A4, 0x00000000}, // PI_BIST_FAIL_DATA:RD:0:128:=0x00000000 + { 0x000002A5, 0x00000000}, // PI_BIST_FAIL_DATA:RD:0:128:=0x00000000 + { 0x000002A6, 0x00000000}, // PI_BIST_FAIL_ADDR:RD:0:34:=0x00000000 + { 0x000002A7, 0x01000400}, // PI_CTRLUPD_REQ_PER_AREF_EN:RW:24:1:=0x01 PI_LONG_COUNT_MASK:RW:16:5:=0x00 PI_BSTLEN:RW_D:8:5:=0x04 PI_BIST_FAIL_ADDR:RD:0:34:=0x00 + { 0x000002A8, 0x00008C00}, // PI_TDFI_CTRLUPD_MAX_F0:RW:8:16:=0x008c PI_TDFI_CTRLUPD_MIN:RD:0:4:=0x00 + { 0x000002A9, 0x00000578}, // PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00000578 + { 0x000002AA, 0x0000304C}, // PI_TDFI_CTRLUPD_MAX_F1:RW:0:16:=0x304c + { 0x000002AB, 0x0001E2F8}, // PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x0001e2f8 + { 0x000002AC, 0x0000304C}, // PI_TDFI_CTRLUPD_MAX_F2:RW:0:16:=0x304c + { 0x000002AD, 0x0001E2F8}, // PI_TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x0001e2f8 + { 0x000002AE, 0x04000001}, // PI_ADDR_SPACE:RW:24:6:=0x08 PI_BIST_RESULT:RD:16:2:=0x00 PI_BIST_GO:WR:8:1:=0x00 PI_UPDATE_ERROR_STATUS:RD:0:7:=0x00 + { 0x000002AF, 0x00000001}, // PI_BIST_ADDR_CHECK:RW:8:1:=0x01 PI_BIST_DATA_CHECK:RW:0:1:=0x00 + { 0x000002B0, 0x00000000}, // PI_BIST_START_ADDRESS:RW:0:34:=0x00000000 + { 0x000002B1, 0x00000000}, // PI_BIST_START_ADDRESS:RW:0:34:=0x00 +// { 0x000002B2, 0x00000000}, // PI_BIST_DATA_MASK:RW:0:64:=0x00000000 +// { 0x000002B3, 0x00000000}, // PI_BIST_DATA_MASK:RW:0:64:=0x00000000 + { 0x000002B2, 0xFFFFFFff}, // PI_BIST_DATA_MASK:RW:0:64:=0x00000000 + { 0x000002B3, 0xFFFFFFFF}, // PI_BIST_DATA_MASK:RW:0:64:=0x00000000 + { 0x000002B4, 0x00000001}, // PI_COL_DIFF:RW:0:4:=0x01 +}; + + + +static const uint32_t DDR_PHY_DDR_PHY_PVT_OVERWITE_1600[DDR_PHY_PVT_OVERWRITE_NUM][2] = +{ + +// By JTAG + { 0x0000071E, ((0x31 << 12) |(0x20 << 6) |( 0x12))}, // PHY_PAD_FDBK_TERM:RW+:0:18:= pvtr[4:0] 0x11, pvtn[5:0] 0x20, pvtp[5:0] 0x12 + { 0x0000071F, ((0x11 << 12) |(0x20 << 6) |( 0x12))}, // PHY_PAD_DATA_TERM:RW+:0:17:= pvtr[4:0] 0x11, pvtn[5:0] 0x20, pvtp[5:0] 0x12 + { 0x00000720, ((0x11 << 12) |(0x20 << 6) |( 0x12))}, // PHY_PAD_DQS_TERM:RW+:0:17:= pvtr[4:0] 0x11, pvtn[5:0] 0x20, pvtp[5:0] 0x12 + { 0x00000721, ((0x11 << 12) |(0x20 << 6) |( 0x12))}, // PHY_PAD_ADDR_TERM:RW+:0:18:= pvtr[4:0] 0x11, pvtn[5:0] 0x20, pvtp[5:0] 0x12 + { 0x00000722, ((0x11 << 12) |(0x20 << 6) |( 0x12))}, // PHY_PAD_CLK_TERM:RW+:0:18:= pvtr[4:0] 0x11, pvtn[5:0] 0x20, pvtp[5:0] 0x12 + { 0x00000724, ((0x11 << 12) |(0x20 << 6) |( 0x12))}, // PHY_PAD_CKE_TERM:RW+:0:18:= pvtr[4:0] 0x11, pvtn[5:0] 0x20, pvtp[5:0] 0x12 + { 0x00000726, ((0x11 << 12) |(0x20 << 6) |( 0x12))}, // PHY_PAD_RST_TERM:RW+:0:18:= pvtr[4:0] 0x11, pvtn[5:0] 0x20, pvtp[5:0] 0x12 + { 0x00000728, ((0x11 << 12) |(0x20 << 6) |( 0x12))}, // PHY_PAD_CS_TERM:RW+:0:18:= pvtr[4:0] 0x11, pvtn[5:0] 0x20, pvtp[5:0] 0x12 + +}; + +static const uint32_t DDR_SIP_SWAP_CH0[9+5][2] = +{ + { 0x00000420, 0x20741365}, // PHY_DQ_SWIZZLING_0:RW:0:32:=0x76543210 // SoC DQ7-0 -> SDRAM 20741365 : 00101101 : 2d -> d2 + { 0x000004A0, 0x34256107}, // PHY_DQ_SWIZZLING_1:RW:0:32:=0x76543210 // SoC DQ15-8 -> SDRAM 34256107 : 10010101 : 95 -> 6a + { 0x00000520, 0x57460321}, // PHY_DQ_SWIZZLING_2:RW:0:32:=0x76543210 // SoC DQ23-16 -> SDRAM 57460321 : 11000101 : c5 -> 3a + { 0x000005A0, 0x70614532}, // PHY_DQ_SWIZZLING_3:RW:0:32:=0x76543210 // SoC DQ31-24 -> SDRAM 70614532 : 10010110 : 96 -> 69 + { 0x0000061C, 0x00543210}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 // SoC AC5-0 -> DRAM 543210 + { 0x0000060C, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_0_0:RW:0:24:=0xdcba98 // SoC Byte0 -> DRAM Byte 0 + { 0x0000060D, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE1_0_0:RW:0:24:=0x000000 // SoC Byte1 -> DRAM Byte 1 + { 0x0000060E, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_1_0:RW:0:24:=0xdcba98 // SoC Byte2 -> DRAM Byte 2 + { 0x0000060F, 0x01DCBA98}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 3 + { 0x00000250, 0x01080000}, // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 +// { 0x0000040E, 0x6aca5a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 +// { 0x0000048E, 0x6aca5a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 +// { 0x0000050E, 0x693a5a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 +// { 0x0000058E, 0x693a5a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 + // MR15(inv_for_dql), MR20(inv_for_dqh), MR32(5a), MR40(3c) + { 0x0000040E, 0xd26a5a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 + { 0x0000048E, 0xd26a5a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 + { 0x0000050E, 0x3a695a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 + { 0x0000058E, 0x3a695a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 +}; + +static const uint32_t DDR_SIP_SWAP_CH1[9+5][2] = +{ + { 0x00000420, 0x23547610}, // PHY_DQ_SWIZZLING_0:RW:0:32:=0x76543210 // SoC DQ7-0 -> SDRAM 23547610 : 01101010 : 6a -> 95 + { 0x000004A0, 0x34526107}, // PHY_DQ_SWIZZLING_1:RW:0:32:=0x76543210 // SoC DQ15-8 -> SDRAM 34526107 : 10100101 : a5 -> 5a + { 0x00000520, 0x67452310}, // PHY_DQ_SWIZZLING_2:RW:0:32:=0x76543210 // SoC DQ23-16 -> SDRAM 67452310 : 01010110 : 56 -> a9 + { 0x000005A0, 0x32106754}, // PHY_DQ_SWIZZLING_3:RW:0:32:=0x76543210 // SoC DQ31-24 -> SDRAM 32106754 : 10100110 : a6 -> 59 + { 0x0000061C, 0x00543210}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 // SoC AC5-0 -> DRAM 543210 +// { 0x0000060C, 0x00543210}, // PHY_ADR_CALVL_SWIZZLE0_0_0:RW:0:24:=0xdcba98 // SoC Byte0 -> DRAM Byte 2 +// { 0x0000060D, 0x00543210}, // PHY_ADR_CALVL_SWIZZLE1_0_0:RW:0:24:=0x000000 // SoC Byte1 -> DRAM Byte 0 +// { 0x0000060E, 0x00543210}, // PHY_ADR_CALVL_SWIZZLE0_1_0:RW:0:24:=0xdcba98 // SoC Byte2 -> DRAM Byte 1 +//// { 0x0000060F, 0x02543210}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 3 +// { 0x0000060F, 0x01543210}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 3 + +// { 0x0000061C, 0x00dcba98}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 // SoC AC5-0 -> DRAM 543210 + { 0x0000060C, 0x00dcba98}, // PHY_ADR_CALVL_SWIZZLE0_0_0:RW:0:24:=0xdcba98 // SoC Byte0 -> DRAM Byte 2 + { 0x0000060D, 0x00dcba98}, // PHY_ADR_CALVL_SWIZZLE1_0_0:RW:0:24:=0x000000 // SoC Byte1 -> DRAM Byte 0 + { 0x0000060E, 0x00dcba98}, // PHY_ADR_CALVL_SWIZZLE0_1_0:RW:0:24:=0xdcba98 // SoC Byte2 -> DRAM Byte 1 + { 0x0000060F, 0x02dcba98}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 3 +// { 0x0000060F, 0x01dcba98}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 3 + + { 0x00000250, 0x01080000}, // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 +// { 0x0000040E, 0x59555a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 +// { 0x0000048E, 0x59555a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 +// { 0x0000050E, 0xa9595a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 +// { 0x0000058E, 0xa9595a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 + // MR15(inv_for_dql), MR20(inv_for_dqh), MR32(5a), MR40(3c) + { 0x0000040E, 0x955a5a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 + { 0x0000048E, 0x955a5a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 + { 0x0000050E, 0xa9595a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 + { 0x0000058E, 0xa9595a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 +}; + +static const uint32_t DDR_SIP_SWAP_CH2[9+5][2] = +{ + { 0x00000420, 0x30216754}, // PHY_DQ_SWIZZLING_0:RW:0:32:=0x76543210 // SoC DQ7-0 -> SDRAM 30216754 : 10010110 : 96 -> 69 + { 0x000004A0, 0x67453210}, // PHY_DQ_SWIZZLING_1:RW:0:32:=0x76543210 // SoC DQ15-8 -> SDRAM 67453210 : 01011010 : 5a -> a5 + { 0x00000520, 0x70165243}, // PHY_DQ_SWIZZLING_2:RW:0:32:=0x76543210 // SoC DQ23-16 -> SDRAM 70165243 : 10101001 : a9 -> 56 + { 0x000005A0, 0x07162345}, // PHY_DQ_SWIZZLING_3:RW:0:32:=0x76543210 // SoC DQ31-24 -> SDRAM 07162345 : 01100101 : 65 -> 9a + { 0x0000061C, 0x00543210}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 // SoC AC5-0 -> DRAM 543210 + { 0x0000060C, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_0_0:RW:0:24:=0xdcba98 // SoC Byte0 -> DRAM Byte 3 + { 0x0000060D, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE1_0_0:RW:0:24:=0x000000 // SoC Byte1 -> DRAM Byte 1 + { 0x0000060E, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_1_0:RW:0:24:=0xdcba98 // SoC Byte2 -> DRAM Byte 2 + { 0x0000060F, 0x01DCBA98}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 0 + { 0x00000250, 0x01080000}, // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 +// { 0x0000040E, 0xa5695a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 +// { 0x0000048E, 0xa5695a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 +// { 0x0000050E, 0x9a565a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 +// { 0x0000058E, 0x9a565a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 + // MR15(inv_for_dql), MR20(inv_for_dqh), MR32(5a), MR40(3c) + { 0x0000040E, 0x69a55a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 + { 0x0000048E, 0x69a55a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 + { 0x0000050E, 0x569a5a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 + { 0x0000058E, 0x569a5a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 +}; + +static const uint32_t DDR_SIP_SWAP_CH3[9+5][2] = +{ + { 0x00000420, 0x01327654}, // PHY_DQ_SWIZZLING_0:RW:0:32:=0x76543210 // SoC DQ7-0 -> SDRAM : 01327654 : 01101010 : 6a -> 95 + { 0x000004A0, 0x70615432}, // PHY_DQ_SWIZZLING_1:RW:0:32:=0x76543210 // SoC DQ15-8 -> SDRAM : 70615432 : 10011010 : 9a -> 65 + { 0x00000520, 0x54760123}, // PHY_DQ_SWIZZLING_2:RW:0:32:=0x76543210 // SoC DQ23-16 -> SDRAM : 54760123 : 10100101 : a5 -> 5a + { 0x000005A0, 0x07162345}, // PHY_DQ_SWIZZLING_3:RW:0:32:=0x76543210 // SoC DQ31-24 -> SDRAM : 07162345 : 01100101 : 65 -> 9a + { 0x0000061C, 0x00543210}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 // SoC AC5-0 -> DRAM 543210 + { 0x0000060C, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_0_0:RW:0:24:=0xdcba98 // SoC Byte0 -> DRAM Byte 3 + { 0x0000060D, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE1_0_0:RW:0:24:=0x000000 // SoC Byte1 -> DRAM Byte 1 + { 0x0000060E, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_1_0:RW:0:24:=0xdcba98 // SoC Byte2 -> DRAM Byte 2 + { 0x0000060F, 0x01DCBA98}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 0 + { 0x00000250, 0x01080000}, // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 +// { 0x0000040E, 0x65955a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 +// { 0x0000048E, 0x65955a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 +// { 0x0000050E, 0x9a5a5a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 +// { 0x0000058E, 0x9a5a5a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 + // MR15(inv_for_dql), MR20(inv_for_dqh), MR32(5a), MR40(3c) + { 0x0000040E, 0x95655a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 + { 0x0000048E, 0x95655a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 + { 0x0000050E, 0x5a9a5a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 + { 0x0000058E, 0x5a9a5a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 +}; + +static const uint32_t DDR_CA_DELAY[7][2] = +{ + { 0x0000061F, 0x0002A06E}, // PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x55 //CA0 delay this means 768/512 tCK delay for address bit + { 0x00000620, 0x02A002A0}, // PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA1/2 delay + { 0x00000621, 0x02A002A0}, // PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA3/4 delay + { 0x00000622, 0x000002A0}, // PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA5 delay + { 0x00000712, 0x0002A003}, // PHY_GRP_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_CSLVL_DLY_STEP:RW+:0:4:=0x03 //CS0 group delay + { 0x00000713, 0x02A002A0}, // PHY_GRP_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP_SLAVE_DELAY_1:RW+:0:11:=0x0300 //CS1/2 group delay + { 0x00000714, 0x000002A0}, // PHY_GRP_SLAVE_DELAY_3:RW+:0:11:=0x0300 //CS3 group delay +}; + + +static const uint32_t DDR_CA_DELAY_CH0[7][2] = +{ + { 0x0000061F, 0x0002c06E}, // PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x55 //CA0 delay this means 768/512 tCK delay for address bit + { 0x00000620, 0x02c002c0}, // PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA1/2 delay + { 0x00000621, 0x02c002c0}, // PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA3/4 delay + { 0x00000622, 0x000002c0}, // PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA5 delay + { 0x00000712, 0x0002c003}, // PHY_GRP_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_CSLVL_DLY_STEP:RW+:0:4:=0x03 //CS0 group delay + { 0x00000713, 0x02c002c0}, // PHY_GRP_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP_SLAVE_DELAY_1:RW+:0:11:=0x0300 //CS1/2 group delay + { 0x00000714, 0x000002c0}, // PHY_GRP_SLAVE_DELAY_3:RW+:0:11:=0x0300 //CS3 group delay +}; + +static const uint32_t DDR_CA_DELAY_CH1[7][2] = +{ + { 0x0000061F, 0x0002C06E}, // PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x55 //CA0 delay this means 768/512 tCK delay for address bit + { 0x00000620, 0x02C002C0}, // PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA1/2 delay + { 0x00000621, 0x02C002C0}, // PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA3/4 delay + { 0x00000622, 0x000002C0}, // PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA5 delay + { 0x00000712, 0x0002D003}, // PHY_GRP_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_CSLVL_DLY_STEP:RW+:0:4:=0x03 //CS0 group delay + { 0x00000713, 0x02D002D0}, // PHY_GRP_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP_SLAVE_DELAY_1:RW+:0:11:=0x0300 //CS1/2 group delay + { 0x00000714, 0x000002D0}, // PHY_GRP_SLAVE_DELAY_3:RW+:0:11:=0x0300 //CS3 group delay +}; + +static const uint32_t DDR_CA_DELAY_CH2[7][2] = +{ + { 0x0000061F, 0x0002C06E}, // PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x55 //CA0 delay this means 768/512 tCK delay for address bit + { 0x00000620, 0x02C002C0}, // PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA1/2 delay + { 0x00000621, 0x02C002C0}, // PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA3/4 delay + { 0x00000622, 0x000002C0}, // PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA5 delay + { 0x00000712, 0x0002C003}, // PHY_GRP_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_CSLVL_DLY_STEP:RW+:0:4:=0x03 //CS0 group delay + { 0x00000713, 0x02C002C0}, // PHY_GRP_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP_SLAVE_DELAY_1:RW+:0:11:=0x0300 //CS1/2 group delay + { 0x00000714, 0x000002C0}, // PHY_GRP_SLAVE_DELAY_3:RW+:0:11:=0x0300 //CS3 group delay +}; + +static const uint32_t DDR_CA_DELAY_CH3[7][2] = +{ + { 0x0000061F, 0x0002C06E}, // PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x55 //CA0 delay this means 768/512 tCK delay for address bit + { 0x00000620, 0x02C002C0}, // PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA1/2 delay + { 0x00000621, 0x02C002C0}, // PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA3/4 delay + { 0x00000622, 0x000002C0}, // PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA5 delay + { 0x00000712, 0x0002C003}, // PHY_GRP_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_CSLVL_DLY_STEP:RW+:0:4:=0x03 //CS0 group delay + { 0x00000713, 0x02C002C0}, // PHY_GRP_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP_SLAVE_DELAY_1:RW+:0:11:=0x0300 //CS1/2 group delay + { 0x00000714, 0x000002C0}, // PHY_GRP_SLAVE_DELAY_3:RW+:0:11:=0x0300 //CS3 group delay +}; + +#endif /* __INIT_DRAM_TBL_H3_ES10_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/H3/WS11/boot_init_dram_h3_ws11.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/H3/WS11/boot_init_dram_h3_ws11.c new file mode 100644 index 0000000..7670ef0 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/H3/WS11/boot_init_dram_h3_ws11.c @@ -0,0 +1,3304 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include //for uint32_t +#include //for uint32_t +#include //for uint32_t +#include "boot_init_dram_h3_ws11.h" +/////////////////////////////////////////////////////////// +// Board define +#define BOARD_SALVATOR_X +//#define BOARD_SALVATOR_M +//#define BOARD_KRIEK +#define DDR_ES1px 1 // 1:ES1.1 / 0:ES1.0 +//#define DDR_BACKUPMODE +#define DDR_QOSSETTING +/////////////////////////////////////////////////////////// +#include "init_dram_tbl_h3_ws11.h" +//#include "bit.h" +//#include "reg_rcarh3.h" +#define RCAR_DDR_VERSION "rev.0.15" +/////////////////////////////////////////////////////////// +#include +#define RST_BASE (0xE6160000U) +#define RST_MODEMR (RST_BASE + 0x0060U) +#define CPG_BASE (0xE6150000U) +#define CPG_PLLECR (CPG_BASE + 0x00D0U) +#define CPG_CPGWPR (CPG_BASE + 0x900U) +#define CPG_PLL3CR (CPG_BASE + 0x0DCU) +#define CPG_SRCR4 (CPG_BASE + 0x0BCU) +#define CPG_SRSTCLR4 (CPG_BASE + 0x950U) +/////////////////////////////////////////////////////////// +#define DDR_DEBUG_ES1P1 // ES1.1 debug code +/////////////////////////////////////////////////////////// +// Kriek board settings +#ifdef BOARD_KRIEK +#define DDR_PAD_NORMAL +#define DDR_2RANK +#else +#define DDR_WDQLVL_CHAB_SWAP_WA +#endif + +/////////////////////////////////////////////////////////// +#define DDR_ODT_SET 0x7170 +#ifdef DDR_2RANK // 2Rank +#define DDR_CSMAP 0xF +#define DDR_CSMAP_WDQLVL 0xF +#define DDR_CSMAP_RDLVL 0xF +#define DDR_CSMAP_GTLVL 0xF +#define DDR_CSMAP_WRLVL 0xF +#define DDR_CSMAP_CALVL 0xF +#else // 1Rank +#define DDR_CSMAP 0x5 +#define DDR_CSMAP_WDQLVL 0x5 +#define DDR_CSMAP_RDLVL 0x1 +#define DDR_CSMAP_GTLVL 0x1 +#define DDR_CSMAP_WRLVL 0x1 +#define DDR_CSMAP_CALVL 0x1 +#endif +#define DDR_LVLEN 0x1e +#define DDR_FDIV 0x0 +#define DDR_FDIVA 0x0 +//#define DDR_PLL3ONLY +#define DDR_DRIVE 0x1 +#define DDR_LPDDR4_EN_OFF_FIRST 0x1 +#define DDR_LP4_BOOT_DISABLE 0x1 +#ifdef DDR_PAD_NORMAL +#define DDR_PVTR_ADJ 0x8 +#else +#define DDR_PAD_BOOST 0x0 +#define DDR_PAD_ADDR_CS_DRIVE 0x7f2c +#define DDR_PVTR_ADJ 0x8 +#endif +#define DDR_RX_CAL_MAN 0x033f +#ifdef DDR_DEBUG_DBI +#define DDR_MR3 0xF1 +#else +#define DDR_MR3 0x31 +#endif +#ifdef DDR_PAD_NORMAL +#define DDR_MR11 0x36 +#else +#define DDR_MR11 0x32 +#endif +#define DDR_MR22 0x06 +#ifdef DDR_PAD_NORMAL +#define DDR_TSEL_SELECT 0x00006E0E +#ifdef BOARD_KRIEK +#define DDR_VREF 0x0F02 +#else +#define DDR_VREF 0x0F19 +#endif +#else +#define DDR_TSEL_SELECT 0x00002C0C +#define DDR_VREF 0x0F1F +#endif +#define DDR_PAD_CAL_WA +#ifdef DDR_PAD_NORMAL +#define DDR_PAD_CAL_WA2 +#endif +#define DDR_UPDT_WA 0x1c48 +#define DDR_FREQCHG +#define DDR_RDDQSDQ 0x0 +#define DDR_CALVLSIDE 0x2 +#define DDR_LOWDIV 0x4 +#define DDR_LOWFIX 0x17 +#define DDR_BPGRP 0x000 +#define DDR_BPCAD 0x000 +#ifdef BOARD_KRIEK +#define DRAM_CH_CNT 4 +#define DDR_PHYVALID 0x5 +#else +#define DRAM_CH_CNT 4 +#define DDR_PHYVALID 0xf +#endif +#define DDR_PHYMRW 0xf +#define DDR_TVAL0 0 +#define DDR_TVAL1 0 +#define DDR_TVAL2 0 +#define DDR_DBS_DFI_WA +#ifdef DDR_PAD_NORMAL +#define DDR_CAD 0x240 +#define DDR_GRP_A 0x240 +#define DDR_GRP_B 0x240 +#else +#define DDR_CAD 0x200 +#define DDR_GRP_A 0x200 +#define DDR_GRP_B 0x200 +#endif +#define DDR_PVTCODE_0 0x10 +#define DDR_PVTCODE_1 0x20 +#define DDR_PVTCODE_2 0x20 +#define DDR1600_CLK 0x2F // 1600 +#define DDR2400_CLK 0x47 // 2400 +#define DDR2800_CLK 0x53 // 2800 +#define DDR3200_CLK 0x5f // 3200 + +#define DDR_CACS_CAPTURE_CNT 0x02 +#define DDR_CACS_RESP_WAIT_CNT 0x00 +#define DDR_CACS_CCCP 0x2816 +#define DDR_CACS_START 0x280 +#define DDR_CACS_QTR 0x80 +#define DDR_CACS_STEP 0x03 +#define DBSC_REFINTS 0x1 +#define DBSC_DBSYSCONF1 0xE6790004 +#define DBSC_DBPHYCONF0 0xE6790010 +#define DBSC_DBKIND 0xE6790020 +#define DBSC_DBMEMCONF_0_0 0xE6790030 +#define DBSC_DBMEMCONF_0_1 0xE6790034 +#define DBSC_DBMEMCONF_1_0 0xE6790040 +#define DBSC_DBMEMCONF_1_1 0xE6790044 +#define DBSC_DBMEMCONF_2_0 0xE6790050 +#define DBSC_DBMEMCONF_2_1 0xE6790054 +#define DBSC_DBMEMCONF_3_0 0xE6790060 +#define DBSC_DBMEMCONF_3_1 0xE6790064 +#define DBSC_DBMEMCONF_0_2 0xE6790038 +#define DBSC_DBMEMCONF_0_3 0xE679003C +#define DBSC_DBMEMCONF_1_2 0xE6790048 +#define DBSC_DBMEMCONF_1_3 0xE679004C +#define DBSC_DBMEMCONF_2_2 0xE6790058 +#define DBSC_DBMEMCONF_2_3 0xE679005C +#define DBSC_DBMEMCONF_3_2 0xE6790068 +#define DBSC_DBMEMCONF_3_3 0xE679006C +#define DBSC_DBSTATE0 0xE6790108 +#define DBSC_DBACEN 0xE6790200 +#define DBSC_DBRFEN 0xE6790204 +#define DBSC_DBCMD 0xE6790208 +#define DBSC_DBWAIT 0xE6790210 +#define DBSC_DBTR0 0xE6790300 +#define DBSC_DBTR1 0xE6790304 +#define DBSC_DBTR3 0xE679030C +#define DBSC_DBTR4 0xE6790310 +#define DBSC_DBTR5 0xE6790314 +#define DBSC_DBTR6 0xE6790318 +#define DBSC_DBTR7 0xE679031C +#define DBSC_DBTR8 0xE6790320 +#define DBSC_DBTR9 0xE6790324 +#define DBSC_DBTR10 0xE6790328 +#define DBSC_DBTR11 0xE679032C +#define DBSC_DBTR12 0xE6790330 +#define DBSC_DBTR13 0xE6790334 +#define DBSC_DBTR14 0xE6790338 +#define DBSC_DBTR15 0xE679033C +#define DBSC_DBTR16 0xE6790340 +#define DBSC_DBTR17 0xE6790344 +#define DBSC_DBTR18 0xE6790348 +#define DBSC_DBTR19 0xE679034C +#define DBSC_DBTR20 0xE6790350 +#define DBSC_DBTR21 0xE6790354 +#define DBSC_DBTR22 0xE6790358 +#define DBSC_DBTR23 0xE679035C +#define DBSC_DBBL 0xE6790400 +#define DBSC_DBRFCNF1 0xE6790414 +#define DBSC_DBRFCNF2 0xE6790418 +#define DBSC_DBRNK0 0xE6790430 +#define DBSC_DBRNK1 0xE6790434 +#define DBSC_DBRNK2 0xE6790438 +#define DBSC_DBRNK3 0xE679043C +#define DBSC_DBRNK4 0xE6790440 +#define DBSC_DBRNK5 0xE6790444 +#define DBSC_DBRNK6 0xE6790448 +#define DBSC_DBADJ0 0xE6790500 +#define DBSC_DBADJ2 0xE6790508 +#define DBSC_DBDBICNT 0xE6790518 +#define DBSC_DBDFIPMSTRCNF 0xE6790520 +#define DBSC_DBPDLK_0 0xE6790620 +#define DBSC_DBPDLK_1 0xE6790660 +#define DBSC_DBPDLK_2 0xE67906a0 +#define DBSC_DBPDLK_3 0xE67906e0 +#define DBSC_INITCOMP_0 0xE6790600 +#define DBSC_INITCOMP_1 0xE6790640 +#define DBSC_INITCOMP_2 0xE6790680 +#define DBSC_INITCOMP_3 0xE67906C0 +#define DBSC_DBDFICNT_0 0xE6790604 +#define DBSC_DBDFICNT_1 0xE6790644 +#define DBSC_DBDFICNT_2 0xE6790684 +#define DBSC_DBDFICNT_3 0xE67906C4 +#define DBSC_DBPDCNT0_0 0xE6790610 +#define DBSC_DBPDCNT0_1 0xE6790650 +#define DBSC_DBPDCNT0_2 0xE6790690 +#define DBSC_DBPDCNT0_3 0xE67906D0 +#define DBSC_DBPDCNT_0 0xE679061C +#define DBSC_DBPDCNT_1 0xE679065C +#define DBSC_DBPDCNT_2 0xE679069C +#define DBSC_DBPDCNT_3 0xE67906DC +#define DBSC_DBPDRGA_0 0xE6790624 // +#define DBSC_DBPDRGD_0 0xE6790628 // +#define DBSC_DBPDRGA_1 0xE6790664 // +#define DBSC_DBPDRGD_1 0xE6790668 // +#define DBSC_DBPDRGA_2 0xE67906A4 // +#define DBSC_DBPDRGD_2 0xE67906A8 // +#define DBSC_DBPDRGA_3 0xE67906E4 // +#define DBSC_DBPDRGD_3 0xE67906E8 // +#define DBSC_DBBUS0CNF0 0xE6790800 +#define DBSC_DBBUS0CNF1 0xE6790804 +#define DBSC_DBCAM0CNF0 0xE6790900 +#define DBSC_DBCAM0CNF1 0xE6790904 +#define DBSC_DBCAM0CNF2 0xE6790908 +#define DBSC_DBCAM0CNF3 0xE679090C +#define DBSC_DBBCAMDIS 0xE67909FC +#define DBSC_DBSCHCNT0 0xE6791000 +#define DBSC_DBSCHCNT1 0xE6791004 +#define DBSC_DBSCHSZ0 0xE6791010 +#define DBSC_DBSCHRW0 0xE6791020 +#define DBSC_DBSCHRW1 0xE6791024 +#define DBSC_DBSCHQOS_0_0 0xE6791030 +#define DBSC_DBSCHQOS_0_1 0xE6791034 +#define DBSC_DBSCHQOS_0_2 0xE6791038 +#define DBSC_DBSCHQOS_0_3 0xE679103C +#define DBSC_DBSCHQOS_4_0 0xE6791070 +#define DBSC_DBSCHQOS_4_1 0xE6791074 +#define DBSC_DBSCHQOS_4_2 0xE6791078 +#define DBSC_DBSCHQOS_4_3 0xE679107C +#define DBSC_DBSCHQOS_9_0 0xE67910C0 +#define DBSC_DBSCHQOS_9_1 0xE67910C4 +#define DBSC_DBSCHQOS_9_2 0xE67910C8 +#define DBSC_DBSCHQOS_9_3 0xE67910CC +#define DBSC_DBSCHQOS_13_0 0xE6791100 +#define DBSC_DBSCHQOS_13_1 0xE6791104 +#define DBSC_DBSCHQOS_13_2 0xE6791108 +#define DBSC_DBSCHQOS_13_3 0xE679110C +#define DBSC_DBSCHQOS_14_0 0xE6791110 +#define DBSC_DBSCHQOS_14_1 0xE6791114 +#define DBSC_DBSCHQOS_14_2 0xE6791118 +#define DBSC_DBSCHQOS_14_3 0xE679111C +#define DBSC_DBSCHQOS_15_0 0xE6791120 +#define DBSC_DBSCHQOS_15_1 0xE6791124 +#define DBSC_DBSCHQOS_15_2 0xE6791128 +#define DBSC_DBSCHQOS_15_3 0xE679112C +#define DBSC_DBSCTR0 0xE6791700 +#define DBSC_DBSCTR1 0xE6791708 +#define DBSC_DBSCHRW2 0xE679170C +#define DBSC_SCFCTST0 0xE6791700 +#define DBSC_SCFCTST1 0xE6791708 +#define DBSC_SCFCTST2 0xE679170C +#define DBSC_DBMEMSWAPCONF0 0xE6792000 +#define DBSC_DBMONCONF4 0xE6793010 +#define DBSC_PLL_LOCK_0 0xE6794054 +#define DBSC_PLL_LOCK_1 0xE6794154 +#define DBSC_PLL_LOCK_2 0xE6794254 +#define DBSC_PLL_LOCK_3 0xE6794354 +#define DBSC_FREQ_CHG_ACK_0 0xE6790618 +#define DBSC_FREQ_CHG_ACK_1 0xE6790658 +#define DBSC_FREQ_CHG_ACK_2 0xE6790698 +#define DBSC_FREQ_CHG_ACK_3 0xE67906D8 +#define DBSC_DFI_FREQ_0 0xE6790614 +#define DBSC_DFI_FREQ_1 0xE6790654 +#define DBSC_DFI_FREQ_2 0xE6790694 +#define DBSC_DFI_FREQ_3 0xE67906D4 +//////////////////////////////////////////////////////////// +// 2800: RL=28,WL=14,nWR=30,nRTP=12 +#define DDR2800_PI_MR1 0xd4 //DeviceFeature1(Post=1.5tck nWR=30 RDpre=static WRPre=2tCK BL=16 // 1 101 0100 +#define DDR2800_PI_MR2 0x2d //DeviceFeature2(0,0SetA,101=WL14,101=RL28) // 0 0 101 101 +#define DDR2800_PI_TFC 0x00c8 // xxxx +#define DDR2800_PI_TRTP 0x0B +#define DDR2800_PI_TCCD 0x08 +#define DDR2800_PI_TWR 0x1A +#define DDR2800_PI_TWTR 0x0E +#define DDR2800_PI_TRCD 0x1A +#define DDR2800_PI_TRP 0x1E +#define DDR2800_PI_TRAS_MIN 0x3B +#define DDR2800_PI_TRAS_MAX 0x0db60 // xxxx +#define DDR2800_PI_TMRW 0x08 // xxxx +#define DDR2800_PI_TMRD 0x0c // xxxx +#define DDR2800_PI_TCCDMW 0x20 +#define DDR2800_PI_TDQSCK_MAX 0x03 +#define DDR2800_PI_RDLAT_ADJ 0x10 //??? +#define DDR2800_PI_CASLAT_LIN 0x50 +#define DDR2800_PI_WRLAT 0x0e +#define DDR2800_PI_WRLAT_ADJ 0x0c +/////////////////////////////////////////////////////////// +// 2400: RL=24,WL=12,nWR=24,nRTP=10 +#define DDR2400_PI_MR1 0xc4 //DeviceFeature1(Post=1.5tck nWR=24 RDpre=static WRPre=2tCK BL=16 // 1 100 0100 +#define DDR2400_PI_MR2 0x24 //DeviceFeature2(0,0SetA,100=WL12,100=RL24) // 0 0 100 100 +#define DDR2400_PI_TFC 0x00c8 // xxxx +#define DDR2400_PI_TRTP 0x09 +#define DDR2400_PI_TCCD 0x08 +#define DDR2400_PI_TWR 0x16 +#define DDR2400_PI_TWTR 0x0c +#define DDR2400_PI_TRCD 0x16 +#define DDR2400_PI_TRP 0x1a +#define DDR2400_PI_TRAS_MIN 0x33 +#define DDR2400_PI_TRAS_MAX 0x0db60 // xxxx +#define DDR2400_PI_TMRW 0x08 // xxxx +#define DDR2400_PI_TMRD 0x0c // xxxx +#define DDR2400_PI_TCCDMW 0x20 +#define DDR2400_PI_TDQSCK_MAX 0x03 +#define DDR2400_PI_RDLAT_ADJ 0x0e +#define DDR2400_PI_CASLAT_LIN 0x50 //PI_CASLAT_LIN_F2:RW:0:7:=0x1c +#define DDR2400_PI_WRLAT 0x0c //PI_WRLAT_F2:RW:16:5:=0x08 +#define DDR2400_PI_WRLAT_ADJ 0x0a +///////////////// +#define DDR1600_PI_MR1 0xa4 //MRW DeviceFeature1(Post=1.5tck nWR=16 RDpre=static WRPre=2tCK BL=16 +#define DDR1600_PI_MR2 0x52 //MRW DeviceFeature2(0,1SetB,010=WL12,010=RL14(nRTP14)) +#define DDR1600_PI_TFC 0x00c8 +#define DDR1600_PI_TRTP 0x08 +#define DDR1600_PI_TCCD 0x08 +#define DDR1600_PI_TWR 0x11 +#define DDR1600_PI_TWTR 0x0a +#define DDR1600_PI_TRCD 0x0f +#define DDR1600_PI_TRP 0x11 +#define DDR1600_PI_TRAS_MIN 0x22 +#define DDR1600_PI_TRAS_MAX 0x0db60 +#define DDR1600_PI_TMRW 0x08 //10 +#define DDR1600_PI_TMRD 0x0c +#define DDR1600_PI_TCCDMW 0x20 +#define DDR1600_PI_TDQSCK_MAX 0x3 +#define DDR1600_PI_RDLAT_ADJ 0x08 //PI_RDLAT_ADJ_F2:RW:16:8:=0x07 +#define DDR1600_PI_CASLAT_LIN 0x50 //PI_CASLAT_LIN_F2:RW:0:7:=0x1c +#define DDR1600_PI_WRLAT 0x0c //PI_WRLAT_F2:RW:16:5:=0x08 +#define DDR1600_PI_WRLAT_ADJ 0x0a +////////////////////////////////////////////////////////////////// +void InitDram_h3_ws11(void); +static void pvt_dbsc_regset(uint32_t freq); +static void pvt_manual_update(uint32_t flag); +static void set_cacs_delay(); +static void _rx_cal_code_set(uint32_t ch, uint32_t slice, uint8_t _cal_code_up[][4][16],uint8_t _cal_code_dn[][4][16]); +static void rx_cal_manual1(uint32_t chmask); +static void mode_register_set(uint32_t freq,uintptr_t phychno,uint32_t mr13_val); +static void _set_reg(uint32_t ch_mask, uint32_t regadd, uint32_t pos, uint32_t width, uint32_t val); +static void pvt_lvl_enable_set(uint32_t go); +static void pvt_freq_change_ack(uint32_t freq, uintptr_t phychno, uint32_t freq_flag); +static uint32_t pvt_pi_training_go_all_o(uint32_t freq); +inline void PLL3_FREQ(uint32_t freq,uint32_t freq_flag); +static uint32_t pvt_pi_training_go_all(uint32_t freq); +static uint32_t pvt_pi_training(uint32_t freq); +static void WaitDBCMD(void); +static void REG_DDRPHY_WRITE ( uintptr_t phyno, uint32_t regadd, uint32_t regdata); +static void change_lpddr4_en(uintptr_t phychno, uint32_t mode); +static void copy_csdelay(uint32_t phychno, uint32_t s_byte); +static void adjust_rddqsgatedelay(uintptr_t phychno); +static void copy_dqdelay(uintptr_t phychno, uint32_t s_byte, uint32_t d_byte); +static uint32_t pvt_pi_training_go_all_soft(uint32_t freq); +inline void dsb_sev(void); +static uint32_t REG_DDRPHY_READ ( uintptr_t phyno, uint32_t regadd); +#ifdef DDR_DEBUG_VREF +static uint32_t InitDDR_0917(uint32_t freq, uint32_t vref); +#else +static uint32_t InitDDR_0917(uint32_t freq); +#endif +//static void freq2800_reg_set(); +//static void freq2400_reg_set(); +static void freq1600_reg_set(); +#ifdef DDR_WDQLVL_CHAB_SWAP_WA +uint32_t wdqlvl(uint32_t phych_mask); +#endif +uint8_t cal_code_up[4][4][16]; +uint8_t cal_code_dn[4][4][16]; +uint8_t fst1[4][4][16]; +uint8_t lst0[4][4][16]; +uint32_t val[4][4][16][4]; +#ifdef DDR_BACKUPMODE +uint32_t ddrBackup; +#endif +static void SoftDelay_ddr(uint32_t loop) +{ + volatile uint32_t i; + for(i=0;i> 17)| + ((*((volatile uint32_t*)RST_MODEMR) & 0x00080000) >> 18); +#endif + } else { +#ifdef DDR_DEBUG_ODTMODE + md = ((*((volatile uint32_t*)RST_MODEMR) & 0x00020000) >> 17)| + ((*((volatile uint32_t*)RST_MODEMR) & 0x00080000) >> 18); +#else + md = (*((volatile uint32_t*)RST_MODEMR) & 0x000A0000) >> 17; + if(DDR_DEBUG_FREQ ==0){ + if (md == 0x0) { + } else if (md == 0x1) { + freq = DDR2800_CLK; + } else if (md == 0x4) { + freq = DDR2400_CLK; + } else { + freq = DDR1600_CLK; + } + } + else if(DDR_DEBUG_FREQ ==1){ + if (md == 0x0) { + } else if (md == 0x1) { + freq = DDR3166_CLK; + } else if (md == 0x4) { + freq = DDR3133_CLK; + } else { + freq = DDR3100_CLK; + } + } + else if(DDR_DEBUG_FREQ ==2){ + if (md == 0x0) { + freq = DDR3100_CLK; + } else if (md == 0x1) { + freq = DDR3200_CLK; + } else if (md == 0x4) { + freq = DDR3000_CLK; + } else { + freq = DDR2900_CLK; + } + } + else { + if (md == 0x0) { + freq = DDR1533_CLK; + } else if (md == 0x1) { + freq = DDR1433_CLK; + } else if (md == 0x4) { + freq = DDR1500_CLK; + } else { + freq = DDR1466_CLK; + } + } +#endif + } +#else + md = (*((volatile uint32_t*)RST_MODEMR) & 0x000A0000) >> 17; + if (md == 0x0) { + } else if (md == 0x1) { + freq = DDR2800_CLK; //MD19=0,MD17=1 : LPDDR4-2800 + NOTICE("BL2: DDR2800(%s)\n", RCAR_DDR_VERSION); + } else if (md == 0x4) { + freq = DDR2400_CLK; //MD19=1,MD17=0 : LPDDR4-2400 + NOTICE("BL2: DDR2400(%s)\n", RCAR_DDR_VERSION); + } else { + freq = DDR1600_CLK; //MD19=1,MD17=1 : LPDDR4-1600 + NOTICE("BL2: DDR1600(%s)\n", RCAR_DDR_VERSION); + } +#endif +#ifdef DDR_DEBUG_VREF + md = *(volatile uint32_t *)0xe6330004; + if((md&0xffff0000)==0xa5a50000){ + vref = md&0xfff; + } + InitDDR_0917(freq,vref); +#else + InitDDR_0917(freq); +#endif +} +static void pvt_dbsc_regset(uint32_t freq) +{ + *((volatile uint32_t*)DBSC_DBPDCNT0_0) = 0x00; + *((volatile uint32_t*)DBSC_DBPDCNT0_1) = 0x00; + *((volatile uint32_t*)DBSC_DBPDCNT0_2) = 0x00; + *((volatile uint32_t*)DBSC_DBPDCNT0_3) = 0x00; + *((volatile uint32_t*)DBSC_DBSTATE0) = 0x00000010; + *((volatile uint32_t*)DBSC_DBKIND) = 0x0000000a; //ddcg=a(lpddr4) + *((volatile uint32_t*)DBSC_DBBL) = 0x00000002; //BL=16(lpddr4) + + *((volatile uint32_t*)DBSC_DBMEMCONF_0_0) = 0x0f030a02; //memconf00(ch0/rank0) + *((volatile uint32_t*)DBSC_DBMEMCONF_0_1) = 0x0f030a02; //memconf01(ch0/rank1) + *((volatile uint32_t*)DBSC_DBMEMCONF_1_0) = 0x0f030a02; //memconf10(ch1/rank0) + *((volatile uint32_t*)DBSC_DBMEMCONF_1_1) = 0x0f030a02; //memconf11(ch1/rank1) + *((volatile uint32_t*)DBSC_DBMEMCONF_2_0) = 0x0f030a02; //memconf20(ch2/rank0) + *((volatile uint32_t*)DBSC_DBMEMCONF_2_1) = 0x0f030a02; //memconf21(ch2/rank1) + *((volatile uint32_t*)DBSC_DBMEMCONF_3_0) = 0x0f030a02; //memconf30(ch3/rank0) + *((volatile uint32_t*)DBSC_DBMEMCONF_3_1) = 0x0f030a02; //memconf31(ch3/rank1) + *((volatile uint32_t*)DBSC_DBMEMCONF_0_2) = 0x0f030a02; //memconf01(ch0/rank2) + *((volatile uint32_t*)DBSC_DBMEMCONF_0_3) = 0x0f030a02; //memconf01(ch0/rank3) + *((volatile uint32_t*)DBSC_DBMEMCONF_1_2) = 0x0f030a02; //memconf01(ch1/rank2) + *((volatile uint32_t*)DBSC_DBMEMCONF_1_3) = 0x0f030a02; //memconf01(ch1/rank3) + *((volatile uint32_t*)DBSC_DBMEMCONF_2_2) = 0x0f030a02; //memconf01(ch2/rank2) + *((volatile uint32_t*)DBSC_DBMEMCONF_2_3) = 0x0f030a02; //memconf01(ch2/rank3) + *((volatile uint32_t*)DBSC_DBMEMCONF_3_2) = 0x0f030a02; //memconf01(ch3/rank2) + *((volatile uint32_t*)DBSC_DBMEMCONF_3_3) = 0x0f030a02; //memconf01(ch3/rank3) + *((volatile uint32_t*)DBSC_DBPHYCONF0) = 0x00000001; //phyconf0 + if(freq>0x53) + { + // DDR3200 + *((volatile uint32_t*)DBSC_DBTR0) = 0x00000020; //dbtr0 cl=32 + *((volatile uint32_t*)DBSC_DBTR1) = 0x0000000e; //dbtr1 cwl=14 + *((volatile uint32_t*)DBSC_DBTR3) = 0x0000001d; //dbtr3 trcd=29 + *((volatile uint32_t*)DBSC_DBTR4) = 0x0022001d; //dbtr4 trpa=34 trp=29 + *((volatile uint32_t*)DBSC_DBTR5) = 0x00000060; //dbtr5 trc=102 + *((volatile uint32_t*)DBSC_DBTR6) = 0x00000044; //dbtr6 tras=68 + *((volatile uint32_t*)DBSC_DBTR7) = 0x00100010; //dbtr7 trrd_s=16 trrd=16 + *((volatile uint32_t*)DBSC_DBTR8) = 0x00000040; //dbtr8 tfaw=64 + *((volatile uint32_t*)DBSC_DBTR9) = 0x0000000c; //dbtr9 trdpr=12 + *((volatile uint32_t*)DBSC_DBTR10) = 0x0000001d; //dbtr10 twr=30 + *((volatile uint32_t*)DBSC_DBTR11) = 0x00000025; //dbtr11 trdwr=37 + *((volatile uint32_t*)DBSC_DBTR12) = 0x00270027; //dbtr12 twrrd_s=39 twrrd=39 + *((volatile uint32_t*)DBSC_DBTR13) = 0x00900120; //dbtr13 trfcpb=96 trfc=208 + *((volatile uint32_t*)DBSC_DBTR14) = 0x000c000c; //dbtr14 tckehdll=12 tckeh=12 + *((volatile uint32_t*)DBSC_DBTR15) = 0x001e000c; //dbtr15 tckesr=30 tckel=12 + *((volatile uint32_t*)DBSC_DBTR16) = 0x10400c0e; //dbtr16 + *((volatile uint32_t*)DBSC_DBTR17) = 0x080a0004; //dbtr17 tmodrd=8 tmod=10 trdmr=4 + *((volatile uint32_t*)DBSC_DBTR18) = 0x00000000; //dbtr18 No odt for DQ exists in LPDDR4. + *((volatile uint32_t*)DBSC_DBTR19) = 0x00000000; //dbtr19 tzqcl=0 tzqcs=0 because LPDDR4 doesn't support ZQC[SL]. + *((volatile uint32_t*)DBSC_DBTR20) = 0x012c012c; //dbtr20 txsdll=trfc+12=220 txs=220 + *((volatile uint32_t*)DBSC_DBTR21) = 0x00140014; //dbtr21 tccd_s=20 tccd=20 + *((volatile uint32_t*)DBSC_DBTR22) = 0x06400030; //dbtr22 tzqcal=1600 tzqlat=48 + } + else if(freq>0x47) + { + // DDR2800 + *((volatile uint32_t*)DBSC_DBTR0) = 0x0000001c; //dbtr0 cl=28 + *((volatile uint32_t*)DBSC_DBTR1) = 0x0000000e; //dbtr1 cwl=14 + *((volatile uint32_t*)DBSC_DBTR3) = 0x0000001a; //dbtr3 trcd=26 + *((volatile uint32_t*)DBSC_DBTR4) = 0x001e001a; //dbtr4 trpa=30 trp=26 + *((volatile uint32_t*)DBSC_DBTR5) = 0x00000055; //dbtr5 trc=85 + *((volatile uint32_t*)DBSC_DBTR6) = 0x0000003b; //dbtr6 tras=59 + *((volatile uint32_t*)DBSC_DBTR7) = 0x000f000f; //dbtr7 trrd_s=15 trrd=15 + *((volatile uint32_t*)DBSC_DBTR8) = 0x00000039; //dbtr8 tfaw=57 + *((volatile uint32_t*)DBSC_DBTR9) = 0x0000000c; //dbtr9 trdpr=12 + *((volatile uint32_t*)DBSC_DBTR10) = 0x0000001E; //dbtr10 twr=30 + *((volatile uint32_t*)DBSC_DBTR11) = 0x00000022; //dbtr11 trdwr=34 + *((volatile uint32_t*)DBSC_DBTR12) = 0x00260026; //dbtr12 twrrd_s=38 twrrd=38 + *((volatile uint32_t*)DBSC_DBTR13) = 0x007f00fd; //dbtr13 trfcpb=127 trfc=253 + *((volatile uint32_t*)DBSC_DBTR14) = 0x000c000c; //dbtr14 tckehdll=12 tckeh=12 + *((volatile uint32_t*)DBSC_DBTR15) = 0x0016000b; //dbtr15 tckesr=22 tckel=11 + *((volatile uint32_t*)DBSC_DBTR16) = 0x101f0c0e; //dbtr16 + *((volatile uint32_t*)DBSC_DBTR17) = 0x0c0f0020; //dbtr17 tmodrd=12 tmod=15 trdmr=32 + *((volatile uint32_t*)DBSC_DBTR18) = 0x00000000; //dbtr18 No odt for DQ exists in LPDDR4. + *((volatile uint32_t*)DBSC_DBTR19) = 0x00000000; //dbtr19 tzqcl=0 tzqcs=0 because LPDDR4 doesn't support ZQC[SL]. + *((volatile uint32_t*)DBSC_DBTR20) = 0x01070107; //dbtr20 txsdll=txs=tRFCab+7.5ns=263 + *((volatile uint32_t*)DBSC_DBTR21) = 0x000e000e; //dbtr21 tccd_s=14 tccd=14 + *((volatile uint32_t*)DBSC_DBTR22) = 0x06400030; //dbtr22 tzqcal=1600 tzqlat=48 + } + else if(freq>0x2f) + { + // DDR2400 + *((volatile uint32_t*)DBSC_DBTR0) = 0x00000018; //dbtr0 cl=24 + *((volatile uint32_t*)DBSC_DBTR1) = 0x0000000c; //dbtr1 cwl=12 + *((volatile uint32_t*)DBSC_DBTR3) = 0x00000016; //dbtr3 trcd=22 + *((volatile uint32_t*)DBSC_DBTR4) = 0x001a0016; //dbtr4 trpa=26 trp=22 + *((volatile uint32_t*)DBSC_DBTR5) = 0x00000049; //dbtr5 trc=73 + *((volatile uint32_t*)DBSC_DBTR6) = 0x00000033; //dbtr6 tras=51 + *((volatile uint32_t*)DBSC_DBTR7) = 0x000d000d; //dbtr7 trrd_s=13 trrd=13 + *((volatile uint32_t*)DBSC_DBTR8) = 0x00000031; //dbtr8 tfaw=49 + *((volatile uint32_t*)DBSC_DBTR9) = 0x0000000a; //dbtr9 trdpr=10 + *((volatile uint32_t*)DBSC_DBTR10) = 0x00000016; //dbtr10 twr=22 + *((volatile uint32_t*)DBSC_DBTR11) = 0x0000001c; //dbtr11 trdwr=28 + *((volatile uint32_t*)DBSC_DBTR12) = 0x00220022; //dbtr12 twrrd_s=34 twrrd=34 + *((volatile uint32_t*)DBSC_DBTR13) = 0x006d00d9; //dbtr13 trfcpb=109 trfc=217 + *((volatile uint32_t*)DBSC_DBTR14) = 0x000a000a; //dbtr14 tckehdll=10 tckeh=10 + *((volatile uint32_t*)DBSC_DBTR15) = 0x0013000c; //dbtr15 tckesr=19 tckel=12 + *((volatile uint32_t*)DBSC_DBTR16) = 0x08400a0c; //dbtr16 latency + *((volatile uint32_t*)DBSC_DBTR17) = 0x080a0004; //dbtr17 tmodrd=8 tmod=10 trdmr=4 + *((volatile uint32_t*)DBSC_DBTR18) = 0x00000000; //dbtr18 No odt for DQ exists in LPDDR4. + *((volatile uint32_t*)DBSC_DBTR19) = 0x00000000; //dbtr19 tzqcl=0 tzqcs=0 because LPDDR4 doesn't support ZQC[SL]. + *((volatile uint32_t*)DBSC_DBTR20) = 0x00e200e2; //dbtr20 txsdll=txs=tRFCab+7.5ns=226 + *((volatile uint32_t*)DBSC_DBTR21) = 0x000C000C; //dbtr21 tccd_s=12 tccd=12 + *((volatile uint32_t*)DBSC_DBTR22) = 0x04b10025; //dbtr22 tzqcal=1201 tzqlat=37 + } + else + { + // DDR1600 + *((volatile uint32_t*)DBSC_DBTR0) = 0x0000000e; //dbtr0 cl=14 + *((volatile uint32_t*)DBSC_DBTR1) = 0x0000000c; //dbtr1 cwl=c + *((volatile uint32_t*)DBSC_DBTR3) = 0x0000000f; //dbtr3 trcd=15 + *((volatile uint32_t*)DBSC_DBTR4) = 0x0011000f; //dbtr4 trpa=17 trp=15 + *((volatile uint32_t*)DBSC_DBTR5) = 0x00000030; //dbtr5 trc=48 + *((volatile uint32_t*)DBSC_DBTR6) = 0x00000022; //dbtr6 tras=34 + *((volatile uint32_t*)DBSC_DBTR7) = 0x00080008; //dbtr7 trrd_s=8 trrd=8 + *((volatile uint32_t*)DBSC_DBTR8) = 0x00000020; //dbtr8 tfaw=32 + *((volatile uint32_t*)DBSC_DBTR9) = 0x00000006; //dbtr9 trdpr=6 + *((volatile uint32_t*)DBSC_DBTR10) = 0x0000000f; //dbtr10 twr=15 + *((volatile uint32_t*)DBSC_DBTR11) = 0x00000011; //dbtr11 trdwr=17 + *((volatile uint32_t*)DBSC_DBTR12) = 0x001D001D; //dbtr12 twrrd_s=29 + *((volatile uint32_t*)DBSC_DBTR13) = 0x00480090; //dbtr13 trfcpb=72 trfcab=144 + *((volatile uint32_t*)DBSC_DBTR14) = 0x00060006; //dbtr14 tckehdll=6 + *((volatile uint32_t*)DBSC_DBTR15) = 0x000c0006; //dbtr15 tckesr=12 + *((volatile uint32_t*)DBSC_DBTR16) = 0x06200a0C; //dbtr16 + *((volatile uint32_t*)DBSC_DBTR17) = 0x080a0004; //dbtr17 tmodrd=8 tmod=10 trdmr=4 + *((volatile uint32_t*)DBSC_DBTR18) = 0x00000000; //dbtr18 No odt for DQ exists in LPDDR4. + *((volatile uint32_t*)DBSC_DBTR19) = 0x00000000; //dbtr19 tzqcl=0 tzqcs=0 because LPDDR4 doesn't support ZQC[SL]. + *((volatile uint32_t*)DBSC_DBTR20) = 0x00b00096; //dbtr20 txsdll=150 + *((volatile uint32_t*)DBSC_DBTR21) = 0x000b000b; //dbtr21 tccd_s=11 tccd=11 + *((volatile uint32_t*)DBSC_DBTR22) = 0x03200018; //dbtr22 tzqcal=800 tzqlat=24 + } + *((volatile uint32_t*)DBSC_DBRNK0) = 0x00000000; //dbrnk0 + *((volatile uint32_t*)DBSC_DBRNK1) = 0x00000000; //dbrnk1 + *((volatile uint32_t*)DBSC_DBRNK2) = 0x00008888; //dbrnk2 rkrr=8 + *((volatile uint32_t*)DBSC_DBRNK3) = 0x00008888; //dbrnk3 rkrw=8 + *((volatile uint32_t*)DBSC_DBRNK4) = 0x00008888; //dbrnk4 rkwr=8 + *((volatile uint32_t*)DBSC_DBRNK5) = 0x00008888; //dbrnk5 rkww=8 + *((volatile uint32_t*)DBSC_DBRNK6) = 0x00000000; //dbrnk6 Use ALL Rank + + *((volatile uint32_t*)DBSC_DBADJ0) = 0x00000000; //dbadj0 No Optional setting + *((volatile uint32_t*)DBSC_DBADJ2) = 0x00000000; //dbadj2 No Optional setting +#ifdef DDR_DEBUG_ES1P1 + if(((*((volatile uint32_t*)0xFFF00044)) & 0x00007FFF ) == 0x00004F00) { + *((volatile uint32_t*)DBSC_DBBCAMDIS) = 0x00000002; //sc disable try + } else { + *((volatile uint32_t*)DBSC_DBBCAMDIS) = 0x00000004; //Simple mode + } +#else //DDR_DEBUG_ES1P1 +#if DDR_ES1px==1 + *((volatile uint32_t*)DBSC_DBBCAMDIS) = 0x00000004; //Simple mode +#else //DDR_ES1px==1 + *((volatile uint32_t*)DBSC_DBBCAMDIS) = 0x00000002; //sc disable try +#endif //DDR_ES1px==1 +#endif //DDR_DEBUG_ES1P1 +#ifdef DDR_QOSSETTING +// *((volatile uint32_t*)DBSC_DBCAM0CNF0) = 0x00000000; //dbcam0cnf0 + *((volatile uint32_t*)DBSC_DBCAM0CNF1) = 0x00044218; //dbcam0cnf1 + *((volatile uint32_t*)DBSC_DBCAM0CNF2) = 0x000000F4; //dbcam0cnf2 +// *((volatile uint32_t*)DBSC_DBCAM0CNF3) = 0x00000003; // + *((volatile uint32_t*)DBSC_DBSCHCNT0) = 0x080F003F; //dbschcnt0 + *((volatile uint32_t*)DBSC_DBSCHCNT1) = 0x00001010; //dbschcnt1 + *((volatile uint32_t*)DBSC_DBSCHSZ0) = 0x00000001; //dbschsz0 + *((volatile uint32_t*)DBSC_DBSCHRW0) = 0xF7311111; //dbschrw0 + *((volatile uint32_t*)DBSC_DBSCHRW1) = 0x00000037; //dbschrw1 +//QoS Settings + *((volatile uint32_t*)DBSC_DBSCHQOS_0_0) = 0x0000F000; //dbschqos00 + *((volatile uint32_t*)DBSC_DBSCHQOS_0_1) = 0x0000E000; //dbschqos01 + *((volatile uint32_t*)DBSC_DBSCHQOS_0_2) = 0x00007000; //dbschqos02 + *((volatile uint32_t*)DBSC_DBSCHQOS_0_3) = 0x00000000; //dbschqos03 + *((volatile uint32_t*)DBSC_DBSCHQOS_4_0) = 0x0000F000; //dbschqos40 + *((volatile uint32_t*)DBSC_DBSCHQOS_4_1) = 0x0000EFFF; //dbschqos41 + *((volatile uint32_t*)DBSC_DBSCHQOS_4_2) = 0x0000B000; //dbschqos42 + *((volatile uint32_t*)DBSC_DBSCHQOS_4_3) = 0x00000000; //dbschqos43 + *((volatile uint32_t*)DBSC_DBSCHQOS_9_0) = 0x0000F000; //dbschqos90 + *((volatile uint32_t*)DBSC_DBSCHQOS_9_1) = 0x0000EFFF; //dbschqos91 + *((volatile uint32_t*)DBSC_DBSCHQOS_9_2) = 0x0000D000; //dbschqos92 + *((volatile uint32_t*)DBSC_DBSCHQOS_9_3) = 0x00000000; //dbschqos93 + *((volatile uint32_t*)DBSC_DBSCHQOS_13_0) = 0x0000F000; //dbschqos130 + *((volatile uint32_t*)DBSC_DBSCHQOS_13_1) = 0x0000EFFF; //dbschqos131 + *((volatile uint32_t*)DBSC_DBSCHQOS_13_2) = 0x0000E800; //dbschqos132 + *((volatile uint32_t*)DBSC_DBSCHQOS_13_3) = 0x00007000; //dbschqos133 + *((volatile uint32_t*)DBSC_DBSCHQOS_14_0) = 0x0000F000; //dbschqos140 + *((volatile uint32_t*)DBSC_DBSCHQOS_14_1) = 0x0000EFFF; //dbschqos141 + *((volatile uint32_t*)DBSC_DBSCHQOS_14_2) = 0x0000E800; //dbschqos142 + *((volatile uint32_t*)DBSC_DBSCHQOS_14_3) = 0x00007000; //dbschqos143 + *((volatile uint32_t*)DBSC_DBSCHQOS_15_0) = 0x000007D0; //dbschqos150 + *((volatile uint32_t*)DBSC_DBSCHQOS_15_1) = 0x000007CF; //dbschqos151 + *((volatile uint32_t*)DBSC_DBSCHQOS_15_2) = 0x000005D0; //dbschqos152 + *((volatile uint32_t*)DBSC_DBSCHQOS_15_3) = 0x000003D0; //dbschqos153 +#endif + *((volatile uint32_t*)DBSC_DBSYSCONF1) = 0x00000002; //dbsysconf1 freqratio=2. + *((volatile uint32_t*)DBSC_DBCAM0CNF1) = 0x00044218; //wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) + *((volatile uint32_t*)DBSC_DBCAM0CNF2) = 0x00000284; //rg_scexp[15:0] 0,0(fillunit),8(dirtymax),4(dirtymin) +#if DDR_ES1px==1 +#ifdef DDR_DEBUG_ES1P1 + if(((*((volatile uint32_t*)0xFFF00044)) & 0x00007FFF ) != 0x00004F00) { + *((volatile uint32_t*)DBSC_DBTR21) = 0x00080008; //dbtr21 tccd_s=8 tccd=8 + *((volatile uint32_t*)DBSC_DBTR23) = 0x00000002; //dbtr23 + *((volatile uint32_t*)DBSC_DBMONCONF4 ) = 0x00700000 | (*((volatile uint32_t*)DBSC_DBMONCONF4 )); + } +#else + //ES1.1 : rg_mnstatsel setting change + *((volatile uint32_t*)DBSC_DBTR21) = 0x00080008; //dbtr21 tccd_s=8 tccd=8 + *((volatile uint32_t*)DBSC_DBTR23) = 0x00000002; //dbtr23 + *((volatile uint32_t*)DBSC_DBMONCONF4 ) = 0x00700000 | (*((volatile uint32_t*)DBSC_DBMONCONF4 )); +#endif +#else // ES1px==0 +#ifdef DDR_DEBUG_ES1P1 + if(((*((volatile uint32_t*)0xFFF00044)) & 0x00007FFF ) != 0x00004F00) { + *((volatile uint32_t*)DBSC_DBTR21) = 0x00080008; //dbtr21 tccd_s=8 tccd=8 + *((volatile uint32_t*)DBSC_DBTR23) = 0x00000002; //dbtr23 + *((volatile uint32_t*)DBSC_DBMONCONF4 ) = 0x00700000 | (*((volatile uint32_t*)DBSC_DBMONCONF4 )); + } +#endif +#endif + if(freq>0x53) + { + // DDR3200 +#ifdef DDR_QOSSETTING + *((volatile uint32_t*)DBSC_DBSCHRW0) = 0xF7311111; //stop_tolerance, independent of dram freq + *((volatile uint32_t*)DBSC_DBSCHRW1) = 0x00000048; //[15: 8]=trfcpb/4; [ 7: 0]=trfcab/4 ; + *((volatile uint32_t*)DBSC_SCFCTST2) = 0x111f1fff; //rd-wr/wr-rd toggle count, independent of dram freq +#endif + *((volatile uint32_t*)DBSC_SCFCTST0) = 0x18030d09; //[31:24]=trc/4 ; [23:16]=trda->act/4; [15:8]=twra->act/4; [7:0]=trp/4 + *((volatile uint32_t*)DBSC_SCFCTST1) = 0x090a080c; //[31:24]=trdwr/4 ; [23:16]=twrrd/4 ; [15:8]=trcd/4 ; [7:0]=asyncofs + } + else if(freq>0x47) + { + // DDR2800 +#ifdef DDR_QOSSETTING + *((volatile uint32_t*)DBSC_DBSCHRW0) = 0xF7311111; //stop_tolerance, independent of dram freq + *((volatile uint32_t*)DBSC_DBSCHRW1) = 0x00018248; //[15: 8]=trfcpb/4; [ 7: 0]=trfcab/4 ; + *((volatile uint32_t*)DBSC_SCFCTST2) = 0x000F0FFF; //rd-wr/wr-rd toggle count, independent of dram freq +#endif +// *((volatile uint32_t*)DBSC_SCFCTST0) = 0x180b1508; //[31:24]=trc/2.5=18 ; [23:16]=trda->act/2.5=11; [15:8]=twra->act/2.5=21; [7:0]=trp/2.5=8 + *((volatile uint32_t*)DBSC_SCFCTST0) = 0x180b1408; //[31:24]=trc/2.5=18 ; [23:16]=trda->act/2.5=11; [15:8]=twra->act/2.5=21; [7:0]=trp/2.5=8 + *((volatile uint32_t*)DBSC_SCFCTST1) = 0x0a0b080C; //[31:24]=trdwr/2.5=9 ; [23:16]=twrrd/2.5=16 ; [15:8]=trcd/2.5=8 ; [7:0]=asyncofs + } + else if(freq>0x2f) + { + // DDR2400 +#ifdef DDR_QOSSETTING + *((volatile uint32_t*)DBSC_DBSCHRW0) = 0x22421111; //stop_tolerance, independent of dram freq + *((volatile uint32_t*)DBSC_DBSCHRW1) = 0x00180034; //[15: 8]=trfcpb/4; [ 7: 0]=trfcab/4 ; + *((volatile uint32_t*)DBSC_SCFCTST2) = 0x012F1123; //rd-wr/wr-rd toggle count, independent of dram freq +#endif + *((volatile uint32_t*)DBSC_SCFCTST0) = 0x180B1708; //[31:24]=trc/4 ; [23:16]=trda->act/4; [15:8]=twra->act/4; [7:0]=trp/4 + *((volatile uint32_t*)DBSC_SCFCTST1) = 0x0808070C; //[31:24]=trdwr/4 ; [23:16]=twrrd/4 ; [15:8]=trcd/4 ; [7:0]=asyncofs + } + else + { +#ifdef DDR_QOSSETTING + *((volatile uint32_t*)DBSC_DBSCHRW0) = 0xF7311111; //stop_tolerance, independent of dram freq + *((volatile uint32_t*)DBSC_DBSCHRW1) = 0x00000024; //[15: 8]=trfcpb/4; [ 7: 0]=trfcab/4 ; + *((volatile uint32_t*)DBSC_SCFCTST2) = 0x000F0FFF; //rd-wr/wr-rd toggle count, independent of dram freq +#endif + *((volatile uint32_t*)DBSC_SCFCTST0) = 0x0c020905; //[31:24]=trc/4 ; [23:16]=trda->act/4; [15:8]=twra->act/4; [7:0]=trp/4 + *((volatile uint32_t*)DBSC_SCFCTST1) = 0x0508040C; //[31:24]=trdwr/4 ; [23:16]=twrrd/4 ; [15:8]=trcd/4 ; [7:0]=asyncofs + } +} +static void pvt_manual_update(uint32_t flag) +{ + if(flag&0x1) {REG_DDRPHY_WRITE(0,0x702,REG_DDRPHY_READ(0,0x702) | (1<<16));}; + if(flag&0x2) {REG_DDRPHY_WRITE(1,0x702,REG_DDRPHY_READ(1,0x702) | (1<<16));}; + if(flag&0x4) {REG_DDRPHY_WRITE(2,0x702,REG_DDRPHY_READ(2,0x702) | (1<<16));}; + if(flag&0x8) {REG_DDRPHY_WRITE(3,0x702,REG_DDRPHY_READ(3,0x702) | (1<<16));}; + if(flag&0x10) {REG_DDRPHY_WRITE(0,0x732,REG_DDRPHY_READ(0,0x732) | (1<<16));}; + if(flag&0x20) {REG_DDRPHY_WRITE(1,0x732,REG_DDRPHY_READ(1,0x732) | (1<<16));}; + if(flag&0x40) {REG_DDRPHY_WRITE(2,0x732,REG_DDRPHY_READ(2,0x732) | (1<<16));}; + if(flag&0x80) {REG_DDRPHY_WRITE(3,0x732,REG_DDRPHY_READ(3,0x732) | (1<<16));}; +} +static void set_cacs_delay() +{ + uint32_t i,f,dataL; + REG_DDRPHY_WRITE (0,0x00000700,0x0301); + REG_DDRPHY_WRITE (1,0x00000700,0x0301); + REG_DDRPHY_WRITE (2,0x00000700,0x0301); + REG_DDRPHY_WRITE (3,0x00000700,0x0301); + for (i=0;i=rx_cal_val) + { + cal_code_up[ch][slice][index]=rx_cal_val; + cal_code_dn[ch][slice][index]=2*rx_cal_val-trial; + } + else + { + cal_code_up[ch][slice][index]=trial; + cal_code_dn[ch][slice][index]=rx_cal_val; + } + } + _rx_cal_code_set(ch,slice,cal_code_up,cal_code_dn); + } + } + for(ch=0;ch>16); + for(index=0;index<11;index++) + { + if(cal_obs&(1<>1; + if(trial>=rx_cal_val) + { + cal_code_up[ch][slice][index]=rx_cal_val; + cal_code_dn[ch][slice][index]=2*rx_cal_val-trial; + } + else + { + cal_code_up[ch][slice][index]=trial; + cal_code_dn[ch][slice][index]=rx_cal_val; + } + } + } + _rx_cal_code_set(ch,slice,cal_code_up,cal_code_dn); + } + } + for(ch=0;ch>16); + else dataL=o_dataL; + dataL&=0xffff; + } + } + } + } +} +static void mode_register_set(uint32_t freq,uintptr_t phychno,uint32_t mr13_val) +{ + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e040d00|(0x00100000 * phychno)|mr13_val; + WaitDBCMD(); + if(freq>0x47) + { + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e0401d4|(0x00100000 * phychno); + } + else if (freq > 0x2f) + { + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e0401c4|(0x00100000 * phychno); + } + else + { + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e0401a4|(0x00100000 * phychno); + } + WaitDBCMD(); + if(freq>0x47) + { + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e04022e|(0x00100000 * phychno); + } + else if (freq > 0x2f) + { + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e040224|(0x00100000 * phychno); + } + else + { + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e040252|(0x00100000 * phychno); + } + WaitDBCMD(); + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e040300|(0x00100000 * phychno)|DDR_MR3; + WaitDBCMD(); + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e040b00|(0x00100000 * phychno)|DDR_MR11; + WaitDBCMD(); + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e040c11|(0x00100000 * phychno); + WaitDBCMD(); + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e040e11|(0x00100000 * phychno); + WaitDBCMD(); + *((volatile uint32_t*)DBSC_DBCMD) = 0x0e041600|(0x00100000 * phychno)|DDR_MR22; + WaitDBCMD(); +} +static void _set_reg(uint32_t ch_mask, uint32_t regadd, uint32_t pos, uint32_t width, uint32_t val) +{ + int ch; + uint32_t dataL; + uintptr_t valids; + uintptr_t valids_shift; + valids=(1ULL<0) + { + wait_count[phychno]--; + dataL = REG_DDRPHY_READ ( phychno, 0x0000029B); + if(dataL&0x1) + { + phytrainingok |= (0x1<>24)+((DDR_TVAL0>>12)&0x0f))&0x0f; + REG_DDRPHY_WRITE(phychno, 0x414 + 0x80*i, (REG_DDRPHY_READ(phychno, 0x414 + 0x80*i)&0xf0ffffff) | (j<<24)); + } + } + if(DDR_TVAL0&0x80) + { + for(phychno=0;phychno=TR_ERR) + { + phytrainingok&=~(1<=TE_ERR) + { + phytrainingok&=~(1<0) + { + for(phychno=0;phychno=4) + { + from=0; to=3; + } + else + { + from=phychno; to=phychno; + } + for(i=from;i<=to;i++) + { +#ifdef DDR_LPDDR4_EN_OFF_FIRST + set = 1ULL <<14; + clr = ~set; + if(!mode) + { + set = 0; + }; + addr=0x71c; REG_DDRPHY_WRITE(i,addr,dataL=((REG_DDRPHY_READ(i,addr)&clr)|set) ); + addr=0x71d; REG_DDRPHY_WRITE(i,addr,dataL=((REG_DDRPHY_READ(i,addr)&clr)|set) ); + addr=0x723; REG_DDRPHY_WRITE(i,addr,dataL=((REG_DDRPHY_READ(i,addr)&clr)|set) ); + addr=0x727; REG_DDRPHY_WRITE(i,addr,dataL=((REG_DDRPHY_READ(i,addr)&clr)|set) ); +#else + addr=0x71c; REG_DDRPHY_WRITE(i,addr,dataL=0x00027B22 ); + addr=0x71d; REG_DDRPHY_WRITE(i,addr,dataL=0x00047B22 ); + addr=0x723; REG_DDRPHY_WRITE(i,addr,dataL=0x00027B22 ); + addr=0x727; REG_DDRPHY_WRITE(i,addr,dataL=0x00027B22 ); +#endif + } +} +static void copy_csdelay(uint32_t phychno, uint32_t s_byte) +{ + uint32_t dataL[4]; + dataL[0] = ((REG_DDRPHY_READ ( phychno, 0x00000712))& 0x000fff00) >> 8; + dataL[1] = ((REG_DDRPHY_READ ( phychno, 0x00000713))& 0x00000fff); + dataL[2] = ((REG_DDRPHY_READ ( phychno, 0x00000713))& 0x0fff0000) >> 16; + dataL[3] = ((REG_DDRPHY_READ ( phychno, 0x00000714))& 0x00000fff); + REG_DDRPHY_WRITE (phychno,0x00000712,( dataL[s_byte] << 8) |((REG_DDRPHY_READ ( phychno, 0x00000712)) & 0x0ff)); + REG_DDRPHY_WRITE (phychno,0x00000713,((dataL[s_byte] << 16)| dataL[s_byte])); + REG_DDRPHY_WRITE (phychno,0x00000714, dataL[s_byte]); +} +static void adjust_rddqsgatedelay(uintptr_t phychno) +{ + uint32_t i; + uint32_t s_dataL; + uint32_t d_dataL; + uint32_t teL; + uint32_t leL; + uint32_t meL; + uint32_t fsL; + uint32_t latL,dlyL; + uint32_t maxlatL =0x0; + uint32_t maxdlyL =0x0; +#ifdef DDR_DBS_DFI_WA + for(i=0;i<4;i++) + { + leL = (REG_DDRPHY_READ ( phychno, 0x00000429 + 0x80*i)>>16) & 0x3fff; + teL = (REG_DDRPHY_READ ( phychno, 0x0000042A + 0x80*i)>>0 ) & 0x3fff; + fsL = (REG_DDRPHY_READ ( phychno, 0x00000456 + 0x80*i)>>16) & 0x3ff; + meL = (leL+teL)>>1; + dlyL = (meL-fsL)&0x1ff; + latL = ((meL-fsL)>>9) & 7; + if(maxlatL < (dlyL + latL* 0x200)) + { + maxdlyL =dlyL; + maxlatL =dlyL + latL* 0x200; + } + } +#endif + for(i=0;i<4;i++) + { + leL = (REG_DDRPHY_READ ( phychno, 0x00000429 + 0x80*i)>>16) & 0x3fff; + teL = (REG_DDRPHY_READ ( phychno, 0x0000042A + 0x80*i)>>0 ) & 0x3fff; + fsL = (REG_DDRPHY_READ ( phychno, 0x00000456 + 0x80*i)>>16 ) & 0x3ff; + meL = (leL+teL)>>1; + if(meL>9) & 7; +#ifdef DDR_DBS_DFI_WA + if((maxdlyL > 0xff) & (dlyL < 0x100)) + { + REG_DDRPHY_WRITE ( phychno, 0x0454 + 0x80*i, (REG_DDRPHY_READ ( phychno, 0x00000454 + 0x80*i) + 0x00010000)); + } +#endif + s_dataL = REG_DDRPHY_READ ( phychno, 0x0000044C + 0x80*i); + d_dataL = (s_dataL & 0xff000000) | (latL<<16) | dlyL; + REG_DDRPHY_WRITE ( phychno, 0x0000044C + 0x80*i,d_dataL); + } +} +static void copy_dqdelay(uintptr_t phychno, uint32_t s_byte, uint32_t d_byte) +{ + uint32_t i; + uint32_t s_dataL; + uint32_t d_dataL; + for (i=0x43A;i<=0x43E;i++) + { + if(i==0x43E) + { + s_dataL = (REG_DDRPHY_READ ( phychno, i+s_byte*0x80)) & 0x0000ffff; + d_dataL = (REG_DDRPHY_READ ( phychno, i+d_byte*0x80)) & 0xffff0000; + REG_DDRPHY_WRITE (phychno,i+d_byte*0x80,(s_dataL|d_dataL)); + } + else + { + s_dataL = REG_DDRPHY_READ ( phychno, i+s_byte*0x80); + REG_DDRPHY_WRITE (phychno,i+d_byte*0x80,s_dataL); + } + } +} +static uint32_t pvt_pi_training_go_all_soft(uint32_t freq) +{ + uint32_t flag; + uint32_t dataL; + uint32_t phytrainingok; + uint32_t retry; + uintptr_t phychno; + PLL3_FREQ(freq,0); + for(phychno=0;phychno0) + { + for(phychno=0;phychno0x53) + { +// // def 3200 + } + else if(freq>0x47) + { +// freq2800_reg_set(); // need more tuning + } + else if(freq>0x2f) + { +// freq2400_reg_set(); // need more tuning + } + else + { + freq1600_reg_set(); + } +#ifdef DDR_DEBUG_DBI + if(DDR_DEBUG_DBI == 1){ + for(ch=0;ch> 17; + if(j==0){ + j = 0x5150; + } else if (j == 1) { + j = 0x6160; + } else if (j == 4) { + j = 0x7170; + } else { + j = 0x5150; + }; + for (i=0;i>16)&0xff; + uint32_t cp=(DDR_CACS_CCCP>>0)&0xff; + REG_DDRPHY_WRITE(ch,0x257,(REG_DDRPHY_READ(ch,0x257) & 0x0000ffff) | (cc<<16)); + REG_DDRPHY_WRITE(ch,0x258,(REG_DDRPHY_READ(ch,0x258) & 0x00000000) | (cc<<16) | cp); + REG_DDRPHY_WRITE(ch,0x259,(REG_DDRPHY_READ(ch,0x259) & 0x00000000) | (cc<<16) | cp); + REG_DDRPHY_WRITE(ch,0x25a,(REG_DDRPHY_READ(ch,0x25a) & 0x00000000) | cp); + for(slice=0;slice<2;slice++){ + REG_DDRPHY_WRITE(ch,0x610+0x80*slice,(REG_DDRPHY_READ(ch,0x610+0x80*slice) & 0xf0f0ffff ) + | ((DDR_CACS_RESP_WAIT_CNT&0x0f)<<24) + | ((DDR_CACS_CAPTURE_CNT&0x0f)<<16) + ); + REG_DDRPHY_WRITE(ch,0x60a+0x80*slice,(REG_DDRPHY_READ(ch,0x60a+0x80*slice) & 0xfffff000 ) + | DDR_CACS_START + ); + REG_DDRPHY_WRITE(ch,0x60b+0x80*slice,(REG_DDRPHY_READ(ch,0x60b+0x80*slice) & 0xfffff000 ) + | DDR_CACS_QTR + ); + REG_DDRPHY_WRITE(ch,0x624+0x80*slice,(REG_DDRPHY_READ(ch,0x624+0x80*slice) & 0xfffffff0 ) + | DDR_CACS_STEP + ); + } + slice=0; + REG_DDRPHY_WRITE(ch,0x704+0x80*slice,(REG_DDRPHY_READ(ch,0x704+0x80*slice) & 0xfff0ffff) | ((DDR_CACS_CAPTURE_CNT&0x0f)<<16)); + REG_DDRPHY_WRITE(ch,0x705+0x80*slice,(REG_DDRPHY_READ(ch,0x705+0x80*slice) & 0xfff0ffff) | ((DDR_CACS_CAPTURE_CNT&0x0f)<<16)); + } + dsb_sev(); + dsb_sev(); + dsb_sev(); + PLL3_FREQ(freq,0); + dsb_sev(); + dsb_sev(); + dsb_sev(); +#ifdef DDR_PAD_CAL_WA + for(i=0;i>24)&0xff; + k=0; + for(phychno=0;phychno0) + { + *((volatile uint32_t*)(DBSC_DBDFICNT_0+0x40*phychno)) = 0x00000011; + dsb_sev(); + *((volatile uint32_t*)(DBSC_DBDFICNT_0+0x40*phychno)) = 0x00000010; + dsb_sev(); + for(retry=0;retry<4;retry++) + { + REG_DDRPHY_WRITE(phychno,0x433+retry*0x80,REG_DDRPHY_READ(phychno,0x433+retry*0x80)|0x1); + } + } + retry=0; + while(retry<2048) + { + dataL = *((volatile uint32_t*)(DBSC_INITCOMP_0+phychno*0x40)); + if((dataL & 0x00000001) == 0x1) break; + retry++; + } + if(retry<2048) + { + phytrainingok|=(1<>18)& 0x03f; + pvtn_l=(dataL >>12)& 0x03f; +#endif + pvtp_h=(dataL >> 6)& 0x03f; + pvtp_l=(dataL >> 0)& 0x03f; + for( i=0; i>12)& 0x01f; +#ifdef DDR_PAD_CAL_WA2 + dataL=(o_dataL & 0xffe00000) | (((pvtr+DDR_PVTR_ADJ)&0x1f)<<12) | (pvtp_h<<6) |pvtp_l; +#else + dataL=(o_dataL & 0xffe00000) | (((pvtr+DDR_PVTR_ADJ)&0x1f)<<12) | (((pvtn_h+pvtn_l)>>1)<<6) | ((pvtp_h+pvtp_l)>>1); +#endif + REG_DDRPHY_WRITE(j,DDR_PHY_DDR_PHY_PVT_OVERWITE_1600[i][0],dataL); + dataL=REG_DDRPHY_READ(j,DDR_PHY_DDR_PHY_PVT_OVERWITE_1600[i][0]); + } + } + for(ch=0;ch0x53) *((volatile uint32_t*)DBSC_DBRFCNF1) = 0x00081860 >>1; //dbrfcnf1 refpmax=8 refint=6240 + else if(freq>0x47) *((volatile uint32_t*)DBSC_DBRFCNF1) = 0x00081554 >>1; //dbrfcnf1 refpmax=8 refint=5460 + else if(freq>0x2f) *((volatile uint32_t*)DBSC_DBRFCNF1) = 0x00081248 >>1; //dbrfcnf1 refpmax=8 refint=4680 + else *((volatile uint32_t*)DBSC_DBRFCNF1) = 0x00080C30 >>1; //dbrfcnf1 refpmax=8 refint=3120 +#else + if(freq>0x53) *((volatile uint32_t*)DBSC_DBRFCNF1) = 0x00081860; //dbrfcnf1 refpmax=8 refint=6240 + else if(freq>0x47) *((volatile uint32_t*)DBSC_DBRFCNF1) = 0x00081554; //dbrfcnf1 refpmax=8 refint=5460 + else if(freq>0x2f) *((volatile uint32_t*)DBSC_DBRFCNF1) = 0x00081248; //dbrfcnf1 refpmax=8 refint=4680 + else *((volatile uint32_t*)DBSC_DBRFCNF1) = 0x00080C30; //dbrfcnf1 refpmax=8 refint=3120 +#endif + *((volatile uint32_t*)DBSC_DBRFCNF2) = 0x00010000|DBSC_REFINTS; //dbrfcnf2 refpmin=1 refints=0 +#ifdef BOARD_KRIEK + *((volatile uint32_t*)DBSC_DBMEMCONF_1_0) = 0x0; + *((volatile uint32_t*)DBSC_DBMEMCONF_1_1) = 0x0; + *((volatile uint32_t*)DBSC_DBMEMCONF_3_0) = 0x0; + *((volatile uint32_t*)DBSC_DBMEMCONF_3_1) = 0x0; +#else + if (DDR_CSMAP != 0xf) { + *((volatile uint32_t*)DBSC_DBMEMCONF_0_1) = 0x0; + *((volatile uint32_t*)DBSC_DBMEMCONF_1_1) = 0x0; + *((volatile uint32_t*)DBSC_DBMEMCONF_2_1) = 0x0; + *((volatile uint32_t*)DBSC_DBMEMCONF_3_1) = 0x0; + } +#endif + *((volatile uint32_t*)DBSC_DBMEMCONF_0_2) = 0x0; + *((volatile uint32_t*)DBSC_DBMEMCONF_0_3) = 0x0; + *((volatile uint32_t*)DBSC_DBMEMCONF_1_2) = 0x0; + *((volatile uint32_t*)DBSC_DBMEMCONF_1_3) = 0x0; + *((volatile uint32_t*)DBSC_DBMEMCONF_2_2) = 0x0; + *((volatile uint32_t*)DBSC_DBMEMCONF_2_3) = 0x0; + *((volatile uint32_t*)DBSC_DBMEMCONF_3_2) = 0x0; + *((volatile uint32_t*)DBSC_DBMEMCONF_3_3) = 0x0; + *((volatile uint32_t*)DBSC_DBRFEN) = 0x00000001; +#ifdef DDR_BACKUPMODE +///// Modify for BackUp (begin) ///////////////////////////////////////////////////////////////////// + if(ddrBackup==WARM_BOOT){ + //(2)LPDDR4-SDRAM + //(b) Self-Refreshing (When the Clock is Stopped) + //Use the following procedure to release self-refresh mode. + //1.Restart the supply of the clock signal to the DBSC4 and wait until they settle. + //2.Reconfigure the PHY unit to suit the PHY specification. + //3.Set the ARFEN bit to 1 in the auto-refresh enable register (DBRFEN). +// *((volatile uint32_t*)DBSC_DBRFEN) = 0x00000001; + + //4.Use the manual command-issuing register (DBCMD) to issue the Power Down Exit command. + // The value written to this register should be OPC = B'1000 (PD), CH = B'1000 (all channels), RANK = B'100 (all ranks), ARG = H'0001 (exit). + *((volatile uint32_t*)DBSC_DBCMD) = 0x08840001; + + //5.Poll the operation completion waiting register (DBWAIT) to check when the issuing of manual commands is complete. + while( *((volatile uint32_t*)DBSC_DBWAIT) ); + + //6.Use the manual command-issuing register (DBCMD) to issue the Self-Refresh Exit command. + // The value written to this register should be OPC = B'1010 (SR), CH = B'1000 (all channels), RANK = B'100 (all ranks), ARG = H'0001 (exit). + *((volatile uint32_t*)DBSC_DBCMD) = 0x0A840001; + + //7.Poll the operation completion waiting register (DBWAIT) to check when the issuing of manual commands is complete. + while( *((volatile uint32_t*)DBSC_DBWAIT) ); + + //8.Use the manual command-issuing register (DBCMD) to issue the PREA (precharge all) command. + // The value written to this register should be OPC = B'0100 (PRE), CH = B'1000 (all channels), RANK = B'100 (all ranks), ARG = H'0010 (all banks). + *((volatile uint32_t*)DBSC_DBCMD) = 0x04840010; + + //9.Poll the operation completion waiting register (DBWAIT) to check when the issuing of manual commands is complete. + while( *((volatile uint32_t*)DBSC_DBWAIT) ); + + //10.Set the ACCEN bit to 1 (enabling access) in the SDRAM access enable register (DBACEN). +// *((volatile uint32_t*)DBSC_DBACEN) = 0x00000001; + } +///// Modify for BackUp (end) /////////////////////////////////////////////////////////////////////// +#endif +//DRAM ACCESS enable + *((volatile uint32_t*)DBSC_DBACEN) = 0x00000001; //dbacen + return phytrainingok; +} +#if 0 +static void freq2800_reg_set() +{ + uint32_t i; + for(i=0;i0); + } else { + done=phych_mask; + } + *((volatile uint32_t*)(DBSC_DBDFICNT_0+0x00)) = 0x00000010; + *((volatile uint32_t*)(DBSC_DBDFICNT_0+0x40)) = 0x00000010; + *((volatile uint32_t*)(DBSC_DBDFICNT_0+0x80)) = 0x00000010; + *((volatile uint32_t*)(DBSC_DBDFICNT_0+0xC0)) = 0x00000010; + if(_WDQCNT&0x20){ + *((volatile uint32_t*)(DBSC_DBPDCNT_0+0x00)) = 0x0000CF00; + *((volatile uint32_t*)(DBSC_DBPDCNT_0+0x40)) = 0x0000CF00; + *((volatile uint32_t*)(DBSC_DBPDCNT_0+0x80)) = 0x0000CF00; + *((volatile uint32_t*)(DBSC_DBPDCNT_0+0xC0)) = 0x0000CF00; + *((volatile uint32_t*)(DBSC_DBPDCNT_0+0x00)) = 0x0000CF01; + *((volatile uint32_t*)(DBSC_DBPDCNT_0+0x40)) = 0x0000CF01; + *((volatile uint32_t*)(DBSC_DBPDCNT_0+0x80)) = 0x0000CF01; + *((volatile uint32_t*)(DBSC_DBPDCNT_0+0xC0)) = 0x0000CF01; + } + dsb_sev(); + if(_WDQCNT&0x4){ + *((volatile uint32_t*)DBSC_DBCMD) = 0x02840000; + } + return done; +} +uint32_t wdqlvl_core0(uint32_t phych_mask, uint32_t *phase_p){ + uintptr_t ch; + uint32_t done; + uint32_t phase=0; + if(phase){ + phase=0; + } else { + phase=1; + } + uint32_t tmp[4]; + for(ch=0;ch (+0) SDRAM 30671254 : 10011010 : 9A + { 0x000004A0, 0x26541037}, // PHY_DQ_SWIZZLING_1:RW:0:32:=0x76543210 // SoC DQ15-8 -> (+16)SDRAM 26541037 : 00101011 : 2B + { 0x00000520, 0x17054623}, // PHY_DQ_SWIZZLING_2:RW:0:32:=0x76543210 // SoC DQ23-16 -> (+8) SDRAM 17054623 : 11010001 : D1 + { 0x000005A0, 0x12307645}, // PHY_DQ_SWIZZLING_3:RW:0:32:=0x76543210 // SoC DQ31-24 -> (+24)SDRAM 12307645 : 10101001 : A9 + { 0x0000061C, 0x00315024}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 // SoC AC305142 -> DRAM 5-0 + { 0x0000060C, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_0_0:RW:0:24:=0xdcba98 // SoC Byte0 -> DRAM Byte 0 + { 0x0000060D, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE1_0_0:RW:0:24:=0x000000 // SoC Byte1 -> DRAM Byte 2 + { 0x0000060E, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_1_0:RW:0:24:=0xdcba98 // SoC Byte2 -> DRAM Byte 1 CALVL needs CS2 patch!! + { 0x0000060F, 0x02dcba98}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 3 + { 0x00000250, 0x01080000}, // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 + { 0x0000040E, 0x65d45a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 + { 0x0000048E, 0x65d45a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 + { 0x0000050E, 0x2e565a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 + { 0x0000058E, 0x2e565a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 +}; + +static const uint32_t DDR_SIP_SWAP_CH1[9+5][2] = +{ + { 0x00000420, 0x70613542}, // PHY_DQ_SWIZZLING_0:RW:0:32:=0x76543210 // SoC DQ7-0 -> (+0) SDRAM 70613542 : 10011100 : 9C + { 0x000004A0, 0x16245307}, // PHY_DQ_SWIZZLING_1:RW:0:32:=0x76543210 // SoC DQ15-8 -> (+8) SDRAM 16245307 : 10001101 : 8D + { 0x00000520, 0x30712645}, // PHY_DQ_SWIZZLING_2:RW:0:32:=0x76543210 // SoC DQ23-16 -> (+16)SDRAM 30712645 : 10110001 : B1 + { 0x000005A0, 0x21706354}, // PHY_DQ_SWIZZLING_3:RW:0:32:=0x76543210 // SoC DQ31-24 -> (+24)SDRAM 21706354 : 01100110 : 66 + { 0x0000061C, 0x00025143}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 // SoC AC310425-> DRAM 5-0 + { 0x0000060C, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_0_0:RW:0:24:=0xdcba98 // SoC Byte0 -> DRAM Byte 0 + { 0x0000060D, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE1_0_0:RW:0:24:=0x000000 // SoC Byte1 -> DRAM Byte 1 + { 0x0000060E, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_1_0:RW:0:24:=0xdcba98 // SoC Byte2 -> DRAM Byte 2 + { 0x0000060F, 0x01DCBA98}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 3 + + { 0x00000250, 0x01080000}, // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 + { 0x0000040E, 0x63725a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 + { 0x0000048E, 0x63725a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 + { 0x0000050E, 0x4e995a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 + { 0x0000058E, 0x4e995a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 +}; + +static const uint32_t DDR_SIP_SWAP_CH2[9+5][2] = +{ + { 0x00000420, 0x70613542}, // PHY_DQ_SWIZZLING_0:RW:0:32:=0x76543210 // SoC DQ7-0 -> (+8) SDRAM 70613542 : 10011100 : 9C + { 0x000004A0, 0x16245307}, // PHY_DQ_SWIZZLING_1:RW:0:32:=0x76543210 // SoC DQ15-8 -> (+0) SDRAM 16245307 : 10001101 : 8D + { 0x00000520, 0x30712645}, // PHY_DQ_SWIZZLING_2:RW:0:32:=0x76543210 // SoC DQ23-16 -> (+24)SDRAM 30712645 : 10110001 : B1 + { 0x000005A0, 0x21706354}, // PHY_DQ_SWIZZLING_3:RW:0:32:=0x76543210 // SoC DQ31-24 -> (+16)SDRAM 21706354 : 01100110 : 66 +// { 0x0000061C, 0x00503421}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 // SoC AC503421-> DRAM 5-0 + { 0x0000061C, 0x00523104}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 // SoC AC503421-> DRAM 5-0 + { 0x0000060C, 0x00543210}, // PHY_ADR_CALVL_SWIZZLE0_0_0:RW:0:24:=0xdcba98 // SoC Byte0 -> DRAM Byte 1 + { 0x0000060D, 0x00543210}, // PHY_ADR_CALVL_SWIZZLE1_0_0:RW:0:24:=0x000000 // SoC Byte1 -> DRAM Byte 0 + { 0x0000060E, 0x00543210}, // PHY_ADR_CALVL_SWIZZLE0_1_0:RW:0:24:=0xdcba98 // SoC Byte2 -> DRAM Byte 3 + { 0x0000060F, 0x01543210}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 2 + { 0x00000250, 0x01080000}, // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 + { 0x0000040E, 0x63725a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 + { 0x0000048E, 0x63725a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 + { 0x0000050E, 0x4e995a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 + { 0x0000058E, 0x4e995a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 +}; + +static const uint32_t DDR_SIP_SWAP_CH3[9+5][2] = +{ + { 0x00000420, 0x30671254}, // PHY_DQ_SWIZZLING_0:RW:0:32:=0x76543210 // SoC DQ7-0 -> (+8) SDRAM : 30671254 : 10011010 : 9A + { 0x000004A0, 0x26541037}, // PHY_DQ_SWIZZLING_1:RW:0:32:=0x76543210 // SoC DQ15-8 -> (+24)SDRAM : 26541037 : 00101011 : 2B + { 0x00000520, 0x17054623}, // PHY_DQ_SWIZZLING_2:RW:0:32:=0x76543210 // SoC DQ23-16 -> (+0) SDRAM : 17054623 : 11010001 : D1 + { 0x000005A0, 0x12307645}, // PHY_DQ_SWIZZLING_3:RW:0:32:=0x76543210 // SoC DQ31-24 -> (+16)SDRAM : 12307645 : 10101001 : A9 + { 0x0000061C, 0x00153402}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 // SoC AC423051 -> DRAM + { 0x0000060C, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_0_0:RW:0:24:=0xdcba98 // SoC Byte0 -> DRAM Byte 2 + { 0x0000060D, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE1_0_0:RW:0:24:=0x000000 // SoC Byte1 -> DRAM Byte 0 + { 0x0000060E, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_1_0:RW:0:24:=0xdcba98 // SoC Byte2 -> DRAM Byte 3 CALVL need CS2 patch + { 0x0000060F, 0x01DCBA98}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 1 + { 0x00000250, 0x01080000}, // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 + { 0x0000040E, 0x65d45a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 + { 0x0000048E, 0x65d45a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 + { 0x0000050E, 0x2e565a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 + { 0x0000058E, 0x2e565a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 +}; +#endif //BOARD_SALVATOR_M +#ifdef BOARD_SALVATOR_X +static const uint32_t DDR_SIP_SWAP_CH0[9+5][2] = +{ + { 0x00000420, 0x20741365}, // PHY_DQ_SWIZZLING_0:RW:0:32:=0x76543210 // SoC DQ7-0 -> SDRAM 20741365 : 00101101 : 2d -> d2 + { 0x000004A0, 0x34256107}, // PHY_DQ_SWIZZLING_1:RW:0:32:=0x76543210 // SoC DQ15-8 -> SDRAM 34256107 : 10010101 : 95 -> 6a + { 0x00000520, 0x57460321}, // PHY_DQ_SWIZZLING_2:RW:0:32:=0x76543210 // SoC DQ23-16 -> SDRAM 57460321 : 11000101 : c5 -> 3a + { 0x000005A0, 0x70614532}, // PHY_DQ_SWIZZLING_3:RW:0:32:=0x76543210 // SoC DQ31-24 -> SDRAM 70614532 : 10010110 : 96 -> 69 + { 0x0000061C, 0x00543210}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 // SoC AC5-0 -> DRAM 543210 + { 0x0000060C, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_0_0:RW:0:24:=0xdcba98 // SoC Byte0 -> DRAM Byte 0 + { 0x0000060D, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE1_0_0:RW:0:24:=0x000000 // SoC Byte1 -> DRAM Byte 1 + { 0x0000060E, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_1_0:RW:0:24:=0xdcba98 // SoC Byte2 -> DRAM Byte 2 + { 0x0000060F, 0x01DCBA98}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 3 + { 0x00000250, 0x01080000}, // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 + { 0x0000040E, 0xd26a5a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 + { 0x0000048E, 0xd26a5a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 + { 0x0000050E, 0x3a695a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 + { 0x0000058E, 0x3a695a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 +}; + +static const uint32_t DDR_SIP_SWAP_CH1[9+5][2] = +{ + { 0x00000420, 0x23547610}, // PHY_DQ_SWIZZLING_0:RW:0:32:=0x76543210 // SoC DQ7-0 -> SDRAM 23547610 : 01101010 : 6a -> 95 + { 0x000004A0, 0x34526107}, // PHY_DQ_SWIZZLING_1:RW:0:32:=0x76543210 // SoC DQ15-8 -> SDRAM 34526107 : 10100101 : a5 -> 5a + { 0x00000520, 0x67452310}, // PHY_DQ_SWIZZLING_2:RW:0:32:=0x76543210 // SoC DQ23-16 -> SDRAM 67452310 : 01010110 : 56 -> a9 + { 0x000005A0, 0x32106754}, // PHY_DQ_SWIZZLING_3:RW:0:32:=0x76543210 // SoC DQ31-24 -> SDRAM 32106754 : 10100110 : a6 -> 59 + { 0x0000061C, 0x00543210}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 // SoC AC5-0 -> DRAM 543210 + + { 0x0000060C, 0x00dcba98}, // PHY_ADR_CALVL_SWIZZLE0_0_0:RW:0:24:=0xdcba98 // SoC Byte0 -> DRAM Byte 2 + { 0x0000060D, 0x00dcba98}, // PHY_ADR_CALVL_SWIZZLE1_0_0:RW:0:24:=0x000000 // SoC Byte1 -> DRAM Byte 0 + { 0x0000060E, 0x00dcba98}, // PHY_ADR_CALVL_SWIZZLE0_1_0:RW:0:24:=0xdcba98 // SoC Byte2 -> DRAM Byte 1 + { 0x0000060F, 0x02dcba98}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 3 + + { 0x00000250, 0x01080000}, // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 + { 0x0000040E, 0x955a5a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 + { 0x0000048E, 0x955a5a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 + { 0x0000050E, 0xa9595a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 + { 0x0000058E, 0xa9595a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 +}; + +static const uint32_t DDR_SIP_SWAP_CH2[9+5][2] = +{ + { 0x00000420, 0x30216754}, // PHY_DQ_SWIZZLING_0:RW:0:32:=0x76543210 // SoC DQ7-0 -> SDRAM 30216754 : 10010110 : 96 -> 69 + { 0x000004A0, 0x67453210}, // PHY_DQ_SWIZZLING_1:RW:0:32:=0x76543210 // SoC DQ15-8 -> SDRAM 67453210 : 01011010 : 5a -> a5 + { 0x00000520, 0x70165243}, // PHY_DQ_SWIZZLING_2:RW:0:32:=0x76543210 // SoC DQ23-16 -> SDRAM 70165243 : 10101001 : a9 -> 56 + { 0x000005A0, 0x07162345}, // PHY_DQ_SWIZZLING_3:RW:0:32:=0x76543210 // SoC DQ31-24 -> SDRAM 07162345 : 01100101 : 65 -> 9a + { 0x0000061C, 0x00543210}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 // SoC AC5-0 -> DRAM 543210 + { 0x0000060C, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_0_0:RW:0:24:=0xdcba98 // SoC Byte0 -> DRAM Byte 3 + { 0x0000060D, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE1_0_0:RW:0:24:=0x000000 // SoC Byte1 -> DRAM Byte 1 + { 0x0000060E, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_1_0:RW:0:24:=0xdcba98 // SoC Byte2 -> DRAM Byte 2 + { 0x0000060F, 0x01DCBA98}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 0 + { 0x00000250, 0x01080000}, // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 + { 0x0000040E, 0x69a55a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 + { 0x0000048E, 0x69a55a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 + { 0x0000050E, 0x569a5a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 + { 0x0000058E, 0x569a5a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 +}; + +static const uint32_t DDR_SIP_SWAP_CH3[9+5][2] = +{ + { 0x00000420, 0x01327654}, // PHY_DQ_SWIZZLING_0:RW:0:32:=0x76543210 // SoC DQ7-0 -> SDRAM : 01327654 : 01101010 : 6a -> 95 + { 0x000004A0, 0x70615432}, // PHY_DQ_SWIZZLING_1:RW:0:32:=0x76543210 // SoC DQ15-8 -> SDRAM : 70615432 : 10011010 : 9a -> 65 + { 0x00000520, 0x54760123}, // PHY_DQ_SWIZZLING_2:RW:0:32:=0x76543210 // SoC DQ23-16 -> SDRAM : 54760123 : 10100101 : a5 -> 5a + { 0x000005A0, 0x07162345}, // PHY_DQ_SWIZZLING_3:RW:0:32:=0x76543210 // SoC DQ31-24 -> SDRAM : 07162345 : 01100101 : 65 -> 9a + { 0x0000061C, 0x00543210}, // PHY_ADR_ADDR_SEL_0:RW:0:24:=0x543210 // SoC AC5-0 -> DRAM 543210 + { 0x0000060C, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_0_0:RW:0:24:=0xdcba98 // SoC Byte0 -> DRAM Byte 3 + { 0x0000060D, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE1_0_0:RW:0:24:=0x000000 // SoC Byte1 -> DRAM Byte 1 + { 0x0000060E, 0x00DCBA98}, // PHY_ADR_CALVL_SWIZZLE0_1_0:RW:0:24:=0xdcba98 // SoC Byte2 -> DRAM Byte 2 + { 0x0000060F, 0x01DCBA98}, // PHY_ADR_CALVL_DEVICE_MAP_0:RW:24:4:=0x01 PHY_ADR_CALVL_SWIZZLE1_1_0:RW:0:24:=0x000000 // SoC Byte3 -> DRAM Byte 0 + { 0x00000250, 0x01080000}, // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 + { 0x0000040E, 0x95655a3c}, // PHY_LP4_RDLVL_PATT8_0:RW:0:32:=0x00000000 + { 0x0000048E, 0x95655a3c}, // PHY_LP4_RDLVL_PATT8_1:RW:0:32:=0x00000000 + { 0x0000050E, 0x5a9a5a3c}, // PHY_LP4_RDLVL_PATT8_2:RW:0:32:=0x00000000 + { 0x0000058E, 0x5a9a5a3c}, // PHY_LP4_RDLVL_PATT8_3:RW:0:32:=0x00000000 +}; +#endif //BOARD_SALVATOR_X +#ifdef BOARD_KRIEK +static const uint32_t DDR_SIP_SWAP_CH0[9+5][2] = +{ + { 0x00000420, 0x01672543}, + { 0x000004A0, 0x45361207}, + { 0x00000520, 0x45632107}, + { 0x000005A0, 0x60715234}, + { 0x0000061C, 0x00345201}, + { 0x0000060C, 0x00543210}, + { 0x0000060D, 0x00543210}, + { 0x0000060E, 0x00543210}, + { 0x0000060F, 0x01543210}, + { 0x00000250, 0x01080000}, + { 0x0000040E, 0xaa965a3c}, + { 0x0000048E, 0xaa965a3c}, + { 0x0000050E, 0xaac55a3c}, + { 0x0000058E, 0xaac55a3c}, +}; + +static const uint32_t DDR_SIP_SWAP_CH1[9+5][2] = +{ + { 0x00000420, 0x01672543}, + { 0x000004A0, 0x45361207}, + { 0x00000520, 0x45632107}, + { 0x000005A0, 0x60715234}, + { 0x0000061C, 0x00345201}, + { 0x0000060C, 0x00543210}, + { 0x0000060D, 0x00543210}, + { 0x0000060E, 0x00543210}, + { 0x0000060F, 0x01543210}, + { 0x00000250, 0x01080000}, + { 0x0000040E, 0xaa965a3c}, + { 0x0000048E, 0xaa965a3c}, + { 0x0000050E, 0xaac55a3c}, + { 0x0000058E, 0xaac55a3c}, +}; + +static const uint32_t DDR_SIP_SWAP_CH2[9+5][2] = +{ + { 0x00000420, 0x01672543}, + { 0x000004A0, 0x45361207}, + { 0x00000520, 0x45632107}, + { 0x000005A0, 0x60715234}, + { 0x0000061C, 0x00302154}, + { 0x0000060C, 0x00DCBA98}, + { 0x0000060D, 0x00DCBA98}, + { 0x0000060E, 0x00DCBA98}, + { 0x0000060F, 0x01DCBA98}, + { 0x00000250, 0x01080000}, + { 0x0000040E, 0xaa965a3c}, + { 0x0000048E, 0xaa965a3c}, + { 0x0000050E, 0xaac55a3c}, + { 0x0000058E, 0xaac55a3c}, +}; + +static const uint32_t DDR_SIP_SWAP_CH3[9+5][2] = +{ + { 0x00000420, 0x01672543}, + { 0x000004A0, 0x45361207}, + { 0x00000520, 0x45632107}, + { 0x000005A0, 0x60715234}, + { 0x0000061C, 0x00302154}, + { 0x0000060C, 0x00DCBA98}, + { 0x0000060D, 0x00DCBA98}, + { 0x0000060E, 0x00DCBA98}, + { 0x0000060F, 0x01DCBA98}, + { 0x00000250, 0x01080000}, + { 0x0000040E, 0xaa965a3c}, + { 0x0000048E, 0xaa965a3c}, + { 0x0000050E, 0xaac55a3c}, + { 0x0000058E, 0xaac55a3c}, +}; +#endif // BOARD_KRIEK + +static const uint32_t DDR_CA_DELAY[7][2] = +{ + { 0x0000061F, 0x0002A06E}, // PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x55 //CA0 delay this means 768/512 tCK delay for address bit + { 0x00000620, 0x02A002A0}, // PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA1/2 delay + { 0x00000621, 0x02A002A0}, // PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA3/4 delay + { 0x00000622, 0x000002A0}, // PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA5 delay + { 0x00000712, 0x0002A003}, // PHY_GRP_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_CSLVL_DLY_STEP:RW+:0:4:=0x03 //CS0 group delay + { 0x00000713, 0x02A002A0}, // PHY_GRP_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP_SLAVE_DELAY_1:RW+:0:11:=0x0300 //CS1/2 group delay + { 0x00000714, 0x000002A0}, // PHY_GRP_SLAVE_DELAY_3:RW+:0:11:=0x0300 //CS3 group delay +}; + + +static const uint32_t DDR_CA_DELAY_CH0[7][2] = +{ + { 0x0000061F, 0x0002c06E}, // PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x55 //CA0 delay this means 768/512 tCK delay for address bit + { 0x00000620, 0x02c002c0}, // PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA1/2 delay + { 0x00000621, 0x02c002c0}, // PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA3/4 delay + { 0x00000622, 0x000002c0}, // PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA5 delay + { 0x00000712, 0x0002c003}, // PHY_GRP_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_CSLVL_DLY_STEP:RW+:0:4:=0x03 //CS0 group delay + { 0x00000713, 0x02c002c0}, // PHY_GRP_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP_SLAVE_DELAY_1:RW+:0:11:=0x0300 //CS1/2 group delay + { 0x00000714, 0x000002c0}, // PHY_GRP_SLAVE_DELAY_3:RW+:0:11:=0x0300 //CS3 group delay +}; + +static const uint32_t DDR_CA_DELAY_CH1[7][2] = +{ + { 0x0000061F, 0x0002C06E}, // PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x55 //CA0 delay this means 768/512 tCK delay for address bit + { 0x00000620, 0x02C002C0}, // PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA1/2 delay + { 0x00000621, 0x02C002C0}, // PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA3/4 delay + { 0x00000622, 0x000002C0}, // PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA5 delay + { 0x00000712, 0x0002D003}, // PHY_GRP_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_CSLVL_DLY_STEP:RW+:0:4:=0x03 //CS0 group delay + { 0x00000713, 0x02D002D0}, // PHY_GRP_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP_SLAVE_DELAY_1:RW+:0:11:=0x0300 //CS1/2 group delay + { 0x00000714, 0x000002D0}, // PHY_GRP_SLAVE_DELAY_3:RW+:0:11:=0x0300 //CS3 group delay +}; + +static const uint32_t DDR_CA_DELAY_CH2[7][2] = +{ + { 0x0000061F, 0x0002C06E}, // PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x55 //CA0 delay this means 768/512 tCK delay for address bit + { 0x00000620, 0x02C002C0}, // PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA1/2 delay + { 0x00000621, 0x02C002C0}, // PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA3/4 delay + { 0x00000622, 0x000002C0}, // PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA5 delay + { 0x00000712, 0x0002C003}, // PHY_GRP_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_CSLVL_DLY_STEP:RW+:0:4:=0x03 //CS0 group delay + { 0x00000713, 0x02C002C0}, // PHY_GRP_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP_SLAVE_DELAY_1:RW+:0:11:=0x0300 //CS1/2 group delay + { 0x00000714, 0x000002C0}, // PHY_GRP_SLAVE_DELAY_3:RW+:0:11:=0x0300 //CS3 group delay +}; + +static const uint32_t DDR_CA_DELAY_CH3[7][2] = +{ + { 0x0000061F, 0x0002C06E}, // PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x55 //CA0 delay this means 768/512 tCK delay for address bit + { 0x00000620, 0x02C002C0}, // PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA1/2 delay + { 0x00000621, 0x02C002C0}, // PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA3/4 delay + { 0x00000622, 0x000002C0}, // PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300 //CA5 delay + { 0x00000712, 0x0002C003}, // PHY_GRP_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_CSLVL_DLY_STEP:RW+:0:4:=0x03 //CS0 group delay + { 0x00000713, 0x02C002C0}, // PHY_GRP_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP_SLAVE_DELAY_1:RW+:0:11:=0x0300 //CS1/2 group delay + { 0x00000714, 0x000002C0}, // PHY_GRP_SLAVE_DELAY_3:RW+:0:11:=0x0300 //CS3 group delay +}; + +#endif /* __INIT_DRAM_TBL_H3_WS11__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/M3/boot_init_dram_m3_es10.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/M3/boot_init_dram_m3_es10.c new file mode 100644 index 0000000..47817f7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/M3/boot_init_dram_m3_es10.c @@ -0,0 +1,1543 @@ +#include //for uint32_t +#include //for uint32_t +#include //for uint32_t +#ifdef RCAR_LSI +#include +#endif + +#define RCAR_DDR_VERSION "rev.0.15" +#define DRAM_CH_CNT 0x02 + +/////////////////////////////////////////////////////////// +//BOARD CONFIGRATION +//PLEASE DEFINE THE FOLLOWING MACRO +/////////////////////////////////////////////////////////// +//number of board configurations(PLEASE SET) +#define BOARDNUM 2 +/////////////////////////////////////////////////////////// +//PLEASE SET _def_BOARDTYPE value +#define BOARD_SALVATOR_X +//#define BOARD_KRIEK + +#ifdef BOARD_SALVATOR_X +#define _def_BOARDTYPE (0) +#else +#define _def_BOARDTYPE (1) +#endif + +#undef BOARD_KRIEK +#undef BOARD_SALVATOR_X + +/////////////////////////////////////////////////////////// +//BOARD CONFIGRATION +//PLEASE DEFINE THE FOLLOWING ARRAY +/////////////////////////////////////////////////////////// +//SoC caX([5][4][3][2][1][0]) -> MEM caY: +//SoC caX([5][4][3][2][1][0]) -> Dfi caY: +static const uint32_t BOARDCNF_CA_SWAP[BOARDNUM][DRAM_CH_CNT]= +{ + { //BOARDTYPE:0 + 0x00543210,//CH0 + 0x00543210 //CH1 + }, + { //BOARDTYPE:1 + 0x00345201,//CH0 + 0x00302154 //CH1 + } +}; +//SoC dqsX([3][2][1][0]) -> MEM dqsY: +static const uint16_t BOARDCNF_DQS_SWAP[BOARDNUM][DRAM_CH_CNT]= +{ + { //BOARDTYPE:0 + 0x3201,//CH0 + 0x2310 //CH1 + }, + { //BOARDTYPE:1 + 0x3201,//CH0 + 0x2310 //CH1 + } +}; +//SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY: (8 means DM) +static const uint32_t BOARDCNF_DQ_SWAP[BOARDNUM][DRAM_CH_CNT][4]= +{ + { //BOARDTYPE0 + { //CH0 SoC_DQS0 SoC_DQS1 SoC_DQS2 SoC_DQS3 + 0x70612543, 0x43251670, 0x45326170, 0x10672534 + }, + { //CH1 SoC_DQS0 SoC_DQS1 SoC_DQS2 SoC_DQS3 + 0x01327654, 0x34526107, 0x35421670, 0x70615324 + } + }, + {//BOARDTYPE1 + { //CH0 SoC_DQS0 SoC_DQS1 SoC_DQS2 SoC_DQS3 + 0x01672543, 0x45361207, 0x45632107, 0x60715234 + }, + { //CH1 SoC_DQS0 SoC_DQS1 SoC_DQS2 SoC_DQS3 + 0x01672543, 0x45361207, 0x45632107, 0x60715234 + } + } +}; +//SoC dm -> MEM dqY: (8 means DM) +static const uint8_t BOARDCNF_DM_SWAP[BOARDNUM][DRAM_CH_CNT][4]= +{ + { //BOARDTYPE0 + { //CH0 SoC_DQS0 SoC_DQS1 SoC_DQS2 SoC_DQS3 + 0x08, 0x08, 0x08, 0x08 + }, + { //CH1 SoC_DQS0 SoC_DQS1 SoC_DQS2 SoC_DQS3 + 0x08, 0x08, 0x08, 0x08 + } + }, + {//BOARDTYPE1 + { //CH0 SoC_DQS0 SoC_DQS1 SoC_DQS2 SoC_DQS3 + 0x08, 0x08, 0x08, 0x08 + }, + { //CH1 SoC_DQS0 SoC_DQS1 SoC_DQS2 SoC_DQS3 + 0x08, 0x08, 0x08, 0x08 + } + } +}; + +/////////////////////////////////////////////////////////// +//MEMORY CONFIGRATION +//PLEASE DEFINE THE FOLLOWING MACRO +/////////////////////////////////////////////////////////// +//0x00... 4Gbit/die +//0x01... 6Gbit/die +//0x02... 8Gbit/die +//0x03...12Gbit/die +//0x04...16Gbit/die +//0x05...24Gbit/die +//0x06...32Gbit/die +//0xff...NO_MEMORY + +//example 1 (8Gbit 2rank device) +#define DBMEMCONF_DENS(ch,cs) (0x02) + +//example 2 (12Gbit 1rank device) +//#define DBMEMCONF_DENS(ch,cs) (!(cs)? 0x03 : 0xff) + +//example 3 (8Gbit 2rank device + 8Gbit 1rank device) +//#define DBMEMCONF_DENS(ch,cs) (!(ch)? 0x02 : !(cs)? 0x02 : 0xff) + +/////////////////////////////////////////////////////////// +//CLOCK DEFINITION +//PLEASE DEFINE +#if 0 //pre-define +//example : 16.66MHz BRD_CLKx3=50 (md14,md13==0,0) +//example : 20.00MHz BRD_CLKx3=60 (md14,md13==0,1) +//example : 25.00MHz BRD_CLKx3=75 (md14,md13==1,0) +//example : 33.33MHz BRD_CLKx3=100 (md14,md13==1,1) +#define _def_BRD_CLKx3 50 +#else +//judge by md14,md13 value (please specify 0) +#define _def_BRD_CLKx3 0 +#endif + +#if 0 //pre-define +// 16.66MHz 20.00MHz 25.00MHz 33.33MHz << board clk +//DDR3200 : 0x5f 0x4f 0x3f 0x2f (md19,17==0,0) +//DDR2800 : 0x53 0x45 0x37 0x29 (md19,17==0,1) +//DDR2400 : 0x47 0x3b 0x2f 0x23 (md19,17==1,0) +//DDR1600 : 0x2f 0x27 0x1f 0x17 (md19,17==1,1) +#define _def_DDR_CLK 0x5f +#else +//judge by md19,md17 value (please specify 0) +#define _def_DDR_CLK 0 +#endif +/////////////////////////////////////////////////////////// +//REFRESH DEFINITION (DO NOT MODIFY) +#if 0 +//define by TCK cycle +//3200Mbps: 1890ns / 625ps = 3024 cycle +//2800Mbps: 1890ns / 714ps = 2646 cycle +//2400Mbps: 1890ns / 833ps = 2268 cycle +//1600Mbps: 1890ns /1300ps = 1512 cycle +#define _def_REFCYCLE 3024 +#define _def_REFPERIOD 0 //in ns (30ns * 63) +#else +//calculated by PERIOD/TCK +//refcycle should be set as 0 +//period should be multiple of (period of board clk) +#define _def_REFCYCLE 0 +#define _def_REFPERIOD 1890 //in ns (30ns * 63) +#endif +/////////////////////////////////////////////////////////// +//DO NOT TOUCH BELOW +/////////////////////////////////////////////////////////// +#define DDRXXXX_CALC(tgt,boardclk,boardclkdiv) ((tgt)*(boardclkdiv)/(boardclk*2)-1) +#define DDRXXXX_RECALC(freq,boardclk,boardclkdiv) (((freq)+1)*(boardclk*2)/(boardclkdiv)) +/// +#define DBMEMCONF_REG(d3,row,bank,col,dw) ((d3)<<30 | ((row)<<24) | ((bank)<<16) | ((col)<<8) | (dw)) +#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density)%2,((density)+1)/2+(29-3-10-2),3,10,2)) +#define DBMEMCONF_VAL(ch,cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch,cs))) +/////////////////////////////////////////////////////////// +#define DDR_PHYVALID 0x03 + +#define DBSC_REFINTS 0x1 // 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. + +/////////////////////////////////////////////////////////// +/* add start */ +#define RST_BASE (0xE6160000U) +#define RST_MODEMR (RST_BASE + 0x0060U) +#define CPG_BASE (0xE6150000U) +#define CPG_PLLECR (CPG_BASE + 0x00D0U) +#define CPG_CPGWPR (CPG_BASE + 0x900U) +#define CPG_PLL3CR (CPG_BASE + 0x0DCU) +#define CPG_SRCR4 (CPG_BASE + 0x0BCU) +#define CPG_SRSTCLR4 (CPG_BASE + 0x950U) +/////////////////////////////////////////////////////////// +#define DBSC_DBSYSCONF1 0xE6790004 +#define DBSC_DBPHYCONF0 0xE6790010 +#define DBSC_DBKIND 0xE6790020 + +#define DBSC_DBMEMCONF_0_0 0xE6790030 +#define DBSC_DBMEMCONF_0_1 0xE6790034 +#define DBSC_DBMEMCONF_1_0 0xE6790040 +#define DBSC_DBMEMCONF_1_1 0xE6790044 +#define DBSC_DBMEMCONF_2_0 0xE6790050 +#define DBSC_DBMEMCONF_2_1 0xE6790054 +#define DBSC_DBMEMCONF_3_0 0xE6790060 +#define DBSC_DBMEMCONF_3_1 0xE6790064 + +#define DBSC_DBMEMCONF_0_2 0xE6790038 +#define DBSC_DBMEMCONF_0_3 0xE679003C +#define DBSC_DBMEMCONF_1_2 0xE6790048 +#define DBSC_DBMEMCONF_1_3 0xE679004C +#define DBSC_DBMEMCONF_2_2 0xE6790058 +#define DBSC_DBMEMCONF_2_3 0xE679005C +#define DBSC_DBMEMCONF_3_2 0xE6790068 +#define DBSC_DBMEMCONF_3_3 0xE679006C + +#define DBSC_DBMEMCONF(ch,cs) (0xE6790030ULL+0x10*ch+0x4*cs) + +#define DBSC_DBSTATE0 0xE6790108 + +#define DBSC_DBACEN 0xE6790200 +#define DBSC_DBRFEN 0xE6790204 +#define DBSC_DBCMD 0xE6790208 +#define DBSC_DBWAIT 0xE6790210 //wait DBCMD 1=busy, 0=ready +#define DBSC_DBSYSCTRL0 0xE6790280 + +#define DBSC_DBTR0 0xE6790300 +#define DBSC_DBTR1 0xE6790304 +#define DBSC_DBTR3 0xE679030C +#define DBSC_DBTR4 0xE6790310 +#define DBSC_DBTR5 0xE6790314 +#define DBSC_DBTR6 0xE6790318 +#define DBSC_DBTR7 0xE679031C +#define DBSC_DBTR8 0xE6790320 +#define DBSC_DBTR9 0xE6790324 +#define DBSC_DBTR10 0xE6790328 +#define DBSC_DBTR11 0xE679032C +#define DBSC_DBTR12 0xE6790330 +#define DBSC_DBTR13 0xE6790334 +#define DBSC_DBTR14 0xE6790338 +#define DBSC_DBTR15 0xE679033C +#define DBSC_DBTR16 0xE6790340 +#define DBSC_DBTR17 0xE6790344 +#define DBSC_DBTR18 0xE6790348 +#define DBSC_DBTR19 0xE679034C +#define DBSC_DBTR20 0xE6790350 +#define DBSC_DBTR21 0xE6790354 +#define DBSC_DBTR22 0xE6790358 +#define DBSC_DBTR23 0xE679035C +#define DBSC_DBTR24 0xE6790360 +#define DBSC_DBTR25 0xE6790364 + +#define DBSC_DBBL 0xE6790400 + +#define DBSC_DBRFCNF1 0xE6790414 +#define DBSC_DBRFCNF2 0xE6790418 + +#define DBSC_DBRNK0 0xE6790430 +#define DBSC_DBRNK1 0xE6790434 +#define DBSC_DBRNK2 0xE6790438 +#define DBSC_DBRNK3 0xE679043C +#define DBSC_DBRNK4 0xE6790440 +#define DBSC_DBRNK5 0xE6790444 +#define DBSC_DBRNK6 0xE6790448 + +#define DBSC_DBADJ0 0xE6790500 +#define DBSC_DBADJ2 0xE6790508 +#define DBSC_DBDBICNT 0xE6790518 + +#define DBSC_DBDFIPMSTRCNF 0xE6790520 + +#define DBSC_DBPDLK_0 0xE6790620 +#define DBSC_DBPDLK_1 0xE6790660 +#define DBSC_DBPDLK_2 0xE67906a0 +#define DBSC_DBPDLK_3 0xE67906e0 + +#define DBSC_INITCOMP_0 0xE6790600 +#define DBSC_INITCOMP_1 0xE6790640 +#define DBSC_INITCOMP_2 0xE6790680 +#define DBSC_INITCOMP_3 0xE67906C0 + +#define DBSC_DBDFICNT_0 0xE6790604 +#define DBSC_DBDFICNT_1 0xE6790644 +#define DBSC_DBDFICNT_2 0xE6790684 +#define DBSC_DBDFICNT_3 0xE67906C4 + +#define DBSC_DBPDCNT0_0 0xE6790610 +#define DBSC_DBPDCNT0_1 0xE6790650 +#define DBSC_DBPDCNT0_2 0xE6790690 +#define DBSC_DBPDCNT0_3 0xE67906D0 + +#define DBSC_DBPDCNT_0 0xE679061C +#define DBSC_DBPDCNT_1 0xE679065C +#define DBSC_DBPDCNT_2 0xE679069C +#define DBSC_DBPDCNT_3 0xE67906DC + +#define DBSC_DBPDRGA_0 0xE6790624 +#define DBSC_DBPDRGD_0 0xE6790628 +#define DBSC_DBPDRGA_1 0xE6790664 +#define DBSC_DBPDRGD_1 0xE6790668 +#define DBSC_DBPDRGA_2 0xE67906A4 +#define DBSC_DBPDRGD_2 0xE67906A8 +#define DBSC_DBPDRGA_3 0xE67906E4 +#define DBSC_DBPDRGD_3 0xE67906E8 +#define DBSC_DBPDRGA(ch) (0xE6790624ULL+0x40*(ch)) +#define DBSC_DBPDRGD(ch) (0xE6790628ULL+0x40*(ch)) + +#define DBSC_DBPDSTAT_0 0xE6790630 +#define DBSC_DBPDSTAT_1 0xE6790670 +#define DBSC_DBPDSTAT_2 0xE67906B0 +#define DBSC_DBPDSTAT_3 0xE67906F0 +#define DBSC_DBPDSTAT(ch) (0xE6790630ULL+0x40*(ch)) + +#define DBSC_DBBUS0CNF0 0xE6790800 +#define DBSC_DBBUS0CNF1 0xE6790804 + +#define DBSC_DBCAM0CNF0 0xE6790900 +#define DBSC_DBCAM0CNF1 0xE6790904 +#define DBSC_DBCAM0CNF2 0xE6790908 +#define DBSC_DBCAM0CNF3 0xE679090C +#define DBSC_DBBCAMDIS 0xE67909FC +#define DBSC_DBSCHCNT0 0xE6791000 +#define DBSC_DBSCHCNT1 0xE6791004 +#define DBSC_DBSCHSZ0 0xE6791010 +#define DBSC_DBSCHRW0 0xE6791020 +#define DBSC_DBSCHRW1 0xE6791024 + +#define DBSC_DBSCHQOS_0_0 0xE6791030 +#define DBSC_DBSCHQOS_0_1 0xE6791034 +#define DBSC_DBSCHQOS_0_2 0xE6791038 +#define DBSC_DBSCHQOS_0_3 0xE679103C +#define DBSC_DBSCHQOS_4_0 0xE6791070 +#define DBSC_DBSCHQOS_4_1 0xE6791074 +#define DBSC_DBSCHQOS_4_2 0xE6791078 +#define DBSC_DBSCHQOS_4_3 0xE679107C +#define DBSC_DBSCHQOS_9_0 0xE67910C0 +#define DBSC_DBSCHQOS_9_1 0xE67910C4 +#define DBSC_DBSCHQOS_9_2 0xE67910C8 +#define DBSC_DBSCHQOS_9_3 0xE67910CC +#define DBSC_DBSCHQOS_13_0 0xE6791100 +#define DBSC_DBSCHQOS_13_1 0xE6791104 +#define DBSC_DBSCHQOS_13_2 0xE6791108 +#define DBSC_DBSCHQOS_13_3 0xE679110C +#define DBSC_DBSCHQOS_14_0 0xE6791110 +#define DBSC_DBSCHQOS_14_1 0xE6791114 +#define DBSC_DBSCHQOS_14_2 0xE6791118 +#define DBSC_DBSCHQOS_14_3 0xE679111C +#define DBSC_DBSCHQOS_15_0 0xE6791120 +#define DBSC_DBSCHQOS_15_1 0xE6791124 +#define DBSC_DBSCHQOS_15_2 0xE6791128 +#define DBSC_DBSCHQOS_15_3 0xE679112C + +#define DBSC_DBSCTR0 0xE6791700 +#define DBSC_DBSCTR1 0xE6791708 +#define DBSC_DBSCHRW2 0xE679170C + +#define DBSC_SCFCTST0 0xE6791700 //Schedule timing setting register 0 +#define DBSC_SCFCTST1 0xE6791708 //Schedule timing setting register 1 +#define DBSC_SCFCTST2 0xE679170C //Schedule timing setting register 2 + +#define DBSC_DBMRRDR(ch) (0xE6791800ULL+0x4*(ch)) +#define DBSC_DBMRRDR_0 0xE6791800 +#define DBSC_DBMRRDR_1 0xE6791804 +#define DBSC_DBMRRDR_2 0xE6791808 +#define DBSC_DBMRRDR_3 0xE679180C + +#define DBSC_DBMEMSWAPCONF0 0xE6792000 + +#define DBSC_DBMONCONF4 0xE6793010 + +#define DBSC_PLL_LOCK(ch) (0xE6794054ULL+0x100*(ch)) +#define DBSC_PLL_LOCK_0 0xE6794054 +#define DBSC_PLL_LOCK_1 0xE6794154 +#define DBSC_PLL_LOCK_2 0xE6794254 +#define DBSC_PLL_LOCK_3 0xE6794354 + +#define DBSC_DBTSTCONF1 0xE6794804 + +#define DBSC_FREQ_CHG_ACK_0 0xE6790618 +#define DBSC_FREQ_CHG_ACK_1 0xE6790658 +#define DBSC_FREQ_CHG_ACK_2 0xE6790698 +#define DBSC_FREQ_CHG_ACK_3 0xE67906D8 + +#define DBSC_DFI_FREQ_0 0xE6790614 +#define DBSC_DFI_FREQ_1 0xE6790654 +#define DBSC_DFI_FREQ_2 0xE6790694 +#define DBSC_DFI_FREQ_3 0xE67906D4 + +#include "init_dram_tbl_m3_es10.h" +uint32_t BRD_CLKx3; +uint32_t DDR1600_CLK; +uint32_t DDR2400_CLK; +uint32_t DDR2800_CLK; +uint32_t DDR3200_CLK; +uint32_t DDR_CLK; +uint32_t _cnf_DDR_PHY_SLICE_REGSET[128][2]; +uint32_t _cnf_DDR_PHY_ADR_V_REGSET[128][2]; +uint32_t _cnf_DDR_PHY_ADR_I_REGSET[128][2]; +uint32_t _cnf_DDR_PHY_ADR_G_REGSET[128][2]; +uint32_t _cnf_DDR_PI_REGSET[255 +1][2]; +static uint32_t InitDDR_start(uint32_t freq); +static void SoftDelay_ddr(uint32_t loop); +static inline void dsb_sev(void); +static uint32_t PLL3_MODE; +uint32_t InitResetCount; +uint32_t PadCalFailCount; +uint32_t TrainingFailCount; +static inline uint32_t PLL3_FREQ_01(); +static inline uint32_t PLL3_FREQ_10(); +static inline uint32_t PLL3_FREQ(uint32_t freq_flag_b,uint32_t freq_flag_a); +static void WaitDBCMD(void); +static void SendDBCMD(uint32_t cmd); +static void REG_DDRPHY_WRITE_A ( uint32_t regadd, uint32_t regdata); +static void REG_DDRPHY_WRITE ( uintptr_t phyno, uint32_t regadd, uint32_t regdata); +static uint32_t REG_DDRPHY_READ ( uintptr_t phyno, uint32_t regadd); +static void change_lpddr4_en(uintptr_t phychno, uint32_t mode); +static void pvt_dbsc_regset(uint32_t freq); +static void mode_register_set(uint32_t freq,uintptr_t phychno,uint32_t mr13_val,uint32_t postflag); +static inline void ResetDram() +{ + *((volatile uint32_t*)CPG_CPGWPR) = ~0x40000000; + dsb_sev(); + *((volatile uint32_t*)CPG_SRCR4) = 0x40000000; + *((volatile uint32_t*)CPG_SRSTCLR4) = 0x40000000; + dsb_sev(); +} +static void SoftDelay_ddr(uint32_t loop) +{ + volatile uint32_t i; + for(i=0;i<(loop*2);i++){}; +} +static inline void dsb_sev(void) +{ + __asm__ __volatile__ ("dsb sy"); +} +static inline void ddrphy_regif_wa() +{ + *((volatile uint32_t*)(DBSC_DBPDRGA_0)) = 0x02A9; + *((volatile uint32_t*)(DBSC_DBPDRGA_1)) = 0x02A9; + dsb_sev(); +} +static void SendDBCMD(uint32_t cmd) +{ + uint32_t dataL; + uint32_t count; + count=0; + dataL = *((volatile uint32_t*)DBSC_DBCMD); + dsb_sev(); + while(1) + { + dataL = *((volatile uint32_t*)DBSC_DBWAIT); + dsb_sev(); + if((dataL & 0x00000001) == 0x0) break; + count++; + } + *((volatile uint32_t*)DBSC_DBCMD) = cmd; + dsb_sev(); +} +static void WaitDBCMD(void) +{ + uint32_t dataL; + dataL = *((volatile uint32_t*)DBSC_DBCMD); + dsb_sev(); + while(1) + { + dataL = *((volatile uint32_t*)DBSC_DBWAIT); + dsb_sev(); + if((dataL & 0x00000001) == 0x0) break; + } +} +static uint32_t REG_DDRPHY_READ ( uintptr_t phyno, uint32_t regadd) +{ + uint32_t val,loop; + *((volatile uint32_t*)(DBSC_DBPDRGA_0 + 0x40 * phyno)) = regadd; + dsb_sev(); + val = *((volatile uint32_t*)(DBSC_DBPDRGA_0 + 0x40 * phyno)); + dsb_sev(); + for(loop=0;loop<(PLL3_MODE?1:8);loop++){ + val = *((volatile uint32_t*)(DBSC_DBPDRGD_0 + 0x40 * phyno)); + dsb_sev(); + } + (void)val; + return val ; +} +static void REG_DDRPHY_WRITE ( uintptr_t phyno, uint32_t regadd, uint32_t regdata) +{ + uint32_t val,loop; + *((volatile uint32_t*)(DBSC_DBPDRGA_0 + 0x40 * phyno)) = regadd; + dsb_sev(); + *((volatile uint32_t*)(DBSC_DBPDRGD_0 + 0x40 * phyno)) = regdata; + dsb_sev(); + for(loop=0;loop<(PLL3_MODE?1:30);loop++){ + val = *((volatile uint32_t*)(DBSC_DBPDRGD_0 + 0x40 * phyno)); + dsb_sev(); + } + (void)val; +} +static void REG_DDRPHY_WRITE_A ( uint32_t regadd, uint32_t regdata) +{ + uint32_t val,loop; + uintptr_t phyno; + for(phyno=0;phyno> (cs*8))&0xff; + if(dataL!=0x4d){ + ddr_density_tp[ch][cs]=0xff; + ddr_density_e1[ch][cs]++; + } + } + for(ch=0;ch> (cs*8))&0xff)>>2; + if(ddr_density_tp[ch][cs]==0xff || (i>0 && (ddr_density_tp[ch][cs]!=dataL))){ + ddr_density_e2[ch][cs]++; + ddr_density_tp[ch][cs]=0xff; + } else { + ddr_density_tp[ch][cs]=dataL; + } + } + } + } + for(ch=0;ch=2) + { + from=0; to=1; + } + else + { + from=phychno; to=phychno; + } + for(i=from;i<=to;i++) + { + set = 1ULL <<14; + clr = ~set; + if(!mode) + { + set = 0; + }; + addr=0x0BA0; REG_DDRPHY_WRITE(i,addr,dataL=((REG_DDRPHY_READ(i,addr)&clr)|set) ); + addr=0x0BA1; REG_DDRPHY_WRITE(i,addr,dataL=((REG_DDRPHY_READ(i,addr)&clr)|set) ); + addr=0x0BA7; REG_DDRPHY_WRITE(i,addr,dataL=((REG_DDRPHY_READ(i,addr)&clr)|set) ); + addr=0x0BAB; REG_DDRPHY_WRITE(i,addr,dataL=((REG_DDRPHY_READ(i,addr)&clr)|set) ); + } + ddrphy_regif_wa(); +} +static void pvt_dbsc_regset(uint32_t freq) +{ + *((volatile uint32_t*)DBSC_DBPDCNT0_0) = 0x00; + *((volatile uint32_t*)DBSC_DBPDCNT0_1) = 0x00; + *((volatile uint32_t*)DBSC_DBSTATE0) = 0x00000010; + *((volatile uint32_t*)DBSC_DBKIND) = 0x0000000a; + *((volatile uint32_t*)DBSC_DBBL) = 0x00000002; + { + uint32_t ch,cs; + for(ch=0;chDDR3200_CLK && 0) + { + *((volatile uint32_t*)DBSC_DBTR0) = 0x00000020; + *((volatile uint32_t*)DBSC_DBTR1) = 0x0000000e; + *((volatile uint32_t*)DBSC_DBTR3) = 0x00000022; + *((volatile uint32_t*)DBSC_DBTR4) = 0x00280022; + *((volatile uint32_t*)DBSC_DBTR5) = 0x00000071; + *((volatile uint32_t*)DBSC_DBTR6) = 0x0000004f; + *((volatile uint32_t*)DBSC_DBTR7) = 0x00130013; + *((volatile uint32_t*)DBSC_DBTR8) = 0x0000004B; + *((volatile uint32_t*)DBSC_DBTR9) = 0x0000000E; + *((volatile uint32_t*)DBSC_DBTR10) = 0x00000023; + *((volatile uint32_t*)DBSC_DBTR11) = 0x00000026; + *((volatile uint32_t*)DBSC_DBTR12) = 0x002A002A; + *((volatile uint32_t*)DBSC_DBTR13) = 0x00900120; + *((volatile uint32_t*)DBSC_DBTR14) = 0x000c000c; + *((volatile uint32_t*)DBSC_DBTR15) = 0x001e000c; + *((volatile uint32_t*)DBSC_DBTR16) = (0x0d1f0c0e); + *((volatile uint32_t*)DBSC_DBTR17) = 0x080a0004; + *((volatile uint32_t*)DBSC_DBTR18) = 0x00000000; + *((volatile uint32_t*)DBSC_DBTR19) = 0x00000000; + *((volatile uint32_t*)DBSC_DBTR20) = 0x012c012c; + *((volatile uint32_t*)DBSC_DBTR21) = (8) |((8)<<16); + *((volatile uint32_t*)DBSC_DBTR22) = 0x06400030; + *((volatile uint32_t*)DBSC_DBTR23) = 0x00000002; + *((volatile uint32_t*)DBSC_DBTR24) = (0x06100509); + } + else if(freq>DDR2800_CLK || 1) + { + *((volatile uint32_t*)DBSC_DBTR0) = 0x00000020; + *((volatile uint32_t*)DBSC_DBTR1) = 0x0000000e; + *((volatile uint32_t*)DBSC_DBTR3) = 0x0000001d; + *((volatile uint32_t*)DBSC_DBTR4) = 0x0022001d; + *((volatile uint32_t*)DBSC_DBTR5) = 0x00000060; + *((volatile uint32_t*)DBSC_DBTR6) = 0x00000044; + *((volatile uint32_t*)DBSC_DBTR7) = 0x00100010; + *((volatile uint32_t*)DBSC_DBTR8) = 0x00000040; + *((volatile uint32_t*)DBSC_DBTR9) = 0x0000000c; + *((volatile uint32_t*)DBSC_DBTR10) = 0x0000001d; + *((volatile uint32_t*)DBSC_DBTR11) = 0x00000025; + *((volatile uint32_t*)DBSC_DBTR12) = 0x00270027; + *((volatile uint32_t*)DBSC_DBTR13) = 0x00900120; + *((volatile uint32_t*)DBSC_DBTR14) = 0x000c000c; + *((volatile uint32_t*)DBSC_DBTR15) = 0x001e000c; + *((volatile uint32_t*)DBSC_DBTR16) = (0x0d1f0c0e); + *((volatile uint32_t*)DBSC_DBTR17) = 0x080a0004; + *((volatile uint32_t*)DBSC_DBTR18) = 0x00000000; + *((volatile uint32_t*)DBSC_DBTR19) = 0x00000000; + *((volatile uint32_t*)DBSC_DBTR20) = 0x012c012c; + *((volatile uint32_t*)DBSC_DBTR21) = (8) |((8)<<16); + *((volatile uint32_t*)DBSC_DBTR22) = 0x06400030; + *((volatile uint32_t*)DBSC_DBTR23) = 0x00000002; + *((volatile uint32_t*)DBSC_DBTR24) = (0x06100509); + } + else if(freq>DDR2400_CLK) + { + *((volatile uint32_t*)DBSC_DBTR0) = 0x0000001c; + *((volatile uint32_t*)DBSC_DBTR1) = 0x0000000e; + *((volatile uint32_t*)DBSC_DBTR3) = 0x0000001a; + *((volatile uint32_t*)DBSC_DBTR4) = 0x001e001a; + *((volatile uint32_t*)DBSC_DBTR5) = 0x00000055; + *((volatile uint32_t*)DBSC_DBTR6) = 0x0000003b; + *((volatile uint32_t*)DBSC_DBTR7) = 0x000f000f; + *((volatile uint32_t*)DBSC_DBTR8) = 0x00000039; + *((volatile uint32_t*)DBSC_DBTR9) = 0x0000000c; + *((volatile uint32_t*)DBSC_DBTR10) = 0x0000001E; + *((volatile uint32_t*)DBSC_DBTR11) = 0x00000022; + *((volatile uint32_t*)DBSC_DBTR12) = 0x00260026; + *((volatile uint32_t*)DBSC_DBTR13) = 0x007f00fd; + *((volatile uint32_t*)DBSC_DBTR14) = 0x000c000c; + *((volatile uint32_t*)DBSC_DBTR15) = 0x0016000b; + *((volatile uint32_t*)DBSC_DBTR16) = (0x0d1f0c0e); + *((volatile uint32_t*)DBSC_DBTR17) = 0x0c0f0020; + *((volatile uint32_t*)DBSC_DBTR18) = 0x00000000; + *((volatile uint32_t*)DBSC_DBTR19) = 0x00000000; + *((volatile uint32_t*)DBSC_DBTR20) = 0x01070107; + *((volatile uint32_t*)DBSC_DBTR21) = (8) |((8)<<16); + *((volatile uint32_t*)DBSC_DBTR22) = 0x06400030; + *((volatile uint32_t*)DBSC_DBTR23) = 0x00000002; + *((volatile uint32_t*)DBSC_DBTR24) = (0x06100509); + } + else if(freq>DDR1600_CLK) + { + *((volatile uint32_t*)DBSC_DBTR0) = 0x00000018; + *((volatile uint32_t*)DBSC_DBTR1) = 0x0000000c; + *((volatile uint32_t*)DBSC_DBTR3) = 0x00000016; + *((volatile uint32_t*)DBSC_DBTR4) = 0x001a0016; + *((volatile uint32_t*)DBSC_DBTR5) = 0x00000049; + *((volatile uint32_t*)DBSC_DBTR6) = 0x00000033; + *((volatile uint32_t*)DBSC_DBTR7) = 0x000d000d; + *((volatile uint32_t*)DBSC_DBTR8) = 0x00000031; + *((volatile uint32_t*)DBSC_DBTR9) = 0x0000000a; + *((volatile uint32_t*)DBSC_DBTR10) = 0x00000016; + *((volatile uint32_t*)DBSC_DBTR11) = 0x0000001c; + *((volatile uint32_t*)DBSC_DBTR12) = 0x00220022; + *((volatile uint32_t*)DBSC_DBTR13) = 0x006d00d9; + *((volatile uint32_t*)DBSC_DBTR14) = 0x000a000a; + *((volatile uint32_t*)DBSC_DBTR15) = 0x0013000c; + *((volatile uint32_t*)DBSC_DBTR16) = (0x0d1f0c0e); + *((volatile uint32_t*)DBSC_DBTR17) = 0x080a0004; + *((volatile uint32_t*)DBSC_DBTR18) = 0x00000000; + *((volatile uint32_t*)DBSC_DBTR19) = 0x00000000; + *((volatile uint32_t*)DBSC_DBTR20) = 0x00e200e2; + *((volatile uint32_t*)DBSC_DBTR21) = (8) |((8)<<16); + *((volatile uint32_t*)DBSC_DBTR22) = 0x04b10025; + *((volatile uint32_t*)DBSC_DBTR23) = 0x00000002; + *((volatile uint32_t*)DBSC_DBTR24) = (0x06100509); + } + else + { + *((volatile uint32_t*)DBSC_DBTR0) = 0x0000000e; + *((volatile uint32_t*)DBSC_DBTR1) = 0x0000000c; + *((volatile uint32_t*)DBSC_DBTR3) = 0x0000000f; + *((volatile uint32_t*)DBSC_DBTR4) = 0x0011000f; + *((volatile uint32_t*)DBSC_DBTR5) = 0x00000030; + *((volatile uint32_t*)DBSC_DBTR6) = 0x00000022; + *((volatile uint32_t*)DBSC_DBTR7) = 0x00080008; + *((volatile uint32_t*)DBSC_DBTR8) = 0x00000020; + *((volatile uint32_t*)DBSC_DBTR9) = 0x00000006; + *((volatile uint32_t*)DBSC_DBTR10) = 0x0000000f; + *((volatile uint32_t*)DBSC_DBTR11) = 0x00000011; + *((volatile uint32_t*)DBSC_DBTR12) = 0x001D001D; + *((volatile uint32_t*)DBSC_DBTR13) = 0x00480090; + *((volatile uint32_t*)DBSC_DBTR14) = 0x00060006; + *((volatile uint32_t*)DBSC_DBTR15) = 0x000c0006; + *((volatile uint32_t*)DBSC_DBTR16) = (0x0d1f0c0e); + *((volatile uint32_t*)DBSC_DBTR17) = 0x080a0004; + *((volatile uint32_t*)DBSC_DBTR18) = 0x00000000; + *((volatile uint32_t*)DBSC_DBTR19) = 0x00000000; + *((volatile uint32_t*)DBSC_DBTR20) = 0x00b00096; + *((volatile uint32_t*)DBSC_DBTR21) = (8) |((8)<<16); + *((volatile uint32_t*)DBSC_DBTR22) = 0x03200018; + *((volatile uint32_t*)DBSC_DBTR23) = 0x00000002; + *((volatile uint32_t*)DBSC_DBTR24) = (0x06100509); + } + *((volatile uint32_t*)DBSC_DBTR16) = (0x0d1f0c0e); + *((volatile uint32_t*)DBSC_DBRNK0) = 0x00000000; + *((volatile uint32_t*)DBSC_DBRNK1) = 0x00000000; + *((volatile uint32_t*)DBSC_DBRNK2) = ( ((((0x8888)>>0)&0xf)<<12) | ((((0x8888)>>0)&0xf)<<8) | ((((0x8888)>>0)&0xf)<<4) | (((0x8888)>>0)&0xf)); + *((volatile uint32_t*)DBSC_DBRNK3) = ( ((((0x8888)>>4)&0xf)<<12) | ((((0x8888)>>4)&0xf)<<8) | ((((0x8888)>>4)&0xf)<<4) | (((0x8888)>>4)&0xf)); + *((volatile uint32_t*)DBSC_DBRNK4) = ( ((((0x8888)>>8)&0xf)<<12) | ((((0x8888)>>8)&0xf)<<8) | ((((0x8888)>>8)&0xf)<<4) | (((0x8888)>>8)&0xf)); + *((volatile uint32_t*)DBSC_DBRNK5) = ( ((((0x8888)>>12)&0xf)<<12) | ((((0x8888)>>12)&0xf)<<8) | ((((0x8888)>>12)&0xf)<<4) | (((0x8888)>>12)&0xf)); + *((volatile uint32_t*)DBSC_DBRNK6) = 0x00000000; + *((volatile uint32_t*)DBSC_DBADJ0) = 0x00000000; + *((volatile uint32_t*)DBSC_DBADJ2) = 0x00000000; + *((volatile uint32_t*)DBSC_DBSYSCONF1) = 0x00000002; + *((volatile uint32_t*)DBSC_DBCAM0CNF1) = 0x00044218; + *((volatile uint32_t*)DBSC_DBCAM0CNF2) = 0x00000284; + if(freq>DDR3200_CLK || 1) + { + *((volatile uint32_t*)DBSC_SCFCTST0) = 0x18030d09; + *((volatile uint32_t*)DBSC_SCFCTST1) = 0x090a080c; + } + else if(freq>DDR2800_CLK) + { + *((volatile uint32_t*)DBSC_SCFCTST0) = 0x18030d09; + *((volatile uint32_t*)DBSC_SCFCTST1) = 0x090a080c; + } + else if(freq>DDR2400_CLK) + { + *((volatile uint32_t*)DBSC_SCFCTST0) = 0x180b1408; + *((volatile uint32_t*)DBSC_SCFCTST1) = 0x0a0b080C; + } + else if(freq>DDR1600_CLK) + { + *((volatile uint32_t*)DBSC_SCFCTST0) = 0x180B1708; + *((volatile uint32_t*)DBSC_SCFCTST1) = 0x0808070C; + } + else + { + *((volatile uint32_t*)DBSC_SCFCTST0) = 0x0c020905; + *((volatile uint32_t*)DBSC_SCFCTST1) = 0x0508040C; + } + *((volatile uint32_t*)DBSC_DBMONCONF4 ) = 0x00700000 | (*((volatile uint32_t*)DBSC_DBMONCONF4 )); + if((1)){ + *((volatile uint32_t*)DBSC_DBTR16) = *((volatile uint32_t*)DBSC_DBTR16)-0x0101; + *((volatile uint32_t*)DBSC_DBTR24) = *((volatile uint32_t*)DBSC_DBTR24)-0x0001; + } +} +static void mode_register_set(uint32_t freq,uintptr_t phychno,uint32_t mr13_val,uint32_t postflag) +{ + uint32_t DDR_MR1, DDR_MR2; + SendDBCMD(0x0e040d00|(0x00100000 * phychno)|mr13_val); + if(0 && freq>DDR3200_CLK){ + DDR_MR1 = 0xe4; + DDR_MR2 = (2) ? 0x36 : + 0x37 ; + } else if(1 || freq>DDR2400_CLK) { + DDR_MR1 = 0xd4; + DDR_MR2 = (2) ? 0x2d : + 0x2e ; + } else if(freq>DDR1600_CLK) { + DDR_MR1 = 0xc4; + DDR_MR2 = 0x24; + } else { + DDR_MR1 = 0xa4; + DDR_MR2 = 0x52; + } + SendDBCMD(0x0e040100|(0x00100000 * phychno)|DDR_MR1); + SendDBCMD(0x0e040200|(0x00100000 * phychno)|DDR_MR2); + if((postflag && ((2)==2)) || ((2)==1)) { + SendDBCMD(0x0e040300|(0x00100000 * phychno)|0x31|0xC0); + } else { + SendDBCMD(0x0e040300|(0x00100000 * phychno)|0x31); + } + if((postflag == 1) && (0)){ + } else { + SendDBCMD(0x0e040b00|(0x00100000 * phychno)|(0x36)); + SendDBCMD(0x0e040c00|(0x00100000 * phychno)|(0x11)); + SendDBCMD(0x0e040e00|(0x00100000 * phychno)|(0x11)); + } + SendDBCMD(0x0e041600|(0x00100000 * phychno)|0x16); +} +static inline uint32_t PLL3_FREQ_01() +{ + uint32_t dataL; + uint32_t count; + count = 100000; + do { + dataL = (*((volatile uint32_t*)DBSC_DBPDSTAT_0)) & + (*((volatile uint32_t*)DBSC_DBPDSTAT_1)) & 0x00000001; + count = count -1; + } while( (dataL!=0x00000001) & (count !=0)); + if(count == 0) { + NOTICE("PLL3_FREQ_01:Time out[1]"); + return (1); + } + *((volatile uint32_t*)CPG_CPGWPR) = ~(0x001f001f); + *((volatile uint32_t*)CPG_PLLECR) = 0x001f001f ; + PLL3_MODE=1; + dsb_sev(); + do { + dataL=*((volatile uint32_t*)CPG_PLLECR); + } while( (dataL&0x1f00)!=0x1f00 ); + SoftDelay_ddr(1000); + *((volatile uint32_t*)DBSC_DBDFICNT_0) = 0x01000010; + *((volatile uint32_t*)DBSC_DBDFICNT_1) = 0x01000010; + dsb_sev(); + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_0)) = 0x0CF20000; + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_1)) = 0x0CF20000; + dsb_sev(); + count = 1000000; + do { + dataL = ((*((volatile uint32_t*)DBSC_DBPDSTAT_0)) | + (*((volatile uint32_t*)DBSC_DBPDSTAT_1))) & 0x00000001; + count = count -1; + } while( (dataL==0x00000001) & (count !=0)); + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_0)) = 0x00000000; + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_1)) = 0x00000000; + dsb_sev(); + if(count == 0) { + NOTICE("PLL3_FREQ_01:Time out[2]"); + return (1); + } + return (0); +} +static inline uint32_t PLL3_FREQ_10() +{ + uint32_t dataL; + uint32_t count; + count = 10000000; + do { + dataL = (*((volatile uint32_t*)DBSC_DBPDSTAT_0)) & + (*((volatile uint32_t*)DBSC_DBPDSTAT_1)) & 0x00000001; + count = count -1; + } while( (dataL!=0x00000001) & (count !=0)); + if(count == 0) { + NOTICE("PLL3_FREQ_10:Time out[1]"); + return (1); + } + *((volatile uint32_t*)CPG_CPGWPR) = ~(0x001f0017); + *((volatile uint32_t*)CPG_PLLECR) = 0x001f0017 ; + PLL3_MODE=0; + dsb_sev(); + *((volatile uint32_t*)DBSC_DBDFICNT_0) = 0x00000010; + *((volatile uint32_t*)DBSC_DBDFICNT_1) = 0x00000010; + dsb_sev(); + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_0)) = 0x0CF20000; + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_1)) = 0x0CF20000; + dsb_sev(); + count = 100000; + do { + dataL = ((*((volatile uint32_t*)DBSC_DBPDSTAT_0)) | + (*((volatile uint32_t*)DBSC_DBPDSTAT_1))) & 0x00000001; + count = count -1; + } while( (dataL==0x00000001) & (count !=0)); + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_0)) = 0x00000000; + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_1)) = 0x00000000; + if(count == 0) { + NOTICE("PLL3_FREQ_10:Time out[2]"); + return (1); + } + return (0); +} +static inline uint32_t PLL3_FREQ(uint32_t freq_flag_b,uint32_t freq_flag_a) +{ + uint32_t dataL; + uint32_t count; + count = 100000; + do { + dataL = (*((volatile uint32_t*)DBSC_DBPDSTAT_0)) & + (*((volatile uint32_t*)DBSC_DBPDSTAT_1)) & 0x00000001; + count = count -1; + } while( (dataL!=0x00000001) & (count !=0)); + if(count == 0) { + return (1); + } + if(freq_flag_a == 0){ + *((volatile uint32_t*)CPG_CPGWPR) = ~(0x001f0017); + *((volatile uint32_t*)CPG_PLLECR) = 0x001f0017 ; + PLL3_MODE=0; + dsb_sev(); + } else if((freq_flag_b == 0)&(freq_flag_a == 1)){ + *((volatile uint32_t*)CPG_CPGWPR) = ~(0x001f001f); + *((volatile uint32_t*)CPG_PLLECR) = 0x001f001f ; + PLL3_MODE=1; + dsb_sev(); + do { + dataL=*((volatile uint32_t*)CPG_PLLECR); + } while( (dataL&0x1f00)!=0x1f00 ); + } + dsb_sev(); + *((volatile uint32_t*)DBSC_DBDFICNT_0) = freq_flag_a << 24| 0x10; + *((volatile uint32_t*)DBSC_DBDFICNT_1) = freq_flag_a << 24| 0x10; + dsb_sev(); + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_0)) = 0x0CF20000; + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_1)) = 0x0CF20000; + count = 100000; + do { + dataL = ((*((volatile uint32_t*)DBSC_DBPDSTAT_0)) | + (*((volatile uint32_t*)DBSC_DBPDSTAT_1))) & 0x00000001; + count = count -1; + } while( (dataL==0x00000001) & (count !=0)); + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_0)) = 0x00000000; + *((volatile uint32_t*)(DBSC_FREQ_CHG_ACK_1)) = 0x00000000; + if(count == 0) { + NOTICE("Time out[2]"); + return (1); + } + return (0); +} +static uint32_t pvt_pi_training_go_all(uint32_t freq) +{ + uint32_t flag; + uint32_t dataL; + uint32_t retry; + uintptr_t ch; + uint32_t mst_ch; + uint32_t cur_frq; + uint32_t complete; + uint32_t frqchg_req; + *((volatile uint32_t*)DBSC_DBDFICNT_0) = 0x01000010; + *((volatile uint32_t*)DBSC_DBDFICNT_1) = 0x01000010; + dsb_sev(); + for(ch=0;ch>0)&0x1); + if(frqchg_req){ + if(cur_frq){ + flag=PLL3_FREQ_10(); + cur_frq=0; + } else { + flag=PLL3_FREQ_01(); + cur_frq=1; + } + retry=4096; + if(flag)break; + } else { + if(cur_frq){ + for(ch=0;ch> 8; + REG_DDRPHY_WRITE( ch, 0x02AA, dataL); + } + return complete; +} +static void ConfigTBL(void){ + _TBLCOPY(_cnf_DDR_PHY_SLICE_REGSET, DDR_PHY_SLICE_REGSET); + _TBLCOPY(_cnf_DDR_PHY_ADR_V_REGSET, DDR_PHY_ADR_V_REGSET); + _TBLCOPY(_cnf_DDR_PHY_ADR_I_REGSET, DDR_PHY_ADR_I_REGSET); + _TBLCOPY(_cnf_DDR_PHY_ADR_G_REGSET, DDR_PHY_ADR_G_REGSET); + _TBLCOPY(_cnf_DDR_PI_REGSET, DDR_PI_REGSET); + if((1)){ + REG_DDRTBL_MOD(_cnf_DDR_PHY_SLICE_REGSET,0x0805,0x00FFFFFF,(0x006E6E0E)); + REG_DDRTBL_MOD(_cnf_DDR_PHY_SLICE_REGSET,0x0806,0x00FFFFFF,(0x006E6E0E)); + } + if((4)==4){ + REG_DDRTBL_MOD(_cnf_DDR_PHY_SLICE_REGSET,0x084D, 0x03FF0000, 0x00000200<<16); + } + if((1)){ + REG_DDRTBL_MOD(_cnf_DDR_PHY_SLICE_REGSET,0x084D, 0x00000300, 0x100); + REG_DDRTBL_WRITE(_cnf_DDR_PI_REGSET,0x0255 ,REG_DDRTBL_READ(_cnf_DDR_PI_REGSET,0x0255)-0x010101); + REG_DDRTBL_WRITE(_cnf_DDR_PI_REGSET,0x022B ,REG_DDRTBL_READ(_cnf_DDR_PI_REGSET,0x022B)-0x01000001); + REG_DDRTBL_WRITE(_cnf_DDR_PI_REGSET,0x022C ,REG_DDRTBL_READ(_cnf_DDR_PI_REGSET,0x022C)-0x00010000); + } + if((3) != (3)){ + REG_DDRTBL_MOD(_cnf_DDR_PHY_ADR_V_REGSET,0x0A10, 0x00000003, (3)<<0); + } +} +static uint32_t InitDDR_start(uint32_t freq) +{ + uint32_t i=0; + uint32_t k=0; + uint32_t dataL=0; + uint32_t phytrainingok=0x0; + uint32_t retry; + uintptr_t ch,slice; + uint32_t ddr_csn; + uint32_t cs; + *((volatile uint32_t*)DBSC_DBPDCNT0_0) = 0x01; + *((volatile uint32_t*)DBSC_DBPDCNT0_1) = 0x01; + dsb_sev(); + pvt_dbsc_regset(freq); + *((volatile uint32_t*)DBSC_DBPDCNT0_0) = 0x00; + *((volatile uint32_t*)DBSC_DBPDCNT0_1) = 0x00; + *((volatile uint32_t*)DBSC_DBPDLK_0) = 0x0000A55A; + *((volatile uint32_t*)DBSC_DBPDLK_1) = 0x0000A55A; + for (ch=0;ch=BOARDNUM){ + NOTICE("DDR:Unknown Board"); + } else { + for(ch=0;ch> (8*slice)) %2 ) { + REG_DDRPHY_WRITE(ch,0x820+slice*0x80,REG_DDRTBL_READ(_cnf_DDR_PHY_SLICE_REGSET,0x820) & 0xff00ffff); + } else { + REG_DDRPHY_WRITE(ch,0x820+slice*0x80,(REG_DDRTBL_READ(_cnf_DDR_PHY_SLICE_REGSET,0x820) & 0xff00ffff) | 0x00010000); + } + } + REG_DDRPHY_WRITE(ch,0xa0c,(BOARDCNF_CA_SWAP[_def_BOARDTYPE][ch] | 0x00888888)); + REG_DDRPHY_WRITE(ch,0xa0d,0x00000000); + REG_DDRPHY_WRITE(ch,0xa0e,(BOARDCNF_CA_SWAP[_def_BOARDTYPE][ch] | 0x00888888)); + REG_DDRPHY_WRITE(ch,0xa0f,((1)<<24) | 0x00000000); + dataL=0; + k=BOARDCNF_CA_SWAP[_def_BOARDTYPE][ch]; + for(i=0;i<6;i++){ + dataL|= ((k&0xf)<<(i*5)); + k=k>>4; + } + REG_DDRPHY_WRITE(ch,0xa1c,dataL); + dataL=0; + k=BOARDCNF_DQS_SWAP[_def_BOARDTYPE][ch]; + for(i=0;i<4;i++){ + dataL|= ((k&0x3)<<(i*2)); + k=k>>4; + } + REG_DDRPHY_WRITE(ch,0xbbc,(REG_DDRTBL_READ(_cnf_DDR_PHY_ADR_G_REGSET,0xbbc) & 0xff00ffff) | (dataL<<16)); + } + for(ch=0;ch4096){ + phytrainingok &= ~(1<>16; + if(dly>(0x180)) + REG_DDRPHY_WRITE(ch,0x084D +slice*0x80,REG_DDRPHY_READ(ch,0x084D +slice*0x80)- 0x0100); + } + } + } +} + for(ch=0;ch0); + if(retry==0){ + } + else + { + } + dsb_sev(); + for(ch=0;ch>13)&0x3; + switch(md){ + case 0x0 : BRD_CLKx3 = 50; break; + case 0x1 : BRD_CLKx3 = 60; break; + case 0x2 : BRD_CLKx3 = 75; break; + case 0x3 : BRD_CLKx3 =100; break; + } + } else { + BRD_CLKx3 = _def_BRD_CLKx3; + } + DDR1600_CLK = DDRXXXX_CALC(1600,BRD_CLKx3,3); + DDR2400_CLK = DDRXXXX_CALC(2400,BRD_CLKx3,3); + DDR2800_CLK = DDRXXXX_CALC(2800,BRD_CLKx3,3); + DDR3200_CLK = DDRXXXX_CALC(3200,BRD_CLKx3,3); + if(_def_DDR_CLK==0) { + md = ((*((volatile uint32_t*)RST_MODEMR))>>17) & 0x5; + md = (md|(md>>1))&0x3; + switch(md){ + case 0x0 : DDR_CLK = DDR3200_CLK; break; + case 0x1 : DDR_CLK = DDR2800_CLK; break; + case 0x2 : DDR_CLK = DDR2400_CLK; break; + case 0x3 : DDR_CLK = DDR1600_CLK; break; + } + } else { + DDR_CLK = _def_DDR_CLK; + } + NOTICE("BL2: DDR%d(%s)\n", DDRXXXX_RECALC(DDR_CLK,BRD_CLKx3,3), RCAR_DDR_VERSION); + *((volatile uint32_t*)CPG_CPGWPR) = ~(DDR_CLK<<24); + *((volatile uint32_t*)CPG_PLL3CR) = DDR_CLK<<24 ; + PLL3_MODE=1; + dsb_sev(); + do { + dataL=*((volatile uint32_t*)CPG_PLLECR); + } while( (dataL&0x1f00)!=0x1f00 ); + while (1){ + dataL=InitDDR_start(DDR_CLK); + if(dataL==DDR_PHYVALID)break; + if(dataL==0xFF){ + InitResetCount++; + } else if(dataL==0xFE){ + PadCalFailCount++; + } else { + TrainingFailCount++; + } + if((InitResetCount+PadCalFailCount)==0x0f || TrainingFailCount==0x0f){ + NOTICE("Training Fail"); + break; + } + *((volatile uint32_t*)CPG_CPGWPR) = ~(0x001f001f); + *((volatile uint32_t*)CPG_PLLECR) = 0x001f001f ; + PLL3_MODE=1; + dsb_sev(); + do { + dataL=*((volatile uint32_t*)CPG_PLLECR); + } while( (dataL&0x1f00)!=0x1f00 ); + SoftDelay_ddr(1000); + ResetDram(); + ResetDram(); + dsb_sev(); + }; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/M3/boot_init_dram_m3_es10.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/M3/boot_init_dram_m3_es10.h new file mode 100644 index 0000000..7cc18cc --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/M3/boot_init_dram_m3_es10.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BOOT_INIT_DRAM_M3_ES10_ +#define __BOOT_INIT_DRAM_M3_ES10_ + +extern void InitDram_m3_es10(void); + +#endif /* __BOOT_INIT_DRAM_M3_ES10_*/ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/M3/init_dram_tbl_m3_es10.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/M3/init_dram_tbl_m3_es10.h new file mode 100644 index 0000000..77d1beb --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/M3/init_dram_tbl_m3_es10.h @@ -0,0 +1,433 @@ +/**********************************************************/ +/* Sample program : DRAM initialization Header */ +/* File Name : init_dram_tbl.h */ +/* Copyright (C) Renesas Electronics Corp. 2016. */ +/**********************************************************/ + +#ifndef __INIT_DRAM_TBL_M3_ES10_ +#define __INIT_DRAM_TBL_M3_ES10_ + +static const uint32_t DDR_PHY_SLICE_REGSET[128][2] = +{ + { 0x0800 , 0x76543210 } , + { 0x0801 , 0x0004F008 } , + { 0x0802 , 0x00000000 } , + { 0x0803 , 0x00000000 } , + { 0x0804 , 0x00000000| ((0x01)<<16) | ((0)<<8)} , + { 0x0805 , 0x00000000 | ((0x01) << 24) | (0x006E6E0E)} , + { 0x0806 , 0x02000000 | (0x006E6E0E) } , + { 0x0807 , 0x00010F00 } , + { 0x0808 , (0x04000100) } , + { 0x0809 , (0x00000300) } , + { 0x080A , 0x001700C0 } , + { 0x080B , 0x00CC0201 } , + { 0x080C , 0x00000066|(0) } , + { 0x080E , 0x00000001 } , + { 0x080F , 0x00000000 } , + { 0x0810 , 0x00000000 } , + { 0x0811 , 0x00000000 } , + { 0x0812 , 0x00000000 } , + { 0x0813 , 0x00000000 } , + { 0x0814 , 0x09000000 } , + { 0x0815 , 0x04080000 } , + { 0x0817 , 0x00000000 } , + { 0x0818 , 0x32103210 } , + { 0x0819 , 0x00C00708 } , + { 0x081A , 0x0001000C } , + { 0x081B , 0x00000100 } , + { 0x081C , 0x55555555 } , + { 0x081D , 0xAAAAAAAA } , + { 0x081E , 0x55555555 } , + { 0x081F , 0xAAAAAAAA } , + { 0x0820 , 0x00015555 } , + { 0x0830 , 0x00000000 } , + { 0x0833 , 0x00200000 } , + { 0x0834 , 0x08200820 } , + { 0x0835 , 0x08200820 } , + { 0x0836 , 0x08200820 } , + { 0x0837 , 0x08200820 } , + { 0x0838 , 0x08200820 } , + { 0x0839 , 0x00000820 } , + { 0x083A , 0x03000300 } , + { 0x083B , 0x03000300 } , + { 0x083C , 0x03000300 } , + { 0x083D , 0x03000300 } , + { 0x083E , 0x00000300 } , + { 0x083F , 0x00000000 } , + { 0x0840 , 0x00000000 } , + { 0x0841 , 0x00000000 } , + { 0x0842 , 0x00000000 } , + { 0x0843 , 0x00A00000 } , + { 0x0844 , 0x00A000A0 } , + { 0x0845 , 0x00A000A0 } , + { 0x0846 , 0x00A000A0 } , + { 0x0847 , 0x00A000A0 } , + { 0x0848 , 0x00A000A0 } , + { 0x0849 , 0x00A000A0 } , + { 0x084A , 0x00A000A0 } , + { 0x084B , 0x00A000A0 } , + { 0x084C , 0x010900A0 } , + { 0x084D , 0x01D00004 } , + { 0x084E , 0x00000000 } , + { 0x084F , 0x00010000 } , + { 0x0850 , 0x00000200 } , + { 0x0851 , (0x4141A141) } , + { 0x0852 , (0xC00141A0) } , + { 0x0853 , (0x0E0100C0) } , + { 0x0854 , (0x0010000C) } , + { 0x0855 , 0x0C064208 } , + { 0x0856 , 0x000F0C18 } , + { 0x0857 , 0x01000140 } , + { 0x0858 , 0x00000C20 } , + { 0xFFFFFFFF , 0xFFFFFFFF } +}; +static const uint32_t DDR_PHY_ADR_V_REGSET[128][2] = +{ + { 0x0A00 , 0x00000000 } , + { 0x0A01 , 0x00000000 } , + { 0x0A02 , 0x00000000 } , + { 0x0A04 , 0x00000000 } , + { 0x0A05 , 0x00000000 } , + { 0x0A06 , 0x00000002 } , + { 0x0A07 , 0x00000000 } , + { 0x0A0A , 0x00400320 } , + { 0x0A0B , 0x00000040 } , + { 0x0A0C , 0x00DCBA98 } , + { 0x0A0D , 0x00000000 } , + { 0x0A0E , 0x00DCBA98 } , + { 0x0A0F , 0x00000000 | ((1)<<24) } , + { 0x0A10 , 0x00000000 | ((2)<<16) | ((3)<<0) } , + { 0x0A11 , 0x00000000 } , + { 0x0A14 , 0x0000002A } , + { 0x0A15 , 0x00000015 } , + { 0x0A16 , 0x00000015 } , + { 0x0A17 , 0x0000002A } , + { 0x0A18 , 0x00000033 } , + { 0x0A19 , 0x0000000C } , + { 0x0A1A , 0x0000000C } , + { 0x0A1B , 0x00000033 } , + { 0x0A1C , 0x0A418820 } , + { 0x0A1D , 0x003F0000 } , + { 0x0A1E , 0x0000003F } , + { 0x0A1F , 0x0000006E|((0x2c0)<<8) } , + { 0x0A20 , 0x00000000|((0x2c0)<<16)|((0x2c0)<<0) } , + { 0x0A21 , 0x00000000|((0x2c0)<<16)|((0x2c0)<<0) } , + { 0x0A22 , 0x00000000|((0x2c0)<<0) } , + { 0x0A23 , 0x42080010 } , + { 0x0A24 , 0x00000003 } , + { 0xFFFFFFFF , 0xFFFFFFFF } +}; +static const uint32_t DDR_PHY_ADR_I_REGSET[128][2] = +{ + { 0x0A80 , 0x04040404 } , + { 0x0A81 , 0x00000404 } , + { 0x0A82 , 0x00000000 } , + { 0x0A84 , 0x00000000 } , + { 0x0A85 , 0x00000000 } , + { 0x0A86 , 0x00000002 } , + { 0x0A87 , 0x00000000 } , + { 0x0A8A , 0x00400320 } , + { 0x0A8B , 0x00000040 } , + { 0x0A8C , 0x00000000 } , + { 0x0A8D , 0x00000000 } , + { 0x0A8E , 0x00000000 } , + { 0x0A8F , 0x00000000 } , + { 0x0A90 , 0x00000000 } , + { 0x0A91 , 0x00000000 } , + { 0x0A94 , 0x0000002A } , + { 0x0A95 , 0x00000015 } , + { 0x0A96 , 0x00000015 } , + { 0x0A97 , 0x0000002A } , + { 0x0A98 , 0x00000033 } , + { 0x0A99 , 0x0000000C } , + { 0x0A9A , 0x0000000C } , + { 0x0A9B , 0x00000033 } , + { 0x0A9C , 0x00000000 } , + { 0x0A9D , 0x00000000 } , + { 0x0A9E , 0x00000000 } , + { 0x0A9F , 0x0000006E|((0x2c0)<<8) } , + { 0x0AA0 , 0x00000000|((0x2c0)<<16)|((0x2c0)<<0) } , + { 0x0AA1 , 0x00000000|((0x2c0)<<16)|((0x2c0)<<0) } , + { 0x0AA2 , 0x00000000|((0x2c0)<<0) } , + { 0x0AA3 , 0x42080010 } , + { 0x0AA4 , 0x00000003 } , + { 0xFFFFFFFF , 0xFFFFFFFF } +}; +static const uint32_t DDR_PHY_ADR_G_REGSET[128][2] = +{ + { 0x0B80 , 0x00000001 } , + { 0x0B81 , 0x00000000 } , + { 0x0B82 , 0x00000005 } , + { 0x0B83 , 0x04000F00 } , + { 0x0B84 , 0x00020040 } , + { 0x0B85 , 0x00020055 } , + { 0x0B86 , 0x00000000 } , + { 0x0B89 , 0x00000050 } , + { 0x0B8A , 0x00000000 } , + { 0x0B8B , 0x01010100 } , + { 0x0B8C , 0x00000600 } , + { 0x0B8D , 0x50640000 } , + { 0x0B8E , 0x01421142 } , + { 0x0B8F , 0x00000142 } , + { 0x0B90 , 0x00000000 } , + { 0x0B91 , ((0x00000F19)<<8) | 0x0 } , + { 0x0B92 , ((0x00000F19)<<16)|(0x00000F19) } , + { 0x0B93 , ((0x00000F19)<<16)|(0x00000F19) } , + { 0x0B94 , 0x00000003 } , + { 0x0B95 , 0x00000000|((0x2c0)<<8) } , + { 0x0B96 , 0x00000000|((0x2c0)<<16)|((0x2c0)<<0) } , + { 0x0B97 , 0x00000000|((0x2c0)<<0) } , + { 0x0B98 , 0x00001000|((0x00000B42)<<16) | ((0x00000B42)<<0) } , + { 0x0B99 , 0x00000000|((0x00000B42)<<0) } , + { 0x0B9C , 0x05020000 } , + { 0x0B9D , 0x00000000|(0) } , + { 0x0B9E , 0x00007F6E|((((0x9F)>>0)&0x1)<<17) } , + { 0x0B9F , 0x007F007F|((((0x9F)>>2)&0x1)<<26) | ((((0x9F)>>1)&0x1)<<9) } , + { 0x0BA0 , 0x00007F6E|((((0x9F)>>3)&0x1)<<17) } , + { 0x0BA1 , 0x00007F6E|((((0x9F)>>4)&0x1)<<18) } , + { 0x0BA2 , (0x0001554F) | 0x00020000 } , + { 0x0BA3 , (0x0001554F) } , + { 0x0BA4 , (0x0001554F) } , + { 0x0BA5 , (0x0001554F) } , + { 0x0BA6 , (0x0001554F) } , + { 0x0BA7 , 0x00003FEE | ((((0x9F)>>5)&0x1)<<17) } , + { 0x0BA8 , (0x0001554F) } , + { 0x0BA9 , 0x00003FEE | ((((0x9F)>>6)&0x1)<<17) } , + { 0x0BAA , (0x0001554F) } , + { 0x0BAB , 0x00007F6E | ((((0x9F)>>7)&0x1)<<17) } , + { 0x0BAC , (0x0001554F) } , + { 0x0BAD , 0x00000000 } , + { 0x0BAE , 0x00000000 } , + { 0x0BAF , 0x00000000 } , + { 0x0BB0 , 0x75000000 } , + { 0x0BB1 , 0x00000000 } , + { 0x0BB2 , 0x00000000 } , + { 0x0BB3 , 0x0000061F } , + { 0x0BB6 , 0x00000000 } , + { 0x0BB7 , 0x00000000 } , + { 0x0BB8 , 0x00000000 } , + { 0x0BB9 , 0x00000000 } , + { 0x0BBB , 0x00000000 } , + { 0x0BBC , 0x06E40000 } , + { 0x0BBD , 0x00000000 } , + { 0x0BBE , 0x00000000 } , + { 0x0BBF , 0x00020000 } , + { 0xFFFFFFFF , 0xFFFFFFFF } +}; +static const uint32_t DDR_PI_REGSET[255 +1][2] = +{ + { 0x0200 , 0x00000B00 } , + { 0x0201 , 0x00000100 } , + { 0x0202 , 0x00000000 } , + { 0x0203 , 0x0000ffff } , + { 0x0204 , 0x00000000 } , + { 0x0205 , 0x0000ffff } , + { 0x0206 , 0x00000000 } , + { 0x0207 , 0x008Cffff } , + { 0x0208 , 0x00000200 } , + { 0x0209 , 0x00000200 } , + { 0x020A , 0x00000200 } , + { 0x020B , 0x00000200 } , + { 0x020C , 0x0000304C } , + { 0x020D , 0x00000200 } , + { 0x020E , 0x00000200 } , + { 0x020F , 0x00000200 } , + { 0x0210 , 0x00000200 } , + { 0x0211 , 0x0000304C } , + { 0x0212 , 0x00000200 } , + { 0x0213 , 0x00000200 } , + { 0x0214 , 0x00000200 } , + { 0x0215 , 0x00000200 } , + { 0x0216 , 0x00010000 } , + { 0x0217 , 0x00000003 } , + { 0x0218 , 0x01000001 } , + { 0x0219 , 0x00000000 } , + { 0x021A , 0x00000000 } , + { 0x021B , 0x00000000 } , + { 0x021C , 0x00000000 } , + { 0x021D , 0x00000000 } , + { 0x021E , 0x00000000 } , + { 0x021F , 0x00000000 } , + { 0x0220 , 0x00000000 } , + { 0x0221 , 0x00000000 } , + { 0x0222 , 0x00000000 } , + { 0x0223 , 0x00000000 } , + { 0x0224 , 0x00000000 } , + { 0x0225 , 0x00000000 } , + { 0x0226 , 0x00000000 } , + { 0x0227 , 0x00000000 } , + { 0x0228 , 0x00000000 } , + { 0x0229 , 0x00000101|(((0xF & 0x0f) << 24)) } , + { 0x022A , 0x08492D25 } , + { 0x022B , 0x00000000|((0x0e)<<24)|(0x0C<<16)|(0x04<<0) } , + { 0x022C , 0x00000000|((0x0e)<<16)|(0x50<<8) } , + { 0x022D , 0x00000200|(0x50<<0) } , + { 0x022E , 0x00460003 } , + { 0x022F , 0x182600CF } , + { 0x0230 , 0x182600CF } , + { 0x0231 , 0x00000005 } , + { 0x0234 , 0x00000000 } , + { 0x0235 , 0x00000000 } , + { 0x0236 , 0x00000000 } , + { 0x0237 , 0x00000000 } , + { 0x0238 , 0x00000000 } , + { 0x0239 , 0x01000000 } , + { 0x023A , 0x00040404 } , + { 0x023B , 0x01280A00 } , + { 0x023C , 0x00000000 } , + { 0x023D , 0x00000000| ((0xF & 0x0f) << 16 ) } , + { 0x023E , 0x00001803 } , + { 0x023F , 0x00000000 } , + { 0x0240 , 0x00000000 } , + { 0x0241 , 0x00060002 } , + { 0x0242 , 0x00010001 } , + { 0x0243 , 0x01000101 } , + { 0x0244 , 0x04020201 } , + { 0x0245 , 0x00080804 } , + { 0x0246 , 0x00000000 } , + { 0x0247 , 0x08030000 } , + { 0x0248 , 0x15150408 } , + { 0x0249 , 0x00000000 } , + { 0x024A , 0x00000000 } , + { 0x024B , 0x00000000 } , + { 0x024C , 0x00000000|((0xF & 0x0f) << 16 ) | ((0xF & 0x0f) << 8 ) } , + { 0x024D , 0x0000001E } , + { 0x024E , 0x00000000 } , + { 0x024F , 0x01010300 } , + { 0x0250 , 0x00000000 } , + { 0x0251 , 0x00000000 } , + { 0x0252 , 0x01000000 } , + { 0x0253 , 0x00010101 } , + { 0x0254, ((0x0e)<<16)|((0x0e)<<8)|((0x0e)<<0)}, + { 0x0255, ((0x0c)<<16)|((0x0c)<<8)|((0x0c)<<0)}, + { 0x0256 , 0x02060601 } , + { 0x0257 , 0x00000000 } , + { 0x0258 , 0x00000003 } , + { 0x0259 , 0x00181700|((0x3 & 0x0f) << 0 ) } , + { 0x025A , 0x00280006 } , + { 0x025B , 0x00280016 } , + { 0x025C , 0x00000016 } , + { 0x025D , 0x00000000 } , + { 0x025E , 0x00000000 } , + { 0x025F , 0x00000000 } , + { 0x0260 , 0x140A0000 } , + { 0x0261 , 0x0005010A } , + { 0x0262 , 0x03018D03 } , + { 0x0263 , 0x010A018D } , + { 0x0264 , 0x00060100 } , + { 0x0265 , 0x01000006 } , + { 0x0266 , 0x018E018E } , + { 0x0267 , 0x018E018E } , + { 0x0268 , 0x1E1A018E } , + { 0x0269 , 0x10010204 } , + { 0x026A , 0x09090650 } , + { 0x026B , 0x20000202 } , + { 0x026C , 0x00201000 } , + { 0x026D , 0x00201000 } , + { 0x026E , 0x04041000 } , + { 0x026F , 0x18020100 } , + { 0x0270 , 0x00010018 } , + { 0x0271 , 0x004B004A } , + { 0x0272 , 0x00000000|(((0x11))<<24)|((0xF & 0x0f) << 16 ) } , + { 0x0273 , 0x01020200|(((0x11))<<0) } , + { 0x0274 , 0x34000000 } , + { 0x0275 , 0x00000000 } , + { 0x0276 , 0x00000000 } , + { 0x0277 , 0x00010000 } , + { 0x0278 , (0xd4<<8) } , + { 0x0279 , (0x31<<16)|(0x2e<<0) } , + { 0x027A , (((0x11))<<16)|(((0x11))<<8)|(((0x36))<<0) } , + { 0x027B , (0x2e<<16)|(0xd4<<0) } , + { 0x027C , (((0x11))<<24)|(((0x36))<<16)|(0x31<<0) } , + { 0x027D , (0xd4<<8)|(((0x11))<<0) } , + { 0x027E , (0x31<<16)|(0x2e<<0) } , + { 0x027F , (((0x11))<<16)|(((0x11))<<8)|(((0x36))<<0) } , + { 0x0280 , (0x2e<<16)|(0xd4<<0) } , + { 0x0281 , (((0x11))<<24)|(((0x36))<<16)|(0x31<<0) } , + { 0x0282 , (0xd4<<8)|(((0x11))<<0) } , + { 0x0283 , (0x31<<16)|(0x2e<<0) } , + { 0x0284 , (((0x11))<<16)|(((0x11))<<8)|(((0x36))<<0) } , + { 0x0285 , (0x2e<<16)|(0xd4<<0) } , + { 0x0286 , (((0x11))<<24)|(((0x36))<<16)|(0x31<<0) } , + { 0x0287 , (0xd4<<16)|(((0x11))<<0) } , + { 0x0288 , (0x31<<16)|(0x2e<<0) } , + { 0x0289 , (((0x11))<<16)|(((0x11))<<8)|(((0x36))<<0) } , + { 0x028A , (0x2e<<16)|(0xd4<<0) } , + { 0x028B , (((0x11))<<24)|(((0x36))<<16)|(0x31<<0) } , + { 0x028C , (0xd4<<8)|(((0x11))<<0) } , + { 0x028D , (0x31<<16)|(0x2e<<0) } , + { 0x028E , (((0x11))<<16)|(((0x11))<<8)|(((0x36))<<0) } , + { 0x028F , (0x2e<<16)|(0xd4<<0) } , + { 0x0290 , (((0x11))<<24)|(((0x36))<<16)|(0x31<<0) } , + { 0x0291 , (0xd4<<8)|(((0x11))<<0) } , + { 0x0292 , (0x31<<16)|(0x2e<<0) } , + { 0x0293 , (((0x11))<<16)|(((0x11))<<8)|(((0x36))<<0) } , + { 0x0294 , (0x2e<<16)|(0xd4<<8) } , + { 0x0295 , (((0x11))<<24)|(((0x36))<<16)|(0x31<<0) } , + { 0x0296 , 0x02000000|(((0x11))<<0) } , + { 0x0297 , (0x018D<<16)|(0x018D<<0) } , + { 0x0298 , 0x00080100|(0x0c<<24)|(0x018D<<0) } , + { 0x0299 , 0x040A0404 } , + { 0x029A , 0x0300057C } , + { 0x029B , 0x010A2001 } , + { 0x029C , 0x1D22000A|(0x0c<<8) } , + { 0x029D , 0x00001F12 } , + { 0x029E , 0x4301B344 } , + { 0x029F , 0x10172006 } , + { 0x02A0 , 0x1D220010|(0x0c<<8) } , + { 0x02A1 , 0x00001F12 } , + { 0x02A2 , 0x4301B344 } , + { 0x02A3 , 0x10172006 } , + { 0x02A4 , 0x02000210 } , + { 0x02A5 , 0x02000200 } , + { 0x02A6 , 0x02000200 } , + { 0x02A7 , 0x02000200 } , + { 0x02A8 , 0x02000200 } , + { 0x02A9 , 0x00000000 } , + { 0x02AA , 0x00000000 } , + { 0x02AB , 0x00000000 } , + { 0x02B5 , 0x00000400 } , + { 0x02B6 , 0x15141312 } , + { 0x02B7 , 0x11100F0E } , + { 0x02B8 , 0x080B0C0D } , + { 0x02B9 , 0x05040A09 } , + { 0x02BA , 0x01000706 } , + { 0x02BB , 0x00000302 } , + { 0x02BC , 0x01030201 } , + { 0x02BD , 0x00008C00 } , + { 0x02BE , 0x00000578 } , + { 0x02BF , 0x0000304C } , + { 0x02C0 , 0x0001E2F8 } , + { 0x02C1 , 0x0000304C } , + { 0x02C2 , 0x0001E2F8 } , + { 0x02C3 , 0x08000000 } , + { 0x02C4 , 0x00000100 } , + { 0x02C5 , 0x00000000 } , + { 0x02C6 , 0x00000000 } , + { 0x02C7 , 0x00000000 } , + { 0x02C8 , 0x00000000 } , + { 0x02C9 , 0x00000002 } , + { 0xFFFFFFFF , 0xFFFFFFFF } +}; +static const uint32_t DDR_BOARD_SWAP[BOARDNUM][DRAM_CH_CNT][0 +1][2] = { +{ +{ + { 0xFFFFFFFF , 0xFFFFFFFF } +} +, +{ + { 0xFFFFFFFF , 0xFFFFFFFF } +} +} +, +{ +{ + { 0xFFFFFFFF , 0xFFFFFFFF } +}, +{ + { 0xFFFFFFFF , 0xFFFFFFFF } +} +} +}; + +#endif /* __INIT_DRAM_TBL_M3_ES10_*/ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/boot_init_dram.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/boot_init_dram.c new file mode 100644 index 0000000..a29c28b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/boot_init_dram.c @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "boot_init_dram.h" +#if RCAR_LSI == RCAR_H3 /* H3 */ + #include "H3/ES10/boot_init_dram_h3_es10.h" + #include "H3/WS11/boot_init_dram_h3_ws11.h" +#endif +#if RCAR_LSI == RCAR_M3 /* M3 */ + #include "M3/boot_init_dram_m3_es10.h" +#endif + + /* Product Register */ +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) +#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */ +#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ +#define PRR_PRODUCT_10 (0x00U) +#define PRR_PRODUCT_11 (0x01U) + +#define PRR_PRODUCT_ERR(reg) do{\ + ERROR("LSI Product ID(PRR=0x%x) DDR "\ + "initialize not supported.\n",reg);\ + panic();\ + }while(0) +#define PRR_CUT_ERR(reg) do{\ + ERROR("LSI Cut ID(PRR=0x%x) DDR "\ + "initialize not supported.\n",reg);\ + panic();\ + }while(0) + +void InitDram(void) +{ + uint32_t reg; + + reg = mmio_read_32(PRR); +#if RCAR_LSI_CUT_COMPAT + switch (reg & PRR_PRODUCT_MASK) { + case PRR_PRODUCT_H3: +#if RCAR_LSI != RCAR_H3 + PRR_PRODUCT_ERR(reg); +#else + switch (reg & PRR_CUT_MASK) { + case PRR_PRODUCT_10: + InitDram_h3_es10(); + break; + case PRR_PRODUCT_11: + InitDram_h3_ws11(); + break; + default: + PRR_CUT_ERR(reg); + break; + } +#endif + break; + case PRR_PRODUCT_M3: +#if RCAR_LSI != RCAR_M3 + PRR_PRODUCT_ERR(reg); +#else + InitDram_m3_es10(); +#endif + break; + default: + PRR_PRODUCT_ERR(reg); + break; + } +#else + #if RCAR_LSI == RCAR_H3 /* H3 */ + #if RCAR_LSI_CUT == RCAR_CUT_10 + /* H3 Cut 10 */ + if ((PRR_PRODUCT_H3 | PRR_PRODUCT_10) + != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { + PRR_PRODUCT_ERR(reg); + } + InitDram_h3_es10(); + #elif RCAR_LSI_CUT == RCAR_CUT_11 + /* H3 Cut 11 */ + if ((PRR_PRODUCT_H3 | PRR_PRODUCT_11) + != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { + PRR_PRODUCT_ERR(reg); + } + InitDram_h3_ws11(); + #else + #error "Don't have DDR initialize routine(H3)." + #endif + #elif RCAR_LSI == RCAR_M3 /* M3 */ + if ((PRR_PRODUCT_M3 | PRR_PRODUCT_10) + != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { + PRR_PRODUCT_ERR(reg); + } + InitDram_m3_es10(); + #else + #error "Don't have DDR initialize routine(M3)." + #endif +#endif +} + + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/boot_init_dram.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/boot_init_dram.h new file mode 100644 index 0000000..c631ec1 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/boot_init_dram.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BOOT_INIT_DRAM_H_ +#define __BOOT_INIT_DRAM_H_ + +extern void InitDram(void); + +#endif /* __BOOT_INIT_DRAM_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/ddr.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/ddr.mk new file mode 100644 index 0000000..b3e1c4a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/ddr/ddr.mk @@ -0,0 +1,55 @@ +# +# Copyright (c) 2015-2016, Renesas Electronics Corporation +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# - Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# - Neither the name of Renesas nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +ifdef RCAR_LSI_CUT_COMPAT + ifeq (${RCAR_LSI},${RCAR_H3}) + BL2_SOURCES += plat/renesas/rcar/ddr/H3/ES10/boot_init_dram_h3_es10.c + BL2_SOURCES += plat/renesas/rcar/ddr/H3/WS11/boot_init_dram_h3_ws11.c + endif + ifeq (${RCAR_LSI},${RCAR_M3}) + $(error "Error: ${LSI} is not supported.") + endif +else + ifeq (${RCAR_LSI},${RCAR_H3}) + ifeq (${LSI_CUT},10) + BL2_SOURCES += plat/renesas/rcar/ddr/H3/ES10/boot_init_dram_h3_es10.c + endif + ifeq (${LSI_CUT},11) + BL2_SOURCES += plat/renesas/rcar/ddr/H3/WS11/boot_init_dram_h3_ws11.c + endif + endif + ifeq (${RCAR_LSI},${RCAR_M3}) + BL2_SOURCES += plat/renesas/rcar/ddr/M3/boot_init_dram_m3_es10.c + endif +endif + + +BL2_SOURCES += plat/renesas/rcar/ddr/boot_init_dram.c diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/auth/rcarboot.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/auth/rcarboot.c new file mode 100644 index 0000000..170eeae --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/auth/rcarboot.c @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include +#include +#include +#include + +#include "rcarboot.h" + +#define RCAR_BOOT_KEY_CERT (0xE6300C00U) +#if RCAR_LSI == RCAR_H3 +#define RCAR_SBROM_API (0xeb10dd64U) +#elif RCAR_LSI == RCAR_M3 +#define RCAR_SBROM_API (0xeb1102fcU) +#endif +#define RST_BASE (0xE6160000U) +#define RST_MODEMR (RST_BASE + 0x0060U) +#define LIFEC_CC_LCS (0xE6110028U) /* cc_lcs Life cycle state read */ +#define MFISSOFTMDR (0xE6260600U) /* SOFTMD register */ + +static SECURE_BOOT_API sbrom_SecureBootAPI; + +#if !RCAR_SECURE_BOOT +static int32_t local_verify(uint32_t a, uint32_t b, void *c); +#endif + +/* + * Return the parent id in the output parameter '*parent_id' + * + * Return value: + * 0 = Image has parent, 1 = Image has no parent or parent is authenticated + */ +int auth_mod_get_parent_id(unsigned int img_id, unsigned int *parent_id) +{ + return 1; +} + +/* + * Authenticate a certificate/image + * + * Return: 0 = success, Otherwise = error + */ +int auth_mod_verify_img(unsigned int img_id, void *img_ptr, + unsigned int img_len) +{ + int32_t ret = 0; + uint32_t cert_addr; + + switch (img_id) { +#if IMAGE_BL2 + case (uint32_t)TRUSTED_KEY_CERT_ID: + case (uint32_t)BL31_KEY_CERT_ID: + case (uint32_t)BL32_KEY_CERT_ID: + case (uint32_t)BL33_KEY_CERT_ID: + case (uint32_t)BL332_KEY_CERT_ID: + case (uint32_t)BL333_KEY_CERT_ID: + case (uint32_t)BL334_KEY_CERT_ID: + case (uint32_t)BL335_KEY_CERT_ID: + case (uint32_t)BL336_KEY_CERT_ID: + case (uint32_t)BL337_KEY_CERT_ID: + case (uint32_t)BL338_KEY_CERT_ID: + case (uint32_t)BL31_CERT_ID: + case (uint32_t)BL32_CERT_ID: + case (uint32_t)BL33_CERT_ID: + case (uint32_t)BL332_CERT_ID: + case (uint32_t)BL333_CERT_ID: + case (uint32_t)BL334_CERT_ID: + case (uint32_t)BL335_CERT_ID: + case (uint32_t)BL336_CERT_ID: + case (uint32_t)BL337_CERT_ID: + case (uint32_t)BL338_CERT_ID: + /* no check */ + break; + case (uint32_t)BL31_IMAGE_ID: + ret = file_to_cert(BL31_CERT_ID, &cert_addr); + if (0 == ret) { + ret = sbrom_SecureBootAPI(RCAR_BOOT_KEY_CERT, cert_addr, NULL); + if (0 != ret) { + ERROR("Verification Failed!!! 0x%x -> BL31\n", ret); + } + } + break; + case (uint32_t)BL32_IMAGE_ID: + ret = file_to_cert(BL32_CERT_ID, &cert_addr); + if (0 == ret) { + ret = sbrom_SecureBootAPI(RCAR_BOOT_KEY_CERT, cert_addr, NULL); + if (0 != ret) { + ERROR("Verification Failed!!! 0x%x -> BL32\n", ret); + } + } + break; + case (uint32_t)BL33_IMAGE_ID: + ret = file_to_cert(BL33_CERT_ID, &cert_addr); + if (0 == ret) { + ret = sbrom_SecureBootAPI(RCAR_BOOT_KEY_CERT, cert_addr, NULL); + if (0 != ret) { + ERROR("Verification Failed!!! 0x%x -> BL33\n", ret); + } + } + break; + case (uint32_t)BL332_IMAGE_ID: + ret = file_to_cert(BL332_CERT_ID, &cert_addr); + if (0 == ret) { + ret = sbrom_SecureBootAPI(RCAR_BOOT_KEY_CERT, cert_addr, NULL); + if (0 != ret) { + ERROR("Verification Failed!!! 0x%x -> BL332\n", ret); + } + } + break; + case (uint32_t)BL333_IMAGE_ID: + ret = file_to_cert(BL333_CERT_ID, &cert_addr); + if (0 == ret) { + ret = sbrom_SecureBootAPI(RCAR_BOOT_KEY_CERT, cert_addr, NULL); + if (0 != ret) { + ERROR("Verification Failed!!! 0x%x -> BL333\n", ret); + } + } + break; + case (uint32_t)BL334_IMAGE_ID: + ret = file_to_cert(BL334_CERT_ID, &cert_addr); + if (0 == ret) { + ret = sbrom_SecureBootAPI(RCAR_BOOT_KEY_CERT, cert_addr, NULL); + if (0 != ret) { + ERROR("Verification Failed!!! 0x%x -> BL334\n", ret); + } + } + break; + case (uint32_t)BL335_IMAGE_ID: + ret = file_to_cert(BL335_CERT_ID, &cert_addr); + if (0 == ret) { + ret = sbrom_SecureBootAPI(RCAR_BOOT_KEY_CERT, cert_addr, NULL); + if (0 != ret) { + ERROR("Verification Failed!!! 0x%x -> BL335\n", ret); + } + } + break; + case (uint32_t)BL336_IMAGE_ID: + ret = file_to_cert(BL336_CERT_ID, &cert_addr); + if (0 == ret) { + ret = sbrom_SecureBootAPI(RCAR_BOOT_KEY_CERT, cert_addr, NULL); + if (0 != ret) { + ERROR("Verification Failed!!! 0x%x -> BL336\n", ret); + } + } + break; + case (uint32_t)BL337_IMAGE_ID: + ret = file_to_cert(BL337_CERT_ID, &cert_addr); + if (0 == ret) { + ret = sbrom_SecureBootAPI(RCAR_BOOT_KEY_CERT, cert_addr, NULL); + if (0 != ret) { + ERROR("Verification Failed!!! 0x%x -> BL337\n", ret); + } + } + break; + case (uint32_t)BL338_IMAGE_ID: + ret = file_to_cert(BL338_CERT_ID, &cert_addr); + if (0 == ret) { + ret = sbrom_SecureBootAPI(RCAR_BOOT_KEY_CERT, cert_addr, NULL); + if (0 != ret) { + ERROR("Verification Failed!!! 0x%x -> BL338\n", ret); + } + } + break; +#endif /* IMAGE_BL2 */ + default: + ret = -1; + break; + } + + return ret; +} + +static int32_t local_verify(uint32_t a, uint32_t b, void *c) +{ + return 0; +} + +/* + * Initialize the different modules in the authentication framework + */ +void auth_mod_init(void) +{ +#if RCAR_SECURE_BOOT + uint32_t lcs = (mmio_read_32(LIFEC_CC_LCS) & 0x000000F0U) >> 4; + uint32_t md = (mmio_read_32(RST_MODEMR) & 0x00000020U) >> 5; + uint32_t softmd = (mmio_read_32(MFISSOFTMDR) & 0x00000001U); + + /* default is Secure boot */ + sbrom_SecureBootAPI = (SECURE_BOOT_API)RCAR_SBROM_API; + + if (lcs == 0x5U) { /* LCS=Secure */ + if (softmd == 0x1U) { + sbrom_SecureBootAPI = &local_verify; /* LCS=Secure + Normal boot (temp setting) */ + } /* else is LCS=Secure + Secure boot */ + } else if (md != 0U) { + sbrom_SecureBootAPI = &local_verify; /* MD5=1 => LCS=CM/DM + Normal boot */ + } /* else is MD5=0 => LCS=CM/DM + Secure boot */ + + if (sbrom_SecureBootAPI == &local_verify) { + NOTICE("BL2: Normal boot\n"); + } else { + NOTICE("BL2: Secure boot\n"); + } +#else + sbrom_SecureBootAPI = &local_verify; + NOTICE("BL2: Normal boot\n"); +#endif +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/auth/rcarboot.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/auth/rcarboot.h new file mode 100644 index 0000000..2d015ca --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/auth/rcarboot.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_RCARBOOT_H_ +#define RCAR_RCARBOOT_H_ + +/* Define */ +typedef int32_t (*SECURE_BOOT_API)(uint32_t a, uint32_t b, void *c); + +/* Prototype */ +extern int32_t file_to_cert(const int32_t filename, uint32_t *cert_addr); + +#endif /* RCAR_RCARBOOT_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/avs/avs_driver.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/avs/avs_driver.c new file mode 100644 index 0000000..415d670 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/avs/avs_driver.c @@ -0,0 +1,654 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "bl2_cpg_init.h" +#include "bl2_cpg_register.h" +#include "avs_driver.h" + +#if AVS_SETTING_ENABLE == 1 +/* Read PMIC register for debug. 1:enable / 0:disable */ +#define AVS_READ_PMIC_REG_ENABLE 0 +/* The re-try number of times of the AVS setting. */ +#define AVS_RETRY_NUM (1U) + +/* Base address of ADVFS Module registers*/ +#define ADVFS_BASE (0xE60A0000U) +/* Register address in eFuse indicates individual R-Car information */ +#define ADVFS_KSEN_ADJCNTS (ADVFS_BASE + 0x013CU) + +/* Mask VOLCOND bit in KSEN_ADJCNTS registers */ +#define KSEN_ADJCNTS_VOLCOND_MASK (0x0000000FU) +#define VOLCOND_INVALID_VAL (0x7U) /* Invalid value */ +#define VOLCOND_CANCEL_BIT (0x8U) /* Cancel bit */ + +/* Mode Monitor Register */ +#define RCAR_MODEMR (0xE6160060U) /* Mode pin register */ +#define MODEMR_MD13 (0x2000U) /* MD13 bit mask */ +#define MODEMR_MD14 (0x4000U) /* MD14 bit mask */ +/* CP Phy input frequency */ +#define CP_PHY_FREQ_8p33M (0x0000U) /* 8.3333MHz */ +#define CP_PHY_FREQ_10M (0x2000U) /* 10MHz */ +#define CP_PHY_FREQ_12p5M (0x4000U) /* 12.5MHz */ +#define CP_PHY_FREQ_16p66M (0x6000U) /* 16.6666MHz */ + +/* I2C for DVFS bit in CPG registers for module standby and software reset*/ +#define CPG_SYS_DVFS_BIT (0x04000000U) +/* ADVFS Module bit in CPG registers for module standby and software reset*/ +#define CPG_SYS_ADVFS_BIT (0x02000000U) + +/* Base address of IICDVFS registers*/ +#define IIC_DVFS_BASE (0xE60B0000U) +/* IIC bus data register */ +#define IIC_ICDR (IIC_DVFS_BASE + 0x0000U) +/* IIC bus control register */ +#define IIC_ICCR (IIC_DVFS_BASE + 0x0004U) +/* IIC bus status register */ +#define IIC_ICSR (IIC_DVFS_BASE + 0x0008U) +/* IIC interrupt control register */ +#define IIC_ICIC (IIC_DVFS_BASE + 0x000CU) +/* IIC clock control register low */ +#define IIC_ICCL (IIC_DVFS_BASE + 0x0010U) +/* IIC clock control register high */ +#define IIC_ICCH (IIC_DVFS_BASE + 0x0014U) + +/* Bit in ICSR register */ +#define ICSR_BUSY (0x10U) +#define ICSR_AL (0x08U) +#define ICSR_TACK (0x04U) +#define ICSR_WAIT (0x02U) +#define ICSR_DTE (0x01U) + +/* Bit in ICIC register */ +#define ICIC_TACKE (0x04U) +#define ICIC_WAITE (0x02U) +#define ICIC_DTEE (0x01U) + +/* I2C bus interface enable */ +#define ICCR_ENABLE (0x80U) +/* Start condition */ +#define ICCR_START (0x94U) +/* Stop condition */ +#define ICCR_STOP (0x90U) +/* Restart condition with change to receive mode change */ +#define ICCR_START_RECV (0x81U) +/* Stop condition for receive mode */ +#define ICCR_STOP_RECV (0xC0U) + +/* Low-level period of SCL */ +#define ICCL_FREQ_8p33M (0x07U) /* for CP Phy 8.3333MHz */ +#define ICCL_FREQ_10M (0x09U) /* for CP Phy 10MHz */ +#define ICCL_FREQ_12p5M (0x0BU) /* for CP Phy 12.5MHz */ +#define ICCL_FREQ_16p66M (0x0EU) /* for CP Phy 16.6666MHz */ +/* High-level period of SCL */ +#define ICCH_FREQ_8p33M (0x01U) /* for CP Phy 8.3333MHz */ +#define ICCH_FREQ_10M (0x02U) /* for CP Phy 10MHz */ +#define ICCH_FREQ_12p5M (0x03U) /* for CP Phy 12.5MHz */ +#define ICCH_FREQ_16p66M (0x05U) /* for CP Phy 16.6666MHz */ + +#define PMIC_W_SLAVE_ADDRESS (0x60U) /* PMIC slave address + (W) */ +#define PMIC_R_SLAVE_ADDRESS (0x61U) /* PMIC slave address + (R) */ +#define PMIC_DVFS_SETVID (0x54U) /* PMIC DVFS SetVID register */ + +/* Individual information */ +#define EFUSE_AVS0 (0U) +#define EFUSE_AVS_NUM (7U) +static const uint8_t pmic_setvid_reg[EFUSE_AVS_NUM] = { + 0x52U, /* AVS0 0.82V */ + 0x52U, /* AVS1 0.82V */ + 0x52U, /* AVS2 0.82V */ + 0x4FU, /* AVS3 0.79V */ + 0x4FU, /* AVS4 0.79V */ + 0x4DU, /* AVS5 0.77V */ + 0x4BU /* AVS6 0.75V */ +}; + +/* Kind of AVS settings status */ +typedef enum +{ + avs_status_none = 0, + avs_status_init, + avs_status_start_condition, + avs_status_set_slave_addr, + avs_status_write_reg_addr, + avs_status_write_reg_data, + avs_status_stop_condition, + avs_status_end, + avs_status_complete, + avs_status_al_start, + avs_status_al_transfer, + avs_status_nack, + avs_status_error_stop, + ave_status_error_end +} avs_status_t; + +/* Kind of AVS error */ +typedef enum +{ + avs_error_none = 0, + avs_error_al, + avs_error_nack +} avs_error_t; + +static avs_status_t avs_status = avs_status_none; +static uint32_t avs_retry = 0U; +static uint32_t efuse_avs = EFUSE_AVS0; + +/* prototype */ +static avs_error_t avs_check_error(void); +static void avs_set_iic_clock(void); +#if AVS_READ_PMIC_REG_ENABLE == 1 +static uint8_t avs_read_pmic_reg(uint8_t addr); +static void avs_poll(uint8_t bit_pos, uint8_t val); +#endif +#endif /* AVS_SETTING_ENABLE */ + +/* + * Initialize to enable the AVS setting. + */ +void bl2_avs_init(void) +{ +#if AVS_SETTING_ENABLE == 1 + uint32_t val; + uint32_t mstp; + + INFO("BL2: AVS setting start. \n"); + + /* Initialize AVS status */ + avs_status = avs_status_init; + + /* Bit of the module which wants to enable clock supply. */ + mstp = CPG_SYS_DVFS_BIT | CPG_SYS_ADVFS_BIT; + /* Enables the clock supply to the CPG. */ + cpg_write(CPG_SMSTPCR9, mmio_read_32(CPG_SMSTPCR9) & (~mstp)); + /* Is the clock supply to the CPG disabled ? */ + while((mmio_read_32(CPG_MSTPSR9) & mstp) != 0U) { + /* Enables the clock supply to the CPG. */ + cpg_write(CPG_SMSTPCR9, + mmio_read_32(CPG_SMSTPCR9) & (~mstp)); + } + + /* Disable I2C module and All internal registers initialized. */ + mmio_write_8(IIC_ICCR, 0x00U); + while ((mmio_read_8(IIC_ICCR) & ICCR_ENABLE) != 0U) { + /* Disable I2C module and All internal registers initialized. */ + mmio_write_8(IIC_ICCR, 0x00U); + } + + /* Read eFuse indicates individual R-Car information */ + val = mmio_read_32(ADVFS_KSEN_ADJCNTS) & KSEN_ADJCNTS_VOLCOND_MASK; + + if ((val == VOLCOND_INVALID_VAL) + || ((val & VOLCOND_CANCEL_BIT) == VOLCOND_CANCEL_BIT)) { + efuse_avs = EFUSE_AVS0; + } else { + efuse_avs = val; + } + + /* Set next status */ + avs_status = avs_status_start_condition; + + INFO("BL2: Read KSEN_ADJCNTS.VOLCOND=0x%x efuse_avs=%u\n", + val, efuse_avs); +#endif /* AVS_SETTING_ENABLE */ +} + +/* + * Set the value of register corresponding to the voltage + * by transfer of I2C to PIMC. + */ +void bl2_avs_setting(void) +{ +#if AVS_SETTING_ENABLE == 1 + avs_error_t err; + + INFO("BL2: bl2_avs_setting avs_status=%d\n", avs_status); + + switch (avs_status) { + case avs_status_start_condition: + /* Set ICCR.ICE=1 to activate the I2C module. */ + mmio_write_8(IIC_ICCR, mmio_read_8(IIC_ICCR) | ICCR_ENABLE); + /* Set frequency of 400kHz */ + avs_set_iic_clock(); + /* Set ICIC.TACKE=1, ICIC.WAITE=1, ICIC.DTEE=1 to */ + /* enable interrupt control. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) + | ICIC_TACKE | ICIC_WAITE | ICIC_DTEE); + /* Write H'94 in ICCR to issue start condition */ + mmio_write_8(IIC_ICCR, ICCR_START); + /* Set next status */ + avs_status = avs_status_set_slave_addr; + break; + case avs_status_set_slave_addr: + /* Check error. */ + err = avs_check_error(); + if (err == avs_error_al) { + /* Recovery sequence of just after start. */ + avs_status = avs_status_al_start; + } else if (err == avs_error_nack) { + /* Recovery sequence of detected NACK */ + avs_status = avs_status_nack; + } else { + /* Was data transmission enabled ? */ + if ((mmio_read_8(IIC_ICSR) & ICSR_DTE) == ICSR_DTE) { + /* Clear ICIC.DTEE to disable a DTE interrupt */ + mmio_write_8(IIC_ICIC, + mmio_read_8(IIC_ICIC) + & (uint8_t)(~ICIC_DTEE)); + /* Send PMIC slave address + (W) */ + mmio_write_8(IIC_ICDR, PMIC_W_SLAVE_ADDRESS); + /* Set next status */ + avs_status = avs_status_write_reg_addr; + } + } + break; + case avs_status_write_reg_addr: + /* Check error. */ + err = avs_check_error(); + if (err == avs_error_al) { + /* Recovery sequence of during data transfer. */ + avs_status = avs_status_al_transfer; + } else if (err == avs_error_nack) { + /* Recovery sequence of detected NACK */ + avs_status = avs_status_nack; + } else { + /* If wait state after data transmission. */ + if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) { + /* Write PMIC DVFS_SetVID address */ + mmio_write_8(IIC_ICDR, PMIC_DVFS_SETVID); + /* Clear ICSR.WAIT to exit from wait state. */ + mmio_write_8(IIC_ICSR, + mmio_read_8(IIC_ICSR) + & (uint8_t)(~ICSR_WAIT)); + /* Set next status */ + avs_status = avs_status_write_reg_data; + } + } + break; + case avs_status_write_reg_data: + /* Check error. */ + err = avs_check_error(); + if (err == avs_error_al) { + /* Recovery sequence of during data transfer. */ + avs_status = avs_status_al_transfer; + } else if (err == avs_error_nack) { + /* Recovery sequence of detected NACK */ + avs_status = avs_status_nack; + } else { + /* If wait state after data transmission. */ + if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) { + /* Dose efuse_avs exceed the number of */ + /* the tables? */ + if (efuse_avs >= EFUSE_AVS_NUM) { + ERROR("BL2: AVS number of eFuse is out " + "of a range. number=%u\n", + efuse_avs); + /* Infinite loop */ + panic(); + } + /* Write PMIC DVFS_SetVID value */ + mmio_write_8(IIC_ICDR, + pmic_setvid_reg[efuse_avs]); + /* Clear ICSR.WAIT to exit from wait state. */ + mmio_write_8(IIC_ICSR, + mmio_read_8(IIC_ICSR) + & (uint8_t)(~ICSR_WAIT)); + /* Set next status */ + avs_status = avs_status_stop_condition; + } + } + break; + case avs_status_stop_condition: + err = avs_check_error(); + if (err == avs_error_al) { + /* Recovery sequence of during data transfer. */ + avs_status = avs_status_al_transfer; + } else if (err == avs_error_nack) { + /* Recovery sequence of detected NACK */ + avs_status = avs_status_nack; + } else { + /* If wait state after data transmission. */ + if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) { + /* Write H'90 in ICCR to issue stop condition */ + mmio_write_8(IIC_ICCR, ICCR_STOP); + /* Clear ICSR.WAIT to exit from wait state. */ + mmio_write_8(IIC_ICSR, + mmio_read_8(IIC_ICSR) + & (uint8_t)(~ICSR_WAIT)); + /* Set next status */ + avs_status = avs_status_end; + } + } + break; + case avs_status_end: + /* Is this module not busy?. */ + if ((mmio_read_8(IIC_ICSR) & ICSR_BUSY) == 0U) { + /* Set ICCR=H'00 to disable the I2C module. */ + mmio_write_8(IIC_ICCR, 0x00U); + /* Set next status */ + avs_status = avs_status_complete; + } + break; + case avs_status_al_start: + /* Clear ICSR.AL bit */ + mmio_write_8(IIC_ICSR, + (mmio_read_8(IIC_ICSR) + & (uint8_t)(~ICSR_AL))); + /* Transmit a clock pulse */ + mmio_write_8(IIC_ICDR, pmic_setvid_reg[EFUSE_AVS0]); + /* Set next status */ + avs_status = avs_status_error_stop; + break; + case avs_status_al_transfer: + /* Clear ICSR.AL bit */ + mmio_write_8(IIC_ICSR, + (mmio_read_8(IIC_ICSR) + & (uint8_t)(~ICSR_AL))); + /* Set next status */ + avs_status = avs_status_error_stop; + break; + case avs_status_nack: + /* Write H'90 in ICCR to issue stop condition */ + mmio_write_8(IIC_ICCR, ICCR_STOP); + /* Disable a WAIT and DTEE interrupt. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) + & (uint8_t)(~(ICIC_WAITE | ICIC_DTEE))); + /* Clear ICSR.TACK bit */ + mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) + & (uint8_t)(~ICSR_TACK)); + /* Set next status */ + avs_status = ave_status_error_end; + break; + case avs_status_error_stop: + /* If wait state after data transmission. */ + if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) { + /* Write H'90 in ICCR to issue stop condition */ + mmio_write_8(IIC_ICCR, ICCR_STOP); + /* Clear ICSR.WAIT to exit from wait state. */ + mmio_write_8(IIC_ICSR, + mmio_read_8(IIC_ICSR) + & (uint8_t)(~ICSR_WAIT)); + /* Set next status */ + avs_status = ave_status_error_end; + } + break; + case ave_status_error_end: + /* Is this module not busy?. */ + if ((mmio_read_8(IIC_ICSR) & ICSR_BUSY) == 0U) { + /* Set ICCR=H'00 to disable the I2C module. */ + mmio_write_8(IIC_ICCR, 0x00U); + /* Increment the re-try number of times. */ + avs_retry++; + /* Set start a re-try to status. */ + avs_status = avs_status_start_condition; + } + break; + case avs_status_complete: + /* After "avs_status" became the "avs_status_complete", */ + /* "bl2_avs_setting()" function may be called. */ + break; + default: + /* This case is not possible. */ + ERROR("BL2: AVS setting is in invalid status. status=%u\n", + avs_status); + /* Infinite loop */ + panic(); + break; + } +#endif /* AVS_SETTING_ENABLE */ +} + +/* + * Finish the AVS setting. + */ +void bl2_avs_end(void) +{ +#if AVS_SETTING_ENABLE == 1 + uint32_t mstp; + + INFO("BL2: bl2_avs_end avs_status=%d\n", avs_status); + + /* While status is not completion, be repeated. */ + while (avs_status != avs_status_complete) { + bl2_avs_setting(); + } + NOTICE("BL2: AVS setting succeeded. DVFS_SetVID=0x%x\n", + pmic_setvid_reg[efuse_avs]); + +#if AVS_READ_PMIC_REG_ENABLE == 1 + { + uint8_t addr = PMIC_DVFS_SETVID; + uint8_t value; + value = avs_read_pmic_reg(addr); + NOTICE("BL2: Read PMIC register. address=0x%x value=0x%x \n", + addr, value); + } +#endif + + /* Bit of the module which wants to disable clock supply. */ + mstp = CPG_SYS_DVFS_BIT | CPG_SYS_ADVFS_BIT; + /* Disables the supply of clock signal to a module. */ + cpg_write(CPG_SMSTPCR9, + mmio_read_32(CPG_SMSTPCR9) | mstp); +#endif /* AVS_SETTING_ENABLE */ +} + +#if AVS_SETTING_ENABLE == 1 +/* + * Check error and judge re-try. + */ +static avs_error_t avs_check_error(void) +{ + avs_error_t ret; + + INFO("BL2: avs_check_error avs_status=%d\n", avs_status); + + if ((mmio_read_8(IIC_ICSR) & ICSR_AL) == ICSR_AL) { + NOTICE("BL2: Loss of arbitration is detected. " + "AVS status=%d Retry=%u\n", + avs_status, avs_retry); + /* Check of retry number of times*/ + if (avs_retry >= AVS_RETRY_NUM) { + ERROR("BL2: AVS setting failed in retry. max=%u\n", + AVS_RETRY_NUM); + /* Infinite loop */ + panic(); + } + /* Set the error detected to error status. */ + ret = avs_error_al; + } else if ((mmio_read_8(IIC_ICSR) & ICSR_TACK) == ICSR_TACK) { + NOTICE("BL2: Non-acknowledge is detected. " + "AVS status=%d Retry=%u\n", + avs_status, avs_retry); + /* Check of retry number of times*/ + if (avs_retry >= AVS_RETRY_NUM) { + ERROR("BL2: AVS setting failed in retry. max=%u\n", + AVS_RETRY_NUM); + /* Infinite loop */ + panic(); + } + /* Set the error detected to error status. */ + ret = avs_error_nack; + } else { + /* Not error. */ + ret = avs_error_none; + } + return ret; +} + +/* + * Set I2C for DVFS clock. + */ +static void avs_set_iic_clock(void) +{ + uint32_t md_pin; + + /* Read Mode pin register. */ + md_pin = mmio_read_32(RCAR_MODEMR) & (MODEMR_MD13 | MODEMR_MD14); + switch (md_pin) { + case CP_PHY_FREQ_8p33M: /* 8.3333MHz */ + mmio_write_8(IIC_ICCL, ICCL_FREQ_8p33M); + mmio_write_8(IIC_ICCH, ICCH_FREQ_8p33M); + break; + case CP_PHY_FREQ_10M: /* 10MHz */ + mmio_write_8(IIC_ICCL, ICCL_FREQ_10M); + mmio_write_8(IIC_ICCH, ICCH_FREQ_10M); + break; + case CP_PHY_FREQ_12p5M: /* 12.5MHz */ + mmio_write_8(IIC_ICCL, ICCL_FREQ_12p5M); + mmio_write_8(IIC_ICCH, ICCH_FREQ_12p5M); + break; + case CP_PHY_FREQ_16p66M: /* 16.6666MHz */ + mmio_write_8(IIC_ICCL, ICCL_FREQ_16p66M); + mmio_write_8(IIC_ICCH, ICCH_FREQ_16p66M); + break; + default: /* This case is not possible. */ + /* CP Phy frequency is to be set for the 16.66MHz */ + mmio_write_8(IIC_ICCL, ICCL_FREQ_16p66M); + mmio_write_8(IIC_ICCH, ICCH_FREQ_16p66M); + break; + } +} + +#if AVS_READ_PMIC_REG_ENABLE == 1 +/* + * Read the value of the register of PMIC. + */ +static uint8_t avs_read_pmic_reg(uint8_t addr) +{ + uint8_t reg; + + INFO("BL2: Read PMIC register start.\n"); + + /* Set ICCR.ICE=1 to activate the I2C module. */ + mmio_write_8(IIC_ICCR, mmio_read_8(IIC_ICCR) | ICCR_ENABLE); + + /* Set frequency of 400kHz */ + avs_set_iic_clock(); + + /* Set ICIC.WAITE=1, ICIC.DTEE=1 to enable data transmission */ + /* interrupt and wait interrupt. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_WAITE | ICIC_DTEE); + + /* Write H'94 in ICCR to issue start condition */ + mmio_write_8(IIC_ICCR, ICCR_START); + + /* Wait for a until ICSR.DTE becomes 1. */ + avs_poll( ICSR_DTE, 1U); + + /* Clear ICIC.DTEE to disable a DTE interrupt. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) & (uint8_t)(~ICIC_DTEE)); + /* Send slave address of PMIC */ + mmio_write_8(IIC_ICDR, PMIC_W_SLAVE_ADDRESS); + + /* Wait for a until ICSR.WAIT becomes 1. */ + avs_poll(ICSR_WAIT, 1U); + + /* write PMIC address */ + mmio_write_8(IIC_ICDR, addr); + /* Clear ICSR.WAIT to exit from WAIT status. */ + mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t)(~ICSR_WAIT)); + + /* Wait for a until ICSR.WAIT becomes 1. */ + avs_poll(ICSR_WAIT, 1U); + + /* Write H'94 in ICCR to issue restart condition */ + mmio_write_8(IIC_ICCR, ICCR_START); + /* Clear ICSR.WAIT to exit from WAIT status. */ + mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t)(~ICSR_WAIT)); + /* Set ICIC.DTEE=1 to enable data transmission interrupt. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_DTEE); + + /* Wait for a until ICSR.DTE becomes 1. */ + avs_poll( ICSR_DTE, 1U); + + /* Clear ICIC.DTEE to disable a DTE interrupt. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) & (uint8_t)(~ICIC_DTEE)); + /* Send slave address of PMIC */ + mmio_write_8(IIC_ICDR, PMIC_R_SLAVE_ADDRESS); + + /* Wait for a until ICSR.WAIT becomes 1. */ + avs_poll(ICSR_WAIT, 1U); + + /* Write H'81 to ICCR to issue the repeated START condition */ + /* for changing the transmission mode to the receive mode. */ + mmio_write_8(IIC_ICCR, ICCR_START_RECV); + /* Clear ICSR.WAIT to exit from WAIT status. */ + mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t)(~ICSR_WAIT)); + + /* Wait for a until ICSR.WAIT becomes 1. */ + avs_poll(ICSR_WAIT, 1U); + + /* Set ICCR to H'C0 for the STOP condition */ + mmio_write_8(IIC_ICCR, ICCR_STOP_RECV); + /* Clear ICSR.WAIT to exit from WAIT status. */ + mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t)(~ICSR_WAIT)); + /* Set ICIC.DTEE=1 to enable data transmission interrupt. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_DTEE); + + /* Wait for a until ICSR.DTE becomes 1. */ + avs_poll( ICSR_DTE, 1U); + + /* Receive DVFS SetVID register */ + /* Clear ICIC.DTEE to disable a DTE interrupt. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) & (uint8_t)(~ICIC_DTEE)); + /* Receive DVFS SetVID register */ + reg = mmio_read_8(IIC_ICDR); + + /* Wait until ICSR.BUSY is cleared. */ + avs_poll( ICSR_BUSY, 0U); + + /* Set ICCR=H'00 to disable the I2C module. */ + mmio_write_8(IIC_ICCR, 0x00U); + + return reg; +} + +/* + * Wait processing by the polling. + */ +static void avs_poll(uint8_t bit_pos, uint8_t val) +{ + uint8_t bit_val = 0U; + + if (val != 0U) { + bit_val = bit_pos; + } + + while (1) { + if ((mmio_read_8(IIC_ICSR) & bit_pos) == bit_val) { + break; + } + } +} +#endif /* AVS_READ_PMIC_REG_ENABLE */ +#endif /* AVS_SETTING_ENABLE */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/dma/dma_driver.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/dma/dma_driver.c new file mode 100644 index 0000000..cfceed3 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/dma/dma_driver.c @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "bl2_cpg_register.h" +#include "bl2_cpg_init.h" +#include "bl2_dma_register.h" +#include "dma_driver.h" +#include "debug.h" + +static void regdump(void); + +static void enableDMA(void); +static void setupDMA(void); +static void startDMA(uint32_t dst, uint32_t src, uint32_t len); +static void endDMA(void); +#if DEBUG +static void disableDMA(void); +#endif + +static void regdump(void) +{ +#if DEBUG + INFO("BL2:\n" + "%s(0x%x) : 0x%x\n" + "%s(0x%x) : 0x%x\n" + "%s(0x%x) : 0x%x\n" + "%s(0x%x) : 0x%x\n" + "%s(0x%x) : 0x%x\n" + "%s(0x%x) : 0x%x\n" + "%s(0x%x) : 0x%x\n" + "%s(0x%x) : 0x%x\n" + "%s(0x%x) : 0x%x\n" + "%s(0x%x) : 0x%x\n", + "CPG_SMSTPCR2",CPG_SMSTPCR2,mmio_read_32(CPG_SMSTPCR2), + "CPG_SRCR2 ",CPG_SRCR2,mmio_read_32(CPG_SRCR2), + "CPG_MSTPSR2 ",CPG_MSTPSR2,mmio_read_32(CPG_MSTPSR2), + "DMAOR2 ",DMA_DMAOR2,mmio_read_16(DMA_DMAOR2), + "DMASEC2 ",DMA_DMASEC2,mmio_read_32(DMA_DMASEC2), + "DMACHCLR2 ",DMA_DMACHCLR2,mmio_read_32(DMA_DMACHCLR2), + "DMASAR32 ",DMA_DMASAR32,mmio_read_32(DMA_DMASAR32), + "DMADAR32 ",DMA_DMADAR32,mmio_read_32(DMA_DMADAR32), + "DMATCR32 ",DMA_DMATCR32,mmio_read_32(DMA_DMATCR32), + "DMACHCR32 ",DMA_DMACHCR32,mmio_read_32(DMA_DMACHCR32) + ); +#endif +} + +static void enableDMA(void) +{ + /* Is the clock supply to the CPG disabled ? */ + while((mmio_read_32(CPG_MSTPSR2) & SYS_DMAC2_BIT) != 0U) { + /* Enables the clock supply to the CPG. */ + cpg_write(CPG_SMSTPCR2, + mmio_read_32(CPG_SMSTPCR2) & (~SYS_DMAC2_BIT)); + } +} + +static void setupDMA(void) +{ + /* DMA operation 2 */ + mmio_write_16(DMA_DMAOR2,0x0000U); + /* DMA channel clear 2 */ + mmio_write_32(DMA_DMACHCLR2,0x0000FFFFU); + mmio_write_32(DMA_DMACHCLR2,0x00000000U); +} + +static void startDMA(uint32_t dst, uint32_t src, uint32_t len) +{ + /* DMA operation 2 */ + mmio_write_16(DMA_DMAOR2,0x0301U); + /* DMA destination address 32 */ + mmio_write_32(DMA_DMADAR32,dst); + /* DMA source address 32 */ + mmio_write_32(DMA_DMASAR32,src); + /* DMA 64bytes-unit transfer count 32 */ + mmio_write_32(DMA_DMATCR32,len >> 6); + /* DMA DMA Secure Control Register 32 to 47 */ + mmio_write_32(DMA_DMASEC2,0x00000001U); + /* DMA channel control 32 */ + mmio_write_32(DMA_DMACHCR32,0x00105409U); +} + +static void endDMA(void) +{ + /* DMA channel control 32 */ + while((mmio_read_32(DMA_DMACHCR32) & 0x00000002U) == 0x00000000U) { + /* DMA channel control 32 */ + if ((mmio_read_32(DMA_DMACHCR32) & 0x80000000U) != 0U) { + ERROR("BL2: DMA - Channel Address Error\n"); + regdump(); + break; + } + } + /* DMA DMA Secure Control Register 32 to 47 */ + mmio_write_32(DMA_DMASEC2,0x00000000U); + /* DMA operation 2 */ + mmio_write_16(DMA_DMAOR2,0x0000U); + /* DMA channel clear 2 */ + mmio_write_32(DMA_DMACHCLR2,0x00000001U); + mmio_write_32(DMA_DMACHCLR2,0x00000000U); +} + +#if DEBUG +static void disableDMA(void) +{ + /* Disable the clock supply to the CPG. */ + cpg_write(CPG_SMSTPCR2, + mmio_read_32(CPG_SMSTPCR2) | SYS_DMAC2_BIT); +} +#endif + +void initDMA(void) +{ + enableDMA(); + setupDMA(); +} + +void execDMA(uint32_t dst, uint32_t src, uint32_t len) +{ + uint32_t dmalen; + uint32_t memlen; + + if (((dst & 0x3FU) != 0U) || ((src & 0x3FU) != 0U) || + ((len & 0xC0000000U) != 0U)) { + /* dst or src are not 64-bit alignment. */ + dmalen = 0U; + memlen = len; + } else { + /* dst and src are 64-bit alignment. */ + dmalen = len & 0x3FFFFFC0U; + memlen = len & 0x3FU; + } + if (dmalen != 0U) { + startDMA(dst, src, dmalen); + endDMA(); + dst += dmalen; + src += dmalen; + } else { + if (memlen == 0U) { + startDMA(dst, src, 0U); + endDMA(); + dmalen = 0x01000000U << 6; + dst += dmalen; + src += dmalen; + } + } + if (memlen != 0U) { + (void)memcpy((void*)(uint64_t)dst, + (const void*)(uint64_t)src, + (size_t)memlen); + } + if (dmalen != 0U) { + INFO("BL2: DMA len=%d(0x%x)\n", + dmalen, dmalen); + } + if (memlen != 0U) { + INFO("BL2: memcpy len=%d(0x%x)\n", + memlen, memlen); + } +} + +#if DEBUG +void termDMA(void) +{ + disableDMA(); +} +#endif diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/error/bl2_int_error.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/error/bl2_int_error.c new file mode 100644 index 0000000..f443df1 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/error/bl2_int_error.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "bl2_int_error.h" +#include "../../rcar_def.h" + +#define INT_ID_MASK (0x000003FFU) +#define SWDT_ERROR_ID (1024U) +#define SWDT_ERROR_TYPE (16U) +#define SWDT_CHAR_MAX (13U) + +void bl2_interrupt_error_id(uint32_t wrong_id) +{ + if (wrong_id >= SWDT_ERROR_ID) { + ERROR("\n"); + ERROR("BL2: bl2_interrupt_error_id error, invalid ID = %d\n" + ,wrong_id); + /* Endless loop */ + panic(); + } + /* Clear the interrupt request */ + arm_gic_end_of_interrupt((uint32_t)wrong_id); + bl2_swdt_release(); + ERROR("\n"); + ERROR("BL2: This interrupt is Invalid, receive interrupt ID = %d\n" + ,wrong_id); + /* Endless loop */ + panic(); +} + +void bl2_interrupt_error_type(uint32_t wrong_type) +{ + const uint8_t interrupt_ex[SWDT_ERROR_TYPE][SWDT_CHAR_MAX] = { + "SYNC SP EL0", + "IRQ SP EL0", + "FIQ SP EL0", + "SERR SP EL0", + "SYNC SP ELx", + "IRQ SP ELx", + "FIQ SP ELx", + "SERR SP ELx", + "SYNC AARCH64", + "IRQ AARCH64", + "FIQ AARCH64", + "SERR AARCH64", + "SYNC AARCH32", + "IRQ AARCH32", + "FIQ AARCH32", + "SERR AARCH32" + }; + uint32_t interrupt_id; + char msg[128]; + + if (wrong_type >= SWDT_ERROR_TYPE) { + /* Clear the interrupt request */ + (void)arm_gic_acknowledge_interrupt(); + ERROR("\n"); + (void)sprintf(msg, + "BL2: bl2_interrupt_error_type error, invalid type = %d\n" + ,wrong_type); + ERROR("%s", msg); + /* endless loop */ + panic(); + } else { + interrupt_id = arm_gic_acknowledge_interrupt() & INT_ID_MASK; + bl2_swdt_release(); + + ERROR("\n"); + (void)sprintf(msg, + "BL2: This interrupt is not FIQ, interrupt type = %s, ID = %d\n" + ,&interrupt_ex[wrong_type][0], interrupt_id); + ERROR("%s", msg); + /* Endless loop */ + panic(); + } +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.c new file mode 100644 index 0000000..4fc59ea --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.c @@ -0,0 +1,402 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "../../rcar_def.h" +#include "iic_dvfs.h" + +#define DVFS_RETRY_MAX (2U) + +#define MODEMR_SET_MASK_13_14 (0x6000U) +#define MODEMR_SET_10p00M (0x2000U) +#define MODEMR_SET_12p50M (0x4000U) +#define MODEMR_SET_08p33M (0x0000U) +#define MODEMR_SET_16p66M (0x6000U) + +#define IIC_DVFS_SET_ICCL_08p33M (0x07U) +#define IIC_DVFS_SET_ICCL_10p00M (0x09U) +#define IIC_DVFS_SET_ICCL_12p50M (0x0BU) +#define IIC_DVFS_SET_ICCL_16p66M (0x0EU) + +#define IIC_DVFS_SET_ICCH_08p33M (0x01U) +#define IIC_DVFS_SET_ICCH_10p00M (0x02U) +#define IIC_DVFS_SET_ICCH_12p50M (0x03U) +#define IIC_DVFS_SET_ICCH_16p66M (0x05U) + +#define CPG_REG_BASE (0xE6150000U) +#define CPG_REG_SMSTPCR9 (CPG_REG_BASE + 0x0994U) +#define CPG_REG_MSTPSR9 (CPG_REG_BASE + 0x09A4U) + +#define CPG_BIT_SMSTPCR9_DVFS (0x04000000U) + +#define IIC_DVFS_REG_BASE (0xE60B0000U) +#define IIC_DVFS_REG_ICDR (IIC_DVFS_REG_BASE + 0x0000U) +#define IIC_DVFS_REG_ICCR (IIC_DVFS_REG_BASE + 0x0004U) +#define IIC_DVFS_REG_ICSR (IIC_DVFS_REG_BASE + 0x0008U) +#define IIC_DVFS_REG_ICIC (IIC_DVFS_REG_BASE + 0x000CU) +#define IIC_DVFS_REG_ICCL (IIC_DVFS_REG_BASE + 0x0010U) +#define IIC_DVFS_REG_ICCH (IIC_DVFS_REG_BASE + 0x0014U) + +#define IIC_DVFS_BIT_ICSR_BUSY (0x10U) +#define IIC_DVFS_BIT_ICSR_AL (0x08U) +#define IIC_DVFS_BIT_ICSR_TACK (0x04U) +#define IIC_DVFS_BIT_ICSR_WAIT (0x02U) +#define IIC_DVFS_BIT_ICSR_DTE (0x01U) + +#define IIC_DVFS_BIT_ICCR_ENABLE (0x80U) +#define IIC_DVFS_SET_ICCR_START (0x94U) +#define IIC_DVFS_SET_ICCR_STOP (0x90U) + +#define IIC_DVFS_BIT_ICIC_TACKE (0x04U) +#define IIC_DVFS_BIT_ICIC_WAITE (0x02U) +#define IIC_DVFS_BIT_ICIC_DTEE (0x01U) + +#define IIC_DVFS_SET_DUMMY (0x52U) +#define IIC_DVFS_SET_BUSY_LOOP (500000000U) + +typedef enum { + DVFS_START_CONDITION = 0, + DVFS_SET_SLAVE_ADDR, + DVFS_WRITE_REG_ADDR, + DVFS_WRITE_REG_DATA, + DVFS_STOP_CONDITION, + DVFS_PROCESS_COMPLETE +}DVFS_STATUS_T; + +#define DVFS_PROCESS (1) +#define DVFS_COMPLETE (0) +#define DVFS_ERROR (-1) + +static int32_t dvfs_check_error(DVFS_STATUS_T *status, uint32_t *err_count); +static int32_t dvfs_start_condition(DVFS_STATUS_T *status); +static int32_t dvfs_set_slave_addr(DVFS_STATUS_T *status, uint32_t *err_count, uint8_t slave_addr); +static int32_t dvfs_write_reg_addr(DVFS_STATUS_T *status, uint32_t *err_count, uint8_t reg_addr); +static int32_t dvfs_write_reg_data(DVFS_STATUS_T *status, uint32_t *err_count, uint8_t reg_data); +static int32_t dvfs_stop_condition(DVFS_STATUS_T *status, uint32_t *err_count); +static int32_t dvfs_process_complete(void); + +int32_t rcar_iic_dvfs_send(uint8_t slave_addr, uint8_t reg_addr, uint8_t reg_data) +{ + int32_t result; + uint32_t reg; + DVFS_STATUS_T status; + uint32_t err_count; + + /* Clock supply of DVFS is enabled */ + reg = mmio_read_32(CPG_REG_SMSTPCR9) & ~CPG_BIT_SMSTPCR9_DVFS; + mmio_write_32(RCAR_CPGWPR, ~reg); + mmio_write_32(CPG_REG_SMSTPCR9, reg); + while ((mmio_read_32(CPG_REG_MSTPSR9) & CPG_BIT_SMSTPCR9_DVFS) + != 0x00000000U) { + } + + /* Disable IIC-DVFS module */ + mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U); + + status = DVFS_START_CONDITION; + result = DVFS_PROCESS; + err_count = 0U; + + while (result == DVFS_PROCESS) { + switch (status) { + case DVFS_START_CONDITION: + result = dvfs_start_condition(&status); + break; + case DVFS_SET_SLAVE_ADDR: + result = dvfs_set_slave_addr(&status, &err_count, slave_addr); + break; + case DVFS_WRITE_REG_ADDR: + result = dvfs_write_reg_addr(&status, &err_count, reg_addr); + break; + case DVFS_WRITE_REG_DATA: + result = dvfs_write_reg_data(&status, &err_count, reg_data); + break; + case DVFS_STOP_CONDITION: + result = dvfs_stop_condition(&status, &err_count); + break; + case DVFS_PROCESS_COMPLETE: + result = dvfs_process_complete(); + break; + default: + panic(); + break; + } + } + + return result; +} + +static int32_t dvfs_check_error(DVFS_STATUS_T *status, uint32_t *err_count) +{ + int32_t error; + uint8_t reg; + uint32_t loop_cnt; + + reg = mmio_read_8(IIC_DVFS_REG_ICSR); + if ((reg & IIC_DVFS_BIT_ICSR_AL) == IIC_DVFS_BIT_ICSR_AL) { + reg = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_AL)); + /* Clear the AL flag */ + mmio_write_8(IIC_DVFS_REG_ICSR, reg); + if (*status == DVFS_SET_SLAVE_ADDR) { + mmio_write_8(IIC_DVFS_REG_ICDR, IIC_DVFS_SET_DUMMY); + } + while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT) + == 0x00U) { + } + /* Write stop condition */ + mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP); + /* Clear the WAIT flag */ + reg = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_WAIT)); + mmio_write_8(IIC_DVFS_REG_ICSR, reg); + loop_cnt = 0U; + while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) + != 0x00U) { + loop_cnt++; + if (loop_cnt > IIC_DVFS_SET_BUSY_LOOP) { + panic(); + } + } + mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U); + /* error count increment */ + (*err_count)++; + if (*err_count >= DVFS_RETRY_MAX) { + error = DVFS_ERROR; + } else { + /* status initialize */ + *status = DVFS_START_CONDITION; + error = DVFS_PROCESS; + } + } else if ((reg & IIC_DVFS_BIT_ICSR_TACK) == IIC_DVFS_BIT_ICSR_TACK) { + /* Write stop condition */ + mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP); + /* Disable WAIT and DTE interrupt */ + reg = mmio_read_8(IIC_DVFS_REG_ICIC); + reg &= ((uint8_t)(~(IIC_DVFS_BIT_ICIC_WAITE | IIC_DVFS_BIT_ICIC_DTEE))); + mmio_write_8(IIC_DVFS_REG_ICIC, reg); + /* Clear the TACK flag */ + reg = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_TACK)); + mmio_write_8(IIC_DVFS_REG_ICSR, reg); + loop_cnt = 0U; + while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) + != 0x00U) { + loop_cnt++; + if (loop_cnt > IIC_DVFS_SET_BUSY_LOOP) { + panic(); + } + } + mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U); + (*err_count)++; + if (*err_count >= DVFS_RETRY_MAX) { + error = DVFS_ERROR; + } else { + /* status initialize */ + *status = DVFS_START_CONDITION; + error = DVFS_PROCESS; + } + } else { + error = DVFS_PROCESS; + } + + return error; +} + +static int32_t dvfs_start_condition(DVFS_STATUS_T *status) +{ + uint32_t reg; + uint8_t mode; + int32_t result; + + result = DVFS_PROCESS; + /* Set ICCR.ICE */ + mode = mmio_read_8(IIC_DVFS_REG_ICCR) + | ((uint8_t)(IIC_DVFS_BIT_ICCR_ENABLE)); + mmio_write_8(IIC_DVFS_REG_ICCR, mode); + /* Set clock */ + reg = mmio_read_32(RCAR_MODEMR) & MODEMR_SET_MASK_13_14; + switch (reg) { + case MODEMR_SET_08p33M: + mmio_write_8(IIC_DVFS_REG_ICCL, IIC_DVFS_SET_ICCL_08p33M); + mmio_write_8(IIC_DVFS_REG_ICCH, IIC_DVFS_SET_ICCH_08p33M); + break; + case MODEMR_SET_10p00M: + mmio_write_8(IIC_DVFS_REG_ICCL, IIC_DVFS_SET_ICCL_10p00M); + mmio_write_8(IIC_DVFS_REG_ICCH, IIC_DVFS_SET_ICCH_10p00M); + break; + case MODEMR_SET_12p50M: + mmio_write_8(IIC_DVFS_REG_ICCL, IIC_DVFS_SET_ICCL_12p50M); + mmio_write_8(IIC_DVFS_REG_ICCH, IIC_DVFS_SET_ICCH_12p50M); + break; + case MODEMR_SET_16p66M: + mmio_write_8(IIC_DVFS_REG_ICCL, IIC_DVFS_SET_ICCL_16p66M); + mmio_write_8(IIC_DVFS_REG_ICCH, IIC_DVFS_SET_ICCH_16p66M); + break; + default: + mmio_write_8(IIC_DVFS_REG_ICCL, IIC_DVFS_SET_ICCL_16p66M); + mmio_write_8(IIC_DVFS_REG_ICCH, IIC_DVFS_SET_ICCH_16p66M); + break; + } + /* Set ICIC.TACKE, ICIC.WAITE and ICIC.DTEE */ + mode = mmio_read_8(IIC_DVFS_REG_ICIC) + | IIC_DVFS_BIT_ICIC_TACKE + | IIC_DVFS_BIT_ICIC_WAITE + | IIC_DVFS_BIT_ICIC_DTEE; + mmio_write_8(IIC_DVFS_REG_ICIC, mode); + /* Write start condition */ + mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_START); + /* Next status */ + *status = DVFS_SET_SLAVE_ADDR; + + return result; +} + +static int32_t dvfs_set_slave_addr(DVFS_STATUS_T *status, uint32_t *err_count, uint8_t slave_addr) +{ + uint8_t mode; + int32_t result; + uint8_t address; + + /* error check */ + result = dvfs_check_error(status, err_count); + if (result != DVFS_ERROR) { + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)IIC_DVFS_BIT_ICSR_DTE); + if (mode == ((uint8_t)IIC_DVFS_BIT_ICSR_DTE)) { + /* Clear ICIC.DTEE */ + mode = mmio_read_8(IIC_DVFS_REG_ICIC) + & ((uint8_t)(~IIC_DVFS_BIT_ICIC_DTEE)); + mmio_write_8(IIC_DVFS_REG_ICIC, mode); + /* Send 7bit slave address + write mode bit */ + address = (uint8_t)(slave_addr << 1); + mmio_write_8(IIC_DVFS_REG_ICDR, address); + /* Next status */ + *status = DVFS_WRITE_REG_ADDR; + } + } + + return result; +} + +static int32_t dvfs_write_reg_addr(DVFS_STATUS_T *status, uint32_t *err_count, uint8_t reg_addr) +{ + uint8_t mode; + int32_t result; + + result = dvfs_check_error(status, err_count); + if (result != DVFS_ERROR) { + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT); + if (mode == ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT)) { + /* Send register address */ + mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr); + /* Clear ICSR.WAIT */ + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_WAIT)); + mmio_write_8(IIC_DVFS_REG_ICSR, mode); + /* Next status */ + *status = DVFS_WRITE_REG_DATA; + } + } + + return result; +} + +static int32_t dvfs_write_reg_data(DVFS_STATUS_T *status, uint32_t *err_count, uint8_t reg_data) +{ + uint8_t mode; + int32_t result; + + result = dvfs_check_error(status, err_count); + if (result != DVFS_ERROR) { + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT); + if (mode == ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT)) { + /* Send data */ + mmio_write_8(IIC_DVFS_REG_ICDR, reg_data); + /* Clear ICSR.WAIT */ + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_WAIT)); + mmio_write_8(IIC_DVFS_REG_ICSR, mode); + /* Next status */ + *status = DVFS_STOP_CONDITION; + } + } + + return result; +} + +static int32_t dvfs_stop_condition(DVFS_STATUS_T *status, uint32_t *err_count) +{ + uint8_t mode; + int32_t result; + + result = dvfs_check_error(status, err_count); + if (result != DVFS_ERROR) { + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT); + if (mode == ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT)) { + /* Write stop condition */ + mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP); + /* Clear ICSR.WAIT */ + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_WAIT)); + mmio_write_8(IIC_DVFS_REG_ICSR, mode); + /* Next status */ + *status = DVFS_PROCESS_COMPLETE; + } + } + + return result; +} + +static int32_t dvfs_process_complete(void) +{ + int32_t result; + uint32_t loop_cnt; + + loop_cnt = 0U; + while ((mmio_read_8(IIC_DVFS_REG_ICSR) & ((uint8_t)IIC_DVFS_BIT_ICSR_BUSY)) + != 0x00U) { + loop_cnt++; + if (loop_cnt > IIC_DVFS_SET_BUSY_LOOP) { + panic(); + } + } + /* Disable IIC for DVFS */ + mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U); + /* process complete */ + result = DVFS_COMPLETE; + + return result; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.h new file mode 100644 index 0000000..d569b45 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef IIC_DVFS_H__ +#define IIC_DVFS_H__ + +#define SLAVE_ADDR_PMIC (0x30U) + +#define REG_ADDR_DVFS_SetVID (0x54U) +#define REG_DATA_DVFS_SetVID_0V (0x00U) + +#define REG_ADDR_BKUP_Mode_Cnt (0x20U) +#define REG_DATA_P_ALL_OFF (0x80U) + +int32_t rcar_iic_dvfs_send(uint8_t slave_addr, uint8_t reg_addr, uint8_t reg_data); + +#endif /* IIC_DVFS_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/io/io_memdrv.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/io/io_memdrv.c new file mode 100644 index 0000000..efc8443 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/io/io_memdrv.c @@ -0,0 +1,236 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "io_memdrv.h" +#include "dma_driver.h" + +/* As we need to be able to keep state for seek, only one file can be open + * at a time. Make this a structure and point to the entity->info. When we + * can malloc memory we can change this to support more open files. + */ +typedef struct { + /* Use the 'in_use' flag as any value for base and file_pos could be + * valid. + */ + uint32_t in_use; + uintptr_t base; + ssize_t file_pos; +} file_state_t; + +static file_state_t current_file = {0}; + +/* memdrv device functions */ +static io_type_t device_type_memdrv(void); +static int32_t memdrv_dev_open(const uintptr_t dev_spec, + io_dev_info_t **dev_info); +static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); +static int32_t memdrv_block_seek(io_entity_t *entity, int32_t mode, + ssize_t offset); +static int32_t memdrv_block_read(io_entity_t *entity, uintptr_t buffer, + size_t length, size_t *length_read); +static int32_t memdrv_block_close(io_entity_t *entity); +static int32_t memdrv_dev_close(io_dev_info_t *dev_info); + + +static const io_dev_connector_t memdrv_dev_connector = { + .dev_open = &memdrv_dev_open +}; + + +static const io_dev_funcs_t memdrv_dev_funcs = { + .type = &device_type_memdrv, + .open = &memdrv_block_open, + .seek = &memdrv_block_seek, + .size = NULL, + .read = &memdrv_block_read, + .write = NULL, + .close = &memdrv_block_close, + .dev_init = NULL, + .dev_close = &memdrv_dev_close, +}; + + +/* No state associated with this device so structure can be const */ +static const io_dev_info_t memdrv_dev_info = { + .funcs = &memdrv_dev_funcs, + .info = (uintptr_t)0 +}; + +/* Identify the device type as memdrv */ +static io_type_t device_type_memdrv(void) +{ + return IO_TYPE_MEMMAP; +} + + +/* Open a connection to the memdrv device */ +static int32_t memdrv_dev_open( + const uintptr_t dev_spec __attribute__((unused)), + io_dev_info_t **dev_info) +{ + assert(dev_info != NULL); + *dev_info = (io_dev_info_t *)&memdrv_dev_info; /* cast away const */ + + return IO_SUCCESS; +} + + + +/* Close a connection to the memdrv device */ +static int32_t memdrv_dev_close(io_dev_info_t *dev_info) +{ + /* NOP */ + /* TODO: Consider tracking open files and cleaning them up here */ + return IO_SUCCESS; +} + + +/* Open a file on the memdrv device */ +/* TODO: Can we do any sensible limit checks on requested memory */ +static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity) +{ + int32_t result; + const io_block_spec_t *block_spec = (io_block_spec_t *)spec; + + /* Since we need to track open state for seek() we only allow one open + * spec at a time. When we have dynamic memory we can malloc and set + * entity->info. + */ + if (current_file.in_use == 0U) { + assert(block_spec != NULL); + assert(entity != NULL); + + current_file.in_use = 1U; + current_file.base = block_spec->offset; + /* File cursor offset for seek and incremental reads etc. */ + current_file.file_pos = 0; + entity->info = (uintptr_t)¤t_file; + result = IO_SUCCESS; + } else { + WARN("A memdrv device is already active. Close first.\n"); + result = IO_RESOURCES_EXHAUSTED; + } + + return result; +} + + +/* Seek to a particular file offset on the memdrv device */ +static int32_t memdrv_block_seek(io_entity_t *entity, int32_t mode, + ssize_t offset) +{ + int32_t result; + + /* We only support IO_SEEK_SET for the moment. */ + if ((io_seek_mode_t)mode == IO_SEEK_SET) { + assert(entity != NULL); + assert(entity->info != (uintptr_t)NULL); + + /* TODO: can we do some basic limit checks on seek? */ + ((file_state_t *)entity->info)->file_pos = offset; + result = IO_SUCCESS; + } else { + result = IO_FAIL; + } + + return result; +} + + +/* Read data from a file on the memdrv device */ +static int32_t memdrv_block_read(io_entity_t *entity, uintptr_t buffer, + size_t length, size_t *length_read) +{ + file_state_t *fp; + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_read != NULL); + + fp = (file_state_t *)entity->info; + + NOTICE("BL2: dst=0x%x src=0x%x len=%d(0x%x)\n", + (uint32_t)buffer, + (uint32_t)(fp->base + fp->file_pos), + (uint32_t)length, (uint32_t)length); + +#if 1 /* DMA driver */ + execDMA((uint32_t)buffer, (uint32_t)(fp->base + fp->file_pos), + (uint32_t)length); +#else + (void)memcpy((void *)buffer, (void *)(fp->base + fp->file_pos), + length); +#endif + + *length_read = length; + /* advance the file 'cursor' for incremental reads */ + fp->file_pos += (ssize_t)length; + + return IO_SUCCESS; +} + + +/* Close a file on the memdrv device */ +static int32_t memdrv_block_close(io_entity_t *entity) +{ + assert(entity != NULL); + + entity->info = 0U; + + /* This would be a mem free() if we had malloc.*/ + (void)memset((void *)¤t_file, 0, sizeof(current_file)); + + return IO_SUCCESS; +} + + +/* Exported functions */ + +/* Register the memdrv driver with the IO abstraction */ +int32_t register_io_dev_memdrv(const io_dev_connector_t **dev_con) +{ + int32_t result; + assert(dev_con != NULL); + + result = io_register_device(&memdrv_dev_info); + if (result == IO_SUCCESS) { + *dev_con = &memdrv_dev_connector; + } + + return result; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/io/io_rcar.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/io/io_rcar.c new file mode 100644 index 0000000..ed368c8 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/io/io_rcar.c @@ -0,0 +1,620 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "io_rcar.h" + + +typedef struct { + const int32_t name; + const uint32_t offset; + const uint32_t attr; +} plat_rcar_name_offset_t; + +typedef struct { + /* Put file_pos above the struct to allow {0} on static init. + * It is a workaround for a known bug in GCC + * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119 + */ + uint32_t file_pos; + uint32_t is_noload; + uint32_t offset_address; + uint32_t size; + uint32_t dest_address; +} file_state_t; + +#define RCAR_GET_FLASH_ADR(a,b) (uint32_t)((0x40000U*(a)) + (b)) +#define RCAR_ATTR_SET_CALCADDR(a) ((a) & 0xF) /* lower 4bit use */ +#define RCAR_ATTR_SET_ISNOLOAD(a) (((a) & 0x1) << 16U) /* 16bit use */ +#define RCAR_ATTR_SET_CERTOFF(a) (((a) & 0xF) << 8U) /* 11-8bit use */ +#define RCAR_ATTR_SET_ALL(a,b,c) (uint32_t)(RCAR_ATTR_SET_CALCADDR(a) |\ + RCAR_ATTR_SET_ISNOLOAD(b) | RCAR_ATTR_SET_CERTOFF(c)) + +#define RCAR_ATTR_GET_CALCADDR(a) ((a) & 0xFU) /* lower 4bit use */ +#define RCAR_ATTR_GET_ISNOLOAD(a) (((a) >> 16) & 0x1U) /* 16bit use */ +#define RCAR_ATTR_GET_CERTOFF(a) (((a) >> 8) & 0xFU) /* 11-8bit use */ + +#define RCAR_MAX_BL3X_IMAGE (8U) +#define RCAR_SECTOR6_CERT_OFFSET (0x400U) +#define RCAR_SDRAM_CERT_ADDRESS (0x43F00000U) +#define RCAR_CERT_SIZE (0x400U) +#define RCAR_CERT_INFO_SIZE_OFFSET (0x264U) /* byte address set : must 4byte alignment */ +#define RCAR_CERT_INFO_DST_OFFSET (0x154U) /* byte address set : must 4byte alignment */ + +#define RCAR_CERT_LOAD (1U) + +static const plat_rcar_name_offset_t name_offset[] = { /* calc addr, no load, cert offset */ + {BL31_IMAGE_ID, RCAR_GET_FLASH_ADR(7U,0x000U), RCAR_ATTR_SET_ALL(0,0,0)}, + /* BL3-2 is optional in the platform */ + {BL32_IMAGE_ID, RCAR_GET_FLASH_ADR(8U,0x000U), RCAR_ATTR_SET_ALL(0,0,1)}, + {BL33_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(1,0,2)}, + {BL332_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(2,0,3)}, + {BL333_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(3,0,4)}, + {BL334_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(4,0,5)}, + {BL335_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(5,0,6)}, + {BL336_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(6,0,7)}, + {BL337_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(7,0,8)}, + {BL338_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(8,0,9)}, +}; +#if TRUSTED_BOARD_BOOT +static const plat_rcar_name_offset_t cert_offset[] = { + /* Certificates */ + {TRUSTED_KEY_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,0)}, + {BL31_KEY_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,0)}, + {BL32_KEY_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,0)}, + {BL33_KEY_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,0)}, + {BL31_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,0)}, + {BL32_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,1)}, + {BL33_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,2)}, + {BL332_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,3)}, + {BL333_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,4)}, + {BL334_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,5)}, + {BL335_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,6)}, + {BL336_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,7)}, + {BL337_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,8)}, + {BL338_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,9)}, +}; +#endif /* TRUSTED_BOARD_BOOT */ + + +static file_state_t current_file = {0}; +static uintptr_t backend_dev_handle; +static uintptr_t backend_image_spec; +static uint32_t rcar_image_header[RCAR_MAX_BL3X_IMAGE + 1U] = {0U}; +static uint32_t rcar_cert_load = {0U}; + + +/* prototype */ +static io_type_t device_type_rcar(void); +static int32_t rcar_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); +static int32_t rcar_file_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); +static int32_t rcar_file_len(io_entity_t *entity, size_t *length); +static int32_t rcar_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read); +static int32_t rcar_file_close(io_entity_t *entity); +static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params); +static int32_t rcar_dev_close(io_dev_info_t *dev_info); +static int32_t file_to_offset(const int32_t file, uint32_t *offset, uint32_t *cert_addr, uint32_t *is_noload); +static int32_t load_bl33x(uintptr_t handle); + + +/* Identify the device type as a virtual driver */ +static io_type_t device_type_rcar(void) +{ + return IO_TYPE_FIRMWARE_IMAGE_PACKAGE; +} + + +static const io_dev_connector_t rcar_dev_connector = { + .dev_open = &rcar_dev_open +}; + + +static const io_dev_funcs_t rcar_dev_funcs = { + .type = &device_type_rcar, + .open = &rcar_file_open, + .seek = NULL, + .size = &rcar_file_len, + .read = &rcar_file_read, + .write = NULL, + .close = &rcar_file_close, + .dev_init = &rcar_dev_init, + .dev_close = &rcar_dev_close, +}; + + +/* No state associated with this device so structure can be const */ +static const io_dev_info_t rcar_dev_info = { + .funcs = &rcar_dev_funcs, + .info = (uintptr_t)0 +}; + + +/* Open a connection to the FIP device */ +static int32_t rcar_dev_open(const uintptr_t dev_spec __attribute__((unused)), + io_dev_info_t **dev_info) +{ + assert(dev_info != NULL); + *dev_info = (io_dev_info_t *)&rcar_dev_info; /* cast away const */ + + return IO_SUCCESS; +} + +int32_t file_to_cert(const int32_t filename, uint32_t *cert_addr) +{ + int32_t i; + int32_t status = -EINVAL; + + for (i = 0; i < (int32_t)ARRAY_SIZE(cert_offset); i++) { + if (filename == cert_offset[i].name) { + *cert_addr = RCAR_CERT_SIZE; + *cert_addr *= (uint32_t)RCAR_ATTR_GET_CERTOFF(cert_offset[i].attr); + *cert_addr += RCAR_SDRAM_CERT_ADDRESS; + status = 0; + break; + } + } + return status; +} + +static int32_t file_to_offset(const int32_t file, uint32_t *offset, uint32_t *cert_addr, uint32_t *is_noload) +{ + int32_t i; + int32_t status = -EINVAL; + uint32_t is_calc_addr; + + assert(offset != NULL); + assert(cert_addr != NULL); + assert(is_noload != NULL); + + for (i = 0; i < (int32_t)ARRAY_SIZE(name_offset); i++) { + if (file == name_offset[i].name) { + is_calc_addr = RCAR_ATTR_GET_CALCADDR(name_offset[i].attr); + if (rcar_image_header[0] >= is_calc_addr) + { + if (0U != is_calc_addr) + { + *offset = rcar_image_header[is_calc_addr]; + } else { + *offset = name_offset[i].offset; + } + *cert_addr = RCAR_CERT_SIZE; + *cert_addr *= RCAR_ATTR_GET_CERTOFF(name_offset[i].attr); + *cert_addr += RCAR_SDRAM_CERT_ADDRESS; + *is_noload = RCAR_ATTR_GET_ISNOLOAD(name_offset[i].attr); + status = IO_SUCCESS; + break; + } + } + } + + if (IO_SUCCESS != status) { + for (i = 0; i < (int32_t)ARRAY_SIZE(cert_offset); i++) { + if (file == cert_offset[i].name) { + *offset = 0U; + *cert_addr = 0U; + *is_noload = RCAR_ATTR_GET_ISNOLOAD(cert_offset[i].attr); + status = IO_SUCCESS; + break; + } + } + } + return status; +} + +void get_info_from_cert(uint64_t cert_addr, uint32_t *size, uint32_t *dest_addr) +{ + assert(size != NULL); + assert(dest_addr != NULL); + + cert_addr &= 0xFFFFFFFFU; /* need? */ + + *size = *((uint32_t *)(cert_addr + RCAR_CERT_INFO_SIZE_OFFSET)) * 4U; + *dest_addr = *((uint32_t *)(cert_addr + RCAR_CERT_INFO_DST_OFFSET)); +} + +static int32_t load_bl33x(uintptr_t handle) +{ + int32_t result = IO_SUCCESS; + uint32_t loop = 1U; /* start is BL332 */ + uint32_t file_offset; + uint32_t noload; + uint32_t cert_addr; + uint32_t l_image_size; + uint32_t dest_addr; + size_t bytes_read; + const int32_t load_names[] = { + BL33_IMAGE_ID, + BL332_IMAGE_ID, + BL333_IMAGE_ID, + BL334_IMAGE_ID, + BL335_IMAGE_ID, + BL336_IMAGE_ID, + BL337_IMAGE_ID, + BL338_IMAGE_ID + }; + + for (; loop < rcar_image_header[0]; loop++) { + + if (IO_SUCCESS != result){ + break; + } + + result = file_to_offset(load_names[loop], &file_offset, + &cert_addr, &noload); + if (IO_SUCCESS != result) { + WARN("load_bl33x: failed to get offset\n"); + result = IO_FAIL; + } else { + + get_info_from_cert((uint64_t) cert_addr, &l_image_size, + &dest_addr); + + result = io_seek(handle, IO_SEEK_SET, + (ssize_t) file_offset); + if (IO_SUCCESS != result) { + WARN("load_bl33x: failed to seek\n"); + result = IO_FAIL; + } + } + + if (IO_SUCCESS == result) { + + result = io_read(handle, (uintptr_t)dest_addr, (size_t)l_image_size, + (size_t *)&bytes_read); + if (IO_SUCCESS != result) { + WARN("load_bl33x: failed to read\n"); + result = IO_FAIL; + } +#if TRUSTED_BOARD_BOOT + else { + /* Authenticate it */ + result = (int32_t)auth_mod_verify_img( + (unsigned int)load_names[loop], + (void *)((uintptr_t)dest_addr), + (unsigned int)l_image_size); + if (0 != result) { + memset((void *)((uintptr_t)dest_addr), + 0x00, + (size_t)l_image_size); + result = IO_FAIL; + } + } +#endif /* TRUSTED_BOARD_BOOT */ + } + } + + return result; +} + +/* Do some basic package checks. */ +static int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params) +{ + int32_t result; + int32_t image_name = (int32_t)init_params; + uintptr_t backend_handle; + size_t bytes_read; + + /* Obtain a reference to the image by querying the platform layer */ + /* get rcar flash memory address... (certain BL2, BL31, BL32, BL33... max 64MB:RPC LBSC address) */ + /* sakata check image number */ + result = plat_get_image_source(image_name, &backend_dev_handle, + &backend_image_spec); + if (result != IO_SUCCESS) { + WARN("Failed to obtain reference to image '%d' (%i)\n", + image_name, result); + result = IO_FAIL; + } else { + + if (RCAR_CERT_LOAD == rcar_cert_load) { + /* not load certificate file after 1at initialize */ + result = IO_SUCCESS; + } else { + + /* Attempt to access the RCAR image */ + /* open memory driver (certain SYS-DMAC2 initialize) */ + result = io_open(backend_dev_handle, backend_image_spec, + &backend_handle); + if (result != IO_SUCCESS) { + WARN("Failed to access image '%d' (%i)\n", + image_name, result); + result = IO_FAIL; + } + + /* get start address list */ + /* [0] address num */ + /* [1] BL33-1 image address */ + /* [2] BL33-2 image address */ + /* [3] BL33-3 image address */ + /* [4] BL33-4 image address */ + /* [5] BL33-5 image address */ + /* [6] BL33-6 image address */ + /* [7] BL33-7 image address */ + /* [8] BL33-8 image address */ + if (IO_SUCCESS == result) { + result = io_seek(backend_handle, IO_SEEK_SET, + (ssize_t) RCAR_GET_FLASH_ADR(6U, 0U)); + if (result != IO_SUCCESS) { + WARN("Firmware Image Package header "\ + "failed to seek\n"); + result = IO_FAIL; + (void) io_close(backend_handle); + } + } + if (IO_SUCCESS == result) { + result = io_read(backend_handle, + (uintptr_t) &rcar_image_header, + sizeof(rcar_image_header), &bytes_read); + if (result == IO_SUCCESS) { + if ((rcar_image_header[0] == 0U) + || (rcar_image_header[0] > 8U)) { + WARN("Firmware Image Package "\ + "header check failed.\n"); + result = IO_FAIL; + (void) io_close(backend_handle); + } else { + VERBOSE("header looks OK.\n"); + } + } + } + /* load cert file */ + if (IO_SUCCESS == result) { + result = io_seek(backend_handle, IO_SEEK_SET, + (ssize_t) (RCAR_GET_FLASH_ADR(6U, 0U) + + RCAR_SECTOR6_CERT_OFFSET)); + if (result != IO_SUCCESS) { + WARN("Firmware Image Package "\ + "header failed to seek\n"); + result = IO_FAIL; + (void) io_close(backend_handle); + } + } + if (IO_SUCCESS == result) { + result = io_read(backend_handle, + (uintptr_t) RCAR_SDRAM_CERT_ADDRESS, + (size_t) (RCAR_CERT_SIZE * + (2U + (size_t) rcar_image_header[0])), + &bytes_read); + if (result != IO_SUCCESS) { + WARN("cert file road error.\n"); + result = IO_FAIL; + } else { + + rcar_cert_load = RCAR_CERT_LOAD; + } + (void) io_close(backend_handle); + } + } + } + + return result; +} + +/* Close a connection to the FIP device */ +static int32_t rcar_dev_close(io_dev_info_t *dev_info) +{ + /* TODO: Consider tracking open files and cleaning them up here */ + + /* Clear the backend. */ + backend_dev_handle = (uintptr_t)0; + backend_image_spec = (uintptr_t)0; + + return IO_SUCCESS; +} + + +/* Open a file for access from package. */ +static int32_t rcar_file_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity) +{ + int32_t result; + uint32_t file_offset; + uint32_t noload; + uint32_t cert_addr; + uint32_t l_image_size; + uint32_t dest_addr; + const io_block_spec_t *file_spec = (io_block_spec_t *)spec; + + assert(file_spec != NULL); + assert(entity != NULL); + + /* Can only have one file open at a time for the moment. We need to + * track state like file cursor position. We know the header lives at + * offset zero, so this entry should never be zero for an active file. + * When the system supports dynamic memory allocation we can allow more + * than one open file at a time if needed. + */ + if (current_file.offset_address != 0U) { + WARN("rcar_file_open : Only one open file at a time.\n"); + result = IO_RESOURCES_EXHAUSTED; + } else { + + /* get file offset(but BL33 image id not get) */ + result = file_to_offset(file_spec->offset, + &file_offset, &cert_addr, &noload); + if (result != IO_SUCCESS) { + WARN("Failed to open file name %ld (%i)\n", + file_spec->offset, result); + result = IO_FAIL; + } else { + if (0U != noload) { + current_file.offset_address = 1U; + current_file.dest_address = 0U; + current_file.size = 1U; + current_file.file_pos = 0U; + current_file.is_noload = noload; + entity->info = (uintptr_t) ¤t_file; + + } else { + + /* get image size and destination address */ + get_info_from_cert((uint64_t) cert_addr, + &l_image_size, &dest_addr); + + current_file.offset_address = file_offset; + current_file.dest_address = dest_addr; + current_file.size = l_image_size; + current_file.file_pos = 0U; + current_file.is_noload = noload; + entity->info = (uintptr_t) ¤t_file; + } + } + } + + return result; +} + + +/* Return the size of a file in package */ +static int32_t rcar_file_len(io_entity_t *entity, size_t *length) +{ + assert(entity != NULL); + assert(length != NULL); + + *length = ((file_state_t *)entity->info)->size; + + return IO_SUCCESS; +} + + +/* Read data from a file in package */ +static int32_t rcar_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read) +{ + int32_t result; + file_state_t *fp; + ssize_t file_offset; + size_t bytes_read; + uintptr_t backend_handle; + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_read != NULL); + assert(entity->info != (uintptr_t)NULL); + + /* cert image no load */ + if ( 0U != current_file.is_noload ) { + result = IO_SUCCESS; + *length_read = length; + } else { + + /* Open the backend, attempt to access the blob image */ + result = io_open(backend_dev_handle, backend_image_spec, + &backend_handle); + if (result != IO_SUCCESS) { + WARN("Failed to open FIP (%i)\n", result); + result = IO_FAIL; + } else { + + fp = (file_state_t *) entity->info; + + /* Seek to the position in the FIP where the payload lives */ + file_offset = (ssize_t) fp->offset_address + + (ssize_t) fp->file_pos; + result = io_seek(backend_handle, IO_SEEK_SET, + file_offset); + if (result != IO_SUCCESS) { + WARN("rcar_file_read: failed to seek\n"); + result = IO_FAIL; + } + + if (result == IO_SUCCESS) { + result = io_read(backend_handle, buffer, length, + &bytes_read); + if (result != IO_SUCCESS) { + /* We cannot read our data. Fail. */ + WARN("Failed to read payload (%i)\n", + result); + result = IO_FAIL; + } else { + /* Set caller length and new file position. */ + *length_read = bytes_read; + fp->file_pos += (uint32_t) bytes_read; + } + } + + if ((result == IO_SUCCESS) && (buffer == (uintptr_t)NS_IMAGE_OFFSET)) { + result = load_bl33x(backend_handle); + } + /* Close the backend. */ + (void) io_close(backend_handle); + } + } + + return result; +} + + +/* Close a file in package */ +static int32_t rcar_file_close(io_entity_t *entity) +{ + /* Clear our current file pointer. + * If we had malloc() we would free() here. + */ + assert(entity != NULL); + if (current_file.offset_address != 0U) { + (void)memset(¤t_file, 0, sizeof(current_file)); + } + + /* Clear the Entity info. */ + entity->info = 0U; + + return IO_SUCCESS; +} + +/* Exported functions */ + +/* Register the Firmware Image Package driver with the IO abstraction */ +int32_t register_io_dev_rcar(const io_dev_connector_t **dev_con) +{ + int32_t result; + assert(dev_con != NULL); + + result = io_register_device(&rcar_dev_info); + if (result == IO_SUCCESS) { + *dev_con = &rcar_dev_connector; + } + + return result; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/memdrv/rcar_console.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/memdrv/rcar_console.S new file mode 100644 index 0000000..e8f5c04 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/memdrv/rcar_console.S @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + +/* + * Pull in generic functions to provide backwards compatibility for + * platform makefiles + */ +#include "../../../drivers/console/console.S" + + .globl console_core_init + .globl console_core_putc + .globl console_core_getc + .globl readreg_cntpct_el0 + + .extern rcar_log_init + .extern rcar_set_log_data + + /* ----------------------------------------------- + * int console_core_init(unsigned long base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the log area. This + * function will be accessed by console_init and + * crash reporting. + * Return 1 on SUCCESS, 0 on error + * In: x0 - Not used + * w1 - Not used + * w2 - Not used + * ----------------------------------------------- + */ +func console_core_init + b rcar_log_init +endfunc console_core_init + + /* -------------------------------------------------------- + * int console_core_putc(int c, unsigned long base_addr) + * Function to output a character over the log area. + * Return 1 on SUCCESS, 0 on error + * In : w0 - Not used + * x1 - Not used + * -------------------------------------------------------- + */ +func console_core_putc + b rcar_set_log_data +endfunc console_core_putc + + /* --------------------------------------------- + * int console_core_getc(unsigned long base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * In : x0 - console base address + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_getc + ret +endfunc console_core_getc + + + /* -------------------------------------------- + * uint64_t readreg_cntpct_el0(void) + * Function to read CNTPCT_EL0 register. + * -------------------------------------------- + */ +func readreg_cntpct_el0 + mrs x0, cntpct_el0 + ret +endfunc readreg_cntpct_el0 diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/memdrv/rcar_printf.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/memdrv/rcar_printf.c new file mode 100644 index 0000000..15a4bcf --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/memdrv/rcar_printf.c @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include "../../rcar_def.h" +#include "../../rcar_private.h" +#include "rcar_printf.h" + +extern RCAR_INSTANTIATE_LOCK + +typedef struct log_head +{ + uint8_t head[4]; + uint32_t index; + uint32_t size; + uint8_t res[4]; +} loghead_t; + +typedef struct log_map +{ + loghead_t header; + uint8_t log_data[RCAR_BL31_LOG_MAX]; + uint8_t res_data[RCAR_LOG_RES_SIZE]; +} logmap_t; + +void rcar_set_log_time(void) +{ + uint64_t now_time; + uint64_t freq; + uint64_t second; + uint64_t micro_sec; + uint64_t t_log[2][15]; + int32_t i; + int32_t start_counter; + + now_time = readreg_cntpct_el0(); + freq = read_cntfrq_el0(); /* get the frequency */ + if (freq == 0U) { /* for zero division */ + second = 0U; + micro_sec = 0U; + } else { + second = now_time / freq; + micro_sec = ((now_time % freq) * 1000000U) / freq; + } + i = 14; /* counter initialize */ + do { + t_log[0][i] = second % 10U; + second = second / 10U; + i--; + } while (second != 0U); + start_counter = i + 1; + t_log[1][0] = micro_sec / 100000U; + micro_sec %= 100000U; + t_log[1][1] = micro_sec / 10000U; + micro_sec %= 10000U; + t_log[1][2] = micro_sec / 1000U; + micro_sec %= 1000U; + t_log[1][3] = micro_sec / 100U; + micro_sec %= 100U; + t_log[1][4] = micro_sec / 10U; + t_log[1][5] = micro_sec % 10U; + + (void)putchar((int)'['); + for (i = start_counter; i < 15; i++) { + (void)putchar((int)((int)t_log[0][i] + (int)0x30)); + } + (void)putchar((int)'.'); + for (i = 0; i < 6; i++) { + (void)putchar((int)((int)t_log[1][i] + (int)0x30)); + } + (void)putchar((int)']'); +} + +int32_t rcar_set_log_data(int32_t c) +{ + logmap_t *t_log; + + t_log = (logmap_t *)RCAR_BL31_LOG_BASE; + + rcar_lock_get(); + + /* + * If index is broken, then index and size initialize + */ + if (t_log->header.index >= (uint32_t)RCAR_BL31_LOG_MAX) { + t_log->header.index = 0U; + t_log->header.size = 0U; + } + /* + * data store to log area then index and size renewal + */ + t_log->log_data[t_log->header.index] = (uint8_t)c; + t_log->header.index++; + if (t_log->header.size < t_log->header.index) { + t_log->header.size = t_log->header.index; + } + if (t_log->header.index >= (uint32_t)RCAR_BL31_LOG_MAX) { + t_log->header.index = 0U; + } + + rcar_lock_release(); + + return(1); +} + +int32_t rcar_log_init(void) +{ + + static const uint8_t const_header[] = "TLOG"; + logmap_t *t_log; + int16_t init_flag = 0; + + t_log = (logmap_t *)RCAR_BL31_LOG_BASE; + if (memcmp((const void *)t_log->header.head, (const void *)const_header, sizeof(t_log->header.head)) != 0) { + /* + * Log header is not "TLOG", then log area initialize + */ + init_flag = 1; + } + if (t_log->header.index >= (uint32_t)RCAR_BL31_LOG_MAX) { + /* + * index is broken, then log area initialize + */ + init_flag = 1; + } + if (init_flag == 1) { + (void)memset((void *)t_log->log_data, 0, (size_t)RCAR_BL31_LOG_MAX); + (void)memcpy((void *)t_log->header.head, (const void *)const_header, sizeof(t_log->header.head)); + t_log->header.index = 0U; + t_log->header.size = 0U; + } + rcar_lock_init(); + + return(1); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/memdrv/rcar_printf.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/memdrv/rcar_printf.h new file mode 100644 index 0000000..f9e4e54 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/memdrv/rcar_printf.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_PRINTF_H__ +#define RCAR_PRINTF_H__ + +#include + +void rcar_set_log_time(void); +int32_t rcar_set_log_data(int32_t c); +int32_t rcar_log_init(void); + +extern uint64_t readreg_cntpct_el0(void); + +#endif /* RCAR_PRINTF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/pwrc/rcar_pwrc.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/pwrc/rcar_pwrc.c new file mode 100644 index 0000000..477e0b2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/pwrc/rcar_pwrc.c @@ -0,0 +1,286 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "../../rcar_def.h" +#include "../../rcar_private.h" +#include "rcar_pwrc.h" + +/* + * TODO: Someday there will be a generic power controller api. At the moment + * each platform has its own pwrc so just exporting functions is fine. + */ +RCAR_INSTANTIATE_LOCK + +#define WUP_IRQ_SHIFT (0U) +#define WUP_FIQ_SHIFT (8U) +#define WUP_CSD_SHIFT (16U) + +#define BIT_SOFTRESET ((uint32_t)1U<<15) +#define BIT_CA53_SCU ((uint32_t)1U<<21) +#define BIT_CA57_SCU ((uint32_t)1U<<12) +#define REQ_RESUME ((uint32_t)1U<<1) +#define REQ_OFF ((uint32_t)1U<<0) +#define STATUS_PWRUP ((uint32_t)1U<<1) +#define STATUS_PWRDOWN ((uint32_t)1U<<0) + +#define STATE_CA57_CPU (27U) +#define STATE_CA53_CPU (22U) + +#define STATUS_L2RST ((uint32_t)0U<<4) +#define MODE_L2_DOWN (0x00000002U) +#define CPU_PWR_OFF (0x00000003U) + +#define RCAR_PSTR_MASK (0x00000003U) +#define ST_ALL_STANDBY (0x00003333U) + +static void SCU_power_up(uint64_t mpidr); + +uint32_t rcar_pwrc_status(uint64_t mpidr) +{ + uint32_t rc; + uint64_t cpu_no; + uint32_t prr_data; + + rcar_lock_get(); + prr_data = mmio_read_32((uintptr_t)RCAR_PRR); + cpu_no = mpidr & (uint64_t)MPIDR_CPU_MASK; + if ((mpidr & ((uint64_t)MPIDR_CLUSTER_MASK)) != 0U) { + /* A53 side */ + if ((prr_data & ((uint32_t)1U << (STATE_CA53_CPU + cpu_no))) + == 0U) { + rc = 0U; + } else { + rc = RCAR_INVALID; + } + } else { + /* A57 side */ + if ((prr_data & ((uint32_t)1U << (STATE_CA57_CPU + cpu_no))) + == 0U) { + rc = 0U; + } else { + rc = RCAR_INVALID; + } + } + rcar_lock_release(); + + return rc; +} + +void rcar_pwrc_cpuon(uint64_t mpidr) +{ + + uintptr_t res_reg; + uint32_t res_data; + uintptr_t on_reg; + uint64_t cpu_no; + uint32_t upper_value; + uint32_t wup_data; + + rcar_lock_get(); + + cpu_no = mpidr & (uint64_t)MPIDR_CPU_MASK; + if ((mpidr & ((uint64_t)MPIDR_CLUSTER_MASK)) != 0U) { + /* A53 side */ + res_reg = (uintptr_t)RCAR_CA53RESCNT; + on_reg = (uintptr_t)RCAR_CA53WUPCR; + upper_value = 0x5A5A0000U; + } else { + /* A57 side */ + res_reg = (uintptr_t)RCAR_CA57RESCNT; + on_reg = (uintptr_t)RCAR_CA57WUPCR; + upper_value = 0xA5A50000U; + } + res_data = mmio_read_32(res_reg) | upper_value; + /* Assert to CPU reset */ + mmio_write_32(res_reg, (res_data | ((uint32_t)1U << (3U - cpu_no)))); + SCU_power_up(mpidr); + wup_data = (uint32_t)((uint32_t)1U << cpu_no); + do { + mmio_write_32(RCAR_CPGWPR, ~wup_data); + mmio_write_32(on_reg, wup_data); + } while ((mmio_read_32(on_reg) & wup_data) == 0U); + /* Dessert to CPU reset */ + mmio_write_32(res_reg, (res_data & (~((uint32_t)1U << (3U - cpu_no))))); + rcar_lock_release(); +} + +static void SCU_power_up(uint64_t mpidr) +{ + uint32_t reg_SYSC_bit; + uintptr_t reg_PWRONCR; + volatile uintptr_t reg_PWRER; + uintptr_t reg_PWRSR; + uintptr_t reg_CPUCMCR; + uintptr_t reg_SYSCIER = (uintptr_t)RCAR_SYSCIER; + uintptr_t reg_SYSCIMR = (uintptr_t)RCAR_SYSCIMR; + volatile uintptr_t reg_SYSCSR = (volatile uintptr_t)RCAR_SYSCSR; + volatile uintptr_t reg_SYSCISR = (volatile uintptr_t)RCAR_SYSCISR; + volatile uintptr_t reg_SYSCISCR = (volatile uintptr_t)RCAR_SYSCISCR; + + if ((mpidr & ((uint64_t)MPIDR_CLUSTER_MASK)) == 0U) { + /* CA57-SCU */ + reg_SYSC_bit = (uint32_t)BIT_CA57_SCU; + reg_PWRONCR = (uintptr_t)RCAR_PWRONCR5; + reg_PWRER = (volatile uintptr_t)RCAR_PWRER5; + reg_PWRSR = (uintptr_t)RCAR_PWRSR5; + reg_CPUCMCR = (uintptr_t)RCAR_CA57CPUCMCR; + } else { + /* CA53-SCU */ + reg_SYSC_bit = (uint32_t)BIT_CA53_SCU; + reg_PWRONCR = (uintptr_t)RCAR_PWRONCR3; + reg_PWRER = (volatile uintptr_t)RCAR_PWRER3; + reg_PWRSR = (uintptr_t)RCAR_PWRSR3; + reg_CPUCMCR = (uintptr_t)RCAR_CA53CPUCMCR; + } + if ((mmio_read_32(reg_PWRSR) & (uint32_t)STATUS_PWRDOWN) != 0x0000U) { + if (mmio_read_32(reg_CPUCMCR) != 0U) { + mmio_write_32(reg_CPUCMCR, (uint32_t)0x00000000U); + } + /* set SYSCIER and SYSCIMR */ + mmio_write_32(reg_SYSCIER, + (mmio_read_32(reg_SYSCIER) | reg_SYSC_bit)); + mmio_write_32(reg_SYSCIMR, + (mmio_read_32(reg_SYSCIMR) | reg_SYSC_bit)); + do { + /* SYSCSR[1]=1? */ + while ((mmio_read_32(reg_SYSCSR) & (uint32_t)REQ_RESUME) + == 0U) { + ; + } + /* If SYSCSR[1]=1 then set bit in PWRONCRn to 1 */ + mmio_write_32(reg_PWRONCR, 0x0001U); + } while ((mmio_read_32(reg_PWRER) & 0x0001U) != 0U); + + /* bit in SYSCISR=1 ? */ + while ((mmio_read_32(reg_SYSCISR) & reg_SYSC_bit) == 0U) { + ; + } + /* clear bit in SYSCISR */ + mmio_write_32(reg_SYSCISCR, reg_SYSC_bit); + } +} + +void rcar_pwrc_cpuoff(uint64_t mpidr) +{ + uintptr_t off_reg; + uint64_t cpu_no; + + rcar_lock_get(); + cpu_no = mpidr & (uint64_t)MPIDR_CPU_MASK; + if ((mpidr & ((uint64_t)MPIDR_CLUSTER_MASK)) != 0U) { + /* A53 side */ + off_reg = (uintptr_t)RCAR_CA53CPU0CR; + } else { + /* A57 side */ + off_reg = (uintptr_t)RCAR_CA57CPU0CR; + } + if (read_mpidr_el1() == mpidr) { + mmio_write_32(RCAR_CPGWPR, ~((uint32_t)CPU_PWR_OFF)); + mmio_write_32(off_reg + (cpu_no * 0x0010U), + (uint32_t)CPU_PWR_OFF); + } else { + panic(); + } + rcar_lock_release(); +} + +void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr) +{ + uintptr_t reg; + uint64_t cpu_no; + uint32_t shift_irq; + uint32_t shift_fiq; + + rcar_lock_get(); + cpu_no = mpidr & (uint64_t)MPIDR_CPU_MASK; + if ((mpidr & ((uint64_t)MPIDR_CLUSTER_MASK)) != 0U) { + /* A53 side */ + reg = (uintptr_t)RCAR_WUPMSKCA53; + } else { + /* A57 side */ + reg = (uintptr_t)RCAR_WUPMSKCA57; + } + shift_irq = WUP_IRQ_SHIFT + (uint32_t)cpu_no; + shift_fiq = WUP_FIQ_SHIFT + (uint32_t)cpu_no; + mmio_write_32(reg, (uint32_t)((~((uint32_t)1U << shift_irq)) + & (~((uint32_t)1U << shift_fiq)))); + rcar_lock_release(); +} + +void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr) +{ + uintptr_t reg; + uint64_t cpu_no; + uint32_t shift_irq; + uint32_t shift_fiq; + + rcar_lock_get(); + cpu_no = mpidr & (uint64_t)MPIDR_CPU_MASK; + if ((mpidr & ((uint64_t)MPIDR_CLUSTER_MASK)) != 0U) { + /* A53 side */ + reg = (uintptr_t)RCAR_WUPMSKCA53; + } else { + /* A57 side */ + reg = (uintptr_t)RCAR_WUPMSKCA57; + } + shift_irq = WUP_IRQ_SHIFT + (uint32_t)cpu_no; + shift_fiq = WUP_FIQ_SHIFT + (uint32_t)cpu_no; + mmio_write_32(reg, (uint32_t)(((uint32_t)1U << shift_irq) + | ((uint32_t)1U << shift_fiq))); + rcar_lock_release(); +} + +void rcar_pwrc_clusteroff(uint64_t mpidr) +{ + uint64_t target_core; + uintptr_t reg_CPUCMCR; + + rcar_lock_get(); + target_core = mpidr & ((uint64_t)MPIDR_CLUSTER_MASK); + if (target_core == 0U) { + reg_CPUCMCR = (uintptr_t)RCAR_CA57CPUCMCR; + } else { + reg_CPUCMCR = (uintptr_t)RCAR_CA53CPUCMCR; + } + /* all of the CPUs in the cluster is in the CoreStandby mode */ + mmio_write_32(reg_CPUCMCR, (uint32_t)(STATUS_L2RST | MODE_L2_DOWN)); + rcar_lock_release(); +} + +/* Nothing else to do here apart from initializing the lock */ +void rcar_pwrc_setup(void) +{ + rcar_lock_init(); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/pwrc/rcar_pwrc.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/pwrc/rcar_pwrc.h new file mode 100644 index 0000000..4366ec7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/pwrc/rcar_pwrc.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_PWRC_H__ +#define RCAR_PWRC_H__ + +/* RCAR Power controller register offset etc */ +#define PPOFFR_OFF 0x0 +#define PPONR_OFF 0x4 +#define PCOFFR_OFF 0x8 +#define PWKUPR_OFF 0xc +#define PSYSR_OFF 0x10 + +#define PWKUPR_WEN (1ull << 31) + +#define PSYSR_AFF_L2 (1 << 31) +#define PSYSR_AFF_L1 (1 << 30) +#define PSYSR_AFF_L0 (1 << 29) +#define PSYSR_WEN (1 << 28) +#define PSYSR_PC (1 << 27) +#define PSYSR_PP (1 << 26) + +#define PSYSR_WK_SHIFT (24) +#define PSYSR_WK_MASK (0x3) +#define PSYSR_WK(x) (((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK) + +#define WKUP_COLD 0x0 +#define WKUP_RESET 0x1 +#define WKUP_PPONR 0x2 +#define WKUP_GICREQ 0x3 + +#define RCAR_INVALID (0xffffffffU) +#define PSYSR_INVALID 0xffffffff + +#ifndef __ASSEMBLY__ + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void rcar_pwrc_setup(void); +void rcar_pwrc_clusteroff(uint64_t mpidr); +void rcar_pwrc_cpuoff(uint64_t mpidr); +void rcar_pwrc_cpuon(uint64_t mpidr); +void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr); +void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr); +uint32_t rcar_pwrc_status(uint64_t mpidr); +uint32_t rcar_pwrc_get_cpu_wkr(uint64_t mpidr); + +#endif /*__ASSEMBLY__*/ + +#endif /* RCAR_PWRC_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/rpc/rpc_driver.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/rpc/rpc_driver.c new file mode 100644 index 0000000..1c92ea6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/rpc/rpc_driver.c @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "bl2_cpg_register.h" +#include "bl2_cpg_init.h" +#include "bl2_rpc_register.h" +#include "rpc_driver.h" +#include "debug.h" + +static void enableRPC(void); +static void setupRPC(void); +#if DEBUG +static void disableRPC(void); +#endif + +static void enableRPC(void) +{ + while((mmio_read_32(CPG_MSTPSR9) & 0x00020000U) != 0U) { + cpg_write(CPG_SMSTPCR9, + mmio_read_32(CPG_SMSTPCR9) & (~0x00020000U)); + } +} + +static void setupRPC(void) +{ + /* manual mode */ + if ((mmio_read_32(RPC_CMNCR) & 0x80000000U) != 0U) { + /* external address space read mode */ + mmio_write_32(RPC_CMNCR, + mmio_read_32(RPC_CMNCR) & (~0x80000000U)); + } +} + +#if DEBUG +static void disableRPC(void) +{ + cpg_write(CPG_SMSTPCR9, + mmio_read_32(CPG_SMSTPCR9) | 0x00020000U); +} +#endif + +void initRPC(void) +{ + enableRPC(); + setupRPC(); +} + +#if DEBUG +void termRPC(void) +{ + disableRPC(); +} +#endif diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/scif/scif.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/scif/scif.S new file mode 100644 index 0000000..0db30cd --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/scif/scif.S @@ -0,0 +1,323 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "scif.h" + +/* Product Register */ +#define PRR (0xFFF00044) +#define PRR_PRODUCT_MASK (0x00007FFF) +#define PRR_PRODUCT_H3_ES_1_0 (0x00004F00) /* R-Car H3 ES1.0 */ + +/* module stop */ +#define CPG_BASE (0xE6150000) +#define CPG_SMSTPCR3 (0x013C) +#define MSTP310 (1 << 10) +#define MSTP207 (1 << 7) +#define CPG_CPGWPR (0x0900) +#define CPG_MSTPSR2 (0x0040) +#define CPG_RMSTPCR2 (0x0118) + +/* SCIF_BASE */ +#define SCIF0_BASE (0xE6E60000) /* SCIF-0 base address */ +/* SCIF2 */ +#define SCIF2_BASE (0xE6E88000) /* SCIF-2 base address */ + +#define SCIF_SCSMR (0x00) /* Serial mode register */ +#define SCIF_SCBRR (0x04) /* Bit rate register */ +#define SCIF_SCSCR (0x08) /* Serial control register */ +#define SCIF_SCFTDR (0x0C) /* Transmit FIFO data register */ +#define SCIF_SCFSR (0x10) /* Serial status register */ +#define SCIF_SCFRDR (0x14) /* Receive FIFO data register */ +#define SCIF_SCFCR (0x18) /* FIFO control register */ +#define SCIF_SCFDR (0x1C) /* FIFO data count register */ +#define SCIF_SCSPTR (0x20) /* Serial port register */ +#define SCIF_SCLSR (0x24) /* Line status register */ +#define SCIF_DL (0x30) /* Frequency division register */ +#define SCIF_CKS (0x34) /* Clock Select register */ +#define SCIF_SCSMRIR (0x40) /* Serial mode register */ + + +#define SCSMR_CA_MASK (1 << 7) +#define SCSMR_CA_ASYNC (0x0000) +#define SCSMR_CHR_MASK (1 << 6) +#define SCSMR_CHR_8 (0x0000) +#define SCSMR_PE_MASK (1 << 5) +#define SCSMR_PE_DIS (0x0000) +#define SCSMR_STOP_MASK (1 << 3) +#define SCSMR_STOP_1 (0x0000) +#define SCSMR_CKS_MASK (3 << 0) +#define SCSMR_CKS_DIV1 (0x0000) +#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + SCSMR_CHR_8 + \ + SCSMR_PE_DIS + SCSMR_STOP_1 + \ + SCSMR_CKS_DIV1) + +#define SCBRR_115200BPS (17) /* 115200bps@66MHz */ +#define SCBRR_230400BPS (8) /* 230400bps@66MHz */ + +#define SCSCR_TE_MASK (1 << 5) +#define SCSCR_TE_DIS (0x0000) +#define SCSCR_TE_EN (0x0020) +#define SCSCR_RE_MASK (1 << 4) +#define SCSCR_RE_DIS (0x0000) +#define SCSCR_RE_EN (0x0010) +#define SCSCR_CKE_MASK (3 << 0) +#define SCSCR_CKE_INT (0x0000) +#define SCSCR_CKE_BRG (0x0002) +#if SCIF_CLK == SCIF_EXTARNAL_CLK +#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG) +#else +#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT) +#endif + +#define SCFSR_INIT_DATA (0x0000) + +#define SCFCR_TTRG_MASK (3 << 4) +#define SCFCR_TTRG_8 (0x0000) +#define SCFCR_TTRG_0 (0x0030) +#define SCFCR_TFRST_MASK (1 << 2) +#define SCFCR_TFRST_DIS (0x0000) +#define SCFCR_TFRST_EN (0x0004) +#define SCFCR_RFRS_MASK (1 << 1) +#define SCFCR_RFRS_DIS (0x0000) +#define SCFCR_RFRS_EN (0x0002) +#define SCFCR_INIT_DATA (SCFCR_TTRG_8) + +#define SCFDR_T_MASK (0x1f << 8) + +#define DL_INIT_DATA (8) /* 14.7456MHz/(115200bps*16)*/ + +#define CKS_CKS_DIV_MASK (1 << 15) +#define CKS_CKS_DIV_CLK (0x0000) +#define CKS_XIN_MASK (1 << 14) +#define CKS_XIN_SCIF_CLK (0x0000) +#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK) + + .globl console_init + .globl console_putc + .globl console_core_init + .globl console_core_putc + .globl console_getc + .globl console_finalize + + /* + * The console base is in the data section and not in .bss + * even though it is zero-init. In particular, this allows + * the console functions to start using this variable before + * the runtime memory is initialized for images which do not + * need to copy the .data section from ROM to RAM. + */ + /* ----------------------------------------------- + * int console_init(unsigned long base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. It saves + * the console base to the data section. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * out: return 1 on success. + * Clobber list : x1 - x3 + * ----------------------------------------------- + */ +func console_init + b console_core_init +endfunc console_init + + /* ----------------------------------------------- + * int console_core_init(unsigned long base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * Out: return 1 on success + * Clobber list : x1, x2 + * ----------------------------------------------- + */ +func console_core_init + ldr x0, =CPG_BASE + + ldr w1, [x0, #CPG_RMSTPCR2] + and w1, w1, #~MSTP207 /* MSTP207=0 */ + mvn w2, w1 + str w2, [x0, #CPG_CPGWPR] + str w1, [x0, #CPG_RMSTPCR2] +4: + ldr w1, [x0, #CPG_MSTPSR2] + and w1, w1, #MSTP207 + cmp w1, #0 + bne 4b + ldr x0, =SCIF0_BASE + mov w1, #0 + strh w1, [x0, #SCIF_SCSMRIR] + /* Clear bits TE and RE in SCSCR to 0 */ + mov w1, #(SCSCR_TE_DIS + SCSCR_RE_DIS) /* TE=0,RE=0 */ + strh w1, [x0, #SCIF_SCSCR] + /* Set bits TFRST and RFRST in SCFCR to 1 */ + ldrh w1, [x0, #SCIF_SCFCR] + orr w1, w1, #(SCFCR_TFRST_EN + SCFCR_RFRS_EN) /* TFRESET=1,RFRESET=1 */ + strh w1, [x0, #SCIF_SCFCR] + /* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER in SCLSR, then clear them to 0 */ + mov w1, #SCFSR_INIT_DATA + strh w1, [x0, #SCIF_SCFSR] + mov w1, #0 + strh w1, [x0, #SCIF_SCLSR] + /* Set bits CKE[1:0] in SCSCR */ + ldrh w1, [x0, #SCIF_SCSCR] + and w1, w1, #~SCSCR_CKE_MASK + mov w2, #SCSCR_CKE_INT_CLK /* CKE=00 */ + orr w1, w1, w2 + strh w1, [x0, #SCIF_SCSCR] + /* Set data transfer format in SCSMR */ + mov w1, #SCSMR_INIT_DATA + strh w1, [x0, #SCIF_SCSMR] /* CA=0,CHR=0,PE=0,STOP=0,CKS=P */ + /* Set value in SCBRR */ +#if SCIF_CLK == SCIF_INTERNAL_CLK + ldr x1, =PRR + ldr w1, [x1] + and w1, w1, #PRR_PRODUCT_MASK + mov w2, #PRR_PRODUCT_H3_ES_1_0 + cmp w1, w2 + beq 3f + mov w1, #SCBRR_115200BPS /* 115200bps */ + b 2f +3: + mov w1, #SCBRR_230400BPS /* H3 ES1.0 sets clock to doubling */ +2: + strb w1, [x0, #SCIF_SCBRR] +#else + mov w1, #DL_INIT_DATA + strh w1, [x0, #SCIF_DL] + mov w1, #CKS_INIT_DATA /* CKS=0,XIN=0 */ + strh w1, [x0, #SCIF_CKS] +#endif + /* 1-bit interval elapsed */ + mov w1, #100 /* 100 times */ +1: + subs w1, w1, #1 + cbnz w1, 1b + /* Set bits RTRG[1:0], TTRG[1:0], and MCE in SCFCR, and clear bits FRST and RFRST to 0 */ + mov w1, #SCFCR_INIT_DATA + strh w1, [x0, #SCIF_SCFCR] + /* Set bits TE and RE in SCSCR to 1 */ + ldrh w1, [x0, #SCIF_SCSCR] + orr w1, w1, #(SCSCR_TE_EN + SCSCR_RE_EN) /* TE=1,RE=1 */ + strh w1, [x0, #SCIF_SCSCR] + mov x1, #1 + + ret +endfunc console_core_init + + /* --------------------------------------------- + * int console_putc(int c) + * Function to output a character over the + * console. It returns the character printed on + * success or -1 on error. + * In : x0 - character to be printed + * Out : return -1 on error else return character. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func console_putc + b console_core_putc +endfunc console_putc + + /* -------------------------------------------------------- + * int console_core_putc(int c, unsigned int base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_core_putc + ldr x1, =SCIF0_BASE + cmp w0, #0xA + /* Prepend '\r' to '\n' */ + bne 2f +1: + /* Check if the transmit FIFO is full */ + ldrh w2, [x1, #SCIF_SCFDR] + ubfx w2, w2, #8, #5 + cmp w2, #16 + bcs 1b + mov w2, #0x0D + strb w2, [x1, #SCIF_SCFTDR] +2: + /* Check if the transmit FIFO is full */ + ldrh w2, [x1, #SCIF_SCFDR] + ubfx w2, w2, #8, #5 + cmp w2, #16 + bcs 2b + strb w0, [x1, #SCIF_SCFTDR] + + ret +endfunc console_core_putc + + /* --------------------------------------------- + * int console_getc(void) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_getc + mov w0, #-1 /* no support */ + ret +endfunc console_getc + + /* ----------------------------------------------- + * void console_finalize(void) + * ----------------------------------------------- + */ +func console_finalize + ldr x0, =SCIF0_BASE +1: + ldrh w1, [x0, #SCIF_SCFDR] + ubfx w1, w1, #8, #5 + cmp w1, #0 + bne 1b + + ldrh w1, [x0, #SCIF_SCSCR] + and w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN) /* TE=0,RE=0 */ + strh w1, [x0, #SCIF_SCSCR] + + ret +endfunc console_finalize + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/timer/bl2_swdt.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/timer/bl2_swdt.c new file mode 100644 index 0000000..4c2d310 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/drivers/timer/bl2_swdt.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "bl2_swdt.h" +#include "../../rcar_def.h" + +#define RST_BASE (0xE6160000U) +#define RST_WDTRSTCR (RST_BASE + 0x0054U) +#define SWDT_BASE (0xE6030000U) +#define SWDT_WTCNT (SWDT_BASE + 0x0000U) +#define SWDT_WTCSRA (SWDT_BASE + 0x0004U) +#define SWDT_WTCSRB (SWDT_BASE + 0x0008U) +#define SWDT_GICD_BASE (0xF1010000U) +#define SWDT_GICC_BASE (0xF1020000U) +#define SWDT_GICD_CTLR (SWDT_GICD_BASE + 0x0000U) +#define SWDT_GICD_IGROUPR (SWDT_GICD_BASE + 0x0080U) +#define SWDT_GICD_ISPRIORITYR (SWDT_GICD_BASE + 0x0400U) +#define SWDT_GICC_CTLR (SWDT_GICC_BASE + 0x0000U) +#define SWDT_GICC_PMR (SWDT_GICC_BASE + 0x0004U) +#define SWDT_GICD_ITARGETSR (SWDT_GICD_BASE + 0x0800U) +#define IGROUPR_NUM (16U) +#define ISPRIORITY_NUM (128U) +#define ITARGET_MASK ((uint32_t)0x03U) + +#define WDTRSTCR_UPPER_BYTE (0xA55A0000U) +#define WTCSRA_UPPER_BYTE (0xA5A5A500U) +#define WTCSRB_UPPER_BYTE (0xA5A5A500U) +#define WTCNT_UPPER_BYTE (0x5A5A0000U) +#define WTCNT_RESET_VALUE (0xF488U) +#define WTCSRA_BIT_CKS (0x0007U) +#define WTCSRB_BIT_CKS (0x003FU) +#define SWDT_RSTMSK ((uint32_t)1U << 1) +#define WTCSRA_WOVFE ((uint32_t)1U << 3) +#define WTCSRA_WRFLG ((uint32_t)1U << 5) +#define SWDT_ENABLE ((uint32_t)1U << 7) + +#define WDTRSTCR_MASK_ALL (0x0000FFFFU) +#define WTCSRA_MASK_ALL (0x000000FFU) +#define WTCNT_INIT_DATA (WTCNT_UPPER_BYTE + WTCNT_RESET_VALUE) +#define WTCSRA_INIT_DATA (WTCSRA_UPPER_BYTE + 0x0FU) +#define WTCSRB_INIT_DATA (WTCSRB_UPPER_BYTE + 0x21U) + +#define WTCNT_COUNT_8p13k (0x10000U - 40687U) +#define WTCNT_COUNT_8p13k_H3ES1p0 (0x10000U - 20343U) +#define WTCNT_COUNT_8p22k (0x10000U - 41115U) +#define WTCSRA_CKS_DIV16 (0x00000002U) + +#define CHECK_MD13_MD14 (0x6000U) +#define FREQ_10p0M (0x2000U) +#define FREQ_12p5M (0x4000U) +#define FREQ_8p33M (0x0000U) +#define FREQ_16p66M (0x6000U) + +static void bl2_swdt_disable(void); + +void bl2_swdt_init(void) +{ + uint32_t sr; + uint32_t rmsk; + uint32_t product_cut = mmio_read_32((uintptr_t)RCAR_PRR) + & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); + uint32_t chk_data = mmio_read_32((uintptr_t)RCAR_MODEMR) + & CHECK_MD13_MD14; + + if ((mmio_read_32(SWDT_WTCSRA) & SWDT_ENABLE) != 0U) { + /* Stop SWDT */ + mmio_write_32(SWDT_WTCSRA,WTCSRA_UPPER_BYTE); + } + + /* clock is OSC/16 and overflow interrupt is enabled */ + mmio_write_32(SWDT_WTCSRA,(WTCSRA_UPPER_BYTE | WTCSRA_WOVFE + | WTCSRA_CKS_DIV16)); + + /* Set the overflow counter */ + switch (chk_data) { + case FREQ_8p33M: /* MD13=0 and MD14=0 */ + case FREQ_12p5M: /* MD13=0 and MD14=1 */ + /* OSCCLK=130.2kHz count=40687, set 0x5A5A6111 */ + mmio_write_32(SWDT_WTCNT,(WTCNT_UPPER_BYTE | WTCNT_COUNT_8p13k)); + break; + case FREQ_10p0M: /* MD13=1 and MD14=0 */ + /* OSCCLK=131.57kHz count=41115, set 0x5A5A5F65 */ + mmio_write_32(SWDT_WTCNT,(WTCNT_UPPER_BYTE | WTCNT_COUNT_8p22k)); + break; + case FREQ_16p66M: /* MD13=1 and MD14=1 */ + /* OSCCLK=130.2kHz */ + if (product_cut==(RCAR_PRODUCT_H3 | RCAR_CUT_ES10)) { + /* R-car H3 ES1.0 */ + /* count=20343, set 0x5A5AB089 */ + mmio_write_32(SWDT_WTCNT,(WTCNT_UPPER_BYTE | WTCNT_COUNT_8p13k_H3ES1p0)); + } else { + /* count=40687, set 0x5A5A6111 */ + mmio_write_32(SWDT_WTCNT,(WTCNT_UPPER_BYTE | WTCNT_COUNT_8p13k)); + } + break; + default: + /* Error */ + ERROR("BL2: MODEMR ERROR value=%x\n", chk_data); + panic(); + break; + } + + rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL; + mmio_write_32(RST_WDTRSTCR,(WDTRSTCR_UPPER_BYTE + | (rmsk | SWDT_RSTMSK))); + while ((mmio_read_8(SWDT_WTCSRA) & WTCSRA_WRFLG) != 0U) { + /* Wait until the WTCNT is reflected */ + ; + } + sr = mmio_read_32(SWDT_WTCSRA) & WTCSRA_MASK_ALL; + /* Start the System WatchDog Timer */ + mmio_write_32(SWDT_WTCSRA,(WTCSRA_UPPER_BYTE | sr | SWDT_ENABLE)); +} + +static void bl2_swdt_disable(void) +{ + uint32_t rmsk; + uintptr_t base = (uintptr_t)RCAR_GICD_BASE; + uint32_t id = (uint32_t)ARM_IRQ_SEC_WDT; + + /* Initialize the HW initial data, but SWDT is not moved */ + rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL; + mmio_write_32(RST_WDTRSTCR,(WDTRSTCR_UPPER_BYTE + | (rmsk | SWDT_RSTMSK))); + mmio_write_32(SWDT_WTCNT,WTCNT_INIT_DATA); + mmio_write_32(SWDT_WTCSRA,WTCSRA_INIT_DATA); + mmio_write_32(SWDT_WTCSRB,WTCSRB_INIT_DATA); + /* Set the interrupt clear enable register */ + gicd_set_icenabler(base, id); +} + +void bl2_swdt_release(void) +{ + uintptr_t p_gicd_ctlr = (uintptr_t)SWDT_GICD_CTLR; + uintptr_t p_igroupr = (uintptr_t)SWDT_GICD_IGROUPR; + uintptr_t p_ispriorityr = (uintptr_t)SWDT_GICD_ISPRIORITYR; + uintptr_t p_gicc_ctlr = (uintptr_t)SWDT_GICC_CTLR; + uintptr_t p_pmr = (uintptr_t)SWDT_GICC_PMR; + uintptr_t p_itargetsr = (uintptr_t)(SWDT_GICD_ITARGETSR + + (ARM_IRQ_SEC_WDT & (uint32_t)(~ITARGET_MASK))); + uint32_t i; + + bl2_swdt_disable(); + disable_fiq(); + arm_gic_cpuif_deactivate(); + for (i=0U; i + +#if 0 /* for QAC */ +#ifndef DEBUG +#define DEBUG 0 +#endif +#endif /* for QAC */ + +void initDMA(void); +void execDMA(uint32_t dst, uint32_t src, uint32_t len); +#if DEBUG +void termDMA(void); +#endif + +#endif /* DMA_DRIVER_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/io_common.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/io_common.h new file mode 100644 index 0000000..1619ad2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/io_common.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014 ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef IO_COMMON_H__ +#define IO_COMMON_H__ + +extern void rcar_io_setup (void); +extern int plat_get_image_source(unsigned int image_id, + uintptr_t *dev_handle, + uintptr_t *image_spec); + + +#endif /* IO_COMMON_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/io_memdrv.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/io_memdrv.h new file mode 100644 index 0000000..4eafa5e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/io_memdrv.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef IO_MEMDRV_H__ +#define IO_MEMDRV_H__ + +struct io_dev_connector; + +int32_t register_io_dev_memdrv(const io_dev_connector_t **dev_con); + +#endif /* IO_MEMDRV_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/io_rcar.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/io_rcar.h new file mode 100644 index 0000000..b176112 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/io_rcar.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2014 ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef IO_RCAR_H__ +#define IO_RCAR_H__ + +int32_t register_io_dev_rcar(const io_dev_connector_t **dev_con); +int32_t file_to_cert(const int32_t filename, uint32_t *cert_addr); +void get_info_from_cert(uint64_t cert_addr, uint32_t *size, uint32_t *dest_addr); + +#endif /* IO_FIP_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/pfc_init.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/pfc_init.h new file mode 100644 index 0000000..a8c982e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/pfc_init.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef PFC_INIT_H__ +#define PFC_INIT_H__ + +void pfc_init(void); + +#endif /* PFC_INIT_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/plat_macros.S b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/plat_macros.S new file mode 100644 index 0000000..4db1bc3 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/plat_macros.S @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include "../rcar_def.h" + +.section .rodata.gic_reg_name, "aS" +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL3-1. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_print_gic_regs + mov_imm x17, RCAR_GICC_BASE_A + mov_imm x16, RCAR_GICD_BASE_A +print_gicc_regs: + /* gicc base address is now in x17 */ + adr x6, gicc_regs /* Load the gicc reg list to x6 */ + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + adr x4, spacer + bl asm_print_str + ldr x4, [x7], #8 + bl asm_print_hex + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + .endm + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* ------------------------------------------------ + * The below macro prints out relevant interconnect + * registers whenever an unhandled exception is + * taken in BL3-1. + * Clobbers: x0 - x9, sp + * ------------------------------------------------ + */ + .macro plat_print_interconnect_regs + adr x6, cci_iface_regs + /* Store in x7 the base address of the first interface */ + mov_imm x7, (CCI500_BASE + SLAVE_IFACE3_OFFSET) + ldr w8, [x7, #SNOOP_CTRL_REG] + /* Store in x7 the base address of the second interface */ + mov_imm x7, (CCI500_BASE + SLAVE_IFACE4_OFFSET) + ldr w9, [x7, #SNOOP_CTRL_REG] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + .endm diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/platform.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/platform.h new file mode 100644 index 0000000..f4c6019 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/platform.h @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_PLATFORM_H__ +#define RCAR_PLATFORM_H__ + +#include + + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct plat_pm_ops; +struct meminfo; +struct image_info; +struct entry_point_info; +struct bl31_params; + +/******************************************************************************* + * Function declarations + ******************************************************************************/ +/******************************************************************************* + * Mandatory common functions + ******************************************************************************/ +uint64_t plat_get_syscnt_freq(void); +int plat_get_image_source(const char *image_name, + uintptr_t *dev_handle, + uintptr_t *image_spec); +unsigned long plat_get_ns_image_entrypoint(void); + +/******************************************************************************* + * Mandatory interrupt management functions + ******************************************************************************/ +uint32_t plat_ic_get_pending_interrupt_id(void); +uint32_t plat_ic_get_pending_interrupt_type(void); +uint32_t plat_ic_acknowledge_interrupt(void); +uint32_t plat_ic_get_interrupt_type(uint32_t id); +void plat_ic_end_of_interrupt(uint32_t id); +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state); + +/******************************************************************************* + * Optional common functions (may be overridden) + ******************************************************************************/ +unsigned int platform_get_core_pos(unsigned long mpidr); +unsigned long platform_get_stack(unsigned long mpidr); +void plat_report_exception(unsigned long); +int plat_crash_console_init(void); +int plat_crash_console_putc(int c); + +/******************************************************************************* + * Mandatory BL1 functions + ******************************************************************************/ +void bl1_early_platform_setup(void); +void bl1_plat_arch_setup(void); +void bl1_platform_setup(void); +struct meminfo *bl1_plat_sec_mem_layout(void); + +/* + * This function allows the platform to change the entrypoint information for + * BL2, after BL1 has loaded BL2 into memory but before BL2 is executed. + */ +void bl1_plat_set_bl2_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/******************************************************************************* + * Optional BL1 functions (may be overridden) + ******************************************************************************/ +void bl1_init_bl2_mem_layout(const struct meminfo *bl1_mem_layout, + struct meminfo *bl2_mem_layout); + +/******************************************************************************* + * Mandatory BL2 functions + ******************************************************************************/ +void bl2_early_platform_setup(struct meminfo *mem_layout); +void bl2_plat_arch_setup(void); +void bl2_platform_setup(void); +struct meminfo *bl2_plat_sec_mem_layout(void); + +/* + * This function returns a pointer to the shared memory that the platform has + * kept aside to pass trusted firmware related information that BL3-1 + * could need + */ +struct bl31_params *bl2_plat_get_bl31_params(void); + +/* + * This function returns a pointer to the shared memory that the platform + * has kept to point to entry point information of BL31 to BL2 + */ +struct entry_point_info *bl2_plat_get_bl31_ep_info(void); + +/* + * This function flushes to main memory all the params that are + * passed to BL3-1 + */ +void bl2_plat_flush_bl31_params(void); + +/* + * The next 2 functions allow the platform to change the entrypoint information + * for the mandatory 3rd level BL images, BL3-1 and BL3-3. This is done after + * BL2 has loaded those images into memory but before BL3-1 is executed. + */ +void bl2_plat_set_bl31_ep_info(struct image_info *image, + struct entry_point_info *ep); + +void bl2_plat_set_bl33_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* Gets the memory layout for BL3-3 */ +void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); + +/******************************************************************************* + * Conditionally mandatory BL2 functions: must be implemented if BL3-0 image + * is supported + ******************************************************************************/ +/* Gets the memory layout for BL3-0 */ +void bl2_plat_get_bl30_meminfo(struct meminfo *mem_info); + +/* + * This function is called after loading BL3-0 image and it is used to perform + * any platform-specific actions required to handle the SCP firmware. + */ +int bl2_plat_handle_bl30(struct image_info *bl30_image_info); + +/******************************************************************************* + * Conditionally mandatory BL2 functions: must be implemented if BL3-2 image + * is supported + ******************************************************************************/ +void bl2_plat_set_bl32_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* Gets the memory layout for BL3-2 */ +void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); + +/******************************************************************************* + * Optional BL2 functions (may be overridden) + ******************************************************************************/ + +/******************************************************************************* + * Mandatory BL3-1 functions + ******************************************************************************/ +void bl31_early_platform_setup(struct bl31_params *from_bl2, + void *plat_params_from_bl2); +void bl31_plat_arch_setup(void); +void bl31_platform_setup(void); +struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type); + +/******************************************************************************* + * Mandatory PSCI functions (BL3-1) + ******************************************************************************/ +int platform_setup_pm(const struct plat_pm_ops **); +unsigned int plat_get_aff_count(unsigned int, unsigned long); +unsigned int plat_get_aff_state(unsigned int, unsigned long); + +/******************************************************************************* + * Optional BL3-1 functions (may be overridden) + ******************************************************************************/ +void bl31_plat_enable_mmu(uint32_t flags); + +/******************************************************************************* + * Optional BL3-2 functions (may be overridden) + ******************************************************************************/ +void bl32_plat_enable_mmu(uint32_t flags); + +/******************************************************************************* + * Mandatory BL3-1 functions + ******************************************************************************/ +void bl33_early_platform_setup(void); +void bl33_plat_arch_setup(void); +void bl33_platform_setup(void); + +/******************************************************************************* + * Trusted Boot functions + ******************************************************************************/ +int plat_match_rotpk(const unsigned char *, unsigned int); + +#endif /* RCAR_PLATFORM_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/platform_def.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/platform_def.h new file mode 100644 index 0000000..559435d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/platform_def.h @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_PLATFORM_DEF_H__ +#define RCAR_PLATFORM_DEF_H__ + +#include +#ifndef __ASSEMBLY__ +#include +#endif +#include "../rcar_def.h" + + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Align the storing version code for BL2 and BL31 */ +#define ALIGN_VERSION (0x400) + +/* Size of cacheable stacks */ +#if IMAGE_BL1 +#if TRUSTED_BOARD_BOOT +#define PLATFORM_STACK_SIZE 0x1000 +#else +#define PLATFORM_STACK_SIZE 0x440 +#endif +#elif IMAGE_BL2 +#if TRUSTED_BOARD_BOOT +#define PLATFORM_STACK_SIZE 0x1000 +#else +#define PLATFORM_STACK_SIZE 0x400 +#endif +#elif IMAGE_BL31 +#define PLATFORM_STACK_SIZE 0x400 +#elif IMAGE_BL32 +#define PLATFORM_STACK_SIZE 0x440 +#elif IMAGE_BL33 +#define PLATFORM_STACK_SIZE 0x440 +#endif + +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" + +#define BL332_IMAGE_ID (BL33_CERT_ID + 1U) +#define BL333_IMAGE_ID (BL33_CERT_ID + 2U) +#define BL334_IMAGE_ID (BL33_CERT_ID + 3U) +#define BL335_IMAGE_ID (BL33_CERT_ID + 4U) +#define BL336_IMAGE_ID (BL33_CERT_ID + 5U) +#define BL337_IMAGE_ID (BL33_CERT_ID + 6U) +#define BL338_IMAGE_ID (BL33_CERT_ID + 7U) + +#define BL332_KEY_CERT_ID (BL33_CERT_ID + 8U) +#define BL333_KEY_CERT_ID (BL33_CERT_ID + 9U) +#define BL334_KEY_CERT_ID (BL33_CERT_ID + 10U) +#define BL335_KEY_CERT_ID (BL33_CERT_ID + 11U) +#define BL336_KEY_CERT_ID (BL33_CERT_ID + 12U) +#define BL337_KEY_CERT_ID (BL33_CERT_ID + 13U) +#define BL338_KEY_CERT_ID (BL33_CERT_ID + 14U) + +#define BL332_CERT_ID (BL33_CERT_ID + 15U) +#define BL333_CERT_ID (BL33_CERT_ID + 16U) +#define BL334_CERT_ID (BL33_CERT_ID + 17U) +#define BL335_CERT_ID (BL33_CERT_ID + 18U) +#define BL336_CERT_ID (BL33_CERT_ID + 19U) +#define BL337_CERT_ID (BL33_CERT_ID + 20U) +#define BL338_CERT_ID (BL33_CERT_ID + 21U) + +/* + * R-Car H3 Cortex-A57 + * L1:I/48KB(16KBx3way) D/32KB(16KBx2way) L2:2MB(128KBx16way) + * Cortex-A53 + * L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way) + */ +#define PLATFORM_CACHE_LINE_SIZE 128 +#define PLATFORM_CLUSTER_COUNT 2ull +#define PLATFORM_CLUSTER0_CORE_COUNT 4 +#define PLATFORM_CLUSTER1_CORE_COUNT 4 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ + PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) +#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1 +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +/******************************************************************************* + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + ******************************************************************************/ +#define BL1_RO_BASE RCAR_TRUSTED_ROM_BASE +#define BL1_RO_LIMIT (RCAR_TRUSTED_ROM_BASE \ + + RCAR_TRUSTED_ROM_SIZE) +/* + * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using + * the current BL1 RW debug size plus a little space for growth. + */ +#if TRUSTED_BOARD_BOOT +#define BL1_RW_BASE (RCAR_TRUSTED_SRAM_BASE \ + + RCAR_TRUSTED_SRAM_SIZE - 0x8000) +#else +#define BL1_RW_BASE (RCAR_TRUSTED_SRAM_BASE \ + + RCAR_TRUSTED_SRAM_SIZE - 0x6000) +#endif +#define BL1_RW_LIMIT (RCAR_TRUSTED_SRAM_BASE \ + + RCAR_TRUSTED_SRAM_SIZE) + +/******************************************************************************* + * BL2 specific defines. + ******************************************************************************/ +/* + * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug + * size plus a little space for growth. + */ +#define RCAR_SECRAM_BASE (0xE6300000) +#define BL2_BASE (0xE6302000) +#define BL2_LIMIT (0xE632E800) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the + * current BL3-1 debug size plus a little space for growth. + */ +#define BL31_BASE (RCAR_TRUSTED_SRAM_BASE) +#define BL31_LIMIT (RCAR_TRUSTED_SRAM_BASE \ + + RCAR_TRUSTED_SRAM_SIZE) +#define RCAR_BL31_LOG_BASE (0x44040000) +#define RCAR_BL31_SDRAM_BTM (RCAR_BL31_LOG_BASE + 0x14000) +#define RCAR_BL31_LOG_SIZE (RCAR_BL31_SDRAM_BTM \ + - RCAR_BL31_LOG_BASE) + +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ + +# define BL32_BASE (0x44100000) +# define BL32_LIMIT (BL32_BASE + 0x100000) +/* + * ID of the secure physical generic timer interrupt used by the TSP. + */ + + +/******************************************************************************* + * BL3-3 specific defines. + ******************************************************************************/ +#define BL33_BASE (0x48000000) +#define BL33_LIMIT (BL33_BASE + (256 * 1024)) + + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define ADDR_SPACE_SIZE (1ull << 32) + +#if IMAGE_BL1 +# define MAX_XLAT_TABLES 2 +#elif IMAGE_BL2 +# define MAX_XLAT_TABLES 3 +#elif IMAGE_BL31 +# define MAX_XLAT_TABLES 4 +#elif IMAGE_BL32 +# define MAX_XLAT_TABLES 3 +#elif IMAGE_BL33 +# define MAX_XLAT_TABLES 3 +#endif + +#define MAX_MMAP_REGIONS (RCAR_MMAP_ENTRIES + RCAR_BL_REGIONS) + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#if !USE_COHERENT_MEM +/******************************************************************************* + * Size of the per-cpu data in bytes that should be reserved in the generic + * per-cpu data structure for the RCAR port. + ******************************************************************************/ +#define PLAT_PCPU_DATA_SIZE 2 +#endif + +#endif /* RCAR_PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/rpc_driver.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/rpc_driver.h new file mode 100644 index 0000000..0089504 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/rpc_driver.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RPC_DRIVER_H__ +#define RPC_DRIVER_H__ + +#if 0 /* for QAC */ +#ifndef DEBUG +#define DEBUG 0 +#endif +#endif /* for QAC */ + +void initRPC(void); +#if DEBUG +void termRPC(void); +#endif + +#endif /* RPC_DRIVER_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/scif.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/scif.h new file mode 100644 index 0000000..fe1fb25 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/include/scif.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef SCIF_H__ +#define SCIF_H__ + + +#define SCIF_INTERNAL_CLK 0 /* Internal clock(S3D4:66.66MHz) */ +#define SCIF_EXTARNAL_CLK 1 /* External clock(SCK2:14.7456MHz) */ +#define SCIF_CLK SCIF_INTERNAL_CLK + + +#ifndef __ASSEMBLY__ + +void console_finalize(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* SCIF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/H3/pfc_init_h3.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/H3/pfc_init_h3.c new file mode 100644 index 0000000..fc3160c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/H3/pfc_init_h3.c @@ -0,0 +1,1352 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include /* for uint32_t */ +#include +#include "pfc_init_h3.h" + + +/* GPIO base address */ +#define GPIO_BASE (0xE6050000U) + +/* GPIO registers */ +#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U) +#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U) +#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U) +#define GPIO_INDT0 (GPIO_BASE + 0x000CU) +#define GPIO_INTDT0 (GPIO_BASE + 0x0010U) +#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U) +#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U) +#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU) +#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U) +#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U) +#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U) +#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U) +#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU) +#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U) +#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U) +#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U) +#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU) +#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U) +#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U) +#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U) +#define GPIO_INDT1 (GPIO_BASE + 0x100CU) +#define GPIO_INTDT1 (GPIO_BASE + 0x1010U) +#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U) +#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U) +#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU) +#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U) +#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U) +#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U) +#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U) +#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU) +#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U) +#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U) +#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U) +#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU) +#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U) +#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U) +#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U) +#define GPIO_INDT2 (GPIO_BASE + 0x200CU) +#define GPIO_INTDT2 (GPIO_BASE + 0x2010U) +#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U) +#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U) +#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU) +#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U) +#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U) +#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U) +#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U) +#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU) +#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U) +#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U) +#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U) +#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU) +#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U) +#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U) +#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U) +#define GPIO_INDT3 (GPIO_BASE + 0x300CU) +#define GPIO_INTDT3 (GPIO_BASE + 0x3010U) +#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U) +#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U) +#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU) +#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U) +#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U) +#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U) +#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U) +#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU) +#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U) +#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U) +#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U) +#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU) +#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U) +#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U) +#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U) +#define GPIO_INDT4 (GPIO_BASE + 0x400CU) +#define GPIO_INTDT4 (GPIO_BASE + 0x4010U) +#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U) +#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U) +#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU) +#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U) +#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U) +#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U) +#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U) +#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU) +#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U) +#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U) +#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U) +#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU) +#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U) +#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U) +#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U) +#define GPIO_INDT5 (GPIO_BASE + 0x500CU) +#define GPIO_INTDT5 (GPIO_BASE + 0x5010U) +#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U) +#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U) +#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU) +#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U) +#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U) +#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U) +#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U) +#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU) +#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U) +#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U) +#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U) +#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU) +#define GPIO_IOINTSEL6 (GPIO_BASE + 0x5400U) +#define GPIO_INOUTSEL6 (GPIO_BASE + 0x5404U) +#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U) +#define GPIO_INDT6 (GPIO_BASE + 0x540CU) +#define GPIO_INTDT6 (GPIO_BASE + 0x5410U) +#define GPIO_INTCLR6 (GPIO_BASE + 0x5414U) +#define GPIO_INTMSK6 (GPIO_BASE + 0x5418U) +#define GPIO_MSKCLR6 (GPIO_BASE + 0x541CU) +#define GPIO_POSNEG6 (GPIO_BASE + 0x5420U) +#define GPIO_EDGLEVEL6 (GPIO_BASE + 0x5424U) +#define GPIO_FILONOFF6 (GPIO_BASE + 0x5428U) +#define GPIO_INTMSKS6 (GPIO_BASE + 0x5438U) +#define GPIO_MSKCLRS6 (GPIO_BASE + 0x543CU) +#define GPIO_OUTDTSEL6 (GPIO_BASE + 0x5440U) +#define GPIO_OUTDTH6 (GPIO_BASE + 0x5444U) +#define GPIO_OUTDTL6 (GPIO_BASE + 0x5448U) +#define GPIO_BOTHEDGE6 (GPIO_BASE + 0x544CU) +#define GPIO_IOINTSEL7 (GPIO_BASE + 0x5800U) +#define GPIO_INOUTSEL7 (GPIO_BASE + 0x5804U) +#define GPIO_OUTDT7 (GPIO_BASE + 0x5808U) +#define GPIO_INDT7 (GPIO_BASE + 0x580CU) +#define GPIO_INTDT7 (GPIO_BASE + 0x5810U) +#define GPIO_INTCLR7 (GPIO_BASE + 0x5814U) +#define GPIO_INTMSK7 (GPIO_BASE + 0x5818U) +#define GPIO_MSKCLR7 (GPIO_BASE + 0x581CU) +#define GPIO_POSNEG7 (GPIO_BASE + 0x5820U) +#define GPIO_EDGLEVEL7 (GPIO_BASE + 0x5824U) +#define GPIO_FILONOFF7 (GPIO_BASE + 0x5828U) +#define GPIO_INTMSKS7 (GPIO_BASE + 0x5838U) +#define GPIO_MSKCLRS7 (GPIO_BASE + 0x583CU) +#define GPIO_OUTDTSEL7 (GPIO_BASE + 0x5840U) +#define GPIO_OUTDTH7 (GPIO_BASE + 0x5844U) +#define GPIO_OUTDTL7 (GPIO_BASE + 0x5848U) +#define GPIO_BOTHEDGE7 (GPIO_BASE + 0x584CU) + + +/* Pin functon base address */ +#define PFC_BASE (0xE6060000U) + +/* Pin functon registers */ +#define PFC_PMMR (PFC_BASE + 0x0000U) +#define PFC_GPSR0 (PFC_BASE + 0x0100U) +#define PFC_GPSR1 (PFC_BASE + 0x0104U) +#define PFC_GPSR2 (PFC_BASE + 0x0108U) +#define PFC_GPSR3 (PFC_BASE + 0x010CU) +#define PFC_GPSR4 (PFC_BASE + 0x0110U) +#define PFC_GPSR5 (PFC_BASE + 0x0114U) +#define PFC_GPSR6 (PFC_BASE + 0x0118U) +#define PFC_GPSR7 (PFC_BASE + 0x011CU) +#define PFC_IPSR0 (PFC_BASE + 0x0200U) +#define PFC_IPSR1 (PFC_BASE + 0x0204U) +#define PFC_IPSR2 (PFC_BASE + 0x0208U) +#define PFC_IPSR3 (PFC_BASE + 0x020CU) +#define PFC_IPSR4 (PFC_BASE + 0x0210U) +#define PFC_IPSR5 (PFC_BASE + 0x0214U) +#define PFC_IPSR6 (PFC_BASE + 0x0218U) +#define PFC_IPSR7 (PFC_BASE + 0x021CU) +#define PFC_IPSR8 (PFC_BASE + 0x0220U) +#define PFC_IPSR9 (PFC_BASE + 0x0224U) +#define PFC_IPSR10 (PFC_BASE + 0x0228U) +#define PFC_IPSR11 (PFC_BASE + 0x022CU) +#define PFC_IPSR12 (PFC_BASE + 0x0230U) +#define PFC_IPSR13 (PFC_BASE + 0x0234U) +#define PFC_IPSR14 (PFC_BASE + 0x0238U) +#define PFC_IPSR15 (PFC_BASE + 0x023CU) +#define PFC_IPSR16 (PFC_BASE + 0x0240U) +#define PFC_IPSR17 (PFC_BASE + 0x0244U) +#define PFC_DRVCTRL0 (PFC_BASE + 0x0300U) +#define PFC_DRVCTRL1 (PFC_BASE + 0x0304U) +#define PFC_DRVCTRL2 (PFC_BASE + 0x0308U) +#define PFC_DRVCTRL3 (PFC_BASE + 0x030CU) +#define PFC_DRVCTRL4 (PFC_BASE + 0x0310U) +#define PFC_DRVCTRL5 (PFC_BASE + 0x0314U) +#define PFC_DRVCTRL6 (PFC_BASE + 0x0318U) +#define PFC_DRVCTRL7 (PFC_BASE + 0x031CU) +#define PFC_DRVCTRL8 (PFC_BASE + 0x0320U) +#define PFC_DRVCTRL9 (PFC_BASE + 0x0324U) +#define PFC_DRVCTRL10 (PFC_BASE + 0x0328U) +#define PFC_DRVCTRL11 (PFC_BASE + 0x032CU) +#define PFC_DRVCTRL12 (PFC_BASE + 0x0330U) +#define PFC_DRVCTRL13 (PFC_BASE + 0x0334U) +#define PFC_DRVCTRL14 (PFC_BASE + 0x0338U) +#define PFC_DRVCTRL15 (PFC_BASE + 0x033CU) +#define PFC_DRVCTRL16 (PFC_BASE + 0x0340U) +#define PFC_DRVCTRL17 (PFC_BASE + 0x0344U) +#define PFC_DRVCTRL18 (PFC_BASE + 0x0348U) +#define PFC_DRVCTRL19 (PFC_BASE + 0x034CU) +#define PFC_DRVCTRL20 (PFC_BASE + 0x0350U) +#define PFC_DRVCTRL21 (PFC_BASE + 0x0354U) +#define PFC_DRVCTRL22 (PFC_BASE + 0x0358U) +#define PFC_DRVCTRL23 (PFC_BASE + 0x035CU) +#define PFC_DRVCTRL24 (PFC_BASE + 0x0360U) +#define PFC_POCCTRL0 (PFC_BASE + 0x0380U) +#define PFC_TDSELCTRL0 (PFC_BASE + 0x03C0U) +#define PFC_IOCTRL (PFC_BASE + 0x03E0U) +#define PFC_TSREG (PFC_BASE + 0x03E4U) +#define PFC_PUEN0 (PFC_BASE + 0x0400U) +#define PFC_PUEN1 (PFC_BASE + 0x0404U) +#define PFC_PUEN2 (PFC_BASE + 0x0408U) +#define PFC_PUEN3 (PFC_BASE + 0x040CU) +#define PFC_PUEN4 (PFC_BASE + 0x0410U) +#define PFC_PUEN5 (PFC_BASE + 0x0414U) +#define PFC_PUEN6 (PFC_BASE + 0x0418U) +#define PFC_PUD0 (PFC_BASE + 0x0440U) +#define PFC_PUD1 (PFC_BASE + 0x0444U) +#define PFC_PUD2 (PFC_BASE + 0x0448U) +#define PFC_PUD3 (PFC_BASE + 0x044CU) +#define PFC_PUD4 (PFC_BASE + 0x0450U) +#define PFC_PUD5 (PFC_BASE + 0x0454U) +#define PFC_PUD6 (PFC_BASE + 0x0458U) +#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U) +#define PFC_MOD_SEL1 (PFC_BASE + 0x0504U) +#define PFC_MOD_SEL2 (PFC_BASE + 0x0508U) + +#define GPSR0_D15 ((uint32_t)1U << 15U) +#define GPSR0_D14 ((uint32_t)1U << 14U) +#define GPSR0_D13 ((uint32_t)1U << 13U) +#define GPSR0_D12 ((uint32_t)1U << 12U) +#define GPSR0_D11 ((uint32_t)1U << 11U) +#define GPSR0_D10 ((uint32_t)1U << 10U) +#define GPSR0_D9 ((uint32_t)1U << 9U) +#define GPSR0_D8 ((uint32_t)1U << 8U) +#define GPSR0_D7 ((uint32_t)1U << 7U) +#define GPSR0_D6 ((uint32_t)1U << 6U) +#define GPSR0_D5 ((uint32_t)1U << 5U) +#define GPSR0_D4 ((uint32_t)1U << 4U) +#define GPSR0_D3 ((uint32_t)1U << 3U) +#define GPSR0_D2 ((uint32_t)1U << 2U) +#define GPSR0_D1 ((uint32_t)1U << 1U) +#define GPSR0_D0 ((uint32_t)1U << 0U) +#define GPSR1_EX_WAIT0_A ((uint32_t)1U << 27U) +#define GPSR1_WE1 ((uint32_t)1U << 26U) +#define GPSR1_WE0 ((uint32_t)1U << 25U) +#define GPSR1_RD_WR ((uint32_t)1U << 24U) +#define GPSR1_RD ((uint32_t)1U << 23U) +#define GPSR1_BS ((uint32_t)1U << 22U) +#define GPSR1_CS1_A26 ((uint32_t)1U << 21U) +#define GPSR1_CS0 ((uint32_t)1U << 20U) +#define GPSR1_A19 ((uint32_t)1U << 19U) +#define GPSR1_A18 ((uint32_t)1U << 18U) +#define GPSR1_A17 ((uint32_t)1U << 17U) +#define GPSR1_A16 ((uint32_t)1U << 16U) +#define GPSR1_A15 ((uint32_t)1U << 15U) +#define GPSR1_A14 ((uint32_t)1U << 14U) +#define GPSR1_A13 ((uint32_t)1U << 13U) +#define GPSR1_A12 ((uint32_t)1U << 12U) +#define GPSR1_A11 ((uint32_t)1U << 11U) +#define GPSR1_A10 ((uint32_t)1U << 10U) +#define GPSR1_A9 ((uint32_t)1U << 9U) +#define GPSR1_A8 ((uint32_t)1U << 8U) +#define GPSR1_A7 ((uint32_t)1U << 7U) +#define GPSR1_A6 ((uint32_t)1U << 6U) +#define GPSR1_A5 ((uint32_t)1U << 5U) +#define GPSR1_A4 ((uint32_t)1U << 4U) +#define GPSR1_A3 ((uint32_t)1U << 3U) +#define GPSR1_A2 ((uint32_t)1U << 2U) +#define GPSR1_A1 ((uint32_t)1U << 1U) +#define GPSR1_A0 ((uint32_t)1U << 0U) +#define GPSR2_AVB_AVTP_CAPTURE_A ((uint32_t)1U << 14U) +#define GPSR2_AVB_AVTP_MATCH_A ((uint32_t)1U << 13U) +#define GPSR2_AVB_LINK ((uint32_t)1U << 12U) +#define GPSR2_AVB_PHY_INT ((uint32_t)1U << 11U) +#define GPSR2_AVB_MAGIC ((uint32_t)1U << 10U) +#define GPSR2_AVB_MDC ((uint32_t)1U << 9U) +#define GPSR2_PWM2_A ((uint32_t)1U << 8U) +#define GPSR2_PWM1_A ((uint32_t)1U << 7U) +#define GPSR2_PWM0 ((uint32_t)1U << 6U) +#define GPSR2_IRQ5 ((uint32_t)1U << 5U) +#define GPSR2_IRQ4 ((uint32_t)1U << 4U) +#define GPSR2_IRQ3 ((uint32_t)1U << 3U) +#define GPSR2_IRQ2 ((uint32_t)1U << 2U) +#define GPSR2_IRQ1 ((uint32_t)1U << 1U) +#define GPSR2_IRQ0 ((uint32_t)1U << 0U) +#define GPSR3_SD1_WP ((uint32_t)1U << 15U) +#define GPSR3_SD1_CD ((uint32_t)1U << 14U) +#define GPSR3_SD0_WP ((uint32_t)1U << 13U) +#define GPSR3_SD0_CD ((uint32_t)1U << 12U) +#define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U) +#define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U) +#define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U) +#define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U) +#define GPSR3_SD1_CMD ((uint32_t)1U << 7U) +#define GPSR3_SD1_CLK ((uint32_t)1U << 6U) +#define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U) +#define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U) +#define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U) +#define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U) +#define GPSR3_SD0_CMD ((uint32_t)1U << 1U) +#define GPSR3_SD0_CLK ((uint32_t)1U << 0U) +#define GPSR4_SD3_DS ((uint32_t)1U << 17U) +#define GPSR4_SD3_DAT7 ((uint32_t)1U << 16U) +#define GPSR4_SD3_DAT6 ((uint32_t)1U << 15U) +#define GPSR4_SD3_DAT5 ((uint32_t)1U << 14U) +#define GPSR4_SD3_DAT4 ((uint32_t)1U << 13U) +#define GPSR4_SD3_DAT3 ((uint32_t)1U << 12U) +#define GPSR4_SD3_DAT2 ((uint32_t)1U << 11U) +#define GPSR4_SD3_DAT1 ((uint32_t)1U << 10U) +#define GPSR4_SD3_DAT0 ((uint32_t)1U << 9U) +#define GPSR4_SD3_CMD ((uint32_t)1U << 8U) +#define GPSR4_SD3_CLK ((uint32_t)1U << 7U) +#define GPSR4_SD2_DS ((uint32_t)1U << 6U) +#define GPSR4_SD2_DAT3 ((uint32_t)1U << 5U) +#define GPSR4_SD2_DAT2 ((uint32_t)1U << 4U) +#define GPSR4_SD2_DAT1 ((uint32_t)1U << 3U) +#define GPSR4_SD2_DAT0 ((uint32_t)1U << 2U) +#define GPSR4_SD2_CMD ((uint32_t)1U << 1U) +#define GPSR4_SD2_CLK ((uint32_t)1U << 0U) +#define GPSR5_MLB_DAT ((uint32_t)1U << 25U) +#define GPSR5_MLB_SIG ((uint32_t)1U << 24U) +#define GPSR5_MLB_CLK ((uint32_t)1U << 23U) +#define GPSR5_MSIOF0_RXD ((uint32_t)1U << 22U) +#define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 21U) +#define GPSR5_MSIOF0_TXD ((uint32_t)1U << 20U) +#define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 19U) +#define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 18U) +#define GPSR5_MSIOF0_SCK ((uint32_t)1U << 17U) +#define GPSR5_HRTS0 ((uint32_t)1U << 16U) +#define GPSR5_HCTS0 ((uint32_t)1U << 15U) +#define GPSR5_HTX0 ((uint32_t)1U << 14U) +#define GPSR5_HRX0 ((uint32_t)1U << 13U) +#define GPSR5_HSCK0 ((uint32_t)1U << 12U) +#define GPSR5_RX2_A ((uint32_t)1U << 11U) +#define GPSR5_TX2_A ((uint32_t)1U << 10U) +#define GPSR5_SCK2 ((uint32_t)1U << 9U) +#define GPSR5_RTS1_TANS ((uint32_t)1U << 8U) +#define GPSR5_CTS1 ((uint32_t)1U << 7U) +#define GPSR5_TX1_A ((uint32_t)1U << 6U) +#define GPSR5_RX1_A ((uint32_t)1U << 5U) +#define GPSR5_RTS0_TANS ((uint32_t)1U << 4U) +#define GPSR5_CTS0 ((uint32_t)1U << 3U) +#define GPSR5_TX0 ((uint32_t)1U << 2U) +#define GPSR5_RX0 ((uint32_t)1U << 1U) +#define GPSR5_SCK0 ((uint32_t)1U << 0U) +#define GPSR6_USB31_OVC ((uint32_t)1U << 31U) +#define GPSR6_USB31_PWEN ((uint32_t)1U << 30U) +#define GPSR6_USB30_OVC ((uint32_t)1U << 29U) +#define GPSR6_USB30_PWEN ((uint32_t)1U << 28U) +#define GPSR6_USB1_OVC ((uint32_t)1U << 27U) +#define GPSR6_USB1_PWEN ((uint32_t)1U << 26U) +#define GPSR6_USB0_OVC ((uint32_t)1U << 25U) +#define GPSR6_USB0_PWEN ((uint32_t)1U << 24U) +#define GPSR6_AUDIO_CLKB_B ((uint32_t)1U << 23U) +#define GPSR6_AUDIO_CLKA_A ((uint32_t)1U << 22U) +#define GPSR6_SSI_SDATA9_A ((uint32_t)1U << 21U) +#define GPSR6_SSI_SDATA8 ((uint32_t)1U << 20U) +#define GPSR6_SSI_SDATA7 ((uint32_t)1U << 19U) +#define GPSR6_SSI_WS78 ((uint32_t)1U << 18U) +#define GPSR6_SSI_SCK78 ((uint32_t)1U << 17U) +#define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U) +#define GPSR6_SSI_WS6 ((uint32_t)1U << 15U) +#define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U) +#define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U) +#define GPSR6_SSI_WS5 ((uint32_t)1U << 12U) +#define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U) +#define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U) +#define GPSR6_SSI_WS4 ((uint32_t)1U << 9U) +#define GPSR6_SSI_SCK4 ((uint32_t)1U << 8U) +#define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U) +#define GPSR6_SSI_WS34 ((uint32_t)1U << 6U) +#define GPSR6_SSI_SCK34 ((uint32_t)1U << 5U) +#define GPSR6_SSI_SDATA2_A ((uint32_t)1U << 4U) +#define GPSR6_SSI_SDATA1_A ((uint32_t)1U << 3U) +#define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U) +#define GPSR6_SSI_WS0129 ((uint32_t)1U << 1U) +#define GPSR6_SSI_SCK0129 ((uint32_t)1U << 0U) +#define GPSR7_HDMI1_CEC ((uint32_t)1U << 3U) +#define GPSR7_HDMI0_CEC ((uint32_t)1U << 2U) +#define GPSR7_AVS2 ((uint32_t)1U << 1U) +#define GPSR7_AVS1 ((uint32_t)1U << 0U) + +#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) +#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) +#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) +#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) +#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) +#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) +#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) +#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) + +#define POC_SD3_DS_33V ((uint32_t)1U << 29U) +#define POC_SD3_DAT7_33V ((uint32_t)1U << 28U) +#define POC_SD3_DAT6_33V ((uint32_t)1U << 27U) +#define POC_SD3_DAT5_33V ((uint32_t)1U << 26U) +#define POC_SD3_DAT4_33V ((uint32_t)1U << 25U) +#define POC_SD3_DAT3_33V ((uint32_t)1U << 24U) +#define POC_SD3_DAT2_33V ((uint32_t)1U << 23U) +#define POC_SD3_DAT1_33V ((uint32_t)1U << 22U) +#define POC_SD3_DAT0_33V ((uint32_t)1U << 21U) +#define POC_SD3_CMD_33V ((uint32_t)1U << 20U) +#define POC_SD3_CLK_33V ((uint32_t)1U << 19U) +#define POC_SD2_DS_33V ((uint32_t)1U << 18U) +#define POC_SD2_DAT3_33V ((uint32_t)1U << 17U) +#define POC_SD2_DAT2_33V ((uint32_t)1U << 16U) +#define POC_SD2_DAT1_33V ((uint32_t)1U << 15U) +#define POC_SD2_DAT0_33V ((uint32_t)1U << 14U) +#define POC_SD2_CMD_33V ((uint32_t)1U << 13U) +#define POC_SD2_CLK_33V ((uint32_t)1U << 12U) +#define POC_SD1_DAT3_33V ((uint32_t)1U << 11U) +#define POC_SD1_DAT2_33V ((uint32_t)1U << 10U) +#define POC_SD1_DAT1_33V ((uint32_t)1U << 9U) +#define POC_SD1_DAT0_33V ((uint32_t)1U << 8U) +#define POC_SD1_CMD_33V ((uint32_t)1U << 7U) +#define POC_SD1_CLK_33V ((uint32_t)1U << 6U) +#define POC_SD0_DAT3_33V ((uint32_t)1U << 5U) +#define POC_SD0_DAT2_33V ((uint32_t)1U << 4U) +#define POC_SD0_DAT1_33V ((uint32_t)1U << 3U) +#define POC_SD0_DAT0_33V ((uint32_t)1U << 2U) +#define POC_SD0_CMD_33V ((uint32_t)1U << 1U) +#define POC_SD0_CLK_33V ((uint32_t)1U << 0U) + +#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) +#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U) +#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U) +#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U) +#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U) +#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) +#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U) +#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U) +#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U) +#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U) +#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U) +#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U) +#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U) +#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U) +#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U) +#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U) +#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U) +#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U) +#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U) +#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U) +#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U) +#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U) +#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U) +#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U) +#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U) +#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U) +#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U) +#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U) +#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U) +#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U) +#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U) +#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U) +#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U) +#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U) +#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U) +#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U) +#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) +#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) +#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U) +#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U) +#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U) +#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U) +#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U) +#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U) +#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U) +#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U) +#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U) +#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U) +#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U) +#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U) +#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U) +#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U) +#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U) +#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U) +#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U) +#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U) +#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U) +#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U) +#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U) +#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U) +#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U) +#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U) +#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U) +#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U) +#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U) +#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U) +#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U) +#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U) +#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U) +#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U) +#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U) +#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U) +#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U) +#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U) +#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U) +#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U) +#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U) +#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U) +#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U) +#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U) +#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U) +#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U) +#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U) +#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U) +#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U) +#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U) +#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U) +#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U) +#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U) +#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U) +#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U) +#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U) +#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U) +#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U) +#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U) +#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U) +#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U) +#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U) +#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U) +#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U) +#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U) +#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U) +#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U) +#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U) +#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U) +#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U) +#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U) +#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U) +#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U) +#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U) +#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U) +#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U) +#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U) +#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U) +#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U) +#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U) +#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U) +#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U) +#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U) +#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U) +#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U) +#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U) +#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U) +#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U) +#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U) +#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U) +#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U) +#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U) +#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U) +#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U) +#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U) +#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U) +#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U) +#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U) +#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U) +#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U) +#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U) +#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U) +#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U) +#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U) +#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U) +#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U) +#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U) +#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U) +#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U) +#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U) +#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U) +#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U) +#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U) +#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U) +#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U) +#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U) +#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U) +#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U) +#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U) +#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U) +#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U) +#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U) +#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U) +#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U) +#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U) +#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U) +#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U) +#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U) +#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U) +#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U) +#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U) +#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U) +#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U) +#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U) +#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U) +#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U) +#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U) +#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U) +#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U) +#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U) +#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U) +#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U) + +#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U) +#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U) +#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U) +#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U) +#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U) +#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U) +#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U) +#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U) +#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U) +#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U) +#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U) +#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U) +#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U) +#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U) +#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U) +#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U) +#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U) +#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U) +#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U) +#define MOD_SEL0_I2C6_A ((uint32_t)0U << 20U) +#define MOD_SEL0_I2C6_B ((uint32_t)1U << 20U) +#define MOD_SEL0_I2C6_C ((uint32_t)2U << 20U) +#define MOD_SEL0_I2C2_A ((uint32_t)0U << 19U) +#define MOD_SEL0_I2C2_B ((uint32_t)1U << 19U) +#define MOD_SEL0_I2C1_A ((uint32_t)0U << 18U) +#define MOD_SEL0_I2C1_B ((uint32_t)1U << 18U) +#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 17U) +#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 17U) +#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 15U) +#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 15U) +#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 15U) +#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 15U) +#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 14U) +#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 14U) +#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 13U) +#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 13U) +#define MOD_SEL0_FSO_A ((uint32_t)0U << 12U) +#define MOD_SEL0_FSO_B ((uint32_t)1U << 12U) +#define MOD_SEL0_FM_A ((uint32_t)0U << 11U) +#define MOD_SEL0_FM_B ((uint32_t)1U << 11U) +#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 10U) +#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 10U) +#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 9U) +#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 9U) +#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 8U) +#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 8U) +#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 6U) +#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 6U) +#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 6U) +#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 4U) +#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 4U) +#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 4U) +#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 3U) +#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 3U) +#define MOD_SEL0_ADG_A ((uint32_t)0U << 1U) +#define MOD_SEL0_ADG_B ((uint32_t)1U << 1U) +#define MOD_SEL0_ADG_C ((uint32_t)2U << 1U) +#define MOD_SEL0_ADG_D ((uint32_t)3U << 1U) +#define MOD_SEL0_5LINE_A ((uint32_t)0U << 0U) +#define MOD_SEL0_5LINE_B ((uint32_t)1U << 0U) +#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U) +#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U) +#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U) +#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U) +#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U) +#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U) +#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U) +#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U) +#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U) +#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U) +#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U) +#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U) +#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U) +#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U) +#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U) +#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U) +#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U) +#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U) +#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U) +#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U) +#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U) +#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U) +#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U) +#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U) +#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U) +#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U) +#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U) +#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U) +#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U) +#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U) +#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U) +#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U) +#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U) +#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U) +#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U) +#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U) +#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U) +#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U) +#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U) +#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U) +#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U) +#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U) +#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U) +#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U) +#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U) +#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U) +#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U) +#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U) +#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U) +#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U) +#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U) +#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U) +#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U) +#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U) +#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U) +#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U) +#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U) +#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U) +#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U) +#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U) +#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U) +#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U) +#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U) +#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U) +#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U) + + +static void pfc_reg_write(uint32_t addr, uint32_t data); + +static void pfc_reg_write(uint32_t addr, uint32_t data) +{ + mmio_write_32(PFC_PMMR, ~data); + mmio_write_32((uintptr_t)addr, data); +} + + +void pfc_init_h3(void) +{ + /* initialize module select */ + pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A + | MOD_SEL0_MSIOF2_A + | MOD_SEL0_MSIOF1_A + | MOD_SEL0_LBSC_A + | MOD_SEL0_IEBUS_A + | MOD_SEL0_I2C6_A + | MOD_SEL0_I2C2_A + | MOD_SEL0_I2C1_A + | MOD_SEL0_HSCIF4_A + | MOD_SEL0_HSCIF3_A + | MOD_SEL0_HSCIF2_A + | MOD_SEL0_HSCIF1_A + | MOD_SEL0_FM_A + | MOD_SEL0_ETHERAVB_A + | MOD_SEL0_DRIF3_A + | MOD_SEL0_DRIF2_A + | MOD_SEL0_DRIF1_A + | MOD_SEL0_DRIF0_A + | MOD_SEL0_CANFD0_A + | MOD_SEL0_ADG_A + | MOD_SEL0_5LINE_A); + pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A + | MOD_SEL1_TSIF0_A + | MOD_SEL1_TIMER_TMU_A + | MOD_SEL1_SSP1_1_A + | MOD_SEL1_SSP1_0_A + | MOD_SEL1_SSI_A + | MOD_SEL1_SPEED_PULSE_IF_A + | MOD_SEL1_SIMCARD_A + | MOD_SEL1_SDHI2_A + | MOD_SEL1_SCIF4_A + | MOD_SEL1_SCIF3_A + | MOD_SEL1_SCIF2_A + | MOD_SEL1_SCIF1_A + | MOD_SEL1_SCIF_A + | MOD_SEL1_REMOCON_A + | MOD_SEL1_RCAN0_A + | MOD_SEL1_PWM6_A + | MOD_SEL1_PWM5_A + | MOD_SEL1_PWM4_A + | MOD_SEL1_PWM3_A + | MOD_SEL1_PWM2_A + | MOD_SEL1_PWM1_A); + pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A + | MOD_SEL2_I2C_3_A + | MOD_SEL2_I2C_0_A + | MOD_SEL2_VIN4_A); + + /* initialize peripheral function select */ + pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(3) + | IPSR_8_FUNC(3) + | IPSR_4_FUNC(3) + | IPSR_0_FUNC(3)); + pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0) + | IPSR_24_FUNC(6) + | IPSR_20_FUNC(6) + | IPSR_16_FUNC(6) + | IPSR_12_FUNC(6) + | IPSR_8_FUNC(6) + | IPSR_4_FUNC(6) + | IPSR_0_FUNC(6)); + pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6) + | IPSR_24_FUNC(6) + | IPSR_20_FUNC(6) + | IPSR_16_FUNC(6) + | IPSR_12_FUNC(6) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(6) + | IPSR_4_FUNC(6) + | IPSR_0_FUNC(6)); + pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(6) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6) + | IPSR_24_FUNC(6) + | IPSR_20_FUNC(6) + | IPSR_16_FUNC(6) + | IPSR_12_FUNC(6) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(6) + | IPSR_4_FUNC(6) + | IPSR_0_FUNC(6)); + pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1) + | IPSR_24_FUNC(1) + | IPSR_20_FUNC(1) + | IPSR_16_FUNC(1) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0) + | IPSR_24_FUNC(4) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(1) + | IPSR_0_FUNC(1)); + pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(4) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(8) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(3) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(3) + | IPSR_0_FUNC(8)); + pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(1) + | IPSR_0_FUNC(1)); + pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(1) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR17, IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + + /* initialize GPIO/perihperal function select */ + pfc_reg_write(PFC_GPSR0, GPSR0_D15 + | GPSR0_D14 + | GPSR0_D13 + | GPSR0_D12 + | GPSR0_D11 + | GPSR0_D10 + | GPSR0_D9 + | GPSR0_D8); + pfc_reg_write(PFC_GPSR1, GPSR1_EX_WAIT0_A + | GPSR1_A19 + | GPSR1_A18 + | GPSR1_A17 + | GPSR1_A16 + | GPSR1_A15 + | GPSR1_A14 + | GPSR1_A13 + | GPSR1_A12 + | GPSR1_A7 + | GPSR1_A6 + | GPSR1_A5 + | GPSR1_A4 + | GPSR1_A3 + | GPSR1_A2 + | GPSR1_A1 + | GPSR1_A0); + pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A + | GPSR2_AVB_AVTP_MATCH_A + | GPSR2_AVB_LINK + | GPSR2_AVB_PHY_INT + | GPSR2_AVB_MDC + | GPSR2_PWM2_A + | GPSR2_PWM1_A + | GPSR2_IRQ5 + | GPSR2_IRQ4 + | GPSR2_IRQ3 + | GPSR2_IRQ2 + | GPSR2_IRQ1 + | GPSR2_IRQ0); + pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP + | GPSR3_SD0_CD + | GPSR3_SD1_DAT3 + | GPSR3_SD1_DAT2 + | GPSR3_SD1_DAT1 + | GPSR3_SD1_DAT0 + | GPSR3_SD0_DAT3 + | GPSR3_SD0_DAT2 + | GPSR3_SD0_DAT1 + | GPSR3_SD0_DAT0 + | GPSR3_SD0_CMD + | GPSR3_SD0_CLK); + pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7 + | GPSR4_SD3_DAT6 + | GPSR4_SD3_DAT3 + | GPSR4_SD3_DAT2 + | GPSR4_SD3_DAT1 + | GPSR4_SD3_DAT0 + | GPSR4_SD3_CMD + | GPSR4_SD3_CLK + | GPSR4_SD2_DS + | GPSR4_SD2_DAT3 + | GPSR4_SD2_DAT2 + | GPSR4_SD2_DAT1 + | GPSR4_SD2_DAT0 + | GPSR4_SD2_CMD + | GPSR4_SD2_CLK); + pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2 + | GPSR5_MSIOF0_SS1 + | GPSR5_MSIOF0_SYNC + | GPSR5_HRTS0 + | GPSR5_HCTS0 + | GPSR5_HTX0 + | GPSR5_HRX0 + | GPSR5_HSCK0 + | GPSR5_RX2_A + | GPSR5_TX2_A + | GPSR5_SCK2 + | GPSR5_RTS1_TANS + | GPSR5_CTS1 + | GPSR5_TX1_A + | GPSR5_RX1_A + | GPSR5_RTS0_TANS + | GPSR5_SCK0); + pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC + | GPSR6_USB30_PWEN + | GPSR6_USB1_OVC + | GPSR6_USB1_PWEN + | GPSR6_USB0_OVC + | GPSR6_USB0_PWEN + | GPSR6_AUDIO_CLKB_B + | GPSR6_AUDIO_CLKA_A + | GPSR6_SSI_SDATA8 + | GPSR6_SSI_SDATA7 + | GPSR6_SSI_WS78 + | GPSR6_SSI_SCK78 + | GPSR6_SSI_WS6 + | GPSR6_SSI_SCK6 + | GPSR6_SSI_SDATA4 + | GPSR6_SSI_WS4 + | GPSR6_SSI_SCK4 + | GPSR6_SSI_SDATA1_A + | GPSR6_SSI_SDATA0 + | GPSR6_SSI_WS0129 + | GPSR6_SSI_SCK0129); + pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC + | GPSR7_HDMI0_CEC + | GPSR7_AVS2 + | GPSR7_AVS1); + + /* initialize POC control register */ + pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V + | POC_SD3_DAT7_33V + | POC_SD3_DAT6_33V + | POC_SD3_DAT5_33V + | POC_SD3_DAT4_33V + | POC_SD3_DAT3_33V + | POC_SD3_DAT2_33V + | POC_SD3_DAT1_33V + | POC_SD3_DAT0_33V + | POC_SD3_CMD_33V + | POC_SD3_CLK_33V + | POC_SD0_DAT3_33V + | POC_SD0_DAT2_33V + | POC_SD0_DAT1_33V + | POC_SD0_DAT0_33V + | POC_SD0_CMD_33V + | POC_SD0_CLK_33V); + + /* initialize DRV control register */ + pfc_reg_write(PFC_DRVCTRL0, DRVCTRL0_QSPI0_SPCLK(3) + | DRVCTRL0_QSPI0_MOSI_IO0(3) + | DRVCTRL0_QSPI0_MISO_IO1(3) + | DRVCTRL0_QSPI0_IO2(3) + | DRVCTRL0_QSPI0_IO3(3) + | DRVCTRL0_QSPI0_SSL(3) + | DRVCTRL0_QSPI1_SPCLK(3) + | DRVCTRL0_QSPI1_MOSI_IO0(3)); + pfc_reg_write(PFC_DRVCTRL1, DRVCTRL1_QSPI1_MISO_IO1(3) + | DRVCTRL1_QSPI1_IO2(3) + | DRVCTRL1_QSPI1_IO3(3) + | DRVCTRL1_QSPI1_SS(3) + | DRVCTRL1_RPC_INT(3) + | DRVCTRL1_RPC_WP(3) + | DRVCTRL1_RPC_RESET(3) + | DRVCTRL1_AVB_RX_CTL(7)); + pfc_reg_write(PFC_DRVCTRL2, DRVCTRL2_AVB_RXC(7) + | DRVCTRL2_AVB_RD0(7) + | DRVCTRL2_AVB_RD1(7) + | DRVCTRL2_AVB_RD2(7) + | DRVCTRL2_AVB_RD3(7) + | DRVCTRL2_AVB_TX_CTL(7) + | DRVCTRL2_AVB_TXC(7) + | DRVCTRL2_AVB_TD0(7)); + pfc_reg_write(PFC_DRVCTRL3, DRVCTRL3_AVB_TD1(7) + | DRVCTRL3_AVB_TD2(7) + | DRVCTRL3_AVB_TD3(7) + | DRVCTRL3_AVB_TXCREFCLK(7) + | DRVCTRL3_AVB_MDIO(7) + | DRVCTRL3_AVB_MDC(7) + | DRVCTRL3_AVB_MAGIC(7) + | DRVCTRL3_AVB_PHY_INT(7)); + pfc_reg_write(PFC_DRVCTRL4, DRVCTRL4_AVB_LINK(7) + | DRVCTRL4_AVB_AVTP_MATCH(7) + | DRVCTRL4_AVB_AVTP_CAPTURE(7) + | DRVCTRL4_IRQ0(7) + | DRVCTRL4_IRQ1(7) + | DRVCTRL4_IRQ2(7) + | DRVCTRL4_IRQ3(7) + | DRVCTRL4_IRQ4(7)); + pfc_reg_write(PFC_DRVCTRL5, DRVCTRL5_IRQ5(7) + | DRVCTRL5_PWM0(7) + | DRVCTRL5_PWM1(7) + | DRVCTRL5_PWM2(7) + | DRVCTRL5_A0(7) + | DRVCTRL5_A1(7) + | DRVCTRL5_A2(7) + | DRVCTRL5_A3(7)); + pfc_reg_write(PFC_DRVCTRL6, DRVCTRL6_A4(7) + | DRVCTRL6_A5(7) + | DRVCTRL6_A6(7) + | DRVCTRL6_A7(7) + | DRVCTRL6_A8(7) + | DRVCTRL6_A9(7) + | DRVCTRL6_A10(7) + | DRVCTRL6_A11(7)); + pfc_reg_write(PFC_DRVCTRL7, DRVCTRL7_A12(7) + | DRVCTRL7_A13(7) + | DRVCTRL7_A14(7) + | DRVCTRL7_A15(7) + | DRVCTRL7_A16(7) + | DRVCTRL7_A17(7) + | DRVCTRL7_A18(7) + | DRVCTRL7_A19(7)); + pfc_reg_write(PFC_DRVCTRL8, DRVCTRL8_CLKOUT(7) + | DRVCTRL8_CS0(7) + | DRVCTRL8_CS1_A2(7) + | DRVCTRL8_BS(7) + | DRVCTRL8_RD(7) + | DRVCTRL8_RD_W(7) + | DRVCTRL8_WE0(7) + | DRVCTRL8_WE1(7)); + pfc_reg_write(PFC_DRVCTRL9, DRVCTRL9_EX_WAIT0(7) + | DRVCTRL9_PRESETOU(7) + | DRVCTRL9_D0(7) + | DRVCTRL9_D1(7) + | DRVCTRL9_D2(7) + | DRVCTRL9_D3(7) + | DRVCTRL9_D4(7) + | DRVCTRL9_D5(7)); + pfc_reg_write(PFC_DRVCTRL10, DRVCTRL10_D6(7) + | DRVCTRL10_D7(7) + | DRVCTRL10_D8(7) + | DRVCTRL10_D9(7) + | DRVCTRL10_D10(7) + | DRVCTRL10_D11(7) + | DRVCTRL10_D12(7) + | DRVCTRL10_D13(7)); + pfc_reg_write(PFC_DRVCTRL11, DRVCTRL11_D14(7) + | DRVCTRL11_D15(7) + | DRVCTRL11_AVS1(7) + | DRVCTRL11_AVS2(7) + | DRVCTRL11_HDMI0_CEC(7) + | DRVCTRL11_HDMI1_CEC(7) + | DRVCTRL11_DU_DOTCLKIN0(3) + | DRVCTRL11_DU_DOTCLKIN1(3)); + pfc_reg_write(PFC_DRVCTRL12, DRVCTRL12_DU_DOTCLKIN2(3) + | DRVCTRL12_DU_DOTCLKIN3(3) + | DRVCTRL12_DU_FSCLKST(3) + | DRVCTRL12_DU_TMS(3)); + pfc_reg_write(PFC_DRVCTRL13, DRVCTRL13_TDO(3) + | DRVCTRL13_ASEBRK(3) + | DRVCTRL13_SD0_CLK(7) + | DRVCTRL13_SD0_CMD(7) + | DRVCTRL13_SD0_DAT0(7) + | DRVCTRL13_SD0_DAT1(7) + | DRVCTRL13_SD0_DAT2(7) + | DRVCTRL13_SD0_DAT3(7)); + pfc_reg_write(PFC_DRVCTRL14, DRVCTRL14_SD1_CLK(7) + | DRVCTRL14_SD1_CMD(7) + | DRVCTRL14_SD1_DAT0(7) + | DRVCTRL14_SD1_DAT1(7) + | DRVCTRL14_SD1_DAT2(7) + | DRVCTRL14_SD1_DAT3(7) + | DRVCTRL14_SD2_CLK(7) + | DRVCTRL14_SD2_CMD(7)); + pfc_reg_write(PFC_DRVCTRL15, DRVCTRL15_SD2_DAT0(7) + | DRVCTRL15_SD2_DAT1(7) + | DRVCTRL15_SD2_DAT2(7) + | DRVCTRL15_SD2_DAT3(7) + | DRVCTRL15_SD2_DS(7) + | DRVCTRL15_SD3_CLK(7) + | DRVCTRL15_SD3_CMD(7) + | DRVCTRL15_SD3_DAT0(7)); + pfc_reg_write(PFC_DRVCTRL16, DRVCTRL16_SD3_DAT1(7) + | DRVCTRL16_SD3_DAT2(7) + | DRVCTRL16_SD3_DAT3(7) + | DRVCTRL16_SD3_DAT4(7) + | DRVCTRL16_SD3_DAT5(7) + | DRVCTRL16_SD3_DAT6(7) + | DRVCTRL16_SD3_DAT7(7) + | DRVCTRL16_SD3_DS(7)); + pfc_reg_write(PFC_DRVCTRL17,DRVCTRL17_SD0_CD(7) + | DRVCTRL17_SD0_WP(7) + | DRVCTRL17_SD1_CD(7) + | DRVCTRL17_SD1_WP(7) + | DRVCTRL17_SCK0(7) + | DRVCTRL17_RX0(7) + | DRVCTRL17_TX0(7) + | DRVCTRL17_CTS0(7)); + pfc_reg_write(PFC_DRVCTRL18, DRVCTRL18_RTS0_TANS(7) + | DRVCTRL18_RX1(7) + | DRVCTRL18_TX1(7) + | DRVCTRL18_CTS1(7) + | DRVCTRL18_RTS1_TANS(7) + | DRVCTRL18_SCK2(7) + | DRVCTRL18_TX2(7) + | DRVCTRL18_RX2(7)); + pfc_reg_write(PFC_DRVCTRL19, DRVCTRL19_HSCK0(7) + | DRVCTRL19_HRX0(7) + | DRVCTRL19_HTX0(7) + | DRVCTRL19_HCTS0(7) + | DRVCTRL19_HRTS0(7) + | DRVCTRL19_MSIOF0_SCK(7) + | DRVCTRL19_MSIOF0_SYNC(7) + | DRVCTRL19_MSIOF0_SS1(7)); + pfc_reg_write(PFC_DRVCTRL20, DRVCTRL20_MSIOF0_TXD(7) + | DRVCTRL20_MSIOF0_SS2(7) + | DRVCTRL20_MSIOF0_RXD(7) + | DRVCTRL20_MLB_CLK(7) + | DRVCTRL20_MLB_SIG(7) + | DRVCTRL20_MLB_DAT(7) + | DRVCTRL20_MLB_REF(7) + | DRVCTRL20_SSI_SCK0129(7)); + pfc_reg_write(PFC_DRVCTRL21, DRVCTRL21_SSI_WS0129(7) + | DRVCTRL21_SSI_SDATA0(7) + | DRVCTRL21_SSI_SDATA1(7) + | DRVCTRL21_SSI_SDATA2(7) + | DRVCTRL21_SSI_SCK34(7) + | DRVCTRL21_SSI_WS34(7) + | DRVCTRL21_SSI_SDATA3(7) + | DRVCTRL21_SSI_SCK4(7)); + pfc_reg_write(PFC_DRVCTRL22, DRVCTRL22_SSI_WS4(7) + | DRVCTRL22_SSI_SDATA4(7) + | DRVCTRL22_SSI_SCK5(7) + | DRVCTRL22_SSI_WS5(7) + | DRVCTRL22_SSI_SDATA5(7) + | DRVCTRL22_SSI_SCK6(7) + | DRVCTRL22_SSI_WS6(7) + | DRVCTRL22_SSI_SDATA6(7)); + pfc_reg_write(PFC_DRVCTRL23, DRVCTRL23_SSI_SCK78(7) + | DRVCTRL23_SSI_WS78(7) + | DRVCTRL23_SSI_SDATA7(7) + | DRVCTRL23_SSI_SDATA8(7) + | DRVCTRL23_SSI_SDATA9(7) + | DRVCTRL23_AUDIO_CLKA(7) + | DRVCTRL23_AUDIO_CLKB(7) + | DRVCTRL23_USB0_PWEN(7)); + pfc_reg_write(PFC_DRVCTRL24, DRVCTRL24_USB0_OVC(7) + | DRVCTRL24_USB1_PWEN(7) + | DRVCTRL24_USB1_OVC(7) + | DRVCTRL24_USB30_PWEN(7) + | DRVCTRL24_USB30_OVC(7) + | DRVCTRL24_USB31_PWEN(7) + | DRVCTRL24_USB31_OVC(7)); + + /* initialize LSI pin pull-up/down control */ + pfc_reg_write(PFC_PUD0,0x00005FBFU); + pfc_reg_write(PFC_PUD1,0x00300FFEU); + pfc_reg_write(PFC_PUD2,0x330001E6U); + pfc_reg_write(PFC_PUD3,0x000002E0U); + pfc_reg_write(PFC_PUD4,0xFFFFFF00U); + pfc_reg_write(PFC_PUD5,0x7F5FFF87U); + pfc_reg_write(PFC_PUD6,0x00000055U); + + /* initialize LSI pin pull-enable register */ + pfc_reg_write(PFC_PUEN0,0x00000FFFU); + pfc_reg_write(PFC_PUEN1,0x00100234U); + pfc_reg_write(PFC_PUEN2,0x000004C4U); + pfc_reg_write(PFC_PUEN3,0x00000200U); + pfc_reg_write(PFC_PUEN4,0x3E000000U); + pfc_reg_write(PFC_PUEN5,0x1F000805U); + pfc_reg_write(PFC_PUEN6,0x00000006U); + + /* initialize positive/negative logic select */ + mmio_write_32(GPIO_POSNEG0, 0x00000000U); + mmio_write_32(GPIO_POSNEG1, 0x00000000U); + mmio_write_32(GPIO_POSNEG2, 0x00000000U); + mmio_write_32(GPIO_POSNEG3, 0x00000000U); + mmio_write_32(GPIO_POSNEG4, 0x00000000U); + mmio_write_32(GPIO_POSNEG5, 0x00000000U); + mmio_write_32(GPIO_POSNEG6, 0x00000000U); + + /* initialize general IO/interrupt switching */ + mmio_write_32(GPIO_IOINTSEL0, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL1, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL2, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL3, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL4, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL5, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL6, 0x00000000U); + + /* initialize general output register */ + mmio_write_32(GPIO_OUTDT1, 0x00000000U); + mmio_write_32(GPIO_OUTDT2, 0x00000400U); + mmio_write_32(GPIO_OUTDT3, 0x0000C000U); + mmio_write_32(GPIO_OUTDT5, 0x00000006U); + mmio_write_32(GPIO_OUTDT6, 0x00003880U); + + /* initialize general input/output switching */ + mmio_write_32(GPIO_INOUTSEL0, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U); + mmio_write_32(GPIO_INOUTSEL2, 0x00000400U); + mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U); + mmio_write_32(GPIO_INOUTSEL4, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU); + mmio_write_32(GPIO_INOUTSEL6, 0x00013880U); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/H3/pfc_init_h3.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/H3/pfc_init_h3.h new file mode 100644 index 0000000..31fde81 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/H3/pfc_init_h3.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef PFC_INIT_H3_H__ +#define PFC_INIT_H3_H__ + +void pfc_init_h3(void); + +#endif /* PFC_INIT_H3_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/M3/pfc_init_m3.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/M3/pfc_init_m3.c new file mode 100644 index 0000000..d284a40 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/M3/pfc_init_m3.c @@ -0,0 +1,1564 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include /* for uint32_t */ +#include +#include "bl2_cpg_init.h" +#include "pfc_init_m3.h" +#include "../../rcar_def.h" + + +/* GPIO base address */ +#define GPIO_BASE (0xE6050000U) + +/* GPIO registers */ +#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U) +#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U) +#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U) +#define GPIO_INDT0 (GPIO_BASE + 0x000CU) +#define GPIO_INTDT0 (GPIO_BASE + 0x0010U) +#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U) +#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U) +#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU) +#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U) +#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U) +#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U) +#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U) +#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU) +#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U) +#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U) +#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U) +#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU) +#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U) +#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U) +#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U) +#define GPIO_INDT1 (GPIO_BASE + 0x100CU) +#define GPIO_INTDT1 (GPIO_BASE + 0x1010U) +#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U) +#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U) +#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU) +#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U) +#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U) +#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U) +#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U) +#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU) +#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U) +#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U) +#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U) +#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU) +#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U) +#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U) +#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U) +#define GPIO_INDT2 (GPIO_BASE + 0x200CU) +#define GPIO_INTDT2 (GPIO_BASE + 0x2010U) +#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U) +#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U) +#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU) +#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U) +#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U) +#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U) +#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U) +#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU) +#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U) +#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U) +#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U) +#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU) +#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U) +#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U) +#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U) +#define GPIO_INDT3 (GPIO_BASE + 0x300CU) +#define GPIO_INTDT3 (GPIO_BASE + 0x3010U) +#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U) +#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U) +#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU) +#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U) +#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U) +#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U) +#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U) +#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU) +#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U) +#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U) +#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U) +#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU) +#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U) +#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U) +#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U) +#define GPIO_INDT4 (GPIO_BASE + 0x400CU) +#define GPIO_INTDT4 (GPIO_BASE + 0x4010U) +#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U) +#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U) +#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU) +#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U) +#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U) +#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U) +#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U) +#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU) +#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U) +#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U) +#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U) +#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU) +#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U) +#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U) +#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U) +#define GPIO_INDT5 (GPIO_BASE + 0x500CU) +#define GPIO_INTDT5 (GPIO_BASE + 0x5010U) +#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U) +#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U) +#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU) +#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U) +#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U) +#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U) +#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U) +#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU) +#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U) +#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U) +#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U) +#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU) +#define GPIO_IOINTSEL6 (GPIO_BASE + 0x5400U) +#define GPIO_INOUTSEL6 (GPIO_BASE + 0x5404U) +#define GPIO_OUTDT6 (GPIO_BASE + 0x5408U) +#define GPIO_INDT6 (GPIO_BASE + 0x540CU) +#define GPIO_INTDT6 (GPIO_BASE + 0x5410U) +#define GPIO_INTCLR6 (GPIO_BASE + 0x5414U) +#define GPIO_INTMSK6 (GPIO_BASE + 0x5418U) +#define GPIO_MSKCLR6 (GPIO_BASE + 0x541CU) +#define GPIO_POSNEG6 (GPIO_BASE + 0x5420U) +#define GPIO_EDGLEVEL6 (GPIO_BASE + 0x5424U) +#define GPIO_FILONOFF6 (GPIO_BASE + 0x5428U) +#define GPIO_INTMSKS6 (GPIO_BASE + 0x5438U) +#define GPIO_MSKCLRS6 (GPIO_BASE + 0x543CU) +#define GPIO_OUTDTSEL6 (GPIO_BASE + 0x5440U) +#define GPIO_OUTDTH6 (GPIO_BASE + 0x5444U) +#define GPIO_OUTDTL6 (GPIO_BASE + 0x5448U) +#define GPIO_BOTHEDGE6 (GPIO_BASE + 0x544CU) +#define GPIO_IOINTSEL7 (GPIO_BASE + 0x5800U) +#define GPIO_INOUTSEL7 (GPIO_BASE + 0x5804U) +#define GPIO_OUTDT7 (GPIO_BASE + 0x5808U) +#define GPIO_INDT7 (GPIO_BASE + 0x580CU) +#define GPIO_INTDT7 (GPIO_BASE + 0x5810U) +#define GPIO_INTCLR7 (GPIO_BASE + 0x5814U) +#define GPIO_INTMSK7 (GPIO_BASE + 0x5818U) +#define GPIO_MSKCLR7 (GPIO_BASE + 0x581CU) +#define GPIO_POSNEG7 (GPIO_BASE + 0x5820U) +#define GPIO_EDGLEVEL7 (GPIO_BASE + 0x5824U) +#define GPIO_FILONOFF7 (GPIO_BASE + 0x5828U) +#define GPIO_INTMSKS7 (GPIO_BASE + 0x5838U) +#define GPIO_MSKCLRS7 (GPIO_BASE + 0x583CU) +#define GPIO_OUTDTSEL7 (GPIO_BASE + 0x5840U) +#define GPIO_OUTDTH7 (GPIO_BASE + 0x5844U) +#define GPIO_OUTDTL7 (GPIO_BASE + 0x5848U) +#define GPIO_BOTHEDGE7 (GPIO_BASE + 0x584CU) + + +/* Pin functon base address */ +#define PFC_BASE (0xE6060000U) + +/* Pin functon registers */ +#define PFC_PMMR (PFC_BASE + 0x0000U) +#define PFC_GPSR0 (PFC_BASE + 0x0100U) +#define PFC_GPSR1 (PFC_BASE + 0x0104U) +#define PFC_GPSR2 (PFC_BASE + 0x0108U) +#define PFC_GPSR3 (PFC_BASE + 0x010CU) +#define PFC_GPSR4 (PFC_BASE + 0x0110U) +#define PFC_GPSR5 (PFC_BASE + 0x0114U) +#define PFC_GPSR6 (PFC_BASE + 0x0118U) +#define PFC_GPSR7 (PFC_BASE + 0x011CU) +#define PFC_IPSR0 (PFC_BASE + 0x0200U) +#define PFC_IPSR1 (PFC_BASE + 0x0204U) +#define PFC_IPSR2 (PFC_BASE + 0x0208U) +#define PFC_IPSR3 (PFC_BASE + 0x020CU) +#define PFC_IPSR4 (PFC_BASE + 0x0210U) +#define PFC_IPSR5 (PFC_BASE + 0x0214U) +#define PFC_IPSR6 (PFC_BASE + 0x0218U) +#define PFC_IPSR7 (PFC_BASE + 0x021CU) +#define PFC_IPSR8 (PFC_BASE + 0x0220U) +#define PFC_IPSR9 (PFC_BASE + 0x0224U) +#define PFC_IPSR10 (PFC_BASE + 0x0228U) +#define PFC_IPSR11 (PFC_BASE + 0x022CU) +#define PFC_IPSR12 (PFC_BASE + 0x0230U) +#define PFC_IPSR13 (PFC_BASE + 0x0234U) +#define PFC_IPSR14 (PFC_BASE + 0x0238U) +#define PFC_IPSR15 (PFC_BASE + 0x023CU) +#define PFC_IPSR16 (PFC_BASE + 0x0240U) +#define PFC_IPSR17 (PFC_BASE + 0x0244U) +#define PFC_IPSR18 (PFC_BASE + 0x0248U) +#define PFC_DRVCTRL0 (PFC_BASE + 0x0300U) +#define PFC_DRVCTRL1 (PFC_BASE + 0x0304U) +#define PFC_DRVCTRL2 (PFC_BASE + 0x0308U) +#define PFC_DRVCTRL3 (PFC_BASE + 0x030CU) +#define PFC_DRVCTRL4 (PFC_BASE + 0x0310U) +#define PFC_DRVCTRL5 (PFC_BASE + 0x0314U) +#define PFC_DRVCTRL6 (PFC_BASE + 0x0318U) +#define PFC_DRVCTRL7 (PFC_BASE + 0x031CU) +#define PFC_DRVCTRL8 (PFC_BASE + 0x0320U) +#define PFC_DRVCTRL9 (PFC_BASE + 0x0324U) +#define PFC_DRVCTRL10 (PFC_BASE + 0x0328U) +#define PFC_DRVCTRL11 (PFC_BASE + 0x032CU) +#define PFC_DRVCTRL12 (PFC_BASE + 0x0330U) +#define PFC_DRVCTRL13 (PFC_BASE + 0x0334U) +#define PFC_DRVCTRL14 (PFC_BASE + 0x0338U) +#define PFC_DRVCTRL15 (PFC_BASE + 0x033CU) +#define PFC_DRVCTRL16 (PFC_BASE + 0x0340U) +#define PFC_DRVCTRL17 (PFC_BASE + 0x0344U) +#define PFC_DRVCTRL18 (PFC_BASE + 0x0348U) +#define PFC_DRVCTRL19 (PFC_BASE + 0x034CU) +#define PFC_DRVCTRL20 (PFC_BASE + 0x0350U) +#define PFC_DRVCTRL21 (PFC_BASE + 0x0354U) +#define PFC_DRVCTRL22 (PFC_BASE + 0x0358U) +#define PFC_DRVCTRL23 (PFC_BASE + 0x035CU) +#define PFC_DRVCTRL24 (PFC_BASE + 0x0360U) +#define PFC_POCCTRL0 (PFC_BASE + 0x0380U) +#define PFC_TDSELCTRL0 (PFC_BASE + 0x03C0U) +#define PFC_IOCTRL (PFC_BASE + 0x03E0U) +#define PFC_TSREG (PFC_BASE + 0x03E4U) +#define PFC_PUEN0 (PFC_BASE + 0x0400U) +#define PFC_PUEN1 (PFC_BASE + 0x0404U) +#define PFC_PUEN2 (PFC_BASE + 0x0408U) +#define PFC_PUEN3 (PFC_BASE + 0x040CU) +#define PFC_PUEN4 (PFC_BASE + 0x0410U) +#define PFC_PUEN5 (PFC_BASE + 0x0414U) +#define PFC_PUEN6 (PFC_BASE + 0x0418U) +#define PFC_PUD0 (PFC_BASE + 0x0440U) +#define PFC_PUD1 (PFC_BASE + 0x0444U) +#define PFC_PUD2 (PFC_BASE + 0x0448U) +#define PFC_PUD3 (PFC_BASE + 0x044CU) +#define PFC_PUD4 (PFC_BASE + 0x0450U) +#define PFC_PUD5 (PFC_BASE + 0x0454U) +#define PFC_PUD6 (PFC_BASE + 0x0458U) +#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U) +#define PFC_MOD_SEL1 (PFC_BASE + 0x0504U) +#define PFC_MOD_SEL2 (PFC_BASE + 0x0508U) + +#define GPSR0_D15 ((uint32_t)1U << 15U) +#define GPSR0_D14 ((uint32_t)1U << 14U) +#define GPSR0_D13 ((uint32_t)1U << 13U) +#define GPSR0_D12 ((uint32_t)1U << 12U) +#define GPSR0_D11 ((uint32_t)1U << 11U) +#define GPSR0_D10 ((uint32_t)1U << 10U) +#define GPSR0_D9 ((uint32_t)1U << 9U) +#define GPSR0_D8 ((uint32_t)1U << 8U) +#define GPSR0_D7 ((uint32_t)1U << 7U) +#define GPSR0_D6 ((uint32_t)1U << 6U) +#define GPSR0_D5 ((uint32_t)1U << 5U) +#define GPSR0_D4 ((uint32_t)1U << 4U) +#define GPSR0_D3 ((uint32_t)1U << 3U) +#define GPSR0_D2 ((uint32_t)1U << 2U) +#define GPSR0_D1 ((uint32_t)1U << 1U) +#define GPSR0_D0 ((uint32_t)1U << 0U) +#define GPSR1_CLKOUT ((uint32_t)1U << 28U) +#define GPSR1_EX_WAIT0_A ((uint32_t)1U << 27U) +#define GPSR1_WE1 ((uint32_t)1U << 26U) +#define GPSR1_WE0 ((uint32_t)1U << 25U) +#define GPSR1_RD_WR ((uint32_t)1U << 24U) +#define GPSR1_RD ((uint32_t)1U << 23U) +#define GPSR1_BS ((uint32_t)1U << 22U) +#define GPSR1_CS1_A26 ((uint32_t)1U << 21U) +#define GPSR1_CS0 ((uint32_t)1U << 20U) +#define GPSR1_A19 ((uint32_t)1U << 19U) +#define GPSR1_A18 ((uint32_t)1U << 18U) +#define GPSR1_A17 ((uint32_t)1U << 17U) +#define GPSR1_A16 ((uint32_t)1U << 16U) +#define GPSR1_A15 ((uint32_t)1U << 15U) +#define GPSR1_A14 ((uint32_t)1U << 14U) +#define GPSR1_A13 ((uint32_t)1U << 13U) +#define GPSR1_A12 ((uint32_t)1U << 12U) +#define GPSR1_A11 ((uint32_t)1U << 11U) +#define GPSR1_A10 ((uint32_t)1U << 10U) +#define GPSR1_A9 ((uint32_t)1U << 9U) +#define GPSR1_A8 ((uint32_t)1U << 8U) +#define GPSR1_A7 ((uint32_t)1U << 7U) +#define GPSR1_A6 ((uint32_t)1U << 6U) +#define GPSR1_A5 ((uint32_t)1U << 5U) +#define GPSR1_A4 ((uint32_t)1U << 4U) +#define GPSR1_A3 ((uint32_t)1U << 3U) +#define GPSR1_A2 ((uint32_t)1U << 2U) +#define GPSR1_A1 ((uint32_t)1U << 1U) +#define GPSR1_A0 ((uint32_t)1U << 0U) +#define GPSR2_AVB_AVTP_CAPTURE_A ((uint32_t)1U << 14U) +#define GPSR2_AVB_AVTP_MATCH_A ((uint32_t)1U << 13U) +#define GPSR2_AVB_LINK ((uint32_t)1U << 12U) +#define GPSR2_AVB_PHY_INT ((uint32_t)1U << 11U) +#define GPSR2_AVB_MAGIC ((uint32_t)1U << 10U) +#define GPSR2_AVB_MDC ((uint32_t)1U << 9U) +#define GPSR2_PWM2_A ((uint32_t)1U << 8U) +#define GPSR2_PWM1_A ((uint32_t)1U << 7U) +#define GPSR2_PWM0 ((uint32_t)1U << 6U) +#define GPSR2_IRQ5 ((uint32_t)1U << 5U) +#define GPSR2_IRQ4 ((uint32_t)1U << 4U) +#define GPSR2_IRQ3 ((uint32_t)1U << 3U) +#define GPSR2_IRQ2 ((uint32_t)1U << 2U) +#define GPSR2_IRQ1 ((uint32_t)1U << 1U) +#define GPSR2_IRQ0 ((uint32_t)1U << 0U) +#define GPSR3_SD1_WP ((uint32_t)1U << 15U) +#define GPSR3_SD1_CD ((uint32_t)1U << 14U) +#define GPSR3_SD0_WP ((uint32_t)1U << 13U) +#define GPSR3_SD0_CD ((uint32_t)1U << 12U) +#define GPSR3_SD1_DAT3 ((uint32_t)1U << 11U) +#define GPSR3_SD1_DAT2 ((uint32_t)1U << 10U) +#define GPSR3_SD1_DAT1 ((uint32_t)1U << 9U) +#define GPSR3_SD1_DAT0 ((uint32_t)1U << 8U) +#define GPSR3_SD1_CMD ((uint32_t)1U << 7U) +#define GPSR3_SD1_CLK ((uint32_t)1U << 6U) +#define GPSR3_SD0_DAT3 ((uint32_t)1U << 5U) +#define GPSR3_SD0_DAT2 ((uint32_t)1U << 4U) +#define GPSR3_SD0_DAT1 ((uint32_t)1U << 3U) +#define GPSR3_SD0_DAT0 ((uint32_t)1U << 2U) +#define GPSR3_SD0_CMD ((uint32_t)1U << 1U) +#define GPSR3_SD0_CLK ((uint32_t)1U << 0U) +#define GPSR4_SD3_DS ((uint32_t)1U << 17U) +#define GPSR4_SD3_DAT7 ((uint32_t)1U << 16U) +#define GPSR4_SD3_DAT6 ((uint32_t)1U << 15U) +#define GPSR4_SD3_DAT5 ((uint32_t)1U << 14U) +#define GPSR4_SD3_DAT4 ((uint32_t)1U << 13U) +#define GPSR4_SD3_DAT3 ((uint32_t)1U << 12U) +#define GPSR4_SD3_DAT2 ((uint32_t)1U << 11U) +#define GPSR4_SD3_DAT1 ((uint32_t)1U << 10U) +#define GPSR4_SD3_DAT0 ((uint32_t)1U << 9U) +#define GPSR4_SD3_CMD ((uint32_t)1U << 8U) +#define GPSR4_SD3_CLK ((uint32_t)1U << 7U) +#define GPSR4_SD2_DS ((uint32_t)1U << 6U) +#define GPSR4_SD2_DAT3 ((uint32_t)1U << 5U) +#define GPSR4_SD2_DAT2 ((uint32_t)1U << 4U) +#define GPSR4_SD2_DAT1 ((uint32_t)1U << 3U) +#define GPSR4_SD2_DAT0 ((uint32_t)1U << 2U) +#define GPSR4_SD2_CMD ((uint32_t)1U << 1U) +#define GPSR4_SD2_CLK ((uint32_t)1U << 0U) +#define GPSR5_MLB_DAT ((uint32_t)1U << 25U) +#define GPSR5_MLB_SIG ((uint32_t)1U << 24U) +#define GPSR5_MLB_CLK ((uint32_t)1U << 23U) +#define GPSR5_MSIOF0_RXD ((uint32_t)1U << 22U) +#define GPSR5_MSIOF0_SS2 ((uint32_t)1U << 21U) +#define GPSR5_MSIOF0_TXD ((uint32_t)1U << 20U) +#define GPSR5_MSIOF0_SS1 ((uint32_t)1U << 19U) +#define GPSR5_MSIOF0_SYNC ((uint32_t)1U << 18U) +#define GPSR5_MSIOF0_SCK ((uint32_t)1U << 17U) +#define GPSR5_HRTS0 ((uint32_t)1U << 16U) +#define GPSR5_HCTS0 ((uint32_t)1U << 15U) +#define GPSR5_HTX0 ((uint32_t)1U << 14U) +#define GPSR5_HRX0 ((uint32_t)1U << 13U) +#define GPSR5_HSCK0 ((uint32_t)1U << 12U) +#define GPSR5_RX2_A ((uint32_t)1U << 11U) +#define GPSR5_TX2_A ((uint32_t)1U << 10U) +#define GPSR5_SCK2 ((uint32_t)1U << 9U) +#define GPSR5_RTS1_TANS ((uint32_t)1U << 8U) +#define GPSR5_CTS1 ((uint32_t)1U << 7U) +#define GPSR5_TX1_A ((uint32_t)1U << 6U) +#define GPSR5_RX1_A ((uint32_t)1U << 5U) +#define GPSR5_RTS0_TANS ((uint32_t)1U << 4U) +#define GPSR5_CTS0 ((uint32_t)1U << 3U) +#define GPSR5_TX0 ((uint32_t)1U << 2U) +#define GPSR5_RX0 ((uint32_t)1U << 1U) +#define GPSR5_SCK0 ((uint32_t)1U << 0U) +#define GPSR6_USB31_OVC ((uint32_t)1U << 31U) +#define GPSR6_USB31_PWEN ((uint32_t)1U << 30U) +#define GPSR6_USB30_OVC ((uint32_t)1U << 29U) +#define GPSR6_USB30_PWEN ((uint32_t)1U << 28U) +#define GPSR6_USB1_OVC ((uint32_t)1U << 27U) +#define GPSR6_USB1_PWEN ((uint32_t)1U << 26U) +#define GPSR6_USB0_OVC ((uint32_t)1U << 25U) +#define GPSR6_USB0_PWEN ((uint32_t)1U << 24U) +#define GPSR6_AUDIO_CLKB_B ((uint32_t)1U << 23U) +#define GPSR6_AUDIO_CLKA_A ((uint32_t)1U << 22U) +#define GPSR6_SSI_SDATA9_A ((uint32_t)1U << 21U) +#define GPSR6_SSI_SDATA8 ((uint32_t)1U << 20U) +#define GPSR6_SSI_SDATA7 ((uint32_t)1U << 19U) +#define GPSR6_SSI_WS78 ((uint32_t)1U << 18U) +#define GPSR6_SSI_SCK78 ((uint32_t)1U << 17U) +#define GPSR6_SSI_SDATA6 ((uint32_t)1U << 16U) +#define GPSR6_SSI_WS6 ((uint32_t)1U << 15U) +#define GPSR6_SSI_SCK6 ((uint32_t)1U << 14U) +#define GPSR6_SSI_SDATA5 ((uint32_t)1U << 13U) +#define GPSR6_SSI_WS5 ((uint32_t)1U << 12U) +#define GPSR6_SSI_SCK5 ((uint32_t)1U << 11U) +#define GPSR6_SSI_SDATA4 ((uint32_t)1U << 10U) +#define GPSR6_SSI_WS4 ((uint32_t)1U << 9U) +#define GPSR6_SSI_SCK4 ((uint32_t)1U << 8U) +#define GPSR6_SSI_SDATA3 ((uint32_t)1U << 7U) +#define GPSR6_SSI_WS34 ((uint32_t)1U << 6U) +#define GPSR6_SSI_SCK34 ((uint32_t)1U << 5U) +#define GPSR6_SSI_SDATA2_A ((uint32_t)1U << 4U) +#define GPSR6_SSI_SDATA1_A ((uint32_t)1U << 3U) +#define GPSR6_SSI_SDATA0 ((uint32_t)1U << 2U) +#define GPSR6_SSI_WS0129 ((uint32_t)1U << 1U) +#define GPSR6_SSI_SCK0129 ((uint32_t)1U << 0U) +#define GPSR7_HDMI1_CEC ((uint32_t)1U << 3U) +#define GPSR7_HDMI0_CEC ((uint32_t)1U << 2U) +#define GPSR7_AVS2 ((uint32_t)1U << 1U) +#define GPSR7_AVS1 ((uint32_t)1U << 0U) + +#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) +#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) +#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) +#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) +#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) +#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) +#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) +#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) + +#define POC_SD3_DS_33V ((uint32_t)1U << 29U) +#define POC_SD3_DAT7_33V ((uint32_t)1U << 28U) +#define POC_SD3_DAT6_33V ((uint32_t)1U << 27U) +#define POC_SD3_DAT5_33V ((uint32_t)1U << 26U) +#define POC_SD3_DAT4_33V ((uint32_t)1U << 25U) +#define POC_SD3_DAT3_33V ((uint32_t)1U << 24U) +#define POC_SD3_DAT2_33V ((uint32_t)1U << 23U) +#define POC_SD3_DAT1_33V ((uint32_t)1U << 22U) +#define POC_SD3_DAT0_33V ((uint32_t)1U << 21U) +#define POC_SD3_CMD_33V ((uint32_t)1U << 20U) +#define POC_SD3_CLK_33V ((uint32_t)1U << 19U) +#define POC_SD2_DS_33V ((uint32_t)1U << 18U) +#define POC_SD2_DAT3_33V ((uint32_t)1U << 17U) +#define POC_SD2_DAT2_33V ((uint32_t)1U << 16U) +#define POC_SD2_DAT1_33V ((uint32_t)1U << 15U) +#define POC_SD2_DAT0_33V ((uint32_t)1U << 14U) +#define POC_SD2_CMD_33V ((uint32_t)1U << 13U) +#define POC_SD2_CLK_33V ((uint32_t)1U << 12U) +#define POC_SD1_DAT3_33V ((uint32_t)1U << 11U) +#define POC_SD1_DAT2_33V ((uint32_t)1U << 10U) +#define POC_SD1_DAT1_33V ((uint32_t)1U << 9U) +#define POC_SD1_DAT0_33V ((uint32_t)1U << 8U) +#define POC_SD1_CMD_33V ((uint32_t)1U << 7U) +#define POC_SD1_CLK_33V ((uint32_t)1U << 6U) +#define POC_SD0_DAT3_33V ((uint32_t)1U << 5U) +#define POC_SD0_DAT2_33V ((uint32_t)1U << 4U) +#define POC_SD0_DAT1_33V ((uint32_t)1U << 3U) +#define POC_SD0_DAT0_33V ((uint32_t)1U << 2U) +#define POC_SD0_CMD_33V ((uint32_t)1U << 1U) +#define POC_SD0_CLK_33V ((uint32_t)1U << 0U) + +#define DRVCTRL0_MASK (0xCCCCCCCCU) +#define DRVCTRL1_MASK (0xCCCCCCC8U) +#define DRVCTRL2_MASK (0x88888888U) +#define DRVCTRL3_MASK (0x88888888U) +#define DRVCTRL4_MASK (0x88888888U) +#define DRVCTRL5_MASK (0x88888888U) +#define DRVCTRL6_MASK (0x88888888U) +#define DRVCTRL7_MASK (0x88888888U) +#define DRVCTRL8_MASK (0x88888888U) +#define DRVCTRL9_MASK (0x88888888U) +#define DRVCTRL10_MASK (0x88888888U) +#define DRVCTRL11_MASK (0x888888CCU) +#define DRVCTRL12_MASK (0xCCCFFFCFU) +#define DRVCTRL13_MASK (0xCC888888U) +#define DRVCTRL14_MASK (0x88888888U) +#define DRVCTRL15_MASK (0x88888888U) +#define DRVCTRL16_MASK (0x88888888U) +#define DRVCTRL17_MASK (0x88888888U) +#define DRVCTRL18_MASK (0x88888888U) +#define DRVCTRL19_MASK (0x88888888U) +#define DRVCTRL20_MASK (0x88888888U) +#define DRVCTRL21_MASK (0x88888888U) +#define DRVCTRL22_MASK (0x88888888U) +#define DRVCTRL23_MASK (0x88888888U) +#define DRVCTRL24_MASK (0x8888888FU) + +#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U) +#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U) +#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U) +#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U) +#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U) +#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U) +#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U) +#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U) +#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U) +#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U) +#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U) +#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U) +#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U) +#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U) +#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U) +#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U) +#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U) +#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U) +#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U) +#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U) +#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U) +#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U) +#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U) +#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U) +#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U) +#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U) +#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U) +#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U) +#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U) +#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U) +#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U) +#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U) +#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U) +#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U) +#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U) +#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U) +#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) +#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) +#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U) +#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U) +#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U) +#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U) +#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U) +#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U) +#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U) +#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U) +#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U) +#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U) +#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U) +#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U) +#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U) +#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U) +#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U) +#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U) +#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U) +#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U) +#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U) +#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U) +#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U) +#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U) +#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U) +#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U) +#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U) +#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U) +#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U) +#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U) +#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U) +#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U) +#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U) +#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U) +#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U) +#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U) +#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U) +#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U) +#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U) +#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U) +#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U) +#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U) +#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U) +#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U) +#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U) +#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U) +#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U) +#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U) +#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U) +#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U) +#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U) +#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U) +#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U) +#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U) +#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U) +#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U) +#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U) +#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U) +#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U) +#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U) +#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U) +#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U) +#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U) +#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U) +#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U) +#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U) +#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U) +#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U) +#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U) +#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U) +#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U) +#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U) +#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U) +#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U) +#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U) +#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U) +#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U) +#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U) +#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U) +#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U) +#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U) +#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U) +#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U) +#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U) +#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U) +#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U) +#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U) +#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U) +#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U) +#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U) +#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U) +#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U) +#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U) +#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U) +#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U) +#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U) +#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U) +#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U) +#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U) +#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U) +#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U) +#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U) +#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U) +#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U) +#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U) +#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U) +#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U) +#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U) +#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U) +#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U) +#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U) +#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U) +#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U) +#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U) +#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U) +#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U) +#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U) +#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U) +#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U) +#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U) +#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U) +#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U) +#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U) +#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U) +#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U) +#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U) +#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U) +#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U) +#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U) +#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U) +#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U) +#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U) +#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U) +#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U) +#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U) +#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U) +#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U) +#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U) +#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U) +#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U) +#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U) +#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U) +#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U) +#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U) +#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U) + +#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U) +#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U) +#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U) +#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U) +#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U) +#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U) +#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U) +#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U) +#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U) +#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U) +#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U) +#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U) +#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U) +#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U) +#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U) +#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U) +#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U) +#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U) +#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U) +#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U) +#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U) +#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U) +#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U) +#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U) +#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U) +#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U) +#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U) +#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U) +#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U) +#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U) +#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U) +#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U) +#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U) +#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U) +#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U) +#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U) +#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U) +#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U) +#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U) +#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U) +#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U) +#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U) +#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U) +#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U) +#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U) +#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U) +#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U) +#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U) +#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U) +#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U) +#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U) +#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U) +#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U) +#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U) +#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U) +#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U) +#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U) +#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U) +#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U) +#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U) +#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U) +#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U) +#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U) +#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U) +#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U) +#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U) +#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U) +#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U) +#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U) +#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U) +#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U) +#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U) +#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U) +#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U) +#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U) +#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U) +#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U) +#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U) +#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U) +#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U) +#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U) +#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U) +#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U) +#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U) +#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U) +#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U) +#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U) +#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U) +#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U) +#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U) +#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U) +#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U) +#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U) +#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U) +#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U) +#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U) +#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U) +#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U) +#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U) +#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U) +#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U) +#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U) +#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U) +#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U) +#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U) +#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U) +#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U) +#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U) +#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U) +#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U) +#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U) +#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U) +#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U) +#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U) +#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U) +#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U) +#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U) +#define MOD_SEL2_FM_A ((uint32_t)0U << 27U) +#define MOD_SEL2_FM_B ((uint32_t)1U << 27U) +#define MOD_SEL2_FM_C ((uint32_t)2U << 27U) +#define MOD_SEL2_FM_D ((uint32_t)3U << 27U) +#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U) +#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U) +#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U) +#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U) +#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U) +#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U) +#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U) +#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U) +#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U) +#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U) +#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U) +#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U) +#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U) +#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U) +#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U) +#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U) +#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U) +#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U) +#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U) + + +/* SCIF3 Registers for Dummy write */ +#define SCIF3_BASE (0xE6C50000U) +#define SCIF3_SCFCR (SCIF3_BASE + 0x0018U) +#define SCIF3_SCFDR (SCIF3_BASE + 0x001CU) +#define SCFCR_DATA (0x0000U) + +/* Realtime module stop control */ +#define CPG_BASE (0xE6150000U) +#define CPG_MSTPSR0 (CPG_BASE + 0x0030U) +#define CPG_RMSTPCR0 (CPG_BASE + 0x0110U) +#define RMSTPCR0_RTDMAC (0x00200000U) + +/* RT-DMAC Registers */ +#define RTDMAC_CH (0U) /* choose 0 to 15 */ + +#define RTDMAC_BASE (0xFFC10000U) +#define RTDMAC_RDMOR (RTDMAC_BASE + 0x0060U) +#define RTDMAC_RDMCHCLR (RTDMAC_BASE + 0x0080U) +#define RTDMAC_RDMSAR(x) (RTDMAC_BASE + 0x8000U + (0x80U * (x))) +#define RTDMAC_RDMDAR(x) (RTDMAC_BASE + 0x8004U + (0x80U * (x))) +#define RTDMAC_RDMTCR(x) (RTDMAC_BASE + 0x8008U + (0x80U * (x))) +#define RTDMAC_RDMCHCR(x) (RTDMAC_BASE + 0x800CU + (0x80U * (x))) +#define RTDMAC_RDMCHCRB(x) (RTDMAC_BASE + 0x801CU + (0x80U * (x))) +#define RTDMAC_RDMDPBASE(x) (RTDMAC_BASE + 0x8050U + (0x80U * (x))) +#define RTDMAC_DESC_BASE (RTDMAC_BASE + 0xA000U) +#define RTDMAC_DESC_RDMSAR (RTDMAC_DESC_BASE + 0x0000U) +#define RTDMAC_DESC_RDMDAR (RTDMAC_DESC_BASE + 0x0004U) +#define RTDMAC_DESC_RDMTCR (RTDMAC_DESC_BASE + 0x0008U) + +#define RDMOR_DME (0x0001U) /* DMA Master Enable */ +#define RDMCHCR_DPM_INFINITE (0x30000000U) /* Infinite repeat mode */ +#define RDMCHCR_RPT_TCR (0x02000000U) /* enable to update TCR */ +#define RDMCHCR_TS_2 (0x00000008U) /* Word(2byte) units transfer */ +#define RDMCHCR_RS_AUTO (0x00000400U) /* Auto request */ +#define RDMCHCR_DE (0x00000001U) /* DMA Enable */ +#define RDMCHCRB_DRST (0x00008000U) /* Descriptor reset */ +#define RDMCHCRB_SLM_256 (0x00000080U) /* once in 256 clock cycle */ +#define RDMDPBASE_SEL_EXT (0x00000001U) /* External memory use */ + + +static void StartRtDma0_Descriptor(void); +static void pfc_reg_write(uint32_t addr, uint32_t data); + + +static void StartRtDma0_Descriptor(void) +{ + uint32_t reg; + + reg = mmio_read_32(RCAR_PRR); + reg &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); + if (reg == (RCAR_PRODUCT_M3_CUT10)) { + /* Module stop clear */ + while((mmio_read_32(CPG_MSTPSR0) & RMSTPCR0_RTDMAC) != 0U) { + reg = mmio_read_32(CPG_RMSTPCR0); + reg &= ~RMSTPCR0_RTDMAC; + cpg_write(CPG_RMSTPCR0, reg); + } + + /* Initialize ch0, Reset Descriptor */ + mmio_write_32(RTDMAC_RDMCHCLR, ((uint32_t)1U << RTDMAC_CH)); + mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_DRST); + + /* Enable DMA */ + mmio_write_16(RTDMAC_RDMOR, RDMOR_DME); + + /* Set first transfer */ + mmio_write_32(RTDMAC_RDMSAR(RTDMAC_CH), RCAR_PRR); + mmio_write_32(RTDMAC_RDMDAR(RTDMAC_CH), SCIF3_SCFDR); + mmio_write_32(RTDMAC_RDMTCR(RTDMAC_CH), 0x00000001U); + + /* Set descriptor */ + mmio_write_32(RTDMAC_DESC_RDMSAR, 0x00000000U); + mmio_write_32(RTDMAC_DESC_RDMDAR, 0x00000000U); + mmio_write_32(RTDMAC_DESC_RDMTCR, 0x00200000U); + mmio_write_32(RTDMAC_RDMCHCRB(RTDMAC_CH), RDMCHCRB_SLM_256); + mmio_write_32(RTDMAC_RDMDPBASE(RTDMAC_CH), RTDMAC_DESC_BASE + | RDMDPBASE_SEL_EXT); + + /* Set transfer parameter, Start transfer */ + mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE + | RDMCHCR_RPT_TCR + | RDMCHCR_TS_2 + | RDMCHCR_RS_AUTO + | RDMCHCR_DE); + } +} + +static void pfc_reg_write(uint32_t addr, uint32_t data) +{ + uint32_t prr; + + prr = mmio_read_32(RCAR_PRR); + prr &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); + + mmio_write_32(PFC_PMMR, ~data); + if (prr == (RCAR_PRODUCT_M3_CUT10)) { + mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */ + } + mmio_write_32((uintptr_t)addr, data); + if (prr == (RCAR_PRODUCT_M3_CUT10)) { + mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */ + } +} + + +void pfc_init_m3(void) +{ + uint32_t reg; + + /* Work around for PFC eratta */ + StartRtDma0_Descriptor(); + + /* initialize module select */ + pfc_reg_write(PFC_MOD_SEL0, MOD_SEL0_MSIOF3_A + | MOD_SEL0_MSIOF2_A + | MOD_SEL0_MSIOF1_A + | MOD_SEL0_LBSC_A + | MOD_SEL0_IEBUS_A + | MOD_SEL0_I2C2_A + | MOD_SEL0_I2C1_A + | MOD_SEL0_HSCIF4_A + | MOD_SEL0_HSCIF3_A + | MOD_SEL0_HSCIF1_A + | MOD_SEL0_FSO_A + | MOD_SEL0_HSCIF2_A + | MOD_SEL0_ETHERAVB_A + | MOD_SEL0_DRIF3_A + | MOD_SEL0_DRIF2_A + | MOD_SEL0_DRIF1_A + | MOD_SEL0_DRIF0_A + | MOD_SEL0_CANFD0_A + | MOD_SEL0_ADG_A_A); + pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A + | MOD_SEL1_TSIF0_A + | MOD_SEL1_TIMER_TMU_A + | MOD_SEL1_SSP1_1_A + | MOD_SEL1_SSP1_0_A + | MOD_SEL1_SSI_A + | MOD_SEL1_SPEED_PULSE_IF_A + | MOD_SEL1_SIMCARD_A + | MOD_SEL1_SDHI2_A + | MOD_SEL1_SCIF4_A + | MOD_SEL1_SCIF3_A + | MOD_SEL1_SCIF2_A + | MOD_SEL1_SCIF1_A + | MOD_SEL1_SCIF_A + | MOD_SEL1_REMOCON_A + | MOD_SEL1_RCAN0_A + | MOD_SEL1_PWM6_A + | MOD_SEL1_PWM5_A + | MOD_SEL1_PWM4_A + | MOD_SEL1_PWM3_A + | MOD_SEL1_PWM2_A + | MOD_SEL1_PWM1_A); + pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A + | MOD_SEL2_I2C_3_A + | MOD_SEL2_I2C_0_A + | MOD_SEL2_FM_A + | MOD_SEL2_SCIF5_A + | MOD_SEL2_I2C6_A + | MOD_SEL2_NDF_A + | MOD_SEL2_SSI2_A + | MOD_SEL2_SSI9_A + | MOD_SEL2_TIMER_TMU2_A + | MOD_SEL2_ADG_B_A + | MOD_SEL2_ADG_C_A + | MOD_SEL2_VIN4_A); + + /* initialize peripheral function select */ + pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(6) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(3) + | IPSR_8_FUNC(3) + | IPSR_4_FUNC(3) + | IPSR_0_FUNC(3)); + pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0) + | IPSR_24_FUNC(6) + | IPSR_20_FUNC(6) + | IPSR_16_FUNC(6) + | IPSR_12_FUNC(6) + | IPSR_8_FUNC(6) + | IPSR_4_FUNC(6) + | IPSR_0_FUNC(6)); + pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(6) + | IPSR_24_FUNC(6) + | IPSR_20_FUNC(6) + | IPSR_16_FUNC(6) + | IPSR_12_FUNC(6) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(6) + | IPSR_4_FUNC(6) + | IPSR_0_FUNC(6)); + pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(6) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(6) + | IPSR_24_FUNC(6) + | IPSR_20_FUNC(6) + | IPSR_16_FUNC(6) + | IPSR_12_FUNC(6) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(6) + | IPSR_4_FUNC(6) + | IPSR_0_FUNC(6)); + pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(1) + | IPSR_24_FUNC(1) + | IPSR_20_FUNC(1) + | IPSR_16_FUNC(1) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(1) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0) + | IPSR_24_FUNC(4) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(1)); + pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(4) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(8) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(3) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(3) + | IPSR_0_FUNC(8)); + pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR16, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR17, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(1) + | IPSR_0_FUNC(0)); + pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + + /* initialize GPIO/perihperal function select */ + pfc_reg_write(PFC_GPSR0, GPSR0_D15 + | GPSR0_D14 + | GPSR0_D13 + | GPSR0_D12 + | GPSR0_D11 + | GPSR0_D10 + | GPSR0_D9 + | GPSR0_D8); + pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT + | GPSR1_EX_WAIT0_A + | GPSR1_A19 + | GPSR1_A18 + | GPSR1_A17 + | GPSR1_A16 + | GPSR1_A15 + | GPSR1_A14 + | GPSR1_A13 + | GPSR1_A12 + | GPSR1_A7 + | GPSR1_A6 + | GPSR1_A5 + | GPSR1_A4 + | GPSR1_A3 + | GPSR1_A2 + | GPSR1_A1 + | GPSR1_A0); + pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A + | GPSR2_AVB_AVTP_MATCH_A + | GPSR2_AVB_LINK + | GPSR2_AVB_PHY_INT + | GPSR2_AVB_MDC + | GPSR2_PWM2_A + | GPSR2_PWM1_A + | GPSR2_IRQ5 + | GPSR2_IRQ4 + | GPSR2_IRQ3 + | GPSR2_IRQ2 + | GPSR2_IRQ1 + | GPSR2_IRQ0); + pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP + | GPSR3_SD0_CD + | GPSR3_SD1_DAT3 + | GPSR3_SD1_DAT2 + | GPSR3_SD1_DAT1 + | GPSR3_SD1_DAT0 + | GPSR3_SD0_DAT3 + | GPSR3_SD0_DAT2 + | GPSR3_SD0_DAT1 + | GPSR3_SD0_DAT0 + | GPSR3_SD0_CMD + | GPSR3_SD0_CLK); + pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7 + | GPSR4_SD3_DAT6 + | GPSR4_SD3_DAT3 + | GPSR4_SD3_DAT2 + | GPSR4_SD3_DAT1 + | GPSR4_SD3_DAT0 + | GPSR4_SD3_CMD + | GPSR4_SD3_CLK + | GPSR4_SD2_DS + | GPSR4_SD2_DAT3 + | GPSR4_SD2_DAT2 + | GPSR4_SD2_DAT1 + | GPSR4_SD2_DAT0 + | GPSR4_SD2_CMD + | GPSR4_SD2_CLK); + pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2 + | GPSR5_MSIOF0_SS1 + | GPSR5_MSIOF0_SYNC + | GPSR5_HRTS0 + | GPSR5_HCTS0 + | GPSR5_HTX0 + | GPSR5_HRX0 + | GPSR5_HSCK0 + | GPSR5_RX2_A + | GPSR5_TX2_A + | GPSR5_SCK2 + | GPSR5_RTS1_TANS + | GPSR5_CTS1 + | GPSR5_TX1_A + | GPSR5_RX1_A + | GPSR5_RTS0_TANS + | GPSR5_SCK0); + pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC + | GPSR6_USB30_PWEN + | GPSR6_USB1_OVC + | GPSR6_USB1_PWEN + | GPSR6_USB0_OVC + | GPSR6_USB0_PWEN + | GPSR6_AUDIO_CLKB_B + | GPSR6_AUDIO_CLKA_A + | GPSR6_SSI_SDATA8 + | GPSR6_SSI_SDATA7 + | GPSR6_SSI_WS78 + | GPSR6_SSI_SCK78 + | GPSR6_SSI_WS6 + | GPSR6_SSI_SCK6 + | GPSR6_SSI_SDATA4 + | GPSR6_SSI_WS4 + | GPSR6_SSI_SCK4 + | GPSR6_SSI_SDATA1_A + | GPSR6_SSI_SDATA0 + | GPSR6_SSI_WS0129 + | GPSR6_SSI_SCK0129); + pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC + | GPSR7_HDMI0_CEC + | GPSR7_AVS2 + | GPSR7_AVS1); + + /* initialize POC control register */ + pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V + | POC_SD3_DAT7_33V + | POC_SD3_DAT6_33V + | POC_SD3_DAT5_33V + | POC_SD3_DAT4_33V + | POC_SD3_DAT3_33V + | POC_SD3_DAT2_33V + | POC_SD3_DAT1_33V + | POC_SD3_DAT0_33V + | POC_SD3_CMD_33V + | POC_SD3_CLK_33V + | POC_SD0_DAT3_33V + | POC_SD0_DAT2_33V + | POC_SD0_DAT1_33V + | POC_SD0_DAT0_33V + | POC_SD0_CMD_33V + | POC_SD0_CLK_33V); + + /* initialize DRV control register */ + reg = mmio_read_32(PFC_DRVCTRL0); + reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3) + | DRVCTRL0_QSPI0_MOSI_IO0(3) + | DRVCTRL0_QSPI0_MISO_IO1(3) + | DRVCTRL0_QSPI0_IO2(3) + | DRVCTRL0_QSPI0_IO3(3) + | DRVCTRL0_QSPI0_SSL(3) + | DRVCTRL0_QSPI1_SPCLK(3) + | DRVCTRL0_QSPI1_MOSI_IO0(3)); + pfc_reg_write(PFC_DRVCTRL0, reg); + reg = mmio_read_32(PFC_DRVCTRL1); + reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3) + | DRVCTRL1_QSPI1_IO2(3) + | DRVCTRL1_QSPI1_IO3(3) + | DRVCTRL1_QSPI1_SS(3) + | DRVCTRL1_RPC_INT(3) + | DRVCTRL1_RPC_WP(3) + | DRVCTRL1_RPC_RESET(3) + | DRVCTRL1_AVB_RX_CTL(7)); + pfc_reg_write(PFC_DRVCTRL1, reg); + reg = mmio_read_32(PFC_DRVCTRL2); + reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7) + | DRVCTRL2_AVB_RD0(7) + | DRVCTRL2_AVB_RD1(7) + | DRVCTRL2_AVB_RD2(7) + | DRVCTRL2_AVB_RD3(7) + | DRVCTRL2_AVB_TX_CTL(7) + | DRVCTRL2_AVB_TXC(7) + | DRVCTRL2_AVB_TD0(7)); + pfc_reg_write(PFC_DRVCTRL2, reg); + reg = mmio_read_32(PFC_DRVCTRL3); + reg = ((reg & DRVCTRL3_MASK) | DRVCTRL3_AVB_TD1(7) + | DRVCTRL3_AVB_TD2(7) + | DRVCTRL3_AVB_TD3(7) + | DRVCTRL3_AVB_TXCREFCLK(7) + | DRVCTRL3_AVB_MDIO(7) + | DRVCTRL3_AVB_MDC(7) + | DRVCTRL3_AVB_MAGIC(7) + | DRVCTRL3_AVB_PHY_INT(7)); + pfc_reg_write(PFC_DRVCTRL3, reg); + reg = mmio_read_32(PFC_DRVCTRL4); + reg = ((reg & DRVCTRL4_MASK) | DRVCTRL4_AVB_LINK(7) + | DRVCTRL4_AVB_AVTP_MATCH(7) + | DRVCTRL4_AVB_AVTP_CAPTURE(7) + | DRVCTRL4_IRQ0(7) + | DRVCTRL4_IRQ1(7) + | DRVCTRL4_IRQ2(7) + | DRVCTRL4_IRQ3(7) + | DRVCTRL4_IRQ4(7)); + pfc_reg_write(PFC_DRVCTRL4, reg); + reg = mmio_read_32(PFC_DRVCTRL5); + reg = ((reg & DRVCTRL5_MASK) | DRVCTRL5_IRQ5(7) + | DRVCTRL5_PWM0(7) + | DRVCTRL5_PWM1(7) + | DRVCTRL5_PWM2(7) + | DRVCTRL5_A0(7) + | DRVCTRL5_A1(7) + | DRVCTRL5_A2(7) + | DRVCTRL5_A3(7)); + pfc_reg_write(PFC_DRVCTRL5, reg); + reg = mmio_read_32(PFC_DRVCTRL6); + reg = ((reg & DRVCTRL6_MASK) | DRVCTRL6_A4(7) + | DRVCTRL6_A5(7) + | DRVCTRL6_A6(7) + | DRVCTRL6_A7(7) + | DRVCTRL6_A8(7) + | DRVCTRL6_A9(7) + | DRVCTRL6_A10(7) + | DRVCTRL6_A11(7)); + pfc_reg_write(PFC_DRVCTRL6, reg); + reg = mmio_read_32(PFC_DRVCTRL7); + reg = ((reg & DRVCTRL7_MASK) | DRVCTRL7_A12(7) + | DRVCTRL7_A13(7) + | DRVCTRL7_A14(7) + | DRVCTRL7_A15(7) + | DRVCTRL7_A16(7) + | DRVCTRL7_A17(7) + | DRVCTRL7_A18(7) + | DRVCTRL7_A19(7)); + pfc_reg_write(PFC_DRVCTRL7, reg); + reg = mmio_read_32(PFC_DRVCTRL8); + reg = ((reg & DRVCTRL8_MASK) | DRVCTRL8_CLKOUT(7) + | DRVCTRL8_CS0(7) + | DRVCTRL8_CS1_A2(7) + | DRVCTRL8_BS(7) + | DRVCTRL8_RD(7) + | DRVCTRL8_RD_W(7) + | DRVCTRL8_WE0(7) + | DRVCTRL8_WE1(7)); + pfc_reg_write(PFC_DRVCTRL8, reg); + reg = mmio_read_32(PFC_DRVCTRL9); + reg = ((reg & DRVCTRL9_MASK) | DRVCTRL9_EX_WAIT0(7) + | DRVCTRL9_PRESETOU(7) + | DRVCTRL9_D0(7) + | DRVCTRL9_D1(7) + | DRVCTRL9_D2(7) + | DRVCTRL9_D3(7) + | DRVCTRL9_D4(7) + | DRVCTRL9_D5(7)); + pfc_reg_write(PFC_DRVCTRL9, reg); + reg = mmio_read_32(PFC_DRVCTRL10); + reg = ((reg & DRVCTRL10_MASK) | DRVCTRL10_D6(7) + | DRVCTRL10_D7(7) + | DRVCTRL10_D8(7) + | DRVCTRL10_D9(7) + | DRVCTRL10_D10(7) + | DRVCTRL10_D11(7) + | DRVCTRL10_D12(7) + | DRVCTRL10_D13(7)); + pfc_reg_write(PFC_DRVCTRL10, reg); + reg = mmio_read_32(PFC_DRVCTRL11); + reg = ((reg & DRVCTRL11_MASK) | DRVCTRL11_D14(7) + | DRVCTRL11_D15(7) + | DRVCTRL11_AVS1(7) + | DRVCTRL11_AVS2(7) + | DRVCTRL11_HDMI0_CEC(7) + | DRVCTRL11_HDMI1_CEC(7) + | DRVCTRL11_DU_DOTCLKIN0(3) + | DRVCTRL11_DU_DOTCLKIN1(3)); + pfc_reg_write(PFC_DRVCTRL11, reg); + reg = mmio_read_32(PFC_DRVCTRL12); + reg = ((reg & DRVCTRL12_MASK) | DRVCTRL12_DU_DOTCLKIN2(3) + | DRVCTRL12_DU_DOTCLKIN3(3) + | DRVCTRL12_DU_FSCLKST(3) + | DRVCTRL12_DU_TMS(3)); + pfc_reg_write(PFC_DRVCTRL12, reg); + reg = mmio_read_32(PFC_DRVCTRL13); + reg = ((reg & DRVCTRL13_MASK) | DRVCTRL13_TDO(3) + | DRVCTRL13_ASEBRK(3) + | DRVCTRL13_SD0_CLK(7) + | DRVCTRL13_SD0_CMD(7) + | DRVCTRL13_SD0_DAT0(7) + | DRVCTRL13_SD0_DAT1(7) + | DRVCTRL13_SD0_DAT2(7) + | DRVCTRL13_SD0_DAT3(7)); + pfc_reg_write(PFC_DRVCTRL13, reg); + reg = mmio_read_32(PFC_DRVCTRL14); + reg = ((reg & DRVCTRL14_MASK) | DRVCTRL14_SD1_CLK(7) + | DRVCTRL14_SD1_CMD(7) + | DRVCTRL14_SD1_DAT0(7) + | DRVCTRL14_SD1_DAT1(7) + | DRVCTRL14_SD1_DAT2(7) + | DRVCTRL14_SD1_DAT3(7) + | DRVCTRL14_SD2_CLK(7) + | DRVCTRL14_SD2_CMD(7)); + pfc_reg_write(PFC_DRVCTRL14, reg); + reg = mmio_read_32(PFC_DRVCTRL15); + reg = ((reg & DRVCTRL15_MASK) | DRVCTRL15_SD2_DAT0(7) + | DRVCTRL15_SD2_DAT1(7) + | DRVCTRL15_SD2_DAT2(7) + | DRVCTRL15_SD2_DAT3(7) + | DRVCTRL15_SD2_DS(7) + | DRVCTRL15_SD3_CLK(7) + | DRVCTRL15_SD3_CMD(7) + | DRVCTRL15_SD3_DAT0(7)); + pfc_reg_write(PFC_DRVCTRL15, reg); + reg = mmio_read_32(PFC_DRVCTRL16); + reg = ((reg & DRVCTRL16_MASK) | DRVCTRL16_SD3_DAT1(7) + | DRVCTRL16_SD3_DAT2(7) + | DRVCTRL16_SD3_DAT3(7) + | DRVCTRL16_SD3_DAT4(7) + | DRVCTRL16_SD3_DAT5(7) + | DRVCTRL16_SD3_DAT6(7) + | DRVCTRL16_SD3_DAT7(7) + | DRVCTRL16_SD3_DS(7)); + pfc_reg_write(PFC_DRVCTRL16, reg); + reg = mmio_read_32(PFC_DRVCTRL17); + reg = ((reg & DRVCTRL17_MASK) | DRVCTRL17_SD0_CD(7) + | DRVCTRL17_SD0_WP(7) + | DRVCTRL17_SD1_CD(7) + | DRVCTRL17_SD1_WP(7) + | DRVCTRL17_SCK0(7) + | DRVCTRL17_RX0(7) + | DRVCTRL17_TX0(7) + | DRVCTRL17_CTS0(7)); + pfc_reg_write(PFC_DRVCTRL17, reg); + reg = mmio_read_32(PFC_DRVCTRL18); + reg = ((reg & DRVCTRL18_MASK) | DRVCTRL18_RTS0_TANS(7) + | DRVCTRL18_RX1(7) + | DRVCTRL18_TX1(7) + | DRVCTRL18_CTS1(7) + | DRVCTRL18_RTS1_TANS(7) + | DRVCTRL18_SCK2(7) + | DRVCTRL18_TX2(7) + | DRVCTRL18_RX2(7)); + pfc_reg_write(PFC_DRVCTRL18, reg); + reg = mmio_read_32(PFC_DRVCTRL19); + reg = ((reg & DRVCTRL19_MASK) | DRVCTRL19_HSCK0(7) + | DRVCTRL19_HRX0(7) + | DRVCTRL19_HTX0(7) + | DRVCTRL19_HCTS0(7) + | DRVCTRL19_HRTS0(7) + | DRVCTRL19_MSIOF0_SCK(7) + | DRVCTRL19_MSIOF0_SYNC(7) + | DRVCTRL19_MSIOF0_SS1(7)); + pfc_reg_write(PFC_DRVCTRL19, reg); + reg = mmio_read_32(PFC_DRVCTRL20); + reg = ((reg & DRVCTRL20_MASK) | DRVCTRL20_MSIOF0_TXD(7) + | DRVCTRL20_MSIOF0_SS2(7) + | DRVCTRL20_MSIOF0_RXD(7) + | DRVCTRL20_MLB_CLK(7) + | DRVCTRL20_MLB_SIG(7) + | DRVCTRL20_MLB_DAT(7) + | DRVCTRL20_MLB_REF(7) + | DRVCTRL20_SSI_SCK0129(7)); + pfc_reg_write(PFC_DRVCTRL20, reg); + reg = mmio_read_32(PFC_DRVCTRL21); + reg = ((reg & DRVCTRL21_MASK) | DRVCTRL21_SSI_WS0129(7) + | DRVCTRL21_SSI_SDATA0(7) + | DRVCTRL21_SSI_SDATA1(7) + | DRVCTRL21_SSI_SDATA2(7) + | DRVCTRL21_SSI_SCK34(7) + | DRVCTRL21_SSI_WS34(7) + | DRVCTRL21_SSI_SDATA3(7) + | DRVCTRL21_SSI_SCK4(7)); + pfc_reg_write(PFC_DRVCTRL21, reg); + reg = mmio_read_32(PFC_DRVCTRL22); + reg = ((reg & DRVCTRL22_MASK) | DRVCTRL22_SSI_WS4(7) + | DRVCTRL22_SSI_SDATA4(7) + | DRVCTRL22_SSI_SCK5(7) + | DRVCTRL22_SSI_WS5(7) + | DRVCTRL22_SSI_SDATA5(7) + | DRVCTRL22_SSI_SCK6(7) + | DRVCTRL22_SSI_WS6(7) + | DRVCTRL22_SSI_SDATA6(7)); + pfc_reg_write(PFC_DRVCTRL22, reg); + reg = mmio_read_32(PFC_DRVCTRL23); + reg = ((reg & DRVCTRL23_MASK) | DRVCTRL23_SSI_SCK78(7) + | DRVCTRL23_SSI_WS78(7) + | DRVCTRL23_SSI_SDATA7(7) + | DRVCTRL23_SSI_SDATA8(7) + | DRVCTRL23_SSI_SDATA9(7) + | DRVCTRL23_AUDIO_CLKA(7) + | DRVCTRL23_AUDIO_CLKB(7) + | DRVCTRL23_USB0_PWEN(7)); + pfc_reg_write(PFC_DRVCTRL23, reg); + reg = mmio_read_32(PFC_DRVCTRL24); + reg = ((reg & DRVCTRL24_MASK) | DRVCTRL24_USB0_OVC(7) + | DRVCTRL24_USB1_PWEN(7) + | DRVCTRL24_USB1_OVC(7) + | DRVCTRL24_USB30_PWEN(7) + | DRVCTRL24_USB30_OVC(7) + | DRVCTRL24_USB31_PWEN(7) + | DRVCTRL24_USB31_OVC(7)); + pfc_reg_write(PFC_DRVCTRL24, reg); + + /* initialize LSI pin pull-up/down control */ + pfc_reg_write(PFC_PUD0,0x00005FBFU); + pfc_reg_write(PFC_PUD1,0x00300FFEU); + pfc_reg_write(PFC_PUD2,0x330001E6U); + pfc_reg_write(PFC_PUD3,0x000002E0U); + pfc_reg_write(PFC_PUD4,0xFFFFFF00U); + pfc_reg_write(PFC_PUD5,0x7F5FFF87U); + pfc_reg_write(PFC_PUD6,0x00000055U); + + /* initialize LSI pin pull-enable register */ + pfc_reg_write(PFC_PUEN0,0x00000FFFU); + pfc_reg_write(PFC_PUEN1,0x00100234U); + pfc_reg_write(PFC_PUEN2,0x000004C4U); + pfc_reg_write(PFC_PUEN3,0x00000200U); + pfc_reg_write(PFC_PUEN4,0x3E000000U); + pfc_reg_write(PFC_PUEN5,0x1F000805U); + pfc_reg_write(PFC_PUEN6,0x00000006U); + + /* initialize positive/negative logic select */ + mmio_write_32(GPIO_POSNEG0, 0x00000000U); + mmio_write_32(GPIO_POSNEG1, 0x00000000U); + mmio_write_32(GPIO_POSNEG2, 0x00000000U); + mmio_write_32(GPIO_POSNEG3, 0x00000000U); + mmio_write_32(GPIO_POSNEG4, 0x00000000U); + mmio_write_32(GPIO_POSNEG5, 0x00000000U); + mmio_write_32(GPIO_POSNEG6, 0x00000000U); + + /* initialize general IO/interrupt switching */ + mmio_write_32(GPIO_IOINTSEL0, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL1, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL2, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL3, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL4, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL5, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL6, 0x00000000U); + + /* initialize general output register */ + mmio_write_32(GPIO_OUTDT1, 0x00000000U); + mmio_write_32(GPIO_OUTDT2, 0x00000400U); + mmio_write_32(GPIO_OUTDT3, 0x0000C000U); + mmio_write_32(GPIO_OUTDT5, 0x00000006U); + mmio_write_32(GPIO_OUTDT6, 0x00003880U); + + /* initialize general input/output switching */ + mmio_write_32(GPIO_INOUTSEL0, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL1, 0x01000A00U); + mmio_write_32(GPIO_INOUTSEL2, 0x00000400U); + mmio_write_32(GPIO_INOUTSEL3, 0x0000C000U); + mmio_write_32(GPIO_INOUTSEL4, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU); + mmio_write_32(GPIO_INOUTSEL6, 0x00013880U); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/M3/pfc_init_m3.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/M3/pfc_init_m3.h new file mode 100644 index 0000000..c409948 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/M3/pfc_init_m3.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef PFC_INIT_M3_H__ +#define PFC_INIT_M3_H__ + +void pfc_init_m3(void); + +#endif /* PFC_INIT_M3_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/pfc.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/pfc.mk new file mode 100644 index 0000000..029d9b0 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/pfc.mk @@ -0,0 +1,39 @@ +# +# Copyright (c) 2015-2016, Renesas Electronics Corporation +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# - Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# - Neither the name of Renesas nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +ifeq (${RCAR_LSI},${RCAR_H3}) + BL2_SOURCES += plat/renesas/rcar/pfc/H3/pfc_init_h3.c +endif +ifeq (${RCAR_LSI},${RCAR_M3}) + BL2_SOURCES += plat/renesas/rcar/pfc/M3/pfc_init_m3.c +endif + +BL2_SOURCES += plat/renesas/rcar/pfc/pfc_init.c diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/pfc_init.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/pfc_init.c new file mode 100644 index 0000000..dc4fe17 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/pfc/pfc_init.c @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "pfc_init.h" +#if RCAR_LSI == RCAR_H3 /* H3 */ + #include "H3/pfc_init_h3.h" +#endif +#if RCAR_LSI == RCAR_M3 /* M3 */ + #include "M3/pfc_init_m3.h" +#endif + + +void pfc_init(void) +{ +#if RCAR_LSI == RCAR_H3 /* H3 */ + pfc_init_h3(); +#elif RCAR_LSI == RCAR_M3 /* M3 */ + pfc_init_m3(); +#endif +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/platform.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/platform.mk new file mode 100644 index 0000000..54dd37f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/platform.mk @@ -0,0 +1,184 @@ +# +# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + + +# Process flags + +PLAT_INCLUDES := -Iinclude/common/tbbr \ + -Iplat/renesas/rcar/include/ + +PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \ + plat/common/aarch64/plat_common.c + +BL2_SOURCES += plat/common/aarch64/platform_up_stack.S \ + drivers/arm/gic/arm_gic.c \ + drivers/arm/gic/gic_v2.c \ + drivers/arm/gic/gic_v3.c \ + plat/common/plat_gic.c \ + plat/renesas/rcar/drivers/timer/bl2_swdt.c \ + plat/renesas/rcar/drivers/error/bl2_int_error.c \ + plat/renesas/rcar/aarch64/rcar_helpers.S \ + plat/renesas/rcar/bl2_rcar_setup.c \ + plat/renesas/rcar/aarch64/rcar_common.c \ + plat/renesas/rcar/drivers/io/io_rcar.c \ + plat/renesas/rcar/drivers/io/io_memdrv.c \ + plat/renesas/rcar/drivers/scif/scif.S \ + plat/renesas/rcar/drivers/auth/rcarboot.c \ + plat/renesas/rcar/rcar_io_storage.c \ + drivers/io/io_storage.c \ + plat/renesas/rcar/drivers/rpc/rpc_driver.c \ + plat/renesas/rcar/drivers/dma/dma_driver.c \ + plat/renesas/rcar/drivers/avs/avs_driver.c \ + plat/renesas/rcar/bl2_secure_setting.c \ + plat/renesas/rcar/bl2_cpg_init.c \ + plat/renesas/rcar/aarch64/bl2_reset.S + +BL31_SOURCES += drivers/arm/cci/cci.c \ + drivers/arm/gic/arm_gic.c \ + drivers/arm/gic/gic_v2.c \ + drivers/arm/gic/gic_v3.c \ + lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + plat/common/plat_gic.c \ + plat/common/aarch64/platform_mp_stack.S \ + plat/renesas/rcar/bl31_rcar_setup.c \ + plat/renesas/rcar/rcar_pm.c \ + plat/renesas/rcar/drivers/memdrv/rcar_console.S \ + plat/renesas/rcar/drivers/memdrv/rcar_printf.c \ + plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.c \ + plat/renesas/rcar/rcar_topology.c \ + plat/renesas/rcar/aarch64/rcar_helpers.S \ + plat/renesas/rcar/aarch64/rcar_common.c \ + plat/renesas/rcar/drivers/pwrc/rcar_pwrc.c + + +BL33_SOURCES += drivers/arm/gic/arm_gic.c \ + drivers/arm/gic/gic_v2.c \ + drivers/arm/gic/gic_v3.c \ + lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + plat/common/plat_gic.c \ + plat/common/aarch64/platform_up_stack.S \ + plat/renesas/rcar/bl33_rcar_setup.c \ + plat/renesas/rcar/aarch64/rcar_common.c \ + plat/renesas/rcar/drivers/scif/scif.S + +# compile option setting +SPD := opteed +ARM_CCI_PRODUCT_ID := 500 +TRUSTED_BOARD_BOOT := 1 + +# LSI setting common define +RCAR_H3:=0 +RCAR_M3:=1 +$(eval $(call add_define,RCAR_H3)) +$(eval $(call add_define,RCAR_M3)) +RCAR_CUT_10:=0 +RCAR_CUT_11:=1 +$(eval $(call add_define,RCAR_CUT_10)) +$(eval $(call add_define,RCAR_CUT_11)) + +ifndef LSI + $(error "Error: Unknown LSI. Please use LSI= to specify the LSI") +else + ifeq (${LSI},H3) + RCAR_LSI:=${RCAR_H3} + ifndef LSI_CUT + # enable compatible function. + RCAR_LSI_CUT_COMPAT := 1 + $(eval $(call add_define,RCAR_LSI_CUT_COMPAT)) + else + # disable compatible function. + ifeq (${LSI_CUT},10) + RCAR_LSI_CUT:=0 + endif + ifeq (${LSI_CUT},11) + RCAR_LSI_CUT:=1 + endif + $(eval $(call add_define,RCAR_LSI_CUT)) + endif + else ifeq (${LSI},M3) + RCAR_LSI:=${RCAR_M3} + else + $(error "Error: ${LSI} is not supported.") + endif + $(eval $(call add_define,RCAR_LSI)) +endif + +# Process RCAR_SECURE_BOOT flag +ifndef RCAR_SECURE_BOOT +RCAR_SECURE_BOOT := 1 +endif +$(eval $(call add_define,RCAR_SECURE_BOOT)) + +# Process RCAR_QOS_TYPE flag +ifndef RCAR_QOS_TYPE +RCAR_QOS_TYPE := 0 +endif +$(eval $(call add_define,RCAR_QOS_TYPE)) + +# Process RCAR_DRAM_SPLIT flag +ifndef RCAR_DRAM_SPLIT +RCAR_DRAM_SPLIT := 0 +endif +$(eval $(call add_define,RCAR_DRAM_SPLIT)) + +# Process RCAR_BL33_EXECUTION_EL flag +ifndef RCAR_BL33_EXECUTION_EL +RCAR_BL33_EXECUTION_EL := 0 +endif +$(eval $(call add_define,RCAR_BL33_EXECUTION_EL)) + +# Process PSCI_DISABLE_BIGLITTLE_IN_CA57BOOT flag +ifndef PSCI_DISABLE_BIGLITTLE_IN_CA57BOOT +PSCI_DISABLE_BIGLITTLE_IN_CA57BOOT := 1 +endif +$(eval $(call add_define,PSCI_DISABLE_BIGLITTLE_IN_CA57BOOT)) + +# Process RCAR_AVS_SETTING_ENABLE flag +ifeq (${RCAR_AVS_SETTING_ENABLE},0) +AVS_SETTING_ENABLE := 0 +else +AVS_SETTING_ENABLE := 1 +endif +$(eval $(call add_define,AVS_SETTING_ENABLE)) + +# Process RCAR_LOSSY_ENABLE flag +ifndef RCAR_LOSSY_ENABLE +RCAR_LOSSY_ENABLE := 0 +endif +$(eval $(call add_define,RCAR_LOSSY_ENABLE)) + +include plat/renesas/rcar/ddr/ddr.mk +include plat/renesas/rcar/qos/qos.mk +include plat/renesas/rcar/pfc/pfc.mk diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/H3/ES10/qos_init_h3_es10.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/H3/ES10/qos_init_h3_es10.c new file mode 100644 index 0000000..7ccfeb4 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/H3/ES10/qos_init_h3_es10.c @@ -0,0 +1,409 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "qos_init_h3_es10.h" + + +#define RCAR_QOS_VERSION "rev.0.31" + +#define RCAR_QOS_NONE (3U) +#define RCAR_QOS_TYPE_DEFAULT (0U) + +#define RCAR_DRAM_SPLIT_LINEAR (0U) +#define RCAR_DRAM_SPLIT_4CH (1U) +#define RCAR_DRAM_SPLIT_2CH (2U) + +#define DBSC_BASE (0xE6790000U) +#define DBSC_AXARB (DBSC_BASE + 0x0800U) + +#define AXI_BASE (0xE6784000U) +#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U) +#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU) +#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U) +#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U) +#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U) +#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U) +#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U) +#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U) +#define ADSPLCR0_SWP (0x0CU) + +#define MSTAT_BASE (0xE67E0000U) +#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U) +#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U) +#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U) +#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U) +#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U) +#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U) +#define MSTAT_STATQC (MSTAT_BASE + 0x8008U) + +#define RALLOC_BASE (0xE67F0000U) +#define RALLOC_RAS (RALLOC_BASE + 0x0000U) +#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U) +#define RALLOC_RAEN (RALLOC_BASE + 0x0018U) +#define RALLOC_REGGD (RALLOC_BASE + 0x0020U) +#define RALLOC_DANN (RALLOC_BASE + 0x0030U) +#define RALLOC_DANT (RALLOC_BASE + 0x0038U) +#define RALLOC_EC (RALLOC_BASE + 0x003CU) +#define RALLOC_EMS (RALLOC_BASE + 0x0040U) +#define RALLOC_INSFC (RALLOC_BASE + 0x0050U) +#define RALLOC_BERR (RALLOC_BASE + 0x0054U) + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +static inline void io_write_32(uintptr_t addr, uint32_t value) +{ + *(volatile uint32_t*)addr = value; +} + +static inline void io_write_64(uintptr_t addr, uint64_t value) +{ + *(volatile uint64_t*)addr = value; +} + +typedef struct { + uintptr_t addr; + uint64_t value; +} mstat_slot_t; + + +#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT +static const mstat_slot_t mstat_fix[] = { + {0x0000U, 0x0000000000000000U}, + {0x0008U, 0x0000000000000000U}, + {0x0010U, 0x0000000000000000U}, + {0x0018U, 0x0000000000000000U}, + {0x0020U, 0x0000000000000000U}, + {0x0028U, 0x0000000000000000U}, + {0x0030U, 0x0000000000000000U}, + {0x0038U, 0x0000000000000000U}, + {0x0040U, 0x00140C060000FFFFU}, + {0x0048U, 0x0000000000000000U}, + {0x0050U, 0x0000000000000000U}, + {0x0058U, 0x001408070000FFFFU}, + {0x0060U, 0x001414140000FFFFU}, + {0x0068U, 0x0000000000000000U}, + {0x0070U, 0x0000000000000000U}, + {0x0078U, 0x0000000000000000U}, + {0x0080U, 0x0000000000000000U}, + {0x0088U, 0x00140C060000FFFFU}, + {0x0090U, 0x001414140000FFFFU}, + {0x0098U, 0x001408070000FFFFU}, + {0x00A0U, 0x0000000000000000U}, + {0x00A8U, 0x0000000000000000U}, + {0x00B0U, 0x0000000000000000U}, + {0x00B8U, 0x0000000000000000U}, + {0x00C0U, 0x0000000000000000U}, + {0x00C8U, 0x0000000000000000U}, + {0x00D0U, 0x0000000000000000U}, + {0x00D8U, 0x0000000000000000U}, + {0x00E0U, 0x0000000000000000U}, + {0x00E8U, 0x0000000000000000U}, + {0x00F0U, 0x0000000000000000U}, + {0x00F8U, 0x0000000000000000U}, + {0x0100U, 0x0000000000000000U}, + {0x0108U, 0x0000000000000000U}, + {0x0110U, 0x0000000000000000U}, + {0x0118U, 0x0000000000000000U}, + {0x0120U, 0x0000000000000000U}, + {0x0128U, 0x0000000000000000U}, + {0x0130U, 0x0000000000000000U}, + {0x0138U, 0x001008060000FFFFU}, + {0x0140U, 0x001008060000FFFFU}, + {0x0148U, 0x001008060000FFFFU}, + {0x0150U, 0x001008060000FFFFU}, + {0x0158U, 0x001008060000FFFFU}, + {0x0160U, 0x001008060000FFFFU}, + {0x0168U, 0x001008060000FFFFU}, + {0x0170U, 0x001008060000FFFFU}, + {0x0178U, 0x001008060000FFFFU}, + {0x0180U, 0x001008060000FFFFU}, + {0x0188U, 0x001008060000FFFFU}, + {0x0190U, 0x0010201E0000FFFFU}, + {0x0198U, 0x0010201E0000FFFFU}, + {0x01A0U, 0x001008060000FFFFU}, + {0x01A8U, 0x001008060000FFFFU}, + {0x01B0U, 0x001008060000FFFFU}, + {0x01B8U, 0x0000000000000000U}, + {0x01C0U, 0x0000000000000000U}, + {0x01C8U, 0x0000000000000000U}, + {0x01D0U, 0x0000000000000000U}, + {0x01D8U, 0x0000000000000000U}, + {0x01E0U, 0x0000000000000000U}, + {0x01E8U, 0x0000000000000000U}, + {0x01F0U, 0x0000000000000000U}, + {0x01F8U, 0x0000000000000000U}, + {0x0200U, 0x0000000000000000U}, + {0x0208U, 0x0000000000000000U}, + {0x0210U, 0x0000000000000000U}, + {0x0218U, 0x0000000000000000U}, + {0x0220U, 0x0000000000000000U}, + {0x0228U, 0x0000000000000000U}, + {0x0230U, 0x0000000000000000U}, + {0x0238U, 0x0000000000000000U}, + {0x0240U, 0x0000000000000000U}, + {0x0248U, 0x0000000000000000U}, + {0x0250U, 0x0000000000000000U}, + {0x0258U, 0x0000000000000000U}, + {0x0260U, 0x000C00000000FFFFU}, + {0x0268U, 0x001410010000FFFFU}, + {0x0270U, 0x001404010000FFFFU}, + {0x0278U, 0x000C00000000FFFFU}, + {0x0280U, 0x001400000000FFFFU}, + {0x0288U, 0x001400000000FFFFU}, + {0x0290U, 0x001410010000FFFFU}, + {0x0298U, 0x001404010000FFFFU}, + {0x02A0U, 0x0000000000000000U}, + {0x02A8U, 0x0000000000000000U}, + {0x02B0U, 0x0000000000000000U}, + {0x02B8U, 0x0000000000000000U}, + {0x02C0U, 0x0000000000000000U}, + {0x02C8U, 0x0000000000000000U}, + {0x02D0U, 0x0000000000000000U}, + {0x02D8U, 0x0000000000000000U}, + {0x02E0U, 0x0000000000000000U}, + {0x02E8U, 0x0000000000000000U}, + {0x02F0U, 0x0000000000000000U}, + {0x02F8U, 0x0000000000000000U}, + {0x0300U, 0x0000000000000000U}, + {0x0308U, 0x0000000000000000U}, + {0x0310U, 0x0000000000000000U}, + {0x0318U, 0x0000000000000000U}, + {0x0320U, 0x0000000000000000U}, + {0x0328U, 0x0000000000000000U}, + {0x0330U, 0x0000000000000000U}, + {0x0338U, 0x0000000000000000U}, +}; + +static const mstat_slot_t mstat_be[] = { + {0x0000U, 0x0000000000000000U}, + {0x0008U, 0x0000000000000000U}, + {0x0010U, 0x0000000000000000U}, + {0x0018U, 0x0000000000000000U}, + {0x0020U, 0x001000100C8FFC01U}, + {0x0028U, 0x001000100C8FFC01U}, + {0x0030U, 0x0000000000000000U}, + {0x0038U, 0x0000000000000000U}, + {0x0040U, 0x0000000000000000U}, + {0x0048U, 0x0000000000000000U}, + {0x0050U, 0x001000100C8FFC01U}, + {0x0058U, 0x0000000000000000U}, + {0x0060U, 0x0000000000000000U}, + {0x0068U, 0x001000100C8FFC01U}, + {0x0070U, 0x001000100C8FFC01U}, + {0x0078U, 0x0000000000000000U}, + {0x0080U, 0x0000000000000000U}, + {0x0088U, 0x0000000000000000U}, + {0x0090U, 0x0000000000000000U}, + {0x0098U, 0x0000000000000000U}, + {0x00A0U, 0x001000100C8FFC01U}, + {0x00A8U, 0x001000100C8FFC01U}, + {0x00B0U, 0x001000100C8FFC01U}, + {0x00B8U, 0x001000100C8FFC01U}, + {0x00C0U, 0x001000100C8FFC01U}, + {0x00C8U, 0x001000100C8FFC01U}, + {0x00D0U, 0x001000100C8FFC01U}, + {0x00D8U, 0x002000200C8FFC01U}, + {0x00E0U, 0x002000200C8FFC01U}, + {0x00E8U, 0x001000100C8FFC01U}, + {0x00F0U, 0x001000100C8FFC01U}, + {0x00F8U, 0x001000100C8FFC01U}, + {0x0100U, 0x0000000000000000U}, + {0x0108U, 0x002000200C8FFC01U}, + {0x0110U, 0x001000100C8FFC01U}, + {0x0118U, 0x001000100C8FFC01U}, + {0x0120U, 0x0000000000000000U}, + {0x0128U, 0x002000200C8FFC01U}, + {0x0130U, 0x001000100C8FFC01U}, + {0x0138U, 0x0000000000000000U}, + {0x0140U, 0x0000000000000000U}, + {0x0148U, 0x0000000000000000U}, + {0x0150U, 0x0000000000000000U}, + {0x0158U, 0x0000000000000000U}, + {0x0160U, 0x0000000000000000U}, + {0x0168U, 0x0000000000000000U}, + {0x0170U, 0x0000000000000000U}, + {0x0178U, 0x0000000000000000U}, + {0x0180U, 0x0000000000000000U}, + {0x0188U, 0x0000000000000000U}, + {0x0190U, 0x0000000000000000U}, + {0x0198U, 0x0000000000000000U}, + {0x01A0U, 0x0000000000000000U}, + {0x01A8U, 0x0000000000000000U}, + {0x01B0U, 0x0000000000000000U}, + {0x01B8U, 0x001000100C8FFC01U}, + {0x01C0U, 0x001000700C8FFC01U}, + {0x01C8U, 0x001000700C8FFC01U}, + {0x01D0U, 0x001000700C8FFC01U}, + {0x01D8U, 0x001000700C8FFC01U}, + {0x01E0U, 0x001000100C8FFC01U}, + {0x01E8U, 0x001000000C8FFC01U}, + {0x01F0U, 0x001000100C8FFC01U}, + {0x01F8U, 0x001000100C8FFC01U}, + {0x0200U, 0x001000100C8FFC01U}, + {0x0208U, 0x001000100C8FFC01U}, + {0x0210U, 0x001000100C8FFC01U}, + {0x0218U, 0x001000100C8FFC01U}, + {0x0220U, 0x001000100C8FFC01U}, + {0x0228U, 0x001000100C8FFC01U}, + {0x0230U, 0x001000100C8FFC01U}, + {0x0238U, 0x001000100C8FFC01U}, + {0x0240U, 0x001000100C8FFC01U}, + {0x0248U, 0x001000100C8FFC01U}, + {0x0250U, 0x001000100C8FFC01U}, + {0x0258U, 0x001000100C8FFC01U}, + {0x0260U, 0x001000100C8FFC01U}, + {0x0268U, 0x001000100C8FFC01U}, + {0x0270U, 0x001000100C8FFC01U}, + {0x0278U, 0x001000100C8FFC01U}, + {0x0280U, 0x001000100C8FFC01U}, + {0x0288U, 0x001000100C8FFC01U}, + {0x0290U, 0x001000100C8FFC01U}, + {0x0298U, 0x001000100C8FFC01U}, + {0x02A0U, 0x001000100C8FFC01U}, + {0x02A8U, 0x001000100C8FFC01U}, + {0x02B0U, 0x001000100C8FFC01U}, + {0x02B8U, 0x0000000000000000U}, + {0x02C0U, 0x001000100C8FFC01U}, + {0x02C8U, 0x001000100C8FFC01U}, + {0x02D0U, 0x001000100C8FFC01U}, + {0x02D8U, 0x001000100C8FFC01U}, + {0x02E0U, 0x001000100C8FFC01U}, + {0x02E8U, 0x0000000000000000U}, + {0x02F0U, 0x001000400C8FFC01U}, + {0x02F8U, 0x001000400C8FFC01U}, + {0x0300U, 0x001000100C8FFC01U}, + {0x0308U, 0x001000400C8FFC01U}, + {0x0310U, 0x001000400C8FFC01U}, + {0x0318U, 0x001000100C8FFC01U}, + {0x0320U, 0x001000400C8FFC01U}, + {0x0328U, 0x001000400C8FFC01U}, + {0x0330U, 0x001000400C8FFC01U}, + {0x0338U, 0x001000400C8FFC01U}, +}; +#endif + + +void qos_init_h3_es10(void) +{ + /* DRAM Split Address mapping */ +#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH + NOTICE("BL2: DRAM Split is 4ch\n"); + io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT + | ADSPLCR0_SPLITSEL(0xFFU) + | ADSPLCR0_AREA(0x1BU) + | ADSPLCR0_SWP); + io_write_32(AXI_ADSPLCR1, 0x00000000U); + io_write_32(AXI_ADSPLCR2, 0xA8A90000U); + io_write_32(AXI_ADSPLCR3, 0x00000000U); +#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH + NOTICE("BL2: DRAM Split is 2ch\n"); + io_write_32(AXI_ADSPLCR0, 0x00000000U); + io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT + | ADSPLCR0_SPLITSEL(0xFFU) + | ADSPLCR0_AREA(0x1BU) + | ADSPLCR0_SWP); + io_write_32(AXI_ADSPLCR2, 0x00000000U); + io_write_32(AXI_ADSPLCR3, 0x00000000U); +#else + NOTICE("BL2: DRAM Split is OFF\n"); +#endif + +#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) +#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT + NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); +#endif + + /* AR Cache setting */ + io_write_32(0xE67D1000U, 0x00000100U); + io_write_32(0xE67D1008U, 0x00000100U); + + /* Resource Alloc setting */ + io_write_32(RALLOC_RAS, 0x00000040U); + io_write_32(RALLOC_FIXTH, 0x000F0005U); + io_write_32(RALLOC_RAEN, 0x00000001U); + io_write_32(RALLOC_REGGD, 0x00000004U); + io_write_64(RALLOC_DANN, 0x0202000004040404U); + io_write_32(RALLOC_DANT, 0x003C1110U); + io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 ES1 */ + io_write_64(RALLOC_EMS, 0x0000000000000000U); + io_write_32(RALLOC_INSFC, 0xC7840001U); + io_write_32(RALLOC_BERR, 0x00000000U); + + /* MSTAT setting */ + io_write_32(MSTAT_SL_INIT, 0x0305007DU); + io_write_32(MSTAT_REF_ARS, 0x00330000U); + + /* MSTAT SRAM setting */ + { + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { + io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr, + mstat_fix[i].value); + io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr, + mstat_fix[i].value); + } + for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { + io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr, + mstat_be[i].value); + io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr, + mstat_be[i].value); + } + } + + /* AXI-IF arbitration setting */ + io_write_32(DBSC_AXARB, 0x18010000U); + + /* 3DG bus Leaf setting */ + io_write_32(0xFD820808U, 0x00001234U); + io_write_32(0xFD820800U, 0x0000003FU); + io_write_32(0xFD821800U, 0x0000003FU); + io_write_32(0xFD822800U, 0x0000003FU); + io_write_32(0xFD823800U, 0x0000003FU); + io_write_32(0xFD824800U, 0x0000003FU); + io_write_32(0xFD825800U, 0x0000003FU); + io_write_32(0xFD826800U, 0x0000003FU); + io_write_32(0xFD827800U, 0x0000003FU); + + /* Resource Alloc start */ + io_write_32(RALLOC_RAEN, 0x00000001U); + + /* MSTAT start */ + io_write_32(MSTAT_STATQC, 0x00000001U); +#else + NOTICE("BL2: QoS is None\n"); + + /* Resource Alloc setting */ + io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 ES1 */ +#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/H3/ES10/qos_init_h3_es10.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/H3/ES10/qos_init_h3_es10.h new file mode 100644 index 0000000..62d1a87 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/H3/ES10/qos_init_h3_es10.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef QOS_INIT_H_H3_ES10__ +#define QOS_INIT_H_H3_ES10__ + +void qos_init_h3_es10(void); + +#endif /* QOS_INIT_H_H3_ES10__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/H3/WS11/qos_init_h3_ws11.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/H3/WS11/qos_init_h3_ws11.c new file mode 100644 index 0000000..017b182 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/H3/WS11/qos_init_h3_ws11.c @@ -0,0 +1,593 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "qos_init_h3_ws11.h" + + +#define RCAR_QOS_VERSION "rev.0.31" + +#define RCAR_QOS_NONE (3U) +#define RCAR_QOS_TYPE_DEFAULT (0U) + +#define RCAR_DRAM_SPLIT_LINEAR (0U) +#define RCAR_DRAM_SPLIT_4CH (1U) +#define RCAR_DRAM_SPLIT_2CH (2U) + +#define RST_BASE (0xE6160000U) +#define RST_MODEMR (RST_BASE + 0x0060U) + +#define DBSC_BASE (0xE6790000U) +#define DBSC_AXARB (DBSC_BASE + 0x0800U) +#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U) +#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) +#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) +#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU) +#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) +#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U) +#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) +#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U) +#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) +#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) +#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) +#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) +#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U) +#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U) +#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U) +#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU) +#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U) +#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U) +#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U) +#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU) +#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U) +#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U) +#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U) +#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) +#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) +#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) +#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) +#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U) +#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U) +#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U) +#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU) +#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U) +#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U) +#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U) +#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU) +#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U) +#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U) +#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U) +#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU) +#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U) +#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U) +#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U) +#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU) +#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) +#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) +#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) +#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) +#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U) +#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U) +#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U) +#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU) +#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U) +#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U) +#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U) +#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU) +#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) +#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) +#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) +#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) +#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) +#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) +#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) +#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) +#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) +#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) +#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) +#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) +#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) + +#define AXI_BASE (0xE6784000U) +#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U) +#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU) +#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U) +#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U) +#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U) +#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U) +#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U) +#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U) +#define ADSPLCR0_SWP (0x0CU) + +#define MSTAT_BASE (0xE67E0000U) +#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U) +#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U) +#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U) +#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U) +#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U) +#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U) +#define MSTAT_STATQC (MSTAT_BASE + 0x8008U) + +#define RALLOC_BASE (0xE67F0000U) +#define RALLOC_RAS (RALLOC_BASE + 0x0000U) +#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U) +#define RALLOC_RAEN (RALLOC_BASE + 0x0018U) +#define RALLOC_REGGD (RALLOC_BASE + 0x0020U) +#define RALLOC_DANN (RALLOC_BASE + 0x0030U) +#define RALLOC_DANT (RALLOC_BASE + 0x0038U) +#define RALLOC_EC (RALLOC_BASE + 0x003CU) +#define RALLOC_EMS (RALLOC_BASE + 0x0040U) +#define RALLOC_INSFC (RALLOC_BASE + 0x0050U) +#define RALLOC_BERR (RALLOC_BASE + 0x0054U) +#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U) + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +static inline void io_write_32(uintptr_t addr, uint32_t value) +{ + *(volatile uint32_t*)addr = value; +} + +static inline void io_write_64(uintptr_t addr, uint64_t value) +{ + *(volatile uint64_t*)addr = value; +} + +typedef struct { + uintptr_t addr; + uint64_t value; +} mstat_slot_t; + + +#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT +static const mstat_slot_t mstat_fix[] = { + {0x0000U, 0x0000000000000000U}, + {0x0008U, 0x0000000000000000U}, + {0x0010U, 0x0000000000000000U}, + {0x0018U, 0x0000000000000000U}, + {0x0020U, 0x0000000000000000U}, + {0x0028U, 0x0000000000000000U}, + {0x0030U, 0x0000000000000000U}, + {0x0038U, 0x0000000000000000U}, + {0x0040U, 0x00140C060000FFFFU}, + {0x0048U, 0x0000000000000000U}, + {0x0050U, 0x0000000000000000U}, + {0x0058U, 0x001408070000FFFFU}, + {0x0060U, 0x001414140000FFFFU}, + {0x0068U, 0x0000000000000000U}, + {0x0070U, 0x0000000000000000U}, + {0x0078U, 0x0000000000000000U}, + {0x0080U, 0x0000000000000000U}, + {0x0088U, 0x00140C060000FFFFU}, + {0x0090U, 0x001414140000FFFFU}, + {0x0098U, 0x001408070000FFFFU}, + {0x00A0U, 0x0000000000000000U}, + {0x00A8U, 0x0000000000000000U}, + {0x00B0U, 0x0000000000000000U}, + {0x00B8U, 0x0000000000000000U}, + {0x00C0U, 0x0000000000000000U}, + {0x00C8U, 0x0000000000000000U}, + {0x00D0U, 0x0000000000000000U}, + {0x00D8U, 0x0000000000000000U}, + {0x00E0U, 0x0000000000000000U}, + {0x00E8U, 0x0000000000000000U}, + {0x00F0U, 0x0000000000000000U}, + {0x00F8U, 0x0000000000000000U}, + {0x0100U, 0x0000000000000000U}, + {0x0108U, 0x0000000000000000U}, + {0x0110U, 0x0000000000000000U}, + {0x0118U, 0x0000000000000000U}, + {0x0120U, 0x0000000000000000U}, + {0x0128U, 0x0000000000000000U}, + {0x0130U, 0x0000000000000000U}, + {0x0138U, 0x001008060000FFFFU}, + {0x0140U, 0x001008060000FFFFU}, + {0x0148U, 0x001008060000FFFFU}, + {0x0150U, 0x001008060000FFFFU}, + {0x0158U, 0x001008060000FFFFU}, + {0x0160U, 0x001008060000FFFFU}, + {0x0168U, 0x001008060000FFFFU}, + {0x0170U, 0x001008060000FFFFU}, + {0x0178U, 0x001008060000FFFFU}, + {0x0180U, 0x001008060000FFFFU}, + {0x0188U, 0x001008060000FFFFU}, + {0x0190U, 0x0010201E0000FFFFU}, + {0x0198U, 0x0010201E0000FFFFU}, + {0x01A0U, 0x001008060000FFFFU}, + {0x01A8U, 0x001008060000FFFFU}, + {0x01B0U, 0x001008060000FFFFU}, + {0x01B8U, 0x0000000000000000U}, + {0x01C0U, 0x0000000000000000U}, + {0x01C8U, 0x0000000000000000U}, + {0x01D0U, 0x0000000000000000U}, + {0x01D8U, 0x0000000000000000U}, + {0x01E0U, 0x0000000000000000U}, + {0x01E8U, 0x0000000000000000U}, + {0x01F0U, 0x0000000000000000U}, + {0x01F8U, 0x0000000000000000U}, + {0x0200U, 0x0000000000000000U}, + {0x0208U, 0x0000000000000000U}, + {0x0210U, 0x0000000000000000U}, + {0x0218U, 0x0000000000000000U}, + {0x0220U, 0x0000000000000000U}, + {0x0228U, 0x0000000000000000U}, + {0x0230U, 0x0000000000000000U}, + {0x0238U, 0x0000000000000000U}, + {0x0240U, 0x0000000000000000U}, + {0x0248U, 0x0000000000000000U}, + {0x0250U, 0x0000000000000000U}, + {0x0258U, 0x0000000000000000U}, + {0x0260U, 0x000C00000000FFFFU}, + {0x0268U, 0x001410010000FFFFU}, + {0x0270U, 0x001404010000FFFFU}, + {0x0278U, 0x000C00000000FFFFU}, + {0x0280U, 0x001400000000FFFFU}, + {0x0288U, 0x001400000000FFFFU}, + {0x0290U, 0x001410010000FFFFU}, + {0x0298U, 0x001404010000FFFFU}, + {0x02A0U, 0x0000000000000000U}, + {0x02A8U, 0x0000000000000000U}, + {0x02B0U, 0x0000000000000000U}, + {0x02B8U, 0x0000000000000000U}, + {0x02C0U, 0x0000000000000000U}, + {0x02C8U, 0x0000000000000000U}, + {0x02D0U, 0x0000000000000000U}, + {0x02D8U, 0x0000000000000000U}, + {0x02E0U, 0x0000000000000000U}, + {0x02E8U, 0x0000000000000000U}, + {0x02F0U, 0x0000000000000000U}, + {0x02F8U, 0x0000000000000000U}, + {0x0300U, 0x0000000000000000U}, + {0x0308U, 0x0000000000000000U}, + {0x0310U, 0x0000000000000000U}, + {0x0318U, 0x0000000000000000U}, + {0x0320U, 0x0000000000000000U}, + {0x0328U, 0x0000000000000000U}, + {0x0330U, 0x0000000000000000U}, + {0x0338U, 0x0000000000000000U}, +}; + +static const mstat_slot_t mstat_be[] = { + {0x0000U, 0x0000000000000000U}, + {0x0008U, 0x0000000000000000U}, + {0x0010U, 0x0000000000000000U}, + {0x0018U, 0x0000000000000000U}, + {0x0020U, 0x001000100C8FFC01U}, + {0x0028U, 0x001000100C8FFC01U}, + {0x0030U, 0x0000000000000000U}, + {0x0038U, 0x0000000000000000U}, + {0x0040U, 0x0000000000000000U}, + {0x0048U, 0x0000000000000000U}, + {0x0050U, 0x001000100C8FFC01U}, + {0x0058U, 0x0000000000000000U}, + {0x0060U, 0x0000000000000000U}, + {0x0068U, 0x001000100C8FFC01U}, + {0x0070U, 0x001000100C8FFC01U}, + {0x0078U, 0x0000000000000000U}, + {0x0080U, 0x0000000000000000U}, + {0x0088U, 0x0000000000000000U}, + {0x0090U, 0x0000000000000000U}, + {0x0098U, 0x0000000000000000U}, + {0x00A0U, 0x001000100C8FFC01U}, + {0x00A8U, 0x001000100C8FFC01U}, + {0x00B0U, 0x001000100C8FFC01U}, + {0x00B8U, 0x001000100C8FFC01U}, + {0x00C0U, 0x001000100C8FFC01U}, + {0x00C8U, 0x001000100C8FFC01U}, + {0x00D0U, 0x001000100C8FFC01U}, + {0x00D8U, 0x002000200C8FFC01U}, + {0x00E0U, 0x002000200C8FFC01U}, + {0x00E8U, 0x001000100C8FFC01U}, + {0x00F0U, 0x001000100C8FFC01U}, + {0x00F8U, 0x001000100C8FFC01U}, + {0x0100U, 0x0000000000000000U}, + {0x0108U, 0x002000200C8FFC01U}, + {0x0110U, 0x001000100C8FFC01U}, + {0x0118U, 0x001000100C8FFC01U}, + {0x0120U, 0x0000000000000000U}, + {0x0128U, 0x002000200C8FFC01U}, + {0x0130U, 0x001000100C8FFC01U}, + {0x0138U, 0x0000000000000000U}, + {0x0140U, 0x0000000000000000U}, + {0x0148U, 0x0000000000000000U}, + {0x0150U, 0x0000000000000000U}, + {0x0158U, 0x0000000000000000U}, + {0x0160U, 0x0000000000000000U}, + {0x0168U, 0x0000000000000000U}, + {0x0170U, 0x0000000000000000U}, + {0x0178U, 0x0000000000000000U}, + {0x0180U, 0x0000000000000000U}, + {0x0188U, 0x0000000000000000U}, + {0x0190U, 0x0000000000000000U}, + {0x0198U, 0x0000000000000000U}, + {0x01A0U, 0x0000000000000000U}, + {0x01A8U, 0x0000000000000000U}, + {0x01B0U, 0x0000000000000000U}, + {0x01B8U, 0x001000100C8FFC01U}, + {0x01C0U, 0x001000700C8FFC01U}, + {0x01C8U, 0x001000700C8FFC01U}, + {0x01D0U, 0x001000700C8FFC01U}, + {0x01D8U, 0x001000700C8FFC01U}, + {0x01E0U, 0x001000100C8FFC01U}, + {0x01E8U, 0x001000000C8FFC01U}, + {0x01F0U, 0x001000100C8FFC01U}, + {0x01F8U, 0x001000100C8FFC01U}, + {0x0200U, 0x001000100C8FFC01U}, + {0x0208U, 0x001000100C8FFC01U}, + {0x0210U, 0x001000100C8FFC01U}, + {0x0218U, 0x001000100C8FFC01U}, + {0x0220U, 0x001000100C8FFC01U}, + {0x0228U, 0x001000100C8FFC01U}, + {0x0230U, 0x001000100C8FFC01U}, + {0x0238U, 0x001000100C8FFC01U}, + {0x0240U, 0x001000100C8FFC01U}, + {0x0248U, 0x001000100C8FFC01U}, + {0x0250U, 0x001000100C8FFC01U}, + {0x0258U, 0x001000100C8FFC01U}, + {0x0260U, 0x001000100C8FFC01U}, + {0x0268U, 0x001000100C8FFC01U}, + {0x0270U, 0x001000100C8FFC01U}, + {0x0278U, 0x001000100C8FFC01U}, + {0x0280U, 0x001000100C8FFC01U}, + {0x0288U, 0x001000100C8FFC01U}, + {0x0290U, 0x001000100C8FFC01U}, + {0x0298U, 0x001000100C8FFC01U}, + {0x02A0U, 0x001000100C8FFC01U}, + {0x02A8U, 0x001000100C8FFC01U}, + {0x02B0U, 0x001000100C8FFC01U}, + {0x02B8U, 0x0000000000000000U}, + {0x02C0U, 0x001000100C8FFC01U}, + {0x02C8U, 0x001000100C8FFC01U}, + {0x02D0U, 0x001000100C8FFC01U}, + {0x02D8U, 0x001000100C8FFC01U}, + {0x02E0U, 0x001000100C8FFC01U}, + {0x02E8U, 0x0000000000000000U}, + {0x02F0U, 0x001000400C8FFC01U}, + {0x02F8U, 0x001000400C8FFC01U}, + {0x0300U, 0x001000100C8FFC01U}, + {0x0308U, 0x001000400C8FFC01U}, + {0x0310U, 0x001000400C8FFC01U}, + {0x0318U, 0x001000100C8FFC01U}, + {0x0320U, 0x001000400C8FFC01U}, + {0x0328U, 0x001000400C8FFC01U}, + {0x0330U, 0x001000400C8FFC01U}, + {0x0338U, 0x001000400C8FFC01U}, +}; +#endif + +static void dbsc_setting(void) +{ + uint32_t md=0; + + /* BUFCAM settings */ + //DBSC_DBCAM0CNF0 not set + io_write_32(DBSC_DBCAM0CNF1, 0x00044218); //dbcam0cnf1 + io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2 + //DBSC_DBCAM0CNF3 not set + io_write_32(DBSC_DBSCHCNT0, 0x080F0037); //dbschcnt0 + io_write_32(DBSC_DBSCHCNT1, 0x00001010); //dbschcnt1 + io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0 + io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0 + io_write_32(DBSC_DBSCHRW1, 0x00180034); //dbschrw1 + + md = (*((volatile uint32_t*)RST_MODEMR) & 0x000A0000) >> 17; + + switch (md) { + case 0x0: + /* DDR3200 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + case 0x1: //MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) + /* DDR2800 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + case 0x4: //MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) + /* DDR2400 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + default: //MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) + /* DDR1600 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + } + + /* QoS Settings */ + io_write_32(DBSC_DBSCHQOS_0_0, 0x0000F000); + io_write_32(DBSC_DBSCHQOS_0_1, 0x0000E000); + io_write_32(DBSC_DBSCHQOS_0_2, 0x00007000); + io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000); + //DBSC_DBSCHQOS_1_0 not set + //DBSC_DBSCHQOS_1_1 not set + //DBSC_DBSCHQOS_1_2 not set + //DBSC_DBSCHQOS_1_3 not set + //DBSC_DBSCHQOS_2_0 not set + //DBSC_DBSCHQOS_2_1 not set + //DBSC_DBSCHQOS_2_2 not set + //DBSC_DBSCHQOS_2_3 not set + //DBSC_DBSCHQOS_3_0 not set + //DBSC_DBSCHQOS_3_1 not set + //DBSC_DBSCHQOS_3_2 not set + //DBSC_DBSCHQOS_3_3 not set + io_write_32(DBSC_DBSCHQOS_4_0, 0x0000F000); + io_write_32(DBSC_DBSCHQOS_4_1, 0x0000EFFF); + io_write_32(DBSC_DBSCHQOS_4_2, 0x0000B000); + io_write_32(DBSC_DBSCHQOS_4_3, 0x00000000); + //DBSC_DBSCHQOS_5_0 not set + //DBSC_DBSCHQOS_5_1 not set + //DBSC_DBSCHQOS_5_2 not set + //DBSC_DBSCHQOS_5_3 not set + //DBSC_DBSCHQOS_6_0 not set + //DBSC_DBSCHQOS_6_1 not set + //DBSC_DBSCHQOS_6_2 not set + //DBSC_DBSCHQOS_6_3 not set + //DBSC_DBSCHQOS_7_0 not set + //DBSC_DBSCHQOS_7_1 not set + //DBSC_DBSCHQOS_7_2 not set + //DBSC_DBSCHQOS_7_3 not set + //DBSC_DBSCHQOS_8_0 not set + //DBSC_DBSCHQOS_8_1 not set + //DBSC_DBSCHQOS_8_2 not set + //DBSC_DBSCHQOS_8_3 not set + io_write_32(DBSC_DBSCHQOS_9_0, 0x0000F000); + io_write_32(DBSC_DBSCHQOS_9_1, 0x0000EFFF); + io_write_32(DBSC_DBSCHQOS_9_2, 0x0000D000); + io_write_32(DBSC_DBSCHQOS_9_3, 0x00000000); + //DBSC_DBSCHQOS_10_0 not set + //DBSC_DBSCHQOS_10_1 not set + //DBSC_DBSCHQOS_10_2 not set + //DBSC_DBSCHQOS_10_3 not set + //DBSC_DBSCHQOS_11_0 not set + //DBSC_DBSCHQOS_11_1 not set + //DBSC_DBSCHQOS_11_2 not set + //DBSC_DBSCHQOS_11_3 not set + //DBSC_DBSCHQOS_12_0 not set + //DBSC_DBSCHQOS_12_1 not set + //DBSC_DBSCHQOS_12_2 not set + //DBSC_DBSCHQOS_12_3 not set + io_write_32(DBSC_DBSCHQOS_13_0, 0x0000F000); + io_write_32(DBSC_DBSCHQOS_13_1, 0x0000EFFF); + io_write_32(DBSC_DBSCHQOS_13_2, 0x0000E800); + io_write_32(DBSC_DBSCHQOS_13_3, 0x00007000); + io_write_32(DBSC_DBSCHQOS_14_0, 0x0000F000); + io_write_32(DBSC_DBSCHQOS_14_1, 0x0000EFFF); + io_write_32(DBSC_DBSCHQOS_14_2, 0x0000E800); + io_write_32(DBSC_DBSCHQOS_14_3, 0x0000B000); + io_write_32(DBSC_DBSCHQOS_15_0, 0x000007D0); + io_write_32(DBSC_DBSCHQOS_15_1, 0x000007CF); + io_write_32(DBSC_DBSCHQOS_15_2, 0x000005D0); + io_write_32(DBSC_DBSCHQOS_15_3, 0x000003D0); +} + +void qos_init_h3_ws11(void) +{ + dbsc_setting(); + + /* DRAM Split Address mapping */ +#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH + NOTICE("BL2: DRAM Split is 4ch\n"); + io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT + | ADSPLCR0_SPLITSEL(0xFFU) + | ADSPLCR0_AREA(0x1BU) + | ADSPLCR0_SWP); + io_write_32(AXI_ADSPLCR1, 0x00000000U); + io_write_32(AXI_ADSPLCR2, 0xA8A90000U); + io_write_32(AXI_ADSPLCR3, 0x00000000U); +#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH + NOTICE("BL2: DRAM Split is 2ch\n"); + io_write_32(AXI_ADSPLCR0, 0x00000000U); + io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT + | ADSPLCR0_SPLITSEL(0xFFU) + | ADSPLCR0_AREA(0x1BU) + | ADSPLCR0_SWP); + io_write_32(AXI_ADSPLCR2, 0x00000000U); + io_write_32(AXI_ADSPLCR3, 0x00000000U); +#else + NOTICE("BL2: DRAM Split is OFF\n"); +#endif + +#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) +#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT + NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); +#endif + + /* AR Cache setting */ + io_write_32(0xE67D1000U, 0x00000100U); + io_write_32(0xE67D1008U, 0x00000100U); + + /* Resource Alloc setting */ + io_write_32(RALLOC_RAS, 0x00000040U); + io_write_32(RALLOC_FIXTH, 0x000F0005U); + io_write_32(RALLOC_RAEN, 0x00000001U); + io_write_32(RALLOC_REGGD, 0x00000000U); + io_write_64(RALLOC_DANN, 0x0202000004040404U); + io_write_32(RALLOC_DANT, 0x003C1110U); + io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 ES1 */ + io_write_64(RALLOC_EMS, 0x0000000000000000U); + io_write_32(RALLOC_INSFC, 0xC7840001U); + io_write_32(RALLOC_BERR, 0x00000000U); + io_write_32(RALLOC_RACNT0, 0x00000000U); + + /* MSTAT setting */ + io_write_32(MSTAT_SL_INIT, 0x0305007DU); + io_write_32(MSTAT_REF_ARS, 0x00330000U); + + /* MSTAT SRAM setting */ + { + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { + io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr, + mstat_fix[i].value); + io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr, + mstat_fix[i].value); + } + for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { + io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr, + mstat_be[i].value); + io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr, + mstat_be[i].value); + } + } + + /* AXI-IF arbitration setting */ + io_write_32(DBSC_AXARB, 0x18010000U); + + /* 3DG bus Leaf setting */ + io_write_32(0xFD820808U, 0x00001234U); + io_write_32(0xFD820800U, 0x0000003FU); + io_write_32(0xFD821800U, 0x0000003FU); + io_write_32(0xFD822800U, 0x0000003FU); + io_write_32(0xFD823800U, 0x0000003FU); + io_write_32(0xFD824800U, 0x0000003FU); + io_write_32(0xFD825800U, 0x0000003FU); + io_write_32(0xFD826800U, 0x0000003FU); + io_write_32(0xFD827800U, 0x0000003FU); + + /* Resource Alloc start */ + io_write_32(RALLOC_RAEN, 0x00000001U); + + /* MSTAT start */ + io_write_32(MSTAT_STATQC, 0x00000001U); +#else + NOTICE("BL2: QoS is None\n"); + + /* Resource Alloc setting */ + io_write_32(RALLOC_EC, 0x00080001U); /* need for H3 ES1 */ +#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/H3/WS11/qos_init_h3_ws11.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/H3/WS11/qos_init_h3_ws11.h new file mode 100644 index 0000000..820e732 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/H3/WS11/qos_init_h3_ws11.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef QOS_INIT_H_H3_WS11__ +#define QOS_INIT_H_H3_WS11__ + +void qos_init_h3_ws11(void); + +#endif /* QOS_INIT_H_H3_WS11__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/M3/qos_init_m3_es10.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/M3/qos_init_m3_es10.c new file mode 100644 index 0000000..3bc1077 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/M3/qos_init_m3_es10.c @@ -0,0 +1,601 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "qos_init_m3_es10.h" + + +#define RCAR_QOS_VERSION "rev.0.14" + +#define RCAR_QOS_NONE (3U) +#define RCAR_QOS_TYPE_DEFAULT (0U) + +#define RCAR_DRAM_SPLIT_LINEAR (0U) +#define RCAR_DRAM_SPLIT_4CH (1U) +#define RCAR_DRAM_SPLIT_2CH (2U) + +#define RST_BASE (0xE6160000U) +#define RST_MODEMR (RST_BASE + 0x0060U) + +#define DBSC_BASE (0xE6790000U) +#define DBSC_AXARB (DBSC_BASE + 0x0800U) +#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U) +#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) +#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) +#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU) +#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) +#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U) +#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) +#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U) +#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) +#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) +#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) +#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) +#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U) +#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U) +#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U) +#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU) +#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U) +#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U) +#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U) +#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU) +#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U) +#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U) +#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U) +#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) +#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) +#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) +#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) +#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U) +#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U) +#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U) +#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU) +#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U) +#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U) +#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U) +#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU) +#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U) +#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U) +#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U) +#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU) +#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U) +#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U) +#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U) +#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU) +#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) +#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) +#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) +#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) +#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U) +#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U) +#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U) +#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU) +#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U) +#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U) +#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U) +#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU) +#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) +#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) +#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) +#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) +#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) +#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) +#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) +#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) +#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) +#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) +#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) +#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) +#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) + +#define AXI_BASE (0xE6784000U) +#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U) +#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU) +#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U) +#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U) +#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U) +#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U) +#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U) +#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U) +#define ADSPLCR0_SWP (0x0CU) + +#define MSTAT_BASE (0xE67E0000U) +#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U) +#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U) +#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U) +#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U) +#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U) +#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U) +#define MSTAT_STATQC (MSTAT_BASE + 0x8008U) + +#define RALLOC_BASE (0xE67F0000U) +#define RALLOC_RAS (RALLOC_BASE + 0x0000U) +#define RALLOC_FIXTH (RALLOC_BASE + 0x0004U) +#define RALLOC_RAEN (RALLOC_BASE + 0x0018U) +#define RALLOC_REGGD (RALLOC_BASE + 0x0020U) +#define RALLOC_DANN (RALLOC_BASE + 0x0030U) +#define RALLOC_DANT (RALLOC_BASE + 0x0038U) +#define RALLOC_EC (RALLOC_BASE + 0x003CU) +#define RALLOC_EMS (RALLOC_BASE + 0x0040U) +#define RALLOC_INSFC (RALLOC_BASE + 0x0050U) +#define RALLOC_BERR (RALLOC_BASE + 0x0054U) +#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U) + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +static inline void io_write_32(uintptr_t addr, uint32_t value) +{ + *(volatile uint32_t*)addr = value; +} + +static inline void io_write_64(uintptr_t addr, uint64_t value) +{ + *(volatile uint64_t*)addr = value; +} + +typedef struct { + uintptr_t addr; + uint64_t value; +} mstat_slot_t; + + +#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT +static const mstat_slot_t mstat_fix[] = { + {0x0000U, 0x0000000000000000U}, + {0x0008U, 0x0000000000000000U}, + {0x0010U, 0x0000000000000000U}, + {0x0018U, 0x0000000000000000U}, + {0x0020U, 0x0000000000000000U}, + {0x0028U, 0x0000000000000000U}, + {0x0030U, 0x0000000000000000U}, + {0x0038U, 0x0000000000000000U}, + {0x0040U, 0x001408030000FFFFU}, + {0x0048U, 0x0000000000000000U}, + {0x0050U, 0x0000000000000000U}, + {0x0058U, 0x001404030000FFFFU}, + {0x0060U, 0x001408060000FFFFU}, + {0x0068U, 0x0000000000000000U}, + {0x0070U, 0x0000000000000000U}, + {0x0078U, 0x0000000000000000U}, + {0x0080U, 0x0000000000000000U}, + {0x0088U, 0x001404020000FFFFU}, + {0x0090U, 0x001404020000FFFFU}, + {0x0098U, 0x0000000000000000U}, + {0x00A0U, 0x0000000000000000U}, + {0x00A8U, 0x0000000000000000U}, + {0x00B0U, 0x0000000000000000U}, + {0x00B8U, 0x0000000000000000U}, + {0x00C0U, 0x0000000000000000U}, + {0x00C8U, 0x0000000000000000U}, + {0x00D0U, 0x0000000000000000U}, + {0x00D8U, 0x0000000000000000U}, + {0x00E0U, 0x0000000000000000U}, + {0x00E8U, 0x0000000000000000U}, + {0x00F0U, 0x0000000000000000U}, + {0x00F8U, 0x0000000000000000U}, + {0x0100U, 0x0000000000000000U}, + {0x0108U, 0x0000000000000000U}, + {0x0110U, 0x0000000000000000U}, + {0x0118U, 0x0000000000000000U}, + {0x0120U, 0x0000000000000000U}, + {0x0128U, 0x0000000000000000U}, + {0x0130U, 0x0000000000000000U}, + {0x0138U, 0x0000000000000000U}, + {0x0140U, 0x0000000000000000U}, + {0x0148U, 0x0000000000000000U}, + {0x0150U, 0x0000000000000000U}, + {0x0158U, 0x0000000000000000U}, + {0x0160U, 0x0000000000000000U}, + {0x0168U, 0x0000000000000000U}, + {0x0170U, 0x0000000000000000U}, + {0x0178U, 0x0000000000000000U}, + {0x0180U, 0x0000000000000000U}, + {0x0188U, 0x0000000000000000U}, + {0x0190U, 0x0000000000000000U}, + {0x0198U, 0x0000000000000000U}, + {0x01A0U, 0x0000000000000000U}, + {0x01A8U, 0x0000000000000000U}, + {0x01B0U, 0x0000000000000000U}, + {0x01B8U, 0x0000000000000000U}, + {0x01C0U, 0x0000000000000000U}, + {0x01C8U, 0x0000000000000000U}, + {0x01D0U, 0x0000000000000000U}, + {0x01D8U, 0x0000000000000000U}, + {0x01E0U, 0x0000000000000000U}, + {0x01E8U, 0x0000000000000000U}, + {0x01F0U, 0x0000000000000000U}, + {0x01F8U, 0x0000000000000000U}, + {0x0200U, 0x0000000000000000U}, + {0x0208U, 0x0000000000000000U}, + {0x0210U, 0x0000000000000000U}, + {0x0218U, 0x0000000000000000U}, + {0x0220U, 0x0000000000000000U}, + {0x0228U, 0x0000000000000000U}, + {0x0230U, 0x0000000000000000U}, + {0x0238U, 0x0000000000000000U}, + {0x0240U, 0x0000000000000000U}, + {0x0248U, 0x0000000000000000U}, + {0x0250U, 0x0000000000000000U}, + {0x0258U, 0x0000000000000000U}, + {0x0260U, 0x0000000000000000U}, + {0x0268U, 0x0000000000000000U}, + {0x0270U, 0x0000000000000000U}, + {0x0278U, 0x0000000000000000U}, + {0x0280U, 0x0000000000000000U}, + {0x0288U, 0x0000000000000000U}, + {0x0290U, 0x0000000000000000U}, + {0x0298U, 0x0000000000000000U}, + {0x02A0U, 0x0000000000000000U}, + {0x02A8U, 0x0000000000000000U}, + {0x02B0U, 0x001404010000FFFFU}, + {0x02B8U, 0x0000000000000000U}, + {0x02C0U, 0x0000000000000000U}, + {0x02C8U, 0x0000000000000000U}, + {0x02D0U, 0x0000000000000000U}, + {0x02D8U, 0x0000000000000000U}, + {0x02E0U, 0x001404010000FFFFU}, + {0x02E8U, 0x0000000000000000U}, + {0x02F0U, 0x0000000000000000U}, + {0x02F8U, 0x0000000000000000U}, + {0x0300U, 0x0000000000000000U}, + {0x0308U, 0x0000000000000000U}, + {0x0310U, 0x0000000000000000U}, + {0x0318U, 0x0000000000000000U}, + {0x0320U, 0x0000000000000000U}, + {0x0328U, 0x0000000000000000U}, + {0x0330U, 0x0000000000000000U}, + {0x0338U, 0x0000000000000000U}, + {0x0340U, 0x0000000000000000U}, + {0x0348U, 0x0000000000000000U}, + {0x0350U, 0x0000000000000000U}, +}; + +static const mstat_slot_t mstat_be[] = { + {0x0000U, 0x001000100C89C401U}, + {0x0008U, 0x001000100C89C401U}, + {0x0010U, 0x001000100C89C401U}, + {0x0018U, 0x001000100C89C401U}, + {0x0020U, 0x0000000000000000U}, + {0x0028U, 0x001000100C803401U}, + {0x0030U, 0x0000000000000000U}, + {0x0038U, 0x0000000000000000U}, + {0x0040U, 0x0000000000000000U}, + {0x0048U, 0x0000000000000000U}, + {0x0050U, 0x001000100C803401U}, + {0x0058U, 0x0000000000000000U}, + {0x0060U, 0x0000000000000000U}, + {0x0068U, 0x001000100C803401U}, + {0x0070U, 0x001000100C803401U}, + {0x0078U, 0x0000000000000000U}, + {0x0080U, 0x0000000000000000U}, + {0x0088U, 0x0000000000000000U}, + {0x0090U, 0x0000000000000000U}, + {0x0098U, 0x0000000000000000U}, + {0x00A0U, 0x001000100C86A401U}, + {0x00A8U, 0x001000100C81F401U}, + {0x00B0U, 0x001000100C80FC01U}, + {0x00B8U, 0x001000000C800401U}, + {0x00C0U, 0x001000100C86A401U}, + {0x00C8U, 0x001000100C81F401U}, + {0x00D0U, 0x001000100C80FC01U}, + {0x00D8U, 0x002000200C8FFC01U}, + {0x00E0U, 0x002000200C8FFC01U}, + {0x00E8U, 0x0000000000000000U}, + {0x00F0U, 0x001000100C87D001U}, + {0x00F8U, 0x0000000000000000U}, + {0x0100U, 0x002000100C89C401U}, + {0x0108U, 0x0000000000000000U}, + {0x0110U, 0x001000100C83E801U}, + {0x0118U, 0x0000000000000000U}, + {0x0120U, 0x002000100C89C401U}, + {0x0128U, 0x002000200C8FFC01U}, + {0x0130U, 0x0000000000000000U}, + {0x0138U, 0x002000200C8FFC01U}, + {0x0140U, 0x0000000000000000U}, + {0x0148U, 0x0000000000000000U}, + {0x0150U, 0x002000300C8FFC01U}, + {0x0158U, 0x0000000000000000U}, + {0x0160U, 0x002000200C8FFC01U}, + {0x0168U, 0x0000000000000000U}, + {0x0170U, 0x0000000000000000U}, + {0x0178U, 0x002000100C89C401U}, + {0x0180U, 0x0000000000000000U}, + {0x0188U, 0x0000000000000000U}, + {0x0190U, 0x002000500C8FFC01U}, + {0x0198U, 0x0000000000000000U}, + {0x01A0U, 0x002000200C8FFC01U}, + {0x01A8U, 0x0000000000000000U}, + {0x01B0U, 0x0000000000000000U}, + {0x01B8U, 0x0000000000000000U}, + {0x01C0U, 0x001000200C8FFC01U}, + {0x01C8U, 0x001000200C8FFC01U}, + {0x01D0U, 0x001000200C8FFC01U}, + {0x01D8U, 0x001000200C8FFC01U}, + {0x01E0U, 0x001000100C80FC01U}, + {0x01E8U, 0x001000000C800401U}, + {0x01F0U, 0x001000100C80FC01U}, + {0x01F8U, 0x0000000000000000U}, + {0x0200U, 0x001000100C80FC01U}, + {0x0208U, 0x001000100C80FC01U}, + {0x0210U, 0x001000100C80FC01U}, + {0x0218U, 0x001000100C80FC01U}, + {0x0220U, 0x001000100C80FC01U}, + {0x0228U, 0x0000000000000000U}, + {0x0230U, 0x001000100C80FC01U}, + {0x0238U, 0x001000100C80FC01U}, + {0x0240U, 0x001000100C81F401U}, + {0x0248U, 0x001000100C81F401U}, + {0x0250U, 0x001000100C81F401U}, + {0x0258U, 0x001000100C81F401U}, + {0x0260U, 0x001000100C84E401U}, + {0x0268U, 0x001000100C81F401U}, + {0x0270U, 0x001000100C81F401U}, + {0x0278U, 0x001000100C81F401U}, + {0x0280U, 0x0000000000000000U}, + {0x0288U, 0x0000000000000000U}, + {0x0290U, 0x001000100C81F401U}, + {0x0298U, 0x001000100C81F401U}, + {0x02A0U, 0x001000100C80FC01U}, + {0x02A8U, 0x001000100C80FC01U}, + {0x02B0U, 0x0000000000000000U}, + {0x02B8U, 0x001000000C800401U}, + {0x02C0U, 0x0000000000000000U}, + {0x02C8U, 0x0000000000000000U}, + {0x02D0U, 0x001000100C80FC01U}, + {0x02D8U, 0x001000100C80FC01U}, + {0x02E0U, 0x0000000000000000U}, + {0x02E8U, 0x001000000C800401U}, + {0x02F0U, 0x001000200C8FFC01U}, + {0x02F8U, 0x001000300C8FFC01U}, + {0x0300U, 0x0000000000000000U}, + {0x0308U, 0x001000200C8FFC01U}, + {0x0310U, 0x001000300C8FFC01U}, + {0x0318U, 0x001000100C803401U}, + {0x0320U, 0x0000000000000000U}, + {0x0328U, 0x0000000000000000U}, + {0x0330U, 0x0000000000000000U}, + {0x0338U, 0x0000000000000000U}, + {0x0340U, 0x0000000000000000U}, + {0x0348U, 0x0000000000000000U}, + {0x0350U, 0x0000000000000000U}, +}; +#endif + +static void dbsc_setting(void) +{ + uint32_t md=0; + + /* BUFCAM settings */ + //DBSC_DBCAM0CNF0 not set + io_write_32(DBSC_DBCAM0CNF1, 0x00044218); //dbcam0cnf1 + io_write_32(DBSC_DBCAM0CNF2, 0x000000F4); //dbcam0cnf2 + io_write_32(DBSC_DBCAM0CNF3, 0x00000007); //dbcam0cnf3 + io_write_32(DBSC_DBSCHCNT0, 0x080F0037); //dbschcnt0 + //DBSC_DBSCHCNT1 not set + io_write_32(DBSC_DBSCHSZ0, 0x00000001); //dbschsz0 + io_write_32(DBSC_DBSCHRW0, 0x22421111); //dbschrw0 + io_write_32(DBSC_DBSCHRW1, 0x00180034); //dbschrw1 + + md = (*((volatile uint32_t*)RST_MODEMR) & 0x000A0000) >> 17; + + switch (md) { + case 0x0: + /* DDR3200 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + case 0x1: //MD19=0,MD17=1 : LPDDR4-3000, 4GByte(1GByte x4) + /* DDR2800 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + case 0x4: //MD19=1,MD17=0 : LPDDR4-2400, 4GByte(1GByte x4) + /* DDR2400 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + default: //MD19=1,MD17=1 : LPDDR4-1600, 4GByte(1GByte x4) + /* DDR1600 */ + io_write_32(DBSC_SCFCTST2, 0x012F1123); + break; + } + + /* QoS Settings */ + io_write_32(DBSC_DBSCHQOS_0_0, 0x0000F000); + io_write_32(DBSC_DBSCHQOS_0_1, 0x0000E000); + io_write_32(DBSC_DBSCHQOS_0_2, 0x00007000); + io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000); + //DBSC_DBSCHQOS_1_0 not set + //DBSC_DBSCHQOS_1_1 not set + //DBSC_DBSCHQOS_1_2 not set + //DBSC_DBSCHQOS_1_3 not set + //DBSC_DBSCHQOS_2_0 not set + //DBSC_DBSCHQOS_2_1 not set + //DBSC_DBSCHQOS_2_2 not set + //DBSC_DBSCHQOS_2_3 not set + //DBSC_DBSCHQOS_3_0 not set + //DBSC_DBSCHQOS_3_1 not set + //DBSC_DBSCHQOS_3_2 not set + //DBSC_DBSCHQOS_3_3 not set + io_write_32(DBSC_DBSCHQOS_4_0, 0x0000F000); + io_write_32(DBSC_DBSCHQOS_4_1, 0x0000EFFF); + io_write_32(DBSC_DBSCHQOS_4_2, 0x0000B000); + io_write_32(DBSC_DBSCHQOS_4_3, 0x00000000); + //DBSC_DBSCHQOS_5_0 not set + //DBSC_DBSCHQOS_5_1 not set + //DBSC_DBSCHQOS_5_2 not set + //DBSC_DBSCHQOS_5_3 not set + //DBSC_DBSCHQOS_6_0 not set + //DBSC_DBSCHQOS_6_1 not set + //DBSC_DBSCHQOS_6_2 not set + //DBSC_DBSCHQOS_6_3 not set + //DBSC_DBSCHQOS_7_0 not set + //DBSC_DBSCHQOS_7_1 not set + //DBSC_DBSCHQOS_7_2 not set + //DBSC_DBSCHQOS_7_3 not set + //DBSC_DBSCHQOS_8_0 not set + //DBSC_DBSCHQOS_8_1 not set + //DBSC_DBSCHQOS_8_2 not set + //DBSC_DBSCHQOS_8_3 not set + io_write_32(DBSC_DBSCHQOS_9_0, 0x0000F000); + io_write_32(DBSC_DBSCHQOS_9_1, 0x0000EFFF); + io_write_32(DBSC_DBSCHQOS_9_2, 0x0000D000); + io_write_32(DBSC_DBSCHQOS_9_3, 0x00000000); + //DBSC_DBSCHQOS_10_0 not set + //DBSC_DBSCHQOS_10_1 not set + //DBSC_DBSCHQOS_10_2 not set + //DBSC_DBSCHQOS_10_3 not set + //DBSC_DBSCHQOS_11_0 not set + //DBSC_DBSCHQOS_11_1 not set + //DBSC_DBSCHQOS_11_2 not set + //DBSC_DBSCHQOS_11_3 not set + //DBSC_DBSCHQOS_12_0 not set + //DBSC_DBSCHQOS_12_1 not set + //DBSC_DBSCHQOS_12_2 not set + //DBSC_DBSCHQOS_12_3 not set + io_write_32(DBSC_DBSCHQOS_13_0, 0x0000F000); + io_write_32(DBSC_DBSCHQOS_13_1, 0x0000EFFF); + io_write_32(DBSC_DBSCHQOS_13_2, 0x0000E800); + io_write_32(DBSC_DBSCHQOS_13_3, 0x00007000); + io_write_32(DBSC_DBSCHQOS_14_0, 0x0000F000); + io_write_32(DBSC_DBSCHQOS_14_1, 0x0000EFFF); + io_write_32(DBSC_DBSCHQOS_14_2, 0x0000E800); + io_write_32(DBSC_DBSCHQOS_14_3, 0x0000B000); + io_write_32(DBSC_DBSCHQOS_15_0, 0x000007D0); + io_write_32(DBSC_DBSCHQOS_15_1, 0x000007CF); + io_write_32(DBSC_DBSCHQOS_15_2, 0x000005D0); + io_write_32(DBSC_DBSCHQOS_15_3, 0x000003D0); +} + +void qos_init_m3_es10(void) +{ + dbsc_setting(); + + /* DRAM Split Address mapping */ +#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH + NOTICE("BL2: DRAM Split is 4ch\n"); + io_write_32(AXI_ADSPLCR0, ADSPLCR0_ADRMODE_DEFAULT + | ADSPLCR0_SPLITSEL(0xFFU) + | ADSPLCR0_AREA(0x1BU) + | ADSPLCR0_SWP); + io_write_32(AXI_ADSPLCR1, 0x00000000U); + io_write_32(AXI_ADSPLCR2, 0xA8A90000U); + io_write_32(AXI_ADSPLCR3, 0x00000000U); +#elif RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH + NOTICE("BL2: DRAM Split is 2ch\n"); + io_write_32(AXI_ADSPLCR0, 0x00000000U); + io_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT + | ADSPLCR0_SPLITSEL(0xFFU) + | ADSPLCR0_AREA(0x1BU) + | ADSPLCR0_SWP); + io_write_32(AXI_ADSPLCR2, 0x089A0000U); + io_write_32(AXI_ADSPLCR3, 0x00000000U); +#else + NOTICE("BL2: DRAM Split is OFF\n"); +#endif + +#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE) +#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT + NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION); +#endif + + /* AR Cache setting */ + io_write_32(0xE67D1000U, 0x00000100U); + io_write_32(0xE67D1008U, 0x00000100U); + + /* Resource Alloc setting */ + io_write_32(RALLOC_RAS, 0x00000020U); + io_write_32(RALLOC_FIXTH, 0x000F0005U); + io_write_32(RALLOC_RAEN, 0x00000001U); + io_write_32(RALLOC_REGGD, 0x00000000U); + io_write_64(RALLOC_DANN, 0x0202010104040404U); + io_write_32(RALLOC_DANT, 0x00181008U); + io_write_32(RALLOC_EC, 0x00000000U); + io_write_64(RALLOC_EMS, 0x0000000000000000U); + io_write_32(RALLOC_INSFC, 0xC7840001U); + io_write_32(RALLOC_BERR, 0x00000000U); + io_write_32(RALLOC_RACNT0, 0x00000003U); + + /* MSTAT setting */ + io_write_32(MSTAT_SL_INIT, 0x0305007DU); + io_write_32(MSTAT_REF_ARS, 0x00330000U); + + /* MSTAT SRAM setting */ + { + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { + io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr, + mstat_fix[i].value); + io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr, + mstat_fix[i].value); + } + for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { + io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr, + mstat_be[i].value); + io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr, + mstat_be[i].value); + } + } + + /* AXI-IF arbitration setting */ + io_write_32(DBSC_AXARB, 0x18010000U); + + /* 3DG bus Leaf setting */ + io_write_32(0xFD820808U, 0x00001234U); + io_write_32(0xFD820800U, 0x00000006U); + io_write_32(0xFD821800U, 0x00000006U); + io_write_32(0xFD822800U, 0x00000006U); + io_write_32(0xFD823800U, 0x00000006U); + io_write_32(0xFD824800U, 0x00000006U); + io_write_32(0xFD825800U, 0x00000006U); + io_write_32(0xFD826800U, 0x00000006U); + io_write_32(0xFD827800U, 0x00000006U); + + /* Resource Alloc start */ + io_write_32(RALLOC_RAEN, 0x00000001U); + + /* MSTAT start */ + io_write_32(MSTAT_STATQC, 0x00000001U); +#else + NOTICE("BL2: QoS is None\n"); + + /* Resource Alloc setting */ + io_write_32(RALLOC_EC, 0x00000000U); + /* Resource Alloc start */ + io_write_32(RALLOC_RAEN, 0x00000001U); +#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */ +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/M3/qos_init_m3_es10.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/M3/qos_init_m3_es10.h new file mode 100644 index 0000000..14ef8b2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/M3/qos_init_m3_es10.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef QOS_INIT_H_M3_ES10__ +#define QOS_INIT_H_M3_ES10__ + +void qos_init_m3_es10(void); + +#endif /* QOS_INIT_H_M3_ES10__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/qos.mk b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/qos.mk new file mode 100644 index 0000000..55203bb --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/qos.mk @@ -0,0 +1,54 @@ +# +# Copyright (c) 2015-2016, Renesas Electronics Corporation +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# - Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# - Neither the name of Renesas nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +ifdef RCAR_LSI_CUT_COMPAT + ifeq (${RCAR_LSI},${RCAR_H3}) + BL2_SOURCES += plat/renesas/rcar/qos/H3/ES10/qos_init_h3_es10.c + BL2_SOURCES += plat/renesas/rcar/qos/H3/WS11/qos_init_h3_ws11.c + endif + ifeq (${RCAR_LSI},${RCAR_M3}) + $(error "Error: ${LSI} is not supported.") + endif +else + ifeq (${RCAR_LSI},${RCAR_H3}) + ifeq (${LSI_CUT},10) + BL2_SOURCES += plat/renesas/rcar/qos/H3/ES10/qos_init_h3_es10.c + endif + ifeq (${LSI_CUT},11) + BL2_SOURCES += plat/renesas/rcar/qos/H3/WS11/qos_init_h3_ws11.c + endif + endif + ifeq (${RCAR_LSI},${RCAR_M3}) + BL2_SOURCES += plat/renesas/rcar/qos/M3/qos_init_m3_es10.c + endif +endif + +BL2_SOURCES += plat/renesas/rcar/qos/qos_init.c diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/qos_init.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/qos_init.c new file mode 100644 index 0000000..20a8e81 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/qos_init.c @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "qos_init.h" +#if RCAR_LSI == RCAR_H3 /* H3 */ + #include "H3/ES10/qos_init_h3_es10.h" + #include "H3/WS11/qos_init_h3_ws11.h" +#endif +#if RCAR_LSI == RCAR_M3 /* M3 */ + #include "M3/qos_init_m3_es10.h" +#endif + + /* Product Register */ +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) +#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */ +#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ +#define PRR_PRODUCT_10 (0x00U) +#define PRR_PRODUCT_11 (0x01U) + +#define PRR_PRODUCT_ERR(reg) do{\ + ERROR("LSI Product ID(PRR=0x%x) QoS "\ + "initialize not supported.\n",reg);\ + panic();\ + }while(0) +#define PRR_CUT_ERR(reg) do{\ + ERROR("LSI Cut ID(PRR=0x%x) QoS "\ + "initialize not supported.\n",reg);\ + panic();\ + }while(0) + +void qos_init(void) +{ + uint32_t reg; + + reg = mmio_read_32(PRR); +#if RCAR_LSI_CUT_COMPAT + switch (reg & PRR_PRODUCT_MASK) { + case PRR_PRODUCT_H3: +#if RCAR_LSI != RCAR_H3 + PRR_PRODUCT_ERR(reg); +#else + switch (reg & PRR_CUT_MASK) { + case PRR_PRODUCT_10: + qos_init_h3_es10(); + break; + case PRR_PRODUCT_11: + qos_init_h3_ws11(); + break; + default: + PRR_CUT_ERR(reg); + break; + } +#endif + break; + case PRR_PRODUCT_M3: +#if RCAR_LSI != RCAR_M3 + PRR_PRODUCT_ERR(reg); +#else + qos_init_m3_es10(); +#endif + break; + default: + PRR_PRODUCT_ERR(reg); + break; + } +#else + #if RCAR_LSI == RCAR_H3 /* H3 */ + #if RCAR_LSI_CUT == RCAR_CUT_10 + /* H3 Cut 10 */ + if ((PRR_PRODUCT_H3 | PRR_PRODUCT_10) + != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { + PRR_PRODUCT_ERR(reg); + } + qos_init_h3_es10(); + #elif RCAR_LSI_CUT == RCAR_CUT_11 + /* H3 Cut 11 */ + if ((PRR_PRODUCT_H3 | PRR_PRODUCT_11) + != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { + PRR_PRODUCT_ERR(reg); + } + qos_init_h3_ws11(); + #else + #error "Don't have QoS initialize routine(H3)." + #endif + #elif RCAR_LSI == RCAR_M3 /* M3 */ + if ((PRR_PRODUCT_M3 | PRR_PRODUCT_10) + != (reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK))) { + PRR_PRODUCT_ERR(reg); + } + qos_init_m3_es10(); + #else + #error "Don't have QoS initialize routine(M3)." + #endif +#endif +} + + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/qos_init.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/qos_init.h new file mode 100644 index 0000000..f7b2ca4 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/qos/qos_init.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef QOS_INIT_H_ +#define QOS_INIT_H_ + +extern void qos_init(void); + +#endif /* QOS_INIT_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_def.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_def.h new file mode 100644 index 0000000..be36d99 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_def.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_DEF_H__ +#define RCAR_DEF_H__ + +#include + +/* Firmware Image Package */ +#define RCAR_PRIMARY_CPU 0x0 + +/* + * Some of the definitions in this file use the 'ull' suffix in order to avoid + * subtle integer overflow errors due to implicit integer type promotion when + * working with 32-bit values. + * + * The TSP linker script includes some of these definitions to define the BL3-2 + * memory map, but the GNU LD does not support the 'ull' suffix, causing the + * build process to fail. To solve this problem, the auxiliary macro MAKE_ULL(x) + * will add the 'ull' suffix only when the macro __LINKER__ is not defined + * (__LINKER__ is defined in the command line to preprocess the linker script). + * Constants in the linker script will not have the 'ull' suffix, but this is + * not a problem since the linker evaluates all constant expressions to 64 bit + * (assuming the target architecture is 64 bit). + */ +#ifndef __LINKER__ + #define MAKE_ULL(x) x##ull +#else + #define MAKE_ULL(x) x +#endif + +/******************************************************************************* + * RCAR memory map related constants + ******************************************************************************/ + +/* The first 4KB of Trusted SRAM are used as shared memory */ +#define RCAR_SHARED_MEM_BASE (RCAR_TRUSTED_SRAM_BASE + RCAR_TRUSTED_SRAM_SIZE) +#define RCAR_SHARED_MEM_SIZE 0x00001000U /* 4 KB */ + +/* The remaining Trusted SRAM is used to load the BL images */ +#define RCAR_TRUSTED_SRAM_BASE 0x44000000 /* Trusted Firmware Image */ +#define RCAR_TRUSTED_SRAM_SIZE 0x0003E000 /* 248 KB */ + +#define FLASH0_BASE 0x08000000U /* LBSC RPC address */ +#define FLASH0_SIZE 0x04000000U /* 64MB */ + +/* Aggregate of all devices in the first GB */ +#define DEVICE_RCAR_BASE 0xE6000000U +#define DEVICE_RCAR_SIZE 0x1A000000U + +#define DRAM1_BASE MAKE_ULL(0x40000000) +#define DRAM1_SIZE MAKE_ULL(0x80000000) + +#define DRAM1_NS_BASE (DRAM1_BASE + 0x8000000U) +#define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_NS_BASE) +#define DRAM1_NS_END (DRAM1_NS_BASE + DRAM1_NS_SIZE - 1) + + +#define SYS_CNTCTL_BASE 0xE6080000U + + + +/* + * The number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#if USE_COHERENT_MEM +#define RCAR_BL_REGIONS 3 +#else +#define RCAR_BL_REGIONS 2 +#endif + +/* + * The RCAR_MAX_MMAP_REGIONS depend on the number of entries in rcar_mmap[] + * defined for each BL stage in rcar_common.c. + */ +#if IMAGE_BL2 +#define RCAR_MMAP_ENTRIES 7 +#endif +#if IMAGE_BL31 +#define RCAR_MMAP_ENTRIES 5 +#endif +#if IMAGE_BL33 +#define RCAR_MMAP_ENTRIES 4 +#endif + +/* Load address of BL33 in the RCAR port */ +#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x09000000U) /* DRAM */ + +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define RCAR_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + + +/******************************************************************************* + * CCI-400 related constants + ******************************************************************************/ +#define CCI500_BASE 0xF1200000 +#define CCI500_CLUSTER0_SL_IFACE_IX 2 +#define CCI500_CLUSTER1_SL_IFACE_IX 3 +#define CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3 1 +#define CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3 2 + +/* CCI-500 */ +#define RCAR_CCI_BASE (0xF1200000U) /* The base address of CCI-500 */ + +/******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ +#define RCAR_GICD_BASE (0xF1010000U) +#define RCAR_GICD_BASE_A (0xF1010000) +#define RCAR_GICR_BASE (0xF1010000U) /* not use */ +#define RCAR_GICC_BASE (0xF1020000U) +#define RCAR_GICC_BASE_A (0xF1020000) +#define RCAR_GICH_BASE (0xF1040000U) /* not use */ +#define RCAR_GICV_BASE (0xF1060000U) /* not use */ + +#define ARM_IRQ_SEC_PHY_TIMER 29U + +#define ARM_IRQ_SEC_SGI_0 8U +#define ARM_IRQ_SEC_SGI_1 9U +#define ARM_IRQ_SEC_SGI_2 10U +#define ARM_IRQ_SEC_SGI_3 11U +#define ARM_IRQ_SEC_SGI_4 12U +#define ARM_IRQ_SEC_SGI_5 13U +#define ARM_IRQ_SEC_SGI_6 14U +#define ARM_IRQ_SEC_SGI_7 15U + +/****************************************************************************************************************************************************************/ +/* */ +/* Interrupt ID for Secure world */ +/* */ +/****************************************************************************************************************************************************************/ +#define ARM_IRQ_SEC_RPC ( 70U) /* RPC */ +#define ARM_IRQ_SEC_TIMER (166U) /* Secure timer */ +#define ARM_IRQ_SEC_TIMER_UP (171U) /* Secure timer UP */ +#define ARM_IRQ_SEC_WDT (173U) /* System watch dog timer */ +#define ARM_IRQ_SEC_WDT_A (173) /* System watch dog timer for Assembly language */ +#define ARM_IRQ_SEC_CRYPT (102U) /* Crypt Engine sec */ +#define ARM_IRQ_SEC_CRYPT_SecPKA ( 97U) /* Crypt Engine PKA sec */ +#define ARM_IRQ_SEC_CRYPT_PubPKA ( 98U) /* Crypt Engine PKA pub */ + +/****************************************************************************************************************************************************************/ +/* */ +/* New definition for R-CarGen3 */ +/* */ +/****************************************************************************************************************************************************************/ +#define RCAR_DEVICE_BASE (0xE6000000) /* Start address of BL31 register area */ +#define RCAR_DEVICE_SIZE (0x1A000000) /* Size of BL31 register area */ +#define RCAR_LOG_RES_SIZE (512/8) /* Size of reservation in log area */ +#define RCAR_LOG_HEADER_SIZE (16) /* Size of LOG header */ +#define RCAR_LOG_OTHER_SIZE (RCAR_LOG_HEADER_SIZE+RCAR_LOG_RES_SIZE) /* Size of write pointer, log header, reservation */ +#define RCAR_BL31_LOG_MAX (RCAR_BL31_LOG_SIZE - RCAR_LOG_OTHER_SIZE) /* MAX log size */ + +#define RCAR_CRASH_STACK (0x4403F800) /* Temporary stack for crash */ + +/****************************************************************************************************************************************************************/ +/* */ +/* Definition of R-CarGen3 register address */ +/* */ +/****************************************************************************************************************************************************************/ +/* Timer */ +#define RCAR_CNTC_BASE (0xE6080000U) /* The base addess of generic timer control register */ +/* Reset */ +#define RCAR_CPGWPR (0xE6150900U) /* CPG write protect register */ +#define RCAR_MODEMR (0xE6160060U) /* Mode pin register */ +#define RCAR_MODEMR_A (0xE6160060) /* Mode pin register for Assembly language */ +#define RCAR_CA57RESCNT (0xE6160040U) /* Reset control register for A57 */ +#define RCAR_CA53RESCNT (0xE6160044U) /* Reset control register for A53 */ +#define RCAR_SRESCR (0xE6160110U) /* Soft Power On Reset Control Register */ +#define RCAR_CA53WUPCR (0xE6151010U) /* Wake-up control register for A53 */ +#define RCAR_CA57WUPCR (0xE6152010U) /* Wake-up control register for A57 */ +#define RCAR_CA53PSTR (0xE6151040U) /* Power status register for A53 */ +#define RCAR_CA57PSTR (0xE6152040U) /* Power status register for A57 */ +#define RCAR_CA53CPU0CR (0xE6151100U) /* The base address of CPU power status control register for A53 */ +#define RCAR_CA57CPU0CR (0xE6152100U) /* The base address of CPU power status control register for A57 */ +#define RCAR_CA53CPUCMCR (0xE6151184U) /* Common power control register for A53 */ +#define RCAR_CA57CPUCMCR (0xE6152184U) /* Common power control register for A57 */ +#define RCAR_WUPMSKCA57 (0xE6180014U) /* Wake-up mask register for A57 */ +#define RCAR_WUPMSKCA53 (0xE6180018U) /* Wake-up mask register for A53 */ +/* SYSC */ +#define RCAR_PWRSR3 (0xE6180140U) /* Power status register CA53-SCU */ +#define RCAR_PWRSR5 (0xE61801C0U) /* Power status register CA57-SCU */ +#define RCAR_SYSCIER (0xE618000CU) /* Interrupt enable register */ +#define RCAR_SYSCIMR (0xE6180010U) /* Interrupt mask register */ +#define RCAR_SYSCSR (0xE6180000U) /* SYSC status register */ +#define RCAR_PWRONCR3 (0xE618014CU) /* Power resume control register CA53-SCU */ +#define RCAR_PWRONCR5 (0xE61801CCU) /* Power resume control register CA57-SCU */ +#define RCAR_PWROFFCR3 (0xE6180144U) /* Power shutoff control register CA53-SCU */ +#define RCAR_PWROFFCR5 (0xE61801C4U) /* Power shutoff control register CA57-SCU */ +#define RCAR_PWRER3 (0xE6180154U) /* Power shutoff/resume error register CA53-SCU */ +#define RCAR_PWRER5 (0xE61801D4U) /* Power shutoff/resume error register CA57-SCU */ +#define RCAR_SYSCISR (0xE6180004U) /* Interrupt status register */ +#define RCAR_SYSCISCR (0xE6180008U) /* Interrupt status clear register */ +/* Product register */ +#define RCAR_PRR (0xFFF00044U) /* Product register */ + +/******************************************************************************* + * RCAR product and cut information + ******************************************************************************/ +#define RCAR_PRODUCT_MASK (0x00007F00U) +#define RCAR_CUT_MASK (0x000000FFU) +#define RCAR_PRODUCT_H3 (0x00004F00U) +#define RCAR_PRODUCT_M3 (0x00005200U) +#define RCAR_CUT_ES10 (0x00000000U) +#define RCAR_CUT_ES11 (0x00000001U) +#define RCAR_MAJOR_MASK (0x000000F0U) +#define RCAR_MINOR_MASK (0x0000000FU) +#define RCAR_PRODUCT_SHIFT (8U) +#define RCAR_MAJOR_SHIFT (4U) +#define RCAR_MINOR_SHIFT (0U) +#define RCAR_MAJOR_OFFSET (1U) +#define RCAR_PRODUCT_H3_CUT10 (RCAR_PRODUCT_H3 | 0x00U) /* H3 WS1.0 */ +#define RCAR_PRODUCT_H3_CUT11 (RCAR_PRODUCT_H3 | 0x01U) /* H3 WS1.1 */ +#define RCAR_PRODUCT_M3_CUT10 (RCAR_PRODUCT_M3 | 0x00U) /* M3 */ + +/******************************************************************************* + * RCAR MD pin information + ******************************************************************************/ +#define MODEMR_BOOT_CPU_MASK (0x000000C0U) +#define MODEMR_BOOT_CPU_CR7 (0x000000C0U) +#define MODEMR_BOOT_CPU_CA57 (0x00000000U) +#define MODEMR_BOOT_CPU_CA53 (0x00000040U) + +/****************************************************************************************************************************************************************/ +/* Memory mapped Generic timer interfaces */ +/****************************************************************************************************************************************************************/ +#define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE + +/******************************************************************************* + * Boot CPU + ******************************************************************************/ +#define RCAR_BOOT_CA5X (0U) /* Master boot CPU is CA57/53 */ +#define RCAR_BOOT_CR7 (1U) /* Master boot CPU is CR7 */ + +/******************************************************************************* + * Shared Data + ******************************************************************************/ + +#define RCAR_BL31_MAIL_BASE (0x4403E000) +#define RCAR_BL31_MAIL_SIZE (0x00002000) +#define RCAR_BL31_WORK_BASE (0x44022000) +#define RCAR_BL31_WORK_SIZE (0x0001C000) + +/* Entrypoint mailboxes */ +#define MBOX_BASE RCAR_SHARED_MEM_BASE +#define MBOX_SIZE 0x200 + +/* Base address where parameters to BL31 are stored */ +#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE) + +#endif /* RCAR_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_io_storage.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_io_storage.c new file mode 100644 index 0000000..fd3e413 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_io_storage.c @@ -0,0 +1,442 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include /* For ARRAY_SIZE */ +#include +#include +#include +#include +#include +#include +#include "io_common.h" +#include "io_rcar.h" +#include "io_memdrv.h" + +/* IO devices */ +static uintptr_t rcar_dev_handle; +static uintptr_t memdrv_dev_handle; + +static const io_block_spec_t rcar_block_spec = { + .offset = FLASH0_BASE, + .length = FLASH0_SIZE +}; + +static const io_block_spec_t bl2_file_spec = { + .offset = BL2_IMAGE_ID, +}; + +static const io_block_spec_t bl31_file_spec = { + .offset = BL31_IMAGE_ID, +}; + +static const io_block_spec_t bl32_file_spec = { + .offset = BL32_IMAGE_ID, +}; + +static const io_block_spec_t bl33_file_spec = { + .offset = BL33_IMAGE_ID, +}; + +static const io_block_spec_t bl332_file_spec = { + .offset = BL332_IMAGE_ID, +}; + +static const io_block_spec_t bl333_file_spec = { + .offset = BL333_IMAGE_ID, +}; + +static const io_block_spec_t bl334_file_spec = { + .offset = BL334_IMAGE_ID, +}; + +static const io_block_spec_t bl335_file_spec = { + .offset = BL335_IMAGE_ID, +}; + +static const io_block_spec_t bl336_file_spec = { + .offset = BL336_IMAGE_ID, +}; + +static const io_block_spec_t bl337_file_spec = { + .offset = BL337_IMAGE_ID, +}; + +static const io_block_spec_t bl338_file_spec = { + .offset = BL338_IMAGE_ID, +}; + + +#if TRUSTED_BOARD_BOOT +static const io_block_spec_t trusted_key_cert_file_spec = { + .offset = TRUSTED_KEY_CERT_ID, +}; + +static const io_block_spec_t bl31_key_cert_file_spec = { + .offset = BL31_KEY_CERT_ID, +}; + +static const io_block_spec_t bl32_key_cert_file_spec = { + .offset = BL32_KEY_CERT_ID, +}; + +static const io_block_spec_t bl33_key_cert_file_spec = { + .offset = BL33_KEY_CERT_ID, +}; + +static const io_block_spec_t bl332_key_cert_file_spec = { + .offset = BL332_KEY_CERT_ID, +}; + +static const io_block_spec_t bl333_key_cert_file_spec = { + .offset = BL333_KEY_CERT_ID, +}; + +static const io_block_spec_t bl334_key_cert_file_spec = { + .offset = BL334_KEY_CERT_ID, +}; + +static const io_block_spec_t bl335_key_cert_file_spec = { + .offset = BL335_KEY_CERT_ID, +}; + +static const io_block_spec_t bl336_key_cert_file_spec = { + .offset = BL336_KEY_CERT_ID, +}; + +static const io_block_spec_t bl337_key_cert_file_spec = { + .offset = BL337_KEY_CERT_ID, +}; + +static const io_block_spec_t bl338_key_cert_file_spec = { + .offset = BL338_KEY_CERT_ID, +}; + +static const io_block_spec_t bl31_cert_file_spec = { + .offset = BL31_CERT_ID, +}; + +static const io_block_spec_t bl32_cert_file_spec = { + .offset = BL32_CERT_ID, +}; + +static const io_block_spec_t bl33_cert_file_spec = { + .offset = BL33_CERT_ID, +}; + +static const io_block_spec_t bl332_cert_file_spec = { + .offset = BL332_CERT_ID, +}; + +static const io_block_spec_t bl333_cert_file_spec = { + .offset = BL333_CERT_ID, +}; + +static const io_block_spec_t bl334_cert_file_spec = { + .offset = BL334_CERT_ID, +}; + +static const io_block_spec_t bl335_cert_file_spec = { + .offset = BL335_CERT_ID, +}; + +static const io_block_spec_t bl336_cert_file_spec = { + .offset = BL336_CERT_ID, +}; + +static const io_block_spec_t bl337_cert_file_spec = { + .offset = BL337_CERT_ID, +}; + +static const io_block_spec_t bl338_cert_file_spec = { + .offset = BL338_CERT_ID, +}; +#endif /* TRUSTED_BOARD_BOOT */ + +static int32_t open_rcar(const uintptr_t spec); +static int32_t open_memmap(const uintptr_t spec); + +/* sakata check table info */ +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int32_t (*check)(const uintptr_t spec); +}; + +static const struct plat_io_policy policies[] = { + [FIP_IMAGE_ID] = { + &memdrv_dev_handle, + (uintptr_t)&rcar_block_spec, + &open_memmap + }, + [BL2_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl2_file_spec, + &open_rcar + }, + [BL31_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl31_file_spec, + &open_rcar + }, + [BL32_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl32_file_spec, + &open_rcar + }, + [BL33_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl33_file_spec, + &open_rcar + }, + [BL332_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl332_file_spec, + &open_rcar + }, + [BL333_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl333_file_spec, + &open_rcar + }, + [BL334_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl334_file_spec, + &open_rcar + }, + [BL335_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl335_file_spec, + &open_rcar + }, + [BL336_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl336_file_spec, + &open_rcar + }, + [BL337_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl337_file_spec, + &open_rcar + }, + [BL338_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl338_file_spec, + &open_rcar + }, +#if TRUSTED_BOARD_BOOT + [TRUSTED_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&trusted_key_cert_file_spec, + &open_rcar + }, + [BL31_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl31_key_cert_file_spec, + &open_rcar + }, + [BL32_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl32_key_cert_file_spec, + &open_rcar + }, + [BL33_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl33_key_cert_file_spec, + &open_rcar + }, + [BL332_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl332_key_cert_file_spec, + &open_rcar + }, + [BL333_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl333_key_cert_file_spec, + &open_rcar + }, + [BL334_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl334_key_cert_file_spec, + &open_rcar + }, + [BL335_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl335_key_cert_file_spec, + &open_rcar + }, + [BL336_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl336_key_cert_file_spec, + &open_rcar + }, + [BL337_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl337_key_cert_file_spec, + &open_rcar + }, + [BL338_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl338_key_cert_file_spec, + &open_rcar + }, + [BL31_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl31_cert_file_spec, + &open_rcar + }, + [BL32_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl32_cert_file_spec, + &open_rcar + }, + [BL33_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl33_cert_file_spec, + &open_rcar + }, + [BL332_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl332_cert_file_spec, + &open_rcar + }, + [BL333_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl333_cert_file_spec, + &open_rcar + }, + [BL334_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl334_cert_file_spec, + &open_rcar + }, + [BL335_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl335_cert_file_spec, + &open_rcar + }, + [BL336_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl336_cert_file_spec, + &open_rcar + }, + [BL337_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl337_cert_file_spec, + &open_rcar + }, + [BL338_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl338_cert_file_spec, + &open_rcar + },{ +#endif /* TRUSTED_BOARD_BOOT */ + 0, 0, 0 + } +}; + + +static int32_t open_rcar(const uintptr_t spec) +{ + int32_t result; + + /* See if a Firmware Image Package is available */ + result = io_dev_init(rcar_dev_handle, (uintptr_t)FIP_IMAGE_ID); + if (result == IO_SUCCESS) { + VERBOSE("Using RCar File Manager\n"); + } + return result; +} + + +static int32_t open_memmap(const uintptr_t spec) +{ + int32_t result; + uintptr_t local_image_handle; + + result = io_dev_init(memdrv_dev_handle, 0U); + if (result == IO_SUCCESS) { + result = io_open(memdrv_dev_handle, spec, &local_image_handle); + if (result == IO_SUCCESS) { + VERBOSE("Using Memdrv IO\n"); + (void)io_close(local_image_handle); + } + } + return result; +} + + + +void rcar_io_setup (void) +{ + int32_t io_result; + const io_dev_connector_t *rcar_dev_con; + const io_dev_connector_t *memmap_dev_con; + + /* Register the IO devices on this platform */ + io_result = register_io_dev_rcar(&rcar_dev_con); + assert(io_result == IO_SUCCESS); + + io_result = register_io_dev_memdrv(&memmap_dev_con); + assert(io_result == IO_SUCCESS); + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(rcar_dev_con, 0U, &rcar_dev_handle); + assert(io_result == IO_SUCCESS); + + io_result = io_dev_open(memmap_dev_con, 0U, + &memdrv_dev_handle); + assert(io_result == IO_SUCCESS); + + /* Ignore improbable errors in release builds */ + (void)io_result; +} + + +/* Return an IO device handle and specification which can be used to access + * an image. Use this to enforce platform load policy */ +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result = IO_FAIL; + const struct plat_io_policy *policy; + + assert(image_id < ARRAY_SIZE(policies)); + + policy = &policies[image_id]; + result = policy->check(policy->image_spec); + if (result == IO_SUCCESS) { + *image_spec = policy->image_spec; + *dev_handle = *(policy->dev_handle); + } + + return result; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_pm.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_pm.c new file mode 100644 index 0000000..87db4a7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_pm.c @@ -0,0 +1,388 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "drivers/pwrc/rcar_pwrc.h" +#include "drivers/iic_dvfs/iic_dvfs.h" +#include "rcar_def.h" +#include "rcar_private.h" + +static void rcar_program_mailbox(uint64_t mpidr, uint64_t address); +static int32_t rcar_do_plat_actions(unsigned int afflvl, unsigned int state); +static void rcar_cpu_pwrdwn_common(void); +static void rcar_cluster_pwrdwn_common(void); +static void __dead2 rcar_system_off(void); +static void __dead2 rcar_system_reset(void); + +/******************************************************************************* + * Private RCAR function to program the mailbox for a cpu before it is released + * from reset. + ******************************************************************************/ +static void rcar_program_mailbox(uint64_t mpidr, uint64_t address) +{ + uint64_t linear_id; + mailbox_t *rcar_mboxes; + + linear_id = platform_get_core_pos(mpidr); + rcar_mboxes = (mailbox_t *)MBOX_BASE; + rcar_mboxes[linear_id].value = address; + flush_dcache_range((unsigned long)&rcar_mboxes[linear_id], + sizeof(unsigned long)); +} + +/******************************************************************************* + * Function which implements the common RCAR specific operations to power down a + * cpu in response to a CPU_OFF or CPU_SUSPEND request. + ******************************************************************************/ +static void rcar_cpu_pwrdwn_common(void) +{ + /* Prevent interrupts from spuriously waking up this cpu */ + arm_gic_cpuif_deactivate(); + + /* Program the power controller to power off this cpu. */ + rcar_pwrc_cpuoff (read_mpidr_el1()); +} + +/******************************************************************************* + * Function which implements the common RCAR specific operations to power down a + * cluster in response to a CPU_OFF or CPU_SUSPEND request. + ******************************************************************************/ +static void rcar_cluster_pwrdwn_common(void) +{ + uint64_t mpidr = read_mpidr_el1(); + + /* Disable coherency if this cluster is to be turned off */ + rcar_cci_disable(); + + /* Program the power controller to turn the cluster off */ + rcar_pwrc_clusteroff(mpidr); +} + +/******************************************************************************* + * Private RCAR function which is used to determine if any platform actions + * should be performed for the specified affinity instance given its + * state. Nothing needs to be done if the 'state' is not off or if this is not + * the highest affinity level which will enter the 'state'. + ******************************************************************************/ +static int32_t rcar_do_plat_actions(unsigned int afflvl, unsigned int state) +{ + unsigned int max_phys_off_afflvl; + + assert(afflvl <= MPIDR_AFFLVL1); + + if (state != PSCI_STATE_OFF) { + return -EAGAIN; + } + + /* + * Find the highest affinity level which will be suspended and postpone + * all the platform specific actions until that level is hit. + */ + max_phys_off_afflvl = psci_get_max_phys_off_afflvl(); + assert(max_phys_off_afflvl != PSCI_INVALID_DATA); + if (afflvl != max_phys_off_afflvl) { + return -EAGAIN; + } + + return 0; +} + +/******************************************************************************* + * RCAR handler called when an affinity instance is about to enter standby. + ******************************************************************************/ +void rcar_affinst_standby(unsigned int power_state) +{ + /* + * Enter standby state + * dsb is good practice before using wfi to enter low power states + */ + dsb(); + wfi(); +} + +/******************************************************************************* + * RCAR handler called when an affinity instance is about to be turned on. The + * level and mpidr determine the affinity instance. + ******************************************************************************/ +int rcar_affinst_on(unsigned long mpidr, unsigned long sec_entrypoint, + unsigned int afflvl, unsigned int state) +{ + int rc = PSCI_E_SUCCESS; + +#if PSCI_DISABLE_BIGLITTLE_IN_CA57BOOT + uint64_t boot_cluster = read_mpidr_el1() & ((uint64_t)MPIDR_CLUSTER_MASK); + if (boot_cluster == 0x0000U) { + if ((mpidr & ((uint64_t)MPIDR_CLUSTER_MASK)) != boot_cluster) { + return PSCI_E_INTERN_FAIL; + } + } +#endif + /* + * It's possible to turn on only affinity level 0 i.e. a cpu + * on the RCAR. Ignore any other affinity level. + */ + if (afflvl != MPIDR_AFFLVL0) { + return rc; + } + + /* + * Ensure that we do not cancel an inflight power off request + * for the target cpu. That would leave it in a zombie wfi. + * Wait for it to power off, program the jump address for the + * target cpu and then program the power controller to turn + * that cpu on + */ + + rcar_program_mailbox(mpidr, sec_entrypoint); + rcar_pwrc_cpuon(mpidr); + + return rc; +} + +/******************************************************************************* + * RCAR handler called when an affinity instance is about to be turned off. The + * level and mpidr determine the affinity instance. The 'state' arg. allows the + * platform to decide whether the cluster is being turned off and take apt + * actions. + * + * CAUTION: There is no guarantee that caches will remain turned on across calls + * to this function as each affinity level is dealt with. So do not write & read + * global variables across calls. It will be wise to do flush a write to the + * global to prevent unpredictable results. + ******************************************************************************/ +void rcar_affinst_off(unsigned int afflvl, unsigned int state) +{ + /* Determine if any platform actions need to be executed */ + if (rcar_do_plat_actions(afflvl, state) == -EAGAIN) { + return; + } + + /* + * If execution reaches this stage then this affinity level will be + * suspended. Perform at least the cpu specific actions followed the + * cluster specific operations if applicable. + */ + rcar_cpu_pwrdwn_common(); + + if (afflvl != MPIDR_AFFLVL0) { + rcar_cluster_pwrdwn_common(); + } +} + +/******************************************************************************* + * RCAR handler called when an affinity instance is about to be suspended. The + * level and mpidr determine the affinity instance. The 'state' arg. allows the + * platform to decide whether the cluster is being turned off and take apt + * actions. + * + * CAUTION: There is no guarantee that caches will remain turned on across calls + * to this function as each affinity level is dealt with. So do not write & read + * global variables across calls. It will be wise to do flush a write to the + * global to prevent unpredictable results. + ******************************************************************************/ +void rcar_affinst_suspend(unsigned long sec_entrypoint, unsigned int afflvl, + unsigned int state) +{ + unsigned long mpidr; + + /* Determine if any platform actions need to be executed. */ + if (rcar_do_plat_actions(afflvl, state) == -EAGAIN) { + return; + } + + /* Get the mpidr for this cpu */ + mpidr = read_mpidr_el1(); + + /* Program the jump address for the this cpu */ + rcar_program_mailbox(mpidr, sec_entrypoint); + + /* Program the power controller to enable wakeup interrupts. */ + rcar_pwrc_enable_interrupt_wakeup(mpidr); + + /* Perform the common cpu specific operations */ + rcar_cpu_pwrdwn_common(); + + /* Perform the common cluster specific operations */ + if (afflvl != MPIDR_AFFLVL0) { + rcar_cluster_pwrdwn_common(); + } +} + +/******************************************************************************* + * RCAR handler called when an affinity instance has just been powered on after + * being turned off earlier. The level and mpidr determine the affinity + * instance. The 'state' arg. allows the platform to decide whether the cluster + * was turned off prior to wakeup and do what's necessary to setup it up + * correctly. + ******************************************************************************/ +void rcar_affinst_on_finish(unsigned int afflvl, unsigned int state) +{ + unsigned long mpidr; + + /* Determine if any platform actions need to be executed. */ + if (rcar_do_plat_actions(afflvl, state) == -EAGAIN) { + return; + } + + /* Get the mpidr for this cpu */ + mpidr = read_mpidr_el1(); + + /* Perform the common cluster specific operations */ + if (afflvl != MPIDR_AFFLVL0) { + /* Enable coherency if this cluster was off */ + rcar_cci_enable(); + } + + /* + * Prohibit cpu wake up by interrupt + */ + rcar_pwrc_disable_interrupt_wakeup(mpidr); + + /* Zero the jump address in the mailbox for this cpu */ + rcar_program_mailbox(mpidr, 0U); + + /* Enable the gic cpu interface */ + arm_gic_cpuif_setup(); + + /* TODO: This setup is needed only after a cold boot */ + arm_gic_pcpu_distif_setup(); +} + +/******************************************************************************* + * RCAR handler called when an affinity instance has just been powered on after + * having been suspended earlier. The level and mpidr determine the affinity + * instance. + * TODO: At the moment we reuse the on finisher and reinitialize the secure + * context. Need to implement a separate suspend finisher. + ******************************************************************************/ +void rcar_affinst_suspend_finish(unsigned int afflvl, unsigned int state) +{ + rcar_affinst_on_finish(afflvl, state); +} + +/******************************************************************************* + * RCAR handlers to shutdown/reboot the system + ******************************************************************************/ +static void __dead2 rcar_system_off(void) +{ + int32_t error; + + error = rcar_iic_dvfs_send(SLAVE_ADDR_PMIC + ,REG_ADDR_DVFS_SetVID + ,REG_DATA_DVFS_SetVID_0V); + if (error != 0) { + ERROR("BL3-1:Failed the SYSTEM-OFF.\n"); + } + wfi(); + ERROR("RCAR System Off: operation not handled.\n"); + panic(); +} + +static void __dead2 rcar_system_reset(void) +{ + int32_t error; + + error = rcar_iic_dvfs_send(SLAVE_ADDR_PMIC + ,REG_ADDR_BKUP_Mode_Cnt + ,REG_DATA_P_ALL_OFF); + if (error != 0) { + ERROR("BL3-1:Failed the SYSTEM-RESET.\n"); + } + wfi(); + ERROR("RCAR System Reset: operation not handled.\n"); + panic(); +} + +/******************************************************************************* + * RCAR handler called to check the validity of the power state parameter. + ******************************************************************************/ +int rcar_validate_power_state(unsigned int power_state) +{ + /* Sanity check the requested state */ + if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { + /* + * It's possible to enter standby only on affinity level 0 + * i.e. a cpu on the rcar. Ignore any other affinity level. + */ + if (psci_get_pstate_afflvl(power_state) != MPIDR_AFFLVL0) { + return PSCI_E_INVALID_PARAMS; + } + } + + /* + * We expect the 'state id' to be zero. + */ + if (psci_get_pstate_id(power_state) != 0U) { + return PSCI_E_INVALID_PARAMS; + } + + return PSCI_E_SUCCESS; +} + +unsigned int rcar_get_sys_suspend_power_state(void) +{ + return psci_make_powerstate(0, PSTATE_TYPE_POWERDOWN, + PLATFORM_MAX_AFFLVL); +} +/******************************************************************************* + * Export the platform handlers to enable psci to invoke them + ******************************************************************************/ +static const plat_pm_ops_t rcar_plat_pm_ops = { + .affinst_standby = rcar_affinst_standby, + .affinst_on = rcar_affinst_on, + .affinst_off = rcar_affinst_off, + .affinst_suspend = rcar_affinst_suspend, + .affinst_on_finish = rcar_affinst_on_finish, + .affinst_suspend_finish = rcar_affinst_suspend_finish, + .system_off = rcar_system_off, + .system_reset = rcar_system_reset, + .validate_power_state = rcar_validate_power_state, + .get_sys_suspend_power_state = rcar_get_sys_suspend_power_state +}; + +/******************************************************************************* + * Export the platform specific power ops & initialize the rcar power controller + ******************************************************************************/ +int platform_setup_pm(const plat_pm_ops_t **plat_ops) +{ + *plat_ops = &rcar_plat_pm_ops; + return 0; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_private.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_private.h new file mode 100644 index 0000000..b5894a1 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_private.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_PRIVATE_H__ +#define RCAR_PRIVATE_H__ + +#include +#include +#include +#include + + +typedef volatile struct mailbox { + unsigned long value + __attribute__((__aligned__(CACHE_WRITEBACK_GRANULE))); +} mailbox_t; + +/******************************************************************************* + * This structure represents the superset of information that is passed to + * BL31 e.g. while passing control to it from BL2 which is bl31_params + * and bl31_plat_params and its elements + ******************************************************************************/ +typedef struct bl2_to_bl31_params_mem { + bl31_params_t bl31_params; + image_info_t bl31_image_info; + image_info_t bl32_image_info; + image_info_t bl33_image_info; + entry_point_info_t bl33_ep_info; + entry_point_info_t bl32_ep_info; + entry_point_info_t bl31_ep_info; +} bl2_to_bl31_params_mem_t; + +#if USE_COHERENT_MEM +/* + * Use this macro to instantiate lock before it is used in below + * rcar_lock_xxx() macros + */ +#define RCAR_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(rcar_lock); + +/* + * These are wrapper macros to the Coherent Memory Bakery Lock API. + */ +#define rcar_lock_init() bakery_lock_init(&rcar_lock) +#define rcar_lock_get() bakery_lock_get(&rcar_lock) +#define rcar_lock_release() bakery_lock_release(&rcar_lock) + + +#else + +/******************************************************************************* + * Constants to specify how many bakery locks this platform implements. These + * are used if the platform chooses not to use coherent memory for bakery lock + * data structures. + ******************************************************************************/ +#define RCAR_MAX_BAKERIES 2 +#define RCAR_PWRC_BAKERY_ID 0 + +/******************************************************************************* + * Definition of structure which holds platform specific per-cpu data. Currently + * it holds only the bakery lock information for each cpu. Constants to + * specify how many bakeries this platform implements and bakery ids are + * specified in rcar_def.h + ******************************************************************************/ +typedef struct rcar_cpu_data { + bakery_info_t pcpu_bakery_info[RCAR_MAX_BAKERIES]; +} rcar_cpu_data_t; + +/* Macro to define the offset of bakery_info_t in rcar_cpu_data_t */ +#define RCAR_CPU_DATA_LOCK_OFFSET __builtin_offsetof\ + (rcar_cpu_data_t, pcpu_bakery_info) + + +/******************************************************************************* + * Helper macros for bakery lock api when using the above rcar_cpu_data_t for + * bakery lock data structures. It assumes that the bakery_info is at the + * beginning of the platform specific per-cpu data. + ******************************************************************************/ +#define rcar_lock_init(_lock_arg) /* No init required */ +#define rcar_lock_get(_lock_arg) bakery_lock_get(_lock_arg, \ + CPU_DATA_PLAT_PCPU_OFFSET + \ + RCAR_CPU_DATA_LOCK_OFFSET) +#define rcar_lock_release(_lock_arg) bakery_lock_release(_lock_arg, \ + CPU_DATA_PLAT_PCPU_OFFSET + \ + RCAR_CPU_DATA_LOCK_OFFSET) + +/* + * Ensure that the size of the RCAR specific per-cpu data structure and the size + * of the memory allocated in generic per-cpu data for the platform are the same. + */ +CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(rcar_cpu_data_t), \ + rcar_pcpu_data_size_mismatch); + +#endif /* __USE_COHERENT_MEM__ */ + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void rcar_configure_mmu_el1(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long +#if USE_COHERENT_MEM + , unsigned long, + unsigned long +#endif + ); +void rcar_configure_mmu_el3(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long +#if USE_COHERENT_MEM + , unsigned long, + unsigned long +#endif + ); + +void rcar_cci_init(void); +void rcar_cci_enable(void); +void rcar_cci_disable(void); + +/* Declarations for rcar_topology.c */ +void rcar_setup_topology(void); + +/* Gets the SPR for BL32 entry */ +uint32_t rcar_get_spsr_for_bl32_entry(void); + +/* Gets the SPSR for BL33 entry */ +uint32_t rcar_get_spsr_for_bl33_entry(void); + +/* Prototype function for power management */ +void rcar_affinst_standby(unsigned int power_state); +int rcar_affinst_on(unsigned long mpidr, unsigned long sec_entrypoint, + unsigned int afflvl, unsigned int state); +void rcar_affinst_off(unsigned int afflvl, unsigned int state); +void rcar_affinst_suspend(unsigned long sec_entrypoint, unsigned int afflvl, + unsigned int state); +void rcar_affinst_on_finish(unsigned int afflvl, unsigned int state); +void rcar_affinst_suspend_finish(unsigned int afflvl, unsigned int state); +int rcar_validate_power_state(unsigned int power_state); + +/* Function prototypes for read and write to the CPU system registers */ +void iciallu(void); + +#endif /* RCAR_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_topology.c b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_topology.c new file mode 100644 index 0000000..78dcdd9 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_topology.c @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +/* TODO: Reusing psci error codes & state information. Get our own! */ +#include +#include "drivers/pwrc/rcar_pwrc.h" + +/* We treat '255' as an invalid affinity instance */ +#define AFFINST_INVAL 0xff + +typedef struct affinity_info { + unsigned char sibling; + unsigned char child; + unsigned char state; + unsigned int data; +} affinity_info_t; + +/******************************************************************************* + * The following two data structures store the topology tree for the rcar. There + * is a separate array for each affinity level i.e. cpus and clusters. The child + * and sibling references allow traversal inside and in between the two arrays. + ******************************************************************************/ +static affinity_info_t rcar_aff1_topology_map[PLATFORM_CLUSTER_COUNT]; +static affinity_info_t rcar_aff0_topology_map[PLATFORM_CORE_COUNT]; + +/* Simple global variable to safeguard us from stupidity */ +static unsigned int topology_setup_done; + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform to allow the former to detect the platform + * topology. psci queries the platform to determine how many affinity instances + * are present at a particular level for a given mpidr e.g. consider a dual + * cluster platform where each cluster has 4 cpus. A call to this function with + * (0, 0x100) will return the number of cpus implemented under cluster 1 i.e. 4. + * Similarly a call with (1, 0x100) will return 2 i.e. the number of clusters. + * This is 'cause we are effectively asking how many affinity level 1 instances + * are implemented under affinity level 2 instance 0. + ******************************************************************************/ +unsigned int plat_get_aff_count(unsigned int aff_lvl, + unsigned long mpidr) +{ + unsigned int aff_count = 1, ctr; + unsigned char parent_aff_id; + + assert(topology_setup_done == 1); + + switch (aff_lvl) { + case 3: + case 2: + /* + * Assert if the parent affinity instance is not 0. + * This also takes care of level 3 in an obfuscated way + */ + parent_aff_id = (mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK; + assert(parent_aff_id == 0); + + /* + * Report that we implement a single instance of + * affinity levels 2 & 3 which are AFF_ABSENT + */ + break; + case 1: + /* Assert if the parent affinity instance is not 0. */ + parent_aff_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; + assert(parent_aff_id == 0); + + /* Fetch the starting index in the aff1 array */ + for (ctr = 0; + rcar_aff1_topology_map[ctr].sibling != AFFINST_INVAL; + ctr = rcar_aff1_topology_map[ctr].sibling) { + aff_count++; + } + + break; + case 0: + /* Assert if the cluster id is anything apart from 0 or 1 */ + parent_aff_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + assert(parent_aff_id < PLATFORM_CLUSTER_COUNT); + + /* Fetch the starting index in the aff0 array */ + for (ctr = rcar_aff1_topology_map[parent_aff_id].child; + rcar_aff0_topology_map[ctr].sibling != AFFINST_INVAL; + ctr = rcar_aff0_topology_map[ctr].sibling) { + aff_count++; + } + + break; + default: + assert(0); + } + + return aff_count; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform to allow the former to detect the state of a + * affinity instance in the platform topology. psci queries the platform to + * determine whether an affinity instance is present or absent. This caters for + * topologies where an intermediate affinity level instance is missing e.g. + * consider a platform which implements a single cluster with 4 cpus and there + * is another cpu sitting directly on the interconnect along with the cluster. + * The mpidrs of the cluster would range from 0x0-0x3. The mpidr of the single + * cpu would be 0x100 to highlight that it does not belong to cluster 0. Cluster + * 1 is however missing but needs to be accounted to reach this single cpu in + * the topology tree. Hence it will be marked as PSCI_AFF_ABSENT. This is not + * applicable to the RCAR but depicted as an example. + ******************************************************************************/ +unsigned int plat_get_aff_state(unsigned int aff_lvl, + unsigned long mpidr) +{ + unsigned int aff_state = PSCI_AFF_ABSENT, idx; + idx = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + + assert(topology_setup_done == 1); + + switch (aff_lvl) { + case 3: + case 2: + /* Report affinity levels 2 & 3 as absent */ + break; + case 1: + aff_state = rcar_aff1_topology_map[idx].state; + break; + case 0: + /* + * First get start index of the aff0 in its array & then add + * to it the affinity id that we want the state of + */ + idx = rcar_aff1_topology_map[idx].child; + idx += (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + aff_state = rcar_aff0_topology_map[idx].state; + break; + default: + assert(0); + } + + return aff_state; +} + +/******************************************************************************* + * This function populates the RCAR specific topology information depending upon + * the RCAR flavour its running on. We construct all the mpidrs we can handle + * and rely on the PRR to flag absent cpus when their status is queried. + ******************************************************************************/ +void rcar_setup_topology(void) +{ + unsigned char aff0, aff1, aff_state, aff0_offset = 0; + unsigned long mpidr; + + topology_setup_done = 0; + + for (aff1 = 0; aff1 < PLATFORM_CLUSTER_COUNT; aff1++) { + + rcar_aff1_topology_map[aff1].child = aff0_offset; + rcar_aff1_topology_map[aff1].sibling = aff1 + 1; + + for (aff0 = 0; aff0 < PLATFORM_MAX_CPUS_PER_CLUSTER; aff0++) { + + mpidr = aff1 << MPIDR_AFF1_SHIFT; + mpidr |= aff0 << MPIDR_AFF0_SHIFT; + + if (rcar_pwrc_status(mpidr) != RCAR_INVALID) { + /* + * Presence of even a single aff0 indicates + * presence of parent aff1 on the RCAR. + */ + aff_state = PSCI_AFF_PRESENT; + rcar_aff1_topology_map[aff1].state = + PSCI_AFF_PRESENT; + } else { + aff_state = PSCI_AFF_ABSENT; + } + + rcar_aff0_topology_map[aff0_offset].child = AFFINST_INVAL; + rcar_aff0_topology_map[aff0_offset].state = aff_state; + rcar_aff0_topology_map[aff0_offset].sibling = + aff0_offset + 1; + + /* Increment the absolute number of aff0s traversed */ + aff0_offset++; + } + + /* Tie-off the last aff0 sibling to -1 to avoid overflow */ + rcar_aff0_topology_map[aff0_offset - 1].sibling = AFFINST_INVAL; + } + + /* Tie-off the last aff1 sibling to AFFINST_INVAL to avoid overflow */ + rcar_aff1_topology_map[aff1 - 1].sibling = AFFINST_INVAL; + + topology_setup_done = 1; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_version.h b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_version.h new file mode 100644 index 0000000..3ca8ed9 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/plat/renesas/rcar/rcar_version.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2015-2018, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_VERSION_H__ +#define RCAR_VERSION_H__ + +#include + +#define VERSION_OF_RENESAS "0.04" +#define VERSION_OF_RENESAS_MAXLEN (128) + +extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]; + +#endif /* RCAR_VERSION_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/readme.md b/IPL/SDK/v3m/src/Dummy_BL33/readme.md new file mode 100644 index 0000000..454b5f1 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/readme.md @@ -0,0 +1,162 @@ +ARM Trusted Firmware - version 1.1 +================================== + +ARM Trusted Firmware provides a reference implementation of secure world +software for [ARMv8-A], including Exception Level 3 (EL3) software. This release +provides complete support for version 0.2 of the [PSCI] specification, initial +support for the new version 1.0 of that specification, and prototype support for +the Trusted Board Boot Requirements specification. + +The intent is to provide a reference implementation of various ARM interface +standards, such as the Power State Coordination Interface ([PSCI]), Trusted +Board Boot Requirements (TBBR) and [Secure Monitor] [TEE-SMC] code. As far as +possible the code is designed for reuse or porting to other ARMv8-A model and +hardware platforms. + +ARM will continue development in collaboration with interested parties to +provide a full reference implementation of PSCI, TBBR and Secure Monitor code +to the benefit of all developers working with ARMv8-A TrustZone technology. + + +License +------- + +The software is provided under a BSD 3-Clause [license]. Certain source files +are derived from FreeBSD code: the original license is included in these +source files. + + +This Release +------------ + +This release is a limited functionality implementation of the Trusted Firmware. +It provides a suitable starting point for productization. Future versions will +contain new features, optimizations and quality improvements. + +### Functionality + +* Prototype implementation of a subset of the Trusted Board Boot Requirements + Platform Design Document (PDD). This includes packaging the various firmware + images into a Firmware Image Package (FIP) to be loaded from non-volatile + storage, and a prototype of authenticated boot using key certificates stored + in the FIP. + +* Initializes the secure world (for example, exception vectors, control + registers, GIC and interrupts for the platform), before transitioning into + the normal world. + +* Supports both GICv2 and GICv3 initialization for use by normal world + software. + +* Starts the normal world at the Exception Level and Register Width specified + by the platform port. Typically this is AArch64 EL2 if available. + +* Handles SMCs (Secure Monitor Calls) conforming to the [SMC Calling + Convention PDD] [SMCCC] using an EL3 runtime services framework. + +* Handles SMCs relating to the [Power State Coordination Interface PDD] [PSCI] + for the Secondary CPU Boot, CPU Hotplug, CPU Idle and System Shutdown/Reset + use-cases. + +* A Test Secure-EL1 Payload and Dispatcher to demonstrate Secure Monitor + functionality such as world switching, EL1 context management and interrupt + routing. This also demonstrates Secure-EL1 interaction with PSCI. Some of + this functionality is provided in library form for re-use by other + Secure-EL1 Payload Dispatchers. + +* Support for alternative Trusted Boot Firmware. Some platforms have their own + Trusted Boot implementation and only require the Secure Monitor + functionality provided by ARM Trusted Firmware. + +* Isolation of memory accessible by the secure world from the normal world + through programming of a TrustZone controller. + +* Support for CPU specific reset sequences, power down sequences and register + dumping during crash reporting. The CPU specific reset sequences include + support for errata workarounds. + +For a full description of functionality and implementation details, please +see the [Firmware Design] and supporting documentation. The [Change Log] +provides details of changes made since the last release. + +### Platforms + +This release of the Trusted Firmware has been tested on Revision B of the +[Juno ARM Development Platform] [Juno] with Version r0p0-00rel7 of the +[ARM SCP Firmware] [SCP download]. + +The Trusted Firmware has also been tested on the 64-bit Linux versions of the +following ARM [FVP]s: + +* `Foundation_Platform` (Version 9.1, Build 9.1.33) +* `FVP_Base_AEMv8A-AEMv8A` (Version 6.2, Build 0.8.6202) +* `FVP_Base_Cortex-A57x4-A53x4` (Version 6.2, Build 0.8.6202) +* `FVP_Base_Cortex-A57x1-A53x1` (Version 6.2, Build 0.8.6202) +* `FVP_Base_Cortex-A57x2-A53x4` (Version 6.2, Build 0.8.6202) + +The Foundation FVP can be downloaded free of charge. The Base FVPs can be +licensed from ARM: see [www.arm.com/fvp] [FVP]. + +### Still to Come + +* Complete and more flexible Trusted Board Boot implementation. + +* Complete implementation of the [PSCI] v1.0 specification. + +* Support for alternative types of Secure-EL1 Payloads. + +* Extending the GICv3 support to the secure world. + +* Support for new System IP devices. + +For a full list of detailed issues in the current code, please see the [Change +Log] and the [GitHub issue tracker]. + + +Getting Started +--------------- + +Get the Trusted Firmware source code from +[GitHub](https://www.github.com/ARM-software/arm-trusted-firmware). + +See the [User Guide] for instructions on how to install, build and use +the Trusted Firmware with the ARM [FVP]s. + +See the [Firmware Design] for information on how the ARM Trusted Firmware works. + +See the [Porting Guide] as well for information about how to use this +software on another ARMv8-A platform. + +See the [Contributing Guidelines] for information on how to contribute to this +project and the [Acknowledgments] file for a list of contributors to the +project. + +### Feedback and support + +ARM welcomes any feedback on the Trusted Firmware. Please send feedback using +the [GitHub issue tracker]. + +ARM licensees may contact ARM directly via their partner managers. + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved._ + + +[License]: ./license.md "BSD license for ARM Trusted Firmware" +[Contributing Guidelines]: ./contributing.md "Guidelines for contributors" +[Acknowledgments]: ./acknowledgements.md "Contributor acknowledgments" +[Change Log]: ./docs/change-log.md +[User Guide]: ./docs/user-guide.md +[Firmware Design]: ./docs/firmware-design.md +[Porting Guide]: ./docs/porting-guide.md + +[ARMv8-A]: http://www.arm.com/products/processors/armv8-architecture.php "ARMv8-A Architecture" +[FVP]: http://www.arm.com/fvp "ARM's Fixed Virtual Platforms" +[Juno]: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php "Juno ARM Development Platform" +[SCP download]: https://silver.arm.com/download/download.tm?pv=1764630 +[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)" +[SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)" +[TEE-SMC]: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php "Secure Monitor and TEEs" +[GitHub issue tracker]: https://github.com/ARM-software/tf-issues/issues diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed.mk b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed.mk new file mode 100644 index 0000000..2141bba --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed.mk @@ -0,0 +1,39 @@ +# +# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +OPTEED_DIR := services/spd/opteed +SPD_INCLUDES := + +SPD_SOURCES := services/spd/opteed/opteed_common.c \ + services/spd/opteed/opteed_helpers.S \ + services/spd/opteed/opteed_main.c \ + services/spd/opteed/opteed_pm.c + +NEED_BL32 := no diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_common.c b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_common.c new file mode 100644 index 0000000..2f20b7c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_common.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "opteed_private.h" + +/******************************************************************************* + * Given a OPTEE entrypoint info pointer, entry point PC, register width, + * cpu id & pointer to a context data structure, this function will + * initialize OPTEE context and entry point info for OPTEE. + ******************************************************************************/ +void opteed_init_optee_ep_state(struct entry_point_info *optee_entry_point, + uint32_t rw, uint64_t pc, + optee_context_t *optee_ctx) +{ + uint32_t ep_attr; + + /* Passing a NULL context is a critical programming error */ + assert(optee_ctx); + assert(optee_entry_point); + assert(pc); + + /* Associate this context with the cpu specified */ + optee_ctx->mpidr = read_mpidr_el1(); + optee_ctx->state = 0; + set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_OFF); + + cm_set_context(&optee_ctx->cpu_ctx, SECURE); + + /* initialise an entrypoint to set up the CPU context */ + ep_attr = SECURE | EP_ST_ENABLE; + if (read_sctlr_el3() & SCTLR_EE_BIT) + ep_attr |= EP_EE_BIG; + SET_PARAM_HEAD(optee_entry_point, PARAM_EP, VERSION_1, ep_attr); + optee_entry_point->pc = pc; + if (rw == OPTEE_AARCH64) + optee_entry_point->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + else + optee_entry_point->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, + SPSR_E_LITTLE, + DAIF_FIQ_BIT | + DAIF_IRQ_BIT | + DAIF_ABT_BIT); + memset(&optee_entry_point->args, 0, sizeof(optee_entry_point->args)); +} + +/******************************************************************************* + * This function takes an OPTEE context pointer and: + * 1. Applies the S-EL1 system register context from optee_ctx->cpu_ctx. + * 2. Saves the current C runtime state (callee saved registers) on the stack + * frame and saves a reference to this state. + * 3. Calls el3_exit() so that the EL3 system and general purpose registers + * from the optee_ctx->cpu_ctx are used to enter the OPTEE image. + ******************************************************************************/ +uint64_t opteed_synchronous_sp_entry(optee_context_t *optee_ctx) +{ + uint64_t rc; + + assert(optee_ctx != NULL); + assert(optee_ctx->c_rt_ctx == 0); + + /* Apply the Secure EL1 system register context and switch to it */ + assert(cm_get_context(SECURE) == &optee_ctx->cpu_ctx); + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + + rc = opteed_enter_sp(&optee_ctx->c_rt_ctx); +#if DEBUG + optee_ctx->c_rt_ctx = 0; +#endif + + return rc; +} + + +/******************************************************************************* + * This function takes an OPTEE context pointer and: + * 1. Saves the S-EL1 system register context tp optee_ctx->cpu_ctx. + * 2. Restores the current C runtime state (callee saved registers) from the + * stack frame using the reference to this state saved in opteed_enter_sp(). + * 3. It does not need to save any general purpose or EL3 system register state + * as the generic smc entry routine should have saved those. + ******************************************************************************/ +void opteed_synchronous_sp_exit(optee_context_t *optee_ctx, uint64_t ret) +{ + assert(optee_ctx != NULL); + /* Save the Secure EL1 system register context */ + assert(cm_get_context(SECURE) == &optee_ctx->cpu_ctx); + cm_el1_sysregs_context_save(SECURE); + + assert(optee_ctx->c_rt_ctx != 0); + opteed_exit_sp(optee_ctx->c_rt_ctx, ret); + + /* Should never reach here */ + assert(0); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_helpers.S new file mode 100644 index 0000000..32c38f1 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_helpers.S @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "opteed_private.h" + + .global opteed_enter_sp + /* --------------------------------------------- + * This function is called with SP_EL0 as stack. + * Here we stash our EL3 callee-saved registers + * on to the stack as a part of saving the C + * runtime and enter the secure payload. + * 'x0' contains a pointer to the memory where + * the address of the C runtime context is to be + * saved. + * --------------------------------------------- + */ +func opteed_enter_sp + /* Make space for the registers that we're going to save */ + mov x3, sp + str x3, [x0, #0] + sub sp, sp, #OPTEED_C_RT_CTX_SIZE + + /* Save callee-saved registers on to the stack */ + stp x19, x20, [sp, #OPTEED_C_RT_CTX_X19] + stp x21, x22, [sp, #OPTEED_C_RT_CTX_X21] + stp x23, x24, [sp, #OPTEED_C_RT_CTX_X23] + stp x25, x26, [sp, #OPTEED_C_RT_CTX_X25] + stp x27, x28, [sp, #OPTEED_C_RT_CTX_X27] + stp x29, x30, [sp, #OPTEED_C_RT_CTX_X29] + + /* --------------------------------------------- + * Everything is setup now. el3_exit() will + * use the secure context to restore to the + * general purpose and EL3 system registers to + * ERET into OPTEE. + * --------------------------------------------- + */ + b el3_exit +endfunc opteed_enter_sp + + /* --------------------------------------------- + * This function is called 'x0' pointing to a C + * runtime context saved in opteed_enter_sp(). It + * restores the saved registers and jumps to + * that runtime with 'x0' as the new sp. This + * destroys the C runtime context that had been + * built on the stack below the saved context by + * the caller. Later the second parameter 'x1' + * is passed as return value to the caller + * --------------------------------------------- + */ + .global opteed_exit_sp +func opteed_exit_sp + /* Restore the previous stack */ + mov sp, x0 + + /* Restore callee-saved registers on to the stack */ + ldp x19, x20, [x0, #(OPTEED_C_RT_CTX_X19 - OPTEED_C_RT_CTX_SIZE)] + ldp x21, x22, [x0, #(OPTEED_C_RT_CTX_X21 - OPTEED_C_RT_CTX_SIZE)] + ldp x23, x24, [x0, #(OPTEED_C_RT_CTX_X23 - OPTEED_C_RT_CTX_SIZE)] + ldp x25, x26, [x0, #(OPTEED_C_RT_CTX_X25 - OPTEED_C_RT_CTX_SIZE)] + ldp x27, x28, [x0, #(OPTEED_C_RT_CTX_X27 - OPTEED_C_RT_CTX_SIZE)] + ldp x29, x30, [x0, #(OPTEED_C_RT_CTX_X29 - OPTEED_C_RT_CTX_SIZE)] + + /* --------------------------------------------- + * This should take us back to the instruction + * after the call to the last opteed_enter_sp(). + * Place the second parameter to x0 so that the + * caller will see it as a return value from the + * original entry call + * --------------------------------------------- + */ + mov x0, x1 + ret +endfunc opteed_exit_sp \ No newline at end of file diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_main.c b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_main.c new file mode 100644 index 0000000..302ed9a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_main.c @@ -0,0 +1,443 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +/******************************************************************************* + * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a + * plug-in component to the Secure Monitor, registered as a runtime service. The + * SPD is expected to be a functional extension of the Secure Payload (SP) that + * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting + * the Trusted OS/Applications range to the dispatcher. The SPD will either + * handle the request locally or delegate it to the Secure Payload. It is also + * responsible for initialising and maintaining communication with the SP. + ******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "opteed_private.h" +#include "teesmc_opteed_macros.h" +#include "teesmc_opteed.h" + +/******************************************************************************* + * Address of the entrypoint vector table in OPTEE. It is + * initialised once on the primary core after a cold boot. + ******************************************************************************/ +optee_vectors_t *optee_vectors; + +/******************************************************************************* + * Array to keep track of per-cpu OPTEE state + ******************************************************************************/ +optee_context_t opteed_sp_context[OPTEED_CORE_COUNT]; +uint32_t opteed_rw; + + + +static int32_t opteed_init(void); + +/******************************************************************************* + * This function is the handler registered for S-EL1 interrupts by the + * OPTEED. It validates the interrupt and upon success arranges entry into + * the OPTEE at 'optee_fiq_entry()' for handling the interrupt. + ******************************************************************************/ +static uint64_t opteed_sel1_interrupt_handler(uint32_t id, + uint32_t flags, + void *handle, + void *cookie) +{ + uint32_t linear_id; + optee_context_t *optee_ctx; + + /* Check the security state when the exception was generated */ + assert(get_interrupt_src_ss(flags) == NON_SECURE); + +#if IMF_READ_INTERRUPT_ID + /* Check the security status of the interrupt */ + assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_S_EL1); +#endif + + /* Sanity check the pointer to this cpu's context */ + assert(handle == cm_get_context(NON_SECURE)); + + /* Save the non-secure context before entering the OPTEE */ + cm_el1_sysregs_context_save(NON_SECURE); + + /* Get a reference to this cpu's OPTEE context */ + linear_id = plat_my_core_pos(); + optee_ctx = &opteed_sp_context[linear_id]; + assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE)); + + cm_set_elr_el3(SECURE, (uint64_t)&optee_vectors->fiq_entry); + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + + /* + * Tell the OPTEE that it has to handle an FIQ (synchronously). + * Also the instruction in normal world where the interrupt was + * generated is passed for debugging purposes. It is safe to + * retrieve this address from ELR_EL3 as the secure context will + * not take effect until el3_exit(). + */ + SMC_RET1(&optee_ctx->cpu_ctx, read_elr_el3()); +} + +/******************************************************************************* + * OPTEE Dispatcher setup. The OPTEED finds out the OPTEE entrypoint and type + * (aarch32/aarch64) if not already known and initialises the context for entry + * into OPTEE for its initialization. + ******************************************************************************/ +int32_t opteed_setup(void) +{ + entry_point_info_t *optee_ep_info; + uint32_t linear_id; + + linear_id = plat_my_core_pos(); + + /* + * Get information about the Secure Payload (BL32) image. Its + * absence is a critical failure. TODO: Add support to + * conditionally include the SPD service + */ + optee_ep_info = bl31_plat_get_next_image_ep_info(SECURE); + if (!optee_ep_info) { + WARN("No OPTEE provided by BL2 boot loader, Booting device" + " without OPTEE initialization. SMC`s destined for OPTEE" + " will return SMC_UNK\n"); + return 1; + } + + /* + * If there's no valid entry point for SP, we return a non-zero value + * signalling failure initializing the service. We bail out without + * registering any handlers + */ + if (!optee_ep_info->pc) + return 1; + + /* + * We could inspect the SP image and determine it's execution + * state i.e whether AArch32 or AArch64. Assuming it's AArch32 + * for the time being. + */ + opteed_rw = OPTEE_AARCH64; + opteed_init_optee_ep_state(optee_ep_info, + opteed_rw, + optee_ep_info->pc, + &opteed_sp_context[linear_id]); + + /* + * All OPTEED initialization done. Now register our init function with + * BL31 for deferred invocation + */ + bl31_register_bl32_init(&opteed_init); + + return 0; +} + +/******************************************************************************* + * This function passes control to the OPTEE image (BL32) for the first time + * on the primary cpu after a cold boot. It assumes that a valid secure + * context has already been created by opteed_setup() which can be directly + * used. It also assumes that a valid non-secure context has been + * initialised by PSCI so it does not need to save and restore any + * non-secure state. This function performs a synchronous entry into + * OPTEE. OPTEE passes control back to this routine through a SMC. + ******************************************************************************/ +static int32_t opteed_init(void) +{ + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + entry_point_info_t *optee_entry_point; + uint64_t rc; + + /* + * Get information about the OPTEE (BL32) image. Its + * absence is a critical failure. + */ + optee_entry_point = bl31_plat_get_next_image_ep_info(SECURE); + assert(optee_entry_point); + + cm_init_my_context(optee_entry_point); + + /* + * Arrange for an entry into OPTEE. It will be returned via + * OPTEE_ENTRY_DONE case + */ + rc = opteed_synchronous_sp_entry(optee_ctx); + assert(rc != 0); + + return rc; +} + + +/******************************************************************************* + * This function is responsible for handling all SMCs in the Trusted OS/App + * range from the non-secure state as defined in the SMC Calling Convention + * Document. It is also responsible for communicating with the Secure + * payload to delegate work and return results back to the non-secure + * state. Lastly it will also return any information that OPTEE needs to do + * the work assigned to it. + ******************************************************************************/ +uint64_t opteed_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + cpu_context_t *ns_cpu_context; + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + uint64_t rc; + + /* + * Determine which security state this SMC originated from + */ + + if (is_caller_non_secure(flags)) { + /* + * This is a fresh request from the non-secure client. + * The parameters are in x1 and x2. Figure out which + * registers need to be preserved, save the non-secure + * state and send the request to the secure payload. + */ + assert(handle == cm_get_context(NON_SECURE)); + + cm_el1_sysregs_context_save(NON_SECURE); + + /* + * We are done stashing the non-secure context. Ask the + * OPTEE to do the work now. + */ + + /* + * Verify if there is a valid context to use, copy the + * operation type and parameters to the secure context + * and jump to the fast smc entry point in the secure + * payload. Entry into S-EL1 will take place upon exit + * from this function. + */ + assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE)); + + /* Set appropriate entry for SMC. + * We expect OPTEE to manage the PSTATE.I and PSTATE.F + * flags as appropriate. + */ + if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) { + cm_set_elr_el3(SECURE, (uint64_t) + &optee_vectors->fast_smc_entry); + } else { + cm_set_elr_el3(SECURE, (uint64_t) + &optee_vectors->std_smc_entry); + } + + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + + write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), + CTX_GPREG_X4, + read_ctx_reg(get_gpregs_ctx(handle), + CTX_GPREG_X4)); + write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), + CTX_GPREG_X5, + read_ctx_reg(get_gpregs_ctx(handle), + CTX_GPREG_X5)); + write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), + CTX_GPREG_X6, + read_ctx_reg(get_gpregs_ctx(handle), + CTX_GPREG_X6)); + /* Propagate hypervisor client ID */ + write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), + CTX_GPREG_X7, + read_ctx_reg(get_gpregs_ctx(handle), + CTX_GPREG_X7)); + + SMC_RET4(&optee_ctx->cpu_ctx, smc_fid, x1, x2, x3); + } + + /* + * Returning from OPTEE + */ + + switch (smc_fid) { + /* + * OPTEE has finished initialising itself after a cold boot + */ + case TEESMC_OPTEED_RETURN_ENTRY_DONE: + /* + * Stash the OPTEE entry points information. This is done + * only once on the primary cpu + */ + assert(optee_vectors == NULL); + optee_vectors = (optee_vectors_t *) x1; + + if (optee_vectors) { + set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_ON); + + /* + * OPTEE has been successfully initialized. + * Register power management hooks with PSCI + */ + psci_register_spd_pm_hook(&opteed_pm); + + /* + * Register an interrupt handler for S-EL1 interrupts + * when generated during code executing in the + * non-secure state. + */ + flags = 0; + set_interrupt_rm_flag(flags, NON_SECURE); + rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, + opteed_sel1_interrupt_handler, + flags); + if (rc) + panic(); + } + + /* + * OPTEE reports completion. The OPTEED must have initiated + * the original request through a synchronous entry into + * OPTEE. Jump back to the original C runtime context. + */ + opteed_synchronous_sp_exit(optee_ctx, x1); + + + /* + * These function IDs is used only by OP-TEE to indicate it has + * finished: + * 1. turning itself on in response to an earlier psci + * cpu_on request + * 2. resuming itself after an earlier psci cpu_suspend + * request. + */ + case TEESMC_OPTEED_RETURN_ON_DONE: + case TEESMC_OPTEED_RETURN_RESUME_DONE: + + + /* + * These function IDs is used only by the SP to indicate it has + * finished: + * 1. suspending itself after an earlier psci cpu_suspend + * request. + * 2. turning itself off in response to an earlier psci + * cpu_off request. + */ + case TEESMC_OPTEED_RETURN_OFF_DONE: + case TEESMC_OPTEED_RETURN_SUSPEND_DONE: + case TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE: + case TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE: + + /* + * OPTEE reports completion. The OPTEED must have initiated the + * original request through a synchronous entry into OPTEE. + * Jump back to the original C runtime context, and pass x1 as + * return value to the caller + */ + opteed_synchronous_sp_exit(optee_ctx, x1); + + /* + * OPTEE is returning from a call or being preempted from a call, in + * either case execution should resume in the normal world. + */ + case TEESMC_OPTEED_RETURN_CALL_DONE: + /* + * This is the result from the secure client of an + * earlier request. The results are in x0-x3. Copy it + * into the non-secure context, save the secure state + * and return to the non-secure state. + */ + assert(handle == cm_get_context(SECURE)); + cm_el1_sysregs_context_save(SECURE); + + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* Restore non-secure state */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + + SMC_RET4(ns_cpu_context, x1, x2, x3, x4); + + /* + * OPTEE has finished handling a S-EL1 FIQ interrupt. Execution + * should resume in the normal world. + */ + case TEESMC_OPTEED_RETURN_FIQ_DONE: + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* + * Restore non-secure state. There is no need to save the + * secure system register context since OPTEE was supposed + * to preserve it during S-EL1 interrupt handling. + */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + + SMC_RET0((uint64_t) ns_cpu_context); + + default: + panic(); + } +} + +/* Define an OPTEED runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + opteed_fast, + + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_FAST, + opteed_setup, + opteed_smc_handler +); + +/* Define an OPTEED runtime service descriptor for standard SMC calls */ +DECLARE_RT_SVC( + opteed_std, + + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_STD, + NULL, + opteed_smc_handler +); diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_pm.c b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_pm.c new file mode 100644 index 0000000..bd3185c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_pm.c @@ -0,0 +1,243 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "opteed_private.h" + +/******************************************************************************* + * The target cpu is being turned on. Allow the OPTEED/OPTEE to perform any + * actions needed. Nothing at the moment. + ******************************************************************************/ +static void opteed_cpu_on_handler(uint64_t target_cpu) +{ +} + +/******************************************************************************* + * This cpu is being turned off. Allow the OPTEED/OPTEE to perform any actions + * needed + ******************************************************************************/ +static int32_t opteed_cpu_off_handler(uint64_t unused) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + + assert(optee_vectors); + assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); + + /* Program the entry point and enter OPTEE */ + cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_off_entry); + rc = opteed_synchronous_sp_entry(optee_ctx); + + /* + * Read the response from OPTEE. A non-zero return means that + * something went wrong while communicating with OPTEE. + */ + if (rc != 0) + panic(); + + /* + * Reset OPTEE's context for a fresh start when this cpu is turned on + * subsequently. + */ + set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_OFF); + + return 0; +} + +/******************************************************************************* + * This cpu is being suspended. S-EL1 state must have been saved in the + * resident cpu (mpidr format) if it is a UP/UP migratable OPTEE. + ******************************************************************************/ +static void opteed_cpu_suspend_handler(uint64_t max_off_pwrlvl) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + + assert(optee_vectors); + assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); + + /* Program the entry point and enter OPTEE */ + cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_suspend_entry); + rc = opteed_synchronous_sp_entry(optee_ctx); + + /* + * Read the response from OPTEE. A non-zero return means that + * something went wrong while communicating with OPTEE. + */ + if (rc != 0) + panic(); + + /* Update its context to reflect the state OPTEE is in */ + set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_SUSPEND); +} + +/******************************************************************************* + * This cpu has been turned on. Enter OPTEE to initialise S-EL1 and other bits + * before passing control back to the Secure Monitor. Entry in S-El1 is done + * after initialising minimal architectural state that guarantees safe + * execution. + ******************************************************************************/ +static void opteed_cpu_on_finish_handler(uint64_t unused) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + entry_point_info_t optee_on_entrypoint; + + assert(optee_vectors); + assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_OFF); + + opteed_init_optee_ep_state(&optee_on_entrypoint, opteed_rw, + (uint64_t)&optee_vectors->cpu_on_entry, + optee_ctx); + + /* Initialise this cpu's secure context */ + cm_init_my_context(&optee_on_entrypoint); + + /* Enter OPTEE */ + rc = opteed_synchronous_sp_entry(optee_ctx); + + /* + * Read the response from OPTEE. A non-zero return means that + * something went wrong while communicating with OPTEE. + */ + if (rc != 0) + panic(); + + /* Update its context to reflect the state OPTEE is in */ + set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_ON); +} + +/******************************************************************************* + * This cpu has resumed from suspend. The OPTEED saved the OPTEE context when it + * completed the preceding suspend call. Use that context to program an entry + * into OPTEE to allow it to do any remaining book keeping + ******************************************************************************/ +static void opteed_cpu_suspend_finish_handler(uint64_t max_off_pwrlvl) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + + assert(optee_vectors); + assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_SUSPEND); + + /* Program the entry point, max_off_pwrlvl and enter the SP */ + write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), + CTX_GPREG_X0, + max_off_pwrlvl); + cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_resume_entry); + rc = opteed_synchronous_sp_entry(optee_ctx); + + /* + * Read the response from OPTEE. A non-zero return means that + * something went wrong while communicating with OPTEE. + */ + if (rc != 0) + panic(); + + /* Update its context to reflect the state OPTEE is in */ + set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_ON); +} + +/******************************************************************************* + * Return the type of OPTEE the OPTEED is dealing with. Report the current + * resident cpu (mpidr format) if it is a UP/UP migratable OPTEE. + ******************************************************************************/ +static int32_t opteed_cpu_migrate_info(uint64_t *resident_cpu) +{ + return OPTEE_MIGRATE_INFO; +} + +/******************************************************************************* + * System is about to be switched off. Allow the OPTEED/OPTEE to perform + * any actions needed. + ******************************************************************************/ +static void opteed_system_off(void) +{ + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + + assert(optee_vectors); + assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); + + /* Program the entry point */ + cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->system_off_entry); + + /* Enter OPTEE. We do not care about the return value because we + * must continue the shutdown anyway */ + opteed_synchronous_sp_entry(optee_ctx); +} + +/******************************************************************************* + * System is about to be reset. Allow the OPTEED/OPTEE to perform + * any actions needed. + ******************************************************************************/ +static void opteed_system_reset(void) +{ + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + + assert(optee_vectors); + assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); + + /* Program the entry point */ + cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->system_reset_entry); + + /* Enter OPTEE. We do not care about the return value because we + * must continue the reset anyway */ + opteed_synchronous_sp_entry(optee_ctx); +} + + +/******************************************************************************* + * Structure populated by the OPTEE Dispatcher to be given a chance to + * perform any OPTEE bookkeeping before PSCI executes a power mgmt. + * operation. + ******************************************************************************/ +const spd_pm_ops_t opteed_pm = { + .svc_on = opteed_cpu_on_handler, + .svc_off = opteed_cpu_off_handler, + .svc_suspend = opteed_cpu_suspend_handler, + .svc_on_finish = opteed_cpu_on_finish_handler, + .svc_suspend_finish = opteed_cpu_suspend_finish_handler, + .svc_migrate = NULL, + .svc_migrate_info = opteed_cpu_migrate_info, + .svc_system_off = opteed_system_off, + .svc_system_reset = opteed_system_reset, +}; + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_private.h b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_private.h new file mode 100644 index 0000000..357c2ec --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/opteed_private.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __OPTEED_PRIVATE_H__ +#define __OPTEED_PRIVATE_H__ + +#include +#include +#include +#include +#include + +/******************************************************************************* + * OPTEE PM state information e.g. OPTEE is suspended, uninitialised etc + * and macros to access the state information in the per-cpu 'state' flags + ******************************************************************************/ +#define OPTEE_PSTATE_OFF 0 +#define OPTEE_PSTATE_ON 1 +#define OPTEE_PSTATE_SUSPEND 2 +#define OPTEE_PSTATE_SHIFT 0 +#define OPTEE_PSTATE_MASK 0x3 +#define get_optee_pstate(state) ((state >> OPTEE_PSTATE_SHIFT) & \ + OPTEE_PSTATE_MASK) +#define clr_optee_pstate(state) (state &= ~(OPTEE_PSTATE_MASK \ + << OPTEE_PSTATE_SHIFT)) +#define set_optee_pstate(st, pst) do { \ + clr_optee_pstate(st); \ + st |= (pst & OPTEE_PSTATE_MASK) << \ + OPTEE_PSTATE_SHIFT; \ + } while (0) + + +/******************************************************************************* + * OPTEE execution state information i.e. aarch32 or aarch64 + ******************************************************************************/ +#define OPTEE_AARCH32 MODE_RW_32 +#define OPTEE_AARCH64 MODE_RW_64 + +/******************************************************************************* + * The OPTEED should know the type of OPTEE + ******************************************************************************/ +#define OPTEE_TYPE_UP PSCI_TOS_NOT_UP_MIG_CAP +#define OPTEE_TYPE_UPM PSCI_TOS_UP_MIG_CAP +#define OPTEE_TYPE_MP PSCI_TOS_NOT_PRESENT_MP + +/******************************************************************************* + * OPTEE migrate type information as known to the OPTEED. We assume that + * the OPTEED is dealing with an MP Secure Payload. + ******************************************************************************/ +#define OPTEE_MIGRATE_INFO OPTEE_TYPE_MP + +/******************************************************************************* + * Number of cpus that the present on this platform. TODO: Rely on a topology + * tree to determine this in the future to avoid assumptions about mpidr + * allocation + ******************************************************************************/ +#define OPTEED_CORE_COUNT PLATFORM_CORE_COUNT + +/******************************************************************************* + * Constants that allow assembler code to preserve callee-saved registers of the + * C runtime context while performing a security state switch. + ******************************************************************************/ +#define OPTEED_C_RT_CTX_X19 0x0 +#define OPTEED_C_RT_CTX_X20 0x8 +#define OPTEED_C_RT_CTX_X21 0x10 +#define OPTEED_C_RT_CTX_X22 0x18 +#define OPTEED_C_RT_CTX_X23 0x20 +#define OPTEED_C_RT_CTX_X24 0x28 +#define OPTEED_C_RT_CTX_X25 0x30 +#define OPTEED_C_RT_CTX_X26 0x38 +#define OPTEED_C_RT_CTX_X27 0x40 +#define OPTEED_C_RT_CTX_X28 0x48 +#define OPTEED_C_RT_CTX_X29 0x50 +#define OPTEED_C_RT_CTX_X30 0x58 +#define OPTEED_C_RT_CTX_SIZE 0x60 +#define OPTEED_C_RT_CTX_ENTRIES (OPTEED_C_RT_CTX_SIZE >> DWORD_SHIFT) + +#ifndef __ASSEMBLY__ + +#include +#include + +typedef uint32_t optee_vector_isn_t; + +typedef struct optee_vectors { + optee_vector_isn_t std_smc_entry; + optee_vector_isn_t fast_smc_entry; + optee_vector_isn_t cpu_on_entry; + optee_vector_isn_t cpu_off_entry; + optee_vector_isn_t cpu_resume_entry; + optee_vector_isn_t cpu_suspend_entry; + optee_vector_isn_t fiq_entry; + optee_vector_isn_t system_off_entry; + optee_vector_isn_t system_reset_entry; +} optee_vectors_t; + +/* + * The number of arguments to save during a SMC call for OPTEE. + * Currently only x1 and x2 are used by OPTEE. + */ +#define OPTEE_NUM_ARGS 0x2 + +/* AArch64 callee saved general purpose register context structure. */ +DEFINE_REG_STRUCT(c_rt_regs, OPTEED_C_RT_CTX_ENTRIES); + +/* + * Compile time assertion to ensure that both the compiler and linker + * have the same double word aligned view of the size of the C runtime + * register context. + */ +CASSERT(OPTEED_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ + assert_spd_c_rt_regs_size_mismatch); + +/******************************************************************************* + * Structure which helps the OPTEED to maintain the per-cpu state of OPTEE. + * 'state' - collection of flags to track OPTEE state e.g. on/off + * 'mpidr' - mpidr to associate a context with a cpu + * 'c_rt_ctx' - stack address to restore C runtime context from after + * returning from a synchronous entry into OPTEE. + * 'cpu_ctx' - space to maintain OPTEE architectural state + ******************************************************************************/ +typedef struct optee_context { + uint32_t state; + uint64_t mpidr; + uint64_t c_rt_ctx; + cpu_context_t cpu_ctx; +} optee_context_t; + +/* OPTEED power management handlers */ +extern const spd_pm_ops_t opteed_pm; + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct optee_vectors; + +/******************************************************************************* + * Function & Data prototypes + ******************************************************************************/ +uint64_t opteed_enter_sp(uint64_t *c_rt_ctx); +void __dead2 opteed_exit_sp(uint64_t c_rt_ctx, uint64_t ret); +uint64_t opteed_synchronous_sp_entry(optee_context_t *optee_ctx); +void __dead2 opteed_synchronous_sp_exit(optee_context_t *optee_ctx, uint64_t ret); +void opteed_init_optee_ep_state(struct entry_point_info *optee_ep, + uint32_t rw, + uint64_t pc, + optee_context_t *optee_ctx); + +extern optee_context_t opteed_sp_context[OPTEED_CORE_COUNT]; +extern uint32_t opteed_rw; +extern struct optee_vectors *optee_vectors; +#endif /*__ASSEMBLY__*/ + +#endif /* __OPTEED_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/teesmc_opteed.h b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/teesmc_opteed.h new file mode 100644 index 0000000..7968d1f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/teesmc_opteed.h @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* Copyright (c) 2014, Linaro Limited. All rights reserved. */ + +#ifndef TEESMC_OPTEED_H +#define TEESMC_OPTEED_H + +/* + * This file specify SMC function IDs used when returning from TEE to the + * secure monitor. + * + * All SMC Function IDs indicates SMC32 Calling Convention but will carry + * full 64 bit values in the argument registers if invoked from Aarch64 + * mode. This violates the SMC Calling Convention, but since this + * convention only coveres API towards Normwal World it's something that + * only concerns the OP-TEE Dispatcher in ARM Trusted Firmware and OP-TEE + * OS at Secure EL1. + */ + +/* + * Issued when returning from initial entry. + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_ENTRY_DONE + * r1/x1 Pointer to entry vector + */ +#define TEESMC_OPTEED_FUNCID_RETURN_ENTRY_DONE 0 +#define TEESMC_OPTEED_RETURN_ENTRY_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_ENTRY_DONE) + + + +/* + * Issued when returning from "cpu_on" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_ON_DONE + * r1/x1 0 on success and anything else to indicate error condition + */ +#define TEESMC_OPTEED_FUNCID_RETURN_ON_DONE 1 +#define TEESMC_OPTEED_RETURN_ON_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_ON_DONE) + +/* + * Issued when returning from "cpu_off" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_OFF_DONE + * r1/x1 0 on success and anything else to indicate error condition + */ +#define TEESMC_OPTEED_FUNCID_RETURN_OFF_DONE 2 +#define TEESMC_OPTEED_RETURN_OFF_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_OFF_DONE) + +/* + * Issued when returning from "cpu_suspend" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_SUSPEND_DONE + * r1/x1 0 on success and anything else to indicate error condition + */ +#define TEESMC_OPTEED_FUNCID_RETURN_SUSPEND_DONE 3 +#define TEESMC_OPTEED_RETURN_SUSPEND_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_SUSPEND_DONE) + +/* + * Issued when returning from "cpu_resume" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_RESUME_DONE + * r1/x1 0 on success and anything else to indicate error condition + */ +#define TEESMC_OPTEED_FUNCID_RETURN_RESUME_DONE 4 +#define TEESMC_OPTEED_RETURN_RESUME_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_RESUME_DONE) + +/* + * Issued when returning from "std_smc" or "fast_smc" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_CALL_DONE + * r1-4/x1-4 Return value 0-3 which will passed to normal world in + * r0-3/x0-3 + */ +#define TEESMC_OPTEED_FUNCID_RETURN_CALL_DONE 5 +#define TEESMC_OPTEED_RETURN_CALL_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_CALL_DONE) + +/* + * Issued when returning from "fiq" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_FIQ_DONE + */ +#define TEESMC_OPTEED_FUNCID_RETURN_FIQ_DONE 6 +#define TEESMC_OPTEED_RETURN_FIQ_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_FIQ_DONE) + +/* + * Issued when returning from "system_off" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE + */ +#define TEESMC_OPTEED_FUNCID_RETURN_SYSTEM_OFF_DONE 7 +#define TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_SYSTEM_OFF_DONE) + +/* + * Issued when returning from "system_reset" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE + */ +#define TEESMC_OPTEED_FUNCID_RETURN_SYSTEM_RESET_DONE 8 +#define TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_SYSTEM_RESET_DONE) + +#endif /*TEESMC_OPTEED_H*/ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/teesmc_opteed_macros.h b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/teesmc_opteed_macros.h new file mode 100644 index 0000000..2453c9a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/opteed/teesmc_opteed_macros.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __TEESMC_OPTEED_MACROS_H__ +#define __TEESMC_OPTEED_MACROS_H__ + +#include + +#define TEESMC_OPTEED_RV(func_num) \ + ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ + ((SMC_32) << FUNCID_CC_SHIFT) | \ + (62 << FUNCID_OEN_SHIFT) | \ + ((func_num) & FUNCID_NUM_MASK)) + +#endif /*__TEESMC_OPTEED_MACROS_H__*/ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd.mk b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd.mk new file mode 100644 index 0000000..b1159e7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd.mk @@ -0,0 +1,36 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +SPD_INCLUDES := -Iinclude/bl32/payloads + +SPD_SOURCES := services/spd/tlkd/tlkd_common.c \ + services/spd/tlkd/tlkd_helpers.S \ + services/spd/tlkd/tlkd_main.c \ + services/spd/tlkd/tlkd_pm.c diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_common.c b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_common.c new file mode 100644 index 0000000..b19e27d --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_common.c @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "tlkd_private.h" + +#define AT_MASK 3 + +/******************************************************************************* + * This function helps the SP to translate NS/S virtual addresses. + ******************************************************************************/ +uint64_t tlkd_va_translate(uintptr_t va, int type) +{ + uint64_t pa; + + if (type & TLK_TRANSLATE_NS_VADDR) { + + /* save secure context */ + cm_el1_sysregs_context_save(SECURE); + + /* restore non-secure context */ + cm_el1_sysregs_context_restore(NON_SECURE); + + /* switch NS bit to start using 64-bit, non-secure mappings */ + write_scr(cm_get_scr_el3(NON_SECURE)); + isb(); + } + + int at = type & AT_MASK; + switch (at) { + case 0: + ats12e1r(va); + break; + case 1: + ats12e1w(va); + break; + case 2: + ats12e0r(va); + break; + case 3: + ats12e0w(va); + break; + default: + assert(0); + } + + /* get the (NS/S) physical address */ + isb(); + pa = read_par_el1(); + + /* Restore secure state */ + if (type & TLK_TRANSLATE_NS_VADDR) { + + /* restore secure context */ + cm_el1_sysregs_context_restore(SECURE); + + /* switch NS bit to start using 32-bit, secure mappings */ + write_scr(cm_get_scr_el3(SECURE)); + isb(); + } + + return pa; +} + +/******************************************************************************* + * Given a secure payload entrypoint, register width, cpu id & pointer to a + * context data structure, this function will create a secure context ready for + * programming an entry into the secure payload. + ******************************************************************************/ +void tlkd_init_tlk_ep_state(struct entry_point_info *tlk_entry_point, + uint32_t rw, + uint64_t pc, + tlk_context_t *tlk_ctx) +{ + uint32_t ep_attr, spsr; + + /* Passing a NULL context is a critical programming error */ + assert(tlk_ctx); + assert(tlk_entry_point); + assert(pc); + + /* Associate this context with the cpu specified */ + tlk_ctx->mpidr = read_mpidr_el1(); + clr_std_smc_active_flag(tlk_ctx->state); + cm_set_context(&tlk_ctx->cpu_ctx, SECURE); + + if (rw == SP_AARCH64) + spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + else + spsr = SPSR_MODE32(MODE32_svc, + SPSR_T_ARM, + read_sctlr_el3() & SCTLR_EE_BIT, + DISABLE_ALL_EXCEPTIONS); + + /* initialise an entrypoint to set up the CPU context */ + ep_attr = SECURE | EP_ST_ENABLE; + if (read_sctlr_el3() & SCTLR_EE_BIT) + ep_attr |= EP_EE_BIG; + SET_PARAM_HEAD(tlk_entry_point, PARAM_EP, VERSION_1, ep_attr); + + tlk_entry_point->pc = pc; + tlk_entry_point->spsr = spsr; +} + +/******************************************************************************* + * This function takes a TLK context pointer and: + * 1. Applies the S-EL1 system register context from tlk_ctx->cpu_ctx. + * 2. Saves the current C runtime state (callee saved registers) on the stack + * frame and saves a reference to this state. + * 3. Calls el3_exit() so that the EL3 system and general purpose registers + * from the tlk_ctx->cpu_ctx are used to enter the secure payload image. + ******************************************************************************/ +uint64_t tlkd_synchronous_sp_entry(tlk_context_t *tlk_ctx) +{ + uint64_t rc; + + /* Passing a NULL context is a critical programming error */ + assert(tlk_ctx); + assert(tlk_ctx->c_rt_ctx == 0); + + /* Apply the Secure EL1 system register context and switch to it */ + assert(cm_get_context(SECURE) == &tlk_ctx->cpu_ctx); + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + + rc = tlkd_enter_sp(&tlk_ctx->c_rt_ctx); +#if DEBUG + tlk_ctx->c_rt_ctx = 0; +#endif + + return rc; +} + +/******************************************************************************* + * This function takes a TLK context pointer and: + * 1. Saves the S-EL1 system register context to tlk_ctx->cpu_ctx. + * 2. Restores the current C runtime state (callee saved registers) from the + * stack frame using reference to this state saved in tlkd_enter_sp(). + * 3. It does not need to save any general purpose or EL3 system register state + * as the generic smc entry routine should have saved those. + ******************************************************************************/ +void tlkd_synchronous_sp_exit(tlk_context_t *tlk_ctx, uint64_t ret) +{ + /* Passing a NULL context is a critical programming error */ + assert(tlk_ctx); + + /* Save the Secure EL1 system register context */ + assert(cm_get_context(SECURE) == &tlk_ctx->cpu_ctx); + cm_el1_sysregs_context_save(SECURE); + + assert(tlk_ctx->c_rt_ctx != 0); + tlkd_exit_sp(tlk_ctx->c_rt_ctx, ret); + + /* Should never reach here */ + assert(0); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_helpers.S new file mode 100644 index 0000000..e6fb9ea --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_helpers.S @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "tlkd_private.h" + + .global tlkd_enter_sp + .global tlkd_exit_sp + + /* --------------------------------------------- + * This function is called with SP_EL0 as stack. + * Here we stash our EL3 callee-saved registers + * on to the stack as a part of saving the C + * runtime and enter the secure payload. + * 'x0' contains a pointer to the memory where + * the address of the C runtime context is to be + * saved. + * --------------------------------------------- + */ +func tlkd_enter_sp + /* Make space for the registers that we're going to save */ + mov x3, sp + str x3, [x0, #0] + sub sp, sp, #TLKD_C_RT_CTX_SIZE + + /* Save callee-saved registers on to the stack */ + stp x19, x20, [sp, #TLKD_C_RT_CTX_X19] + stp x21, x22, [sp, #TLKD_C_RT_CTX_X21] + stp x23, x24, [sp, #TLKD_C_RT_CTX_X23] + stp x25, x26, [sp, #TLKD_C_RT_CTX_X25] + stp x27, x28, [sp, #TLKD_C_RT_CTX_X27] + stp x29, x30, [sp, #TLKD_C_RT_CTX_X29] + + /* ---------------------------------------------- + * Everything is setup now. el3_exit() will + * use the secure context to restore to the + * general purpose and EL3 system registers to + * ERET into the secure payload. + * ---------------------------------------------- + */ + b el3_exit +endfunc tlkd_enter_sp + + /* ---------------------------------------------- + * This function is called with 'x0' pointing to + * a C runtime context saved in tlkd_enter_sp(). + * It restores the saved registers and jumps to + * that runtime with 'x0' as the new sp. This + * destroys the C runtime context that had been + * built on the stack below the saved context by + * the caller. Later the second parameter 'x1' + * is passed as return value to the caller + * ---------------------------------------------- + */ +func tlkd_exit_sp + /* Restore the previous stack */ + mov sp, x0 + + /* Restore callee-saved registers on to the stack */ + ldp x19, x20, [x0, #(TLKD_C_RT_CTX_X19 - TLKD_C_RT_CTX_SIZE)] + ldp x21, x22, [x0, #(TLKD_C_RT_CTX_X21 - TLKD_C_RT_CTX_SIZE)] + ldp x23, x24, [x0, #(TLKD_C_RT_CTX_X23 - TLKD_C_RT_CTX_SIZE)] + ldp x25, x26, [x0, #(TLKD_C_RT_CTX_X25 - TLKD_C_RT_CTX_SIZE)] + ldp x27, x28, [x0, #(TLKD_C_RT_CTX_X27 - TLKD_C_RT_CTX_SIZE)] + ldp x29, x30, [x0, #(TLKD_C_RT_CTX_X29 - TLKD_C_RT_CTX_SIZE)] + + /* ------------------------------------------------ + * This should take us back to the instruction + * after the call to the last tlkd_enter_sp(). + * Place the second parameter to x0 so that the + * caller will see it as a return value from the + * original entry call + * ------------------------------------------------ + */ + mov x0, x1 + ret +endfunc tlkd_exit_sp diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_main.c b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_main.c new file mode 100644 index 0000000..f5dd744 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_main.c @@ -0,0 +1,482 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/******************************************************************************* + * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a + * plug-in component to the Secure Monitor, registered as a runtime service. The + * SPD is expected to be a functional extension of the Secure Payload (SP) that + * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting + * the Trusted OS/Applications range to the dispatcher. The SPD will either + * handle the request locally or delegate it to the Secure Payload. It is also + * responsible for initialising and maintaining communication with the SP. + ******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "tlkd_private.h" + +extern const spd_pm_ops_t tlkd_pm_ops; + +/******************************************************************************* + * Per-cpu Secure Payload state + ******************************************************************************/ +tlk_context_t tlk_ctx; + +/* TLK UID: RFC-4122 compliant UUID (version-5, sha-1) */ +DEFINE_SVC_UUID(tlk_uuid, + 0xbd11e9c9, 0x2bba, 0x52ee, 0xb1, 0x72, + 0x46, 0x1f, 0xba, 0x97, 0x7f, 0x63); + +int32_t tlkd_init(void); + +/******************************************************************************* + * Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type + * (aarch32/aarch64) if not already known and initialises the context for entry + * into the SP for its initialisation. + ******************************************************************************/ +int32_t tlkd_setup(void) +{ + entry_point_info_t *tlk_ep_info; + + /* + * Get information about the Secure Payload (BL32) image. Its + * absence is a critical failure. + */ + tlk_ep_info = bl31_plat_get_next_image_ep_info(SECURE); + if (!tlk_ep_info) { + WARN("No SP provided. Booting device without SP" + " initialization. SMC`s destined for SP" + " will return SMC_UNK\n"); + return 1; + } + + /* + * If there's no valid entry point for SP, we return a non-zero value + * signalling failure initializing the service. We bail out without + * registering any handlers + */ + if (!tlk_ep_info->pc) + return 1; + + /* + * Inspect the SP image's SPSR and determine it's execution state + * i.e whether AArch32 or AArch64. + */ + tlkd_init_tlk_ep_state(tlk_ep_info, + (tlk_ep_info->spsr >> MODE_RW_SHIFT) & MODE_RW_MASK, + tlk_ep_info->pc, + &tlk_ctx); + + /* + * All TLK SPD initialization done. Now register our init function + * with BL31 for deferred invocation + */ + bl31_register_bl32_init(&tlkd_init); + + return 0; +} + +/******************************************************************************* + * This function passes control to the Secure Payload image (BL32) for the first + * time on the primary cpu after a cold boot. It assumes that a valid secure + * context has already been created by tlkd_setup() which can be directly + * used. This function performs a synchronous entry into the Secure payload. + * The SP passes control back to this routine through a SMC. + ******************************************************************************/ +int32_t tlkd_init(void) +{ + entry_point_info_t *tlk_entry_point; + + /* + * Get information about the Secure Payload (BL32) image. Its + * absence is a critical failure. + */ + tlk_entry_point = bl31_plat_get_next_image_ep_info(SECURE); + assert(tlk_entry_point); + + cm_init_my_context(tlk_entry_point); + + /* + * Arrange for an entry into the test secure payload. + */ + return tlkd_synchronous_sp_entry(&tlk_ctx); +} + +/******************************************************************************* + * This function is responsible for handling all SMCs in the Trusted OS/App + * range from the non-secure state as defined in the SMC Calling Convention + * Document. It is also responsible for communicating with the Secure payload + * to delegate work and return results back to the non-secure state. Lastly it + * will also return any information that the secure payload needs to do the + * work assigned to it. + ******************************************************************************/ +uint64_t tlkd_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + cpu_context_t *ns_cpu_context; + gp_regs_t *gp_regs; + uint32_t ns; + uint64_t par; + + /* Passing a NULL context is a critical programming error */ + assert(handle); + + /* These SMCs are only supported by CPU0 */ + if ((read_mpidr() & MPIDR_CPU_MASK) != 0) + SMC_RET1(handle, SMC_UNK); + + /* Determine which security state this SMC originated from */ + ns = is_caller_non_secure(flags); + + switch (smc_fid) { + + /* + * This function ID is used by SP to indicate that it was + * preempted by a non-secure world IRQ. + */ + case TLK_PREEMPTED: + + if (ns) + SMC_RET1(handle, SMC_UNK); + + assert(handle == cm_get_context(SECURE)); + cm_el1_sysregs_context_save(SECURE); + + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* + * Restore non-secure state. There is no need to save the + * secure system register context since the SP was supposed + * to preserve it during S-EL1 interrupt handling. + */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + + SMC_RET1(ns_cpu_context, x1); + + /* + * Request from non secure world to resume the preempted + * Standard SMC call. + */ + case TLK_RESUME_FID: + + /* RESUME should be invoked only by normal world */ + if (!ns) + SMC_RET1(handle, SMC_UNK); + + /* + * This is a resume request from the non-secure client. + * save the non-secure state and send the request to + * the secure payload. + */ + assert(handle == cm_get_context(NON_SECURE)); + + /* Check if we are already preempted before resume */ + if (!get_std_smc_active_flag(tlk_ctx.state)) + SMC_RET1(handle, SMC_UNK); + + cm_el1_sysregs_context_save(NON_SECURE); + + /* + * We are done stashing the non-secure context. Ask the + * secure payload to do the work now. + */ + + /* We just need to return to the preempted point in + * SP and the execution will resume as normal. + */ + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + SMC_RET0(handle); + + /* + * This is a request from the non-secure context to: + * + * a. register shared memory with the SP for storing it's + * activity logs. + * b. register shared memory with the SP for passing args + * required for maintaining sessions with the Trusted + * Applications. + * c. open/close sessions + * d. issue commands to the Trusted Apps + */ + case TLK_REGISTER_LOGBUF: + case TLK_REGISTER_REQBUF: + case TLK_OPEN_TA_SESSION: + case TLK_CLOSE_TA_SESSION: + case TLK_TA_LAUNCH_OP: + case TLK_TA_SEND_EVENT: + + if (!ns) + SMC_RET1(handle, SMC_UNK); + + /* + * This is a fresh request from the non-secure client. + * The parameters are in x1 and x2. Figure out which + * registers need to be preserved, save the non-secure + * state and send the request to the secure payload. + */ + assert(handle == cm_get_context(NON_SECURE)); + + /* Check if we are already preempted */ + if (get_std_smc_active_flag(tlk_ctx.state)) + SMC_RET1(handle, SMC_UNK); + + cm_el1_sysregs_context_save(NON_SECURE); + + /* + * Verify if there is a valid context to use. + */ + assert(&tlk_ctx.cpu_ctx == cm_get_context(SECURE)); + + /* + * Mark the SP state as active. + */ + set_std_smc_active_flag(tlk_ctx.state); + + /* + * We are done stashing the non-secure context. Ask the + * secure payload to do the work now. + */ + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + + /* + * TLK is a 32-bit Trusted OS and so expects the SMC + * arguments via r0-r7. TLK expects the monitor frame + * registers to be 64-bits long. Hence, we pass x0 in + * r0-r1, x1 in r2-r3, x3 in r4-r5 and x4 in r6-r7. + * + * As smc_fid is a uint32 value, r1 contains 0. + */ + gp_regs = get_gpregs_ctx(&tlk_ctx.cpu_ctx); + write_ctx_reg(gp_regs, CTX_GPREG_X4, (uint32_t)x2); + write_ctx_reg(gp_regs, CTX_GPREG_X5, (uint32_t)(x2 >> 32)); + write_ctx_reg(gp_regs, CTX_GPREG_X6, (uint32_t)x3); + write_ctx_reg(gp_regs, CTX_GPREG_X7, (uint32_t)(x3 >> 32)); + SMC_RET4(&tlk_ctx.cpu_ctx, smc_fid, 0, (uint32_t)x1, + (uint32_t)(x1 >> 32)); + + /* + * Translate NS/EL1-S virtual addresses. + * + * x1 = virtual address + * x3 = type (NS/S) + * + * Returns PA:lo in r0, PA:hi in r1. + */ + case TLK_VA_TRANSLATE: + + /* Should be invoked only by secure world */ + if (ns) + SMC_RET1(handle, SMC_UNK); + + /* NS virtual addresses are 64-bit long */ + if (x3 & TLK_TRANSLATE_NS_VADDR) + x1 = (uint32_t)x1 | (x2 << 32); + + if (!x1) + SMC_RET1(handle, SMC_UNK); + + /* + * TODO: Sanity check x1. This would require platform + * support. + */ + + /* virtual address and type: ns/s */ + par = tlkd_va_translate(x1, x3); + + /* return physical address in r0-r1 */ + SMC_RET4(handle, (uint32_t)par, (uint32_t)(par >> 32), 0, 0); + + /* + * This is a request from the SP to mark completion of + * a standard function ID. + */ + case TLK_REQUEST_DONE: + if (ns) + SMC_RET1(handle, SMC_UNK); + + /* + * Mark the SP state as inactive. + */ + clr_std_smc_active_flag(tlk_ctx.state); + + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* + * This is a request completion SMC and we must switch to + * the non-secure world to pass the result. + */ + cm_el1_sysregs_context_save(SECURE); + + /* + * We are done stashing the secure context. Switch to the + * non-secure context and return the result. + */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + SMC_RET1(ns_cpu_context, x1); + + /* + * This function ID is used only by the SP to indicate it has + * finished initialising itself after a cold boot + */ + case TLK_ENTRY_DONE: + if (ns) + SMC_RET1(handle, SMC_UNK); + + /* + * SP has been successfully initialized. Register power + * managemnt hooks with PSCI + */ + psci_register_spd_pm_hook(&tlkd_pm_ops); + + /* + * TLK reports completion. The SPD must have initiated + * the original request through a synchronous entry + * into the SP. Jump back to the original C runtime + * context. + */ + tlkd_synchronous_sp_exit(&tlk_ctx, x1); + + /* + * These function IDs are used only by TLK to indicate it has + * finished: + * 1. suspending itself after an earlier psci cpu_suspend + * request. + * 2. resuming itself after an earlier psci cpu_suspend + * request. + * 3. powering down after an earlier psci system_off/system_reset + * request. + */ + case TLK_SUSPEND_DONE: + case TLK_RESUME_DONE: + case TLK_SYSTEM_OFF_DONE: + + if (ns) + SMC_RET1(handle, SMC_UNK); + + /* + * TLK reports completion. TLKD must have initiated the + * original request through a synchronous entry into the SP. + * Jump back to the original C runtime context, and pass x1 as + * return value to the caller + */ + tlkd_synchronous_sp_exit(&tlk_ctx, x1); + + /* + * Return the number of service function IDs implemented to + * provide service to non-secure + */ + case TOS_CALL_COUNT: + SMC_RET1(handle, TLK_NUM_FID); + + /* + * Return TLK's UID to the caller + */ + case TOS_UID: + SMC_UUID_RET(handle, tlk_uuid); + + /* + * Return the version of current implementation + */ + case TOS_CALL_VERSION: + SMC_RET2(handle, TLK_VERSION_MAJOR, TLK_VERSION_MINOR); + + default: + break; + } + + SMC_RET1(handle, SMC_UNK); +} + +/* Define a SPD runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + tlkd_tos_fast, + + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_FAST, + tlkd_setup, + tlkd_smc_handler +); + +/* Define a SPD runtime service descriptor for standard SMC calls */ +DECLARE_RT_SVC( + tlkd_tos_std, + + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_STD, + NULL, + tlkd_smc_handler +); + +/* Define a SPD runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + tlkd_tap_fast, + + OEN_TAP_START, + OEN_TAP_END, + SMC_TYPE_FAST, + NULL, + tlkd_smc_handler +); + +/* Define a SPD runtime service descriptor for standard SMC calls */ +DECLARE_RT_SVC( + tlkd_tap_std, + + OEN_TAP_START, + OEN_TAP_END, + SMC_TYPE_STD, + NULL, + tlkd_smc_handler +); diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_pm.c b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_pm.c new file mode 100644 index 0000000..1eff0aa --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_pm.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "tlkd_private.h" + +extern tlk_context_t tlk_ctx; + +#define MPIDR_CPU0 0x80000000 + +/******************************************************************************* + * Return the type of payload TLKD is dealing with. Report the current + * resident cpu (mpidr format) if it is a UP/UP migratable payload. + ******************************************************************************/ +static int32_t cpu_migrate_info(uint64_t *resident_cpu) +{ + /* the payload runs only on CPU0 */ + *resident_cpu = MPIDR_CPU0; + + /* Uniprocessor, not migrate capable payload */ + return PSCI_TOS_NOT_UP_MIG_CAP; +} + +/******************************************************************************* + * This cpu is being suspended. Inform TLK of the SYSTEM_SUSPEND event, so + * that it can pass this information to its Trusted Apps. + ******************************************************************************/ +static void cpu_suspend_handler(uint64_t suspend_level) +{ + gp_regs_t *gp_regs; + int cpu = read_mpidr() & MPIDR_CPU_MASK; + int32_t rc = 0; + + /* + * TLK runs only on CPU0 and suspends its Trusted Apps during + * SYSTEM_SUSPEND. It has no role to play during CPU_SUSPEND. + */ + if ((cpu != 0) || (suspend_level != PLAT_MAX_PWR_LVL)) + return; + + /* pass system suspend event to TLK */ + gp_regs = get_gpregs_ctx(&tlk_ctx.cpu_ctx); + write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_SUSPEND); + + /* Program the entry point and enter TLK */ + rc = tlkd_synchronous_sp_entry(&tlk_ctx); + + /* + * Read the response from TLK. A non-zero return means that + * something went wrong while communicating with it. + */ + if (rc != 0) + panic(); +} + +/******************************************************************************* + * This cpu is being resumed. Inform TLK of the SYSTEM_SUSPEND exit, so + * that it can pass this information to its Trusted Apps. + ******************************************************************************/ +static void cpu_resume_handler(uint64_t suspend_level) +{ + gp_regs_t *gp_regs; + int cpu = read_mpidr() & MPIDR_CPU_MASK; + int32_t rc = 0; + + /* + * TLK runs only on CPU0 and resumes its Trusted Apps during + * SYSTEM_SUSPEND exit. It has no role to play during CPU_SUSPEND + * exit. + */ + if ((cpu != 0) || (suspend_level != PLAT_MAX_PWR_LVL)) + return; + + /* pass system resume event to TLK */ + gp_regs = get_gpregs_ctx(&tlk_ctx.cpu_ctx); + write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_RESUME); + + /* Program the entry point and enter TLK */ + rc = tlkd_synchronous_sp_entry(&tlk_ctx); + + /* + * Read the response from TLK. A non-zero return means that + * something went wrong while communicating with it. + */ + if (rc != 0) + panic(); +} + +/******************************************************************************* + * System is about to be reset. Inform the SP to allow any book-keeping + ******************************************************************************/ +static void system_off_handler(void) +{ + int cpu = read_mpidr() & MPIDR_CPU_MASK; + gp_regs_t *gp_regs; + + /* TLK runs only on CPU0 */ + if (cpu != 0) + return; + + /* pass system off/reset events to TLK */ + gp_regs = get_gpregs_ctx(&tlk_ctx.cpu_ctx); + write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_OFF); + + /* + * Enter the SP. We do not care about the return value because we + * must continue with the shutdown anyway. + */ + (void)tlkd_synchronous_sp_entry(&tlk_ctx); +} + +/******************************************************************************* + * Structure populated by the Dispatcher to be given a chance to perform any + * bookkeeping before PSCI executes a power mgmt. operation. + ******************************************************************************/ +const spd_pm_ops_t tlkd_pm_ops = { + .svc_migrate_info = cpu_migrate_info, + .svc_suspend = cpu_suspend_handler, + .svc_suspend_finish = cpu_resume_handler, + .svc_system_off = system_off_handler, + .svc_system_reset = system_off_handler +}; diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_private.h b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_private.h new file mode 100644 index 0000000..271c24c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tlkd/tlkd_private.h @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TLKD_PRIVATE_H__ +#define __TLKD_PRIVATE_H__ + +#include +#include +#include +#include +#include + +/* + * This flag is used by the TLKD to determine if the SP is servicing a standard + * SMC request prior to programming the next entry into the SP e.g. if SP + * execution is preempted by a non-secure interrupt and handed control to the + * normal world. If another request which is distinct from what the SP was + * previously doing arrives, then this flag will be help the TLKD to either + * reject the new request or service it while ensuring that the previous context + * is not corrupted. + */ +#define STD_SMC_ACTIVE_FLAG_SHIFT 2 +#define STD_SMC_ACTIVE_FLAG_MASK 1 +#define get_std_smc_active_flag(state) (((state) >> STD_SMC_ACTIVE_FLAG_SHIFT) \ + & STD_SMC_ACTIVE_FLAG_MASK) +#define set_std_smc_active_flag(state) ((state) |= \ + (1 << STD_SMC_ACTIVE_FLAG_SHIFT)) +#define clr_std_smc_active_flag(state) ((state) &= \ + ~(STD_SMC_ACTIVE_FLAG_MASK \ + << STD_SMC_ACTIVE_FLAG_SHIFT)) + +/******************************************************************************* + * Translate virtual address received from the NS world + ******************************************************************************/ +#define TLK_TRANSLATE_NS_VADDR 4 + +/******************************************************************************* + * Secure Payload execution state information i.e. aarch32 or aarch64 + ******************************************************************************/ +#define SP_AARCH32 MODE_RW_32 +#define SP_AARCH64 MODE_RW_64 + +/******************************************************************************* + * Number of cpus that the present on this platform. TODO: Rely on a topology + * tree to determine this in the future to avoid assumptions about mpidr + * allocation + ******************************************************************************/ +#define TLKD_CORE_COUNT PLATFORM_CORE_COUNT + +/******************************************************************************* + * Constants that allow assembler code to preserve callee-saved registers of the + * C runtime context while performing a security state switch. + ******************************************************************************/ +#define TLKD_C_RT_CTX_X19 0x0 +#define TLKD_C_RT_CTX_X20 0x8 +#define TLKD_C_RT_CTX_X21 0x10 +#define TLKD_C_RT_CTX_X22 0x18 +#define TLKD_C_RT_CTX_X23 0x20 +#define TLKD_C_RT_CTX_X24 0x28 +#define TLKD_C_RT_CTX_X25 0x30 +#define TLKD_C_RT_CTX_X26 0x38 +#define TLKD_C_RT_CTX_X27 0x40 +#define TLKD_C_RT_CTX_X28 0x48 +#define TLKD_C_RT_CTX_X29 0x50 +#define TLKD_C_RT_CTX_X30 0x58 +#define TLKD_C_RT_CTX_SIZE 0x60 +#define TLKD_C_RT_CTX_ENTRIES (TLKD_C_RT_CTX_SIZE >> DWORD_SHIFT) + +#ifndef __ASSEMBLY__ + +#include +#include + +/* AArch64 callee saved general purpose register context structure. */ +DEFINE_REG_STRUCT(c_rt_regs, TLKD_C_RT_CTX_ENTRIES); + +/* + * Compile time assertion to ensure that both the compiler and linker + * have the same double word aligned view of the size of the C runtime + * register context. + */ +CASSERT(TLKD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ + assert_tlkd_c_rt_regs_size_mismatch); + +/******************************************************************************* + * Structure which helps the SPD to maintain the per-cpu state of the SP. + * 'state' - collection of flags to track SP state e.g. on/off + * 'mpidr' - mpidr to associate a context with a cpu + * 'c_rt_ctx' - stack address to restore C runtime context from after + * returning from a synchronous entry into the SP. + * 'cpu_ctx' - space to maintain SP architectural state + * 'saved_tsp_args' - space to store arguments for TSP arithmetic operations + * which will queried using the TSP_GET_ARGS SMC by TSP. + ******************************************************************************/ +typedef struct tlk_context { + uint32_t state; + uint64_t mpidr; + uint64_t c_rt_ctx; + cpu_context_t cpu_ctx; +} tlk_context_t; + +/******************************************************************************* + * Function & Data prototypes + ******************************************************************************/ +uint64_t tlkd_va_translate(uintptr_t va, int type); +uint64_t tlkd_enter_sp(uint64_t *c_rt_ctx); +void __dead2 tlkd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); +uint64_t tlkd_synchronous_sp_entry(tlk_context_t *tlk_ctx); +void __dead2 tlkd_synchronous_sp_exit(tlk_context_t *tlk_ctx, + uint64_t ret); +void tlkd_init_tlk_ep_state(struct entry_point_info *tlk_entry_point, + uint32_t rw, + uint64_t pc, + tlk_context_t *tlk_ctx); + +#endif /*__ASSEMBLY__*/ + +#endif /* __TLKD_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd.mk b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd.mk new file mode 100644 index 0000000..139c7d7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd.mk @@ -0,0 +1,61 @@ +# +# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +TSPD_DIR := services/spd/tspd +SPD_INCLUDES := -Iinclude/bl32/tsp + +SPD_SOURCES := services/spd/tspd/tspd_common.c \ + services/spd/tspd/tspd_helpers.S \ + services/spd/tspd/tspd_main.c \ + services/spd/tspd/tspd_pm.c + +# This dispatcher is paired with a Test Secure Payload source and we intend to +# build the Test Secure Payload along with this dispatcher. +# +# In cases where an associated Secure Payload lies outside this build +# system/source tree, the the dispatcher Makefile can either invoke an external +# build command or assume it pre-built + +BL32_ROOT := bl32/tsp + +# Include SP's Makefile. The assumption is that the TSP's build system is +# compatible with that of Trusted Firmware, and it'll add and populate necessary +# build targets and variables +include ${BL32_ROOT}/tsp.mk + +# Let the top-level Makefile know that we intend to build the SP from source +NEED_BL32 := yes + +# Flag used to enable routing of non-secure interrupts to EL3 when they are +# generated while the code is executing in S-EL1/0. +TSPD_ROUTE_IRQ_TO_EL3 := 0 + +$(eval $(call assert_boolean,TSPD_ROUTE_IRQ_TO_EL3)) +$(eval $(call add_define,TSPD_ROUTE_IRQ_TO_EL3)) diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_common.c b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_common.c new file mode 100644 index 0000000..322413c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_common.c @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "tspd_private.h" + +/******************************************************************************* + * Given a secure payload entrypoint info pointer, entry point PC, register + * width, cpu id & pointer to a context data structure, this function will + * initialize tsp context and entry point info for the secure payload + ******************************************************************************/ +void tspd_init_tsp_ep_state(struct entry_point_info *tsp_entry_point, + uint32_t rw, + uint64_t pc, + tsp_context_t *tsp_ctx) +{ + uint32_t ep_attr; + + /* Passing a NULL context is a critical programming error */ + assert(tsp_ctx); + assert(tsp_entry_point); + assert(pc); + + /* + * We support AArch64 TSP for now. + * TODO: Add support for AArch32 TSP + */ + assert(rw == TSP_AARCH64); + + /* Associate this context with the cpu specified */ + tsp_ctx->mpidr = read_mpidr_el1(); + tsp_ctx->state = 0; + set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); + clr_std_smc_active_flag(tsp_ctx->state); + + cm_set_context(&tsp_ctx->cpu_ctx, SECURE); + + /* initialise an entrypoint to set up the CPU context */ + ep_attr = SECURE | EP_ST_ENABLE; + if (read_sctlr_el3() & SCTLR_EE_BIT) + ep_attr |= EP_EE_BIG; + SET_PARAM_HEAD(tsp_entry_point, PARAM_EP, VERSION_1, ep_attr); + + tsp_entry_point->pc = pc; + tsp_entry_point->spsr = SPSR_64(MODE_EL1, + MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + memset(&tsp_entry_point->args, 0, sizeof(tsp_entry_point->args)); +} + +/******************************************************************************* + * This function takes an SP context pointer and: + * 1. Applies the S-EL1 system register context from tsp_ctx->cpu_ctx. + * 2. Saves the current C runtime state (callee saved registers) on the stack + * frame and saves a reference to this state. + * 3. Calls el3_exit() so that the EL3 system and general purpose registers + * from the tsp_ctx->cpu_ctx are used to enter the secure payload image. + ******************************************************************************/ +uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx) +{ + uint64_t rc; + + assert(tsp_ctx != NULL); + assert(tsp_ctx->c_rt_ctx == 0); + + /* Apply the Secure EL1 system register context and switch to it */ + assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + + rc = tspd_enter_sp(&tsp_ctx->c_rt_ctx); +#if DEBUG + tsp_ctx->c_rt_ctx = 0; +#endif + + return rc; +} + + +/******************************************************************************* + * This function takes an SP context pointer and: + * 1. Saves the S-EL1 system register context tp tsp_ctx->cpu_ctx. + * 2. Restores the current C runtime state (callee saved registers) from the + * stack frame using the reference to this state saved in tspd_enter_sp(). + * 3. It does not need to save any general purpose or EL3 system register state + * as the generic smc entry routine should have saved those. + ******************************************************************************/ +void tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret) +{ + assert(tsp_ctx != NULL); + /* Save the Secure EL1 system register context */ + assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); + cm_el1_sysregs_context_save(SECURE); + + assert(tsp_ctx->c_rt_ctx != 0); + tspd_exit_sp(tsp_ctx->c_rt_ctx, ret); + + /* Should never reach here */ + assert(0); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_helpers.S new file mode 100644 index 0000000..515e824 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_helpers.S @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "tspd_private.h" + + .global tspd_enter_sp + /* --------------------------------------------- + * This function is called with SP_EL0 as stack. + * Here we stash our EL3 callee-saved registers + * on to the stack as a part of saving the C + * runtime and enter the secure payload. + * 'x0' contains a pointer to the memory where + * the address of the C runtime context is to be + * saved. + * --------------------------------------------- + */ +func tspd_enter_sp + /* Make space for the registers that we're going to save */ + mov x3, sp + str x3, [x0, #0] + sub sp, sp, #TSPD_C_RT_CTX_SIZE + + /* Save callee-saved registers on to the stack */ + stp x19, x20, [sp, #TSPD_C_RT_CTX_X19] + stp x21, x22, [sp, #TSPD_C_RT_CTX_X21] + stp x23, x24, [sp, #TSPD_C_RT_CTX_X23] + stp x25, x26, [sp, #TSPD_C_RT_CTX_X25] + stp x27, x28, [sp, #TSPD_C_RT_CTX_X27] + stp x29, x30, [sp, #TSPD_C_RT_CTX_X29] + + /* --------------------------------------------- + * Everything is setup now. el3_exit() will + * use the secure context to restore to the + * general purpose and EL3 system registers to + * ERET into the secure payload. + * --------------------------------------------- + */ + b el3_exit +endfunc tspd_enter_sp + + /* --------------------------------------------- + * This function is called 'x0' pointing to a C + * runtime context saved in tspd_enter_sp(). It + * restores the saved registers and jumps to + * that runtime with 'x0' as the new sp. This + * destroys the C runtime context that had been + * built on the stack below the saved context by + * the caller. Later the second parameter 'x1' + * is passed as return value to the caller + * --------------------------------------------- + */ + .global tspd_exit_sp +func tspd_exit_sp + /* Restore the previous stack */ + mov sp, x0 + + /* Restore callee-saved registers on to the stack */ + ldp x19, x20, [x0, #(TSPD_C_RT_CTX_X19 - TSPD_C_RT_CTX_SIZE)] + ldp x21, x22, [x0, #(TSPD_C_RT_CTX_X21 - TSPD_C_RT_CTX_SIZE)] + ldp x23, x24, [x0, #(TSPD_C_RT_CTX_X23 - TSPD_C_RT_CTX_SIZE)] + ldp x25, x26, [x0, #(TSPD_C_RT_CTX_X25 - TSPD_C_RT_CTX_SIZE)] + ldp x27, x28, [x0, #(TSPD_C_RT_CTX_X27 - TSPD_C_RT_CTX_SIZE)] + ldp x29, x30, [x0, #(TSPD_C_RT_CTX_X29 - TSPD_C_RT_CTX_SIZE)] + + /* --------------------------------------------- + * This should take us back to the instruction + * after the call to the last tspd_enter_sp(). + * Place the second parameter to x0 so that the + * caller will see it as a return value from the + * original entry call + * --------------------------------------------- + */ + mov x0, x1 + ret +endfunc tspd_exit_sp diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_main.c b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_main.c new file mode 100644 index 0000000..b8b67fa --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_main.c @@ -0,0 +1,719 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +/******************************************************************************* + * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a + * plug-in component to the Secure Monitor, registered as a runtime service. The + * SPD is expected to be a functional extension of the Secure Payload (SP) that + * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting + * the Trusted OS/Applications range to the dispatcher. The SPD will either + * handle the request locally or delegate it to the Secure Payload. It is also + * responsible for initialising and maintaining communication with the SP. + ******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "tspd_private.h" + +/******************************************************************************* + * Address of the entrypoint vector table in the Secure Payload. It is + * initialised once on the primary core after a cold boot. + ******************************************************************************/ +tsp_vectors_t *tsp_vectors; + +/******************************************************************************* + * Array to keep track of per-cpu Secure Payload state + ******************************************************************************/ +tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; + + +/* TSP UID */ +DEFINE_SVC_UUID(tsp_uuid, + 0x5b3056a0, 0x3291, 0x427b, 0x98, 0x11, + 0x71, 0x68, 0xca, 0x50, 0xf3, 0xfa); + +int32_t tspd_init(void); + +uint64_t tspd_handle_sp_preemption(void *handle) +{ + cpu_context_t *ns_cpu_context; + assert(handle == cm_get_context(SECURE)); + cm_el1_sysregs_context_save(SECURE); + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* + * Restore non-secure state. The secure system + * register context will be saved when required. + */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + + SMC_RET1(ns_cpu_context, SMC_PREEMPTED); +} +/******************************************************************************* + * This function is the handler registered for S-EL1 interrupts by the TSPD. It + * validates the interrupt and upon success arranges entry into the TSP at + * 'tsp_fiq_entry()' for handling the interrupt. + ******************************************************************************/ +static uint64_t tspd_sel1_interrupt_handler(uint32_t id, + uint32_t flags, + void *handle, + void *cookie) +{ + uint32_t linear_id; + tsp_context_t *tsp_ctx; + + /* Check the security state when the exception was generated */ + assert(get_interrupt_src_ss(flags) == NON_SECURE); + +#if IMF_READ_INTERRUPT_ID + /* Check the security status of the interrupt */ + assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_S_EL1); +#endif + + /* Sanity check the pointer to this cpu's context */ + assert(handle == cm_get_context(NON_SECURE)); + + /* Save the non-secure context before entering the TSP */ + cm_el1_sysregs_context_save(NON_SECURE); + + /* Get a reference to this cpu's TSP context */ + linear_id = plat_my_core_pos(); + tsp_ctx = &tspd_sp_context[linear_id]; + assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); + + /* + * Determine if the TSP was previously preempted. Its last known + * context has to be preserved in this case. + * The TSP should return control to the TSPD after handling this + * FIQ. Preserve essential EL3 context to allow entry into the + * TSP at the FIQ entry point using the 'cpu_context' structure. + * There is no need to save the secure system register context + * since the TSP is supposed to preserve it during S-EL1 interrupt + * handling. + */ + if (get_std_smc_active_flag(tsp_ctx->state)) { + tsp_ctx->saved_spsr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, + CTX_SPSR_EL3); + tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, + CTX_ELR_EL3); +#if TSPD_ROUTE_IRQ_TO_EL3 + /*Need to save the previously interrupted secure context */ + memcpy(&tsp_ctx->sp_ctx, &tsp_ctx->cpu_ctx, TSPD_SP_CTX_SIZE); +#endif + } + + cm_el1_sysregs_context_restore(SECURE); + cm_set_elr_spsr_el3(SECURE, (uint64_t) &tsp_vectors->fiq_entry, + SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)); + + cm_set_next_eret_context(SECURE); + + /* + * Tell the TSP that it has to handle an FIQ synchronously. Also the + * instruction in normal world where the interrupt was generated is + * passed for debugging purposes. It is safe to retrieve this address + * from ELR_EL3 as the secure context will not take effect until + * el3_exit(). + */ + SMC_RET2(&tsp_ctx->cpu_ctx, TSP_HANDLE_FIQ_AND_RETURN, read_elr_el3()); +} + +#if TSPD_ROUTE_IRQ_TO_EL3 +/******************************************************************************* + * This function is the handler registered for S-EL1 interrupts by the TSPD. It + * validates the interrupt and upon success arranges entry into the TSP at + * 'tsp_fiq_entry()' for handling the interrupt. + ******************************************************************************/ +static uint64_t tspd_ns_interrupt_handler(uint32_t id, + uint32_t flags, + void *handle, + void *cookie) +{ + /* Check the security state when the exception was generated */ + assert(get_interrupt_src_ss(flags) == SECURE); + +#if IMF_READ_INTERRUPT_ID + /* Check the security status of the interrupt */ + assert(plat_ic_get_interrupt_type(id) == INTR_TYPE_NS); +#endif + /* + * Disable the routing of NS interrupts from secure world to EL3 while + * interrupted on this core. + */ + disable_intr_rm_local(INTR_TYPE_NS, SECURE); + + return tspd_handle_sp_preemption(handle); +} +#endif + +/******************************************************************************* + * Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type + * (aarch32/aarch64) if not already known and initialises the context for entry + * into the SP for its initialisation. + ******************************************************************************/ +int32_t tspd_setup(void) +{ + entry_point_info_t *tsp_ep_info; + uint32_t linear_id; + + linear_id = plat_my_core_pos(); + + /* + * Get information about the Secure Payload (BL32) image. Its + * absence is a critical failure. TODO: Add support to + * conditionally include the SPD service + */ + tsp_ep_info = bl31_plat_get_next_image_ep_info(SECURE); + if (!tsp_ep_info) { + WARN("No TSP provided by BL2 boot loader, Booting device" + " without TSP initialization. SMC`s destined for TSP" + " will return SMC_UNK\n"); + return 1; + } + + /* + * If there's no valid entry point for SP, we return a non-zero value + * signalling failure initializing the service. We bail out without + * registering any handlers + */ + if (!tsp_ep_info->pc) + return 1; + + /* + * We could inspect the SP image and determine it's execution + * state i.e whether AArch32 or AArch64. Assuming it's AArch64 + * for the time being. + */ + tspd_init_tsp_ep_state(tsp_ep_info, + TSP_AARCH64, + tsp_ep_info->pc, + &tspd_sp_context[linear_id]); + +#if TSP_INIT_ASYNC + bl31_set_next_image_type(SECURE); +#else + /* + * All TSPD initialization done. Now register our init function with + * BL31 for deferred invocation + */ + bl31_register_bl32_init(&tspd_init); +#endif + return 0; +} + +/******************************************************************************* + * This function passes control to the Secure Payload image (BL32) for the first + * time on the primary cpu after a cold boot. It assumes that a valid secure + * context has already been created by tspd_setup() which can be directly used. + * It also assumes that a valid non-secure context has been initialised by PSCI + * so it does not need to save and restore any non-secure state. This function + * performs a synchronous entry into the Secure payload. The SP passes control + * back to this routine through a SMC. + ******************************************************************************/ +int32_t tspd_init(void) +{ + uint32_t linear_id = plat_my_core_pos(); + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + entry_point_info_t *tsp_entry_point; + uint64_t rc; + + /* + * Get information about the Secure Payload (BL32) image. Its + * absence is a critical failure. + */ + tsp_entry_point = bl31_plat_get_next_image_ep_info(SECURE); + assert(tsp_entry_point); + + cm_init_my_context(tsp_entry_point); + + /* + * Arrange for an entry into the test secure payload. It will be + * returned via TSP_ENTRY_DONE case + */ + rc = tspd_synchronous_sp_entry(tsp_ctx); + assert(rc != 0); + + return rc; +} + + +/******************************************************************************* + * This function is responsible for handling all SMCs in the Trusted OS/App + * range from the non-secure state as defined in the SMC Calling Convention + * Document. It is also responsible for communicating with the Secure payload + * to delegate work and return results back to the non-secure state. Lastly it + * will also return any information that the secure payload needs to do the + * work assigned to it. + ******************************************************************************/ +uint64_t tspd_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + cpu_context_t *ns_cpu_context; + uint32_t linear_id = plat_my_core_pos(), ns; + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + uint64_t rc; +#if TSP_INIT_ASYNC + entry_point_info_t *next_image_info; +#endif + + /* Determine which security state this SMC originated from */ + ns = is_caller_non_secure(flags); + + switch (smc_fid) { + + /* + * This function ID is used by TSP to indicate that it was + * preempted by a normal world IRQ. + * + */ + case TSP_PREEMPTED: + if (ns) + SMC_RET1(handle, SMC_UNK); + + return tspd_handle_sp_preemption(handle); + + /* + * This function ID is used only by the TSP to indicate that it has + * finished handling a S-EL1 FIQ interrupt. Execution should resume + * in the normal world. + */ + case TSP_HANDLED_S_EL1_FIQ: + if (ns) + SMC_RET1(handle, SMC_UNK); + + assert(handle == cm_get_context(SECURE)); + + /* + * Restore the relevant EL3 state which saved to service + * this SMC. + */ + if (get_std_smc_active_flag(tsp_ctx->state)) { + SMC_SET_EL3(&tsp_ctx->cpu_ctx, + CTX_SPSR_EL3, + tsp_ctx->saved_spsr_el3); + SMC_SET_EL3(&tsp_ctx->cpu_ctx, + CTX_ELR_EL3, + tsp_ctx->saved_elr_el3); +#if TSPD_ROUTE_IRQ_TO_EL3 + /* + * Need to restore the previously interrupted + * secure context. + */ + memcpy(&tsp_ctx->cpu_ctx, &tsp_ctx->sp_ctx, + TSPD_SP_CTX_SIZE); +#endif + } + + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* + * Restore non-secure state. There is no need to save the + * secure system register context since the TSP was supposed + * to preserve it during S-EL1 interrupt handling. + */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + + SMC_RET0((uint64_t) ns_cpu_context); + + + /* + * This function ID is used only by the TSP to indicate that it was + * interrupted due to a EL3 FIQ interrupt. Execution should resume + * in the normal world. + */ + case TSP_EL3_FIQ: + if (ns) + SMC_RET1(handle, SMC_UNK); + + assert(handle == cm_get_context(SECURE)); + + /* Assert that standard SMC execution has been preempted */ + assert(get_std_smc_active_flag(tsp_ctx->state)); + + /* Save the secure system register state */ + cm_el1_sysregs_context_save(SECURE); + + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* Restore non-secure state */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + + SMC_RET1(ns_cpu_context, TSP_EL3_FIQ); + + + /* + * This function ID is used only by the SP to indicate it has + * finished initialising itself after a cold boot + */ + case TSP_ENTRY_DONE: + if (ns) + SMC_RET1(handle, SMC_UNK); + + /* + * Stash the SP entry points information. This is done + * only once on the primary cpu + */ + assert(tsp_vectors == NULL); + tsp_vectors = (tsp_vectors_t *) x1; + + if (tsp_vectors) { + set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); + + /* + * TSP has been successfully initialized. Register power + * managemnt hooks with PSCI + */ + psci_register_spd_pm_hook(&tspd_pm); + + /* + * Register an interrupt handler for S-EL1 interrupts + * when generated during code executing in the + * non-secure state. + */ + flags = 0; + set_interrupt_rm_flag(flags, NON_SECURE); + rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, + tspd_sel1_interrupt_handler, + flags); + if (rc) + panic(); + +#if TSPD_ROUTE_IRQ_TO_EL3 + /* + * Register an interrupt handler for NS interrupts when + * generated during code executing in secure state are + * routed to EL3. + */ + flags = 0; + set_interrupt_rm_flag(flags, SECURE); + + rc = register_interrupt_type_handler(INTR_TYPE_NS, + tspd_ns_interrupt_handler, + flags); + if (rc) + panic(); + + /* + * Disable the interrupt NS locally since it will be enabled globally + * within cm_init_my_context. + */ + disable_intr_rm_local(INTR_TYPE_NS, SECURE); +#endif + } + + +#if TSP_INIT_ASYNC + /* Save the Secure EL1 system register context */ + assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); + cm_el1_sysregs_context_save(SECURE); + + /* Program EL3 registers to enable entry into the next EL */ + next_image_info = bl31_plat_get_next_image_ep_info(NON_SECURE); + assert(next_image_info); + assert(NON_SECURE == + GET_SECURITY_STATE(next_image_info->h.attr)); + + cm_init_my_context(next_image_info); + cm_prepare_el3_exit(NON_SECURE); + SMC_RET0(cm_get_context(NON_SECURE)); +#else + /* + * SP reports completion. The SPD must have initiated + * the original request through a synchronous entry + * into the SP. Jump back to the original C runtime + * context. + */ + tspd_synchronous_sp_exit(tsp_ctx, x1); +#endif + + /* + * These function IDs is used only by the SP to indicate it has + * finished: + * 1. turning itself on in response to an earlier psci + * cpu_on request + * 2. resuming itself after an earlier psci cpu_suspend + * request. + */ + case TSP_ON_DONE: + case TSP_RESUME_DONE: + + /* + * These function IDs is used only by the SP to indicate it has + * finished: + * 1. suspending itself after an earlier psci cpu_suspend + * request. + * 2. turning itself off in response to an earlier psci + * cpu_off request. + */ + case TSP_OFF_DONE: + case TSP_SUSPEND_DONE: + case TSP_SYSTEM_OFF_DONE: + case TSP_SYSTEM_RESET_DONE: + if (ns) + SMC_RET1(handle, SMC_UNK); + + /* + * SP reports completion. The SPD must have initiated the + * original request through a synchronous entry into the SP. + * Jump back to the original C runtime context, and pass x1 as + * return value to the caller + */ + tspd_synchronous_sp_exit(tsp_ctx, x1); + + /* + * Request from non-secure client to perform an + * arithmetic operation or response from secure + * payload to an earlier request. + */ + case TSP_FAST_FID(TSP_ADD): + case TSP_FAST_FID(TSP_SUB): + case TSP_FAST_FID(TSP_MUL): + case TSP_FAST_FID(TSP_DIV): + + case TSP_STD_FID(TSP_ADD): + case TSP_STD_FID(TSP_SUB): + case TSP_STD_FID(TSP_MUL): + case TSP_STD_FID(TSP_DIV): + if (ns) { + /* + * This is a fresh request from the non-secure client. + * The parameters are in x1 and x2. Figure out which + * registers need to be preserved, save the non-secure + * state and send the request to the secure payload. + */ + assert(handle == cm_get_context(NON_SECURE)); + + /* Check if we are already preempted */ + if (get_std_smc_active_flag(tsp_ctx->state)) + SMC_RET1(handle, SMC_UNK); + + cm_el1_sysregs_context_save(NON_SECURE); + + /* Save x1 and x2 for use by TSP_GET_ARGS call below */ + store_tsp_args(tsp_ctx, x1, x2); + + /* + * We are done stashing the non-secure context. Ask the + * secure payload to do the work now. + */ + + /* + * Verify if there is a valid context to use, copy the + * operation type and parameters to the secure context + * and jump to the fast smc entry point in the secure + * payload. Entry into S-EL1 will take place upon exit + * from this function. + */ + assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); + + /* Set appropriate entry for SMC. + * We expect the TSP to manage the PSTATE.I and PSTATE.F + * flags as appropriate. + */ + if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) { + cm_set_elr_el3(SECURE, (uint64_t) + &tsp_vectors->fast_smc_entry); + } else { + set_std_smc_active_flag(tsp_ctx->state); + cm_set_elr_el3(SECURE, (uint64_t) + &tsp_vectors->std_smc_entry); +#if TSPD_ROUTE_IRQ_TO_EL3 + /* + * Enable the routing of NS interrupts to EL3 + * during STD SMC processing on this core. + */ + enable_intr_rm_local(INTR_TYPE_NS, SECURE); +#endif + } + + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + SMC_RET3(&tsp_ctx->cpu_ctx, smc_fid, x1, x2); + } else { + /* + * This is the result from the secure client of an + * earlier request. The results are in x1-x3. Copy it + * into the non-secure context, save the secure state + * and return to the non-secure state. + */ + assert(handle == cm_get_context(SECURE)); + cm_el1_sysregs_context_save(SECURE); + + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* Restore non-secure state */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_STD) { + clr_std_smc_active_flag(tsp_ctx->state); +#if TSPD_ROUTE_IRQ_TO_EL3 + /* + * Disable the routing of NS interrupts to EL3 + * after STD SMC processing is finished on this + * core. + */ + disable_intr_rm_local(INTR_TYPE_NS, SECURE); +#endif + } + + SMC_RET3(ns_cpu_context, x1, x2, x3); + } + + break; + + /* + * Request from non secure world to resume the preempted + * Standard SMC call. + */ + case TSP_FID_RESUME: + /* RESUME should be invoked only by normal world */ + if (!ns) { + assert(0); + break; + } + + /* + * This is a resume request from the non-secure client. + * save the non-secure state and send the request to + * the secure payload. + */ + assert(handle == cm_get_context(NON_SECURE)); + + /* Check if we are already preempted before resume */ + if (!get_std_smc_active_flag(tsp_ctx->state)) + SMC_RET1(handle, SMC_UNK); + + cm_el1_sysregs_context_save(NON_SECURE); + + /* + * We are done stashing the non-secure context. Ask the + * secure payload to do the work now. + */ +#if TSPD_ROUTE_IRQ_TO_EL3 + /* + * Enable the routing of NS interrupts to EL3 during resumption + * of STD SMC call on this core. + */ + enable_intr_rm_local(INTR_TYPE_NS, SECURE); +#endif + + + + /* We just need to return to the preempted point in + * TSP and the execution will resume as normal. + */ + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + SMC_RET0(&tsp_ctx->cpu_ctx); + + /* + * This is a request from the secure payload for more arguments + * for an ongoing arithmetic operation requested by the + * non-secure world. Simply return the arguments from the non- + * secure client in the original call. + */ + case TSP_GET_ARGS: + if (ns) + SMC_RET1(handle, SMC_UNK); + + get_tsp_args(tsp_ctx, x1, x2); + SMC_RET2(handle, x1, x2); + + case TOS_CALL_COUNT: + /* + * Return the number of service function IDs implemented to + * provide service to non-secure + */ + SMC_RET1(handle, TSP_NUM_FID); + + case TOS_UID: + /* Return TSP UID to the caller */ + SMC_UUID_RET(handle, tsp_uuid); + + case TOS_CALL_VERSION: + /* Return the version of current implementation */ + SMC_RET2(handle, TSP_VERSION_MAJOR, TSP_VERSION_MINOR); + + default: + break; + } + + SMC_RET1(handle, SMC_UNK); +} + +/* Define a SPD runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + tspd_fast, + + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_FAST, + tspd_setup, + tspd_smc_handler +); + +/* Define a SPD runtime service descriptor for standard SMC calls */ +DECLARE_RT_SVC( + tspd_std, + + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_STD, + NULL, + tspd_smc_handler +); diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_pm.c b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_pm.c new file mode 100644 index 0000000..5089420 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_pm.c @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "tspd_private.h" + +/******************************************************************************* + * The target cpu is being turned on. Allow the TSPD/TSP to perform any actions + * needed. Nothing at the moment. + ******************************************************************************/ +static void tspd_cpu_on_handler(uint64_t target_cpu) +{ +} + +/******************************************************************************* + * This cpu is being turned off. Allow the TSPD/TSP to perform any actions + * needed + ******************************************************************************/ +static int32_t tspd_cpu_off_handler(uint64_t unused) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + + assert(tsp_vectors); + assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); + + /* Program the entry point and enter the TSP */ + cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry); + rc = tspd_synchronous_sp_entry(tsp_ctx); + + /* + * Read the response from the TSP. A non-zero return means that + * something went wrong while communicating with the TSP. + */ + if (rc != 0) + panic(); + + /* + * Reset TSP's context for a fresh start when this cpu is turned on + * subsequently. + */ + set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); + + return 0; +} + +/******************************************************************************* + * This cpu is being suspended. S-EL1 state must have been saved in the + * resident cpu (mpidr format) if it is a UP/UP migratable TSP. + ******************************************************************************/ +static void tspd_cpu_suspend_handler(uint64_t max_off_pwrlvl) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + + assert(tsp_vectors); + assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); + + /* Program the entry point and enter the TSP */ + cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry); + rc = tspd_synchronous_sp_entry(tsp_ctx); + + /* + * Read the response from the TSP. A non-zero return means that + * something went wrong while communicating with the TSP. + */ + if (rc != 0) + panic(); + + /* Update its context to reflect the state the TSP is in */ + set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_SUSPEND); +} + +/******************************************************************************* + * This cpu has been turned on. Enter the TSP to initialise S-EL1 and other bits + * before passing control back to the Secure Monitor. Entry in S-El1 is done + * after initialising minimal architectural state that guarantees safe + * execution. + ******************************************************************************/ +static void tspd_cpu_on_finish_handler(uint64_t unused) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + entry_point_info_t tsp_on_entrypoint; + + assert(tsp_vectors); + assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF); + + tspd_init_tsp_ep_state(&tsp_on_entrypoint, + TSP_AARCH64, + (uint64_t) &tsp_vectors->cpu_on_entry, + tsp_ctx); + + /* Initialise this cpu's secure context */ + cm_init_my_context(&tsp_on_entrypoint); + +#if TSPD_ROUTE_IRQ_TO_EL3 + /* + * Disable the NS interrupt locally since it will be enabled globally + * within cm_init_my_context. + */ + disable_intr_rm_local(INTR_TYPE_NS, SECURE); +#endif + + /* Enter the TSP */ + rc = tspd_synchronous_sp_entry(tsp_ctx); + + /* + * Read the response from the TSP. A non-zero return means that + * something went wrong while communicating with the SP. + */ + if (rc != 0) + panic(); + + /* Update its context to reflect the state the SP is in */ + set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); +} + +/******************************************************************************* + * This cpu has resumed from suspend. The SPD saved the TSP context when it + * completed the preceding suspend call. Use that context to program an entry + * into the TSP to allow it to do any remaining book keeping + ******************************************************************************/ +static void tspd_cpu_suspend_finish_handler(uint64_t max_off_pwrlvl) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + + assert(tsp_vectors); + assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND); + + /* Program the entry point, max_off_pwrlvl and enter the SP */ + write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx), + CTX_GPREG_X0, + max_off_pwrlvl); + cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry); + rc = tspd_synchronous_sp_entry(tsp_ctx); + + /* + * Read the response from the TSP. A non-zero return means that + * something went wrong while communicating with the TSP. + */ + if (rc != 0) + panic(); + + /* Update its context to reflect the state the SP is in */ + set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); +} + +/******************************************************************************* + * Return the type of TSP the TSPD is dealing with. Report the current resident + * cpu (mpidr format) if it is a UP/UP migratable TSP. + ******************************************************************************/ +static int32_t tspd_cpu_migrate_info(uint64_t *resident_cpu) +{ + return TSP_MIGRATE_INFO; +} + +/******************************************************************************* + * System is about to be switched off. Allow the TSPD/TSP to perform + * any actions needed. + ******************************************************************************/ +static void tspd_system_off(void) +{ + uint32_t linear_id = plat_my_core_pos(); + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + + assert(tsp_vectors); + assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); + + /* Program the entry point */ + cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry); + + /* Enter the TSP. We do not care about the return value because we + * must continue the shutdown anyway */ + tspd_synchronous_sp_entry(tsp_ctx); +} + +/******************************************************************************* + * System is about to be reset. Allow the TSPD/TSP to perform + * any actions needed. + ******************************************************************************/ +static void tspd_system_reset(void) +{ + uint32_t linear_id = plat_my_core_pos(); + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + + assert(tsp_vectors); + assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); + + /* Program the entry point */ + cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_reset_entry); + + /* Enter the TSP. We do not care about the return value because we + * must continue the reset anyway */ + tspd_synchronous_sp_entry(tsp_ctx); +} + +/******************************************************************************* + * Structure populated by the TSP Dispatcher to be given a chance to perform any + * TSP bookkeeping before PSCI executes a power mgmt. operation. + ******************************************************************************/ +const spd_pm_ops_t tspd_pm = { + .svc_on = tspd_cpu_on_handler, + .svc_off = tspd_cpu_off_handler, + .svc_suspend = tspd_cpu_suspend_handler, + .svc_on_finish = tspd_cpu_on_finish_handler, + .svc_suspend_finish = tspd_cpu_suspend_finish_handler, + .svc_migrate = NULL, + .svc_migrate_info = tspd_cpu_migrate_info, + .svc_system_off = tspd_system_off, + .svc_system_reset = tspd_system_reset +}; diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_private.h b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_private.h new file mode 100644 index 0000000..5f6fb2b --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/spd/tspd/tspd_private.h @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TSPD_PRIVATE_H__ +#define __TSPD_PRIVATE_H__ + +#include +#include +#include +#include +#include + +/******************************************************************************* + * Secure Payload PM state information e.g. SP is suspended, uninitialised etc + * and macros to access the state information in the per-cpu 'state' flags + ******************************************************************************/ +#define TSP_PSTATE_OFF 0 +#define TSP_PSTATE_ON 1 +#define TSP_PSTATE_SUSPEND 2 +#define TSP_PSTATE_SHIFT 0 +#define TSP_PSTATE_MASK 0x3 +#define get_tsp_pstate(state) ((state >> TSP_PSTATE_SHIFT) & TSP_PSTATE_MASK) +#define clr_tsp_pstate(state) (state &= ~(TSP_PSTATE_MASK \ + << TSP_PSTATE_SHIFT)) +#define set_tsp_pstate(st, pst) do { \ + clr_tsp_pstate(st); \ + st |= (pst & TSP_PSTATE_MASK) << \ + TSP_PSTATE_SHIFT; \ + } while (0); + + +/* + * This flag is used by the TSPD to determine if the TSP is servicing a standard + * SMC request prior to programming the next entry into the TSP e.g. if TSP + * execution is preempted by a non-secure interrupt and handed control to the + * normal world. If another request which is distinct from what the TSP was + * previously doing arrives, then this flag will be help the TSPD to either + * reject the new request or service it while ensuring that the previous context + * is not corrupted. + */ +#define STD_SMC_ACTIVE_FLAG_SHIFT 2 +#define STD_SMC_ACTIVE_FLAG_MASK 1 +#define get_std_smc_active_flag(state) ((state >> STD_SMC_ACTIVE_FLAG_SHIFT) \ + & STD_SMC_ACTIVE_FLAG_MASK) +#define set_std_smc_active_flag(state) (state |= \ + 1 << STD_SMC_ACTIVE_FLAG_SHIFT) +#define clr_std_smc_active_flag(state) (state &= \ + ~(STD_SMC_ACTIVE_FLAG_MASK \ + << STD_SMC_ACTIVE_FLAG_SHIFT)) + +/******************************************************************************* + * Secure Payload execution state information i.e. aarch32 or aarch64 + ******************************************************************************/ +#define TSP_AARCH32 MODE_RW_32 +#define TSP_AARCH64 MODE_RW_64 + +/******************************************************************************* + * The SPD should know the type of Secure Payload. + ******************************************************************************/ +#define TSP_TYPE_UP PSCI_TOS_NOT_UP_MIG_CAP +#define TSP_TYPE_UPM PSCI_TOS_UP_MIG_CAP +#define TSP_TYPE_MP PSCI_TOS_NOT_PRESENT_MP + +/******************************************************************************* + * Secure Payload migrate type information as known to the SPD. We assume that + * the SPD is dealing with an MP Secure Payload. + ******************************************************************************/ +#define TSP_MIGRATE_INFO TSP_TYPE_MP + +/******************************************************************************* + * Number of cpus that the present on this platform. TODO: Rely on a topology + * tree to determine this in the future to avoid assumptions about mpidr + * allocation + ******************************************************************************/ +#define TSPD_CORE_COUNT PLATFORM_CORE_COUNT + +/******************************************************************************* + * Constants that allow assembler code to preserve callee-saved registers of the + * C runtime context while performing a security state switch. + ******************************************************************************/ +#define TSPD_C_RT_CTX_X19 0x0 +#define TSPD_C_RT_CTX_X20 0x8 +#define TSPD_C_RT_CTX_X21 0x10 +#define TSPD_C_RT_CTX_X22 0x18 +#define TSPD_C_RT_CTX_X23 0x20 +#define TSPD_C_RT_CTX_X24 0x28 +#define TSPD_C_RT_CTX_X25 0x30 +#define TSPD_C_RT_CTX_X26 0x38 +#define TSPD_C_RT_CTX_X27 0x40 +#define TSPD_C_RT_CTX_X28 0x48 +#define TSPD_C_RT_CTX_X29 0x50 +#define TSPD_C_RT_CTX_X30 0x58 +#define TSPD_C_RT_CTX_SIZE 0x60 +#define TSPD_C_RT_CTX_ENTRIES (TSPD_C_RT_CTX_SIZE >> DWORD_SHIFT) + +/******************************************************************************* + * Constants that allow assembler code to preserve caller-saved registers of the + * SP context while performing a TSP preemption. + * Note: These offsets have to match with the offsets for the corresponding + * registers in cpu_context as we are using memcpy to copy the values from + * cpu_context to sp_ctx. + ******************************************************************************/ +#define TSPD_SP_CTX_X0 0x0 +#define TSPD_SP_CTX_X1 0x8 +#define TSPD_SP_CTX_X2 0x10 +#define TSPD_SP_CTX_X3 0x18 +#define TSPD_SP_CTX_X4 0x20 +#define TSPD_SP_CTX_X5 0x28 +#define TSPD_SP_CTX_X6 0x30 +#define TSPD_SP_CTX_X7 0x38 +#define TSPD_SP_CTX_X8 0x40 +#define TSPD_SP_CTX_X9 0x48 +#define TSPD_SP_CTX_X10 0x50 +#define TSPD_SP_CTX_X11 0x58 +#define TSPD_SP_CTX_X12 0x60 +#define TSPD_SP_CTX_X13 0x68 +#define TSPD_SP_CTX_X14 0x70 +#define TSPD_SP_CTX_X15 0x78 +#define TSPD_SP_CTX_X16 0x80 +#define TSPD_SP_CTX_X17 0x88 +#define TSPD_SP_CTX_SIZE 0x90 +#define TSPD_SP_CTX_ENTRIES (TSPD_SP_CTX_SIZE >> DWORD_SHIFT) + +#ifndef __ASSEMBLY__ + +#include +#include + +/* + * The number of arguments to save during a SMC call for TSP. + * Currently only x1 and x2 are used by TSP. + */ +#define TSP_NUM_ARGS 0x2 + +/* AArch64 callee saved general purpose register context structure. */ +DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES); + +/* + * Compile time assertion to ensure that both the compiler and linker + * have the same double word aligned view of the size of the C runtime + * register context. + */ +CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ + assert_spd_c_rt_regs_size_mismatch); + +/* SEL1 Secure payload (SP) caller saved register context structure. */ +DEFINE_REG_STRUCT(sp_ctx_regs, TSPD_SP_CTX_ENTRIES); + +/* + * Compile time assertion to ensure that both the compiler and linker + * have the same double word aligned view of the size of the C runtime + * register context. + */ +CASSERT(TSPD_SP_CTX_SIZE == sizeof(sp_ctx_regs_t), \ + assert_spd_sp_regs_size_mismatch); + +/******************************************************************************* + * Structure which helps the SPD to maintain the per-cpu state of the SP. + * 'saved_spsr_el3' - temporary copy to allow FIQ handling when the TSP has been + * preempted. + * 'saved_elr_el3' - temporary copy to allow FIQ handling when the TSP has been + * preempted. + * 'state' - collection of flags to track SP state e.g. on/off + * 'mpidr' - mpidr to associate a context with a cpu + * 'c_rt_ctx' - stack address to restore C runtime context from after + * returning from a synchronous entry into the SP. + * 'cpu_ctx' - space to maintain SP architectural state + * 'saved_tsp_args' - space to store arguments for TSP arithmetic operations + * which will queried using the TSP_GET_ARGS SMC by TSP. + * 'sp_ctx' - space to save the SEL1 Secure Payload(SP) caller saved + * register context after it has been preempted by an EL3 + * routed NS interrupt and when a Secure Interrupt is taken + * to SP. + ******************************************************************************/ +typedef struct tsp_context { + uint64_t saved_elr_el3; + uint32_t saved_spsr_el3; + uint32_t state; + uint64_t mpidr; + uint64_t c_rt_ctx; + cpu_context_t cpu_ctx; + uint64_t saved_tsp_args[TSP_NUM_ARGS]; +#if TSPD_ROUTE_IRQ_TO_EL3 + sp_ctx_regs_t sp_ctx; +#endif +} tsp_context_t; + +/* Helper macros to store and retrieve tsp args from tsp_context */ +#define store_tsp_args(tsp_ctx, x1, x2) do {\ + tsp_ctx->saved_tsp_args[0] = x1;\ + tsp_ctx->saved_tsp_args[1] = x2;\ + } while (0) + +#define get_tsp_args(tsp_ctx, x1, x2) do {\ + x1 = tsp_ctx->saved_tsp_args[0];\ + x2 = tsp_ctx->saved_tsp_args[1];\ + } while (0) + +/* TSPD power management handlers */ +extern const spd_pm_ops_t tspd_pm; + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct tsp_vectors; + +/******************************************************************************* + * Function & Data prototypes + ******************************************************************************/ +uint64_t tspd_enter_sp(uint64_t *c_rt_ctx); +void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); +uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx); +void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret); +void tspd_init_tsp_ep_state(struct entry_point_info *tsp_ep, + uint32_t rw, + uint64_t pc, + tsp_context_t *tsp_ctx); + +extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; +extern struct tsp_vectors *tsp_vectors; +#endif /*__ASSEMBLY__*/ + +#endif /* __TSPD_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_common.c b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_common.c new file mode 100644 index 0000000..7332695 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_common.c @@ -0,0 +1,907 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "psci_private.h" + +/* + * SPD power management operations, expected to be supplied by the registered + * SPD on successful SP initialization + */ +const spd_pm_ops_t *psci_spd_pm; + +/* + * PSCI requested local power state map. This array is used to store the local + * power states requested by a CPU for power levels from level 1 to + * PLAT_MAX_PWR_LVL. It does not store the requested local power state for power + * level 0 (PSCI_CPU_PWR_LVL) as the requested and the target power state for a + * CPU are the same. + * + * During state coordination, the platform is passed an array containing the + * local states requested for a particular non cpu power domain by each cpu + * within the domain. + * + * TODO: Dense packing of the requested states will cause cache thrashing + * when multiple power domains write to it. If we allocate the requested + * states at each power level in a cache-line aligned per-domain memory, + * the cache thrashing can be avoided. + */ +static plat_local_state_t + psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT]; + + +/******************************************************************************* + * Arrays that hold the platform's power domain tree information for state + * management of power domains. + * Each node in the array 'psci_non_cpu_pd_nodes' corresponds to a power domain + * which is an ancestor of a CPU power domain. + * Each node in the array 'psci_cpu_pd_nodes' corresponds to a cpu power domain + ******************************************************************************/ +non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS] +#if USE_COHERENT_MEM +__attribute__ ((section("tzfw_coherent_mem"))) +#endif +; + +DEFINE_BAKERY_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); + +cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; + +/******************************************************************************* + * Pointer to functions exported by the platform to complete power mgmt. ops + ******************************************************************************/ +const plat_psci_ops_t *psci_plat_pm_ops; + +/****************************************************************************** + * Check that the maximum power level supported by the platform makes sense + *****************************************************************************/ +CASSERT(PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL && \ + PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL, \ + assert_platform_max_pwrlvl_check); + +/* + * The plat_local_state used by the platform is one of these types: RUN, + * RETENTION and OFF. The platform can define further sub-states for each type + * apart from RUN. This categorization is done to verify the sanity of the + * psci_power_state passed by the platform and to print debug information. The + * categorization is done on the basis of the following conditions: + * + * 1. If (plat_local_state == 0) then the category is STATE_TYPE_RUN. + * + * 2. If (0 < plat_local_state <= PLAT_MAX_RET_STATE), then the category is + * STATE_TYPE_RETN. + * + * 3. If (plat_local_state > PLAT_MAX_RET_STATE), then the category is + * STATE_TYPE_OFF. + */ +typedef enum plat_local_state_type { + STATE_TYPE_RUN = 0, + STATE_TYPE_RETN, + STATE_TYPE_OFF +} plat_local_state_type_t; + +/* The macro used to categorize plat_local_state. */ +#define find_local_state_type(plat_local_state) \ + ((plat_local_state) ? ((plat_local_state > PLAT_MAX_RET_STATE) \ + ? STATE_TYPE_OFF : STATE_TYPE_RETN) \ + : STATE_TYPE_RUN) + +/****************************************************************************** + * Check that the maximum retention level supported by the platform is less + * than the maximum off level. + *****************************************************************************/ +CASSERT(PLAT_MAX_RET_STATE < PLAT_MAX_OFF_STATE, \ + assert_platform_max_off_and_retn_state_check); + +/****************************************************************************** + * This function ensures that the power state parameter in a CPU_SUSPEND request + * is valid. If so, it returns the requested states for each power level. + *****************************************************************************/ +int psci_validate_power_state(unsigned int power_state, + psci_power_state_t *state_info) +{ + /* Check SBZ bits in power state are zero */ + if (psci_check_power_state(power_state)) + return PSCI_E_INVALID_PARAMS; + + assert(psci_plat_pm_ops->validate_power_state); + + /* Validate the power_state using platform pm_ops */ + return psci_plat_pm_ops->validate_power_state(power_state, state_info); +} + +/****************************************************************************** + * This function retrieves the `psci_power_state_t` for system suspend from + * the platform. + *****************************************************************************/ +void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info) +{ + /* + * Assert that the required pm_ops hook is implemented to ensure that + * the capability detected during psci_setup() is valid. + */ + assert(psci_plat_pm_ops->get_sys_suspend_power_state); + + /* + * Query the platform for the power_state required for system suspend + */ + psci_plat_pm_ops->get_sys_suspend_power_state(state_info); +} + +/******************************************************************************* + * This function verifies that the all the other cores in the system have been + * turned OFF and the current CPU is the last running CPU in the system. + * Returns 1 (true) if the current CPU is the last ON CPU or 0 (false) + * otherwise. + ******************************************************************************/ +unsigned int psci_is_last_on_cpu(void) +{ + unsigned int cpu_idx, my_idx = plat_my_core_pos(); + + for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) { + if (cpu_idx == my_idx) { + assert(psci_get_aff_info_state() == AFF_STATE_ON); + continue; + } + + if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF) + return 0; + } + + return 1; +} + +/******************************************************************************* + * Routine to return the maximum power level to traverse to after a cpu has + * been physically powered up. It is expected to be called immediately after + * reset from assembler code. + ******************************************************************************/ +static unsigned int get_power_on_target_pwrlvl(void) +{ + unsigned int pwrlvl; + + /* + * Assume that this cpu was suspended and retrieve its target power + * level. If it is invalid then it could only have been turned off + * earlier. PLAT_MAX_PWR_LVL will be the highest power level a + * cpu can be turned off to. + */ + pwrlvl = psci_get_suspend_pwrlvl(); + if (pwrlvl == PSCI_INVALID_PWR_LVL) + pwrlvl = PLAT_MAX_PWR_LVL; + return pwrlvl; +} + +/****************************************************************************** + * Helper function to update the requested local power state array. This array + * does not store the requested state for the CPU power level. Hence an + * assertion is added to prevent us from accessing the wrong index. + *****************************************************************************/ +static void psci_set_req_local_pwr_state(unsigned int pwrlvl, + unsigned int cpu_idx, + plat_local_state_t req_pwr_state) +{ + assert(pwrlvl > PSCI_CPU_PWR_LVL); + psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state; +} + +/****************************************************************************** + * This function initializes the psci_req_local_pwr_states. + *****************************************************************************/ +void psci_init_req_local_pwr_states(void) +{ + /* Initialize the requested state of all non CPU power domains as OFF */ + memset(&psci_req_local_pwr_states, PLAT_MAX_OFF_STATE, + sizeof(psci_req_local_pwr_states)); +} + +/****************************************************************************** + * Helper function to return a reference to an array containing the local power + * states requested by each cpu for a power domain at 'pwrlvl'. The size of the + * array will be the number of cpu power domains of which this power domain is + * an ancestor. These requested states will be used to determine a suitable + * target state for this power domain during psci state coordination. An + * assertion is added to prevent us from accessing the CPU power level. + *****************************************************************************/ +static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl, + unsigned int cpu_idx) +{ + assert(pwrlvl > PSCI_CPU_PWR_LVL); + + return &psci_req_local_pwr_states[pwrlvl - 1][cpu_idx]; +} + +/****************************************************************************** + * Helper function to return the current local power state of each power domain + * from the current cpu power domain to its ancestor at the 'end_pwrlvl'. This + * function will be called after a cpu is powered on to find the local state + * each power domain has emerged from. + *****************************************************************************/ +static void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, + psci_power_state_t *target_state) +{ + unsigned int parent_idx, lvl; + plat_local_state_t *pd_state = target_state->pwr_domain_state; + + pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state(); + parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node; + + /* Copy the local power state from node to state_info */ + for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { +#if !USE_COHERENT_MEM + /* + * If using normal memory for psci_non_cpu_pd_nodes, we need + * to flush before reading the local power state as another + * cpu in the same power domain could have updated it and this + * code runs before caches are enabled. + */ + flush_dcache_range( + (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], + sizeof(psci_non_cpu_pd_nodes[parent_idx])); +#endif + pd_state[lvl] = psci_non_cpu_pd_nodes[parent_idx].local_state; + parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; + } + + /* Set the the higher levels to RUN */ + for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) + target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; +} + +/****************************************************************************** + * Helper function to set the target local power state that each power domain + * from the current cpu power domain to its ancestor at the 'end_pwrlvl' will + * enter. This function will be called after coordination of requested power + * states has been done for each power level. + *****************************************************************************/ +static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl, + const psci_power_state_t *target_state) +{ + unsigned int parent_idx, lvl; + const plat_local_state_t *pd_state = target_state->pwr_domain_state; + + psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]); + + /* + * Need to flush as local_state will be accessed with Data Cache + * disabled during power on + */ + flush_cpu_data(psci_svc_cpu_data.local_state); + + parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node; + + /* Copy the local_state from state_info */ + for (lvl = 1; lvl <= end_pwrlvl; lvl++) { + psci_non_cpu_pd_nodes[parent_idx].local_state = pd_state[lvl]; +#if !USE_COHERENT_MEM + flush_dcache_range( + (uintptr_t)&psci_non_cpu_pd_nodes[parent_idx], + sizeof(psci_non_cpu_pd_nodes[parent_idx])); +#endif + parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; + } +} + + +/******************************************************************************* + * PSCI helper function to get the parent nodes corresponding to a cpu_index. + ******************************************************************************/ +void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, + unsigned int end_lvl, + unsigned int node_index[]) +{ + unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node; + int i; + + for (i = PSCI_CPU_PWR_LVL + 1; i <= end_lvl; i++) { + *node_index++ = parent_node; + parent_node = psci_non_cpu_pd_nodes[parent_node].parent_node; + } +} + +/****************************************************************************** + * This function is invoked post CPU power up and initialization. It sets the + * affinity info state, target power state and requested power state for the + * current CPU and all its ancestor power domains to RUN. + *****************************************************************************/ +void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl) +{ + unsigned int parent_idx, cpu_idx = plat_my_core_pos(), lvl; + parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; + + /* Reset the local_state to RUN for the non cpu power domains. */ + for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { + psci_non_cpu_pd_nodes[parent_idx].local_state = + PSCI_LOCAL_STATE_RUN; +#if !USE_COHERENT_MEM + flush_dcache_range( + (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], + sizeof(psci_non_cpu_pd_nodes[parent_idx])); +#endif + psci_set_req_local_pwr_state(lvl, + cpu_idx, + PSCI_LOCAL_STATE_RUN); + parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; + } + + /* Set the affinity info state to ON */ + psci_set_aff_info_state(AFF_STATE_ON); + + psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); + flush_cpu_data(psci_svc_cpu_data); +} + +/****************************************************************************** + * This function is passed the local power states requested for each power + * domain (state_info) between the current CPU domain and its ancestors until + * the target power level (end_pwrlvl). It updates the array of requested power + * states with this information. + * + * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it + * retrieves the states requested by all the cpus of which the power domain at + * that level is an ancestor. It passes this information to the platform to + * coordinate and return the target power state. If the target state for a level + * is RUN then subsequent levels are not considered. At the CPU level, state + * coordination is not required. Hence, the requested and the target states are + * the same. + * + * The 'state_info' is updated with the target state for each level between the + * CPU and the 'end_pwrlvl' and returned to the caller. + * + * This function will only be invoked with data cache enabled and while + * powering down a core. + *****************************************************************************/ +void psci_do_state_coordination(unsigned int end_pwrlvl, + psci_power_state_t *state_info) +{ + unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos(); + unsigned int start_idx, ncpus; + plat_local_state_t target_state, *req_states; + + parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; + + /* For level 0, the requested state will be equivalent + to target state */ + for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { + + /* First update the requested power state */ + psci_set_req_local_pwr_state(lvl, cpu_idx, + state_info->pwr_domain_state[lvl]); + + /* Get the requested power states for this power level */ + start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx; + req_states = psci_get_req_local_pwr_states(lvl, start_idx); + + /* + * Let the platform coordinate amongst the requested states at + * this power level and return the target local power state. + */ + ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus; + target_state = plat_get_target_pwr_state(lvl, + req_states, + ncpus); + + state_info->pwr_domain_state[lvl] = target_state; + + /* Break early if the negotiated target power state is RUN */ + if (is_local_state_run(state_info->pwr_domain_state[lvl])) + break; + + parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; + } + + /* + * This is for cases when we break out of the above loop early because + * the target power state is RUN at a power level < end_pwlvl. + * We update the requested power state from state_info and then + * set the target state as RUN. + */ + for (lvl = lvl + 1; lvl <= end_pwrlvl; lvl++) { + psci_set_req_local_pwr_state(lvl, cpu_idx, + state_info->pwr_domain_state[lvl]); + state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; + + } + + /* Update the target state in the power domain nodes */ + psci_set_target_local_pwr_states(end_pwrlvl, state_info); +} + +/****************************************************************************** + * This function validates a suspend request by making sure that if a standby + * state is requested then no power level is turned off and the highest power + * level is placed in a standby/retention state. + * + * It also ensures that the state level X will enter is not shallower than the + * state level X + 1 will enter. + * + * This validation will be enabled only for DEBUG builds as the platform is + * expected to perform these validations as well. + *****************************************************************************/ +int psci_validate_suspend_req(const psci_power_state_t *state_info, + unsigned int is_power_down_state) +{ + unsigned int max_off_lvl, target_lvl, max_retn_lvl; + plat_local_state_t state; + plat_local_state_type_t req_state_type, deepest_state_type; + int i; + + /* Find the target suspend power level */ + target_lvl = psci_find_target_suspend_lvl(state_info); + if (target_lvl == PSCI_INVALID_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + /* All power domain levels are in a RUN state to begin with */ + deepest_state_type = STATE_TYPE_RUN; + + for (i = target_lvl; i >= PSCI_CPU_PWR_LVL; i--) { + state = state_info->pwr_domain_state[i]; + req_state_type = find_local_state_type(state); + + /* + * While traversing from the highest power level to the lowest, + * the state requested for lower levels has to be the same or + * deeper i.e. equal to or greater than the state at the higher + * levels. If this condition is true, then the requested state + * becomes the deepest state encountered so far. + */ + if (req_state_type < deepest_state_type) + return PSCI_E_INVALID_PARAMS; + deepest_state_type = req_state_type; + } + + /* Find the highest off power level */ + max_off_lvl = psci_find_max_off_lvl(state_info); + + /* The target_lvl is either equal to the max_off_lvl or max_retn_lvl */ + max_retn_lvl = PSCI_INVALID_PWR_LVL; + if (target_lvl != max_off_lvl) + max_retn_lvl = target_lvl; + + /* + * If this is not a request for a power down state then max off level + * has to be invalid and max retention level has to be a valid power + * level. + */ + if (!is_power_down_state && (max_off_lvl != PSCI_INVALID_PWR_LVL || + max_retn_lvl == PSCI_INVALID_PWR_LVL)) + return PSCI_E_INVALID_PARAMS; + + return PSCI_E_SUCCESS; +} + +/****************************************************************************** + * This function finds the highest power level which will be powered down + * amongst all the power levels specified in the 'state_info' structure + *****************************************************************************/ +unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info) +{ + int i; + + for (i = PLAT_MAX_PWR_LVL; i >= PSCI_CPU_PWR_LVL; i--) { + if (is_local_state_off(state_info->pwr_domain_state[i])) + return i; + } + + return PSCI_INVALID_PWR_LVL; +} + +/****************************************************************************** + * This functions finds the level of the highest power domain which will be + * placed in a low power state during a suspend operation. + *****************************************************************************/ +unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info) +{ + int i; + + for (i = PLAT_MAX_PWR_LVL; i >= PSCI_CPU_PWR_LVL; i--) { + if (!is_local_state_run(state_info->pwr_domain_state[i])) + return i; + } + + return PSCI_INVALID_PWR_LVL; +} + +/******************************************************************************* + * This function is passed a cpu_index and the highest level in the topology + * tree that the operation should be applied to. It picks up locks in order of + * increasing power domain level in the range specified. + ******************************************************************************/ +void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, + unsigned int cpu_idx) +{ + unsigned int parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; + unsigned int level; + + /* No locking required for level 0. Hence start locking from level 1 */ + for (level = PSCI_CPU_PWR_LVL + 1; level <= end_pwrlvl; level++) { + psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]); + parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; + } +} + +/******************************************************************************* + * This function is passed a cpu_index and the highest level in the topology + * tree that the operation should be applied to. It releases the locks in order + * of decreasing power domain level in the range specified. + ******************************************************************************/ +void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, + unsigned int cpu_idx) +{ + unsigned int parent_idx, parent_nodes[PLAT_MAX_PWR_LVL] = {0}; + int level; + + /* Get the parent nodes */ + psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes); + + /* Unlock top down. No unlocking required for level 0. */ + for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1; level--) { + parent_idx = parent_nodes[level - 1]; + psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]); + } +} + +/******************************************************************************* + * Simple routine to determine whether a mpidr is valid or not. + ******************************************************************************/ +int psci_validate_mpidr(u_register_t mpidr) +{ + if (plat_core_pos_by_mpidr(mpidr) < 0) + return PSCI_E_INVALID_PARAMS; + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * This function determines the full entrypoint information for the requested + * PSCI entrypoint on power on/resume and returns it. + ******************************************************************************/ +static int psci_get_ns_ep_info(entry_point_info_t *ep, + uintptr_t entrypoint, + u_register_t context_id) +{ + unsigned long ep_attr, sctlr; + unsigned int daif, ee, mode; + unsigned long ns_scr_el3 = read_scr_el3(); + unsigned long ns_sctlr_el1 = read_sctlr_el1(); + + sctlr = ns_scr_el3 & SCR_HCE_BIT ? read_sctlr_el2() : ns_sctlr_el1; + ee = 0; + + ep_attr = NON_SECURE | EP_ST_DISABLE; + if (sctlr & SCTLR_EE_BIT) { + ep_attr |= EP_EE_BIG; + ee = 1; + } + SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); + + ep->pc = entrypoint; + memset(&ep->args, 0, sizeof(ep->args)); + ep->args.arg0 = context_id; + + /* + * Figure out whether the cpu enters the non-secure address space + * in aarch32 or aarch64 + */ + if (ns_scr_el3 & SCR_RW_BIT) { + + /* + * Check whether a Thumb entry point has been provided for an + * aarch64 EL + */ + if (entrypoint & 0x1) + return PSCI_E_INVALID_ADDRESS; + + mode = ns_scr_el3 & SCR_HCE_BIT ? MODE_EL2 : MODE_EL1; + + ep->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + } else { + + mode = ns_scr_el3 & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; + + /* + * TODO: Choose async. exception bits if HYP mode is not + * implemented according to the values of SCR.{AW, FW} bits + */ + daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT; + + ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif); + } + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * This function validates the entrypoint with the platform layer if the + * appropriate pm_ops hook is exported by the platform and returns the + * 'entry_point_info'. + ******************************************************************************/ +int psci_validate_entry_point(entry_point_info_t *ep, + uintptr_t entrypoint, + u_register_t context_id) +{ + int rc; + + /* Validate the entrypoint using platform psci_ops */ + if (psci_plat_pm_ops->validate_ns_entrypoint) { + rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint); + if (rc != PSCI_E_SUCCESS) + return PSCI_E_INVALID_ADDRESS; + } + + /* + * Verify and derive the re-entry information for + * the non-secure world from the non-secure state from + * where this call originated. + */ + rc = psci_get_ns_ep_info(ep, entrypoint, context_id); + return rc; +} + +/******************************************************************************* + * Generic handler which is called when a cpu is physically powered on. It + * traverses the node information and finds the highest power level powered + * off and performs generic, architectural, platform setup and state management + * to power on that power level and power levels below it. + * e.g. For a cpu that's been powered on, it will call the platform specific + * code to enable the gic cpu interface and for a cluster it will enable + * coherency at the interconnect level in addition to gic cpu interface. + ******************************************************************************/ +void psci_power_up_finish(void) +{ + unsigned int end_pwrlvl, cpu_idx = plat_my_core_pos(); + psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; + + /* + * Verify that we have been explicitly turned ON or resumed from + * suspend. + */ + if (psci_get_aff_info_state() == AFF_STATE_OFF) { + ERROR("Unexpected affinity info state"); + panic(); + } + + /* + * Get the maximum power domain level to traverse to after this cpu + * has been physically powered up. + */ + end_pwrlvl = get_power_on_target_pwrlvl(); + + /* + * This function acquires the lock corresponding to each power level so + * that by the time all locks are taken, the system topology is snapshot + * and state management can be done safely. + */ + psci_acquire_pwr_domain_locks(end_pwrlvl, + cpu_idx); + + psci_get_target_local_pwr_states(end_pwrlvl, &state_info); + + /* + * This CPU could be resuming from suspend or it could have just been + * turned on. To distinguish between these 2 cases, we examine the + * affinity state of the CPU: + * - If the affinity state is ON_PENDING then it has just been + * turned on. + * - Else it is resuming from suspend. + * + * Depending on the type of warm reset identified, choose the right set + * of power management handler and perform the generic, architecture + * and platform specific handling. + */ + if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING) + psci_cpu_on_finish(cpu_idx, &state_info); + else + psci_cpu_suspend_finish(cpu_idx, &state_info); + + /* + * Set the requested and target state of this CPU and all the higher + * power domains which are ancestors of this CPU to run. + */ + psci_set_pwr_domains_to_run(end_pwrlvl); + + /* + * This loop releases the lock corresponding to each power level + * in the reverse order to which they were acquired. + */ + psci_release_pwr_domain_locks(end_pwrlvl, + cpu_idx); +} + +/******************************************************************************* + * This function initializes the set of hooks that PSCI invokes as part of power + * management operation. The power management hooks are expected to be provided + * by the SPD, after it finishes all its initialization + ******************************************************************************/ +void psci_register_spd_pm_hook(const spd_pm_ops_t *pm) +{ + assert(pm); + psci_spd_pm = pm; + + if (pm->svc_migrate) + psci_caps |= define_psci_cap(PSCI_MIG_AARCH64); + + if (pm->svc_migrate_info) + psci_caps |= define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) + | define_psci_cap(PSCI_MIG_INFO_TYPE); +} + +/******************************************************************************* + * This function invokes the migrate info hook in the spd_pm_ops. It performs + * the necessary return value validation. If the Secure Payload is UP and + * migrate capable, it returns the mpidr of the CPU on which the Secure payload + * is resident through the mpidr parameter. Else the value of the parameter on + * return is undefined. + ******************************************************************************/ +int psci_spd_migrate_info(u_register_t *mpidr) +{ + int rc; + + if (!psci_spd_pm || !psci_spd_pm->svc_migrate_info) + return PSCI_E_NOT_SUPPORTED; + + rc = psci_spd_pm->svc_migrate_info(mpidr); + + assert(rc == PSCI_TOS_UP_MIG_CAP || rc == PSCI_TOS_NOT_UP_MIG_CAP \ + || rc == PSCI_TOS_NOT_PRESENT_MP || rc == PSCI_E_NOT_SUPPORTED); + + return rc; +} + + +/******************************************************************************* + * This function prints the state of all power domains present in the + * system + ******************************************************************************/ +void psci_print_power_domain_map(void) +{ +#if LOG_LEVEL >= LOG_LEVEL_INFO + unsigned int idx; + plat_local_state_t state; + plat_local_state_type_t state_type; + + /* This array maps to the PSCI_STATE_X definitions in psci.h */ + static const char *psci_state_type_str[] = { + "ON", + "RETENTION", + "OFF", + }; + + INFO("PSCI Power Domain Map:\n"); + for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - PLATFORM_CORE_COUNT); + idx++) { + state_type = find_local_state_type( + psci_non_cpu_pd_nodes[idx].local_state); + INFO(" Domain Node : Level %u, parent_node %d," + " State %s (0x%x)\n", + psci_non_cpu_pd_nodes[idx].level, + psci_non_cpu_pd_nodes[idx].parent_node, + psci_state_type_str[state_type], + psci_non_cpu_pd_nodes[idx].local_state); + } + + for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) { + state = psci_get_cpu_local_state_by_idx(idx); + state_type = find_local_state_type(state); + INFO(" CPU Node : MPID 0x%lx, parent_node %d," + " State %s (0x%x)\n", + psci_cpu_pd_nodes[idx].mpidr, + psci_cpu_pd_nodes[idx].parent_node, + psci_state_type_str[state_type], + psci_get_cpu_local_state_by_idx(idx)); + } +#endif +} + +#if ENABLE_PLAT_COMPAT +/******************************************************************************* + * PSCI Compatibility helper function to return the 'power_state' parameter of + * the PSCI CPU SUSPEND request for the current CPU. Returns PSCI_INVALID_DATA + * if not invoked within CPU_SUSPEND for the current CPU. + ******************************************************************************/ +int psci_get_suspend_powerstate(void) +{ + /* Sanity check to verify that CPU is within CPU_SUSPEND */ + if (psci_get_aff_info_state() == AFF_STATE_ON && + !is_local_state_run(psci_get_cpu_local_state())) + return psci_power_state_compat[plat_my_core_pos()]; + + return PSCI_INVALID_DATA; +} + +/******************************************************************************* + * PSCI Compatibility helper function to return the state id of the current + * cpu encoded in the 'power_state' parameter. Returns PSCI_INVALID_DATA + * if not invoked within CPU_SUSPEND for the current CPU. + ******************************************************************************/ +int psci_get_suspend_stateid(void) +{ + unsigned int power_state; + power_state = psci_get_suspend_powerstate(); + if (power_state != PSCI_INVALID_DATA) + return psci_get_pstate_id(power_state); + + return PSCI_INVALID_DATA; +} + +/******************************************************************************* + * PSCI Compatibility helper function to return the state id encoded in the + * 'power_state' parameter of the CPU specified by 'mpidr'. Returns + * PSCI_INVALID_DATA if the CPU is not in CPU_SUSPEND. + ******************************************************************************/ +int psci_get_suspend_stateid_by_mpidr(unsigned long mpidr) +{ + int cpu_idx = plat_core_pos_by_mpidr(mpidr); + + if (cpu_idx == -1) + return PSCI_INVALID_DATA; + + /* Sanity check to verify that the CPU is in CPU_SUSPEND */ + if (psci_get_aff_info_state_by_idx(cpu_idx) == AFF_STATE_ON && + !is_local_state_run(psci_get_cpu_local_state_by_idx(cpu_idx))) + return psci_get_pstate_id(psci_power_state_compat[cpu_idx]); + + return PSCI_INVALID_DATA; +} + +/******************************************************************************* + * This function returns highest affinity level which is in OFF + * state. The affinity instance with which the level is associated is + * determined by the caller. + ******************************************************************************/ +unsigned int psci_get_max_phys_off_afflvl(void) +{ + psci_power_state_t state_info; + + memset(&state_info, 0, sizeof(state_info)); + psci_get_target_local_pwr_states(PLAT_MAX_PWR_LVL, &state_info); + + return psci_find_target_suspend_lvl(&state_info); +} + +/******************************************************************************* + * PSCI Compatibility helper function to return target affinity level requested + * for the CPU_SUSPEND. This function assumes affinity levels correspond to + * power domain levels on the platform. + ******************************************************************************/ +int psci_get_suspend_afflvl(void) +{ + return psci_get_suspend_pwrlvl(); +} + +#endif diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_entry.S b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_entry.S new file mode 100644 index 0000000..73c3377 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_entry.S @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + + .globl psci_entrypoint + .globl psci_power_down_wfi + + /* -------------------------------------------------------------------- + * This CPU has been physically powered up. It is either resuming from + * suspend or has simply been turned on. In both cases, call the power + * on finisher. + * -------------------------------------------------------------------- + */ +func psci_entrypoint + /* + * On the warm boot path, most of the EL3 initialisations performed by + * 'el3_entrypoint_common' must be skipped: + * + * - Only when the platform bypasses the BL1/BL3-1 entrypoint by + * programming the reset address do we need to set the CPU endianness. + * In other cases, we assume this has been taken care by the + * entrypoint code. + * + * - No need to determine the type of boot, we know it is a warm boot. + * + * - Do not try to distinguish between primary and secondary CPUs, this + * notion only exists for a cold boot. + * + * - No need to initialise the memory or the C runtime environment, + * it has been done once and for all on the cold boot path. + */ + el3_entrypoint_common \ + _set_endian=PROGRAMMABLE_RESET_ADDRESS \ + _warm_boot_mailbox=0 \ + _secondary_cold_boot=0 \ + _init_memory=0 \ + _init_c_runtime=0 \ + _exception_vectors=runtime_exceptions + + /* -------------------------------------------- + * Enable the MMU with the DCache disabled. It + * is safe to use stacks allocated in normal + * memory as a result. All memory accesses are + * marked nGnRnE when the MMU is disabled. So + * all the stack writes will make it to memory. + * All memory accesses are marked Non-cacheable + * when the MMU is enabled but D$ is disabled. + * So used stack memory is guaranteed to be + * visible immediately after the MMU is enabled + * Enabling the DCache at the same time as the + * MMU can lead to speculatively fetched and + * possibly stale stack memory being read from + * other caches. This can lead to coherency + * issues. + * -------------------------------------------- + */ + mov x0, #DISABLE_DCACHE + bl bl31_plat_enable_mmu + + bl psci_power_up_finish + + b el3_exit +endfunc psci_entrypoint + + /* -------------------------------------------- + * This function is called to indicate to the + * power controller that it is safe to power + * down this cpu. It should not exit the wfi + * and will be released from reset upon power + * up. 'wfi_spill' is used to catch erroneous + * exits from wfi. + * -------------------------------------------- + */ +func psci_power_down_wfi + dsb sy // ensure write buffer empty + wfi +wfi_spill: + b wfi_spill +endfunc psci_power_down_wfi + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_helpers.S b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_helpers.S new file mode 100644 index 0000000..6ccf943 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_helpers.S @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + .globl psci_do_pwrdown_cache_maintenance + .globl psci_do_pwrup_cache_maintenance + +/* ----------------------------------------------------------------------- + * void psci_do_pwrdown_cache_maintenance(unsigned int power level); + * + * This function performs cache maintenance for the specified power + * level. The levels of cache affected are determined by the power + * level which is passed as the argument i.e. level 0 results + * in a flush of the L1 cache. Both the L1 and L2 caches are flushed + * for a higher power level. + * + * Additionally, this function also ensures that stack memory is correctly + * flushed out to avoid coherency issues due to a change in its memory + * attributes after the data cache is disabled. + * ----------------------------------------------------------------------- + */ +func psci_do_pwrdown_cache_maintenance + stp x29, x30, [sp,#-16]! + stp x19, x20, [sp,#-16]! + + /* --------------------------------------------- + * Determine to how many levels of cache will be + * subject to cache maintenance. Power level + * 0 implies that only the cpu is being powered + * down. Only the L1 data cache needs to be + * flushed to the PoU in this case. For a higher + * power level we are assuming that a flush + * of L1 data and L2 unified cache is enough. + * This information should be provided by the + * platform. + * --------------------------------------------- + */ + cmp w0, #PSCI_CPU_PWR_LVL + b.eq do_core_pwr_dwn + bl prepare_cluster_pwr_dwn + b do_stack_maintenance + +do_core_pwr_dwn: + bl prepare_core_pwr_dwn + + /* --------------------------------------------- + * Do stack maintenance by flushing the used + * stack to the main memory and invalidating the + * remainder. + * --------------------------------------------- + */ +do_stack_maintenance: + bl plat_get_my_stack + + /* --------------------------------------------- + * Calculate and store the size of the used + * stack memory in x1. + * --------------------------------------------- + */ + mov x19, x0 + mov x1, sp + sub x1, x0, x1 + mov x0, sp + bl flush_dcache_range + + /* --------------------------------------------- + * Calculate and store the size of the unused + * stack memory in x1. Calculate and store the + * stack base address in x0. + * --------------------------------------------- + */ + sub x0, x19, #PLATFORM_STACK_SIZE + sub x1, sp, x0 + bl inv_dcache_range + + ldp x19, x20, [sp], #16 + ldp x29, x30, [sp], #16 + ret +endfunc psci_do_pwrdown_cache_maintenance + + +/* ----------------------------------------------------------------------- + * void psci_do_pwrup_cache_maintenance(void); + * + * This function performs cache maintenance after this cpu is powered up. + * Currently, this involves managing the used stack memory before turning + * on the data cache. + * ----------------------------------------------------------------------- + */ +func psci_do_pwrup_cache_maintenance + stp x29, x30, [sp,#-16]! + + /* --------------------------------------------- + * Ensure any inflight stack writes have made it + * to main memory. + * --------------------------------------------- + */ + dmb st + + /* --------------------------------------------- + * Calculate and store the size of the used + * stack memory in x1. Calculate and store the + * stack base address in x0. + * --------------------------------------------- + */ + bl plat_get_my_stack + mov x1, sp + sub x1, x0, x1 + mov x0, sp + bl inv_dcache_range + + /* --------------------------------------------- + * Enable the data cache. + * --------------------------------------------- + */ + mrs x0, sctlr_el3 + orr x0, x0, #SCTLR_C_BIT + msr sctlr_el3, x0 + isb + + ldp x29, x30, [sp], #16 + ret +endfunc psci_do_pwrup_cache_maintenance diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_main.c b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_main.c new file mode 100644 index 0000000..e6cd3a3 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_main.c @@ -0,0 +1,408 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "psci_private.h" + +/******************************************************************************* + * PSCI frontend api for servicing SMCs. Described in the PSCI spec. + ******************************************************************************/ +int psci_cpu_on(u_register_t target_cpu, + uintptr_t entrypoint, + u_register_t context_id) + +{ + int rc; + unsigned int end_pwrlvl; + entry_point_info_t ep; + + /* Determine if the cpu exists of not */ + rc = psci_validate_mpidr(target_cpu); + if (rc != PSCI_E_SUCCESS) + return PSCI_E_INVALID_PARAMS; + + /* Validate the entry point and get the entry_point_info */ + rc = psci_validate_entry_point(&ep, entrypoint, context_id); + if (rc != PSCI_E_SUCCESS) + return rc; + + /* + * To turn this cpu on, specify which power + * levels need to be turned on + */ + end_pwrlvl = PLAT_MAX_PWR_LVL; + rc = psci_cpu_on_start(target_cpu, + &ep, + end_pwrlvl); + return rc; +} + +unsigned int psci_version(void) +{ + return PSCI_MAJOR_VER | PSCI_MINOR_VER; +} + +int psci_cpu_suspend(unsigned int power_state, + uintptr_t entrypoint, + u_register_t context_id) +{ + int rc; + unsigned int target_pwrlvl, is_power_down_state; + entry_point_info_t ep; + psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; + plat_local_state_t cpu_pd_state; + + /* Validate the power_state parameter */ + rc = psci_validate_power_state(power_state, &state_info); + if (rc != PSCI_E_SUCCESS) { + assert(rc == PSCI_E_INVALID_PARAMS); + return rc; + } + + /* + * Get the value of the state type bit from the power state parameter. + */ + is_power_down_state = psci_get_pstate_type(power_state); + + /* Sanity check the requested suspend levels */ + assert (psci_validate_suspend_req(&state_info, is_power_down_state) + == PSCI_E_SUCCESS); + + target_pwrlvl = psci_find_target_suspend_lvl(&state_info); + + /* Fast path for CPU standby.*/ + if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) { + if (!psci_plat_pm_ops->cpu_standby) + return PSCI_E_INVALID_PARAMS; + + /* + * Set the state of the CPU power domain to the platform + * specific retention state and enter the standby state. + */ + cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; + psci_set_cpu_local_state(cpu_pd_state); + psci_plat_pm_ops->cpu_standby(cpu_pd_state); + + /* Upon exit from standby, set the state back to RUN. */ + psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); + + return PSCI_E_SUCCESS; + } + + /* + * If a power down state has been requested, we need to verify entry + * point and program entry information. + */ + if (is_power_down_state) { + rc = psci_validate_entry_point(&ep, entrypoint, context_id); + if (rc != PSCI_E_SUCCESS) + return rc; + } + + /* + * Do what is needed to enter the power down state. Upon success, + * enter the final wfi which will power down this CPU. This function + * might return if the power down was abandoned for any reason, e.g. + * arrival of an interrupt + */ + psci_cpu_suspend_start(&ep, + target_pwrlvl, + &state_info, + is_power_down_state); + + return PSCI_E_SUCCESS; +} + + +int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) +{ + int rc; + psci_power_state_t state_info; + entry_point_info_t ep; + + /* Check if the current CPU is the last ON CPU in the system */ + if (!psci_is_last_on_cpu()) + return PSCI_E_DENIED; + + /* Validate the entry point and get the entry_point_info */ + rc = psci_validate_entry_point(&ep, entrypoint, context_id); + if (rc != PSCI_E_SUCCESS) + return rc; + + /* Query the psci_power_state for system suspend */ + psci_query_sys_suspend_pwrstate(&state_info); + + /* Ensure that the psci_power_state makes sense */ + assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL); + assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN) + == PSCI_E_SUCCESS); + assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL])); + + /* + * Do what is needed to enter the system suspend state. This function + * might return if the power down was abandoned for any reason, e.g. + * arrival of an interrupt + */ + psci_cpu_suspend_start(&ep, + PLAT_MAX_PWR_LVL, + &state_info, + PSTATE_TYPE_POWERDOWN); + + return PSCI_E_SUCCESS; +} + +int psci_cpu_off(void) +{ + int rc; + unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL; + + /* + * Do what is needed to power off this CPU and possible higher power + * levels if it able to do so. Upon success, enter the final wfi + * which will power down this CPU. + */ + rc = psci_do_cpu_off(target_pwrlvl); + + /* + * The only error cpu_off can return is E_DENIED. So check if that's + * indeed the case. + */ + assert (rc == PSCI_E_DENIED); + + return rc; +} + +int psci_affinity_info(u_register_t target_affinity, + unsigned int lowest_affinity_level) +{ + unsigned int target_idx; + + /* We dont support level higher than PSCI_CPU_PWR_LVL */ + if (lowest_affinity_level > PSCI_CPU_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + /* Calculate the cpu index of the target */ + target_idx = plat_core_pos_by_mpidr(target_affinity); + if (target_idx == -1) + return PSCI_E_INVALID_PARAMS; + + return psci_get_aff_info_state_by_idx(target_idx); +} + +int psci_migrate(u_register_t target_cpu) +{ + int rc; + u_register_t resident_cpu_mpidr; + + rc = psci_spd_migrate_info(&resident_cpu_mpidr); + if (rc != PSCI_TOS_UP_MIG_CAP) + return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? + PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED; + + /* + * Migrate should only be invoked on the CPU where + * the Secure OS is resident. + */ + if (resident_cpu_mpidr != read_mpidr_el1()) + return PSCI_E_NOT_PRESENT; + + /* Check the validity of the specified target cpu */ + rc = psci_validate_mpidr(target_cpu); + if (rc != PSCI_E_SUCCESS) + return PSCI_E_INVALID_PARAMS; + + assert(psci_spd_pm && psci_spd_pm->svc_migrate); + + rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu); + assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); + + return rc; +} + +int psci_migrate_info_type(void) +{ + u_register_t resident_cpu_mpidr; + + return psci_spd_migrate_info(&resident_cpu_mpidr); +} + +long psci_migrate_info_up_cpu(void) +{ + u_register_t resident_cpu_mpidr; + int rc; + + /* + * Return value of this depends upon what + * psci_spd_migrate_info() returns. + */ + rc = psci_spd_migrate_info(&resident_cpu_mpidr); + if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP) + return PSCI_E_INVALID_PARAMS; + + return resident_cpu_mpidr; +} + +int psci_features(unsigned int psci_fid) +{ + unsigned int local_caps = psci_caps; + + /* Check if it is a 64 bit function */ + if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64) + local_caps &= PSCI_CAP_64BIT_MASK; + + /* Check for invalid fid */ + if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid) + && is_psci_fid(psci_fid))) + return PSCI_E_NOT_SUPPORTED; + + + /* Check if the psci fid is supported or not */ + if (!(local_caps & define_psci_cap(psci_fid))) + return PSCI_E_NOT_SUPPORTED; + + /* Format the feature flags */ + if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 || + psci_fid == PSCI_CPU_SUSPEND_AARCH64) { + /* + * The trusted firmware does not support OS Initiated Mode. + */ + return (FF_PSTATE << FF_PSTATE_SHIFT) | + ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT); + } + + /* Return 0 for all other fid's */ + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * PSCI top level handler for servicing SMCs. + ******************************************************************************/ +uint64_t psci_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + if (is_caller_secure(flags)) + SMC_RET1(handle, SMC_UNK); + + /* Check the fid against the capabilities */ + if (!(psci_caps & define_psci_cap(smc_fid))) + SMC_RET1(handle, SMC_UNK); + + if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { + /* 32-bit PSCI function, clear top parameter bits */ + + x1 = (uint32_t)x1; + x2 = (uint32_t)x2; + x3 = (uint32_t)x3; + + switch (smc_fid) { + case PSCI_VERSION: + SMC_RET1(handle, psci_version()); + + case PSCI_CPU_OFF: + SMC_RET1(handle, psci_cpu_off()); + + case PSCI_CPU_SUSPEND_AARCH32: + SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3)); + + case PSCI_CPU_ON_AARCH32: + SMC_RET1(handle, psci_cpu_on(x1, x2, x3)); + + case PSCI_AFFINITY_INFO_AARCH32: + SMC_RET1(handle, psci_affinity_info(x1, x2)); + + case PSCI_MIG_AARCH32: + SMC_RET1(handle, psci_migrate(x1)); + + case PSCI_MIG_INFO_TYPE: + SMC_RET1(handle, psci_migrate_info_type()); + + case PSCI_MIG_INFO_UP_CPU_AARCH32: + SMC_RET1(handle, psci_migrate_info_up_cpu()); + + case PSCI_SYSTEM_SUSPEND_AARCH32: + SMC_RET1(handle, psci_system_suspend(x1, x2)); + + case PSCI_SYSTEM_OFF: + psci_system_off(); + /* We should never return from psci_system_off() */ + + case PSCI_SYSTEM_RESET: + psci_system_reset(); + /* We should never return from psci_system_reset() */ + + case PSCI_FEATURES: + SMC_RET1(handle, psci_features(x1)); + + default: + break; + } + } else { + /* 64-bit PSCI function */ + + switch (smc_fid) { + case PSCI_CPU_SUSPEND_AARCH64: + SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3)); + + case PSCI_CPU_ON_AARCH64: + SMC_RET1(handle, psci_cpu_on(x1, x2, x3)); + + case PSCI_AFFINITY_INFO_AARCH64: + SMC_RET1(handle, psci_affinity_info(x1, x2)); + + case PSCI_MIG_AARCH64: + SMC_RET1(handle, psci_migrate(x1)); + + case PSCI_MIG_INFO_UP_CPU_AARCH64: + SMC_RET1(handle, psci_migrate_info_up_cpu()); + + case PSCI_SYSTEM_SUSPEND_AARCH64: + SMC_RET1(handle, psci_system_suspend(x1, x2)); + + default: + break; + } + } + + WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid); + SMC_RET1(handle, SMC_UNK); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_off.c b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_off.c new file mode 100644 index 0000000..f565ffb --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_off.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "psci_private.h" + +/****************************************************************************** + * Construct the psci_power_state to request power OFF at all power levels. + ******************************************************************************/ +static void psci_set_power_off_state(psci_power_state_t *state_info) +{ + int lvl; + + for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) + state_info->pwr_domain_state[lvl] = PLAT_MAX_OFF_STATE; +} + +/****************************************************************************** + * Top level handler which is called when a cpu wants to power itself down. + * It's assumed that along with turning the cpu power domain off, power + * domains at higher levels will be turned off as far as possible. It finds + * the highest level where a domain has to be powered off by traversing the + * node information and then performs generic, architectural, platform setup + * and state management required to turn OFF that power domain and domains + * below it. e.g. For a cpu that's to be powered OFF, it could mean programming + * the power controller whereas for a cluster that's to be powered off, it will + * call the platform specific code which will disable coherency at the + * interconnect level if the cpu is the last in the cluster and also the + * program the power controller. + ******************************************************************************/ +int psci_do_cpu_off(unsigned int end_pwrlvl) +{ + int rc, idx = plat_my_core_pos(); + psci_power_state_t state_info; + + /* + * This function must only be called on platforms where the + * CPU_OFF platform hooks have been implemented. + */ + assert(psci_plat_pm_ops->pwr_domain_off); + + /* + * This function acquires the lock corresponding to each power + * level so that by the time all locks are taken, the system topology + * is snapshot and state management can be done safely. + */ + psci_acquire_pwr_domain_locks(end_pwrlvl, + idx); + + /* + * Call the cpu off handler registered by the Secure Payload Dispatcher + * to let it do any bookkeeping. Assume that the SPD always reports an + * E_DENIED error if SP refuse to power down + */ + if (psci_spd_pm && psci_spd_pm->svc_off) { + rc = psci_spd_pm->svc_off(0); + if (rc) + goto exit; + } + + /* Construct the psci_power_state for CPU_OFF */ + psci_set_power_off_state(&state_info); + + /* + * This function is passed the requested state info and + * it returns the negotiated state info for each power level upto + * the end level specified. + */ + psci_do_state_coordination(end_pwrlvl, &state_info); + + /* + * Arch. management. Perform the necessary steps to flush all + * cpu caches. + */ + psci_do_pwrdown_cache_maintenance(psci_find_max_off_lvl(&state_info)); + + /* + * Plat. management: Perform platform specific actions to turn this + * cpu off e.g. exit cpu coherency, program the power controller etc. + */ + psci_plat_pm_ops->pwr_domain_off(&state_info); + +exit: + /* + * Release the locks corresponding to each power level in the + * reverse order to which they were acquired. + */ + psci_release_pwr_domain_locks(end_pwrlvl, + idx); + + /* + * Set the affinity info state to OFF. This writes directly to main + * memory as caches are disabled, so cache maintenance is required + * to ensure that later cached reads of aff_info_state return + * AFF_STATE_OFF. + */ + flush_cpu_data(psci_svc_cpu_data.aff_info_state); + psci_set_aff_info_state(AFF_STATE_OFF); + inv_cpu_data(psci_svc_cpu_data.aff_info_state); + + /* + * Check if all actions needed to safely power down this cpu have + * successfully completed. Enter a wfi loop which will allow the + * power controller to physically power down this cpu. + */ + if (rc == PSCI_E_SUCCESS) + psci_power_down_wfi(); + + return rc; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_on.c b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_on.c new file mode 100644 index 0000000..c37adc2 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_on.c @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "psci_private.h" + +/******************************************************************************* + * This function checks whether a cpu which has been requested to be turned on + * is OFF to begin with. + ******************************************************************************/ +static int cpu_on_validate_state(aff_info_state_t aff_state) +{ + if (aff_state == AFF_STATE_ON) + return PSCI_E_ALREADY_ON; + + if (aff_state == AFF_STATE_ON_PENDING) + return PSCI_E_ON_PENDING; + + assert(aff_state == AFF_STATE_OFF); + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * This function sets the aff_info_state in the per-cpu data of the CPU + * specified by cpu_idx + ******************************************************************************/ +static void psci_set_aff_info_state_by_idx(unsigned int cpu_idx, + aff_info_state_t aff_state) +{ + + set_cpu_data_by_index(cpu_idx, + psci_svc_cpu_data.aff_info_state, + aff_state); + + /* + * Flush aff_info_state as it will be accessed with caches turned OFF. + */ + flush_cpu_data_by_index(cpu_idx, psci_svc_cpu_data.aff_info_state); +} + +/******************************************************************************* + * Generic handler which is called to physically power on a cpu identified by + * its mpidr. It performs the generic, architectural, platform setup and state + * management to power on the target cpu e.g. it will ensure that + * enough information is stashed for it to resume execution in the non-secure + * security state. + * + * The state of all the relevant power domains are changed after calling the + * platform handler as it can return error. + ******************************************************************************/ +int psci_cpu_on_start(u_register_t target_cpu, + entry_point_info_t *ep, + unsigned int end_pwrlvl) +{ + int rc; + unsigned int target_idx = plat_core_pos_by_mpidr(target_cpu); + + /* + * This function must only be called on platforms where the + * CPU_ON platform hooks have been implemented. + */ + assert(psci_plat_pm_ops->pwr_domain_on && + psci_plat_pm_ops->pwr_domain_on_finish); + + /* Protect against multiple CPUs trying to turn ON the same target CPU */ + psci_spin_lock_cpu(target_idx); + + /* + * Generic management: Ensure that the cpu is off to be + * turned on. + */ + rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx)); + if (rc != PSCI_E_SUCCESS) + goto exit; + + /* + * Call the cpu on handler registered by the Secure Payload Dispatcher + * to let it do any bookeeping. If the handler encounters an error, it's + * expected to assert within + */ + if (psci_spd_pm && psci_spd_pm->svc_on) + psci_spd_pm->svc_on(target_cpu); + + /* + * Set the Affinity info state of the target cpu to ON_PENDING. + */ + psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); + + /* + * Perform generic, architecture and platform specific handling. + */ + /* + * Plat. management: Give the platform the current state + * of the target cpu to allow it to perform the necessary + * steps to power on. + */ + rc = psci_plat_pm_ops->pwr_domain_on(target_cpu); + assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); + + if (rc == PSCI_E_SUCCESS) + /* Store the re-entry information for the non-secure world. */ + cm_init_context_by_index(target_idx, ep); + else + /* Restore the state on error. */ + psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF); + +exit: + psci_spin_unlock_cpu(target_idx); + return rc; +} + +/******************************************************************************* + * The following function finish an earlier power on request. They + * are called by the common finisher routine in psci_common.c. The `state_info` + * is the psci_power_state from which this CPU has woken up from. + ******************************************************************************/ +void psci_cpu_on_finish(unsigned int cpu_idx, + psci_power_state_t *state_info) +{ + /* + * Plat. management: Perform the platform specific actions + * for this cpu e.g. enabling the gic or zeroing the mailbox + * register. The actual state of this cpu has already been + * changed. + */ + psci_plat_pm_ops->pwr_domain_on_finish(state_info); + + /* + * Arch. management: Enable data cache and manage stack memory + */ + psci_do_pwrup_cache_maintenance(); + + /* + * All the platform specific actions for turning this cpu + * on have completed. Perform enough arch.initialization + * to run in the non-secure address space. + */ + bl31_arch_setup(); + + /* + * Lock the CPU spin lock to make sure that the context initialization + * is done. Since the lock is only used in this function to create + * a synchronization point with cpu_on_start(), it can be released + * immediately. + */ + psci_spin_lock_cpu(cpu_idx); + psci_spin_unlock_cpu(cpu_idx); + + /* Ensure we have been explicitly woken up by another cpu */ + assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING); + + /* + * Call the cpu on finish handler registered by the Secure Payload + * Dispatcher to let it do any bookeeping. If the handler encounters an + * error, it's expected to assert within + */ + if (psci_spd_pm && psci_spd_pm->svc_on_finish) + psci_spd_pm->svc_on_finish(0); + + /* Populate the mpidr field within the cpu node array */ + /* This needs to be done only once */ + psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK; + + /* + * Generic management: Now we just need to retrieve the + * information that we had stashed away during the cpu_on + * call to set this cpu on its way. + */ + cm_prepare_el3_exit(NON_SECURE); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_private.h b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_private.h new file mode 100644 index 0000000..8c028a7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_private.h @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PSCI_PRIVATE_H__ +#define __PSCI_PRIVATE_H__ + +#include +#include +#include +#include +#include +#include + +/* + * The following helper macros abstract the interface to the Bakery + * Lock API. + */ +#define psci_lock_init(non_cpu_pd_node, idx) \ + ((non_cpu_pd_node)[(idx)].lock_index = (idx)) +#define psci_lock_get(non_cpu_pd_node) \ + bakery_lock_get(&psci_locks[(non_cpu_pd_node)->lock_index]) +#define psci_lock_release(non_cpu_pd_node) \ + bakery_lock_release(&psci_locks[(non_cpu_pd_node)->lock_index]) + +/* + * The PSCI capability which are provided by the generic code but does not + * depend on the platform or spd capabilities. + */ +#define PSCI_GENERIC_CAP \ + (define_psci_cap(PSCI_VERSION) | \ + define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ + define_psci_cap(PSCI_FEATURES)) + +/* + * The PSCI capabilities mask for 64 bit functions. + */ +#define PSCI_CAP_64BIT_MASK \ + (define_psci_cap(PSCI_CPU_SUSPEND_AARCH64) | \ + define_psci_cap(PSCI_CPU_ON_AARCH64) | \ + define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ + define_psci_cap(PSCI_MIG_AARCH64) | \ + define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) | \ + define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64)) + +/* + * Helper macros to get/set the fields of PSCI per-cpu data. + */ +#define psci_set_aff_info_state(aff_state) \ + set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state) +#define psci_get_aff_info_state() \ + get_cpu_data(psci_svc_cpu_data.aff_info_state) +#define psci_get_aff_info_state_by_idx(idx) \ + get_cpu_data_by_index(idx, psci_svc_cpu_data.aff_info_state) +#define psci_get_suspend_pwrlvl() \ + get_cpu_data(psci_svc_cpu_data.target_pwrlvl) +#define psci_set_suspend_pwrlvl(target_lvl) \ + set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl) +#define psci_set_cpu_local_state(state) \ + set_cpu_data(psci_svc_cpu_data.local_state, state) +#define psci_get_cpu_local_state() \ + get_cpu_data(psci_svc_cpu_data.local_state) +#define psci_get_cpu_local_state_by_idx(idx) \ + get_cpu_data_by_index(idx, psci_svc_cpu_data.local_state) + +/* + * Helper macros for the CPU level spinlocks + */ +#define psci_spin_lock_cpu(idx) spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock) +#define psci_spin_unlock_cpu(idx) spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock) + +/* Helper macro to identify a CPU standby request in PSCI Suspend call */ +#define is_cpu_standby_req(is_power_down_state, retn_lvl) \ + (((!(is_power_down_state)) && ((retn_lvl) == 0)) ? 1 : 0) + +/******************************************************************************* + * The following two data structures implement the power domain tree. The tree + * is used to track the state of all the nodes i.e. power domain instances + * described by the platform. The tree consists of nodes that describe CPU power + * domains i.e. leaf nodes and all other power domains which are parents of a + * CPU power domain i.e. non-leaf nodes. + ******************************************************************************/ +typedef struct non_cpu_pwr_domain_node { + /* + * Index of the first CPU power domain node level 0 which has this node + * as its parent. + */ + unsigned int cpu_start_idx; + + /* + * Number of CPU power domains which are siblings of the domain indexed + * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx + * -> cpu_start_idx + ncpus' have this node as their parent. + */ + unsigned int ncpus; + + /* + * Index of the parent power domain node. + * TODO: Figure out whether to whether using pointer is more efficient. + */ + unsigned int parent_node; + + plat_local_state_t local_state; + + unsigned char level; + + /* For indexing the psci_lock array*/ + unsigned char lock_index; +} non_cpu_pd_node_t; + +typedef struct cpu_pwr_domain_node { + u_register_t mpidr; + + /* + * Index of the parent power domain node. + * TODO: Figure out whether to whether using pointer is more efficient. + */ + unsigned int parent_node; + + /* + * A CPU power domain does not require state coordination like its + * parent power domains. Hence this node does not include a bakery + * lock. A spinlock is required by the CPU_ON handler to prevent a race + * when multiple CPUs try to turn ON the same target CPU. + */ + spinlock_t cpu_lock; +} cpu_pd_node_t; + +/******************************************************************************* + * Data prototypes + ******************************************************************************/ +extern const plat_psci_ops_t *psci_plat_pm_ops; +extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; +extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; +extern unsigned int psci_caps; + +/* One bakery lock is required for each non-cpu power domain */ +DECLARE_BAKERY_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); + +/******************************************************************************* + * SPD's power management hooks registered with PSCI + ******************************************************************************/ +extern const spd_pm_ops_t *psci_spd_pm; + +/******************************************************************************* + * Function prototypes + ******************************************************************************/ +/* Private exported functions from psci_common.c */ +int psci_validate_power_state(unsigned int power_state, + psci_power_state_t *state_info); +void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info); +int psci_validate_mpidr(u_register_t mpidr); +void psci_init_req_local_pwr_states(void); +void psci_power_up_finish(void); +int psci_validate_entry_point(entry_point_info_t *ep, + uintptr_t entrypoint, u_register_t context_id); +void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, + unsigned int end_lvl, + unsigned int node_index[]); +void psci_do_state_coordination(unsigned int end_pwrlvl, + psci_power_state_t *state_info); +void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, + unsigned int cpu_idx); +void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, + unsigned int cpu_idx); +int psci_validate_suspend_req(const psci_power_state_t *state_info, + unsigned int is_power_down_state_req); +unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info); +unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info); +void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl); +void psci_print_power_domain_map(void); +unsigned int psci_is_last_on_cpu(void); +int psci_spd_migrate_info(u_register_t *mpidr); + +/* Private exported functions from psci_on.c */ +int psci_cpu_on_start(unsigned long target_cpu, + entry_point_info_t *ep, + unsigned int end_pwrlvl); + +void psci_cpu_on_finish(unsigned int cpu_idx, + psci_power_state_t *state_info); + +/* Private exported functions from psci_cpu_off.c */ +int psci_do_cpu_off(unsigned int end_pwrlvl); + +/* Private exported functions from psci_pwrlvl_suspend.c */ +void psci_cpu_suspend_start(entry_point_info_t *ep, + unsigned int end_pwrlvl, + psci_power_state_t *state_info, + unsigned int is_power_down_state_req); + +void psci_cpu_suspend_finish(unsigned int cpu_idx, + psci_power_state_t *state_info); + +/* Private exported functions from psci_helpers.S */ +void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level); +void psci_do_pwrup_cache_maintenance(void); + +/* Private exported functions from psci_system_off.c */ +void __dead2 psci_system_off(void); +void __dead2 psci_system_reset(void); + +#endif /* __PSCI_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_setup.c new file mode 100644 index 0000000..cd1bb09 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_setup.c @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "psci_private.h" + +/******************************************************************************* + * Per cpu non-secure contexts used to program the architectural state prior + * return to the normal world. + * TODO: Use the memory allocator to set aside memory for the contexts instead + * of relying on platform defined constants. + ******************************************************************************/ +static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT]; + +/****************************************************************************** + * Define the psci capability variable. + *****************************************************************************/ +unsigned int psci_caps; + +/******************************************************************************* + * Function which initializes the 'psci_non_cpu_pd_nodes' or the + * 'psci_cpu_pd_nodes' corresponding to the power level. + ******************************************************************************/ +static void psci_init_pwr_domain_node(unsigned int node_idx, + unsigned int parent_idx, + unsigned int level) +{ + if (level > PSCI_CPU_PWR_LVL) { + psci_non_cpu_pd_nodes[node_idx].level = level; + psci_lock_init(psci_non_cpu_pd_nodes, node_idx); + psci_non_cpu_pd_nodes[node_idx].parent_node = parent_idx; + psci_non_cpu_pd_nodes[node_idx].local_state = + PLAT_MAX_OFF_STATE; + } else { + psci_cpu_data_t *svc_cpu_data; + + psci_cpu_pd_nodes[node_idx].parent_node = parent_idx; + + /* Initialize with an invalid mpidr */ + psci_cpu_pd_nodes[node_idx].mpidr = PSCI_INVALID_MPIDR; + + svc_cpu_data = + &(_cpu_data_by_index(node_idx)->psci_svc_cpu_data); + + /* Set the Affinity Info for the cores as OFF */ + svc_cpu_data->aff_info_state = AFF_STATE_OFF; + + /* Invalidate the suspend level for the cpu */ + svc_cpu_data->target_pwrlvl = PSCI_INVALID_PWR_LVL; + + /* Set the power state to OFF state */ + svc_cpu_data->local_state = PLAT_MAX_OFF_STATE; + + flush_dcache_range((uintptr_t)svc_cpu_data, + sizeof(*svc_cpu_data)); + + cm_set_context_by_index(node_idx, + (void *) &psci_ns_context[node_idx], + NON_SECURE); + } +} + +/******************************************************************************* + * This functions updates cpu_start_idx and ncpus field for each of the node in + * psci_non_cpu_pd_nodes[]. It does so by comparing the parent nodes of each of + * the CPUs and check whether they match with the parent of the previous + * CPU. The basic assumption for this work is that children of the same parent + * are allocated adjacent indices. The platform should ensure this though proper + * mapping of the CPUs to indices via plat_core_pos_by_mpidr() and + * plat_my_core_pos() APIs. + *******************************************************************************/ +static void psci_update_pwrlvl_limits(void) +{ + int j; + unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0}; + unsigned int temp_index[PLAT_MAX_PWR_LVL], cpu_idx; + + for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) { + psci_get_parent_pwr_domain_nodes(cpu_idx, + PLAT_MAX_PWR_LVL, + temp_index); + for (j = PLAT_MAX_PWR_LVL - 1; j >= 0; j--) { + if (temp_index[j] != nodes_idx[j]) { + nodes_idx[j] = temp_index[j]; + psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx + = cpu_idx; + } + psci_non_cpu_pd_nodes[nodes_idx[j]].ncpus++; + } + } +} + +/******************************************************************************* + * Core routine to populate the power domain tree. The tree descriptor passed by + * the platform is populated breadth-first and the first entry in the map + * informs the number of root power domains. The parent nodes of the root nodes + * will point to an invalid entry(-1). + ******************************************************************************/ +static void populate_power_domain_tree(const unsigned char *topology) +{ + unsigned int i, j = 0, num_nodes_at_lvl = 1, num_nodes_at_next_lvl; + unsigned int node_index = 0, parent_node_index = 0, num_children; + int level = PLAT_MAX_PWR_LVL; + + /* + * For each level the inputs are: + * - number of nodes at this level in plat_array i.e. num_nodes_at_level + * This is the sum of values of nodes at the parent level. + * - Index of first entry at this level in the plat_array i.e. + * parent_node_index. + * - Index of first free entry in psci_non_cpu_pd_nodes[] or + * psci_cpu_pd_nodes[] i.e. node_index depending upon the level. + */ + while (level >= PSCI_CPU_PWR_LVL) { + num_nodes_at_next_lvl = 0; + /* + * For each entry (parent node) at this level in the plat_array: + * - Find the number of children + * - Allocate a node in a power domain array for each child + * - Set the parent of the child to the parent_node_index - 1 + * - Increment parent_node_index to point to the next parent + * - Accumulate the number of children at next level. + */ + for (i = 0; i < num_nodes_at_lvl; i++) { + assert(parent_node_index <= + PSCI_NUM_NON_CPU_PWR_DOMAINS); + num_children = topology[parent_node_index]; + + for (j = node_index; + j < node_index + num_children; j++) + psci_init_pwr_domain_node(j, + parent_node_index - 1, + level); + + node_index = j; + num_nodes_at_next_lvl += num_children; + parent_node_index++; + } + + num_nodes_at_lvl = num_nodes_at_next_lvl; + level--; + + /* Reset the index for the cpu power domain array */ + if (level == PSCI_CPU_PWR_LVL) + node_index = 0; + } + + /* Validate the sanity of array exported by the platform */ + assert(j == PLATFORM_CORE_COUNT); +} + +/******************************************************************************* + * This function initializes the power domain topology tree by querying the + * platform. The power domain nodes higher than the CPU are populated in the + * array psci_non_cpu_pd_nodes[] and the CPU power domains are populated in + * psci_cpu_pd_nodes[]. The platform exports its static topology map through the + * populate_power_domain_topology_tree() API. The algorithm populates the + * psci_non_cpu_pd_nodes and psci_cpu_pd_nodes iteratively by using this + * topology map. On a platform that implements two clusters of 2 cpus each, and + * supporting 3 domain levels, the populated psci_non_cpu_pd_nodes would look + * like this: + * + * --------------------------------------------------- + * | system node | cluster 0 node | cluster 1 node | + * --------------------------------------------------- + * + * And populated psci_cpu_pd_nodes would look like this : + * <- cpus cluster0 -><- cpus cluster1 -> + * ------------------------------------------------ + * | CPU 0 | CPU 1 | CPU 2 | CPU 3 | + * ------------------------------------------------ + ******************************************************************************/ +int psci_setup(void) +{ + const unsigned char *topology_tree; + + /* Query the topology map from the platform */ + topology_tree = plat_get_power_domain_tree_desc(); + + /* Populate the power domain arrays using the platform topology map */ + populate_power_domain_tree(topology_tree); + + /* Update the CPU limits for each node in psci_non_cpu_pd_nodes */ + psci_update_pwrlvl_limits(); + + /* Populate the mpidr field of cpu node for this CPU */ + psci_cpu_pd_nodes[plat_my_core_pos()].mpidr = + read_mpidr() & MPIDR_AFFINITY_MASK; + + psci_init_req_local_pwr_states(); + + /* + * Set the requested and target state of this CPU and all the higher + * power domain levels for this CPU to run. + */ + psci_set_pwr_domains_to_run(PLAT_MAX_PWR_LVL); + + plat_setup_psci_ops((uintptr_t)psci_entrypoint, + &psci_plat_pm_ops); + assert(psci_plat_pm_ops); + + /* Initialize the psci capability */ + psci_caps = PSCI_GENERIC_CAP; + + if (psci_plat_pm_ops->pwr_domain_off) + psci_caps |= define_psci_cap(PSCI_CPU_OFF); + if (psci_plat_pm_ops->pwr_domain_on && + psci_plat_pm_ops->pwr_domain_on_finish) + psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64); + if (psci_plat_pm_ops->pwr_domain_suspend && + psci_plat_pm_ops->pwr_domain_suspend_finish) { + psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64); + if (psci_plat_pm_ops->get_sys_suspend_power_state) + psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64); + } + if (psci_plat_pm_ops->system_off) + psci_caps |= define_psci_cap(PSCI_SYSTEM_OFF); + if (psci_plat_pm_ops->system_reset) + psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET); + + return 0; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_suspend.c b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_suspend.c new file mode 100644 index 0000000..bd0c5db --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_suspend.c @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "psci_private.h" + +/******************************************************************************* + * This function does generic and platform specific operations after a wake-up + * from standby/retention states at multiple power levels. + ******************************************************************************/ +static void psci_suspend_to_standby_finisher(unsigned int cpu_idx, + psci_power_state_t *state_info, + unsigned int end_pwrlvl) +{ + psci_acquire_pwr_domain_locks(end_pwrlvl, + cpu_idx); + + /* + * Plat. management: Allow the platform to do operations + * on waking up from retention. + */ + psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); + + /* + * Set the requested and target state of this CPU and all the higher + * power domain levels for this CPU to run. + */ + psci_set_pwr_domains_to_run(end_pwrlvl); + + psci_release_pwr_domain_locks(end_pwrlvl, + cpu_idx); +} + +/******************************************************************************* + * This function does generic and platform specific suspend to power down + * operations. + ******************************************************************************/ +static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl, + entry_point_info_t *ep, + psci_power_state_t *state_info) +{ + unsigned int max_off_lvl = psci_find_max_off_lvl(state_info); + + /* Save PSCI target power level for the suspend finisher handler */ + psci_set_suspend_pwrlvl(end_pwrlvl); + + /* + * Flush the target power level as it will be accessed on power up with + * Data cache disabled. + */ + flush_cpu_data(psci_svc_cpu_data.target_pwrlvl); + + /* + * Call the cpu suspend handler registered by the Secure Payload + * Dispatcher to let it do any book-keeping. If the handler encounters an + * error, it's expected to assert within + */ + if (psci_spd_pm && psci_spd_pm->svc_suspend) + psci_spd_pm->svc_suspend(max_off_lvl); + + /* + * Store the re-entry information for the non-secure world. + */ + cm_init_my_context(ep); + + /* + * Arch. management. Perform the necessary steps to flush all + * cpu caches. Currently we assume that the power level correspond + * the cache level. + * TODO : Introduce a mechanism to query the cache level to flush + * and the cpu-ops power down to perform from the platform. + */ + psci_do_pwrdown_cache_maintenance(max_off_lvl); +} + +/******************************************************************************* + * Top level handler which is called when a cpu wants to suspend its execution. + * It is assumed that along with suspending the cpu power domain, power domains + * at higher levels until the target power level will be suspended as well. It + * coordinates with the platform to negotiate the target state for each of + * the power domain level till the target power domain level. It then performs + * generic, architectural, platform setup and state management required to + * suspend that power domain level and power domain levels below it. + * e.g. For a cpu that's to be suspended, it could mean programming the + * power controller whereas for a cluster that's to be suspended, it will call + * the platform specific code which will disable coherency at the interconnect + * level if the cpu is the last in the cluster and also the program the power + * controller. + * + * All the required parameter checks are performed at the beginning and after + * the state transition has been done, no further error is expected and it is + * not possible to undo any of the actions taken beyond that point. + ******************************************************************************/ +void psci_cpu_suspend_start(entry_point_info_t *ep, + unsigned int end_pwrlvl, + psci_power_state_t *state_info, + unsigned int is_power_down_state) +{ + int skip_wfi = 0; + unsigned int idx = plat_my_core_pos(); + + /* + * This function must only be called on platforms where the + * CPU_SUSPEND platform hooks have been implemented. + */ + assert(psci_plat_pm_ops->pwr_domain_suspend && + psci_plat_pm_ops->pwr_domain_suspend_finish); + + /* + * This function acquires the lock corresponding to each power + * level so that by the time all locks are taken, the system topology + * is snapshot and state management can be done safely. + */ + psci_acquire_pwr_domain_locks(end_pwrlvl, + idx); + + /* + * We check if there are any pending interrupts after the delay + * introduced by lock contention to increase the chances of early + * detection that a wake-up interrupt has fired. + */ + if (read_isr_el1()) { + skip_wfi = 1; + goto exit; + } + + /* + * This function is passed the requested state info and + * it returns the negotiated state info for each power level upto + * the end level specified. + */ + psci_do_state_coordination(end_pwrlvl, state_info); + + if (is_power_down_state) + psci_suspend_to_pwrdown_start(end_pwrlvl, ep, state_info); + + /* + * Plat. management: Allow the platform to perform the + * necessary actions to turn off this cpu e.g. set the + * platform defined mailbox with the psci entrypoint, + * program the power controller etc. + */ + psci_plat_pm_ops->pwr_domain_suspend(state_info); + +exit: + /* + * Release the locks corresponding to each power level in the + * reverse order to which they were acquired. + */ + psci_release_pwr_domain_locks(end_pwrlvl, + idx); + if (skip_wfi) + return; + + if (is_power_down_state) + psci_power_down_wfi(); + + /* + * We will reach here if only retention/standby states have been + * requested at multiple power levels. This means that the cpu + * context will be preserved. + */ + wfi(); + + /* + * After we wake up from context retaining suspend, call the + * context retaining suspend finisher. + */ + psci_suspend_to_standby_finisher(idx, state_info, end_pwrlvl); +} + +/******************************************************************************* + * The following functions finish an earlier suspend request. They + * are called by the common finisher routine in psci_common.c. The `state_info` + * is the psci_power_state from which this CPU has woken up from. + ******************************************************************************/ +void psci_cpu_suspend_finish(unsigned int cpu_idx, + psci_power_state_t *state_info) +{ + unsigned long long counter_freq; + unsigned int max_off_lvl; + + /* Ensure we have been woken up from a suspended state */ + assert(psci_get_aff_info_state() == AFF_STATE_ON && is_local_state_off(\ + state_info->pwr_domain_state[PSCI_CPU_PWR_LVL])); + + /* + * Plat. management: Perform the platform specific actions + * before we change the state of the cpu e.g. enabling the + * gic or zeroing the mailbox register. If anything goes + * wrong then assert as there is no way to recover from this + * situation. + */ + psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); + + /* + * Arch. management: Enable the data cache, manage stack memory and + * restore the stashed EL3 architectural context from the 'cpu_context' + * structure for this cpu. + */ + psci_do_pwrup_cache_maintenance(); + + /* Re-init the cntfrq_el0 register */ + counter_freq = plat_get_syscnt_freq(); + write_cntfrq_el0(counter_freq); + + /* + * Call the cpu suspend finish handler registered by the Secure Payload + * Dispatcher to let it do any bookeeping. If the handler encounters an + * error, it's expected to assert within + */ + if (psci_spd_pm && psci_spd_pm->svc_suspend) { + max_off_lvl = psci_find_max_off_lvl(state_info); + assert (max_off_lvl != PSCI_INVALID_PWR_LVL); + psci_spd_pm->svc_suspend_finish(max_off_lvl); + } + + /* Invalidate the suspend level for the cpu */ + psci_set_suspend_pwrlvl(PSCI_INVALID_PWR_LVL); + + /* + * Generic management: Now we just need to retrieve the + * information that we had stashed away during the suspend + * call to set this cpu on its way. + */ + cm_prepare_el3_exit(NON_SECURE); +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_system_off.c b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_system_off.c new file mode 100644 index 0000000..28315d6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/psci/psci_system_off.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "psci_private.h" + +void psci_system_off(void) +{ + psci_print_power_domain_map(); + + assert(psci_plat_pm_ops->system_off); + + /* Notify the Secure Payload Dispatcher */ + if (psci_spd_pm && psci_spd_pm->svc_system_off) { + psci_spd_pm->svc_system_off(); + } + + /* Call the platform specific hook */ + psci_plat_pm_ops->system_off(); + + /* This function does not return. We should never get here */ +} + +void psci_system_reset(void) +{ + psci_print_power_domain_map(); + + assert(psci_plat_pm_ops->system_reset); + + /* Notify the Secure Payload Dispatcher */ + if (psci_spd_pm && psci_spd_pm->svc_system_reset) { + psci_spd_pm->svc_system_reset(); + } + + /* Call the platform specific hook */ + psci_plat_pm_ops->system_reset(); + + /* This function does not return. We should never get here */ +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/std_svc_setup.c b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/std_svc_setup.c new file mode 100644 index 0000000..6cb0319 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/services/std_svc/std_svc_setup.c @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* Standard Service UUID */ +DEFINE_SVC_UUID(arm_svc_uid, + 0x108d905b, 0xf863, 0x47e8, 0xae, 0x2d, + 0xc0, 0xfb, 0x56, 0x41, 0xf6, 0xe2); + +/* Setup Standard Services */ +static int32_t std_svc_setup(void) +{ + /* + * PSCI is the only specification implemented as a Standard Service. + * Invoke PSCI setup from here + */ + return psci_setup(); +} + +/* + * Top-level Standard Service SMC handler. This handler will in turn dispatch + * calls to PSCI SMC handler + */ +uint64_t std_svc_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + /* + * Dispatch PSCI calls to PSCI SMC handler and return its return + * value + */ + if (is_psci_fid(smc_fid)) { + return psci_smc_handler(smc_fid, x1, x2, x3, x4, cookie, + handle, flags); + } + + switch (smc_fid) { + case ARM_STD_SVC_CALL_COUNT: + /* + * Return the number of Standard Service Calls. PSCI is the only + * standard service implemented; so return number of PSCI calls + */ + SMC_RET1(handle, PSCI_NUM_CALLS); + + case ARM_STD_SVC_UID: + /* Return UID to the caller */ + SMC_UUID_RET(handle, arm_svc_uid); + + case ARM_STD_SVC_VERSION: + /* Return the version of current implementation */ + SMC_RET2(handle, STD_SVC_VERSION_MAJOR, STD_SVC_VERSION_MINOR); + + default: + WARN("Unimplemented Standard Service Call: 0x%x \n", smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} + +/* Register Standard Service Calls as runtime service */ +DECLARE_RT_SVC( + std_svc, + + OEN_STD_START, + OEN_STD_END, + SMC_TYPE_FAST, + std_svc_setup, + std_svc_smc_handler +); diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/Makefile b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/Makefile new file mode 100644 index 0000000..7efaf8a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/Makefile @@ -0,0 +1,99 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +PROJECT := cert_create +PLAT := none +V := 0 +DEBUG := 0 +BINARY := ${PROJECT} +OPENSSL_DIR := /usr + +OBJECTS := src/cert.o \ + src/ext.o \ + src/key.o \ + src/main.o \ + src/sha.o \ + src/tbbr/tbb_cert.o \ + src/tbbr/tbb_ext.o \ + src/tbbr/tbb_key.o + +CFLAGS := -Wall -std=c99 + +# Check the platform +ifeq (${PLAT},none) + $(error "Error: Unknown platform. Please use PLAT= to specify the platform") +endif +PLAT_MAKEFILE := platform.mk +PLAT_INCLUDE := $(shell find ../../plat/ -wholename '*/${PLAT}/${PLAT_MAKEFILE}' | \ + sed 's/${PLAT_MAKEFILE}/include/') +ifeq ($(PLAT_INCLUDE),) + $(error "Error: Invalid platform '${PLAT}'") +endif + +ifeq (${DEBUG},1) + CFLAGS += -g -O0 -DDEBUG -DLOG_LEVEL=40 +else + CFLAGS += -O2 -DLOG_LEVEL=20 +endif +ifeq (${V},0) + Q := @ +else + Q := +endif + +# Make soft links and include from local directory otherwise wrong headers +# could get pulled in from firmware tree. +INC_DIR := -I ./include -I ${PLAT_INCLUDE} -I ${OPENSSL_DIR}/include +LIB_DIR := -L ${OPENSSL_DIR}/lib +LIB := -lssl -lcrypto + +CC := gcc +RM := rm -rf + +.PHONY: all clean + +all: clean ${BINARY} + +${BINARY}: ${OBJECTS} Makefile + @echo " LD $@" + @echo 'const char build_msg[] = "Built : "__TIME__", "__DATE__; \ + const char platform_msg[] = "${PLAT}";' | \ + ${CC} -c ${CFLAGS} -xc - -o src/build_msg.o + ${Q}${CC} src/build_msg.o ${OBJECTS} ${LIB_DIR} ${LIB} -o $@ + +%.o: %.c + @echo " CC $<" + ${Q}${CC} -c ${CFLAGS} ${INC_DIR} $< -o $@ + +clean: + ${Q}${RM} -f src/build_msg.o ${OBJECTS} + +realclean: clean + ${Q}${RM} -f ${BINARY} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/cert.h b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/cert.h new file mode 100644 index 0000000..18129a7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/cert.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef CERT_H_ +#define CERT_H_ + +#include +#include +#include "ext.h" +#include "key.h" + +#define CERT_MAX_EXT 4 + +/* + * This structure contains information related to the generation of the + * certificates. All these fields must be known and specified at build time + * except for the file name, which is picked up from the command line at + * run time. + * + * One instance of this structure must be created for each of the certificates + * present in the chain of trust. + * + * If the issuer points to this same instance, the generated certificate will + * be self-signed. + */ +typedef struct cert_s cert_t; +struct cert_s { + int id; /* Unique identifier */ + + const char *fn; /* Filename to save the certificate */ + const char *cn; /* Subject CN (Company Name) */ + + /* These fields must be defined statically */ + int key; /* Key to be signed */ + int issuer; /* Issuer certificate */ + int ext[CERT_MAX_EXT]; /* Certificate extensions */ + int num_ext; /* Number of extensions in the certificate */ + + X509 *x; /* X509 certificate container */ +}; + +/* Exported API */ +int cert_add_ext(X509 *issuer, X509 *subject, int nid, char *value); +int cert_new(cert_t *cert, int days, int ca, STACK_OF(X509_EXTENSION) * sk); + +/* Macro to register the certificates used in the CoT */ +#define REGISTER_COT(_certs) \ + cert_t *certs = &_certs[0]; \ + const unsigned int num_certs = sizeof(_certs)/sizeof(_certs[0]); + +/* Exported variables */ +extern cert_t *certs; +extern const unsigned int num_certs; + +#endif /* CERT_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/debug.h b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/debug.h new file mode 100644 index 0000000..dd0510a --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/debug.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +#include + +/* The log output macros print output to the console. These macros produce + * compiled log output only if the LOG_LEVEL defined in the makefile (or the + * make command line) is greater or equal than the level required for that + * type of log output. + * The format expected is the same as for printf(). For example: + * INFO("Info %s.\n", "message") -> INFO: Info message. + * WARN("Warning %s.\n", "message") -> WARNING: Warning message. + */ + +#define LOG_LEVEL_NONE 0 +#define LOG_LEVEL_ERROR 10 +#define LOG_LEVEL_NOTICE 20 +#define LOG_LEVEL_WARNING 30 +#define LOG_LEVEL_INFO 40 +#define LOG_LEVEL_VERBOSE 50 + + +#if LOG_LEVEL >= LOG_LEVEL_NOTICE +# define NOTICE(...) printf("NOTICE: " __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_ERROR +# define ERROR(...) printf("ERROR: " __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_WARNING +# define WARN(...) printf("WARNING: " __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_INFO +# define INFO(...) printf("INFO: " __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE +# define VERBOSE(...) printf("VERBOSE: " __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + +#endif /* __DEBUG_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/ext.h b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/ext.h new file mode 100644 index 0000000..60455e6 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/ext.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef EXT_H_ +#define EXT_H_ + +#include "key.h" +#include + +/* Extension types supported */ +enum { + EXT_TYPE_NVCOUNTER, + EXT_TYPE_PKEY, + EXT_TYPE_HASH +}; + +/* + * This structure contains the relevant information to create the extensions + * to be included in the certificates. This extensions will be used to + * establish the chain of trust. + */ +typedef struct ext_s { + const char *oid; /* OID of the extension */ + const char *sn; /* Short name */ + const char *ln; /* Long description */ + int asn1_type; /* OpenSSL ASN1 type of the extension data. + * Supported types are: + * - V_ASN1_INTEGER + * - V_ASN1_OCTET_STRING + */ + int type; + /* Extension data (depends on extension type) */ + union { + const char *fn; /* File with extension data */ + int nvcounter; /* Non volatile counter */ + int key; /* Public key */ + } data; + + int alias; /* In case OpenSSL provides an standard + * extension of the same type, add the new + * extension as an alias of this one + */ + + X509V3_EXT_METHOD method; /* This field may be used to define a custom + * function to print the contents of the + * extension */ +} ext_t; + +enum { + EXT_NON_CRIT = 0, + EXT_CRIT = !EXT_NON_CRIT, +}; + +/* Exported API */ +int ext_register(ext_t *tbb_ext); +X509_EXTENSION *ext_new_hash(int nid, int crit, const EVP_MD *md, + unsigned char *buf, size_t len); +X509_EXTENSION *ext_new_nvcounter(int nid, int crit, int value); +X509_EXTENSION *ext_new_key(int nid, int crit, EVP_PKEY *k); + +/* Macro to register the extensions used in the CoT */ +#define REGISTER_EXTENSIONS(_ext) \ + ext_t *extensions = &_ext[0]; \ + const unsigned int num_extensions = sizeof(_ext)/sizeof(_ext[0]); + +/* Exported variables */ +extern ext_t *extensions; +extern const unsigned int num_extensions; + +#endif /* EXT_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/key.h b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/key.h new file mode 100644 index 0000000..da9f119 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/key.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef KEY_H_ +#define KEY_H_ + +#include + +#define RSA_KEY_BITS 2048 + +/* Error codes */ +enum { + KEY_ERR_NONE, + KEY_ERR_MALLOC, + KEY_ERR_FILENAME, + KEY_ERR_OPEN, + KEY_ERR_LOAD +}; + +/* Supported key algorithms */ +enum { + KEY_ALG_RSA, +#ifndef OPENSSL_NO_EC + KEY_ALG_ECDSA, +#endif /* OPENSSL_NO_EC */ + KEY_ALG_MAX_NUM +}; + +/* + * This structure contains the relevant information to create the keys + * required to sign the certificates. + * + * One instance of this structure must be created for each key, usually in an + * array fashion. The filename is obtained at run time from the command line + * parameters + */ +typedef struct key_s { + int id; /* Key id */ + const char *desc; /* Key description (debug purposes) */ + char *fn; /* Filename to load/store the key */ + EVP_PKEY *key; /* Key container */ +} key_t; + +/* Exported API */ +int key_create(key_t *key, int type); +int key_load(key_t *key, unsigned int *err_code); +int key_store(key_t *key); + +/* Macro to register the keys used in the CoT */ +#define REGISTER_KEYS(_keys) \ + key_t *keys = &_keys[0]; \ + const unsigned int num_keys = sizeof(_keys)/sizeof(_keys[0]); + +/* Exported variables */ +extern key_t *keys; +extern const unsigned int num_keys; + +#endif /* KEY_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/sha.h b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/sha.h new file mode 100644 index 0000000..466d668 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/sha.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef SHA_H_ +#define SHA_H_ + +int sha_file(const char *filename, unsigned char *md); + +#endif /* SHA_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/tbbr/tbb_cert.h b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/tbbr/tbb_cert.h new file mode 100644 index 0000000..21626c7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/tbbr/tbb_cert.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef TBB_CERT_H_ +#define TBB_CERT_H_ + +#include "cert.h" + +/* + * Enumerate the certificates that are used to establish the chain of trust + */ +enum { + BL2_CERT, + TRUSTED_KEY_CERT, + BL30_KEY_CERT, + BL30_CERT, + BL31_KEY_CERT, + BL31_CERT, + BL32_KEY_CERT, + BL32_CERT, + BL33_KEY_CERT, + BL33_CERT +}; + +#endif /* TBB_CERT_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/tbbr/tbb_ext.h b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/tbbr/tbb_ext.h new file mode 100644 index 0000000..03b12d7 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/tbbr/tbb_ext.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef TBB_EXT_H_ +#define TBB_EXT_H_ + +#include "ext.h" + +/* TBBR extensions */ +enum { + TZ_FW_NVCOUNTER_EXT, + NTZ_FW_NVCOUNTER_EXT, + BL2_HASH_EXT, + TZ_WORLD_PK_EXT, + NTZ_WORLD_PK_EXT, + BL31_CONTENT_CERT_PK_EXT, + BL31_HASH_EXT, + BL30_CONTENT_CERT_PK_EXT, + BL30_HASH_EXT, + BL32_CONTENT_CERT_PK_EXT, + BL32_HASH_EXT, + BL33_CONTENT_CERT_PK_EXT, + BL33_HASH_EXT +}; + +#endif /* TBB_EXT_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/tbbr/tbb_key.h b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/tbbr/tbb_key.h new file mode 100644 index 0000000..1590309 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/include/tbbr/tbb_key.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef TBB_KEY_H_ +#define TBB_KEY_H_ + +#include "key.h" + +/* + * Enumerate the keys that are used to establish the chain of trust + */ +enum { + ROT_KEY, + TRUSTED_WORLD_KEY, + NON_TRUSTED_WORLD_KEY, + BL30_KEY, + BL31_KEY, + BL32_KEY, + BL33_KEY +}; + +#endif /* TBB_KEY_H_ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/cert.c b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/cert.c new file mode 100644 index 0000000..e58b10e --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/cert.c @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "cert.h" +#include "debug.h" +#include "key.h" +#include "platform_oid.h" +#include "sha.h" + +#define SERIAL_RAND_BITS 64 + +int rand_serial(BIGNUM *b, ASN1_INTEGER *ai) +{ + BIGNUM *btmp; + int ret = 0; + if (b) + btmp = b; + else + btmp = BN_new(); + + if (!btmp) + return 0; + + if (!BN_pseudo_rand(btmp, SERIAL_RAND_BITS, 0, 0)) + goto error; + if (ai && !BN_to_ASN1_INTEGER(btmp, ai)) + goto error; + + ret = 1; + +error: + + if (!b) + BN_free(btmp); + + return ret; +} + +int cert_add_ext(X509 *issuer, X509 *subject, int nid, char *value) +{ + X509_EXTENSION *ex; + X509V3_CTX ctx; + + /* No configuration database */ + X509V3_set_ctx_nodb(&ctx); + + /* Set issuer and subject certificates in the context */ + X509V3_set_ctx(&ctx, issuer, subject, NULL, NULL, 0); + ex = X509V3_EXT_conf_nid(NULL, &ctx, nid, value); + if (!ex) { + ERR_print_errors_fp(stdout); + return 0; + } + + X509_add_ext(subject, ex, -1); + X509_EXTENSION_free(ex); + + return 1; +} + + +int cert_new(cert_t *cert, int days, int ca, STACK_OF(X509_EXTENSION) * sk) +{ + EVP_PKEY *pkey = keys[cert->key].key; + cert_t *issuer_cert = &certs[cert->issuer]; + EVP_PKEY *ikey = keys[issuer_cert->key].key; + X509 *issuer = issuer_cert->x; + X509 *x = NULL; + X509_EXTENSION *ex = NULL; + X509_NAME *name = NULL; + ASN1_INTEGER *sno = NULL; + int i, num; + + /* Create the certificate structure */ + x = X509_new(); + if (!x) { + return 0; + } + + /* If we do not have a key, use the issuer key (the certificate will + * become self signed). This happens in content certificates. */ + if (!pkey) { + pkey = ikey; + } + + /* If we do not have an issuer certificate, use our own (the certificate + * will become self signed) */ + if (!issuer) { + issuer = x; + } + + /* x509.v3 */ + X509_set_version(x, 2); + + /* Random serial number */ + sno = ASN1_INTEGER_new(); + rand_serial(NULL, sno); + X509_set_serialNumber(x, sno); + ASN1_INTEGER_free(sno); + + X509_gmtime_adj(X509_get_notBefore(x), 0); + X509_gmtime_adj(X509_get_notAfter(x), (long)60*60*24*days); + X509_set_pubkey(x, pkey); + + /* Subject name */ + name = X509_get_subject_name(x); + X509_NAME_add_entry_by_txt(name, "CN", MBSTRING_ASC, + (const unsigned char *)cert->cn, -1, -1, 0); + X509_set_subject_name(x, name); + + /* Issuer name */ + name = X509_get_issuer_name(x); + X509_NAME_add_entry_by_txt(name, "CN", MBSTRING_ASC, + (const unsigned char *)issuer_cert->cn, -1, -1, 0); + X509_set_issuer_name(x, name); + + /* Add various extensions: standard extensions */ + cert_add_ext(issuer, x, NID_subject_key_identifier, "hash"); + cert_add_ext(issuer, x, NID_authority_key_identifier, "keyid:always"); + if (ca) { + cert_add_ext(issuer, x, NID_basic_constraints, "CA:TRUE"); + cert_add_ext(issuer, x, NID_key_usage, "keyCertSign"); + } else { + cert_add_ext(issuer, x, NID_basic_constraints, "CA:FALSE"); + } + + /* Add custom extensions */ + if (sk != NULL) { + num = sk_X509_EXTENSION_num(sk); + for (i = 0; i < num; i++) { + ex = sk_X509_EXTENSION_value(sk, i); + X509_add_ext(x, ex, -1); + } + } + + /* Sign the certificate with the issuer key */ + if (!X509_sign(x, ikey, EVP_sha256())) { + ERR_print_errors_fp(stdout); + return 0; + } + + cert->x = x; + return 1; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/ext.c b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/ext.c new file mode 100644 index 0000000..6d09837 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/ext.c @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ext.h" + +DECLARE_ASN1_ITEM(ASN1_INTEGER) +DECLARE_ASN1_ITEM(X509_ALGOR) +DECLARE_ASN1_ITEM(ASN1_OCTET_STRING) + +typedef struct { + X509_ALGOR *hashAlgorithm; + ASN1_OCTET_STRING *dataHash; +} HASH; + +ASN1_SEQUENCE(HASH) = { + ASN1_SIMPLE(HASH, hashAlgorithm, X509_ALGOR), + ASN1_SIMPLE(HASH, dataHash, ASN1_OCTET_STRING), +} ASN1_SEQUENCE_END(HASH) + +DECLARE_ASN1_FUNCTIONS(HASH) +IMPLEMENT_ASN1_FUNCTIONS(HASH) + +/* + * This function adds the TBB extensions to the internal extension list + * maintained by OpenSSL so they can be used later. + * + * It also initializes the methods to print the contents of the extension. If an + * alias is specified in the TBB extension, we reuse the methods of the alias. + * Otherwise, only methods for V_ASN1_INTEGER and V_ASN1_OCTET_STRING are + * provided. Any other type will be printed as a raw ascii string. + * + * Return: 0 = success, Otherwise: error + */ +int ext_register(ext_t *exts) +{ + ext_t *ext; + X509V3_EXT_METHOD *m; + int i = 0, nid, ret; + + while ((ext = &exts[i++]) && ext->oid) { + nid = OBJ_create(ext->oid, ext->sn, ext->ln); + if (ext->alias) { + X509V3_EXT_add_alias(nid, ext->alias); + } else { + m = &ext->method; + memset(m, 0x0, sizeof(X509V3_EXT_METHOD)); + switch (ext->asn1_type) { + case V_ASN1_INTEGER: + m->it = ASN1_ITEM_ref(ASN1_INTEGER); + m->i2s = (X509V3_EXT_I2S)i2s_ASN1_INTEGER; + m->s2i = (X509V3_EXT_S2I)s2i_ASN1_INTEGER; + break; + case V_ASN1_OCTET_STRING: + m->it = ASN1_ITEM_ref(ASN1_OCTET_STRING); + m->i2s = (X509V3_EXT_I2S)i2s_ASN1_OCTET_STRING; + m->s2i = (X509V3_EXT_S2I)s2i_ASN1_OCTET_STRING; + break; + default: + continue; + } + m->ext_nid = nid; + ret = X509V3_EXT_add(m); + if (!ret) { + ERR_print_errors_fp(stdout); + return 1; + } + } + } + return 0; +} + +/* + * Create a new extension + * + * Extension ::= SEQUENCE { + * id OBJECT IDENTIFIER, + * critical BOOLEAN DEFAULT FALSE, + * value OCTET STRING } + * + * Parameters: + * pex: OpenSSL extension pointer (output parameter) + * nid: extension identifier + * crit: extension critical (EXT_NON_CRIT, EXT_CRIT) + * data: extension data. This data will be encapsulated in an Octet String + * + * Return: Extension address, NULL if error + */ +static +X509_EXTENSION *ext_new(int nid, int crit, unsigned char *data, int len) +{ + X509_EXTENSION *ex; + ASN1_OCTET_STRING *ext_data; + + /* Octet string containing the extension data */ + ext_data = ASN1_OCTET_STRING_new(); + ASN1_OCTET_STRING_set(ext_data, data, len); + + /* Create the extension */ + ex = X509_EXTENSION_create_by_NID(NULL, nid, crit, ext_data); + + /* The extension makes a copy of the data, so we can free this object */ + ASN1_OCTET_STRING_free(ext_data); + + return ex; +} + +/* + * Creates a x509v3 extension containing a hash + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm AlgorithmIdentifier, + * digest OCTET STRING + * } + * + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL + * } + * + * Parameters: + * nid: extension identifier + * crit: extension critical (EXT_NON_CRIT, EXT_CRIT) + * md: hash algorithm + * buf: pointer to the buffer that contains the hash + * len: size of the hash in bytes + * + * Return: Extension address, NULL if error + */ +X509_EXTENSION *ext_new_hash(int nid, int crit, const EVP_MD *md, + unsigned char *buf, size_t len) +{ + X509_EXTENSION *ex = NULL; + ASN1_OCTET_STRING *octet = NULL; + HASH *hash = NULL; + ASN1_OBJECT *algorithm = NULL; + X509_ALGOR *x509_algor = NULL; + unsigned char *p = NULL; + int sz = -1; + + /* OBJECT_IDENTIFIER with hash algorithm */ + algorithm = OBJ_nid2obj(md->type); + if (algorithm == NULL) { + return NULL; + } + + /* Create X509_ALGOR */ + x509_algor = X509_ALGOR_new(); + if (x509_algor == NULL) { + return NULL; + } + x509_algor->algorithm = algorithm; + x509_algor->parameter = ASN1_TYPE_new(); + ASN1_TYPE_set(x509_algor->parameter, V_ASN1_NULL, NULL); + + /* OCTET_STRING with the actual hash */ + octet = ASN1_OCTET_STRING_new(); + if (octet == NULL) { + X509_ALGOR_free(x509_algor); + return NULL; + } + ASN1_OCTET_STRING_set(octet, buf, len); + + /* HASH structure containing algorithm + hash */ + hash = HASH_new(); + if (hash == NULL) { + ASN1_OCTET_STRING_free(octet); + X509_ALGOR_free(x509_algor); + return NULL; + } + hash->hashAlgorithm = x509_algor; + hash->dataHash = octet; + + /* DER encoded HASH */ + sz = i2d_HASH(hash, &p); + if ((sz <= 0) || (p == NULL)) { + HASH_free(hash); + X509_ALGOR_free(x509_algor); + return NULL; + } + + /* Create the extension */ + ex = ext_new(nid, crit, p, sz); + + /* Clean up */ + OPENSSL_free(p); + HASH_free(hash); + + return ex; +} + +/* + * Creates a x509v3 extension containing a nvcounter encapsulated in an ASN1 + * Integer + * + * Parameters: + * pex: OpenSSL extension pointer (output parameter) + * nid: extension identifier + * crit: extension critical (EXT_NON_CRIT, EXT_CRIT) + * value: nvcounter value + * + * Return: Extension address, NULL if error + */ +X509_EXTENSION *ext_new_nvcounter(int nid, int crit, int value) +{ + X509_EXTENSION *ex = NULL; + ASN1_INTEGER *counter = NULL; + unsigned char *p = NULL; + int sz = -1; + + /* Encode counter */ + counter = ASN1_INTEGER_new(); + ASN1_INTEGER_set(counter, value); + sz = i2d_ASN1_INTEGER(counter, NULL); + i2d_ASN1_INTEGER(counter, &p); + + /* Create the extension */ + ex = ext_new(nid, crit, p, sz); + + /* Free objects */ + OPENSSL_free(p); + ASN1_INTEGER_free(counter); + + return ex; +} + +/* + * Creates a x509v3 extension containing a public key in DER format: + * + * SubjectPublicKeyInfo ::= SEQUENCE { + * algorithm AlgorithmIdentifier, + * subjectPublicKey BIT STRING } + * + * Parameters: + * pex: OpenSSL extension pointer (output parameter) + * nid: extension identifier + * crit: extension critical (EXT_NON_CRIT, EXT_CRIT) + * k: key + * + * Return: Extension address, NULL if error + */ +X509_EXTENSION *ext_new_key(int nid, int crit, EVP_PKEY *k) +{ + X509_EXTENSION *ex = NULL; + unsigned char *p = NULL; + int sz = -1; + + /* Encode key */ + BIO *mem = BIO_new(BIO_s_mem()); + if (i2d_PUBKEY_bio(mem, k) <= 0) { + ERR_print_errors_fp(stderr); + return NULL; + } + p = (unsigned char *)OPENSSL_malloc(4096); + sz = BIO_read(mem, p, 4096); + + /* Create the extension */ + ex = ext_new(nid, crit, p, sz); + + /* Clean up */ + OPENSSL_free(p); + + return ex; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/key.c b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/key.c new file mode 100644 index 0000000..6072d9c --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/key.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include "cert.h" +#include "debug.h" +#include "key.h" +#include "platform_oid.h" +#include "sha.h" + +#define MAX_FILENAME_LEN 1024 + +/* + * Create a new key container + */ +static int key_new(key_t *key) +{ + /* Create key pair container */ + key->key = EVP_PKEY_new(); + if (key->key == NULL) { + return 0; + } + + return 1; +} + +static int key_create_rsa(key_t *key) +{ + RSA *rsa = NULL; + + rsa = RSA_generate_key(RSA_KEY_BITS, RSA_F4, NULL, NULL); + if (rsa == NULL) { + printf("Cannot create RSA key\n"); + goto err; + } + if (!EVP_PKEY_assign_RSA(key->key, rsa)) { + printf("Cannot assign RSA key\n"); + goto err; + } + + return 1; +err: + RSA_free(rsa); + return 0; +} + +#ifndef OPENSSL_NO_EC +static int key_create_ecdsa(key_t *key) +{ + EC_KEY *ec = NULL; + + ec = EC_KEY_new_by_curve_name(NID_X9_62_prime256v1); + if (ec == NULL) { + printf("Cannot create EC key\n"); + goto err; + } + if (!EC_KEY_generate_key(ec)) { + printf("Cannot generate EC key\n"); + goto err; + } + EC_KEY_set_flags(ec, EC_PKEY_NO_PARAMETERS); + EC_KEY_set_asn1_flag(ec, OPENSSL_EC_NAMED_CURVE); + if (!EVP_PKEY_assign_EC_KEY(key->key, ec)) { + printf("Cannot assign EC key\n"); + goto err; + } + + return 1; +err: + EC_KEY_free(ec); + return 0; +} +#endif /* OPENSSL_NO_EC */ + +typedef int (*key_create_fn_t)(key_t *key); +static const key_create_fn_t key_create_fn[KEY_ALG_MAX_NUM] = { + key_create_rsa, +#ifndef OPENSSL_NO_EC + key_create_ecdsa, +#endif /* OPENSSL_NO_EC */ +}; + +int key_create(key_t *key, int type) +{ + if (type >= KEY_ALG_MAX_NUM) { + printf("Invalid key type\n"); + return 0; + } + + /* Create OpenSSL key container */ + if (!key_new(key)) { + return 0; + } + + if (key_create_fn[type]) { + return key_create_fn[type](key); + } + + return 0; +} + +int key_load(key_t *key, unsigned int *err_code) +{ + FILE *fp = NULL; + EVP_PKEY *k = NULL; + + /* Create OpenSSL key container */ + if (!key_new(key)) { + *err_code = KEY_ERR_MALLOC; + return 0; + } + + if (key->fn) { + /* Load key from file */ + fp = fopen(key->fn, "r"); + if (fp) { + k = PEM_read_PrivateKey(fp, &key->key, NULL, NULL); + fclose(fp); + if (k) { + *err_code = KEY_ERR_NONE; + return 1; + } else { + ERROR("Cannot load key from %s\n", key->fn); + *err_code = KEY_ERR_LOAD; + } + } else { + WARN("Cannot open file %s\n", key->fn); + *err_code = KEY_ERR_OPEN; + } + } else { + WARN("Key filename not specified\n"); + *err_code = KEY_ERR_FILENAME; + } + + return 0; +} + +int key_store(key_t *key) +{ + FILE *fp = NULL; + + if (key->fn) { + fp = fopen(key->fn, "w"); + if (fp) { + PEM_write_PrivateKey(fp, key->key, + NULL, NULL, 0, NULL, NULL); + fclose(fp); + return 1; + } else { + ERROR("Cannot create file %s\n", key->fn); + } + } else { + ERROR("Key filename not specified\n"); + } + + return 0; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/main.c b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/main.c new file mode 100644 index 0000000..29bf452 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/main.c @@ -0,0 +1,569 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "cert.h" +#include "debug.h" +#include "ext.h" +#include "key.h" +#include "platform_oid.h" +#include "sha.h" +#include "tbbr/tbb_ext.h" +#include "tbbr/tbb_cert.h" +#include "tbbr/tbb_key.h" + +/* + * Helper macros to simplify the code. This macro assigns the return value of + * the 'fn' function to 'v' and exits if the value is NULL. + */ +#define CHECK_NULL(v, fn) \ + do { \ + v = fn; \ + if (v == NULL) { \ + ERROR("NULL object at %s:%d\n", __FILE__, __LINE__); \ + exit(1); \ + } \ + } while (0) + +/* + * This macro assigns the NID corresponding to 'oid' to 'v' and exits if the + * NID is undefined. + */ +#define CHECK_OID(v, oid) \ + do { \ + v = OBJ_txt2nid(oid); \ + if (v == NID_undef) { \ + ERROR("Cannot find TBB extension %s\n", oid); \ + exit(1); \ + } \ + } while (0) + +#define MAX_FILENAME_LEN 1024 +#define VAL_DAYS 7300 +#define ID_TO_BIT_MASK(id) (1 << id) +#define NUM_ELEM(x) ((sizeof(x)) / (sizeof(x[0]))) + +/* Files */ +enum { + /* Image file names (inputs) */ + BL2_ID = 0, + BL30_ID, + BL31_ID, + BL32_ID, + BL33_ID, + /* Certificate file names (outputs) */ + BL2_CERT_ID, + TRUSTED_KEY_CERT_ID, + BL30_KEY_CERT_ID, + BL30_CERT_ID, + BL31_KEY_CERT_ID, + BL31_CERT_ID, + BL32_KEY_CERT_ID, + BL32_CERT_ID, + BL33_KEY_CERT_ID, + BL33_CERT_ID, + /* Key file names (input/output) */ + ROT_KEY_ID, + TRUSTED_WORLD_KEY_ID, + NON_TRUSTED_WORLD_KEY_ID, + BL30_KEY_ID, + BL31_KEY_ID, + BL32_KEY_ID, + BL33_KEY_ID, + NUM_OPTS +}; + +/* Global options */ +static int key_alg; +static int new_keys; +static int save_keys; +static int print_cert; +static int bl30_present; +static int bl32_present; + +/* Info messages created in the Makefile */ +extern const char build_msg[]; +extern const char platform_msg[]; + + +static char *strdup(const char *str) +{ + int n = strlen(str) + 1; + char *dup = malloc(n); + if (dup) { + strcpy(dup, str); + } + return dup; +} + +static const char *key_algs_str[] = { + [KEY_ALG_RSA] = "rsa", +#ifndef OPENSSL_NO_EC + [KEY_ALG_ECDSA] = "ecdsa" +#endif /* OPENSSL_NO_EC */ +}; + +/* Command line options */ +static const struct option long_opt[] = { + /* Binary images */ + {"bl2", required_argument, 0, BL2_ID}, + {"bl30", required_argument, 0, BL30_ID}, + {"bl31", required_argument, 0, BL31_ID}, + {"bl32", required_argument, 0, BL32_ID}, + {"bl33", required_argument, 0, BL33_ID}, + /* Certificate files */ + {"bl2-cert", required_argument, 0, BL2_CERT_ID}, + {"trusted-key-cert", required_argument, 0, TRUSTED_KEY_CERT_ID}, + {"bl30-key-cert", required_argument, 0, BL30_KEY_CERT_ID}, + {"bl30-cert", required_argument, 0, BL30_CERT_ID}, + {"bl31-key-cert", required_argument, 0, BL31_KEY_CERT_ID}, + {"bl31-cert", required_argument, 0, BL31_CERT_ID}, + {"bl32-key-cert", required_argument, 0, BL32_KEY_CERT_ID}, + {"bl32-cert", required_argument, 0, BL32_CERT_ID}, + {"bl33-key-cert", required_argument, 0, BL33_KEY_CERT_ID}, + {"bl33-cert", required_argument, 0, BL33_CERT_ID}, + /* Private key files */ + {"rot-key", required_argument, 0, ROT_KEY_ID}, + {"trusted-world-key", required_argument, 0, TRUSTED_WORLD_KEY_ID}, + {"non-trusted-world-key", required_argument, 0, NON_TRUSTED_WORLD_KEY_ID}, + {"bl30-key", required_argument, 0, BL30_KEY_ID}, + {"bl31-key", required_argument, 0, BL31_KEY_ID}, + {"bl32-key", required_argument, 0, BL32_KEY_ID}, + {"bl33-key", required_argument, 0, BL33_KEY_ID}, + /* Common options */ + {"key-alg", required_argument, 0, 'a'}, + {"help", no_argument, 0, 'h'}, + {"save-keys", no_argument, 0, 'k'}, + {"new-chain", no_argument, 0, 'n'}, + {"print-cert", no_argument, 0, 'p'}, + {0, 0, 0, 0} +}; + +static void print_help(const char *cmd) +{ + int i = 0; + printf("\n\n"); + printf("The certificate generation tool loads the binary images and\n" + "optionally the RSA keys, and outputs the key and content\n" + "certificates properly signed to implement the chain of trust.\n" + "If keys are provided, they must be in PEM format.\n" + "Certificates are generated in DER format.\n"); + printf("\n"); + printf("Usage:\n\n"); + printf(" %s [-hknp] \\\n", cmd); + for (i = 0; i < NUM_OPTS; i++) { + printf(" --%s \\\n", long_opt[i].name); + } + printf("\n"); + printf("-a Key algorithm: rsa (default), ecdsa\n"); + printf("-h Print help and exit\n"); + printf("-k Save key pairs into files. Filenames must be provided\n"); + printf("-n Generate new key pairs if no key files are provided\n"); + printf("-p Print the certificates in the standard output\n"); + printf("\n"); + + exit(0); +} + +static int get_key_alg(const char *key_alg_str) +{ + int i; + + for (i = 0 ; i < NUM_ELEM(key_algs_str) ; i++) { + if (0 == strcmp(key_alg_str, key_algs_str[i])) { + return i; + } + } + + return -1; +} + +static void check_cmd_params(void) +{ + /* Only save new keys */ + if (save_keys && !new_keys) { + ERROR("Only new keys can be saved to disk\n"); + exit(1); + } + + /* BL2, BL31 and BL33 are mandatory */ + if (extensions[BL2_HASH_EXT].data.fn == NULL) { + ERROR("BL2 image not specified\n"); + exit(1); + } + + if (extensions[BL31_HASH_EXT].data.fn == NULL) { + ERROR("BL31 image not specified\n"); + exit(1); + } + + if (extensions[BL33_HASH_EXT].data.fn == NULL) { + ERROR("BL33 image not specified\n"); + exit(1); + } + + /* BL30 and BL32 are optional */ + if (extensions[BL30_HASH_EXT].data.fn != NULL) { + bl30_present = 1; + } + + if (extensions[BL32_HASH_EXT].data.fn != NULL) { + bl32_present = 1; + } + + /* TODO: Certificate filenames */ + + /* Filenames to store keys must be specified */ + if (save_keys || !new_keys) { + if (keys[ROT_KEY].fn == NULL) { + ERROR("ROT key not specified\n"); + exit(1); + } + + if (keys[TRUSTED_WORLD_KEY].fn == NULL) { + ERROR("Trusted World key not specified\n"); + exit(1); + } + + if (keys[NON_TRUSTED_WORLD_KEY].fn == NULL) { + ERROR("Non-trusted World key not specified\n"); + exit(1); + } + + if (keys[BL31_KEY].fn == NULL) { + ERROR("BL31 key not specified\n"); + exit(1); + } + + if (keys[BL33_KEY].fn == NULL) { + ERROR("BL33 key not specified\n"); + exit(1); + } + + if (bl30_present && (keys[BL30_KEY].fn == NULL)) { + ERROR("BL30 key not specified\n"); + exit(1); + } + + if (bl32_present && (keys[BL32_KEY].fn == NULL)) { + ERROR("BL32 key not specified\n"); + exit(1); + } + } +} + +int main(int argc, char *argv[]) +{ + STACK_OF(X509_EXTENSION) * sk = NULL; + X509_EXTENSION *cert_ext = NULL; + ext_t *ext = NULL; + cert_t *cert; + FILE *file = NULL; + int i, j, ext_nid; + int c, opt_idx = 0; + unsigned int err_code; + unsigned char md[SHA256_DIGEST_LENGTH]; + const EVP_MD *md_info; + + NOTICE("CoT Generation Tool: %s\n", build_msg); + NOTICE("Target platform: %s\n", platform_msg); + + /* Set default options */ + key_alg = KEY_ALG_RSA; + + while (1) { + /* getopt_long stores the option index here. */ + c = getopt_long(argc, argv, "ahknp", long_opt, &opt_idx); + + /* Detect the end of the options. */ + if (c == -1) { + break; + } + + switch (c) { + case 'a': + key_alg = get_key_alg(optarg); + if (key_alg < 0) { + ERROR("Invalid key algorithm '%s'\n", optarg); + exit(1); + } + break; + case 'h': + print_help(argv[0]); + break; + case 'k': + save_keys = 1; + break; + case 'n': + new_keys = 1; + break; + case 'p': + print_cert = 1; + break; + case BL2_ID: + extensions[BL2_HASH_EXT].data.fn = strdup(optarg); + break; + case BL30_ID: + extensions[BL30_HASH_EXT].data.fn = strdup(optarg); + break; + case BL31_ID: + extensions[BL31_HASH_EXT].data.fn = strdup(optarg); + break; + case BL32_ID: + extensions[BL32_HASH_EXT].data.fn = strdup(optarg); + break; + case BL33_ID: + extensions[BL33_HASH_EXT].data.fn = strdup(optarg); + break; + case BL2_CERT_ID: + certs[BL2_CERT].fn = strdup(optarg); + break; + case TRUSTED_KEY_CERT_ID: + certs[TRUSTED_KEY_CERT].fn = strdup(optarg); + break; + case BL30_KEY_CERT_ID: + certs[BL30_KEY_CERT].fn = strdup(optarg); + break; + case BL30_CERT_ID: + certs[BL30_CERT].fn = strdup(optarg); + break; + case BL31_KEY_CERT_ID: + certs[BL31_KEY_CERT].fn = strdup(optarg); + break; + case BL31_CERT_ID: + certs[BL31_CERT].fn = strdup(optarg); + break; + case BL32_KEY_CERT_ID: + certs[BL32_KEY_CERT].fn = strdup(optarg); + break; + case BL32_CERT_ID: + certs[BL32_CERT].fn = strdup(optarg); + break; + case BL33_KEY_CERT_ID: + certs[BL33_KEY_CERT].fn = strdup(optarg); + break; + case BL33_CERT_ID: + certs[BL33_CERT].fn = strdup(optarg); + break; + case ROT_KEY_ID: + keys[ROT_KEY].fn = strdup(optarg); + break; + case TRUSTED_WORLD_KEY_ID: + keys[TRUSTED_WORLD_KEY].fn = strdup(optarg); + break; + case NON_TRUSTED_WORLD_KEY_ID: + keys[NON_TRUSTED_WORLD_KEY].fn = strdup(optarg); + break; + case BL30_KEY_ID: + keys[BL30_KEY].fn = strdup(optarg); + break; + case BL31_KEY_ID: + keys[BL31_KEY].fn = strdup(optarg); + break; + case BL32_KEY_ID: + keys[BL32_KEY].fn = strdup(optarg); + break; + case BL33_KEY_ID: + keys[BL33_KEY].fn = strdup(optarg); + break; + case '?': + default: + printf("%s\n", optarg); + exit(1); + } + } + + /* Check command line arguments */ + check_cmd_params(); + + /* Register the new types and OIDs for the extensions */ + if (ext_register(extensions) != 0) { + ERROR("Cannot register TBB extensions\n"); + exit(1); + } + + /* Indicate SHA256 as image hash algorithm in the certificate + * extension */ + md_info = EVP_sha256(); + + /* Load private keys from files (or generate new ones) */ + for (i = 0 ; i < num_keys ; i++) { + /* First try to load the key from disk */ + if (key_load(&keys[i], &err_code)) { + /* Key loaded successfully */ + continue; + } + + /* Key not loaded. Check the error code */ + if (err_code == KEY_ERR_MALLOC) { + /* Cannot allocate memory. Abort. */ + ERROR("Malloc error while loading '%s'\n", keys[i].fn); + exit(1); + } else if (err_code == KEY_ERR_LOAD) { + /* File exists, but it does not contain a valid private + * key. Abort. */ + ERROR("Error loading '%s'\n", keys[i].fn); + exit(1); + } + + /* File does not exist, could not be opened or no filename was + * given */ + if (new_keys) { + /* Try to create a new key */ + NOTICE("Creating new key for '%s'\n", keys[i].desc); + if (!key_create(&keys[i], key_alg)) { + ERROR("Error creating key '%s'\n", keys[i].desc); + exit(1); + } + } else { + if (err_code == KEY_ERR_OPEN) { + ERROR("Error opening '%s'\n", keys[i].fn); + } else { + ERROR("Key '%s' not specified\n", keys[i].desc); + } + exit(1); + } + } + + /* Create the certificates */ + for (i = 0 ; i < num_certs ; i++) { + + cert = &certs[i]; + + /* Create a new stack of extensions. This stack will be used + * to create the certificate */ + CHECK_NULL(sk, sk_X509_EXTENSION_new_null()); + + for (j = 0 ; j < cert->num_ext ; j++) { + + ext = &extensions[cert->ext[j]]; + + /* Get OpenSSL internal ID for this extension */ + CHECK_OID(ext_nid, ext->oid); + + /* + * Three types of extensions are currently supported: + * - EXT_TYPE_NVCOUNTER + * - EXT_TYPE_HASH + * - EXT_TYPE_PKEY + */ + switch (ext->type) { + case EXT_TYPE_NVCOUNTER: + CHECK_NULL(cert_ext, ext_new_nvcounter(ext_nid, + EXT_CRIT, ext->data.nvcounter)); + break; + case EXT_TYPE_HASH: + if (ext->data.fn == NULL) { + break; + } + if (!sha_file(ext->data.fn, md)) { + ERROR("Cannot calculate hash of %s\n", + ext->data.fn); + exit(1); + } + CHECK_NULL(cert_ext, ext_new_hash(ext_nid, + EXT_CRIT, md_info, md, + SHA256_DIGEST_LENGTH)); + break; + case EXT_TYPE_PKEY: + CHECK_NULL(cert_ext, ext_new_key(ext_nid, + EXT_CRIT, keys[ext->data.key].key)); + break; + default: + ERROR("Unknown extension type in %s\n", + cert->cn); + exit(1); + } + + /* Push the extension into the stack */ + sk_X509_EXTENSION_push(sk, cert_ext); + } + + /* Create certificate. Signed with ROT key */ + if (!cert_new(cert, VAL_DAYS, 0, sk)) { + ERROR("Cannot create %s\n", cert->cn); + exit(1); + } + + sk_X509_EXTENSION_free(sk); + } + + + /* Print the certificates */ + if (print_cert) { + for (i = 0 ; i < num_certs ; i++) { + if (!certs[i].x) { + continue; + } + printf("\n\n=====================================\n\n"); + X509_print_fp(stdout, certs[i].x); + } + } + + /* Save created certificates to files */ + for (i = 0 ; i < num_certs ; i++) { + if (certs[i].x && certs[i].fn) { + file = fopen(certs[i].fn, "w"); + if (file != NULL) { + i2d_X509_fp(file, certs[i].x); + fclose(file); + } else { + ERROR("Cannot create file %s\n", certs[i].fn); + } + } + } + + /* Save keys */ + if (save_keys) { + for (i = 0 ; i < num_keys ; i++) { + if (!key_store(&keys[i])) { + ERROR("Cannot save %s\n", keys[i].desc); + } + } + } + +#ifndef OPENSSL_NO_ENGINE + ENGINE_cleanup(); +#endif + CRYPTO_cleanup_all_ex_data(); + + return 0; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/sha.c b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/sha.c new file mode 100644 index 0000000..57026b5 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/sha.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "debug.h" + +#define BUFFER_SIZE 256 + +int sha_file(const char *filename, unsigned char *md) +{ + FILE *inFile; + SHA256_CTX shaContext; + int bytes; + unsigned char data[BUFFER_SIZE]; + + if ((filename == NULL) || (md == NULL)) { + ERROR("%s(): NULL argument\n", __FUNCTION__); + return 0; + } + + inFile = fopen(filename, "rb"); + if (inFile == NULL) { + ERROR("Cannot read %s\n", filename); + return 0; + } + + SHA256_Init(&shaContext); + while ((bytes = fread(data, 1, BUFFER_SIZE, inFile)) != 0) { + SHA256_Update(&shaContext, data, bytes); + } + SHA256_Final(md, &shaContext); + + fclose(inFile); + return 1; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/tbbr/tbb_cert.c b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/tbbr/tbb_cert.c new file mode 100644 index 0000000..d0ae836 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/tbbr/tbb_cert.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "tbbr/tbb_cert.h" +#include "tbbr/tbb_ext.h" +#include "tbbr/tbb_key.h" + +/* + * Certificates used in the chain of trust + * + * The order of the certificates must follow the enumeration specified in + * tbb_cert.h. All certificates are self-signed, so the issuer certificate + * field points to itself. + */ +static cert_t tbb_certs[] = { + [BL2_CERT] = { + .id = BL2_CERT, + .fn = NULL, + .cn = "BL2 Certificate", + .key = ROT_KEY, + .issuer = BL2_CERT, + .ext = { + BL2_HASH_EXT + }, + .num_ext = 1 + }, + [TRUSTED_KEY_CERT] = { + .id = TRUSTED_KEY_CERT, + .fn = NULL, + .cn = "Trusted Key Certificate", + .key = ROT_KEY, + .issuer = TRUSTED_KEY_CERT, + .ext = { + TZ_WORLD_PK_EXT, + NTZ_WORLD_PK_EXT + }, + .num_ext = 2 + }, + [BL30_KEY_CERT] = { + .id = BL30_KEY_CERT, + .fn = NULL, + .cn = "BL3-0 Key Certificate", + .key = TRUSTED_WORLD_KEY, + .issuer = BL30_KEY_CERT, + .ext = { + BL30_CONTENT_CERT_PK_EXT + }, + .num_ext = 1 + }, + [BL30_CERT] = { + .id = BL30_CERT, + .fn = NULL, + .cn = "BL3-0 Content Certificate", + .key = BL30_KEY, + .issuer = BL30_CERT, + .ext = { + BL30_HASH_EXT + }, + .num_ext = 1 + }, + [BL31_KEY_CERT] = { + .id = BL31_KEY_CERT, + .fn = NULL, + .cn = "BL3-1 Key Certificate", + .key = TRUSTED_WORLD_KEY, + .issuer = BL31_KEY_CERT, + .ext = { + BL31_CONTENT_CERT_PK_EXT + }, + .num_ext = 1 + }, + [BL31_CERT] = { + .id = BL31_CERT, + .fn = NULL, + .cn = "BL3-1 Content Certificate", + .key = BL31_KEY, + .issuer = BL31_CERT, + .ext = { + BL31_HASH_EXT + }, + .num_ext = 1 + }, + [BL32_KEY_CERT] = { + .id = BL32_KEY_CERT, + .fn = NULL, + .cn = "BL3-2 Key Certificate", + .key = TRUSTED_WORLD_KEY, + .issuer = BL32_KEY_CERT, + .ext = { + BL32_CONTENT_CERT_PK_EXT + }, + .num_ext = 1 + }, + [BL32_CERT] = { + .id = BL32_CERT, + .fn = NULL, + .cn = "BL3-2 Content Certificate", + .key = BL32_KEY, + .issuer = BL32_CERT, + .ext = { + BL32_HASH_EXT + }, + .num_ext = 1 + }, + [BL33_KEY_CERT] = { + .id = BL33_KEY_CERT, + .fn = NULL, + .cn = "BL3-3 Key Certificate", + .key = NON_TRUSTED_WORLD_KEY, + .issuer = BL33_KEY_CERT, + .ext = { + BL33_CONTENT_CERT_PK_EXT + }, + .num_ext = 1 + }, + [BL33_CERT] = { + .id = BL33_CERT, + .fn = NULL, + .cn = "BL3-3 Content Certificate", + .key = BL33_KEY, + .issuer = BL33_CERT, + .ext = { + BL33_HASH_EXT + }, + .num_ext = 1 + } +}; + +REGISTER_COT(tbb_certs); diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/tbbr/tbb_ext.c b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/tbbr/tbb_ext.c new file mode 100644 index 0000000..c4816df --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/tbbr/tbb_ext.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "ext.h" +#include "platform_oid.h" +#include "tbbr/tbb_ext.h" +#include "tbbr/tbb_key.h" + +/* TODO: get these values from the command line */ +#define TRUSTED_WORLD_NVCTR_VALUE 0 +#define NORMAL_WORLD_NVCTR_VALUE 0 + +static ext_t tbb_ext[] = { + [TZ_FW_NVCOUNTER_EXT] = { + .oid = TZ_FW_NVCOUNTER_OID, + .sn = "TrustedWorldNVCounter", + .ln = "Trusted World Non-Volatile counter", + .asn1_type = V_ASN1_INTEGER, + .type = EXT_TYPE_NVCOUNTER, + .data.nvcounter = TRUSTED_WORLD_NVCTR_VALUE + }, + [NTZ_FW_NVCOUNTER_EXT] = { + .oid = NTZ_FW_NVCOUNTER_OID, + .sn = "NormalWorldNVCounter", + .ln = "Normal World Non-Volatile counter", + .asn1_type = V_ASN1_INTEGER, + .type = EXT_TYPE_NVCOUNTER, + .data.nvcounter = NORMAL_WORLD_NVCTR_VALUE + }, + [BL2_HASH_EXT] = { + .oid = BL2_HASH_OID, + .sn = "TrustedBootFirmwareHash", + .ln = "Trusted Boot Firmware (BL2) hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + }, + [TZ_WORLD_PK_EXT] = { + .oid = TZ_WORLD_PK_OID, + .sn = "TrustedWorldPublicKey", + .ln = "Trusted World Public Key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .data.key = TRUSTED_WORLD_KEY + }, + [NTZ_WORLD_PK_EXT] = { + .oid = NTZ_WORLD_PK_OID, + .sn = "NonTrustedWorldPublicKey", + .ln = "Non-Trusted World Public Key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .data.key = NON_TRUSTED_WORLD_KEY + }, + [BL30_CONTENT_CERT_PK_EXT] = { + .oid = BL30_CONTENT_CERT_PK_OID, + .sn = "SCPFirmwareContentCertPK", + .ln = "SCP Firmware content certificate public key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .data.key = BL30_KEY + }, + [BL30_HASH_EXT] = { + .oid = BL30_HASH_OID, + .sn = "SCPFirmwareHash", + .ln = "SCP Firmware (BL30) hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + }, + [BL31_CONTENT_CERT_PK_EXT] = { + .oid = BL31_CONTENT_CERT_PK_OID, + .sn = "SoCFirmwareContentCertPK", + .ln = "SoC Firmware content certificate public key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .data.key = BL31_KEY + }, + [BL31_HASH_EXT] = { + .oid = BL31_HASH_OID, + .sn = "SoCAPFirmwareHash", + .ln = "SoC AP Firmware (BL31) hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + }, + [BL32_CONTENT_CERT_PK_EXT] = { + .oid = BL32_CONTENT_CERT_PK_OID, + .sn = "TrustedOSFirmwareContentCertPK", + .ln = "Trusted OS Firmware content certificate public key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .data.key = BL32_KEY + }, + [BL32_HASH_EXT] = { + .oid = BL32_HASH_OID, + .sn = "TrustedOSHash", + .ln = "Trusted OS (BL32) hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + }, + [BL33_CONTENT_CERT_PK_EXT] = { + .oid = BL33_CONTENT_CERT_PK_OID, + .sn = "NonTrustedFirmwareContentCertPK", + .ln = "Non-Trusted Firmware content certificate public key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .data.key = BL33_KEY + }, + [BL33_HASH_EXT] = { + .oid = BL33_HASH_OID, + .sn = "NonTrustedWorldBootloaderHash", + .ln = "Non-Trusted World (BL33) hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + } +}; + +REGISTER_EXTENSIONS(tbb_ext); diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/tbbr/tbb_key.c b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/tbbr/tbb_key.c new file mode 100644 index 0000000..3685559 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/cert_create/src/tbbr/tbb_key.c @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "tbbr/tbb_key.h" + +/* + * Keys used to establish the chain of trust + * + * The order of the keys must follow the enumeration specified in tbb_key.h + */ +static key_t tbb_keys[] = { + [ROT_KEY] = { + .id = ROT_KEY, + .desc = "Root Of Trust key" + }, + [TRUSTED_WORLD_KEY] = { + .id = TRUSTED_WORLD_KEY, + .desc = "Trusted World key" + }, + [NON_TRUSTED_WORLD_KEY] = { + .id = NON_TRUSTED_WORLD_KEY, + .desc = "Non Trusted World key" + }, + [BL30_KEY] = { + .id = BL30_KEY, + .desc = "BL30 key" + }, + [BL31_KEY] = { + .id = BL31_KEY, + .desc = "BL31 key" + }, + [BL32_KEY] = { + .id = BL32_KEY, + .desc = "BL32 key" + }, + [BL33_KEY] = { + .id = BL33_KEY, + .desc = "BL33 key" + } +}; + +REGISTER_KEYS(tbb_keys); diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/makefile b/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/makefile new file mode 100644 index 0000000..4f40932 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/makefile @@ -0,0 +1,103 @@ +# +# Copyright (c) 2015-2016, Renesas Electronics Corporation +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# - Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# - Neither the name of Renesas nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +################################################### +# makefile +################################################### + +#output file name +FILE_NAME_SA0 = bootparam_sa0 +FILE_NAME_SA6 = cert_header_sa6 + +OUTPUT_FILE_SA0 = $(FILE_NAME_SA0).elf +OUTPUT_FILE_SA6 = $(FILE_NAME_SA6).elf + +#object file name +OBJ_FILE_SA0 = sa0.o +OBJ_FILE_SA6 = sa6.o + +#linker script name +MEMORY_DEF_SA0 = sa0.ld.S +MEMORY_DEF_SA6 = sa6.ld.S + +################################################### + +#c compiler +CC = $(CROSS_COMPILE)gcc + +#Linker +LD = $(CROSS_COMPILE)ld + +#objcopy +objcopy = $(CROSS_COMPILE)objcopy + +#clean +CL = rm -f + +################################################### +.SUFFIXES : .s .c .o + +################################################### +# command + +.PHONY: all +all: $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA6) +################################################### +# Linker +################################################### +$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0) + $(LD) $(OBJ_FILE_SA0) \ + -T $(MEMORY_DEF_SA0) \ + -o $(OUTPUT_FILE_SA0) \ + -Map $(FILE_NAME_SA0).map \ + + $(objcopy) -O srec --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec + $(objcopy) -O binary --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin + +$(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6) + $(LD) $(OBJ_FILE_SA6) \ + -T $(MEMORY_DEF_SA6) \ + -o $(OUTPUT_FILE_SA6) \ + -Map $(FILE_NAME_SA6).map \ + + $(objcopy) -O srec --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec + $(objcopy) -O binary --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin + +################################################### +# Compile +################################################### + +%.o:../%.c + $(CC) -c -I $< -o $@ + +.PHONY: clean +clean: + $(CL) *.bin *.map *.srec *.elf *.o diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/sa0.c b/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/sa0.c new file mode 100644 index 0000000..9f0cb10 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/sa0.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +/* SA0 */ +/* 0x00000000 */ +const unsigned int __attribute__ ((section (".sa0_bootrom"))) bootrom_paramA = 0x00000100; +/* 0x00000C00 */ +/* 0x00000D54 */ +const unsigned int __attribute__ ((section (".sa0_bl2cert_addr"))) bl2cert_addr = 0xE6302000; +/* 0x00000E64 */ +const unsigned int __attribute__ ((section (".sa0_bl2cert_size"))) bl2cert_size = 0x00008000; + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/sa0.ld.S b/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/sa0.ld.S new file mode 100644 index 0000000..55a0eee --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/sa0.ld.S @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +SECTIONS +{ + . = 0x00000000; + .rodata : { + KEEP(*(.sa0_bootrom)) + . = 0x00000D54; + KEEP(*(.sa0_bl2cert_addr)) + . = 0x00000E64; + KEEP(*(.sa0_bl2cert_size)) + } + +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/sa6.c b/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/sa6.c new file mode 100644 index 0000000..8b864ec --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/sa6.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +/* SA6 */ +/* 0x00180000 */ +const unsigned int __attribute__ ((section (".sa6_image_num"))) image_num = 0x00000001; +/* 0x00180004 */ +const unsigned int __attribute__ ((section (".sa6_start_addr_1"))) start_addr_1 = 0x00640000; +/* 0x00180400 */ +/* 0x00180554 */ +const unsigned int __attribute__ ((section (".sa6_bl31cert_addr"))) bl31cert_addr = 0x44000000; +/* 0x00180664 */ +const unsigned int __attribute__ ((section (".sa6_bl31cert_size"))) bl31cert_size = 0x00004000; +/* 0x00180800 */ +/* 0x00180954 */ +const unsigned int __attribute__ ((section (".sa6_bl32cert_addr"))) bl32cert_addr = 0x44100000; +/* 0x00180A64 */ +const unsigned int __attribute__ ((section (".sa6_bl32cert_size"))) bl32cert_size = 0x00020000; +/* 0x00180C00 */ +/* 0x00180D54 */ +const unsigned int __attribute__ ((section (".sa6_bl33cert_addr"))) bl33cert_addr = 0x49000000; +/* 0x00180E64 */ +const unsigned int __attribute__ ((section (".sa6_bl33cert_size"))) bl33cert_size = 0x00040000; + diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/sa6.ld.S b/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/sa6.ld.S new file mode 100644 index 0000000..98569cb --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/dummy_create/sa6.ld.S @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +SECTIONS +{ + . = 0x00000000; + .rodata : { + KEEP(*(.sa6_image_num)) + . = 0x00000004; + KEEP(*(.sa6_start_addr_1)) + . = 0x00000554; + KEEP(*(.sa6_bl31cert_addr)) + . = 0x00000664; + KEEP(*(.sa6_bl31cert_size)) + . = 0x00000954; + KEEP(*(.sa6_bl32cert_addr)) + . = 0x00000A64; + KEEP(*(.sa6_bl32cert_size)) + . = 0x00000D54; + KEEP(*(.sa6_bl33cert_addr)) + . = 0x00000E64; + KEEP(*(.sa6_bl33cert_size)) + } + +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/Makefile b/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/Makefile new file mode 100644 index 0000000..c72bae5 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/Makefile @@ -0,0 +1,65 @@ +# +# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +PROJECT = fip_create +OBJECTS = fip_create.o + +CFLAGS = -Wall -Werror -pedantic -std=c99 +ifeq (${DEBUG},1) + CFLAGS += -g -O0 -DDEBUG +else + CFLAGS += -O2 +endif + +# Make soft links and include from local directory otherwise wrong headers +# could get pulled in from firmware tree. +INCLUDE_PATHS = -I. + +CC := gcc +RM := rm -rf + +.PHONY: all clean + +all: ${PROJECT} + +${PROJECT}: ${OBJECTS} Makefile + @echo " LD $@" + ${Q}${CC} ${OBJECTS} -o $@ + @echo + @echo "Built $@ successfully" + @echo + +%.o: %.c %.h Makefile + @echo " CC $<" + ${Q}${CC} -c ${CFLAGS} ${INCLUDE_PATHS} $< -o $@ + +clean: + ${Q}${RM} ${PROJECT} + ${Q}${RM} ${OBJECTS} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/fip_create.c b/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/fip_create.c new file mode 100644 index 0000000..c6869f9 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/fip_create.c @@ -0,0 +1,695 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include /* getopt_long() is a GNU extention */ +#include +#include +#include +#include +#include +#include "fip_create.h" +#include "firmware_image_package.h" + +/* Values returned by getopt() as part of the command line parsing */ +#define OPT_TOC_ENTRY 0 +#define OPT_DUMP 1 +#define OPT_HELP 2 + +file_info_t files[MAX_FILES]; +unsigned file_info_count = 0; +uuid_t uuid_null = {0}; + +/* + * TODO: Add ability to specify and flag different file types. + * Add flags to the toc_entry? + * const char* format_type_str[] = { "RAW", "ELF", "PIC" }; + */ + +/* The images used depends on the platform. */ +static entry_lookup_list_t toc_entry_lookup_list[] = { + { "Trusted Boot Firmware BL2", UUID_TRUSTED_BOOT_FIRMWARE_BL2, + "bl2", NULL, FLAG_FILENAME }, + { "SCP Firmware BL3-0", UUID_SCP_FIRMWARE_BL30, + "bl30", NULL, FLAG_FILENAME}, + { "EL3 Runtime Firmware BL3-1", UUID_EL3_RUNTIME_FIRMWARE_BL31, + "bl31", NULL, FLAG_FILENAME}, + { "Secure Payload BL3-2 (Trusted OS)", UUID_SECURE_PAYLOAD_BL32, + "bl32", NULL, FLAG_FILENAME}, + { "Non-Trusted Firmware BL3-3", UUID_NON_TRUSTED_FIRMWARE_BL33, + "bl33", NULL, FLAG_FILENAME}, + /* Key Certificates */ + { "Root Of Trust key certificate", UUID_ROT_KEY_CERT, + "rot-cert", NULL, FLAG_FILENAME }, + { "Trusted key certificate", UUID_TRUSTED_KEY_CERT, + "trusted-key-cert", NULL, FLAG_FILENAME}, + { "SCP Firmware BL3-0 key certificate", UUID_SCP_FIRMWARE_BL30_KEY_CERT, + "bl30-key-cert", NULL, FLAG_FILENAME}, + { "EL3 Runtime Firmware BL3-1 key certificate", UUID_EL3_RUNTIME_FIRMWARE_BL31_KEY_CERT, + "bl31-key-cert", NULL, FLAG_FILENAME}, + { "Secure Payload BL3-2 (Trusted OS) key certificate", UUID_SECURE_PAYLOAD_BL32_KEY_CERT, + "bl32-key-cert", NULL, FLAG_FILENAME}, + { "Non-Trusted Firmware BL3-3 key certificate", UUID_NON_TRUSTED_FIRMWARE_BL33_KEY_CERT, + "bl33-key-cert", NULL, FLAG_FILENAME}, + /* Content certificates */ + { "Trusted Boot Firmware BL2 certificate", UUID_TRUSTED_BOOT_FIRMWARE_BL2_CERT, + "bl2-cert", NULL, FLAG_FILENAME }, + { "SCP Firmware BL3-0 certificate", UUID_SCP_FIRMWARE_BL30_CERT, + "bl30-cert", NULL, FLAG_FILENAME}, + { "EL3 Runtime Firmware BL3-1 certificate", UUID_EL3_RUNTIME_FIRMWARE_BL31_CERT, + "bl31-cert", NULL, FLAG_FILENAME}, + { "Secure Payload BL3-2 (Trusted OS) certificate", UUID_SECURE_PAYLOAD_BL32_CERT, + "bl32-cert", NULL, FLAG_FILENAME}, + { "Non-Trusted Firmware BL3-3 certificate", UUID_NON_TRUSTED_FIRMWARE_BL33_CERT, + "bl33-cert", NULL, FLAG_FILENAME}, + { NULL, {0}, 0 } +}; + + +/* Return 0 for equal uuids */ +static inline int compare_uuids(const uuid_t *uuid1, const uuid_t *uuid2) +{ + return memcmp(uuid1, uuid2, sizeof(uuid_t)); +} + + +static inline void copy_uuid(uuid_t *to_uuid, const uuid_t *from_uuid) +{ + memcpy(to_uuid, from_uuid, sizeof(uuid_t)); +} + + +static void print_usage(void) +{ + entry_lookup_list_t *entry = toc_entry_lookup_list; + + printf("Usage: fip_create [options] FIP_FILENAME\n\n"); + printf("\tThis tool is used to create a Firmware Image Package.\n\n"); + printf("Options:\n"); + printf("\t--help: Print this help message and exit\n"); + printf("\t--dump: Print contents of FIP\n\n"); + printf("\tComponents that can be added/updated:\n"); + for (; entry->command_line_name != NULL; entry++) { + printf("\t--%s%s\t\t%s", + entry->command_line_name, + (entry->flags & FLAG_FILENAME) ? " FILENAME" : "", + entry->name); + printf("\n"); + } +} + + +static entry_lookup_list_t *get_entry_lookup_from_uuid(const uuid_t *uuid) +{ + unsigned int lookup_index = 0; + + while (toc_entry_lookup_list[lookup_index].command_line_name != NULL) { + if (compare_uuids(&toc_entry_lookup_list[lookup_index].name_uuid, + uuid) == 0) { + return &toc_entry_lookup_list[lookup_index]; + } + lookup_index++; + } + return NULL; +} + + +static file_info_t *find_file_info_from_uuid(const uuid_t *uuid) +{ + int index; + + for (index = 0; index < file_info_count; index++) { + if (compare_uuids(&files[index].name_uuid, uuid) == 0) { + return &files[index]; + } + } + return NULL; +} + + +static int add_file_info_entry(entry_lookup_list_t *lookup_entry, char *filename) +{ + file_info_t *file_info_entry; + int error; + struct stat file_status; + bool is_new_entry = false; + + /* Check if the file already exists in the array */ + file_info_entry = find_file_info_from_uuid(&lookup_entry->name_uuid); + if (file_info_entry == NULL) { + /* The file does not exist in the current list; take the next + * one available in the file_info list. 'file_info_count' is + * incremented in case of successful update at the end of the + * function. + */ + file_info_entry = &files[file_info_count]; + is_new_entry = true; + + /* Copy the uuid for the new entry */ + copy_uuid(&file_info_entry->name_uuid, + &lookup_entry->name_uuid); + } + + /* Get the file information for entry */ + error = stat(filename, &file_status); + if (error != 0) { + printf("Error: Cannot get information for file \"%s\": %s\n", + filename, strerror(errno)); + return errno; + } + file_info_entry->filename = filename; + file_info_entry->size = (unsigned int)file_status.st_size; + file_info_entry->entry = lookup_entry; + + /* Increment the file_info counter on success if it is new file entry */ + if (is_new_entry) { + file_info_count++; + + /* Ensure we do not overflow */ + if (file_info_count > MAX_FILES) { + printf("ERROR: Too many files in Package\n"); + return 1; + } + } + + return 0; +} + + +static int write_memory_to_file(const uint8_t *start, const char *filename, + unsigned int size) +{ + FILE *stream; + unsigned int bytes_written; + + /* Write the packed file out to the filesystem */ + stream = fopen(filename, "r+"); + if (stream == NULL) { + stream = fopen(filename, "w"); + if (stream == NULL) { + printf("Error: Cannot create output file \"%s\": %s\n", + filename, strerror(errno)); + return errno; + } else { + printf("Creating \"%s\"\n", filename); + } + } else { + printf("Updating \"%s\"\n", filename); + } + + bytes_written = fwrite(start, sizeof(uint8_t), size, stream); + fclose(stream); + + if (bytes_written != size) { + printf("Error: Incorrect write for file \"%s\": Size=%u," + "Written=%u bytes.\n", filename, size, bytes_written); + return EIO; + } + + return 0; +} + + +static int read_file_to_memory(void *memory, const file_info_t *info) +{ + FILE *stream; + unsigned int bytes_read; + + /* If the file_info is defined by its filename we need to load it */ + if (info->filename) { + /* Read image from filesystem */ + stream = fopen(info->filename, "r"); + if (stream == NULL) { + printf("Error: Cannot open file \"%s\": %s\n", + info->filename, strerror(errno)); + return errno; + } + + bytes_read = (unsigned int)fread(memory, sizeof(uint8_t), + info->size, stream); + fclose(stream); + if (bytes_read != info->size) { + printf("Error: Incomplete read for file \"%s\":" + "Size=%u, Read=%u bytes.\n", info->filename, + info->size, bytes_read); + return EIO; + } + } else { + if (info->image_buffer == NULL) { + printf("ERROR: info->image_buffer = NULL\n"); + return EIO; + } + /* Copy the file_info buffer (extracted from the existing + * image package) into the new buffer. + */ + memcpy(memory, info->image_buffer, info->size); + } + + return 0; +} + + +/* Create the image package file */ +static int pack_images(const char *fip_filename) +{ + int status; + uint8_t *fip_base_address; + void *entry_address; + fip_toc_header_t *toc_header; + fip_toc_entry_t *toc_entry; + unsigned int entry_index; + unsigned int toc_size; + unsigned int fip_size; + unsigned int entry_offset_address; + unsigned int payload_size = 0; + + /* Validate filename */ + if ((fip_filename == NULL) || (strcmp(fip_filename, "") == 0)) { + return EINVAL; + } + + /* Payload size calculation */ + for (entry_index = 0; entry_index < file_info_count; entry_index++) { + payload_size += files[entry_index].size; + } + + /* Allocate memory for entire package, including the final null entry */ + toc_size = (sizeof(fip_toc_header_t) + + (sizeof(fip_toc_entry_t) * (file_info_count + 1))); + fip_size = toc_size + payload_size; + fip_base_address = malloc(fip_size); + if (fip_base_address == NULL) { + printf("Error: Can't allocate enough memory to create package." + "Process aborted.\n"); + return ENOMEM; + } + memset(fip_base_address, 0, fip_size); + + /* Create ToC Header */ + toc_header = (fip_toc_header_t *)fip_base_address; + toc_header->name = TOC_HEADER_NAME; + toc_header->serial_number = TOC_HEADER_SERIAL_NUMBER; + toc_header->flags = 0; + + toc_entry = (fip_toc_entry_t *)(fip_base_address + + sizeof(fip_toc_header_t)); + + /* Calculate the starting address of the first image, right after the + * toc header. + */ + entry_offset_address = toc_size; + entry_index = 0; + + /* Create the package in memory. */ + for (entry_index = 0; entry_index < file_info_count; entry_index++) { + entry_address = (fip_base_address + entry_offset_address); + status = read_file_to_memory(entry_address, + &files[entry_index]); + if (status != 0) { + printf("Error: While reading \"%s\" from filesystem.\n", + files[entry_index].filename); + return status; + } + + copy_uuid(&toc_entry->uuid, &files[entry_index].name_uuid); + toc_entry->offset_address = entry_offset_address; + toc_entry->size = files[entry_index].size; + toc_entry->flags = 0; + entry_offset_address += toc_entry->size; + toc_entry++; + } + + /* Add a null uuid entry to mark the end of toc entries */ + copy_uuid(&toc_entry->uuid, &uuid_null); + toc_entry->offset_address = entry_offset_address; + toc_entry->size = 0; + toc_entry->flags = 0; + + /* Save the package to file */ + status = write_memory_to_file(fip_base_address, fip_filename, fip_size); + if (status != 0) { + printf("Error: Failed while writing package to file \"%s\" " + "with status=%d.\n", fip_filename, status); + return status; + } + return 0; +} + + +static void dump_toc(void) +{ + unsigned int index = 0; + unsigned int image_offset; + unsigned int image_size = 0; + + image_offset = sizeof(fip_toc_header_t) + + (sizeof(fip_toc_entry_t) * (file_info_count + 1)); + + printf("Firmware Image Package ToC:\n"); + printf("---------------------------\n"); + for (index = 0; index < file_info_count; index++) { + if (files[index].entry) { + printf("- %s: ", files[index].entry->name); + } else { + printf("- Unknown entry: "); + } + image_size = files[index].size; + + printf("offset=0x%X, size=0x%X\n", image_offset, image_size); + image_offset += image_size; + + if (files[index].filename) { + printf(" file: '%s'\n", files[index].filename); + } + } + printf("---------------------------\n"); +} + + +/* Read and load existing package into memory. */ +static int parse_fip(const char *fip_filename) +{ + FILE *fip; + char *fip_buffer; + char *fip_buffer_end; + int fip_size, read_fip_size; + fip_toc_header_t *toc_header; + fip_toc_entry_t *toc_entry; + bool found_last_toc_entry = false; + file_info_t *file_info_entry; + int status = -1; + struct stat st; + + fip = fopen(fip_filename, "r"); + if (fip == NULL) { + /* If the fip does not exist just return, it should not be + * considered as an error. The package will be created later + */ + status = 0; + goto parse_fip_return; + } + + if (stat(fip_filename, &st) != 0) { + status = errno; + goto parse_fip_fclose; + } else { + fip_size = (int)st.st_size; + } + + /* Allocate a buffer to read the package */ + fip_buffer = (char *)malloc(fip_size); + if (fip_buffer == NULL) { + printf("ERROR: Cannot allocate %d bytes.\n", fip_size); + status = errno; + goto parse_fip_fclose; + } + fip_buffer_end = fip_buffer + fip_size; + + /* Read the file */ + read_fip_size = fread(fip_buffer, sizeof(char), fip_size, fip); + if (read_fip_size != fip_size) { + printf("ERROR: Cannot read the FIP.\n"); + status = EIO; + goto parse_fip_free; + } + fclose(fip); + fip = NULL; + + /* The package must at least contain the ToC Header */ + if (fip_size < sizeof(fip_toc_header_t)) { + printf("ERROR: Given FIP is smaller than the ToC header.\n"); + status = EINVAL; + goto parse_fip_free; + } + /* Set the ToC Header at the base of the buffer */ + toc_header = (fip_toc_header_t *)fip_buffer; + /* The first toc entry should be just after the ToC header */ + toc_entry = (fip_toc_entry_t *)(toc_header + 1); + + /* While the ToC entry is contained into the buffer */ + int cnt = 0; + while (((char *)toc_entry + sizeof(fip_toc_entry_t)) < fip_buffer_end) { + cnt++; + /* Check if the ToC Entry is the last one */ + if (compare_uuids(&toc_entry->uuid, &uuid_null) == 0) { + found_last_toc_entry = true; + status = 0; + break; + } + + /* Add the entry into file_info */ + + /* Get the new entry in the array and clear it */ + file_info_entry = &files[file_info_count++]; + memset(file_info_entry, 0, sizeof(file_info_t)); + + /* Copy the info from the ToC entry */ + copy_uuid(&file_info_entry->name_uuid, &toc_entry->uuid); + file_info_entry->image_buffer = fip_buffer + + toc_entry->offset_address; + file_info_entry->size = toc_entry->size; + + /* Check if there is a corresponding entry in lookup table */ + file_info_entry->entry = + get_entry_lookup_from_uuid(&toc_entry->uuid); + + /* Go to the next ToC entry */ + toc_entry++; + } + + if (!found_last_toc_entry) { + printf("ERROR: Given FIP does not have an end ToC entry.\n"); + status = EINVAL; + goto parse_fip_free; + } else { + /* All is well, we should not free any of the loaded images */ + goto parse_fip_fclose; + } + + parse_fip_free: + if (fip_buffer != NULL) { + free(fip_buffer); + fip_buffer = NULL; + } + + parse_fip_fclose: + if (fip != NULL) { + fclose(fip); + } + + parse_fip_return: + return status; +} + + +/* Parse all command-line options and return the FIP name if present. */ +static char *get_filename(int argc, char **argv, struct option *options) +{ + int c; + char *filename = NULL; + + /* Reset option pointer so we parse all args. starts at 1. + * The filename is the only argument that does not have an option flag. + */ + optind = 1; + while (1) { + c = getopt_long(argc, argv, "", options, NULL); + if (c == -1) + break; + + if (c == '?') { + /* Failed to parse an option. Fail. */ + return NULL; + } + } + + /* Only one argument left then it is the filename. + * We dont expect any other options + */ + if (optind + 1 == argc) + filename = argv[optind]; + + return filename; +} + + +/* Work through command-line options */ +static int parse_cmdline(int argc, char **argv, struct option *options, + int *do_pack) +{ + int c; + int status = 0; + int option_index = 0; + entry_lookup_list_t *lookup_entry; + int do_dump = 0; + + /* restart parse to process all options. starts at 1. */ + optind = 1; + while (1) { + c = getopt_long(argc, argv, "", options, &option_index); + if (c == -1) + break; + + switch (c) { + case OPT_TOC_ENTRY: + if (optarg) { + /* Does the option expect a filename. */ + lookup_entry = &toc_entry_lookup_list[option_index]; + if (lookup_entry->flags & FLAG_FILENAME) { + status = add_file_info_entry(lookup_entry, optarg); + if (status != 0) { + printf("Failed to process %s\n", + options[option_index].name); + return status; + } else { + /* Update package */ + *do_pack = 1; + } + } + } + break; + + case OPT_DUMP: + do_dump = 1; + continue; + + case OPT_HELP: + print_usage(); + exit(0); + + default: + /* Unrecognised options are caught in get_filename() */ + break; + } + } + + + /* Do not dump toc if we have an error as it could hide the error */ + if ((status == 0) && (do_dump)) { + dump_toc(); + } + + return status; + +} + +int main(int argc, char **argv) +{ + int i; + int status; + char *fip_filename; + int do_pack = 0; + + /* Clear file list table. */ + memset(files, 0, sizeof(files)); + + /* Initialise for getopt_long(). + * Use image table as defined at top of file to get options. + * Add 'dump' option, 'help' option and end marker. + */ + static struct option long_options[(sizeof(toc_entry_lookup_list)/ + sizeof(entry_lookup_list_t)) + 2]; + + for (i = 0; + /* -1 because we dont want to process end marker in toc table */ + i < sizeof(toc_entry_lookup_list)/sizeof(entry_lookup_list_t) - 1; + i++) { + long_options[i].name = toc_entry_lookup_list[i].command_line_name; + /* The only flag defined at the moment is for a FILENAME */ + long_options[i].has_arg = toc_entry_lookup_list[i].flags ? 1 : 0; + long_options[i].flag = 0; + long_options[i].val = OPT_TOC_ENTRY; + } + + /* Add '--dump' option */ + long_options[i].name = "dump"; + long_options[i].has_arg = 0; + long_options[i].flag = 0; + long_options[i].val = OPT_DUMP; + + /* Add '--help' option */ + long_options[++i].name = "help"; + long_options[i].has_arg = 0; + long_options[i].flag = 0; + long_options[i].val = OPT_HELP; + + /* Zero the last entry (required) */ + long_options[++i].name = 0; + long_options[i].has_arg = 0; + long_options[i].flag = 0; + long_options[i].val = 0; + +#ifdef DEBUG + /* Print all supported options */ + for (i = 0; i < sizeof(long_options)/sizeof(struct option); i++) { + printf("long opt (%d) : name = %s\n", i, long_options[i].name); + } +#endif /* DEBUG */ + + /* As the package may already exist and is to be updated we need to get + * the filename from the arguments and load from it. + * NOTE: As this is the first function to look at the program arguments + * it causes a failure if bad options were provided. + */ + fip_filename = get_filename(argc, argv, long_options); + + /* Try to open the file and load it into memory */ + if (fip_filename != NULL) { + status = parse_fip(fip_filename); + if (status != 0) { + return status; + } + } + + /* Work through provided program arguments and perform actions */ + status = parse_cmdline(argc, argv, long_options, &do_pack); + if (status != 0) { + return status; + }; + + if (fip_filename == NULL) { + printf("ERROR: Missing FIP filename\n"); + print_usage(); + return 0; + } + + /* Processed all command line options. Create/update the package if + * required. + */ + if (do_pack) { + status = pack_images(fip_filename); + if (status != 0) { + printf("Failed to create package (status = %d).\n", + status); + } + } + + return status; +} diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/fip_create.h b/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/fip_create.h new file mode 100644 index 0000000..3258335 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/fip_create.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FIP_CREATE_H__ +#define __FIP_CREATE_H__ + +#include +#include + +#define MAX_FILES 20 + +/* TODO: Update this number as required */ +#define TOC_HEADER_SERIAL_NUMBER 0x12345678 + +#define FLAG_FILENAME (1 << 0) + +typedef struct entry_lookup_list { + const char *name; + uuid_t name_uuid; + const char *command_line_name; + struct file_info *info; + unsigned int flags; +} entry_lookup_list_t; + +typedef struct file_info { + uuid_t name_uuid; + const char *filename; + unsigned int size; + void *image_buffer; + entry_lookup_list_t *entry; +} file_info_t; + +#endif /* __FIP_CREATE_H__ */ diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/firmware_image_package.h b/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/firmware_image_package.h new file mode 100644 index 0000000..cc61903 --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/firmware_image_package.h @@ -0,0 +1 @@ +../../include/common/firmware_image_package.h \ No newline at end of file diff --git a/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/uuid.h b/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/uuid.h new file mode 100644 index 0000000..c77762f --- /dev/null +++ b/IPL/SDK/v3m/src/Dummy_BL33/tools/fip_create/uuid.h @@ -0,0 +1 @@ +../../include/stdlib/sys/uuid.h \ No newline at end of file diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/Makefile b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/Makefile new file mode 100644 index 0000000..85b1e34 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/Makefile @@ -0,0 +1,340 @@ +# +# Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. +# + +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +INCLUDE_DIR = -Iinclude + +#output file name +FILE_NAME = cr7_loader +FILE_NAME_SA0 = bootparam_sa0 +FILE_NAME_SA3 = cert_header_sa3 + +OUTPUT_FILE = $(FILE_NAME).elf +OUTPUT_FILE_SA0 = $(FILE_NAME_SA0).elf +OUTPUT_FILE_SA3 = $(FILE_NAME_SA3).elf + +#object file name +OBJ_FILE = common/mem.o \ + common/scif.o \ + common/div.o \ + common/llsl.o \ + common/llsr.o \ + common/micro_wait.o \ + common/printf.o \ + common/dma_driver.o \ + common/rpc_driver.o \ + common/rcar_pwrc.o \ + common/cpsr_acc.o \ + common/ecc.o \ + common/swdt.o \ + common/arm_gic.o \ + common/gic_v2.o \ + common/error_output.o \ + common/report_exception.o \ + common/protection_setting.o \ + common/lifec_init.o \ + common/rom_api.o \ + common/auth.o \ + common/mfis_init.o \ + common/edc_init.o \ + common/axi_bus_timeout.o \ + common/ths_init.o \ + loader/loader.o \ + loader/loader_main.o \ + loader/rcar_version.o \ + loader/cpg_init.o \ + loader/stack.o \ + loader/rcar_addr.o + +OBJ_FILE_SA0 = tools/dummy_create/sa0.o +OBJ_FILE_SA3 = tools/dummy_create/sa3.o + + +#linker script name +MEMORY_DEF = loader/loader.ld.S +MEMORY_DEF_SA0 = tools/dummy_create/sa0.ld.S +MEMORY_DEF_SA3 = tools/dummy_create/sa3.ld.S + +################################################### + +# Debug build +DEBUG:=0 + +# LSI setting common define +RCAR_V3M:=0 +$(eval $(call add_define,RCAR_V3M)) +RCAR_CUT_10:=0 +$(eval $(call add_define,RCAR_CUT_10)) + +ifndef LSI + $(error "Error: Unknown LSI. Please use LSI= to specify the LSI") +else + ifeq (${LSI},V3M) + RCAR_LSI:=${RCAR_V3M} + else + $(error "Error: ${LSI} is not supported.") + endif + $(eval $(call add_define,RCAR_LSI)) +endif + +# Process DEBUG flag +$(eval $(call assert_boolean,DEBUG)) +$(eval $(call add_define,DEBUG)) +ifeq (${DEBUG},0) + # Use LOG_LEVEL_NOTICE by default for release builds + LOG_LEVEL:=20 +else + # Use LOG_LEVEL_INFO by default for debug builds + LOG_LEVEL:=40 + CFLAGS += -g + ASFLAGS += -g -Wa,--gdwarf-2 +endif + +# Process LOG_LEVEL flag +ifndef LOG_LEVEL +LOG_LEVEL := 20 +endif +$(eval $(call add_define,LOG_LEVEL)) + +# Process RCAR_SECURE_BOOT flag +ifndef RCAR_SECURE_BOOT +RCAR_SECURE_BOOT := 1 +endif +$(eval $(call add_define,RCAR_SECURE_BOOT)) + +# Process RCAR_DRAM_SPLIT flag +ifndef RCAR_DRAM_SPLIT +RCAR_DRAM_SPLIT := 0 +endif +$(eval $(call add_define,RCAR_DRAM_SPLIT)) + +# Process RCAR_KICK_MAIN_CPU flag +ifndef RCAR_KICK_MAIN_CPU +RCAR_KICK_MAIN_CPU := 2 +endif +$(eval $(call add_define,RCAR_KICK_MAIN_CPU)) + +# Process RCAR_SYSRAM_ECC_ENABLE flag +ifndef RCAR_SYSRAM_ECC_ENABLE +RCAR_SYSRAM_ECC_ENABLE := 0 +endif +$(eval $(call add_define,RCAR_SYSRAM_ECC_ENABLE)) + + +# Process RCAR_DRAM_ECC_ENABLE flag +ifndef RCAR_DRAM_ECC_ENABLE +RCAR_DRAM_ECC_ENABLE := 0 +endif +$(eval $(call add_define,RCAR_DRAM_ECC_ENABLE)) + +# Process ARM_GIC_ARCH flag +ARM_GIC_ARCH := 2 +$(eval $(call add_define,ARM_GIC_ARCH)) + +# Process RCAR_LIFEC_NON_SECURE_MASTER +ifndef RCAR_LIFEC_NON_SECURE_MASTER +RCAR_LIFEC_NON_SECURE_MASTER := 0 +endif +$(eval $(call add_define,RCAR_LIFEC_NON_SECURE_MASTER)) + +# Process RCAR_GEN3_ULCB flag +ifndef RCAR_GEN3_ULCB +RCAR_GEN3_ULCB := 0 +endif +$(eval $(call add_define,RCAR_GEN3_ULCB)) + +# Process ENABLE_AXI_LIFEC_SYSC flag +ifndef RCAR_DISABLE_AXI_LIFEC_SYSC +RCAR_DISABLE_AXI_LIFEC_SYSC := 1 +endif +$(eval $(call add_define,RCAR_DISABLE_AXI_LIFEC_SYSC)) + +# Process RCAR_AXI_BUS_TIMEOUT flag +ifndef RCAR_AXI_BUS_TIMEOUT +RCAR_AXI_BUS_TIMEOUT := 0 +endif +$(eval $(call add_define,RCAR_AXI_BUS_TIMEOUT)) + +# Process RCAR_REF_INT flag +ifndef RCAR_REF_INT +RCAR_REF_INT :=0 +endif +$(eval $(call add_define,RCAR_REF_INT)) + +# Process RCAR_DDR_REG_CHECK flag +ifndef RCAR_DDR_REG_CHECK +RCAR_DDR_REG_CHECK :=0 +endif +$(eval $(call add_define,RCAR_DDR_REG_CHECK)) + +# Process V3MSK_2GB flag +ifndef V3MSK_2GB +V3MSK_2GB :=0 +endif +$(eval $(call add_define,V3MSK_2GB)) + +################################################### +# pass SecureMonitor parametor +################################################### +# Process CA53_PROG1_SMONI flag +ifndef CA53_PROG1_IS_SMONI +CA53_PROG1_IS_SMONI := 1 +endif +$(eval $(call add_define,CA53_PROG1_IS_SMONI)) + +ifeq (${CA53_PROG1_IS_SMONI},1) + # STag_Smoni_EntrypointInfo parametor + ifndef CA53_PROG2_ATTR + CA53_PROG2_ATTR := 0x00000001 + endif + + ifndef CA53_PROG2_PC + CA53_PROG2_PC := 0x0000000050000000 + endif + + ifndef CA53_PROG2_SPSR + CA53_PROG2_SPSR := 0x00000000000003C5 + endif + + ifndef CA53_PROG2_ARG0 + CA53_PROG2_ARG0 := 0x0000000000000000 + endif + + ifndef CA53_PROG2_ARG1 + CA53_PROG2_ARG1 := 0x0000000000000000 + endif + + ifndef CA53_PROG2_ARG2 + CA53_PROG2_ARG2 := 0x0000000000000000 + endif + + ifndef CA53_PROG2_ARG3 + CA53_PROG2_ARG3 := 0x0000000000000000 + endif + + ifndef CA53_PROG2_ARG4 + CA53_PROG2_ARG4 := 0x0000000000000000 + endif + + ifndef CA53_PROG2_ARG5 + CA53_PROG2_ARG5 := 0x0000000000000000 + endif + + ifndef CA53_PROG2_ARG6 + CA53_PROG2_ARG6 := 0x0000000000000000 + endif + + ifndef CA53_PROG2_ARG7 + CA53_PROG2_ARG7 := 0x0000000000000000 + endif + + + $(eval $(call add_define,SMONI_ATTR)) + $(eval $(call add_define,CA53_PROG2_ATTR)) + $(eval $(call add_define,CA53_PROG2_PC)) + $(eval $(call add_define,CA53_PROG2_SPSR)) + $(eval $(call add_define,CA53_PROG2_ARG0)) + $(eval $(call add_define,CA53_PROG2_ARG1)) + $(eval $(call add_define,CA53_PROG2_ARG2)) + $(eval $(call add_define,CA53_PROG2_ARG3)) + $(eval $(call add_define,CA53_PROG2_ARG4)) + $(eval $(call add_define,CA53_PROG2_ARG5)) + $(eval $(call add_define,CA53_PROG2_ARG6)) + $(eval $(call add_define,CA53_PROG2_ARG7)) +endif + +include pfc/pfc.mk +include ddr/ddr.mk +include qos/qos.mk + +################################################### + +CC = $(CROSS_COMPILE)gcc +CPP = ${CROSS_COMPILE}cpp +AS = ${CROSS_COMPILE}gcc +AR = ${CROSS_COMPILE}ar +LD = $(CROSS_COMPILE)ld +OC = ${CROSS_COMPILE}objcopy +OD = ${CROSS_COMPILE}objdump + +ASFLAGS += -marm -march=armv7-r \ + -nostdinc -ffreestanding -Wa,--fatal-warnings \ + -Werror -Wmissing-include-dirs \ + -c -D__ASSEMBLY \ + $(INCLUDE_DIR) $(DEFINES) + +CFLAGS += -marm -march=armv7-r \ + -nostdinc -ffreestanding -Wall \ + -Werror -Wmissing-include-dirs \ + -std=c99 -c -Os \ + -ffunction-sections -fdata-sections \ + $(INCLUDE_DIR) $(DEFINES) + +LDFLAGS = --fatal-warnings -O1 --gc-sections + +BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__ + +################################################### +.SUFFIXES : .s .c .o + +################################################### +# command + +.PHONY: all +all: $(OUTPUT_FILE) $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA3) + +################################################### +# Linker +################################################### +$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE) + @echo 'const char g_build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' | \ + $(CC) $(CFLAGS) -xc - -o g_build_message.o + + $(LD) $(OBJ_FILE) g_build_message.o \ + -T $(MEMORY_DEF) \ + -o $(OUTPUT_FILE) \ + $(LDFLAGS) \ + -Map $(FILE_NAME).map + + $(OC) -O srec --srec-forceS3 $(OUTPUT_FILE) $(FILE_NAME).srec + $(OC) -O binary $(OUTPUT_FILE) $(FILE_NAME).bin + $(OD) -dx $(OUTPUT_FILE) > $(FILE_NAME).dump + +$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0) + $(LD) $(OBJ_FILE_SA0) \ + -T $(MEMORY_DEF_SA0) \ + -o $(OUTPUT_FILE_SA0) \ + -Map $(FILE_NAME_SA0).map \ + + $(OC) -O srec --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec + $(OC) -O binary --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin + +$(OUTPUT_FILE_SA3) : $(MEMORY_DEF_SA3) $(OBJ_FILE_SA3) + $(LD) $(OBJ_FILE_SA3) \ + -T $(MEMORY_DEF_SA3) \ + -o $(OUTPUT_FILE_SA3) \ + -Map $(FILE_NAME_SA3).map \ + + $(OC) -O srec --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA3) $(FILE_NAME_SA3).srec + $(OC) -O binary --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA3) $(FILE_NAME_SA3).bin + + +################################################### +# Compile +################################################### + +%.o:../%.c + $(CC) $(CFLAGS) -o $@ $< + +%.o:../%.s + $(AS) $(ASFLAGS) -o $@ $< + + +.PHONY: clean +clean: + $(RM) $(OBJ_FILE) $(OUTPUT_FILE) $(OBJ_FILE_SA0) $(OBJ_FILE_SA3) $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA3) \ + $(FILE_NAME).* $(FILE_NAME_SA0).* $(FILE_NAME_SA3).* *.o diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/arm_gic.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/arm_gic.c new file mode 100644 index 0000000..5a9631d --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/arm_gic.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/****************************************************************************** + * @file arm_gic.c + * - Version : 0.01 + * @brief GIC driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + + +#include +#include +#include +#include +#include +#include + +/* Value used to initialize Non-Secure IRQ priorities four at a time */ +#define GICD_IPRIORITYR_DEF_VAL \ + (GIC_HIGHEST_NS_PRIORITY | \ + (GIC_HIGHEST_NS_PRIORITY << 8) | \ + (GIC_HIGHEST_NS_PRIORITY << 16) | \ + (GIC_HIGHEST_NS_PRIORITY << 24)) + +static uintptr_t s_g_gicc_base; +static uintptr_t s_g_gicd_base; + +/******************************************************************************* + * Enable secure interrupts and use FIQs to route them. Disable legacy bypass + * and set the priority mask register to allow all interrupts to trickle in. + ******************************************************************************/ +void arm_gic_cpuif_setup(void) +{ + unsigned int val; + + assert(s_g_gicc_base); + val = gicc_read_iidr(s_g_gicc_base); + + /* Not used FIQ for CR7Loader * + * So do not enable FIQ */ + val = ENABLE_GRP0 /* | FIQ_EN */ | FIQ_BYP_DIS_GRP0; + val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; + + gicc_write_pmr(s_g_gicc_base, GIC_PRI_MASK); + gicc_write_ctlr(s_g_gicc_base, val); +} +/* End of function arm_gic_cpuif_setup */ + +/******************************************************************************* + * Place the cpu interface in a state where it can never make a cpu exit wfi as + * as result of an asserted interrupt. This is critical for powering down a cpu + ******************************************************************************/ +void arm_gic_cpuif_deactivate(void) +{ + unsigned int val; + + /* Disable secure, non-secure interrupts and disable their bypass */ + assert(s_g_gicc_base); + val = gicc_read_ctlr(s_g_gicc_base); + val &= ~(ENABLE_GRP0 | ENABLE_GRP1); + val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; + val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; + gicc_write_ctlr(s_g_gicc_base, val); + + val = gicc_read_iidr(s_g_gicc_base); +} +/* End of function arm_gic_cpuif_deactivate */ + +/******************************************************************************* + * Per cpu gic distributor setup which will be done by all cpus after a cold + * boot/hotplug. This marks out the secure interrupts & enables them. + ******************************************************************************/ +void arm_gic_pcpu_distif_setup(void) +{ +#if RCAR_LIFEC_NON_SECURE_MASTER + uint32_t index; + uint32_t sec_ppi_sgi_mask=0; +#endif + + assert(s_g_gicd_base); +#if RCAR_LIFEC_NON_SECURE_MASTER + /* Setup PPI priorities doing four at a time */ + for (index = 0; index < 32; index += 4) { + gicd_write_ipriorityr(s_g_gicd_base, index, + GICD_IPRIORITYR_DEF_VAL); + } +#endif + + /* + * Invert the bitmask to create a mask for non-secure PPIs and + * SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will + * update the GICR_IGROUPR0 as well in case we are running on a GICv3 + * system. This is critical if GICD_CTLR.ARE_NS=1. + */ +#if RCAR_LIFEC_NON_SECURE_MASTER + gicd_write_igroupr(s_g_gicd_base, 0, ~sec_ppi_sgi_mask); +#endif +} +/* End of function arm_gic_pcpu_distif_setup */ + +/******************************************************************************* + * Global gic distributor setup which will be done by the primary cpu after a + * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It + * then enables the secure GIC distributor interface. + ******************************************************************************/ +static void arm_gic_distif_setup(void) +{ + +#if RCAR_LIFEC_NON_SECURE_MASTER + uint32_t num_ints; + uint32_t index; +#endif + + /* + * Mark out non-secure SPI interrupts. The number of interrupts is + * calculated as 32 * (IT_LINES + 1). We do 32 at a time. + */ +#if RCAR_LIFEC_NON_SECURE_MASTER + num_ints = gicd_read_typer(s_g_gicd_base) & IT_LINES_NO_MASK; + num_ints = (num_ints + 1) << 5; + for (index = MIN_SPI_ID; index < num_ints; index += 32) + gicd_write_igroupr(s_g_gicd_base, index, ~0); + + /* Setup SPI priorities doing four at a time */ + for (index = MIN_SPI_ID; index < num_ints; index += 4) { + gicd_write_ipriorityr(s_g_gicd_base, index, + GICD_IPRIORITYR_DEF_VAL); + } +#endif + + /* + * Configure the SGI and PPI. This is done in a separated function + * because each CPU is responsible for initializing its own private + * interrupts. + */ + arm_gic_pcpu_distif_setup(); + + +} +/* End of function arm_gic_distif_setup */ + +/******************************************************************************* + * Initialize the ARM GIC driver with the provided platform inputs +******************************************************************************/ +void arm_gic_init(uintptr_t gicc_base, + uintptr_t gicd_base, + const unsigned int *irq_sec_ptr, + unsigned int num_irqs) +{ + assert(gicc_base); + assert(gicd_base); + + s_g_gicc_base = gicc_base; + s_g_gicd_base = gicd_base; + +} +/* End of function arm_gic_init */ + +/******************************************************************************* + * Setup the ARM GIC CPU and distributor interfaces. +******************************************************************************/ +void arm_gic_setup(void) +{ + arm_gic_distif_setup(); +} +/* End of function arm_gic_setup */ + +#if ARM_GIC_ARCH == 2 +/******************************************************************************* + * This functions reads the GIC cpu interface Interrupt Acknowledge register + * to start handling the pending interrupt. It returns the contents of the IAR. + ******************************************************************************/ +uint32_t arm_gic_acknowledge_interrupt(void) +{ + assert(s_g_gicc_base); + return gicc_read_IAR(s_g_gicc_base); +} + +/******************************************************************************* + * This functions writes the GIC cpu interface End Of Interrupt register with + * the passed value to finish handling the active interrupt + ******************************************************************************/ +void arm_gic_end_of_interrupt(uint32_t id) +{ + assert(s_g_gicc_base); + gicc_write_EOIR(s_g_gicc_base, id); +} + +#else +#error "Invalid ARM GIC architecture version specified for platform port" +#endif /* ARM_GIC_ARCH */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/auth.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/auth.c new file mode 100644 index 0000000..1da0ca5 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/auth.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file auth.c + * - Version : 0.01 + * @brief Read data from certificate. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include "rcar_def.h" +#include "debug.h" +#include "auth.h" + + +#define RCAR_CERT_INFO_SIZE_OFFSET (0x264U) /* byte address set : must 4byte alignment */ +#define RCAR_CERT_INFO_DST_OFFSET (0x154U) /* byte address set : must 4byte alignment */ +#define RCAR_CERT_INFO_SIZE_OFFSET1 (0x364U) /* for Map Type-1 */ +#define RCAR_CERT_INFO_DST_OFFSET1 (0x1D4U) /* for Map Type-1 */ +#define RCAR_CERT_INFO_SIZE_OFFSET2 (0x464U) /* for Map Type-2 */ +#define RCAR_CERT_INFO_DST_OFFSET2 (0x254U) /* for Map Type-2 */ + +#define RCAR_BOOT_KEY_CERT_NEW (0xE6300F00U) +#define RCAR_CERT_MAGIC_NUM (0xE291F358U) + +#define FLASH_SEC_BOOT_CERT_ADDR (0x00000800U) +#define FLASH_SEC_BOOT_CERT_ADDR2 (0x00000B00U) +#define FLASH_IPL_CERT_ADDR (0x00000C00U) +#define FLASH_IPL_CERT_ADDR2 (0x00000080U) + +static uint32_t s_boot_cert_offset = 0U; +static uint32_t s_ipl_cert_offset = 0U; + +void pre_read_cert_info(void) +{ + uint32_t magicNumber; + + magicNumber = mmio_read_32((uintptr_t)RCAR_BOOT_KEY_CERT_NEW); + + if (RCAR_CERT_MAGIC_NUM == magicNumber) { + s_boot_cert_offset = FLASH_SEC_BOOT_CERT_ADDR2; + s_ipl_cert_offset = FLASH_IPL_CERT_ADDR2; + } else { + s_boot_cert_offset = FLASH_SEC_BOOT_CERT_ADDR; + s_ipl_cert_offset = FLASH_IPL_CERT_ADDR; + } +} +/* End of function pre_read_cert_info */ + +void get_cert_info(uint32_t *boot_cert_addr, uint32_t *size, + uint32_t *ipl_cert_addr) +{ + *boot_cert_addr = s_boot_cert_offset; + *size = 0x1100U; + *ipl_cert_addr = s_ipl_cert_offset; +} +/* End of function get_cert_info */ + +void get_info_from_cert(uint32_t cert_addr, uint32_t *size, + uintptr_t *dest_addr) +{ + uint32_t val; + uint32_t magicNumber; + uint32_t certInfo1; + uintptr_t pSize; + uintptr_t pDestL; + + magicNumber = mmio_read_32((uintptr_t)RCAR_BOOT_KEY_CERT_NEW); + val = mmio_read_32((uintptr_t)cert_addr + 0xCU); + certInfo1 = (val >> 21U) & 0x3U; + + if (RCAR_CERT_MAGIC_NUM == magicNumber) + { + if (0x2U == certInfo1) + { + pSize = cert_addr + RCAR_CERT_INFO_SIZE_OFFSET2; + *size = mmio_read_32(pSize) * 4U; + pDestL = cert_addr + RCAR_CERT_INFO_DST_OFFSET2; + *dest_addr = (uintptr_t)mmio_read_32(pDestL); + } + else if (0x1U == certInfo1) + { + pSize = cert_addr + RCAR_CERT_INFO_SIZE_OFFSET1; + *size = mmio_read_32(pSize) * 4U; + pDestL = cert_addr + RCAR_CERT_INFO_DST_OFFSET1; + *dest_addr = (uintptr_t)mmio_read_32(pDestL); + } + else if (0x0U == certInfo1) + { + pSize = cert_addr + RCAR_CERT_INFO_SIZE_OFFSET; + *size = mmio_read_32(pSize) * 4U; + pDestL = cert_addr + RCAR_CERT_INFO_DST_OFFSET; + *dest_addr = (uintptr_t)mmio_read_32(pDestL); + } + else /* if (0x3U == certInfo2) */ + { + ERROR("Cert is invalid.\n"); + *size = 0x0U; + *dest_addr = 0x0U; + } + } + else + { + pSize = cert_addr + RCAR_CERT_INFO_SIZE_OFFSET; + *size = mmio_read_32(pSize) * 4U; + pDestL = cert_addr + RCAR_CERT_INFO_DST_OFFSET; + *dest_addr = (uintptr_t)mmio_read_32(pDestL); + } +} +/* End of function get_info_from_cert */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/axi_bus_timeout.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/axi_bus_timeout.c new file mode 100644 index 0000000..51d69a1 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/axi_bus_timeout.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2019-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file axi_bus_timeout.c + * - Version : 0.01 + * @brief AXI bus timeout setting. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include "axi_register.h" +#include "axi_init.h" + +#define FDT_NON_SAFETY_RELATED (0x00000000U) +#define FDT_SAFETY_RELATED (0x00000001U) +#define FDT_TIMEOUT_CNT (0x00000002U) + +#define TIMEOUT_TBL_MAX (sizeof(s_timeout_tbl) / sizeof((s_timeout_tbl)[0])) + +#define EDC_FIX_ENABLE_BIT (0x00000001U) + +#define FDT_CCP (0xE6620500U) +#define FDT_SDHI0 (0xE7751304U) +#define FDT_SDM1B (0xE7751308U) +#define FDT_SDM2B (0xE775130CU) +#define FDT_SDM1M (0xE7751310U) +#define FDT_SDM2M (0xE7751314U) +#define FDT_SDM1P (0xE7780704U) +#define FDT_SDM2P (0xE7780708U) +#define FDT_FCPVD0 (0xFEBF0600U) +#define FDT_IMR01 (0xFEBF0610U) +#define FDT_IMR23 (0xFEBF0614U) +#define FDT_VIN0 (0xFEBF0630U) +#define FDT_IV1E (0xFEBF0680U) +#define FDT_ISP0 (0xFEBF0690U) +#define FDT_ISP1 (0xFEBF0694U) +#define FDT_FBAC530 (0xFF860200U) +#define FDT_FBAC531 (0xFF860204U) +#define FDT_FBAC53D (0xFF86020CU) +#define FDT_FBAIMR01 (0xFF860210U) +#define FDT_FBAIMR23 (0xFF860214U) +#define FDT_FBAIMP0 (0xFF860218U) +#define FDT_FBAIMP1 (0xFF86021CU) +#define FDT_FBAIMP2 (0xFF860220U) +#define FDT_FBAIMP3 (0xFF860224U) +#define FDT_FBAMM (0xFF860228U) +#define FDT_FBAOCV0 (0xFF86022CU) +#define FDT_FBAOCV1 (0xFF860230U) +#define FDT_IMP0 (0xFF880600U) +#define FDT_IMP1 (0xFF880604U) +#define FDT_RTD0P (0xFFC30700U) +#define FDT_RTD1P (0xFFC30704U) +#define FDT_CR7 (0xFFC40500U) +#define FDT_RTD0B (0xFFC40504U) +#define FDT_RTD0M (0xFFC40508U) +#define FDT_CSD (0xFFC40520U) +#define FDT_EAVB (0xFFC405C0U) +#define FDT_IPC64 (0xFFC405C4U) +#define FDT_FRAY (0xFFC405CCU) +#define FDT_CAIP (0xFFC405D0U) +#define FDT_RTD1B (0xFFC405D4U) +#define FDT_RTD1M (0xFFC405D8U) + +typedef struct { + uintptr_t addr; + uintptr_t safety_related; +} st_axi_bus_timeout_counter_data_t; + +void axi_bus_timeout_setting(void) +{ + uint32_t loop; + + static const st_axi_bus_timeout_counter_data_t s_timeout_tbl[] = { + { FDT_CCP, FDT_NON_SAFETY_RELATED }, + { FDT_SDHI0, FDT_NON_SAFETY_RELATED }, + { FDT_SDM1B, FDT_SAFETY_RELATED }, + { FDT_SDM2B, FDT_SAFETY_RELATED }, + { FDT_SDM1M, FDT_SAFETY_RELATED }, + { FDT_SDM2M, FDT_SAFETY_RELATED }, + { FDT_SDM1P, FDT_SAFETY_RELATED }, + { FDT_SDM2P, FDT_SAFETY_RELATED }, + { FDT_IMR23, FDT_SAFETY_RELATED }, + { FDT_FCPVD0, FDT_NON_SAFETY_RELATED }, + { FDT_IMR01, FDT_SAFETY_RELATED }, + { FDT_VIN0, FDT_SAFETY_RELATED }, + { FDT_IV1E, FDT_NON_SAFETY_RELATED }, + { FDT_ISP0, FDT_SAFETY_RELATED }, + { FDT_ISP1, FDT_SAFETY_RELATED }, + { FDT_FBAC530, FDT_SAFETY_RELATED }, + { FDT_FBAC531, FDT_SAFETY_RELATED }, + { FDT_FBAC53D, FDT_SAFETY_RELATED }, + { FDT_FBAIMR01, FDT_SAFETY_RELATED }, + { FDT_FBAIMR23, FDT_SAFETY_RELATED }, + { FDT_FBAIMP0, FDT_SAFETY_RELATED }, + { FDT_FBAIMP1, FDT_SAFETY_RELATED }, + { FDT_FBAIMP2, FDT_SAFETY_RELATED }, + { FDT_FBAIMP3, FDT_SAFETY_RELATED }, + { FDT_FBAMM, FDT_SAFETY_RELATED }, + { FDT_FBAOCV0, FDT_SAFETY_RELATED }, + { FDT_FBAOCV1, FDT_SAFETY_RELATED }, + { FDT_IMP0, FDT_NON_SAFETY_RELATED }, + { FDT_IMP1, FDT_NON_SAFETY_RELATED }, + { FDT_RTD0P, FDT_SAFETY_RELATED }, + { FDT_RTD1P, FDT_SAFETY_RELATED }, + { FDT_CR7, FDT_SAFETY_RELATED }, + { FDT_RTD0B, FDT_SAFETY_RELATED }, + { FDT_RTD0M, FDT_SAFETY_RELATED }, + { FDT_CSD, FDT_NON_SAFETY_RELATED }, + { FDT_EAVB, FDT_SAFETY_RELATED }, + { FDT_IPC64, FDT_SAFETY_RELATED }, + { FDT_FRAY, FDT_SAFETY_RELATED }, + { FDT_CAIP, FDT_NON_SAFETY_RELATED }, + { FDT_RTD1B, FDT_SAFETY_RELATED }, + { FDT_RTD1M, FDT_SAFETY_RELATED } + }; + + for (loop = 0U; loop < TIMEOUT_TBL_MAX; loop++) + { + if (s_timeout_tbl[loop].safety_related == FDT_SAFETY_RELATED) + { + mmio_write_32(s_timeout_tbl[loop].addr, FDT_TIMEOUT_CNT); + } + } + + if ((mmio_read_32(EDC_EDCFIXERREN) & + EDC_FIX_ENABLE_BIT) != 0x00000001U) { + mmio_write_32(EDC_EDCFIXERREN, 0x00000001U); + } + + mmio_write_32(EDC_EDCFIXERRINTEN0, 0x11B40078U); + mmio_write_32(EDC_EDCFIXERRINTEN1, 0x00000000U); + mmio_write_32(EDC_EDCFIXERRINTEN2, 0xC0000E00U); + mmio_write_32(EDC_EDCFIXERRINTEN3, 0x7E18BAFFU); + +} +/* End of function axi_bus_timeout_setting */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/cpsr_acc.s b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/cpsr_acc.s new file mode 100644 index 0000000..29e0d8b --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/cpsr_acc.s @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + + +#ifndef __ARCH_HELPERS_S__ +#define __ARCH_HELPERS_S__ + + .globl aif_enable_i + .globl aif_disable_i + .globl aif_enable_a + .globl aif_disable_a + +/***************************************************************************** + * enable_aif + *****************************************************************************/ +aif_enable_i: + cpsie i + bx lr + +/***************************************************************************** + * disable_aif + *****************************************************************************/ + aif_disable_i: + cpsid i + bx lr + +/***************************************************************************** + * enable_aif + *****************************************************************************/ +aif_enable_a: + cpsie a + bx lr + +/***************************************************************************** + * disable_aif + *****************************************************************************/ + aif_disable_a: + cpsid a + bx lr + + .end diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/div.s b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/div.s new file mode 100644 index 0000000..3e5620e --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/div.s @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + + .global __aeabi_uidivmod + .global __aeabi_uidiv + .global __aeabi_idivmod + .global __aeabi_idiv + + +/***************************************************************************** + * input: + * r0: divided + * r1: divisor + * + * output + * r0: quot + * r1: rem + *****************************************************************************/ + +__aeabi_uidivmod: + push {r4, r5} + mov r4, #0 + mov r5, #1 + + clz r2, r1 + mov r3, r1, LSL r2 +1: + cmp r3, r0 + subls r0, r0, r3 + addls r4, r5, LSL r2 + + lsr r3, r3, #1 + subs r2, r2, #1 + bpl 1b + + mov r1, r0 + mov r0, r4 + + pop {r4, r5} + bx lr + +/***************************************************************************** + * input: + * r0: divided + * r1: divisor + * + * output + * r0: quot + *****************************************************************************/ + +__aeabi_uidiv: + b __aeabi_uidivmod /* same as __aeabi_uidivmod */ + +/***************************************************************************** + * input: + * r0: divided + * r1: divisor + * + * output + * r0: quot + *****************************************************************************/ + +__aeabi_idiv: + b __aeabi_idivmod /* same as __aeabi_idivmod */ + +/***************************************************************************** + * input: + * r0: divided + * r1: divisor + * + * output + * r0: quot + * r1: rem + *****************************************************************************/ + +__aeabi_idivmod: + + subs r2, r0, #0 + push {r4, r5, r6, lr} + movlt r4, #1 + rsblt r2, r2, #0 + movge r4, #0 + cmp r1, #0 + movlt lr, #1 + rsblt r1, r1, #0 + movge lr, #0 + mov r3, #0 + +4: + cmp r2, r1, lsl r3 + sublt r3, r3, #1 + lsllt r1, r1, r3 + blt 3f + add r3, r3, #1 + cmp r3, #32 + bne 4b + mov r3, #0 + +3: + mov r0, #0 + mov r5, #1 + mov ip, r0 + +2: + cmp ip, r3 + bgt 1f + cmp r2, #0 + beq 1f + cmp r2, r1 + subge r6, r3, ip + subge r2, r2, r1 + orrge r0, r0, r5, lsl r6 + asr r1, r1, #1 + add ip, ip, #1 + b 2b + +1: + cmp r4, lr + rsbne r0, r0, #0 + mov r1, r0 + tst r4, lr + rsbne r2, r2, #0 + pop {r4, r5, r6, lr} + bx lr + + .end diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/dma_driver.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/dma_driver.c new file mode 100644 index 0000000..00788fe --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/dma_driver.c @@ -0,0 +1,146 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file dma_driver.c + * - Version : 0.01 + * @brief DMA driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include "cpg_register.h" +#include "cpg_init.h" +#include "dma_register.h" +#include "dma_driver.h" +#include "debug.h" + +static void enable_dma(void); +static void setup_dma(void); +static void start_dma(uint32_t dst, uint32_t src, uint32_t len); +static void end_dma(void); + +static void enable_dma(void) +{ + /* Is the clock supply to the CPG disabled ? */ + while ((mmio_read_32(CPG_MSTPSR0) & RT_DMAC_BIT) != 0U) + { + /* Enables the clock supply to the CPG. */ + cpg_write(CPG_RMSTPCR0, + mmio_read_32(CPG_RMSTPCR0) & (~RT_DMAC_BIT)); + } +} +/* End of function enable_dma */ + +static void setup_dma(void) +{ + /* DMA channel clear */ + mmio_write_32(DMA_RDMCHCLR, (1U << DMACH)); +} +/* End of function setup_dma */ + +static void start_dma(uint32_t dst, uint32_t src, uint32_t len) +{ + + uint32_t reg; + + /* DMA operation */ + mmio_write_16(DMA_RDMOR, 0x0301U); + /* DMA secure control register */ + reg = mmio_read_32(DMA_RDMSEC); + reg |= (1U << DMACH); + mmio_write_32(DMA_RDMSEC, reg); + /* DMA destination address */ + mmio_write_32(DMA_RDMDAR, dst); + /* DMA source address */ + mmio_write_32(DMA_RDMSAR, src); + /* DMA 64bytes-unit transfer count */ + mmio_write_32(DMA_RDMTCR, (len >> 6U)); + /* DMA channel control */ + mmio_write_32(DMA_RDMCHCR, 0x00105409U); +} +/* End of function start_dma */ + +static void end_dma(void) +{ + uint32_t reg; + + /* DMA channel control */ + while ((mmio_read_32(DMA_RDMCHCR) & 0x00000002U) == 0x00000000U) + { + /* DMA channel control 32 */ + if ((mmio_read_32(DMA_RDMCHCR) & 0x80000000U) != 0U) + { + ERROR("DMA - Channel Address Error\n"); + panic(); + break; + } + } + /* DMA channel clear 2 */ + mmio_write_32(DMA_RDMCHCLR,(1U << DMACH)); + reg = mmio_read_32(DMA_RDMSEC); + reg &= (~(1U << DMACH)); + mmio_write_32(DMA_RDMSEC, reg); +} +/* End of function end_dma */ + +void init_dma(void) +{ + enable_dma(); + setup_dma(); +} +/* End of function init_dma */ + +void exec_dma(uint32_t dst, uint32_t src, uint32_t len) +{ + uint32_t dmalen; + uint32_t memlen; + + if (((dst & 0x3FU) != 0U) || ((src & 0x3FU) != 0U) || + ((len & 0xC0000000U) != 0U)) + { + /* dst or src are not 64-bit alignment. */ + dmalen = 0U; + memlen = len; + } + else + { + /* dst and src are 64-bit alignment. */ + dmalen = len & 0x3FFFFFC0U; + memlen = len & 0x3FU; + } + if (dmalen != 0U) + { + start_dma(dst, src, dmalen); + end_dma(); + dst += dmalen; + src += dmalen; + } + else + { + if (memlen == 0U) + { + start_dma(dst, src, 0U); + end_dma(); + dmalen = 0x01000000U << 6; + dst += dmalen; + src += dmalen; + } + } + if (memlen != 0U) + { + (void)memcpy((void*)(uintptr_t)dst, + (const void*)(uintptr_t)src, + (size_t)memlen); + } +} +/* End of function exec_dma */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/ecc.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/ecc.c new file mode 100644 index 0000000..6e0a33f --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/ecc.c @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file ecc.c + * - Version : 0.01 + * @brief Initial setting process of ECC. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include "debug.h" +#include "mmio.h" +#include "ecc.h" + +/* AXI-Bus registers definitions */ +#define AXI_BASE (0xE6784000U) + +/* System RAM ECC Register */ +#define AXI_SFUSAAREACR0 (AXI_BASE+0x1100U) +#define AXI_SECCAREACR0 (AXI_BASE+0x1140U) + +/* SDRAM ECC Register */ +#define DFUSAAREACR0 (AXI_BASE + 0x1000U) +#define DECCAREACR0 (AXI_BASE + 0x1040U) + +/* Error Detection Register */ +#define EDCEN0 (0xFF840010U) +#define EDCEN1 (0xFF840014U) +#define EDCINTEN0 (0xFF840040U) +#define EDCINTEN1 (0xFF840044U) +#define EDCINTEN2 (0xFF840048U) +#define EDCINTEN3 (0xFF84004CU) +#define EDCINTEN4 (0xFF840190U) + +/** EDC Enable Register 0 */ +/* Bit[31] : CCI 1:Enable */ +/* Bit[30] : CR7 1:Enable */ +/* Bit[29] : DMAC 1:Enable */ +/* Bit[28] : GPU 1:Enable */ +/* Bit[27] : IMP 1:Enable */ +/* Bit[26:25] : Reserved */ +/* Bit[24] : ETH 1:Enable */ +/* Bit[23:22] : Reserved */ +/* Bit[21] : IPMMUVI 1:Enable */ +/* Bit[20] : IPMMURT 1:Enable */ +/* Bit[19] : IPMMUIR 1:Enable */ +/* Bit[18] : IPMMUDS0 1:Enable */ +/* Bit[17] : IPMMUDS1 1:Enable */ +/* Bit[16] : IPMMUPV 1:Enable */ +/* Bit[15] : MEM 1:Enable */ +/* Bit[14:11] : Reserved */ +/* Bit[10] : ARMCNT 1:Enable */ +/* Bit[9] : RST 1:Enable */ +/* Bit[8] : INTAP 1:Enable */ +/* Bit[7] : INTRT 1:Enable */ +/* Bit[6] : BOOTROM 1:Enable */ +/* Bit[5] : MFIS 1:Enable */ +/* Bit[4] : Reserved */ +/* Bit[3] : LIFEC1 1:Enable */ +/* Bit[2] : LIFEC0 1:Enable */ +/* Bit[1:0] : Reserved */ +#define EDCEN0_ALL_EN (0xF93F87ECU) + +/** EDC Enable Register 1 */ +/* Bit[31:19] : Reserved */ +/* Bit[18] : IPMMUVC 1:Enable */ +/* Bit[17] : FCPCS 1:Enable */ +/* Bit[16] : INTC 1:Enable */ +/* Bit[15] : SYSC 1:Enable */ +/* Bit[14] : PFC 1:Enable */ +/* Bit[13] : CPG 1:Enable */ +/* Bit[12] : Reserved */ +/* Bit[11] : iV1E 1:Enable */ +/* Bit[10] : FCPVD 1:Enable */ +/* Bit[9] : IMR 1:Enable */ +/* Bit[8] : ISP 1:Enable */ +/* Bit[7] : VIN 1:Enable */ +/* Bit[6] : Reserved */ +/* Bit[5] : FRAY 1:Enable */ +/* Bit[4] : IPC 1:Enable */ +/* Bit[3] : CAIP 1:Enable */ +/* Bit[2] : SDHI 1:Enable */ +/* Bit[1] : RTDMAC 1:Enable */ +/* Bit[0] : STBE 1:Enable */ +#define EDCEN1_ALL_EN (0x0007EFBFU) + +/** EDC Interrupt Enable Register 0 */ +/* Bit[31] : IPMMUDS0 1:Enable */ +/* Bit[30] : IPMMUDS1 1:Enable */ +/* Bit[29] : IPMMUIR 1:Enable */ +/* Bit[28] : IMP1 1:Enable */ +/* Bit[27] : IMP0 1:Enable */ +/* Bit[26] : IMP_SLAVE 1:Enable */ +/* Bit[25:19] : Reserved */ +/* Bit[18] : IPMMURT 1:Enable */ +/* Bit[17:15] : Reserved */ +/* Bit[14] : MFIS 1:Enable */ +/* Bit[13] : INTAP 1:Enable */ +/* Bit[12] : INTRT 1:Enable */ +/* Bit[11] : BOOTROM 1:Enable */ +/* Bit[10] : CR7 1:Enable */ +/* Bit[9] : IPMMUPV 1:Enable */ +/* Bit[8] : MEM3 1:Enable */ +/* Bit[7] : MEM2 1:Enable */ +/* Bit[6] : MEM1 1:Enable */ +/* Bit[5] : MEM0 1:Enable */ +/* Bit[4] : RGX_SLAVE 1:Enable */ +/* Bit[3] : RGX3 1:Enable */ +/* Bit[2] : RGX2 1:Enable */ +/* Bit[1] : RGX1 1:Enable */ +/* Bit[0] : RGX0 1:Enable */ +#define EDCINTEN0_ALL_EN (0xFC047FFFU) + +/** EDC Interrupt Enable Register 1 */ +/* Bit[31] : DRAM 1:Enable */ +/* Bit[30] : DRAM_MLT 1:Enable */ +/* Bit[29] : DRAM_SGL 1:Enable */ +/* Bit[28] : TR2 1:Enable */ +/* Bit[27] : TR1 1:Enable */ +/* Bit[26] : TR0 1:Enable */ +/* Bit[25] : Reserved */ +/* Bit[24] : RST 1:Enable */ +/* Bit[23] : ARMCNT 1:Enable */ +/* Bit[22] : APS0 1:Enable */ +/* Bit[21] : LIFEC1 1:Enable */ +/* Bit[20] : LIFEC0 1:Enable */ +/* Bit[19] : ETHER 1:Enable */ +/* Bit[18] : Reserved */ +/* Bit[17] : ETHER(X2X) 1:Enable */ +/* Bit[16] : SYSD1 1:Enable */ +/* Bit[15] : SYSD2 1:Enable */ +/* Bit[14] : SYSD(X2X) 1:Enable */ +/* Bit[13] : CR7(utlb) 1:Enable */ +/* Bit[12:0] : Reserved */ +#define EDCINTEN1_ALL_EN (0xFDFBE000U) + +/** EDC Interrupt Enable Register 2 */ +/* Bit[31] : X2X128to64_RT 1:Enable */ +/* Bit[30] : X2X_APVI2 1:Enable */ +/* Bit[29] : X2X_SDS2 1:Enable */ +/* Bit[28] : X2X_APVI1 1:Enable */ +/* Bit[27] : ISP_Slave 1:Enable */ +/* Bit[26] : X2X_APVI0 1:Enable */ +/* Bit[25] : VIN0 1:Enable */ +/* Bit[24] : ISP1 1:Enable */ +/* Bit[23] : ISP0 1:Enable */ +/* Bit[22] : IMR23 1:Enable */ +/* Bit[21] : IMR01 1:Enable */ +/* Bit[20] : FCPVD 1:Enable */ +/* Bit[19] : iV1E 1:Enable */ +/* Bit[18] : Reserved */ +/* Bit[17] : IPMMUVI 1:Enable */ +/* Bit[16] : PFC 1:Enable */ +/* Bit[15] : SYSC 1:Enable */ +/* Bit[14] : INTC 1:Enable */ +/* Bit[13] : FCPCS 1:Enable */ +/* Bit[12] : CAIP 1:Enable */ +/* Bit[11] : CPG 1:Enable */ +/* Bit[10] : IMR0 1:Enable */ +/* Bit[9] : IMR1 1:Enable */ +/* Bit[8] : IMR2 1:Enable */ +/* Bit[7] : IMR3 1:Enable */ +/* Bit[6] : ISPC 1:Enable */ +/* Bit[5] : VIN0 1:Enable */ +/* Bit[4] : VIN1 1:Enable */ +/* Bit[3] : VIN2 1:Enable */ +/* Bit[2] : VIN3 1:Enable */ +/* Bit[1] : Reserved */ +/* Bit[0] : X2X_iV1E 1:Enable */ +#define EDCINTEN2_ALL_EN (0xFFFBFFFDU) + +/** EDC Interrupt Enable Register 3 */ +/* Bit[31] : X2X_IPC 1:Enable */ +/* Bit[30] : SYDM1 1:Enable */ +/* Bit[29] : SYDM2 1:Enable */ +/* Bit[28] : RTDM0 1:Enable */ +/* Bit[27] : RTDM1 1:Enable */ +/* Bit[26] : AHFRAY 1:Enable */ +/* Bit[25] : X2X_RDS0 1:Enable */ +/* Bit[24] : X2X_RDS1 1:Enable */ +/* Bit[23] : X2X_CR7 1:Enable */ +/* Bit[22] : AXMM_DUP 1:Enable */ +/* Bit[21] : X2X_AXRT_128 1:Enable */ +/* Bit[20] : X2X_AXRT_64 1:Enable */ +/* Bit[19] : X2X_SDS1 1:Enable */ +/* Bit[18] : AVB_SLAVE 1:Enable */ +/* Bit[17] : CAIP 1:Enable */ +/* Bit[16] : X2X_APVC0 1:Enable */ +/* Bit[15] : IPMMUPV1 1:Enable */ +/* Bit[14] : IPMMUPV2 1:Enable */ +/* Bit[13] : IPMMUPV3 1:Enable */ +/* Bit[12] : VIN1 (master) 1:Enable */ +/* Bit[11] : VIN4 1:Enable */ +/* Bit[10] : VIN5 1:Enable */ +/* Bit[9] : VIN6 1:Enable */ +/* Bit[8] : VIN7 1:Enable */ +/* Bit[7] : X2X_AXVC_128 1:Enable */ +/* Bit[6] : X2X_AXVC_256 1:Enable */ +/* Bit[5] : FCPCI 1:Enable */ +/* Bit[4] : FCPCS 1:Enable */ +/* Bit[3] : VCPLF_CE 1:Enable */ +/* Bit[2] : VCPLF_VLC 1:Enable */ +/* Bit[1] : X2X_APSW1 1:Enable */ +/* Bit[0] : X2X_APSE1 1:Enable */ +#define EDCINTEN3_ALL_EN (0xFFFFFFFFU) + +/** EDC Interrupt Enable Register 4 */ +/* Bit[31:3] : Reserved */ +/* Bit[2] : IPMMUVC1 1:Enable */ +/* Bit[1] : IPMMUVC0 1:Enable */ +/* Bit[0] : X2X_APSW2 1:Enable */ +#define EDCINTEN4_ALL_EN (0x00000007U) + +#define DATA64_ECC8 (1U) +#define DATA8_ECC5 (0U) +#define ECC_ON (1U) +#define ECC_OFF (0U) +#define FUSA_SIZE_4KB (0U) +#define FUSA_SIZE_8KB (1U) +#define FUSA_SIZE_16KB (2U) +#define FUSA_SIZE_32KB (3U) +#define FUSA_SIZE_64KB (4U) +#define FUSA_SIZE_128KB (5U) +#define FUSA_SIZE_256KB (6U) +#define DRAM_FUSA_SIZE_1MB (0U) +#define DRAM_FUSA_SIZE_2MB (1U) +#define DRAM_FUSA_SIZE_4MB (2U) +#define DRAM_FUSA_SIZE_8MB (3U) +#define DRAM_FUSA_SIZE_16MB (4U) +#define DRAM_FUSA_SIZE_32MB (5U) +#define DRAM_FUSA_SIZE_64MB (6U) +#define DRAM_FUSA_SIZE_128MB (7U) +#define DRAM_FUSA_SIZE_256MB (8U) +#define DRAM_FUSA_SIZE_512MB (9U) +#define AREA_NUM (8U) +#define DRAM_AREA_NUM (16U) + +#define START_ADDRESS_MASK (0xFFFFF000U) +#define DRAM_40BIT_ADDRESS (0x400000U) +#define DRAM_START_ADDRESS (0x40000000U) +#define NON_START_ADDRESS (0x00000000U) + +static inline void dsb(void) +{ + __asm__ __volatile__ ("dsb sy"); + +} +/* End of function dsb */ + +/************************************************************************/ +/* System RAM ECC enable */ +/************************************************************************/ +void ecc_init(void) +{ +#if RCAR_SYSRAM_ECC_ENABLE == 1 + uint32_t i; + uint32_t ecc_enable[AREA_NUM]; + + /* Functional Safety settings */ + /* Area ECC mode * + * 64DATA_8ECC = 64bit Data/8bit ECC mode * + * 8DATA_5ECC = 8bit Data/5bit ECC mode * + * + * Area FUSA size * + * FUSA_SIZE_4KB: 4KB * + * FUSA_SIZE_8KB: 8KB * + * FUSA_SIZE_16KB: 16KB * + * FUSA_SIZE_32KB: 32KB * + * FUSA_SIZE_64KB: 64KB * + * FUSA_SIZE_128KB: 128KB * + * FUSA_SIZE_256KB: 256KB * + * Others: Reserved */ + const struct { + uint32_t data_address; + uint32_t ecc_address; + uint32_t area_ecc_mode; + uint32_t ecc_area_size; + } ecc_setting_table[] = { + {0xE6350000U, 0xE6358000U, DATA8_ECC5, FUSA_SIZE_32KB}, /* area0 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, FUSA_SIZE_4KB}, /* area1 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, FUSA_SIZE_4KB}, /* area2 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, FUSA_SIZE_4KB}, /* area3 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, FUSA_SIZE_4KB}, /* area4 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, FUSA_SIZE_4KB}, /* area5 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, FUSA_SIZE_4KB}, /* area6 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, FUSA_SIZE_4KB} /* area7 */ + }; + + /* Address Check */ + for (i = 0; i < AREA_NUM; i++) + { + /* FUSA Register Setting */ + if ((ecc_setting_table[i].data_address != NON_START_ADDRESS) || + (ecc_setting_table[i].ecc_address != NON_START_ADDRESS)) + { + + ecc_enable[i] = ECC_ON; + } + else + { + ecc_enable[i] = ECC_OFF; + } + } + + /* register param set */ + /* System RAM ECC enable */ + for (i = 0; i < AREA_NUM; i++) + { + /* FUSA Register Setting */ + if (ecc_enable[i] == ECC_ON) + { + /* ECC Register Setting */ + mmio_write_32(AXI_SECCAREACR0 + (i*4U), + (ecc_setting_table[i].area_ecc_mode << 31) + | ((ecc_setting_table[i].ecc_address & START_ADDRESS_MASK) >> 12)); + + mmio_write_32(AXI_SFUSAAREACR0 + (i*4U), + (ECC_ON << 31) + | (ecc_setting_table[i].ecc_area_size << 24) + | ((ecc_setting_table[i].data_address & START_ADDRESS_MASK) >> 12)); + } + } + + dsb(); + NOTICE("System RAM ECC enable(CR7)\n"); +#endif /* RCAR_SYSRAM_ECC_ENABLE == 1 */ +} +/* End of function ecc_init */ + +void dram_ecc_init(void) +{ +#if RCAR_DRAM_ECC_ENABLE == 1 + + uint32_t reg; + uint32_t i; + uint32_t dram_start_addr; + uint32_t ecc_enable[DRAM_AREA_NUM]; + + /* Functional Safety settings */ + /* Area ECC mode * + * 64DATA_8ECC = 64bit Data/8bit ECC mode * + * 8DATA_5ECC = 8bit Data/5bit ECC mode * + * + * Area FUSA size * + * DRAM_FUSA_SIZE_1MB: 1MB * + * DRAM_FUSA_SIZE_2MB: 2MB * + * DRAM_FUSA_SIZE_4MB: 4MB * + * DRAM_FUSA_SIZE_8MB: 8MB * + * DRAM_FUSA_SIZE_16MB: 16MB * + * DRAM_FUSA_SIZE_32MB: 32MB * + * DRAM_FUSA_SIZE_64MB: 64MB * + * DRAM_FUSA_SIZE_128MB: 128MB * + * DRAM_FUSA_SIZE_256MB: 256MB * + * DRAM_FUSA_SIZE_512MB: 512MB * + * Others: Reserved */ + const struct { + uint32_t data_address; + uint32_t ecc_address; + uint32_t area_ecc_mode; + uint32_t ecc_area_size; + } dram_ecc_setting_table[] = { + {0x40000000U, 0x40100000U, DATA8_ECC5, DRAM_FUSA_SIZE_1MB}, /* area0 */ + {0x40200000U, 0x44200000U, DATA8_ECC5, DRAM_FUSA_SIZE_64MB}, /* area1 */ + {0x48200000U, 0x4C200000U, DATA8_ECC5, DRAM_FUSA_SIZE_64MB}, /* area2 */ + {0x50200000U, 0x50300000U, DATA8_ECC5, DRAM_FUSA_SIZE_1MB}, /* area3 */ + {0x50400000U, 0x54400000U, DATA8_ECC5, DRAM_FUSA_SIZE_64MB}, /* area4 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, DRAM_FUSA_SIZE_1MB}, /* area5 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, DRAM_FUSA_SIZE_1MB}, /* area6 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, DRAM_FUSA_SIZE_1MB}, /* area7 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, DRAM_FUSA_SIZE_1MB}, /* area8 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, DRAM_FUSA_SIZE_1MB}, /* area9 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, DRAM_FUSA_SIZE_1MB}, /* area10 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, DRAM_FUSA_SIZE_1MB}, /* area11 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, DRAM_FUSA_SIZE_1MB}, /* area12 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, DRAM_FUSA_SIZE_1MB}, /* area13 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, DRAM_FUSA_SIZE_1MB}, /* area14 */ + {0x00000000U, 0x00000000U, DATA8_ECC5, DRAM_FUSA_SIZE_1MB} /* area15 */ + }; + + /* Address Check */ + for (i = 0; i < DRAM_AREA_NUM; i++) + { + if ((DRAM_START_ADDRESS <= dram_ecc_setting_table[i].data_address) && + (DRAM_START_ADDRESS <= dram_ecc_setting_table[i].ecc_address)) + { + ecc_enable[i] = ECC_ON; + } + else + { + ecc_enable[i] = ECC_OFF; + } + } + + /* Error Detection Circuit */ + reg = mmio_read_32(EDCEN0); + reg = (reg | EDCEN0_ALL_EN); + mmio_write_32(EDCEN0, reg); + + reg = mmio_read_32(EDCEN1); + reg = (reg | EDCEN1_ALL_EN); + mmio_write_32(EDCEN1, reg); + + reg = mmio_read_32(EDCINTEN0); + reg = (reg | EDCINTEN0_ALL_EN); + mmio_write_32(EDCINTEN0, reg); + + reg = mmio_read_32(EDCINTEN1); + reg = (reg | EDCINTEN1_ALL_EN); + mmio_write_32(EDCINTEN1, reg); + + reg = mmio_read_32(EDCINTEN2); + reg = (reg | EDCINTEN2_ALL_EN); + mmio_write_32(EDCINTEN2, reg); + + reg = mmio_read_32(EDCINTEN3); + reg = (reg | EDCINTEN3_ALL_EN); + mmio_write_32(EDCINTEN3, reg); + + reg = mmio_read_32(EDCINTEN4); + reg = (reg | EDCINTEN4_ALL_EN); + mmio_write_32(EDCINTEN4, reg); + + /* register param set */ + /* DRAM ECC enable */ + for (i = 0; i < DRAM_AREA_NUM; i++) + { + if (ecc_enable[i] == ECC_ON) + { + /* ECC Register Setting */ + /* ECC mode[31] + ECC Start Address[23:0] */ + dram_start_addr = (((dram_ecc_setting_table[i].ecc_address - DRAM_START_ADDRESS) >> 12)) | DRAM_40BIT_ADDRESS; + mmio_write_32(DECCAREACR0 + (i*4U), + (dram_ecc_setting_table[i].area_ecc_mode << 31) + | dram_start_addr); + + /* FUSA Register Setting */ + /* FuSa Area enable[31] + FuSa Area size[27:24] + FuSa Start Address[23:0] */ + dram_start_addr = (((dram_ecc_setting_table[i].data_address - DRAM_START_ADDRESS) >> 12)) | DRAM_40BIT_ADDRESS; + mmio_write_32(DFUSAAREACR0 + (i*4U), + (ECC_ON << 31) + | (dram_ecc_setting_table[i].ecc_area_size << 24) + | dram_start_addr); + } + } + + /* log output */ + NOTICE("DRAM ECC enable(CR7)\n"); + +#endif /* RCAR_DRAM_ECC_ENABLE == 1 */ +} +/* End of function dram_ecc_init */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/edc_init.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/edc_init.c new file mode 100644 index 0000000..7b1ffd5 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/edc_init.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2018-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file edc_init.c + * - Version : 0.01 + * @brief Initial setting process of EDC. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include "axi_register.h" +#include "edc_init.h" + +void edc_routing_err_init(void) +{ + uint32_t loop; + const uint32_t edcrouerr_reg_tbl[][2] = { + { EDC_EDCROUERREN, 0x00000001U }, + { EDC_EDCRERRINTEN0, 0xFFFF9CFFU }, + { EDC_EDCRERRINTEN1, 0xF7FFFFFFU }, + { EDC_EDCRERRINTEN2, 0xFFFFFFFFU }, + { EDC_EDCRERRINTEN3, 0xFC7FFFFFU }, + { EDC_EDCRERRINTEN4, 0xFFFFFFFFU }, + { EDC_EDCRERRINTEN5, 0x0000001EU } + }; + + + for (loop = 0U; + loop < (sizeof(edcrouerr_reg_tbl) / + sizeof(edcrouerr_reg_tbl[0]));loop++) + { + mmio_write_32(edcrouerr_reg_tbl[loop][0], + edcrouerr_reg_tbl[loop][1]); + } +} +/* End of function edc_routing_err_init */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/error_output.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/error_output.c new file mode 100644 index 0000000..ce54ac2 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/error_output.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file error_output.c + * - Version : 0.01 + * @brief Output error message. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include "error_output.h" +#include "swdt.h" + +void undef_error(uint32_t occ_add) +{ + /* Clear the interrupt request */ + swdt_release(); + + ERROR("\n"); + ERROR("CR7: Undefined Instruction occurred.\n"); + ERROR(" Occurred address : 0x%x\n" ,occ_add); + ERROR("\n"); + + /* Endless loop */ + panic(); +} +/* End of function undef_error */ + +void fiq_error(void) +{ + /* Clear the interrupt request */ + swdt_release(); + + ERROR("\n"); + ERROR("CR7: FIQ handled.\n"); + + /* Endless loop */ + panic(); +} +/* End of function fiq_error */ + +void interrupt_error_id(uint32_t int_id, uint32_t occ_add) +{ + + /* Clear the interrupt request */ + swdt_release(); + + ERROR("\n"); + ERROR("CR7: Unhandled exception occurred.\n"); + ERROR(" Occurred address : 0x%x\n" ,occ_add); + ERROR(" Interrupt ID : %d\n",int_id); + ERROR("\n"); + /* Endless loop */ + panic(); + +} +/* End of function interrupt_error_id */ + +void dabort_error(uint32_t occ_add,uint32_t dfsr, uint32_t dfar) +{ + /* Clear the interrupt request */ + swdt_release(); + + ERROR("\n"); + ERROR("CR7: data abort.\n"); + ERROR(" data abort occurrred address : 0x%x\n",occ_add); + ERROR(" DFSR : 0x%x DFAR : 0x%x\n",dfsr, dfar); + ERROR("\n"); + + /* Endless loop */ + panic(); +} +/* End of function dabort_error */ + +void pabort_error(uint32_t ifsr, uint32_t ifar) +{ + /* Clear the interrupt request */ + swdt_release(); + + ERROR("\n"); + ERROR("CR7: prefetch abort.\n"); + ERROR(" IFSR : 0x%x IFAR : 0x%x\n",ifsr, ifar); + ERROR("\n"); + + /* Endless loop */ + panic(); +} +/* End of function pabort_error */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/gic_v2.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/gic_v2.c new file mode 100644 index 0000000..f011aaa --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/gic_v2.c @@ -0,0 +1,314 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/****************************************************************************** + * @file gic_v2.c + * - Version : 0.01 + * @brief Read / Write GIC register. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include + +/******************************************************************************* + * GIC Distributor interface accessors for reading entire registers + ******************************************************************************/ + +unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> IGROUPR_SHIFT; + return mmio_read_32(base + GICD_IGROUPR + (n << 2)); +} +/* End of function gicd_read_igroupr */ + +unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ISENABLER_SHIFT; + return mmio_read_32(base + GICD_ISENABLER + (n << 2)); +} +/* End of function gicd_read_isenabler */ + +unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICENABLER_SHIFT; + return mmio_read_32(base + GICD_ICENABLER + (n << 2)); +} +/* End of function gicd_read_icenabler */ + +unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ISPENDR_SHIFT; + return mmio_read_32(base + GICD_ISPENDR + (n << 2)); +} +/* End of function gicd_read_ispendr */ + +unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICPENDR_SHIFT; + return mmio_read_32(base + GICD_ICPENDR + (n << 2)); +} +/* End of function gicd_read_icpendr */ + +unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ISACTIVER_SHIFT; + return mmio_read_32(base + GICD_ISACTIVER + (n << 2)); +} +/* End of function gicd_read_isactiver */ + +unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICACTIVER_SHIFT; + return mmio_read_32(base + GICD_ICACTIVER + (n << 2)); +} +/* End of function gicd_read_icactiver */ + +unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> IPRIORITYR_SHIFT; + return mmio_read_32(base + GICD_IPRIORITYR + (n << 2)); +} +/* End of function gicd_read_ipriorityr */ + +unsigned int gicd_read_itargetsr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ITARGETSR_SHIFT; + return mmio_read_32(base + GICD_ITARGETSR + (n << 2)); +} +/* End of function gicd_read_itargetsr */ + +unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICFGR_SHIFT; + return mmio_read_32(base + GICD_ICFGR + (n << 2)); +} +/* End of function gicd_read_icfgr */ + +unsigned int gicd_read_cpendsgir(uintptr_t base, unsigned int id) +{ + unsigned n = id >> CPENDSGIR_SHIFT; + return mmio_read_32(base + GICD_CPENDSGIR + (n << 2)); +} +/* End of function gicd_read_cpendsgir */ + +unsigned int gicd_read_spendsgir(uintptr_t base, unsigned int id) +{ + unsigned n = id >> SPENDSGIR_SHIFT; + return mmio_read_32(base + GICD_SPENDSGIR + (n << 2)); +} +/* End of function gicd_read_spendsgir */ + +/******************************************************************************* + * GIC Distributor interface accessors for writing entire registers + ******************************************************************************/ + +void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> IGROUPR_SHIFT; + mmio_write_32(base + GICD_IGROUPR + (n << 2), val); +} +/* End of function gicd_write_igroupr */ + +void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISENABLER_SHIFT; + mmio_write_32(base + GICD_ISENABLER + (n << 2), val); +} +/* End of function gicd_write_isenabler */ + +void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICENABLER_SHIFT; + mmio_write_32(base + GICD_ICENABLER + (n << 2), val); +} +/* End of function gicd_write_icenabler */ + +void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISPENDR_SHIFT; + mmio_write_32(base + GICD_ISPENDR + (n << 2), val); +} +/* End of function gicd_write_ispendr */ + +void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICPENDR_SHIFT; + mmio_write_32(base + GICD_ICPENDR + (n << 2), val); +} +/* End of function gicd_write_icpendr */ + +void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISACTIVER_SHIFT; + mmio_write_32(base + GICD_ISACTIVER + (n << 2), val); +} +/* End of function gicd_write_isactiver */ + +void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICACTIVER_SHIFT; + mmio_write_32(base + GICD_ICACTIVER + (n << 2), val); +} +/* End of function gicd_write_icactiver */ + +void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> IPRIORITYR_SHIFT; + mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val); +} +/* End of function gicd_write_ipriorityr */ + +void gicd_write_itargetsr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ITARGETSR_SHIFT; + mmio_write_32(base + GICD_ITARGETSR + (n << 2), val); +} +/* End of function gicd_write_itargetsr */ + +void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICFGR_SHIFT; + mmio_write_32(base + GICD_ICFGR + (n << 2), val); +} +/* End of function gicd_write_icfgr */ + +void gicd_write_cpendsgir(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> CPENDSGIR_SHIFT; + mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val); +} +/* End of function gicd_write_cpendsgir */ + +void gicd_write_spendsgir(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> SPENDSGIR_SHIFT; + mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val); +} +/* End of function gicd_write_spendsgir */ + +/******************************************************************************* + * GIC Distributor interface accessors for individual interrupt manipulation + ******************************************************************************/ +unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + return (reg_val >> bit_num) & 0x1; +} +/* End of function gicd_get_igroupr */ + +void gicd_set_igroupr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + gicd_write_igroupr(base, id, reg_val | (1 << bit_num)); +} +/* End of function gicd_set_igroupr */ + +void gicd_clr_igroupr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num)); +} +/* End of function gicd_clr_igroupr */ + +void gicd_set_isenabler(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); + + gicd_write_isenabler(base, id, (1 << bit_num)); +} +/* End of function gicd_set_isenabler */ + +void gicd_set_icenabler(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1); + + gicd_write_icenabler(base, id, (1 << bit_num)); +} +/* End of function gicd_set_icenabler */ + +void gicd_set_ispendr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1); + + gicd_write_ispendr(base, id, (1 << bit_num)); +} +/* End of function gicd_set_ispendr */ + +void gicd_set_icpendr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1); + + gicd_write_icpendr(base, id, (1 << bit_num)); +} +/* End of function gicd_set_icpendr */ + +void gicd_set_isactiver(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1); + + gicd_write_isactiver(base, id, (1 << bit_num)); +} +/* End of function gicd_set_isactiver */ + +void gicd_set_icactiver(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1); + + gicd_write_icactiver(base, id, (1 << bit_num)); +} +/* End of function gicd_set_icactiver */ + +/* + * Make sure that the interrupt's group is set before expecting + * this function to do its job correctly. + */ +void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) +{ + unsigned int reg = base + GICD_IPRIORITYR + (id & ~3); + unsigned int shift = (id & 3) << 3; + unsigned int reg_val = mmio_read_32(reg); + + /* + * Enforce ARM recommendation to manage priority values such + * that group1 interrupts always have a lower priority than + * group0 interrupts. + * Note, lower numerical values are higher priorities so the comparison + * checks below are reversed from what might be expected. + */ + assert(gicd_get_igroupr(base, id) == GRP1 ? + pri >= GIC_HIGHEST_NS_PRIORITY && + pri <= GIC_LOWEST_NS_PRIORITY : + pri >= GIC_HIGHEST_SEC_PRIORITY && + pri <= GIC_LOWEST_SEC_PRIORITY); + + reg_val &= ~(GIC_PRI_MASK << shift); + reg_val |= (pri & GIC_PRI_MASK) << shift; + mmio_write_32(reg, reg_val); +} +/* End of function gicd_set_ipriorityr */ + +void gicd_set_itargetsr(uintptr_t base, unsigned int id, unsigned int target) +{ + unsigned byte_off = id & ((1 << ITARGETSR_SHIFT) - 1); + unsigned int reg_val = gicd_read_itargetsr(base, id); + + gicd_write_itargetsr(base, id, reg_val | (target << (byte_off << 3))); +} +/* End of function gicd_set_itargetsr */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/lifec_init.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/lifec_init.c new file mode 100644 index 0000000..999f7ac --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/lifec_init.c @@ -0,0 +1,202 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file lifec_init.c + * - Version : 0.01 + * @brief Initial setting process of LifeC. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include /* for uint32_t */ +#include +#include "lifec_register.h" +#include "lifec_init.h" +#include "micro_wait.h" + +static void lifec_reg_write(uint32_t addr, uint32_t data); + +static void lifec_reg_write(uint32_t addr, uint32_t data) +{ + mmio_write_32((uintptr_t)addr, data); +} +/* End of function lifec_reg_write */ + +void lifec_init(void) +{ + uint32_t loop; + const uint32_t lifec_reg_tbl[][2] = { + { SEC_GRP0CR2 , 0x3002981BU }, + { SEC_GRP1CR2 , 0x00000002U }, + { SAFE_GRP0CR2, 0x3002981BU }, + { SAFE_GRP1CR2, 0x20001803U }, + + { SEC_GRP0CR0 , 0x63000081U }, + { SEC_GRP1CR0 , 0x00000000U }, + { SAFE_GRP0CR0, 0x63000081U }, + { SAFE_GRP1CR0, 0x20000000U }, + + { SEC_GRP0CR1 , 0x30000C00U }, + { SEC_GRP1CR1 , 0x00000000U }, + { SAFE_GRP0CR1, 0x30000C00U }, + { SAFE_GRP1CR1, 0x20000000U }, + + { SEC_GRP0CR3 , 0x72F04781U }, + { SEC_GRP1CR3 , 0x00000000U }, + { SAFE_GRP0CR3, 0x72F04781U }, + { SAFE_GRP1CR3, 0x00004000U }, + + { SEC_SEL0 , 0xFFFFFFFFU }, + { SEC_GRP0COND0 , 0x02880F00U }, + { SEC_GRP1COND0 , 0x00000000U }, + { SEC_READONLY0 , 0x00000000U }, + { SAFE_GRP0COND0 , 0x02880F00U }, + { SAFE_GRP1COND0 , 0x00000000U }, + { SAFE_READONLY0 , 0x00000000U }, + + { SEC_SEL1 , 0xFFFFFFFFU }, + { SEC_GRP0COND1 , 0x00000086U }, + { SEC_GRP1COND1 , 0x00000000U }, + { SEC_READONLY1 , 0x00000000U }, + { SAFE_GRP0COND1 , 0x00000886U }, + { SAFE_GRP1COND1 , 0x00000800U }, + { SAFE_READONLY1 , 0x00000800U }, + + { SEC_SEL2 , 0xFFFFFFFFU }, + { SEC_GRP0COND2 , 0x00078000U }, + { SEC_GRP1COND2 , 0x00000000U }, + { SEC_READONLY2 , 0x00000000U }, + { SAFE_GRP0COND2 , 0x0007A000U }, + { SAFE_GRP1COND2 , 0x00002000U }, + { SAFE_READONLY2 , 0x00002000U }, + + { SEC_SEL3 , 0xFFFFFFFFU }, + { SEC_GRP0COND3 , 0x84080200U }, + { SEC_GRP1COND3 , 0x00000000U }, + { SEC_READONLY3 , 0x00000000U }, + { SAFE_GRP0COND3 , 0xC444047CU }, + { SAFE_GRP1COND3 , 0x4044047CU }, + { SAFE_READONLY3 , 0x4044047CU }, + + { SEC_SEL4 , 0xFFFFFFFFU }, + { SEC_GRP0COND4 , 0x80000000U }, + { SEC_GRP1COND4 , 0x00000000U }, + { SEC_READONLY4 , 0x00000000U }, + { SAFE_GRP0COND4 , 0xF0000001U }, + { SAFE_GRP1COND4 , 0x70000001U }, + { SAFE_READONLY4 , 0x70000001U }, + + { SEC_SEL5 , 0xFFFFFFFFU }, + { SEC_GRP0COND5 , 0x00000808U }, + { SEC_GRP1COND5 , 0x00000000U }, + { SEC_READONLY5 , 0x00000000U }, + { SAFE_GRP0COND5 , 0x0BDFD05BU }, + { SAFE_GRP1COND5 , 0x0BDFD053U }, + { SAFE_READONLY5 , 0x0BDFD053U }, + + { SEC_SEL6 , 0xFFFFFFFFU }, + { SEC_GRP0COND6 , 0x00000000U }, + { SEC_GRP1COND6 , 0x00000000U }, + { SEC_READONLY6 , 0x00000000U }, + { SAFE_GRP0COND6 , 0x000035FBU }, + { SAFE_GRP1COND6 , 0x000035FBU }, + { SAFE_READONLY6 , 0x000035FBU }, + + { SEC_SEL7 , 0xFFFFFFFFU }, + { SEC_GRP0COND7 , 0x00000000U }, + { SEC_GRP1COND7 , 0x00000000U }, + { SEC_READONLY7 , 0x00000000U }, + { SAFE_GRP0COND7 , 0x00000000U }, + { SAFE_GRP1COND7 , 0x00000000U }, + { SAFE_READONLY7 , 0x00000000U }, + + { SEC_SEL8 , 0xFFFFFFFFU }, + { SEC_GRP0COND8 , 0x00000000U }, + { SEC_GRP1COND8 , 0x00000000U }, + { SEC_READONLY8 , 0x00000000U }, + { SAFE_GRP0COND8 , 0x00000000U }, + { SAFE_GRP1COND8 , 0x00000000U }, + { SAFE_READONLY8 , 0x00000000U }, + + { SEC_SEL9 , 0xFFFFFFFFU }, + { SEC_GRP0COND9 , 0x00000000U }, + { SEC_GRP1COND9 , 0x00000000U }, + { SEC_READONLY9 , 0x00000000U }, + { SAFE_GRP0COND9 , 0x00000000U }, + { SAFE_GRP1COND9 , 0x00000000U }, + { SAFE_READONLY9 , 0x00000000U }, + + { SEC_SEL10 , 0xFFFFFFFFU }, + { SEC_GRP0COND10 , 0x00000000U }, + { SEC_GRP1COND10 , 0x00000000U }, + { SEC_READONLY10 , 0x00000000U }, + { SAFE_GRP0COND10 , 0x00000000U }, + { SAFE_GRP1COND10 , 0x00000000U }, + { SAFE_READONLY10 , 0x00000000U }, + + { SEC_SEL11 , 0xFFFFFFFFU }, + { SEC_GRP0COND11 , 0x03000000U }, + { SEC_GRP1COND11 , 0x00000000U }, + { SEC_READONLY11 , 0x00000000U }, + { SAFE_GRP0COND11 , 0xE3000000U }, + { SAFE_GRP1COND11 , 0xE0000000U }, + { SAFE_READONLY11 , 0xE0000000U }, + + { SEC_SEL12 , 0xFFFFFFFFU }, + { SEC_GRP0COND12 , 0x06884001U }, + { SEC_GRP1COND12 , 0x00000000U }, + { SEC_READONLY12 , 0x00000000U }, + { SAFE_GRP0COND12 , 0x07F8C001U }, + { SAFE_GRP1COND12 , 0x01708000U }, + { SAFE_READONLY12 , 0x0170C000U }, + + { SEC_SEL13 , 0xFFFFFFFFU }, + { SEC_GRP0COND13 , 0x01407018U }, + { SEC_GRP1COND13 , 0x00000000U }, + { SEC_READONLY13 , 0x00000000U }, + { SAFE_GRP0COND13 , 0xF907F018U }, + { SAFE_GRP1COND13 , 0xF8078000U }, + { SAFE_READONLY13 , 0xF8078000U }, + + { SEC_SEL14 , 0xFFFFFFFFU }, + { SEC_GRP0COND14 , 0xD18844C4U }, + { SEC_GRP1COND14 , 0x00000000U }, + { SEC_READONLY14 , 0x00000000U }, + { SAFE_GRP0COND14 , 0xFF8A46C4U }, + { SAFE_GRP1COND14 , 0x2E020200U }, + { SAFE_READONLY14 , 0x2E020200U }, + + { SEC_SEL15 , 0xFFFFFFBFU }, + { SEC_GRP0COND15 , 0x00005208U }, + { SEC_GRP1COND15 , 0x00000000U }, + { SEC_READONLY15 , 0x00000180U }, + { SAFE_GRP0COND15 , 0x3E78BFCFU }, + { SAFE_GRP1COND15 , 0x3E78ADC7U }, + { SAFE_READONLY15 , 0x3E78AD87U }, + }; + + for (loop = 0U; + loop < (sizeof(lifec_reg_tbl) / sizeof(lifec_reg_tbl[0])); + loop++) + { + lifec_reg_write(lifec_reg_tbl[loop][0], lifec_reg_tbl[loop][1]); + } +} +/* End of function lifec_init */ + +void lifec_cr7_setting(void) +{ +#if RCAR_LIFEC_NON_SECURE_MASTER + /* Security attribute setting for master ports (CR7 Secure -> Non Secure)*/ + lifec_reg_write(SEC_SRC, 0x0000001EU); + micro_wait(10U); +#endif +} +/* End of function lifec_cr7_setting */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/llsl.s b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/llsl.s new file mode 100644 index 0000000..13a69e0 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/llsl.s @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + + .global __aeabi_llsl + +/***************************************************************************** + * long long logical shift left + * + * input: + * r0: + * r1: + * r2: + * + * output + * r0: + * r1: + *****************************************************************************/ + +__aeabi_llsl: + subs r3, r2, #32 + rsb ip, r2, #32 + movmi r1, r1, lsl r2 + movpl r1, r0, lsl r3 + orrmi r1, r1, r0, lsr ip + mov r0, r0, lsl r2 + mov pc, lr + + .end diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/llsr.s b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/llsr.s new file mode 100644 index 0000000..f524710 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/llsr.s @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + + .global __aeabi_llsr + +/***************************************************************************** + * long long logical shift right + *****************************************************************************/ + + +__aeabi_llsr: + + subs r3, r2, #32 + rsb ip, r2, #32 + movmi r0, r0, lsr r2 + movpl r0, r1, lsr r3 + orrmi r0, r0, r1, lsl ip + mov r1, r1, lsr r2 + mov pc, lr + + .end diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/mem.s b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/mem.s new file mode 100644 index 0000000..874ade1 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/mem.s @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + + + .global memcpy + .global memset + +/***************************************************************************** + * input: + * r0: dest + * r1: source + * r2: copy bytes + * + * output + * r0: dest + *****************************************************************************/ +memcpy: + mov r12, r0 /* backup dest */ + + cmp r2, #4 + bcc 2f + + and r3, r0, #0x03 + cmp r3, #0 + bne 2f /* unaligned dest address */ + + and r3, r1, #0x03 + cmp r3, #0 + bne 2f /* unaligned source address */ + +1: /* aligned copy */ + ldr r3, [r1], #4 + str r3, [r0], #4 + subs r2, r2, #4 + beq 3f + cmp r2, #4 + bcs 1b + +2: /* unaligned copy */ + ldrb r3, [r1], #1 + strb r3, [r0], #1 + subs r2, r2, #1 + bne 2b +3: + mov r0, r12 /* restore dest */ + bx lr + + +/***************************************************************************** + * input: + * r0: dest + * r1: val + * r2: count + * + * output + * r0: dest + *****************************************************************************/ +memset: + mov r12, r0 /* backup dest */ + + cmp r2, #0 + beq 2f /* no copy */ +1: + strb r1, [r0], #1 + subs r2, r2, #1 + bne 1b +2: + mov r0, r12 /* restore dest */ + bx lr + + + .end diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/mfis_init.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/mfis_init.c new file mode 100644 index 0000000..5e3e6a6 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/mfis_init.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2018-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file mfis_init.c + * - Version : 0.01 + * @brief Initial setting process of MFIS. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include "mfis_register.h" +#include "mfis.h" + +#define MFIS_EXTRQHLDCNTR_TIMER_COUNT (0x80000001U) + +void mfis_init(void) +{ + uint32_t loop; + const uint32_t mfis_tbl[][2] = { + { MFIS_MFIERRCTLR0, 0x9F7BFA00U }, + { MFIS_MFIERRCTLR1, 0x9207FAFFU }, + { MFIS_MFIERRCTLR2, 0xFFFFFFFFU }, + { MFIS_MFIERRCTLR3, 0x1FFFFFFFU }, + { MFIS_MFIERRCTLR4, 0x119EFC0BU }, + { MFIS_MFIERRCTLR5, 0x00000000U }, + { MFIS_MFIERRCTLR6, 0x00000000U }, + { MFIS_MFIERRCTLR7, 0xF8050000U }, + { MFIS_MFIERRCTLR8, 0x01E00F84U }, + { MFIS_MFIERRCTLR9, 0xFF00175FU }, + { MFIS_MFIERRCTLR10, 0x00000000U }, + { MFIS_MFIERRCTLR11, 0x00000000U }, + + { MFIS_MFIERRTGTR0, 0x80000000U }, + { MFIS_MFIERRTGTR1, 0x80000017U }, + { MFIS_MFIERRTGTR2, 0x00000000U }, + { MFIS_MFIERRTGTR3, 0x00000000U }, + { MFIS_MFIERRTGTR4, 0x00000000U }, + { MFIS_MFIERRTGTR5, 0x00000000U }, + { MFIS_MFIERRTGTR6, 0x00000000U }, + { MFIS_MFIERRTGTR7, 0x00000000U }, + { MFIS_MFIERRTGTR8, 0x00000080U }, + { MFIS_MFIERRTGTR9, 0xFF000000U }, + { MFIS_MFIERRTGTR10, 0x00000000U }, + { MFIS_MFIERRTGTR11, 0x00000000U }, + }; + + for (loop = 0U; + loop < (sizeof(mfis_tbl) / sizeof(mfis_tbl[0])); + loop++) + { + mmio_write_32((uintptr_t)mfis_tbl[loop][0], + mfis_tbl[loop][1]); + } + + mmio_write_32((uintptr_t)MFIS_MFIEXTRQHLDCNTR, + MFIS_EXTRQHLDCNTR_TIMER_COUNT); +} +/* End of function mfis_init */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/micro_wait.S b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/micro_wait.S new file mode 100644 index 0000000..d7ed376 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/micro_wait.S @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#include "micro_wait.h" + + +#define CPG_BASE (0xE6150000) +#define CPG_SMSTPCR1 (0x0134) +#define CPG_CPGWPR (0x0900) + +#define MSTPCR1_TMU1 (1 << 24) + +#define TMU3_BASE (0xE6FC0000) +#define TMU_TSTR (0x0004) +#define TMU_TCOR (0x0008) +#define TMU_TCNT (0x000C) +#define TMU_TCR (0x0010) + +#define TSTR1_TMU3 (1 << 0) + + + .globl micro_wait +#if (TMU3_MEASUREMENT == 1) + .globl init_TMU3 + .globl start_TMU3 + .globl snapshot_TCNT3 + .globl stop_TMU3 +#endif /* TMU3_MEASUREMENT */ + + .align 5 /* Aligned with the cache line */ + +micro_wait: /* Cortex-R7 800MHz */ + cmp r0, #0 + beq micro_wait_e + +micro_wait_loop_1: + ldr r1, =#310 +micro_wait_loop_2: + subs r1, r1, #1 + bne micro_wait_loop_2 + subs r0, r0, #1 + bne micro_wait_loop_1 +micro_wait_e: + bx lr + + +/* Time measurement function using the TMU3. */ +#if (TMU3_MEASUREMENT == 1) +init_TMU3: + ldr r0, =CPG_BASE + ldr r1, [r0, #CPG_SMSTPCR1] + and r1, r1, #~MSTPCR1_TMU1 + mvn r2, r1 + str r2, [r0, #CPG_CPGWPR] + str r1, [r0, #CPG_SMSTPCR1] + dsb sy + bx lr + + +start_TMU3: + ldr r0, =TMU3_BASE + mov r1, #0xFFFFFFFF + str r1, [r0, #TMU_TCNT] + + ldr r0, =TMU3_BASE + ldrb r1, [r0, #TMU_TSTR] + orr r1, r1, #TSTR1_TMU3 + strb r1, [r0, #TMU_TSTR] + bx lr + + +snapshot_TCNT3: + ldr r0, =TMU3_BASE + ldr r0, [r0, #TMU_TCNT] + bx lr + + +stop_TMU3: + ldr r0, =TMU3_BASE + ldrb r1, [r0, #TMU_TSTR] + and r1, r1, #~TSTR1_TMU3 + strb r1, [r0, #TMU_TSTR] + bx lr +#endif /* TMU3_MEASUREMENT */ + + .end diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/printf.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/printf.c new file mode 100644 index 0000000..0e4aec1 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/printf.c @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file printf.c + * - Version : 0.01 + * @brief Log output library. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include "debug.h" +#include "scif.h" + +/*********************************************************** + * tf_printf + ***********************************************************/ + +static uint32_t uint32_print(uint32_t num) +{ + uint8_t num_buf[10]; + uint32_t count = 0U; + uint32_t i = 0U; + uint32_t rem; + uint32_t unum = num; + + while(1) + { + rem = unum % 10U; + num_buf[i] = '0' + rem; + + i++; + unum = unum / 10U; + if (unum < 1U ) + { + break; + } + } + + while (i != 0U) + { + i--; + (void)console_putc(num_buf[i]); + count++; + }; + + return count; +} +/* End of function uint32_print */ + +static uint32_t int32_print(int32_t num) +{ + uint32_t unum; + uint32_t count = 0U; + + if (num < 0) + { + console_putc('-'); + count = 1U; + unum = (uint32_t)-num; + } + else + { + unum = (uint32_t)num; + } + + count += uint32_print(unum); + + return count; +} +/* End of function int32_print */ + +static uint32_t uint32_hex_print(uint32_t num) +{ + uint32_t i; + uint32_t count = 0U; + uint8_t c; + + for (i = 0U; i < 8U; i++) + { + c = (uint8_t)((num >> ((7U - i) * 4)) & 0x0FU); /* 0-F */ + if ( c >= 0x0AU) + { + c += 'a' - 0x0AU; /* A-F */ + } + else + { + c += '0'; /* 0-9 */ + } + (void)console_putc(c); + count++; + } + + return count; +} +/* End of function uint32_hex_print */ + +static uint32_t str_print(const char *str) +{ + uint32_t count = 0; + + while (*str) + { + (void)console_putc(*str); + str++; + count++; + } + + return count; +} +/* End of function str_print */ + +void tf_printf(const char *fmt, ...) +{ + va_list args; + int32_t num; + uint32_t unum; + char *str; + uint32_t count = 0U; + + va_start(args, fmt); + while (*fmt) + { + if (*fmt == '%') + { + fmt++; + switch (*fmt) + { + case 'i': + case 'd': + { + num = va_arg(args, int32_t); + count += int32_print(num); + break; + } + case 's': + { + str = va_arg(args, char *); + count += str_print(str); + break; + } + case 'x': + { + unum = va_arg(args, uint32_t); + count += uint32_hex_print(unum); + break; + } + case 'u': + { + unum = va_arg(args, uint32_t); + count += uint32_print(unum); + break; + } + default: + { + break; + } + } + } + else + { + (void)console_putc(*fmt); + count++; + } + fmt++; + } + va_end(args); +} +/* End of function tf_printf */ + +/*********************************************************** + * sprintf + ***********************************************************/ + +static uint32_t uint32_sprint(uint32_t num, char *buf) +{ + uint8_t num_buf[10]; + uint32_t count = 0U; + uint32_t i = 0U; + uint32_t rem; + uint32_t unum = num; + + while(1) + { + rem = unum % 10U; + num_buf[i] = '0' + rem; + + i++; + unum = unum / 10U; + if (unum < 1U ) + { + break; + } + } + + while (i != 0U) + { + i--; + *(buf + count) = num_buf[i]; + count++; + }; + + return count; +} +/* End of function uint32_sprint */ + +static uint32_t int32_sprint(int32_t num, char *buf) +{ + uint32_t unum; + uint32_t count = 0U; + + if (num < 0) + { + *(buf + count) = '-'; + count = 1U; + unum = (uint32_t)-num; + } + else + { + unum = (uint32_t)num; + } + + count += uint32_sprint(unum, (buf + count)); + + return count; +} +/* End of function int32_sprint */ + +static uint32_t uint32_hex_sprint(uint32_t num, char *buf) +{ + uint32_t i; + uint32_t count = 0U; + uint8_t c; + + for (i = 0U; i < 8U; i++) + { + c = (uint8_t)((num >> ((7U - i) * 4)) & 0x0FU); /* 0-F */ + if ( c >= 0x0AU) + { + c += 'a' - 0x0AU; /* A-F */ + } + else + { + c += '0'; /* 0-9 */ + } + *(buf + count) = c; + count++; + } + + return count; +} +/* End of function uint32_hex_sprint */ + +static uint32_t str_sprint(const char *str, char *buf) +{ + uint32_t count = 0; + + while (*str) + { + *(buf + count) = *str; + str++; + count++; + } + + return count; +} +/* End of function str_sprint */ + +int sprintf(char *buf, const char *fmt, ...) +{ + va_list args; + int32_t num; + uint32_t unum; + char *str; + int32_t count = 0; + + va_start(args, fmt); + + if (fmt == NULL) + { + fmt = "(fmt null)\n"; + } + + while (*fmt) + { + if (*fmt == '%') + { + fmt++; + switch (*fmt) + { + case 'i': + case 'd': + { + num = va_arg(args, int32_t); + count += int32_sprint(num, (buf + count)); + break; + } + case 's': + { + str = va_arg(args, char *); + count += str_sprint(str, (buf + count)); + break; + } + case 'x': + { + unum = va_arg(args, uint32_t); + count += uint32_hex_sprint(unum, (buf + count)); + break; + } + case 'u': + { + unum = va_arg(args, uint32_t); + count += uint32_sprint(unum, (buf + count)); + break; + } + default: + { + break; + } + } + } + else + { + *(buf + count) = *fmt; + count++; + } + fmt++; + } + *(buf + count) = '\0'; + va_end(args); + + return(count); +} +/* End of function sprintf */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/protection_setting.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/protection_setting.c new file mode 100644 index 0000000..cdac410 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/protection_setting.c @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file protection_setting.c + * - Version : 0.01 + * @brief Initial setting process of security setting. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include "axi_register.h" +#include "protection_setting.h" +#include "mmio.h" +#include "micro_wait.h" +#include "rcar_def.h" +#include "debug.h" + +#define CR7_GICD_CTLR (GICD_BASE + GICD_CTLR) +#define CR7_GICD_IGROUPR (GICD_BASE + GICD_IGROUPR) +#define CR7_GICD_ISENABLER (GICD_BASE + GICD_ISENABLER) +#define CR7_GICD_IPRIORITYR (GICD_BASE + GICD_IPRIORITYR) +#define CR7_GICD_ITARGETSR (GICD_BASE + GICD_ITARGETSR) +#define CR7_GICC_CTLR (GICC_BASE + GICC_CTLR) + +#define TARGET_CPU (0x01U) + +#define SPI_NUM (512U) + +/* LIFEC0 (SECURITY) base address */ +#define LIFEC_SEC_BASE (0xE6110000U) + +/* Security attribute setting for master ports */ +#define SEC_SRC (LIFEC_SEC_BASE + 0x0008U) + +/* SYSC Power control protection register */ +#define RCAR_SYSCPCPR (0xE618004CU) +#define SYSCPCPR_A3VP ((uint32_t)0U << 10U) +#define SYSCPCPR_A3VC ((uint32_t)0U << 9U) +#define SYSCPCPR_A2VC ((uint32_t)0U << 8U) +#define SYSCPCPR_3DG ((uint32_t)0U << 7U) +#define SYSCPCPR_CA57SCU ((uint32_t)0U << 6U) +#define SYSCPCPR_CA57CPU ((uint32_t)0U << 5U) +#define SYSCPCPR_MP_A3IR ((uint32_t)0U << 4U) +#define SYSCPCPR_A2IR_A2SC ((uint32_t)0U << 3U) +#define SYSCPCPR_CR7 ((uint32_t)1U << 2U) +#define SYSCPCPR_CA53SCU ((uint32_t)1U << 1U) +#define SYSCPCPR_CA53CPU ((uint32_t)0U << 0U) + +/* SRAM/DRAM protection setting */ +void axi_security_setting(void) +{ + int32_t i; + int32_t ie; + + /* AXI settings */ +static const struct { + uint32_t adr; + uint32_t val; +} s_axi_reg_setting[] = { + + /* DRAM protection */ + + /* AXI dram protected area division */ + {AXI_DPTDIVCR0, 0xEB040020U}, + {AXI_DPTDIVCR1, 0xEB040820U}, + {AXI_DPTDIVCR2, 0xEB041020U}, + {AXI_DPTDIVCR3, 0xEB050000U}, + {AXI_DPTDIVCR4, 0xEB050000U}, + {AXI_DPTDIVCR5, 0xEB050000U}, + {AXI_DPTDIVCR6, 0xEB050000U}, + {AXI_DPTDIVCR7, 0xEB050000U}, + {AXI_DPTDIVCR8, 0xEB050000U}, + {AXI_DPTDIVCR9, 0xEB050000U}, + {AXI_DPTDIVCR10, 0xEB050000U}, + {AXI_DPTDIVCR11, 0xEB050000U}, + {AXI_DPTDIVCR12, 0xEB050000U}, + {AXI_DPTDIVCR13, 0xEB050000U}, + {AXI_DPTDIVCR14, 0xEB050000U}, + + /* AXI dram protected area setting */ + {AXI_DPTCR0, 0xEB00BBBBU}, + {AXI_DPTCR1, 0xEB00ABABU}, + {AXI_DPTCR2, 0xEB00EBEBU}, + {AXI_DPTCR3, 0xEB00BBBBU}, + {AXI_DPTCR4, 0xEB000000U}, + {AXI_DPTCR5, 0xEB000000U}, + {AXI_DPTCR6, 0xEB000000U}, + {AXI_DPTCR7, 0xEB000000U}, + {AXI_DPTCR8, 0xEB000000U}, + {AXI_DPTCR9, 0xEB000000U}, + {AXI_DPTCR10, 0xEB000000U}, + {AXI_DPTCR11, 0xEB000000U}, + {AXI_DPTCR12, 0xEB000000U}, + {AXI_DPTCR13, 0xEB000000U}, + {AXI_DPTCR14, 0xEB000000U}, + {AXI_DPTCR15, 0xEB000000U}, + + + /* SRAM ptotection */ + + /* AXI sram protected area division */ + {AXI_SPTDIVCR0, 0xEB0E6350U}, + {AXI_SPTDIVCR1, 0xEB0E6370U}, + {AXI_SPTDIVCR2, 0xEB0E6370U}, + {AXI_SPTDIVCR3, 0xEB0E6370U}, + {AXI_SPTDIVCR4, 0xEB0E6370U}, + {AXI_SPTDIVCR5, 0xEB0E6370U}, + {AXI_SPTDIVCR6, 0xEB0E6370U}, + {AXI_SPTDIVCR7, 0xEB0E6370U}, + {AXI_SPTDIVCR8, 0xEB0E6370U}, + {AXI_SPTDIVCR9, 0xEB0E6370U}, + {AXI_SPTDIVCR10, 0xEB0E6370U}, + {AXI_SPTDIVCR11, 0xEB0E6370U}, + {AXI_SPTDIVCR12, 0xEB0E6370U}, + {AXI_SPTDIVCR13, 0xEB0E6370U}, + {AXI_SPTDIVCR14, 0xEB0E6370U}, + + /* AXI sram protected area setting */ + {AXI_SPTCR0, 0xEB00ABABU}, + {AXI_SPTCR1, 0xEB00DFDFU}, + {AXI_SPTCR2, 0xEB000000U}, + {AXI_SPTCR3, 0xEB000000U}, + {AXI_SPTCR4, 0xEB000000U}, + {AXI_SPTCR5, 0xEB000000U}, + {AXI_SPTCR6, 0xEB000000U}, + {AXI_SPTCR7, 0xEB000000U}, + {AXI_SPTCR8, 0xEB000000U}, + {AXI_SPTCR9, 0xEB000000U}, + {AXI_SPTCR10, 0xEB000000U}, + {AXI_SPTCR11, 0xEB000000U}, + {AXI_SPTCR12, 0xEB000000U}, + {AXI_SPTCR13, 0xEB000000U}, + {AXI_SPTCR14, 0xEB000000U}, + {AXI_SPTCR15, 0xEB000000U} + +}; + + + i = 0; + ie = (int32_t)(sizeof(s_axi_reg_setting) / sizeof(s_axi_reg_setting[0])); + for (; i < ie; i++) + { + mmio_write_32((uintptr_t)s_axi_reg_setting[i].adr, + s_axi_reg_setting[i].val); + + } + + micro_wait(10U); /* 10us wait */ + return; +} +/* End of function axi_security_setting */ + +void gic_security_setting(void) +{ + gicc_write_pmr(GICC_BASE, GIC_PRI_MASK); + return; +} +/* End of function gic_security_setting */ + +/* System Controller setting */ +void sysc_security_setting(void) +{ + mmio_write_32(RCAR_SYSCPCPR, SYSCPCPR_A3VP + | SYSCPCPR_A3VC + | SYSCPCPR_A2VC + | SYSCPCPR_3DG + | SYSCPCPR_CA57SCU + | SYSCPCPR_CA57CPU + | SYSCPCPR_MP_A3IR + | SYSCPCPR_A2IR_A2SC + | SYSCPCPR_CR7 + | SYSCPCPR_CA53SCU + | SYSCPCPR_CA53CPU); + + return; +} +/* End of function sysc_security_setting */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/rcar_pwrc.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/rcar_pwrc.c new file mode 100644 index 0000000..17a4985 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/rcar_pwrc.c @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/****************************************************************************** + * @file rcar_pwrc.c + * - Version : 0.1 + * @brief Boot process of ARM CPU. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include "rcar_pwrc.h" + +/****************************************************************************************************************************************************************/ +/* */ +/* Definition of R-CarGen3 register address */ +/* */ +/****************************************************************************************************************************************************************/ +/* Timer */ +#define RCAR_CNTC_BASE (0xE6080000U) /* The base addess of generic timer control register */ +/* Reset */ +#define RCAR_CPGWPR (0xE6150900U) /* CPG write protect register */ +#define RCAR_MODEMR (0xE6160060U) /* Mode pin register */ +#define RCAR_MODEMR_A (0xE6160060U) /* Mode pin register for Assembly language */ +#define RCAR_CA57RESCNT (0xE6160040U) /* Reset control register for A57 */ +#define RCAR_CA53RESCNT (0xE6160044U) /* Reset control register for A53 */ +#define RCAR_CA53WUPCR (0xE6151010U) /* Wake-up control register for A53 */ +#define RCAR_CA57WUPCR (0xE6152010U) /* Wake-up control register for A57 */ +#define RCAR_CA53PSTR (0xE6151040U) /* Power status register for A53 */ +#define RCAR_CA57PSTR (0xE6152040U) /* Power status register for A57 */ +#define RCAR_CA53CPU0CR (0xE6151100U) /* The base address of CPU power status control register for A53 */ +#define RCAR_CA57CPU0CR (0xE6152100U) /* The base address of CPU power status control register for A57 */ +#define RCAR_CA53CPUCMCR (0xE6151184U) /* Common power control register for A53 */ +#define RCAR_CA57CPUCMCR (0xE6152184U) /* Common power control register for A57 */ +#define RCAR_WUPMSKCA57 (0xE6180014U) /* Wake-up mask register for A57 */ +#define RCAR_WUPMSKCA53 (0xE6180018U) /* Wake-up mask register for A53 */ +/* SYSC */ +#define RCAR_PWRSR3 (0xE6180140U) /* Power status register CA53-SCU */ +#define RCAR_PWRSR5 (0xE61801C0U) /* Power status register CA57-SCU */ +#define RCAR_SYSCIER (0xE618000CU) /* Interrupt enable register */ +#define RCAR_SYSCIMR (0xE6180010U) /* Interrupt mask register */ +#define RCAR_SYSCSR (0xE6180000U) /* SYSC status register */ +#define RCAR_PWRONCR3 (0xE618014CU) /* Power resume control register CA53-SCU */ +#define RCAR_PWRONCR5 (0xE61801CCU) /* Power resume control register CA57-SCU */ +#define RCAR_PWRER3 (0xE6180154U) /* Power shutoff/resume error register CA53-SCU */ +#define RCAR_PWRER5 (0xE61801D4U) /* Power shutoff/resume error register CA57-SCU */ +#define RCAR_SYSCISR (0xE6180004U) /* Interrupt status register */ +#define RCAR_SYSCISCR (0xE6180008U) /* Interrupt status clear register */ + + +#define WUP_IRQ_SHIFT (0U) +#define WUP_FIQ_SHIFT (8U) +#define WUP_CSD_SHIFT (16U) + +#define BIT_CA53_SCU (1U<<21) +#define BIT_CA57_SCU (1U<<12) +#define REQ_RESUME (1U<<1) +#define REQ_OFF (1U<<0) +#define STATUS_PWRUP (1U<<1) +#define STATUS_PWRDOWN (1U<<0) + +#define STATE_CA57_CPU (27U) +#define STATE_CA53_CPU (22U) + +#define RST_CA57CPU0BARL (0xE61600C4U) +#define RST_CA57CPU0BARH (0xE61600C0U) +#define RST_CA53CPU0BARL (0xE6160084U) +#define RST_CA53CPU0BARH (0xE6160080U) + +#define MAIN_CPU_NONE (0) +#define MAIN_CPU_CA57 (1) +#define MAIN_CPU_CA53 (2) + +#define ARMREG_COMMON_0 (0xE6270000U) +#define DMS_SW ((uint32_t)1U<<4U) + +#if RCAR_KICK_MAIN_CPU == MAIN_CPU_CA57 +#define RES_REG ((uintptr_t)RCAR_CA57RESCNT) +#define ON_REG ((uintptr_t)RCAR_CA57WUPCR) +#define UPPER_VALUE ((uint32_t)0xA5A50000U) + +#define REG_SYSC_BIT ((uint32_t)BIT_CA57_SCU) +#define REG_PWRONCR ((uintptr_t)RCAR_PWRONCR5) +#define REG_PWRSR ((uintptr_t)RCAR_PWRSR5) +#define REG_PWRER ((uintptr_t)RCAR_PWRER5) + +#elif RCAR_KICK_MAIN_CPU == MAIN_CPU_CA53 +#define RES_REG ((uintptr_t)RCAR_CA53RESCNT) +#define ON_REG ((uintptr_t)RCAR_CA53WUPCR) +#define UPPER_VALUE ((uint32_t)0x5A5A0000U); + +#define REG_SYSC_BIT ((uint32_t)BIT_CA53_SCU) +#define REG_PWRONCR ((uintptr_t)RCAR_PWRONCR3) +#define REG_PWRSR ((uintptr_t)RCAR_PWRSR3) +#define REG_PWRER ((uintptr_t)RCAR_PWRER3) + +#endif + +#if (RCAR_KICK_MAIN_CPU != MAIN_CPU_NONE) +static void SCU_power_up(void); +#endif + +void rcar_pwrc_cpuon(uint32_t boot_addr) +{ +#if (RCAR_KICK_MAIN_CPU == MAIN_CPU_NONE) + return; +#else + const uint32_t cpu_no = 0U; + uint32_t res_data; + uint32_t reg; + +#if (RCAR_KICK_MAIN_CPU == MAIN_CPU_CA57) + /* CA57 boot address setting */ + mmio_write_32(RST_CA57CPU0BARL, boot_addr & 0xFFFFFFFFU); + mmio_write_32(RST_CA57CPU0BARH, ((uint64_t)boot_addr >> 32U) & 0xFFFFFFFFU); +#elif (RCAR_KICK_MAIN_CPU == MAIN_CPU_CA53) + /* CA53 boot address setting */ + mmio_write_32(RST_CA53CPU0BARL, boot_addr & 0xFFFFFFFFU); + mmio_write_32(RST_CA53CPU0BARH, ((uint64_t)boot_addr >> 32U) & 0xFFFFFFFFU); +#endif + SCU_power_up(); + + /* DMS Disable */ + reg = mmio_read_32(ARMREG_COMMON_0); + reg = (reg & ~DMS_SW); + mmio_write_32(ARMREG_COMMON_0, reg); + + mmio_write_32(RCAR_CPGWPR, ~((uint32_t)((uint32_t)1U << cpu_no))); + mmio_write_32(ON_REG, (uint32_t)((uint32_t)1U << cpu_no)); + res_data = mmio_read_32(RES_REG) | UPPER_VALUE; + mmio_write_32(RES_REG, (res_data & (~((uint32_t)1U << (3U - cpu_no))))); +#endif +} +/* End of function rcar_pwrc_cpuon */ + +#if (RCAR_KICK_MAIN_CPU != MAIN_CPU_NONE) +static void SCU_power_up() +{ + const uintptr_t reg_SYSCIER = (uintptr_t)RCAR_SYSCIER; + const uintptr_t reg_SYSCIMR = (uintptr_t)RCAR_SYSCIMR; + const uintptr_t reg_SYSCSR = (uintptr_t)RCAR_SYSCSR; + const uintptr_t reg_SYSCISR = (uintptr_t)RCAR_SYSCISR; + const uintptr_t reg_SYSCISCR = (uintptr_t)RCAR_SYSCISCR; + + if ((mmio_read_32(REG_PWRSR) & (uint32_t)STATUS_PWRDOWN) != 0x0000U) { + /* set SYSCIER and SYSCIMR */ + mmio_write_32(reg_SYSCIER, (mmio_read_32(reg_SYSCIER) | REG_SYSC_BIT)); + mmio_write_32(reg_SYSCIMR, (mmio_read_32(reg_SYSCIMR) | REG_SYSC_BIT)); + do { + /* SYSCSR[1]=1? */ + while ((mmio_read_32(reg_SYSCSR) & (uint32_t)REQ_RESUME) == 0U) { + ; + } + /* If SYSCSR[1]=1 then set bit in PWRONCRn to 1 */ + mmio_write_32(REG_PWRONCR, 0x0001U); + } while ((mmio_read_32(REG_PWRER) & 0x0001U) != 0U); + + /* bit in SYSCISR=1 ? */ + while ((mmio_read_32(reg_SYSCISR) & REG_SYSC_BIT) == 0U) { + ; + } + /* clear bit in SYSCISR */ + mmio_write_32(reg_SYSCISCR, REG_SYSC_BIT); + } +} +#endif /* (RCAR_KICK_MAIN_CPU != MAIN_CPU_NONE) */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/report_exception.s b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/report_exception.s new file mode 100644 index 0000000..40c811c --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/report_exception.s @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation. + * All rights reserved. + */ + +#define INT_ID_MASK (0x3ff) +#define ARM_IRQ_WDT_A (173) /* System watch dog timer for Assembly language */ + + .globl undef_report_exception + .globl irq_exception + .globl fiq_report_exception + .globl dabt_report_exception + .globl pabt_report_exception + + .extern swdt_exec + .extern arm_gic_acknowledge_interrupt + .extern undef_error + .extern fiq_error + .extern interrupt_error_id + .extern dabort_error + .extern pabort_error + +undef_report_exception: + b undef_error + +fiq_report_exception: + b fiq_error + +irq_exception: + bl arm_gic_acknowledge_interrupt + movw r2, #0x03FF /* INT_ID_MASK */ + and r0, r0, r2 + mov r3, #173 /* ARM_IRQ_WDT_A */ + cmp r0, r3 + moveq r0, r4 + beq swdt_exec +rep_exec_panic_id: /* interrupt id error */ + /* r0 is interrupt ID */ + b interrupt_error_id + +/******************************************************** + * abort exception + ********************************************************/ +dabt_report_exception: + mrc p15, 0, r1, c5, c0, 0 /* Read DFSR */ + mrc p15, 0, r2, c6, c0, 0 /* Read DFAR */ + bl dabort_error + +pabt_report_exception: + mrc p15, 0, r0, c5, c0, 1 /* Read IFSR */ + mrc p15, 0, r1, c6, c0, 2 /* Read IFAR */ + bl pabort_error + + .end diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/rom_api.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/rom_api.c new file mode 100644 index 0000000..0445f78 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/rom_api.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file rom_api.c + * - Version : 0.01 + * @brief 1.Call ROM_SecureBootAPI. + * 2.Call ROM_GetLcsAPI. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include "rcar_def.h" +#include "rom_api.h" + +#define V3M_API_TABLE (0U) /* V3M ES1.0 */ +#define NEW_API_TABLE (1U) /* V3M ES2.0 */ +#define API_TABLE_MAX (2U) /* table max */ + +typedef uint32_t (*ROM_SECURE_BOOT_API)(uint32_t *pKeyCert, + uint32_t *pContentCert, + ROM_FuncReadFlash pFuncReadFlash); +typedef uint32_t (*ROM_GETLCS_API)(uint32_t *pLcs); + +static uint32_t get_table_index(void); + +uint32_t ROM_SecureBootAPI( uint32_t *pKeyCert, + uint32_t *pContentCert, + ROM_FuncReadFlash pFuncReadFlash) +{ + /* Secure Boot API address table */ + static const uintptr_t ROM_SecureBootAPI_table[API_TABLE_MAX] = { + 0xEB103DECU, /* V3M ES1.0 */ + 0xEB100100U /* V3M ES2.0 or later */ + }; + + ROM_SECURE_BOOT_API func; + uint32_t index; + + index = get_table_index(); + func = (ROM_SECURE_BOOT_API)ROM_SecureBootAPI_table[index]; + + return func(pKeyCert, pContentCert, pFuncReadFlash); +} +/* End of function ROM_SecureBootAPI */ + +uint32_t ROM_GetLcs(uint32_t *pLcs) +{ + /* Get LCS stete API address table */ + static const uintptr_t ROM_GetLcs_table[API_TABLE_MAX] = { + 0xEB10404CU, /* V3M ES1.0 */ + 0xEB10010CU /* V3M ES2.0 or later */ + }; + + ROM_GETLCS_API func; + uint32_t index; + + index = get_table_index(); + func = (ROM_GETLCS_API)ROM_GetLcs_table[index]; + + return func(pLcs); +} +/* End of function ROM_GetLcs */ + +static uint32_t get_table_index(void) +{ + uint32_t cut_ver; + uint32_t index; + + cut_ver = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK; + + if (cut_ver == RCAR_CUT_VER10) { + index = V3M_API_TABLE; /* V3M ES1.0 */ + } else { + index = NEW_API_TABLE; /* V3M ES2.0 or later */ + } + + return index; +} +/* End of function get_table_index */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/rpc_driver.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/rpc_driver.c new file mode 100644 index 0000000..3a547da --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/rpc_driver.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file rpc_driver.c + * - Version : 0.01 + * @brief RPC driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include "cpg_register.h" +#include "cpg_init.h" +#include "rpc_register.h" +#include "rpc_driver.h" +#include "debug.h" + +#define RPC_PHYCNT_CAL ((uint32_t)1U << 31U) +#define RPC_DRCR_RCF ((uint32_t)1U << 9U) +#define RPC_DRCMR_CMD_MASK (0x00FF0000U) +#define RPC_DRCMR_READ_32BIT_ADDR ((uint32_t)0x13U << 16U) +#define RPC_DRENR_CDE_ENABLE ((uint32_t)0x1U << 14U) +#define RPC_DRENR_ADE_MASK (0x00000F00U) +#define RPC_DRENR_ADE_32BIT_ADDR ((uint32_t)0xFU << 8U) +#define RPC_DREAR_EAC_EXT_ADDR_25BIT ((uint32_t)0x1U << 0U) +#define RPC_PHYCNT_STRTIM ((uint32_t)0x7U << 15U) + +static void enable_rpc(void); +static void setup_rpc(void); + +static void enable_rpc(void) +{ + while((mmio_read_32(CPG_MSTPSR9) & 0x00020000U) != 0U) + { + cpg_write(CPG_SMSTPCR9, + mmio_read_32(CPG_SMSTPCR9) & (~0x00020000U)); + } +} +/* End of function enable_rpc */ + +static void setup_rpc(void) +{ + uint32_t reg; + + /* manual mode */ + if ((mmio_read_32(RPC_CMNCR) & 0x80000000U) != 0U) + { + /* external address space read mode */ + mmio_write_32(RPC_CMNCR, + mmio_read_32(RPC_CMNCR) & (~0x80000000U)); + } + + while((mmio_read_32(RPC_CMNSR) & 0x1U) != 1U) + { + /* check the transfer end flag */ + } + + /* PHY calibration */ + reg = mmio_read_32(RPC_PHYCNT); + reg |= RPC_PHYCNT_STRTIM; + mmio_write_32(RPC_PHYCNT, reg); + reg |= RPC_PHYCNT_CAL; + mmio_write_32(RPC_PHYCNT, reg); + + /* CMNCR is not set */ + /* SSLDR is not set */ + + /* Read cache Flash */ + reg = mmio_read_32(RPC_DRCR); + mmio_write_32(RPC_DRCR, (reg | RPC_DRCR_RCF)); + + /* Read 32bit addr command */ + mmio_write_32(RPC_DRCMR, RPC_DRCMR_READ_32BIT_ADDR); + + /* Extended external address valid range is [25:0]*/ + mmio_write_32(RPC_DREAR, RPC_DREAR_EAC_EXT_ADDR_25BIT); + + /* DROPR is not set */ + + /* output command is 32bit addr */ + mmio_write_32(RPC_DRENR, (RPC_DRENR_CDE_ENABLE + | RPC_DRENR_ADE_32BIT_ADDR)); + /* DRDMCR is not set */ + /* DRDRENR is not set */ +} +/* End of function setup_rpc */ + +void init_rpc(void) +{ + enable_rpc(); + setup_rpc(); +} +/* End of function init_rpc */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/scif.S b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/scif.S new file mode 100644 index 0000000..0398f35 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/scif.S @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#include + +/* Product Register */ +#define PRR (0xFFF00044) +#define PRR_PRODUCT_MASK (0x00007FFF) + +/* Pin functon */ +#if !defined PFC_BASE +#define PFC_BASE (0xE6060000) +#endif +#define PMMR (0x0000) +#define GPSR5 (0x0114) +#define IPSR12 (0x0230) +#define MOD_SEL1 (0x0504) + +/* module stop */ +#define CPG_BASE (0xE6150000) +#define CPG_SMSTPCR3 (0x013C) +#define MSTP310 (1 << 10) +#define CPG_SMSTPCR2 (0x0138) +#define MSTP207 (1 << 7) +#define CPG_CPGWPR (0x0900) +#define CPG_MSTPSR2 (0x0040) +#define CPG_RMSTPCR2 (0x0118) + +/* SCIF_BASE */ +#define SCIF_BASE (0xE6E60000) /* SCIF-0 base address */ + +#define SCIF_SCSMR (0x00) /* Serial mode register */ +#define SCIF_SCBRR (0x04) /* Bit rate register */ +#define SCIF_SCSCR (0x08) /* Serial control register */ +#define SCIF_SCFTDR (0x0C) /* Transmit FIFO data register */ +#define SCIF_SCFSR (0x10) /* Serial status register */ +#define SCIF_SCFRDR (0x14) /* Receive FIFO data register */ +#define SCIF_SCFCR (0x18) /* FIFO control register */ +#define SCIF_SCFDR (0x1C) /* FIFO data count register */ +#define SCIF_SCSPTR (0x20) /* Serial port register */ +#define SCIF_SCLSR (0x24) /* Line status register */ +#define SCIF_DL (0x30) /* Frequency division register */ +#define SCIF_CKS (0x34) /* Clock Select register */ +#define SCIF_SCSMRIR (0x40) /* Serial mode register */ + + +#define SCSMR_CA_MASK (1 << 7) +#define SCSMR_CA_ASYNC (0x0000) +#define SCSMR_CHR_MASK (1 << 6) +#define SCSMR_CHR_8 (0x0000) +#define SCSMR_PE_MASK (1 << 5) +#define SCSMR_PE_DIS (0x0000) +#define SCSMR_STOP_MASK (1 << 3) +#define SCSMR_STOP_1 (0x0000) +#define SCSMR_CKS_MASK (3 << 0) +#define SCSMR_CKS_DIV1 (0x0000) +#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + SCSMR_CHR_8 + \ + SCSMR_PE_DIS + SCSMR_STOP_1 + \ + SCSMR_CKS_DIV1) + +#define SCBRR_230400BPS (8) /* 230400bps@66MHz */ +#define SCBRR_115200BPS (17) /* 115200bps@66MHz */ +#define SCBRR_INIT_DATA (SCBRR_230400BPS) + +#define SCSCR_TE_MASK (1 << 5) +#define SCSCR_TE_DIS (0x0000) +#define SCSCR_TE_EN (0x0020) +#define SCSCR_RE_MASK (1 << 4) +#define SCSCR_RE_DIS (0x0000) +#define SCSCR_RE_EN (0x0010) +#define SCSCR_CKE_MASK (3 << 0) +#define SCSCR_CKE_INT (0x0000) +#define SCSCR_CKE_BRG (0x0002) +#if SCIF_CLK == SCIF_EXTARNAL_CLK +#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG) +#else +#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT) +#endif + +#define SCFSR_INIT_DATA (0x0000) + +#define SCFCR_TTRG_MASK (3 << 4) +#define SCFCR_TTRG_8 (0x0000) +#define SCFCR_TTRG_0 (0x0030) +#define SCFCR_TFRST_MASK (1 << 2) +#define SCFCR_TFRST_DIS (0x0000) +#define SCFCR_TFRST_EN (0x0004) +#define SCFCR_RFRS_MASK (1 << 1) +#define SCFCR_RFRS_DIS (0x0000) +#define SCFCR_RFRS_EN (0x0002) +#define SCFCR_INIT_DATA (SCFCR_TTRG_8) + +#define SCFDR_T_MASK (0x1f << 8) + +#define DL_INIT_DATA (8) /* 14.7456MHz/(115200bps*16)*/ + +#define CKS_CKS_DIV_MASK (1 << 15) +#define CKS_CKS_DIV_CLK (0x0000) +#define CKS_XIN_MASK (1 << 14) +#define CKS_XIN_SCIF_CLK (0x0000) +#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK) + +#define GPSR5_MASK (3 << 10) +#define GPSR5_RX2_A (1 << 11) +#define GPSR5_TX2_A (1 << 10) +#define GPSR5_SCK2 (1 << 9) +#if SCIF_CLK == SCIF_EXTARNAL_CLK +#define GPSR5_INIT_DATA (GPSR5_RX2_A + GPSR5_TX2_A + GPSR5_SCK2) +#else +#define GPSR5_INIT_DATA (GPSR5_RX2_A + GPSR5_TX2_A) +#endif + +#define IPSR12_MASK (255 << 0) +#define IPSR12_RX2_A (0 << 4) +#define IPSR12_TX2_A (0 << 0) +#define IPSR12_INIT_DATA (IPSR12_RX2_A + IPSR12_TX2_A) + +#define MOD_SEL1_SCIF2_MASK (1 << 12) +#define MOD_SEL1_SCIF2 (0 << 12) + + + + .global console_init + .global console_putc + .global console_wait + .global micro_wait + +console_init: + ldr r0, =CPG_BASE + ldr r1, [r0, #CPG_RMSTPCR2] + and r1, r1, #~MSTP207 /* MSTP207=0 */ + mvn r2, r1 + str r2, [r0, #CPG_CPGWPR] + str r1, [r0, #CPG_RMSTPCR2] +4: + ldr r1, [r0, #CPG_MSTPSR2] + and r1, r1, #MSTP207 + cmp r1, #0 + bne 4b + ldr r0, =SCIF_BASE + mov r1, #0 + strh r1, [r0, #SCIF_SCSMRIR] + /* Clear bits TE and RE in SCSCR to 0 */ + mov r1, #(SCSCR_TE_DIS + SCSCR_RE_DIS) /* TE=0,RE=0 */ + strh r1, [r0, #SCIF_SCSCR] + /* Set bits TFRST and RFRST in SCFCR to 1 */ + ldrh r1, [r0, #SCIF_SCFCR] + orr r1, r1, #(SCFCR_TFRST_EN + SCFCR_RFRS_EN) /* TFRESET=1,RFRESET=1 */ + strh r1, [r0, #SCIF_SCFCR] + /* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER in SCLSR, then clear them to 0 */ + mov r1, #SCFSR_INIT_DATA + strh r1, [r0, #SCIF_SCFSR] + mov r1, #0 + strh r1, [r0, #SCIF_SCLSR] + /* Set bits CKE[1:0] in SCSCR */ + ldrh r1, [r0, #SCIF_SCSCR] + and r1, r1, #~SCSCR_CKE_MASK + mov r2, #SCSCR_CKE_INT_CLK /* CKE=00 */ + orr r1, r1, r2 + strh r1, [r0, #SCIF_SCSCR] + /* Set data transfer format in SCSMR */ + mov r1, #SCSMR_INIT_DATA + strh r1, [r0, #SCIF_SCSMR] /* CA=0,CHR=0,PE=0,STOP=0,CKS=P */ + /* Set value in SCBRR */ +#if SCIF_CLK == SCIF_INTERNAL_CLK + mov r1, #SCBRR_115200BPS /* 115200bps */ + strb r1, [r0, #SCIF_SCBRR] +#else + mov r1, #DL_INIT_DATA + strh r1, [r0, #SCIF_DL] + mov r1, #CKS_INIT_DATA /* CKS=0,XIN=0 */ + strh r1, [r0, #SCIF_CKS] +#endif + /* 1-bit interval elapsed */ + mov r1, #100 /* 100 times */ +1: + subs r1, r1, #1 + bne 1b + /* Set bits RTRG[1:0], TTRG[1:0], and MCE in SCFCR, and clear bits FRST and RFRST to 0 */ + mov r1, #SCFCR_INIT_DATA + strh r1, [r0, #SCIF_SCFCR] + /* Set bits TE and RE in SCSCR to 1 */ + ldrh r1, [r0, #SCIF_SCSCR] + orr r1, r1, #(SCSCR_TE_EN + SCSCR_RE_EN) /* TE=1,RE=1 */ + strh r1, [r0, #SCIF_SCSCR] + mov r1, #1 + + bx lr + + +console_putc: + ldr r1, =SCIF_BASE + cmp r0, #0xA + /* Prepend '\r' to '\n' */ + bne 2f +1: + /* Check if the transmit FIFO is full */ + ldrh r2, [r1, #SCIF_SCFDR] + ubfx r2, r2, #8, #5 + cmp r2, #16 + bcs 1b + mov r2, #0x0D + strb r2, [r1, #SCIF_SCFTDR] +2: + /* Check if the transmit FIFO is full */ + ldrh r2, [r1, #SCIF_SCFDR] + ubfx r2, r2, #8, #5 + cmp r2, #16 + bcs 2b + strb r0, [r1, #SCIF_SCFTDR] + + bx lr + + +console_wait: + ldr r1, =SCIF_BASE +1: + ldrh r2, [r1, #SCIF_SCFDR] + ubfx r2, r2, #8, #5 + cmp r2, #0 + bne 1b + + mov r0, #100 + push {r6, lr} + bl micro_wait + pop {r6, lr} + bx lr + + + .end diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/swdt.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/swdt.c new file mode 100644 index 0000000..3db54e0 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/swdt.c @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file swdt.c + * - Version : 0.01 + * @brief SWDT driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include "swdt.h" +#include "rcar_def.h" +#include "cpsr_acc.h" + +/* Use WDT Regsiters */ +#define RST_BASE (0xE6160000U) +#define RST_WDTRSTCR (RST_BASE + 0x0054U) +#define SWDT_BASE (0xE6030000U) +#define SWDT_WTCNT (SWDT_BASE + 0x0000U) +#define SWDT_WTCSRA (SWDT_BASE + 0x0004U) +#define SWDT_WTCSRB (SWDT_BASE + 0x0008U) + +/* Use GIC Regsiters */ +#define SWDT_GICD_CTLR (GICD_BASE + GICD_CTLR) +#define SWDT_GICD_IGROUPR (GICD_BASE + GICD_IGROUPR) +#define SWDT_GICD_ISPRIORITYR (GICD_BASE + GICD_IPRIORITYR) +#define SWDT_GICD_ITARGETSR (GICD_BASE + GICD_ITARGETSR) +#define SWDT_GICC_CTLR (GICC_BASE + GICC_CTLR) +#define SWDT_GICC_PMR (GICC_BASE + GICC_PMR) +/* GIC Parameter */ +#define IGROUPR_NUM (16U) +#define IGROUPR_RELSET (0xFFFFFFFF) +#define ISPRIORITY_NUM (128U) +#define ITARGET_MASK ((uint32_t)0x03U) + +/* WDT Parameter */ +#define WDTRSTCR_UPPER_BYTE (0xA55A0000U) +#define WTCSRA_UPPER_BYTE (0xA5A5A500U) +#define WTCSRB_UPPER_BYTE (0xA5A5A500U) +#define WTCNT_UPPER_BYTE (0x5A5A0000U) +#define WTCNT_RESET_VALUE (0xF488U) +#define WTCSRA_BIT_CKS (0x0007U) +#define WTCSRB_BIT_CKS (0x003FU) +#define SWDT_RSTMSK ((uint32_t)1U << 1U) +#define WTCSRA_WOVFE ((uint32_t)1U << 3U) +#define WTCSRA_WRFLG ((uint32_t)1U << 5U) +#define SWDT_ENABLE ((uint32_t)1U << 7U) + +#define WDTRSTCR_MASK_ALL (0x0000FFFFU) +#define WTCSRA_MASK_ALL (0x000000FFU) +#define WTCNT_INIT_DATA (WTCNT_UPPER_BYTE + WTCNT_RESET_VALUE) +#define WTCSRA_INIT_DATA (WTCSRA_UPPER_BYTE + 0x0FU) +#define WTCSRB_INIT_DATA (WTCSRB_UPPER_BYTE + 0x21U) + +/* WDT Timeout Setting */ +/* OSCCLK */ +#define OSCCLK_131570HZ (131570U) /* MD13=H MD14=L*/ +#define OSCCLK_130200HZ (130200U) /* other */ + +/* CKS0 setting */ +#define RPHI_1 (1U) /* 000:RPhi */ +#define RPHI_4 (4U) /* 001:RPhi4 */ +#define RPHI_16 (16U) /* 010:RPhi16 */ +#define RPHI_32 (32U) /* 011:RPhi32 */ +#define RPHI_64 (64U) /* 100:RPhi64 */ +#define RPHI_128 (128U) /* 101:RPhi128 */ +#define RPHI_1024 (1024U) /* 110:RPhi1024 */ + +#define SWTCSRA_CKS (0x00000003U) /* division ratio RPhi32*/ + +/* clock */ +/* (maicro sec / (Hz / RPhi) */ +#define CLK_131570HZ ((uint32_t)((1U * 1000U * 1000U) / (OSCCLK_131570HZ / RPHI_32))) +#define CLK_130200HZ ((uint32_t)((1U * 1000U * 1000U) / (OSCCLK_130200HZ / RPHI_32))) + + +/* SWDT over flow sec */ +#define SWDT_COUNT_SEC (5U) /* set param(1-10sec) */ + +/* SWDT over flow sec need count*/ +#define SWDT_COUNT_131570HZ ((uint32_t)((SWDT_COUNT_SEC * 1000U * 1000U) / CLK_131570HZ)) +#define SWDT_COUNT_130200HZ ((uint32_t)((SWDT_COUNT_SEC * 1000U * 1000U) / CLK_130200HZ)) + +/* SWDTCNT Setting param */ +#define SWDTCNT_131570HZ (0x10000U - SWDT_COUNT_131570HZ) +#define SWDTCNT_131570HZ_H3WS10 ((uint32_t)((0x10000U - SWDT_COUNT_131570HZ)/2U)) +#define SWDTCNT_130200HZ (0x10000U - SWDT_COUNT_130200HZ) +#define SWDTCNT_130200HZ_H3WS10 ((uint32_t)((0x10000U - SWDT_COUNT_130200HZ)/2U)) + + +#define CHECK_MD13_MD14 (0x6000U) +#define FREQ_10P0M (0x2000U) +#define FREQ_12P5M (0x4000U) +#define FREQ_8P33M (0x0000U) +#define FREQ_16P66M (0x6000U) + +#define RCAR_MODEMR (0xE6160060U) /* Mode pin register */ +#define RCAR_MODEMR_A (0xE6160060) /* Mode pin register for Assembly language */ + +/* Processer State Register*/ +#define PSR_A ((uint32_t)1U << 8U) /* Abort */ +#define PSR_I ((uint32_t)1U << 7U) /* IRQ */ +#define PSR_F ((uint32_t)1U << 6U) /* FIQ */ + + +static void swdt_disable(void); + +void swdt_init(void) +{ + uint32_t sr; + uint32_t rmsk; + uint32_t chk_data = mmio_read_32((uintptr_t)RCAR_MODEMR) + & CHECK_MD13_MD14; + + if ((mmio_read_32(SWDT_WTCSRA) & SWDT_ENABLE) != 0U) + { + /* Stop SWDT */ + mmio_write_32(SWDT_WTCSRA,WTCSRA_UPPER_BYTE); + } + + /* clock is OSC/16 and overflow interrupt is enabled */ + mmio_write_32(SWDT_WTCSRA,(WTCSRA_UPPER_BYTE | WTCSRA_WOVFE + | SWTCSRA_CKS)); + + /* Set the overflow counter */ + switch (chk_data) + { + case FREQ_8P33M: /* MD13=0 and MD14=0 */ + case FREQ_12P5M: /* MD13=0 and MD14=1 */ + { + mmio_write_32(SWDT_WTCNT,(WTCNT_UPPER_BYTE | SWDTCNT_130200HZ)); + break; + } + case FREQ_10P0M: /* MD13=1 and MD14=0 */ + { + mmio_write_32(SWDT_WTCNT,(WTCNT_UPPER_BYTE | SWDTCNT_131570HZ)); + break; + } + case FREQ_16P66M: /* MD13=1 and MD14=1 */ + { + mmio_write_32(SWDT_WTCNT,(WTCNT_UPPER_BYTE | SWDTCNT_130200HZ)); + break; + } + default: + { + /* Error */ + ERROR("CR7: MODEMR ERROR value=%x\n", chk_data); + panic(); + break; + } + } + + rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL; + mmio_write_32(RST_WDTRSTCR,(WDTRSTCR_UPPER_BYTE + | (rmsk | SWDT_RSTMSK))); + while ((mmio_read_8(SWDT_WTCSRA) & WTCSRA_WRFLG) != 0U) + { + /* Wait until the WTCNT is reflected */ + } + sr = mmio_read_32(SWDT_WTCSRA) & WTCSRA_MASK_ALL; + /* Start the System WatchDog Timer */ + mmio_write_32(SWDT_WTCSRA,(WTCSRA_UPPER_BYTE | sr | SWDT_ENABLE)); +} +/* End of function swdt_init */ + +static void swdt_disable(void) +{ + uint32_t rmsk; + uintptr_t base = (uintptr_t)GICD_BASE; + uint32_t id = (uint32_t)ARM_IRQ_WDT; + + /* Initialize the HW initial data, but SWDT is not moved */ + rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL; + mmio_write_32(RST_WDTRSTCR,(WDTRSTCR_UPPER_BYTE + | (rmsk | SWDT_RSTMSK))); + mmio_write_32(SWDT_WTCNT,WTCNT_INIT_DATA); + mmio_write_32(SWDT_WTCSRA,WTCSRA_INIT_DATA); + mmio_write_32(SWDT_WTCSRB,WTCSRB_INIT_DATA); + /* Set the interrupt clear enable register */ + gicd_set_icenabler(base, id); +} +/* End of function swdt_disable */ + +void swdt_release(void) +{ +#if RCAR_LIFEC_NON_SECURE_MASTER + uintptr_t base = (uintptr_t)GICD_BASE; +#endif + uintptr_t p_gicd_ctlr = (uintptr_t)SWDT_GICD_CTLR; + uintptr_t p_gicc_ctlr = (uintptr_t)SWDT_GICC_CTLR; + uintptr_t p_pmr = (uintptr_t)SWDT_GICC_PMR; + uintptr_t p_itargetsr = (uintptr_t)(SWDT_GICD_ITARGETSR + + (ARM_IRQ_WDT & (uint32_t)(~ITARGET_MASK))); + + aif_disable_i(); + swdt_disable(); + arm_gic_cpuif_deactivate(); +#if RCAR_LIFEC_NON_SECURE_MASTER + gicd_set_igroupr(base, ARM_IRQ_WDT); + gicd_set_ipriorityr(base, ARM_IRQ_WDT, GIC_HIGHEST_NS_PRIORITY); +#endif + mmio_write_32(p_itargetsr, 0U); + mmio_write_32(p_gicd_ctlr, 0U); + mmio_write_32(p_gicc_ctlr, 0U); + mmio_write_32(p_pmr, 0U); +} +/* End of function swdt_release */ + +void swdt_exec(uint32_t occ_add) +{ + /* Clear the interrupt request */ + arm_gic_end_of_interrupt((uint32_t)ARM_IRQ_WDT); + swdt_release(); + ERROR("\n"); + ERROR("CR7: System WDT overflow\n"); + ERROR(" Occurred address : 0x%x\n" ,occ_add); + /* Endless loop */ + panic(); +} +/* End of function swdt_exec */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/ths_init.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/ths_init.c new file mode 100644 index 0000000..c1a203c --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/common/ths_init.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2020-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file ths_init.c + * - Version : 0.01 + * @brief Initial setting process of THS. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include "ths_init.h" + +#define DEVUID0 (0xE6110040U) +#define DEVUID1 (0xE6110044U) +#define DEVUID_PROD_MASK (0x0000000FU) + +#define THS_THSCR (0xE619012CU) +#define THS_THSCR_CPCTL (0x00001000U) +#define THS_THSCR_MASK (0x000000F0U) +#define THS_THSCR_BIT16 (0x00010000U) + +static void set_val_conv(void); + +void ths_conv(void) +{ + uint32_t loop; + const uint32_t product_list[] = { + 0x231E281CU, + 0x2321C7A4U, + 0x232DB762U, + 0x232DE91EU, + 0x2336071FU, + 0x231E381CU, + 0x231A381CU, + 0x231A391FU, + 0x231DC761U + }; + + for (loop = 0U; + loop < (sizeof(product_list) / sizeof(product_list[0])); + loop++) + { + /* Judgment of affected products. */ + if (((mmio_read_32(DEVUID1) & DEVUID_PROD_MASK) == 0x00000005U) + && (mmio_read_32(DEVUID0) == product_list[loop])) + { + /* Conversion the setting value of THSCR. */ + set_val_conv(); + break; + } + } +} +/* End of function ths_conv */ + +static void set_val_conv(void) +{ + uint32_t reg; + uint32_t loop; + + const uint32_t conv_tbl[16][2] = { + {0x000000F0U, 0x00000070U}, + {0x000000D0U, 0x00000070U}, + {0x000000B0U, 0x00000070U}, + {0x00000090U, 0x00000060U}, + {0x00000070U, 0x00000050U}, + {0x00000050U, 0x00000040U}, + {0x00000030U, 0x00000030U}, + {0x00000010U, 0x00000020U}, + {0x00000000U, 0x00000010U}, + {0x00000020U, 0x00000000U}, + {0x00000040U, 0x000000F0U}, + {0x00000060U, 0x000000E0U}, + {0x00000080U, 0x000000D0U}, + {0x000000A0U, 0x000000C0U}, + {0x000000C0U, 0x000000B0U}, + {0x000000E0U, 0x00000040U}, + }; + + mmio_write_32(THS_THSCR, mmio_read_32(THS_THSCR) | THS_THSCR_CPCTL); + reg = mmio_read_32(THS_THSCR) & THS_THSCR_MASK; + + for (loop = 0U; + loop < sizeof(conv_tbl) / sizeof(conv_tbl[0]); loop++) + { + /* Judgment of conversion table. */ + if(conv_tbl[loop][0] == reg) + { + mmio_clrsetbits_32(THS_THSCR, THS_THSCR_MASK, + (conv_tbl[loop][1] | THS_THSCR_BIT16)); + break; + } + } + + mmio_write_32(THS_THSCR, mmio_read_32(THS_THSCR) & ~THS_THSCR_CPCTL); +} +/* End of function set_val_conv */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/V3M/boot_init_dram_regdef_v3m.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/V3M/boot_init_dram_regdef_v3m.h new file mode 100644 index 0000000..2529f2a --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/V3M/boot_init_dram_regdef_v3m.h @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef BOOT_INIT_DRAM_REGDEF_V3M_H_ +#define BOOT_INIT_DRAM_REGDEF_V3M_H_ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#define BIT0 0x00000001U +#define BIT1 0x00000002U +#define BIT2 0x00000004U +#define BIT3 0x00000008U +#define BIT4 0x00000010U +#define BIT5 0x00000020U +#define BIT6 0x00000040U +#define BIT7 0x00000080U +#define BIT8 0x00000100U +#define BIT9 0x00000200U +#define BIT10 0x00000400U +#define BIT11 0x00000800U +#define BIT12 0x00001000U +#define BIT13 0x00002000U +#define BIT14 0x00004000U +#define BIT15 0x00008000U +#define BIT16 0x00010000U +#define BIT17 0x00020000U +#define BIT18 0x00040000U +#define BIT19 0x00080000U +#define BIT20 0x00100000U +#define BIT21 0x00200000U +#define BIT22 0x00400000U +#define BIT23 0x00800000U +#define BIT24 0x01000000U +#define BIT25 0x02000000U +#define BIT26 0x04000000U +#define BIT27 0x08000000U +#define BIT28 0x10000000U +#define BIT29 0x20000000U +#define BIT30 0x40000000U +#define BIT31 0x80000000U + +/* DBSC registers */ + +// modified , last 2017.06.06 + +#define DBSC_V3M_DBSYSCONF1 0xE6790004U +#define DBSC_V3M_DBPHYCONF0 0xE6790010U +#define DBSC_V3M_DBKIND 0xE6790020U +#define DBSC_V3M_DBMEMCONF00 0xE6790030U +#define DBSC_V3M_DBMEMCONF01 0xE6790034U +#define DBSC_V3M_DBMEMCONF10 0xE6790040U +#define DBSC_V3M_DBMEMCONF11 0xE6790044U +#define DBSC_V3M_DBMEMCONF20 0xE6790050U +#define DBSC_V3M_DBMEMCONF21 0xE6790054U +#define DBSC_V3M_DBMEMCONF30 0xE6790060U +#define DBSC_V3M_DBMEMCONF31 0xE6790064U +#define DBSC_V3M_DBSYSCNT0 0xE6790100U +#define DBSC_V3M_DBSTATE0 0xE6790108U +#define DBSC_V3M_DBSTATE1 0xE679010CU +#define DBSC_V3M_DBACEN 0xE6790200U +#define DBSC_V3M_DBRFEN 0xE6790204U +#define DBSC_V3M_DBCMD 0xE6790208U +#define DBSC_V3M_DBWAIT 0xE6790210U +#define DBSC_V3M_DBSYSCTRL0 0xE6790280U +#define DBSC_V3M_DBTR0 0xE6790300U +#define DBSC_V3M_DBTR1 0xE6790304U +#define DBSC_V3M_DBTR2 0xE6790308U +#define DBSC_V3M_DBTR3 0xE679030CU +#define DBSC_V3M_DBTR4 0xE6790310U +#define DBSC_V3M_DBTR5 0xE6790314U +#define DBSC_V3M_DBTR6 0xE6790318U +#define DBSC_V3M_DBTR7 0xE679031CU +#define DBSC_V3M_DBTR8 0xE6790320U +#define DBSC_V3M_DBTR9 0xE6790324U +#define DBSC_V3M_DBTR10 0xE6790328U +#define DBSC_V3M_DBTR11 0xE679032CU +#define DBSC_V3M_DBTR12 0xE6790330U +#define DBSC_V3M_DBTR13 0xE6790334U +#define DBSC_V3M_DBTR14 0xE6790338U +#define DBSC_V3M_DBTR15 0xE679033CU +#define DBSC_V3M_DBTR16 0xE6790340U +#define DBSC_V3M_DBTR17 0xE6790344U +#define DBSC_V3M_DBTR18 0xE6790348U +#define DBSC_V3M_DBTR19 0xE679034CU +#define DBSC_V3M_DBTR20 0xE6790350U +#define DBSC_V3M_DBTR21 0xE6790354U +#define DBSC_V3M_DBTR22 0xE6790358U +#define DBSC_V3M_DBTR24 0xE6790360U +#define DBSC_V3M_DBTR25 0xE6790364U +#define DBSC_V3M_DBBL 0xE6790400U +#define DBSC_V3M_DBRFCNF1 0xE6790414U +#define DBSC_V3M_DBRFCNF2 0xE6790418U +#define DBSC_V3M_DBCALCNF 0xE6790424U +#define DBSC_V3M_DBRNK2 0xE6790438U +#define DBSC_V3M_DBRNK3 0xE679043CU +#define DBSC_V3M_DBRNK4 0xE6790440U +#define DBSC_V3M_DBRNK5 0xE6790444U +#define DBSC_V3M_DBPDNCNF 0xE6790450U +#define DBSC_V3M_DBODT0 0xE6790460U +#define DBSC_V3M_DBODT1 0xE6790464U +#define DBSC_V3M_DBODT2 0xE6790468U +#define DBSC_V3M_DBODT3 0xE679046CU +#define DBSC_V3M_DBADJ0 0xE6790500U +#define DBSC_V3M_DBDBICNT 0xE6790518U +#define DBSC_V3M_DBDFICUPDCNF 0xE679052CU +#define DBSC_V3M_DBDFICNT0 0xE6790604U +#define DBSC_V3M_DBPDLK0 0xE6790620U +#define DBSC_V3M_DBPDRGA0 0xE6790624U +#define DBSC_V3M_DBPDRGD0 0xE6790628U +#define DBSC_V3M_DBPDSTAT00 0xE6790630U +#define DBSC_V3M_DBDFICNT1 0xE6790644U +#define DBSC_V3M_DBPDLK1 0xE6790660U +#define DBSC_V3M_DBPDRGA1 0xE6790664U +#define DBSC_V3M_DBPDRGD1 0xE6790668U +#define DBSC_V3M_DBDFICNT2 0xE6790684U +#define DBSC_V3M_DBPDLK2 0xE67906A0U +#define DBSC_V3M_DBPDRGA2 0xE67906A4U +#define DBSC_V3M_DBPDRGD2 0xE67906A8U +#define DBSC_V3M_DBPDSTAT20 0xE67906B0U +#define DBSC_V3M_DBDFICNT3 0xE67906C4U +#define DBSC_V3M_DBPDLK3 0xE67906E0U +#define DBSC_V3M_DBPDRGA3 0xE67906E4U +#define DBSC_V3M_DBPDRGD3 0xE67906E8U +#define DBSC_V3M_DBBUS0CNF1 0xE6790804U +#define DBSC_V3M_DBCAM0CNF1 0xE6790904U +#define DBSC_V3M_DBCAM0CNF2 0xE6790908U +#define DBSC_V3M_DBCAM0STAT0 0xE6790980U +#define DBSC_V3M_DBCAM1STAT0 0xE6790990U +#define DBSC_V3M_DBBCAMDIS 0xE67909FCU +#define DBSC_V3M_DBSCHCNT0 0xE6791000U +#define DBSC_V3M_DBSCHSZ0 0xE6791010U +#define DBSC_V3M_DBSCHRW0 0xE6791020U +#define DBSC_V3M_DBSCHRW1 0xE6791024U +#define DBSC_V3M_DBSCHQOS00 0xE6791030U +#define DBSC_V3M_DBSCHQOS01 0xE6791034U +#define DBSC_V3M_DBSCHQOS02 0xE6791038U +#define DBSC_V3M_DBSCHQOS03 0xE679103CU +#define DBSC_V3M_DBSCHQOS10 0xE6791040U +#define DBSC_V3M_DBSCHQOS11 0xE6791044U +#define DBSC_V3M_DBSCHQOS12 0xE6791048U +#define DBSC_V3M_DBSCHQOS13 0xE679104CU +#define DBSC_V3M_DBSCHQOS20 0xE6791050U +#define DBSC_V3M_DBSCHQOS21 0xE6791054U +#define DBSC_V3M_DBSCHQOS22 0xE6791058U +#define DBSC_V3M_DBSCHQOS23 0xE679105CU +#define DBSC_V3M_DBSCHQOS30 0xE6791060U +#define DBSC_V3M_DBSCHQOS31 0xE6791064U +#define DBSC_V3M_DBSCHQOS32 0xE6791068U +#define DBSC_V3M_DBSCHQOS33 0xE679106CU +#define DBSC_V3M_DBSCHQOS40 0xE6791070U +#define DBSC_V3M_DBSCHQOS41 0xE6791074U +#define DBSC_V3M_DBSCHQOS42 0xE6791078U +#define DBSC_V3M_DBSCHQOS43 0xE679107CU +#define DBSC_V3M_DBSCHQOS50 0xE6791080U +#define DBSC_V3M_DBSCHQOS51 0xE6791084U +#define DBSC_V3M_DBSCHQOS52 0xE6791088U +#define DBSC_V3M_DBSCHQOS53 0xE679108CU +#define DBSC_V3M_DBSCHQOS60 0xE6791090U +#define DBSC_V3M_DBSCHQOS61 0xE6791094U +#define DBSC_V3M_DBSCHQOS62 0xE6791098U +#define DBSC_V3M_DBSCHQOS63 0xE679109CU +#define DBSC_V3M_DBSCHQOS70 0xE67910A0U +#define DBSC_V3M_DBSCHQOS71 0xE67910A4U +#define DBSC_V3M_DBSCHQOS72 0xE67910A8U +#define DBSC_V3M_DBSCHQOS73 0xE67910ACU +#define DBSC_V3M_DBSCHQOS80 0xE67910B0U +#define DBSC_V3M_DBSCHQOS81 0xE67910B4U +#define DBSC_V3M_DBSCHQOS82 0xE67910B8U +#define DBSC_V3M_DBSCHQOS83 0xE67910BCU +#define DBSC_V3M_DBSCHQOS90 0xE67910C0U +#define DBSC_V3M_DBSCHQOS91 0xE67910C4U +#define DBSC_V3M_DBSCHQOS92 0xE67910C8U +#define DBSC_V3M_DBSCHQOS93 0xE67910CCU +#define DBSC_V3M_DBSCHQOS100 0xE67910D0U +#define DBSC_V3M_DBSCHQOS101 0xE67910D4U +#define DBSC_V3M_DBSCHQOS102 0xE67910D8U +#define DBSC_V3M_DBSCHQOS103 0xE67910DCU +#define DBSC_V3M_DBSCHQOS110 0xE67910E0U +#define DBSC_V3M_DBSCHQOS111 0xE67910E4U +#define DBSC_V3M_DBSCHQOS112 0xE67910E8U +#define DBSC_V3M_DBSCHQOS113 0xE67910ECU +#define DBSC_V3M_DBSCHQOS120 0xE67910F0U +#define DBSC_V3M_DBSCHQOS121 0xE67910F4U +#define DBSC_V3M_DBSCHQOS122 0xE67910F8U +#define DBSC_V3M_DBSCHQOS123 0xE67910FCU +#define DBSC_V3M_DBSCHQOS130 0xE6791100U +#define DBSC_V3M_DBSCHQOS131 0xE6791104U +#define DBSC_V3M_DBSCHQOS132 0xE6791108U +#define DBSC_V3M_DBSCHQOS133 0xE679110CU +#define DBSC_V3M_DBSCHQOS140 0xE6791110U +#define DBSC_V3M_DBSCHQOS141 0xE6791114U +#define DBSC_V3M_DBSCHQOS142 0xE6791118U +#define DBSC_V3M_DBSCHQOS143 0xE679111CU +#define DBSC_V3M_DBSCHQOS150 0xE6791120U +#define DBSC_V3M_DBSCHQOS151 0xE6791124U +#define DBSC_V3M_DBSCHQOS152 0xE6791128U +#define DBSC_V3M_DBSCHQOS153 0xE679112CU +#define DBSC_V3M_SCFCTST0 0xE6791700U +#define DBSC_V3M_SCFCTST1 0xE6791708U +#define DBSC_V3M_SCFCTST2 0xE679170CU +#define DBSC_V3M_DBMRRDR0 0xE6791800U +#define DBSC_V3M_DBMRRDR1 0xE6791804U +#define DBSC_V3M_DBMRRDR2 0xE6791808U +#define DBSC_V3M_DBMRRDR3 0xE679180CU +#define DBSC_V3M_DBMRRDR4 0xE6791810U +#define DBSC_V3M_DBMRRDR5 0xE6791814U +#define DBSC_V3M_DBMRRDR6 0xE6791818U +#define DBSC_V3M_DBMRRDR7 0xE679181CU + +#define DBSC_V3M_CPGWPR 0xE6150900U +#define DBSC_V3M_CPGWPCR 0xE6150904U + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* BOOT_INIT_DRAM_REGDEF_V3M_H_*/ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/V3M/ddr_init_v3m.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/V3M/ddr_init_v3m.c new file mode 100644 index 0000000..2a6906a --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/V3M/ddr_init_v3m.c @@ -0,0 +1,3666 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +// +//*******************************************************************************// +// Program name : V3M DDR initial sequence // +//*******************************************************************************// +// Rev Date Content +// 0.1 2017.06.08 Start revision control +// (ref. R-CarGen3_V3Mddr_init_seq_rev0.1.docx) +// 0.2 2017.09.29 Add Initial Sequence +// init_ddr_v3m1583, init_ddr_v3m1316 +// Add Pll3 Freq Change Sequence +// pll3_freq_change_bypmode_1316, pll3_freq_change_bypmode_1583 +// 0.3 2018.07.27 Modify Initial Sequence based on UM 0.81 +// 0.4 2018.10.19 Add additinal Workaround for DRAM limitation +// 0.5 2018.10.23 Correct syntax warning strictly (add parentheses at 6 sentences of same contents) +// from: WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R6 - RegVal_R12) & 0X000000FF | RegVal_R2); +// to: WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2); +// 0.6 2019.06.19 Change the default of following registers by changing refresh rate (tREFI) from 7.8us to 3.9us. +// DBPDRGD0(DBPDRGA0=0x00000004), DBPDRGD0(DBPDRGA0=0x00000029), DBCALCNF, DBRFCNF1 +// Modified original 7.8us setting (which is comment out)as follows, +// init_ddr_v3m1600 : DBCALCNF : 0x0100200E => 0x0100200D +// init_ddr_v3m1333 : DBCALCNF : 0x0100200E => 0x0100200D +// init_ddr_v3m1333 : DBRFCNF1 : 0x00081450 => 0x0008144F +// init_ddr_v3m1316 : DBRFCNF1 : 0x0008140F => 0x0008140E +// init_ddr_v3m1316(memory size(device density): less than 8Gb) : DBPDRGD0(DBPDRGA0=0x00000004) : 0x07309EE8 => 0x07309EE7 +// init_ddr_v3m1583(memory size(device density): 8Gb) : DBPDRGD0(DBPDRGA0=0x00000004) : 0x08A0BF67 => 0x08B0BF67 +// init_ddr_v3m1580(memory size(device density): 8Gb) : DBPDRGD0(DBPDRGA0=0x00000004) : 0x08A0BF00 => 0x08B0BF00 +// init_ddr_v3m1320(memory size(device density): 8Gb) : DBPDRGD0(DBPDRGA0=0x00000004) : 0x07309F50 => 0x07409F50 +// init_ddr_v3m1316(memory size(device density): 8Gb) : DBPDRGD0(DBPDRGA0=0x00000004) : 0x07309EE7 => 0x07409EE7 +// 0.7 2021.07.05 Add refresh rate (tREFI) 1.95us. +// 0.8 2021.07.05 Add the compiler option "V3MSK_2GB" for the R-car V3M starter kit. +//*******************************************************************************// + +#include +//#include "mmio_v3m.h" +#include "boot_init_dram_regdef_v3m.h" + +#define RCAR_REF_DEFAULT (0U) +#define RCAR_REF_7800 (1U) +#define RCAR_REF_1950 (2U) + +static void WriteReg_32(uint32_t a, uint32_t v) +{ + (*(volatile uint32_t*)a) = v; +} + +static uint32_t ReadReg_32(uint32_t a) +{ + uint32_t w = (*(volatile uint32_t*)a); + return w; +} + +uint32_t init_ddr_v3m1600(void) +{ + // modified last, 2018.10.11 + uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i; + + uint32_t RegVal,j; + uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16; + uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; + +/* Initial setting ===============================================*/ + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_V3M_DBKIND,0x00000007); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001); + WriteReg_32(DBSC_V3M_DBTR0,0x0000000B); + WriteReg_32(DBSC_V3M_DBTR1,0x00000008); + WriteReg_32(DBSC_V3M_DBTR2,0x00000000); + WriteReg_32(DBSC_V3M_DBTR3,0x0000000B); + WriteReg_32(DBSC_V3M_DBTR4,0x000B000B); + WriteReg_32(DBSC_V3M_DBTR5,0x00000027); + WriteReg_32(DBSC_V3M_DBTR6,0x0000001C); + WriteReg_32(DBSC_V3M_DBTR7,0x00060006); + WriteReg_32(DBSC_V3M_DBTR8,0x00000020); + WriteReg_32(DBSC_V3M_DBTR9,0x00000006); + WriteReg_32(DBSC_V3M_DBTR10,0x0000000C); + WriteReg_32(DBSC_V3M_DBTR11,0x0000000A); //0x0000000B -> 0x0000000A + WriteReg_32(DBSC_V3M_DBTR12,0x00120012); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBTR13,0x000000D0);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBTR13,0x00000118);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_DBTR14,0x00140005); + WriteReg_32(DBSC_V3M_DBTR15,0x00050004); + WriteReg_32(DBSC_V3M_DBTR16,0x071F0305); + WriteReg_32(DBSC_V3M_DBTR17,0x040C0000); + WriteReg_32(DBSC_V3M_DBTR18,0x00000200); + WriteReg_32(DBSC_V3M_DBTR19,0x01000040); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBTR20,0x020000D8);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBTR20,0x02000120);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_DBTR21,0x00040004); + WriteReg_32(DBSC_V3M_DBBL,0x00000000); + WriteReg_32(DBSC_V3M_DBODT0,0x00000001); + WriteReg_32(DBSC_V3M_DBADJ0,0x00000001); + WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002); + WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010); + WriteReg_32(DBSC_V3M_DBBCAMDIS,0x00000001); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000046);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBSCHRW1,0x0000005E);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_SCFCTST0,0x0D050B03); //0x0D060C04 -> 0x0D050B03 + WriteReg_32(DBSC_V3M_SCFCTST1,0x0306030C); //0x0406040C -> 0x0306030C + + WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A); + WriteReg_32(DBSC_V3M_DBCMD,0x01000001); + WriteReg_32(DBSC_V3M_DBCMD,0x08000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C720); //0x0780C700 -> 0x0780C720 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); + while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08C05FF0); //tREFI=3.9us +#elif (RCAR_REF_INT == RCAR_REF_7800) + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08C0C170); //tREFI=7.8us +#elif (RCAR_REF_INT == RCAR_REF_1950) + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08C02BAC); //tREFI=1.95us +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X2D9C0B66); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X2A88C400); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X30005200); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A9C9); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000D70); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000098); //tREFI=3.9us +#elif (RCAR_REF_INT == RCAR_REF_7800) + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000018); //tREFI=7.8us +#elif (RCAR_REF_INT == RCAR_REF_1950) + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000098); //tREFI=1.95us +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X33C03C10); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181); + WriteReg_32(DBSC_V3M_DBCMD,0x08000001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0;i<4;i++) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20); + RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20); + RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20); + RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ; + if ( RegVal_R6 > 0 ) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6); + } else + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2); + } + } + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); + WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00C0); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); + WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00D8); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); +// while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00011001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00012001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00014001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00018001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0;i<4;i++) + { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B1 + i * 0x20); + RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8; + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B4 + i * 0x20); + RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B3 + i * 0x20); + RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007); + RegVal_R12 = (RegVal_R5 >> 2); + if (RegVal_R6 - RegVal_R12 > 0) + { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2); + } + else + { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2); + } + } + +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0; i< 4; i++) { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + dqsgd_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B1 + i * 0x20); + bdlcount_0c = ((ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8); + + bdlcount_0c_div2 = (bdlcount_0c >> 1); + bdlcount_0c_div4 = (bdlcount_0c >> 2); + bdlcount_0c_div8 = (bdlcount_0c >> 3); + bdlcount_0c_div16 = (bdlcount_0c >> 4); + + if (dqsgd_0c > bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8) { + if (dqsgd_0c <= bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16) { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal)); + } else { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20); + gatesl_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFFF8); + WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal|(gatesl_0c + 1))); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rdqsd_0c = (RegVal & 0x0000FF00) >> 8; + rdqsnd_0c = (RegVal & 0x00FF0000) >> 16; + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16))); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rbd_0c[0] = (RegVal ) & 0x0000001f; + rbd_0c[1] = (RegVal >> 8) & 0x0000001f; + rbd_0c[2] = (RegVal >> 16) & 0x0000001f; + rbd_0c[3] = (RegVal >> 24) & 0x0000001f; + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0); + for (j=0; j< 4; j++) { + rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); + if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; + RegVal = RegVal | (rbd_0c[j] <<8*j); + } + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rbd_0c[0] = (RegVal ) & 0x0000001f; + rbd_0c[1] = (RegVal >> 8) & 0x0000001f; + rbd_0c[2] = (RegVal >> 16) & 0x0000001f; + rbd_0c[3] = (RegVal >> 24) & 0x0000001f; + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0); + for (j=0; j< 4; j++) { + rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); + if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; + RegVal = RegVal | (rbd_0c[j] <<8*j); + } + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + } + } + } + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000002); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x07D81E37); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C720); //0x0380C700 -> 0x0380C720 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); + while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E); + + WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A); //tREFI=3.9us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080C30); //tREFI=3.9us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); //tREFI=3.9us +#elif (RCAR_REF_INT == RCAR_REF_7800) + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200D); //tREFI=7.8us, 0x0100200E => 0x0100200D + WriteReg_32(DBSC_V3M_DBRFCNF1,0x00081860); //tREFI=7.8us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); //tREFI=7.8us +#elif (RCAR_REF_INT == RCAR_REF_1950) + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A); //tREFI=1.95us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080C30); //tREFI=1.95us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010001); //tREFI=1.95us +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001); + WriteReg_32(DBSC_V3M_DBRFEN,0x00000001); + WriteReg_32(DBSC_V3M_DBACEN,0x00000001); + + WriteReg_32(0xE67F0018,0x00000001); + RegVal = ReadReg_32(0x40000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000); + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); + +#ifdef ddr_qos_init_setting // only for non qos_init:add 2018.01.25 + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00043218); + WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000000F4); + WriteReg_32(DBSC_V3M_DBSCHCNT0,0x000f0037); + WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001); + WriteReg_32(DBSC_V3M_DBSCHRW0,0x22421111); + WriteReg_32(DBSC_V3M_SCFCTST2,0x012F1123); + WriteReg_32(DBSC_V3M_DBSCHQOS00,0x00000F00); + WriteReg_32(DBSC_V3M_DBSCHQOS01,0x00000B00); + WriteReg_32(DBSC_V3M_DBSCHQOS02,0x00000000); + WriteReg_32(DBSC_V3M_DBSCHQOS03,0x00000000); + WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000300); + WriteReg_32(DBSC_V3M_DBSCHQOS41,0x000002F0); + WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000200); + WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000300); + WriteReg_32(DBSC_V3M_DBSCHQOS91,0x000002F0); + WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200); + WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS131,0x000000F0); + WriteReg_32(DBSC_V3M_DBSCHQOS132,0x000000A0); + WriteReg_32(DBSC_V3M_DBSCHQOS133,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS140,0x000000C0); + WriteReg_32(DBSC_V3M_DBSCHQOS141,0x000000B0); + WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000080); + WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS151,0x00000030); + WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000020); + WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000010); +// WriteReg_32(0xE67F0018,0X00000001); //move + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); +#endif + + return 1; +} + +uint32_t init_ddr_v3m1333(void) +{ + // modified last, 2018.10.11 + uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i; + + uint32_t RegVal,j; + uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div4, bdlcount_0c_div8; + uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; + +/* Initial setting ===============================================*/ + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_V3M_DBKIND,0x00000007); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001); + WriteReg_32(DBSC_V3M_DBTR0,0x00000009); + WriteReg_32(DBSC_V3M_DBTR1,0x00000007); + WriteReg_32(DBSC_V3M_DBTR2,0x00000000); + WriteReg_32(DBSC_V3M_DBTR3,0x00000009); + WriteReg_32(DBSC_V3M_DBTR4,0x00090009); + WriteReg_32(DBSC_V3M_DBTR5,0x00000021); + WriteReg_32(DBSC_V3M_DBTR6,0x00000018); + WriteReg_32(DBSC_V3M_DBTR7,0x00050005); + WriteReg_32(DBSC_V3M_DBTR8,0x0000001E); + WriteReg_32(DBSC_V3M_DBTR9,0x00000005); + WriteReg_32(DBSC_V3M_DBTR10,0x0000000A); + WriteReg_32(DBSC_V3M_DBTR11,0x00000009); //0x0000000A -> 0x00000009 + WriteReg_32(DBSC_V3M_DBTR12,0x00100010); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBTR13,0x000000AE);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBTR13,0x000000EA);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_DBTR14,0x00100004); + WriteReg_32(DBSC_V3M_DBTR15,0x00040004); //0x00050004 -> 0x00040004 + WriteReg_32(DBSC_V3M_DBTR16,0x051B0305); + WriteReg_32(DBSC_V3M_DBTR17,0x040C0000); + WriteReg_32(DBSC_V3M_DBTR18,0x00000200); + WriteReg_32(DBSC_V3M_DBTR19,0x01000040); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBTR20,0x020000B4);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBTR20,0x020000F0);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_DBTR21,0x00040004); + WriteReg_32(DBSC_V3M_DBBL,0x00000000); + WriteReg_32(DBSC_V3M_DBODT0,0x00000001); + WriteReg_32(DBSC_V3M_DBADJ0,0x00000001); + WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002); + WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010); + WriteReg_32(DBSC_V3M_DBBCAMDIS,0x00000001); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000046);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBSCHRW1,0x0000005E);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_SCFCTST0,0x0D050C03); //0x0E060C04 -> 0x0D050C03 + WriteReg_32(DBSC_V3M_SCFCTST1,0x0306030C); //0x0407040D -> 0x0306030C + + WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A); + WriteReg_32(DBSC_V3M_DBCMD,0x01000001); + WriteReg_32(DBSC_V3M_DBCMD,0x08000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C720); //0x0780C700 -> 0x0780C720 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); + while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X07404FAF); //Eagle board,tREFI=3.9us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X07504FAF); //V3MSK board,tREFI=3.9us,memory size : 8Gb + #endif +#elif (RCAR_REF_INT == RCAR_REF_7800) + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0740A0EF); //Eagle board,tREFI=7.8us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0750A0EF); //V3MSK board,tREFI=7.8us,memory size : 8Gb + #endif +#elif (RCAR_REF_INT == RCAR_REF_1950) + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0740238B); //Eagle board,tREFI=1.95us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0750238B); //V3MSK board,tREFI=1.95us,memory size : 8Gb + #endif +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X25580955); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X268753C0); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X30004200); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A849); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000B50); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000090); //tREFI=3.9us +#elif (RCAR_REF_INT == RCAR_REF_7800) + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000010); //tREFI=7.8us +#elif (RCAR_REF_INT == RCAR_REF_1950) + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000090); //tREFI=1.95us +#else + #error "Don't set out of range of RCAR_REWT_TRAINING." +#endif + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X33C03C10); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181); + WriteReg_32(DBSC_V3M_DBCMD,0x08000001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0;i<4;i++) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20); + RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20); + RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20); + RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ; + if ( RegVal_R6 > 0 ) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6); + } else + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2); + } + } + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); + WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00A0); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); + WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00B8); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); +// while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00011001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00012001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00014001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00018001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0;i<4;i++) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1+ i*0x20); + RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4+ i*0x20); + RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3+ i*0x20); + RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ; + RegVal_R12= (RegVal_R5 >> 2 ) ; + if ( RegVal_R6 - RegVal_R12 > 0 ) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7 + 1)&0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R6 - RegVal_R12)&0X000000FF) | RegVal_R2); + } else + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,(RegVal_R7&0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R6 + RegVal_R5 + (RegVal_R5>>1) + RegVal_R12) & 0X000000FF) | RegVal_R2 ); + } + } + +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0; i< 4; i++) { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + dqsgd_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B1 + i * 0x20); + bdlcount_0c = ((ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8); + + bdlcount_0c_div4 = (bdlcount_0c >> 2); + bdlcount_0c_div8 = (bdlcount_0c >> 3); + + if (dqsgd_0c > bdlcount_0c) { + if (dqsgd_0c <= bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div8) { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal)); + } else { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20); + gatesl_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFFF8); + WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal|(gatesl_0c + 1))); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rdqsd_0c = (RegVal & 0x0000FF00) >> 8; + rdqsnd_0c = (RegVal & 0x00FF0000) >> 16; + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div8) << 8)|((rdqsnd_0c + bdlcount_0c_div8) << 16))); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rbd_0c[0] = (RegVal ) & 0x0000001f; + rbd_0c[1] = (RegVal >> 8) & 0x0000001f; + rbd_0c[2] = (RegVal >> 16) & 0x0000001f; + rbd_0c[3] = (RegVal >> 24) & 0x0000001f; + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0); + for (j=0; j< 4; j++) { + rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div8); + if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; + RegVal = RegVal | (rbd_0c[j] <<8*j); + } + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rbd_0c[0] = (RegVal ) & 0x0000001f; + rbd_0c[1] = (RegVal >> 8) & 0x0000001f; + rbd_0c[2] = (RegVal >> 16) & 0x0000001f; + rbd_0c[3] = (RegVal >> 24) & 0x0000001f; + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0); + for (j=0; j< 4; j++) { + rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div8); + if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; + RegVal = RegVal | (rbd_0c[j] <<8*j); + } + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + } + } + } + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000002); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x07D81E37); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C720); //0x0380C700 -> 0x0380C720 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); + while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E); + + WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A); //tREFI=3.9us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080A27); //tREFI=3.9us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); //tREFI=3.9us +#elif (RCAR_REF_INT == RCAR_REF_7800) + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200D); //tREFI=7.8us, 0x0100200E => 0x0100200D + WriteReg_32(DBSC_V3M_DBRFCNF1,0x0008144F); //tREFI=7.8us, 0x00081450 => 0x0008144F + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); //tREFI=7.8us +#elif (RCAR_REF_INT == RCAR_REF_1950) + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A); //tREFI=1.95us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080A27); //tREFI=1.95us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010001); //tREFI=1.95us +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001); + WriteReg_32(DBSC_V3M_DBRFEN,0x00000001); + WriteReg_32(DBSC_V3M_DBACEN,0x00000001); + + WriteReg_32(0xE67F0018,0x00000001); + RegVal = ReadReg_32(0x40000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000); + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); + +#ifdef ddr_qos_init_setting // only for non qos_init:add 2018.01.25 + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00043218); + WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000000F4); + WriteReg_32(DBSC_V3M_DBSCHCNT0,0x000f0037); + WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001); + WriteReg_32(DBSC_V3M_DBSCHRW0,0x22421111); + WriteReg_32(DBSC_V3M_SCFCTST2,0x012F1123); + WriteReg_32(DBSC_V3M_DBSCHQOS00,0x00000F00); + WriteReg_32(DBSC_V3M_DBSCHQOS01,0x00000B00); + WriteReg_32(DBSC_V3M_DBSCHQOS02,0x00000000); + WriteReg_32(DBSC_V3M_DBSCHQOS03,0x00000000); + WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000300); + WriteReg_32(DBSC_V3M_DBSCHQOS41,0x000002F0); + WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000200); + WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000300); + WriteReg_32(DBSC_V3M_DBSCHQOS91,0x000002F0); + WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200); + WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS131,0x000000F0); + WriteReg_32(DBSC_V3M_DBSCHQOS132,0x000000A0); + WriteReg_32(DBSC_V3M_DBSCHQOS133,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS140,0x000000C0); + WriteReg_32(DBSC_V3M_DBSCHQOS141,0x000000B0); + WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000080); + WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS151,0x00000030); + WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000020); + WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000010); +// WriteReg_32(0xE67F0018,0X00000001); //move + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); +#endif + + return 1; +} + +uint32_t init_ddr_v3m1583(void) +{ + // modified last, 2018.10.11 + uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i; + + uint32_t RegVal,j; + uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16; + uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; + +/* Initial setting ===============================================*/ + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_V3M_DBKIND,0x00000007); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001); + WriteReg_32(DBSC_V3M_DBTR0,0x0000000B); + WriteReg_32(DBSC_V3M_DBTR1,0x00000008); + WriteReg_32(DBSC_V3M_DBTR2,0x00000000); + WriteReg_32(DBSC_V3M_DBTR3,0x0000000B); + WriteReg_32(DBSC_V3M_DBTR4,0x000B000B); + WriteReg_32(DBSC_V3M_DBTR5,0x00000027); + WriteReg_32(DBSC_V3M_DBTR6,0x0000001C); + WriteReg_32(DBSC_V3M_DBTR7,0x00060006); + WriteReg_32(DBSC_V3M_DBTR8,0x00000020); + WriteReg_32(DBSC_V3M_DBTR9,0x00000006); + WriteReg_32(DBSC_V3M_DBTR10,0x0000000C); + WriteReg_32(DBSC_V3M_DBTR11,0x0000000A); + WriteReg_32(DBSC_V3M_DBTR12,0x00120012); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBTR13,0x000000CE);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBTR13,0x00000116);//V3MSK board,0x00000118 -> 0x00000116 +#endif + WriteReg_32(DBSC_V3M_DBTR14,0x00130005);//0x00140005 -> 0x00130005 + WriteReg_32(DBSC_V3M_DBTR15,0x00050004); + WriteReg_32(DBSC_V3M_DBTR16,0x071F0305); + WriteReg_32(DBSC_V3M_DBTR17,0x040C0000); + WriteReg_32(DBSC_V3M_DBTR18,0x00000200); + WriteReg_32(DBSC_V3M_DBTR19,0x01000040); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBTR20,0x020000D6);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBTR20,0x0200011D);//V3MSK board,0x02000120 -> 0x0200011D +#endif + WriteReg_32(DBSC_V3M_DBTR21,0x00040004); + WriteReg_32(DBSC_V3M_DBBL,0x00000000); + WriteReg_32(DBSC_V3M_DBODT0,0x00000001); + WriteReg_32(DBSC_V3M_DBADJ0,0x00000001); + WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002); + WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010); + WriteReg_32(DBSC_V3M_DBBCAMDIS,0x00000001); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000046);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBSCHRW1,0x0000005E);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_SCFCTST0,0x0D050B03);//0x0D060C04 -> 0x0D050B03 + WriteReg_32(DBSC_V3M_SCFCTST1,0x0306030C);//0x0406040C -> 0x0306030C + + WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A); + WriteReg_32(DBSC_V3M_DBCMD,0x01000001); + WriteReg_32(DBSC_V3M_DBCMD,0x08000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C720); //0x0780C700 -> 0x0780C720 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); + while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08A05EEB);//Eagle board,tREFI=3.9us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08B05EEB);//V3MSK board,tREFI=3.9us,memory size : 8Gb + #endif +#elif (RCAR_REF_INT == RCAR_REF_7800) + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08A0BF67);//Eagle board,tREFI=7.8us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08B0BF67);//V3MSK board,tREFI=7.8us,memory size : 8Gb + #endif +#elif (RCAR_REF_INT == RCAR_REF_1950) + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08A02B29);//Eagle board,tREFI=1.95us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08B02B29);//V3MSK board,tREFI=1.95us,memory size : 8Gb + #endif +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X2D9C0B66); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X2A88B400);//0x2A88C400 -> 0x2A88B400 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X30004E00);//0x30005200 -> 0X30004E00 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A9C9); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000D70); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000098);//tREFI=3.9us +#elif (RCAR_REF_INT == RCAR_REF_7800) + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000018);//tREFI=7.8us +#elif (RCAR_REF_INT == RCAR_REF_1950) + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000098);//tREFI=1.95us +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X33C03C10); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181); + WriteReg_32(DBSC_V3M_DBCMD,0x08000001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0;i<4;i++) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20); + RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20); + RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20); + RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ; + if ( RegVal_R6 > 0 ) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6); + } else + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2); + } + } + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); + WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00C0); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); + WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00D8); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); +// while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00011001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00012001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00014001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00018001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0;i<4;i++) + { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B1 + i * 0x20); + RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8; + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B4 + i * 0x20); + RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B3 + i * 0x20); + RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007); + RegVal_R12 = (RegVal_R5 >> 2); + if (RegVal_R6 - RegVal_R12 > 0) + { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2); + } + else + { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2); + } + } + +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0; i< 4; i++) { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + dqsgd_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B1 + i * 0x20); + bdlcount_0c = ((ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8); + + bdlcount_0c_div2 = (bdlcount_0c >> 1); + bdlcount_0c_div4 = (bdlcount_0c >> 2); + bdlcount_0c_div8 = (bdlcount_0c >> 3); + bdlcount_0c_div16 = (bdlcount_0c >> 4); + + if (dqsgd_0c > bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8) { + if (dqsgd_0c <= bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16) { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal)); + } else { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20); + gatesl_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFFF8); + WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal|(gatesl_0c + 1))); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rdqsd_0c = (RegVal & 0x0000FF00) >> 8; + rdqsnd_0c = (RegVal & 0x00FF0000) >> 16; + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16))); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rbd_0c[0] = (RegVal ) & 0x0000001f; + rbd_0c[1] = (RegVal >> 8) & 0x0000001f; + rbd_0c[2] = (RegVal >> 16) & 0x0000001f; + rbd_0c[3] = (RegVal >> 24) & 0x0000001f; + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0); + for (j=0; j< 4; j++) { + rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); + if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; + RegVal = RegVal | (rbd_0c[j] <<8*j); + } + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rbd_0c[0] = (RegVal ) & 0x0000001f; + rbd_0c[1] = (RegVal >> 8) & 0x0000001f; + rbd_0c[2] = (RegVal >> 16) & 0x0000001f; + rbd_0c[3] = (RegVal >> 24) & 0x0000001f; + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0); + for (j=0; j< 4; j++) { + rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); + if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; + RegVal = RegVal | (rbd_0c[j] <<8*j); + } + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + } + } + } + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000002); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x07D81E37); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C720); //0x0380C700 -> 0x0380C720 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); + while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E); + + WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A);//tREFI=3.9us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080C0F);//tREFI=3.9us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);//tREFI=3.9us +#elif (RCAR_REF_INT == RCAR_REF_7800) + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200D);//tREFI=7.8us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x0008181E);//tREFI=7.8us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);//tREFI=7.8us +#elif (RCAR_REF_INT == RCAR_REF_1950) + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A);//tREFI=1.95us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080C0F);//tREFI=1.95us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010001);//tREFI=1.95us +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001); + WriteReg_32(DBSC_V3M_DBRFEN,0x00000001); + WriteReg_32(DBSC_V3M_DBACEN,0x00000001); + + WriteReg_32(0xE67F0018,0x00000001); + RegVal = ReadReg_32(0x40000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000); + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); + +#ifdef ddr_qos_init_setting // only for non qos_init:add 2018.01.25 + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00043218); + WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000000F4); + WriteReg_32(DBSC_V3M_DBSCHCNT0,0x000f0037); + WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001); + WriteReg_32(DBSC_V3M_DBSCHRW0,0x22421111); + WriteReg_32(DBSC_V3M_SCFCTST2,0x012F1123); + WriteReg_32(DBSC_V3M_DBSCHQOS00,0x00000F00); + WriteReg_32(DBSC_V3M_DBSCHQOS01,0x00000B00); + WriteReg_32(DBSC_V3M_DBSCHQOS02,0x00000000); + WriteReg_32(DBSC_V3M_DBSCHQOS03,0x00000000); + WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000300); + WriteReg_32(DBSC_V3M_DBSCHQOS41,0x000002F0); + WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000200); + WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000300); + WriteReg_32(DBSC_V3M_DBSCHQOS91,0x000002F0); + WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200); + WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS131,0x000000F0); + WriteReg_32(DBSC_V3M_DBSCHQOS132,0x000000A0); + WriteReg_32(DBSC_V3M_DBSCHQOS133,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS140,0x000000C0); + WriteReg_32(DBSC_V3M_DBSCHQOS141,0x000000B0); + WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000080); + WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS151,0x00000030); + WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000020); + WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000010); +// WriteReg_32(0xE67F0018,0X00000001); //move + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); +#endif + + return 1; +} + +uint32_t init_ddr_v3m1316(void) +{ + // modified last, 2018.10.11 + uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i; + + uint32_t RegVal,j; + uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div4, bdlcount_0c_div8; + uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; + +/* Initial setting ===============================================*/ + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_V3M_DBKIND,0x00000007); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001); + WriteReg_32(DBSC_V3M_DBTR0,0x00000009); + WriteReg_32(DBSC_V3M_DBTR1,0x00000007); + WriteReg_32(DBSC_V3M_DBTR2,0x00000000); + WriteReg_32(DBSC_V3M_DBTR3,0x00000009); + WriteReg_32(DBSC_V3M_DBTR4,0x00090009); + WriteReg_32(DBSC_V3M_DBTR5,0x00000021); + WriteReg_32(DBSC_V3M_DBTR6,0x00000018); + WriteReg_32(DBSC_V3M_DBTR7,0x00050005); + WriteReg_32(DBSC_V3M_DBTR8,0x0000001E); + WriteReg_32(DBSC_V3M_DBTR9,0x00000005); + WriteReg_32(DBSC_V3M_DBTR10,0x0000000A); + WriteReg_32(DBSC_V3M_DBTR11,0x00000009); + WriteReg_32(DBSC_V3M_DBTR12,0x00100010); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBTR13,0x000000AC);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBTR13,0x000000E7);//V3MSK board,0x000000EA -> 0x000000E7 +#endif + WriteReg_32(DBSC_V3M_DBTR14,0x00100004); + WriteReg_32(DBSC_V3M_DBTR15,0x00040004); + WriteReg_32(DBSC_V3M_DBTR16,0x051B0305); + WriteReg_32(DBSC_V3M_DBTR17,0x040C0000); + WriteReg_32(DBSC_V3M_DBTR18,0x00000200); + WriteReg_32(DBSC_V3M_DBTR19,0x01000040); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBTR20,0x020000B2);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBTR20,0x020000ED);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_DBTR21,0x00040004); + WriteReg_32(DBSC_V3M_DBBL,0x00000000); + WriteReg_32(DBSC_V3M_DBODT0,0x00000001); + WriteReg_32(DBSC_V3M_DBADJ0,0x00000001); + WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002); + WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010); + WriteReg_32(DBSC_V3M_DBBCAMDIS,0x00000001); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000046);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBSCHRW1,0x0000005E);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_SCFCTST0,0x0D050C03); + WriteReg_32(DBSC_V3M_SCFCTST1,0x0306030C); + + WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A); + WriteReg_32(DBSC_V3M_DBCMD,0x01000001); + WriteReg_32(DBSC_V3M_DBCMD,0x08000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C720); //0x0780C700 -> 0x0780C720 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); + while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X07304EAB);//Eagle board,tREFI=3.9us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X07404EAB);//V3MSK board,tREFI=3.9us,memory size : 8Gb + #endif +#elif (RCAR_REF_INT == RCAR_REF_7800) + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X07309EE7);//Eagle board,tREFI=7.8us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X07409EE7);//V3MSK board,tREFI=7.8us,memory size : 8Gb + #endif +#elif (RCAR_REF_INT == RCAR_REF_1950) + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X07302309);//Eagle board,tREFI=1.95us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X07402309);//V3MSK board,tREFI=1.95us,memory size : 8Gb + #endif +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X25580955); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X26873BC0);//0X268753C0 -> 0x26873BC0 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X30004200); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A849); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000B50); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000090);//tREFI=3.9us +#elif (RCAR_REF_INT == RCAR_REF_7800) + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000010);//tREFI=7.8us +#elif (RCAR_REF_INT == RCAR_REF_1950) + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000090);//tREFI=1.95us +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X33C03C10); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181); + WriteReg_32(DBSC_V3M_DBCMD,0x08000001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for(i=0;i<4;i++) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20); + RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20); + RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20); + RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ; + if ( RegVal_R6 > 0 ) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6); + } else + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2); + } + } + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); + WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00A0); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); + WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00B8); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); +// while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00011001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00012001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00014001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00018001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0;i<4;i++) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1+ i*0x20); + RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4+ i*0x20); + RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3+ i*0x20); + RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ; + RegVal_R12= (RegVal_R5 >> 2 ) ; + if ( RegVal_R6 - RegVal_R12 > 0 ) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7 + 1)&0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R6 - RegVal_R12)&0X000000FF) | RegVal_R2); + } else + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,(RegVal_R7&0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R6 + RegVal_R5 + (RegVal_R5>>1) + RegVal_R12) & 0X000000FF) | RegVal_R2 ); + } + } + +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0; i< 4; i++) { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + dqsgd_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B1 + i * 0x20); + bdlcount_0c = ((ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8); + + bdlcount_0c_div4 = (bdlcount_0c >> 2); + bdlcount_0c_div8 = (bdlcount_0c >> 3); + + if (dqsgd_0c > bdlcount_0c) { + if (dqsgd_0c <= bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div8) { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal)); + } else { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20); + gatesl_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFFF8); + WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal|(gatesl_0c + 1))); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rdqsd_0c = (RegVal & 0x0000FF00) >> 8; + rdqsnd_0c = (RegVal & 0x00FF0000) >> 16; + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div8) << 8)|((rdqsnd_0c + bdlcount_0c_div8) << 16))); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rbd_0c[0] = (RegVal ) & 0x0000001f; + rbd_0c[1] = (RegVal >> 8) & 0x0000001f; + rbd_0c[2] = (RegVal >> 16) & 0x0000001f; + rbd_0c[3] = (RegVal >> 24) & 0x0000001f; + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0); + for (j=0; j< 4; j++) { + rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div8); + if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; + RegVal = RegVal | (rbd_0c[j] <<8*j); + } + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rbd_0c[0] = (RegVal ) & 0x0000001f; + rbd_0c[1] = (RegVal >> 8) & 0x0000001f; + rbd_0c[2] = (RegVal >> 16) & 0x0000001f; + rbd_0c[3] = (RegVal >> 24) & 0x0000001f; + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0); + for (j=0; j< 4; j++) { + rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div8); + if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; + RegVal = RegVal | (rbd_0c[j] <<8*j); + } + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + } + } + } + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000002); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x07D81E37); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C720); //0x0380C700 -> 0x0380C720 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); + while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E); + + WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A);//tREFI=3.9us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080A07);//tREFI=3.9us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);//tREFI=3.9us +#elif (RCAR_REF_INT == RCAR_REF_7800) + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200D);//tREFI=7.8us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x0008140E);//tREFI=7.8us, 0x0008140F => 0x0008140E + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);//tREFI=7.8us +#elif (RCAR_REF_INT == RCAR_REF_1950) + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A);//tREFI=1.95us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080A07);//tREFI=1.95us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010001);//tREFI=1.95us +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001); + WriteReg_32(DBSC_V3M_DBRFEN,0x00000001); + WriteReg_32(DBSC_V3M_DBACEN,0x00000001); + + WriteReg_32(0xE67F0018,0x00000001); + RegVal = ReadReg_32(0x40000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000); + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); + +#ifdef ddr_qos_init_setting // only for non qos_init:add 2018.01.25 + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00043218); + WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000000F4); + WriteReg_32(DBSC_V3M_DBSCHCNT0,0x000f0037); + WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001); + WriteReg_32(DBSC_V3M_DBSCHRW0,0x22421111); + WriteReg_32(DBSC_V3M_SCFCTST2,0x012F1123); + WriteReg_32(DBSC_V3M_DBSCHQOS00,0x00000F00); + WriteReg_32(DBSC_V3M_DBSCHQOS01,0x00000B00); + WriteReg_32(DBSC_V3M_DBSCHQOS02,0x00000000); + WriteReg_32(DBSC_V3M_DBSCHQOS03,0x00000000); + WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000300); + WriteReg_32(DBSC_V3M_DBSCHQOS41,0x000002F0); + WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000200); + WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000300); + WriteReg_32(DBSC_V3M_DBSCHQOS91,0x000002F0); + WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200); + WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS131,0x000000F0); + WriteReg_32(DBSC_V3M_DBSCHQOS132,0x000000A0); + WriteReg_32(DBSC_V3M_DBSCHQOS133,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS140,0x000000C0); + WriteReg_32(DBSC_V3M_DBSCHQOS141,0x000000B0); + WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000080); + WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS151,0x00000030); + WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000020); + WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000010); +// WriteReg_32(0xE67F0018,0X00000001); //move + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); +#endif + + return 1; + +} + +uint32_t init_ddr_v3m1580(void) +{ + // modified last, 2018.10.11 + uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i; + + uint32_t RegVal,j; + uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16; + uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; + +/* Initial setting ===============================================*/ + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_V3M_DBKIND,0x00000007); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001); + WriteReg_32(DBSC_V3M_DBTR0,0x0000000B); + WriteReg_32(DBSC_V3M_DBTR1,0x00000008); + WriteReg_32(DBSC_V3M_DBTR2,0x00000000); + WriteReg_32(DBSC_V3M_DBTR3,0x0000000B); + WriteReg_32(DBSC_V3M_DBTR4,0x000B000B); + WriteReg_32(DBSC_V3M_DBTR5,0x00000027); + WriteReg_32(DBSC_V3M_DBTR6,0x0000001C); + WriteReg_32(DBSC_V3M_DBTR7,0x00060006); + WriteReg_32(DBSC_V3M_DBTR8,0x00000020); + WriteReg_32(DBSC_V3M_DBTR9,0x00000006); + WriteReg_32(DBSC_V3M_DBTR10,0x0000000C); + WriteReg_32(DBSC_V3M_DBTR11,0x0000000A); + WriteReg_32(DBSC_V3M_DBTR12,0x00120012); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBTR13,0x000000CE);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBTR13,0x00000115);//V3MSK board,0x00000116 -> 0x00000115 +#endif + WriteReg_32(DBSC_V3M_DBTR14,0x00130005); + WriteReg_32(DBSC_V3M_DBTR15,0x00050004); + WriteReg_32(DBSC_V3M_DBTR16,0x071F0305); + WriteReg_32(DBSC_V3M_DBTR17,0x040C0000); + WriteReg_32(DBSC_V3M_DBTR18,0x00000200); + WriteReg_32(DBSC_V3M_DBTR19,0x01000040); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBTR20,0x020000D6);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBTR20,0x0200011D);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_DBTR21,0x00040004); + WriteReg_32(DBSC_V3M_DBBL,0x00000000); + WriteReg_32(DBSC_V3M_DBODT0,0x00000001); + WriteReg_32(DBSC_V3M_DBADJ0,0x00000001); + WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002); + WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010); + WriteReg_32(DBSC_V3M_DBBCAMDIS,0x00000001); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000046);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBSCHRW1,0x0000005E);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_SCFCTST0,0x0D050B03); + WriteReg_32(DBSC_V3M_SCFCTST1,0x0306030C); + + WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A); + WriteReg_32(DBSC_V3M_DBCMD,0x01000001); + WriteReg_32(DBSC_V3M_DBCMD,0x08000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C720); //0x0780C700 -> 0x0780C720 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); + while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08A05EB8);//Eagle board,tREFI=3.9us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08B05EB8);//V3MSK board,tREFI=3.9us,memory size : 8Gb + #endif +#elif (RCAR_REF_INT == RCAR_REF_7800) + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08A0BF00);//Eagle board,tREFI=7.8us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08B0BF00);//V3MSK board,tREFI=7.8us,memory size : 8Gb + #endif +#elif (RCAR_REF_INT == RCAR_REF_1950) + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08A02B10);//Eagle board,tREFI=1.95us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X08B02B10);//V3MSK board,tREFI=1.95us,memory size : 8Gb + #endif +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X2D9C0B66); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X2A88AC00);//0x2A88B400 -> 0x2A88AC00 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X30004E00); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A9C9); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000D70); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000098);//tREFI=3.9us +#elif (RCAR_REF_INT == RCAR_REF_7800) + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000018); //tREFI=7.8us +#elif (RCAR_REF_INT == RCAR_REF_1950) + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000098);//tREFI=1.95us +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X33C03C10); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181); + WriteReg_32(DBSC_V3M_DBCMD,0x08000001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0;i<4;i++) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20); + RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20); + RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20); + RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ; + if ( RegVal_R6 > 0 ) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6); + } else + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2); + } + } + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); + WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00C0); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); + WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00D8); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); +// while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00011001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00012001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00014001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00018001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0;i<4;i++) + { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B1 + i * 0x20); + RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8; + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B4 + i * 0x20); + RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B3 + i * 0x20); + RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007); + RegVal_R12 = (RegVal_R5 >> 2); + if (RegVal_R6 - RegVal_R12 > 0) + { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R7 + 1) & 0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 - RegVal_R12) & 0X000000FF) | RegVal_R2); + } + else + { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B2 + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal_R7 & 0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0X000000B0 + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal_R6 + RegVal_R5 + (RegVal_R5 >> 1) + RegVal_R12) & 0X000000FF) | RegVal_R2); + } + } + +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0; i< 4; i++) { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + dqsgd_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B1 + i * 0x20); + bdlcount_0c = ((ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8); + + bdlcount_0c_div2 = (bdlcount_0c >> 1); + bdlcount_0c_div4 = (bdlcount_0c >> 2); + bdlcount_0c_div8 = (bdlcount_0c >> 3); + bdlcount_0c_div16 = (bdlcount_0c >> 4); + + if (dqsgd_0c > bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8) { + if (dqsgd_0c <= bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16) { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal)); + } else { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20); + gatesl_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFFF8); + WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal|(gatesl_0c + 1))); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rdqsd_0c = (RegVal & 0x0000FF00) >> 8; + rdqsnd_0c = (RegVal & 0x00FF0000) >> 16; + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16))); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rbd_0c[0] = (RegVal ) & 0x0000001f; + rbd_0c[1] = (RegVal >> 8) & 0x0000001f; + rbd_0c[2] = (RegVal >> 16) & 0x0000001f; + rbd_0c[3] = (RegVal >> 24) & 0x0000001f; + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0); + for (j=0; j< 4; j++) { + rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); + if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; + RegVal = RegVal | (rbd_0c[j] <<8*j); + } + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rbd_0c[0] = (RegVal ) & 0x0000001f; + rbd_0c[1] = (RegVal >> 8) & 0x0000001f; + rbd_0c[2] = (RegVal >> 16) & 0x0000001f; + rbd_0c[3] = (RegVal >> 24) & 0x0000001f; + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0); + for (j=0; j< 4; j++) { + rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); + if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; + RegVal = RegVal | (rbd_0c[j] <<8*j); + } + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + } + } + } + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000002); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x07D81E37); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C720); //0x0380C700 -> 0x0380C720 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); + while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E); + + WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A); //tREFI=3.9us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080C09); //tREFI=3.9us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); //tREFI=3.9us +#elif (RCAR_REF_INT == RCAR_REF_7800) + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200D); //tREFI=7.8us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x00081812); //tREFI=7.8us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000); //tREFI=7.8us +#elif (RCAR_REF_INT == RCAR_REF_1950) + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A); //tREFI=1.95us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080C09);//tREFI=1.95us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010001);//tREFI=1.95us +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001); + WriteReg_32(DBSC_V3M_DBRFEN,0x00000001); + WriteReg_32(DBSC_V3M_DBACEN,0x00000001); + + WriteReg_32(0xE67F0018,0x00000001); + RegVal = ReadReg_32(0x40000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000); + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); + +#ifdef ddr_qos_init_setting // only for non qos_init:add 2018.01.25 + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00043218); + WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000000F4); + WriteReg_32(DBSC_V3M_DBSCHCNT0,0x000f0037); + WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001); + WriteReg_32(DBSC_V3M_DBSCHRW0,0x22421111); + WriteReg_32(DBSC_V3M_SCFCTST2,0x012F1123); + WriteReg_32(DBSC_V3M_DBSCHQOS00,0x00000F00); + WriteReg_32(DBSC_V3M_DBSCHQOS01,0x00000B00); + WriteReg_32(DBSC_V3M_DBSCHQOS02,0x00000000); + WriteReg_32(DBSC_V3M_DBSCHQOS03,0x00000000); + WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000300); + WriteReg_32(DBSC_V3M_DBSCHQOS41,0x000002F0); + WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000200); + WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000300); + WriteReg_32(DBSC_V3M_DBSCHQOS91,0x000002F0); + WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200); + WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS131,0x000000F0); + WriteReg_32(DBSC_V3M_DBSCHQOS132,0x000000A0); + WriteReg_32(DBSC_V3M_DBSCHQOS133,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS140,0x000000C0); + WriteReg_32(DBSC_V3M_DBSCHQOS141,0x000000B0); + WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000080); + WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS151,0x00000030); + WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000020); + WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000010); +// WriteReg_32(0xE67F0018,0X00000001); //move + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); +#endif + + return 1; + +} + +uint32_t init_ddr_v3m1320(void) +{ + // modified last, 2018.10.11 + uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i; + + uint32_t RegVal,j; + uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div4, bdlcount_0c_div8; + uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; + +/* Initial setting ===============================================*/ + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_V3M_DBKIND,0x00000007); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBMEMCONF00,0x0f030a02);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBMEMCONF00,0x10030a02);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_DBPHYCONF0,0x00000001); + WriteReg_32(DBSC_V3M_DBTR0,0x00000009); + WriteReg_32(DBSC_V3M_DBTR1,0x00000007); + WriteReg_32(DBSC_V3M_DBTR2,0x00000000); + WriteReg_32(DBSC_V3M_DBTR3,0x00000009); + WriteReg_32(DBSC_V3M_DBTR4,0x00090009); + WriteReg_32(DBSC_V3M_DBTR5,0x00000021); + WriteReg_32(DBSC_V3M_DBTR6,0x00000018); + WriteReg_32(DBSC_V3M_DBTR7,0x00050005); + WriteReg_32(DBSC_V3M_DBTR8,0x0000001E); + WriteReg_32(DBSC_V3M_DBTR9,0x00000005); + WriteReg_32(DBSC_V3M_DBTR10,0x0000000A); + WriteReg_32(DBSC_V3M_DBTR11,0x00000009); + WriteReg_32(DBSC_V3M_DBTR12,0x00100010); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBTR13,0x000000AC);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBTR13,0x000000E7);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_DBTR14,0x00100004); + WriteReg_32(DBSC_V3M_DBTR15,0x00040004); + WriteReg_32(DBSC_V3M_DBTR16,0x051B0305); + WriteReg_32(DBSC_V3M_DBTR17,0x040C0000); + WriteReg_32(DBSC_V3M_DBTR18,0x00000200); + WriteReg_32(DBSC_V3M_DBTR19,0x01000040); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBTR20,0x020000B3);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBTR20,0x020000EE);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_DBTR21,0x00040004); + WriteReg_32(DBSC_V3M_DBBL,0x00000000); + WriteReg_32(DBSC_V3M_DBODT0,0x00000001); + WriteReg_32(DBSC_V3M_DBADJ0,0x00000001); + WriteReg_32(DBSC_V3M_DBSYSCONF1,0x00000002); + WriteReg_32(DBSC_V3M_DBDFICNT0,0x00000010); + WriteReg_32(DBSC_V3M_DBBCAMDIS,0x00000001); +#if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBSCHRW1,0x00000046);//Eagle board +#else + WriteReg_32(DBSC_V3M_DBSCHRW1,0x0000005E);//V3MSK board +#endif + WriteReg_32(DBSC_V3M_SCFCTST0,0x0D050C03); + WriteReg_32(DBSC_V3M_SCFCTST1,0x0306030C); + + WriteReg_32(DBSC_V3M_DBPDLK0,0X0000A55A); + WriteReg_32(DBSC_V3M_DBCMD,0x01000001); + WriteReg_32(DBSC_V3M_DBCMD,0x08000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X80010000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000B8000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058904); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000091); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000095); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6B); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000099); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0007BB6D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024641E); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010073); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0C058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000090); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X04058900); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0780C720); //0x0780C700 -> 0x0780C720 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); + while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000004); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X07304EE0);//Eagle board,tREFI=3.9us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X07404EE0);//V3MSK board,tREFI=3.9us,memory size : 8Gb + #endif +#elif (RCAR_REF_INT == RCAR_REF_7800) + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X07309F50);//Eagle board,tREFI=7.8us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X07409F50);//V3MSK board,tREFI=7.8us,memory size : 8Gb + #endif +#elif (RCAR_REF_INT == RCAR_REF_1950) + #if V3MSK_2GB == 0 + WriteReg_32(DBSC_V3M_DBPDRGD0,0X07302324);//Eagle board,tREFI=1.95us,memory size : less than 8Gb + #else + WriteReg_32(DBSC_V3M_DBPDRGD0,0X07402324);//V3MSK board,tREFI=1.95us,memory size : 8Gb + #endif +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000022); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X1000040B); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000023); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X25580955); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000024); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X26873BC0); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000025); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X30004200); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000026); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0014A849); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000027); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000B50); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000028); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000004); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000029); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000090);//tREFI=3.9us +#elif (RCAR_REF_INT == RCAR_REF_7800) + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000010);//tREFI=7.8us +#elif (RCAR_REF_INT == RCAR_REF_1950) + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00000090);//tREFI=1.95us +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003047); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000020); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00181884); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000001A); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X33C03C10); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E7); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E8); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E9); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000107); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000108); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0D0D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000109); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X000D0D0D); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010181); + WriteReg_32(DBSC_V3M_DBCMD,0x08000001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010601); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for(i=0;i<4;i++) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1 + i*0x20); + RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4 + i*0x20); + RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3 + i*0x20); + RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ; + if ( RegVal_R6 > 0 ) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7+1)&0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R6); + } else + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal_R2 | RegVal_R7); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0 + i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,(((RegVal_R5<<1) + RegVal_R6 ) & 0X000000FF )| RegVal_R2); + } + } + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); + WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00A0); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010801); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000005); + WriteReg_32(DBSC_V3M_DBPDRGD0,0XC1AA00B8); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X0001F001); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); +// while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00011001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00012001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C000285); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00014001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00018001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C000285); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X0000002C); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X81003087); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00010401); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0;i<4;i++) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B1+ i*0x20); + RegVal_R5 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00 ) >> 8; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B4+ i*0x20); + RegVal_R6 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B3+ i*0x20); + RegVal_R7 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007 ) ; + RegVal_R12= (RegVal_R5 >> 2 ) ; + if ( RegVal_R6 - RegVal_R12 > 0 ) + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R7 + 1)&0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R6 - RegVal_R12)&0X000000FF) | RegVal_R2); + } else + { + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFFF8 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B2+ i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,(RegVal_R7&0X00000007) | RegVal_R2); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20); + RegVal_R2 = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0XFFFFFF00 ) ; + WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000B0+ i*0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0,((RegVal_R6 + RegVal_R5 + (RegVal_R5>>1) + RegVal_R12) & 0X000000FF) | RegVal_R2 ); + } + } + +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000A0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000C0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X000000E0); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); +// WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000100); +// WriteReg_32(DBSC_V3M_DBPDRGD0,0X7C0002C5); + +// PDR always off add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000008); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000001); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X00015001); + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000006); + while ( (BIT0 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + for (i=0; i< 4; i++) { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + dqsgd_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x000000FF); + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B1 + i * 0x20); + bdlcount_0c = ((ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x0000FF00) >> 8); + + bdlcount_0c_div4 = (bdlcount_0c >> 2); + bdlcount_0c_div8 = (bdlcount_0c >> 3); + + if (dqsgd_0c > bdlcount_0c) { + if (dqsgd_0c <= bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div8) { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal)); + } else { + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B0 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFF00); + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20); + gatesl_0c = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0x00000007); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000B2 + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xFFFFFFF8); + WriteReg_32(DBSC_V3M_DBPDRGD0, (RegVal|(gatesl_0c + 1))); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rdqsd_0c = (RegVal & 0x0000FF00) >> 8; + rdqsnd_0c = (RegVal & 0x00FF0000) >> 16; + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AF + i * 0x20); + WriteReg_32(DBSC_V3M_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div8) << 8)|((rdqsnd_0c + bdlcount_0c_div8) << 16))); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rbd_0c[0] = (RegVal ) & 0x0000001f; + rbd_0c[1] = (RegVal >> 8) & 0x0000001f; + rbd_0c[2] = (RegVal >> 16) & 0x0000001f; + rbd_0c[3] = (RegVal >> 24) & 0x0000001f; + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AA + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0); + for (j=0; j< 4; j++) { + rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div8); + if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; + RegVal = RegVal | (rbd_0c[j] <<8*j); + } + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0)); + rbd_0c[0] = (RegVal ) & 0x0000001f; + rbd_0c[1] = (RegVal >> 8) & 0x0000001f; + rbd_0c[2] = (RegVal >> 16) & 0x0000001f; + rbd_0c[3] = (RegVal >> 24) & 0x0000001f; + + WriteReg_32(DBSC_V3M_DBPDRGA0, 0x000000AB + i * 0x20); + RegVal = (ReadReg_32(DBSC_V3M_DBPDRGD0) & 0xE0E0E0E0); + for (j=0; j< 4; j++) { + rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div8); + if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; + RegVal = RegVal | (rbd_0c[j] <<8*j); + } + WriteReg_32(DBSC_V3M_DBPDRGD0, RegVal); + } + } + } + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000002); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x07D81E37); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000003); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0380C720); //0x0380C700 -> 0x0380C720 + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000007); + while ( (BIT30& ReadReg_32(DBSC_V3M_DBPDRGD0)) != 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0X00000021); + WriteReg_32(DBSC_V3M_DBPDRGD0,0X0024643E); + + WriteReg_32(DBSC_V3M_DBBUS0CNF1,0x00000000); +#if (RCAR_REF_INT == RCAR_REF_DEFAULT) //REF 3.9usec + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A);//tREFI=3.9us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080A0E);//tREFI=3.9us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);//tREFI=3.9us +#elif (RCAR_REF_INT == RCAR_REF_7800) + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100200D);//tREFI=7.8us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x0008141C);//tREFI=7.8us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010000);//tREFI=7.8us +#elif (RCAR_REF_INT == RCAR_REF_1950) + WriteReg_32(DBSC_V3M_DBCALCNF,0x0100401A);//tREFI=1.95us + WriteReg_32(DBSC_V3M_DBRFCNF1,0x00080A0E);//tREFI=1.95us + WriteReg_32(DBSC_V3M_DBRFCNF2,0x00010001);//tREFI=1.95us +#else + #error "Don't set out of range of RCAR_REF_INT." +#endif + WriteReg_32(DBSC_V3M_DBDFICUPDCNF,0x40100001); + WriteReg_32(DBSC_V3M_DBRFEN,0x00000001); + WriteReg_32(DBSC_V3M_DBACEN,0x00000001); + + WriteReg_32(0xE67F0018,0x00000001); + RegVal = ReadReg_32(0x40000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGD0,RegVal); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E0); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000100); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x7C0002C5); + +// PDR default(dynamic) add 2018/10/11 + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000C3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E3); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000103); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x00000000); + + WriteReg_32(DBSC_V3M_DBPDLK0,0X00000000); + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); + +#ifdef ddr_qos_init_setting // only for non qos_init:add 2018.01.25 + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_V3M_DBCAM0CNF1,0x00043218); + WriteReg_32(DBSC_V3M_DBCAM0CNF2,0x000000F4); + WriteReg_32(DBSC_V3M_DBSCHCNT0,0x000f0037); + WriteReg_32(DBSC_V3M_DBSCHSZ0,0x00000001); + WriteReg_32(DBSC_V3M_DBSCHRW0,0x22421111); + WriteReg_32(DBSC_V3M_SCFCTST2,0x012F1123); + WriteReg_32(DBSC_V3M_DBSCHQOS00,0x00000F00); + WriteReg_32(DBSC_V3M_DBSCHQOS01,0x00000B00); + WriteReg_32(DBSC_V3M_DBSCHQOS02,0x00000000); + WriteReg_32(DBSC_V3M_DBSCHQOS03,0x00000000); + WriteReg_32(DBSC_V3M_DBSCHQOS40,0x00000300); + WriteReg_32(DBSC_V3M_DBSCHQOS41,0x000002F0); + WriteReg_32(DBSC_V3M_DBSCHQOS42,0x00000200); + WriteReg_32(DBSC_V3M_DBSCHQOS43,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS90,0x00000300); + WriteReg_32(DBSC_V3M_DBSCHQOS91,0x000002F0); + WriteReg_32(DBSC_V3M_DBSCHQOS92,0x00000200); + WriteReg_32(DBSC_V3M_DBSCHQOS93,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS130,0x00000100); + WriteReg_32(DBSC_V3M_DBSCHQOS131,0x000000F0); + WriteReg_32(DBSC_V3M_DBSCHQOS132,0x000000A0); + WriteReg_32(DBSC_V3M_DBSCHQOS133,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS140,0x000000C0); + WriteReg_32(DBSC_V3M_DBSCHQOS141,0x000000B0); + WriteReg_32(DBSC_V3M_DBSCHQOS142,0x00000080); + WriteReg_32(DBSC_V3M_DBSCHQOS143,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS150,0x00000040); + WriteReg_32(DBSC_V3M_DBSCHQOS151,0x00000030); + WriteReg_32(DBSC_V3M_DBSCHQOS152,0x00000020); + WriteReg_32(DBSC_V3M_DBSCHQOS153,0x00000010); +// WriteReg_32(0xE67F0018,0X00000001); //move + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); +#endif + + return 1; + +} + +uint32_t pll3_freq_change_bypmode_1316(void) +{ +/* CPG & PHY setting ===============================================*/ + while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 ); + WriteReg_32(DBSC_V3M_CPGWPR,0x5A5AFFFF); + WriteReg_32(DBSC_V3M_CPGWPCR,0xA5A50000); + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_V3M_DBPDLK0,0x0000A55A); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x802F8800); + while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x802B8000); + + WriteReg_32(0xE6150380,0x00000C00); + WriteReg_32(0xE61500DC,0x4E000000); + while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 ); + WriteReg_32(0xE61500E4,0x00000000); + WriteReg_32(0xE6150004,0x80321235); + while ( (BIT31 & ReadReg_32(0xE6150004)) == 1 ); + while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 ); + WriteReg_32(0xE61500E4,0x00040202); + WriteReg_32(0xE6150004,0x80321235); + while ( (BIT31 & ReadReg_32(0xE6150004)) == 1 ); + WriteReg_32(0xE6150380,0x00000000); + while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x002F8800); + + /*== add 20171106 ====================================*/ + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + /*====================================================*/ + + while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 ); + + /*== add 20171106 ====================================*/ + while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 ); + /*====================================================*/ + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x000F8800); + + /*== add 20171106 ====================================*/ + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + /*====================================================*/ + + while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 ); + + /*== add 20171106 ====================================*/ + while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 ); + /*====================================================*/ + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x000F8000); + while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 ); + /*== add 20171106 ====================================*/ + while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 ); + /*====================================================*/ + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x000B8000); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + WriteReg_32(DBSC_V3M_CPGWPCR,0xA5A50001); + WriteReg_32(DBSC_V3M_DBPDLK0,0x00000000); + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); + + return 1; + +} + +uint32_t pll3_freq_change_bypmode_1583(void) +{ +/* CPG & PHY setting ===============================================*/ + while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 ); + WriteReg_32(DBSC_V3M_CPGWPR,0x5A5AFFFF); + WriteReg_32(DBSC_V3M_CPGWPCR,0xA5A50000); + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00001234); + WriteReg_32(DBSC_V3M_DBPDLK0,0x0000A55A); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x802F8800); + while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x802B8000); + WriteReg_32(0xE6150380,0x00000C00); + WriteReg_32(0xE61500DC,0x5E000000); + while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 ); + WriteReg_32(0xE61500E4,0x00000000); + WriteReg_32(0xE6150004,0x80321235); + while ( (BIT31 & ReadReg_32(0xE6150004)) == 1 ); + while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 ); + WriteReg_32(0xE61500E4,0x00040202); + WriteReg_32(0xE6150004,0x80321235); + while ( (BIT31 & ReadReg_32(0xE6150004)) == 1 ); + WriteReg_32(0xE6150380,0x00000000); + while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x002F8800); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 ); + while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x000F8800); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 1 ); + while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 ); + while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x000F8000); + while ( (0x000003FF & ReadReg_32(0xE6150108)) != 0x00000030 ); + while ( (BIT11 & ReadReg_32(0xE61500D0)) == 0 ); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000008); + WriteReg_32(DBSC_V3M_DBPDRGD0,0x000B8000); + + WriteReg_32(DBSC_V3M_DBPDRGA0,0x00000006); + while ( (BIT31 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000A4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + WriteReg_32(DBSC_V3M_DBPDRGA0,0x000000E4); + while ( (BIT15 & ReadReg_32(DBSC_V3M_DBPDRGD0)) == 0 ); + WriteReg_32(DBSC_V3M_CPGWPCR,0xA5A50001); + WriteReg_32(DBSC_V3M_DBPDLK0,0x00000000); + WriteReg_32(DBSC_V3M_DBSYSCNT0,0x00000000); + + return 1; + +} diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/V3M/ddr_init_v3m.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/V3M/ddr_init_v3m.h new file mode 100644 index 0000000..f3416b2 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/V3M/ddr_init_v3m.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation + * All rights reserved. + */ + +#pragma once +#include + +#define RCAR_V3M_DDR_VERSION "rev.0.8" + +uint32_t init_ddr_v3m1600(void); +uint32_t init_ddr_v3m1333(void); + +uint32_t init_ddr_v3m1583(void); +uint32_t init_ddr_v3m1316(void); + +uint32_t init_ddr_v3m1580(void); +uint32_t init_ddr_v3m1320(void); + +uint32_t pll3_freq_change_bypmode_1316(void); +uint32_t pll3_freq_change_bypmode_1583(void); diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/boot_init_dram.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/boot_init_dram.c new file mode 100644 index 0000000..72a0f52 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/boot_init_dram.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation + * All rights reserved. + */ + +#include +#include +#include +#include "boot_init_dram.h" +#include "V3M/ddr_init_v3m.h" + +/* Mode pin register */ +#define RCAR_MODEMR (0xE6160060U) +#define CHECK_MD19 (0x80000U) + +#define DDR3L_1600 (0x00000U) +#define DDR3L_1333 (0x80000U) + +void InitDram(void) +{ + uint32_t chk_data; + uint32_t ret; + const char *str; + const char *ddr3l_1583 = "1583"; + const char *ddr3l_1316 = "1316"; + + chk_data = mmio_read_32((uintptr_t)RCAR_MODEMR) + & CHECK_MD19; + + switch (chk_data) { + case DDR3L_1600:/* MD19=0 */ + str = ddr3l_1583; + pll3_freq_change_bypmode_1583(); + ret = init_ddr_v3m1583(); + if(ret != 1U) + { + ERROR("Failed to DRAM initialize (%d).\n", ret); + panic(); + } + break; + case DDR3L_1333:/* MD19=1 */ + str = ddr3l_1316; + pll3_freq_change_bypmode_1316(); + ret = init_ddr_v3m1316(); + if(ret != 1U) + { + ERROR("Failed to DRAM initialize (%d).\n", ret); + panic(); + } + break; + default: + /* Error */ + ERROR("CR7: MODEMR ERROR value=%x\n", chk_data); + panic(); + break; + } + + NOTICE("DDR3L %sMbps(%s)\n", str, RCAR_V3M_DDR_VERSION); + +#if RCAR_DDR_REG_CHECK == 1 + /* initialized reg check */ + ret = InitDram_regcheck(); + + if (ret != 0U) { + ERROR("Failed to DDRPHY REG check (%d).\n", ret); + /* + * User need to implement what IPL should do + * if InitDram_regcheck() is failed. + */ + } else { + NOTICE("DDRPHY REG check is OK (%d).\n", ret); + } +#endif /* #if RCAR_DDR_REG_CHECK == 1 */ +} + + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/boot_init_dram.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/boot_init_dram.h new file mode 100644 index 0000000..000d614 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/boot_init_dram.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef BOOT_INIT_DRAM_H_ +#define BOOT_INIT_DRAM_H_ + +extern void InitDram(void); +extern int32_t InitDram_regcheck(void); + +#endif /* __BOOT_INIT_DRAM_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/ddr.mk b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/ddr.mk new file mode 100644 index 0000000..1a2265b --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/ddr.mk @@ -0,0 +1,8 @@ +# +# Copyright (c) 2015-2019, Renesas Electronics Corporation +# All rights reserved. +# + +OBJ_FILE += ddr/V3M/ddr_init_v3m.o \ + ddr/boot_init_dram.o \ + ddr/ddr_regcheck/boot_init_dram_regcheck.o diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/ddr_regcheck/boot_init_dram_regcheck.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/ddr_regcheck/boot_init_dram_regcheck.c new file mode 100644 index 0000000..29837d2 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/ddr_regcheck/boot_init_dram_regcheck.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "../V3M/boot_init_dram_regdef_v3m.h" +#include "init_dram_tbl_chk.h" +#include "init_dram_tbl_v3m.h" + +int32_t InitDram_regcheck(void) +{ + int32_t err; + + uint32_t i; + uint32_t dataL; + + err = 0; + + mmio_write_32(DBSC_V3M_DBSYSCNT0, 0x00001234); + mmio_write_32(DBSC_V3M_DBPDLK0, 0x0000A55A); + + for (i = 0; i < DDR_PHY_REGSET_NUM_V3M; i++) { + if (DDR_PHY_REGCHK[i/32] & (1U << (i%32))) { + mmio_write_32(DBSC_V3M_DBPDRGA0, i); + dataL = mmio_read_32(DBSC_V3M_DBPDRGD0); + + if (dataL != DDR_PHY_REGSET_V3M[i]) { + ERROR("REG[0x%x] = 0x%x -> 0x%x\n", i, DDR_PHY_REGSET_V3M[i], dataL); + err = 1; + } + } + } + + mmio_write_32(DBSC_V3M_DBPDLK0, 0x00000000); + mmio_write_32(DBSC_V3M_DBSYSCNT0, 0x00000000); + + + return err; +} diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/ddr_regcheck/init_dram_tbl_chk.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/ddr_regcheck/init_dram_tbl_chk.h new file mode 100644 index 0000000..f721e49 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/ddr_regcheck/init_dram_tbl_chk.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. + */ + +static const uint32_t DDR_PHY_REGCHK[9] = { +/* 000-11f */ +/* 000-01f */ 0x00003F0E, +/* 020-03f */ 0x1FE7E007, +/* 040-05f */ 0x00000000, +/* 060-07f */ 0x03FF003D, +/* 080-09f */ 0x00010000, +/* 0a0-0bf */ 0x0000000F, +/* 0c0-0df */ 0x0000000F, +/* 0e0-0ff */ 0x0000000F, +/* 100-11f */ 0x0000000F +}; diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/ddr_regcheck/init_dram_tbl_v3m.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/ddr_regcheck/init_dram_tbl_v3m.h new file mode 100644 index 0000000..79cb28b --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/ddr/ddr_regcheck/init_dram_tbl_v3m.h @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation. + * All rights reserved. + */ + +#define DDR_PHY_REGSET_NUM_V3M 288 + +static const uint32_t DDR_PHY_REGSET_V3M[DDR_PHY_REGSET_NUM_V3M] = { +/*0x000*/ 0x00201160, +/*0x001*/ 0x00010000, +/*0x002*/ 0x07D81E37, +/*0x003*/ 0x0380C720, +/*0x004*/ 0x08C05FF0, +/*0x005*/ 0xC1AA00D8, +/*0x006*/ 0xC0000FFF, +/*0x007*/ 0x00000000, +/*0x008*/ 0x000B8000, +/*0x009*/ 0x42C21590, +/*0x00a*/ 0xD05612C0, +/*0x00b*/ 0x00083DEF, +/*0x00c*/ 0x18082356, +/*0x00d*/ 0x0C834156, +/*0x00e*/ 0x00403231, +/*0x00f*/ 0x00000000, +/*0x010*/ 0x00000000, +/*0x011*/ 0x00000000, +/*0x012*/ 0x00000000, +/*0x013*/ 0x00000000, +/*0x014*/ 0x00000000, +/*0x015*/ 0x00000000, +/*0x016*/ 0x00000000, +/*0x017*/ 0x00000000, +/*0x018*/ 0x00000000, +/*0x019*/ 0x00000000, +/*0x01a*/ 0x00000000, +/*0x01b*/ 0x00000000, +/*0x01c*/ 0x00000000, +/*0x01d*/ 0x00000000, +/*0x01e*/ 0x00000000, +/*0x01f*/ 0x00000000, +/*0x020*/ 0x00181884, +/*0x021*/ 0x0024643E, +/*0x022*/ 0x1000040B, +/*0x023*/ 0x2D9C0B66, +/*0x024*/ 0x2A88C400, +/*0x025*/ 0x30005200, +/*0x026*/ 0x0014A9C9, +/*0x027*/ 0x00000D70, +/*0x028*/ 0x00000004, +/*0x029*/ 0x00000098, +/*0x02a*/ 0x00000000, +/*0x02b*/ 0x00010000, +/*0x02c*/ 0x81003087, +/*0x02d*/ 0x00000000, +/*0x02e*/ 0x00000008, +/*0x02f*/ 0x00000010, +/*0x030*/ 0x00000018, +/*0x031*/ 0xDD22EE11, +/*0x032*/ 0x7788BB44, +/*0x033*/ 0x00032D00, +/*0x034*/ 0x00002C02, +/*0x035*/ 0x3C530000, +/*0x036*/ 0xFFFF0C80, +/*0x037*/ 0x00000000, +/*0x038*/ 0x00000000, +/*0x039*/ 0x00000000, +/*0x03a*/ 0x00000000, +/*0x03b*/ 0x00141054, +/*0x03c*/ 0x0103AAAA, +/*0x03d*/ 0x00000000, +/*0x03e*/ 0x00000000, +/*0x03f*/ 0x00000000, +/*0x040*/ 0x00000000, +/*0x041*/ 0x00000000, +/*0x042*/ 0x00000000, +/*0x043*/ 0x00000000, +/*0x044*/ 0x00000000, +/*0x045*/ 0x00000000, +/*0x046*/ 0x00000000, +/*0x047*/ 0x00000000, +/*0x048*/ 0x00000000, +/*0x049*/ 0x00000000, +/*0x04a*/ 0x00000000, +/*0x04b*/ 0x00000000, +/*0x04c*/ 0x00000000, +/*0x04d*/ 0x00000000, +/*0x04e*/ 0x00000000, +/*0x04f*/ 0x00000000, +/*0x050*/ 0x00000000, +/*0x051*/ 0x00000000, +/*0x052*/ 0x00000000, +/*0x053*/ 0x00000000, +/*0x054*/ 0x00000000, +/*0x055*/ 0x00000000, +/*0x056*/ 0x00000000, +/*0x057*/ 0x00000000, +/*0x058*/ 0x00000000, +/*0x059*/ 0x00000000, +/*0x05a*/ 0x00000000, +/*0x05b*/ 0x00000000, +/*0x05c*/ 0x00000000, +/*0x05d*/ 0x00000000, +/*0x05e*/ 0x00000000, +/*0x05f*/ 0x00000000, +/*0x060*/ 0x00000000, +/*0x061*/ 0x00000000, +/*0x062*/ 0x00000000, +/*0x063*/ 0xF0000000, +/*0x064*/ 0x00000000, +/*0x065*/ 0x00000000, +/*0x066*/ 0x00000000, +/*0x067*/ 0x00000000, +/*0x068*/ 0x00000000, +/*0x069*/ 0x00000000, +/*0x06a*/ 0x00000000, +/*0x06b*/ 0x00000000, +/*0x06c*/ 0x00000000, +/*0x06d*/ 0x00000000, +/*0x06e*/ 0x00000000, +/*0x06f*/ 0x00000000, +/*0x070*/ 0xF8000000, +/*0x071*/ 0x00000020, +/*0x072*/ 0x00000000, +/*0x073*/ 0x00000000, +/*0x074*/ 0x00000000, +/*0x075*/ 0x1234ABCD, +/*0x076*/ 0x00000000, +/*0x077*/ 0x0000000C, +/*0x078*/ 0x7FFFFFFF, +/*0x079*/ 0xFFFF0000, +/*0x07a*/ 0x00000000, +/*0x07b*/ 0x00000000, +/*0x07c*/ 0x00000000, +/*0x07d*/ 0x00000000, +/*0x07e*/ 0x00000000, +/*0x07f*/ 0x00000000, +/*0x080*/ 0x00000000, +/*0x081*/ 0x00000000, +/*0x082*/ 0x00000000, +/*0x083*/ 0x00000000, +/*0x084*/ 0x00000000, +/*0x085*/ 0x00000000, +/*0x086*/ 0x00000000, +/*0x087*/ 0x00000000, +/*0x088*/ 0x00000000, +/*0x089*/ 0x00000000, +/*0x08a*/ 0x00000000, +/*0x08b*/ 0x00000000, +/*0x08c*/ 0x00000000, +/*0x08d*/ 0x00000000, +/*0x08e*/ 0x00000000, +/*0x08f*/ 0x00000000, +/*0x090*/ 0x04058900, +/*0x091*/ 0x0007BB6D, +/*0x092*/ 0x02C59CBA, +/*0x093*/ 0x00000230, +/*0x094*/ 0x00000000, +/*0x095*/ 0x0007BB6B, +/*0x096*/ 0x02C598B2, +/*0x097*/ 0x00000200, +/*0x098*/ 0x00000000, +/*0x099*/ 0x0007BB6D, +/*0x09a*/ 0x02C59CBA, +/*0x09b*/ 0x00000200, +/*0x09c*/ 0x00000000, +/*0x09d*/ 0x00000000, +/*0x09e*/ 0x00000000, +/*0x09f*/ 0x00000000, +/*0x0a0*/ 0x7C0002C5, +/*0x0a1*/ 0x00000000, +/*0x0a2*/ 0x00000000, +/*0x0a3*/ 0x00000000, +/*0x0a4*/ 0x20329A20, +/*0x0a5*/ 0x00000000, +/*0x0a6*/ 0x00000000, +/*0x0a7*/ 0x110D0F0E, +/*0x0a8*/ 0x0F110F0E, +/*0x0a9*/ 0x000D0D10, +/*0x0aa*/ 0x04010302, +/*0x0ab*/ 0x03020201, +/*0x0ac*/ 0x00000000, +/*0x0ad*/ 0x00000000, +/*0x0ae*/ 0x0000005C, +/*0x0af*/ 0x00171715, +/*0x0b0*/ 0x00000020, +/*0x0b1*/ 0x00303231, +/*0x0b2*/ 0x00000001, +/*0x0b3*/ 0x00020000, +/*0x0b4*/ 0x0000002B, +/*0x0b5*/ 0x00000009, +/*0x0b6*/ 0x00000000, +/*0x0b7*/ 0x00000000, +/*0x0b8*/ 0x00000000, +/*0x0b9*/ 0x00000000, +/*0x0ba*/ 0x00000000, +/*0x0bb*/ 0x00000000, +/*0x0bc*/ 0x00000000, +/*0x0bd*/ 0x00000000, +/*0x0be*/ 0x00000000, +/*0x0bf*/ 0x00000000, +/*0x0c0*/ 0x7C0002C5, +/*0x0c1*/ 0x00000000, +/*0x0c2*/ 0x00000000, +/*0x0c3*/ 0x00000000, +/*0x0c4*/ 0x203119A0, +/*0x0c5*/ 0x00000000, +/*0x0c6*/ 0x00000000, +/*0x0c7*/ 0x0D110D0D, +/*0x0c8*/ 0x0E0E0E0D, +/*0x0c9*/ 0x000D0D0E, +/*0x0ca*/ 0x03040403, +/*0x0cb*/ 0x03040102, +/*0x0cc*/ 0x00000000, +/*0x0cd*/ 0x00000000, +/*0x0ce*/ 0x0000005D, +/*0x0cf*/ 0x00181815, +/*0x0d0*/ 0x0000001D, +/*0x0d1*/ 0x00203331, +/*0x0d2*/ 0x00000001, +/*0x0d3*/ 0x00020000, +/*0x0d4*/ 0x00000028, +/*0x0d5*/ 0x00000003, +/*0x0d6*/ 0x00000000, +/*0x0d7*/ 0x00000000, +/*0x0d8*/ 0x00000000, +/*0x0d9*/ 0x00000000, +/*0x0da*/ 0x00000000, +/*0x0db*/ 0x00000000, +/*0x0dc*/ 0x00000000, +/*0x0dd*/ 0x00000000, +/*0x0de*/ 0x00000000, +/*0x0df*/ 0x00000000, +/*0x0e0*/ 0x7C0002C5, +/*0x0e1*/ 0x00000000, +/*0x0e2*/ 0x00000000, +/*0x0e3*/ 0x00000000, +/*0x0e4*/ 0x20339920, +/*0x0e5*/ 0x00000000, +/*0x0e6*/ 0x00000000, +/*0x0e7*/ 0x0F110E12, +/*0x0e8*/ 0x11100D0F, +/*0x0e9*/ 0x000D0D12, +/*0x0ea*/ 0x02040005, +/*0x0eb*/ 0x03040001, +/*0x0ec*/ 0x00000000, +/*0x0ed*/ 0x00000000, +/*0x0ee*/ 0x0000004E, +/*0x0ef*/ 0x00181813, +/*0x0f0*/ 0x0000002A, +/*0x0f1*/ 0x00403231, +/*0x0f2*/ 0x00000001, +/*0x0f3*/ 0x00020000, +/*0x0f4*/ 0x00000036, +/*0x0f5*/ 0x00000013, +/*0x0f6*/ 0x00000000, +/*0x0f7*/ 0x00000000, +/*0x0f8*/ 0x00000000, +/*0x0f9*/ 0x00000000, +/*0x0fa*/ 0x00000000, +/*0x0fb*/ 0x00000000, +/*0x0fc*/ 0x00000000, +/*0x0fd*/ 0x00000000, +/*0x0fe*/ 0x00000000, +/*0x0ff*/ 0x00000000, +/*0x100*/ 0x7C0002C5, +/*0x101*/ 0x00000000, +/*0x102*/ 0x00000000, +/*0x103*/ 0x00000000, +/*0x104*/ 0x003118A0, +/*0x105*/ 0x00000000, +/*0x106*/ 0x00000000, +/*0x107*/ 0x0F140F12, +/*0x108*/ 0x13120E12, +/*0x109*/ 0x000D0D0E, +/*0x10a*/ 0x01050201, +/*0x10b*/ 0x05020003, +/*0x10c*/ 0x00000000, +/*0x10d*/ 0x00000000, +/*0x10e*/ 0x00000051, +/*0x10f*/ 0x00171812, +/*0x110*/ 0x00000027, +/*0x111*/ 0x00323131, +/*0x112*/ 0x00000001, +/*0x113*/ 0x00020000, +/*0x114*/ 0x00000033, +/*0x115*/ 0x0000000F, +/*0x116*/ 0x00000000, +/*0x117*/ 0x00000000, +/*0x118*/ 0x00000000, +/*0x119*/ 0x00000000, +/*0x11a*/ 0x00000000, +/*0x11b*/ 0x00000000, +/*0x11c*/ 0x00000000, +/*0x11d*/ 0x00000000, +/*0x11e*/ 0x00000000, +/*0x11f*/ 0x00000000 +}; diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/arm_gic.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/arm_gic.h new file mode 100644 index 0000000..9d2eed6 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/arm_gic.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __ARM_GIC_H__ +#define __ARM_GIC_H__ + +#include + +/******************************************************************************* + * Function declarations + ******************************************************************************/ +void arm_gic_init(uintptr_t gicc_base, + uintptr_t gicd_base, + const unsigned int *irq_sec_ptr, + unsigned int num_irqs); +void arm_gic_setup(void); +void arm_gic_cpuif_deactivate(void); +void arm_gic_cpuif_setup(void); +void arm_gic_pcpu_distif_setup(void); + + +uint32_t arm_gic_acknowledge_interrupt(void); +void arm_gic_end_of_interrupt(uint32_t id); + +#endif /* __GIC_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/assert.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/assert.h new file mode 100644 index 0000000..fb4e6cb --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/assert.h @@ -0,0 +1,79 @@ +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)assert.h 8.2 (Berkeley) 1/21/94 + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2017, ARM Limited and Contributors. + * All rights reserved. + * Portions copyright (c) 2019, Renesas Electronics Corporation. + * All rights reserved. + */ + +#ifndef _ASSERT_H_ +#define _ASSERT_H_ + +#include +#include + +#ifndef PLAT_LOG_LEVEL_ASSERT +#define PLAT_LOG_LEVEL_ASSERT LOG_LEVEL +#endif + +#if ENABLE_ASSERTIONS +#define _assert(e) assert(e) +# if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE +# define assert(e) ((e) ? (void)0 : __assert(__FILE__, __LINE__, #e)) +# elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO +# define assert(e) ((e) ? (void)0 : __assert(__FILE__, __LINE__)) +# else +# define assert(e) ((e) ? (void)0 : __assert()) +# endif +#else +#define assert(e) ((void)0) +#define _assert(e) ((void)0) +#endif /* ENABLE_ASSERTIONS */ + +__BEGIN_DECLS +#if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE +void __assert(const char *, unsigned int, const char *) __dead2; +#elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO +void __assert(const char *, unsigned int) __dead2; +#else +void __assert(void) __dead2; +#endif +__END_DECLS + +#endif /* !_ASSERT_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/auth.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/auth.h new file mode 100644 index 0000000..c4fe6aa --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/auth.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + + +#ifndef AUTH_H__ +#define AUTH_H__ + +void pre_read_cert_info(void); +void get_cert_info(uint32_t *boot_cert_addr, uint32_t *size, + uint32_t *ipl_cert_addr); +void get_info_from_cert(uint32_t cert_addr, uint32_t *size, + uintptr_t *dest_addr); + +#endif /* AUTH_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/axi_init.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/axi_init.h new file mode 100644 index 0000000..c171511 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/axi_init.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2019-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef AXI_INIT_H__ +#define AXI_INIT_H__ + +void axi_bus_timeout_setting(void); + +#endif /* AXI_INIT_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/axi_register.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/axi_register.h new file mode 100644 index 0000000..a4f8910 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/axi_register.h @@ -0,0 +1,274 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef AXI_REGISTER_H__ +#define AXI_REGISTER_H__ + +/* AXI registers */ + +/* AXI base address */ +#define AXI_BASE (0xE6780000U) + +/* address split */ + +/* AXI address split control 0 */ +#define AXI_ADSPLCR0 (AXI_BASE + 0x4008U) +/* AXI address split control 1 */ +#define AXI_ADSPLCR1 (AXI_BASE + 0x400CU) +/* AXI address split control 2 */ +#define AXI_ADSPLCR2 (AXI_BASE + 0x4010U) +/* AXI address split control 3 */ +#define AXI_ADSPLCR3 (AXI_BASE + 0x4014U) + +/* functional safety */ + +/* AXI functional safety control */ +#define AXI_FUSACR (AXI_BASE + 0x4020U) + +/* decompression */ + +/* AXI decompression area configuration A0 */ +#define AXI_DCMPAREACRA0 (AXI_BASE + 0x4100U) +/* AXI decompression area configuration B0 */ +#define AXI_DCMPAREACRB0 (AXI_BASE + 0x4104U) +/* AXI decompression area configuration A1 */ +#define AXI_DCMPAREACRA1 (AXI_BASE + 0x4108U) +/* AXI decompression area configuration B1 */ +#define AXI_DCMPAREACRB1 (AXI_BASE + 0x410CU) +/* AXI decompression area configuration A2 */ +#define AXI_DCMPAREACRA2 (AXI_BASE + 0x4110U) +/* AXI decompression area configuration B2 */ +#define AXI_DCMPAREACRB2 (AXI_BASE + 0x4114U) +/* AXI decompression area configuration A3 */ +#define AXI_DCMPAREACRA3 (AXI_BASE + 0x4118U) +/* AXI decompression area configuration B3 */ +#define AXI_DCMPAREACRB3 (AXI_BASE + 0x411CU) +/* AXI decompression area configuration A4 */ +#define AXI_DCMPAREACRA4 (AXI_BASE + 0x4120U) +/* AXI decompression area configuration B4 */ +#define AXI_DCMPAREACRB4 (AXI_BASE + 0x4124U) +/* AXI decompression area configuration A5 */ +#define AXI_DCMPAREACRA5 (AXI_BASE + 0x4128U) +/* AXI decompression area configuration B5 */ +#define AXI_DCMPAREACRB5 (AXI_BASE + 0x412CU) +/* AXI decompression area configuration A6 */ +#define AXI_DCMPAREACRA6 (AXI_BASE + 0x4130U) +/* AXI decompression area configuration B6 */ +#define AXI_DCMPAREACRB6 (AXI_BASE + 0x4134U) +/* AXI decompression area configuration A7 */ +#define AXI_DCMPAREACRA7 (AXI_BASE + 0x4138U) +/* AXI decompression area configuration B7 */ +#define AXI_DCMPAREACRB7 (AXI_BASE + 0x413CU) +/* AXI decompression area configuration A8 */ +#define AXI_DCMPAREACRA8 (AXI_BASE + 0x4140U) +/* AXI decompression area configuration B8 */ +#define AXI_DCMPAREACRB8 (AXI_BASE + 0x4144U) +/* AXI decompression area configuration A9 */ +#define AXI_DCMPAREACRA9 (AXI_BASE + 0x4148U) +/* AXI decompression area configuration B9 */ +#define AXI_DCMPAREACRB9 (AXI_BASE + 0x414CU) +/* AXI decompression area configuration A10 */ +#define AXI_DCMPAREACRA10 (AXI_BASE + 0x4150U) +/* AXI decompression area configuration B10 */ +#define AXI_DCMPAREACRB10 (AXI_BASE + 0x4154U) +/* AXI decompression area configuration A11 */ +#define AXI_DCMPAREACRA11 (AXI_BASE + 0x4158U) +/* AXI decompression area configuration B11 */ +#define AXI_DCMPAREACRB11 (AXI_BASE + 0x415CU) +/* AXI decompression area configuration A12 */ +#define AXI_DCMPAREACRA12 (AXI_BASE + 0x4160U) +/* AXI decompression area configuration B12 */ +#define AXI_DCMPAREACRB12 (AXI_BASE + 0x4164U) +/* AXI decompression area configuration A13 */ +#define AXI_DCMPAREACRA13 (AXI_BASE + 0x4168U) +/* AXI decompression area configuration B13 */ +#define AXI_DCMPAREACRB13 (AXI_BASE + 0x416CU) +/* AXI decompression area configuration A14 */ +#define AXI_DCMPAREACRA14 (AXI_BASE + 0x4170U) +/* AXI decompression area configuration B14 */ +#define AXI_DCMPAREACRB14 (AXI_BASE + 0x4174U) +/* AXI decompression area configuration A15 */ +#define AXI_DCMPAREACRA15 (AXI_BASE + 0x4178U) +/* AXI decompression area configuration B15 */ +#define AXI_DCMPAREACRB15 (AXI_BASE + 0x417CU) +/* AXI decompression shadow area configuration */ +#define AXI_DCMPSHDWCR (AXI_BASE + 0x4280U) + +/* SDRAM protection */ + +/* AXI dram protected area division 0 */ +#define AXI_DPTDIVCR0 (AXI_BASE + 0x4400U) +/* AXI dram protected area division 1 */ +#define AXI_DPTDIVCR1 (AXI_BASE + 0x4404U) +/* AXI dram protected area division 2 */ +#define AXI_DPTDIVCR2 (AXI_BASE + 0x4408U) +/* AXI dram protected area division 3 */ +#define AXI_DPTDIVCR3 (AXI_BASE + 0x440CU) +/* AXI dram protected area division 4 */ +#define AXI_DPTDIVCR4 (AXI_BASE + 0x4410U) +/* AXI dram protected area division 5 */ +#define AXI_DPTDIVCR5 (AXI_BASE + 0x4414U) +/* AXI dram protected area division 6 */ +#define AXI_DPTDIVCR6 (AXI_BASE + 0x4418U) +/* AXI dram protected area division 7 */ +#define AXI_DPTDIVCR7 (AXI_BASE + 0x441CU) +/* AXI dram protected area division 8 */ +#define AXI_DPTDIVCR8 (AXI_BASE + 0x4420U) +/* AXI dram protected area division 9 */ +#define AXI_DPTDIVCR9 (AXI_BASE + 0x4424U) +/* AXI dram protected area division 10 */ +#define AXI_DPTDIVCR10 (AXI_BASE + 0x4428U) +/* AXI dram protected area division 11 */ +#define AXI_DPTDIVCR11 (AXI_BASE + 0x442CU) +/* AXI dram protected area division 12 */ +#define AXI_DPTDIVCR12 (AXI_BASE + 0x4430U) +/* AXI dram protected area division 13 */ +#define AXI_DPTDIVCR13 (AXI_BASE + 0x4434U) +/* AXI dram protected area division 14 */ +#define AXI_DPTDIVCR14 (AXI_BASE + 0x4438U) + +/* AXI dram protected area setting 0 */ +#define AXI_DPTCR0 (AXI_BASE + 0x4440U) +/* AXI dram protected area setting 1 */ +#define AXI_DPTCR1 (AXI_BASE + 0x4444U) +/* AXI dram protected area setting 2 */ +#define AXI_DPTCR2 (AXI_BASE + 0x4448U) +/* AXI dram protected area setting 3 */ +#define AXI_DPTCR3 (AXI_BASE + 0x444CU) +/* AXI dram protected area setting 4 */ +#define AXI_DPTCR4 (AXI_BASE + 0x4450U) +/* AXI dram protected area setting 5 */ +#define AXI_DPTCR5 (AXI_BASE + 0x4454U) +/* AXI dram protected area setting 6 */ +#define AXI_DPTCR6 (AXI_BASE + 0x4458U) +/* AXI dram protected area setting 7 */ +#define AXI_DPTCR7 (AXI_BASE + 0x445CU) +/* AXI dram protected area setting 8 */ +#define AXI_DPTCR8 (AXI_BASE + 0x4460U) +/* AXI dram protected area setting 9 */ +#define AXI_DPTCR9 (AXI_BASE + 0x4464U) +/* AXI dram protected area setting 10 */ +#define AXI_DPTCR10 (AXI_BASE + 0x4468U) +/* AXI dram protected area setting 11 */ +#define AXI_DPTCR11 (AXI_BASE + 0x446CU) +/* AXI dram protected area setting 12 */ +#define AXI_DPTCR12 (AXI_BASE + 0x4470U) +/* AXI dram protected area setting 13 */ +#define AXI_DPTCR13 (AXI_BASE + 0x4474U) +/* AXI dram protected area setting 14 */ +#define AXI_DPTCR14 (AXI_BASE + 0x4478U) +/* AXI dram protected area setting 15 */ +#define AXI_DPTCR15 (AXI_BASE + 0x447CU) + +/* SRAM protection */ + +/* AXI sram protected area division 0 */ +#define AXI_SPTDIVCR0 (AXI_BASE + 0x4500U) +/* AXI sram protected area division 1 */ +#define AXI_SPTDIVCR1 (AXI_BASE + 0x4504U) +/* AXI sram protected area division 2 */ +#define AXI_SPTDIVCR2 (AXI_BASE + 0x4508U) +/* AXI sram protected area division 3 */ +#define AXI_SPTDIVCR3 (AXI_BASE + 0x450CU) +/* AXI sram protected area division 4 */ +#define AXI_SPTDIVCR4 (AXI_BASE + 0x4510U) +/* AXI sram protected area division 5 */ +#define AXI_SPTDIVCR5 (AXI_BASE + 0x4514U) +/* AXI sram protected area division 6 */ +#define AXI_SPTDIVCR6 (AXI_BASE + 0x4518U) +/* AXI sram protected area division 7 */ +#define AXI_SPTDIVCR7 (AXI_BASE + 0x451CU) +/* AXI sram protected area division 8 */ +#define AXI_SPTDIVCR8 (AXI_BASE + 0x4520U) +/* AXI sram protected area division 9 */ +#define AXI_SPTDIVCR9 (AXI_BASE + 0x4524U) +/* AXI sram protected area division 10 */ +#define AXI_SPTDIVCR10 (AXI_BASE + 0x4528U) +/* AXI sram protected area division 11 */ +#define AXI_SPTDIVCR11 (AXI_BASE + 0x452CU) +/* AXI sram protected area division 12 */ +#define AXI_SPTDIVCR12 (AXI_BASE + 0x4530U) +/* AXI sram protected area division 13 */ +#define AXI_SPTDIVCR13 (AXI_BASE + 0x4534U) +/* AXI sram protected area division 14 */ +#define AXI_SPTDIVCR14 (AXI_BASE + 0x4538U) + +/* AXI sram protected area setting 0 */ +#define AXI_SPTCR0 (AXI_BASE + 0x4540U) +/* AXI sram protected area setting 1 */ +#define AXI_SPTCR1 (AXI_BASE + 0x4544U) +/* AXI sram protected area setting 2 */ +#define AXI_SPTCR2 (AXI_BASE + 0x4548U) +/* AXI sram protected area setting 3 */ +#define AXI_SPTCR3 (AXI_BASE + 0x454CU) +/* AXI sram protected area setting 4 */ +#define AXI_SPTCR4 (AXI_BASE + 0x4550U) +/* AXI sram protected area setting 5 */ +#define AXI_SPTCR5 (AXI_BASE + 0x4554U) +/* AXI sram protected area setting 6 */ +#define AXI_SPTCR6 (AXI_BASE + 0x4558U) +/* AXI sram protected area setting 7 */ +#define AXI_SPTCR7 (AXI_BASE + 0x455CU) +/* AXI sram protected area setting 8 */ +#define AXI_SPTCR8 (AXI_BASE + 0x4560U) +/* AXI sram protected area setting 9 */ +#define AXI_SPTCR9 (AXI_BASE + 0x4564U) +/* AXI sram protected area setting 10 */ +#define AXI_SPTCR10 (AXI_BASE + 0x4568U) +/* AXI sram protected area setting 11 */ +#define AXI_SPTCR11 (AXI_BASE + 0x456CU) +/* AXI sram protected area setting 12 */ +#define AXI_SPTCR12 (AXI_BASE + 0x4570U) +/* AXI sram protected area setting 13 */ +#define AXI_SPTCR13 (AXI_BASE + 0x4574U) +/* AXI sram protected area setting 14 */ +#define AXI_SPTCR14 (AXI_BASE + 0x4578U) +/* AXI sram protected area setting 15 */ +#define AXI_SPTCR15 (AXI_BASE + 0x457CU) + +/* EDC base address */ +#define EDC_BASE (0xFF840000U) + +/* EDC edc enable */ +#define EDC_EDCEN (EDC_BASE + 0x0010U) +/* EDC edc status 0 */ +#define EDC_EDCST0 (EDC_BASE + 0x0020U) +/* EDC edc status 1 */ +#define EDC_EDCST1 (EDC_BASE + 0x0024U) +/* EDC edc interrupt enable 0 */ +#define EDC_EDCINTEN0 (EDC_BASE + 0x0040U) +/* EDC edc interrupt enable 1 */ +#define EDC_EDCINTEN1 (EDC_BASE + 0x0044U) + +/* EDC FIX ERR Enable Register */ +#define EDC_EDCFIXERREN (EDC_BASE + 0x0050U) + +/* EDC FIX ERR Interrupt Enable 0 Register */ +#define EDC_EDCFIXERRINTEN0 (EDC_BASE + 0x0080U) +/* EDC FIX ERR Interrupt Enable 1 Register */ +#define EDC_EDCFIXERRINTEN1 (EDC_BASE + 0x0084U) +/* EDC FIX ERR Interrupt Enable 2 Register */ +#define EDC_EDCFIXERRINTEN2 (EDC_BASE + 0x0088U) +/* EDC FIX ERR Interrupt Enable 3 Register */ +#define EDC_EDCFIXERRINTEN3 (EDC_BASE + 0x008CU) + +/* EDC Routing Error Enable */ +#define EDC_EDCROUERREN (EDC_BASE + 0x0100U) + +/* EDC Routing ERROR Interrupt Enable 0 */ +#define EDC_EDCRERRINTEN0 (EDC_BASE + 0x0150U) +/* EDC Routing ERROR Interrupt Enable 1 */ +#define EDC_EDCRERRINTEN1 (EDC_BASE + 0x0154U) +/* EDC Routing ERROR Interrupt Enable 2 */ +#define EDC_EDCRERRINTEN2 (EDC_BASE + 0x0158U) +/* EDC Routing ERROR Interrupt Enable 3 */ +#define EDC_EDCRERRINTEN3 (EDC_BASE + 0x015CU) +/* EDC Routing ERROR Interrupt Enable 4 */ +#define EDC_EDCRERRINTEN4 (EDC_BASE + 0x0160U) +/* EDC Routing ERROR Interrupt Enable 5 */ +#define EDC_EDCRERRINTEN5 (EDC_BASE + 0x0164U) + +#endif /* AXI_REGISTER_H__ */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/bit.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/bit.h new file mode 100644 index 0000000..d5c15f5 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/bit.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef BIT_H__ +#define BIT_H__ + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#endif /* BIT_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/bl_common.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/bl_common.h new file mode 100644 index 0000000..9385ac5 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/bl_common.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __BL_COMMON_H__ +#define __BL_COMMON_H__ + + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + + +#endif /* __BL_COMMON_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/cpg_init.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/cpg_init.h new file mode 100644 index 0000000..60555e0 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/cpg_init.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef CPG_INIT_H__ +#define CPG_INIT_H__ + +void cpg_init(void); +void cpg_write(uintptr_t regadr, uint32_t regval); + +#endif /* CPG_INIT_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/cpg_register.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/cpg_register.h new file mode 100644 index 0000000..6fd3a37 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/cpg_register.h @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef CPG_REGISTER_H__ +#define CPG_REGISTER_H__ + +/* CPG base address */ +#define CPG_BASE (0xE6150000U) + +/* CPG Realtime module stop control 0 */ +#define CPG_RMSTPCR0 (CPG_BASE + 0x0110U) +/* CPG module stop status 0 */ +#define CPG_MSTPSR0 (CPG_BASE + 0x0030U) + +/* CPG system module stop control 2 */ +#define CPG_SMSTPCR2 (CPG_BASE + 0x0138U) +/* CPG software reset 2 */ +#define CPG_SRCR2 (CPG_BASE + 0x00B0U) +/* CPG module stop status 2 */ +#define CPG_MSTPSR2 (CPG_BASE + 0x0040U) +/* CPG write protect */ +#define CPG_CPGWPR (CPG_BASE + 0x0900U) +/* CPG write protect control */ +#define CPG_CPGWPCR (CPG_BASE + 0x0904U) +/* CPG system module stop control 9 */ +#define CPG_SMSTPCR9 (CPG_BASE + 0x0994U) +/* CPG module stop status 9 */ +#define CPG_MSTPSR9 (CPG_BASE + 0x09A4U) + +/* CPG (SECURITY) registers */ + +/* Secure Module Stop Control Register 0 */ +#define SCMSTPCR0 (CPG_BASE + 0x0B20U) +/* Secure Module Stop Control Register 1 */ +#define SCMSTPCR1 (CPG_BASE + 0x0B24U) +/* Secure Module Stop Control Register 2 */ +#define SCMSTPCR2 (CPG_BASE + 0x0B28U) +/* Secure Module Stop Control Register 3 */ +#define SCMSTPCR3 (CPG_BASE + 0x0B2CU) +/* Secure Module Stop Control Register 4 */ +#define SCMSTPCR4 (CPG_BASE + 0x0B30U) +/* Secure Module Stop Control Register 5 */ +#define SCMSTPCR5 (CPG_BASE + 0x0B34U) +/* Secure Module Stop Control Register 6 */ +#define SCMSTPCR6 (CPG_BASE + 0x0B38U) +/* Secure Module Stop Control Register 7 */ +#define SCMSTPCR7 (CPG_BASE + 0x0B3CU) +/* Secure Module Stop Control Register 8 */ +#define SCMSTPCR8 (CPG_BASE + 0x0B40U) +/* Secure Module Stop Control Register 9 */ +#define SCMSTPCR9 (CPG_BASE + 0x0B44U) +/* Secure Module Stop Control Register 10 */ +#define SCMSTPCR10 (CPG_BASE + 0x0B48U) +/* Secure Module Stop Control Register 11 */ +#define SCMSTPCR11 (CPG_BASE + 0x0B4CU) + +/* CPG (SECURITY) registers */ + +/* Secure Software Reset Access Enable Control Register 0 */ +#define SCSRSTECR0 (CPG_BASE + 0x0B80U) +/* Secure Software Reset Access Enable Control Register 1 */ +#define SCSRSTECR1 (CPG_BASE + 0x0B84U) +/* Secure Software Reset Access Enable Control Register 2 */ +#define SCSRSTECR2 (CPG_BASE + 0x0B88U) +/* Secure Software Reset Access Enable Control Register 3 */ +#define SCSRSTECR3 (CPG_BASE + 0x0B8CU) +/* Secure Software Reset Access Enable Control Register 4 */ +#define SCSRSTECR4 (CPG_BASE + 0x0B90U) +/* Secure Software Reset Access Enable Control Register 5 */ +#define SCSRSTECR5 (CPG_BASE + 0x0B94U) +/* Secure Software Reset Access Enable Control Register 6 */ +#define SCSRSTECR6 (CPG_BASE + 0x0B98U) +/* Secure Software Reset Access Enable Control Register 7 */ +#define SCSRSTECR7 (CPG_BASE + 0x0B9CU) +/* Secure Software Reset Access Enable Control Register 8 */ +#define SCSRSTECR8 (CPG_BASE + 0x0BA0U) +/* Secure Software Reset Access Enable Control Register 9 */ +#define SCSRSTECR9 (CPG_BASE + 0x0BA4U) +/* Secure Software Reset Access Enable Control Register 10 */ +#define SCSRSTECR10 (CPG_BASE + 0x0BA8U) +/* Secure Software Reset Access Enable Control Register 11 */ +#define SCSRSTECR11 (CPG_BASE + 0x0BACU) + +/* CPG (REALTIME) registers */ + +/* Realtime Module Stop Control Register 0 */ +#define RMSTPCR0 (CPG_BASE + 0x0110U) +/* Realtime Module Stop Control Register 1 */ +#define RMSTPCR1 (CPG_BASE + 0x0114U) +/* Realtime Module Stop Control Register 2 */ +#define RMSTPCR2 (CPG_BASE + 0x0118U) +/* Realtime Module Stop Control Register 3 */ +#define RMSTPCR3 (CPG_BASE + 0x011CU) +/* Realtime Module Stop Control Register 4 */ +#define RMSTPCR4 (CPG_BASE + 0x0120U) +/* Realtime Module Stop Control Register 5 */ +#define RMSTPCR5 (CPG_BASE + 0x0124U) +/* Realtime Module Stop Control Register 6 */ +#define RMSTPCR6 (CPG_BASE + 0x0128U) +/* Realtime Module Stop Control Register 7 */ +#define RMSTPCR7 (CPG_BASE + 0x012CU) +/* Realtime Module Stop Control Register 8 */ +#define RMSTPCR8 (CPG_BASE + 0x0980U) +/* Realtime Module Stop Control Register 9 */ +#define RMSTPCR9 (CPG_BASE + 0x0984U) +/* Realtime Module Stop Control Register 10 */ +#define RMSTPCR10 (CPG_BASE + 0x0988U) +/* Realtime Module Stop Control Register 11 */ +#define RMSTPCR11 (CPG_BASE + 0x098CU) + +/* CPG (SAFETY) registers */ + +/* Safety Module Stop Control Register 0 */ +#define SAMSTPCR0 (CPG_BASE + 0x0C20U) +/* Safety Module Stop Control Register 1 */ +#define SAMSTPCR1 (CPG_BASE + 0x0C24U) +/* Safety Module Stop Control Register 2 */ +#define SAMSTPCR2 (CPG_BASE + 0x0C28U) +/* Safety Module Stop Control Register 3 */ +#define SAMSTPCR3 (CPG_BASE + 0x0C2CU) +/* Safety Module Stop Control Register 4 */ +#define SAMSTPCR4 (CPG_BASE + 0x0C30U) +/* Safety Module Stop Control Register 5 */ +#define SAMSTPCR5 (CPG_BASE + 0x0C34U) +/* Safety Module Stop Control Register 6 */ +#define SAMSTPCR6 (CPG_BASE + 0x0C38U) +/* Safety Module Stop Control Register 7 */ +#define SAMSTPCR7 (CPG_BASE + 0x0C3CU) +/* Safety Module Stop Control Register 8 */ +#define SAMSTPCR8 (CPG_BASE + 0x0C40U) +/* Safety Module Stop Control Register 9 */ +#define SAMSTPCR9 (CPG_BASE + 0x0C44U) + +/* Automatic Module clock stop function off register */ +#define ASTPOFFR (CPG_BASE + 0x0278U) + +#endif /* CPG_REGISTER_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/cpsr_acc.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/cpsr_acc.h new file mode 100644 index 0000000..6f778c9 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/cpsr_acc.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef __CPSR_ACC_H__ +#define __CPSR_ACC_H__ + +#ifndef __ASSEMBLY +/* AArch32 AIF SET/CLEAR Function */ +void aif_enable_i(void); +void aif_disable_i(void); +void aif_enable_a(void); +void aif_disable_a(void); +#endif /* __ASSEMBLY */ + +#endif /* __CPSR_ACC_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/debug.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/debug.h new file mode 100644 index 0000000..8f265f6 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/debug.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2021, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +#include + +/* The log output macros print output to the console. These macros produce + * compiled log output only if the LOG_LEVEL defined in the makefile (or the + * make command line) is greater or equal than the level required for that + * type of log output. + * The format expected is the same as for printf(). For example: + * INFO("Info %s.\n", "message") -> INFO: Info message. + * WARN("Warning %s.\n", "message") -> WARNING: Warning message. + */ + +#define LOG_LEVEL_NONE 0 +#define LOG_LEVEL_ERROR 10 +#define LOG_LEVEL_NOTICE 20 +#define LOG_LEVEL_WARNING 30 +#define LOG_LEVEL_INFO 40 +#define LOG_LEVEL_VERBOSE 50 + + +#if LOG_LEVEL >= LOG_LEVEL_NOTICE +# define NOTICE(...) tf_printf("NOTICE: " __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_ERROR +# define ERROR(...) tf_printf("ERROR: " __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_WARNING +# define WARN(...) tf_printf("WARNING: " __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_INFO +# define INFO(...) tf_printf("INFO: " __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE +# define VERBOSE(...) tf_printf("VERBOSE: " __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + + +void __dead2 do_panic(void); +#define panic() do_panic() + +void tf_printf(const char *fmt, ...) __printflike(1, 2); +int sprintf(char *buf, const char *format, ...); + +#endif /* __DEBUG_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/dma_driver.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/dma_driver.h new file mode 100644 index 0000000..f41665a --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/dma_driver.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef DMA_DRIVER_H__ +#define DMA_DRIVER_H__ + +#include + +void init_dma(void); +void exec_dma(uint32_t dst, uint32_t src, uint32_t len); +#if DEBUG +void termDMA(void); +#endif + +#endif /* DMA_DRIVER_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/dma_register.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/dma_register.h new file mode 100644 index 0000000..73ec9f9 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/dma_register.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef DMA_REGISTER_H__ +#define DMA_REGISTER_H__ + +#include "cpg_register.h" + +#define DMACH 1U /* DMA CH setting (1-15) */ + +#define CPG_RMSTPCR0 (CPG_BASE + 0x0110U) +#define RT_DMAC_BIT (0x00200000U) +#define DMA_BASE (0xFFC10000U) + +/* DMA operation 0 */ +#define DMA_RDMOR (DMA_BASE + 0x0060U) +/* DMA secure control */ +#define DMA_RDMSEC (DMA_BASE + 0x0030U) +/* DMA channel clear */ +#define DMA_RDMCHCLR (DMA_BASE + 0x0080U) +/* DMA source address */ +#define DMA_RDMSAR (DMA_BASE + (DMACH * 0x80U) + 0x8000U) +/* DMA destination address */ +#define DMA_RDMDAR (DMA_BASE + (DMACH * 0x80U) + 0x8004U) +/* DMA transfer count */ +#define DMA_RDMTCR (DMA_BASE + (DMACH * 0x80U) + 0x8008U) +/* DMA channel control */ +#define DMA_RDMCHCR (DMA_BASE + (DMACH * 0x80U) + 0x800CU) + +#endif /* DMA_REGISTER_H__ */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/ecc.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/ecc.h new file mode 100644 index 0000000..7c2ee4b --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/ecc.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef ECC_INIT_H__ +#define ECC_INIT_H__ + +void ecc_init(void); +void dram_ecc_init(void); + +#endif /* ECC_INIT_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/edc_init.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/edc_init.h new file mode 100644 index 0000000..0b99357 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/edc_init.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2018-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef EDC_INIT_H__ +#define EDC_INIT_H__ + +void edc_routing_err_init(void); + +#endif /* EDC_INIT_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/error_output.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/error_output.h new file mode 100644 index 0000000..f27ad69 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/error_output.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef ABT_ERROR_H__ +#define ABT_ERROR_H__ + +extern void swdt_release(void); + +void undef_error(uint32_t occ_add); +void fiq_error(void); +void interrupt_error_id(uint32_t int_id, uint32_t occ_add); +void dabort_error(uint32_t occ_add,uint32_t dfsr, uint32_t dfar); +void pabort_error(uint32_t ifsr, uint32_t ifar); + +#endif /* ABT_ERROR_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/gic_v2.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/gic_v2.h new file mode 100644 index 0000000..b120ee1 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/gic_v2.h @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __GIC_V2_H__ +#define __GIC_V2_H__ + + +#define GIC400_NUM_SPIS 480 +#define MAX_PPIS 14 +#define MAX_SGIS 16 + +#define MIN_SGI_ID 0 +#define MIN_PPI_ID 16 +#define MIN_SPI_ID 32 + +#define GRP0 0 +#define GRP1 1 +#define GIC_PRI_MASK 0xff +#define GIC_HIGHEST_SEC_PRIORITY 0 +#define GIC_LOWEST_SEC_PRIORITY 127 +#define GIC_HIGHEST_NS_PRIORITY 128 +#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ +#define GIC_SPURIOUS_INTERRUPT 1023 +#define GIC_TARGET_CPU_MASK 0xff + +#define ENABLE_GRP0 (1 << 0) +#define ENABLE_GRP1 (1 << 1) + +/* Distributor interface definitions */ +#define GICD_CTLR 0x0 +#define GICD_TYPER 0x4 +#define GICD_IGROUPR 0x80 +#define GICD_ISENABLER 0x100 +#define GICD_ICENABLER 0x180 +#define GICD_ISPENDR 0x200 +#define GICD_ICPENDR 0x280 +#define GICD_ISACTIVER 0x300 +#define GICD_ICACTIVER 0x380 +#define GICD_IPRIORITYR 0x400 +#define GICD_ITARGETSR 0x800 +#define GICD_ICFGR 0xC00 +#define GICD_SGIR 0xF00 +#define GICD_CPENDSGIR 0xF10 +#define GICD_SPENDSGIR 0xF20 + +#define IGROUPR_SHIFT 5 +#define ISENABLER_SHIFT 5 +#define ICENABLER_SHIFT ISENABLER_SHIFT +#define ISPENDR_SHIFT 5 +#define ICPENDR_SHIFT ISPENDR_SHIFT +#define ISACTIVER_SHIFT 5 +#define ICACTIVER_SHIFT ISACTIVER_SHIFT +#define IPRIORITYR_SHIFT 2 +#define ITARGETSR_SHIFT 2 +#define ICFGR_SHIFT 4 +#define CPENDSGIR_SHIFT 2 +#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT + +/* GICD_TYPER bit definitions */ +#define IT_LINES_NO_MASK 0x1f + +/* Physical CPU Interface registers */ +#define GICC_CTLR 0x0 +#define GICC_PMR 0x4 +#define GICC_BPR 0x8 +#define GICC_IAR 0xC +#define GICC_EOIR 0x10 +#define GICC_RPR 0x14 +#define GICC_HPPIR 0x18 +#define GICC_AHPPIR 0x28 +#define GICC_IIDR 0xFC +#define GICC_DIR 0x1000 +#define GICC_PRIODROP GICC_EOIR + +/* Common CPU Interface definitions */ +#define INT_ID_MASK 0x3ff + +/* GICC_CTLR bit definitions */ +#define EOI_MODE_NS (1 << 10) +#define EOI_MODE_S (1 << 9) +#define IRQ_BYP_DIS_GRP1 (1 << 8) +#define FIQ_BYP_DIS_GRP1 (1 << 7) +#define IRQ_BYP_DIS_GRP0 (1 << 6) +#define FIQ_BYP_DIS_GRP0 (1 << 5) +#define CBPR (1 << 4) +#define FIQ_EN (1 << 3) +#define ACK_CTL (1 << 2) + +/* GICC_IIDR bit masks and shifts */ +#define GICC_IIDR_PID_SHIFT 20 +#define GICC_IIDR_ARCH_SHIFT 16 +#define GICC_IIDR_REV_SHIFT 12 +#define GICC_IIDR_IMP_SHIFT 0 + +#define GICC_IIDR_PID_MASK 0xfff +#define GICC_IIDR_ARCH_MASK 0xf +#define GICC_IIDR_REV_MASK 0xf +#define GICC_IIDR_IMP_MASK 0xfff + +/* HYP view virtual CPU Interface registers */ +#define GICH_CTL 0x0 +#define GICH_VTR 0x4 +#define GICH_ELRSR0 0x30 +#define GICH_ELRSR1 0x34 +#define GICH_APR0 0xF0 +#define GICH_LR_BASE 0x100 + +/* Virtual CPU Interface registers */ +#define GICV_CTL 0x0 +#define GICV_PRIMASK 0x4 +#define GICV_BP 0x8 +#define GICV_INTACK 0xC +#define GICV_EOI 0x10 +#define GICV_RUNNINGPRI 0x14 +#define GICV_HIGHESTPEND 0x18 +#define GICV_DEACTIVATE 0x1000 + +#ifndef __ASSEMBLY__ + +#include +#include + +/******************************************************************************* + * GIC Distributor function prototypes + ******************************************************************************/ + +unsigned int gicd_read_igroupr(uintptr_t, unsigned int); +unsigned int gicd_read_isenabler(uintptr_t, unsigned int); +unsigned int gicd_read_icenabler(uintptr_t, unsigned int); +unsigned int gicd_read_ispendr(uintptr_t, unsigned int); +unsigned int gicd_read_icpendr(uintptr_t, unsigned int); +unsigned int gicd_read_isactiver(uintptr_t, unsigned int); +unsigned int gicd_read_icactiver(uintptr_t, unsigned int); +unsigned int gicd_read_ipriorityr(uintptr_t, unsigned int); +unsigned int gicd_read_itargetsr(uintptr_t, unsigned int); +unsigned int gicd_read_icfgr(uintptr_t, unsigned int); +unsigned int gicd_read_cpendsgir(uintptr_t, unsigned int); +unsigned int gicd_read_spendsgir(uintptr_t, unsigned int); +void gicd_write_igroupr(uintptr_t, unsigned int, unsigned int); +void gicd_write_isenabler(uintptr_t, unsigned int, unsigned int); +void gicd_write_icenabler(uintptr_t, unsigned int, unsigned int); +void gicd_write_ispendr(uintptr_t, unsigned int, unsigned int); +void gicd_write_icpendr(uintptr_t, unsigned int, unsigned int); +void gicd_write_isactiver(uintptr_t, unsigned int, unsigned int); +void gicd_write_icactiver(uintptr_t, unsigned int, unsigned int); +void gicd_write_ipriorityr(uintptr_t, unsigned int, unsigned int); +void gicd_write_itargetsr(uintptr_t, unsigned int, unsigned int); +void gicd_write_icfgr(uintptr_t, unsigned int, unsigned int); +void gicd_write_cpendsgir(uintptr_t, unsigned int, unsigned int); +void gicd_write_spendsgir(uintptr_t, unsigned int, unsigned int); +unsigned int gicd_get_igroupr(uintptr_t, unsigned int); +void gicd_set_igroupr(uintptr_t, unsigned int); +void gicd_clr_igroupr(uintptr_t, unsigned int); +void gicd_set_isenabler(uintptr_t, unsigned int); +void gicd_set_icenabler(uintptr_t, unsigned int); +void gicd_set_ispendr(uintptr_t, unsigned int); +void gicd_set_icpendr(uintptr_t, unsigned int); +void gicd_set_isactiver(uintptr_t, unsigned int); +void gicd_set_icactiver(uintptr_t, unsigned int); +void gicd_set_ipriorityr(uintptr_t, unsigned int, unsigned int); +void gicd_set_itargetsr(uintptr_t, unsigned int, unsigned int); + + +/******************************************************************************* + * GIC Distributor interface accessors for reading entire registers + ******************************************************************************/ + +static inline unsigned int gicd_read_ctlr(uintptr_t base) +{ + return mmio_read_32(base + GICD_CTLR); +} + +static inline unsigned int gicd_read_typer(uintptr_t base) +{ + return mmio_read_32(base + GICD_TYPER); +} + +static inline unsigned int gicd_read_sgir(uintptr_t base) +{ + return mmio_read_32(base + GICD_SGIR); +} + + +/******************************************************************************* + * GIC Distributor interface accessors for writing entire registers + ******************************************************************************/ + +static inline void gicd_write_ctlr(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICD_CTLR, val); +} + +static inline void gicd_write_sgir(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICD_SGIR, val); +} + + +/******************************************************************************* + * GIC CPU interface accessors for reading entire registers + ******************************************************************************/ + +static inline unsigned int gicc_read_ctlr(uintptr_t base) +{ + return mmio_read_32(base + GICC_CTLR); +} + +static inline unsigned int gicc_read_pmr(uintptr_t base) +{ + return mmio_read_32(base + GICC_PMR); +} + +static inline unsigned int gicc_read_BPR(uintptr_t base) +{ + return mmio_read_32(base + GICC_BPR); +} + +static inline unsigned int gicc_read_IAR(uintptr_t base) +{ + return mmio_read_32(base + GICC_IAR); +} + +static inline unsigned int gicc_read_EOIR(uintptr_t base) +{ + return mmio_read_32(base + GICC_EOIR); +} + +static inline unsigned int gicc_read_hppir(uintptr_t base) +{ + return mmio_read_32(base + GICC_HPPIR); +} + +static inline unsigned int gicc_read_ahppir(uintptr_t base) +{ + return mmio_read_32(base + GICC_AHPPIR); +} + +static inline unsigned int gicc_read_dir(uintptr_t base) +{ + return mmio_read_32(base + GICC_DIR); +} + +static inline unsigned int gicc_read_iidr(uintptr_t base) +{ + return mmio_read_32(base + GICC_IIDR); +} + + +/******************************************************************************* + * GIC CPU interface accessors for writing entire registers + ******************************************************************************/ + +static inline void gicc_write_ctlr(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_CTLR, val); +} + +static inline void gicc_write_pmr(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_PMR, val); +} + +static inline void gicc_write_BPR(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_BPR, val); +} + + +static inline void gicc_write_IAR(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_IAR, val); +} + +static inline void gicc_write_EOIR(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_EOIR, val); +} + +static inline void gicc_write_hppir(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_HPPIR, val); +} + +static inline void gicc_write_dir(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_DIR, val); +} + +#endif /*__ASSEMBLY__*/ + +#endif /* __GIC_V2_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/lifec_init.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/lifec_init.h new file mode 100644 index 0000000..a0d42fc --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/lifec_init.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef LIFEC_INIT_H__ +#define LIFEC_INIT_H__ + +void lifec_init(void); +void lifec_cr7_setting(void); + +#endif /* LIFEC_INIT_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/lifec_register.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/lifec_register.h new file mode 100644 index 0000000..c390854 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/lifec_register.h @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef LIFEC_REGISTER_H__ +#define LIFEC_REGISTER_H__ + +/* LIFEC0 (SECURITY) registers */ + +/* LIFEC0 (SECURITY) base address */ +#define LIFEC_SEC_BASE (0xE6110000U) + +/* Security attribute setting for master ports */ +#define SEC_SRC (LIFEC_SEC_BASE + 0x0008U) +/* Security attribute setting for slave ports 0 */ +#define SEC_SEL0 (LIFEC_SEC_BASE + 0x0030U) +/* Security attribute setting for slave ports 1 */ +#define SEC_SEL1 (LIFEC_SEC_BASE + 0x0034U) +/* Security attribute setting for slave ports 2 */ +#define SEC_SEL2 (LIFEC_SEC_BASE + 0x0038U) +/* Security attribute setting for slave ports 3 */ +#define SEC_SEL3 (LIFEC_SEC_BASE + 0x003CU) +/* Security attribute setting for slave ports 4 */ +#define SEC_SEL4 (LIFEC_SEC_BASE + 0x0058U) +/* Security attribute setting for slave ports 5 */ +#define SEC_SEL5 (LIFEC_SEC_BASE + 0x005CU) +/* Security attribute setting for slave ports 6 */ +#define SEC_SEL6 (LIFEC_SEC_BASE + 0x0060U) +/* Security attribute setting for slave ports 7 */ +#define SEC_SEL7 (LIFEC_SEC_BASE + 0x0064U) +/* Security attribute setting for slave ports 8 */ +#define SEC_SEL8 (LIFEC_SEC_BASE + 0x0068U) +/* Security attribute setting for slave ports 9 */ +#define SEC_SEL9 (LIFEC_SEC_BASE + 0x006CU) +/* Security attribute setting for slave ports 10 */ +#define SEC_SEL10 (LIFEC_SEC_BASE + 0x0070U) +/* Security attribute setting for slave ports 11 */ +#define SEC_SEL11 (LIFEC_SEC_BASE + 0x0074U) +/* Security attribute setting for slave ports 12 */ +#define SEC_SEL12 (LIFEC_SEC_BASE + 0x0078U) +/* Security attribute setting for slave ports 13 */ +#define SEC_SEL13 (LIFEC_SEC_BASE + 0x007CU) +/* Security attribute setting for slave ports 14 */ +#define SEC_SEL14 (LIFEC_SEC_BASE + 0x0080U) +/* Security attribute setting for slave ports 15 */ +#define SEC_SEL15 (LIFEC_SEC_BASE + 0x0084U) +/* Security group 0 attribute setting for master ports 0 */ +#define SEC_GRP0CR0 (LIFEC_SEC_BASE + 0x0138U) +/* Security group 1 attribute setting for master ports 0 */ +#define SEC_GRP1CR0 (LIFEC_SEC_BASE + 0x013CU) +/* Security group 0 attribute setting for master ports 1 */ +#define SEC_GRP0CR1 (LIFEC_SEC_BASE + 0x0140U) +/* Security group 1 attribute setting for master ports 1 */ +#define SEC_GRP1CR1 (LIFEC_SEC_BASE + 0x0144U) +/* Security group 0 attribute setting for master ports 2 */ +#define SEC_GRP0CR2 (LIFEC_SEC_BASE + 0x0148U) +/* Security group 1 attribute setting for master ports 2 */ +#define SEC_GRP1CR2 (LIFEC_SEC_BASE + 0x014CU) +/* Security group 0 attribute setting for master ports 3 */ +#define SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U) +/* Security group 1 attribute setting for master ports 3 */ +#define SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U) +/* Security group 0 attribute setting for slave ports 0 */ +#define SEC_GRP0COND0 (LIFEC_SEC_BASE + 0x0158U) +/* Security group 1 attribute setting for slave ports 0 */ +#define SEC_GRP1COND0 (LIFEC_SEC_BASE + 0x015CU) +/* Security group 0 attribute setting for slave ports 1 */ +#define SEC_GRP0COND1 (LIFEC_SEC_BASE + 0x0160U) +/* Security group 1 attribute setting for slave ports 1 */ +#define SEC_GRP1COND1 (LIFEC_SEC_BASE + 0x0164U) +/* Security group 0 attribute setting for slave ports 2 */ +#define SEC_GRP0COND2 (LIFEC_SEC_BASE + 0x0168U) +/* Security group 1 attribute setting for slave ports 2 */ +#define SEC_GRP1COND2 (LIFEC_SEC_BASE + 0x016CU) +/* Security group 0 attribute setting for slave ports 3 */ +#define SEC_GRP0COND3 (LIFEC_SEC_BASE + 0x0170U) +/* Security group 1 attribute setting for slave ports 3 */ +#define SEC_GRP1COND3 (LIFEC_SEC_BASE + 0x0174U) +/* Security group 0 attribute setting for slave ports 4 */ +#define SEC_GRP0COND4 (LIFEC_SEC_BASE + 0x0178U) +/* Security group 1 attribute setting for slave ports 4 */ +#define SEC_GRP1COND4 (LIFEC_SEC_BASE + 0x017CU) +/* Security group 0 attribute setting for slave ports 5 */ +#define SEC_GRP0COND5 (LIFEC_SEC_BASE + 0x0180U) +/* Security group 1 attribute setting for slave ports 5 */ +#define SEC_GRP1COND5 (LIFEC_SEC_BASE + 0x0184U) +/* Security group 0 attribute setting for slave ports 6 */ +#define SEC_GRP0COND6 (LIFEC_SEC_BASE + 0x0188U) +/* Security group 1 attribute setting for slave ports 6 */ +#define SEC_GRP1COND6 (LIFEC_SEC_BASE + 0x018CU) +/* Security group 0 attribute setting for slave ports 7 */ +#define SEC_GRP0COND7 (LIFEC_SEC_BASE + 0x0190U) +/* Security group 1 attribute setting for slave ports 7 */ +#define SEC_GRP1COND7 (LIFEC_SEC_BASE + 0x0194U) +/* Security group 0 attribute setting for slave ports 8 */ +#define SEC_GRP0COND8 (LIFEC_SEC_BASE + 0x0198U) +/* Security group 1 attribute setting for slave ports 8 */ +#define SEC_GRP1COND8 (LIFEC_SEC_BASE + 0x019CU) +/* Security group 0 attribute setting for slave ports 9 */ +#define SEC_GRP0COND9 (LIFEC_SEC_BASE + 0x01A0U) +/* Security group 1 attribute setting for slave ports 9 */ +#define SEC_GRP1COND9 (LIFEC_SEC_BASE + 0x01A4U) +/* Security group 0 attribute setting for slave ports 10 */ +#define SEC_GRP0COND10 (LIFEC_SEC_BASE + 0x01A8U) +/* Security group 1 attribute setting for slave ports 10 */ +#define SEC_GRP1COND10 (LIFEC_SEC_BASE + 0x01ACU) +/* Security group 0 attribute setting for slave ports 11 */ +#define SEC_GRP0COND11 (LIFEC_SEC_BASE + 0x01B0U) +/* Security group 1 attribute setting for slave ports 11 */ +#define SEC_GRP1COND11 (LIFEC_SEC_BASE + 0x01B4U) +/* Security group 0 attribute setting for slave ports 12 */ +#define SEC_GRP0COND12 (LIFEC_SEC_BASE + 0x01B8U) +/* Security group 1 attribute setting for slave ports 12 */ +#define SEC_GRP1COND12 (LIFEC_SEC_BASE + 0x01BCU) +/* Security group 0 attribute setting for slave ports 13 */ +#define SEC_GRP0COND13 (LIFEC_SEC_BASE + 0x01C0U) +/* Security group 1 attribute setting for slave ports 13 */ +#define SEC_GRP1COND13 (LIFEC_SEC_BASE + 0x01C4U) +/* Security group 0 attribute setting for slave ports 14 */ +#define SEC_GRP0COND14 (LIFEC_SEC_BASE + 0x01C8U) +/* Security group 1 attribute setting for slave ports 14 */ +#define SEC_GRP1COND14 (LIFEC_SEC_BASE + 0x01CCU) +/* Security group 0 attribute setting for slave ports 15 */ +#define SEC_GRP0COND15 (LIFEC_SEC_BASE + 0x01D0U) +/* Security group 1 attribute setting for slave ports 15 */ +#define SEC_GRP1COND15 (LIFEC_SEC_BASE + 0x01D4U) +/* Security write protection attribute setting for slave ports 0 */ +#define SEC_READONLY0 (LIFEC_SEC_BASE + 0x01D8U) +/* Security write protection attribute setting for slave ports 1 */ +#define SEC_READONLY1 (LIFEC_SEC_BASE + 0x01DCU) +/* Security write protection attribute setting for slave ports 2 */ +#define SEC_READONLY2 (LIFEC_SEC_BASE + 0x01E0U) +/* Security write protection attribute setting for slave ports 3 */ +#define SEC_READONLY3 (LIFEC_SEC_BASE + 0x01E4U) +/* Security write protection attribute setting for slave ports 4 */ +#define SEC_READONLY4 (LIFEC_SEC_BASE + 0x01E8U) +/* Security write protection attribute setting for slave ports 5 */ +#define SEC_READONLY5 (LIFEC_SEC_BASE + 0x01ECU) +/* Security write protection attribute setting for slave ports 6 */ +#define SEC_READONLY6 (LIFEC_SEC_BASE + 0x01F0U) +/* Security write protection attribute setting for slave ports 7 */ +#define SEC_READONLY7 (LIFEC_SEC_BASE + 0x01F4U) +/* Security write protection attribute setting for slave ports 8 */ +#define SEC_READONLY8 (LIFEC_SEC_BASE + 0x01F8U) +/* Security write protection attribute setting for slave ports 9 */ +#define SEC_READONLY9 (LIFEC_SEC_BASE + 0x01FCU) +/* Security write protection attribute setting for slave ports 10 */ +#define SEC_READONLY10 (LIFEC_SEC_BASE + 0x0200U) +/* Security write protection attribute setting for slave ports 11 */ +#define SEC_READONLY11 (LIFEC_SEC_BASE + 0x0204U) +/* Security write protection attribute setting for slave ports 12 */ +#define SEC_READONLY12 (LIFEC_SEC_BASE + 0x0208U) +/* Security write protection attribute setting for slave ports 13 */ +#define SEC_READONLY13 (LIFEC_SEC_BASE + 0x020CU) +/* Security write protection attribute setting for slave ports 14 */ +#define SEC_READONLY14 (LIFEC_SEC_BASE + 0x0210U) +/* Security write protection attribute setting for slave ports 15 */ +#define SEC_READONLY15 (LIFEC_SEC_BASE + 0x0214U) + +/* LIFEC1 (SAFETY) registers */ + +/* LIFEC1 (SAFETY) base address */ +#define LIFEC_SAFE_BASE (0xE6120000U) + +/* Safety group 0 attribute setting for master ports 0 */ +#define SAFE_GRP0CR0 (LIFEC_SAFE_BASE + 0x0138U) +/* Safety group 1 attribute setting for master ports 0 */ +#define SAFE_GRP1CR0 (LIFEC_SAFE_BASE + 0x013CU) +/* Safety group 0 attribute setting for master ports 1 */ +#define SAFE_GRP0CR1 (LIFEC_SAFE_BASE + 0x0140U) +/* Safety group 1 attribute setting for master ports 1 */ +#define SAFE_GRP1CR1 (LIFEC_SAFE_BASE + 0x0144U) +/* Safety group 0 attribute setting for master ports 2 */ +#define SAFE_GRP0CR2 (LIFEC_SAFE_BASE + 0x0148U) +/* Safety group 1 attribute setting for master ports 2 */ +#define SAFE_GRP1CR2 (LIFEC_SAFE_BASE + 0x014CU) +/* Safety group 0 attribute setting for master ports 3 */ +#define SAFE_GRP0CR3 (LIFEC_SAFE_BASE + 0x0150U) +/* Safety group 1 attribute setting for master ports 3 */ +#define SAFE_GRP1CR3 (LIFEC_SAFE_BASE + 0x0154U) +/* Safety group 0 attribute setting for slave ports 0 */ +#define SAFE_GRP0COND0 (LIFEC_SAFE_BASE + 0x0158U) +/* Safety group 1 attribute setting for slave ports 0 */ +#define SAFE_GRP1COND0 (LIFEC_SAFE_BASE + 0x015CU) +/* Safety group 0 attribute setting for slave ports 1 */ +#define SAFE_GRP0COND1 (LIFEC_SAFE_BASE + 0x0160U) +/* Safety group 1 attribute setting for slave ports 1 */ +#define SAFE_GRP1COND1 (LIFEC_SAFE_BASE + 0x0164U) +/* Safety group 0 attribute setting for slave ports 2 */ +#define SAFE_GRP0COND2 (LIFEC_SAFE_BASE + 0x0168U) +/* Safety group 1 attribute setting for slave ports 2 */ +#define SAFE_GRP1COND2 (LIFEC_SAFE_BASE + 0x016CU) +/* Safety group 0 attribute setting for slave ports 3 */ +#define SAFE_GRP0COND3 (LIFEC_SAFE_BASE + 0x0170U) +/* Safety group 1 attribute setting for slave ports 3 */ +#define SAFE_GRP1COND3 (LIFEC_SAFE_BASE + 0x0174U) +/* Safety group 0 attribute setting for slave ports 4 */ +#define SAFE_GRP0COND4 (LIFEC_SAFE_BASE + 0x0178U) +/* Safety group 1 attribute setting for slave ports 4 */ +#define SAFE_GRP1COND4 (LIFEC_SAFE_BASE + 0x017CU) +/* Safety group 0 attribute setting for slave ports 5 */ +#define SAFE_GRP0COND5 (LIFEC_SAFE_BASE + 0x0180U) +/* Safety group 1 attribute setting for slave ports 5 */ +#define SAFE_GRP1COND5 (LIFEC_SAFE_BASE + 0x0184U) +/* Safety group 0 attribute setting for slave ports 6 */ +#define SAFE_GRP0COND6 (LIFEC_SAFE_BASE + 0x0188U) +/* Safety group 1 attribute setting for slave ports 6 */ +#define SAFE_GRP1COND6 (LIFEC_SAFE_BASE + 0x018CU) +/* Safety group 0 attribute setting for slave ports 7 */ +#define SAFE_GRP0COND7 (LIFEC_SAFE_BASE + 0x0190U) +/* Safety group 1 attribute setting for slave ports 7 */ +#define SAFE_GRP1COND7 (LIFEC_SAFE_BASE + 0x0194U) +/* Safety group 0 attribute setting for slave ports 8 */ +#define SAFE_GRP0COND8 (LIFEC_SAFE_BASE + 0x0198U) +/* Safety group 1 attribute setting for slave ports 8 */ +#define SAFE_GRP1COND8 (LIFEC_SAFE_BASE + 0x019CU) +/* Safety group 0 attribute setting for slave ports 9 */ +#define SAFE_GRP0COND9 (LIFEC_SAFE_BASE + 0x01A0U) +/* Safety group 1 attribute setting for slave ports 9 */ +#define SAFE_GRP1COND9 (LIFEC_SAFE_BASE + 0x01A4U) +/* Safety group 0 attribute setting for slave ports 10 */ +#define SAFE_GRP0COND10 (LIFEC_SAFE_BASE + 0x01A8U) +/* Safety group 1 attribute setting for slave ports 10 */ +#define SAFE_GRP1COND10 (LIFEC_SAFE_BASE + 0x01ACU) +/* Safety group 0 attribute setting for slave ports 11 */ +#define SAFE_GRP0COND11 (LIFEC_SAFE_BASE + 0x01B0U) +/* Safety group 1 attribute setting for slave ports 11 */ +#define SAFE_GRP1COND11 (LIFEC_SAFE_BASE + 0x01B4U) +/* Safety group 0 attribute setting for slave ports 12 */ +#define SAFE_GRP0COND12 (LIFEC_SAFE_BASE + 0x01B8U) +/* Safety group 1 attribute setting for slave ports 12 */ +#define SAFE_GRP1COND12 (LIFEC_SAFE_BASE + 0x01BCU) +/* Safety group 0 attribute setting for slave ports 13 */ +#define SAFE_GRP0COND13 (LIFEC_SAFE_BASE + 0x01C0U) +/* Safety group 1 attribute setting for slave ports 13 */ +#define SAFE_GRP1COND13 (LIFEC_SAFE_BASE + 0x01C4U) +/* Safety group 0 attribute setting for slave ports 14 */ +#define SAFE_GRP0COND14 (LIFEC_SAFE_BASE + 0x01C8U) +/* Safety group 1 attribute setting for slave ports 14 */ +#define SAFE_GRP1COND14 (LIFEC_SAFE_BASE + 0x01CCU) +/* Safety group 0 attribute setting for slave ports 15 */ +#define SAFE_GRP0COND15 (LIFEC_SAFE_BASE + 0x01D0U) +/* Safety group 1 attribute setting for slave ports 15 */ +#define SAFE_GRP1COND15 (LIFEC_SAFE_BASE + 0x01D4U) +/* Safety write protection attribute setting for slave ports 0 */ +#define SAFE_READONLY0 (LIFEC_SAFE_BASE + 0x01D8U) +/* Safety write protection attribute setting for slave ports 1 */ +#define SAFE_READONLY1 (LIFEC_SAFE_BASE + 0x01DCU) +/* Safety write protection attribute setting for slave ports 2 */ +#define SAFE_READONLY2 (LIFEC_SAFE_BASE + 0x01E0U) +/* Safety write protection attribute setting for slave ports 3 */ +#define SAFE_READONLY3 (LIFEC_SAFE_BASE + 0x01E4U) +/* Safety write protection attribute setting for slave ports 4 */ +#define SAFE_READONLY4 (LIFEC_SAFE_BASE + 0x01E8U) +/* Safety write protection attribute setting for slave ports 5 */ +#define SAFE_READONLY5 (LIFEC_SAFE_BASE + 0x01ECU) +/* Safety write protection attribute setting for slave ports 6 */ +#define SAFE_READONLY6 (LIFEC_SAFE_BASE + 0x01F0U) +/* Safety write protection attribute setting for slave ports 7 */ +#define SAFE_READONLY7 (LIFEC_SAFE_BASE + 0x01F4U) +/* Safety write protection attribute setting for slave ports 8 */ +#define SAFE_READONLY8 (LIFEC_SAFE_BASE + 0x01F8U) +/* Safety write protection attribute setting for slave ports 9 */ +#define SAFE_READONLY9 (LIFEC_SAFE_BASE + 0x01FCU) +/* Safety write protection attribute setting for slave ports 10 */ +#define SAFE_READONLY10 (LIFEC_SAFE_BASE + 0x0200U) +/* Safety write protection attribute setting for slave ports 11 */ +#define SAFE_READONLY11 (LIFEC_SAFE_BASE + 0x0204U) +/* Safety write protection attribute setting for slave ports 12 */ +#define SAFE_READONLY12 (LIFEC_SAFE_BASE + 0x0208U) +/* Safety write protection attribute setting for slave ports 13 */ +#define SAFE_READONLY13 (LIFEC_SAFE_BASE + 0x020CU) +/* Safety write protection attribute setting for slave ports 14 */ +#define SAFE_READONLY14 (LIFEC_SAFE_BASE + 0x0210U) +/* Safety write protection attribute setting for slave ports 15 */ +#define SAFE_READONLY15 (LIFEC_SAFE_BASE + 0x0214U) + +#endif /* LIFEC_REGISTER_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/loader_main.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/loader_main.h new file mode 100644 index 0000000..c3afdad --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/loader_main.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef LOADER_MAIN_H__ +#define LOADER_MAIN_H__ + +uint32_t loader_main(void); + +#endif /* LOADER_MAIN_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/machine/_stdint.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/machine/_stdint.h new file mode 100644 index 0000000..e36c659 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/machine/_stdint.h @@ -0,0 +1,164 @@ +/*- + * Copyright (c) 2001, 2002 Mike Barcroft + * Copyright (c) 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Klaus Klein. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE__STDINT_H_ +#define _MACHINE__STDINT_H_ + +#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) + +#define INT8_C(c) (c) +#define INT16_C(c) (c) +#define INT32_C(c) (c) +#define INT64_C(c) (c ## L) + +#define UINT8_C(c) (c) +#define UINT16_C(c) (c) +#define UINT32_C(c) (c ## U) +#define UINT64_C(c) (c ## UL) + +#define INTMAX_C(c) INT64_C(c) +#define UINTMAX_C(c) UINT64_C(c) + +#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */ + +#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) + +/* + * ISO/IEC 9899:1999 + * 7.18.2.1 Limits of exact-width integer types + */ +/* Minimum values of exact-width signed integer types. */ +#define INT8_MIN (-0x7f-1) +#define INT16_MIN (-0x7fff-1) +#define INT32_MIN (-0x7fffffff-1) +#define INT64_MIN (-0x7fffffffffffffffL-1) + +/* Maximum values of exact-width signed integer types. */ +#define INT8_MAX 0x7f +#define INT16_MAX 0x7fff +#define INT32_MAX 0x7fffffff +#define INT64_MAX 0x7fffffffffffffffL + +/* Maximum values of exact-width unsigned integer types. */ +#define UINT8_MAX 0xff +#define UINT16_MAX 0xffff +#define UINT32_MAX 0xffffffffU +#define UINT64_MAX 0xffffffffffffffffUL + +/* + * ISO/IEC 9899:1999 + * 7.18.2.2 Limits of minimum-width integer types + */ +/* Minimum values of minimum-width signed integer types. */ +#define INT_LEAST8_MIN INT8_MIN +#define INT_LEAST16_MIN INT16_MIN +#define INT_LEAST32_MIN INT32_MIN +#define INT_LEAST64_MIN INT64_MIN + +/* Maximum values of minimum-width signed integer types. */ +#define INT_LEAST8_MAX INT8_MAX +#define INT_LEAST16_MAX INT16_MAX +#define INT_LEAST32_MAX INT32_MAX +#define INT_LEAST64_MAX INT64_MAX + +/* Maximum values of minimum-width unsigned integer types. */ +#define UINT_LEAST8_MAX UINT8_MAX +#define UINT_LEAST16_MAX UINT16_MAX +#define UINT_LEAST32_MAX UINT32_MAX +#define UINT_LEAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.3 Limits of fastest minimum-width integer types + */ +/* Minimum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MIN INT32_MIN +#define INT_FAST16_MIN INT32_MIN +#define INT_FAST32_MIN INT32_MIN +#define INT_FAST64_MIN INT64_MIN + +/* Maximum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MAX INT32_MAX +#define INT_FAST16_MAX INT32_MAX +#define INT_FAST32_MAX INT32_MAX +#define INT_FAST64_MAX INT64_MAX + +/* Maximum values of fastest minimum-width unsigned integer types. */ +#define UINT_FAST8_MAX UINT32_MAX +#define UINT_FAST16_MAX UINT32_MAX +#define UINT_FAST32_MAX UINT32_MAX +#define UINT_FAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.4 Limits of integer types capable of holding object pointers + */ +#define INTPTR_MIN INT64_MIN +#define INTPTR_MAX INT64_MAX +#define UINTPTR_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.5 Limits of greatest-width integer types + */ +#define INTMAX_MIN INT64_MIN +#define INTMAX_MAX INT64_MAX +#define UINTMAX_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.3 Limits of other integer types + */ +/* Limits of ptrdiff_t. */ +#define PTRDIFF_MIN INT64_MIN +#define PTRDIFF_MAX INT64_MAX + +/* Limits of sig_atomic_t. */ +#define SIG_ATOMIC_MIN INT32_MIN +#define SIG_ATOMIC_MAX INT32_MAX + +/* Limit of size_t. */ +#define SIZE_MAX UINT64_MAX + +#ifndef WCHAR_MIN /* Also possibly defined in */ +/* Limits of wchar_t. */ +#define WCHAR_MIN INT32_MIN +#define WCHAR_MAX INT32_MAX +#endif + +/* Limits of wint_t. */ +#define WINT_MIN INT32_MIN +#define WINT_MAX INT32_MAX + +#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ + +#endif /* !_MACHINE__STDINT_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/machine/_types.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/machine/_types.h new file mode 100644 index 0000000..0f1e14e --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/machine/_types.h @@ -0,0 +1,110 @@ +/*- + * Copyright (c) 2002 Mike Barcroft + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * From: @(#)ansi.h 8.2 (Berkeley) 1/4/94 + * From: @(#)types.h 8.3 (Berkeley) 1/5/94 + * $FreeBSD$ + */ + +#ifndef _MACHINE__TYPES_H_ +#define _MACHINE__TYPES_H_ + +#ifndef _SYS_CDEFS_H_ +#error this file needs sys/cdefs.h as a prerequisite +#endif + +/* + * Basic types upon which most other types are built. + */ +typedef __signed char __int8_t; +typedef unsigned char __uint8_t; +typedef short __int16_t; +typedef unsigned short __uint16_t; +typedef int __int32_t; +typedef unsigned int __uint32_t; +typedef long long __int64_t; +typedef unsigned long long __uint64_t; + +/* + * Standard type definitions. + */ +typedef __int32_t __clock_t; /* clock()... */ +typedef __int32_t __critical_t; +typedef double __double_t; +typedef float __float_t; +typedef __int32_t __intfptr_t; +typedef __int32_t __intmax_t; +typedef __int32_t __intptr_t; +typedef __int32_t __int_fast8_t; +typedef __int32_t __int_fast16_t; +typedef __int32_t __int_fast32_t; +typedef __int32_t __int_fast64_t; +typedef __int8_t __int_least8_t; +typedef __int16_t __int_least16_t; +typedef __int32_t __int_least32_t; +typedef __int64_t __int_least64_t; +typedef __int32_t __ptrdiff_t; /* ptr1 - ptr2 */ +typedef __int32_t __register_t; +typedef __int32_t __segsz_t; /* segment size (in pages) */ +typedef __uint32_t __size_t; /* sizeof() */ +typedef __int32_t __ssize_t; /* byte count or error */ +typedef __int32_t __time_t; /* time()... */ +typedef __uint32_t __uintfptr_t; +typedef __uint64_t __uintmax_t; +typedef __uint32_t __uintptr_t; +typedef __uint32_t __uint_fast8_t; +typedef __uint32_t __uint_fast16_t; +typedef __uint32_t __uint_fast32_t; +typedef __uint64_t __uint_fast64_t; +typedef __uint8_t __uint_least8_t; +typedef __uint16_t __uint_least16_t; +typedef __uint32_t __uint_least32_t; +typedef __uint64_t __uint_least64_t; +typedef __uint32_t __u_register_t; +typedef __uint32_t __vm_offset_t; +typedef __int32_t __vm_ooffset_t; +typedef __uint32_t __vm_paddr_t; +typedef __uint32_t __vm_pindex_t; +typedef __uint32_t __vm_size_t; + +/* + * Unusual type definitions. + */ +#ifdef __GNUCLIKE_BUILTIN_VARARGS +typedef __builtin_va_list __va_list; /* internally known to gcc */ +#else +typedef char * __va_list; +#endif /* __GNUCLIKE_BUILTIN_VARARGS */ +#if defined(__GNUCLIKE_BUILTIN_VAALIST) && !defined(__GNUC_VA_LIST) \ + && !defined(__NO_GNUC_VA_LIST) +#define __GNUC_VA_LIST +typedef __va_list __gnuc_va_list; /* compatibility w/GNU headers*/ +#endif + +#endif /* !_MACHINE__TYPES_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/mfis.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/mfis.h new file mode 100644 index 0000000..77eba7f --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/mfis.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2018-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef MFIS_H__ +#define MFIS_H__ + +#define MFIS_WPCNTR_PASSWORD (0xACCE0000U) +#define MFIS_WPCNTR_WPD_BIT (((uint32_t)1U) << 0U) + +void mfis_init(void); + +#endif /* MFIS_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/mfis_register.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/mfis_register.h new file mode 100644 index 0000000..d8bcc07 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/mfis_register.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2018-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef MFIS_REGISTER_H__ +#define MFIS_REGISTER_H__ + +/* MFIS registers */ + +/* MFIS base address */ +#define MFIS_BASE (0xE6260000U) + +/* MFIS Error Control0 Register */ +#define MFIS_MFIERRCTLR0 (MFIS_BASE + 0x0200U) +/* MFIS Error Control1 Register */ +#define MFIS_MFIERRCTLR1 (MFIS_BASE + 0x0204U) +/* MFIS Error Control2 Register */ +#define MFIS_MFIERRCTLR2 (MFIS_BASE + 0x0208U) +/* MFIS Error Control3 Register */ +#define MFIS_MFIERRCTLR3 (MFIS_BASE + 0x020CU) +/* MFIS Error Control4 Register */ +#define MFIS_MFIERRCTLR4 (MFIS_BASE + 0x0210U) +/* MFIS Error Control5 Register */ +#define MFIS_MFIERRCTLR5 (MFIS_BASE + 0x0214U) +/* MFIS Error Control6 Register */ +#define MFIS_MFIERRCTLR6 (MFIS_BASE + 0x0218U) +/* MFIS Error Control7 Register */ +#define MFIS_MFIERRCTLR7 (MFIS_BASE + 0x0260U) +/* MFIS Error Control8 Register */ +#define MFIS_MFIERRCTLR8 (MFIS_BASE + 0x026CU) +/* MFIS Error Control9 Register */ +#define MFIS_MFIERRCTLR9 (MFIS_BASE + 0x0804U) +/* MFIS Error Control10 Register */ +#define MFIS_MFIERRCTLR10 (MFIS_BASE + 0x0808U) +/* MFIS Error Control11 Register */ +#define MFIS_MFIERRCTLR11 (MFIS_BASE + 0x080CU) + +/* MFIS Error Target0 Register */ +#define MFIS_MFIERRTGTR0 (MFIS_BASE + 0x0280U) +/* MFIS Error Target1 Register */ +#define MFIS_MFIERRTGTR1 (MFIS_BASE + 0x0284U) +/* MFIS Error Target2 Register */ +#define MFIS_MFIERRTGTR2 (MFIS_BASE + 0x0288U) +/* MFIS Error Target3 Register */ +#define MFIS_MFIERRTGTR3 (MFIS_BASE + 0x028CU) +/* MFIS Error Target4 Register */ +#define MFIS_MFIERRTGTR4 (MFIS_BASE + 0x0290U) +/* MFIS Error Target5 Register */ +#define MFIS_MFIERRTGTR5 (MFIS_BASE + 0x0294U) +/* MFIS Error Target6 Register */ +#define MFIS_MFIERRTGTR6 (MFIS_BASE + 0x025CU) +/* MFIS Error Target7 Register */ +#define MFIS_MFIERRTGTR7 (MFIS_BASE + 0x0268U) +/* MFIS Error Target8 Register */ +#define MFIS_MFIERRTGTR8 (MFIS_BASE + 0x0274U) +/* MFIS Error Target9 Register */ +#define MFIS_MFIERRTGTR9 (MFIS_BASE + 0x081CU) +/* MFIS Error Target10 Register */ +#define MFIS_MFIERRTGTR10 (MFIS_BASE + 0x0820U) +/* MFIS Error Target11 Register */ +#define MFIS_MFIERRTGTR11 (MFIS_BASE + 0x0824U) + +/* External Error Request Hold Control Register */ +#define MFIS_MFIEXTRQHLDCNTR (MFIS_BASE + 0x08A0U) + +/* Write Protection Control Register */ +#define MFIS_MFISWPCNTR (MFIS_BASE + 0x0900U) + +#endif /* MFIS_REGISTER_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/micro_wait.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/micro_wait.h new file mode 100644 index 0000000..928919d --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/micro_wait.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef MICRO_WAIT_H__ +#define MICRO_WAIT_H__ + +#define TMU3_MEASUREMENT (1) /* for time measurement */ + +#ifndef __ASSEMBLY +void micro_wait(uint32_t count_us); + +/* Time measurement function using the TMU3. */ +#if (TMU3_MEASUREMENT == 1) +void init_TMU3(void); +void start_TMU3(void); +uint32_t snapshot_TCNT3(void); +void stop_TMU3(void); +#endif /* TMU3_MEASUREMENT */ + +#endif /* __ASSEMBLY */ + +#endif /* MICRO_TWAIT_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/mmio.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/mmio.h new file mode 100644 index 0000000..4973453 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/mmio.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef __MMIO_H__ +#define __MMIO_H__ + +#include + +static inline void mmio_write_8(uintptr_t addr, uint8_t value) +{ + *(volatile uint8_t* )addr = value; +} + +static inline uint8_t mmio_read_8(uintptr_t addr) +{ + return *(volatile uint8_t *)addr; +} + +static inline void mmio_write_16(uintptr_t addr, uint16_t value) +{ + *(volatile uint16_t *)addr = value; +} + +static inline uint16_t mmio_read_16(uintptr_t addr) +{ + return *(volatile uint16_t *)addr; +} + +static inline void mmio_write_32(uintptr_t addr, uint32_t value) +{ + *(volatile uint32_t *)addr = value; +} + +static inline uint32_t mmio_read_32(uintptr_t addr) +{ + return *(volatile uint32_t *)addr; +} + +static inline void mmio_write_64(uintptr_t addr, uint64_t value) +{ + *(volatile uint64_t *)addr = value; +} + +static inline uint64_t mmio_read_64(uintptr_t addr) +{ + return *(volatile uint64_t *)addr; +} + +static inline void mmio_clrsetbits_32(uintptr_t addr, + uint32_t clear, + uint32_t set) +{ + mmio_write_32(addr, (mmio_read_32(addr) & ~clear) | set); +} + +#endif /* __MMIO_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/pfc_init.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/pfc_init.h new file mode 100644 index 0000000..cf8b2dc --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/pfc_init.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef PFC_INIT_H__ +#define PFC_INIT_H__ + +void pfc_init(void); + +#endif /* PFC_INIT_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/protection_setting.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/protection_setting.h new file mode 100644 index 0000000..00f2c7b --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/protection_setting.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef PROTECTION_SETTING_H__ +#define PROTECTION_SETTING_H__ + +void axi_security_setting(void); +void gic_security_setting(void); +void sysc_security_setting(void); + +#endif /* PROTECTION_SETTING_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/qos_mstat390.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/qos_mstat390.h new file mode 100644 index 0000000..82bbc5e --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/qos_mstat390.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2019-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef QOS_MSTAT_H_ +#define QOS_MSTAT_H_ + +#include +typedef struct { + uint32_t addr; + uint64_t value; +} mstat_slot_t; + +static const mstat_slot_t mstat_fix[] = { + {0x0000U, 0x000000000000FFFFU}, + {0x0008U, 0x000000000000FFFFU}, + {0x0010U, 0x000000000000FFFFU}, + {0x0018U, 0x000000000000FFFFU}, + {0x0020U, 0x0014149E0000FFFFU}, + {0x0028U, 0x000C00000000FFFFU}, + {0x0030U, 0x001004020000FFFFU}, + {0x0038U, 0x00100C840000FFFFU}, + {0x0040U, 0x00100C840000FFFFU}, + {0x0048U, 0x000000000000FFFFU}, + {0x0050U, 0x001008530000FFFFU}, + {0x0058U, 0x001008530000FFFFU}, + {0x0060U, 0x000000000000FFFFU}, + {0x0068U, 0x0014087F0000FFFFU}, + {0x0070U, 0x001004110000FFFFU}, + {0x0078U, 0x0010085B0000FFFFU}, + {0x0080U, 0x0010085B0000FFFFU}, + {0x0088U, 0x000000000000FFFFU}, + {0x0090U, 0x0010042A0000FFFFU}, + {0x0098U, 0x0010042A0000FFFFU}, + {0x00A0U, 0x000C04020000FFFFU}, + {0x00A8U, 0x000C04020000FFFFU}, + {0x00B0U, 0x000C04020000FFFFU}, + {0x00B8U, 0x000C04020000FFFFU}, + {0x00C0U, 0x000C04020000FFFFU}, + {0x00C8U, 0x000C04020000FFFFU}, + {0x00D0U, 0x001404020000FFFFU}, + {0x00D8U, 0x000C04020000FFFFU}, + {0x00E0U, 0x000C04150000FFFFU}, + {0x00E8U, 0x000C04020000FFFFU}, + {0x00F0U, 0x000C04020000FFFFU}, + {0x00F8U, 0x000C04020000FFFFU}, + {0x0100U, 0x000C04020000FFFFU}, + {0x0108U, 0x000C04020000FFFFU}, + {0x0110U, 0x000C04020000FFFFU}, + {0x0118U, 0x000C04150000FFFFU}, + {0x0120U, 0x000C04020000FFFFU}, + {0x0128U, 0x000C04020000FFFFU}, + {0x0130U, 0x000C04020000FFFFU}, + {0x0138U, 0x000C04020000FFFFU}, + {0x0140U, 0x000C04020000FFFFU}, + {0x0148U, 0x000C04020000FFFFU}, +}; + +static const mstat_slot_t mstat_be[] = { + {0x0000U, 0x001000D002FFFC01U}, + {0x0008U, 0x001000D002FFFC01U}, + {0x0010U, 0x001001A002FFFC01U}, + {0x0018U, 0x001001A002FFFC01U}, + {0x0020U, 0x0000000000000000U}, + {0x0028U, 0x0000000000000000U}, + {0x0030U, 0x0000000000000000U}, + {0x0038U, 0x0000000000000000U}, + {0x0040U, 0x0000000000000000U}, + {0x0048U, 0x0000000000000000U}, + {0x0050U, 0x0000000000000000U}, + {0x0058U, 0x0000000000000000U}, + {0x0060U, 0x0000000000000000U}, + {0x0068U, 0x0000000000000000U}, + {0x0070U, 0x0000000000000000U}, + {0x0078U, 0x0000000000000000U}, + {0x0080U, 0x0000000000000000U}, + {0x0088U, 0x0000000000000000U}, + {0x0090U, 0x0000000000000000U}, + {0x0098U, 0x0000000000000000U}, + {0x00A0U, 0x0010003002FFFC01U}, + {0x00A8U, 0x0010003002FFFC01U}, + {0x00B0U, 0x0010003002FFFC01U}, + {0x00B8U, 0x0010003002FFFC01U}, + {0x00C0U, 0x0010003002FFFC01U}, + {0x00C8U, 0x0010003002FFFC01U}, + {0x00D0U, 0x0000000000000000U}, + {0x00D8U, 0x0010003002FFFC01U}, + {0x00E0U, 0x0000000000000000U}, + {0x00E8U, 0x0010003002FFFC01U}, + {0x00F0U, 0x0010003002FFFC01U}, + {0x00F8U, 0x0010003002FFFC01U}, + {0x0100U, 0x0010003002FFFC01U}, + {0x0108U, 0x0000000000000000U}, + {0x0110U, 0x0010003002FFFC01U}, + {0x0118U, 0x0000000000000000U}, + {0x0120U, 0x0010003002FFFC01U}, + {0x0128U, 0x0010003002FFFC01U}, + {0x0130U, 0x0010003002FFFC01U}, + {0x0138U, 0x0010003002FFFC01U}, + {0x0140U, 0x001001A002FFFC01U}, + {0x0148U, 0x001001A002FFFC01U}, +}; + +#endif /* QOS_MSTAT_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/qos_mstat780.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/qos_mstat780.h new file mode 100644 index 0000000..9e384ab --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/qos_mstat780.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2019-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef QOS_MSTAT_H_ +#define QOS_MSTAT_H_ + +#include +typedef struct { + uint32_t addr; + uint64_t value; +} mstat_slot_t; + +static const mstat_slot_t mstat_fix[] = { + {0x0000U, 0x000000000000FFFFU}, + {0x0008U, 0x000000000000FFFFU}, + {0x0010U, 0x000000000000FFFFU}, + {0x0018U, 0x000000000000FFFFU}, + {0x0020U, 0x0014153C0000FFFFU}, + {0x0028U, 0x000C00000000FFFFU}, + {0x0030U, 0x001004040000FFFFU}, + {0x0038U, 0x00100B080000FFFFU}, + {0x0040U, 0x00100B080000FFFFU}, + {0x0048U, 0x000000000000FFFFU}, + {0x0050U, 0x00100CA50000FFFFU}, + {0x0058U, 0x00100CA50000FFFFU}, + {0x0060U, 0x000000000000FFFFU}, + {0x0068U, 0x001410FE0000FFFFU}, + {0x0070U, 0x001008210000FFFFU}, + {0x0078U, 0x00100CB50000FFFFU}, + {0x0080U, 0x00100CB50000FFFFU}, + {0x0088U, 0x000000000000FFFFU}, + {0x0090U, 0x001008530000FFFFU}, + {0x0098U, 0x001008530000FFFFU}, + {0x00A0U, 0x000C04040000FFFFU}, + {0x00A8U, 0x000C04040000FFFFU}, + {0x00B0U, 0x000C04040000FFFFU}, + {0x00B8U, 0x000C04040000FFFFU}, + {0x00C0U, 0x000C04040000FFFFU}, + {0x00C8U, 0x000C04040000FFFFU}, + {0x00D0U, 0x001404040000FFFFU}, + {0x00D8U, 0x000C04040000FFFFU}, + {0x00E0U, 0x000C082A0000FFFFU}, + {0x00E8U, 0x000C04040000FFFFU}, + {0x00F0U, 0x000C04040000FFFFU}, + {0x00F8U, 0x000C04040000FFFFU}, + {0x0100U, 0x000C04040000FFFFU}, + {0x0108U, 0x000C04040000FFFFU}, + {0x0110U, 0x000C04040000FFFFU}, + {0x0118U, 0x000C082A0000FFFFU}, + {0x0120U, 0x000C04040000FFFFU}, + {0x0128U, 0x000C04040000FFFFU}, + {0x0130U, 0x000C04040000FFFFU}, + {0x0138U, 0x000C04040000FFFFU}, + {0x0140U, 0x000C04040000FFFFU}, + {0x0148U, 0x000C04040000FFFFU}, +}; + +static const mstat_slot_t mstat_be[] = { + {0x0000U, 0x001001A0017FFC01U}, + {0x0008U, 0x001001A0017FFC01U}, + {0x0010U, 0x00100340017FFC01U}, + {0x0018U, 0x00100340017FFC01U}, + {0x0020U, 0x0000000000000000U}, + {0x0028U, 0x0000000000000000U}, + {0x0030U, 0x0000000000000000U}, + {0x0038U, 0x0000000000000000U}, + {0x0040U, 0x0000000000000000U}, + {0x0048U, 0x0000000000000000U}, + {0x0050U, 0x0000000000000000U}, + {0x0058U, 0x0000000000000000U}, + {0x0060U, 0x0000000000000000U}, + {0x0068U, 0x0000000000000000U}, + {0x0070U, 0x0000000000000000U}, + {0x0078U, 0x0000000000000000U}, + {0x0080U, 0x0000000000000000U}, + {0x0088U, 0x0000000000000000U}, + {0x0090U, 0x0000000000000000U}, + {0x0098U, 0x0000000000000000U}, + {0x00A0U, 0x00100050017FFC01U}, + {0x00A8U, 0x00100050017FFC01U}, + {0x00B0U, 0x00100050017FFC01U}, + {0x00B8U, 0x00100050017FFC01U}, + {0x00C0U, 0x00100050017FFC01U}, + {0x00C8U, 0x00100050017FFC01U}, + {0x00D0U, 0x0000000000000000U}, + {0x00D8U, 0x00100050017FFC01U}, + {0x00E0U, 0x0000000000000000U}, + {0x00E8U, 0x00100050017FFC01U}, + {0x00F0U, 0x00100050017FFC01U}, + {0x00F8U, 0x00100050017FFC01U}, + {0x0100U, 0x00100050017FFC01U}, + {0x0108U, 0x0000000000000000U}, + {0x0110U, 0x00100050017FFC01U}, + {0x0118U, 0x0000000000000000U}, + {0x0120U, 0x00100050017FFC01U}, + {0x0128U, 0x00100050017FFC01U}, + {0x0130U, 0x00100050017FFC01U}, + {0x0138U, 0x00100050017FFC01U}, + {0x0140U, 0x00100340017FFC01U}, + {0x0148U, 0x00100340017FFC01U}, + +}; + +#endif /* QOS_MSTAT_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rcar_addr.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rcar_addr.h new file mode 100644 index 0000000..fdbf1f1 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rcar_addr.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef RCAR_ADDR_H__ +#define RCAR_ADDR_H__ + +uint32_t rcar_addr(uint32_t *main_cpu_addr); + +#endif /* RCAR_ADDR_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rcar_def.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rcar_def.h new file mode 100644 index 0000000..cec3d21 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rcar_def.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RCAR_DEF_H__ +#define RCAR_DEF_H__ + +/* Product register */ +#define RCAR_PRR (0xFFF00044U) /* Product register */ + +/******************************************************************************* + * RCAR product and cut information + ******************************************************************************/ +#define RCAR_PRODUCT_MASK (0x00007F00U) +#define RCAR_CUT_MASK (0x000000FFU) +#define RCAR_PRODUCT_V3M (0x00005400U) +#define RCAR_CUT_VER10 (0x00000000U) +#define RCAR_CUT_VER20 (0x00000010U) +#define RCAR_MAJOR_MASK (0x000000F0U) +#define RCAR_MINOR_MASK (0x0000000FU) +#define RCAR_PRODUCT_SHIFT (8U) +#define RCAR_MAJOR_SHIFT (4U) +#define RCAR_MINOR_SHIFT (0U) +#define RCAR_MAJOR_OFFSET (1U) + +/******************************************************************************* + * RCAR MD pin information + ******************************************************************************/ +#define RCAR_MODEMR (0xE6160060U) /* Mode pin register */ +#define MODEMR_BOOT_CPU_MASK (0x000000C0U) +#define MODEMR_BOOT_CPU_CR7 (0x000000C0U) +#define MODEMR_BOOT_CPU_CA57 (0x00000000U) +#define MODEMR_BOOT_CPU_CA53 (0x00000040U) + +/****************************************************************************************************************************************************************/ +/* Memory mapped Generic timer interfaces */ +/****************************************************************************************************************************************************************/ +#define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE + +/******************************************************************************* + * Boot CPU + ******************************************************************************/ +#define RCAR_BOOT_CA5X (0U) /* Master boot CPU is CA57/53 */ +#define RCAR_BOOT_CR7 (1U) /* Master boot CPU is CR7 */ + +/******************************************************************************* + * CR Loader GIC Base + ******************************************************************************/ +#define GICD_BASE (0xF1110000U) +#define GICC_BASE (0xF1120000U) + +/****************************************************************************************************************************************************************/ +/* Interrupt ID */ +/****************************************************************************************************************************************************************/ +#define ARM_IRQ_WDT (173U) /* System watch dog timer */ + +/******************************************************************************* + * Shared Data + ******************************************************************************/ + + +#endif /* RCAR_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rcar_pwrc.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rcar_pwrc.h new file mode 100644 index 0000000..ef5fd63 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rcar_pwrc.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef RCAR_PWRC_H__ +#define RCAR_PWRC_H__ + +/* RCAR Power controller register offset etc */ +#define PPOFFR_OFF 0x0 +#define PPONR_OFF 0x4 +#define PCOFFR_OFF 0x8 +#define PWKUPR_OFF 0xc +#define PSYSR_OFF 0x10 + +#define PWKUPR_WEN (1ull << 31) + +#define PSYSR_AFF_L2 (1 << 31) +#define PSYSR_AFF_L1 (1 << 30) +#define PSYSR_AFF_L0 (1 << 29) +#define PSYSR_WEN (1 << 28) +#define PSYSR_PC (1 << 27) +#define PSYSR_PP (1 << 26) + +#define PSYSR_WK_SHIFT (24) +#define PSYSR_WK_MASK (0x3) +#define PSYSR_WK(x) (((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK) + +#define WKUP_COLD 0x0 +#define WKUP_RESET 0x1 +#define WKUP_PPONR 0x2 +#define WKUP_GICREQ 0x3 + +#define RCAR_INVALID (0xffffffffU) +#define PSYSR_INVALID 0xffffffff + +#ifndef __ASSEMBLY__ + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void rcar_pwrc_cpuon(uint32_t boot_addr); + +#endif /*__ASSEMBLY__*/ + +#endif /* RCAR_PWRC_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rcar_version.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rcar_version.h new file mode 100644 index 0000000..609f49b --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rcar_version.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef RCAR_VERSION_H__ +#define RCAR_VERSION_H__ + +#include + +#define VER_SIZE (8U) +#define VERSION_OF_RENESAS "1.0.7" + +extern const uint8_t g_version_of_renesas[VER_SIZE]; + +#endif /* RCAR_VERSION_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rom_api.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rom_api.h new file mode 100644 index 0000000..67f9399 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rom_api.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef ROM_API_H__ +#define ROM_API_H__ + +#include + +#define SBROM_OK (0x00000000U) +#define SBROM_ILLEGAL_INPUT_PARAM_ERR (0x0B000001U) +#define SBROM_ILLEGAL_OEM_HASH_VALUE_ERR (0x0B000008U) +#define SBROM_ILLEGAL_LCS_FOR_OPERATION_ERR (0x0B000010U) +#define SBROM_HASH_NOT_PROGRAMMED_ERR (0x0B000100U) +#define SBROM_PUB_KEY_HASH_VALIDATION_FAILURE (0xF1000006U) +#define SBROM_RSA_SIG_VERIFICATION_FAILED (0xF1000007U) + +#define LCS_CM (0x0U) /* CM */ +#define LCS_DM (0x1U) /* DM */ +#define LCS_SD (0x3U) /* SD */ +#define LCS_SE (0x5U) /* SE */ +#define LCS_FA (0x7U) /* FA */ + +typedef uint32_t (*ROM_FuncReadFlash)(uint64_t srcAddr, + uint8_t *pDest, + uint32_t sizeToRead); + +uint32_t ROM_SecureBootAPI(uint32_t *pKeyCert, + uint32_t *pContentCert, + ROM_FuncReadFlash pFuncReadFlash); +uint32_t ROM_GetLcs(uint32_t *pLcs); + + +#endif /* ROM_API_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rpc_driver.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rpc_driver.h new file mode 100644 index 0000000..c8b62ba --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rpc_driver.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef RPC_DRIVER_H__ +#define RPC_DRIVER_H__ + +void init_rpc(void); + +#endif /* RPC_DRIVER_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rpc_register.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rpc_register.h new file mode 100644 index 0000000..1c3de70 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/rpc_register.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef RPC_REGISTER_H__ +#define RPC_REGISTER_H__ + +/* RPC base address */ +#define RPC_BASE (0xEE200000U) + +/* RPC common control */ +#define RPC_CMNCR (RPC_BASE + 0x0000U) +/* RPC ssl delay */ +#define RPC_SSLDR (RPC_BASE + 0x0004U) +/* RPC data read control */ +#define RPC_DRCR (RPC_BASE + 0x000CU) +/* RPC data read command setting */ +#define RPC_DRCMR (RPC_BASE + 0x0010U) +/* RPC read extended address setting register */ +#define RPC_DREAR (RPC_BASE + 0x0014U) +/* RPC data read enable setting */ +#define RPC_DRENR (RPC_BASE + 0x001CU) + +/* RPC manual mode control */ +#define RPC_SMCR (RPC_BASE + 0x0020U) +/* RPC manual mode command setting */ +#define RPC_SMCMR (RPC_BASE + 0x0024U) +/* RPC manual mode enable setting */ +#define RPC_SMENR (RPC_BASE + 0x0030U) + +/* RPC common status */ +#define RPC_CMNSR (RPC_BASE + 0x0048U) +/* RPC data read dummy cycle setting */ +#define RPC_DRDMCR (RPC_BASE + 0x0058U) +/* RPC data read ddr enable */ +#define RPC_DRDRENR (RPC_BASE + 0x005CU) + +/* RPC phy control */ +#define RPC_PHYCNT (RPC_BASE + 0x007CU) +/* RPC phy interrupt */ +#define RPC_PHYINT (RPC_BASE + 0x0088U) + +#endif /* RPC_REGISTER_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/scif.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/scif.h new file mode 100644 index 0000000..a93bf93 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/scif.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef __SCIF_H__ +#define __SCIF_H__ + + +#define SCIF_INTERNAL_CLK 0 /* Internal clock(S3D4:66.66MHz) */ +#define SCIF_EXTARNAL_CLK 1 /* External clock(SCK2:14.7456MHz) */ +#define SCIF_CLK SCIF_INTERNAL_CLK + + +#ifndef __ASSEMBLY +uint32_t console_init(void); +uint32_t console_putc(uint8_t c); +#endif /* __ASSEMBLY */ + +#endif /* __SCIF_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/stdarg.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/stdarg.h new file mode 100644 index 0000000..c315dfc --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/stdarg.h @@ -0,0 +1,75 @@ +/*- + * Copyright (c) 2002 David E. O'Brien. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_STDARG_H_ +#define _MACHINE_STDARG_H_ + +#include +#include + +#ifndef _VA_LIST_DECLARED +#define _VA_LIST_DECLARED +typedef __va_list va_list; +#endif + +#ifdef __GNUCLIKE_BUILTIN_STDARG + +#define va_start(ap, last) \ + __builtin_va_start((ap), (last)) + +#define va_arg(ap, type) \ + __builtin_va_arg((ap), type) + +#define __va_copy(dest, src) \ + __builtin_va_copy((dest), (src)) + +#if __ISO_C_VISIBLE >= 1999 +#define va_copy(dest, src) \ + __va_copy(dest, src) +#endif + +#define va_end(ap) \ + __builtin_va_end(ap) + +#elif defined(lint) +/* Provide a fake implementation for lint's benefit */ +#define __va_size(type) \ + (((sizeof(type) + sizeof(long) - 1) / sizeof(long)) * sizeof(long)) +#define va_start(ap, last) \ + ((ap) = (va_list)&(last) + __va_size(last)) +#define va_arg(ap, type) \ + (*(type *)((ap) += __va_size(type), (ap) - __va_size(type))) +#define va_end(ap) + +#else +#error this file needs to be ported to your compiler +#endif + +#endif /* !_MACHINE_STDARG_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/stddef.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/stddef.h new file mode 100644 index 0000000..ea88214 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/stddef.h @@ -0,0 +1,64 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stddef.h 8.1 (Berkeley) 6/2/93 + * + * $FreeBSD$ + */ + +#ifndef _STDDEF_H_ +#define _STDDEF_H_ + +#include +#include +#include + +typedef __ptrdiff_t ptrdiff_t; + +#if __BSD_VISIBLE +#ifndef _RUNE_T_DECLARED +typedef __rune_t rune_t; +#define _RUNE_T_DECLARED +#endif +#endif + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#ifndef __cplusplus +#ifndef _WCHAR_T_DECLARED +typedef __wchar_t wchar_t; +#define _WCHAR_T_DECLARED +#endif +#endif + +#define offsetof(type, member) __offsetof(type, member) + +#endif /* _STDDEF_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/stdint.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/stdint.h new file mode 100644 index 0000000..aa5ac81 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/stdint.h @@ -0,0 +1,74 @@ +/*- + * Copyright (c) 2001 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS_STDINT_H_ +#define _SYS_STDINT_H_ + +#include +#include + +#include +#include + +typedef __int_least8_t int_least8_t; +typedef __int_least16_t int_least16_t; +typedef __int_least32_t int_least32_t; +typedef __int_least64_t int_least64_t; + +typedef __uint_least8_t uint_least8_t; +typedef __uint_least16_t uint_least16_t; +typedef __uint_least32_t uint_least32_t; +typedef __uint_least64_t uint_least64_t; + +typedef __int_fast8_t int_fast8_t; +typedef __int_fast16_t int_fast16_t; +typedef __int_fast32_t int_fast32_t; +typedef __int_fast64_t int_fast64_t; + +typedef __uint_fast8_t uint_fast8_t; +typedef __uint_fast16_t uint_fast16_t; +typedef __uint_fast32_t uint_fast32_t; +typedef __uint_fast64_t uint_fast64_t; + +#ifndef _INTMAX_T_DECLARED +typedef __intmax_t intmax_t; +#define _INTMAX_T_DECLARED +#endif +#ifndef _UINTMAX_T_DECLARED +typedef __uintmax_t uintmax_t; +#define _UINTMAX_T_DECLARED +#endif + +/* GNU and Darwin define this and people seem to think it's portable */ +#if defined(UINTPTR_MAX) && defined(UINT64_MAX) && (UINTPTR_MAX == UINT64_MAX) +#define __WORDSIZE 64 +#else +#define __WORDSIZE 32 +#endif + +#endif /* !_SYS_STDINT_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/stdio.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/stdio.h new file mode 100644 index 0000000..57e5c7f --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/stdio.h @@ -0,0 +1,78 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stdio.h 8.5 (Berkeley) 4/29/95 + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2013-2014, ARM Limited and Contributors. + * All rights reserved. + */ + + +#ifndef _STDIO_H_ +#define _STDIO_H_ + +#include +#include +#include + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#ifndef _SSIZE_T_DECLARED +#define _SSIZE_T_DECLARED +typedef __ssize_t ssize_t; +#endif + +#define EOF (-1) + +int printf(const char * __restrict, ...) __printflike(1, 2); +int putchar(int); +int puts(const char *); +int sprintf(char * __restrict, const char * __restrict, ...) + __printflike(2, 3); +int vsprintf(char * __restrict, const char * __restrict, + __va_list) __printflike(2, 0); + +int sscanf(const char *__restrict, char const *__restrict, ...); + +#if __ISO_C_VISIBLE >= 1999 +int snprintf(char * __restrict, size_t, const char * __restrict, + ...) __printflike(3, 4); +int vsnprintf(char * __restrict, size_t, const char * __restrict, + __va_list) __printflike(3, 0); +#endif + +#endif /* !_STDIO_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/string.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/string.h new file mode 100644 index 0000000..61e8102 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/string.h @@ -0,0 +1,66 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)string.h 8.1 (Berkeley) 6/2/93 + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2013-2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include +#include +#include + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +__BEGIN_DECLS + +void *memchr(const void *, int, size_t) __pure; +int memcmp(const void *, const void *, size_t) __pure; +void *memcpy(void * __restrict, const void * __restrict, size_t); +void *memmove(void *, const void *, size_t); +void *memset(void *, int, size_t); + +char *strchr(const char *, int) __pure; +int strcmp(const char *, const char *) __pure; +size_t strlen(const char *) __pure; +int strncmp(const char *, const char *, size_t) __pure; +int strcasecmp(const char *, const char *); + +__END_DECLS + +#endif /* _STRING_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/swdt.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/swdt.h new file mode 100644 index 0000000..c379afd --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/swdt.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef SWDT_H__ +#define SWDT_H__ + +void swdt_init(void); + +void swdt_enable(void); + +void swdt_release(void); + +void swdt_exec(uint32_t occ_add); + +#endif /* SWDT_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/sys/_null.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/sys/_null.h new file mode 100644 index 0000000..92706c6 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/sys/_null.h @@ -0,0 +1,47 @@ +/*- + * Copyright (c) 2003 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef NULL + +#if !defined(__cplusplus) +#define NULL ((void *)0) +#else +#if __cplusplus >= 201103L +#define NULL nullptr +#elif defined(__GNUG__) && defined(__GNUC__) && __GNUC__ >= 4 +#define NULL __null +#else +#if defined(__LP64__) +#define NULL (0L) +#else +#define NULL 0 +#endif /* __LP64__ */ +#endif /* __GNUG__ */ +#endif /* !__cplusplus */ + +#endif diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/sys/_stdint.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/sys/_stdint.h new file mode 100644 index 0000000..d0f9249 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/sys/_stdint.h @@ -0,0 +1,82 @@ +/*- + * Copyright (c) 2011 David E. O'Brien + * Copyright (c) 2001 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS__STDINT_H_ +#define _SYS__STDINT_H_ + +#ifndef _INT8_T_DECLARED +typedef __int8_t int8_t; +#define _INT8_T_DECLARED +#endif + +#ifndef _INT16_T_DECLARED +typedef __int16_t int16_t; +#define _INT16_T_DECLARED +#endif + +#ifndef _INT32_T_DECLARED +typedef __int32_t int32_t; +#define _INT32_T_DECLARED +#endif + +#ifndef _INT64_T_DECLARED +typedef __int64_t int64_t; +#define _INT64_T_DECLARED +#endif + +#ifndef _UINT8_T_DECLARED +typedef __uint8_t uint8_t; +#define _UINT8_T_DECLARED +#endif + +#ifndef _UINT16_T_DECLARED +typedef __uint16_t uint16_t; +#define _UINT16_T_DECLARED +#endif + +#ifndef _UINT32_T_DECLARED +typedef __uint32_t uint32_t; +#define _UINT32_T_DECLARED +#endif + +#ifndef _UINT64_T_DECLARED +typedef __uint64_t uint64_t; +#define _UINT64_T_DECLARED +#endif + +#ifndef _INTPTR_T_DECLARED +typedef __intptr_t intptr_t; +#define _INTPTR_T_DECLARED +#endif +#ifndef _UINTPTR_T_DECLARED +typedef __uintptr_t uintptr_t; +#define _UINTPTR_T_DECLARED +#endif + +#endif /* !_SYS__STDINT_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/sys/_types.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/sys/_types.h new file mode 100644 index 0000000..1afeaea --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/sys/_types.h @@ -0,0 +1,106 @@ +/*- + * Copyright (c) 2002 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS__TYPES_H_ +#define _SYS__TYPES_H_ + +#include +#include + +/* + * Standard type definitions. + */ +typedef __uint32_t __blksize_t; /* file block size */ +typedef __int64_t __blkcnt_t; /* file block count */ +typedef __int32_t __clockid_t; /* clock_gettime()... */ +typedef __uint32_t __cap_rights_t; /* capability rights */ +typedef __uint32_t __fflags_t; /* file flags */ +typedef __uint32_t __fsblkcnt_t; +typedef __uint32_t __fsfilcnt_t; +typedef __uint32_t __gid_t; +typedef __int32_t __id_t; /* can hold a gid_t, pid_t, or uid_t */ +typedef __uint32_t __ino_t; /* inode number */ +typedef long __key_t; /* IPC key (for Sys V IPC) */ +typedef __int32_t __lwpid_t; /* Thread ID (a.k.a. LWP) */ +typedef __uint16_t __mode_t; /* permissions */ +typedef int __accmode_t; /* access permissions */ +typedef int __nl_item; +typedef __uint16_t __nlink_t; /* link count */ +typedef __int32_t __off_t; /* file offset */ +typedef __int32_t __pid_t; /* process [group] */ +typedef __int32_t __rlim_t; /* resource limit - intentionally */ + /* signed, because of legacy code */ + /* that uses -1 for RLIM_INFINITY */ +typedef __uint8_t __sa_family_t; +typedef __uint32_t __socklen_t; +typedef long __suseconds_t; /* microseconds (signed) */ +typedef struct __timer *__timer_t; /* timer_gettime()... */ +typedef struct __mq *__mqd_t; /* mq_open()... */ +typedef __uint32_t __uid_t; +typedef unsigned int __useconds_t; /* microseconds (unsigned) */ +typedef int __cpuwhich_t; /* which parameter for cpuset. */ +typedef int __cpulevel_t; /* level parameter for cpuset. */ +typedef int __cpusetid_t; /* cpuset identifier. */ + +/* + * Unusual type definitions. + */ +/* + * rune_t is declared to be an ``int'' instead of the more natural + * ``unsigned long'' or ``long''. Two things are happening here. It is not + * unsigned so that EOF (-1) can be naturally assigned to it and used. Also, + * it looks like 10646 will be a 31 bit standard. This means that if your + * ints cannot hold 32 bits, you will be in trouble. The reason an int was + * chosen over a long is that the is*() and to*() routines take ints (says + * ANSI C), but they use __ct_rune_t instead of int. + * + * NOTE: rune_t is not covered by ANSI nor other standards, and should not + * be instantiated outside of lib/libc/locale. Use wchar_t. wchar_t and + * rune_t must be the same type. Also, wint_t must be no narrower than + * wchar_t, and should be able to hold all members of the largest + * character set plus one extra value (WEOF), and must be at least 16 bits. + */ +typedef int __ct_rune_t; /* arg type for ctype funcs */ +typedef __ct_rune_t __rune_t; /* rune_t (see above) */ +typedef __ct_rune_t __wchar_t; /* wchar_t (see above) */ +typedef __ct_rune_t __wint_t; /* wint_t (see above) */ + +typedef __uint32_t __dev_t; /* device number */ + +typedef __uint32_t __fixpt_t; /* fixed point number */ + +/* + * mbstate_t is an opaque object to keep conversion state during multibyte + * stream conversions. + */ +typedef union { + char __mbstate8[128]; + __int64_t _mbstateL; /* for alignment */ +} __mbstate_t; + +#endif /* !_SYS__TYPES_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/sys/cdefs.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/sys/cdefs.h new file mode 100644 index 0000000..16fb151 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/sys/cdefs.h @@ -0,0 +1,686 @@ +/*- + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Berkeley Software Design, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)cdefs.h 8.8 (Berkeley) 1/9/95 + * $FreeBSD$ + */ + +#ifndef _SYS_CDEFS_H_ +#define _SYS_CDEFS_H_ + +#if defined(__cplusplus) +#define __BEGIN_DECLS extern "C" { +#define __END_DECLS } +#else +#define __BEGIN_DECLS +#define __END_DECLS +#endif + +/* + * This code has been put in place to help reduce the addition of + * compiler specific defines in FreeBSD code. It helps to aid in + * having a compiler-agnostic source tree. + */ + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) + +#if __GNUC__ >= 3 || defined(__INTEL_COMPILER) +#define __GNUCLIKE_ASM 3 +#define __GNUCLIKE_MATH_BUILTIN_CONSTANTS +#else +#define __GNUCLIKE_ASM 2 +#endif +#define __GNUCLIKE___TYPEOF 1 +#define __GNUCLIKE___OFFSETOF 1 +#define __GNUCLIKE___SECTION 1 + +#ifndef __INTEL_COMPILER +# define __GNUCLIKE_CTOR_SECTION_HANDLING 1 +#endif + +#define __GNUCLIKE_BUILTIN_CONSTANT_P 1 +# if defined(__INTEL_COMPILER) && defined(__cplusplus) \ + && __INTEL_COMPILER < 800 +# undef __GNUCLIKE_BUILTIN_CONSTANT_P +# endif + +#if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3) && !defined(__INTEL_COMPILER) +# define __GNUCLIKE_BUILTIN_VARARGS 1 +# define __GNUCLIKE_BUILTIN_STDARG 1 +# define __GNUCLIKE_BUILTIN_VAALIST 1 +#endif + +#if defined(__GNUC__) +# define __GNUC_VA_LIST_COMPATIBILITY 1 +#endif + +#ifndef __INTEL_COMPILER +# define __GNUCLIKE_BUILTIN_NEXT_ARG 1 +# define __GNUCLIKE_MATH_BUILTIN_RELOPS +#endif + +#define __GNUCLIKE_BUILTIN_MEMCPY 1 + +/* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */ +#define __CC_SUPPORTS_INLINE 1 +#define __CC_SUPPORTS___INLINE 1 +#define __CC_SUPPORTS___INLINE__ 1 + +#define __CC_SUPPORTS___FUNC__ 1 +#define __CC_SUPPORTS_WARNING 1 + +#define __CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */ + +#define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1 + +#endif /* __GNUC__ || __INTEL_COMPILER */ + +/* + * Macro to test if we're using a specific version of gcc or later. + */ +#if defined(__GNUC__) && !defined(__INTEL_COMPILER) +#define __GNUC_PREREQ__(ma, mi) \ + (__GNUC__ > (ma) || __GNUC__ == (ma) && __GNUC_MINOR__ >= (mi)) +#else +#define __GNUC_PREREQ__(ma, mi) 0 +#endif + +/* + * The __CONCAT macro is used to concatenate parts of symbol names, e.g. + * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. + * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI + * mode -- there must be no spaces between its arguments, and for nested + * __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also + * concatenate double-quoted strings produced by the __STRING macro, but + * this only works with ANSI C. + * + * __XSTRING is like __STRING, but it expands any macros in its argument + * first. It is only available with ANSI C. + */ +#if defined(__STDC__) || defined(__cplusplus) +#define __P(protos) protos /* full-blown ANSI C */ +#define __CONCAT1(x,y) x ## y +#define __CONCAT(x,y) __CONCAT1(x,y) +#define __STRING(x) #x /* stringify without expanding x */ +#define __XSTRING(x) __STRING(x) /* expand x, then stringify */ + +#define __const const /* define reserved names to standard */ +#define __signed signed +#define __volatile volatile +#if defined(__cplusplus) +#define __inline inline /* convert to C++ keyword */ +#else +#if !(defined(__CC_SUPPORTS___INLINE)) +#define __inline /* delete GCC keyword */ +#endif /* ! __CC_SUPPORTS___INLINE */ +#endif /* !__cplusplus */ + +#else /* !(__STDC__ || __cplusplus) */ +#define __P(protos) () /* traditional C preprocessor */ +#define __CONCAT(x,y) x/**/y +#define __STRING(x) "x" + +#if !defined(__CC_SUPPORTS___INLINE) +#define __const /* delete pseudo-ANSI C keywords */ +#define __inline +#define __signed +#define __volatile +/* + * In non-ANSI C environments, new programs will want ANSI-only C keywords + * deleted from the program and old programs will want them left alone. + * When using a compiler other than gcc, programs using the ANSI C keywords + * const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS. + * When using "gcc -traditional", we assume that this is the intent; if + * __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone. + */ +#ifndef NO_ANSI_KEYWORDS +#define const /* delete ANSI C keywords */ +#define inline +#define signed +#define volatile +#endif /* !NO_ANSI_KEYWORDS */ +#endif /* !__CC_SUPPORTS___INLINE */ +#endif /* !(__STDC__ || __cplusplus) */ + +/* + * Compiler-dependent macros to help declare dead (non-returning) and + * pure (no side effects) functions, and unused variables. They are + * null except for versions of gcc that are known to support the features + * properly (old versions of gcc-2 supported the dead and pure features + * in a different (wrong) way). If we do not provide an implementation + * for a given compiler, let the compile fail if it is told to use + * a feature that we cannot live without. + */ +#ifdef lint +#define __dead2 +#define __pure2 +#define __unused +#define __packed +#define __aligned(x) +#define __section(x) +#else +#if !__GNUC_PREREQ__(2, 5) && !defined(__INTEL_COMPILER) +#define __dead2 +#define __pure2 +#define __unused +#endif +#if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 && !defined(__INTEL_COMPILER) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused +/* XXX Find out what to do for __packed, __aligned and __section */ +#endif +#if __GNUC_PREREQ__(2, 7) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) +#endif +#if defined(__INTEL_COMPILER) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) +#endif +#endif + +#if !__GNUC_PREREQ__(2, 95) +#define __alignof(x) __offsetof(struct { char __a; x __b; }, __b) +#endif + +/* + * Keywords added in C11. + */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define _Alignas(e) alignas(e) +#define _Alignof(e) alignof(e) +#define _Noreturn [[noreturn]] +#define _Static_assert(e, s) static_assert(e, s) +/* FIXME: change this to thread_local when clang in base supports it */ +#define _Thread_local __thread +#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +/* Do nothing. They are language keywords. */ +#else +/* Not supported. Implement them using our versions. */ +#define _Alignas(x) __aligned(x) +#define _Alignof(x) __alignof(x) +#define _Noreturn __dead2 +#define _Thread_local __thread +#ifdef __COUNTER__ +#define _Static_assert(x, y) __Static_assert(x, __COUNTER__) +#define __Static_assert(x, y) ___Static_assert(x, y) +#define ___Static_assert(x, y) typedef char __assert_ ## y[(x) ? 1 : -1] +#else +#define _Static_assert(x, y) struct __hack +#endif +#endif + +/* + * Emulation of C11 _Generic(). Unlike the previously defined C11 + * keywords, it is not possible to implement this using exactly the same + * syntax. Therefore implement something similar under the name + * __generic(). Unlike _Generic(), this macro can only distinguish + * between a single type, so it requires nested invocations to + * distinguish multiple cases. + */ + +#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +#define __generic(expr, t, yes, no) \ + _Generic(expr, t: yes, default: no) +#elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus) +#define __generic(expr, t, yes, no) \ + __builtin_choose_expr( \ + __builtin_types_compatible_p(__typeof(expr), t), yes, no) +#endif + +#if __GNUC_PREREQ__(2, 96) +#define __malloc_like __attribute__((__malloc__)) +#define __pure __attribute__((__pure__)) +#else +#define __malloc_like +#define __pure +#endif + +#if __GNUC_PREREQ__(3, 1) || (defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 800) +#define __always_inline __attribute__((__always_inline__)) +#else +#define __always_inline +#endif + +#if __GNUC_PREREQ__(3, 1) +#define __noinline __attribute__ ((__noinline__)) +#else +#define __noinline +#endif + +#if __GNUC_PREREQ__(3, 3) +#define __nonnull(x) __attribute__((__nonnull__(x))) +#else +#define __nonnull(x) +#endif + +#if __GNUC_PREREQ__(3, 4) +#define __fastcall __attribute__((__fastcall__)) +#else +#define __fastcall +#endif + +#if __GNUC_PREREQ__(4, 1) +#define __returns_twice __attribute__((__returns_twice__)) +#else +#define __returns_twice +#endif + +/* XXX: should use `#if __STDC_VERSION__ < 199901'. */ +#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER) +#define __func__ NULL +#endif + +#if (defined(__INTEL_COMPILER) || (defined(__GNUC__) && __GNUC__ >= 2)) && !defined(__STRICT_ANSI__) || __STDC_VERSION__ >= 199901 +#define __LONG_LONG_SUPPORTED +#endif + +/* C++11 exposes a load of C99 stuff */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define __LONG_LONG_SUPPORTED +#ifndef __STDC_LIMIT_MACROS +#define __STDC_LIMIT_MACROS +#endif +#ifndef __STDC_CONSTANT_MACROS +#define __STDC_CONSTANT_MACROS +#endif +#endif + +/* + * GCC 2.95 provides `__restrict' as an extension to C90 to support the + * C99-specific `restrict' type qualifier. We happen to use `__restrict' as + * a way to define the `restrict' type qualifier without disturbing older + * software that is unaware of C99 keywords. + */ +#if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95) +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901 || defined(lint) +#define __restrict +#else +#define __restrict restrict +#endif +#endif + +/* + * GNU C version 2.96 adds explicit branch prediction so that + * the CPU back-end can hint the processor and also so that + * code blocks can be reordered such that the predicted path + * sees a more linear flow, thus improving cache behavior, etc. + * + * The following two macros provide us with a way to utilize this + * compiler feature. Use __predict_true() if you expect the expression + * to evaluate to true, and __predict_false() if you expect the + * expression to evaluate to false. + * + * A few notes about usage: + * + * * Generally, __predict_false() error condition checks (unless + * you have some _strong_ reason to do otherwise, in which case + * document it), and/or __predict_true() `no-error' condition + * checks, assuming you want to optimize for the no-error case. + * + * * Other than that, if you don't know the likelihood of a test + * succeeding from empirical or other `hard' evidence, don't + * make predictions. + * + * * These are meant to be used in places that are run `a lot'. + * It is wasteful to make predictions in code that is run + * seldomly (e.g. at subsystem initialization time) as the + * basic block reordering that this affects can often generate + * larger code. + */ +#if __GNUC_PREREQ__(2, 96) +#define __predict_true(exp) __builtin_expect((exp), 1) +#define __predict_false(exp) __builtin_expect((exp), 0) +#else +#define __predict_true(exp) (exp) +#define __predict_false(exp) (exp) +#endif + +#if __GNUC_PREREQ__(4, 2) +#define __hidden __attribute__((__visibility__("hidden"))) +#define __exported __attribute__((__visibility__("default"))) +#else +#define __hidden +#define __exported +#endif + +/* + * We define this here since , , and + * require it. + */ +#if __GNUC_PREREQ__(4, 1) +#define __offsetof(type, field) __builtin_offsetof(type, field) +#else +#ifndef __cplusplus +#define __offsetof(type, field) \ + ((__size_t)(__uintptr_t)((const volatile void *)&((type *)0)->field)) +#else +#define __offsetof(type, field) \ + (__offsetof__ (reinterpret_cast <__size_t> \ + (&reinterpret_cast \ + (static_cast (0)->field)))) +#endif +#endif +#define __rangeof(type, start, end) \ + (__offsetof(type, end) - __offsetof(type, start)) + +/* + * Given the pointer x to the member m of the struct s, return + * a pointer to the containing structure. When using GCC, we first + * assign pointer x to a local variable, to check that its type is + * compatible with member m. + */ +#if __GNUC_PREREQ__(3, 1) +#define __containerof(x, s, m) ({ \ + const volatile __typeof(((s *)0)->m) *__x = (x); \ + __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\ +}) +#else +#define __containerof(x, s, m) \ + __DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m)) +#endif + +/* + * Compiler-dependent macros to declare that functions take printf-like + * or scanf-like arguments. They are null except for versions of gcc + * that are known to support the features properly (old versions of gcc-2 + * didn't permit keeping the keywords out of the application namespace). + */ +#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER) +#define __printflike(fmtarg, firstvararg) +#define __scanflike(fmtarg, firstvararg) +#define __format_arg(fmtarg) +#define __strfmonlike(fmtarg, firstvararg) +#define __strftimelike(fmtarg, firstvararg) +#else +#define __printflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf__, fmtarg, firstvararg))) +#define __scanflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__scanf__, fmtarg, firstvararg))) +#define __format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg))) +#define __strfmonlike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strfmon__, fmtarg, firstvararg))) +#define __strftimelike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strftime__, fmtarg, firstvararg))) +#endif + +/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */ +#if __FreeBSD_cc_version >= 300001 && defined(__GNUC__) && !defined(__INTEL_COMPILER) +#define __printf0like(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf0__, fmtarg, firstvararg))) +#else +#define __printf0like(fmtarg, firstvararg) +#endif + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) +#ifndef __INTEL_COMPILER +#define __strong_reference(sym,aliassym) \ + extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym))) +#endif +#ifdef __STDC__ +#define __weak_reference(sym,alias) \ + __asm__(".weak " #alias); \ + __asm__(".equ " #alias ", " #sym) +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning." #sym); \ + __asm__(".asciz \"" msg "\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@" #verid) +#define __sym_default(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@@" #verid) +#else +#define __weak_reference(sym,alias) \ + __asm__(".weak alias"); \ + __asm__(".equ alias, sym") +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning.sym"); \ + __asm__(".asciz \"msg\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver impl, sym@verid") +#define __sym_default(impl,sym,verid) \ + __asm__(".symver impl, sym@@verid") +#endif /* __STDC__ */ +#endif /* __GNUC__ || __INTEL_COMPILER */ + +#define __GLOBL1(sym) __asm__(".globl " #sym) +#define __GLOBL(sym) __GLOBL1(sym) + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) +#define __IDSTRING(name,string) __asm__(".ident\t\"" string "\"") +#else +/* + * The following definition might not work well if used in header files, + * but it should be better than nothing. If you want a "do nothing" + * version, then it should generate some harmless declaration, such as: + * #define __IDSTRING(name,string) struct __hack + */ +#define __IDSTRING(name,string) static const char name[] __unused = string +#endif + +/* + * Embed the rcs id of a source file in the resulting library. Note that in + * more recent ELF binutils, we use .ident allowing the ID to be stripped. + * Usage: + * __FBSDID("$FreeBSD$"); + */ +#ifndef __FBSDID +#if !defined(lint) && !defined(STRIP_FBSDID) +#define __FBSDID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __FBSDID(s) struct __hack +#endif +#endif + +#ifndef __RCSID +#ifndef NO__RCSID +#define __RCSID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __RCSID(s) struct __hack +#endif +#endif + +#ifndef __RCSID_SOURCE +#ifndef NO__RCSID_SOURCE +#define __RCSID_SOURCE(s) __IDSTRING(__CONCAT(__rcsid_source_,__LINE__),s) +#else +#define __RCSID_SOURCE(s) struct __hack +#endif +#endif + +#ifndef __SCCSID +#ifndef NO__SCCSID +#define __SCCSID(s) __IDSTRING(__CONCAT(__sccsid_,__LINE__),s) +#else +#define __SCCSID(s) struct __hack +#endif +#endif + +#ifndef __COPYRIGHT +#ifndef NO__COPYRIGHT +#define __COPYRIGHT(s) __IDSTRING(__CONCAT(__copyright_,__LINE__),s) +#else +#define __COPYRIGHT(s) struct __hack +#endif +#endif + +#ifndef __DECONST +#define __DECONST(type, var) ((type)(__uintptr_t)(const void *)(var)) +#endif + +#ifndef __DEVOLATILE +#define __DEVOLATILE(type, var) ((type)(__uintptr_t)(volatile void *)(var)) +#endif + +#ifndef __DEQUALIFY +#define __DEQUALIFY(type, var) ((type)(__uintptr_t)(const volatile void *)(var)) +#endif + +/*- + * The following definitions are an extension of the behavior originally + * implemented in , but with a different level of granularity. + * POSIX.1 requires that the macros we test be defined before any standard + * header file is included. + * + * Here's a quick run-down of the versions: + * defined(_POSIX_SOURCE) 1003.1-1988 + * _POSIX_C_SOURCE == 1 1003.1-1990 + * _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option + * _POSIX_C_SOURCE == 199309 1003.1b-1993 + * _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995, + * and the omnibus ISO/IEC 9945-1: 1996 + * _POSIX_C_SOURCE == 200112 1003.1-2001 + * _POSIX_C_SOURCE == 200809 1003.1-2008 + * + * In addition, the X/Open Portability Guide, which is now the Single UNIX + * Specification, defines a feature-test macro which indicates the version of + * that specification, and which subsumes _POSIX_C_SOURCE. + * + * Our macros begin with two underscores to avoid namespace screwage. + */ + +/* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 1 +#undef _POSIX_C_SOURCE /* Probably illegal, but beyond caring now. */ +#define _POSIX_C_SOURCE 199009 +#endif + +/* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 2 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199209 +#endif + +/* Deal with various X/Open Portability Guides and Single UNIX Spec. */ +#ifdef _XOPEN_SOURCE +#if _XOPEN_SOURCE - 0 >= 700 +#define __XSI_VISIBLE 700 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809 +#elif _XOPEN_SOURCE - 0 >= 600 +#define __XSI_VISIBLE 600 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200112 +#elif _XOPEN_SOURCE - 0 >= 500 +#define __XSI_VISIBLE 500 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199506 +#endif +#endif + +/* + * Deal with all versions of POSIX. The ordering relative to the tests above is + * important. + */ +#if defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE) +#define _POSIX_C_SOURCE 198808 +#endif +#ifdef _POSIX_C_SOURCE +#if _POSIX_C_SOURCE >= 200809 +#define __POSIX_VISIBLE 200809 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 200112 +#define __POSIX_VISIBLE 200112 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 199506 +#define __POSIX_VISIBLE 199506 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199309 +#define __POSIX_VISIBLE 199309 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199209 +#define __POSIX_VISIBLE 199209 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199009 +#define __POSIX_VISIBLE 199009 +#define __ISO_C_VISIBLE 1990 +#else +#define __POSIX_VISIBLE 198808 +#define __ISO_C_VISIBLE 0 +#endif /* _POSIX_C_SOURCE */ +#else +/*- + * Deal with _ANSI_SOURCE: + * If it is defined, and no other compilation environment is explicitly + * requested, then define our internal feature-test macros to zero. This + * makes no difference to the preprocessor (undefined symbols in preprocessing + * expressions are defined to have value zero), but makes it more convenient for + * a test program to print out the values. + * + * If a program mistakenly defines _ANSI_SOURCE and some other macro such as + * _POSIX_C_SOURCE, we will assume that it wants the broader compilation + * environment (and in fact we will never get here). + */ +#if defined(_ANSI_SOURCE) /* Hide almost everything. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1990 +#elif defined(_C99_SOURCE) /* Localism to specify strict C99 env. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1999 +#else /* Default environment: show everything. */ +#define __POSIX_VISIBLE 200809 +#define __XSI_VISIBLE 700 +#define __BSD_VISIBLE 1 +#define __ISO_C_VISIBLE 1999 +#endif +#endif + +#ifndef __has_feature +#define __has_feature(x) 0 +#endif +#ifndef __has_include +#define __has_include(x) 0 +#endif +#ifndef __has_builtin +#define __has_builtin(x) 0 +#endif + +#if defined(__mips) || defined(__powerpc64__) || defined(__arm__) +#define __NO_TLS 1 +#endif + +#endif /* !_SYS_CDEFS_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/ths_init.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/ths_init.h new file mode 100644 index 0000000..763505b --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/include/ths_init.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2020-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef THS_INIT_H__ +#define THS_INIT_H__ + +void ths_conv(void); + +#endif /* THS_INIT_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/cpg_init.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/cpg_init.c new file mode 100644 index 0000000..9ad1d8c --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/cpg_init.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file cgp_init.c + * - Version : 0.01 + * @brief Initial setting process of CPG. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include "cpg_register.h" +#include "cpg_init.h" +#include "rcar_def.h" + +/* define for ASTPOFFR register */ +#define IMP0_A_DISABLE (((uint32_t)1U) << 12U) +#define IMP1_A_DISABLE (((uint32_t)1U) << 13U) +#define IMP2_A_DISABLE (((uint32_t)1U) << 14U) +#define IMP3_A_DISABLE (((uint32_t)1U) << 15U) + +typedef struct { + uintptr_t adr; + uint32_t val; +} st_reg_setting_t; + +static const st_reg_setting_t s_reg_setting_rt[] = { + + /* CPG (REALTIME) registers */ + + /* Realtime Module Stop Control Register 0 */ + {RMSTPCR0, 0x00000000U}, + /* Realtime Module Stop Control Register 1 */ + {RMSTPCR1, 0xFDDFFFFFU}, + /* Realtime Module Stop Control Register 2 */ + {RMSTPCR2, 0x00000000U}, + /* Realtime Module Stop Control Register 3 */ + {RMSTPCR3, 0xFF7FFF19U}, + /* Realtime Module Stop Control Register 4 */ + {RMSTPCR4, 0x00000000U}, + /* Realtime Module Stop Control Register 5 */ + {RMSTPCR5, 0x83BFFFD7U}, + /* Realtime Module Stop Control Register 6 */ + {RMSTPCR6, 0xFFFFFFFFU}, + /* Realtime Module Stop Control Register 7 */ + {RMSTPCR7, 0xFFFFFFFFU}, + /* Realtime Module Stop Control Register 8 */ + {RMSTPCR8, 0x7FF3EFF4U}, + /* Realtime Module Stop Control Register 9 */ + {RMSTPCR9, 0x03F1A017U} +}; + +static const st_reg_setting_t s_reg_setting_safety[] = { + + /* CPG (SAFETY) registers */ + + /* Safety Module Stop Control Register 0 */ + {SAMSTPCR0, 0xFFFFFFFFU}, + /* Safety Module Stop Control Register 1 */ + {SAMSTPCR1, 0xFFFFFFFFU}, + /* Safety Module Stop Control Register 2 */ + {SAMSTPCR2, 0xFFFFFFFFU}, + /* Safety Module Stop Control Register 3 */ + {SAMSTPCR3, 0xFFFFFFFFU}, + /* Safety Module Stop Control Register 4 */ + {SAMSTPCR4, 0xFFFFFFFFU}, + /* Safety Module Stop Control Register 5 */ + {SAMSTPCR5, 0xFFFFFFFFU}, + /* Safety Module Stop Control Register 6 */ + {SAMSTPCR6, 0xFFFFFFFFU}, + /* Safety Module Stop Control Register 7 */ + {SAMSTPCR7, 0xFFFFFFFFU}, + /* Safety Module Stop Control Register 8 */ + {SAMSTPCR8, 0xFFFFFFFFU}, + /* Safety Module Stop Control Register 9 */ + {SAMSTPCR9, 0xFFFFFFFFU} +}; + + +void cpg_init(void) +{ + uint32_t i; + uint32_t ie; + uint32_t reg; + + /* CPG (Realtime) registers */ + ie = (uint32_t)(sizeof(s_reg_setting_rt) / sizeof(st_reg_setting_t)); + + for (i = 0U; i < ie; i++) + { + cpg_write(s_reg_setting_rt[i].adr, s_reg_setting_rt[i].val); + } + + /* CPG (Safety) registers */ + ie = (uint32_t)(sizeof(s_reg_setting_safety) / sizeof(st_reg_setting_t)); + + for (i = 0U; i < ie; i++) + { + cpg_write(s_reg_setting_safety[i].adr, s_reg_setting_safety[i].val); + } + + /* Disable automatic module clock stop function */ + reg = mmio_read_32(RCAR_PRR); + if ((reg & RCAR_CUT_MASK) == RCAR_CUT_VER20) + { + reg = mmio_read_32(ASTPOFFR); + reg |= (IMP0_A_DISABLE | IMP1_A_DISABLE | IMP2_A_DISABLE | + IMP3_A_DISABLE); + cpg_write(ASTPOFFR, reg); + } +} +/* End of function cpg_init */ + +void cpg_write(uintptr_t regadr, uint32_t regval) +{ + uint32_t value = (regval); + mmio_write_32((uintptr_t)CPG_CPGWPR,~value); + mmio_write_32(regadr,value); +} +/* End of function cpg_write */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/loader.S b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/loader.S new file mode 100644 index 0000000..4852b51 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/loader.S @@ -0,0 +1,270 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#define MODE_FIQ (0x11) +#define MODE_IRQ (0x12) +#define MODE_SVC (0x13) +#define MODE_ABT (0x17) +#define MODE_UND (0x1B) +#define MODE_SYS (0x1F) + +#define ARMREG_P_CR7SS (0xE6271800) +#define SYSRAM_BASE (0xE6300000) +#define SCU_BASE (0xF0000000) + +#define TCM_ENABLE (0x00000001) +#define ITCM_BASE (0xEB000000) +#define DTCM_BASE (0xEB020000) +#define ITCMRR_INIT_TADA (ITCM_BASE | TCM_ENABLE) +#define DTCMRR_INIT_TADA (DTCM_BASE | TCM_ENABLE) + +#define WBWA (0x00B) /* Write-Back Write Allocate */ +#define WT (0x002) /* Write-Through */ +#define NC (0x008) /* Non-cacheable */ +#define DEV (0x001) /* Device */ +#define SO (0x000) /* Strongly Ordered */ +#define SHARE (0x004) /* Shareable */ +#define AP_FULL (0x300) + +#define REGION_SIZE_4KB (0x16) +#define REGION_SIZE_8KB (0x18) +#define REGION_SIZE_16KB (0x1A) +#define REGION_SIZE_32KB (0x1C) +#define REGION_SIZE_64KB (0x1E) +#define REGION_SIZE_128KB (0x20) +#define REGION_SIZE_256KB (0x22) +#define REGION_SIZE_512KB (0x24) +#define REGION_SIZE_1MB (0x26) +#define REGION_SIZE_2MB (0x28) +#define REGION_SIZE_4MB (0x2A) +#define REGION_SIZE_8MB (0x2C) +#define REGION_SIZE_16MB (0x2E) +#define REGION_SIZE_32MB (0x30) +#define REGION_SIZE_64MB (0x32) +#define REGION_SIZE_128MB (0x34) +#define REGION_SIZE_256MB (0x36) +#define REGION_SIZE_512MB (0x38) +#define REGION_SIZE_1GB (0x3A) +#define REGION_SIZE_2GB (0x3C) +#define REGION_SIZE_4GB (0x3E) + +#define REGION_ENABLE (0x1) + +#define REGION0_SIZE (REGION_SIZE_4GB | REGION_ENABLE) +#define REGION1_SIZE (REGION_SIZE_512MB | REGION_ENABLE) +#define REGION2_SIZE (REGION_SIZE_512KB | REGION_ENABLE) +#define REGION3_SIZE (REGION_SIZE_64KB | REGION_ENABLE) +#define REGION4_SIZE (REGION_SIZE_64KB | REGION_ENABLE) + +#define REGION0_BASE (0x00000000) +#define REGION1_BASE (0xE0000000) +#define REGION2_BASE (0xE6300000) +#define REGION3_BASE (ITCM_BASE) +#define REGION4_BASE (0xEB100000) + +#define REGION0_ATTR (AP_FULL | WBWA | SHARE) +#define REGION1_ATTR (AP_FULL | DEV | SHARE) +#define REGION2_ATTR (AP_FULL | WBWA | SHARE) +#define REGION3_ATTR (AP_FULL | WBWA | SHARE) +#define REGION4_ATTR (AP_FULL | WBWA | SHARE) + + +#define SCTLR_I (1 << 12) +#define SCTLR_M (1 << 0) + + .global Startup + .global do_panic + + .global loader_main + .global ecc_init + .global dram_ecc_init + .global rcar_addr + + .align 5 + +/***************************************************************************** + * Reset Hander + *****************************************************************************/ +Startup: + /* initialize registers*/ + mov r0, #0 + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 + mov r8, #0 + mov r9, #0 + mov r10, #0 + mov r11, #0 + mov r12, #0 + mov lr, #0 + + ldr r0, =__STACKS_END__ + + /* stack initialize */ + msr CPSR_c, #(0x17 | 0x80 | 0x40) /* ABT */ + mov sp, r0 /* STACK_BASE_ABT */ + + msr CPSR_c, #(0x1B | 0x80 | 0x40) /* UND */ + sub r0, r0, #0x80 /* STACK_BASE_UND */ + mov sp, r0 + + msr CPSR_c, #(0x11 | 0x80 | 0x40) /* FIQ */ + sub r0, r0, #0x80 /* STACK_BASE_FIQ */ + mov sp, r0 + + msr CPSR_c, #(0x12 | 0x80 | 0x40) /* IRQ */ + sub r0, r0, #0x80 /* STACK_BASE_IRQ */ + mov sp, r0 + + msr CPSR_c, #(0x13 | 0x80 | 0x40) /* SVC */ + sub r0, r0, #0x80 /* STACK_BASE_SVC */ + mov sp, r0 + + /* Dual core lock step enable */ + ldr r0, =(0xE6271800) /* ARMREG_P_CR7SS */ + ldr r1, [r0] + orr r1, r1, #0x80000000 /* bit31 */ + str r1, [r0] + + /* Cache ECC error detection enable */ + mov r0, #0 + mcr p15, 0, r0, c15, c2, 0 /* DEER0 */ + mcr p15, 0, r0, c15, c2, 1 /* DEER1 */ + mcr p15, 0, r0, c15, c2, 2 /* DEER2 */ + mcr p15, 0, r0, c15, c3, 0 /* IEER0 */ + mcr p15, 0, r0, c15, c3, 1 /* IEER1 */ + mcr p15, 0, r0, c15, c3, 2 /* IEER2 */ + + + /* Instruction cache enable */ + mrc p15, 0, r1, c1, c0, 0 /* SCTLR */ + orr R1, R1, #1 << 12 /* I=1 */ + orr R1, R1, #1 << 11 /* Z=1 */ + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + mcr p15, 0, r1, c1, c0, 0 /* SCTLR */ + isb + + /* Invalidate D-Cache */ + mov r10, #0 + mcr p15, 2, r10, c0, c0, 0 /* CSSELR */ + isb + + mrc p15, 1, r1, c0, c0, 0 /* CCSIDR */ + and r2, r1, #7 /* b001=8word/line */ + add r2, r2, #4 /* DCISW calc shift */ + ldr r4, =0x3FF /* mac way mask */ + ands r4, r4, r1, LSR #3 /* r4 = way */ + clz r5, r4 + ldr r7,=0x7FFF + ands r7, r7, r1, LSR #13 +inv_d_cache_loop2: + mov r9, r4 +inv_d_cache_loop3: + orr r11, r10, r9, LSL r5 + orr r11, r11, r7, LSL r2 + mcr p15, 0, r11, c7, c6, 2 + subs r9, r9, #1 + bge inv_d_cache_loop3 + subs r7, r7, #1 + bge inv_d_cache_loop2 + + /* clear bss section */ + mov r0, #0x0 + ldr r1, =__BSS_START__ + ldr r2, =__BSS_SIZE__ +bss_loop: + subs r2, r2, #4 + bcc bss_end + str r0, [r1, +r2] + b bss_loop +bss_end: + + /* copy data section */ + ldr r0, =__DATA_COPY_START__ + ldr r1, =__DATA_START__ + ldr r2, =__DATA_SIZE__ +data_loop: + subs r2, r2, #4 + bcc data_end + ldr r3, [r0, +r2] + str r3, [r1, +r2] + b data_loop + +data_end: + + /* Loader Main */ + BL loader_main + + /* System RAM/SDRAM ECC enable */ + bl ecc_init + bl dram_ecc_init + + /* Loader Main */ + sub sp, sp, #8 + mov r0, sp + bl rcar_addr + ldr r1, [sp, #0] + add sp, sp, #8 + push {r0, r1} /* r0 = CR7 boot address */ + mov r0, r1 + push {r0, r1} /* r0 = CA5x boot address */ + + /* serial outpu wait */ + bl console_wait + + /* GIC Non Secure setting */ + bl gic_security_setting + +#if RCAR_DISABLE_AXI_LIFEC_SYSC == 0 + /* SRAM/DRAM protection setting */ + bl axi_security_setting + + /* LifeC setting */ + bl lifec_init +#endif + + /* CA57/53 bootup */ + pop {r0, r1} + bl rcar_pwrc_cpuon + +#if RCAR_DISABLE_AXI_LIFEC_SYSC == 0 + /* LifeC setting for CR7 */ + bl lifec_cr7_setting + + /* SYSC setting */ + bl sysc_security_setting +#endif + + /* Instruction cache invalidate & branch predictor invalidate */ + mrc p15, 0, r0, c1, c0, 0 /* SCTLR */ + bic R0, R0, #0x1 <<12 /* I = 0 */ + bic R0, R0, #0x1 <<11 /* Z = 0 */ + mcr p15, 0, r0, c1, c0, 0 + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + isb + + /* Jump to RTOS */ + pop {r0, r1} + bx r0 /* RTOS_BASE */ + NOP + NOP + NOP + +do_panic: + nop +1: + wfe + b 1b + + +/***************************************************************************** + * Exception Handers + *****************************************************************************/ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/loader.ld.S b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/loader.ld.S new file mode 100644 index 0000000..bfa0666 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/loader.ld.S @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + + +OUTPUT_FORMAT("elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(Startup) + +MEMORY { + RAM (rwxa): ORIGIN = 0xE6304000, LENGTH = 0x0002A800 +} + + +SECTIONS +{ + ASSERT(. == ALIGN(4096), + "CR7 Loader address is not aligned on a page boundary.") + + .loader_start : { + __RO_START__ = .; + loader/loader.o(.text*) + . = NEXT(1024); + *rcar_version.o(.version*) + . = NEXT(16); + *scif.o(".text*" ".rodata*") + *cpsr_acc.o(".text*" ".rodata*") + *report_exception.o(".text*" ".rodata*") + *arm_gic.o(".text*" ".rodata*") + *gic_v2.o(".text*" ".rodata*") + *error_output.o(".text*" ".rodata*") + *micro_wait.o(".text*" ".rodata*") + *protection_setting.o(".text*" ".rodata*") + *mem.o(".text*" ".rodata*") + *rom_api.o(".text*" ".rodata*") + *swdt.o(".text*" ".rodata*") + *dma_driver.o(".text*" ".rodata*") + *printf.o(".text*" ".rodata*") + *rcar_pwrc.o(".text*" ".rodata*") + *rpc_driver.o(".text*" ".rodata*") + *auth.o(".text*" ".rodata*") + *lifec_init.o(".text*" ".rodata*") + *mfis_init.o(".text*" ".rodata*") + *edc_init.o(".text*" ".rodata*") + *axi_bus_timeout.o(".text*" ".rodata*") + } >RAM + + .loader_ro : { + *(.text*) + *(.rodata*) + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as + * read-only, executable. No RW data from the next section must + * creep in. Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __RO_END__ = .; + __DATA_COPY_START__ = .; + } >RAM + + .data : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + + __DATA_SIZE__ = SIZEOF(.data); + + stacks (NOLOAD) : ALIGN(16) { + __STACKS_START__ = .; + KEEP(*(cr7_loader_stack)) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } >RAM + + __BSS_SIZE__ = SIZEOF(.bss); + + __CR7_END__ = .; +} diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/loader_main.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/loader_main.c new file mode 100644 index 0000000..798da63 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/loader_main.c @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file loader_main.c + * - Version : 0.01 + * @brief IP initialization. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include "rcar_def.h" +#include "bit.h" +#include "debug.h" +#include "mmio.h" +#include "cpg_init.h" +#include "cpg_register.h" +#include "pfc_init.h" +#include "scif.h" +#include "mfis_register.h" +#include "mfis.h" +#include "rcar_version.h" +#include "../ddr/boot_init_dram.h" +#include "../qos/qos_init.h" + +#include "swdt.h" +#include "arm_gic.h" +#include "cpsr_acc.h" +#include "bl_common.h" +#include "rom_api.h" +#include "auth.h" +#include "edc_init.h" +#include "axi_init.h" +#include "ths_init.h" + +/***************************************************************************** + * Definitions + *****************************************************************************/ +/* Product Register */ +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) +#define PRR_MAJOR_MASK (0x000000F0U) +#define PRR_MINOR_MASK (0x0000000FU) +#define PRR_PRODUCT_SHIFT (8U) +#define PRR_MAJOR_SHIFT (4U) +#define PRR_MINOR_SHIFT (0U) +#define PRR_MAJOR_OFFSET (1U) +#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */ + +/* R-Car Gen3 product check */ +#define TARGET_PRODUCT RCAR_PRODUCT_V3M +#define TARGET_NAME "R-Car V3M" + +/* CPG write protect registers */ +#define CPGWPR_PASSWORD (0x5A5AFFFFU) +#define CPGWPCR_PASSWORD (0xA5A50000U) + +/* RST Registers */ +#define RST_BASE (0xE6160000U) +#define RST_WDTRSTCR (RST_BASE + 0x0054U) +#define RST_CR7BAR (RST_BASE + 0x0070U) +#define RST_CR7BAR_BAREN ((uint32_t)1U << 4) +#define WDTRSTCR_PASSWORD (0xA55A0000U) +#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U) + +/* CRLoader GIC Base */ +#define GICD_BASE (0xF1110000U) +#define GICC_BASE (0xF1120000U) + +/* Processer State Register*/ +#define PSR_A (~((uint32_t)1U << 8U)) /* Abort */ +#define PSR_I (~((uint32_t)1U << 7U)) /* IRQ */ +#define PSR_F (~((uint32_t)1U << 6U)) /* FIQ */ + +/***************************************************************************** + * Unions + *****************************************************************************/ + + +/***************************************************************************** + * Structs + *****************************************************************************/ + + +/***************************************************************************** + * Globals + *****************************************************************************/ +extern const char g_build_message[]; + +/***************************************************************************** + * Macros + *****************************************************************************/ + +/***************************************************************************** + * Prototypes + *****************************************************************************/ + +uint32_t loader_main(void) +{ + + uint32_t reg; + uint32_t lcs; + char msg[128]; + const char *str; + const char *product_v3m = "V3M"; + const char *lcs_cm = "CM"; + const char *lcs_dm = "DM"; + const char *lcs_sd = "SD"; + const char *lcs_se = "SE"; + const char *lcs_fa = "FA"; + const char *unknown = "unknown"; + +/***************************************************************************** + * Disable MFIS write protection + *****************************************************************************/ + mmio_write_32(MFIS_MFISWPCNTR, MFIS_WPCNTR_PASSWORD + | MFIS_WPCNTR_WPD_BIT); + + /* MFIS initialize */ + mfis_init(); + + /* Destination ID Checker for AXI-bus */ + edc_routing_err_init(); + +#if RCAR_AXI_BUS_TIMEOUT + /* Timeout Counter Setting for AXI-bus */ + axi_bus_timeout_setting(); +#endif + +/***************************************************************************** + * Initialize Hardware + *****************************************************************************/ + cpg_init(); /* CPG initialize */ + pfc_init(); /* Pin function initialize */ + console_init(); /* SCIF initialize */ + + /* GIC initialize */ + arm_gic_init(GICC_BASE, GICD_BASE, NULL, 0); + + /* GIC setup */ + arm_gic_setup(); + + /* boot message */ + NOTICE("R-Car Gen3 Initial Program Loader(CR7) Rev.%s\n", + g_version_of_renesas); + NOTICE("%s\n", g_build_message); + + reg = mmio_read_32(PRR); + switch (reg & PRR_PRODUCT_MASK) + { + case PRR_PRODUCT_V3M: + { + str = product_v3m; + break; + } + default: + { + str = unknown; + break; + } + } + (void)sprintf(msg, "PRR is R-Car %s Ver%d.%d\n", str, + ((reg & PRR_MAJOR_MASK) >> PRR_MAJOR_SHIFT) + PRR_MAJOR_OFFSET, + (reg & PRR_MINOR_MASK)); + NOTICE("%s", msg); + if ((reg & RCAR_PRODUCT_MASK) != TARGET_PRODUCT) + { + ERROR("This IPL has been built for the %s.\n", TARGET_NAME); + ERROR("Please write the correct IPL to flash memory.\n"); + panic(); + } + + reg = ROM_GetLcs(&lcs); + if (reg == 0U) + { + switch (lcs) + { + case LCS_CM: + { + str = lcs_cm; + break; + } + case LCS_DM: + { + str = lcs_dm; + break; + } + case LCS_SD: + { + str = lcs_sd; + break; + } + case LCS_SE: + { + str = lcs_se; + break; + } + case LCS_FA: + { + str = lcs_fa; + break; + } + default: + { + str = unknown; + break; + } + } + } + else + { + str = unknown; + } + NOTICE("LCM state is %s\n", str); + + InitDram(); /* DDR initialize */ + qos_init(); /* QoS configuration */ + ths_conv(); /* THS configuration */ + + pre_read_cert_info(); + +/***************************************************************************** + * Unmask the detection of RWDT overflow + *****************************************************************************/ + reg = mmio_read_32(RST_WDTRSTCR); + reg &= ~WDTRSTCR_RWDT_RSTMSK; + reg |= WDTRSTCR_PASSWORD; + mmio_write_32(RST_WDTRSTCR, reg); + +/***************************************************************************** + * Release CPG write protect + *****************************************************************************/ + mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); + mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); + + return 0U; +} +/* End of function loader_main */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/rcar_addr.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/rcar_addr.c new file mode 100644 index 0000000..c6c102b --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/rcar_addr.c @@ -0,0 +1,456 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file rcar_addr.c + * - Version : 0.01 + * @brief 1. IP initialization. + * 2. DMA transfer the binary image from Flash to RAM. + * 3. Authentication of the transferred image. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include "bit.h" +#include "debug.h" +#include "mmio.h" +#include "rpc_driver.h" +#include "dma_driver.h" +#include "rom_api.h" +#include "auth.h" +#include "rcar_def.h" + + +/***************************************************************************** + * Definitions + *****************************************************************************/ +#define RTOS_MAX_SIZE (1024U * 1024U) +#define MAIN_LOADER_MAX_SIZE ( 170U * 1024U) +#define UBOOT_MAX_SIZE (1024U * 1024U) + +#define FLASH_BASE (0x08000000U) +#define FLASH_SIZE (0x04000000U) +#define FLASH_RTOS_CERT_ADDR (FLASH_BASE + 0x000C0000U) +#define FLASH_CA5X_CERT_ADDR (FLASH_BASE + 0x000C0800U) +#define FLASH_UBOOT_CERT_ADDR (FLASH_BASE + 0x000C1000U) + +#define FLASH_RTOS_IMAGE_ADDR (FLASH_BASE + 0x001C0000U) +#define FLASH_CA5X_IMAGE_ADDR (FLASH_BASE + 0x002C0000U) +#define FLASH_UBOOT_IMAGE_ADDR (FLASH_BASE + 0x00840000U) +#define FLASH_CERT_SIZE (0x400U) + +#define SYSRAM_BASE (0xE6300000U) +#define SYSRAM_END (0xE636FFFFU) +#define DRAM_BASE (0x40000000U) +#define DRAM_END (0xBFFFFFFFU) +/* Calculate address of certificate */ +#define SEC_BOOT_CERT_ADDR(a) (SYSRAM_BASE + (a) + 0x400U) +#define RTOS_CERT_ADDR (DRAM_BASE + 0x08220000U) +#define CA5X_CERT_ADDR (DRAM_BASE + 0x0800U) +#define UBOOT_CERT_ADDR (DRAM_BASE + 0x1000U) + +#define MAIN_CPU_NONE (0U) + +#define SMONI_IPL_PARAM_OFFSET (0x00022200U) +#define SMONI_EP_INFO_OFFSET (SMONI_IPL_PARAM_OFFSET + 0x0030U) + +/*********************** RCarGen3_MFI *************************/ +#define MFISSOFTMDR (0xE6260600U) /* SOFTMD register */ + +/*********************** RCarGen3_RST *************************/ +#define RST_MODEMR (0xE6160060U) /* Mode Monitor Register */ + +typedef uint32_t (* SECURE_BOOT_API)(uint32_t a, uint32_t b, ROM_FuncReadFlash c); + + +/***************************************************************************** + * Unions + *****************************************************************************/ + + +/***************************************************************************** + * Structs + *****************************************************************************/ +typedef struct{ + uint8_t uctype; + uint8_t ucversion; + uint16_t ussize; + uint32_t uiattr; + uint32_t psecmonimageinfo_low; + uint32_t psecmonimageinfo_high; + uint32_t psecoptepinfo_low; + uint32_t psecoptepinfo_high; + uint32_t psecoptimageinfo_low; + uint32_t psecoptimageinfo_high; + uint32_t pnonsecepinfo_low; + uint32_t pnonsecepinfo_high; + uint32_t pnonsecimageinfo_low; + uint32_t pnonsecimageinfo_high; +}st_smoni_iplparams_t; + +typedef struct{ + uint8_t uctype; + uint8_t ucversion; + uint16_t ussize; + uint32_t uiattr; + uint32_t ulpc_low; + uint32_t ulpc_high; + uint32_t ulspsr_low; + uint32_t ulspsr_high; + uint32_t ularg0_low; + uint32_t ularg0_high; + uint32_t ularg1_low; + uint32_t ularg1_high; + uint32_t ularg2_low; + uint32_t ularg2_high; + uint32_t ularg3_low; + uint32_t ularg3_high; + uint32_t ularg4_low; + uint32_t ularg4_high; + uint32_t ularg5_low; + uint32_t ularg5_high; + uint32_t ularg6_low; + uint32_t ularg6_high; + uint32_t ularg7_low; + uint32_t ularg7_high; +}st_smoni_entrypointinfo_t; + +/***************************************************************************** + * Globals + *****************************************************************************/ + + +/***************************************************************************** + * Macros + *****************************************************************************/ + + +/***************************************************************************** + * Prototypes + *****************************************************************************/ +static void check_load_area(uint32_t dst, uint32_t src, uint32_t len); +static void smoni_set_param(uint32_t smoni_entry_point); + +uint32_t rcar_addr(uint32_t *main_cpu_addr) +{ +#if (RCAR_KICK_MAIN_CPU != MAIN_CPU_NONE) + uint32_t ca5x_load_addr; + uint32_t uboot_load_addr; +#endif /* RCAR_KICK_MAIN_CPU */ + uint32_t rtos_load_addr; + uint32_t boot_cert_addr; + uint32_t ipl_cert_addr; + uint32_t size; + uint32_t ret; + SECURE_BOOT_API sbrom_SecureBootAPI; + +/***************************************************************************** + * Initialize Hardware + *****************************************************************************/ + init_rpc(); /* Initialize RPC */ + init_dma(); /* Initialize DMA */ + +/***************************************************************************** + * LCS judgement for secure boot + *****************************************************************************/ +#if RCAR_SECURE_BOOT == 1 +{ + uint32_t lcs; + uint32_t md = (mmio_read_32(RST_MODEMR) & 0x00000020U) >> 5U; + uint32_t softmd = (mmio_read_32(MFISSOFTMDR) & 0x00000001U); + + /* Get LCS */ + ret = ROM_GetLcs(&lcs); + if(ret != 0U) + { /* error check */ + ERROR("CR7: Failed to get the LCS. (%d)\n", ret); + panic(); + } + + if (lcs == LCS_SE) + { /* LCS=Secure */ + if (softmd == 0x1U) + { /* LCS=Secure + Normal boot (temp setting) */ + sbrom_SecureBootAPI = NULL; + } + else + { /* else is LCS=Secure + Secure boot */ + sbrom_SecureBootAPI = (SECURE_BOOT_API)ROM_SecureBootAPI; + } + } + else if (lcs == LCS_SD) + { + /* LCS=SD */ + sbrom_SecureBootAPI = NULL; + } + else if (md == 0U) + { /* MD5=0 => LCS=CM/DM/RMA + Secure boot */ + sbrom_SecureBootAPI = (SECURE_BOOT_API)ROM_SecureBootAPI; + } + else + { + sbrom_SecureBootAPI = NULL; /* MD5=1 => LCS=CM/DM/SD/RMA + Normal boot */ + } +} +#else /* RCAR_SECURE_BOOT == 1 */ + sbrom_SecureBootAPI = NULL; +#endif /* RCAR_SECURE_BOOT == 1 */ + + if (sbrom_SecureBootAPI != NULL) + { + NOTICE("Secure boot(CR7)\n"); + } + else + { + NOTICE("Normal boot(CR7)\n"); + } + +/***************************************************************************** + * Reload certificate from HyperFlash + *****************************************************************************/ + get_cert_info(&boot_cert_addr, &size, &ipl_cert_addr); + +/***************************************************************************** + * Load CR7 RTOS certificate from HyperFlash + *****************************************************************************/ + exec_dma(RTOS_CERT_ADDR, FLASH_RTOS_CERT_ADDR, FLASH_CERT_SIZE); + +/***************************************************************************** + * Load RTOS from HyperFlash + *****************************************************************************/ + get_info_from_cert(RTOS_CERT_ADDR, &size, &rtos_load_addr); + + if (size == 0U) + { + ERROR("RTOS image size error\n"); + panic(); + } + else if (size > RTOS_MAX_SIZE) + { + ERROR("RTOS image size error\n"); + panic(); + } + else + { + /* No else processing QAC compliant */ + } + + check_load_area(rtos_load_addr, FLASH_RTOS_IMAGE_ADDR, size); + + NOTICE("RTOS load address=0x%x RTOS image size=0x%x\n", rtos_load_addr, size); + exec_dma(rtos_load_addr, FLASH_RTOS_IMAGE_ADDR, size); + +/***************************************************************************** + * CR7 RTOS authentication + *****************************************************************************/ + if (sbrom_SecureBootAPI != NULL) + { + ret = sbrom_SecureBootAPI(SEC_BOOT_CERT_ADDR(boot_cert_addr), + RTOS_CERT_ADDR, 0U); + if (ret != 0U) + { + ERROR("RTOS image Verification Failed!!!(0x%x)\n", ret); + panic(); + } + } + +#if (RCAR_KICK_MAIN_CPU != MAIN_CPU_NONE) +/***************************************************************************** + * Load BL31 certificate from HyperFlash + *****************************************************************************/ + exec_dma(CA5X_CERT_ADDR, FLASH_CA5X_CERT_ADDR, FLASH_CERT_SIZE); + +/***************************************************************************** + * Load BL31 from HyperFlash + *****************************************************************************/ + get_info_from_cert(CA5X_CERT_ADDR, &size, &ca5x_load_addr); + + if (size == 0U) + { + ERROR("BL31 image size error\n"); + panic(); + } + else if (size > MAIN_LOADER_MAX_SIZE) + { + ERROR("BL31 image size error\n"); + panic(); + } + else + { + /* No else processing QAC compliant */ + } + + check_load_area(ca5x_load_addr, FLASH_CA5X_IMAGE_ADDR, size); + + NOTICE("BL31 load address=0x%x BL31 image size=0x%x\n", ca5x_load_addr, size); + exec_dma(ca5x_load_addr, FLASH_CA5X_IMAGE_ADDR, size); + *main_cpu_addr = ca5x_load_addr; + +/***************************************************************************** + * BL31 authentication + *****************************************************************************/ + if (sbrom_SecureBootAPI != NULL) + { + ret = sbrom_SecureBootAPI(SEC_BOOT_CERT_ADDR(boot_cert_addr) + ,CA5X_CERT_ADDR, 0); + if (ret != 0U) + { + ERROR("BL31 image Verification Failed!!!(0x%x)\n", ret); + panic(); + } + } + +/***************************************************************************** + * Load U-Boot Loader certificate from HyperFlash + *****************************************************************************/ + exec_dma(UBOOT_CERT_ADDR, FLASH_UBOOT_CERT_ADDR, FLASH_CERT_SIZE); + +/***************************************************************************** + * Load U-Boot from HyperFlash + *****************************************************************************/ + get_info_from_cert(UBOOT_CERT_ADDR, &size, &uboot_load_addr); + + if (size == 0U) + { + ERROR("U-Boot image size error\n"); + panic(); + } + else if (size > UBOOT_MAX_SIZE) + { + ERROR("U-Boot image size error\n"); + panic(); + } + else + { + /* No else processing QAC compliant */ + } + + check_load_area(uboot_load_addr, FLASH_UBOOT_IMAGE_ADDR, size); + + NOTICE("U-Boot load address=0x%x U-Boot image size=0x%x\n", uboot_load_addr, size); + exec_dma(uboot_load_addr, FLASH_UBOOT_IMAGE_ADDR, size); + +/***************************************************************************** + * U-Boot Loader authentication + *****************************************************************************/ + if (sbrom_SecureBootAPI != NULL) + { + ret = sbrom_SecureBootAPI(SEC_BOOT_CERT_ADDR(boot_cert_addr) + ,UBOOT_CERT_ADDR, 0); + if (ret != 0U) + { + ERROR("U-Boot image Verification Failed!!!(0x%x)\n", ret); + panic(); + } + } + +/***************************************************************************** + * store the Secure monitor parameter to SDRAM. + *****************************************************************************/ + smoni_set_param(ca5x_load_addr); +#endif /* (RCAR_KICK_MAIN_CPU != MAIN_CPU_NONE) */ + return rtos_load_addr; +} +/* End of function rcar_addr */ + +static void check_load_area(uint32_t dst, uint32_t src, uint32_t len) +{ + /* check source range */ + if((src < FLASH_BASE) || ((FLASH_BASE + FLASH_SIZE -1) < (src + len))) + { + ERROR("CR7: check load area (source address)\n"); + panic(); + } + + /* check destination range */ + if((dst < DRAM_BASE) || (DRAM_END < (dst + len))) + { + ERROR("CR7: check_load_area (destination address)\n"); + panic(); + } +} +/* End of function check_load_area */ + +static void smoni_set_param(uint32_t smoni_entry_point) +{ +#if CA53_PROG1_IS_SMONI + st_smoni_iplparams_t *smoni_ipl_param; + st_smoni_entrypointinfo_t *smoni_ep_info; + + /* set struct address */ + smoni_ipl_param = (st_smoni_iplparams_t *) + (smoni_entry_point + SMONI_IPL_PARAM_OFFSET); + smoni_ep_info = (st_smoni_entrypointinfo_t *) + (smoni_entry_point + SMONI_EP_INFO_OFFSET); + + /* set parameter */ + smoni_ipl_param->uctype = 0x03U; + smoni_ipl_param->ucversion = 0x01U; + smoni_ipl_param->ussize = 0x0030U; + smoni_ipl_param->uiattr = 0x00000000U; + smoni_ipl_param->psecmonimageinfo_low = 0x00000000U; + smoni_ipl_param->psecmonimageinfo_high = 0x00000000U; + smoni_ipl_param->psecoptepinfo_low = 0x00000000U; + smoni_ipl_param->psecoptepinfo_high = 0x00000000U; + smoni_ipl_param->psecoptimageinfo_low = 0x00000000U; + smoni_ipl_param->psecoptimageinfo_high = 0x00000000U; + smoni_ipl_param->pnonsecepinfo_low = (uintptr_t)smoni_ep_info; + smoni_ipl_param->pnonsecepinfo_high = 0x00000000U; + smoni_ipl_param->pnonsecimageinfo_low = 0x00000000U; + smoni_ipl_param->pnonsecimageinfo_high = 0x00000000U; + + smoni_ep_info->uctype = 0x01U; + smoni_ep_info->ucversion = 0x01U; + smoni_ep_info->ussize = 0x0058U; + smoni_ep_info->uiattr = (uint32_t)CA53_PROG2_ATTR; + smoni_ep_info->ulpc_low = + (uint32_t)((uint64_t)CA53_PROG2_PC & 0xFFFFFFFFU); + smoni_ep_info->ulpc_high = + (uint32_t)(((uint64_t)CA53_PROG2_PC >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ulspsr_low = + (uint32_t)((uint64_t)CA53_PROG2_SPSR & 0xFFFFFFFFU); + smoni_ep_info->ulspsr_high = + (uint32_t)(((uint64_t)CA53_PROG2_SPSR >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg0_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG0 & 0xFFFFFFFFU); + smoni_ep_info->ularg0_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG0 >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg1_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG1 & 0xFFFFFFFFU); + smoni_ep_info->ularg1_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG1 >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg2_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG2 & 0xFFFFFFFFU); + smoni_ep_info->ularg2_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG2 >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg3_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG3 & 0xFFFFFFFFU); + smoni_ep_info->ularg3_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG3 >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg4_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG4 & 0xFFFFFFFFU); + smoni_ep_info->ularg4_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG4 >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg5_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG5 & 0xFFFFFFFFU); + smoni_ep_info->ularg5_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG5 >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg6_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG6 & 0xFFFFFFFFU); + smoni_ep_info->ularg6_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG6 >> 32U) & 0xFFFFFFFFU); + smoni_ep_info->ularg7_low = + (uint32_t)((uint64_t)CA53_PROG2_ARG7 & 0xFFFFFFFFU); + smoni_ep_info->ularg7_high = + (uint32_t)(((uint64_t)CA53_PROG2_ARG7 >> 32U) & 0xFFFFFFFFU); +#endif /* CA53_PROG1_IS_SMONI */ +} +/* End of function smoni_set_param */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/rcar_version.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/rcar_version.c new file mode 100644 index 0000000..93eb210 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/rcar_version.c @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/****************************************************************************** + * @file rcar_version.c + * - Version : 0.1 + * @brief IPL version string. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include "rcar_version.h" + +const uint8_t g_version_of_renesas[VER_SIZE] __attribute__((__section__(".version"))) = VERSION_OF_RENESAS; + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/stack.s b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/stack.s new file mode 100644 index 0000000..0ff4cf9 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/loader/stack.s @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + + + .section cr7_loader_stack, "aw", %nobits + .align 5 +stacks: + .space (8*1024), 0 + + .end diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/pfc/V3M/pfc_init_v3m.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/pfc/V3M/pfc_init_v3m.c new file mode 100644 index 0000000..93d93ec --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/pfc/V3M/pfc_init_v3m.c @@ -0,0 +1,1000 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file pfc_init_v3m.c + * - Version : 0.01 + * @brief PFC driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include /* for uint32_t */ +#include +#include "cpg_init.h" +#include "pfc_init_v3m.h" +#include "rcar_def.h" + +#define RST_MODEMR 0xE6160060 + +/* GPIO base address */ +#define GPIO_BASE (0xE6050000U) + +/* GPIO registers */ +#define GPIO_IOINTSEL0 (GPIO_BASE + 0x0000U) +#define GPIO_INOUTSEL0 (GPIO_BASE + 0x0004U) +#define GPIO_OUTDT0 (GPIO_BASE + 0x0008U) +#define GPIO_INDT0 (GPIO_BASE + 0x000CU) +#define GPIO_INTDT0 (GPIO_BASE + 0x0010U) +#define GPIO_INTCLR0 (GPIO_BASE + 0x0014U) +#define GPIO_INTMSK0 (GPIO_BASE + 0x0018U) +#define GPIO_MSKCLR0 (GPIO_BASE + 0x001CU) +#define GPIO_POSNEG0 (GPIO_BASE + 0x0020U) +#define GPIO_EDGLEVEL0 (GPIO_BASE + 0x0024U) +#define GPIO_FILONOFF0 (GPIO_BASE + 0x0028U) +#define GPIO_INTMSKS0 (GPIO_BASE + 0x0038U) +#define GPIO_MSKCLRS0 (GPIO_BASE + 0x003CU) +#define GPIO_OUTDTSEL0 (GPIO_BASE + 0x0040U) +#define GPIO_OUTDTH0 (GPIO_BASE + 0x0044U) +#define GPIO_OUTDTL0 (GPIO_BASE + 0x0048U) +#define GPIO_BOTHEDGE0 (GPIO_BASE + 0x004CU) +#define GPIO_IOINTSEL1 (GPIO_BASE + 0x1000U) +#define GPIO_INOUTSEL1 (GPIO_BASE + 0x1004U) +#define GPIO_OUTDT1 (GPIO_BASE + 0x1008U) +#define GPIO_INDT1 (GPIO_BASE + 0x100CU) +#define GPIO_INTDT1 (GPIO_BASE + 0x1010U) +#define GPIO_INTCLR1 (GPIO_BASE + 0x1014U) +#define GPIO_INTMSK1 (GPIO_BASE + 0x1018U) +#define GPIO_MSKCLR1 (GPIO_BASE + 0x101CU) +#define GPIO_POSNEG1 (GPIO_BASE + 0x1020U) +#define GPIO_EDGLEVEL1 (GPIO_BASE + 0x1024U) +#define GPIO_FILONOFF1 (GPIO_BASE + 0x1028U) +#define GPIO_INTMSKS1 (GPIO_BASE + 0x1038U) +#define GPIO_MSKCLRS1 (GPIO_BASE + 0x103CU) +#define GPIO_OUTDTSEL1 (GPIO_BASE + 0x1040U) +#define GPIO_OUTDTH1 (GPIO_BASE + 0x1044U) +#define GPIO_OUTDTL1 (GPIO_BASE + 0x1048U) +#define GPIO_BOTHEDGE1 (GPIO_BASE + 0x104CU) +#define GPIO_IOINTSEL2 (GPIO_BASE + 0x2000U) +#define GPIO_INOUTSEL2 (GPIO_BASE + 0x2004U) +#define GPIO_OUTDT2 (GPIO_BASE + 0x2008U) +#define GPIO_INDT2 (GPIO_BASE + 0x200CU) +#define GPIO_INTDT2 (GPIO_BASE + 0x2010U) +#define GPIO_INTCLR2 (GPIO_BASE + 0x2014U) +#define GPIO_INTMSK2 (GPIO_BASE + 0x2018U) +#define GPIO_MSKCLR2 (GPIO_BASE + 0x201CU) +#define GPIO_POSNEG2 (GPIO_BASE + 0x2020U) +#define GPIO_EDGLEVEL2 (GPIO_BASE + 0x2024U) +#define GPIO_FILONOFF2 (GPIO_BASE + 0x2028U) +#define GPIO_INTMSKS2 (GPIO_BASE + 0x2038U) +#define GPIO_MSKCLRS2 (GPIO_BASE + 0x203CU) +#define GPIO_OUTDTSEL2 (GPIO_BASE + 0x2040U) +#define GPIO_OUTDTH2 (GPIO_BASE + 0x2044U) +#define GPIO_OUTDTL2 (GPIO_BASE + 0x2048U) +#define GPIO_BOTHEDGE2 (GPIO_BASE + 0x204CU) +#define GPIO_IOINTSEL3 (GPIO_BASE + 0x3000U) +#define GPIO_INOUTSEL3 (GPIO_BASE + 0x3004U) +#define GPIO_OUTDT3 (GPIO_BASE + 0x3008U) +#define GPIO_INDT3 (GPIO_BASE + 0x300CU) +#define GPIO_INTDT3 (GPIO_BASE + 0x3010U) +#define GPIO_INTCLR3 (GPIO_BASE + 0x3014U) +#define GPIO_INTMSK3 (GPIO_BASE + 0x3018U) +#define GPIO_MSKCLR3 (GPIO_BASE + 0x301CU) +#define GPIO_POSNEG3 (GPIO_BASE + 0x3020U) +#define GPIO_EDGLEVEL3 (GPIO_BASE + 0x3024U) +#define GPIO_FILONOFF3 (GPIO_BASE + 0x3028U) +#define GPIO_INTMSKS3 (GPIO_BASE + 0x3038U) +#define GPIO_MSKCLRS3 (GPIO_BASE + 0x303CU) +#define GPIO_OUTDTSEL3 (GPIO_BASE + 0x3040U) +#define GPIO_OUTDTH3 (GPIO_BASE + 0x3044U) +#define GPIO_OUTDTL3 (GPIO_BASE + 0x3048U) +#define GPIO_BOTHEDGE3 (GPIO_BASE + 0x304CU) +#define GPIO_IOINTSEL4 (GPIO_BASE + 0x4000U) +#define GPIO_INOUTSEL4 (GPIO_BASE + 0x4004U) +#define GPIO_OUTDT4 (GPIO_BASE + 0x4008U) +#define GPIO_INDT4 (GPIO_BASE + 0x400CU) +#define GPIO_INTDT4 (GPIO_BASE + 0x4010U) +#define GPIO_INTCLR4 (GPIO_BASE + 0x4014U) +#define GPIO_INTMSK4 (GPIO_BASE + 0x4018U) +#define GPIO_MSKCLR4 (GPIO_BASE + 0x401CU) +#define GPIO_POSNEG4 (GPIO_BASE + 0x4020U) +#define GPIO_EDGLEVEL4 (GPIO_BASE + 0x4024U) +#define GPIO_FILONOFF4 (GPIO_BASE + 0x4028U) +#define GPIO_INTMSKS4 (GPIO_BASE + 0x4038U) +#define GPIO_MSKCLRS4 (GPIO_BASE + 0x403CU) +#define GPIO_OUTDTSEL4 (GPIO_BASE + 0x4040U) +#define GPIO_OUTDTH4 (GPIO_BASE + 0x4044U) +#define GPIO_OUTDTL4 (GPIO_BASE + 0x4048U) +#define GPIO_BOTHEDGE4 (GPIO_BASE + 0x404CU) +#define GPIO_IOINTSEL5 (GPIO_BASE + 0x5000U) +#define GPIO_INOUTSEL5 (GPIO_BASE + 0x5004U) +#define GPIO_OUTDT5 (GPIO_BASE + 0x5008U) +#define GPIO_INDT5 (GPIO_BASE + 0x500CU) +#define GPIO_INTDT5 (GPIO_BASE + 0x5010U) +#define GPIO_INTCLR5 (GPIO_BASE + 0x5014U) +#define GPIO_INTMSK5 (GPIO_BASE + 0x5018U) +#define GPIO_MSKCLR5 (GPIO_BASE + 0x501CU) +#define GPIO_POSNEG5 (GPIO_BASE + 0x5020U) +#define GPIO_EDGLEVEL5 (GPIO_BASE + 0x5024U) +#define GPIO_FILONOFF5 (GPIO_BASE + 0x5028U) +#define GPIO_INTMSKS5 (GPIO_BASE + 0x5038U) +#define GPIO_MSKCLRS5 (GPIO_BASE + 0x503CU) +#define GPIO_OUTDTSEL5 (GPIO_BASE + 0x5040U) +#define GPIO_OUTDTH5 (GPIO_BASE + 0x5044U) +#define GPIO_OUTDTL5 (GPIO_BASE + 0x5048U) +#define GPIO_BOTHEDGE5 (GPIO_BASE + 0x504CU) + +/* Pin functon base address */ +#define PFC_BASE (0xE6060000U) + +/* Pin functon registers */ +#define PFC_PMMR (PFC_BASE + 0x0000U) +#define PFC_GPSR0 (PFC_BASE + 0x0100U) +#define PFC_GPSR1 (PFC_BASE + 0x0104U) +#define PFC_GPSR2 (PFC_BASE + 0x0108U) +#define PFC_GPSR3 (PFC_BASE + 0x010CU) +#define PFC_GPSR4 (PFC_BASE + 0x0110U) +#define PFC_GPSR5 (PFC_BASE + 0x0114U) +#define PFC_IPSR0 (PFC_BASE + 0x0200U) +#define PFC_IPSR1 (PFC_BASE + 0x0204U) +#define PFC_IPSR2 (PFC_BASE + 0x0208U) +#define PFC_IPSR3 (PFC_BASE + 0x020CU) +#define PFC_IPSR4 (PFC_BASE + 0x0210U) +#define PFC_IPSR5 (PFC_BASE + 0x0214U) +#define PFC_IPSR6 (PFC_BASE + 0x0218U) +#define PFC_IPSR7 (PFC_BASE + 0x021CU) +#define PFC_IPSR8 (PFC_BASE + 0x0220U) +#define PFC_IOCTRL30 (PFC_BASE + 0x0380U) +#define PFC_IOCTRL31 (PFC_BASE + 0x0384U) +#define PFC_IOCTRL32 (PFC_BASE + 0x0388U) +#define PFC_IOCTRL40 (PFC_BASE + 0x03C0U) +#define PFC_PUEN0 (PFC_BASE + 0x0400U) +#define PFC_PUEN1 (PFC_BASE + 0x0404U) +#define PFC_PUEN2 (PFC_BASE + 0x0408U) +#define PFC_PUEN3 (PFC_BASE + 0x040CU) +#define PFC_PUD0 (PFC_BASE + 0x0440U) +#define PFC_PUD1 (PFC_BASE + 0x0444U) +#define PFC_PUD2 (PFC_BASE + 0x0448U) +#define PFC_PUD3 (PFC_BASE + 0x044CU) +#define PFC_MOD_SEL0 (PFC_BASE + 0x0500U) + +/* Pin functon bit */ +#define GPSR0_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) +#define GPSR0_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) +#define GPSR0_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) +#define GPSR0_DU_DOTCLKOUT ((uint32_t)1U << 18U) +#define GPSR0_DU_DB7 ((uint32_t)1U << 17U) +#define GPSR0_DU_DB6 ((uint32_t)1U << 16U) +#define GPSR0_DU_DB5 ((uint32_t)1U << 15U) +#define GPSR0_DU_DB4 ((uint32_t)1U << 14U) +#define GPSR0_DU_DB3 ((uint32_t)1U << 13U) +#define GPSR0_DU_DB2 ((uint32_t)1U << 12U) +#define GPSR0_DU_DG7 ((uint32_t)1U << 11U) +#define GPSR0_DU_DG6 ((uint32_t)1U << 10U) +#define GPSR0_DU_DG5 ((uint32_t)1U << 9U) +#define GPSR0_DU_DG4 ((uint32_t)1U << 8U) +#define GPSR0_DU_DG3 ((uint32_t)1U << 7U) +#define GPSR0_DU_DG2 ((uint32_t)1U << 6U) +#define GPSR0_DU_DR7 ((uint32_t)1U << 5U) +#define GPSR0_DU_DR6 ((uint32_t)1U << 4U) +#define GPSR0_DU_DR5 ((uint32_t)1U << 3U) +#define GPSR0_DU_DR4 ((uint32_t)1U << 2U) +#define GPSR0_DU_DR3 ((uint32_t)1U << 1U) +#define GPSR0_DU_DR2 ((uint32_t)1U << 0U) + +#define GPSR1_DIGRF_CLKOUT ((uint32_t)1U << 27U) +#define GPSR1_DIGRF_CLKIN ((uint32_t)1U << 26U) +#define GPSR1_CANFD_CLK ((uint32_t)1U << 25U) +#define GPSR1_CANFD1_RX ((uint32_t)1U << 24U) +#define GPSR1_CANFD1_TX ((uint32_t)1U << 23U) +#define GPSR1_CANFD0_RX ((uint32_t)1U << 22U) +#define GPSR1_CANFD0_TX ((uint32_t)1U << 21U) +#define GPSR1_AVB0_AVTP_CAPTURE ((uint32_t)1U << 20U) +#define GPSR1_AVB0_AVTP_MATCH ((uint32_t)1U << 19U) +#define GPSR1_AVB0_LINK ((uint32_t)1U << 18U) +#define GPSR1_AVB0_PHY_INT ((uint32_t)1U << 17U) +#define GPSR1_AVB0_MAGIC ((uint32_t)1U << 16U) +#define GPSR1_AVB0_MDC ((uint32_t)1U << 15U) +#define GPSR1_AVB0_MDIO ((uint32_t)1U << 14U) +#define GPSR1_AVB0_TXCREFCLK ((uint32_t)1U << 13U) +#define GPSR1_AVB0_TD3 ((uint32_t)1U << 12U) +#define GPSR1_AVB0_TD2 ((uint32_t)1U << 11U) +#define GPSR1_AVB0_TD1 ((uint32_t)1U << 10U) +#define GPSR1_AVB0_TD0 ((uint32_t)1U << 9U) +#define GPSR1_AVB0_TXC ((uint32_t)1U << 8U) +#define GPSR1_AVB0_TX_CTL ((uint32_t)1U << 7U) +#define GPSR1_AVB0_RD3 ((uint32_t)1U << 6U) +#define GPSR1_AVB0_RD2 ((uint32_t)1U << 5U) +#define GPSR1_AVB0_RD1 ((uint32_t)1U << 4U) +#define GPSR1_AVB0_RD0 ((uint32_t)1U << 3U) +#define GPSR1_AVB0_RXC ((uint32_t)1U << 2U) +#define GPSR1_AVB0_RX_CTL ((uint32_t)1U << 1U) +#define GPSR1_IRQ0 ((uint32_t)1U << 0U) + +#define GPSR2_VI0_FIELD ((uint32_t)1U << 16U) +#define GPSR2_VI0_DATA11 ((uint32_t)1U << 15U) +#define GPSR2_VI0_DATA10 ((uint32_t)1U << 14U) +#define GPSR2_VI0_DATA9 ((uint32_t)1U << 13U) +#define GPSR2_VI0_DATA8 ((uint32_t)1U << 12U) +#define GPSR2_VI0_DATA7 ((uint32_t)1U << 11U) +#define GPSR2_VI0_DATA6 ((uint32_t)1U << 10U) +#define GPSR2_VI0_DATA5 ((uint32_t)1U << 9U) +#define GPSR2_VI0_DATA4 ((uint32_t)1U << 8U) +#define GPSR2_VI0_DATA3 ((uint32_t)1U << 7U) +#define GPSR2_VI0_DATA2 ((uint32_t)1U << 6U) +#define GPSR2_VI0_DATA1 ((uint32_t)1U << 5U) +#define GPSR2_VI0_DATA0 ((uint32_t)1U << 4U) +#define GPSR2_VI0_VSYNC_N ((uint32_t)1U << 3U) +#define GPSR2_VI0_HSYNC_N ((uint32_t)1U << 2U) +#define GPSR2_VI0_CLKENB ((uint32_t)1U << 1U) +#define GPSR2_VI0_CLK ((uint32_t)1U << 0U) + +#define GPSR3_VI1_FIELD ((uint32_t)1U << 16U) +#define GPSR3_VI1_DATA11 ((uint32_t)1U << 15U) +#define GPSR3_VI1_DATA10 ((uint32_t)1U << 14U) +#define GPSR3_VI1_DATA9 ((uint32_t)1U << 13U) +#define GPSR3_VI1_DATA8 ((uint32_t)1U << 12U) +#define GPSR3_VI1_DATA7 ((uint32_t)1U << 11U) +#define GPSR3_VI1_DATA6 ((uint32_t)1U << 10U) +#define GPSR3_VI1_DATA5 ((uint32_t)1U << 9U) +#define GPSR3_VI1_DATA4 ((uint32_t)1U << 8U) +#define GPSR3_VI1_DATA3 ((uint32_t)1U << 7U) +#define GPSR3_VI1_DATA2 ((uint32_t)1U << 6U) +#define GPSR3_VI1_DATA1 ((uint32_t)1U << 5U) +#define GPSR3_VI1_DATA0 ((uint32_t)1U << 4U) +#define GPSR3_VI1_VSYNC_N ((uint32_t)1U << 3U) +#define GPSR3_VI1_HSYNC_N ((uint32_t)1U << 2U) +#define GPSR3_VI1_CLKENB ((uint32_t)1U << 1U) +#define GPSR3_VI1_CLK ((uint32_t)1U << 0U) + +#define GPSR4_SDA2 ((uint32_t)1U << 5U) +#define GPSR4_SCL2 ((uint32_t)1U << 4U) +#define GPSR4_SDA1 ((uint32_t)1U << 3U) +#define GPSR4_SCL1 ((uint32_t)1U << 2U) +#define GPSR4_SDA0 ((uint32_t)1U << 1U) +#define GPSR4_SCL0 ((uint32_t)1U << 0U) + +#define GPSR5_RPC_INT_N ((uint32_t)1U << 14U) +#define GPSR5_RPC_WP_N ((uint32_t)1U << 13U) +#define GPSR5_RPC_RESET_N ((uint32_t)1U << 12U) +#define GPSR5_QSPI1_SSL ((uint32_t)1U << 11U) +#define GPSR5_QSPI1_IO3 ((uint32_t)1U << 10U) +#define GPSR5_QSPI1_IO2 ((uint32_t)1U << 9U) +#define GPSR5_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) +#define GPSR5_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) +#define GPSR5_QSPI1_SPCLK ((uint32_t)1U << 6U) +#define GPSR5_QSPI0_SSL ((uint32_t)1U << 5U) +#define GPSR5_QSPI0_IO3 ((uint32_t)1U << 4U) +#define GPSR5_QSPI0_IO2 ((uint32_t)1U << 3U) +#define GPSR5_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) +#define GPSR5_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) +#define GPSR5_QSPI0_SPCLK ((uint32_t)1U << 0U) + +/* Macro to calculate the set value of IPSR.(for bit31:28) */ +#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) +/* Macro to calculate the set value of IPSR.(for bit27:24) */ +#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) +/* Macro to calculate the set value of IPSR.(for bit23:20) */ +#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) +/* Macro to calculate the set value of IPSR.(for bit19:16) */ +#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) +/* Macro to calculate the set value of IPSR.(for bit15:12) */ +#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) +/* Macro to calculate the set value of IPSR.(for bit11:8) */ +#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) +/* Macro to calculate the set value of IPSR.(for bit7:4) */ +#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) +/* Macro to calculate the set value of IPSR.(for bit3:0) */ +#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) + +#define IOCTRL30_POC_VI0_DATA5 ((uint32_t)1U << 31U) +#define IOCTRL30_POC_VI0_DATA4 ((uint32_t)1U << 30U) +#define IOCTRL30_POC_VI0_DATA3 ((uint32_t)1U << 29U) +#define IOCTRL30_POC_VI0_DATA2 ((uint32_t)1U << 28U) +#define IOCTRL30_POC_VI0_DATA1 ((uint32_t)1U << 27U) +#define IOCTRL30_POC_VI0_DATA0 ((uint32_t)1U << 26U) +#define IOCTRL30_POC_VI0_VSYNC_N ((uint32_t)1U << 25U) +#define IOCTRL30_POC_VI0_HSYNC_N ((uint32_t)1U << 24U) +#define IOCTRL30_POC_VI0_CLKENB ((uint32_t)1U << 23U) +#define IOCTRL30_POC_VI0_CLK ((uint32_t)1U << 22U) +#define IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) +#define IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) +#define IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) +#define IOCTRL30_POC_DU_DOTCLKOUT ((uint32_t)1U << 18U) +#define IOCTRL30_POC_DU_DB7 ((uint32_t)1U << 17U) +#define IOCTRL30_POC_DU_DB6 ((uint32_t)1U << 16U) +#define IOCTRL30_POC_DU_DB5 ((uint32_t)1U << 15U) +#define IOCTRL30_POC_DU_DB4 ((uint32_t)1U << 14U) +#define IOCTRL30_POC_DU_DB3 ((uint32_t)1U << 13U) +#define IOCTRL30_POC_DU_DB2 ((uint32_t)1U << 12U) +#define IOCTRL30_POC_DU_DG7 ((uint32_t)1U << 11U) +#define IOCTRL30_POC_DU_DG6 ((uint32_t)1U << 10U) +#define IOCTRL30_POC_DU_DG5 ((uint32_t)1U << 9U) +#define IOCTRL30_POC_DU_DG4 ((uint32_t)1U << 8U) +#define IOCTRL30_POC_DU_DG3 ((uint32_t)1U << 7U) +#define IOCTRL30_POC_DU_DG2 ((uint32_t)1U << 6U) +#define IOCTRL30_POC_DU_DR7 ((uint32_t)1U << 5U) +#define IOCTRL30_POC_DU_DR6 ((uint32_t)1U << 4U) +#define IOCTRL30_POC_DU_DR5 ((uint32_t)1U << 3U) +#define IOCTRL30_POC_DU_DR4 ((uint32_t)1U << 2U) +#define IOCTRL30_POC_DU_DR3 ((uint32_t)1U << 1U) +#define IOCTRL30_POC_DU_DR2 ((uint32_t)1U << 0U) + +#define IOCTRL31_POC_DUMMY_31 ((uint32_t)1U << 31U) +#define IOCTRL31_POC_DUMMY_30 ((uint32_t)1U << 30U) +#define IOCTRL31_POC_DUMMY_29 ((uint32_t)1U << 29U) +#define IOCTRL31_POC_DUMMY_28 ((uint32_t)1U << 28U) +#define IOCTRL31_POC_DUMMY_27 ((uint32_t)1U << 27U) +#define IOCTRL31_POC_DUMMY_26 ((uint32_t)1U << 26U) +#define IOCTRL31_POC_DUMMY_25 ((uint32_t)1U << 25U) +#define IOCTRL31_POC_DUMMY_24 ((uint32_t)1U << 24U) +#define IOCTRL31_POC_VI1_FIELD ((uint32_t)1U << 23U) +#define IOCTRL31_POC_VI1_DATA11 ((uint32_t)1U << 22U) +#define IOCTRL31_POC_VI1_DATA10 ((uint32_t)1U << 21U) +#define IOCTRL31_POC_VI1_DATA9 ((uint32_t)1U << 20U) +#define IOCTRL31_POC_VI1_DATA8 ((uint32_t)1U << 19U) +#define IOCTRL31_POC_VI1_DATA7 ((uint32_t)1U << 18U) +#define IOCTRL31_POC_VI1_DATA6 ((uint32_t)1U << 17U) +#define IOCTRL31_POC_VI1_DATA5 ((uint32_t)1U << 16U) +#define IOCTRL31_POC_VI1_DATA4 ((uint32_t)1U << 15U) +#define IOCTRL31_POC_VI1_DATA3 ((uint32_t)1U << 14U) +#define IOCTRL31_POC_VI1_DATA2 ((uint32_t)1U << 13U) +#define IOCTRL31_POC_VI1_DATA1 ((uint32_t)1U << 12U) +#define IOCTRL31_POC_VI1_DATA0 ((uint32_t)1U << 11U) +#define IOCTRL31_POC_VI1_VSYNC_N ((uint32_t)1U << 10U) +#define IOCTRL31_POC_VI1_HSYNC_N ((uint32_t)1U << 9U) +#define IOCTRL31_POC_VI1_CLKENB ((uint32_t)1U << 8U) +#define IOCTRL31_POC_VI1_CLK ((uint32_t)1U << 7U) +#define IOCTRL31_POC_VI0_FIELD ((uint32_t)1U << 6U) +#define IOCTRL31_POC_VI0_DATA11 ((uint32_t)1U << 5U) +#define IOCTRL31_POC_VI0_DATA10 ((uint32_t)1U << 4U) +#define IOCTRL31_POC_VI0_DATA9 ((uint32_t)1U << 3U) +#define IOCTRL31_POC_VI0_DATA8 ((uint32_t)1U << 2U) +#define IOCTRL31_POC_VI0_DATA7 ((uint32_t)1U << 1U) +#define IOCTRL31_POC_VI0_DATA6 ((uint32_t)1U << 0U) +#define IOCTRL32_POC2_VREF ((uint32_t)1U << 0U) +#define IOCTRL40_SD0TDSEL1 ((uint32_t)1U << 1U) +#define IOCTRL40_SD0TDSEL0 ((uint32_t)1U << 0U) + +#define PUEN0_PUEN_VI0_CLK ((uint32_t)1U << 31U) +#define PUEN0_PUEN_TDI ((uint32_t)1U << 30U) +#define PUEN0_PUEN_TMS ((uint32_t)1U << 29U) +#define PUEN0_PUEN_TCK ((uint32_t)1U << 28U) +#define PUEN0_PUEN_TRST_N ((uint32_t)1U << 27U) +#define PUEN0_PUEN_IRQ0 ((uint32_t)1U << 26U) +#define PUEN0_PUEN_FSCLKST_N ((uint32_t)1U << 25U) +#define PUEN0_PUEN_EXTALR ((uint32_t)1U << 24U) +#define PUEN0_PUEN_PRESETOUT_N ((uint32_t)1U << 23U) +#define PUEN0_PUEN_DU_DOTCLKIN ((uint32_t)1U << 22U) +#define PUEN0_PUEN_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) +#define PUEN0_PUEN_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) +#define PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) +#define PUEN0_PUEN_DU_DOTCLKOUT ((uint32_t)1U << 18U) +#define PUEN0_PUEN_DU_DB7 ((uint32_t)1U << 17U) +#define PUEN0_PUEN_DU_DB6 ((uint32_t)1U << 16U) +#define PUEN0_PUEN_DU_DB5 ((uint32_t)1U << 15U) +#define PUEN0_PUEN_DU_DB4 ((uint32_t)1U << 14U) +#define PUEN0_PUEN_DU_DB3 ((uint32_t)1U << 13U) +#define PUEN0_PUEN_DU_DB2 ((uint32_t)1U << 12U) +#define PUEN0_PUEN_DU_DG7 ((uint32_t)1U << 11U) +#define PUEN0_PUEN_DU_DG6 ((uint32_t)1U << 10U) +#define PUEN0_PUEN_DU_DG5 ((uint32_t)1U << 9U) +#define PUEN0_PUEN_DU_DG4 ((uint32_t)1U << 8U) +#define PUEN0_PUEN_DU_DG3 ((uint32_t)1U << 7U) +#define PUEN0_PUEN_DU_DG2 ((uint32_t)1U << 6U) +#define PUEN0_PUEN_DU_DR7 ((uint32_t)1U << 5U) +#define PUEN0_PUEN_DU_DR6 ((uint32_t)1U << 4U) +#define PUEN0_PUEN_DU_DR5 ((uint32_t)1U << 3U) +#define PUEN0_PUEN_DU_DR4 ((uint32_t)1U << 2U) +#define PUEN0_PUEN_DU_DR3 ((uint32_t)1U << 1U) +#define PUEN0_PUEN_DU_DR2 ((uint32_t)1U << 0U) + +#define PUEN1_PUEN_VI1_DATA11 ((uint32_t)1U << 31U) +#define PUEN1_PUEN_VI1_DATA10 ((uint32_t)1U << 30U) +#define PUEN1_PUEN_VI1_DATA9 ((uint32_t)1U << 29U) +#define PUEN1_PUEN_VI1_DATA8 ((uint32_t)1U << 28U) +#define PUEN1_PUEN_VI1_DATA7 ((uint32_t)1U << 27U) +#define PUEN1_PUEN_VI1_DATA6 ((uint32_t)1U << 26U) +#define PUEN1_PUEN_VI1_DATA5 ((uint32_t)1U << 25U) +#define PUEN1_PUEN_VI1_DATA4 ((uint32_t)1U << 24U) +#define PUEN1_PUEN_VI1_DATA3 ((uint32_t)1U << 23U) +#define PUEN1_PUEN_VI1_DATA2 ((uint32_t)1U << 22U) +#define PUEN1_PUEN_VI1_DATA1 ((uint32_t)1U << 21U) +#define PUEN1_PUEN_VI1_DATA0 ((uint32_t)1U << 20U) +#define PUEN1_PUEN_VI1_VSYNC_N ((uint32_t)1U << 19U) +#define PUEN1_PUEN_VI1_HSYNC_N ((uint32_t)1U << 18U) +#define PUEN1_PUEN_VI1_CLKENB ((uint32_t)1U << 17U) +#define PUEN1_PUEN_VI1_CLK ((uint32_t)1U << 16U) +#define PUEN1_PUEN_VI0_FIELD ((uint32_t)1U << 15U) +#define PUEN1_PUEN_VI0_DATA11 ((uint32_t)1U << 14U) +#define PUEN1_PUEN_VI0_DATA10 ((uint32_t)1U << 13U) +#define PUEN1_PUEN_VI0_DATA9 ((uint32_t)1U << 12U) +#define PUEN1_PUEN_VI0_DATA8 ((uint32_t)1U << 11U) +#define PUEN1_PUEN_VI0_DATA7 ((uint32_t)1U << 10U) +#define PUEN1_PUEN_VI0_DATA6 ((uint32_t)1U << 9U) +#define PUEN1_PUEN_VI0_DATA5 ((uint32_t)1U << 8U) +#define PUEN1_PUEN_VI0_DATA4 ((uint32_t)1U << 7U) +#define PUEN1_PUEN_VI0_DATA3 ((uint32_t)1U << 6U) +#define PUEN1_PUEN_VI0_DATA2 ((uint32_t)1U << 5U) +#define PUEN1_PUEN_VI0_DATA1 ((uint32_t)1U << 4U) +#define PUEN1_PUEN_VI0_DATA0 ((uint32_t)1U << 3U) +#define PUEN1_PUEN_VI0_VSYNC_N ((uint32_t)1U << 2U) +#define PUEN1_PUEN_VI0_HSYNC_N ((uint32_t)1U << 1U) +#define PUEN1_PUEN_VI0_CLKENB ((uint32_t)1U << 0U) + +#define PUEN2_PUEN_CANFD_CLK ((uint32_t)1U << 31U) +#define PUEN2_PUEN_CANFD1_RX ((uint32_t)1U << 30U) +#define PUEN2_PUEN_CANFD1_TX ((uint32_t)1U << 29U) +#define PUEN2_PUEN_CANFD0_RX ((uint32_t)1U << 28U) +#define PUEN2_PUEN_CANFD0_TX ((uint32_t)1U << 27U) +#define PUEN2_PUEN_AVB0_AVTP_CAPTURE ((uint32_t)1U << 26U) +#define PUEN2_PUEN_AVB0_AVTP_MATCH ((uint32_t)1U << 25U) +#define PUEN2_PUEN_AVB0_LINK ((uint32_t)1U << 24U) +#define PUEN2_PUEN_AVB0_PHY_INT ((uint32_t)1U << 23U) +#define PUEN2_PUEN_AVB0_MAGIC ((uint32_t)1U << 22U) +#define PUEN2_PUEN_AVB0_MDC ((uint32_t)1U << 21U) +#define PUEN2_PUEN_AVB0_MDIO ((uint32_t)1U << 20U) +#define PUEN2_PUEN_AVB0_TXCREFCLK ((uint32_t)1U << 19U) +#define PUEN2_PUEN_AVB0_TD3 ((uint32_t)1U << 18U) +#define PUEN2_PUEN_AVB0_TD2 ((uint32_t)1U << 17U) +#define PUEN2_PUEN_AVB0_TD1 ((uint32_t)1U << 16U) +#define PUEN2_PUEN_AVB0_TD0 ((uint32_t)1U << 15U) +#define PUEN2_PUEN_AVB0_TXC ((uint32_t)1U << 14U) +#define PUEN2_PUEN_AVB0_TX_CTL ((uint32_t)1U << 13U) +#define PUEN2_PUEN_AVB0_RD3 ((uint32_t)1U << 12U) +#define PUEN2_PUEN_AVB0_RD2 ((uint32_t)1U << 11U) +#define PUEN2_PUEN_AVB0_RD1 ((uint32_t)1U << 10U) +#define PUEN2_PUEN_AVB0_RD0 ((uint32_t)1U << 9U) +#define PUEN2_PUEN_AVB0_RXC ((uint32_t)1U << 8U) +#define PUEN2_PUEN_AVB0_RX_CTL ((uint32_t)1U << 7U) +#define PUEN2_PUEN_SDA2 ((uint32_t)1U << 6U) +#define PUEN2_PUEN_SCL2 ((uint32_t)1U << 5U) +#define PUEN2_PUEN_SDA1 ((uint32_t)1U << 4U) +#define PUEN2_PUEN_SCL1 ((uint32_t)1U << 3U) +#define PUEN2_PUEN_SDA0 ((uint32_t)1U << 2U) +#define PUEN2_PUEN_SCL0 ((uint32_t)1U << 1U) +#define PUEN2_PUEN_VI1_FIELD ((uint32_t)1U << 0U) + +#define PUEN3_PUEN_DIGRF_CLKOUT ((uint32_t)1U << 16U) +#define PUEN3_PUEN_DIGRF_CLKIN ((uint32_t)1U << 15U) +#define PUEN3_PUEN_RPC_INT_N ((uint32_t)1U << 14U) +#define PUEN3_PUEN_RPC_WP_N ((uint32_t)1U << 13U) +#define PUEN3_PUEN_RPC_RESET_N ((uint32_t)1U << 12U) +#define PUEN3_PUEN_QSPI1_SSL ((uint32_t)1U << 11U) +#define PUEN3_PUEN_QSPI1_IO3 ((uint32_t)1U << 10U) +#define PUEN3_PUEN_QSPI1_IO2 ((uint32_t)1U << 9U) +#define PUEN3_PUEN_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) +#define PUEN3_PUEN_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) +#define PUEN3_PUEN_QSPI1_SPCLK ((uint32_t)1U << 6U) +#define PUEN3_PUEN_QSPI0_SSL ((uint32_t)1U << 5U) +#define PUEN3_PUEN_QSPI0_IO3 ((uint32_t)1U << 4U) +#define PUEN3_PUEN_QSPI0_IO2 ((uint32_t)1U << 3U) +#define PUEN3_PUEN_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) +#define PUEN3_PUEN_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) +#define PUEN3_PUEN_QSPI0_SPCLK ((uint32_t)1U << 0U) + +#define PUD0_PUD_VI0_CLK ((uint32_t)1U << 31U) +#define PUD0_PUD_IRQ0 ((uint32_t)1U << 26U) +#define PUD0_PUD_FSCLKST_N ((uint32_t)1U << 25U) +#define PUD0_PUD_PRESETOUT_N ((uint32_t)1U << 23U) +#define PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE ((uint32_t)1U << 21U) +#define PUD0_PUD_DU_EXVSYNC_DU_VSYNC ((uint32_t)1U << 20U) +#define PUD0_PUD_DU_EXHSYNC_DU_HSYNC ((uint32_t)1U << 19U) +#define PUD0_PUD_DU_DOTCLKOUT ((uint32_t)1U << 18U) +#define PUD0_PUD_DU_DB7 ((uint32_t)1U << 17U) +#define PUD0_PUD_DU_DB6 ((uint32_t)1U << 16U) +#define PUD0_PUD_DU_DB5 ((uint32_t)1U << 15U) +#define PUD0_PUD_DU_DB4 ((uint32_t)1U << 14U) +#define PUD0_PUD_DU_DB3 ((uint32_t)1U << 13U) +#define PUD0_PUD_DU_DB2 ((uint32_t)1U << 12U) +#define PUD0_PUD_DU_DG7 ((uint32_t)1U << 11U) +#define PUD0_PUD_DU_DG6 ((uint32_t)1U << 10U) +#define PUD0_PUD_DU_DG5 ((uint32_t)1U << 9U) +#define PUD0_PUD_DU_DG4 ((uint32_t)1U << 8U) +#define PUD0_PUD_DU_DG3 ((uint32_t)1U << 7U) +#define PUD0_PUD_DU_DG2 ((uint32_t)1U << 6U) +#define PUD0_PUD_DU_DR7 ((uint32_t)1U << 5U) +#define PUD0_PUD_DU_DR6 ((uint32_t)1U << 4U) +#define PUD0_PUD_DU_DR5 ((uint32_t)1U << 3U) +#define PUD0_PUD_DU_DR4 ((uint32_t)1U << 2U) +#define PUD0_PUD_DU_DR3 ((uint32_t)1U << 1U) +#define PUD0_PUD_DU_DR2 ((uint32_t)1U << 0U) + +#define PUD1_PUD_VI1_DATA11 ((uint32_t)1U << 31U) +#define PUD1_PUD_VI1_DATA10 ((uint32_t)1U << 30U) +#define PUD1_PUD_VI1_DATA9 ((uint32_t)1U << 29U) +#define PUD1_PUD_VI1_DATA8 ((uint32_t)1U << 28U) +#define PUD1_PUD_VI1_DATA7 ((uint32_t)1U << 27U) +#define PUD1_PUD_VI1_DATA6 ((uint32_t)1U << 26U) +#define PUD1_PUD_VI1_DATA5 ((uint32_t)1U << 25U) +#define PUD1_PUD_VI1_DATA4 ((uint32_t)1U << 24U) +#define PUD1_PUD_VI1_DATA3 ((uint32_t)1U << 23U) +#define PUD1_PUD_VI1_DATA2 ((uint32_t)1U << 22U) +#define PUD1_PUD_VI1_DATA1 ((uint32_t)1U << 21U) +#define PUD1_PUD_VI1_DATA0 ((uint32_t)1U << 20U) +#define PUD1_PUD_VI1_VSYNC_N ((uint32_t)1U << 19U) +#define PUD1_PUD_VI1_HSYNC_N ((uint32_t)1U << 18U) +#define PUD1_PUD_VI1_CLKENB ((uint32_t)1U << 17U) +#define PUD1_PUD_VI1_CLK ((uint32_t)1U << 16U) +#define PUD1_PUD_VI0_FIELD ((uint32_t)1U << 15U) +#define PUD1_PUD_VI0_DATA11 ((uint32_t)1U << 14U) +#define PUD1_PUD_VI0_DATA10 ((uint32_t)1U << 13U) +#define PUD1_PUD_VI0_DATA9 ((uint32_t)1U << 12U) +#define PUD1_PUD_VI0_DATA8 ((uint32_t)1U << 11U) +#define PUD1_PUD_VI0_DATA7 ((uint32_t)1U << 10U) +#define PUD1_PUD_VI0_DATA6 ((uint32_t)1U << 9U) +#define PUD1_PUD_VI0_DATA5 ((uint32_t)1U << 8U) +#define PUD1_PUD_VI0_DATA4 ((uint32_t)1U << 7U) +#define PUD1_PUD_VI0_DATA3 ((uint32_t)1U << 6U) +#define PUD1_PUD_VI0_DATA2 ((uint32_t)1U << 5U) +#define PUD1_PUD_VI0_DATA1 ((uint32_t)1U << 4U) +#define PUD1_PUD_VI0_DATA0 ((uint32_t)1U << 3U) +#define PUD1_PUD_VI0_VSYNC_N ((uint32_t)1U << 2U) +#define PUD1_PUD_VI0_HSYNC_N ((uint32_t)1U << 1U) +#define PUD1_PUD_VI0_CLKENB ((uint32_t)1U << 0U) + +#define PUD2_PUD_CANFD_CLK ((uint32_t)1U << 31U) +#define PUD2_PUD_CANFD1_RX ((uint32_t)1U << 30U) +#define PUD2_PUD_CANFD1_TX ((uint32_t)1U << 29U) +#define PUD2_PUD_CANFD0_RX ((uint32_t)1U << 28U) +#define PUD2_PUD_CANFD0_TX ((uint32_t)1U << 27U) +#define PUD2_PUD_AVB0_AVTP_CAPTURE ((uint32_t)1U << 26U) +#define PUD2_PUD_AVB0_AVTP_MATCH ((uint32_t)1U << 25U) +#define PUD2_PUD_AVB0_LINK ((uint32_t)1U << 24U) +#define PUD2_PUD_AVB0_PHY_INT ((uint32_t)1U << 23U) +#define PUD2_PUD_AVB0_MAGIC ((uint32_t)1U << 22U) +#define PUD2_PUD_AVB0_MDC ((uint32_t)1U << 21U) +#define PUD2_PUD_AVB0_MDIO ((uint32_t)1U << 20U) +#define PUD2_PUD_AVB0_TXCREFCLK ((uint32_t)1U << 19U) +#define PUD2_PUD_AVB0_TD3 ((uint32_t)1U << 18U) +#define PUD2_PUD_AVB0_TD2 ((uint32_t)1U << 17U) +#define PUD2_PUD_AVB0_TD1 ((uint32_t)1U << 16U) +#define PUD2_PUD_AVB0_TD0 ((uint32_t)1U << 15U) +#define PUD2_PUD_AVB0_TXC ((uint32_t)1U << 14U) +#define PUD2_PUD_AVB0_TX_CTL ((uint32_t)1U << 13U) +#define PUD2_PUD_AVB0_RD3 ((uint32_t)1U << 12U) +#define PUD2_PUD_AVB0_RD2 ((uint32_t)1U << 11U) +#define PUD2_PUD_AVB0_RD1 ((uint32_t)1U << 10U) +#define PUD2_PUD_AVB0_RD0 ((uint32_t)1U << 9U) +#define PUD2_PUD_AVB0_RXC ((uint32_t)1U << 8U) +#define PUD2_PUD_AVB0_RX_CTL ((uint32_t)1U << 7U) +#define PUD2_PUD_SDA2 ((uint32_t)1U << 6U) +#define PUD2_PUD_SCL2 ((uint32_t)1U << 5U) +#define PUD2_PUD_SDA1 ((uint32_t)1U << 4U) +#define PUD2_PUD_SCL1 ((uint32_t)1U << 3U) +#define PUD2_PUD_SDA0 ((uint32_t)1U << 2U) +#define PUD2_PUD_SCL0 ((uint32_t)1U << 1U) +#define PUD2_PUD_VI1_FIELD ((uint32_t)1U << 0U) + +#define PUD3_PUD_DIGRF_CLKOUT ((uint32_t)1U << 16U) +#define PUD3_PUD_DIGRF_CLKIN ((uint32_t)1U << 15U) +#define PUD3_PUD_RPC_INT_N ((uint32_t)1U << 14U) +#define PUD3_PUD_RPC_WP_N ((uint32_t)1U << 13U) +#define PUD3_PUD_RPC_RESET_N ((uint32_t)1U << 12U) +#define PUD3_PUD_QSPI1_SSL ((uint32_t)1U << 11U) +#define PUD3_PUD_QSPI1_IO3 ((uint32_t)1U << 10U) +#define PUD3_PUD_QSPI1_IO2 ((uint32_t)1U << 9U) +#define PUD3_PUD_QSPI1_MISO_IO1 ((uint32_t)1U << 8U) +#define PUD3_PUD_QSPI1_MOSI_IO0 ((uint32_t)1U << 7U) +#define PUD3_PUD_QSPI1_SPCLK ((uint32_t)1U << 6U) +#define PUD3_PUD_QSPI0_SSL ((uint32_t)1U << 5U) +#define PUD3_PUD_QSPI0_IO3 ((uint32_t)1U << 4U) +#define PUD3_PUD_QSPI0_IO2 ((uint32_t)1U << 3U) +#define PUD3_PUD_QSPI0_MISO_IO1 ((uint32_t)1U << 2U) +#define PUD3_PUD_QSPI0_MOSI_IO0 ((uint32_t)1U << 1U) +#define PUD3_PUD_QSPI0_SPCLK ((uint32_t)1U << 0U) + +#define MOD_SEL0_sel_hscif0 ((uint32_t)1U << 10U) +#define MOD_SEL0_sel_scif1 ((uint32_t)1U << 9U) +#define MOD_SEL0_sel_canfd0 ((uint32_t)1U << 8U) +#define MOD_SEL0_sel_pwm4 ((uint32_t)1U << 7U) +#define MOD_SEL0_sel_pwm3 ((uint32_t)1U << 6U) +#define MOD_SEL0_sel_pwm2 ((uint32_t)1U << 5U) +#define MOD_SEL0_sel_pwm1 ((uint32_t)1U << 4U) +#define MOD_SEL0_sel_pwm0 ((uint32_t)1U << 3U) +#define MOD_SEL0_sel_rfso ((uint32_t)1U << 2U) +#define MOD_SEL0_sel_rsp ((uint32_t)1U << 1U) +#define MOD_SEL0_sel_tmu ((uint32_t)1U << 0U) + +/* SCIF3 Registers for Dummy write */ +#define SCIF3_BASE (0xE6C50000U) +#define SCIF3_SCFCR (SCIF3_BASE + 0x0018U) +#define SCIF3_SCFDR (SCIF3_BASE + 0x001CU) +#define SCFCR_DATA (0x0000U) + +/* Realtime module stop control */ +#define CPG_BASE (0xE6150000U) +#define CPG_MSTPSR0 (CPG_BASE + 0x0030U) +#define CPG_RMSTPCR0 (CPG_BASE + 0x0110U) +#define RMSTPCR0_RTDMAC (0x00200000U) + +static void pfc_reg_write(uint32_t addr, uint32_t data); + +static void pfc_reg_write(uint32_t addr, uint32_t data) +{ + mmio_write_32(PFC_PMMR, ~data); + mmio_write_32((uintptr_t)addr, data); +} +/* End of function pfc_reg_write */ + +void pfc_init_v3m(void) +{ + + /* initialize GPIO/perihperal function select */ + + pfc_reg_write(PFC_GPSR0, 0x00000000); + + pfc_reg_write(PFC_GPSR1, GPSR1_CANFD_CLK); + + pfc_reg_write(PFC_GPSR2, 0x00000000); + + pfc_reg_write(PFC_GPSR3, 0x00000000); + + pfc_reg_write(PFC_GPSR4, GPSR4_SDA2 + | GPSR4_SCL2); + + pfc_reg_write(PFC_GPSR5, GPSR5_QSPI1_SSL + | GPSR5_QSPI1_IO3 + | GPSR5_QSPI1_IO2 + | GPSR5_QSPI1_MISO_IO1 + | GPSR5_QSPI1_MOSI_IO0 + | GPSR5_QSPI1_SPCLK + | GPSR5_QSPI0_SSL + | GPSR5_QSPI0_IO3 + | GPSR5_QSPI0_IO2 + | GPSR5_QSPI0_MISO_IO1 + | GPSR5_QSPI0_MOSI_IO0 + | GPSR5_QSPI0_SPCLK); + + + /* initialize peripheral function select */ + pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + + pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + + pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + + pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + + pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + + pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + + pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(0) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + + pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) + | IPSR_24_FUNC(4) + | IPSR_20_FUNC(4) + | IPSR_16_FUNC(4) + | IPSR_12_FUNC(4) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + + pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0) + | IPSR_24_FUNC(0) + | IPSR_20_FUNC(0) + | IPSR_16_FUNC(4) + | IPSR_12_FUNC(0) + | IPSR_8_FUNC(0) + | IPSR_4_FUNC(0) + | IPSR_0_FUNC(0)); + + /* initialize POC Control */ + + pfc_reg_write(PFC_IOCTRL30, IOCTRL30_POC_VI0_DATA5 + | IOCTRL30_POC_VI0_DATA4 + | IOCTRL30_POC_VI0_DATA3 + | IOCTRL30_POC_VI0_DATA2 + | IOCTRL30_POC_VI0_DATA1 + | IOCTRL30_POC_VI0_DATA0 + | IOCTRL30_POC_VI0_VSYNC_N + | IOCTRL30_POC_VI0_HSYNC_N + | IOCTRL30_POC_VI0_CLKENB + | IOCTRL30_POC_VI0_CLK + | IOCTRL30_POC_DU_EXODDF_DU_ODDF_DISP_CDE + | IOCTRL30_POC_DU_EXVSYNC_DU_VSYNC + | IOCTRL30_POC_DU_EXHSYNC_DU_HSYNC + | IOCTRL30_POC_DU_DOTCLKOUT + | IOCTRL30_POC_DU_DB7 + | IOCTRL30_POC_DU_DB6 + | IOCTRL30_POC_DU_DB5 + | IOCTRL30_POC_DU_DB4 + | IOCTRL30_POC_DU_DB3 + | IOCTRL30_POC_DU_DB2 + | IOCTRL30_POC_DU_DG7 + | IOCTRL30_POC_DU_DG6 + | IOCTRL30_POC_DU_DG5 + | IOCTRL30_POC_DU_DG4 + | IOCTRL30_POC_DU_DG3 + | IOCTRL30_POC_DU_DG2 + | IOCTRL30_POC_DU_DR7 + | IOCTRL30_POC_DU_DR6 + | IOCTRL30_POC_DU_DR5 + | IOCTRL30_POC_DU_DR4 + | IOCTRL30_POC_DU_DR3 + | IOCTRL30_POC_DU_DR2); + + pfc_reg_write(PFC_IOCTRL31, IOCTRL31_POC_DUMMY_31 + | IOCTRL31_POC_DUMMY_30 + | IOCTRL31_POC_DUMMY_29 + | IOCTRL31_POC_DUMMY_28 + | IOCTRL31_POC_DUMMY_27 + | IOCTRL31_POC_DUMMY_26 + | IOCTRL31_POC_DUMMY_25 + | IOCTRL31_POC_DUMMY_24 + | IOCTRL31_POC_VI1_FIELD + | IOCTRL31_POC_VI1_DATA11 + | IOCTRL31_POC_VI1_DATA10 + | IOCTRL31_POC_VI1_DATA9 + | IOCTRL31_POC_VI1_DATA8 + | IOCTRL31_POC_VI1_DATA7 + | IOCTRL31_POC_VI1_DATA6 + | IOCTRL31_POC_VI1_DATA5 + | IOCTRL31_POC_VI1_DATA4 + | IOCTRL31_POC_VI1_DATA3 + | IOCTRL31_POC_VI1_DATA2 + | IOCTRL31_POC_VI1_DATA1 + | IOCTRL31_POC_VI1_DATA0 + | IOCTRL31_POC_VI1_VSYNC_N + | IOCTRL31_POC_VI1_HSYNC_N + | IOCTRL31_POC_VI1_CLKENB + | IOCTRL31_POC_VI1_CLK + | IOCTRL31_POC_VI0_FIELD + | IOCTRL31_POC_VI0_DATA11 + | IOCTRL31_POC_VI0_DATA10 + | IOCTRL31_POC_VI0_DATA9 + | IOCTRL31_POC_VI0_DATA8 + | IOCTRL31_POC_VI0_DATA7 + | IOCTRL31_POC_VI0_DATA6); + + pfc_reg_write(PFC_IOCTRL32,0x00000000); + + pfc_reg_write(PFC_IOCTRL40,0x00000000); + + /* initialize Pull enable */ + pfc_reg_write(PFC_PUEN0,PUEN0_PUEN_VI0_CLK + | PUEN0_PUEN_TDI + | PUEN0_PUEN_TMS + | PUEN0_PUEN_TCK + | PUEN0_PUEN_TRST_N + | PUEN0_PUEN_IRQ0 + | PUEN0_PUEN_FSCLKST_N + | PUEN0_PUEN_DU_EXHSYNC_DU_HSYNC + | PUEN0_PUEN_DU_DOTCLKOUT + | PUEN0_PUEN_DU_DB7 + | PUEN0_PUEN_DU_DB6 + | PUEN0_PUEN_DU_DB5 + | PUEN0_PUEN_DU_DB4 + | PUEN0_PUEN_DU_DB3 + | PUEN0_PUEN_DU_DB2 + | PUEN0_PUEN_DU_DG7 + | PUEN0_PUEN_DU_DG6 + | PUEN0_PUEN_DU_DG5 + | PUEN0_PUEN_DU_DG4 + | PUEN0_PUEN_DU_DG3 + | PUEN0_PUEN_DU_DG2 + | PUEN0_PUEN_DU_DR7 + | PUEN0_PUEN_DU_DR6 + | PUEN0_PUEN_DU_DR5 + | PUEN0_PUEN_DU_DR4 + | PUEN0_PUEN_DU_DR3 + | PUEN0_PUEN_DU_DR2); + + pfc_reg_write(PFC_PUEN1,PUEN1_PUEN_VI1_DATA11 + | PUEN1_PUEN_VI1_DATA10 + | PUEN1_PUEN_VI1_DATA9 + | PUEN1_PUEN_VI1_DATA8 + | PUEN1_PUEN_VI1_DATA7 + | PUEN1_PUEN_VI1_DATA6 + | PUEN1_PUEN_VI1_DATA5 + | PUEN1_PUEN_VI1_DATA4 + | PUEN1_PUEN_VI1_DATA3 + | PUEN1_PUEN_VI1_DATA2 + | PUEN1_PUEN_VI1_DATA1 + | PUEN1_PUEN_VI1_DATA0 + | PUEN1_PUEN_VI1_VSYNC_N + | PUEN1_PUEN_VI1_HSYNC_N + | PUEN1_PUEN_VI1_CLKENB + | PUEN1_PUEN_VI1_CLK + | PUEN1_PUEN_VI0_DATA11 + | PUEN1_PUEN_VI0_DATA10 + | PUEN1_PUEN_VI0_DATA9 + | PUEN1_PUEN_VI0_DATA8 + | PUEN1_PUEN_VI0_DATA7 + | PUEN1_PUEN_VI0_DATA6 + | PUEN1_PUEN_VI0_DATA5 + | PUEN1_PUEN_VI0_DATA4 + | PUEN1_PUEN_VI0_DATA3 + | PUEN1_PUEN_VI0_DATA2 + | PUEN1_PUEN_VI0_DATA1); + + pfc_reg_write(PFC_PUEN2,PUEN2_PUEN_CANFD_CLK + | PUEN2_PUEN_CANFD1_RX + | PUEN2_PUEN_CANFD1_TX + | PUEN2_PUEN_CANFD0_RX + | PUEN2_PUEN_CANFD0_TX + | PUEN2_PUEN_AVB0_AVTP_CAPTURE + | PUEN2_PUEN_AVB0_AVTP_MATCH + | PUEN2_PUEN_AVB0_LINK + | PUEN2_PUEN_AVB0_PHY_INT + | PUEN2_PUEN_AVB0_MAGIC + | PUEN2_PUEN_AVB0_TXCREFCLK + | PUEN2_PUEN_AVB0_TD3 + | PUEN2_PUEN_AVB0_TD2 + | PUEN2_PUEN_AVB0_TD1 + | PUEN2_PUEN_AVB0_TD0 + | PUEN2_PUEN_AVB0_TXC + | PUEN2_PUEN_AVB0_TX_CTL + | PUEN2_PUEN_AVB0_RD3 + | PUEN2_PUEN_AVB0_RD2 + | PUEN2_PUEN_AVB0_RD1 + | PUEN2_PUEN_AVB0_RD0 + | PUEN2_PUEN_AVB0_RXC + | PUEN2_PUEN_AVB0_RX_CTL + | PUEN2_PUEN_VI1_FIELD); + + pfc_reg_write(PFC_PUEN3,PUEN3_PUEN_DIGRF_CLKOUT + | PUEN3_PUEN_DIGRF_CLKIN); + + /* initialize PUD Control */ + pfc_reg_write(PFC_PUD0,PUD0_PUD_VI0_CLK + | PUD0_PUD_IRQ0 + | PUD0_PUD_FSCLKST_N + | PUD0_PUD_DU_EXODDF_DU_ODDF_DISP_CDE + | PUD0_PUD_DU_EXVSYNC_DU_VSYNC + | PUD0_PUD_DU_EXHSYNC_DU_HSYNC + | PUD0_PUD_DU_DOTCLKOUT + | PUD0_PUD_DU_DB7 + | PUD0_PUD_DU_DB6 + | PUD0_PUD_DU_DB5 + | PUD0_PUD_DU_DB4 + | PUD0_PUD_DU_DB3 + | PUD0_PUD_DU_DB2 + | PUD0_PUD_DU_DG7 + | PUD0_PUD_DU_DG6 + | PUD0_PUD_DU_DG5 + | PUD0_PUD_DU_DG4 + | PUD0_PUD_DU_DG3 + | PUD0_PUD_DU_DG2 + | PUD0_PUD_DU_DR7 + | PUD0_PUD_DU_DR6 + | PUD0_PUD_DU_DR5 + | PUD0_PUD_DU_DR4 + | PUD0_PUD_DU_DR3 + | PUD0_PUD_DU_DR2); + + pfc_reg_write(PFC_PUD1,PUD1_PUD_VI1_DATA11 + | PUD1_PUD_VI1_DATA10 + | PUD1_PUD_VI1_DATA9 + | PUD1_PUD_VI1_DATA8 + | PUD1_PUD_VI1_DATA7 + | PUD1_PUD_VI1_DATA6 + | PUD1_PUD_VI1_DATA5 + | PUD1_PUD_VI1_DATA4 + | PUD1_PUD_VI1_DATA3 + | PUD1_PUD_VI1_DATA2 + | PUD1_PUD_VI1_DATA1 + | PUD1_PUD_VI1_DATA0 + | PUD1_PUD_VI1_VSYNC_N + | PUD1_PUD_VI1_HSYNC_N + | PUD1_PUD_VI1_CLKENB + | PUD1_PUD_VI1_CLK + | PUD1_PUD_VI0_DATA11 + | PUD1_PUD_VI0_DATA10 + | PUD1_PUD_VI0_DATA9 + | PUD1_PUD_VI0_DATA8 + | PUD1_PUD_VI0_DATA7 + | PUD1_PUD_VI0_DATA6 + | PUD1_PUD_VI0_DATA5 + | PUD1_PUD_VI0_DATA4 + | PUD1_PUD_VI0_DATA3 + | PUD1_PUD_VI0_DATA2 + | PUD1_PUD_VI0_DATA1 + | PUD1_PUD_VI0_DATA0 + | PUD1_PUD_VI0_VSYNC_N + | PUD1_PUD_VI0_HSYNC_N + | PUD1_PUD_VI0_CLKENB); + + pfc_reg_write(PFC_PUD2,PUD2_PUD_CANFD_CLK + | PUD2_PUD_CANFD1_RX + | PUD2_PUD_CANFD1_TX + | PUD2_PUD_CANFD0_RX + | PUD2_PUD_CANFD0_TX + | PUD2_PUD_AVB0_AVTP_CAPTURE + | PUD2_PUD_VI1_FIELD); + + pfc_reg_write(PFC_PUD3,PUD3_PUD_DIGRF_CLKOUT + | PUD3_PUD_DIGRF_CLKIN); + + /* initialize Module Select */ + pfc_reg_write(PFC_MOD_SEL0,0x00000000); + + /* initialize positive/negative logic select */ + mmio_write_32(GPIO_POSNEG0, 0x00000000U); + mmio_write_32(GPIO_POSNEG1, 0x00000000U); + mmio_write_32(GPIO_POSNEG2, 0x00000000U); + mmio_write_32(GPIO_POSNEG3, 0x00000000U); + mmio_write_32(GPIO_POSNEG4, 0x00000000U); + mmio_write_32(GPIO_POSNEG5, 0x00000000U); + + /* initialize general IO/interrupt switching */ + mmio_write_32(GPIO_IOINTSEL0, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL1, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL2, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL3, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL4, 0x00000000U); + mmio_write_32(GPIO_IOINTSEL5, 0x00000000U); + + /* initialize general output register */ + mmio_write_32(GPIO_OUTDT0, 0x00000000U); + mmio_write_32(GPIO_OUTDT1, 0x00000000U); + mmio_write_32(GPIO_OUTDT2, 0x00000000U); + mmio_write_32(GPIO_OUTDT3, 0x00000000U); + mmio_write_32(GPIO_OUTDT4, 0x00000000U); + mmio_write_32(GPIO_OUTDT5, 0x00000000U); + + /* initialize general input/output switching */ + mmio_write_32(GPIO_INOUTSEL0, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL1, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL2, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL3, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL4, 0x00000000U); + mmio_write_32(GPIO_INOUTSEL5, 0x00000000U); +} +/* End of function pfc_init_v3m */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/pfc/V3M/pfc_init_v3m.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/pfc/V3M/pfc_init_v3m.h new file mode 100644 index 0000000..5a7b724 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/pfc/V3M/pfc_init_v3m.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef PFC_INIT_V3M_H__ +#define PFC_INIT_V3M_H__ + +void pfc_init_v3m(void); + +#endif /* PFC_INIT_V3M_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/pfc/pfc.mk b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/pfc/pfc.mk new file mode 100644 index 0000000..d0446a3 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/pfc/pfc.mk @@ -0,0 +1,7 @@ +# +# Copyright (c) 2015-2019, Renesas Electronics Corporation +# All rights reserved. +# + +OBJ_FILE += pfc/V3M/pfc_init_v3m.o \ + pfc/pfc_init.o diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/pfc/pfc_init.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/pfc/pfc_init.c new file mode 100644 index 0000000..856e4bb --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/pfc/pfc_init.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file pfc_init.c + * - Version : 0.01 + * @brief Initial setting process of PFC. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include "rcar_def.h" +#include "pfc_init.h" +#include "V3M/pfc_init_v3m.h" + +void pfc_init(void) +{ + pfc_init_v3m(); +} +/* End of function pfc_init */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/V3M/qos_init_v3m.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/V3M/qos_init_v3m.c new file mode 100644 index 0000000..0d3a573 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/V3M/qos_init_v3m.c @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file qos_init_v3m.c + * - Version : 0.01 + * @brief QoS driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include "qos_init_v3m.h" + +#if ((RCAR_REF_INT == RCAR_REF_DEFAULT) || (RCAR_REF_INT == RCAR_REF_1950)) +#include "qos_mstat390.h" +#else +#include "qos_mstat780.h" +#endif + +#define RCAR_QOS_VERSION "rev.0.07" + +#define RCAR_DRAM_SPLIT_LINEAR (0U) +#define RCAR_DRAM_SPLIT_4CH (1U) +#define RCAR_DRAM_SPLIT_2CH (2U) + +#define RCAR_REF_DEFAULT (0U) +#define RCAR_REF_7800 (1U) +#define RCAR_REF_1950 (2U) + +#define DBSC_BASE (0xE6790000U) +#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U) +#define DBSC_AXARB (DBSC_BASE + 0x0800U) + +#define DBSC_DBCAM0CNF0 (DBSC_BASE + 0x0900U) +#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) +#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) +#define DBSC_DBCAMDIS (DBSC_BASE + 0x09fCU) +#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) +#define DBSC_DBSCHCNT1 (DBSC_BASE + 0x1004U) +#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) +#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U) +#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) +#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) +#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) +#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) +#define DBSC_DBSCHQOS_1_0 (DBSC_BASE + 0x1040U) +#define DBSC_DBSCHQOS_1_1 (DBSC_BASE + 0x1044U) +#define DBSC_DBSCHQOS_1_2 (DBSC_BASE + 0x1048U) +#define DBSC_DBSCHQOS_1_3 (DBSC_BASE + 0x104CU) +#define DBSC_DBSCHQOS_2_0 (DBSC_BASE + 0x1050U) +#define DBSC_DBSCHQOS_2_1 (DBSC_BASE + 0x1054U) +#define DBSC_DBSCHQOS_2_2 (DBSC_BASE + 0x1058U) +#define DBSC_DBSCHQOS_2_3 (DBSC_BASE + 0x105CU) +#define DBSC_DBSCHQOS_3_0 (DBSC_BASE + 0x1060U) +#define DBSC_DBSCHQOS_3_1 (DBSC_BASE + 0x1064U) +#define DBSC_DBSCHQOS_3_2 (DBSC_BASE + 0x1068U) +#define DBSC_DBSCHQOS_3_3 (DBSC_BASE + 0x106CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) +#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) +#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) +#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) +#define DBSC_DBSCHQOS_5_0 (DBSC_BASE + 0x1080U) +#define DBSC_DBSCHQOS_5_1 (DBSC_BASE + 0x1084U) +#define DBSC_DBSCHQOS_5_2 (DBSC_BASE + 0x1088U) +#define DBSC_DBSCHQOS_5_3 (DBSC_BASE + 0x108CU) +#define DBSC_DBSCHQOS_6_0 (DBSC_BASE + 0x1090U) +#define DBSC_DBSCHQOS_6_1 (DBSC_BASE + 0x1094U) +#define DBSC_DBSCHQOS_6_2 (DBSC_BASE + 0x1098U) +#define DBSC_DBSCHQOS_6_3 (DBSC_BASE + 0x109CU) +#define DBSC_DBSCHQOS_7_0 (DBSC_BASE + 0x10A0U) +#define DBSC_DBSCHQOS_7_1 (DBSC_BASE + 0x10A4U) +#define DBSC_DBSCHQOS_7_2 (DBSC_BASE + 0x10A8U) +#define DBSC_DBSCHQOS_7_3 (DBSC_BASE + 0x10ACU) +#define DBSC_DBSCHQOS_8_0 (DBSC_BASE + 0x10B0U) +#define DBSC_DBSCHQOS_8_1 (DBSC_BASE + 0x10B4U) +#define DBSC_DBSCHQOS_8_2 (DBSC_BASE + 0x10B8U) +#define DBSC_DBSCHQOS_8_3 (DBSC_BASE + 0x10BCU) +#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) +#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) +#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) +#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) +#define DBSC_DBSCHQOS_10_0 (DBSC_BASE + 0x10D0U) +#define DBSC_DBSCHQOS_10_1 (DBSC_BASE + 0x10D4U) +#define DBSC_DBSCHQOS_10_2 (DBSC_BASE + 0x10D8U) +#define DBSC_DBSCHQOS_10_3 (DBSC_BASE + 0x10DCU) +#define DBSC_DBSCHQOS_11_0 (DBSC_BASE + 0x10E0U) +#define DBSC_DBSCHQOS_11_1 (DBSC_BASE + 0x10E4U) +#define DBSC_DBSCHQOS_11_2 (DBSC_BASE + 0x10E8U) +#define DBSC_DBSCHQOS_11_3 (DBSC_BASE + 0x10ECU) +#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) +#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) +#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) +#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) +#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) +#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) +#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) +#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) +#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) +#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) +#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) +#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) +#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U) +#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U) +#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) + +#define AXI_BASE (0xE6784000U) +#define AXI_ADSPLCR0 (AXI_BASE + 0x0008U) +#define AXI_ADSPLCR1 (AXI_BASE + 0x000CU) +#define AXI_ADSPLCR2 (AXI_BASE + 0x0010U) +#define AXI_ADSPLCR3 (AXI_BASE + 0x0014U) +#define AXI_MMCR (AXI_BASE + 0x0300U) +#define ADSPLCR0_ADRMODE_DEFAULT ((uint32_t)0U << 31U) +#define ADSPLCR0_ADRMODE_GEN2 ((uint32_t)1U << 31U) +/* bit shift for SPLITSEL of ADSPLCR0 */ +#define ADSPLCR0_SPLITSEL(x) ((uint32_t)(x) << 16U) +/* bit shift for AREA of ADSPLCR0 */ +#define ADSPLCR0_AREA(x) ((uint32_t)(x) << 8U) +#define ADSPLCR0_SWP (0x0CU) + +#define MSTAT_BASE (0xE67E0000U) +#define MSTAT_FIX_QOS_BANK0 (MSTAT_BASE + 0x0000U) +#define MSTAT_FIX_QOS_BANK1 (MSTAT_BASE + 0x1000U) +#define MSTAT_BE_QOS_BANK0 (MSTAT_BASE + 0x2000U) +#define MSTAT_BE_QOS_BANK1 (MSTAT_BASE + 0x3000U) +#define MSTAT_SL_INIT (MSTAT_BASE + 0x8000U) +#define MSTAT_REF_ARS (MSTAT_BASE + 0x8004U) +#define MSTAT_STATQC (MSTAT_BASE + 0x8008U) + +#define RALLOC_BASE (0xE67F0000U) +#define RALLOC_RAS (RALLOC_BASE + 0x0000U) +#define RALLOC_RAEN (RALLOC_BASE + 0x0018U) +#define RALLOC_DANN (RALLOC_BASE + 0x0030U) +#define RALLOC_DANT (RALLOC_BASE + 0x0038U) +#define RALLOC_EMS (RALLOC_BASE + 0x0040U) +#define RALLOC_FSS (RALLOC_BASE + 0x0048U) +#define RALLOC_INSFC (RALLOC_BASE + 0x0050U) +#define RALLOC_RACNT0 (RALLOC_BASE + 0x0080U) + +#define CPU_DOMAIN_ACT_BASE (0xF1300000U) +#define CPU_ACT0 (CPU_DOMAIN_ACT_BASE + 0x0800U) +#define CPU_ACT1 (CPU_DOMAIN_ACT_BASE + 0x40800U) + +/* Calculating the number of array */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + + +static inline void io_write_32(uintptr_t addr, uint32_t value) +{ + *(volatile uint32_t*)addr = value; +} +/* End of function io_write_32 */ + +static inline void io_write_64(uintptr_t addr, uint64_t value) +{ + *(volatile uint64_t*)addr = value; +} +/* End of function io_write_64 */ + +static void dbsc_setting(void) +{ + + /* Register write enable */ + io_write_32(DBSC_DBSYSCNT0, 0x00001234U); + + /* BUFCAM settings */ + /* DBSC_DBCAM0CNF0 not set */ + io_write_32(DBSC_DBCAM0CNF1, 0x00043218U); /* dbcam0cnf1 */ + io_write_32(DBSC_DBCAM0CNF2, 0x000000F4U); /* dbcam0cnf2 */ + /* io_write_32(DBSC_DBCAM0CNF3, 0x00000007); */ /* dbcam0cnf3 */ + io_write_32(DBSC_DBSCHCNT0, 0x000F0037U); /* dbschcnt0 */ + /* dbschcnt0 not set */ + + io_write_32(DBSC_DBSCHSZ0, 0x00000001U); /* dbschsz0 */ + io_write_32(DBSC_DBSCHRW0, 0x22421111U); /* dbschrw0 */ + /* dbschrw1 not set */ + /* SCFCTST0 not set */ + /* SCFCTST1 not set */ + io_write_32(DBSC_SCFCTST2,0x012F1123U); + + /* QoS Settings */ + io_write_32(DBSC_DBSCHQOS_0_0, 0x00000F00U); + io_write_32(DBSC_DBSCHQOS_0_1, 0x00000B00U); + io_write_32(DBSC_DBSCHQOS_0_2, 0x00000000U); + io_write_32(DBSC_DBSCHQOS_0_3, 0x00000000U); + /* DBSC_DBSCHQOS_1_0 not set */ + /* DBSC_DBSCHQOS_1_1 not set */ + /* DBSC_DBSCHQOS_1_2 not set */ + /* DBSC_DBSCHQOS_1_3 not set */ + /* DBSC_DBSCHQOS_2_0 not set */ + /* DBSC_DBSCHQOS_2_1 not set */ + /* DBSC_DBSCHQOS_2_2 not set */ + /* DBSC_DBSCHQOS_2_3 not set */ + /* DBSC_DBSCHQOS_3_0 not set */ + /* DBSC_DBSCHQOS_3_1 not set */ + /* DBSC_DBSCHQOS_3_2 not set */ + /* DBSC_DBSCHQOS_3_3 not set */ + io_write_32(DBSC_DBSCHQOS_4_0, 0x00000300U); + io_write_32(DBSC_DBSCHQOS_4_1, 0x000002F0U); + io_write_32(DBSC_DBSCHQOS_4_2, 0x00000200U); + io_write_32(DBSC_DBSCHQOS_4_3, 0x00000100U); + /* DBSC_DBSCHQOS_5_0 not set */ + /* DBSC_DBSCHQOS_5_1 not set */ + /* DBSC_DBSCHQOS_5_2 not set */ + /* DBSC_DBSCHQOS_5_3 not set */ + /* DBSC_DBSCHQOS_6_0 not set */ + /* DBSC_DBSCHQOS_6_1 not set */ + /* DBSC_DBSCHQOS_6_2 not set */ + /* DBSC_DBSCHQOS_6_3 not set */ + /* DBSC_DBSCHQOS_7_0 not set */ + /* DBSC_DBSCHQOS_7_1 not set */ + /* DBSC_DBSCHQOS_7_2 not set */ + /* DBSC_DBSCHQOS_7_3 not set */ + /* DBSC_DBSCHQOS_8_0 not set */ + /* DBSC_DBSCHQOS_8_1 not set */ + /* DBSC_DBSCHQOS_8_2 not set */ + /* DBSC_DBSCHQOS_8_3 not set */ + io_write_32(DBSC_DBSCHQOS_9_0, 0x00000100U); + io_write_32(DBSC_DBSCHQOS_9_1, 0x000000F0U); + io_write_32(DBSC_DBSCHQOS_9_2, 0x000000A0U); + io_write_32(DBSC_DBSCHQOS_9_3, 0x00000040U); + /* DBSC_DBSCHQOS_10_0 not set */ + /* DBSC_DBSCHQOS_10_1 not set */ + /* DBSC_DBSCHQOS_10_2 not set */ + /* DBSC_DBSCHQOS_10_3 not set */ + /* DBSC_DBSCHQOS_11_0 not set */ + /* DBSC_DBSCHQOS_11_1 not set */ + /* DBSC_DBSCHQOS_11_2 not set */ + /* DBSC_DBSCHQOS_11_3 not set */ + io_write_32(DBSC_DBSCHQOS_12_0, 0x00000100U); + io_write_32(DBSC_DBSCHQOS_12_1, 0x000000F0U); + io_write_32(DBSC_DBSCHQOS_12_2, 0x000000A0U); + io_write_32(DBSC_DBSCHQOS_12_3, 0x00000040U); + io_write_32(DBSC_DBSCHQOS_13_0, 0x00000100U); + io_write_32(DBSC_DBSCHQOS_13_1, 0x000000F0U); + io_write_32(DBSC_DBSCHQOS_13_2, 0x000000A0U); + io_write_32(DBSC_DBSCHQOS_13_3, 0x00000040U); + io_write_32(DBSC_DBSCHQOS_14_0, 0x000000C0U); + io_write_32(DBSC_DBSCHQOS_14_1, 0x000000B0U); + io_write_32(DBSC_DBSCHQOS_14_2, 0x00000080U); + io_write_32(DBSC_DBSCHQOS_14_3, 0x00000040U); + io_write_32(DBSC_DBSCHQOS_15_0, 0x00000040U); + io_write_32(DBSC_DBSCHQOS_15_1, 0x00000030U); + io_write_32(DBSC_DBSCHQOS_15_2, 0x00000020U); + io_write_32(DBSC_DBSCHQOS_15_3, 0x00000010U); + + /* Register write protect */ + io_write_32(DBSC_DBSYSCNT0, 0x00000000U); + +} +/* End of function dbsc_setting */ + +void qos_init_v3m(void) +{ + + dbsc_setting(); + + NOTICE("CR7: QoS is default setting(%s)\n", RCAR_QOS_VERSION); + +#if RCAR_REF_INT == RCAR_REF_DEFAULT + NOTICE("DRAM refresh interval 3.9 usec\n"); +#elif RCAR_REF_INT == RCAR_REF_7800 + NOTICE("DRAM refresh interval 7.8 usec\n"); +#elif RCAR_REF_INT == RCAR_REF_1950 + NOTICE("DRAM refresh interval 1.95 usec\n"); +#endif + + /* Resource Alloc setting */ + io_write_32(RALLOC_RAS, 0x00000020U); + /* RALLOC_FIXTH is not set */ + /* RegGuard is not set */ + io_write_64(RALLOC_DANN, 0x0404020002020201U); + io_write_32(RALLOC_DANT, 0x00100804U); + /* RALLOC_EC is not set */ + /* RALLOC_EMS is not set */ + io_write_32(RALLOC_INSFC, 0x6330001U); + /* BERR is not set */ + + /* MSTAT setting */ +#if ((RCAR_REF_INT == RCAR_REF_DEFAULT) || (RCAR_REF_INT == RCAR_REF_1950)) + /* REF 3.9usec */ + io_write_32(MSTAT_SL_INIT, 0x030500AEU); + io_write_32(MSTAT_REF_ARS, 0x00A90000U); +#else /* REF 7.8usec */ + io_write_32(MSTAT_SL_INIT, 0x0305015DU); + io_write_32(MSTAT_REF_ARS, 0x01580000U); +#endif + + /* MSTAT SRAM setting */ + { + uint32_t i; + + for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) + { + io_write_64(MSTAT_FIX_QOS_BANK0 + mstat_fix[i].addr, + mstat_fix[i].value); + io_write_64(MSTAT_FIX_QOS_BANK1 + mstat_fix[i].addr, + mstat_fix[i].value); + } + for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) + { + io_write_64(MSTAT_BE_QOS_BANK0 + mstat_be[i].addr, + mstat_be[i].value); + io_write_64(MSTAT_BE_QOS_BANK1 + mstat_be[i].addr, + mstat_be[i].value); + } + } + + /* AXI-IF arbitration setting */ + /* AXARB is not set */ + + /* Resource Alloc start */ + io_write_32(RALLOC_RAEN, 0x00000001U); + + /* MSTAT start */ + io_write_32(MSTAT_STATQC, 0x00000001U); + + io_write_32(CPU_ACT0, 0x00000003U); + io_write_32(CPU_ACT1, 0x00000003U); + io_write_32(RALLOC_FSS, 0x0000000AU); + io_write_32(RALLOC_RACNT0, 0x00010003U); + io_write_32(AXI_MMCR, 0x00000000U); +} +/* End of function qos_init_v3m */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/V3M/qos_init_v3m.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/V3M/qos_init_v3m.h new file mode 100644 index 0000000..539e53e --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/V3M/qos_init_v3m.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef QOS_INIT_H_V3M__ +#define QOS_INIT_H_V3M__ + +void qos_init_v3m(void); + +#endif /* QOS_INIT_H_V3M__ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/qos.mk b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/qos.mk new file mode 100644 index 0000000..cbb0289 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/qos.mk @@ -0,0 +1,7 @@ +# +# Copyright (c) 2015-2019, Renesas Electronics Corporation +# All rights reserved. +# + +OBJ_FILE += qos/V3M/qos_init_v3m.o \ + qos/qos_init.o diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/qos_init.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/qos_init.c new file mode 100644 index 0000000..4721b69 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/qos_init.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/****************************************************************************** + * @file qos_init.c + * - Version : 0.01 + * @brief Initial setting process of QoS. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.05.2020 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include "qos_init.h" +#include "V3M/qos_init_v3m.h" + +void qos_init(void) +{ + qos_init_v3m(); +} +/* End of function qos_init */ + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/qos_init.h b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/qos_init.h new file mode 100644 index 0000000..2e9a993 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/qos/qos_init.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation + * All rights reserved. + */ + +#ifndef QOS_INIT_H_ +#define QOS_INIT_H_ + +extern void qos_init(void); + +#endif /* QOS_INIT_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/tools/dummy_create/sa0.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/tools/dummy_create/sa0.c new file mode 100644 index 0000000..3e3ad07 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/tools/dummy_create/sa0.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation + * All rights reserved. + */ + +/* SA0 */ +/* 0x00000000 */ +const unsigned int __attribute__ ((section (".sa0_bootrom"))) bootrom_paramA = 0x00000100U; +/* 0x00000C00*/ +/* 0x00000D54 */ +const unsigned int __attribute__ ((section (".sa0_cert_addr1"))) cert_addr1 = 0xE6304000U; +/* 0x00000E64 */ +const unsigned int __attribute__ ((section (".sa0_cert_size1"))) cert_size1 = 0x00008000U; + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/tools/dummy_create/sa0.ld.S b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/tools/dummy_create/sa0.ld.S new file mode 100644 index 0000000..b699194 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/tools/dummy_create/sa0.ld.S @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +SECTIONS +{ + . = 0x00000000; + .rodata : { + KEEP(*(.sa0_bootrom)) + /* A-side IPL "Start Address" */ + . = 0x00000D54; /* H'00000C00 + H'00000154 */ + KEEP(*(.sa0_cert_addr1)) + /* A-side IPL "Size" */ + . = 0x00000E64; /* H'00000C00 + H'00000264 */ + KEEP(*(.sa0_cert_size1)) + } + +} diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/tools/dummy_create/sa3.c b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/tools/dummy_create/sa3.c new file mode 100644 index 0000000..18a2c60 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/tools/dummy_create/sa3.c @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +/* SA3 */ +/* 0x000C0154 */ +const unsigned int __attribute__ ((section (".sa3_rtos_addr"))) rtos_addr = 0x42220800; +/* 0x000C0264 */ +const unsigned int __attribute__ ((section (".sa3_rtos_size"))) rtos_size = 0x00008000; +/* 0x000C0954 */ +const unsigned int __attribute__ ((section (".sa3_loader_addr"))) sa3_loader_addr = 0x46400000; +/* 0x000C0A64 */ +const unsigned int __attribute__ ((section (".sa3_loader_size"))) sa3_loader_size = 0x00008000; +/* 0x000C1154 */ +const unsigned int __attribute__ ((section (".sa3_uboot_addr"))) uboot_addr = 0x50000000; +/* 0x000C1264 */ +const unsigned int __attribute__ ((section (".sa3_uboot_size"))) uboot_size = 0x00040000; + diff --git a/IPL/SDK/v3m/src/V3M_CortexR7_Loader/tools/dummy_create/sa3.ld.S b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/tools/dummy_create/sa3.ld.S new file mode 100644 index 0000000..1448525 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_CortexR7_Loader/tools/dummy_create/sa3.ld.S @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2015-2021, Renesas Electronics Corporation + * All rights reserved. + */ + +SECTIONS +{ + . = 0x00000000; + .rodata : { + . = 0x00000154; + KEEP(*(.sa3_rtos_addr)) + . = 0x00000264; + KEEP(*(.sa3_rtos_size)) + . = 0x00000954; + KEEP(*(.sa3_loader_addr)) + . = 0x00000A64; + KEEP(*(.sa3_loader_size)) + . = 0x00001154; + KEEP(*(.sa3_uboot_addr)) + . = 0x00001264; + KEEP(*(.sa3_uboot_size)) + } + +} diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/Makefile b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/Makefile new file mode 100644 index 0000000..3eadcc1 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/Makefile @@ -0,0 +1,116 @@ +################################################### +# makefile +################################################### + +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +INCLUDE_DIR = -Iinclude + +#output file name +FILE_NAME = dummy_rtos + +OUTPUT_FILE = $(FILE_NAME).elf + +OUTPUT_DIR = output +OBJECT_DIR = obj + +#object file name +OBJ_FILE = common/scif.o \ + common/div.o \ + common/printf.o \ + common/micro_wait.o \ + rtos/rtos.o \ + rtos/rtos_main.o +# rtos/rtos_main2.o \ +# rtos/rtos_main3.o \ +# rtos/rtos_main4.o \ +# rtos/rtos_main5.o \ +# rtos/rtos_main6.o + + +#linker script name +MEMORY_DEF = rtos/rtos.ld.S + +################################################### +# Process LOG_LEVEL flag +ifndef LOG_LEVEL +LOG_LEVEL := 20 +endif +$(eval $(call add_define,LOG_LEVEL)) + +################################################### + +CC = $(CROSS_COMPILE)gcc +CPP = ${CROSS_COMPILE}cpp +AS = ${CROSS_COMPILE}gcc +AR = ${CROSS_COMPILE}ar +LD = $(CROSS_COMPILE)ld +OC = ${CROSS_COMPILE}objcopy +OD = ${CROSS_COMPILE}objdump + +ASFLAGS = -marm -march=armv7-r \ + -nostdinc -ffreestanding -Wa,--fatal-warnings \ + -Werror -Wmissing-include-dirs \ + -c -D__ASSEMBLY \ + $(INCLUDE_DIR) $(DEFINES) + +CFLAGS = -marm -march=armv7-r \ + -nostdinc -ffreestanding -Wall \ + -Werror -Wmissing-include-dirs \ + -std=c99 -c -Os \ + -ffunction-sections -fdata-sections \ + $(INCLUDE_DIR) $(DEFINES) + +CFLAGS += -g +ASFLAGS += -g -Wa,--gdwarf-2 + +LDFLAGS = --fatal-warnings -O1 --gc-sections + +################################################### +.SUFFIXES : .s .c .o + +################################################### +# command + +.PHONY: all +all: $(OBJECT_DIR) $(OUTPUT_DIR) $(OUTPUT_FILE) +################################################### +# Make Directory +################################################### +$(OBJECT_DIR): + mkdir -p $(OBJECT_DIR) + +$(OUTPUT_DIR): + mkdir -p $(OUTPUT_DIR) + +################################################### +# Linker +################################################### +$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE) + $(LD) $(OBJ_FILE) \ + -T $(MEMORY_DEF) \ + -o $(OUTPUT_FILE) \ + $(LDFLAGS) \ + -Map $(FILE_NAME).map + + $(OC) -O srec --srec-forceS3 $(OUTPUT_FILE) $(FILE_NAME).srec + $(OC) -O binary $(OUTPUT_FILE) $(FILE_NAME).bin + $(OD) -dx $(OUTPUT_FILE) > $(FILE_NAME).dump + + +################################################### +# Compile +################################################### + +%.o:../%.c + $(CC) $(CFLAGS) -o $@ $< + +%.o:../%.s + $(AS) $(ASFLAGS) -o $@ $< + + +.PHONY: clean +clean: + $(RM) $(OBJ_FILE) $(OUTPUT_FILE) $(FILE_NAME).* diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/common/div.s b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/common/div.s new file mode 100644 index 0000000..b6f4113 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/common/div.s @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + .global __aeabi_uidivmod + +/***************************************************************************** + * input: + * r0: divided + * r1: divisor + * + * output + * r0: quot + * r1: rem + *****************************************************************************/ + +__aeabi_uidivmod: + push {r4, r5} + mov r4, #0 + mov r5, #1 + + clz r2, r1 + mov r3, r1, LSL r2 +1: + cmp r3, r0 + subls r0, r0, r3 + addls r4, r5, LSL r2 + + lsr r3, r3, #1 + subs r2, r2, #1 + bpl 1b + + mov r1, r0 + mov r0, r4 + + pop {r4, r5} + bx lr + + .end diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/common/micro_wait.c b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/common/micro_wait.c new file mode 100644 index 0000000..da8745a --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/common/micro_wait.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include "debug.h" +#include "micro_wait.h" + +#define GLOBAL_TIMER_COUNT_L (0xF0000200U) +#define GLOBAL_TIMER_COUNT_U (0xF0000204U) +#define GLOBAL_TIMER_CONTROL_REG (0xF0000208U) +#define GLOBAL_TIMER_EN (0x1U) +/* In case of Prescaler is 0, Global Timer is 200 MHz. */ +#define GLOBAL_TIMER_CLOCK (200U) + +#define UPPER_SHIFT (32U) + +void micro_wait_init(void) +{ + mmio_write_32(GLOBAL_TIMER_CONTROL_REG, GLOBAL_TIMER_EN); +} + +void micro_wait(uint64_t count_us) +{ + uint64_t count_init; + uint64_t count = 0; + uint64_t loop_num; + + count_init = mmio_read_32(GLOBAL_TIMER_COUNT_U); + count_init = count_init << UPPER_SHIFT; + count_init += mmio_read_32(GLOBAL_TIMER_COUNT_L); + loop_num = count_us * GLOBAL_TIMER_CLOCK; + + while( loop_num > count){ + count = mmio_read_32(GLOBAL_TIMER_COUNT_U); + count = count << UPPER_SHIFT; + count += mmio_read_32(GLOBAL_TIMER_COUNT_L); + count -= count_init; + } +} + diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/common/printf.c b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/common/printf.c new file mode 100644 index 0000000..2e63ac0 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/common/printf.c @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "debug.h" +#include "scif.h" + + +static uint32_t uint32_print(uint32_t num) +{ + uint8_t num_buf[10]; + uint32_t count = 0U; + uint32_t i = 0U; + uint32_t rem; + uint32_t unum = num; + + while(1) { + rem = unum % 10U; + if (rem < 0x0AU) { + num_buf[i] = '0' + rem; + } else { + num_buf[i] = 'a' + (rem - 0xa); + } + i++; + unum = unum / 10U; + if (unum < 1U ) { + break; + } + } + + while (i != 0U) { + i--; + (void)console_putc(num_buf[i]); + count++; + }; + + return count; +} + + +static uint32_t int32_print(int32_t num) +{ + uint32_t unum; + uint32_t count = 0U; + + if (num < 0) { + console_putc('-'); + count = 1U; + unum = (uint32_t)-num; + } else { + unum = (uint32_t)num; + } + + count += uint32_print(unum); + + return count; +} + + +static uint32_t uint32_hex_print(uint32_t num) +{ + uint32_t i; + uint32_t count = 0U; + uint8_t c; + + for (i = 0U; i < 8U; i++) { + c = (uint8_t)((num >> ((7U - i) * 4)) & 0x0FU); /* 0-F */ + if ( c >= 0x0AU) { + c += 'a' - 0x0AU; /* A-F */ + } else { + c += '0'; /* 0-9 */ + } + (void)console_putc(c); + count++; + } + + return count; +} + + +static uint32_t str_print(const char *str) +{ + uint32_t count = 0; + + while (*str) { + (void)console_putc(*str); + str++; + count++; + } + + return count; +} + + +void tf_printf(const char *format, ...) +{ + va_list args; + int32_t num; + uint32_t unum; + char *str; + uint32_t count = 0U; + + va_start(args, format); + while (*format) { + if (*format == '%') { + format++; + switch (*format) { + case 'i': + case 'd': + num = va_arg(args, int32_t); + count += int32_print(num); + break; + case 's': + str = va_arg(args, char *); + count += str_print(str); + break; + case 'x': + unum = va_arg(args, uint32_t); + count += uint32_hex_print(unum); + break; + case 'u': + unum = va_arg(args, uint32_t); + count += uint32_print(unum); + break; + default: + break; + } + } else { + (void)console_putc(*format); + count++; + } + format++; + } + va_end(args); +} diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/common/scif.S b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/common/scif.S new file mode 100644 index 0000000..6d882b3 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/common/scif.S @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +//#include +//#include +#include + +/* Product Register */ +#define PRR (0xFFF00044) +#define PRR_PRODUCT_MASK (0x00007FFF) +#define PRR_PRODUCT_H3_ES_1_0 (0x00004F00) /* R-Car H3 ES1.0 */ + + + .global console_init + .global console_putc + .global console_wait + +console_init: + ldr r0, =CPG_BASE + ldr r1, [r0, #CPG_RMSTPCR2] + and r1, r1, #~MSTP207 /* MSTP207=0 */ + mvn r2, r1 + str r2, [r0, #CPG_CPGWPR] + str r1, [r0, #CPG_RMSTPCR2] +4: + ldr r1, [r0, #CPG_MSTPSR2] + and r1, r1, #MSTP207 + cmp r1, #0 + bne 4b +#if 0 + ldr r1, [r0, #CPG_SMSTPCR3] + and r1, r1, #~MSTP310 /* MSTP310=0 */ + mvn r2, r1 + str r2, [r0, #CPG_CPGWPR] + str r1, [r0, #CPG_SMSTPCR3] + + ldr r0, =PFC_BASE + ldr r1, [r0, #MOD_SEL1] + and r1, r1, #~MOD_SEL1_SCIF2_MASK + mvn r2, r1 + str r2, [r0, #PMMR] + str r1, [r0, #MOD_SEL1] + + ldr r1, [r0, #IPSR12] + and r1, r1, #~IPSR12_MASK + mov r2, #IPSR12_INIT_DATA /* IP12[7:4]=H'0, IP12[3:0]=H'0 */ + orr r1, r1, r2 + mvn r2, r1 + str r2, [r0, #PMMR] + str r1, [r0, #IPSR12] + + ldr r1, [r0, #GPSR5] + and r1, r1, #~GPSR5_MASK /* GP2[12]=Peripheral function selected by IP4[23:22] */ + orr r1, r1, #GPSR5_INIT_DATA /* GP2[13]=Peripheral function selected by IP4[25:24] */ + mvn r2, r1 + str r2, [r0, #PMMR] + str r1, [r0, #GPSR5] +#endif + ldr r0, =SCIF_BASE + mov r1, #0 + strh r1, [r0, #SCIF_SCSMRIR] + /* Clear bits TE and RE in SCSCR to 0 */ + mov r1, #(SCSCR_TE_DIS + SCSCR_RE_DIS) /* TE=0,RE=0 */ + strh r1, [r0, #SCIF_SCSCR] + /* Set bits TFRST and RFRST in SCFCR to 1 */ + ldrh r1, [r0, #SCIF_SCFCR] + orr r1, r1, #(SCFCR_TFRST_EN + SCFCR_RFRS_EN) /* TFRESET=1,RFRESET=1 */ + strh r1, [r0, #SCIF_SCFCR] + /* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER in SCLSR, then clear them to 0 */ + mov r1, #SCFSR_INIT_DATA + strh r1, [r0, #SCIF_SCFSR] + mov r1, #0 + strh r1, [r0, #SCIF_SCLSR] + /* Set bits CKE[1:0] in SCSCR */ + ldrh r1, [r0, #SCIF_SCSCR] + and r1, r1, #~SCSCR_CKE_MASK + mov r2, #SCSCR_CKE_INT_CLK /* CKE=00 */ + orr r1, r1, r2 + strh r1, [r0, #SCIF_SCSCR] + /* Set data transfer format in SCSMR */ + mov r1, #SCSMR_INIT_DATA + strh r1, [r0, #SCIF_SCSMR] /* CA=0,CHR=0,PE=0,STOP=0,CKS=P */ + /* Set value in SCBRR */ +#if SCIF_CLK == SCIF_INTERNAL_CLK + ldr r1, =PRR + ldr r1, [r1] + ldr r2, =PRR_PRODUCT_MASK + and r1, r1, r2 + mov r2, #PRR_PRODUCT_H3_ES_1_0 + cmp r1, r2 + beq 3f + mov r1, #SCBRR_115200BPS /* 115200bps */ + b 2f +3: + mov r1, #SCBRR_230400BPS /* H3 ES1.0 sets clock to doubling */ +2: + strb r1, [r0, #SCIF_SCBRR] +#else + mov r1, #DL_INIT_DATA + strh r1, [r0, #SCIF_DL] + mov r1, #CKS_INIT_DATA /* CKS=0,XIN=0 */ + strh r1, [r0, #SCIF_CKS] +#endif + /* 1-bit interval elapsed */ + mov r1, #100 /* 100 times */ +1: + subs r1, r1, #1 + bne 1b + /* Set bits RTRG[1:0], TTRG[1:0], and MCE in SCFCR, and clear bits FRST and RFRST to 0 */ + mov r1, #SCFCR_INIT_DATA + strh r1, [r0, #SCIF_SCFCR] + /* Set bits TE and RE in SCSCR to 1 */ + ldrh r1, [r0, #SCIF_SCSCR] + orr r1, r1, #(SCSCR_TE_EN + SCSCR_RE_EN) /* TE=1,RE=1 */ + strh r1, [r0, #SCIF_SCSCR] + mov r1, #1 + + bx lr + + +console_putc: + ldr r1, =SCIF_BASE + cmp r0, #0xA + /* Prepend '\r' to '\n' */ + bne 2f +1: + /* Check if the transmit FIFO is full */ + ldrh r2, [r1, #SCIF_SCFDR] + ubfx r2, r2, #8, #5 + cmp r2, #16 + bcs 1b + mov r2, #0x0D + strb r2, [r1, #SCIF_SCFTDR] +2: + /* Check if the transmit FIFO is full */ + ldrh r2, [r1, #SCIF_SCFDR] + ubfx r2, r2, #8, #5 + cmp r2, #16 + bcs 2b + strb r0, [r1, #SCIF_SCFTDR] + + bx lr + + +console_wait: + ldr r1, =SCIF_BASE +1: + ldrh r2, [r1, #SCIF_SCFDR] + ubfx r2, r2, #8, #5 + cmp r2, #0 + bne 1b + + bx lr + + + .end diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/debug.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/debug.h new file mode 100644 index 0000000..db31217 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/debug.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +#include + +/* The log output macros print output to the console. These macros produce + * compiled log output only if the LOG_LEVEL defined in the makefile (or the + * make command line) is greater or equal than the level required for that + * type of log output. + * The format expected is the same as for printf(). For example: + * INFO("Info %s.\n", "message") -> INFO: Info message. + * WARN("Warning %s.\n", "message") -> WARNING: Warning message. + */ + +#define LOG_LEVEL_NONE 0 +#define LOG_LEVEL_ERROR 10 +#define LOG_LEVEL_NOTICE 20 +#define LOG_LEVEL_WARNING 30 +#define LOG_LEVEL_INFO 40 +#define LOG_LEVEL_VERBOSE 50 + + +#if LOG_LEVEL >= LOG_LEVEL_NOTICE +# define NOTICE(...) tf_printf("NOTICE: " __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_ERROR +# define ERROR(...) tf_printf("ERROR: " __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_WARNING +# define WARN(...) tf_printf("WARNING: " __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_INFO +# define INFO(...) tf_printf("INFO: " __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE +# define VERBOSE(...) tf_printf("VERBOSE: " __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + + +void __dead2 do_panic(void); +#define panic() do_panic() + +//void tf_printf(const char *fmt, ...) __printflike(1, 2); + +#endif /* __DEBUG_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/machine/_stdint.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/machine/_stdint.h new file mode 100644 index 0000000..e36c659 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/machine/_stdint.h @@ -0,0 +1,164 @@ +/*- + * Copyright (c) 2001, 2002 Mike Barcroft + * Copyright (c) 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Klaus Klein. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE__STDINT_H_ +#define _MACHINE__STDINT_H_ + +#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) + +#define INT8_C(c) (c) +#define INT16_C(c) (c) +#define INT32_C(c) (c) +#define INT64_C(c) (c ## L) + +#define UINT8_C(c) (c) +#define UINT16_C(c) (c) +#define UINT32_C(c) (c ## U) +#define UINT64_C(c) (c ## UL) + +#define INTMAX_C(c) INT64_C(c) +#define UINTMAX_C(c) UINT64_C(c) + +#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */ + +#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) + +/* + * ISO/IEC 9899:1999 + * 7.18.2.1 Limits of exact-width integer types + */ +/* Minimum values of exact-width signed integer types. */ +#define INT8_MIN (-0x7f-1) +#define INT16_MIN (-0x7fff-1) +#define INT32_MIN (-0x7fffffff-1) +#define INT64_MIN (-0x7fffffffffffffffL-1) + +/* Maximum values of exact-width signed integer types. */ +#define INT8_MAX 0x7f +#define INT16_MAX 0x7fff +#define INT32_MAX 0x7fffffff +#define INT64_MAX 0x7fffffffffffffffL + +/* Maximum values of exact-width unsigned integer types. */ +#define UINT8_MAX 0xff +#define UINT16_MAX 0xffff +#define UINT32_MAX 0xffffffffU +#define UINT64_MAX 0xffffffffffffffffUL + +/* + * ISO/IEC 9899:1999 + * 7.18.2.2 Limits of minimum-width integer types + */ +/* Minimum values of minimum-width signed integer types. */ +#define INT_LEAST8_MIN INT8_MIN +#define INT_LEAST16_MIN INT16_MIN +#define INT_LEAST32_MIN INT32_MIN +#define INT_LEAST64_MIN INT64_MIN + +/* Maximum values of minimum-width signed integer types. */ +#define INT_LEAST8_MAX INT8_MAX +#define INT_LEAST16_MAX INT16_MAX +#define INT_LEAST32_MAX INT32_MAX +#define INT_LEAST64_MAX INT64_MAX + +/* Maximum values of minimum-width unsigned integer types. */ +#define UINT_LEAST8_MAX UINT8_MAX +#define UINT_LEAST16_MAX UINT16_MAX +#define UINT_LEAST32_MAX UINT32_MAX +#define UINT_LEAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.3 Limits of fastest minimum-width integer types + */ +/* Minimum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MIN INT32_MIN +#define INT_FAST16_MIN INT32_MIN +#define INT_FAST32_MIN INT32_MIN +#define INT_FAST64_MIN INT64_MIN + +/* Maximum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MAX INT32_MAX +#define INT_FAST16_MAX INT32_MAX +#define INT_FAST32_MAX INT32_MAX +#define INT_FAST64_MAX INT64_MAX + +/* Maximum values of fastest minimum-width unsigned integer types. */ +#define UINT_FAST8_MAX UINT32_MAX +#define UINT_FAST16_MAX UINT32_MAX +#define UINT_FAST32_MAX UINT32_MAX +#define UINT_FAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.4 Limits of integer types capable of holding object pointers + */ +#define INTPTR_MIN INT64_MIN +#define INTPTR_MAX INT64_MAX +#define UINTPTR_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.5 Limits of greatest-width integer types + */ +#define INTMAX_MIN INT64_MIN +#define INTMAX_MAX INT64_MAX +#define UINTMAX_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.3 Limits of other integer types + */ +/* Limits of ptrdiff_t. */ +#define PTRDIFF_MIN INT64_MIN +#define PTRDIFF_MAX INT64_MAX + +/* Limits of sig_atomic_t. */ +#define SIG_ATOMIC_MIN INT32_MIN +#define SIG_ATOMIC_MAX INT32_MAX + +/* Limit of size_t. */ +#define SIZE_MAX UINT64_MAX + +#ifndef WCHAR_MIN /* Also possibly defined in */ +/* Limits of wchar_t. */ +#define WCHAR_MIN INT32_MIN +#define WCHAR_MAX INT32_MAX +#endif + +/* Limits of wint_t. */ +#define WINT_MIN INT32_MIN +#define WINT_MAX INT32_MAX + +#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ + +#endif /* !_MACHINE__STDINT_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/machine/_types.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/machine/_types.h new file mode 100644 index 0000000..0f1e14e --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/machine/_types.h @@ -0,0 +1,110 @@ +/*- + * Copyright (c) 2002 Mike Barcroft + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * From: @(#)ansi.h 8.2 (Berkeley) 1/4/94 + * From: @(#)types.h 8.3 (Berkeley) 1/5/94 + * $FreeBSD$ + */ + +#ifndef _MACHINE__TYPES_H_ +#define _MACHINE__TYPES_H_ + +#ifndef _SYS_CDEFS_H_ +#error this file needs sys/cdefs.h as a prerequisite +#endif + +/* + * Basic types upon which most other types are built. + */ +typedef __signed char __int8_t; +typedef unsigned char __uint8_t; +typedef short __int16_t; +typedef unsigned short __uint16_t; +typedef int __int32_t; +typedef unsigned int __uint32_t; +typedef long long __int64_t; +typedef unsigned long long __uint64_t; + +/* + * Standard type definitions. + */ +typedef __int32_t __clock_t; /* clock()... */ +typedef __int32_t __critical_t; +typedef double __double_t; +typedef float __float_t; +typedef __int32_t __intfptr_t; +typedef __int32_t __intmax_t; +typedef __int32_t __intptr_t; +typedef __int32_t __int_fast8_t; +typedef __int32_t __int_fast16_t; +typedef __int32_t __int_fast32_t; +typedef __int32_t __int_fast64_t; +typedef __int8_t __int_least8_t; +typedef __int16_t __int_least16_t; +typedef __int32_t __int_least32_t; +typedef __int64_t __int_least64_t; +typedef __int32_t __ptrdiff_t; /* ptr1 - ptr2 */ +typedef __int32_t __register_t; +typedef __int32_t __segsz_t; /* segment size (in pages) */ +typedef __uint32_t __size_t; /* sizeof() */ +typedef __int32_t __ssize_t; /* byte count or error */ +typedef __int32_t __time_t; /* time()... */ +typedef __uint32_t __uintfptr_t; +typedef __uint64_t __uintmax_t; +typedef __uint32_t __uintptr_t; +typedef __uint32_t __uint_fast8_t; +typedef __uint32_t __uint_fast16_t; +typedef __uint32_t __uint_fast32_t; +typedef __uint64_t __uint_fast64_t; +typedef __uint8_t __uint_least8_t; +typedef __uint16_t __uint_least16_t; +typedef __uint32_t __uint_least32_t; +typedef __uint64_t __uint_least64_t; +typedef __uint32_t __u_register_t; +typedef __uint32_t __vm_offset_t; +typedef __int32_t __vm_ooffset_t; +typedef __uint32_t __vm_paddr_t; +typedef __uint32_t __vm_pindex_t; +typedef __uint32_t __vm_size_t; + +/* + * Unusual type definitions. + */ +#ifdef __GNUCLIKE_BUILTIN_VARARGS +typedef __builtin_va_list __va_list; /* internally known to gcc */ +#else +typedef char * __va_list; +#endif /* __GNUCLIKE_BUILTIN_VARARGS */ +#if defined(__GNUCLIKE_BUILTIN_VAALIST) && !defined(__GNUC_VA_LIST) \ + && !defined(__NO_GNUC_VA_LIST) +#define __GNUC_VA_LIST +typedef __va_list __gnuc_va_list; /* compatibility w/GNU headers*/ +#endif + +#endif /* !_MACHINE__TYPES_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/micro_wait.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/micro_wait.h new file mode 100644 index 0000000..7e72745 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/micro_wait.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef MICRO_WAIT_H__ +#define MICRO_WAIT_H__ + +void micro_wait_init(void); +void micro_wait(uint64_t count_us); + +#endif /* MICRO_TWAIT_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/mmio.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/mmio.h new file mode 100644 index 0000000..051adfe --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/mmio.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MMIO_H__ +#define __MMIO_H__ + +#include + +static inline void mmio_write_8(uintptr_t addr, uint8_t value) +{ + *(volatile uint8_t* )addr = value; +} + +static inline uint8_t mmio_read_8(uintptr_t addr) +{ + return *(volatile uint8_t *)addr; +} + +static inline void mmio_write_16(uintptr_t addr, uint16_t value) +{ + *(volatile uint16_t *)addr = value; +} + +static inline uint16_t mmio_read_16(uintptr_t addr) +{ + return *(volatile uint16_t *)addr; +} + +static inline void mmio_write_32(uintptr_t addr, uint32_t value) +{ + *(volatile uint32_t *)addr = value; +} + +static inline uint32_t mmio_read_32(uintptr_t addr) +{ + return *(volatile uint32_t *)addr; +} + +static inline void mmio_write_64(uintptr_t addr, uint64_t value) +{ + *(volatile uint64_t *)addr = value; +} + +static inline uint64_t mmio_read_64(uintptr_t addr) +{ + return *(volatile uint64_t *)addr; +} + +#endif /* __MMIO_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/reg_rcar_gen3.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/reg_rcar_gen3.h new file mode 100644 index 0000000..d68fd51 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/reg_rcar_gen3.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __H_REG_RCAR_GEN3_ +#define __H_REG_RCAR_GEN3_ + +/*********************** RCarGen3_MFI *************************/ +#define MFISSOFTMDR 0xE6260600 //SOFTMD register +#define MFISSHESTSR 0xE6260604 //SHE status register + +/*********************** RCarGen3_LIFEC *************************/ +#define LIFEC_CC_LCS 0xE6110028 // cc_lcs Life cycle state read + +/*********************** RCarGen3_RST *************************/ +#define RST_MODEMR 0xE6160060 // Mode Monitor Register + +/*********************** RCarGen3_DMA *************************/ +#define DMA_DMAOR 0xE6700060 //DMA operation register (for west channel) +#define DMA_CHCLR 0xE6700080 //DMA channel clear register (for west channel) +#define DMA_SAR0 0xE6708000 //DMA source address register +#define DMA_DAR0 0xE6708004 //DMA destination address register +#define DMA_TCR0 0xE6708008 //DMA transfer count register +#define DMA_CHCR0 0xE670800C //DMA channel control register +#define DMA_DMARS0 0xE6708040 //DMA extended resource register + +/*********************** RCarGen3_RPC/QSPI *************************/ +//RPC/QSPI + +#define RPC_BASE 0xEE200000 +#define RPC_CMNCR (RPC_BASE + 0x0000) // +//#define RPC_DRCR (RPC_BASE + 0x000C) // +//#define RPC_DRCMR (RPC_BASE + 0x0010) // +//#define RPC_DRENR (RPC_BASE + 0x001C) // +#define RPC_SMCR (RPC_BASE + 0x0020) // +#define RPC_SMCMR (RPC_BASE + 0x0024) // +#define RPC_SMENR (RPC_BASE + 0x0030) // +#define RPC_CMNSR (RPC_BASE + 0x0048) // +//#define RPC_DRDMCR (RPC_BASE + 0x0058) // +//#define RPC_DRDRENR (RPC_BASE + 0x005C) // +//#define RPC_PHY_OFFSET1 (RPC_BASE + 0x0080) // +#define RPC_PHY_INT (RPC_BASE + 0x0088) // + + +/*********************** RCarH3_PFC *************************/ +// 5 . PFC + +#define PFC_BASE 0xE6060000 +#define RCarH3_PFC_PMMR (PFC_BASE + 0x0000) // LSI Multiplexed Pin Setting Mask Register +#define RCarH3_PFC_GPSR5 (PFC_BASE + 0x0114) // GPIO/peripheral function select register 5 +#define RCarH3_PFC_IPSR12 (PFC_BASE + 0x0230) // Peripheral function select register 12 +#define RCarH3_PFC_MOD_SEL1 (PFC_BASE + 0x0504) // Module select register 1 + + + +/*********************** RCarH3_SCIF ****************************************************/ +// 51 . Serial Communication Interface with FIFO (SCIF) +/* H3 SCIF2 */ +#define H3_SCIF2_BASE 0xE6E88000 + +#define RCarH3_SCIF2_SCSMR (H3_SCIF2_BASE + 0x00) // 16 Serial mode register +#define RCarH3_SCIF2_SCBRR (H3_SCIF2_BASE + 0x04) // 8 Bit rate register +#define RCarH3_SCIF2_SCSCR (H3_SCIF2_BASE + 0x08) // 16 Serial control register +#define RCarH3_SCIF2_SCFTDR (H3_SCIF2_BASE + 0x0C) // 8 Transmit FIFO data register +#define RCarH3_SCIF2_SCFSR (H3_SCIF2_BASE + 0x10) // 16 Serial status register +#define RCarH3_SCIF2_SCFRDR (H3_SCIF2_BASE + 0x14) // 8 Receive FIFO data register +#define RCarH3_SCIF2_SCFCR (H3_SCIF2_BASE + 0x18) // 16 FIFO control register +#define RCarH3_SCIF2_SCFDR (H3_SCIF2_BASE + 0x1C) // 16 FIFO data count register +#define RCarH3_SCIF2_SCSPTR (H3_SCIF2_BASE + 0x20) // 16 Serial port register +#define RCarH3_SCIF2_SCLSR (H3_SCIF2_BASE + 0x24) // 16 Line status register +#define RCarH3_SCIF2_DL (H3_SCIF2_BASE + 0x30) // 16 Frequency division register +#define RCarH3_SCIF2_CKS (H3_SCIF2_BASE + 0x34) // 16 Clock Select register +#define RCarH3_SCIF2_SCFER (H3_SCIF2_BASE + 0x44) // 16 FIFO error count register + +#define RCarH3_SCIF2_SCSMRIR (H3_SCIF2_BASE + 0x40) // 16 Serial mode register + + + +/*********************** RCarH3_CPG_Module Standby, Software Reset *************************/ +// 7A . Module Standby, Software Reset + +#define H3_CPG_MSTPRST_BASE 0xE6150000 + +#define RCarH3_CPG_MSTPSR3 (H3_CPG_MSTPRST_BASE+0x0048) // Module stop status register 3 +#define RCarH3_CPG_SMSTPCR3 (H3_CPG_MSTPRST_BASE+0x013C) // System module stop control register 3 +//#define RCarH3_CPG_SRCR3 (H3_CPG_MSTPRST_BASE+0x00B8) // Software reset register 3 + +#define RCarH3_CPG_CPGWPCR (H3_CPG_MSTPRST_BASE+0x0904) // CPG Write Protect Control Register +#define RCarH3_CPG_CPGWPR (H3_CPG_MSTPRST_BASE+0x0900) // CPG Write Protect Register + + + +#endif /* __H_REG_RCAR_GEN3_ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/scif.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/scif.h new file mode 100644 index 0000000..c14dd82 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/scif.h @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SCIF_H__ +#define __SCIF_H__ + + +#define SCIF_INTERNAL_CLK 0 /* Internal clock(S3D4:66.66MHz) */ +#define SCIF_EXTARNAL_CLK 1 /* External clock(SCK2:14.7456MHz) */ +#define SCIF_CLK SCIF_EXTARNAL_CLK + +/* Pin functon */ +#if !defined PFC_BASE +#define PFC_BASE (0xE6060000) +#endif +#define PMMR (0x0000) +#define GPSR5 (0x0114) +#define IPSR12 (0x0230) +#define MOD_SEL1 (0x0504) + +/* module stop */ +#define CPG_BASE (0xE6150000) +#define CPG_SMSTPCR3 (0x013C) +#define MSTP310 (1 << 10) +#define MSTP207 (1 << 7) +#define CPG_CPGWPR (0x0900) +#define CPG_MSTPSR2 (0x0040) +#define CPG_RMSTPCR2 (0x0118) + +/* SCIF2 */ +#define SCIF2_BASE (0xE6E88000) /* SCIF-2 base address */ +#define SCIF0_BASE (0xE6E60000) /* SCIF-0 base address */ + +#define SCIF_BASE (SCIF0_BASE) + +#define SCIF_SCSMR (0x00) /* Serial mode register */ +#define SCIF_SCBRR (0x04) /* Bit rate register */ +#define SCIF_SCSCR (0x08) /* Serial control register */ +#define SCIF_SCFTDR (0x0C) /* Transmit FIFO data register */ +#define SCIF_SCFSR (0x10) /* Serial status register */ +#define SCIF_SCFRDR (0x14) /* Receive FIFO data register */ +#define SCIF_SCFCR (0x18) /* FIFO control register */ +#define SCIF_SCFDR (0x1C) /* FIFO data count register */ +#define SCIF_SCSPTR (0x20) /* Serial port register */ +#define SCIF_SCLSR (0x24) /* Line status register */ +#define SCIF_DL (0x30) /* Frequency division register */ +#define SCIF_CKS (0x34) /* Clock Select register */ +#define SCIF_SCSMRIR (0x40) /* Serial mode register */ + + +#define SCSMR_CA_MASK (1 << 7) +#define SCSMR_CA_ASYNC (0x0000) +#define SCSMR_CHR_MASK (1 << 6) +#define SCSMR_CHR_8 (0x0000) +#define SCSMR_PE_MASK (1 << 5) +#define SCSMR_PE_DIS (0x0000) +#define SCSMR_STOP_MASK (1 << 3) +#define SCSMR_STOP_1 (0x0000) +#define SCSMR_CKS_MASK (3 << 0) +#define SCSMR_CKS_DIV1 (0x0000) +#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + SCSMR_CHR_8 + \ + SCSMR_PE_DIS + SCSMR_STOP_1 + \ + SCSMR_CKS_DIV1) + +#define SCBRR_115200BPS (17) /* 115200bps@66MHz */ +#define SCBRR_INIT_DATA (SCBRR_115200BPS) + +#define SCSCR_TE_MASK (1 << 5) +#define SCSCR_TE_DIS (0x0000) +#define SCSCR_TE_EN (0x0020) +#define SCSCR_RE_MASK (1 << 4) +#define SCSCR_RE_DIS (0x0000) +#define SCSCR_RE_EN (0x0010) +#define SCSCR_CKE_MASK (3 << 0) +#define SCSCR_CKE_INT (0x0000) +#define SCSCR_CKE_BRG (0x0002) +#if SCIF_CLK == SCIF_EXTARNAL_CLK +#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG) +#else +#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT) +#endif + +#define SCFSR_INIT_DATA (0x0000) + +#define SCFCR_TTRG_MASK (3 << 4) +#define SCFCR_TTRG_8 (0x0000) +#define SCFCR_TTRG_0 (0x0030) +#define SCFCR_TFRST_MASK (1 << 2) +#define SCFCR_TFRST_DIS (0x0000) +#define SCFCR_TFRST_EN (0x0004) +#define SCFCR_RFRS_MASK (1 << 1) +#define SCFCR_RFRS_DIS (0x0000) +#define SCFCR_RFRS_EN (0x0002) +#define SCFCR_INIT_DATA (SCFCR_TTRG_8) + +#define SCFDR_T_MASK (0x1f << 8) + +#define DL_INIT_DATA (8) /* 14.7456MHz/(115200bps*16)*/ + +#define CKS_CKS_DIV_MASK (1 << 15) +#define CKS_CKS_DIV_CLK (0x0000) +#define CKS_XIN_MASK (1 << 14) +#define CKS_XIN_SCIF_CLK (0x0000) +#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK) + +#define GPSR5_MASK (3 << 10) +#define GPSR5_RX2_A (1 << 11) +#define GPSR5_TX2_A (1 << 10) +#define GPSR5_SCK2 (1 << 9) +#if SCIF_CLK == SCIF_EXTARNAL_CLK +#define GPSR5_INIT_DATA (GPSR5_RX2_A + GPSR5_TX2_A + GPSR5_SCK2) +#else +#define GPSR5_INIT_DATA (GPSR5_RX2_A + GPSR5_TX2_A) +#endif + +#define IPSR12_MASK (255 << 0) +#define IPSR12_RX2_A (0 << 4) +#define IPSR12_TX2_A (0 << 0) +#define IPSR12_INIT_DATA (IPSR12_RX2_A + IPSR12_TX2_A) + +#define MOD_SEL1_SCIF2_MASK (1 << 12) +#define MOD_SEL1_SCIF2 (0 << 12) + +#ifndef __ASSEMBLY +uint32_t console_init(void); +uint32_t console_putc(uint8_t c); +#endif /* __ASSEMBLY */ + + +#endif /* __SCIF_H__ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/stdarg.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/stdarg.h new file mode 100644 index 0000000..c315dfc --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/stdarg.h @@ -0,0 +1,75 @@ +/*- + * Copyright (c) 2002 David E. O'Brien. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_STDARG_H_ +#define _MACHINE_STDARG_H_ + +#include +#include + +#ifndef _VA_LIST_DECLARED +#define _VA_LIST_DECLARED +typedef __va_list va_list; +#endif + +#ifdef __GNUCLIKE_BUILTIN_STDARG + +#define va_start(ap, last) \ + __builtin_va_start((ap), (last)) + +#define va_arg(ap, type) \ + __builtin_va_arg((ap), type) + +#define __va_copy(dest, src) \ + __builtin_va_copy((dest), (src)) + +#if __ISO_C_VISIBLE >= 1999 +#define va_copy(dest, src) \ + __va_copy(dest, src) +#endif + +#define va_end(ap) \ + __builtin_va_end(ap) + +#elif defined(lint) +/* Provide a fake implementation for lint's benefit */ +#define __va_size(type) \ + (((sizeof(type) + sizeof(long) - 1) / sizeof(long)) * sizeof(long)) +#define va_start(ap, last) \ + ((ap) = (va_list)&(last) + __va_size(last)) +#define va_arg(ap, type) \ + (*(type *)((ap) += __va_size(type), (ap) - __va_size(type))) +#define va_end(ap) + +#else +#error this file needs to be ported to your compiler +#endif + +#endif /* !_MACHINE_STDARG_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/stddef.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/stddef.h new file mode 100644 index 0000000..ea88214 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/stddef.h @@ -0,0 +1,64 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stddef.h 8.1 (Berkeley) 6/2/93 + * + * $FreeBSD$ + */ + +#ifndef _STDDEF_H_ +#define _STDDEF_H_ + +#include +#include +#include + +typedef __ptrdiff_t ptrdiff_t; + +#if __BSD_VISIBLE +#ifndef _RUNE_T_DECLARED +typedef __rune_t rune_t; +#define _RUNE_T_DECLARED +#endif +#endif + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#ifndef __cplusplus +#ifndef _WCHAR_T_DECLARED +typedef __wchar_t wchar_t; +#define _WCHAR_T_DECLARED +#endif +#endif + +#define offsetof(type, member) __offsetof(type, member) + +#endif /* _STDDEF_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/stdint.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/stdint.h new file mode 100644 index 0000000..aa5ac81 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/stdint.h @@ -0,0 +1,74 @@ +/*- + * Copyright (c) 2001 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS_STDINT_H_ +#define _SYS_STDINT_H_ + +#include +#include + +#include +#include + +typedef __int_least8_t int_least8_t; +typedef __int_least16_t int_least16_t; +typedef __int_least32_t int_least32_t; +typedef __int_least64_t int_least64_t; + +typedef __uint_least8_t uint_least8_t; +typedef __uint_least16_t uint_least16_t; +typedef __uint_least32_t uint_least32_t; +typedef __uint_least64_t uint_least64_t; + +typedef __int_fast8_t int_fast8_t; +typedef __int_fast16_t int_fast16_t; +typedef __int_fast32_t int_fast32_t; +typedef __int_fast64_t int_fast64_t; + +typedef __uint_fast8_t uint_fast8_t; +typedef __uint_fast16_t uint_fast16_t; +typedef __uint_fast32_t uint_fast32_t; +typedef __uint_fast64_t uint_fast64_t; + +#ifndef _INTMAX_T_DECLARED +typedef __intmax_t intmax_t; +#define _INTMAX_T_DECLARED +#endif +#ifndef _UINTMAX_T_DECLARED +typedef __uintmax_t uintmax_t; +#define _UINTMAX_T_DECLARED +#endif + +/* GNU and Darwin define this and people seem to think it's portable */ +#if defined(UINTPTR_MAX) && defined(UINT64_MAX) && (UINTPTR_MAX == UINT64_MAX) +#define __WORDSIZE 64 +#else +#define __WORDSIZE 32 +#endif + +#endif /* !_SYS_STDINT_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/stdio.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/stdio.h new file mode 100644 index 0000000..57e5c7f --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/stdio.h @@ -0,0 +1,78 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stdio.h 8.5 (Berkeley) 4/29/95 + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2013-2014, ARM Limited and Contributors. + * All rights reserved. + */ + + +#ifndef _STDIO_H_ +#define _STDIO_H_ + +#include +#include +#include + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#ifndef _SSIZE_T_DECLARED +#define _SSIZE_T_DECLARED +typedef __ssize_t ssize_t; +#endif + +#define EOF (-1) + +int printf(const char * __restrict, ...) __printflike(1, 2); +int putchar(int); +int puts(const char *); +int sprintf(char * __restrict, const char * __restrict, ...) + __printflike(2, 3); +int vsprintf(char * __restrict, const char * __restrict, + __va_list) __printflike(2, 0); + +int sscanf(const char *__restrict, char const *__restrict, ...); + +#if __ISO_C_VISIBLE >= 1999 +int snprintf(char * __restrict, size_t, const char * __restrict, + ...) __printflike(3, 4); +int vsnprintf(char * __restrict, size_t, const char * __restrict, + __va_list) __printflike(3, 0); +#endif + +#endif /* !_STDIO_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/string.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/string.h new file mode 100644 index 0000000..61e8102 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/string.h @@ -0,0 +1,66 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)string.h 8.1 (Berkeley) 6/2/93 + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2013-2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include +#include +#include + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +__BEGIN_DECLS + +void *memchr(const void *, int, size_t) __pure; +int memcmp(const void *, const void *, size_t) __pure; +void *memcpy(void * __restrict, const void * __restrict, size_t); +void *memmove(void *, const void *, size_t); +void *memset(void *, int, size_t); + +char *strchr(const char *, int) __pure; +int strcmp(const char *, const char *) __pure; +size_t strlen(const char *) __pure; +int strncmp(const char *, const char *, size_t) __pure; +int strcasecmp(const char *, const char *); + +__END_DECLS + +#endif /* _STRING_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/sys/_null.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/sys/_null.h new file mode 100644 index 0000000..92706c6 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/sys/_null.h @@ -0,0 +1,47 @@ +/*- + * Copyright (c) 2003 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef NULL + +#if !defined(__cplusplus) +#define NULL ((void *)0) +#else +#if __cplusplus >= 201103L +#define NULL nullptr +#elif defined(__GNUG__) && defined(__GNUC__) && __GNUC__ >= 4 +#define NULL __null +#else +#if defined(__LP64__) +#define NULL (0L) +#else +#define NULL 0 +#endif /* __LP64__ */ +#endif /* __GNUG__ */ +#endif /* !__cplusplus */ + +#endif diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/sys/_stdint.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/sys/_stdint.h new file mode 100644 index 0000000..d0f9249 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/sys/_stdint.h @@ -0,0 +1,82 @@ +/*- + * Copyright (c) 2011 David E. O'Brien + * Copyright (c) 2001 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS__STDINT_H_ +#define _SYS__STDINT_H_ + +#ifndef _INT8_T_DECLARED +typedef __int8_t int8_t; +#define _INT8_T_DECLARED +#endif + +#ifndef _INT16_T_DECLARED +typedef __int16_t int16_t; +#define _INT16_T_DECLARED +#endif + +#ifndef _INT32_T_DECLARED +typedef __int32_t int32_t; +#define _INT32_T_DECLARED +#endif + +#ifndef _INT64_T_DECLARED +typedef __int64_t int64_t; +#define _INT64_T_DECLARED +#endif + +#ifndef _UINT8_T_DECLARED +typedef __uint8_t uint8_t; +#define _UINT8_T_DECLARED +#endif + +#ifndef _UINT16_T_DECLARED +typedef __uint16_t uint16_t; +#define _UINT16_T_DECLARED +#endif + +#ifndef _UINT32_T_DECLARED +typedef __uint32_t uint32_t; +#define _UINT32_T_DECLARED +#endif + +#ifndef _UINT64_T_DECLARED +typedef __uint64_t uint64_t; +#define _UINT64_T_DECLARED +#endif + +#ifndef _INTPTR_T_DECLARED +typedef __intptr_t intptr_t; +#define _INTPTR_T_DECLARED +#endif +#ifndef _UINTPTR_T_DECLARED +typedef __uintptr_t uintptr_t; +#define _UINTPTR_T_DECLARED +#endif + +#endif /* !_SYS__STDINT_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/sys/_types.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/sys/_types.h new file mode 100644 index 0000000..1afeaea --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/sys/_types.h @@ -0,0 +1,106 @@ +/*- + * Copyright (c) 2002 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS__TYPES_H_ +#define _SYS__TYPES_H_ + +#include +#include + +/* + * Standard type definitions. + */ +typedef __uint32_t __blksize_t; /* file block size */ +typedef __int64_t __blkcnt_t; /* file block count */ +typedef __int32_t __clockid_t; /* clock_gettime()... */ +typedef __uint32_t __cap_rights_t; /* capability rights */ +typedef __uint32_t __fflags_t; /* file flags */ +typedef __uint32_t __fsblkcnt_t; +typedef __uint32_t __fsfilcnt_t; +typedef __uint32_t __gid_t; +typedef __int32_t __id_t; /* can hold a gid_t, pid_t, or uid_t */ +typedef __uint32_t __ino_t; /* inode number */ +typedef long __key_t; /* IPC key (for Sys V IPC) */ +typedef __int32_t __lwpid_t; /* Thread ID (a.k.a. LWP) */ +typedef __uint16_t __mode_t; /* permissions */ +typedef int __accmode_t; /* access permissions */ +typedef int __nl_item; +typedef __uint16_t __nlink_t; /* link count */ +typedef __int32_t __off_t; /* file offset */ +typedef __int32_t __pid_t; /* process [group] */ +typedef __int32_t __rlim_t; /* resource limit - intentionally */ + /* signed, because of legacy code */ + /* that uses -1 for RLIM_INFINITY */ +typedef __uint8_t __sa_family_t; +typedef __uint32_t __socklen_t; +typedef long __suseconds_t; /* microseconds (signed) */ +typedef struct __timer *__timer_t; /* timer_gettime()... */ +typedef struct __mq *__mqd_t; /* mq_open()... */ +typedef __uint32_t __uid_t; +typedef unsigned int __useconds_t; /* microseconds (unsigned) */ +typedef int __cpuwhich_t; /* which parameter for cpuset. */ +typedef int __cpulevel_t; /* level parameter for cpuset. */ +typedef int __cpusetid_t; /* cpuset identifier. */ + +/* + * Unusual type definitions. + */ +/* + * rune_t is declared to be an ``int'' instead of the more natural + * ``unsigned long'' or ``long''. Two things are happening here. It is not + * unsigned so that EOF (-1) can be naturally assigned to it and used. Also, + * it looks like 10646 will be a 31 bit standard. This means that if your + * ints cannot hold 32 bits, you will be in trouble. The reason an int was + * chosen over a long is that the is*() and to*() routines take ints (says + * ANSI C), but they use __ct_rune_t instead of int. + * + * NOTE: rune_t is not covered by ANSI nor other standards, and should not + * be instantiated outside of lib/libc/locale. Use wchar_t. wchar_t and + * rune_t must be the same type. Also, wint_t must be no narrower than + * wchar_t, and should be able to hold all members of the largest + * character set plus one extra value (WEOF), and must be at least 16 bits. + */ +typedef int __ct_rune_t; /* arg type for ctype funcs */ +typedef __ct_rune_t __rune_t; /* rune_t (see above) */ +typedef __ct_rune_t __wchar_t; /* wchar_t (see above) */ +typedef __ct_rune_t __wint_t; /* wint_t (see above) */ + +typedef __uint32_t __dev_t; /* device number */ + +typedef __uint32_t __fixpt_t; /* fixed point number */ + +/* + * mbstate_t is an opaque object to keep conversion state during multibyte + * stream conversions. + */ +typedef union { + char __mbstate8[128]; + __int64_t _mbstateL; /* for alignment */ +} __mbstate_t; + +#endif /* !_SYS__TYPES_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/sys/cdefs.h b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/sys/cdefs.h new file mode 100644 index 0000000..16fb151 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/include/sys/cdefs.h @@ -0,0 +1,686 @@ +/*- + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Berkeley Software Design, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)cdefs.h 8.8 (Berkeley) 1/9/95 + * $FreeBSD$ + */ + +#ifndef _SYS_CDEFS_H_ +#define _SYS_CDEFS_H_ + +#if defined(__cplusplus) +#define __BEGIN_DECLS extern "C" { +#define __END_DECLS } +#else +#define __BEGIN_DECLS +#define __END_DECLS +#endif + +/* + * This code has been put in place to help reduce the addition of + * compiler specific defines in FreeBSD code. It helps to aid in + * having a compiler-agnostic source tree. + */ + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) + +#if __GNUC__ >= 3 || defined(__INTEL_COMPILER) +#define __GNUCLIKE_ASM 3 +#define __GNUCLIKE_MATH_BUILTIN_CONSTANTS +#else +#define __GNUCLIKE_ASM 2 +#endif +#define __GNUCLIKE___TYPEOF 1 +#define __GNUCLIKE___OFFSETOF 1 +#define __GNUCLIKE___SECTION 1 + +#ifndef __INTEL_COMPILER +# define __GNUCLIKE_CTOR_SECTION_HANDLING 1 +#endif + +#define __GNUCLIKE_BUILTIN_CONSTANT_P 1 +# if defined(__INTEL_COMPILER) && defined(__cplusplus) \ + && __INTEL_COMPILER < 800 +# undef __GNUCLIKE_BUILTIN_CONSTANT_P +# endif + +#if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3) && !defined(__INTEL_COMPILER) +# define __GNUCLIKE_BUILTIN_VARARGS 1 +# define __GNUCLIKE_BUILTIN_STDARG 1 +# define __GNUCLIKE_BUILTIN_VAALIST 1 +#endif + +#if defined(__GNUC__) +# define __GNUC_VA_LIST_COMPATIBILITY 1 +#endif + +#ifndef __INTEL_COMPILER +# define __GNUCLIKE_BUILTIN_NEXT_ARG 1 +# define __GNUCLIKE_MATH_BUILTIN_RELOPS +#endif + +#define __GNUCLIKE_BUILTIN_MEMCPY 1 + +/* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */ +#define __CC_SUPPORTS_INLINE 1 +#define __CC_SUPPORTS___INLINE 1 +#define __CC_SUPPORTS___INLINE__ 1 + +#define __CC_SUPPORTS___FUNC__ 1 +#define __CC_SUPPORTS_WARNING 1 + +#define __CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */ + +#define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1 + +#endif /* __GNUC__ || __INTEL_COMPILER */ + +/* + * Macro to test if we're using a specific version of gcc or later. + */ +#if defined(__GNUC__) && !defined(__INTEL_COMPILER) +#define __GNUC_PREREQ__(ma, mi) \ + (__GNUC__ > (ma) || __GNUC__ == (ma) && __GNUC_MINOR__ >= (mi)) +#else +#define __GNUC_PREREQ__(ma, mi) 0 +#endif + +/* + * The __CONCAT macro is used to concatenate parts of symbol names, e.g. + * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. + * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI + * mode -- there must be no spaces between its arguments, and for nested + * __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also + * concatenate double-quoted strings produced by the __STRING macro, but + * this only works with ANSI C. + * + * __XSTRING is like __STRING, but it expands any macros in its argument + * first. It is only available with ANSI C. + */ +#if defined(__STDC__) || defined(__cplusplus) +#define __P(protos) protos /* full-blown ANSI C */ +#define __CONCAT1(x,y) x ## y +#define __CONCAT(x,y) __CONCAT1(x,y) +#define __STRING(x) #x /* stringify without expanding x */ +#define __XSTRING(x) __STRING(x) /* expand x, then stringify */ + +#define __const const /* define reserved names to standard */ +#define __signed signed +#define __volatile volatile +#if defined(__cplusplus) +#define __inline inline /* convert to C++ keyword */ +#else +#if !(defined(__CC_SUPPORTS___INLINE)) +#define __inline /* delete GCC keyword */ +#endif /* ! __CC_SUPPORTS___INLINE */ +#endif /* !__cplusplus */ + +#else /* !(__STDC__ || __cplusplus) */ +#define __P(protos) () /* traditional C preprocessor */ +#define __CONCAT(x,y) x/**/y +#define __STRING(x) "x" + +#if !defined(__CC_SUPPORTS___INLINE) +#define __const /* delete pseudo-ANSI C keywords */ +#define __inline +#define __signed +#define __volatile +/* + * In non-ANSI C environments, new programs will want ANSI-only C keywords + * deleted from the program and old programs will want them left alone. + * When using a compiler other than gcc, programs using the ANSI C keywords + * const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS. + * When using "gcc -traditional", we assume that this is the intent; if + * __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone. + */ +#ifndef NO_ANSI_KEYWORDS +#define const /* delete ANSI C keywords */ +#define inline +#define signed +#define volatile +#endif /* !NO_ANSI_KEYWORDS */ +#endif /* !__CC_SUPPORTS___INLINE */ +#endif /* !(__STDC__ || __cplusplus) */ + +/* + * Compiler-dependent macros to help declare dead (non-returning) and + * pure (no side effects) functions, and unused variables. They are + * null except for versions of gcc that are known to support the features + * properly (old versions of gcc-2 supported the dead and pure features + * in a different (wrong) way). If we do not provide an implementation + * for a given compiler, let the compile fail if it is told to use + * a feature that we cannot live without. + */ +#ifdef lint +#define __dead2 +#define __pure2 +#define __unused +#define __packed +#define __aligned(x) +#define __section(x) +#else +#if !__GNUC_PREREQ__(2, 5) && !defined(__INTEL_COMPILER) +#define __dead2 +#define __pure2 +#define __unused +#endif +#if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 && !defined(__INTEL_COMPILER) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused +/* XXX Find out what to do for __packed, __aligned and __section */ +#endif +#if __GNUC_PREREQ__(2, 7) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) +#endif +#if defined(__INTEL_COMPILER) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) +#endif +#endif + +#if !__GNUC_PREREQ__(2, 95) +#define __alignof(x) __offsetof(struct { char __a; x __b; }, __b) +#endif + +/* + * Keywords added in C11. + */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define _Alignas(e) alignas(e) +#define _Alignof(e) alignof(e) +#define _Noreturn [[noreturn]] +#define _Static_assert(e, s) static_assert(e, s) +/* FIXME: change this to thread_local when clang in base supports it */ +#define _Thread_local __thread +#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +/* Do nothing. They are language keywords. */ +#else +/* Not supported. Implement them using our versions. */ +#define _Alignas(x) __aligned(x) +#define _Alignof(x) __alignof(x) +#define _Noreturn __dead2 +#define _Thread_local __thread +#ifdef __COUNTER__ +#define _Static_assert(x, y) __Static_assert(x, __COUNTER__) +#define __Static_assert(x, y) ___Static_assert(x, y) +#define ___Static_assert(x, y) typedef char __assert_ ## y[(x) ? 1 : -1] +#else +#define _Static_assert(x, y) struct __hack +#endif +#endif + +/* + * Emulation of C11 _Generic(). Unlike the previously defined C11 + * keywords, it is not possible to implement this using exactly the same + * syntax. Therefore implement something similar under the name + * __generic(). Unlike _Generic(), this macro can only distinguish + * between a single type, so it requires nested invocations to + * distinguish multiple cases. + */ + +#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +#define __generic(expr, t, yes, no) \ + _Generic(expr, t: yes, default: no) +#elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus) +#define __generic(expr, t, yes, no) \ + __builtin_choose_expr( \ + __builtin_types_compatible_p(__typeof(expr), t), yes, no) +#endif + +#if __GNUC_PREREQ__(2, 96) +#define __malloc_like __attribute__((__malloc__)) +#define __pure __attribute__((__pure__)) +#else +#define __malloc_like +#define __pure +#endif + +#if __GNUC_PREREQ__(3, 1) || (defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 800) +#define __always_inline __attribute__((__always_inline__)) +#else +#define __always_inline +#endif + +#if __GNUC_PREREQ__(3, 1) +#define __noinline __attribute__ ((__noinline__)) +#else +#define __noinline +#endif + +#if __GNUC_PREREQ__(3, 3) +#define __nonnull(x) __attribute__((__nonnull__(x))) +#else +#define __nonnull(x) +#endif + +#if __GNUC_PREREQ__(3, 4) +#define __fastcall __attribute__((__fastcall__)) +#else +#define __fastcall +#endif + +#if __GNUC_PREREQ__(4, 1) +#define __returns_twice __attribute__((__returns_twice__)) +#else +#define __returns_twice +#endif + +/* XXX: should use `#if __STDC_VERSION__ < 199901'. */ +#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER) +#define __func__ NULL +#endif + +#if (defined(__INTEL_COMPILER) || (defined(__GNUC__) && __GNUC__ >= 2)) && !defined(__STRICT_ANSI__) || __STDC_VERSION__ >= 199901 +#define __LONG_LONG_SUPPORTED +#endif + +/* C++11 exposes a load of C99 stuff */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define __LONG_LONG_SUPPORTED +#ifndef __STDC_LIMIT_MACROS +#define __STDC_LIMIT_MACROS +#endif +#ifndef __STDC_CONSTANT_MACROS +#define __STDC_CONSTANT_MACROS +#endif +#endif + +/* + * GCC 2.95 provides `__restrict' as an extension to C90 to support the + * C99-specific `restrict' type qualifier. We happen to use `__restrict' as + * a way to define the `restrict' type qualifier without disturbing older + * software that is unaware of C99 keywords. + */ +#if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95) +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901 || defined(lint) +#define __restrict +#else +#define __restrict restrict +#endif +#endif + +/* + * GNU C version 2.96 adds explicit branch prediction so that + * the CPU back-end can hint the processor and also so that + * code blocks can be reordered such that the predicted path + * sees a more linear flow, thus improving cache behavior, etc. + * + * The following two macros provide us with a way to utilize this + * compiler feature. Use __predict_true() if you expect the expression + * to evaluate to true, and __predict_false() if you expect the + * expression to evaluate to false. + * + * A few notes about usage: + * + * * Generally, __predict_false() error condition checks (unless + * you have some _strong_ reason to do otherwise, in which case + * document it), and/or __predict_true() `no-error' condition + * checks, assuming you want to optimize for the no-error case. + * + * * Other than that, if you don't know the likelihood of a test + * succeeding from empirical or other `hard' evidence, don't + * make predictions. + * + * * These are meant to be used in places that are run `a lot'. + * It is wasteful to make predictions in code that is run + * seldomly (e.g. at subsystem initialization time) as the + * basic block reordering that this affects can often generate + * larger code. + */ +#if __GNUC_PREREQ__(2, 96) +#define __predict_true(exp) __builtin_expect((exp), 1) +#define __predict_false(exp) __builtin_expect((exp), 0) +#else +#define __predict_true(exp) (exp) +#define __predict_false(exp) (exp) +#endif + +#if __GNUC_PREREQ__(4, 2) +#define __hidden __attribute__((__visibility__("hidden"))) +#define __exported __attribute__((__visibility__("default"))) +#else +#define __hidden +#define __exported +#endif + +/* + * We define this here since , , and + * require it. + */ +#if __GNUC_PREREQ__(4, 1) +#define __offsetof(type, field) __builtin_offsetof(type, field) +#else +#ifndef __cplusplus +#define __offsetof(type, field) \ + ((__size_t)(__uintptr_t)((const volatile void *)&((type *)0)->field)) +#else +#define __offsetof(type, field) \ + (__offsetof__ (reinterpret_cast <__size_t> \ + (&reinterpret_cast \ + (static_cast (0)->field)))) +#endif +#endif +#define __rangeof(type, start, end) \ + (__offsetof(type, end) - __offsetof(type, start)) + +/* + * Given the pointer x to the member m of the struct s, return + * a pointer to the containing structure. When using GCC, we first + * assign pointer x to a local variable, to check that its type is + * compatible with member m. + */ +#if __GNUC_PREREQ__(3, 1) +#define __containerof(x, s, m) ({ \ + const volatile __typeof(((s *)0)->m) *__x = (x); \ + __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\ +}) +#else +#define __containerof(x, s, m) \ + __DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m)) +#endif + +/* + * Compiler-dependent macros to declare that functions take printf-like + * or scanf-like arguments. They are null except for versions of gcc + * that are known to support the features properly (old versions of gcc-2 + * didn't permit keeping the keywords out of the application namespace). + */ +#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER) +#define __printflike(fmtarg, firstvararg) +#define __scanflike(fmtarg, firstvararg) +#define __format_arg(fmtarg) +#define __strfmonlike(fmtarg, firstvararg) +#define __strftimelike(fmtarg, firstvararg) +#else +#define __printflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf__, fmtarg, firstvararg))) +#define __scanflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__scanf__, fmtarg, firstvararg))) +#define __format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg))) +#define __strfmonlike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strfmon__, fmtarg, firstvararg))) +#define __strftimelike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strftime__, fmtarg, firstvararg))) +#endif + +/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */ +#if __FreeBSD_cc_version >= 300001 && defined(__GNUC__) && !defined(__INTEL_COMPILER) +#define __printf0like(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf0__, fmtarg, firstvararg))) +#else +#define __printf0like(fmtarg, firstvararg) +#endif + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) +#ifndef __INTEL_COMPILER +#define __strong_reference(sym,aliassym) \ + extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym))) +#endif +#ifdef __STDC__ +#define __weak_reference(sym,alias) \ + __asm__(".weak " #alias); \ + __asm__(".equ " #alias ", " #sym) +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning." #sym); \ + __asm__(".asciz \"" msg "\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@" #verid) +#define __sym_default(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@@" #verid) +#else +#define __weak_reference(sym,alias) \ + __asm__(".weak alias"); \ + __asm__(".equ alias, sym") +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning.sym"); \ + __asm__(".asciz \"msg\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver impl, sym@verid") +#define __sym_default(impl,sym,verid) \ + __asm__(".symver impl, sym@@verid") +#endif /* __STDC__ */ +#endif /* __GNUC__ || __INTEL_COMPILER */ + +#define __GLOBL1(sym) __asm__(".globl " #sym) +#define __GLOBL(sym) __GLOBL1(sym) + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) +#define __IDSTRING(name,string) __asm__(".ident\t\"" string "\"") +#else +/* + * The following definition might not work well if used in header files, + * but it should be better than nothing. If you want a "do nothing" + * version, then it should generate some harmless declaration, such as: + * #define __IDSTRING(name,string) struct __hack + */ +#define __IDSTRING(name,string) static const char name[] __unused = string +#endif + +/* + * Embed the rcs id of a source file in the resulting library. Note that in + * more recent ELF binutils, we use .ident allowing the ID to be stripped. + * Usage: + * __FBSDID("$FreeBSD$"); + */ +#ifndef __FBSDID +#if !defined(lint) && !defined(STRIP_FBSDID) +#define __FBSDID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __FBSDID(s) struct __hack +#endif +#endif + +#ifndef __RCSID +#ifndef NO__RCSID +#define __RCSID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __RCSID(s) struct __hack +#endif +#endif + +#ifndef __RCSID_SOURCE +#ifndef NO__RCSID_SOURCE +#define __RCSID_SOURCE(s) __IDSTRING(__CONCAT(__rcsid_source_,__LINE__),s) +#else +#define __RCSID_SOURCE(s) struct __hack +#endif +#endif + +#ifndef __SCCSID +#ifndef NO__SCCSID +#define __SCCSID(s) __IDSTRING(__CONCAT(__sccsid_,__LINE__),s) +#else +#define __SCCSID(s) struct __hack +#endif +#endif + +#ifndef __COPYRIGHT +#ifndef NO__COPYRIGHT +#define __COPYRIGHT(s) __IDSTRING(__CONCAT(__copyright_,__LINE__),s) +#else +#define __COPYRIGHT(s) struct __hack +#endif +#endif + +#ifndef __DECONST +#define __DECONST(type, var) ((type)(__uintptr_t)(const void *)(var)) +#endif + +#ifndef __DEVOLATILE +#define __DEVOLATILE(type, var) ((type)(__uintptr_t)(volatile void *)(var)) +#endif + +#ifndef __DEQUALIFY +#define __DEQUALIFY(type, var) ((type)(__uintptr_t)(const volatile void *)(var)) +#endif + +/*- + * The following definitions are an extension of the behavior originally + * implemented in , but with a different level of granularity. + * POSIX.1 requires that the macros we test be defined before any standard + * header file is included. + * + * Here's a quick run-down of the versions: + * defined(_POSIX_SOURCE) 1003.1-1988 + * _POSIX_C_SOURCE == 1 1003.1-1990 + * _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option + * _POSIX_C_SOURCE == 199309 1003.1b-1993 + * _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995, + * and the omnibus ISO/IEC 9945-1: 1996 + * _POSIX_C_SOURCE == 200112 1003.1-2001 + * _POSIX_C_SOURCE == 200809 1003.1-2008 + * + * In addition, the X/Open Portability Guide, which is now the Single UNIX + * Specification, defines a feature-test macro which indicates the version of + * that specification, and which subsumes _POSIX_C_SOURCE. + * + * Our macros begin with two underscores to avoid namespace screwage. + */ + +/* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 1 +#undef _POSIX_C_SOURCE /* Probably illegal, but beyond caring now. */ +#define _POSIX_C_SOURCE 199009 +#endif + +/* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 2 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199209 +#endif + +/* Deal with various X/Open Portability Guides and Single UNIX Spec. */ +#ifdef _XOPEN_SOURCE +#if _XOPEN_SOURCE - 0 >= 700 +#define __XSI_VISIBLE 700 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809 +#elif _XOPEN_SOURCE - 0 >= 600 +#define __XSI_VISIBLE 600 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200112 +#elif _XOPEN_SOURCE - 0 >= 500 +#define __XSI_VISIBLE 500 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199506 +#endif +#endif + +/* + * Deal with all versions of POSIX. The ordering relative to the tests above is + * important. + */ +#if defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE) +#define _POSIX_C_SOURCE 198808 +#endif +#ifdef _POSIX_C_SOURCE +#if _POSIX_C_SOURCE >= 200809 +#define __POSIX_VISIBLE 200809 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 200112 +#define __POSIX_VISIBLE 200112 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 199506 +#define __POSIX_VISIBLE 199506 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199309 +#define __POSIX_VISIBLE 199309 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199209 +#define __POSIX_VISIBLE 199209 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199009 +#define __POSIX_VISIBLE 199009 +#define __ISO_C_VISIBLE 1990 +#else +#define __POSIX_VISIBLE 198808 +#define __ISO_C_VISIBLE 0 +#endif /* _POSIX_C_SOURCE */ +#else +/*- + * Deal with _ANSI_SOURCE: + * If it is defined, and no other compilation environment is explicitly + * requested, then define our internal feature-test macros to zero. This + * makes no difference to the preprocessor (undefined symbols in preprocessing + * expressions are defined to have value zero), but makes it more convenient for + * a test program to print out the values. + * + * If a program mistakenly defines _ANSI_SOURCE and some other macro such as + * _POSIX_C_SOURCE, we will assume that it wants the broader compilation + * environment (and in fact we will never get here). + */ +#if defined(_ANSI_SOURCE) /* Hide almost everything. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1990 +#elif defined(_C99_SOURCE) /* Localism to specify strict C99 env. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1999 +#else /* Default environment: show everything. */ +#define __POSIX_VISIBLE 200809 +#define __XSI_VISIBLE 700 +#define __BSD_VISIBLE 1 +#define __ISO_C_VISIBLE 1999 +#endif +#endif + +#ifndef __has_feature +#define __has_feature(x) 0 +#endif +#ifndef __has_include +#define __has_include(x) 0 +#endif +#ifndef __has_builtin +#define __has_builtin(x) 0 +#endif + +#if defined(__mips) || defined(__powerpc64__) || defined(__arm__) +#define __NO_TLS 1 +#endif + +#endif /* !_SYS_CDEFS_H_ */ diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos.ld.S b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos.ld.S new file mode 100644 index 0000000..ee3e213 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos.ld.S @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2015-2018, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(Vector) + +MEMORY { + RAM (rwx): ORIGIN = 0x42220800, LENGTH = 0x00100000 +} + + +SECTIONS +{ + . = 0x42220800; + ASSERT(. == ALIGN(1024), + "CR7 dummy rtos address is not aligned on a page boundary.") + + ro . : { + __RO_START__ = .; + *rtos.o(.text*) + *rtos_main.o(.text*) + . = NEXT(32768); + *rtos_main2.o(.text*) + . = NEXT(32768); + *rtos_main3.o(.text*) +/* + . = NEXT(32768); + *rtos_main4.o(.text*) + . = NEXT(32768); + *rtos_main5.o(.text*) + . = NEXT(32768); + *rtos_main6.o(.text*) + . = NEXT(16384); +*/ + *(.text*) + *(.rodata*) + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as + * read-only, executable. No RW data from the next section must + * creep in. Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + . = NEXT(16384); + __RO_END__ = .; + } >RAM + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + + stacks (NOLOAD) : { + __STACKS_START__ = .; + *(tzfw_normal_stacks) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } >RAM + + __BL2_END__ = .; + + __BSS_SIZE__ = SIZEOF(.bss); + + ASSERT(. <= 0x48421000, "CR7 dummy rtos has exceeded its limit.") +} diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos.s b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos.s new file mode 100644 index 0000000..2a1f260 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos.s @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + .global Vector + .global Start + +/***************************************************************************** + * Vector table + *****************************************************************************/ + .align 5 + +Vector: + b Start /* Reset */ + b Undef /* Undefined Instruction */ + b SWI /* Supervisor Call */ + b PAbort /* Prefetch Abort */ + b DAbort /* Data Abort */ + nop /* Not used */ + b IRQ /* IRQ interrupt */ + b FIQ /* FIQ interrupt */ + + +/***************************************************************************** + * Reset Hander + *****************************************************************************/ +Start: + /* initialize registers*/ + mov r0, #0 + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 + mov r8, #0 + mov r9, #0 + mov r10, #0 + mov r11, #0 + mov r12, #0 + mov lr, #0 + + /* stack initialize */ + msr CPSR_c, #(0x17 | 0x80 | 0x40) /* ABT */ + ldr r0, =(__STACKS_END__) /* STACK_BASE_ABT */ + mov sp, r0 + + msr CPSR_c, #(0x1B | 0x80 | 0x40) /* UND */ + sub r0, r0, #0x80 /* STACK_BASE_UND */ + mov sp, r0 + + msr CPSR_c, #(0x11 | 0x80 | 0x40) /* FIQ */ + sub r0, r0, #0x80 /* STACK_BASE_FIQ */ + mov sp, r0 + + msr CPSR_c, #(0x12 | 0x80 | 0x40) /* IRQ */ + sub r0, r0, #0x80 /* STACK_BASE_IRQ */ + mov sp, r0 + + msr CPSR_c, #(0x13 | 0x80 | 0x40) /* SVC */ + sub r0, r0, #0x80 /* STACK_BASE_SVC */ + mov sp, r0 + + /* exception handler setting */ +// ldr r0, =Vector +// mcr p15, 0, r0, c12, c0, 0 + + /* Loader Main */ + BL rtos_main +// BL rtos_main2 +// BL rtos_main3 +// BL rtos_main4 +// BL rtos_main5 +// BL rtos_main6 + +NO_BOOT: + nop +1: + wfe + b 1b + + +/***************************************************************************** + * Exception Handers + *****************************************************************************/ + + /* Undefined Instruction */ +Undef: + nop +1: + wfe + b 1b + + /* Supervisor Call */ +SWI: + nop +1: + wfe + b 1b + + /* Prefetch Abort */ +PAbort: + nop +1: + wfe + b 1b + + /* Data Abort */ +DAbort: + nop +1: + wfe + b 1b + + /* IRQ interrupt */ +IRQ: + nop +1: + wfe + b 1b + + /* FIQ interrupt */ +FIQ: + nop +1: + wfe + b 1b + + + .end diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main.c b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main.c new file mode 100644 index 0000000..2838adf --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "scif.h" +#include "debug.h" +#include "micro_wait.h" +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Unions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Structs */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Globals */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Macros */ +/************************************************************************************************/ + +/************************************************************************************************/ +/* Prototypes */ +/************************************************************************************************/ +uint32_t rtos_main(void); +extern void tf_printf(const char *format, ...); + +/* Wait about 3.442[s] */ +#define WAIT_TIME (3442000U) + +uint32_t rtos_main(void) +{ + + micro_wait_init(); + micro_wait(WAIT_TIME); + NOTICE("R-Car Gen3 Dummy RTOS(CR7)\n"); + + { + uint32_t v; + + __asm__ volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r" (v)); + NOTICE("MIDR = (0x%x)\n", v); + + __asm__ volatile ("mrc p15, 4, %0, c15, c0, 0" : "=r" (v)); + NOTICE("CBAR = (0x%x)\n", v); + + __asm__ volatile ("mrs %0, cpsr" : "=r" (v)); + NOTICE("CPSR = (0x%x)\n", v); + } + + NOTICE("Dummy RTOS boot end\n"); + + return 0U; +} diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main2.c b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main2.c new file mode 100644 index 0000000..2cef2ae --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main2.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "debug.h" + + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Unions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Structs */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Globals */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Macros */ +/************************************************************************************************/ + +/************************************************************************************************/ +/* Prototypes */ +/************************************************************************************************/ +uint32_t rtos_main2(void); + + +uint32_t rtos_main2(void) +{ + NOTICE("Executing 0xE6308000\n"); + + return 0U; +} diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main3.c b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main3.c new file mode 100644 index 0000000..dd542ca --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main3.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "debug.h" + + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Unions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Structs */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Globals */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Macros */ +/************************************************************************************************/ + +/************************************************************************************************/ +/* Prototypes */ +/************************************************************************************************/ +uint32_t rtos_main3(void); + + +uint32_t rtos_main3(void) +{ + NOTICE("Executing 0xE6310000\n"); + + return 0U; +} diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main4.c b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main4.c new file mode 100644 index 0000000..2bd40e7 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main4.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "debug.h" + + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Unions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Structs */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Globals */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Macros */ +/************************************************************************************************/ + +/************************************************************************************************/ +/* Prototypes */ +/************************************************************************************************/ +uint32_t rtos_main4(void); + + +uint32_t rtos_main4(void) +{ + NOTICE("Executing 0xE6318000\n"); + + return 0U; +} diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main5.c b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main5.c new file mode 100644 index 0000000..615c125 --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main5.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "debug.h" + + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Unions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Structs */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Globals */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Macros */ +/************************************************************************************************/ + +/************************************************************************************************/ +/* Prototypes */ +/************************************************************************************************/ +uint32_t rtos_main5(void); + + +uint32_t rtos_main5(void) +{ + NOTICE("Executing 0xE6320000\n"); + + return 0U; +} diff --git a/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main6.c b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main6.c new file mode 100644 index 0000000..ab00b4b --- /dev/null +++ b/IPL/SDK/v3m/src/V3M_Dummy_RTOS/rtos/rtos_main6.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "debug.h" + + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Unions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Structs */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Globals */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Macros */ +/************************************************************************************************/ + +/************************************************************************************************/ +/* Prototypes */ +/************************************************************************************************/ +uint32_t rtos_main6(void); + + +uint32_t rtos_main6(void) +{ + NOTICE("Executing 0xE6328000\n"); + + return 0U; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/.checkpatch.conf b/IPL/SDK/v3m/src/arm-trusted-firmware/.checkpatch.conf new file mode 100644 index 0000000..c8a6084 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/.checkpatch.conf @@ -0,0 +1,87 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# Configure how the Linux checkpatch script should be invoked in the context of +# the Trusted Firmware source tree. +# + +# This is not Linux so don't expect a Linux tree! +--no-tree + +# 'Signed-off-by' lines in commit messages are not mandated for TF. +--no-signoff + +# This clarifes the lines indications in the report. +# +# E.g.: +# Without this option, we have the following output: +# #333: FILE: drivers/arm/gic/arm_gic.c:160: +# So we have 2 lines indications (333 and 160), which is confusing. +# We only care about the position in the source file. +# +# With this option, it becomes: +# drivers/arm/gic/arm_gic.c:160: +--showfile + +# +# Ignore the following message types, as they don't necessarily make sense in +# the context of the Trusted Firmware. +# + +# COMPLEX_MACRO generates false positives. +--ignore COMPLEX_MACRO + +# Commit messages might contain a Gerrit Change-Id. +--ignore GERRIT_CHANGE_ID + +# Do not check the format of commit messages, as Github's merge commits do not +# observe it. +--ignore GIT_COMMIT_ID + +# FILE_PATH_CHANGES reports this kind of message: +# "added, moved or deleted file(s), does MAINTAINERS need updating?" +# We do not use this MAINTAINERS file process in TF. +--ignore FILE_PATH_CHANGES + +# AVOID_EXTERNS reports this kind of messages: +# "externs should be avoided in .c files" +# We don't follow this convention in TF. +--ignore AVOID_EXTERNS + +# NEW_TYPEDEFS reports this kind of messages: +# "do not add new typedefs" +# We allow adding new typedefs in TF. +--ignore NEW_TYPEDEFS + +# VOLATILE reports this kind of messages: +# "Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt" +# We allow the usage of the volatile keyword in TF. +--ignore VOLATILE diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/Makefile b/IPL/SDK/v3m/src/arm-trusted-firmware/Makefile new file mode 100644 index 0000000..13bc2ec --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/Makefile @@ -0,0 +1,763 @@ +# +# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# +# Trusted Firmware Version +# +VERSION_MAJOR := 1 +VERSION_MINOR := 3 + +# Default goal is build all images +.DEFAULT_GOAL := all + +MAKE_HELPERS_DIRECTORY := make_helpers/ +include ${MAKE_HELPERS_DIRECTORY}build_macros.mk +include ${MAKE_HELPERS_DIRECTORY}build_env.mk + +################################################################################ +# Default values for build configurations +################################################################################ + +# The Target build architecture. Supported values are: aarch64, aarch32. +ARCH := aarch64 +# Build verbosity +V := 0 +# Debug build +DEBUG := 0 +# Build platform +DEFAULT_PLAT := fvp +PLAT := ${DEFAULT_PLAT} +# SPD choice +SPD := none +# The AArch32 Secure Payload to be built as BL32 image +AARCH32_SP := none +# Base commit to perform code check on +BASE_COMMIT := origin/master +# NS timer register save and restore +NS_TIMER_SWITCH := 0 +# By default, BL1 acts as the reset handler, not BL31 +RESET_TO_BL31 := 0 +# Include FP registers in cpu context +CTX_INCLUDE_FPREGS := 0 +# Build flag to include AArch32 registers in cpu context save and restore +# during world switch. This flag must be set to 0 for AArch64-only platforms. +CTX_INCLUDE_AARCH32_REGS := 1 +# Determine the version of ARM GIC architecture to use for interrupt management +# in EL3. The platform port can change this value if needed. +ARM_GIC_ARCH := 2 +# Determine the version of ARM CCI product used in the platform. The platform +# port can change this value if needed. +ARM_CCI_PRODUCT_ID := 400 +# Flag used to indicate if ASM_ASSERTION should be enabled for the build. +# This defaults to being present in DEBUG builds only. +ASM_ASSERTION := ${DEBUG} +# Build option to choose whether Trusted firmware uses Coherent memory or not. +USE_COHERENT_MEM := 1 +# Flag used to choose the power state format viz Extended State-ID or the Original +# format. +PSCI_EXTENDED_STATE_ID := 0 +# Default FIP file name +FIP_NAME := fip.bin +# Default FWU_FIP file name +FWU_FIP_NAME := fwu_fip.bin +# By default, use the -pedantic option in the gcc command line +DISABLE_PEDANTIC := 0 +# Flags to generate the Chain of Trust +GENERATE_COT := 0 +CREATE_KEYS := 1 +SAVE_KEYS := 0 +# Flags to build TF with Trusted Boot support +TRUSTED_BOARD_BOOT := 0 +# By default, consider that the platform's reset address is not programmable. +# The platform Makefile is free to override this value. +PROGRAMMABLE_RESET_ADDRESS := 0 +# Build flag to treat usage of deprecated platform and framework APIs as error. +ERROR_DEPRECATED := 0 +# By default, consider that the platform may release several CPUs out of reset. +# The platform Makefile is free to override this value. +COLD_BOOT_SINGLE_CPU := 0 +# Flag to introduce an infinite loop in BL1 just before it exits into the next +# image. This is meant to help debugging the post-BL2 phase. +SPIN_ON_BL1_EXIT := 0 +# Build PL011 UART driver in minimal generic UART mode +PL011_GENERIC_UART := 0 +# Flag to enable Performance Measurement Framework +ENABLE_PMF := 0 +# Flag to enable PSCI STATs functionality +ENABLE_PSCI_STAT := 0 +# Whether code and read-only data should be put on separate memory pages. +# The platform Makefile is free to override this value. +SEPARATE_CODE_AND_RODATA := 0 +# Flag to enable new version of image loading +LOAD_IMAGE_V2 := 0 + +################################################################################ +# Checkpatch script options +################################################################################ + +CHECKCODE_ARGS := --no-patch +# Do not check the coding style on imported library files or documentation files +INC_LIB_DIRS_TO_CHECK := $(sort $(filter-out \ + include/lib/libfdt \ + include/lib/stdlib, \ + $(wildcard include/lib/*))) +INC_DIRS_TO_CHECK := $(sort $(filter-out \ + include/lib, \ + $(wildcard include/*))) +LIB_DIRS_TO_CHECK := $(sort $(filter-out \ + lib/libfdt \ + lib/stdlib, \ + $(wildcard lib/*))) +ROOT_DIRS_TO_CHECK := $(sort $(filter-out \ + lib \ + include \ + docs \ + %.md, \ + $(wildcard *))) +CHECK_PATHS := ${ROOT_DIRS_TO_CHECK} \ + ${INC_DIRS_TO_CHECK} \ + ${INC_LIB_DIRS_TO_CHECK} \ + ${LIB_DIRS_TO_CHECK} + + +################################################################################ +# Process build options +################################################################################ + +# Verbose flag +ifeq (${V},0) + Q:=@ + CHECKCODE_ARGS += --no-summary --terse +else + Q:= +endif +export Q + +# Process Debug flag +$(eval $(call add_define,DEBUG)) +ifneq (${DEBUG}, 0) + BUILD_TYPE := debug + TF_CFLAGS += -g + ASFLAGS += -g -Wa,--gdwarf-2 + # Use LOG_LEVEL_INFO by default for debug builds + LOG_LEVEL := 40 +else + BUILD_TYPE := release + $(eval $(call add_define,NDEBUG)) + # Use LOG_LEVEL_NOTICE by default for release builds + LOG_LEVEL := 20 +endif + +# Default build string (git branch and commit) +ifeq (${BUILD_STRING},) + BUILD_STRING := $(shell git log -n 1 --pretty=format:"%h") +endif +VERSION_STRING := v${VERSION_MAJOR}.${VERSION_MINOR}(${BUILD_TYPE}):${BUILD_STRING} + +# The cert_create tool cannot generate certificates individually, so we use the +# target 'certificates' to create them all +ifneq (${GENERATE_COT},0) + FIP_DEPS += certificates + FWU_FIP_DEPS += fwu_certificates +endif + +# For AArch32, enable new version of image loading. +ifeq (${ARCH},aarch32) + LOAD_IMAGE_V2 := 1 +endif + +################################################################################ +# Toolchain +################################################################################ + +CC := ${CROSS_COMPILE}gcc +CPP := ${CROSS_COMPILE}cpp +AS := ${CROSS_COMPILE}gcc +AR := ${CROSS_COMPILE}ar +LD := ${CROSS_COMPILE}ld +OC := ${CROSS_COMPILE}objcopy +OD := ${CROSS_COMPILE}objdump +NM := ${CROSS_COMPILE}nm +PP := ${CROSS_COMPILE}gcc -E + +ASFLAGS_aarch64 = -mgeneral-regs-only +TF_CFLAGS_aarch64 = -mgeneral-regs-only -mstrict-align + +ASFLAGS_aarch32 = -march=armv8-a +TF_CFLAGS_aarch32 = -march=armv8-a + +ASFLAGS += -nostdinc -ffreestanding -Wa,--fatal-warnings \ + -Werror -Wmissing-include-dirs \ + -D__ASSEMBLY__ $(ASFLAGS_$(ARCH)) \ + ${DEFINES} ${INCLUDES} +TF_CFLAGS += -nostdinc -ffreestanding -Wall \ + -Werror -Wmissing-include-dirs \ + -std=c99 -c -Os \ + $(TF_CFLAGS_$(ARCH)) \ + ${DEFINES} ${INCLUDES} +TF_CFLAGS += -ffunction-sections -fdata-sections + +LDFLAGS += --fatal-warnings -O1 +LDFLAGS += --gc-sections + + +################################################################################ +# Common sources and include directories +################################################################################ +include lib/stdlib/stdlib.mk + +BL_COMMON_SOURCES += common/bl_common.c \ + common/tf_printf.c \ + common/${ARCH}/debug.S \ + lib/${ARCH}/cache_helpers.S \ + lib/${ARCH}/misc_helpers.S \ + plat/common/${ARCH}/platform_helpers.S \ + ${STDLIB_SRCS} + +INCLUDES += -Iinclude/bl1 \ + -Iinclude/bl31 \ + -Iinclude/common \ + -Iinclude/common/${ARCH} \ + -Iinclude/drivers \ + -Iinclude/drivers/arm \ + -Iinclude/drivers/auth \ + -Iinclude/drivers/io \ + -Iinclude/drivers/ti/uart \ + -Iinclude/lib \ + -Iinclude/lib/${ARCH} \ + -Iinclude/lib/cpus/${ARCH} \ + -Iinclude/lib/el3_runtime \ + -Iinclude/lib/el3_runtime/${ARCH} \ + -Iinclude/lib/pmf \ + -Iinclude/lib/psci \ + -Iinclude/plat/common \ + -Iinclude/services \ + ${PLAT_INCLUDES} \ + ${SPD_INCLUDES} + + +################################################################################ +# Generic definitions +################################################################################ + +include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk + +BUILD_BASE := ./build +BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${BUILD_TYPE} + +SPDS := $(sort $(filter-out none, $(patsubst services/spd/%,%,$(wildcard services/spd/*)))) + +# Platforms providing their own TBB makefile may override this value +INCLUDE_TBBR_MK := 1 + + +################################################################################ +# Include SPD Makefile if one has been specified +################################################################################ + +ifneq (${SPD},none) +ifeq (${ARCH},aarch32) + $(error "Error: SPD is incompatible with AArch32.") +endif +ifdef EL3_PAYLOAD_BASE + $(warning "SPD and EL3_PAYLOAD_BASE are incompatible build options.") + $(warning "The SPD and its BL32 companion will be present but ignored.") +endif + # We expect to locate an spd.mk under the specified SPD directory + SPD_MAKE := $(wildcard services/spd/${SPD}/${SPD}.mk) + + ifeq (${SPD_MAKE},) + $(error Error: No services/spd/${SPD}/${SPD}.mk located) + endif + $(info Including ${SPD_MAKE}) + include ${SPD_MAKE} + + # If there's BL32 companion for the chosen SPD, we expect that the SPD's + # Makefile would set NEED_BL32 to "yes". In this case, the build system + # supports two mutually exclusive options: + # * BL32 is built from source: then BL32_SOURCES must contain the list + # of source files to build BL32 + # * BL32 is a prebuilt binary: then BL32 must point to the image file + # that will be included in the FIP + # If both BL32_SOURCES and BL32 are defined, the binary takes precedence + # over the sources. +endif + + +################################################################################ +# Include the platform specific Makefile after the SPD Makefile (the platform +# makefile may use all previous definitions in this file) +################################################################################ + +include ${PLAT_MAKEFILE_FULL} + +# Platform compatibility is not supported in AArch32 +ifneq (${ARCH},aarch32) +# If the platform has not defined ENABLE_PLAT_COMPAT, then enable it by default +ifndef ENABLE_PLAT_COMPAT +ENABLE_PLAT_COMPAT := 1 +endif + +# Include the platform compatibility helpers for PSCI +ifneq (${ENABLE_PLAT_COMPAT}, 0) +include plat/compat/plat_compat.mk +endif +endif + +# Include the CPU specific operations makefile, which provides default +# values for all CPU errata workarounds and CPU specific optimisations. +# This can be overridden by the platform. +include lib/cpus/cpu-ops.mk + + +################################################################################ +# Check incompatible options +################################################################################ + +ifdef EL3_PAYLOAD_BASE + ifdef PRELOADED_BL33_BASE + $(warning "PRELOADED_BL33_BASE and EL3_PAYLOAD_BASE are \ + incompatible build options. EL3_PAYLOAD_BASE has priority.") + endif +endif + +ifeq (${NEED_BL33},yes) + ifdef EL3_PAYLOAD_BASE + $(warning "BL33 image is not needed when option \ + BL33_PAYLOAD_BASE is used and won't be added to the FIP file.") + endif + ifdef PRELOADED_BL33_BASE + $(warning "BL33 image is not needed when option \ + PRELOADED_BL33_BASE is used and won't be added to the FIP \ + file.") + endif +endif + +# TRUSTED_BOARD_BOOT is currently not supported when LOAD_IMAGE_V2 is enabled. +ifeq (${LOAD_IMAGE_V2},1) + ifeq (${TRUSTED_BOARD_BOOT},1) + $(error "TRUSTED_BOARD_BOOT is currently not supported \ + for LOAD_IMAGE_V2=1") + endif +endif + +# For AArch32, LOAD_IMAGE_V2 must be enabled. +ifeq (${ARCH},aarch32) + ifeq (${LOAD_IMAGE_V2}, 0) + $(error "For AArch32, LOAD_IMAGE_V2 must be enabled.") + endif +endif + + +################################################################################ +# Process platform overrideable behaviour +################################################################################ + +# Check if -pedantic option should be used +ifeq (${DISABLE_PEDANTIC},0) + TF_CFLAGS += -pedantic +endif + +# Using the ARM Trusted Firmware BL2 implies that a BL33 image also needs to be +# supplied for the FIP and Certificate generation tools. This flag can be +# overridden by the platform. +ifdef BL2_SOURCES + ifdef EL3_PAYLOAD_BASE + # If booting an EL3 payload there is no need for a BL33 image + # in the FIP file. + NEED_BL33 := no + else + ifdef PRELOADED_BL33_BASE + # If booting a BL33 preloaded image there is no need of + # another one in the FIP file. + NEED_BL33 := no + else + NEED_BL33 ?= yes + endif + endif +endif + +# Process TBB related flags +ifneq (${GENERATE_COT},0) + # Common cert_create options + ifneq (${CREATE_KEYS},0) + $(eval CRT_ARGS += -n) + $(eval FWU_CRT_ARGS += -n) + ifneq (${SAVE_KEYS},0) + $(eval CRT_ARGS += -k) + $(eval FWU_CRT_ARGS += -k) + endif + endif + # Include TBBR makefile (unless the platform indicates otherwise) + ifeq (${INCLUDE_TBBR_MK},1) + include make_helpers/tbbr/tbbr_tools.mk + endif +endif + +# Make sure PMF is enabled if PSCI STAT is enabled. +ifeq (${ENABLE_PSCI_STAT},1) +ENABLE_PMF := 1 +endif + +################################################################################ +# Auxiliary tools (fiptool, cert_create, etc) +################################################################################ + +# Variables for use with Certificate Generation Tool +CRTTOOLPATH ?= tools/cert_create +CRTTOOL ?= ${CRTTOOLPATH}/cert_create${BIN_EXT} + +# Variables for use with Firmware Image Package +FIPTOOLPATH ?= tools/fiptool +FIPTOOL ?= ${FIPTOOLPATH}/fiptool${BIN_EXT} + +# Dummy Image Create +DUMMYTOOLPATH ?= tools/dummy_create +DUMMYTOOL ?= ${DUMMYTOOLPATH}/dummy_create + +################################################################################ +# Build options checks +################################################################################ + +$(eval $(call assert_boolean,DEBUG)) +$(eval $(call assert_boolean,NS_TIMER_SWITCH)) +$(eval $(call assert_boolean,RESET_TO_BL31)) +$(eval $(call assert_boolean,CTX_INCLUDE_FPREGS)) +$(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS)) +$(eval $(call assert_boolean,ASM_ASSERTION)) +$(eval $(call assert_boolean,USE_COHERENT_MEM)) +$(eval $(call assert_boolean,DISABLE_PEDANTIC)) +$(eval $(call assert_boolean,GENERATE_COT)) +$(eval $(call assert_boolean,CREATE_KEYS)) +$(eval $(call assert_boolean,SAVE_KEYS)) +$(eval $(call assert_boolean,TRUSTED_BOARD_BOOT)) +$(eval $(call assert_boolean,PROGRAMMABLE_RESET_ADDRESS)) +$(eval $(call assert_boolean,COLD_BOOT_SINGLE_CPU)) +$(eval $(call assert_boolean,PSCI_EXTENDED_STATE_ID)) +$(eval $(call assert_boolean,ERROR_DEPRECATED)) +$(eval $(call assert_boolean,ENABLE_PLAT_COMPAT)) +$(eval $(call assert_boolean,SPIN_ON_BL1_EXIT)) +$(eval $(call assert_boolean,PL011_GENERIC_UART)) +$(eval $(call assert_boolean,ENABLE_PMF)) +$(eval $(call assert_boolean,ENABLE_PSCI_STAT)) +$(eval $(call assert_boolean,SEPARATE_CODE_AND_RODATA)) +$(eval $(call assert_boolean,LOAD_IMAGE_V2)) + + +################################################################################ +# Add definitions to the cpp preprocessor based on the current build options. +# This is done after including the platform specific makefile to allow the +# platform to overwrite the default options +################################################################################ + +$(eval $(call add_define,PLAT_${PLAT})) +$(eval $(call add_define,SPD_${SPD})) +$(eval $(call add_define,NS_TIMER_SWITCH)) +$(eval $(call add_define,RESET_TO_BL31)) +$(eval $(call add_define,CTX_INCLUDE_FPREGS)) +$(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS)) +$(eval $(call add_define,ARM_GIC_ARCH)) +$(eval $(call add_define,ARM_CCI_PRODUCT_ID)) +$(eval $(call add_define,ASM_ASSERTION)) +$(eval $(call add_define,LOG_LEVEL)) +$(eval $(call add_define,USE_COHERENT_MEM)) +$(eval $(call add_define,TRUSTED_BOARD_BOOT)) +$(eval $(call add_define,PROGRAMMABLE_RESET_ADDRESS)) +$(eval $(call add_define,COLD_BOOT_SINGLE_CPU)) +$(eval $(call add_define,PSCI_EXTENDED_STATE_ID)) +$(eval $(call add_define,ERROR_DEPRECATED)) +$(eval $(call add_define,ENABLE_PLAT_COMPAT)) +$(eval $(call add_define,SPIN_ON_BL1_EXIT)) +$(eval $(call add_define,PL011_GENERIC_UART)) +$(eval $(call add_define,ENABLE_PMF)) +$(eval $(call add_define,ENABLE_PSCI_STAT)) +$(eval $(call add_define,SEPARATE_CODE_AND_RODATA)) +$(eval $(call add_define,LOAD_IMAGE_V2)) +# Define the EL3_PAYLOAD_BASE flag only if it is provided. +ifdef EL3_PAYLOAD_BASE + $(eval $(call add_define,EL3_PAYLOAD_BASE)) +else + # Define the PRELOADED_BL33_BASE flag only if it is provided and + # EL3_PAYLOAD_BASE is not defined, as it has priority. + ifdef PRELOADED_BL33_BASE + $(eval $(call add_define,PRELOADED_BL33_BASE)) + endif +endif +# Define the AARCH32/AARCH64 flag based on the ARCH flag +ifeq (${ARCH},aarch32) + $(eval $(call add_define,AARCH32)) +else + $(eval $(call add_define,AARCH64)) +endif + +################################################################################ +# Include BL specific makefiles +################################################################################ +ifdef BL1_SOURCES +NEED_BL1 := yes +include bl1/bl1.mk +endif + +ifdef BL2_SOURCES +NEED_BL2 := yes +include bl2/bl2.mk +endif + +# For AArch32, BL31 is not applicable, and BL2U is not supported at present. +ifneq (${ARCH},aarch32) +ifdef BL2U_SOURCES +NEED_BL2U := yes +include bl2u/bl2u.mk +endif + +ifdef BL31_SOURCES +# When booting an EL3 payload, there is no need to compile the BL31 image nor +# put it in the FIP. +ifndef EL3_PAYLOAD_BASE +NEED_BL31 := yes +include bl31/bl31.mk +endif +endif +endif + +ifeq (${ARCH},aarch32) +NEED_BL32 := yes + +################################################################################ +# Build `AARCH32_SP` as BL32 image for AArch32 +################################################################################ +ifneq (${AARCH32_SP},none) +# We expect to locate an sp.mk under the specified AARCH32_SP directory +AARCH32_SP_MAKE := $(wildcard bl32/${AARCH32_SP}/${AARCH32_SP}.mk) + +ifeq (${AARCH32_SP_MAKE},) + $(error Error: No bl32/${AARCH32_SP}/${AARCH32_SP}.mk located) +endif + +$(info Including ${AARCH32_SP_MAKE}) +include ${AARCH32_SP_MAKE} +endif + +endif + +################################################################################ +# Build targets +################################################################################ + +.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool fip fwu_fip certtool +.SUFFIXES: + +all: msg_start + +msg_start: + @echo "Building ${PLAT}" + +# Check if deprecated declarations should be treated as error or not. +ifeq (${ERROR_DEPRECATED},0) + TF_CFLAGS += -Wno-error=deprecated-declarations +endif + +# Expand build macros for the different images +ifeq (${NEED_BL1},yes) +$(eval $(call MAKE_BL,1)) +endif + +ifeq (${NEED_BL2},yes) +$(if ${BL2}, $(eval $(call MAKE_TOOL_ARGS,2,${BL2},tb-fw)),\ + $(eval $(call MAKE_BL,2,tb-fw))) +endif + +ifeq (${NEED_BL31},yes) +BL31_SOURCES += ${SPD_SOURCES} +$(if ${BL31}, $(eval $(call MAKE_TOOL_ARGS,31,${BL31},soc-fw)),\ + $(eval $(call MAKE_BL,31,soc-fw))) +endif + +# If a BL32 image is needed but neither BL32 nor BL32_SOURCES is defined, the +# build system will call FIP_ADD_IMG to print a warning message and abort the +# process. Note that the dependency on BL32 applies to the FIP only. +ifeq (${NEED_BL32},yes) +$(if ${BL32}, $(eval $(call MAKE_TOOL_ARGS,32,${BL32},tos-fw)),\ + $(if ${BL32_SOURCES}, $(eval $(call MAKE_BL,32,tos-fw)),\ + $(eval $(call FIP_ADD_IMG,BL32,--tos-fw)))) +endif + +# Add the BL33 image if required by the platform +ifeq (${NEED_BL33},yes) +$(eval $(call FIP_ADD_IMG,BL33,--nt-fw)) +endif + +ifeq (${NEED_BL2U},yes) +BL2U_PATH := $(if ${BL2U},${BL2U},$(call IMG_BIN,2u)) +$(if ${BL2U}, ,$(eval $(call MAKE_BL,2u))) +$(eval $(call FWU_FIP_ADD_PAYLOAD,${BL2U_PATH},--ap-fwu-cfg)) +endif + +locate-checkpatch: +ifndef CHECKPATCH + $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/script/checkpatch.pl") +else +ifeq (,$(wildcard ${CHECKPATCH})) + $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/script/checkpatch.pl") +endif +endif + +clean: + @echo " CLEAN" + $(call SHELL_REMOVE_DIR,${BUILD_PLAT}) + ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean + ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean + ${Q}${MAKE} -C ${DUMMYTOOLPATH} clean + +realclean distclean: + @echo " REALCLEAN" + $(call SHELL_REMOVE_DIR,${BUILD_BASE}) + $(call SHELL_DELETE_ALL, ${CURDIR}/cscope.*) + ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean + ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean + ${Q}${MAKE} -C ${DUMMYTOOLPATH} clean + +checkcodebase: locate-checkpatch + @echo " CHECKING STYLE" + @if test -d .git ; then \ + git ls-files | grep -E -v libfdt\|stdlib\|docs\|\.md | \ + while read GIT_FILE ; \ + do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ; \ + done ; \ + else \ + find . -type f -not -iwholename "*.git*" \ + -not -iwholename "*build*" \ + -not -iwholename "*libfdt*" \ + -not -iwholename "*stdlib*" \ + -not -iwholename "*docs*" \ + -not -iwholename "*.md" \ + -exec ${CHECKPATCH} ${CHECKCODE_ARGS} -f {} \; ; \ + fi + +checkpatch: locate-checkpatch + @echo " CHECKING STYLE" + ${Q}git log -p ${BASE_COMMIT}..HEAD -- ${CHECK_PATHS} | ${CHECKPATCH} - || true + +certtool: ${CRTTOOL} + +.PHONY: ${CRTTOOL} +${CRTTOOL}: + ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} + @${ECHO_BLANK_LINE} + @echo "Built $@ successfully" + @${ECHO_BLANK_LINE} + +ifneq (${GENERATE_COT},0) +certificates: ${CRT_DEPS} ${CRTTOOL} + ${Q}${CRTTOOL} ${CRT_ARGS} + @${ECHO_BLANK_LINE} + @echo "Built $@ successfully" + @echo "Certificates can be found in ${BUILD_PLAT}" + @${ECHO_BLANK_LINE} +endif + +${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} ${FIPTOOL} + ${Q}${FIPTOOL} create ${FIP_ARGS} $@ + ${Q}${FIPTOOL} info $@ + @${ECHO_BLANK_LINE} + @echo "Built $@ successfully" + @${ECHO_BLANK_LINE} + +ifneq (${GENERATE_COT},0) +fwu_certificates: ${FWU_CRT_DEPS} ${CRTTOOL} + ${Q}${CRTTOOL} ${FWU_CRT_ARGS} + @echo + @echo "Built $@ successfully" + @echo "FWU certificates can be found in ${BUILD_PLAT}" + @echo +endif + +${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS} ${FIPTOOL} + ${Q}${FIPTOOL} create ${FWU_FIP_ARGS} $@ + ${Q}${FIPTOOL} info $@ + @echo + @echo "Built $@ successfully" + @echo + +fiptool: ${FIPTOOL} +fip: ${BUILD_PLAT}/${FIP_NAME} +fwu_fip: ${BUILD_PLAT}/${FWU_FIP_NAME} + +.PHONY: ${FIPTOOL} +${FIPTOOL}: + ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${FIPTOOLPATH} + +dummytool: ${DUMMYTOOL} + +.PHONY: ${DUMMYTOOL} +${DUMMYTOOL}: + ${Q}${MAKE} CPPFLAGS="-D=AARCH64" --no-print-directory -C ${DUMMYTOOLPATH} + +cscope: + @echo " CSCOPE" + ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files + ${Q}cscope -b -q -k + +help: + @echo "usage: ${MAKE} PLAT=<${PLATFORM_LIST}> [OPTIONS] [TARGET]" + @echo "" + @echo "PLAT is used to specify which platform you wish to build." + @echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}" + @echo "" + @echo "Please refer to the User Guide for a list of all supported options." + @echo "Note that the build system doesn't track dependencies for build " + @echo "options. Therefore, if any of the build options are changed " + @echo "from a previous build, a clean build must be performed." + @echo "" + @echo "Supported Targets:" + @echo " all Build all individual bootloader binaries" + @echo " bl1 Build the BL1 binary" + @echo " bl2 Build the BL2 binary" + @echo " bl2u Build the BL2U binary" + @echo " bl31 Build the BL31 binary" + @echo " bl32 Build the BL32 binary. If ARCH=aarch32, then " + @echo " this builds secure payload specified by AARCH32_SP" + @echo " certificates Build the certificates (requires 'GENERATE_COT=1')" + @echo " fip Build the Firmware Image Package (FIP)" + @echo " fwu_fip Build the FWU Firmware Image Package (FIP)" + @echo " checkcodebase Check the coding style of the entire source tree" + @echo " checkpatch Check the coding style on changes in the current" + @echo " branch against BASE_COMMIT (default origin/master)" + @echo " clean Clean the build for the selected platform" + @echo " cscope Generate cscope index" + @echo " distclean Remove all build artifacts for all platforms" + @echo " certtool Build the Certificate generation tool" + @echo " fiptool Build the Firmware Image Package(FIP) creation tool" + @echo "" + @echo "Note: most build targets require PLAT to be set to a specific platform." + @echo "" + @echo "example: build all targets for the FVP platform:" + @echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all" diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/acknowledgements.md b/IPL/SDK/v3m/src/arm-trusted-firmware/acknowledgements.md new file mode 100644 index 0000000..2f6309e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/acknowledgements.md @@ -0,0 +1,13 @@ +Contributor Acknowledgements +============================ + +Companies +--------- +Linaro Limited + +NVIDIA Corporation + +Xilinx, Inc. + +Individuals +----------- diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch32/bl1_arch_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch32/bl1_arch_setup.c new file mode 100644 index 0000000..6b906c7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch32/bl1_arch_setup.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +/******************************************************************************* + * TODO: Function that does the first bit of architectural setup. + ******************************************************************************/ +void bl1_arch_setup(void) +{ + +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch32/bl1_context_mgmt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch32/bl1_context_mgmt.c new file mode 100644 index 0000000..a369097 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch32/bl1_context_mgmt.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * Following arrays will be used for context management. + * There are 2 instances, for the Secure and Non-Secure contexts. + */ +static cpu_context_t bl1_cpu_context[2]; +static smc_ctx_t bl1_smc_context[2]; + +/* Following contains the next cpu context pointer. */ +static void *bl1_next_cpu_context_ptr; + +/* Following contains the next smc context pointer. */ +static void *bl1_next_smc_context_ptr; + +/* Following functions are used for SMC context handling */ +void *smc_get_ctx(int security_state) +{ + assert(sec_state_is_valid(security_state)); + return &bl1_smc_context[security_state]; +} + +void smc_set_next_ctx(int security_state) +{ + assert(sec_state_is_valid(security_state)); + bl1_next_smc_context_ptr = &bl1_smc_context[security_state]; +} + +void *smc_get_next_ctx(void) +{ + return bl1_next_smc_context_ptr; +} + +/* Following functions are used for CPU context handling */ +void *cm_get_context(uint32_t security_state) +{ + assert(sec_state_is_valid(security_state)); + return &bl1_cpu_context[security_state]; +} + +void cm_set_next_context(void *cpu_context) +{ + assert(cpu_context); + bl1_next_cpu_context_ptr = cpu_context; +} + +void *cm_get_next_context(void) +{ + return bl1_next_cpu_context_ptr; +} + +/******************************************************************************* + * Following function copies GP regs r0-r4, lr and spsr, + * from the CPU context to the SMC context structures. + ******************************************************************************/ +static void copy_cpu_ctx_to_smc_ctx(const regs_t *cpu_reg_ctx, + smc_ctx_t *next_smc_ctx) +{ + next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0); + next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1); + next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2); + next_smc_ctx->r3 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R3); + next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR); + next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR); +} + +/******************************************************************************* + * Following function flushes the SMC & CPU context pointer and its data. + ******************************************************************************/ +static void flush_smc_and_cpu_ctx(void) +{ + flush_dcache_range((uintptr_t)&bl1_next_smc_context_ptr, + sizeof(bl1_next_smc_context_ptr)); + flush_dcache_range((uintptr_t)bl1_next_smc_context_ptr, + sizeof(smc_ctx_t)); + + flush_dcache_range((uintptr_t)&bl1_next_cpu_context_ptr, + sizeof(bl1_next_cpu_context_ptr)); + flush_dcache_range((uintptr_t)bl1_next_cpu_context_ptr, + sizeof(cpu_context_t)); +} + +/******************************************************************************* + * This function prepares the context for Secure/Normal world images. + * Normal world images are transitioned to HYP(if supported) else SVC. + ******************************************************************************/ +void bl1_prepare_next_image(unsigned int image_id) +{ + unsigned int security_state; + image_desc_t *image_desc; + entry_point_info_t *next_bl_ep; + + /* Get the image descriptor. */ + image_desc = bl1_plat_get_image_desc(image_id); + assert(image_desc); + + /* Get the entry point info. */ + next_bl_ep = &image_desc->ep_info; + + /* Get the image security state. */ + security_state = GET_SECURITY_STATE(next_bl_ep->h.attr); + + /* Prepare the SPSR for the next BL image. */ + if (security_state == SECURE) { + next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, + SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); + } else { + /* Use HYP mode if supported else use SVC. */ + if (GET_VIRT_EXT(read_id_pfr1())) { + next_bl_ep->spsr = SPSR_MODE32(MODE32_hyp, SPSR_T_ARM, + SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); + } else { + next_bl_ep->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, + SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); + } + } + + /* Allow platform to make change */ + bl1_plat_set_ep_info(image_id, next_bl_ep); + + /* Prepare the cpu context for the next BL image. */ + cm_init_my_context(next_bl_ep); + cm_prepare_el3_exit(security_state); + cm_set_next_context(cm_get_context(security_state)); + + /* Prepare the smc context for the next BL image. */ + smc_set_next_ctx(security_state); + copy_cpu_ctx_to_smc_ctx(get_regs_ctx(cm_get_next_context()), + smc_get_next_ctx()); + + /* + * Flush the SMC & CPU context and the (next)pointers, + * to access them after caches are disabled. + */ + flush_smc_and_cpu_ctx(); + + /* Indicate that image is in execution state. */ + image_desc->state = IMAGE_STATE_EXECUTED; + + print_entry_point_info(next_bl_ep); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch32/bl1_entrypoint.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch32/bl1_entrypoint.S new file mode 100644 index 0000000..b881786 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch32/bl1_entrypoint.S @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + + .globl bl1_vector_table + .globl bl1_entrypoint + + /* ----------------------------------------------------- + * Setup the vector table to support SVC & MON mode. + * ----------------------------------------------------- + */ +vector_base bl1_vector_table + b bl1_entrypoint + b report_exception /* Undef */ + b bl1_aarch32_smc_handler /* SMC call */ + b report_exception /* Prefetch abort */ + b report_exception /* Data abort */ + b report_exception /* Reserved */ + b report_exception /* IRQ */ + b report_exception /* FIQ */ + + /* ----------------------------------------------------- + * bl1_entrypoint() is the entry point into the trusted + * firmware code when a cpu is released from warm or + * cold reset. + * ----------------------------------------------------- + */ + +func bl1_entrypoint +/* --------------------------------------------------------------------- +* If the reset address is programmable then bl1_entrypoint() is +* executed only on the cold boot path. Therefore, we can skip the warm +* boot mailbox mechanism. +* --------------------------------------------------------------------- +*/ + el3_entrypoint_common \ + _set_endian=1 \ + _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ + _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ + _init_memory=1 \ + _init_c_runtime=1 \ + _exception_vectors=bl1_vector_table + + /* ----------------------------------------------------- + * Perform early platform setup & platform + * specific early arch. setup e.g. mmu setup + * ----------------------------------------------------- + */ + bl bl1_early_platform_setup + bl bl1_plat_arch_setup + + /* ----------------------------------------------------- + * Jump to main function. + * ----------------------------------------------------- + */ + bl bl1_main + + /* ----------------------------------------------------- + * Jump to next image. + * ----------------------------------------------------- + */ + + /* + * MMU needs to be disabled because both BL1 and BL2 execute + * in PL1, and therefore share the same address space. + * BL2 will initialize the address space according to its + * own requirement. + */ + bl disable_mmu_icache_secure + stcopr r0, TLBIALL + dsb sy + isb + + /* Get the cpu_context for next BL image */ + bl cm_get_next_context + + /* Restore the SCR */ + ldr r2, [r0, #CTX_REGS_OFFSET + CTX_SCR] + stcopr r2, SCR + isb + + /* + * Get the smc_context for next BL image, + * program the gp/system registers and exit + * secure monitor mode + */ + bl smc_get_next_ctx + smcc_restore_gp_mode_regs + eret +endfunc bl1_entrypoint diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch32/bl1_exceptions.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch32/bl1_exceptions.S new file mode 100644 index 0000000..e109e9f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch32/bl1_exceptions.S @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + .globl bl1_aarch32_smc_handler + + +func bl1_aarch32_smc_handler + /* ------------------------------------------------ + * SMC in BL1 is handled assuming that the MMU is + * turned off by BL2. + * ------------------------------------------------ + */ + + /* ---------------------------------------------- + * Only RUN_IMAGE SMC is supported. + * ---------------------------------------------- + */ + mov r8, #BL1_SMC_RUN_IMAGE + cmp r8, r0 + blne report_exception + + /* ------------------------------------------------ + * Make sure only Secure world reaches here. + * ------------------------------------------------ + */ + ldcopr r8, SCR + tst r8, #SCR_NS_BIT + blne report_exception + + /* --------------------------------------------------------------------- + * Pass control to next secure image. + * Here it expects r1 to contain the address of a entry_point_info_t + * structure describing the BL entrypoint. + * --------------------------------------------------------------------- + */ + mov r8, r1 + mov r0, r1 + bl bl1_print_next_bl_ep_info + +#if SPIN_ON_BL1_EXIT + bl print_debug_loop_message +debug_loop: + b debug_loop +#endif + + mov r0, r8 + bl bl1_plat_prepare_exit + + stcopr r0, TLBIALL + dsb sy + isb + + /* + * Extract PC and SPSR based on struct `entry_point_info_t` + * and load it in LR and SPSR registers respectively. + */ + ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] + ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] + msr spsr, r1 + + add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET + ldm r8, {r0, r1, r2, r3} + eret +endfunc bl1_aarch32_smc_handler diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch64/bl1_arch_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch64/bl1_arch_setup.c new file mode 100644 index 0000000..61c01e1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch64/bl1_arch_setup.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/******************************************************************************* + * Function that does the first bit of architectural setup that affects + * execution in the non-secure address space. + ******************************************************************************/ +void bl1_arch_setup(void) +{ + /* Set the next EL to be AArch64 */ + write_scr_el3(read_scr_el3() | SCR_RW_BIT); +} + +/******************************************************************************* + * Set the Secure EL1 required architectural state + ******************************************************************************/ +void bl1_arch_next_el_setup(void) +{ + unsigned long next_sctlr; + + /* Use the same endianness than the current BL */ + next_sctlr = (read_sctlr_el3() & SCTLR_EE_BIT); + + /* Set SCTLR Secure EL1 */ + next_sctlr |= SCTLR_EL1_RES1; + + write_sctlr_el1(next_sctlr); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch64/bl1_context_mgmt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch64/bl1_context_mgmt.c new file mode 100644 index 0000000..972c7f6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch64/bl1_context_mgmt.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* + * Following array will be used for context management. + * There are 2 instances, for the Secure and Non-Secure contexts. + */ +static cpu_context_t bl1_cpu_context[2]; + +/* Following contains the cpu context pointers. */ +static void *bl1_cpu_context_ptr[2]; + + +void *cm_get_context(uint32_t security_state) +{ + assert(sec_state_is_valid(security_state)); + return bl1_cpu_context_ptr[security_state]; +} + +void cm_set_context(void *context, uint32_t security_state) +{ + assert(sec_state_is_valid(security_state)); + bl1_cpu_context_ptr[security_state] = context; +} + +/******************************************************************************* + * This function prepares the context for Secure/Normal world images. + * Normal world images are transitioned to EL2(if supported) else EL1. + ******************************************************************************/ +void bl1_prepare_next_image(unsigned int image_id) +{ + unsigned int security_state; + image_desc_t *image_desc; + entry_point_info_t *next_bl_ep; + +#if CTX_INCLUDE_AARCH32_REGS + /* + * Ensure that the build flag to save AArch32 system registers in CPU + * context is not set for AArch64-only platforms. + */ + if (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL1_SHIFT) + & ID_AA64PFR0_ELX_MASK) == 0x1) { + ERROR("EL1 supports AArch64-only. Please set build flag " + "CTX_INCLUDE_AARCH32_REGS = 0"); + panic(); + } +#endif + + /* Get the image descriptor. */ + image_desc = bl1_plat_get_image_desc(image_id); + assert(image_desc); + + /* Get the entry point info. */ + next_bl_ep = &image_desc->ep_info; + + /* Get the image security state. */ + security_state = GET_SECURITY_STATE(next_bl_ep->h.attr); + + /* Setup the Secure/Non-Secure context if not done already. */ + if (!cm_get_context(security_state)) + cm_set_context(&bl1_cpu_context[security_state], security_state); + + /* Prepare the SPSR for the next BL image. */ + if (security_state == SECURE) { + next_bl_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + } else { + /* Use EL2 if supported else use EL1. */ + if (read_id_aa64pfr0_el1() & + (ID_AA64PFR0_ELX_MASK << ID_AA64PFR0_EL2_SHIFT)) { + next_bl_ep->spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + } else { + next_bl_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + } + } + + /* Allow platform to make change */ + bl1_plat_set_ep_info(image_id, next_bl_ep); + + /* Prepare the context for the next BL image. */ + cm_init_my_context(next_bl_ep); + cm_prepare_el3_exit(security_state); + + /* Indicate that image is in execution state. */ + image_desc->state = IMAGE_STATE_EXECUTED; + + print_entry_point_info(next_bl_ep); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch64/bl1_entrypoint.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch64/bl1_entrypoint.S new file mode 100644 index 0000000..ce27752 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch64/bl1_entrypoint.S @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl bl1_entrypoint + + + /* ----------------------------------------------------- + * bl1_entrypoint() is the entry point into the trusted + * firmware code when a cpu is released from warm or + * cold reset. + * ----------------------------------------------------- + */ + +func bl1_entrypoint + /* --------------------------------------------------------------------- + * If the reset address is programmable then bl1_entrypoint() is + * executed only on the cold boot path. Therefore, we can skip the warm + * boot mailbox mechanism. + * --------------------------------------------------------------------- + */ + el3_entrypoint_common \ + _set_endian=1 \ + _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ + _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ + _init_memory=1 \ + _init_c_runtime=1 \ + _exception_vectors=bl1_exceptions + + /* --------------------------------------------- + * Architectural init. can be generic e.g. + * enabling stack alignment and platform spec- + * ific e.g. MMU & page table setup as per the + * platform memory map. Perform the latter here + * and the former in bl1_main. + * --------------------------------------------- + */ + bl bl1_early_platform_setup + bl bl1_plat_arch_setup + + /* -------------------------------------------------- + * Initialize platform and jump to our c-entry point + * for this type of reset. + * -------------------------------------------------- + */ + bl bl1_main + + /* -------------------------------------------------- + * Do the transition to next boot image. + * -------------------------------------------------- + */ + b el3_exit +endfunc bl1_entrypoint diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch64/bl1_exceptions.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch64/bl1_exceptions.S new file mode 100644 index 0000000..869261d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/aarch64/bl1_exceptions.S @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/* ----------------------------------------------------------------------------- + * Very simple stackless exception handlers used by BL1. + * ----------------------------------------------------------------------------- + */ + .globl bl1_exceptions + +vector_base bl1_exceptions + + /* ----------------------------------------------------- + * Current EL with SP0 : 0x0 - 0x200 + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionSP0 + mov x0, #SYNC_EXCEPTION_SP_EL0 + bl plat_report_exception + bl plat_panic_handler + check_vector_size SynchronousExceptionSP0 + +vector_entry IrqSP0 + mov x0, #IRQ_SP_EL0 + bl plat_report_exception + bl plat_panic_handler + check_vector_size IrqSP0 + +vector_entry FiqSP0 + mov x0, #FIQ_SP_EL0 + bl plat_report_exception + bl plat_panic_handler + check_vector_size FiqSP0 + +vector_entry SErrorSP0 + mov x0, #SERROR_SP_EL0 + bl plat_report_exception + bl plat_panic_handler + check_vector_size SErrorSP0 + + /* ----------------------------------------------------- + * Current EL with SPx: 0x200 - 0x400 + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionSPx + mov x0, #SYNC_EXCEPTION_SP_ELX + bl plat_report_exception + bl plat_panic_handler + check_vector_size SynchronousExceptionSPx + +vector_entry IrqSPx + mov x0, #IRQ_SP_ELX + bl plat_report_exception + bl plat_panic_handler + check_vector_size IrqSPx + +vector_entry FiqSPx + mov x0, #FIQ_SP_ELX + bl plat_report_exception + bl plat_panic_handler + check_vector_size FiqSPx + +vector_entry SErrorSPx + mov x0, #SERROR_SP_ELX + bl plat_report_exception + bl plat_panic_handler + check_vector_size SErrorSPx + + /* ----------------------------------------------------- + * Lower EL using AArch64 : 0x400 - 0x600 + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionA64 + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + + /* Expect only SMC exceptions */ + mrs x30, esr_el3 + ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH + cmp x30, #EC_AARCH64_SMC + b.ne unexpected_sync_exception + + b smc_handler64 + check_vector_size SynchronousExceptionA64 + +vector_entry IrqA64 + mov x0, #IRQ_AARCH64 + bl plat_report_exception + bl plat_panic_handler + check_vector_size IrqA64 + +vector_entry FiqA64 + mov x0, #FIQ_AARCH64 + bl plat_report_exception + bl plat_panic_handler + check_vector_size FiqA64 + +vector_entry SErrorA64 + mov x0, #SERROR_AARCH64 + bl plat_report_exception + bl plat_panic_handler + check_vector_size SErrorA64 + + /* ----------------------------------------------------- + * Lower EL using AArch32 : 0x600 - 0x800 + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionA32 + mov x0, #SYNC_EXCEPTION_AARCH32 + bl plat_report_exception + bl plat_panic_handler + check_vector_size SynchronousExceptionA32 + +vector_entry IrqA32 + mov x0, #IRQ_AARCH32 + bl plat_report_exception + bl plat_panic_handler + check_vector_size IrqA32 + +vector_entry FiqA32 + mov x0, #FIQ_AARCH32 + bl plat_report_exception + bl plat_panic_handler + check_vector_size FiqA32 + +vector_entry SErrorA32 + mov x0, #SERROR_AARCH32 + bl plat_report_exception + bl plat_panic_handler + check_vector_size SErrorA32 + + +func smc_handler64 + + /* ---------------------------------------------- + * Detect if this is a RUN_IMAGE or other SMC. + * ---------------------------------------------- + */ + mov x30, #BL1_SMC_RUN_IMAGE + cmp x30, x0 + b.ne smc_handler + + /* ------------------------------------------------ + * Make sure only Secure world reaches here. + * ------------------------------------------------ + */ + mrs x30, scr_el3 + tst x30, #SCR_NS_BIT + b.ne unexpected_sync_exception + + /* ---------------------------------------------- + * Handling RUN_IMAGE SMC. First switch back to + * SP_EL0 for the C runtime stack. + * ---------------------------------------------- + */ + ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] + msr spsel, #0 + mov sp, x30 + + /* --------------------------------------------------------------------- + * Pass EL3 control to next BL image. + * Here it expects X1 with the address of a entry_point_info_t + * structure describing the next BL image entrypoint. + * --------------------------------------------------------------------- + */ + mov x20, x1 + + mov x0, x20 + bl bl1_print_next_bl_ep_info + + ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] + msr elr_el3, x0 + msr spsr_el3, x1 + ubfx x0, x1, #MODE_EL_SHIFT, #2 + cmp x0, #MODE_EL3 + b.ne unexpected_sync_exception + + bl disable_mmu_icache_el3 + tlbi alle3 + +#if SPIN_ON_BL1_EXIT + bl print_debug_loop_message +debug_loop: + b debug_loop +#endif + + mov x0, x20 + bl bl1_plat_prepare_exit + + ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] + ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] + ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] + ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] + eret +endfunc smc_handler64 + +unexpected_sync_exception: + mov x0, #SYNC_EXCEPTION_AARCH64 + bl plat_report_exception + bl plat_panic_handler + + /* ----------------------------------------------------- + * Save Secure/Normal world context and jump to + * BL1 SMC handler. + * ----------------------------------------------------- + */ +smc_handler: + /* ----------------------------------------------------- + * Save the GP registers x0-x29. + * TODO: Revisit to store only SMCC specified registers. + * ----------------------------------------------------- + */ + bl save_gp_registers + + /* ----------------------------------------------------- + * Populate the parameters for the SMC handler. We + * already have x0-x4 in place. x5 will point to a + * cookie (not used now). x6 will point to the context + * structure (SP_EL3) and x7 will contain flags we need + * to pass to the handler. + * ----------------------------------------------------- + */ + mov x5, xzr + mov x6, sp + + /* ----------------------------------------------------- + * Restore the saved C runtime stack value which will + * become the new SP_EL0 i.e. EL3 runtime stack. It was + * saved in the 'cpu_context' structure prior to the last + * ERET from EL3. + * ----------------------------------------------------- + */ + ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] + + /* --------------------------------------------- + * Switch back to SP_EL0 for the C runtime stack. + * --------------------------------------------- + */ + msr spsel, #0 + mov sp, x12 + + /* ----------------------------------------------------- + * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there + * is a world switch during SMC handling. + * ----------------------------------------------------- + */ + mrs x16, spsr_el3 + mrs x17, elr_el3 + mrs x18, scr_el3 + stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] + str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] + + /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ + bfi x7, x18, #0, #1 + + /* ----------------------------------------------------- + * Go to BL1 SMC handler. + * ----------------------------------------------------- + */ + bl bl1_smc_handler + + /* ----------------------------------------------------- + * Do the transition to next BL image. + * ----------------------------------------------------- + */ + b el3_exit diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1.ld.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1.ld.S new file mode 100644 index 0000000..b9554d1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1.ld.S @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) +OUTPUT_ARCH(PLATFORM_LINKER_ARCH) +ENTRY(bl1_entrypoint) + +MEMORY { + ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE + RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE +} + +SECTIONS +{ + . = BL1_RO_BASE; + ASSERT(. == ALIGN(4096), + "BL1_RO_BASE address is not aligned on a page boundary.") + +#if SEPARATE_CODE_AND_RODATA + .text . : { + __TEXT_START__ = .; + *bl1_entrypoint.o(.text*) + *(.text*) + *(.vectors) + . = NEXT(4096); + __TEXT_END__ = .; + } >ROM + + .rodata . : { + __RODATA_START__ = .; + *(.rodata*) + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __PARSER_LIB_DESCS_START__ = .; + KEEP(*(.img_parser_lib_descs)) + __PARSER_LIB_DESCS_END__ = .; + + /* + * Ensure 8-byte alignment for cpu_ops so that its fields are also + * aligned. Also ensure cpu_ops inclusion. + */ + . = ALIGN(8); + __CPU_OPS_START__ = .; + KEEP(*(cpu_ops)) + __CPU_OPS_END__ = .; + + /* + * No need to pad out the .rodata section to a page boundary. Next is + * the .data section, which can mapped in ROM with the same memory + * attributes as the .rodata section. + */ + __RODATA_END__ = .; + } >ROM +#else + ro . : { + __RO_START__ = .; + *bl1_entrypoint.o(.text*) + *(.text*) + *(.rodata*) + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __PARSER_LIB_DESCS_START__ = .; + KEEP(*(.img_parser_lib_descs)) + __PARSER_LIB_DESCS_END__ = .; + + /* + * Ensure 8-byte alignment for cpu_ops so that its fields are also + * aligned. Also ensure cpu_ops inclusion. + */ + . = ALIGN(8); + __CPU_OPS_START__ = .; + KEEP(*(cpu_ops)) + __CPU_OPS_END__ = .; + + *(.vectors) + __RO_END__ = .; + } >ROM +#endif + + ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, + "cpu_ops not defined for this platform.") + + /* + * The .data section gets copied from ROM to RAM at runtime. + * Its LMA must be 16-byte aligned. + * Its VMA must be page-aligned as it marks the first read/write page. + */ + . = BL1_RW_BASE; + ASSERT(. == ALIGN(4096), + "BL1_RW_BASE address is not aligned on a page boundary.") + .data . : ALIGN(16) { + __DATA_RAM_START__ = .; + *(.data*) + __DATA_RAM_END__ = .; + } >RAM AT>ROM + + stacks . (NOLOAD) : { + __STACKS_START__ = .; + *(tzfw_normal_stacks) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss : ALIGN(16) { + __BSS_START__ = .; + *(.bss*) + *(COMMON) + __BSS_END__ = .; + } >RAM + + /* + * The xlat_table section is for full, aligned page tables (4K). + * Removing them from .bss avoids forcing 4K alignment on + * the .bss section and eliminates the unecessary zero init + */ + xlat_table (NOLOAD) : { + *(xlat_table) + } >RAM + +#if USE_COHERENT_MEM + /* + * The base address of the coherent memory section must be page-aligned (4K) + * to guarantee that the coherent data are stored on their own pages and + * are not mixed with normal data. This is required to set up the correct + * memory attributes for the coherent data page tables. + */ + coherent_ram (NOLOAD) : ALIGN(4096) { + __COHERENT_RAM_START__ = .; + *(tzfw_coherent_mem) + __COHERENT_RAM_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked + * as device memory. No other unexpected data must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __COHERENT_RAM_END__ = .; + } >RAM +#endif + + __BL1_RAM_START__ = ADDR(.data); + __BL1_RAM_END__ = .; + + __DATA_ROM_START__ = LOADADDR(.data); + __DATA_SIZE__ = SIZEOF(.data); + + /* + * The .data section is the last PROGBITS section so its end marks the end + * of BL1's actual content in Trusted ROM. + */ + __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__; + ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT, + "BL1's ROM content has exceeded its limit.") + + __BSS_SIZE__ = SIZEOF(.bss); + +#if USE_COHERENT_MEM + __COHERENT_RAM_UNALIGNED_SIZE__ = + __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; +#endif + + ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.") +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1.mk new file mode 100644 index 0000000..9ef5b40 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1.mk @@ -0,0 +1,49 @@ +# +# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +BL1_SOURCES += bl1/bl1_main.c \ + bl1/${ARCH}/bl1_arch_setup.c \ + bl1/${ARCH}/bl1_context_mgmt.c \ + bl1/${ARCH}/bl1_entrypoint.S \ + bl1/${ARCH}/bl1_exceptions.S \ + lib/cpus/${ARCH}/cpu_helpers.S \ + lib/el3_runtime/${ARCH}/context_mgmt.c \ + plat/common/plat_bl1_common.c + + +ifeq (${ARCH},aarch64) +BL1_SOURCES += lib/el3_runtime/aarch64/context.S +endif + +ifeq (${TRUSTED_BOARD_BOOT},1) +BL1_SOURCES += bl1/bl1_fwu.c +endif + +BL1_LINKERFILE := bl1/bl1.ld.S diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1_fwu.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1_fwu.c new file mode 100644 index 0000000..f333805 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1_fwu.c @@ -0,0 +1,507 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "bl1_private.h" + +/* + * Function declarations. + */ +static int bl1_fwu_image_copy(unsigned int image_id, + uintptr_t image_addr, + unsigned int block_size, + unsigned int image_size, + unsigned int flags); +static int bl1_fwu_image_auth(unsigned int image_id, + uintptr_t image_addr, + unsigned int image_size, + unsigned int flags); +static int bl1_fwu_image_execute(unsigned int image_id, + void **handle, + unsigned int flags); +static register_t bl1_fwu_image_resume(register_t image_param, + void **handle, + unsigned int flags); +static int bl1_fwu_sec_image_done(void **handle, + unsigned int flags); +__dead2 static void bl1_fwu_done(void *client_cookie, void *reserved); + +/* + * This keeps track of last executed secure image id. + */ +static unsigned int sec_exec_image_id = INVALID_IMAGE_ID; + +/******************************************************************************* + * Top level handler for servicing FWU SMCs. + ******************************************************************************/ +register_t bl1_fwu_smc_handler(unsigned int smc_fid, + register_t x1, + register_t x2, + register_t x3, + register_t x4, + void *cookie, + void *handle, + unsigned int flags) +{ + + switch (smc_fid) { + case FWU_SMC_IMAGE_COPY: + SMC_RET1(handle, bl1_fwu_image_copy(x1, x2, x3, x4, flags)); + + case FWU_SMC_IMAGE_AUTH: + SMC_RET1(handle, bl1_fwu_image_auth(x1, x2, x3, flags)); + + case FWU_SMC_IMAGE_EXECUTE: + SMC_RET1(handle, bl1_fwu_image_execute(x1, &handle, flags)); + + case FWU_SMC_IMAGE_RESUME: + SMC_RET1(handle, bl1_fwu_image_resume(x1, &handle, flags)); + + case FWU_SMC_SEC_IMAGE_DONE: + SMC_RET1(handle, bl1_fwu_sec_image_done(&handle, flags)); + + case FWU_SMC_UPDATE_DONE: + bl1_fwu_done((void *)x1, NULL); + /* We should never return from bl1_fwu_done() */ + + default: + assert(0); + break; + } + + SMC_RET0(handle); +} + +/******************************************************************************* + * This function is responsible for copying secure images in AP Secure RAM. + ******************************************************************************/ +static int bl1_fwu_image_copy(unsigned int image_id, + uintptr_t image_src, + unsigned int block_size, + unsigned int image_size, + unsigned int flags) +{ + uintptr_t base_addr; + meminfo_t *mem_layout; + + /* Get the image descriptor. */ + image_desc_t *image_desc = bl1_plat_get_image_desc(image_id); + + /* Check if we are in correct state. */ + if ((!image_desc) || + ((image_desc->state != IMAGE_STATE_RESET) && + (image_desc->state != IMAGE_STATE_COPYING))) { + WARN("BL1-FWU: Copy not allowed due to invalid state\n"); + return -EPERM; + } + + /* Only Normal world is allowed to copy a Secure image. */ + if ((GET_SECURITY_STATE(flags) == SECURE) || + (GET_SECURITY_STATE(image_desc->ep_info.h.attr) == NON_SECURE)) { + WARN("BL1-FWU: Copy not allowed for Non-Secure " + "image from Secure-world\n"); + return -EPERM; + } + + if ((!image_src) || (!block_size)) { + WARN("BL1-FWU: Copy not allowed due to invalid image source" + " or block size\n"); + return -ENOMEM; + } + + /* Get the image base address. */ + base_addr = image_desc->image_info.image_base; + + if (image_desc->state == IMAGE_STATE_COPYING) { + /* + * If last block is more than expected then + * clip the block to the required image size. + */ + if (image_desc->copied_size + block_size > + image_desc->image_info.image_size) { + block_size = image_desc->image_info.image_size - + image_desc->copied_size; + WARN("BL1-FWU: Copy argument block_size > remaining image size." + " Clipping block_size\n"); + } + + /* Make sure the image src/size is mapped. */ + if (bl1_plat_mem_check(image_src, block_size, flags)) { + WARN("BL1-FWU: Copy arguments source/size not mapped\n"); + return -ENOMEM; + } + + INFO("BL1-FWU: Continuing image copy in blocks\n"); + + /* Copy image for given block size. */ + base_addr += image_desc->copied_size; + image_desc->copied_size += block_size; + memcpy((void *)base_addr, (const void *)image_src, block_size); + flush_dcache_range(base_addr, block_size); + + /* Update the state if last block. */ + if (image_desc->copied_size == + image_desc->image_info.image_size) { + image_desc->state = IMAGE_STATE_COPIED; + INFO("BL1-FWU: Image copy in blocks completed\n"); + } + } else { + /* This means image is in RESET state and ready to be copied. */ + INFO("BL1-FWU: Fresh call to copy an image\n"); + + if (!image_size) { + WARN("BL1-FWU: Copy not allowed due to invalid image size\n"); + return -ENOMEM; + } + + /* + * If block size is more than total size then + * assume block size as the total image size. + */ + if (block_size > image_size) { + block_size = image_size; + WARN("BL1-FWU: Copy argument block_size > image size." + " Clipping block_size\n"); + } + + /* Make sure the image src/size is mapped. */ + if (bl1_plat_mem_check(image_src, block_size, flags)) { + WARN("BL1-FWU: Copy arguments source/size not mapped\n"); + return -ENOMEM; + } + + /* Find out how much free trusted ram remains after BL1 load */ + mem_layout = bl1_plat_sec_mem_layout(); + if ((image_desc->image_info.image_base < mem_layout->free_base) || + (image_desc->image_info.image_base + image_size > + mem_layout->free_base + mem_layout->free_size)) { + WARN("BL1-FWU: Memory not available to copy\n"); + return -ENOMEM; + } + + /* Update the image size. */ + image_desc->image_info.image_size = image_size; + + /* Copy image for given size. */ + memcpy((void *)base_addr, (const void *)image_src, block_size); + flush_dcache_range(base_addr, block_size); + + /* Update the state. */ + if (block_size == image_size) { + image_desc->state = IMAGE_STATE_COPIED; + INFO("BL1-FWU: Image is copied successfully\n"); + } else { + image_desc->state = IMAGE_STATE_COPYING; + INFO("BL1-FWU: Started image copy in blocks\n"); + } + + image_desc->copied_size = block_size; + } + + return 0; +} + +/******************************************************************************* + * This function is responsible for authenticating Normal/Secure images. + ******************************************************************************/ +static int bl1_fwu_image_auth(unsigned int image_id, + uintptr_t image_src, + unsigned int image_size, + unsigned int flags) +{ + int result; + uintptr_t base_addr; + unsigned int total_size; + + /* Get the image descriptor. */ + image_desc_t *image_desc = bl1_plat_get_image_desc(image_id); + if (!image_desc) + return -EPERM; + + if (GET_SECURITY_STATE(flags) == SECURE) { + if (image_desc->state != IMAGE_STATE_RESET) { + WARN("BL1-FWU: Authentication from secure world " + "while in invalid state\n"); + return -EPERM; + } + } else { + if (GET_SECURITY_STATE(image_desc->ep_info.h.attr) == SECURE) { + if (image_desc->state != IMAGE_STATE_COPIED) { + WARN("BL1-FWU: Authentication of secure image " + "from non-secure world while not in copied state\n"); + return -EPERM; + } + } else { + if (image_desc->state != IMAGE_STATE_RESET) { + WARN("BL1-FWU: Authentication of non-secure image " + "from non-secure world while in invalid state\n"); + return -EPERM; + } + } + } + + if (image_desc->state == IMAGE_STATE_COPIED) { + /* + * Image is in COPIED state. + * Use the stored address and size. + */ + base_addr = image_desc->image_info.image_base; + total_size = image_desc->image_info.image_size; + } else { + if ((!image_src) || (!image_size)) { + WARN("BL1-FWU: Auth not allowed due to invalid" + " image source/size\n"); + return -ENOMEM; + } + + /* + * Image is in RESET state. + * Check the parameters and authenticate the source image in place. + */ + if (bl1_plat_mem_check(image_src, image_size, \ + image_desc->ep_info.h.attr)) { + WARN("BL1-FWU: Authentication arguments source/size not mapped\n"); + return -ENOMEM; + } + + base_addr = image_src; + total_size = image_size; + + /* Update the image size in the descriptor. */ + image_desc->image_info.image_size = total_size; + } + + /* + * Authenticate the image. + */ + INFO("BL1-FWU: Authenticating image_id:%d\n", image_id); + result = auth_mod_verify_img(image_id, (void *)base_addr, total_size); + if (result != 0) { + WARN("BL1-FWU: Authentication Failed err=%d\n", result); + + /* + * Authentication has failed. + * Clear the memory if the image was copied. + * This is to prevent an attack where this contains + * some malicious code that can somehow be executed later. + */ + if (image_desc->state == IMAGE_STATE_COPIED) { + /* Clear the memory.*/ + memset((void *)base_addr, 0, total_size); + flush_dcache_range(base_addr, total_size); + + /* Indicate that image can be copied again*/ + image_desc->state = IMAGE_STATE_RESET; + } + return -EAUTH; + } + + /* Indicate that image is in authenticated state. */ + image_desc->state = IMAGE_STATE_AUTHENTICATED; + + /* + * Flush image_info to memory so that other + * secure world images can see changes. + */ + flush_dcache_range((unsigned long)&image_desc->image_info, + sizeof(image_info_t)); + + INFO("BL1-FWU: Authentication was successful\n"); + + return 0; +} + +/******************************************************************************* + * This function is responsible for executing Secure images. + ******************************************************************************/ +static int bl1_fwu_image_execute(unsigned int image_id, + void **handle, + unsigned int flags) +{ + /* Get the image descriptor. */ + image_desc_t *image_desc = bl1_plat_get_image_desc(image_id); + + /* + * Execution is NOT allowed if: + * image_id is invalid OR + * Caller is from Secure world OR + * Image is Non-Secure OR + * Image is Non-Executable OR + * Image is NOT in AUTHENTICATED state. + */ + if ((!image_desc) || + (GET_SECURITY_STATE(flags) == SECURE) || + (GET_SECURITY_STATE(image_desc->ep_info.h.attr) == NON_SECURE) || + (EP_GET_EXE(image_desc->ep_info.h.attr) == NON_EXECUTABLE) || + (image_desc->state != IMAGE_STATE_AUTHENTICATED)) { + WARN("BL1-FWU: Execution not allowed due to invalid state/args\n"); + return -EPERM; + } + + INFO("BL1-FWU: Executing Secure image\n"); + + /* Save NS-EL1 system registers. */ + cm_el1_sysregs_context_save(NON_SECURE); + + /* Prepare the image for execution. */ + bl1_prepare_next_image(image_id); + + /* Update the secure image id. */ + sec_exec_image_id = image_id; + + *handle = cm_get_context(SECURE); + return 0; +} + +/******************************************************************************* + * This function is responsible for resuming execution in the other security + * world + ******************************************************************************/ +static register_t bl1_fwu_image_resume(register_t image_param, + void **handle, + unsigned int flags) +{ + image_desc_t *image_desc; + unsigned int resume_sec_state; + unsigned int caller_sec_state = GET_SECURITY_STATE(flags); + + /* Get the image descriptor for last executed secure image id. */ + image_desc = bl1_plat_get_image_desc(sec_exec_image_id); + if (caller_sec_state == NON_SECURE) { + if (!image_desc) { + WARN("BL1-FWU: Resume not allowed due to no available" + "secure image\n"); + return -EPERM; + } + } else { + /* image_desc must be valid for secure world callers */ + assert(image_desc); + } + + assert(GET_SECURITY_STATE(image_desc->ep_info.h.attr) == SECURE); + assert(EP_GET_EXE(image_desc->ep_info.h.attr) == EXECUTABLE); + + if (caller_sec_state == SECURE) { + assert(image_desc->state == IMAGE_STATE_EXECUTED); + + /* Update the flags. */ + image_desc->state = IMAGE_STATE_INTERRUPTED; + resume_sec_state = NON_SECURE; + } else { + assert(image_desc->state == IMAGE_STATE_INTERRUPTED); + + /* Update the flags. */ + image_desc->state = IMAGE_STATE_EXECUTED; + resume_sec_state = SECURE; + } + + /* Save the EL1 system registers of calling world. */ + cm_el1_sysregs_context_save(caller_sec_state); + + /* Restore the EL1 system registers of resuming world. */ + cm_el1_sysregs_context_restore(resume_sec_state); + + /* Update the next context. */ + cm_set_next_eret_context(resume_sec_state); + + INFO("BL1-FWU: Resuming %s world context\n", + (resume_sec_state == SECURE) ? "secure" : "normal"); + + *handle = cm_get_context(resume_sec_state); + return image_param; +} + +/******************************************************************************* + * This function is responsible for resuming normal world context. + ******************************************************************************/ +static int bl1_fwu_sec_image_done(void **handle, unsigned int flags) +{ + image_desc_t *image_desc; + + /* Make sure caller is from the secure world */ + if (GET_SECURITY_STATE(flags) == NON_SECURE) { + WARN("BL1-FWU: Image done not allowed from normal world\n"); + return -EPERM; + } + + /* Get the image descriptor for last executed secure image id */ + image_desc = bl1_plat_get_image_desc(sec_exec_image_id); + + /* image_desc must correspond to a valid secure executing image */ + assert(image_desc); + assert(GET_SECURITY_STATE(image_desc->ep_info.h.attr) == SECURE); + assert(EP_GET_EXE(image_desc->ep_info.h.attr) == EXECUTABLE); + assert(image_desc->state == IMAGE_STATE_EXECUTED); + + /* Update the flags. */ + image_desc->state = IMAGE_STATE_RESET; + sec_exec_image_id = INVALID_IMAGE_ID; + + /* + * Secure world is done so no need to save the context. + * Just restore the Non-Secure context. + */ + cm_el1_sysregs_context_restore(NON_SECURE); + + /* Update the next context. */ + cm_set_next_eret_context(NON_SECURE); + + INFO("BL1-FWU: Resuming Normal world context\n"); + + *handle = cm_get_context(NON_SECURE); + return 0; +} + +/******************************************************************************* + * This function provides the opportunity for users to perform any + * platform specific handling after the Firmware update is done. + ******************************************************************************/ +__dead2 static void bl1_fwu_done(void *client_cookie, void *reserved) +{ + NOTICE("BL1-FWU: *******FWU Process Completed*******\n"); + + /* + * Call platform done function. + */ + bl1_plat_fwu_done(client_cookie, reserved); + assert(0); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1_main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1_main.c new file mode 100644 index 0000000..fbb75e0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1_main.c @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "bl1_private.h" +#include + +/* BL1 Service UUID */ +DEFINE_SVC_UUID(bl1_svc_uid, + 0xfd3967d4, 0x72cb, 0x4d9a, 0xb5, 0x75, + 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); + + +static void bl1_load_bl2(void); + +/******************************************************************************* + * The next function has a weak definition. Platform specific code can override + * it if it wishes to. + ******************************************************************************/ +#pragma weak bl1_init_bl2_mem_layout + +/******************************************************************************* + * Function that takes a memory layout into which BL2 has been loaded and + * populates a new memory layout for BL2 that ensures that BL1's data sections + * resident in secure RAM are not visible to BL2. + ******************************************************************************/ +void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, + meminfo_t *bl2_mem_layout) +{ + + assert(bl1_mem_layout != NULL); + assert(bl2_mem_layout != NULL); + +#if LOAD_IMAGE_V2 + /* + * Remove BL1 RW data from the scope of memory visible to BL2. + * This is assuming BL1 RW data is at the top of bl1_mem_layout. + */ + assert(BL1_RW_BASE > bl1_mem_layout->total_base); + bl2_mem_layout->total_base = bl1_mem_layout->total_base; + bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base; +#else + /* Check that BL1's memory is lying outside of the free memory */ + assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) || + (BL1_RAM_BASE >= bl1_mem_layout->free_base + + bl1_mem_layout->free_size)); + + /* Remove BL1 RW data from the scope of memory visible to BL2 */ + *bl2_mem_layout = *bl1_mem_layout; + reserve_mem(&bl2_mem_layout->total_base, + &bl2_mem_layout->total_size, + BL1_RAM_BASE, + BL1_RAM_LIMIT - BL1_RAM_BASE); +#endif /* LOAD_IMAGE_V2 */ + + flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); +} + +/******************************************************************************* + * Function to perform late architectural and platform specific initialization. + * It also queries the platform to load and run next BL image. Only called + * by the primary cpu after a cold boot. + ******************************************************************************/ +void bl1_main(void) +{ + unsigned int image_id; + + /* Announce our arrival */ + NOTICE(FIRMWARE_WELCOME_STR); + NOTICE("BL1: %s\n", version_string); + NOTICE("BL1: %s\n", build_message); + + INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE, + (void *)BL1_RAM_LIMIT); + + +#if DEBUG + u_register_t val; + /* + * Ensure that MMU/Caches and coherency are turned on + */ +#ifdef AARCH32 + val = read_sctlr(); +#else + val = read_sctlr_el3(); +#endif + assert(val & SCTLR_M_BIT); + assert(val & SCTLR_C_BIT); + assert(val & SCTLR_I_BIT); + /* + * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the + * provided platform value + */ + val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; + /* + * If CWG is zero, then no CWG information is available but we can + * at least check the platform value is less than the architectural + * maximum. + */ + if (val != 0) + assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val)); + else + assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE); +#endif + + /* Perform remaining generic architectural setup from EL3 */ + bl1_arch_setup(); + +#if TRUSTED_BOARD_BOOT + /* Initialize authentication module */ + auth_mod_init(); +#endif /* TRUSTED_BOARD_BOOT */ + + /* Perform platform setup in BL1. */ + bl1_platform_setup(); + + /* Get the image id of next image to load and run. */ + image_id = bl1_plat_get_next_image_id(); + + /* + * We currently interpret any image id other than + * BL2_IMAGE_ID as the start of firmware update. + */ + if (image_id == BL2_IMAGE_ID) + bl1_load_bl2(); + else + NOTICE("BL1-FWU: *******FWU Process Started*******\n"); + + bl1_prepare_next_image(image_id); +} + +/******************************************************************************* + * This function locates and loads the BL2 raw binary image in the trusted SRAM. + * Called by the primary cpu after a cold boot. + * TODO: Add support for alternative image load mechanism e.g using virtio/elf + * loader etc. + ******************************************************************************/ +void bl1_load_bl2(void) +{ + image_desc_t *image_desc; + image_info_t *image_info; + entry_point_info_t *ep_info; + meminfo_t *bl1_tzram_layout; + meminfo_t *bl2_tzram_layout; + int err; + + /* Get the image descriptor */ + image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); + assert(image_desc); + + /* Get the image info */ + image_info = &image_desc->image_info; + + /* Get the entry point info */ + ep_info = &image_desc->ep_info; + + /* Find out how much free trusted ram remains after BL1 load */ + bl1_tzram_layout = bl1_plat_sec_mem_layout(); + + INFO("BL1: Loading BL2\n"); + +#if LOAD_IMAGE_V2 + err = load_auth_image(BL2_IMAGE_ID, image_info); +#else + /* Load the BL2 image */ + err = load_auth_image(bl1_tzram_layout, + BL2_IMAGE_ID, + image_info->image_base, + image_info, + ep_info); + +#endif /* LOAD_IMAGE_V2 */ + + if (err) { + ERROR("Failed to load BL2 firmware.\n"); + plat_error_handler(err); + } + + /* + * Create a new layout of memory for BL2 as seen by BL1 i.e. + * tell it the amount of total and free memory available. + * This layout is created at the first free address visible + * to BL2. BL2 will read the memory layout before using its + * memory for other purposes. + */ +#if LOAD_IMAGE_V2 + bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->total_base; +#else + bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base; +#endif /* LOAD_IMAGE_V2 */ + + bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout); + + ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout; + NOTICE("BL1: Booting BL2\n"); + VERBOSE("BL1: BL2 memory layout address = %p\n", + (void *) bl2_tzram_layout); +} + +/******************************************************************************* + * Function called just before handing over to the next BL to inform the user + * about the boot progress. In debug mode, also print details about the BL + * image's execution context. + ******************************************************************************/ +void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info) +{ +#ifdef AARCH32 + NOTICE("BL1: Booting BL32\n"); +#else + NOTICE("BL1: Booting BL31\n"); +#endif /* AARCH32 */ + print_entry_point_info(bl_ep_info); +} + +#if SPIN_ON_BL1_EXIT +void print_debug_loop_message(void) +{ + NOTICE("BL1: Debug loop, spinning forever\n"); + NOTICE("BL1: Please connect the debugger to continue\n"); +} +#endif + +/******************************************************************************* + * Top level handler for servicing BL1 SMCs. + ******************************************************************************/ +register_t bl1_smc_handler(unsigned int smc_fid, + register_t x1, + register_t x2, + register_t x3, + register_t x4, + void *cookie, + void *handle, + unsigned int flags) +{ + +#if TRUSTED_BOARD_BOOT + /* + * Dispatch FWU calls to FWU SMC handler and return its return + * value + */ + if (is_fwu_fid(smc_fid)) { + return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie, + handle, flags); + } +#endif + + switch (smc_fid) { + case BL1_SMC_CALL_COUNT: + SMC_RET1(handle, BL1_NUM_SMC_CALLS); + + case BL1_SMC_UID: + SMC_UUID_RET(handle, bl1_svc_uid); + + case BL1_SMC_VERSION: + SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER); + + default: + break; + } + + WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid); + SMC_RET1(handle, SMC_UNK); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1_private.h new file mode 100644 index 0000000..2ef8d0e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/bl1_private.h @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BL1_PRIVATE_H__ +#define __BL1_PRIVATE_H__ + +#include + +/******************************************************************************* + * Declarations of linker defined symbols which will tell us where BL1 lives + * in Trusted ROM and RAM + ******************************************************************************/ +extern uintptr_t __BL1_ROM_END__; +#define BL1_ROM_END (uintptr_t)(&__BL1_ROM_END__) + +extern uintptr_t __BL1_RAM_START__; +extern uintptr_t __BL1_RAM_END__; +#define BL1_RAM_BASE (uintptr_t)(&__BL1_RAM_START__) +#define BL1_RAM_LIMIT (uintptr_t)(&__BL1_RAM_END__) + +/****************************************** + * Function prototypes + *****************************************/ +void bl1_arch_setup(void); +void bl1_arch_next_el_setup(void); + +void bl1_prepare_next_image(unsigned int image_id); + +register_t bl1_fwu_smc_handler(unsigned int smc_fid, + register_t x1, + register_t x2, + register_t x3, + register_t x4, + void *cookie, + void *handle, + unsigned int flags); +#endif /* __BL1_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/tbbr/tbbr_img_desc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/tbbr/tbbr_img_desc.c new file mode 100644 index 0000000..7651f1c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl1/tbbr/tbbr_img_desc.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +image_desc_t bl1_tbbr_image_descs[] = { + { + .image_id = FWU_CERT_ID, + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_1, image_info_t, 0), + .image_info.image_base = BL2_BASE, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_1, entry_point_info_t, SECURE), + }, +#if NS_BL1U_BASE + { + .image_id = NS_BL1U_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_1, entry_point_info_t, NON_SECURE | EXECUTABLE), + .ep_info.pc = NS_BL1U_BASE, + }, +#endif +#if SCP_BL2U_BASE + { + .image_id = SCP_BL2U_IMAGE_ID, + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_1, image_info_t, 0), + .image_info.image_base = SCP_BL2U_BASE, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_1, entry_point_info_t, SECURE), + }, +#endif +#if BL2U_BASE + { + .image_id = BL2U_IMAGE_ID, + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_1, image_info_t, 0), + .image_info.image_base = BL2U_BASE, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_1, entry_point_info_t, SECURE | EXECUTABLE), + .ep_info.pc = BL2U_BASE, + }, +#endif +#if NS_BL2U_BASE + { + .image_id = NS_BL2U_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_1, entry_point_info_t, NON_SECURE), + }, +#endif + BL2_IMAGE_DESC, + + { + .image_id = INVALID_IMAGE_ID, + } +}; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/aarch32/bl2_arch_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/aarch32/bl2_arch_setup.c new file mode 100644 index 0000000..665c29c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/aarch32/bl2_arch_setup.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +/******************************************************************************* + * Place holder function to perform any Secure SVC specific architectural + * setup. At the moment there is nothing to do. + ******************************************************************************/ +void bl2_arch_setup(void) +{ + +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/aarch32/bl2_entrypoint.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/aarch32/bl2_entrypoint.S new file mode 100644 index 0000000..6c620e2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/aarch32/bl2_entrypoint.S @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + + .globl bl2_vector_table + .globl bl2_entrypoint + + +vector_base bl2_vector_table + b bl2_entrypoint + b report_exception /* Undef */ + b report_exception /* SVC call */ + b report_exception /* Prefetch abort */ + b report_exception /* Data abort */ + b report_exception /* Reserved */ + b report_exception /* IRQ */ + b report_exception /* FIQ */ + + +func bl2_entrypoint + /*--------------------------------------------- + * Save from r1 the extents of the trusted ram + * available to BL2 for future use. + * r0 is not currently used. + * --------------------------------------------- + */ + mov r11, r1 + + /* --------------------------------------------- + * Set the exception vector to something sane. + * --------------------------------------------- + */ + ldr r0, =bl2_vector_table + stcopr r0, VBAR + isb + + /* ----------------------------------------------------- + * Enable the instruction cache + * ----------------------------------------------------- + */ + ldcopr r0, SCTLR + orr r0, r0, #SCTLR_I_BIT + stcopr r0, SCTLR + isb + + /* --------------------------------------------- + * Since BL2 executes after BL1, it is assumed + * here that BL1 has already has done the + * necessary register initializations. + * --------------------------------------------- + */ + + /* --------------------------------------------- + * Invalidate the RW memory used by the BL2 + * image. This includes the data and NOBITS + * sections. This is done to safeguard against + * possible corruption of this memory by dirty + * cache lines in a system cache as a result of + * use by an earlier boot loader stage. + * --------------------------------------------- + */ + ldr r0, =__RW_START__ + ldr r1, =__RW_END__ + sub r1, r1, r0 + bl inv_dcache_range + + /* --------------------------------------------- + * Zero out NOBITS sections. There are 2 of them: + * - the .bss section; + * - the coherent memory section. + * --------------------------------------------- + */ + ldr r0, =__BSS_START__ + ldr r1, =__BSS_SIZE__ + bl zeromem + +#if USE_COHERENT_MEM + ldr r0, =__COHERENT_RAM_START__ + ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ + bl zeromem +#endif + + /* -------------------------------------------- + * Allocate a stack whose memory will be marked + * as Normal-IS-WBWA when the MMU is enabled. + * There is no risk of reading stale stack + * memory after enabling the MMU as only the + * primary cpu is running at the moment. + * -------------------------------------------- + */ + bl plat_set_my_stack + + /* --------------------------------------------- + * Perform early platform setup & platform + * specific early arch. setup e.g. mmu setup + * --------------------------------------------- + */ + mov r0, r11 + bl bl2_early_platform_setup + bl bl2_plat_arch_setup + + /* --------------------------------------------- + * Jump to main function. + * --------------------------------------------- + */ + bl bl2_main + + /* --------------------------------------------- + * Should never reach this point. + * --------------------------------------------- + */ + bl plat_panic_handler + +endfunc bl2_entrypoint diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/aarch64/bl2_arch_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/aarch64/bl2_arch_setup.c new file mode 100644 index 0000000..0eafd15 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/aarch64/bl2_arch_setup.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/******************************************************************************* + * Place holder function to perform any S-EL1 specific architectural setup. At + * the moment there is nothing to do. + ******************************************************************************/ +void bl2_arch_setup(void) +{ + /* Give access to FP/SIMD registers */ + write_cpacr(CPACR_EL1_FPEN(CPACR_EL1_FP_TRAP_NONE)); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/aarch64/bl2_entrypoint.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/aarch64/bl2_entrypoint.S new file mode 100644 index 0000000..476efe8 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/aarch64/bl2_entrypoint.S @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + + .globl bl2_entrypoint + + + +func bl2_entrypoint + /*--------------------------------------------- + * Save from x1 the extents of the tzram + * available to BL2 for future use. + * x0 is not currently used. + * --------------------------------------------- + */ + mov x20, x1 + + /* --------------------------------------------- + * Set the exception vector to something sane. + * --------------------------------------------- + */ + adr x0, early_exceptions + msr vbar_el1, x0 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT + + /* --------------------------------------------- + * Enable the instruction cache, stack pointer + * and data access alignment checks + * --------------------------------------------- + */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el1 + orr x0, x0, x1 + msr sctlr_el1, x0 + isb + + /* --------------------------------------------- + * Invalidate the RW memory used by the BL2 + * image. This includes the data and NOBITS + * sections. This is done to safeguard against + * possible corruption of this memory by dirty + * cache lines in a system cache as a result of + * use by an earlier boot loader stage. + * --------------------------------------------- + */ + adr x0, __RW_START__ + adr x1, __RW_END__ + sub x1, x1, x0 + bl inv_dcache_range + + /* --------------------------------------------- + * Zero out NOBITS sections. There are 2 of them: + * - the .bss section; + * - the coherent memory section. + * --------------------------------------------- + */ + ldr x0, =__BSS_START__ + ldr x1, =__BSS_SIZE__ + bl zeromem16 + +#if USE_COHERENT_MEM + ldr x0, =__COHERENT_RAM_START__ + ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ + bl zeromem16 +#endif + + /* -------------------------------------------- + * Allocate a stack whose memory will be marked + * as Normal-IS-WBWA when the MMU is enabled. + * There is no risk of reading stale stack + * memory after enabling the MMU as only the + * primary cpu is running at the moment. + * -------------------------------------------- + */ + bl plat_set_my_stack + + /* --------------------------------------------- + * Perform early platform setup & platform + * specific early arch. setup e.g. mmu setup + * --------------------------------------------- + */ + mov x0, x20 + bl bl2_early_platform_setup + bl bl2_plat_arch_setup + + /* --------------------------------------------- + * Jump to main function. + * --------------------------------------------- + */ + bl bl2_main + + /* --------------------------------------------- + * Should never reach this point. + * --------------------------------------------- + */ + bl plat_panic_handler + +endfunc bl2_entrypoint diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2.ld.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2.ld.S new file mode 100644 index 0000000..9b1e531 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2.ld.S @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) +OUTPUT_ARCH(PLATFORM_LINKER_ARCH) +#if PLAT_rcar +ENTRY(bl2_reset) +#else +ENTRY(bl2_entrypoint) +#endif + +MEMORY { + RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE +} + + +SECTIONS +{ + . = BL2_BASE; + ASSERT(. == ALIGN(4096), + "BL2_BASE address is not aligned on a page boundary.") + +#if SEPARATE_CODE_AND_RODATA + .text . : { + __TEXT_START__ = .; + *bl2_entrypoint.o(.text*) + *(.text*) + *(.vectors) + . = NEXT(4096); + __TEXT_END__ = .; + } >RAM + + .rodata . : { + __RODATA_START__ = .; + *(.rodata*) + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __PARSER_LIB_DESCS_START__ = .; + KEEP(*(.img_parser_lib_descs)) + __PARSER_LIB_DESCS_END__ = .; + + . = NEXT(4096); + __RODATA_END__ = .; + } >RAM +#else + ro . : { + __RO_START__ = .; +#if PLAT_rcar + *bl2_reset.o(.text*) +#endif + *bl2_entrypoint.o(.text*) +#if PLAT_rcar + . = NEXT(ALIGN_VERSION); + *rcar_common.o(.version*) +#endif + *(.text*) + *(.rodata*) + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __PARSER_LIB_DESCS_START__ = .; + KEEP(*(.img_parser_lib_descs)) + __PARSER_LIB_DESCS_END__ = .; + + *(.vectors) + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as + * read-only, executable. No RW data from the next section must + * creep in. Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __RO_END__ = .; + } >RAM +#endif + + /* + * Define a linker symbol to mark start of the RW memory area for this + * image. + */ + __RW_START__ = . ; + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + + stacks (NOLOAD) : { + __STACKS_START__ = .; + *(tzfw_normal_stacks) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } >RAM + + /* + * The xlat_table section is for full, aligned page tables (4K). + * Removing them from .bss avoids forcing 4K alignment on + * the .bss section and eliminates the unecessary zero init + */ + xlat_table (NOLOAD) : { + *(xlat_table) + } >RAM + +#if USE_COHERENT_MEM + /* + * The base address of the coherent memory section must be page-aligned (4K) + * to guarantee that the coherent data are stored on their own pages and + * are not mixed with normal data. This is required to set up the correct + * memory attributes for the coherent data page tables. + */ + coherent_ram (NOLOAD) : ALIGN(4096) { + __COHERENT_RAM_START__ = .; + *(tzfw_coherent_mem) + __COHERENT_RAM_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked + * as device memory. No other unexpected data must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __COHERENT_RAM_END__ = .; + } >RAM +#endif + + /* + * Define a linker symbol to mark end of the RW memory area for this + * image. + */ + __RW_END__ = .; + __BL2_END__ = .; + + __BSS_SIZE__ = SIZEOF(.bss); + +#if USE_COHERENT_MEM + __COHERENT_RAM_UNALIGNED_SIZE__ = + __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; +#endif + + ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.") +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2.mk new file mode 100644 index 0000000..f823ef4 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2.mk @@ -0,0 +1,46 @@ +# +# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +BL2_SOURCES += bl2/bl2_main.c \ + bl2/${ARCH}/bl2_entrypoint.S \ + bl2/${ARCH}/bl2_arch_setup.c \ + lib/locks/exclusive/${ARCH}/spinlock.S + +ifeq (${ARCH},aarch64) +BL2_SOURCES += common/aarch64/early_exceptions.S +endif + +ifeq (${LOAD_IMAGE_V2},1) +BL2_SOURCES += bl2/bl2_image_load_v2.c +else +BL2_SOURCES += bl2/bl2_image_load.c +endif + +BL2_LINKERFILE := bl2/bl2.ld.S diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2_image_load.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2_image_load.c new file mode 100644 index 0000000..63bbc2f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2_image_load.c @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Check for platforms that use obsolete image terminology + */ +#ifdef BL30_BASE +# error "BL30_BASE platform define no longer used - please use SCP_BL2_BASE" +#endif + +/******************************************************************************* + * Load the SCP_BL2 image if there's one. + * If a platform does not want to attempt to load SCP_BL2 image it must leave + * SCP_BL2_BASE undefined. + * Return 0 on success or if there's no SCP_BL2 image to load, a negative error + * code otherwise. + ******************************************************************************/ +static int load_scp_bl2(void) +{ + int e = 0; +#ifdef SCP_BL2_BASE + meminfo_t scp_bl2_mem_info; + image_info_t scp_bl2_image_info; + + /* + * It is up to the platform to specify where SCP_BL2 should be loaded if + * it exists. It could create space in the secure sram or point to a + * completely different memory. + * + * The entry point information is not relevant in this case as the AP + * won't execute the SCP_BL2 image. + */ + INFO("BL2: Loading SCP_BL2\n"); + bl2_plat_get_scp_bl2_meminfo(&scp_bl2_mem_info); + scp_bl2_image_info.h.version = VERSION_1; + e = load_auth_image(&scp_bl2_mem_info, + SCP_BL2_IMAGE_ID, + SCP_BL2_BASE, + &scp_bl2_image_info, + NULL); + + if (e == 0) { + /* The subsequent handling of SCP_BL2 is platform specific */ + e = bl2_plat_handle_scp_bl2(&scp_bl2_image_info); + if (e) { + ERROR("Failure in platform-specific handling of SCP_BL2 image.\n"); + } + } +#endif /* SCP_BL2_BASE */ + + return e; +} + +#ifndef EL3_PAYLOAD_BASE +/******************************************************************************* + * Load the BL31 image. + * The bl2_to_bl31_params and bl31_ep_info params will be updated with the + * relevant BL31 information. + * Return 0 on success, a negative error code otherwise. + ******************************************************************************/ +static int load_bl31(bl31_params_t *bl2_to_bl31_params, + entry_point_info_t *bl31_ep_info) +{ + meminfo_t *bl2_tzram_layout; + int e; + + INFO("BL2: Loading BL31\n"); + assert(bl2_to_bl31_params != NULL); + assert(bl31_ep_info != NULL); + + /* Find out how much free trusted ram remains after BL2 load */ + bl2_tzram_layout = bl2_plat_sec_mem_layout(); + + /* Set the X0 parameter to BL31 */ + bl31_ep_info->args.arg0 = (unsigned long)bl2_to_bl31_params; + + /* Load the BL31 image */ + e = load_auth_image(bl2_tzram_layout, + BL31_IMAGE_ID, +#if PLAT_rcar + /* load destination address from header */ + plat_get_bl31_bl32_image_entrypoint(SOC_FW_CONTENT_CERT_ID), +#else + BL31_BASE, +#endif /* PLAT_rcar */ + bl2_to_bl31_params->bl31_image_info, + bl31_ep_info); + + if (e == 0) { + bl2_plat_set_bl31_ep_info(bl2_to_bl31_params->bl31_image_info, + bl31_ep_info); + } + + return e; +} + +/******************************************************************************* + * Load the BL32 image if there's one. + * The bl2_to_bl31_params param will be updated with the relevant BL32 + * information. + * If a platform does not want to attempt to load BL32 image it must leave + * BL32_BASE undefined. + * Return 0 on success or if there's no BL32 image to load, a negative error + * code otherwise. + ******************************************************************************/ +static int load_bl32(bl31_params_t *bl2_to_bl31_params) +{ + int e = 0; +#ifdef BL32_BASE + meminfo_t bl32_mem_info; + + INFO("BL2: Loading BL32\n"); + assert(bl2_to_bl31_params != NULL); + + /* + * It is up to the platform to specify where BL32 should be loaded if + * it exists. It could create space in the secure sram or point to a + * completely different memory. + */ + bl2_plat_get_bl32_meminfo(&bl32_mem_info); + e = load_auth_image(&bl32_mem_info, + BL32_IMAGE_ID, +#if PLAT_rcar + /* load destination address from header */ + plat_get_bl31_bl32_image_entrypoint(TRUSTED_OS_FW_CONTENT_CERT_ID), +#else + BL32_BASE, +#endif /* PLAT_rcar */ + bl2_to_bl31_params->bl32_image_info, + bl2_to_bl31_params->bl32_ep_info); + + if (e == 0) { + bl2_plat_set_bl32_ep_info( + bl2_to_bl31_params->bl32_image_info, + bl2_to_bl31_params->bl32_ep_info); + } +#endif /* BL32_BASE */ + + return e; +} + +#ifndef PRELOADED_BL33_BASE +/******************************************************************************* + * Load the BL33 image. + * The bl2_to_bl31_params param will be updated with the relevant BL33 + * information. + * Return 0 on success, a negative error code otherwise. + ******************************************************************************/ +static int load_bl33(bl31_params_t *bl2_to_bl31_params) +{ + meminfo_t bl33_mem_info; + int e; + + INFO("BL2: Loading BL33\n"); + assert(bl2_to_bl31_params != NULL); + + bl2_plat_get_bl33_meminfo(&bl33_mem_info); + + /* Load the BL33 image in non-secure memory provided by the platform */ + e = load_auth_image(&bl33_mem_info, + BL33_IMAGE_ID, + plat_get_ns_image_entrypoint(), + bl2_to_bl31_params->bl33_image_info, + bl2_to_bl31_params->bl33_ep_info); + + if (e == 0) { + bl2_plat_set_bl33_ep_info(bl2_to_bl31_params->bl33_image_info, + bl2_to_bl31_params->bl33_ep_info); + } + + return e; +} +#endif /* PRELOADED_BL33_BASE */ + +#endif /* EL3_PAYLOAD_BASE */ + +/******************************************************************************* + * This function loads SCP_BL2/BL3x images and returns the ep_info for + * the next executable image. + ******************************************************************************/ +entry_point_info_t *bl2_load_images(void) +{ + bl31_params_t *bl2_to_bl31_params; + entry_point_info_t *bl31_ep_info; + int e; + + e = load_scp_bl2(); + if (e) { + ERROR("Failed to load SCP_BL2 (%i)\n", e); + plat_error_handler(e); + } + + /* Perform platform setup in BL2 after loading SCP_BL2 */ + bl2_platform_setup(); + + /* + * Get a pointer to the memory the platform has set aside to pass + * information to BL31. + */ + bl2_to_bl31_params = bl2_plat_get_bl31_params(); + bl31_ep_info = bl2_plat_get_bl31_ep_info(); + +#ifdef EL3_PAYLOAD_BASE + /* + * In the case of an EL3 payload, we don't need to load any further + * images. Just update the BL31 entrypoint info structure to make BL1 + * jump to the EL3 payload. + * The pointer to the memory the platform has set aside to pass + * information to BL31 in the normal boot flow is reused here, even + * though only a fraction of the information contained in the + * bl31_params_t structure makes sense in the context of EL3 payloads. + * This will be refined in the future. + */ + INFO("BL2: Populating the entrypoint info for the EL3 payload\n"); + bl31_ep_info->pc = EL3_PAYLOAD_BASE; + bl31_ep_info->args.arg0 = (unsigned long) bl2_to_bl31_params; + bl2_plat_set_bl31_ep_info(NULL, bl31_ep_info); +#else + e = load_bl31(bl2_to_bl31_params, bl31_ep_info); + if (e) { + ERROR("Failed to load BL31 (%i)\n", e); + plat_error_handler(e); + } + + e = load_bl32(bl2_to_bl31_params); + if (e) { +#if PLAT_rcar + if (e) { + ERROR("Failed to load BL32 (%i)\n", e); + plat_error_handler(e); + } +#else + if (e == -EAUTH) { + ERROR("Failed to authenticate BL32\n"); + plat_error_handler(e); + } else { + WARN("Failed to load BL32 (%i)\n", e); + } +#endif /* PLAT_rcar */ + } + +#ifdef PRELOADED_BL33_BASE + /* + * In this case, don't load the BL33 image as it's already loaded in + * memory. Update BL33 entrypoint information. + */ + INFO("BL2: Populating the entrypoint info for the preloaded BL33\n"); + bl2_to_bl31_params->bl33_ep_info->pc = PRELOADED_BL33_BASE; + bl2_plat_set_bl33_ep_info(NULL, bl2_to_bl31_params->bl33_ep_info); +#else + e = load_bl33(bl2_to_bl31_params); + if (e) { + ERROR("Failed to load BL33 (%i)\n", e); + plat_error_handler(e); + } +#endif /* PRELOADED_BL33_BASE */ + +#endif /* EL3_PAYLOAD_BASE */ + + /* Flush the params to be passed to memory */ + bl2_plat_flush_bl31_params(); + + return bl31_ep_info; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2_image_load_v2.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2_image_load_v2.c new file mode 100644 index 0000000..4fab655 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2_image_load_v2.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/******************************************************************************* + * This function loads SCP_BL2/BL3x images and returns the ep_info for + * the next executable image. + ******************************************************************************/ +entry_point_info_t *bl2_load_images(void) +{ + bl_params_t *bl2_to_next_bl_params; + bl_load_info_t *bl2_load_info; + const bl_load_info_node_t *bl2_node_info; + int plat_setup_done = 0; + int err; + + /* + * Get information about the images to load. + */ + bl2_load_info = plat_get_bl_image_load_info(); + assert(bl2_load_info); + assert(bl2_load_info->head); + assert(bl2_load_info->h.type == PARAM_BL_LOAD_INFO); + assert(bl2_load_info->h.version >= VERSION_2); + bl2_node_info = bl2_load_info->head; + + while (bl2_node_info) { + /* + * Perform platform setup before loading the image, + * if indicated in the image attributes AND if NOT + * already done before. + */ + if (bl2_node_info->image_info->h.attr & IMAGE_ATTRIB_PLAT_SETUP) { + if (plat_setup_done) { + WARN("BL2: Platform setup already done!!\n"); + } else { + INFO("BL2: Doing platform setup\n"); + bl2_platform_setup(); + plat_setup_done = 1; + } + } + + if (!(bl2_node_info->image_info->h.attr & IMAGE_ATTRIB_SKIP_LOADING)) { + INFO("BL2: Loading image id %d\n", bl2_node_info->image_id); + err = load_auth_image(bl2_node_info->image_id, + bl2_node_info->image_info); + if (err) { + ERROR("BL2: Failed to load image (%i)\n", err); + plat_error_handler(err); + } + } else { + INFO("BL2: Skip loading image id %d\n", bl2_node_info->image_id); + } + + /* Allow platform to handle image information. */ + err = bl2_plat_handle_post_image_load(bl2_node_info->image_id); + if (err) { + ERROR("BL2: Failure in post image load handling (%i)\n", err); + plat_error_handler(err); + } + + /* Go to next image */ + bl2_node_info = bl2_node_info->next_load_info; + } + + /* + * Get information to pass to the next image. + */ + bl2_to_next_bl_params = plat_get_next_bl_params(); + assert(bl2_to_next_bl_params); + assert(bl2_to_next_bl_params->head); + assert(bl2_to_next_bl_params->h.type == PARAM_BL_PARAMS); + assert(bl2_to_next_bl_params->h.version >= VERSION_2); + + /* Flush the parameters to be passed to next image */ + plat_flush_next_bl_params(); + + return bl2_to_next_bl_params->head->ep_info; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2_main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2_main.c new file mode 100644 index 0000000..514c005 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2_main.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "bl2_private.h" + + +/******************************************************************************* + * The only thing to do in BL2 is to load further images and pass control to + * next BL. The memory occupied by BL2 will be reclaimed by BL3x stages. BL2 + * runs entirely in S-EL1. + ******************************************************************************/ +void bl2_main(void) +{ + entry_point_info_t *next_bl_ep_info; + + NOTICE("BL2: %s\n", version_string); + NOTICE("BL2: %s\n", build_message); + + /* Perform remaining generic architectural setup in S-EL1 */ + bl2_arch_setup(); + +#if TRUSTED_BOARD_BOOT + /* Initialize authentication module */ + auth_mod_init(); +#endif /* TRUSTED_BOARD_BOOT */ + + /* Load the subsequent bootloader images. */ + next_bl_ep_info = bl2_load_images(); + +#ifdef AARCH32 + /* + * For AArch32 state BL1 and BL2 share the MMU setup. + * Given that BL2 does not map BL1 regions, MMU needs + * to be disabled in order to go back to BL1. + */ + disable_mmu_icache_secure(); +#endif /* AARCH32 */ + + /* + * Run next BL image via an SMC to BL1. Information on how to pass + * control to the BL32 (if present) and BL33 software images will + * be passed to next BL image as an argument. + */ + smc(BL1_SMC_RUN_IMAGE, (unsigned long)next_bl_ep_info, 0, 0, 0, 0, 0, 0); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2_private.h new file mode 100644 index 0000000..b339777 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2/bl2_private.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BL2_PRIVATE_H__ +#define __BL2_PRIVATE_H__ + +/****************************************** + * Forward declarations + *****************************************/ +struct entry_point_info; + +/****************************************** + * Function prototypes + *****************************************/ +void bl2_arch_setup(void); +struct entry_point_info *bl2_load_images(void); + +#endif /* __BL2_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl2u/aarch64/bl2u_entrypoint.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2u/aarch64/bl2u_entrypoint.S new file mode 100644 index 0000000..ef3db92 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2u/aarch64/bl2u_entrypoint.S @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + + .globl bl2u_entrypoint + + +func bl2u_entrypoint + /*--------------------------------------------- + * Store the extents of the tzram available to + * BL2U and other platform specific information + * for future use. x0 is currently not used. + * --------------------------------------------- + */ + mov x20, x1 + mov x21, x2 + + /* --------------------------------------------- + * Set the exception vector to something sane. + * --------------------------------------------- + */ + adr x0, early_exceptions + msr vbar_el1, x0 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT + + /* --------------------------------------------- + * Enable the instruction cache, stack pointer + * and data access alignment checks + * --------------------------------------------- + */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el1 + orr x0, x0, x1 + msr sctlr_el1, x0 + isb + + /* --------------------------------------------- + * Invalidate the RW memory used by the BL2U + * image. This includes the data and NOBITS + * sections. This is done to safeguard against + * possible corruption of this memory by dirty + * cache lines in a system cache as a result of + * use by an earlier boot loader stage. + * --------------------------------------------- + */ + adr x0, __RW_START__ + adr x1, __RW_END__ + sub x1, x1, x0 + bl inv_dcache_range + + /* --------------------------------------------- + * Zero out NOBITS sections. There are 2 of them: + * - the .bss section; + * - the coherent memory section. + * --------------------------------------------- + */ + ldr x0, =__BSS_START__ + ldr x1, =__BSS_SIZE__ + bl zeromem16 + + /* -------------------------------------------- + * Allocate a stack whose memory will be marked + * as Normal-IS-WBWA when the MMU is enabled. + * There is no risk of reading stale stack + * memory after enabling the MMU as only the + * primary cpu is running at the moment. + * -------------------------------------------- + */ + bl plat_set_my_stack + + /* --------------------------------------------- + * Perform early platform setup & platform + * specific early arch. setup e.g. mmu setup + * --------------------------------------------- + */ + mov x0, x20 + mov x1, x21 + bl bl2u_early_platform_setup + bl bl2u_plat_arch_setup + + /* --------------------------------------------- + * Jump to bl2u_main function. + * --------------------------------------------- + */ + bl bl2u_main + + /* --------------------------------------------- + * Should never reach this point. + * --------------------------------------------- + */ + bl plat_panic_handler + +endfunc bl2u_entrypoint diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl2u/bl2u.ld.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2u/bl2u.ld.S new file mode 100644 index 0000000..d72589f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2u/bl2u.ld.S @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) +OUTPUT_ARCH(PLATFORM_LINKER_ARCH) +ENTRY(bl2u_entrypoint) + +MEMORY { + RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE +} + + +SECTIONS +{ + . = BL2U_BASE; + ASSERT(. == ALIGN(4096), + "BL2U_BASE address is not aligned on a page boundary.") + +#if SEPARATE_CODE_AND_RODATA + .text . : { + __TEXT_START__ = .; + *bl2u_entrypoint.o(.text*) + *(.text*) + *(.vectors) + . = NEXT(4096); + __TEXT_END__ = .; + } >RAM + + .rodata . : { + __RODATA_START__ = .; + *(.rodata*) + . = NEXT(4096); + __RODATA_END__ = .; + } >RAM +#else + ro . : { + __RO_START__ = .; + *bl2u_entrypoint.o(.text*) + *(.text*) + *(.rodata*) + + *(.vectors) + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as + * read-only, executable. No RW data from the next section must + * creep in. Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __RO_END__ = .; + } >RAM +#endif + + /* + * Define a linker symbol to mark start of the RW memory area for this + * image. + */ + __RW_START__ = . ; + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + + stacks (NOLOAD) : { + __STACKS_START__ = .; + *(tzfw_normal_stacks) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } >RAM + + /* + * The xlat_table section is for full, aligned page tables (4K). + * Removing them from .bss avoids forcing 4K alignment on + * the .bss section and eliminates the unecessary zero init + */ + xlat_table (NOLOAD) : { + *(xlat_table) + } >RAM + +#if USE_COHERENT_MEM + /* + * The base address of the coherent memory section must be page-aligned (4K) + * to guarantee that the coherent data are stored on their own pages and + * are not mixed with normal data. This is required to set up the correct + * memory attributes for the coherent data page tables. + */ + coherent_ram (NOLOAD) : ALIGN(4096) { + __COHERENT_RAM_START__ = .; + *(tzfw_coherent_mem) + __COHERENT_RAM_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked + * as device memory. No other unexpected data must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __COHERENT_RAM_END__ = .; + } >RAM +#endif + + /* + * Define a linker symbol to mark end of the RW memory area for this + * image. + */ + __RW_END__ = .; + __BL2U_END__ = .; + + __BSS_SIZE__ = SIZEOF(.bss); + + ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.") +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl2u/bl2u.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2u/bl2u.mk new file mode 100644 index 0000000..aa9de54 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2u/bl2u.mk @@ -0,0 +1,35 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +BL2U_SOURCES += bl2u/bl2u_main.c \ + bl2u/aarch64/bl2u_entrypoint.S \ + common/aarch64/early_exceptions.S + +BL2U_LINKERFILE := bl2u/bl2u.ld.S diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl2u/bl2u_main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2u/bl2u_main.c new file mode 100644 index 0000000..515ddfb --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl2u/bl2u_main.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * This function is responsible to: + * Load SCP_BL2U if platform has defined SCP_BL2U_BASE + * Perform platform setup. + * Go back to EL3. + ******************************************************************************/ +void bl2u_main(void) +{ + NOTICE("BL2U: %s\n", version_string); + NOTICE("BL2U: %s\n", build_message); + +#if SCP_BL2U_BASE + int rc; + /* Load the subsequent bootloader images */ + rc = bl2u_plat_handle_scp_bl2u(); + if (rc) { + ERROR("Failed to load SCP_BL2U (%i)\n", rc); + panic(); + } +#endif + + /* Perform platform setup in BL2U after loading SCP_BL2U */ + bl2u_platform_setup(); + + /* + * Indicate that BL2U is done and resume back to + * normal world via an SMC to BL1. + * x1 could be passed to Normal world, + * so DO NOT pass any secret information. + */ + smc(FWU_SMC_SEC_IMAGE_DONE, 0, 0, 0, 0, 0, 0, 0); + wfi(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/aarch64/bl31_entrypoint.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/aarch64/bl31_entrypoint.S new file mode 100644 index 0000000..34199a0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/aarch64/bl31_entrypoint.S @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + .globl bl31_entrypoint + .globl bl31_warm_entrypoint + + /* ----------------------------------------------------- + * bl31_entrypoint() is the cold boot entrypoint, + * executed only by the primary cpu. + * ----------------------------------------------------- + */ + +func bl31_entrypoint +#if !RESET_TO_BL31 + /* --------------------------------------------------------------- + * Preceding bootloader has populated x0 with a pointer to a + * 'bl31_params' structure & x1 with a pointer to platform + * specific structure + * --------------------------------------------------------------- + */ + mov x20, x0 + mov x21, x1 + + /* --------------------------------------------------------------------- + * For !RESET_TO_BL31 systems, only the primary CPU ever reaches + * bl31_entrypoint() during the cold boot flow, so the cold/warm boot + * and primary/secondary CPU logic should not be executed in this case. + * + * Also, assume that the previous bootloader has already set up the CPU + * endianness and has initialised the memory. + * --------------------------------------------------------------------- + */ +#if PLAT_rcar + el3_entrypoint_common \ + _set_endian=0 \ + _warm_boot_mailbox=1 \ + _secondary_cold_boot=1 \ + _init_memory=1 \ + _init_c_runtime=1 \ + _exception_vectors=runtime_exceptions +#else + el3_entrypoint_common \ + _set_endian=0 \ + _warm_boot_mailbox=0 \ + _secondary_cold_boot=0 \ + _init_memory=0 \ + _init_c_runtime=1 \ + _exception_vectors=runtime_exceptions +#endif + + /* --------------------------------------------------------------------- + * Relay the previous bootloader's arguments to the platform layer + * --------------------------------------------------------------------- + */ + mov x0, x20 + mov x1, x21 +#else + /* --------------------------------------------------------------------- + * For RESET_TO_BL31 systems which have a programmable reset address, + * bl31_entrypoint() is executed only on the cold boot path so we can + * skip the warm boot mailbox mechanism. + * --------------------------------------------------------------------- + */ + el3_entrypoint_common \ + _set_endian=1 \ + _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ + _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ + _init_memory=1 \ + _init_c_runtime=1 \ + _exception_vectors=runtime_exceptions + + /* --------------------------------------------------------------------- + * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so + * there's no argument to relay from a previous bootloader. Zero the + * arguments passed to the platform layer to reflect that. + * --------------------------------------------------------------------- + */ + mov x0, 0 + mov x1, 0 +#endif /* RESET_TO_BL31 */ + + /* --------------------------------------------- + * Perform platform specific early arch. setup + * --------------------------------------------- + */ + bl bl31_early_platform_setup + bl bl31_plat_arch_setup + + /* --------------------------------------------- + * Jump to main function. + * --------------------------------------------- + */ + bl bl31_main + + /* ------------------------------------------------------------- + * Clean the .data & .bss sections to main memory. This ensures + * that any global data which was initialised by the primary CPU + * is visible to secondary CPUs before they enable their data + * caches and participate in coherency. + * ------------------------------------------------------------- + */ + adr x0, __DATA_START__ + adr x1, __DATA_END__ + sub x1, x1, x0 + bl clean_dcache_range + + adr x0, __BSS_START__ + adr x1, __BSS_END__ + sub x1, x1, x0 + bl clean_dcache_range + + b el3_exit +endfunc bl31_entrypoint + + /* -------------------------------------------------------------------- + * This CPU has been physically powered up. It is either resuming from + * suspend or has simply been turned on. In both cases, call the BL31 + * warmboot entrypoint + * -------------------------------------------------------------------- + */ +func bl31_warm_entrypoint + /* + * On the warm boot path, most of the EL3 initialisations performed by + * 'el3_entrypoint_common' must be skipped: + * + * - Only when the platform bypasses the BL1/BL31 entrypoint by + * programming the reset address do we need to set the CPU endianness. + * In other cases, we assume this has been taken care by the + * entrypoint code. + * + * - No need to determine the type of boot, we know it is a warm boot. + * + * - Do not try to distinguish between primary and secondary CPUs, this + * notion only exists for a cold boot. + * + * - No need to initialise the memory or the C runtime environment, + * it has been done once and for all on the cold boot path. + */ + el3_entrypoint_common \ + _set_endian=PROGRAMMABLE_RESET_ADDRESS \ + _warm_boot_mailbox=0 \ + _secondary_cold_boot=0 \ + _init_memory=0 \ + _init_c_runtime=0 \ + _exception_vectors=runtime_exceptions + + /* -------------------------------------------- + * Enable the MMU with the DCache disabled. It + * is safe to use stacks allocated in normal + * memory as a result. All memory accesses are + * marked nGnRnE when the MMU is disabled. So + * all the stack writes will make it to memory. + * All memory accesses are marked Non-cacheable + * when the MMU is enabled but D$ is disabled. + * So used stack memory is guaranteed to be + * visible immediately after the MMU is enabled + * Enabling the DCache at the same time as the + * MMU can lead to speculatively fetched and + * possibly stale stack memory being read from + * other caches. This can lead to coherency + * issues. + * -------------------------------------------- + */ + mov x0, #DISABLE_DCACHE + bl bl31_plat_enable_mmu + + bl psci_warmboot_entrypoint + + b el3_exit +endfunc bl31_warm_entrypoint diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/aarch64/crash_reporting.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/aarch64/crash_reporting.S new file mode 100644 index 0000000..7f5a86b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/aarch64/crash_reporting.S @@ -0,0 +1,366 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include + + .globl report_unhandled_exception + .globl report_unhandled_interrupt + .globl el3_panic + +#if CRASH_REPORTING +#define REG_SIZE 0x8 + + /* ------------------------------------------------------ + * The below section deals with dumping the system state + * when an unhandled exception is taken in EL3. + * The layout and the names of the registers which will + * be dumped during a unhandled exception is given below. + * ------------------------------------------------------ + */ +.section .rodata.crash_prints, "aS" +print_spacer: + .asciz " =\t\t0x" + +gp_regs: + .asciz "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\ + "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",\ + "x16", "x17", "x18", "x19", "x20", "x21", "x22",\ + "x23", "x24", "x25", "x26", "x27", "x28", "x29", "" +el3_sys_regs: + .asciz "scr_el3", "sctlr_el3", "cptr_el3", "tcr_el3",\ + "daif", "mair_el3", "spsr_el3", "elr_el3", "ttbr0_el3",\ + "esr_el3", "far_el3", "" + +non_el3_sys_regs: + .asciz "spsr_el1", "elr_el1", "spsr_abt", "spsr_und",\ + "spsr_irq", "spsr_fiq", "sctlr_el1", "actlr_el1", "cpacr_el1",\ + "csselr_el1", "sp_el1", "esr_el1", "ttbr0_el1", "ttbr1_el1",\ + "mair_el1", "amair_el1", "tcr_el1", "tpidr_el1", "tpidr_el0",\ + "tpidrro_el0", "dacr32_el2", "ifsr32_el2", "par_el1",\ + "mpidr_el1", "afsr0_el1", "afsr1_el1", "contextidr_el1",\ + "vbar_el1", "cntp_ctl_el0", "cntp_cval_el0", "cntv_ctl_el0",\ + "cntv_cval_el0", "cntkctl_el1", "fpexc32_el2", "sp_el0",\ + "isr_el1", "" + +panic_msg: + .asciz "PANIC in EL3 at x30 = 0x" +excpt_msg: + .asciz "Unhandled Exception in EL3.\nx30 =\t\t0x" +intr_excpt_msg: + .asciz "Unhandled Interrupt Exception in EL3.\nx30 =\t\t0x" + + /* + * Helper function to print newline to console. + */ +func print_newline + mov x0, '\n' + b plat_crash_console_putc +endfunc print_newline + + /* + * Helper function to print from crash buf. + * The print loop is controlled by the buf size and + * ascii reg name list which is passed in x6. The + * function returns the crash buf address in x0. + * Clobbers : x0 - x7, sp + */ +func size_controlled_print + /* Save the lr */ + mov sp, x30 + /* load the crash buf address */ + mrs x7, tpidr_el3 +test_size_list: + /* Calculate x5 always as it will be clobbered by asm_print_hex */ + mrs x5, tpidr_el3 + add x5, x5, #CPU_DATA_CRASH_BUF_SIZE + /* Test whether we have reached end of crash buf */ + cmp x7, x5 + b.eq exit_size_print + ldrb w4, [x6] + /* Test whether we are at end of list */ + cbz w4, exit_size_print + mov x4, x6 + /* asm_print_str updates x4 to point to next entry in list */ + bl asm_print_str + /* update x6 with the updated list pointer */ + mov x6, x4 + adr x4, print_spacer + bl asm_print_str + ldr x4, [x7], #REG_SIZE + bl asm_print_hex + bl print_newline + b test_size_list +exit_size_print: + mov x30, sp + ret +endfunc size_controlled_print + + /* + * Helper function to store x8 - x15 registers to + * the crash buf. The system registers values are + * copied to x8 to x15 by the caller which are then + * copied to the crash buf by this function. + * x0 points to the crash buf. It then calls + * size_controlled_print to print to console. + * Clobbers : x0 - x7, sp + */ +func str_in_crash_buf_print + /* restore the crash buf address in x0 */ + mrs x0, tpidr_el3 + stp x8, x9, [x0] + stp x10, x11, [x0, #REG_SIZE * 2] + stp x12, x13, [x0, #REG_SIZE * 4] + stp x14, x15, [x0, #REG_SIZE * 6] + b size_controlled_print +endfunc str_in_crash_buf_print + + /* ------------------------------------------------------ + * This macro calculates the offset to crash buf from + * cpu_data and stores it in tpidr_el3. It also saves x0 + * and x1 in the crash buf by using sp as a temporary + * register. + * ------------------------------------------------------ + */ + .macro prepare_crash_buf_save_x0_x1 + /* we can corrupt this reg to free up x0 */ + mov sp, x0 + /* tpidr_el3 contains the address to cpu_data structure */ + mrs x0, tpidr_el3 + /* Calculate the Crash buffer offset in cpu_data */ + add x0, x0, #CPU_DATA_CRASH_BUF_OFFSET + /* Store crash buffer address in tpidr_el3 */ + msr tpidr_el3, x0 + str x1, [x0, #REG_SIZE] + mov x1, sp + str x1, [x0] + .endm + + /* ----------------------------------------------------- + * This function allows to report a crash (if crash + * reporting is enabled) when an unhandled exception + * occurs. It prints the CPU state via the crash console + * making use of the crash buf. This function will + * not return. + * ----------------------------------------------------- + */ +func report_unhandled_exception + prepare_crash_buf_save_x0_x1 + adr x0, excpt_msg + mov sp, x0 + /* This call will not return */ + b do_crash_reporting +endfunc report_unhandled_exception + + + /* ----------------------------------------------------- + * This function allows to report a crash (if crash + * reporting is enabled) when an unhandled interrupt + * occurs. It prints the CPU state via the crash console + * making use of the crash buf. This function will + * not return. + * ----------------------------------------------------- + */ +func report_unhandled_interrupt + prepare_crash_buf_save_x0_x1 + adr x0, intr_excpt_msg + mov sp, x0 + /* This call will not return */ + b do_crash_reporting +endfunc report_unhandled_interrupt + + /* ----------------------------------------------------- + * This function allows to report a crash (if crash + * reporting is enabled) when panic() is invoked from + * C Runtime. It prints the CPU state via the crash + * console making use of the crash buf. This function + * will not return. + * ----------------------------------------------------- + */ +func el3_panic + msr spsel, #1 + prepare_crash_buf_save_x0_x1 + adr x0, panic_msg + mov sp, x0 + /* This call will not return */ + b do_crash_reporting +endfunc el3_panic + + /* ------------------------------------------------------------ + * The common crash reporting functionality. It requires x0 + * and x1 has already been stored in crash buf, sp points to + * crash message and tpidr_el3 contains the crash buf address. + * The function does the following: + * - Retrieve the crash buffer from tpidr_el3 + * - Store x2 to x6 in the crash buffer + * - Initialise the crash console. + * - Print the crash message by using the address in sp. + * - Print x30 value to the crash console. + * - Print x0 - x7 from the crash buf to the crash console. + * - Print x8 - x29 (in groups of 8 registers) using the + * crash buf to the crash console. + * - Print el3 sys regs (in groups of 8 registers) using the + * crash buf to the crash console. + * - Print non el3 sys regs (in groups of 8 registers) using + * the crash buf to the crash console. + * ------------------------------------------------------------ + */ +func do_crash_reporting + /* Retrieve the crash buf from tpidr_el3 */ + mrs x0, tpidr_el3 + /* Store x2 - x6, x30 in the crash buffer */ + stp x2, x3, [x0, #REG_SIZE * 2] + stp x4, x5, [x0, #REG_SIZE * 4] + stp x6, x30, [x0, #REG_SIZE * 6] + /* Initialize the crash console */ + bl plat_crash_console_init + /* Verify the console is initialized */ + cbz x0, crash_panic + /* Print the crash message. sp points to the crash message */ + mov x4, sp + bl asm_print_str + /* load the crash buf address */ + mrs x0, tpidr_el3 + /* report x30 first from the crash buf */ + ldr x4, [x0, #REG_SIZE * 7] + bl asm_print_hex + bl print_newline + /* Load the crash buf address */ + mrs x0, tpidr_el3 + /* Now mov x7 into crash buf */ + str x7, [x0, #REG_SIZE * 7] + + /* Report x0 - x29 values stored in crash buf*/ + /* Store the ascii list pointer in x6 */ + adr x6, gp_regs + /* Print x0 to x7 from the crash buf */ + bl size_controlled_print + /* Store x8 - x15 in crash buf and print */ + bl str_in_crash_buf_print + /* Load the crash buf address */ + mrs x0, tpidr_el3 + /* Store the rest of gp regs and print */ + stp x16, x17, [x0] + stp x18, x19, [x0, #REG_SIZE * 2] + stp x20, x21, [x0, #REG_SIZE * 4] + stp x22, x23, [x0, #REG_SIZE * 6] + bl size_controlled_print + /* Load the crash buf address */ + mrs x0, tpidr_el3 + stp x24, x25, [x0] + stp x26, x27, [x0, #REG_SIZE * 2] + stp x28, x29, [x0, #REG_SIZE * 4] + bl size_controlled_print + + /* Print the el3 sys registers */ + adr x6, el3_sys_regs + mrs x8, scr_el3 + mrs x9, sctlr_el3 + mrs x10, cptr_el3 + mrs x11, tcr_el3 + mrs x12, daif + mrs x13, mair_el3 + mrs x14, spsr_el3 + mrs x15, elr_el3 + bl str_in_crash_buf_print + mrs x8, ttbr0_el3 + mrs x9, esr_el3 + mrs x10, far_el3 + bl str_in_crash_buf_print + + /* Print the non el3 sys registers */ + adr x6, non_el3_sys_regs + mrs x8, spsr_el1 + mrs x9, elr_el1 + mrs x10, spsr_abt + mrs x11, spsr_und + mrs x12, spsr_irq + mrs x13, spsr_fiq + mrs x14, sctlr_el1 + mrs x15, actlr_el1 + bl str_in_crash_buf_print + mrs x8, cpacr_el1 + mrs x9, csselr_el1 + mrs x10, sp_el1 + mrs x11, esr_el1 + mrs x12, ttbr0_el1 + mrs x13, ttbr1_el1 + mrs x14, mair_el1 + mrs x15, amair_el1 + bl str_in_crash_buf_print + mrs x8, tcr_el1 + mrs x9, tpidr_el1 + mrs x10, tpidr_el0 + mrs x11, tpidrro_el0 + mrs x12, dacr32_el2 + mrs x13, ifsr32_el2 + mrs x14, par_el1 + mrs x15, mpidr_el1 + bl str_in_crash_buf_print + mrs x8, afsr0_el1 + mrs x9, afsr1_el1 + mrs x10, contextidr_el1 + mrs x11, vbar_el1 + mrs x12, cntp_ctl_el0 + mrs x13, cntp_cval_el0 + mrs x14, cntv_ctl_el0 + mrs x15, cntv_cval_el0 + bl str_in_crash_buf_print + mrs x8, cntkctl_el1 + mrs x9, fpexc32_el2 + mrs x10, sp_el0 + mrs x11, isr_el1 + bl str_in_crash_buf_print + + /* Get the cpu specific registers to report */ + bl do_cpu_reg_dump + bl str_in_crash_buf_print + + /* Print some platform registers */ + plat_crash_print_regs + + /* Done reporting */ + bl plat_panic_handler +endfunc do_crash_reporting + +#else /* CRASH_REPORTING */ +func report_unhandled_exception +report_unhandled_interrupt: + bl plat_panic_handler +endfunc report_unhandled_exception +#endif /* CRASH_REPORTING */ + + +func crash_panic + bl plat_panic_handler +endfunc crash_panic diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/aarch64/runtime_exceptions.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/aarch64/runtime_exceptions.S new file mode 100644 index 0000000..799062e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/aarch64/runtime_exceptions.S @@ -0,0 +1,436 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + + .globl runtime_exceptions + + /* ----------------------------------------------------- + * Handle SMC exceptions separately from other sync. + * exceptions. + * ----------------------------------------------------- + */ + .macro handle_sync_exception + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + mrs x30, esr_el3 + ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH + + cmp x30, #EC_AARCH32_SMC + b.eq smc_handler32 + + cmp x30, #EC_AARCH64_SMC + b.eq smc_handler64 + + /* ----------------------------------------------------- + * The following code handles any synchronous exception + * that is not an SMC. + * ----------------------------------------------------- + */ + + bl report_unhandled_exception + .endm + + + /* ----------------------------------------------------- + * This macro handles FIQ or IRQ interrupts i.e. EL3, + * S-EL1 and NS interrupts. + * ----------------------------------------------------- + */ + .macro handle_interrupt_exception label + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + bl save_gp_registers + + /* + * Save the EL3 system registers needed to return from + * this exception. + */ + mrs x0, spsr_el3 + mrs x1, elr_el3 + stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] + + /* Switch to the runtime stack i.e. SP_EL0 */ + ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] + mov x20, sp + msr spsel, #0 + mov sp, x2 + + /* + * Find out whether this is a valid interrupt type. If the + * interrupt controller reports a spurious interrupt then + * return to where we came from. + */ + bl plat_ic_get_pending_interrupt_type + cmp x0, #INTR_TYPE_INVAL + b.eq interrupt_exit_\label + + /* + * Get the registered handler for this interrupt type. A + * NULL return value could be 'cause of the following + * conditions: + * + * a. An interrupt of a type was routed correctly but a + * handler for its type was not registered. + * + * b. An interrupt of a type was not routed correctly so + * a handler for its type was not registered. + * + * c. An interrupt of a type was routed correctly to EL3, + * but was deasserted before its pending state could + * be read. Another interrupt of a different type pended + * at the same time and its type was reported as pending + * instead. However, a handler for this type was not + * registered. + * + * a. and b. can only happen due to a programming error. + * The occurrence of c. could be beyond the control of + * Trusted Firmware. It makes sense to return from this + * exception instead of reporting an error. + */ + bl get_interrupt_type_handler + cbz x0, interrupt_exit_\label + mov x21, x0 + + mov x0, #INTR_ID_UNAVAILABLE + + /* Set the current security state in the 'flags' parameter */ + mrs x2, scr_el3 + ubfx x1, x2, #0, #1 + + /* Restore the reference to the 'handle' i.e. SP_EL3 */ + mov x2, x20 + + /* x3 will point to a cookie (not used now) */ + mov x3, xzr + + /* Call the interrupt type handler */ + blr x21 + +interrupt_exit_\label: + /* Return from exception, possibly in a different security state */ + b el3_exit + + .endm + + + .macro save_x18_to_x29_sp_el0 + stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] + stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] + stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] + stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] + stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] + stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] + mrs x18, sp_el0 + str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] + .endm + + +vector_base runtime_exceptions + + /* ----------------------------------------------------- + * Current EL with _sp_el0 : 0x0 - 0x200 + * ----------------------------------------------------- + */ +vector_entry sync_exception_sp_el0 + /* ----------------------------------------------------- + * We don't expect any synchronous exceptions from EL3 + * ----------------------------------------------------- + */ + bl report_unhandled_exception + check_vector_size sync_exception_sp_el0 + + /* ----------------------------------------------------- + * EL3 code is non-reentrant. Any asynchronous exception + * is a serious error. Loop infinitely. + * ----------------------------------------------------- + */ +vector_entry irq_sp_el0 + bl report_unhandled_interrupt + check_vector_size irq_sp_el0 + + +vector_entry fiq_sp_el0 + bl report_unhandled_interrupt + check_vector_size fiq_sp_el0 + + +vector_entry serror_sp_el0 + bl report_unhandled_exception + check_vector_size serror_sp_el0 + + /* ----------------------------------------------------- + * Current EL with SPx: 0x200 - 0x400 + * ----------------------------------------------------- + */ + +vector_entry sync_exception_sp_elx + /* ----------------------------------------------------- + * This exception will trigger if anything went wrong + * during a previous exception entry or exit or while + * handling an earlier unexpected synchronous exception. + * There is a high probability that SP_EL3 is corrupted. + * ----------------------------------------------------- + */ + bl report_unhandled_exception + check_vector_size sync_exception_sp_elx + +vector_entry irq_sp_elx + bl report_unhandled_interrupt + check_vector_size irq_sp_elx + +vector_entry fiq_sp_elx + bl report_unhandled_interrupt + check_vector_size fiq_sp_elx + +vector_entry serror_sp_elx + bl report_unhandled_exception + check_vector_size serror_sp_elx + + /* ----------------------------------------------------- + * Lower EL using AArch64 : 0x400 - 0x600 + * ----------------------------------------------------- + */ +vector_entry sync_exception_aarch64 + /* ----------------------------------------------------- + * This exception vector will be the entry point for + * SMCs and traps that are unhandled at lower ELs most + * commonly. SP_EL3 should point to a valid cpu context + * where the general purpose and system register state + * can be saved. + * ----------------------------------------------------- + */ + handle_sync_exception + check_vector_size sync_exception_aarch64 + + /* ----------------------------------------------------- + * Asynchronous exceptions from lower ELs are not + * currently supported. Report their occurrence. + * ----------------------------------------------------- + */ +vector_entry irq_aarch64 + handle_interrupt_exception irq_aarch64 + check_vector_size irq_aarch64 + +vector_entry fiq_aarch64 + handle_interrupt_exception fiq_aarch64 + check_vector_size fiq_aarch64 + +vector_entry serror_aarch64 + bl report_unhandled_exception + check_vector_size serror_aarch64 + + /* ----------------------------------------------------- + * Lower EL using AArch32 : 0x600 - 0x800 + * ----------------------------------------------------- + */ +vector_entry sync_exception_aarch32 + /* ----------------------------------------------------- + * This exception vector will be the entry point for + * SMCs and traps that are unhandled at lower ELs most + * commonly. SP_EL3 should point to a valid cpu context + * where the general purpose and system register state + * can be saved. + * ----------------------------------------------------- + */ + handle_sync_exception + check_vector_size sync_exception_aarch32 + + /* ----------------------------------------------------- + * Asynchronous exceptions from lower ELs are not + * currently supported. Report their occurrence. + * ----------------------------------------------------- + */ +vector_entry irq_aarch32 + handle_interrupt_exception irq_aarch32 + check_vector_size irq_aarch32 + +vector_entry fiq_aarch32 + handle_interrupt_exception fiq_aarch32 + check_vector_size fiq_aarch32 + +vector_entry serror_aarch32 + bl report_unhandled_exception + check_vector_size serror_aarch32 + + + /* ----------------------------------------------------- + * The following code handles secure monitor calls. + * Depending upon the execution state from where the SMC + * has been invoked, it frees some general purpose + * registers to perform the remaining tasks. They + * involve finding the runtime service handler that is + * the target of the SMC & switching to runtime stacks + * (SP_EL0) before calling the handler. + * + * Note that x30 has been explicitly saved and can be + * used here + * ----------------------------------------------------- + */ +func smc_handler +smc_handler32: + /* Check whether aarch32 issued an SMC64 */ + tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited + + /* ----------------------------------------------------- + * Since we're are coming from aarch32, x8-x18 need to + * be saved as per SMC32 calling convention. If a lower + * EL in aarch64 is making an SMC32 call then it must + * have saved x8-x17 already therein. + * ----------------------------------------------------- + */ + stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] + stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] + stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] + stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] + stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] + + /* x4-x7, x18, sp_el0 are saved below */ + +smc_handler64: + /* ----------------------------------------------------- + * Populate the parameters for the SMC handler. We + * already have x0-x4 in place. x5 will point to a + * cookie (not used now). x6 will point to the context + * structure (SP_EL3) and x7 will contain flags we need + * to pass to the handler Hence save x5-x7. Note that x4 + * only needs to be preserved for AArch32 callers but we + * do it for AArch64 callers as well for convenience + * ----------------------------------------------------- + */ + stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] + + /* Save rest of the gpregs and sp_el0*/ + save_x18_to_x29_sp_el0 + + mov x5, xzr + mov x6, sp + + /* Get the unique owning entity number */ + ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH + ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH + orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH + + adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) + + /* Load descriptor index from array of indices */ + adr x14, rt_svc_descs_indices + ldrb w15, [x14, x16] + + /* ----------------------------------------------------- + * Restore the saved C runtime stack value which will + * become the new SP_EL0 i.e. EL3 runtime stack. It was + * saved in the 'cpu_context' structure prior to the last + * ERET from EL3. + * ----------------------------------------------------- + */ + ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] + + /* + * Any index greater than 127 is invalid. Check bit 7 for + * a valid index + */ + tbnz w15, 7, smc_unknown + + /* Switch to SP_EL0 */ + msr spsel, #0 + + /* ----------------------------------------------------- + * Get the descriptor using the index + * x11 = (base + off), x15 = index + * + * handler = (base + off) + (index << log2(size)) + * ----------------------------------------------------- + */ + lsl w10, w15, #RT_SVC_SIZE_LOG2 + ldr x15, [x11, w10, uxtw] + + /* ----------------------------------------------------- + * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there + * is a world switch during SMC handling. + * TODO: Revisit if all system registers can be saved + * later. + * ----------------------------------------------------- + */ + mrs x16, spsr_el3 + mrs x17, elr_el3 + mrs x18, scr_el3 + stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] + str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] + + /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ + bfi x7, x18, #0, #1 + + mov sp, x12 + + /* ----------------------------------------------------- + * Call the Secure Monitor Call handler and then drop + * directly into el3_exit() which will program any + * remaining architectural state prior to issuing the + * ERET to the desired lower EL. + * ----------------------------------------------------- + */ +#if DEBUG + cbz x15, rt_svc_fw_critical_error +#endif + blr x15 + + b el3_exit + +smc_unknown: + /* + * Here we restore x4-x18 regardless of where we came from. AArch32 + * callers will find the registers contents unchanged, but AArch64 + * callers will find the registers modified (with stale earlier NS + * content). Either way, we aren't leaking any secure information + * through them + */ + mov w0, #SMC_UNK + b restore_gp_registers_callee_eret + +smc_prohibited: + ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + mov w0, #SMC_UNK + eret + +rt_svc_fw_critical_error: + msr spsel, #1 /* Switch to SP_ELx */ + bl report_unhandled_exception +endfunc smc_handler diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/bl31.ld.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/bl31.ld.S new file mode 100644 index 0000000..8ff61f2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/bl31.ld.S @@ -0,0 +1,277 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) +OUTPUT_ARCH(PLATFORM_LINKER_ARCH) +ENTRY(bl31_entrypoint) + + +MEMORY { + RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE +#if PLAT_rcar + SRAM (rwx): ORIGIN = BL31_SRAM_BASE, LENGTH = BL31_SRAM_LIMIT - BL31_SRAM_BASE +#endif +} + + +SECTIONS +{ + . = BL31_BASE; + ASSERT(. == ALIGN(4096), + "BL31_BASE address is not aligned on a page boundary.") + +#if SEPARATE_CODE_AND_RODATA + .text . : { + __TEXT_START__ = .; + *bl31_entrypoint.o(.text*) + *(.text*) + *(.vectors) + . = NEXT(4096); + __TEXT_END__ = .; + } >RAM + + .rodata . : { + __RODATA_START__ = .; + *(.rodata*) + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __RT_SVC_DESCS_START__ = .; + KEEP(*(rt_svc_descs)) + __RT_SVC_DESCS_END__ = .; + +#if ENABLE_PMF + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __PMF_SVC_DESCS_START__ = .; + KEEP(*(pmf_svc_descs)) + __PMF_SVC_DESCS_END__ = .; +#endif /* ENABLE_PMF */ + + /* + * Ensure 8-byte alignment for cpu_ops so that its fields are also + * aligned. Also ensure cpu_ops inclusion. + */ + . = ALIGN(8); + __CPU_OPS_START__ = .; + KEEP(*(cpu_ops)) + __CPU_OPS_END__ = .; + + . = NEXT(4096); + __RODATA_END__ = .; + } >RAM +#else + ro . : { + __RO_START__ = .; + *bl31_entrypoint.o(.text*) +#if PLAT_rcar + . = NEXT(ALIGN_VERSION); + *rcar_common.o(.version*) + + __SRAM_COPY_START__ = .; + } >RAM +#if PMIC_ON_BOARD + .system_ram : { + __system_ram_start__ = .; + *(.system_ram*) + *(.rodata) + __system_ram_end__ = .; + } >SRAM AT> RAM +#endif /* PMIC_ON_BOARD */ + . = BL31_BASE; + . : { +#endif + *(.text*) + *(.rodata*) + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __RT_SVC_DESCS_START__ = .; + KEEP(*(rt_svc_descs)) + __RT_SVC_DESCS_END__ = .; + +#if ENABLE_PMF + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __PMF_SVC_DESCS_START__ = .; + KEEP(*(pmf_svc_descs)) + __PMF_SVC_DESCS_END__ = .; +#endif /* ENABLE_PMF */ + + /* + * Ensure 8-byte alignment for cpu_ops so that its fields are also + * aligned. Also ensure cpu_ops inclusion. + */ + . = ALIGN(8); + __CPU_OPS_START__ = .; + KEEP(*(cpu_ops)) + __CPU_OPS_END__ = .; + + *(.vectors) + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as read-only, + * executable. No RW data from the next section must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __RO_END__ = .; + } >RAM +#endif + + ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, + "cpu_ops not defined for this platform.") + + /* + * Define a linker symbol to mark start of the RW memory area for this + * image. + */ + __RW_START__ = . ; + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + +#ifdef BL31_PROGBITS_LIMIT + ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") +#endif + + stacks (NOLOAD) : { + __STACKS_START__ = .; + *(tzfw_normal_stacks) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss (NOLOAD) : ALIGN(16) { + __BSS_START__ = .; + *(.bss*) + *(COMMON) +#if !USE_COHERENT_MEM + /* + * Bakery locks are stored in normal .bss memory + * + * Each lock's data is spread across multiple cache lines, one per CPU, + * but multiple locks can share the same cache line. + * The compiler will allocate enough memory for one CPU's bakery locks, + * the remaining cache lines are allocated by the linker script + */ + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __BAKERY_LOCK_START__ = .; + *(bakery_lock) + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); + . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); + __BAKERY_LOCK_END__ = .; +#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE + ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, + "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); +#endif +#endif + +#if ENABLE_PMF + /* + * Time-stamps are stored in normal .bss memory + * + * The compiler will allocate enough memory for one CPU's time-stamps, + * the remaining memory for other CPU's is allocated by the + * linker script + */ + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __PMF_TIMESTAMP_START__ = .; + KEEP(*(pmf_timestamp_array)) + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __PMF_PERCPU_TIMESTAMP_END__ = .; + __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); + . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); + __PMF_TIMESTAMP_END__ = .; +#endif /* ENABLE_PMF */ + __BSS_END__ = .; + } >RAM + + /* + * The xlat_table section is for full, aligned page tables (4K). + * Removing them from .bss avoids forcing 4K alignment on + * the .bss section and eliminates the unecessary zero init + */ + xlat_table (NOLOAD) : { + *(xlat_table) + } >RAM + +#if USE_COHERENT_MEM + /* + * The base address of the coherent memory section must be page-aligned (4K) + * to guarantee that the coherent data are stored on their own pages and + * are not mixed with normal data. This is required to set up the correct + * memory attributes for the coherent data page tables. + */ + coherent_ram (NOLOAD) : ALIGN(4096) { + __COHERENT_RAM_START__ = .; + /* + * Bakery locks are stored in coherent memory + * + * Each lock's data is contiguous and fully allocated by the compiler + */ + *(bakery_lock) + *(tzfw_coherent_mem) + __COHERENT_RAM_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked + * as device memory. No other unexpected data must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __COHERENT_RAM_END__ = .; + } >RAM +#endif + + /* + * Define a linker symbol to mark end of the RW memory area for this + * image. + */ + __RW_END__ = .; + __BL31_END__ = .; + + __BSS_SIZE__ = SIZEOF(.bss); +#if USE_COHERENT_MEM + __COHERENT_RAM_UNALIGNED_SIZE__ = + __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; +#endif + + ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/bl31.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/bl31.mk new file mode 100644 index 0000000..4de511b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/bl31.mk @@ -0,0 +1,56 @@ +# +# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +include lib/psci/psci_lib.mk + +BL31_SOURCES += bl31/bl31_main.c \ + bl31/interrupt_mgmt.c \ + bl31/aarch64/bl31_entrypoint.S \ + bl31/aarch64/runtime_exceptions.S \ + bl31/aarch64/crash_reporting.S \ + bl31/bl31_context_mgmt.c \ + common/runtime_svc.c \ + services/std_svc/std_svc_setup.c \ + ${PSCI_LIB_SOURCES} + +ifeq (${ENABLE_PMF}, 1) +BL31_SOURCES += lib/pmf/pmf_main.c +endif + +BL31_LINKERFILE := bl31/bl31.ld.S + +# Flag used to indicate if Crash reporting via console should be included +# in BL31. This defaults to being present in DEBUG builds only +ifndef CRASH_REPORTING +CRASH_REPORTING := $(DEBUG) +endif + +$(eval $(call assert_boolean,CRASH_REPORTING)) +$(eval $(call add_define,CRASH_REPORTING)) diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/bl31_context_mgmt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/bl31_context_mgmt.c new file mode 100644 index 0000000..f8751c2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/bl31_context_mgmt.c @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + + +/******************************************************************************* + * This function returns a pointer to the most recent 'cpu_context' structure + * for the calling CPU that was set as the context for the specified security + * state. NULL is returned if no such structure has been specified. + ******************************************************************************/ +void *cm_get_context(uint32_t security_state) +{ + assert(security_state <= NON_SECURE); + + return get_cpu_data(cpu_context[security_state]); +} + +/******************************************************************************* + * This function sets the pointer to the current 'cpu_context' structure for the + * specified security state for the calling CPU + ******************************************************************************/ +void cm_set_context(void *context, uint32_t security_state) +{ + assert(security_state <= NON_SECURE); + + set_cpu_data(cpu_context[security_state], context); +} + +/******************************************************************************* + * This function returns a pointer to the most recent 'cpu_context' structure + * for the CPU identified by `cpu_idx` that was set as the context for the + * specified security state. NULL is returned if no such structure has been + * specified. + ******************************************************************************/ +void *cm_get_context_by_index(unsigned int cpu_idx, + unsigned int security_state) +{ + assert(sec_state_is_valid(security_state)); + + return get_cpu_data_by_index(cpu_idx, cpu_context[security_state]); +} + +/******************************************************************************* + * This function sets the pointer to the current 'cpu_context' structure for the + * specified security state for the CPU identified by CPU index. + ******************************************************************************/ +void cm_set_context_by_index(unsigned int cpu_idx, void *context, + unsigned int security_state) +{ + assert(sec_state_is_valid(security_state)); + + set_cpu_data_by_index(cpu_idx, cpu_context[security_state], context); +} + +#if !ERROR_DEPRECATED +/* + * These context management helpers are deprecated but are maintained for use + * by SPDs which have not migrated to the new API. If ERROR_DEPRECATED + * is enabled, these are excluded from the build so as to force users to + * migrate to the new API. + */ + +/******************************************************************************* + * This function returns a pointer to the most recent 'cpu_context' structure + * for the CPU identified by MPIDR that was set as the context for the specified + * security state. NULL is returned if no such structure has been specified. + ******************************************************************************/ +void *cm_get_context_by_mpidr(uint64_t mpidr, uint32_t security_state) +{ + assert(sec_state_is_valid(security_state)); + + return cm_get_context_by_index(platform_get_core_pos(mpidr), security_state); +} + +/******************************************************************************* + * This function sets the pointer to the current 'cpu_context' structure for the + * specified security state for the CPU identified by MPIDR + ******************************************************************************/ +void cm_set_context_by_mpidr(uint64_t mpidr, void *context, uint32_t security_state) +{ + assert(sec_state_is_valid(security_state)); + + cm_set_context_by_index(platform_get_core_pos(mpidr), + context, security_state); +} + +/******************************************************************************* + * The following function provides a compatibility function for SPDs using the + * existing cm library routines. This function is expected to be invoked for + * initializing the cpu_context for the CPU specified by MPIDR for first use. + ******************************************************************************/ +void cm_init_context(unsigned long mpidr, const entry_point_info_t *ep) +{ + if ((mpidr & MPIDR_AFFINITY_MASK) == + (read_mpidr_el1() & MPIDR_AFFINITY_MASK)) + cm_init_my_context(ep); + else + cm_init_context_by_index(platform_get_core_pos(mpidr), ep); +} +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/bl31_main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/bl31_main.c new file mode 100644 index 0000000..fae5ee4 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/bl31_main.c @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * This function pointer is used to initialise the BL32 image. It's initialized + * by SPD calling bl31_register_bl32_init after setting up all things necessary + * for SP execution. In cases where both SPD and SP are absent, or when SPD + * finds it impossible to execute SP, this pointer is left as NULL + ******************************************************************************/ +static int32_t (*bl32_init)(void); + +/******************************************************************************* + * Variable to indicate whether next image to execute after BL31 is BL33 + * (non-secure & default) or BL32 (secure). + ******************************************************************************/ +static uint32_t next_image_type = NON_SECURE; + +/* + * Implement the ARM Standard Service function to get arguments for a + * particular service. + */ +uintptr_t get_arm_std_svc_args(unsigned int svc_mask) +{ + /* Setup the arguments for PSCI Library */ + DEFINE_STATIC_PSCI_LIB_ARGS_V1(psci_args, bl31_warm_entrypoint); + + /* PSCI is the only ARM Standard Service implemented */ + assert(svc_mask == PSCI_FID_MASK); + + return (uintptr_t)&psci_args; +} + +/******************************************************************************* + * Simple function to initialise all BL31 helper libraries. + ******************************************************************************/ +void bl31_lib_init(void) +{ + cm_init(); +} + +/******************************************************************************* + * BL31 is responsible for setting up the runtime services for the primary cpu + * before passing control to the bootloader or an Operating System. This + * function calls runtime_svc_init() which initializes all registered runtime + * services. The run time services would setup enough context for the core to + * swtich to the next exception level. When this function returns, the core will + * switch to the programmed exception level via. an ERET. + ******************************************************************************/ +void bl31_main(void) +{ + NOTICE("BL31: %s\n", version_string); + NOTICE("BL31: %s\n", build_message); + + /* Perform platform setup in BL31 */ + bl31_platform_setup(); + + /* Initialise helper libraries */ + bl31_lib_init(); + + /* Initialize the runtime services e.g. psci. */ + INFO("BL31: Initializing runtime services\n"); + runtime_svc_init(); + + /* + * All the cold boot actions on the primary cpu are done. We now need to + * decide which is the next image (BL32 or BL33) and how to execute it. + * If the SPD runtime service is present, it would want to pass control + * to BL32 first in S-EL1. In that case, SPD would have registered a + * function to intialize bl32 where it takes responsibility of entering + * S-EL1 and returning control back to bl31_main. Once this is done we + * can prepare entry into BL33 as normal. + */ + + /* + * If SPD had registerd an init hook, invoke it. + */ + if (bl32_init) { + INFO("BL31: Initializing BL32\n"); + (*bl32_init)(); + } + /* + * We are ready to enter the next EL. Prepare entry into the image + * corresponding to the desired security state after the next ERET. + */ + bl31_prepare_next_image_entry(); + + /* + * Perform any platform specific runtime setup prior to cold boot exit + * from BL31 + */ + bl31_plat_runtime_setup(); +} + +/******************************************************************************* + * Accessor functions to help runtime services decide which image should be + * executed after BL31. This is BL33 or the non-secure bootloader image by + * default but the Secure payload dispatcher could override this by requesting + * an entry into BL32 (Secure payload) first. If it does so then it should use + * the same API to program an entry into BL33 once BL32 initialisation is + * complete. + ******************************************************************************/ +void bl31_set_next_image_type(uint32_t security_state) +{ + assert(sec_state_is_valid(security_state)); + next_image_type = security_state; +} + +uint32_t bl31_get_next_image_type(void) +{ + return next_image_type; +} + +/******************************************************************************* + * This function programs EL3 registers and performs other setup to enable entry + * into the next image after BL31 at the next ERET. + ******************************************************************************/ +void bl31_prepare_next_image_entry(void) +{ + entry_point_info_t *next_image_info; + uint32_t image_type; + +#if CTX_INCLUDE_AARCH32_REGS + /* + * Ensure that the build flag to save AArch32 system registers in CPU + * context is not set for AArch64-only platforms. + */ + if (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL1_SHIFT) + & ID_AA64PFR0_ELX_MASK) == 0x1) { + ERROR("EL1 supports AArch64-only. Please set build flag " + "CTX_INCLUDE_AARCH32_REGS = 0"); + panic(); + } +#endif + + /* Determine which image to execute next */ + image_type = bl31_get_next_image_type(); + + /* Program EL3 registers to enable entry into the next EL */ + next_image_info = bl31_plat_get_next_image_ep_info(image_type); + assert(next_image_info); + assert(image_type == GET_SECURITY_STATE(next_image_info->h.attr)); + + INFO("BL31: Preparing for EL3 exit to %s world\n", + (image_type == SECURE) ? "secure" : "normal"); + print_entry_point_info(next_image_info); + cm_init_my_context(next_image_info); + cm_prepare_el3_exit(image_type); +} + +/******************************************************************************* + * This function initializes the pointer to BL32 init function. This is expected + * to be called by the SPD after it finishes all its initialization + ******************************************************************************/ +void bl31_register_bl32_init(int32_t (*func)(void)) +{ + bl32_init = func; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/interrupt_mgmt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/interrupt_mgmt.c new file mode 100644 index 0000000..e991851 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl31/interrupt_mgmt.c @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Local structure and corresponding array to keep track of the state of the + * registered interrupt handlers for each interrupt type. + * The field descriptions are: + * + * 'flags' : Bit[0], Routing model for this interrupt type when execution is + * not in EL3 in the secure state. '1' implies that this + * interrupt will be routed to EL3. '0' implies that this + * interrupt will be routed to the current exception level. + * + * Bit[1], Routing model for this interrupt type when execution is + * not in EL3 in the non-secure state. '1' implies that this + * interrupt will be routed to EL3. '0' implies that this + * interrupt will be routed to the current exception level. + * + * All other bits are reserved and SBZ. + * + * 'scr_el3[2]' : Mapping of the routing model in the 'flags' field to the + * value of the SCR_EL3.IRQ or FIQ bit for each security state. + * There are two instances of this field corresponding to the + * two security states. + ******************************************************************************/ +typedef struct intr_type_desc { + interrupt_type_handler_t handler; + uint32_t flags; + uint32_t scr_el3[2]; +} intr_type_desc_t; + +static intr_type_desc_t intr_type_descs[MAX_INTR_TYPES]; + +/******************************************************************************* + * This function validates the interrupt type. + ******************************************************************************/ +static int32_t validate_interrupt_type(uint32_t type) +{ + if (type == INTR_TYPE_S_EL1 || type == INTR_TYPE_NS || + type == INTR_TYPE_EL3) + return 0; + + return -EINVAL; +} + +/******************************************************************************* +* This function validates the routing model for this type of interrupt + ******************************************************************************/ +static int32_t validate_routing_model(uint32_t type, uint32_t flags) +{ + flags >>= INTR_RM_FLAGS_SHIFT; + flags &= INTR_RM_FLAGS_MASK; + + if (type == INTR_TYPE_S_EL1) + return validate_sel1_interrupt_rm(flags); + + if (type == INTR_TYPE_NS) + return validate_ns_interrupt_rm(flags); + + if (type == INTR_TYPE_EL3) + return validate_el3_interrupt_rm(flags); + + return -EINVAL; +} + +/******************************************************************************* + * This function returns the cached copy of the SCR_EL3 which contains the + * routing model (expressed through the IRQ and FIQ bits) for a security state + * which was stored through a call to 'set_routing_model()' earlier. + ******************************************************************************/ +uint32_t get_scr_el3_from_routing_model(uint32_t security_state) +{ + uint32_t scr_el3; + + assert(sec_state_is_valid(security_state)); + scr_el3 = intr_type_descs[INTR_TYPE_NS].scr_el3[security_state]; + scr_el3 |= intr_type_descs[INTR_TYPE_S_EL1].scr_el3[security_state]; + scr_el3 |= intr_type_descs[INTR_TYPE_EL3].scr_el3[security_state]; + return scr_el3; +} + +/******************************************************************************* + * This function uses the 'interrupt_type_flags' parameter to obtain the value + * of the trap bit (IRQ/FIQ) in the SCR_EL3 for a security state for this + * interrupt type. It uses it to update the SCR_EL3 in the cpu context and the + * 'intr_type_desc' for that security state. + ******************************************************************************/ +static void set_scr_el3_from_rm(uint32_t type, + uint32_t interrupt_type_flags, + uint32_t security_state) +{ + uint32_t flag, bit_pos; + + flag = get_interrupt_rm_flag(interrupt_type_flags, security_state); + bit_pos = plat_interrupt_type_to_line(type, security_state); + intr_type_descs[type].scr_el3[security_state] = flag << bit_pos; + + /* Update scr_el3 only if there is a context available. If not, it + * will be updated later during context initialization which will obtain + * the scr_el3 value to be used via get_scr_el3_from_routing_model() */ + if (cm_get_context(security_state)) + cm_write_scr_el3_bit(security_state, bit_pos, flag); +} + +/******************************************************************************* + * This function validates the routing model specified in the 'flags' and + * updates internal data structures to reflect the new routing model. It also + * updates the copy of SCR_EL3 for each security state with the new routing + * model in the 'cpu_context' structure for this cpu. + ******************************************************************************/ +int32_t set_routing_model(uint32_t type, uint32_t flags) +{ + int32_t rc; + + rc = validate_interrupt_type(type); + if (rc) + return rc; + + rc = validate_routing_model(type, flags); + if (rc) + return rc; + + /* Update the routing model in internal data structures */ + intr_type_descs[type].flags = flags; + set_scr_el3_from_rm(type, flags, SECURE); + set_scr_el3_from_rm(type, flags, NON_SECURE); + + return 0; +} + +/****************************************************************************** + * This function disables the routing model of interrupt 'type' from the + * specified 'security_state' on the local core. The disable is in effect + * till the core powers down or till the next enable for that interrupt + * type. + *****************************************************************************/ +int disable_intr_rm_local(uint32_t type, uint32_t security_state) +{ + uint32_t bit_pos, flag; + + assert(intr_type_descs[type].handler); + + flag = get_interrupt_rm_flag(INTR_DEFAULT_RM, security_state); + + bit_pos = plat_interrupt_type_to_line(type, security_state); + cm_write_scr_el3_bit(security_state, bit_pos, flag); + + return 0; +} + +/****************************************************************************** + * This function enables the routing model of interrupt 'type' from the + * specified 'security_state' on the local core. + *****************************************************************************/ +int enable_intr_rm_local(uint32_t type, uint32_t security_state) +{ + uint32_t bit_pos, flag; + + assert(intr_type_descs[type].handler); + + flag = get_interrupt_rm_flag(intr_type_descs[type].flags, + security_state); + + bit_pos = plat_interrupt_type_to_line(type, security_state); + cm_write_scr_el3_bit(security_state, bit_pos, flag); + + return 0; +} + +/******************************************************************************* + * This function registers a handler for the 'type' of interrupt specified. It + * also validates the routing model specified in the 'flags' for this type of + * interrupt. + ******************************************************************************/ +int32_t register_interrupt_type_handler(uint32_t type, + interrupt_type_handler_t handler, + uint32_t flags) +{ + int32_t rc; + + /* Validate the 'handler' parameter */ + if (!handler) + return -EINVAL; + + /* Validate the 'flags' parameter */ + if (flags & INTR_TYPE_FLAGS_MASK) + return -EINVAL; + + /* Check if a handler has already been registered */ + if (intr_type_descs[type].handler) + return -EALREADY; + + rc = set_routing_model(type, flags); + if (rc) + return rc; + + /* Save the handler */ + intr_type_descs[type].handler = handler; + + return 0; +} + +/******************************************************************************* + * This function is called when an interrupt is generated and returns the + * handler for the interrupt type (if registered). It returns NULL if the + * interrupt type is not supported or its handler has not been registered. + ******************************************************************************/ +interrupt_type_handler_t get_interrupt_type_handler(uint32_t type) +{ + if (validate_interrupt_type(type)) + return NULL; + + return intr_type_descs[type].handler; +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/aarch32/entrypoint.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/aarch32/entrypoint.S new file mode 100644 index 0000000..54f2ced --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/aarch32/entrypoint.S @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + + .globl sp_min_vector_table + .globl sp_min_entrypoint + .globl sp_min_warm_entrypoint + + +vector_base sp_min_vector_table + b sp_min_entrypoint + b plat_panic_handler /* Undef */ + b handle_smc /* Syscall */ + b plat_panic_handler /* Prefetch abort */ + b plat_panic_handler /* Data abort */ + b plat_panic_handler /* Reserved */ + b plat_panic_handler /* IRQ */ + b plat_panic_handler /* FIQ */ + + +/* + * The Cold boot/Reset entrypoint for SP_MIN + */ +func sp_min_entrypoint +#if !RESET_TO_SP_MIN + /* --------------------------------------------------------------- + * Preceding bootloader has populated r0 with a pointer to a + * 'bl_params_t' structure & r1 with a pointer to platform + * specific structure + * --------------------------------------------------------------- + */ + mov r11, r0 + mov r12, r1 + + /* --------------------------------------------------------------------- + * For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches + * sp_min_entrypoint() during the cold boot flow, so the cold/warm boot + * and primary/secondary CPU logic should not be executed in this case. + * + * Also, assume that the previous bootloader has already set up the CPU + * endianness and has initialised the memory. + * --------------------------------------------------------------------- + */ + el3_entrypoint_common \ + _set_endian=0 \ + _warm_boot_mailbox=0 \ + _secondary_cold_boot=0 \ + _init_memory=0 \ + _init_c_runtime=1 \ + _exception_vectors=sp_min_vector_table + + /* --------------------------------------------------------------------- + * Relay the previous bootloader's arguments to the platform layer + * --------------------------------------------------------------------- + */ + mov r0, r11 + mov r1, r12 +#else + /* --------------------------------------------------------------------- + * For RESET_TO_SP_MIN systems which have a programmable reset address, + * sp_min_entrypoint() is executed only on the cold boot path so we can + * skip the warm boot mailbox mechanism. + * --------------------------------------------------------------------- + */ + el3_entrypoint_common \ + _set_endian=1 \ + _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ + _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ + _init_memory=1 \ + _init_c_runtime=1 \ + _exception_vectors=sp_min_vector_table + + /* --------------------------------------------------------------------- + * For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader + * to run so there's no argument to relay from a previous bootloader. + * Zero the arguments passed to the platform layer to reflect that. + * --------------------------------------------------------------------- + */ + mov r0, #0 + mov r1, #0 +#endif /* RESET_TO_SP_MIN */ + + bl sp_min_early_platform_setup + bl sp_min_plat_arch_setup + + /* Jump to the main function */ + bl sp_min_main + + /* ------------------------------------------------------------- + * Clean the .data & .bss sections to main memory. This ensures + * that any global data which was initialised by the primary CPU + * is visible to secondary CPUs before they enable their data + * caches and participate in coherency. + * ------------------------------------------------------------- + */ + ldr r0, =__DATA_START__ + ldr r1, =__DATA_END__ + sub r1, r1, r0 + bl clean_dcache_range + + ldr r0, =__BSS_START__ + ldr r1, =__BSS_END__ + sub r1, r1, r0 + bl clean_dcache_range + + /* Program the registers in cpu_context and exit monitor mode */ + mov r0, #NON_SECURE + bl cm_get_context + + /* Restore the SCR */ + ldr r2, [r0, #CTX_REGS_OFFSET + CTX_SCR] + stcopr r2, SCR + isb + + /* Restore the SCTLR */ + ldr r2, [r0, #CTX_REGS_OFFSET + CTX_NS_SCTLR] + stcopr r2, SCTLR + + bl smc_get_next_ctx + /* The other cpu_context registers have been copied to smc context */ + b sp_min_exit +endfunc sp_min_entrypoint + + +/* + * SMC handling function for SP_MIN. + */ +func handle_smc + smcc_save_gp_mode_regs + + /* r0 points to smc_context */ + mov r2, r0 /* handle */ + ldcopr r0, SCR + + /* Save SCR in stack */ + push {r0} + and r3, r0, #SCR_NS_BIT /* flags */ + + /* Switch to Secure Mode*/ + bic r0, #SCR_NS_BIT + stcopr r0, SCR + isb + ldr r0, [r2, #SMC_CTX_GPREG_R0] /* smc_fid */ + /* Check whether an SMC64 is issued */ + tst r0, #(FUNCID_CC_MASK << FUNCID_CC_SHIFT) + beq 1f /* SMC32 is detected */ + mov r0, #SMC_UNK + str r0, [r2, #SMC_CTX_GPREG_R0] + mov r0, r2 + b 2f /* Skip handling the SMC */ +1: + mov r1, #0 /* cookie */ + bl handle_runtime_svc +2: + /* r0 points to smc context */ + + /* Restore SCR from stack */ + pop {r1} + stcopr r1, SCR + isb + + b sp_min_exit +endfunc handle_smc + + +/* + * The Warm boot entrypoint for SP_MIN. + */ +func sp_min_warm_entrypoint + /* + * On the warm boot path, most of the EL3 initialisations performed by + * 'el3_entrypoint_common' must be skipped: + * + * - Only when the platform bypasses the BL1/BL32 (SP_MIN) entrypoint by + * programming the reset address do we need to set the CPU endianness. + * In other cases, we assume this has been taken care by the + * entrypoint code. + * + * - No need to determine the type of boot, we know it is a warm boot. + * + * - Do not try to distinguish between primary and secondary CPUs, this + * notion only exists for a cold boot. + * + * - No need to initialise the memory or the C runtime environment, + * it has been done once and for all on the cold boot path. + */ + el3_entrypoint_common \ + _set_endian=PROGRAMMABLE_RESET_ADDRESS \ + _warm_boot_mailbox=0 \ + _secondary_cold_boot=0 \ + _init_memory=0 \ + _init_c_runtime=0 \ + _exception_vectors=sp_min_vector_table + + /* -------------------------------------------- + * Enable the MMU with the DCache disabled. It + * is safe to use stacks allocated in normal + * memory as a result. All memory accesses are + * marked nGnRnE when the MMU is disabled. So + * all the stack writes will make it to memory. + * All memory accesses are marked Non-cacheable + * when the MMU is enabled but D$ is disabled. + * So used stack memory is guaranteed to be + * visible immediately after the MMU is enabled + * Enabling the DCache at the same time as the + * MMU can lead to speculatively fetched and + * possibly stale stack memory being read from + * other caches. This can lead to coherency + * issues. + * -------------------------------------------- + */ + mov r0, #DISABLE_DCACHE + bl bl32_plat_enable_mmu + + bl sp_min_warm_boot + + /* Program the registers in cpu_context and exit monitor mode */ + mov r0, #NON_SECURE + bl cm_get_context + + /* Restore the SCR */ + ldr r2, [r0, #CTX_REGS_OFFSET + CTX_SCR] + stcopr r2, SCR + isb + + /* Restore the SCTLR */ + ldr r2, [r0, #CTX_REGS_OFFSET + CTX_NS_SCTLR] + stcopr r2, SCTLR + + bl smc_get_next_ctx + + /* The other cpu_context registers have been copied to smc context */ + b sp_min_exit +endfunc sp_min_warm_entrypoint + +/* + * The function to restore the registers from SMC context and return + * to the mode restored to SPSR. + * + * Arguments : r0 must point to the SMC context to restore from. + */ +func sp_min_exit + smcc_restore_gp_mode_regs + eret +endfunc sp_min_exit diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/sp_min.ld.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/sp_min.ld.S new file mode 100644 index 0000000..e0e23e8 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/sp_min.ld.S @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +OUTPUT_FORMAT(elf32-littlearm) +OUTPUT_ARCH(arm) +ENTRY(sp_min_vector_table) + +MEMORY { + RAM (rwx): ORIGIN = BL32_BASE, LENGTH = BL32_LIMIT - BL32_BASE +} + + +SECTIONS +{ + . = BL32_BASE; + ASSERT(. == ALIGN(4096), + "BL32_BASE address is not aligned on a page boundary.") + +#if SEPARATE_CODE_AND_RODATA + .text . : { + __TEXT_START__ = .; + *entrypoint.o(.text*) + *(.text*) + *(.vectors) + . = NEXT(4096); + __TEXT_END__ = .; + } >RAM + + .rodata . : { + __RODATA_START__ = .; + *(.rodata*) + + /* Ensure 4-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(4); + __RT_SVC_DESCS_START__ = .; + KEEP(*(rt_svc_descs)) + __RT_SVC_DESCS_END__ = .; + + /* + * Ensure 4-byte alignment for cpu_ops so that its fields are also + * aligned. Also ensure cpu_ops inclusion. + */ + . = ALIGN(4); + __CPU_OPS_START__ = .; + KEEP(*(cpu_ops)) + __CPU_OPS_END__ = .; + + . = NEXT(4096); + __RODATA_END__ = .; + } >RAM +#else + ro . : { + __RO_START__ = .; + *entrypoint.o(.text*) + *(.text*) + *(.rodata*) + + /* Ensure 4-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(4); + __RT_SVC_DESCS_START__ = .; + KEEP(*(rt_svc_descs)) + __RT_SVC_DESCS_END__ = .; + + /* + * Ensure 4-byte alignment for cpu_ops so that its fields are also + * aligned. Also ensure cpu_ops inclusion. + */ + . = ALIGN(4); + __CPU_OPS_START__ = .; + KEEP(*(cpu_ops)) + __CPU_OPS_END__ = .; + + *(.vectors) + __RO_END_UNALIGNED__ = .; + + /* + * Memory page(s) mapped to this section will be marked as + * read-only, executable. No RW data from the next section must + * creep in. Ensure the rest of the current memory block is unused. + */ + . = NEXT(4096); + __RO_END__ = .; + } >RAM +#endif + + ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, + "cpu_ops not defined for this platform.") + /* + * Define a linker symbol to mark start of the RW memory area for this + * image. + */ + __RW_START__ = . ; + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + + stacks (NOLOAD) : { + __STACKS_START__ = .; + *(tzfw_normal_stacks) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss (NOLOAD) : ALIGN(16) { + __BSS_START__ = .; + *(.bss*) + *(COMMON) +#if !USE_COHERENT_MEM + /* + * Bakery locks are stored in normal .bss memory + * + * Each lock's data is spread across multiple cache lines, one per CPU, + * but multiple locks can share the same cache line. + * The compiler will allocate enough memory for one CPU's bakery locks, + * the remaining cache lines are allocated by the linker script + */ + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __BAKERY_LOCK_START__ = .; + *(bakery_lock) + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); + . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); + __BAKERY_LOCK_END__ = .; +#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE + ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, + "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); +#endif +#endif + +#if ENABLE_PMF + /* + * Time-stamps are stored in normal .bss memory + * + * The compiler will allocate enough memory for one CPU's time-stamps, + * the remaining memory for other CPU's is allocated by the + * linker script + */ + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __PMF_TIMESTAMP_START__ = .; + KEEP(*(pmf_timestamp_array)) + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __PMF_PERCPU_TIMESTAMP_END__ = .; + __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); + . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); + __PMF_TIMESTAMP_END__ = .; +#endif /* ENABLE_PMF */ + + __BSS_END__ = .; + } >RAM + + /* + * The xlat_table section is for full, aligned page tables (4K). + * Removing them from .bss avoids forcing 4K alignment on + * the .bss section and eliminates the unecessary zero init + */ + xlat_table (NOLOAD) : { + *(xlat_table) + } >RAM + + __BSS_SIZE__ = SIZEOF(.bss); + +#if USE_COHERENT_MEM + /* + * The base address of the coherent memory section must be page-aligned (4K) + * to guarantee that the coherent data are stored on their own pages and + * are not mixed with normal data. This is required to set up the correct + * memory attributes for the coherent data page tables. + */ + coherent_ram (NOLOAD) : ALIGN(4096) { + __COHERENT_RAM_START__ = .; + /* + * Bakery locks are stored in coherent memory + * + * Each lock's data is contiguous and fully allocated by the compiler + */ + *(bakery_lock) + *(tzfw_coherent_mem) + __COHERENT_RAM_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked + * as device memory. No other unexpected data must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __COHERENT_RAM_END__ = .; + } >RAM + + __COHERENT_RAM_UNALIGNED_SIZE__ = + __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; +#endif + + /* + * Define a linker symbol to mark end of the RW memory area for this + * image. + */ + __RW_END__ = .; + + __BL32_END__ = .; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/sp_min.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/sp_min.mk new file mode 100644 index 0000000..ac7f03e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/sp_min.mk @@ -0,0 +1,63 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +ifneq (${ARCH}, aarch32) + $(error SP_MIN is only supported on AArch32 platforms) +endif + +include lib/psci/psci_lib.mk + +INCLUDES += -Iinclude/bl32/sp_min + +BL32_SOURCES += bl32/sp_min/sp_min_main.c \ + bl32/sp_min/aarch32/entrypoint.S \ + common/runtime_svc.c \ + services/std_svc/std_svc_setup.c \ + ${PSCI_LIB_SOURCES} + +ifeq (${ENABLE_PMF}, 1) +BL32_SOURCES += lib/pmf/pmf_main.c +endif + +BL32_LINKERFILE := bl32/sp_min/sp_min.ld.S + +# Include the platform-specific SP_MIN Makefile +# If no platform-specific SP_MIN Makefile exists, it means SP_MIN is not supported +# on this platform. +SP_MIN_PLAT_MAKEFILE := $(wildcard ${PLAT_DIR}/sp_min/sp_min-${PLAT}.mk) +ifeq (,${SP_MIN_PLAT_MAKEFILE}) + $(error SP_MIN is not supported on platform ${PLAT}) +else + include ${SP_MIN_PLAT_MAKEFILE} +endif + +RESET_TO_SP_MIN := 0 +$(eval $(call add_define,RESET_TO_SP_MIN)) +$(eval $(call assert_boolean,RESET_TO_SP_MIN)) diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/sp_min_main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/sp_min_main.c new file mode 100644 index 0000000..02663a2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/sp_min_main.c @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "sp_min_private.h" + +/* Pointers to per-core cpu contexts */ +static void *sp_min_cpu_ctx_ptr[PLATFORM_CORE_COUNT]; + +/* SP_MIN only stores the non secure smc context */ +static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT]; + +/****************************************************************************** + * Define the smcc helper library API's + *****************************************************************************/ +void *smc_get_ctx(int security_state) +{ + assert(security_state == NON_SECURE); + return &sp_min_smc_context[plat_my_core_pos()]; +} + +void smc_set_next_ctx(int security_state) +{ + assert(security_state == NON_SECURE); + /* SP_MIN stores only non secure smc context. Nothing to do here */ +} + +void *smc_get_next_ctx(void) +{ + return &sp_min_smc_context[plat_my_core_pos()]; +} + +/******************************************************************************* + * This function returns a pointer to the most recent 'cpu_context' structure + * for the calling CPU that was set as the context for the specified security + * state. NULL is returned if no such structure has been specified. + ******************************************************************************/ +void *cm_get_context(uint32_t security_state) +{ + assert(security_state == NON_SECURE); + return sp_min_cpu_ctx_ptr[plat_my_core_pos()]; +} + +/******************************************************************************* + * This function sets the pointer to the current 'cpu_context' structure for the + * specified security state for the calling CPU + ******************************************************************************/ +void cm_set_context(void *context, uint32_t security_state) +{ + assert(security_state == NON_SECURE); + sp_min_cpu_ctx_ptr[plat_my_core_pos()] = context; +} + +/******************************************************************************* + * This function returns a pointer to the most recent 'cpu_context' structure + * for the CPU identified by `cpu_idx` that was set as the context for the + * specified security state. NULL is returned if no such structure has been + * specified. + ******************************************************************************/ +void *cm_get_context_by_index(unsigned int cpu_idx, + unsigned int security_state) +{ + assert(security_state == NON_SECURE); + return sp_min_cpu_ctx_ptr[cpu_idx]; +} + +/******************************************************************************* + * This function sets the pointer to the current 'cpu_context' structure for the + * specified security state for the CPU identified by CPU index. + ******************************************************************************/ +void cm_set_context_by_index(unsigned int cpu_idx, void *context, + unsigned int security_state) +{ + assert(security_state == NON_SECURE); + sp_min_cpu_ctx_ptr[cpu_idx] = context; +} + +static void copy_cpu_ctx_to_smc_stx(const regs_t *cpu_reg_ctx, + smc_ctx_t *next_smc_ctx) +{ + next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0); + next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR); + next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR); +} + +/******************************************************************************* + * This function invokes the PSCI library interface to initialize the + * non secure cpu context and copies the relevant cpu context register values + * to smc context. These registers will get programmed during `smc_exit`. + ******************************************************************************/ +static void sp_min_prepare_next_image_entry(void) +{ + entry_point_info_t *next_image_info; + + /* Program system registers to proceed to non-secure */ + next_image_info = sp_min_plat_get_bl33_ep_info(); + assert(next_image_info); + assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr)); + + INFO("SP_MIN: Preparing exit to normal world\n"); + + psci_prepare_next_non_secure_ctx(next_image_info); + smc_set_next_ctx(NON_SECURE); + + /* Copy r0, lr and spsr from cpu context to SMC context */ + copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)), + smc_get_next_ctx()); +} + +/****************************************************************************** + * Implement the ARM Standard Service function to get arguments for a + * particular service. + *****************************************************************************/ +uintptr_t get_arm_std_svc_args(unsigned int svc_mask) +{ + /* Setup the arguments for PSCI Library */ + DEFINE_STATIC_PSCI_LIB_ARGS_V1(psci_args, sp_min_warm_entrypoint); + + /* PSCI is the only ARM Standard Service implemented */ + assert(svc_mask == PSCI_FID_MASK); + + return (uintptr_t)&psci_args; +} + +/****************************************************************************** + * The SP_MIN main function. Do the platform and PSCI Library setup. Also + * initialize the runtime service framework. + *****************************************************************************/ +void sp_min_main(void) +{ + NOTICE("SP_MIN: %s\n", version_string); + NOTICE("SP_MIN: %s\n", build_message); + + /* Perform the SP_MIN platform setup */ + sp_min_platform_setup(); + + /* Initialize the runtime services e.g. psci */ + INFO("SP_MIN: Initializing runtime services\n"); + runtime_svc_init(); + + /* + * We are ready to enter the next EL. Prepare entry into the image + * corresponding to the desired security state after the next ERET. + */ + sp_min_prepare_next_image_entry(); +} + +/****************************************************************************** + * This function is invoked during warm boot. Invoke the PSCI library + * warm boot entry point which takes care of Architectural and platform setup/ + * restore. Copy the relevant cpu_context register values to smc context which + * will get programmed during `smc_exit`. + *****************************************************************************/ +void sp_min_warm_boot(void) +{ + smc_ctx_t *next_smc_ctx; + + psci_warmboot_entrypoint(); + + smc_set_next_ctx(NON_SECURE); + + next_smc_ctx = smc_get_next_ctx(); + memset(next_smc_ctx, 0, sizeof(smc_ctx_t)); + + copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)), + next_smc_ctx); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/sp_min_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/sp_min_private.h new file mode 100644 index 0000000..0042f40 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/sp_min/sp_min_private.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SP_MIN_H__ +#define __SP_MIN_H__ + +void sp_min_warm_entrypoint(void); +void sp_min_main(void); +void sp_min_warm_boot(void); + +#endif /* __SP_MIN_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S new file mode 100644 index 0000000..453d2c1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/aarch64/tsp_entrypoint.S @@ -0,0 +1,443 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "../tsp_private.h" + + + .globl tsp_entrypoint + .globl tsp_vector_table + + + + /* --------------------------------------------- + * Populate the params in x0-x7 from the pointer + * to the smc args structure in x0. + * --------------------------------------------- + */ + .macro restore_args_call_smc + ldp x6, x7, [x0, #TSP_ARG6] + ldp x4, x5, [x0, #TSP_ARG4] + ldp x2, x3, [x0, #TSP_ARG2] + ldp x0, x1, [x0, #TSP_ARG0] + smc #0 + .endm + + .macro save_eret_context reg1 reg2 + mrs \reg1, elr_el1 + mrs \reg2, spsr_el1 + stp \reg1, \reg2, [sp, #-0x10]! + stp x30, x18, [sp, #-0x10]! + .endm + + .macro restore_eret_context reg1 reg2 + ldp x30, x18, [sp], #0x10 + ldp \reg1, \reg2, [sp], #0x10 + msr elr_el1, \reg1 + msr spsr_el1, \reg2 + .endm + + .section .text, "ax" + .align 3 + +func tsp_entrypoint + + /* --------------------------------------------- + * Set the exception vector to something sane. + * --------------------------------------------- + */ + adr x0, tsp_exceptions + msr vbar_el1, x0 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT + + /* --------------------------------------------- + * Enable the instruction cache, stack pointer + * and data access alignment checks + * --------------------------------------------- + */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el1 + orr x0, x0, x1 + msr sctlr_el1, x0 + isb + + /* --------------------------------------------- + * Invalidate the RW memory used by the BL32 + * image. This includes the data and NOBITS + * sections. This is done to safeguard against + * possible corruption of this memory by dirty + * cache lines in a system cache as a result of + * use by an earlier boot loader stage. + * --------------------------------------------- + */ + adr x0, __RW_START__ + adr x1, __RW_END__ + sub x1, x1, x0 + bl inv_dcache_range + + /* --------------------------------------------- + * Zero out NOBITS sections. There are 2 of them: + * - the .bss section; + * - the coherent memory section. + * --------------------------------------------- + */ + ldr x0, =__BSS_START__ + ldr x1, =__BSS_SIZE__ + bl zeromem16 + +#if USE_COHERENT_MEM + ldr x0, =__COHERENT_RAM_START__ + ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ + bl zeromem16 +#endif + + /* -------------------------------------------- + * Allocate a stack whose memory will be marked + * as Normal-IS-WBWA when the MMU is enabled. + * There is no risk of reading stale stack + * memory after enabling the MMU as only the + * primary cpu is running at the moment. + * -------------------------------------------- + */ + bl plat_set_my_stack + + /* --------------------------------------------- + * Perform early platform setup & platform + * specific early arch. setup e.g. mmu setup + * --------------------------------------------- + */ + bl tsp_early_platform_setup + bl tsp_plat_arch_setup + + /* --------------------------------------------- + * Jump to main function. + * --------------------------------------------- + */ + bl tsp_main + + /* --------------------------------------------- + * Tell TSPD that we are done initialising + * --------------------------------------------- + */ + mov x1, x0 + mov x0, #TSP_ENTRY_DONE + smc #0 + +tsp_entrypoint_panic: + b tsp_entrypoint_panic +endfunc tsp_entrypoint + + + /* ------------------------------------------- + * Table of entrypoint vectors provided to the + * TSPD for the various entrypoints + * ------------------------------------------- + */ +func tsp_vector_table + b tsp_std_smc_entry + b tsp_fast_smc_entry + b tsp_cpu_on_entry + b tsp_cpu_off_entry + b tsp_cpu_resume_entry + b tsp_cpu_suspend_entry + b tsp_sel1_intr_entry + b tsp_system_off_entry + b tsp_system_reset_entry +endfunc tsp_vector_table + + /*--------------------------------------------- + * This entrypoint is used by the TSPD when this + * cpu is to be turned off through a CPU_OFF + * psci call to ask the TSP to perform any + * bookeeping necessary. In the current + * implementation, the TSPD expects the TSP to + * re-initialise its state so nothing is done + * here except for acknowledging the request. + * --------------------------------------------- + */ +func tsp_cpu_off_entry + bl tsp_cpu_off_main + restore_args_call_smc +endfunc tsp_cpu_off_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD when the + * system is about to be switched off (through + * a SYSTEM_OFF psci call) to ask the TSP to + * perform any necessary bookkeeping. + * --------------------------------------------- + */ +func tsp_system_off_entry + bl tsp_system_off_main + restore_args_call_smc +endfunc tsp_system_off_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD when the + * system is about to be reset (through a + * SYSTEM_RESET psci call) to ask the TSP to + * perform any necessary bookkeeping. + * --------------------------------------------- + */ +func tsp_system_reset_entry + bl tsp_system_reset_main + restore_args_call_smc +endfunc tsp_system_reset_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD when this + * cpu is turned on using a CPU_ON psci call to + * ask the TSP to initialise itself i.e. setup + * the mmu, stacks etc. Minimal architectural + * state will be initialised by the TSPD when + * this function is entered i.e. Caches and MMU + * will be turned off, the execution state + * will be aarch64 and exceptions masked. + * --------------------------------------------- + */ +func tsp_cpu_on_entry + /* --------------------------------------------- + * Set the exception vector to something sane. + * --------------------------------------------- + */ + adr x0, tsp_exceptions + msr vbar_el1, x0 + isb + + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + /* --------------------------------------------- + * Enable the instruction cache, stack pointer + * and data access alignment checks + * --------------------------------------------- + */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el1 + orr x0, x0, x1 + msr sctlr_el1, x0 + isb + + /* -------------------------------------------- + * Give ourselves a stack whose memory will be + * marked as Normal-IS-WBWA when the MMU is + * enabled. + * -------------------------------------------- + */ + bl plat_set_my_stack + + /* -------------------------------------------- + * Enable the MMU with the DCache disabled. It + * is safe to use stacks allocated in normal + * memory as a result. All memory accesses are + * marked nGnRnE when the MMU is disabled. So + * all the stack writes will make it to memory. + * All memory accesses are marked Non-cacheable + * when the MMU is enabled but D$ is disabled. + * So used stack memory is guaranteed to be + * visible immediately after the MMU is enabled + * Enabling the DCache at the same time as the + * MMU can lead to speculatively fetched and + * possibly stale stack memory being read from + * other caches. This can lead to coherency + * issues. + * -------------------------------------------- + */ + mov x0, #DISABLE_DCACHE + bl bl32_plat_enable_mmu + + /* --------------------------------------------- + * Enable the Data cache now that the MMU has + * been enabled. The stack has been unwound. It + * will be written first before being read. This + * will invalidate any stale cache lines resi- + * -dent in other caches. We assume that + * interconnect coherency has been enabled for + * this cluster by EL3 firmware. + * --------------------------------------------- + */ + mrs x0, sctlr_el1 + orr x0, x0, #SCTLR_C_BIT + msr sctlr_el1, x0 + isb + + /* --------------------------------------------- + * Enter C runtime to perform any remaining + * book keeping + * --------------------------------------------- + */ + bl tsp_cpu_on_main + restore_args_call_smc + + /* Should never reach here */ +tsp_cpu_on_entry_panic: + b tsp_cpu_on_entry_panic +endfunc tsp_cpu_on_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD when this + * cpu is to be suspended through a CPU_SUSPEND + * psci call to ask the TSP to perform any + * bookeeping necessary. In the current + * implementation, the TSPD saves and restores + * the EL1 state. + * --------------------------------------------- + */ +func tsp_cpu_suspend_entry + bl tsp_cpu_suspend_main + restore_args_call_smc +endfunc tsp_cpu_suspend_entry + + /*------------------------------------------------- + * This entrypoint is used by the TSPD to pass + * control for `synchronously` handling a S-EL1 + * Interrupt which was triggered while executing + * in normal world. 'x0' contains a magic number + * which indicates this. TSPD expects control to + * be handed back at the end of interrupt + * processing. This is done through an SMC. + * The handover agreement is: + * + * 1. PSTATE.DAIF are set upon entry. 'x1' has + * the ELR_EL3 from the non-secure state. + * 2. TSP has to preserve the callee saved + * general purpose registers, SP_EL1/EL0 and + * LR. + * 3. TSP has to preserve the system and vfp + * registers (if applicable). + * 4. TSP can use 'x0-x18' to enable its C + * runtime. + * 5. TSP returns to TSPD using an SMC with + * 'x0' = TSP_HANDLED_S_EL1_INTR + * ------------------------------------------------ + */ +func tsp_sel1_intr_entry +#if DEBUG + mov_imm x2, TSP_HANDLE_SEL1_INTR_AND_RETURN + cmp x0, x2 + b.ne tsp_sel1_int_entry_panic +#endif + /*------------------------------------------------- + * Save any previous context needed to perform + * an exception return from S-EL1 e.g. context + * from a previous Non secure Interrupt. + * Update statistics and handle the S-EL1 + * interrupt before returning to the TSPD. + * IRQ/FIQs are not enabled since that will + * complicate the implementation. Execution + * will be transferred back to the normal world + * in any case. The handler can return 0 + * if the interrupt was handled or TSP_PREEMPTED + * if the expected interrupt was preempted + * by an interrupt that should be handled in EL3 + * e.g. Group 0 interrupt in GICv3. In both + * the cases switch to EL3 using SMC with id + * TSP_HANDLED_S_EL1_INTR. Any other return value + * from the handler will result in panic. + * ------------------------------------------------ + */ + save_eret_context x2 x3 + bl tsp_update_sync_sel1_intr_stats + bl tsp_common_int_handler + /* Check if the S-EL1 interrupt has been handled */ + cbnz x0, tsp_sel1_intr_check_preemption + b tsp_sel1_intr_return +tsp_sel1_intr_check_preemption: + /* Check if the S-EL1 interrupt has been preempted */ + mov_imm x1, TSP_PREEMPTED + cmp x0, x1 + b.ne tsp_sel1_int_entry_panic +tsp_sel1_intr_return: + mov_imm x0, TSP_HANDLED_S_EL1_INTR + restore_eret_context x2 x3 + smc #0 + + /* Should never reach here */ +tsp_sel1_int_entry_panic: + bl plat_panic_handler +endfunc tsp_sel1_intr_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD when this + * cpu resumes execution after an earlier + * CPU_SUSPEND psci call to ask the TSP to + * restore its saved context. In the current + * implementation, the TSPD saves and restores + * EL1 state so nothing is done here apart from + * acknowledging the request. + * --------------------------------------------- + */ +func tsp_cpu_resume_entry + bl tsp_cpu_resume_main + restore_args_call_smc + + /* Should never reach here */ + bl plat_panic_handler +endfunc tsp_cpu_resume_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD to ask + * the TSP to service a fast smc request. + * --------------------------------------------- + */ +func tsp_fast_smc_entry + bl tsp_smc_handler + restore_args_call_smc + + /* Should never reach here */ + bl plat_panic_handler +endfunc tsp_fast_smc_entry + + /*--------------------------------------------- + * This entrypoint is used by the TSPD to ask + * the TSP to service a std smc request. + * We will enable preemption during execution + * of tsp_smc_handler. + * --------------------------------------------- + */ +func tsp_std_smc_entry + msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT + bl tsp_smc_handler + msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT + restore_args_call_smc + + /* Should never reach here */ + bl plat_panic_handler +endfunc tsp_std_smc_entry diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/aarch64/tsp_exceptions.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/aarch64/tsp_exceptions.S new file mode 100644 index 0000000..20e40df --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/aarch64/tsp_exceptions.S @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + + /* ---------------------------------------------------- + * The caller-saved registers x0-x18 and LR are saved + * here. + * ---------------------------------------------------- + */ + +#define SCRATCH_REG_SIZE #(20 * 8) + + .macro save_caller_regs_and_lr + sub sp, sp, SCRATCH_REG_SIZE + stp x0, x1, [sp] + stp x2, x3, [sp, #0x10] + stp x4, x5, [sp, #0x20] + stp x6, x7, [sp, #0x30] + stp x8, x9, [sp, #0x40] + stp x10, x11, [sp, #0x50] + stp x12, x13, [sp, #0x60] + stp x14, x15, [sp, #0x70] + stp x16, x17, [sp, #0x80] + stp x18, x30, [sp, #0x90] + .endm + + .macro restore_caller_regs_and_lr + ldp x0, x1, [sp] + ldp x2, x3, [sp, #0x10] + ldp x4, x5, [sp, #0x20] + ldp x6, x7, [sp, #0x30] + ldp x8, x9, [sp, #0x40] + ldp x10, x11, [sp, #0x50] + ldp x12, x13, [sp, #0x60] + ldp x14, x15, [sp, #0x70] + ldp x16, x17, [sp, #0x80] + ldp x18, x30, [sp, #0x90] + add sp, sp, SCRATCH_REG_SIZE + .endm + + /* ---------------------------------------------------- + * Common TSP interrupt handling routine + * ---------------------------------------------------- + */ + .macro handle_tsp_interrupt label + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + save_caller_regs_and_lr + bl tsp_common_int_handler + cbz x0, interrupt_exit_\label + + /* + * This interrupt was not targetted to S-EL1 so send it to + * the monitor and wait for execution to resume. + */ + smc #0 +interrupt_exit_\label: + restore_caller_regs_and_lr + eret + .endm + + .globl tsp_exceptions + + /* ----------------------------------------------------- + * TSP exception handlers. + * ----------------------------------------------------- + */ +vector_base tsp_exceptions + /* ----------------------------------------------------- + * Current EL with _sp_el0 : 0x0 - 0x200. No exceptions + * are expected and treated as irrecoverable errors. + * ----------------------------------------------------- + */ +vector_entry sync_exception_sp_el0 + bl plat_panic_handler + check_vector_size sync_exception_sp_el0 + +vector_entry irq_sp_el0 + bl plat_panic_handler + check_vector_size irq_sp_el0 + +vector_entry fiq_sp_el0 + bl plat_panic_handler + check_vector_size fiq_sp_el0 + +vector_entry serror_sp_el0 + bl plat_panic_handler + check_vector_size serror_sp_el0 + + + /* ----------------------------------------------------- + * Current EL with SPx: 0x200 - 0x400. Only IRQs/FIQs + * are expected and handled + * ----------------------------------------------------- + */ +vector_entry sync_exception_sp_elx + bl plat_panic_handler + check_vector_size sync_exception_sp_elx + +vector_entry irq_sp_elx + handle_tsp_interrupt irq_sp_elx + check_vector_size irq_sp_elx + +vector_entry fiq_sp_elx + handle_tsp_interrupt fiq_sp_elx + check_vector_size fiq_sp_elx + +vector_entry serror_sp_elx + bl plat_panic_handler + check_vector_size serror_sp_elx + + + /* ----------------------------------------------------- + * Lower EL using AArch64 : 0x400 - 0x600. No exceptions + * are handled since TSP does not implement a lower EL + * ----------------------------------------------------- + */ +vector_entry sync_exception_aarch64 + bl plat_panic_handler + check_vector_size sync_exception_aarch64 + +vector_entry irq_aarch64 + bl plat_panic_handler + check_vector_size irq_aarch64 + +vector_entry fiq_aarch64 + bl plat_panic_handler + check_vector_size fiq_aarch64 + +vector_entry serror_aarch64 + bl plat_panic_handler + check_vector_size serror_aarch64 + + + /* ----------------------------------------------------- + * Lower EL using AArch32 : 0x600 - 0x800. No exceptions + * handled since the TSP does not implement a lower EL. + * ----------------------------------------------------- + */ +vector_entry sync_exception_aarch32 + bl plat_panic_handler + check_vector_size sync_exception_aarch32 + +vector_entry irq_aarch32 + bl plat_panic_handler + check_vector_size irq_aarch32 + +vector_entry fiq_aarch32 + bl plat_panic_handler + check_vector_size fiq_aarch32 + +vector_entry serror_aarch32 + bl plat_panic_handler + check_vector_size serror_aarch32 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/aarch64/tsp_request.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/aarch64/tsp_request.S new file mode 100644 index 0000000..e30acf6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/aarch64/tsp_request.S @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl tsp_get_magic + + +/* + * This function raises an SMC to retrieve arguments from secure + * monitor/dispatcher, saves the returned arguments the array received in x0, + * and then returns to the caller + */ +func tsp_get_magic + /* Save address to stack */ + stp x0, xzr, [sp, #-16]! + + /* Load arguments */ + ldr w0, _tsp_fid_get_magic + + /* Raise SMC */ + smc #0 + + /* Restore address from stack */ + ldp x4, xzr, [sp], #16 + + /* Store returned arguments to the array */ + stp x0, x1, [x4, #0] + + ret +endfunc tsp_get_magic + + .align 2 +_tsp_fid_get_magic: + .word TSP_GET_ARGS diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp.ld.S b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp.ld.S new file mode 100644 index 0000000..7e24f66 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp.ld.S @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) +OUTPUT_ARCH(PLATFORM_LINKER_ARCH) +ENTRY(tsp_entrypoint) + + +MEMORY { + RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE +} + + +SECTIONS +{ + . = BL32_BASE; + ASSERT(. == ALIGN(4096), + "BL32_BASE address is not aligned on a page boundary.") + +#if SEPARATE_CODE_AND_RODATA + .text . : { + __TEXT_START__ = .; + *tsp_entrypoint.o(.text*) + *(.text*) + *(.vectors) + . = NEXT(4096); + __TEXT_END__ = .; + } >RAM + + .rodata . : { + __RODATA_START__ = .; + *(.rodata*) + . = NEXT(4096); + __RODATA_END__ = .; + } >RAM +#else + ro . : { + __RO_START__ = .; + *tsp_entrypoint.o(.text*) + *(.text*) + *(.rodata*) + *(.vectors) + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as + * read-only, executable. No RW data from the next section must + * creep in. Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __RO_END__ = .; + } >RAM +#endif + + /* + * Define a linker symbol to mark start of the RW memory area for this + * image. + */ + __RW_START__ = . ; + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + +#ifdef TSP_PROGBITS_LIMIT + ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.") +#endif + + stacks (NOLOAD) : { + __STACKS_START__ = .; + *(tzfw_normal_stacks) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } >RAM + + /* + * The xlat_table section is for full, aligned page tables (4K). + * Removing them from .bss avoids forcing 4K alignment on + * the .bss section and eliminates the unecessary zero init + */ + xlat_table (NOLOAD) : { + *(xlat_table) + } >RAM + +#if USE_COHERENT_MEM + /* + * The base address of the coherent memory section must be page-aligned (4K) + * to guarantee that the coherent data are stored on their own pages and + * are not mixed with normal data. This is required to set up the correct + * memory attributes for the coherent data page tables. + */ + coherent_ram (NOLOAD) : ALIGN(4096) { + __COHERENT_RAM_START__ = .; + *(tzfw_coherent_mem) + __COHERENT_RAM_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked + * as device memory. No other unexpected data must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __COHERENT_RAM_END__ = .; + } >RAM +#endif + + /* + * Define a linker symbol to mark the end of the RW memory area for this + * image. + */ + __RW_END__ = .; + __BL32_END__ = .; + + __BSS_SIZE__ = SIZEOF(.bss); +#if USE_COHERENT_MEM + __COHERENT_RAM_UNALIGNED_SIZE__ = + __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; +#endif + + ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.") +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp.mk new file mode 100644 index 0000000..2f3391e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp.mk @@ -0,0 +1,60 @@ +# +# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +INCLUDES += -Iinclude/bl32/tsp + +BL32_SOURCES += bl32/tsp/tsp_main.c \ + bl32/tsp/aarch64/tsp_entrypoint.S \ + bl32/tsp/aarch64/tsp_exceptions.S \ + bl32/tsp/aarch64/tsp_request.S \ + bl32/tsp/tsp_interrupt.c \ + bl32/tsp/tsp_timer.c \ + common/aarch64/early_exceptions.S \ + lib/locks/exclusive/aarch64/spinlock.S + +BL32_LINKERFILE := bl32/tsp/tsp.ld.S + +# This flag determines if the TSPD initializes BL32 in tspd_init() (synchronous +# method) or configures BL31 to pass control to BL32 instead of BL33 +# (asynchronous method). +TSP_INIT_ASYNC := 0 + +$(eval $(call assert_boolean,TSP_INIT_ASYNC)) +$(eval $(call add_define,TSP_INIT_ASYNC)) + +# Include the platform-specific TSP Makefile +# If no platform-specific TSP Makefile exists, it means TSP is not supported +# on this platform. +TSP_PLAT_MAKEFILE := $(wildcard ${PLAT_DIR}/tsp/tsp-${PLAT}.mk) +ifeq (,${TSP_PLAT_MAKEFILE}) + $(error TSP is not supported on platform ${PLAT}) +else + include ${TSP_PLAT_MAKEFILE} +endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp_interrupt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp_interrupt.c new file mode 100644 index 0000000..7654d2e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp_interrupt.c @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "tsp_private.h" + +/******************************************************************************* + * This function updates the TSP statistics for S-EL1 interrupts handled + * synchronously i.e the ones that have been handed over by the TSPD. It also + * keeps count of the number of times control was passed back to the TSPD + * after handling the interrupt. In the future it will be possible that the + * TSPD hands over an S-EL1 interrupt to the TSP but does not expect it to + * return execution. This statistic will be useful to distinguish between these + * two models of synchronous S-EL1 interrupt handling. The 'elr_el3' parameter + * contains the address of the instruction in normal world where this S-EL1 + * interrupt was generated. + ******************************************************************************/ +void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3) +{ + uint32_t linear_id = plat_my_core_pos(); + + tsp_stats[linear_id].sync_sel1_intr_count++; + if (type == TSP_HANDLE_SEL1_INTR_AND_RETURN) + tsp_stats[linear_id].sync_sel1_intr_ret_count++; + +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + spin_lock(&console_lock); + VERBOSE("TSP: cpu 0x%lx sync s-el1 interrupt request from 0x%lx\n", + read_mpidr(), elr_el3); + VERBOSE("TSP: cpu 0x%lx: %d sync s-el1 interrupt requests," + " %d sync s-el1 interrupt returns\n", + read_mpidr(), + tsp_stats[linear_id].sync_sel1_intr_count, + tsp_stats[linear_id].sync_sel1_intr_ret_count); + spin_unlock(&console_lock); +#endif +} + +/****************************************************************************** + * This function is invoked when a non S-EL1 interrupt is received and causes + * the preemption of TSP. This function returns TSP_PREEMPTED and results + * in the control being handed over to EL3 for handling the interrupt. + *****************************************************************************/ +int32_t tsp_handle_preemption(void) +{ + uint32_t linear_id = plat_my_core_pos(); + + tsp_stats[linear_id].preempt_intr_count++; +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + spin_lock(&console_lock); + VERBOSE("TSP: cpu 0x%lx: %d preempt interrupt requests\n", + read_mpidr(), tsp_stats[linear_id].preempt_intr_count); + spin_unlock(&console_lock); +#endif + return TSP_PREEMPTED; +} + +/******************************************************************************* + * TSP interrupt handler is called as a part of both synchronous and + * asynchronous handling of TSP interrupts. Currently the physical timer + * interrupt is the only S-EL1 interrupt that this handler expects. It returns + * 0 upon successfully handling the expected interrupt and all other + * interrupts are treated as normal world or EL3 interrupts. + ******************************************************************************/ +int32_t tsp_common_int_handler(void) +{ + uint32_t linear_id = plat_my_core_pos(), id; + + /* + * Get the highest priority pending interrupt id and see if it is the + * secure physical generic timer interrupt in which case, handle it. + * Otherwise throw this interrupt at the EL3 firmware. + * + * There is a small time window between reading the highest priority + * pending interrupt and acknowledging it during which another + * interrupt of higher priority could become the highest pending + * interrupt. This is not expected to happen currently for TSP. + */ + id = plat_ic_get_pending_interrupt_id(); + + /* TSP can only handle the secure physical timer interrupt */ + if (id != TSP_IRQ_SEC_PHY_TIMER) + return tsp_handle_preemption(); + + /* + * Acknowledge and handle the secure timer interrupt. Also sanity check + * if it has been preempted by another interrupt through an assertion. + */ + id = plat_ic_acknowledge_interrupt(); + assert(id == TSP_IRQ_SEC_PHY_TIMER); + tsp_generic_timer_handler(); + plat_ic_end_of_interrupt(id); + + /* Update the statistics and print some messages */ + tsp_stats[linear_id].sel1_intr_count++; +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + spin_lock(&console_lock); + VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %d\n", + read_mpidr(), id); + VERBOSE("TSP: cpu 0x%lx: %d S-EL1 requests\n", + read_mpidr(), tsp_stats[linear_id].sel1_intr_count); + spin_unlock(&console_lock); +#endif + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp_main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp_main.c new file mode 100644 index 0000000..d03f7e2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp_main.c @@ -0,0 +1,418 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "tsp_private.h" + + +/******************************************************************************* + * Lock to control access to the console + ******************************************************************************/ +spinlock_t console_lock; + +/******************************************************************************* + * Per cpu data structure to populate parameters for an SMC in C code and use + * a pointer to this structure in assembler code to populate x0-x7 + ******************************************************************************/ +static tsp_args_t tsp_smc_args[PLATFORM_CORE_COUNT]; + +/******************************************************************************* + * Per cpu data structure to keep track of TSP activity + ******************************************************************************/ +work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; + +/******************************************************************************* + * The TSP memory footprint starts at address BL32_BASE and ends with the + * linker symbol __BL32_END__. Use these addresses to compute the TSP image + * size. + ******************************************************************************/ +#define BL32_TOTAL_LIMIT (unsigned long)(&__BL32_END__) +#define BL32_TOTAL_SIZE (BL32_TOTAL_LIMIT - (unsigned long) BL32_BASE) + +static tsp_args_t *set_smc_args(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id; + tsp_args_t *pcpu_smc_args; + + /* + * Return to Secure Monitor by raising an SMC. The results of the + * service are passed as an arguments to the SMC + */ + linear_id = plat_my_core_pos(); + pcpu_smc_args = &tsp_smc_args[linear_id]; + write_sp_arg(pcpu_smc_args, TSP_ARG0, arg0); + write_sp_arg(pcpu_smc_args, TSP_ARG1, arg1); + write_sp_arg(pcpu_smc_args, TSP_ARG2, arg2); + write_sp_arg(pcpu_smc_args, TSP_ARG3, arg3); + write_sp_arg(pcpu_smc_args, TSP_ARG4, arg4); + write_sp_arg(pcpu_smc_args, TSP_ARG5, arg5); + write_sp_arg(pcpu_smc_args, TSP_ARG6, arg6); + write_sp_arg(pcpu_smc_args, TSP_ARG7, arg7); + + return pcpu_smc_args; +} + +/******************************************************************************* + * TSP main entry point where it gets the opportunity to initialize its secure + * state/applications. Once the state is initialized, it must return to the + * SPD with a pointer to the 'tsp_vector_table' jump table. + ******************************************************************************/ +uint64_t tsp_main(void) +{ + NOTICE("TSP: %s\n", version_string); + NOTICE("TSP: %s\n", build_message); + INFO("TSP: Total memory base : 0x%lx\n", (unsigned long) BL32_BASE); + INFO("TSP: Total memory size : 0x%lx bytes\n", BL32_TOTAL_SIZE); + + uint32_t linear_id = plat_my_core_pos(); + + /* Initialize the platform */ + tsp_platform_setup(); + + /* Initialize secure/applications state here */ + tsp_generic_timer_start(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_on_count++; + +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_on_count); + spin_unlock(&console_lock); +#endif + return (uint64_t) &tsp_vector_table; +} + +/******************************************************************************* + * This function performs any remaining book keeping in the test secure payload + * after this cpu's architectural state has been setup in response to an earlier + * psci cpu_on request. + ******************************************************************************/ +tsp_args_t *tsp_cpu_on_main(void) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* Initialize secure/applications state here */ + tsp_generic_timer_start(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_on_count++; + +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); + INFO("TSP: cpu 0x%lx turned on\n", read_mpidr()); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_on_count); + spin_unlock(&console_lock); +#endif + /* Indicate to the SPD that we have completed turned ourselves on */ + return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * This function performs any remaining book keeping in the test secure payload + * before this cpu is turned off in response to a psci cpu_off request. + ******************************************************************************/ +tsp_args_t *tsp_cpu_off_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* + * This cpu is being turned off, so disable the timer to prevent the + * secure timer interrupt from interfering with power down. A pending + * interrupt will be lost but we do not care as we are turning off. + */ + tsp_generic_timer_stop(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_off_count++; + +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); + INFO("TSP: cpu 0x%lx off request\n", read_mpidr()); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_off_count); + spin_unlock(&console_lock); +#endif + + /* Indicate to the SPD that we have completed this request */ + return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * This function performs any book keeping in the test secure payload before + * this cpu's architectural state is saved in response to an earlier psci + * cpu_suspend request. + ******************************************************************************/ +tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* + * Save the time context and disable it to prevent the secure timer + * interrupt from interfering with wakeup from the suspend state. + */ + tsp_generic_timer_save(); + tsp_generic_timer_stop(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_suspend_count++; + +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_suspend_count); + spin_unlock(&console_lock); +#endif + + /* Indicate to the SPD that we have completed this request */ + return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * This function performs any book keeping in the test secure payload after this + * cpu's architectural state has been restored after wakeup from an earlier psci + * cpu_suspend request. + ******************************************************************************/ +tsp_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* Restore the generic timer context */ + tsp_generic_timer_restore(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + tsp_stats[linear_id].cpu_resume_count++; + +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); + INFO("TSP: cpu 0x%lx resumed. maximum off power level %ld\n", + read_mpidr(), max_off_pwrlvl); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n", + read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count, + tsp_stats[linear_id].cpu_suspend_count); + spin_unlock(&console_lock); +#endif + /* Indicate to the SPD that we have completed this request */ + return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * This function performs any remaining bookkeeping in the test secure payload + * before the system is switched off (in response to a psci SYSTEM_OFF request) + ******************************************************************************/ +tsp_args_t *tsp_system_off_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); + INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", read_mpidr()); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count); + spin_unlock(&console_lock); +#endif + + /* Indicate to the SPD that we have completed this request */ + return set_smc_args(TSP_SYSTEM_OFF_DONE, 0, 0, 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * This function performs any remaining bookkeeping in the test secure payload + * before the system is reset (in response to a psci SYSTEM_RESET request) + ******************************************************************************/ +tsp_args_t *tsp_system_reset_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint32_t linear_id = plat_my_core_pos(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + +#if LOG_LEVEL >= LOG_LEVEL_INFO + spin_lock(&console_lock); + INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", read_mpidr()); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count); + spin_unlock(&console_lock); +#endif + + /* Indicate to the SPD that we have completed this request */ + return set_smc_args(TSP_SYSTEM_RESET_DONE, 0, 0, 0, 0, 0, 0, 0); +} + +/******************************************************************************* + * TSP fast smc handler. The secure monitor jumps to this function by + * doing the ERET after populating X0-X7 registers. The arguments are received + * in the function arguments in order. Once the service is rendered, this + * function returns to Secure Monitor by raising SMC. + ******************************************************************************/ +tsp_args_t *tsp_smc_handler(uint64_t func, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7) +{ + uint64_t results[2]; + uint64_t service_args[2]; + uint32_t linear_id = plat_my_core_pos(); + + /* Update this cpu's statistics */ + tsp_stats[linear_id].smc_count++; + tsp_stats[linear_id].eret_count++; + + INFO("TSP: cpu 0x%lx received %s smc 0x%lx\n", read_mpidr(), + ((func >> 31) & 1) == 1 ? "fast" : "standard", + func); + INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(), + tsp_stats[linear_id].smc_count, + tsp_stats[linear_id].eret_count); + + /* Render secure services and obtain results here */ + results[0] = arg1; + results[1] = arg2; + + /* + * Request a service back from dispatcher/secure monitor. This call + * return and thereafter resume exectuion + */ + tsp_get_magic(service_args); + + /* Determine the function to perform based on the function ID */ + switch (TSP_BARE_FID(func)) { + case TSP_ADD: + results[0] += service_args[0]; + results[1] += service_args[1]; + break; + case TSP_SUB: + results[0] -= service_args[0]; + results[1] -= service_args[1]; + break; + case TSP_MUL: + results[0] *= service_args[0]; + results[1] *= service_args[1]; + break; + case TSP_DIV: + results[0] /= service_args[0] ? service_args[0] : 1; + results[1] /= service_args[1] ? service_args[1] : 1; + break; + default: + break; + } + + return set_smc_args(func, 0, + results[0], + results[1], + 0, 0, 0, 0); +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp_private.h new file mode 100644 index 0000000..e341cfd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp_private.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TSP_PRIVATE_H__ +#define __TSP_PRIVATE_H__ + +/* Definitions to help the assembler access the SMC/ERET args structure */ +#define TSP_ARGS_SIZE 0x40 +#define TSP_ARG0 0x0 +#define TSP_ARG1 0x8 +#define TSP_ARG2 0x10 +#define TSP_ARG3 0x18 +#define TSP_ARG4 0x20 +#define TSP_ARG5 0x28 +#define TSP_ARG6 0x30 +#define TSP_ARG7 0x38 +#define TSP_ARGS_END 0x40 + + +#ifndef __ASSEMBLY__ + +#include +#include /* For CACHE_WRITEBACK_GRANULE */ +#include +#include +#include + + +typedef struct work_statistics { + /* Number of s-el1 interrupts on this cpu */ + uint32_t sel1_intr_count; + /* Number of non s-el1 interrupts on this cpu which preempted TSP */ + uint32_t preempt_intr_count; + /* Number of sync s-el1 interrupts on this cpu */ + uint32_t sync_sel1_intr_count; + /* Number of s-el1 interrupts returns on this cpu */ + uint32_t sync_sel1_intr_ret_count; + uint32_t smc_count; /* Number of returns on this cpu */ + uint32_t eret_count; /* Number of entries on this cpu */ + uint32_t cpu_on_count; /* Number of cpu on requests */ + uint32_t cpu_off_count; /* Number of cpu off requests */ + uint32_t cpu_suspend_count; /* Number of cpu suspend requests */ + uint32_t cpu_resume_count; /* Number of cpu resume requests */ +} __aligned(CACHE_WRITEBACK_GRANULE) work_statistics_t; + +typedef struct tsp_args { + uint64_t _regs[TSP_ARGS_END >> 3]; +} __aligned(CACHE_WRITEBACK_GRANULE) tsp_args_t; + +/* Macros to access members of the above structure using their offsets */ +#define read_sp_arg(args, offset) ((args)->_regs[offset >> 3]) +#define write_sp_arg(args, offset, val) (((args)->_regs[offset >> 3]) \ + = val) +/* + * Ensure that the assembler's view of the size of the tsp_args is the + * same as the compilers + */ +CASSERT(TSP_ARGS_SIZE == sizeof(tsp_args_t), assert_sp_args_size_mismatch); + +void tsp_get_magic(uint64_t args[4]); + +tsp_args_t *tsp_cpu_resume_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); +tsp_args_t *tsp_cpu_on_main(void); +tsp_args_t *tsp_cpu_off_main(uint64_t arg0, + uint64_t arg1, + uint64_t arg2, + uint64_t arg3, + uint64_t arg4, + uint64_t arg5, + uint64_t arg6, + uint64_t arg7); + +/* Generic Timer functions */ +void tsp_generic_timer_start(void); +void tsp_generic_timer_handler(void); +void tsp_generic_timer_stop(void); +void tsp_generic_timer_save(void); +void tsp_generic_timer_restore(void); + +/* S-EL1 interrupt management functions */ +void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3); + + +/* Data structure to keep track of TSP statistics */ +extern spinlock_t console_lock; +extern work_statistics_t tsp_stats[PLATFORM_CORE_COUNT]; + +/* Vector table of jumps */ +extern tsp_vectors_t tsp_vector_table; + + +#endif /* __ASSEMBLY__ */ + +#endif /* __TSP_PRIVATE_H__ */ + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp_timer.c b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp_timer.c new file mode 100644 index 0000000..7ca8734 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/bl32/tsp/tsp_timer.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include "tsp_private.h" + +/******************************************************************************* + * Data structure to keep track of per-cpu secure generic timer context across + * power management operations. + ******************************************************************************/ +typedef struct timer_context { + uint64_t cval; + uint32_t ctl; +} timer_context_t; + +static timer_context_t pcpu_timer_context[PLATFORM_CORE_COUNT]; + +/******************************************************************************* + * This function initializes the generic timer to fire every 0.5 second + ******************************************************************************/ +void tsp_generic_timer_start(void) +{ + uint64_t cval; + uint32_t ctl = 0; + + /* The timer will fire every 0.5 second */ + cval = read_cntpct_el0() + (read_cntfrq_el0() >> 1); + write_cntps_cval_el1(cval); + + /* Enable the secure physical timer */ + set_cntp_ctl_enable(ctl); + write_cntps_ctl_el1(ctl); +} + +/******************************************************************************* + * This function deasserts the timer interrupt and sets it up again + ******************************************************************************/ +void tsp_generic_timer_handler(void) +{ + /* Ensure that the timer did assert the interrupt */ + assert(get_cntp_ctl_istatus(read_cntps_ctl_el1())); + + /* + * Disable the timer and reprogram it. The barriers ensure that there is + * no reordering of instructions around the reprogramming code. + */ + isb(); + write_cntps_ctl_el1(0); + tsp_generic_timer_start(); + isb(); +} + +/******************************************************************************* + * This function deasserts the timer interrupt prior to cpu power down + ******************************************************************************/ +void tsp_generic_timer_stop(void) +{ + /* Disable the timer */ + write_cntps_ctl_el1(0); +} + +/******************************************************************************* + * This function saves the timer context prior to cpu suspension + ******************************************************************************/ +void tsp_generic_timer_save(void) +{ + uint32_t linear_id = plat_my_core_pos(); + + pcpu_timer_context[linear_id].cval = read_cntps_cval_el1(); + pcpu_timer_context[linear_id].ctl = read_cntps_ctl_el1(); + flush_dcache_range((uint64_t) &pcpu_timer_context[linear_id], + sizeof(pcpu_timer_context[linear_id])); +} + +/******************************************************************************* + * This function restores the timer context post cpu resummption + ******************************************************************************/ +void tsp_generic_timer_restore(void) +{ + uint32_t linear_id = plat_my_core_pos(); + + write_cntps_cval_el1(pcpu_timer_context[linear_id].cval); + write_cntps_ctl_el1(pcpu_timer_context[linear_id].ctl); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/common/aarch32/debug.S b/IPL/SDK/v3m/src/arm-trusted-firmware/common/aarch32/debug.S new file mode 100644 index 0000000..6be6951 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/common/aarch32/debug.S @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl do_panic + .globl report_exception + + /*********************************************************** + * The common implementation of do_panic for all BL stages + ***********************************************************/ +func do_panic + b plat_panic_handler +endfunc do_panic + + /*********************************************************** + * This function is called from the vector table for + * unhandled exceptions. It reads the current mode and + * passes it to platform. + ***********************************************************/ +func report_exception + mrs r0, cpsr + and r0, #MODE32_MASK + bl plat_report_exception + bl plat_panic_handler +endfunc report_exception diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/common/aarch64/debug.S b/IPL/SDK/v3m/src/arm-trusted-firmware/common/aarch64/debug.S new file mode 100644 index 0000000..d353879 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/common/aarch64/debug.S @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl asm_print_str + .globl asm_print_hex + .globl asm_assert + .globl do_panic + +/* Since the max decimal input number is 65536 */ +#define MAX_DEC_DIVISOR 10000 +/* The offset to add to get ascii for numerals '0 - 9' */ +#define ASCII_OFFSET_NUM 0x30 + +#if ASM_ASSERTION +.section .rodata.assert_str, "aS" +assert_msg1: + .asciz "ASSERT: File " +assert_msg2: + .asciz " Line " + + /* + * This macro is intended to be used to print the + * line number in decimal. Used by asm_assert macro. + * The max number expected is 65536. + * In: x4 = the decimal to print. + * Clobber: x30, x0, x1, x2, x5, x6 + */ + .macro asm_print_line_dec + mov x6, #10 /* Divide by 10 after every loop iteration */ + mov x5, #MAX_DEC_DIVISOR +dec_print_loop: + udiv x0, x4, x5 /* Get the quotient */ + msub x4, x0, x5, x4 /* Find the remainder */ + add x0, x0, #ASCII_OFFSET_NUM /* Convert to ascii */ + bl plat_crash_console_putc + udiv x5, x5, x6 /* Reduce divisor */ + cbnz x5, dec_print_loop + .endm + + +/* --------------------------------------------------------------------------- + * Assertion support in assembly. + * The below function helps to support assertions in assembly where we do not + * have a C runtime stack. Arguments to the function are : + * x0 - File name + * x1 - Line no + * Clobber list : x30, x0, x1, x2, x3, x4, x5, x6. + * --------------------------------------------------------------------------- + */ +func asm_assert + mov x5, x0 + mov x6, x1 + /* Ensure the console is initialized */ + bl plat_crash_console_init + /* Check if the console is initialized */ + cbz x0, _assert_loop + /* The console is initialized */ + adr x4, assert_msg1 + bl asm_print_str + mov x4, x5 + bl asm_print_str + adr x4, assert_msg2 + bl asm_print_str + /* Check if line number higher than max permitted */ + tst x6, #~0xffff + b.ne _assert_loop + mov x4, x6 + asm_print_line_dec +_assert_loop: + b _assert_loop +endfunc asm_assert +#endif + +/* + * This function prints a string from address in x4. + * In: x4 = pointer to string. + * Clobber: x30, x0, x1, x2, x3 + */ +func asm_print_str + mov x3, x30 +1: + ldrb w0, [x4], #0x1 + cbz x0, 2f + bl plat_crash_console_putc + b 1b +2: + ret x3 +endfunc asm_print_str + +/* + * This function prints a hexadecimal number in x4. + * In: x4 = the hexadecimal to print. + * Clobber: x30, x0 - x3, x5 + */ +func asm_print_hex + mov x3, x30 + mov x5, #64 /* No of bits to convert to ascii */ +1: + sub x5, x5, #4 + lsrv x0, x4, x5 + and x0, x0, #0xf + cmp x0, #0xA + b.lo 2f + /* Add by 0x27 in addition to ASCII_OFFSET_NUM + * to get ascii for characters 'a - f'. + */ + add x0, x0, #0x27 +2: + add x0, x0, #ASCII_OFFSET_NUM + bl plat_crash_console_putc + cbnz x5, 1b + ret x3 +endfunc asm_print_hex + + /*********************************************************** + * The common implementation of do_panic for all BL stages + ***********************************************************/ + +.section .rodata.panic_str, "aS" + panic_msg: .asciz "PANIC at PC : 0x" + +/* --------------------------------------------------------------------------- + * do_panic assumes that it is invoked from a C Runtime Environment ie a + * valid stack exists. This call will not return. + * Clobber list : if CRASH_REPORTING is not enabled then x30, x0 - x6 + * --------------------------------------------------------------------------- + */ + +/* This is for the non el3 BL stages to compile through */ + .weak el3_panic + +func do_panic +#if CRASH_REPORTING + str x0, [sp, #-0x10]! + mrs x0, currentel + ubfx x0, x0, #2, #2 + cmp x0, #0x3 + ldr x0, [sp], #0x10 + b.eq el3_panic +#endif + +panic_common: +/* + * el3_panic will be redefined by the BL31 + * crash reporting mechanism (if enabled) + */ +el3_panic: + mov x6, x30 + bl plat_crash_console_init + /* Check if the console is initialized */ + cbz x0, _panic_handler + /* The console is initialized */ + adr x4, panic_msg + bl asm_print_str + mov x4, x6 + /* The panic location is lr -4 */ + sub x4, x4, #4 + bl asm_print_hex + +_panic_handler: + /* Pass to plat_panic_handler the address from where el3_panic was + * called, not the address of the call from el3_panic. */ + mov x30,x6 + b plat_panic_handler +endfunc do_panic diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/common/aarch64/early_exceptions.S b/IPL/SDK/v3m/src/arm-trusted-firmware/common/aarch64/early_exceptions.S new file mode 100644 index 0000000..ad5b4d8 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/common/aarch64/early_exceptions.S @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/* ----------------------------------------------------------------------------- + * Very simple stackless exception handlers used by BL2 and BL31 stages. + * BL31 uses them before stacks are setup. BL2 uses them throughout. + * ----------------------------------------------------------------------------- + */ + .globl early_exceptions + +vector_base early_exceptions + + /* ----------------------------------------------------- + * Current EL with SP0 : 0x0 - 0x200 + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionSP0 + mov x0, #SYNC_EXCEPTION_SP_EL0 + bl plat_report_exception + bl plat_panic_handler + check_vector_size SynchronousExceptionSP0 + +vector_entry IrqSP0 + mov x0, #IRQ_SP_EL0 + bl plat_report_exception + bl plat_panic_handler + check_vector_size IrqSP0 + +vector_entry FiqSP0 + mov x0, #FIQ_SP_EL0 + bl plat_report_exception + bl plat_panic_handler + check_vector_size FiqSP0 + +vector_entry SErrorSP0 + mov x0, #SERROR_SP_EL0 + bl plat_report_exception + bl plat_panic_handler + check_vector_size SErrorSP0 + + /* ----------------------------------------------------- + * Current EL with SPx: 0x200 - 0x400 + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionSPx + mov x0, #SYNC_EXCEPTION_SP_ELX + bl plat_report_exception + bl plat_panic_handler + check_vector_size SynchronousExceptionSPx + +vector_entry IrqSPx + mov x0, #IRQ_SP_ELX + bl plat_report_exception + bl plat_panic_handler + check_vector_size IrqSPx + +vector_entry FiqSPx + mov x0, #FIQ_SP_ELX + bl plat_report_exception + bl plat_panic_handler + check_vector_size FiqSPx + +vector_entry SErrorSPx + mov x0, #SERROR_SP_ELX + bl plat_report_exception + bl plat_panic_handler + check_vector_size SErrorSPx + + /* ----------------------------------------------------- + * Lower EL using AArch64 : 0x400 - 0x600 + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionA64 + mov x0, #SYNC_EXCEPTION_AARCH64 + bl plat_report_exception + bl plat_panic_handler + check_vector_size SynchronousExceptionA64 + +vector_entry IrqA64 + mov x0, #IRQ_AARCH64 + bl plat_report_exception + bl plat_panic_handler + check_vector_size IrqA64 + +vector_entry FiqA64 + mov x0, #FIQ_AARCH64 + bl plat_report_exception + bl plat_panic_handler + check_vector_size FiqA64 + +vector_entry SErrorA64 + mov x0, #SERROR_AARCH64 + bl plat_report_exception + bl plat_panic_handler + check_vector_size SErrorA64 + + /* ----------------------------------------------------- + * Lower EL using AArch32 : 0x600 - 0x800 + * ----------------------------------------------------- + */ +vector_entry SynchronousExceptionA32 + mov x0, #SYNC_EXCEPTION_AARCH32 + bl plat_report_exception + bl plat_panic_handler + check_vector_size SynchronousExceptionA32 + +vector_entry IrqA32 + mov x0, #IRQ_AARCH32 + bl plat_report_exception + bl plat_panic_handler + check_vector_size IrqA32 + +vector_entry FiqA32 + mov x0, #FIQ_AARCH32 + bl plat_report_exception + bl plat_panic_handler + check_vector_size FiqA32 + +vector_entry SErrorA32 + mov x0, #SERROR_AARCH32 + bl plat_report_exception + bl plat_panic_handler + check_vector_size SErrorA32 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/common/bl_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/common/bl_common.c new file mode 100644 index 0000000..193e972 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/common/bl_common.c @@ -0,0 +1,581 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +uintptr_t page_align(uintptr_t value, unsigned dir) +{ + /* Round up the limit to the next page boundary */ + if (value & (PAGE_SIZE - 1)) { + value &= ~(PAGE_SIZE - 1); + if (dir == UP) + value += PAGE_SIZE; + } + + return value; +} + +#if !LOAD_IMAGE_V2 +/****************************************************************************** + * Determine whether the memory region delimited by 'addr' and 'size' is free, + * given the extents of free memory. + * Return 1 if it is free, 0 if it is not free or if the input values are + * invalid. + *****************************************************************************/ +static int is_mem_free(uintptr_t free_base, size_t free_size, + uintptr_t addr, size_t size) +{ + uintptr_t free_end, requested_end; + + /* + * Handle corner cases first. + * + * The order of the 2 tests is important, because if there's no space + * left (i.e. free_size == 0) but we don't ask for any memory + * (i.e. size == 0) then we should report that the memory is free. + */ + if (size == 0) + return 1; /* A zero-byte region is always free */ + if (free_size == 0) + return 0; + + /* + * Check that the end addresses don't overflow. + * If they do, consider that this memory region is not free, as this + * is an invalid scenario. + */ + if (check_uptr_overflow(free_base, free_size - 1)) + return 0; + free_end = free_base + (free_size - 1); + + if (check_uptr_overflow(addr, size - 1)) + return 0; + requested_end = addr + (size - 1); + + /* + * Finally, check that the requested memory region lies within the free + * region. + */ + return (addr >= free_base) && (requested_end <= free_end); +} + +/****************************************************************************** + * Inside a given memory region, determine whether a sub-region of memory is + * closer from the top or the bottom of the encompassing region. Return the + * size of the smallest chunk of free memory surrounding the sub-region in + * 'small_chunk_size'. + *****************************************************************************/ +static unsigned int choose_mem_pos(uintptr_t mem_start, uintptr_t mem_end, + uintptr_t submem_start, uintptr_t submem_end, + size_t *small_chunk_size) +{ + size_t top_chunk_size, bottom_chunk_size; + + assert(mem_start <= submem_start); + assert(submem_start <= submem_end); + assert(submem_end <= mem_end); + assert(small_chunk_size != NULL); + + top_chunk_size = mem_end - submem_end; + bottom_chunk_size = submem_start - mem_start; + + if (top_chunk_size < bottom_chunk_size) { + *small_chunk_size = top_chunk_size; + return TOP; + } else { + *small_chunk_size = bottom_chunk_size; + return BOTTOM; + } +} + +/****************************************************************************** + * Reserve the memory region delimited by 'addr' and 'size'. The extents of free + * memory are passed in 'free_base' and 'free_size' and they will be updated to + * reflect the memory usage. + * The caller must ensure the memory to reserve is free and that the addresses + * and sizes passed in arguments are sane. + *****************************************************************************/ +void reserve_mem(uintptr_t *free_base, size_t *free_size, + uintptr_t addr, size_t size) +{ + size_t discard_size; + size_t reserved_size; + unsigned int pos; + + assert(free_base != NULL); + assert(free_size != NULL); + assert(is_mem_free(*free_base, *free_size, addr, size)); + + if (size == 0) { + WARN("Nothing to allocate, requested size is zero\n"); + return; + } + + pos = choose_mem_pos(*free_base, *free_base + (*free_size - 1), + addr, addr + (size - 1), + &discard_size); + + reserved_size = size + discard_size; + *free_size -= reserved_size; + + if (pos == BOTTOM) + *free_base = addr + size; + + VERBOSE("Reserved 0x%zx bytes (discarded 0x%zx bytes %s)\n", + reserved_size, discard_size, + pos == TOP ? "above" : "below"); +} + +static void dump_load_info(uintptr_t image_load_addr, + size_t image_size, + const meminfo_t *mem_layout) +{ + INFO("Trying to load image at address %p, size = 0x%zx\n", + (void *)image_load_addr, image_size); + INFO("Current memory layout:\n"); + INFO(" total region = [base = %p, size = 0x%zx]\n", + (void *) mem_layout->total_base, mem_layout->total_size); + INFO(" free region = [base = %p, size = 0x%zx]\n", + (void *) mem_layout->free_base, mem_layout->free_size); +} +#endif /* LOAD_IMAGE_V2 */ + +/* Generic function to return the size of an image */ +size_t image_size(unsigned int image_id) +{ + uintptr_t dev_handle; + uintptr_t image_handle; + uintptr_t image_spec; + size_t image_size = 0; + int io_result; + + /* Obtain a reference to the image by querying the platform layer */ + io_result = plat_get_image_source(image_id, &dev_handle, &image_spec); + if (io_result != 0) { + WARN("Failed to obtain reference to image id=%u (%i)\n", + image_id, io_result); + return 0; + } + + /* Attempt to access the image */ + io_result = io_open(dev_handle, image_spec, &image_handle); + if (io_result != 0) { + WARN("Failed to access image id=%u (%i)\n", + image_id, io_result); + return 0; + } + + /* Find the size of the image */ + io_result = io_size(image_handle, &image_size); + if ((io_result != 0) || (image_size == 0)) { + WARN("Failed to determine the size of the image id=%u (%i)\n", + image_id, io_result); + } + io_result = io_close(image_handle); + /* Ignore improbable/unrecoverable error in 'close' */ + + /* TODO: Consider maintaining open device connection from this + * bootloader stage + */ + io_result = io_dev_close(dev_handle); + /* Ignore improbable/unrecoverable error in 'dev_close' */ + + return image_size; +} + +#if LOAD_IMAGE_V2 + +/******************************************************************************* + * Generic function to load an image at a specific address given + * an image ID and extents of free memory. + * + * If the load is successful then the image information is updated. + * + * Returns 0 on success, a negative error code otherwise. + ******************************************************************************/ +int load_image(unsigned int image_id, image_info_t *image_data) +{ + uintptr_t dev_handle; + uintptr_t image_handle; + uintptr_t image_spec; + uintptr_t image_base; + size_t image_size; + size_t bytes_read; + int io_result; + + assert(image_data != NULL); + assert(image_data->h.version >= VERSION_2); + + image_base = image_data->image_base; + + /* Obtain a reference to the image by querying the platform layer */ + io_result = plat_get_image_source(image_id, &dev_handle, &image_spec); + if (io_result != 0) { + WARN("Failed to obtain reference to image id=%u (%i)\n", + image_id, io_result); + return io_result; + } + + /* Attempt to access the image */ + io_result = io_open(dev_handle, image_spec, &image_handle); + if (io_result != 0) { + WARN("Failed to access image id=%u (%i)\n", + image_id, io_result); + return io_result; + } + + INFO("Loading image id=%u at address %p\n", image_id, + (void *) image_base); + + /* Find the size of the image */ + io_result = io_size(image_handle, &image_size); + if ((io_result != 0) || (image_size == 0)) { + WARN("Failed to determine the size of the image id=%u (%i)\n", + image_id, io_result); + goto exit; + } + + /* Check that the image size to load is within limit */ + if (image_size > image_data->image_max_size) { + WARN("Image id=%u size out of bounds\n", image_id); + io_result = -EFBIG; + goto exit; + } + + image_data->image_size = image_size; + + /* We have enough space so load the image now */ + /* TODO: Consider whether to try to recover/retry a partially successful read */ + io_result = io_read(image_handle, image_base, image_size, &bytes_read); + if ((io_result != 0) || (bytes_read < image_size)) { + WARN("Failed to load image id=%u (%i)\n", image_id, io_result); + goto exit; + } + +#if !TRUSTED_BOARD_BOOT + /* + * File has been successfully loaded. + * Flush the image to main memory so that it can be executed later by + * any CPU, regardless of cache and MMU state. + * When TBB is enabled the image is flushed later, after image + * authentication. + */ + flush_dcache_range(image_base, image_size); +#endif /* TRUSTED_BOARD_BOOT */ + + INFO("Image id=%u loaded: %p - %p\n", image_id, (void *) image_base, + (void *) (image_base + image_size)); + +exit: + io_close(image_handle); + /* Ignore improbable/unrecoverable error in 'close' */ + + /* TODO: Consider maintaining open device connection from this bootloader stage */ + io_dev_close(dev_handle); + /* Ignore improbable/unrecoverable error in 'dev_close' */ + + return io_result; +} + +/******************************************************************************* + * Generic function to load and authenticate an image. The image is actually + * loaded by calling the 'load_image()' function. Therefore, it returns the + * same error codes if the loading operation failed, or -EAUTH if the + * authentication failed. In addition, this function uses recursion to + * authenticate the parent images up to the root of trust. + ******************************************************************************/ +int load_auth_image(unsigned int image_id, image_info_t *image_data) +{ + int rc; + +#if TRUSTED_BOARD_BOOT + unsigned int parent_id; + + /* Use recursion to authenticate parent images */ + rc = auth_mod_get_parent_id(image_id, &parent_id); + if (rc == 0) { + rc = load_auth_image(parent_id, image_data); + if (rc != 0) { + return rc; + } + } +#endif /* TRUSTED_BOARD_BOOT */ + + /* Load the image */ + rc = load_image(image_id, image_data); + if (rc != 0) { + return rc; + } + +#if TRUSTED_BOARD_BOOT + /* Authenticate it */ + rc = auth_mod_verify_img(image_id, + (void *)image_data->image_base, + image_data->image_size); + if (rc != 0) { + memset((void *)image_data->image_base, 0x00, + image_data->image_size); + flush_dcache_range(image_data->image_base, + image_data->image_size); + return -EAUTH; + } + + /* + * File has been successfully loaded and authenticated. + * Flush the image to main memory so that it can be executed later by + * any CPU, regardless of cache and MMU state. + */ + flush_dcache_range(image_data->image_base, image_data->image_size); +#endif /* TRUSTED_BOARD_BOOT */ + + return 0; +} + +#else /* LOAD_IMAGE_V2 */ + +/******************************************************************************* + * Generic function to load an image at a specific address given an image ID and + * extents of free memory. + * + * If the load is successful then the image information is updated. + * + * If the entry_point_info argument is not NULL then this function also updates: + * - the memory layout to mark the memory as reserved; + * - the entry point information. + * + * The caller might pass a NULL pointer for the entry point if they are not + * interested in this information. This is typically the case for non-executable + * images (e.g. certificates) and executable images that won't ever be executed + * on the application processor (e.g. additional microcontroller firmware). + * + * Returns 0 on success, a negative error code otherwise. + ******************************************************************************/ +int load_image(meminfo_t *mem_layout, + unsigned int image_id, + uintptr_t image_base, + image_info_t *image_data, + entry_point_info_t *entry_point_info) +{ + uintptr_t dev_handle; + uintptr_t image_handle; + uintptr_t image_spec; + size_t image_size; + size_t bytes_read; + int io_result; + + assert(mem_layout != NULL); + assert(image_data != NULL); + assert(image_data->h.version == VERSION_1); + + /* Obtain a reference to the image by querying the platform layer */ + io_result = plat_get_image_source(image_id, &dev_handle, &image_spec); + if (io_result != 0) { + WARN("Failed to obtain reference to image id=%u (%i)\n", + image_id, io_result); + return io_result; + } + + /* Attempt to access the image */ + io_result = io_open(dev_handle, image_spec, &image_handle); + if (io_result != 0) { + WARN("Failed to access image id=%u (%i)\n", + image_id, io_result); + return io_result; + } + + INFO("Loading image id=%u at address %p\n", image_id, + (void *) image_base); + + /* Find the size of the image */ + io_result = io_size(image_handle, &image_size); + if ((io_result != 0) || (image_size == 0)) { + WARN("Failed to determine the size of the image id=%u (%i)\n", + image_id, io_result); + goto exit; + } + + /* Check that the memory where the image will be loaded is free */ + if (!is_mem_free(mem_layout->free_base, mem_layout->free_size, + image_base, image_size)) { + WARN("Failed to reserve region [base = %p, size = 0x%zx]\n", + (void *) image_base, image_size); + dump_load_info(image_base, image_size, mem_layout); + io_result = -ENOMEM; + goto exit; + } + + /* We have enough space so load the image now */ + /* TODO: Consider whether to try to recover/retry a partially successful read */ + io_result = io_read(image_handle, image_base, image_size, &bytes_read); + if ((io_result != 0) || (bytes_read < image_size)) { + WARN("Failed to load image id=%u (%i)\n", image_id, io_result); + goto exit; + } + + image_data->image_base = image_base; + image_data->image_size = image_size; + + /* + * Update the memory usage info. + * This is done after the actual loading so that it is not updated when + * the load is unsuccessful. + * If the caller does not provide an entry point, bypass the memory + * reservation. + */ + if (entry_point_info != NULL) { + reserve_mem(&mem_layout->free_base, &mem_layout->free_size, + image_base, image_size); + entry_point_info->pc = image_base; + } else { + INFO("Skip reserving region [base = %p, size = 0x%zx]\n", + (void *) image_base, image_size); + } + +#if !TRUSTED_BOARD_BOOT + /* + * File has been successfully loaded. + * Flush the image to main memory so that it can be executed later by + * any CPU, regardless of cache and MMU state. + * When TBB is enabled the image is flushed later, after image + * authentication. + */ + flush_dcache_range(image_base, image_size); +#endif /* TRUSTED_BOARD_BOOT */ + + INFO("Image id=%u loaded at address %p, size = 0x%zx\n", image_id, + (void *) image_base, image_size); + +exit: + io_close(image_handle); + /* Ignore improbable/unrecoverable error in 'close' */ + + /* TODO: Consider maintaining open device connection from this bootloader stage */ + io_dev_close(dev_handle); + /* Ignore improbable/unrecoverable error in 'dev_close' */ + + return io_result; +} + +/******************************************************************************* + * Generic function to load and authenticate an image. The image is actually + * loaded by calling the 'load_image()' function. Therefore, it returns the + * same error codes if the loading operation failed, or -EAUTH if the + * authentication failed. In addition, this function uses recursion to + * authenticate the parent images up to the root of trust. + ******************************************************************************/ +int load_auth_image(meminfo_t *mem_layout, + unsigned int image_id, + uintptr_t image_base, + image_info_t *image_data, + entry_point_info_t *entry_point_info) +{ + int rc; + +#if TRUSTED_BOARD_BOOT + unsigned int parent_id; + + /* Use recursion to authenticate parent images */ + rc = auth_mod_get_parent_id(image_id, &parent_id); + if (rc == 0) { + rc = load_auth_image(mem_layout, parent_id, image_base, + image_data, NULL); + if (rc != 0) { + return rc; + } + } +#endif /* TRUSTED_BOARD_BOOT */ + + /* Load the image */ + rc = load_image(mem_layout, image_id, image_base, image_data, + entry_point_info); + if (rc != 0) { + return rc; + } + +#if TRUSTED_BOARD_BOOT + /* Authenticate it */ + rc = auth_mod_verify_img(image_id, + (void *)image_data->image_base, + image_data->image_size); + if (rc != 0) { + memset((void *)image_data->image_base, 0x00, + image_data->image_size); + flush_dcache_range(image_data->image_base, + image_data->image_size); + return -EAUTH; + } + /* + * File has been successfully loaded and authenticated. + * Flush the image to main memory so that it can be executed later by + * any CPU, regardless of cache and MMU state. + */ + flush_dcache_range(image_data->image_base, image_data->image_size); +#endif /* TRUSTED_BOARD_BOOT */ + + return 0; +} + +#endif /* LOAD_IMAGE_V2 */ + +/******************************************************************************* + * Print the content of an entry_point_info_t structure. + ******************************************************************************/ +void print_entry_point_info(const entry_point_info_t *ep_info) +{ + INFO("Entry point address = %p\n", (void *)ep_info->pc); + INFO("SPSR = 0x%x\n", ep_info->spsr); + +#define PRINT_IMAGE_ARG(n) \ + VERBOSE("Argument #" #n " = 0x%llx\n", \ + (unsigned long long) ep_info->args.arg##n) + + PRINT_IMAGE_ARG(0); + PRINT_IMAGE_ARG(1); + PRINT_IMAGE_ARG(2); + PRINT_IMAGE_ARG(3); +#ifndef AARCH32 + PRINT_IMAGE_ARG(4); + PRINT_IMAGE_ARG(5); + PRINT_IMAGE_ARG(6); + PRINT_IMAGE_ARG(7); +#endif +#undef PRINT_IMAGE_ARG +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/common/desc_image_load.c b/IPL/SDK/v3m/src/arm-trusted-firmware/common/desc_image_load.c new file mode 100644 index 0000000..a9762b7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/common/desc_image_load.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + +extern bl_mem_params_node_t *bl_mem_params_desc_ptr; +extern unsigned int bl_mem_params_desc_num; + +static bl_load_info_t bl_load_info; +static bl_params_t next_bl_params; + + +/******************************************************************************* + * This function flushes the data structures so that they are visible + * in memory for the next BL image. + ******************************************************************************/ +void flush_bl_params_desc(void) +{ + flush_dcache_range((unsigned long)bl_mem_params_desc_ptr, + sizeof(*bl_mem_params_desc_ptr) * bl_mem_params_desc_num); +} + +/******************************************************************************* + * This function returns the index for given image_id, within the + * image descriptor array provided by bl_image_info_descs_ptr, if the + * image is found else it returns -1. + ******************************************************************************/ +int get_bl_params_node_index(unsigned int image_id) +{ + int index; + assert(image_id != INVALID_IMAGE_ID); + + for (index = 0; index < bl_mem_params_desc_num; index++) { + if (bl_mem_params_desc_ptr[index].image_id == image_id) + return index; + } + + return -1; +} + +/******************************************************************************* + * This function returns the pointer to `bl_mem_params_node_t` object for + * given image_id, within the image descriptor array provided by + * bl_mem_params_desc_ptr, if the image is found else it returns NULL. + ******************************************************************************/ +bl_mem_params_node_t *get_bl_mem_params_node(unsigned int image_id) +{ + int index; + assert(image_id != INVALID_IMAGE_ID); + + index = get_bl_params_node_index(image_id); + if (index >= 0) + return &bl_mem_params_desc_ptr[index]; + else + return NULL; +} + +/******************************************************************************* + * This function creates the list of loadable images, by populating and + * linking each `bl_load_info_node_t` type node, using the internal array + * of image descriptor provided by bl_mem_params_desc_ptr. It also populates + * and returns `bl_load_info_t` type structure that contains head of the list + * of loadable images. + ******************************************************************************/ +bl_load_info_t *get_bl_load_info_from_mem_params_desc(void) +{ + int index = 0; + + /* If there is no image to start with, return NULL */ + if (!bl_mem_params_desc_num) + return NULL; + + /* Assign initial data structures */ + bl_load_info_node_t *bl_node_info = + &bl_mem_params_desc_ptr[index].load_node_mem; + bl_load_info.head = bl_node_info; + SET_PARAM_HEAD(&bl_load_info, PARAM_BL_LOAD_INFO, VERSION_2, 0); + + /* Go through the image descriptor array and create the list */ + for (; index < bl_mem_params_desc_num; index++) { + + /* Populate the image information */ + bl_node_info->image_id = bl_mem_params_desc_ptr[index].image_id; + bl_node_info->image_info = &bl_mem_params_desc_ptr[index].image_info; + + /* Link next image if present */ + if ((index + 1) < bl_mem_params_desc_num) { + /* Get the memory and link the next node */ + bl_node_info->next_load_info = + &bl_mem_params_desc_ptr[index + 1].load_node_mem; + bl_node_info = bl_node_info->next_load_info; + } + } + + return &bl_load_info; +} + +/******************************************************************************* + * This function creates the list of executable images, by populating and + * linking each `bl_params_node_t` type node, using the internal array of + * image descriptor provided by bl_mem_params_desc_ptr. It also populates + * and returns `bl_params_t` type structure that contains head of the list + * of executable images. + ******************************************************************************/ +bl_params_t *get_next_bl_params_from_mem_params_desc(void) +{ + int count; + unsigned int img_id = 0; + int link_index = 0; + bl_params_node_t *bl_current_exec_node = NULL; + bl_params_node_t *bl_last_exec_node = NULL; + bl_mem_params_node_t *desc_ptr; + + /* If there is no image to start with, return NULL */ + if (!bl_mem_params_desc_num) + return NULL; + + /* Get the list HEAD */ + for (count = 0; count < bl_mem_params_desc_num; count++) { + + desc_ptr = &bl_mem_params_desc_ptr[count]; + + if ((EP_GET_EXE(desc_ptr->ep_info.h.attr) == EXECUTABLE) && + (EP_GET_FIRST_EXE(desc_ptr->ep_info.h.attr) == EP_FIRST_EXE)) { + next_bl_params.head = &desc_ptr->params_node_mem; + link_index = count; + break; + } + } + + /* Make sure we have a HEAD node */ + assert(next_bl_params.head != NULL); + + /* Populate the HEAD information */ + SET_PARAM_HEAD(&next_bl_params, PARAM_BL_PARAMS, VERSION_2, 0); + + /* + * Go through the image descriptor array and create the list. + * This bounded loop is to make sure that we are not looping forever. + */ + for (count = 0 ; count < bl_mem_params_desc_num; count++) { + + desc_ptr = &bl_mem_params_desc_ptr[link_index]; + + /* Make sure the image is executable */ + assert(EP_GET_EXE(desc_ptr->ep_info.h.attr) == EXECUTABLE); + + /* Get the memory for current node */ + bl_current_exec_node = &desc_ptr->params_node_mem; + + /* Populate the image information */ + bl_current_exec_node->image_id = desc_ptr->image_id; + bl_current_exec_node->image_info = &desc_ptr->image_info; + bl_current_exec_node->ep_info = &desc_ptr->ep_info; + + if (bl_last_exec_node) { + /* Assert if loop detected */ + assert(bl_last_exec_node->next_params_info == NULL); + + /* Link the previous node to the current one */ + bl_last_exec_node->next_params_info = bl_current_exec_node; + } + + /* Update the last node */ + bl_last_exec_node = bl_current_exec_node; + + /* If no next hand-off image then break out */ + img_id = desc_ptr->next_handoff_image_id; + if (img_id == INVALID_IMAGE_ID) + break; + + /* Get the index for the next hand-off image */ + link_index = get_bl_params_node_index(img_id); + assert((link_index > 0) && + (link_index < bl_mem_params_desc_num)); + } + + /* Invalid image is expected to terminate the loop */ + assert(img_id == INVALID_IMAGE_ID); + + /* Populate arg0 for the next BL image */ + next_bl_params.head->ep_info->args.arg0 = (unsigned long)&next_bl_params; + + /* Flush the parameters to be passed to the next BL image */ + flush_dcache_range((unsigned long)&next_bl_params, + sizeof(next_bl_params)); + + return &next_bl_params; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/common/runtime_svc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/common/runtime_svc.c new file mode 100644 index 0000000..df0d64c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/common/runtime_svc.c @@ -0,0 +1,175 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/******************************************************************************* + * The 'rt_svc_descs' array holds the runtime service descriptors exported by + * services by placing them in the 'rt_svc_descs' linker section. + * The 'rt_svc_descs_indices' array holds the index of a descriptor in the + * 'rt_svc_descs' array. When an SMC arrives, the OEN[29:24] bits and the call + * type[31] bit in the function id are combined to get an index into the + * 'rt_svc_descs_indices' array. This gives the index of the descriptor in the + * 'rt_svc_descs' array which contains the SMC handler. + ******************************************************************************/ +#define RT_SVC_DESCS_START ((uintptr_t) (&__RT_SVC_DESCS_START__)) +#define RT_SVC_DESCS_END ((uintptr_t) (&__RT_SVC_DESCS_END__)) +uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; +static rt_svc_desc_t *rt_svc_descs; + +#define RT_SVC_DECS_NUM ((RT_SVC_DESCS_END - RT_SVC_DESCS_START)\ + / sizeof(rt_svc_desc_t)) + +/******************************************************************************* + * Function to invoke the registered `handle` corresponding to the smc_fid. + ******************************************************************************/ +uintptr_t handle_runtime_svc(uint32_t smc_fid, + void *cookie, + void *handle, + unsigned int flags) +{ + u_register_t x1, x2, x3, x4; + int index, idx; + const rt_svc_desc_t *rt_svc_descs; + + assert(handle); + idx = get_unique_oen_from_smc_fid(smc_fid); + assert(idx >= 0 && idx < MAX_RT_SVCS); + + index = rt_svc_descs_indices[idx]; + if (index < 0 || index >= RT_SVC_DECS_NUM) + SMC_RET1(handle, SMC_UNK); + + rt_svc_descs = (rt_svc_desc_t *) RT_SVC_DESCS_START; + + get_smc_params_from_ctx(handle, x1, x2, x3, x4); + + return rt_svc_descs[index].handle(smc_fid, x1, x2, x3, x4, cookie, + handle, flags); +} + +/******************************************************************************* + * Simple routine to sanity check a runtime service descriptor before using it + ******************************************************************************/ +static int32_t validate_rt_svc_desc(const rt_svc_desc_t *desc) +{ + if (desc == NULL) + return -EINVAL; + + if (desc->start_oen > desc->end_oen) + return -EINVAL; + + if (desc->end_oen >= OEN_LIMIT) + return -EINVAL; + + if (desc->call_type != SMC_TYPE_FAST && desc->call_type != SMC_TYPE_STD) + return -EINVAL; + + /* A runtime service having no init or handle function doesn't make sense */ + if (desc->init == NULL && desc->handle == NULL) + return -EINVAL; + + return 0; +} + +/******************************************************************************* + * This function calls the initialisation routine in the descriptor exported by + * a runtime service. Once a descriptor has been validated, its start & end + * owning entity numbers and the call type are combined to form a unique oen. + * The unique oen is used as an index into the 'rt_svc_descs_indices' array. + * The index of the runtime service descriptor is stored at this index. + ******************************************************************************/ +void runtime_svc_init(void) +{ + int rc = 0, index, start_idx, end_idx; + + /* Assert the number of descriptors detected are less than maximum indices */ + assert((RT_SVC_DESCS_END >= RT_SVC_DESCS_START) && + (RT_SVC_DECS_NUM < MAX_RT_SVCS)); + + /* If no runtime services are implemented then simply bail out */ + if (RT_SVC_DECS_NUM == 0) + return; + + /* Initialise internal variables to invalid state */ + memset(rt_svc_descs_indices, -1, sizeof(rt_svc_descs_indices)); + + rt_svc_descs = (rt_svc_desc_t *) RT_SVC_DESCS_START; + for (index = 0; index < RT_SVC_DECS_NUM; index++) { + rt_svc_desc_t *service = &rt_svc_descs[index]; + + /* + * An invalid descriptor is an error condition since it is + * difficult to predict the system behaviour in the absence + * of this service. + */ + rc = validate_rt_svc_desc(service); + if (rc) { + ERROR("Invalid runtime service descriptor %p\n", + (void *) service); + panic(); + } + + /* + * The runtime service may have separate rt_svc_desc_t + * for its fast smc and standard smc. Since the service itself + * need to be initialized only once, only one of them will have + * an initialisation routine defined. Call the initialisation + * routine for this runtime service, if it is defined. + */ + if (service->init) { + rc = service->init(); + if (rc) { + ERROR("Error initializing runtime service %s\n", + service->name); + continue; + } + } + + /* + * Fill the indices corresponding to the start and end + * owning entity numbers with the index of the + * descriptor which will handle the SMCs for this owning + * entity range. + */ + start_idx = get_unique_oen(rt_svc_descs[index].start_oen, + service->call_type); + assert(start_idx < MAX_RT_SVCS); + end_idx = get_unique_oen(rt_svc_descs[index].end_oen, + service->call_type); + assert(end_idx < MAX_RT_SVCS); + for (; start_idx <= end_idx; start_idx++) + rt_svc_descs_indices[start_idx] = index; + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/common/tf_printf.c b/IPL/SDK/v3m/src/arm-trusted-firmware/common/tf_printf.c new file mode 100644 index 0000000..4bc6643 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/common/tf_printf.c @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include + +#if ((IMAGE_BL31 || IMAGE_BL2) && PLAT_rcar) +extern void rcar_set_log_time(void); +static int newline = 1; +#endif +/*********************************************************** + * The tf_printf implementation for all BL stages + ***********************************************************/ + +#define get_num_va_args(args, lcount) \ + (((lcount) > 1) ? va_arg(args, long long int) : \ + ((lcount) ? va_arg(args, long int) : va_arg(args, int))) + +#define get_unum_va_args(args, lcount) \ + (((lcount) > 1) ? va_arg(args, unsigned long long int) : \ + ((lcount) ? va_arg(args, unsigned long int) : va_arg(args, unsigned int))) + +static void string_print(const char *str) +{ + while (*str) + putchar(*str++); +#if ((IMAGE_BL31 || IMAGE_BL2) && PLAT_rcar) + if ((str - 1) && (*(str - 1) == '\n')) + newline = 1; +#endif +} + +#ifdef AARCH32 +#define unsigned_num_print(unum, radix) \ + do { \ + if ((radix) == 16) \ + unsigned_hex_print(unum); \ + else if ((radix) == 10) \ + unsigned_dec_print(unum); \ + else \ + string_print("tf_printf : Unsupported radix");\ + } while (0); + +/* + * Utility function to print an unsigned number in decimal format for AArch32. + * The function doesn't support printing decimal integers higher than 32 bits + * to avoid having to implement 64-bit integer compiler library functions. + */ +static void unsigned_dec_print(unsigned long long int unum) +{ + unsigned int local_num; + /* Just need enough space to store 32 bit decimal integer */ + unsigned char num_buf[10]; + int i = 0, rem; + + if (unum > UINT_MAX) { + string_print("tf_printf : decimal numbers higher than 32 bits" + " not supported\n"); + return; + } + + local_num = (unsigned int)unum; + + do { + rem = local_num % 10; + num_buf[i++] = '0' + rem; + } while (local_num /= 10); + + while (--i >= 0) + putchar(num_buf[i]); +} + +/* + * Utility function to print an unsigned number in hexadecimal format for + * AArch32. The function doesn't use 64-bit integer arithmetic to avoid + * having to implement 64-bit compiler library functions. It splits the + * 64 bit number into two 32 bit numbers and converts them into equivalent + * ASCII characters. + */ +static void unsigned_hex_print(unsigned long long int unum) +{ + /* Just need enough space to store 16 characters */ + unsigned char num_buf[16]; + int i = 0, rem; + uint32_t num_local = 0, num_msb = 0; + + /* Get the LSB of 64 bit unum */ + num_local = (uint32_t)unum; + /* Get the MSB of 64 bit unum. This works only on Little Endian */ + assert((read_sctlr() & SCTLR_EE_BIT) == 0); + num_msb = *(((uint32_t *) &unum) + 1); + + do { + do { + rem = (num_local & 0xf); + if (rem < 0xa) + num_buf[i++] = '0' + rem; + else + num_buf[i++] = 'a' + (rem - 0xa); + } while (num_local >>= 4); + + num_local = num_msb; + num_msb = 0; + } while (num_local); + + while (--i >= 0) + putchar(num_buf[i]); +} + +#else + +static void unsigned_num_print(unsigned long long int unum, unsigned int radix) +{ + /* Just need enough space to store 64 bit decimal integer */ + unsigned char num_buf[20]; + int i = 0, rem; + + do { + rem = unum % radix; + if (rem < 0xa) + num_buf[i++] = '0' + rem; + else + num_buf[i++] = 'a' + (rem - 0xa); + } while (unum /= radix); + + while (--i >= 0) + putchar(num_buf[i]); +} +#endif /* AARCH32 */ + +/******************************************************************* + * Reduced format print for Trusted firmware. + * The following type specifiers are supported by this print + * %x - hexadecimal format + * %s - string format + * %d or %i - signed decimal format + * %u - unsigned decimal format + * %p - pointer format + * + * The following length specifiers are supported by this print + * %l - long int (64-bit on AArch64) + * %ll - long long int (64-bit on AArch64) + * %z - size_t sized integer formats (64 bit on AArch64) + * + * The print exits on all other formats specifiers other than valid + * combinations of the above specifiers. + *******************************************************************/ +void tf_printf(const char *fmt, ...) +{ + va_list args; + int l_count; + long long int num; + unsigned long long int unum; + char *str; + +#if ((IMAGE_BL31 || IMAGE_BL2) && PLAT_rcar) + if (newline) { + newline = 0; + rcar_set_log_time(); + } +#endif + + va_start(args, fmt); + while (*fmt) { + l_count = 0; + + if (*fmt == '%') { + fmt++; + /* Check the format specifier */ +loop: + switch (*fmt) { + case 'i': /* Fall through to next one */ + case 'd': + num = get_num_va_args(args, l_count); + if (num < 0) { + putchar('-'); + unum = (unsigned long long int)-num; + } else + unum = (unsigned long long int)num; + + unsigned_num_print(unum, 10); + break; + case 's': + str = va_arg(args, char *); + string_print(str); + break; + case 'p': + unum = (uintptr_t)va_arg(args, void *); + if (unum) + string_print("0x"); + + unsigned_num_print(unum, 16); + break; + case 'x': + unum = get_unum_va_args(args, l_count); + unsigned_num_print(unum, 16); + break; + case 'z': + if (sizeof(size_t) == 8) + l_count = 2; + + fmt++; + goto loop; + case 'l': + l_count++; + fmt++; + goto loop; + case 'u': + unum = get_unum_va_args(args, l_count); + unsigned_num_print(unum, 10); + break; + default: + /* Exit on any other format specifier */ + goto exit; + } + fmt++; + continue; + } +#if ((IMAGE_BL31 || IMAGE_BL2) && PLAT_rcar) + if (*fmt == '\n') + newline = 1; +#endif + putchar(*fmt++); + } +exit: + va_end(args); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/contributing.md b/IPL/SDK/v3m/src/arm-trusted-firmware/contributing.md new file mode 100644 index 0000000..9a253ca --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/contributing.md @@ -0,0 +1,107 @@ +Contributing to ARM Trusted Firmware +==================================== + +Getting Started +--------------- + +* Make sure you have a [GitHub account]. +* Create an [issue] for your work if one does not already exist. This gives + everyone visibility of whether others are working on something similar. ARM + licensees may contact ARM directly via their partner managers instead if + they prefer. + * Note that the [issue] tracker for this project is in a separate + [issue tracking repository]. Please follow the guidelines in that + repository. + * If you intend to include Third Party IP in your contribution, please + raise a separate [issue] for this and ensure that the changes that + include Third Party IP are made on a separate topic branch. +* [Fork][] [arm-trusted-firmware][] on GitHub. +* Clone the fork to your own machine. +* Create a local topic branch based on the [arm-trusted-firmware][] `master` + branch. + + +Making Changes +-------------- + +* Make commits of logical units. See these general [Git guidelines] for + contributing to a project. +* Follow the [Linux coding style]; this style is enforced for the ARM Trusted + Firmware project (style errors only, not warnings). + * Use the checkpatch.pl script provided with the Linux source tree. A + Makefile target is provided for convenience (see section 2 in the + [User Guide]). +* Keep the commits on topic. If you need to fix another bug or make another + enhancement, please create a separate [issue] and address it on a separate + topic branch. +* Avoid long commit series. If you do have a long series, consider whether + some commits should be squashed together or addressed in a separate topic. +* Make sure your commit messages are in the proper format. If a commit fixes + a GitHub [issue], include a reference (e.g. + "fixes arm-software/tf-issues#45"); this ensures the [issue] is + [automatically closed] when merged into the [arm-trusted-firmware] `master` + branch. +* Where appropriate, please update the documentation. + * Consider whether the [User Guide], [Porting Guide], [Firmware Design] or + other in-source documentation needs updating. + * If this is your first contribution, you may add your name or your + company name to the [Acknowledgements] file. + * For topics with multiple commits, you should make all documentation + changes (and nothing else) in the last commit of the series. Otherwise, + include the documentation changes within the single commit. +* Please test your changes. As a minimum, ensure UEFI boots to the shell on + the Foundation FVP. See the "[Running the software]" section of the + [User Guide] for more information. + + +Submitting Changes +------------------ + +* Ensure that each commit in the series has at least one `Signed-off-by:` + line, using your real name and email address. The names in the + `Signed-off-by:` and `Author:` lines must match. If anyone else contributes + to the commit, they must also add their own `Signed-off-by:` line. + By adding this line the contributor certifies the contribution is made under + the terms of the [Developer Certificate of Origin (DCO)][DCO]. +* Push your local changes to your fork of the repository. +* Submit a [pull request] to the [arm-trusted-firmware] `integration` branch. + * The changes in the [pull request] will then undergo further review and + testing. Any review comments will be made as comments on the [pull + request]. This may require you to do some rework. +* When the changes are accepted, ARM will integrate them. + * Typically, ARM will merge the [pull request] into the `integration` + branch within the GitHub UI, creating a merge commit. + * Please avoid creating merge commits in the [pull request] itself. + * If the [pull request] is not based on a recent commit, ARM may rebase + it onto the `master` branch first, or ask you to do this. + * If the [pull request] cannot be automatically merged, ARM will ask you + to rebase it onto the `master` branch. + * After final integration testing, ARM will push your merge commit to the + `master` branch. If a problem is found at this stage, the merge commit + will be removed from the `integration` branch and ARM will ask you to + create a new pull request to resolve the problem. + * Please do not delete your topic branch until it is safely merged into + the `master` branch. + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._ + + +[User Guide]: ./docs/user-guide.md +[Running the software]: ./docs/user-guide.md#6--running-the-software +[Porting Guide]: ./docs/porting-guide.md +[Firmware Design]: ./docs/firmware-design.md +[Acknowledgements]: ./acknowledgements.md "Contributor acknowledgements" +[DCO]: ./dco.txt + +[GitHub account]: https://github.com/signup/free +[Fork]: https://help.github.com/articles/fork-a-repo +[issue tracking repository]: https://github.com/ARM-software/tf-issues +[issue]: https://github.com/ARM-software/tf-issues/issues +[pull request]: https://help.github.com/articles/using-pull-requests +[automatically closed]: https://help.github.com/articles/closing-issues-via-commit-messages +[Git guidelines]: http://git-scm.com/book/ch5-2.html +[Linux coding style]: https://www.kernel.org/doc/Documentation/CodingStyle +[arm-trusted-firmware]: https://github.com/ARM-software/arm-trusted-firmware diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/dco.txt b/IPL/SDK/v3m/src/arm-trusted-firmware/dco.txt new file mode 100644 index 0000000..8201f99 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/dco.txt @@ -0,0 +1,37 @@ +Developer Certificate of Origin +Version 1.1 + +Copyright (C) 2004, 2006 The Linux Foundation and its contributors. +1 Letterman Drive +Suite D4700 +San Francisco, CA, 94129 + +Everyone is permitted to copy and distribute verbatim copies of this +license document, but changing it is not allowed. + + +Developer's Certificate of Origin 1.1 + +By making a contribution to this project, I certify that: + +(a) The contribution was created in whole or in part by me and I + have the right to submit it under the open source license + indicated in the file; or + +(b) The contribution is based upon previous work that, to the best + of my knowledge, is covered under an appropriate open source + license and I have the right under that license to submit that + work with modifications, whether created in whole or in part + by me, under the same open source license (unless I am + permitted to submit under a different license), as indicated + in the file; or + +(c) The contribution was provided directly to me by some other + person who certified (a), (b) or (c) and I have not modified + it. + +(d) I understand and agree that this project and the contribution + are public and that a record of the contribution (including all + personal information I submit with it, including my sign-off) is + maintained indefinitely and may be redistributed consistent with + this project or the open source license(s) involved. diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/auth-framework.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/auth-framework.md new file mode 100644 index 0000000..531505b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/auth-framework.md @@ -0,0 +1,921 @@ +Abstracting a Chain of Trust +============================ + +Contents : + +1. [Introduction](#1--introduction) +2. [Framework design](#2--framework-design) +3. [Specifying a Chain of Trust](#3--specifying-a-chain-of-trust) +4. [Implementation example](#4--implementation-example) + + +1. Introduction +---------------- + +The aim of this document is to describe the authentication framework implemented +in the Trusted Firmware. This framework fulfills the following requirements: + +1. It should be possible for a platform port to specify the Chain of Trust in + terms of certificate hierarchy and the mechanisms used to verify a + particular image/certificate. + +2. The framework should distinguish between: + + - The mechanism used to encode and transport information, e.g. DER encoded + X.509v3 certificates to ferry Subject Public Keys, hashes and non-volatile + counters. + + - The mechanism used to verify the transported information i.e. the + cryptographic libraries. + +The framework has been designed following a modular approach illustrated in the +next diagram: + +``` + +---------------+---------------+------------+ + | Trusted | Trusted | Trusted | + | Firmware | Firmware | Firmware | + | Generic | IO Framework | Platform | + | Code i.e. | (IO) | Port | + | BL1/BL2 (GEN) | | (PP) | + +---------------+---------------+------------+ + ^ ^ ^ + | | | + v v v + +-----------+ +-----------+ +-----------+ + | | | | | Image | + | Crypto | | Auth | | Parser | + | Module |<->| Module |<->| Module | + | (CM) | | (AM) | | (IPM) | + | | | | | | + +-----------+ +-----------+ +-----------+ + ^ ^ + | | + v v + +----------------+ +-----------------+ + | Cryptographic | | Image Parser | + | Libraries (CL) | | Libraries (IPL) | + +----------------+ +-----------------+ + | | + | | + | | + v v + +-----------------+ + | Misc. Libs e.g. | + | ASN.1 decoder | + | | + +-----------------+ + + DIAGRAM 1. +``` + +This document describes the inner details of the authentication framework and +the abstraction mechanisms available to specify a Chain of Trust. + + +2. Framework design +-------------------- + +This section describes some aspects of the framework design and the rationale +behind them. These aspects are key to verify a Chain of Trust. + +### 2.1 Chain of Trust + +A CoT is basically a sequence of authentication images which usually starts with +a root of trust and culminates in a single data image. The following diagram +illustrates how this maps to a CoT for the BL31 image described in the +TBBR-Client specification. + +``` + +------------------+ +-------------------+ + | ROTPK/ROTPK Hash |------>| Trusted Key | + +------------------+ | Certificate | + | (Auth Image) | + /+-------------------+ + / | + / | + / | + / | + L v + +------------------+ +-------------------+ + | Trusted World |------>| BL31 Key | + | Public Key | | Certificate | + +------------------+ | (Auth Image) | + +-------------------+ + / | + / | + / | + / | + / v + +------------------+ L +-------------------+ + | BL31 Content |------>| BL31 Content | + | Certificate PK | | Certificate | + +------------------+ | (Auth Image) | + +-------------------+ + / | + / | + / | + / | + / v + +------------------+ L +-------------------+ + | BL31 Hash |------>| BL31 Image | + | | | (Data Image) | + +------------------+ | | + +-------------------+ + + DIAGRAM 2. +``` + +The root of trust is usually a public key (ROTPK) that has been burnt in the +platform and cannot be modified. + +### 2.2 Image types + +Images in a CoT are categorised as authentication and data images. An +authentication image contains information to authenticate a data image or +another authentication image. A data image is usually a boot loader binary, but +it could be any other data that requires authentication. + +### 2.3 Component responsibilities + +For every image in a Chain of Trust, the following high level operations are +performed to verify it: + +1. Allocate memory for the image either statically or at runtime. + +2. Identify the image and load it in the allocated memory. + +3. Check the integrity of the image as per its type. + +4. Authenticate the image as per the cryptographic algorithms used. + +5. If the image is an authentication image, extract the information that will + be used to authenticate the next image in the CoT. + +In Diagram 1, each component is responsible for one or more of these operations. +The responsibilities are briefly described below. + + +#### 2.2.1 TF Generic code and IO framework (GEN/IO) + +These components are responsible for initiating the authentication process for a +particular image in BL1 or BL2. For each BL image that requires authentication, +the Generic code asks recursively the Authentication module what is the parent +image until either an authenticated image or the ROT is reached. Then the +Generic code calls the IO framewotk to load the image and calls the +Authentication module to authenticate it, following the CoT from ROT to Image. + + +#### 2.2.2 TF Platform Port (PP) + +The platform is responsible for: + +1. Specifying the CoT for each image that needs to be authenticated. Details of + how a CoT can be specified by the platform are explained later. The platform + also specifies the authentication methods and the parsing method used for + each image. + +2. Statically allocating memory for each parameter in each image which is + used for verifying the CoT, e.g. memory for public keys, hashes etc. + +3. Providing the ROTPK or a hash of it. + +4. Providing additional information to the IPM to enable it to identify and + extract authentication parameters contained in an image, e.g. if the + parameters are stored as X509v3 extensions, the corresponding OID must be + provided. + +5. Fulfill any other memory requirements of the IPM and the CM (not currently + described in this document). + +6. Export functions to verify an image which uses an authentication method that + cannot be interpreted by the CM, e.g. if an image has to be verified using a + NV counter, then the value of the counter to compare with can only be + provided by the platform. + +7. Export a custom IPM if a proprietary image format is being used (described + later). + + +#### 2.2.3 Authentication Module (AM) + +It is responsible for: + +1. Providing the necessary abstraction mechanisms to describe a CoT. Amongst + other things, the authentication and image parsing methods must be specified + by the PP in the CoT. + +2. Verifying the CoT passed by GEN by utilising functionality exported by the + PP, IPM and CM. + +3. Tracking which images have been verified. In case an image is a part of + multiple CoTs then it should be verified only once e.g. the Trusted World + Key Certificate in the TBBR-Client spec. contains information to verify + SCP_BL2, BL31, BL32 each of which have a separate CoT. (This + responsibility has not been described in this document but should be + trivial to implement). + +4. Reusing memory meant for a data image to verify authentication images e.g. + in the CoT described in Diagram 2, each certificate can be loaded and + verified in the memory reserved by the platform for the BL31 image. By the + time BL31 (the data image) is loaded, all information to authenticate it + will have been extracted from the parent image i.e. BL31 content + certificate. It is assumed that the size of an authentication image will + never exceed the size of a data image. It should be possible to verify this + at build time using asserts. + + +#### 2.2.4 Cryptographic Module (CM) + +The CM is responsible for providing an API to: + +1. Verify a digital signature. +2. Verify a hash. + +The CM does not include any cryptography related code, but it relies on an +external library to perform the cryptographic operations. A Crypto-Library (CL) +linking the CM and the external library must be implemented. The following +functions must be provided by the CL: + +``` +void (*init)(void); +int (*verify_signature)(void *data_ptr, unsigned int data_len, + void *sig_ptr, unsigned int sig_len, + void *sig_alg, unsigned int sig_alg_len, + void *pk_ptr, unsigned int pk_len); +int (*verify_hash)(void *data_ptr, unsigned int data_len, + void *digest_info_ptr, unsigned int digest_info_len); +``` + +These functions are registered in the CM using the macro: +``` +REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash); +``` + +`_name` must be a string containing the name of the CL. This name is used for +debugging purposes. + +#### 2.2.5 Image Parser Module (IPM) + +The IPM is responsible for: + +1. Checking the integrity of each image loaded by the IO framework. +2. Extracting parameters used for authenticating an image based upon a + description provided by the platform in the CoT descriptor. + +Images may have different formats (for example, authentication images could be +x509v3 certificates, signed ELF files or any other platform specific format). +The IPM allows to register an Image Parser Library (IPL) for every image format +used in the CoT. This library must implement the specific methods to parse the +image. The IPM obtains the image format from the CoT and calls the right IPL to +check the image integrity and extract the authentication parameters. + +See Section "Describing the image parsing methods" for more details about the +mechanism the IPM provides to define and register IPLs. + + +### 2.3 Authentication methods + +The AM supports the following authentication methods: + +1. Hash +2. Digital signature + +The platform may specify these methods in the CoT in case it decides to define +a custom CoT instead of reusing a predefined one. + +If a data image uses multiple methods, then all the methods must be a part of +the same CoT. The number and type of parameters are method specific. These +parameters should be obtained from the parent image using the IPM. + +1. Hash + + Parameters: + + 1. A pointer to data to hash + 2. Length of the data + 4. A pointer to the hash + 5. Length of the hash + + The hash will be represented by the DER encoding of the following ASN.1 + type: + + ``` + DigestInfo ::= SEQUENCE { + digestAlgorithm DigestAlgorithmIdentifier, + digest Digest + } + ``` + + This ASN.1 structure makes it possible to remove any assumption about the + type of hash algorithm used as this information accompanies the hash. This + should allow the Cryptography Library (CL) to support multiple hash + algorithm implementations. + +2. Digital Signature + + Parameters: + + 1. A pointer to data to sign + 2. Length of the data + 3. Public Key Algorithm + 4. Public Key value + 5. Digital Signature Algorithm + 6. Digital Signature value + + The Public Key parameters will be represented by the DER encoding of the + following ASN.1 type: + + ``` + SubjectPublicKeyInfo ::= SEQUENCE { + algorithm AlgorithmIdentifier{PUBLIC-KEY,{PublicKeyAlgorithms}}, + subjectPublicKey BIT STRING } + ``` + + The Digital Signature Algorithm will be represented by the DER encoding of + the following ASN.1 types. + + ``` + AlgorithmIdentifier {ALGORITHM:IOSet } ::= SEQUENCE { + algorithm ALGORITHM.&id({IOSet}), + parameters ALGORITHM.&Type({IOSet}{@algorithm}) OPTIONAL + } + ``` + + The digital signature will be represented by: + ``` + signature ::= BIT STRING + ``` + +The authentication framework will use the image descriptor to extract all the +information related to authentication. + + +3. Specifying a Chain of Trust +------------------------------- + +A CoT can be described as a set of image descriptors linked together in a +particular order. The order dictates the sequence in which they must be +verified. Each image has a set of properties which allow the AM to verify it. +These properties are described below. + +The PP is responsible for defining a single or multiple CoTs for a data image. +Unless otherwise specified, the data structures described in the following +sections are populated by the PP statically. + + +### 3.1 Describing the image parsing methods + +The parsing method refers to the format of a particular image. For example, an +authentication image that represents a certificate could be in the X.509v3 +format. A data image that represents a boot loader stage could be in raw binary +or ELF format. The IPM supports three parsing methods. An image has to use one +of the three methods described below. An IPL is responsible for interpreting a +single parsing method. There has to be one IPL for every method used by the +platform. + +1. Raw format: This format is effectively a nop as an image using this method + is treated as being in raw binary format e.g. boot loader images used by ARM + TF. This method should only be used by data images. + +2. X509V3 method: This method uses industry standards like X.509 to represent + PKI certificates (authentication images). It is expected that open source + libraries will be available which can be used to parse an image represented + by this method. Such libraries can be used to write the corresponding IPL + e.g. the X.509 parsing library code in mbed TLS. + +3. Platform defined method: This method caters for platform specific + proprietary standards to represent authentication or data images. For + example, The signature of a data image could be appended to the data image + raw binary. A header could be prepended to the combined blob to specify the + extents of each component. The platform will have to implement the + corresponding IPL to interpret such a format. + +The following enum can be used to define these three methods. + +``` +typedef enum img_type_enum { + IMG_RAW, /* Binary image */ + IMG_PLAT, /* Platform specific format */ + IMG_CERT, /* X509v3 certificate */ + IMG_MAX_TYPES, +} img_type_t; +``` + +An IPL must provide functions with the following prototypes: + +``` +void init(void); +int check_integrity(void *img, unsigned int img_len); +int get_auth_param(const auth_param_type_desc_t *type_desc, + void *img, unsigned int img_len, + void **param, unsigned int *param_len); +``` + +An IPL for each type must be registered using the following macro: + +``` +REGISTER_IMG_PARSER_LIB(_type, _name, _init, _check_int, _get_param) +``` + +* `_type`: one of the types described above. +* `_name`: a string containing the IPL name for debugging purposes. +* `_init`: initialization function pointer. +* `_check_int`: check image integrity function pointer. +* `_get_param`: extract authentication parameter funcion pointer. + +The `init()` function will be used to initialize the IPL. + +The `check_integrity()` function is passed a pointer to the memory where the +image has been loaded by the IO framework and the image length. It should ensure +that the image is in the format corresponding to the parsing method and has not +been tampered with. For example, RFC-2459 describes a validation sequence for an +X.509 certificate. + +The `get_auth_param()` function is passed a parameter descriptor containing +information about the parameter (`type_desc` and `cookie`) to identify and +extract the data corresponding to that parameter from an image. This data will +be used to verify either the current or the next image in the CoT sequence. + +Each image in the CoT will specify the parsing method it uses. This information +will be used by the IPM to find the right parser descriptor for the image. + + +### 3.2 Describing the authentication method(s) + +As part of the CoT, each image has to specify one or more authentication methods +which will be used to verify it. As described in the Section "Authentication +methods", there are three methods supported by the AM. + +``` +typedef enum { + AUTH_METHOD_NONE, + AUTH_METHOD_HASH, + AUTH_METHOD_SIG, + AUTH_METHOD_NUM +} auth_method_type_t; +``` + +The AM defines the type of each parameter used by an authentication method. It +uses this information to: + +1. Specify to the `get_auth_param()` function exported by the IPM, which + parameter should be extracted from an image. + +2. Correctly marshall the parameters while calling the verification function + exported by the CM and PP. + +3. Extract authentication parameters from a parent image in order to verify a + child image e.g. to verify the certificate image, the public key has to be + obtained from the parent image. + +``` +typedef enum { + AUTH_PARAM_NONE, + AUTH_PARAM_RAW_DATA, /* Raw image data */ + AUTH_PARAM_SIG, /* The image signature */ + AUTH_PARAM_SIG_ALG, /* The image signature algorithm */ + AUTH_PARAM_HASH, /* A hash (including the algorithm) */ + AUTH_PARAM_PUB_KEY, /* A public key */ +} auth_param_type_t; +``` + +The AM defines the following structure to identify an authentication parameter +required to verify an image. + +``` +typedef struct auth_param_type_desc_s { + auth_param_type_t type; + void *cookie; +} auth_param_type_desc_t; +``` + +`cookie` is used by the platform to specify additional information to the IPM +which enables it to uniquely identify the parameter that should be extracted +from an image. For example, the hash of a BL3x image in its corresponding +content certificate is stored in an X509v3 custom extension field. An extension +field can only be identified using an OID. In this case, the `cookie` could +contain the pointer to the OID defined by the platform for the hash extension +field while the `type` field could be set to `AUTH_PARAM_HASH`. A value of 0 for +the `cookie` field means that it is not used. + +For each method, the AM defines a structure with the parameters required to +verify the image. + +``` +/* + * Parameters for authentication by hash matching + */ +typedef struct auth_method_param_hash_s { + auth_param_type_desc_t *data; /* Data to hash */ + auth_param_type_desc_t *hash; /* Hash to match with */ +} auth_method_param_hash_t; + +/* + * Parameters for authentication by signature + */ +typedef struct auth_method_param_sig_s { + auth_param_type_desc_t *pk; /* Public key */ + auth_param_type_desc_t *sig; /* Signature to check */ + auth_param_type_desc_t *alg; /* Signature algorithm */ + auth_param_type_desc_t *tbs; /* Data signed */ +} auth_method_param_sig_t; + +``` + +The AM defines the following structure to describe an authentication method for +verifying an image + +``` +/* + * Authentication method descriptor + */ +typedef struct auth_method_desc_s { + auth_method_type_t type; + union { + auth_method_param_hash_t hash; + auth_method_param_sig_t sig; + } param; +} auth_method_desc_t; +``` + +Using the method type specified in the `type` field, the AM finds out what field +needs to access within the `param` union. + +### 3.3 Storing Authentication parameters + +A parameter described by `auth_param_type_desc_t` to verify an image could be +obtained from either the image itself or its parent image. The memory allocated +for loading the parent image will be reused for loading the child image. Hence +parameters which are obtained from the parent for verifying a child image need +to have memory allocated for them separately where they can be stored. This +memory must be statically allocated by the platform port. + +The AM defines the following structure to store the data corresponding to an +authentication parameter. + +``` +typedef struct auth_param_data_desc_s { + void *auth_param_ptr; + unsigned int auth_param_len; +} auth_param_data_desc_t; +``` + +The `auth_param_ptr` field is initialized by the platform. The `auth_param_len` +field is used to specify the length of the data in the memory. + +For parameters that can be obtained from the child image itself, the IPM is +responsible for populating the `auth_param_ptr` and `auth_param_len` fields +while executing the `img_get_auth_param()` function. + +The AM defines the following structure to enable an image to describe the +parameters that should be extracted from it and used to verify the next image +(child) in a CoT. + +``` +typedef struct auth_param_desc_s { + auth_param_type_desc_t type_desc; + auth_param_data_desc_t data; +} auth_param_desc_t; +``` + +### 3.4 Describing an image in a CoT + +An image in a CoT is a consolidation of the following aspects of a CoT described +above. + +1. A unique identifier specified by the platform which allows the IO framework + to locate the image in a FIP and load it in the memory reserved for the data + image in the CoT. + +2. A parsing method which is used by the AM to find the appropriate IPM. + +3. Authentication methods and their parameters as described in the previous + section. These are used to verify the current image. + +4. Parameters which are used to verify the next image in the current CoT. These + parameters are specified only by authentication images and can be extracted + from the current image once it has been verified. + +The following data structure describes an image in a CoT. +``` +typedef struct auth_img_desc_s { + unsigned int img_id; + const struct auth_img_desc_s *parent; + img_type_t img_type; + auth_method_desc_t img_auth_methods[AUTH_METHOD_NUM]; + auth_param_desc_t authenticated_data[COT_MAX_VERIFIED_PARAMS]; +} auth_img_desc_t; +``` +A CoT is defined as an array of `auth_image_desc_t` structures linked together +by the `parent` field. Those nodes with no parent must be authenticated using +the ROTPK stored in the platform. + + +4. Implementation example +-------------------------- + +This section is a detailed guide explaining a trusted boot implementation using +the authentication framework. This example corresponds to the Applicative +Functional Mode (AFM) as specified in the TBBR-Client document. It is +recommended to read this guide along with the source code. + +### 4.1 The TBBR CoT + +The CoT can be found in `drivers/auth/tbbr/tbbr_cot.c`. This CoT consists of an +array of image descriptors and it is registered in the framework using the macro +`REGISTER_COT(cot_desc)`, where 'cot_desc' must be the name of the array +(passing a pointer or any other type of indirection will cause the registration +process to fail). + +The number of images participating in the boot process depends on the CoT. There +is, however, a minimum set of images that are mandatory in the Trusted Firmware +and thus all CoTs must present: + +* `BL2` +* `SCP_BL2` (platform specific) +* `BL31` +* `BL32` (optional) +* `BL33` + +The TBBR specifies the additional certificates that must accompany these images +for a proper authentication. Details about the TBBR CoT may be found in the +[Trusted Board Boot] document. + +Following the [Platform Porting Guide], a platform must provide unique +identifiers for all the images and certificates that will be loaded during the +boot process. If a platform is using the TBBR as a reference for trusted boot, +these identifiers can be obtained from `include/common/tbbr/tbbr_img_def.h`. +ARM platforms include this file in `include/plat/arm/common/arm_def.h`. Other +platforms may also include this file or provide their own identifiers. + +**Important**: the authentication module uses these identifiers to index the +CoT array, so the descriptors location in the array must match the identifiers. + +Each image descriptor must specify: + +* `img_id`: the corresponding image unique identifier defined by the platform. +* `img_type`: the image parser module uses the image type to call the proper + parsing library to check the image integrity and extract the required + authentication parameters. Three types of images are currently supported: + * `IMG_RAW`: image is a raw binary. No parsing functions are available, + other than reading the whole image. + * `IMG_PLAT`: image format is platform specific. The platform may use this + type for custom images not directly supported by the authentication + framework. + * `IMG_CERT`: image is an x509v3 certificate. +* `parent`: pointer to the parent image descriptor. The parent will contain + the information required to authenticate the current image. If the parent + is NULL, the authentication parameters will be obtained from the platform + (i.e. the BL2 and Trusted Key certificates are signed with the ROT private + key, whose public part is stored in the platform). +* `img_auth_methods`: this array defines the authentication methods that must + be checked to consider an image authenticated. Each method consists of a + type and a list of parameter descriptors. A parameter descriptor consists of + a type and a cookie which will point to specific information required to + extract that parameter from the image (i.e. if the parameter is stored in an + x509v3 extension, the cookie will point to the extension OID). Depending on + the method type, a different number of parameters must be specified. + Supported methods are: + * `AUTH_METHOD_HASH`: the hash of the image must match the hash extracted + from the parent image. The following parameter descriptors must be + specified: + * `data`: data to be hashed (obtained from current image) + * `hash`: reference hash (obtained from parent image) + * `AUTH_METHOD_SIG`: the image (usually a certificate) must be signed with + the private key whose public part is extracted from the parent image (or + the platform if the parent is NULL). The following parameter descriptors + must be specified: + * `pk`: the public key (obtained from parent image) + * `sig`: the digital signature (obtained from current image) + * `alg`: the signature algorithm used (obtained from current image) + * `data`: the data to be signed (obtained from current image) +* `authenticated_data`: this array indicates what authentication parameters + must be extracted from an image once it has been authenticated. Each + parameter consists of a parameter descriptor and the buffer address/size + to store the parameter. The CoT is responsible for allocating the required + memory to store the parameters. + +In the `tbbr_cot.c` file, a set of buffers are allocated to store the parameters +extracted from the certificates. In the case of the TBBR CoT, these parameters +are hashes and public keys. In DER format, an RSA-2048 public key requires 294 +bytes, and a hash requires 51 bytes. Depending on the CoT and the authentication +process, some of the buffers may be reused at different stages during the boot. + +Next in that file, the parameter descriptors are defined. These descriptors will +be used to extract the parameter data from the corresponding image. + +#### 4.1.1 Example: the BL31 Chain of Trust + +Four image descriptors form the BL31 Chain of Trust: + +``` +[TRUSTED_KEY_CERT_ID] = { + .img_id = TRUSTED_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = NULL, + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &subject_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &trusted_world_pk, + .data = { + .ptr = (void *)trusted_world_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + }, + [1] = { + .type_desc = &non_trusted_world_pk, + .data = { + .ptr = (void *)non_trusted_world_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + } + } +}, +[SOC_FW_KEY_CERT_ID] = { + .img_id = SOC_FW_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[TRUSTED_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &trusted_world_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &soc_fw_content_pk, + .data = { + .ptr = (void *)content_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + } + } +}, +[SOC_FW_CONTENT_CERT_ID] = { + .img_id = SOC_FW_CONTENT_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[SOC_FW_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &soc_fw_content_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &soc_fw_hash, + .data = { + .ptr = (void *)soc_fw_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } +}, +[BL31_IMAGE_ID] = { + .img_id = BL31_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[SOC_FW_CONTENT_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &soc_fw_hash, + } + } + } +} +``` +The **Trusted Key certificate** is signed with the ROT private key and contains +the Trusted World public key and the Non-Trusted World public key as x509v3 +extensions. This must be specified in the image descriptor using the +`img_auth_methods` and `authenticated_data` arrays, respectively. + +The Trusted Key certificate is authenticated by checking its digital signature +using the ROTPK. Four parameters are required to check a signature: the public +key, the algorithm, the signature and the data that has been signed. Therefore, +four parameter descriptors must be specified with the authentication method: + +* `subject_pk`: parameter descriptor of type `AUTH_PARAM_PUB_KEY`. This type + is used to extract a public key from the parent image. If the cookie is an + OID, the key is extracted from the corresponding x509v3 extension. If the + cookie is NULL, the subject public key is retrieved. In this case, because + the parent image is NULL, the public key is obtained from the platform + (this key will be the ROTPK). +* `sig`: parameter descriptor of type `AUTH_PARAM_SIG`. It is used to extract + the signature from the certificate. +* `sig_alg`: parameter descriptor of type `AUTH_PARAM_SIG`. It is used to + extract the signature algorithm from the certificate. +* `raw_data`: parameter descriptor of type `AUTH_PARAM_RAW_DATA`. It is used + to extract the data to be signed from the certificate. + +Once the signature has been checked and the certificate authenticated, the +Trusted World public key needs to be extracted from the certificate. A new entry +is created in the `authenticated_data` array for that purpose. In that entry, +the corresponding parameter descriptor must be specified along with the buffer +address to store the parameter value. In this case, the `tz_world_pk` descriptor +is used to extract the public key from an x509v3 extension with OID +`TRUSTED_WORLD_PK_OID`. The BL31 key certificate will use this descriptor as +parameter in the signature authentication method. The key is stored in the +`plat_tz_world_pk_buf` buffer. + +The **BL31 Key certificate** is authenticated by checking its digital signature +using the Trusted World public key obtained previously from the Trusted Key +certificate. In the image descriptor, we specify a single authentication method +by signature whose public key is the `tz_world_pk`. Once this certificate has +been authenticated, we have to extract the BL31 public key, stored in the +extension specified by `bl31_content_pk`. This key will be copied to the +`plat_content_pk` buffer. + +The **BL31 certificate** is authenticated by checking its digital signature +using the BL31 public key obtained previously from the BL31 Key certificate. +We specify the authentication method using `bl31_content_pk` as public key. +After authentication, we need to extract the BL31 hash, stored in the extension +specified by `bl31_hash`. This hash will be copied to the `plat_bl31_hash_buf` +buffer. + +The **BL31 image** is authenticated by calculating its hash and matching it +with the hash obtained from the BL31 certificate. The image descriptor contains +a single authentication method by hash. The parameters to the hash method are +the reference hash, `bl31_hash`, and the data to be hashed. In this case, it is +the whole image, so we specify `raw_data`. + +### 4.2 The image parser library + +The image parser module relies on libraries to check the image integrity and +extract the authentication parameters. The number and type of parser libraries +depend on the images used in the CoT. Raw images do not need a library, so +only an x509v3 library is required for the TBBR CoT. + +ARM platforms will use an x509v3 library based on mbed TLS. This library may be +found in `drivers/auth/mbedtls/mbedtls_x509_parser.c`. It exports three +functions: + +``` +void init(void); +int check_integrity(void *img, unsigned int img_len); +int get_auth_param(const auth_param_type_desc_t *type_desc, + void *img, unsigned int img_len, + void **param, unsigned int *param_len); +``` + +The library is registered in the framework using the macro +`REGISTER_IMG_PARSER_LIB()`. Each time the image parser module needs to access +an image of type `IMG_CERT`, it will call the corresponding function exported +in this file. + +The build system must be updated to include the corresponding library and +mbed TLS sources. ARM platforms use the `arm_common.mk` file to pull the +sources. + +### 4.3 The cryptographic library + +The cryptographic module relies on a library to perform the required operations, +i.e. verify a hash or a digital signature. ARM platforms will use a library +based on mbed TLS, which can be found in +`drivers/auth/mbedtls/mbedtls_crypto.c`. This library is registered in the +authentication framework using the macro `REGISTER_CRYPTO_LIB()` and exports +three functions: + +``` +void init(void); +int verify_signature(void *data_ptr, unsigned int data_len, + void *sig_ptr, unsigned int sig_len, + void *sig_alg, unsigned int sig_alg_len, + void *pk_ptr, unsigned int pk_len); +int verify_hash(void *data_ptr, unsigned int data_len, + void *digest_info_ptr, unsigned int digest_info_len); +``` + +The key algorithm (rsa, ecdsa) must be specified in the build system using the +`MBEDTLS_KEY_ALG` variable, so the Makefile can include the corresponding +sources in the build. + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2015, ARM Limited and Contributors. All rights reserved._ + + +[Trusted Board Boot]: ./trusted-board-boot.md +[Platform Porting Guide]: ./porting-guide.md diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/change-log.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/change-log.md new file mode 100644 index 0000000..74edf98 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/change-log.md @@ -0,0 +1,1103 @@ + +ARM Trusted Firmware - version 1.3 +================================== + +New features +------------ + +* Added support for running Trusted Firmware in AArch32 execution state. + + The PSCI library has been refactored to allow integration with **EL3 Runtime + Software**. This is software that is executing at the highest secure + privilege which is EL3 in AArch64 or Secure SVC/Monitor mode in AArch32. See + [PSCI Integration Guide]. + + Included is a minimal AArch32 Secure Payload, **SP-MIN**, that illustrates + the usage and integration of the PSCI library with EL3 Runtime Software + running in AArch32 state. + + Booting to the BL1/BL2 images as well as booting straight to the Secure + Payload is supported. + +* Improvements to the initialization framework for the PSCI service and ARM + Standard Services in general. + + The PSCI service is now initialized as part of ARM Standard Service + initialization. This consolidates the initializations of any ARM Standard + Service that may be added in the future. + + A new function `get_arm_std_svc_args()` is introduced to get arguments + corresponding to each standard service and must be implemented by the EL3 + Runtime Software. + + For PSCI, a new versioned structure `psci_lib_args_t` is introduced to + initialize the PSCI Library. **Note** this is a compatibility break due to + the change in the prototype of `psci_setup()`. + +* To support AArch32 builds of BL1 and BL2, implemented a new, alternative + firmware image loading mechanism that adds flexibility. + + The current mechanism has a hard-coded set of images and execution order + (BL31, BL32, etc). The new mechanism is data-driven by a list of image + descriptors provided by the platform code. + + ARM platforms have been updated to support the new loading mechanism. + + The new mechanism is enabled by a build flag (`LOAD_IMAGE_V2`) which is + currently off by default for the AArch64 build. + + **Note** `TRUSTED_BOARD_BOOT` is currently not supported when + `LOAD_IMAGE_V2` is enabled. + +* Updated requirements for making contributions to ARM TF. + + Commits now must have a 'Signed-off-by:' field to certify that the + contribution has been made under the terms of the + [Developer Certificate of Origin]. + + A signed CLA is no longer required. + + The [Contribution Guide] has been updated to reflect this change. + +* Introduced Performance Measurement Framework (PMF) which provides support + for capturing, storing, dumping and retrieving time-stamps to measure the + execution time of critical paths in the firmware. This relies on defining + fixed sample points at key places in the code. + +* To support the QEMU platform port, imported libfdt v1.4.1 from + https://git.kernel.org/cgit/utils/dtc/dtc.git + +* Updated PSCI support: + + * Added support for PSCI NODE_HW_STATE API for ARM platforms. + + * New optional platform hook, `pwr_domain_pwr_down_wfi()`, in + `plat_psci_ops` to enable platforms to perform platform-specific actions + needed to enter powerdown, including the 'wfi' invocation. + + * PSCI STAT residency and count functions have been added on ARM platforms + by using PMF. + +* Enhancements to the translation table library: + + * Limited memory mapping support for region overlaps to only allow regions + to overlap that are identity mapped or have the same virtual to physical + address offset, and overlap completely but must not cover the same area. + + This limitation will enable future enhancements without having to + support complex edge cases that may not be necessary. + + * The initial translation lookup level is now inferred from the virtual + address space size. Previously, it was hard-coded. + + * Added support for mapping Normal, Inner Non-cacheable, Outer + Non-cacheable memory in the translation table library. + + This can be useful to map a non-cacheable memory region, such as a DMA + buffer. + + * Introduced the MT_EXECUTE/MT_EXECUTE_NEVER memory mapping attributes to + specify the access permissions for instruction execution of a memory + region. + +* Enabled support to isolate code and read-only data on separate memory pages, + allowing independent access control to be applied to each. + +* Enabled SCR_EL3.SIF (Secure Instruction Fetch) bit in BL1 and BL31 common + architectural setup code, preventing fetching instructions from non-secure + memory when in secure state. + +* Enhancements to FIP support: + + * Replaced `fip_create` with `fiptool` which provides a more consistent + and intuitive interface as well as additional support to remove an image + from a FIP file. + + * Enabled printing the SHA256 digest with info command, allowing quick + verification of an image within a FIP without having to extract the + image and running sha256sum on it. + + * Added support for unpacking the contents of an existing FIP file into + the working directory. + + * Aligned command line options for specifying images to use same naming + convention as specified by TBBR and already used in cert_create tool. + +* Refactored the TZC-400 driver to also support memory controllers that + integrate TZC functionality, for example ARM CoreLink DMC-500. Also added + DMC-500 specific support. + +* Implemented generic delay timer based on the system generic counter and + migrated all platforms to use it. + +* Enhanced support for ARM platforms: + + * Updated image loading support to make SCP images (SCP_BL2 and SCP_BL2U) + optional. + + * Enhanced topology description support to allow multi-cluster topology + definitions. + + * Added interconnect abstraction layer to help platform ports select the + right interconnect driver, CCI or CCN, for the platform. + + * Added support to allow loading BL31 in the TZC-secured DRAM instead of + the default secure SRAM. + + * Added support to use a System Security Control (SSC) Registers Unit + enabling ARM TF to be compiled to support multiple ARM platforms and + then select one at runtime. + + * Restricted mapping of Trusted ROM in BL1 to what is actually needed by + BL1 rather than entire Trusted ROM region. + + * Flash is now mapped as execute-never by default. This increases security + by restricting the executable region to what is strictly needed. + +* Applied following erratum workarounds for Cortex-A57: 833471, 826977, + 829520, 828024 and 826974. + +* Added support for Mediatek MT6795 platform. + +* Added support for QEMU virtualization ARMv8-A target. + +* Added support for Rockchip RK3368 and RK3399 platforms. + +* Added support for Xilinx Zynq UltraScale+ MPSoC platform. + +* Added support for ARM Cortex-A73 MPCore Processor. + +* Added support for ARM Cortex-A72 processor. + +* Added support for ARM Cortex-A35 processor. + +* Added support for ARM Cortex-A32 MPCore Processor. + +* Enabled preloaded BL33 alternative boot flow, in which BL2 does not load + BL33 from non-volatile storage and BL31 hands execution over to a preloaded + BL33. The User Guide has been updated with an example of how to use this + option with a bootwrapped kernel. + +* Added support to build ARM TF on a Windows-based host machine. + +* Updated Trusted Board Boot prototype implementation: + + * Enabled the ability for a production ROM with TBBR enabled to boot test + software before a real ROTPK is deployed (e.g. manufacturing mode). + Added support to use ROTPK in certificate without verifying against the + platform value when `ROTPK_NOT_DEPLOYED` bit is set. + + * Added support for non-volatile counter authentication to the + Authentication Module to protect against roll-back. + +* Updated GICv3 support: + + * Enabled processor power-down and automatic power-on using GICv3. + + * Enabled G1S or G0 interrupts to be configured independently. + + * Changed FVP default interrupt driver to be the GICv3-only driver. + **Note** the default build of Trusted Firmware will not be able to boot + Linux kernel with GICv2 FDT blob. + + * Enabled wake-up from CPU_SUSPEND to stand-by by temporarily re-routing + interrupts and then restoring after resume. + +Issues resolved since last release +---------------------------------- + +Known issues +------------ + +* The version of the AEMv8 Base FVP used in this release resets the model + instead of terminating its execution in response to a shutdown request using + the PSCI `SYSTEM_OFF` API. This issue will be fixed in a future version of + the model. + +* Building TF with compiler optimisations disabled (`-O0`) fails. + + +* ARM TF cannot be built with mbed TLS version v2.3.0 due to build warnings + that the ARM TF build system interprets as errors. + +* TBBR is not currently supported when running Trusted Firmware in AArch32 + state. + + +ARM Trusted Firmware - version 1.2 +================================== + +New features +------------ + +* The Trusted Board Boot implementation on ARM platforms now conforms to the + mandatory requirements of the TBBR specification. + + In particular, the boot process is now guarded by a Trusted Watchdog, which + will reset the system in case of an authentication or loading error. On ARM + platforms, a secure instance of ARM SP805 is used as the Trusted Watchdog. + + Also, a firmware update process has been implemented. It enables + authenticated firmware to update firmware images from external interfaces to + SoC Non-Volatile memories. This feature functions even when the current + firmware in the system is corrupt or missing; it therefore may be used as + a recovery mode. + +* Improvements have been made to the Certificate Generation Tool + (`cert_create`) as follows. + + * Added support for the Firmware Update process by extending the Chain + of Trust definition in the tool to include the Firmware Update + certificate and the required extensions. + + * Introduced a new API that allows one to specify command line options in + the Chain of Trust description. This makes the declaration of the tool's + arguments more flexible and easier to extend. + + * The tool has been reworked to follow a data driven approach, which + makes it easier to maintain and extend. + +* Extended the FIP tool (`fip_create`) to support the new set of images + involved in the Firmware Update process. + +* Various memory footprint improvements. In particular: + + * The bakery lock structure for coherent memory has been optimised. + + * The mbed TLS SHA1 functions are not needed, as SHA256 is used to + generate the certificate signature. Therefore, they have been compiled + out, reducing the memory footprint of BL1 and BL2 by approximately + 6 KB. + + * On ARM development platforms, each BL stage now individually defines + the number of regions that it needs to map in the MMU. + +* Added the following new design documents: + + * [Authentication framework] + * [Firmware Update] + * [TF Reset Design] + * [Power Domain Topology Design] + +* Applied the new image terminology to the code base and documentation, as + described on the [TF wiki on GitHub][TF Image Terminology]. + +* The build system has been reworked to improve readability and facilitate + adding future extensions. + +* On ARM standard platforms, BL31 uses the boot console during cold boot + but switches to the runtime console for any later logs at runtime. The TSP + uses the runtime console for all output. + +* Implemented a basic NOR flash driver for ARM platforms. It programs the + device using CFI (Common Flash Interface) standard commands. + +* Implemented support for booting EL3 payloads on ARM platforms, which + reduces the complexity of developing EL3 baremetal code by doing essential + baremetal initialization. + +* Provided separate drivers for GICv3 and GICv2. These expect the entire + software stack to use either GICv2 or GICv3; hybrid GIC software systems + are no longer supported and the legacy ARM GIC driver has been deprecated. + +* Added support for Juno r1 and r2. A single set of Juno TF binaries can run + on Juno r0, r1 and r2 boards. Note that this TF version depends on a Linaro + release that does *not* contain Juno r2 support. + +* Added support for MediaTek mt8173 platform. + +* Implemented a generic driver for ARM CCN IP. + +* Major rework of the PSCI implementation. + + * Added framework to handle composite power states. + + * Decoupled the notions of affinity instances (which describes the + hierarchical arrangement of cores) and of power domain topology, instead + of assuming a one-to-one mapping. + + * Better alignment with version 1.0 of the PSCI specification. + +* Added support for the SYSTEM_SUSPEND PSCI API on ARM platforms. When invoked + on the last running core on a supported platform, this puts the system + into a low power mode with memory retention. + +* Unified the reset handling code as much as possible across BL stages. + Also introduced some build options to enable optimization of the reset path + on platforms that support it. + +* Added a simple delay timer API, as well as an SP804 timer driver, which is + enabled on FVP. + +* Added support for NVidia Tegra T210 and T132 SoCs. + +* Reorganised ARM platforms ports to greatly improve code shareability and + facilitate the reuse of some of this code by other platforms. + +* Added support for ARM Cortex-A72 processor in the CPU specific framework. + +* Provided better error handling. Platform ports can now define their own + error handling, for example to perform platform specific bookkeeping or + post-error actions. + +* Implemented a unified driver for ARM Cache Coherent Interconnects used for + both CCI-400 & CCI-500 IPs. ARM platforms ports have been migrated to this + common driver. The standalone CCI-400 driver has been deprecated. + + +Issues resolved since last release +---------------------------------- + +* The Trusted Board Boot implementation has been redesigned to provide greater + modularity and scalability. See the [Authentication Framework] document. + All missing mandatory features are now implemented. + +* The FVP and Juno ports may now use the hash of the ROTPK stored in the + Trusted Key Storage registers to verify the ROTPK. Alternatively, a + development public key hash embedded in the BL1 and BL2 binaries might be + used instead. The location of the ROTPK is chosen at build-time using the + `ARM_ROTPK_LOCATION` build option. + +* GICv3 is now fully supported and stable. + + +Known issues +------------ + +* The version of the AEMv8 Base FVP used in this release resets the model + instead of terminating its execution in response to a shutdown request using + the PSCI `SYSTEM_OFF` API. This issue will be fixed in a future version of + the model. + +* While this version has low on-chip RAM requirements, there are further + RAM usage enhancements that could be made. + +* The upstream documentation could be improved for structural consistency, + clarity and completeness. In particular, the design documentation is + incomplete for PSCI, the TSP(D) and the Juno platform. + +* Building TF with compiler optimisations disabled (`-O0`) fails. + + +ARM Trusted Firmware - version 1.1 +================================== + +New features +------------ + +* A prototype implementation of Trusted Board Boot has been added. Boot + loader images are verified by BL1 and BL2 during the cold boot path. BL1 and + BL2 use the PolarSSL SSL library to verify certificates and images. The + OpenSSL library is used to create the X.509 certificates. Support has been + added to `fip_create` tool to package the certificates in a FIP. + +* Support for calling CPU and platform specific reset handlers upon entry into + BL3-1 during the cold and warm boot paths has been added. This happens after + another Boot ROM `reset_handler()` has already run. This enables a developer + to perform additional actions or undo actions already performed during the + first call of the reset handlers e.g. apply additional errata workarounds. + +* Support has been added to demonstrate routing of IRQs to EL3 instead of + S-EL1 when execution is in secure world. + +* The PSCI implementation now conforms to version 1.0 of the PSCI + specification. All the mandatory APIs and selected optional APIs are + supported. In particular, support for the `PSCI_FEATURES` API has been + added. A capability variable is constructed during initialization by + examining the `plat_pm_ops` and `spd_pm_ops` exported by the platform and + the Secure Payload Dispatcher. This is used by the PSCI FEATURES function + to determine which PSCI APIs are supported by the platform. + +* Improvements have been made to the PSCI code as follows. + + * The code has been refactored to remove redundant parameters from + internal functions. + + * Changes have been made to the code for PSCI `CPU_SUSPEND`, `CPU_ON` and + `CPU_OFF` calls to facilitate an early return to the caller in case a + failure condition is detected. For example, a PSCI `CPU_SUSPEND` call + returns `SUCCESS` to the caller if a pending interrupt is detected early + in the code path. + + * Optional platform APIs have been added to validate the `power_state` and + `entrypoint` parameters early in PSCI `CPU_ON` and `CPU_SUSPEND` code + paths. + + * PSCI migrate APIs have been reworked to invoke the SPD hook to determine + the type of Trusted OS and the CPU it is resident on (if + applicable). Also, during a PSCI `MIGRATE` call, the SPD hook to migrate + the Trusted OS is invoked. + +* It is now possible to build Trusted Firmware without marking at least an + extra page of memory as coherent. The build flag `USE_COHERENT_MEM` can be + used to choose between the two implementations. This has been made possible + through these changes. + + * An implementation of Bakery locks, where the locks are not allocated in + coherent memory has been added. + + * Memory which was previously marked as coherent is now kept coherent + through the use of software cache maintenance operations. + + Approximately, 4K worth of memory is saved for each boot loader stage when + `USE_COHERENT_MEM=0`. Enabling this option increases the latencies + associated with acquire and release of locks. It also requires changes to + the platform ports. + +* It is now possible to specify the name of the FIP at build time by defining + the `FIP_NAME` variable. + +* Issues with depedencies on the 'fiptool' makefile target have been + rectified. The `fip_create` tool is now rebuilt whenever its source files + change. + +* The BL3-1 runtime console is now also used as the crash console. The crash + console is changed to SoC UART0 (UART2) from the previous FPGA UART0 (UART0) + on Juno. In FVP, it is changed from UART0 to UART1. + +* CPU errata workarounds are applied only when the revision and part number + match. This behaviour has been made consistent across the debug and release + builds. The debug build additionally prints a warning if a mismatch is + detected. + +* It is now possible to issue cache maintenance operations by set/way for a + particular level of data cache. Levels 1-3 are currently supported. + +* The following improvements have been made to the FVP port. + + * The build option `FVP_SHARED_DATA_LOCATION` which allowed relocation of + shared data into the Trusted DRAM has been deprecated. Shared data is + now always located at the base of Trusted SRAM. + + * BL2 Translation tables have been updated to map only the region of + DRAM which is accessible to normal world. This is the region of the 2GB + DDR-DRAM memory at 0x80000000 excluding the top 16MB. The top 16MB is + accessible to only the secure world. + + * BL3-2 can now reside in the top 16MB of DRAM which is accessible only to + the secure world. This can be done by setting the build flag + `FVP_TSP_RAM_LOCATION` to the value `dram`. + +* Separate transation tables are created for each boot loader image. The + `IMAGE_BLx` build options are used to do this. This allows each stage to + create mappings only for areas in the memory map that it needs. + +* A Secure Payload Dispatcher (OPTEED) for the OP-TEE Trusted OS has been + added. Details of using it with ARM Trusted Firmware can be found in + [OP-TEE Dispatcher] + + + +Issues resolved since last release +---------------------------------- + +* The Juno port has been aligned with the FVP port as follows. + + * Support for reclaiming all BL1 RW memory and BL2 memory by overlaying + the BL3-1/BL3-2 NOBITS sections on top of them has been added to the + Juno port. + + * The top 16MB of the 2GB DDR-DRAM memory at 0x80000000 is configured + using the TZC-400 controller to be accessible only to the secure world. + + * The ARM GIC driver is used to configure the GIC-400 instead of using a + GIC driver private to the Juno port. + + * PSCI `CPU_SUSPEND` calls that target a standby state are now supported. + + * The TZC-400 driver is used to configure the controller instead of direct + accesses to the registers. + +* The Linux kernel version referred to in the user guide has DVFS and HMP + support enabled. + +* DS-5 v5.19 did not detect Version 5.8 of the Cortex-A57-A53 Base FVPs in + CADI server mode. This issue is not seen with DS-5 v5.20 and Version 6.2 of + the Cortex-A57-A53 Base FVPs. + + +Known issues +------------ + +* The Trusted Board Boot implementation is a prototype. There are issues with + the modularity and scalability of the design. Support for a Trusted + Watchdog, firmware update mechanism, recovery images and Trusted debug is + absent. These issues will be addressed in future releases. + +* The FVP and Juno ports do not use the hash of the ROTPK stored in the + Trusted Key Storage registers to verify the ROTPK in the + `plat_match_rotpk()` function. This prevents the correct establishment of + the Chain of Trust at the first step in the Trusted Board Boot process. + +* The version of the AEMv8 Base FVP used in this release resets the model + instead of terminating its execution in response to a shutdown request using + the PSCI `SYSTEM_OFF` API. This issue will be fixed in a future version of + the model. + +* GICv3 support is experimental. There are known issues with GICv3 + initialization in the ARM Trusted Firmware. + +* While this version greatly reduces the on-chip RAM requirements, there are + further RAM usage enhancements that could be made. + +* The firmware design documentation for the Test Secure-EL1 Payload (TSP) and + its dispatcher (TSPD) is incomplete. Similarly for the PSCI section. + +* The Juno-specific firmware design documentation is incomplete. + + +ARM Trusted Firmware - version 1.0 +================================== + +New features +------------ + +* It is now possible to map higher physical addresses using non-flat virtual + to physical address mappings in the MMU setup. + +* Wider use is now made of the per-CPU data cache in BL3-1 to store: + + * Pointers to the non-secure and secure security state contexts. + + * A pointer to the CPU-specific operations. + + * A pointer to PSCI specific information (for example the current power + state). + + * A crash reporting buffer. + +* The following RAM usage improvements result in a BL3-1 RAM usage reduction + from 96KB to 56KB (for FVP with TSPD), and a total RAM usage reduction + across all images from 208KB to 88KB, compared to the previous release. + + * Removed the separate `early_exception` vectors from BL3-1 (2KB code size + saving). + + * Removed NSRAM from the FVP memory map, allowing the removal of one + (4KB) translation table. + + * Eliminated the internal `psci_suspend_context` array, saving 2KB. + + * Correctly dimensioned the PSCI `aff_map_node` array, saving 1.5KB in the + FVP port. + + * Removed calling CPU mpidr from the bakery lock API, saving 160 bytes. + + * Removed current CPU mpidr from PSCI common code, saving 160 bytes. + + * Inlined the mmio accessor functions, saving 360 bytes. + + * Fully reclaimed all BL1 RW memory and BL2 memory on the FVP port by + overlaying the BL3-1/BL3-2 NOBITS sections on top of these at runtime. + + * Made storing the FP register context optional, saving 0.5KB per context + (8KB on the FVP port, with TSPD enabled and running on 8 CPUs). + + * Implemented a leaner `tf_printf()` function, allowing the stack to be + greatly reduced. + + * Removed coherent stacks from the codebase. Stacks allocated in normal + memory are now used before and after the MMU is enabled. This saves 768 + bytes per CPU in BL3-1. + + * Reworked the crash reporting in BL3-1 to use less stack. + + * Optimized the EL3 register state stored in the `cpu_context` structure + so that registers that do not change during normal execution are + re-initialized each time during cold/warm boot, rather than restored + from memory. This saves about 1.2KB. + + * As a result of some of the above, reduced the runtime stack size in all + BL images. For BL3-1, this saves 1KB per CPU. + +* PSCI SMC handler improvements to correctly handle calls from secure states + and from AArch32. + +* CPU contexts are now initialized from the `entry_point_info`. BL3-1 fully + determines the exception level to use for the non-trusted firmware (BL3-3) + based on the SPSR value provided by the BL2 platform code (or otherwise + provided to BL3-1). This allows platform code to directly run non-trusted + firmware payloads at either EL2 or EL1 without requiring an EL2 stub or OS + loader. + +* Code refactoring improvements: + + * Refactored `fvp_config` into a common platform header. + + * Refactored the fvp gic code to be a generic driver that no longer has an + explicit dependency on platform code. + + * Refactored the CCI-400 driver to not have dependency on platform code. + + * Simplified the IO driver so it's no longer necessary to call `io_init()` + and moved all the IO storage framework code to one place. + + * Simplified the interface the the TZC-400 driver. + + * Clarified the platform porting interface to the TSP. + + * Reworked the TSPD setup code to support the alternate BL3-2 + intialization flow where BL3-1 generic code hands control to BL3-2, + rather than expecting the TSPD to hand control directly to BL3-2. + + * Considerable rework to PSCI generic code to support CPU specific + operations. + +* Improved console log output, by: + + * Adding the concept of debug log levels. + + * Rationalizing the existing debug messages and adding new ones. + + * Printing out the version of each BL stage at runtime. + + * Adding support for printing console output from assembler code, + including when a crash occurs before the C runtime is initialized. + +* Moved up to the latest versions of the FVPs, toolchain, EDK2, kernel, Linaro + file system and DS-5. + +* On the FVP port, made the use of the Trusted DRAM region optional at build + time (off by default). Normal platforms will not have such a "ready-to-use" + DRAM area so it is not a good example to use it. + +* Added support for PSCI `SYSTEM_OFF` and `SYSTEM_RESET` APIs. + +* Added support for CPU specific reset sequences, power down sequences and + register dumping during crash reporting. The CPU specific reset sequences + include support for errata workarounds. + +* Merged the Juno port into the master branch. Added support for CPU hotplug + and CPU idle. Updated the user guide to describe how to build and run on the + Juno platform. + + +Issues resolved since last release +---------------------------------- + +* Removed the concept of top/bottom image loading. The image loader now + automatically detects the position of the image inside the current memory + layout and updates the layout to minimize fragementation. This resolves the + image loader limitations of previously releases. There are currently no + plans to support dynamic image loading. + +* CPU idle now works on the publicized version of the Foundation FVP. + +* All known issues relating to the compiler version used have now been + resolved. This TF version uses Linaro toolchain 14.07 (based on GCC 4.9). + + +Known issues +------------ + +* GICv3 support is experimental. The Linux kernel patches to support this are + not widely available. There are known issues with GICv3 initialization in + the ARM Trusted Firmware. + +* While this version greatly reduces the on-chip RAM requirements, there are + further RAM usage enhancements that could be made. + +* The firmware design documentation for the Test Secure-EL1 Payload (TSP) and + its dispatcher (TSPD) is incomplete. Similarly for the PSCI section. + +* The Juno-specific firmware design documentation is incomplete. + +* Some recent enhancements to the FVP port have not yet been translated into + the Juno port. These will be tracked via the tf-issues project. + +* The Linux kernel version referred to in the user guide has DVFS and HMP + support disabled due to some known instabilities at the time of this + release. A future kernel version will re-enable these features. + +* DS-5 v5.19 does not detect Version 5.8 of the Cortex-A57-A53 Base FVPs in + CADI server mode. This is because the `` reported by the FVP in + this version has changed. For example, for the Cortex-A57x4-A53x4 Base FVP, + the `` reported by the FVP is `FVP_Base_Cortex_A57x4_A53x4`, while + DS-5 expects it to be `FVP_Base_A57x4_A53x4`. + + The temporary fix to this problem is to change the name of the FVP in + `sw/debugger/configdb/Boards/ARM FVP/Base_A57x4_A53x4/cadi_config.xml`. + Change the following line: + + System Generator:FVP_Base_A57x4_A53x4 + to + System Generator:FVP_Base_Cortex-A57x4_A53x4 + + A similar change can be made to the other Cortex-A57-A53 Base FVP variants. + + +ARM Trusted Firmware - version 0.4 +================================== + +New features +------------ + +* Makefile improvements: + + * Improved dependency checking when building. + + * Removed `dump` target (build now always produces dump files). + + * Enabled platform ports to optionally make use of parts of the Trusted + Firmware (e.g. BL3-1 only), rather than being forced to use all parts. + Also made the `fip` target optional. + + * Specified the full path to source files and removed use of the `vpath` + keyword. + +* Provided translation table library code for potential re-use by platforms + other than the FVPs. + +* Moved architectural timer setup to platform-specific code. + +* Added standby state support to PSCI cpu_suspend implementation. + +* SRAM usage improvements: + + * Started using the `-ffunction-sections`, `-fdata-sections` and + `--gc-sections` compiler/linker options to remove unused code and data + from the images. Previously, all common functions were being built into + all binary images, whether or not they were actually used. + + * Placed all assembler functions in their own section to allow more unused + functions to be removed from images. + + * Updated BL1 and BL2 to use a single coherent stack each, rather than one + per CPU. + + * Changed variables that were unnecessarily declared and initialized as + non-const (i.e. in the .data section) so they are either uninitialized + (zero init) or const. + +* Moved the Test Secure-EL1 Payload (BL3-2) to execute in Trusted SRAM by + default. The option for it to run in Trusted DRAM remains. + +* Implemented a TrustZone Address Space Controller (TZC-400) driver. A + default configuration is provided for the Base FVPs. This means the model + parameter `-C bp.secure_memory=1` is now supported. + +* Started saving the PSCI cpu_suspend 'power_state' parameter prior to + suspending a CPU. This allows platforms that implement multiple power-down + states at the same affinity level to identify a specific state. + +* Refactored the entire codebase to reduce the amount of nesting in header + files and to make the use of system/user includes more consistent. Also + split platform.h to separate out the platform porting declarations from the + required platform porting definitions and the definitions/declarations + specific to the platform port. + +* Optimized the data cache clean/invalidate operations. + +* Improved the BL3-1 unhandled exception handling and reporting. Unhandled + exceptions now result in a dump of registers to the console. + +* Major rework to the handover interface between BL stages, in particular the + interface to BL3-1. The interface now conforms to a specification and is + more future proof. + +* Added support for optionally making the BL3-1 entrypoint a reset handler + (instead of BL1). This allows platforms with an alternative image loading + architecture to re-use BL3-1 with fewer modifications to generic code. + +* Reserved some DDR DRAM for secure use on FVP platforms to avoid future + compatibility problems with non-secure software. + +* Added support for secure interrupts targeting the Secure-EL1 Payload (SP) + (using GICv2 routing only). Demonstrated this working by adding an interrupt + target and supporting test code to the TSP. Also demonstrated non-secure + interrupt handling during TSP processing. + + +Issues resolved since last release +---------------------------------- + +* Now support use of the model parameter `-C bp.secure_memory=1` in the Base + FVPs (see **New features**). + +* Support for secure world interrupt handling now available (see **New + features**). + +* Made enough SRAM savings (see **New features**) to enable the Test Secure-EL1 + Payload (BL3-2) to execute in Trusted SRAM by default. + +* The tested filesystem used for this release (Linaro AArch64 OpenEmbedded + 14.04) now correctly reports progress in the console. + +* Improved the Makefile structure to make it easier to separate out parts of + the Trusted Firmware for re-use in platform ports. Also, improved target + dependency checking. + + +Known issues +------------ + +* GICv3 support is experimental. The Linux kernel patches to support this are + not widely available. There are known issues with GICv3 initialization in + the ARM Trusted Firmware. + +* Dynamic image loading is not available yet. The current image loader + implementation (used to load BL2 and all subsequent images) has some + limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead + to loading errors, even if the images should theoretically fit in memory. + +* The ARM Trusted Firmware still uses too much on-chip Trusted SRAM. A number + of RAM usage enhancements have been identified to rectify this situation. + +* CPU idle does not work on the advertised version of the Foundation FVP. + Some FVP fixes are required that are not available externally at the time + of writing. This can be worked around by disabling CPU idle in the Linux + kernel. + +* Various bugs in ARM Trusted Firmware, UEFI and the Linux kernel have been + observed when using Linaro toolchain versions later than 13.11. Although + most of these have been fixed, some remain at the time of writing. These + mainly seem to relate to a subtle change in the way the compiler converts + between 64-bit and 32-bit values (e.g. during casting operations), which + reveals previously hidden bugs in client code. + +* The firmware design documentation for the Test Secure-EL1 Payload (TSP) and + its dispatcher (TSPD) is incomplete. Similarly for the PSCI section. + + +ARM Trusted Firmware - version 0.3 +================================== + +New features +------------ + +* Support for Foundation FVP Version 2.0 added. + The documented UEFI configuration disables some devices that are unavailable + in the Foundation FVP, including MMC and CLCD. The resultant UEFI binary can + be used on the AEMv8 and Cortex-A57-A53 Base FVPs, as well as the Foundation + FVP. + + NOTE: The software will not work on Version 1.0 of the Foundation FVP. + +* Enabled third party contributions. Added a new contributing.md containing + instructions for how to contribute and updated copyright text in all files + to acknowledge contributors. + +* The PSCI CPU_SUSPEND API has been stabilised to the extent where it can be + used for entry into power down states with the following restrictions: + - Entry into standby states is not supported. + - The API is only supported on the AEMv8 and Cortex-A57-A53 Base FVPs. + +* The PSCI AFFINITY_INFO api has undergone limited testing on the Base FVPs to + allow experimental use. + +* Required C library and runtime header files are now included locally in ARM + Trusted Firmware instead of depending on the toolchain standard include + paths. The local implementation has been cleaned up and reduced in scope. + +* Added I/O abstraction framework, primarily to allow generic code to load + images in a platform-independent way. The existing image loading code has + been reworked to use the new framework. Semi-hosting and NOR flash I/O + drivers are provided. + +* Introduced Firmware Image Package (FIP) handling code and tools. A FIP + combines multiple firmware images with a Table of Contents (ToC) into a + single binary image. The new FIP driver is another type of I/O driver. The + Makefile builds a FIP by default and the FVP platform code expect to load a + FIP from NOR flash, although some support for image loading using semi- + hosting is retained. + + NOTE: Building a FIP by default is a non-backwards-compatible change. + + NOTE: Generic BL2 code now loads a BL3-3 (non-trusted firmware) image into + DRAM instead of expecting this to be pre-loaded at known location. This is + also a non-backwards-compatible change. + + NOTE: Some non-trusted firmware (e.g. UEFI) will need to be rebuilt so that + it knows the new location to execute from and no longer needs to copy + particular code modules to DRAM itself. + +* Reworked BL2 to BL3-1 handover interface. A new composite structure + (bl31_args) holds the superset of information that needs to be passed from + BL2 to BL3-1, including information on how handover execution control to + BL3-2 (if present) and BL3-3 (non-trusted firmware). + +* Added library support for CPU context management, allowing the saving and + restoring of + - Shared system registers between Secure-EL1 and EL1. + - VFP registers. + - Essential EL3 system registers. + +* Added a framework for implementing EL3 runtime services. Reworked the PSCI + implementation to be one such runtime service. + +* Reworked the exception handling logic, making use of both SP_EL0 and SP_EL3 + stack pointers for determining the type of exception, managing general + purpose and system register context on exception entry/exit, and handling + SMCs. SMCs are directed to the correct EL3 runtime service. + +* Added support for a Test Secure-EL1 Payload (TSP) and a corresponding + Dispatcher (TSPD), which is loaded as an EL3 runtime service. The TSPD + implements Secure Monitor functionality such as world switching and + EL1 context management, and is responsible for communication with the TSP. + NOTE: The TSPD does not yet contain support for secure world interrupts. + NOTE: The TSP/TSPD is not built by default. + + +Issues resolved since last release +---------------------------------- + +* Support has been added for switching context between secure and normal + worlds in EL3. + +* PSCI API calls `AFFINITY_INFO` & `PSCI_VERSION` have now been tested (to + a limited extent). + +* The ARM Trusted Firmware build artifacts are now placed in the `./build` + directory and sub-directories instead of being placed in the root of the + project. + +* The ARM Trusted Firmware is now free from build warnings. Build warnings + are now treated as errors. + +* The ARM Trusted Firmware now provides C library support locally within the + project to maintain compatibility between toolchains/systems. + +* The PSCI locking code has been reworked so it no longer takes locks in an + incorrect sequence. + +* The RAM-disk method of loading a Linux file-system has been confirmed to + work with the ARM Trusted Firmware and Linux kernel version (based on + version 3.13) used in this release, for both Foundation and Base FVPs. + + +Known issues +------------ + +The following is a list of issues which are expected to be fixed in the future +releases of the ARM Trusted Firmware. + +* The TrustZone Address Space Controller (TZC-400) is not being programmed + yet. Use of model parameter `-C bp.secure_memory=1` is not supported. + +* No support yet for secure world interrupt handling. + +* GICv3 support is experimental. The Linux kernel patches to support this are + not widely available. There are known issues with GICv3 initialization in + the ARM Trusted Firmware. + +* Dynamic image loading is not available yet. The current image loader + implementation (used to load BL2 and all subsequent images) has some + limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead + to loading errors, even if the images should theoretically fit in memory. + +* The ARM Trusted Firmware uses too much on-chip Trusted SRAM. Currently the + Test Secure-EL1 Payload (BL3-2) executes in Trusted DRAM since there is not + enough SRAM. A number of RAM usage enhancements have been identified to + rectify this situation. + +* CPU idle does not work on the advertised version of the Foundation FVP. + Some FVP fixes are required that are not available externally at the time + of writing. + +* Various bugs in ARM Trusted Firmware, UEFI and the Linux kernel have been + observed when using Linaro toolchain versions later than 13.11. Although + most of these have been fixed, some remain at the time of writing. These + mainly seem to relate to a subtle change in the way the compiler converts + between 64-bit and 32-bit values (e.g. during casting operations), which + reveals previously hidden bugs in client code. + +* The tested filesystem used for this release (Linaro AArch64 OpenEmbedded + 14.01) does not report progress correctly in the console. It only seems to + produce error output, not standard output. It otherwise appears to function + correctly. Other filesystem versions on the same software stack do not + exhibit the problem. + +* The Makefile structure doesn't make it easy to separate out parts of the + Trusted Firmware for re-use in platform ports, for example if only BL3-1 is + required in a platform port. Also, dependency checking in the Makefile is + flawed. + +* The firmware design documentation for the Test Secure-EL1 Payload (TSP) and + its dispatcher (TSPD) is incomplete. Similarly for the PSCI section. + + +ARM Trusted Firmware - version 0.2 +================================== + +New features +------------ + +* First source release. + +* Code for the PSCI suspend feature is supplied, although this is not enabled + by default since there are known issues (see below). + + +Issues resolved since last release +---------------------------------- + +* The "psci" nodes in the FDTs provided in this release now fully comply + with the recommendations made in the PSCI specification. + + +Known issues +------------ + +The following is a list of issues which are expected to be fixed in the future +releases of the ARM Trusted Firmware. + +* The TrustZone Address Space Controller (TZC-400) is not being programmed + yet. Use of model parameter `-C bp.secure_memory=1` is not supported. + +* No support yet for secure world interrupt handling or for switching context + between secure and normal worlds in EL3. + +* GICv3 support is experimental. The Linux kernel patches to support this are + not widely available. There are known issues with GICv3 initialization in + the ARM Trusted Firmware. + +* Dynamic image loading is not available yet. The current image loader + implementation (used to load BL2 and all subsequent images) has some + limitations. Changing BL2 or BL3-1 load addresses in certain ways can lead + to loading errors, even if the images should theoretically fit in memory. + +* Although support for PSCI `CPU_SUSPEND` is present, it is not yet stable + and ready for use. + +* PSCI API calls `AFFINITY_INFO` & `PSCI_VERSION` are implemented but have not + been tested. + +* The ARM Trusted Firmware make files result in all build artifacts being + placed in the root of the project. These should be placed in appropriate + sub-directories. + +* The compilation of ARM Trusted Firmware is not free from compilation + warnings. Some of these warnings have not been investigated yet so they + could mask real bugs. + +* The ARM Trusted Firmware currently uses toolchain/system include files like + stdio.h. It should provide versions of these within the project to maintain + compatibility between toolchains/systems. + +* The PSCI code takes some locks in an incorrect sequence. This may cause + problems with suspend and hotplug in certain conditions. + +* The Linux kernel used in this release is based on version 3.12-rc4. Using + this kernel with the ARM Trusted Firmware fails to start the file-system as + a RAM-disk. It fails to execute user-space `init` from the RAM-disk. As an + alternative, the VirtioBlock mechanism can be used to provide a file-system + to the kernel. + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._ + +[OP-TEE Dispatcher]: optee-dispatcher.md +[Power Domain Topology Design]: psci-pd-tree.md +[TF Image Terminology]: https://github.com/ARM-software/arm-trusted-firmware/wiki/Trusted-Firmware-Image-Terminology +[Authentication Framework]: auth-framework.md +[Firmware Update]: firmware-update.md +[TF Reset Design]: reset-design.md +[PSCI Integration Guide]: psci-lib-integration-guide.md +[Firmware Design]: firmware-design.md +[CPU Specific Build Macros]: cpu-specific-build-macros.md +[User Guide]: user-guide.md +[Porting Guide]: porting-guide.md +[Developer Certificate of Origin]: ../dco.txt +[Contribution Guide]: ../contributing.md diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/cpu-specific-build-macros.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/cpu-specific-build-macros.md new file mode 100644 index 0000000..df2fbd8 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/cpu-specific-build-macros.md @@ -0,0 +1,118 @@ +ARM CPU Specific Build Macros +============================= + +Contents +-------- + +1. [Introduction](#1--introduction) +2. [CPU Errata Workarounds](#2--cpu-errata-workarounds) +3. [CPU Specific optimizations](#3--cpu-specific-optimizations) + + +1. Introduction +---------------- + +This document describes the various build options present in the CPU specific +operations framework to enable errata workarounds and to enable optimizations +for a specific CPU on a platform. + +2. CPU Errata Workarounds +-------------------------- + +ARM Trusted Firmware exports a series of build flags which control the +errata workarounds that are applied to each CPU by the reset handler. The +errata details can be found in the CPU specific errata documents published +by ARM: + +* [Cortex-A53 MPCore Software Developers Errata Notice][A53 Errata Notice] +* [Cortex-A57 MPCore Software Developers Errata Notice][A57 Errata Notice] + +The errata workarounds are implemented for a particular revision or a set of +processor revisions. This is checked by the reset handler at runtime. Each +errata workaround is identified by its `ID` as specified in the processor's +errata notice document. The format of the define used to enable/disable the +errata workaround is `ERRATA__`, where the `Processor name` +is for example `A57` for the `Cortex_A57` CPU. + +All workarounds are disabled by default. The platform is responsible for +enabling these workarounds according to its requirement by defining the +errata workaround build flags in the platform specific makefile. In case +these workarounds are enabled for the wrong CPU revision then the errata +workaround is not applied. In the DEBUG build, this is indicated by +printing a warning to the crash console. + +In the current implementation, a platform which has more than 1 variant +with different revisions of a processor has no runtime mechanism available +for it to specify which errata workarounds should be enabled or not. + +The value of the build flags are 0 by default, that is, disabled. Any other +value will enable it. + +For Cortex-A53, following errata build flags are defined : + +* `ERRATA_A53_826319`: This applies errata 826319 workaround to Cortex-A53 + CPU. This needs to be enabled only for revision <= r0p2 of the CPU. + +* `ERRATA_A53_836870`: This applies errata 836870 workaround to Cortex-A53 + CPU. This needs to be enabled only for revision <= r0p3 of the CPU. From + r0p4 and onwards, this errata is enabled by default. + +For Cortex-A57, following errata build flags are defined : + +* `ERRATA_A57_806969`: This applies errata 806969 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision r0p0 of the CPU. + +* `ERRATA_A57_813420`: This applies errata 813420 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision r0p0 of the CPU. + +* `ERRATA_A57_826974`: This applies errata 826974 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision <= r1p1 of the CPU. + +* `ERRATA_A57_826977`: This applies errata 826977 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision <= r1p1 of the CPU. + +* `ERRATA_A57_828024`: This applies errata 828024 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision <= r1p1 of the CPU. + +* `ERRATA_A57_829520`: This applies errata 829520 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision <= r1p2 of the CPU. + +* `ERRATA_A57_833471`: This applies errata 833471 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision <= r1p2 of the CPU. + +3. CPU Specific optimizations +------------------------------ + +This section describes some of the optimizations allowed by the CPU micro +architecture that can be enabled by the platform as desired. + +* `SKIP_A57_L1_FLUSH_PWR_DWN`: This flag enables an optimization in the + Cortex-A57 cluster power down sequence by not flushing the Level 1 data + cache. The L1 data cache and the L2 unified cache are inclusive. A flush + of the L2 by set/way flushes any dirty lines from the L1 as well. This + is a known safe deviation from the Cortex-A57 TRM defined power down + sequence. Each Cortex-A57 based platform must make its own decision on + whether to use the optimization. + +* `A53_DISABLE_NON_TEMPORAL_HINT`: This flag disables the cache non-temporal + hint. The LDNP/STNP instructions as implemented on Cortex-A53 do not behave + in a way most programmers expect, and will most probably result in a + significant speed degradation to any code that employs them. The ARMv8-A + architecture (see ARM DDI 0487A.h, section D3.4.3) allows cores to ignore + the non-temporal hint and treat LDNP/STNP as LDP/STP instead. Enabling this + flag enforces this behaviour. This needs to be enabled only for revisions + <= r0p3 of the CPU and is enabled by default. + +* `A57_DISABLE_NON_TEMPORAL_HINT`: This flag has the same behaviour as + `A53_DISABLE_NON_TEMPORAL_HINT` but for Cortex-A57. This needs to be + enabled only for revisions <= r1p2 of the CPU and is enabled by default, + as recommended in section "4.7 Non-Temporal Loads/Stores" of the + [Cortex-A57 Software Optimization Guide][A57 SW Optimization Guide]. + +- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved._ + +[A57 SW Optimization Guide]: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf +[A53 Errata Notice]: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html +[A57 Errata Notice]: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/diagrams/default_reset_code.png b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/diagrams/default_reset_code.png new file mode 100644 index 0000000000000000000000000000000000000000..d8675e4a3f81b7e8bfedfb9c39c48f7f9b286344 GIT binary patch literal 41796 zcmdqJbwE|^wmymtA_|HiElMb@bSohOQqqk`cXt?oq)0a?A<~GjXqJj}*8&zL9gFVf z4%}z&d(Qstv+q9loOA!U^TTh!WUhC<^L8`SyRVmyh;cTJ# zXtWt$XX5e8R}7Eg{COpVh`g*>@wjNL5w1?Wk-C+GHSzwe1;xzloQe~2xs+%Fbt0J0 zt4Vt^%tiPH3-!480{kq6Z+Qj_>*IAXO*r@EeAnqk4F9cPmGx>rtw|nMSu%Myv)5{l zp*tP;ay0^8!vR%~p4e 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https://wiki.gnome.org/Apps/Dia/Download +# + +set -e + +# Usage: generate_image +function generate_image +{ + dia \ + --show-layers=$1 \ + --filter=png \ + --export=$2 \ + reset_code_flow.dia + +} + +# The 'reset_code_flow.dia' file is organized in several layers. +# Each image is generated by combining and exporting the appropriate set of +# layers. +generate_image \ + Frontground,Background,cpu_type_check,boot_type_check \ + default_reset_code.png + +generate_image \ + Frontground,Background,no_cpu_type_check,boot_type_check \ + reset_code_no_cpu_check.png + +generate_image \ + Frontground,Background,cpu_type_check,no_boot_type_check \ + reset_code_no_boot_type_check.png + +generate_image \ + Frontground,Background,no_cpu_type_check,no_boot_type_check \ + reset_code_no_checks.png diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/diagrams/non-sec-int-handling.png b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/diagrams/non-sec-int-handling.png new file mode 100644 index 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[Introduction](#1--introduction) +2. [Cold boot](#2--cold-boot) +3. [EL3 runtime services framework](#3--el3-runtime-services-framework) +4. [Power State Coordination Interface](#4--power-state-coordination-interface) +5. [Secure-EL1 Payloads and Dispatchers](#5--secure-el1-payloads-and-dispatchers) +6. [Crash Reporting in BL31](#6--crash-reporting-in-bl31) +7. [Guidelines for Reset Handlers](#7--guidelines-for-reset-handlers) +8. [CPU specific operations framework](#8--cpu-specific-operations-framework) +9. [Memory layout of BL images](#9-memory-layout-of-bl-images) +10. [Firmware Image Package (FIP)](#10--firmware-image-package-fip) +11. [Use of coherent memory in Trusted Firmware](#11--use-of-coherent-memory-in-trusted-firmware) +12. [Isolating code and read-only data on separate memory pages](#12--isolating-code-and-read-only-data-on-separate-memory-pages) +13. [Performance Measurement Framework](#13--performance-measurement-framework) +14. [Code Structure](#14--code-structure) +15. [References](#15--references) + + +1. Introduction +---------------- + +The ARM Trusted Firmware implements a subset of the Trusted Board Boot +Requirements (TBBR) Platform Design Document (PDD) [1] for ARM reference +platforms. The TBB sequence starts when the platform is powered on and runs up +to the stage where it hands-off control to firmware running in the normal +world in DRAM. This is the cold boot path. + +The ARM Trusted Firmware also implements the Power State Coordination Interface +([PSCI]) PDD [2] as a runtime service. PSCI is the interface from normal world +software to firmware implementing power management use-cases (for example, +secondary CPU boot, hotplug and idle). Normal world software can access ARM +Trusted Firmware runtime services via the ARM SMC (Secure Monitor Call) +instruction. The SMC instruction must be used as mandated by the [SMC Calling +Convention PDD][SMCCC] [3]. + +The ARM Trusted Firmware implements a framework for configuring and managing +interrupts generated in either security state. The details of the interrupt +management framework and its design can be found in [ARM Trusted +Firmware Interrupt Management Design guide][INTRG] [4]. + +The ARM Trusted Firmware can be built to support either AArch64 or AArch32 +execution state. + +2. Cold boot +------------- + +The cold boot path starts when the platform is physically turned on. If +`COLD_BOOT_SINGLE_CPU=0`, one of the CPUs released from reset is chosen as the +primary CPU, and the remaining CPUs are considered secondary CPUs. The primary +CPU is chosen through platform-specific means. The cold boot path is mainly +executed by the primary CPU, other than essential CPU initialization executed by +all CPUs. The secondary CPUs are kept in a safe platform-specific state until +the primary CPU has performed enough initialization to boot them. + +Refer to the [Reset Design] for more information on the effect of the +`COLD_BOOT_SINGLE_CPU` platform build option. + +The cold boot path in this implementation of the ARM Trusted Firmware, +depends on the execution state. +For AArch64, it is divided into five steps (in order of execution): + +* Boot Loader stage 1 (BL1) _AP Trusted ROM_ +* Boot Loader stage 2 (BL2) _Trusted Boot Firmware_ +* Boot Loader stage 3-1 (BL31) _EL3 Runtime Software_ +* Boot Loader stage 3-2 (BL32) _Secure-EL1 Payload_ (optional) +* Boot Loader stage 3-3 (BL33) _Non-trusted Firmware_ + +For AArch32, it is divided into four steps (in order of execution): + +* Boot Loader stage 1 (BL1) _AP Trusted ROM_ +* Boot Loader stage 2 (BL2) _Trusted Boot Firmware_ +* Boot Loader stage 3-2 (BL32) _EL3 Runtime Software_ +* Boot Loader stage 3-3 (BL33) _Non-trusted Firmware_ + +ARM development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a +combination of the following types of memory regions. Each bootloader stage uses +one or more of these memory regions. + +* Regions accessible from both non-secure and secure states. For example, + non-trusted SRAM, ROM and DRAM. +* Regions accessible from only the secure state. For example, trusted SRAM and + ROM. The FVPs also implement the trusted DRAM which is statically + configured. Additionally, the Base FVPs and Juno development platform + configure the TrustZone Controller (TZC) to create a region in the DRAM + which is accessible only from the secure state. + + +The sections below provide the following details: + +* initialization and execution of the first three stages during cold boot +* specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for + AArch32) entrypoint requirements for use by alternative Trusted Boot + Firmware in place of the provided BL1 and BL2 + + +### BL1 + +This stage begins execution from the platform's reset vector at EL3. The reset +address is platform dependent but it is usually located in a Trusted ROM area. +The BL1 data section is copied to trusted SRAM at runtime. + +On the ARM development platforms, BL1 code starts execution from the reset +vector defined by the constant `BL1_RO_BASE`. The BL1 data section is copied +to the top of trusted SRAM as defined by the constant `BL1_RW_BASE`. + +The functionality implemented by this stage is as follows. + +#### Determination of boot path + +Whenever a CPU is released from reset, BL1 needs to distinguish between a warm +boot and a cold boot. This is done using platform-specific mechanisms (see the +`plat_get_my_entrypoint()` function in the [Porting Guide]). In the case of a +warm boot, a CPU is expected to continue execution from a separate +entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe +platform-specific state (see the `plat_secondary_cold_boot_setup()` function in +the [Porting Guide]) while the primary CPU executes the remaining cold boot path +as described in the following sections. + +This step only applies when `PROGRAMMABLE_RESET_ADDRESS=0`. Refer to the +[Reset Design] for more information on the effect of the +`PROGRAMMABLE_RESET_ADDRESS` platform build option. + +#### Architectural initialization + +BL1 performs minimal architectural initialization as follows. + +* Exception vectors + + BL1 sets up simple exception vectors for both synchronous and asynchronous + exceptions. The default behavior upon receiving an exception is to populate + a status code in the general purpose register `X0/R0` and call the + `plat_report_exception()` function (see the [Porting Guide]). The status + code is one of: + + For AArch64: + 0x0 : Synchronous exception from Current EL with SP_EL0 + 0x1 : IRQ exception from Current EL with SP_EL0 + 0x2 : FIQ exception from Current EL with SP_EL0 + 0x3 : System Error exception from Current EL with SP_EL0 + 0x4 : Synchronous exception from Current EL with SP_ELx + 0x5 : IRQ exception from Current EL with SP_ELx + 0x6 : FIQ exception from Current EL with SP_ELx + 0x7 : System Error exception from Current EL with SP_ELx + 0x8 : Synchronous exception from Lower EL using aarch64 + 0x9 : IRQ exception from Lower EL using aarch64 + 0xa : FIQ exception from Lower EL using aarch64 + 0xb : System Error exception from Lower EL using aarch64 + 0xc : Synchronous exception from Lower EL using aarch32 + 0xd : IRQ exception from Lower EL using aarch32 + 0xe : FIQ exception from Lower EL using aarch32 + 0xf : System Error exception from Lower EL using aarch32 + + For AArch32: + 0x10 : User mode + 0x11 : FIQ mode + 0x12 : IRQ mode + 0x13 : SVC mode + 0x16 : Monitor mode + 0x17 : Abort mode + 0x1a : Hypervisor mode + 0x1b : Undefined mode + 0x1f : System mode + + The `plat_report_exception()` implementation on the ARM FVP port programs + the Versatile Express System LED register in the following format to + indicate the occurence of an unexpected exception: + + SYS_LED[0] - Security state (Secure=0/Non-Secure=1) + SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0) + For AArch32 it is always 0x0 + SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value + of the status code + + A write to the LED register reflects in the System LEDs (S6LED0..7) in the + CLCD window of the FVP. + + BL1 does not expect to receive any exceptions other than the SMC exception. + For the latter, BL1 installs a simple stub. The stub expects to receive a + limited set of SMC types (determined by their function IDs in the general + purpose register `X0/R0`): + - `BL1_SMC_RUN_IMAGE`: This SMC is raised by BL2 to make BL1 pass control + to EL3 Runtime Software. + - All SMCs listed in section "BL1 SMC Interface" in the [Firmware Update] + Design Guide are supported for AArch64 only. These SMCs are currently + not supported when BL1 is built for AArch32. + + Any other SMC leads to an assertion failure. + +* CPU initialization + + BL1 calls the `reset_handler()` function which in turn calls the CPU + specific reset handler function (see the section: "CPU specific operations + framework"). + +* Control register setup (for AArch64) + - `SCTLR_EL3`. Instruction cache is enabled by setting the `SCTLR_EL3.I` + bit. Alignment and stack alignment checking is enabled by setting the + `SCTLR_EL3.A` and `SCTLR_EL3.SA` bits. Exception endianness is set to + little-endian by clearing the `SCTLR_EL3.EE` bit. + + - `SCR_EL3`. The register width of the next lower exception level is set + to AArch64 by setting the `SCR.RW` bit. The `SCR.EA` bit is set to trap + both External Aborts and SError Interrupts in EL3. The `SCR.SIF` bit is + also set to disable instruction fetches from Non-secure memory when in + secure state. + + - `CPTR_EL3`. Accesses to the `CPACR_EL1` register from EL1 or EL2, or the + `CPTR_EL2` register from EL2 are configured to not trap to EL3 by + clearing the `CPTR_EL3.TCPAC` bit. Access to the trace functionality is + configured not to trap to EL3 by clearing the `CPTR_EL3.TTA` bit. + Instructions that access the registers associated with Floating Point + and Advanced SIMD execution are configured to not trap to EL3 by + clearing the `CPTR_EL3.TFP` bit. + + - `DAIF`. The SError interrupt is enabled by clearing the SError interrupt + mask bit. + +* Control register setup (for AArch32) + - `SCTLR`. Instruction cache is enabled by setting the `SCTLR.I` bit. + Alignment checking is enabled by setting the `SCTLR.A` bit. + Exception endianness is set to little-endian by clearing the + `SCTLR.EE` bit. + + - `SCR`. The `SCR.SIF` bit is set to disable instruction fetches from + Non-secure memory when in secure state. + + - `CPACR`. Allow execution of Advanced SIMD instructions at PL0 and PL1, + by clearing the `CPACR.ASEDIS` bit. Access to the trace functionality + is configured not to trap to undefined mode by clearing the + `CPACR.TRCDIS` bit. + + - `NSACR`. Enable non-secure access to Advanced SIMD functionality and + system register access to implemented trace registers. + + - `FPEXC`. Enable access to the Advanced SIMD and floating-point + functionality from all Exception levels. + + - `CPSR.A`. The Asynchronous data abort interrupt is enabled by clearing + the Asynchronous data abort interrupt mask bit. + +#### Platform initialization + +On ARM platforms, BL1 performs the following platform initializations: + +* Enable the Trusted Watchdog. +* Initialize the console. +* Configure the Interconnect to enable hardware coherency. +* Enable the MMU and map the memory it needs to access. +* Configure any required platform storage to load the next bootloader image + (BL2). + +#### Firmware Update detection and execution + +After performing platform setup, BL1 common code calls +`bl1_plat_get_next_image_id()` to determine if [Firmware Update] is required or +to proceed with the normal boot process. If the platform code returns +`BL2_IMAGE_ID` then the normal boot sequence is executed as described in the +next section, else BL1 assumes that [Firmware Update] is required and execution +passes to the first image in the [Firmware Update] process. In either case, BL1 +retrieves a descriptor of the next image by calling `bl1_plat_get_image_desc()`. +The image descriptor contains an `entry_point_info_t` structure, which BL1 +uses to initialize the execution state of the next image. + +#### BL2 image load and execution + +In the normal boot flow, BL1 execution continues as follows: + +1. BL1 prints the following string from the primary CPU to indicate successful + execution of the BL1 stage: + + "Booting Trusted Firmware" + +2. BL1 determines the amount of free trusted SRAM memory available by + calculating the extent of its own data section, which also resides in + trusted SRAM. BL1 loads a BL2 raw binary image from platform storage, at a + platform-specific base address. If the BL2 image file is not present or if + there is not enough free trusted SRAM the following error message is + printed: + + "Failed to load BL2 firmware." + + BL1 calculates the amount of Trusted SRAM that can be used by the BL2 + image. The exact load location of the image is provided as a base address + in the platform header. Further description of the memory layout can be + found later in this document. + +3. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at + Secure SVC mode (for AArch32), starting from its load address. + +4. BL1 also passes information about the amount of trusted SRAM used and + available for use. This information is populated at a platform-specific + memory address. + + +### BL2 + +BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure +SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific +base address (more information can be found later in this document). +The functionality implemented by BL2 is as follows. + +#### Architectural initialization + +For AArch64, BL2 performs the minimal architectural initialization required +for subsequent stages of the ARM Trusted Firmware and normal world software. +EL1 and EL0 are given access to Floating Point and Advanced SIMD registers +by clearing the `CPACR.FPEN` bits. + +For AArch32, the minimal architectural initialization required for subsequent +stages of the ARM Trusted Firmware and normal world software is taken care of +in BL1 as both BL1 and BL2 execute at PL1. + +#### Platform initialization + +On ARM platforms, BL2 performs the following platform initializations: + +* Initialize the console. +* Configure any required platform storage to allow loading further bootloader + images. +* Enable the MMU and map the memory it needs to access. +* Perform platform security setup to allow access to controlled components. +* Reserve some memory for passing information to the next bootloader image + EL3 Runtime Software and populate it. +* Define the extents of memory available for loading each subsequent + bootloader image. + +#### Image loading in BL2 + +Image loading scheme in BL2 depends on `LOAD_IMAGE_V2` build option. If the +flag is disabled, the BLxx images are loaded, by calling the respective +load_blxx() function from BL2 generic code. If the flag is enabled, the BL2 +generic code loads the images based on the list of loadable images provided +by the platform. BL2 passes the list of executable images provided by the +platform to the next handover BL image. By default, this flag is disabled for +AArch64 and the AArch32 build is supported only if this flag is enabled. + +#### SCP_BL2 (System Control Processor Firmware) image load + +Some systems have a separate System Control Processor (SCP) for power, clock, +reset and system control. BL2 loads the optional SCP_BL2 image from platform +storage into a platform-specific region of secure memory. The subsequent +handling of SCP_BL2 is platform specific. For example, on the Juno ARM +development platform port the image is transferred into SCP's internal memory +using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM +memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP) +for BL2 execution to continue. + +#### EL3 Runtime Software image load + +BL2 loads the EL3 Runtime Software image from platform storage into a platform- +specific address in trusted SRAM. If there is not enough memory to load the +image or image is missing it leads to an assertion failure. If `LOAD_IMAGE_V2` +is disabled and if image loads successfully, BL2 updates the amount of trusted +SRAM used and available for use by EL3 Runtime Software. This information is +populated at a platform-specific memory address. + +#### AArch64 BL32 (Secure-EL1 Payload) image load + +BL2 loads the optional BL32 image from platform storage into a platform- +specific region of secure memory. The image executes in the secure world. BL2 +relies on BL31 to pass control to the BL32 image, if present. Hence, BL2 +populates a platform-specific area of memory with the entrypoint/load-address +of the BL32 image. The value of the Saved Processor Status Register (`SPSR`) +for entry into BL32 is not determined by BL2, it is initialized by the +Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for +managing interaction with BL32. This information is passed to BL31. + +#### BL33 (Non-trusted Firmware) image load + +BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from +platform storage into non-secure memory as defined by the platform. + +BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state +initialization is complete. Hence, BL2 populates a platform-specific area of +memory with the entrypoint and Saved Program Status Register (`SPSR`) of the +normal world software image. The entrypoint is the load address of the BL33 +image. The `SPSR` is determined as specified in Section 5.13 of the [PSCI PDD] +[PSCI]. This information is passed to the EL3 Runtime Software. + +#### AArch64 BL31 (EL3 Runtime Software) execution + +BL2 execution continues as follows: + +1. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the + BL31 entrypoint. The exception is handled by the SMC exception handler + installed by BL1. + +2. BL1 turns off the MMU and flushes the caches. It clears the + `SCTLR_EL3.M/I/C` bits, flushes the data cache to the point of coherency + and invalidates the TLBs. + +3. BL1 passes control to BL31 at the specified entrypoint at EL3. + + +### AArch64 BL31 + +The image for this stage is loaded by BL2 and BL1 passes control to BL31 at +EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and +loaded at a platform-specific base address (more information can be found later +in this document). The functionality implemented by BL31 is as follows. + +#### Architectural initialization + +Currently, BL31 performs a similar architectural initialization to BL1 as +far as system register settings are concerned. Since BL1 code resides in ROM, +architectural initialization in BL31 allows override of any previous +initialization done by BL1. + +BL31 initializes the per-CPU data framework, which provides a cache of +frequently accessed per-CPU data optimised for fast, concurrent manipulation +on different CPUs. This buffer includes pointers to per-CPU contexts, crash +buffer, CPU reset and power down operations, PSCI data, platform data and so on. + +It then replaces the exception vectors populated by BL1 with its own. BL31 +exception vectors implement more elaborate support for handling SMCs since this +is the only mechanism to access the runtime services implemented by BL31 (PSCI +for example). BL31 checks each SMC for validity as specified by the +[SMC calling convention PDD][SMCCC] before passing control to the required SMC +handler routine. + +BL31 programs the `CNTFRQ_EL0` register with the clock frequency of the system +counter, which is provided by the platform. + +#### Platform initialization + +BL31 performs detailed platform initialization, which enables normal world +software to function correctly. + +On ARM platforms, this consists of the following: + +* Initialize the console. +* Configure the Interconnect to enable hardware coherency. +* Enable the MMU and map the memory it needs to access. +* Initialize the generic interrupt controller. +* Initialize the power controller device. +* Detect the system topology. + +#### Runtime services initialization + +BL31 is responsible for initializing the runtime services. One of them is PSCI. + +As part of the PSCI initializations, BL31 detects the system topology. It also +initializes the data structures that implement the state machine used to track +the state of power domain nodes. The state can be one of `OFF`, `RUN` or +`RETENTION`. All secondary CPUs are initially in the `OFF` state. The cluster +that the primary CPU belongs to is `ON`; any other cluster is `OFF`. It also +initializes the locks that protect them. BL31 accesses the state of a CPU or +cluster immediately after reset and before the data cache is enabled in the +warm boot path. It is not currently possible to use 'exclusive' based spinlocks, +therefore BL31 uses locks based on Lamport's Bakery algorithm instead. + +The runtime service framework and its initialization is described in more +detail in the "EL3 runtime services framework" section below. + +Details about the status of the PSCI implementation are provided in the +"Power State Coordination Interface" section below. + +#### AArch64 BL32 (Secure-EL1 Payload) image initialization + +If a BL32 image is present then there must be a matching Secure-EL1 Payload +Dispatcher (SPD) service (see later for details). During initialization +that service must register a function to carry out initialization of BL32 +once the runtime services are fully initialized. BL31 invokes such a +registered function to initialize BL32 before running BL33. This initialization +is not necessary for AArch32 SPs. + +Details on BL32 initialization and the SPD's role are described in the +"Secure-EL1 Payloads and Dispatchers" section below. + +#### BL33 (Non-trusted Firmware) execution + +EL3 Runtime Software initializes the EL2 or EL1 processor context for normal- +world cold boot, ensuring that no secure state information finds its way into +the non-secure execution state. EL3 Runtime Software uses the entrypoint +information provided by BL2 to jump to the Non-trusted firmware image (BL33) +at the highest available Exception Level (EL2 if available, otherwise EL1). + +### Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only) + +Some platforms have existing implementations of Trusted Boot Firmware that +would like to use ARM Trusted Firmware BL31 for the EL3 Runtime Software. To +enable this firmware architecture it is important to provide a fully documented +and stable interface between the Trusted Boot Firmware and BL31. + +Future changes to the BL31 interface will be done in a backwards compatible +way, and this enables these firmware components to be independently enhanced/ +updated to develop and exploit new functionality. + +#### Required CPU state when calling `bl31_entrypoint()` during cold boot + +This function must only be called by the primary CPU. + +On entry to this function the calling primary CPU must be executing in AArch64 +EL3, little-endian data access, and all interrupt sources masked: + + PSTATE.EL = 3 + PSTATE.RW = 1 + PSTATE.DAIF = 0xf + SCTLR_EL3.EE = 0 + +X0 and X1 can be used to pass information from the Trusted Boot Firmware to the +platform code in BL31: + + X0 : Reserved for common Trusted Firmware information + X1 : Platform specific information + +BL31 zero-init sections (e.g. `.bss`) should not contain valid data on entry, +these will be zero filled prior to invoking platform setup code. + +##### Use of the X0 and X1 parameters + +The parameters are platform specific and passed from `bl31_entrypoint()` to +`bl31_early_platform_setup()`. The value of these parameters is never directly +used by the common BL31 code. + +The convention is that `X0` conveys information regarding the BL31, BL32 and +BL33 images from the Trusted Boot firmware and `X1` can be used for other +platform specific purpose. This convention allows platforms which use ARM +Trusted Firmware's BL1 and BL2 images to transfer additional platform specific +information from Secure Boot without conflicting with future evolution of the +Trusted Firmware using `X0` to pass a `bl31_params` structure. + +BL31 common and SPD initialization code depends on image and entrypoint +information about BL33 and BL32, which is provided via BL31 platform APIs. +This information is required until the start of execution of BL33. This +information can be provided in a platform defined manner, e.g. compiled into +the platform code in BL31, or provided in a platform defined memory location +by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the +Cold boot Initialization parameters. This data may need to be cleaned out of +the CPU caches if it is provided by an earlier boot stage and then accessed by +BL31 platform code before the caches are enabled. + +ARM Trusted Firmware's BL2 implementation passes a `bl31_params` structure in +`X0` and the ARM development platforms interpret this in the BL31 platform +code. + +##### MMU, Data caches & Coherency + +BL31 does not depend on the enabled state of the MMU, data caches or +interconnect coherency on entry to `bl31_entrypoint()`. If these are disabled +on entry, these should be enabled during `bl31_plat_arch_setup()`. + +##### Data structures used in the BL31 cold boot interface + +These structures are designed to support compatibility and independent +evolution of the structures and the firmware images. For example, a version of +BL31 that can interpret the BL3x image information from different versions of +BL2, a platform that uses an extended entry_point_info structure to convey +additional register information to BL31, or a ELF image loader that can convey +more details about the firmware images. + +To support these scenarios the structures are versioned and sized, which enables +BL31 to detect which information is present and respond appropriately. The +`param_header` is defined to capture this information: + + typedef struct param_header { + uint8_t type; /* type of the structure */ + uint8_t version; /* version of this structure */ + uint16_t size; /* size of this structure in bytes */ + uint32_t attr; /* attributes: unused bits SBZ */ + } param_header_t; + +The structures using this format are `entry_point_info`, `image_info` and +`bl31_params`. The code that allocates and populates these structures must set +the header fields appropriately, and the `SET_PARAM_HEAD()` a macro is defined +to simplify this action. + +#### Required CPU state for BL31 Warm boot initialization + +When requesting a CPU power-on, or suspending a running CPU, ARM Trusted +Firmware provides the platform power management code with a Warm boot +initialization entry-point, to be invoked by the CPU immediately after the +reset handler. On entry to the Warm boot initialization function the calling +CPU must be in AArch64 EL3, little-endian data access and all interrupt sources +masked: + + PSTATE.EL = 3 + PSTATE.RW = 1 + PSTATE.DAIF = 0xf + SCTLR_EL3.EE = 0 + +The PSCI implementation will initialize the processor state and ensure that the +platform power management code is then invoked as required to initialize all +necessary system, cluster and CPU resources. + +### AArch32 EL3 Runtime Software entrypoint interface + +To enable this firmware architecture it is important to provide a fully +documented and stable interface between the Trusted Boot Firmware and the +AArch32 EL3 Runtime Software. + +Future changes to the entrypoint interface will be done in a backwards +compatible way, and this enables these firmware components to be independently +enhanced/updated to develop and exploit new functionality. + +#### Required CPU state when entering during cold boot + +This function must only be called by the primary CPU. + +On entry to this function the calling primary CPU must be executing in AArch32 +EL3, little-endian data access, and all interrupt sources masked: + + PSTATE.AIF = 0x7 + SCTLR.EE = 0 + +R0 and R1 are used to pass information from the Trusted Boot Firmware to the +platform code in AArch32 EL3 Runtime Software: + + R0 : Reserved for common Trusted Firmware information + R1 : Platform specific information + +##### Use of the R0 and R1 parameters + +The parameters are platform specific and the convention is that `R0` conveys +information regarding the BL3x images from the Trusted Boot firmware and `R1` +can be used for other platform specific purpose. This convention allows +platforms which use ARM Trusted Firmware's BL1 and BL2 images to transfer +additional platform specific information from Secure Boot without conflicting +with future evolution of the Trusted Firmware using `R0` to pass a `bl_params` +structure. + +The AArch32 EL3 Runtime Software is responsible for entry into BL33. This +information can be obtained in a platform defined manner, e.g. compiled into +the AArch32 EL3 Runtime Software, or provided in a platform defined memory +location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware +via the Cold boot Initialization parameters. This data may need to be cleaned +out of the CPU caches if it is provided by an earlier boot stage and then +accessed by AArch32 EL3 Runtime Software before the caches are enabled. + +When using AArch32 EL3 Runtime Software, the ARM development platforms pass a +`bl_params` structure in `R0` from BL2 to be interpreted by AArch32 EL3 Runtime +Software platform code. + +##### MMU, Data caches & Coherency + +AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU, +data caches or interconnect coherency in its entrypoint. They must be explicitly +enabled if required. + +##### Data structures used in cold boot interface + +The AArch32 EL3 Runtime Software cold boot interface uses `bl_params` instead +of `bl31_params`. The `bl_params` structure is based on the convention +described in AArch64 BL31 cold boot interface section. + +#### Required CPU state for warm boot initialization + +When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3 +Runtime Software must ensure execution of a warm boot initialization entrypoint. +If ARM Trusted Firmware BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build +flag is false, then AArch32 EL3 Runtime Software must ensure that BL1 branches +to the warm boot entrypoint by arranging for the BL1 platform function, +plat_get_my_entrypoint(), to return a non-zero value. + +In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian +data access and all interrupt sources masked: + + PSTATE.AIF = 0x7 + SCTLR.EE = 0 + +The warm boot entrypoint may be implemented by using the ARM Trusted Firmware +`psci_warmboot_entrypoint()` function. In that case, the platform must fulfil +the pre-requisites mentioned in the [PSCI Library integration guide] +[PSCI Lib guide]. + +3. EL3 runtime services framework +---------------------------------- + +Software executing in the non-secure state and in the secure state at exception +levels lower than EL3 will request runtime services using the Secure Monitor +Call (SMC) instruction. These requests will follow the convention described in +the SMC Calling Convention PDD ([SMCCC]). The [SMCCC] assigns function +identifiers to each SMC request and describes how arguments are passed and +returned. + +The EL3 runtime services framework enables the development of services by +different providers that can be easily integrated into final product firmware. +The following sections describe the framework which facilitates the +registration, initialization and use of runtime services in EL3 Runtime +Software (BL31). + +The design of the runtime services depends heavily on the concepts and +definitions described in the [SMCCC], in particular SMC Function IDs, Owning +Entity Numbers (OEN), Fast and Standard calls, and the SMC32 and SMC64 calling +conventions. Please refer to that document for more detailed explanation of +these terms. + +The following runtime services are expected to be implemented first. They have +not all been instantiated in the current implementation. + +1. Standard service calls + + This service is for management of the entire system. The Power State + Coordination Interface ([PSCI]) is the first set of standard service calls + defined by ARM (see PSCI section later). + +2. Secure-EL1 Payload Dispatcher service + + If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then + it also requires a _Secure Monitor_ at EL3 to switch the EL1 processor + context between the normal world (EL1/EL2) and trusted world (Secure-EL1). + The Secure Monitor will make these world switches in response to SMCs. The + [SMCCC] provides for such SMCs with the Trusted OS Call and Trusted + Application Call OEN ranges. + + The interface between the EL3 Runtime Software and the Secure-EL1 Payload is + not defined by the [SMCCC] or any other standard. As a result, each + Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime + service - within ARM Trusted Firmware this service is referred to as the + Secure-EL1 Payload Dispatcher (SPD). + + ARM Trusted Firmware provides a Test Secure-EL1 Payload (TSP) and its + associated Dispatcher (TSPD). Details of SPD design and TSP/TSPD operation + are described in the "Secure-EL1 Payloads and Dispatchers" section below. + +3. CPU implementation service + + This service will provide an interface to CPU implementation specific + services for a given platform e.g. access to processor errata workarounds. + This service is currently unimplemented. + +Additional services for ARM Architecture, SiP and OEM calls can be implemented. +Each implemented service handles a range of SMC function identifiers as +described in the [SMCCC]. + + +### Registration + +A runtime service is registered using the `DECLARE_RT_SVC()` macro, specifying +the name of the service, the range of OENs covered, the type of service and +initialization and call handler functions. This macro instantiates a `const +struct rt_svc_desc` for the service with these details (see `runtime_svc.h`). +This structure is allocated in a special ELF section `rt_svc_descs`, enabling +the framework to find all service descriptors included into BL31. + +The specific service for a SMC Function is selected based on the OEN and call +type of the Function ID, and the framework uses that information in the service +descriptor to identify the handler for the SMC Call. + +The service descriptors do not include information to identify the precise set +of SMC function identifiers supported by this service implementation, the +security state from which such calls are valid nor the capability to support +64-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately +to these aspects of a SMC call is the responsibility of the service +implementation, the framework is focused on integration of services from +different providers and minimizing the time taken by the framework before the +service handler is invoked. + +Details of the parameters, requirements and behavior of the initialization and +call handling functions are provided in the following sections. + + +### Initialization + +`runtime_svc_init()` in `runtime_svc.c` initializes the runtime services +framework running on the primary CPU during cold boot as part of the BL31 +initialization. This happens prior to initializing a Trusted OS and running +Normal world boot firmware that might in turn use these services. +Initialization involves validating each of the declared runtime service +descriptors, calling the service initialization function and populating the +index used for runtime lookup of the service. + +The BL31 linker script collects all of the declared service descriptors into a +single array and defines symbols that allow the framework to locate and traverse +the array, and determine its size. + +The framework does basic validation of each descriptor to halt firmware +initialization if service declaration errors are detected. The framework does +not check descriptors for the following error conditions, and may behave in an +unpredictable manner under such scenarios: + +1. Overlapping OEN ranges +2. Multiple descriptors for the same range of OENs and `call_type` +3. Incorrect range of owning entity numbers for a given `call_type` + +Once validated, the service `init()` callback is invoked. This function carries +out any essential EL3 initialization before servicing requests. The `init()` +function is only invoked on the primary CPU during cold boot. If the service +uses per-CPU data this must either be initialized for all CPUs during this call, +or be done lazily when a CPU first issues an SMC call to that service. If +`init()` returns anything other than `0`, this is treated as an initialization +error and the service is ignored: this does not cause the firmware to halt. + +The OEN and call type fields present in the SMC Function ID cover a total of +128 distinct services, but in practice a single descriptor can cover a range of +OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a +service handler, the framework uses an array of 128 indices that map every +distinct OEN/call-type combination either to one of the declared services or to +indicate the service is not handled. This `rt_svc_descs_indices[]` array is +populated for all of the OENs covered by a service after the service `init()` +function has reported success. So a service that fails to initialize will never +have it's `handle()` function invoked. + +The following figure shows how the `rt_svc_descs_indices[]` index maps the SMC +Function ID call type and OEN onto a specific service handler in the +`rt_svc_descs[]` array. + +![Image 1](diagrams/rt-svc-descs-layout.png?raw=true) + + +### Handling an SMC + +When the EL3 runtime services framework receives a Secure Monitor Call, the SMC +Function ID is passed in W0 from the lower exception level (as per the +[SMCCC]). If the calling register width is AArch32, it is invalid to invoke an +SMC Function which indicates the SMC64 calling convention: such calls are +ignored and return the Unknown SMC Function Identifier result code `0xFFFFFFFF` +in R0/X0. + +Bit[31] (fast/standard call) and bits[29:24] (owning entity number) of the SMC +Function ID are combined to index into the `rt_svc_descs_indices[]` array. The +resulting value might indicate a service that has no handler, in this case the +framework will also report an Unknown SMC Function ID. Otherwise, the value is +used as a further index into the `rt_svc_descs[]` array to locate the required +service and handler. + +The service's `handle()` callback is provided with five of the SMC parameters +directly, the others are saved into memory for retrieval (if needed) by the +handler. The handler is also provided with an opaque `handle` for use with the +supporting library for parameter retrieval, setting return values and context +manipulation; and with `flags` indicating the security state of the caller. The +framework finally sets up the execution stack for the handler, and invokes the +services `handle()` function. + +On return from the handler the result registers are populated in X0-X3 before +restoring the stack and CPU state and returning from the original SMC. + + +4. Power State Coordination Interface +-------------------------------------- + +TODO: Provide design walkthrough of PSCI implementation. + +The PSCI v1.0 specification categorizes APIs as optional and mandatory. All the +mandatory APIs in PSCI v1.0 and all the APIs in PSCI v0.2 draft specification +[Power State Coordination Interface PDD] [PSCI] are implemented. The table lists +the PSCI v1.0 APIs and their support in generic code. + +An API implementation might have a dependency on platform code e.g. CPU_SUSPEND +requires the platform to export a part of the implementation. Hence the level +of support of the mandatory APIs depends upon the support exported by the +platform port as well. The Juno and FVP (all variants) platforms export all the +required support. + +| PSCI v1.0 API |Supported| Comments | +|:----------------------|:--------|:------------------------------------------| +|`PSCI_VERSION` | Yes | The version returned is 1.0 | +|`CPU_SUSPEND` | Yes* | | +|`CPU_OFF` | Yes* | | +|`CPU_ON` | Yes* | | +|`AFFINITY_INFO` | Yes | | +|`MIGRATE` | Yes** | | +|`MIGRATE_INFO_TYPE` | Yes** | | +|`MIGRATE_INFO_CPU` | Yes** | | +|`SYSTEM_OFF` | Yes* | | +|`SYSTEM_RESET` | Yes* | | +|`PSCI_FEATURES` | Yes | | +|`CPU_FREEZE` | No | | +|`CPU_DEFAULT_SUSPEND` | No | | +|`NODE_HW_STATE` | Yes* | | +|`SYSTEM_SUSPEND` | Yes* | | +|`PSCI_SET_SUSPEND_MODE`| No | | +|`PSCI_STAT_RESIDENCY` | Yes* | | +|`PSCI_STAT_COUNT` | Yes* | | + +*Note : These PSCI APIs require platform power management hooks to be +registered with the generic PSCI code to be supported. + +**Note : These PSCI APIs require appropriate Secure Payload Dispatcher +hooks to be registered with the generic PSCI code to be supported. + +The PSCI implementation in ARM Trusted Firmware is a library which can be +integrated with AArch64 or AArch32 EL3 Runtime Software for ARMv8-A systems. +A guide to integrating PSCI library with AArch32 EL3 Runtime Software +can be found [here][PSCI Lib guide]. + + +5. Secure-EL1 Payloads and Dispatchers +--------------------------------------- + +On a production system that includes a Trusted OS running in Secure-EL1/EL0, +the Trusted OS is coupled with a companion runtime service in the BL31 +firmware. This service is responsible for the initialisation of the Trusted +OS and all communications with it. The Trusted OS is the BL32 stage of the +boot flow in ARM Trusted Firmware. The firmware will attempt to locate, load +and execute a BL32 image. + +ARM Trusted Firmware uses a more general term for the BL32 software that runs +at Secure-EL1 - the _Secure-EL1 Payload_ - as it is not always a Trusted OS. + +The ARM Trusted Firmware provides a Test Secure-EL1 Payload (TSP) and a Test +Secure-EL1 Payload Dispatcher (TSPD) service as an example of how a Trusted OS +is supported on a production system using the Runtime Services Framework. On +such a system, the Test BL32 image and service are replaced by the Trusted OS +and its dispatcher service. The ARM Trusted Firmware build system expects that +the dispatcher will define the build flag `NEED_BL32` to enable it to include +the BL32 in the build either as a binary or to compile from source depending +on whether the `BL32` build option is specified or not. + +The TSP runs in Secure-EL1. It is designed to demonstrate synchronous +communication with the normal-world software running in EL1/EL2. Communication +is initiated by the normal-world software + +* either directly through a Fast SMC (as defined in the [SMCCC]) + +* or indirectly through a [PSCI] SMC. The [PSCI] implementation in turn + informs the TSPD about the requested power management operation. This allows + the TSP to prepare for or respond to the power state change + +The TSPD service is responsible for. + +* Initializing the TSP + +* Routing requests and responses between the secure and the non-secure + states during the two types of communications just described + +### Initializing a BL32 Image + +The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing +the BL32 image. It needs access to the information passed by BL2 to BL31 to do +so. This is provided by: + + entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t); + +which returns a reference to the `entry_point_info` structure corresponding to +the image which will be run in the specified security state. The SPD uses this +API to get entry point information for the SECURE image, BL32. + +In the absence of a BL32 image, BL31 passes control to the normal world +bootloader image (BL33). When the BL32 image is present, it is typical +that the SPD wants control to be passed to BL32 first and then later to BL33. + +To do this the SPD has to register a BL32 initialization function during +initialization of the SPD service. The BL32 initialization function has this +prototype: + + int32_t init(void); + +and is registered using the `bl31_register_bl32_init()` function. + +Trusted Firmware supports two approaches for the SPD to pass control to BL32 +before returning through EL3 and running the non-trusted firmware (BL33): + +1. In the BL32 setup function, use `bl31_set_next_image_type()` to + request that the exit from `bl31_main()` is to the BL32 entrypoint in + Secure-EL1. BL31 will exit to BL32 using the asynchronous method by + calling `bl31_prepare_next_image_entry()` and `el3_exit()`. + + When the BL32 has completed initialization at Secure-EL1, it returns to + BL31 by issuing an SMC, using a Function ID allocated to the SPD. On + receipt of this SMC, the SPD service handler should switch the CPU context + from trusted to normal world and use the `bl31_set_next_image_type()` and + `bl31_prepare_next_image_entry()` functions to set up the initial return to + the normal world firmware BL33. On return from the handler the framework + will exit to EL2 and run BL33. + +2. The BL32 setup function registers an initialization function using + `bl31_register_bl32_init()` which provides a SPD-defined mechanism to + invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32 + entrypoint. + NOTE: The Test SPD service included with the Trusted Firmware provides one + implementation of such a mechanism. + + On completion BL32 returns control to BL31 via a SMC, and on receipt the + SPD service handler invokes the synchronous call return mechanism to return + to the BL32 initialization function. On return from this function, + `bl31_main()` will set up the return to the normal world firmware BL33 and + continue the boot process in the normal world. + + +6. Crash Reporting in BL31 +---------------------------- + +BL31 implements a scheme for reporting the processor state when an unhandled +exception is encountered. The reporting mechanism attempts to preserve all the +register contents and report it via a dedicated UART (PL011 console). BL31 +reports the general purpose, EL3, Secure EL1 and some EL2 state registers. + +A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via +the per-CPU pointer cache. The implementation attempts to minimise the memory +required for this feature. The file `crash_reporting.S` contains the +implementation for crash reporting. + +The sample crash output is shown below. + + x0 :0x000000004F00007C + x1 :0x0000000007FFFFFF + x2 :0x0000000004014D50 + x3 :0x0000000000000000 + x4 :0x0000000088007998 + x5 :0x00000000001343AC + x6 :0x0000000000000016 + x7 :0x00000000000B8A38 + x8 :0x00000000001343AC + x9 :0x00000000000101A8 + x10 :0x0000000000000002 + x11 :0x000000000000011C + x12 :0x00000000FEFDC644 + x13 :0x00000000FED93FFC + x14 :0x0000000000247950 + x15 :0x00000000000007A2 + x16 :0x00000000000007A4 + x17 :0x0000000000247950 + x18 :0x0000000000000000 + x19 :0x00000000FFFFFFFF + x20 :0x0000000004014D50 + x21 :0x000000000400A38C + x22 :0x0000000000247950 + x23 :0x0000000000000010 + x24 :0x0000000000000024 + x25 :0x00000000FEFDC868 + x26 :0x00000000FEFDC86A + x27 :0x00000000019EDEDC + x28 :0x000000000A7CFDAA + x29 :0x0000000004010780 + x30 :0x000000000400F004 + scr_el3 :0x0000000000000D3D + sctlr_el3 :0x0000000000C8181F + cptr_el3 :0x0000000000000000 + tcr_el3 :0x0000000080803520 + daif :0x00000000000003C0 + mair_el3 :0x00000000000004FF + spsr_el3 :0x00000000800003CC + elr_el3 :0x000000000400C0CC + ttbr0_el3 :0x00000000040172A0 + esr_el3 :0x0000000096000210 + sp_el3 :0x0000000004014D50 + far_el3 :0x000000004F00007C + spsr_el1 :0x0000000000000000 + elr_el1 :0x0000000000000000 + spsr_abt :0x0000000000000000 + spsr_und :0x0000000000000000 + spsr_irq :0x0000000000000000 + spsr_fiq :0x0000000000000000 + sctlr_el1 :0x0000000030C81807 + actlr_el1 :0x0000000000000000 + cpacr_el1 :0x0000000000300000 + csselr_el1 :0x0000000000000002 + sp_el1 :0x0000000004028800 + esr_el1 :0x0000000000000000 + ttbr0_el1 :0x000000000402C200 + ttbr1_el1 :0x0000000000000000 + mair_el1 :0x00000000000004FF + amair_el1 :0x0000000000000000 + tcr_el1 :0x0000000000003520 + tpidr_el1 :0x0000000000000000 + tpidr_el0 :0x0000000000000000 + tpidrro_el0 :0x0000000000000000 + dacr32_el2 :0x0000000000000000 + ifsr32_el2 :0x0000000000000000 + par_el1 :0x0000000000000000 + far_el1 :0x0000000000000000 + afsr0_el1 :0x0000000000000000 + afsr1_el1 :0x0000000000000000 + contextidr_el1 :0x0000000000000000 + vbar_el1 :0x0000000004027000 + cntp_ctl_el0 :0x0000000000000000 + cntp_cval_el0 :0x0000000000000000 + cntv_ctl_el0 :0x0000000000000000 + cntv_cval_el0 :0x0000000000000000 + cntkctl_el1 :0x0000000000000000 + fpexc32_el2 :0x0000000004000700 + sp_el0 :0x0000000004010780 + +7. Guidelines for Reset Handlers +--------------------------------- + +Trusted Firmware implements a framework that allows CPU and platform ports to +perform actions very early after a CPU is released from reset in both the cold +and warm boot paths. This is done by calling the `reset_handler()` function in +both the BL1 and BL31 images. It in turn calls the platform and CPU specific +reset handling functions. + +Details for implementing a CPU specific reset handler can be found in +Section 8. Details for implementing a platform specific reset handler can be +found in the [Porting Guide](see the `plat_reset_handler()` function). + +When adding functionality to a reset handler, keep in mind that if a different +reset handling behavior is required between the first and the subsequent +invocations of the reset handling code, this should be detected at runtime. +In other words, the reset handler should be able to detect whether an action has +already been performed and act as appropriate. Possible courses of actions are, +e.g. skip the action the second time, or undo/redo it. + +8. CPU specific operations framework +----------------------------- + +Certain aspects of the ARMv8 architecture are implementation defined, +that is, certain behaviours are not architecturally defined, but must be defined +and documented by individual processor implementations. The ARM Trusted +Firmware implements a framework which categorises the common implementation +defined behaviours and allows a processor to export its implementation of that +behaviour. The categories are: + +1. Processor specific reset sequence. + +2. Processor specific power down sequences. + +3. Processor specific register dumping as a part of crash reporting. + +Each of the above categories fulfils a different requirement. + +1. allows any processor specific initialization before the caches and MMU + are turned on, like implementation of errata workarounds, entry into + the intra-cluster coherency domain etc. + +2. allows each processor to implement the power down sequence mandated in + its Technical Reference Manual (TRM). + +3. allows a processor to provide additional information to the developer + in the event of a crash, for example Cortex-A53 has registers which + can expose the data cache contents. + +Please note that only 2. is mandated by the TRM. + +The CPU specific operations framework scales to accommodate a large number of +different CPUs during power down and reset handling. The platform can specify +any CPU optimization it wants to enable for each CPU. It can also specify +the CPU errata workarounds to be applied for each CPU type during reset +handling by defining CPU errata compile time macros. Details on these macros +can be found in the [cpu-specific-build-macros.md][CPUBM] file. + +The CPU specific operations framework depends on the `cpu_ops` structure which +needs to be exported for each type of CPU in the platform. It is defined in +`include/lib/cpus/aarch64/cpu_macros.S` and has the following fields : `midr`, +`reset_func()`, `core_pwr_dwn()`, `cluster_pwr_dwn()` and `cpu_reg_dump()`. + +The CPU specific files in `lib/cpus` export a `cpu_ops` data structure with +suitable handlers for that CPU. For example, `lib/cpus/aarch64/cortex_a53.S` +exports the `cpu_ops` for Cortex-A53 CPU. According to the platform +configuration, these CPU specific files must be included in the build by +the platform makefile. The generic CPU specific operations framework code exists +in `lib/cpus/aarch64/cpu_helpers.S`. + +### CPU specific Reset Handling + +After a reset, the state of the CPU when it calls generic reset handler is: +MMU turned off, both instruction and data caches turned off and not part +of any coherency domain. + +The BL entrypoint code first invokes the `plat_reset_handler()` to allow +the platform to perform any system initialization required and any system +errata workarounds that needs to be applied. The `get_cpu_ops_ptr()` reads +the current CPU midr, finds the matching `cpu_ops` entry in the `cpu_ops` +array and returns it. Note that only the part number and implementer fields +in midr are used to find the matching `cpu_ops` entry. The `reset_func()` in +the returned `cpu_ops` is then invoked which executes the required reset +handling for that CPU and also any errata workarounds enabled by the platform. +This function must preserve the values of general purpose registers x20 to x29. + +Refer to Section "Guidelines for Reset Handlers" for general guidelines +regarding placement of code in a reset handler. + +### CPU specific power down sequence + +During the BL31 initialization sequence, the pointer to the matching `cpu_ops` +entry is stored in per-CPU data by `init_cpu_ops()` so that it can be quickly +retrieved during power down sequences. + +The PSCI service, upon receiving a power down request, determines the highest +power level at which to execute power down sequence for a particular CPU and +invokes the corresponding 'prepare' power down handler in the CPU specific +operations framework. For example, when a CPU executes a power down for power +level 0, the `prepare_core_pwr_dwn()` retrieves the `cpu_ops` pointer from the +per-CPU data and the corresponding `core_pwr_dwn()` is invoked. Similarly when +a CPU executes power down at power level 1, the `prepare_cluster_pwr_dwn()` +retrieves the `cpu_ops` pointer and the corresponding `cluster_pwr_dwn()` is +invoked. + +At runtime the platform hooks for power down are invoked by the PSCI service to +perform platform specific operations during a power down sequence, for example +turning off CCI coherency during a cluster power down. + +### CPU specific register reporting during crash + +If the crash reporting is enabled in BL31, when a crash occurs, the crash +reporting framework calls `do_cpu_reg_dump` which retrieves the matching +`cpu_ops` using `get_cpu_ops_ptr()` function. The `cpu_reg_dump()` in +`cpu_ops` is invoked, which then returns the CPU specific register values to +be reported and a pointer to the ASCII list of register names in a format +expected by the crash reporting framework. + + +9. Memory layout of BL images +----------------------------- + +Each bootloader image can be divided in 2 parts: + + * the static contents of the image. These are data actually stored in the + binary on the disk. In the ELF terminology, they are called `PROGBITS` + sections; + + * the run-time contents of the image. These are data that don't occupy any + space in the binary on the disk. The ELF binary just contains some + metadata indicating where these data will be stored at run-time and the + corresponding sections need to be allocated and initialized at run-time. + In the ELF terminology, they are called `NOBITS` sections. + +All PROGBITS sections are grouped together at the beginning of the image, +followed by all NOBITS sections. This is true for all Trusted Firmware images +and it is governed by the linker scripts. This ensures that the raw binary +images are as small as possible. If a NOBITS section was inserted in between +PROGBITS sections then the resulting binary file would contain zero bytes in +place of this NOBITS section, making the image unnecessarily bigger. Smaller +images allow faster loading from the FIP to the main memory. + +### Linker scripts and symbols + +Each bootloader stage image layout is described by its own linker script. The +linker scripts export some symbols into the program symbol table. Their values +correspond to particular addresses. The trusted firmware code can refer to these +symbols to figure out the image memory layout. + +Linker symbols follow the following naming convention in the trusted firmware. + +* `__

_START__` + + Start address of a given section named `
`. + +* `__
_END__` + + End address of a given section named `
`. If there is an alignment + constraint on the section's end address then `__
_END__` corresponds + to the end address of the section's actual contents, rounded up to the right + boundary. Refer to the value of `__
_UNALIGNED_END__` to know the + actual end address of the section's contents. + +* `__
_UNALIGNED_END__` + + End address of a given section named `
` without any padding or + rounding up due to some alignment constraint. + +* `__
_SIZE__` + + Size (in bytes) of a given section named `
`. If there is an + alignment constraint on the section's end address then `__
_SIZE__` + corresponds to the size of the section's actual contents, rounded up to the + right boundary. In other words, `__
_SIZE__ = __
_END__ - + _
_START__`. Refer to the value of `__
_UNALIGNED_SIZE__` + to know the actual size of the section's contents. + +* `__
_UNALIGNED_SIZE__` + + Size (in bytes) of a given section named `
` without any padding or + rounding up due to some alignment constraint. In other words, + `__
_UNALIGNED_SIZE__ = __
_UNALIGNED_END__ - + __
_START__`. + +Some of the linker symbols are mandatory as the trusted firmware code relies on +them to be defined. They are listed in the following subsections. Some of them +must be provided for each bootloader stage and some are specific to a given +bootloader stage. + +The linker scripts define some extra, optional symbols. They are not actually +used by any code but they help in understanding the bootloader images' memory +layout as they are easy to spot in the link map files. + +#### Common linker symbols + +All BL images share the following requirements: + +* The BSS section must be zero-initialised before executing any C code. +* The coherent memory section (if enabled) must be zero-initialised as well. +* The MMU setup code needs to know the extents of the coherent and read-only + memory regions to set the right memory attributes. When + `SEPARATE_CODE_AND_RODATA=1`, it needs to know more specifically how the + read-only memory region is divided between code and data. + +The following linker symbols are defined for this purpose: + +* `__BSS_START__` Must be aligned on a 16-byte boundary. +* `__BSS_SIZE__` +* `__COHERENT_RAM_START__` Must be aligned on a page-size boundary. +* `__COHERENT_RAM_END__` Must be aligned on a page-size boundary. +* `__COHERENT_RAM_UNALIGNED_SIZE__` +* `__RO_START__` +* `__RO_END__` +* `__TEXT_START__` +* `__TEXT_END__` +* `__RODATA_START__` +* `__RODATA_END__` + +#### BL1's linker symbols + +BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and +it is entirely executed in place but it needs some read-write memory for its +mutable data. Its `.data` section (i.e. its allocated read-write data) must be +relocated from ROM to RAM before executing any C code. + +The following additional linker symbols are defined for BL1: + +* `__BL1_ROM_END__` End address of BL1's ROM contents, covering its code + and `.data` section in ROM. +* `__DATA_ROM_START__` Start address of the `.data` section in ROM. Must be + aligned on a 16-byte boundary. +* `__DATA_RAM_START__` Address in RAM where the `.data` section should be + copied over. Must be aligned on a 16-byte boundary. +* `__DATA_SIZE__` Size of the `.data` section (in ROM or RAM). +* `__BL1_RAM_START__` Start address of BL1 read-write data. +* `__BL1_RAM_END__` End address of BL1 read-write data. + + +### How to choose the right base addresses for each bootloader stage image + +There is currently no support for dynamic image loading in the Trusted Firmware. +This means that all bootloader images need to be linked against their ultimate +runtime locations and the base addresses of each image must be chosen carefully +such that images don't overlap each other in an undesired way. As the code +grows, the base addresses might need adjustments to cope with the new memory +layout. + +The memory layout is completely specific to the platform and so there is no +general recipe for choosing the right base addresses for each bootloader image. +However, there are tools to aid in understanding the memory layout. These are +the link map files: `build///bl/bl.map`, with `` +being the stage bootloader. They provide a detailed view of the memory usage of +each image. Among other useful information, they provide the end address of +each image. + +* `bl1.map` link map file provides `__BL1_RAM_END__` address. +* `bl2.map` link map file provides `__BL2_END__` address. +* `bl31.map` link map file provides `__BL31_END__` address. +* `bl32.map` link map file provides `__BL32_END__` address. + +For each bootloader image, the platform code must provide its start address +as well as a limit address that it must not overstep. The latter is used in the +linker scripts to check that the image doesn't grow past that address. If that +happens, the linker will issue a message similar to the following: + + aarch64-none-elf-ld: BLx has exceeded its limit. + +Additionally, if the platform memory layout implies some image overlaying like +on FVP, BL31 and TSP need to know the limit address that their PROGBITS +sections must not overstep. The platform code must provide those. + +When LOAD_IMAGE_V2 is disabled, Trusted Firmware provides a mechanism to +verify at boot time that the memory to load a new image is free to prevent +overwriting a previously loaded image. For this mechanism to work, the platform +must specify the memory available in the system as regions, where each region +consists of base address, total size and the free area within it (as defined +in the `meminfo_t` structure). Trusted Firmware retrieves these memory regions +by calling the corresponding platform API: + +* `meminfo_t *bl1_plat_sec_mem_layout(void)` +* `meminfo_t *bl2_plat_sec_mem_layout(void)` +* `void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)` +* `void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)` +* `void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)` + +For example, in the case of BL1 loading BL2, `bl1_plat_sec_mem_layout()` will +return the region defined by the platform where BL1 intends to load BL2. The +`load_image()` function will check that the memory where BL2 will be loaded is +within the specified region and marked as free. + +The actual number of regions and their base addresses and sizes is platform +specific. The platform may return the same region or define a different one for +each API. However, the overlap verification mechanism applies only to a single +region. Hence, it is the platform responsibility to guarantee that different +regions do not overlap, or that if they do, the overlapping images are not +accessed at the same time. This could be used, for example, to load temporary +images (e.g. certificates) or firmware images prior to being transfered to its +corresponding processor (e.g. the SCP BL2 image). + +To reduce fragmentation and simplify the tracking of free memory, all the free +memory within a region is always located in one single buffer defined by its +base address and size. Trusted Firmware implements a top/bottom load approach: +after a new image is loaded, it checks how much memory remains free above and +below the image. The smallest area is marked as unavailable, while the larger +area becomes the new free memory buffer. Platforms should take this behaviour +into account when defining the base address for each of the images. For example, +if an image is loaded near the middle of the region, small changes in image size +could cause a flip between a top load and a bottom load, which may result in an +unexpected memory layout. + +The following diagram is an example of an image loaded in the bottom part of +the memory region. The region is initially free (nothing has been loaded yet): + + Memory region + +----------+ + | | + | | <<<<<<<<<<<<< Free + | | + |----------| +------------+ + | image | <<<<<<<<<<<<< | image | + |----------| +------------+ + | xxxxxxxx | <<<<<<<<<<<<< Marked as unavailable + +----------+ + +And the following diagram is an example of an image loaded in the top part: + + Memory region + +----------+ + | xxxxxxxx | <<<<<<<<<<<<< Marked as unavailable + |----------| +------------+ + | image | <<<<<<<<<<<<< | image | + |----------| +------------+ + | | + | | <<<<<<<<<<<<< Free + | | + +----------+ + + +When LOAD_IMAGE_V2 is enabled, Trusted Firmware does not provide any mechanism +to verify at boot time that the memory to load a new image is free to prevent +overwriting a previously loaded image. The platform must specify the memory +available in the system for all the relevant BL images to be loaded. + +For example, in the case of BL1 loading BL2, `bl1_plat_sec_mem_layout()` will +return the region defined by the platform where BL1 intends to load BL2. The +`load_image()` function performs bounds check for the image size based on the +base and maximum image size provided by the platforms. Platforms must take +this behaviour into account when defining the base/size for each of the images. + +#### Memory layout on ARM development platforms + +The following list describes the memory layout on the ARM development platforms: + +* A 4KB page of shared memory is used for communication between Trusted + Firmware and the platform's power controller. This is located at the base of + Trusted SRAM. The amount of Trusted SRAM available to load the bootloader + images is reduced by the size of the shared memory. + + The shared memory is used to store the CPUs' entrypoint mailbox. On Juno, + this is also used for the MHU payload when passing messages to and from the + SCP. + +* On FVP, BL1 is originally sitting in the Trusted ROM at address `0x0`. On + Juno, BL1 resides in flash memory at address `0x0BEC0000`. BL1 read-write + data are relocated to the top of Trusted SRAM at runtime. + +* EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN), + is loaded at the top of the Trusted SRAM, such that its NOBITS sections will + overwrite BL1 R/W data. This implies that BL1 global variables remain valid + only until execution reaches the EL3 Runtime Software entry point during a + cold boot. + +* BL2 is loaded below EL3 Runtime Software. + +* On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory + region and transfered to the SCP before being overwritten by EL3 Runtime + Software. + +* BL32 (for AArch64) can be loaded in one of the following locations: + + * Trusted SRAM + * Trusted DRAM (FVP only) + * Secure region of DRAM (top 16MB of DRAM configured by the TrustZone + controller) + + When BL32 (for AArch64) is loaded into Trusted SRAM, its NOBITS sections + are allowed to overlay BL2. This memory layout is designed to give the + BL32 image as much memory as possible when it is loaded into Trusted SRAM. + +When LOAD_IMAGE_V2 is disabled the memory regions for the overlap detection +mechanism at boot time are defined as follows (shown per API): + +* `meminfo_t *bl1_plat_sec_mem_layout(void)` + + This region corresponds to the whole Trusted SRAM except for the shared + memory at the base. This region is initially free. At boot time, BL1 will + mark the BL1(rw) section within this region as occupied. The BL1(rw) section + is placed at the top of Trusted SRAM. + +* `meminfo_t *bl2_plat_sec_mem_layout(void)` + + This region corresponds to the whole Trusted SRAM as defined by + `bl1_plat_sec_mem_layout()`, but with the BL1(rw) section marked as + occupied. This memory region is used to check that BL2 and BL31 do not + overlap with each other. BL2_BASE and BL1_RW_BASE are carefully chosen so + that the memory for BL31 is top loaded above BL2. + +* `void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)` + + This region is an exact copy of the region defined by + `bl2_plat_sec_mem_layout()`. Being a disconnected copy means that all the + changes made to this region by the Trusted Firmware will not be propagated. + This approach is valid because the SCP BL2 image is loaded temporarily + while it is being transferred to the SCP, so this memory is reused + afterwards. + +* `void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)` + + This region depends on the location of the BL32 image. Currently, ARM + platforms support three different locations (detailed below): Trusted SRAM, + Trusted DRAM and the TZC-Secured DRAM. + +* `void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)` + + This region corresponds to the Non-Secure DDR-DRAM, excluding the + TZC-Secured area. + +The location of the BL32 image will result in different memory maps. This is +illustrated for both FVP and Juno in the following diagrams, using the TSP as +an example. + +Note: Loading the BL32 image in TZC secured DRAM doesn't change the memory +layout of the other images in Trusted SRAM. + +**FVP with TSP in Trusted SRAM (default option):** +(These diagrams only cover the AArch64 case) + + Trusted SRAM + 0x04040000 +----------+ loaded by BL2 ------------------ + | BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS | + |----------| <<<<<<<<<<<<< |----------------| + | | <<<<<<<<<<<<< | BL31 PROGBITS | + |----------| ------------------ + | BL2 | <<<<<<<<<<<<< | BL32 NOBITS | + |----------| <<<<<<<<<<<<< |----------------| + | | <<<<<<<<<<<<< | BL32 PROGBITS | + 0x04001000 +----------+ ------------------ + | Shared | + 0x04000000 +----------+ + + Trusted ROM + 0x04000000 +----------+ + | BL1 (ro) | + 0x00000000 +----------+ + + +**FVP with TSP in Trusted DRAM:** + + Trusted DRAM + 0x08000000 +----------+ + | BL32 | + 0x06000000 +----------+ + + Trusted SRAM + 0x04040000 +----------+ loaded by BL2 ------------------ + | BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS | + |----------| <<<<<<<<<<<<< |----------------| + | | <<<<<<<<<<<<< | BL31 PROGBITS | + |----------| ------------------ + | BL2 | + |----------| + | | + 0x04001000 +----------+ + | Shared | + 0x04000000 +----------+ + + Trusted ROM + 0x04000000 +----------+ + | BL1 (ro) | + 0x00000000 +----------+ + +**FVP with TSP in TZC-Secured DRAM:** + + DRAM + 0xffffffff +----------+ + | BL32 | (secure) + 0xff000000 +----------+ + | | + : : (non-secure) + | | + 0x80000000 +----------+ + + Trusted SRAM + 0x04040000 +----------+ loaded by BL2 ------------------ + | BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS | + |----------| <<<<<<<<<<<<< |----------------| + | | <<<<<<<<<<<<< | BL31 PROGBITS | + |----------| ------------------ + | BL2 | + |----------| + | | + 0x04001000 +----------+ + | Shared | + 0x04000000 +----------+ + + Trusted ROM + 0x04000000 +----------+ + | BL1 (ro) | + 0x00000000 +----------+ + + +**Juno with BL32 in Trusted SRAM (default option):** + + Flash0 + 0x0C000000 +----------+ + : : + 0x0BED0000 |----------| + | BL1 (ro) | + 0x0BEC0000 |----------| + : : + 0x08000000 +----------+ BL31 is loaded + after SCP_BL2 has + Trusted SRAM been sent to SCP + 0x04040000 +----------+ loaded by BL2 ------------------ + | BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS | + |----------| <<<<<<<<<<<<< |----------------| + | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | + |----------| ------------------ + | BL2 | <<<<<<<<<<<<< | BL32 NOBITS | + |----------| <<<<<<<<<<<<< |----------------| + | | <<<<<<<<<<<<< | BL32 PROGBITS | + 0x04001000 +----------+ ------------------ + | MHU | + 0x04000000 +----------+ + + +**Juno with BL32 in TZC-secured DRAM:** + + DRAM + 0xFFE00000 +----------+ + | BL32 | (secure) + 0xFF000000 |----------| + | | + : : (non-secure) + | | + 0x80000000 +----------+ + + Flash0 + 0x0C000000 +----------+ + : : + 0x0BED0000 |----------| + | BL1 (ro) | + 0x0BEC0000 |----------| + : : + 0x08000000 +----------+ BL31 is loaded + after SCP_BL2 has + Trusted SRAM been sent to SCP + 0x04040000 +----------+ loaded by BL2 ------------------ + | BL1 (rw) | <<<<<<<<<<<<< | BL31 NOBITS | + |----------| <<<<<<<<<<<<< |----------------| + | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS | + |----------| ------------------ + | BL2 | + |----------| + | | + 0x04001000 +----------+ + | MHU | + 0x04000000 +----------+ + + +10. Firmware Image Package (FIP) +--------------------------------- + +Using a Firmware Image Package (FIP) allows for packing bootloader images (and +potentially other payloads) into a single archive that can be loaded by the ARM +Trusted Firmware from non-volatile platform storage. A driver to load images +from a FIP has been added to the storage layer and allows a package to be read +from supported platform storage. A tool to create Firmware Image Packages is +also provided and described below. + +### Firmware Image Package layout + +The FIP layout consists of a table of contents (ToC) followed by payload data. +The ToC itself has a header followed by one or more table entries. The ToC is +terminated by an end marker entry. All ToC entries describe some payload data +that has been appended to the end of the binary package. With the information +provided in the ToC entry the corresponding payload data can be retrieved. + + ------------------ + | ToC Header | + |----------------| + | ToC Entry 0 | + |----------------| + | ToC Entry 1 | + |----------------| + | ToC End Marker | + |----------------| + | | + | Data 0 | + | | + |----------------| + | | + | Data 1 | + | | + ------------------ + +The ToC header and entry formats are described in the header file +`include/firmware_image_package.h`. This file is used by both the tool and the +ARM Trusted firmware. + +The ToC header has the following fields: + + `name`: The name of the ToC. This is currently used to validate the header. + `serial_number`: A non-zero number provided by the creation tool + `flags`: Flags associated with this data. + Bits 0-13: Reserved + Bits 32-47: Platform defined + Bits 48-63: Reserved + +A ToC entry has the following fields: + + `uuid`: All files are referred to by a pre-defined Universally Unique + IDentifier [UUID] . The UUIDs are defined in + `include/firmware_image_package`. The platform translates the requested + image name into the corresponding UUID when accessing the package. + `offset_address`: The offset address at which the corresponding payload data + can be found. The offset is calculated from the ToC base address. + `size`: The size of the corresponding payload data in bytes. + `flags`: Flags associated with this entry. Non are yet defined. + +### Firmware Image Package creation tool + +The FIP creation tool can be used to pack specified images into a binary package +that can be loaded by the ARM Trusted Firmware from platform storage. The tool +currently only supports packing bootloader images. Additional image definitions +can be added to the tool as required. + +The tool can be found in `tools/fiptool`. + +### Loading from a Firmware Image Package (FIP) + +The Firmware Image Package (FIP) driver can load images from a binary package on +non-volatile platform storage. For the ARM development platforms, this is +currently NOR FLASH. + +Bootloader images are loaded according to the platform policy as specified by +the function `plat_get_image_source()`. For the ARM development platforms, this +means the platform will attempt to load images from a Firmware Image Package +located at the start of NOR FLASH0. + +The ARM development platforms' policy is to only allow loading of a known set of +images. The platform policy can be modified to allow additional images. + + +11. Use of coherent memory in Trusted Firmware +----------------------------------------------- + +There might be loss of coherency when physical memory with mismatched +shareability, cacheability and memory attributes is accessed by multiple CPUs +(refer to section B2.9 of [ARM ARM] for more details). This possibility occurs +in Trusted Firmware during power up/down sequences when coherency, MMU and +caches are turned on/off incrementally. + +Trusted Firmware defines coherent memory as a region of memory with Device +nGnRE attributes in the translation tables. The translation granule size in +Trusted Firmware is 4KB. This is the smallest possible size of the coherent +memory region. + +By default, all data structures which are susceptible to accesses with +mismatched attributes from various CPUs are allocated in a coherent memory +region (refer to section 2.1 of [Porting Guide]). The coherent memory region +accesses are Outer Shareable, non-cacheable and they can be accessed +with the Device nGnRE attributes when the MMU is turned on. Hence, at the +expense of at least an extra page of memory, Trusted Firmware is able to work +around coherency issues due to mismatched memory attributes. + +The alternative to the above approach is to allocate the susceptible data +structures in Normal WriteBack WriteAllocate Inner shareable memory. This +approach requires the data structures to be designed so that it is possible to +work around the issue of mismatched memory attributes by performing software +cache maintenance on them. + +### Disabling the use of coherent memory in Trusted Firmware + +It might be desirable to avoid the cost of allocating coherent memory on +platforms which are memory constrained. Trusted Firmware enables inclusion of +coherent memory in firmware images through the build flag `USE_COHERENT_MEM`. +This flag is enabled by default. It can be disabled to choose the second +approach described above. + +The below sections analyze the data structures allocated in the coherent memory +region and the changes required to allocate them in normal memory. + +### Coherent memory usage in PSCI implementation + +The `psci_non_cpu_pd_nodes` data structure stores the platform's power domain +tree information for state management of power domains. By default, this data +structure is allocated in the coherent memory region in the Trusted Firmware +because it can be accessed by multple CPUs, either with caches enabled or +disabled. + + typedef struct non_cpu_pwr_domain_node { + /* + * Index of the first CPU power domain node level 0 which has this node + * as its parent. + */ + unsigned int cpu_start_idx; + + /* + * Number of CPU power domains which are siblings of the domain indexed + * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx + * -> cpu_start_idx + ncpus' have this node as their parent. + */ + unsigned int ncpus; + + /* + * Index of the parent power domain node. + * TODO: Figure out whether to whether using pointer is more efficient. + */ + unsigned int parent_node; + + plat_local_state_t local_state; + + unsigned char level; + + /* For indexing the psci_lock array*/ + unsigned char lock_index; + } non_cpu_pd_node_t; + +In order to move this data structure to normal memory, the use of each of its +fields must be analyzed. Fields like `cpu_start_idx`, `ncpus`, `parent_node` +`level` and `lock_index` are only written once during cold boot. Hence removing +them from coherent memory involves only doing a clean and invalidate of the +cache lines after these fields are written. + +The field `local_state` can be concurrently accessed by multiple CPUs in +different cache states. A Lamport's Bakery lock `psci_locks` is used to ensure +mutual exlusion to this field and a clean and invalidate is needed after it +is written. + +### Bakery lock data + +The bakery lock data structure `bakery_lock_t` is allocated in coherent memory +and is accessed by multiple CPUs with mismatched attributes. `bakery_lock_t` is +defined as follows: + + typedef struct bakery_lock { + /* + * The lock_data is a bit-field of 2 members: + * Bit[0] : choosing. This field is set when the CPU is + * choosing its bakery number. + * Bits[1 - 15] : number. This is the bakery number allocated. + */ + volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; + } bakery_lock_t; + +It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU +fields can be read by all CPUs but only written to by the owning CPU. + +Depending upon the data cache line size, the per-CPU fields of the +`bakery_lock_t` structure for multiple CPUs may exist on a single cache line. +These per-CPU fields can be read and written during lock contention by multiple +CPUs with mismatched memory attributes. Since these fields are a part of the +lock implementation, they do not have access to any other locking primitive to +safeguard against the resulting coherency issues. As a result, simple software +cache maintenance is not enough to allocate them in coherent memory. Consider +the following example. + +CPU0 updates its per-CPU field with data cache enabled. This write updates a +local cache line which contains a copy of the fields for other CPUs as well. Now +CPU1 updates its per-CPU field of the `bakery_lock_t` structure with data cache +disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of +its field in any other cache line in the system. This operation will invalidate +the update made by CPU0 as well. + +To use bakery locks when `USE_COHERENT_MEM` is disabled, the lock data structure +has been redesigned. The changes utilise the characteristic of Lamport's Bakery +algorithm mentioned earlier. The bakery_lock structure only allocates the memory +for a single CPU. The macro `DEFINE_BAKERY_LOCK` allocates all the bakery locks +needed for a CPU into a section `bakery_lock`. The linker allocates the memory +for other cores by using the total size allocated for the bakery_lock section +and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to +perform software cache maintenance on the lock data structure without running +into coherency issues associated with mismatched attributes. + +The bakery lock data structure `bakery_info_t` is defined for use when +`USE_COHERENT_MEM` is disabled as follows: + + typedef struct bakery_info { + /* + * The lock_data is a bit-field of 2 members: + * Bit[0] : choosing. This field is set when the CPU is + * choosing its bakery number. + * Bits[1 - 15] : number. This is the bakery number allocated. + */ + volatile uint16_t lock_data; + } bakery_info_t; + +The `bakery_info_t` represents a single per-CPU field of one lock and +the combination of corresponding `bakery_info_t` structures for all CPUs in the +system represents the complete bakery lock. The view in memory for a system +with n bakery locks are: + + bakery_lock section start + |----------------| + | `bakery_info_t`| <-- Lock_0 per-CPU field + | Lock_0 | for CPU0 + |----------------| + | `bakery_info_t`| <-- Lock_1 per-CPU field + | Lock_1 | for CPU0 + |----------------| + | .... | + |----------------| + | `bakery_info_t`| <-- Lock_N per-CPU field + | Lock_N | for CPU0 + ------------------ + | XXXXX | + | Padding to | + | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate + | Granule | continuous memory for remaining CPUs. + ------------------ + | `bakery_info_t`| <-- Lock_0 per-CPU field + | Lock_0 | for CPU1 + |----------------| + | `bakery_info_t`| <-- Lock_1 per-CPU field + | Lock_1 | for CPU1 + |----------------| + | .... | + |----------------| + | `bakery_info_t`| <-- Lock_N per-CPU field + | Lock_N | for CPU1 + ------------------ + | XXXXX | + | Padding to | + | next Cache WB | + | Granule | + ------------------ + +Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an +operation on Lock_N, the corresponding `bakery_info_t` in both CPU0 and CPU1 +`bakery_lock` section need to be fetched and appropriate cache operations need +to be performed for each access. + +On ARM Platforms, bakery locks are used in psci (`psci_locks`) and power controller +driver (`arm_lock`). + + +### Non Functional Impact of removing coherent memory + +Removal of the coherent memory region leads to the additional software overhead +of performing cache maintenance for the affected data structures. However, since +the memory where the data structures are allocated is cacheable, the overhead is +mostly mitigated by an increase in performance. + +There is however a performance impact for bakery locks, due to: +* Additional cache maintenance operations, and +* Multiple cache line reads for each lock operation, since the bakery locks + for each CPU are distributed across different cache lines. + +The implementation has been optimized to minimize this additional overhead. +Measurements indicate that when bakery locks are allocated in Normal memory, the +minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas +in Device memory the same is 2 micro seconds. The measurements were done on the +Juno ARM development platform. + +As mentioned earlier, almost a page of memory can be saved by disabling +`USE_COHERENT_MEM`. Each platform needs to consider these trade-offs to decide +whether coherent memory should be used. If a platform disables +`USE_COHERENT_MEM` and needs to use bakery locks in the porting layer, it can +optionally define macro `PLAT_PERCPU_BAKERY_LOCK_SIZE` (see the [Porting +Guide]). Refer to the reference platform code for examples. + + +12. Isolating code and read-only data on separate memory pages +--------------------------------------------------------------- + +In the ARMv8 VMSA, translation table entries include fields that define the +properties of the target memory region, such as its access permissions. The +smallest unit of memory that can be addressed by a translation table entry is +a memory page. Therefore, if software needs to set different permissions on two +memory regions then it needs to map them using different memory pages. + +The default memory layout for each BL image is as follows: + + | ... | + +-------------------+ + | Read-write data | + +-------------------+ Page boundary + | | + +-------------------+ + | Exception vectors | + +-------------------+ 2 KB boundary + | | + +-------------------+ + | Read-only data | + +-------------------+ + | Code | + +-------------------+ BLx_BASE + +Note: The 2KB alignment for the exception vectors is an architectural +requirement. + +The read-write data start on a new memory page so that they can be mapped with +read-write permissions, whereas the code and read-only data below are configured +as read-only. + +However, the read-only data are not aligned on a page boundary. They are +contiguous to the code. Therefore, the end of the code section and the beginning +of the read-only data one might share a memory page. This forces both to be +mapped with the same memory attributes. As the code needs to be executable, this +means that the read-only data stored on the same memory page as the code are +executable as well. This could potentially be exploited as part of a security +attack. + +TF provides the build flag `SEPARATE_CODE_AND_RODATA` to isolate the code and +read-only data on separate memory pages. This in turn allows independent control +of the access permissions for the code and read-only data. In this case, +platform code gets a finer-grained view of the image layout and can +appropriately map the code region as executable and the read-only data as +execute-never. + +This has an impact on memory footprint, as padding bytes need to be introduced +between the code and read-only data to ensure the segragation of the two. To +limit the memory cost, this flag also changes the memory layout such that the +code and exception vectors are now contiguous, like so: + + | ... | + +-------------------+ + | Read-write data | + +-------------------+ Page boundary + | | + +-------------------+ + | Read-only data | + +-------------------+ Page boundary + | | + +-------------------+ + | Exception vectors | + +-------------------+ 2 KB boundary + | | + +-------------------+ + | Code | + +-------------------+ BLx_BASE + +With this more condensed memory layout, the separation of read-only data will +add zero or one page to the memory footprint of each BL image. Each platform +should consider the trade-off between memory footprint and security. + +This build flag is disabled by default, minimising memory footprint. On ARM +platforms, it is enabled. + + +13. Performance Measurement Framework +-------------------------------------- + +The Performance Measurement Framework (PMF) facilitates collection of +timestamps by registered services and provides interfaces to retrieve +them from within the ARM Trusted Firmware. A platform can choose to +expose appropriate SMCs to retrieve these collected timestamps. + +By default, the global physical counter is used for the timestamp +value and is read via `CNTPCT_EL0`. The framework allows to retrieve +timestamps captured by other CPUs. + +### Timestamp identifier format + +A PMF timestamp is uniquely identified across the system via the +timestamp ID or `tid`. The `tid` is composed as follows: + + Bits 0-7: The local timestamp identifier. + Bits 8-9: Reserved. + Bits 10-15: The service identifier. + Bits 16-31: Reserved. + +1. The service identifier. Each PMF service is identified by a + service name and a service identifier. Both the service name and + identifier are unique within the system as a whole. + +2. The local timestamp identifier. This identifier is unique within a given + service. + +### Registering a PMF service + +To register a PMF service, the `PMF_REGISTER_SERVICE()` macro from `pmf.h` +is used. The arguments required are the service name, the service ID, +the total number of local timestamps to be captured and a set of flags. + +The `flags` field can be specified as a bitwise-OR of the following values: + + PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval. + PMF_DUMP_ENABLE: The timestamp is dumped on the serial console. + +The `PMF_REGISTER_SERVICE()` reserves memory to store captured +timestamps in a PMF specific linker section at build time. +Additionally, it defines necessary functions to capture and +retrieve a particular timestamp for the given service at runtime. + +The macro `PMF_REGISTER_SERVICE()` only enables capturing PMF +timestamps from within ARM Trusted Firmware. In order to retrieve +timestamps from outside of ARM Trusted Firmware, the +`PMF_REGISTER_SERVICE_SMC()` macro must be used instead. This macro +accepts the same set of arguments as the `PMF_REGISTER_SERVICE()` +macro but additionally supports retrieving timestamps using SMCs. + +### Capturing a timestamp + +PMF timestamps are stored in a per-service timestamp region. On a +system with multiple CPUs, each timestamp is captured and stored +in a per-CPU cache line aligned memory region. + +Having registered the service, the `PMF_CAPTURE_TIMESTAMP()` macro can be +used to capture a timestamp at the location where it is used. The macro +takes the service name, a local timestamp identifier and a flag as arguments. + +The `flags` field argument can be zero, or `PMF_CACHE_MAINT` which +instructs PMF to do cache maintenance following the capture. Cache +maintenance is required if any of the service's timestamps are captured +with data cache disabled. + +To capture a timestamp in assembly code, the caller should use +`pmf_calc_timestamp_addr` macro (defined in `pmf_asm_macros.S`) to +calculate the address of where the timestamp would be stored. The +caller should then read `CNTPCT_EL0` register to obtain the timestamp +and store it at the determined address for later retrieval. + +### Retrieving a timestamp + +From within ARM Trusted Firmware, timestamps for individual CPUs can +be retrieved using either `PMF_GET_TIMESTAMP_BY_MPIDR()` or +`PMF_GET_TIMESTAMP_BY_INDEX()` macros. These macros accept the CPU's MPIDR +value, or its ordinal position, respectively. + +From outside ARM Trusted Firmware, timestamps for individual CPUs can be +retrieved by calling into `pmf_smc_handler()`. + + Interface : pmf_smc_handler() + Argument : unsigned int smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3, + u_register_t x4, void *cookie, + void *handle, u_register_t flags + Return : uintptr_t + + smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32` + when the caller of the SMC is running in AArch32 mode + or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode. + x1: Timestamp identifier. + x2: The `mpidr` of the CPU for which the timestamp has to be retrieved. + This can be the `mpidr` of a different core to the one initiating + the SMC. In that case, service specific cache maintenance may be + required to ensure the updated copy of the timestamp is returned. + x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If + `PMF_CACHE_MAINT` is passed, then the PMF code will perform a + cache invalidate before reading the timestamp. This ensures + an updated copy is returned. + +The remaining arguments, `x4`, `cookie`, `handle` and `flags` are unused +in this implementation. + +### PMF code structure + +1. `pmf_main.c` consists of core functions that implement service registration, + initialization, storing, dumping and retrieving timestamps. + +2. `pmf_smc.c` contains the SMC handling for registered PMF services. + +3. `pmf.h` contains the public interface to Performance Measurement Framework. + +4. `pmf_asm_macros.S` consists of macros to facilitate capturing timestamps in + assembly code. + +5. `pmf_helpers.h` is an internal header used by `pmf.h`. + + +14. Code Structure +------------------- + +Trusted Firmware code is logically divided between the three boot loader +stages mentioned in the previous sections. The code is also divided into the +following categories (present as directories in the source code): + +* **Platform specific.** Choice of architecture specific code depends upon + the platform. +* **Common code.** This is platform and architecture agnostic code. +* **Library code.** This code comprises of functionality commonly used by all + other code. The PSCI implementation and other EL3 runtime frameworks reside + as Library components. +* **Stage specific.** Code specific to a boot stage. +* **Drivers.** +* **Services.** EL3 runtime services (eg: SPD). Specific SPD services + reside in the `services/spd` directory (e.g. `services/spd/tspd`). + +Each boot loader stage uses code from one or more of the above mentioned +categories. Based upon the above, the code layout looks like this: + + Directory Used by BL1? Used by BL2? Used by BL31? + bl1 Yes No No + bl2 No Yes No + bl31 No No Yes + plat Yes Yes Yes + drivers Yes No Yes + common Yes Yes Yes + lib Yes Yes Yes + services No No Yes + +The build system provides a non configurable build option IMAGE_BLx for each +boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be +defined by the build system. This enables the Trusted Firmware to compile +certain code only for specific boot loader stages + +All assembler files have the `.S` extension. The linker source files for each +boot stage have the extension `.ld.S`. These are processed by GCC to create the +linker scripts which have the extension `.ld`. + +FDTs provide a description of the hardware platform and are used by the Linux +kernel at boot time. These can be found in the `fdts` directory. + + +15. References +--------------- + +1. Trusted Board Boot Requirements CLIENT PDD (ARM DEN 0006B-5). Available + under NDA through your ARM account representative. + +2. [Power State Coordination Interface PDD (ARM DEN 0022B.b)][PSCI]. + +3. [SMC Calling Convention PDD (ARM DEN 0028A)][SMCCC]. + +4. [ARM Trusted Firmware Interrupt Management Design guide][INTRG]. + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._ + +[ARM ARM]: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0487a.e/index.html "ARMv8-A Reference Manual (ARM DDI0487A.E)" +[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)" +[SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)" +[UUID]: https://tools.ietf.org/rfc/rfc4122.txt "A Universally Unique IDentifier (UUID) URN Namespace" +[User Guide]: ./user-guide.md +[Porting Guide]: ./porting-guide.md +[Reset Design]: ./reset-design.md +[INTRG]: ./interrupt-framework-design.md +[CPUBM]: ./cpu-specific-build-macros.md +[Firmware Update]: ./firmware-update.md +[PSCI Lib guide]: ./psci-lib-integration-guide.md diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/firmware-update.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/firmware-update.md new file mode 100644 index 0000000..97df8cf --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/firmware-update.md @@ -0,0 +1,357 @@ +ARM Trusted Firmware - Firmware Update Design Guide +=================================================== + +Contents : + +1. [Introduction](#1--introduction) +2. [FWU Overview](#2--fwu-overview) +3. [Image Identification](#3--image-identification) +4. [FWU State Machine](#4--fwu-state-machine) +5. [BL1 SMC Interface](#5--bl1-smc-interface) + +- - - - - - - - - - - - - - - - - - + +1. Introduction +---------------- + +This document describes the design of the Firmware Update (FWU) feature, which +enables authenticated firmware to update firmware images from external +interfaces such as USB, UART, SD-eMMC, NAND, NOR or Ethernet to SoC Non-Volatile +memories such as NAND Flash, LPPDR2-NVM or any memory determined by the +platform. This feature functions even when the current firmware in the system +is corrupt or missing; it therefore may be used as a recovery mode. It may also +be complemented by other, higher level firmware update software. + +FWU implements a specific part of the Trusted Board Boot Requirements (TBBR) +specification, ARM DEN0006C-1. It should be used in conjunction with the +[Trusted Board Boot] design document, which describes the image authentication +parts of the Trusted Firmware (TF) TBBR implementation. + +### Scope + +This document describes the secure world FWU design. It is beyond its scope to +describe how normal world FWU images should operate. To implement normal world +FWU images, please refer to the "Non-Trusted Firmware Updater" requirements in +the TBBR. + + +2. FWU Overview +---------------- + +The FWU boot flow is primarily mediated by BL1. Since BL1 executes in ROM, and +it is usually desirable to minimize the amount of ROM code, the design allows +some parts of FWU to be implemented in other secure and normal world images. +Platform code may choose which parts are implemented in which images but the +general expectation is: + +* BL1 handles: + * Detection and initiation of the FWU boot flow. + * Copying images from non-secure to secure memory + * FWU image authentication + * Context switching between the normal and secure world during the FWU + process. +* Other secure world FWU images handle platform initialization required by + the FWU process. +* Normal world FWU images handle loading of firmware images from external + interfaces to non-secure memory. + +The primary requirements of the FWU feature are: + +1. Export a BL1 SMC interface to interoperate with other FWU images executing + at other Exception Levels. +2. Export a platform interface to provide FWU common code with the information + it needs, and to enable platform specific FWU functionality. See the + [Porting Guide] for details of this interface. + +TF uses abbreviated image terminology for FWU images like for other TF images. +An overview of this terminology can be found [here][TF Image Terminology]. + +The following diagram shows the FWU boot flow for ARM development platforms. +ARM CSS platforms like Juno have a System Control Processor (SCP), and these +use all defined FWU images. Other platforms may use a subset of these. + +![Flow Diagram](diagrams/fwu_flow.png?raw=true) + + +3. Image Identification +------------------------ + +Each FWU image and certificate is identified by a unique ID, defined by the +platform, which BL1 uses to fetch an image descriptor (`image_desc_t`) via a +call to `bl1_plat_get_image_desc()`. The same ID is also used to prepare the +Chain of Trust (Refer to the [Authentication Framework Design][Auth Framework] +for more information). + +The image descriptor includes the following information: + +* Executable or non-executable image. This indicates whether the normal world + is permitted to request execution of a secure world FWU image (after + authentication). Secure world certificates and non-AP images are examples + of non-executable images. +* Secure or non-secure image. This indicates whether the image is + authenticated/executed in secure or non-secure memory. +* Image base address and size. +* Image entry point configuration (an `entry_point_info_t`). +* FWU image state. + +BL1 uses the FWU image descriptors to: + +* Validate the arguments of FWU SMCs +* Manage the state of the FWU process +* Initialize the execution state of the next FWU image. + + +4. FWU State Machine +--------------------- + +BL1 maintains state for each FWU image during FWU execution. FWU images at lower +Exception Levels raise SMCs to invoke FWU functionality in BL1, which causes +BL1 to update its FWU image state. The BL1 image states and valid state +transitions are shown in the diagram below. Note that secure images have a more +complex state machine than non-secure images. + +![FWU state machine](diagrams/fwu_states.png?raw=true) + +The following is a brief description of the supported states: + +* RESET: This is the initial state of every image at the start of FWU. + Authentication failure also leads to this state. A secure + image may yield to this state if it has completed execution. + +* COPYING: This is the state of a secure image while BL1 is copying it + in blocks from non-secure to secure memory. + +* COPIED: This is the state of a secure image when BL1 has completed + copying it to secure memory. + +* AUTHENTICATED: This is the state of an image when BL1 has successfully + authenticated it. + +* EXECUTED: This is the state of a secure, executable image when BL1 has + passed execution control to it. + +* INTERRUPTED: This is the state of a secure, executable image after it has + requested BL1 to resume normal world execution. + + +5. BL1 SMC Interface +--------------------- + +### BL1_SMC_CALL_COUNT + + Arguments: + uint32_t function ID : 0x0 + + Return: + uint32_t + +This SMC returns the number of SMCs supported by BL1. + +### BL1_SMC_UID + + Arguments: + uint32_t function ID : 0x1 + + Return: + UUID : 32 bits in each of w0-w3 (or r0-r3 for AArch32 callers) + +This SMC returns the 128-bit [Universally Unique Identifier][UUID] for the +BL1 SMC service. + +### BL1_SMC_VERSION + + Argument: + uint32_t function ID : 0x3 + + Return: + uint32_t : Bits [31:16] Major Version + Bits [15:0] Minor Version + +This SMC returns the current version of the BL1 SMC service. + +### BL1_SMC_RUN_IMAGE + + Arguments: + uint32_t function ID : 0x4 + entry_point_info_t *ep_info + + Return: + void + + Pre-conditions: + if (normal world caller) synchronous exception + if (ep_info not EL3) synchronous exception + +This SMC passes execution control to an EL3 image described by the provided +`entry_point_info_t` structure. In the normal TF boot flow, BL2 invokes this SMC +for BL1 to pass execution control to BL31. + + +### FWU_SMC_IMAGE_COPY + + Arguments: + uint32_t function ID : 0x10 + unsigned int image_id + uintptr_t image_addr + unsigned int block_size + unsigned int image_size + + Return: + int : 0 (Success) + : -ENOMEM + : -EPERM + + Pre-conditions: + if (image_id is invalid) return -EPERM + if (image_id is non-secure image) return -EPERM + if (image_id state is not (RESET or COPYING)) return -EPERM + if (secure world caller) return -EPERM + if (source block is in secure memory) return -ENOMEM + if (source block is not mapped into BL1) return -ENOMEM + if (image_size > free secure memory) return -ENOMEM + +This SMC copies the secure image indicated by `image_id` into secure memory. The +image may be copied in a single block or multiple blocks. In either case, the +total size of the image must be provided in `image_size` when invoking this SMC +the first time for each image. The `image_addr` and `block_size` specify the +source memory block to copy from. If `block_size` >= the size of the remaining +image to copy, then BL1 completes the copy operation and sets the image state +to COPIED. If there is still more to copy, BL1 sets the image state to COPYING. +When using multiple blocks, the source blocks do not necessarily need to be in +contiguous memory. + +BL1 returns from exception to the normal world caller. + + +### FWU_SMC_IMAGE_AUTH + + Arguments: + uint32_t function ID : 0x11 + unsigned int image_id + uintptr_t image_addr + unsigned int image_size + + Return: + int : 0 (Success) + : -ENOMEM + : -EPERM + : -EAUTH + + Pre-conditions: + if (image_id is invalid) return -EPERM + if (secure world caller) + if (image_id state is not RESET) return -EPERM + if (image_addr/image_size is not mappped into BL1) return -ENOMEM + else // normal world caller + if (image_id is secure image) + if (image_id state is not COPIED) return -EPERM + else // image_id is non-secure image + if (image_id state is not RESET) return -EPERM + if (image_addr/image_size is in secure memory) return -ENOMEM + if (image_addr/image_size not mappped into BL1) return -ENOMEM + +This SMC authenticates the image specified by `image_id`. If the image is in the + RESET state, BL1 authenticates the image in place using the provided +`image_addr` and `image_size`. If the image is a secure image in the COPIED +state, BL1 authenticates the image from the secure memory that BL1 previously +copied the image into. + +BL1 returns from exception to the caller. If authentication succeeds then BL1 +sets the image state to AUTHENTICATED. If authentication fails then BL1 returns +the -EAUTH error and sets the image state back to RESET. + + +### FWU_SMC_IMAGE_EXECUTE + + Arguments: + uint32_t function ID : 0x12 + unsigned int image_id + + Return: + int : 0 (Success) + : -EPERM + + Pre-conditions: + if (image_id is invalid) return -EPERM + if (secure world caller) return -EPERM + if (image_id is non-secure image) return -EPERM + if (image_id is non-executable image) return -EPERM + if (image_id state is not AUTHENTICATED) return -EPERM + +This SMC initiates execution of a previously authenticated image specified by +`image_id`, in the other security world to the caller. The current +implementation only supports normal world callers initiating execution of a +secure world image. + +BL1 saves the normal world caller's context, sets the secure image state to +EXECUTED, and returns from exception to the secure image. + + +### FWU_SMC_IMAGE_RESUME + + Arguments: + uint32_t function ID : 0x13 + register_t image_param + + Return: + register_t : image_param (Success) + : -EPERM + + Pre-conditions: + if (normal world caller and no INTERRUPTED secure image) return -EPERM + +This SMC resumes execution in the other security world while there is a secure +image in the EXECUTED/INTERRUPTED state. + +For normal world callers, BL1 sets the previously interrupted secure image state +to EXECUTED. For secure world callers, BL1 sets the previously executing secure +image state to INTERRUPTED. In either case, BL1 saves the calling world's +context, restores the resuming world's context and returns from exception into +the resuming world. If the call is successful then the caller provided +`image_param` is returned to the resumed world, otherwise an error code is +returned to the caller. + + +### FWU_SMC_SEC_IMAGE_DONE + + Arguments: + uint32_t function ID : 0x14 + + Return: + int : 0 (Success) + : -EPERM + + Pre-conditions: + if (normal world caller) return -EPERM + +This SMC indicates completion of a previously executing secure image. + +BL1 sets the previously executing secure image state to the RESET state, +restores the normal world context and returns from exception into the normal +world. + + +### FWU_SMC_UPDATE_DONE + + Arguments: + uint32_t function ID : 0x15 + register_t client_cookie + + Return: + N/A + +This SMC completes the firmware update process. BL1 calls the platform specific +function `bl1_plat_fwu_done`, passing the optional argument `client_cookie` as +a `void *`. The SMC does not return. + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2015, ARM Limited and Contributors. All rights reserved._ + + +[Porting Guide]: ./porting-guide.md +[Auth Framework]: ./auth-framework.md +[Trusted Board Boot]: ./trusted-board-boot.md +[TF Image Terminology]: https://github.com/ARM-software/arm-trusted-firmware/wiki/Trusted-Firmware-Image-Terminology +[UUID]: https://tools.ietf.org/rfc/rfc4122.txt "A Universally Unique IDentifier (UUID) URN Namespace" diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/interrupt-framework-design.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/interrupt-framework-design.md new file mode 100644 index 0000000..e50d175 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/interrupt-framework-design.md @@ -0,0 +1,991 @@ +ARM Trusted Firmware Interrupt Management Design guide +====================================================== + +Contents : + +1. [Introduction](#1-introduction) + * [Concepts](#11-concepts) + - [Interrupt Types](#111-interrupt-types) + - [Routing Model](#112-routing-model) + - [Valid Routing Models](#113-valid-routing-models) + + [Secure-EL1 Interrupts](#1131-secure-el1-interrupts) + + [Non-secure Interrupts](#1132-non-secure-interrupts) + + [EL3 interrupts](#1133-el3-interrupts) + - [Mapping of Interrupt Type to Signal](#114-mapping-of-interrupt-type-to-signal) + + [Effect of mapping of several interrupt types to one signal](#1141-effect-of-mapping-of-several-interrupt-types-to-one-signal) + - [Assumptions in Interrupt Management Framework](#12-assumptions-in-interrupt-management-framework) + +2. [Interrupt Management](#2-interrupt-management) + * [Software Components](#21-software-components) + * [Interrupt Registration](#22-interrupt-registration) + - [EL3 Runtime Firmware](#221-el3-runtime-firmware) + - [Secure Payload Dispatcher](#222-secure-payload-dispatcher) + + [Test Secure Payload Dispatcher behavior](#2221-test-secure-payload-dispatcher-behavior) + - [Secure Payload](#223-secure-payload) + + [Secure Payload IHF design w.r.t Secure-EL1 interrupts](#2231-secure-payload-ihf-design-wrt-secure-el1-interrupts) + + [Secure Payload IHF design w.r.t Non-secure interrupts](#2232-secure-payload-ihf-design-wrt-non-secure-interrupts) + + [Test Secure Payload behavior](#2233-test-secure-payload-behavior) + * [Interrupt Handling](#23-interrupt-handling) + - [EL3 Runtime Firmware](#231-el3-runtime-firmware) + - [Secure Payload Dispatcher](#232-secure-payload-dispatcher) + + [Interrupt Entry](#2321-interrupt-entry) + + [Interrupt Exit](#2322-interrupt-exit) + + [Test secure payload dispatcher Secure-EL1 interrupt handling](#2323-test-secure-payload-dispatcher-secure-el1-interrupt-handling) + + [Test secure payload dispatcher non-secure interrupt handling](#2324-test-secure-payload-dispatcher-non-secure-interrupt-handling) + - [Secure Payload](#233-secure-payload) + + [Test Secure Payload behavior](#2331-test-secure-payload-behavior) + +3. [Other considerations](#3-other-considerations) + * [Implication of preempted SMC on Non-Secure Software](#31-implication-of-preempted-smc-on-non-secure-software) + + +1. Introduction +---------------- +This document describes the design of the Interrupt management framework in ARM +Trusted Firmware. This section briefly describes the requirements from this +framework. It also briefly explains some concepts and assumptions. They will +help in understanding the implementation of the framework explained in +subsequent sections. + +This framework is responsible for managing interrupts routed to EL3. It also +allows EL3 software to configure the interrupt routing behavior. Its main +objective is to implement the following two requirements. + +1. It should be possible to route interrupts meant to be handled by secure + software (Secure interrupts) to EL3, when execution is in non-secure state + (normal world). The framework should then take care of handing control of + the interrupt to either software in EL3 or Secure-EL1 depending upon the + software configuration and the GIC implementation. This requirement ensures + that secure interrupts are under the control of the secure software with + respect to their delivery and handling without the possibility of + intervention from non-secure software. + +2. It should be possible to route interrupts meant to be handled by + non-secure software (Non-secure interrupts) to the last executed exception + level in the normal world when the execution is in secure world at + exception levels lower than EL3. This could be done with or without the + knowledge of software executing in Secure-EL1/Secure-EL0. The choice of + approach should be governed by the secure software. This requirement + ensures that non-secure software is able to execute in tandem with the + secure software without overriding it. + +### 1.1 Concepts + +#### 1.1.1 Interrupt types +The framework categorises an interrupt to be one of the following depending upon +the exception level(s) it is handled in. + +1. Secure EL1 interrupt. This type of interrupt can be routed to EL3 or + Secure-EL1 depending upon the security state of the current execution + context. It is always handled in Secure-EL1. + +2. Non-secure interrupt. This type of interrupt can be routed to EL3, + Secure-EL1, Non-secure EL1 or EL2 depending upon the security state of the + current execution context. It is always handled in either Non-secure EL1 + or EL2. + +3. EL3 interrupt. This type of interrupt can be routed to EL3 or Secure-EL1 + depending upon the security state of the current execution context. It is + always handled in EL3. + +The following constants define the various interrupt types in the framework +implementation. + + #define INTR_TYPE_S_EL1 0 + #define INTR_TYPE_EL3 1 + #define INTR_TYPE_NS 2 + + +#### 1.1.2 Routing model +A type of interrupt can be either generated as an FIQ or an IRQ. The target +exception level of an interrupt type is configured through the FIQ and IRQ bits +in the Secure Configuration Register at EL3 (`SCR_EL3.FIQ` and `SCR_EL3.IRQ` +bits). When `SCR_EL3.FIQ`=1, FIQs are routed to EL3. Otherwise they are routed +to the First Exception Level (FEL) capable of handling interrupts. When +`SCR_EL3.IRQ`=1, IRQs are routed to EL3. Otherwise they are routed to the +FEL. This register is configured independently by EL3 software for each security +state prior to entry into a lower exception level in that security state. + +A routing model for a type of interrupt (generated as FIQ or IRQ) is defined as +its target exception level for each security state. It is represented by a +single bit for each security state. A value of `0` means that the interrupt +should be routed to the FEL. A value of `1` means that the interrupt should be +routed to EL3. A routing model is applicable only when execution is not in EL3. + +The default routing model for an interrupt type is to route it to the FEL in +either security state. + + +#### 1.1.3 Valid routing models +The framework considers certain routing models for each type of interrupt to be +incorrect as they conflict with the requirements mentioned in Section 1. The +following sub-sections describe all the possible routing models and specify +which ones are valid or invalid. EL3 interrupts are currently supported only +for GIC version 3.0 (ARM GICv3) and only the Secure-EL1 and Non-secure interrupt +types are supported for GIC version 2.0 (ARM GICv2) (See 1.2). The terminology +used in the following sub-sections is explained below. + +1. __CSS__. Current Security State. `0` when secure and `1` when non-secure + +2. __TEL3__. Target Exception Level 3. `0` when targeted to the FEL. `1` when + targeted to EL3. + + +##### 1.1.3.1 Secure-EL1 interrupts + +1. __CSS=0, TEL3=0__. Interrupt is routed to the FEL when execution is in + secure state. This is a valid routing model as secure software is in + control of handling secure interrupts. + +2. __CSS=0, TEL3=1__. Interrupt is routed to EL3 when execution is in secure + state. This is a valid routing model as secure software in EL3 can + handover the interrupt to Secure-EL1 for handling. + +3. __CSS=1, TEL3=0__. Interrupt is routed to the FEL when execution is in + non-secure state. This is an invalid routing model as a secure interrupt + is not visible to the secure software which violates the motivation behind + the ARM Security Extensions. + +4. __CSS=1, TEL3=1__. Interrupt is routed to EL3 when execution is in + non-secure state. This is a valid routing model as secure software in EL3 + can handover the interrupt to Secure-EL1 for handling. + + +##### 1.1.3.2 Non-secure interrupts + +1. __CSS=0, TEL3=0__. Interrupt is routed to the FEL when execution is in + secure state. This allows the secure software to trap non-secure + interrupts, perform its book-keeping and hand the interrupt to the + non-secure software through EL3. This is a valid routing model as secure + software is in control of how its execution is preempted by non-secure + interrupts. + +2. __CSS=0, TEL3=1__. Interrupt is routed to EL3 when execution is in secure + state. This is a valid routing model as secure software in EL3 can save + the state of software in Secure-EL1/Secure-EL0 before handing the + interrupt to non-secure software. This model requires additional + coordination between Secure-EL1 and EL3 software to ensure that the + former's state is correctly saved by the latter. + +3. __CSS=1, TEL3=0__. Interrupt is routed to FEL when execution is in + non-secure state. This is an valid routing model as a non-secure interrupt + is handled by non-secure software. + +4. __CSS=1, TEL3=1__. Interrupt is routed to EL3 when execution is in + non-secure state. This is an invalid routing model as there is no valid + reason to route the interrupt to EL3 software and then hand it back to + non-secure software for handling. + + +##### 1.1.3.3 EL3 interrupts + +1. __CSS=0, TEL3=0__. Interrupt is routed to the FEL when execution is in + Secure-EL1/Secure-EL0. This is a valid routing model as secure software + in Secure-EL1/Secure-EL0 is in control of how its execution is preempted + by EL3 interrupt and can handover the interrupt to EL3 for handling. + +2. __CSS=0, TEL3=1__. Interrupt is routed to EL3 when execution is in + Secure-EL1/Secure-EL0. This is a valid routing model as secure software + in EL3 can handle the interrupt. + +3. __CSS=1, TEL3=0__. Interrupt is routed to the FEL when execution is in + non-secure state. This is an invalid routing model as a secure interrupt + is not visible to the secure software which violates the motivation behind + the ARM Security Extensions. + +4. __CSS=1, TEL3=1__. Interrupt is routed to EL3 when execution is in + non-secure state. This is a valid routing model as secure software in EL3 + can handle the interrupt. + + +#### 1.1.4 Mapping of interrupt type to signal +The framework is meant to work with any interrupt controller implemented by a +platform. A interrupt controller could generate a type of interrupt as either an +FIQ or IRQ signal to the CPU depending upon the current security state. The +mapping between the type and signal is known only to the platform. The framework +uses this information to determine whether the IRQ or the FIQ bit should be +programmed in `SCR_EL3` while applying the routing model for a type of +interrupt. The platform provides this information through the +`plat_interrupt_type_to_line()` API (described in the [Porting +Guide]). For example, on the FVP port when the platform uses an ARM GICv2 +interrupt controller, Secure-EL1 interrupts are signaled through the FIQ signal +while Non-secure interrupts are signaled through the IRQ signal. This applies +when execution is in either security state. + + +##### 1.1.4.1 Effect of mapping of several interrupt types to one signal +It should be noted that if more than one interrupt type maps to a single +interrupt signal, and if any one of the interrupt type sets __TEL3=1__ for a +particular security state, then interrupt signal will be routed to EL3 when in +that security state. This means that all the other interrupt types using the +same interrupt signal will be forced to the same routing model. This should be +borne in mind when choosing the routing model for an interrupt type. + +For example, in ARM GICv3, when the execution context is Secure-EL1/ +Secure-EL0, both the EL3 and the non secure interrupt types map to the FIQ +signal. So if either one of the interrupt type sets the routing model so +that __TEL3=1__ when __CSS=0__, the FIQ bit in `SCR_EL3` will be programmed to +route the FIQ signal to EL3 when executing in Secure-EL1/Secure-EL0, thereby +effectively routing the other interrupt type also to EL3. + + +### 1.2 Assumptions in Interrupt Management Framework +The framework makes the following assumptions to simplify its implementation. + +1. Although the framework has support for 2 types of secure interrupts (EL3 + and Secure-EL1 interrupt), only interrupt controller architectures + like ARM GICv3 has architectural support for EL3 interrupts in the form of + Group 0 interrupts. In ARM GICv2, all secure interrupts are assumed to be + handled in Secure-EL1. They can be delivered to Secure-EL1 via EL3 but they + cannot be handled in EL3. + +2. Interrupt exceptions (`PSTATE.I` and `F` bits) are masked during execution + in EL3. + + +2. Interrupt management +----------------------- +The following sections describe how interrupts are managed by the interrupt +handling framework. This entails: + +1. Providing an interface to allow registration of a handler and specification + of the routing model for a type of interrupt. + +2. Implementing support to hand control of an interrupt type to its registered + handler when the interrupt is generated. + +Both aspects of interrupt management involve various components in the secure +software stack spanning from EL3 to Secure-EL1. These components are described +in the section 2.1. The framework stores information associated with each type +of interrupt in the following data structure. + +``` +typedef struct intr_type_desc { + interrupt_type_handler_t handler; + uint32_t flags; + uint32_t scr_el3[2]; +} intr_type_desc_t; +``` + +The `flags` field stores the routing model for the interrupt type in +bits[1:0]. Bit[0] stores the routing model when execution is in the secure +state. Bit[1] stores the routing model when execution is in the non-secure +state. As mentioned in Section 1.2.2, a value of `0` implies that the interrupt +should be targeted to the FEL. A value of `1` implies that it should be targeted +to EL3. The remaining bits are reserved and SBZ. The helper macro +`set_interrupt_rm_flag()` should be used to set the bits in the `flags` +parameter. + +The `scr_el3[2]` field also stores the routing model but as a mapping of the +model in the `flags` field to the corresponding bit in the `SCR_EL3` for each +security state. + +The framework also depends upon the platform port to configure the interrupt +controller to distinguish between secure and non-secure interrupts. The platform +is expected to be aware of the secure devices present in the system and their +associated interrupt numbers. It should configure the interrupt controller to +enable the secure interrupts, ensure that their priority is always higher than +the non-secure interrupts and target them to the primary CPU. It should also +export the interface described in the [Porting Guide] to enable +handling of interrupts. + +In the remainder of this document, for the sake of simplicity a ARM GICv2 system +is considered and it is assumed that the FIQ signal is used to generate Secure-EL1 +interrupts and the IRQ signal is used to generate non-secure interrupts in either +security state. EL3 interrupts are not considered. + + +### 2.1 Software components +Roles and responsibilities for interrupt management are sub-divided between the +following components of software running in EL3 and Secure-EL1. Each component is +briefly described below. + +1. EL3 Runtime Firmware. This component is common to all ports of the ARM + Trusted Firmware. + +2. Secure Payload Dispatcher (SPD) service. This service interfaces with the + Secure Payload (SP) software which runs in Secure-EL1/Secure-EL0 and is + responsible for switching execution between secure and non-secure states. + A switch is triggered by a Secure Monitor Call and it uses the APIs + exported by the Context management library to implement this functionality. + Switching execution between the two security states is a requirement for + interrupt management as well. This results in a significant dependency on + the SPD service. ARM Trusted firmware implements an example Test Secure + Payload Dispatcher (TSPD) service. + + An SPD service plugs into the EL3 runtime firmware and could be common to + some ports of the ARM Trusted Firmware. + +3. Secure Payload (SP). On a production system, the Secure Payload corresponds + to a Secure OS which runs in Secure-EL1/Secure-EL0. It interfaces with the + SPD service to manage communication with non-secure software. ARM Trusted + Firmware implements an example secure payload called Test Secure Payload + (TSP) which runs only in Secure-EL1. + + A Secure payload implementation could be common to some ports of the ARM + Trusted Firmware just like the SPD service. + + +### 2.2 Interrupt registration +This section describes in detail the role of each software component (see 2.1) +during the registration of a handler for an interrupt type. + + +#### 2.2.1 EL3 runtime firmware +This component declares the following prototype for a handler of an interrupt type. + + typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, + uint32_t flags, + void *handle, + void *cookie); + +The `id` is parameter is reserved and could be used in the future for passing +the interrupt id of the highest pending interrupt only if there is a foolproof +way of determining the id. Currently it contains `INTR_ID_UNAVAILABLE`. + +The `flags` parameter contains miscellaneous information as follows. + +1. Security state, bit[0]. This bit indicates the security state of the lower + exception level when the interrupt was generated. A value of `1` means + that it was in the non-secure state. A value of `0` indicates that it was + in the secure state. This bit can be used by the handler to ensure that + interrupt was generated and routed as per the routing model specified + during registration. + +2. Reserved, bits[31:1]. The remaining bits are reserved for future use. + +The `handle` parameter points to the `cpu_context` structure of the current CPU +for the security state specified in the `flags` parameter. + +Once the handler routine completes, execution will return to either the secure +or non-secure state. The handler routine should return a pointer to +`cpu_context` structure of the current CPU for the target security state. It +should treat all error conditions as critical errors and take appropriate action +within its implementation e.g. use assertion failures. + +The runtime firmware provides the following API for registering a handler for a +particular type of interrupt. A Secure Payload Dispatcher service should use +this API to register a handler for Secure-EL1 and optionally for non-secure +interrupts. This API also requires the caller to specify the routing model for +the type of interrupt. + + int32_t register_interrupt_type_handler(uint32_t type, + interrupt_type_handler handler, + uint64_t flags); + + +The `type` parameter can be one of the three interrupt types listed above i.e. +`INTR_TYPE_S_EL1`, `INTR_TYPE_NS` & `INTR_TYPE_EL3`. The `flags` parameter +is as described in Section 2. + +The function will return `0` upon a successful registration. It will return +`-EALREADY` in case a handler for the interrupt type has already been +registered. If the `type` is unrecognised or the `flags` or the `handler` are +invalid it will return `-EINVAL`. + +Interrupt routing is governed by the configuration of the `SCR_EL3.FIQ/IRQ` bits +prior to entry into a lower exception level in either security state. The +context management library maintains a copy of the `SCR_EL3` system register for +each security state in the `cpu_context` structure of each CPU. It exports the +following APIs to let EL3 Runtime Firmware program and retrieve the routing +model for each security state for the current CPU. The value of `SCR_EL3` stored +in the `cpu_context` is used by the `el3_exit()` function to program the +`SCR_EL3` register prior to returning from the EL3 exception level. + + uint32_t cm_get_scr_el3(uint32_t security_state); + void cm_write_scr_el3_bit(uint32_t security_state, + uint32_t bit_pos, + uint32_t value); + +`cm_get_scr_el3()` returns the value of the `SCR_EL3` register for the specified +security state of the current CPU. `cm_write_scr_el3()` writes a `0` or `1` to +the bit specified by `bit_pos`. `register_interrupt_type_handler()` invokes +`set_routing_model()` API which programs the `SCR_EL3` according to the routing +model using the `cm_get_scr_el3()` and `cm_write_scr_el3_bit()` APIs. + +It is worth noting that in the current implementation of the framework, the EL3 +runtime firmware is responsible for programming the routing model. The SPD is +responsible for ensuring that the routing model has been adhered to upon +receiving an interrupt. + + +#### 2.2.2 Secure payload dispatcher +A SPD service is responsible for determining and maintaining the interrupt +routing model supported by itself and the Secure Payload. It is also responsible +for ferrying interrupts between secure and non-secure software depending upon +the routing model. It could determine the routing model at build time or at +runtime. It must use this information to register a handler for each interrupt +type using the `register_interrupt_type_handler()` API in EL3 runtime firmware. + +If the routing model is not known to the SPD service at build time, then it must +be provided by the SP as the result of its initialisation. The SPD should +program the routing model only after SP initialisation has completed e.g. in the +SPD initialisation function pointed to by the `bl32_init` variable. + +The SPD should determine the mechanism to pass control to the Secure Payload +after receiving an interrupt from the EL3 runtime firmware. This information +could either be provided to the SPD service at build time or by the SP at +runtime. + + +#### 2.2.2.1 Test secure payload dispatcher behavior +The TSPD only handles Secure-EL1 interrupts and is provided with the following +routing model at build time. + +* Secure-EL1 interrupts are routed to EL3 when execution is in non-secure + state and are routed to the FEL when execution is in the secure state + i.e __CSS=0, TEL3=0__ & __CSS=1, TEL3=1__ for Secure-EL1 interrupts + +* When the build flag `TSP_NS_INTR_ASYNC_PREEMPT` is zero, the default routing + model is used for non-secure interrupts. They are routed to the FEL in + either security state i.e __CSS=0, TEL3=0__ & __CSS=1, TEL3=0__ for + Non-secure interrupts. + +* When the build flag `TSP_NS_INTR_ASYNC_PREEMPT` is defined to 1, then the + non secure interrupts are routed to EL3 when execution is in secure state + i.e __CSS=0, TEL3=1__ for non-secure interrupts. This effectively preempts + Secure-EL1. The default routing model is used for non secure interrupts in + non-secure state. i.e __CSS=1, TEL3=0__. + +It performs the following actions in the `tspd_init()` function to fulfill the +requirements mentioned earlier. + +1. It passes control to the Test Secure Payload to perform its + initialisation. The TSP provides the address of the vector table + `tsp_vectors` in the SP which also includes the handler for Secure-EL1 + interrupts in the `sel1_intr_entry` field. The TSPD passes control to the TSP at + this address when it receives a Secure-EL1 interrupt. + + The handover agreement between the TSP and the TSPD requires that the TSPD + masks all interrupts (`PSTATE.DAIF` bits) when it calls + `tsp_sel1_intr_entry()`. The TSP has to preserve the callee saved general + purpose, SP_EL1/Secure-EL0, LR, VFP and system registers. It can use + `x0-x18` to enable its C runtime. + +2. The TSPD implements a handler function for Secure-EL1 interrupts. This + function is registered with the EL3 runtime firmware using the + `register_interrupt_type_handler()` API as follows + + /* Forward declaration */ + interrupt_type_handler tspd_secure_el1_interrupt_handler; + int32_t rc, flags = 0; + set_interrupt_rm_flag(flags, NON_SECURE); + rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, + tspd_secure_el1_interrupt_handler, + flags); + if (rc) + panic(); + +3. When the build flag `TSP_NS_INTR_ASYNC_PREEMPT` is defined to 1, the TSPD + implements a handler function for non-secure interrupts. This function is + registered with the EL3 runtime firmware using the + `register_interrupt_type_handler()` API as follows + + /* Forward declaration */ + interrupt_type_handler tspd_ns_interrupt_handler; + int32_t rc, flags = 0; + set_interrupt_rm_flag(flags, SECURE); + rc = register_interrupt_type_handler(INTR_TYPE_NS, + tspd_ns_interrupt_handler, + flags); + if (rc) + panic(); + + +#### 2.2.3 Secure payload +A Secure Payload must implement an interrupt handling framework at Secure-EL1 +(Secure-EL1 IHF) to support its chosen interrupt routing model. Secure payload +execution will alternate between the below cases. + +1. In the code where IRQ, FIQ or both interrupts are enabled, if an interrupt + type is targeted to the FEL, then it will be routed to the Secure-EL1 + exception vector table. This is defined as the __asynchronous mode__ of + handling interrupts. This mode applies to both Secure-EL1 and non-secure + interrupts. + +2. In the code where both interrupts are disabled, if an interrupt type is + targeted to the FEL, then execution will eventually migrate to the + non-secure state. Any non-secure interrupts will be handled as described + in the routing model where __CSS=1 and TEL3=0__. Secure-EL1 interrupts + will be routed to EL3 (as per the routing model where __CSS=1 and + TEL3=1__) where the SPD service will hand them to the SP. This is defined + as the __synchronous mode__ of handling interrupts. + +The interrupt handling framework implemented by the SP should support one or +both these interrupt handling models depending upon the chosen routing model. + +The following list briefly describes how the choice of a valid routing model +(See 1.2.3) effects the implementation of the Secure-EL1 IHF. If the choice of +the interrupt routing model is not known to the SPD service at compile time, +then the SP should pass this information to the SPD service at runtime during +its initialisation phase. + +As mentioned earlier, a ARM GICv2 system is considered and it is assumed that +the FIQ signal is used to generate Secure-EL1 interrupts and the IRQ signal +is used to generate non-secure interrupts in either security state. + + +##### 2.2.3.1 Secure payload IHF design w.r.t secure-EL1 interrupts +1. __CSS=0, TEL3=0__. If `PSTATE.F=0`, Secure-EL1 interrupts will be + triggered at one of the Secure-EL1 FIQ exception vectors. The Secure-EL1 + IHF should implement support for handling FIQ interrupts asynchronously. + + If `PSTATE.F=1` then Secure-EL1 interrupts will be handled as per the + synchronous interrupt handling model. The SP could implement this scenario + by exporting a separate entrypoint for Secure-EL1 interrupts to the SPD + service during the registration phase. The SPD service would also need to + know the state of the system, general purpose and the `PSTATE` registers + in which it should arrange to return execution to the SP. The SP should + provide this information in an implementation defined way during the + registration phase if it is not known to the SPD service at build time. + +2. __CSS=1, TEL3=1__. Interrupts are routed to EL3 when execution is in + non-secure state. They should be handled through the synchronous interrupt + handling model as described in 1. above. + +3. __CSS=0, TEL3=1__. Secure-EL1 interrupts are routed to EL3 when execution + is in secure state. They will not be visible to the SP. The `PSTATE.F` bit + in Secure-EL1/Secure-EL0 will not mask FIQs. The EL3 runtime firmware will + call the handler registered by the SPD service for Secure-EL1 interrupts. + Secure-EL1 IHF should then handle all Secure-EL1 interrupt through the + synchronous interrupt handling model described in 1. above. + + +##### 2.2.3.2 Secure payload IHF design w.r.t non-secure interrupts +1. __CSS=0, TEL3=0__. If `PSTATE.I=0`, non-secure interrupts will be + triggered at one of the Secure-EL1 IRQ exception vectors . The Secure-EL1 + IHF should co-ordinate with the SPD service to transfer execution to the + non-secure state where the interrupt should be handled e.g the SP could + allocate a function identifier to issue a SMC64 or SMC32 to the SPD + service which indicates that the SP execution has been preempted by a + non-secure interrupt. If this function identifier is not known to the SPD + service at compile time then the SP could provide it during the + registration phase. + + If `PSTATE.I=1` then the non-secure interrupt will pend until execution + resumes in the non-secure state. + +2. __CSS=0, TEL3=1__. Non-secure interrupts are routed to EL3. They will not + be visible to the SP. The `PSTATE.I` bit in Secure-EL1/Secure-EL0 will + have not effect. The SPD service should register a non-secure interrupt + handler which should save the SP state correctly and resume execution in + the non-secure state where the interrupt will be handled. The Secure-EL1 + IHF does not need to take any action. + +3. __CSS=1, TEL3=0__. Non-secure interrupts are handled in the FEL in + non-secure state (EL1/EL2) and are not visible to the SP. This routing + model does not affect the SP behavior. + +A Secure Payload must also ensure that all Secure-EL1 interrupts are correctly +configured at the interrupt controller by the platform port of the EL3 runtime +firmware. It should configure any additional Secure-EL1 interrupts which the EL3 +runtime firmware is not aware of through its platform port. + + +#### 2.2.3.3 Test secure payload behavior +The routing model for Secure-EL1 and non-secure interrupts chosen by the TSP is +described in Section 2.2.2. It is known to the TSPD service at build time. + +The TSP implements an entrypoint (`tsp_sel1_intr_entry()`) for handling Secure-EL1 +interrupts taken in non-secure state and routed through the TSPD service +(synchronous handling model). It passes the reference to this entrypoint via +`tsp_vectors` to the TSPD service. + +The TSP also replaces the default exception vector table referenced through the +`early_exceptions` variable, with a vector table capable of handling FIQ and IRQ +exceptions taken at the same (Secure-EL1) exception level. This table is +referenced through the `tsp_exceptions` variable and programmed into the +VBAR_EL1. It caters for the asynchronous handling model. + +The TSP also programs the Secure Physical Timer in the ARM Generic Timer block +to raise a periodic interrupt (every half a second) for the purpose of testing +interrupt management across all the software components listed in 2.1 + + +### 2.3 Interrupt handling +This section describes in detail the role of each software component (see +Section 2.1) in handling an interrupt of a particular type. + + +#### 2.3.1 EL3 runtime firmware +The EL3 runtime firmware populates the IRQ and FIQ exception vectors referenced +by the `runtime_exceptions` variable as follows. + +1. IRQ and FIQ exceptions taken from the current exception level with + `SP_EL0` or `SP_EL3` are reported as irrecoverable error conditions. As + mentioned earlier, EL3 runtime firmware always executes with the + `PSTATE.I` and `PSTATE.F` bits set. + +2. The following text describes how the IRQ and FIQ exceptions taken from a + lower exception level using AArch64 or AArch32 are handled. + +When an interrupt is generated, the vector for each interrupt type is +responsible for: + +1. Saving the entire general purpose register context (x0-x30) immediately + upon exception entry. The registers are saved in the per-cpu `cpu_context` + data structure referenced by the `SP_EL3`register. + +2. Saving the `ELR_EL3`, `SP_EL0` and `SPSR_EL3` system registers in the + per-cpu `cpu_context` data structure referenced by the `SP_EL3` register. + +3. Switching to the C runtime stack by restoring the `CTX_RUNTIME_SP` value + from the per-cpu `cpu_context` data structure in `SP_EL0` and + executing the `msr spsel, #0` instruction. + +4. Determining the type of interrupt. Secure-EL1 interrupts will be signaled + at the FIQ vector. Non-secure interrupts will be signaled at the IRQ + vector. The platform should implement the following API to determine the + type of the pending interrupt. + + uint32_t plat_ic_get_interrupt_type(void); + + It should return either `INTR_TYPE_S_EL1` or `INTR_TYPE_NS`. + +5. Determining the handler for the type of interrupt that has been generated. + The following API has been added for this purpose. + + interrupt_type_handler get_interrupt_type_handler(uint32_t interrupt_type); + + It returns the reference to the registered handler for this interrupt + type. The `handler` is retrieved from the `intr_type_desc_t` structure as + described in Section 2. `NULL` is returned if no handler has been + registered for this type of interrupt. This scenario is reported as an + irrecoverable error condition. + +6. Calling the registered handler function for the interrupt type generated. + The `id` parameter is set to `INTR_ID_UNAVAILABLE` currently. The id along + with the current security state and a reference to the `cpu_context_t` + structure for the current security state are passed to the handler function + as its arguments. + + The handler function returns a reference to the per-cpu `cpu_context_t` + structure for the target security state. + +7. Calling `el3_exit()` to return from EL3 into a lower exception level in + the security state determined by the handler routine. The `el3_exit()` + function is responsible for restoring the register context from the + `cpu_context_t` data structure for the target security state. + + +#### 2.3.2 Secure payload dispatcher + +##### 2.3.2.1 Interrupt entry +The SPD service begins handling an interrupt when the EL3 runtime firmware calls +the handler function for that type of interrupt. The SPD service is responsible +for the following: + +1. Validating the interrupt. This involves ensuring that the interrupt was + generating according to the interrupt routing model specified by the SPD + service during registration. It should use the security state of the + exception level (passed in the `flags` parameter of the handler) where + the interrupt was taken from to determine this. If the interrupt is not + recognised then the handler should treat it as an irrecoverable error + condition. + + A SPD service can register a handler for Secure-EL1 and/or Non-secure + interrupts. A non-secure interrupt should never be routed to EL3 from + from non-secure state. Also if a routing model is chosen where Secure-EL1 + interrupts are routed to S-EL1 when execution is in Secure state, then a + S-EL1 interrupt should never be routed to EL3 from secure state. The handler + could use the security state flag to check this. + +2. Determining whether a context switch is required. This depends upon the + routing model and interrupt type. For non secure and S-EL1 interrupt, + if the security state of the execution context where the interrupt was + generated is not the same as the security state required for handling + the interrupt, a context switch is required. The following 2 cases + require a context switch from secure to non-secure or vice-versa: + + 1. A Secure-EL1 interrupt taken from the non-secure state should be + routed to the Secure Payload. + + 2. A non-secure interrupt taken from the secure state should be routed + to the last known non-secure exception level. + + The SPD service must save the system register context of the current + security state. It must then restore the system register context of the + target security state. It should use the `cm_set_next_eret_context()` API + to ensure that the next `cpu_context` to be restored is of the target + security state. + + If the target state is secure then execution should be handed to the SP as + per the synchronous interrupt handling model it implements. A Secure-EL1 + interrupt can be routed to EL3 while execution is in the SP. This implies + that SP execution can be preempted while handling an interrupt by a + another higher priority Secure-EL1 interrupt or a EL3 interrupt. The SPD + service should be able to handle this preemption or manage secure interrupt + priorities before handing control to the SP. + +3. Setting the return value of the handler to the per-cpu `cpu_context` if + the interrupt has been successfully validated and ready to be handled at a + lower exception level. + +The routing model allows non-secure interrupts to interrupt Secure-EL1 when in +secure state if it has been configured to do so. The SPD service and the SP +should implement a mechanism for routing these interrupts to the last known +exception level in the non-secure state. The former should save the SP context, +restore the non-secure context and arrange for entry into the non-secure state +so that the interrupt can be handled. + + +##### 2.3.2.2 Interrupt exit +When the Secure Payload has finished handling a Secure-EL1 interrupt, it could +return control back to the SPD service through a SMC32 or SMC64. The SPD service +should handle this secure monitor call so that execution resumes in the +exception level and the security state from where the Secure-EL1 interrupt was +originally taken. + + +##### 2.3.2.3 Test secure payload dispatcher Secure-EL1 interrupt handling +The example TSPD service registers a handler for Secure-EL1 interrupts taken +from the non-secure state. During execution in S-EL1, the TSPD expects that the +Secure-EL1 interrupts are handled in S-EL1 by TSP. Its handler +`tspd_secure_el1_interrupt_handler()` expects only to be invoked for Secure-EL1 +originating from the non-secure state. It takes the following actions upon being +invoked. + +1. It uses the security state provided in the `flags` parameter to ensure + that the secure interrupt originated from the non-secure state. It asserts + if this is not the case. + +2. It saves the system register context for the non-secure state by calling + `cm_el1_sysregs_context_save(NON_SECURE);`. + +3. It sets the `ELR_EL3` system register to `tsp_sel1_intr_entry` and sets the + `SPSR_EL3.DAIF` bits in the secure CPU context. It sets `x0` to + `TSP_HANDLE_SEL1_INTR_AND_RETURN`. If the TSP was preempted earlier by a non + secure interrupt during `standard` SMC processing, save the registers that + will be trashed, which is the `ELR_EL3` and `SPSR_EL3`, in order to be able + to re-enter TSP for Secure-EL1 interrupt processing. It does not need to + save any other secure context since the TSP is expected to preserve it + (see Section 2.2.2.1). + +4. It restores the system register context for the secure state by calling + `cm_el1_sysregs_context_restore(SECURE);`. + +5. It ensures that the secure CPU context is used to program the next + exception return from EL3 by calling `cm_set_next_eret_context(SECURE);`. + +6. It returns the per-cpu `cpu_context` to indicate that the interrupt can + now be handled by the SP. `x1` is written with the value of `elr_el3` + register for the non-secure state. This information is used by the SP for + debugging purposes. + +The figure below describes how the interrupt handling is implemented by the TSPD +when a Secure-EL1 interrupt is generated when execution is in the non-secure +state. + +![Image 1](diagrams/sec-int-handling.png?raw=true) + +The TSP issues an SMC with `TSP_HANDLED_S_EL1_INTR` as the function identifier to +signal completion of interrupt handling. + +The TSPD service takes the following actions in `tspd_smc_handler()` function +upon receiving an SMC with `TSP_HANDLED_S_EL1_INTR` as the function identifier: + +1. It ensures that the call originated from the secure state otherwise + execution returns to the non-secure state with `SMC_UNK` in `x0`. + +2. It restores the saved `ELR_EL3` and `SPSR_EL3` system registers back to + the secure CPU context (see step 3 above) in case the TSP had been preempted + by a non secure interrupt earlier. + +3. It restores the system register context for the non-secure state by + calling `cm_el1_sysregs_context_restore(NON_SECURE)`. + +4. It ensures that the non-secure CPU context is used to program the next + exception return from EL3 by calling `cm_set_next_eret_context(NON_SECURE)`. + +5. `tspd_smc_handler()` returns a reference to the non-secure `cpu_context` + as the return value. + + +##### 2.3.2.4 Test secure payload dispatcher non-secure interrupt handling +The TSP in Secure-EL1 can be preempted by a non-secure interrupt during +`standard` SMC processing or by a higher priority EL3 interrupt during +Secure-EL1 interrupt processing. Currently only non-secure interrupts can +cause preemption of TSP since there are no EL3 interrupts in the +system. + +It should be noted that while TSP is preempted, the TSPD only allows entry into +the TSP either for Secure-EL1 interrupt handling or for resuming the preempted +`standard` SMC in response to the `TSP_FID_RESUME` SMC from the normal world. +(See Section 3). + +The non-secure interrupt triggered in Secure-EL1 during `standard` SMC processing +can be routed to either EL3 or Secure-EL1 and is controlled by build option +`TSP_NS_INTR_ASYNC_PREEMPT` (see Section 2.2.2.1). If the build option is set, +the TSPD will set the routing model for the non-secure interrupt to be routed to +EL3 from secure state i.e. __TEL3=1, CSS=0__ and registers +`tspd_ns_interrupt_handler()` as the non-secure interrupt handler. The +`tspd_ns_interrupt_handler()` on being invoked ensures that the interrupt +originated from the secure state and disables routing of non-secure interrupts +from secure state to EL3. This is to prevent further preemption (by a non-secure +interrupt) when TSP is reentered for handling Secure-EL1 interrupts that +triggered while execution was in the normal world. The +`tspd_ns_interrupt_handler()` then invokes `tspd_handle_sp_preemption()` for +further handling. + +If the `TSP_NS_INTR_ASYNC_PREEMPT` build option is zero (default), the default +routing model for non-secure interrupt in secure state is in effect +i.e. __TEL3=0, CSS=0__. During `standard` SMC processing, the IRQ +exceptions are unmasked i.e. `PSTATE.I=0`, and a non-secure interrupt will +trigger at Secure-EL1 IRQ exception vector. The TSP saves the general purpose +register context and issues an SMC with `TSP_PREEMPTED` as the function +identifier to signal preemption of TSP. The TSPD SMC handler, +`tspd_smc_handler()`, ensures that the SMC call originated from the +secure state otherwise execution returns to the non-secure state with +`SMC_UNK` in `x0`. It then invokes `tspd_handle_sp_preemption()` for +further handling. + +The `tspd_handle_sp_preemption()` takes the following actions upon being +invoked: + +1. It saves the system register context for the secure state by calling + `cm_el1_sysregs_context_save(SECURE)`. + +2. It restores the system register context for the non-secure state by + calling `cm_el1_sysregs_context_restore(NON_SECURE)`. + +3. It ensures that the non-secure CPU context is used to program the next + exception return from EL3 by calling `cm_set_next_eret_context(NON_SECURE)`. + +4. `SMC_PREEMPTED` is set in x0 and return to non secure state after + restoring non secure context. + +The Normal World is expected to resume the TSP after the `standard` SMC preemption +by issuing an SMC with `TSP_FID_RESUME` as the function identifier (see section 3). +The TSPD service takes the following actions in `tspd_smc_handler()` function +upon receiving this SMC: + +1. It ensures that the call originated from the non secure state. An + assertion is raised otherwise. + +2. Checks whether the TSP needs a resume i.e check if it was preempted. It + then saves the system register context for the non-secure state by calling + `cm_el1_sysregs_context_save(NON_SECURE)`. + +3. Restores the secure context by calling + `cm_el1_sysregs_context_restore(SECURE)` + +4. It ensures that the secure CPU context is used to program the next + exception return from EL3 by calling `cm_set_next_eret_context(SECURE)`. + +5. `tspd_smc_handler()` returns a reference to the secure `cpu_context` as the + return value. + +The figure below describes how the TSP/TSPD handle a non-secure interrupt when +it is generated during execution in the TSP with `PSTATE.I` = 0 when the +`TSP_NS_INTR_ASYNC_PREEMPT` build flag is 0. + +![Image 2](diagrams/non-sec-int-handling.png?raw=true) + + +#### 2.3.3 Secure payload +The SP should implement one or both of the synchronous and asynchronous +interrupt handling models depending upon the interrupt routing model it has +chosen (as described in 2.2.3). + +In the synchronous model, it should begin handling a Secure-EL1 interrupt after +receiving control from the SPD service at an entrypoint agreed upon during build +time or during the registration phase. Before handling the interrupt, the SP +should save any Secure-EL1 system register context which is needed for resuming +normal execution in the SP later e.g. `SPSR_EL1, `ELR_EL1`. After handling the +interrupt, the SP could return control back to the exception level and security +state where the interrupt was originally taken from. The SP should use an SMC32 +or SMC64 to ask the SPD service to do this. + +In the asynchronous model, the Secure Payload is responsible for handling +non-secure and Secure-EL1 interrupts at the IRQ and FIQ vectors in its exception +vector table when `PSTATE.I` and `PSTATE.F` bits are 0. As described earlier, +when a non-secure interrupt is generated, the SP should coordinate with the SPD +service to pass control back to the non-secure state in the last known exception +level. This will allow the non-secure interrupt to be handled in the non-secure +state. + + +##### 2.3.3.1 Test secure payload behavior +The TSPD hands control of a Secure-EL1 interrupt to the TSP at the +`tsp_sel1_intr_entry()`. The TSP handles the interrupt while ensuring that the +handover agreement described in Section 2.2.2.1 is maintained. It updates some +statistics by calling `tsp_update_sync_sel1_intr_stats()`. It then calls +`tsp_common_int_handler()` which. + +1. Checks whether the interrupt is the secure physical timer interrupt. It + uses the platform API `plat_ic_get_pending_interrupt_id()` to get the + interrupt number. If it is not the secure physical timer interrupt, then + that means that a higher priority interrupt has preempted it. Invoke + `tsp_handle_preemption()` to handover control back to EL3 by issuing + an SMC with `TSP_PREEMPTED` as the function identifier. + +2. Handles the secure timer interrupt interrupt by acknowledging it using the + `plat_ic_acknowledge_interrupt()` platform API, calling + `tsp_generic_timer_handler()` to reprogram the secure physical generic + timer and calling the `plat_ic_end_of_interrupt()` platform API to signal + end of interrupt processing. + +The TSP passes control back to the TSPD by issuing an SMC64 with +`TSP_HANDLED_S_EL1_INTR` as the function identifier. + +The TSP handles interrupts under the asynchronous model as follows. + +1. Secure-EL1 interrupts are handled by calling the `tsp_common_int_handler()` + function. The function has been described above. + +2. Non-secure interrupts are handled by by calling the `tsp_common_int_handler()` + function which ends up invoking `tsp_handle_preemption()` and issuing an + SMC64 with `TSP_PREEMPTED` as the function identifier. Execution resumes at + the instruction that follows this SMC instruction when the TSPD hands + control to the TSP in response to an SMC with `TSP_FID_RESUME` as the + function identifier from the non-secure state (see section 2.3.2.4). + + +3. Other considerations +----------------------- + +### 3.1 Implication of preempted SMC on Non-Secure Software +A `standard` SMC call to Secure payload can be preempted by a non-secure +interrupt and the execution can return to the non-secure world for handling +the interrupt (For details on `standard` SMC refer [SMC calling convention]). +In this case, the SMC call has not completed its execution and the execution +must return back to the secure payload to resume the preempted SMC call. +This can be achieved by issuing an SMC call which instructs to resume the +preempted SMC. + +A `fast` SMC cannot be preempted and hence this case will not happen for +a fast SMC call. + +In the Test Secure Payload implementation, `TSP_FID_RESUME` is designated +as the resume SMC FID. It is important to note that `TSP_FID_RESUME` is a +`standard` SMC which means it too can be be preempted. The typical non +secure software sequence for issuing a `standard` SMC would look like this, +assuming `P.STATE.I=0` in the non secure state : + + int rc; + rc = smc(TSP_STD_SMC_FID, ...); /* Issue a Standard SMC call */ + /* The pending non-secure interrupt is handled by the interrupt handler + and returns back here. */ + while (rc == SMC_PREEMPTED) { /* Check if the SMC call is preempted */ + rc = smc(TSP_FID_RESUME); /* Issue resume SMC call */ + } + +The `TSP_STD_SMC_FID` is any `standard` SMC function identifier and the smc() +function invokes a SMC call with the required arguments. The pending non-secure +interrupt causes an IRQ exception and the IRQ handler registered at the +exception vector handles the non-secure interrupt and returns. The return value +from the SMC call is tested for `SMC_PREEMPTED` to check whether it is +preempted. If it is, then the resume SMC call `TSP_FID_RESUME` is issued. The +return value of the SMC call is tested again to check if it is preempted. +This is done in a loop till the SMC call succeeds or fails. If a `standard` +SMC is preempted, until it is resumed using `TSP_FID_RESUME` SMC and +completed, the current TSPD prevents any other SMC call from re-entering +TSP by returning `SMC_UNK` error. + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved._ + +[Porting Guide]: ./porting-guide.md +[SMC calling convention]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)" diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/plat/nvidia-tegra.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/plat/nvidia-tegra.md new file mode 100644 index 0000000..b29532c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/plat/nvidia-tegra.md @@ -0,0 +1,70 @@ +Tegra SoCs - Overview +====================== + +* T210 +------- + +T210 has Quad ARM® Cortex®-A57 cores in a switched configuration with a +companion set of quad ARM Cortex-A53 cores. The Cortex-A57 and A53 cores +support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code +including legacy ARMv7 applications. The Cortex-A57 processors each have +48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared +Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction +and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache. + +* T132 +------- + +Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is +fully ARMv8 architecture compatible. Each of the two Denver cores +implements a 7-way superscalar microarchitecture (up to 7 concurrent +micro-ops can be executed per clock), and includes a 128KB 4-way L1 +instruction cache, a 64KB 4-way L1 data cache, and a 2MB 16-way L2 +cache, which services both cores. + +Denver implements an innovative process called Dynamic Code Optimization, +which optimizes frequently used software routines at runtime into dense, +highly tuned microcode-equivalent routines. These are stored in a +dedicated, 128MB main-memory-based optimization cache. After being read +into the instruction cache, the optimized micro-ops are executed, +re-fetched and executed from the instruction cache as long as needed and +capacity allows. + +Effectively, this reduces the need to re-optimize the software routines. +Instead of using hardware to extract the instruction-level parallelism +(ILP) inherent in the code, Denver extracts the ILP once via software +techniques, and then executes those routines repeatedly, thus amortizing +the cost of ILP extraction over the many execution instances. + +Denver also features new low latency power-state transitions, in addition +to extensive power-gating and dynamic voltage and clock scaling based on +workloads. + +Directory structure +==================== + +* plat/nvidia/tegra/common - Common code for all Tegra SoCs +* plat/nvidia/tegra/soc/txxx - Chip specific code + +Trusted OS dispatcher +===================== +Tegra supports multiple Trusted OS', Trusted Little Kernel (TLK) being one of +them. In order to include the 'tlkd' dispatcher in the image, pass 'SPD=tlkd' +on the command line while preparing a bl31 image. This allows other Trusted OS +vendors to use the upstream code and include their dispatchers in the image +without changing any makefiles. + +Preparing the BL31 image to run on Tegra SoCs +=================================================== +'CROSS_COMPILE=/bin/aarch64-none-elf- make PLAT=tegra \ +TARGET_SOC= SPD= bl31' + +Platforms wanting to use different TZDRAM_BASE, can add 'TZDRAM_BASE=' +to the build command line. + +Power Management +================ +The PSCI implementation expects each platform to expose the 'power state' +parameter to be used during the 'SYSTEM SUSPEND' call. The state-id field +is implementation defined on Tegra SoCs and is preferably defined by +tegra_def.h. diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/plat/qemu.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/plat/qemu.md new file mode 100644 index 0000000..5e6bcbc --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/plat/qemu.md @@ -0,0 +1,44 @@ +ARM Trusted Firmware for QEMU virt ARMv8-A +========================================== + +ARM Trusted Firmware implements the EL3 firmware layer for QEMU virt +ARMv8-A. BL1 is used as the BootROM, supplied with the -bios argument. +When QEMU starts all CPUs are released simultaneously, BL1 selects a +primary CPU to handle the boot and the secondaries are placed in a polling +loop to be released by normal world via PSCI. + +BL2 edits the Flattened Device Tree, FDT, generated by QEMU at run-time to +add a node describing PSCI and also enable methods for the CPUs. + +An ARM64 defonfig v4.5 Linux kernel is known to boot, FTD doesn't need to be +provided as it's generated by QEMU. + +Current limitations: +* Only cold boot is supported +* No build instructions for QEMU_EFI.fd and rootfs-arm64.cpio.gz +* No instructions for how to load a BL32 (Secure Payload) + +`QEMU_EFI.fd` can be dowloaded from +http://snapshots.linaro.org/components/kernel/leg-virt-tianocore-edk2-upstream/latest/QEMU-KERNEL-AARCH64/RELEASE_GCC49/QEMU_EFI.fd + +Boot binaries, except BL1, are primarily loaded via semi-hosting so all +binaries has to reside in the same directory as QEMU is started from. This +is conveniently achieved with symlinks the local names as: +* `bl2.bin` -> BL2 +* `bl31.bin` -> BL31 +* `bl33.bin` -> BL33 (`QEMU_EFI.fd`) +* `Image` -> linux/Image + +To build: +``` +make CROSS_COMPILE=aarch64-none-elf- PLAT=qemu +``` + +To start (QEMU v2.6.0): +``` +qemu-system-aarch64 -nographic -machine virt,secure=on -cpu cortex-a57 \ + -kernel Image \ + -append console=ttyAMA0,38400 keep_bootcon root=/dev/vda2 \ + -initrd rootfs-arm64.cpio.gz -smp 2 -m 1024 -bios bl1.bin \ + -d unimp -semihosting-config enable,target=native +``` diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/plat/xilinx-zynqmp.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/plat/xilinx-zynqmp.md new file mode 100644 index 0000000..09546b0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/plat/xilinx-zynqmp.md @@ -0,0 +1,56 @@ +ARM Trusted Firmware for Xilinx Zynq UltraScale+ MPSoC +================================ + +ARM Trusted Firmware implements the EL3 firmware layer for Xilinx Zynq +UltraScale + MPSoC. +The platform only uses the runtime part of ATF as ZynqMP already has a +BootROM (BL1) and FSBL (BL2). + +BL31 is ATF. +BL32 is an optional Secure Payload. +BL33 is the non-secure world software (U-Boot, Linux etc). + +To build: +```bash +make ERROR_DEPRECATED=1 RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp bl31 +``` + +To build bl32 TSP you have to rebuild bl31 too: +```bash +make ERROR_DEPRECATED=1 RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32 +``` + +# ZynqMP platform specific build options +* `ZYNQMP_ATF_MEM_BASE`: Specifies the base address of the bl31 binary. +* `ZYNQMP_ATF_MEM_SIZE`: Specifies the size of the memory region of the bl31 binary. +* `ZYNQMP_BL32_MEM_BASE`: Specifies the base address of the bl32 binary. +* `ZYNQMP_BL32_MEM_SIZE`: Specifies the size of the memory region of the bl32 binary. + +* `ZYNQMP_CONSOLE`: Select the console driver. Options: + - `cadence`, `cadence0`: Cadence UART 0 + - `cadence1` : Cadence UART 1 + +# FSBL->ATF Parameter Passing +The FSBL populates a data structure with image information for the ATF. The ATF +uses that data to hand off to the loaded images. The address of the handoff data +structure is passed in the ```PMU_GLOBAL.GLOBAL_GEN_STORAGE6``` register. The +register is free to be used by other software once the ATF is bringing up +further firmware images. + +# Power Domain Tree +The following power domain tree represents the power domain model used by the +ATF for ZynqMP: +``` + +-+ + |0| + +-+ + +-------+---+---+-------+ + | | | | + | | | | + v v v v + +-+ +-+ +-+ +-+ + |0| |1| |2| |3| + +-+ +-+ +-+ +-+ +``` +The 4 leaf power domains represent the individual A53 cores, while resources +common to the cluster are grouped in the power domain on the top. diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/platform-migration-guide.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/platform-migration-guide.md new file mode 100644 index 0000000..27cd067 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/platform-migration-guide.md @@ -0,0 +1,575 @@ +Guide to migrate to new Platform porting interface +================================================== + +Contents +-------- + +1. [Introduction](#1--introduction) +2. [Platform API modification due to PSCI framework changes](#2--platform-api-modification-due-to-psci-framework-changes) + * [Power domain topology framework platform API modifications](#21-power-domain-topology-framework-platform-api-modifications) + * [Composite power state framework platform API modifications](#22-composite-power-state-framework-platform-api-modifications) + * [Miscellaneous modifications](#23-miscellaneous-modifications) +3. [Compatibility layer](#3--compatibility-layer) +4. [Deprecated Platform API](#4--deprecated-platform-api) + +- - - - - - - - - - - - - - - - - - + + +1. Introduction +---------------- + +The PSCI implementation in Trusted Firmware has undergone a redesign because of +three requirements that the PSCI 1.0 specification introduced : + +* Removing the framework assumption about the structure of the MPIDR, and + its relation to the power topology enables support for deeper and more + complex hierarchies. + +* Reworking the power state coordination implementation in the framework + to support the more detailed PSCI 1.0 requirements and reduce platform + port complexity + +* Enable the use of the extended power_state parameter and the larger StateID + field + +The PSCI 1.0 implementation introduces new frameworks to fulfill the above +requirements. These framework changes mean that the platform porting API must +also be modified. This document is a guide to assist migration of the existing +platform ports to the new platform API. + +This document describes the new platform API and compares it with the +deprecated API. It also describes the compatibility layer that enables the +existing platform ports to work with the PSCI 1.0 implementation. The +deprecated platform API is documented for reference. + + +2. Platform API modification due to PSCI framework changes +----------------------------------------------------------- + +This section describes changes to the platform APIs. + + +2.1 Power domain topology framework platform API modifications +-------------------------------------------------------------- + +This removes the assumption in the PSCI implementation that MPIDR +based affinity instances map directly to power domains. A power domain, as +described in section 4.2 of [PSCI], could contain a core or a logical group +of cores (a cluster) which share some state on which power management +operations can be performed. The existing affinity instance based APIs +`plat_get_aff_count()` and `plat_get_aff_state()` are deprecated. The new +platform interfaces that are introduced for this framework are: + +* `plat_core_pos_by_mpidr()` +* `plat_my_core_pos()` +* `plat_get_power_domain_tree_desc()` + +`plat_my_core_pos()` and `plat_core_pos_by_mpidr()` are mandatory +and are meant to replace the existing `platform_get_core_pos()` API. +The description of these APIs can be found in the [Porting Guide][my_core_pos]. +These are used by the power domain topology framework such that: + +1. The generic PSCI code does not generate MPIDRs or use them to query the + platform about the number of power domains at a particular power level. The + `plat_get_power_domain_tree_desc()` provides a description of the power + domain tree on the SoC through a pointer to the byte array containing the + power domain topology tree description data structure. + +2. The linear indices returned by `plat_core_pos_by_mpidr()` and + `plat_my_core_pos()` are used to retrieve core power domain nodes from + the power domain tree. These core indices are unique for a core and it is a + number between `0` and `PLATFORM_CORE_COUNT - 1`. The platform can choose + to implement a static mapping between `MPIDR` and core index or implement + a dynamic mapping, choosing to skip the unavailable/unused cores to compact + the core indices. + +In addition, the platforms must define the macros `PLAT_NUM_PWR_DOMAINS` and +`PLAT_MAX_PWR_LVL` which replace the macros `PLAT_NUM_AFFS` and +`PLATFORM_MAX_AFFLVL` respectively. On platforms where the affinity instances +correspond to power domains, the values of new macros remain the same as the +old ones. + +More details on the power domain topology description and its platform +interface can be found in [psci pd tree]. + + +2.2 Composite power state framework platform API modifications +-------------------------------------------------------------- + +The state-ID field in the power-state parameter of a CPU_SUSPEND call can be +used to describe the composite power states specific to a platform. The existing +PSCI state coordination had the limitation that it operates on a run/off +granularity of power states and it did not interpret the state-ID field. This +was acceptable as the specification requirement in PSCI 0.2 and the framework's +approach to coordination only required maintaining a reference +count of the number of cores that have requested the cluster to remain powered. + +In the PSCI 1.0 specification, this approach is non optimal. If composite +power states are used, the PSCI implementation cannot make global +decisions about state coordination required because it does not understand the +platform specific states. + +The PSCI 1.0 implementation now defines a generic representation of the +power-state parameter : + + typedef struct psci_power_state { + plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + 1]; + } psci_power_state_t; + + +`pwr_domain_state` is an array where each index corresponds to a power level. +Each entry in the array contains the local power state the power domain at +that power level could enter. The meaning of the local power state value is +platform defined, and can vary between levels in a single platform. The PSCI +implementation constraints the values only so that it can classify the state +as RUN, RETENTION or OFF as required by the specification: + +1. Zero means RUN + +2. All OFF state values at all levels must be higher than all + RETENTION state values at all levels + +The platform is required to define the macros `PLAT_MAX_RET_STATE` and +`PLAT_MAX_OFF_STATE` to the framework. The requirement for these macros can +be found in the [Porting Guide]. + +The PSCI 1.0 implementation adds support to involve the platform in state +coordination. This enables the platform to decide the final target state. +During a request to place a power domain in a low power state, the platform +is passed an array of requested `plat_local_state_t` for that power domain by +each core within it through the `plat_get_target_pwr_state()` API. This API +coordinates amongst these requested states to determine a target +`plat_local_state_t` for that power domain. A default weak implementation of +this API is provided in the platform layer which returns the minimum of the +requested local states back to the PSCI state coordination. More details +of `plat_get_target_pwr_state()` API can be found in the +[Porting Guide][get_target_pwr_state]. + +The PSCI Generic implementation expects platform ports to populate the handlers +for the `plat_psci_ops` structure which is declared as : + + typedef struct plat_psci_ops { + void (*cpu_standby)(plat_local_state_t cpu_state); + int (*pwr_domain_on)(u_register_t mpidr); + void (*pwr_domain_off)(const psci_power_state_t *target_state); + void (*pwr_domain_suspend)(const psci_power_state_t *target_state); + void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); + void (*pwr_domain_suspend_finish)( + const psci_power_state_t *target_state); + void (*system_off)(void) __dead2; + void (*system_reset)(void) __dead2; + int (*validate_power_state)(unsigned int power_state, + psci_power_state_t *req_state); + int (*validate_ns_entrypoint)(unsigned long ns_entrypoint); + void (*get_sys_suspend_power_state)( + psci_power_state_t *req_state); + } plat_psci_ops_t; + +The description of these handlers can be found in the [Porting Guide][psci_ops]. +The previous `plat_pm_ops` structure is deprecated. Compared with the previous +handlers, the major differences are: + +* Difference in parameters + +The PSCI 1.0 implementation depends on the `validate_power_state` handler to +convert the power-state parameter (possibly encoding a composite power state) +passed in a PSCI `CPU_SUSPEND` to the `psci_power_state` format. This handler +is now mandatory for PSCI `CPU_SUSPEND` support. + +The `plat_psci_ops` handlers, `pwr_domain_off` and `pwr_domain_suspend`, are +passed the target local state for each affected power domain. The platform +must execute operations specific to these target states. Similarly, +`pwr_domain_on_finish` and `pwr_domain_suspend_finish` are passed the local +states of the affected power domains before wakeup. The platform +must execute actions to restore these power domains from these specific +local states. + +* Difference in invocation + +Whereas the power management handlers in `plat_pm_ops` used to be invoked +for each affinity level till the target affinity level, the new handlers +are only invoked once. The `target_state` encodes the target low power +state or the low power state woken up from for each affected power domain. + +* Difference in semantics + +Although the previous `suspend` handlers could be used for power down as well +as retention at different affinity levels, the new handlers make this support +explicit. The `pwr_domain_suspend` can be used to specify powerdown and +retention at various power domain levels subject to the conditions mentioned +in section 4.2.1 of [PSCI] + +Unlike the previous `standby` handler, the `cpu_standby()` handler is only used +as a fast path for placing a core power domain into a standby or retention +state. + +The below diagram shows the sequence of a PSCI SUSPEND call and the interaction +with the platform layer depicting the exchange of data between PSCI Generic +layer and the platform layer. + +![Image 1](diagrams/psci-suspend-sequence.png?raw=true) + +Refer [plat/arm/board/fvp/fvp_pm.c] for the implementation details of +these handlers for the FVP. The commit 38dce70f51fb83b27958ba3e2ad15f5635cb1061 +demonstrates the migration of ARM reference platforms to the new platform API. + + +2.3 Miscellaneous modifications +------------------------------- + +In addition to the framework changes, unification of warm reset entry points on +wakeup from low power modes has led to a change in the platform API. In the +earlier implementation, the warm reset entry used to be programmed into the +mailboxes by the 'ON' and 'SUSPEND' power management hooks. In the PSCI 1.0 +implementation, this information is not required, because it can figure that +out by querying affinity info state whether to execute the 'suspend_finisher` +or 'on_finisher'. + +As a result, the warm reset entry point must be programmed only once. The +`plat_setup_psci_ops()` API takes the secure entry point as an +additional parameter to enable the platforms to configure their mailbox. The +plat_psci_ops handlers `pwr_domain_on` and `pwr_domain_suspend` no longer take +the warm reset entry point as a parameter. + +Also, some platform APIs which took `MPIDR` as an argument were only ever +invoked to perform actions specific to the caller core which makes the argument +redundant. Therefore the platform APIs `plat_get_my_entrypoint()`, +`plat_is_my_cpu_primary()`, `plat_set_my_stack()` and +`plat_get_my_stack()` are defined which are meant to be invoked only for +operations on the current caller core instead of `platform_get_entrypoint()`, +`platform_is_primary_cpu()`, `platform_set_stack()` and `platform_get_stack()`. + + +3. Compatibility layer +---------------------- + +To ease the migration of the platform ports to the new porting interface, +a compatibility layer is introduced that essentially implements a glue layer +between the old platform API and the new API. The build flag +`ENABLE_PLAT_COMPAT` (enabled by default), specifies whether to enable this +layer or not. A platform port which has migrated to the new API can disable +this flag within the platform specific makefile. + +The compatibility layer works on the assumption that the onus of +state coordination, in case multiple low power states are supported, +is with the platform. The generic PSCI implementation only takes into +account whether the suspend request is power down or not. This corresponds +with the behavior of the PSCI implementation before the introduction of +new frameworks. Also, it assumes that the affinity levels of the platform +correspond directly to the power domain levels. + +The compatibility layer dynamically constructs the new topology +description array by querying the platform using `plat_get_aff_count()` +and `plat_get_aff_state()` APIs. The linear index returned by +`platform_get_core_pos()` is used as the core index for the cores. The +higher level (non-core) power domain nodes must know the cores contained +within its domain. It does so by storing the core index of first core +within it and number of core indexes following it. This means that core +indices returned by `platform_get_core_pos()` for cores within a particular +power domain must be consecutive. We expect that this is the case for most +platform ports including ARM reference platforms. + +The old PSCI helpers like `psci_get_suspend_powerstate()`, +`psci_get_suspend_stateid()`, `psci_get_suspend_stateid_by_mpidr()`, +`psci_get_max_phys_off_afflvl()` and `psci_get_suspend_afflvl()` are also +implemented for the compatibility layer. This allows the existing +platform ports to work with the new PSCI frameworks without significant +rework. + + +4. Deprecated Platform API +--------------------------- + +This section documents the deprecated platform porting API. + +## Common mandatory modifications + +The mandatory macros to be defined by the platform port in `platform_def.h` + +* **#define : PLATFORM_NUM_AFFS** + + Defines the total number of nodes in the affinity hierarchy at all affinity + levels used by the platform. + +* **#define : PLATFORM_MAX_AFFLVL** + + Defines the maximum affinity level that the power management operations + should apply to. ARMv8-A has support for four affinity levels. It is likely + that hardware will implement fewer affinity levels. This macro allows the + PSCI implementation to consider only those affinity levels in the system + that the platform implements. For example, the Base AEM FVP implements two + clusters with a configurable number of cores. It reports the maximum + affinity level as 1, resulting in PSCI power control up to the cluster + level. + +The following functions must be implemented by the platform port to enable +the reset vector code to perform the required tasks. + +### Function : platform_get_entrypoint() [mandatory] + + Argument : unsigned long + Return : unsigned long + +This function is called with the `SCTLR.M` and `SCTLR.C` bits disabled. The core +is identified by its `MPIDR`, which is passed as the argument. The function is +responsible for distinguishing between a warm and cold reset using platform- +specific means. If it is a warm reset, it returns the entrypoint into the +BL31 image that the core must jump to. If it is a cold reset, this function +must return zero. + +This function is also responsible for implementing a platform-specific mechanism +to handle the condition where the core has been warm reset but there is no +entrypoint to jump to. + +This function does not follow the Procedure Call Standard used by the +Application Binary Interface for the ARM 64-bit architecture. The caller should +not assume that callee saved registers are preserved across a call to this +function. + +### Function : platform_is_primary_cpu() [mandatory] + + Argument : unsigned long + Return : unsigned int + +This function identifies a core by its `MPIDR`, which is passed as the argument, +to determine whether this core is the primary core or a secondary core. A return +value of zero indicates that the core is not the primary core, while a non-zero +return value indicates that the core is the primary core. + +## Common optional modifications + +### Function : platform_get_core_pos() + + Argument : unsigned long + Return : int + +A platform may need to convert the `MPIDR` of a core to an absolute number, which +can be used as a core-specific linear index into blocks of memory (for example +while allocating per-core stacks). This routine contains a simple mechanism +to perform this conversion, using the assumption that each cluster contains a +maximum of four cores: + + linear index = cpu_id + (cluster_id * 4) + + cpu_id = 8-bit value in MPIDR at affinity level 0 + cluster_id = 8-bit value in MPIDR at affinity level 1 + + +### Function : platform_set_stack() + + Argument : unsigned long + Return : void + +This function sets the current stack pointer to the normal memory stack that +has been allocated for the core specified by MPIDR. For BL images that only +require a stack for the primary core the parameter is ignored. The size of +the stack allocated to each core is specified by the platform defined constant +`PLATFORM_STACK_SIZE`. + +Common implementations of this function for the UP and MP BL images are +provided in [plat/common/aarch64/platform_up_stack.S] and +[plat/common/aarch64/platform_mp_stack.S] + + +### Function : platform_get_stack() + + Argument : unsigned long + Return : unsigned long + +This function returns the base address of the normal memory stack that +has been allocated for the core specificed by MPIDR. For BL images that only +require a stack for the primary core the parameter is ignored. The size of +the stack allocated to each core is specified by the platform defined constant +`PLATFORM_STACK_SIZE`. + +Common implementations of this function for the UP and MP BL images are +provided in [plat/common/aarch64/platform_up_stack.S] and +[plat/common/aarch64/platform_mp_stack.S] + + +## Modifications for Power State Coordination Interface (in BL31) + +The following functions must be implemented to initialize PSCI functionality in +the ARM Trusted Firmware. + + +### Function : plat_get_aff_count() [mandatory] + + Argument : unsigned int, unsigned long + Return : unsigned int + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initializations in `bl31_plat_arch_setup()`. It is only +called by the primary core. + +This function is called by the PSCI initialization code to detect the system +topology. Its purpose is to return the number of affinity instances implemented +at a given `affinity level` (specified by the first argument) and a given +`MPIDR` (specified by the second argument). For example, on a dual-cluster +system where first cluster implements two cores and the second cluster +implements four cores, a call to this function with an `MPIDR` corresponding +to the first cluster (`0x0`) and affinity level 0, would return 2. A call +to this function with an `MPIDR` corresponding to the second cluster (`0x100`) +and affinity level 0, would return 4. + + +### Function : plat_get_aff_state() [mandatory] + + Argument : unsigned int, unsigned long + Return : unsigned int + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initializations in `bl31_plat_arch_setup()`. It is only +called by the primary core. + +This function is called by the PSCI initialization code. Its purpose is to +return the state of an affinity instance. The affinity instance is determined by +the affinity ID at a given `affinity level` (specified by the first argument) +and an `MPIDR` (specified by the second argument). The state can be one of +`PSCI_AFF_PRESENT` or `PSCI_AFF_ABSENT`. The latter state is used to cater for +system topologies where certain affinity instances are unimplemented. For +example, consider a platform that implements a single cluster with four cores and +another core implemented directly on the interconnect with the cluster. The +`MPIDR`s of the cluster would range from `0x0-0x3`. The `MPIDR` of the single +core is 0x100 to indicate that it does not belong to cluster 0. Cluster 1 +is missing but needs to be accounted for to reach this single core in the +topology tree. Therefore it is marked as `PSCI_AFF_ABSENT`. + + +### Function : platform_setup_pm() [mandatory] + + Argument : const plat_pm_ops ** + Return : int + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initializations in `bl31_plat_arch_setup()`. It is only +called by the primary core. + +This function is called by PSCI initialization code. Its purpose is to export +handler routines for platform-specific power management actions by populating +the passed pointer with a pointer to the private `plat_pm_ops` structure of +BL31. + +A description of each member of this structure is given below. A platform port +is expected to implement these handlers if the corresponding PSCI operation +is to be supported and these handlers are expected to succeed if the return +type is `void`. + +#### plat_pm_ops.affinst_standby() + +Perform the platform-specific setup to enter the standby state indicated by the +passed argument. The generic code expects the handler to succeed. + +#### plat_pm_ops.affinst_on() + +Perform the platform specific setup to power on an affinity instance, specified +by the `MPIDR` (first argument) and `affinity level` (third argument). The +`state` (fourth argument) contains the current state of that affinity instance +(ON or OFF). This is useful to determine whether any action must be taken. For +example, while powering on a core, the cluster that contains this core might +already be in the ON state. The platform decides what actions must be taken to +transition from the current state to the target state (indicated by the power +management operation). The generic code expects the platform to return +E_SUCCESS on success or E_INTERN_FAIL for any failure. + +#### plat_pm_ops.affinst_off() + +Perform the platform specific setup to power off an affinity instance of the +calling core. It is called by the PSCI `CPU_OFF` API implementation. + +The `affinity level` (first argument) and `state` (second argument) have +a similar meaning as described in the `affinst_on()` operation. They +identify the affinity instance on which the call is made and its +current state. This gives the platform port an indication of the +state transition it must make to perform the requested action. For example, if +the calling core is the last powered on core in the cluster, after powering down +affinity level 0 (the core), the platform port should power down affinity +level 1 (the cluster) as well. The generic code expects the handler to succeed. + +#### plat_pm_ops.affinst_suspend() + +Perform the platform specific setup to power off an affinity instance of the +calling core. It is called by the PSCI `CPU_SUSPEND` API and `SYSTEM_SUSPEND` +API implementation + +The `affinity level` (second argument) and `state` (third argument) have a +similar meaning as described in the `affinst_on()` operation. They are used to +identify the affinity instance on which the call is made and its current state. +This gives the platform port an indication of the state transition it must +make to perform the requested action. For example, if the calling core is the +last powered on core in the cluster, after powering down affinity level 0 +(the core), the platform port should power down affinity level 1 (the cluster) +as well. + +The difference between turning an affinity instance off and suspending it +is that in the former case, the affinity instance is expected to re-initialize +its state when it is next powered on (see `affinst_on_finish()`). In the latter +case, the affinity instance is expected to save enough state so that it can +resume execution by restoring this state when it is powered on (see +`affinst_suspend_finish()`).The generic code expects the handler to succeed. + +#### plat_pm_ops.affinst_on_finish() + +This function is called by the PSCI implementation after the calling core is +powered on and released from reset in response to an earlier PSCI `CPU_ON` call. +It performs the platform-specific setup required to initialize enough state for +this core to enter the Normal world and also provide secure runtime firmware +services. + +The `affinity level` (first argument) and `state` (second argument) have a +similar meaning as described in the previous operations. The generic code +expects the handler to succeed. + +#### plat_pm_ops.affinst_suspend_finish() + +This function is called by the PSCI implementation after the calling core is +powered on and released from reset in response to an asynchronous wakeup +event, for example a timer interrupt that was programmed by the core during the +`CPU_SUSPEND` call or `SYSTEM_SUSPEND` call. It performs the platform-specific +setup required to restore the saved state for this core to resume execution +in the Normal world and also provide secure runtime firmware services. + +The `affinity level` (first argument) and `state` (second argument) have a +similar meaning as described in the previous operations. The generic code +expects the platform to succeed. + +#### plat_pm_ops.validate_power_state() + +This function is called by the PSCI implementation during the `CPU_SUSPEND` +call to validate the `power_state` parameter of the PSCI API. If the +`power_state` is known to be invalid, the platform must return +PSCI_E_INVALID_PARAMS as an error, which is propagated back to the Normal +world PSCI client. + +#### plat_pm_ops.validate_ns_entrypoint() + +This function is called by the PSCI implementation during the `CPU_SUSPEND`, +`SYSTEM_SUSPEND` and `CPU_ON` calls to validate the Non-secure `entry_point` +parameter passed by the Normal world. If the `entry_point` is known to be +invalid, the platform must return PSCI_E_INVALID_PARAMS as an error, which is +propagated back to the Normal world PSCI client. + +#### plat_pm_ops.get_sys_suspend_power_state() + +This function is called by the PSCI implementation during the `SYSTEM_SUSPEND` +call to return the `power_state` parameter. This allows the platform to encode +the appropriate State-ID field within the `power_state` parameter which can be +utilized in `affinst_suspend()` to suspend to system affinity level. The +`power_state` parameter should be in the same format as specified by the +PSCI specification for the CPU_SUSPEND API. + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2015, ARM Limited and Contributors. All rights reserved._ + + +[Porting Guide]: porting-guide.md +[Power Domain Topology Design]: psci-pd-tree.md +[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf +[psci pd tree]: psci-pd-tree.md +[my_core_pos]: porting-guide.md#function--plat_my_core_pos +[get_target_pwr_state]: porting-guide.md#function--plat_get_target_pwr_state-optional +[psci_ops]: porting-guide.md#function--plat_setup_psci_ops-mandatory +[plat/arm/board/fvp/fvp_pm.c]: ../plat/arm/board/fvp/fvp_pm.c +[plat/common/aarch64/platform_mp_stack.S]: ../plat/common/aarch64/platform_mp_stack.S +[plat/common/aarch64/platform_up_stack.S]: ../plat/common/aarch64/platform_up_stack.S diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/porting-guide.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/porting-guide.md new file mode 100644 index 0000000..8e913b9 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/porting-guide.md @@ -0,0 +1,2245 @@ +ARM Trusted Firmware Porting Guide +================================== + +Contents +-------- + +1. [Introduction](#1--introduction) +2. [Common Modifications](#2--common-modifications) + * [Common mandatory modifications](#21-common-mandatory-modifications) + * [Handling reset](#22-handling-reset) + * [Common mandatory function modifications](#23-common-mandatory-function-modifications) + * [Common optional modifications](#24-common-optional-modifications) +3. [Boot Loader stage specific modifications](#3--modifications-specific-to-a-boot-loader-stage) + * [Boot Loader stage 1 (BL1)](#31-boot-loader-stage-1-bl1) + * [Boot Loader stage 2 (BL2)](#32-boot-loader-stage-2-bl2) + * [FWU Boot Loader stage 2 (BL2U)](#33-fwu-boot-loader-stage-2-bl2u) + * [Boot Loader stage 3-1 (BL31)](#34-boot-loader-stage-3-1-bl31) + * [PSCI implementation (in BL31)](#35-power-state-coordination-interface-in-bl31) + * [Interrupt Management framework (in BL31)](#36--interrupt-management-framework-in-bl31) + * [Crash Reporting mechanism (in BL31)](#37--crash-reporting-mechanism-in-bl31) +4. [Build flags](#4--build-flags) +5. [C Library](#5--c-library) +6. [Storage abstraction layer](#6--storage-abstraction-layer) + +- - - - - - - - - - - - - - - - - - + +1. Introduction +---------------- + +Please note that this document has been updated for the new platform API +as required by the PSCI v1.0 implementation. Please refer to the +[Migration Guide] for the previous platform API. + +Porting the ARM Trusted Firmware to a new platform involves making some +mandatory and optional modifications for both the cold and warm boot paths. +Modifications consist of: + +* Implementing a platform-specific function or variable, +* Setting up the execution context in a certain way, or +* Defining certain constants (for example #defines). + +The platform-specific functions and variables are declared in +[include/plat/common/platform.h]. The firmware provides a default implementation +of variables and functions to fulfill the optional requirements. These +implementations are all weakly defined; they are provided to ease the porting +effort. Each platform port can override them with its own implementation if the +default implementation is inadequate. + +Platform ports that want to be aligned with standard ARM platforms (for example +FVP and Juno) may also use [include/plat/arm/common/plat_arm.h] and the +corresponding source files in `plat/arm/common/`. These provide standard +implementations for some of the required platform porting functions. However, +using these functions requires the platform port to implement additional +ARM standard platform porting functions. These additional functions are not +documented here. + +Some modifications are common to all Boot Loader (BL) stages. Section 2 +discusses these in detail. The subsequent sections discuss the remaining +modifications for each BL stage in detail. + +This document should be read in conjunction with the ARM Trusted Firmware +[User Guide]. + + +2. Common modifications +------------------------ + +This section covers the modifications that should be made by the platform for +each BL stage to correctly port the firmware stack. They are categorized as +either mandatory or optional. + + +2.1 Common mandatory modifications +---------------------------------- + +A platform port must enable the Memory Management Unit (MMU) as well as the +instruction and data caches for each BL stage. Setting up the translation +tables is the responsibility of the platform port because memory maps differ +across platforms. A memory translation library (see `lib/xlat_tables/`) is +provided to help in this setup. Note that although this library supports +non-identity mappings, this is intended only for re-mapping peripheral physical +addresses and allows platforms with high I/O addresses to reduce their virtual +address space. All other addresses corresponding to code and data must currently +use an identity mapping. + +In ARM standard platforms, each BL stage configures the MMU in the +platform-specific architecture setup function, `blX_plat_arch_setup()`, and uses +an identity mapping for all addresses. + +If the build option `USE_COHERENT_MEM` is enabled, each platform can allocate a +block of identity mapped secure memory with Device-nGnRE attributes aligned to +page boundary (4K) for each BL stage. All sections which allocate coherent +memory are grouped under `coherent_ram`. For ex: Bakery locks are placed in a +section identified by name `bakery_lock` inside `coherent_ram` so that its +possible for the firmware to place variables in it using the following C code +directive: + + __section("bakery_lock") + +Or alternatively the following assembler code directive: + + .section bakery_lock + +The `coherent_ram` section is a sum of all sections like `bakery_lock` which are +used to allocate any data structures that are accessed both when a CPU is +executing with its MMU and caches enabled, and when it's running with its MMU +and caches disabled. Examples are given below. + +The following variables, functions and constants must be defined by the platform +for the firmware to work correctly. + + +### File : platform_def.h [mandatory] + +Each platform must ensure that a header file of this name is in the system +include path with the following constants defined. This may require updating the +list of `PLAT_INCLUDES` in the `platform.mk` file. In the ARM development +platforms, this file is found in `plat/arm/board//include/`. + +Platform ports may optionally use the file [include/plat/common/common_def.h], +which provides typical values for some of the constants below. These values are +likely to be suitable for all platform ports. + +Platform ports that want to be aligned with standard ARM platforms (for example +FVP and Juno) may also use [include/plat/arm/common/arm_def.h], which provides +standard values for some of the constants below. However, this requires the +platform port to define additional platform porting constants in +`platform_def.h`. These additional constants are not documented here. + +* **#define : PLATFORM_LINKER_FORMAT** + + Defines the linker format used by the platform, for example + `elf64-littleaarch64`. + +* **#define : PLATFORM_LINKER_ARCH** + + Defines the processor architecture for the linker by the platform, for + example `aarch64`. + +* **#define : PLATFORM_STACK_SIZE** + + Defines the normal stack memory available to each CPU. This constant is used + by [plat/common/aarch64/platform_mp_stack.S] and + [plat/common/aarch64/platform_up_stack.S]. + +* **define : CACHE_WRITEBACK_GRANULE** + + Defines the size in bits of the largest cache line across all the cache + levels in the platform. + +* **#define : FIRMWARE_WELCOME_STR** + + Defines the character string printed by BL1 upon entry into the `bl1_main()` + function. + +* **#define : PLATFORM_CORE_COUNT** + + Defines the total number of CPUs implemented by the platform across all + clusters in the system. + +* **#define : PLAT_NUM_PWR_DOMAINS** + + Defines the total number of nodes in the power domain topology + tree at all the power domain levels used by the platform. + This macro is used by the PSCI implementation to allocate + data structures to represent power domain topology. + +* **#define : PLAT_MAX_PWR_LVL** + + Defines the maximum power domain level that the power management operations + should apply to. More often, but not always, the power domain level + corresponds to affinity level. This macro allows the PSCI implementation + to know the highest power domain level that it should consider for power + management operations in the system that the platform implements. For + example, the Base AEM FVP implements two clusters with a configurable + number of CPUs and it reports the maximum power domain level as 1. + +* **#define : PLAT_MAX_OFF_STATE** + + Defines the local power state corresponding to the deepest power down + possible at every power domain level in the platform. The local power + states for each level may be sparsely allocated between 0 and this value + with 0 being reserved for the RUN state. The PSCI implementation uses this + value to initialize the local power states of the power domain nodes and + to specify the requested power state for a PSCI_CPU_OFF call. + +* **#define : PLAT_MAX_RET_STATE** + + Defines the local power state corresponding to the deepest retention state + possible at every power domain level in the platform. This macro should be + a value less than PLAT_MAX_OFF_STATE and greater than 0. It is used by the + PSCI implementation to distinguish between retention and power down local + power states within PSCI_CPU_SUSPEND call. + +* **#define : PLAT_MAX_PWR_LVL_STATES** + + Defines the maximum number of local power states per power domain level + that the platform supports. The default value of this macro is 2 since + most platforms just support a maximum of two local power states at each + power domain level (power-down and retention). If the platform needs to + account for more local power states, then it must redefine this macro. + + Currently, this macro is used by the Generic PSCI implementation to size + the array used for PSCI_STAT_COUNT/RESIDENCY accounting. + +* **#define : BL1_RO_BASE** + + Defines the base address in secure ROM where BL1 originally lives. Must be + aligned on a page-size boundary. + +* **#define : BL1_RO_LIMIT** + + Defines the maximum address in secure ROM that BL1's actual content (i.e. + excluding any data section allocated at runtime) can occupy. + +* **#define : BL1_RW_BASE** + + Defines the base address in secure RAM where BL1's read-write data will live + at runtime. Must be aligned on a page-size boundary. + +* **#define : BL1_RW_LIMIT** + + Defines the maximum address in secure RAM that BL1's read-write data can + occupy at runtime. + +* **#define : BL2_BASE** + + Defines the base address in secure RAM where BL1 loads the BL2 binary image. + Must be aligned on a page-size boundary. + +* **#define : BL2_LIMIT** + + Defines the maximum address in secure RAM that the BL2 image can occupy. + +* **#define : BL31_BASE** + + Defines the base address in secure RAM where BL2 loads the BL31 binary + image. Must be aligned on a page-size boundary. + +* **#define : BL31_LIMIT** + + Defines the maximum address in secure RAM that the BL31 image can occupy. + +For every image, the platform must define individual identifiers that will be +used by BL1 or BL2 to load the corresponding image into memory from non-volatile +storage. For the sake of performance, integer numbers will be used as +identifiers. The platform will use those identifiers to return the relevant +information about the image to be loaded (file handler, load address, +authentication information, etc.). The following image identifiers are +mandatory: + +* **#define : BL2_IMAGE_ID** + + BL2 image identifier, used by BL1 to load BL2. + +* **#define : BL31_IMAGE_ID** + + BL31 image identifier, used by BL2 to load BL31. + +* **#define : BL33_IMAGE_ID** + + BL33 image identifier, used by BL2 to load BL33. + +If Trusted Board Boot is enabled, the following certificate identifiers must +also be defined: + +* **#define : TRUSTED_BOOT_FW_CERT_ID** + + BL2 content certificate identifier, used by BL1 to load the BL2 content + certificate. + +* **#define : TRUSTED_KEY_CERT_ID** + + Trusted key certificate identifier, used by BL2 to load the trusted key + certificate. + +* **#define : SOC_FW_KEY_CERT_ID** + + BL31 key certificate identifier, used by BL2 to load the BL31 key + certificate. + +* **#define : SOC_FW_CONTENT_CERT_ID** + + BL31 content certificate identifier, used by BL2 to load the BL31 content + certificate. + +* **#define : NON_TRUSTED_FW_KEY_CERT_ID** + + BL33 key certificate identifier, used by BL2 to load the BL33 key + certificate. + +* **#define : NON_TRUSTED_FW_CONTENT_CERT_ID** + + BL33 content certificate identifier, used by BL2 to load the BL33 content + certificate. + +* **#define : FWU_CERT_ID** + + Firmware Update (FWU) certificate identifier, used by NS_BL1U to load the + FWU content certificate. + + +If the AP Firmware Updater Configuration image, BL2U is used, the following +must also be defined: + +* **#define : BL2U_BASE** + + Defines the base address in secure memory where BL1 copies the BL2U binary + image. Must be aligned on a page-size boundary. + +* **#define : BL2U_LIMIT** + + Defines the maximum address in secure memory that the BL2U image can occupy. + +* **#define : BL2U_IMAGE_ID** + + BL2U image identifier, used by BL1 to fetch an image descriptor + corresponding to BL2U. + +If the SCP Firmware Update Configuration Image, SCP_BL2U is used, the following +must also be defined: + +* **#define : SCP_BL2U_IMAGE_ID** + + SCP_BL2U image identifier, used by BL1 to fetch an image descriptor + corresponding to SCP_BL2U. + NOTE: TF does not provide source code for this image. + +If the Non-Secure Firmware Updater ROM, NS_BL1U is used, the following must +also be defined: + +* **#define : NS_BL1U_BASE** + + Defines the base address in non-secure ROM where NS_BL1U executes. + Must be aligned on a page-size boundary. + NOTE: TF does not provide source code for this image. + +* **#define : NS_BL1U_IMAGE_ID** + + NS_BL1U image identifier, used by BL1 to fetch an image descriptor + corresponding to NS_BL1U. + +If the Non-Secure Firmware Updater, NS_BL2U is used, the following must also +be defined: + +* **#define : NS_BL2U_BASE** + + Defines the base address in non-secure memory where NS_BL2U executes. + Must be aligned on a page-size boundary. + NOTE: TF does not provide source code for this image. + +* **#define : NS_BL2U_IMAGE_ID** + + NS_BL2U image identifier, used by BL1 to fetch an image descriptor + corresponding to NS_BL2U. + + +If a SCP_BL2 image is supported by the platform, the following constants must +also be defined: + +* **#define : SCP_BL2_IMAGE_ID** + + SCP_BL2 image identifier, used by BL2 to load SCP_BL2 into secure memory + from platform storage before being transfered to the SCP. + +* **#define : SCP_FW_KEY_CERT_ID** + + SCP_BL2 key certificate identifier, used by BL2 to load the SCP_BL2 key + certificate (mandatory when Trusted Board Boot is enabled). + +* **#define : SCP_FW_CONTENT_CERT_ID** + + SCP_BL2 content certificate identifier, used by BL2 to load the SCP_BL2 + content certificate (mandatory when Trusted Board Boot is enabled). + +If a BL32 image is supported by the platform, the following constants must +also be defined: + +* **#define : BL32_IMAGE_ID** + + BL32 image identifier, used by BL2 to load BL32. + +* **#define : TRUSTED_OS_FW_KEY_CERT_ID** + + BL32 key certificate identifier, used by BL2 to load the BL32 key + certificate (mandatory when Trusted Board Boot is enabled). + +* **#define : TRUSTED_OS_FW_CONTENT_CERT_ID** + + BL32 content certificate identifier, used by BL2 to load the BL32 content + certificate (mandatory when Trusted Board Boot is enabled). + +* **#define : BL32_BASE** + + Defines the base address in secure memory where BL2 loads the BL32 binary + image. Must be aligned on a page-size boundary. + +* **#define : BL32_LIMIT** + + Defines the maximum address that the BL32 image can occupy. + +If the Test Secure-EL1 Payload (TSP) instantiation of BL32 is supported by the +platform, the following constants must also be defined: + +* **#define : TSP_SEC_MEM_BASE** + + Defines the base address of the secure memory used by the TSP image on the + platform. This must be at the same address or below `BL32_BASE`. + +* **#define : TSP_SEC_MEM_SIZE** + + Defines the size of the secure memory used by the BL32 image on the + platform. `TSP_SEC_MEM_BASE` and `TSP_SEC_MEM_SIZE` must fully accomodate + the memory required by the BL32 image, defined by `BL32_BASE` and + `BL32_LIMIT`. + +* **#define : TSP_IRQ_SEC_PHY_TIMER** + + Defines the ID of the secure physical generic timer interrupt used by the + TSP's interrupt handling code. + +If the platform port uses the translation table library code, the following +constant must also be defined: + +* **#define : MAX_XLAT_TABLES** + + Defines the maximum number of translation tables that are allocated by the + translation table library code. To minimize the amount of runtime memory + used, choose the smallest value needed to map the required virtual addresses + for each BL stage. + +* **#define : MAX_MMAP_REGIONS** + + Defines the maximum number of regions that are allocated by the translation + table library code. A region consists of physical base address, virtual base + address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as + defined in the `mmap_region_t` structure. The platform defines the regions + that should be mapped. Then, the translation table library will create the + corresponding tables and descriptors at runtime. To minimize the amount of + runtime memory used, choose the smallest value needed to register the + required regions for each BL stage. + +* **#define : ADDR_SPACE_SIZE** + + Defines the total size of the address space in bytes. For example, for a 32 + bit address space, this value should be `(1ull << 32)`. + +If the platform port uses the IO storage framework, the following constants +must also be defined: + +* **#define : MAX_IO_DEVICES** + + Defines the maximum number of registered IO devices. Attempting to register + more devices than this value using `io_register_device()` will fail with + -ENOMEM. + +* **#define : MAX_IO_HANDLES** + + Defines the maximum number of open IO handles. Attempting to open more IO + entities than this value using `io_open()` will fail with -ENOMEM. + +* **#define : MAX_IO_BLOCK_DEVICES** + + Defines the maximum number of registered IO block devices. Attempting to + register more devices this value using `io_dev_open()` will fail + with -ENOMEM. MAX_IO_BLOCK_DEVICES should be less than MAX_IO_DEVICES. + With this macro, multiple block devices could be supported at the same + time. + +If the platform needs to allocate data within the per-cpu data framework in +BL31, it should define the following macro. Currently this is only required if +the platform decides not to use the coherent memory section by undefining the +`USE_COHERENT_MEM` build flag. In this case, the framework allocates the +required memory within the the per-cpu data to minimize wastage. + +* **#define : PLAT_PCPU_DATA_SIZE** + + Defines the memory (in bytes) to be reserved within the per-cpu data + structure for use by the platform layer. + +The following constants are optional. They should be defined when the platform +memory layout implies some image overlaying like in ARM standard platforms. + +* **#define : BL31_PROGBITS_LIMIT** + + Defines the maximum address in secure RAM that the BL31's progbits sections + can occupy. + +* **#define : TSP_PROGBITS_LIMIT** + + Defines the maximum address that the TSP's progbits sections can occupy. + +If the platform port uses the PL061 GPIO driver, the following constant may +optionally be defined: + +* **PLAT_PL061_MAX_GPIOS** + Maximum number of GPIOs required by the platform. This allows control how + much memory is allocated for PL061 GPIO controllers. The default value is + 32. + [For example, define the build flag in platform.mk]: + PLAT_PL061_MAX_GPIOS := 160 + $(eval $(call add_define,PLAT_PL061_MAX_GPIOS)) + + +### File : plat_macros.S [mandatory] + +Each platform must ensure a file of this name is in the system include path with +the following macro defined. In the ARM development platforms, this file is +found in `plat/arm/board//include/plat_macros.S`. + +* **Macro : plat_crash_print_regs** + + This macro allows the crash reporting routine to print relevant platform + registers in case of an unhandled exception in BL31. This aids in debugging + and this macro can be defined to be empty in case register reporting is not + desired. + + For instance, GIC or interconnect registers may be helpful for + troubleshooting. + + +2.2 Handling Reset +------------------ + +BL1 by default implements the reset vector where execution starts from a cold +or warm boot. BL31 can be optionally set as a reset vector using the +`RESET_TO_BL31` make variable. + +For each CPU, the reset vector code is responsible for the following tasks: + +1. Distinguishing between a cold boot and a warm boot. + +2. In the case of a cold boot and the CPU being a secondary CPU, ensuring that + the CPU is placed in a platform-specific state until the primary CPU + performs the necessary steps to remove it from this state. + +3. In the case of a warm boot, ensuring that the CPU jumps to a platform- + specific address in the BL31 image in the same processor mode as it was + when released from reset. + +The following functions need to be implemented by the platform port to enable +reset vector code to perform the above tasks. + + +### Function : plat_get_my_entrypoint() [mandatory when PROGRAMMABLE_RESET_ADDRESS == 0] + + Argument : void + Return : uintptr_t + +This function is called with the called with the MMU and caches disabled +(`SCTLR_EL3.M` = 0 and `SCTLR_EL3.C` = 0). The function is responsible for +distinguishing between a warm and cold reset for the current CPU using +platform-specific means. If it's a warm reset, then it returns the warm +reset entrypoint point provided to `plat_setup_psci_ops()` during +BL31 initialization. If it's a cold reset then this function must return zero. + +This function does not follow the Procedure Call Standard used by the +Application Binary Interface for the ARM 64-bit architecture. The caller should +not assume that callee saved registers are preserved across a call to this +function. + +This function fulfills requirement 1 and 3 listed above. + +Note that for platforms that support programming the reset address, it is +expected that a CPU will start executing code directly at the right address, +both on a cold and warm reset. In this case, there is no need to identify the +type of reset nor to query the warm reset entrypoint. Therefore, implementing +this function is not required on such platforms. + + +### Function : plat_secondary_cold_boot_setup() [mandatory when COLD_BOOT_SINGLE_CPU == 0] + + Argument : void + +This function is called with the MMU and data caches disabled. It is responsible +for placing the executing secondary CPU in a platform-specific state until the +primary CPU performs the necessary actions to bring it out of that state and +allow entry into the OS. This function must not return. + +In the ARM FVP port, when using the normal boot flow, each secondary CPU powers +itself off. The primary CPU is responsible for powering up the secondary CPUs +when normal world software requires them. When booting an EL3 payload instead, +they stay powered on and are put in a holding pen until their mailbox gets +populated. + +This function fulfills requirement 2 above. + +Note that for platforms that can't release secondary CPUs out of reset, only the +primary CPU will execute the cold boot code. Therefore, implementing this +function is not required on such platforms. + + +### Function : plat_is_my_cpu_primary() [mandatory when COLD_BOOT_SINGLE_CPU == 0] + + Argument : void + Return : unsigned int + +This function identifies whether the current CPU is the primary CPU or a +secondary CPU. A return value of zero indicates that the CPU is not the +primary CPU, while a non-zero return value indicates that the CPU is the +primary CPU. + +Note that for platforms that can't release secondary CPUs out of reset, only the +primary CPU will execute the cold boot code. Therefore, there is no need to +distinguish between primary and secondary CPUs and implementing this function is +not required. + + +### Function : platform_mem_init() [mandatory] + + Argument : void + Return : void + +This function is called before any access to data is made by the firmware, in +order to carry out any essential memory initialization. + + +### Function: plat_get_rotpk_info() + + Argument : void *, void **, unsigned int *, unsigned int * + Return : int + +This function is mandatory when Trusted Board Boot is enabled. It returns a +pointer to the ROTPK stored in the platform (or a hash of it) and its length. +The ROTPK must be encoded in DER format according to the following ASN.1 +structure: + + AlgorithmIdentifier ::= SEQUENCE { + algorithm OBJECT IDENTIFIER, + parameters ANY DEFINED BY algorithm OPTIONAL + } + + SubjectPublicKeyInfo ::= SEQUENCE { + algorithm AlgorithmIdentifier, + subjectPublicKey BIT STRING + } + +In case the function returns a hash of the key: + + DigestInfo ::= SEQUENCE { + digestAlgorithm AlgorithmIdentifier, + digest OCTET STRING + } + +The function returns 0 on success. Any other value is treated as error by the +Trusted Board Boot. The function also reports extra information related +to the ROTPK in the flags parameter: + + ROTPK_IS_HASH : Indicates that the ROTPK returned by the platform is a + hash. + ROTPK_NOT_DEPLOYED : This allows the platform to skip certificate ROTPK + verification while the platform ROTPK is not deployed. + When this flag is set, the function does not need to + return a platform ROTPK, and the authentication + framework uses the ROTPK in the certificate without + verifying it against the platform value. This flag + must not be used in a deployed production environment. + +### Function: plat_get_nv_ctr() + + Argument : void *, unsigned int * + Return : int + +This function is mandatory when Trusted Board Boot is enabled. It returns the +non-volatile counter value stored in the platform in the second argument. The +cookie in the first argument may be used to select the counter in case the +platform provides more than one (for example, on platforms that use the default +TBBR CoT, the cookie will correspond to the OID values defined in +TRUSTED_FW_NVCOUNTER_OID or NON_TRUSTED_FW_NVCOUNTER_OID). + +The function returns 0 on success. Any other value means the counter value could +not be retrieved from the platform. + + +### Function: plat_set_nv_ctr() + + Argument : void *, unsigned int + Return : int + +This function is mandatory when Trusted Board Boot is enabled. It sets a new +counter value in the platform. The cookie in the first argument may be used to +select the counter (as explained in plat_get_nv_ctr()). + +The function returns 0 on success. Any other value means the counter value could +not be updated. + + +2.3 Common mandatory function modifications +--------------------------------- + +The following functions are mandatory functions which need to be implemented +by the platform port. + +### Function : plat_my_core_pos() + + Argument : void + Return : unsigned int + +This funtion returns the index of the calling CPU which is used as a +CPU-specific linear index into blocks of memory (for example while allocating +per-CPU stacks). This function will be invoked very early in the +initialization sequence which mandates that this function should be +implemented in assembly and should not rely on the avalability of a C +runtime environment. This function can clobber x0 - x8 and must preserve +x9 - x29. + +This function plays a crucial role in the power domain topology framework in +PSCI and details of this can be found in [Power Domain Topology Design]. + +### Function : plat_core_pos_by_mpidr() + + Argument : u_register_t + Return : int + +This function validates the `MPIDR` of a CPU and converts it to an index, +which can be used as a CPU-specific linear index into blocks of memory. In +case the `MPIDR` is invalid, this function returns -1. This function will only +be invoked by BL31 after the power domain topology is initialized and can +utilize the C runtime environment. For further details about how ARM Trusted +Firmware represents the power domain topology and how this relates to the +linear CPU index, please refer [Power Domain Topology Design]. + + +2.4 Common optional modifications +--------------------------------- + +The following are helper functions implemented by the firmware that perform +common platform-specific tasks. A platform may choose to override these +definitions. + +### Function : plat_set_my_stack() + + Argument : void + Return : void + +This function sets the current stack pointer to the normal memory stack that +has been allocated for the current CPU. For BL images that only require a +stack for the primary CPU, the UP version of the function is used. The size +of the stack allocated to each CPU is specified by the platform defined +constant `PLATFORM_STACK_SIZE`. + +Common implementations of this function for the UP and MP BL images are +provided in [plat/common/aarch64/platform_up_stack.S] and +[plat/common/aarch64/platform_mp_stack.S] + + +### Function : plat_get_my_stack() + + Argument : void + Return : uintptr_t + +This function returns the base address of the normal memory stack that +has been allocated for the current CPU. For BL images that only require a +stack for the primary CPU, the UP version of the function is used. The size +of the stack allocated to each CPU is specified by the platform defined +constant `PLATFORM_STACK_SIZE`. + +Common implementations of this function for the UP and MP BL images are +provided in [plat/common/aarch64/platform_up_stack.S] and +[plat/common/aarch64/platform_mp_stack.S] + + +### Function : plat_report_exception() + + Argument : unsigned int + Return : void + +A platform may need to report various information about its status when an +exception is taken, for example the current exception level, the CPU security +state (secure/non-secure), the exception type, and so on. This function is +called in the following circumstances: + +* In BL1, whenever an exception is taken. +* In BL2, whenever an exception is taken. + +The default implementation doesn't do anything, to avoid making assumptions +about the way the platform displays its status information. + +For AArch64, this function receives the exception type as its argument. +Possible values for exceptions types are listed in the +[include/common/bl_common.h] header file. Note that these constants are not +related to any architectural exception code; they are just an ARM Trusted +Firmware convention. + +For AArch32, this function receives the exception mode as its argument. +Possible values for exception modes are listed in the +[include/lib/aarch32/arch.h] header file. + +### Function : plat_reset_handler() + + Argument : void + Return : void + +A platform may need to do additional initialization after reset. This function +allows the platform to do the platform specific intializations. Platform +specific errata workarounds could also be implemented here. The api should +preserve the values of callee saved registers x19 to x29. + +The default implementation doesn't do anything. If a platform needs to override +the default implementation, refer to the [Firmware Design] for general +guidelines. + +### Function : plat_disable_acp() + + Argument : void + Return : void + +This api allows a platform to disable the Accelerator Coherency Port (if +present) during a cluster power down sequence. The default weak implementation +doesn't do anything. Since this api is called during the power down sequence, +it has restrictions for stack usage and it can use the registers x0 - x17 as +scratch registers. It should preserve the value in x18 register as it is used +by the caller to store the return address. + +### Function : plat_error_handler() + + Argument : int + Return : void + +This API is called when the generic code encounters an error situation from +which it cannot continue. It allows the platform to perform error reporting or +recovery actions (for example, reset the system). This function must not return. + +The parameter indicates the type of error using standard codes from `errno.h`. +Possible errors reported by the generic code are: + +* `-EAUTH`: a certificate or image could not be authenticated (when Trusted + Board Boot is enabled) +* `-ENOENT`: the requested image or certificate could not be found or an IO + error was detected +* `-ENOMEM`: resources exhausted. Trusted Firmware does not use dynamic + memory, so this error is usually an indication of an incorrect array size + +The default implementation simply spins. + +### Function : plat_panic_handler() + + Argument : void + Return : void + +This API is called when the generic code encounters an unexpected error +situation from which it cannot recover. This function must not return, +and must be implemented in assembly because it may be called before the C +environment is initialized. + +Note: The address from where it was called is stored in x30 (Link Register). +The default implementation simply spins. + + +### Function : plat_get_bl_image_load_info() + + Argument : void + Return : bl_load_info_t * + +This function returns pointer to the list of images that the platform has +populated to load. This function is currently invoked in BL2 to load the +BL3xx images, when LOAD_IMAGE_V2 is enabled. + +### Function : plat_get_next_bl_params() + + Argument : void + Return : bl_params_t * + +This function returns a pointer to the shared memory that the platform has +kept aside to pass trusted firmware related information that next BL image +needs. This function is currently invoked in BL2 to pass this information to +the next BL image, when LOAD_IMAGE_V2 is enabled. + +### Function : plat_flush_next_bl_params() + + Argument : void + Return : void + +This function flushes to main memory all the image params that are passed to +next image. This function is currently invoked in BL2 to flush this information +to the next BL image, when LOAD_IMAGE_V2 is enabled. + +3. Modifications specific to a Boot Loader stage +------------------------------------------------- + +3.1 Boot Loader Stage 1 (BL1) +----------------------------- + +BL1 implements the reset vector where execution starts from after a cold or +warm boot. For each CPU, BL1 is responsible for the following tasks: + +1. Handling the reset as described in section 2.2 + +2. In the case of a cold boot and the CPU being the primary CPU, ensuring that + only this CPU executes the remaining BL1 code, including loading and passing + control to the BL2 stage. + +3. Identifying and starting the Firmware Update process (if required). + +4. Loading the BL2 image from non-volatile storage into secure memory at the + address specified by the platform defined constant `BL2_BASE`. + +5. Populating a `meminfo` structure with the following information in memory, + accessible by BL2 immediately upon entry. + + meminfo.total_base = Base address of secure RAM visible to BL2 + meminfo.total_size = Size of secure RAM visible to BL2 + meminfo.free_base = Base address of secure RAM available for + allocation to BL2 + meminfo.free_size = Size of secure RAM available for allocation to BL2 + + BL1 places this `meminfo` structure at the beginning of the free memory + available for its use. Since BL1 cannot allocate memory dynamically at the + moment, its free memory will be available for BL2's use as-is. However, this + means that BL2 must read the `meminfo` structure before it starts using its + free memory (this is discussed in Section 3.2). + + In future releases of the ARM Trusted Firmware it will be possible for + the platform to decide where it wants to place the `meminfo` structure for + BL2. + + BL1 implements the `bl1_init_bl2_mem_layout()` function to populate the + BL2 `meminfo` structure. The platform may override this implementation, for + example if the platform wants to restrict the amount of memory visible to + BL2. Details of how to do this are given below. + +The following functions need to be implemented by the platform port to enable +BL1 to perform the above tasks. + + +### Function : bl1_early_platform_setup() [mandatory] + + Argument : void + Return : void + +This function executes with the MMU and data caches disabled. It is only called +by the primary CPU. + +On ARM standard platforms, this function: + +* Enables a secure instance of SP805 to act as the Trusted Watchdog. + +* Initializes a UART (PL011 console), which enables access to the `printf` + family of functions in BL1. + +* Enables issuing of snoop and DVM (Distributed Virtual Memory) requests to + the CCI slave interface corresponding to the cluster that includes the + primary CPU. + +### Function : bl1_plat_arch_setup() [mandatory] + + Argument : void + Return : void + +This function performs any platform-specific and architectural setup that the +platform requires. Platform-specific setup might include configuration of +memory controllers and the interconnect. + +In ARM standard platforms, this function enables the MMU. + +This function helps fulfill requirement 2 above. + + +### Function : bl1_platform_setup() [mandatory] + + Argument : void + Return : void + +This function executes with the MMU and data caches enabled. It is responsible +for performing any remaining platform-specific setup that can occur after the +MMU and data cache have been enabled. + +In ARM standard platforms, this function initializes the storage abstraction +layer used to load the next bootloader image. + +This function helps fulfill requirement 4 above. + + +### Function : bl1_plat_sec_mem_layout() [mandatory] + + Argument : void + Return : meminfo * + +This function should only be called on the cold boot path. It executes with the +MMU and data caches enabled. The pointer returned by this function must point to +a `meminfo` structure containing the extents and availability of secure RAM for +the BL1 stage. + + meminfo.total_base = Base address of secure RAM visible to BL1 + meminfo.total_size = Size of secure RAM visible to BL1 + meminfo.free_base = Base address of secure RAM available for allocation + to BL1 + meminfo.free_size = Size of secure RAM available for allocation to BL1 + +This information is used by BL1 to load the BL2 image in secure RAM. BL1 also +populates a similar structure to tell BL2 the extents of memory available for +its own use. + +This function helps fulfill requirements 4 and 5 above. + + +### Function : bl1_init_bl2_mem_layout() [optional] + + Argument : meminfo *, meminfo * + Return : void + +BL1 needs to tell the next stage the amount of secure RAM available +for it to use. This information is populated in a `meminfo` +structure. + +Depending upon where BL2 has been loaded in secure RAM (determined by +`BL2_BASE`), BL1 calculates the amount of free memory available for BL2 to use. +BL1 also ensures that its data sections resident in secure RAM are not visible +to BL2. An illustration of how this is done in ARM standard platforms is given +in the **Memory layout on ARM development platforms** section in the +[Firmware Design]. + + +### Function : bl1_plat_prepare_exit() [optional] + + Argument : entry_point_info_t * + Return : void + +This function is called prior to exiting BL1 in response to the +`BL1_SMC_RUN_IMAGE` SMC request raised by BL2. It should be used to perform +platform specific clean up or bookkeeping operations before transferring +control to the next image. It receives the address of the `entry_point_info_t` +structure passed from BL2. This function runs with MMU disabled. + +### Function : bl1_plat_set_ep_info() [optional] + + Argument : unsigned int image_id, entry_point_info_t *ep_info + Return : void + +This function allows platforms to override `ep_info` for the given `image_id`. + +The default implementation just returns. + +### Function : bl1_plat_get_next_image_id() [optional] + + Argument : void + Return : unsigned int + +This and the following function must be overridden to enable the FWU feature. + +BL1 calls this function after platform setup to identify the next image to be +loaded and executed. If the platform returns `BL2_IMAGE_ID` then BL1 proceeds +with the normal boot sequence, which loads and executes BL2. If the platform +returns a different image id, BL1 assumes that Firmware Update is required. + +The default implementation always returns `BL2_IMAGE_ID`. The ARM development +platforms override this function to detect if firmware update is required, and +if so, return the first image in the firmware update process. + +### Function : bl1_plat_get_image_desc() [optional] + + Argument : unsigned int image_id + Return : image_desc_t * + +BL1 calls this function to get the image descriptor information `image_desc_t` +for the provided `image_id` from the platform. + +The default implementation always returns a common BL2 image descriptor. ARM +standard platforms return an image descriptor corresponding to BL2 or one of +the firmware update images defined in the Trusted Board Boot Requirements +specification. + +### Function : bl1_plat_fwu_done() [optional] + + Argument : unsigned int image_id, uintptr_t image_src, + unsigned int image_size + Return : void + +BL1 calls this function when the FWU process is complete. It must not return. +The platform may override this function to take platform specific action, for +example to initiate the normal boot flow. + +The default implementation spins forever. + +### Function : bl1_plat_mem_check() [mandatory] + + Argument : uintptr_t mem_base, unsigned int mem_size, + unsigned int flags + Return : void + +BL1 calls this function while handling FWU copy and authenticate SMCs. The +platform must ensure that the provided `mem_base` and `mem_size` are mapped into +BL1, and that this memory corresponds to either a secure or non-secure memory +region as indicated by the security state of the `flags` argument. + +The default implementation of this function asserts therefore platforms must +override it when using the FWU feature. + + +3.2 Boot Loader Stage 2 (BL2) +----------------------------- + +The BL2 stage is executed only by the primary CPU, which is determined in BL1 +using the `platform_is_primary_cpu()` function. BL1 passed control to BL2 at +`BL2_BASE`. BL2 executes in Secure EL1 and is responsible for: + +1. (Optional) Loading the SCP_BL2 binary image (if present) from platform + provided non-volatile storage. To load the SCP_BL2 image, BL2 makes use of + the `meminfo` returned by the `bl2_plat_get_scp_bl2_meminfo()` function. + The platform also defines the address in memory where SCP_BL2 is loaded + through the optional constant `SCP_BL2_BASE`. BL2 uses this information + to determine if there is enough memory to load the SCP_BL2 image. + Subsequent handling of the SCP_BL2 image is platform-specific and is + implemented in the `bl2_plat_handle_scp_bl2()` function. + If `SCP_BL2_BASE` is not defined then this step is not performed. + +2. Loading the BL31 binary image into secure RAM from non-volatile storage. To + load the BL31 image, BL2 makes use of the `meminfo` structure passed to it + by BL1. This structure allows BL2 to calculate how much secure RAM is + available for its use. The platform also defines the address in secure RAM + where BL31 is loaded through the constant `BL31_BASE`. BL2 uses this + information to determine if there is enough memory to load the BL31 image. + +3. (Optional) Loading the BL32 binary image (if present) from platform + provided non-volatile storage. To load the BL32 image, BL2 makes use of + the `meminfo` returned by the `bl2_plat_get_bl32_meminfo()` function. + The platform also defines the address in memory where BL32 is loaded + through the optional constant `BL32_BASE`. BL2 uses this information + to determine if there is enough memory to load the BL32 image. + If `BL32_BASE` is not defined then this and the next step is not performed. + +4. (Optional) Arranging to pass control to the BL32 image (if present) that + has been pre-loaded at `BL32_BASE`. BL2 populates an `entry_point_info` + structure in memory provided by the platform with information about how + BL31 should pass control to the BL32 image. + +5. (Optional) Loading the normal world BL33 binary image (if not loaded by + other means) into non-secure DRAM from platform storage and arranging for + BL31 to pass control to this image. This address is determined using the + `plat_get_ns_image_entrypoint()` function described below. + +6. BL2 populates an `entry_point_info` structure in memory provided by the + platform with information about how BL31 should pass control to the + other BL images. + +The following functions must be implemented by the platform port to enable BL2 +to perform the above tasks. + + +### Function : bl2_early_platform_setup() [mandatory] + + Argument : meminfo * + Return : void + +This function executes with the MMU and data caches disabled. It is only called +by the primary CPU. The arguments to this function is the address of the +`meminfo` structure populated by BL1. + +The platform may copy the contents of the `meminfo` structure into a private +variable as the original memory may be subsequently overwritten by BL2. The +copied structure is made available to all BL2 code through the +`bl2_plat_sec_mem_layout()` function. + +On ARM standard platforms, this function also: + +* Initializes a UART (PL011 console), which enables access to the `printf` + family of functions in BL2. + +* Initializes the storage abstraction layer used to load further bootloader + images. It is necessary to do this early on platforms with a SCP_BL2 image, + since the later `bl2_platform_setup` must be done after SCP_BL2 is loaded. + + +### Function : bl2_plat_arch_setup() [mandatory] + + Argument : void + Return : void + +This function executes with the MMU and data caches disabled. It is only called +by the primary CPU. + +The purpose of this function is to perform any architectural initialization +that varies across platforms. + +On ARM standard platforms, this function enables the MMU. + +### Function : bl2_platform_setup() [mandatory] + + Argument : void + Return : void + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initialization in `bl2_plat_arch_setup()`. It is only +called by the primary CPU. + +The purpose of this function is to perform any platform initialization +specific to BL2. + +In ARM standard platforms, this function performs security setup, including +configuration of the TrustZone controller to allow non-secure masters access +to most of DRAM. Part of DRAM is reserved for secure world use. + + +### Function : bl2_plat_sec_mem_layout() [mandatory] + + Argument : void + Return : meminfo * + +This function should only be called on the cold boot path. It may execute with +the MMU and data caches enabled if the platform port does the necessary +initialization in `bl2_plat_arch_setup()`. It is only called by the primary CPU. + +The purpose of this function is to return a pointer to a `meminfo` structure +populated with the extents of secure RAM available for BL2 to use. See +`bl2_early_platform_setup()` above. + + +Following function is required only when LOAD_IMAGE_V2 is enabled. + +### Function : bl2_plat_handle_post_image_load() [mandatory] + + Argument : unsigned int + Return : int + +This function can be used by the platforms to update/use image information +for given `image_id`. This function is currently invoked in BL2 to handle +BL image specific information based on the `image_id` passed, when +LOAD_IMAGE_V2 is enabled. + +Following functions are required only when LOAD_IMAGE_V2 is disabled. + +### Function : bl2_plat_get_scp_bl2_meminfo() [mandatory] + + Argument : meminfo * + Return : void + +This function is used to get the memory limits where BL2 can load the +SCP_BL2 image. The meminfo provided by this is used by load_image() to +validate whether the SCP_BL2 image can be loaded within the given +memory from the given base. + + +### Function : bl2_plat_handle_scp_bl2() [mandatory] + + Argument : image_info * + Return : int + +This function is called after loading SCP_BL2 image and it is used to perform +any platform-specific actions required to handle the SCP firmware. Typically it +transfers the image into SCP memory using a platform-specific protocol and waits +until SCP executes it and signals to the Application Processor (AP) for BL2 +execution to continue. + +This function returns 0 on success, a negative error code otherwise. + + +### Function : bl2_plat_get_bl31_params() [mandatory] + + Argument : void + Return : bl31_params * + +BL2 platform code needs to return a pointer to a `bl31_params` structure it +will use for passing information to BL31. The `bl31_params` structure carries +the following information. + - Header describing the version information for interpreting the bl31_param + structure + - Information about executing the BL33 image in the `bl33_ep_info` field + - Information about executing the BL32 image in the `bl32_ep_info` field + - Information about the type and extents of BL31 image in the + `bl31_image_info` field + - Information about the type and extents of BL32 image in the + `bl32_image_info` field + - Information about the type and extents of BL33 image in the + `bl33_image_info` field + +The memory pointed by this structure and its sub-structures should be +accessible from BL31 initialisation code. BL31 might choose to copy the +necessary content, or maintain the structures until BL33 is initialised. + + +### Funtion : bl2_plat_get_bl31_ep_info() [mandatory] + + Argument : void + Return : entry_point_info * + +BL2 platform code returns a pointer which is used to populate the entry point +information for BL31 entry point. The location pointed by it should be +accessible from BL1 while processing the synchronous exception to run to BL31. + +In ARM standard platforms this is allocated inside a bl2_to_bl31_params_mem +structure in BL2 memory. + + +### Function : bl2_plat_set_bl31_ep_info() [mandatory] + + Argument : image_info *, entry_point_info * + Return : void + +In the normal boot flow, this function is called after loading BL31 image and +it can be used to overwrite the entry point set by loader and also set the +security state and SPSR which represents the entry point system state for BL31. + +When booting an EL3 payload instead, this function is called after populating +its entry point address and can be used for the same purpose for the payload +image. It receives a null pointer as its first argument in this case. + +### Function : bl2_plat_set_bl32_ep_info() [mandatory] + + Argument : image_info *, entry_point_info * + Return : void + +This function is called after loading BL32 image and it can be used to +overwrite the entry point set by loader and also set the security state +and SPSR which represents the entry point system state for BL32. + + +### Function : bl2_plat_set_bl33_ep_info() [mandatory] + + Argument : image_info *, entry_point_info * + Return : void + +This function is called after loading BL33 image and it can be used to +overwrite the entry point set by loader and also set the security state +and SPSR which represents the entry point system state for BL33. + +In the preloaded BL33 alternative boot flow, this function is called after +populating its entry point address. It is passed a null pointer as its first +argument in this case. + + +### Function : bl2_plat_get_bl32_meminfo() [mandatory] + + Argument : meminfo * + Return : void + +This function is used to get the memory limits where BL2 can load the +BL32 image. The meminfo provided by this is used by load_image() to +validate whether the BL32 image can be loaded with in the given +memory from the given base. + +### Function : bl2_plat_get_bl33_meminfo() [mandatory] + + Argument : meminfo * + Return : void + +This function is used to get the memory limits where BL2 can load the +BL33 image. The meminfo provided by this is used by load_image() to +validate whether the BL33 image can be loaded with in the given +memory from the given base. + +This function isn't needed if either `PRELOADED_BL33_BASE` or `EL3_PAYLOAD_BASE` +build options are used. + +### Function : bl2_plat_flush_bl31_params() [mandatory] + + Argument : void + Return : void + +Once BL2 has populated all the structures that needs to be read by BL1 +and BL31 including the bl31_params structures and its sub-structures, +the bl31_ep_info structure and any platform specific data. It flushes +all these data to the main memory so that it is available when we jump to +later Bootloader stages with MMU off + +### Function : plat_get_ns_image_entrypoint() [mandatory] + + Argument : void + Return : uintptr_t + +As previously described, BL2 is responsible for arranging for control to be +passed to a normal world BL image through BL31. This function returns the +entrypoint of that image, which BL31 uses to jump to it. + +BL2 is responsible for loading the normal world BL33 image (e.g. UEFI). + +This function isn't needed if either `PRELOADED_BL33_BASE` or `EL3_PAYLOAD_BASE` +build options are used. + + +3.3 FWU Boot Loader Stage 2 (BL2U) +---------------------------------- + +The AP Firmware Updater Configuration, BL2U, is an optional part of the FWU +process and is executed only by the primary CPU. BL1 passes control to BL2U at +`BL2U_BASE`. BL2U executes in Secure-EL1 and is responsible for: + +1. (Optional) Transfering the optional SCP_BL2U binary image from AP secure + memory to SCP RAM. BL2U uses the SCP_BL2U `image_info` passed by BL1. + `SCP_BL2U_BASE` defines the address in AP secure memory where SCP_BL2U + should be copied from. Subsequent handling of the SCP_BL2U image is + implemented by the platform specific `bl2u_plat_handle_scp_bl2u()` function. + If `SCP_BL2U_BASE` is not defined then this step is not performed. + +2. Any platform specific setup required to perform the FWU process. For + example, ARM standard platforms initialize the TZC controller so that the + normal world can access DDR memory. + +The following functions must be implemented by the platform port to enable +BL2U to perform the tasks mentioned above. + +### Function : bl2u_early_platform_setup() [mandatory] + + Argument : meminfo *mem_info, void *plat_info + Return : void + +This function executes with the MMU and data caches disabled. It is only +called by the primary CPU. The arguments to this function is the address +of the `meminfo` structure and platform specific info provided by BL1. + +The platform may copy the contents of the `mem_info` and `plat_info` into +private storage as the original memory may be subsequently overwritten by BL2U. + +On ARM CSS platforms `plat_info` is interpreted as an `image_info_t` structure, +to extract SCP_BL2U image information, which is then copied into a private +variable. + +### Function : bl2u_plat_arch_setup() [mandatory] + + Argument : void + Return : void + +This function executes with the MMU and data caches disabled. It is only +called by the primary CPU. + +The purpose of this function is to perform any architectural initialization +that varies across platforms, for example enabling the MMU (since the memory +map differs across platforms). + +### Function : bl2u_platform_setup() [mandatory] + + Argument : void + Return : void + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initialization in `bl2u_plat_arch_setup()`. It is only +called by the primary CPU. + +The purpose of this function is to perform any platform initialization +specific to BL2U. + +In ARM standard platforms, this function performs security setup, including +configuration of the TrustZone controller to allow non-secure masters access +to most of DRAM. Part of DRAM is reserved for secure world use. + +### Function : bl2u_plat_handle_scp_bl2u() [optional] + + Argument : void + Return : int + +This function is used to perform any platform-specific actions required to +handle the SCP firmware. Typically it transfers the image into SCP memory using +a platform-specific protocol and waits until SCP executes it and signals to the +Application Processor (AP) for BL2U execution to continue. + +This function returns 0 on success, a negative error code otherwise. +This function is included if SCP_BL2U_BASE is defined. + + +3.4 Boot Loader Stage 3-1 (BL31) +--------------------------------- + +During cold boot, the BL31 stage is executed only by the primary CPU. This is +determined in BL1 using the `platform_is_primary_cpu()` function. BL1 passes +control to BL31 at `BL31_BASE`. During warm boot, BL31 is executed by all +CPUs. BL31 executes at EL3 and is responsible for: + +1. Re-initializing all architectural and platform state. Although BL1 performs + some of this initialization, BL31 remains resident in EL3 and must ensure + that EL3 architectural and platform state is completely initialized. It + should make no assumptions about the system state when it receives control. + +2. Passing control to a normal world BL image, pre-loaded at a platform- + specific address by BL2. BL31 uses the `entry_point_info` structure that BL2 + populated in memory to do this. + +3. Providing runtime firmware services. Currently, BL31 only implements a + subset of the Power State Coordination Interface (PSCI) API as a runtime + service. See Section 3.3 below for details of porting the PSCI + implementation. + +4. Optionally passing control to the BL32 image, pre-loaded at a platform- + specific address by BL2. BL31 exports a set of apis that allow runtime + services to specify the security state in which the next image should be + executed and run the corresponding image. BL31 uses the `entry_point_info` + structure populated by BL2 to do this. + +If BL31 is a reset vector, It also needs to handle the reset as specified in +section 2.2 before the tasks described above. + +The following functions must be implemented by the platform port to enable BL31 +to perform the above tasks. + + +### Function : bl31_early_platform_setup() [mandatory] + + Argument : bl31_params *, void * + Return : void + +This function executes with the MMU and data caches disabled. It is only called +by the primary CPU. The arguments to this function are: + +* The address of the `bl31_params` structure populated by BL2. +* An opaque pointer that the platform may use as needed. + +The platform can copy the contents of the `bl31_params` structure and its +sub-structures into private variables if the original memory may be +subsequently overwritten by BL31 and similarly the `void *` pointing +to the platform data also needs to be saved. + +In ARM standard platforms, BL2 passes a pointer to a `bl31_params` structure +in BL2 memory. BL31 copies the information in this pointer to internal data +structures. It also performs the following: + +* Initialize a UART (PL011 console), which enables access to the `printf` + family of functions in BL31. + +* Enable issuing of snoop and DVM (Distributed Virtual Memory) requests to the + CCI slave interface corresponding to the cluster that includes the primary + CPU. + + +### Function : bl31_plat_arch_setup() [mandatory] + + Argument : void + Return : void + +This function executes with the MMU and data caches disabled. It is only called +by the primary CPU. + +The purpose of this function is to perform any architectural initialization +that varies across platforms. + +On ARM standard platforms, this function enables the MMU. + + +### Function : bl31_platform_setup() [mandatory] + + Argument : void + Return : void + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initialization in `bl31_plat_arch_setup()`. It is only +called by the primary CPU. + +The purpose of this function is to complete platform initialization so that both +BL31 runtime services and normal world software can function correctly. + +On ARM standard platforms, this function does the following: + +* Initialize the generic interrupt controller. + + Depending on the GIC driver selected by the platform, the appropriate GICv2 + or GICv3 initialization will be done, which mainly consists of: + + - Enable secure interrupts in the GIC CPU interface. + - Disable the legacy interrupt bypass mechanism. + - Configure the priority mask register to allow interrupts of all priorities + to be signaled to the CPU interface. + - Mark SGIs 8-15 and the other secure interrupts on the platform as secure. + - Target all secure SPIs to CPU0. + - Enable these secure interrupts in the GIC distributor. + - Configure all other interrupts as non-secure. + - Enable signaling of secure interrupts in the GIC distributor. + +* Enable system-level implementation of the generic timer counter through the + memory mapped interface. + +* Grant access to the system counter timer module + +* Initialize the power controller device. + + In particular, initialise the locks that prevent concurrent accesses to the + power controller device. + + +### Function : bl31_plat_runtime_setup() [optional] + + Argument : void + Return : void + +The purpose of this function is allow the platform to perform any BL31 runtime +setup just prior to BL31 exit during cold boot. The default weak +implementation of this function will invoke `console_uninit()` which will +suppress any BL31 runtime logs. + +In ARM Standard platforms, this function will initialize the BL31 runtime +console which will cause all further BL31 logs to be output to the +runtime console. + + +### Function : bl31_get_next_image_info() [mandatory] + + Argument : unsigned int + Return : entry_point_info * + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initializations in `bl31_plat_arch_setup()`. + +This function is called by `bl31_main()` to retrieve information provided by +BL2 for the next image in the security state specified by the argument. BL31 +uses this information to pass control to that image in the specified security +state. This function must return a pointer to the `entry_point_info` structure +(that was copied during `bl31_early_platform_setup()`) if the image exists. It +should return NULL otherwise. + +### Function : plat_get_syscnt_freq2() [mandatory] + + Argument : void + Return : unsigned int + +This function is used by the architecture setup code to retrieve the counter +frequency for the CPU's generic timer. This value will be programmed into the +`CNTFRQ_EL0` register. In ARM standard platforms, it returns the base frequency +of the system counter, which is retrieved from the first entry in the frequency +modes table. + + +### #define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional] + + When `USE_COHERENT_MEM = 0`, this constant defines the total memory (in + bytes) aligned to the cache line boundary that should be allocated per-cpu to + accommodate all the bakery locks. + + If this constant is not defined when `USE_COHERENT_MEM = 0`, the linker + calculates the size of the `bakery_lock` input section, aligns it to the + nearest `CACHE_WRITEBACK_GRANULE`, multiplies it with `PLATFORM_CORE_COUNT` + and stores the result in a linker symbol. This constant prevents a platform + from relying on the linker and provide a more efficient mechanism for + accessing per-cpu bakery lock information. + + If this constant is defined and its value is not equal to the value + calculated by the linker then a link time assertion is raised. A compile time + assertion is raised if the value of the constant is not aligned to the cache + line boundary. + +3.5 Power State Coordination Interface (in BL31) +------------------------------------------------ + +The ARM Trusted Firmware's implementation of the PSCI API is based around the +concept of a _power domain_. A _power domain_ is a CPU or a logical group of +CPUs which share some state on which power management operations can be +performed as specified by [PSCI]. Each CPU in the system is assigned a cpu +index which is a unique number between `0` and `PLATFORM_CORE_COUNT - 1`. +The _power domains_ are arranged in a hierarchical tree structure and +each _power domain_ can be identified in a system by the cpu index of any CPU +that is part of that domain and a _power domain level_. A processing element +(for example, a CPU) is at level 0. If the _power domain_ node above a CPU is +a logical grouping of CPUs that share some state, then level 1 is that group +of CPUs (for example, a cluster), and level 2 is a group of clusters +(for example, the system). More details on the power domain topology and its +organization can be found in [Power Domain Topology Design]. + +BL31's platform initialization code exports a pointer to the platform-specific +power management operations required for the PSCI implementation to function +correctly. This information is populated in the `plat_psci_ops` structure. The +PSCI implementation calls members of the `plat_psci_ops` structure for performing +power management operations on the power domains. For example, the target +CPU is specified by its `MPIDR` in a PSCI `CPU_ON` call. The `pwr_domain_on()` +handler (if present) is called for the CPU power domain. + +The `power-state` parameter of a PSCI `CPU_SUSPEND` call can be used to +describe composite power states specific to a platform. The PSCI implementation +defines a generic representation of the power-state parameter viz which is an +array of local power states where each index corresponds to a power domain +level. Each entry contains the local power state the power domain at that power +level could enter. It depends on the `validate_power_state()` handler to +convert the power-state parameter (possibly encoding a composite power state) +passed in a PSCI `CPU_SUSPEND` call to this representation. + +The following functions must be implemented to initialize PSCI functionality in +the ARM Trusted Firmware. + + +### Function : plat_get_target_pwr_state() [optional] + + Argument : unsigned int, const plat_local_state_t *, unsigned int + Return : plat_local_state_t + +The PSCI generic code uses this function to let the platform participate in +state coordination during a power management operation. The function is passed +a pointer to an array of platform specific local power state `states` (second +argument) which contains the requested power state for each CPU at a particular +power domain level `lvl` (first argument) within the power domain. The function +is expected to traverse this array of upto `ncpus` (third argument) and return +a coordinated target power state by the comparing all the requested power +states. The target power state should not be deeper than any of the requested +power states. + +A weak definition of this API is provided by default wherein it assumes +that the platform assigns a local state value in order of increasing depth +of the power state i.e. for two power states X & Y, if X < Y +then X represents a shallower power state than Y. As a result, the +coordinated target local power state for a power domain will be the minimum +of the requested local power state values. + + +### Function : plat_get_power_domain_tree_desc() [mandatory] + + Argument : void + Return : const unsigned char * + +This function returns a pointer to the byte array containing the power domain +topology tree description. The format and method to construct this array are +described in [Power Domain Topology Design]. The BL31 PSCI initilization code +requires this array to be described by the platform, either statically or +dynamically, to initialize the power domain topology tree. In case the array +is populated dynamically, then plat_core_pos_by_mpidr() and +plat_my_core_pos() should also be implemented suitably so that the topology +tree description matches the CPU indices returned by these APIs. These APIs +together form the platform interface for the PSCI topology framework. + + +## Function : plat_setup_psci_ops() [mandatory] + + Argument : uintptr_t, const plat_psci_ops ** + Return : int + +This function may execute with the MMU and data caches enabled if the platform +port does the necessary initializations in `bl31_plat_arch_setup()`. It is only +called by the primary CPU. + +This function is called by PSCI initialization code. Its purpose is to let +the platform layer know about the warm boot entrypoint through the +`sec_entrypoint` (first argument) and to export handler routines for +platform-specific psci power management actions by populating the passed +pointer with a pointer to BL31's private `plat_psci_ops` structure. + +A description of each member of this structure is given below. Please refer to +the ARM FVP specific implementation of these handlers in +[plat/arm/board/fvp/fvp_pm.c] as an example. For each PSCI function that the +platform wants to support, the associated operation or operations in this +structure must be provided and implemented (Refer section 4 of +[Firmware Design] for the PSCI API supported in Trusted Firmware). To disable +a PSCI function in a platform port, the operation should be removed from this +structure instead of providing an empty implementation. + +#### plat_psci_ops.cpu_standby() + +Perform the platform-specific actions to enter the standby state for a cpu +indicated by the passed argument. This provides a fast path for CPU standby +wherein overheads of PSCI state management and lock acquistion is avoided. +For this handler to be invoked by the PSCI `CPU_SUSPEND` API implementation, +the suspend state type specified in the `power-state` parameter should be +STANDBY and the target power domain level specified should be the CPU. The +handler should put the CPU into a low power retention state (usually by +issuing a wfi instruction) and ensure that it can be woken up from that +state by a normal interrupt. The generic code expects the handler to succeed. + +#### plat_psci_ops.pwr_domain_on() + +Perform the platform specific actions to power on a CPU, specified +by the `MPIDR` (first argument). The generic code expects the platform to +return PSCI_E_SUCCESS on success or PSCI_E_INTERN_FAIL for any failure. + +#### plat_psci_ops.pwr_domain_off() + +Perform the platform specific actions to prepare to power off the calling CPU +and its higher parent power domain levels as indicated by the `target_state` +(first argument). It is called by the PSCI `CPU_OFF` API implementation. + +The `target_state` encodes the platform coordinated target local power states +for the CPU power domain and its parent power domain levels. The handler +needs to perform power management operation corresponding to the local state +at each power level. + +For this handler, the local power state for the CPU power domain will be a +power down state where as it could be either power down, retention or run state +for the higher power domain levels depending on the result of state +coordination. The generic code expects the handler to succeed. + +#### plat_psci_ops.pwr_domain_suspend() + +Perform the platform specific actions to prepare to suspend the calling +CPU and its higher parent power domain levels as indicated by the +`target_state` (first argument). It is called by the PSCI `CPU_SUSPEND` +API implementation. + +The `target_state` has a similar meaning as described in +the `pwr_domain_off()` operation. It encodes the platform coordinated +target local power states for the CPU power domain and its parent +power domain levels. The handler needs to perform power management operation +corresponding to the local state at each power level. The generic code +expects the handler to succeed. + +The difference between turning a power domain off versus suspending it +is that in the former case, the power domain is expected to re-initialize +its state when it is next powered on (see `pwr_domain_on_finish()`). In the +latter case, the power domain is expected to save enough state so that it can +resume execution by restoring this state when its powered on (see +`pwr_domain_suspend_finish()`). + +#### plat_psci_ops.pwr_domain_pwr_down_wfi() + +This is an optional function and, if implemented, is expected to perform +platform specific actions including the `wfi` invocation which allows the +CPU to powerdown. Since this function is invoked outside the PSCI locks, +the actions performed in this hook must be local to the CPU or the platform +must ensure that races between multiple CPUs cannot occur. + +The `target_state` has a similar meaning as described in the `pwr_domain_off()` +operation and it encodes the platform coordinated target local power states for +the CPU power domain and its parent power domain levels. This function must +not return back to the caller. + +If this function is not implemented by the platform, PSCI generic +implementation invokes `psci_power_down_wfi()` for power down. + +#### plat_psci_ops.pwr_domain_on_finish() + +This function is called by the PSCI implementation after the calling CPU is +powered on and released from reset in response to an earlier PSCI `CPU_ON` call. +It performs the platform-specific setup required to initialize enough state for +this CPU to enter the normal world and also provide secure runtime firmware +services. + +The `target_state` (first argument) is the prior state of the power domains +immediately before the CPU was turned on. It indicates which power domains +above the CPU might require initialization due to having previously been in +low power states. The generic code expects the handler to succeed. + +#### plat_psci_ops.pwr_domain_suspend_finish() + +This function is called by the PSCI implementation after the calling CPU is +powered on and released from reset in response to an asynchronous wakeup +event, for example a timer interrupt that was programmed by the CPU during the +`CPU_SUSPEND` call or `SYSTEM_SUSPEND` call. It performs the platform-specific +setup required to restore the saved state for this CPU to resume execution +in the normal world and also provide secure runtime firmware services. + +The `target_state` (first argument) has a similar meaning as described in +the `pwr_domain_on_finish()` operation. The generic code expects the platform +to succeed. + +#### plat_psci_ops.validate_power_state() + +This function is called by the PSCI implementation during the `CPU_SUSPEND` +call to validate the `power_state` parameter of the PSCI API and if valid, +populate it in `req_state` (second argument) array as power domain level +specific local states. If the `power_state` is invalid, the platform must +return PSCI_E_INVALID_PARAMS as error, which is propagated back to the +normal world PSCI client. + +#### plat_psci_ops.validate_ns_entrypoint() + +This function is called by the PSCI implementation during the `CPU_SUSPEND`, +`SYSTEM_SUSPEND` and `CPU_ON` calls to validate the non-secure `entry_point` +parameter passed by the normal world. If the `entry_point` is invalid, +the platform must return PSCI_E_INVALID_ADDRESS as error, which is +propagated back to the normal world PSCI client. + +#### plat_psci_ops.get_sys_suspend_power_state() + +This function is called by the PSCI implementation during the `SYSTEM_SUSPEND` +call to get the `req_state` parameter from platform which encodes the power +domain level specific local states to suspend to system affinity level. The +`req_state` will be utilized to do the PSCI state coordination and +`pwr_domain_suspend()` will be invoked with the coordinated target state to +enter system suspend. + +#### plat_psci_ops.get_pwr_lvl_state_idx() + +This is an optional function and, if implemented, is invoked by the PSCI +implementation to convert the `local_state` (first argument) at a specified +`pwr_lvl` (second argument) to an index between 0 and +`PLAT_MAX_PWR_LVL_STATES` - 1. This function is only needed if the platform +supports more than two local power states at each power domain level, that is +`PLAT_MAX_PWR_LVL_STATES` is greater than 2, and needs to account for these +local power states. + +#### plat_psci_ops.translate_power_state_by_mpidr() + +This is an optional function and, if implemented, verifies the `power_state` +(second argument) parameter of the PSCI API corresponding to a target power +domain. The target power domain is identified by using both `MPIDR` (first +argument) and the power domain level encoded in `power_state`. The power domain +level specific local states are to be extracted from `power_state` and be +populated in the `output_state` (third argument) array. The functionality +is similar to the `validate_power_state` function described above and is +envisaged to be used in case the validity of `power_state` depend on the +targeted power domain. If the `power_state` is invalid for the targeted power +domain, the platform must return PSCI_E_INVALID_PARAMS as error. If this +function is not implemented, then the generic implementation relies on +`validate_power_state` function to translate the `power_state`. + +This function can also be used in case the platform wants to support local +power state encoding for `power_state` parameter of PSCI_STAT_COUNT/RESIDENCY +APIs as described in Section 5.18 of [PSCI]. + +#### plat_psci_ops.get_node_hw_state() + +This is an optional function. If implemented this function is intended to return +the power state of a node (identified by the first parameter, the `MPIDR`) in +the power domain topology (identified by the second parameter, `power_level`), +as retrieved from a power controller or equivalent component on the platform. +Upon successful completion, the implementation must map and return the final +status among `HW_ON`, `HW_OFF` or `HW_STANDBY`. Upon encountering failures, it +must return either `PSCI_E_INVALID_PARAMS` or `PSCI_E_NOT_SUPPORTED` as +appropriate. + +Implementations are not expected to handle `power_levels` greater than +`PLAT_MAX_PWR_LVL`. + +3.6 Interrupt Management framework (in BL31) +---------------------------------------------- +BL31 implements an Interrupt Management Framework (IMF) to manage interrupts +generated in either security state and targeted to EL1 or EL2 in the non-secure +state or EL3/S-EL1 in the secure state. The design of this framework is +described in the [IMF Design Guide] + +A platform should export the following APIs to support the IMF. The following +text briefly describes each api and its implementation in ARM standard +platforms. The API implementation depends upon the type of interrupt controller +present in the platform. ARM standard platform layer supports both [ARM Generic +Interrupt Controller version 2.0 (GICv2)][ARM GIC Architecture Specification 2.0] +and [3.0 (GICv3)][ARM GIC Architecture Specification 3.0]. Juno builds the ARM +Standard layer to use GICv2 and the FVP can be configured to use either GICv2 or +GICv3 depending on the build flag `FVP_USE_GIC_DRIVER` (See FVP platform +specific build options in [User Guide] for more details). + +### Function : plat_interrupt_type_to_line() [mandatory] + + Argument : uint32_t, uint32_t + Return : uint32_t + +The ARM processor signals an interrupt exception either through the IRQ or FIQ +interrupt line. The specific line that is signaled depends on how the interrupt +controller (IC) reports different interrupt types from an execution context in +either security state. The IMF uses this API to determine which interrupt line +the platform IC uses to signal each type of interrupt supported by the framework +from a given security state. This API must be invoked at EL3. + +The first parameter will be one of the `INTR_TYPE_*` values (see [IMF Design +Guide]) indicating the target type of the interrupt, the second parameter is the +security state of the originating execution context. The return result is the +bit position in the `SCR_EL3` register of the respective interrupt trap: IRQ=1, +FIQ=2. + +In the case of ARM standard platforms using GICv2, S-EL1 interrupts are +configured as FIQs and Non-secure interrupts as IRQs from either security +state. + +In the case of ARM standard platforms using GICv3, the interrupt line to be +configured depends on the security state of the execution context when the +interrupt is signalled and are as follows: +* The S-EL1 interrupts are signaled as IRQ in S-EL0/1 context and as FIQ in + NS-EL0/1/2 context. +* The Non secure interrupts are signaled as FIQ in S-EL0/1 context and as IRQ + in the NS-EL0/1/2 context. +* The EL3 interrupts are signaled as FIQ in both S-EL0/1 and NS-EL0/1/2 + context. + + +### Function : plat_ic_get_pending_interrupt_type() [mandatory] + + Argument : void + Return : uint32_t + +This API returns the type of the highest priority pending interrupt at the +platform IC. The IMF uses the interrupt type to retrieve the corresponding +handler function. `INTR_TYPE_INVAL` is returned when there is no interrupt +pending. The valid interrupt types that can be returned are `INTR_TYPE_EL3`, +`INTR_TYPE_S_EL1` and `INTR_TYPE_NS`. This API must be invoked at EL3. + +In the case of ARM standard platforms using GICv2, the _Highest Priority +Pending Interrupt Register_ (`GICC_HPPIR`) is read to determine the id of +the pending interrupt. The type of interrupt depends upon the id value as +follows. + +1. id < 1022 is reported as a S-EL1 interrupt +2. id = 1022 is reported as a Non-secure interrupt. +3. id = 1023 is reported as an invalid interrupt type. + +In the case of ARM standard platforms using GICv3, the system register +`ICC_HPPIR0_EL1`, _Highest Priority Pending group 0 Interrupt Register_, +is read to determine the id of the pending interrupt. The type of interrupt +depends upon the id value as follows. + +1. id = `PENDING_G1S_INTID` (1020) is reported as a S-EL1 interrupt +2. id = `PENDING_G1NS_INTID` (1021) is reported as a Non-secure interrupt. +3. id = `GIC_SPURIOUS_INTERRUPT` (1023) is reported as an invalid interrupt type. +4. All other interrupt id's are reported as EL3 interrupt. + + +### Function : plat_ic_get_pending_interrupt_id() [mandatory] + + Argument : void + Return : uint32_t + +This API returns the id of the highest priority pending interrupt at the +platform IC. `INTR_ID_UNAVAILABLE` is returned when there is no interrupt +pending. + +In the case of ARM standard platforms using GICv2, the _Highest Priority +Pending Interrupt Register_ (`GICC_HPPIR`) is read to determine the id of the +pending interrupt. The id that is returned by API depends upon the value of +the id read from the interrupt controller as follows. + +1. id < 1022. id is returned as is. +2. id = 1022. The _Aliased Highest Priority Pending Interrupt Register_ + (`GICC_AHPPIR`) is read to determine the id of the non-secure interrupt. + This id is returned by the API. +3. id = 1023. `INTR_ID_UNAVAILABLE` is returned. + +In the case of ARM standard platforms using GICv3, if the API is invoked from +EL3, the system register `ICC_HPPIR0_EL1`, _Highest Priority Pending Interrupt +group 0 Register_, is read to determine the id of the pending interrupt. The id +that is returned by API depends upon the value of the id read from the +interrupt controller as follows. + +1. id < `PENDING_G1S_INTID` (1020). id is returned as is. +2. id = `PENDING_G1S_INTID` (1020) or `PENDING_G1NS_INTID` (1021). The system + register `ICC_HPPIR1_EL1`, _Highest Priority Pending Interrupt group 1 + Register_ is read to determine the id of the group 1 interrupt. This id + is returned by the API as long as it is a valid interrupt id +3. If the id is any of the special interrupt identifiers, + `INTR_ID_UNAVAILABLE` is returned. + +When the API invoked from S-EL1 for GICv3 systems, the id read from system +register `ICC_HPPIR1_EL1`, _Highest Priority Pending group 1 Interrupt +Register_, is returned if is not equal to GIC_SPURIOUS_INTERRUPT (1023) else +`INTR_ID_UNAVAILABLE` is returned. + +### Function : plat_ic_acknowledge_interrupt() [mandatory] + + Argument : void + Return : uint32_t + +This API is used by the CPU to indicate to the platform IC that processing of +the highest pending interrupt has begun. It should return the id of the +interrupt which is being processed. + +This function in ARM standard platforms using GICv2, reads the _Interrupt +Acknowledge Register_ (`GICC_IAR`). This changes the state of the highest +priority pending interrupt from pending to active in the interrupt controller. +It returns the value read from the `GICC_IAR`. This value is the id of the +interrupt whose state has been changed. + +In the case of ARM standard platforms using GICv3, if the API is invoked +from EL3, the function reads the system register `ICC_IAR0_EL1`, _Interrupt +Acknowledge Register group 0_. If the API is invoked from S-EL1, the function +reads the system register `ICC_IAR1_EL1`, _Interrupt Acknowledge Register +group 1_. The read changes the state of the highest pending interrupt from +pending to active in the interrupt controller. The value read is returned +and is the id of the interrupt whose state has been changed. + +The TSP uses this API to start processing of the secure physical timer +interrupt. + + +### Function : plat_ic_end_of_interrupt() [mandatory] + + Argument : uint32_t + Return : void + +This API is used by the CPU to indicate to the platform IC that processing of +the interrupt corresponding to the id (passed as the parameter) has +finished. The id should be the same as the id returned by the +`plat_ic_acknowledge_interrupt()` API. + +ARM standard platforms write the id to the _End of Interrupt Register_ +(`GICC_EOIR`) in case of GICv2, and to `ICC_EOIR0_EL1` or `ICC_EOIR1_EL1` +system register in case of GICv3 depending on where the API is invoked from, +EL3 or S-EL1. This deactivates the corresponding interrupt in the interrupt +controller. + +The TSP uses this API to finish processing of the secure physical timer +interrupt. + + +### Function : plat_ic_get_interrupt_type() [mandatory] + + Argument : uint32_t + Return : uint32_t + +This API returns the type of the interrupt id passed as the parameter. +`INTR_TYPE_INVAL` is returned if the id is invalid. If the id is valid, a valid +interrupt type (one of `INTR_TYPE_EL3`, `INTR_TYPE_S_EL1` and `INTR_TYPE_NS`) is +returned depending upon how the interrupt has been configured by the platform +IC. This API must be invoked at EL3. + +ARM standard platforms using GICv2 configures S-EL1 interrupts as Group0 interrupts +and Non-secure interrupts as Group1 interrupts. It reads the group value +corresponding to the interrupt id from the relevant _Interrupt Group Register_ +(`GICD_IGROUPRn`). It uses the group value to determine the type of interrupt. + +In the case of ARM standard platforms using GICv3, both the _Interrupt Group +Register_ (`GICD_IGROUPRn`) and _Interrupt Group Modifier Register_ +(`GICD_IGRPMODRn`) is read to figure out whether the interrupt is configured +as Group 0 secure interrupt, Group 1 secure interrupt or Group 1 NS interrupt. + + +3.7 Crash Reporting mechanism (in BL31) +---------------------------------------------- +BL31 implements a crash reporting mechanism which prints the various registers +of the CPU to enable quick crash analysis and debugging. It requires that a +console is designated as the crash console by the platform which will be used to +print the register dump. + +The following functions must be implemented by the platform if it wants crash +reporting mechanism in BL31. The functions are implemented in assembly so that +they can be invoked without a C Runtime stack. + +### Function : plat_crash_console_init + + Argument : void + Return : int + +This API is used by the crash reporting mechanism to initialize the crash +console. It must only use the general purpose registers x0 to x4 to do the +initialization and returns 1 on success. + +### Function : plat_crash_console_putc + + Argument : int + Return : int + +This API is used by the crash reporting mechanism to print a character on the +designated crash console. It must only use general purpose registers x1 and +x2 to do its work. The parameter and the return value are in general purpose +register x0. + +4. Build flags +--------------- + +* **ENABLE_PLAT_COMPAT** + All the platforms ports conforming to this API specification should define + the build flag `ENABLE_PLAT_COMPAT` to 0 as the compatibility layer should + be disabled. For more details on compatibility layer, refer + [Migration Guide]. + +There are some build flags which can be defined by the platform to control +inclusion or exclusion of certain BL stages from the FIP image. These flags +need to be defined in the platform makefile which will get included by the +build system. + +* **NEED_BL33** + By default, this flag is defined `yes` by the build system and `BL33` + build option should be supplied as a build option. The platform has the + option of excluding the BL33 image in the `fip` image by defining this flag + to `no`. If any of the options `EL3_PAYLOAD_BASE` or `PRELOADED_BL33_BASE` + are used, this flag will be set to `no` automatically. + +5. C Library +------------- + +To avoid subtle toolchain behavioral dependencies, the header files provided +by the compiler are not used. The software is built with the `-nostdinc` flag +to ensure no headers are included from the toolchain inadvertently. Instead the +required headers are included in the ARM Trusted Firmware source tree. The +library only contains those C library definitions required by the local +implementation. If more functionality is required, the needed library functions +will need to be added to the local implementation. + +Versions of [FreeBSD] headers can be found in `include/lib/stdlib`. Some of +these headers have been cut down in order to simplify the implementation. In +order to minimize changes to the header files, the [FreeBSD] layout has been +maintained. The generic C library definitions can be found in +`include/lib/stdlib` with more system and machine specific declarations in +`include/lib/stdlib/sys` and `include/lib/stdlib/machine`. + +The local C library implementations can be found in `lib/stdlib`. In order to +extend the C library these files may need to be modified. It is recommended to +use a release version of [FreeBSD] as a starting point. + +The C library header files in the [FreeBSD] source tree are located in the +`include` and `sys/sys` directories. [FreeBSD] machine specific definitions +can be found in the `sys/` directories. These files define things +like 'the size of a pointer' and 'the range of an integer'. Since an AArch64 +port for [FreeBSD] does not yet exist, the machine specific definitions are +based on existing machine types with similar properties (for example SPARC64). + +Where possible, C library function implementations were taken from [FreeBSD] +as found in the `lib/libc` directory. + +A copy of the [FreeBSD] sources can be downloaded with `git`. + + git clone git://github.com/freebsd/freebsd.git -b origin/release/9.2.0 + + +6. Storage abstraction layer +----------------------------- + +In order to improve platform independence and portability an storage abstraction +layer is used to load data from non-volatile platform storage. + +Each platform should register devices and their drivers via the Storage layer. +These drivers then need to be initialized by bootloader phases as +required in their respective `blx_platform_setup()` functions. Currently +storage access is only required by BL1 and BL2 phases. The `load_image()` +function uses the storage layer to access non-volatile platform storage. + +It is mandatory to implement at least one storage driver. For the ARM +development platforms the Firmware Image Package (FIP) driver is provided as +the default means to load data from storage (see the "Firmware Image Package" +section in the [User Guide]). The storage layer is described in the header file +`include/drivers/io/io_storage.h`. The implementation of the common library +is in `drivers/io/io_storage.c` and the driver files are located in +`drivers/io/`. + +Each IO driver must provide `io_dev_*` structures, as described in +`drivers/io/io_driver.h`. These are returned via a mandatory registration +function that is called on platform initialization. The semi-hosting driver +implementation in `io_semihosting.c` can be used as an example. + +The Storage layer provides mechanisms to initialize storage devices before +IO operations are called. The basic operations supported by the layer +include `open()`, `close()`, `read()`, `write()`, `size()` and `seek()`. +Drivers do not have to implement all operations, but each platform must +provide at least one driver for a device capable of supporting generic +operations such as loading a bootloader image. + +The current implementation only allows for known images to be loaded by the +firmware. These images are specified by using their identifiers, as defined in +[include/plat/common/platform_def.h] (or a separate header file included from +there). The platform layer (`plat_get_image_source()`) then returns a reference +to a device and a driver-specific `spec` which will be understood by the driver +to allow access to the image data. + +The layer is designed in such a way that is it possible to chain drivers with +other drivers. For example, file-system drivers may be implemented on top of +physical block devices, both represented by IO devices with corresponding +drivers. In such a case, the file-system "binding" with the block device may +be deferred until the file-system device is initialised. + +The abstraction currently depends on structures being statically allocated +by the drivers and callers, as the system does not yet provide a means of +dynamically allocating memory. This may also have the affect of limiting the +amount of open resources per driver. + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._ + + +[ARM GIC Architecture Specification 2.0]: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0048b/index.html +[ARM GIC Architecture Specification 3.0]: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069b/index.html +[IMF Design Guide]: interrupt-framework-design.md +[User Guide]: user-guide.md +[FreeBSD]: http://www.freebsd.org +[Firmware Design]: firmware-design.md +[Power Domain Topology Design]: psci-pd-tree.md +[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf +[Migration Guide]: platform-migration-guide.md +[Firmware Update]: firmware-update.md + +[plat/common/aarch64/platform_mp_stack.S]: ../plat/common/aarch64/platform_mp_stack.S +[plat/common/aarch64/platform_up_stack.S]: ../plat/common/aarch64/platform_up_stack.S +[plat/arm/board/fvp/fvp_pm.c]: ../plat/arm/board/fvp/fvp_pm.c +[include/common/bl_common.h]: ../include/common/bl_common.h +[include/lib/aarch32/arch.h]: ../include/lib/aarch32/arch.h +[include/plat/arm/common/arm_def.h]: ../include/plat/arm/common/arm_def.h +[include/plat/common/common_def.h]: ../include/plat/common/common_def.h +[include/plat/common/platform.h]: ../include/plat/common/platform.h +[include/plat/arm/common/plat_arm.h]: ../include/plat/arm/common/plat_arm.h] diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/psci-lib-integration-guide.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/psci-lib-integration-guide.md new file mode 100644 index 0000000..f290966 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/psci-lib-integration-guide.md @@ -0,0 +1,535 @@ +PSCI Library Integration guide for ARMv8-A AArch32 systems +========================================================== + +Contents +-------- + +1. [Introduction](#1-introduction) +2. [Generic call sequence for PSCI Library interface (AArch32)](#2-generic-call-sequence-for-psci-library-interface-aarch32) +3. [PSCI CPU context management](#3-psci-cpu-context-management) +4. [PSCI Library Interface](#4-psci-library-interface) +5. [EL3 Runtime Software dependencies](#5-el3-runtime-software-dependencies) + + +1. Introduction +--------------- + +This document describes the PSCI library interface with a focus on how to +integrate with a suitable Trusted OS for an ARMv8-A AArch32 system. The PSCI +Library implements the PSCI Standard as described in [PSCI spec] and is meant +to be integrated with EL3 Runtime Software which invokes the PSCI Library +interface appropriately. **EL3 Runtime Software** refers to software executing +at the highest secure privileged mode, which is EL3 in AArch64 or Secure SVC/ +Monitor mode in AArch32, and provides runtime services to the non-secure world. +The runtime service request is made via SMC (Secure Monitor Call) and the call +must adhere to [SMCCC]. In AArch32, EL3 Runtime Software may additionally +include Trusted OS functionality. A minimal AArch32 Secure Payload, SP-MIN, is +provided in ARM Trusted Firmware to illustrate the usage and integration of the +PSCI library. The description of PSCI library interface and its integration +with EL3 Runtime Software in this document is targeted towards AArch32 systems. + +2. Generic call sequence for PSCI Library interface (AArch32) +------------------------------------------------------------- + +The generic call sequence of PSCI Library interfaces +[(see section 4)](#4-psci-library-interface) during cold boot in AArch32 +system is described below: + +1. After cold reset, the EL3 Runtime Software performs its cold boot + initialization including the PSCI library pre-requisites mentioned in + [section 4](#4-psci-library-interface), and also the necessary platform + setup. + +2. Call `psci_setup()` in Monitor mode. + +3. Optionally call `psci_register_spd_pm_hook()` to register callbacks to + do bookkeeping for the EL3 Runtime Software during power management. + +4. Call `psci_prepare_next_non_secure_ctx()` to initialize the non-secure CPU + context. + +5. Get the non-secure `cpu_context_t` for the current CPU by calling + `cm_get_context()` , then programming the registers in the non-secure + context and exiting to non-secure world. If the EL3 Runtime Software needs + additional configuration to be set for non-secure context, like routing + FIQs to the secure world, the values of the registers can be modified prior + to programming. See [section 3](#3-psci-cpu-context-management) for more + details on CPU context management. + +The generic call sequence of PSCI library interfaces during warm boot in +AArch32 systems is described below: + +1. After warm reset, the EL3 Runtime Software performs the necessary warm + boot initialization including the PSCI library pre-requisites mentioned in + [section 4](#4-psci-library-interface) (Note that the Data cache + **must not** be enabled). + +2. Call `psci_warmboot_entrypoint()` in Monitor mode. This interface + initializes/restores the non-secure CPU context as well. + +3. Do step 5 of the cold boot call sequence described above. + +The generic call sequence of PSCI library interfaces on receipt of a PSCI SMC +on an AArch32 system is described below: + +1. On receipt of an SMC, save the register context as per [SMCCC]. + +2. If the SMC function identifier corresponds to a SMC32 PSCI API, construct + the appropriate arguments and call the `psci_smc_handler()` interface. + The invocation may or may not return back to the caller depending on + whether the PSCI API resulted in power down of the CPU. + +3. If `psci_smc_handler()` returns, populate the return value in R0 (AArch32)/ + X0 (AArch64) and restore other registers as per [SMCCC]. + + +3. PSCI CPU context management +------------------------------ + +PSCI library is in charge of initializing/restoring the non-secure CPU system +registers according to [PSCI specification][PSCI spec] during cold/warm boot. +This is referred to as `PSCI CPU Context Management`. Registers that need to +be preserved across CPU power down/power up cycles are maintained in +`cpu_context_t` data structure. The initialization of other non-secure CPU +system registers which do not require coordination with the EL3 Runtime +Software is done directly by the PSCI library (see `cm_prepare_el3_exit()`). + +The EL3 Runtime Software is responsible for managing register context +during switch between Normal and Secure worlds. The register context to be +saved and restored depends on the mechanism used to trigger the world switch. +For example, if the world switch was triggered by an SMC call, then the +registers need to be saved and restored according to [SMCCC]. In AArch64, +due to the tight integration with BL31, both BL31 and PSCI library +use the same `cpu_context_t` data structure for PSCI CPU context management +and register context management during world switch. This cannot be assumed +for AArch32 EL3 Runtime Software since most AArch32 Trusted OSes already implement +a mechanism for register context management during world switch. Hence, when +the PSCI library is integrated with a AArch32 EL3 Runtime Software, the +`cpu_context_t` is stripped down for just PSCI CPU context management. + +During cold/warm boot, after invoking appropriate PSCI library interfaces, it +is expected that the EL3 Runtime Software will query the `cpu_context_t` and +write appropriate values to the corresponding system registers. This mechanism +resolves 2 additional problems for AArch32 EL3 Runtime Software: + +1. Values for certain system registers like SCR and SCTLR cannot be + unilaterally determined by PSCI library and need inputs from the EL3 + Runtime Software. Using `cpu_context_t` as an intermediary data store + allows EL3 Runtime Software to modify the register values appropriately + before programming them. + +2. The PSCI library provides appropriate LR and SPSR values (entrypoint + information) for exit into non-secure world. Using `cpu_context_t` as an + intermediary data store allows the EL3 Runtime Software to store these + values safely until it is ready for exit to non-secure world. + +Currently the `cpu_context_t` data structure for AArch32 stores the following +registers: R0 - R3, LR (R14), SCR, SPSR, SCTLR. + +The EL3 Runtime Software must implement accessors to get/set pointers +to CPU context `cpu_context_t` data and these are described in +[section 5.2](#52-cpu-context-management-api). + + +4. PSCI Library Interface +------------------------- + +The PSCI library implements the [PSCI Specification][PSCI spec]. The interfaces +to this library are declared in `psci.h` and are as listed below: + +``` + u_register_t psci_smc_handler(uint32_t smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3, + u_register_t x4, void *cookie, + void *handle, u_register_t flags); + int psci_setup(const psci_lib_args_t *lib_args); + void psci_warmboot_entrypoint(void); + void psci_register_spd_pm_hook(const spd_pm_ops_t *pm); + void psci_prepare_next_non_secure_ctx(entry_point_info_t *next_image_info); +``` + +The CPU context data 'cpu_context_t' is programmed to the registers differently +when PSCI is integrated with an AArch32 EL3 Runtime Software compared to +when the PSCI is integrated with an AArch64 EL3 Runtime Software (BL31). For +example, in the case of AArch64, there is no need to retrieve `cpu_context_t` +data and program the registers as it will done implicitly as part of +`el3_exit`. The description below of the PSCI interfaces is targeted at +integration with an AArch32 EL3 Runtime Software. + +The PSCI library is responsible for initializing/restoring the non-secure world +to an appropriate state after boot and may choose to directly program the +non-secure system registers. The PSCI generic code takes care not to directly +modify any of the system registers affecting the secure world and instead +returns the values to be programmed to these registers via `cpu_context_t`. +The EL3 Runtime Software is responsible for programming those registers and +can use the proposed values provided in the `cpu_context_t`, modifying the +values if required. + +PSCI library needs the flexibility to access both secure and non-secure +copies of banked registers. Hence it needs to be invoked in Monitor mode +for AArch32 and in EL3 for AArch64. The NS bit in SCR (in AArch32) or SCR_EL3 +(in AArch64) must be set to 0. Additional requirements for the PSCI library +interfaces are: + + * Instruction cache must be enabled + * Both IRQ and FIQ must be masked for the current CPU + * The page tables must be setup and the MMU enabled + * The C runtime environment must be setup and stack initialized + * The Data cache must be enabled prior to invoking any of the PSCI library + interfaces except for `psci_warmboot_entrypoint()`. + +Further requirements for each interface can be found in the interface +description. + +### 4.1 Interface : psci_setup() + + Argument : const psci_lib_args_t *lib_args + Return : void + +This function is to be called by the primary CPU during cold boot before +any other interface to the PSCI library. It takes `lib_args`, a const pointer +to `psci_lib_args_t`, as the argument. The `psci_lib_args_t` is a versioned +structure and is declared in `psci.h` header as follows: + +``` + typedef struct psci_lib_args { + /* The version information of PSCI Library Interface */ + param_header_t h; + /* The warm boot entrypoint function */ + mailbox_entrypoint_t mailbox_ep; + } psci_lib_args_t; +``` + +The first field `h`, of `param_header_t` type, provides the version +information. The second field `mailbox_ep` is the warm boot entrypoint address +and is used to configure the platform mailbox. Helper macros are provided in +psci.h to construct the `lib_args` argument statically or during runtime. Prior +to calling the `psci_setup()` interface, the platform setup for cold boot +must have completed. Major actions performed by this interface are: + + * Initializes architecture. + * Initializes PSCI power domain and state coordination data structures. + * Calls `plat_setup_psci_ops()` with warm boot entrypoint `mailbox_ep` as + argument. + * Calls `cm_set_context_by_index()` (see + [section 5.2](#52-cpu-context-management-api)) for all the CPUs in the + platform + +### 4.2 Interface : psci_prepare_next_non_secure_ctx() + + Argument : entry_point_info_t *next_image_info + Return : void + +After `psci_setup()` and prior to exit to the non-secure world, this function +must be called by the EL3 Runtime Software to initialize the non-secure world +context. The non-secure world entrypoint information `next_image_info` (first +argument) will be used to determine the non-secure context. After this function +returns, the EL3 Runtime Software must retrieve the `cpu_context_t` (using +cm_get_context()) for the current CPU and program the registers prior to exit +to the non-secure world. + +### 4.3 Interface : psci_register_spd_pm_hook() + + Argument : const spd_pm_ops_t * + Return : void + +As explained in [section 5.4](#54-secure-payload-power-management-callback), +the EL3 Runtime Software may want to perform some bookkeeping during power +management operations. This function is used to register the `spd_pm_ops_t` +(first argument) callbacks with the PSCI library which will be called +ppropriately during power management. Calling this function is optional and +need to be called by the primary CPU during the cold boot sequence after +`psci_setup()` has completed. + +### 4.4 Interface : psci_smc_handler() + + Argument : uint32_t smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3, + u_register_t x4, void *cookie, + void *handle, u_register_t flags + Return : u_register_t + +This function is the top level handler for SMCs which fall within the +PSCI service range specified in [SMCCC]. The function ID `smc_fid` (first +argument) determines the PSCI API to be called. The `x1` to `x4` (2nd to 5th +arguments), are the values of the registers r1 - r4 (in AArch32) or x1 - x4 +(in AArch64) when the SMC is received. These are the arguments to PSCI API as +described in [PSCI spec]. The 'flags' (8th argument) is a bit field parameter +and is detailed in 'smcc.h' header. It includes whether the call is from the +secure or non-secure world. The `cookie` (6th argument) and the `handle` +(7th argument) are not used and are reserved for future use. + +The return value from this interface is the return value from the underlying +PSCI API corresponding to `smc_fid`. This function may not return back to the +caller if PSCI API causes power down of the CPU. In this case, when the CPU +wakes up, it will start execution from the warm reset address. + +### 4.5 Interface : psci_warmboot_entrypoint() + + Argument : void + Return : void + +This function performs the warm boot initialization/restoration as mandated by +[PSCI spec]. For AArch32, on wakeup from power down the CPU resets to secure +SVC mode and the EL3 Runtime Software must perform the prerequisite +initializations mentioned at top of this section. This function must be called +with Data cache disabled but with MMU initialized and enabled. The major +actions performed by this function are: + + * Invalidates the stack and enables the data cache. + * Initializes architecture and PSCI state coordination. + * Restores/Initializes the peripheral drivers to the required state via + appropriate `plat_psci_ops_t` hooks + * Restores the EL3 Runtime Software context via appropriate `spd_pm_ops_t` + callbacks. + * Restores/Initializes the non-secure context and populates the + `cpu_context_t` for the current CPU. + +Upon the return of this function, the EL3 Runtime Software must retrieve the +non-secure `cpu_context_t` using `cm_get_context()` and program the registers +prior to exit to the non-secure world. + + +5. EL3 Runtime Software dependencies +--------------------------------------- + +The PSCI Library includes supporting frameworks like context management, +cpu operations (cpu_ops) and per-cpu data framework. Other helper library +functions like bakery locks and spin locks are also included in the library. +The dependencies which must be fulfilled by the EL3 Runtime Software +for integration with PSCI library are described below. + +### 5.1 General dependencies + +The PSCI library being a Multiprocessor (MP) implementation, EL3 Runtime +Software must provide an SMC handling framework capable of MP adhering to +[SMCCC] specification. + +The EL3 Runtime Software must also export cache maintenance primitives +and some helper utilities for assert, print and memory operations as listed +below. The ARM Trusted Firmware source tree provides implementations for all +these functions but the EL3 Runtime Software may use its own implementation. + +**Functions : assert(), memcpy(), memset** + +These must be implemented as described in ISO C Standard. + +**Function : flush_dcache_range()** + + Argument : uintptr_t addr, size_t size + Return : void + +This function cleans and invalidates (flushes) the data cache for memory +at address `addr` (first argument) address and of size `size` (second argument). + +**Function : inv_dcache_range()** + + Argument : uintptr_t addr, size_t size + Return : void + +This function invalidates (flushes) the data cache for memory at address +`addr` (first argument) address and of size `size` (second argument). + +**Function : do_panic()** + + Argument : void + Return : void + +This function will be called by the PSCI library on encountering a critical +failure that cannot be recovered from. This function **must not** return. + +**Function : tf_printf()** + +This is printf-compatible function, but unlike printf, it does not return any +value. The ARM Trusted Firmware source tree provides an implementation which +is optimized for stack usage and supports only a subset of format specifiers. +The details of the format specifiers supported can be found in the +`tf_printf.c` file in ARM Trusted Firmware source tree. + +### 5.2 CPU Context management API + +The CPU context management data memory is statically allocated by PSCI library +in BSS section. The PSCI library requires the EL3 Runtime Software to implement +APIs to store and retrieve pointers to this CPU context data. SP-MIN +demonstrates how these APIs can be implemented but the EL3 Runtime Software can +choose a more optimal implementation (like dedicating the secure TPIDRPRW +system register (in AArch32) for storing these pointers). + +**Function : cm_set_context_by_index()** + + Argument : unsigned int cpu_idx, void *context, unsigned int security_state + Return : void + +This function is called during cold boot when the `psci_setup()` PSCI library +interface is called. + +This function must store the pointer to the CPU context data, `context` (2nd +argument), for the specified `security_state` (3rd argument) and CPU identified +by `cpu_idx` (first argument). The `security_state` will always be non-secure +when called by PSCI library and this argument is retained for compatibility +with BL31. The `cpu_idx` will correspond to the index returned by the +`plat_core_pos_by_mpidr()` for `mpidr` of the CPU. + +The actual method of storing the `context` pointers is implementation specific. +For example, SP-MIN stores the pointers in the array `sp_min_cpu_ctx_ptr` +declared in `sp_min_main.c`. + +**Function : cm_get_context()** + + Argument : uint32_t security_state + Return : void * + +This function must return the pointer to the `cpu_context_t` structure for +the specified `security_state` (first argument) for the current CPU. The caller +must ensure that `cm_set_context_by_index` is called first and the appropriate +context pointers are stored prior to invoking this API. The `security_state` +will always be non-secure when called by PSCI library and this argument +is retained for compatibility with BL31. + +**Function : cm_get_context_by_index()** + + Argument : unsigned int cpu_idx, unsigned int security_state + Return : void * + +This function must return the pointer to the `cpu_context_t` structure for +the specified `security_state` (second argument) for the CPU identified by +`cpu_idx` (first argument). The caller must ensure that +`cm_set_context_by_index` is called first and the appropriate context +pointers are stored prior to invoking this API. The `security_state` will +always be non-secure when called by PSCI library and this argument is +retained for compatibility with BL31. The `cpu_idx` will correspond to the +index returned by the `plat_core_pos_by_mpidr()` for `mpidr` of the CPU. + +### 5.3 Platform API + +The platform layer abstracts the platform-specific details from the generic +PSCI library. The following platform APIs/macros must be defined by the EL3 +Runtime Software for integration with the PSCI library. + +The mandatory platform APIs are: + + * plat_my_core_pos + * plat_core_pos_by_mpidr + * plat_get_syscnt_freq2 + * plat_get_power_domain_tree_desc + * plat_setup_psci_ops + * plat_reset_handler + * plat_panic_handler + * plat_get_my_stack + +The mandatory platform macros are: + + * PLATFORM_CORE_COUNT + * PLAT_MAX_PWR_LVL + * PLAT_NUM_PWR_DOMAINS + * CACHE_WRITEBACK_GRANULE + * PLAT_MAX_OFF_STATE + * PLAT_MAX_RET_STATE + * PLAT_MAX_PWR_LVL_STATES (optional) + * PLAT_PCPU_DATA_SIZE (optional) + +The details of these APIs/macros can be found in [Porting Guide]. + +All platform specific operations for power management are done via +`plat_psci_ops_t` callbacks registered by the platform when +`plat_setup_psci_ops()` API is called. The description of each of +the callbacks in `plat_psci_ops_t` can be found in PSCI section of the +[Porting Guide]. If any these callbacks are not registered, then the +PSCI API associated with that callback will not be supported by PSCI +library. + +### 5.4 Secure payload power management callback + +During PSCI power management operations, the EL3 Runtime Software may +need to perform some bookkeeping, and PSCI library provides +`spd_pm_ops_t` callbacks for this purpose. These hooks must be +populated and registered by using `psci_register_spd_pm_hook()` PSCI +library interface. + +Typical bookkeeping during PSCI power management calls include save/restore +of the EL3 Runtime Software context. Also if the EL3 Runtime Software makes +use of secure interrupts, then these interrupts must also be managed +appropriately during CPU power down/power up. Any secure interrupt targeted +to the current CPU must be disabled or re-targeted to other running CPU prior +to power down of the current CPU. During power up, these interrupt can be +enabled/re-targeted back to the current CPU. + +``` + typedef struct spd_pm_ops { + void (*svc_on)(u_register_t target_cpu); + int32_t (*svc_off)(u_register_t __unused); + void (*svc_suspend)(u_register_t max_off_pwrlvl); + void (*svc_on_finish)(u_register_t __unused); + void (*svc_suspend_finish)(u_register_t max_off_pwrlvl); + int32_t (*svc_migrate)(u_register_t from_cpu, u_register_t to_cpu); + int32_t (*svc_migrate_info)(u_register_t *resident_cpu); + void (*svc_system_off)(void); + void (*svc_system_reset)(void); + } spd_pm_ops_t; +``` +A brief description of each callback is given below: + +* svc_on, svc_off, svc_on_finish + + The `svc_on`, `svc_off` callbacks are called during PSCI_CPU_ON, + PSCI_CPU_OFF APIs respectively. The `svc_on_finish` is called when the + target CPU of PSCI_CPU_ON API powers up and executes the + `psci_warmboot_entrypoint()` PSCI library interface. + +* svc_suspend, svc_suspend_finish + + The `svc_suspend` callback is called during power down bu either + PSCI_SUSPEND or PSCI_SYSTEM_SUSPEND APIs. The `svc_suspend_finish` is + called when the CPU wakes up from suspend and executes the + `psci_warmboot_entrypoint()` PSCI library interface. The `max_off_pwrlvl` + (first parameter) denotes the highest power domain level being powered down + to or woken up from suspend. + +* svc_system_off, svc_system_reset + + These callbacks are called during PSCI_SYSTEM_OFF and PSCI_SYSTEM_RESET + PSCI APIs respectively. + +* svc_migrate_info + + This callback is called in response to PSCI_MIGRATE_INFO_TYPE or + PSCI_MIGRATE_INFO_UP_CPU APIs. The return value of this callback must + correspond to the return value of PSCI_MIGRATE_INFO_TYPE API as described + in [PSCI spec]. If the secure payload is a Uniprocessor (UP) + implementation, then it must update the mpidr of the CPU it is resident in + via `resident_cpu` (first argument). The updates to `resident_cpu` is + ignored if the secure payload is a multiprocessor (MP) implementation. + +* svc_migrate + + This callback is only relevant if the secure payload in EL3 Runtime + Software is a Uniprocessor (UP) implementation and supports migration from + the current CPU `from_cpu` (first argument) to another CPU `to_cpu` + (second argument). This callback is called in response to PSCI_MIGRATE + API. This callback is never called if the secure payload is a + Multiprocessor (MP) implementation. + +### 5.5 CPU operations + +The CPU operations (cpu_ops) framework implement power down sequence specific +to the CPU and the details of which can be found in the `CPU specific +operations framework` section of [Firmware Design]. The ARM Trusted Firmware +tree implements the `cpu_ops` for various supported CPUs and the EL3 Runtime +Software needs to include the required `cpu_ops` in its build. The start and +end of the `cpu_ops` descriptors must be exported by the EL3 Runtime Software +via the `__CPU_OPS_START__` and `__CPU_OPS_END__` linker symbols. + +The `cpu_ops` descriptors also include reset sequences and may include errata +workarounds for the CPU. The EL3 Runtime Software can choose to call this +during cold/warm reset if it does not implement its own reset sequence/errata +workarounds. + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2016, ARM Limited and Contributors. All rights reserved._ + +[PSCI spec]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)" +[SMCCC]: https://silver.arm.com/download/ARM_and_AMBA_Architecture/AR570-DA-80002-r0p0-00rel0/ARM_DEN0028A_SMC_Calling_Convention.pdf "SMC Calling Convention" +[Porting Guide]: porting-guide.md +[Firmware Design]: ./firmware-design.md diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/psci-pd-tree.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/psci-pd-tree.md new file mode 100644 index 0000000..c253905 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/psci-pd-tree.md @@ -0,0 +1,295 @@ +------------ +Requirements +------------ + +1. A platform must export the `plat_get_aff_count()` and + `plat_get_aff_state()` APIs to enable the generic PSCI code to + populate a tree that describes the hierarchy of power domains in the + system. This approach is inflexible because a change to the topology + requires a change in the code. + + It would be much simpler for the platform to describe its power domain tree + in a data structure. + +2. The generic PSCI code generates MPIDRs in order to populate the power domain + tree. It also uses an MPIDR to find a node in the tree. The assumption that + a platform will use exactly the same MPIDRs as generated by the generic PSCI + code is not scalable. The use of an MPIDR also restricts the number of + levels in the power domain tree to four. + + Therefore, there is a need to decouple allocation of MPIDRs from the + mechanism used to populate the power domain topology tree. + +3. The current arrangement of the power domain tree requires a binary search + over the sibling nodes at a particular level to find a specified power + domain node. During a power management operation, the tree is traversed from + a 'start' to an 'end' power level. The binary search is required to find the + node at each level. The natural way to perform this traversal is to + start from a leaf node and follow the parent node pointer to reach the end + level. + + Therefore, there is a need to define data structures that implement the tree in + a way which facilitates such a traversal. + +4. The attributes of a core power domain differ from the attributes of power + domains at higher levels. For example, only a core power domain can be identified + using an MPIDR. There is no requirement to perform state coordination while + performing a power management operation on the core power domain. + + Therefore, there is a need to implement the tree in a way which facilitates this + distinction between a leaf and non-leaf node and any associated + optimizations. + + +------ +Design +------ + +### Describing a power domain tree + +To fulfill requirement 1., the existing platform APIs +`plat_get_aff_count()` and `plat_get_aff_state()` have been +removed. A platform must define an array of unsigned chars such that: + +1. The first entry in the array specifies the number of power domains at the + highest power level implemented in the platform. This caters for platforms + where the power domain tree does not have a single root node, for example, + the FVP has two cluster power domains at the highest level (1). + +2. Each subsequent entry corresponds to a power domain and contains the number + of power domains that are its direct children. + +3. The size of the array minus the first entry will be equal to the number of + non-leaf power domains. + +4. The value in each entry in the array is used to find the number of entries + to consider at the next level. The sum of the values (number of children) of + all the entries at a level specifies the number of entries in the array for + the next level. + +The following example power domain topology tree will be used to describe the +above text further. The leaf and non-leaf nodes in this tree have been numbered +separately. + +``` + +-+ + |0| + +-+ + / \ + / \ + / \ + / \ + / \ + / \ + / \ + / \ + / \ + / \ + +-+ +-+ + |1| |2| + +-+ +-+ + / \ / \ + / \ / \ + / \ / \ + / \ / \ + +-+ +-+ +-+ +-+ + |3| |4| |5| |6| + +-+ +-+ +-+ +-+ + +---+-----+ +----+----| +----+----+ +----+-----+-----+ + | | | | | | | | | | | | | + | | | | | | | | | | | | | + v v v v v v v v v v v v v + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +--+ +--+ +--+ + |0| |1| |2| |3| |4| |5| |6| |7| |8| |9| |10| |11| |12| + +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +-+ +--+ +--+ +--+ +``` + + +This tree is defined by the platform as the array described above as follows: + +``` + #define PLAT_NUM_POWER_DOMAINS 20 + #define PLATFORM_CORE_COUNT 13 + #define PSCI_NUM_NON_CPU_PWR_DOMAINS \ + (PLAT_NUM_POWER_DOMAINS - PLATFORM_CORE_COUNT) + + unsigned char plat_power_domain_tree_desc[] = { 1, 2, 2, 2, 3, 3, 3, 4}; +``` + +### Removing assumptions about MPIDRs used in a platform + +To fulfill requirement 2., it is assumed that the platform assigns a +unique number (core index) between `0` and `PLAT_CORE_COUNT - 1` to each core +power domain. MPIDRs could be allocated in any manner and will not be used to +populate the tree. + +`plat_core_pos_by_mpidr(mpidr)` will return the core index for the core +corresponding to the MPIDR. It will return an error (-1) if an MPIDR is passed +which is not allocated or corresponds to an absent core. The semantics of this +platform API have changed since it is required to validate the passed MPIDR. It +has been made a mandatory API as a result. + +Another mandatory API, `plat_my_core_pos()` has been added to return the core +index for the calling core. This API provides a more lightweight mechanism to get +the index since there is no need to validate the MPIDR of the calling core. + +The platform should assign the core indices (as illustrated in the diagram above) +such that, if the core nodes are numbered from left to right, then the index +for a core domain will be the same as the index returned by + `plat_core_pos_by_mpidr()` or `plat_my_core_pos()` for that core. This +relationship allows the core nodes to be allocated in a separate array +(requirement 4.) during `psci_setup()` in such an order that the index of the +core in the array is the same as the return value from these APIs. + +#### Dealing with holes in MPIDR allocation + +For platforms where the number of allocated MPIDRs is equal to the number of +core power domains, for example, Juno and FVPs, the logic to convert an MPIDR to +a core index should remain unchanged. Both Juno and FVP use a simple collision +proof hash function to do this. + +It is possible that on some platforms, the allocation of MPIDRs is not +contiguous or certain cores have been disabled. This essentially means that the +MPIDRs have been sparsely allocated, that is, the size of the range of MPIDRs +used by the platform is not equal to the number of core power domains. + +The platform could adopt one of the following approaches to deal with this +scenario: + +1. Implement more complex logic to convert a valid MPIDR to a core index while + maintaining the relationship described earlier. This means that the power + domain tree descriptor will not describe any core power domains which are + disabled or absent. Entries will not be allocated in the tree for these + domains. + +2. Treat unallocated MPIDRs and disabled cores as absent but still describe them + in the power domain descriptor, that is, the number of core nodes described + is equal to the size of the range of MPIDRs allocated. This approach will + lead to memory wastage since entries will be allocated in the tree but will + allow use of a simpler logic to convert an MPIDR to a core index. + + +### Traversing through and distinguishing between core and non-core power domains + +To fulfill requirement 3 and 4, separate data structures have been defined +to represent leaf and non-leaf power domain nodes in the tree. + +``` +/******************************************************************************* + * The following two data structures implement the power domain tree. The tree + * is used to track the state of all the nodes i.e. power domain instances + * described by the platform. The tree consists of nodes that describe CPU power + * domains i.e. leaf nodes and all other power domains which are parents of a + * CPU power domain i.e. non-leaf nodes. + ******************************************************************************/ +typedef struct non_cpu_pwr_domain_node { + /* + * Index of the first CPU power domain node level 0 which has this node + * as its parent. + */ + unsigned int cpu_start_idx; + + /* + * Number of CPU power domains which are siblings of the domain indexed + * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx + * -> cpu_start_idx + ncpus' have this node as their parent. + */ + unsigned int ncpus; + + /* Index of the parent power domain node */ + unsigned int parent_node; + + ----- +} non_cpu_pd_node_t; + +typedef struct cpu_pwr_domain_node { + u_register_t mpidr; + + /* Index of the parent power domain node */ + unsigned int parent_node; + + ----- +} cpu_pd_node_t; +``` + +The power domain tree is implemented as a combination of the following data +structures. + +``` +non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; +cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; +``` + +### Populating the power domain tree + +The `populate_power_domain_tree()` function in `psci_setup.c` implements the +algorithm to parse the power domain descriptor exported by the platform to +populate the two arrays. It is essentially a breadth-first-search. The nodes for +each level starting from the root are laid out one after another in the +`psci_non_cpu_pd_nodes` and `psci_cpu_pd_nodes` arrays as follows: + +``` +psci_non_cpu_pd_nodes -> [[Level 3 nodes][Level 2 nodes][Level 1 nodes]] +psci_cpu_pd_nodes -> [Level 0 nodes] +``` + +For the example power domain tree illustrated above, the `psci_cpu_pd_nodes` +will be populated as follows. The value in each entry is the index of the parent +node. Other fields have been ignored for simplicity. + +``` + +-------------+ ^ + CPU0 | 3 | | + +-------------+ | + CPU1 | 3 | | + +-------------+ | + CPU2 | 3 | | + +-------------+ | + CPU3 | 4 | | + +-------------+ | + CPU4 | 4 | | + +-------------+ | + CPU5 | 4 | | PLATFORM_CORE_COUNT + +-------------+ | + CPU6 | 5 | | + +-------------+ | + CPU7 | 5 | | + +-------------+ | + CPU8 | 5 | | + +-------------+ | + CPU9 | 6 | | + +-------------+ | + CPU10 | 6 | | + +-------------+ | + CPU11 | 6 | | + +-------------+ | + CPU12 | 6 | v + +-------------+ +``` + +The `psci_non_cpu_pd_nodes` array will be populated as follows. The value in +each entry is the index of the parent node. + +``` + +-------------+ ^ + PD0 | -1 | | + +-------------+ | + PD1 | 0 | | + +-------------+ | + PD2 | 0 | | + +-------------+ | + PD3 | 1 | | PLAT_NUM_POWER_DOMAINS - + +-------------+ | PLATFORM_CORE_COUNT + PD4 | 1 | | + +-------------+ | + PD5 | 2 | | + +-------------+ | + PD6 | 2 | | + +-------------+ v +``` + +Each core can find its node in the `psci_cpu_pd_nodes` array using the +`plat_my_core_pos()` function. When a core is turned on, the normal world +provides an MPIDR. The `plat_core_pos_by_mpidr()` function is used to validate +the MPIDR before using it to find the corresponding core node. The non-core power +domain nodes do not need to be identified. diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/reset-design.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/reset-design.md new file mode 100644 index 0000000..3e45d41 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/reset-design.md @@ -0,0 +1,172 @@ +ARM Trusted Firmware Reset Design +================================= + +1. [Introduction](#1--introduction) +2. [General reset code flow](#2--general-reset-code-flow) +3. [Programmable CPU reset address](#3--programmable-cpu-reset-address) +4. [Cold boot on a single CPU](#4--cold-boot-on-a-single-cpu) +5. [Programmable CPU reset address, Cold boot on a single CPU](#5--programmable-cpu-reset-address-cold-boot-on-a-single-cpu) +6. [Using BL31 entrypoint as the reset address](#6--using-bl31-entrypoint-as-the-reset-address) + + +1. Introduction +---------------- + +This document describes the high-level design of the framework to handle CPU +resets in ARM Trusted Firmware. It also describes how the platform integrator +can tailor this code to the system configuration to some extent, resulting in a +simplified and more optimised boot flow. + +This document should be used in conjunction with the [Firmware Design], which +provides greater implementation details around the reset code, specifically +for the cold boot path. + + +2. General reset code flow +--------------------------- + +The ARM Trusted Firmware (TF) reset code is implemented in BL1 by default. The +following high-level diagram illustrates this: + +![Default reset code flow](diagrams/default_reset_code.png?raw=true) + +This diagram shows the default, unoptimised reset flow. Depending on the system +configuration, some of these steps might be unnecessary. The following sections +guide the platform integrator by indicating which build options exclude which +steps, depending on the capability of the platform. + +Note: If BL31 is used as the Trusted Firmware entry point instead of BL1, the +diagram above is still relevant, as all these operations will occur in BL31 in +this case. Please refer to section 6 "Using BL31 entrypoint as the reset +address" for more information. + + +3. Programmable CPU reset address +---------------------------------- + +By default, the TF assumes that the CPU reset address is not programmable. +Therefore, all CPUs start at the same address (typically address 0) whenever +they reset. Further logic is then required to identify whether it is a cold or +warm boot to direct CPUs to the right execution path. + +If the reset vector address (reflected in the reset vector base address register +`RVBAR_EL3`) is programmable then it is possible to make each CPU start directly +at the right address, both on a cold and warm reset. Therefore, the boot type +detection can be skipped, resulting in the following boot flow: + +![Reset code flow with programmable reset address]( +diagrams/reset_code_no_boot_type_check.png?raw=true) + +To enable this boot flow, compile the TF with `PROGRAMMABLE_RESET_ADDRESS=1`. +This option only affects the TF reset image, which is BL1 by default or BL31 if +`RESET_TO_BL31=1`. + +On both the FVP and Juno platforms, the reset vector address is not programmable +so both ports use `PROGRAMMABLE_RESET_ADDRESS=0`. + + +4. Cold boot on a single CPU +----------------------------- + +By default, the TF assumes that several CPUs may be released out of reset. +Therefore, the cold boot code has to arbitrate access to hardware resources +shared amongst CPUs. This is done by nominating one of the CPUs as the primary, +which is responsible for initialising shared hardware and coordinating the boot +flow with the other CPUs. + +If the platform guarantees that only a single CPU will ever be brought up then +no arbitration is required. The notion of primary/secondary CPU itself no longer +applies. This results in the following boot flow: + +![Reset code flow with single CPU released out of reset]( +diagrams/reset_code_no_cpu_check.png?raw=true) + +To enable this boot flow, compile the TF with `COLD_BOOT_SINGLE_CPU=1`. This +option only affects the TF reset image, which is BL1 by default or BL31 if +`RESET_TO_BL31=1`. + +On both the FVP and Juno platforms, although only one core is powered up by +default, there are platform-specific ways to release any number of cores out of +reset. Therefore, both platform ports use `COLD_BOOT_SINGLE_CPU=0`. + + +5. Programmable CPU reset address, Cold boot on a single CPU +------------------------------------------------------------- + +It is obviously possible to combine both optimisations on platforms that have +a programmable CPU reset address and which release a single CPU out of reset. +This results in the following boot flow: + +![Reset code flow with programmable reset address and single CPU released out of +reset](diagrams/reset_code_no_checks.png?raw=true) + +To enable this boot flow, compile the TF with both `COLD_BOOT_SINGLE_CPU=1` +and `PROGRAMMABLE_RESET_ADDRESS=1`. These options only affect the TF reset +image, which is BL1 by default or BL31 if `RESET_TO_BL31=1`. + + +6. Using BL31 entrypoint as the reset address +---------------------------------------------- + +On some platforms the runtime firmware (BL3x images) for the application +processors are loaded by some firmware running on a secure system processor +on the SoC, rather than by BL1 and BL2 running on the primary application +processor. For this type of SoC it is desirable for the application processor +to always reset to BL31 which eliminates the need for BL1 and BL2. + +TF provides a build-time option `RESET_TO_BL31` that includes some additional +logic in the BL31 entry point to support this use case. + +In this configuration, the platform's Trusted Boot Firmware must ensure that +BL31 is loaded to its runtime address, which must match the CPU's `RVBAR_EL3` +reset vector base address, before the application processor is powered on. +Additionally, platform software is responsible for loading the other BL3x images +required and providing entry point information for them to BL31. Loading these +images might be done by the Trusted Boot Firmware or by platform code in BL31. + +Although the ARM FVP platform does not support programming the reset base +address dynamically at run-time, it is possible to set the initial value of the +`RVBAR_EL3` register at start-up. This feature is provided on the Base FVP only. +It allows the ARM FVP port to support the `RESET_TO_BL31` configuration, in +which case the `bl31.bin` image must be loaded to its run address in Trusted +SRAM and all CPU reset vectors be changed from the default `0x0` to this run +address. See the [User Guide] for details of running the FVP models in this way. + +Although technically it would be possible to program the reset base address with +the right support in the SCP firmware, this is currently not implemented so the +Juno port doesn't support the `RESET_TO_BL31` configuration. + +The `RESET_TO_BL31` configuration requires some additions and changes in the +BL31 functionality: + +#### Determination of boot path + +In this configuration, BL31 uses the same reset framework and code as the one +described for BL1 above. Therefore, it is affected by the +`PROGRAMMABLE_RESET_ADDRESS` and `COLD_BOOT_SINGLE_CPU` build options in the +same way. + +In the default, unoptimised BL31 reset flow, on a warm boot a CPU is directed +to the PSCI implementation via a platform defined mechanism. On a cold boot, +the platform must place any secondary CPUs into a safe state while the primary +CPU executes a modified BL31 initialization, as described below. + +#### Platform initialization + +In this configuration, when the CPU resets to BL31 there are no parameters that +can be passed in registers by previous boot stages. Instead, the platform code +in BL31 needs to know, or be able to determine, the location of the BL32 (if +required) and BL33 images and provide this information in response to the +`bl31_plat_get_next_image_ep_info()` function. + +Additionally, platform software is responsible for carrying out any security +initialisation, for example programming a TrustZone address space controller. +This might be done by the Trusted Boot Firmware or by platform code in BL31. + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2015, ARM Limited and Contributors. All rights reserved._ + + +[User Guide]: user-guide.md +[Firmware Design]: firmware-design.md diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/rt-svc-writers-guide.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/rt-svc-writers-guide.md new file mode 100644 index 0000000..4b811fe --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/rt-svc-writers-guide.md @@ -0,0 +1,307 @@ +EL3 Runtime Service Writers Guide for ARM Trusted Firmware +========================================================== + +Contents +-------- + +1. [Introduction](#1--introduction) +2. [Owning Entities, Call Types and Function IDs](#2--owning-entities-call-types-and-function-ids) +3. [Getting started](#3--getting-started) +4. [Registering a runtime service](#4--registering-a-runtime-service) +5. [Initializing a runtime service](#5-initializing-a-runtime-service) +6. [Handling runtime service requests](#6--handling-runtime-service-requests) +7. [Services that contain multiple sub-services](#7--services-that-contain-multiple-sub-services) +8. [Secure-EL1 Payload Dispatcher service (SPD)](#8--secure-el1-payload-dispatcher-service-spd) + +- - - - - - - - - - - - - - - - - - + +1. Introduction +---------------- + +This document describes how to add a runtime service to the EL3 Runtime +Firmware component of ARM Trusted Firmware (BL31). + +Software executing in the normal world and in the trusted world at exception +levels lower than EL3 will request runtime services using the Secure Monitor +Call (SMC) instruction. These requests will follow the convention described in +the SMC Calling Convention PDD ([SMCCC]). The [SMCCC] assigns function +identifiers to each SMC request and describes how arguments are passed and +results are returned. + +SMC Functions are grouped together based on the implementor of the service, for +example a subset of the Function IDs are designated as "OEM Calls" (see [SMCCC] +for full details). The EL3 runtime services framework in BL31 enables the +independent implementation of services for each group, which are then compiled +into the BL31 image. This simplifies the integration of common software from +ARM to support [PSCI], Secure Monitor for a Trusted OS and SoC specific +software. The common runtime services framework ensures that SMC Functions are +dispatched to their respective service implementation - the [Firmware Design] +provides details of how this is achieved. + +The interface and operation of the runtime services depends heavily on the +concepts and definitions described in the [SMCCC], in particular SMC Function +IDs, Owning Entity Numbers (OEN), Fast and Standard calls, and the SMC32 and +SMC64 calling conventions. Please refer to that document for a full explanation +of these terms. + + +2. Owning Entities, Call Types and Function IDs +------------------------------------------------ + +The SMC Function Identifier includes a OEN field. These values and their +meaning are described in [SMCCC] and summarized in table 1 below. Some entities +are allocated a range of of OENs. The OEN must be interpreted in conjunction +with the SMC call type, which is either _Fast_ or _Standard_. Fast calls are +uninterruptible whereas Standard calls can be pre-empted. The majority of +Owning Entities only have allocated ranges for Fast calls: Standard calls are +reserved exclusively for Trusted OS providers or for interoperability with +legacy 32-bit software that predates the [SMCCC]. + + Type OEN Service + Fast 0 ARM Architecture calls + Fast 1 CPU Service calls + Fast 2 SiP Service calls + Fast 3 OEM Service calls + Fast 4 Standard Service calls + Fast 5-47 Reserved for future use + Fast 48-49 Trusted Application calls + Fast 50-63 Trusted OS calls + + Std 0- 1 Reserved for existing ARMv7 calls + Std 2-63 Trusted OS Standard Calls + +_Table 1: Service types and their corresponding Owning Entity Numbers_ + +Each individual entity can allocate the valid identifiers within the entity +range as they need - it is not necessary to coordinate with other entities of +the same type. For example, two SoC providers can use the same Function ID +within the SiP Service calls OEN range to mean different things - as these +calls should be specific to the SoC. The Standard Runtime Calls OEN is used for +services defined by ARM standards, such as [PSCI]. + +The SMC Function ID also indicates whether the call has followed the SMC32 +calling convention, where all parameters are 32-bit, or the SMC64 calling +convention, where the parameters are 64-bit. The framework identifies and +rejects invalid calls that use the SMC64 calling convention but that originate +from an AArch32 caller. + +The EL3 runtime services framework uses the call type and OEN to identify a +specific handler for each SMC call, but it is expected that an individual +handler will be responsible for all SMC Functions within a given service type. + + +3. Getting started +------------------- + +ARM Trusted Firmware has a [`services`] directory in the source tree under which +each owning entity can place the implementation of its runtime service. The +[PSCI] implementation is located here in the [`lib/psci`] directory. + +Runtime service sources will need to include the [`runtime_svc.h`] header file. + + +4. Registering a runtime service +--------------------------------- + +A runtime service is registered using the `DECLARE_RT_SVC()` macro, specifying +the name of the service, the range of OENs covered, the type of service and +initialization and call handler functions. + + #define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) + +* `_name` is used to identify the data structure declared by this macro, and + is also used for diagnostic purposes + +* `_start` and `_end` values must be based on the `OEN_*` values defined in + [`smcc.h`] + +* `_type` must be one of `SMC_TYPE_FAST` or `SMC_TYPE_STD` + +* `_setup` is the initialization function with the `rt_svc_init` signature: + + typedef int32_t (*rt_svc_init)(void); + +* `_smch` is the SMC handler function with the `rt_svc_handle` signature: + + typedef uintptr_t (*rt_svc_handle_t)(uint32_t smc_fid, + u_register_t x1, u_register_t x2, + u_register_t x3, u_register_t x4, + void *cookie, + void *handle, + u_register_t flags); + +Details of the requirements and behavior of the two callbacks is provided in +the following sections. + +During initialization the services framework validates each declared service +to ensure that the following conditions are met: + +1. The `_start` OEN is not greater than the `_end` OEN +2. The `_end` OEN does not exceed the maximum OEN value (63) +3. The `_type` is one of `SMC_TYPE_FAST` or `SMC_TYPE_STD` +4. `_setup` and `_smch` routines have been specified + +[`std_svc_setup.c`] provides an example of registering a runtime service: + + /* Register Standard Service Calls as runtime service */ + DECLARE_RT_SVC( + std_svc, + OEN_STD_START, + OEN_STD_END, + SMC_TYPE_FAST, + std_svc_setup, + std_svc_smc_handler + ); + + +5. Initializing a runtime service +--------------------------------- + +Runtime services are initialized once, during cold boot, by the primary CPU +after platform and architectural initialization is complete. The framework +performs basic validation of the declared service before calling +the service initialization function (`_setup` in the declaration). This +function must carry out any essential EL3 initialization prior to receiving a +SMC Function call via the handler function. + +On success, the initialization function must return `0`. Any other return value +will cause the framework to issue a diagnostic: + + Error initializing runtime service + +and then ignore the service - the system will continue to boot but SMC calls +will not be passed to the service handler and instead return the _Unknown SMC +Function ID_ result `0xFFFFFFFF`. + +If the system must not be allowed to proceed without the service, the +initialization function must itself cause the firmware boot to be halted. + +If the service uses per-CPU data this must either be initialized for all CPUs +during this call, or be done lazily when a CPU first issues an SMC call to that +service. + + +6. Handling runtime service requests +------------------------------------- + +SMC calls for a service are forwarded by the framework to the service's SMC +handler function (`_smch` in the service declaration). This function must have +the following signature: + + typedef uintptr_t (*rt_svc_handle_t)(uint32_t smc_fid, + u_register_t x1, u_register_t x2, + u_register_t x3, u_register_t x4, + void *cookie, + void *handle, + u_register_t flags); + +The handler is responsible for: + +1. Determining that `smc_fid` is a valid and supported SMC Function ID, + otherwise completing the request with the _Unknown SMC Function ID_: + + SMC_RET1(handle, SMC_UNK); + +2. Determining if the requested function is valid for the calling security + state. SMC Calls can be made from both the normal and trusted worlds and + the framework will forward all calls to the service handler. + + The `flags` parameter to this function indicates the caller security state + in bit[0], where a value of `1` indicates a non-secure caller. The + `is_caller_secure(flags)` and `is_caller_non_secure(flags)` can be used to + test this condition. + + If invalid, the request should be completed with: + + SMC_RET1(handle, SMC_UNK); + +3. Truncating parameters for calls made using the SMC32 calling convention. + Such calls can be determined by checking the CC field in bit[30] of the + `smc_fid` parameter, for example by using: + + if (GET_SMC_CC(smc_fid) == SMC_32) ... + + For such calls, the upper bits of the parameters x1-x4 and the saved + parameters X5-X7 are UNDEFINED and must be explicitly ignored by the + handler. This can be done by truncating the values to a suitable 32-bit + integer type before use, for example by ensuring that functions defined + to handle individual SMC Functions use appropriate 32-bit parameters. + +4. Providing the service requested by the SMC Function, utilizing the + immediate parameters x1-x4 and/or the additional saved parameters X5-X7. + The latter can be retrieved using the `SMC_GET_GP(handle, ref)` function, + supplying the appropriate `CTX_GPREG_Xn` reference, e.g. + + uint64_t x6 = SMC_GET_GP(handle, CTX_GPREG_X6); + +5. Implementing the standard SMC32 Functions that provide information about + the implementation of the service. These are the Call Count, Implementor + UID and Revision Details for each service documented in section 6 of the + [SMCCC]. + + The ARM Trusted Firmware expects owning entities to follow this + recommendation. + +5. Returning the result to the caller. The [SMCCC] allows for up to 256 bits + of return value in SMC64 using X0-X3 and 128 bits in SMC32 using W0-W3. The + framework provides a family of macros to set the multi-register return + value and complete the handler: + + SMC_RET1(handle, x0); + SMC_RET2(handle, x0, x1); + SMC_RET3(handle, x0, x1, x2); + SMC_RET4(handle, x0, x1, x2, x3); + +The `cookie` parameter to the handler is reserved for future use and can be +ignored. The `handle` is returned by the SMC handler - completion of the +handler function must always be via one of the `SMC_RETn()` macros. + +NOTE: The PSCI and Test Secure-EL1 Payload Dispatcher services do not follow +all of the above requirements yet. + + +7. Services that contain multiple sub-services +----------------------------------------------- + +It is possible that a single owning entity implements multiple sub-services. For +example, the Standard calls service handles `0x84000000`-`0x8400FFFF` and +`0xC4000000`-`0xC400FFFF` functions. Within that range, the [PSCI] service +handles the `0x84000000`-`0x8400001F` and `0xC4000000`-`0xC400001F` functions. +In that respect, [PSCI] is a 'sub-service' of the Standard calls service. In +future, there could be additional such sub-services in the Standard calls +service which perform independent functions. + +In this situation it may be valuable to introduce a second level framework to +enable independent implementation of sub-services. Such a framework might look +very similar to the current runtime services framework, but using a different +part of the SMC Function ID to identify the sub-service. Trusted Firmware does +not provide such a framework at present. + + +8. Secure-EL1 Payload Dispatcher service (SPD) +----------------------------------------------- + +Services that handle SMC Functions targeting a Trusted OS, Trusted Application, +or other Secure-EL1 Payload are special. These services need to manage the +Secure-EL1 context, provide the _Secure Monitor_ functionality of switching +between the normal and secure worlds, deliver SMC Calls through to Secure-EL1 +and generally manage the Secure-EL1 Payload through CPU power-state transitions. + +TODO: Provide details of the additional work required to implement a SPD and +the BL31 support for these services. Or a reference to the document that will +provide this information.... + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved._ + + +[Firmware Design]: ./firmware-design.md +[`services`]: ../services +[`lib/psci`]: ../lib/psci +[`std_svc_setup.c`]: ../services/std_svc/std_svc_setup.c +[`runtime_svc.h`]: ../include/common/runtime_svc.h +[`smcc.h`]: ../include/lib/smcc.h +[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)" +[SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)" diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/spd/optee-dispatcher.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/spd/optee-dispatcher.md new file mode 100644 index 0000000..c154f6b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/spd/optee-dispatcher.md @@ -0,0 +1,13 @@ +OP-TEE Dispatcher +================= + +[OP-TEE OS] is a Trusted OS running as Secure EL1. + +To build and execute [OP-TEE OS] follow the instructions at +[ARM Trusted Firmware with OP-TEE] [OP-TEE OS] + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2014, ARM Limited and Contributors. All rights reserved._ + +[OP-TEE OS]: http://github.com/OP-TEE/optee_os/tree/master/documentation/arm_trusted_firmware.md diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/spd/tlk-dispatcher.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/spd/tlk-dispatcher.md new file mode 100644 index 0000000..40c8344 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/spd/tlk-dispatcher.md @@ -0,0 +1,70 @@ +Trusted Little Kernel (TLK) Dispatcher +======================================= +TLK dispatcher adds support for NVIDIA's Trusted Little Kernel (TLK) to work +with the Trusted Firmware. TLK-D can be compiled by including it in the +platform's makefile. TLK is primarily meant to work with Tegra SoCs, so until +Trusted Firmware starts supporting Tegra, the dispatcher code can only be +compiled for other platforms. + +In order to compile TLK-D, we need a BL32 image to be present. Since, TLKD +just needs to compile, any BL32 image would do. To use TLK as the BL32, please +refer to the "Build TLK" section. + +Once a BL32 is ready, TLKD can be included in the image by adding "SPD=tlkd" +to the build command. + +Trusted Little Kernel (TLK) +=========================== +TLK is a Trusted OS running as Secure EL1. It is a Free Open Source Software +(FOSS) release of the NVIDIA® Trusted Little Kernel (TLK) technology, which +extends technology made available with the development of the Little Kernel (LK). +You can download the LK modular embedded preemptive kernel for use on ARM, +x86, and AVR32 systems from https://github.com/travisg/lk + +NVIDIA implemented its Trusted Little Kernel (TLK) technology, designed as a +free and open-source trusted execution environment (OTE). + +TLK features include: + +• Small, pre-emptive kernel +• Supports multi-threading, IPCs, and thread scheduling +• Added TrustZone features +• Added Secure Storage +• Under MIT/FreeBSD license + +NVIDIA extensions to Little Kernel (LK) include: + +• User mode +• Address-space separation for TAs +• TLK Client Application (CA) library +• TLK TA library +• Crypto library (encrypt/decrypt, key handling) via OpenSSL +• Linux kernel driver +• Cortex A9/A15 support +• Power Management +• TrustZone memory carve-out (reconfigurable) +• Page table management +• Debugging support over UART (USB planned) + +TLK is hosted by NVIDIA on http://nv-tegra.nvidia.com under the +3rdparty/ote_partner/tlk.git repository. Detailed information about +TLK and OTE can be found in the Tegra_BSP_for_Android_TLK_FOSS_Reference.pdf +manual located under the "documentation" directory_. + +Build TLK +========= +To build and execute TLK, follow the instructions from "Building a TLK Device" +section from Tegra_BSP_for_Android_TLK_FOSS_Reference.pdf manual. + +Input parameters to TLK +======================= +TLK expects the TZDRAM size and a structure containing the boot arguments. BL2 +passes this information to the EL3 software as members of the bl32_ep_info +struct, where bl32_ep_info is part of bl31_params_t (passed by BL2 in X0) + +Example: +-------- + bl32_ep_info->args.arg0 = TZDRAM size available for BL32 + bl32_ep_info->args.arg1 = unused (used only on ARMv7) + bl32_ep_info->args.arg2 = pointer to boot args + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/trusted-board-boot.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/trusted-board-boot.md new file mode 100644 index 0000000..833b5db --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/trusted-board-boot.md @@ -0,0 +1,251 @@ +Trusted Board Boot Design Guide +=============================== + +Contents : + +1. [Introduction](#1--introduction) +2. [Chain of Trust](#2--chain-of-trust) +3. [Trusted Board Boot Sequence](#3--trusted-board-boot-sequence) +4. [Authentication Framework](#4--authentication-framework) +5. [Certificate Generation Tool](#5--certificate-generation-tool) + + +1. Introduction +---------------- + +The Trusted Board Boot (TBB) feature prevents malicious firmware from running on +the platform by authenticating all firmware images up to and including the +normal world bootloader. It does this by establishing a Chain of Trust using +Public-Key-Cryptography Standards (PKCS). + +This document describes the design of ARM Trusted Firmware TBB, which is an +implementation of the Trusted Board Boot Requirements (TBBR) specification, +ARM DEN0006C-1. It should be used in conjunction with the [Firmware Update] +design document, which implements a specific aspect of the TBBR. + + +2. Chain of Trust +------------------ + +A Chain of Trust (CoT) starts with a set of implicitly trusted components. On +the ARM development platforms, these components are: + +* A SHA-256 hash of the Root of Trust Public Key (ROTPK). It is stored in the + trusted root-key storage registers. + +* The BL1 image, on the assumption that it resides in ROM so cannot be + tampered with. + +The remaining components in the CoT are either certificates or boot loader +images. The certificates follow the [X.509 v3] standard. This standard +enables adding custom extensions to the certificates, which are used to store +essential information to establish the CoT. + +In the TBB CoT all certificates are self-signed. There is no need for a +Certificate Authority (CA) because the CoT is not established by verifying the +validity of a certificate's issuer but by the content of the certificate +extensions. To sign the certificates, the PKCS#1 SHA-256 with RSA Encryption +signature scheme is used with a RSA key length of 2048 bits. Future version of +Trusted Firmware will support additional cryptographic algorithms. + +The certificates are categorised as "Key" and "Content" certificates. Key +certificates are used to verify public keys which have been used to sign content +certificates. Content certificates are used to store the hash of a boot loader +image. An image can be authenticated by calculating its hash and matching it +with the hash extracted from the content certificate. The SHA-256 function is +used to calculate all hashes. The public keys and hashes are included as +non-standard extension fields in the [X.509 v3] certificates. + +The keys used to establish the CoT are: + +* **Root of trust key** + + The private part of this key is used to sign the BL2 content certificate and + the trusted key certificate. The public part is the ROTPK. + +* **Trusted world key** + + The private part is used to sign the key certificates corresponding to the + secure world images (SCP_BL2, BL31 and BL32). The public part is stored in + one of the extension fields in the trusted world certificate. + +* **Non-trusted world key** + + The private part is used to sign the key certificate corresponding to the + non secure world image (BL33). The public part is stored in one of the + extension fields in the trusted world certificate. + +* **BL3-X keys** + + For each of SCP_BL2, BL31, BL32 and BL33, the private part is used to + sign the content certificate for the BL3-X image. The public part is stored + in one of the extension fields in the corresponding key certificate. + +The following images are included in the CoT: + +* BL1 +* BL2 +* SCP_BL2 (optional) +* BL31 +* BL33 +* BL32 (optional) + +The following certificates are used to authenticate the images. + +* **BL2 content certificate** + + It is self-signed with the private part of the ROT key. It contains a hash + of the BL2 image. + +* **Trusted key certificate** + + It is self-signed with the private part of the ROT key. It contains the + public part of the trusted world key and the public part of the non-trusted + world key. + +* **SCP_BL2 key certificate** + + It is self-signed with the trusted world key. It contains the public part of + the SCP_BL2 key. + +* **SCP_BL2 content certificate** + + It is self-signed with the SCP_BL2 key. It contains a hash of the SCP_BL2 + image. + +* **BL31 key certificate** + + It is self-signed with the trusted world key. It contains the public part of + the BL31 key. + +* **BL31 content certificate** + + It is self-signed with the BL31 key. It contains a hash of the BL31 image. + +* **BL32 key certificate** + + It is self-signed with the trusted world key. It contains the public part of + the BL32 key. + +* **BL32 content certificate** + + It is self-signed with the BL32 key. It contains a hash of the BL32 image. + +* **BL33 key certificate** + + It is self-signed with the non-trusted world key. It contains the public + part of the BL33 key. + +* **BL33 content certificate** + + It is self-signed with the BL33 key. It contains a hash of the BL33 image. + +The SCP_BL2 and BL32 certificates are optional, but they must be present if the +corresponding SCP_BL2 or BL32 images are present. + + +3. Trusted Board Boot Sequence +------------------------------- + +The CoT is verified through the following sequence of steps. The system panics +if any of the steps fail. + +* BL1 loads and verifies the BL2 content certificate. The issuer public key is + read from the verified certificate. A hash of that key is calculated and + compared with the hash of the ROTPK read from the trusted root-key storage + registers. If they match, the BL2 hash is read from the certificate. + + Note: the matching operation is platform specific and is currently + unimplemented on the ARM development platforms. + +* BL1 loads the BL2 image. Its hash is calculated and compared with the hash + read from the certificate. Control is transferred to the BL2 image if all + the comparisons succeed. + +* BL2 loads and verifies the trusted key certificate. The issuer public key is + read from the verified certificate. A hash of that key is calculated and + compared with the hash of the ROTPK read from the trusted root-key storage + registers. If the comparison succeeds, BL2 reads and saves the trusted and + non-trusted world public keys from the verified certificate. + +The next two steps are executed for each of the SCP_BL2, BL31 & BL32 images. +The steps for the optional SCP_BL2 and BL32 images are skipped if these images +are not present. + +* BL2 loads and verifies the BL3x key certificate. The certificate signature + is verified using the trusted world public key. If the signature + verification succeeds, BL2 reads and saves the BL3x public key from the + certificate. + +* BL2 loads and verifies the BL3x content certificate. The signature is + verified using the BL3x public key. If the signature verification succeeds, + BL2 reads and saves the BL3x image hash from the certificate. + +The next two steps are executed only for the BL33 image. + +* BL2 loads and verifies the BL33 key certificate. If the signature + verification succeeds, BL2 reads and saves the BL33 public key from the + certificate. + +* BL2 loads and verifies the BL33 content certificate. If the signature + verification succeeds, BL2 reads and saves the BL33 image hash from the + certificate. + +The next step is executed for all the boot loader images. + +* BL2 calculates the hash of each image. It compares it with the hash obtained + from the corresponding content certificate. The image authentication succeeds + if the hashes match. + +The Trusted Board Boot implementation spans both generic and platform-specific +BL1 and BL2 code, and in tool code on the host build machine. The feature is +enabled through use of specific build flags as described in the [User Guide]. + +On the host machine, a tool generates the certificates, which are included in +the FIP along with the boot loader images. These certificates are loaded in +Trusted SRAM using the IO storage framework. They are then verified by an +Authentication module included in the Trusted Firmware. + +The mechanism used for generating the FIP and the Authentication module are +described in the following sections. + + +4. Authentication Framework +---------------------------- + +The authentication framework included in the Trusted Firmware provides support +to implement the desired trusted boot sequence. ARM platforms use this framework +to implement the boot requirements specified in the TBBR-client document. + +More information about the authentication framework can be found in the +[Auth Framework] document. + + +5. Certificate Generation Tool +------------------------------- + +The `cert_create` tool is built and runs on the host machine as part of the +Trusted Firmware build process when `GENERATE_COT=1`. It takes the boot loader +images and keys as inputs (keys must be in PEM format) and generates the +certificates (in DER format) required to establish the CoT. New keys can be +generated by the tool in case they are not provided. The certificates are then +passed as inputs to the `fiptool` utility for creating the FIP. + +The certificates are also stored individually in the in the output build +directory. + +The tool resides in the `tools/cert_create` directory. It uses OpenSSL SSL +library version 1.0.1 or later to generate the X.509 certificates. Instructions +for building and using the tool can be found in the [User Guide]. + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2015, ARM Limited and Contributors. All rights reserved._ + + +[X.509 v3]: http://www.ietf.org/rfc/rfc5280.txt +[X.690]: http://www.itu.int/ITU-T/studygroups/com17/languages/X.690-0207.pdf +[Auth Framework]: auth-framework.md +[User Guide]: user-guide.md +[Firmware Update]: firmware-update.md diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/docs/user-guide.md b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/user-guide.md new file mode 100644 index 0000000..5b73b66 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/docs/user-guide.md @@ -0,0 +1,1447 @@ +ARM Trusted Firmware User Guide +=============================== + +Contents : + +1. [Introduction](#1--introduction) +2. [Host machine requirements](#2--host-machine-requirements) +3. [Tools](#3--tools) +4. [Getting the Trusted Firmware source code](#4--getting-the-trusted-firmware-source-code) +5. [Building the Trusted Firmware](#5--building-the-trusted-firmware) +6. [Building a FIP for Juno and FVP](#6--building-a-fip-for-juno-and-fvp) +7. [EL3 payloads alternative boot flow](#7--el3-payloads-alternative-boot-flow) +8. [Preloaded BL33 alternative boot flow](#8--preloaded-bl33-alternative-boot-flow) +9. [Running the software on FVP](#9--running-the-software-on-fvp) +10. [Running the software on Juno](#10--running-the-software-on-juno) + + +1. Introduction +---------------- + +This document describes how to build ARM Trusted Firmware (TF) and run it with a +tested set of other software components using defined configurations on the Juno +ARM development platform and ARM Fixed Virtual Platform (FVP) models. It is +possible to use other software components, configurations and platforms but that +is outside the scope of this document. + +This document assumes that the reader has previous experience running a fully +bootable Linux software stack on Juno or FVP using the prebuilt binaries and +filesystems provided by [Linaro][Linaro Release Notes]. Further information may +be found in the [Instructions for using the Linaro software deliverables] +[Linaro SW Instructions]. It also assumes that the user understands the role of +the different software components required to boot a Linux system: + +* Specific firmware images required by the platform (e.g. SCP firmware on Juno) +* Normal world bootloader (e.g. UEFI or U-Boot) +* Device tree +* Linux kernel image +* Root filesystem + +This document also assumes that the user is familiar with the FVP models and +the different command line options available to launch the model. + +This document should be used in conjunction with the [Firmware Design]. + + +2. Host machine requirements +----------------------------- + +The minimum recommended machine specification for building the software and +running the FVP models is a dual-core processor running at 2GHz with 12GB of +RAM. For best performance, use a machine with a quad-core processor running at +2.6GHz with 16GB of RAM. + +The software has been tested on Ubuntu 14.04 LTS (64-bit). Packages used for +building the software were installed from that distribution unless otherwise +specified. + +The software has also been built on Windows 7 Enterprise SP1, using CMD.EXE, +Cygwin, and Msys (MinGW) shells, using version 4.9.1 of the GNU toolchain. + +3. Tools +--------- + +Install the required packages to build Trusted Firmware with the following +command: + + sudo apt-get install build-essential gcc make git libssl-dev + +Download and install the AArch64 little-endian GCC cross compiler as indicated +in the [Linaro instructions][Linaro SW Instructions]. + +In addition, the following optional packages and tools may be needed: + +* `device-tree-compiler` package if you need to rebuild the Flattened Device + Tree (FDT) source files (`.dts` files) provided with this software. + +* For debugging, ARM [Development Studio 5 (DS-5)][DS-5]. + + +4. Getting the Trusted Firmware source code +-------------------------------------------- + +Download the Trusted Firmware source code from Github: + + git clone https://github.com/ARM-software/arm-trusted-firmware.git + + +5. Building the Trusted Firmware +--------------------------------- + +* Before building Trusted Firmware, the environment variable `CROSS_COMPILE` + must point to the Linaro cross compiler. + + For AArch64: + + export CROSS_COMPILE=/bin/aarch64-linux-gnu- + + For AArch32: + + export CROSS_COMPILE=/bin/arm-linux-gnueabihf- + +* Change to the root directory of the Trusted Firmware source tree and build. + + For AArch64: + + make PLAT= all + + For AArch32: + + make PLAT= ARCH=aarch32 AARCH32_SP=sp_min all + + + Notes: + + * If `PLAT` is not specified, `fvp` is assumed by default. See the + "Summary of build options" for more information on available build + options. + + * (AArch32 only) Currently only `PLAT=fvp` is supported. + + * (AArch32 only) `AARCH32_SP` is the AArch32 EL3 Runtime Software and it + corresponds to the BL32 image. A minimal `AARCH32_SP`, sp_min, is + provided by ARM Trusted Firmware to demonstrate how PSCI Library can + be integrated with an AArch32 EL3 Runtime Software. Some AArch32 EL3 + Runtime Software may include other runtime services, for example + Trusted OS services. A guide to integrate PSCI library with AArch32 + EL3 Runtime Software can be found [here][PSCI Lib Integration]. + + * (AArch64 only) The TSP (Test Secure Payload), corresponding to the BL32 + image, is not compiled in by default. Refer to the "Building the Test + Secure Payload" section below. + + * By default this produces a release version of the build. To produce a + debug version instead, refer to the "Debugging options" section below. + + * The build process creates products in a `build` directory tree, building + the objects and binaries for each boot loader stage in separate + sub-directories. The following boot loader binary files are created + from the corresponding ELF files: + + * `build///bl1.bin` + * `build///bl2.bin` + * `build///bl31.bin` (AArch64 only) + * `build///bl32.bin` (mandatory for AArch32) + + where `` is the name of the chosen platform and `` + is either `debug` or `release`. The actual number of images might differ + depending on the platform. + +* Build products for a specific build variant can be removed using: + + make DEBUG= PLAT= clean + + ... where `` is `0` or `1`, as specified when building. + + The build tree can be removed completely using: + + make realclean + +### Summary of build options + +ARM Trusted Firmware build system supports the following build options. Unless +mentioned otherwise, these options are expected to be specified at the build +command line and are not to be modified in any component makefiles. Note that +the build system doesn't track dependency for build options. Therefore, if any +of the build options are changed from a previous build, a clean build must be +performed. + +#### Common build options + +* `SCP_BL2`: Path to SCP_BL2 image in the host file system. This image is optional. + If a SCP_BL2 image is present then this option must be passed for the `fip` + target. + +* `BL33`: Path to BL33 image in the host file system. This is mandatory for + `fip` target in case the BL2 from ARM Trusted Firmware is used. + +* `BL2`: This is an optional build option which specifies the path to BL2 + image for the `fip` target. In this case, the BL2 in the ARM Trusted + Firmware will not be built. + +* `BL31`: This is an optional build option which specifies the path to + BL31 image for the `fip` target. In this case, the BL31 in the ARM + Trusted Firmware will not be built. + +* `BL32`: This is an optional build option which specifies the path to + BL32 image for the `fip` target. In this case, the BL32 in the ARM + Trusted Firmware will not be built. + +* `FIP_NAME`: This is an optional build option which specifies the FIP + filename for the `fip` target. Default is `fip.bin`. + +* `FWU_FIP_NAME`: This is an optional build option which specifies the FWU + FIP filename for the `fwu_fip` target. Default is `fwu_fip.bin`. + +* `BL2U`: This is an optional build option which specifies the path to + BL2U image. In this case, the BL2U in the ARM Trusted Firmware will not + be built. + +* `SCP_BL2U`: Path to SCP_BL2U image in the host file system. This image is + optional. It is only needed if the platform makefile specifies that it + is required in order to build the `fwu_fip` target. + +* `NS_BL2U`: Path to NS_BL2U image in the host file system. This image is + optional. It is only needed if the platform makefile specifies that it + is required in order to build the `fwu_fip` target. + +* `DEBUG`: Chooses between a debug and release build. It can take either 0 + (release) or 1 (debug) as values. 0 is the default. + +* `LOG_LEVEL`: Chooses the log level, which controls the amount of console log + output compiled into the build. This should be one of the following: + + 0 (LOG_LEVEL_NONE) + 10 (LOG_LEVEL_NOTICE) + 20 (LOG_LEVEL_ERROR) + 30 (LOG_LEVEL_WARNING) + 40 (LOG_LEVEL_INFO) + 50 (LOG_LEVEL_VERBOSE) + + All log output up to and including the log level is compiled into the build. + The default value is 40 in debug builds and 20 in release builds. + +* `NS_TIMER_SWITCH`: Enable save and restore for non-secure timer register + contents upon world switch. It can take either 0 (don't save and restore) or + 1 (do save and restore). 0 is the default. An SPD may set this to 1 if it + wants the timer registers to be saved and restored. + +* `PLAT`: Choose a platform to build ARM Trusted Firmware for. The chosen + platform name must be subdirectory of any depth under `plat/`, and must + contain a platform makefile named `platform.mk`. + +* `ARCH` : Choose the target build architecture for ARM Trusted Firmware. + It can take either `aarch64` or `aarch32` as values. By default, it is + defined to `aarch64`. + +* `SPD`: Choose a Secure Payload Dispatcher component to be built into the + Trusted Firmware. This build option is only valid if `ARCH=aarch64`. The + value should be the path to the directory containing the SPD source, + relative to `services/spd/`; the directory is expected to + contain a makefile called `.mk`. + +* `AARCH32_SP` : Choose the AArch32 Secure Payload component to be built as + as the BL32 image when `ARCH=aarch32`. The value should be the path to the + directory containing the SP source, relative to the `bl32/`; the directory + is expected to contain a makefile called `.mk`. + +* `V`: Verbose build. If assigned anything other than 0, the build commands + are printed. Default is 0. + +* `ARM_GIC_ARCH`: Choice of ARM GIC architecture version used by the ARM + Legacy GIC driver for implementing the platform GIC API. This API is used + by the interrupt management framework. Default is 2 (that is, version 2.0). + This build option is deprecated. + +* `ARM_CCI_PRODUCT_ID`: Choice of ARM CCI product used by the platform. This + is used to determine the number of valid slave interfaces available in the + ARM CCI driver. Default is 400 (that is, CCI-400). + +* `RESET_TO_BL31`: Enable BL31 entrypoint as the CPU reset vector instead + of the BL1 entrypoint. It can take the value 0 (CPU reset to BL1 + entrypoint) or 1 (CPU reset to BL31 entrypoint). + The default value is 0. + +* `RESET_TO_SP_MIN`: SP_MIN is the minimal AArch32 Secure Payload provided in + ARM Trusted Firmware. This flag configures SP_MIN entrypoint as the CPU + reset vector instead of the BL1 entrypoint. It can take the value 0 (CPU + reset to BL1 entrypoint) or 1 (CPU reset to SP_MIN entrypoint). The default + value is 0. + +* `CRASH_REPORTING`: A non-zero value enables a console dump of processor + register state when an unexpected exception occurs during execution of + BL31. This option defaults to the value of `DEBUG` - i.e. by default + this is only enabled for a debug build of the firmware. + +* `ASM_ASSERTION`: This flag determines whether the assertion checks within + assembly source files are enabled or not. This option defaults to the + value of `DEBUG` - that is, by default this is only enabled for a debug + build of the firmware. + +* `TSP_INIT_ASYNC`: Choose BL32 initialization method as asynchronous or + synchronous, (see "Initializing a BL32 Image" section in [Firmware + Design]). It can take the value 0 (BL32 is initialized using + synchronous method) or 1 (BL32 is initialized using asynchronous method). + Default is 0. + +* `USE_COHERENT_MEM`: This flag determines whether to include the coherent + memory region in the BL memory map or not (see "Use of Coherent memory in + Trusted Firmware" section in [Firmware Design]). It can take the value 1 + (Coherent memory region is included) or 0 (Coherent memory region is + excluded). Default is 1. + +* `TSP_NS_INTR_ASYNC_PREEMPT`: A non zero value enables the interrupt + routing model which routes non-secure interrupts asynchronously from TSP + to EL3 causing immediate preemption of TSP. The EL3 is responsible + for saving and restoring the TSP context in this routing model. The + default routing model (when the value is 0) is to route non-secure + interrupts to TSP allowing it to save its context and hand over + synchronously to EL3 via an SMC. + +* `TRUSTED_BOARD_BOOT`: Boolean flag to include support for the Trusted Board + Boot feature. When set to '1', BL1 and BL2 images include support to load + and verify the certificates and images in a FIP, and BL1 includes support + for the Firmware Update. The default value is '0'. Generation and inclusion + of certificates in the FIP and FWU_FIP depends upon the value of the + `GENERATE_COT` option. + +* `GENERATE_COT`: Boolean flag used to build and execute the `cert_create` + tool to create certificates as per the Chain of Trust described in + [Trusted Board Boot]. The build system then calls `fiptool` to + include the certificates in the FIP and FWU_FIP. Default value is '0'. + + Specify both `TRUSTED_BOARD_BOOT=1` and `GENERATE_COT=1` to include support + for the Trusted Board Boot feature in the BL1 and BL2 images, to generate + the corresponding certificates, and to include those certificates in the + FIP and FWU_FIP. + + Note that if `TRUSTED_BOARD_BOOT=0` and `GENERATE_COT=1`, the BL1 and BL2 + images will not include support for Trusted Board Boot. The FIP will still + include the corresponding certificates. This FIP can be used to verify the + Chain of Trust on the host machine through other mechanisms. + + Note that if `TRUSTED_BOARD_BOOT=1` and `GENERATE_COT=0`, the BL1 and BL2 + images will include support for Trusted Board Boot, but the FIP and FWU_FIP + will not include the corresponding certificates, causing a boot failure. + +* `CREATE_KEYS`: This option is used when `GENERATE_COT=1`. It tells the + certificate generation tool to create new keys in case no valid keys are + present or specified. Allowed options are '0' or '1'. Default is '1'. + +* `SAVE_KEYS`: This option is used when `GENERATE_COT=1`. It tells the + certificate generation tool to save the keys used to establish the Chain of + Trust. Allowed options are '0' or '1'. Default is '0' (do not save). + + Note: This option depends on 'CREATE_KEYS' to be enabled. If the keys + already exist in disk, they will be overwritten without further notice. + +* `ROT_KEY`: This option is used when `GENERATE_COT=1`. It specifies the + file that contains the ROT private key in PEM format. If `SAVE_KEYS=1`, this + file name will be used to save the key. + +* `TRUSTED_WORLD_KEY`: This option is used when `GENERATE_COT=1`. It + specifies the file that contains the Trusted World private key in PEM + format. If `SAVE_KEYS=1`, this file name will be used to save the key. + +* `NON_TRUSTED_WORLD_KEY`: This option is used when `GENERATE_COT=1`. It + specifies the file that contains the Non-Trusted World private key in PEM + format. If `SAVE_KEYS=1`, this file name will be used to save the key. + +* `SCP_BL2_KEY`: This option is used when `GENERATE_COT=1`. It specifies the + file that contains the SCP_BL2 private key in PEM format. If `SAVE_KEYS=1`, + this file name will be used to save the key. + +* `BL31_KEY`: This option is used when `GENERATE_COT=1`. It specifies the + file that contains the BL31 private key in PEM format. If `SAVE_KEYS=1`, + this file name will be used to save the key. + +* `BL32_KEY`: This option is used when `GENERATE_COT=1`. It specifies the + file that contains the BL32 private key in PEM format. If `SAVE_KEYS=1`, + this file name will be used to save the key. + +* `BL33_KEY`: This option is used when `GENERATE_COT=1`. It specifies the + file that contains the BL33 private key in PEM format. If `SAVE_KEYS=1`, + this file name will be used to save the key. + +* `PROGRAMMABLE_RESET_ADDRESS`: This option indicates whether the reset + vector address can be programmed or is fixed on the platform. It can take + either 0 (fixed) or 1 (programmable). Default is 0. If the platform has a + programmable reset address, it is expected that a CPU will start executing + code directly at the right address, both on a cold and warm reset. In this + case, there is no need to identify the entrypoint on boot and the boot path + can be optimised. The `plat_get_my_entrypoint()` platform porting interface + does not need to be implemented in this case. + +* `COLD_BOOT_SINGLE_CPU`: This option indicates whether the platform may + release several CPUs out of reset. It can take either 0 (several CPUs may be + brought up) or 1 (only one CPU will ever be brought up during cold reset). + Default is 0. If the platform always brings up a single CPU, there is no + need to distinguish between primary and secondary CPUs and the boot path can + be optimised. The `plat_is_my_cpu_primary()` and + `plat_secondary_cold_boot_setup()` platform porting interfaces do not need + to be implemented in this case. + +* `PSCI_EXTENDED_STATE_ID`: As per PSCI1.0 Specification, there are 2 formats + possible for the PSCI power-state parameter viz original and extended + State-ID formats. This flag if set to 1, configures the generic PSCI layer + to use the extended format. The default value of this flag is 0, which + means by default the original power-state format is used by the PSCI + implementation. This flag should be specified by the platform makefile + and it governs the return value of PSCI_FEATURES API for CPU_SUSPEND + smc function id. + +* `ERROR_DEPRECATED`: This option decides whether to treat the usage of + deprecated platform APIs, helper functions or drivers within Trusted + Firmware as error. It can take the value 1 (flag the use of deprecated + APIs as error) or 0. The default is 0. + +* `SPIN_ON_BL1_EXIT`: This option introduces an infinite loop in BL1. It can + take either 0 (no loop) or 1 (add a loop). 0 is the default. This loop stops + execution in BL1 just before handing over to BL31. At this point, all + firmware images have been loaded in memory, and the MMU and caches are + turned off. Refer to the "Debugging options" section for more details. + +* `EL3_PAYLOAD_BASE`: This option enables booting an EL3 payload instead of + the normal boot flow. It must specify the entry point address of the EL3 + payload. Please refer to the "Booting an EL3 payload" section for more + details. + +* `PRELOADED_BL33_BASE`: This option enables booting a preloaded BL33 image + instead of the normal boot flow. When defined, it must specify the entry + point address for the preloaded BL33 image. This option is incompatible with + `EL3_PAYLOAD_BASE`. If both are defined, `EL3_PAYLOAD_BASE` has priority + over `PRELOADED_BL33_BASE`. + +* `PL011_GENERIC_UART`: Boolean option to indicate the PL011 driver that + the underlying hardware is not a full PL011 UART but a minimally compliant + generic UART, which is a subset of the PL011. The driver will not access + any register that is not part of the SBSA generic UART specification. + Default value is 0 (a full PL011 compliant UART is present). + +* `CTX_INCLUDE_AARCH32_REGS` : Boolean option that, when set to 1, will cause + the AArch32 system registers to be included when saving and restoring the + CPU context. The option must be set to 0 for AArch64-only platforms (that + is on hardware that does not implement AArch32, or at least not at EL1 and + higher ELs). Default value is 1. + +* `CTX_INCLUDE_FPREGS`: Boolean option that, when set to 1, will cause the FP + registers to be included when saving and restoring the CPU context. Default + is 0. + +* `DISABLE_PEDANTIC`: When set to 1 it will disable the -pedantic option in + the GCC command line. Default is 0. + +* `BUILD_STRING`: Input string for VERSION_STRING, which allows the TF build + to be uniquely identified. Defaults to the current git commit id. + +* `VERSION_STRING`: String used in the log output for each TF image. Defaults + to a string formed by concatenating the version number, build type and build + string. + +* `BUILD_MESSAGE_TIMESTAMP`: String used to identify the time and date of the + compilation of each build. It must be set to a C string (including quotes + where applicable). Defaults to a string that contains the time and date of + the compilation. + +* `HANDLE_EA_EL3_FIRST`: When defined External Aborts and SError Interrupts + will be always trapped in EL3 i.e. in BL31 at runtime. + +* `ENABLE_PMF`: Boolean option to enable support for optional Performance + Measurement Framework(PMF). Default is 0. + +* `ENABLE_PSCI_STAT`: Boolean option to enable support for optional PSCI + functions `PSCI_STAT_RESIDENCY` and `PSCI_STAT_COUNT`. Default is 0. + Enabling this option enables the `ENABLE_PMF` build option as well. + The PMF is used for collecting the statistics. + +* `SEPARATE_CODE_AND_RODATA`: Whether code and read-only data should be + isolated on separate memory pages. This is a trade-off between security and + memory usage. See "Isolating code and read-only data on separate memory + pages" section in [Firmware Design]. This flag is disabled by default and + affects all BL images. + +* `LOAD_IMAGE_V2`: Boolean option to enable support for new version (v2) of + image loading, which provides more flexibility and scalability around what + images are loaded and executed during boot. Default is 0. + Note: `TRUSTED_BOARD_BOOT` is currently not supported when `LOAD_IMAGE_V2` + is enabled. + +#### ARM development platform specific build options + +* `ARM_TSP_RAM_LOCATION`: location of the TSP binary. Options: + - `tsram` : Trusted SRAM (default option) + - `tdram` : Trusted DRAM (if available) + - `dram` : Secure region in DRAM (configured by the TrustZone controller) + +For a better understanding of these options, the ARM development platform memory +map is explained in the [Firmware Design]. + +* `ARM_ROTPK_LOCATION`: used when `TRUSTED_BOARD_BOOT=1`. It specifies the + location of the ROTPK hash returned by the function `plat_get_rotpk_info()` + for ARM platforms. Depending on the selected option, the proper private key + must be specified using the `ROT_KEY` option when building the Trusted + Firmware. This private key will be used by the certificate generation tool + to sign the BL2 and Trusted Key certificates. Available options for + `ARM_ROTPK_LOCATION` are: + + - `regs` : return the ROTPK hash stored in the Trusted root-key storage + registers. The private key corresponding to this ROTPK hash is not + currently available. + - `devel_rsa` : return a development public key hash embedded in the BL1 + and BL2 binaries. This hash has been obtained from the RSA public key + `arm_rotpk_rsa.der`, located in `plat/arm/board/common/rotpk`. To use + this option, `arm_rotprivk_rsa.pem` must be specified as `ROT_KEY` when + creating the certificates. + +* `ARM_RECOM_STATE_ID_ENC`: The PSCI1.0 specification recommends an encoding + for the construction of composite state-ID in the power-state parameter. + The existing PSCI clients currently do not support this encoding of + State-ID yet. Hence this flag is used to configure whether to use the + recommended State-ID encoding or not. The default value of this flag is 0, + in which case the platform is configured to expect NULL in the State-ID + field of power-state parameter. + +* `ARM_DISABLE_TRUSTED_WDOG`: boolean option to disable the Trusted Watchdog. + By default, ARM platforms use a watchdog to trigger a system reset in case + an error is encountered during the boot process (for example, when an image + could not be loaded or authenticated). The watchdog is enabled in the early + platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The + Trusted Watchdog may be disabled at build time for testing or development + purposes. + +* `ARM_CONFIG_CNTACR`: boolean option to unlock access to the CNTBase + frame registers by setting the CNTCTLBase.CNTACR register bits. The + frame number is defined by 'PLAT_ARM_NSTIMER_FRAME_ID', which should + match the frame used by the Non-Secure image (normally the Linux kernel). + Default is true (access to the frame is allowed). + +* `ARM_BOARD_OPTIMISE_MEM`: Boolean option to enable or disable optimisation + of the memory reserved for each image. This affects the maximum size of each + BL image as well as the number of allocated memory regions and translation + tables. By default this flag is 0, which means it uses the default + unoptimised values for these macros. ARM development platforms that wish to + optimise memory usage need to set this flag to 1 and must override the + related macros. + +* 'ARM_BL31_IN_DRAM': Boolean option to select loading of BL31 in TZC secured + DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load + BL31 in TZC secured DRAM. If TSP is present, then setting this option also + sets the TSP location to DRAM and ignores the `ARM_TSP_RAM_LOCATION` build + flag. + +#### ARM CSS platform specific build options + +* `CSS_DETECT_PRE_1_7_0_SCP`: Boolean flag to detect SCP version + incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards + compatible change to the MTL protocol, used for AP/SCP communication. + Trusted Firmware no longer supports earlier SCP versions. If this option is + set to 1 then Trusted Firmware will detect if an earlier version is in use. + Default is 1. + +* `CSS_LOAD_SCP_IMAGES`: Boolean flag, which when set, adds SCP_BL2 and + SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded + during boot. Default is 1. + +#### ARM FVP platform specific build options + +* `FVP_USE_GIC_DRIVER` : Selects the GIC driver to be built. Options: + - `FVP_GICV2` : The GICv2 only driver is selected + - `FVP_GICV3` : The GICv3 only driver is selected (default option) + - `FVP_GICV3_LEGACY`: The Legacy GICv3 driver is selected (deprecated) + Note: If Trusted Firmware is compiled with this option on FVPs with + GICv3 hardware, then it configures the hardware to run in GICv2 + emulation mode + +* `FVP_CLUSTER_COUNT` : Configures the cluster count to be used to + build the topology tree within Trusted Firmware. By default the + Trusted Firmware is configured for dual cluster topology and this option + can be used to override the default value. + +* `FVP_USE_SP804_TIMER` : Use the SP804 timer instead of the Generic Timer + for functions that wait for an arbitrary time length (udelay and mdelay). + The default value is 0. + +* `FVP_INTERCONNECT_DRIVER`: Selects the interconnect driver to be built. The + default interconnect driver depends on the value of `FVP_CLUSTER_COUNT` as + explained in the options below: + - `FVP_CCI` : The CCI driver is selected. This is the default + if 0 < `FVP_CLUSTER_COUNT` <= 2. + - `FVP_CCN` : The CCN driver is selected. This is the default + if `FVP_CLUSTER_COUNT` > 2. + +### Debugging options + +To compile a debug version and make the build more verbose use + + make PLAT= DEBUG=1 V=1 all + +AArch64 GCC uses DWARF version 4 debugging symbols by default. Some tools (for +example DS-5) might not support this and may need an older version of DWARF +symbols to be emitted by GCC. This can be achieved by using the +`-gdwarf-` flag, with the version being set to 2 or 3. Setting the +version to 2 is recommended for DS-5 versions older than 5.16. + +When debugging logic problems it might also be useful to disable all compiler +optimizations by using `-O0`. + +NOTE: Using `-O0` could cause output images to be larger and base addresses +might need to be recalculated (see the **Memory layout on ARM development +platforms** section in the [Firmware Design]). + +Extra debug options can be passed to the build system by setting `CFLAGS`: + + CFLAGS='-O0 -gdwarf-2' \ + make PLAT= DEBUG=1 V=1 all + +It is also possible to introduce an infinite loop to help in debugging the +post-BL2 phase of the Trusted Firmware. This can be done by rebuilding BL1 with +the `SPIN_ON_BL1_EXIT=1` build flag. Refer to the "Summary of build options" +section. In this case, the developer may take control of the target using a +debugger when indicated by the console output. When using DS-5, the following +commands can be used: + + # Stop target execution + interrupt + + # + # Prepare your debugging environment, e.g. set breakpoints + # + + # Jump over the debug loop + set var $AARCH64::$Core::$PC = $AARCH64::$Core::$PC + 4 + + # Resume execution + continue + + +### Building the Test Secure Payload + +The TSP is coupled with a companion runtime service in the BL31 firmware, +called the TSPD. Therefore, if you intend to use the TSP, the BL31 image +must be recompiled as well. For more information on SPs and SPDs, see the +"Secure-EL1 Payloads and Dispatchers" section in the [Firmware Design]. + +First clean the Trusted Firmware build directory to get rid of any previous +BL31 binary. Then to build the TSP image use: + + make PLAT= SPD=tspd all + +An additional boot loader binary file is created in the `build` directory: + + build///bl32.bin + +### Checking source code style + +When making changes to the source for submission to the project, the source +must be in compliance with the Linux style guide, and to assist with this check +the project Makefile contains two targets, which both utilise the +`checkpatch.pl` script that ships with the Linux source tree. + +To check the entire source tree, you must first download a copy of +`checkpatch.pl` (or the full Linux source), set the `CHECKPATCH` environment +variable to point to the script and build the target checkcodebase: + + make CHECKPATCH=/linux/scripts/checkpatch.pl checkcodebase + +To just check the style on the files that differ between your local branch and +the remote master, use: + + make CHECKPATCH=/linux/scripts/checkpatch.pl checkpatch + +If you wish to check your patch against something other than the remote master, +set the `BASE_COMMIT` variable to your desired branch. By default, `BASE_COMMIT` +is set to `origin/master`. + + +### Building and using the FIP tool + +Firmware Image Package (FIP) is a packaging format used by the Trusted Firmware +project to package firmware images in a single binary. The number and type of +images that should be packed in a FIP is platform specific and may include TF +images and other firmware images required by the platform. For example, most +platforms require a BL33 image which corresponds to the normal world bootloader +(e.g. UEFI or U-Boot). + +The TF build system provides the make target `fip` to create a FIP file for the +specified platform using the FIP creation tool included in the TF project. +Examples below show how to build a FIP file for FVP, packaging TF images and a +BL33 image. + +For AArch64: + + make PLAT=fvp BL33= fip + +For AArch32: + + make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33= fip + +Note that AArch32 support for Normal world boot loader (BL33), like U-boot or +UEFI, on FVP is not available upstream. Hence custom solutions are required to +allow Linux boot on FVP. These instructions assume such a custom boot loader +(BL33) is available. + +The resulting FIP may be found in: + + build/fvp//fip.bin + +For advanced operations on FIP files, it is also possible to independently build +the tool and create or modify FIPs using this tool. To do this, follow these +steps: + +It is recommended to remove old artifacts before building the tool: + + make -C tools/fiptool clean + +Build the tool: + + make [DEBUG=1] [V=1] fiptool + +The tool binary can be located in: + + ./tools/fiptool/fiptool + +Invoking the tool with `--help` will print a help message with all available +options. + +Example 1: create a new Firmware package `fip.bin` that contains BL2 and BL31: + + ./tools/fiptool/fiptool create \ + --tb-fw build///bl2.bin \ + --soc-fw build///bl31.bin \ + fip.bin + +Example 2: view the contents of an existing Firmware package: + + ./tools/fiptool/fiptool info /fip.bin + +Example 3: update the entries of an existing Firmware package: + + # Change the BL2 from Debug to Release version + ./tools/fiptool/fiptool update \ + --tb-fw build//release/bl2.bin \ + build//debug/fip.bin + +Example 4: unpack all entries from an existing Firmware package: + + # Images will be unpacked to the working directory + ./tools/fiptool/fiptool unpack /fip.bin + +Example 5: remove an entry from an existing Firmware package: + + ./tools/fiptool/fiptool remove \ + --tb-fw build//debug/fip.bin + +Note that if the destination FIP file exists, the create, update and +remove operations will automatically overwrite it. + +The unpack operation will fail if the images already exist at the +destination. In that case, use -f or --force to continue. + +More information about FIP can be found in the [Firmware Design document] +[Firmware Design]. + +#### Migrating from fip_create to fiptool + +The previous version of fiptool was called fip_create. A compatibility script +that emulates the basic functionality of the previous fip_create is provided. +However, users are strongly encouraged to migrate to fiptool. + +* To create a new FIP file, replace "fip_create" with "fiptool create". +* To update a FIP file, replace "fip_create" with "fiptool update". +* To dump the contents of a FIP file, replace "fip_create --dump" + with "fiptool info". + +### Building FIP images with support for Trusted Board Boot + +Trusted Board Boot primarily consists of the following two features: + +* Image Authentication, described in [Trusted Board Boot], and +* Firmware Update, described in [Firmware Update] + +The following steps should be followed to build FIP and (optionally) FWU_FIP +images with support for these features: + +1. Fulfill the dependencies of the `mbedtls` cryptographic and image parser + modules by checking out a recent version of the [mbed TLS Repository]. It + is important to use a version that is compatible with TF and fixes any + known security vulnerabilities. See [mbed TLS Security Center] for more + information. This version of TF is tested with tag `mbedtls-2.2.1`. + + The `drivers/auth/mbedtls/mbedtls_*.mk` files contain the list of mbed TLS + source files the modules depend upon. + `include/drivers/auth/mbedtls/mbedtls_config.h` contains the configuration + options required to build the mbed TLS sources. + + Note that the mbed TLS library is licensed under the Apache version 2.0 + license. Using mbed TLS source code will affect the licensing of + Trusted Firmware binaries that are built using this library. + +2. To build the FIP image, ensure the following command line variables are set + while invoking `make` to build Trusted Firmware: + + * `MBEDTLS_DIR=` + * `TRUSTED_BOARD_BOOT=1` + * `GENERATE_COT=1` + + In the case of ARM platforms, the location of the ROTPK hash must also be + specified at build time. Two locations are currently supported (see + `ARM_ROTPK_LOCATION` build option): + + * `ARM_ROTPK_LOCATION=regs`: the ROTPK hash is obtained from the Trusted + root-key storage registers present in the platform. On Juno, this + registers are read-only. On FVP Base and Cortex models, the registers + are read-only, but the value can be specified using the command line + option `bp.trusted_key_storage.public_key` when launching the model. + On both Juno and FVP models, the default value corresponds to an + ECDSA-SECP256R1 public key hash, whose private part is not currently + available. + + * `ARM_ROTPK_LOCATION=devel_rsa`: use the ROTPK hash that is hardcoded + in the ARM platform port. The private/public RSA key pair may be + found in `plat/arm/board/common/rotpk`. + + Example of command line using RSA development keys: + + MBEDTLS_DIR= \ + make PLAT= TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \ + ARM_ROTPK_LOCATION=devel_rsa \ + ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ + BL33=/ \ + all fip + + The result of this build will be the bl1.bin and the fip.bin binaries. This + FIP will include the certificates corresponding to the Chain of Trust + described in the TBBR-client document. These certificates can also be found + in the output build directory. + +3. The optional FWU_FIP contains any additional images to be loaded from + Non-Volatile storage during the [Firmware Update] process. To build the + FWU_FIP, any FWU images required by the platform must be specified on the + command line. On ARM development platforms like Juno, these are: + + * NS_BL2U. The AP non-secure Firmware Updater image. + * SCP_BL2U. The SCP Firmware Update Configuration image. + + Example of Juno command line for generating both `fwu` and `fwu_fip` + targets using RSA development: + + MBEDTLS_DIR= \ + make PLAT=juno TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 \ + ARM_ROTPK_LOCATION=devel_rsa \ + ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \ + BL33=/ \ + SCP_BL2=/ \ + SCP_BL2U=/ \ + NS_BL2U=/ \ + all fip fwu_fip + + Note: The BL2U image will be built by default and added to the FWU_FIP. + The user may override this by adding `BL2U=/` + to the command line above. + + Note: Building and installing the non-secure and SCP FWU images (NS_BL1U, + NS_BL2U and SCP_BL2U) is outside the scope of this document. + + The result of this build will be bl1.bin, fip.bin and fwu_fip.bin binaries. + Both the FIP and FWU_FIP will include the certificates corresponding to the + Chain of Trust described in the TBBR-client document. These certificates + can also be found in the output build directory. + + +### Building the Certificate Generation Tool + +The `cert_create` tool is built as part of the TF build process when the `fip` +make target is specified and TBB is enabled (as described in the previous +section), but it can also be built separately with the following command: + + make PLAT= [DEBUG=1] [V=1] certtool + +Specifying the platform is mandatory since the tool is platform specific. +`DEBUG=1` builds the tool in debug mode. `V=1` makes the build process more +verbose. The following command should be used to obtain help about the tool: + + ./tools/cert_create/cert_create -h + + +6. Building a FIP for Juno and FVP +----------------------------------- + +This section provides Juno and FVP specific instructions to build Trusted +Firmware, obtain the additional required firmware, and pack it all together in +a single FIP binary. It assumes that a [Linaro Release][Linaro Release Notes] +has been installed. + +Note currently [Linaro Release][Linaro Release Notes] only includes pre-built +binaries for AArch64. For AArch32, pre-built binaries are not available. + +Note: follow the full instructions for one platform before switching to a +different one. Mixing instructions for different platforms may result in +corrupted binaries. + +1. Clean the working directory + + make realclean + +2. Obtain SCP_BL2 (Juno) and BL33 (all platforms) + + Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP + package included in the Linaro release: + + # Build the fiptool + make [DEBUG=1] [V=1] fiptool + + # Unpack firmware images from Linaro FIP + ./tools/fiptool/fiptool unpack \ + /fip.bin + + The unpack operation will result in a set of binary images extracted to the + working directory. The SCP_BL2 image corresponds to `scp-fw.bin` and BL33 + corresponds to `nt-fw.bin`. + + Note: the fiptool will complain if the images to be unpacked already + exist in the current directory. If that is the case, either delete those + files or use the `--force` option to overwrite. + + Note for AArch32, the instructions below assume that nt-fw.bin is a custom + Normal world boot loader that supports AArch32. + +3. Build TF images and create a new FIP + + # Juno + make PLAT=juno SCP_BL2=scp-fw.bin BL33=nt-fw.bin all fip + + # FVP AArch64 + make PLAT=fvp BL33=nt-fw.bin all fip + + # FVP AArch32 + make PLAT=fvp ARCH=aarch32 AARCH32_SP=sp_min BL33=nt-fw.bin all fip + +The resulting BL1 and FIP images may be found in: + + # Juno + ./build/juno/release/bl1.bin + ./build/juno/release/fip.bin + + # FVP + ./build/fvp/release/bl1.bin + ./build/fvp/release/fip.bin + + +7. EL3 payloads alternative boot flow +-------------------------------------- + +On a pre-production system, the ability to execute arbitrary, bare-metal code at +the highest exception level is required. It allows full, direct access to the +hardware, for example to run silicon soak tests. + +Although it is possible to implement some baremetal secure firmware from +scratch, this is a complex task on some platforms, depending on the level of +configuration required to put the system in the expected state. + +Rather than booting a baremetal application, a possible compromise is to boot +`EL3 payloads` through the Trusted Firmware instead. This is implemented as an +alternative boot flow, where a modified BL2 boots an EL3 payload, instead of +loading the other BL images and passing control to BL31. It reduces the +complexity of developing EL3 baremetal code by: + +* putting the system into a known architectural state; +* taking care of platform secure world initialization; +* loading the SCP_BL2 image if required by the platform. + +When booting an EL3 payload on ARM standard platforms, the configuration of the +TrustZone controller is simplified such that only region 0 is enabled and is +configured to permit secure access only. This gives full access to the whole +DRAM to the EL3 payload. + +The system is left in the same state as when entering BL31 in the default boot +flow. In particular: + +* Running in EL3; +* Current state is AArch64; +* Little-endian data access; +* All exceptions disabled; +* MMU disabled; +* Caches disabled. + +### Booting an EL3 payload + +The EL3 payload image is a standalone image and is not part of the FIP. It is +not loaded by the Trusted Firmware. Therefore, there are 2 possible scenarios: + +* The EL3 payload may reside in non-volatile memory (NVM) and execute in + place. In this case, booting it is just a matter of specifying the right + address in NVM through `EL3_PAYLOAD_BASE` when building the TF. + +* The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at + run-time. + +To help in the latter scenario, the `SPIN_ON_BL1_EXIT=1` build option can be +used. The infinite loop that it introduces in BL1 stops execution at the right +moment for a debugger to take control of the target and load the payload (for +example, over JTAG). + +It is expected that this loading method will work in most cases, as a debugger +connection is usually available in a pre-production system. The user is free to +use any other platform-specific mechanism to load the EL3 payload, though. + +#### Booting an EL3 payload on FVP + +The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for +the secondary CPUs holding pen to work properly. Unfortunately, its reset value +is undefined on the FVP platform and the FVP platform code doesn't clear it. +Therefore, one must modify the way the model is normally invoked in order to +clear the mailbox at start-up. + +One way to do that is to create an 8-byte file containing all zero bytes using +the following command: + + dd if=/dev/zero of=mailbox.dat bs=1 count=8 + +and pre-load it into the FVP memory at the mailbox address (i.e. `0x04000000`) +using the following model parameters: + + --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs] + --data=mailbox.dat@0x04000000 [Foundation FVP] + +To provide the model with the EL3 payload image, the following methods may be +used: + +1. If the EL3 payload is able to execute in place, it may be programmed into + flash memory. On Base Cortex and AEM FVPs, the following model parameter + loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already + used for the FIP): + + -C bp.flashloader1.fname="/path/to/el3-payload" + + On Foundation FVP, there is no flash loader component and the EL3 payload + may be programmed anywhere in flash using method 3 below. + +2. When using the `SPIN_ON_BL1_EXIT=1` loading method, the following DS-5 + command may be used to load the EL3 payload ELF image over JTAG: + + load /path/to/el3-payload.elf + +3. The EL3 payload may be pre-loaded in volatile memory using the following + model parameters: + + --data cluster0.cpu0="/path/to/el3-payload"@address [Base FVPs] + --data="/path/to/el3-payload"@address [Foundation FVP] + + The address provided to the FVP must match the `EL3_PAYLOAD_BASE` address + used when building the Trusted Firmware. + +#### Booting an EL3 payload on Juno + +If the EL3 payload is able to execute in place, it may be programmed in flash +memory by adding an entry in the `SITE1/HBI0262x/images.txt` configuration file +on the Juno SD card (where `x` depends on the revision of the Juno board). +Refer to the [Juno Getting Started Guide], section 2.3 "Flash memory +programming" for more information. + +Alternatively, the same DS-5 command mentioned in the FVP section above can +be used to load the EL3 payload's ELF file over JTAG on Juno. + + +8. Preloaded BL33 alternative boot flow +---------------------------------------- + +Some platforms have the ability to preload BL33 into memory instead of relying +on Trusted Firmware to load it. This may simplify packaging of the normal world +code and improve performance in a development environment. When secure world +cold boot is complete, Trusted Firmware simply jumps to a BL33 base address +provided at build time. + +For this option to be used, the `PRELOADED_BL33_BASE` build option has to be +used when compiling the Trusted Firmware. For example, the following command +will create a FIP without a BL33 and prepare to jump to a BL33 image loaded at +address 0x80000000: + + make PRELOADED_BL33_BASE=0x80000000 PLAT=fvp all fip + +#### Boot of a preloaded bootwrapped kernel image on Base FVP + +The following example uses the AArch64 boot wrapper. This simplifies normal +world booting while also making use of TF features. It can be obtained from its +repository with: + + git clone git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git + +After compiling it, an ELF file is generated. It can be loaded with the +following command: + + /FVP_Base_AEMv8A-AEMv8A \ + -C bp.secureflashloader.fname=bl1.bin \ + -C bp.flashloader0.fname=fip.bin \ + -a cluster0.cpu0= \ + --start cluster0.cpu0=0x0 + +The `-a cluster0.cpu0=` option loads the ELF file. It +also sets the PC register to the ELF entry point address, which is not the +desired behaviour, so the `--start cluster0.cpu0=0x0` option forces the PC back +to 0x0 (the BL1 entry point address) on CPU #0. The `PRELOADED_BL33_BASE` define +used when compiling the FIP must match the ELF entry point. + +#### Boot of a preloaded bootwrapped kernel image on Juno + +The procedure to obtain and compile the boot wrapper is very similar to the case +of the FVP. The execution must be stopped at the end of bl2_main(), and the +loading method explained above in the EL3 payload boot flow section may be used +to load the ELF file over JTAG on Juno. + + +9. Running the software on FVP +------------------------------- + +The AArch64 build of this version of ARM Trusted Firmware has been tested on +the following ARM FVPs (64-bit host machine only). + +* `Foundation_Platform` (Version 10.1, Build 10.1.32) +* `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701) +* `FVP_Base_Cortex-A57x4-A53x4` (Version 7.7, Build 0.8.7701) +* `FVP_Base_Cortex-A57x1-A53x1` (Version 7.7, Build 0.8.7701) +* `FVP_Base_Cortex-A57x2-A53x4` (Version 7.7, Build 0.8.7701) + +The AArch32 build of this version of ARM Trusted Firmware has been tested on +the following ARM FVPs (64-bit host machine only). + +* `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701) +* `FVP_Base_Cortex-A32x4` (Version 10.1, Build 10.1.32) + +NOTE: The build numbers quoted above are those reported by launching the FVP +with the `--version` parameter. + +NOTE: The software will not work on Version 1.0 of the Foundation FVP. +The commands below would report an `unhandled argument` error in this case. + +NOTE: The Foundation FVP does not provide a debugger interface. + +The Foundation FVP is a cut down version of the AArch64 Base FVP. It can be +downloaded for free from [ARM's website][ARM FVP website]. + +Please refer to the FVP documentation for a detailed description of the model +parameter options. A brief description of the important ones that affect the ARM +Trusted Firmware and normal world software behavior is provided below. + +### Obtaining the Flattened Device Trees + +Depending on the FVP configuration and Linux configuration used, different +FDT files are required. FDTs for the Foundation and Base FVPs can be found in +the Trusted Firmware source directory under `fdts/`. The Foundation FVP has a +subset of the Base FVP components. For example, the Foundation FVP lacks CLCD +and MMC support, and has only one CPU cluster. + +Note: It is not recommended to use the FDTs built along the kernel because not +all FDTs are available from there. + +* `fvp-base-gicv2-psci.dtb` + + For use with both AEMv8 and Cortex-A57-A53 Base FVPs with + Base memory map configuration. + +* `fvp-base-gicv2-psci-aarch32.dtb` + + For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state + with Base memory map configuration. + +* `fvp-base-gicv3-psci.dtb` + + (Default) For use with both AEMv8 and Cortex-A57-A53 Base FVPs with Base + memory map configuration and Linux GICv3 support. + +* `fvp-base-gicv3-psci-aarch32.dtb` + + For use with AEMv8 and Cortex-A32 Base FVPs running Linux in AArch32 state + with Base memory map configuration and Linux GICv3 support. + +* `fvp-foundation-gicv2-psci.dtb` + + For use with Foundation FVP with Base memory map configuration. + +* `fvp-foundation-gicv3-psci.dtb` + + (Default) For use with Foundation FVP with Base memory map configuration + and Linux GICv3 support. + +### Running on the Foundation FVP with reset to BL1 entrypoint + +The following `Foundation_Platform` parameters should be used to boot Linux with +4 CPUs using the AArch64 build of ARM Trusted Firmware. + + /Foundation_Platform \ + --cores=4 \ + --secure-memory \ + --visualization \ + --gicv3 \ + --data="/"@0x0 \ + --data="/"@0x08000000 \ + --data="/"@0x83000000 \ + --data="/"@0x80080000 \ + --block-device="/" + +Notes: +* BL1 is loaded at the start of the Trusted ROM. +* The Firmware Image Package is loaded at the start of NOR FLASH0. +* The Linux kernel image and device tree are loaded in DRAM. +* The default use-case for the Foundation FVP is to use the `--gicv3` option + and enable the GICv3 device in the model. Note that without this option, + the Foundation FVP defaults to legacy (Versatile Express) memory map which + is not supported by ARM Trusted Firmware. + +### Running on the AEMv8 Base FVP with reset to BL1 entrypoint + +The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux +with 8 CPUs using the AArch64 build of ARM Trusted Firmware. + + /FVP_Base_AEMv8A-AEMv8A \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cluster0.NUM_CORES=4 \ + -C cluster1.NUM_CORES=4 \ + -C cache_state_modelled=1 \ + -C bp.secureflashloader.fname="/" \ + -C bp.flashloader0.fname="/" \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + +### Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint + +The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux +with 8 CPUs using the AArch32 build of ARM Trusted Firmware. + + /FVP_Base_AEMv8A-AEMv8A \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cluster0.NUM_CORES=4 \ + -C cluster1.NUM_CORES=4 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.CONFIG64=0 \ + -C cluster0.cpu1.CONFIG64=0 \ + -C cluster0.cpu2.CONFIG64=0 \ + -C cluster0.cpu3.CONFIG64=0 \ + -C cluster1.cpu0.CONFIG64=0 \ + -C cluster1.cpu1.CONFIG64=0 \ + -C cluster1.cpu2.CONFIG64=0 \ + -C cluster1.cpu3.CONFIG64=0 \ + -C bp.secureflashloader.fname="/" \ + -C bp.flashloader0.fname="/" \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + +### Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint + +The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to +boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware. + + /FVP_Base_Cortex-A57x4-A53x4 \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cache_state_modelled=1 \ + -C bp.secureflashloader.fname="/" \ + -C bp.flashloader0.fname="/" \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + +### Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint + +The following `FVP_Base_Cortex-A32x4` model parameters should be used to +boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware. + + /FVP_Base_Cortex-A32x4 \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cache_state_modelled=1 \ + -C bp.secureflashloader.fname="/" \ + -C bp.flashloader0.fname="/" \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + +### Running on the AEMv8 Base FVP with reset to BL31 entrypoint + +The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux +with 8 CPUs using the AArch64 build of ARM Trusted Firmware. + + /FVP_Base_AEMv8A-AEMv8A \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cluster0.NUM_CORES=4 \ + -C cluster1.NUM_CORES=4 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.RVBAR=0x04023000 \ + -C cluster0.cpu1.RVBAR=0x04023000 \ + -C cluster0.cpu2.RVBAR=0x04023000 \ + -C cluster0.cpu3.RVBAR=0x04023000 \ + -C cluster1.cpu0.RVBAR=0x04023000 \ + -C cluster1.cpu1.RVBAR=0x04023000 \ + -C cluster1.cpu2.RVBAR=0x04023000 \ + -C cluster1.cpu3.RVBAR=0x04023000 \ + --data cluster0.cpu0="/"@0x04023000 \ + --data cluster0.cpu0="/"@0x04001000 \ + --data cluster0.cpu0="/"@0x88000000 \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + +Notes: + +* Since a FIP is not loaded when using BL31 as reset entrypoint, the + `--data=""@` + parameter is needed to load the individual bootloader images in memory. + BL32 image is only needed if BL31 has been built to expect a Secure-EL1 + Payload. + +* The `-C cluster.cpu.RVBAR=@` parameter, where + X and Y are the cluster and CPU numbers respectively, is used to set the + reset vector for each core. + +* Changing the default value of `ARM_TSP_RAM_LOCATION` will also require + changing the value of + `--data=""@` to the new value of + `BL32_BASE`. + +### Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint + +The following `FVP_Base_AEMv8A-AEMv8A` parameters should be used to boot Linux +with 8 CPUs using the AArch32 build of ARM Trusted Firmware. + + /FVP_Base_AEMv8A-AEMv8A \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cluster0.NUM_CORES=4 \ + -C cluster1.NUM_CORES=4 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.CONFIG64=0 \ + -C cluster0.cpu1.CONFIG64=0 \ + -C cluster0.cpu2.CONFIG64=0 \ + -C cluster0.cpu3.CONFIG64=0 \ + -C cluster1.cpu0.CONFIG64=0 \ + -C cluster1.cpu1.CONFIG64=0 \ + -C cluster1.cpu2.CONFIG64=0 \ + -C cluster1.cpu3.CONFIG64=0 \ + -C cluster0.cpu0.RVBAR=0x04001000 \ + -C cluster0.cpu1.RVBAR=0x04001000 \ + -C cluster0.cpu2.RVBAR=0x04001000 \ + -C cluster0.cpu3.RVBAR=0x04001000 \ + -C cluster1.cpu0.RVBAR=0x04001000 \ + -C cluster1.cpu1.RVBAR=0x04001000 \ + -C cluster1.cpu2.RVBAR=0x04001000 \ + -C cluster1.cpu3.RVBAR=0x04001000 \ + --data cluster0.cpu0="/"@0x04001000 \ + --data cluster0.cpu0="/"@0x88000000 \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + +Note: The load address of `` depends on the value `BL32_BASE`. +It should match the address programmed into the RVBAR register as well. + +### Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint + +The following `FVP_Base_Cortex-A57x4-A53x4` model parameters should be used to +boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware. + + /FVP_Base_Cortex-A57x4-A53x4 \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.RVBARADDR=0x04023000 \ + -C cluster0.cpu1.RVBARADDR=0x04023000 \ + -C cluster0.cpu2.RVBARADDR=0x04023000 \ + -C cluster0.cpu3.RVBARADDR=0x04023000 \ + -C cluster1.cpu0.RVBARADDR=0x04023000 \ + -C cluster1.cpu1.RVBARADDR=0x04023000 \ + -C cluster1.cpu2.RVBARADDR=0x04023000 \ + -C cluster1.cpu3.RVBARADDR=0x04023000 \ + --data cluster0.cpu0="/"@0x04023000 \ + --data cluster0.cpu0="/"@0x04001000 \ + --data cluster0.cpu0="/"@0x88000000 \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + +### Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint + +The following `FVP_Base_Cortex-A32x4` model parameters should be used to +boot Linux with 4 CPUs using the AArch32 build of ARM Trusted Firmware. + + /FVP_Base_Cortex-A32x4 \ + -C pctl.startup=0.0.0.0 \ + -C bp.secure_memory=1 \ + -C bp.tzc_400.diagnostics=1 \ + -C cache_state_modelled=1 \ + -C cluster0.cpu0.RVBARADDR=0x04001000 \ + -C cluster0.cpu1.RVBARADDR=0x04001000 \ + -C cluster0.cpu2.RVBARADDR=0x04001000 \ + -C cluster0.cpu3.RVBARADDR=0x04001000 \ + --data cluster0.cpu0="/"@0x04001000 \ + --data cluster0.cpu0="/"@0x88000000 \ + --data cluster0.cpu0="/"@0x83000000 \ + --data cluster0.cpu0="/"@0x80080000 \ + -C bp.virtioblockdevice.image_path="/" + +10. Running the software on Juno +--------------------------------- + +This version of the ARM Trusted Firmware has been tested on Juno r0 and Juno r1. + +To execute the software stack on Juno, the version of the Juno board recovery +image indicated in the [Linaro Release Notes] must be installed. If you have an +earlier version installed or are unsure which version is installed, please +re-install the recovery image by following the [Instructions for using Linaro's +deliverables on Juno][Juno Instructions]. + +### Preparing Trusted Firmware images + +After building Trusted Firmware, the files `bl1.bin` and `fip.bin` need copying +to the `SOFTWARE/` directory of the Juno SD card. + +### Other Juno software information + +Please visit the [ARM Platforms Portal] to get support and obtain any other Juno +software information. Please also refer to the [Juno Getting Started Guide] to +get more detailed information about the Juno ARM development platform and how to +configure it. + +### Testing SYSTEM SUSPEND on Juno + +The SYSTEM SUSPEND is a PSCI API which can be used to implement system suspend +to RAM. For more details refer to section 5.16 of [PSCI]. To test system suspend +on Juno, at the linux shell prompt, issue the following command: + + echo +10 > /sys/class/rtc/rtc0/wakealarm + echo -n mem > /sys/power/state + +The Juno board should suspend to RAM and then wakeup after 10 seconds due to +wakeup interrupt from RTC. + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._ + + +[Firmware Design]: firmware-design.md +[ARM FVP website]: http://www.arm.com/fvp +[Linaro Release Notes]: https://community.arm.com/docs/DOC-10952#jive_content_id_Linaro_Release_1606 +[ARM Platforms Portal]: https://community.arm.com/groups/arm-development-platforms +[Linaro SW Instructions]: https://community.arm.com/docs/DOC-10803 +[Juno Instructions]: https://community.arm.com/docs/DOC-10804 +[FVP Instructions]: https://community.arm.com/docs/DOC-10831 +[Juno Getting Started Guide]: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf +[DS-5]: http://www.arm.com/products/tools/software-tools/ds-5/index.php +[mbed TLS Repository]: https://github.com/ARMmbed/mbedtls.git +[mbed TLS Security Center]: https://tls.mbed.org/security +[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)" +[Trusted Board Boot]: trusted-board-boot.md +[Firmware Update]: ./firmware-update.md +[PSCI Lib Integration]: ./psci-lib-integration-guide.md diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/cci/cci.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/cci/cci.c new file mode 100644 index 0000000..2e773a9 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/cci/cci.c @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +static uintptr_t g_cci_base; +static unsigned int g_max_master_id; +static const int *g_cci_slave_if_map; + +#if DEBUG +static int validate_cci_map(const int *map) +{ + unsigned int valid_cci_map = 0; + int slave_if_id; + int i; + + /* Validate the map */ + for (i = 0; i <= g_max_master_id; i++) { + slave_if_id = map[i]; + + if (slave_if_id < 0) + continue; + + if (slave_if_id >= CCI_SLAVE_INTERFACE_COUNT) { + tf_printf("Slave interface ID is invalid\n"); + return 0; + } + + if (valid_cci_map & (1 << slave_if_id)) { + tf_printf("Multiple masters are assigned same" + " slave interface ID\n"); + return 0; + } + valid_cci_map |= 1 << slave_if_id; + } + + if (!valid_cci_map) { + tf_printf("No master is assigned a valid slave interface\n"); + return 0; + } + + return 1; +} +#endif /* DEBUG */ + +void cci_init(uintptr_t cci_base, + const int *map, + unsigned int num_cci_masters) +{ + assert(map); + assert(cci_base); + + g_cci_base = cci_base; + + /* + * Master Id's are assigned from zero, So in an array of size n + * the max master id is (n - 1). + */ + g_max_master_id = num_cci_masters - 1; + + assert(validate_cci_map(map)); + g_cci_slave_if_map = map; +} + +void cci_enable_snoop_dvm_reqs(unsigned int master_id) +{ + int slave_if_id; + + assert(g_cci_base); + assert(master_id <= g_max_master_id); + + slave_if_id = g_cci_slave_if_map[master_id]; + assert((slave_if_id < CCI_SLAVE_INTERFACE_COUNT) && (slave_if_id >= 0)); + + /* + * Enable Snoops and DVM messages, no need for Read/Modify/Write as + * rest of bits are write ignore + */ + mmio_write_32(g_cci_base + + SLAVE_IFACE_OFFSET(slave_if_id) + + SNOOP_CTRL_REG, DVM_EN_BIT | SNOOP_EN_BIT); + + /* Wait for the dust to settle down */ + while (mmio_read_32(g_cci_base + STATUS_REG) & CHANGE_PENDING_BIT) + ; +} + +void cci_disable_snoop_dvm_reqs(unsigned int master_id) +{ + int slave_if_id; + + assert(g_cci_base); + assert(master_id <= g_max_master_id); + + slave_if_id = g_cci_slave_if_map[master_id]; + assert((slave_if_id < CCI_SLAVE_INTERFACE_COUNT) && (slave_if_id >= 0)); + + /* + * Disable Snoops and DVM messages, no need for Read/Modify/Write as + * rest of bits are write ignore. + */ + mmio_write_32(g_cci_base + + SLAVE_IFACE_OFFSET(slave_if_id) + + SNOOP_CTRL_REG, ~(DVM_EN_BIT | SNOOP_EN_BIT)); + + /* Wait for the dust to settle down */ + while (mmio_read_32(g_cci_base + STATUS_REG) & CHANGE_PENDING_BIT) + ; +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/cci400/cci400.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/cci400/cci400.c new file mode 100644 index 0000000..4b1181b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/cci400/cci400.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#define MAX_CLUSTERS 2 + +static uintptr_t cci_base_addr; +static unsigned int cci_cluster_ix_to_iface[MAX_CLUSTERS]; + + +void cci_init(uintptr_t cci_base, + int slave_iface3_cluster_ix, + int slave_iface4_cluster_ix) +{ + /* + * Check the passed arguments are valid. The cluster indices must be + * less than MAX_CLUSTERS, not the same as each other and at least one + * of them must refer to a valid cluster index. + */ + assert(cci_base); + assert(slave_iface3_cluster_ix < MAX_CLUSTERS); + assert(slave_iface4_cluster_ix < MAX_CLUSTERS); + assert(slave_iface3_cluster_ix != slave_iface4_cluster_ix); + assert((slave_iface3_cluster_ix >= 0) || + (slave_iface4_cluster_ix >= 0)); + + WARN("Please migrate to common cci driver, This driver will be" \ + " deprecated in future\n"); + + cci_base_addr = cci_base; + if (slave_iface3_cluster_ix >= 0) + cci_cluster_ix_to_iface[slave_iface3_cluster_ix] = + SLAVE_IFACE3_OFFSET; + if (slave_iface4_cluster_ix >= 0) + cci_cluster_ix_to_iface[slave_iface4_cluster_ix] = + SLAVE_IFACE4_OFFSET; +} + +static inline unsigned long get_slave_iface_base(unsigned long mpidr) +{ + /* + * We assume the TF topology code allocates affinity instances + * consecutively from zero. + * It is a programming error if this is called without initializing + * the slave interface to use for this cluster. + */ + unsigned int cluster_id = + (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + + assert(cluster_id < MAX_CLUSTERS); + assert(cci_cluster_ix_to_iface[cluster_id] != 0); + + return cci_base_addr + cci_cluster_ix_to_iface[cluster_id]; +} + +void cci_enable_cluster_coherency(unsigned long mpidr) +{ + assert(cci_base_addr); + /* Enable Snoops and DVM messages */ + mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG, + DVM_EN_BIT | SNOOP_EN_BIT); + + /* Wait for the dust to settle down */ + while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT) + ; +} + +void cci_disable_cluster_coherency(unsigned long mpidr) +{ + assert(cci_base_addr); + /* Disable Snoops and DVM messages */ + mmio_write_32(get_slave_iface_base(mpidr) + SNOOP_CTRL_REG, + ~(DVM_EN_BIT | SNOOP_EN_BIT)); + + /* Wait for the dust to settle down */ + while (mmio_read_32(cci_base_addr + STATUS_REG) & CHANGE_PENDING_BIT) + ; +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/ccn/ccn.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/ccn/ccn.c new file mode 100644 index 0000000..060acdd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/ccn/ccn.c @@ -0,0 +1,516 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ccn_private.h" + +static const ccn_desc_t *ccn_plat_desc; +#if IMAGE_BL31 +DEFINE_BAKERY_LOCK(ccn_lock); +#endif + +/******************************************************************************* + * This function takes the base address of the CCN's programmer's view (PV), a + * region ID of one of the 256 regions (0-255) and a register offset within the + * region. It converts the first two parameters into a base address and uses it + * to read the register at the offset. + ******************************************************************************/ +static inline unsigned long long ccn_reg_read(uintptr_t periphbase, + unsigned int region_id, + unsigned int register_offset) +{ + uintptr_t region_base; + + assert(periphbase); + assert(region_id < REGION_ID_LIMIT); + + region_base = periphbase + region_id_to_base(region_id); + return mmio_read_64(region_base + register_offset); +} + +/******************************************************************************* + * This function takes the base address of the CCN's programmer's view (PV), a + * region ID of one of the 256 regions (0-255), a register offset within the + * region and a value. It converts the first two parameters into a base address + * and uses it to write the value in the register at the offset. + ******************************************************************************/ +static inline void ccn_reg_write(uintptr_t periphbase, + unsigned int region_id, + unsigned int register_offset, + unsigned long long value) +{ + uintptr_t region_base; + + assert(periphbase); + assert(region_id < REGION_ID_LIMIT); + + region_base = periphbase + region_id_to_base(region_id); + mmio_write_64(region_base + register_offset, value); +} + +#if DEBUG + +typedef struct rn_info { + unsigned char node_desc[MAX_RN_NODES]; + } rn_info_t; + +/******************************************************************************* + * This function takes the base address of the CCN's programmer's view (PV) and + * the node ID of a Request Node (RN-D or RN-I). It returns the maximum number + * of master interfaces resident on that node. This number is equal to the least + * significant two bits of the node type ID + 1. + ******************************************************************************/ +static unsigned int ccn_get_rni_mcount(uintptr_t periphbase, + unsigned int rn_id) +{ + unsigned int rn_type_id; + + /* Use the node id to find the type of RN-I/D node */ + rn_type_id = get_node_type(ccn_reg_read(periphbase, + rn_id + RNI_REGION_ID_START, + REGION_ID_OFFSET)); + + /* Return the number master interfaces based on node type */ + return rn_type_id_to_master_cnt(rn_type_id); +} + +/******************************************************************************* + * This function reads the CCN registers to find the following information about + * the ACE/ACELite/ACELite+DVM/CHI interfaces resident on the various types of + * Request Nodes (RN-Fs, RN-Is and RN-Ds) in the system: + * + * 1. The total number of such interfaces that this CCN IP supports. This is the + * cumulative number of interfaces across all Request node types. It is + * passed back as the return value of this function. + * + * 2. The maximum number of interfaces of a type resident on a Request node of + * one of the three types. This information is populated in the 'info' + * array provided by the caller as described next. + * + * The array has 64 entries. Each entry corresponds to a Request node. The + * Miscellaneous node's programmer's view has RN-F, RN-I and RN-D ID + * registers. For each RN-I and RN-D ID indicated as being present in these + * registers, its identification register (offset 0xFF00) is read. This + * register specifies the maximum number of master interfaces the node + * supports. For RN-Fs it is assumed that there can be only a single fully + * coherent master resident on each node. The counts for each type of node + * are use to populate the array entry at the index corresponding to the node + * ID i.e. rn_info[node ID] = + ******************************************************************************/ +static unsigned int ccn_get_rn_master_info(uintptr_t periphbase, + rn_info_t *info) +{ + unsigned int num_masters = 0; + rn_types_t rn_type; + + assert (info); + + for (rn_type = RN_TYPE_RNF; rn_type < NUM_RN_TYPES; rn_type++) { + unsigned int mn_reg_off, node_id; + unsigned long long rn_bitmap; + + /* + * RN-F, RN-I, RN-D node registers in the MN region occupy + * contiguous 16 byte apart offsets. + */ + mn_reg_off = MN_RNF_NODEID_OFFSET + (rn_type << 4); + rn_bitmap = ccn_reg_read(periphbase, MN_REGION_ID, mn_reg_off); + + FOR_EACH_PRESENT_NODE_ID(node_id, rn_bitmap) { + unsigned int node_mcount; + + /* + * A RN-F does not have a node type since it does not + * export a programmer's interface. It can only have a + * single fully coherent master residing on it. If the + * offset of the MN(Miscellaneous Node) register points + * to a RN-I/D node then the master count is set to the + * maximum number of master interfaces that can possibly + * reside on the node. + */ + node_mcount = (mn_reg_off == MN_RNF_NODEID_OFFSET ? 1 : + ccn_get_rni_mcount(periphbase, node_id)); + + /* + * Use this value to increment the maximum possible + * master interfaces in the system. + */ + num_masters += node_mcount; + + /* + * Update the entry in 'info' for this node ID with + * the maximum number of masters than can sit on + * it. This information will be used to validate the + * node information passed by the platform later. + */ + info->node_desc[node_id] = node_mcount; + } + } + + return num_masters; +} + +/******************************************************************************* + * This function validates parameters passed by the platform (in a debug build). + * It collects information about the maximum number of master interfaces that: + * a) the CCN IP can accommodate and + * b) can exist on each Request node. + * It compares this with the information provided by the platform to determine + * the validity of the latter. + ******************************************************************************/ +static void ccn_validate_plat_params(const ccn_desc_t *plat_desc) +{ + unsigned int master_id, num_rn_masters; + rn_info_t info = { {0} }; + + assert(plat_desc); + assert(plat_desc->periphbase); + assert(plat_desc->master_to_rn_id_map); + assert(plat_desc->num_masters); + assert(plat_desc->num_masters < CCN_MAX_RN_MASTERS); + + /* + * Find the number and properties of fully coherent, IO coherent and IO + * coherent + DVM master interfaces + */ + num_rn_masters = ccn_get_rn_master_info(plat_desc->periphbase, &info); + assert(plat_desc->num_masters < num_rn_masters); + + /* + * Iterate through the Request nodes specified by the platform. + * Decrement the count of the masters in the 'info' array for each + * Request node encountered. If the count would drop below 0 then the + * platform's view of this aspect of CCN configuration is incorrect. + */ + for (master_id = 0; master_id < plat_desc->num_masters; master_id++) { + unsigned int node_id; + + node_id = plat_desc->master_to_rn_id_map[master_id]; + assert(node_id < MAX_RN_NODES); + assert(info.node_desc[node_id]); + info.node_desc[node_id]--; + } +} +#endif /* DEBUG */ + +/******************************************************************************* + * This function validates parameters passed by the platform (in a debug build) + * and initialises its internal data structures. A lock is required to prevent + * simultaneous CCN operations at runtime (only BL31) to add and remove Request + * nodes from coherency. + ******************************************************************************/ +void ccn_init(const ccn_desc_t *plat_desc) +{ +#if DEBUG + ccn_validate_plat_params(plat_desc); +#endif + + ccn_plat_desc = plat_desc; +} + +/******************************************************************************* + * This function converts a bit map of master interface IDs to a bit map of the + * Request node IDs that they reside on. + ******************************************************************************/ +static unsigned long long ccn_master_to_rn_id_map(unsigned long long master_map) +{ + unsigned long long rn_id_map = 0; + unsigned int node_id, iface_id; + + assert(master_map); + assert(ccn_plat_desc); + + FOR_EACH_PRESENT_MASTER_INTERFACE(iface_id, master_map) { + assert(iface_id < ccn_plat_desc->num_masters); + + /* Convert the master ID into the node ID */ + node_id = ccn_plat_desc->master_to_rn_id_map[iface_id]; + + /* Set the bit corresponding to this node ID */ + rn_id_map |= (1UL << node_id); + } + + return rn_id_map; +} + +/******************************************************************************* + * This function executes the necessary operations to add or remove Request node + * IDs specified in the 'rn_id_map' bitmap from the snoop/DVM domains specified + * in the 'hn_id_map'. The 'region_id' specifies the ID of the first HN-F/MN + * on which the operation should be performed. 'op_reg_offset' specifies the + * type of operation (add/remove). 'stat_reg_offset' specifies the register + * which should be polled to determine if the operation has completed or not. + ******************************************************************************/ +static void ccn_snoop_dvm_do_op(unsigned long long rn_id_map, + unsigned long long hn_id_map, + unsigned int region_id, + unsigned int op_reg_offset, + unsigned int stat_reg_offset) +{ + unsigned int start_region_id; + + assert(ccn_plat_desc); + assert(ccn_plat_desc->periphbase); + +#if IMAGE_BL31 + bakery_lock_get(&ccn_lock); +#endif + start_region_id = region_id; + FOR_EACH_PRESENT_REGION_ID(start_region_id, hn_id_map) { + ccn_reg_write(ccn_plat_desc->periphbase, + start_region_id, + op_reg_offset, + rn_id_map); + } + + start_region_id = region_id; + + FOR_EACH_PRESENT_REGION_ID(start_region_id, hn_id_map) { + WAIT_FOR_DOMAIN_CTRL_OP_COMPLETION(start_region_id, + stat_reg_offset, + op_reg_offset, + rn_id_map); + } + +#if IMAGE_BL31 + bakery_lock_release(&ccn_lock); +#endif +} + +/******************************************************************************* + * The following functions provide the boot and runtime API to the platform for + * adding and removing master interfaces from the snoop/DVM domains. A bitmap of + * master interfaces IDs is passed as a parameter. It is converted into a bitmap + * of Request node IDs using the mapping provided by the platform while + * initialising the driver. + * For example, consider a dual cluster system where the clusters have values 0 + * & 1 in the affinity level 1 field of their respective MPIDRs. While + * initialising this driver, the platform provides the mapping between each + * cluster and the corresponding Request node. To add or remove a cluster from + * the snoop and dvm domain, the bit position corresponding to the cluster ID + * should be set in the 'master_iface_map' i.e. to remove both clusters the + * bitmap would equal 0x11. + ******************************************************************************/ +void ccn_enter_snoop_dvm_domain(unsigned long long master_iface_map) +{ + unsigned long long rn_id_map; + + rn_id_map = ccn_master_to_rn_id_map(master_iface_map); + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_HN_NODEID_MAP(ccn_plat_desc->periphbase, + MN_HNF_NODEID_OFFSET), + HNF_REGION_ID_START, + HNF_SDC_SET_OFFSET, + HNF_SDC_STAT_OFFSET); + + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_MN_NODEID_MAP(ccn_plat_desc->periphbase), + MN_REGION_ID, + MN_DDC_SET_OFFSET, + MN_DDC_STAT_OFFSET); +} + +void ccn_exit_snoop_dvm_domain(unsigned long long master_iface_map) +{ + unsigned long long rn_id_map; + + rn_id_map = ccn_master_to_rn_id_map(master_iface_map); + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_HN_NODEID_MAP(ccn_plat_desc->periphbase, + MN_HNF_NODEID_OFFSET), + HNF_REGION_ID_START, + HNF_SDC_CLR_OFFSET, + HNF_SDC_STAT_OFFSET); + + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_MN_NODEID_MAP(ccn_plat_desc->periphbase), + MN_REGION_ID, + MN_DDC_CLR_OFFSET, + MN_DDC_STAT_OFFSET); +} + +void ccn_enter_dvm_domain(unsigned long long master_iface_map) +{ + unsigned long long rn_id_map; + + rn_id_map = ccn_master_to_rn_id_map(master_iface_map); + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_MN_NODEID_MAP(ccn_plat_desc->periphbase), + MN_REGION_ID, + MN_DDC_SET_OFFSET, + MN_DDC_STAT_OFFSET); +} + +void ccn_exit_dvm_domain(unsigned long long master_iface_map) +{ + unsigned long long rn_id_map; + + rn_id_map = ccn_master_to_rn_id_map(master_iface_map); + ccn_snoop_dvm_do_op(rn_id_map, + CCN_GET_MN_NODEID_MAP(ccn_plat_desc->periphbase), + MN_REGION_ID, + MN_DDC_CLR_OFFSET, + MN_DDC_STAT_OFFSET); +} + +/******************************************************************************* + * This function returns the run mode of all the L3 cache partitions in the + * system. The state is expected to be one of NO_L3, SF_ONLY, L3_HAM or + * L3_FAM. Instead of comparing the states reported by all HN-Fs, the state of + * the first present HN-F node is reported. Since the driver does not export an + * interface to program them seperately, there is no reason to perform this + * check. An HN-F could report that the L3 cache is transitioning from one mode + * to another e.g. HNF_PM_NOL3_2_SFONLY. In this case, the function waits for + * the transition to complete and reports the final state. + ******************************************************************************/ +unsigned int ccn_get_l3_run_mode(void) +{ + unsigned long long hnf_pstate_stat; + + assert(ccn_plat_desc); + assert(ccn_plat_desc->periphbase); + + /* + * Wait for a L3 cache paritition to enter any run mode. The pstate + * parameter is read from an HN-F P-state status register. A non-zero + * value in bits[1:0] means that the cache is transitioning to a run + * mode. + */ + do { + hnf_pstate_stat = ccn_reg_read(ccn_plat_desc->periphbase, + HNF_REGION_ID_START, + HNF_PSTATE_STAT_OFFSET); + } while (hnf_pstate_stat & 0x3); + + return PSTATE_TO_RUN_MODE(hnf_pstate_stat); +} + +/******************************************************************************* + * This function sets the run mode of all the L3 cache partitions in the + * system to one of NO_L3, SF_ONLY, L3_HAM or L3_FAM depending upon the state + * specified by the 'mode' argument. + ******************************************************************************/ +void ccn_set_l3_run_mode(unsigned int mode) +{ + unsigned long long mn_hnf_id_map, hnf_pstate_stat; + unsigned int region_id; + + assert(ccn_plat_desc); + assert(ccn_plat_desc->periphbase); + assert(mode <= CCN_L3_RUN_MODE_FAM); + + mn_hnf_id_map = ccn_reg_read(ccn_plat_desc->periphbase, + MN_REGION_ID, + MN_HNF_NODEID_OFFSET); + region_id = HNF_REGION_ID_START; + + /* Program the desired run mode */ + FOR_EACH_PRESENT_REGION_ID(region_id, mn_hnf_id_map) { + ccn_reg_write(ccn_plat_desc->periphbase, + region_id, + HNF_PSTATE_REQ_OFFSET, + mode); + } + + /* Wait for the caches to transition to the run mode */ + region_id = HNF_REGION_ID_START; + FOR_EACH_PRESENT_REGION_ID(region_id, mn_hnf_id_map) { + /* + * Wait for a L3 cache paritition to enter a target run + * mode. The pstate parameter is read from an HN-F P-state + * status register. + */ + do { + hnf_pstate_stat = ccn_reg_read(ccn_plat_desc->periphbase, + region_id, + HNF_PSTATE_STAT_OFFSET); + } while (((hnf_pstate_stat & HNF_PSTATE_MASK) >> 2) != mode); + } +} + +/******************************************************************************* + * This function configures system address map and provides option to enable the + * 3SN striping mode of Slave node operation. The Slave node IDs and the Top + * Address bit1 and bit0 are provided as parameters to this function. This + * configuration is needed only if network contains a single SN-F or 3 SN-F and + * must be completed before the first request by the system to normal memory. + ******************************************************************************/ +void ccn_program_sys_addrmap(unsigned int sn0_id, + unsigned int sn1_id, + unsigned int sn2_id, + unsigned int top_addr_bit0, + unsigned int top_addr_bit1, + unsigned char three_sn_en) +{ + unsigned long long mn_hnf_id_map, hnf_sam_ctrl_value; + unsigned int region_id; + + assert(ccn_plat_desc); + assert(ccn_plat_desc->periphbase); + + mn_hnf_id_map = ccn_reg_read(ccn_plat_desc->periphbase, + MN_REGION_ID, + MN_HNF_NODEID_OFFSET); + region_id = HNF_REGION_ID_START; + hnf_sam_ctrl_value = MAKE_HNF_SAM_CTRL_VALUE(sn0_id, + sn1_id, + sn2_id, + top_addr_bit0, + top_addr_bit1, + three_sn_en); + + FOR_EACH_PRESENT_REGION_ID(region_id, mn_hnf_id_map) { + + /* Program the SAM control register */ + ccn_reg_write(ccn_plat_desc->periphbase, + region_id, + HNF_SAM_CTRL_OFFSET, + hnf_sam_ctrl_value); + } + +} + +/******************************************************************************* + * This function returns the part0 id from the peripheralID 0 register + * in CCN. This id can be used to distinguish the CCN variant present in the + * system. + ******************************************************************************/ +int ccn_get_part0_id(uintptr_t periphbase) +{ + assert(periphbase); + return (int)(mmio_read_64(periphbase + + MN_PERIPH_ID_0_1_OFFSET) & 0xFF); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/ccn/ccn_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/ccn/ccn_private.h new file mode 100644 index 0000000..a5a6146 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/ccn/ccn_private.h @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCN_PRIVATE_H__ +#define __CCN_PRIVATE_H__ + +/* + * A CCN implementation can have a maximum of 64 Request nodes with node IDs + * from 0-63. These IDs are split across the three types of Request nodes + * i.e. RN-F, RN-D and RN-I. + */ +#define MAX_RN_NODES 64 + +/* Enum used to loop through the 3 types of Request nodes */ +typedef enum rn_types { + RN_TYPE_RNF = 0, + RN_TYPE_RNI, + RN_TYPE_RND, + NUM_RN_TYPES +} rn_types_t; + +/* Macro to convert a region id to its base address */ +#define region_id_to_base(id) ((id) << 16) + +/* + * Macro to calculate the number of master interfaces resident on a RN-I/RN-D. + * Value of first two bits of the RN-I/D node type + 1 == Maximum number of + * ACE-Lite or ACE-Lite+DVM interfaces supported on this node. E.g. + * + * 0x14 : RN-I with 1 ACE-Lite interface + * 0x15 : RN-I with 2 ACE-Lite interfaces + * 0x16 : RN-I with 3 ACE-Lite interfaces + */ +#define rn_type_id_to_master_cnt(id) (((id) & 0x3) + 1) + +/* + * Constants used to identify a region in the programmer's view. These are + * common for all regions. + */ +#define REGION_ID_LIMIT 256 +#define REGION_ID_OFFSET 0xFF00 + +#define REGION_NODE_ID_SHIFT 8 +#define REGION_NODE_ID_MASK 0x7f +#define get_node_id(id_reg) (((id_reg) >> REGION_NODE_ID_SHIFT) \ + & REGION_NODE_ID_MASK) + +#define REGION_NODE_TYPE_SHIFT 0 +#define REGION_NODE_TYPE_MASK 0x1f +#define get_node_type(id_reg) (((id_reg) >> REGION_NODE_TYPE_SHIFT) \ + & REGION_NODE_TYPE_MASK) + +/* Common offsets of registers to enter or exit a snoop/dvm domain */ +#define DOMAIN_CTRL_STAT_OFFSET 0x0200 +#define DOMAIN_CTRL_SET_OFFSET 0x0210 +#define DOMAIN_CTRL_CLR_OFFSET 0x0220 + +/* + * Thess macros are used to determine if an operation to add or remove a Request + * node from the snoop/dvm domain has completed. 'rn_id_map' is a bit map of + * nodes. It was used to program the SET or CLEAR control register. The type of + * register is specified by 'op_reg_offset'. 'status_reg' is the bit map of + * nodes currently present in the snoop/dvm domain. 'rn_id_map' and 'status_reg' + * are logically ANDed and the result it stored back in the 'status_reg'. There + * are two outcomes of this operation: + * + * 1. If the DOMAIN_CTRL_SET_OFFSET register was programmed, then the set bits in + * 'rn_id_map' should appear in 'status_reg' when the operation completes. So + * after the AND operation, at some point of time 'status_reg' should equal + * 'rn_id_map'. + * + * 2. If the DOMAIN_CTRL_CLR_OFFSET register was programmed, then the set bits in + * 'rn_id_map' should disappear in 'status_reg' when the operation + * completes. So after the AND operation, at some point of time 'status_reg' + * should equal 0. + */ +#define WAIT_FOR_DOMAIN_CTRL_OP_COMPLETION(region_id, stat_reg_offset, \ + op_reg_offset, rn_id_map) \ + { \ + unsigned long long status_reg; \ + do { \ + status_reg = ccn_reg_read((ccn_plat_desc->periphbase), \ + (region_id), \ + (stat_reg_offset)); \ + status_reg &= (rn_id_map); \ + } while ((op_reg_offset) == DOMAIN_CTRL_SET_OFFSET ? \ + (rn_id_map) != status_reg : status_reg); \ + } + +/* + * Region ID of the Miscellaneous Node is always 0 as its located at the base of + * the programmer's view. + */ +#define MN_REGION_ID 0 + +#define MN_REGION_ID_START 0 +#define DEBUG_REGION_ID_START 1 +#define HNI_REGION_ID_START 8 +#define SBSX_REGION_ID_START 16 +#define HNF_REGION_ID_START 32 +#define XP_REGION_ID_START 64 +#define RNI_REGION_ID_START 128 + +/* Selected register offsets from the base of a HNF region */ +#define HNF_CFG_CTRL_OFFSET 0x0000 +#define HNF_SAM_CTRL_OFFSET 0x0008 +#define HNF_PSTATE_REQ_OFFSET 0x0010 +#define HNF_PSTATE_STAT_OFFSET 0x0018 +#define HNF_SDC_STAT_OFFSET DOMAIN_CTRL_STAT_OFFSET +#define HNF_SDC_SET_OFFSET DOMAIN_CTRL_SET_OFFSET +#define HNF_SDC_CLR_OFFSET DOMAIN_CTRL_CLR_OFFSET +#define HNF_AUX_CTRL_OFFSET 0x0500 + +/* Selected register offsets from the base of a MN region */ +#define MN_SAR_OFFSET 0x0000 +#define MN_RNF_NODEID_OFFSET 0x0180 +#define MN_RNI_NODEID_OFFSET 0x0190 +#define MN_RND_NODEID_OFFSET 0x01A0 +#define MN_HNF_NODEID_OFFSET 0x01B0 +#define MN_HNI_NODEID_OFFSET 0x01C0 +#define MN_SN_NODEID_OFFSET 0x01D0 +#define MN_DDC_STAT_OFFSET DOMAIN_CTRL_STAT_OFFSET +#define MN_DDC_SET_OFFSET DOMAIN_CTRL_SET_OFFSET +#define MN_DDC_CLR_OFFSET DOMAIN_CTRL_CLR_OFFSET +#define MN_PERIPH_ID_0_1_OFFSET 0xFE0 +#define MN_ID_OFFSET REGION_ID_OFFSET + +/* HNF System Address Map register bit masks and shifts */ +#define HNF_SAM_CTRL_SN_ID_MASK 0x7f +#define HNF_SAM_CTRL_SN0_ID_SHIFT 0 +#define HNF_SAM_CTRL_SN1_ID_SHIFT 8 +#define HNF_SAM_CTRL_SN2_ID_SHIFT 16 + +#define HNF_SAM_CTRL_TAB0_MASK 0x3fUL +#define HNF_SAM_CTRL_TAB0_SHIFT 48 +#define HNF_SAM_CTRL_TAB1_MASK 0x3fUL +#define HNF_SAM_CTRL_TAB1_SHIFT 56 + +#define HNF_SAM_CTRL_3SN_ENB_SHIFT 32 +#define HNF_SAM_CTRL_3SN_ENB_MASK 0x01UL + +/* + * Macro to create a value suitable for programming into a HNF SAM Control + * register for enabling 3SN striping. + */ +#define MAKE_HNF_SAM_CTRL_VALUE(sn0, sn1, sn2, tab0, tab1, three_sn_en) \ + ((((sn0) & HNF_SAM_CTRL_SN_ID_MASK) << HNF_SAM_CTRL_SN0_ID_SHIFT) | \ + (((sn1) & HNF_SAM_CTRL_SN_ID_MASK) << HNF_SAM_CTRL_SN1_ID_SHIFT) | \ + (((sn2) & HNF_SAM_CTRL_SN_ID_MASK) << HNF_SAM_CTRL_SN2_ID_SHIFT) | \ + (((tab0) & HNF_SAM_CTRL_TAB0_MASK) << HNF_SAM_CTRL_TAB0_SHIFT) | \ + (((tab1) & HNF_SAM_CTRL_TAB1_MASK) << HNF_SAM_CTRL_TAB1_SHIFT) | \ + (((three_sn_en) & HNF_SAM_CTRL_3SN_ENB_MASK) << HNF_SAM_CTRL_3SN_ENB_SHIFT)) + +/* Mask to read the power state value from an HN-F P-state register */ +#define HNF_PSTATE_MASK 0xf + +/* Macro to extract the run mode from a p-state value */ +#define PSTATE_TO_RUN_MODE(pstate) (((pstate) & HNF_PSTATE_MASK) >> 2) + +/* + * Helper macro that iterates through a given bit map. In each iteration, + * it returns the position of the set bit. + * It can be used by other utility macros to iterates through all nodes + * or masters given a bit map of them. + */ +#define FOR_EACH_BIT(bit_pos, bit_map) \ + for (bit_pos = __builtin_ctzll(bit_map); \ + bit_map; \ + bit_map &= ~(1UL << bit_pos), \ + bit_pos = __builtin_ctzll(bit_map)) + +/* + * Utility macro that iterates through a bit map of node IDs. In each + * iteration, it returns the ID of the next present node in the bit map. Node + * ID of a present node == Position of set bit == Number of zeroes trailing the + * bit. + */ +#define FOR_EACH_PRESENT_NODE_ID(node_id, bit_map) \ + FOR_EACH_BIT(node_id, bit_map) + +/* + * Helper function to return number of set bits in bitmap + */ +static inline unsigned int count_set_bits(unsigned long long bitmap) +{ + unsigned int count = 0; + + for (; bitmap; bitmap &= bitmap - 1) + ++count; + + return count; +} + +/* + * Utility macro that iterates through a bit map of node IDs. In each iteration, + * it returns the ID of the next present region corresponding to a node present + * in the bit map. Region ID of a present node is in between passed region id + * and region id + number of set bits in the bitmap i.e. the number of present + * nodes. + */ +#define FOR_EACH_PRESENT_REGION_ID(region_id, bit_map) \ + for (unsigned long long region_id_limit = count_set_bits(bit_map) \ + + region_id; \ + region_id < region_id_limit; \ + region_id++) + +/* + * Same macro as FOR_EACH_PRESENT_NODE, but renamed to indicate it traverses + * through a bit map of master interfaces. + */ +#define FOR_EACH_PRESENT_MASTER_INTERFACE(iface_id, bit_map) \ + FOR_EACH_BIT(iface_id, bit_map) + +/* + * Macro that returns the node id bit map for the Miscellaneous Node + */ +#define CCN_GET_MN_NODEID_MAP(periphbase) \ + (1 << get_node_id(ccn_reg_read(periphbase, MN_REGION_ID, \ + REGION_ID_OFFSET))) + +/* + * This macro returns the bitmap of Home nodes on the basis of the + * 'mn_hn_id_reg_offset' parameter from the Miscellaneous node's (MN) + * programmer's view. The MN has a register which carries the bitmap of present + * Home nodes of each type i.e. HN-Fs, HN-Is & HN-Ds. + */ +#define CCN_GET_HN_NODEID_MAP(periphbase, mn_hn_id_reg_offset) \ + ccn_reg_read(periphbase, MN_REGION_ID, mn_hn_id_reg_offset) + +#endif /* __CCN_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/arm_gic.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/arm_gic.c new file mode 100644 index 0000000..82c5448 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/arm_gic.c @@ -0,0 +1,459 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Value used to initialize Non-Secure IRQ priorities four at a time */ +#define GICD_IPRIORITYR_DEF_VAL \ + (GIC_HIGHEST_NS_PRIORITY | \ + (GIC_HIGHEST_NS_PRIORITY << 8) | \ + (GIC_HIGHEST_NS_PRIORITY << 16) | \ + (GIC_HIGHEST_NS_PRIORITY << 24)) + +static uintptr_t g_gicc_base; +static uintptr_t g_gicd_base; +static uintptr_t g_gicr_base; +static const unsigned int *g_irq_sec_ptr; +static unsigned int g_num_irqs; + + +/******************************************************************************* + * This function does some minimal GICv3 configuration. The Firmware itself does + * not fully support GICv3 at this time and relies on GICv2 emulation as + * provided by GICv3. This function allows software (like Linux) in later stages + * to use full GICv3 features. + ******************************************************************************/ +static void gicv3_cpuif_setup(void) +{ + unsigned int val; + uintptr_t base; + + /* + * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep + * bit set. In order to allow interrupts to get routed to the CPU we + * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep + * to clear (GICv3 Architecture specification 5.4.23). + * GICR_WAKER is NOT banked per CPU, compute the correct base address + * per CPU. + */ + assert(g_gicr_base); + base = gicv3_get_rdist(g_gicr_base, read_mpidr()); + if (base == (uintptr_t)NULL) { + /* No re-distributor base address. This interface cannot be + * configured. + */ + panic(); + } + + val = gicr_read_waker(base); + + val &= ~WAKER_PS; + gicr_write_waker(base, val); + dsb(); + + /* We need to wait for ChildrenAsleep to clear. */ + val = gicr_read_waker(base); + while (val & WAKER_CA) + val = gicr_read_waker(base); + + val = read_icc_sre_el3(); + write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE); + isb(); +} + +/******************************************************************************* + * This function does some minimal GICv3 configuration when cores go + * down. + ******************************************************************************/ +static void gicv3_cpuif_deactivate(void) +{ + unsigned int val; + uintptr_t base; + + /* + * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and + * wait for GICR_WAKER.ChildrenAsleep to get set. + * (GICv3 Architecture specification 5.4.23). + * GICR_WAKER is NOT banked per CPU, compute the correct base address + * per CPU. + */ + assert(g_gicr_base); + base = gicv3_get_rdist(g_gicr_base, read_mpidr()); + if (base == (uintptr_t)NULL) { + /* No re-distributor base address. This interface cannot be + * configured. + */ + panic(); + } + + val = gicr_read_waker(base); + val |= WAKER_PS; + gicr_write_waker(base, val); + dsb(); + + /* We need to wait for ChildrenAsleep to set. */ + val = gicr_read_waker(base); + while ((val & WAKER_CA) == 0) + val = gicr_read_waker(base); +} + + +/******************************************************************************* + * Enable secure interrupts and use FIQs to route them. Disable legacy bypass + * and set the priority mask register to allow all interrupts to trickle in. + ******************************************************************************/ +void arm_gic_cpuif_setup(void) +{ + unsigned int val; + + assert(g_gicc_base); + val = gicc_read_iidr(g_gicc_base); + + /* + * If GICv3 we need to do a bit of additional setup. We want to + * allow default GICv2 behaviour but allow the next stage to + * enable full gicv3 features. + */ + if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) + gicv3_cpuif_setup(); + + val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0; + val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; + + gicc_write_pmr(g_gicc_base, GIC_PRI_MASK); + gicc_write_ctlr(g_gicc_base, val); +} + +/******************************************************************************* + * Place the cpu interface in a state where it can never make a cpu exit wfi as + * as result of an asserted interrupt. This is critical for powering down a cpu + ******************************************************************************/ +void arm_gic_cpuif_deactivate(void) +{ + unsigned int val; + + /* Disable secure, non-secure interrupts and disable their bypass */ + assert(g_gicc_base); + val = gicc_read_ctlr(g_gicc_base); + val &= ~(ENABLE_GRP0 | ENABLE_GRP1); + val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; + val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; + gicc_write_ctlr(g_gicc_base, val); + + val = gicc_read_iidr(g_gicc_base); + + /* + * If GICv3 we need to do a bit of additional setup. Make sure the + * RDIST is put to sleep. + */ + if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) + gicv3_cpuif_deactivate(); +} + +/******************************************************************************* + * Per cpu gic distributor setup which will be done by all cpus after a cold + * boot/hotplug. This marks out the secure interrupts & enables them. + ******************************************************************************/ +void arm_gic_pcpu_distif_setup(void) +{ + unsigned int index, irq_num, sec_ppi_sgi_mask; + + assert(g_gicd_base); + + /* Setup PPI priorities doing four at a time */ + for (index = 0; index < 32; index += 4) { + gicd_write_ipriorityr(g_gicd_base, index, + GICD_IPRIORITYR_DEF_VAL); + } + + assert(g_irq_sec_ptr); + sec_ppi_sgi_mask = 0; + + /* Ensure all SGIs and PPIs are Group0 to begin with */ + gicd_write_igroupr(g_gicd_base, 0, 0); + + for (index = 0; index < g_num_irqs; index++) { + irq_num = g_irq_sec_ptr[index]; + if (irq_num < MIN_SPI_ID) { + /* We have an SGI or a PPI */ + sec_ppi_sgi_mask |= 1U << irq_num; + gicd_set_ipriorityr(g_gicd_base, irq_num, + GIC_HIGHEST_SEC_PRIORITY); + gicd_set_isenabler(g_gicd_base, irq_num); + } + } + + /* + * Invert the bitmask to create a mask for non-secure PPIs and + * SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will + * update the GICR_IGROUPR0 as well in case we are running on a GICv3 + * system. This is critical if GICD_CTLR.ARE_NS=1. + */ + gicd_write_igroupr(g_gicd_base, 0, ~sec_ppi_sgi_mask); +} + +/******************************************************************************* + * Get the current CPU bit mask from GICD_ITARGETSR0 + ******************************************************************************/ +static unsigned int arm_gic_get_cpuif_id(void) +{ + unsigned int val; + + val = gicd_read_itargetsr(g_gicd_base, 0); + return val & GIC_TARGET_CPU_MASK; +} + +/******************************************************************************* + * Global gic distributor setup which will be done by the primary cpu after a + * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It + * then enables the secure GIC distributor interface. + ******************************************************************************/ +static void arm_gic_distif_setup(void) +{ + unsigned int num_ints, ctlr, index, irq_num; + uint8_t target_cpu; + + /* Disable the distributor before going further */ + assert(g_gicd_base); + ctlr = gicd_read_ctlr(g_gicd_base); + ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1); + gicd_write_ctlr(g_gicd_base, ctlr); + + /* + * Mark out non-secure SPI interrupts. The number of interrupts is + * calculated as 32 * (IT_LINES + 1). We do 32 at a time. + */ + num_ints = gicd_read_typer(g_gicd_base) & IT_LINES_NO_MASK; + num_ints = (num_ints + 1) << 5; + for (index = MIN_SPI_ID; index < num_ints; index += 32) + gicd_write_igroupr(g_gicd_base, index, ~0); + + /* Setup SPI priorities doing four at a time */ + for (index = MIN_SPI_ID; index < num_ints; index += 4) { + gicd_write_ipriorityr(g_gicd_base, index, + GICD_IPRIORITYR_DEF_VAL); + } + + /* Read the target CPU mask */ + target_cpu = arm_gic_get_cpuif_id(); + + /* Configure SPI secure interrupts now */ + assert(g_irq_sec_ptr); + for (index = 0; index < g_num_irqs; index++) { + irq_num = g_irq_sec_ptr[index]; + if (irq_num >= MIN_SPI_ID) { + /* We have an SPI */ + gicd_clr_igroupr(g_gicd_base, irq_num); + gicd_set_ipriorityr(g_gicd_base, irq_num, + GIC_HIGHEST_SEC_PRIORITY); + gicd_set_itargetsr(g_gicd_base, irq_num, target_cpu); + gicd_set_isenabler(g_gicd_base, irq_num); + } + } + + /* + * Configure the SGI and PPI. This is done in a separated function + * because each CPU is responsible for initializing its own private + * interrupts. + */ + arm_gic_pcpu_distif_setup(); + + gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0); +} + +/******************************************************************************* + * Initialize the ARM GIC driver with the provided platform inputs +******************************************************************************/ +void arm_gic_init(uintptr_t gicc_base, + uintptr_t gicd_base, + uintptr_t gicr_base, + const unsigned int *irq_sec_ptr, + unsigned int num_irqs) +{ + unsigned int val; + + assert(gicc_base); + assert(gicd_base); + assert(irq_sec_ptr); + + g_gicc_base = gicc_base; + g_gicd_base = gicd_base; + + val = gicc_read_iidr(g_gicc_base); + + if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) { + assert(gicr_base); + g_gicr_base = gicr_base; + } + + g_irq_sec_ptr = irq_sec_ptr; + g_num_irqs = num_irqs; +} + +/******************************************************************************* + * Setup the ARM GIC CPU and distributor interfaces. +******************************************************************************/ +void arm_gic_setup(void) +{ + arm_gic_cpuif_setup(); + arm_gic_distif_setup(); +} + +/******************************************************************************* + * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. + * The interrupt controller knows which pin/line it uses to signal a type of + * interrupt. This function provides a common implementation of + * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use + * across platforms. It lets the interrupt management framework determine + * for a type of interrupt and security state, which line should be used in the + * SCR_EL3 to control its routing to EL3. The interrupt line is represented as + * the bit position of the IRQ or FIQ bit in the SCR_EL3. + ******************************************************************************/ +uint32_t arm_gic_interrupt_type_to_line(uint32_t type, + uint32_t security_state) +{ + assert(type == INTR_TYPE_S_EL1 || + type == INTR_TYPE_EL3 || + type == INTR_TYPE_NS); + + assert(sec_state_is_valid(security_state)); + + /* + * We ignore the security state parameter under the assumption that + * both normal and secure worlds are using ARM GICv2. This parameter + * will be used when the secure world starts using GICv3. + */ +#if ARM_GIC_ARCH == 2 + return gicv2_interrupt_type_to_line(g_gicc_base, type); +#else +#error "Invalid ARM GIC architecture version specified for platform port" +#endif /* ARM_GIC_ARCH */ +} + +#if ARM_GIC_ARCH == 2 +/******************************************************************************* + * This function returns the type of the highest priority pending interrupt at + * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no + * interrupt pending. + ******************************************************************************/ +uint32_t arm_gic_get_pending_interrupt_type(void) +{ + uint32_t id; + + assert(g_gicc_base); + id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK; + + /* Assume that all secure interrupts are S-EL1 interrupts */ + if (id < 1022) + return INTR_TYPE_S_EL1; + + if (id == GIC_SPURIOUS_INTERRUPT) + return INTR_TYPE_INVAL; + + return INTR_TYPE_NS; +} + +/******************************************************************************* + * This function returns the id of the highest priority pending interrupt at + * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no + * interrupt pending. + ******************************************************************************/ +uint32_t arm_gic_get_pending_interrupt_id(void) +{ + uint32_t id; + + assert(g_gicc_base); + id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK; + + if (id < 1022) + return id; + + if (id == 1023) + return INTR_ID_UNAVAILABLE; + + /* + * Find out which non-secure interrupt it is under the assumption that + * the GICC_CTLR.AckCtl bit is 0. + */ + return gicc_read_ahppir(g_gicc_base) & INT_ID_MASK; +} + +/******************************************************************************* + * This functions reads the GIC cpu interface Interrupt Acknowledge register + * to start handling the pending interrupt. It returns the contents of the IAR. + ******************************************************************************/ +uint32_t arm_gic_acknowledge_interrupt(void) +{ + assert(g_gicc_base); + return gicc_read_IAR(g_gicc_base); +} + +/******************************************************************************* + * This functions writes the GIC cpu interface End Of Interrupt register with + * the passed value to finish handling the active interrupt + ******************************************************************************/ +void arm_gic_end_of_interrupt(uint32_t id) +{ + assert(g_gicc_base); + gicc_write_EOIR(g_gicc_base, id); +} + +/******************************************************************************* + * This function returns the type of the interrupt id depending upon the group + * this interrupt has been configured under by the interrupt controller i.e. + * group0 or group1. + ******************************************************************************/ +uint32_t arm_gic_get_interrupt_type(uint32_t id) +{ + uint32_t group; + + assert(g_gicd_base); + group = gicd_get_igroupr(g_gicd_base, id); + + /* Assume that all secure interrupts are S-EL1 interrupts */ + if (group == GRP0) + return INTR_TYPE_S_EL1; + else + return INTR_TYPE_NS; +} + +#else +#error "Invalid ARM GIC architecture version specified for platform port" +#endif /* ARM_GIC_ARCH */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/common/gic_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/common/gic_common.c new file mode 100644 index 0000000..cfa0d23 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/common/gic_common.c @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "gic_common_private.h" + +/******************************************************************************* + * GIC Distributor interface accessors for reading entire registers + ******************************************************************************/ +/* + * Accessor to read the GIC Distributor IGROUPR corresponding to the interrupt + * `id`, 32 interrupt ids at a time. + */ +unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> IGROUPR_SHIFT; + return mmio_read_32(base + GICD_IGROUPR + (n << 2)); +} + +/* + * Accessor to read the GIC Distributor ISENABLER corresponding to the + * interrupt `id`, 32 interrupt ids at a time. + */ +unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ISENABLER_SHIFT; + return mmio_read_32(base + GICD_ISENABLER + (n << 2)); +} + +/* + * Accessor to read the GIC Distributor ICENABLER corresponding to the + * interrupt `id`, 32 interrupt IDs at a time. + */ +unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICENABLER_SHIFT; + return mmio_read_32(base + GICD_ICENABLER + (n << 2)); +} + +/* + * Accessor to read the GIC Distributor ISPENDR corresponding to the + * interrupt `id`, 32 interrupt IDs at a time. + */ +unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ISPENDR_SHIFT; + return mmio_read_32(base + GICD_ISPENDR + (n << 2)); +} + +/* + * Accessor to read the GIC Distributor ICPENDR corresponding to the + * interrupt `id`, 32 interrupt IDs at a time. + */ +unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICPENDR_SHIFT; + return mmio_read_32(base + GICD_ICPENDR + (n << 2)); +} + +/* + * Accessor to read the GIC Distributor ISACTIVER corresponding to the + * interrupt `id`, 32 interrupt IDs at a time. + */ +unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ISACTIVER_SHIFT; + return mmio_read_32(base + GICD_ISACTIVER + (n << 2)); +} + +/* + * Accessor to read the GIC Distributor ICACTIVER corresponding to the + * interrupt `id`, 32 interrupt IDs at a time. + */ +unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICACTIVER_SHIFT; + return mmio_read_32(base + GICD_ICACTIVER + (n << 2)); +} + +/* + * Accessor to read the GIC Distributor IPRIORITYR corresponding to the + * interrupt `id`, 4 interrupt IDs at a time. + */ +unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> IPRIORITYR_SHIFT; + return mmio_read_32(base + GICD_IPRIORITYR + (n << 2)); +} + +/* + * Accessor to read the GIC Distributor ICGFR corresponding to the + * interrupt `id`, 16 interrupt IDs at a time. + */ +unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICFGR_SHIFT; + return mmio_read_32(base + GICD_ICFGR + (n << 2)); +} + +/* + * Accessor to read the GIC Distributor NSACR corresponding to the + * interrupt `id`, 16 interrupt IDs at a time. + */ +unsigned int gicd_read_nsacr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> NSACR_SHIFT; + return mmio_read_32(base + GICD_NSACR + (n << 2)); +} + +/******************************************************************************* + * GIC Distributor interface accessors for writing entire registers + ******************************************************************************/ +/* + * Accessor to write the GIC Distributor IGROUPR corresponding to the + * interrupt `id`, 32 interrupt IDs at a time. + */ +void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> IGROUPR_SHIFT; + mmio_write_32(base + GICD_IGROUPR + (n << 2), val); +} + +/* + * Accessor to write the GIC Distributor ISENABLER corresponding to the + * interrupt `id`, 32 interrupt IDs at a time. + */ +void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISENABLER_SHIFT; + mmio_write_32(base + GICD_ISENABLER + (n << 2), val); +} + +/* + * Accessor to write the GIC Distributor ICENABLER corresponding to the + * interrupt `id`, 32 interrupt IDs at a time. + */ +void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICENABLER_SHIFT; + mmio_write_32(base + GICD_ICENABLER + (n << 2), val); +} + +/* + * Accessor to write the GIC Distributor ISPENDR corresponding to the + * interrupt `id`, 32 interrupt IDs at a time. + */ +void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISPENDR_SHIFT; + mmio_write_32(base + GICD_ISPENDR + (n << 2), val); +} + +/* + * Accessor to write the GIC Distributor ICPENDR corresponding to the + * interrupt `id`, 32 interrupt IDs at a time. + */ +void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICPENDR_SHIFT; + mmio_write_32(base + GICD_ICPENDR + (n << 2), val); +} + +/* + * Accessor to write the GIC Distributor ISACTIVER corresponding to the + * interrupt `id`, 32 interrupt IDs at a time. + */ +void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISACTIVER_SHIFT; + mmio_write_32(base + GICD_ISACTIVER + (n << 2), val); +} + +/* + * Accessor to write the GIC Distributor ICACTIVER corresponding to the + * interrupt `id`, 32 interrupt IDs at a time. + */ +void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICACTIVER_SHIFT; + mmio_write_32(base + GICD_ICACTIVER + (n << 2), val); +} + +/* + * Accessor to write the GIC Distributor IPRIORITYR corresponding to the + * interrupt `id`, 4 interrupt IDs at a time. + */ +void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> IPRIORITYR_SHIFT; + mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val); +} + +/* + * Accessor to write the GIC Distributor ICFGR corresponding to the + * interrupt `id`, 16 interrupt IDs at a time. + */ +void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICFGR_SHIFT; + mmio_write_32(base + GICD_ICFGR + (n << 2), val); +} + +/* + * Accessor to write the GIC Distributor NSACR corresponding to the + * interrupt `id`, 16 interrupt IDs at a time. + */ +void gicd_write_nsacr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> NSACR_SHIFT; + mmio_write_32(base + GICD_NSACR + (n << 2), val); +} + +/******************************************************************************* + * GIC Distributor functions for accessing the GIC registers + * corresponding to a single interrupt ID. These functions use bitwise + * operations or appropriate register accesses to modify or return + * the bit-field corresponding the single interrupt ID. + ******************************************************************************/ +unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + return (reg_val >> bit_num) & 0x1; +} + +void gicd_set_igroupr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + gicd_write_igroupr(base, id, reg_val | (1 << bit_num)); +} + +void gicd_clr_igroupr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num)); +} + +void gicd_set_isenabler(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); + + gicd_write_isenabler(base, id, (1 << bit_num)); +} + +void gicd_set_icenabler(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1); + + gicd_write_icenabler(base, id, (1 << bit_num)); +} + +void gicd_set_ispendr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1); + + gicd_write_ispendr(base, id, (1 << bit_num)); +} + +void gicd_set_icpendr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1); + + gicd_write_icpendr(base, id, (1 << bit_num)); +} + +void gicd_set_isactiver(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1); + + gicd_write_isactiver(base, id, (1 << bit_num)); +} + +void gicd_set_icactiver(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1); + + gicd_write_icactiver(base, id, (1 << bit_num)); +} + +void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) +{ + mmio_write_8(base + GICD_IPRIORITYR + id, pri & GIC_PRI_MASK); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/common/gic_common_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/common/gic_common_private.h new file mode 100644 index 0000000..2919b7f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/common/gic_common_private.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef GIC_COMMON_PRIVATE_H_ +#define GIC_COMMON_PRIVATE_H_ + +#include +#include +#include + +/******************************************************************************* + * GIC Distributor interface register accessors that are common to GICv3 & GICv2 + ******************************************************************************/ +static inline unsigned int gicd_read_ctlr(uintptr_t base) +{ + return mmio_read_32(base + GICD_CTLR); +} + +static inline unsigned int gicd_read_typer(uintptr_t base) +{ + return mmio_read_32(base + GICD_TYPER); +} + +static inline unsigned int gicd_read_iidr(uintptr_t base) +{ + return mmio_read_32(base + GICD_IIDR); +} + +static inline void gicd_write_ctlr(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICD_CTLR, val); +} + +/******************************************************************************* + * GIC Distributor function prototypes for accessing entire registers. + * Note: The raw register values correspond to multiple interrupt IDs and + * the number of interrupt IDs involved depends on the register accessed. + ******************************************************************************/ +unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id); +unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id); +unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id); +unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id); +unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id); +unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id); +unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id); +unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id); +unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id); +unsigned int gicd_read_nsacr(uintptr_t base, unsigned int id); +void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val); +void gicd_write_nsacr(uintptr_t base, unsigned int id, unsigned int val); + +/******************************************************************************* + * GIC Distributor function prototypes for accessing the GIC registers + * corresponding to a single interrupt ID. These functions use bitwise + * operations or appropriate register accesses to modify or return + * the bit-field corresponding the single interrupt ID. + ******************************************************************************/ +unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id); +void gicd_set_igroupr(uintptr_t base, unsigned int id); +void gicd_clr_igroupr(uintptr_t base, unsigned int id); +void gicd_set_isenabler(uintptr_t base, unsigned int id); +void gicd_set_icenabler(uintptr_t base, unsigned int id); +void gicd_set_ispendr(uintptr_t base, unsigned int id); +void gicd_set_icpendr(uintptr_t base, unsigned int id); +void gicd_set_isactiver(uintptr_t base, unsigned int id); +void gicd_set_icactiver(uintptr_t base, unsigned int id); +void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); + +#endif /* GIC_COMMON_PRIVATE_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/gic_v2.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/gic_v2.c new file mode 100644 index 0000000..05399c3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/gic_v2.c @@ -0,0 +1,308 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/******************************************************************************* + * GIC Distributor interface accessors for reading entire registers + ******************************************************************************/ + +unsigned int gicd_read_igroupr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> IGROUPR_SHIFT; + return mmio_read_32(base + GICD_IGROUPR + (n << 2)); +} + +unsigned int gicd_read_isenabler(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ISENABLER_SHIFT; + return mmio_read_32(base + GICD_ISENABLER + (n << 2)); +} + +unsigned int gicd_read_icenabler(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICENABLER_SHIFT; + return mmio_read_32(base + GICD_ICENABLER + (n << 2)); +} + +unsigned int gicd_read_ispendr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ISPENDR_SHIFT; + return mmio_read_32(base + GICD_ISPENDR + (n << 2)); +} + +unsigned int gicd_read_icpendr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICPENDR_SHIFT; + return mmio_read_32(base + GICD_ICPENDR + (n << 2)); +} + +unsigned int gicd_read_isactiver(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ISACTIVER_SHIFT; + return mmio_read_32(base + GICD_ISACTIVER + (n << 2)); +} + +unsigned int gicd_read_icactiver(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICACTIVER_SHIFT; + return mmio_read_32(base + GICD_ICACTIVER + (n << 2)); +} + +unsigned int gicd_read_ipriorityr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> IPRIORITYR_SHIFT; + return mmio_read_32(base + GICD_IPRIORITYR + (n << 2)); +} + +unsigned int gicd_read_itargetsr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ITARGETSR_SHIFT; + return mmio_read_32(base + GICD_ITARGETSR + (n << 2)); +} + +unsigned int gicd_read_icfgr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ICFGR_SHIFT; + return mmio_read_32(base + GICD_ICFGR + (n << 2)); +} + +unsigned int gicd_read_cpendsgir(uintptr_t base, unsigned int id) +{ + unsigned n = id >> CPENDSGIR_SHIFT; + return mmio_read_32(base + GICD_CPENDSGIR + (n << 2)); +} + +unsigned int gicd_read_spendsgir(uintptr_t base, unsigned int id) +{ + unsigned n = id >> SPENDSGIR_SHIFT; + return mmio_read_32(base + GICD_SPENDSGIR + (n << 2)); +} + +/******************************************************************************* + * GIC Distributor interface accessors for writing entire registers + ******************************************************************************/ + +void gicd_write_igroupr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> IGROUPR_SHIFT; + mmio_write_32(base + GICD_IGROUPR + (n << 2), val); +} + +void gicd_write_isenabler(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISENABLER_SHIFT; + mmio_write_32(base + GICD_ISENABLER + (n << 2), val); +} + +void gicd_write_icenabler(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICENABLER_SHIFT; + mmio_write_32(base + GICD_ICENABLER + (n << 2), val); +} + +void gicd_write_ispendr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISPENDR_SHIFT; + mmio_write_32(base + GICD_ISPENDR + (n << 2), val); +} + +void gicd_write_icpendr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICPENDR_SHIFT; + mmio_write_32(base + GICD_ICPENDR + (n << 2), val); +} + +void gicd_write_isactiver(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ISACTIVER_SHIFT; + mmio_write_32(base + GICD_ISACTIVER + (n << 2), val); +} + +void gicd_write_icactiver(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICACTIVER_SHIFT; + mmio_write_32(base + GICD_ICACTIVER + (n << 2), val); +} + +void gicd_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> IPRIORITYR_SHIFT; + mmio_write_32(base + GICD_IPRIORITYR + (n << 2), val); +} + +void gicd_write_itargetsr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ITARGETSR_SHIFT; + mmio_write_32(base + GICD_ITARGETSR + (n << 2), val); +} + +void gicd_write_icfgr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ICFGR_SHIFT; + mmio_write_32(base + GICD_ICFGR + (n << 2), val); +} + +void gicd_write_cpendsgir(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> CPENDSGIR_SHIFT; + mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val); +} + +void gicd_write_spendsgir(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> SPENDSGIR_SHIFT; + mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val); +} + +/******************************************************************************* + * GIC Distributor interface accessors for individual interrupt manipulation + ******************************************************************************/ +unsigned int gicd_get_igroupr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + return (reg_val >> bit_num) & 0x1; +} + +void gicd_set_igroupr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + gicd_write_igroupr(base, id, reg_val | (1 << bit_num)); +} + +void gicd_clr_igroupr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igroupr(base, id); + + gicd_write_igroupr(base, id, reg_val & ~(1 << bit_num)); +} + +void gicd_set_isenabler(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); + + gicd_write_isenabler(base, id, (1 << bit_num)); +} + +void gicd_set_icenabler(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1); + + gicd_write_icenabler(base, id, (1 << bit_num)); +} + +void gicd_set_ispendr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1); + + gicd_write_ispendr(base, id, (1 << bit_num)); +} + +void gicd_set_icpendr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1); + + gicd_write_icpendr(base, id, (1 << bit_num)); +} + +void gicd_set_isactiver(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1); + + gicd_write_isactiver(base, id, (1 << bit_num)); +} + +void gicd_set_icactiver(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ICACTIVER_SHIFT) - 1); + + gicd_write_icactiver(base, id, (1 << bit_num)); +} + +/* + * Make sure that the interrupt's group is set before expecting + * this function to do its job correctly. + */ +void gicd_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) +{ + /* + * Enforce ARM recommendation to manage priority values such + * that group1 interrupts always have a lower priority than + * group0 interrupts. + * Note, lower numerical values are higher priorities so the comparison + * checks below are reversed from what might be expected. + */ + assert(gicd_get_igroupr(base, id) == GRP1 ? + pri >= GIC_HIGHEST_NS_PRIORITY && + pri <= GIC_LOWEST_NS_PRIORITY : + pri >= GIC_HIGHEST_SEC_PRIORITY && + pri <= GIC_LOWEST_SEC_PRIORITY); + + mmio_write_8(base + GICD_IPRIORITYR + id, pri & GIC_PRI_MASK); +} + +void gicd_set_itargetsr(uintptr_t base, unsigned int id, unsigned int target) +{ + mmio_write_8(base + GICD_ITARGETSR + id, target & GIC_TARGET_CPU_MASK); +} + +/******************************************************************************* + * This function allows the interrupt management framework to determine (through + * the platform) which interrupt line (IRQ/FIQ) to use for an interrupt type to + * route it to EL3. The interrupt line is represented as the bit position of the + * IRQ or FIQ bit in the SCR_EL3. + ******************************************************************************/ +uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type) +{ + uint32_t gicc_ctlr; + + /* Non-secure interrupts are signalled on the IRQ line always */ + if (type == INTR_TYPE_NS) + return __builtin_ctz(SCR_IRQ_BIT); + + /* + * Secure interrupts are signalled using the IRQ line if the FIQ_EN + * bit is not set else they are signalled using the FIQ line. + */ + gicc_ctlr = gicc_read_ctlr(cpuif_base); + if (gicc_ctlr & FIQ_EN) + return __builtin_ctz(SCR_FIQ_BIT); + else + return __builtin_ctz(SCR_IRQ_BIT); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/gic_v3.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/gic_v3.c new file mode 100644 index 0000000..11185b2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/gic_v3.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr) +{ + uint32_t cpu_aff, gicr_aff; + uint64_t gicr_typer; + uintptr_t addr; + + /* Construct the affinity as used by GICv3. MPIDR and GIC affinity level + * mask is the same. + */ + cpu_aff = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF0_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF1_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF2_SHIFT; + cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) << + GICV3_AFF3_SHIFT; + + addr = gicr_base; + do { + gicr_typer = gicr_read_typer(addr); + + gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) & + GICR_TYPER_AFF_MASK; + if (cpu_aff == gicr_aff) { + /* Disable this print for now as it appears every time + * when using PSCI CPU_SUSPEND. + * TODO: Print this only the first time for each CPU. + * INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at %p\n", + * mpidr, (void *) addr); + */ + return addr; + } + + /* TODO: + * For GICv4 we need to adjust the Base address based on + * GICR_TYPER.VLPIS + */ + addr += (1 << GICR_PCPUBASE_SHIFT); + + } while (!(gicr_typer & GICR_TYPER_LAST)); + + /* If we get here we did not find a match. */ + ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr); + return (uintptr_t)NULL; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v2/gicv2_helpers.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v2/gicv2_helpers.c new file mode 100644 index 0000000..b60a5cd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v2/gicv2_helpers.c @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "../common/gic_common_private.h" +#include "gicv2_private.h" + +/* + * Accessor to read the GIC Distributor ITARGETSR corresponding to the + * interrupt `id`, 4 interrupt IDs at a time. + */ +unsigned int gicd_read_itargetsr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> ITARGETSR_SHIFT; + return mmio_read_32(base + GICD_ITARGETSR + (n << 2)); +} + +/* + * Accessor to read the GIC Distributor CPENDSGIR corresponding to the + * interrupt `id`, 4 interrupt IDs at a time. + */ +unsigned int gicd_read_cpendsgir(uintptr_t base, unsigned int id) +{ + unsigned n = id >> CPENDSGIR_SHIFT; + return mmio_read_32(base + GICD_CPENDSGIR + (n << 2)); +} + +/* + * Accessor to read the GIC Distributor SPENDSGIR corresponding to the + * interrupt `id`, 4 interrupt IDs at a time. + */ +unsigned int gicd_read_spendsgir(uintptr_t base, unsigned int id) +{ + unsigned n = id >> SPENDSGIR_SHIFT; + return mmio_read_32(base + GICD_SPENDSGIR + (n << 2)); +} + +/* + * Accessor to write the GIC Distributor ITARGETSR corresponding to the + * interrupt `id`, 4 interrupt IDs at a time. + */ +void gicd_write_itargetsr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> ITARGETSR_SHIFT; + mmio_write_32(base + GICD_ITARGETSR + (n << 2), val); +} + +/* + * Accessor to write the GIC Distributor CPENDSGIR corresponding to the + * interrupt `id`, 4 interrupt IDs at a time. + */ +void gicd_write_cpendsgir(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> CPENDSGIR_SHIFT; + mmio_write_32(base + GICD_CPENDSGIR + (n << 2), val); +} + +/* + * Accessor to write the GIC Distributor SPENDSGIR corresponding to the + * interrupt `id`, 4 interrupt IDs at a time. + */ +void gicd_write_spendsgir(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> SPENDSGIR_SHIFT; + mmio_write_32(base + GICD_SPENDSGIR + (n << 2), val); +} + +/* + * Accessor to write the GIC Distributor ITARGETSR corresponding to the + * interrupt `id`. + */ +void gicd_set_itargetsr(uintptr_t base, unsigned int id, unsigned int target) +{ + mmio_write_8(base + GICD_ITARGETSR + id, target & GIC_TARGET_CPU_MASK); +} + +/******************************************************************************* + * Get the current CPU bit mask from GICD_ITARGETSR0 + ******************************************************************************/ +unsigned int gicv2_get_cpuif_id(uintptr_t base) +{ + unsigned int val; + + val = gicd_read_itargetsr(base, 0); + return val & GIC_TARGET_CPU_MASK; +} + +/******************************************************************************* + * Helper function to configure the default attributes of SPIs. + ******************************************************************************/ +void gicv2_spis_configure_defaults(uintptr_t gicd_base) +{ + unsigned int index, num_ints; + + num_ints = gicd_read_typer(gicd_base); + num_ints &= TYPER_IT_LINES_NO_MASK; + num_ints = (num_ints + 1) << 5; + + /* + * Treat all SPIs as G1NS by default. The number of interrupts is + * calculated as 32 * (IT_LINES + 1). We do 32 at a time. + */ + for (index = MIN_SPI_ID; index < num_ints; index += 32) + gicd_write_igroupr(gicd_base, index, ~0U); + + /* Setup the default SPI priorities doing four at a time */ + for (index = MIN_SPI_ID; index < num_ints; index += 4) + gicd_write_ipriorityr(gicd_base, + index, + GICD_IPRIORITYR_DEF_VAL); + + /* Treat all SPIs as level triggered by default, 16 at a time */ + for (index = MIN_SPI_ID; index < num_ints; index += 16) + gicd_write_icfgr(gicd_base, index, 0); +} + +/******************************************************************************* + * Helper function to configure secure G0 SPIs. + ******************************************************************************/ +void gicv2_secure_spis_configure(uintptr_t gicd_base, + unsigned int num_ints, + const unsigned int *sec_intr_list) +{ + unsigned int index, irq_num; + + /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ + assert(num_ints ? (uintptr_t)sec_intr_list : 1); + + for (index = 0; index < num_ints; index++) { + irq_num = sec_intr_list[index]; + if (irq_num >= MIN_SPI_ID) { + /* Configure this interrupt as a secure interrupt */ + gicd_clr_igroupr(gicd_base, irq_num); + + /* Set the priority of this interrupt */ + gicd_set_ipriorityr(gicd_base, + irq_num, + GIC_HIGHEST_SEC_PRIORITY); + + /* Target the secure interrupts to primary CPU */ + gicd_set_itargetsr(gicd_base, irq_num, + gicv2_get_cpuif_id(gicd_base)); + + /* Enable this interrupt */ + gicd_set_isenabler(gicd_base, irq_num); + } + } + +} + +/******************************************************************************* + * Helper function to configure secure G0 SGIs and PPIs. + ******************************************************************************/ +void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base, + unsigned int num_ints, + const unsigned int *sec_intr_list) +{ + unsigned int index, irq_num, sec_ppi_sgi_mask = 0; + + /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ + assert(num_ints ? (uintptr_t)sec_intr_list : 1); + + /* + * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a + * more scalable approach as it avoids clearing the enable bits in the + * GICD_CTLR. + */ + gicd_write_icenabler(gicd_base, 0, ~0); + + /* Setup the default PPI/SGI priorities doing four at a time */ + for (index = 0; index < MIN_SPI_ID; index += 4) + gicd_write_ipriorityr(gicd_base, + index, + GICD_IPRIORITYR_DEF_VAL); + + for (index = 0; index < num_ints; index++) { + irq_num = sec_intr_list[index]; + if (irq_num < MIN_SPI_ID) { + /* We have an SGI or a PPI. They are Group0 at reset */ + sec_ppi_sgi_mask |= 1U << irq_num; + + /* Set the priority of this interrupt */ + gicd_set_ipriorityr(gicd_base, + irq_num, + GIC_HIGHEST_SEC_PRIORITY); + } + } + + /* + * Invert the bitmask to create a mask for non-secure PPIs and + * SGIs. Program the GICD_IGROUPR0 with this bit mask. + */ + gicd_write_igroupr(gicd_base, 0, ~sec_ppi_sgi_mask); + + /* Enable the Group 0 SGIs and PPIs */ + gicd_write_isenabler(gicd_base, 0, sec_ppi_sgi_mask); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v2/gicv2_main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v2/gicv2_main.c new file mode 100644 index 0000000..305a8b0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v2/gicv2_main.c @@ -0,0 +1,255 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "../common/gic_common_private.h" +#include "gicv2_private.h" + +static const gicv2_driver_data_t *driver_data; + +/******************************************************************************* + * Enable secure interrupts and use FIQs to route them. Disable legacy bypass + * and set the priority mask register to allow all interrupts to trickle in. + ******************************************************************************/ +void gicv2_cpuif_enable(void) +{ + unsigned int val; + + assert(driver_data); + assert(driver_data->gicc_base); + + /* + * Enable the Group 0 interrupts, FIQEn and disable Group 0/1 + * bypass. + */ + val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0; + val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; + + /* Program the idle priority in the PMR */ + gicc_write_pmr(driver_data->gicc_base, GIC_PRI_MASK); + gicc_write_ctlr(driver_data->gicc_base, val); +} + +/******************************************************************************* + * Place the cpu interface in a state where it can never make a cpu exit wfi as + * as result of an asserted interrupt. This is critical for powering down a cpu + ******************************************************************************/ +void gicv2_cpuif_disable(void) +{ + unsigned int val; + + assert(driver_data); + assert(driver_data->gicc_base); + + /* Disable secure, non-secure interrupts and disable their bypass */ + val = gicc_read_ctlr(driver_data->gicc_base); + val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT); + val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; + val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; + gicc_write_ctlr(driver_data->gicc_base, val); +} + +/******************************************************************************* + * Per cpu gic distributor setup which will be done by all cpus after a cold + * boot/hotplug. This marks out the secure SPIs and PPIs & enables them. + ******************************************************************************/ +void gicv2_pcpu_distif_init(void) +{ + assert(driver_data); + assert(driver_data->gicd_base); + assert(driver_data->g0_interrupt_array); + + gicv2_secure_ppi_sgi_setup(driver_data->gicd_base, + driver_data->g0_interrupt_num, + driver_data->g0_interrupt_array); +} + +/******************************************************************************* + * Global gic distributor init which will be done by the primary cpu after a + * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It + * then enables the secure GIC distributor interface. + ******************************************************************************/ +void gicv2_distif_init(void) +{ + unsigned int ctlr; + + assert(driver_data); + assert(driver_data->gicd_base); + assert(driver_data->g0_interrupt_array); + + /* Disable the distributor before going further */ + ctlr = gicd_read_ctlr(driver_data->gicd_base); + gicd_write_ctlr(driver_data->gicd_base, + ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT)); + + /* Set the default attribute of all SPIs */ + gicv2_spis_configure_defaults(driver_data->gicd_base); + + /* Configure the G0 SPIs */ + gicv2_secure_spis_configure(driver_data->gicd_base, + driver_data->g0_interrupt_num, + driver_data->g0_interrupt_array); + + /* Re-enable the secure SPIs now that they have been configured */ + gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); +} + +/******************************************************************************* + * Initialize the ARM GICv2 driver with the provided platform inputs + ******************************************************************************/ +void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data) +{ + unsigned int gic_version; + assert(plat_driver_data); + assert(plat_driver_data->gicd_base); + assert(plat_driver_data->gicc_base); + + /* + * The platform should provide a list of atleast one type of + * interrupts + */ + assert(plat_driver_data->g0_interrupt_array); + + /* + * If there are no interrupts of a particular type, then the number of + * interrupts of that type should be 0 and vice-versa. + */ + assert(plat_driver_data->g0_interrupt_array ? + plat_driver_data->g0_interrupt_num : + plat_driver_data->g0_interrupt_num == 0); + + /* Ensure that this is a GICv2 system */ + gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); + gic_version = (gic_version >> PIDR2_ARCH_REV_SHIFT) + & PIDR2_ARCH_REV_MASK; + assert(gic_version == ARCH_REV_GICV2); + + driver_data = plat_driver_data; + + INFO("ARM GICv2 driver initialized\n"); +} + +/****************************************************************************** + * This function returns whether FIQ is enabled in the GIC CPU interface. + *****************************************************************************/ +unsigned int gicv2_is_fiq_enabled(void) +{ + unsigned int gicc_ctlr; + + assert(driver_data); + assert(driver_data->gicc_base); + + gicc_ctlr = gicc_read_ctlr(driver_data->gicc_base); + return (gicc_ctlr >> FIQ_EN_SHIFT) & 0x1; +} + +/******************************************************************************* + * This function returns the type of the highest priority pending interrupt at + * the GIC cpu interface. The return values can be one of the following : + * PENDING_G1_INTID : The interrupt type is non secure Group 1. + * 0 - 1019 : The interrupt type is secure Group 0. + * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with + * sufficient priority to be signaled + ******************************************************************************/ +unsigned int gicv2_get_pending_interrupt_type(void) +{ + assert(driver_data); + assert(driver_data->gicc_base); + + return gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; +} + +/******************************************************************************* + * This function returns the id of the highest priority pending interrupt at + * the GIC cpu interface. GIC_SPURIOUS_INTERRUPT is returned when there is no + * interrupt pending. + ******************************************************************************/ +unsigned int gicv2_get_pending_interrupt_id(void) +{ + unsigned int id; + + assert(driver_data); + assert(driver_data->gicc_base); + + id = gicc_read_hppir(driver_data->gicc_base) & INT_ID_MASK; + + /* + * Find out which non-secure interrupt it is under the assumption that + * the GICC_CTLR.AckCtl bit is 0. + */ + if (id == PENDING_G1_INTID) + id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK; + + return id; +} + +/******************************************************************************* + * This functions reads the GIC cpu interface Interrupt Acknowledge register + * to start handling the pending secure 0 interrupt. It returns the + * contents of the IAR. + ******************************************************************************/ +unsigned int gicv2_acknowledge_interrupt(void) +{ + assert(driver_data); + assert(driver_data->gicc_base); + + return gicc_read_IAR(driver_data->gicc_base); +} + +/******************************************************************************* + * This functions writes the GIC cpu interface End Of Interrupt register with + * the passed value to finish handling the active secure group 0 interrupt. + ******************************************************************************/ +void gicv2_end_of_interrupt(unsigned int id) +{ + assert(driver_data); + assert(driver_data->gicc_base); + + gicc_write_EOIR(driver_data->gicc_base, id); +} + +/******************************************************************************* + * This function returns the type of the interrupt id depending upon the group + * this interrupt has been configured under by the interrupt controller i.e. + * group0 secure or group1 non secure. It returns zero for Group 0 secure and + * one for Group 1 non secure interrupt. + ******************************************************************************/ +unsigned int gicv2_get_interrupt_group(unsigned int id) +{ + assert(driver_data); + assert(driver_data->gicd_base); + + return gicd_get_igroupr(driver_data->gicd_base, id); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v2/gicv2_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v2/gicv2_private.h new file mode 100644 index 0000000..6a1ec82 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v2/gicv2_private.h @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GICV2_PRIVATE_H__ +#define __GICV2_PRIVATE_H__ + +#include +#include +#include + +/******************************************************************************* + * Private function prototypes + ******************************************************************************/ +void gicv2_spis_configure_defaults(uintptr_t gicd_base); +void gicv2_secure_spis_configure(uintptr_t gicd_base, + unsigned int num_ints, + const unsigned int *sec_intr_list); +void gicv2_secure_ppi_sgi_setup(uintptr_t gicd_base, + unsigned int num_ints, + const unsigned int *sec_intr_list); +unsigned int gicv2_get_cpuif_id(uintptr_t base); + +/******************************************************************************* + * GIC Distributor interface accessors for reading entire registers + ******************************************************************************/ +static inline unsigned int gicd_read_pidr2(uintptr_t base) +{ + return mmio_read_32(base + GICD_PIDR2_GICV2); +} + +/******************************************************************************* + * GIC CPU interface accessors for reading entire registers + ******************************************************************************/ + +static inline unsigned int gicc_read_ctlr(uintptr_t base) +{ + return mmio_read_32(base + GICC_CTLR); +} + +static inline unsigned int gicc_read_pmr(uintptr_t base) +{ + return mmio_read_32(base + GICC_PMR); +} + +static inline unsigned int gicc_read_BPR(uintptr_t base) +{ + return mmio_read_32(base + GICC_BPR); +} + +static inline unsigned int gicc_read_IAR(uintptr_t base) +{ + return mmio_read_32(base + GICC_IAR); +} + +static inline unsigned int gicc_read_EOIR(uintptr_t base) +{ + return mmio_read_32(base + GICC_EOIR); +} + +static inline unsigned int gicc_read_hppir(uintptr_t base) +{ + return mmio_read_32(base + GICC_HPPIR); +} + +static inline unsigned int gicc_read_ahppir(uintptr_t base) +{ + return mmio_read_32(base + GICC_AHPPIR); +} + +static inline unsigned int gicc_read_dir(uintptr_t base) +{ + return mmio_read_32(base + GICC_DIR); +} + +static inline unsigned int gicc_read_iidr(uintptr_t base) +{ + return mmio_read_32(base + GICC_IIDR); +} + +/******************************************************************************* + * GIC CPU interface accessors for writing entire registers + ******************************************************************************/ + +static inline void gicc_write_ctlr(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_CTLR, val); +} + +static inline void gicc_write_pmr(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_PMR, val); +} + +static inline void gicc_write_BPR(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_BPR, val); +} + + +static inline void gicc_write_IAR(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_IAR, val); +} + +static inline void gicc_write_EOIR(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_EOIR, val); +} + +static inline void gicc_write_hppir(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_HPPIR, val); +} + +static inline void gicc_write_dir(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_DIR, val); +} + +#endif /* __GICV2_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v3/gicv3_helpers.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v3/gicv3_helpers.c new file mode 100644 index 0000000..0a81c86 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v3/gicv3_helpers.c @@ -0,0 +1,425 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "../common/gic_common_private.h" +#include "gicv3_private.h" + +/* + * Accessor to read the GIC Distributor IGRPMODR corresponding to the + * interrupt `id`, 32 interrupt IDs at a time. + */ +unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> IGRPMODR_SHIFT; + return mmio_read_32(base + GICD_IGRPMODR + (n << 2)); +} + +/* + * Accessor to write the GIC Distributor IGRPMODR corresponding to the + * interrupt `id`, 32 interrupt IDs at a time. + */ +void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> IGRPMODR_SHIFT; + mmio_write_32(base + GICD_IGRPMODR + (n << 2), val); +} + +/* + * Accessor to get the bit corresponding to interrupt ID + * in GIC Distributor IGRPMODR. + */ +unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igrpmodr(base, id); + + return (reg_val >> bit_num) & 0x1; +} + +/* + * Accessor to set the bit corresponding to interrupt ID + * in GIC Distributor IGRPMODR. + */ +void gicd_set_igrpmodr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igrpmodr(base, id); + + gicd_write_igrpmodr(base, id, reg_val | (1 << bit_num)); +} + +/* + * Accessor to clear the bit corresponding to interrupt ID + * in GIC Distributor IGRPMODR. + */ +void gicd_clr_igrpmodr(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); + unsigned int reg_val = gicd_read_igrpmodr(base, id); + + gicd_write_igrpmodr(base, id, reg_val & ~(1 << bit_num)); +} + +/* + * Accessor to read the GIC Re-distributor IPRIORITYR corresponding to the + * interrupt `id`, 4 interrupts IDs at a time. + */ +unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id) +{ + unsigned n = id >> IPRIORITYR_SHIFT; + return mmio_read_32(base + GICR_IPRIORITYR + (n << 2)); +} + +/* + * Accessor to write the GIC Re-distributor IPRIORITYR corresponding to the + * interrupt `id`, 4 interrupts IDs at a time. + */ +void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val) +{ + unsigned n = id >> IPRIORITYR_SHIFT; + mmio_write_32(base + GICR_IPRIORITYR + (n << 2), val); +} + +/* + * Accessor to get the bit corresponding to interrupt ID + * from GIC Re-distributor IGROUPR0. + */ +unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicr_read_igroupr0(base); + + return (reg_val >> bit_num) & 0x1; +} + +/* + * Accessor to set the bit corresponding to interrupt ID + * in GIC Re-distributor IGROUPR0. + */ +void gicr_set_igroupr0(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicr_read_igroupr0(base); + + gicr_write_igroupr0(base, reg_val | (1 << bit_num)); +} + +/* + * Accessor to clear the bit corresponding to interrupt ID + * in GIC Re-distributor IGROUPR0. + */ +void gicr_clr_igroupr0(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1); + unsigned int reg_val = gicr_read_igroupr0(base); + + gicr_write_igroupr0(base, reg_val & ~(1 << bit_num)); +} + +/* + * Accessor to get the bit corresponding to interrupt ID + * from GIC Re-distributor IGRPMODR0. + */ +unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); + unsigned int reg_val = gicr_read_igrpmodr0(base); + + return (reg_val >> bit_num) & 0x1; +} + +/* + * Accessor to set the bit corresponding to interrupt ID + * in GIC Re-distributor IGRPMODR0. + */ +void gicr_set_igrpmodr0(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); + unsigned int reg_val = gicr_read_igrpmodr0(base); + + gicr_write_igrpmodr0(base, reg_val | (1 << bit_num)); +} + +/* + * Accessor to clear the bit corresponding to interrupt ID + * in GIC Re-distributor IGRPMODR0. + */ +void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1); + unsigned int reg_val = gicr_read_igrpmodr0(base); + + gicr_write_igrpmodr0(base, reg_val & ~(1 << bit_num)); +} + +/* + * Accessor to set the bit corresponding to interrupt ID + * in GIC Re-distributor ISENABLER0. + */ +void gicr_set_isenabler0(uintptr_t base, unsigned int id) +{ + unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1); + + gicr_write_isenabler0(base, (1 << bit_num)); +} + +/* + * Accessor to set the byte corresponding to interrupt ID + * in GIC Re-distributor IPRIORITYR. + */ +void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri) +{ + mmio_write_8(base + GICR_IPRIORITYR + id, pri & GIC_PRI_MASK); +} + +/****************************************************************************** + * This function marks the core as awake in the re-distributor and + * ensures that the interface is active. + *****************************************************************************/ +void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base) +{ + /* + * The WAKER_PS_BIT should be changed to 0 + * only when WAKER_CA_BIT is 1. + */ + assert(gicr_read_waker(gicr_base) & WAKER_CA_BIT); + + /* Mark the connected core as awake */ + gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT); + + /* Wait till the WAKER_CA_BIT changes to 0 */ + while (gicr_read_waker(gicr_base) & WAKER_CA_BIT) + ; +} + + +/****************************************************************************** + * This function marks the core as asleep in the re-distributor and ensures + * that the interface is quiescent. + *****************************************************************************/ +void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base) +{ + /* Mark the connected core as asleep */ + gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT); + + /* Wait till the WAKER_CA_BIT changes to 1 */ + while (!(gicr_read_waker(gicr_base) & WAKER_CA_BIT)) + ; +} + + +/******************************************************************************* + * This function probes the Redistributor frames when the driver is initialised + * and saves their base addresses. These base addresses are used later to + * initialise each Redistributor interface. + ******************************************************************************/ +void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, + unsigned int rdistif_num, + uintptr_t gicr_base, + mpidr_hash_fn mpidr_to_core_pos) +{ + u_register_t mpidr; + unsigned int proc_num; + unsigned long long typer_val; + uintptr_t rdistif_base = gicr_base; + + assert(rdistif_base_addrs); + + /* + * Iterate over the Redistributor frames. Store the base address of each + * frame in the platform provided array. Use the "Processor Number" + * field to index into the array if the platform has not provided a hash + * function to convert an MPIDR (obtained from the "Affinity Value" + * field into a linear index. + */ + do { + typer_val = gicr_read_typer(rdistif_base); + if (mpidr_to_core_pos) { + mpidr = mpidr_from_gicr_typer(typer_val); + proc_num = mpidr_to_core_pos(mpidr); + } else { + proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) & + TYPER_PROC_NUM_MASK; + } + assert(proc_num < rdistif_num); + rdistif_base_addrs[proc_num] = rdistif_base; + rdistif_base += (1 << GICR_PCPUBASE_SHIFT); + } while (!(typer_val & TYPER_LAST_BIT)); +} + +/******************************************************************************* + * Helper function to configure the default attributes of SPIs. + ******************************************************************************/ +void gicv3_spis_configure_defaults(uintptr_t gicd_base) +{ + unsigned int index, num_ints; + + num_ints = gicd_read_typer(gicd_base); + num_ints &= TYPER_IT_LINES_NO_MASK; + num_ints = (num_ints + 1) << 5; + + /* + * Treat all SPIs as G1NS by default. The number of interrupts is + * calculated as 32 * (IT_LINES + 1). We do 32 at a time. + */ + for (index = MIN_SPI_ID; index < num_ints; index += 32) + gicd_write_igroupr(gicd_base, index, ~0U); + + /* Setup the default SPI priorities doing four at a time */ + for (index = MIN_SPI_ID; index < num_ints; index += 4) + gicd_write_ipriorityr(gicd_base, + index, + GICD_IPRIORITYR_DEF_VAL); + + /* + * Treat all SPIs as level triggered by default, write 16 at + * a time + */ + for (index = MIN_SPI_ID; index < num_ints; index += 16) + gicd_write_icfgr(gicd_base, index, 0); +} + +/******************************************************************************* + * Helper function to configure secure G0 and G1S SPIs. + ******************************************************************************/ +void gicv3_secure_spis_configure(uintptr_t gicd_base, + unsigned int num_ints, + const unsigned int *sec_intr_list, + unsigned int int_grp) +{ + unsigned int index, irq_num; + unsigned long long gic_affinity_val; + + assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0)); + /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ + assert(num_ints ? (uintptr_t)sec_intr_list : 1); + + for (index = 0; index < num_ints; index++) { + irq_num = sec_intr_list[index]; + if (irq_num >= MIN_SPI_ID) { + + /* Configure this interrupt as a secure interrupt */ + gicd_clr_igroupr(gicd_base, irq_num); + + /* Configure this interrupt as G0 or a G1S interrupt */ + if (int_grp == INTR_GROUP1S) + gicd_set_igrpmodr(gicd_base, irq_num); + else + gicd_clr_igrpmodr(gicd_base, irq_num); + + /* Set the priority of this interrupt */ + gicd_set_ipriorityr(gicd_base, + irq_num, + GIC_HIGHEST_SEC_PRIORITY); + + /* Target SPIs to the primary CPU */ + gic_affinity_val = + gicd_irouter_val_from_mpidr(read_mpidr(), 0); + gicd_write_irouter(gicd_base, + irq_num, + gic_affinity_val); + + /* Enable this interrupt */ + gicd_set_isenabler(gicd_base, irq_num); + } + } + +} + +/******************************************************************************* + * Helper function to configure the default attributes of SPIs. + ******************************************************************************/ +void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base) +{ + unsigned int index; + + /* + * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a + * more scalable approach as it avoids clearing the enable bits in the + * GICD_CTLR + */ + gicr_write_icenabler0(gicr_base, ~0); + gicr_wait_for_pending_write(gicr_base); + + /* Treat all SGIs/PPIs as G1NS by default. */ + gicr_write_igroupr0(gicr_base, ~0U); + + /* Setup the default PPI/SGI priorities doing four at a time */ + for (index = 0; index < MIN_SPI_ID; index += 4) + gicr_write_ipriorityr(gicr_base, + index, + GICD_IPRIORITYR_DEF_VAL); + + /* Configure all PPIs as level triggered by default */ + gicr_write_icfgr1(gicr_base, 0); +} + +/******************************************************************************* + * Helper function to configure secure G0 and G1S SPIs. + ******************************************************************************/ +void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base, + unsigned int num_ints, + const unsigned int *sec_intr_list, + unsigned int int_grp) +{ + unsigned int index, irq_num; + + assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0)); + /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ + assert(num_ints ? (uintptr_t)sec_intr_list : 1); + + for (index = 0; index < num_ints; index++) { + irq_num = sec_intr_list[index]; + if (irq_num < MIN_SPI_ID) { + + /* Configure this interrupt as a secure interrupt */ + gicr_clr_igroupr0(gicr_base, irq_num); + + /* Configure this interrupt as G0 or a G1S interrupt */ + if (int_grp == INTR_GROUP1S) + gicr_set_igrpmodr0(gicr_base, irq_num); + else + gicr_clr_igrpmodr0(gicr_base, irq_num); + + /* Set the priority of this interrupt */ + gicr_set_ipriorityr(gicr_base, + irq_num, + GIC_HIGHEST_SEC_PRIORITY); + + /* Enable this interrupt */ + gicr_set_isenabler0(gicr_base, irq_num); + } + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v3/gicv3_main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v3/gicv3_main.c new file mode 100644 index 0000000..ac43372 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v3/gicv3_main.c @@ -0,0 +1,397 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "../common/gic_common_private.h" +#include "gicv3_private.h" + +static const gicv3_driver_data_t *driver_data; +static unsigned int gicv2_compat; + +/******************************************************************************* + * This function initialises the ARM GICv3 driver in EL3 with provided platform + * inputs. + ******************************************************************************/ +void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data) +{ + unsigned int gic_version; + + assert(plat_driver_data); + assert(plat_driver_data->gicd_base); + assert(plat_driver_data->gicr_base); + assert(plat_driver_data->rdistif_num); + assert(plat_driver_data->rdistif_base_addrs); + + assert(IS_IN_EL3()); + + /* + * The platform should provide a list of at least one type of + * interrupts + */ + assert(plat_driver_data->g0_interrupt_array || + plat_driver_data->g1s_interrupt_array); + + /* + * If there are no interrupts of a particular type, then the number of + * interrupts of that type should be 0 and vice-versa. + */ + assert(plat_driver_data->g0_interrupt_array ? + plat_driver_data->g0_interrupt_num : + plat_driver_data->g0_interrupt_num == 0); + assert(plat_driver_data->g1s_interrupt_array ? + plat_driver_data->g1s_interrupt_num : + plat_driver_data->g1s_interrupt_num == 0); + + /* Check for system register support */ +#ifdef AARCH32 + assert(read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)); +#else + assert(read_id_aa64pfr0_el1() & + (ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)); +#endif /* AARCH32 */ + + /* The GIC version should be 3.0 */ + gic_version = gicd_read_pidr2(plat_driver_data->gicd_base); + gic_version >>= PIDR2_ARCH_REV_SHIFT; + gic_version &= PIDR2_ARCH_REV_MASK; + assert(gic_version == ARCH_REV_GICV3); + + /* + * Find out whether the GIC supports the GICv2 compatibility mode. The + * ARE_S bit resets to 0 if supported + */ + gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base); + gicv2_compat >>= CTLR_ARE_S_SHIFT; + gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK); + + /* + * Find the base address of each implemented Redistributor interface. + * The number of interfaces should be equal to the number of CPUs in the + * system. The memory for saving these addresses has to be allocated by + * the platform port + */ + gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs, + plat_driver_data->rdistif_num, + plat_driver_data->gicr_base, + plat_driver_data->mpidr_to_core_pos); + + driver_data = plat_driver_data; + + INFO("GICv3 %s legacy support detected." + " ARM GICV3 driver initialized in EL3\n", + gicv2_compat ? "with" : "without"); +} + +/******************************************************************************* + * This function initialises the GIC distributor interface based upon the data + * provided by the platform while initialising the driver. + ******************************************************************************/ +void gicv3_distif_init(void) +{ + unsigned int bitmap = 0; + + assert(driver_data); + assert(driver_data->gicd_base); + assert(driver_data->g1s_interrupt_array || + driver_data->g0_interrupt_array); + + assert(IS_IN_EL3()); + + /* + * Clear the "enable" bits for G0/G1S/G1NS interrupts before configuring + * the ARE_S bit. The Distributor might generate a system error + * otherwise. + */ + gicd_clr_ctlr(driver_data->gicd_base, + CTLR_ENABLE_G0_BIT | + CTLR_ENABLE_G1S_BIT | + CTLR_ENABLE_G1NS_BIT, + RWP_TRUE); + + /* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */ + gicd_set_ctlr(driver_data->gicd_base, + CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE); + + /* Set the default attribute of all SPIs */ + gicv3_spis_configure_defaults(driver_data->gicd_base); + + /* Configure the G1S SPIs */ + if (driver_data->g1s_interrupt_array) { + gicv3_secure_spis_configure(driver_data->gicd_base, + driver_data->g1s_interrupt_num, + driver_data->g1s_interrupt_array, + INTR_GROUP1S); + bitmap |= CTLR_ENABLE_G1S_BIT; + } + + /* Configure the G0 SPIs */ + if (driver_data->g0_interrupt_array) { + gicv3_secure_spis_configure(driver_data->gicd_base, + driver_data->g0_interrupt_num, + driver_data->g0_interrupt_array, + INTR_GROUP0); + bitmap |= CTLR_ENABLE_G0_BIT; + } + + /* Enable the secure SPIs now that they have been configured */ + gicd_set_ctlr(driver_data->gicd_base, bitmap, RWP_TRUE); +} + +/******************************************************************************* + * This function initialises the GIC Redistributor interface of the calling CPU + * (identified by the 'proc_num' parameter) based upon the data provided by the + * platform while initialising the driver. + ******************************************************************************/ +void gicv3_rdistif_init(unsigned int proc_num) +{ + uintptr_t gicr_base; + + assert(driver_data); + assert(proc_num < driver_data->rdistif_num); + assert(driver_data->rdistif_base_addrs); + assert(driver_data->gicd_base); + assert(gicd_read_ctlr(driver_data->gicd_base) & CTLR_ARE_S_BIT); + assert(driver_data->g1s_interrupt_array || + driver_data->g0_interrupt_array); + + assert(IS_IN_EL3()); + + gicr_base = driver_data->rdistif_base_addrs[proc_num]; + + /* Set the default attribute of all SGIs and PPIs */ + gicv3_ppi_sgi_configure_defaults(gicr_base); + + /* Configure the G1S SGIs/PPIs */ + if (driver_data->g1s_interrupt_array) { + gicv3_secure_ppi_sgi_configure(gicr_base, + driver_data->g1s_interrupt_num, + driver_data->g1s_interrupt_array, + INTR_GROUP1S); + } + + /* Configure the G0 SGIs/PPIs */ + if (driver_data->g0_interrupt_array) { + gicv3_secure_ppi_sgi_configure(gicr_base, + driver_data->g0_interrupt_num, + driver_data->g0_interrupt_array, + INTR_GROUP0); + } +} + +/******************************************************************************* + * This function enables the GIC CPU interface of the calling CPU using only + * system register accesses. + ******************************************************************************/ +void gicv3_cpuif_enable(unsigned int proc_num) +{ + uintptr_t gicr_base; + unsigned int scr_el3; + unsigned int icc_sre_el3; + + assert(driver_data); + assert(proc_num < driver_data->rdistif_num); + assert(driver_data->rdistif_base_addrs); + assert(IS_IN_EL3()); + + /* Mark the connected core as awake */ + gicr_base = driver_data->rdistif_base_addrs[proc_num]; + gicv3_rdistif_mark_core_awake(gicr_base); + + /* Disable the legacy interrupt bypass */ + icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT; + + /* + * Enable system register access for EL3 and allow lower exception + * levels to configure the same for themselves. If the legacy mode is + * not supported, the SRE bit is RAO/WI + */ + icc_sre_el3 |= (ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT); + write_icc_sre_el3(read_icc_sre_el3() | icc_sre_el3); + + scr_el3 = read_scr_el3(); + + /* + * Switch to NS state to write Non secure ICC_SRE_EL1 and + * ICC_SRE_EL2 registers. + */ + write_scr_el3(scr_el3 | SCR_NS_BIT); + isb(); + + write_icc_sre_el2(read_icc_sre_el2() | icc_sre_el3); + write_icc_sre_el1(ICC_SRE_SRE_BIT); + isb(); + + /* Switch to secure state. */ + write_scr_el3(scr_el3 & (~SCR_NS_BIT)); + isb(); + + /* Program the idle priority in the PMR */ + write_icc_pmr_el1(GIC_PRI_MASK); + + /* Enable Group0 interrupts */ + write_icc_igrpen0_el1(IGRPEN1_EL1_ENABLE_G0_BIT); + + /* Enable Group1 Secure interrupts */ + write_icc_igrpen1_el3(read_icc_igrpen1_el3() | + IGRPEN1_EL3_ENABLE_G1S_BIT); + + /* Write the secure ICC_SRE_EL1 register */ + write_icc_sre_el1(ICC_SRE_SRE_BIT); + isb(); +} + +/******************************************************************************* + * This function disables the GIC CPU interface of the calling CPU using + * only system register accesses. + ******************************************************************************/ +void gicv3_cpuif_disable(unsigned int proc_num) +{ + uintptr_t gicr_base; + + assert(driver_data); + assert(proc_num < driver_data->rdistif_num); + assert(driver_data->rdistif_base_addrs); + + assert(IS_IN_EL3()); + + /* Disable legacy interrupt bypass */ + write_icc_sre_el3(read_icc_sre_el3() | + (ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)); + + /* Disable Group0 interrupts */ + write_icc_igrpen0_el1(read_icc_igrpen0_el1() & + ~IGRPEN1_EL1_ENABLE_G0_BIT); + + /* Disable Group1 Secure and Non-Secure interrupts */ + write_icc_igrpen1_el3(read_icc_igrpen1_el3() & + ~(IGRPEN1_EL3_ENABLE_G1NS_BIT | + IGRPEN1_EL3_ENABLE_G1S_BIT)); + + /* Synchronise accesses to group enable registers */ + isb(); + + /* Mark the connected core as asleep */ + gicr_base = driver_data->rdistif_base_addrs[proc_num]; + gicv3_rdistif_mark_core_asleep(gicr_base); +} + +/******************************************************************************* + * This function returns the id of the highest priority pending interrupt at + * the GIC cpu interface. + ******************************************************************************/ +unsigned int gicv3_get_pending_interrupt_id(void) +{ + unsigned int id; + + assert(IS_IN_EL3()); + id = read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; + + /* + * If the ID is special identifier corresponding to G1S or G1NS + * interrupt, then read the highest pending group 1 interrupt. + */ + if ((id == PENDING_G1S_INTID) || (id == PENDING_G1NS_INTID)) + return read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK; + + return id; +} + +/******************************************************************************* + * This function returns the type of the highest priority pending interrupt at + * the GIC cpu interface. The return values can be one of the following : + * PENDING_G1S_INTID : The interrupt type is secure Group 1. + * PENDING_G1NS_INTID : The interrupt type is non secure Group 1. + * 0 - 1019 : The interrupt type is secure Group 0. + * GIC_SPURIOUS_INTERRUPT : there is no pending interrupt with + * sufficient priority to be signaled + ******************************************************************************/ +unsigned int gicv3_get_pending_interrupt_type(void) +{ + assert(IS_IN_EL3()); + return read_icc_hppir0_el1() & HPPIR0_EL1_INTID_MASK; +} + +/******************************************************************************* + * This function returns the type of the interrupt id depending upon the group + * this interrupt has been configured under by the interrupt controller i.e. + * group0 or group1 Secure / Non Secure. The return value can be one of the + * following : + * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt + * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt + * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure + * interrupt. + ******************************************************************************/ +unsigned int gicv3_get_interrupt_type(unsigned int id, + unsigned int proc_num) +{ + unsigned int igroup, grpmodr; + uintptr_t gicr_base; + + assert(IS_IN_EL3()); + assert(driver_data); + + /* Ensure the parameters are valid */ + assert(id < PENDING_G1S_INTID || id >= MIN_LPI_ID); + assert(proc_num < driver_data->rdistif_num); + + /* All LPI interrupts are Group 1 non secure */ + if (id >= MIN_LPI_ID) + return INTR_GROUP1NS; + + if (id < MIN_SPI_ID) { + assert(driver_data->rdistif_base_addrs); + gicr_base = driver_data->rdistif_base_addrs[proc_num]; + igroup = gicr_get_igroupr0(gicr_base, id); + grpmodr = gicr_get_igrpmodr0(gicr_base, id); + } else { + assert(driver_data->gicd_base); + igroup = gicd_get_igroupr(driver_data->gicd_base, id); + grpmodr = gicd_get_igrpmodr(driver_data->gicd_base, id); + } + + /* + * If the IGROUP bit is set, then it is a Group 1 Non secure + * interrupt + */ + if (igroup) + return INTR_GROUP1NS; + + /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ + if (grpmodr) + return INTR_GROUP1S; + + /* Else it is a Group 0 Secure interrupt */ + return INTR_GROUP0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v3/gicv3_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v3/gicv3_private.h new file mode 100644 index 0000000..1344a88 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/gic/v3/gicv3_private.h @@ -0,0 +1,256 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GICV3_PRIVATE_H__ +#define __GICV3_PRIVATE_H__ + +#include +#include +#include + +/******************************************************************************* + * GICv3 private macro definitions + ******************************************************************************/ + +/* Constants to indicate the status of the RWP bit */ +#define RWP_TRUE 1 +#define RWP_FALSE 0 + +/* + * Macro to wait for updates to : + * GICD_CTLR[2:0] - the Group Enables + * GICD_CTLR[5:4] - the ARE bits + * GICD_ICENABLERn - the clearing of enable state for SPIs + */ +#define gicd_wait_for_pending_write(gicd_base) \ + do { \ + ; \ + } while (gicd_read_ctlr(gicd_base) & GICD_CTLR_RWP_BIT) + +/* + * Macro to convert an mpidr to a value suitable for programming into a + * GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant + * to GICv3. + */ +#define gicd_irouter_val_from_mpidr(mpidr, irm) \ + ((mpidr & ~(0xff << 24)) | \ + (irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT) + +/* + * Macro to wait for updates to : + * GICR_ICENABLER0 + * GICR_CTLR.DPG1S + * GICR_CTLR.DPG1NS + * GICR_CTLR.DPG0 + */ +#define gicr_wait_for_pending_write(gicr_base) \ + do { \ + ; \ + } while (gicr_read_ctlr(gicr_base) & GICR_CTLR_RWP_BIT) + +/* + * Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24] + * are zeroes. + */ +#ifdef AARCH32 +#define mpidr_from_gicr_typer(typer_val) (((typer_val) >> 32) & 0xffffff) +#else +#define mpidr_from_gicr_typer(typer_val) \ + (((((typer_val) >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \ + (((typer_val) >> 32) & 0xffffff)) +#endif + +/******************************************************************************* + * Private GICv3 function prototypes for accessing entire registers. + * Note: The raw register values correspond to multiple interrupt IDs and + * the number of interrupt IDs involved depends on the register accessed. + ******************************************************************************/ +unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id); +unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id); +void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val); +void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val); + +/******************************************************************************* + * Private GICv3 function prototypes for accessing the GIC registers + * corresponding to a single interrupt ID. These functions use bitwise + * operations or appropriate register accesses to modify or return + * the bit-field corresponding the single interrupt ID. + ******************************************************************************/ +unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id); +unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id); +unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id); +void gicd_set_igrpmodr(uintptr_t base, unsigned int id); +void gicr_set_igrpmodr0(uintptr_t base, unsigned int id); +void gicr_set_isenabler0(uintptr_t base, unsigned int id); +void gicr_set_igroupr0(uintptr_t base, unsigned int id); +void gicd_clr_igrpmodr(uintptr_t base, unsigned int id); +void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id); +void gicr_clr_igroupr0(uintptr_t base, unsigned int id); +void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri); + +/******************************************************************************* + * Private GICv3 helper function prototypes + ******************************************************************************/ +void gicv3_spis_configure_defaults(uintptr_t gicd_base); +void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base); +void gicv3_secure_spis_configure(uintptr_t gicd_base, + unsigned int num_ints, + const unsigned int *sec_intr_list, + unsigned int int_grp); +void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base, + unsigned int num_ints, + const unsigned int *sec_intr_list, + unsigned int int_grp); +void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs, + unsigned int rdistif_num, + uintptr_t gicr_base, + mpidr_hash_fn mpidr_to_core_pos); +void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base); +void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base); + +/******************************************************************************* + * GIC Distributor interface accessors + ******************************************************************************/ +static inline unsigned int gicd_read_pidr2(uintptr_t base) +{ + return mmio_read_32(base + GICD_PIDR2_GICV3); +} + +static inline unsigned long long gicd_read_irouter(uintptr_t base, unsigned int id) +{ + assert(id >= MIN_SPI_ID); + return mmio_read_64(base + GICD_IROUTER + (id << 3)); +} + +static inline void gicd_write_irouter(uintptr_t base, + unsigned int id, + unsigned long long affinity) +{ + assert(id >= MIN_SPI_ID); + mmio_write_64(base + GICD_IROUTER + (id << 3), affinity); +} + +static inline void gicd_clr_ctlr(uintptr_t base, + unsigned int bitmap, + unsigned int rwp) +{ + gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); + if (rwp) + gicd_wait_for_pending_write(base); +} + +static inline void gicd_set_ctlr(uintptr_t base, + unsigned int bitmap, + unsigned int rwp) +{ + gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); + if (rwp) + gicd_wait_for_pending_write(base); +} + +/******************************************************************************* + * GIC Redistributor interface accessors + ******************************************************************************/ +static inline unsigned long long gicr_read_ctlr(uintptr_t base) +{ + return mmio_read_64(base + GICR_CTLR); +} + +static inline unsigned long long gicr_read_typer(uintptr_t base) +{ + return mmio_read_64(base + GICR_TYPER); +} + +static inline unsigned int gicr_read_waker(uintptr_t base) +{ + return mmio_read_32(base + GICR_WAKER); +} + +static inline void gicr_write_waker(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICR_WAKER, val); +} + +/******************************************************************************* + * GIC Re-distributor functions for accessing entire registers. + * Note: The raw register values correspond to multiple interrupt IDs and + * the number of interrupt IDs involved depends on the register accessed. + ******************************************************************************/ +static inline unsigned int gicr_read_icenabler0(uintptr_t base) +{ + return mmio_read_32(base + GICR_ICENABLER0); +} + +static inline void gicr_write_icenabler0(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICR_ICENABLER0, val); +} + +static inline unsigned int gicr_read_isenabler0(uintptr_t base) +{ + return mmio_read_32(base + GICR_ISENABLER0); +} + +static inline void gicr_write_isenabler0(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICR_ISENABLER0, val); +} + +static inline unsigned int gicr_read_igroupr0(uintptr_t base) +{ + return mmio_read_32(base + GICR_IGROUPR0); +} + +static inline void gicr_write_igroupr0(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICR_IGROUPR0, val); +} + +static inline unsigned int gicr_read_igrpmodr0(uintptr_t base) +{ + return mmio_read_32(base + GICR_IGRPMODR0); +} + +static inline void gicr_write_igrpmodr0(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICR_IGRPMODR0, val); +} + +static inline unsigned int gicr_read_icfgr1(uintptr_t base) +{ + return mmio_read_32(base + GICR_ICFGR1); +} + +static inline void gicr_write_icfgr1(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICR_ICFGR1, val); +} + +#endif /* __GICV3_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/pl011/aarch32/pl011_console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/pl011/aarch32/pl011_console.S new file mode 100644 index 0000000..21ed7ab --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/pl011/aarch32/pl011_console.S @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +/* + * Pull in generic functions to provide backwards compatibility for + * platform makefiles + */ +#include "../../../console/aarch32/console.S" + + .globl console_core_init + .globl console_core_putc + .globl console_core_getc + + + /* ----------------------------------------------- + * int console_core_init(uintptr_t base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * In: r0 - console base address + * r1 - Uart clock in Hz + * r2 - Baud rate + * Out: return 1 on success else 0 on error + * Clobber list : r1, r2, r3 + * ----------------------------------------------- + */ +func console_core_init + /* Check the input base address */ + cmp r0, #0 + beq core_init_fail +#if !PL011_GENERIC_UART + /* Check baud rate and uart clock for sanity */ + cmp r1, #0 + beq core_init_fail + cmp r2, #0 + beq core_init_fail + /* Disable the UART before initialization */ + ldr r3, [r0, #UARTCR] + bic r3, r3, #PL011_UARTCR_UARTEN + str r3, [r0, #UARTCR] + /* Program the baudrate */ + /* Divisor = (Uart clock * 4) / baudrate */ + lsl r1, r1, #2 + udiv r2, r1, r2 + /* IBRD = Divisor >> 6 */ + lsr r1, r2, #6 + /* Write the IBRD */ + str r1, [r0, #UARTIBRD] + /* FBRD = Divisor & 0x3F */ + and r1, r2, #0x3f + /* Write the FBRD */ + str r1, [r0, #UARTFBRD] + mov r1, #PL011_LINE_CONTROL + str r1, [r0, #UARTLCR_H] + /* Clear any pending errors */ + mov r1, #0 + str r1, [r0, #UARTECR] + /* Enable tx, rx, and uart overall */ + ldr r1, =(PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN) + str r1, [r0, #UARTCR] +#endif + mov r0, #1 + bx lr +core_init_fail: + mov r0, #0 + bx lr +endfunc console_core_init + + /* -------------------------------------------------------- + * int console_core_putc(int c, uintptr_t base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : r0 - character to be printed + * r1 - console base address + * Out : return -1 on error else return character. + * Clobber list : r2 + * -------------------------------------------------------- + */ +func console_core_putc + /* Check the input parameter */ + cmp r1, #0 + beq putc_error + /* Prepend '\r' to '\n' */ + cmp r0, #0xA + bne 2f +1: + /* Check if the transmit FIFO is full */ + ldr r2, [r1, #UARTFR] + tst r2, #PL011_UARTFR_TXFF_BIT + beq 1b + mov r2, #0xD + str r2, [r1, #UARTDR] +2: + /* Check if the transmit FIFO is full */ + ldr r2, [r1, #UARTFR] + tst r2, #PL011_UARTFR_TXFF_BIT + beq 2b + str r0, [r1, #UARTDR] + bx lr +putc_error: + mov r0, #-1 + bx lr +endfunc console_core_putc + + /* --------------------------------------------- + * int console_core_getc(uintptr_t base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * In : r0 - console base address + * Clobber list : r0, r1 + * --------------------------------------------- + */ +func console_core_getc + cmp r0, #0 + beq getc_error +1: + /* Check if the receive FIFO is empty */ + ldr r1, [r0, #UARTFR] + tst r1, #PL011_UARTFR_RXFE_BIT + beq 1b + ldr r1, [r0, #UARTDR] + mov r0, r1 + bx lr +getc_error: + mov r0, #-1 + bx lr +endfunc console_core_getc diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/pl011/aarch64/pl011_console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/pl011/aarch64/pl011_console.S new file mode 100644 index 0000000..11e3df7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/pl011/aarch64/pl011_console.S @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +/* + * Pull in generic functions to provide backwards compatibility for + * platform makefiles + */ +#include "../../../console/aarch64/console.S" + + + .globl console_core_init + .globl console_core_putc + .globl console_core_getc + + + /* ----------------------------------------------- + * int console_core_init(uintptr_t base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * Out: return 1 on success else 0 on error + * Clobber list : x1, x2, x3, x4 + * ----------------------------------------------- + */ +func console_core_init + /* Check the input base address */ + cbz x0, core_init_fail +#if !PL011_GENERIC_UART + /* Check baud rate and uart clock for sanity */ + cbz w1, core_init_fail + cbz w2, core_init_fail + /* Disable uart before programming */ + ldr w3, [x0, #UARTCR] + mov w4, #PL011_UARTCR_UARTEN + bic w3, w3, w4 + str w3, [x0, #UARTCR] + /* Program the baudrate */ + /* Divisor = (Uart clock * 4) / baudrate */ + lsl w1, w1, #2 + udiv w2, w1, w2 + /* IBRD = Divisor >> 6 */ + lsr w1, w2, #6 + /* Write the IBRD */ + str w1, [x0, #UARTIBRD] + /* FBRD = Divisor & 0x3F */ + and w1, w2, #0x3f + /* Write the FBRD */ + str w1, [x0, #UARTFBRD] + mov w1, #PL011_LINE_CONTROL + str w1, [x0, #UARTLCR_H] + /* Clear any pending errors */ + str wzr, [x0, #UARTECR] + /* Enable tx, rx, and uart overall */ + mov w1, #(PL011_UARTCR_RXE | PL011_UARTCR_TXE | PL011_UARTCR_UARTEN) + str w1, [x0, #UARTCR] +#endif + mov w0, #1 + ret +core_init_fail: + mov w0, wzr + ret +endfunc console_core_init + + /* -------------------------------------------------------- + * int console_core_putc(int c, uintptr_t base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_core_putc + /* Check the input parameter */ + cbz x1, putc_error + /* Prepend '\r' to '\n' */ + cmp w0, #0xA + b.ne 2f +1: + /* Check if the transmit FIFO is full */ + ldr w2, [x1, #UARTFR] + tbnz w2, #PL011_UARTFR_TXFF_BIT, 1b + mov w2, #0xD + str w2, [x1, #UARTDR] +2: + /* Check if the transmit FIFO is full */ + ldr w2, [x1, #UARTFR] + tbnz w2, #PL011_UARTFR_TXFF_BIT, 2b + str w0, [x1, #UARTDR] + ret +putc_error: + mov w0, #-1 + ret +endfunc console_core_putc + + /* --------------------------------------------- + * int console_core_getc(uintptr_t base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * In : x0 - console base address + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_getc + cbz x0, getc_error +1: + /* Check if the receive FIFO is empty */ + ldr w1, [x0, #UARTFR] + tbnz w1, #PL011_UARTFR_RXFE_BIT, 1b + ldr w1, [x0, #UARTDR] + mov w0, w1 + ret +getc_error: + mov w0, #-1 + ret +endfunc console_core_getc diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/pl011/pl011_console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/pl011/pl011_console.S new file mode 100644 index 0000000..44aafc2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/pl011/pl011_console.S @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#if !ERROR_DEPRECATED +#include "./aarch64/pl011_console.S" +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/pl061/pl061_gpio.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/pl061/pl061_gpio.c new file mode 100644 index 0000000..fca0056 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/pl061/pl061_gpio.c @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * ARM PL061 GPIO Driver. + * Reference to ARM DDI 0190B document. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#if !PLAT_PL061_MAX_GPIOS +# define PLAT_PL061_MAX_GPIOS 32 +#endif /* PLAT_PL061_MAX_GPIOS */ + +CASSERT(PLAT_PL061_MAX_GPIOS > 0, assert_plat_pl061_max_gpios); + +#define MAX_GPIO_DEVICES ((PLAT_PL061_MAX_GPIOS + \ + (GPIOS_PER_PL061 - 1)) / GPIOS_PER_PL061) + +#define PL061_GPIO_DIR 0x400 + +#define GPIOS_PER_PL061 8 +#define BIT(nr) (1UL << (nr)) + +static int pl061_get_direction(int gpio); +static void pl061_set_direction(int gpio, int direction); +static int pl061_get_value(int gpio); +static void pl061_set_value(int gpio, int value); + +static uintptr_t pl061_reg_base[MAX_GPIO_DEVICES]; + +static const gpio_ops_t pl061_gpio_ops = { + .get_direction = pl061_get_direction, + .set_direction = pl061_set_direction, + .get_value = pl061_get_value, + .set_value = pl061_set_value, +}; + +static int pl061_get_direction(int gpio) +{ + uintptr_t base_addr; + unsigned int data, offset; + + assert((gpio >= 0) && (gpio < PLAT_PL061_MAX_GPIOS)); + + base_addr = pl061_reg_base[gpio / GPIOS_PER_PL061]; + offset = gpio % GPIOS_PER_PL061; + data = mmio_read_8(base_addr + PL061_GPIO_DIR); + if (data & BIT(offset)) + return GPIO_DIR_OUT; + return GPIO_DIR_IN; +} + +static void pl061_set_direction(int gpio, int direction) +{ + uintptr_t base_addr; + unsigned int data, offset; + + assert((gpio >= 0) && (gpio < PLAT_PL061_MAX_GPIOS)); + + base_addr = pl061_reg_base[gpio / GPIOS_PER_PL061]; + offset = gpio % GPIOS_PER_PL061; + if (direction == GPIO_DIR_OUT) { + data = mmio_read_8(base_addr + PL061_GPIO_DIR) | BIT(offset); + mmio_write_8(base_addr + PL061_GPIO_DIR, data); + } else { + data = mmio_read_8(base_addr + PL061_GPIO_DIR) & ~BIT(offset); + mmio_write_8(base_addr + PL061_GPIO_DIR, data); + } +} + +/* + * The offset of GPIODATA register is 0. + * The values read from GPIODATA are determined for each bit, by the mask bit + * derived from the address used to access the data register, PADDR[9:2]. + * Bits that are 1 in the address mask cause the corresponding bits in GPIODATA + * to be read, and bits that are 0 in the address mask cause the corresponding + * bits in GPIODATA to be read as 0, regardless of their value. + */ +static int pl061_get_value(int gpio) +{ + uintptr_t base_addr; + unsigned int offset; + + assert((gpio >= 0) && (gpio < PLAT_PL061_MAX_GPIOS)); + + base_addr = pl061_reg_base[gpio / GPIOS_PER_PL061]; + offset = gpio % GPIOS_PER_PL061; + if (mmio_read_8(base_addr + BIT(offset + 2))) + return GPIO_LEVEL_HIGH; + return GPIO_LEVEL_LOW; +} + +/* + * In order to write GPIODATA, the corresponding bits in the mask, resulting + * from the address bus, PADDR[9:2], must be HIGH. Otherwise the bit values + * remain unchanged by the write. + */ +static void pl061_set_value(int gpio, int value) +{ + uintptr_t base_addr; + int offset; + + assert((gpio >= 0) && (gpio < PLAT_PL061_MAX_GPIOS)); + + base_addr = pl061_reg_base[gpio / GPIOS_PER_PL061]; + offset = gpio % GPIOS_PER_PL061; + if (value == GPIO_LEVEL_HIGH) + mmio_write_8(base_addr + BIT(offset + 2), BIT(offset)); + else + mmio_write_8(base_addr + BIT(offset + 2), 0); +} + + +/* + * Register the PL061 GPIO controller with a base address and the offset + * of start pin in this GPIO controller. + * This function is called after pl061_gpio_ops_init(). + */ +void pl061_gpio_register(uintptr_t base_addr, int gpio_dev) +{ + assert((gpio_dev >= 0) && (gpio_dev < MAX_GPIO_DEVICES)); + + pl061_reg_base[gpio_dev] = base_addr; +} + +/* + * Initialize PL061 GPIO controller with the total GPIO numbers in SoC. + */ +void pl061_gpio_init(void) +{ + gpio_init(&pl061_gpio_ops); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/sp804/sp804_delay_timer.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/sp804/sp804_delay_timer.c new file mode 100644 index 0000000..78940bf --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/sp804/sp804_delay_timer.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +uintptr_t sp804_base_addr; + +#define SP804_TIMER1_LOAD (sp804_base_addr + 0x000) +#define SP804_TIMER1_VALUE (sp804_base_addr + 0x004) +#define SP804_TIMER1_CONTROL (sp804_base_addr + 0x008) +#define SP804_TIMER1_BGLOAD (sp804_base_addr + 0x018) + +#define TIMER_CTRL_ONESHOT (1 << 0) +#define TIMER_CTRL_32BIT (1 << 1) +#define TIMER_CTRL_DIV1 (0 << 2) +#define TIMER_CTRL_DIV16 (1 << 2) +#define TIMER_CTRL_DIV256 (2 << 2) +#define TIMER_CTRL_IE (1 << 5) +#define TIMER_CTRL_PERIODIC (1 << 6) +#define TIMER_CTRL_ENABLE (1 << 7) + +/******************************************************************** + * The SP804 timer delay function + ********************************************************************/ +uint32_t sp804_get_timer_value(void) +{ + return mmio_read_32(SP804_TIMER1_VALUE); +} + +/******************************************************************** + * Initialize the 1st timer in the SP804 dual timer with a base + * address and a timer ops + ********************************************************************/ +void sp804_timer_ops_init(uintptr_t base_addr, const timer_ops_t *ops) +{ + assert(base_addr != 0); + assert(ops != 0 && ops->get_timer_value == sp804_get_timer_value); + + sp804_base_addr = base_addr; + timer_init(ops); + + /* disable timer1 */ + mmio_write_32(SP804_TIMER1_CONTROL, 0); + mmio_write_32(SP804_TIMER1_LOAD, UINT32_MAX); + mmio_write_32(SP804_TIMER1_VALUE, UINT32_MAX); + + /* enable as a free running 32-bit counter */ + mmio_write_32(SP804_TIMER1_CONTROL, + TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/sp805/sp805.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/sp805/sp805.c new file mode 100644 index 0000000..4886e01 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/sp805/sp805.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/* Inline register access functions */ + +static inline void sp805_write_wdog_load(uintptr_t base, unsigned long value) +{ + mmio_write_32(base + SP805_WDOG_LOAD_OFF, value); +} + +static inline void sp805_write_wdog_ctrl(uintptr_t base, unsigned long value) +{ + mmio_write_32(base + SP805_WDOG_CTR_OFF, value); +} + +static inline void sp805_write_wdog_lock(uintptr_t base, unsigned long value) +{ + mmio_write_32(base + SP805_WDOG_LOCK_OFF, value); +} + + +/* Public API implementation */ + +void sp805_start(uintptr_t base, unsigned long ticks) +{ + sp805_write_wdog_load(base, ticks); + sp805_write_wdog_ctrl(base, SP805_CTR_RESEN | SP805_CTR_INTEN); + /* Lock registers access */ + sp805_write_wdog_lock(base, 0); +} + +void sp805_stop(uintptr_t base) +{ + sp805_write_wdog_lock(base, WDOG_UNLOCK_KEY); + sp805_write_wdog_ctrl(base, 0); +} + +void sp805_refresh(uintptr_t base, unsigned long ticks) +{ + sp805_write_wdog_lock(base, WDOG_UNLOCK_KEY); + sp805_write_wdog_load(base, ticks); + sp805_write_wdog_lock(base, 0); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/tzc/tzc400.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/tzc/tzc400.c new file mode 100644 index 0000000..ca088c3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/tzc/tzc400.c @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "tzc_common_private.c" + +/* + * Macros which will be used by common core functions. + */ +#define TZC_400_REGION_BASE_LOW_0_OFFSET 0x100 +#define TZC_400_REGION_BASE_HIGH_0_OFFSET 0x104 +#define TZC_400_REGION_TOP_LOW_0_OFFSET 0x108 +#define TZC_400_REGION_TOP_HIGH_0_OFFSET 0x10c +#define TZC_400_REGION_ATTR_0_OFFSET 0x110 +#define TZC_400_REGION_ID_ACCESS_0_OFFSET 0x114 + +/* + * Implementation defined values used to validate inputs later. + * Filters : max of 4 ; 0 to 3 + * Regions : max of 9 ; 0 to 8 + * Address width : Values between 32 to 64 + */ +typedef struct tzc400_instance { + uintptr_t base; + uint8_t addr_width; + uint8_t num_filters; + uint8_t num_regions; +} tzc400_instance_t; + +tzc400_instance_t tzc400; + +static inline unsigned int _tzc400_read_build_config(uintptr_t base) +{ + return mmio_read_32(base + BUILD_CONFIG_OFF); +} + +static inline unsigned int _tzc400_read_gate_keeper(uintptr_t base) +{ + return mmio_read_32(base + GATE_KEEPER_OFF); +} + +static inline void _tzc400_write_gate_keeper(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GATE_KEEPER_OFF, val); +} + +/* + * Get the open status information for all filter units. + */ +#define get_gate_keeper_os(base) ((_tzc400_read_gate_keeper(base) >> \ + GATE_KEEPER_OS_SHIFT) & \ + GATE_KEEPER_OS_MASK) + + +/* Define common core functions used across different TZC peripherals. */ +DEFINE_TZC_COMMON_WRITE_ACTION(400, 400) +DEFINE_TZC_COMMON_WRITE_REGION_BASE(400, 400) +DEFINE_TZC_COMMON_WRITE_REGION_TOP(400, 400) +DEFINE_TZC_COMMON_WRITE_REGION_ATTRIBUTES(400, 400) +DEFINE_TZC_COMMON_WRITE_REGION_ID_ACCESS(400, 400) +DEFINE_TZC_COMMON_CONFIGURE_REGION0(400) +DEFINE_TZC_COMMON_CONFIGURE_REGION(400) + +static unsigned int _tzc400_get_gate_keeper(uintptr_t base, + unsigned int filter) +{ + unsigned int open_status; + + open_status = get_gate_keeper_os(base); + + return (open_status >> filter) & GATE_KEEPER_FILTER_MASK; +} + +/* This function is not MP safe. */ +static void _tzc400_set_gate_keeper(uintptr_t base, + unsigned int filter, + int val) +{ + unsigned int open_status; + + /* Upper half is current state. Lower half is requested state. */ + open_status = get_gate_keeper_os(base); + + if (val) + open_status |= (1 << filter); + else + open_status &= ~(1 << filter); + + _tzc400_write_gate_keeper(base, (open_status & GATE_KEEPER_OR_MASK) << + GATE_KEEPER_OR_SHIFT); + + /* Wait here until we see the change reflected in the TZC status. */ + while ((get_gate_keeper_os(base)) != open_status) + ; +} + +void tzc400_set_action(tzc_action_t action) +{ + assert(tzc400.base); + assert(action <= TZC_ACTION_ERR_INT); + + /* + * - Currently no handler is provided to trap an error via interrupt + * or exception. + * - The interrupt action has not been tested. + */ + _tzc400_write_action(tzc400.base, action); +} + +void tzc400_init(uintptr_t base) +{ +#if DEBUG + unsigned int tzc400_id; +#endif + unsigned int tzc400_build; + + assert(base); + tzc400.base = base; + +#if DEBUG + tzc400_id = _tzc_read_peripheral_id(base); + if (tzc400_id != TZC_400_PERIPHERAL_ID) { + ERROR("TZC-400 : Wrong device ID (0x%x).\n", tzc400_id); + panic(); + } +#endif + + /* Save values we will use later. */ + tzc400_build = _tzc400_read_build_config(tzc400.base); + tzc400.num_filters = ((tzc400_build >> BUILD_CONFIG_NF_SHIFT) & + BUILD_CONFIG_NF_MASK) + 1; + tzc400.addr_width = ((tzc400_build >> BUILD_CONFIG_AW_SHIFT) & + BUILD_CONFIG_AW_MASK) + 1; + tzc400.num_regions = ((tzc400_build >> BUILD_CONFIG_NR_SHIFT) & + BUILD_CONFIG_NR_MASK) + 1; +} + +/* + * `tzc400_configure_region0` is used to program region 0 into the TrustZone + * controller. Region 0 covers the whole address space that is not mapped + * to any other region, and is enabled on all filters; this cannot be + * changed. This function only changes the access permissions. + */ +void tzc400_configure_region0(tzc_region_attributes_t sec_attr, + unsigned int ns_device_access) +{ + assert(tzc400.base); + assert(sec_attr <= TZC_REGION_S_RDWR); + + _tzc400_configure_region0(tzc400.base, sec_attr, ns_device_access); +} + +/* + * `tzc400_configure_region` is used to program regions into the TrustZone + * controller. A region can be associated with more than one filter. The + * associated filters are passed in as a bitmap (bit0 = filter0). + * NOTE: + * Region 0 is special; it is preferable to use tzc400_configure_region0 + * for this region (see comment for that function). + */ +void tzc400_configure_region(unsigned int filters, + int region, + unsigned long long region_base, + unsigned long long region_top, + tzc_region_attributes_t sec_attr, + unsigned int nsaid_permissions) +{ + assert(tzc400.base); + + /* Do range checks on filters and regions. */ + assert(((filters >> tzc400.num_filters) == 0) && + (region >= 0) && (region < tzc400.num_regions)); + + /* + * Do address range check based on TZC configuration. A 64bit address is + * the max and expected case. + */ + assert(((region_top <= _tzc_get_max_top_addr(tzc400.addr_width)) && + (region_base < region_top))); + + /* region_base and (region_top + 1) must be 4KB aligned */ + assert(((region_base | (region_top + 1)) & (4096 - 1)) == 0); + + assert(sec_attr <= TZC_REGION_S_RDWR); + + _tzc400_configure_region(tzc400.base, filters, region, region_base, + region_top, + sec_attr, nsaid_permissions); +} + +void tzc400_enable_filters(void) +{ + unsigned int state; + unsigned int filter; + + assert(tzc400.base); + + for (filter = 0; filter < tzc400.num_filters; filter++) { + state = _tzc400_get_gate_keeper(tzc400.base, filter); + if (state) { + /* The TZC filter is already configured. Changing the + * programmer's view in an active system can cause + * unpredictable behavior therefore panic for now rather + * than try to determine whether this is safe in this + * instance. See: + * http://infocenter.arm.com/help/index.jsp?\ + * topic=/com.arm.doc.ddi0504c/CJHHECBF.html */ + ERROR("TZC-400 : Filter %d Gatekeeper already" + " enabled.\n", filter); + panic(); + } + _tzc400_set_gate_keeper(tzc400.base, filter, 1); + } +} + +void tzc400_disable_filters(void) +{ + unsigned int filter; + + assert(tzc400.base); + + /* + * We don't do the same state check as above as the Gatekeepers are + * disabled after reset. + */ + for (filter = 0; filter < tzc400.num_filters; filter++) + _tzc400_set_gate_keeper(tzc400.base, filter, 0); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/tzc/tzc_common_private.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/tzc/tzc_common_private.c new file mode 100644 index 0000000..8b1ddf4 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/tzc/tzc_common_private.c @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#define DEFINE_TZC_COMMON_WRITE_ACTION(fn_name, macro_name) \ + static inline void _tzc##fn_name##_write_action( \ + uintptr_t base, \ + tzc_action_t action) \ + { \ + mmio_write_32(base + TZC_##macro_name##_ACTION_OFF, \ + action); \ + } + +#define DEFINE_TZC_COMMON_WRITE_REGION_BASE(fn_name, macro_name) \ + static inline void _tzc##fn_name##_write_region_base( \ + uintptr_t base, \ + int region_no, \ + unsigned long long region_base) \ + { \ + mmio_write_32(base + \ + TZC_REGION_OFFSET( \ + TZC_##macro_name##_REGION_SIZE, \ + region_no) + \ + TZC_##macro_name##_REGION_BASE_LOW_0_OFFSET, \ + (uint32_t)region_base); \ + mmio_write_32(base + \ + TZC_REGION_OFFSET( \ + TZC_##macro_name##_REGION_SIZE, \ + region_no) + \ + TZC_##macro_name##_REGION_BASE_HIGH_0_OFFSET, \ + (uint32_t)(region_base >> 32)); \ + } + +#define DEFINE_TZC_COMMON_WRITE_REGION_TOP(fn_name, macro_name) \ + static inline void _tzc##fn_name##_write_region_top( \ + uintptr_t base, \ + int region_no, \ + unsigned long long region_top) \ + { \ + mmio_write_32(base + \ + TZC_REGION_OFFSET \ + (TZC_##macro_name##_REGION_SIZE, \ + region_no) + \ + TZC_##macro_name##_REGION_TOP_LOW_0_OFFSET, \ + (uint32_t)region_top); \ + mmio_write_32(base + \ + TZC_REGION_OFFSET( \ + TZC_##macro_name##_REGION_SIZE, \ + region_no) + \ + TZC_##macro_name##_REGION_TOP_HIGH_0_OFFSET, \ + (uint32_t)(region_top >> 32)); \ + } + +#define DEFINE_TZC_COMMON_WRITE_REGION_ATTRIBUTES(fn_name, macro_name) \ + static inline void _tzc##fn_name##_write_region_attributes( \ + uintptr_t base, \ + int region_no, \ + unsigned int attr) \ + { \ + mmio_write_32(base + \ + TZC_REGION_OFFSET( \ + TZC_##macro_name##_REGION_SIZE, \ + region_no) + \ + TZC_##macro_name##_REGION_ATTR_0_OFFSET, \ + attr); \ + } + +#define DEFINE_TZC_COMMON_WRITE_REGION_ID_ACCESS(fn_name, macro_name) \ + static inline void _tzc##fn_name##_write_region_id_access( \ + uintptr_t base, \ + int region_no, \ + unsigned int val) \ + { \ + mmio_write_32(base + \ + TZC_REGION_OFFSET( \ + TZC_##macro_name##_REGION_SIZE, \ + region_no) + \ + TZC_##macro_name##_REGION_ID_ACCESS_0_OFFSET, \ + val); \ + } + +/* + * It is used to program region 0 ATTRIBUTES and ACCESS register. + */ +#define DEFINE_TZC_COMMON_CONFIGURE_REGION0(fn_name) \ + void _tzc##fn_name##_configure_region0(uintptr_t base, \ + tzc_region_attributes_t sec_attr, \ + unsigned int ns_device_access) \ + { \ + assert(base); \ + VERBOSE("TrustZone : Configuring region 0 " \ + "(TZC Interface Base=%p sec_attr=0x%x," \ + " ns_devs=0x%x)\n", (void *)base, \ + sec_attr, ns_device_access); \ + \ + /* Set secure attributes on region 0 */ \ + _tzc##fn_name##_write_region_attributes(base, 0, \ + sec_attr << TZC_REGION_ATTR_SEC_SHIFT); \ + \ + /***************************************************/ \ + /* Specify which non-secure devices have permission*/ \ + /* to access region 0. */ \ + /***************************************************/ \ + _tzc##fn_name##_write_region_id_access(base, \ + 0, \ + ns_device_access); \ + } + +/* + * It is used to program a region from 1 to 8 in the TrustZone controller. + * NOTE: + * Region 0 is special; it is preferable to use + * ##fn_name##_configure_region0 for this region (see comment for + * that function). + */ +#define DEFINE_TZC_COMMON_CONFIGURE_REGION(fn_name) \ + void _tzc##fn_name##_configure_region(uintptr_t base, \ + unsigned int filters, \ + int region_no, \ + unsigned long long region_base, \ + unsigned long long region_top, \ + tzc_region_attributes_t sec_attr, \ + unsigned int nsaid_permissions) \ + { \ + assert(base); \ + VERBOSE("TrustZone : Configuring region " \ + "(TZC Interface Base: %p, region_no = %d)" \ + "...\n", (void *)base, region_no); \ + VERBOSE("TrustZone : ... base = %llx, top = %llx," \ + "\n", region_base, region_top);\ + VERBOSE("TrustZone : ... sec_attr = 0x%x," \ + " ns_devs = 0x%x)\n", \ + sec_attr, nsaid_permissions); \ + \ + /***************************************************/ \ + /* Inputs look ok, start programming registers. */ \ + /* All the address registers are 32 bits wide and */ \ + /* have a LOW and HIGH */ \ + /* component used to construct an address up to a */ \ + /* 64bit. */ \ + /***************************************************/ \ + _tzc##fn_name##_write_region_base(base, \ + region_no, region_base); \ + _tzc##fn_name##_write_region_top(base, \ + region_no, region_top); \ + \ + /* Enable filter to the region and set secure attributes */\ + _tzc##fn_name##_write_region_attributes(base, \ + region_no, \ + (sec_attr << TZC_REGION_ATTR_SEC_SHIFT) |\ + (filters << TZC_REGION_ATTR_F_EN_SHIFT));\ + \ + /***************************************************/ \ + /* Specify which non-secure devices have permission*/ \ + /* to access this region. */ \ + /***************************************************/ \ + _tzc##fn_name##_write_region_id_access(base, \ + region_no, \ + nsaid_permissions); \ + } + +#if DEBUG +static unsigned int _tzc_read_peripheral_id(uintptr_t base) +{ + unsigned int id; + + id = mmio_read_32(base + PID0_OFF); + /* Masks DESC part in PID1 */ + id |= ((mmio_read_32(base + PID1_OFF) & 0xF) << 8); + + return id; +} + +#ifdef AARCH32 +static unsigned long long _tzc_get_max_top_addr(int addr_width) +{ + /* + * Assume at least 32 bit wide address and initialize the max. + * This function doesn't use 64-bit integer arithmetic to avoid + * having to implement additional compiler library functions. + */ + unsigned long long addr_mask = 0xFFFFFFFF; + uint32_t *addr_ptr = (uint32_t *)&addr_mask; + + assert(addr_width >= 32); + + /* This logic works only on little - endian platforms */ + assert((read_sctlr() & SCTLR_EE_BIT) == 0); + + /* + * If required address width is greater than 32, populate the higher + * 32 bits of the 64 bit field with the max address. + */ + if (addr_width > 32) + *(addr_ptr + 1) = ((1 << (addr_width - 32)) - 1); + + return addr_mask; +} +#else +#define _tzc_get_max_top_addr(addr_width)\ + (UINT64_MAX >> (64 - (addr_width))) +#endif /* AARCH32 */ + +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/tzc/tzc_dmc500.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/tzc/tzc_dmc500.c new file mode 100644 index 0000000..24e587c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/tzc/tzc_dmc500.c @@ -0,0 +1,299 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "tzc_common.h" +#include "tzc_common_private.c" + +/* + * Macros which will be used by common core functions. + */ +#define TZC_DMC500_REGION_BASE_LOW_0_OFFSET 0x054 +#define TZC_DMC500_REGION_BASE_HIGH_0_OFFSET 0x058 +#define TZC_DMC500_REGION_TOP_LOW_0_OFFSET 0x05C +#define TZC_DMC500_REGION_TOP_HIGH_0_OFFSET 0x060 +#define TZC_DMC500_REGION_ATTR_0_OFFSET 0x064 +#define TZC_DMC500_REGION_ID_ACCESS_0_OFFSET 0x068 + +#define TZC_DMC500_ACTION_OFF 0x50 + +/* Pointer to the tzc_dmc500_driver_data structure populated by the platform */ +static const tzc_dmc500_driver_data_t *g_driver_data; + +#define verify_region_attr(region, attr) \ + ((g_conf_regions[(region)].sec_attr == \ + ((attr) >> TZC_REGION_ATTR_SEC_SHIFT)) \ + && ((attr) & (0x1 << TZC_REGION_ATTR_F_EN_SHIFT))) + +/* + * Structure for configured regions attributes in DMC500. + */ +typedef struct tzc_dmc500_regions { + tzc_region_attributes_t sec_attr; + int is_enabled; +} tzc_dmc500_regions_t; + +/* + * Array storing the attributes of the configured regions. This array + * will be used by the `tzc_dmc500_verify_complete` to verify the flush + * completion. + */ +static tzc_dmc500_regions_t g_conf_regions[MAX_REGION_VAL + 1]; + +/* Helper Macros for making the code readable */ +#define DMC_INST_BASE_ADDR(instance) (g_driver_data->dmc_base[instance]) +#define DMC_INST_SI_BASE(instance, interface) \ + (DMC_INST_BASE_ADDR(instance) + IFACE_OFFSET(interface)) + +DEFINE_TZC_COMMON_WRITE_ACTION(_dmc500, DMC500) +DEFINE_TZC_COMMON_WRITE_REGION_BASE(_dmc500, DMC500) +DEFINE_TZC_COMMON_WRITE_REGION_TOP(_dmc500, DMC500) +DEFINE_TZC_COMMON_WRITE_REGION_ATTRIBUTES(_dmc500, DMC500) +DEFINE_TZC_COMMON_WRITE_REGION_ID_ACCESS(_dmc500, DMC500) + +DEFINE_TZC_COMMON_CONFIGURE_REGION0(_dmc500) +DEFINE_TZC_COMMON_CONFIGURE_REGION(_dmc500) + +static inline unsigned int _tzc_dmc500_read_region_attr_0( + uintptr_t dmc_si_base, + int region_no) +{ + return mmio_read_32(dmc_si_base + + TZC_REGION_OFFSET(TZC_DMC500_REGION_SIZE, region_no) + + TZC_DMC500_REGION_ATTR_0_OFFSET); +} + +static inline void _tzc_dmc500_write_flush_control(uintptr_t dmc_si_base) +{ + mmio_write_32(dmc_si_base + SI_FLUSH_CTRL_OFFSET, 1); +} + +/* + * Sets the Flush controls for all the DMC Instances and System Interfaces. + * This initiates the flush of configuration settings from the shadow + * registers to the actual configuration register. The caller should poll + * changed register to confirm update. + */ +void tzc_dmc500_config_complete(void) +{ + int dmc_inst, sys_if; + + assert(g_driver_data); + + for (dmc_inst = 0; dmc_inst < g_driver_data->dmc_count; dmc_inst++) { + assert(DMC_INST_BASE_ADDR(dmc_inst)); + for (sys_if = 0; sys_if < MAX_SYS_IF_COUNT; sys_if++) + _tzc_dmc500_write_flush_control( + DMC_INST_SI_BASE(dmc_inst, sys_if)); + } +} + +/* + * This function reads back the secure attributes from the configuration + * register for each DMC Instance and System Interface and compares it with + * the configured value. The successful verification of the region attributes + * confirms that the flush operation has completed. + * If the verification fails, the caller is expected to invoke this API again + * till it succeeds. + * Returns 0 on success and 1 on failure. + */ +int tzc_dmc500_verify_complete(void) +{ + int dmc_inst, sys_if, region_no; + unsigned int attr; + + assert(g_driver_data); + /* Region 0 must be configured */ + assert(g_conf_regions[0].is_enabled); + + /* Iterate over all configured regions */ + for (region_no = 0; region_no <= MAX_REGION_VAL; region_no++) { + if (!g_conf_regions[region_no].is_enabled) + continue; + for (dmc_inst = 0; dmc_inst < g_driver_data->dmc_count; + dmc_inst++) { + assert(DMC_INST_BASE_ADDR(dmc_inst)); + for (sys_if = 0; sys_if < MAX_SYS_IF_COUNT; + sys_if++) { + attr = _tzc_dmc500_read_region_attr_0( + DMC_INST_SI_BASE(dmc_inst, sys_if), + region_no); + VERBOSE("Verifying DMC500 region:%d" + " dmc_inst:%d sys_if:%d attr:%x\n", + region_no, dmc_inst, sys_if, attr); + if (!verify_region_attr(region_no, attr)) + return 1; + } + } + } + + return 0; +} + +/* + * `tzc_dmc500_configure_region0` is used to program region 0 in both the + * system interfaces of all the DMC-500 instances. Region 0 covers the whole + * address space that is not mapped to any other region for a system interface, + * and is always enabled; this cannot be changed. This function only changes + * the access permissions. + */ +void tzc_dmc500_configure_region0(tzc_region_attributes_t sec_attr, + unsigned int nsaid_permissions) +{ + int dmc_inst, sys_if; + + /* Assert if DMC-500 is not initialized */ + assert(g_driver_data); + + /* Configure region_0 in all DMC instances */ + for (dmc_inst = 0; dmc_inst < g_driver_data->dmc_count; dmc_inst++) { + assert(DMC_INST_BASE_ADDR(dmc_inst)); + for (sys_if = 0; sys_if < MAX_SYS_IF_COUNT; sys_if++) + _tzc_dmc500_configure_region0( + DMC_INST_SI_BASE(dmc_inst, sys_if), + sec_attr, nsaid_permissions); + } + + g_conf_regions[0].sec_attr = sec_attr; + g_conf_regions[0].is_enabled = 1; +} + +/* + * `tzc_dmc500_configure_region` is used to program a region into all system + * interfaces of all the DMC instances. + * NOTE: + * Region 0 is special; it is preferable to use tzc_dmc500_configure_region0 + * for this region (see comment for that function). + */ +void tzc_dmc500_configure_region(int region_no, + unsigned long long region_base, + unsigned long long region_top, + tzc_region_attributes_t sec_attr, + unsigned int nsaid_permissions) +{ + int dmc_inst, sys_if; + + assert(g_driver_data); + /* Do range checks on regions. */ + assert(region_no >= 0 && region_no <= MAX_REGION_VAL); + + /* + * Do address range check based on DMC-TZ configuration. A 43bit address + * is the max and expected case. + */ + assert(((region_top <= _tzc_get_max_top_addr(43)) && + (region_base < region_top))); + + /* region_base and (region_top + 1) must be 4KB aligned */ + assert(((region_base | (region_top + 1)) & (4096 - 1)) == 0); + + for (dmc_inst = 0; dmc_inst < g_driver_data->dmc_count; dmc_inst++) { + assert(DMC_INST_BASE_ADDR(dmc_inst)); + for (sys_if = 0; sys_if < MAX_SYS_IF_COUNT; sys_if++) + _tzc_dmc500_configure_region( + DMC_INST_SI_BASE(dmc_inst, sys_if), + TZC_DMC500_REGION_ATTR_F_EN_MASK, + region_no, region_base, region_top, + sec_attr, nsaid_permissions); + } + + g_conf_regions[region_no].sec_attr = sec_attr; + g_conf_regions[region_no].is_enabled = 1; +} + +/* Sets the action value for all the DMC instances */ +void tzc_dmc500_set_action(tzc_action_t action) +{ + int dmc_inst; + + assert(g_driver_data); + + for (dmc_inst = 0; dmc_inst < g_driver_data->dmc_count; dmc_inst++) { + assert(DMC_INST_BASE_ADDR(dmc_inst)); + /* + * - Currently no handler is provided to trap an error via + * interrupt or exception. + * - The interrupt action has not been tested. + */ + _tzc_dmc500_write_action(DMC_INST_BASE_ADDR(dmc_inst), action); + } +} + +/* + * A DMC-500 instance must be present at each base address provided by the + * platform. It also expects platform to pass at least one instance of + * DMC-500. + */ +static void validate_plat_driver_data( + const tzc_dmc500_driver_data_t *plat_driver_data) +{ +#if DEBUG + int i; + unsigned int dmc_id; + uintptr_t dmc_base; + + assert(plat_driver_data); + assert(plat_driver_data->dmc_count > 0 && + (plat_driver_data->dmc_count <= MAX_DMC_COUNT)); + + for (i = 0; i < plat_driver_data->dmc_count; i++) { + dmc_base = plat_driver_data->dmc_base[i]; + assert(dmc_base); + + dmc_id = _tzc_read_peripheral_id(dmc_base); + assert(dmc_id == DMC500_PERIPHERAL_ID); + } +#endif /* DEBUG */ +} + + +/* + * Initializes the base address and count of DMC instances. + * + * Note : Only pointer to plat_driver_data is saved, so it is caller's + * responsibility to keep it valid until the driver is used. + */ +void tzc_dmc500_driver_init(const tzc_dmc500_driver_data_t *plat_driver_data) +{ + /* Check valid pointer is passed */ + assert(plat_driver_data); + + /* + * NOTE: This driver expects the DMC-500 controller is already in + * READY state. Hence, it uses the reconfiguration method for + * programming TrustZone regions + */ + /* Validates the information passed by platform */ + validate_plat_driver_data(plat_driver_data); + g_driver_data = plat_driver_data; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/tzc400/tzc400.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/tzc400/tzc400.c new file mode 100644 index 0000000..97adf81 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/arm/tzc400/tzc400.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#if ERROR_DEPRECATED +#error "Using deprecated TZC-400 source file" +#else +#include "../tzc/tzc400.c" +#endif /* ERROR_DEPRECATED */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/auth_mod.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/auth_mod.c new file mode 100644 index 0000000..88ef0b0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/auth_mod.c @@ -0,0 +1,438 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* ASN.1 tags */ +#define ASN1_INTEGER 0x02 + +#define return_if_error(rc) \ + do { \ + if (rc != 0) { \ + return rc; \ + } \ + } while (0) + +/* Pointer to CoT */ +extern const auth_img_desc_t *const cot_desc_ptr; +extern unsigned int auth_img_flags[]; + +static int cmp_auth_param_type_desc(const auth_param_type_desc_t *a, + const auth_param_type_desc_t *b) +{ + if ((a->type == b->type) && (a->cookie == b->cookie)) { + return 0; + } + return 1; +} + +/* + * This function obtains the requested authentication parameter data from the + * information extracted from the parent image after its authentication. + */ +static int auth_get_param(const auth_param_type_desc_t *param_type_desc, + const auth_img_desc_t *img_desc, + void **param, unsigned int *len) +{ + int i; + + for (i = 0 ; i < COT_MAX_VERIFIED_PARAMS ; i++) { + if (0 == cmp_auth_param_type_desc(param_type_desc, + img_desc->authenticated_data[i].type_desc)) { + *param = img_desc->authenticated_data[i].data.ptr; + *len = img_desc->authenticated_data[i].data.len; + return 0; + } + } + + return 1; +} + +/* + * Authenticate an image by matching the data hash + * + * This function implements 'AUTH_METHOD_HASH'. To authenticate an image using + * this method, the image must contain: + * + * - The data to calculate the hash from + * + * The parent image must contain: + * + * - The hash to be matched with (including hash algorithm) + * + * For a successful authentication, both hashes must match. The function calls + * the crypto-module to check this matching. + * + * Parameters: + * param: parameters to perform the hash authentication + * img_desc: pointer to image descriptor so we can know the image type + * and parent image + * img: pointer to image in memory + * img_len: length of image (in bytes) + * + * Return: + * 0 = success, Otherwise = error + */ +static int auth_hash(const auth_method_param_hash_t *param, + const auth_img_desc_t *img_desc, + void *img, unsigned int img_len) +{ + void *data_ptr, *hash_der_ptr; + unsigned int data_len, hash_der_len; + int rc = 0; + + /* Get the hash from the parent image. This hash will be DER encoded + * and contain the hash algorithm */ + rc = auth_get_param(param->hash, img_desc->parent, + &hash_der_ptr, &hash_der_len); + return_if_error(rc); + + /* Get the data to be hashed from the current image */ + rc = img_parser_get_auth_param(img_desc->img_type, param->data, + img, img_len, &data_ptr, &data_len); + return_if_error(rc); + + /* Ask the crypto module to verify this hash */ + rc = crypto_mod_verify_hash(data_ptr, data_len, + hash_der_ptr, hash_der_len); + + return rc; +} + +/* + * Authenticate by digital signature + * + * This function implements 'AUTH_METHOD_SIG'. To authenticate an image using + * this method, the image must contain: + * + * - Data to be signed + * - Signature + * - Signature algorithm + * + * We rely on the image parser module to extract this data from the image. + * The parent image must contain: + * + * - Public key (or a hash of it) + * + * If the parent image contains only a hash of the key, we will try to obtain + * the public key from the image itself (i.e. self-signed certificates). In that + * case, the signature verification is considered just an integrity check and + * the authentication is established by calculating the hash of the key and + * comparing it with the hash obtained from the parent. + * + * If the image has no parent (NULL), it means it has to be authenticated using + * the ROTPK stored in the platform. Again, this ROTPK could be the key itself + * or a hash of it. + * + * Return: 0 = success, Otherwise = error + */ +static int auth_signature(const auth_method_param_sig_t *param, + const auth_img_desc_t *img_desc, + void *img, unsigned int img_len) +{ + void *data_ptr, *pk_ptr, *pk_hash_ptr, *sig_ptr, *sig_alg_ptr; + unsigned int data_len, pk_len, pk_hash_len, sig_len, sig_alg_len; + unsigned int flags = 0; + int rc = 0; + + /* Get the data to be signed from current image */ + rc = img_parser_get_auth_param(img_desc->img_type, param->data, + img, img_len, &data_ptr, &data_len); + return_if_error(rc); + + /* Get the signature from current image */ + rc = img_parser_get_auth_param(img_desc->img_type, param->sig, + img, img_len, &sig_ptr, &sig_len); + return_if_error(rc); + + /* Get the signature algorithm from current image */ + rc = img_parser_get_auth_param(img_desc->img_type, param->alg, + img, img_len, &sig_alg_ptr, &sig_alg_len); + return_if_error(rc); + + /* Get the public key from the parent. If there is no parent (NULL), + * the certificate has been signed with the ROTPK, so we have to get + * the PK from the platform */ + if (img_desc->parent) { + rc = auth_get_param(param->pk, img_desc->parent, + &pk_ptr, &pk_len); + } else { + rc = plat_get_rotpk_info(param->pk->cookie, &pk_ptr, &pk_len, + &flags); + } + return_if_error(rc); + + if (flags & (ROTPK_IS_HASH | ROTPK_NOT_DEPLOYED)) { + /* If the PK is a hash of the key or if the ROTPK is not + deployed on the platform, retrieve the key from the image */ + pk_hash_ptr = pk_ptr; + pk_hash_len = pk_len; + rc = img_parser_get_auth_param(img_desc->img_type, + param->pk, img, img_len, + &pk_ptr, &pk_len); + return_if_error(rc); + + /* Ask the crypto module to verify the signature */ + rc = crypto_mod_verify_signature(data_ptr, data_len, + sig_ptr, sig_len, + sig_alg_ptr, sig_alg_len, + pk_ptr, pk_len); + return_if_error(rc); + + if (flags & ROTPK_NOT_DEPLOYED) { + NOTICE("ROTPK is not deployed on platform. " + "Skipping ROTPK verification.\n"); + } else { + /* Ask the crypto-module to verify the key hash */ + rc = crypto_mod_verify_hash(pk_ptr, pk_len, + pk_hash_ptr, pk_hash_len); + } + } else { + /* Ask the crypto module to verify the signature */ + rc = crypto_mod_verify_signature(data_ptr, data_len, + sig_ptr, sig_len, + sig_alg_ptr, sig_alg_len, + pk_ptr, pk_len); + } + + return rc; +} + +/* + * Authenticate by Non-Volatile counter + * + * To protect the system against rollback, the platform includes a non-volatile + * counter whose value can only be increased. All certificates include a counter + * value that should not be lower than the value stored in the platform. If the + * value is larger, the counter in the platform must be updated to the new + * value. + * + * Return: 0 = success, Otherwise = error + */ +static int auth_nvctr(const auth_method_param_nv_ctr_t *param, + const auth_img_desc_t *img_desc, + void *img, unsigned int img_len) +{ + char *p; + void *data_ptr = NULL; + unsigned int data_len, len, i; + unsigned int cert_nv_ctr, plat_nv_ctr; + int rc = 0; + + /* Get the counter value from current image. The AM expects the IPM + * to return the counter value as a DER encoded integer */ + rc = img_parser_get_auth_param(img_desc->img_type, param->cert_nv_ctr, + img, img_len, &data_ptr, &data_len); + return_if_error(rc); + + /* Parse the DER encoded integer */ + assert(data_ptr); + p = (char *)data_ptr; + if (*p != ASN1_INTEGER) { + /* Invalid ASN.1 integer */ + return 1; + } + p++; + + /* NV-counters are unsigned integers up to 32-bit */ + len = (unsigned int)(*p & 0x7f); + if ((*p & 0x80) || (len > 4)) { + return 1; + } + p++; + + /* Check the number is not negative */ + if (*p & 0x80) { + return 1; + } + + /* Convert to unsigned int. This code is for a little-endian CPU */ + cert_nv_ctr = 0; + for (i = 0; i < len; i++) { + cert_nv_ctr = (cert_nv_ctr << 8) | *p++; + } + + /* Get the counter from the platform */ + rc = plat_get_nv_ctr(param->plat_nv_ctr->cookie, &plat_nv_ctr); + return_if_error(rc); + + if (cert_nv_ctr < plat_nv_ctr) { + /* Invalid NV-counter */ + return 1; + } else if (cert_nv_ctr > plat_nv_ctr) { + if (img_desc->parent == NULL) { + /* This certificate has been signed with the ROT key. + * Update the platform counter value */ + rc = plat_set_nv_ctr(param->plat_nv_ctr->cookie, + cert_nv_ctr); + return_if_error(rc); + } else { + /* Secondary certificates cannot modify the counter */ + return 1; + } + } + + return 0; +} + +/* + * Return the parent id in the output parameter '*parent_id' + * + * Return value: + * 0 = Image has parent, 1 = Image has no parent or parent is authenticated + */ +int auth_mod_get_parent_id(unsigned int img_id, unsigned int *parent_id) +{ + const auth_img_desc_t *img_desc = NULL; + + assert(parent_id != NULL); + + /* Get the image descriptor */ + img_desc = &cot_desc_ptr[img_id]; + + /* Check if the image has no parent (ROT) */ + if (img_desc->parent == NULL) { + *parent_id = 0; + return 1; + } + + /* Check if the parent has already been authenticated */ + if (auth_img_flags[img_desc->parent->img_id] & IMG_FLAG_AUTHENTICATED) { + *parent_id = 0; + return 1; + } + + *parent_id = img_desc->parent->img_id; + return 0; +} + +/* + * Initialize the different modules in the authentication framework + */ +void auth_mod_init(void) +{ + /* Check we have a valid CoT registered */ + assert(cot_desc_ptr != NULL); + + /* Crypto module */ + crypto_mod_init(); + + /* Image parser module */ + img_parser_init(); +} + +/* + * Authenticate a certificate/image + * + * Return: 0 = success, Otherwise = error + */ +int auth_mod_verify_img(unsigned int img_id, + void *img_ptr, + unsigned int img_len) +{ + const auth_img_desc_t *img_desc = NULL; + const auth_method_desc_t *auth_method = NULL; + void *param_ptr; + unsigned int param_len; + int rc, i; + + /* Get the image descriptor from the chain of trust */ + img_desc = &cot_desc_ptr[img_id]; + + /* Ask the parser to check the image integrity */ + rc = img_parser_check_integrity(img_desc->img_type, img_ptr, img_len); + return_if_error(rc); + + /* Authenticate the image using the methods indicated in the image + * descriptor. */ + for (i = 0 ; i < AUTH_METHOD_NUM ; i++) { + auth_method = &img_desc->img_auth_methods[i]; + switch (auth_method->type) { + case AUTH_METHOD_NONE: + rc = 0; + break; + case AUTH_METHOD_HASH: + rc = auth_hash(&auth_method->param.hash, + img_desc, img_ptr, img_len); + break; + case AUTH_METHOD_SIG: + rc = auth_signature(&auth_method->param.sig, + img_desc, img_ptr, img_len); + break; + case AUTH_METHOD_NV_CTR: + rc = auth_nvctr(&auth_method->param.nv_ctr, + img_desc, img_ptr, img_len); + break; + default: + /* Unknown authentication method */ + rc = 1; + break; + } + return_if_error(rc); + } + + /* Extract the parameters indicated in the image descriptor to + * authenticate the children images. */ + for (i = 0 ; i < COT_MAX_VERIFIED_PARAMS ; i++) { + if (img_desc->authenticated_data[i].type_desc == NULL) { + continue; + } + + /* Get the parameter from the image parser module */ + rc = img_parser_get_auth_param(img_desc->img_type, + img_desc->authenticated_data[i].type_desc, + img_ptr, img_len, ¶m_ptr, ¶m_len); + return_if_error(rc); + + /* Check parameter size */ + if (param_len > img_desc->authenticated_data[i].data.len) { + return 1; + } + + /* Copy the parameter for later use */ + memcpy((void *)img_desc->authenticated_data[i].data.ptr, + (void *)param_ptr, param_len); + } + + /* Mark image as authenticated */ + auth_img_flags[img_desc->img_id] |= IMG_FLAG_AUTHENTICATED; + + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/crypto_mod.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/crypto_mod.c new file mode 100644 index 0000000..b432e6a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/crypto_mod.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/* Variable exported by the crypto library through REGISTER_CRYPTO_LIB() */ +extern const crypto_lib_desc_t crypto_lib_desc; + +/* + * The crypto module is responsible for verifying digital signatures and hashes. + * It relies on a crypto library to perform the cryptographic operations. + * + * The crypto module itself does not impose any specific format on signatures, + * signature algorithm, keys or hashes, but most cryptographic libraries will + * take the parameters as the following DER encoded ASN.1 structures: + * + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL + * } + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm AlgorithmIdentifier, + * digest OCTET STRING + * } + * + * SubjectPublicKeyInfo ::= SEQUENCE { + * algorithm AlgorithmIdentifier, + * subjectPublicKey BIT STRING + * } + * + * SignatureAlgorithm ::= AlgorithmIdentifier + * + * SignatureValue ::= BIT STRING + */ + +/* + * Perform some static checking and call the library initialization function + */ +void crypto_mod_init(void) +{ + assert(crypto_lib_desc.name != NULL); + assert(crypto_lib_desc.init != NULL); + assert(crypto_lib_desc.verify_signature != NULL); + assert(crypto_lib_desc.verify_hash != NULL); + + /* Initialize the cryptographic library */ + crypto_lib_desc.init(); + INFO("Using crypto library '%s'\n", crypto_lib_desc.name); +} + +/* + * Function to verify a digital signature + * + * Parameters: + * + * data_ptr, data_len: signed data + * sig_ptr, sig_len: the digital signature + * sig_alg_ptr, sig_alg_len: the digital signature algorithm + * pk_ptr, pk_len: the public key + */ +int crypto_mod_verify_signature(void *data_ptr, unsigned int data_len, + void *sig_ptr, unsigned int sig_len, + void *sig_alg_ptr, unsigned int sig_alg_len, + void *pk_ptr, unsigned int pk_len) +{ + assert(data_ptr != NULL); + assert(data_len != 0); + assert(sig_ptr != NULL); + assert(sig_len != 0); + assert(sig_alg_ptr != NULL); + assert(sig_alg_len != 0); + assert(pk_ptr != NULL); + assert(pk_len != 0); + + return crypto_lib_desc.verify_signature(data_ptr, data_len, + sig_ptr, sig_len, + sig_alg_ptr, sig_alg_len, + pk_ptr, pk_len); +} + +/* + * Verify a hash by comparison + * + * Parameters: + * + * data_ptr, data_len: data to be hashed + * digest_info_ptr, digest_info_len: hash to be compared + */ +int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, + void *digest_info_ptr, unsigned int digest_info_len) +{ + assert(data_ptr != NULL); + assert(data_len != 0); + assert(digest_info_ptr != NULL); + assert(digest_info_len != 0); + + return crypto_lib_desc.verify_hash(data_ptr, data_len, + digest_info_ptr, digest_info_len); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/img_parser_mod.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/img_parser_mod.c new file mode 100644 index 0000000..c8cbe34 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/img_parser_mod.c @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +extern uintptr_t __PARSER_LIB_DESCS_START__; +extern uintptr_t __PARSER_LIB_DESCS_END__; +#define PARSER_LIB_DESCS_START ((uintptr_t) (&__PARSER_LIB_DESCS_START__)) +#define PARSER_LIB_DESCS_END ((uintptr_t) (&__PARSER_LIB_DESCS_END__)) +static unsigned int parser_lib_indices[IMG_MAX_TYPES]; +static img_parser_lib_desc_t *parser_lib_descs; + +#define INVALID_IDX UINT_MAX + +static void validate_desc(img_parser_lib_desc_t *desc) +{ + assert(desc != NULL); + assert(desc->init != NULL); + assert(desc->name != NULL); + assert(desc->check_integrity != NULL); + assert(desc->get_auth_param != NULL); +} + +void img_parser_init(void) +{ + unsigned int index, mod_num; + + /* Initialise internal variables to invalid state */ + for (index = 0; index < IMG_MAX_TYPES; index++) { + parser_lib_indices[index] = INVALID_IDX; + } + + /* Calculate how many image parsers are registered. At least one parser + * must be present */ + mod_num = PARSER_LIB_DESCS_END - PARSER_LIB_DESCS_START; + mod_num /= sizeof(img_parser_lib_desc_t); + assert(mod_num > 0); + + parser_lib_descs = (img_parser_lib_desc_t *) PARSER_LIB_DESCS_START; + for (index = 0; index < mod_num; index++) { + + /* Check that the image parser library descriptor is valid */ + validate_desc(&parser_lib_descs[index]); + + /* Initialize image parser */ + parser_lib_descs[index].init(); + + /* Ensure only one parser is registered for each image type */ + assert(parser_lib_indices[parser_lib_descs[index].img_type] == + INVALID_IDX); + + /* Keep the index of this hash calculator */ + parser_lib_indices[parser_lib_descs[index].img_type] = index; + } +} + +int img_parser_check_integrity(img_type_t img_type, + void *img_ptr, unsigned int img_len) +{ + unsigned int idx; + + assert(img_ptr != NULL); + assert(img_len != 0); + + /* No integrity checks on raw images */ + if (img_type == IMG_RAW) { + return IMG_PARSER_OK; + } + + /* Find the index of the required image parser */ + idx = parser_lib_indices[img_type]; + assert(idx != INVALID_IDX); + + /* Call the function to check the image integrity */ + return parser_lib_descs[idx].check_integrity(img_ptr, img_len); +} + +/* + * Extract an authentication parameter from an image + * + * Parameters: + * img_type: image type (certificate, raw image, etc) + * type_desc: provides info to obtain the parameter + * img_ptr: pointer to image data + * img_len: image length + * param_ptr: [out] stores a pointer to the parameter + * param_len: [out] stores the length of the parameter + */ +int img_parser_get_auth_param(img_type_t img_type, + const auth_param_type_desc_t *type_desc, + void *img_ptr, unsigned int img_len, + void **param_ptr, unsigned int *param_len) +{ + unsigned int idx; + + assert(type_desc != NULL); + assert(img_ptr != NULL); + assert(img_len != 0); + assert(param_ptr != NULL); + assert(param_len != NULL); + + /* In a raw image we can only get the data itself */ + if (img_type == IMG_RAW) { + assert(type_desc->type == AUTH_PARAM_RAW_DATA); + *param_ptr = img_ptr; + *param_len = img_len; + return IMG_PARSER_OK; + } + + /* Find the index of the required image parser library */ + idx = parser_lib_indices[img_type]; + assert(idx != INVALID_IDX); + + /* Call the function to obtain the parameter */ + return parser_lib_descs[idx].get_auth_param(type_desc, img_ptr, img_len, + param_ptr, param_len); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_common.c new file mode 100644 index 0000000..053bf1a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_common.c @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* mbed TLS headers */ +#include + +/* + * mbed TLS heap + */ +#if (MBEDTLS_KEY_ALG_ID == MBEDTLS_ECDSA) +#define MBEDTLS_HEAP_SIZE (14*1024) +#elif (MBEDTLS_KEY_ALG_ID == MBEDTLS_RSA) +#define MBEDTLS_HEAP_SIZE (8*1024) +#endif +static unsigned char heap[MBEDTLS_HEAP_SIZE]; + +/* + * mbed TLS initialization function + */ +void mbedtls_init(void) +{ + static int ready; + + if (!ready) { + /* Initialize the mbed TLS heap */ + mbedtls_memory_buffer_alloc_init(heap, MBEDTLS_HEAP_SIZE); + ready = 1; + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_common.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_common.mk new file mode 100644 index 0000000..5186f16 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_common.mk @@ -0,0 +1,59 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +ifneq (${MBEDTLS_COMMON_MK},1) +MBEDTLS_COMMON_MK := 1 + +# MBEDTLS_DIR must be set to the mbed TLS main directory (it must contain +# the 'include' and 'library' subdirectories). +ifeq (${MBEDTLS_DIR},) + $(error Error: MBEDTLS_DIR not set) +endif + +INCLUDES += -I${MBEDTLS_DIR}/include \ + -Iinclude/drivers/auth/mbedtls + +# Specify mbed TLS configuration file +MBEDTLS_CONFIG_FILE := "" +$(eval $(call add_define,MBEDTLS_CONFIG_FILE)) + +MBEDTLS_COMMON_SOURCES := drivers/auth/mbedtls/mbedtls_common.c \ + $(addprefix ${MBEDTLS_DIR}/library/, \ + asn1parse.c \ + asn1write.c \ + memory_buffer_alloc.c \ + oid.c \ + platform.c \ + ) + +BL1_SOURCES += ${MBEDTLS_COMMON_SOURCES} +BL2_SOURCES += ${MBEDTLS_COMMON_SOURCES} + +endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_crypto.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_crypto.c new file mode 100644 index 0000000..1a96e8f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_crypto.c @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include +#include +#include +#include + +/* mbed TLS headers */ +#include +#include +#include +#include + +#define LIB_NAME "mbed TLS" + +/* + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL + * } + * + * SubjectPublicKeyInfo ::= SEQUENCE { + * algorithm AlgorithmIdentifier, + * subjectPublicKey BIT STRING + * } + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm AlgorithmIdentifier, + * digest OCTET STRING + * } + */ + +/* + * Initialize the library and export the descriptor + */ +static void init(void) +{ + /* Initialize mbed TLS */ + mbedtls_init(); +} + +/* + * Verify a signature. + * + * Parameters are passed using the DER encoding format following the ASN.1 + * structures detailed above. + */ +static int verify_signature(void *data_ptr, unsigned int data_len, + void *sig_ptr, unsigned int sig_len, + void *sig_alg, unsigned int sig_alg_len, + void *pk_ptr, unsigned int pk_len) +{ + mbedtls_asn1_buf sig_oid, sig_params; + mbedtls_asn1_buf signature; + mbedtls_md_type_t md_alg; + mbedtls_pk_type_t pk_alg; + mbedtls_pk_context pk; + int rc; + void *sig_opts = NULL; + const mbedtls_md_info_t *md_info; + unsigned char *p, *end; + unsigned char hash[MBEDTLS_MD_MAX_SIZE]; + + /* Get pointers to signature OID and parameters */ + p = (unsigned char *)sig_alg; + end = (unsigned char *)(p + sig_alg_len); + rc = mbedtls_asn1_get_alg(&p, end, &sig_oid, &sig_params); + if (rc != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + /* Get the actual signature algorithm (MD + PK) */ + rc = mbedtls_oid_get_sig_alg(&sig_oid, &md_alg, &pk_alg); + if (rc != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + /* Parse the public key */ + mbedtls_pk_init(&pk); + p = (unsigned char *)pk_ptr; + end = (unsigned char *)(p + pk_len); + rc = mbedtls_pk_parse_subpubkey(&p, end, &pk); + if (rc != 0) { + return CRYPTO_ERR_SIGNATURE; + } + + /* Get the signature (bitstring) */ + p = (unsigned char *)sig_ptr; + end = (unsigned char *)(p + sig_len); + signature.tag = *p; + rc = mbedtls_asn1_get_bitstring_null(&p, end, &signature.len); + if (rc != 0) { + rc = CRYPTO_ERR_SIGNATURE; + goto end; + } + signature.p = p; + + /* Calculate the hash of the data */ + md_info = mbedtls_md_info_from_type(md_alg); + if (md_info == NULL) { + rc = CRYPTO_ERR_SIGNATURE; + goto end; + } + p = (unsigned char *)data_ptr; + rc = mbedtls_md(md_info, p, data_len, hash); + if (rc != 0) { + rc = CRYPTO_ERR_SIGNATURE; + goto end; + } + + /* Verify the signature */ + rc = mbedtls_pk_verify_ext(pk_alg, sig_opts, &pk, md_alg, hash, + mbedtls_md_get_size(md_info), + signature.p, signature.len); + if (rc != 0) { + rc = CRYPTO_ERR_SIGNATURE; + goto end; + } + + /* Signature verification success */ + rc = CRYPTO_SUCCESS; + +end: + mbedtls_pk_free(&pk); + return rc; +} + +/* + * Match a hash + * + * Digest info is passed in DER format following the ASN.1 structure detailed + * above. + */ +static int verify_hash(void *data_ptr, unsigned int data_len, + void *digest_info_ptr, unsigned int digest_info_len) +{ + mbedtls_asn1_buf hash_oid, params; + mbedtls_md_type_t md_alg; + const mbedtls_md_info_t *md_info; + unsigned char *p, *end, *hash; + unsigned char data_hash[MBEDTLS_MD_MAX_SIZE]; + size_t len; + int rc; + + /* Digest info should be an MBEDTLS_ASN1_SEQUENCE */ + p = (unsigned char *)digest_info_ptr; + end = p + digest_info_len; + rc = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + /* Get the hash algorithm */ + rc = mbedtls_asn1_get_alg(&p, end, &hash_oid, ¶ms); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + rc = mbedtls_oid_get_md_alg(&hash_oid, &md_alg); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + md_info = mbedtls_md_info_from_type(md_alg); + if (md_info == NULL) { + return CRYPTO_ERR_HASH; + } + + /* Hash should be octet string type */ + rc = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_OCTET_STRING); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + /* Length of hash must match the algorithm's size */ + if (len != mbedtls_md_get_size(md_info)) { + return CRYPTO_ERR_HASH; + } + hash = p; + + /* Calculate the hash of the data */ + p = (unsigned char *)data_ptr; + rc = mbedtls_md(md_info, p, data_len, data_hash); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + /* Compare values */ + rc = memcmp(data_hash, hash, mbedtls_md_get_size(md_info)); + if (rc != 0) { + return CRYPTO_ERR_HASH; + } + + return CRYPTO_SUCCESS; +} + +/* + * Register crypto library descriptor + */ +REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_crypto.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_crypto.mk new file mode 100644 index 0000000..275ed55 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_crypto.mk @@ -0,0 +1,72 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +include drivers/auth/mbedtls/mbedtls_common.mk + +# The platform may define the variable 'MBEDTLS_KEY_ALG' to select the key +# algorithm to use. Default algorithm is ECDSA. +ifeq (${MBEDTLS_KEY_ALG},) + MBEDTLS_KEY_ALG := rsa +endif + +MBEDTLS_CRYPTO_SOURCES := drivers/auth/mbedtls/mbedtls_crypto.c \ + $(addprefix ${MBEDTLS_DIR}/library/, \ + bignum.c \ + md.c \ + md_wrap.c \ + pk.c \ + pk_wrap.c \ + pkparse.c \ + pkwrite.c \ + sha256.c \ + ) + +# Key algorithm specific files +ifeq (${MBEDTLS_KEY_ALG},ecdsa) + MBEDTLS_CRYPTO_SOURCES += $(addprefix ${MBEDTLS_DIR}/library/, \ + ecdsa.c \ + ecp_curves.c \ + ecp.c \ + ) + MBEDTLS_KEY_ALG_ID := MBEDTLS_ECDSA +else ifeq (${MBEDTLS_KEY_ALG},rsa) + MBEDTLS_CRYPTO_SOURCES += $(addprefix ${MBEDTLS_DIR}/library/, \ + rsa.c \ + ) + MBEDTLS_KEY_ALG_ID := MBEDTLS_RSA +else + $(error "MBEDTLS_KEY_ALG=${MBEDTLS_KEY_ALG} not supported on mbed TLS") +endif + +# mbed TLS libraries rely on this define to build correctly +$(eval $(call add_define,MBEDTLS_KEY_ALG_ID)) + +BL1_SOURCES += ${MBEDTLS_CRYPTO_SOURCES} +BL2_SOURCES += ${MBEDTLS_CRYPTO_SOURCES} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_x509.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_x509.mk new file mode 100644 index 0000000..3f9420d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_x509.mk @@ -0,0 +1,40 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +include drivers/auth/mbedtls/mbedtls_common.mk + +MBEDTLS_X509_SOURCES := drivers/auth/mbedtls/mbedtls_x509_parser.c \ + $(addprefix ${MBEDTLS_DIR}/library/, \ + x509.c \ + x509_crt.c \ + ) + +BL1_SOURCES += ${MBEDTLS_X509_SOURCES} +BL2_SOURCES += ${MBEDTLS_X509_SOURCES} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_x509_parser.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_x509_parser.c new file mode 100644 index 0000000..1a6a9a7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/mbedtls/mbedtls_x509_parser.c @@ -0,0 +1,465 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * X509 parser based on mbed TLS + * + * This module implements functions to check the integrity of a X509v3 + * certificate ASN.1 structure and extract authentication parameters from the + * extensions field, such as an image hash or a public key. + */ + +#include +#include +#include +#include +#include +#include + +/* mbed TLS headers */ +#include +#include +#include + +/* Maximum OID string length ("a.b.c.d.e.f ...") */ +#define MAX_OID_STR_LEN 64 + +#define LIB_NAME "mbed TLS X509v3" + +/* Temporary variables to speed up the authentication parameters search. These + * variables are assigned once during the integrity check and used any time an + * authentication parameter is requested, so we do not have to parse the image + * again */ +static mbedtls_asn1_buf tbs; +static mbedtls_asn1_buf v3_ext; +static mbedtls_asn1_buf pk; +static mbedtls_asn1_buf sig_alg; +static mbedtls_asn1_buf signature; + +/* + * Get X509v3 extension + * + * Global variable 'v3_ext' must point to the extensions region + * in the certificate. No need to check for errors since the image has passed + * the integrity check. + */ +static int get_ext(const char *oid, void **ext, unsigned int *ext_len) +{ + int oid_len; + size_t len; + unsigned char *end_ext_data, *end_ext_octet; + unsigned char *p; + const unsigned char *end; + char oid_str[MAX_OID_STR_LEN]; + mbedtls_asn1_buf extn_oid; + int is_critical; + + assert(oid != NULL); + + p = v3_ext.p; + end = v3_ext.p + v3_ext.len; + + mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + + while (p < end) { + memset(&extn_oid, 0x0, sizeof(extn_oid)); + is_critical = 0; /* DEFAULT FALSE */ + + mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + end_ext_data = p + len; + + /* Get extension ID */ + extn_oid.tag = *p; + mbedtls_asn1_get_tag(&p, end, &extn_oid.len, MBEDTLS_ASN1_OID); + extn_oid.p = p; + p += extn_oid.len; + + /* Get optional critical */ + mbedtls_asn1_get_bool(&p, end_ext_data, &is_critical); + + /* Extension data */ + mbedtls_asn1_get_tag(&p, end_ext_data, &len, + MBEDTLS_ASN1_OCTET_STRING); + end_ext_octet = p + len; + + /* Detect requested extension */ + oid_len = mbedtls_oid_get_numeric_string(oid_str, + MAX_OID_STR_LEN, + &extn_oid); + if (oid_len == MBEDTLS_ERR_OID_BUF_TOO_SMALL) { + return IMG_PARSER_ERR; + } + if ((oid_len == strlen(oid_str)) && !strcmp(oid, oid_str)) { + *ext = (void *)p; + *ext_len = (unsigned int)len; + return IMG_PARSER_OK; + } + + /* Next */ + p = end_ext_octet; + } + + return IMG_PARSER_ERR_NOT_FOUND; +} + + +/* + * Check the integrity of the certificate ASN.1 structure. + * Extract the relevant data that will be used later during authentication. + */ +static int cert_parse(void *img, unsigned int img_len) +{ + int ret, is_critical; + size_t len; + unsigned char *p, *end, *crt_end; + mbedtls_asn1_buf sig_alg1, sig_alg2; + + p = (unsigned char *)img; + len = img_len; + end = p + len; + + /* + * Certificate ::= SEQUENCE { + * tbsCertificate TBSCertificate, + * signatureAlgorithm AlgorithmIdentifier, + * signatureValue BIT STRING } + */ + ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + + if (len > (size_t)(end - p)) { + return IMG_PARSER_ERR_FORMAT; + } + crt_end = p + len; + + /* + * TBSCertificate ::= SEQUENCE { + */ + tbs.p = p; + ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + end = p + len; + tbs.len = end - tbs.p; + + /* + * Version ::= INTEGER { v1(0), v2(1), v3(2) } + */ + ret = mbedtls_asn1_get_tag(&p, end, &len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | + MBEDTLS_ASN1_CONSTRUCTED | 0); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + p += len; + + /* + * CertificateSerialNumber ::= INTEGER + */ + ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_INTEGER); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + p += len; + + /* + * signature AlgorithmIdentifier + */ + sig_alg1.p = p; + ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + if ((end - p) < 1) { + return IMG_PARSER_ERR_FORMAT; + } + sig_alg1.len = (p + len) - sig_alg1.p; + p += len; + + /* + * issuer Name + */ + ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + p += len; + + /* + * Validity ::= SEQUENCE { + * notBefore Time, + * notAfter Time } + * + */ + ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + p += len; + + /* + * subject Name + */ + ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + p += len; + + /* + * SubjectPublicKeyInfo + */ + pk.p = p; + ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + pk.len = (p + len) - pk.p; + p += len; + + /* + * issuerUniqueID [1] IMPLICIT UniqueIdentifier OPTIONAL, + */ + ret = mbedtls_asn1_get_tag(&p, end, &len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | + MBEDTLS_ASN1_CONSTRUCTED | 1); + if (ret != 0) { + if (ret != MBEDTLS_ERR_ASN1_UNEXPECTED_TAG) { + return IMG_PARSER_ERR_FORMAT; + } + } else { + p += len; + } + + /* + * subjectUniqueID [2] IMPLICIT UniqueIdentifier OPTIONAL, + */ + ret = mbedtls_asn1_get_tag(&p, end, &len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | + MBEDTLS_ASN1_CONSTRUCTED | 2); + if (ret != 0) { + if (ret != MBEDTLS_ERR_ASN1_UNEXPECTED_TAG) { + return IMG_PARSER_ERR_FORMAT; + } + } else { + p += len; + } + + /* + * extensions [3] EXPLICIT Extensions OPTIONAL + */ + ret = mbedtls_asn1_get_tag(&p, end, &len, + MBEDTLS_ASN1_CONTEXT_SPECIFIC | + MBEDTLS_ASN1_CONSTRUCTED | 3); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + + /* + * Extensions ::= SEQUENCE SIZE (1..MAX) OF Extension + */ + v3_ext.p = p; + ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + v3_ext.len = (p + len) - v3_ext.p; + + /* + * Check extensions integrity + */ + while (p < end) { + ret = mbedtls_asn1_get_tag(&p, end, &len, + MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + + /* Get extension ID */ + ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_OID); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + p += len; + + /* Get optional critical */ + ret = mbedtls_asn1_get_bool(&p, end, &is_critical); + if ((ret != 0) && (ret != MBEDTLS_ERR_ASN1_UNEXPECTED_TAG)) { + return IMG_PARSER_ERR_FORMAT; + } + + /* Data should be octet string type */ + ret = mbedtls_asn1_get_tag(&p, end, &len, + MBEDTLS_ASN1_OCTET_STRING); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + p += len; + } + + if (p != end) { + return IMG_PARSER_ERR_FORMAT; + } + + end = crt_end; + + /* + * } + * -- end of TBSCertificate + * + * signatureAlgorithm AlgorithmIdentifier + */ + sig_alg2.p = p; + ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_CONSTRUCTED | + MBEDTLS_ASN1_SEQUENCE); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + if ((end - p) < 1) { + return IMG_PARSER_ERR_FORMAT; + } + sig_alg2.len = (p + len) - sig_alg2.p; + p += len; + + /* Compare both signature algorithms */ + if (sig_alg1.len != sig_alg2.len) { + return IMG_PARSER_ERR_FORMAT; + } + if (0 != memcmp(sig_alg1.p, sig_alg2.p, sig_alg1.len)) { + return IMG_PARSER_ERR_FORMAT; + } + memcpy(&sig_alg, &sig_alg1, sizeof(sig_alg)); + + /* + * signatureValue BIT STRING + */ + signature.p = p; + ret = mbedtls_asn1_get_tag(&p, end, &len, MBEDTLS_ASN1_BIT_STRING); + if (ret != 0) { + return IMG_PARSER_ERR_FORMAT; + } + signature.len = (p + len) - signature.p; + p += len; + + /* Check certificate length */ + if (p != end) { + return IMG_PARSER_ERR_FORMAT; + } + + return IMG_PARSER_OK; +} + + +/* Exported functions */ + +static void init(void) +{ + mbedtls_init(); +} + +static int check_integrity(void *img, unsigned int img_len) +{ + return cert_parse(img, img_len); +} + +/* + * Extract an authentication parameter from an X509v3 certificate + * + * This function returns a pointer to the extracted data and its length. + * Depending on the type of parameter, a pointer to the data stored in the + * certificate may be returned (i.e. an octet string containing a hash). Other + * data may need to be copied and formatted (i.e. integers). In the later case, + * a buffer of the correct type needs to be statically allocated, filled and + * returned. + */ +static int get_auth_param(const auth_param_type_desc_t *type_desc, + void *img, unsigned int img_len, + void **param, unsigned int *param_len) +{ + int rc = IMG_PARSER_OK; + + /* We do not use img because the check_integrity function has already + * extracted the relevant data (v3_ext, pk, sig_alg, etc) */ + + switch (type_desc->type) { + case AUTH_PARAM_RAW_DATA: + /* Data to be signed */ + *param = (void *)tbs.p; + *param_len = (unsigned int)tbs.len; + break; + case AUTH_PARAM_HASH: + case AUTH_PARAM_NV_CTR: + /* All these parameters are included as X509v3 extensions */ + rc = get_ext(type_desc->cookie, param, param_len); + break; + case AUTH_PARAM_PUB_KEY: + if (type_desc->cookie != 0) { + /* Get public key from extension */ + rc = get_ext(type_desc->cookie, param, param_len); + } else { + /* Get the subject public key */ + *param = (void *)pk.p; + *param_len = (unsigned int)pk.len; + } + break; + case AUTH_PARAM_SIG_ALG: + /* Get the certificate signature algorithm */ + *param = (void *)sig_alg.p; + *param_len = (unsigned int)sig_alg.len; + break; + case AUTH_PARAM_SIG: + /* Get the certificate signature */ + *param = (void *)signature.p; + *param_len = (unsigned int)signature.len; + break; + default: + rc = IMG_PARSER_ERR_NOT_FOUND; + break; + } + + return rc; +} + +REGISTER_IMG_PARSER_LIB(IMG_CERT, LIB_NAME, init, \ + check_integrity, get_auth_param); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/tbbr/tbbr_cot.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/tbbr/tbbr_cot.c new file mode 100644 index 0000000..dae35d1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/auth/tbbr/tbbr_cot.c @@ -0,0 +1,619 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +/* + * Maximum key and hash sizes (in DER format) + */ +#define PK_DER_LEN 294 +#define HASH_DER_LEN 51 + +/* + * The platform must allocate buffers to store the authentication parameters + * extracted from the certificates. In this case, because of the way the CoT is + * established, we can reuse some of the buffers on different stages + */ +static unsigned char tb_fw_hash_buf[HASH_DER_LEN]; +static unsigned char scp_fw_hash_buf[HASH_DER_LEN]; +static unsigned char soc_fw_hash_buf[HASH_DER_LEN]; +static unsigned char tos_fw_hash_buf[HASH_DER_LEN]; +static unsigned char nt_world_bl_hash_buf[HASH_DER_LEN]; +static unsigned char trusted_world_pk_buf[PK_DER_LEN]; +static unsigned char non_trusted_world_pk_buf[PK_DER_LEN]; +static unsigned char content_pk_buf[PK_DER_LEN]; + +/* + * Parameter type descriptors + */ +static auth_param_type_desc_t trusted_nv_ctr = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_NV_CTR, TRUSTED_FW_NVCOUNTER_OID); +static auth_param_type_desc_t non_trusted_nv_ctr = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_NV_CTR, NON_TRUSTED_FW_NVCOUNTER_OID); + +static auth_param_type_desc_t subject_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, 0); +static auth_param_type_desc_t sig = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_SIG, 0); +static auth_param_type_desc_t sig_alg = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_SIG_ALG, 0); +static auth_param_type_desc_t raw_data = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_RAW_DATA, 0); + +static auth_param_type_desc_t trusted_world_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, TRUSTED_WORLD_PK_OID); +static auth_param_type_desc_t non_trusted_world_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, NON_TRUSTED_WORLD_PK_OID); + +static auth_param_type_desc_t scp_fw_content_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, SCP_FW_CONTENT_CERT_PK_OID); +static auth_param_type_desc_t soc_fw_content_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, SOC_FW_CONTENT_CERT_PK_OID); +static auth_param_type_desc_t tos_fw_content_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, TRUSTED_OS_FW_CONTENT_CERT_PK_OID); +static auth_param_type_desc_t nt_fw_content_pk = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_PUB_KEY, NON_TRUSTED_FW_CONTENT_CERT_PK_OID); + +static auth_param_type_desc_t tb_fw_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, TRUSTED_BOOT_FW_HASH_OID); +static auth_param_type_desc_t scp_fw_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, SCP_FW_HASH_OID); +static auth_param_type_desc_t soc_fw_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, SOC_AP_FW_HASH_OID); +static auth_param_type_desc_t tos_fw_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, TRUSTED_OS_FW_HASH_OID); +static auth_param_type_desc_t nt_world_bl_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, NON_TRUSTED_WORLD_BOOTLOADER_HASH_OID); +static auth_param_type_desc_t scp_bl2u_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, SCP_FWU_CFG_HASH_OID); +static auth_param_type_desc_t bl2u_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, AP_FWU_CFG_HASH_OID); +static auth_param_type_desc_t ns_bl2u_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, FWU_HASH_OID); + +/* + * TBBR Chain of trust definition + */ +static const auth_img_desc_t cot_desc[] = { + /* + * BL2 + */ + [TRUSTED_BOOT_FW_CERT_ID] = { + .img_id = TRUSTED_BOOT_FW_CERT_ID, + .img_type = IMG_CERT, + .parent = NULL, + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &subject_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &trusted_nv_ctr, + .plat_nv_ctr = &trusted_nv_ctr + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &tb_fw_hash, + .data = { + .ptr = (void *)tb_fw_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } + }, + [BL2_IMAGE_ID] = { + .img_id = BL2_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[TRUSTED_BOOT_FW_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &tb_fw_hash, + } + } + } + }, + /* + * Trusted key certificate + */ + [TRUSTED_KEY_CERT_ID] = { + .img_id = TRUSTED_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = NULL, + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &subject_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &trusted_nv_ctr, + .plat_nv_ctr = &trusted_nv_ctr + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &trusted_world_pk, + .data = { + .ptr = (void *)trusted_world_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + }, + [1] = { + .type_desc = &non_trusted_world_pk, + .data = { + .ptr = (void *)non_trusted_world_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + } + } + }, + /* + * SCP Firmware + */ + [SCP_FW_KEY_CERT_ID] = { + .img_id = SCP_FW_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[TRUSTED_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &trusted_world_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &trusted_nv_ctr, + .plat_nv_ctr = &trusted_nv_ctr + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &scp_fw_content_pk, + .data = { + .ptr = (void *)content_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + } + } + }, + [SCP_FW_CONTENT_CERT_ID] = { + .img_id = SCP_FW_CONTENT_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[SCP_FW_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &scp_fw_content_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &trusted_nv_ctr, + .plat_nv_ctr = &trusted_nv_ctr + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &scp_fw_hash, + .data = { + .ptr = (void *)scp_fw_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } + }, + [SCP_BL2_IMAGE_ID] = { + .img_id = SCP_BL2_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[SCP_FW_CONTENT_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &scp_fw_hash, + } + } + } + }, + /* + * SoC Firmware + */ + [SOC_FW_KEY_CERT_ID] = { + .img_id = SOC_FW_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[TRUSTED_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &trusted_world_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &trusted_nv_ctr, + .plat_nv_ctr = &trusted_nv_ctr + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &soc_fw_content_pk, + .data = { + .ptr = (void *)content_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + } + } + }, + [SOC_FW_CONTENT_CERT_ID] = { + .img_id = SOC_FW_CONTENT_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[SOC_FW_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &soc_fw_content_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &trusted_nv_ctr, + .plat_nv_ctr = &trusted_nv_ctr + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &soc_fw_hash, + .data = { + .ptr = (void *)soc_fw_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } + }, + [BL31_IMAGE_ID] = { + .img_id = BL31_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[SOC_FW_CONTENT_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &soc_fw_hash, + } + } + } + }, + /* + * Trusted OS Firmware + */ + [TRUSTED_OS_FW_KEY_CERT_ID] = { + .img_id = TRUSTED_OS_FW_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[TRUSTED_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &trusted_world_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &trusted_nv_ctr, + .plat_nv_ctr = &trusted_nv_ctr + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &tos_fw_content_pk, + .data = { + .ptr = (void *)content_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + } + } + }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { + .img_id = TRUSTED_OS_FW_CONTENT_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[TRUSTED_OS_FW_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &tos_fw_content_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &trusted_nv_ctr, + .plat_nv_ctr = &trusted_nv_ctr + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &tos_fw_hash, + .data = { + .ptr = (void *)tos_fw_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } + }, + [BL32_IMAGE_ID] = { + .img_id = BL32_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[TRUSTED_OS_FW_CONTENT_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &tos_fw_hash, + } + } + } + }, + /* + * Non-Trusted Firmware + */ + [NON_TRUSTED_FW_KEY_CERT_ID] = { + .img_id = NON_TRUSTED_FW_KEY_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[TRUSTED_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &non_trusted_world_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &non_trusted_nv_ctr, + .plat_nv_ctr = &non_trusted_nv_ctr + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &nt_fw_content_pk, + .data = { + .ptr = (void *)content_pk_buf, + .len = (unsigned int)PK_DER_LEN + } + } + } + }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { + .img_id = NON_TRUSTED_FW_CONTENT_CERT_ID, + .img_type = IMG_CERT, + .parent = &cot_desc[NON_TRUSTED_FW_KEY_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &nt_fw_content_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + }, + [1] = { + .type = AUTH_METHOD_NV_CTR, + .param.nv_ctr = { + .cert_nv_ctr = &non_trusted_nv_ctr, + .plat_nv_ctr = &non_trusted_nv_ctr + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &nt_world_bl_hash, + .data = { + .ptr = (void *)nt_world_bl_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } + }, + [BL33_IMAGE_ID] = { + .img_id = BL33_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[NON_TRUSTED_FW_CONTENT_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &nt_world_bl_hash, + } + } + } + }, + /* + * FWU auth descriptor. + */ + [FWU_CERT_ID] = { + .img_id = FWU_CERT_ID, + .img_type = IMG_CERT, + .parent = NULL, + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_SIG, + .param.sig = { + .pk = &subject_pk, + .sig = &sig, + .alg = &sig_alg, + .data = &raw_data, + } + } + }, + .authenticated_data = { + [0] = { + .type_desc = &scp_bl2u_hash, + .data = { + .ptr = (void *)scp_fw_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + }, + [1] = { + .type_desc = &bl2u_hash, + .data = { + .ptr = (void *)tb_fw_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + }, + [2] = { + .type_desc = &ns_bl2u_hash, + .data = { + .ptr = (void *)nt_world_bl_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + } + } + }, + /* + * SCP_BL2U + */ + [SCP_BL2U_IMAGE_ID] = { + .img_id = SCP_BL2U_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[FWU_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &scp_bl2u_hash, + } + } + } + }, + /* + * BL2U + */ + [BL2U_IMAGE_ID] = { + .img_id = BL2U_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[FWU_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &bl2u_hash, + } + } + } + }, + /* + * NS_BL2U + */ + [NS_BL2U_IMAGE_ID] = { + .img_id = NS_BL2U_IMAGE_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[FWU_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &ns_bl2u_hash, + } + } + } + } +}; + +/* Register the CoT in the authentication module */ +REGISTER_COT(cot_desc); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/cadence/uart/aarch64/cdns_console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/cadence/uart/aarch64/cdns_console.S new file mode 100644 index 0000000..2c7960d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/cadence/uart/aarch64/cdns_console.S @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + + .globl console_core_init + .globl console_core_putc + .globl console_core_getc + + /* ----------------------------------------------- + * int console_core_init(unsigned long base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * We assume that the bootloader already set up + * the HW (baud, ...) and only enable the trans- + * mitter and receiver here. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * Out: return 1 on success else 0 on error + * Clobber list : x1, x2, x3 + * ----------------------------------------------- + */ +func console_core_init + /* Check the input base address */ + cbz x0, core_init_fail + /* Check baud rate and uart clock for sanity */ + cbz w1, core_init_fail + cbz w2, core_init_fail + + /* RX/TX enabled & reset */ + mov w3, #(R_UART_CR_TX_EN | R_UART_CR_RX_EN | R_UART_CR_TXRST | R_UART_CR_RXRST) + str w3, [x0, #R_UART_CR] + + mov w0, #1 + ret +core_init_fail: + mov w0, wzr + ret +endfunc console_core_init + + /* -------------------------------------------------------- + * int console_core_putc(int c, unsigned long base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_core_putc + /* Check the input parameter */ + cbz x1, putc_error + /* Prepend '\r' to '\n' */ + cmp w0, #0xA + b.ne 2f +1: + /* Check if the transmit FIFO is full */ + ldr w2, [x1, #R_UART_SR] + tbnz w2, #UART_SR_INTR_TFUL_BIT, 1b + mov w2, #0xD + str w2, [x1, #R_UART_TX] +2: + /* Check if the transmit FIFO is full */ + ldr w2, [x1, #R_UART_SR] + tbnz w2, #UART_SR_INTR_TFUL_BIT, 2b + str w0, [x1, #R_UART_TX] + ret +putc_error: + mov w0, #-1 + ret +endfunc console_core_putc + + /* --------------------------------------------- + * int console_core_getc(unsigned long base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * In : x0 - console base address + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_getc + cbz x0, getc_error +1: + /* Check if the receive FIFO is empty */ + ldr w1, [x0, #R_UART_SR] + tbnz w1, #UART_SR_INTR_REMPTY_BIT, 1b + ldr w1, [x0, #R_UART_RX] + mov w0, w1 + ret +getc_error: + mov w0, #-1 + ret +endfunc console_core_getc diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/cadence/uart/cdns_console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/cadence/uart/cdns_console.S new file mode 100644 index 0000000..f727838 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/cadence/uart/cdns_console.S @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#if !ERROR_DEPRECATED +#include "./aarch64/cdns_console.S" +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/aarch32/console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/aarch32/console.S new file mode 100644 index 0000000..2993345 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/aarch32/console.S @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include + + .globl console_init + .globl console_uninit + .globl console_putc + .globl console_getc + + /* + * The console base is in the data section and not in .bss + * even though it is zero-init. In particular, this allows + * the console functions to start using this variable before + * the runtime memory is initialized for images which do not + * need to copy the .data section from ROM to RAM. + */ +.section .data.console_base ; .align 2 + console_base: .word 0x0 + + /* ----------------------------------------------- + * int console_init(uintptr_t base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. It saves + * the console base to the data section. + * In: r0 - console base address + * r1 - Uart clock in Hz + * r2 - Baud rate + * out: return 1 on success else 0 on error + * Clobber list : r1 - r3 + * ----------------------------------------------- + */ +func console_init + /* Check the input base address */ + cmp r0, #0 + beq init_fail + ldr r3, =console_base + str r0, [r3] + b console_core_init +init_fail: + bx lr +endfunc console_init + + /* ----------------------------------------------- + * void console_uninit(void) + * Function to finish the use of console driver. + * It sets the console_base as NULL so that any + * further invocation of `console_putc` or + * `console_getc` APIs would return error. + * ----------------------------------------------- + */ +func console_uninit + mov r0, #0 + ldr r3, =console_base + str r0, [r3] + bx lr +endfunc console_uninit + + /* --------------------------------------------- + * int console_putc(int c) + * Function to output a character over the + * console. It returns the character printed on + * success or -1 on error. + * In : r0 - character to be printed + * Out : return -1 on error else return character. + * Clobber list : r1, r2 + * --------------------------------------------- + */ +func console_putc + ldr r2, =console_base + ldr r1, [r2] + b console_core_putc +endfunc console_putc + + /* --------------------------------------------- + * int console_getc(void) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * Clobber list : r0, r1 + * --------------------------------------------- + */ +func console_getc + ldr r1, =console_base + ldr r0, [r1] + b console_core_getc +endfunc console_getc diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/aarch32/skeleton_console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/aarch32/skeleton_console.S new file mode 100644 index 0000000..383874e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/aarch32/skeleton_console.S @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include + + /* + * This file contains a skeleton console implementation that can + * be used as basis for a real console implementation by platforms + * that do not contain PL011 hardware. + */ + + .globl console_core_init + .globl console_core_putc + .globl console_core_getc + + /* ----------------------------------------------- + * int console_core_init(uintptr_t base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * In: r0 - console base address + * r1 - Uart clock in Hz + * r2 - Baud rate + * Out: return 1 on success else 0 on error + * Clobber list : r1, r2 + * ----------------------------------------------- + */ +func console_core_init + /* Check the input base address */ + cmp r0, #0 + beq core_init_fail + /* Check baud rate and uart clock for sanity */ + cmp r1, #0 + beq core_init_fail + cmp r2, #0 + beq core_init_fail + /* Insert implementation here */ + mov r0, #1 + bx lr +core_init_fail: + mov r0, #0 + bx lr +endfunc console_core_init + + /* -------------------------------------------------------- + * int console_core_putc(int c, uintptr_t base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : r0 - character to be printed + * r1 - console base address + * Out : return -1 on error else return character. + * Clobber list : r2 + * -------------------------------------------------------- + */ +func console_core_putc + /* Check the input parameter */ + cmp r1, #0 + beq putc_error + /* Insert implementation here */ + bx lr +putc_error: + mov r0, #-1 + bx lr +endfunc console_core_putc + + /* --------------------------------------------- + * int console_core_getc(uintptr_t base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * In : r0 - console base address + * Clobber list : r0, r1 + * --------------------------------------------- + */ +func console_core_getc + cmp r0, #0 + beq getc_error + /* Insert implementation here */ + bx lr +getc_error: + mov r0, #-1 + bx lr +endfunc console_core_getc diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/aarch64/console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/aarch64/console.S new file mode 100644 index 0000000..bdd5f4c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/aarch64/console.S @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include + + .globl console_init + .globl console_uninit + .globl console_putc + .globl console_getc + + /* + * The console base is in the data section and not in .bss + * even though it is zero-init. In particular, this allows + * the console functions to start using this variable before + * the runtime memory is initialized for images which do not + * need to copy the .data section from ROM to RAM. + */ +.section .data.console_base ; .align 3 + console_base: .quad 0x0 + + /* ----------------------------------------------- + * int console_init(uintptr_t base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. It saves + * the console base to the data section. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * out: return 1 on success else 0 on error + * Clobber list : x1 - x4 + * ----------------------------------------------- + */ +func console_init + /* Check the input base address */ + cbz x0, init_fail + adrp x3, console_base + str x0, [x3, :lo12:console_base] + b console_core_init +init_fail: + ret +endfunc console_init + + /* ----------------------------------------------- + * void console_uninit(void) + * Function to finish the use of console driver. + * It sets the console_base as NULL so that any + * further invocation of `console_putc` or + * `console_getc` APIs would return error. + * ----------------------------------------------- + */ +func console_uninit + mov x0, #0 + adrp x3, console_base + str x0, [x3, :lo12:console_base] + ret +endfunc console_uninit + + /* --------------------------------------------- + * int console_putc(int c) + * Function to output a character over the + * console. It returns the character printed on + * success or -1 on error. + * In : x0 - character to be printed + * Out : return -1 on error else return character. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func console_putc + adrp x2, console_base + ldr x1, [x2, :lo12:console_base] + b console_core_putc +endfunc console_putc + + /* --------------------------------------------- + * int console_getc(void) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_getc + adrp x1, console_base + ldr x0, [x1, :lo12:console_base] + b console_core_getc +endfunc console_getc diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/aarch64/skeleton_console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/aarch64/skeleton_console.S new file mode 100644 index 0000000..1583ee7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/aarch64/skeleton_console.S @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include + + /* + * This file contains a skeleton console implementation that can + * be used as basis for a real console implementation by platforms + * that do not contain PL011 hardware. + */ + + .globl console_core_init + .globl console_core_putc + .globl console_core_getc + + /* ----------------------------------------------- + * int console_core_init(uintptr_t base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * Out: return 1 on success else 0 on error + * Clobber list : x1, x2 + * ----------------------------------------------- + */ +func console_core_init + /* Check the input base address */ + cbz x0, core_init_fail + /* Check baud rate and uart clock for sanity */ + cbz w1, core_init_fail + cbz w2, core_init_fail + /* Insert implementation here */ + mov w0, #1 + ret +core_init_fail: + mov w0, wzr + ret +endfunc console_core_init + + /* -------------------------------------------------------- + * int console_core_putc(int c, uintptr_t base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_core_putc + /* Check the input parameter */ + cbz x1, putc_error + /* Insert implementation here */ + ret +putc_error: + mov w0, #-1 + ret +endfunc console_core_putc + + /* --------------------------------------------- + * int console_core_getc(uintptr_t base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * In : x0 - console base address + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_getc + cbz x0, getc_error + /* Insert implementation here */ + ret +getc_error: + mov w0, #-1 + ret +endfunc console_core_getc diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/console.S new file mode 100644 index 0000000..e861298 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/console.S @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#if !ERROR_DEPRECATED +#include "./aarch64/console.S" +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/skeleton_console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/skeleton_console.S new file mode 100644 index 0000000..ddfd834 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/console/skeleton_console.S @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#if !ERROR_DEPRECATED +#include "./aarch64/skeleton_console.S" +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/delay_timer/delay_timer.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/delay_timer/delay_timer.c new file mode 100644 index 0000000..ed7ed52 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/delay_timer/delay_timer.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/*********************************************************** + * The delay timer implementation + ***********************************************************/ +static const timer_ops_t *ops; + +/*********************************************************** + * Delay for the given number of microseconds. The driver must + * be initialized before calling this function. + ***********************************************************/ +void udelay(uint32_t usec) +{ + assert(ops != 0 && + (ops->clk_mult != 0) && + (ops->clk_div != 0) && + (ops->get_timer_value != 0)); + + uint32_t start, delta, total_delta; + + assert(usec < UINT32_MAX / ops->clk_div); + + start = ops->get_timer_value(); + + total_delta = (usec * ops->clk_div) / ops->clk_mult; + + do { + /* + * If the timer value wraps around, the subtraction will + * overflow and it will still give the correct result. + */ + delta = start - ops->get_timer_value(); /* Decreasing counter */ + + } while (delta < total_delta); +} + +/*********************************************************** + * Delay for the given number of milliseconds. The driver must + * be initialized before calling this function. + ***********************************************************/ +void mdelay(uint32_t msec) +{ + udelay(msec*1000); +} + +/*********************************************************** + * Initialize the timer. The fields in the provided timer + * ops pointer must be valid. + ***********************************************************/ +void timer_init(const timer_ops_t *ops_ptr) +{ + assert(ops_ptr != 0 && + (ops_ptr->clk_mult != 0) && + (ops_ptr->clk_div != 0) && + (ops_ptr->get_timer_value != 0)); + + ops = ops_ptr; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/delay_timer/generic_delay_timer.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/delay_timer/generic_delay_timer.c new file mode 100644 index 0000000..4c364a3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/delay_timer/generic_delay_timer.c @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* Ticks elapsed in one second by a signal of 1 MHz */ +#define MHZ_TICKS_PER_SEC 1000000 + +static timer_ops_t ops; + +static uint32_t get_timer_value(void) +{ + /* + * Generic delay timer implementation expects the timer to be a down + * counter. We apply bitwise NOT operator to the tick values returned + * by read_cntpct_el0() to simulate the down counter. The value is + * clipped from 64 to 32 bits. + */ + return (uint32_t)(~read_cntpct_el0()); +} + +void generic_delay_timer_init_args(uint32_t mult, uint32_t div) +{ + ops.get_timer_value = get_timer_value; + ops.clk_mult = mult; + ops.clk_div = div; + + timer_init(&ops); + + VERBOSE("Generic delay timer configured with mult=%u and div=%u\n", + mult, div); +} + +void generic_delay_timer_init(void) +{ + /* Value in ticks */ + unsigned int mult = MHZ_TICKS_PER_SEC; + + /* Value in ticks per second (Hz) */ + unsigned int div = plat_get_syscnt_freq2(); + + /* Reduce multiplier and divider by dividing them repeatedly by 10 */ + while ((mult % 10 == 0) && (div % 10 == 0)) { + mult /= 10; + div /= 10; + } + + generic_delay_timer_init_args(mult, div); +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/emmc/emmc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/emmc/emmc.c new file mode 100644 index 0000000..3fae2a1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/emmc/emmc.c @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Defines a simple and generic interface to access eMMC device. + */ + +#include +#include +#include +#include +#include +#include + +static const emmc_ops_t *ops; +static unsigned int emmc_ocr_value; +static emmc_csd_t emmc_csd; +static unsigned int emmc_flags; + +static int is_cmd23_enabled(void) +{ + return (!!(emmc_flags & EMMC_FLAG_CMD23)); +} + +static int emmc_device_state(void) +{ + emmc_cmd_t cmd; + int ret; + + do { + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD13; + cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET; + cmd.resp_type = EMMC_RESPONSE_R1; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + assert((cmd.resp_data[0] & STATUS_SWITCH_ERROR) == 0); + /* Ignore improbable errors in release builds */ + (void)ret; + } while ((cmd.resp_data[0] & STATUS_READY_FOR_DATA) == 0); + return EMMC_GET_STATE(cmd.resp_data[0]); +} + +static void emmc_set_ext_csd(unsigned int ext_cmd, unsigned int value) +{ + emmc_cmd_t cmd; + int ret, state; + + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD6; + cmd.cmd_arg = EXTCSD_WRITE_BYTES | EXTCSD_CMD(ext_cmd) | + EXTCSD_VALUE(value) | 1; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + + /* wait to exit PRG state */ + do { + state = emmc_device_state(); + } while (state == EMMC_STATE_PRG); + /* Ignore improbable errors in release builds */ + (void)ret; +} + +static void emmc_set_ios(int clk, int bus_width) +{ + int ret; + + /* set IO speed & IO bus width */ + if (emmc_csd.spec_vers == 4) + emmc_set_ext_csd(CMD_EXTCSD_BUS_WIDTH, bus_width); + ret = ops->set_ios(clk, bus_width); + assert(ret == 0); + /* Ignore improbable errors in release builds */ + (void)ret; +} + +static int emmc_enumerate(int clk, int bus_width) +{ + emmc_cmd_t cmd; + int ret, state; + + ops->init(); + + /* CMD0: reset to IDLE */ + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD0; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + + while (1) { + /* CMD1: get OCR register */ + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD1; + cmd.cmd_arg = OCR_SECTOR_MODE | OCR_VDD_MIN_2V7 | + OCR_VDD_MIN_1V7; + cmd.resp_type = EMMC_RESPONSE_R3; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + emmc_ocr_value = cmd.resp_data[0]; + if (emmc_ocr_value & OCR_POWERUP) + break; + } + + /* CMD2: Card Identification */ + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD2; + cmd.resp_type = EMMC_RESPONSE_R2; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + + /* CMD3: Set Relative Address */ + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD3; + cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET; + cmd.resp_type = EMMC_RESPONSE_R1; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + + /* CMD9: CSD Register */ + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD9; + cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET; + cmd.resp_type = EMMC_RESPONSE_R2; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + memcpy(&emmc_csd, &cmd.resp_data, sizeof(cmd.resp_data)); + + /* CMD7: Select Card */ + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD7; + cmd.cmd_arg = EMMC_FIX_RCA << RCA_SHIFT_OFFSET; + cmd.resp_type = EMMC_RESPONSE_R1; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + /* wait to TRAN state */ + do { + state = emmc_device_state(); + } while (state != EMMC_STATE_TRAN); + + emmc_set_ios(clk, bus_width); + return ret; +} + +size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size) +{ + emmc_cmd_t cmd; + int ret; + + assert((ops != 0) && + (ops->read != 0) && + ((buf & EMMC_BLOCK_MASK) == 0) && + ((size & EMMC_BLOCK_MASK) == 0)); + + inv_dcache_range(buf, size); + ret = ops->prepare(lba, buf, size); + assert(ret == 0); + + if (is_cmd23_enabled()) { + memset(&cmd, 0, sizeof(emmc_cmd_t)); + /* set block count */ + cmd.cmd_idx = EMMC_CMD23; + cmd.cmd_arg = size / EMMC_BLOCK_SIZE; + cmd.resp_type = EMMC_RESPONSE_R1; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD18; + } else { + if (size > EMMC_BLOCK_SIZE) + cmd.cmd_idx = EMMC_CMD18; + else + cmd.cmd_idx = EMMC_CMD17; + } + if ((emmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE) + cmd.cmd_arg = lba * EMMC_BLOCK_SIZE; + else + cmd.cmd_arg = lba; + cmd.resp_type = EMMC_RESPONSE_R1; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + + ret = ops->read(lba, buf, size); + assert(ret == 0); + + /* wait buffer empty */ + emmc_device_state(); + + if (is_cmd23_enabled() == 0) { + if (size > EMMC_BLOCK_SIZE) { + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD12; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + } + } + /* Ignore improbable errors in release builds */ + (void)ret; + return size; +} + +size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size) +{ + emmc_cmd_t cmd; + int ret; + + assert((ops != 0) && + (ops->write != 0) && + ((buf & EMMC_BLOCK_MASK) == 0) && + ((size & EMMC_BLOCK_MASK) == 0)); + + clean_dcache_range(buf, size); + ret = ops->prepare(lba, buf, size); + assert(ret == 0); + + if (is_cmd23_enabled()) { + /* set block count */ + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD23; + cmd.cmd_arg = size / EMMC_BLOCK_SIZE; + cmd.resp_type = EMMC_RESPONSE_R1; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD25; + } else { + memset(&cmd, 0, sizeof(emmc_cmd_t)); + if (size > EMMC_BLOCK_SIZE) + cmd.cmd_idx = EMMC_CMD25; + else + cmd.cmd_idx = EMMC_CMD24; + } + if ((emmc_ocr_value & OCR_ACCESS_MODE_MASK) == OCR_BYTE_MODE) + cmd.cmd_arg = lba * EMMC_BLOCK_SIZE; + else + cmd.cmd_arg = lba; + cmd.resp_type = EMMC_RESPONSE_R1; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + + ret = ops->write(lba, buf, size); + assert(ret == 0); + + /* wait buffer empty */ + emmc_device_state(); + + if (is_cmd23_enabled() == 0) { + if (size > EMMC_BLOCK_SIZE) { + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD12; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + } + } + /* Ignore improbable errors in release builds */ + (void)ret; + return size; +} + +size_t emmc_erase_blocks(int lba, size_t size) +{ + emmc_cmd_t cmd; + int ret, state; + + assert(ops != 0); + assert((size != 0) && ((size % EMMC_BLOCK_SIZE) == 0)); + + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD35; + cmd.cmd_arg = lba; + cmd.resp_type = EMMC_RESPONSE_R1; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD36; + cmd.cmd_arg = lba + (size / EMMC_BLOCK_SIZE) - 1; + cmd.resp_type = EMMC_RESPONSE_R1; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + + memset(&cmd, 0, sizeof(emmc_cmd_t)); + cmd.cmd_idx = EMMC_CMD38; + cmd.resp_type = EMMC_RESPONSE_R1B; + ret = ops->send_cmd(&cmd); + assert(ret == 0); + + /* wait to TRAN state */ + do { + state = emmc_device_state(); + } while (state != EMMC_STATE_TRAN); + /* Ignore improbable errors in release builds */ + (void)ret; + return size; +} + +static inline void emmc_rpmb_enable(void) +{ + emmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG, + PART_CFG_BOOT_PARTITION1_ENABLE | + PART_CFG_PARTITION1_ACCESS); +} + +static inline void emmc_rpmb_disable(void) +{ + emmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG, + PART_CFG_BOOT_PARTITION1_ENABLE); +} + +size_t emmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size) +{ + size_t size_read; + + emmc_rpmb_enable(); + size_read = emmc_read_blocks(lba, buf, size); + emmc_rpmb_disable(); + return size_read; +} + +size_t emmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size) +{ + size_t size_written; + + emmc_rpmb_enable(); + size_written = emmc_write_blocks(lba, buf, size); + emmc_rpmb_disable(); + return size_written; +} + +size_t emmc_rpmb_erase_blocks(int lba, size_t size) +{ + size_t size_erased; + + emmc_rpmb_enable(); + size_erased = emmc_erase_blocks(lba, size); + emmc_rpmb_disable(); + return size_erased; +} + +void emmc_init(const emmc_ops_t *ops_ptr, int clk, int width, + unsigned int flags) +{ + assert((ops_ptr != 0) && + (ops_ptr->init != 0) && + (ops_ptr->send_cmd != 0) && + (ops_ptr->set_ios != 0) && + (ops_ptr->prepare != 0) && + (ops_ptr->read != 0) && + (ops_ptr->write != 0) && + (clk != 0) && + ((width == EMMC_BUS_WIDTH_1) || + (width == EMMC_BUS_WIDTH_4) || + (width == EMMC_BUS_WIDTH_8))); + ops = ops_ptr; + emmc_flags = flags; + + emmc_enumerate(clk, width); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/gpio/gpio.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/gpio/gpio.c new file mode 100644 index 0000000..ef6bb9c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/gpio/gpio.c @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * GPIO -- General Purpose Input/Output + * + * Defines a simple and generic interface to access GPIO device. + * + */ + +#include +#include +#include + +/* + * The gpio implementation + */ +static const gpio_ops_t *ops; + +int gpio_get_direction(int gpio) +{ + assert(ops); + assert(ops->get_direction != 0); + assert(gpio >= 0); + + return ops->get_direction(gpio); +} + +void gpio_set_direction(int gpio, int direction) +{ + assert(ops); + assert(ops->set_direction != 0); + assert((direction == GPIO_DIR_OUT) || (direction == GPIO_DIR_IN)); + assert(gpio >= 0); + + ops->set_direction(gpio, direction); +} + +int gpio_get_value(int gpio) +{ + assert(ops); + assert(ops->get_value != 0); + assert(gpio >= 0); + + return ops->get_value(gpio); +} + +void gpio_set_value(int gpio, int value) +{ + assert(ops); + assert(ops->set_value != 0); + assert((value == GPIO_LEVEL_LOW) || (value == GPIO_LEVEL_HIGH)); + assert(gpio >= 0); + + ops->set_value(gpio, value); +} + +void gpio_set_pull(int gpio, int pull) +{ + assert(ops); + assert(ops->set_pull != 0); + assert((pull == GPIO_PULL_NONE) || (pull == GPIO_PULL_UP) || + (pull == GPIO_PULL_DOWN)); + assert(gpio >= 0); + + ops->set_pull(gpio, pull); +} + +int gpio_get_pull(int gpio) +{ + assert(ops); + assert(ops->get_pull != 0); + assert(gpio >= 0); + + return ops->get_pull(gpio); +} + +/* + * Initialize the gpio. The fields in the provided gpio + * ops pointer must be valid. + */ +void gpio_init(const gpio_ops_t *ops_ptr) +{ + assert(ops_ptr != 0 && + (ops_ptr->get_direction != 0) && + (ops_ptr->set_direction != 0) && + (ops_ptr->get_value != 0) && + (ops_ptr->set_value != 0)); + + ops = ops_ptr; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_block.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_block.c new file mode 100644 index 0000000..4ec59bc --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_block.c @@ -0,0 +1,448 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + io_block_dev_spec_t *dev_spec; + uintptr_t base; + size_t file_pos; + size_t size; +} block_dev_state_t; + +#define is_power_of_2(x) ((x != 0) && ((x & (x - 1)) == 0)) + +io_type_t device_type_block(void); + +static int block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); +static int block_seek(io_entity_t *entity, int mode, ssize_t offset); +static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read); +static int block_write(io_entity_t *entity, const uintptr_t buffer, + size_t length, size_t *length_written); +static int block_close(io_entity_t *entity); +static int block_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); +static int block_dev_close(io_dev_info_t *dev_info); + +static const io_dev_connector_t block_dev_connector = { + .dev_open = block_dev_open +}; + +static const io_dev_funcs_t block_dev_funcs = { + .type = device_type_block, + .open = block_open, + .seek = block_seek, + .size = NULL, + .read = block_read, + .write = block_write, + .close = block_close, + .dev_init = NULL, + .dev_close = block_dev_close, +}; + +static block_dev_state_t state_pool[MAX_IO_BLOCK_DEVICES]; +static io_dev_info_t dev_info_pool[MAX_IO_BLOCK_DEVICES]; + +/* Track number of allocated block state */ +static unsigned int block_dev_count; + +io_type_t device_type_block(void) +{ + return IO_TYPE_BLOCK; +} + +/* Locate a block state in the pool, specified by address */ +static int find_first_block_state(const io_block_dev_spec_t *dev_spec, + unsigned int *index_out) +{ + int result = -ENOENT; + for (int index = 0; index < MAX_IO_BLOCK_DEVICES; ++index) { + /* dev_spec is used as identifier since it's unique */ + if (state_pool[index].dev_spec == dev_spec) { + result = 0; + *index_out = index; + break; + } + } + return result; +} + +/* Allocate a device info from the pool and return a pointer to it */ +static int allocate_dev_info(io_dev_info_t **dev_info) +{ + int result = -ENOMEM; + assert(dev_info != NULL); + + if (block_dev_count < MAX_IO_BLOCK_DEVICES) { + unsigned int index = 0; + result = find_first_block_state(NULL, &index); + assert(result == 0); + /* initialize dev_info */ + dev_info_pool[index].funcs = &block_dev_funcs; + dev_info_pool[index].info = (uintptr_t)&state_pool[index]; + *dev_info = &dev_info_pool[index]; + ++block_dev_count; + } + + return result; +} + + +/* Release a device info to the pool */ +static int free_dev_info(io_dev_info_t *dev_info) +{ + int result; + unsigned int index = 0; + block_dev_state_t *state; + assert(dev_info != NULL); + + state = (block_dev_state_t *)dev_info->info; + result = find_first_block_state(state->dev_spec, &index); + if (result == 0) { + /* free if device info is valid */ + memset(state, 0, sizeof(block_dev_state_t)); + memset(dev_info, 0, sizeof(io_dev_info_t)); + --block_dev_count; + } + + return result; +} + +static int block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity) +{ + block_dev_state_t *cur; + io_block_spec_t *region; + + assert((dev_info->info != (uintptr_t)NULL) && + (spec != (uintptr_t)NULL) && + (entity->info == (uintptr_t)NULL)); + + region = (io_block_spec_t *)spec; + cur = (block_dev_state_t *)dev_info->info; + assert(((region->offset % cur->dev_spec->block_size) == 0) && + ((region->length % cur->dev_spec->block_size) == 0)); + + cur->base = region->offset; + cur->size = region->length; + cur->file_pos = 0; + + entity->info = (uintptr_t)cur; + return 0; +} + +/* parameter offset is relative address at here */ +static int block_seek(io_entity_t *entity, int mode, ssize_t offset) +{ + block_dev_state_t *cur; + + assert(entity->info != (uintptr_t)NULL); + + cur = (block_dev_state_t *)entity->info; + assert((offset >= 0) && (offset < cur->size)); + + switch (mode) { + case IO_SEEK_SET: + cur->file_pos = offset; + break; + case IO_SEEK_CUR: + cur->file_pos += offset; + break; + default: + return -EINVAL; + } + assert(cur->file_pos < cur->size); + return 0; +} + +static int block_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read) +{ + block_dev_state_t *cur; + io_block_spec_t *buf; + io_block_ops_t *ops; + size_t aligned_length, skip, count, left, padding, block_size; + int lba; + int buffer_not_aligned; + + assert(entity->info != (uintptr_t)NULL); + cur = (block_dev_state_t *)entity->info; + ops = &(cur->dev_spec->ops); + buf = &(cur->dev_spec->buffer); + block_size = cur->dev_spec->block_size; + assert((length <= cur->size) && + (length > 0) && + (ops->read != 0)); + + if ((buffer & (block_size - 1)) != 0) { + /* + * buffer isn't aligned with block size. + * Block device always relies on DMA operation. + * It's better to make the buffer as block size aligned. + */ + buffer_not_aligned = 1; + } else { + buffer_not_aligned = 0; + } + + skip = cur->file_pos % block_size; + aligned_length = ((skip + length) + (block_size - 1)) & + ~(block_size - 1); + padding = aligned_length - (skip + length); + left = aligned_length; + do { + lba = (cur->file_pos + cur->base) / block_size; + if (left >= buf->length) { + /* + * Since left is larger, it's impossible to padding. + * + * If buffer isn't aligned, we need to use aligned + * buffer instead. + */ + if (skip || buffer_not_aligned) { + /* + * The beginning address (file_pos) isn't + * aligned with block size, we need to use + * block buffer to read block. Since block + * device is always relied on DMA operation. + */ + count = ops->read(lba, buf->offset, + buf->length); + } else { + count = ops->read(lba, buffer, buf->length); + } + assert(count == buf->length); + cur->file_pos += count - skip; + if (skip || buffer_not_aligned) { + /* + * Since there's not aligned block size caused + * by skip or not aligned buffer, block buffer + * is used to store data. + */ + memcpy((void *)buffer, + (void *)(buf->offset + skip), + count - skip); + } + left = left - (count - skip); + } else { + if (skip || padding || buffer_not_aligned) { + /* + * The beginning address (file_pos) isn't + * aligned with block size, we have to read + * full block by block buffer instead. + * The size isn't aligned with block size. + * Use block buffer to avoid overflow. + * + * If buffer isn't aligned, use block buffer + * to avoid DMA error. + */ + count = ops->read(lba, buf->offset, left); + } else + count = ops->read(lba, buffer, left); + assert(count == left); + left = left - (skip + padding); + cur->file_pos += left; + if (skip || padding || buffer_not_aligned) { + /* + * Since there's not aligned block size or + * buffer, block buffer is used to store data. + */ + memcpy((void *)buffer, + (void *)(buf->offset + skip), + left); + } + /* It's already the last block operation */ + left = 0; + } + skip = cur->file_pos % block_size; + } while (left > 0); + *length_read = length; + + return 0; +} + +static int block_write(io_entity_t *entity, const uintptr_t buffer, + size_t length, size_t *length_written) +{ + block_dev_state_t *cur; + io_block_spec_t *buf; + io_block_ops_t *ops; + size_t aligned_length, skip, count, left, padding, block_size; + int lba; + int buffer_not_aligned; + + assert(entity->info != (uintptr_t)NULL); + cur = (block_dev_state_t *)entity->info; + ops = &(cur->dev_spec->ops); + buf = &(cur->dev_spec->buffer); + block_size = cur->dev_spec->block_size; + assert((length <= cur->size) && + (length > 0) && + (ops->read != 0) && + (ops->write != 0)); + + if ((buffer & (block_size - 1)) != 0) { + /* + * buffer isn't aligned with block size. + * Block device always relies on DMA operation. + * It's better to make the buffer as block size aligned. + */ + buffer_not_aligned = 1; + } else { + buffer_not_aligned = 0; + } + + skip = cur->file_pos % block_size; + aligned_length = ((skip + length) + (block_size - 1)) & + ~(block_size - 1); + padding = aligned_length - (skip + length); + left = aligned_length; + do { + lba = (cur->file_pos + cur->base) / block_size; + if (left >= buf->length) { + /* Since left is larger, it's impossible to padding. */ + if (skip || buffer_not_aligned) { + /* + * The beginning address (file_pos) isn't + * aligned with block size or buffer isn't + * aligned, we need to use block buffer to + * write block. + */ + count = ops->read(lba, buf->offset, + buf->length); + assert(count == buf->length); + memcpy((void *)(buf->offset + skip), + (void *)buffer, + count - skip); + count = ops->write(lba, buf->offset, + buf->length); + } else + count = ops->write(lba, buffer, buf->length); + assert(count == buf->length); + cur->file_pos += count - skip; + left = left - (count - skip); + } else { + if (skip || padding || buffer_not_aligned) { + /* + * The beginning address (file_pos) isn't + * aligned with block size, we need to avoid + * poluate data in the beginning. Reading and + * skipping the beginning is the only way. + * The size isn't aligned with block size. + * Use block buffer to avoid overflow. + * + * If buffer isn't aligned, use block buffer + * to avoid DMA error. + */ + count = ops->read(lba, buf->offset, left); + assert(count == left); + memcpy((void *)(buf->offset + skip), + (void *)buffer, + left - skip - padding); + count = ops->write(lba, buf->offset, left); + } else + count = ops->write(lba, buffer, left); + assert(count == left); + cur->file_pos += left - (skip + padding); + /* It's already the last block operation */ + left = 0; + } + skip = cur->file_pos % block_size; + } while (left > 0); + *length_written = length; + return 0; +} + +static int block_close(io_entity_t *entity) +{ + entity->info = (uintptr_t)NULL; + return 0; +} + +static int block_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info) +{ + block_dev_state_t *cur; + io_block_spec_t *buffer; + io_dev_info_t *info; + size_t block_size; + int result; + + assert(dev_info != NULL); + result = allocate_dev_info(&info); + if (result) + return -ENOENT; + + cur = (block_dev_state_t *)info->info; + /* dev_spec is type of io_block_dev_spec_t. */ + cur->dev_spec = (io_block_dev_spec_t *)dev_spec; + buffer = &(cur->dev_spec->buffer); + block_size = cur->dev_spec->block_size; + assert((block_size > 0) && + (is_power_of_2(block_size) != 0) && + ((buffer->offset % block_size) == 0) && + ((buffer->length % block_size) == 0)); + + *dev_info = info; /* cast away const */ + (void)block_size; + (void)buffer; + return 0; +} + +static int block_dev_close(io_dev_info_t *dev_info) +{ + return free_dev_info(dev_info); +} + +/* Exported functions */ + +/* Register the Block driver with the IO abstraction */ +int register_io_dev_block(const io_dev_connector_t **dev_con) +{ + int result; + + assert(dev_con != NULL); + + /* + * Since dev_info isn't really used in io_register_device, always + * use the same device info at here instead. + */ + result = io_register_device(&dev_info_pool[0]); + if (result == 0) + *dev_con = &block_dev_connector; + return result; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_dummy.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_dummy.c new file mode 100644 index 0000000..e2458de --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_dummy.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +struct file_state { + int in_use; + size_t size; +}; + +static struct file_state current_file = {0}; + +/* Identify the device type as dummy */ +io_type_t device_type_dummy(void) +{ + return IO_TYPE_DUMMY; +} + +/* Dummy device functions */ +static int dummy_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); +static int dummy_block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); +static int dummy_block_len(io_entity_t *entity, size_t *length); +static int dummy_block_read(io_entity_t *entity, uintptr_t buffer, + size_t length, size_t *length_read); +static int dummy_block_close(io_entity_t *entity); +static int dummy_dev_close(io_dev_info_t *dev_info); + + +static const io_dev_connector_t dummy_dev_connector = { + .dev_open = dummy_dev_open +}; + + +static const io_dev_funcs_t dummy_dev_funcs = { + .type = device_type_dummy, + .open = dummy_block_open, + .seek = NULL, + .size = dummy_block_len, + .read = dummy_block_read, + .write = NULL, + .close = dummy_block_close, + .dev_init = NULL, + .dev_close = dummy_dev_close, +}; + + +static const io_dev_info_t dummy_dev_info = { + .funcs = &dummy_dev_funcs, + .info = (uintptr_t)NULL +}; + + +/* Open a connection to the dummy device */ +static int dummy_dev_open(const uintptr_t dev_spec __attribute__((unused)), + io_dev_info_t **dev_info) +{ + assert(dev_info != NULL); + *dev_info = (io_dev_info_t *)&dummy_dev_info; + + return 0; +} + + +/* Close a connection to the dummy device */ +static int dummy_dev_close(io_dev_info_t *dev_info) +{ + return 0; +} + + +/* Open a file on the dummy device */ +static int dummy_block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity) +{ + int result; + const io_block_spec_t *block_spec = (io_block_spec_t *)spec; + + if (current_file.in_use == 0) { + assert(block_spec != NULL); + assert(entity != NULL); + + current_file.in_use = 1; + current_file.size = block_spec->length; + entity->info = (uintptr_t)¤t_file; + result = 0; + } else { + WARN("A Dummy device is already active. Close first.\n"); + result = -ENOMEM; + } + + return result; +} + + +/* Return the size of a file on the dummy device */ +static int dummy_block_len(io_entity_t *entity, size_t *length) +{ + assert(entity != NULL); + assert(length != NULL); + + *length = ((struct file_state *)entity->info)->size; + + return 0; +} + + +/* Read data from a file on the dummy device */ +static int dummy_block_read(io_entity_t *entity, uintptr_t buffer, + size_t length, size_t *length_read) +{ + assert(length_read != NULL); + + *length_read = length; + + return 0; +} + + +/* Close a file on the dummy device */ +static int dummy_block_close(io_entity_t *entity) +{ + assert(entity != NULL); + + entity->info = 0; + current_file.in_use = 0; + + return 0; +} + + +/* Exported functions */ + +/* Register the dummy driver with the IO abstraction */ +int register_io_dev_dummy(const io_dev_connector_t **dev_con) +{ + int result; + + assert(dev_con != NULL); + + result = io_register_device(&dummy_dev_info); + if (result == 0) + *dev_con = &dummy_dev_connector; + + return result; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_fip.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_fip.c new file mode 100644 index 0000000..99cf15b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_fip.c @@ -0,0 +1,376 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Useful for printing UUIDs when debugging.*/ +#define PRINT_UUID2(x) \ + "%08x-%04hx-%04hx-%02hhx%02hhx-%02hhx%02hhx%02hhx%02hhx%02hhx%02hhx", \ + x.time_low, x.time_mid, x.time_hi_and_version, \ + x.clock_seq_hi_and_reserved, x.clock_seq_low, \ + x.node[0], x.node[1], x.node[2], x.node[3], \ + x.node[4], x.node[5] + +typedef struct { + /* Put file_pos above the struct to allow {0} on static init. + * It is a workaround for a known bug in GCC + * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119 + */ + unsigned int file_pos; + fip_toc_entry_t entry; +} file_state_t; + +static const uuid_t uuid_null = {0}; +static file_state_t current_file = {0}; +static uintptr_t backend_dev_handle; +static uintptr_t backend_image_spec; + + +/* Firmware Image Package driver functions */ +static int fip_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); +static int fip_file_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); +static int fip_file_len(io_entity_t *entity, size_t *length); +static int fip_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read); +static int fip_file_close(io_entity_t *entity); +static int fip_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params); +static int fip_dev_close(io_dev_info_t *dev_info); + + +/* Return 0 for equal uuids. */ +static inline int compare_uuids(const uuid_t *uuid1, const uuid_t *uuid2) +{ + return memcmp(uuid1, uuid2, sizeof(uuid_t)); +} + + +/* TODO: We could check version numbers or do a package checksum? */ +static inline int is_valid_header(fip_toc_header_t *header) +{ + if ((header->name == TOC_HEADER_NAME) && (header->serial_number != 0)) { + return 1; + } else { + return 0; + } +} + + +/* Identify the device type as a virtual driver */ +io_type_t device_type_fip(void) +{ + return IO_TYPE_FIRMWARE_IMAGE_PACKAGE; +} + + +static const io_dev_connector_t fip_dev_connector = { + .dev_open = fip_dev_open +}; + + +static const io_dev_funcs_t fip_dev_funcs = { + .type = device_type_fip, + .open = fip_file_open, + .seek = NULL, + .size = fip_file_len, + .read = fip_file_read, + .write = NULL, + .close = fip_file_close, + .dev_init = fip_dev_init, + .dev_close = fip_dev_close, +}; + + +/* No state associated with this device so structure can be const */ +static const io_dev_info_t fip_dev_info = { + .funcs = &fip_dev_funcs, + .info = (uintptr_t)NULL +}; + + +/* Open a connection to the FIP device */ +static int fip_dev_open(const uintptr_t dev_spec __unused, + io_dev_info_t **dev_info) +{ + assert(dev_info != NULL); + *dev_info = (io_dev_info_t *)&fip_dev_info; /* cast away const */ + + return 0; +} + + +/* Do some basic package checks. */ +static int fip_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params) +{ + int result; + unsigned int image_id = (unsigned int)init_params; + uintptr_t backend_handle; + fip_toc_header_t header; + size_t bytes_read; + + /* Obtain a reference to the image by querying the platform layer */ + result = plat_get_image_source(image_id, &backend_dev_handle, + &backend_image_spec); + if (result != 0) { + WARN("Failed to obtain reference to image id=%u (%i)\n", + image_id, result); + result = -ENOENT; + goto fip_dev_init_exit; + } + + /* Attempt to access the FIP image */ + result = io_open(backend_dev_handle, backend_image_spec, + &backend_handle); + if (result != 0) { + WARN("Failed to access image id=%u (%i)\n", image_id, result); + result = -ENOENT; + goto fip_dev_init_exit; + } + + result = io_read(backend_handle, (uintptr_t)&header, sizeof(header), + &bytes_read); + if (result == 0) { + if (!is_valid_header(&header)) { + WARN("Firmware Image Package header check failed.\n"); + result = -ENOENT; + } else { + VERBOSE("FIP header looks OK.\n"); + } + } + + io_close(backend_handle); + + fip_dev_init_exit: + return result; +} + +/* Close a connection to the FIP device */ +static int fip_dev_close(io_dev_info_t *dev_info) +{ + /* TODO: Consider tracking open files and cleaning them up here */ + + /* Clear the backend. */ + backend_dev_handle = (uintptr_t)NULL; + backend_image_spec = (uintptr_t)NULL; + + return 0; +} + + +/* Open a file for access from package. */ +static int fip_file_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity) +{ + int result; + uintptr_t backend_handle; + const io_uuid_spec_t *uuid_spec = (io_uuid_spec_t *)spec; + size_t bytes_read; + int found_file = 0; + + assert(uuid_spec != NULL); + assert(entity != NULL); + + /* Can only have one file open at a time for the moment. We need to + * track state like file cursor position. We know the header lives at + * offset zero, so this entry should never be zero for an active file. + * When the system supports dynamic memory allocation we can allow more + * than one open file at a time if needed. + */ + if (current_file.entry.offset_address != 0) { + WARN("fip_file_open : Only one open file at a time.\n"); + return -ENOMEM; + } + + /* Attempt to access the FIP image */ + result = io_open(backend_dev_handle, backend_image_spec, + &backend_handle); + if (result != 0) { + WARN("Failed to open Firmware Image Package (%i)\n", result); + result = -ENOENT; + goto fip_file_open_exit; + } + + /* Seek past the FIP header into the Table of Contents */ + result = io_seek(backend_handle, IO_SEEK_SET, sizeof(fip_toc_header_t)); + if (result != 0) { + WARN("fip_file_open: failed to seek\n"); + result = -ENOENT; + goto fip_file_open_close; + } + + found_file = 0; + do { + result = io_read(backend_handle, + (uintptr_t)¤t_file.entry, + sizeof(current_file.entry), + &bytes_read); + if (result == 0) { + if (compare_uuids(¤t_file.entry.uuid, + &uuid_spec->uuid) == 0) { + found_file = 1; + break; + } + } else { + WARN("Failed to read FIP (%i)\n", result); + goto fip_file_open_close; + } + } while (compare_uuids(¤t_file.entry.uuid, &uuid_null) != 0); + + if (found_file == 1) { + /* All fine. Update entity info with file state and return. Set + * the file position to 0. The 'current_file.entry' holds the + * base and size of the file. + */ + current_file.file_pos = 0; + entity->info = (uintptr_t)¤t_file; + } else { + /* Did not find the file in the FIP. */ + current_file.entry.offset_address = 0; + result = -ENOENT; + } + + fip_file_open_close: + io_close(backend_handle); + + fip_file_open_exit: + return result; +} + + +/* Return the size of a file in package */ +static int fip_file_len(io_entity_t *entity, size_t *length) +{ + assert(entity != NULL); + assert(length != NULL); + + *length = ((file_state_t *)entity->info)->entry.size; + + return 0; +} + + +/* Read data from a file in package */ +static int fip_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read) +{ + int result; + file_state_t *fp; + size_t file_offset; + size_t bytes_read; + uintptr_t backend_handle; + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_read != NULL); + assert(entity->info != (uintptr_t)NULL); + + /* Open the backend, attempt to access the blob image */ + result = io_open(backend_dev_handle, backend_image_spec, + &backend_handle); + if (result != 0) { + WARN("Failed to open FIP (%i)\n", result); + result = -ENOENT; + goto fip_file_read_exit; + } + + fp = (file_state_t *)entity->info; + + /* Seek to the position in the FIP where the payload lives */ + file_offset = fp->entry.offset_address + fp->file_pos; + result = io_seek(backend_handle, IO_SEEK_SET, file_offset); + if (result != 0) { + WARN("fip_file_read: failed to seek\n"); + result = -ENOENT; + goto fip_file_read_close; + } + + result = io_read(backend_handle, buffer, length, &bytes_read); + if (result != 0) { + /* We cannot read our data. Fail. */ + WARN("Failed to read payload (%i)\n", result); + result = -ENOENT; + goto fip_file_read_close; + } else { + /* Set caller length and new file position. */ + *length_read = bytes_read; + fp->file_pos += bytes_read; + } + +/* Close the backend. */ + fip_file_read_close: + io_close(backend_handle); + + fip_file_read_exit: + return result; +} + + +/* Close a file in package */ +static int fip_file_close(io_entity_t *entity) +{ + /* Clear our current file pointer. + * If we had malloc() we would free() here. + */ + if (current_file.entry.offset_address != 0) { + memset(¤t_file, 0, sizeof(current_file)); + } + + /* Clear the Entity info. */ + entity->info = 0; + + return 0; +} + +/* Exported functions */ + +/* Register the Firmware Image Package driver with the IO abstraction */ +int register_io_dev_fip(const io_dev_connector_t **dev_con) +{ + int result; + assert(dev_con != NULL); + + result = io_register_device(&fip_dev_info); + if (result == 0) + *dev_con = &fip_dev_connector; + + return result; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_memmap.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_memmap.c new file mode 100644 index 0000000..fe39652 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_memmap.c @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/* As we need to be able to keep state for seek, only one file can be open + * at a time. Make this a structure and point to the entity->info. When we + * can malloc memory we can change this to support more open files. + */ +typedef struct { + /* Use the 'in_use' flag as any value for base and file_pos could be + * valid. + */ + int in_use; + uintptr_t base; + size_t file_pos; + size_t size; +} file_state_t; + +static file_state_t current_file = {0}; + +/* Identify the device type as memmap */ +io_type_t device_type_memmap(void) +{ + return IO_TYPE_MEMMAP; +} + +/* Memmap device functions */ +static int memmap_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); +static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); +static int memmap_block_seek(io_entity_t *entity, int mode, + ssize_t offset); +static int memmap_block_len(io_entity_t *entity, size_t *length); +static int memmap_block_read(io_entity_t *entity, uintptr_t buffer, + size_t length, size_t *length_read); +static int memmap_block_write(io_entity_t *entity, const uintptr_t buffer, + size_t length, size_t *length_written); +static int memmap_block_close(io_entity_t *entity); +static int memmap_dev_close(io_dev_info_t *dev_info); + + +static const io_dev_connector_t memmap_dev_connector = { + .dev_open = memmap_dev_open +}; + + +static const io_dev_funcs_t memmap_dev_funcs = { + .type = device_type_memmap, + .open = memmap_block_open, + .seek = memmap_block_seek, + .size = memmap_block_len, + .read = memmap_block_read, + .write = memmap_block_write, + .close = memmap_block_close, + .dev_init = NULL, + .dev_close = memmap_dev_close, +}; + + +/* No state associated with this device so structure can be const */ +static const io_dev_info_t memmap_dev_info = { + .funcs = &memmap_dev_funcs, + .info = (uintptr_t)NULL +}; + + +/* Open a connection to the memmap device */ +static int memmap_dev_open(const uintptr_t dev_spec __unused, + io_dev_info_t **dev_info) +{ + assert(dev_info != NULL); + *dev_info = (io_dev_info_t *)&memmap_dev_info; /* cast away const */ + + return 0; +} + + + +/* Close a connection to the memmap device */ +static int memmap_dev_close(io_dev_info_t *dev_info) +{ + /* NOP */ + /* TODO: Consider tracking open files and cleaning them up here */ + return 0; +} + + +/* Open a file on the memmap device */ +/* TODO: Can we do any sensible limit checks on requested memory */ +static int memmap_block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity) +{ + int result = -ENOMEM; + const io_block_spec_t *block_spec = (io_block_spec_t *)spec; + + /* Since we need to track open state for seek() we only allow one open + * spec at a time. When we have dynamic memory we can malloc and set + * entity->info. + */ + if (current_file.in_use == 0) { + assert(block_spec != NULL); + assert(entity != NULL); + + current_file.in_use = 1; + current_file.base = block_spec->offset; + /* File cursor offset for seek and incremental reads etc. */ + current_file.file_pos = 0; + current_file.size = block_spec->length; + entity->info = (uintptr_t)¤t_file; + result = 0; + } else { + WARN("A Memmap device is already active. Close first.\n"); + } + + return result; +} + + +/* Seek to a particular file offset on the memmap device */ +static int memmap_block_seek(io_entity_t *entity, int mode, ssize_t offset) +{ + int result = -ENOENT; + + /* We only support IO_SEEK_SET for the moment. */ + if (mode == IO_SEEK_SET) { + assert(entity != NULL); + + /* TODO: can we do some basic limit checks on seek? */ + ((file_state_t *)entity->info)->file_pos = offset; + result = 0; + } + + return result; +} + + +/* Return the size of a file on the memmap device */ +static int memmap_block_len(io_entity_t *entity, size_t *length) +{ + assert(entity != NULL); + assert(length != NULL); + + *length = ((file_state_t *)entity->info)->size; + + return 0; +} + + +/* Read data from a file on the memmap device */ +static int memmap_block_read(io_entity_t *entity, uintptr_t buffer, + size_t length, size_t *length_read) +{ + file_state_t *fp; + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_read != NULL); + + fp = (file_state_t *)entity->info; + + memcpy((void *)buffer, (void *)(fp->base + fp->file_pos), length); + + *length_read = length; + /* advance the file 'cursor' for incremental reads */ + fp->file_pos += length; + + return 0; +} + + +/* Write data to a file on the memmap device */ +static int memmap_block_write(io_entity_t *entity, const uintptr_t buffer, + size_t length, size_t *length_written) +{ + file_state_t *fp; + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_written != NULL); + + fp = (file_state_t *)entity->info; + + memcpy((void *)(fp->base + fp->file_pos), (void *)buffer, length); + + *length_written = length; + + /* advance the file 'cursor' for incremental writes */ + fp->file_pos += length; + + return 0; +} + + +/* Close a file on the memmap device */ +static int memmap_block_close(io_entity_t *entity) +{ + assert(entity != NULL); + + entity->info = 0; + + /* This would be a mem free() if we had malloc.*/ + memset((void *)¤t_file, 0, sizeof(current_file)); + + return 0; +} + + +/* Exported functions */ + +/* Register the memmap driver with the IO abstraction */ +int register_io_dev_memmap(const io_dev_connector_t **dev_con) +{ + int result; + assert(dev_con != NULL); + + result = io_register_device(&memmap_dev_info); + if (result == 0) + *dev_con = &memmap_dev_connector; + + return result; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_semihosting.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_semihosting.c new file mode 100644 index 0000000..30ca99c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_semihosting.c @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + + +/* Identify the device type as semihosting */ +static io_type_t device_type_sh(void) +{ + return IO_TYPE_SEMIHOSTING; +} + + +/* Semi-hosting functions, device info and handle */ + +static int sh_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); +static int sh_file_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); +static int sh_file_seek(io_entity_t *entity, int mode, ssize_t offset); +static int sh_file_len(io_entity_t *entity, size_t *length); +static int sh_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read); +static int sh_file_write(io_entity_t *entity, const uintptr_t buffer, + size_t length, size_t *length_written); +static int sh_file_close(io_entity_t *entity); + +static const io_dev_connector_t sh_dev_connector = { + .dev_open = sh_dev_open +}; + + +static const io_dev_funcs_t sh_dev_funcs = { + .type = device_type_sh, + .open = sh_file_open, + .seek = sh_file_seek, + .size = sh_file_len, + .read = sh_file_read, + .write = sh_file_write, + .close = sh_file_close, + .dev_init = NULL, /* NOP */ + .dev_close = NULL, /* NOP */ +}; + + +/* No state associated with this device so structure can be const */ +static const io_dev_info_t sh_dev_info = { + .funcs = &sh_dev_funcs, + .info = (uintptr_t)NULL +}; + + +/* Open a connection to the semi-hosting device */ +static int sh_dev_open(const uintptr_t dev_spec __unused, + io_dev_info_t **dev_info) +{ + assert(dev_info != NULL); + *dev_info = (io_dev_info_t *)&sh_dev_info; /* cast away const */ + return 0; +} + + +/* Open a file on the semi-hosting device */ +static int sh_file_open(io_dev_info_t *dev_info __unused, + const uintptr_t spec, io_entity_t *entity) +{ + int result = -ENOENT; + long sh_result = -1; + const io_file_spec_t *file_spec = (const io_file_spec_t *)spec; + + assert(file_spec != NULL); + assert(entity != NULL); + + sh_result = semihosting_file_open(file_spec->path, file_spec->mode); + + if (sh_result > 0) { + entity->info = (uintptr_t)sh_result; + result = 0; + } + return result; +} + + +/* Seek to a particular file offset on the semi-hosting device */ +static int sh_file_seek(io_entity_t *entity, int mode, ssize_t offset) +{ + long file_handle, sh_result; + + assert(entity != NULL); + + file_handle = (long)entity->info; + + sh_result = semihosting_file_seek(file_handle, offset); + + return (sh_result == 0) ? 0 : -ENOENT; +} + + +/* Return the size of a file on the semi-hosting device */ +static int sh_file_len(io_entity_t *entity, size_t *length) +{ + int result = -ENOENT; + + assert(entity != NULL); + assert(length != NULL); + + long sh_handle = (long)entity->info; + long sh_result = semihosting_file_length(sh_handle); + + if (sh_result >= 0) { + result = 0; + *length = (size_t)sh_result; + } + + return result; +} + + +/* Read data from a file on the semi-hosting device */ +static int sh_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read) +{ + int result = -ENOENT; + long sh_result = -1; + size_t bytes = length; + long file_handle; + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_read != NULL); + + file_handle = (long)entity->info; + + sh_result = semihosting_file_read(file_handle, &bytes, buffer); + + if (sh_result >= 0) { + *length_read = (bytes != length) ? bytes : length; + result = 0; + } + + return result; +} + + +/* Write data to a file on the semi-hosting device */ +static int sh_file_write(io_entity_t *entity, const uintptr_t buffer, + size_t length, size_t *length_written) +{ + long sh_result = -1; + long file_handle; + size_t bytes = length; + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_written != NULL); + + file_handle = (long)entity->info; + + sh_result = semihosting_file_write(file_handle, &bytes, buffer); + + *length_written = length - bytes; + + return (sh_result == 0) ? 0 : -ENOENT; +} + + +/* Close a file on the semi-hosting device */ +static int sh_file_close(io_entity_t *entity) +{ + long sh_result = -1; + long file_handle; + + assert(entity != NULL); + + file_handle = (long)entity->info; + + sh_result = semihosting_file_close(file_handle); + + return (sh_result >= 0) ? 0 : -ENOENT; +} + + +/* Exported functions */ + +/* Register the semi-hosting driver with the IO abstraction */ +int register_io_dev_sh(const io_dev_connector_t **dev_con) +{ + int result; + assert(dev_con != NULL); + + result = io_register_device(&sh_dev_info); + if (result == 0) + *dev_con = &sh_dev_connector; + + return result; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_storage.c b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_storage.c new file mode 100644 index 0000000..7cb1a6a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/io/io_storage.c @@ -0,0 +1,358 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + + +/* Storage for a fixed maximum number of IO entities, definable by platform */ +static io_entity_t entity_pool[MAX_IO_HANDLES]; + +/* Simple way of tracking used storage - each entry is NULL or a pointer to an + * entity */ +static io_entity_t *entity_map[MAX_IO_HANDLES]; + +/* Track number of allocated entities */ +static unsigned int entity_count; + +/* Array of fixed maximum of registered devices, definable by platform */ +static const io_dev_info_t *devices[MAX_IO_DEVICES]; + +/* Number of currently registered devices */ +static unsigned int dev_count; + + +#if DEBUG /* Extra validation functions only used in debug builds */ + +/* Return a boolean value indicating whether a device connector is valid */ +static int is_valid_dev_connector(const io_dev_connector_t *dev_con) +{ + int result = (dev_con != NULL) && (dev_con->dev_open != NULL); + return result; +} + + +/* Return a boolean value indicating whether a device handle is valid */ +static int is_valid_dev(const uintptr_t dev_handle) +{ + const io_dev_info_t *dev = (io_dev_info_t *)dev_handle; + int result = (dev != NULL) && (dev->funcs != NULL) && + (dev->funcs->type != NULL) && + (dev->funcs->type() < IO_TYPE_MAX); + return result; +} + + +/* Return a boolean value indicating whether an IO entity is valid */ +static int is_valid_entity(const uintptr_t handle) +{ + const io_entity_t *entity = (io_entity_t *)handle; + int result = (entity != NULL) && + (is_valid_dev((uintptr_t)entity->dev_handle)); + return result; +} + + +/* Return a boolean value indicating whether a seek mode is valid */ +static int is_valid_seek_mode(io_seek_mode_t mode) +{ + return ((mode != IO_SEEK_INVALID) && (mode < IO_SEEK_MAX)); +} + +#endif /* End of debug-only validation functions */ + + +/* Open a connection to a specific device */ +static int dev_open(const io_dev_connector_t *dev_con, const uintptr_t dev_spec, + io_dev_info_t **dev_info) +{ + int result; + assert(dev_info != NULL); + assert(is_valid_dev_connector(dev_con)); + + result = dev_con->dev_open(dev_spec, dev_info); + return result; +} + + +/* Set a handle to track an entity */ +static void set_handle(uintptr_t *handle, io_entity_t *entity) +{ + assert(handle != NULL); + *handle = (uintptr_t)entity; +} + + +/* Locate an entity in the pool, specified by address */ +static int find_first_entity(const io_entity_t *entity, unsigned int *index_out) +{ + int result = -ENOENT; + for (int index = 0; index < MAX_IO_HANDLES; ++index) { + if (entity_map[index] == entity) { + result = 0; + *index_out = index; + break; + } + } + return result; +} + + +/* Allocate an entity from the pool and return a pointer to it */ +static int allocate_entity(io_entity_t **entity) +{ + int result = -ENOMEM; + assert(entity != NULL); + + if (entity_count < MAX_IO_HANDLES) { + unsigned int index = 0; + result = find_first_entity(NULL, &index); + assert(result == 0); + *entity = entity_map[index] = &entity_pool[index]; + ++entity_count; + } + + return result; +} + + +/* Release an entity back to the pool */ +static int free_entity(const io_entity_t *entity) +{ + int result; + unsigned int index = 0; + assert(entity != NULL); + + result = find_first_entity(entity, &index); + if (result == 0) { + entity_map[index] = NULL; + --entity_count; + } + + return result; +} + + +/* Exported API */ + +/* Register a device driver */ +int io_register_device(const io_dev_info_t *dev_info) +{ + int result = -ENOMEM; + assert(dev_info != NULL); + + if (dev_count < MAX_IO_DEVICES) { + devices[dev_count] = dev_info; + dev_count++; + result = 0; + } + + return result; +} + + +/* Open a connection to an IO device */ +int io_dev_open(const io_dev_connector_t *dev_con, const uintptr_t dev_spec, + uintptr_t *handle) +{ + int result; + assert(handle != NULL); + + result = dev_open(dev_con, dev_spec, (io_dev_info_t **)handle); + return result; +} + + +/* Initialise an IO device explicitly - to permit lazy initialisation or + * re-initialisation */ +int io_dev_init(uintptr_t dev_handle, const uintptr_t init_params) +{ + int result = 0; + assert(dev_handle != (uintptr_t)NULL); + assert(is_valid_dev(dev_handle)); + + io_dev_info_t *dev = (io_dev_info_t *)dev_handle; + + /* Absence of registered function implies NOP here */ + if (dev->funcs->dev_init != NULL) { + result = dev->funcs->dev_init(dev, init_params); + } + + return result; +} + + +/* TODO: Consider whether an explicit "shutdown" API should be included */ + +/* Close a connection to a device */ +int io_dev_close(uintptr_t dev_handle) +{ + int result = 0; + assert(dev_handle != (uintptr_t)NULL); + assert(is_valid_dev(dev_handle)); + + io_dev_info_t *dev = (io_dev_info_t *)dev_handle; + + /* Absence of registered function implies NOP here */ + if (dev->funcs->dev_close != NULL) { + result = dev->funcs->dev_close(dev); + } + + return result; +} + + +/* Synchronous operations */ + + +/* Open an IO entity */ +int io_open(uintptr_t dev_handle, const uintptr_t spec, uintptr_t *handle) +{ + int result; + assert((spec != (uintptr_t)NULL) && (handle != NULL)); + assert(is_valid_dev(dev_handle)); + + io_dev_info_t *dev = (io_dev_info_t *)dev_handle; + io_entity_t *entity; + + result = allocate_entity(&entity); + + if (result == 0) { + assert(dev->funcs->open != NULL); + result = dev->funcs->open(dev, spec, entity); + + if (result == 0) { + entity->dev_handle = dev; + set_handle(handle, entity); + } else + free_entity(entity); + } + return result; +} + + +/* Seek to a specific position in an IO entity */ +int io_seek(uintptr_t handle, io_seek_mode_t mode, ssize_t offset) +{ + int result = -ENODEV; + assert(is_valid_entity(handle) && is_valid_seek_mode(mode)); + + io_entity_t *entity = (io_entity_t *)handle; + + io_dev_info_t *dev = entity->dev_handle; + + if (dev->funcs->seek != NULL) + result = dev->funcs->seek(entity, mode, offset); + + return result; +} + + +/* Determine the length of an IO entity */ +int io_size(uintptr_t handle, size_t *length) +{ + int result = -ENODEV; + assert(is_valid_entity(handle) && (length != NULL)); + + io_entity_t *entity = (io_entity_t *)handle; + + io_dev_info_t *dev = entity->dev_handle; + + if (dev->funcs->size != NULL) + result = dev->funcs->size(entity, length); + + return result; +} + + +/* Read data from an IO entity */ +int io_read(uintptr_t handle, + uintptr_t buffer, + size_t length, + size_t *length_read) +{ + int result = -ENODEV; + assert(is_valid_entity(handle) && (buffer != (uintptr_t)NULL)); + + io_entity_t *entity = (io_entity_t *)handle; + + io_dev_info_t *dev = entity->dev_handle; + + if (dev->funcs->read != NULL) + result = dev->funcs->read(entity, buffer, length, length_read); + + return result; +} + + +/* Write data to an IO entity */ +int io_write(uintptr_t handle, + const uintptr_t buffer, + size_t length, + size_t *length_written) +{ + int result = -ENODEV; + assert(is_valid_entity(handle) && (buffer != (uintptr_t)NULL)); + + io_entity_t *entity = (io_entity_t *)handle; + + io_dev_info_t *dev = entity->dev_handle; + + if (dev->funcs->write != NULL) { + result = dev->funcs->write(entity, buffer, length, + length_written); + } + + return result; +} + + +/* Close an IO entity */ +int io_close(uintptr_t handle) +{ + int result = 0; + assert(is_valid_entity(handle)); + + io_entity_t *entity = (io_entity_t *)handle; + + io_dev_info_t *dev = entity->dev_handle; + + /* Absence of registered function implies NOP here */ + if (dev->funcs->close != NULL) + result = dev->funcs->close(entity); + + /* Ignore improbable free_entity failure */ + (void)free_entity(entity); + + return result; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/ti/uart/16550_console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/ti/uart/16550_console.S new file mode 100644 index 0000000..90b12e5 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/ti/uart/16550_console.S @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#if !ERROR_DEPRECATED +#include "./aarch64/16550_console.S" +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/ti/uart/aarch64/16550_console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/ti/uart/aarch64/16550_console.S new file mode 100644 index 0000000..0535381 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/drivers/ti/uart/aarch64/16550_console.S @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .globl console_core_init + .globl console_core_putc + .globl console_core_getc + + /* ----------------------------------------------- + * int console_core_init(unsigned long base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * Out: return 1 on success + * Clobber list : x1, x2, x3 + * ----------------------------------------------- + */ +func console_core_init + /* Check the input base address */ + cbz x0, init_fail + /* Check baud rate and uart clock for sanity */ + cbz w1, init_fail + cbz w2, init_fail + + /* Program the baudrate */ + /* Divisor = Uart clock / (16 * baudrate) */ + lsl w2, w2, #4 + udiv w2, w1, w2 + and w1, w2, #0xff /* w1 = DLL */ + lsr w2, w2, #8 + and w2, w2, #0xff /* w2 = DLLM */ + ldr w3, [x0, #UARTLCR] + orr w3, w3, #UARTLCR_DLAB + str w3, [x0, #UARTLCR] /* enable DLL, DLLM programming */ + str w1, [x0, #UARTDLL] /* program DLL */ + str w2, [x0, #UARTDLLM] /* program DLLM */ + mov w2, #~UARTLCR_DLAB + and w3, w3, w2 + str w3, [x0, #UARTLCR] /* disable DLL, DLLM programming */ + + /* 8n1 */ + mov w3, #3 + str w3, [x0, #UARTLCR] + /* no interrupt */ + mov w3, #0 + str w3, [x0, #UARTIER] + /* enable fifo, DMA */ + mov w3, #(UARTFCR_FIFOEN | UARTFCR_DMAEN) + str w3, [x0, #UARTFCR] + /* DTR + RTS */ + mov w3, #3 + str w3, [x0, #UARTMCR] + mov w0, #1 +init_fail: + ret +endfunc console_core_init + + /* -------------------------------------------------------- + * int console_core_putc(int c, unsigned int base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_core_putc + /* Check the input parameter */ + cbz x1, putc_error + + /* Prepend '\r' to '\n' */ + cmp w0, #0xA + b.ne 2f + /* Check if the transmit FIFO is full */ +1: ldr w2, [x1, #UARTLSR] + and w2, w2, #(UARTLSR_TEMT | UARTLSR_THRE) + cmp w2, #(UARTLSR_TEMT | UARTLSR_THRE) + b.ne 1b + mov w2, #0xD /* '\r' */ + str w2, [x1, #UARTTX] + ldr w2, [x1, #UARTFCR] + orr w2, w2, #UARTFCR_TXCLR + str w2, [x1, #UARTFCR] + + /* Check if the transmit FIFO is full */ +2: ldr w2, [x1, #UARTLSR] + and w2, w2, #(UARTLSR_TEMT | UARTLSR_THRE) + cmp w2, #(UARTLSR_TEMT | UARTLSR_THRE) + b.ne 2b + str w0, [x1, #UARTTX] + ldr w2, [x1, #UARTFCR] + orr w2, w2, #UARTFCR_TXCLR + str w2, [x1, #UARTFCR] + ret +putc_error: + mov w0, #-1 + ret +endfunc console_core_putc + + /* --------------------------------------------- + * int console_core_getc(void) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * In : w0 - console base address + * Out : return -1 on error else return character. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_getc + /* Check if the receive FIFO is empty */ +1: ldr w1, [x0, #UARTLSR] + tbz w1, #UARTLSR_RDR, 1b + ldr w0, [x0, #UARTRX] + ret +getc_error: + mov w0, #-1 + ret +endfunc console_core_getc diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-base-gicv2-psci-aarch32.dtb b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-base-gicv2-psci-aarch32.dtb new file mode 100644 index 0000000000000000000000000000000000000000..b044a769b07e2d04da2a0012b4e9f93843994313 GIT binary patch literal 10336 zcmb_iOOG5^6~5Jz3<(gN@P5a5GT=m0ad(d=nM4FS9^1i+?U=||2r24RS69zeT-9Bv zs&3C@V>|hxp7HoJdV9DeA&aGQ@+C3h5Jh@VJopZl? z&;9PX=RT^c|M1X%|7Og|SB)`WGv={B;eHa=Be)*Mg|zfN$<^0-Ai{}cd$_R8+Tndtn1Q0URH!LJAlOguiz4&GvDt#*%qIR(tfgAD=c37 z`jsLLwLW}vek?NRdMtLKvn^g6yPMD-Q2O_wGbV&zm`$spuFIbQrpKCN%jBV~p9Yzg zlW9>#xg8y1lRT;v*X|EdkZss@fLDezPPxXrwA}D!ee$pIb)xh5{m`2>ET@L={+yPp zI>LD$PVdwBKAh;wgE%?g*1Y0j68S|Ll+8R~nIChysrV587D*IkzIc+pIfhH(rLln= z>jU0@Udi;+Z>qJx`SEt-aZ$91*#m~*jqw*s+&5yDjWB6}A-Vepk z_4}y&7|WU;^_t)O8gM9nuHQ%Hhx&8;sMq{DcEfV~4-tPHUa@;req7&N`;5P4y~Fr+ z+7f{dKMcS3D*njHwNKg25w3sWClToI!|;2r;*aaQYoFYxtMQcxbogQTu@0}JjxYBP z*FO2V{l-hWei(#1dLQQ4FH0r_Bv+4Psn;#qq0W9vU(+a^9{?SWhNZmPT3jmJ1O`u+i@rdB$xG!`UWq$PVl0m7^^1AD96$P*y7;1u(Sh8fjvuN!P)u~O&jkLvcHw(a{EYu2my*>Qg2+sr~Di>7a` zjjB!YJ^Sf&E<8?$=)J|CQ68ibxvbA|fe$^NP1pkKJ0C-o=N9K<_^jge9YRQ!6Wb9V zXKB6v-{xN+vwAK&|I)&janU{#_jf0MMaf^SWN8DBGf;&m&j!myoMt%j4XTs1>;DO0 zEbnys!}V_$BK=V(E;?1iwnxx8Kvf>?Nctpxt32A3^jZ8?dDYEM?n>c)C5aAEbs>73 zKaLZ9{xe%re%WWVao;bH|0|VGvE~T5ZnMgF81EWm9~?$mW9*B=C~J(e!zgQveRCLP zjd3k>7-fyQd5LV+!7UFv=QZoH&fK#^CoFqpUH^{TidJ zF{}kOMpKN3b&=YA*adLKrnt4CR5A5j=(jWLW}Jr&Z(HRfXqqpa(F zTw#zI33*U{$Ono0_G z-%EmGr`N9Ec##Ye*E+_Jirg-tk$D~Tm-S;TYw?CLr%KByc~t)1QZp?A{^@_bBkG6a5=J+Z&_mcVewFOy;^|5y&ekIPh%~du{i+!ouZ*dMN zUE+a-E8Jr|P?!G0d{`zu8}rCSV!68SMTQf$eW#n_s2@g2;>uVqv?AuD9%8A*b)Wv_ zSi3mHe%4yGaboaLfDkl6Ht1&*m>jovAv<5TIj-^qfl|@9&5BVja!1KsCD&(RH}3R> zv(0`x-*`a~#=Z7wcVM6EbC$GEcMj?^tgAk=EzWhGfvUE|2d?ipQ?*v-dRzHEP03;7 z4jek02l|~S!^ZC%3v%H3jpsD-;8-vgB~Wl@a{13fX1+vHm5+Y3w#={PG1&Fv>%bnV zaI{hP%k>Ro+*(~6P8(a-Q*`es*F9;wjw|?h-*0;j`SiQM#Y`{gK=!F zvdx9r2LSav%cuV6bT~eYxvntNp!neoUgYEKxOirKySXm$b7MH!zEk|j`rPZNEp3t0>4P|N zrCH>}*rczqH_H0MHJpieu3wHH&YZ1PySYST*&$@Fz!yoq(^Rouah0PUjUmmAC;fLI zS79MbE9<%SiSq4S$)BZ}e@|R7V|$%DuUqQ}t`mHcT=XgU3Lmcd+^-$4JML9s5)ONv zI@s8kI@Yp;N8$t4Dn5-Ya&Tuu7i)aRc0453*ycX5#q%eg7$(zM_8Bh8H9=LJ(YTnq{I-I4;w#-_Z#uL`2ZP>!Oiwqb0!RIpC7W;CZ z$H{J*1mz@mpYp^8gJrpfd?|^nn)_`1nm)g@zH7SQ`l-TyqI6`pe%WAh#^da%{2*sM z>cS}vLx_T{;68W0T*E8uQM|p+@z&XD{SI~HtS~7MhqPpE(f*t*9|Z)pIQ{<@=$xax z$c=gb@m`CvrQiPjohlFG=DiD5e z#4>#UGS4x!g;)TIWgJi0;h~GI;Ve!k!^jQb{-0wSRDVW zpln-UUGA03l1J3qyF;8WfwR2hWj*+13FCvCtwSCCCL}-9@$TojHErG=b-nA^fv32?C#s0;uvscewH6ovR;bkiz^V-%+ zm#&=bJl@nfi8?p80QI+?ztZ2>*yxx>dupRmHa9m}%WMP{xBK zGR;SzEXbpAX;y;akbgSz`HWPUl_Gv4s^lWd;~;4pd&f%{(Yw`s-K2Q?Fc}(rJM0(J zB8$dWo{UD4HyIl|ruDPQjVNax6|@wUL=D=`_wbEFOki0HlIpWZQBE?uD)WCjm0=%j z@j}E_!WtEg!#y7_`J>&q^p&2*V;^nALsuY)$J5=lY$q7wpCD!!&EhcXmwQ=cu%y9W z0H-(>pyfAz_9)Ca+J*6G7A5xMo>^(UXT7EL`jcAY;=;%a5`UCOuTM$Hlq_4zFE1z&^NZ-4SPpg}Oc?%#-q<&IggZCE~5o=nSZTKZ#r z-YLv>7Eja%KeJ*pWU!^UV`+a epWx4Svs$8HX5tbY(z+%bmza1#R+vGSng0W0?c}Zi literal 0 HcmV?d00001 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-base-gicv2-psci-aarch32.dts b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-base-gicv2-psci-aarch32.dts new file mode 100644 index 0000000..3a6007d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-base-gicv2-psci-aarch32.dts @@ -0,0 +1,331 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { +}; + +/ { + model = "FVP Base"; + compatible = "arm,vfp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU4:cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU5:cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU6:cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x102>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU7:cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x103>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, + <0x0 0x2c000000 0 0x2000>, + <0x0 0x2c010000 0 0x2000>, + <0x0 0x2c02F000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "rtsm_ve-motherboard.dtsi" + }; + + panels { + panel@0 { + compatible = "panel"; + mode = "XVGA"; + refresh = <60>; + xres = <1024>; + yres = <768>; + pixclock = <15748>; + left_margin = <152>; + right_margin = <48>; + upper_margin = <23>; + lower_margin = <3>; + hsync_len = <104>; + vsync_len = <4>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + }; +}; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-base-gicv2-psci.dtb b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-base-gicv2-psci.dtb new file mode 100644 index 0000000000000000000000000000000000000000..245a6c33b7f6ce0c45f9c7ec8f01010b850e3b69 GIT binary patch literal 10368 zcmb_iOOG5^6~5Jz3<(gN@P5a5GT=m0ad(d=aUud8kL_T^c1&a}gcLQ^)zvc?AV5g1sfgvETn z{~)mo*RLKw8x&Dhj`^R)wH)N>+H92h17e~?J6RqTg)PW(_u(Q3+I0E}$StLJD%}gW zCq*=dW^pe_VptYyta}RAbEk@Qa4MaY+fhE41o`k(JQ-zML2rGnU8PggATN9EXQ{l;C_4ePq}kCzo;%nl&2|0}q}=gjvzPqxM9qO_mv)(VT) zzJ8@hL#+?rZjMFvMsqB7fU_-L9J^b_KgzrRNw*AJ(^19_57f19{iE=c7V7p4_<8@Fw`bk~ z^cSUr--B<@b*cRUrIR1^+Rup3UNZ*0W5`1h=_C6hzJ%XrXP9gAF`nLMtXk(GuDnOp z*w9BT=i^R0n#Xg{KZr~Fk(``Po(+!8m^(B_w+UU=kIE7C8yu6HP3NiJkHlZjCH3i5$W*5 za(u7ik-QuS%5L6pT?9voNQWPm<9ij4SOXdysjIP;h`d*htjFu9W6izAai9;~e&i)x zKMcZcy-za^mL(GclB>rt)oU8MnNUF-{fvG%NjZGA{E;l0ySd{M?}ltV!x{xGij{^i#wF$_T6#zV&Z&)NNulCfvi`Pjom zcJ1D}|6hNC8P#sD8=S%7rOw|U)$KoR+xIcntXJ`~`{)zjVHOfu%=_lrsM-|Yv!71q zBII<4-kbaxF67mNxLX166qP+^}54X@(QwpgMWG{+|HG@=m8eT>o|; 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All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { +}; + +/ { + model = "FVP Base"; + compatible = "arm,vfp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU4:cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU5:cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU6:cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU7:cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, + <0x0 0x2c000000 0 0x2000>, + <0x0 0x2c010000 0 0x2000>, + <0x0 0x2c02F000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "rtsm_ve-motherboard.dtsi" + }; + + panels { + panel@0 { + compatible = "panel"; + mode = "XVGA"; + refresh = <60>; + xres = <1024>; + yres = <768>; + pixclock = <15748>; + left_margin = <152>; + right_margin = <48>; + upper_margin = <23>; + lower_margin = <3>; + hsync_len = <104>; + vsync_len = <4>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + }; +}; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-base-gicv3-psci-aarch32.dtb b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-base-gicv3-psci-aarch32.dtb new file mode 100644 index 0000000000000000000000000000000000000000..474b18885c3e4bafe236889a5d39bfc0da469b59 GIT binary patch literal 10803 zcmb_i&5s;M6|bHpO9BZ_`2LRL4aTvy3Xkz z_3BrzUVU`;{P~eP|5WPano{a3N*(_N?k8|PhU-yWNJ~G3{yKBF`NQPt+uX0!E%-C&{arF*X1Td4chd#)Rnb?F~3E5eu^Kw|$_aEZ^U_ghal#pfb4pKg}|;ia#? zUZkNb_g|YGiwv?m7Q2wy7B7z7tB@ab zNimLcJvuBK<&hC=yKexmP7EZs{sWM!HZ-S-Z#}1F zQ%5-0aC)y>Uc-sL+>ev>ZOJR{Cy`%_gK;$vi1|6En-d@6-y(^k%ok6xpGR;>yi_)z z(LUh)*CtOt{obqv)<1uOj_Ze&-$K6c$ZsQ0ADeQIWBxuzrXMKlzG~n4hv6qJl z5L4dc&bZJ&7<13Zoi82b+4dQK)q02V zZ8aqVZTUg?y<71|PPTpK?Hu9y2YwQPw)`Oc-mUoK`fl4NH_FcVN(9>SgYaV=UWXlD z?j5#$^0WJmm$dyb2zT6lm}9>zN@S31J&vWjZqW{9_EY+rM(HTu>umBgg9NqI1!Tk zQ$6V|_sb|_-pJ}0^0aMb2Dp`x^}42v`GLt_wVZjVlqAy+2h>N6d{p08ji{7XtQuS? zH{Lb~DJKW`(fbzeL~?B0^^7`RhO0-vi!L4)bVJ)Z+hEH5U;Dua3?;fgZr=Az9<22k zoMO+J^qs%Fym6dHIrX|Ods*#;epyOhO~5VxN0j=X<@^CBkMSw>*b^mh`}Fz)|NR@= zsoL$dgH0@q&RPD$Zu`&b_I<<^>(NfxpOfFA3W+Q#zu7iSoA(q0-XIUsh+NiYxL|y| zUzrwY&yFA4<1>;Szlzg$S%joHl|IhW@~koEUzF$|rhV&QTKFO^+GpZf!sfr^7!|AeTPVxKsgKSy83*wv;W#R&78rD66%mFewwkzr5_%%A(k@RW& z8lAc6g~SNl8zs>pPF-X@&ST4oKL4#o$}jtjHkPUXgQI7* zcO4>_pT}@_?R*gOydCOX%!g_))VUZ=vw1tt)I+IKAF07m=i2#b4Td@w^RXHXbuNZe ze4dXp?NO@KCu%U%xpug2&fBqTDT*ZV%rK9k&b7nkWgg=!Ib!ECH5lq#JD;t=Q0HPE zufb5~Vvg2esB#LD4x!bVU(TRKT7;`fFnq2R zwp!xmS$kqo&s4Spo^pm{U9le~H{0v!&MVSl$we&>;@zn4hsh|s$s$|#9S28SuY1F1 zY&rG@?+%9Z3pF;0B@4D|ZE=q*dF0Um)moN`@yWgOP)E*mjBVJ|JZfxO9^9i`9+br& zy3Shrrgq7}d8pekCAP7DxjbfUS{~d_T^^K$$HJ?3TGd#t`}!Fn?FDkeoSi(zo}9hu zb1O4CtW0j4D@-g`>ZtsB#a@v|+nr|hSRm!)bAg?=z6P=q>*Fkg_@#CINkrRJjmJzm z`rCK{dG^ilk$B)9Z)L^s?QerH^e1JAKMr;-Q9qJulf+9s>N00s3DNw{0y*VOO0JeKk| zkhiggHp+h4zF~|T>x;vweS9-T_nxuc6PsmR!N(i>_K&Cks(;qU=#$u~Zf@)sKb*mfe5@TCKa6iX*Cl>#^+(%xiyv8^J1u8RTjaF9 zA1AIfi<}sn^fmTIS%0{OGx5&#%ksmSv$3u>muM(EgzOdgs_gDGCe{tt`S*=8{@a(U zu#lyd-0b?q{5)6kCz|^E;))sDY2AI@THAM>;1lkmPq~8`-sPH3`L26an1uaKs|+?` zOJ8LPkHq_|ReTy*9WSGrfEE4ZQ6z{oV&?TPt z9_99Ptk__%ESE*TAfYO`e{b!EdwyyBM76*6OQ-xdjtq6<&8ke!c$_`P5At4}vT#bn z5Lqc(!F}fWXceC!2Jv>y@z&aE{1tWNtS~ANhqR<^(f*7r9{?%U<@Eo*A#;xMA~)!k z9`?Q&WlMkj*IP!%x$_S4OvGRe^m!iUF#OUY^~BK*N5RTm&nfGEPIl#gG)*Xwh~ayp zS&pd&5r9ODOL7 z>lZGyyJxn}D#={9x+TS8<2cHHuyy(R#qPzev)9jGSCT*T!Zn?N^2XMcOIJ^{&`~C~ zdjhu~ZK0^Ub^2;|V`HPGD(RVxO4!`ov~|#jr5{6Jyu0J}5Q8C6;V8|5aokHHRei|I zf;<|I)k@Is^N(XbpOFf+QpB%BCSOE(93)Mp?|2C#a@*Y3REoC`qrSrT-)=D}vS_ID zqrpIQqoKlMS~nZrigM~GprvTcQiZnjJ$yS76Ij-Q#C%RF#-mKH%KWdDG3}wENQS8z$umm zX!+G2b_z9&c40i4Mv4AFt5z!SX>aAha2x*)a@6J5(MnmUw1}PWrb=F$_=7xpc|w{> zK5+TNN!r7=zRDKWCbzG!FC8bd-!;J=&<#2g$8qukaCA+_mkyhH@{+; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU4:cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU5:cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU6:cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x102>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU7:cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x103>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, // GICD + <0x0 0x2f100000 0 0x200000>, // GICR + <0x0 0x2c000000 0 0x2000>, // GICC + <0x0 0x2c010000 0 0x2000>, // GICH + <0x0 0x2c02f000 0 0x2000>; // GICV + interrupts = <1 9 4>; + + its: its@2f020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x2f020000 0x0 0x20000>; // GITS + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 0 0 4>, + <0 0 1 &gic 0 0 0 1 4>, + <0 0 2 &gic 0 0 0 2 4>, + <0 0 3 &gic 0 0 0 3 4>, + <0 0 4 &gic 0 0 0 4 4>, + <0 0 5 &gic 0 0 0 5 4>, + <0 0 6 &gic 0 0 0 6 4>, + <0 0 7 &gic 0 0 0 7 4>, + <0 0 8 &gic 0 0 0 8 4>, + <0 0 9 &gic 0 0 0 9 4>, + <0 0 10 &gic 0 0 0 10 4>, + <0 0 11 &gic 0 0 0 11 4>, + <0 0 12 &gic 0 0 0 12 4>, + <0 0 13 &gic 0 0 0 13 4>, + <0 0 14 &gic 0 0 0 14 4>, + <0 0 15 &gic 0 0 0 15 4>, + <0 0 16 &gic 0 0 0 16 4>, + <0 0 17 &gic 0 0 0 17 4>, + <0 0 18 &gic 0 0 0 18 4>, + <0 0 19 &gic 0 0 0 19 4>, + <0 0 20 &gic 0 0 0 20 4>, + <0 0 21 &gic 0 0 0 21 4>, + <0 0 22 &gic 0 0 0 22 4>, + <0 0 23 &gic 0 0 0 23 4>, + <0 0 24 &gic 0 0 0 24 4>, + <0 0 25 &gic 0 0 0 25 4>, + <0 0 26 &gic 0 0 0 26 4>, + <0 0 27 &gic 0 0 0 27 4>, + <0 0 28 &gic 0 0 0 28 4>, + <0 0 29 &gic 0 0 0 29 4>, + <0 0 30 &gic 0 0 0 30 4>, + <0 0 31 &gic 0 0 0 31 4>, + <0 0 32 &gic 0 0 0 32 4>, + <0 0 33 &gic 0 0 0 33 4>, + <0 0 34 &gic 0 0 0 34 4>, + <0 0 35 &gic 0 0 0 35 4>, + <0 0 36 &gic 0 0 0 36 4>, + <0 0 37 &gic 0 0 0 37 4>, + <0 0 38 &gic 0 0 0 38 4>, + <0 0 39 &gic 0 0 0 39 4>, + <0 0 40 &gic 0 0 0 40 4>, + <0 0 41 &gic 0 0 0 41 4>, + <0 0 42 &gic 0 0 0 42 4>; + + /include/ "rtsm_ve-motherboard.dtsi" + }; + + panels { + panel@0 { + compatible = "panel"; + mode = "XVGA"; + refresh = <60>; + xres = <1024>; + yres = <768>; + pixclock = <15748>; + left_margin = <152>; + right_margin = <48>; + upper_margin = <23>; + lower_margin = <3>; + hsync_len = <104>; + vsync_len = <4>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + }; +}; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-base-gicv3-psci.dtb b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-base-gicv3-psci.dtb new file mode 100644 index 0000000000000000000000000000000000000000..e175bf02e46c4daadcc8889d59f34d0136c7d986 GIT binary patch literal 10835 zcmb_iO^h5z6|SBoO9BZ_`2UZS4Z(@F#5pWHB->a(b>Y4V+>rF{LUGLRb zufBTq>ZiNs&kwx)Pov;hjloty^wq}P6yB27uV ztb6v3>jn#TFWzz8?S;Bux#PNFS(pCtvLcMx0VMW+1(*1odcX5jTYN4;`>Adz5MKKF zYegEm^59l|EV9??W3h*Fw#AEM_bSTob>tsFW=sgbFq@j8F7Zuc3%K%t_0u5J`D9v5 zqFj#-%f@+R1l#UUOdGl#lru<>+;Zm2@~#xu%E`YhUt27{$CPV~=46_=EvIGIW&@{p zyX6g>=*xpRS>F;PxOk96elZCq)jS~P=bUa%e29OGB#JU$JW1ai!zJ-j*?>m-koRAi zJpJ@LvldwY{s}s+A69+?`GF(9i9E;1lzW`t?{Q@MfwJpc|0w*Vg|a;be%^no_S73F z`iCQf-+i|#S!%!6k;#v8>1V`euO5TmG3Wr1KC&<3OZa`ZNv+mnJiSk7vD6{1yoa5! zp^u33ai<-Z$8(VH$L0EwoUBZqHIDU|J2XeT4j+{x`MDgK*JBMo*5m%r9Bu!P%8_yH za->{xtgi=$=4ktWRF0@$<4C#W*wGu9?ZYACQMPf`Jt{}8d6om?v04K$)}6LQq%A)z z$9F0o$;)zJ-p(7Yi{K~`Y0D4G@tulCtN}HSl%27bh`d{ltjFu9W6izAa-a|Ge&i)x zKMcZMcb{e)EQ=BuBwLST>aJtOj_ES0M0eb-uQ#bd zdR5=h9agPqn_PcoE#HYlf2J1#%l#6{m^ZR| z6nWaVGK1a9$a;NK#{AIaFI&z$bV`z`hy(0{Mn10Zt435xD^?Azlv{5agp`v5{OElX zcOp49?ixoOFT>TN-$fTs3c8_dooz7X`9S-@2Mi^;K5pLkOdhQD9(R&GXVQ26^71Be z8s*gMy6k1OSNdfsd9?wz{2x&2f0pz6oIJ*-)MLMtyzSHL_x$&7Y^Q3s*9|tYP&#M* z54!C?qucipSFA@nWq+RhHdRPuQTffbVcNW-81RO9kVfRPR^x*4@qTGqpglW&Y>&@S zcKj+%-(eAw=2ZGPOUtv!oPSZGgP8WMe`(?KxM-h==M0v0}iPW1V2G*W)qXSA_Q{U01Xvn5AIU$$+^=P{IBjQG;2&n$H=hJBp3L!FCZ zejY=ei=hwZG1R#juG8}v>RgOnE1)hDbuNZOId8`qUa7}5X&z(ODFNVzXW)4Zb#7aX zzj+LGE(YVbfT7OCV2xS8Q0HQ>_AFqib1_^i=lM|QVi<<=7$-DQTD=Pq!TdagyKCqD zkmv1C=VCt4fT7OCaGK5Aai$(hmHJQvhC0{IhZ``|xtNbMV5oC3oZ|C*oN13zr9Rex zq0Y6#b#va1T}x3UiO*#780uU*Twdle&XOZ`KGlGs&b9OD1`KsB=HUhmbuQ+31BN;m z^GE}RIv4Y31BN;mv(kW}&c!^|fT7OCe5L_Ior`(A0YjaO`D_D*Iu~=I0YjaOd7=SB zor`(00Ye=zp7UxEqU>qVdw>!yCzQFpOl(zd%-kwTw8!z3tn zd+qYACUi{PBN%_R_I&}Xa2T5$ks6EnRlT1uPLP|)n?1+-JMdJ=-ZjHnrq``CO&r&t zdb$~cEV0a++4RO2K7v} ze0hdsU9le~*SqWK?kmz_$we&>mIwD!mj`9xvG8gh1xUnl-Pg|u>2@F|%=+Xp_T=nMpIe#HVP$gTTw!9l zQpe@jEB1>#+Ud2c#{wxYp9}1~^)--{SRZE@#4oMuPbS)?YCUAi(cji1$g^*TkHiD_ zcq=m=C`y_rZ&}vhPKPCl~$RKF1?e7$pgc9WJy|al!m*`B2cm9BUhg*k@bo zddw9bwh)3U$hP|#Gfb8nP@mytr_YQr&UK#sOk3gu+jpETTkEyn8V+en4jZ@O(AhlD z?>s?QerH^e1JAKMr;-Q9qK7-j+9s<%4+ZrSNw{0ySJZF0JeKm;k+-phHp+h4zF~}8 z>x;vweSAGd_nx-h6PsmR!N(g1_K&Cks(;qU=#$uK;)1hfYyE|b=dYYSw{_u#dVI;4 z3!i81k`JS2k&j(h?uyUcM?j8&>mO`0@&%=N-f^TC`7kPIr-={7v9-=N7iJ#{P{-4J z$`6Z&B~nHZJnvC?1hd`2qBBd>FZld@xRT&*#Pf-;m|iA#IDD zGJddbw>J)oAI{)KKGu$nAI7(x>k>aV2IHOE#gDAdy^gb`Epl2vh!aO%)W19`J#vJ%5Upk!)XH)}qL?yHAqB)QtNq&L{D>zs&mdhev zkWiJ}zq@wLJ-@Vmth!(Qg;V}(M~1p}t16Q-9%qm7gS=O#ES%CXL{`dHaIZZdt>QDp zFy3i6-dbC&zoL$u6~+bPke0M9+OOI20gzH%PXGTKGUq5Sa)WN^e(xJmw)Dq;y28Pubxi zi><*dPRE1D4q&q_1EL`$*Ou%)(9xEAd08-ul7evjcZPZ00_$?GToxTmwY}TK`4VR} z-<`7_{IY}@hFc{+rn6=F6L`J;np56I{%4NN_w96>wf6$@Y{SYgnY@)F$h%HCCkhGJ z@_po)D8tUux6YmJU%U9?nX~;%FJ3x->FU`l7fx-RJyT+^J}$j>_58(d|Mb=wC7JV= zx1?BXJdX13Z(X{2p?_iP%++&OmE=!9e?@1Yyteh?#mgr;=qMB0J%QT~w@}pII(50f zv9ZxnmGtyRC2VeP+B)dN(vKi8-raG#kHL_raGYkrB;HOURei|If;<{c)JiZI@Q-Ca zpOFf+QpB%BCSOE(93*X}?|2C#a@X9~REoC`k&iawfdwS-Xu7wW?FJ+K+eZzeSsX_F$$l0oENQS8z$ummX!+G2dI~j)_Fz1k zMT!1Et5z!SX>aAhXb1lua@6J5(MnmUw1}PWrb=F$_`^JUc}ki}K5+S?X}XPXeU&Zz zrwjkL+9!z%CiZ-t4>HK&)$)*#3gs*6Y+R5Uv%Vk9? zWb6fA7f&+ssaG0L)JUoqCyw21nHG|+w8o(_lTQnh)|s3UT; z(m2e=vvD$U^=P9>A0#(|{lZ6Jao4u*8p^#Oj|V&Te@mLz5Ua!KC2-n)c*k~k?$Y? literal 0 HcmV?d00001 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-base-gicv3-psci.dts b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-base-gicv3-psci.dts new file mode 100644 index 0000000..57f3516 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-base-gicv3-psci.dts @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { +}; + +/ { + model = "FVP Base"; + compatible = "arm,vfp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU4:cpu@100 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU5:cpu@101 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU6:cpu@102 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU7:cpu@103 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, // GICD + <0x0 0x2f100000 0 0x200000>, // GICR + <0x0 0x2c000000 0 0x2000>, // GICC + <0x0 0x2c010000 0 0x2000>, // GICH + <0x0 0x2c02f000 0 0x2000>; // GICV + interrupts = <1 9 4>; + + its: its@2f020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x2f020000 0x0 0x20000>; // GITS + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 0 0 4>, + <0 0 1 &gic 0 0 0 1 4>, + <0 0 2 &gic 0 0 0 2 4>, + <0 0 3 &gic 0 0 0 3 4>, + <0 0 4 &gic 0 0 0 4 4>, + <0 0 5 &gic 0 0 0 5 4>, + <0 0 6 &gic 0 0 0 6 4>, + <0 0 7 &gic 0 0 0 7 4>, + <0 0 8 &gic 0 0 0 8 4>, + <0 0 9 &gic 0 0 0 9 4>, + <0 0 10 &gic 0 0 0 10 4>, + <0 0 11 &gic 0 0 0 11 4>, + <0 0 12 &gic 0 0 0 12 4>, + <0 0 13 &gic 0 0 0 13 4>, + <0 0 14 &gic 0 0 0 14 4>, + <0 0 15 &gic 0 0 0 15 4>, + <0 0 16 &gic 0 0 0 16 4>, + <0 0 17 &gic 0 0 0 17 4>, + <0 0 18 &gic 0 0 0 18 4>, + <0 0 19 &gic 0 0 0 19 4>, + <0 0 20 &gic 0 0 0 20 4>, + <0 0 21 &gic 0 0 0 21 4>, + <0 0 22 &gic 0 0 0 22 4>, + <0 0 23 &gic 0 0 0 23 4>, + <0 0 24 &gic 0 0 0 24 4>, + <0 0 25 &gic 0 0 0 25 4>, + <0 0 26 &gic 0 0 0 26 4>, + <0 0 27 &gic 0 0 0 27 4>, + <0 0 28 &gic 0 0 0 28 4>, + <0 0 29 &gic 0 0 0 29 4>, + <0 0 30 &gic 0 0 0 30 4>, + <0 0 31 &gic 0 0 0 31 4>, + <0 0 32 &gic 0 0 0 32 4>, + <0 0 33 &gic 0 0 0 33 4>, + <0 0 34 &gic 0 0 0 34 4>, + <0 0 35 &gic 0 0 0 35 4>, + <0 0 36 &gic 0 0 0 36 4>, + <0 0 37 &gic 0 0 0 37 4>, + <0 0 38 &gic 0 0 0 38 4>, + <0 0 39 &gic 0 0 0 39 4>, + <0 0 40 &gic 0 0 0 40 4>, + <0 0 41 &gic 0 0 0 41 4>, + <0 0 42 &gic 0 0 0 42 4>; + + /include/ "rtsm_ve-motherboard.dtsi" + }; + + panels { + panel@0 { + compatible = "panel"; + mode = "XVGA"; + refresh = <60>; + xres = <1024>; + yres = <768>; + pixclock = <15748>; + left_margin = <152>; + right_margin = <48>; + upper_margin = <23>; + lower_margin = <3>; + hsync_len = <104>; + vsync_len = <4>; + sync = <0>; + vmode = "FB_VMODE_NONINTERLACED"; + tim2 = "TIM2_BCD", "TIM2_IPC"; + cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; + caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; + bpp = <16>; + }; + }; +}; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-foundation-gicv2-psci.dtb b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-foundation-gicv2-psci.dtb new file mode 100644 index 0000000000000000000000000000000000000000..5acb139a3cc99c30314df26296bd4246b2972070 GIT binary patch literal 7673 zcmbtZ&yO5O6|NqfB?iJK{Kf&Y@j?jJbUZT~6B`j2MIz#mATH#9gjT&hwdXUf+JEchyy1i4xG3l#2?^0+_(mb0~aI?AjAduzE}NvUV9eH>n*9L-+N!xtFK=D zoa#S5^Pj&t_xXQ2=f3US^Kaq(GM?w~Jc|cu^c&bOQM%6`rYO7~`c>-(VBaS8<~!fr zd9z$C7fG9yOUX^_3ZAW`F2;w)ReX>%-cdRBCspm6MzT5PW1Zwdzp7t_JTm&U)1&lu z+4xWg@hHhNcouIgdmYc~*PG(tdQrBweSJ_S_2PO~9#%)md~ZDI()CqRxAVy@swffa zW!Y~%cG+a3?AwoB_F$vz_a3`!+Lx8~S52Bp3ql)qAxq3@kEgFpB<7+_UYYfZl+alJ zpea%sR9`$8_C@uRVPBj8XI{;J5BSqY|0(p#(1l-Gt-7x6^Iz>SEziDXijX%hk}Amg zs%d>4dWTq9`%ckvKSxH^5$XZnIkGtA9-qM2GlO(6tW9mo0K1H*M0c z#~j=G3l4457t)p{_r8jSHF?k#gv3#Bn(8&&^TWe^HJc*Onvop5t)totvY!|DqgGe!!8saLi|M znxwbw8pN@)B}NEH+BWtn##gU%d{L(#@m2VutWW1RxsoHnEP0VH+71{^V%yR2e4iGi zd*Su;{qT0(Tl{8AteEwxYU8wAwso23zMjtx*R=$nUqVrtJ6Ka&e-bCt8}U(=%I2V^ zTVe@yXuG}xRpZRQyBc7zL5%i0e6F0ip-N&zkjCMK-yM<0oxRsbT*jDo_`|wB0$(lO z%!ze&+m0dH_$WWdnYzTH%?e*bK_dPvp7nYW_b4%RKwrl*&iz;Ye$>bxHZs;8$)ok& zd+MKmh8t7we3smtYS&8rpRo167V3}D*DTlZ3+vXkAJK$F7VEZY9bKIgd$v<`Js(j= zir(YTVVxA7T=oWB5W|Rj1#4h_jWI+yvuTVGvyRh`2_XeetXE=O75#erP<(+L%Z#Rf zjW0cX9S{98ajjMP8%F+SCrceT%0U&L=mWRaWJQG?_@Fyg&_8`##l!rnGalN$6NrpQ zpEw!2ibIQ_vx7Pt{Yd%@emfieO8OjrJ6rdX0IH4ag(L>Vl!X{^{wOEL{8u5T{Iboc z^Va2>+I}`@oh1-K{3h}V_OuXY%$7;QMMS{rWj?5aV=Dgvc+^>!Yq5O z#n=^E&U6d2${A8Ip0R8>?*EEWwiw5WVw5e0xc3-ki(&5f7-frLE$A`I7TY!$Ws7kb zC>Jv%U|s*`QQ4OJ7>rtuvc*1bFv=F=FxGNrNW<#fCk;l~miv^!C|m5)2BT~-P7$ro zOcz+4`>eqz+j9JGsO2bIjORDSC|iuvPcbtUVa19lr6SnFv=Et z(O{Gg!6;jd`?j{7vc+C97-frn*RKEbYoT7Fe=tTWMH5Q49r;geS!lU+wC^l6l=jP$I z-;AVX}T!01XCCk_W`3_+Jv2m2KTCgsL)ud$r4 zU**(|Tz)xWL0^kJHS)~J{rOS*o%^-=X1l3NyC1sD8??E~Cz#@LJ9BoM*}8R`Sr_Lz z&o}ggxJV4xc5VN2Y(MMVX!(Foe?fRYK8*AxAD*c$$fv(_JRcvndXo?1e?dO|MdtbV zu-7;Fpr4+c&)o&?g5_^AeTyGEXC^luHGa4&Z1Pb*I(|6H2IJ@MqCEP4<45Mkd}@}H zO-`>qiW5fY8Ju(-!MY@4S|W*zd~=>EKb)OLSHi^hOPQTAPjP!}XL&c)JFc?L!Uxl! zKe6Ua9?6xb+s*jV2OrCo{K=K}C*q13JD#*( zywKmHD`&;)IIHoIWdDGN1nd~=f9Amt+qV_+jEf>Gp^E>oKC_0+SY3mWv5~b<&LG&0 zR(aBvwO*l$4{kDBJrqk$n0o#%?Y(2y+|dm;`~EKt{)v~=!0EMIINWvbH>;-d%OIDBhhoF`HEi?yRe9Ifv{6A#z9s5V zcYTU`C2@fvmgL=4Q`44JSTXorsB;{HZBlfFFkbvJJ&kd(;!mDrMX#kyTKqmEZLP>$iALw)ESvDCu4@Q$kMtzF7wvflan*; iNq#puZDRC1k1_opC!JVzwm2GoTJ6r6; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, + <0x0 0x2c000000 0 0x2000>, + <0x0 0x2c010000 0 0x2000>, + <0x0 0x2c02F000 0 0x2000>; + interrupts = <1 9 0xf04>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 4>, + <0 0 1 &gic 0 1 4>, + <0 0 2 &gic 0 2 4>, + <0 0 3 &gic 0 3 4>, + <0 0 4 &gic 0 4 4>, + <0 0 5 &gic 0 5 4>, + <0 0 6 &gic 0 6 4>, + <0 0 7 &gic 0 7 4>, + <0 0 8 &gic 0 8 4>, + <0 0 9 &gic 0 9 4>, + <0 0 10 &gic 0 10 4>, + <0 0 11 &gic 0 11 4>, + <0 0 12 &gic 0 12 4>, + <0 0 13 &gic 0 13 4>, + <0 0 14 &gic 0 14 4>, + <0 0 15 &gic 0 15 4>, + <0 0 16 &gic 0 16 4>, + <0 0 17 &gic 0 17 4>, + <0 0 18 &gic 0 18 4>, + <0 0 19 &gic 0 19 4>, + <0 0 20 &gic 0 20 4>, + <0 0 21 &gic 0 21 4>, + <0 0 22 &gic 0 22 4>, + <0 0 23 &gic 0 23 4>, + <0 0 24 &gic 0 24 4>, + <0 0 25 &gic 0 25 4>, + <0 0 26 &gic 0 26 4>, + <0 0 27 &gic 0 27 4>, + <0 0 28 &gic 0 28 4>, + <0 0 29 &gic 0 29 4>, + <0 0 30 &gic 0 30 4>, + <0 0 31 &gic 0 31 4>, + <0 0 32 &gic 0 32 4>, + <0 0 33 &gic 0 33 4>, + <0 0 34 &gic 0 34 4>, + <0 0 35 &gic 0 35 4>, + <0 0 36 &gic 0 36 4>, + <0 0 37 &gic 0 37 4>, + <0 0 38 &gic 0 38 4>, + <0 0 39 &gic 0 39 4>, + <0 0 40 &gic 0 40 4>, + <0 0 41 &gic 0 41 4>, + <0 0 42 &gic 0 42 4>; + + /include/ "fvp-foundation-motherboard.dtsi" + }; +}; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-foundation-gicv3-psci.dtb b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-foundation-gicv3-psci.dtb new file mode 100644 index 0000000000000000000000000000000000000000..34bf8db662ccd190da6de31ab70f491b6d38c54d GIT binary patch literal 8140 zcmbtZO^@V887?=;kOjgfe19bDFvCY?)y{PHBxHjKv=BsGK)H|u0*yTG>KSY8wz1v4 zGvSa$AjE-dIB-Hjh&v|^9D~FG2_*hNxF9Y_kpfrXdETnB%WgB;*(u4cdf$5Lt*74l zbonoj|L31d-TISK>KjTu{RHA?@H~l!X@t@5m3r!rOx@>;Auv(z?X>TL{wDKYe)W~z zm-F>%5!Fe)5;XHZfoCTwv+;6MgeOs@6@`sHFG^ii0#n32f`>e4*U5WGk34y5XkJ;d|UVU?X6W_f+4%ac4R7l%o{EKZ~O(RgCR;W{eo`Q$~4C}HYl z*{?rv*=VcmHy^m{$yV8KKXBQ&DJ$(SsyLArm^SPqEk36{oIX1dpNlYgcGd_|!uk4p zRTfj>Y5j;))5p%owk3x2J2rgNqI;`rb zZpR$k`U?(iuP>x6RjPFn3TyJ$MZ9rq{WBePNCa2%ox#!yQXXrRzo%|Nk3r~I< zX|~7a2b@bgp8Rero3^>NLd5iu&*LSN*YKhr$;s#0 z;n*E>SLW!}yz6o#Kc6Ghrmx}0?zq1)N7w%Aa^$%7IZ|#ocIV!eIlA^=mm|t|I8qjl z=`4(+_{?8}ICgeKi3Eac8~YUFtC2arDASJE%5;{O7xOz@$q}FyEO5b1lSh^4cHMZs zPYuHBCVK3?iIt7TZnDCPS+0vZjPq4p=4q zl6q5?t!&q(u*oH_3E+Xx1Q-6qY#d6GV+H?DdR3VT>>o-@2t@DA#K(H*MOq0t|hYR{A__eKp_FVt5KAsO< z|FxWc#4H5Esqt}P2j}06`K}8W(Qdv>y_{^yseIQBs_(;)!9fK=yY70B+wyV zStJ9_W5LHouRd>|?~2UU?>|^D%5=-wt&?hUq?r zIv+zH^fA==7_QTO40S%ntrbu=fjS?w3^P3mLZIwb(Scy{SysPpUM`0Hb+ z^D*eZEev%&25Za~hB_aEwPy=MosZ#K+2=!@kKr)vW4xh>-1a+91p9gtv2W)Cko$J1 z^D!SBz)q0YDSkpT>KKIWqX80vfsr+A-_H|>$D)W-)f)cJO} zZuafCwG>$rcn0ocsPpY`dFf-kB}eQ$J%FLkxAUn140S%{)&Pb&AG14vq0YyAdH_S6 zkJ%f*Q0HUz2Qbw6n9mGgsPi$O9l%iMV?H;4q0YyAegH$Ak9lSQL!FN~7{E~HV{Q*% zs3Ruuu1z4yo(6sJ*Rql?9j?*rH#uLptDNy>mW9PsJ;Z)V+x}h!)3SdCnzuJAUC(D@ zb8u_V$#QP1vML^@(dxx%Je``4FmmIb#&JI4hGR!J^{j{IE|z6h5T|!%&t+$?AOM?~ZLIk|kB&{pgL|USgR=10 zx~ij9gXLOj&b8S|B&V|OfV1}Gyh@)tnWMwW0BU?Lk5Rvaj7Z#NISIFylnw0|i4+Ma9W+!32Zj#&Pd_ zH$n0p`I-SruO=+0OG!_?^vp}k$ECAHJ3OB_neC=5?e1O3cG_H|6HIZrVH<8UTi3Rk zV~lg1=Rn#)ABhjxcGrHKIYtMpbF1YYKFuZX)%eiU+kD)ZxCWo*;`nNO*y?RQ^#3*e z(_BVhjSqW$n-Bc*@OM_iFM-W(shC-@@<}2FN6=`W}P5E z^!Mms$X}bJ#E-7y6CM(6F(R?EkGOlj z!*${^IUU$?n|gnWGTg(0Y<({O+OSzL(2x9{>eve{hyVm)ILCg4m}?S)a9V7VEMI8n zfMHt}WQuic$*N~-AC)2Z*h=kJ$!prC zD_tg0I#DLZ!B^y&jgM4@(`&v^_+N2ct*b(>OgdjKMTdW+*yfLm{GKkUqkx)p&0K}L z%M0Asi3tp`D79C3Rh<`R#o)g^Yd8ekD6@qyUi2!y2ytPh&yzaz*M;O&h^G{b^OHl|F}Yz0s+;6j%GL_l&p7XmyG| zWS+XYk#3ch%BsY>t5$OC4wt3={+cwETq=gEb#{XL)z%jN5#m2#b+@Y$*YHckT%pUK z#C>DYa5Cw9T^H**T;aO1Ql~|d`vmrlLONXFmE~mM?Zl%@N0})a(z{s_m-!}7YhNFo k59*`zUUX4~7zjMoxU=Qh&9gFDoOb_~+hgZ=xn9NUf5^A1+5i9m literal 0 HcmV?d00001 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-foundation-gicv3-psci.dts b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-foundation-gicv3-psci.dts new file mode 100644 index 0000000..2c84559 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-foundation-gicv3-psci.dts @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +/memreserve/ 0x80000000 0x00010000; + +/ { +}; + +/ { + model = "FVP Foundation"; + compatible = "arm,fvp-base", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + aliases { + serial0 = &v2m_serial0; + serial1 = &v2m_serial1; + serial2 = &v2m_serial2; + serial3 = &v2m_serial3; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xc4000003>; + sys_poweroff = <0x84000008>; + sys_reset = <0x84000009>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + }; + + idle-states { + entry-method = "arm,psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <40>; + exit-latency-us = <100>; + min-residency-us = <150>; + }; + + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <500>; + exit-latency-us = <1000>; + min-residency-us = <2500>; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU2:cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + CPU3:cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x7F000000>, + <0x00000008 0x80000000 0 0x80000000>; + }; + + gic: interrupt-controller@2f000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + reg = <0x0 0x2f000000 0 0x10000>, // GICD + <0x0 0x2f100000 0 0x200000>, // GICR + <0x0 0x2c000000 0 0x2000>, // GICC + <0x0 0x2c010000 0 0x2000>, // GICH + <0x0 0x2c02f000 0 0x2000>; // GICV + interrupts = <1 9 4>; + + its: its@2f020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x2f020000 0x0 0x20000>; // GITS + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xff01>, + <1 14 0xff01>, + <1 11 0xff01>, + <1 10 0xff01>; + clock-frequency = <100000000>; + }; + + timer@2a810000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x2a810000 0x0 0x10000>; + clock-frequency = <100000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + frame@2a830000 { + frame-number = <1>; + interrupts = <0 26 4>; + reg = <0x0 0x2a830000 0x0 0x10000>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 60 4>, + <0 61 4>, + <0 62 4>, + <0 63 4>; + }; + + smb { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 63>; + interrupt-map = <0 0 0 &gic 0 0 0 0 4>, + <0 0 1 &gic 0 0 0 1 4>, + <0 0 2 &gic 0 0 0 2 4>, + <0 0 3 &gic 0 0 0 3 4>, + <0 0 4 &gic 0 0 0 4 4>, + <0 0 5 &gic 0 0 0 5 4>, + <0 0 6 &gic 0 0 0 6 4>, + <0 0 7 &gic 0 0 0 7 4>, + <0 0 8 &gic 0 0 0 8 4>, + <0 0 9 &gic 0 0 0 9 4>, + <0 0 10 &gic 0 0 0 10 4>, + <0 0 11 &gic 0 0 0 11 4>, + <0 0 12 &gic 0 0 0 12 4>, + <0 0 13 &gic 0 0 0 13 4>, + <0 0 14 &gic 0 0 0 14 4>, + <0 0 15 &gic 0 0 0 15 4>, + <0 0 16 &gic 0 0 0 16 4>, + <0 0 17 &gic 0 0 0 17 4>, + <0 0 18 &gic 0 0 0 18 4>, + <0 0 19 &gic 0 0 0 19 4>, + <0 0 20 &gic 0 0 0 20 4>, + <0 0 21 &gic 0 0 0 21 4>, + <0 0 22 &gic 0 0 0 22 4>, + <0 0 23 &gic 0 0 0 23 4>, + <0 0 24 &gic 0 0 0 24 4>, + <0 0 25 &gic 0 0 0 25 4>, + <0 0 26 &gic 0 0 0 26 4>, + <0 0 27 &gic 0 0 0 27 4>, + <0 0 28 &gic 0 0 0 28 4>, + <0 0 29 &gic 0 0 0 29 4>, + <0 0 30 &gic 0 0 0 30 4>, + <0 0 31 &gic 0 0 0 31 4>, + <0 0 32 &gic 0 0 0 32 4>, + <0 0 33 &gic 0 0 0 33 4>, + <0 0 34 &gic 0 0 0 34 4>, + <0 0 35 &gic 0 0 0 35 4>, + <0 0 36 &gic 0 0 0 36 4>, + <0 0 37 &gic 0 0 0 37 4>, + <0 0 38 &gic 0 0 0 38 4>, + <0 0 39 &gic 0 0 0 39 4>, + <0 0 40 &gic 0 0 0 40 4>, + <0 0 41 &gic 0 0 0 41 4>, + <0 0 42 &gic 0 0 0 42 4>; + + /include/ "fvp-foundation-motherboard.dtsi" + }; +}; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-foundation-motherboard.dtsi b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-foundation-motherboard.dtsi new file mode 100644 index 0000000..9d29e48 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/fvp-foundation-motherboard.dtsi @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of the ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + motherboard { + arm,v2m-memory-map = "rs1"; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + ethernet@2,02000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + virtio_block@0130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x1000>; + interrupts = <0x2a>; + }; + }; + + v2m_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + + mcc { + compatible = "arm,vexpress,config-bus", "simple-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + /* + * Not supported in FVP models + * + * reset@0 { + * compatible = "arm,vexpress-reset"; + * arm,vexpress-sysreg,func = <5 0>; + * }; + */ + + muxfpga@0 { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + /* + * Not used - Superseded by PSCI sys_poweroff + * + * shutdown@0 { + * compatible = "arm,vexpress-shutdown"; + * arm,vexpress-sysreg,func = <8 0>; + * }; + */ + + /* + * Not used - Superseded by PSCI sys_reset + * + * reboot@0 { + * compatible = "arm,vexpress-reboot"; + * arm,vexpress-sysreg,func = <9 0>; + * }; + */ + + dvimode@0 { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/rtsm_ve-motherboard.dtsi b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/rtsm_ve-motherboard.dtsi new file mode 100644 index 0000000..6aa40ff --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/fdts/rtsm_ve-motherboard.dtsi @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + motherboard { + arm,v2m-memory-map = "rs1"; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; + }; + + vram@2,00000000 { + compatible = "arm,vexpress-vram"; + reg = <2 0x00000000 0x00800000>; + }; + + ethernet@2,02000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + + aaci@040000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + mmci@050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9 10>; + cd-gpios = <&v2m_sysreg 0 0>; + wp-gpios = <&v2m_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; + clock-names = "clcdclk", "apb_pclk"; + mode = "XVGA"; + use_dma = <0>; + framebuffer = <0x18000000 0x00180000>; + }; + + virtio_block@0130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x1000>; + interrupts = <0x2a>; + }; + }; + + v2m_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + mcc { + compatible = "arm,vexpress,config-bus", "simple-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + v2m_oscclk1: osc@1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + /* + * Not supported in FVP models + * + * reset@0 { + * compatible = "arm,vexpress-reset"; + * arm,vexpress-sysreg,func = <5 0>; + * }; + */ + + muxfpga@0 { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + /* + * Not used - Superseded by PSCI sys_poweroff + * + * shutdown@0 { + * compatible = "arm,vexpress-shutdown"; + * arm,vexpress-sysreg,func = <8 0>; + * }; + */ + + /* + * Not used - Superseded by PSCI sys_reset + * + * reboot@0 { + * compatible = "arm,vexpress-reboot"; + * arm,vexpress-sysreg,func = <9 0>; + * }; + */ + + dvimode@0 { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl1/bl1.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl1/bl1.h new file mode 100644 index 0000000..9fb3cb2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl1/bl1.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BL1_FWU_H__ +#define __BL1_FWU_H__ + +#include + +/* + * Defines for BL1 SMC function ids. + */ +#define BL1_SMC_CALL_COUNT 0x0 +#define BL1_SMC_UID 0x1 +/* SMC #0x2 reserved */ +#define BL1_SMC_VERSION 0x3 + +/* + * Corresponds to the function ID of the SMC that + * the BL1 exception handler service to execute BL31. + */ +#define BL1_SMC_RUN_IMAGE 0x4 + +/* + * BL1 SMC version + */ +#define BL1_SMC_MAJOR_VER 0x0 +#define BL1_SMC_MINOR_VER 0x1 + +/* + * Defines for FWU SMC function ids. + */ + +#define FWU_SMC_IMAGE_COPY 0x10 +#define FWU_SMC_IMAGE_AUTH 0x11 +#define FWU_SMC_IMAGE_EXECUTE 0x12 +#define FWU_SMC_IMAGE_RESUME 0x13 +#define FWU_SMC_SEC_IMAGE_DONE 0x14 +#define FWU_SMC_UPDATE_DONE 0x15 + +/* + * Number of FWU calls (above) implemented + */ +#define FWU_NUM_SMC_CALLS 6 + +#if TRUSTED_BOARD_BOOT +# define BL1_NUM_SMC_CALLS (FWU_NUM_SMC_CALLS + 4) +#else +# define BL1_NUM_SMC_CALLS 4 +#endif + +/* + * The macros below are used to identify FWU + * calls from the SMC function ID + */ +#define FWU_SMC_FID_START FWU_SMC_IMAGE_COPY +#define FWU_SMC_FID_END FWU_SMC_UPDATE_DONE +#define is_fwu_fid(_fid) \ + ((_fid >= FWU_SMC_FID_START) && (_fid <= FWU_SMC_FID_END)) + +#ifndef __ASSEMBLY__ +#include + +/* + * Check if the total number of FWU SMC calls are as expected. + */ +CASSERT(FWU_NUM_SMC_CALLS == \ + (FWU_SMC_FID_END - FWU_SMC_FID_START + 1),\ + assert_FWU_NUM_SMC_CALLS_mismatch); + +#endif /* __ASSEMBLY__ */ +#endif /* __BL1_FWU_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl1/tbbr/tbbr_img_desc.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl1/tbbr/tbbr_img_desc.h new file mode 100644 index 0000000..56f3507 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl1/tbbr/tbbr_img_desc.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TBBR_IMG_DESC_H__ +#define __TBBR_IMG_DESC_H__ + +#include + +extern image_desc_t bl1_tbbr_image_descs[]; + +#endif /* __TBBR_IMG_DESC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl31/bl31.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl31/bl31.h new file mode 100644 index 0000000..8352c49 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl31/bl31.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BL31_H__ +#define __BL31_H__ + +#include + +/******************************************************************************* + * Function prototypes + ******************************************************************************/ +void bl31_next_el_arch_setup(uint32_t security_state); +void bl31_set_next_image_type(uint32_t type); +uint32_t bl31_get_next_image_type(void); +void bl31_prepare_next_image_entry(void); +void bl31_register_bl32_init(int32_t (*)(void)); +void bl31_warm_entrypoint(void); + +#endif /* __BL31_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl31/interrupt_mgmt.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl31/interrupt_mgmt.h new file mode 100644 index 0000000..0172b60 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl31/interrupt_mgmt.h @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __INTERRUPT_MGMT_H__ +#define __INTERRUPT_MGMT_H__ + +#include + +/******************************************************************************* + * Constants for the types of interrupts recognised by the IM framework + ******************************************************************************/ +#define INTR_TYPE_S_EL1 0 +#define INTR_TYPE_EL3 1 +#define INTR_TYPE_NS 2 +#define MAX_INTR_TYPES 3 +#define INTR_TYPE_INVAL MAX_INTR_TYPES +/* + * Constant passed to the interrupt handler in the 'id' field when the + * framework does not read the gic registers to determine the interrupt id. + */ +#define INTR_ID_UNAVAILABLE 0xFFFFFFFF + + +/******************************************************************************* + * Mask for _both_ the routing model bits in the 'flags' parameter and + * constants to define the valid routing models for each supported interrupt + * type + ******************************************************************************/ +#define INTR_RM_FLAGS_SHIFT 0x0 +#define INTR_RM_FLAGS_MASK 0x3 +/* Routed to EL3 from NS. Taken to S-EL1 from Secure */ +#define INTR_SEL1_VALID_RM0 0x2 +/* Routed to EL3 from NS and Secure */ +#define INTR_SEL1_VALID_RM1 0x3 +/* Routed to EL1/EL2 from NS and to S-EL1 from Secure */ +#define INTR_NS_VALID_RM0 0x0 +/* Routed to EL1/EL2 from NS and to EL3 from Secure */ +#define INTR_NS_VALID_RM1 0x1 +/* Routed to EL3 from NS. Taken to S-EL1 from Secure and handed over to EL3 */ +#define INTR_EL3_VALID_RM0 0x2 +/* Routed to EL3 from NS and Secure */ +#define INTR_EL3_VALID_RM1 0x3 +/* This is the default routing model */ +#define INTR_DEFAULT_RM 0x0 + +/******************************************************************************* + * Constants for the _individual_ routing model bits in the 'flags' field for + * each interrupt type and mask to validate the 'flags' parameter while + * registering an interrupt handler + ******************************************************************************/ +#define INTR_TYPE_FLAGS_MASK 0xFFFFFFFC + +#define INTR_RM_FROM_SEC_SHIFT SECURE /* BIT[0] */ +#define INTR_RM_FROM_NS_SHIFT NON_SECURE /* BIT[1] */ +#define INTR_RM_FROM_FLAG_MASK 1 +#define get_interrupt_rm_flag(flag, ss) (((flag >> INTR_RM_FLAGS_SHIFT) >> ss) \ + & INTR_RM_FROM_FLAG_MASK) +#define set_interrupt_rm_flag(flag, ss) (flag |= 1 << ss) +#define clr_interrupt_rm_flag(flag, ss) (flag &= ~(1 << ss)) + + +/******************************************************************************* + * Macros to validate the routing model bits in the 'flags' for a type + * of interrupt. If the model does not match one of the valid masks + * -EINVAL is returned. + ******************************************************************************/ +#define validate_sel1_interrupt_rm(x) ((x) == INTR_SEL1_VALID_RM0 ? 0 : \ + ((x) == INTR_SEL1_VALID_RM1 ? 0 :\ + -EINVAL)) + +#define validate_ns_interrupt_rm(x) ((x) == INTR_NS_VALID_RM0 ? 0 : \ + ((x) == INTR_NS_VALID_RM1 ? 0 :\ + -EINVAL)) + +#define validate_el3_interrupt_rm(x) ((x) == INTR_EL3_VALID_RM0 ? 0 : \ + ((x) == INTR_EL3_VALID_RM1 ? 0 :\ + -EINVAL)) + +/******************************************************************************* + * Macros to set the 'flags' parameter passed to an interrupt type handler. Only + * the flag to indicate the security state when the exception was generated is + * supported. + ******************************************************************************/ +#define INTR_SRC_SS_FLAG_SHIFT 0 /* BIT[0] */ +#define INTR_SRC_SS_FLAG_MASK 1 +#define set_interrupt_src_ss(flag, val) (flag |= val << INTR_SRC_SS_FLAG_SHIFT) +#define clr_interrupt_src_ss(flag) (flag &= ~(1 << INTR_SRC_SS_FLAG_SHIFT)) +#define get_interrupt_src_ss(flag) ((flag >> INTR_SRC_SS_FLAG_SHIFT) & \ + INTR_SRC_SS_FLAG_MASK) + +#ifndef __ASSEMBLY__ + +/* Prototype for defining a handler for an interrupt type */ +typedef uint64_t (*interrupt_type_handler_t)(uint32_t id, + uint32_t flags, + void *handle, + void *cookie); + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +uint32_t get_scr_el3_from_routing_model(uint32_t security_state); +int32_t set_routing_model(uint32_t type, uint32_t flags); +int32_t register_interrupt_type_handler(uint32_t type, + interrupt_type_handler_t handler, + uint32_t flags); +interrupt_type_handler_t get_interrupt_type_handler(uint32_t interrupt_type); +int disable_intr_rm_local(uint32_t type, uint32_t security_state); +int enable_intr_rm_local(uint32_t type, uint32_t security_state); + +#endif /*__ASSEMBLY__*/ +#endif /* __INTERRUPT_MGMT_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl32/payloads/tlk.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl32/payloads/tlk.h new file mode 100644 index 0000000..6ce1eb6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl32/payloads/tlk.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TLK_H__ +#define __TLK_H__ + +/* + * Generate function IDs for the Trusted OS/Apps + */ +#define TLK_TOS_STD_FID(fid) ((fid) | 0x72000000 | (0 << 31)) +#define TLK_TA_STD_FID(fid) ((fid) | 0x70000000 | (0 << 31)) + +/* + * Trusted OS specific function IDs + */ +#define TLK_REGISTER_LOGBUF TLK_TOS_STD_FID(0x1) +#define TLK_REGISTER_REQBUF TLK_TOS_STD_FID(0x2) +#define TLK_RESUME_FID TLK_TOS_STD_FID(0x100) +#define TLK_SYSTEM_SUSPEND TLK_TOS_STD_FID(0xE001) +#define TLK_SYSTEM_RESUME TLK_TOS_STD_FID(0xE002) +#define TLK_SYSTEM_OFF TLK_TOS_STD_FID(0xE003) + +/* + * SMC function IDs that TLK uses to signal various forms of completions + * to the secure payload dispatcher. + */ +#define TLK_REQUEST_DONE (0x32000001 | (1 << 31)) +#define TLK_PREEMPTED (0x32000002 | (1 << 31)) +#define TLK_ENTRY_DONE (0x32000003 | (1 << 31)) +#define TLK_VA_TRANSLATE (0x32000004 | (1 << 31)) +#define TLK_SUSPEND_DONE (0x32000005 | (1 << 31)) +#define TLK_RESUME_DONE (0x32000006 | (1 << 31)) +#define TLK_SYSTEM_OFF_DONE (0x32000007 | (1 << 31)) + +/* + * Trusted Application specific function IDs + */ +#define TLK_OPEN_TA_SESSION TLK_TA_STD_FID(0x1) +#define TLK_CLOSE_TA_SESSION TLK_TA_STD_FID(0x2) +#define TLK_TA_LAUNCH_OP TLK_TA_STD_FID(0x3) +#define TLK_TA_SEND_EVENT TLK_TA_STD_FID(0x4) + +/* + * Total number of function IDs implemented for services offered to NS clients. + */ +#define TLK_NUM_FID 7 + +/* TLK implementation version numbers */ +#define TLK_VERSION_MAJOR 0x0 /* Major version */ +#define TLK_VERSION_MINOR 0x1 /* Minor version */ + +/* + * Standard Trusted OS Function IDs that fall under Trusted OS call range + * according to SMC calling convention + */ +#define TOS_CALL_COUNT 0xbf00ff00 /* Number of calls implemented */ +#define TOS_UID 0xbf00ff01 /* Implementation UID */ +#define TOS_CALL_VERSION 0xbf00ff03 /* Trusted OS Call Version */ + +#endif /* __TLK_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl32/sp_min/platform_sp_min.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl32/sp_min/platform_sp_min.h new file mode 100644 index 0000000..c8c3fc5 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl32/sp_min/platform_sp_min.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_SP_MIN_H__ +#define __PLATFORM_SP_MIN_H__ + +/******************************************************************************* + * Mandatory SP_MIN functions + ******************************************************************************/ +void sp_min_early_platform_setup(void *from_bl2, + void *plat_params_from_bl2); +void sp_min_plat_arch_setup(void); +void sp_min_platform_setup(void); +entry_point_info_t *sp_min_plat_get_bl33_ep_info(void); + +#endif /* __PLATFORM_SP_MIN_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl32/tsp/platform_tsp.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl32/tsp/platform_tsp.h new file mode 100644 index 0000000..f6f7391 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl32/tsp/platform_tsp.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_TSP_H__ + + +/******************************************************************************* + * Mandatory TSP functions (only if platform contains a TSP) + ******************************************************************************/ +void tsp_early_platform_setup(void); +void tsp_plat_arch_setup(void); +void tsp_platform_setup(void); + + +#define __PLATFORM_H__ + +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl32/tsp/tsp.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl32/tsp/tsp.h new file mode 100644 index 0000000..fd43fd3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/bl32/tsp/tsp.h @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TSP_H__ +#define __TSP_H__ + +/* + * SMC function IDs that TSP uses to signal various forms of completions + * to the secure payload dispatcher. + */ +#define TSP_ENTRY_DONE 0xf2000000 +#define TSP_ON_DONE 0xf2000001 +#define TSP_OFF_DONE 0xf2000002 +#define TSP_SUSPEND_DONE 0xf2000003 +#define TSP_RESUME_DONE 0xf2000004 +#define TSP_PREEMPTED 0xf2000005 +#define TSP_SYSTEM_OFF_DONE 0xf2000008 +#define TSP_SYSTEM_RESET_DONE 0xf2000009 + +/* + * Function identifiers to handle S-El1 interrupt through the synchronous + * handling model. If the TSP was previously interrupted then control has to + * be returned to the TSPD after handling the interrupt else execution can + * remain in the TSP. + */ +#define TSP_HANDLED_S_EL1_INTR 0xf2000006 + +/* SMC function ID that TSP uses to request service from secure monitor */ +#define TSP_GET_ARGS 0xf2001000 + +/* + * Identifiers for various TSP services. Corresponding function IDs (whether + * fast or standard) are generated by macros defined below + */ +#define TSP_ADD 0x2000 +#define TSP_SUB 0x2001 +#define TSP_MUL 0x2002 +#define TSP_DIV 0x2003 +#define TSP_HANDLE_SEL1_INTR_AND_RETURN 0x2004 + +/* + * Generate function IDs for TSP services to be used in SMC calls, by + * appropriately setting bit 31 to differentiate standard and fast SMC calls + */ +#define TSP_STD_FID(fid) ((fid) | 0x72000000 | (0 << 31)) +#define TSP_FAST_FID(fid) ((fid) | 0x72000000 | (1 << 31)) + +/* SMC function ID to request a previously preempted std smc */ +#define TSP_FID_RESUME TSP_STD_FID(0x3000) + +/* + * Identify a TSP service from function ID filtering the last 16 bits from the + * SMC function ID + */ +#define TSP_BARE_FID(fid) ((fid) & 0xffff) + +/* + * Total number of function IDs implemented for services offered to NS clients. + * The function IDs are defined above + */ +#define TSP_NUM_FID 0x4 + +/* TSP implementation version numbers */ +#define TSP_VERSION_MAJOR 0x0 /* Major version */ +#define TSP_VERSION_MINOR 0x1 /* Minor version */ + +/* + * Standard Trusted OS Function IDs that fall under Trusted OS call range + * according to SMC calling convention + */ +#define TOS_CALL_COUNT 0xbf00ff00 /* Number of calls implemented */ +#define TOS_UID 0xbf00ff01 /* Implementation UID */ +/* 0xbf00ff02 is reserved */ +#define TOS_CALL_VERSION 0xbf00ff03 /* Trusted OS Call Version */ + + +#ifndef __ASSEMBLY__ + +#include + + +typedef uint32_t tsp_vector_isn_t; + +typedef struct tsp_vectors { + tsp_vector_isn_t std_smc_entry; + tsp_vector_isn_t fast_smc_entry; + tsp_vector_isn_t cpu_on_entry; + tsp_vector_isn_t cpu_off_entry; + tsp_vector_isn_t cpu_resume_entry; + tsp_vector_isn_t cpu_suspend_entry; + tsp_vector_isn_t sel1_intr_entry; + tsp_vector_isn_t system_off_entry; + tsp_vector_isn_t system_reset_entry; +} tsp_vectors_t; + + +#endif /* __ASSEMBLY__ */ + +#endif /* __TSP_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch32/asm_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch32/asm_macros.S new file mode 100644 index 0000000..5f04499 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch32/asm_macros.S @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ASM_MACROS_S__ +#define __ASM_MACROS_S__ + +#include +#include + +#define WORD_SIZE 4 + + /* + * Co processor register accessors + */ + .macro ldcopr reg, coproc, opc1, CRn, CRm, opc2 + mrc \coproc, \opc1, \reg, \CRn, \CRm, \opc2 + .endm + + .macro ldcopr16 reg1, reg2, coproc, opc1, CRm + mrrc \coproc, \opc1, \reg1, \reg2, \CRm + .endm + + .macro stcopr reg, coproc, opc1, CRn, CRm, opc2 + mcr \coproc, \opc1, \reg, \CRn, \CRm, \opc2 + .endm + + .macro stcopr16 reg1, reg2, coproc, opc1, CRm + mcrr \coproc, \opc1, \reg1, \reg2, \CRm + .endm + + /* Cache line size helpers */ + .macro dcache_line_size reg, tmp + ldcopr \tmp, CTR + ubfx \tmp, \tmp, #CTR_DMINLINE_SHIFT, #CTR_DMINLINE_WIDTH + mov \reg, #WORD_SIZE + lsl \reg, \reg, \tmp + .endm + + .macro icache_line_size reg, tmp + ldcopr \tmp, CTR + and \tmp, \tmp, #CTR_IMINLINE_MASK + mov \reg, #WORD_SIZE + lsl \reg, \reg, \tmp + .endm + + /* + * Declare the exception vector table, enforcing it is aligned on a + * 32 byte boundary. + */ + .macro vector_base label + .section .vectors, "ax" + .align 5 + \label: + .endm + + /* + * This macro calculates the base address of the current CPU's multi + * processor(MP) stack using the plat_my_core_pos() index, the name of + * the stack storage and the size of each stack. + * Out: r0 = physical address of stack base + * Clobber: r14, r1, r2 + */ + .macro get_my_mp_stack _name, _size + bl plat_my_core_pos + ldr r2, =(\_name + \_size) + mov r1, #\_size + mla r0, r0, r1, r2 + .endm + + /* + * This macro calculates the base address of a uniprocessor(UP) stack + * using the name of the stack storage and the size of the stack + * Out: r0 = physical address of stack base + */ + .macro get_up_stack _name, _size + ldr r0, =(\_name + \_size) + .endm + +#endif /* __ASM_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch32/assert_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch32/assert_macros.S new file mode 100644 index 0000000..f35fc6a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch32/assert_macros.S @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ASSERT_MACROS_S__ +#define __ASSERT_MACROS_S__ + + /* + * Assembler macro to enable asm_assert. We assume that the stack is + * initialized prior to invoking this macro. + */ +#define ASM_ASSERT(_cc) \ +.ifndef .L_assert_filename ;\ + .pushsection .rodata.str1.1, "aS" ;\ + .L_assert_filename: ;\ + .string __FILE__ ;\ + .popsection ;\ +.endif ;\ + b##_cc 300f ;\ + ldr r0, =.L_assert_filename ;\ + mov r1, #__LINE__ ;\ + b . ;\ +300: + +#endif /* __ASSERT_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch32/el3_common_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch32/el3_common_macros.S new file mode 100644 index 0000000..50ce952 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch32/el3_common_macros.S @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __EL3_COMMON_MACROS_S__ +#define __EL3_COMMON_MACROS_S__ + +#include +#include +#include + + /* + * Helper macro to initialise EL3 registers we care about. + */ + .macro el3_arch_init_common _exception_vectors + /* --------------------------------------------------------------------- + * Enable the instruction cache and alignment checks + * --------------------------------------------------------------------- + */ + ldr r1, =(SCTLR_RES1 | SCTLR_I_BIT | SCTLR_A_BIT) + ldcopr r0, SCTLR + orr r0, r0, r1 + stcopr r0, SCTLR + isb + + /* --------------------------------------------------------------------- + * Set the exception vectors (VBAR/MVBAR). + * --------------------------------------------------------------------- + */ + ldr r0, =\_exception_vectors + stcopr r0, VBAR + stcopr r0, MVBAR + isb + + /* ----------------------------------------------------- + * Enable the SIF bit to disable instruction fetches + * from Non-secure memory. + * ----------------------------------------------------- + */ + ldcopr r0, SCR + orr r0, r0, #SCR_SIF_BIT + stcopr r0, SCR + + /* ----------------------------------------------------- + * Enable the Asynchronous data abort now that the + * exception vectors have been setup. + * ----------------------------------------------------- + */ + cpsie a + isb + + /* Enable access to Advanced SIMD registers */ + ldcopr r0, NSACR + bic r0, r0, #NSASEDIS_BIT + bic r0, r0, #NSTRCDIS_BIT + orr r0, r0, #(NASCR_CP10_BIT | NASCR_CP11_BIT) + stcopr r0, NSACR + isb + + /* + * Enable access to Advanced SIMD, Floating point and to the Trace + * functionality as well. + */ + ldcopr r0, CPACR + bic r0, r0, #ASEDIS_BIT + bic r0, r0, #TRCDIS_BIT + orr r0, r0, #CPACR_ENABLE_FP_ACCESS + stcopr r0, CPACR + isb + + vmrs r0, FPEXC + orr r0, r0, #FPEXC_EN_BIT + vmsr FPEXC, r0 + isb + .endm + +/* ----------------------------------------------------------------------------- + * This is the super set of actions that need to be performed during a cold boot + * or a warm boot in EL3. This code is shared by BL1 and BL32 (SP_MIN). + * + * This macro will always perform reset handling, architectural initialisations + * and stack setup. The rest of the actions are optional because they might not + * be needed, depending on the context in which this macro is called. This is + * why this macro is parameterised ; each parameter allows to enable/disable + * some actions. + * + * _set_endian: + * Whether the macro needs to configure the endianness of data accesses. + * + * _warm_boot_mailbox: + * Whether the macro needs to detect the type of boot (cold/warm). The + * detection is based on the platform entrypoint address : if it is zero + * then it is a cold boot, otherwise it is a warm boot. In the latter case, + * this macro jumps on the platform entrypoint address. + * + * _secondary_cold_boot: + * Whether the macro needs to identify the CPU that is calling it: primary + * CPU or secondary CPU. The primary CPU will be allowed to carry on with + * the platform initialisations, while the secondaries will be put in a + * platform-specific state in the meantime. + * + * If the caller knows this macro will only be called by the primary CPU + * then this parameter can be defined to 0 to skip this step. + * + * _init_memory: + * Whether the macro needs to initialise the memory. + * + * _init_c_runtime: + * Whether the macro needs to initialise the C runtime environment. + * + * _exception_vectors: + * Address of the exception vectors to program in the VBAR_EL3 register. + * ----------------------------------------------------------------------------- + */ + .macro el3_entrypoint_common \ + _set_endian, _warm_boot_mailbox, _secondary_cold_boot, \ + _init_memory, _init_c_runtime, _exception_vectors + + /* Make sure we are in Secure Mode */ +#if ASM_ASSERTION + ldcopr r0, SCR + tst r0, #SCR_NS_BIT + ASM_ASSERT(eq) +#endif + + .if \_set_endian + /* ------------------------------------------------------------- + * Set the CPU endianness before doing anything that might + * involve memory reads or writes. + * ------------------------------------------------------------- + */ + ldcopr r0, SCTLR + bic r0, r0, #SCTLR_EE_BIT + stcopr r0, SCTLR + isb + .endif /* _set_endian */ + + /* Switch to monitor mode */ + cps #MODE32_mon + isb + + .if \_warm_boot_mailbox + /* ------------------------------------------------------------- + * This code will be executed for both warm and cold resets. + * Now is the time to distinguish between the two. + * Query the platform entrypoint address and if it is not zero + * then it means it is a warm boot so jump to this address. + * ------------------------------------------------------------- + */ + bl plat_get_my_entrypoint + cmp r0, #0 + bxne r0 + .endif /* _warm_boot_mailbox */ + + /* --------------------------------------------------------------------- + * It is a cold boot. + * Perform any processor specific actions upon reset e.g. cache, TLB + * invalidations etc. + * --------------------------------------------------------------------- + */ + bl reset_handler + + el3_arch_init_common \_exception_vectors + + .if \_secondary_cold_boot + /* ------------------------------------------------------------- + * Check if this is a primary or secondary CPU cold boot. + * The primary CPU will set up the platform while the + * secondaries are placed in a platform-specific state until the + * primary CPU performs the necessary actions to bring them out + * of that state and allows entry into the OS. + * ------------------------------------------------------------- + */ + bl plat_is_my_cpu_primary + cmp r0, #0 + bne do_primary_cold_boot + + /* This is a cold boot on a secondary CPU */ + bl plat_secondary_cold_boot_setup + /* plat_secondary_cold_boot_setup() is not supposed to return */ + bl plat_panic_handler + + do_primary_cold_boot: + .endif /* _secondary_cold_boot */ + + /* --------------------------------------------------------------------- + * Initialize memory now. Secondary CPU initialization won't get to this + * point. + * --------------------------------------------------------------------- + */ + + .if \_init_memory + bl platform_mem_init + .endif /* _init_memory */ + + /* --------------------------------------------------------------------- + * Init C runtime environment: + * - Zero-initialise the NOBITS sections. There are 2 of them: + * - the .bss section; + * - the coherent memory section (if any). + * - Relocate the data section from ROM to RAM, if required. + * --------------------------------------------------------------------- + */ + .if \_init_c_runtime +#if IMAGE_BL32 + /* ----------------------------------------------------------------- + * Invalidate the RW memory used by the BL32 (SP_MIN) image. This + * includes the data and NOBITS sections. This is done to + * safeguard against possible corruption of this memory by + * dirty cache lines in a system cache as a result of use by + * an earlier boot loader stage. + * ----------------------------------------------------------------- + */ + ldr r0, =__RW_START__ + ldr r1, =__RW_END__ + sub r1, r1, r0 + bl inv_dcache_range +#endif /* IMAGE_BL32 */ + + ldr r0, =__BSS_START__ + ldr r1, =__BSS_SIZE__ + bl zeromem + +#if USE_COHERENT_MEM + ldr r0, =__COHERENT_RAM_START__ + ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ + bl zeromem +#endif + +#if IMAGE_BL1 + /* ----------------------------------------------------- + * Copy data from ROM to RAM. + * ----------------------------------------------------- + */ + ldr r0, =__DATA_RAM_START__ + ldr r1, =__DATA_ROM_START__ + ldr r2, =__DATA_SIZE__ + bl memcpy4 +#endif + .endif /* _init_c_runtime */ + + /* --------------------------------------------------------------------- + * Allocate a stack whose memory will be marked as Normal-IS-WBWA when + * the MMU is enabled. There is no risk of reading stale stack memory + * after enabling the MMU as only the primary CPU is running at the + * moment. + * --------------------------------------------------------------------- + */ + bl plat_set_my_stack + .endm + +#endif /* __EL3_COMMON_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch64/asm_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch64/asm_macros.S new file mode 100644 index 0000000..1d6212e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch64/asm_macros.S @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ASM_MACROS_S__ +#define __ASM_MACROS_S__ + +#include +#include + + + .macro func_prologue + stp x29, x30, [sp, #-0x10]! + mov x29,sp + .endm + + .macro func_epilogue + ldp x29, x30, [sp], #0x10 + .endm + + + .macro dcache_line_size reg, tmp + mrs \tmp, ctr_el0 + ubfx \tmp, \tmp, #16, #4 + mov \reg, #4 + lsl \reg, \reg, \tmp + .endm + + + .macro icache_line_size reg, tmp + mrs \tmp, ctr_el0 + and \tmp, \tmp, #0xf + mov \reg, #4 + lsl \reg, \reg, \tmp + .endm + + + .macro smc_check label + mrs x0, esr_el3 + ubfx x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH + cmp x0, #EC_AARCH64_SMC + b.ne $label + .endm + + /* + * Declare the exception vector table, enforcing it is aligned on a + * 2KB boundary, as required by the ARMv8 architecture. + * Use zero bytes as the fill value to be stored in the padding bytes + * so that it inserts illegal AArch64 instructions. This increases + * security, robustness and potentially facilitates debugging. + */ + .macro vector_base label + .section .vectors, "ax" +#if PLAT_rcar + .align 11 +#else + .align 11, 0 +#endif + \label: + .endm + + /* + * Create an entry in the exception vector table, enforcing it is + * aligned on a 128-byte boundary, as required by the ARMv8 architecture. + * Use zero bytes as the fill value to be stored in the padding bytes + * so that it inserts illegal AArch64 instructions. This increases + * security, robustness and potentially facilitates debugging. + */ + .macro vector_entry label + .section .vectors, "ax" +#if PLAT_rcar + .align 7 +#else + .align 7, 0 +#endif + \label: + .endm + + /* + * This macro verifies that the given vector doesn't exceed the + * architectural limit of 32 instructions. This is meant to be placed + * immediately after the last instruction in the vector. It takes the + * vector entry as the parameter + */ + .macro check_vector_size since + .if (. - \since) > (32 * 4) + .error "Vector exceeds 32 instructions" + .endif + .endm + +#if ENABLE_PLAT_COMPAT + /* + * This macro calculates the base address of an MP stack using the + * platform_get_core_pos() index, the name of the stack storage and + * the size of each stack + * In: X0 = MPIDR of CPU whose stack is wanted + * Out: X0 = physical address of stack base + * Clobber: X30, X1, X2 + */ + .macro get_mp_stack _name, _size + bl platform_get_core_pos + ldr x2, =(\_name + \_size) + mov x1, #\_size + madd x0, x0, x1, x2 + .endm +#endif + + /* + * This macro calculates the base address of the current CPU's MP stack + * using the plat_my_core_pos() index, the name of the stack storage + * and the size of each stack + * Out: X0 = physical address of stack base + * Clobber: X30, X1, X2 + */ + .macro get_my_mp_stack _name, _size + bl plat_my_core_pos + ldr x2, =(\_name + \_size) + mov x1, #\_size + madd x0, x0, x1, x2 + .endm + + /* + * This macro calculates the base address of a UP stack using the + * name of the stack storage and the size of the stack + * Out: X0 = physical address of stack base + */ + .macro get_up_stack _name, _size + ldr x0, =(\_name + \_size) + .endm + + /* + * Helper macro to generate the best mov/movk combinations according + * the value to be moved. The 16 bits from '_shift' are tested and + * if not zero, they are moved into '_reg' without affecting + * other bits. + */ + .macro _mov_imm16 _reg, _val, _shift + .if (\_val >> \_shift) & 0xffff + .if (\_val & (1 << \_shift - 1)) + movk \_reg, (\_val >> \_shift) & 0xffff, LSL \_shift + .else + mov \_reg, \_val & (0xffff << \_shift) + .endif + .endif + .endm + + /* + * Helper macro to load arbitrary values into 32 or 64-bit registers + * which generates the best mov/movk combinations. Many base addresses + * are 64KB aligned the macro will eliminate updating bits 15:0 in + * that case + */ + .macro mov_imm _reg, _val + .if (\_val) == 0 + mov \_reg, #0 + .else + _mov_imm16 \_reg, (\_val), 0 + _mov_imm16 \_reg, (\_val), 16 + _mov_imm16 \_reg, (\_val), 32 + _mov_imm16 \_reg, (\_val), 48 + .endif + .endm + +#endif /* __ASM_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch64/assert_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch64/assert_macros.S new file mode 100644 index 0000000..b7e536c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch64/assert_macros.S @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ASSERT_MACROS_S__ +#define __ASSERT_MACROS_S__ + + /* + * Assembler macro to enable asm_assert. Use this macro wherever + * assert is required in assembly. Please note that the macro makes + * use of label '300' to provide the logic and the caller + * should make sure that this label is not used to branch prior + * to calling this macro. + */ +#define ASM_ASSERT(_cc) \ +.ifndef .L_assert_filename ;\ + .pushsection .rodata.str1.1, "aS" ;\ + .L_assert_filename: ;\ + .string __FILE__ ;\ + .popsection ;\ +.endif ;\ + b._cc 300f ;\ + adr x0, .L_assert_filename ;\ + mov x1, __LINE__ ;\ + b asm_assert ;\ +300: + +#endif /* __ASSERT_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch64/el3_common_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch64/el3_common_macros.S new file mode 100644 index 0000000..9b22a73 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/aarch64/el3_common_macros.S @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __EL3_COMMON_MACROS_S__ +#define __EL3_COMMON_MACROS_S__ + +#include +#include + + /* + * Helper macro to initialise EL3 registers we care about. + */ + .macro el3_arch_init_common _exception_vectors + /* --------------------------------------------------------------------- + * Enable the instruction cache, stack pointer and data access alignment + * checks + * --------------------------------------------------------------------- + */ + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el3 + orr x0, x0, x1 + msr sctlr_el3, x0 + isb + +#if IMAGE_BL31 + /* --------------------------------------------------------------------- + * Initialise the per-cpu cache pointer to the CPU. + * This is done early to enable crash reporting to have access to crash + * stack. Since crash reporting depends on cpu_data to report the + * unhandled exception, not doing so can lead to recursive exceptions + * due to a NULL TPIDR_EL3. + * --------------------------------------------------------------------- + */ + bl init_cpu_data_ptr +#endif /* IMAGE_BL31 */ + + /* --------------------------------------------------------------------- + * Set the exception vectors. + * --------------------------------------------------------------------- + */ + adr x0, \_exception_vectors + msr vbar_el3, x0 + isb + + /* --------------------------------------------------------------------- + * Early set RES1 bits in SCR_EL3. Set EA bit to catch both + * External Aborts and SError Interrupts in EL3 and also the SIF bit + * to disable instruction fetches from Non-secure memory. + * --------------------------------------------------------------------- + */ + mov x0, #(SCR_RES1_BITS | SCR_EA_BIT | SCR_SIF_BIT) + msr scr_el3, x0 + /* --------------------------------------------------------------------- + * Enable External Aborts and SError Interrupts now that the exception + * vectors have been setup. + * --------------------------------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT + + /* --------------------------------------------------------------------- + * The initial state of the Architectural feature trap register + * (CPTR_EL3) is unknown and it must be set to a known state. All + * feature traps are disabled. Some bits in this register are marked as + * reserved and should not be modified. + * + * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 + * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. + * + * CPTR_EL3.TTA: This causes access to the Trace functionality to trap + * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register + * access to trace functionality is not supported, this bit is RES0. + * + * CPTR_EL3.TFP: This causes instructions that access the registers + * associated with Floating Point and Advanced SIMD execution to trap + * to EL3 when executed from any exception level, unless trapped to EL1 + * or EL2. + * --------------------------------------------------------------------- + */ + mrs x0, cptr_el3 + bic w0, w0, #TCPAC_BIT + bic w0, w0, #TTA_BIT + bic w0, w0, #TFP_BIT + msr cptr_el3, x0 + .endm + +/* ----------------------------------------------------------------------------- + * This is the super set of actions that need to be performed during a cold boot + * or a warm boot in EL3. This code is shared by BL1 and BL31. + * + * This macro will always perform reset handling, architectural initialisations + * and stack setup. The rest of the actions are optional because they might not + * be needed, depending on the context in which this macro is called. This is + * why this macro is parameterised ; each parameter allows to enable/disable + * some actions. + * + * _set_endian: + * Whether the macro needs to configure the endianness of data accesses. + * + * _warm_boot_mailbox: + * Whether the macro needs to detect the type of boot (cold/warm). The + * detection is based on the platform entrypoint address : if it is zero + * then it is a cold boot, otherwise it is a warm boot. In the latter case, + * this macro jumps on the platform entrypoint address. + * + * _secondary_cold_boot: + * Whether the macro needs to identify the CPU that is calling it: primary + * CPU or secondary CPU. The primary CPU will be allowed to carry on with + * the platform initialisations, while the secondaries will be put in a + * platform-specific state in the meantime. + * + * If the caller knows this macro will only be called by the primary CPU + * then this parameter can be defined to 0 to skip this step. + * + * _init_memory: + * Whether the macro needs to initialise the memory. + * + * _init_c_runtime: + * Whether the macro needs to initialise the C runtime environment. + * + * _exception_vectors: + * Address of the exception vectors to program in the VBAR_EL3 register. + * ----------------------------------------------------------------------------- + */ + .macro el3_entrypoint_common \ + _set_endian, _warm_boot_mailbox, _secondary_cold_boot, \ + _init_memory, _init_c_runtime, _exception_vectors + + .if \_set_endian + /* ------------------------------------------------------------- + * Set the CPU endianness before doing anything that might + * involve memory reads or writes. + * ------------------------------------------------------------- + */ + mrs x0, sctlr_el3 + bic x0, x0, #SCTLR_EE_BIT + msr sctlr_el3, x0 + isb + .endif /* _set_endian */ + + .if \_warm_boot_mailbox + /* ------------------------------------------------------------- + * This code will be executed for both warm and cold resets. + * Now is the time to distinguish between the two. + * Query the platform entrypoint address and if it is not zero + * then it means it is a warm boot so jump to this address. + * ------------------------------------------------------------- + */ + bl plat_get_my_entrypoint + cbz x0, do_cold_boot + br x0 + + do_cold_boot: + .endif /* _warm_boot_mailbox */ + + /* --------------------------------------------------------------------- + * It is a cold boot. + * Perform any processor specific actions upon reset e.g. cache, TLB + * invalidations etc. + * --------------------------------------------------------------------- + */ + bl reset_handler + + el3_arch_init_common \_exception_vectors + + .if \_secondary_cold_boot + /* ------------------------------------------------------------- + * Check if this is a primary or secondary CPU cold boot. + * The primary CPU will set up the platform while the + * secondaries are placed in a platform-specific state until the + * primary CPU performs the necessary actions to bring them out + * of that state and allows entry into the OS. + * ------------------------------------------------------------- + */ + bl plat_is_my_cpu_primary + cbnz w0, do_primary_cold_boot + + /* This is a cold boot on a secondary CPU */ + bl plat_secondary_cold_boot_setup + /* plat_secondary_cold_boot_setup() is not supposed to return */ + bl el3_panic + + do_primary_cold_boot: + .endif /* _secondary_cold_boot */ + + /* --------------------------------------------------------------------- + * Initialize memory now. Secondary CPU initialization won't get to this + * point. + * --------------------------------------------------------------------- + */ + + .if \_init_memory + bl platform_mem_init + .endif /* _init_memory */ + + /* --------------------------------------------------------------------- + * Init C runtime environment: + * - Zero-initialise the NOBITS sections. There are 2 of them: + * - the .bss section; + * - the coherent memory section (if any). + * - Relocate the data section from ROM to RAM, if required. + * --------------------------------------------------------------------- + */ + .if \_init_c_runtime +#if IMAGE_BL31 + /* ------------------------------------------------------------- + * Invalidate the RW memory used by the BL31 image. This + * includes the data and NOBITS sections. This is done to + * safeguard against possible corruption of this memory by + * dirty cache lines in a system cache as a result of use by + * an earlier boot loader stage. + * ------------------------------------------------------------- + */ + adr x0, __RW_START__ + adr x1, __RW_END__ + sub x1, x1, x0 + bl inv_dcache_range +#endif /* IMAGE_BL31 */ + + ldr x0, =__BSS_START__ + ldr x1, =__BSS_SIZE__ + bl zeromem16 + +#if USE_COHERENT_MEM + ldr x0, =__COHERENT_RAM_START__ + ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ + bl zeromem16 +#endif + +#if IMAGE_BL1 + ldr x0, =__DATA_RAM_START__ + ldr x1, =__DATA_ROM_START__ + ldr x2, =__DATA_SIZE__ + bl memcpy16 +#endif + .endif /* _init_c_runtime */ + + /* --------------------------------------------------------------------- + * Use SP_EL0 for the C runtime stack. + * --------------------------------------------------------------------- + */ + msr spsel, #0 + + /* --------------------------------------------------------------------- + * Allocate a stack whose memory will be marked as Normal-IS-WBWA when + * the MMU is enabled. There is no risk of reading stale stack memory + * after enabling the MMU as only the primary CPU is running at the + * moment. + * --------------------------------------------------------------------- + */ + bl plat_set_my_stack + .endm + +#endif /* __EL3_COMMON_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/asm_macros_common.S b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/asm_macros_common.S new file mode 100644 index 0000000..023124b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/asm_macros_common.S @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ASM_MACROS_COMMON_S__ +#define __ASM_MACROS_COMMON_S__ + + /* + * This macro is used to create a function label and place the + * code into a separate text section based on the function name + * to enable elimination of unused code during linking + */ + .macro func _name + .section .text.\_name, "ax" + .type \_name, %function + .func \_name + \_name: + .endm + + /* + * This macro is used to mark the end of a function. + */ + .macro endfunc _name + .endfunc + .size \_name, . - \_name + .endm + + /* + * Theses macros are used to create function labels for deprecated + * APIs. If ERROR_DEPRECATED is non zero, the callers of these APIs + * will fail to link and cause build failure. + */ +#if ERROR_DEPRECATED + .macro func_deprecated _name + func deprecated\_name + .endm + + .macro endfunc_deprecated _name + endfunc deprecated\_name + .endm +#else + .macro func_deprecated _name + func \_name + .endm + + .macro endfunc_deprecated _name + endfunc \_name + .endm +#endif + + /* + * Helper assembler macro to count trailing zeros. The output is + * populated in the `TZ_COUNT` symbol. + */ + .macro count_tz _value, _tz_count + .if \_value + count_tz "(\_value >> 1)", "(\_tz_count + 1)" + .else + .equ TZ_COUNT, (\_tz_count - 1) + .endif + .endm + + /* + * This macro declares an array of 1 or more stacks, properly + * aligned and in the requested section + */ +#define DEFAULT_STACK_ALIGN (1 << 6) /* In case the caller doesnt provide alignment */ + + .macro declare_stack _name, _section, _size, _count, _align=DEFAULT_STACK_ALIGN + count_tz \_align, 0 + .if (\_align - (1 << TZ_COUNT)) + .error "Incorrect stack alignment specified (Must be a power of 2)." + .endif + .if ((\_size & ((1 << TZ_COUNT) - 1)) <> 0) + .error "Stack size not correctly aligned" + .endif + .section \_section, "aw", %nobits + .align TZ_COUNT + \_name: + .space ((\_count) * (\_size)), 0 + .endm + + +#endif /* __ASM_MACROS_COMMON_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/bl_common.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/bl_common.h new file mode 100644 index 0000000..12d5036 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/bl_common.h @@ -0,0 +1,394 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BL_COMMON_H__ +#define __BL_COMMON_H__ + +#define SECURE 0x0 +#define NON_SECURE 0x1 +#define sec_state_is_valid(s) (((s) == SECURE) || ((s) == NON_SECURE)) + +#define UP 1 +#define DOWN 0 + +/******************************************************************************* + * Constants to identify the location of a memory region in a given memory + * layout. +******************************************************************************/ +#define TOP 0x1 +#define BOTTOM !TOP + +/******************************************************************************* + * Constants that allow assembler code to access members of and the + * 'entry_point_info' structure at their correct offsets. + ******************************************************************************/ +#define ENTRY_POINT_INFO_PC_OFFSET 0x08 +#ifdef AARCH32 +#define ENTRY_POINT_INFO_ARGS_OFFSET 0x10 +#else +#define ENTRY_POINT_INFO_ARGS_OFFSET 0x18 +#endif + +/* The following are used to set/get image attributes. */ +#define PARAM_EP_SECURITY_MASK (0x1) + +#define GET_SECURITY_STATE(x) (x & PARAM_EP_SECURITY_MASK) +#define SET_SECURITY_STATE(x, security) \ + ((x) = ((x) & ~PARAM_EP_SECURITY_MASK) | (security)) + + +/* + * The following are used for image state attributes. + * Image can only be in one of the following state. + */ +#define IMAGE_STATE_RESET 0 +#define IMAGE_STATE_COPIED 1 +#define IMAGE_STATE_COPYING 2 +#define IMAGE_STATE_AUTHENTICATED 3 +#define IMAGE_STATE_EXECUTED 4 +#define IMAGE_STATE_INTERRUPTED 5 + +#define EP_EE_MASK 0x2 +#define EP_EE_LITTLE 0x0 +#define EP_EE_BIG 0x2 +#define EP_GET_EE(x) (x & EP_EE_MASK) +#define EP_SET_EE(x, ee) ((x) = ((x) & ~EP_EE_MASK) | (ee)) + +#define EP_ST_MASK 0x4 +#define EP_ST_DISABLE 0x0 +#define EP_ST_ENABLE 0x4 +#define EP_GET_ST(x) (x & EP_ST_MASK) +#define EP_SET_ST(x, ee) ((x) = ((x) & ~EP_ST_MASK) | (ee)) + +#define EP_EXE_MASK 0x8 +#define NON_EXECUTABLE 0x0 +#define EXECUTABLE 0x8 +#define EP_GET_EXE(x) (x & EP_EXE_MASK) +#define EP_SET_EXE(x, ee) ((x) = ((x) & ~EP_EXE_MASK) | (ee)) + +#define EP_FIRST_EXE_MASK 0x10 +#define EP_FIRST_EXE 0x10 +#define EP_GET_FIRST_EXE(x) ((x) & EP_FIRST_EXE_MASK) +#define EP_SET_FIRST_EXE(x, ee) ((x) = ((x) & ~EP_FIRST_EXE_MASK) | (ee)) + +#define PARAM_EP 0x01 +#define PARAM_IMAGE_BINARY 0x02 +#define PARAM_BL31 0x03 +#define PARAM_BL_LOAD_INFO 0x04 +#define PARAM_BL_PARAMS 0x05 +#define PARAM_PSCI_LIB_ARGS 0x06 + +#define IMAGE_ATTRIB_SKIP_LOADING 0x02 +#define IMAGE_ATTRIB_PLAT_SETUP 0x04 + +#define VERSION_1 0x01 +#define VERSION_2 0x02 + +#define INVALID_IMAGE_ID (0xFFFFFFFF) + +#define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \ + (_p)->h.type = (uint8_t)(_type); \ + (_p)->h.version = (uint8_t)(_ver); \ + (_p)->h.size = (uint16_t)sizeof(*_p); \ + (_p)->h.attr = (uint32_t)(_attr) ; \ + } while (0) + +/* Following is used for populating structure members statically. */ +#define SET_STATIC_PARAM_HEAD(_p, _type, _ver, _p_type, _attr) \ + ._p.h.type = (uint8_t)(_type), \ + ._p.h.version = (uint8_t)(_ver), \ + ._p.h.size = (uint16_t)sizeof(_p_type), \ + ._p.h.attr = (uint32_t)(_attr) + + +/******************************************************************************* + * Constants to indicate type of exception to the common exception handler. + ******************************************************************************/ +#define SYNC_EXCEPTION_SP_EL0 0x0 +#define IRQ_SP_EL0 0x1 +#define FIQ_SP_EL0 0x2 +#define SERROR_SP_EL0 0x3 +#define SYNC_EXCEPTION_SP_ELX 0x4 +#define IRQ_SP_ELX 0x5 +#define FIQ_SP_ELX 0x6 +#define SERROR_SP_ELX 0x7 +#define SYNC_EXCEPTION_AARCH64 0x8 +#define IRQ_AARCH64 0x9 +#define FIQ_AARCH64 0xa +#define SERROR_AARCH64 0xb +#define SYNC_EXCEPTION_AARCH32 0xc +#define IRQ_AARCH32 0xd +#define FIQ_AARCH32 0xe +#define SERROR_AARCH32 0xf + +#ifndef __ASSEMBLY__ +#include /* For __dead2 */ +#include +#include +#include +#include +#include /* To retain compatibility */ + +/* + * Declarations of linker defined symbols to help determine memory layout of + * BL images + */ +#if SEPARATE_CODE_AND_RODATA +extern uintptr_t __TEXT_START__; +extern uintptr_t __TEXT_END__; +extern uintptr_t __RODATA_START__; +extern uintptr_t __RODATA_END__; +#else +extern uintptr_t __RO_START__; +extern uintptr_t __RO_END__; +#endif + +#if IMAGE_BL2 +extern uintptr_t __BL2_END__; +#elif IMAGE_BL2U +extern uintptr_t __BL2U_END__; +#elif IMAGE_BL31 +extern uintptr_t __BL31_END__; +#elif IMAGE_BL32 +extern uintptr_t __BL32_END__; +#endif /* IMAGE_BLX */ + +#if USE_COHERENT_MEM +extern uintptr_t __COHERENT_RAM_START__; +extern uintptr_t __COHERENT_RAM_END__; +#endif + + +/******************************************************************************* + * Structure used for telling the next BL how much of a particular type of + * memory is available for its use and how much is already used. + ******************************************************************************/ +typedef struct meminfo { + uintptr_t total_base; + size_t total_size; +#if !LOAD_IMAGE_V2 + uintptr_t free_base; + size_t free_size; +#endif +} meminfo_t; + +typedef struct aapcs64_params { + u_register_t arg0; + u_register_t arg1; + u_register_t arg2; + u_register_t arg3; + u_register_t arg4; + u_register_t arg5; + u_register_t arg6; + u_register_t arg7; +} aapcs64_params_t; + +typedef struct aapcs32_params { + u_register_t arg0; + u_register_t arg1; + u_register_t arg2; + u_register_t arg3; +} aapcs32_params_t; + +/*************************************************************************** + * This structure provides version information and the size of the + * structure, attributes for the structure it represents + ***************************************************************************/ +typedef struct param_header { + uint8_t type; /* type of the structure */ + uint8_t version; /* version of this structure */ + uint16_t size; /* size of this structure in bytes */ + uint32_t attr; /* attributes: unused bits SBZ */ +} param_header_t; + +/***************************************************************************** + * This structure represents the superset of information needed while + * switching exception levels. The only two mechanisms to do so are + * ERET & SMC. Security state is indicated using bit zero of header + * attribute + * NOTE: BL1 expects entrypoint followed by spsr at an offset from the start + * of this structure defined by the macro `ENTRY_POINT_INFO_PC_OFFSET` while + * processing SMC to jump to BL31. + *****************************************************************************/ +typedef struct entry_point_info { + param_header_t h; + uintptr_t pc; + uint32_t spsr; +#ifdef AARCH32 + aapcs32_params_t args; +#else + aapcs64_params_t args; +#endif +} entry_point_info_t; + +/***************************************************************************** + * Image info binary provides information from the image loader that + * can be used by the firmware to manage available trusted RAM. + * More advanced firmware image formats can provide additional + * information that enables optimization or greater flexibility in the + * common firmware code + *****************************************************************************/ +typedef struct image_info { + param_header_t h; + uintptr_t image_base; /* physical address of base of image */ + uint32_t image_size; /* bytes read from image file */ +#if LOAD_IMAGE_V2 + uint32_t image_max_size; +#endif +} image_info_t; + +/***************************************************************************** + * The image descriptor struct definition. + *****************************************************************************/ +typedef struct image_desc { + /* Contains unique image id for the image. */ + unsigned int image_id; + /* + * This member contains Image state information. + * Refer IMAGE_STATE_XXX defined above. + */ + unsigned int state; + uint32_t copied_size; /* image size copied in blocks */ + image_info_t image_info; + entry_point_info_t ep_info; +} image_desc_t; + +#if LOAD_IMAGE_V2 +/* BL image node in the BL image loading sequence */ +typedef struct bl_load_info_node { + unsigned int image_id; + image_info_t *image_info; + struct bl_load_info_node *next_load_info; +} bl_load_info_node_t; + +/* BL image head node in the BL image loading sequence */ +typedef struct bl_load_info { + param_header_t h; + bl_load_info_node_t *head; +} bl_load_info_t; + +/* BL image node in the BL image execution sequence */ +typedef struct bl_params_node { + unsigned int image_id; + image_info_t *image_info; + entry_point_info_t *ep_info; + struct bl_params_node *next_params_info; +} bl_params_node_t; + +/* + * BL image head node in the BL image execution sequence + * It is also used to pass information to next BL image. + */ +typedef struct bl_params { + param_header_t h; + bl_params_node_t *head; +} bl_params_t; + +#else /* LOAD_IMAGE_V2 */ + +/******************************************************************************* + * This structure represents the superset of information that can be passed to + * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be + * populated only if BL2 detects its presence. A pointer to a structure of this + * type should be passed in X0 to BL31's cold boot entrypoint. + * + * Use of this structure and the X0 parameter is not mandatory: the BL31 + * platform code can use other mechanisms to provide the necessary information + * about BL32 and BL33 to the common and SPD code. + * + * BL31 image information is mandatory if this structure is used. If either of + * the optional BL32 and BL33 image information is not provided, this is + * indicated by the respective image_info pointers being zero. + ******************************************************************************/ +typedef struct bl31_params { + param_header_t h; + image_info_t *bl31_image_info; + entry_point_info_t *bl32_ep_info; + image_info_t *bl32_image_info; + entry_point_info_t *bl33_ep_info; + image_info_t *bl33_image_info; +} bl31_params_t; + +#endif /* LOAD_IMAGE_V2 */ + +/* + * Compile time assertions related to the 'entry_point_info' structure to + * ensure that the assembler and the compiler view of the offsets of + * the structure members is the same. + */ +CASSERT(ENTRY_POINT_INFO_PC_OFFSET == + __builtin_offsetof(entry_point_info_t, pc), \ + assert_BL31_pc_offset_mismatch); + +CASSERT(ENTRY_POINT_INFO_ARGS_OFFSET == \ + __builtin_offsetof(entry_point_info_t, args), \ + assert_BL31_args_offset_mismatch); + +CASSERT(sizeof(uintptr_t) == + __builtin_offsetof(entry_point_info_t, spsr) - \ + __builtin_offsetof(entry_point_info_t, pc), \ + assert_entrypoint_and_spsr_should_be_adjacent); + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +size_t image_size(unsigned int image_id); + +#if LOAD_IMAGE_V2 + +int load_image(unsigned int image_id, image_info_t *image_data); +int load_auth_image(unsigned int image_id, image_info_t *image_data); + +#else + +uintptr_t page_align(uintptr_t, unsigned); +int load_image(meminfo_t *mem_layout, + unsigned int image_id, + uintptr_t image_base, + image_info_t *image_data, + entry_point_info_t *entry_point_info); +int load_auth_image(meminfo_t *mem_layout, + unsigned int image_id, + uintptr_t image_base, + image_info_t *image_data, + entry_point_info_t *entry_point_info); +void reserve_mem(uintptr_t *free_base, size_t *free_size, + uintptr_t addr, size_t size); + +#endif /* LOAD_IMAGE_V2 */ + +extern const char build_message[]; +extern const char version_string[]; + +void print_entry_point_info(const entry_point_info_t *ep_info); + +#endif /*__ASSEMBLY__*/ + +#endif /* __BL_COMMON_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/debug.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/debug.h new file mode 100644 index 0000000..41c8df0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/debug.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +/* The log output macros print output to the console. These macros produce + * compiled log output only if the LOG_LEVEL defined in the makefile (or the + * make command line) is greater or equal than the level required for that + * type of log output. + * The format expected is the same as for printf(). For example: + * INFO("Info %s.\n", "message") -> INFO: Info message. + * WARN("Warning %s.\n", "message") -> WARNING: Warning message. + */ + +#define LOG_LEVEL_NONE 0 +#define LOG_LEVEL_ERROR 10 +#define LOG_LEVEL_NOTICE 20 +#define LOG_LEVEL_WARNING 30 +#define LOG_LEVEL_INFO 40 +#define LOG_LEVEL_VERBOSE 50 + +#ifndef __ASSEMBLY__ +#include + +#if LOG_LEVEL >= LOG_LEVEL_NOTICE +# define NOTICE(...) tf_printf("NOTICE: " __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_ERROR +# define ERROR(...) tf_printf("ERROR: " __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_WARNING +# define WARN(...) tf_printf("WARNING: " __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_INFO +# define INFO(...) tf_printf("INFO: " __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE +# define VERBOSE(...) tf_printf("VERBOSE: " __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + + +void __dead2 do_panic(void); +#define panic() do_panic() + +void tf_printf(const char *fmt, ...) __printflike(1, 2); + +#endif /* __ASSEMBLY__ */ +#endif /* __DEBUG_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/desc_image_load.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/desc_image_load.h new file mode 100644 index 0000000..7834262 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/desc_image_load.h @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __DESC_IMAGE_LOAD_H__ +#define __DESC_IMAGE_LOAD_H__ + +#include + +#if LOAD_IMAGE_V2 +/* Following structure is used to store BL ep/image info. */ +typedef struct bl_mem_params_node { + unsigned int image_id; + image_info_t image_info; + entry_point_info_t ep_info; + unsigned int next_handoff_image_id; + bl_load_info_node_t load_node_mem; + bl_params_node_t params_node_mem; +} bl_mem_params_node_t; + +/* + * Macro to register list of BL image descriptors, + * defined as an array of bl_mem_params_node_t. + */ +#define REGISTER_BL_IMAGE_DESCS(_img_desc) \ + bl_mem_params_node_t *bl_mem_params_desc_ptr = &_img_desc[0]; \ + unsigned int bl_mem_params_desc_num = ARRAY_SIZE(_img_desc); + +/* BL image loading utility functions */ +void flush_bl_params_desc(void); +int get_bl_params_node_index(unsigned int image_id); +bl_mem_params_node_t *get_bl_mem_params_node(unsigned int image_id); +bl_load_info_t *get_bl_load_info_from_mem_params_desc(void); +bl_params_t *get_next_bl_params_from_mem_params_desc(void); + + +#endif /* LOAD_IMAGE_V2 */ +#endif /* __DESC_IMAGE_LOAD_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/firmware_image_package.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/firmware_image_package.h new file mode 100644 index 0000000..b972395 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/firmware_image_package.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FIRMWARE_IMAGE_PACKAGE_H__ +#define __FIRMWARE_IMAGE_PACKAGE_H__ + +#include +#include + +/* This is used as a signature to validate the blob header */ +#define TOC_HEADER_NAME 0xAA640001 + + +/* ToC Entry UUIDs */ +#define UUID_TRUSTED_UPDATE_FIRMWARE_SCP_BL2U \ + {0x03279265, 0x742f, 0x44e6, 0x8d, 0xff, {0x57, 0x9a, 0xc1, 0xff, 0x06, 0x10} } +#define UUID_TRUSTED_UPDATE_FIRMWARE_BL2U \ + {0x37ebb360, 0xe5c1, 0x41ea, 0x9d, 0xf3, {0x19, 0xed, 0xa1, 0x1f, 0x68, 0x01} } +#define UUID_TRUSTED_UPDATE_FIRMWARE_NS_BL2U \ + {0x111d514f, 0xe52b, 0x494e, 0xb4, 0xc5, {0x83, 0xc2, 0xf7, 0x15, 0x84, 0x0a} } +#define UUID_TRUSTED_FWU_CERT \ + {0xb28a4071, 0xd618, 0x4c87, 0x8b, 0x2e, {0xc6, 0xdc, 0xcd, 0x50, 0xf0, 0x96} } +#define UUID_TRUSTED_BOOT_FIRMWARE_BL2 \ + {0x0becf95f, 0x224d, 0x4d3e, 0xa5, 0x44, {0xc3, 0x9d, 0x81, 0xc7, 0x3f, 0x0a} } +#define UUID_SCP_FIRMWARE_SCP_BL2 \ + {0x3dfd6697, 0xbe89, 0x49e8, 0xae, 0x5d, {0x78, 0xa1, 0x40, 0x60, 0x82, 0x13} } +#define UUID_EL3_RUNTIME_FIRMWARE_BL31 \ + {0x6d08d447, 0xfe4c, 0x4698, 0x9b, 0x95, {0x29, 0x50, 0xcb, 0xbd, 0x5a, 0x00} } +#define UUID_SECURE_PAYLOAD_BL32 \ + {0x89e1d005, 0xdc53, 0x4713, 0x8d, 0x2b, {0x50, 0x0a, 0x4b, 0x7a, 0x3e, 0x38} } +#define UUID_NON_TRUSTED_FIRMWARE_BL33 \ + {0xa7eed0d6, 0xeafc, 0x4bd5, 0x97, 0x82, {0x99, 0x34, 0xf2, 0x34, 0xb6, 0xe4} } +/* Key certificates */ +#define UUID_ROT_KEY_CERT \ + {0x721d2d86, 0x60f8, 0x11e4, 0x92, 0x0b, {0x8b, 0xe7, 0x62, 0x16, 0x0f, 0x24} } +#define UUID_TRUSTED_KEY_CERT \ + {0x90e87e82, 0x60f8, 0x11e4, 0xa1, 0xb4, {0x77, 0x7a, 0x21, 0xb4, 0xf9, 0x4c} } +#define UUID_NON_TRUSTED_WORLD_KEY_CERT \ + {0x3d87671c, 0x635f, 0x11e4, 0x97, 0x8d, {0x27, 0xc0, 0xc7, 0x14, 0x8a, 0xbd} } +#define UUID_SCP_FW_KEY_CERT \ + {0xa1214202, 0x60f8, 0x11e4, 0x8d, 0x9b, {0xf3, 0x3c, 0x0e, 0x15, 0xa0, 0x14} } +#define UUID_SOC_FW_KEY_CERT \ + {0xccbeb88a, 0x60f9, 0x11e4, 0x9a, 0xd0, {0xeb, 0x48, 0x22, 0xd8, 0xdc, 0xf8} } +#define UUID_TRUSTED_OS_FW_KEY_CERT \ + {0x03d67794, 0x60fb, 0x11e4, 0x85, 0xdd, {0xb7, 0x10, 0x5b, 0x8c, 0xee, 0x04} } +#define UUID_NON_TRUSTED_FW_KEY_CERT \ + {0x2a83d58a, 0x60fb, 0x11e4, 0x8a, 0xaf, {0xdf, 0x30, 0xbb, 0xc4, 0x98, 0x59} } +/* Content certificates */ +#define UUID_TRUSTED_BOOT_FW_CERT \ + {0xea69e2d6, 0x635d, 0x11e4, 0x8d, 0x8c, {0x9f, 0xba, 0xbe, 0x99, 0x56, 0xa5} } +#define UUID_SCP_FW_CONTENT_CERT \ + {0x046fbe44, 0x635e, 0x11e4, 0xb2, 0x8b, {0x73, 0xd8, 0xea, 0xae, 0x96, 0x56} } +#define UUID_SOC_FW_CONTENT_CERT \ + {0x200cb2e2, 0x635e, 0x11e4, 0x9c, 0xe8, {0xab, 0xcc, 0xf9, 0x2b, 0xb6, 0x66} } +#define UUID_TRUSTED_OS_FW_CONTENT_CERT \ + {0x11449fa4, 0x635e, 0x11e4, 0x87, 0x28, {0x3f, 0x05, 0x72, 0x2a, 0xf3, 0x3d} } +#define UUID_NON_TRUSTED_FW_CONTENT_CERT \ + {0xf3c1c48e, 0x635d, 0x11e4, 0xa7, 0xa9, {0x87, 0xee, 0x40, 0xb2, 0x3f, 0xa7} } + +typedef struct fip_toc_header { + uint32_t name; + uint32_t serial_number; + uint64_t flags; +} fip_toc_header_t; + +typedef struct fip_toc_entry { + uuid_t uuid; + uint64_t offset_address; + uint64_t size; + uint64_t flags; +} fip_toc_entry_t; + +#endif /* __FIRMWARE_IMAGE_PACKAGE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/runtime_svc.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/runtime_svc.h new file mode 100644 index 0000000..514f334 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/runtime_svc.h @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __RUNTIME_SVC_H__ +#define __RUNTIME_SVC_H__ + +#include /* to include exception types */ +#include /* to include SMCC definitions */ + + +/******************************************************************************* + * Structure definition, typedefs & constants for the runtime service framework + ******************************************************************************/ + +/* + * Constants to allow the assembler access a runtime service + * descriptor + */ +#ifdef AARCH32 +#define RT_SVC_SIZE_LOG2 4 +#define RT_SVC_DESC_INIT 8 +#define RT_SVC_DESC_HANDLE 12 +#else +#define RT_SVC_SIZE_LOG2 5 +#define RT_SVC_DESC_INIT 16 +#define RT_SVC_DESC_HANDLE 24 +#endif /* AARCH32 */ +#define SIZEOF_RT_SVC_DESC (1 << RT_SVC_SIZE_LOG2) + + +/* + * The function identifier has 6 bits for the owning entity number and + * single bit for the type of smc call. When taken together these + * values limit the maximum number of runtime services to 128. + */ +#define MAX_RT_SVCS 128 + +#ifndef __ASSEMBLY__ + +/* Prototype for runtime service initializing function */ +typedef int32_t (*rt_svc_init_t)(void); + +/* + * Prototype for runtime service SMC handler function. x0 (SMC Function ID) to + * x4 are as passed by the caller. Rest of the arguments to SMC and the context + * can be accessed using the handle pointer. The cookie parameter is reserved + * for future use + */ +typedef uintptr_t (*rt_svc_handle_t)(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags); +typedef struct rt_svc_desc { + uint8_t start_oen; + uint8_t end_oen; + uint8_t call_type; + const char *name; + rt_svc_init_t init; + rt_svc_handle_t handle; +} rt_svc_desc_t; + +/* + * Convenience macro to declare a service descriptor + */ +#define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch) \ + static const rt_svc_desc_t __svc_desc_ ## _name \ + __section("rt_svc_descs") __used = { \ + .start_oen = _start, \ + .end_oen = _end, \ + .call_type = _type, \ + .name = #_name, \ + .init = _setup, \ + .handle = _smch } + +/* + * Compile time assertions related to the 'rt_svc_desc' structure to: + * 1. ensure that the assembler and the compiler view of the size + * of the structure are the same. + * 2. ensure that the assembler and the compiler see the initialisation + * routine at the same offset. + * 3. ensure that the assembler and the compiler see the handler + * routine at the same offset. + */ +CASSERT((sizeof(rt_svc_desc_t) == SIZEOF_RT_SVC_DESC), \ + assert_sizeof_rt_svc_desc_mismatch); +CASSERT(RT_SVC_DESC_INIT == __builtin_offsetof(rt_svc_desc_t, init), \ + assert_rt_svc_desc_init_offset_mismatch); +CASSERT(RT_SVC_DESC_HANDLE == __builtin_offsetof(rt_svc_desc_t, handle), \ + assert_rt_svc_desc_handle_offset_mismatch); + + +/* + * This macro combines the call type and the owning entity number corresponding + * to a runtime service to generate a unique owning entity number. This unique + * oen is used to access an entry in the 'rt_svc_descs_indices' array. The entry + * contains the index of the service descriptor in the 'rt_svc_descs' array. + */ +#define get_unique_oen(oen, call_type) ((oen & FUNCID_OEN_MASK) | \ + ((call_type & FUNCID_TYPE_MASK) \ + << FUNCID_OEN_WIDTH)) + +/* + * This macro generates the unique owning entity number from the SMC Function + * ID. This unique oen is used to access an entry in the + * 'rt_svc_descs_indices' array to invoke the corresponding runtime service + * handler during SMC handling. + */ +#define get_unique_oen_from_smc_fid(fid) \ + get_unique_oen(((fid) >> FUNCID_OEN_SHIFT), \ + ((fid) >> FUNCID_TYPE_SHIFT)) + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void runtime_svc_init(void); +uintptr_t handle_runtime_svc(uint32_t smc_fid, void *cookie, void *handle, + unsigned int flags); +extern uintptr_t __RT_SVC_DESCS_START__; +extern uintptr_t __RT_SVC_DESCS_END__; +void init_crash_reporting(void); + +#endif /*__ASSEMBLY__*/ +#endif /* __RUNTIME_SVC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/tbbr/cot_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/tbbr/cot_def.h new file mode 100644 index 0000000..d6dca4a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/tbbr/cot_def.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __COT_DEF_H__ +#define __COT_DEF_H__ + +/* TBBR CoT definitions */ + +#define COT_MAX_VERIFIED_PARAMS 4 + +#endif /* __COT_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/tbbr/tbbr_img_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/tbbr/tbbr_img_def.h new file mode 100644 index 0000000..ad10e2e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/common/tbbr/tbbr_img_def.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TBBR_IMG_DEF_H__ +#define __TBBR_IMG_DEF_H__ + +/* Firmware Image Package */ +#define FIP_IMAGE_ID 0 + +/* Trusted Boot Firmware BL2 */ +#define BL2_IMAGE_ID 1 + +/* SCP Firmware SCP_BL2 */ +#define SCP_BL2_IMAGE_ID 2 + +/* EL3 Runtime Firmware BL31 */ +#define BL31_IMAGE_ID 3 + +/* Secure Payload BL32 (Trusted OS) */ +#define BL32_IMAGE_ID 4 + +/* Non-Trusted Firmware BL33 */ +#define BL33_IMAGE_ID 5 + +/* Certificates */ +#define TRUSTED_BOOT_FW_CERT_ID 6 +#define TRUSTED_KEY_CERT_ID 7 + +#define SCP_FW_KEY_CERT_ID 8 +#define SOC_FW_KEY_CERT_ID 9 +#define TRUSTED_OS_FW_KEY_CERT_ID 10 +#define NON_TRUSTED_FW_KEY_CERT_ID 11 + +#define SCP_FW_CONTENT_CERT_ID 12 +#define SOC_FW_CONTENT_CERT_ID 13 +#define TRUSTED_OS_FW_CONTENT_CERT_ID 14 +#define NON_TRUSTED_FW_CONTENT_CERT_ID 15 + +/* Non-Trusted ROM Firmware NS_BL1U */ +#define NS_BL1U_IMAGE_ID 16 + +/* Trusted FWU Certificate */ +#define FWU_CERT_ID 17 + +/* Trusted FWU SCP Firmware SCP_BL2U */ +#define SCP_BL2U_IMAGE_ID 18 + +/* Trusted FWU Boot Firmware BL2U */ +#define BL2U_IMAGE_ID 19 + +/* Non-Trusted FWU Firmware NS_BL2U */ +#define NS_BL2U_IMAGE_ID 20 + +#endif /* __TBBR_IMG_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/arm_gic.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/arm_gic.h new file mode 100644 index 0000000..37ff5c9 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/arm_gic.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARM_GIC_H__ +#define __ARM_GIC_H__ + +#include + +/******************************************************************************* + * Function declarations + ******************************************************************************/ +void arm_gic_init(uintptr_t gicc_base, + uintptr_t gicd_base, + uintptr_t gicr_base, + const unsigned int *irq_sec_ptr, + unsigned int num_irqs) __deprecated; +void arm_gic_setup(void) __deprecated; +void arm_gic_cpuif_deactivate(void) __deprecated; +void arm_gic_cpuif_setup(void) __deprecated; +void arm_gic_pcpu_distif_setup(void) __deprecated; + +uint32_t arm_gic_interrupt_type_to_line(uint32_t type, + uint32_t security_state) __deprecated; +uint32_t arm_gic_get_pending_interrupt_type(void) __deprecated; +uint32_t arm_gic_get_pending_interrupt_id(void) __deprecated; +uint32_t arm_gic_acknowledge_interrupt(void) __deprecated; +void arm_gic_end_of_interrupt(uint32_t id) __deprecated; +uint32_t arm_gic_get_interrupt_type(uint32_t id) __deprecated; + +#endif /* __GIC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/cci.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/cci.h new file mode 100644 index 0000000..1145f91 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/cci.h @@ -0,0 +1,157 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCI_H__ +#define __CCI_H__ + +/* Slave interface offsets from PERIPHBASE */ +#define SLAVE_IFACE6_OFFSET 0x7000 +#define SLAVE_IFACE5_OFFSET 0x6000 +#define SLAVE_IFACE4_OFFSET 0x5000 +#define SLAVE_IFACE3_OFFSET 0x4000 +#define SLAVE_IFACE2_OFFSET 0x3000 +#define SLAVE_IFACE1_OFFSET 0x2000 +#define SLAVE_IFACE0_OFFSET 0x1000 +#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \ + (0x1000 * (index))) + +/* Slave interface event and count register offsets from PERIPHBASE */ +#define EVENT_SELECT7_OFFSET 0x80000 +#define EVENT_SELECT6_OFFSET 0x70000 +#define EVENT_SELECT5_OFFSET 0x60000 +#define EVENT_SELECT4_OFFSET 0x50000 +#define EVENT_SELECT3_OFFSET 0x40000 +#define EVENT_SELECT2_OFFSET 0x30000 +#define EVENT_SELECT1_OFFSET 0x20000 +#define EVENT_SELECT0_OFFSET 0x10000 +#define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \ + (0x10000 * (index))) + +/* Control and ID register offsets */ +#define CTRL_OVERRIDE_REG 0x0 +#define SECURE_ACCESS_REG 0x8 +#define STATUS_REG 0xc +#define IMPRECISE_ERR_REG 0x10 +#define PERFMON_CTRL_REG 0x100 +#define IFACE_MON_CTRL_REG 0x104 + +/* Component and peripheral ID registers */ +#define PERIPHERAL_ID0 0xFE0 +#define PERIPHERAL_ID1 0xFE4 +#define PERIPHERAL_ID2 0xFE8 +#define PERIPHERAL_ID3 0xFEC +#define PERIPHERAL_ID4 0xFD0 +#define PERIPHERAL_ID5 0xFD4 +#define PERIPHERAL_ID6 0xFD8 +#define PERIPHERAL_ID7 0xFDC + +#define COMPONENT_ID0 0xFF0 +#define COMPONENT_ID1 0xFF4 +#define COMPONENT_ID2 0xFF8 +#define COMPONENT_ID3 0xFFC +#define COMPONENT_ID4 0x1000 +#define COMPONENT_ID5 0x1004 +#define COMPONENT_ID6 0x1008 +#define COMPONENT_ID7 0x100C + +/* Slave interface register offsets */ +#define SNOOP_CTRL_REG 0x0 +#define SH_OVERRIDE_REG 0x4 +#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100 +#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104 +#define MAX_OT_REG 0x110 + +/* Snoop Control register bit definitions */ +#define DVM_EN_BIT (1 << 1) +#define SNOOP_EN_BIT (1 << 0) +#define SUPPORT_SNOOPS (1 << 30) +#define SUPPORT_DVM (1 << 31) + +/* Status register bit definitions */ +#define CHANGE_PENDING_BIT (1 << 0) + +/* Event and count register offsets */ +#define EVENT_SELECT_REG 0x0 +#define EVENT_COUNT_REG 0x4 +#define COUNT_CNTRL_REG 0x8 +#define COUNT_OVERFLOW_REG 0xC + +/* Slave interface monitor registers */ +#define INT_MON_REG_SI0 0x90000 +#define INT_MON_REG_SI1 0x90004 +#define INT_MON_REG_SI2 0x90008 +#define INT_MON_REG_SI3 0x9000C +#define INT_MON_REG_SI4 0x90010 +#define INT_MON_REG_SI5 0x90014 +#define INT_MON_REG_SI6 0x90018 + +/* Master interface monitor registers */ +#define INT_MON_REG_MI0 0x90100 +#define INT_MON_REG_MI1 0x90104 +#define INT_MON_REG_MI2 0x90108 +#define INT_MON_REG_MI3 0x9010c +#define INT_MON_REG_MI4 0x90110 +#define INT_MON_REG_MI5 0x90114 + +#define SLAVE_IF_UNUSED -1 + +#if ARM_CCI_PRODUCT_ID == 400 + #define CCI_SLAVE_INTERFACE_COUNT 5 +#elif ARM_CCI_PRODUCT_ID == 500 + #define CCI_SLAVE_INTERFACE_COUNT 7 +#else + #error "Invalid CCI product or CCI not supported" +#endif + +#ifndef __ASSEMBLY__ + +#include + +/* Function declarations */ + +/* + * The ARM CCI driver needs the following: + * 1. Base address of the CCI-500/CCI-400 + * 2. An array of map between AMBA 4 master ids and ACE/ACE lite slave + * interfaces. + * 3. Size of the array. + * + * SLAVE_IF_UNUSED should be used in the map to represent no AMBA 4 master exists + * for that interface. + */ +void cci_init(uintptr_t cci_base, + const int *map, + unsigned int num_cci_masters); + +void cci_enable_snoop_dvm_reqs(unsigned int master_id); +void cci_disable_snoop_dvm_reqs(unsigned int master_id); + +#endif /* __ASSEMBLY__ */ +#endif /* __CCI_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/cci400.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/cci400.h new file mode 100644 index 0000000..bfadc8f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/cci400.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCI_400_H__ +#define __CCI_400_H__ + +/************************************************************** + * THIS DRIVER IS DEPRECATED. Please use the driver in cci.h + **************************************************************/ +#if ERROR_DEPRECATED +#error " The CCI-400 specific driver is deprecated." +#endif + + +/* Slave interface offsets from PERIPHBASE */ +#define SLAVE_IFACE4_OFFSET 0x5000 +#define SLAVE_IFACE3_OFFSET 0x4000 +#define SLAVE_IFACE2_OFFSET 0x3000 +#define SLAVE_IFACE1_OFFSET 0x2000 +#define SLAVE_IFACE0_OFFSET 0x1000 +#define SLAVE_IFACE_OFFSET(index) SLAVE_IFACE0_OFFSET + \ + (0x1000 * (index)) + +/* Control and ID register offsets */ +#define CTRL_OVERRIDE_REG 0x0 +#define SPEC_CTRL_REG 0x4 +#define SECURE_ACCESS_REG 0x8 +#define STATUS_REG 0xc +#define IMPRECISE_ERR_REG 0x10 +#define PERFMON_CTRL_REG 0x100 + +/* Slave interface register offsets */ +#define SNOOP_CTRL_REG 0x0 +#define SH_OVERRIDE_REG 0x4 +#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100 +#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104 +#define QOS_CTRL_REG 0x10c +#define MAX_OT_REG 0x110 +#define TARGET_LATENCY_REG 0x130 +#define LATENCY_REGULATION_REG 0x134 +#define QOS_RANGE_REG 0x138 + +/* Snoop Control register bit definitions */ +#define DVM_EN_BIT (1 << 1) +#define SNOOP_EN_BIT (1 << 0) + +/* Status register bit definitions */ +#define CHANGE_PENDING_BIT (1 << 0) + +#ifndef __ASSEMBLY__ + +#include + +/* Function declarations */ + +/* + * The CCI-400 driver must be initialized with the base address of the + * CCI-400 device in the platform memory map, and the cluster indices for + * the CCI-400 slave interfaces 3 and 4 respectively. These are the fully + * coherent ACE slave interfaces of CCI-400. + * The cluster indices must either be 0 or 1, corresponding to the level 1 + * affinity instance of the mpidr representing the cluster. A negative cluster + * index indicates that no cluster is present on that slave interface. + */ +void cci_init(uintptr_t cci_base, + int slave_iface3_cluster_ix, + int slave_iface4_cluster_ix) __deprecated; + +void cci_enable_cluster_coherency(unsigned long mpidr) __deprecated; +void cci_disable_cluster_coherency(unsigned long mpidr) __deprecated; + +#endif /* __ASSEMBLY__ */ +#endif /* __CCI_400_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/ccn.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/ccn.h new file mode 100644 index 0000000..85c45c6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/ccn.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCN_H__ +#define __CCN_H__ + +/* + * This macro defines the maximum number of master interfaces that reside on + * Request nodes which the CCN driver can accommodate. The driver APIs to add + * and remove Request nodes from snoop/dvm domains take a bit map of master + * interfaces as inputs. The largest C data type that can be used is a 64-bit + * unsigned integer. Hence the value of 64. The platform will have to ensure + * that the master interfaces are numbered from 0-63. + */ +#define CCN_MAX_RN_MASTERS 64 + +/* + * The following constants define the various run modes that the platform can + * request the CCN driver to place the L3 cache in. These map to the + * programmable P-State values in a HN-F P-state register. + */ +#define CCN_L3_RUN_MODE_NOL3 0x0 /* HNF_PM_NOL3 */ +#define CCN_L3_RUN_MODE_SFONLY 0x1 /* HNF_PM_SFONLY */ +#define CCN_L3_RUN_MODE_HAM 0x2 /* HNF_PM_HALF */ +#define CCN_L3_RUN_MODE_FAM 0x3 /* HNF_PM_FULL */ + +/* part 0 IDs for various CCN variants */ +#define CCN_502_PART0_ID 0x30 +#define CCN_504_PART0_ID 0x26 +#define CCN_505_PART0_ID 0x27 +#define CCN_508_PART0_ID 0x28 +#define CCN_512_PART0_ID 0x29 + +/* + * The following macro takes the value returned from a read of a HN-F P-state + * status register and returns the retention state value. + */ +#define CCN_GET_RETENTION_STATE(pstate) ((pstate >> 4) & 0x3) + +/* + * The following macro takes the value returned from a read of a HN-F P-state + * status register and returns the run state value. + */ +#define CCN_GET_RUN_STATE(pstate) (pstate & 0xf) + +#ifndef __ASSEMBLY__ +#include + +/* + * This structure describes some of the implementation defined attributes of the + * CCN IP. It is used by the platform port to specify these attributes in order + * to initialise the CCN driver. The attributes are described below. + * + * 1. The 'num_masters' field specifies the total number of master interfaces + * resident on Request nodes. + * + * 2. The 'master_to_rn_id_map' field is a ponter to an array in which each + * index corresponds to a master interface and its value corresponds to the + * Request node on which the master interface resides. + * This field is not simply defined as an array of size CCN_MAX_RN_MASTERS. + * In reality, a platform will have much fewer master * interfaces than + * CCN_MAX_RN_MASTERS. With an array of this size, it would also have to + * set the unused entries to a suitable value. Zeroing the array would not + * be enough since 0 is also a valid node id. Hence, such an array is not + * used. + * + * 3. The 'periphbase' field is the base address of the programmer's view of the + * CCN IP. + */ +typedef struct ccn_desc { + unsigned int num_masters; + const unsigned char *master_to_rn_id_map; + uintptr_t periphbase; +} ccn_desc_t; + + +void ccn_init(const ccn_desc_t *plat_ccn_desc); +void ccn_enter_snoop_dvm_domain(unsigned long long master_iface_map); +void ccn_exit_snoop_dvm_domain(unsigned long long master_iface_map); +void ccn_enter_dvm_domain(unsigned long long master_iface_map); +void ccn_exit_dvm_domain(unsigned long long master_iface_map); +void ccn_set_l3_run_mode(unsigned int mode); +void ccn_program_sys_addrmap(unsigned int sn0_id, + unsigned int sn1_id, + unsigned int sn2_id, + unsigned int top_addr_bit0, + unsigned int top_addr_bit1, + unsigned char three_sn_en); +unsigned int ccn_get_l3_run_mode(void); +int ccn_get_part0_id(uintptr_t periphbase); + +#endif /* __ASSEMBLY__ */ +#endif /* __CCN_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gic_common.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gic_common.h new file mode 100644 index 0000000..dd8efdc --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gic_common.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GIC_COMMON_H__ +#define __GIC_COMMON_H__ + +/******************************************************************************* + * GIC Distributor interface general definitions + ******************************************************************************/ +/* Constants to categorise interrupts */ +#define MIN_SGI_ID 0 +#define MIN_PPI_ID 16 +#define MIN_SPI_ID 32 + +/* Mask for the priority field common to all GIC interfaces */ +#define GIC_PRI_MASK 0xff + +/* Constant to indicate a spurious interrupt in all GIC versions */ +#define GIC_SPURIOUS_INTERRUPT 1023 + +/* Constants to categorise priorities */ +#define GIC_HIGHEST_SEC_PRIORITY 0 +#define GIC_LOWEST_SEC_PRIORITY 127 +#define GIC_HIGHEST_NS_PRIORITY 128 +#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ + +/******************************************************************************* + * GIC Distributor interface register offsets that are common to GICv3 & GICv2 + ******************************************************************************/ +#define GICD_CTLR 0x0 +#define GICD_TYPER 0x4 +#define GICD_IIDR 0x8 +#define GICD_IGROUPR 0x80 +#define GICD_ISENABLER 0x100 +#define GICD_ICENABLER 0x180 +#define GICD_ISPENDR 0x200 +#define GICD_ICPENDR 0x280 +#define GICD_ISACTIVER 0x300 +#define GICD_ICACTIVER 0x380 +#define GICD_IPRIORITYR 0x400 +#define GICD_ICFGR 0xc00 +#define GICD_NSACR 0xe00 + +/* GICD_CTLR bit definitions */ +#define CTLR_ENABLE_G0_SHIFT 0 +#define CTLR_ENABLE_G0_MASK 0x1 +#define CTLR_ENABLE_G0_BIT (1 << CTLR_ENABLE_G0_SHIFT) + + +/******************************************************************************* + * GIC Distributor interface register constants that are common to GICv3 & GICv2 + ******************************************************************************/ +#define PIDR2_ARCH_REV_SHIFT 4 +#define PIDR2_ARCH_REV_MASK 0xf + +/* GICv3 revision as reported by the PIDR2 register */ +#define ARCH_REV_GICV3 0x3 +/* GICv2 revision as reported by the PIDR2 register */ +#define ARCH_REV_GICV2 0x2 + +#define IGROUPR_SHIFT 5 +#define ISENABLER_SHIFT 5 +#define ICENABLER_SHIFT ISENABLER_SHIFT +#define ISPENDR_SHIFT 5 +#define ICPENDR_SHIFT ISPENDR_SHIFT +#define ISACTIVER_SHIFT 5 +#define ICACTIVER_SHIFT ISACTIVER_SHIFT +#define IPRIORITYR_SHIFT 2 +#define ICFGR_SHIFT 4 +#define NSACR_SHIFT 4 + +/* GICD_TYPER shifts and masks */ +#define TYPER_IT_LINES_NO_SHIFT 0 +#define TYPER_IT_LINES_NO_MASK 0x1f + +/* Value used to initialize Normal world interrupt priorities four at a time */ +#define GICD_IPRIORITYR_DEF_VAL \ + (GIC_HIGHEST_NS_PRIORITY | \ + (GIC_HIGHEST_NS_PRIORITY << 8) | \ + (GIC_HIGHEST_NS_PRIORITY << 16) | \ + (GIC_HIGHEST_NS_PRIORITY << 24)) + +#endif /* __GIC_COMMON_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gic_v2.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gic_v2.h new file mode 100644 index 0000000..594ce49 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gic_v2.h @@ -0,0 +1,331 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GIC_V2_H__ +#define __GIC_V2_H__ + +/****************************************************************************** + * THIS DRIVER IS DEPRECATED. For GICv2 systems, use the driver in gicv2.h + * and for GICv3 systems, use the driver in gicv3.h. + *****************************************************************************/ +#if ERROR_DEPRECATED +#error " The legacy ARM GIC driver is deprecated." +#endif + +#define GIC400_NUM_SPIS 480 +#define MAX_PPIS 14 +#define MAX_SGIS 16 + +#define MIN_SGI_ID 0 +#define MIN_PPI_ID 16 +#define MIN_SPI_ID 32 + +#define GRP0 0 +#define GRP1 1 +#define GIC_PRI_MASK 0xff +#define GIC_HIGHEST_SEC_PRIORITY 0 +#define GIC_LOWEST_SEC_PRIORITY 127 +#define GIC_HIGHEST_NS_PRIORITY 128 +#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ +#define GIC_SPURIOUS_INTERRUPT 1023 +#define GIC_TARGET_CPU_MASK 0xff + +#define ENABLE_GRP0 (1 << 0) +#define ENABLE_GRP1 (1 << 1) + +/* Distributor interface definitions */ +#define GICD_CTLR 0x0 +#define GICD_TYPER 0x4 +#define GICD_IGROUPR 0x80 +#define GICD_ISENABLER 0x100 +#define GICD_ICENABLER 0x180 +#define GICD_ISPENDR 0x200 +#define GICD_ICPENDR 0x280 +#define GICD_ISACTIVER 0x300 +#define GICD_ICACTIVER 0x380 +#define GICD_IPRIORITYR 0x400 +#define GICD_ITARGETSR 0x800 +#define GICD_ICFGR 0xC00 +#define GICD_SGIR 0xF00 +#define GICD_CPENDSGIR 0xF10 +#define GICD_SPENDSGIR 0xF20 + +#define IGROUPR_SHIFT 5 +#define ISENABLER_SHIFT 5 +#define ICENABLER_SHIFT ISENABLER_SHIFT +#define ISPENDR_SHIFT 5 +#define ICPENDR_SHIFT ISPENDR_SHIFT +#define ISACTIVER_SHIFT 5 +#define ICACTIVER_SHIFT ISACTIVER_SHIFT +#define IPRIORITYR_SHIFT 2 +#define ITARGETSR_SHIFT 2 +#define ICFGR_SHIFT 4 +#define CPENDSGIR_SHIFT 2 +#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT + +/* GICD_TYPER bit definitions */ +#define IT_LINES_NO_MASK 0x1f + +/* Physical CPU Interface registers */ +#define GICC_CTLR 0x0 +#define GICC_PMR 0x4 +#define GICC_BPR 0x8 +#define GICC_IAR 0xC +#define GICC_EOIR 0x10 +#define GICC_RPR 0x14 +#define GICC_HPPIR 0x18 +#define GICC_AHPPIR 0x28 +#define GICC_IIDR 0xFC +#define GICC_DIR 0x1000 +#define GICC_PRIODROP GICC_EOIR + +/* Common CPU Interface definitions */ +#define INT_ID_MASK 0x3ff + +/* GICC_CTLR bit definitions */ +#define EOI_MODE_NS (1 << 10) +#define EOI_MODE_S (1 << 9) +#define IRQ_BYP_DIS_GRP1 (1 << 8) +#define FIQ_BYP_DIS_GRP1 (1 << 7) +#define IRQ_BYP_DIS_GRP0 (1 << 6) +#define FIQ_BYP_DIS_GRP0 (1 << 5) +#define CBPR (1 << 4) +#define FIQ_EN (1 << 3) +#define ACK_CTL (1 << 2) + +/* GICC_IIDR bit masks and shifts */ +#define GICC_IIDR_PID_SHIFT 20 +#define GICC_IIDR_ARCH_SHIFT 16 +#define GICC_IIDR_REV_SHIFT 12 +#define GICC_IIDR_IMP_SHIFT 0 + +#define GICC_IIDR_PID_MASK 0xfff +#define GICC_IIDR_ARCH_MASK 0xf +#define GICC_IIDR_REV_MASK 0xf +#define GICC_IIDR_IMP_MASK 0xfff + +/* HYP view virtual CPU Interface registers */ +#define GICH_CTL 0x0 +#define GICH_VTR 0x4 +#define GICH_ELRSR0 0x30 +#define GICH_ELRSR1 0x34 +#define GICH_APR0 0xF0 +#define GICH_LR_BASE 0x100 + +/* Virtual CPU Interface registers */ +#define GICV_CTL 0x0 +#define GICV_PRIMASK 0x4 +#define GICV_BP 0x8 +#define GICV_INTACK 0xC +#define GICV_EOI 0x10 +#define GICV_RUNNINGPRI 0x14 +#define GICV_HIGHESTPEND 0x18 +#define GICV_DEACTIVATE 0x1000 + +#ifndef __ASSEMBLY__ + +#include +#include + +/******************************************************************************* + * GIC Distributor function prototypes + ******************************************************************************/ + +unsigned int gicd_read_igroupr(uintptr_t, unsigned int); +unsigned int gicd_read_isenabler(uintptr_t, unsigned int); +unsigned int gicd_read_icenabler(uintptr_t, unsigned int); +unsigned int gicd_read_ispendr(uintptr_t, unsigned int); +unsigned int gicd_read_icpendr(uintptr_t, unsigned int); +unsigned int gicd_read_isactiver(uintptr_t, unsigned int); +unsigned int gicd_read_icactiver(uintptr_t, unsigned int); +unsigned int gicd_read_ipriorityr(uintptr_t, unsigned int); +unsigned int gicd_read_itargetsr(uintptr_t, unsigned int); +unsigned int gicd_read_icfgr(uintptr_t, unsigned int); +unsigned int gicd_read_cpendsgir(uintptr_t, unsigned int); +unsigned int gicd_read_spendsgir(uintptr_t, unsigned int); +void gicd_write_igroupr(uintptr_t, unsigned int, unsigned int); +void gicd_write_isenabler(uintptr_t, unsigned int, unsigned int); +void gicd_write_icenabler(uintptr_t, unsigned int, unsigned int); +void gicd_write_ispendr(uintptr_t, unsigned int, unsigned int); +void gicd_write_icpendr(uintptr_t, unsigned int, unsigned int); +void gicd_write_isactiver(uintptr_t, unsigned int, unsigned int); +void gicd_write_icactiver(uintptr_t, unsigned int, unsigned int); +void gicd_write_ipriorityr(uintptr_t, unsigned int, unsigned int); +void gicd_write_itargetsr(uintptr_t, unsigned int, unsigned int); +void gicd_write_icfgr(uintptr_t, unsigned int, unsigned int); +void gicd_write_cpendsgir(uintptr_t, unsigned int, unsigned int); +void gicd_write_spendsgir(uintptr_t, unsigned int, unsigned int); +unsigned int gicd_get_igroupr(uintptr_t, unsigned int); +void gicd_set_igroupr(uintptr_t, unsigned int); +void gicd_clr_igroupr(uintptr_t, unsigned int); +void gicd_set_isenabler(uintptr_t, unsigned int); +void gicd_set_icenabler(uintptr_t, unsigned int); +void gicd_set_ispendr(uintptr_t, unsigned int); +void gicd_set_icpendr(uintptr_t, unsigned int); +void gicd_set_isactiver(uintptr_t, unsigned int); +void gicd_set_icactiver(uintptr_t, unsigned int); +void gicd_set_ipriorityr(uintptr_t, unsigned int, unsigned int); +void gicd_set_itargetsr(uintptr_t, unsigned int, unsigned int); + + +/******************************************************************************* + * GIC Distributor interface accessors for reading entire registers + ******************************************************************************/ + +static inline unsigned int gicd_read_ctlr(uintptr_t base) +{ + return mmio_read_32(base + GICD_CTLR); +} + +static inline unsigned int gicd_read_typer(uintptr_t base) +{ + return mmio_read_32(base + GICD_TYPER); +} + +static inline unsigned int gicd_read_sgir(uintptr_t base) +{ + return mmio_read_32(base + GICD_SGIR); +} + + +/******************************************************************************* + * GIC Distributor interface accessors for writing entire registers + ******************************************************************************/ + +static inline void gicd_write_ctlr(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICD_CTLR, val); +} + +static inline void gicd_write_sgir(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICD_SGIR, val); +} + + +/******************************************************************************* + * GIC CPU interface accessors for reading entire registers + ******************************************************************************/ + +static inline unsigned int gicc_read_ctlr(uintptr_t base) +{ + return mmio_read_32(base + GICC_CTLR); +} + +static inline unsigned int gicc_read_pmr(uintptr_t base) +{ + return mmio_read_32(base + GICC_PMR); +} + +static inline unsigned int gicc_read_BPR(uintptr_t base) +{ + return mmio_read_32(base + GICC_BPR); +} + +static inline unsigned int gicc_read_IAR(uintptr_t base) +{ + return mmio_read_32(base + GICC_IAR); +} + +static inline unsigned int gicc_read_EOIR(uintptr_t base) +{ + return mmio_read_32(base + GICC_EOIR); +} + +static inline unsigned int gicc_read_hppir(uintptr_t base) +{ + return mmio_read_32(base + GICC_HPPIR); +} + +static inline unsigned int gicc_read_ahppir(uintptr_t base) +{ + return mmio_read_32(base + GICC_AHPPIR); +} + +static inline unsigned int gicc_read_dir(uintptr_t base) +{ + return mmio_read_32(base + GICC_DIR); +} + +static inline unsigned int gicc_read_iidr(uintptr_t base) +{ + return mmio_read_32(base + GICC_IIDR); +} + + +/******************************************************************************* + * GIC CPU interface accessors for writing entire registers + ******************************************************************************/ + +static inline void gicc_write_ctlr(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_CTLR, val); +} + +static inline void gicc_write_pmr(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_PMR, val); +} + +static inline void gicc_write_BPR(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_BPR, val); +} + + +static inline void gicc_write_IAR(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_IAR, val); +} + +static inline void gicc_write_EOIR(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_EOIR, val); +} + +static inline void gicc_write_hppir(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_HPPIR, val); +} + +static inline void gicc_write_dir(uintptr_t base, unsigned int val) +{ + mmio_write_32(base + GICC_DIR, val); +} + +/******************************************************************************* + * Prototype of function to map an interrupt type to the interrupt line used to + * signal it. + ******************************************************************************/ +uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type); + +#endif /*__ASSEMBLY__*/ + +#endif /* __GIC_V2_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gic_v3.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gic_v3.h new file mode 100644 index 0000000..c5360ff --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gic_v3.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GIC_V3_H__ +#define __GIC_V3_H__ + +/****************************************************************************** + * THIS DRIVER IS DEPRECATED. For GICv2 systems, use the driver in gicv2.h + * and for GICv3 systems, use the driver in gicv3.h. + *****************************************************************************/ +#if ERROR_DEPRECATED +#error " The legacy ARM GIC driver is deprecated." +#endif + +#include +#include +#include + + +/* GICv3 Re-distributor interface registers & shifts */ +#define GICR_PCPUBASE_SHIFT 0x11 +#define GICR_TYPER 0x08 +#define GICR_WAKER 0x14 + +/* GICR_WAKER bit definitions */ +#define WAKER_CA (1UL << 2) +#define WAKER_PS (1UL << 1) + +/* GICR_TYPER bit definitions */ +#define GICR_TYPER_AFF_SHIFT 32 +#define GICR_TYPER_AFF_MASK 0xffffffff +#define GICR_TYPER_LAST (1UL << 4) + +/* GICv3 ICC_SRE register bit definitions*/ +#define ICC_SRE_EN (1UL << 3) +#define ICC_SRE_SRE (1UL << 0) + +/******************************************************************************* + * GICv3 defintions + ******************************************************************************/ +#define GICV3_AFFLVL_MASK 0xff +#define GICV3_AFF0_SHIFT 0 +#define GICV3_AFF1_SHIFT 8 +#define GICV3_AFF2_SHIFT 16 +#define GICV3_AFF3_SHIFT 24 +#define GICV3_AFFINITY_MASK 0xffffffff + +/******************************************************************************* + * Function prototypes + ******************************************************************************/ +uintptr_t gicv3_get_rdist(uintptr_t gicr_base, u_register_t mpidr); + +/******************************************************************************* + * GIC Redistributor interface accessors + ******************************************************************************/ +static inline uint32_t gicr_read_waker(uintptr_t base) +{ + return mmio_read_32(base + GICR_WAKER); +} + +static inline void gicr_write_waker(uintptr_t base, uint32_t val) +{ + mmio_write_32(base + GICR_WAKER, val); +} + +static inline uint64_t gicr_read_typer(uintptr_t base) +{ + return mmio_read_64(base + GICR_TYPER); +} + + +#endif /* __GIC_V3_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gicv2.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gicv2.h new file mode 100644 index 0000000..88dc015 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gicv2.h @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GICV2_H__ +#define __GICV2_H__ + +/******************************************************************************* + * GICv2 miscellaneous definitions + ******************************************************************************/ +/* Interrupt IDs reported by the HPPIR and IAR registers */ +#define PENDING_G1_INTID 1022 + +/******************************************************************************* + * GICv2 specific Distributor interface register offsets and constants. + ******************************************************************************/ +#define GICD_ITARGETSR 0x800 +#define GICD_SGIR 0xF00 +#define GICD_CPENDSGIR 0xF10 +#define GICD_SPENDSGIR 0xF20 +#define GICD_PIDR2_GICV2 0xFE8 + +#define ITARGETSR_SHIFT 2 +#define GIC_TARGET_CPU_MASK 0xff + +#define CPENDSGIR_SHIFT 2 +#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT + +/******************************************************************************* + * GICv2 specific CPU interface register offsets and constants. + ******************************************************************************/ +/* Physical CPU Interface registers */ +#define GICC_CTLR 0x0 +#define GICC_PMR 0x4 +#define GICC_BPR 0x8 +#define GICC_IAR 0xC +#define GICC_EOIR 0x10 +#define GICC_RPR 0x14 +#define GICC_HPPIR 0x18 +#define GICC_AHPPIR 0x28 +#define GICC_IIDR 0xFC +#define GICC_DIR 0x1000 +#define GICC_PRIODROP GICC_EOIR + +/* GICC_CTLR bit definitions */ +#define EOI_MODE_NS (1 << 10) +#define EOI_MODE_S (1 << 9) +#define IRQ_BYP_DIS_GRP1 (1 << 8) +#define FIQ_BYP_DIS_GRP1 (1 << 7) +#define IRQ_BYP_DIS_GRP0 (1 << 6) +#define FIQ_BYP_DIS_GRP0 (1 << 5) +#define CBPR (1 << 4) +#define FIQ_EN_SHIFT 3 +#define FIQ_EN_BIT (1 << FIQ_EN_SHIFT) +#define ACK_CTL (1 << 2) + +/* GICC_IIDR bit masks and shifts */ +#define GICC_IIDR_PID_SHIFT 20 +#define GICC_IIDR_ARCH_SHIFT 16 +#define GICC_IIDR_REV_SHIFT 12 +#define GICC_IIDR_IMP_SHIFT 0 + +#define GICC_IIDR_PID_MASK 0xfff +#define GICC_IIDR_ARCH_MASK 0xf +#define GICC_IIDR_REV_MASK 0xf +#define GICC_IIDR_IMP_MASK 0xfff + +/* HYP view virtual CPU Interface registers */ +#define GICH_CTL 0x0 +#define GICH_VTR 0x4 +#define GICH_ELRSR0 0x30 +#define GICH_ELRSR1 0x34 +#define GICH_APR0 0xF0 +#define GICH_LR_BASE 0x100 + +/* Virtual CPU Interface registers */ +#define GICV_CTL 0x0 +#define GICV_PRIMASK 0x4 +#define GICV_BP 0x8 +#define GICV_INTACK 0xC +#define GICV_EOI 0x10 +#define GICV_RUNNINGPRI 0x14 +#define GICV_HIGHESTPEND 0x18 +#define GICV_DEACTIVATE 0x1000 + +/* GICD_CTLR bit definitions */ +#define CTLR_ENABLE_G1_SHIFT 1 +#define CTLR_ENABLE_G1_MASK 0x1 +#define CTLR_ENABLE_G1_BIT (1 << CTLR_ENABLE_G1_SHIFT) + +/* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ +#define INT_ID_MASK 0x3ff + +#ifndef __ASSEMBLY__ + +#include + +/******************************************************************************* + * This structure describes some of the implementation defined attributes of + * the GICv2 IP. It is used by the platform port to specify these attributes + * in order to initialize the GICv2 driver. The attributes are described + * below. + * + * 1. The 'gicd_base' field contains the base address of the Distributor + * interface programmer's view. + * + * 2. The 'gicc_base' field contains the base address of the CPU Interface + * programmer's view. + * + * 3. The 'g0_interrupt_array' field is a pointer to an array in which each + * entry corresponds to an ID of a Group 0 interrupt. + * + * 4. The 'g0_interrupt_num' field contains the number of entries in the + * 'g0_interrupt_array'. + ******************************************************************************/ +typedef struct gicv2_driver_data { + uintptr_t gicd_base; + uintptr_t gicc_base; + unsigned int g0_interrupt_num; + const unsigned int *g0_interrupt_array; +} gicv2_driver_data_t; + +/******************************************************************************* + * Function prototypes + ******************************************************************************/ +void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data); +void gicv2_distif_init(void); +void gicv2_pcpu_distif_init(void); +void gicv2_cpuif_enable(void); +void gicv2_cpuif_disable(void); +unsigned int gicv2_is_fiq_enabled(void); +unsigned int gicv2_get_pending_interrupt_type(void); +unsigned int gicv2_get_pending_interrupt_id(void); +unsigned int gicv2_acknowledge_interrupt(void); +void gicv2_end_of_interrupt(unsigned int id); +unsigned int gicv2_get_interrupt_group(unsigned int id); + +#endif /* __ASSEMBLY__ */ +#endif /* __GICV2_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gicv3.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gicv3.h new file mode 100644 index 0000000..b7ad778 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/gicv3.h @@ -0,0 +1,271 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GICV3_H__ +#define __GICV3_H__ + +/******************************************************************************* + * GICv3 miscellaneous definitions + ******************************************************************************/ +/* Interrupt group definitions */ +#define INTR_GROUP1S 0 +#define INTR_GROUP0 1 +#define INTR_GROUP1NS 2 + +/* Interrupt IDs reported by the HPPIR and IAR registers */ +#define PENDING_G1S_INTID 1020 +#define PENDING_G1NS_INTID 1021 + +/* Constant to categorize LPI interrupt */ +#define MIN_LPI_ID 8192 + +/******************************************************************************* + * GICv3 specific Distributor interface register offsets and constants. + ******************************************************************************/ +#define GICD_STATUSR 0x10 +#define GICD_SETSPI_NSR 0x40 +#define GICD_CLRSPI_NSR 0x48 +#define GICD_SETSPI_SR 0x50 +#define GICD_CLRSPI_SR 0x50 +#define GICD_IGRPMODR 0xd00 +/* + * GICD_IROUTER register is at 0x6000 + 8n, where n is the interrupt id and + * n >= 32, making the effective offset as 0x6100. + */ +#define GICD_IROUTER 0x6000 +#define GICD_PIDR2_GICV3 0xffe8 + +#define IGRPMODR_SHIFT 5 + +/* GICD_CTLR bit definitions */ +#define CTLR_ENABLE_G1NS_SHIFT 1 +#define CTLR_ENABLE_G1S_SHIFT 2 +#define CTLR_ARE_S_SHIFT 4 +#define CTLR_ARE_NS_SHIFT 5 +#define CTLR_DS_SHIFT 6 +#define CTLR_E1NWF_SHIFT 7 +#define GICD_CTLR_RWP_SHIFT 31 + +#define CTLR_ENABLE_G1NS_MASK 0x1 +#define CTLR_ENABLE_G1S_MASK 0x1 +#define CTLR_ARE_S_MASK 0x1 +#define CTLR_ARE_NS_MASK 0x1 +#define CTLR_DS_MASK 0x1 +#define CTLR_E1NWF_MASK 0x1 +#define GICD_CTLR_RWP_MASK 0x1 + +#define CTLR_ENABLE_G1NS_BIT (1 << CTLR_ENABLE_G1NS_SHIFT) +#define CTLR_ENABLE_G1S_BIT (1 << CTLR_ENABLE_G1S_SHIFT) +#define CTLR_ARE_S_BIT (1 << CTLR_ARE_S_SHIFT) +#define CTLR_ARE_NS_BIT (1 << CTLR_ARE_NS_SHIFT) +#define CTLR_DS_BIT (1 << CTLR_DS_SHIFT) +#define CTLR_E1NWF_BIT (1 << CTLR_E1NWF_SHIFT) +#define GICD_CTLR_RWP_BIT (1 << GICD_CTLR_RWP_SHIFT) + +/* GICD_IROUTER shifts and masks */ +#define IROUTER_IRM_SHIFT 31 +#define IROUTER_IRM_MASK 0x1 + +/******************************************************************************* + * GICv3 Re-distributor interface registers & constants + ******************************************************************************/ +#define GICR_PCPUBASE_SHIFT 0x11 +#define GICR_SGIBASE_OFFSET (1 << 0x10) /* 64 KB */ +#define GICR_CTLR 0x0 +#define GICR_TYPER 0x08 +#define GICR_WAKER 0x14 +#define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + 0x80) +#define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + 0x100) +#define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + 0x180) +#define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + 0x400) +#define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + 0xc00) +#define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + 0xc04) +#define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + 0xd00) + +/* GICR_CTLR bit definitions */ +#define GICR_CTLR_RWP_SHIFT 3 +#define GICR_CTLR_RWP_MASK 0x1 +#define GICR_CTLR_RWP_BIT (1 << GICR_CTLR_RWP_SHIFT) + +/* GICR_WAKER bit definitions */ +#define WAKER_CA_SHIFT 2 +#define WAKER_PS_SHIFT 1 + +#define WAKER_CA_MASK 0x1 +#define WAKER_PS_MASK 0x1 + +#define WAKER_CA_BIT (1 << WAKER_CA_SHIFT) +#define WAKER_PS_BIT (1 << WAKER_PS_SHIFT) + +/* GICR_TYPER bit definitions */ +#define TYPER_AFF_VAL_SHIFT 32 +#define TYPER_PROC_NUM_SHIFT 8 +#define TYPER_LAST_SHIFT 4 + +#define TYPER_AFF_VAL_MASK 0xffffffff +#define TYPER_PROC_NUM_MASK 0xffff +#define TYPER_LAST_MASK 0x1 + +#define TYPER_LAST_BIT (1 << TYPER_LAST_SHIFT) + +/******************************************************************************* + * GICv3 CPU interface registers & constants + ******************************************************************************/ +/* ICC_SRE bit definitions*/ +#define ICC_SRE_EN_BIT (1 << 3) +#define ICC_SRE_DIB_BIT (1 << 2) +#define ICC_SRE_DFB_BIT (1 << 1) +#define ICC_SRE_SRE_BIT (1 << 0) + +/* ICC_IGRPEN1_EL3 bit definitions */ +#define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0 +#define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1 + +#define IGRPEN1_EL3_ENABLE_G1NS_BIT (1 << IGRPEN1_EL3_ENABLE_G1NS_SHIFT) +#define IGRPEN1_EL3_ENABLE_G1S_BIT (1 << IGRPEN1_EL3_ENABLE_G1S_SHIFT) + +/* ICC_IGRPEN0_EL1 bit definitions */ +#define IGRPEN1_EL1_ENABLE_G0_SHIFT 0 +#define IGRPEN1_EL1_ENABLE_G0_BIT (1 << IGRPEN1_EL1_ENABLE_G0_SHIFT) + +/* ICC_HPPIR0_EL1 bit definitions */ +#define HPPIR0_EL1_INTID_SHIFT 0 +#define HPPIR0_EL1_INTID_MASK 0xffffff + +/* ICC_HPPIR1_EL1 bit definitions */ +#define HPPIR1_EL1_INTID_SHIFT 0 +#define HPPIR1_EL1_INTID_MASK 0xffffff + +/* ICC_IAR0_EL1 bit definitions */ +#define IAR0_EL1_INTID_SHIFT 0 +#define IAR0_EL1_INTID_MASK 0xffffff + +/* ICC_IAR1_EL1 bit definitions */ +#define IAR1_EL1_INTID_SHIFT 0 +#define IAR1_EL1_INTID_MASK 0xffffff + +#ifndef __ASSEMBLY__ + +#include +#include + +#define gicv3_is_intr_id_special_identifier(id) \ + (((id) >= PENDING_G1S_INTID) && ((id) <= GIC_SPURIOUS_INTERRUPT)) + +/******************************************************************************* + * Helper GICv3 macros for SEL1 + ******************************************************************************/ +#define gicv3_acknowledge_interrupt_sel1() read_icc_iar1_el1() &\ + IAR1_EL1_INTID_MASK +#define gicv3_get_pending_interrupt_id_sel1() read_icc_hppir1_el1() &\ + HPPIR1_EL1_INTID_MASK +#define gicv3_end_of_interrupt_sel1(id) write_icc_eoir1_el1(id) + + +/******************************************************************************* + * Helper GICv3 macros for EL3 + ******************************************************************************/ +#define gicv3_acknowledge_interrupt() read_icc_iar0_el1() &\ + IAR0_EL1_INTID_MASK +#define gicv3_end_of_interrupt(id) write_icc_eoir0_el1(id) + +/******************************************************************************* + * This structure describes some of the implementation defined attributes of the + * GICv3 IP. It is used by the platform port to specify these attributes in order + * to initialise the GICV3 driver. The attributes are described below. + * + * 1. The 'gicd_base' field contains the base address of the Distributor + * interface programmer's view. + * + * 2. The 'gicr_base' field contains the base address of the Re-distributor + * interface programmer's view. + * + * 3. The 'g0_interrupt_array' field is a ponter to an array in which each + * entry corresponds to an ID of a Group 0 interrupt. + * + * 4. The 'g0_interrupt_num' field contains the number of entries in the + * 'g0_interrupt_array'. + * + * 5. The 'g1s_interrupt_array' field is a ponter to an array in which each + * entry corresponds to an ID of a Group 1 interrupt. + * + * 6. The 'g1s_interrupt_num' field contains the number of entries in the + * 'g1s_interrupt_array'. + * + * 7. The 'rdistif_num' field contains the number of Redistributor interfaces + * the GIC implements. This is equal to the number of CPUs or CPU interfaces + * instantiated in the GIC. + * + * 8. The 'rdistif_base_addrs' field is a pointer to an array that has an entry + * for storing the base address of the Redistributor interface frame of each + * CPU in the system. The size of the array = 'rdistif_num'. The base + * addresses are detected during driver initialisation. + * + * 9. The 'mpidr_to_core_pos' field is a pointer to a hash function which the + * driver will use to convert an MPIDR value to a linear core index. This + * index will be used for accessing the 'rdistif_base_addrs' array. This is + * an optional field. A GICv3 implementation maps each MPIDR to a linear core + * index as well. This mapping can be found by reading the "Affinity Value" + * and "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the + * "Processor Numbers" are suitable to index into an array to access core + * specific information. If this not the case, the platform port must provide + * a hash function. Otherwise, the "Processor Number" field will be used to + * access the array elements. + ******************************************************************************/ +typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr); + +typedef struct gicv3_driver_data { + uintptr_t gicd_base; + uintptr_t gicr_base; + unsigned int g0_interrupt_num; + unsigned int g1s_interrupt_num; + const unsigned int *g0_interrupt_array; + const unsigned int *g1s_interrupt_array; + unsigned int rdistif_num; + uintptr_t *rdistif_base_addrs; + mpidr_hash_fn mpidr_to_core_pos; +} gicv3_driver_data_t; + +/******************************************************************************* + * GICv3 EL3 driver API + ******************************************************************************/ +void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data); +void gicv3_distif_init(void); +void gicv3_rdistif_init(unsigned int proc_num); +void gicv3_cpuif_enable(unsigned int proc_num); +void gicv3_cpuif_disable(unsigned int proc_num); +unsigned int gicv3_get_pending_interrupt_type(void); +unsigned int gicv3_get_pending_interrupt_id(void); +unsigned int gicv3_get_interrupt_type(unsigned int id, + unsigned int proc_num); + + +#endif /* __ASSEMBLY__ */ +#endif /* __GICV3_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/nic_400.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/nic_400.h new file mode 100644 index 0000000..1031662 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/nic_400.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NIC_400_H__ +#define __NIC_400_H__ + +/* + * Address of slave 'n' security setting in the NIC-400 address region + * control + */ +#define NIC400_ADDR_CTRL_SECURITY_REG(n) (0x8 + (n) * 4) + +#endif /* __NIC_400_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/pl011.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/pl011.h new file mode 100644 index 0000000..ce6cdcf --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/pl011.h @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PL011_H__ +#define __PL011_H__ + +/* PL011 Registers */ +#define UARTDR 0x000 +#define UARTRSR 0x004 +#define UARTECR 0x004 +#define UARTFR 0x018 +#define UARTIMSC 0x038 +#define UARTRIS 0x03C +#define UARTICR 0x044 + +/* PL011 registers (out of the SBSA specification) */ +#if !PL011_GENERIC_UART +#define UARTILPR 0x020 +#define UARTIBRD 0x024 +#define UARTFBRD 0x028 +#define UARTLCR_H 0x02C +#define UARTCR 0x030 +#define UARTIFLS 0x034 +#define UARTMIS 0x040 +#define UARTDMACR 0x048 +#endif /* !PL011_GENERIC_UART */ + +/* Data status bits */ +#define UART_DATA_ERROR_MASK 0x0F00 + +/* Status reg bits */ +#define UART_STATUS_ERROR_MASK 0x0F + +/* Flag reg bits */ +#define PL011_UARTFR_RI (1 << 8) /* Ring indicator */ +#define PL011_UARTFR_TXFE (1 << 7) /* Transmit FIFO empty */ +#define PL011_UARTFR_RXFF (1 << 6) /* Receive FIFO full */ +#define PL011_UARTFR_TXFF (1 << 5) /* Transmit FIFO full */ +#define PL011_UARTFR_RXFE (1 << 4) /* Receive FIFO empty */ +#define PL011_UARTFR_BUSY (1 << 3) /* UART busy */ +#define PL011_UARTFR_DCD (1 << 2) /* Data carrier detect */ +#define PL011_UARTFR_DSR (1 << 1) /* Data set ready */ +#define PL011_UARTFR_CTS (1 << 0) /* Clear to send */ + +#define PL011_UARTFR_TXFF_BIT 5 /* Transmit FIFO full bit in UARTFR register */ +#define PL011_UARTFR_RXFE_BIT 4 /* Receive FIFO empty bit in UARTFR register */ +#define PL011_UARTFR_BUSY_BIT 3 /* UART busy bit in UARTFR register */ + +/* Control reg bits */ +#if !PL011_GENERIC_UART +#define PL011_UARTCR_CTSEN (1 << 15) /* CTS hardware flow control enable */ +#define PL011_UARTCR_RTSEN (1 << 14) /* RTS hardware flow control enable */ +#define PL011_UARTCR_RTS (1 << 11) /* Request to send */ +#define PL011_UARTCR_DTR (1 << 10) /* Data transmit ready. */ +#define PL011_UARTCR_RXE (1 << 9) /* Receive enable */ +#define PL011_UARTCR_TXE (1 << 8) /* Transmit enable */ +#define PL011_UARTCR_LBE (1 << 7) /* Loopback enable */ +#define PL011_UARTCR_UARTEN (1 << 0) /* UART Enable */ + +#if !defined(PL011_LINE_CONTROL) +/* FIFO Enabled / No Parity / 8 Data bit / One Stop Bit */ +#define PL011_LINE_CONTROL (PL011_UARTLCR_H_FEN | PL011_UARTLCR_H_WLEN_8) +#endif + +/* Line Control Register Bits */ +#define PL011_UARTLCR_H_SPS (1 << 7) /* Stick parity select */ +#define PL011_UARTLCR_H_WLEN_8 (3 << 5) +#define PL011_UARTLCR_H_WLEN_7 (2 << 5) +#define PL011_UARTLCR_H_WLEN_6 (1 << 5) +#define PL011_UARTLCR_H_WLEN_5 (0 << 5) +#define PL011_UARTLCR_H_FEN (1 << 4) /* FIFOs Enable */ +#define PL011_UARTLCR_H_STP2 (1 << 3) /* Two stop bits select */ +#define PL011_UARTLCR_H_EPS (1 << 2) /* Even parity select */ +#define PL011_UARTLCR_H_PEN (1 << 1) /* Parity Enable */ +#define PL011_UARTLCR_H_BRK (1 << 0) /* Send break */ + +#endif /* !PL011_GENERIC_UART */ + +#endif /* __PL011_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/pl061_gpio.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/pl061_gpio.h new file mode 100644 index 0000000..ca79630 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/pl061_gpio.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PL061_GPIO_H__ +#define __PL061_GPIO_H__ + +#include + +void pl061_gpio_register(uintptr_t base_addr, int gpio_dev); +void pl061_gpio_init(void); + +#endif /* __PL061_GPIO_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/sp804_delay_timer.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/sp804_delay_timer.h new file mode 100644 index 0000000..1531e5a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/sp804_delay_timer.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SP804_DELAY_TIMER_H__ +#define __SP804_DELAY_TIMER_H__ + +#include +#include + + +uint32_t sp804_get_timer_value(void); + +void sp804_timer_ops_init(uintptr_t base_addr, const timer_ops_t *ops); + +#define sp804_timer_init(base_addr, clk_mult, clk_div) \ + do { \ + static const timer_ops_t sp804_timer_ops = { \ + sp804_get_timer_value, \ + (clk_mult), \ + (clk_div) \ + }; \ + sp804_timer_ops_init((base_addr), &sp804_timer_ops); \ + } while (0) + +#endif /* __SP804_DELAY_TIMER_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/sp805.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/sp805.h new file mode 100644 index 0000000..6bd8158 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/sp805.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SP805_H__ +#define __SP805_H__ + +/* SP805 register offset */ +#define SP805_WDOG_LOAD_OFF 0x000 +#define SP805_WDOG_CTR_OFF 0x008 +#define SP805_WDOG_LOCK_OFF 0xc00 + +/* Magic word to unlock the wd registers */ +#define WDOG_UNLOCK_KEY 0x1ACCE551 + +/* Register field definitions */ +#define SP805_CTR_RESEN (1 << 1) +#define SP805_CTR_INTEN (1 << 0) + +#ifndef __ASSEMBLY__ + +#include + +/* Public high level API */ + +void sp805_start(uintptr_t base, unsigned long ticks); +void sp805_stop(uintptr_t base); +void sp805_refresh(uintptr_t base, unsigned long ticks); + +#endif /* __ASSEMBLY__ */ + +#endif /* __SP805_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/tzc400.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/tzc400.h new file mode 100644 index 0000000..d8af7e1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/tzc400.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TZC400_H__ +#define __TZC400_H__ + +#include + +#define BUILD_CONFIG_OFF 0x000 +#define GATE_KEEPER_OFF 0x008 +#define SPECULATION_CTRL_OFF 0x00c +#define INT_STATUS 0x010 +#define INT_CLEAR 0x014 + +#define FAIL_ADDRESS_LOW_OFF 0x020 +#define FAIL_ADDRESS_HIGH_OFF 0x024 +#define FAIL_CONTROL_OFF 0x028 +#define FAIL_ID 0x02c + +/* ID registers not common across different varieties of TZC */ +#define PID5 0xFD4 +#define PID6 0xFD8 +#define PID7 0xFDC + +#define BUILD_CONFIG_NF_SHIFT 24 +#define BUILD_CONFIG_NF_MASK 0x3 +#define BUILD_CONFIG_AW_SHIFT 8 +#define BUILD_CONFIG_AW_MASK 0x3f +#define BUILD_CONFIG_NR_SHIFT 0 +#define BUILD_CONFIG_NR_MASK 0x1f + +/* + * Number of gate keepers is implementation defined. But we know the max for + * this device is 4. Get implementation details from BUILD_CONFIG. + */ +#define GATE_KEEPER_OS_SHIFT 16 +#define GATE_KEEPER_OS_MASK 0xf +#define GATE_KEEPER_OR_SHIFT 0 +#define GATE_KEEPER_OR_MASK 0xf +#define GATE_KEEPER_FILTER_MASK 0x1 + +/* Speculation is enabled by default. */ +#define SPECULATION_CTRL_WRITE_DISABLE (1 << 1) +#define SPECULATION_CTRL_READ_DISABLE (1 << 0) + +/* Max number of filters allowed is 4. */ +#define INT_STATUS_OVERLAP_SHIFT 16 +#define INT_STATUS_OVERLAP_MASK 0xf +#define INT_STATUS_OVERRUN_SHIFT 8 +#define INT_STATUS_OVERRUN_MASK 0xf +#define INT_STATUS_STATUS_SHIFT 0 +#define INT_STATUS_STATUS_MASK 0xf + +#define INT_CLEAR_CLEAR_SHIFT 0 +#define INT_CLEAR_CLEAR_MASK 0xf + +#define FAIL_CONTROL_DIR_SHIFT (1 << 24) +#define FAIL_CONTROL_DIR_READ 0x0 +#define FAIL_CONTROL_DIR_WRITE 0x1 +#define FAIL_CONTROL_NS_SHIFT (1 << 21) +#define FAIL_CONTROL_NS_SECURE 0x0 +#define FAIL_CONTROL_NS_NONSECURE 0x1 +#define FAIL_CONTROL_PRIV_SHIFT (1 << 20) +#define FAIL_CONTROL_PRIV_PRIV 0x0 +#define FAIL_CONTROL_PRIV_UNPRIV 0x1 + +/* + * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. + * Platform should provide the value on initialisation. + */ +#define FAIL_ID_VNET_SHIFT 24 +#define FAIL_ID_VNET_MASK 0xf +#define FAIL_ID_ID_SHIFT 0 + +#define TZC_400_PERIPHERAL_ID 0x460 + +/* Filter enable bits in a TZC */ +#define TZC_400_REGION_ATTR_F_EN_MASK 0xf +#define TZC_400_REGION_ATTR_FILTER_BIT(x) ((1 << x) \ + << TZC_REGION_ATTR_F_EN_SHIFT) +#define TZC_400_REGION_ATTR_FILTER_BIT_ALL \ + (TZC_400_REGION_ATTR_F_EN_MASK << \ + TZC_REGION_ATTR_F_EN_SHIFT) + +/* + * Define some macros for backward compatibility with existing tzc400 clients. + */ +#if !ERROR_DEPRECATED +#define REG_ATTR_FILTER_BIT(x) ((1 << x) \ + << TZC_REGION_ATTR_F_EN_SHIFT) +#define REG_ATTR_FILTER_BIT_ALL (TZC_400_REGION_ATTR_F_EN_MASK << \ + TZC_REGION_ATTR_F_EN_SHIFT) +#endif /* __ERROR_DEPRECATED__ */ + +/* + * All TZC region configuration registers are placed one after another. It + * depicts size of block of registers for programming each region. + */ +#define TZC_400_REGION_SIZE 0x20 +#define TZC_400_ACTION_OFF 0x4 + +#ifndef __ASSEMBLY__ + +#include +#include + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void tzc400_init(uintptr_t base); +void tzc400_configure_region0(tzc_region_attributes_t sec_attr, + unsigned int ns_device_access); +void tzc400_configure_region(unsigned int filters, + int region, + unsigned long long region_base, + unsigned long long region_top, + tzc_region_attributes_t sec_attr, + unsigned int ns_device_access); +void tzc400_set_action(tzc_action_t action); +void tzc400_enable_filters(void); +void tzc400_disable_filters(void); + +/* + * Deprecated APIs + */ +static inline void tzc_init(uintptr_t base) __deprecated; +static inline void tzc_configure_region0( + tzc_region_attributes_t sec_attr, + unsigned int ns_device_access) __deprecated; +static inline void tzc_configure_region( + unsigned int filters, + int region, + unsigned long long region_base, + unsigned long long region_top, + tzc_region_attributes_t sec_attr, + unsigned int ns_device_access) __deprecated; +static inline void tzc_set_action(tzc_action_t action) __deprecated; +static inline void tzc_enable_filters(void) __deprecated; +static inline void tzc_disable_filters(void) __deprecated; + +static inline void tzc_init(uintptr_t base) +{ + tzc400_init(base); +} + +static inline void tzc_configure_region0( + tzc_region_attributes_t sec_attr, + unsigned int ns_device_access) +{ + tzc400_configure_region0(sec_attr, ns_device_access); +} + +static inline void tzc_configure_region( + unsigned int filters, + int region, + unsigned long long region_base, + unsigned long long region_top, + tzc_region_attributes_t sec_attr, + unsigned int ns_device_access) +{ + tzc400_configure_region(filters, region, region_base, + region_top, sec_attr, ns_device_access); +} + +static inline void tzc_set_action(tzc_action_t action) +{ + tzc400_set_action(action); +} + + +static inline void tzc_enable_filters(void) +{ + tzc400_enable_filters(); +} + +static inline void tzc_disable_filters(void) +{ + tzc400_disable_filters(); +} + +#endif /* __ASSEMBLY__ */ + +#endif /* __TZC400__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/tzc_common.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/tzc_common.h new file mode 100644 index 0000000..9b73c3f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/tzc_common.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TZC_COMMON_H__ +#define __TZC_COMMON_H__ + +/* + * Offset of core registers from the start of the base of configuration + * registers for each region. + */ + +/* ID Registers */ +#define PID0_OFF 0xfe0 +#define PID1_OFF 0xfe4 +#define PID2_OFF 0xfe8 +#define PID3_OFF 0xfec +#define PID4_OFF 0xfd0 +#define CID0_OFF 0xff0 +#define CID1_OFF 0xff4 +#define CID2_OFF 0xff8 +#define CID3_OFF 0xffc + +/* Bit positions of TZC_ACTION registers */ +#define TZC_ACTION_RV_SHIFT 0 +#define TZC_ACTION_RV_MASK 0x3 +#define TZC_ACTION_RV_LOWOK 0x0 +#define TZC_ACTION_RV_LOWERR 0x1 +#define TZC_ACTION_RV_HIGHOK 0x2 +#define TZC_ACTION_RV_HIGHERR 0x3 + +/* Used along with 'tzc_region_attributes_t' below */ +#define TZC_REGION_ATTR_S_RD_SHIFT 30 +#define TZC_REGION_ATTR_S_WR_SHIFT 31 +#define TZC_REGION_ATTR_F_EN_SHIFT 0 +#define TZC_REGION_ATTR_SEC_SHIFT 30 +#define TZC_REGION_ATTR_S_RD_MASK 0x1 +#define TZC_REGION_ATTR_S_WR_MASK 0x1 +#define TZC_REGION_ATTR_SEC_MASK 0x3 + +#define TZC_REGION_ACCESS_WR_EN_SHIFT 16 +#define TZC_REGION_ACCESS_RD_EN_SHIFT 0 +#define TZC_REGION_ACCESS_ID_MASK 0xf + +/* Macros for allowing Non-Secure access to a region based on NSAID */ +#define TZC_REGION_ACCESS_RD(nsaid) \ + ((1 << (nsaid & TZC_REGION_ACCESS_ID_MASK)) << \ + TZC_REGION_ACCESS_RD_EN_SHIFT) +#define TZC_REGION_ACCESS_WR(nsaid) \ + ((1 << (nsaid & TZC_REGION_ACCESS_ID_MASK)) << \ + TZC_REGION_ACCESS_WR_EN_SHIFT) +#define TZC_REGION_ACCESS_RDWR(nsaid) \ + (TZC_REGION_ACCESS_RD(nsaid) | \ + TZC_REGION_ACCESS_WR(nsaid)) + +#ifndef __ASSEMBLY__ + +/* Returns offset of registers to program for a given region no */ +#define TZC_REGION_OFFSET(region_size, region_no) \ + ((region_size) * (region_no)) + +/* + * What type of action is expected when an access violation occurs. + * The memory requested is returned as zero. But we can also raise an event to + * let the system know it happened. + * We can raise an interrupt(INT) and/or cause an exception(ERR). + * TZC_ACTION_NONE - No interrupt, no Exception + * TZC_ACTION_ERR - No interrupt, raise exception -> sync external + * data abort + * TZC_ACTION_INT - Raise interrupt, no exception + * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync + * external data abort + */ +typedef enum { + TZC_ACTION_NONE = 0, + TZC_ACTION_ERR = 1, + TZC_ACTION_INT = 2, + TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) +} tzc_action_t; + +/* + * Controls secure access to a region. If not enabled secure access is not + * allowed to region. + */ +typedef enum { + TZC_REGION_S_NONE = 0, + TZC_REGION_S_RD = 1, + TZC_REGION_S_WR = 2, + TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR) +} tzc_region_attributes_t; + +#endif /* __ASSEMBLY__ */ +#endif /* __TZC_COMMON_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/tzc_dmc500.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/tzc_dmc500.h new file mode 100644 index 0000000..e21818f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/arm/tzc_dmc500.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TZC_DMC500_H__ +#define __TZC_DMC500_H__ + +#include + +#define SI_STATUS_OFFSET 0x000 +#define SI_STATE_CTRL_OFFSET 0x030 +#define SI_FLUSH_CTRL_OFFSET 0x034 +#define SI_INT_CONTROL_OFFSET 0x048 + +#define SI_INT_STATUS_OFFSET 0x004 +#define SI_TZ_FAIL_ADDRESS_LOW_OFFSET 0x008 +#define SI_TZ_FAIL_ADDRESS_HIGH_OFFSET 0x00c +#define SI_FAIL_CONTROL_OFFSET 0x010 +#define SI_FAIL_ID_OFFSET 0x014 +#define SI_INT_CLR_OFFSET 0x04c + +/* + * DMC-500 has 2 system interfaces each having a similar set of regs + * to configure each interface. + */ +#define SI0_BASE 0x0000 +#define SI1_BASE 0x0200 + +/* Bit positions of SIx_SI_STATUS */ +#define SI_EMPTY_SHIFT 0x01 +#define SI_STALL_ACK_SHIFT 0x00 +#define SI_EMPTY_MASK 0x01 +#define SI_STALL_ACK_MASK 0x01 + +/* Bit positions of SIx_SI_INT_STATUS */ +#define PMU_REQ_INT_OVERFLOW_STATUS_SHIFT 18 +#define FAILED_ACCESS_INT_OVERFLOW_STATUS_SHIFT 16 +#define PMU_REQ_INT_STATUS_SHIFT 2 +#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_SHIFT 1 +#define FAILED_ACCESS_INT_STATUS_SHIFT 0 +#define PMU_REQ_INT_OVERFLOW_STATUS_MASK 0x1 +#define FAILED_ACCESS_INT_OVERFLOW_STATUS_MASK 0x1 +#define PMU_REQ_INT_STATUS_MASK 0x1 +#define FAILED_ACCESS_INT_INFO_TZ_OVERLAP_STATUS_MASK 0x1 +#define FAILED_ACCESS_INT_STATUS_MASK 0x1 + +/* Bit positions of SIx_TZ_FAIL_CONTROL */ +#define DIRECTION_SHIFT 24 +#define NON_SECURE_SHIFT 21 +#define PRIVILEGED_SHIFT 20 +#define FAILED_ACCESS_INT_INFO_RANK_MASKED_SHIFT 3 +#define FAILED_ACCESS_INT_INFO_UNMAPPED_SHIFT 2 +#define FAILED_ACCESS_INT_TZ_FAIL_SHIFT 0x1 +#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_SHIFT 0 +#define DIRECTION_MASK 0x1 +#define NON_SECURE_MASK 0x1 +#define PRIVILEGED_MASK 0x1 +#define FAILED_ACCESS_INT_INFO_RANK_MASKED_MASK 0x1 +#define FAILED_ACCESS_INT_INFO_UNMAPPED_MASK 0x1 +#define FAILED_ACCESS_INT_TZ_FAIL_MASK 1 +#define FAILED_ACCESS_INT_INFO_OUTSIDE_DEFAULT_MASK 0x1 + +/* Bit positions of SIx_FAIL_STATUS */ +#define FAIL_ID_VNET_SHIFT 24 +#define FAIL_ID_ID_SHIFT 0 +#define FAIL_ID_VNET_MASK 0xf +#define FAIL_ID_ID_MASK 0xffffff + +/* Bit positions of SIx_SI_STATE_CONTRL */ +#define SI_STALL_REQ_GO 0x0 +#define SI_STALL_REQ_STALL 0x1 + +/* Bit positions of SIx_SI_FLUSH_CONTROL */ +#define SI_FLUSH_REQ_INACTIVE 0x0 +#define SI_FLUSH_REQ_ACTIVE 0x1 +#define SI_FLUSH_REQ_MASK 0x1 + +/* Bit positions of SIx_SI_INT_CONTROL */ +#define PMU_REQ_INT_EN_SHIFT 2 +#define OVERLAP_DETECT_INT_EN_SHIFT 1 +#define FAILED_ACCESS_INT_EN_SHIFT 0 +#define PMU_REQ_INT_EN_MASK 0x1 +#define OVERLAP_DETECT_INT_EN_MASK 0x1 +#define FAILED_ACCESS_INT_EN_MASK 0x1 +#define PMU_REQ_INT_EN 0x1 +#define OVERLAP_DETECT_INT_EN 0x1 +#define FAILED_ACCESS_INT_EN 0x1 + +/* Bit positions of SIx_SI_INT_CLR */ +#define PMU_REQ_OFLOW_CLR_SHIFT 18 +#define FAILED_ACCESS_OFLOW_CLR_SHIFT 16 +#define PMU_REQ_INT_CLR_SHIFT 2 +#define FAILED_ACCESS_INT_CLR_SHIFT 0 +#define PMU_REQ_OFLOW_CLR_MASK 0x1 +#define FAILED_ACCESS_OFLOW_CLR_MASK 0x1 +#define PMU_REQ_INT_CLR_MASK 0x1 +#define FAILED_ACCESS_INT_CLR_MASK 0x1 +#define PMU_REQ_OFLOW_CLR 0x1 +#define FAILED_ACCESS_OFLOW_CLR 0x1 +#define PMU_REQ_INT_CLR 0x1 +#define FAILED_ACCESS_INT_CLR 0x1 + +/* Macro to get the correct base register for a system interface */ +#define IFACE_OFFSET(sys_if) ((sys_if) ? SI1_BASE : SI0_BASE) + +#define MAX_SYS_IF_COUNT 2 +#define MAX_REGION_VAL 8 + +/* DMC-500 supports striping across a max of 4 DMC instances */ +#define MAX_DMC_COUNT 4 + +/* Consist of part_number_1 and part_number_0 */ +#define DMC500_PERIPHERAL_ID 0x0450 + +/* Filter enable bits in a TZC */ +#define TZC_DMC500_REGION_ATTR_F_EN_MASK 0x1 + +/* Length of registers for configuring each region */ +#define TZC_DMC500_REGION_SIZE 0x018 + +#ifndef __ASSEMBLY__ + +#include + +/* + * Contains the base addresses of all the DMC instances. + */ +typedef struct tzc_dmc500_driver_data { + uintptr_t dmc_base[MAX_DMC_COUNT]; + int dmc_count; +} tzc_dmc500_driver_data_t; + +void tzc_dmc500_driver_init(const tzc_dmc500_driver_data_t *plat_driver_data); +void tzc_dmc500_configure_region0(tzc_region_attributes_t sec_attr, + unsigned int nsaid_permissions); +void tzc_dmc500_configure_region(int region_no, + unsigned long long region_base, + unsigned long long region_top, + tzc_region_attributes_t sec_attr, + unsigned int nsaid_permissions); +void tzc_dmc500_set_action(tzc_action_t action); +void tzc_dmc500_config_complete(void); +int tzc_dmc500_verify_complete(void); + + +#endif /* __ASSEMBLY__ */ +#endif /* __TZC_DMC500_H__ */ + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/auth_common.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/auth_common.h new file mode 100644 index 0000000..456f69f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/auth_common.h @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AUTH_COMMON_H__ +#define __AUTH_COMMON_H__ + +/* + * Authentication framework common types + */ + +/* + * Type of parameters that can be extracted from an image and + * used for authentication + */ +typedef enum auth_param_type_enum { + AUTH_PARAM_NONE, + AUTH_PARAM_RAW_DATA, /* Raw image data */ + AUTH_PARAM_SIG, /* The image signature */ + AUTH_PARAM_SIG_ALG, /* The image signature algorithm */ + AUTH_PARAM_HASH, /* A hash (including the algorithm) */ + AUTH_PARAM_PUB_KEY, /* A public key */ + AUTH_PARAM_NV_CTR, /* A non-volatile counter */ +} auth_param_type_t; + +/* + * Defines an authentication parameter. The cookie will be interpreted by the + * image parser module. + */ +typedef struct auth_param_type_desc_s { + auth_param_type_t type; + void *cookie; +} auth_param_type_desc_t; + +/* + * Store a pointer to the authentication parameter and its length + */ +typedef struct auth_param_data_desc_s { + void *ptr; + unsigned int len; +} auth_param_data_desc_t; + +/* + * Authentication parameter descriptor, including type and value + */ +typedef struct auth_param_desc_s { + auth_param_type_desc_t *type_desc; + auth_param_data_desc_t data; +} auth_param_desc_t; + +/* + * The method type defines how an image is authenticated + */ +typedef enum auth_method_type_enum { + AUTH_METHOD_NONE = 0, + AUTH_METHOD_HASH, /* Authenticate by hash matching */ + AUTH_METHOD_SIG, /* Authenticate by PK operation */ + AUTH_METHOD_NV_CTR, /* Authenticate by Non-Volatile Counter */ + AUTH_METHOD_NUM /* Number of methods */ +} auth_method_type_t; + +/* + * Parameters for authentication by hash matching + */ +typedef struct auth_method_param_hash_s { + auth_param_type_desc_t *data; /* Data to hash */ + auth_param_type_desc_t *hash; /* Hash to match with */ +} auth_method_param_hash_t; + +/* + * Parameters for authentication by signature + */ +typedef struct auth_method_param_sig_s { + auth_param_type_desc_t *pk; /* Public key */ + auth_param_type_desc_t *sig; /* Signature to check */ + auth_param_type_desc_t *alg; /* Signature algorithm */ + auth_param_type_desc_t *data; /* Data signed */ +} auth_method_param_sig_t; + +/* + * Parameters for authentication by NV counter + */ +typedef struct auth_method_param_nv_ctr_s { + auth_param_type_desc_t *cert_nv_ctr; /* NV counter in certificate */ + auth_param_type_desc_t *plat_nv_ctr; /* NV counter in platform */ +} auth_method_param_nv_ctr_t; + +/* + * Authentication method descriptor + */ +typedef struct auth_method_desc_s { + auth_method_type_t type; + union { + auth_method_param_hash_t hash; + auth_method_param_sig_t sig; + auth_method_param_nv_ctr_t nv_ctr; + } param; +} auth_method_desc_t; + +/* + * Helper macro to define an authentication parameter type descriptor + */ +#define AUTH_PARAM_TYPE_DESC(_type, _cookie) \ + { \ + .type = _type, \ + .cookie = (void *)_cookie \ + } + +/* + * Helper macro to define an authentication parameter data descriptor + */ +#define AUTH_PARAM_DATA_DESC(_ptr, _len) \ + { \ + .ptr = (void *)_ptr, \ + .len = (unsigned int)_len \ + } + +#endif /* __AUTH_COMMON_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/auth_mod.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/auth_mod.h new file mode 100644 index 0000000..4ed4684 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/auth_mod.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AUTH_MOD_H__ +#define __AUTH_MOD_H__ + +#if TRUSTED_BOARD_BOOT + +#include +#include +#include + +/* + * Image flags + */ +#define IMG_FLAG_AUTHENTICATED (1 << 0) + + +/* + * Authentication image descriptor + */ +typedef struct auth_img_desc_s { + unsigned int img_id; + img_type_t img_type; + const struct auth_img_desc_s *parent; + auth_method_desc_t img_auth_methods[AUTH_METHOD_NUM]; + auth_param_desc_t authenticated_data[COT_MAX_VERIFIED_PARAMS]; +} auth_img_desc_t; + +/* Public functions */ +void auth_mod_init(void); +int auth_mod_get_parent_id(unsigned int img_id, unsigned int *parent_id); +int auth_mod_verify_img(unsigned int img_id, + void *img_ptr, + unsigned int img_len); + +/* Macro to register a CoT defined as an array of auth_img_desc_t */ +#define REGISTER_COT(_cot) \ + const auth_img_desc_t *const cot_desc_ptr = \ + (const auth_img_desc_t *const)&_cot[0]; \ + unsigned int auth_img_flags[sizeof(_cot)/sizeof(_cot[0])] + +#endif /* TRUSTED_BOARD_BOOT */ + +#endif /* __AUTH_MOD_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/crypto_mod.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/crypto_mod.h new file mode 100644 index 0000000..5a55624 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/crypto_mod.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CRYPTO_MOD_H__ +#define __CRYPTO_MOD_H__ + +/* Return values */ +enum crypto_ret_value { + CRYPTO_SUCCESS = 0, + CRYPTO_ERR_INIT, + CRYPTO_ERR_HASH, + CRYPTO_ERR_SIGNATURE, + CRYPTO_ERR_UNKNOWN +}; + +/* + * Cryptographic library descriptor + */ +typedef struct crypto_lib_desc_s { + const char *name; + + /* Initialize library. This function is not expected to fail. All errors + * must be handled inside the function, asserting or panicing in case of + * a non-recoverable error */ + void (*init)(void); + + /* Verify a digital signature. Return one of the + * 'enum crypto_ret_value' options */ + int (*verify_signature)(void *data_ptr, unsigned int data_len, + void *sig_ptr, unsigned int sig_len, + void *sig_alg, unsigned int sig_alg_len, + void *pk_ptr, unsigned int pk_len); + + /* Verify a hash. Return one of the 'enum crypto_ret_value' options */ + int (*verify_hash)(void *data_ptr, unsigned int data_len, + void *digest_info_ptr, unsigned int digest_info_len); +} crypto_lib_desc_t; + +/* Public functions */ +void crypto_mod_init(void); +int crypto_mod_verify_signature(void *data_ptr, unsigned int data_len, + void *sig_ptr, unsigned int sig_len, + void *sig_alg, unsigned int sig_alg_len, + void *pk_ptr, unsigned int pk_len); +int crypto_mod_verify_hash(void *data_ptr, unsigned int data_len, + void *digest_info_ptr, unsigned int digest_info_len); + +/* Macro to register a cryptographic library */ +#define REGISTER_CRYPTO_LIB(_name, _init, _verify_signature, _verify_hash) \ + const crypto_lib_desc_t crypto_lib_desc = { \ + .name = _name, \ + .init = _init, \ + .verify_signature = _verify_signature, \ + .verify_hash = _verify_hash \ + } + +#endif /* __CRYPTO_MOD_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/img_parser_mod.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/img_parser_mod.h new file mode 100644 index 0000000..79d7d79 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/img_parser_mod.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IMG_PARSER_MOD_H__ +#define __IMG_PARSER_MOD_H__ + +#include + +/* + * Return values + */ +enum img_parser_ret_value { + IMG_PARSER_OK, + IMG_PARSER_ERR, /* Parser internal error */ + IMG_PARSER_ERR_FORMAT, /* Malformed image */ + IMG_PARSER_ERR_NOT_FOUND /* Authentication data not found */ +}; + +/* + * Image types. A parser should be instantiated and registered for each type + */ +typedef enum img_type_enum { + IMG_RAW, /* Binary image */ + IMG_PLAT, /* Platform specific format */ + IMG_CERT, /* X509v3 certificate */ + IMG_MAX_TYPES, +} img_type_t; + +/* Image parser library structure */ +typedef struct img_parser_lib_desc_s { + img_type_t img_type; + const char *name; + + void (*init)(void); + int (*check_integrity)(void *img, unsigned int img_len); + int (*get_auth_param)(const auth_param_type_desc_t *type_desc, + void *img, unsigned int img_len, + void **param, unsigned int *param_len); +} img_parser_lib_desc_t; + +/* Exported functions */ +void img_parser_init(void); +int img_parser_check_integrity(img_type_t img_type, + void *img, unsigned int img_len); +int img_parser_get_auth_param(img_type_t img_type, + const auth_param_type_desc_t *type_desc, + void *img, unsigned int img_len, + void **param_ptr, unsigned int *param_len); + +/* Macro to register an image parser library */ +#define REGISTER_IMG_PARSER_LIB(_type, _name, _init, _check_int, _get_param) \ + static const img_parser_lib_desc_t __img_parser_lib_desc_##_type \ + __section(".img_parser_lib_descs") __used = { \ + .img_type = _type, \ + .name = _name, \ + .init = _init, \ + .check_integrity = _check_int, \ + .get_auth_param = _get_param \ + } + +#endif /* __IMG_PARSER_MOD_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/mbedtls/mbedtls_common.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/mbedtls/mbedtls_common.h new file mode 100644 index 0000000..eb22e8a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/mbedtls/mbedtls_common.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MBEDTLS_COMMON_H__ +#define __MBEDTLS_COMMON_H__ + +void mbedtls_init(void); + +#endif /* __MBEDTLS_COMMON_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/mbedtls/mbedtls_config.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/mbedtls/mbedtls_config.h new file mode 100644 index 0000000..a8d7241 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/auth/mbedtls/mbedtls_config.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MBEDTLS_CONFIG_H__ +#define __MBEDTLS_CONFIG_H__ + +/* + * Key algorithms currently supported on mbed TLS libraries + */ +#define MBEDTLS_RSA 1 +#define MBEDTLS_ECDSA 2 + +/* + * Configuration file to build mbed TLS with the required features for + * Trusted Boot + */ + +#define MBEDTLS_PLATFORM_MEMORY +#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS + +#define MBEDTLS_PKCS1_V15 +#define MBEDTLS_PKCS1_V21 + +#define MBEDTLS_X509_ALLOW_UNSUPPORTED_CRITICAL_EXTENSION +#define MBEDTLS_X509_CHECK_KEY_USAGE +#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE + +#define MBEDTLS_ASN1_PARSE_C +#define MBEDTLS_ASN1_WRITE_C + +#define MBEDTLS_BASE64_C +#define MBEDTLS_BIGNUM_C + +#define MBEDTLS_ERROR_C +#define MBEDTLS_MD_C + +#define MBEDTLS_MEMORY_BUFFER_ALLOC_C +#define MBEDTLS_OID_C + +#define MBEDTLS_PK_C +#define MBEDTLS_PK_PARSE_C +#define MBEDTLS_PK_WRITE_C + +#define MBEDTLS_PLATFORM_C + +#if (MBEDTLS_KEY_ALG_ID == MBEDTLS_ECDSA) +#define MBEDTLS_ECDSA_C +#define MBEDTLS_ECP_C +#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#elif (MBEDTLS_KEY_ALG_ID == MBEDTLS_RSA) +#define MBEDTLS_RSA_C +#endif + +#define MBEDTLS_SHA256_C + +#define MBEDTLS_VERSION_C + +#define MBEDTLS_X509_USE_C +#define MBEDTLS_X509_CRT_PARSE_C + +/* MPI / BIGNUM options */ +#define MBEDTLS_MPI_WINDOW_SIZE 2 +#define MBEDTLS_MPI_MAX_SIZE 256 + +/* Memory buffer allocator options */ +#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 8 + +#include "mbedtls/check_config.h" + +/* System headers required to build mbed TLS with the current configuration */ +#include + +#endif /* __MBEDTLS_CONFIG_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/cadence/cdns_uart.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/cadence/cdns_uart.h new file mode 100644 index 0000000..bc1cc90 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/cadence/cdns_uart.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CADENCE_UART_H__ +#define __CADENCE_UART_H__ + +/* This is very minimalistic and will only work in QEMU. */ + +/* CADENCE Registers */ +#define R_UART_CR 0 +#define R_UART_CR_RXRST (1 << 0) /* RX logic reset */ +#define R_UART_CR_TXRST (1 << 1) /* TX logic reset */ +#define R_UART_CR_RX_EN (1 << 2) /* RX enabled */ +#define R_UART_CR_TX_EN (1 << 4) /* TX enabled */ + +#define R_UART_SR 0x2C +#define UART_SR_INTR_REMPTY_BIT 1 +#define UART_SR_INTR_TFUL_BIT 4 + +#define R_UART_TX 0x30 +#define R_UART_RX 0x30 + +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/console.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/console.h new file mode 100644 index 0000000..69ad0bd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/console.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CONSOLE_H__ +#define __CONSOLE_H__ + +#include + +int console_init(uintptr_t base_addr, + unsigned int uart_clk, unsigned int baud_rate); +void console_uninit(void); +int console_putc(int c); +int console_getc(void); + +#endif /* __CONSOLE_H__ */ + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/delay_timer.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/delay_timer.h new file mode 100644 index 0000000..0dec626 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/delay_timer.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DELAY_TIMER_H__ +#define __DELAY_TIMER_H__ + +#include + +/******************************************************************** + * A simple timer driver providing synchronous delay functionality. + * The driver must be initialized with a structure that provides a + * function pointer to return the timer value and a clock + * multiplier/divider. The ratio of the multiplier and the divider is + * the clock period in microseconds. + ********************************************************************/ + +typedef struct timer_ops { + uint32_t (*get_timer_value)(void); + uint32_t clk_mult; + uint32_t clk_div; +} timer_ops_t; + +void mdelay(uint32_t msec); +void udelay(uint32_t usec); +void timer_init(const timer_ops_t *ops); + + +#endif /* __DELAY_TIMER_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/emmc.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/emmc.h new file mode 100644 index 0000000..5f78dce --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/emmc.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __EMMC_H__ +#define __EMMC_H__ + +#include + +#define EMMC_BLOCK_SIZE 512 +#define EMMC_BLOCK_MASK (EMMC_BLOCK_SIZE - 1) +#define EMMC_BOOT_CLK_RATE (400 * 1000) + +#define EMMC_CMD0 0 +#define EMMC_CMD1 1 +#define EMMC_CMD2 2 +#define EMMC_CMD3 3 +#define EMMC_CMD6 6 +#define EMMC_CMD7 7 +#define EMMC_CMD8 8 +#define EMMC_CMD9 9 +#define EMMC_CMD12 12 +#define EMMC_CMD13 13 +#define EMMC_CMD17 17 +#define EMMC_CMD18 18 +#define EMMC_CMD23 23 +#define EMMC_CMD24 24 +#define EMMC_CMD25 25 +#define EMMC_CMD35 35 +#define EMMC_CMD36 36 +#define EMMC_CMD38 38 + +#define OCR_POWERUP (1 << 31) +#define OCR_BYTE_MODE (0 << 29) +#define OCR_SECTOR_MODE (2 << 29) +#define OCR_ACCESS_MODE_MASK (3 << 29) +#define OCR_VDD_MIN_2V7 (0x1ff << 15) +#define OCR_VDD_MIN_2V0 (0x7f << 8) +#define OCR_VDD_MIN_1V7 (1 << 7) + +#define EMMC_RESPONSE_R1 1 +#define EMMC_RESPONSE_R1B 1 +#define EMMC_RESPONSE_R2 4 +#define EMMC_RESPONSE_R3 1 +#define EMMC_RESPONSE_R4 1 +#define EMMC_RESPONSE_R5 1 + +#define EMMC_FIX_RCA 6 /* > 1 */ +#define RCA_SHIFT_OFFSET 16 + +#define CMD_EXTCSD_PARTITION_CONFIG 179 +#define CMD_EXTCSD_BUS_WIDTH 183 +#define CMD_EXTCSD_HS_TIMING 185 + +#define PART_CFG_BOOT_PARTITION1_ENABLE (1 << 3) +#define PART_CFG_PARTITION1_ACCESS (1 << 0) + +/* values in EXT CSD register */ +#define EMMC_BUS_WIDTH_1 0 +#define EMMC_BUS_WIDTH_4 1 +#define EMMC_BUS_WIDTH_8 2 +#define EMMC_BOOT_MODE_BACKWARD (0 << 3) +#define EMMC_BOOT_MODE_HS_TIMING (1 << 3) +#define EMMC_BOOT_MODE_DDR (2 << 3) + +#define EXTCSD_SET_CMD (0 << 24) +#define EXTCSD_SET_BITS (1 << 24) +#define EXTCSD_CLR_BITS (2 << 24) +#define EXTCSD_WRITE_BYTES (3 << 24) +#define EXTCSD_CMD(x) (((x) & 0xff) << 16) +#define EXTCSD_VALUE(x) (((x) & 0xff) << 8) + +#define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9) +#define STATUS_READY_FOR_DATA (1 << 8) +#define STATUS_SWITCH_ERROR (1 << 7) +#define EMMC_GET_STATE(x) (((x) >> 9) & 0xf) +#define EMMC_STATE_IDLE 0 +#define EMMC_STATE_READY 1 +#define EMMC_STATE_IDENT 2 +#define EMMC_STATE_STBY 3 +#define EMMC_STATE_TRAN 4 +#define EMMC_STATE_DATA 5 +#define EMMC_STATE_RCV 6 +#define EMMC_STATE_PRG 7 +#define EMMC_STATE_DIS 8 +#define EMMC_STATE_BTST 9 +#define EMMC_STATE_SLP 10 + +#define EMMC_FLAG_CMD23 (1 << 0) + +typedef struct emmc_cmd { + unsigned int cmd_idx; + unsigned int cmd_arg; + unsigned int resp_type; + unsigned int resp_data[4]; +} emmc_cmd_t; + +typedef struct emmc_ops { + void (*init)(void); + int (*send_cmd)(emmc_cmd_t *cmd); + int (*set_ios)(int clk, int width); + int (*prepare)(int lba, uintptr_t buf, size_t size); + int (*read)(int lba, uintptr_t buf, size_t size); + int (*write)(int lba, const uintptr_t buf, size_t size); +} emmc_ops_t; + +typedef struct emmc_csd { + unsigned char not_used: 1; + unsigned char crc: 7; + unsigned char ecc: 2; + unsigned char file_format: 2; + unsigned char tmp_write_protect: 1; + unsigned char perm_write_protect: 1; + unsigned char copy: 1; + unsigned char file_format_grp: 1; + + unsigned short reserved_1: 5; + unsigned short write_bl_partial: 1; + unsigned short write_bl_len: 4; + unsigned short r2w_factor: 3; + unsigned short default_ecc: 2; + unsigned short wp_grp_enable: 1; + + unsigned int wp_grp_size: 5; + unsigned int erase_grp_mult: 5; + unsigned int erase_grp_size: 5; + unsigned int c_size_mult: 3; + unsigned int vdd_w_curr_max: 3; + unsigned int vdd_w_curr_min: 3; + unsigned int vdd_r_curr_max: 3; + unsigned int vdd_r_curr_min: 3; + unsigned int c_size_low: 2; + + unsigned int c_size_high: 10; + unsigned int reserved_2: 2; + unsigned int dsr_imp: 1; + unsigned int read_blk_misalign: 1; + unsigned int write_blk_misalign: 1; + unsigned int read_bl_partial: 1; + unsigned int read_bl_len: 4; + unsigned int ccc: 12; + + unsigned int tran_speed: 8; + unsigned int nsac: 8; + unsigned int taac: 8; + unsigned int reserved_3: 2; + unsigned int spec_vers: 4; + unsigned int csd_structure: 2; +} emmc_csd_t; + +size_t emmc_read_blocks(int lba, uintptr_t buf, size_t size); +size_t emmc_write_blocks(int lba, const uintptr_t buf, size_t size); +size_t emmc_erase_blocks(int lba, size_t size); +size_t emmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size); +size_t emmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size); +size_t emmc_rpmb_erase_blocks(int lba, size_t size); +void emmc_init(const emmc_ops_t *ops, int clk, int bus_width, + unsigned int flags); + +#endif /* __EMMC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/generic_delay_timer.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/generic_delay_timer.h new file mode 100644 index 0000000..1450162 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/generic_delay_timer.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GENERIC_DELAY_TIMER_H__ +#define __GENERIC_DELAY_TIMER_H__ + +#include + +void generic_delay_timer_init_args(uint32_t mult, uint32_t div); + +void generic_delay_timer_init(void); + +#endif /* __GENERIC_DELAY_TIMER_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/gpio.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/gpio.h new file mode 100644 index 0000000..633b3f6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/gpio.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#define GPIO_DIR_OUT 0 +#define GPIO_DIR_IN 1 + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 + +#define GPIO_PULL_NONE 0 +#define GPIO_PULL_UP 1 +#define GPIO_PULL_DOWN 2 + +typedef struct gpio_ops { + int (*get_direction)(int gpio); + void (*set_direction)(int gpio, int direction); + int (*get_value)(int gpio); + void (*set_value)(int gpio, int value); + void (*set_pull)(int gpio, int pull); + int (*get_pull)(int gpio); +} gpio_ops_t; + +int gpio_get_direction(int gpio); +void gpio_set_direction(int gpio, int direction); +int gpio_get_value(int gpio); +void gpio_set_value(int gpio, int value); +void gpio_set_pull(int gpio, int pull); +int gpio_get_pull(int gpio); +void gpio_init(const gpio_ops_t *ops); + +#endif /* __GPIO_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_block.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_block.h new file mode 100644 index 0000000..ebf43cd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_block.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_BLOCK_H__ +#define __IO_BLOCK_H__ + +#include + +/* block devices ops */ +typedef struct io_block_ops { + size_t (*read)(int lba, uintptr_t buf, size_t size); + size_t (*write)(int lba, const uintptr_t buf, size_t size); +} io_block_ops_t; + +typedef struct io_block_dev_spec { + io_block_spec_t buffer; + io_block_ops_t ops; + size_t block_size; +} io_block_dev_spec_t; + +struct io_dev_connector; + +int register_io_dev_block(const struct io_dev_connector **dev_con); + +#endif /* __IO_BLOCK_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_driver.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_driver.h new file mode 100644 index 0000000..adb38b0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_driver.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_DRIVER_H__ +#define __IO_DRIVER_H__ + +#include +#include + + +/* Generic IO entity structure,representing an accessible IO construct on the + * device, such as a file */ +typedef struct io_entity { + struct io_dev_info *dev_handle; + uintptr_t info; +} io_entity_t; + + +/* Device info structure, providing device-specific functions and a means of + * adding driver-specific state */ +typedef struct io_dev_info { + const struct io_dev_funcs *funcs; + uintptr_t info; +} io_dev_info_t; + + +/* Structure used to create a connection to a type of device */ +typedef struct io_dev_connector { + /* dev_open opens a connection to a particular device driver */ + int (*dev_open)(const uintptr_t dev_spec, io_dev_info_t **dev_info); +} io_dev_connector_t; + + +/* Structure to hold device driver function pointers */ +typedef struct io_dev_funcs { + io_type_t (*type)(void); + int (*open)(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); + int (*seek)(io_entity_t *entity, int mode, ssize_t offset); + int (*size)(io_entity_t *entity, size_t *length); + int (*read)(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read); + int (*write)(io_entity_t *entity, const uintptr_t buffer, + size_t length, size_t *length_written); + int (*close)(io_entity_t *entity); + int (*dev_init)(io_dev_info_t *dev_info, const uintptr_t init_params); + int (*dev_close)(io_dev_info_t *dev_info); +} io_dev_funcs_t; + + +/* Operations intended to be performed during platform initialisation */ + +/* Register an IO device */ +int io_register_device(const io_dev_info_t *dev_info); + +#endif /* __IO_DRIVER_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_dummy.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_dummy.h new file mode 100644 index 0000000..c7ee454 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_dummy.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_DUMMY_H__ +#define __IO_DUMMY_H__ + +int register_io_dev_dummy(const struct io_dev_connector **dev_con); + +#endif /* __IO_DUMMY_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_fip.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_fip.h new file mode 100644 index 0000000..90b2fd0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_fip.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2014 ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_FIP_H__ +#define __IO_FIP_H__ + +struct io_dev_connector; + +int register_io_dev_fip(const struct io_dev_connector **dev_con); + +#endif /* __IO_FIP_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_memmap.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_memmap.h new file mode 100644 index 0000000..7ee60fe --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_memmap.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_MEMMAP_H__ +#define __IO_MEMMAP_H__ + +struct io_dev_connector; + +int register_io_dev_memmap(const struct io_dev_connector **dev_con); + +#endif /* __IO_MEMMAP_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_semihosting.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_semihosting.h new file mode 100644 index 0000000..8902a6f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_semihosting.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_SH_H__ +#define __IO_SH_H__ + +struct io_dev_connector; + +int register_io_dev_sh(const struct io_dev_connector **dev_con); + +#endif /* __IO_SH_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_storage.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_storage.h new file mode 100644 index 0000000..1b3028a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/io/io_storage.h @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __IO_H__ +#define __IO_H__ + +#include +#include +#include /* For ssize_t */ +#include + + +/* Device type which can be used to enable policy decisions about which device + * to access */ +typedef enum { + IO_TYPE_INVALID, + IO_TYPE_SEMIHOSTING, + IO_TYPE_MEMMAP, + IO_TYPE_DUMMY, + IO_TYPE_FIRMWARE_IMAGE_PACKAGE, + IO_TYPE_BLOCK, + IO_TYPE_MAX +} io_type_t; + + +/* Modes used when seeking data on a supported device */ +typedef enum { + IO_SEEK_INVALID, + IO_SEEK_SET, + IO_SEEK_END, + IO_SEEK_CUR, + IO_SEEK_MAX +} io_seek_mode_t; + + +/* Connector type, providing a means of identifying a device to open */ +struct io_dev_connector; + + +/* File specification - used to refer to data on a device supporting file-like + * entities */ +typedef struct io_file_spec { + const char *path; + unsigned int mode; +} io_file_spec_t; + +/* UUID specification - used to refer to data accessed using UUIDs (i.e. FIP + * images) */ +typedef struct io_uuid_spec { + const uuid_t uuid; +} io_uuid_spec_t; + +/* Block specification - used to refer to data on a device supporting + * block-like entities */ +typedef struct io_block_spec { + size_t offset; + size_t length; +} io_block_spec_t; + + +/* Access modes used when accessing data on a device */ +#define IO_MODE_INVALID (0) +#define IO_MODE_RO (1 << 0) +#define IO_MODE_RW (1 << 1) + + +/* Open a connection to a device */ +int io_dev_open(const struct io_dev_connector *dev_con, + const uintptr_t dev_spec, + uintptr_t *dev_handle); + + +/* Initialise a device explicitly - to permit lazy initialisation or + * re-initialisation */ +int io_dev_init(uintptr_t dev_handle, const uintptr_t init_params); + +/* TODO: Consider whether an explicit "shutdown" API should be included */ + +/* Close a connection to a device */ +int io_dev_close(uintptr_t dev_handle); + + +/* Synchronous operations */ +int io_open(uintptr_t dev_handle, const uintptr_t spec, uintptr_t *handle); + +int io_seek(uintptr_t handle, io_seek_mode_t mode, ssize_t offset); + +int io_size(uintptr_t handle, size_t *length); + +int io_read(uintptr_t handle, uintptr_t buffer, size_t length, + size_t *length_read); + +int io_write(uintptr_t handle, const uintptr_t buffer, size_t length, + size_t *length_written); + +int io_close(uintptr_t handle); + + +#endif /* __IO_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/ti/uart/uart_16550.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/ti/uart/uart_16550.h new file mode 100644 index 0000000..2c814ef --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/drivers/ti/uart/uart_16550.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __UART_16550_H__ +#define __UART_16550_H__ + +/* UART16550 Registers */ +#define UARTTX 0x0 +#define UARTRX 0x0 +#define UARTDLL 0x0 +#define UARTIER 0x4 +#define UARTDLLM 0x4 +#define UARTIIR 0x8 +#define UARTFCR 0x8 +#define UARTLCR 0xc +#define UARTMCR 0x10 +#define UARTLSR 0x14 +#define UARTMSR 0x18 +#define UARTSPR 0x1c +#define UARTCSR 0x20 +#define UARTRXFIFOCFG 0x24 +#define UARTMIE 0x28 +#define UARTVNDR 0x2c +#define UARTASR 0x3c + +/* FIFO Control Register bits */ +#define UARTFCR_FIFOMD_16450 (0 << 6) +#define UARTFCR_FIFOMD_16550 (1 << 6) +#define UARTFCR_RXTRIG_1 (0 << 6) +#define UARTFCR_RXTRIG_4 (1 << 6) +#define UARTFCR_RXTRIG_8 (2 << 6) +#define UARTFCR_RXTRIG_16 (3 << 6) +#define UARTFCR_TXTRIG_1 (0 << 4) +#define UARTFCR_TXTRIG_4 (1 << 4) +#define UARTFCR_TXTRIG_8 (2 << 4) +#define UARTFCR_TXTRIG_16 (3 << 4) +#define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */ +#define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */ +#define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */ +#define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */ + +/* Line Control Register bits */ +#define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */ +#define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */ +#define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */ +#define UARTLCR_EVEN (1 << 4) /* Even Parity Format */ +#define UARTLCR_PAR (1 << 3) /* Parity */ +#define UARTLCR_STOP (1 << 2) /* Stop Bit */ +#define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */ +#define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */ +#define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */ +#define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */ + +/* Line Status Register bits */ +#define UARTLSR_RXFIFOEMT (1 << 9) /* Rx Fifo Empty */ +#define UARTLSR_TXFIFOFULL (1 << 8) /* Tx Fifo Full */ +#define UARTLSR_RXFIFOERR (1 << 7) /* Rx Fifo Error */ +#define UARTLSR_TEMT (1 << 6) /* Tx Shift Register Empty */ +#define UARTLSR_THRE (1 << 5) /* Tx Holding Register Empty */ +#define UARTLSR_BRK (1 << 4) /* Break Condition Detected */ +#define UARTLSR_FERR (1 << 3) /* Framing Error */ +#define UARTLSR_PERR (1 << 3) /* Parity Error */ +#define UARTLSR_OVRF (1 << 2) /* Rx Overrun Error */ +#define UARTLSR_RDR (1 << 2) /* Rx Data Ready */ + +#endif /* __UART_16550_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch32/arch.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch32/arch.h new file mode 100644 index 0000000..aba15df --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch32/arch.h @@ -0,0 +1,411 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_H__ +#define __ARCH_H__ + +/******************************************************************************* + * MIDR bit definitions + ******************************************************************************/ +#define MIDR_IMPL_MASK 0xff +#define MIDR_IMPL_SHIFT 24 +#define MIDR_VAR_SHIFT 20 +#define MIDR_VAR_BITS 4 +#define MIDR_REV_SHIFT 0 +#define MIDR_REV_BITS 4 +#define MIDR_PN_MASK 0xfff +#define MIDR_PN_SHIFT 4 + +/******************************************************************************* + * MPIDR macros + ******************************************************************************/ +#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK +#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) +#define MPIDR_AFFINITY_BITS 8 +#define MPIDR_AFFLVL_MASK 0xff +#define MPIDR_AFFLVL_SHIFT 3 +#define MPIDR_AFF0_SHIFT 0 +#define MPIDR_AFF1_SHIFT 8 +#define MPIDR_AFF2_SHIFT 16 +#define MPIDR_AFFINITY_MASK 0x00ffffff +#define MPIDR_AFFLVL0 0 +#define MPIDR_AFFLVL1 1 +#define MPIDR_AFFLVL2 2 + +#define MPIDR_AFFLVL0_VAL(mpidr) \ + (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL1_VAL(mpidr) \ + (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL2_VAL(mpidr) \ + (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) + +/* + * The MPIDR_MAX_AFFLVL count starts from 0. Take care to + * add one while using this macro to define array sizes. + */ +#define MPIDR_MAX_AFFLVL 2 + +/* Data Cache set/way op type defines */ +#define DC_OP_ISW 0x0 +#define DC_OP_CISW 0x1 +#define DC_OP_CSW 0x2 + +/******************************************************************************* + * Generic timer memory mapped registers & offsets + ******************************************************************************/ +#define CNTCR_OFF 0x000 +#define CNTFID_OFF 0x020 + +#define CNTCR_EN (1 << 0) +#define CNTCR_HDBG (1 << 1) +#define CNTCR_FCREQ(x) ((x) << 8) + +/******************************************************************************* + * System register bit definitions + ******************************************************************************/ +/* CLIDR definitions */ +#define LOUIS_SHIFT 21 +#define LOC_SHIFT 24 +#define CLIDR_FIELD_WIDTH 3 + +/* CSSELR definitions */ +#define LEVEL_SHIFT 1 + +/* ID_PFR1 definitions */ +#define ID_PFR1_VIRTEXT_SHIFT 12 +#define ID_PFR1_VIRTEXT_MASK 0xf +#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ + & ID_PFR1_VIRTEXT_MASK) +#define ID_PFR1_GIC_SHIFT 28 +#define ID_PFR1_GIC_MASK 0xf + +/* SCTLR definitions */ +#define SCTLR_RES1 ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \ + (1 << 3) | SCTLR_CP15BEN_BIT | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT) +#define SCTLR_M_BIT (1 << 0) +#define SCTLR_A_BIT (1 << 1) +#define SCTLR_C_BIT (1 << 2) +#define SCTLR_CP15BEN_BIT (1 << 5) +#define SCTLR_ITD_BIT (1 << 7) +#define SCTLR_I_BIT (1 << 12) +#define SCTLR_V_BIT (1 << 13) +#define SCTLR_NTWI_BIT (1 << 16) +#define SCTLR_NTWE_BIT (1 << 18) +#define SCTLR_WXN_BIT (1 << 19) +#define SCTLR_UWXN_BIT (1 << 20) +#define SCTLR_EE_BIT (1 << 25) +#define SCTLR_TRE_BIT (1 << 28) +#define SCTLR_AFE_BIT (1 << 29) +#define SCTLR_TE_BIT (1 << 30) + +/* HSCTLR definitions */ +#define HSCTLR_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) \ + | (1 << 18) | (1 << 16) | (1 << 11) | (1 << 4) \ + | (1 << 3) | HSCTLR_CP15BEN_BIT) +#define HSCTLR_M_BIT (1 << 0) +#define HSCTLR_A_BIT (1 << 1) +#define HSCTLR_C_BIT (1 << 2) +#define HSCTLR_CP15BEN_BIT (1 << 5) +#define HSCTLR_ITD_BIT (1 << 7) +#define HSCTLR_SED_BIT (1 << 8) +#define HSCTLR_I_BIT (1 << 12) +#define HSCTLR_WXN_BIT (1 << 19) +#define HSCTLR_EE_BIT (1 << 25) +#define HSCTLR_TE_BIT (1 << 30) + +/* CPACR definitions */ +#define CPACR_FPEN(x) ((x) << 20) +#define CPACR_FP_TRAP_PL0 0x1 +#define CPACR_FP_TRAP_ALL 0x2 +#define CPACR_FP_TRAP_NONE 0x3 + +/* SCR definitions */ +#define SCR_TWE_BIT (1 << 13) +#define SCR_TWI_BIT (1 << 12) +#define SCR_SIF_BIT (1 << 9) +#define SCR_HCE_BIT (1 << 8) +#define SCR_SCD_BIT (1 << 7) +#define SCR_NET_BIT (1 << 6) +#define SCR_AW_BIT (1 << 5) +#define SCR_FW_BIT (1 << 4) +#define SCR_EA_BIT (1 << 3) +#define SCR_FIQ_BIT (1 << 2) +#define SCR_IRQ_BIT (1 << 1) +#define SCR_NS_BIT (1 << 0) +#define SCR_VALID_BIT_MASK 0x33ff + +#define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT) + +/* HCR definitions */ +#define HCR_AMO_BIT (1 << 5) +#define HCR_IMO_BIT (1 << 4) +#define HCR_FMO_BIT (1 << 3) + +/* CNTHCTL definitions */ +#define EVNTEN_BIT (1 << 2) +#define PL1PCEN_BIT (1 << 1) +#define PL1PCTEN_BIT (1 << 0) + +/* CNTKCTL definitions */ +#define PL0PTEN_BIT (1 << 9) +#define PL0VTEN_BIT (1 << 8) +#define PL0PCTEN_BIT (1 << 0) +#define PL0VCTEN_BIT (1 << 1) +#define EVNTEN_BIT (1 << 2) +#define EVNTDIR_BIT (1 << 3) +#define EVNTI_SHIFT 4 +#define EVNTI_MASK 0xf + +/* HCPTR definitions */ +#define TCPAC_BIT (1 << 31) +#define TTA_BIT (1 << 20) +#define TCP11_BIT (1 << 10) +#define TCP10_BIT (1 << 10) + +/* NASCR definitions */ +#define NSASEDIS_BIT (1 << 15) +#define NSTRCDIS_BIT (1 << 20) +#define NASCR_CP11_BIT (1 << 11) +#define NASCR_CP10_BIT (1 << 10) + +/* CPACR definitions */ +#define ASEDIS_BIT (1 << 31) +#define TRCDIS_BIT (1 << 28) +#define CPACR_CP11_SHIFT 22 +#define CPACR_CP10_SHIFT 20 +#define CPACR_ENABLE_FP_ACCESS (0x3 << CPACR_CP11_SHIFT |\ + 0x3 << CPACR_CP10_SHIFT) + +/* FPEXC definitions */ +#define FPEXC_EN_BIT (1 << 30) + +/* SPSR/CPSR definitions */ +#define SPSR_FIQ_BIT (1 << 0) +#define SPSR_IRQ_BIT (1 << 1) +#define SPSR_ABT_BIT (1 << 2) +#define SPSR_AIF_SHIFT 6 +#define SPSR_AIF_MASK 0x7 + +#define SPSR_E_SHIFT 9 +#define SPSR_E_MASK 0x1 +#define SPSR_E_LITTLE 0 +#define SPSR_E_BIG 1 + +#define SPSR_T_SHIFT 5 +#define SPSR_T_MASK 0x1 +#define SPSR_T_ARM 0 +#define SPSR_T_THUMB 1 + +#define SPSR_MODE_SHIFT 0 +#define SPSR_MODE_MASK 0x7 + + +#define DISABLE_ALL_EXCEPTIONS \ + (SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) + +/* + * TTBCR definitions + */ +/* The ARM Trusted Firmware uses the long descriptor format */ +#define TTBCR_EAE_BIT (1 << 31) + +#define TTBCR_SH1_NON_SHAREABLE (0x0 << 28) +#define TTBCR_SH1_OUTER_SHAREABLE (0x2 << 28) +#define TTBCR_SH1_INNER_SHAREABLE (0x3 << 28) + +#define TTBCR_RGN1_OUTER_NC (0x0 << 26) +#define TTBCR_RGN1_OUTER_WBA (0x1 << 26) +#define TTBCR_RGN1_OUTER_WT (0x2 << 26) +#define TTBCR_RGN1_OUTER_WBNA (0x3 << 26) + +#define TTBCR_RGN1_INNER_NC (0x0 << 24) +#define TTBCR_RGN1_INNER_WBA (0x1 << 24) +#define TTBCR_RGN1_INNER_WT (0x2 << 24) +#define TTBCR_RGN1_INNER_WBNA (0x3 << 24) + +#define TTBCR_EPD1_BIT (1 << 23) +#define TTBCR_A1_BIT (1 << 22) + +#define TTBCR_T1SZ_SHIFT 16 +#define TTBCR_T1SZ_MASK (0x7) +#define TTBCR_TxSZ_MIN 0 +#define TTBCR_TxSZ_MAX 7 + +#define TTBCR_SH0_NON_SHAREABLE (0x0 << 12) +#define TTBCR_SH0_OUTER_SHAREABLE (0x2 << 12) +#define TTBCR_SH0_INNER_SHAREABLE (0x3 << 12) + +#define TTBCR_RGN0_OUTER_NC (0x0 << 10) +#define TTBCR_RGN0_OUTER_WBA (0x1 << 10) +#define TTBCR_RGN0_OUTER_WT (0x2 << 10) +#define TTBCR_RGN0_OUTER_WBNA (0x3 << 10) + +#define TTBCR_RGN0_INNER_NC (0x0 << 8) +#define TTBCR_RGN0_INNER_WBA (0x1 << 8) +#define TTBCR_RGN0_INNER_WT (0x2 << 8) +#define TTBCR_RGN0_INNER_WBNA (0x3 << 8) + +#define TTBCR_EPD0_BIT (1 << 7) +#define TTBCR_T0SZ_SHIFT 0 +#define TTBCR_T0SZ_MASK (0x7) + +#define MODE_RW_SHIFT 0x4 +#define MODE_RW_MASK 0x1 +#define MODE_RW_32 0x1 + +#define MODE32_SHIFT 0 +#define MODE32_MASK 0x1f +#define MODE32_usr 0x10 +#define MODE32_fiq 0x11 +#define MODE32_irq 0x12 +#define MODE32_svc 0x13 +#define MODE32_mon 0x16 +#define MODE32_abt 0x17 +#define MODE32_hyp 0x1a +#define MODE32_und 0x1b +#define MODE32_sys 0x1f + +#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) + +#define SPSR_MODE32(mode, isa, endian, aif) \ + (MODE_RW_32 << MODE_RW_SHIFT | \ + ((mode) & MODE32_MASK) << MODE32_SHIFT | \ + ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ + ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ + ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) + +/* + * CTR definitions + */ +#define CTR_CWG_SHIFT 24 +#define CTR_CWG_MASK 0xf +#define CTR_ERG_SHIFT 20 +#define CTR_ERG_MASK 0xf +#define CTR_DMINLINE_SHIFT 16 +#define CTR_DMINLINE_WIDTH 4 +#define CTR_DMINLINE_MASK ((1 << 4) - 1) +#define CTR_L1IP_SHIFT 14 +#define CTR_L1IP_MASK 0x3 +#define CTR_IMINLINE_SHIFT 0 +#define CTR_IMINLINE_MASK 0xf + +#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */ + +/******************************************************************************* + * Definitions of register offsets and fields in the CNTCTLBase Frame of the + * system level implementation of the Generic Timer. + ******************************************************************************/ +#define CNTNSAR 0x4 +#define CNTNSAR_NS_SHIFT(x) (x) + +#define CNTACR_BASE(x) (0x40 + ((x) << 2)) +#define CNTACR_RPCT_SHIFT 0x0 +#define CNTACR_RVCT_SHIFT 0x1 +#define CNTACR_RFRQ_SHIFT 0x2 +#define CNTACR_RVOFF_SHIFT 0x3 +#define CNTACR_RWVT_SHIFT 0x4 +#define CNTACR_RWPT_SHIFT 0x5 + +/* MAIR macros */ +#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << 3)) +#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - 3) << 3)) + +/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */ +#define SCR p15, 0, c1, c1, 0 +#define SCTLR p15, 0, c1, c0, 0 +#define MPIDR p15, 0, c0, c0, 5 +#define MIDR p15, 0, c0, c0, 0 +#define VBAR p15, 0, c12, c0, 0 +#define MVBAR p15, 0, c12, c0, 1 +#define NSACR p15, 0, c1, c1, 2 +#define CPACR p15, 0, c1, c0, 2 +#define DCCIMVAC p15, 0, c7, c14, 1 +#define DCCMVAC p15, 0, c7, c10, 1 +#define DCIMVAC p15, 0, c7, c6, 1 +#define DCCISW p15, 0, c7, c14, 2 +#define DCCSW p15, 0, c7, c10, 2 +#define DCISW p15, 0, c7, c6, 2 +#define CTR p15, 0, c0, c0, 1 +#define CNTFRQ p15, 0, c14, c0, 0 +#define ID_PFR1 p15, 0, c0, c1, 1 +#define MAIR0 p15, 0, c10, c2, 0 +#define MAIR1 p15, 0, c10, c2, 1 +#define TTBCR p15, 0, c2, c0, 2 +#define TTBR0 p15, 0, c2, c0, 0 +#define TTBR1 p15, 0, c2, c0, 1 +#define TLBIALL p15, 0, c8, c7, 0 +#define TLBIALLIS p15, 0, c8, c3, 0 +#define TLBIMVA p15, 0, c8, c7, 1 +#define TLBIMVAA p15, 0, c8, c7, 3 +#define HSCTLR p15, 4, c1, c0, 0 +#define HCR p15, 4, c1, c1, 0 +#define HCPTR p15, 4, c1, c1, 2 +#define CNTHCTL p15, 4, c14, c1, 0 +#define VPIDR p15, 4, c0, c0, 0 +#define VMPIDR p15, 4, c0, c0, 5 +#define ISR p15, 0, c12, c1, 0 +#define CLIDR p15, 1, c0, c0, 1 +#define CSSELR p15, 2, c0, c0, 0 +#define CCSIDR p15, 1, c0, c0, 0 + +/* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ +#define ICC_IAR1 p15, 0, c12, c12, 0 +#define ICC_IAR0 p15, 0, c12, c8, 0 +#define ICC_EOIR1 p15, 0, c12, c12, 1 +#define ICC_EOIR0 p15, 0, c12, c8, 1 +#define ICC_HPPIR1 p15, 0, c12, c12, 2 +#define ICC_HPPIR0 p15, 0, c12, c8, 2 +#define ICC_BPR1 p15, 0, c12, c12, 3 +#define ICC_BPR0 p15, 0, c12, c8, 3 +#define ICC_DIR p15, 0, c12, c11, 1 +#define ICC_PMR p15, 0, c4, c6, 0 +#define ICC_RPR p15, 0, c12, c11, 3 +#define ICC_CTLR p15, 0, c12, c12, 4 +#define ICC_MCTLR p15, 6, c12, c12, 4 +#define ICC_SRE p15, 0, c12, c12, 5 +#define ICC_HSRE p15, 4, c12, c9, 5 +#define ICC_MSRE p15, 6, c12, c12, 5 +#define ICC_IGRPEN0 p15, 0, c12, c12, 6 +#define ICC_IGRPEN1 p15, 0, c12, c12, 7 +#define ICC_MGRPEN1 p15, 6, c12, c12, 7 + +/* 64 bit system register defines The format is: coproc, opt1, CRm */ +#define TTBR0_64 p15, 0, c2 +#define TTBR1_64 p15, 1, c2 +#define CNTVOFF_64 p15, 4, c14 +#define VTTBR_64 p15, 6, c2 +#define CNTPCT_64 p15, 0, c14 + +/* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */ +#define ICC_SGI1R_EL1_64 p15, 0, c12 +#define ICC_ASGI1R_EL1_64 p15, 1, c12 +#define ICC_SGI0R_EL1_64 p15, 2, c12 + +#endif /* __ARCH_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch32/arch_helpers.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch32/arch_helpers.h new file mode 100644 index 0000000..3b4349c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch32/arch_helpers.h @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_HELPERS_H__ +#define __ARCH_HELPERS_H__ + +#include /* for additional register definitions */ +#include +#include + +/********************************************************************** + * Macros which create inline functions to read or write CPU system + * registers + *********************************************************************/ + +#define _DEFINE_COPROCR_WRITE_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \ +static inline void write_## _name(u_register_t v) \ +{ \ + __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ +} + +#define _DEFINE_COPROCR_READ_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \ +static inline u_register_t read_ ## _name(void) \ +{ \ + u_register_t v; \ + __asm__ volatile ("mrc "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : "=r" (v));\ + return v; \ +} + +/* + * The undocumented %Q and %R extended asm are used to implemented the below + * 64 bit `mrrc` and `mcrr` instructions. It works only on Little Endian + * systems for GCC versions < 4.6. Above GCC 4.6, both Little Endian and + * Big Endian systems generate the right instruction encoding. + */ +#if !(__GNUC__ > (4) || __GNUC__ == (4) && __GNUC_MINOR__ >= (6)) +#error "GCC 4.6 or above is required to build AArch32 Trusted Firmware" +#endif + +#define _DEFINE_COPROCR_WRITE_FUNC_64(_name, coproc, opc1, CRm) \ +static inline void write64_## _name(uint64_t v) \ +{ \ + __asm__ volatile ("mcrr "#coproc","#opc1", %Q0, %R0,"#CRm : : "r" (v));\ +} + +#define _DEFINE_COPROCR_READ_FUNC_64(_name, coproc, opc1, CRm) \ +static inline uint64_t read64_## _name(void) \ +{ uint64_t v; \ + __asm__ volatile ("mrrc "#coproc","#opc1", %Q0, %R0,"#CRm : "=r" (v));\ + return v; \ +} + +#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ +static inline u_register_t read_ ## _name(void) \ +{ \ + u_register_t v; \ + __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ + return v; \ +} + +#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ +static inline void write_ ## _name(u_register_t v) \ +{ \ + __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ +} + +#define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \ +static inline void write_ ## _name(const u_register_t v) \ +{ \ + __asm__ volatile ("msr " #_reg_name ", %0" : : "i" (v)); \ +} + +/* Define read function for coproc register */ +#define DEFINE_COPROCR_READ_FUNC(_name, ...) \ + _DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__) + +/* Define read & write function for coproc register */ +#define DEFINE_COPROCR_RW_FUNCS(_name, ...) \ + _DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__) \ + _DEFINE_COPROCR_WRITE_FUNC(_name, __VA_ARGS__) + +/* Define 64 bit read function for coproc register */ +#define DEFINE_COPROCR_READ_FUNC_64(_name, ...) \ + _DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__) + +/* Define 64 bit read & write function for coproc register */ +#define DEFINE_COPROCR_RW_FUNCS_64(_name, ...) \ + _DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__) \ + _DEFINE_COPROCR_WRITE_FUNC_64(_name, __VA_ARGS__) + +/* Define read & write function for system register */ +#define DEFINE_SYSREG_RW_FUNCS(_name) \ + _DEFINE_SYSREG_READ_FUNC(_name, _name) \ + _DEFINE_SYSREG_WRITE_FUNC(_name, _name) + +/********************************************************************** + * Macros to create inline functions for tlbi operations + *********************************************************************/ + +#define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ +static inline void tlbi##_op(void) \ +{ \ + u_register_t v = 0; \ + __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ +} + +#define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ +static inline void tlbi##_op(u_register_t v) \ +{ \ + __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ +} + +/* Define function for simple TLBI operation */ +#define DEFINE_TLBIOP_FUNC(_op, ...) \ + _DEFINE_TLBIOP_FUNC(_op, __VA_ARGS__) + +/* Define function for TLBI operation with register parameter */ +#define DEFINE_TLBIOP_PARAM_FUNC(_op, ...) \ + _DEFINE_TLBIOP_PARAM_FUNC(_op, __VA_ARGS__) + +/********************************************************************** + * Macros to create inline functions for DC operations + *********************************************************************/ +#define _DEFINE_DCOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ +static inline void dc##_op(u_register_t v) \ +{ \ + __asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ +} + +/* Define function for DC operation with register parameter */ +#define DEFINE_DCOP_PARAM_FUNC(_op, ...) \ + _DEFINE_DCOP_PARAM_FUNC(_op, __VA_ARGS__) + +/********************************************************************** + * Macros to create inline functions for system instructions + *********************************************************************/ + /* Define function for simple system instruction */ +#define DEFINE_SYSOP_FUNC(_op) \ +static inline void _op(void) \ +{ \ + __asm__ (#_op); \ +} + + +/* Define function for system instruction with type specifier */ +#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ +static inline void _op ## _type(void) \ +{ \ + __asm__ (#_op " " #_type); \ +} + +/* Define function for system instruction with register parameter */ +#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ +static inline void _op ## _type(u_register_t v) \ +{ \ + __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ +} + +void flush_dcache_range(uintptr_t addr, size_t size); +void clean_dcache_range(uintptr_t addr, size_t size); +void inv_dcache_range(uintptr_t addr, size_t size); + +void disable_mmu_secure(void); +void disable_mmu_icache_secure(void); + +DEFINE_SYSOP_FUNC(wfi) +DEFINE_SYSOP_FUNC(wfe) +DEFINE_SYSOP_FUNC(sev) +DEFINE_SYSOP_TYPE_FUNC(dsb, sy) +DEFINE_SYSOP_TYPE_FUNC(dmb, sy) +DEFINE_SYSOP_TYPE_FUNC(dsb, ish) +DEFINE_SYSOP_TYPE_FUNC(dmb, ish) +DEFINE_SYSOP_FUNC(isb) + +void __dead2 smc(uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3, + uint32_t r4, uint32_t r5, uint32_t r6, uint32_t r7); + +DEFINE_SYSREG_RW_FUNCS(spsr) +DEFINE_SYSREG_RW_FUNCS(cpsr) + +/******************************************************************************* + * System register accessor prototypes + ******************************************************************************/ +DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR) +DEFINE_COPROCR_READ_FUNC(midr, MIDR) +DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1) +DEFINE_COPROCR_READ_FUNC(isr, ISR) +DEFINE_COPROCR_READ_FUNC(clidr, CLIDR) +DEFINE_COPROCR_READ_FUNC_64(cntpct, CNTPCT_64) + +DEFINE_COPROCR_RW_FUNCS(scr, SCR) +DEFINE_COPROCR_RW_FUNCS(ctr, CTR) +DEFINE_COPROCR_RW_FUNCS(sctlr, SCTLR) +DEFINE_COPROCR_RW_FUNCS(hsctlr, HSCTLR) +DEFINE_COPROCR_RW_FUNCS(hcr, HCR) +DEFINE_COPROCR_RW_FUNCS(hcptr, HCPTR) +DEFINE_COPROCR_RW_FUNCS(cntfrq, CNTFRQ) +DEFINE_COPROCR_RW_FUNCS(cnthctl, CNTHCTL) +DEFINE_COPROCR_RW_FUNCS(mair0, MAIR0) +DEFINE_COPROCR_RW_FUNCS(mair1, MAIR1) +DEFINE_COPROCR_RW_FUNCS(ttbcr, TTBCR) +DEFINE_COPROCR_RW_FUNCS(ttbr0, TTBR0) +DEFINE_COPROCR_RW_FUNCS_64(ttbr0, TTBR0_64) +DEFINE_COPROCR_RW_FUNCS(ttbr1, TTBR1) +DEFINE_COPROCR_RW_FUNCS(vpidr, VPIDR) +DEFINE_COPROCR_RW_FUNCS(vmpidr, VMPIDR) +DEFINE_COPROCR_RW_FUNCS_64(vttbr, VTTBR_64) +DEFINE_COPROCR_RW_FUNCS_64(ttbr1, TTBR1_64) +DEFINE_COPROCR_RW_FUNCS_64(cntvoff, CNTVOFF_64) +DEFINE_COPROCR_RW_FUNCS(csselr, CSSELR) + +DEFINE_COPROCR_RW_FUNCS(icc_sre_el1, ICC_SRE) +DEFINE_COPROCR_RW_FUNCS(icc_sre_el2, ICC_HSRE) +DEFINE_COPROCR_RW_FUNCS(icc_sre_el3, ICC_MSRE) +DEFINE_COPROCR_RW_FUNCS(icc_pmr_el1, ICC_PMR) +DEFINE_COPROCR_RW_FUNCS(icc_igrpen1_el3, ICC_MGRPEN1) +DEFINE_COPROCR_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0) +DEFINE_COPROCR_RW_FUNCS(icc_hppir0_el1, ICC_HPPIR0) +DEFINE_COPROCR_RW_FUNCS(icc_hppir1_el1, ICC_HPPIR1) +DEFINE_COPROCR_RW_FUNCS(icc_iar0_el1, ICC_IAR0) +DEFINE_COPROCR_RW_FUNCS(icc_iar1_el1, ICC_IAR1) +DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0) +DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1) + +/* + * TLBI operation prototypes + */ +DEFINE_TLBIOP_FUNC(all, TLBIALL) +DEFINE_TLBIOP_FUNC(allis, TLBIALLIS) +DEFINE_TLBIOP_PARAM_FUNC(mva, TLBIMVA) +DEFINE_TLBIOP_PARAM_FUNC(mvaa, TLBIMVAA) + +/* + * DC operation prototypes + */ +DEFINE_DCOP_PARAM_FUNC(civac, DCCIMVAC) +DEFINE_DCOP_PARAM_FUNC(ivac, DCIMVAC) +DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC) + +/* Previously defined accessor functions with incomplete register names */ +#define dsb() dsbsy() + +#define IS_IN_SECURE() \ + (GET_NS_BIT(read_scr()) == 0) + + /* + * If EL3 is AArch32, then secure PL1 and monitor mode correspond to EL3 + */ +#define IS_IN_EL3() \ + ((GET_M32(read_cpsr()) == MODE32_mon) || \ + (IS_IN_SECURE() && (GET_M32(read_cpsr()) != MODE32_usr))) + +/* Macros for compatibility with AArch64 system registers */ +#define read_mpidr_el1() read_mpidr() + +#define read_scr_el3() read_scr() +#define write_scr_el3(_v) write_scr(_v) + +#define read_hcr_el2() read_hcr() +#define write_hcr_el2(_v) write_hcr(_v) + +#define read_cpacr_el1() read_cpacr() +#define write_cpacr_el1(_v) write_cpacr(_v) + +#define read_cntfrq_el0() read_cntfrq() +#define write_cntfrq_el0(_v) write_cntfrq(_v) +#define read_isr_el1() read_isr() + +#define read_cntpct_el0() read64_cntpct() + +#define read_ctr_el0() read_ctr() + +#endif /* __ARCH_HELPERS_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch32/smcc_helpers.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch32/smcc_helpers.h new file mode 100644 index 0000000..5aeca22 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch32/smcc_helpers.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SMCC_HELPERS_H__ +#define __SMCC_HELPERS_H__ + +#include + +/* These are offsets to registers in smc_ctx_t */ +#define SMC_CTX_GPREG_R0 0x0 +#define SMC_CTX_GPREG_R1 0x4 +#define SMC_CTX_GPREG_R2 0x8 +#define SMC_CTX_GPREG_R3 0xC +#define SMC_CTX_GPREG_R4 0x10 +#define SMC_CTX_SP_USR 0x34 +#define SMC_CTX_SPSR_MON 0x78 +#define SMC_CTX_LR_MON 0x7C +#define SMC_CTX_SIZE 0x80 + +#ifndef __ASSEMBLY__ +#include +#include + +/* + * The generic structure to save arguments and callee saved registers during + * an SMC. Also this structure is used to store the result return values after + * the completion of SMC service. + */ +typedef struct smc_ctx { + u_register_t r0; + u_register_t r1; + u_register_t r2; + u_register_t r3; + u_register_t r4; + u_register_t r5; + u_register_t r6; + u_register_t r7; + u_register_t r8; + u_register_t r9; + u_register_t r10; + u_register_t r11; + u_register_t r12; + /* spsr_usr doesn't exist */ + u_register_t sp_usr; + u_register_t lr_usr; + u_register_t spsr_irq; + u_register_t sp_irq; + u_register_t lr_irq; + u_register_t spsr_fiq; + u_register_t sp_fiq; + u_register_t lr_fiq; + u_register_t spsr_svc; + u_register_t sp_svc; + u_register_t lr_svc; + u_register_t spsr_abt; + u_register_t sp_abt; + u_register_t lr_abt; + u_register_t spsr_und; + u_register_t sp_und; + u_register_t lr_und; + u_register_t spsr_mon; + /* No need to save 'sp_mon' because we are already in monitor mode */ + u_register_t lr_mon; +} smc_ctx_t; + +/* + * Compile time assertions related to the 'smc_context' structure to + * ensure that the assembler and the compiler view of the offsets of + * the structure members is the same. + */ +CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0), \ + assert_smc_ctx_greg_r0_offset_mismatch); +CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1), \ + assert_smc_ctx_greg_r1_offset_mismatch); +CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2), \ + assert_smc_ctx_greg_r2_offset_mismatch); +CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3), \ + assert_smc_ctx_greg_r3_offset_mismatch); +CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4), \ + assert_smc_ctx_greg_r4_offset_mismatch); +CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr), \ + assert_smc_ctx_sp_usr_offset_mismatch); +CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon), \ + assert_smc_ctx_lr_mon_offset_mismatch); +CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon), \ + assert_smc_ctx_spsr_mon_offset_mismatch); + +CASSERT(SMC_CTX_SIZE == sizeof(smc_ctx_t), assert_smc_ctx_size_mismatch); + +/* Convenience macros to return from SMC handler */ +#define SMC_RET0(_h) { \ + return (uintptr_t)(_h); \ +} +#define SMC_RET1(_h, _r0) { \ + ((smc_ctx_t *)(_h))->r0 = (_r0); \ + SMC_RET0(_h); \ +} +#define SMC_RET2(_h, _r0, _r1) { \ + ((smc_ctx_t *)(_h))->r1 = (_r1); \ + SMC_RET1(_h, (_r0)); \ +} +#define SMC_RET3(_h, _r0, _r1, _r2) { \ + ((smc_ctx_t *)(_h))->r2 = (_r2); \ + SMC_RET2(_h, (_r0), (_r1)); \ +} +#define SMC_RET4(_h, _r0, _r1, _r2, _r3) { \ + ((smc_ctx_t *)(_h))->r3 = (_r3); \ + SMC_RET3(_h, (_r0), (_r1), (_r2)); \ +} + +/* Return a UUID in the SMC return registers */ +#define SMC_UUID_RET(_h, _uuid) \ + SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \ + ((const uint32_t *) &(_uuid))[1], \ + ((const uint32_t *) &(_uuid))[2], \ + ((const uint32_t *) &(_uuid))[3]) + +/* + * Helper macro to retrieve the SMC parameters from smc_ctx_t. + */ +#define get_smc_params_from_ctx(_hdl, _r1, _r2, _r3, _r4) { \ + _r1 = ((smc_ctx_t *)_hdl)->r1; \ + _r2 = ((smc_ctx_t *)_hdl)->r2; \ + _r3 = ((smc_ctx_t *)_hdl)->r3; \ + _r4 = ((smc_ctx_t *)_hdl)->r4; \ + } + +/* ------------------------------------------------------------------------ + * Helper APIs for setting and retrieving appropriate `smc_ctx_t`. + * These functions need to implemented by the BL including this library. + * ------------------------------------------------------------------------ + */ + +/* Get the pointer to `smc_ctx_t` corresponding to the security state. */ +void *smc_get_ctx(int security_state); + +/* Set the next `smc_ctx_t` corresponding to the security state. */ +void smc_set_next_ctx(int security_state); + +/* Get the pointer to next `smc_ctx_t` already set by `smc_set_next_ctx()`. */ +void *smc_get_next_ctx(void); + +#endif /*__ASSEMBLY__*/ +#endif /* __SMCC_HELPERS_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch32/smcc_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch32/smcc_macros.S new file mode 100644 index 0000000..c80c3e4 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch32/smcc_macros.S @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __SMCC_MACROS_S__ +#define __SMCC_MACROS_S__ + +#include + +/* + * Macro to save the General purpose registers including the banked + * registers to the SMC context on entry due a SMC call. On return, r0 + * contains the pointer to the `smc_context_t`. + */ + .macro smcc_save_gp_mode_regs + push {r0-r3, lr} + + ldcopr r0, SCR + and r0, r0, #SCR_NS_BIT + bl smc_get_ctx + + /* Save r4 - r12 in the SMC context */ + add r1, r0, #SMC_CTX_GPREG_R4 + stm r1!, {r4-r12} + + /* + * Pop r0 - r3, lr to r4 - r7, lr from stack and then save + * it to SMC context. + */ + pop {r4-r7, lr} + stm r0, {r4-r7} + + /* Save the banked registers including the current SPSR and LR */ + mrs r4, sp_usr + mrs r5, lr_usr + mrs r6, spsr_irq + mrs r7, sp_irq + mrs r8, lr_irq + mrs r9, spsr_fiq + mrs r10, sp_fiq + mrs r11, lr_fiq + mrs r12, spsr_svc + stm r1!, {r4-r12} + + mrs r4, sp_svc + mrs r5, lr_svc + mrs r6, spsr_abt + mrs r7, sp_abt + mrs r8, lr_abt + mrs r9, spsr_und + mrs r10, sp_und + mrs r11, lr_und + mrs r12, spsr + stm r1!, {r4-r12, lr} + + .endm + +/* + * Macro to restore the General purpose registers including the banked + * registers from the SMC context prior to exit from the SMC call. + * r0 must point to the `smc_context_t` to restore from. + */ + .macro smcc_restore_gp_mode_regs + + /* Restore the banked registers including the current SPSR and LR */ + add r1, r0, #SMC_CTX_SP_USR + ldm r1!, {r4-r12} + msr sp_usr, r4 + msr lr_usr, r5 + msr spsr_irq, r6 + msr sp_irq, r7 + msr lr_irq, r8 + msr spsr_fiq, r9 + msr sp_fiq, r10 + msr lr_fiq, r11 + msr spsr_svc, r12 + + ldm r1!, {r4-r12, lr} + msr sp_svc, r4 + msr lr_svc, r5 + msr spsr_abt, r6 + msr sp_abt, r7 + msr lr_abt, r8 + msr spsr_und, r9 + msr sp_und, r10 + msr lr_und, r11 + msr spsr, r12 + + /* Restore the rest of the general purpose registers */ + ldm r0, {r0-r12} + .endm + +#endif /* __SMCC_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch64/arch.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch64/arch.h new file mode 100644 index 0000000..fb8cbc0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch64/arch.h @@ -0,0 +1,411 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_H__ +#define __ARCH_H__ + + +/******************************************************************************* + * MIDR bit definitions + ******************************************************************************/ +#define MIDR_IMPL_MASK 0xff +#define MIDR_IMPL_SHIFT 0x18 +#define MIDR_VAR_SHIFT 20 +#define MIDR_VAR_BITS 4 +#define MIDR_REV_SHIFT 0 +#define MIDR_REV_BITS 4 +#define MIDR_PN_MASK 0xfff +#define MIDR_PN_SHIFT 0x4 + +/******************************************************************************* + * MPIDR macros + ******************************************************************************/ +#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK +#define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS +#define MPIDR_AFFINITY_BITS 8 +#define MPIDR_AFFLVL_MASK 0xff +#define MPIDR_AFF0_SHIFT 0 +#define MPIDR_AFF1_SHIFT 8 +#define MPIDR_AFF2_SHIFT 16 +#define MPIDR_AFF3_SHIFT 32 +#define MPIDR_AFFINITY_MASK 0xff00ffffff +#define MPIDR_AFFLVL_SHIFT 3 +#define MPIDR_AFFLVL0 0 +#define MPIDR_AFFLVL1 1 +#define MPIDR_AFFLVL2 2 +#define MPIDR_AFFLVL3 3 +#define MPIDR_AFFLVL0_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL1_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL2_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) +#define MPIDR_AFFLVL3_VAL(mpidr) \ + ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) +/* + * The MPIDR_MAX_AFFLVL count starts from 0. Take care to + * add one while using this macro to define array sizes. + * TODO: Support only the first 3 affinity levels for now. + */ +#define MPIDR_MAX_AFFLVL 2 + +/* Constant to highlight the assumption that MPIDR allocation starts from 0 */ +#define FIRST_MPIDR 0 + +/******************************************************************************* + * Definitions for CPU system register interface to GICv3 + ******************************************************************************/ +#define ICC_SRE_EL1 S3_0_C12_C12_5 +#define ICC_SRE_EL2 S3_4_C12_C9_5 +#define ICC_SRE_EL3 S3_6_C12_C12_5 +#define ICC_CTLR_EL1 S3_0_C12_C12_4 +#define ICC_CTLR_EL3 S3_6_C12_C12_4 +#define ICC_PMR_EL1 S3_0_C4_C6_0 +#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 +#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 +#define ICC_HPPIR0_EL1 S3_0_c12_c8_2 +#define ICC_HPPIR1_EL1 S3_0_c12_c12_2 +#define ICC_IAR0_EL1 S3_0_c12_c8_0 +#define ICC_IAR1_EL1 S3_0_c12_c12_0 +#define ICC_EOIR0_EL1 S3_0_c12_c8_1 +#define ICC_EOIR1_EL1 S3_0_c12_c12_1 + +/******************************************************************************* + * Generic timer memory mapped registers & offsets + ******************************************************************************/ +#define CNTCR_OFF 0x000 +#define CNTFID_OFF 0x020 + +#define CNTCR_EN (1 << 0) +#define CNTCR_HDBG (1 << 1) +#define CNTCR_FCREQ(x) ((x) << 8) + +/******************************************************************************* + * System register bit definitions + ******************************************************************************/ +/* CLIDR definitions */ +#define LOUIS_SHIFT 21 +#define LOC_SHIFT 24 +#define CLIDR_FIELD_WIDTH 3 + +/* CSSELR definitions */ +#define LEVEL_SHIFT 1 + +/* D$ set/way op type defines */ +#define DCISW 0x0 +#define DCCISW 0x1 +#define DCCSW 0x2 + +/* ID_AA64PFR0_EL1 definitions */ +#define ID_AA64PFR0_EL0_SHIFT 0 +#define ID_AA64PFR0_EL1_SHIFT 4 +#define ID_AA64PFR0_EL2_SHIFT 8 +#define ID_AA64PFR0_EL3_SHIFT 12 +#define ID_AA64PFR0_ELX_MASK 0xf + +#define ID_AA64PFR0_GIC_SHIFT 24 +#define ID_AA64PFR0_GIC_WIDTH 4 +#define ID_AA64PFR0_GIC_MASK ((1 << ID_AA64PFR0_GIC_WIDTH) - 1) + +/* ID_PFR1_EL1 definitions */ +#define ID_PFR1_VIRTEXT_SHIFT 12 +#define ID_PFR1_VIRTEXT_MASK 0xf +#define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \ + & ID_PFR1_VIRTEXT_MASK) + +/* SCTLR definitions */ +#define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ + (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \ + (1 << 4)) + +#define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ + (1 << 20) | (1 << 11)) +#define SCTLR_AARCH32_EL1_RES1 \ + ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \ + (1 << 3)) + +#define SCTLR_M_BIT (1 << 0) +#define SCTLR_A_BIT (1 << 1) +#define SCTLR_C_BIT (1 << 2) +#define SCTLR_SA_BIT (1 << 3) +#define SCTLR_I_BIT (1 << 12) +#define SCTLR_WXN_BIT (1 << 19) +#define SCTLR_EE_BIT (1 << 25) + +/* CPACR_El1 definitions */ +#define CPACR_EL1_FPEN(x) (x << 20) +#define CPACR_EL1_FP_TRAP_EL0 0x1 +#define CPACR_EL1_FP_TRAP_ALL 0x2 +#define CPACR_EL1_FP_TRAP_NONE 0x3 + +/* SCR definitions */ +#define SCR_RES1_BITS ((1 << 4) | (1 << 5)) +#define SCR_TWE_BIT (1 << 13) +#define SCR_TWI_BIT (1 << 12) +#define SCR_ST_BIT (1 << 11) +#define SCR_RW_BIT (1 << 10) +#define SCR_SIF_BIT (1 << 9) +#define SCR_HCE_BIT (1 << 8) +#define SCR_SMD_BIT (1 << 7) +#define SCR_EA_BIT (1 << 3) +#define SCR_FIQ_BIT (1 << 2) +#define SCR_IRQ_BIT (1 << 1) +#define SCR_NS_BIT (1 << 0) +#define SCR_VALID_BIT_MASK 0x2f8f + +/* HCR definitions */ +#define HCR_RW_BIT (1ull << 31) +#define HCR_AMO_BIT (1 << 5) +#define HCR_IMO_BIT (1 << 4) +#define HCR_FMO_BIT (1 << 3) + +/* ISR definitions */ +#define ISR_A_SHIFT 8 +#define ISR_I_SHIFT 7 +#define ISR_F_SHIFT 6 + +/* CNTHCTL_EL2 definitions */ +#define EVNTEN_BIT (1 << 2) +#define EL1PCEN_BIT (1 << 1) +#define EL1PCTEN_BIT (1 << 0) + +/* CNTKCTL_EL1 definitions */ +#define EL0PTEN_BIT (1 << 9) +#define EL0VTEN_BIT (1 << 8) +#define EL0PCTEN_BIT (1 << 0) +#define EL0VCTEN_BIT (1 << 1) +#define EVNTEN_BIT (1 << 2) +#define EVNTDIR_BIT (1 << 3) +#define EVNTI_SHIFT 4 +#define EVNTI_MASK 0xf + +/* CPTR_EL3 definitions */ +#define TCPAC_BIT (1 << 31) +#define TTA_BIT (1 << 20) +#define TFP_BIT (1 << 10) + +/* CPSR/SPSR definitions */ +#define DAIF_FIQ_BIT (1 << 0) +#define DAIF_IRQ_BIT (1 << 1) +#define DAIF_ABT_BIT (1 << 2) +#define DAIF_DBG_BIT (1 << 3) +#define SPSR_DAIF_SHIFT 6 +#define SPSR_DAIF_MASK 0xf + +#define SPSR_AIF_SHIFT 6 +#define SPSR_AIF_MASK 0x7 + +#define SPSR_E_SHIFT 9 +#define SPSR_E_MASK 0x1 +#define SPSR_E_LITTLE 0x0 +#define SPSR_E_BIG 0x1 + +#define SPSR_T_SHIFT 5 +#define SPSR_T_MASK 0x1 +#define SPSR_T_ARM 0x0 +#define SPSR_T_THUMB 0x1 + +#define DISABLE_ALL_EXCEPTIONS \ + (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) + + +/* + * TCR defintions + */ +#define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23)) +#define TCR_EL1_IPS_SHIFT 32 +#define TCR_EL3_PS_SHIFT 16 + +#define TCR_TxSZ_MIN 16 +#define TCR_TxSZ_MAX 39 + +/* (internal) physical address size bits in EL3/EL1 */ +#define TCR_PS_BITS_4GB (0x0) +#define TCR_PS_BITS_64GB (0x1) +#define TCR_PS_BITS_1TB (0x2) +#define TCR_PS_BITS_4TB (0x3) +#define TCR_PS_BITS_16TB (0x4) +#define TCR_PS_BITS_256TB (0x5) + +#define ADDR_MASK_48_TO_63 0xFFFF000000000000UL +#define ADDR_MASK_44_TO_47 0x0000F00000000000UL +#define ADDR_MASK_42_TO_43 0x00000C0000000000UL +#define ADDR_MASK_40_TO_41 0x0000030000000000UL +#define ADDR_MASK_36_TO_39 0x000000F000000000UL +#define ADDR_MASK_32_TO_35 0x0000000F00000000UL + +#define TCR_RGN_INNER_NC (0x0 << 8) +#define TCR_RGN_INNER_WBA (0x1 << 8) +#define TCR_RGN_INNER_WT (0x2 << 8) +#define TCR_RGN_INNER_WBNA (0x3 << 8) + +#define TCR_RGN_OUTER_NC (0x0 << 10) +#define TCR_RGN_OUTER_WBA (0x1 << 10) +#define TCR_RGN_OUTER_WT (0x2 << 10) +#define TCR_RGN_OUTER_WBNA (0x3 << 10) + +#define TCR_SH_NON_SHAREABLE (0x0 << 12) +#define TCR_SH_OUTER_SHAREABLE (0x2 << 12) +#define TCR_SH_INNER_SHAREABLE (0x3 << 12) + +#define MODE_SP_SHIFT 0x0 +#define MODE_SP_MASK 0x1 +#define MODE_SP_EL0 0x0 +#define MODE_SP_ELX 0x1 + +#define MODE_RW_SHIFT 0x4 +#define MODE_RW_MASK 0x1 +#define MODE_RW_64 0x0 +#define MODE_RW_32 0x1 + +#define MODE_EL_SHIFT 0x2 +#define MODE_EL_MASK 0x3 +#define MODE_EL3 0x3 +#define MODE_EL2 0x2 +#define MODE_EL1 0x1 +#define MODE_EL0 0x0 + +#define MODE32_SHIFT 0 +#define MODE32_MASK 0xf +#define MODE32_usr 0x0 +#define MODE32_fiq 0x1 +#define MODE32_irq 0x2 +#define MODE32_svc 0x3 +#define MODE32_mon 0x6 +#define MODE32_abt 0x7 +#define MODE32_hyp 0xa +#define MODE32_und 0xb +#define MODE32_sys 0xf + +#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) +#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) +#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) +#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) + +#define SPSR_64(el, sp, daif) \ + (MODE_RW_64 << MODE_RW_SHIFT | \ + ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \ + ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \ + ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT) + +#define SPSR_MODE32(mode, isa, endian, aif) \ + (MODE_RW_32 << MODE_RW_SHIFT | \ + ((mode) & MODE32_MASK) << MODE32_SHIFT | \ + ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ + ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ + ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) + +/* + * CTR_EL0 definitions + */ +#define CTR_CWG_SHIFT 24 +#define CTR_CWG_MASK 0xf +#define CTR_ERG_SHIFT 20 +#define CTR_ERG_MASK 0xf +#define CTR_DMINLINE_SHIFT 16 +#define CTR_DMINLINE_MASK 0xf +#define CTR_L1IP_SHIFT 14 +#define CTR_L1IP_MASK 0x3 +#define CTR_IMINLINE_SHIFT 0 +#define CTR_IMINLINE_MASK 0xf + +#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */ + +/* Physical timer control register bit fields shifts and masks */ +#define CNTP_CTL_ENABLE_SHIFT 0 +#define CNTP_CTL_IMASK_SHIFT 1 +#define CNTP_CTL_ISTATUS_SHIFT 2 + +#define CNTP_CTL_ENABLE_MASK 1 +#define CNTP_CTL_IMASK_MASK 1 +#define CNTP_CTL_ISTATUS_MASK 1 + +#define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \ + CNTP_CTL_ENABLE_MASK) +#define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \ + CNTP_CTL_IMASK_MASK) +#define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \ + CNTP_CTL_ISTATUS_MASK) + +#define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT) +#define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT) + +#define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT)) +#define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT)) + +/* Exception Syndrome register bits and bobs */ +#define ESR_EC_SHIFT 26 +#define ESR_EC_MASK 0x3f +#define ESR_EC_LENGTH 6 +#define EC_UNKNOWN 0x0 +#define EC_WFE_WFI 0x1 +#define EC_AARCH32_CP15_MRC_MCR 0x3 +#define EC_AARCH32_CP15_MRRC_MCRR 0x4 +#define EC_AARCH32_CP14_MRC_MCR 0x5 +#define EC_AARCH32_CP14_LDC_STC 0x6 +#define EC_FP_SIMD 0x7 +#define EC_AARCH32_CP10_MRC 0x8 +#define EC_AARCH32_CP14_MRRC_MCRR 0xc +#define EC_ILLEGAL 0xe +#define EC_AARCH32_SVC 0x11 +#define EC_AARCH32_HVC 0x12 +#define EC_AARCH32_SMC 0x13 +#define EC_AARCH64_SVC 0x15 +#define EC_AARCH64_HVC 0x16 +#define EC_AARCH64_SMC 0x17 +#define EC_AARCH64_SYS 0x18 +#define EC_IABORT_LOWER_EL 0x20 +#define EC_IABORT_CUR_EL 0x21 +#define EC_PC_ALIGN 0x22 +#define EC_DABORT_LOWER_EL 0x24 +#define EC_DABORT_CUR_EL 0x25 +#define EC_SP_ALIGN 0x26 +#define EC_AARCH32_FP 0x28 +#define EC_AARCH64_FP 0x2c +#define EC_SERROR 0x2f + +#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK + +/******************************************************************************* + * Definitions of register offsets and fields in the CNTCTLBase Frame of the + * system level implementation of the Generic Timer. + ******************************************************************************/ +#define CNTNSAR 0x4 +#define CNTNSAR_NS_SHIFT(x) x + +#define CNTACR_BASE(x) (0x40 + (x << 2)) +#define CNTACR_RPCT_SHIFT 0x0 +#define CNTACR_RVCT_SHIFT 0x1 +#define CNTACR_RFRQ_SHIFT 0x2 +#define CNTACR_RVOFF_SHIFT 0x3 +#define CNTACR_RWVT_SHIFT 0x4 +#define CNTACR_RWPT_SHIFT 0x5 + +#endif /* __ARCH_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch64/arch_helpers.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch64/arch_helpers.h new file mode 100644 index 0000000..4d936ad --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch64/arch_helpers.h @@ -0,0 +1,321 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ARCH_HELPERS_H__ +#define __ARCH_HELPERS_H__ + +#include /* for additional register definitions */ +#include /* For __dead2 */ +#include + +/********************************************************************** + * Macros which create inline functions to read or write CPU system + * registers + *********************************************************************/ + +#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ +static inline uint64_t read_ ## _name(void) \ +{ \ + uint64_t v; \ + __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ + return v; \ +} + +#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ +static inline void write_ ## _name(uint64_t v) \ +{ \ + __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ +} + +#define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \ +static inline void write_ ## _name(const uint64_t v) \ +{ \ + __asm__ volatile ("msr " #_reg_name ", %0" : : "i" (v)); \ +} + +/* Define read function for system register */ +#define DEFINE_SYSREG_READ_FUNC(_name) \ + _DEFINE_SYSREG_READ_FUNC(_name, _name) + +/* Define read & write function for system register */ +#define DEFINE_SYSREG_RW_FUNCS(_name) \ + _DEFINE_SYSREG_READ_FUNC(_name, _name) \ + _DEFINE_SYSREG_WRITE_FUNC(_name, _name) + +/* Define read & write function for renamed system register */ +#define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ + _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ + _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) + +/* Define read function for renamed system register */ +#define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \ + _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) + +/* Define write function for renamed system register */ +#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ + _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) + +/* Define write function for special system registers */ +#define DEFINE_SYSREG_WRITE_CONST_FUNC(_name) \ + _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _name) + + +/********************************************************************** + * Macros to create inline functions for system instructions + *********************************************************************/ + +/* Define function for simple system instruction */ +#define DEFINE_SYSOP_FUNC(_op) \ +static inline void _op(void) \ +{ \ + __asm__ (#_op); \ +} + +/* Define function for system instruction with type specifier */ +#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ +static inline void _op ## _type(void) \ +{ \ + __asm__ (#_op " " #_type); \ +} + +/* Define function for system instruction with register parameter */ +#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ +static inline void _op ## _type(uint64_t v) \ +{ \ + __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ +} + +/******************************************************************************* + * TLB maintenance accessor prototypes + ******************************************************************************/ +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) +DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) +DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) + +/******************************************************************************* + * Cache maintenance accessor prototypes + ******************************************************************************/ +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) +DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) + +/******************************************************************************* + * Address translation accessor prototypes + ******************************************************************************/ +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r) +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w) +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r) +DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w) + +void flush_dcache_range(uint64_t, uint64_t); +void clean_dcache_range(uint64_t, uint64_t); +void inv_dcache_range(uint64_t, uint64_t); +void dcsw_op_louis(uint32_t); +void dcsw_op_all(uint32_t); + +void disable_mmu_el3(void); +void disable_mmu_icache_el3(void); + +/******************************************************************************* + * Misc. accessor prototypes + ******************************************************************************/ + +DEFINE_SYSREG_WRITE_CONST_FUNC(daifset) +DEFINE_SYSREG_WRITE_CONST_FUNC(daifclr) + +DEFINE_SYSREG_READ_FUNC(par_el1) +DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) +DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) +DEFINE_SYSREG_READ_FUNC(CurrentEl) +DEFINE_SYSREG_RW_FUNCS(daif) +DEFINE_SYSREG_RW_FUNCS(spsr_el1) +DEFINE_SYSREG_RW_FUNCS(spsr_el2) +DEFINE_SYSREG_RW_FUNCS(spsr_el3) +DEFINE_SYSREG_RW_FUNCS(elr_el1) +DEFINE_SYSREG_RW_FUNCS(elr_el2) +DEFINE_SYSREG_RW_FUNCS(elr_el3) + +DEFINE_SYSOP_FUNC(wfi) +DEFINE_SYSOP_FUNC(wfe) +DEFINE_SYSOP_FUNC(sev) +DEFINE_SYSOP_TYPE_FUNC(dsb, sy) +DEFINE_SYSOP_TYPE_FUNC(dmb, sy) +DEFINE_SYSOP_TYPE_FUNC(dmb, st) +DEFINE_SYSOP_TYPE_FUNC(dmb, ld) +DEFINE_SYSOP_TYPE_FUNC(dsb, ish) +DEFINE_SYSOP_TYPE_FUNC(dmb, ish) +DEFINE_SYSOP_FUNC(isb) + +uint32_t get_afflvl_shift(uint32_t); +uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t); + + +void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); +void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); + +/******************************************************************************* + * System register accessor prototypes + ******************************************************************************/ +DEFINE_SYSREG_READ_FUNC(midr_el1) +DEFINE_SYSREG_READ_FUNC(mpidr_el1) + +DEFINE_SYSREG_RW_FUNCS(scr_el3) +DEFINE_SYSREG_RW_FUNCS(hcr_el2) + +DEFINE_SYSREG_RW_FUNCS(vbar_el1) +DEFINE_SYSREG_RW_FUNCS(vbar_el2) +DEFINE_SYSREG_RW_FUNCS(vbar_el3) + +DEFINE_SYSREG_RW_FUNCS(sctlr_el1) +DEFINE_SYSREG_RW_FUNCS(sctlr_el2) +DEFINE_SYSREG_RW_FUNCS(sctlr_el3) + +DEFINE_SYSREG_RW_FUNCS(actlr_el1) +DEFINE_SYSREG_RW_FUNCS(actlr_el2) +DEFINE_SYSREG_RW_FUNCS(actlr_el3) + +DEFINE_SYSREG_RW_FUNCS(esr_el1) +DEFINE_SYSREG_RW_FUNCS(esr_el2) +DEFINE_SYSREG_RW_FUNCS(esr_el3) + +DEFINE_SYSREG_RW_FUNCS(afsr0_el1) +DEFINE_SYSREG_RW_FUNCS(afsr0_el2) +DEFINE_SYSREG_RW_FUNCS(afsr0_el3) + +DEFINE_SYSREG_RW_FUNCS(afsr1_el1) +DEFINE_SYSREG_RW_FUNCS(afsr1_el2) +DEFINE_SYSREG_RW_FUNCS(afsr1_el3) + +DEFINE_SYSREG_RW_FUNCS(far_el1) +DEFINE_SYSREG_RW_FUNCS(far_el2) +DEFINE_SYSREG_RW_FUNCS(far_el3) + +DEFINE_SYSREG_RW_FUNCS(mair_el1) +DEFINE_SYSREG_RW_FUNCS(mair_el2) +DEFINE_SYSREG_RW_FUNCS(mair_el3) + +DEFINE_SYSREG_RW_FUNCS(amair_el1) +DEFINE_SYSREG_RW_FUNCS(amair_el2) +DEFINE_SYSREG_RW_FUNCS(amair_el3) + +DEFINE_SYSREG_READ_FUNC(rvbar_el1) +DEFINE_SYSREG_READ_FUNC(rvbar_el2) +DEFINE_SYSREG_READ_FUNC(rvbar_el3) + +DEFINE_SYSREG_RW_FUNCS(rmr_el1) +DEFINE_SYSREG_RW_FUNCS(rmr_el2) +DEFINE_SYSREG_RW_FUNCS(rmr_el3) + +DEFINE_SYSREG_RW_FUNCS(tcr_el1) +DEFINE_SYSREG_RW_FUNCS(tcr_el2) +DEFINE_SYSREG_RW_FUNCS(tcr_el3) + +DEFINE_SYSREG_RW_FUNCS(ttbr0_el1) +DEFINE_SYSREG_RW_FUNCS(ttbr0_el2) +DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) + +DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) + +DEFINE_SYSREG_RW_FUNCS(vttbr_el2) + +DEFINE_SYSREG_RW_FUNCS(cptr_el2) +DEFINE_SYSREG_RW_FUNCS(cptr_el3) + +DEFINE_SYSREG_RW_FUNCS(cpacr_el1) +DEFINE_SYSREG_RW_FUNCS(cntfrq_el0) +DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1) +DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1) +DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1) +DEFINE_SYSREG_READ_FUNC(cntpct_el0) +DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) + +DEFINE_SYSREG_RW_FUNCS(tpidr_el3) + +DEFINE_SYSREG_RW_FUNCS(cntvoff_el2) + +DEFINE_SYSREG_RW_FUNCS(vpidr_el2) +DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) +DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0) + +DEFINE_SYSREG_READ_FUNC(isr_el1) + +DEFINE_SYSREG_READ_FUNC(ctr_el0) + +DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) +DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) +DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) +DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3) +DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1) +DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1) +DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1) +DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1) +DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1) +DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) +DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) + + +#define IS_IN_EL(x) \ + (GET_EL(read_CurrentEl()) == MODE_EL##x) + +#define IS_IN_EL1() IS_IN_EL(1) +#define IS_IN_EL3() IS_IN_EL(3) + +/* Previously defined accesor functions with incomplete register names */ + +#define read_current_el() read_CurrentEl() + +#define dsb() dsbsy() + +#define read_midr() read_midr_el1() + +#define read_mpidr() read_mpidr_el1() + +#define read_scr() read_scr_el3() +#define write_scr(_v) write_scr_el3(_v) + +#define read_hcr() read_hcr_el2() +#define write_hcr(_v) write_hcr_el2(_v) + +#define read_cpacr() read_cpacr_el1() +#define write_cpacr(_v) write_cpacr_el1(_v) + +#endif /* __ARCH_HELPERS_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch64/smcc_helpers.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch64/smcc_helpers.h new file mode 100644 index 0000000..6e63383 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/aarch64/smcc_helpers.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SMCC_HELPERS_H__ +#define __SMCC_HELPERS_H__ + +#include + +#ifndef __ASSEMBLY__ +#include + +/* Convenience macros to return from SMC handler */ +#define SMC_RET0(_h) { \ + return (uint64_t) (_h); \ +} +#define SMC_RET1(_h, _x0) { \ + write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X0, (_x0)); \ + SMC_RET0(_h); \ +} +#define SMC_RET2(_h, _x0, _x1) { \ + write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X1, (_x1)); \ + SMC_RET1(_h, (_x0)); \ +} +#define SMC_RET3(_h, _x0, _x1, _x2) { \ + write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X2, (_x2)); \ + SMC_RET2(_h, (_x0), (_x1)); \ +} +#define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \ + write_ctx_reg(get_gpregs_ctx(_h), CTX_GPREG_X3, (_x3)); \ + SMC_RET3(_h, (_x0), (_x1), (_x2)); \ +} + +/* + * Convenience macros to access general purpose registers using handle provided + * to SMC handler. These take the offset values defined in context.h + */ +#define SMC_GET_GP(_h, _g) \ + read_ctx_reg(get_gpregs_ctx(_h), (_g)) +#define SMC_SET_GP(_h, _g, _v) \ + write_ctx_reg(get_gpregs_ctx(_h), (_g), (_v)) + +/* + * Convenience macros to access EL3 context registers using handle provided to + * SMC handler. These take the offset values defined in context.h + */ +#define SMC_GET_EL3(_h, _e) \ + read_ctx_reg(get_el3state_ctx(_h), (_e)) +#define SMC_SET_EL3(_h, _e, _v) \ + write_ctx_reg(get_el3state_ctx(_h), (_e), (_v)) + +/* Return a UUID in the SMC return registers */ +#define SMC_UUID_RET(_h, _uuid) \ + SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \ + ((const uint32_t *) &(_uuid))[1], \ + ((const uint32_t *) &(_uuid))[2], \ + ((const uint32_t *) &(_uuid))[3]) + +/* + * Helper macro to retrieve the SMC parameters from cpu_context_t. + */ +#define get_smc_params_from_ctx(_hdl, _x1, _x2, _x3, _x4) \ + do { \ + const gp_regs_t *regs = get_gpregs_ctx(_hdl); \ + _x1 = read_ctx_reg(regs, CTX_GPREG_X1); \ + _x2 = read_ctx_reg(regs, CTX_GPREG_X2); \ + _x3 = read_ctx_reg(regs, CTX_GPREG_X3); \ + _x4 = read_ctx_reg(regs, CTX_GPREG_X4); \ + } while (0) + +#endif /*__ASSEMBLY__*/ +#endif /* __SMCC_HELPERS_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/bakery_lock.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/bakery_lock.h new file mode 100644 index 0000000..6b8157e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/bakery_lock.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BAKERY_LOCK_H__ +#define __BAKERY_LOCK_H__ + +#include + +#define BAKERY_LOCK_MAX_CPUS PLATFORM_CORE_COUNT + +#ifndef __ASSEMBLY__ +#include + +/***************************************************************************** + * Internal helper macros used by the bakery lock implementation. + ****************************************************************************/ +/* Convert a ticket to priority */ +#define PRIORITY(t, pos) (((t) << 8) | (pos)) + +#define CHOOSING_TICKET 0x1 +#define CHOSEN_TICKET 0x0 + +#define bakery_is_choosing(info) (info & 0x1) +#define bakery_ticket_number(info) ((info >> 1) & 0x7FFF) +#define make_bakery_data(choosing, number) \ + (((choosing & 0x1) | (number << 1)) & 0xFFFF) + +/***************************************************************************** + * External bakery lock interface. + ****************************************************************************/ +#if USE_COHERENT_MEM +/* + * Bakery locks are stored in coherent memory + * + * Each lock's data is contiguous and fully allocated by the compiler + */ + +typedef struct bakery_lock { + /* + * The lock_data is a bit-field of 2 members: + * Bit[0] : choosing. This field is set when the CPU is + * choosing its bakery number. + * Bits[1 - 15] : number. This is the bakery number allocated. + */ + volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS]; +} bakery_lock_t; + +#else +/* + * Bakery locks are stored in normal .bss memory + * + * Each lock's data is spread across multiple cache lines, one per CPU, + * but multiple locks can share the same cache line. + * The compiler will allocate enough memory for one CPU's bakery locks, + * the remaining cache lines are allocated by the linker script + */ + +typedef struct bakery_info { + /* + * The lock_data is a bit-field of 2 members: + * Bit[0] : choosing. This field is set when the CPU is + * choosing its bakery number. + * Bits[1 - 15] : number. This is the bakery number allocated. + */ + volatile uint16_t lock_data; +} bakery_info_t; + +typedef bakery_info_t bakery_lock_t; + +#endif /* __USE_COHERENT_MEM__ */ + +static inline void bakery_lock_init(bakery_lock_t *bakery) {} +void bakery_lock_get(bakery_lock_t *bakery); +void bakery_lock_release(bakery_lock_t *bakery); + +#define DEFINE_BAKERY_LOCK(_name) bakery_lock_t _name __section("bakery_lock") + +#define DECLARE_BAKERY_LOCK(_name) extern bakery_lock_t _name + + +#endif /* __ASSEMBLY__ */ +#endif /* __BAKERY_LOCK_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cassert.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cassert.h new file mode 100644 index 0000000..00ee4d5 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cassert.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CASSERT_H__ +#define __CASSERT_H__ + +/******************************************************************************* + * Macro to flag a compile time assertion. It uses the preprocessor to generate + * an invalid C construct if 'cond' evaluates to false. + * The following compilation error is triggered if the assertion fails: + * "error: size of array 'msg' is negative" + * The 'unused' attribute ensures that the unused typedef does not emit a + * compiler warning. + ******************************************************************************/ +#define CASSERT(cond, msg) \ + typedef char msg[(cond) ? 1 : -1] __unused + +#endif /* __CASSERT_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch32/aem_generic.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch32/aem_generic.h new file mode 100644 index 0000000..9b31367 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch32/aem_generic.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AEM_GENERIC_H__ +#define __AEM_GENERIC_H__ + +/* BASE AEM midr for revision 0 */ +#define BASE_AEM_MIDR 0x410FD0F0 + +#endif /* __AEM_GENERIC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch32/cortex_a32.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch32/cortex_a32.h new file mode 100644 index 0000000..458b41f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch32/cortex_a32.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CORTEX_A32_H__ +#define __CORTEX_A32_H__ + +/* Cortex-A32 Main ID register for revision 0 */ +#define CORTEX_A32_MIDR 0x410FD010 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + * CPUECTLR_EL1 is an implementation-specific register. + ******************************************************************************/ +#define CORTEX_A32_CPUECTLR_EL1 p15, 1, c15 +#define CORTEX_A32_CPUECTLR_SMPEN_BIT (1 << 6) + +#endif /* __CORTEX_A32_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch32/cpu_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch32/cpu_macros.S new file mode 100644 index 0000000..2b9947e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch32/cpu_macros.S @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __CPU_MACROS_S__ +#define __CPU_MACROS_S__ + +#include + +#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ + (MIDR_PN_MASK << MIDR_PN_SHIFT) + + /* + * Define the offsets to the fields in cpu_ops structure. + */ + .struct 0 +CPU_MIDR: /* cpu_ops midr */ + .space 4 +/* Reset fn is needed during reset */ +#if IMAGE_BL1 || IMAGE_BL32 +CPU_RESET_FUNC: /* cpu_ops reset_func */ + .space 4 +#endif +#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */ +CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */ + .space 4 +CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */ + .space 4 +#endif +CPU_OPS_SIZE = . + + /* + * Convenience macro to declare cpu_ops structure. + * Make sure the structure fields are as per the offsets + * defined above. + */ + .macro declare_cpu_ops _name:req, _midr:req, _noresetfunc = 0 + .section cpu_ops, "a" + .align 2 + .type cpu_ops_\_name, %object + .word \_midr +#if IMAGE_BL1 || IMAGE_BL32 + .if \_noresetfunc + .word 0 + .else + .word \_name\()_reset_func + .endif +#endif +#if IMAGE_BL32 + .word \_name\()_core_pwr_dwn + .word \_name\()_cluster_pwr_dwn +#endif + .endm + +#endif /* __CPU_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/aem_generic.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/aem_generic.h new file mode 100644 index 0000000..2f701d1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/aem_generic.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __AEM_GENERIC_H__ +#define __AEM_GENERIC_H__ + +/* BASE AEM midr for revision 0 */ +#define BASE_AEM_MIDR 0x410FD0F0 + +/* Foundation AEM midr for revision 0 */ +#define FOUNDATION_AEM_MIDR 0x410FD000 + + +#endif /* __AEM_GENERIC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a35.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a35.h new file mode 100644 index 0000000..4288b9f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a35.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CORTEX_A35_H__ +#define __CORTEX_A35_H__ + +/* Cortex-A35 Main ID register for revision 0 */ +#define CORTEX_A35_MIDR 0x410FD040 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + * CPUECTLR_EL1 is an implementation-specific register. + ******************************************************************************/ +#define CORTEX_A35_CPUECTLR_EL1 S3_1_C15_C2_1 +#define CORTEX_A35_CPUECTLR_SMPEN_BIT (1 << 6) + +#endif /* __CORTEX_A35_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a53.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a53.h new file mode 100644 index 0000000..6976b80 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a53.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CORTEX_A53_H__ +#define __CORTEX_A53_H__ + +/* Cortex-A53 midr for revision 0 */ +#define CORTEX_A53_MIDR 0x410FD030 + +/* Retention timer tick definitions */ +#define RETENTION_ENTRY_TICKS_2 0x1 +#define RETENTION_ENTRY_TICKS_8 0x2 +#define RETENTION_ENTRY_TICKS_32 0x3 +#define RETENTION_ENTRY_TICKS_64 0x4 +#define RETENTION_ENTRY_TICKS_128 0x5 +#define RETENTION_ENTRY_TICKS_256 0x6 +#define RETENTION_ENTRY_TICKS_512 0x7 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ + +#define CPUECTLR_SMP_BIT (1 << 6) + +#define CPUECTLR_CPU_RET_CTRL_SHIFT 0 +#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) + +#define CPUECTLR_FPU_RET_CTRL_SHIFT 3 +#define CPUECTLR_FPU_RET_CTRL_MASK (0x7 << CPUECTLR_FPU_RET_CTRL_SHIFT) + +/******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ + +#define CPUACTLR_DTAH (1 << 24) + +/******************************************************************************* + * L2 Auxiliary Control register specific definitions. + ******************************************************************************/ +#define L2ACTLR_EL1 S3_1_C15_C0_0 /* Instruction def. */ + +#define L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) +#define L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) + +/******************************************************************************* + * L2 Extended Control register specific definitions. + ******************************************************************************/ +#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */ + +#define L2ECTLR_RET_CTRL_SHIFT 0 +#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) + +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + +#endif /* __CORTEX_A53_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a57.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a57.h new file mode 100644 index 0000000..c5a218b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a57.h @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CORTEX_A57_H__ +#define __CORTEX_A57_H__ + +/* Cortex-A57 midr for revision 0 */ +#define CORTEX_A57_MIDR 0x410FD070 + +/* Retention timer tick definitions */ +#define RETENTION_ENTRY_TICKS_2 0x1 +#define RETENTION_ENTRY_TICKS_8 0x2 +#define RETENTION_ENTRY_TICKS_32 0x3 +#define RETENTION_ENTRY_TICKS_64 0x4 +#define RETENTION_ENTRY_TICKS_128 0x5 +#define RETENTION_ENTRY_TICKS_256 0x6 +#define RETENTION_ENTRY_TICKS_512 0x7 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ + +#define CPUECTLR_SMP_BIT (1 << 6) +#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) +#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) +#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) + +#define CPUECTLR_CPU_RET_CTRL_SHIFT 0 +#define CPUECTLR_CPU_RET_CTRL_MASK (0x7 << CPUECTLR_CPU_RET_CTRL_SHIFT) + +/******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ + +#define CPUACTLR_DIS_LOAD_PASS_DMB (1 << 59) +#define CPUACTLR_GRE_NGRE_AS_NGNRE (1 << 54) +#define CPUACTLR_DIS_OVERREAD (1 << 52) +#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) +#define CPUACTLR_DCC_AS_DCCI (1 << 44) +#define CPUACTLR_FORCE_FPSCR_FLUSH (1 << 38) +#define CPUACTLR_DIS_STREAMING (3 << 27) +#define CPUACTLR_DIS_L1_STREAMING (3 << 25) +#define CPUACTLR_DIS_INDIRECT_PREDICTOR (1 << 4) + +/******************************************************************************* + * L2 Control register specific definitions. + ******************************************************************************/ +#define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */ + +#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 +#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 + +#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 + +/******************************************************************************* + * L2 Extended Control register specific definitions. + ******************************************************************************/ +#define L2ECTLR_EL1 S3_1_C11_C0_3 /* Instruction def. */ + +#define L2ECTLR_RET_CTRL_SHIFT 0 +#define L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) + +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + +#endif /* __CORTEX_A57_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a72.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a72.h new file mode 100644 index 0000000..01edf43 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a72.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CORTEX_A72_H__ +#define __CORTEX_A72_H__ + +/* Cortex-A72 midr for revision 0 */ +#define CORTEX_A72_MIDR 0x410FD080 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ + +#define CPUECTLR_SMP_BIT (1 << 6) +#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) +#define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) +#define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) + +/******************************************************************************* + * CPU Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CPUMERRSR_EL1 S3_1_C15_C2_2 /* Instruction def. */ + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define CPUACTLR_EL1 S3_1_C15_C2_0 /* Instruction def. */ + +#define CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56) +#define CPUACTLR_NO_ALLOC_WBWA (1 << 49) +#define CPUACTLR_DCC_AS_DCCI (1 << 44) + +/******************************************************************************* + * L2 Control register specific definitions. + ******************************************************************************/ +#define L2CTLR_EL1 S3_1_C11_C0_2 /* Instruction def. */ + +#define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 +#define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 + +#define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 +#define L2_TAG_RAM_LATENCY_2_CYCLES 0x1 +#define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 + +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + +#endif /* __CORTEX_A72_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a73.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a73.h new file mode 100644 index 0000000..13e114a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cortex_a73.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CORTEX_A73_H__ +#define __CORTEX_A73_H__ + +/* Cortex-A73 midr for revision 0 */ +#define CORTEX_A73_MIDR 0x410FD090 + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A73_CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ + +#define CORTEX_A73_CPUECTLR_SMP_BIT (1 << 6) + +/******************************************************************************* + * L2 Memory Error Syndrome register specific definitions. + ******************************************************************************/ +#define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ + +#endif /* __CORTEX_A73_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cpu_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cpu_macros.S new file mode 100644 index 0000000..f34f078 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/cpu_macros.S @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __CPU_MACROS_S__ +#define __CPU_MACROS_S__ + +#include + +#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ + (MIDR_PN_MASK << MIDR_PN_SHIFT) + + /* + * Define the offsets to the fields in cpu_ops structure. + */ + .struct 0 +CPU_MIDR: /* cpu_ops midr */ + .space 8 +/* Reset fn is needed in BL at reset vector */ +#if IMAGE_BL1 || IMAGE_BL31 +CPU_RESET_FUNC: /* cpu_ops reset_func */ + .space 8 +#endif +#if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */ +CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */ + .space 8 +CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */ + .space 8 +#endif +#if (IMAGE_BL31 && CRASH_REPORTING) +CPU_REG_DUMP: /* cpu specific register dump for crash reporting */ + .space 8 +#endif +CPU_OPS_SIZE = . + + /* + * Convenience macro to declare cpu_ops structure. + * Make sure the structure fields are as per the offsets + * defined above. + */ + .macro declare_cpu_ops _name:req, _midr:req, _noresetfunc = 0 + .section cpu_ops, "a"; .align 3 + .type cpu_ops_\_name, %object + .quad \_midr +#if IMAGE_BL1 || IMAGE_BL31 + .if \_noresetfunc + .quad 0 + .else + .quad \_name\()_reset_func + .endif +#endif +#if IMAGE_BL31 + .quad \_name\()_core_pwr_dwn + .quad \_name\()_cluster_pwr_dwn +#endif +#if (IMAGE_BL31 && CRASH_REPORTING) + .quad \_name\()_cpu_reg_dump +#endif + .endm + +#endif /* __CPU_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/denver.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/denver.h new file mode 100644 index 0000000..c7bee80 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/cpus/aarch64/denver.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DENVER_H__ +#define __DENVER_H__ + +/* MIDR for Denver v1.0 */ +#define DENVER_1_0_MIDR 0x4E0F0000 + +/* CPU state ids - implementation defined */ +#define DENVER_CPU_STATE_POWER_DOWN 0x3 + +#endif /* __DENVER_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/el3_runtime/aarch32/context.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/el3_runtime/aarch32/context.h new file mode 100644 index 0000000..5108141 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/el3_runtime/aarch32/context.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CONTEXT_H__ +#define __CONTEXT_H__ + +/******************************************************************************* + * Constants that allow assembler code to access members of and the 'regs' + * structure at their correct offsets. + ******************************************************************************/ +#define CTX_REGS_OFFSET 0x0 +#define CTX_GPREG_R0 0x0 +#define CTX_GPREG_R1 0x4 +#define CTX_GPREG_R2 0x8 +#define CTX_GPREG_R3 0xC +#define CTX_LR 0x10 +#define CTX_SCR 0x14 +#define CTX_SPSR 0x18 +#define CTX_NS_SCTLR 0x1C +#define CTX_REGS_END 0x20 + +#ifndef __ASSEMBLY__ + +#include +#include + +/* + * Common constants to help define the 'cpu_context' structure and its + * members below. + */ +#define WORD_SHIFT 2 +#define DEFINE_REG_STRUCT(name, num_regs) \ + typedef struct name { \ + uint32_t _regs[num_regs]; \ + } __aligned(8) name##_t + +/* Constants to determine the size of individual context structures */ +#define CTX_REG_ALL (CTX_REGS_END >> WORD_SHIFT) + +DEFINE_REG_STRUCT(regs, CTX_REG_ALL); + +#undef CTX_REG_ALL + +#define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> WORD_SHIFT]) +#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> WORD_SHIFT]) \ + = val) +typedef struct cpu_context { + regs_t regs_ctx; +} cpu_context_t; + +/* Macros to access members of the 'cpu_context_t' structure */ +#define get_regs_ctx(h) (&((cpu_context_t *) h)->regs_ctx) + +/* + * Compile time assertions related to the 'cpu_context' structure to + * ensure that the assembler and the compiler view of the offsets of + * the structure members is the same. + */ +CASSERT(CTX_REGS_OFFSET == __builtin_offsetof(cpu_context_t, regs_ctx), \ + assert_core_context_regs_offset_mismatch); + +#endif /* __ASSEMBLY__ */ + +#endif /* __CONTEXT_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/el3_runtime/aarch64/context.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/el3_runtime/aarch64/context.h new file mode 100644 index 0000000..b528c03 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/el3_runtime/aarch64/context.h @@ -0,0 +1,351 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CONTEXT_H__ +#define __CONTEXT_H__ + +/******************************************************************************* + * Constants that allow assembler code to access members of and the 'gp_regs' + * structure at their correct offsets. + ******************************************************************************/ +#define CTX_GPREGS_OFFSET 0x0 +#define CTX_GPREG_X0 0x0 +#define CTX_GPREG_X1 0x8 +#define CTX_GPREG_X2 0x10 +#define CTX_GPREG_X3 0x18 +#define CTX_GPREG_X4 0x20 +#define CTX_GPREG_X5 0x28 +#define CTX_GPREG_X6 0x30 +#define CTX_GPREG_X7 0x38 +#define CTX_GPREG_X8 0x40 +#define CTX_GPREG_X9 0x48 +#define CTX_GPREG_X10 0x50 +#define CTX_GPREG_X11 0x58 +#define CTX_GPREG_X12 0x60 +#define CTX_GPREG_X13 0x68 +#define CTX_GPREG_X14 0x70 +#define CTX_GPREG_X15 0x78 +#define CTX_GPREG_X16 0x80 +#define CTX_GPREG_X17 0x88 +#define CTX_GPREG_X18 0x90 +#define CTX_GPREG_X19 0x98 +#define CTX_GPREG_X20 0xa0 +#define CTX_GPREG_X21 0xa8 +#define CTX_GPREG_X22 0xb0 +#define CTX_GPREG_X23 0xb8 +#define CTX_GPREG_X24 0xc0 +#define CTX_GPREG_X25 0xc8 +#define CTX_GPREG_X26 0xd0 +#define CTX_GPREG_X27 0xd8 +#define CTX_GPREG_X28 0xe0 +#define CTX_GPREG_X29 0xe8 +#define CTX_GPREG_LR 0xf0 +#define CTX_GPREG_SP_EL0 0xf8 +#define CTX_GPREGS_END 0x100 + +/******************************************************************************* + * Constants that allow assembler code to access members of and the 'el3_state' + * structure at their correct offsets. Note that some of the registers are only + * 32-bits wide but are stored as 64-bit values for convenience + ******************************************************************************/ +#define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) +#define CTX_SCR_EL3 0x0 +#define CTX_RUNTIME_SP 0x8 +#define CTX_SPSR_EL3 0x10 +#define CTX_ELR_EL3 0x18 +#define CTX_EL3STATE_END 0x20 + +/******************************************************************************* + * Constants that allow assembler code to access members of and the + * 'el1_sys_regs' structure at their correct offsets. Note that some of the + * registers are only 32-bits wide but are stored as 64-bit values for + * convenience + ******************************************************************************/ +#define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) +#define CTX_SPSR_EL1 0x0 +#define CTX_ELR_EL1 0x8 +#define CTX_SCTLR_EL1 0x10 +#define CTX_ACTLR_EL1 0x18 +#define CTX_CPACR_EL1 0x20 +#define CTX_CSSELR_EL1 0x28 +#define CTX_SP_EL1 0x30 +#define CTX_ESR_EL1 0x38 +#define CTX_TTBR0_EL1 0x40 +#define CTX_TTBR1_EL1 0x48 +#define CTX_MAIR_EL1 0x50 +#define CTX_AMAIR_EL1 0x58 +#define CTX_TCR_EL1 0x60 +#define CTX_TPIDR_EL1 0x68 +#define CTX_TPIDR_EL0 0x70 +#define CTX_TPIDRRO_EL0 0x78 +#define CTX_PAR_EL1 0x80 +#define CTX_FAR_EL1 0x88 +#define CTX_AFSR0_EL1 0x90 +#define CTX_AFSR1_EL1 0x98 +#define CTX_CONTEXTIDR_EL1 0xa0 +#define CTX_VBAR_EL1 0xa8 + +/* + * If the platform is AArch64-only, there is no need to save and restore these + * AArch32 registers. + */ +#if CTX_INCLUDE_AARCH32_REGS +#define CTX_SPSR_ABT 0xb0 +#define CTX_SPSR_UND 0xb8 +#define CTX_SPSR_IRQ 0xc0 +#define CTX_SPSR_FIQ 0xc8 +#define CTX_DACR32_EL2 0xd0 +#define CTX_IFSR32_EL2 0xd8 +#define CTX_FP_FPEXC32_EL2 0xe0 +#define CTX_TIMER_SYSREGS_OFF 0xf0 /* Align to the next 16 byte boundary */ +#else +#define CTX_TIMER_SYSREGS_OFF 0xb0 +#endif /* __CTX_INCLUDE_AARCH32_REGS__ */ + +/* + * If the timer registers aren't saved and restored, we don't have to reserve + * space for them in the context + */ +#if NS_TIMER_SWITCH +#define CTX_CNTP_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x0) +#define CTX_CNTP_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x8) +#define CTX_CNTV_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x10) +#define CTX_CNTV_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + 0x18) +#define CTX_CNTKCTL_EL1 (CTX_TIMER_SYSREGS_OFF + 0x20) +#define CTX_SYSREGS_END (CTX_TIMER_SYSREGS_OFF + 0x30) /* Align to the next 16 byte boundary */ +#else +#define CTX_SYSREGS_END CTX_TIMER_SYSREGS_OFF +#endif /* __NS_TIMER_SWITCH__ */ + +/******************************************************************************* + * Constants that allow assembler code to access members of and the 'fp_regs' + * structure at their correct offsets. + ******************************************************************************/ +#if CTX_INCLUDE_FPREGS +#define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) +#define CTX_FP_Q0 0x0 +#define CTX_FP_Q1 0x10 +#define CTX_FP_Q2 0x20 +#define CTX_FP_Q3 0x30 +#define CTX_FP_Q4 0x40 +#define CTX_FP_Q5 0x50 +#define CTX_FP_Q6 0x60 +#define CTX_FP_Q7 0x70 +#define CTX_FP_Q8 0x80 +#define CTX_FP_Q9 0x90 +#define CTX_FP_Q10 0xa0 +#define CTX_FP_Q11 0xb0 +#define CTX_FP_Q12 0xc0 +#define CTX_FP_Q13 0xd0 +#define CTX_FP_Q14 0xe0 +#define CTX_FP_Q15 0xf0 +#define CTX_FP_Q16 0x100 +#define CTX_FP_Q17 0x110 +#define CTX_FP_Q18 0x120 +#define CTX_FP_Q19 0x130 +#define CTX_FP_Q20 0x140 +#define CTX_FP_Q21 0x150 +#define CTX_FP_Q22 0x160 +#define CTX_FP_Q23 0x170 +#define CTX_FP_Q24 0x180 +#define CTX_FP_Q25 0x190 +#define CTX_FP_Q26 0x1a0 +#define CTX_FP_Q27 0x1b0 +#define CTX_FP_Q28 0x1c0 +#define CTX_FP_Q29 0x1d0 +#define CTX_FP_Q30 0x1e0 +#define CTX_FP_Q31 0x1f0 +#define CTX_FP_FPSR 0x200 +#define CTX_FP_FPCR 0x208 +#define CTX_FPREGS_END 0x210 +#endif + +#ifndef __ASSEMBLY__ + +#include +#include /* for CACHE_WRITEBACK_GRANULE */ +#include + +/* + * Common constants to help define the 'cpu_context' structure and its + * members below. + */ +#define DWORD_SHIFT 3 +#define DEFINE_REG_STRUCT(name, num_regs) \ + typedef struct name { \ + uint64_t _regs[num_regs]; \ + } __aligned(16) name##_t + +/* Constants to determine the size of individual context structures */ +#define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) +#define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT) +#if CTX_INCLUDE_FPREGS +#define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) +#endif +#define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) + +/* + * AArch64 general purpose register context structure. Usually x0-x18, + * lr are saved as the compiler is expected to preserve the remaining + * callee saved registers if used by the C runtime and the assembler + * does not touch the remaining. But in case of world switch during + * exception handling, we need to save the callee registers too. + */ +DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); + +/* + * AArch64 EL1 system register context structure for preserving the + * architectural state during switches from one security state to + * another in EL1. + */ +DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL); + +/* + * AArch64 floating point register context structure for preserving + * the floating point state during switches from one security state to + * another. + */ +#if CTX_INCLUDE_FPREGS +DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); +#endif + +/* + * Miscellaneous registers used by EL3 firmware to maintain its state + * across exception entries and exits + */ +DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); + +/* + * Macros to access members of any of the above structures using their + * offsets + */ +#define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> DWORD_SHIFT]) +#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> DWORD_SHIFT]) \ + = val) + +/* + * Top-level context structure which is used by EL3 firmware to + * preserve the state of a core at EL1 in one of the two security + * states and save enough EL3 meta data to be able to return to that + * EL and security state. The context management library will be used + * to ensure that SP_EL3 always points to an instance of this + * structure at exception entry and exit. Each instance will + * correspond to either the secure or the non-secure state. + */ +typedef struct cpu_context { + gp_regs_t gpregs_ctx; + el3_state_t el3state_ctx; + el1_sys_regs_t sysregs_ctx; +#if CTX_INCLUDE_FPREGS + fp_regs_t fpregs_ctx; +#endif +} cpu_context_t; + +/* Macros to access members of the 'cpu_context_t' structure */ +#define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) +#if CTX_INCLUDE_FPREGS +#define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) +#endif +#define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx) +#define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) + +/* + * Compile time assertions related to the 'cpu_context' structure to + * ensure that the assembler and the compiler view of the offsets of + * the structure members is the same. + */ +CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \ + assert_core_context_gp_offset_mismatch); +CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \ + assert_core_context_sys_offset_mismatch); +#if CTX_INCLUDE_FPREGS +CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \ + assert_core_context_fp_offset_mismatch); +#endif +CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \ + assert_core_context_el3state_offset_mismatch); + +/* + * Helper macro to set the general purpose registers that correspond to + * parameters in an aapcs_64 call i.e. x0-x7 + */ +#define set_aapcs_args0(ctx, x0) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ + } while (0) +#define set_aapcs_args1(ctx, x0, x1) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ + set_aapcs_args0(ctx, x0); \ + } while (0) +#define set_aapcs_args2(ctx, x0, x1, x2) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ + set_aapcs_args1(ctx, x0, x1); \ + } while (0) +#define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ + set_aapcs_args2(ctx, x0, x1, x2); \ + } while (0) +#define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ + set_aapcs_args3(ctx, x0, x1, x2, x3); \ + } while (0) +#define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ + set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ + } while (0) +#define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ + set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ + } while (0) +#define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ + write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ + set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ + } while (0) + +/******************************************************************************* + * Function prototypes + ******************************************************************************/ +void el1_sysregs_context_save(el1_sys_regs_t *regs); +void el1_sysregs_context_restore(el1_sys_regs_t *regs); +#if CTX_INCLUDE_FPREGS +void fpregs_context_save(fp_regs_t *regs); +void fpregs_context_restore(fp_regs_t *regs); +#endif + + +#undef CTX_SYSREG_ALL +#if CTX_INCLUDE_FPREGS +#undef CTX_FPREG_ALL +#endif +#undef CTX_GPREG_ALL +#undef CTX_EL3STATE_ALL + +#endif /* __ASSEMBLY__ */ + +#endif /* __CONTEXT_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/el3_runtime/context_mgmt.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/el3_runtime/context_mgmt.h new file mode 100644 index 0000000..676973c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/el3_runtime/context_mgmt.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CM_H__ +#define __CM_H__ + +#include + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct entry_point_info; + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void cm_init(void); +void *cm_get_context_by_index(unsigned int cpu_idx, + unsigned int security_state); +void cm_set_context_by_index(unsigned int cpu_idx, + void *context, + unsigned int security_state); +void *cm_get_context(uint32_t security_state); +void cm_set_context(void *context, uint32_t security_state); +void cm_init_my_context(const struct entry_point_info *ep); +void cm_init_context_by_index(unsigned int cpu_idx, + const struct entry_point_info *ep); +void cm_prepare_el3_exit(uint32_t security_state); + +#ifndef AARCH32 +void cm_el1_sysregs_context_save(uint32_t security_state); +void cm_el1_sysregs_context_restore(uint32_t security_state); +void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint); +void cm_set_elr_spsr_el3(uint32_t security_state, + uintptr_t entrypoint, uint32_t spsr); +void cm_write_scr_el3_bit(uint32_t security_state, + uint32_t bit_pos, + uint32_t value); +void cm_set_next_eret_context(uint32_t security_state); +uint32_t cm_get_scr_el3(uint32_t security_state); + + +void cm_init_context(uint64_t mpidr, + const struct entry_point_info *ep) __deprecated; + +void *cm_get_context_by_mpidr(uint64_t mpidr, + uint32_t security_state) __deprecated; +void cm_set_context_by_mpidr(uint64_t mpidr, + void *context, + uint32_t security_state) __deprecated; + +/* Inline definitions */ + +/******************************************************************************* + * This function is used to program the context that's used for exception + * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for + * the required security state + ******************************************************************************/ +static inline void cm_set_next_context(void *context) +{ +#if DEBUG + uint64_t sp_mode; + + /* + * Check that this function is called with SP_EL0 as the stack + * pointer + */ + __asm__ volatile("mrs %0, SPSel\n" + : "=r" (sp_mode)); + + assert(sp_mode == MODE_SP_EL0); +#endif + + __asm__ volatile("msr spsel, #1\n" + "mov sp, %0\n" + "msr spsel, #0\n" + : : "r" (context)); +} + +#else +void *cm_get_next_context(void); +#endif /* AARCH32 */ + +#endif /* __CM_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/el3_runtime/cpu_data.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/el3_runtime/cpu_data.h new file mode 100644 index 0000000..910b153 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/el3_runtime/cpu_data.h @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CPU_DATA_H__ +#define __CPU_DATA_H__ + +#ifdef AARCH32 + +#if CRASH_REPORTING +#error "Crash reporting is not supported in AArch32" +#endif +#define CPU_DATA_CPU_OPS_PTR 0x0 + +#else /* AARCH32 */ + +/* Offsets for the cpu_data structure */ +#define CPU_DATA_CRASH_BUF_OFFSET 0x18 +/* need enough space in crash buffer to save 8 registers */ +#define CPU_DATA_CRASH_BUF_SIZE 64 +#define CPU_DATA_CPU_OPS_PTR 0x10 + +#endif /* AARCH32 */ + +#if CRASH_REPORTING +#define CPU_DATA_LOG2SIZE 7 +#else +#define CPU_DATA_LOG2SIZE 6 +#endif + +#ifndef __ASSEMBLY__ + +#include +#include +#include +#include +#include + +/* Offsets for the cpu_data structure */ +#define CPU_DATA_PSCI_LOCK_OFFSET __builtin_offsetof\ + (cpu_data_t, psci_svc_cpu_data.pcpu_bakery_info) + +#if PLAT_PCPU_DATA_SIZE +#define CPU_DATA_PLAT_PCPU_OFFSET __builtin_offsetof\ + (cpu_data_t, platform_cpu_data) +#endif + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ + +/******************************************************************************* + * Cache of frequently used per-cpu data: + * Pointers to non-secure and secure security state contexts + * Address of the crash stack + * It is aligned to the cache line boundary to allow efficient concurrent + * manipulation of these pointers on different cpus + * + * TODO: Add other commonly used variables to this (tf_issues#90) + * + * The data structure and the _cpu_data accessors should not be used directly + * by components that have per-cpu members. The member access macros should be + * used for this. + ******************************************************************************/ +typedef struct cpu_data { +#ifndef AARCH32 + void *cpu_context[2]; +#endif + uintptr_t cpu_ops_ptr; +#if CRASH_REPORTING + u_register_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3]; +#endif + struct psci_cpu_data psci_svc_cpu_data; +#if PLAT_PCPU_DATA_SIZE + uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE]; +#endif +} __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t; + +#if CRASH_REPORTING +/* verify assembler offsets match data structures */ +CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof + (cpu_data_t, crash_buf), + assert_cpu_data_crash_stack_offset_mismatch); +#endif + +CASSERT((1 << CPU_DATA_LOG2SIZE) == sizeof(cpu_data_t), + assert_cpu_data_log2size_mismatch); + +CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof + (cpu_data_t, cpu_ops_ptr), + assert_cpu_data_cpu_ops_ptr_offset_mismatch); + +struct cpu_data *_cpu_data_by_index(uint32_t cpu_index); + +#ifndef AARCH32 +/* Return the cpu_data structure for the current CPU. */ +static inline struct cpu_data *_cpu_data(void) +{ + return (cpu_data_t *)read_tpidr_el3(); +} +#else +struct cpu_data *_cpu_data(void); +#endif + +/************************************************************************** + * APIs for initialising and accessing per-cpu data + *************************************************************************/ + +void init_cpu_data_ptr(void); +void init_cpu_ops(void); + +#define get_cpu_data(_m) _cpu_data()->_m +#define set_cpu_data(_m, _v) _cpu_data()->_m = _v +#define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m +#define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = _v + +#define flush_cpu_data(_m) flush_dcache_range((uintptr_t) \ + &(_cpu_data()->_m), \ + sizeof(_cpu_data()->_m)) +#define inv_cpu_data(_m) inv_dcache_range((uintptr_t) \ + &(_cpu_data()->_m), \ + sizeof(_cpu_data()->_m)) +#define flush_cpu_data_by_index(_ix, _m) \ + flush_dcache_range((uintptr_t) \ + &(_cpu_data_by_index(_ix)->_m), \ + sizeof(_cpu_data_by_index(_ix)->_m)) + + +#endif /* __ASSEMBLY__ */ +#endif /* __CPU_DATA_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/libfdt/fdt.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/libfdt/fdt.h new file mode 100644 index 0000000..6331998 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/libfdt/fdt.h @@ -0,0 +1,119 @@ +#ifndef _FDT_H +#define _FDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * Copyright 2012 Kim Phillips, Freescale Semiconductor. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Portions copyright (c) 2016, ARM Limited and Contributors. + * All rights reserved. + */ + +#ifndef __ASSEMBLY__ + +#include + + +struct fdt_header { + fdt32_t magic; /* magic word FDT_MAGIC */ + fdt32_t totalsize; /* total size of DT block */ + fdt32_t off_dt_struct; /* offset to structure */ + fdt32_t off_dt_strings; /* offset to strings */ + fdt32_t off_mem_rsvmap; /* offset to memory reserve map */ + fdt32_t version; /* format version */ + fdt32_t last_comp_version; /* last compatible version */ + + /* version 2 fields below */ + fdt32_t boot_cpuid_phys; /* Which physical CPU id we're + booting on */ + /* version 3 fields below */ + fdt32_t size_dt_strings; /* size of the strings block */ + + /* version 17 fields below */ + fdt32_t size_dt_struct; /* size of the structure block */ +}; + +struct fdt_reserve_entry { + fdt64_t address; + fdt64_t size; +}; + +struct fdt_node_header { + fdt32_t tag; + char name[]; +}; + +struct fdt_property { + fdt32_t tag; + fdt32_t len; + fdt32_t nameoff; + char data[]; +}; + +#endif /* !__ASSEMBLY */ + +#define FDT_MAGIC 0xd00dfeed /* 4: version, 4: total size */ +#define FDT_TAGSIZE sizeof(fdt32_t) + +#define FDT_BEGIN_NODE 0x1 /* Start node: full name */ +#define FDT_END_NODE 0x2 /* End node */ +#define FDT_PROP 0x3 /* Property: name off, + size, content */ +#define FDT_NOP 0x4 /* nop */ +#define FDT_END 0x9 + +#define FDT_V1_SIZE (7*sizeof(fdt32_t)) +#define FDT_V2_SIZE (FDT_V1_SIZE + sizeof(fdt32_t)) +#define FDT_V3_SIZE (FDT_V2_SIZE + sizeof(fdt32_t)) +#define FDT_V16_SIZE FDT_V3_SIZE +#define FDT_V17_SIZE (FDT_V16_SIZE + sizeof(fdt32_t)) + +#endif /* _FDT_H */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/libfdt/libfdt.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/libfdt/libfdt.h new file mode 100644 index 0000000..74f4895 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/libfdt/libfdt.h @@ -0,0 +1,1580 @@ +#ifndef _LIBFDT_H +#define _LIBFDT_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Portions copyright (c) 2016, ARM Limited and Contributors. + * All rights reserved. + */ + +#include +#include + +#define FDT_FIRST_SUPPORTED_VERSION 0x10 +#define FDT_LAST_SUPPORTED_VERSION 0x11 + +/* Error codes: informative error codes */ +#define FDT_ERR_NOTFOUND 1 + /* FDT_ERR_NOTFOUND: The requested node or property does not exist */ +#define FDT_ERR_EXISTS 2 + /* FDT_ERR_EXISTS: Attemped to create a node or property which + * already exists */ +#define FDT_ERR_NOSPACE 3 + /* FDT_ERR_NOSPACE: Operation needed to expand the device + * tree, but its buffer did not have sufficient space to + * contain the expanded tree. Use fdt_open_into() to move the + * device tree to a buffer with more space. */ + +/* Error codes: codes for bad parameters */ +#define FDT_ERR_BADOFFSET 4 + /* FDT_ERR_BADOFFSET: Function was passed a structure block + * offset which is out-of-bounds, or which points to an + * unsuitable part of the structure for the operation. */ +#define FDT_ERR_BADPATH 5 + /* FDT_ERR_BADPATH: Function was passed a badly formatted path + * (e.g. missing a leading / for a function which requires an + * absolute path) */ +#define FDT_ERR_BADPHANDLE 6 + /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle + * value. phandle values of 0 and -1 are not permitted. */ +#define FDT_ERR_BADSTATE 7 + /* FDT_ERR_BADSTATE: Function was passed an incomplete device + * tree created by the sequential-write functions, which is + * not sufficiently complete for the requested operation. */ + +/* Error codes: codes for bad device tree blobs */ +#define FDT_ERR_TRUNCATED 8 + /* FDT_ERR_TRUNCATED: Structure block of the given device tree + * ends without an FDT_END tag. */ +#define FDT_ERR_BADMAGIC 9 + /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a + * device tree at all - it is missing the flattened device + * tree magic number. */ +#define FDT_ERR_BADVERSION 10 + /* FDT_ERR_BADVERSION: Given device tree has a version which + * can't be handled by the requested operation. For + * read-write functions, this may mean that fdt_open_into() is + * required to convert the tree to the expected version. */ +#define FDT_ERR_BADSTRUCTURE 11 + /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt + * structure block or other serious error (e.g. misnested + * nodes, or subnodes preceding properties). */ +#define FDT_ERR_BADLAYOUT 12 + /* FDT_ERR_BADLAYOUT: For read-write functions, the given + * device tree has it's sub-blocks in an order that the + * function can't handle (memory reserve map, then structure, + * then strings). Use fdt_open_into() to reorganize the tree + * into a form suitable for the read-write operations. */ + +/* "Can't happen" error indicating a bug in libfdt */ +#define FDT_ERR_INTERNAL 13 + /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion. + * Should never be returned, if it is, it indicates a bug in + * libfdt itself. */ + +/* Errors in device tree content */ +#define FDT_ERR_BADNCELLS 14 + /* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells + * or similar property with a bad format or value */ + +#define FDT_ERR_MAX 14 + +/**********************************************************************/ +/* Low-level functions (you probably don't need these) */ +/**********************************************************************/ + +const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen); +static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen) +{ + return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen); +} + +uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); + +/**********************************************************************/ +/* Traversal functions */ +/**********************************************************************/ + +int fdt_next_node(const void *fdt, int offset, int *depth); + +/** + * fdt_first_subnode() - get offset of first direct subnode + * + * @fdt: FDT blob + * @offset: Offset of node to check + * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none + */ +int fdt_first_subnode(const void *fdt, int offset); + +/** + * fdt_next_subnode() - get offset of next direct subnode + * + * After first calling fdt_first_subnode(), call this function repeatedly to + * get direct subnodes of a parent node. + * + * @fdt: FDT blob + * @offset: Offset of previous subnode + * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more + * subnodes + */ +int fdt_next_subnode(const void *fdt, int offset); + +/**********************************************************************/ +/* General functions */ +/**********************************************************************/ + +#define fdt_get_header(fdt, field) \ + (fdt32_to_cpu(((const struct fdt_header *)(fdt))->field)) +#define fdt_magic(fdt) (fdt_get_header(fdt, magic)) +#define fdt_totalsize(fdt) (fdt_get_header(fdt, totalsize)) +#define fdt_off_dt_struct(fdt) (fdt_get_header(fdt, off_dt_struct)) +#define fdt_off_dt_strings(fdt) (fdt_get_header(fdt, off_dt_strings)) +#define fdt_off_mem_rsvmap(fdt) (fdt_get_header(fdt, off_mem_rsvmap)) +#define fdt_version(fdt) (fdt_get_header(fdt, version)) +#define fdt_last_comp_version(fdt) (fdt_get_header(fdt, last_comp_version)) +#define fdt_boot_cpuid_phys(fdt) (fdt_get_header(fdt, boot_cpuid_phys)) +#define fdt_size_dt_strings(fdt) (fdt_get_header(fdt, size_dt_strings)) +#define fdt_size_dt_struct(fdt) (fdt_get_header(fdt, size_dt_struct)) + +#define __fdt_set_hdr(name) \ + static inline void fdt_set_##name(void *fdt, uint32_t val) \ + { \ + struct fdt_header *fdth = (struct fdt_header*)fdt; \ + fdth->name = cpu_to_fdt32(val); \ + } +__fdt_set_hdr(magic) +__fdt_set_hdr(totalsize) +__fdt_set_hdr(off_dt_struct) +__fdt_set_hdr(off_dt_strings) +__fdt_set_hdr(off_mem_rsvmap) +__fdt_set_hdr(version) +__fdt_set_hdr(last_comp_version) +__fdt_set_hdr(boot_cpuid_phys) +__fdt_set_hdr(size_dt_strings) +__fdt_set_hdr(size_dt_struct) +#undef __fdt_set_hdr + +/** + * fdt_check_header - sanity check a device tree or possible device tree + * @fdt: pointer to data which might be a flattened device tree + * + * fdt_check_header() checks that the given buffer contains what + * appears to be a flattened device tree with sane information in its + * header. + * + * returns: + * 0, if the buffer appears to contain a valid device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings, as above + */ +int fdt_check_header(const void *fdt); + +/** + * fdt_move - move a device tree around in memory + * @fdt: pointer to the device tree to move + * @buf: pointer to memory where the device is to be moved + * @bufsize: size of the memory space at buf + * + * fdt_move() relocates, if possible, the device tree blob located at + * fdt to the buffer at buf of size bufsize. The buffer may overlap + * with the existing device tree blob at fdt. Therefore, + * fdt_move(fdt, fdt, fdt_totalsize(fdt)) + * should always succeed. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_move(const void *fdt, void *buf, int bufsize); + +/**********************************************************************/ +/* Read-only functions */ +/**********************************************************************/ + +/** + * fdt_string - retrieve a string from the strings block of a device tree + * @fdt: pointer to the device tree blob + * @stroffset: offset of the string within the strings block (native endian) + * + * fdt_string() retrieves a pointer to a single string from the + * strings block of the device tree blob at fdt. + * + * returns: + * a pointer to the string, on success + * NULL, if stroffset is out of bounds + */ +const char *fdt_string(const void *fdt, int stroffset); + +/** + * fdt_num_mem_rsv - retrieve the number of memory reserve map entries + * @fdt: pointer to the device tree blob + * + * Returns the number of entries in the device tree blob's memory + * reservation map. This does not include the terminating 0,0 entry + * or any other (0,0) entries reserved for expansion. + * + * returns: + * the number of entries + */ +int fdt_num_mem_rsv(const void *fdt); + +/** + * fdt_get_mem_rsv - retrieve one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: pointers to 64-bit variables + * + * On success, *address and *size will contain the address and size of + * the n-th reserve map entry from the device tree blob, in + * native-endian format. + * + * returns: + * 0, on success + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size); + +/** + * fdt_subnode_offset_namelen - find a subnode based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_subnode_offset(), but only examine the first + * namelen characters of name for matching the subnode name. This is + * useful for finding subnodes based on a portion of a larger string, + * such as a full path. + */ +int fdt_subnode_offset_namelen(const void *fdt, int parentoffset, + const char *name, int namelen); +/** + * fdt_subnode_offset - find a subnode of a given node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_subnode_offset() finds a subnode of the node at structure block + * offset parentoffset with the given name. name may include a unit + * address, in which case fdt_subnode_offset() will find the subnode + * with that unit address, or the unit address may be omitted, in + * which case fdt_subnode_offset() will find an arbitrary subnode + * whose name excluding unit address matches the given name. + * + * returns: + * structure block offset of the requested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name); + +/** + * fdt_path_offset - find a tree node by its full path + * @fdt: pointer to the device tree blob + * @path: full path of the node to locate + * + * fdt_path_offset() finds a node of a given path in the device tree. + * Each path component may omit the unit address portion, but the + * results of this are undefined if any such path component is + * ambiguous (that is if there are multiple nodes at the relevant + * level matching the given component, differentiated only by unit + * address). + * + * returns: + * structure block offset of the node with the requested path (>=0), on success + * -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid + * -FDT_ERR_NOTFOUND, if the requested node does not exist + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_path_offset(const void *fdt, const char *path); + +/** + * fdt_get_name - retrieve the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the starting node + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_name() retrieves the name (including unit address) of the + * device tree node at structure block offset nodeoffset. If lenp is + * non-NULL, the length of this name is also returned, in the integer + * pointed to by lenp. + * + * returns: + * pointer to the node's name, on success + * If lenp is non-NULL, *lenp contains the length of that name (>=0) + * NULL, on error + * if lenp is non-NULL *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp); + +/** + * fdt_first_property_offset - find the offset of a node's first property + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * + * fdt_first_property_offset() finds the first property of the node at + * the given structure block offset. + * + * returns: + * structure block offset of the property (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested node has no properties + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_first_property_offset(const void *fdt, int nodeoffset); + +/** + * fdt_next_property_offset - step through a node's properties + * @fdt: pointer to the device tree blob + * @offset: structure block offset of a property + * + * fdt_next_property_offset() finds the property immediately after the + * one at the given structure block offset. This will be a property + * of the same node as the given property. + * + * returns: + * structure block offset of the next property (>=0), on success + * -FDT_ERR_NOTFOUND, if the given property is the last in its node + * -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_next_property_offset(const void *fdt, int offset); + +/** + * fdt_get_property_by_offset - retrieve the property at a given offset + * @fdt: pointer to the device tree blob + * @offset: offset of the property to retrieve + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property_by_offset() retrieves a pointer to the + * fdt_property structure within the device tree blob at the given + * offset. If lenp is non-NULL, the length of the property value is + * also returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp); + +/** + * fdt_get_property_namelen - find a property based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_get_property_namelen(), but only examine the first + * namelen characters of name for matching the property name. + */ +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int nodeoffset, + const char *name, + int namelen, int *lenp); + +/** + * fdt_get_property - find a given property in a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_get_property() retrieves a pointer to the fdt_property + * structure within the device tree blob corresponding to the property + * named 'name' of the node at offset nodeoffset. If lenp is + * non-NULL, the length of the property value is also returned, in the + * integer pointed to by lenp. + * + * returns: + * pointer to the structure representing the property + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset, + const char *name, + int *lenp) +{ + return (struct fdt_property *)(uintptr_t) + fdt_get_property(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_getprop_by_offset - retrieve the value of a property at a given offset + * @fdt: pointer to the device tree blob + * @ffset: offset of the property to read + * @namep: pointer to a string variable (will be overwritten) or NULL + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop_by_offset() retrieves a pointer to the value of the + * property at structure block offset 'offset' (this will be a pointer + * to within the device blob itself, not a copy of the value). If + * lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. If namep is non-NULL, + * the property's namne will also be returned in the char * pointed to + * by namep (this will be a pointer to within the device tree's string + * block, not a new copy of the name). + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * if namep is non-NULL *namep contiains a pointer to the property + * name. + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp); + +/** + * fdt_getprop_namelen - get property value based on substring + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @namelen: number of characters of name to consider + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * Identical to fdt_getprop(), but only examine the first namelen + * characters of name for matching the property name. + */ +const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, + const char *name, int namelen, int *lenp); + +/** + * fdt_getprop - retrieve the value of a given property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to find + * @name: name of the property to find + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop() retrieves a pointer to the value of the property + * named 'name' of the node at offset nodeoffset (this will be a + * pointer to within the device blob itself, not a copy of the value). + * If lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_getprop(const void *fdt, int nodeoffset, + const char *name, int *lenp); +static inline void *fdt_getprop_w(void *fdt, int nodeoffset, + const char *name, int *lenp) +{ + return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp); +} + +/** + * fdt_get_phandle - retrieve the phandle of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of the node + * + * fdt_get_phandle() retrieves the phandle of the device tree node at + * structure block offset nodeoffset. + * + * returns: + * the phandle of the node at nodeoffset, on success (!= 0, != -1) + * 0, if the node has no phandle, or another error occurs + */ +uint32_t fdt_get_phandle(const void *fdt, int nodeoffset); + +/** + * fdt_get_alias_namelen - get alias based on substring + * @fdt: pointer to the device tree blob + * @name: name of the alias th look up + * @namelen: number of characters of name to consider + * + * Identical to fdt_get_alias(), but only examine the first namelen + * characters of name for matching the alias name. + */ +const char *fdt_get_alias_namelen(const void *fdt, + const char *name, int namelen); + +/** + * fdt_get_alias - retreive the path referenced by a given alias + * @fdt: pointer to the device tree blob + * @name: name of the alias th look up + * + * fdt_get_alias() retrieves the value of a given alias. That is, the + * value of the property named 'name' in the node /aliases. + * + * returns: + * a pointer to the expansion of the alias named 'name', if it exists + * NULL, if the given alias or the /aliases node does not exist + */ +const char *fdt_get_alias(const void *fdt, const char *name); + +/** + * fdt_get_path - determine the full path of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose path to find + * @buf: character buffer to contain the returned path (will be overwritten) + * @buflen: size of the character buffer at buf + * + * fdt_get_path() computes the full path of the node at offset + * nodeoffset, and records that path in the buffer at buf. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * 0, on success + * buf contains the absolute path of the node at + * nodeoffset, as a NUL-terminated string. + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1) + * characters and will not fit in the given buffer. + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen); + +/** + * fdt_supernode_atdepth_offset - find a specific ancestor of a node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * @supernodedepth: depth of the ancestor to find + * @nodedepth: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_supernode_atdepth_offset() finds an ancestor of the given node + * at a specific depth from the root (where the root itself has depth + * 0, its immediate subnodes depth 1 and so forth). So + * fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL); + * will always return 0, the offset of the root node. If the node at + * nodeoffset has depth D, then: + * fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL); + * will return nodeoffset itself. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + + * structure block offset of the node at node offset's ancestor + * of depth supernodedepth (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag +* -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, + int supernodedepth, int *nodedepth); + +/** + * fdt_node_depth - find the depth of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_node_depth() finds the depth of a given node. The root node + * has depth 0, its immediate subnodes depth 1 and so forth. + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset. + * + * returns: + * depth of the node at nodeoffset (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_depth(const void *fdt, int nodeoffset); + +/** + * fdt_parent_offset - find the parent of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose parent to find + * + * fdt_parent_offset() locates the parent node of a given node (that + * is, it finds the offset of the node which contains the node at + * nodeoffset as a subnode). + * + * NOTE: This function is expensive, as it must scan the device tree + * structure from the start to nodeoffset, *twice*. + * + * returns: + * structure block offset of the parent of the node at nodeoffset + * (>=0), on success + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_parent_offset(const void *fdt, int nodeoffset); + +/** + * fdt_node_offset_by_prop_value - find nodes with a given property value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @propname: property name to check + * @propval: property value to search for + * @proplen: length of the value in propval + * + * fdt_node_offset_by_prop_value() returns the offset of the first + * node after startoffset, which has a property named propname whose + * value is of length proplen and has value equal to propval; or if + * startoffset is -1, the very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_prop_value(fdt, -1, propname, + * propval, proplen); + * while (offset != -FDT_ERR_NOTFOUND) { + * // other code here + * offset = fdt_node_offset_by_prop_value(fdt, offset, propname, + * propval, proplen); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, + const char *propname, + const void *propval, int proplen); + +/** + * fdt_node_offset_by_phandle - find the node with a given phandle + * @fdt: pointer to the device tree blob + * @phandle: phandle value + * + * fdt_node_offset_by_phandle() returns the offset of the node + * which has the given phandle value. If there is more than one node + * in the tree with the given phandle (an invalid tree), results are + * undefined. + * + * returns: + * structure block offset of the located node (>= 0), on success + * -FDT_ERR_NOTFOUND, no node with that phandle exists + * -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle); + +/** + * fdt_node_check_compatible: check a node's compatible property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of a tree node + * @compatible: string to match against + * + * + * fdt_node_check_compatible() returns 0 if the given node contains a + * 'compatible' property with the given string as one of its elements, + * it returns non-zero otherwise, or on error. + * + * returns: + * 0, if the node has a 'compatible' property listing the given string + * 1, if the node has a 'compatible' property, but it does not list + * the given string + * -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property + * -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_check_compatible(const void *fdt, int nodeoffset, + const char *compatible); + +/** + * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value + * @fdt: pointer to the device tree blob + * @startoffset: only find nodes after this offset + * @compatible: 'compatible' string to match against + * + * fdt_node_offset_by_compatible() returns the offset of the first + * node after startoffset, which has a 'compatible' property which + * lists the given compatible string; or if startoffset is -1, the + * very first such node in the tree. + * + * To iterate through all nodes matching the criterion, the following + * idiom can be used: + * offset = fdt_node_offset_by_compatible(fdt, -1, compatible); + * while (offset != -FDT_ERR_NOTFOUND) { + * // other code here + * offset = fdt_node_offset_by_compatible(fdt, offset, compatible); + * } + * + * Note the -1 in the first call to the function, if 0 is used here + * instead, the function will never locate the root node, even if it + * matches the criterion. + * + * returns: + * structure block offset of the located node (>= 0, >startoffset), + * on success + * -FDT_ERR_NOTFOUND, no node matching the criterion exists in the + * tree after startoffset + * -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, standard meanings + */ +int fdt_node_offset_by_compatible(const void *fdt, int startoffset, + const char *compatible); + +/** + * fdt_stringlist_contains - check a string list property for a string + * @strlist: Property containing a list of strings to check + * @listlen: Length of property + * @str: String to search for + * + * This is a utility function provided for convenience. The list contains + * one or more strings, each terminated by \0, as is found in a device tree + * "compatible" property. + * + * @return: 1 if the string is found in the list, 0 not found, or invalid list + */ +int fdt_stringlist_contains(const char *strlist, int listlen, const char *str); + +/**********************************************************************/ +/* Read-only functions (addressing related) */ +/**********************************************************************/ + +/** + * FDT_MAX_NCELLS - maximum value for #address-cells and #size-cells + * + * This is the maximum value for #address-cells, #size-cells and + * similar properties that will be processed by libfdt. IEE1275 + * requires that OF implementations handle values up to 4. + * Implementations may support larger values, but in practice higher + * values aren't used. + */ +#define FDT_MAX_NCELLS 4 + +/** + * fdt_address_cells - retrieve address size for a bus represented in the tree + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to find the address size for + * + * When the node has a valid #address-cells property, returns its value. + * + * returns: + * 0 <= n < FDT_MAX_NCELLS, on success + * 2, if the node has no #address-cells property + * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid #address-cells property + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_address_cells(const void *fdt, int nodeoffset); + +/** + * fdt_size_cells - retrieve address range size for a bus represented in the + * tree + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to find the address range size for + * + * When the node has a valid #size-cells property, returns its value. + * + * returns: + * 0 <= n < FDT_MAX_NCELLS, on success + * 2, if the node has no #address-cells property + * -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid #size-cells property + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_size_cells(const void *fdt, int nodeoffset); + + +/**********************************************************************/ +/* Write-in-place functions */ +/**********************************************************************/ + +/** + * fdt_setprop_inplace - change a property's value, but not its size + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to replace the property value with + * @len: length of the property value + * + * fdt_setprop_inplace() replaces the value of a given property with + * the data in val, of length len. This function cannot change the + * size of a property, and so will only work if len is equal to the + * current length of the property. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if len is not equal to the property's current length + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to replace the property with + * + * fdt_setprop_inplace_u32() replaces the value of a given property + * with the 32-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 4. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 4 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to replace the property with + * + * fdt_setprop_inplace_u64() replaces the value of a given property + * with the 64-bit integer value in val, converting val to big-endian + * if necessary. This function cannot change the size of a property, + * and so will only work if the property already exists and has length + * 8. + * + * This function will alter only the bytes in the blob which contain + * the given property value, and will not alter or move any other part + * of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, if the property's length is not equal to 8 + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_inplace_cell - change the value of a single-cell property + * + * This is an alternative name for fdt_setprop_inplace_u32() + */ +static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_nop_property - replace a property with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_nop_property() will replace a given property's representation + * in the blob with FDT_NOP tags, effectively removing it from the + * tree. + * + * This function will alter only the bytes in the blob which contain + * the property, and will not alter or move any other part of the + * tree. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_property(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_nop_node - replace a node (subtree) with nop tags + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_nop_node() will replace a given node's representation in the + * blob, including all its subnodes, if any, with FDT_NOP tags, + * effectively removing it from the tree. + * + * This function will alter only the bytes in the blob which contain + * the node and its properties and subnodes, and will not alter or + * move any other part of the tree. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_nop_node(void *fdt, int nodeoffset); + +/**********************************************************************/ +/* Sequential write functions */ +/**********************************************************************/ + +int fdt_create(void *buf, int bufsize); +int fdt_resize(void *fdt, void *buf, int bufsize); +int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size); +int fdt_finish_reservemap(void *fdt); +int fdt_begin_node(void *fdt, const char *name); +int fdt_property(void *fdt, const char *name, const void *val, int len); +static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_property(fdt, name, &tmp, sizeof(tmp)); +} +static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val) +{ + return fdt_property_u32(fdt, name, val); +} +#define fdt_property_string(fdt, name, str) \ + fdt_property(fdt, name, str, strlen(str)+1) +int fdt_end_node(void *fdt); +int fdt_finish(void *fdt); + +/**********************************************************************/ +/* Read-write functions */ +/**********************************************************************/ + +int fdt_create_empty_tree(void *buf, int bufsize); +int fdt_open_into(const void *fdt, void *buf, int bufsize); +int fdt_pack(void *fdt); + +/** + * fdt_add_mem_rsv - add one memory reserve map entry + * @fdt: pointer to the device tree blob + * @address, @size: 64-bit values (native endian) + * + * Adds a reserve map entry to the given blob reserving a region at + * address address of length size. + * + * This function will insert data into the reserve map and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new reservation entry + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size); + +/** + * fdt_del_mem_rsv - remove a memory reserve map entry + * @fdt: pointer to the device tree blob + * @n: entry to remove + * + * fdt_del_mem_rsv() removes the n-th memory reserve map entry from + * the blob. + * + * This function will delete data from the reservation table and will + * therefore change the indexes of some entries in the table. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there + * are less than n+1 reserve map entries) + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_mem_rsv(void *fdt, int n); + +/** + * fdt_set_name - change the name of a given node + * @fdt: pointer to the device tree blob + * @nodeoffset: structure block offset of a node + * @name: name to give the node + * + * fdt_set_name() replaces the name (including unit address, if any) + * of the given node with the given string. NOTE: this function can't + * efficiently check if the new name is unique amongst the given + * node's siblings; results are undefined if this function is invoked + * with a name equal to one of the given node's siblings. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob + * to contain the new name + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, standard meanings + */ +int fdt_set_name(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_setprop - create or change a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: pointer to data to set the property value to + * @len: length of the property value + * + * fdt_setprop() sets the value of the named property in the given + * node to the given value and length, creating the property if it + * does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_setprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_setprop_u32 - set a property to a 32-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value for the property (native endian) + * + * fdt_setprop_u32() sets the value of the named property in the given + * node to the given 32-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_u64 - set a property to a 64-bit integer + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value for the property (native endian) + * + * fdt_setprop_u64() sets the value of the named property in the given + * node to the given 64-bit integer value (converting to big-endian if + * necessary), or creates a new property with that value if it does + * not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name, + uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_setprop_cell - set a property to a single cell value + * + * This is an alternative name for fdt_setprop_u32() + */ +static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name, + uint32_t val) +{ + return fdt_setprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_setprop_string - set a property to a string value + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value for the property + * + * fdt_setprop_string() sets the value of the named property in the + * given node to the given string value (using the length of the + * string to determine the new length of the property), or creates a + * new property with that value if it does not already exist. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_setprop_string(fdt, nodeoffset, name, str) \ + fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** + * fdt_appendprop - append to or create a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to append to + * @val: pointer to data to append to the property value + * @len: length of the data to append to the property value + * + * fdt_appendprop() appends the value to the named property in the + * given node, creating the property if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len); + +/** + * fdt_appendprop_u32 - append a 32-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 32-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u32() appends the given 32-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u32(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + fdt32_t tmp = cpu_to_fdt32(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_u64 - append a 64-bit integer value to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @val: 64-bit integer value to append to the property (native endian) + * + * fdt_appendprop_u64() appends the given 64-bit integer value + * (converting to big-endian if necessary) to the value of the named + * property in the given node, or creates a new property with that + * value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +static inline int fdt_appendprop_u64(void *fdt, int nodeoffset, + const char *name, uint64_t val) +{ + fdt64_t tmp = cpu_to_fdt64(val); + return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); +} + +/** + * fdt_appendprop_cell - append a single cell value to a property + * + * This is an alternative name for fdt_appendprop_u32() + */ +static inline int fdt_appendprop_cell(void *fdt, int nodeoffset, + const char *name, uint32_t val) +{ + return fdt_appendprop_u32(fdt, nodeoffset, name, val); +} + +/** + * fdt_appendprop_string - append a string to a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to change + * @name: name of the property to change + * @str: string value to append to the property + * + * fdt_appendprop_string() appends the given string to the value of + * the named property in the given node, or creates a new property + * with that value if it does not already exist. + * + * This function may insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +#define fdt_appendprop_string(fdt, nodeoffset, name, str) \ + fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1) + +/** + * fdt_delprop - delete a property + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node whose property to nop + * @name: name of the property to nop + * + * fdt_del_property() will delete the given property. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOTFOUND, node does not have the named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_delprop(void *fdt, int nodeoffset, const char *name); + +/** + * fdt_add_subnode_namelen - creates a new node based on substring + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * @namelen: number of characters of name to consider + * + * Identical to fdt_add_subnode(), but use only the first namelen + * characters of name as the name of the new node. This is useful for + * creating subnodes based on a portion of a larger string, such as a + * full path. + */ +int fdt_add_subnode_namelen(void *fdt, int parentoffset, + const char *name, int namelen); + +/** + * fdt_add_subnode - creates a new node + * @fdt: pointer to the device tree blob + * @parentoffset: structure block offset of a node + * @name: name of the subnode to locate + * + * fdt_add_subnode() creates a new node as a subnode of the node at + * structure block offset parentoffset, with the given name (which + * should include the unit address, if any). + * + * This function will insert data into the blob, and will therefore + * change the offsets of some existing nodes. + + * returns: + * structure block offset of the created nodeequested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of + * the given name + * -FDT_ERR_NOSPACE, if there is insufficient free space in the + * blob to contain the new node + * -FDT_ERR_NOSPACE + * -FDT_ERR_BADLAYOUT + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_add_subnode(void *fdt, int parentoffset, const char *name); + +/** + * fdt_del_node - delete a node (subtree) + * @fdt: pointer to the device tree blob + * @nodeoffset: offset of the node to nop + * + * fdt_del_node() will remove the given node, including all its + * subnodes if any, from the blob. + * + * This function will delete data from the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_del_node(void *fdt, int nodeoffset); + +/**********************************************************************/ +/* Debugging / informational functions */ +/**********************************************************************/ + +const char *fdt_strerror(int errval); + +#endif /* _LIBFDT_H */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/libfdt/libfdt_env.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/libfdt/libfdt_env.h new file mode 100644 index 0000000..9dea97d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/libfdt/libfdt_env.h @@ -0,0 +1,111 @@ +#ifndef _LIBFDT_ENV_H +#define _LIBFDT_ENV_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * Copyright 2012 Kim Phillips, Freescale Semiconductor. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#ifdef __CHECKER__ +#define __force __attribute__((force)) +#define __bitwise __attribute__((bitwise)) +#else +#define __force +#define __bitwise +#endif + +typedef uint16_t __bitwise fdt16_t; +typedef uint32_t __bitwise fdt32_t; +typedef uint64_t __bitwise fdt64_t; + +#define EXTRACT_BYTE(x, n) ((unsigned long long)((uint8_t *)&x)[n]) +#define CPU_TO_FDT16(x) ((EXTRACT_BYTE(x, 0) << 8) | EXTRACT_BYTE(x, 1)) +#define CPU_TO_FDT32(x) ((EXTRACT_BYTE(x, 0) << 24) | (EXTRACT_BYTE(x, 1) << 16) | \ + (EXTRACT_BYTE(x, 2) << 8) | EXTRACT_BYTE(x, 3)) +#define CPU_TO_FDT64(x) ((EXTRACT_BYTE(x, 0) << 56) | (EXTRACT_BYTE(x, 1) << 48) | \ + (EXTRACT_BYTE(x, 2) << 40) | (EXTRACT_BYTE(x, 3) << 32) | \ + (EXTRACT_BYTE(x, 4) << 24) | (EXTRACT_BYTE(x, 5) << 16) | \ + (EXTRACT_BYTE(x, 6) << 8) | EXTRACT_BYTE(x, 7)) + +static inline uint16_t fdt16_to_cpu(fdt16_t x) +{ + return (__force uint16_t)CPU_TO_FDT16(x); +} +static inline fdt16_t cpu_to_fdt16(uint16_t x) +{ + return (__force fdt16_t)CPU_TO_FDT16(x); +} + +static inline uint32_t fdt32_to_cpu(fdt32_t x) +{ + return (__force uint32_t)CPU_TO_FDT32(x); +} +static inline fdt32_t cpu_to_fdt32(uint32_t x) +{ + return (__force fdt32_t)CPU_TO_FDT32(x); +} + +static inline uint64_t fdt64_to_cpu(fdt64_t x) +{ + return (__force uint64_t)CPU_TO_FDT64(x); +} +static inline fdt64_t cpu_to_fdt64(uint64_t x) +{ + return (__force fdt64_t)CPU_TO_FDT64(x); +} +#undef CPU_TO_FDT64 +#undef CPU_TO_FDT32 +#undef CPU_TO_FDT16 +#undef EXTRACT_BYTE + +#endif /* _LIBFDT_ENV_H */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/mmio.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/mmio.h new file mode 100644 index 0000000..19f798f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/mmio.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MMIO_H__ +#define __MMIO_H__ + +#include + +static inline void mmio_write_8(uintptr_t addr, uint8_t value) +{ + *(volatile uint8_t*)addr = value; +} + +static inline uint8_t mmio_read_8(uintptr_t addr) +{ + return *(volatile uint8_t*)addr; +} + +static inline void mmio_write_16(uintptr_t addr, uint16_t value) +{ + *(volatile uint16_t*)addr = value; +} + +static inline uint16_t mmio_read_16(uintptr_t addr) +{ + return *(volatile uint16_t*)addr; +} + +static inline void mmio_write_32(uintptr_t addr, uint32_t value) +{ + *(volatile uint32_t*)addr = value; +} + +static inline uint32_t mmio_read_32(uintptr_t addr) +{ + return *(volatile uint32_t*)addr; +} + +static inline void mmio_write_64(uintptr_t addr, uint64_t value) +{ + *(volatile uint64_t*)addr = value; +} + +static inline uint64_t mmio_read_64(uintptr_t addr) +{ + return *(volatile uint64_t*)addr; +} + +static inline void mmio_clrbits_32(uintptr_t addr, uint32_t clear) +{ + mmio_write_32(addr, mmio_read_32(addr) & ~clear); +} + +static inline void mmio_setbits_32(uintptr_t addr, uint32_t set) +{ + mmio_write_32(addr, mmio_read_32(addr) | set); +} + +static inline void mmio_clrsetbits_32(uintptr_t addr, + uint32_t clear, + uint32_t set) +{ + mmio_write_32(addr, (mmio_read_32(addr) & ~clear) | set); +} + +#endif /* __MMIO_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/pmf/pmf.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/pmf/pmf.h new file mode 100644 index 0000000..5f953b5 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/pmf/pmf.h @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PMF_H__ +#define __PMF_H__ + +#include +#include + +/* + * Constants used for/by PMF services. + */ +#define PMF_ARM_TIF_IMPL_ID (0x41000000) +#define PMF_TID_SHIFT 0 +#define PMF_TID_MASK (0xFF << PMF_TID_SHIFT) +#define PMF_SVC_ID_SHIFT 10 +#define PMF_SVC_ID_MASK (0x3F << PMF_SVC_ID_SHIFT) +#define PMF_IMPL_ID_SHIFT 24 +#define PMF_IMPL_ID_MASK (0xFF << PMF_IMPL_ID_SHIFT) + +/* + * Flags passed to PMF_REGISTER_SERVICE + */ +#define PMF_STORE_ENABLE (1 << 0) +#define PMF_DUMP_ENABLE (1 << 1) + +/* + * Flags passed to PMF_GET_TIMESTAMP_XXX + * and PMF_CAPTURE_TIMESTAMP + */ +#define PMF_CACHE_MAINT (1 << 0) +#define PMF_NO_CACHE_MAINT 0 + +/* + * Defines for PMF SMC function ids. + */ +#define PMF_SMC_GET_TIMESTAMP_32 0x82000010 +#define PMF_SMC_GET_TIMESTAMP_64 0xC2000010 +#define PMF_NUM_SMC_CALLS 2 + +/* + * The macros below are used to identify + * PMF calls from the SMC function ID. + */ +#define PMF_FID_MASK 0xffe0u +#define PMF_FID_VALUE 0u +#define is_pmf_fid(_fid) (((_fid) & PMF_FID_MASK) == PMF_FID_VALUE) + +/* Following are the supported PMF service IDs */ +#define PMF_PSCI_STAT_SVC_ID 0 + +#if ENABLE_PMF +/* + * Convenience macros for capturing time-stamp. + */ +#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name) \ + void pmf_capture_timestamp_with_cache_maint_ ## _name( \ + unsigned int tid, \ + unsigned long long ts); \ + void pmf_capture_timestamp_ ## _name( \ + unsigned int tid, \ + unsigned long long ts); + +#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags) \ + do { \ + unsigned long long ts = read_cntpct_el0(); \ + if ((_flags) & PMF_CACHE_MAINT) \ + pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), ts);\ + else \ + pmf_capture_timestamp_ ## _name((_tid), ts); \ + } while (0) + +#define PMF_CAPTURE_AND_GET_TIMESTAMP(_name, _tid, _flags, _tsval) \ + do { \ + (_tsval) = read_cntpct_el0(); \ + CASSERT(sizeof(_tsval) == sizeof(unsigned long long), invalid_tsval_size);\ + if ((_flags) & PMF_CACHE_MAINT) \ + pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_tsval));\ + else \ + pmf_capture_timestamp_ ## _name((_tid), (_tsval));\ + } while (0) + +#define PMF_WRITE_TIMESTAMP(_name, _tid, _flags, _wrval) \ + do { \ + CASSERT(sizeof(_wrval) == sizeof(unsigned long long), invalid_wrval_size);\ + if ((_flags) & PMF_CACHE_MAINT) \ + pmf_capture_timestamp_with_cache_maint_ ## _name((_tid), (_wrval));\ + else \ + pmf_capture_timestamp_ ## _name((_tid), (_wrval));\ + } while (0) + +/* + * Convenience macros for retrieving time-stamp. + */ +#define PMF_DECLARE_GET_TIMESTAMP(_name) \ + unsigned long long pmf_get_timestamp_by_index_ ## _name(\ + unsigned int tid, \ + unsigned int cpuid, \ + unsigned int flags); \ + unsigned long long pmf_get_timestamp_by_mpidr_ ## _name(\ + unsigned int tid, \ + u_register_t mpidr, \ + unsigned int flags); + +#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval)\ + _tsval = pmf_get_timestamp_by_mpidr_ ## _name(_tid, _mpidr, _flags) + +#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval)\ + _tsval = pmf_get_timestamp_by_index_ ## _name(_tid, _cpuid, _flags) + +/* Convenience macros to register a PMF service.*/ +/* + * This macro is used to register a PMF Service. It allocates PMF memory + * and defines default service-specific PMF functions. + */ +#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) \ + PMF_ALLOCATE_TIMESTAMP_MEMORY(_name, _totalid) \ + PMF_DEFINE_CAPTURE_TIMESTAMP(_name, _flags) \ + PMF_DEFINE_GET_TIMESTAMP(_name) + +/* + * This macro is used to register a PMF service, including an + * SMC interface to that service. + */ +#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags)\ + PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) \ + PMF_DEFINE_SERVICE_DESC(_name, PMF_ARM_TIF_IMPL_ID, \ + _svcid, _totalid, NULL, \ + pmf_get_timestamp_by_mpidr_ ## _name) + +/* + * This macro is used to register a PMF service that has an SMC interface + * but provides its own service-specific PMF functions. + */ +#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid, \ + _init, _getts) \ + PMF_DEFINE_SERVICE_DESC(_name, _implid, _svcid, _totalid, \ + _init, _getts) + +#else + +#define PMF_REGISTER_SERVICE(_name, _svcid, _totalid, _flags) +#define PMF_REGISTER_SERVICE_SMC(_name, _svcid, _totalid, _flags) +#define PMF_REGISTER_SERVICE_SMC_OWN(_name, _implid, _svcid, _totalid, \ + _init, _getts) +#define PMF_DECLARE_CAPTURE_TIMESTAMP(_name) +#define PMF_DECLARE_GET_TIMESTAMP(_name) +#define PMF_CAPTURE_TIMESTAMP(_name, _tid, _flags) +#define PMF_GET_TIMESTAMP_BY_MPIDR(_name, _tid, _mpidr, _flags, _tsval) +#define PMF_GET_TIMESTAMP_BY_INDEX(_name, _tid, _cpuid, _flags, _tsval) + +#endif /* ENABLE_PMF */ + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +/* PMF common functions */ +int pmf_get_timestamp_smc(unsigned int tid, + u_register_t mpidr, + unsigned int flags, + unsigned long long *ts); +int pmf_setup(void); +uintptr_t pmf_smc_handler(unsigned int smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags); + +#endif /* __PMF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/pmf/pmf_asm_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/pmf/pmf_asm_macros.S new file mode 100644 index 0000000..be7338b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/pmf/pmf_asm_macros.S @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PMF_ASM_MACROS_S__ +#define __PMF_ASM_MACROS_S__ + +#define PMF_TS_SIZE 8 + + /* + * This macro calculates the address of the per-cpu timestamp + * for the given service name and local timestamp id. + * Clobbers: x0 - x9 + */ + .macro pmf_calc_timestamp_addr _name _tid + mov x9, x30 + bl plat_my_core_pos + mov x30, x9 + ldr x1, =__PERCPU_TIMESTAMP_SIZE__ + mov x2, #(\_tid * PMF_TS_SIZE) + madd x0, x0, x1, x2 + ldr x1, =pmf_ts_mem_\_name + add x0, x0, x1 + .endm + +#endif /* __PMF_ASM_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/pmf/pmf_helpers.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/pmf/pmf_helpers.h new file mode 100644 index 0000000..bb4242c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/pmf/pmf_helpers.h @@ -0,0 +1,168 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PMF_HELPERS_H__ +#define __PMF_HELPERS_H__ + +#include +#include +#include +#include +#include +#include + +/* + * Prototype for PMF service functions. + */ +typedef int (*pmf_svc_init_t)(void); +typedef unsigned long long (*pmf_svc_get_ts_t)(unsigned int tid, + u_register_t mpidr, + unsigned int flags); + +/* + * This is the definition of PMF service desc. + */ +typedef struct pmf_svc_desc { + /* Structure version information */ + param_header_t h; + + /* Name of the PMF service */ + const char *name; + + /* PMF service config: Implementer id, Service id and total id*/ + unsigned int svc_config; + + /* PMF service initialization handler */ + pmf_svc_init_t init; + + /* PMF service time-stamp retrieval handler */ + pmf_svc_get_ts_t get_ts; +} pmf_svc_desc_t; + +/* + * Convenience macro to allocate memory for a PMF service. + */ +#define PMF_ALLOCATE_TIMESTAMP_MEMORY(_name, _total_id) \ + unsigned long long pmf_ts_mem_ ## _name[_total_id] \ + __aligned(CACHE_WRITEBACK_GRANULE) \ + __section("pmf_timestamp_array") \ + __used; + +/* + * Convenience macro to validate tid index for the given TS array. + */ +#define PMF_VALIDATE_TID(_name, _tid) \ + assert((_tid & PMF_TID_MASK) < (ARRAY_SIZE(pmf_ts_mem_ ## _name))) + +/* + * Convenience macros for capturing time-stamp. + */ +#define PMF_DEFINE_CAPTURE_TIMESTAMP(_name, _flags) \ + void pmf_capture_timestamp_ ## _name( \ + unsigned int tid, \ + unsigned long long ts) \ + { \ + CASSERT(_flags, select_proper_config); \ + PMF_VALIDATE_TID(_name, tid); \ + uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \ + if ((_flags) & PMF_STORE_ENABLE) \ + __pmf_store_timestamp(base_addr, tid, ts); \ + if ((_flags) & PMF_DUMP_ENABLE) \ + __pmf_dump_timestamp(tid, ts); \ + } \ + void pmf_capture_timestamp_with_cache_maint_ ## _name( \ + unsigned int tid, \ + unsigned long long ts) \ + { \ + CASSERT(_flags, select_proper_config); \ + PMF_VALIDATE_TID(_name, tid); \ + uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \ + if ((_flags) & PMF_STORE_ENABLE) \ + __pmf_store_timestamp_with_cache_maint(base_addr, tid, ts);\ + if ((_flags) & PMF_DUMP_ENABLE) \ + __pmf_dump_timestamp(tid, ts); \ + } + +/* + * Convenience macros for retrieving time-stamp. + */ +#define PMF_DEFINE_GET_TIMESTAMP(_name) \ + unsigned long long pmf_get_timestamp_by_index_ ## _name( \ + unsigned int tid, unsigned int cpuid, unsigned int flags)\ + { \ + PMF_VALIDATE_TID(_name, tid); \ + uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \ + return __pmf_get_timestamp(base_addr, tid, cpuid, flags);\ + } \ + unsigned long long pmf_get_timestamp_by_mpidr_ ## _name( \ + unsigned int tid, u_register_t mpidr, unsigned int flags)\ + { \ + PMF_VALIDATE_TID(_name, tid); \ + uintptr_t base_addr = (uintptr_t) pmf_ts_mem_ ## _name; \ + return __pmf_get_timestamp(base_addr, tid, \ + plat_core_pos_by_mpidr(mpidr), flags); \ + } + +/* + * Convenience macro to register a PMF service. + * This is needed for services that require SMC handling. + */ +#define PMF_DEFINE_SERVICE_DESC(_name, _implid, _svcid, _totalid, \ + _init, _getts_by_mpidr) \ + static const pmf_svc_desc_t __pmf_desc_ ## _name \ + __section("pmf_svc_descs") __used = { \ + .h.type = PARAM_EP, \ + .h.version = VERSION_1, \ + .h.size = sizeof(pmf_svc_desc_t), \ + .h.attr = 0, \ + .name = #_name, \ + .svc_config = ((((_implid) << PMF_IMPL_ID_SHIFT) & \ + PMF_IMPL_ID_MASK) | \ + (((_svcid) << PMF_SVC_ID_SHIFT) & \ + PMF_SVC_ID_MASK) | \ + (((_totalid) << PMF_TID_SHIFT) & \ + PMF_TID_MASK)), \ + .init = _init, \ + .get_ts = _getts_by_mpidr \ + }; + +/* PMF internal functions */ +void __pmf_dump_timestamp(unsigned int tid, unsigned long long ts); +void __pmf_store_timestamp(uintptr_t base_addr, + unsigned int tid, + unsigned long long ts); +void __pmf_store_timestamp_with_cache_maint(uintptr_t base_addr, + unsigned int tid, + unsigned long long ts); +unsigned long long __pmf_get_timestamp(uintptr_t base_addr, + unsigned int tid, + unsigned int cpuid, + unsigned int flags); +#endif /* __PMF_HELPERS_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/psci/psci.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/psci/psci.h new file mode 100644 index 0000000..34de4c2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/psci/psci.h @@ -0,0 +1,419 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PSCI_H__ +#define __PSCI_H__ + +#include +#include +#include /* for PLAT_NUM_PWR_DOMAINS */ +#if ENABLE_PLAT_COMPAT +#include +#endif + +/******************************************************************************* + * Number of power domains whose state this PSCI implementation can track + ******************************************************************************/ +#ifdef PLAT_NUM_PWR_DOMAINS +#define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS +#else +#define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT) +#endif + +#define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ + PLATFORM_CORE_COUNT) + +/* This is the power level corresponding to a CPU */ +#define PSCI_CPU_PWR_LVL 0 + +/* + * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND + * uses the old power_state parameter format which has 2 bits to specify the + * power level, this constant is defined to be 3. + */ +#define PSCI_MAX_PWR_LVL 3 + +/******************************************************************************* + * Defines for runtime services function ids + ******************************************************************************/ +#define PSCI_VERSION 0x84000000 +#define PSCI_CPU_SUSPEND_AARCH32 0x84000001 +#define PSCI_CPU_SUSPEND_AARCH64 0xc4000001 +#define PSCI_CPU_OFF 0x84000002 +#define PSCI_CPU_ON_AARCH32 0x84000003 +#define PSCI_CPU_ON_AARCH64 0xc4000003 +#define PSCI_AFFINITY_INFO_AARCH32 0x84000004 +#define PSCI_AFFINITY_INFO_AARCH64 0xc4000004 +#define PSCI_MIG_AARCH32 0x84000005 +#define PSCI_MIG_AARCH64 0xc4000005 +#define PSCI_MIG_INFO_TYPE 0x84000006 +#define PSCI_MIG_INFO_UP_CPU_AARCH32 0x84000007 +#define PSCI_MIG_INFO_UP_CPU_AARCH64 0xc4000007 +#define PSCI_SYSTEM_OFF 0x84000008 +#define PSCI_SYSTEM_RESET 0x84000009 +#define PSCI_FEATURES 0x8400000A +#define PSCI_NODE_HW_STATE_AARCH32 0x8400000d +#define PSCI_NODE_HW_STATE_AARCH64 0xc400000d +#define PSCI_SYSTEM_SUSPEND_AARCH32 0x8400000E +#define PSCI_SYSTEM_SUSPEND_AARCH64 0xc400000E +#define PSCI_STAT_RESIDENCY_AARCH32 0x84000010 +#define PSCI_STAT_RESIDENCY_AARCH64 0xc4000010 +#define PSCI_STAT_COUNT_AARCH32 0x84000011 +#define PSCI_STAT_COUNT_AARCH64 0xc4000011 + +/* Macro to help build the psci capabilities bitfield */ +#define define_psci_cap(x) (1 << (x & 0x1f)) + +/* + * Number of PSCI calls (above) implemented + */ +#if ENABLE_PSCI_STAT +#define PSCI_NUM_CALLS 22 +#else +#define PSCI_NUM_CALLS 18 +#endif + +/* The macros below are used to identify PSCI calls from the SMC function ID */ +#define PSCI_FID_MASK 0xffe0u +#define PSCI_FID_VALUE 0u +#define is_psci_fid(_fid) \ + (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) + +/******************************************************************************* + * PSCI Migrate and friends + ******************************************************************************/ +#define PSCI_TOS_UP_MIG_CAP 0 +#define PSCI_TOS_NOT_UP_MIG_CAP 1 +#define PSCI_TOS_NOT_PRESENT_MP 2 + +/******************************************************************************* + * PSCI CPU_SUSPEND 'power_state' parameter specific defines + ******************************************************************************/ +#define PSTATE_ID_SHIFT 0 + +#if PSCI_EXTENDED_STATE_ID +#define PSTATE_VALID_MASK 0xB0000000 +#define PSTATE_TYPE_SHIFT 30 +#define PSTATE_ID_MASK 0xfffffff +#else +#define PSTATE_VALID_MASK 0xFCFE0000 +#define PSTATE_TYPE_SHIFT 16 +#define PSTATE_PWR_LVL_SHIFT 24 +#define PSTATE_ID_MASK 0xffff +#define PSTATE_PWR_LVL_MASK 0x3 + +#define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \ + PSTATE_PWR_LVL_MASK) +#define psci_make_powerstate(state_id, type, pwrlvl) \ + (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\ + (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\ + (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT) +#endif /* __PSCI_EXTENDED_STATE_ID__ */ + +#define PSTATE_TYPE_STANDBY 0x0 +#define PSTATE_TYPE_POWERDOWN 0x1 +#define PSTATE_TYPE_MASK 0x1 + +#define psci_get_pstate_id(pstate) (((pstate) >> PSTATE_ID_SHIFT) & \ + PSTATE_ID_MASK) +#define psci_get_pstate_type(pstate) (((pstate) >> PSTATE_TYPE_SHIFT) & \ + PSTATE_TYPE_MASK) +#define psci_check_power_state(pstate) ((pstate) & PSTATE_VALID_MASK) + +/******************************************************************************* + * PSCI CPU_FEATURES feature flag specific defines + ******************************************************************************/ +/* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */ +#define FF_PSTATE_SHIFT 1 +#define FF_PSTATE_ORIG 0 +#define FF_PSTATE_EXTENDED 1 +#if PSCI_EXTENDED_STATE_ID +#define FF_PSTATE FF_PSTATE_EXTENDED +#else +#define FF_PSTATE FF_PSTATE_ORIG +#endif + +/* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */ +#define FF_MODE_SUPPORT_SHIFT 0 +#define FF_SUPPORTS_OS_INIT_MODE 1 + +/******************************************************************************* + * PSCI version + ******************************************************************************/ +#define PSCI_MAJOR_VER (1 << 16) +#define PSCI_MINOR_VER 0x0 + +/******************************************************************************* + * PSCI error codes + ******************************************************************************/ +#define PSCI_E_SUCCESS 0 +#define PSCI_E_NOT_SUPPORTED -1 +#define PSCI_E_INVALID_PARAMS -2 +#define PSCI_E_DENIED -3 +#define PSCI_E_ALREADY_ON -4 +#define PSCI_E_ON_PENDING -5 +#define PSCI_E_INTERN_FAIL -6 +#define PSCI_E_NOT_PRESENT -7 +#define PSCI_E_DISABLED -8 +#define PSCI_E_INVALID_ADDRESS -9 + +#define PSCI_INVALID_MPIDR ~((u_register_t)0) + +#ifndef __ASSEMBLY__ + +#include +#include + +/* + * These are the states reported by the PSCI_AFFINITY_INFO API for the specified + * CPU. The definitions of these states can be found in Section 5.7.1 in the + * PSCI specification (ARM DEN 0022C). + */ +typedef enum { + AFF_STATE_ON = 0, + AFF_STATE_OFF = 1, + AFF_STATE_ON_PENDING = 2 +} aff_info_state_t; + +/* + * These are the power states reported by PSCI_NODE_HW_STATE API for the + * specified CPU. The definitions of these states can be found in Section 5.15.3 + * of PSCI specification (ARM DEN 0022C). + */ +typedef enum { + HW_ON = 0, + HW_OFF = 1, + HW_STANDBY = 2 +} node_hw_state_t; + +/* + * Macro to represent invalid affinity level within PSCI. + */ +#define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + 1) + +/* + * Type for representing the local power state at a particular level. + */ +typedef uint8_t plat_local_state_t; + +/* The local state macro used to represent RUN state. */ +#define PSCI_LOCAL_STATE_RUN 0 + +/* + * Macro to test whether the plat_local_state is RUN state + */ +#define is_local_state_run(plat_local_state) \ + ((plat_local_state) == PSCI_LOCAL_STATE_RUN) + +/* + * Macro to test whether the plat_local_state is RETENTION state + */ +#define is_local_state_retn(plat_local_state) \ + (((plat_local_state) > PSCI_LOCAL_STATE_RUN) && \ + ((plat_local_state) <= PLAT_MAX_RET_STATE)) + +/* + * Macro to test whether the plat_local_state is OFF state + */ +#define is_local_state_off(plat_local_state) \ + (((plat_local_state) > PLAT_MAX_RET_STATE) && \ + ((plat_local_state) <= PLAT_MAX_OFF_STATE)) + +/***************************************************************************** + * This data structure defines the representation of the power state parameter + * for its exchange between the generic PSCI code and the platform port. For + * example, it is used by the platform port to specify the requested power + * states during a power management operation. It is used by the generic code to + * inform the platform about the target power states that each level should + * enter. + ****************************************************************************/ +typedef struct psci_power_state { + /* + * The pwr_domain_state[] stores the local power state at each level + * for the CPU. + */ + plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + 1]; +} psci_power_state_t; + +/******************************************************************************* + * Structure used to store per-cpu information relevant to the PSCI service. + * It is populated in the per-cpu data array. In return we get a guarantee that + * this information will not reside on a cache line shared with another cpu. + ******************************************************************************/ +typedef struct psci_cpu_data { + /* State as seen by PSCI Affinity Info API */ + aff_info_state_t aff_info_state; + + /* + * Highest power level which takes part in a power management + * operation. + */ + unsigned char target_pwrlvl; + + /* The local power state of this CPU */ + plat_local_state_t local_state; +} psci_cpu_data_t; + +/******************************************************************************* + * Structure populated by platform specific code to export routines which + * perform common low level power management functions + ******************************************************************************/ +typedef struct plat_psci_ops { + void (*cpu_standby)(plat_local_state_t cpu_state); + int (*pwr_domain_on)(u_register_t mpidr); + void (*pwr_domain_off)(const psci_power_state_t *target_state); + void (*pwr_domain_suspend)(const psci_power_state_t *target_state); + void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); + void (*pwr_domain_suspend_finish)( + const psci_power_state_t *target_state); + void (*pwr_domain_pwr_down_wfi)( + const psci_power_state_t *target_state) __dead2; + void (*system_off)(void) __dead2; + void (*system_reset)(void) __dead2; + int (*validate_power_state)(unsigned int power_state, + psci_power_state_t *req_state); + int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint); + void (*get_sys_suspend_power_state)( + psci_power_state_t *req_state); + int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state, + int pwrlvl); + int (*translate_power_state_by_mpidr)(u_register_t mpidr, + unsigned int power_state, + psci_power_state_t *output_state); + int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level); +} plat_psci_ops_t; + +/******************************************************************************* + * Optional structure populated by the Secure Payload Dispatcher to be given a + * chance to perform any bookkeeping before PSCI executes a power management + * operation. It also allows PSCI to determine certain properties of the SP e.g. + * migrate capability etc. + ******************************************************************************/ +typedef struct spd_pm_ops { + void (*svc_on)(u_register_t target_cpu); + int32_t (*svc_off)(u_register_t __unused); + void (*svc_suspend)(u_register_t max_off_pwrlvl); + void (*svc_on_finish)(u_register_t __unused); + void (*svc_suspend_finish)(u_register_t max_off_pwrlvl); + int32_t (*svc_migrate)(u_register_t from_cpu, u_register_t to_cpu); + int32_t (*svc_migrate_info)(u_register_t *resident_cpu); + void (*svc_system_off)(void); + void (*svc_system_reset)(void); +} spd_pm_ops_t; + +/******************************************************************************* + * Function & Data prototypes + ******************************************************************************/ +unsigned int psci_version(void); +int psci_cpu_on(u_register_t target_cpu, + uintptr_t entrypoint, + u_register_t context_id); +int psci_cpu_suspend(unsigned int power_state, + uintptr_t entrypoint, + u_register_t context_id); +int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id); +int psci_cpu_off(void); +int psci_affinity_info(u_register_t target_affinity, + unsigned int lowest_affinity_level); +int psci_migrate(u_register_t target_cpu); +int psci_migrate_info_type(void); +long psci_migrate_info_up_cpu(void); +int psci_node_hw_state(u_register_t target_cpu, + unsigned int power_level); +int psci_features(unsigned int psci_fid); +void __dead2 psci_power_down_wfi(void); +void psci_arch_setup(void); + +/* + * The below API is deprecated. This is now replaced by bl31_warmboot_entry in + * AArch64. + */ +void psci_entrypoint(void) __deprecated; + +/* + * Function prototype for the warmboot entrypoint function which will be + * programmed in the mailbox by the platform. + */ +typedef void (*mailbox_entrypoint_t)(void); + +/****************************************************************************** + * Structure to pass PSCI Library arguments. + *****************************************************************************/ +typedef struct psci_lib_args { + /* The version information of PSCI Library Interface */ + param_header_t h; + /* The warm boot entrypoint function */ + mailbox_entrypoint_t mailbox_ep; +} psci_lib_args_t; + +/* Helper macro to set the psci_lib_args_t structure at runtime */ +#define SET_PSCI_LIB_ARGS_V1(_p, _entry) do { \ + SET_PARAM_HEAD(_p, PARAM_PSCI_LIB_ARGS, VERSION_1, 0); \ + (_p)->mailbox_ep = (_entry); \ + } while (0) + +/* Helper macro to define the psci_lib_args_t statically */ +#define DEFINE_STATIC_PSCI_LIB_ARGS_V1(_name, _entry) \ + static const psci_lib_args_t (_name) = { \ + .h.type = (uint8_t)PARAM_PSCI_LIB_ARGS, \ + .h.version = (uint8_t)VERSION_1, \ + .h.size = (uint16_t)sizeof(_name), \ + .h.attr = 0, \ + .mailbox_ep = (_entry) \ + } + +/* Helper macro to verify the pointer to psci_lib_args_t structure */ +#define VERIFY_PSCI_LIB_ARGS_V1(_p) ((_p) \ + && ((_p)->h.type == PARAM_PSCI_LIB_ARGS) \ + && ((_p)->h.version == VERSION_1) \ + && ((_p)->h.size == sizeof(*(_p))) \ + && ((_p)->h.attr == 0) \ + && ((_p)->mailbox_ep)) + +/****************************************************************************** + * PSCI Library Interfaces + *****************************************************************************/ +u_register_t psci_smc_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags); +int psci_setup(const psci_lib_args_t *lib_args); +void psci_warmboot_entrypoint(void); +void psci_register_spd_pm_hook(const spd_pm_ops_t *pm); +void psci_prepare_next_non_secure_ctx( + entry_point_info_t *next_image_info); + +#endif /*__ASSEMBLY__*/ + +#endif /* __PSCI_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/psci/psci_compat.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/psci/psci_compat.h new file mode 100644 index 0000000..3554667 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/psci/psci_compat.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PSCI_COMPAT_H__ +#define __PSCI_COMPAT_H__ + +#include +#include + +#ifndef __ASSEMBLY__ +/* + * The below declarations are to enable compatibility for the platform ports + * using the old platform interface and psci helpers. + */ +#define PLAT_MAX_PWR_LVL PLATFORM_MAX_AFFLVL +#define PLAT_NUM_PWR_DOMAINS PLATFORM_NUM_AFFS + +/******************************************************************************* + * PSCI affinity related constants. An affinity instance could + * be present or absent physically to cater for asymmetric topologies. + ******************************************************************************/ +#define PSCI_AFF_ABSENT 0x0 +#define PSCI_AFF_PRESENT 0x1 + +#define PSCI_STATE_ON 0x0 +#define PSCI_STATE_OFF 0x1 +#define PSCI_STATE_ON_PENDING 0x2 +#define PSCI_STATE_SUSPEND 0x3 + +/* + * Using the compatibility platform interfaces means that the local states + * used in psci_power_state_t need to only convey whether its power down + * or standby state. The onus is on the platform port to do the right thing + * including the state coordination in case multiple power down states are + * involved. Hence if we assume 3 generic states viz, run, standby and + * power down, we can assign 1 and 2 to standby and power down respectively. + */ +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE 2 + +/* + * Macro to represent invalid affinity level within PSCI. + */ +#define PSCI_INVALID_DATA -1 + +#define psci_get_pstate_afflvl(pstate) psci_get_pstate_pwrlvl(pstate) + +/* + * This array stores the 'power_state' requests of each CPU during + * CPU_SUSPEND and SYSTEM_SUSPEND which will be populated by the + * compatibility layer when appropriate platform hooks are invoked. + */ +extern unsigned int psci_power_state_compat[PLATFORM_CORE_COUNT]; + +/******************************************************************************* + * Structure populated by platform specific code to export routines which + * perform common low level pm functions + ******************************************************************************/ +typedef struct plat_pm_ops { + void (*affinst_standby)(unsigned int power_state); + int (*affinst_on)(unsigned long mpidr, + unsigned long sec_entrypoint, + unsigned int afflvl, + unsigned int state); + void (*affinst_off)(unsigned int afflvl, unsigned int state); + void (*affinst_suspend)(unsigned long sec_entrypoint, + unsigned int afflvl, + unsigned int state); + void (*affinst_on_finish)(unsigned int afflvl, unsigned int state); + void (*affinst_suspend_finish)(unsigned int afflvl, + unsigned int state); + void (*system_off)(void) __dead2; + void (*system_reset)(void) __dead2; + int (*validate_power_state)(unsigned int power_state); + int (*validate_ns_entrypoint)(unsigned long ns_entrypoint); + unsigned int (*get_sys_suspend_power_state)(void); +} plat_pm_ops_t; + +/******************************************************************************* + * Function & Data prototypes to enable compatibility for older platform ports + ******************************************************************************/ +int psci_get_suspend_stateid_by_mpidr(unsigned long); +int psci_get_suspend_stateid(void); +int psci_get_suspend_powerstate(void); +unsigned int psci_get_max_phys_off_afflvl(void); +int psci_get_suspend_afflvl(void); + +#endif /* ____ASSEMBLY__ */ +#endif /* __PSCI_COMPAT_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/semihosting.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/semihosting.h new file mode 100644 index 0000000..b4eecc5 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/semihosting.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SEMIHOSTING_H__ +#define __SEMIHOSTING_H__ + +#include +#include /* For ssize_t */ + + +#define SEMIHOSTING_SYS_OPEN 0x01 +#define SEMIHOSTING_SYS_CLOSE 0x02 +#define SEMIHOSTING_SYS_WRITE0 0x04 +#define SEMIHOSTING_SYS_WRITEC 0x03 +#define SEMIHOSTING_SYS_WRITE 0x05 +#define SEMIHOSTING_SYS_READ 0x06 +#define SEMIHOSTING_SYS_READC 0x07 +#define SEMIHOSTING_SYS_SEEK 0x0A +#define SEMIHOSTING_SYS_FLEN 0x0C +#define SEMIHOSTING_SYS_REMOVE 0x0E +#define SEMIHOSTING_SYS_SYSTEM 0x12 +#define SEMIHOSTING_SYS_ERRNO 0x13 + +#define FOPEN_MODE_R 0x0 +#define FOPEN_MODE_RB 0x1 +#define FOPEN_MODE_RPLUS 0x2 +#define FOPEN_MODE_RPLUSB 0x3 +#define FOPEN_MODE_W 0x4 +#define FOPEN_MODE_WB 0x5 +#define FOPEN_MODE_WPLUS 0x6 +#define FOPEN_MODE_WPLUSB 0x7 +#define FOPEN_MODE_A 0x8 +#define FOPEN_MODE_AB 0x9 +#define FOPEN_MODE_APLUS 0xa +#define FOPEN_MODE_APLUSB 0xb + +long semihosting_connection_supported(void); +long semihosting_file_open(const char *file_name, size_t mode); +long semihosting_file_seek(long file_handle, ssize_t offset); +long semihosting_file_read(long file_handle, size_t *length, uintptr_t buffer); +long semihosting_file_write(long file_handle, + size_t *length, + const uintptr_t buffer); +long semihosting_file_close(long file_handle); +long semihosting_file_length(long file_handle); +long semihosting_system(char *command_line); +long semihosting_get_flen(const char *file_name); +long semihosting_download_file(const char *file_name, + size_t buf_size, + uintptr_t buf); +void semihosting_write_char(char character); +void semihosting_write_string(char *string); +char semihosting_read_char(void); + +#endif /* __SEMIHOSTING_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/smcc.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/smcc.h new file mode 100644 index 0000000..c415ba1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/smcc.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SMCC_H__ +#define __SMCC_H__ + +/******************************************************************************* + * Bit definitions inside the function id as per the SMC calling convention + ******************************************************************************/ +#define FUNCID_TYPE_SHIFT 31 +#define FUNCID_CC_SHIFT 30 +#define FUNCID_OEN_SHIFT 24 +#define FUNCID_NUM_SHIFT 0 + +#define FUNCID_TYPE_MASK 0x1 +#define FUNCID_CC_MASK 0x1 +#define FUNCID_OEN_MASK 0x3f +#define FUNCID_NUM_MASK 0xffff + +#define FUNCID_TYPE_WIDTH 1 +#define FUNCID_CC_WIDTH 1 +#define FUNCID_OEN_WIDTH 6 +#define FUNCID_NUM_WIDTH 16 + +#define GET_SMC_CC(id) ((id >> FUNCID_CC_SHIFT) & \ + FUNCID_CC_MASK) +#define GET_SMC_TYPE(id) ((id >> FUNCID_TYPE_SHIFT) & \ + FUNCID_TYPE_MASK) + +#define SMC_64 1 +#define SMC_32 0 +#define SMC_UNK 0xffffffff +#define SMC_TYPE_FAST 1 +#define SMC_TYPE_STD 0 +#define SMC_PREEMPTED 0xfffffffe +/******************************************************************************* + * Owning entity number definitions inside the function id as per the SMC + * calling convention + ******************************************************************************/ +#define OEN_ARM_START 0 +#define OEN_ARM_END 0 +#define OEN_CPU_START 1 +#define OEN_CPU_END 1 +#define OEN_SIP_START 2 +#define OEN_SIP_END 2 +#define OEN_OEM_START 3 +#define OEN_OEM_END 3 +#define OEN_STD_START 4 /* Standard Calls */ +#define OEN_STD_END 4 +#define OEN_TAP_START 48 /* Trusted Applications */ +#define OEN_TAP_END 49 +#define OEN_TOS_START 50 /* Trusted OS */ +#define OEN_TOS_END 63 +#define OEN_LIMIT 64 + +#ifndef __ASSEMBLY__ + +#include +#include + +/* Various flags passed to SMC handlers */ +#define SMC_FROM_SECURE (0 << 0) +#define SMC_FROM_NON_SECURE (1 << 0) + +#define is_caller_non_secure(_f) (!!(_f & SMC_FROM_NON_SECURE)) +#define is_caller_secure(_f) (!(is_caller_non_secure(_f))) + +/* The macro below is used to identify a Standard Service SMC call */ +#define is_std_svc_call(_fid) ((((_fid) >> FUNCID_OEN_SHIFT) & \ + FUNCID_OEN_MASK) == OEN_STD_START) + +/* The macro below is used to identify a valid Fast SMC call */ +#define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & 0xff)) && \ + (GET_SMC_TYPE(_fid) == SMC_TYPE_FAST)) + +/* + * Macro to define UUID for services. Apart from defining and initializing a + * uuid_t structure, this macro verifies that the first word of the defined UUID + * does not equal SMC_UNK. This is to ensure that the caller won't mistake the + * returned UUID in x0 for an invalid SMC error return + */ +#define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \ + _n0, _n1, _n2, _n3, _n4, _n5) \ + CASSERT(_tl != SMC_UNK, invalid_svc_uuid);\ + static const uuid_t _name = { \ + _tl, _tm, _th, _cl, _ch, \ + { _n0, _n1, _n2, _n3, _n4, _n5 } \ + } + +#endif /*__ASSEMBLY__*/ +#endif /* __SMCC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/spinlock.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/spinlock.h new file mode 100644 index 0000000..cb0bc3e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/spinlock.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SPINLOCK_H__ +#define __SPINLOCK_H__ + +typedef struct spinlock { + volatile unsigned int lock; +} spinlock_t; + +void spin_lock(spinlock_t *lock); +void spin_unlock(spinlock_t *lock); + +#endif /* __SPINLOCK_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/assert.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/assert.h new file mode 100644 index 0000000..5621f8c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/assert.h @@ -0,0 +1,63 @@ +/*- + * Copyright (c) 1992, 1993 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)assert.h 8.2 (Berkeley) 1/21/94 + * $FreeBSD$ + */ + +#include + +/* + * Unlike other ANSI header files, may usefully be included + * multiple times, with and without NDEBUG defined. + */ + +#undef assert +#undef _assert + +#ifdef NDEBUG +#define assert(e) ((void)0) +#define _assert(e) ((void)0) +#else +#define _assert(e) assert(e) + +#define assert(e) ((e) ? (void)0 : __assert(__func__, __FILE__, \ + __LINE__, #e)) +#endif /* NDEBUG */ + +#ifndef _ASSERT_H_ +#define _ASSERT_H_ +__BEGIN_DECLS +void __assert(const char *, const char *, int, const char *) __dead2; +__END_DECLS +#endif /* !_ASSERT_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/inttypes.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/inttypes.h new file mode 100644 index 0000000..269f3e7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/inttypes.h @@ -0,0 +1,52 @@ +/*- + * Copyright (c) 2001 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _INTTYPES_H_ +#define _INTTYPES_H_ + +#include +#include + +typedef struct { + intmax_t quot; /* Quotient. */ + intmax_t rem; /* Remainder. */ +} imaxdiv_t; + +__BEGIN_DECLS +#ifdef _XLOCALE_H_ +#include +#endif +intmax_t imaxabs(intmax_t) __pure2; +imaxdiv_t imaxdiv(intmax_t, intmax_t) __pure2; + +intmax_t strtoimax(const char *__restrict, char **__restrict, int); +uintmax_t strtoumax(const char *__restrict, char **__restrict, int); + +__END_DECLS + +#endif /* !_INTTYPES_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/machine/_inttypes.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/machine/_inttypes.h new file mode 100644 index 0000000..8dd07d6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/machine/_inttypes.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _MACHINE_INTTYPES_H_ +#define _MACHINE_INTTYPES_H_ + +/* + * Trusted Firmware does not depend on any definitions in this file. Content + * will be added as needed. + */ + +#endif /* !_MACHINE_INTTYPES_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/machine/_limits.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/machine/_limits.h new file mode 100644 index 0000000..49a768b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/machine/_limits.h @@ -0,0 +1,85 @@ +/*- + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)limits.h 8.3 (Berkeley) 1/4/94 + * $FreeBSD$ + */ + +#ifndef _MACHINE__LIMITS_H_ +#define _MACHINE__LIMITS_H_ + +/* + * According to ANSI (section 2.2.4.2), the values below must be usable by + * #if preprocessing directives. Additionally, the expression must have the + * same type as would an expression that is an object of the corresponding + * type converted according to the integral promotions. The subtraction for + * INT_MIN, etc., is so the value is not unsigned; e.g., 0x80000000 is an + * unsigned int for 32-bit two's complement ANSI compilers (section 3.1.3.2). + */ + +#define __CHAR_BIT 8 /* number of bits in a char */ + +#define __SCHAR_MAX 0x7f /* max value for a signed char */ +#define __SCHAR_MIN (-0x7f-1) /* min value for a signed char */ + +#define __UCHAR_MAX 0xff /* max value for an unsigned char */ + +#define __USHRT_MAX 0xffff /* max value for an unsigned short */ +#define __SHRT_MAX 0x7fff /* max value for a short */ +#define __SHRT_MIN (-0x7fff-1) /* min value for a short */ + +#define __UINT_MAX 0xffffffff /* max value for an unsigned int */ +#define __INT_MAX 0x7fffffff /* max value for an int */ +#define __INT_MIN (-0x7fffffff-1) /* min value for an int */ + +#define __ULONG_MAX 0xffffffffffffffff /* max for an unsigned long */ +#define __LONG_MAX 0x7fffffffffffffff /* max for a long */ +#define __LONG_MIN (-0x7fffffffffffffff-1) /* min for a long */ + +/* Long longs have the same size but not the same type as longs. */ + /* max for an unsigned long long */ +#define __ULLONG_MAX 0xffffffffffffffffULL +#define __LLONG_MAX 0x7fffffffffffffffLL /* max for a long long */ +#define __LLONG_MIN (-0x7fffffffffffffffLL-1) /* min for a long long */ + +#define __SSIZE_MAX __LONG_MAX /* max value for a ssize_t */ + +#define __SIZE_T_MAX __ULONG_MAX /* max value for a size_t */ + +#define __OFF_MAX __LONG_MAX /* max value for an off_t */ +#define __OFF_MIN __LONG_MIN /* min value for an off_t */ + +/* Quads and longs are the same size. Ensure they stay in sync. */ +#define __UQUAD_MAX (__ULONG_MAX) /* max value for a uquad_t */ +#define __QUAD_MAX (__LONG_MAX) /* max value for a quad_t */ +#define __QUAD_MIN (__LONG_MIN) /* min value for a quad_t */ + +#define __LONG_BIT 64 +#define __WORD_BIT 32 + +/* Minimum signal stack size. */ +#define __MINSIGSTKSZ (1024 * 4) + +#endif /* !_MACHINE__LIMITS_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/machine/_stdint.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/machine/_stdint.h new file mode 100644 index 0000000..9a4f35f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/machine/_stdint.h @@ -0,0 +1,169 @@ +/*- + * Copyright (c) 2001, 2002 Mike Barcroft + * Copyright (c) 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Klaus Klein. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2016, ARM Limited and Contributors. + * All rights reserved. + */ + +#ifndef _MACHINE__STDINT_H_ +#define _MACHINE__STDINT_H_ + +#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) + +#define INT8_C(c) (c) +#define INT16_C(c) (c) +#define INT32_C(c) (c) +#define INT64_C(c) (c ## LL) + +#define UINT8_C(c) (c) +#define UINT16_C(c) (c) +#define UINT32_C(c) (c ## U) +#define UINT64_C(c) (c ## ULL) + +#define INTMAX_C(c) INT64_C(c) +#define UINTMAX_C(c) UINT64_C(c) + +#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */ + +#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) + +/* + * ISO/IEC 9899:1999 + * 7.18.2.1 Limits of exact-width integer types + */ +/* Minimum values of exact-width signed integer types. */ +#define INT8_MIN (-0x7f-1) +#define INT16_MIN (-0x7fff-1) +#define INT32_MIN (-0x7fffffff-1) +#define INT64_MIN (-0x7fffffffffffffffLL-1) + +/* Maximum values of exact-width signed integer types. */ +#define INT8_MAX 0x7f +#define INT16_MAX 0x7fff +#define INT32_MAX 0x7fffffff +#define INT64_MAX 0x7fffffffffffffffLL + +/* Maximum values of exact-width unsigned integer types. */ +#define UINT8_MAX 0xff +#define UINT16_MAX 0xffff +#define UINT32_MAX 0xffffffffU +#define UINT64_MAX 0xffffffffffffffffULL + +/* + * ISO/IEC 9899:1999 + * 7.18.2.2 Limits of minimum-width integer types + */ +/* Minimum values of minimum-width signed integer types. */ +#define INT_LEAST8_MIN INT8_MIN +#define INT_LEAST16_MIN INT16_MIN +#define INT_LEAST32_MIN INT32_MIN +#define INT_LEAST64_MIN INT64_MIN + +/* Maximum values of minimum-width signed integer types. */ +#define INT_LEAST8_MAX INT8_MAX +#define INT_LEAST16_MAX INT16_MAX +#define INT_LEAST32_MAX INT32_MAX +#define INT_LEAST64_MAX INT64_MAX + +/* Maximum values of minimum-width unsigned integer types. */ +#define UINT_LEAST8_MAX UINT8_MAX +#define UINT_LEAST16_MAX UINT16_MAX +#define UINT_LEAST32_MAX UINT32_MAX +#define UINT_LEAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.3 Limits of fastest minimum-width integer types + */ +/* Minimum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MIN INT32_MIN +#define INT_FAST16_MIN INT32_MIN +#define INT_FAST32_MIN INT32_MIN +#define INT_FAST64_MIN INT64_MIN + +/* Maximum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MAX INT32_MAX +#define INT_FAST16_MAX INT32_MAX +#define INT_FAST32_MAX INT32_MAX +#define INT_FAST64_MAX INT64_MAX + +/* Maximum values of fastest minimum-width unsigned integer types. */ +#define UINT_FAST8_MAX UINT32_MAX +#define UINT_FAST16_MAX UINT32_MAX +#define UINT_FAST32_MAX UINT32_MAX +#define UINT_FAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.4 Limits of integer types capable of holding object pointers + */ +#define INTPTR_MIN INT64_MIN +#define INTPTR_MAX INT64_MAX +#define UINTPTR_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.5 Limits of greatest-width integer types + */ +#define INTMAX_MIN INT64_MIN +#define INTMAX_MAX INT64_MAX +#define UINTMAX_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.3 Limits of other integer types + */ +/* Limits of ptrdiff_t. */ +#define PTRDIFF_MIN INT64_MIN +#define PTRDIFF_MAX INT64_MAX + +/* Limits of sig_atomic_t. */ +#define SIG_ATOMIC_MIN INT32_MIN +#define SIG_ATOMIC_MAX INT32_MAX + +/* Limit of size_t. */ +#define SIZE_MAX UINT64_MAX + +#ifndef WCHAR_MIN /* Also possibly defined in */ +/* Limits of wchar_t. */ +#define WCHAR_MIN INT32_MIN +#define WCHAR_MAX INT32_MAX +#endif + +/* Limits of wint_t. */ +#define WINT_MIN INT32_MIN +#define WINT_MAX INT32_MAX + +#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ + +#endif /* !_MACHINE__STDINT_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/machine/_types.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/machine/_types.h new file mode 100644 index 0000000..fb1083b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/machine/_types.h @@ -0,0 +1,140 @@ +/*- + * Copyright (c) 2002 Mike Barcroft + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * From: @(#)ansi.h 8.2 (Berkeley) 1/4/94 + * From: @(#)types.h 8.3 (Berkeley) 1/5/94 + * $FreeBSD$ + */ +/* + * Portions copyright (c) 2016, ARM Limited and Contributors. + * All rights reserved. + */ + +#ifndef _MACHINE__TYPES_H_ +#define _MACHINE__TYPES_H_ + +#ifndef _SYS_CDEFS_H_ +#error this file needs sys/cdefs.h as a prerequisite +#endif + +/* + * Basic types upon which most other types are built. + */ +typedef __signed char __int8_t; +typedef unsigned char __uint8_t; +typedef short __int16_t; +typedef unsigned short __uint16_t; +typedef int __int32_t; +typedef unsigned int __uint32_t; + + +/* + * Standard type definitions which are different in AArch64 and AArch32 + */ +#ifdef AARCH32 +typedef long long __int64_t; +typedef unsigned long long __uint64_t; +typedef __int32_t __critical_t; +typedef __int32_t __intfptr_t; +typedef __int32_t __intptr_t; +typedef __int32_t __ptrdiff_t; /* ptr1 - ptr2 */ +typedef __int32_t __register_t; +typedef __int32_t __segsz_t; /* segment size (in pages) */ +typedef __uint32_t __size_t; /* sizeof() */ +typedef __int32_t __ssize_t; /* byte count or error */ +typedef __uint32_t __uintfptr_t; +typedef __uint32_t __uintptr_t; +typedef __uint32_t __u_register_t; +typedef __uint32_t __vm_offset_t; +typedef __uint32_t __vm_paddr_t; +typedef __uint32_t __vm_size_t; +#elif defined AARCH64 +typedef long __int64_t; +typedef unsigned long __uint64_t; +typedef __int64_t __critical_t; +typedef __int64_t __intfptr_t; +typedef __int64_t __intptr_t; +typedef __int64_t __ptrdiff_t; /* ptr1 - ptr2 */ +typedef __int64_t __register_t; +typedef __int64_t __segsz_t; /* segment size (in pages) */ +typedef __uint64_t __size_t; /* sizeof() */ +typedef __int64_t __ssize_t; /* byte count or error */ +typedef __uint64_t __uintfptr_t; +typedef __uint64_t __uintptr_t; +typedef __uint64_t __u_register_t; +typedef __uint64_t __vm_offset_t; +typedef __uint64_t __vm_paddr_t; +typedef __uint64_t __vm_size_t; +#else +#error "Only AArch32 or AArch64 supported" +#endif /* AARCH32 */ + +/* + * Standard type definitions. + */ +typedef __int32_t __clock_t; /* clock()... */ +typedef double __double_t; +typedef float __float_t; +typedef __int64_t __intmax_t; +typedef __int32_t __int_fast8_t; +typedef __int32_t __int_fast16_t; +typedef __int32_t __int_fast32_t; +typedef __int64_t __int_fast64_t; +typedef __int8_t __int_least8_t; +typedef __int16_t __int_least16_t; +typedef __int32_t __int_least32_t; +typedef __int64_t __int_least64_t; +typedef __int64_t __time_t; /* time()... */ +typedef __uint64_t __uintmax_t; +typedef __uint32_t __uint_fast8_t; +typedef __uint32_t __uint_fast16_t; +typedef __uint32_t __uint_fast32_t; +typedef __uint64_t __uint_fast64_t; +typedef __uint8_t __uint_least8_t; +typedef __uint16_t __uint_least16_t; +typedef __uint32_t __uint_least32_t; +typedef __uint64_t __uint_least64_t; +typedef __int64_t __vm_ooffset_t; +typedef __uint64_t __vm_pindex_t; + +/* + * Unusual type definitions. + */ +#ifdef __GNUCLIKE_BUILTIN_VARARGS +typedef __builtin_va_list __va_list; /* internally known to gcc */ +#else +typedef char * __va_list; +#endif /* __GNUCLIKE_BUILTIN_VARARGS */ +#if defined(__GNUCLIKE_BUILTIN_VAALIST) && !defined(__GNUC_VA_LIST) \ + && !defined(__NO_GNUC_VA_LIST) +#define __GNUC_VA_LIST +typedef __va_list __gnuc_va_list; /* compatibility w/GNU headers*/ +#endif + +#endif /* !_MACHINE__TYPES_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/stddef.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/stddef.h new file mode 100644 index 0000000..ea88214 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/stddef.h @@ -0,0 +1,64 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stddef.h 8.1 (Berkeley) 6/2/93 + * + * $FreeBSD$ + */ + +#ifndef _STDDEF_H_ +#define _STDDEF_H_ + +#include +#include +#include + +typedef __ptrdiff_t ptrdiff_t; + +#if __BSD_VISIBLE +#ifndef _RUNE_T_DECLARED +typedef __rune_t rune_t; +#define _RUNE_T_DECLARED +#endif +#endif + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#ifndef __cplusplus +#ifndef _WCHAR_T_DECLARED +typedef __wchar_t wchar_t; +#define _WCHAR_T_DECLARED +#endif +#endif + +#define offsetof(type, member) __offsetof(type, member) + +#endif /* _STDDEF_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/stdio.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/stdio.h new file mode 100644 index 0000000..57e5c7f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/stdio.h @@ -0,0 +1,78 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stdio.h 8.5 (Berkeley) 4/29/95 + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2013-2014, ARM Limited and Contributors. + * All rights reserved. + */ + + +#ifndef _STDIO_H_ +#define _STDIO_H_ + +#include +#include +#include + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#ifndef _SSIZE_T_DECLARED +#define _SSIZE_T_DECLARED +typedef __ssize_t ssize_t; +#endif + +#define EOF (-1) + +int printf(const char * __restrict, ...) __printflike(1, 2); +int putchar(int); +int puts(const char *); +int sprintf(char * __restrict, const char * __restrict, ...) + __printflike(2, 3); +int vsprintf(char * __restrict, const char * __restrict, + __va_list) __printflike(2, 0); + +int sscanf(const char *__restrict, char const *__restrict, ...); + +#if __ISO_C_VISIBLE >= 1999 +int snprintf(char * __restrict, size_t, const char * __restrict, + ...) __printflike(3, 4); +int vsnprintf(char * __restrict, size_t, const char * __restrict, + __va_list) __printflike(3, 0); +#endif + +#endif /* !_STDIO_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/stdlib.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/stdlib.h new file mode 100644 index 0000000..b1ac1bf --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/stdlib.h @@ -0,0 +1,313 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stdlib.h 8.5 (Berkeley) 5/19/95 + * $FreeBSD$ + */ + +#ifndef _STDLIB_H_ +#define _STDLIB_H_ + +#include +#include +#include + +#if __BSD_VISIBLE +#ifndef _RUNE_T_DECLARED +typedef __rune_t rune_t; +#define _RUNE_T_DECLARED +#endif +#endif + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +typedef struct { + int quot; /* quotient */ + int rem; /* remainder */ +} div_t; + +typedef struct { + long quot; + long rem; +} ldiv_t; + +#define EXIT_FAILURE 1 +#define EXIT_SUCCESS 0 + +#define RAND_MAX 0x7ffffffd + +__BEGIN_DECLS +#ifdef _XLOCALE_H_ +#include +#endif +extern int __mb_cur_max; +extern int ___mb_cur_max(void); +#define MB_CUR_MAX (___mb_cur_max()) + +_Noreturn void abort(void); +int abs(int) __pure2; +int atexit(void (*)(void)); +double atof(const char *); +int atoi(const char *); +long atol(const char *); +void *bsearch(const void *, const void *, size_t, + size_t, int (*)(const void *, const void *)); +void *calloc(size_t, size_t) __malloc_like; +div_t div(int, int) __pure2; +_Noreturn void exit(int); +void free(void *); +char *getenv(const char *); +long labs(long) __pure2; +ldiv_t ldiv(long, long) __pure2; +void *malloc(size_t) __malloc_like; +int mblen(const char *, size_t); +void qsort(void *, size_t, size_t, + int (*)(const void *, const void *)); +int rand(void); +void *realloc(void *, size_t); +void srand(unsigned); +double strtod(const char *__restrict, char **__restrict); +float strtof(const char *__restrict, char **__restrict); +long strtol(const char *__restrict, char **__restrict, int); +long double + strtold(const char *__restrict, char **__restrict); +unsigned long + strtoul(const char *__restrict, char **__restrict, int); +int system(const char *); + +/* + * Functions added in C99 which we make conditionally available in the + * BSD^C89 namespace if the compiler supports `long long'. + * The #if test is more complicated than it ought to be because + * __BSD_VISIBLE implies __ISO_C_VISIBLE == 1999 *even if* `long long' + * is not supported in the compilation environment (which therefore means + * that it can't really be ISO C99). + * + * (The only other extension made by C99 in thie header is _Exit().) + */ +#if __ISO_C_VISIBLE >= 1999 +#ifdef __LONG_LONG_SUPPORTED +/* LONGLONG */ +typedef struct { + long long quot; + long long rem; +} lldiv_t; + +/* LONGLONG */ +long long + atoll(const char *); +/* LONGLONG */ +long long + llabs(long long) __pure2; +/* LONGLONG */ +lldiv_t lldiv(long long, long long) __pure2; +/* LONGLONG */ +long long + strtoll(const char *__restrict, char **__restrict, int); +/* LONGLONG */ +unsigned long long + strtoull(const char *__restrict, char **__restrict, int); +#endif /* __LONG_LONG_SUPPORTED */ + +_Noreturn void _Exit(int); +#endif /* __ISO_C_VISIBLE >= 1999 */ + +/* + * If we're in a mode greater than C99, expose C11 functions. + */ +#if __ISO_C_VISIBLE >= 2011 || __cplusplus >= 201103L +void *aligned_alloc(size_t, size_t) __malloc_like; +int at_quick_exit(void (*)(void)); +_Noreturn void + quick_exit(int); +#endif /* __ISO_C_VISIBLE >= 2011 */ +/* + * Extensions made by POSIX relative to C. + */ +#if __POSIX_VISIBLE >= 199506 || __XSI_VISIBLE +char *realpath(const char *__restrict, char *__restrict); +#endif +#if __POSIX_VISIBLE >= 199506 +int rand_r(unsigned *); /* (TSF) */ +#endif +#if __POSIX_VISIBLE >= 200112 +int posix_memalign(void **, size_t, size_t); /* (ADV) */ +int setenv(const char *, const char *, int); +int unsetenv(const char *); +#endif + +#if __POSIX_VISIBLE >= 200809 || __XSI_VISIBLE +int getsubopt(char **, char *const *, char **); +#ifndef _MKDTEMP_DECLARED +char *mkdtemp(char *); +#define _MKDTEMP_DECLARED +#endif +#ifndef _MKSTEMP_DECLARED +int mkstemp(char *); +#define _MKSTEMP_DECLARED +#endif +#endif /* __POSIX_VISIBLE >= 200809 || __XSI_VISIBLE */ + +/* + * The only changes to the XSI namespace in revision 6 were the deletion + * of the ttyslot() and valloc() functions, which FreeBSD never declared + * in this header. For revision 7, ecvt(), fcvt(), and gcvt(), which + * FreeBSD also does not have, and mktemp(), are to be deleted. + */ +#if __XSI_VISIBLE +/* XXX XSI requires pollution from here. We'd rather not. */ +long a64l(const char *); +double drand48(void); +/* char *ecvt(double, int, int * __restrict, int * __restrict); */ +double erand48(unsigned short[3]); +/* char *fcvt(double, int, int * __restrict, int * __restrict); */ +/* char *gcvt(double, int, int * __restrict, int * __restrict); */ +int grantpt(int); +char *initstate(unsigned long /* XSI requires u_int */, char *, long); +long jrand48(unsigned short[3]); +char *l64a(long); +void lcong48(unsigned short[7]); +long lrand48(void); +#if !defined(_MKTEMP_DECLARED) && (__BSD_VISIBLE || __XSI_VISIBLE <= 600) +char *mktemp(char *); +#define _MKTEMP_DECLARED +#endif +long mrand48(void); +long nrand48(unsigned short[3]); +int posix_openpt(int); +char *ptsname(int); +int putenv(char *); +long random(void); +unsigned short + *seed48(unsigned short[3]); +#ifndef _SETKEY_DECLARED +int setkey(const char *); +#define _SETKEY_DECLARED +#endif +char *setstate(/* const */ char *); +void srand48(long); +void srandom(unsigned long); +int unlockpt(int); +#endif /* __XSI_VISIBLE */ + +#if __BSD_VISIBLE +extern const char *malloc_conf; +extern void (*malloc_message)(void *, const char *); + +/* + * The alloca() function can't be implemented in C, and on some + * platforms it can't be implemented at all as a callable function. + * The GNU C compiler provides a built-in alloca() which we can use; + * in all other cases, provide a prototype, mainly to pacify various + * incarnations of lint. On platforms where alloca() is not in libc, + * programs which use it will fail to link when compiled with non-GNU + * compilers. + */ +#if __GNUC__ >= 2 || defined(__INTEL_COMPILER) +#undef alloca /* some GNU bits try to get cute and define this on their own */ +#define alloca(sz) __builtin_alloca(sz) +#elif defined(lint) +void *alloca(size_t); +#endif + +void abort2(const char *, int, void **) __dead2; +__uint32_t + arc4random(void); +void arc4random_addrandom(unsigned char *, int); +void arc4random_buf(void *, size_t); +void arc4random_stir(void); +__uint32_t + arc4random_uniform(__uint32_t); +#ifdef __BLOCKS__ +int atexit_b(void (^)(void)); +void *bsearch_b(const void *, const void *, size_t, + size_t, int (^)(const void *, const void *)); +#endif +char *getbsize(int *, long *); + /* getcap(3) functions */ +char *cgetcap(char *, const char *, int); +int cgetclose(void); +int cgetent(char **, char **, const char *); +int cgetfirst(char **, char **); +int cgetmatch(const char *, const char *); +int cgetnext(char **, char **); +int cgetnum(char *, const char *, long *); +int cgetset(const char *); +int cgetstr(char *, const char *, char **); +int cgetustr(char *, const char *, char **); + +int daemon(int, int); +char *devname(__dev_t, __mode_t); +char *devname_r(__dev_t, __mode_t, char *, int); +char *fdevname(int); +char *fdevname_r(int, char *, int); +int getloadavg(double [], int); +const char * + getprogname(void); + +int heapsort(void *, size_t, size_t, int (*)(const void *, const void *)); +#ifdef __BLOCKS__ +int heapsort_b(void *, size_t, size_t, int (^)(const void *, const void *)); +void qsort_b(void *, size_t, size_t, + int (^)(const void *, const void *)); +#endif +int l64a_r(long, char *, int); +int mergesort(void *, size_t, size_t, int (*)(const void *, const void *)); +#ifdef __BLOCKS__ +int mergesort_b(void *, size_t, size_t, int (^)(const void *, const void *)); +#endif +int mkostemp(char *, int); +int mkostemps(char *, int, int); +void qsort_r(void *, size_t, size_t, void *, + int (*)(void *, const void *, const void *)); +int radixsort(const unsigned char **, int, const unsigned char *, + unsigned); +void *reallocf(void *, size_t); +int rpmatch(const char *); +void setprogname(const char *); +int sradixsort(const unsigned char **, int, const unsigned char *, + unsigned); +void sranddev(void); +void srandomdev(void); +long long + strtonum(const char *, long long, long long, const char **); + +/* Deprecated interfaces, to be removed in FreeBSD 6.0. */ +__int64_t + strtoq(const char *, char **, int); +__uint64_t + strtouq(const char *, char **, int); + +extern char *suboptarg; /* getsubopt(3) external variable */ +#endif /* __BSD_VISIBLE */ +__END_DECLS + +#endif /* !_STDLIB_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/string.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/string.h new file mode 100644 index 0000000..61e8102 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/string.h @@ -0,0 +1,66 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)string.h 8.1 (Berkeley) 6/2/93 + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2013-2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include +#include +#include + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +__BEGIN_DECLS + +void *memchr(const void *, int, size_t) __pure; +int memcmp(const void *, const void *, size_t) __pure; +void *memcpy(void * __restrict, const void * __restrict, size_t); +void *memmove(void *, const void *, size_t); +void *memset(void *, int, size_t); + +char *strchr(const char *, int) __pure; +int strcmp(const char *, const char *) __pure; +size_t strlen(const char *) __pure; +int strncmp(const char *, const char *, size_t) __pure; +int strcasecmp(const char *, const char *); + +__END_DECLS + +#endif /* _STRING_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/strings.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/strings.h new file mode 100644 index 0000000..2210df0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/strings.h @@ -0,0 +1,71 @@ +/*- + * Copyright (c) 2002 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _STRINGS_H_ +#define _STRINGS_H_ + +#include +#include + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +__BEGIN_DECLS +#if __BSD_VISIBLE || __POSIX_VISIBLE <= 200112 +int bcmp(const void *, const void *, size_t) __pure; /* LEGACY */ +void bcopy(const void *, void *, size_t); /* LEGACY */ +void bzero(void *, size_t); /* LEGACY */ +#endif +#if __BSD_VISIBLE +void explicit_bzero(void *, size_t); +#endif +#if __XSI_VISIBLE +int ffs(int) __pure2; +#endif +#if __BSD_VISIBLE +int ffsl(long) __pure2; +int ffsll(long long) __pure2; +int fls(int) __pure2; +int flsl(long) __pure2; +int flsll(long long) __pure2; +#endif +#if __BSD_VISIBLE || __POSIX_VISIBLE <= 200112 +char *index(const char *, int) __pure; /* LEGACY */ +char *rindex(const char *, int) __pure; /* LEGACY */ +#endif +int strcasecmp(const char *, const char *) __pure; +int strncasecmp(const char *, const char *, size_t) __pure; + +#if __POSIX_VISIBLE >= 200809 || defined(_XLOCALE_H_) +#include +#endif +__END_DECLS + +#endif /* _STRINGS_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/_null.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/_null.h new file mode 100644 index 0000000..92706c6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/_null.h @@ -0,0 +1,47 @@ +/*- + * Copyright (c) 2003 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef NULL + +#if !defined(__cplusplus) +#define NULL ((void *)0) +#else +#if __cplusplus >= 201103L +#define NULL nullptr +#elif defined(__GNUG__) && defined(__GNUC__) && __GNUC__ >= 4 +#define NULL __null +#else +#if defined(__LP64__) +#define NULL (0L) +#else +#define NULL 0 +#endif /* __LP64__ */ +#endif /* __GNUG__ */ +#endif /* !__cplusplus */ + +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/_stdint.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/_stdint.h new file mode 100644 index 0000000..d0f9249 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/_stdint.h @@ -0,0 +1,82 @@ +/*- + * Copyright (c) 2011 David E. O'Brien + * Copyright (c) 2001 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS__STDINT_H_ +#define _SYS__STDINT_H_ + +#ifndef _INT8_T_DECLARED +typedef __int8_t int8_t; +#define _INT8_T_DECLARED +#endif + +#ifndef _INT16_T_DECLARED +typedef __int16_t int16_t; +#define _INT16_T_DECLARED +#endif + +#ifndef _INT32_T_DECLARED +typedef __int32_t int32_t; +#define _INT32_T_DECLARED +#endif + +#ifndef _INT64_T_DECLARED +typedef __int64_t int64_t; +#define _INT64_T_DECLARED +#endif + +#ifndef _UINT8_T_DECLARED +typedef __uint8_t uint8_t; +#define _UINT8_T_DECLARED +#endif + +#ifndef _UINT16_T_DECLARED +typedef __uint16_t uint16_t; +#define _UINT16_T_DECLARED +#endif + +#ifndef _UINT32_T_DECLARED +typedef __uint32_t uint32_t; +#define _UINT32_T_DECLARED +#endif + +#ifndef _UINT64_T_DECLARED +typedef __uint64_t uint64_t; +#define _UINT64_T_DECLARED +#endif + +#ifndef _INTPTR_T_DECLARED +typedef __intptr_t intptr_t; +#define _INTPTR_T_DECLARED +#endif +#ifndef _UINTPTR_T_DECLARED +typedef __uintptr_t uintptr_t; +#define _UINTPTR_T_DECLARED +#endif + +#endif /* !_SYS__STDINT_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/_timespec.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/_timespec.h new file mode 100644 index 0000000..d51559c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/_timespec.h @@ -0,0 +1,49 @@ +/*- + * Copyright (c) 1982, 1986, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)time.h 8.5 (Berkeley) 5/4/95 + * from: FreeBSD: src/sys/sys/time.h,v 1.43 2000/03/20 14:09:05 phk Exp + * $FreeBSD$ + */ + +#ifndef _SYS__TIMESPEC_H_ +#define _SYS__TIMESPEC_H_ + +#include + +#ifndef _TIME_T_DECLARED +typedef __time_t time_t; +#define _TIME_T_DECLARED +#endif + +struct timespec { + time_t tv_sec; /* seconds */ + long tv_nsec; /* and nanoseconds */ +}; + +#endif /* !_SYS__TIMESPEC_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/_types.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/_types.h new file mode 100644 index 0000000..c59afd3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/_types.h @@ -0,0 +1,106 @@ +/*- + * Copyright (c) 2002 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS__TYPES_H_ +#define _SYS__TYPES_H_ + +#include +#include + +/* + * Standard type definitions. + */ +typedef __uint32_t __blksize_t; /* file block size */ +typedef __int64_t __blkcnt_t; /* file block count */ +typedef __int32_t __clockid_t; /* clock_gettime()... */ +typedef __uint64_t __cap_rights_t; /* capability rights */ +typedef __uint32_t __fflags_t; /* file flags */ +typedef __uint64_t __fsblkcnt_t; +typedef __uint64_t __fsfilcnt_t; +typedef __uint32_t __gid_t; +typedef __int64_t __id_t; /* can hold a gid_t, pid_t, or uid_t */ +typedef __uint32_t __ino_t; /* inode number */ +typedef long __key_t; /* IPC key (for Sys V IPC) */ +typedef __int32_t __lwpid_t; /* Thread ID (a.k.a. LWP) */ +typedef __uint16_t __mode_t; /* permissions */ +typedef int __accmode_t; /* access permissions */ +typedef int __nl_item; +typedef __uint16_t __nlink_t; /* link count */ +typedef __int64_t __off_t; /* file offset */ +typedef __int32_t __pid_t; /* process [group] */ +typedef __int64_t __rlim_t; /* resource limit - intentionally */ + /* signed, because of legacy code */ + /* that uses -1 for RLIM_INFINITY */ +typedef __uint8_t __sa_family_t; +typedef __uint32_t __socklen_t; +typedef long __suseconds_t; /* microseconds (signed) */ +typedef struct __timer *__timer_t; /* timer_gettime()... */ +typedef struct __mq *__mqd_t; /* mq_open()... */ +typedef __uint32_t __uid_t; +typedef unsigned int __useconds_t; /* microseconds (unsigned) */ +typedef int __cpuwhich_t; /* which parameter for cpuset. */ +typedef int __cpulevel_t; /* level parameter for cpuset. */ +typedef int __cpusetid_t; /* cpuset identifier. */ + +/* + * Unusual type definitions. + */ +/* + * rune_t is declared to be an ``int'' instead of the more natural + * ``unsigned long'' or ``long''. Two things are happening here. It is not + * unsigned so that EOF (-1) can be naturally assigned to it and used. Also, + * it looks like 10646 will be a 31 bit standard. This means that if your + * ints cannot hold 32 bits, you will be in trouble. The reason an int was + * chosen over a long is that the is*() and to*() routines take ints (says + * ANSI C), but they use __ct_rune_t instead of int. + * + * NOTE: rune_t is not covered by ANSI nor other standards, and should not + * be instantiated outside of lib/libc/locale. Use wchar_t. wchar_t and + * rune_t must be the same type. Also, wint_t must be no narrower than + * wchar_t, and should be able to hold all members of the largest + * character set plus one extra value (WEOF), and must be at least 16 bits. + */ +typedef int __ct_rune_t; /* arg type for ctype funcs */ +typedef __ct_rune_t __rune_t; /* rune_t (see above) */ +typedef __ct_rune_t __wchar_t; /* wchar_t (see above) */ +typedef __ct_rune_t __wint_t; /* wint_t (see above) */ + +typedef __uint32_t __dev_t; /* device number */ + +typedef __uint32_t __fixpt_t; /* fixed point number */ + +/* + * mbstate_t is an opaque object to keep conversion state during multibyte + * stream conversions. + */ +typedef union { + char __mbstate8[128]; + __int64_t _mbstateL; /* for alignment */ +} __mbstate_t; + +#endif /* !_SYS__TYPES_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/cdefs.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/cdefs.h new file mode 100644 index 0000000..70c09fd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/cdefs.h @@ -0,0 +1,688 @@ +/*- + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Berkeley Software Design, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)cdefs.h 8.8 (Berkeley) 1/9/95 + * $FreeBSD$ + */ + +#ifndef _SYS_CDEFS_H_ +#define _SYS_CDEFS_H_ + +#if defined(__cplusplus) +#define __BEGIN_DECLS extern "C" { +#define __END_DECLS } +#else +#define __BEGIN_DECLS +#define __END_DECLS +#endif + +/* + * This code has been put in place to help reduce the addition of + * compiler specific defines in FreeBSD code. It helps to aid in + * having a compiler-agnostic source tree. + */ + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) + +#if __GNUC__ >= 3 || defined(__INTEL_COMPILER) +#define __GNUCLIKE_ASM 3 +#define __GNUCLIKE_MATH_BUILTIN_CONSTANTS +#else +#define __GNUCLIKE_ASM 2 +#endif +#define __GNUCLIKE___TYPEOF 1 +#define __GNUCLIKE___OFFSETOF 1 +#define __GNUCLIKE___SECTION 1 + +#ifndef __INTEL_COMPILER +# define __GNUCLIKE_CTOR_SECTION_HANDLING 1 +#endif + +#define __GNUCLIKE_BUILTIN_CONSTANT_P 1 +# if defined(__INTEL_COMPILER) && defined(__cplusplus) \ + && __INTEL_COMPILER < 800 +# undef __GNUCLIKE_BUILTIN_CONSTANT_P +# endif + +#if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3) && !defined(__INTEL_COMPILER) +# define __GNUCLIKE_BUILTIN_VARARGS 1 +# define __GNUCLIKE_BUILTIN_STDARG 1 +# define __GNUCLIKE_BUILTIN_VAALIST 1 +#endif + +#if defined(__GNUC__) +# define __GNUC_VA_LIST_COMPATIBILITY 1 +#endif + +#ifndef __INTEL_COMPILER +# define __GNUCLIKE_BUILTIN_NEXT_ARG 1 +# define __GNUCLIKE_MATH_BUILTIN_RELOPS +#endif + +#define __GNUCLIKE_BUILTIN_MEMCPY 1 + +/* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */ +#define __CC_SUPPORTS_INLINE 1 +#define __CC_SUPPORTS___INLINE 1 +#define __CC_SUPPORTS___INLINE__ 1 + +#define __CC_SUPPORTS___FUNC__ 1 +#define __CC_SUPPORTS_WARNING 1 + +#define __CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */ + +#define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1 + +#endif /* __GNUC__ || __INTEL_COMPILER */ + +/* + * Macro to test if we're using a specific version of gcc or later. + */ +#if defined(__GNUC__) && !defined(__INTEL_COMPILER) +#define __GNUC_PREREQ__(ma, mi) \ + (__GNUC__ > (ma) || __GNUC__ == (ma) && __GNUC_MINOR__ >= (mi)) +#else +#define __GNUC_PREREQ__(ma, mi) 0 +#endif + +/* + * The __CONCAT macro is used to concatenate parts of symbol names, e.g. + * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. + * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI + * mode -- there must be no spaces between its arguments, and for nested + * __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also + * concatenate double-quoted strings produced by the __STRING macro, but + * this only works with ANSI C. + * + * __XSTRING is like __STRING, but it expands any macros in its argument + * first. It is only available with ANSI C. + */ +#if defined(__STDC__) || defined(__cplusplus) +#define __P(protos) protos /* full-blown ANSI C */ +#define __CONCAT1(x,y) x ## y +#define __CONCAT(x,y) __CONCAT1(x,y) +#define __STRING(x) #x /* stringify without expanding x */ +#define __XSTRING(x) __STRING(x) /* expand x, then stringify */ + +#define __const const /* define reserved names to standard */ +#define __signed signed +#define __volatile volatile +#if defined(__cplusplus) +#define __inline inline /* convert to C++ keyword */ +#else +#if !(defined(__CC_SUPPORTS___INLINE)) +#define __inline /* delete GCC keyword */ +#endif /* ! __CC_SUPPORTS___INLINE */ +#endif /* !__cplusplus */ + +#else /* !(__STDC__ || __cplusplus) */ +#define __P(protos) () /* traditional C preprocessor */ +#define __CONCAT(x,y) x/**/y +#define __STRING(x) "x" + +#if !defined(__CC_SUPPORTS___INLINE) +#define __const /* delete pseudo-ANSI C keywords */ +#define __inline +#define __signed +#define __volatile +/* + * In non-ANSI C environments, new programs will want ANSI-only C keywords + * deleted from the program and old programs will want them left alone. + * When using a compiler other than gcc, programs using the ANSI C keywords + * const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS. + * When using "gcc -traditional", we assume that this is the intent; if + * __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone. + */ +#ifndef NO_ANSI_KEYWORDS +#define const /* delete ANSI C keywords */ +#define inline +#define signed +#define volatile +#endif /* !NO_ANSI_KEYWORDS */ +#endif /* !__CC_SUPPORTS___INLINE */ +#endif /* !(__STDC__ || __cplusplus) */ + +/* + * Compiler-dependent macros to help declare dead (non-returning) and + * pure (no side effects) functions, and unused variables. They are + * null except for versions of gcc that are known to support the features + * properly (old versions of gcc-2 supported the dead and pure features + * in a different (wrong) way). If we do not provide an implementation + * for a given compiler, let the compile fail if it is told to use + * a feature that we cannot live without. + */ +#ifdef lint +#define __dead2 +#define __pure2 +#define __unused +#define __packed +#define __aligned(x) +#define __section(x) +#else +#if !__GNUC_PREREQ__(2, 5) && !defined(__INTEL_COMPILER) +#define __dead2 +#define __pure2 +#define __unused +#endif +#if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 && !defined(__INTEL_COMPILER) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused +/* XXX Find out what to do for __packed, __aligned and __section */ +#endif +#if __GNUC_PREREQ__(2, 7) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) +#endif +#if defined(__INTEL_COMPILER) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) +#endif +#endif + +#if !__GNUC_PREREQ__(2, 95) +#define __alignof(x) __offsetof(struct { char __a; x __b; }, __b) +#endif + +/* + * Keywords added in C11. + */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define _Alignas(e) alignas(e) +#define _Alignof(e) alignof(e) +#define _Noreturn [[noreturn]] +#define _Static_assert(e, s) static_assert(e, s) +/* FIXME: change this to thread_local when clang in base supports it */ +#define _Thread_local __thread +#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +/* Do nothing. They are language keywords. */ +#else +/* Not supported. Implement them using our versions. */ +#define _Alignas(x) __aligned(x) +#define _Alignof(x) __alignof(x) +#define _Noreturn __dead2 +#define _Thread_local __thread +#ifdef __COUNTER__ +#define _Static_assert(x, y) __Static_assert(x, __COUNTER__) +#define __Static_assert(x, y) ___Static_assert(x, y) +#define ___Static_assert(x, y) typedef char __assert_ ## y[(x) ? 1 : -1] +#else +#define _Static_assert(x, y) struct __hack +#endif +#endif + +/* + * Emulation of C11 _Generic(). Unlike the previously defined C11 + * keywords, it is not possible to implement this using exactly the same + * syntax. Therefore implement something similar under the name + * __generic(). Unlike _Generic(), this macro can only distinguish + * between a single type, so it requires nested invocations to + * distinguish multiple cases. + */ + +#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +#define __generic(expr, t, yes, no) \ + _Generic(expr, t: yes, default: no) +#elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus) +#define __generic(expr, t, yes, no) \ + __builtin_choose_expr( \ + __builtin_types_compatible_p(__typeof(expr), t), yes, no) +#endif + +#if __GNUC_PREREQ__(2, 96) +#define __malloc_like __attribute__((__malloc__)) +#define __pure __attribute__((__pure__)) +#else +#define __malloc_like +#define __pure +#endif + +#if __GNUC_PREREQ__(3, 1) || (defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 800) +#define __always_inline __attribute__((__always_inline__)) +#else +#define __always_inline +#endif + +#if __GNUC_PREREQ__(3, 1) +#define __noinline __attribute__ ((__noinline__)) +#define __deprecated __attribute__ ((__deprecated__)) +#else +#define __noinline +#define __deprecated +#endif + +#if __GNUC_PREREQ__(3, 3) +#define __nonnull(x) __attribute__((__nonnull__(x))) +#else +#define __nonnull(x) +#endif + +#if __GNUC_PREREQ__(3, 4) +#define __fastcall __attribute__((__fastcall__)) +#else +#define __fastcall +#endif + +#if __GNUC_PREREQ__(4, 1) +#define __returns_twice __attribute__((__returns_twice__)) +#else +#define __returns_twice +#endif + +/* XXX: should use `#if __STDC_VERSION__ < 199901'. */ +#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER) +#define __func__ NULL +#endif + +#if (defined(__INTEL_COMPILER) || (defined(__GNUC__) && __GNUC__ >= 2)) && !defined(__STRICT_ANSI__) || __STDC_VERSION__ >= 199901 +#define __LONG_LONG_SUPPORTED +#endif + +/* C++11 exposes a load of C99 stuff */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define __LONG_LONG_SUPPORTED +#ifndef __STDC_LIMIT_MACROS +#define __STDC_LIMIT_MACROS +#endif +#ifndef __STDC_CONSTANT_MACROS +#define __STDC_CONSTANT_MACROS +#endif +#endif + +/* + * GCC 2.95 provides `__restrict' as an extension to C90 to support the + * C99-specific `restrict' type qualifier. We happen to use `__restrict' as + * a way to define the `restrict' type qualifier without disturbing older + * software that is unaware of C99 keywords. + */ +#if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95) +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901 || defined(lint) +#define __restrict +#else +#define __restrict restrict +#endif +#endif + +/* + * GNU C version 2.96 adds explicit branch prediction so that + * the CPU back-end can hint the processor and also so that + * code blocks can be reordered such that the predicted path + * sees a more linear flow, thus improving cache behavior, etc. + * + * The following two macros provide us with a way to utilize this + * compiler feature. Use __predict_true() if you expect the expression + * to evaluate to true, and __predict_false() if you expect the + * expression to evaluate to false. + * + * A few notes about usage: + * + * * Generally, __predict_false() error condition checks (unless + * you have some _strong_ reason to do otherwise, in which case + * document it), and/or __predict_true() `no-error' condition + * checks, assuming you want to optimize for the no-error case. + * + * * Other than that, if you don't know the likelihood of a test + * succeeding from empirical or other `hard' evidence, don't + * make predictions. + * + * * These are meant to be used in places that are run `a lot'. + * It is wasteful to make predictions in code that is run + * seldomly (e.g. at subsystem initialization time) as the + * basic block reordering that this affects can often generate + * larger code. + */ +#if __GNUC_PREREQ__(2, 96) +#define __predict_true(exp) __builtin_expect((exp), 1) +#define __predict_false(exp) __builtin_expect((exp), 0) +#else +#define __predict_true(exp) (exp) +#define __predict_false(exp) (exp) +#endif + +#if __GNUC_PREREQ__(4, 2) +#define __hidden __attribute__((__visibility__("hidden"))) +#define __exported __attribute__((__visibility__("default"))) +#else +#define __hidden +#define __exported +#endif + +/* + * We define this here since , , and + * require it. + */ +#if __GNUC_PREREQ__(4, 1) +#define __offsetof(type, field) __builtin_offsetof(type, field) +#else +#ifndef __cplusplus +#define __offsetof(type, field) \ + ((__size_t)(__uintptr_t)((const volatile void *)&((type *)0)->field)) +#else +#define __offsetof(type, field) \ + (__offsetof__ (reinterpret_cast <__size_t> \ + (&reinterpret_cast \ + (static_cast (0)->field)))) +#endif +#endif +#define __rangeof(type, start, end) \ + (__offsetof(type, end) - __offsetof(type, start)) + +/* + * Given the pointer x to the member m of the struct s, return + * a pointer to the containing structure. When using GCC, we first + * assign pointer x to a local variable, to check that its type is + * compatible with member m. + */ +#if __GNUC_PREREQ__(3, 1) +#define __containerof(x, s, m) ({ \ + const volatile __typeof(((s *)0)->m) *__x = (x); \ + __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\ +}) +#else +#define __containerof(x, s, m) \ + __DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m)) +#endif + +/* + * Compiler-dependent macros to declare that functions take printf-like + * or scanf-like arguments. They are null except for versions of gcc + * that are known to support the features properly (old versions of gcc-2 + * didn't permit keeping the keywords out of the application namespace). + */ +#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER) +#define __printflike(fmtarg, firstvararg) +#define __scanflike(fmtarg, firstvararg) +#define __format_arg(fmtarg) +#define __strfmonlike(fmtarg, firstvararg) +#define __strftimelike(fmtarg, firstvararg) +#else +#define __printflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf__, fmtarg, firstvararg))) +#define __scanflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__scanf__, fmtarg, firstvararg))) +#define __format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg))) +#define __strfmonlike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strfmon__, fmtarg, firstvararg))) +#define __strftimelike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strftime__, fmtarg, firstvararg))) +#endif + +/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */ +#if __FreeBSD_cc_version >= 300001 && defined(__GNUC__) && !defined(__INTEL_COMPILER) +#define __printf0like(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf0__, fmtarg, firstvararg))) +#else +#define __printf0like(fmtarg, firstvararg) +#endif + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) +#ifndef __INTEL_COMPILER +#define __strong_reference(sym,aliassym) \ + extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym))) +#endif +#ifdef __STDC__ +#define __weak_reference(sym,alias) \ + __asm__(".weak " #alias); \ + __asm__(".equ " #alias ", " #sym) +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning." #sym); \ + __asm__(".asciz \"" msg "\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@" #verid) +#define __sym_default(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@@" #verid) +#else +#define __weak_reference(sym,alias) \ + __asm__(".weak alias"); \ + __asm__(".equ alias, sym") +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning.sym"); \ + __asm__(".asciz \"msg\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver impl, sym@verid") +#define __sym_default(impl,sym,verid) \ + __asm__(".symver impl, sym@@verid") +#endif /* __STDC__ */ +#endif /* __GNUC__ || __INTEL_COMPILER */ + +#define __GLOBL1(sym) __asm__(".globl " #sym) +#define __GLOBL(sym) __GLOBL1(sym) + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) +#define __IDSTRING(name,string) __asm__(".ident\t\"" string "\"") +#else +/* + * The following definition might not work well if used in header files, + * but it should be better than nothing. If you want a "do nothing" + * version, then it should generate some harmless declaration, such as: + * #define __IDSTRING(name,string) struct __hack + */ +#define __IDSTRING(name,string) static const char name[] __unused = string +#endif + +/* + * Embed the rcs id of a source file in the resulting library. Note that in + * more recent ELF binutils, we use .ident allowing the ID to be stripped. + * Usage: + * __FBSDID("$FreeBSD$"); + */ +#ifndef __FBSDID +#if !defined(lint) && !defined(STRIP_FBSDID) +#define __FBSDID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __FBSDID(s) struct __hack +#endif +#endif + +#ifndef __RCSID +#ifndef NO__RCSID +#define __RCSID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __RCSID(s) struct __hack +#endif +#endif + +#ifndef __RCSID_SOURCE +#ifndef NO__RCSID_SOURCE +#define __RCSID_SOURCE(s) __IDSTRING(__CONCAT(__rcsid_source_,__LINE__),s) +#else +#define __RCSID_SOURCE(s) struct __hack +#endif +#endif + +#ifndef __SCCSID +#ifndef NO__SCCSID +#define __SCCSID(s) __IDSTRING(__CONCAT(__sccsid_,__LINE__),s) +#else +#define __SCCSID(s) struct __hack +#endif +#endif + +#ifndef __COPYRIGHT +#ifndef NO__COPYRIGHT +#define __COPYRIGHT(s) __IDSTRING(__CONCAT(__copyright_,__LINE__),s) +#else +#define __COPYRIGHT(s) struct __hack +#endif +#endif + +#ifndef __DECONST +#define __DECONST(type, var) ((type)(__uintptr_t)(const void *)(var)) +#endif + +#ifndef __DEVOLATILE +#define __DEVOLATILE(type, var) ((type)(__uintptr_t)(volatile void *)(var)) +#endif + +#ifndef __DEQUALIFY +#define __DEQUALIFY(type, var) ((type)(__uintptr_t)(const volatile void *)(var)) +#endif + +/*- + * The following definitions are an extension of the behavior originally + * implemented in , but with a different level of granularity. + * POSIX.1 requires that the macros we test be defined before any standard + * header file is included. + * + * Here's a quick run-down of the versions: + * defined(_POSIX_SOURCE) 1003.1-1988 + * _POSIX_C_SOURCE == 1 1003.1-1990 + * _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option + * _POSIX_C_SOURCE == 199309 1003.1b-1993 + * _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995, + * and the omnibus ISO/IEC 9945-1: 1996 + * _POSIX_C_SOURCE == 200112 1003.1-2001 + * _POSIX_C_SOURCE == 200809 1003.1-2008 + * + * In addition, the X/Open Portability Guide, which is now the Single UNIX + * Specification, defines a feature-test macro which indicates the version of + * that specification, and which subsumes _POSIX_C_SOURCE. + * + * Our macros begin with two underscores to avoid namespace screwage. + */ + +/* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 1 +#undef _POSIX_C_SOURCE /* Probably illegal, but beyond caring now. */ +#define _POSIX_C_SOURCE 199009 +#endif + +/* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 2 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199209 +#endif + +/* Deal with various X/Open Portability Guides and Single UNIX Spec. */ +#ifdef _XOPEN_SOURCE +#if _XOPEN_SOURCE - 0 >= 700 +#define __XSI_VISIBLE 700 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809 +#elif _XOPEN_SOURCE - 0 >= 600 +#define __XSI_VISIBLE 600 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200112 +#elif _XOPEN_SOURCE - 0 >= 500 +#define __XSI_VISIBLE 500 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199506 +#endif +#endif + +/* + * Deal with all versions of POSIX. The ordering relative to the tests above is + * important. + */ +#if defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE) +#define _POSIX_C_SOURCE 198808 +#endif +#ifdef _POSIX_C_SOURCE +#if _POSIX_C_SOURCE >= 200809 +#define __POSIX_VISIBLE 200809 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 200112 +#define __POSIX_VISIBLE 200112 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 199506 +#define __POSIX_VISIBLE 199506 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199309 +#define __POSIX_VISIBLE 199309 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199209 +#define __POSIX_VISIBLE 199209 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199009 +#define __POSIX_VISIBLE 199009 +#define __ISO_C_VISIBLE 1990 +#else +#define __POSIX_VISIBLE 198808 +#define __ISO_C_VISIBLE 0 +#endif /* _POSIX_C_SOURCE */ +#else +/*- + * Deal with _ANSI_SOURCE: + * If it is defined, and no other compilation environment is explicitly + * requested, then define our internal feature-test macros to zero. This + * makes no difference to the preprocessor (undefined symbols in preprocessing + * expressions are defined to have value zero), but makes it more convenient for + * a test program to print out the values. + * + * If a program mistakenly defines _ANSI_SOURCE and some other macro such as + * _POSIX_C_SOURCE, we will assume that it wants the broader compilation + * environment (and in fact we will never get here). + */ +#if defined(_ANSI_SOURCE) /* Hide almost everything. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1990 +#elif defined(_C99_SOURCE) /* Localism to specify strict C99 env. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1999 +#else /* Default environment: show everything. */ +#define __POSIX_VISIBLE 200809 +#define __XSI_VISIBLE 700 +#define __BSD_VISIBLE 1 +#define __ISO_C_VISIBLE 1999 +#endif +#endif + +#ifndef __has_feature +#define __has_feature(x) 0 +#endif +#ifndef __has_include +#define __has_include(x) 0 +#endif +#ifndef __has_builtin +#define __has_builtin(x) 0 +#endif + +#if defined(__mips) || defined(__powerpc64__) || defined(__arm__) +#define __NO_TLS 1 +#endif + +#endif /* !_SYS_CDEFS_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/ctype.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/ctype.h new file mode 100644 index 0000000..f2758b7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/ctype.h @@ -0,0 +1,59 @@ +/*- + * Copyright (c) 1982, 1988, 1991, 1993 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2009-2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#ifndef _SYS_CTYPE_H_ +#define _SYS_CTYPE_H_ + +#define isspace(c) ((c) == ' ' || ((c) >= '\t' && (c) <= '\r')) +#define isascii(c) (((c) & ~0x7f) == 0) +#define isupper(c) ((c) >= 'A' && (c) <= 'Z') +#define islower(c) ((c) >= 'a' && (c) <= 'z') +#define isalpha(c) (isupper(c) || islower(c)) +#define isdigit(c) ((c) >= '0' && (c) <= '9') +#define isxdigit(c) (isdigit(c) \ + || ((c) >= 'A' && (c) <= 'F') \ + || ((c) >= 'a' && (c) <= 'f')) +#define isprint(c) ((c) >= ' ' && (c) <= '~') + +#define toupper(c) ((c) - 0x20 * (((c) >= 'a') && ((c) <= 'z'))) +#define tolower(c) ((c) + 0x20 * (((c) >= 'A') && ((c) <= 'Z'))) + +#endif /* !_SYS_CTYPE_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/errno.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/errno.h new file mode 100644 index 0000000..f595514 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/errno.h @@ -0,0 +1,193 @@ +/*- + * Copyright (c) 1982, 1986, 1989, 1993 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)errno.h 8.5 (Berkeley) 1/21/94 + * $FreeBSD$ + */ + +#ifndef _SYS_ERRNO_H_ +#define _SYS_ERRNO_H_ + +#ifndef _KERNEL +#include +__BEGIN_DECLS +int * __error(void); +__END_DECLS +#define errno (* __error()) +#endif + +#define EPERM 1 /* Operation not permitted */ +#define ENOENT 2 /* No such file or directory */ +#define ESRCH 3 /* No such process */ +#define EINTR 4 /* Interrupted system call */ +#define EIO 5 /* Input/output error */ +#define ENXIO 6 /* Device not configured */ +#define E2BIG 7 /* Argument list too long */ +#define ENOEXEC 8 /* Exec format error */ +#define EBADF 9 /* Bad file descriptor */ +#define ECHILD 10 /* No child processes */ +#define EDEADLK 11 /* Resource deadlock avoided */ + /* 11 was EAGAIN */ +#define ENOMEM 12 /* Cannot allocate memory */ +#define EACCES 13 /* Permission denied */ +#define EFAULT 14 /* Bad address */ +#ifndef _POSIX_SOURCE +#define ENOTBLK 15 /* Block device required */ +#endif +#define EBUSY 16 /* Device busy */ +#define EEXIST 17 /* File exists */ +#define EXDEV 18 /* Cross-device link */ +#define ENODEV 19 /* Operation not supported by device */ +#define ENOTDIR 20 /* Not a directory */ +#define EISDIR 21 /* Is a directory */ +#define EINVAL 22 /* Invalid argument */ +#define ENFILE 23 /* Too many open files in system */ +#define EMFILE 24 /* Too many open files */ +#define ENOTTY 25 /* Inappropriate ioctl for device */ +#ifndef _POSIX_SOURCE +#define ETXTBSY 26 /* Text file busy */ +#endif +#define EFBIG 27 /* File too large */ +#define ENOSPC 28 /* No space left on device */ +#define ESPIPE 29 /* Illegal seek */ +#define EROFS 30 /* Read-only filesystem */ +#define EMLINK 31 /* Too many links */ +#define EPIPE 32 /* Broken pipe */ + +/* math software */ +#define EDOM 33 /* Numerical argument out of domain */ +#define ERANGE 34 /* Result too large */ + +/* non-blocking and interrupt i/o */ +#define EAGAIN 35 /* Resource temporarily unavailable */ +#ifndef _POSIX_SOURCE +#define EWOULDBLOCK EAGAIN /* Operation would block */ +#define EINPROGRESS 36 /* Operation now in progress */ +#define EALREADY 37 /* Operation already in progress */ + +/* ipc/network software -- argument errors */ +#define ENOTSOCK 38 /* Socket operation on non-socket */ +#define EDESTADDRREQ 39 /* Destination address required */ +#define EMSGSIZE 40 /* Message too long */ +#define EPROTOTYPE 41 /* Protocol wrong type for socket */ +#define ENOPROTOOPT 42 /* Protocol not available */ +#define EPROTONOSUPPORT 43 /* Protocol not supported */ +#define ESOCKTNOSUPPORT 44 /* Socket type not supported */ +#define EOPNOTSUPP 45 /* Operation not supported */ +#define ENOTSUP EOPNOTSUPP /* Operation not supported */ +#define EPFNOSUPPORT 46 /* Protocol family not supported */ +#define EAFNOSUPPORT 47 /* Address family not supported by protocol family */ +#define EADDRINUSE 48 /* Address already in use */ +#define EADDRNOTAVAIL 49 /* Can't assign requested address */ + +/* ipc/network software -- operational errors */ +#define ENETDOWN 50 /* Network is down */ +#define ENETUNREACH 51 /* Network is unreachable */ +#define ENETRESET 52 /* Network dropped connection on reset */ +#define ECONNABORTED 53 /* Software caused connection abort */ +#define ECONNRESET 54 /* Connection reset by peer */ +#define ENOBUFS 55 /* No buffer space available */ +#define EISCONN 56 /* Socket is already connected */ +#define ENOTCONN 57 /* Socket is not connected */ +#define ESHUTDOWN 58 /* Can't send after socket shutdown */ +#define ETOOMANYREFS 59 /* Too many references: can't splice */ +#define ETIMEDOUT 60 /* Operation timed out */ +#define ECONNREFUSED 61 /* Connection refused */ + +#define ELOOP 62 /* Too many levels of symbolic links */ +#endif /* _POSIX_SOURCE */ +#define ENAMETOOLONG 63 /* File name too long */ + +/* should be rearranged */ +#ifndef _POSIX_SOURCE +#define EHOSTDOWN 64 /* Host is down */ +#define EHOSTUNREACH 65 /* No route to host */ +#endif /* _POSIX_SOURCE */ +#define ENOTEMPTY 66 /* Directory not empty */ + +/* quotas & mush */ +#ifndef _POSIX_SOURCE +#define EPROCLIM 67 /* Too many processes */ +#define EUSERS 68 /* Too many users */ +#define EDQUOT 69 /* Disc quota exceeded */ + +/* Network File System */ +#define ESTALE 70 /* Stale NFS file handle */ +#define EREMOTE 71 /* Too many levels of remote in path */ +#define EBADRPC 72 /* RPC struct is bad */ +#define ERPCMISMATCH 73 /* RPC version wrong */ +#define EPROGUNAVAIL 74 /* RPC prog. not avail */ +#define EPROGMISMATCH 75 /* Program version wrong */ +#define EPROCUNAVAIL 76 /* Bad procedure for program */ +#endif /* _POSIX_SOURCE */ + +#define ENOLCK 77 /* No locks available */ +#define ENOSYS 78 /* Function not implemented */ + +#ifndef _POSIX_SOURCE +#define EFTYPE 79 /* Inappropriate file type or format */ +#define EAUTH 80 /* Authentication error */ +#define ENEEDAUTH 81 /* Need authenticator */ +#define EIDRM 82 /* Identifier removed */ +#define ENOMSG 83 /* No message of desired type */ +#define EOVERFLOW 84 /* Value too large to be stored in data type */ +#define ECANCELED 85 /* Operation canceled */ +#define EILSEQ 86 /* Illegal byte sequence */ +#define ENOATTR 87 /* Attribute not found */ + +#define EDOOFUS 88 /* Programming error */ +#endif /* _POSIX_SOURCE */ + +#define EBADMSG 89 /* Bad message */ +#define EMULTIHOP 90 /* Multihop attempted */ +#define ENOLINK 91 /* Link has been severed */ +#define EPROTO 92 /* Protocol error */ + +#ifndef _POSIX_SOURCE +#define ENOTCAPABLE 93 /* Capabilities insufficient */ +#define ECAPMODE 94 /* Not permitted in capability mode */ +#endif /* _POSIX_SOURCE */ + +#ifndef _POSIX_SOURCE +#define ELAST 94 /* Must be equal largest errno */ +#endif /* _POSIX_SOURCE */ + +#ifdef _KERNEL +/* pseudo-errors returned inside kernel to modify return to process */ +#define ERESTART (-1) /* restart syscall */ +#define EJUSTRETURN (-2) /* don't modify regs, just return */ +#define ENOIOCTL (-3) /* ioctl not handled by this layer */ +#define EDIRIOCTL (-4) /* do direct ioctl in GEOM */ +#endif + +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/limits.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/limits.h new file mode 100644 index 0000000..c56a337 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/limits.h @@ -0,0 +1,100 @@ +/*- + * Copyright (c) 1988, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS_LIMITS_H_ +#define _SYS_LIMITS_H_ + +#include +#include + +#define CHAR_BIT __CHAR_BIT /* number of bits in a char */ + +#define SCHAR_MAX __SCHAR_MAX /* max value for a signed char */ +#define SCHAR_MIN __SCHAR_MIN /* min value for a signed char */ + +#define UCHAR_MAX __UCHAR_MAX /* max value for an unsigned char */ + +#ifdef __CHAR_UNSIGNED__ +#define CHAR_MAX UCHAR_MAX /* max value for a char */ +#define CHAR_MIN 0 /* min value for a char */ +#else +#define CHAR_MAX SCHAR_MAX +#define CHAR_MIN SCHAR_MIN +#endif + +#define USHRT_MAX __USHRT_MAX /* max value for an unsigned short */ +#define SHRT_MAX __SHRT_MAX /* max value for a short */ +#define SHRT_MIN __SHRT_MIN /* min value for a short */ + +#define UINT_MAX __UINT_MAX /* max value for an unsigned int */ +#define INT_MAX __INT_MAX /* max value for an int */ +#define INT_MIN __INT_MIN /* min value for an int */ + +#define ULONG_MAX __ULONG_MAX /* max for an unsigned long */ +#define LONG_MAX __LONG_MAX /* max for a long */ +#define LONG_MIN __LONG_MIN /* min for a long */ + +#ifdef __LONG_LONG_SUPPORTED +#define ULLONG_MAX __ULLONG_MAX /* max for an unsigned long long */ +#define LLONG_MAX __LLONG_MAX /* max for a long long */ +#define LLONG_MIN __LLONG_MIN /* min for a long long */ +#endif + +#if __POSIX_VISIBLE || __XSI_VISIBLE +#define SSIZE_MAX __SSIZE_MAX /* max value for an ssize_t */ +#endif + +#if __POSIX_VISIBLE >= 200112 || __XSI_VISIBLE +#define SIZE_T_MAX __SIZE_T_MAX /* max value for a size_t */ + +#define OFF_MAX __OFF_MAX /* max value for an off_t */ +#define OFF_MIN __OFF_MIN /* min value for an off_t */ +#endif + +#if __BSD_VISIBLE +#define GID_MAX UINT_MAX /* max value for a gid_t */ +#define UID_MAX UINT_MAX /* max value for a uid_t */ + +#define UQUAD_MAX (__UQUAD_MAX) /* max value for a uquad_t */ +#define QUAD_MAX (__QUAD_MAX) /* max value for a quad_t */ +#define QUAD_MIN (__QUAD_MIN) /* min value for a quad_t */ +#endif + +#if __XSI_VISIBLE || __POSIX_VISIBLE >= 200809 +#define LONG_BIT __LONG_BIT +#define WORD_BIT __WORD_BIT +#endif + +#if __POSIX_VISIBLE +#define MQ_PRIO_MAX 64 +#endif + +#endif /* !_SYS_LIMITS_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/stdarg.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/stdarg.h new file mode 100644 index 0000000..c315dfc --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/stdarg.h @@ -0,0 +1,75 @@ +/*- + * Copyright (c) 2002 David E. O'Brien. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_STDARG_H_ +#define _MACHINE_STDARG_H_ + +#include +#include + +#ifndef _VA_LIST_DECLARED +#define _VA_LIST_DECLARED +typedef __va_list va_list; +#endif + +#ifdef __GNUCLIKE_BUILTIN_STDARG + +#define va_start(ap, last) \ + __builtin_va_start((ap), (last)) + +#define va_arg(ap, type) \ + __builtin_va_arg((ap), type) + +#define __va_copy(dest, src) \ + __builtin_va_copy((dest), (src)) + +#if __ISO_C_VISIBLE >= 1999 +#define va_copy(dest, src) \ + __va_copy(dest, src) +#endif + +#define va_end(ap) \ + __builtin_va_end(ap) + +#elif defined(lint) +/* Provide a fake implementation for lint's benefit */ +#define __va_size(type) \ + (((sizeof(type) + sizeof(long) - 1) / sizeof(long)) * sizeof(long)) +#define va_start(ap, last) \ + ((ap) = (va_list)&(last) + __va_size(last)) +#define va_arg(ap, type) \ + (*(type *)((ap) += __va_size(type), (ap) - __va_size(type))) +#define va_end(ap) + +#else +#error this file needs to be ported to your compiler +#endif + +#endif /* !_MACHINE_STDARG_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/stdint.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/stdint.h new file mode 100644 index 0000000..aa5ac81 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/stdint.h @@ -0,0 +1,74 @@ +/*- + * Copyright (c) 2001 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS_STDINT_H_ +#define _SYS_STDINT_H_ + +#include +#include + +#include +#include + +typedef __int_least8_t int_least8_t; +typedef __int_least16_t int_least16_t; +typedef __int_least32_t int_least32_t; +typedef __int_least64_t int_least64_t; + +typedef __uint_least8_t uint_least8_t; +typedef __uint_least16_t uint_least16_t; +typedef __uint_least32_t uint_least32_t; +typedef __uint_least64_t uint_least64_t; + +typedef __int_fast8_t int_fast8_t; +typedef __int_fast16_t int_fast16_t; +typedef __int_fast32_t int_fast32_t; +typedef __int_fast64_t int_fast64_t; + +typedef __uint_fast8_t uint_fast8_t; +typedef __uint_fast16_t uint_fast16_t; +typedef __uint_fast32_t uint_fast32_t; +typedef __uint_fast64_t uint_fast64_t; + +#ifndef _INTMAX_T_DECLARED +typedef __intmax_t intmax_t; +#define _INTMAX_T_DECLARED +#endif +#ifndef _UINTMAX_T_DECLARED +typedef __uintmax_t uintmax_t; +#define _UINTMAX_T_DECLARED +#endif + +/* GNU and Darwin define this and people seem to think it's portable */ +#if defined(UINTPTR_MAX) && defined(UINT64_MAX) && (UINTPTR_MAX == UINT64_MAX) +#define __WORDSIZE 64 +#else +#define __WORDSIZE 32 +#endif + +#endif /* !_SYS_STDINT_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/timespec.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/timespec.h new file mode 100644 index 0000000..2505cef --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/timespec.h @@ -0,0 +1,63 @@ +/*- + * Copyright (c) 1982, 1986, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)time.h 8.5 (Berkeley) 5/4/95 + * from: FreeBSD: src/sys/sys/time.h,v 1.43 2000/03/20 14:09:05 phk Exp + * $FreeBSD$ + */ + +#ifndef _SYS_TIMESPEC_H_ +#define _SYS_TIMESPEC_H_ + +#include +#include + +#if __BSD_VISIBLE +#define TIMEVAL_TO_TIMESPEC(tv, ts) \ + do { \ + (ts)->tv_sec = (tv)->tv_sec; \ + (ts)->tv_nsec = (tv)->tv_usec * 1000; \ + } while (0) +#define TIMESPEC_TO_TIMEVAL(tv, ts) \ + do { \ + (tv)->tv_sec = (ts)->tv_sec; \ + (tv)->tv_usec = (ts)->tv_nsec / 1000; \ + } while (0) + +#endif /* __BSD_VISIBLE */ + +/* + * Structure defined by POSIX.1b to be like a itimerval, but with + * timespecs. Used in the timer_*() system calls. + */ +struct itimerspec { + struct timespec it_interval; + struct timespec it_value; +}; + +#endif /* _SYS_TIMESPEC_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/types.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/types.h new file mode 100644 index 0000000..ae2ea33 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/types.h @@ -0,0 +1,245 @@ +/*- + * Copyright (c) 1982, 1986, 1991, 1993, 1994 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)types.h 8.6 (Berkeley) 2/19/95 + * $FreeBSD$ + */ + +#ifndef _SYS_TYPES_H_ +#define _SYS_TYPES_H_ + +#include + +/* Machine type dependent parameters. */ +#include + +#if __BSD_VISIBLE +typedef unsigned char u_char; +typedef unsigned short u_short; +typedef unsigned int u_int; +typedef unsigned long u_long; +#ifndef _KERNEL +typedef unsigned short ushort; /* Sys V compatibility */ +typedef unsigned int uint; /* Sys V compatibility */ +#endif +#endif + +/* + * XXX POSIX sized integrals that should appear only in . + */ +#include + +typedef __uint8_t u_int8_t; /* unsigned integrals (deprecated) */ +typedef __uint16_t u_int16_t; +typedef __uint32_t u_int32_t; +typedef __uint64_t u_int64_t; + +typedef __uint64_t u_quad_t; /* quads (deprecated) */ +typedef __int64_t quad_t; +typedef quad_t *qaddr_t; + +typedef char *caddr_t; /* core address */ +typedef const char *c_caddr_t; /* core address, pointer to const */ + +#ifndef _BLKSIZE_T_DECLARED +typedef __blksize_t blksize_t; +#define _BLKSIZE_T_DECLARED +#endif + +typedef __cpuwhich_t cpuwhich_t; +typedef __cpulevel_t cpulevel_t; +typedef __cpusetid_t cpusetid_t; + +#ifndef _BLKCNT_T_DECLARED +typedef __blkcnt_t blkcnt_t; +#define _BLKCNT_T_DECLARED +#endif + +#ifndef _CLOCK_T_DECLARED +typedef __clock_t clock_t; +#define _CLOCK_T_DECLARED +#endif + +#ifndef _CLOCKID_T_DECLARED +typedef __clockid_t clockid_t; +#define _CLOCKID_T_DECLARED +#endif + +typedef __critical_t critical_t; /* Critical section value */ +typedef __int64_t daddr_t; /* disk address */ + +#ifndef _DEV_T_DECLARED +typedef __dev_t dev_t; /* device number or struct cdev */ +#define _DEV_T_DECLARED +#endif + +#ifndef _FFLAGS_T_DECLARED +typedef __fflags_t fflags_t; /* file flags */ +#define _FFLAGS_T_DECLARED +#endif + +typedef __fixpt_t fixpt_t; /* fixed point number */ + +#ifndef _FSBLKCNT_T_DECLARED /* for statvfs() */ +typedef __fsblkcnt_t fsblkcnt_t; +typedef __fsfilcnt_t fsfilcnt_t; +#define _FSBLKCNT_T_DECLARED +#endif + +#ifndef _GID_T_DECLARED +typedef __gid_t gid_t; /* group id */ +#define _GID_T_DECLARED +#endif + +#ifndef _IN_ADDR_T_DECLARED +typedef __uint32_t in_addr_t; /* base type for internet address */ +#define _IN_ADDR_T_DECLARED +#endif + +#ifndef _IN_PORT_T_DECLARED +typedef __uint16_t in_port_t; +#define _IN_PORT_T_DECLARED +#endif + +#ifndef _ID_T_DECLARED +typedef __id_t id_t; /* can hold a uid_t or pid_t */ +#define _ID_T_DECLARED +#endif + +#ifndef _INO_T_DECLARED +typedef __ino_t ino_t; /* inode number */ +#define _INO_T_DECLARED +#endif + +#ifndef _KEY_T_DECLARED +typedef __key_t key_t; /* IPC key (for Sys V IPC) */ +#define _KEY_T_DECLARED +#endif + +#ifndef _LWPID_T_DECLARED +typedef __lwpid_t lwpid_t; /* Thread ID (a.k.a. LWP) */ +#define _LWPID_T_DECLARED +#endif + +#ifndef _MODE_T_DECLARED +typedef __mode_t mode_t; /* permissions */ +#define _MODE_T_DECLARED +#endif + +#ifndef _ACCMODE_T_DECLARED +typedef __accmode_t accmode_t; /* access permissions */ +#define _ACCMODE_T_DECLARED +#endif + +#ifndef _NLINK_T_DECLARED +typedef __nlink_t nlink_t; /* link count */ +#define _NLINK_T_DECLARED +#endif + +#ifndef _OFF_T_DECLARED +typedef __off_t off_t; /* file offset */ +#define _OFF_T_DECLARED +#endif + +#ifndef _PID_T_DECLARED +typedef __pid_t pid_t; /* process id */ +#define _PID_T_DECLARED +#endif + +typedef __register_t register_t; + +#ifndef _RLIM_T_DECLARED +typedef __rlim_t rlim_t; /* resource limit */ +#define _RLIM_T_DECLARED +#endif + +typedef __int64_t sbintime_t; + +typedef __segsz_t segsz_t; /* segment size (in pages) */ + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#ifndef _SSIZE_T_DECLARED +typedef __ssize_t ssize_t; +#define _SSIZE_T_DECLARED +#endif + +#ifndef _SUSECONDS_T_DECLARED +typedef __suseconds_t suseconds_t; /* microseconds (signed) */ +#define _SUSECONDS_T_DECLARED +#endif + +#ifndef _TIME_T_DECLARED +typedef __time_t time_t; +#define _TIME_T_DECLARED +#endif + +#ifndef _TIMER_T_DECLARED +typedef __timer_t timer_t; +#define _TIMER_T_DECLARED +#endif + +#ifndef _MQD_T_DECLARED +typedef __mqd_t mqd_t; +#define _MQD_T_DECLARED +#endif + +typedef __u_register_t u_register_t; + +#ifndef _UID_T_DECLARED +typedef __uid_t uid_t; /* user id */ +#define _UID_T_DECLARED +#endif + +#ifndef _USECONDS_T_DECLARED +typedef __useconds_t useconds_t; /* microseconds (unsigned) */ +#define _USECONDS_T_DECLARED +#endif + +#ifndef _CAP_RIGHTS_T_DECLARED +#define _CAP_RIGHTS_T_DECLARED +struct cap_rights; + +typedef struct cap_rights cap_rights_t; +#endif + +typedef __vm_offset_t vm_offset_t; +typedef __vm_ooffset_t vm_ooffset_t; +typedef __vm_paddr_t vm_paddr_t; +typedef __vm_pindex_t vm_pindex_t; +typedef __vm_size_t vm_size_t; + +#endif /* !_SYS_TYPES_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/uuid.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/uuid.h new file mode 100644 index 0000000..5c4767b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/sys/uuid.h @@ -0,0 +1,61 @@ +/*- + * Copyright (c) 2002 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#ifndef _SYS_UUID_H_ +#define _SYS_UUID_H_ + +#include + +/* Length of a node address (an IEEE 802 address). */ +#define _UUID_NODE_LEN 6 + +/* + * See also: + * http://www.opengroup.org/dce/info/draft-leach-uuids-guids-01.txt + * http://www.opengroup.org/onlinepubs/009629399/apdxa.htm + * + * A DCE 1.1 compatible source representation of UUIDs. + */ +struct uuid { + uint32_t time_low; + uint16_t time_mid; + uint16_t time_hi_and_version; + uint8_t clock_seq_hi_and_reserved; + uint8_t clock_seq_low; + uint8_t node[_UUID_NODE_LEN]; +}; + +/* XXX namespace pollution? */ +typedef struct uuid uuid_t; + +#endif /* _SYS_UUID_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/time.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/time.h new file mode 100644 index 0000000..08200cf --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/time.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 1989, 1993 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)time.h 8.3 (Berkeley) 1/21/94 + */ + +/* + * $FreeBSD$ + */ + +#ifndef _TIME_H_ +#define _TIME_H_ + +#include +#include +#include + +#if __POSIX_VISIBLE > 0 && __POSIX_VISIBLE < 200112 || __BSD_VISIBLE +/* + * Frequency of the clock ticks reported by times(). Deprecated - use + * sysconf(_SC_CLK_TCK) instead. (Removed in 1003.1-2001.) + */ +#define CLK_TCK 128 +#endif + +/* Frequency of the clock ticks reported by clock(). */ +#define CLOCKS_PER_SEC 128 + +#ifndef _CLOCK_T_DECLARED +typedef __clock_t clock_t; +#define _CLOCK_T_DECLARED +#endif + +#ifndef _TIME_T_DECLARED +typedef __time_t time_t; +#define _TIME_T_DECLARED +#endif + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#if __POSIX_VISIBLE >= 199309 +/* + * New in POSIX 1003.1b-1993. + */ +#ifndef _CLOCKID_T_DECLARED +typedef __clockid_t clockid_t; +#define _CLOCKID_T_DECLARED +#endif + +#ifndef _TIMER_T_DECLARED +typedef __timer_t timer_t; +#define _TIMER_T_DECLARED +#endif + +#include +#endif /* __POSIX_VISIBLE >= 199309 */ + +#if __POSIX_VISIBLE >= 200112 +#ifndef _PID_T_DECLARED +typedef __pid_t pid_t; +#define _PID_T_DECLARED +#endif +#endif + +/* These macros are also in sys/time.h. */ +#if !defined(CLOCK_REALTIME) && __POSIX_VISIBLE >= 200112 +#define CLOCK_REALTIME 0 +#ifdef __BSD_VISIBLE +#define CLOCK_VIRTUAL 1 +#define CLOCK_PROF 2 +#endif +#define CLOCK_MONOTONIC 4 +#define CLOCK_UPTIME 5 /* FreeBSD-specific. */ +#define CLOCK_UPTIME_PRECISE 7 /* FreeBSD-specific. */ +#define CLOCK_UPTIME_FAST 8 /* FreeBSD-specific. */ +#define CLOCK_REALTIME_PRECISE 9 /* FreeBSD-specific. */ +#define CLOCK_REALTIME_FAST 10 /* FreeBSD-specific. */ +#define CLOCK_MONOTONIC_PRECISE 11 /* FreeBSD-specific. */ +#define CLOCK_MONOTONIC_FAST 12 /* FreeBSD-specific. */ +#define CLOCK_SECOND 13 /* FreeBSD-specific. */ +#define CLOCK_THREAD_CPUTIME_ID 14 +#define CLOCK_PROCESS_CPUTIME_ID 15 +#endif /* !defined(CLOCK_REALTIME) && __POSIX_VISIBLE >= 200112 */ + +#if !defined(TIMER_ABSTIME) && __POSIX_VISIBLE >= 200112 +#if __BSD_VISIBLE +#define TIMER_RELTIME 0x0 /* relative timer */ +#endif +#define TIMER_ABSTIME 0x1 /* absolute timer */ +#endif /* !defined(TIMER_ABSTIME) && __POSIX_VISIBLE >= 200112 */ + +struct tm { + int tm_sec; /* seconds after the minute [0-60] */ + int tm_min; /* minutes after the hour [0-59] */ + int tm_hour; /* hours since midnight [0-23] */ + int tm_mday; /* day of the month [1-31] */ + int tm_mon; /* months since January [0-11] */ + int tm_year; /* years since 1900 */ + int tm_wday; /* days since Sunday [0-6] */ + int tm_yday; /* days since January 1 [0-365] */ + int tm_isdst; /* Daylight Savings Time flag */ + long tm_gmtoff; /* offset from UTC in seconds */ + char *tm_zone; /* timezone abbreviation */ +}; + +#if __POSIX_VISIBLE +extern char *tzname[]; +#endif + +__BEGIN_DECLS +char *asctime(const struct tm *); +clock_t clock(void); +char *ctime(const time_t *); +double difftime(time_t, time_t); +/* XXX missing: getdate() */ +struct tm *gmtime(const time_t *); +struct tm *localtime(const time_t *); +time_t mktime(struct tm *); +size_t strftime(char *__restrict, size_t, const char *__restrict, + const struct tm *__restrict); +time_t time(time_t *); +#if __POSIX_VISIBLE >= 200112 +struct sigevent; +int timer_create(clockid_t, struct sigevent *__restrict, timer_t *__restrict); +int timer_delete(timer_t); +int timer_gettime(timer_t, struct itimerspec *); +int timer_getoverrun(timer_t); +int timer_settime(timer_t, int, const struct itimerspec *__restrict, + struct itimerspec *__restrict); +#endif +#if __POSIX_VISIBLE +void tzset(void); +#endif + +#if __POSIX_VISIBLE >= 199309 +int clock_getres(clockid_t, struct timespec *); +int clock_gettime(clockid_t, struct timespec *); +int clock_settime(clockid_t, const struct timespec *); +/* XXX missing: clock_nanosleep() */ +int nanosleep(const struct timespec *, struct timespec *); +#endif /* __POSIX_VISIBLE >= 199309 */ + +#if __POSIX_VISIBLE >= 200112 +int clock_getcpuclockid(pid_t, clockid_t *); +#endif + +#if __POSIX_VISIBLE >= 199506 +char *asctime_r(const struct tm *, char *); +char *ctime_r(const time_t *, char *); +struct tm *gmtime_r(const time_t *, struct tm *); +struct tm *localtime_r(const time_t *, struct tm *); +#endif + +#if __XSI_VISIBLE +char *strptime(const char *__restrict, const char *__restrict, + struct tm *__restrict); +#endif + +#if __BSD_VISIBLE +char *timezone(int, int); /* XXX XSI conflict */ +void tzsetwall(void); +time_t timelocal(struct tm * const); +time_t timegm(struct tm * const); +#endif /* __BSD_VISIBLE */ + +#if __POSIX_VISIBLE >= 200809 || defined(_XLOCALE_H_) +#include +#endif +__END_DECLS + +#endif /* !_TIME_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/xlocale/_strings.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/xlocale/_strings.h new file mode 100644 index 0000000..da1cff3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/xlocale/_strings.h @@ -0,0 +1,48 @@ +/*- + * Copyright (c) 2011, 2012 The FreeBSD Foundation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _LOCALE_T_DEFINED +#define _LOCALE_T_DEFINED +typedef struct _xlocale *locale_t; +#endif + +/* + * This file is included from both strings.h and xlocale.h. We need to expose + * the declarations unconditionally if we are included from xlocale.h, but only + * if we are in POSIX2008 mode if included from string.h. + */ + +#ifndef _XLOCALE_STRINGS1_H +#define _XLOCALE_STRINGS1_H + +/* + * POSIX2008 functions + */ +int strcasecmp_l(const char *, const char *, locale_t); +int strncasecmp_l(const char *, const char *, size_t, locale_t); +#endif /* _XLOCALE_STRINGS1_H */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/xlocale/_time.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/xlocale/_time.h new file mode 100644 index 0000000..6da49a4 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/stdlib/xlocale/_time.h @@ -0,0 +1,58 @@ +/*- + * Copyright (c) 2011, 2012 The FreeBSD Foundation + * All rights reserved. + * + * This software was developed by David Chisnall under sponsorship from + * the FreeBSD Foundation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _LOCALE_T_DEFINED +#define _LOCALE_T_DEFINED +typedef struct _xlocale *locale_t; +#endif + +/* + * This file is included from both locale.h and xlocale.h. We need to expose + * the declarations unconditionally if we are included from xlocale.h, but only + * if we are in POSIX2008 mode if included from locale.h. + */ +#ifndef _XLOCALE_LOCALE1_H +#define _XLOCALE_LOCALE1_H + +size_t strftime_l(char *__restrict, size_t, const char *__restrict, + const struct tm *__restrict, locale_t) __strftimelike(3, 0); + +#endif /* _XLOCALE_LOCALE1_H */ + +#ifdef _XLOCALE_H_ +#ifndef _XLOCALE_LOCALE2_H +#define _XLOCALE_LOCALE2_H + +char *strptime_l(const char *__restrict, const char *__restrict, + struct tm *__restrict, locale_t); + +#endif /* _XLOCALE_LOCALE2_H */ +#endif /* _XLOCALE_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/utils.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/utils.h new file mode 100644 index 0000000..a234e3c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/utils.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __UTILS_H__ +#define __UTILS_H__ + +/* Compute the number of elements in the given array */ +#define ARRAY_SIZE(a) \ + (sizeof(a) / sizeof((a)[0])) + +#define IS_POWER_OF_TWO(x) \ + (((x) & ((x) - 1)) == 0) + +#define SIZE_FROM_LOG2_WORDS(n) (4 << (n)) + +/* + * The round_up() macro rounds up a value to the given boundary in a + * type-agnostic yet type-safe manner. The boundary must be a power of two. + * In other words, it computes the smallest multiple of boundary which is + * greater than or equal to value. + * + * round_down() is similar but rounds the value down instead. + */ +#define round_boundary(value, boundary) \ + ((__typeof__(value))((boundary) - 1)) + +#define round_up(value, boundary) \ + ((((value) - 1) | round_boundary(value, boundary)) + 1) + +#define round_down(value, boundary) \ + ((value) & ~round_boundary(value, boundary)) + +/* + * Evaluates to 1 if (ptr + inc) overflows, 0 otherwise. + * Both arguments must be unsigned pointer values (i.e. uintptr_t). + */ +#define check_uptr_overflow(ptr, inc) \ + (((ptr) > UINTPTR_MAX - (inc)) ? 1 : 0) + +#endif /* __UTILS_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/xlat_tables.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/xlat_tables.h new file mode 100644 index 0000000..0e9800a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/lib/xlat_tables.h @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __XLAT_TABLES_H__ +#define __XLAT_TABLES_H__ + +/* Miscellaneous MMU related constants */ +#define NUM_2MB_IN_GB (1 << 9) +#define NUM_4K_IN_2MB (1 << 9) +#define NUM_GB_IN_4GB (1 << 2) + +#define TWO_MB_SHIFT 21 +#define ONE_GB_SHIFT 30 +#define FOUR_KB_SHIFT 12 + +#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) +#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) +#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) + +#define INVALID_DESC 0x0 +#define BLOCK_DESC 0x1 /* Table levels 0-2 */ +#define TABLE_DESC 0x3 /* Table levels 0-2 */ +#define PAGE_DESC 0x3 /* Table level 3 */ + +#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT +#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT +#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT + +#define XN (1ull << 2) +#define PXN (1ull << 1) +#define CONT_HINT (1ull << 0) + +#define UPPER_ATTRS(x) (x & 0x7) << 52 +#define NON_GLOBAL (1 << 9) +#define ACCESS_FLAG (1 << 8) +#define NSH (0x0 << 6) +#define OSH (0x2 << 6) +#define ISH (0x3 << 6) + +#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT +#define PAGE_SIZE (1 << PAGE_SIZE_SHIFT) +#define PAGE_SIZE_MASK (PAGE_SIZE - 1) +#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0) + +#define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */ +#define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT) + +#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT +#define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT) + +#ifdef AARCH32 +#define XLAT_TABLE_LEVEL_MIN 1 +#else +#define XLAT_TABLE_LEVEL_MIN 0 +#endif /* AARCH32 */ + +#define XLAT_TABLE_LEVEL_MAX 3 + +/* Values for number of entries in each MMU translation table */ +#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) +#define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT) +#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1) + +/* Values to convert a memory address to an index into a translation table */ +#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT +#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) +#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) +#define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) + +/* + * AP[1] bit is ignored by hardware and is + * treated as if it is One in EL2/EL3 + */ +#define AP_RO (0x1 << 5) +#define AP_RW (0x0 << 5) + +#define NS (0x1 << 3) +#define ATTR_NON_CACHEABLE_INDEX 0x2 +#define ATTR_DEVICE_INDEX 0x1 +#define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0 +#define LOWER_ATTRS(x) (((x) & 0xfff) << 2) +#define ATTR_NON_CACHEABLE (0x44) +#define ATTR_DEVICE (0x4) +#define ATTR_IWBWA_OWBWA_NTR (0xff) +#define MAIR_ATTR_SET(attr, index) (attr << (index << 3)) + +/* + * Flags to override default values used to program system registers while + * enabling the MMU. + */ +#define DISABLE_DCACHE (1 << 0) + +#ifndef __ASSEMBLY__ +#include +#include + +/* Helper macro to define entries for mmap_region_t. It creates + * identity mappings for each region. + */ +#define MAP_REGION_FLAT(adr, sz, attr) MAP_REGION(adr, adr, sz, attr) + +/* Helper macro to define entries for mmap_region_t. It allows to + * re-map address mappings from 'pa' to 'va' for each region. + */ +#define MAP_REGION(pa, va, sz, attr) {(pa), (va), (sz), (attr)} + +/* + * Shifts and masks to access fields of an mmap_attr_t + */ +#define MT_TYPE_MASK 0x7 +#define MT_TYPE(_attr) ((_attr) & MT_TYPE_MASK) +/* Access permissions (RO/RW) */ +#define MT_PERM_SHIFT 3 +/* Security state (SECURE/NS) */ +#define MT_SEC_SHIFT 4 +/* Access permissions for instruction execution (EXECUTE/EXECUTE_NEVER) */ +#define MT_EXECUTE_SHIFT 5 + +/* + * Memory mapping attributes + */ +typedef enum { + /* + * Memory types supported. + * These are organised so that, going down the list, the memory types + * are getting weaker; conversely going up the list the memory types are + * getting stronger. + */ + MT_DEVICE, + MT_NON_CACHEABLE, + MT_MEMORY, + /* Values up to 7 are reserved to add new memory types in the future */ + + MT_RO = 0 << MT_PERM_SHIFT, + MT_RW = 1 << MT_PERM_SHIFT, + + MT_SECURE = 0 << MT_SEC_SHIFT, + MT_NS = 1 << MT_SEC_SHIFT, + + /* + * Access permissions for instruction execution are only relevant for + * normal read-only memory, i.e. MT_MEMORY | MT_RO. They are ignored + * (and potentially overridden) otherwise: + * - Device memory is always marked as execute-never. + * - Read-write normal memory is always marked as execute-never. + */ + MT_EXECUTE = 0 << MT_EXECUTE_SHIFT, + MT_EXECUTE_NEVER = 1 << MT_EXECUTE_SHIFT, +} mmap_attr_t; + +#define MT_CODE (MT_MEMORY | MT_RO | MT_EXECUTE) +#define MT_RO_DATA (MT_MEMORY | MT_RO | MT_EXECUTE_NEVER) + +/* + * Structure for specifying a single region of memory. + */ +typedef struct mmap_region { + unsigned long long base_pa; + uintptr_t base_va; + size_t size; + mmap_attr_t attr; +} mmap_region_t; + +/* Generic translation table APIs */ +void init_xlat_tables(void); +void mmap_add_region(unsigned long long base_pa, uintptr_t base_va, + size_t size, unsigned int attr); +void mmap_add(const mmap_region_t *mm); + +#ifdef AARCH32 +/* AArch32 specific translation table API */ +void enable_mmu_secure(uint32_t flags); +#else +/* AArch64 specific translation table APIs */ +void enable_mmu_el1(unsigned int flags); +void enable_mmu_el3(unsigned int flags); +#endif /* AARCH32 */ + +#endif /*__ASSEMBLY__*/ +#endif /* __XLAT_TABLES_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/board_arm_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/board_arm_def.h new file mode 100644 index 0000000..ad82923 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/board_arm_def.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __BOARD_ARM_DEF_H__ +#define __BOARD_ARM_DEF_H__ + +#include + + +/* + * Required platform porting definitions common to all ARM + * development platforms + */ + +/* Size of cacheable stacks */ +#if IMAGE_BL1 +#if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE 0x1000 +#else +# define PLATFORM_STACK_SIZE 0x440 +#endif +#elif IMAGE_BL2 +# if TRUSTED_BOARD_BOOT +# define PLATFORM_STACK_SIZE 0x1000 +# else +# define PLATFORM_STACK_SIZE 0x400 +# endif +#elif IMAGE_BL2U +# define PLATFORM_STACK_SIZE 0x200 +#elif IMAGE_BL31 +# define PLATFORM_STACK_SIZE 0x400 +#elif IMAGE_BL32 +# define PLATFORM_STACK_SIZE 0x440 +#endif + +/* + * The constants below are not optimised for memory usage. Platforms that wish + * to optimise these constants should set `ARM_BOARD_OPTIMISE_MEM` to 1 and + * provide there own values. + */ +#if !ARM_BOARD_OPTIMISE_MEM +/* + * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the + * plat_arm_mmap array defined for each BL stage. + * + * Provide relatively optimised values for the runtime images (BL31 and BL32). + * Optimisation is less important for the other, transient boot images so a + * common, maximum value is used across these images. + */ +#if IMAGE_BL31 || IMAGE_BL32 +# define PLAT_ARM_MMAP_ENTRIES 6 +# define MAX_XLAT_TABLES 4 +#else +# define PLAT_ARM_MMAP_ENTRIES 10 +# define MAX_XLAT_TABLES 5 +#endif + +/* + * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size + * plus a little space for growth. + */ +#define PLAT_ARM_MAX_BL1_RW_SIZE 0xA000 + +/* + * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a + * little space for growth. + */ +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL2_SIZE 0x1D000 +#else +# define PLAT_ARM_MAX_BL2_SIZE 0xF000 +#endif + +/* + * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a + * little space for growth. + */ +#define PLAT_ARM_MAX_BL31_SIZE 0x1D000 + +#endif /* ARM_BOARD_OPTIMISE_MEM */ + +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00040000 /* 256 KB */ + +#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE +#define PLAT_ARM_FIP_MAX_SIZE V2M_FLASH0_SIZE + +#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE +#define PLAT_ARM_NVM_SIZE V2M_FLASH0_SIZE + + +#endif /* __BOARD_ARM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/board_arm_oid.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/board_arm_oid.h new file mode 100644 index 0000000..cbf2290 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/board_arm_oid.h @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BOARD_ARM_OID_H__ +#define __BOARD_ARM_OID_H__ + +/* + * The following is a list of OID values defined and reserved by ARM, which + * are used to define the extension fields of the certificate structure, as + * defined in the Trusted Board Boot Requirements (TBBR) specification, + * ARM DEN0006C-1. + * + * Non-ARM platform owners that wish to align with the TBBR should define + * constants with the same name in their own platform port(s), using their + * own OIDs obtained from the ITU-T. + */ + + +/* TrustedFirmwareNVCounter - Non-volatile counter extension */ +#define TRUSTED_FW_NVCOUNTER_OID "1.3.6.1.4.1.4128.2100.1" +/* NonTrustedFirmwareNVCounter - Non-volatile counter extension */ +#define NON_TRUSTED_FW_NVCOUNTER_OID "1.3.6.1.4.1.4128.2100.2" + + +/* + * Non-Trusted Firmware Updater Certificate + */ + +/* APFirmwareUpdaterConfigHash - BL2U */ +#define AP_FWU_CFG_HASH_OID "1.3.6.1.4.1.4128.2100.101" +/* SCPFirmwareUpdaterConfigHash - SCP_BL2U */ +#define SCP_FWU_CFG_HASH_OID "1.3.6.1.4.1.4128.2100.102" +/* FirmwareUpdaterHash - NS_BL2U */ +#define FWU_HASH_OID "1.3.6.1.4.1.4128.2100.103" +/* TrustedWatchdogRefreshTime */ +#define TRUSTED_WATCHDOG_TIME_OID "1.3.6.1.4.1.4128.2100.104" + + +/* + * Trusted Boot Firmware Certificate + */ + +/* TrustedBootFirmwareHash - BL2 */ +#define TRUSTED_BOOT_FW_HASH_OID "1.3.6.1.4.1.4128.2100.201" + + +/* + * Trusted Key Certificate + */ + +/* PrimaryDebugCertificatePK */ +#define PRIMARY_DEBUG_PK_OID "1.3.6.1.4.1.4128.2100.301" +/* TrustedWorldPK */ +#define TRUSTED_WORLD_PK_OID "1.3.6.1.4.1.4128.2100.302" +/* NonTrustedWorldPK */ +#define NON_TRUSTED_WORLD_PK_OID "1.3.6.1.4.1.4128.2100.303" + + +/* + * Trusted Debug Certificate + */ + +/* DebugScenario */ +#define TRUSTED_DEBUG_SCENARIO_OID "1.3.6.1.4.1.4128.2100.401" +/* SoC Specific */ +#define TRUSTED_DEBUG_SOC_SPEC_OID "1.3.6.1.4.1.4128.2100.402" +/* SecondaryDebugCertPK */ +#define SECONDARY_DEBUG_PK_OID "1.3.6.1.4.1.4128.2100.403" + + +/* + * SoC Firmware Key Certificate + */ + +/* SoCFirmwareContentCertPK */ +#define SOC_FW_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.501" + + +/* + * SoC Firmware Content Certificate + */ + +/* APRomPatchHash - BL1_PATCH */ +#define APROM_PATCH_HASH_OID "1.3.6.1.4.1.4128.2100.601" +/* SoCConfigHash */ +#define SOC_CONFIG_HASH_OID "1.3.6.1.4.1.4128.2100.602" +/* SoCAPFirmwareHash - BL31 */ +#define SOC_AP_FW_HASH_OID "1.3.6.1.4.1.4128.2100.603" + + +/* + * SCP Firmware Key Certificate + */ + +/* SCPFirmwareContentCertPK */ +#define SCP_FW_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.701" + + +/* + * SCP Firmware Content Certificate + */ + +/* SCPFirmwareHash - SCP_BL2 */ +#define SCP_FW_HASH_OID "1.3.6.1.4.1.4128.2100.801" +/* SCPRomPatchHash - SCP_BL1_PATCH */ +#define SCP_ROM_PATCH_HASH_OID "1.3.6.1.4.1.4128.2100.802" + + +/* + * Trusted OS Firmware Key Certificate + */ + +/* TrustedOSFirmwareContentCertPK */ +#define TRUSTED_OS_FW_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.901" + + +/* + * Trusted OS Firmware Content Certificate + */ + +/* TrustedOSFirmwareHash - BL32 */ +#define TRUSTED_OS_FW_HASH_OID "1.3.6.1.4.1.4128.2100.1001" + + +/* + * Non-Trusted Firmware Key Certificate + */ + +/* NonTrustedFirmwareContentCertPK */ +#define NON_TRUSTED_FW_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2100.1101" + + +/* + * Non-Trusted Firmware Content Certificate + */ + +/* NonTrustedWorldBootloaderHash - BL33 */ +#define NON_TRUSTED_WORLD_BOOTLOADER_HASH_OID "1.3.6.1.4.1.4128.2100.1201" + +#endif /* __BOARD_ARM_OID_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/board_css_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/board_css_def.h new file mode 100644 index 0000000..975f1fc --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/board_css_def.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __BOARD_CSS_DEF_H__ +#define __BOARD_CSS_DEF_H__ + +#include +#include +#include + +/* + * Definitions common to all ARM CSS-based development platforms + */ + +/* Platform ID address */ +#define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0 + +/* Platform ID related accessors */ +#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f +#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0 +#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00 +#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8 +#define BOARD_CSS_PLAT_TYPE_RTL 0x00 +#define BOARD_CSS_PLAT_TYPE_FPGA 0x01 +#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02 +#define BOARD_CSS_PLAT_TYPE_FVP 0x03 + +#ifndef __ASSEMBLY__ + +#include + +#define BOARD_CSS_GET_PLAT_TYPE(addr) \ + ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ + >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) + +#endif /* __ASSEMBLY__ */ + + +/* + * Required platform porting definitions common to all ARM CSS-based + * development platforms + */ + +#define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x180000000) + +/* UART related constants */ +#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ + +#define PLAT_ARM_BL31_RUN_UART_BASE SOC_CSS_UART1_BASE +#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ + +#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ + +#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE +#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ + + +#endif /* __BOARD_CSS_DEF_H__ */ + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/drivers/norflash.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/drivers/norflash.h new file mode 100644 index 0000000..0bf35a5 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/drivers/norflash.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __NORFLASH_H_ +#define __NORFLASH_H_ + +#include + +/* First bus cycle */ +#define NOR_CMD_READ_ARRAY 0xFF +#define NOR_CMD_READ_ID_CODE 0x90 +#define NOR_CMD_READ_QUERY 0x98 +#define NOR_CMD_READ_STATUS_REG 0x70 +#define NOR_CMD_CLEAR_STATUS_REG 0x50 +#define NOR_CMD_WRITE_TO_BUFFER 0xE8 +#define NOR_CMD_WORD_PROGRAM 0x40 +#define NOR_CMD_BLOCK_ERASE 0x20 +#define NOR_CMD_LOCK_UNLOCK 0x60 + +/* Second bus cycle */ +#define NOR_LOCK_BLOCK 0x01 +#define NOR_UNLOCK_BLOCK 0xD0 + +/* Status register bits */ +#define NOR_DWS (1 << 7) +#define NOR_ESS (1 << 6) +#define NOR_ES (1 << 5) +#define NOR_PS (1 << 4) +#define NOR_VPPS (1 << 3) +#define NOR_PSS (1 << 2) +#define NOR_BLS (1 << 1) +#define NOR_BWS (1 << 0) + +/* Public API */ +void nor_send_cmd(uintptr_t base_addr, unsigned long cmd); +int nor_word_program(uintptr_t base_addr, unsigned long data); +void nor_lock(uintptr_t base_addr); +void nor_unlock(uintptr_t base_addr); + +#endif /* __NORFLASH_H_ */ + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/v2m_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/v2m_def.h new file mode 100644 index 0000000..7cee4e8 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/board/common/v2m_def.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __V2M_DEF_H__ +#define __V2M_DEF_H__ + +#include + + +/* V2M motherboard system registers & offsets */ +#define V2M_SYSREGS_BASE 0x1c010000 +#define V2M_SYS_ID 0x0 +#define V2M_SYS_SWITCH 0x4 +#define V2M_SYS_LED 0x8 +#define V2M_SYS_NVFLAGS 0x38 +#define V2M_SYS_NVFLAGSSET 0x38 +#define V2M_SYS_NVFLAGSCLR 0x3c +#define V2M_SYS_CFGDATA 0xa0 +#define V2M_SYS_CFGCTRL 0xa4 +#define V2M_SYS_CFGSTATUS 0xa8 + +#define V2M_CFGCTRL_START (1 << 31) +#define V2M_CFGCTRL_RW (1 << 30) +#define V2M_CFGCTRL_FUNC_SHIFT 20 +#define V2M_CFGCTRL_FUNC(fn) (fn << V2M_CFGCTRL_FUNC_SHIFT) +#define V2M_FUNC_CLK_GEN 0x01 +#define V2M_FUNC_TEMP 0x04 +#define V2M_FUNC_DB_RESET 0x05 +#define V2M_FUNC_SCC_CFG 0x06 +#define V2M_FUNC_SHUTDOWN 0x08 +#define V2M_FUNC_REBOOT 0x09 + +/* + * V2M sysled bit definitions. The values written to this + * register are defined in arch.h & runtime_svc.h. Only + * used by the primary cpu to diagnose any cold boot issues. + * + * SYS_LED[0] - Security state (S=0/NS=1) + * SYS_LED[2:1] - Exception Level (EL3-EL0) + * SYS_LED[7:3] - Exception Class (Sync/Async & origin) + * + */ +#define V2M_SYS_LED_SS_SHIFT 0x0 +#define V2M_SYS_LED_EL_SHIFT 0x1 +#define V2M_SYS_LED_EC_SHIFT 0x3 + +#define V2M_SYS_LED_SS_MASK 0x1 +#define V2M_SYS_LED_EL_MASK 0x3 +#define V2M_SYS_LED_EC_MASK 0x1f + +/* V2M sysid register bits */ +#define V2M_SYS_ID_REV_SHIFT 28 +#define V2M_SYS_ID_HBI_SHIFT 16 +#define V2M_SYS_ID_BLD_SHIFT 12 +#define V2M_SYS_ID_ARCH_SHIFT 8 +#define V2M_SYS_ID_FPGA_SHIFT 0 + +#define V2M_SYS_ID_REV_MASK 0xf +#define V2M_SYS_ID_HBI_MASK 0xfff +#define V2M_SYS_ID_BLD_MASK 0xf +#define V2M_SYS_ID_ARCH_MASK 0xf +#define V2M_SYS_ID_FPGA_MASK 0xff + +#define V2M_SYS_ID_BLD_LENGTH 4 + + +/* NOR Flash */ +#define V2M_FLASH0_BASE 0x08000000 +#define V2M_FLASH0_SIZE 0x04000000 + +#define V2M_IOFPGA_BASE 0x1c000000 +#define V2M_IOFPGA_SIZE 0x03000000 + +/* PL011 UART related constants */ +#define V2M_IOFPGA_UART0_BASE 0x1c090000 +#define V2M_IOFPGA_UART1_BASE 0x1c0a0000 +#define V2M_IOFPGA_UART2_BASE 0x1c0b0000 +#define V2M_IOFPGA_UART3_BASE 0x1c0c0000 + +#define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000 +#define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000 +#define V2M_IOFPGA_UART2_CLK_IN_HZ 24000000 +#define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000 + +/* SP804 timer related constants */ +#define V2M_SP804_TIMER0_BASE 0x1C110000 +#define V2M_SP804_TIMER1_BASE 0x1C120000 + +/* SP810 controller */ +#define V2M_SP810_BASE 0x1c020000 +#define V2M_SP810_CTRL_TIM0_SEL (1 << 15) +#define V2M_SP810_CTRL_TIM1_SEL (1 << 17) +#define V2M_SP810_CTRL_TIM2_SEL (1 << 19) +#define V2M_SP810_CTRL_TIM3_SEL (1 << 21) + +/* + * The flash can be mapped either as read-only or read-write. + * + * If it is read-write then it should also be mapped as device memory because + * NOR flash programming involves sending a fixed, ordered sequence of commands. + * + * If it is read-only then it should also be mapped as: + * - Normal memory, because reading from NOR flash is transparent, it is like + * reading from RAM. + * - Non-executable by default. If some parts of the flash need to be executable + * then platform code is responsible for re-mapping the appropriate portion + * of it as executable. + */ +#define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\ + V2M_FLASH0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ + V2M_FLASH0_SIZE, \ + MT_RO_DATA | MT_SECURE) + +#define V2M_MAP_IOFPGA MAP_REGION_FLAT(V2M_IOFPGA_BASE,\ + V2M_IOFPGA_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + + + +#endif /* __V2M_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/aarch64/arm_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/aarch64/arm_macros.S new file mode 100644 index 0000000..3b19a7d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/aarch64/arm_macros.S @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ARM_MACROS_S__ +#define __ARM_MACROS_S__ + +#include +#include +#include +#include + +.section .rodata.gic_reg_name, "aS" +/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" + +/* Applicable only to GICv3 with SRE enabled */ +icc_regs: + .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" + +/* Registers common to both GICv2 and GICv3 */ +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ + " Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below utility macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL31 on ARM standard platforms. + * Expects: GICD base in x16, GICC base in x17 + * Clobbers: x0 - x10, sp + * --------------------------------------------- + */ + .macro arm_print_gic_regs + /* Check for GICv3 system register access */ + mrs x7, id_aa64pfr0_el1 + ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH + cmp x7, #1 + b.ne print_gicv2 + + /* Check for SRE enable */ + mrs x8, ICC_SRE_EL3 + tst x8, #ICC_SRE_SRE_BIT + b.eq print_gicv2 + + /* Load the icc reg list to x6 */ + adr x6, icc_regs + /* Load the icc regs to gp regs used by str_in_crash_buf_print */ + mrs x8, ICC_HPPIR0_EL1 + mrs x9, ICC_HPPIR1_EL1 + mrs x10, ICC_CTLR_EL3 + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + b print_gic_common + +print_gicv2: + /* Load the gicc reg list to x6 */ + adr x6, gicc_regs + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + +print_gic_common: + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + .endm + +#endif /* __ARM_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/aarch64/cci_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/aarch64/cci_macros.S new file mode 100644 index 0000000..902fb15 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/aarch64/cci_macros.S @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __CCI_MACROS_S__ +#define __CCI_MACROS_S__ + +#include +#include + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* ------------------------------------------------ + * The below required platform porting macro prints + * out relevant interconnect registers whenever an + * unhandled exception is taken in BL31. + * Clobbers: x0 - x9, sp + * ------------------------------------------------ + */ + .macro print_cci_regs + adr x6, cci_iface_regs + /* Store in x7 the base address of the first interface */ + mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX)) + ldr w8, [x7, #SNOOP_CTRL_REG] + /* Store in x7 the base address of the second interface */ + mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX)) + ldr w9, [x7, #SNOOP_CTRL_REG] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + .endm + +#endif /* __CCI_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/arm_config.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/arm_config.h new file mode 100644 index 0000000..0380849 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/arm_config.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ARM_CONFIG_H__ +#define __ARM_CONFIG_H__ + +#include + +enum arm_config_flags { + /* Whether Base memory map is in use */ + ARM_CONFIG_BASE_MMAP = 0x1, + /* Whether interconnect should be enabled */ + ARM_CONFIG_HAS_INTERCONNECT = 0x2, + /* Whether TZC should be configured */ + ARM_CONFIG_HAS_TZC = 0x4 +}; + +typedef struct arm_config { + unsigned long flags; +} arm_config_t; + + +/* If used, arm_config must be defined and populated in the platform port */ +extern arm_config_t arm_config; + +static inline const arm_config_t *get_arm_config(void) +{ + return &arm_config; +} + + +#endif /* __ARM_CONFIG_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/arm_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/arm_def.h new file mode 100644 index 0000000..4a4dfd4 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/arm_def.h @@ -0,0 +1,355 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ARM_DEF_H__ +#define __ARM_DEF_H__ + +#include +#include +#include +#include +#include + + +/****************************************************************************** + * Definitions common to all ARM standard platforms + *****************************************************************************/ + +/* Special value used to verify platform parameters from BL2 to BL31 */ +#define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + +#define ARM_SYSTEM_COUNT 1 + +#define ARM_CACHE_WRITEBACK_SHIFT 6 + +/* + * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The + * power levels have a 1:1 mapping with the MPIDR affinity levels. + */ +#define ARM_PWR_LVL0 MPIDR_AFFLVL0 +#define ARM_PWR_LVL1 MPIDR_AFFLVL1 +#define ARM_PWR_LVL2 MPIDR_AFFLVL2 + +/* + * Macros for local power states in ARM platforms encoded by State-ID field + * within the power-state parameter. + */ +/* Local power state for power domains in Run state. */ +#define ARM_LOCAL_STATE_RUN 0 +/* Local power state for retention. Valid only for CPU power domains */ +#define ARM_LOCAL_STATE_RET 1 +/* Local power state for OFF/power-down. Valid for CPU and cluster power + domains */ +#define ARM_LOCAL_STATE_OFF 2 + +/* Memory location options for TSP */ +#define ARM_TRUSTED_SRAM_ID 0 +#define ARM_TRUSTED_DRAM_ID 1 +#define ARM_DRAM_ID 2 + +/* The first 4KB of Trusted SRAM are used as shared memory */ +#define ARM_TRUSTED_SRAM_BASE 0x04000000 +#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE +#define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ + +/* The remaining Trusted SRAM is used to load the BL images */ +#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ + ARM_SHARED_RAM_SIZE) +#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ + ARM_SHARED_RAM_SIZE) + +/* + * The top 16MB of DRAM1 is configured as secure access only using the TZC + * - SCP TZC DRAM: If present, DRAM reserved for SCP use + * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use + */ +#define ARM_TZC_DRAM1_SIZE MAKE_ULL(0x01000000) + +#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - \ + ARM_SCP_TZC_DRAM1_SIZE) +#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE +#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ + ARM_SCP_TZC_DRAM1_SIZE - 1) + +#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - \ + ARM_TZC_DRAM1_SIZE) +#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ + ARM_SCP_TZC_DRAM1_SIZE) +#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE - 1) + + +#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE +#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ + ARM_TZC_DRAM1_SIZE) +#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ + ARM_NS_DRAM1_SIZE - 1) + +#define ARM_DRAM1_BASE MAKE_ULL(0x80000000) +#define ARM_DRAM1_SIZE MAKE_ULL(0x80000000) +#define ARM_DRAM1_END (ARM_DRAM1_BASE + \ + ARM_DRAM1_SIZE - 1) + +#define ARM_DRAM2_BASE MAKE_ULL(0x880000000) +#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE +#define ARM_DRAM2_END (ARM_DRAM2_BASE + \ + ARM_DRAM2_SIZE - 1) + +#define ARM_IRQ_SEC_PHY_TIMER 29 + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ + ARM_IRQ_SEC_SGI_1, \ + ARM_IRQ_SEC_SGI_2, \ + ARM_IRQ_SEC_SGI_3, \ + ARM_IRQ_SEC_SGI_4, \ + ARM_IRQ_SEC_SGI_5, \ + ARM_IRQ_SEC_SGI_7 + +#define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ + ARM_IRQ_SEC_SGI_6 + +#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ + ARM_SHARED_RAM_BASE, \ + ARM_SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ + ARM_NS_DRAM1_BASE, \ + ARM_NS_DRAM1_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ + TSP_SEC_MEM_BASE, \ + TSP_SEC_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#if ARM_BL31_IN_DRAM +#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ + BL31_BASE, \ + PLAT_ARM_MAX_BL31_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif + +/* + * The number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#if USE_COHERENT_MEM +#define ARM_BL_REGIONS 3 +#else +#define ARM_BL_REGIONS 2 +#endif + +#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ + ARM_BL_REGIONS) + +/* Memory mapped Generic timer interfaces */ +#define ARM_SYS_CNTCTL_BASE 0x2a430000 +#define ARM_SYS_CNTREAD_BASE 0x2a800000 +#define ARM_SYS_TIMCTL_BASE 0x2a810000 + +#define ARM_CONSOLE_BAUDRATE 115200 + +/* Trusted Watchdog constants */ +#define ARM_SP805_TWDG_BASE 0x2a490000 +#define ARM_SP805_TWDG_CLK_HZ 32768 +/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 + * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ +#define ARM_TWDG_TIMEOUT_SEC 128 +#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ + ARM_TWDG_TIMEOUT_SEC) + +/****************************************************************************** + * Required platform porting definitions common to all ARM standard platforms + *****************************************************************************/ + +#define ADDR_SPACE_SIZE (1ull << 32) + +/* + * This macro defines the deepest retention state possible. A higher state + * id will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) + + +/******************************************************************************* + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + ******************************************************************************/ +#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE +#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ + + PLAT_ARM_TRUSTED_ROM_SIZE) +/* + * Put BL1 RW at the top of the Trusted SRAM. + */ +#define BL1_RW_BASE (ARM_BL_RAM_BASE + \ + ARM_BL_RAM_SIZE - \ + PLAT_ARM_MAX_BL1_RW_SIZE) +#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) + +/******************************************************************************* + * BL2 specific defines. + ******************************************************************************/ +#if ARM_BL31_IN_DRAM +/* + * BL31 is loaded in the DRAM. + * Put BL2 just below BL1. + */ +#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) +#define BL2_LIMIT BL1_RW_BASE +#else +/* + * Put BL2 just below BL31. + */ +#define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE) +#define BL2_LIMIT BL31_BASE +#endif + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +#if ARM_BL31_IN_DRAM +/* + * Put BL31 at the bottom of TZC secured DRAM + */ +#define BL31_BASE ARM_AP_TZC_DRAM1_BASE +#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ + PLAT_ARM_MAX_BL31_SIZE) +#else +/* + * Put BL31 at the top of the Trusted SRAM. + */ +#define BL31_BASE (ARM_BL_RAM_BASE + \ + ARM_BL_RAM_SIZE - \ + PLAT_ARM_MAX_BL31_SIZE) +#define BL31_PROGBITS_LIMIT BL1_RW_BASE +#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) +#endif + +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ +/* + * On ARM standard platforms, the TSP can execute from Trusted SRAM, + * Trusted DRAM (if available) or the DRAM region secured by the TrustZone + * controller. + */ +#if ARM_BL31_IN_DRAM +# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ + PLAT_ARM_MAX_BL31_SIZE) +# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ + PLAT_ARM_MAX_BL31_SIZE) +# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ + PLAT_ARM_MAX_BL31_SIZE) +# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE) +#elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID +# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE +# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE +# define TSP_PROGBITS_LIMIT BL2_BASE +# define BL32_BASE ARM_BL_RAM_BASE +# define BL32_LIMIT BL31_BASE +#elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID +# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE +# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE +# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE +# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ + + (1 << 21)) +#elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID +# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE +# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE +# define BL32_BASE ARM_AP_TZC_DRAM1_BASE +# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ + ARM_AP_TZC_DRAM1_SIZE) +#else +# error "Unsupported ARM_TSP_RAM_LOCATION_ID value" +#endif + +/* BL32 is mandatory in AArch32 */ +#ifndef AARCH32 +#ifdef SPD_none +#undef BL32_BASE +#endif /* SPD_none */ +#endif + +/******************************************************************************* + * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. + ******************************************************************************/ +#define BL2U_BASE BL2_BASE +#if ARM_BL31_IN_DRAM +#define BL2U_LIMIT BL1_RW_BASE +#else +#define BL2U_LIMIT BL31_BASE +#endif +#define NS_BL2U_BASE ARM_NS_DRAM1_BASE +#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000) + +/* + * ID of the secure physical generic timer interrupt used by the TSP. + */ +#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER + + +/* + * One cache line needed for bakery locks on ARM platforms + */ +#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) + + +#endif /* __ARM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/plat_arm.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/plat_arm.h new file mode 100644 index 0000000..29fcffe --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/common/plat_arm.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __PLAT_ARM_H__ +#define __PLAT_ARM_H__ + +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct bl31_params; +struct meminfo; +struct image_info; + +#define ARM_CASSERT_MMAP \ + CASSERT((ARRAY_SIZE(plat_arm_mmap) + ARM_BL_REGIONS) \ + <= MAX_MMAP_REGIONS, \ + assert_max_mmap_regions); + +/* + * Utility functions common to ARM standard platforms + */ +void arm_setup_page_tables(uintptr_t total_base, + size_t total_size, + uintptr_t code_start, + uintptr_t code_limit, + uintptr_t rodata_start, + uintptr_t rodata_limit +#if USE_COHERENT_MEM + , uintptr_t coh_start, + uintptr_t coh_limit +#endif +); + +#if IMAGE_BL31 +/* + * Use this macro to instantiate lock before it is used in below + * arm_lock_xxx() macros + */ +#define ARM_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_lock); + +/* + * These are wrapper macros to the Coherent Memory Bakery Lock API. + */ +#define arm_lock_init() bakery_lock_init(&arm_lock) +#define arm_lock_get() bakery_lock_get(&arm_lock) +#define arm_lock_release() bakery_lock_release(&arm_lock) + +#else + +/* + * Empty macros for all other BL stages other than BL31 + */ +#define ARM_INSTANTIATE_LOCK +#define arm_lock_init() +#define arm_lock_get() +#define arm_lock_release() + +#endif /* IMAGE_BL31 */ + +#if ARM_RECOM_STATE_ID_ENC +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define ARM_LOCAL_PSTATE_WIDTH 4 +#define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) + +/* Macros to construct the composite power state */ + +/* Make composite power state parameter till power level 0 */ +#if PSCI_EXTENDED_STATE_ID + +#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) +#else +#define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) +#endif /* __PSCI_EXTENDED_STATE_ID__ */ + +/* Make composite power state parameter till power level 1 */ +#define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ + arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) + +/* Make composite power state parameter till power level 2 */ +#define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ + arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) + +#endif /* __ARM_RECOM_STATE_ID_ENC__ */ + + +/* IO storage utility functions */ +void arm_io_setup(void); + +/* Security utility functions */ +void arm_tzc400_setup(void); +struct tzc_dmc500_driver_data; +void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data); + +/* Systimer utility function */ +void arm_configure_sys_timer(void); + +/* PM utility functions */ +int arm_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state); +int arm_validate_ns_entrypoint(uintptr_t entrypoint); +void arm_system_pwr_domain_resume(void); +void arm_program_trusted_mailbox(uintptr_t address); + +/* Topology utility function */ +int arm_check_mpidr(u_register_t mpidr); + +/* BL1 utility functions */ +void arm_bl1_early_platform_setup(void); +void arm_bl1_platform_setup(void); +void arm_bl1_plat_arch_setup(void); + +/* BL2 utility functions */ +void arm_bl2_early_platform_setup(struct meminfo *mem_layout); +void arm_bl2_platform_setup(void); +void arm_bl2_plat_arch_setup(void); +uint32_t arm_get_spsr_for_bl32_entry(void); +uint32_t arm_get_spsr_for_bl33_entry(void); + +/* BL2U utility functions */ +void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, + void *plat_info); +void arm_bl2u_platform_setup(void); +void arm_bl2u_plat_arch_setup(void); + +/* BL31 utility functions */ +#if LOAD_IMAGE_V2 +void arm_bl31_early_platform_setup(void *from_bl2, + void *plat_params_from_bl2); +#else +void arm_bl31_early_platform_setup(struct bl31_params *from_bl2, + void *plat_params_from_bl2); +#endif /* LOAD_IMAGE_V2 */ +void arm_bl31_platform_setup(void); +void arm_bl31_plat_runtime_setup(void); +void arm_bl31_plat_arch_setup(void); + +/* TSP utility functions */ +void arm_tsp_early_platform_setup(void); + +/* SP_MIN utility functions */ +void arm_sp_min_early_platform_setup(void *from_bl2, + void *plat_params_from_bl2); + +/* FIP TOC validity check */ +int arm_io_is_toc_valid(void); + +/* + * Mandatory functions required in ARM standard platforms + */ +unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); +void plat_arm_gic_driver_init(void); +void plat_arm_gic_init(void); +void plat_arm_gic_cpuif_enable(void); +void plat_arm_gic_cpuif_disable(void); +void plat_arm_gic_pcpu_init(void); +void plat_arm_security_setup(void); +void plat_arm_pwrc_setup(void); +void plat_arm_interconnect_init(void); +void plat_arm_interconnect_enter_coherency(void); +void plat_arm_interconnect_exit_coherency(void); + +#if LOAD_IMAGE_V2 +/* + * This function is called after loading SCP_BL2 image and it is used to perform + * any platform-specific actions required to handle the SCP firmware. + */ +int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); +#endif + +/* + * Optional functions required in ARM standard platforms + */ +void plat_arm_io_setup(void); +int plat_arm_get_alt_image_source( + unsigned int image_id, + uintptr_t *dev_handle, + uintptr_t *image_spec); +unsigned int plat_arm_calc_core_pos(u_register_t mpidr); +const mmap_region_t *plat_arm_get_mmap(void); + +#endif /* __PLAT_ARM_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/css/common/aarch64/css_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/css/common/aarch64/css_macros.S new file mode 100644 index 0000000..518867b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/css/common/aarch64/css_macros.S @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __CSS_MACROS_S__ +#define __CSS_MACROS_S__ + +#include +#include + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC registers whenever an + * unhandled exception is taken in BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro css_print_gic_regs + mov_imm x16, PLAT_ARM_GICD_BASE + mov_imm x17, PLAT_ARM_GICC_BASE + arm_print_gic_regs + .endm + + +#endif /* __CSS_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/css/common/css_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/css/common/css_def.h new file mode 100644 index 0000000..173de1b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/css/common/css_def.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CSS_DEF_H__ +#define __CSS_DEF_H__ + +#include +#include + +/************************************************************************* + * Definitions common to all ARM Compute SubSystems (CSS) + *************************************************************************/ +#define NSROM_BASE 0x1f000000 +#define NSROM_SIZE 0x00001000 + +/* Following covers CSS Peripherals excluding NSROM and NSRAM */ +#define CSS_DEVICE_BASE 0x20000000 +#define CSS_DEVICE_SIZE 0x0e000000 + +#define NSRAM_BASE 0x2e000000 +#define NSRAM_SIZE 0x00008000 + +/* System Security Control Registers */ +#define SSC_REG_BASE 0x2a420000 +#define SSC_GPRETN (SSC_REG_BASE + 0x030) + +/* The slave_bootsecure controls access to GPU, DMC and CS. */ +#define CSS_NIC400_SLAVE_BOOTSECURE 8 + +/* Interrupt handling constants */ +#define CSS_IRQ_MHU 69 +#define CSS_IRQ_GPU_SMMU_0 71 +#define CSS_IRQ_TZC 80 +#define CSS_IRQ_TZ_WDOG 86 +#define CSS_IRQ_SEC_SYS_TIMER 91 + +/* + * Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a + * GICv2 system or mode, the interrupts will be treated as Group 0 interrupts. + */ +#define CSS_G1S_IRQS CSS_IRQ_MHU, \ + CSS_IRQ_GPU_SMMU_0, \ + CSS_IRQ_TZC, \ + CSS_IRQ_TZ_WDOG, \ + CSS_IRQ_SEC_SYS_TIMER + +/* + * SCP <=> AP boot configuration + * + * The SCP/AP boot configuration is a 32-bit word located at a known offset from + * the start of the Trusted SRAM. + * + * Note that the value stored at this address is only valid at boot time, before + * the SCP_BL2 image is transferred to SCP. + */ +#define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE + +#define CSS_MAP_DEVICE MAP_REGION_FLAT( \ + CSS_DEVICE_BASE, \ + CSS_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/* Platform ID address */ +#define SSC_VERSION_OFFSET 0x040 + +#define SSC_VERSION_CONFIG_SHIFT 28 +#define SSC_VERSION_MAJOR_REV_SHIFT 24 +#define SSC_VERSION_MINOR_REV_SHIFT 20 +#define SSC_VERSION_DESIGNER_ID_SHIFT 12 +#define SSC_VERSION_PART_NUM_SHIFT 0x0 +#define SSC_VERSION_CONFIG_MASK 0xf +#define SSC_VERSION_MAJOR_REV_MASK 0xf +#define SSC_VERSION_MINOR_REV_MASK 0xf +#define SSC_VERSION_DESIGNER_ID_MASK 0xff +#define SSC_VERSION_PART_NUM_MASK 0xfff + +#ifndef __ASSEMBLY__ + +/* SSC_VERSION related accessors */ + +/* Returns the part number of the platform */ +#define GET_SSC_VERSION_PART_NUM(val) \ + (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ + SSC_VERSION_PART_NUM_MASK) + +/* Returns the configuration number of the platform */ +#define GET_SSC_VERSION_CONFIG(val) \ + (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ + SSC_VERSION_CONFIG_MASK) + +#endif /* __ASSEMBLY__ */ + +/************************************************************************* + * Required platform porting definitions common to all + * ARM Compute SubSystems (CSS) + ************************************************************************/ + +/* + * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there + * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE). + * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load + * an SCP_BL2/SCP_BL2U image. + */ +#if CSS_LOAD_SCP_IMAGES +/* + * Load address of SCP_BL2 in CSS platform ports + * SCP_BL2 is loaded to the same place as BL31. Once SCP_BL2 is transferred to the + * SCP, it is discarded and BL31 is loaded over the top. + */ +#define SCP_BL2_BASE BL31_BASE + +#define SCP_BL2U_BASE BL31_BASE +#endif /* CSS_LOAD_SCP_IMAGES */ + +/* Load address of Non-Secure Image for CSS platform ports */ +#define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000 + +/* TZC related constants */ +#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL + +/* Trusted mailbox base address common to all CSS */ +#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE + +/* + * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP + * command + */ +#define CSS_CLUSTER_PWR_STATE_ON 0 +#define CSS_CLUSTER_PWR_STATE_OFF 3 + +#define CSS_CPU_PWR_STATE_ON 1 +#define CSS_CPU_PWR_STATE_OFF 0 +#define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1) + +#endif /* __CSS_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/css/common/css_pm.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/css/common/css_pm.h new file mode 100644 index 0000000..4a6ca81 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/css/common/css_pm.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CSS_PM_H__ +#define __CSS_PM_H__ + +#include +#include +#include + +int css_pwr_domain_on(u_register_t mpidr); +void css_pwr_domain_on_finish(const psci_power_state_t *target_state); +void css_pwr_domain_off(const psci_power_state_t *target_state); +void css_pwr_domain_suspend(const psci_power_state_t *target_state); +void css_pwr_domain_suspend_finish( + const psci_power_state_t *target_state); +void __dead2 css_system_off(void); +void __dead2 css_system_reset(void); +void css_cpu_standby(plat_local_state_t cpu_state); +void css_get_sys_suspend_power_state(psci_power_state_t *req_state); +int css_node_hw_state(u_register_t mpidr, unsigned int power_level); + +#endif /* __CSS_PM_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/soc/common/soc_css.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/soc/common/soc_css.h new file mode 100644 index 0000000..5f97cde --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/soc/common/soc_css.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SOC_CSS_H__ +#define __SOC_CSS_H__ + +/* + * Utility functions for ARM CSS SoCs + */ +void soc_css_init_nic400(void); +void soc_css_init_pcie(void); + +static inline void soc_css_security_setup(void) +{ + soc_css_init_nic400(); + soc_css_init_pcie(); +} + + +#endif /* __SOC_CSS_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/soc/common/soc_css_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/soc/common/soc_css_def.h new file mode 100644 index 0000000..f1396a6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/arm/soc/common/soc_css_def.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SOC_CSS_DEF_H__ +#define __SOC_CSS_DEF_H__ + +#include +#include + + +/* + * Definitions common to all ARM CSS SoCs + */ + +/* Following covers ARM CSS SoC Peripherals and PCIe expansion area */ +#define SOC_CSS_DEVICE_BASE 0x40000000 +#define SOC_CSS_DEVICE_SIZE 0x40000000 +#define SOC_CSS_PCIE_CONTROL_BASE 0x7ff20000 + +/* PL011 UART related constants */ +#define SOC_CSS_UART0_BASE 0x7ff80000 +#define SOC_CSS_UART1_BASE 0x7ff70000 + +#define SOC_CSS_UART0_CLK_IN_HZ 7273800 +#define SOC_CSS_UART1_CLK_IN_HZ 7273800 + +/* SoC NIC-400 Global Programmers View (GPV) */ +#define SOC_CSS_NIC400_BASE 0x7fd00000 + +#define SOC_CSS_NIC400_USB_EHCI 0 +#define SOC_CSS_NIC400_TLX_MASTER 1 +#define SOC_CSS_NIC400_USB_OHCI 2 +#define SOC_CSS_NIC400_PL354_SMC 3 +/* + * The apb4_bridge controls access to: + * - the PCIe configuration registers + * - the MMU units for USB, HDLCD and DMA + */ +#define SOC_CSS_NIC400_APB4_BRIDGE 4 + +/* Non-volatile counters */ +#define SOC_TRUSTED_NVCTR_BASE 0x7fe70000 +#define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000) +#define TFW_NVCTR_SIZE 4 +#define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) +#define NTFW_CTR_SIZE 4 + +/* Keys */ +#define SOC_KEYS_BASE 0x7fe80000 +#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) +#define TZ_PUB_KEY_HASH_SIZE 32 +#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) +#define HU_KEY_SIZE 16 +#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) +#define END_KEY_SIZE 32 + +#define SOC_CSS_MAP_DEVICE MAP_REGION_FLAT( \ + SOC_CSS_DEVICE_BASE, \ + SOC_CSS_DEVICE_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + + +/* + * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. + */ +#define SOC_CSS_NIC400_BOOTSEC_BRIDGE 5 +#define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 (1 << 12) + +/* + * Required platform porting definitions common to all ARM CSS SoCs + */ + +/* 2MB used for SCP DDR retraining */ +#define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x00200000) + + +#endif /* __SOC_CSS_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/common/common_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/common/common_def.h new file mode 100644 index 0000000..e2c4513 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/common/common_def.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __COMMON_DEF_H__ +#define __COMMON_DEF_H__ + +#include +#include + +/****************************************************************************** + * Required platform porting definitions that are expected to be common to + * all platforms + *****************************************************************************/ + +/* + * Platform binary types for linking + */ +#ifdef AARCH32 +#define PLATFORM_LINKER_FORMAT "elf32-littlearm" +#define PLATFORM_LINKER_ARCH arm +#else +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 +#endif /* AARCH32 */ + +/* + * Generic platform constants + */ +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" + +/* + * Some of the platform porting definitions use the 'ull' suffix in order to + * avoid subtle integer overflow errors due to implicit integer type promotion + * when working with 32-bit values. + * + * The TSP linker script includes some of these definitions to define the BL32 + * memory map, but the GNU LD does not support the 'ull' suffix, causing the + * build process to fail. To solve this problem, the auxiliary macro MAKE_ULL(x) + * will add the 'ull' suffix only when the macro __LINKER__ is not defined + * (__LINKER__ is defined in the command line to preprocess the linker script). + * Constants in the linker script will not have the 'ull' suffix, but this is + * not a problem since the linker evaluates all constant expressions to 64 bit + * (assuming the target architecture is 64 bit). + */ +#ifndef __LINKER__ + #define MAKE_ULL(x) x##ull +#else + #define MAKE_ULL(x) x +#endif + +#if LOAD_IMAGE_V2 +#define BL2_IMAGE_DESC { \ + .image_id = BL2_IMAGE_ID, \ + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \ + VERSION_2, image_info_t, 0), \ + .image_info.image_base = BL2_BASE, \ + .image_info.image_max_size = BL2_LIMIT - BL2_BASE,\ + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \ + VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),\ + .ep_info.pc = BL2_BASE, \ +} +#else /* LOAD_IMAGE_V2 */ +#define BL2_IMAGE_DESC { \ + .image_id = BL2_IMAGE_ID, \ + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, \ + VERSION_1, image_info_t, 0), \ + .image_info.image_base = BL2_BASE, \ + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, \ + VERSION_1, entry_point_info_t, SECURE | EXECUTABLE),\ + .ep_info.pc = BL2_BASE, \ +} +#endif /* LOAD_IMAGE_V2 */ + +/* + * The following constants identify the extents of the code & read-only data + * regions. These addresses are used by the MMU setup code and therefore they + * must be page-aligned. + * + * When the code and read-only data are mapped as a single atomic section + * (i.e. when SEPARATE_CODE_AND_RODATA=0) then we treat the whole section as + * code by specifying the read-only data section as empty. + * + * BL1 is different than the other images in the sense that its read-write data + * originally lives in Trusted ROM and needs to be relocated in Trusted SRAM at + * run-time. Therefore, the read-write data in ROM can be mapped with the same + * memory attributes as the read-only data region. For this reason, BL1 uses + * different macros. + * + * Note that BL1_ROM_END is not necessarily aligned on a page boundary as it + * just points to the end of BL1's actual content in Trusted ROM. Therefore it + * needs to be rounded up to the next page size in order to map the whole last + * page of it with the right memory attributes. + */ +#if SEPARATE_CODE_AND_RODATA +#define BL_CODE_BASE (unsigned long)(&__TEXT_START__) +#define BL_CODE_LIMIT (unsigned long)(&__TEXT_END__) +#define BL_RO_DATA_BASE (unsigned long)(&__RODATA_START__) +#define BL_RO_DATA_LIMIT (unsigned long)(&__RODATA_END__) + +#define BL1_CODE_LIMIT BL_CODE_LIMIT +#define BL1_RO_DATA_BASE (unsigned long)(&__RODATA_START__) +#define BL1_RO_DATA_LIMIT round_up(BL1_ROM_END, PAGE_SIZE) +#else +#define BL_CODE_BASE (unsigned long)(&__RO_START__) +#define BL_CODE_LIMIT (unsigned long)(&__RO_END__) +#define BL_RO_DATA_BASE 0 +#define BL_RO_DATA_LIMIT 0 + +#define BL1_CODE_LIMIT round_up(BL1_ROM_END, PAGE_SIZE) +#define BL1_RO_DATA_BASE 0 +#define BL1_RO_DATA_LIMIT 0 +#endif /* SEPARATE_CODE_AND_RODATA */ + +#endif /* __COMMON_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/common/platform.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/common/platform.h new file mode 100644 index 0000000..a0794fe --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/plat/common/platform.h @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_H__ +#define __PLATFORM_H__ + +#include +#include +#include + + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct meminfo; +struct image_info; +struct entry_point_info; +struct bl31_params; +struct image_desc; +struct bl_load_info; +struct bl_params; + +/******************************************************************************* + * plat_get_rotpk_info() flags + ******************************************************************************/ +#define ROTPK_IS_HASH (1 << 0) +/* Flag used to skip verification of the certificate ROTPK while the platform + ROTPK is not deployed */ +#define ROTPK_NOT_DEPLOYED (1 << 1) + +/******************************************************************************* + * Function declarations + ******************************************************************************/ +/******************************************************************************* + * Mandatory common functions + ******************************************************************************/ +unsigned long long plat_get_syscnt_freq(void) __deprecated; +unsigned int plat_get_syscnt_freq2(void); + +int plat_get_image_source(unsigned int image_id, + uintptr_t *dev_handle, + uintptr_t *image_spec); +#if IMAGE_BL2 +uintptr_t plat_get_bl31_bl32_image_entrypoint(int32_t content_cert_id); +#endif /* IMAGE_BL2 */ +uintptr_t plat_get_ns_image_entrypoint(void); +unsigned int plat_my_core_pos(void); +int plat_core_pos_by_mpidr(u_register_t mpidr); + +/******************************************************************************* + * Mandatory interrupt management functions + ******************************************************************************/ +uint32_t plat_ic_get_pending_interrupt_id(void); +uint32_t plat_ic_get_pending_interrupt_type(void); +uint32_t plat_ic_acknowledge_interrupt(void); +uint32_t plat_ic_get_interrupt_type(uint32_t id); +void plat_ic_end_of_interrupt(uint32_t id); +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state); + +/******************************************************************************* + * Optional common functions (may be overridden) + ******************************************************************************/ +uintptr_t plat_get_my_stack(void); +void plat_report_exception(unsigned int exception_type); +int plat_crash_console_init(void); +int plat_crash_console_putc(int c); +void plat_error_handler(int err) __dead2; +void plat_panic_handler(void) __dead2; + +/******************************************************************************* + * Mandatory BL1 functions + ******************************************************************************/ +void bl1_early_platform_setup(void); +void bl1_plat_arch_setup(void); +void bl1_platform_setup(void); +struct meminfo *bl1_plat_sec_mem_layout(void); + +/* + * The following function is mandatory when the + * firmware update feature is used. + */ +int bl1_plat_mem_check(uintptr_t mem_base, unsigned int mem_size, + unsigned int flags); + +/******************************************************************************* + * Optional BL1 functions (may be overridden) + ******************************************************************************/ +void bl1_init_bl2_mem_layout(const struct meminfo *bl1_mem_layout, + struct meminfo *bl2_mem_layout); + +/* + * The following functions are used for image loading process in BL1. + */ +void bl1_plat_set_ep_info(unsigned int image_id, + struct entry_point_info *ep_info); +/* + * The following functions are mandatory when firmware update + * feature is used and optional otherwise. + */ +unsigned int bl1_plat_get_next_image_id(void); +struct image_desc *bl1_plat_get_image_desc(unsigned int image_id); + +/* + * The following functions are used by firmware update + * feature and may optionally be overridden. + */ +__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved); + + +/******************************************************************************* + * Mandatory BL2 functions + ******************************************************************************/ +void bl2_early_platform_setup(struct meminfo *mem_layout); +void bl2_plat_arch_setup(void); +void bl2_platform_setup(void); +struct meminfo *bl2_plat_sec_mem_layout(void); + +#if LOAD_IMAGE_V2 +/* + * This function can be used by the platforms to update/use image + * information for given `image_id`. + */ +int bl2_plat_handle_post_image_load(unsigned int image_id); + +#else /* LOAD_IMAGE_V2 */ + +/* + * This function returns a pointer to the shared memory that the platform has + * kept aside to pass trusted firmware related information that BL31 + * could need + */ +struct bl31_params *bl2_plat_get_bl31_params(void); + +/* + * This function returns a pointer to the shared memory that the platform + * has kept to point to entry point information of BL31 to BL2 + */ +struct entry_point_info *bl2_plat_get_bl31_ep_info(void); + +/* + * This function flushes to main memory all the params that are + * passed to BL31 + */ +void bl2_plat_flush_bl31_params(void); + +/* + * The next 2 functions allow the platform to change the entrypoint information + * for the mandatory 3rd level BL images, BL31 and BL33. This is done after + * BL2 has loaded those images into memory but before BL31 is executed. + */ +void bl2_plat_set_bl31_ep_info(struct image_info *image, + struct entry_point_info *ep); + +void bl2_plat_set_bl33_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* Gets the memory layout for BL33 */ +void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); + +/******************************************************************************* + * Conditionally mandatory BL2 functions: must be implemented if SCP_BL2 image + * is supported + ******************************************************************************/ +/* Gets the memory layout for SCP_BL2 */ +void bl2_plat_get_scp_bl2_meminfo(struct meminfo *mem_info); + +/* + * This function is called after loading SCP_BL2 image and it is used to perform + * any platform-specific actions required to handle the SCP firmware. + */ +int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info); + +/******************************************************************************* + * Conditionally mandatory BL2 functions: must be implemented if BL32 image + * is supported + ******************************************************************************/ +void bl2_plat_set_bl32_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* Gets the memory layout for BL32 */ +void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); + +#endif /* LOAD_IMAGE_V2 */ + +/******************************************************************************* + * Optional BL2 functions (may be overridden) + ******************************************************************************/ + +/******************************************************************************* + * Mandatory BL2U functions. + ******************************************************************************/ +void bl2u_early_platform_setup(struct meminfo *mem_layout, + void *plat_info); +void bl2u_plat_arch_setup(void); +void bl2u_platform_setup(void); + +/******************************************************************************* + * Conditionally mandatory BL2U functions for CSS platforms. + ******************************************************************************/ +/* + * This function is used to perform any platform-specific actions required to + * handle the BL2U_SCP firmware. + */ +int bl2u_plat_handle_scp_bl2u(void); + +/******************************************************************************* + * Mandatory BL31 functions + ******************************************************************************/ +#if LOAD_IMAGE_V2 +void bl31_early_platform_setup(void *from_bl2, + void *plat_params_from_bl2); +#else +void bl31_early_platform_setup(struct bl31_params *from_bl2, + void *plat_params_from_bl2); +#endif +void bl31_plat_arch_setup(void); +void bl31_platform_setup(void); +void bl31_plat_runtime_setup(void); +struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type); +uint32_t bl31_plat_mmu_pa_chk(uint32_t pa_flg, uintptr_t chk_va, uint64_t chk_pa); +uint32_t bl31_plat_cpu_migrate_info(u_register_t *resident_cpu); +int32_t bl31_plat_denied_cpu_off_chk(void); + +/******************************************************************************* + * Mandatory PSCI functions (BL31) + ******************************************************************************/ +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const struct plat_psci_ops **); +const unsigned char *plat_get_power_domain_tree_desc(void); + +/******************************************************************************* + * Optional PSCI functions (BL31). + ******************************************************************************/ +plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, + const plat_local_state_t *states, + unsigned int ncpu); + +/******************************************************************************* + * Optional BL31 functions (may be overridden) + ******************************************************************************/ +void bl31_plat_enable_mmu(uint32_t flags); + +/******************************************************************************* + * Optional BL32 functions (may be overridden) + ******************************************************************************/ +void bl32_plat_enable_mmu(uint32_t flags); + +/******************************************************************************* + * Trusted Board Boot functions + ******************************************************************************/ +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags); +int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr); +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr); + +#if LOAD_IMAGE_V2 +/******************************************************************************* + * Mandatory BL image load functions(may be overridden). + ******************************************************************************/ +/* + * This function returns pointer to the list of images that the + * platform has populated to load. + */ +struct bl_load_info *plat_get_bl_image_load_info(void); + +/* + * This function returns a pointer to the shared memory that the + * platform has kept aside to pass trusted firmware related + * information that next BL image could need. + */ +struct bl_params *plat_get_next_bl_params(void); + +/* + * This function flushes to main memory all the params that are + * passed to next image. + */ +void plat_flush_next_bl_params(void); + +#endif /* LOAD_IMAGE_V2 */ + +#if ENABLE_PLAT_COMPAT +/* + * The below declarations are to enable compatibility for the platform ports + * using the old platform interface. + */ + +/******************************************************************************* + * Optional common functions (may be overridden) + ******************************************************************************/ +unsigned int platform_get_core_pos(unsigned long mpidr); + +/******************************************************************************* + * Mandatory PSCI Compatibility functions (BL31) + ******************************************************************************/ +int platform_setup_pm(const plat_pm_ops_t **); + +unsigned int plat_get_aff_count(unsigned int, unsigned long); +unsigned int plat_get_aff_state(unsigned int, unsigned long); +#else +/* + * The below function enable Trusted Firmware components like SPDs which + * haven't migrated to the new platform API to compile on platforms which + * have the compatibility layer disabled. + */ +unsigned int platform_get_core_pos(unsigned long mpidr) __deprecated; + +#endif /* __ENABLE_PLAT_COMPAT__ */ +#endif /* __PLATFORM_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/include/services/std_svc.h b/IPL/SDK/v3m/src/arm-trusted-firmware/include/services/std_svc.h new file mode 100644 index 0000000..38ce8bb --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/include/services/std_svc.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __STD_SVC_H__ +#define __STD_SVC_H__ + +/* SMC function IDs for Standard Service queries */ + +#define ARM_STD_SVC_CALL_COUNT 0x8400ff00 +#define ARM_STD_SVC_UID 0x8400ff01 +/* 0x8400ff02 is reserved */ +#define ARM_STD_SVC_VERSION 0x8400ff03 + +/* ARM Standard Service Calls version numbers */ +#define STD_SVC_VERSION_MAJOR 0x0 +#define STD_SVC_VERSION_MINOR 0x1 + +/* + * Get the ARM Standard Service argument from EL3 Runtime. + * This function must be implemented by EL3 Runtime and the + * `svc_mask` identifies the service. `svc_mask` is a bit + * mask identifying the range of SMC function IDs available + * to the service. + */ +uintptr_t get_arm_std_svc_args(unsigned int svc_mask); + +#endif /* __STD_SVC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch32/cache_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch32/cache_helpers.S new file mode 100644 index 0000000..d0e5cd0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch32/cache_helpers.S @@ -0,0 +1,237 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl flush_dcache_range + .globl clean_dcache_range + .globl inv_dcache_range + .globl dcsw_op_louis + .globl dcsw_op_all + .globl dcsw_op_level1 + .globl dcsw_op_level2 + .globl dcsw_op_level3 + +/* + * This macro can be used for implementing various data cache operations `op` + */ +.macro do_dcache_maintenance_by_mva op, coproc, opc1, CRn, CRm, opc2 + dcache_line_size r2, r3 + add r1, r0, r1 + sub r3, r2, #1 + bic r0, r0, r3 +loop_\op: + stcopr r0, \coproc, \opc1, \CRn, \CRm, \opc2 + add r0, r0, r2 + cmp r0, r1 + blo loop_\op + dsb sy + bx lr +.endm + + /* ------------------------------------------ + * Clean+Invalidate from base address till + * size. 'r0' = addr, 'r1' = size + * ------------------------------------------ + */ +func flush_dcache_range + do_dcache_maintenance_by_mva cimvac, DCCIMVAC +endfunc flush_dcache_range + + /* ------------------------------------------ + * Clean from base address till size. + * 'r0' = addr, 'r1' = size + * ------------------------------------------ + */ +func clean_dcache_range + do_dcache_maintenance_by_mva cmvac, DCCMVAC +endfunc clean_dcache_range + + /* ------------------------------------------ + * Invalidate from base address till + * size. 'r0' = addr, 'r1' = size + * ------------------------------------------ + */ +func inv_dcache_range + do_dcache_maintenance_by_mva imvac, DCIMVAC +endfunc inv_dcache_range + + /* ---------------------------------------------------------------- + * Data cache operations by set/way to the level specified + * + * The main function, do_dcsw_op requires: + * r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW), + * as defined in arch.h + * r1: The cache level to begin operation from + * r2: clidr_el1 + * r3: The last cache level to operate on + * and will carry out the operation on each data cache from level 0 + * to the level in r3 in sequence + * + * The dcsw_op macro sets up the r2 and r3 parameters based on + * clidr_el1 cache information before invoking the main function + * ---------------------------------------------------------------- + */ + + .macro dcsw_op shift, fw, ls + ldcopr r2, CLIDR + ubfx r3, r2, \shift, \fw + lsl r3, r3, \ls + mov r1, #0 + b do_dcsw_op + .endm + +func do_dcsw_op + push {r4-r12,lr} + adr r11, dcsw_loop_table // compute cache op based on the operation type + add r6, r11, r0, lsl #3 // cache op is 2x32-bit instructions +loop1: + add r10, r1, r1, LSR #1 // Work out 3x current cache level + mov r12, r2, LSR r10 // extract cache type bits from clidr + and r12, r12, #7 // mask the bits for current cache only + cmp r12, #2 // see what cache we have at this level + blt level_done // no cache or only instruction cache at this level + + stcopr r1, CSSELR // select current cache level in csselr + isb // isb to sych the new cssr&csidr + ldcopr r12, CCSIDR // read the new ccsidr + and r10, r12, #7 // extract the length of the cache lines + add r10, r10, #4 // add 4 (r10 = line length offset) + ubfx r4, r12, #3, #10 // r4 = maximum way number (right aligned) + clz r5, r4 // r5 = the bit position of the way size increment + mov r9, r4 // r9 working copy of the aligned max way number + +loop2: + ubfx r7, r12, #13, #15 // r7 = max set number (right aligned) + +loop3: + orr r0, r1, r9, LSL r5 // factor in the way number and cache level into r0 + orr r0, r0, r7, LSL r10 // factor in the set number + + blx r6 + subs r7, r7, #1 // decrement the set number + bge loop3 + subs r9, r9, #1 // decrement the way number + bge loop2 +level_done: + add r1, r1, #2 // increment the cache number + cmp r3, r1 + dsb sy // ensure completion of previous cache maintenance instruction + bgt loop1 + + mov r6, #0 + stcopr r6, CSSELR //select cache level 0 in csselr + dsb sy + isb + pop {r4-r12,pc} + +dcsw_loop_table: + stcopr r0, DCISW + bx lr + stcopr r0, DCCISW + bx lr + stcopr r0, DCCSW + bx lr + +endfunc do_dcsw_op + + /* --------------------------------------------------------------- + * Data cache operations by set/way till PoU. + * + * The function requires : + * r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW), + * as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_louis + dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT +endfunc dcsw_op_louis + + /* --------------------------------------------------------------- + * Data cache operations by set/way till PoC. + * + * The function requires : + * r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW), + * as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_all + dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT +endfunc dcsw_op_all + + + /* --------------------------------------------------------------- + * Helper macro for data cache operations by set/way for the + * level specified + * --------------------------------------------------------------- + */ + .macro dcsw_op_level level + ldcopr r2, CLIDR + mov r3, \level + sub r1, r3, #2 + b do_dcsw_op + .endm + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 1 cache + * + * The main function, do_dcsw_op requires: + * r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW), + * as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level1 + dcsw_op_level #(1 << LEVEL_SHIFT) +endfunc dcsw_op_level1 + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 2 cache + * + * The main function, do_dcsw_op requires: + * r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW), + * as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level2 + dcsw_op_level #(2 << LEVEL_SHIFT) +endfunc dcsw_op_level2 + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 3 cache + * + * The main function, do_dcsw_op requires: + * r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW), + * as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level3 + dcsw_op_level #(3 << LEVEL_SHIFT) +endfunc dcsw_op_level3 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch32/misc_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch32/misc_helpers.S new file mode 100644 index 0000000..bf4084a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch32/misc_helpers.S @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .globl smc + .globl zeromem + .globl memcpy4 + .globl disable_mmu_icache_secure + .globl disable_mmu_secure + +func smc + /* + * For AArch32 only r0-r3 will be in the registers; + * rest r4-r6 will be pushed on to the stack. So here, we'll + * have to load them from the stack to registers r4-r6 explicitly. + * Clobbers: r4-r6 + */ + ldm sp, {r4, r5, r6} + smc #0 +endfunc smc + +/* ----------------------------------------------------------------------- + * void zeromem(void *mem, unsigned int length); + * + * Initialise a memory region to 0. + * The memory address and length must be 4-byte aligned. + * ----------------------------------------------------------------------- + */ +func zeromem +#if ASM_ASSERTION + tst r0, #0x3 + ASM_ASSERT(eq) + tst r1, #0x3 + ASM_ASSERT(eq) +#endif + add r2, r0, r1 + mov r1, #0 +z_loop: + cmp r2, r0 + beq z_end + str r1, [r0], #4 + b z_loop +z_end: + bx lr +endfunc zeromem + +/* -------------------------------------------------------------------------- + * void memcpy4(void *dest, const void *src, unsigned int length) + * + * Copy length bytes from memory area src to memory area dest. + * The memory areas should not overlap. + * Destination and source addresses must be 4-byte aligned. + * -------------------------------------------------------------------------- + */ +func memcpy4 +#if ASM_ASSERTION + orr r3, r0, r1 + tst r3, #0x3 + ASM_ASSERT(eq) +#endif +/* copy 4 bytes at a time */ +m_loop4: + cmp r2, #4 + blt m_loop1 + ldr r3, [r1], #4 + str r3, [r0], #4 + sub r2, r2, #4 + b m_loop4 +/* copy byte per byte */ +m_loop1: + cmp r2,#0 + beq m_end + ldrb r3, [r1], #1 + strb r3, [r0], #1 + subs r2, r2, #1 + bne m_loop1 +m_end: + bx lr +endfunc memcpy4 + +/* --------------------------------------------------------------------------- + * Disable the MMU in Secure State + * --------------------------------------------------------------------------- + */ + +func disable_mmu_secure + mov r1, #(SCTLR_M_BIT | SCTLR_C_BIT) +do_disable_mmu: + ldcopr r0, SCTLR + bic r0, r0, r1 + stcopr r0, SCTLR + isb // ensure MMU is off + dsb sy + bx lr +endfunc disable_mmu_secure + + +func disable_mmu_icache_secure + ldr r1, =(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) + b do_disable_mmu +endfunc disable_mmu_icache_secure diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch64/cache_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch64/cache_helpers.S new file mode 100644 index 0000000..476b906 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch64/cache_helpers.S @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl flush_dcache_range + .globl clean_dcache_range + .globl inv_dcache_range + .globl dcsw_op_louis + .globl dcsw_op_all + .globl dcsw_op_level1 + .globl dcsw_op_level2 + .globl dcsw_op_level3 + +/* + * This macro can be used for implementing various data cache operations `op` + */ +.macro do_dcache_maintenance_by_mva op + dcache_line_size x2, x3 + add x1, x0, x1 + sub x3, x2, #1 + bic x0, x0, x3 +loop_\op: + dc \op, x0 + add x0, x0, x2 + cmp x0, x1 + b.lo loop_\op + dsb sy + ret +.endm + /* ------------------------------------------ + * Clean+Invalidate from base address till + * size. 'x0' = addr, 'x1' = size + * ------------------------------------------ + */ +func flush_dcache_range + do_dcache_maintenance_by_mva civac +endfunc flush_dcache_range + + /* ------------------------------------------ + * Clean from base address till size. + * 'x0' = addr, 'x1' = size + * ------------------------------------------ + */ +func clean_dcache_range + do_dcache_maintenance_by_mva cvac +endfunc clean_dcache_range + + /* ------------------------------------------ + * Invalidate from base address till + * size. 'x0' = addr, 'x1' = size + * ------------------------------------------ + */ +func inv_dcache_range + do_dcache_maintenance_by_mva ivac +endfunc inv_dcache_range + + + /* --------------------------------------------------------------- + * Data cache operations by set/way to the level specified + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * x3: The last cache level to operate on + * x9: clidr_el1 + * x10: The cache level to begin operation from + * and will carry out the operation on each data cache from level 0 + * to the level in x3 in sequence + * + * The dcsw_op macro sets up the x3 and x9 parameters based on + * clidr_el1 cache information before invoking the main function + * --------------------------------------------------------------- + */ + + .macro dcsw_op shift, fw, ls + mrs x9, clidr_el1 + ubfx x3, x9, \shift, \fw + lsl x3, x3, \ls + mov x10, xzr + b do_dcsw_op + .endm + +func do_dcsw_op + cbz x3, exit + adr x14, dcsw_loop_table // compute inner loop address + add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions + mov x0, x9 + mov w8, #1 +loop1: + add x2, x10, x10, lsr #1 // work out 3x current cache level + lsr x1, x0, x2 // extract cache type bits from clidr + and x1, x1, #7 // mask the bits for current cache only + cmp x1, #2 // see what cache we have at this level + b.lt level_done // nothing to do if no cache or icache + + msr csselr_el1, x10 // select current cache level in csselr + isb // isb to sych the new cssr&csidr + mrs x1, ccsidr_el1 // read the new ccsidr + and x2, x1, #7 // extract the length of the cache lines + add x2, x2, #4 // add 4 (line length offset) + ubfx x4, x1, #3, #10 // maximum way number + clz w5, w4 // bit position of way size increment + lsl w9, w4, w5 // w9 = aligned max way number + lsl w16, w8, w5 // w16 = way number loop decrement + orr w9, w10, w9 // w9 = combine way and cache number + ubfx w6, w1, #13, #15 // w6 = max set number + lsl w17, w8, w2 // w17 = set number loop decrement + dsb sy // barrier before we start this level + br x14 // jump to DC operation specific loop + + .macro dcsw_loop _op +loop2_\_op: + lsl w7, w6, w2 // w7 = aligned max set number + +loop3_\_op: + orr w11, w9, w7 // combine cache, way and set number + dc \_op, x11 + subs w7, w7, w17 // decrement set number + b.ge loop3_\_op + + subs x9, x9, x16 // decrement way number + b.ge loop2_\_op + + b level_done + .endm + +level_done: + add x10, x10, #2 // increment cache number + cmp x3, x10 + b.gt loop1 + msr csselr_el1, xzr // select cache level 0 in csselr + dsb sy // barrier to complete final cache operation + isb +exit: + ret +endfunc do_dcsw_op + +dcsw_loop_table: + dcsw_loop isw + dcsw_loop cisw + dcsw_loop csw + + +func dcsw_op_louis + dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT +endfunc dcsw_op_louis + + +func dcsw_op_all + dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT +endfunc dcsw_op_all + + /* --------------------------------------------------------------- + * Helper macro for data cache operations by set/way for the + * level specified + * --------------------------------------------------------------- + */ + .macro dcsw_op_level level + mrs x9, clidr_el1 + mov x3, \level + sub x10, x3, #2 + b do_dcsw_op + .endm + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 1 cache + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level1 + dcsw_op_level #(1 << LEVEL_SHIFT) +endfunc dcsw_op_level1 + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 2 cache + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level2 + dcsw_op_level #(2 << LEVEL_SHIFT) +endfunc dcsw_op_level2 + + /* --------------------------------------------------------------- + * Data cache operations by set/way for level 3 cache + * + * The main function, do_dcsw_op requires: + * x0: The operation type (0-2), as defined in arch.h + * --------------------------------------------------------------- + */ +func dcsw_op_level3 + dcsw_op_level #(3 << LEVEL_SHIFT) +endfunc dcsw_op_level3 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch64/misc_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch64/misc_helpers.S new file mode 100644 index 0000000..e7c246e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch64/misc_helpers.S @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .globl get_afflvl_shift + .globl mpidr_mask_lower_afflvls + .globl eret + .globl smc + + .globl zeromem16 + .globl memcpy16 + + .globl disable_mmu_el3 + .globl disable_mmu_icache_el3 + +#if SUPPORT_VFP + .globl enable_vfp +#endif + +func get_afflvl_shift + cmp x0, #3 + cinc x0, x0, eq + mov x1, #MPIDR_AFFLVL_SHIFT + lsl x0, x0, x1 + ret +endfunc get_afflvl_shift + +func mpidr_mask_lower_afflvls + cmp x1, #3 + cinc x1, x1, eq + mov x2, #MPIDR_AFFLVL_SHIFT + lsl x2, x1, x2 + lsr x0, x0, x2 + lsl x0, x0, x2 + ret +endfunc mpidr_mask_lower_afflvls + + +func eret + eret +endfunc eret + + +func smc + smc #0 +endfunc smc + +/* ----------------------------------------------------------------------- + * void zeromem16(void *mem, unsigned int length); + * + * Initialise a memory region to 0. + * The memory address must be 16-byte aligned. + * ----------------------------------------------------------------------- + */ +func zeromem16 +#if ASM_ASSERTION + tst x0, #0xf + ASM_ASSERT(eq) +#endif + add x2, x0, x1 +/* zero 16 bytes at a time */ +z_loop16: + sub x3, x2, x0 + cmp x3, #16 + b.lt z_loop1 + stp xzr, xzr, [x0], #16 + b z_loop16 +/* zero byte per byte */ +z_loop1: + cmp x0, x2 + b.eq z_end + strb wzr, [x0], #1 + b z_loop1 +z_end: + ret +endfunc zeromem16 + + +/* -------------------------------------------------------------------------- + * void memcpy16(void *dest, const void *src, unsigned int length) + * + * Copy length bytes from memory area src to memory area dest. + * The memory areas should not overlap. + * Destination and source addresses must be 16-byte aligned. + * -------------------------------------------------------------------------- + */ +func memcpy16 +#if ASM_ASSERTION + orr x3, x0, x1 + tst x3, #0xf + ASM_ASSERT(eq) +#endif +/* copy 16 bytes at a time */ +m_loop16: + cmp x2, #16 + b.lt m_loop1 + ldp x3, x4, [x1], #16 + stp x3, x4, [x0], #16 + sub x2, x2, #16 + b m_loop16 +/* copy byte per byte */ +m_loop1: + cbz x2, m_end + ldrb w3, [x1], #1 + strb w3, [x0], #1 + subs x2, x2, #1 + b.ne m_loop1 +m_end: + ret +endfunc memcpy16 + +/* --------------------------------------------------------------------------- + * Disable the MMU at EL3 + * --------------------------------------------------------------------------- + */ + +func disable_mmu_el3 + mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT) +do_disable_mmu: + mrs x0, sctlr_el3 + bic x0, x0, x1 + msr sctlr_el3, x0 + isb // ensure MMU is off + dsb sy + ret +endfunc disable_mmu_el3 + + +func disable_mmu_icache_el3 + mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) + b do_disable_mmu +endfunc disable_mmu_icache_el3 + +/* --------------------------------------------------------------------------- + * Enable the use of VFP at EL3 + * --------------------------------------------------------------------------- + */ +#if SUPPORT_VFP +func enable_vfp + mrs x0, cpacr_el1 + orr x0, x0, #CPACR_VFP_BITS + msr cpacr_el1, x0 + mrs x0, cptr_el3 + mov x1, #AARCH64_CPTR_TFP + bic x0, x0, x1 + msr cptr_el3, x0 + isb + ret +endfunc enable_vfp +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch64/xlat_tables.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch64/xlat_tables.c new file mode 100644 index 0000000..b140f29 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/aarch64/xlat_tables.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * This file is deprecated and is retained here only for compatibility. + * The xlat_tables library can be found in `lib/xlat_tables` directory. + */ +#if !ERROR_DEPRECATED +#include "../xlat_tables/xlat_tables_common.c" +#include "../xlat_tables/aarch64/xlat_tables.c" +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch32/aem_generic.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch32/aem_generic.S new file mode 100644 index 0000000..10ea4e4 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch32/aem_generic.S @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include + +func aem_generic_core_pwr_dwn + /* Assert if cache is enabled */ +#if ASM_ASSERTION + ldcopr r0, SCTLR + tst r0, #SCTLR_C_BIT + ASM_ASSERT(eq) +#endif + /* --------------------------------------------- + * Flush L1 cache to PoU. + * --------------------------------------------- + */ + mov r0, #DC_OP_CISW + b dcsw_op_louis +endfunc aem_generic_core_pwr_dwn + + +func aem_generic_cluster_pwr_dwn + /* Assert if cache is enabled */ +#if ASM_ASSERTION + ldcopr r0, SCTLR + tst r0, #SCTLR_C_BIT + ASM_ASSERT(eq) +#endif + /* --------------------------------------------- + * Flush L1 and L2 caches to PoC. + * --------------------------------------------- + */ + mov r0, #DC_OP_CISW + b dcsw_op_all +endfunc aem_generic_cluster_pwr_dwn + +/* cpu_ops for Base AEM FVP */ +declare_cpu_ops aem_generic, BASE_AEM_MIDR, 1 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch32/cortex_a32.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch32/cortex_a32.S new file mode 100644 index 0000000..b51f997 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch32/cortex_a32.S @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + + + /* --------------------------------------------- + * Disable intra-cluster coherency + * Clobbers: r0-r1 + * --------------------------------------------- + */ +func cortex_a32_disable_smp + ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1 + bic r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT + stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1 + isb + dsb sy + bx lr +endfunc cortex_a32_disable_smp + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A32. + * Clobbers: r0-r1 + * ------------------------------------------------- + */ +func cortex_a32_reset_func + /* --------------------------------------------- + * Enable the SMP bit. + * --------------------------------------------- + */ + ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1 + orr r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT + stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1 + isb + bx lr +endfunc cortex_a32_reset_func + + /* ---------------------------------------------------- + * The CPU Ops core power down function for Cortex-A32. + * Clobbers: r0-r3 + * ---------------------------------------------------- + */ +func cortex_a32_core_pwr_dwn + push {lr} + + /* Assert if cache is enabled */ +#if ASM_ASSERTION + ldcopr r0, SCTLR + tst r0, #SCTLR_C_BIT + ASM_ASSERT(eq) +#endif + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov r0, #DC_OP_CISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + pop {lr} + b cortex_a32_disable_smp +endfunc cortex_a32_core_pwr_dwn + + /* ------------------------------------------------------- + * The CPU Ops cluster power down function for Cortex-A32. + * Clobbers: r0-r3 + * ------------------------------------------------------- + */ +func cortex_a32_cluster_pwr_dwn + push {lr} + + /* Assert if cache is enabled */ +#if ASM_ASSERTION + ldcopr r0, SCTLR + tst r0, #SCTLR_C_BIT + ASM_ASSERT(eq) +#endif + + /* --------------------------------------------- + * Flush L1 cache. + * --------------------------------------------- + */ + mov r0, #DC_OP_CISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Disable the optional ACP. + * --------------------------------------------- + */ + bl plat_disable_acp + + /* --------------------------------------------- + * Flush L2 cache. + * --------------------------------------------- + */ + mov r0, #DC_OP_CISW + bl dcsw_op_level2 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + pop {lr} + b cortex_a32_disable_smp +endfunc cortex_a32_cluster_pwr_dwn + +declare_cpu_ops cortex_a32, CORTEX_A32_MIDR diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch32/cpu_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch32/cpu_helpers.S new file mode 100644 index 0000000..042ffbd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch32/cpu_helpers.S @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +#if IMAGE_BL1 || IMAGE_BL32 + /* + * The reset handler common to all platforms. After a matching + * cpu_ops structure entry is found, the correponding reset_handler + * in the cpu_ops is invoked. The reset handler is invoked very early + * in the boot sequence and it is assumed that we can clobber r0 - r10 + * without the need to follow AAPCS. + * Clobbers: r0 - r10 + */ + .globl reset_handler +func reset_handler + mov r10, lr + + /* The plat_reset_handler can clobber r0 - r9 */ + bl plat_reset_handler + + /* Get the matching cpu_ops pointer (clobbers: r0 - r5) */ + bl get_cpu_ops_ptr + +#if ASM_ASSERTION + cmp r0, #0 + ASM_ASSERT(ne) +#endif + + /* Get the cpu_ops reset handler */ + ldr r1, [r0, #CPU_RESET_FUNC] + cmp r1, #0 + mov lr, r10 + bxne r1 + bx lr +endfunc reset_handler + +#endif /* IMAGE_BL1 || IMAGE_BL32 */ + +#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */ + /* + * The prepare core power down function for all platforms. After + * the cpu_ops pointer is retrieved from cpu_data, the corresponding + * pwr_dwn_core in the cpu_ops is invoked. Follows AAPCS. + */ + .globl prepare_core_pwr_dwn +func prepare_core_pwr_dwn + push {lr} + bl _cpu_data + pop {lr} + + ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR] +#if ASM_ASSERTION + cmp r1, #0 + ASM_ASSERT(ne) +#endif + + /* Get the cpu_ops core_pwr_dwn handler */ + ldr r0, [r1, #CPU_PWR_DWN_CORE] + bx r0 +endfunc prepare_core_pwr_dwn + + /* + * The prepare cluster power down function for all platforms. After + * the cpu_ops pointer is retrieved from cpu_data, the corresponding + * pwr_dwn_cluster in the cpu_ops is invoked. Follows AAPCS. + */ + .globl prepare_cluster_pwr_dwn +func prepare_cluster_pwr_dwn + push {lr} + bl _cpu_data + pop {lr} + + ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR] +#if ASM_ASSERTION + cmp r1, #0 + ASM_ASSERT(ne) +#endif + + /* Get the cpu_ops cluster_pwr_dwn handler */ + ldr r0, [r1, #CPU_PWR_DWN_CLUSTER] + bx r0 +endfunc prepare_cluster_pwr_dwn + + /* + * Initializes the cpu_ops_ptr if not already initialized + * in cpu_data. This must only be called after the data cache + * is enabled. AAPCS is followed. + */ + .globl init_cpu_ops +func init_cpu_ops + push {r4 - r6, lr} + bl _cpu_data + mov r6, r0 + ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR] + cmp r1, #0 + bne 1f + bl get_cpu_ops_ptr +#if ASM_ASSERTION + cmp r0, #0 + ASM_ASSERT(ne) +#endif + str r0, [r6, #CPU_DATA_CPU_OPS_PTR]! +1: + pop {r4 - r6, pc} +endfunc init_cpu_ops + +#endif /* IMAGE_BL32 */ + + /* + * The below function returns the cpu_ops structure matching the + * midr of the core. It reads the MIDR and finds the matching + * entry in cpu_ops entries. Only the implementation and part number + * are used to match the entries. + * Return : + * r0 - The matching cpu_ops pointer on Success + * r0 - 0 on failure. + * Clobbers: r0 - r5 + */ + .globl get_cpu_ops_ptr +func get_cpu_ops_ptr + /* Get the cpu_ops start and end locations */ + ldr r4, =(__CPU_OPS_START__ + CPU_MIDR) + ldr r5, =(__CPU_OPS_END__ + CPU_MIDR) + + /* Initialize the return parameter */ + mov r0, #0 + + /* Read the MIDR_EL1 */ + ldcopr r2, MIDR + ldr r3, =CPU_IMPL_PN_MASK + + /* Retain only the implementation and part number using mask */ + and r2, r2, r3 +1: + /* Check if we have reached end of list */ + cmp r4, r5 + bge error_exit + + /* load the midr from the cpu_ops */ + ldr r1, [r4], #CPU_OPS_SIZE + and r1, r1, r3 + + /* Check if midr matches to midr of this core */ + cmp r1, r2 + bne 1b + + /* Subtract the increment and offset to get the cpu-ops pointer */ + sub r0, r4, #(CPU_OPS_SIZE + CPU_MIDR) +error_exit: + bx lr +endfunc get_cpu_ops_ptr diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/aem_generic.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/aem_generic.S new file mode 100644 index 0000000..0ab5253 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/aem_generic.S @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include + +func aem_generic_core_pwr_dwn + /* --------------------------------------------- + * Disable the Data Cache. + * --------------------------------------------- + */ + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + + mov x0, #DCCISW + + /* --------------------------------------------- + * Flush L1 cache to PoU. + * --------------------------------------------- + */ + b dcsw_op_louis +endfunc aem_generic_core_pwr_dwn + + +func aem_generic_cluster_pwr_dwn + /* --------------------------------------------- + * Disable the Data Cache. + * --------------------------------------------- + */ + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + + /* --------------------------------------------- + * Flush L1 and L2 caches to PoC. + * --------------------------------------------- + */ + mov x0, #DCCISW + b dcsw_op_all +endfunc aem_generic_cluster_pwr_dwn + + /* --------------------------------------------- + * This function provides cpu specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.aem_generic_regs, "aS" +aem_generic_regs: /* The ascii list of register names to be reported */ + .asciz "" /* no registers to report */ + +func aem_generic_cpu_reg_dump + adr x6, aem_generic_regs + ret +endfunc aem_generic_cpu_reg_dump + + +/* cpu_ops for Base AEM FVP */ +declare_cpu_ops aem_generic, BASE_AEM_MIDR, 1 + +/* cpu_ops for Foundation FVP */ +declare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, 1 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a35.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a35.S new file mode 100644 index 0000000..ba29d6d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a35.S @@ -0,0 +1,160 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + + /* --------------------------------------------- + * Disable L1 data cache and unified L2 cache + * --------------------------------------------- + */ +func cortex_a35_disable_dcache + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + ret +endfunc cortex_a35_disable_dcache + + /* --------------------------------------------- + * Disable intra-cluster coherency + * --------------------------------------------- + */ +func cortex_a35_disable_smp + mrs x0, CORTEX_A35_CPUECTLR_EL1 + bic x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT + msr CORTEX_A35_CPUECTLR_EL1, x0 + isb + dsb sy + ret +endfunc cortex_a35_disable_smp + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A35. + * Clobbers: x0 + * ------------------------------------------------- + */ +func cortex_a35_reset_func + /* --------------------------------------------- + * Enable the SMP bit. + * --------------------------------------------- + */ + mrs x0, CORTEX_A35_CPUECTLR_EL1 + orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT + msr CORTEX_A35_CPUECTLR_EL1, x0 + isb + ret +endfunc cortex_a35_reset_func + +func cortex_a35_core_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a35_disable_dcache + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a35_disable_smp +endfunc cortex_a35_core_pwr_dwn + +func cortex_a35_cluster_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a35_disable_dcache + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Disable the optional ACP. + * --------------------------------------------- + */ + bl plat_disable_acp + + /* --------------------------------------------- + * Flush L2 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level2 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a35_disable_smp +endfunc cortex_a35_cluster_pwr_dwn + + /* --------------------------------------------- + * This function provides cortex_a35 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a35_regs, "aS" +cortex_a35_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a35_cpu_reg_dump + adr x6, cortex_a35_regs + mrs x8, CORTEX_A35_CPUECTLR_EL1 + ret +endfunc cortex_a35_cpu_reg_dump + +declare_cpu_ops cortex_a35, CORTEX_A35_MIDR diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a53.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a53.S new file mode 100644 index 0000000..ed546e7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a53.S @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include + + /* --------------------------------------------- + * Disable L1 data cache and unified L2 cache + * --------------------------------------------- + */ +func cortex_a53_disable_dcache + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + ret +endfunc cortex_a53_disable_dcache + + /* --------------------------------------------- + * Disable intra-cluster coherency + * --------------------------------------------- + */ +func cortex_a53_disable_smp + mrs x0, CPUECTLR_EL1 + bic x0, x0, #CPUECTLR_SMP_BIT + msr CPUECTLR_EL1, x0 + isb + dsb sy + ret +endfunc cortex_a53_disable_smp + + /* -------------------------------------------------- + * Errata Workaround for Cortex A53 Errata #826319. + * This applies only to revision <= r0p2 of Cortex A53. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * -------------------------------------------------- + */ +func errata_a53_826319_wa + /* + * Compare x0 against revision r0p2 + */ + cmp x0, #2 + b.ls apply_826319 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_826319: + mrs x1, L2ACTLR_EL1 + bic x1, x1, #L2ACTLR_ENABLE_UNIQUECLEAN + orr x1, x1, #L2ACTLR_DISABLE_CLEAN_PUSH + msr L2ACTLR_EL1, x1 + ret +endfunc errata_a53_826319_wa + + /* --------------------------------------------------------------------- + * Disable the cache non-temporal hint. + * + * This ignores the Transient allocation hint in the MAIR and treats + * allocations the same as non-transient allocation types. As a result, + * the LDNP and STNP instructions in AArch64 behave the same as the + * equivalent LDP and STP instructions. + * + * This is relevant only for revisions <= r0p3 of Cortex-A53. + * From r0p4 and onwards, the bit to disable the hint is enabled by + * default at reset. + * + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------------------------- + */ +func a53_disable_non_temporal_hint + /* + * Compare x0 against revision r0p3 + */ + cmp x0, #3 + b.ls disable_hint +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +disable_hint: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_DTAH + msr CPUACTLR_EL1, x1 + ret +endfunc a53_disable_non_temporal_hint + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A53. + * Clobbers: x0-x5, x15, x19, x30 + * ------------------------------------------------- + */ +func cortex_a53_reset_func + mov x19, x30 + mrs x0, midr_el1 + + /* + * Extract the variant[20:23] and revision[0:3] from x0 + * and pack it in x15[0:7] as variant[4:7] and revision[0:3]. + * First extract x0[16:23] to x15[0:7] and zero fill the rest. + * Then extract x0[0:3] into x15[0:3] retaining other bits. + */ + ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), \ + #(MIDR_REV_BITS + MIDR_VAR_BITS) + bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS + +#if ERRATA_A53_826319 + mov x0, x15 + bl errata_a53_826319_wa +#endif + +#if ERRATA_A53_836870 || A53_DISABLE_NON_TEMPORAL_HINT + mov x0, x15 + bl a53_disable_non_temporal_hint +#endif + + /* --------------------------------------------- + * Enable the SMP bit. + * --------------------------------------------- + */ + mrs x0, CPUECTLR_EL1 + orr x0, x0, #CPUECTLR_SMP_BIT + msr CPUECTLR_EL1, x0 + isb + ret x19 +endfunc cortex_a53_reset_func + +func cortex_a53_core_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a53_disable_dcache + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a53_disable_smp +endfunc cortex_a53_core_pwr_dwn + +func cortex_a53_cluster_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a53_disable_dcache + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Disable the optional ACP. + * --------------------------------------------- + */ + bl plat_disable_acp + + /* --------------------------------------------- + * Flush L2 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level2 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a53_disable_smp +endfunc cortex_a53_cluster_pwr_dwn + + /* --------------------------------------------- + * This function provides cortex_a53 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a53_regs, "aS" +cortex_a53_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" + +func cortex_a53_cpu_reg_dump + adr x6, cortex_a53_regs + mrs x8, CPUECTLR_EL1 + mrs x9, CPUMERRSR_EL1 + mrs x10, L2MERRSR_EL1 + ret +endfunc cortex_a53_cpu_reg_dump + +declare_cpu_ops cortex_a53, CORTEX_A53_MIDR diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a57.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a57.S new file mode 100644 index 0000000..d6b181d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a57.S @@ -0,0 +1,491 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include + + /* --------------------------------------------- + * Disable L1 data cache and unified L2 cache + * --------------------------------------------- + */ +func cortex_a57_disable_dcache + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + ret +endfunc cortex_a57_disable_dcache + + /* --------------------------------------------- + * Disable all types of L2 prefetches. + * --------------------------------------------- + */ +func cortex_a57_disable_l2_prefetch + mrs x0, CPUECTLR_EL1 + orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT + mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK + orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK + bic x0, x0, x1 + msr CPUECTLR_EL1, x0 + isb + dsb ish + ret +endfunc cortex_a57_disable_l2_prefetch + + /* --------------------------------------------- + * Disable intra-cluster coherency + * --------------------------------------------- + */ +func cortex_a57_disable_smp + mrs x0, CPUECTLR_EL1 + bic x0, x0, #CPUECTLR_SMP_BIT + msr CPUECTLR_EL1, x0 + ret +endfunc cortex_a57_disable_smp + + /* --------------------------------------------- + * Disable debug interfaces + * --------------------------------------------- + */ +func cortex_a57_disable_ext_debug + mov x0, #1 + msr osdlr_el1, x0 + isb + dsb sy + ret +endfunc cortex_a57_disable_ext_debug + + /* -------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #806969. + * This applies only to revision r0p0 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * -------------------------------------------------- + */ +func errata_a57_806969_wa + /* + * Compare x0 against revision r0p0 + */ + cbz x0, apply_806969 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_806969: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_806969_wa + + + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #813420. + * This applies only to revision r0p0 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_813420_wa + /* + * Compare x0 against revision r0p0 + */ + cbz x0, apply_813420 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_813420: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_DCC_AS_DCCI + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_813420_wa + + /* -------------------------------------------------------------------- + * Disable the over-read from the LDNP instruction. + * + * This applies to all revisions <= r1p2. The performance degradation + * observed with LDNP/STNP has been fixed on r1p3 and onwards. + * + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5, x30 + * --------------------------------------------------------------------- + */ +func a57_disable_ldnp_overread + /* + * Compare x0 against revision r1p2 + */ + cmp x0, #0x12 + b.ls disable_hint +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +disable_hint: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_DIS_OVERREAD + msr CPUACTLR_EL1, x1 + ret +endfunc a57_disable_ldnp_overread + + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #826974. + * This applies only to revision <= r1p1 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_826974_wa + /* + * Compare x0 against revision r1p1 + */ + cmp x0, #0x11 + b.ls apply_826974 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_826974: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_DIS_LOAD_PASS_DMB + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_826974_wa + + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #826977. + * This applies only to revision <= r1p1 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_826977_wa + /* + * Compare x0 against revision r1p1 + */ + cmp x0, #0x11 + b.ls apply_826977 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_826977: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_GRE_NGRE_AS_NGNRE + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_826977_wa + + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #828024. + * This applies only to revision <= r1p1 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_828024_wa + /* + * Compare x0 against revision r1p1 + */ + cmp x0, #0x11 + b.ls apply_828024 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_828024: + mrs x1, CPUACTLR_EL1 + /* + * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 + * instructions here because the resulting bitmask doesn't fit in a + * 16-bit value so it cannot be encoded in a single instruction. + */ + orr x1, x1, #CPUACTLR_NO_ALLOC_WBWA + orr x1, x1, #(CPUACTLR_DIS_L1_STREAMING | CPUACTLR_DIS_STREAMING) + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_828024_wa + + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #829520. + * This applies only to revision <= r1p2 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_829520_wa + /* + * Compare x0 against revision r1p2 + */ + cmp x0, #0x12 + b.ls apply_829520 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_829520: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_829520_wa + + /* --------------------------------------------------- + * Errata Workaround for Cortex A57 Errata #833471. + * This applies only to revision <= r1p2 of Cortex A57. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Clobbers : x0 - x5 + * --------------------------------------------------- + */ +func errata_a57_833471_wa + /* + * Compare x0 against revision r1p2 + */ + cmp x0, #0x12 + b.ls apply_833471 +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + b print_revision_warning +#else + ret +#endif +apply_833471: + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_FORCE_FPSCR_FLUSH + msr CPUACTLR_EL1, x1 + ret +endfunc errata_a57_833471_wa + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A57. + * Clobbers: x0-x5, x15, x19, x30 + * ------------------------------------------------- + */ +func cortex_a57_reset_func + mov x19, x30 + mrs x0, midr_el1 + + /* + * Extract the variant[20:23] and revision[0:3] from x0 + * and pack it in x15[0:7] as variant[4:7] and revision[0:3]. + * First extract x0[16:23] to x15[0:7] and zero fill the rest. + * Then extract x0[0:3] into x15[0:3] retaining other bits. + */ + ubfx x15, x0, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), #(MIDR_REV_BITS + MIDR_VAR_BITS) + bfxil x15, x0, #MIDR_REV_SHIFT, #MIDR_REV_BITS + +#if ERRATA_A57_806969 + mov x0, x15 + bl errata_a57_806969_wa +#endif + +#if ERRATA_A57_813420 + mov x0, x15 + bl errata_a57_813420_wa +#endif + +#if A57_DISABLE_NON_TEMPORAL_HINT + mov x0, x15 + bl a57_disable_ldnp_overread +#endif + +#if ERRATA_A57_826974 + mov x0, x15 + bl errata_a57_826974_wa +#endif + +#if ERRATA_A57_826977 + mov x0, x15 + bl errata_a57_826977_wa +#endif + +#if ERRATA_A57_828024 + mov x0, x15 + bl errata_a57_828024_wa +#endif + +#if ERRATA_A57_829520 + mov x0, x15 + bl errata_a57_829520_wa +#endif + +#if ERRATA_A57_833471 + mov x0, x15 + bl errata_a57_833471_wa +#endif + + /* --------------------------------------------- + * Enable the SMP bit. + * --------------------------------------------- + */ + mrs x0, CPUECTLR_EL1 + orr x0, x0, #CPUECTLR_SMP_BIT + msr CPUECTLR_EL1, x0 + isb + ret x19 +endfunc cortex_a57_reset_func + + /* ---------------------------------------------------- + * The CPU Ops core power down function for Cortex-A57. + * ---------------------------------------------------- + */ +func cortex_a57_core_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a57_disable_dcache + + /* --------------------------------------------- + * Disable the L2 prefetches. + * --------------------------------------------- + */ + bl cortex_a57_disable_l2_prefetch + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + bl cortex_a57_disable_smp + + /* --------------------------------------------- + * Force the debug interfaces to be quiescent + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a57_disable_ext_debug +endfunc cortex_a57_core_pwr_dwn + + /* ------------------------------------------------------- + * The CPU Ops cluster power down function for Cortex-A57. + * ------------------------------------------------------- + */ +func cortex_a57_cluster_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a57_disable_dcache + + /* --------------------------------------------- + * Disable the L2 prefetches. + * --------------------------------------------- + */ + bl cortex_a57_disable_l2_prefetch + +#if !SKIP_A57_L1_FLUSH_PWR_DWN + /* ------------------------------------------------- + * Flush the L1 caches. + * ------------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 +#endif + /* --------------------------------------------- + * Disable the optional ACP. + * --------------------------------------------- + */ + bl plat_disable_acp + + /* ------------------------------------------------- + * Flush the L2 caches. + * ------------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level2 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + bl cortex_a57_disable_smp + + /* --------------------------------------------- + * Force the debug interfaces to be quiescent + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a57_disable_ext_debug +endfunc cortex_a57_cluster_pwr_dwn + + /* --------------------------------------------- + * This function provides cortex_a57 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a57_regs, "aS" +cortex_a57_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" + +func cortex_a57_cpu_reg_dump + adr x6, cortex_a57_regs + mrs x8, CPUECTLR_EL1 + mrs x9, CPUMERRSR_EL1 + mrs x10, L2MERRSR_EL1 + ret +endfunc cortex_a57_cpu_reg_dump + + +declare_cpu_ops cortex_a57, CORTEX_A57_MIDR diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a72.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a72.S new file mode 100644 index 0000000..9f04fb7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a72.S @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include + + /* --------------------------------------------- + * Disable L1 data cache and unified L2 cache + * --------------------------------------------- + */ +func cortex_a72_disable_dcache + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + ret +endfunc cortex_a72_disable_dcache + + /* --------------------------------------------- + * Disable all types of L2 prefetches. + * --------------------------------------------- + */ +func cortex_a72_disable_l2_prefetch + mrs x0, CPUECTLR_EL1 + orr x0, x0, #CPUECTLR_DIS_TWD_ACC_PFTCH_BIT + mov x1, #CPUECTLR_L2_IPFTCH_DIST_MASK + orr x1, x1, #CPUECTLR_L2_DPFTCH_DIST_MASK + bic x0, x0, x1 + msr CPUECTLR_EL1, x0 + isb + ret +endfunc cortex_a72_disable_l2_prefetch + + /* --------------------------------------------- + * Disable the load-store hardware prefetcher. + * --------------------------------------------- + */ +func cortex_a72_disable_hw_prefetcher + mrs x0, CPUACTLR_EL1 + orr x0, x0, #CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH + msr CPUACTLR_EL1, x0 + isb + dsb ish + ret +endfunc cortex_a72_disable_hw_prefetcher + + /* --------------------------------------------- + * Disable intra-cluster coherency + * --------------------------------------------- + */ +func cortex_a72_disable_smp + mrs x0, CPUECTLR_EL1 + bic x0, x0, #CPUECTLR_SMP_BIT + msr CPUECTLR_EL1, x0 + ret +endfunc cortex_a72_disable_smp + + /* --------------------------------------------- + * Disable debug interfaces + * --------------------------------------------- + */ +func cortex_a72_disable_ext_debug + mov x0, #1 + msr osdlr_el1, x0 + isb + dsb sy + ret +endfunc cortex_a72_disable_ext_debug + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-A72. + * ------------------------------------------------- + */ +func cortex_a72_reset_func + /* --------------------------------------------- + * As a bare minimum enable the SMP bit. + * --------------------------------------------- + */ + mrs x0, CPUECTLR_EL1 + orr x0, x0, #CPUECTLR_SMP_BIT + msr CPUECTLR_EL1, x0 + isb + ret +endfunc cortex_a72_reset_func + + /* ---------------------------------------------------- + * The CPU Ops core power down function for Cortex-A72. + * ---------------------------------------------------- + */ +func cortex_a72_core_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a72_disable_dcache + + /* --------------------------------------------- + * Disable the L2 prefetches. + * --------------------------------------------- + */ + bl cortex_a72_disable_l2_prefetch + + /* --------------------------------------------- + * Disable the load-store hardware prefetcher. + * --------------------------------------------- + */ + bl cortex_a72_disable_hw_prefetcher + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + bl cortex_a72_disable_smp + + /* --------------------------------------------- + * Force the debug interfaces to be quiescent + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a72_disable_ext_debug +endfunc cortex_a72_core_pwr_dwn + + /* ------------------------------------------------------- + * The CPU Ops cluster power down function for Cortex-A72. + * ------------------------------------------------------- + */ +func cortex_a72_cluster_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a72_disable_dcache + + /* --------------------------------------------- + * Disable the L2 prefetches. + * --------------------------------------------- + */ + bl cortex_a72_disable_l2_prefetch + + /* --------------------------------------------- + * Disable the load-store hardware prefetcher. + * --------------------------------------------- + */ + bl cortex_a72_disable_hw_prefetcher + +#if !SKIP_A72_L1_FLUSH_PWR_DWN + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 +#endif + + /* --------------------------------------------- + * Disable the optional ACP. + * --------------------------------------------- + */ + bl plat_disable_acp + + /* ------------------------------------------------- + * Flush the L2 caches. + * ------------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level2 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + bl cortex_a72_disable_smp + + /* --------------------------------------------- + * Force the debug interfaces to be quiescent + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a72_disable_ext_debug +endfunc cortex_a72_cluster_pwr_dwn + + /* --------------------------------------------- + * This function provides cortex_a72 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a72_regs, "aS" +cortex_a72_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" + +func cortex_a72_cpu_reg_dump + adr x6, cortex_a72_regs + mrs x8, CPUECTLR_EL1 + mrs x9, CPUMERRSR_EL1 + mrs x10, L2MERRSR_EL1 + ret +endfunc cortex_a72_cpu_reg_dump + + +declare_cpu_ops cortex_a72, CORTEX_A72_MIDR diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a73.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a73.S new file mode 100644 index 0000000..e1615db --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cortex_a73.S @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include + + /* --------------------------------------------- + * Disable L1 data cache + * --------------------------------------------- + */ +func cortex_a73_disable_dcache + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + ret +endfunc cortex_a73_disable_dcache + + /* --------------------------------------------- + * Disable intra-cluster coherency + * --------------------------------------------- + */ +func cortex_a73_disable_smp + mrs x0, CORTEX_A73_CPUECTLR_EL1 + bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT + msr CORTEX_A73_CPUECTLR_EL1, x0 + isb + dsb sy + ret +endfunc cortex_a73_disable_smp + +func cortex_a73_reset_func + /* --------------------------------------------- + * Enable the SMP bit. + * Clobbers : x0 + * --------------------------------------------- + */ + mrs x0, CORTEX_A73_CPUECTLR_EL1 + orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT + msr CORTEX_A73_CPUECTLR_EL1, x0 + isb + ret +endfunc cortex_a73_reset_func + +func cortex_a73_core_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a73_disable_dcache + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a73_disable_smp +endfunc cortex_a73_core_pwr_dwn + +func cortex_a73_cluster_pwr_dwn + mov x18, x30 + + /* --------------------------------------------- + * Turn off caches. + * --------------------------------------------- + */ + bl cortex_a73_disable_dcache + + /* --------------------------------------------- + * Flush L1 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level1 + + /* --------------------------------------------- + * Disable the optional ACP. + * --------------------------------------------- + */ + bl plat_disable_acp + + /* --------------------------------------------- + * Flush L2 caches. + * --------------------------------------------- + */ + mov x0, #DCCISW + bl dcsw_op_level2 + + /* --------------------------------------------- + * Come out of intra cluster coherency + * --------------------------------------------- + */ + mov x30, x18 + b cortex_a73_disable_smp +endfunc cortex_a73_cluster_pwr_dwn + + /* --------------------------------------------- + * This function provides cortex_a73 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a73_regs, "aS" +cortex_a73_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "l2merrsr_el1", "" + +func cortex_a73_cpu_reg_dump + adr x6, cortex_a73_regs + mrs x8, CORTEX_A73_CPUECTLR_EL1 + mrs x9, CORTEX_A73_L2MERRSR_EL1 + ret +endfunc cortex_a73_cpu_reg_dump + +declare_cpu_ops cortex_a73, CORTEX_A73_MIDR diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cpu_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cpu_helpers.S new file mode 100644 index 0000000..dab933c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/cpu_helpers.S @@ -0,0 +1,234 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#if IMAGE_BL31 +#include +#endif +#include + + /* Reset fn is needed in BL at reset vector */ +#if IMAGE_BL1 || IMAGE_BL31 + /* + * The reset handler common to all platforms. After a matching + * cpu_ops structure entry is found, the correponding reset_handler + * in the cpu_ops is invoked. + * Clobbers: x0 - x19, x30 + */ + .globl reset_handler +func reset_handler + mov x19, x30 + + /* The plat_reset_handler can clobber x0 - x18, x30 */ + bl plat_reset_handler + + /* Get the matching cpu_ops pointer */ + bl get_cpu_ops_ptr +#if ASM_ASSERTION + cmp x0, #0 + ASM_ASSERT(ne) +#endif + + /* Get the cpu_ops reset handler */ + ldr x2, [x0, #CPU_RESET_FUNC] + mov x30, x19 + cbz x2, 1f + + /* The cpu_ops reset handler can clobber x0 - x19, x30 */ + br x2 +1: + ret +endfunc reset_handler + +#endif /* IMAGE_BL1 || IMAGE_BL31 */ + +#if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */ + /* + * The prepare core power down function for all platforms. After + * the cpu_ops pointer is retrieved from cpu_data, the corresponding + * pwr_dwn_core in the cpu_ops is invoked. + */ + .globl prepare_core_pwr_dwn +func prepare_core_pwr_dwn + mrs x1, tpidr_el3 + ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR] +#if ASM_ASSERTION + cmp x0, #0 + ASM_ASSERT(ne) +#endif + + /* Get the cpu_ops core_pwr_dwn handler */ + ldr x1, [x0, #CPU_PWR_DWN_CORE] + br x1 +endfunc prepare_core_pwr_dwn + + /* + * The prepare cluster power down function for all platforms. After + * the cpu_ops pointer is retrieved from cpu_data, the corresponding + * pwr_dwn_cluster in the cpu_ops is invoked. + */ + .globl prepare_cluster_pwr_dwn +func prepare_cluster_pwr_dwn + mrs x1, tpidr_el3 + ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR] +#if ASM_ASSERTION + cmp x0, #0 + ASM_ASSERT(ne) +#endif + + /* Get the cpu_ops cluster_pwr_dwn handler */ + ldr x1, [x0, #CPU_PWR_DWN_CLUSTER] + br x1 +endfunc prepare_cluster_pwr_dwn + + + /* + * Initializes the cpu_ops_ptr if not already initialized + * in cpu_data. This can be called without a runtime stack, but may + * only be called after the MMU is enabled. + * clobbers: x0 - x6, x10 + */ + .globl init_cpu_ops +func init_cpu_ops + mrs x6, tpidr_el3 + ldr x0, [x6, #CPU_DATA_CPU_OPS_PTR] + cbnz x0, 1f + mov x10, x30 + bl get_cpu_ops_ptr +#if ASM_ASSERTION + cmp x0, #0 + ASM_ASSERT(ne) +#endif + str x0, [x6, #CPU_DATA_CPU_OPS_PTR]! + mov x30, x10 +1: + ret +endfunc init_cpu_ops +#endif /* IMAGE_BL31 */ + +#if IMAGE_BL31 && CRASH_REPORTING + /* + * The cpu specific registers which need to be reported in a crash + * are reported via cpu_ops cpu_reg_dump function. After a matching + * cpu_ops structure entry is found, the correponding cpu_reg_dump + * in the cpu_ops is invoked. + */ + .globl do_cpu_reg_dump +func do_cpu_reg_dump + mov x16, x30 + + /* Get the matching cpu_ops pointer */ + bl get_cpu_ops_ptr + cbz x0, 1f + + /* Get the cpu_ops cpu_reg_dump */ + ldr x2, [x0, #CPU_REG_DUMP] + cbz x2, 1f + blr x2 +1: + mov x30, x16 + ret +endfunc do_cpu_reg_dump +#endif + + /* + * The below function returns the cpu_ops structure matching the + * midr of the core. It reads the MIDR_EL1 and finds the matching + * entry in cpu_ops entries. Only the implementation and part number + * are used to match the entries. + * Return : + * x0 - The matching cpu_ops pointer on Success + * x0 - 0 on failure. + * Clobbers : x0 - x5 + */ + .globl get_cpu_ops_ptr +func get_cpu_ops_ptr + /* Get the cpu_ops start and end locations */ + adr x4, (__CPU_OPS_START__ + CPU_MIDR) + adr x5, (__CPU_OPS_END__ + CPU_MIDR) + + /* Initialize the return parameter */ + mov x0, #0 + + /* Read the MIDR_EL1 */ + mrs x2, midr_el1 + mov_imm x3, CPU_IMPL_PN_MASK + + /* Retain only the implementation and part number using mask */ + and w2, w2, w3 +1: + /* Check if we have reached end of list */ + cmp x4, x5 + b.eq error_exit + + /* load the midr from the cpu_ops */ + ldr x1, [x4], #CPU_OPS_SIZE + and w1, w1, w3 + + /* Check if midr matches to midr of this core */ + cmp w1, w2 + b.ne 1b + + /* Subtract the increment and offset to get the cpu-ops pointer */ + sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR) +error_exit: + ret +endfunc get_cpu_ops_ptr + +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE +.section .rodata.rev_verbose_str, "aS" +rev_verbose_str: + .asciz "VERBOSE: Skipping CPU specific reset operation for non-matching CPU revision number.\n" + + /* + * This function prints the above warning message to the crash console. + * It should be called when a CPU specific operation is enabled in the + * build but doesn't apply to this CPU revision/part number. + * + * Clobber: x30, x0 - x5 + */ + .globl print_revision_warning +func print_revision_warning + mov x5, x30 + /* Ensure the console is initialized */ + bl plat_crash_console_init + /* Check if the console is initialized */ + cbz x0, 1f + /* The console is initialized */ + adr x4, rev_verbose_str + bl asm_print_str +1: + ret x5 +endfunc print_revision_warning +#endif + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/denver.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/denver.S new file mode 100644 index 0000000..bce0573 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/aarch64/denver.S @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + + /* --------------------------------------------- + * Disable debug interfaces + * --------------------------------------------- + */ +func denver_disable_ext_debug + mov x0, #1 + msr osdlr_el1, x0 + isb + dsb sy + ret +endfunc denver_disable_ext_debug + + /* ---------------------------------------------------- + * Enable dynamic code optimizer (DCO) + * ---------------------------------------------------- + */ +func denver_enable_dco + mrs x0, mpidr_el1 + and x0, x0, #0xF + mov x1, #1 + lsl x1, x1, x0 + msr s3_0_c15_c0_2, x1 + isb + ret +endfunc denver_enable_dco + + /* ---------------------------------------------------- + * Disable dynamic code optimizer (DCO) + * ---------------------------------------------------- + */ +func denver_disable_dco + + /* turn off background work */ + mrs x0, mpidr_el1 + and x0, x0, #0xF + mov x1, #1 + lsl x1, x1, x0 + lsl x2, x1, #16 + msr s3_0_c15_c0_2, x2 + isb + + /* wait till the background work turns off */ +1: mrs x2, s3_0_c15_c0_2 + lsr x2, x2, #32 + and w2, w2, 0xFFFF + and x2, x2, x1 + cbnz x2, 1b + + ret +endfunc denver_disable_dco + + /* ------------------------------------------------- + * The CPU Ops reset function for Denver. + * ------------------------------------------------- + */ +func denver_reset_func + + mov x19, x30 + + /* ---------------------------------------------------- + * Enable dynamic code optimizer (DCO) + * ---------------------------------------------------- + */ + bl denver_enable_dco + + ret x19 +endfunc denver_reset_func + + /* ---------------------------------------------------- + * The CPU Ops core power down function for Denver. + * ---------------------------------------------------- + */ +func denver_core_pwr_dwn + + mov x19, x30 + + /* ---------------------------------------------------- + * We enter the 'core power gated with ARM state not + * retained' power state during CPU power down. We let + * DCO know that we expect to enter this power state + * by writing to the ACTLR_EL1 register. + * ---------------------------------------------------- + */ + mov x0, #DENVER_CPU_STATE_POWER_DOWN + msr actlr_el1, x0 + + /* --------------------------------------------- + * Force DCO to be quiescent + * --------------------------------------------- + */ + bl denver_disable_dco + + /* --------------------------------------------- + * Force the debug interfaces to be quiescent + * --------------------------------------------- + */ + bl denver_disable_ext_debug + + ret x19 +endfunc denver_core_pwr_dwn + + /* ------------------------------------------------------- + * The CPU Ops cluster power down function for Denver. + * ------------------------------------------------------- + */ +func denver_cluster_pwr_dwn + ret +endfunc denver_cluster_pwr_dwn + + /* --------------------------------------------- + * This function provides Denver specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.denver_regs, "aS" +denver_regs: /* The ascii list of register names to be reported */ + .asciz "actlr_el1", "" + +func denver_cpu_reg_dump + adr x6, denver_regs + mrs x8, ACTLR_EL1 + ret +endfunc denver_cpu_reg_dump + +declare_cpu_ops denver, DENVER_1_0_MIDR diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/cpu-ops.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/cpu-ops.mk new file mode 100644 index 0000000..0659bff --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/cpus/cpu-ops.mk @@ -0,0 +1,131 @@ +# +# Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# Cortex A57 specific optimisation to skip L1 cache flush when +# cluster is powered down. +SKIP_A57_L1_FLUSH_PWR_DWN ?=0 + +# Flag to disable the cache non-temporal hint. +# It is enabled by default. +A53_DISABLE_NON_TEMPORAL_HINT ?=1 + +# Flag to disable the cache non-temporal hint. +# It is enabled by default. +A57_DISABLE_NON_TEMPORAL_HINT ?=1 + +# Process SKIP_A57_L1_FLUSH_PWR_DWN flag +$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN)) +$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN)) + +# Process A53_DISABLE_NON_TEMPORAL_HINT flag +$(eval $(call assert_boolean,A53_DISABLE_NON_TEMPORAL_HINT)) +$(eval $(call add_define,A53_DISABLE_NON_TEMPORAL_HINT)) + +# Process A57_DISABLE_NON_TEMPORAL_HINT flag +$(eval $(call assert_boolean,A57_DISABLE_NON_TEMPORAL_HINT)) +$(eval $(call add_define,A57_DISABLE_NON_TEMPORAL_HINT)) + + +# CPU Errata Build flags. +# These should be enabled by the platform if the erratum workaround needs to be +# applied. + +# Flag to apply erratum 826319 workaround during reset. This erratum applies +# only to revision <= r0p2 of the Cortex A53 cpu. +ERRATA_A53_826319 ?=0 + +# Flag to apply erratum 836870 workaround during reset. This erratum applies +# only to revision <= r0p3 of the Cortex A53 cpu. From r0p4 and onwards, this +# erratum workaround is enabled by default. +ERRATA_A53_836870 ?=0 + +# Flag to apply erratum 806969 workaround during reset. This erratum applies +# only to revision r0p0 of the Cortex A57 cpu. +ERRATA_A57_806969 ?=0 + +# Flag to apply erratum 813420 workaround during reset. This erratum applies +# only to revision r0p0 of the Cortex A57 cpu. +ERRATA_A57_813420 ?=0 + +# Flag to apply erratum 826974 workaround during reset. This erratum applies +# only to revision <= r1p1 of the Cortex A57 cpu. +ERRATA_A57_826974 ?=0 + +# Flag to apply erratum 826977 workaround during reset. This erratum applies +# only to revision <= r1p1 of the Cortex A57 cpu. +ERRATA_A57_826977 ?=0 + +# Flag to apply erratum 828024 workaround during reset. This erratum applies +# only to revision <= r1p1 of the Cortex A57 cpu. +ERRATA_A57_828024 ?=0 + +# Flag to apply erratum 829520 workaround during reset. This erratum applies +# only to revision <= r1p2 of the Cortex A57 cpu. +ERRATA_A57_829520 ?=0 + +# Flag to apply erratum 833471 workaround during reset. This erratum applies +# only to revision <= r1p2 of the Cortex A57 cpu. +ERRATA_A57_833471 ?=0 + +# Process ERRATA_A53_826319 flag +$(eval $(call assert_boolean,ERRATA_A53_826319)) +$(eval $(call add_define,ERRATA_A53_826319)) + +# Process ERRATA_A53_836870 flag +$(eval $(call assert_boolean,ERRATA_A53_836870)) +$(eval $(call add_define,ERRATA_A53_836870)) + +# Process ERRATA_A57_806969 flag +$(eval $(call assert_boolean,ERRATA_A57_806969)) +$(eval $(call add_define,ERRATA_A57_806969)) + +# Process ERRATA_A57_813420 flag +$(eval $(call assert_boolean,ERRATA_A57_813420)) +$(eval $(call add_define,ERRATA_A57_813420)) + +# Process ERRATA_A57_826974 flag +$(eval $(call assert_boolean,ERRATA_A57_826974)) +$(eval $(call add_define,ERRATA_A57_826974)) + +# Process ERRATA_A57_826977 flag +$(eval $(call assert_boolean,ERRATA_A57_826977)) +$(eval $(call add_define,ERRATA_A57_826977)) + +# Process ERRATA_A57_828024 flag +$(eval $(call assert_boolean,ERRATA_A57_828024)) +$(eval $(call add_define,ERRATA_A57_828024)) + +# Process ERRATA_A57_829520 flag +$(eval $(call assert_boolean,ERRATA_A57_829520)) +$(eval $(call add_define,ERRATA_A57_829520)) + +# Process ERRATA_A57_833471 flag +$(eval $(call assert_boolean,ERRATA_A57_833471)) +$(eval $(call add_define,ERRATA_A57_833471)) diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch32/context_mgmt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch32/context_mgmt.c new file mode 100644 index 0000000..bc5f9c4 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch32/context_mgmt.c @@ -0,0 +1,235 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Context management library initialisation routine. This library is used by + * runtime services to share pointers to 'cpu_context' structures for the secure + * and non-secure states. Management of the structures and their associated + * memory is not done by the context management library e.g. the PSCI service + * manages the cpu context used for entry from and exit to the non-secure state. + * The Secure payload manages the context(s) corresponding to the secure state. + * It also uses this library to get access to the non-secure + * state cpu context pointers. + ******************************************************************************/ +void cm_init(void) +{ + /* + * The context management library has only global data to initialize, but + * that will be done when the BSS is zeroed out + */ +} + +/******************************************************************************* + * The following function initializes the cpu_context 'ctx' for + * first use, and sets the initial entrypoint state as specified by the + * entry_point_info structure. + * + * The security state to initialize is determined by the SECURE attribute + * of the entry_point_info. The function returns a pointer to the initialized + * context and sets this as the next context to return to. + * + * The EE and ST attributes are used to configure the endianness and secure + * timer availability for the new execution context. + * + * To prepare the register state for entry call cm_prepare_el3_exit() and + * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to + * cm_e1_sysreg_context_restore(). + ******************************************************************************/ +static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) +{ + unsigned int security_state; + uint32_t scr, sctlr; + regs_t *reg_ctx; + + assert(ctx); + + security_state = GET_SECURITY_STATE(ep->h.attr); + + /* Clear any residual register values from the context */ + memset(ctx, 0, sizeof(*ctx)); + + reg_ctx = get_regs_ctx(ctx); + + /* + * Base the context SCR on the current value, adjust for entry point + * specific requirements + */ + scr = read_scr(); + scr &= ~(SCR_NS_BIT | SCR_HCE_BIT); + + if (security_state != SECURE) + scr |= SCR_NS_BIT; + + /* + * Set up SCTLR for the Non Secure context. + * EE bit is taken from the entrypoint attributes + * M, C and I bits must be zero (as required by PSCI specification) + * + * The target exception level is based on the spsr mode requested. + * If execution is requested to hyp mode, HVC is enabled + * via SCR.HCE. + * + * Always compute the SCTLR_EL1 value and save in the cpu_context + * - the HYP registers are set up by cm_preapre_ns_entry() as they + * are not part of the stored cpu_context + * + * TODO: In debug builds the spsr should be validated and checked + * against the CPU support, security state, endianness and pc + */ + if (security_state != SECURE) { + sctlr = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; + sctlr |= SCTLR_RES1; + write_ctx_reg(reg_ctx, CTX_NS_SCTLR, sctlr); + } + + if (GET_M32(ep->spsr) == MODE32_hyp) + scr |= SCR_HCE_BIT; + + write_ctx_reg(reg_ctx, CTX_SCR, scr); + write_ctx_reg(reg_ctx, CTX_LR, ep->pc); + write_ctx_reg(reg_ctx, CTX_SPSR, ep->spsr); + + /* + * Store the r0-r3 value from the entrypoint into the context + * Use memcpy as we are in control of the layout of the structures + */ + memcpy((void *)reg_ctx, (void *)&ep->args, sizeof(aapcs32_params_t)); +} + +/******************************************************************************* + * The following function initializes the cpu_context for a CPU specified by + * its `cpu_idx` for first use, and sets the initial entrypoint state as + * specified by the entry_point_info structure. + ******************************************************************************/ +void cm_init_context_by_index(unsigned int cpu_idx, + const entry_point_info_t *ep) +{ + cpu_context_t *ctx; + ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); + cm_init_context_common(ctx, ep); +} + +/******************************************************************************* + * The following function initializes the cpu_context for the current CPU + * for first use, and sets the initial entrypoint state as specified by the + * entry_point_info structure. + ******************************************************************************/ +void cm_init_my_context(const entry_point_info_t *ep) +{ + cpu_context_t *ctx; + ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); + cm_init_context_common(ctx, ep); +} + +/******************************************************************************* + * Prepare the CPU system registers for first entry into secure or normal world + * + * If execution is requested to hyp mode, HSCTLR is initialized + * If execution is requested to non-secure PL1, and the CPU supports + * HYP mode then HYP mode is disabled by configuring all necessary HYP mode + * registers. + ******************************************************************************/ +void cm_prepare_el3_exit(uint32_t security_state) +{ + uint32_t sctlr, scr, hcptr; + cpu_context_t *ctx = cm_get_context(security_state); + + assert(ctx); + + if (security_state == NON_SECURE) { + scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR); + if (scr & SCR_HCE_BIT) { + /* Use SCTLR value to initialize HSCTLR */ + sctlr = read_ctx_reg(get_regs_ctx(ctx), + CTX_NS_SCTLR); + sctlr |= HSCTLR_RES1; + /* Temporarily set the NS bit to access HSCTLR */ + write_scr(read_scr() | SCR_NS_BIT); + /* + * Make sure the write to SCR is complete so that + * we can access HSCTLR + */ + isb(); + write_hsctlr(sctlr); + isb(); + + write_scr(read_scr() & ~SCR_NS_BIT); + isb(); + } else if (read_id_pfr1() & + (ID_PFR1_VIRTEXT_MASK << ID_PFR1_VIRTEXT_SHIFT)) { + /* Set the NS bit to access HCR, HCPTR, CNTHCTL, VPIDR, VMPIDR */ + write_scr(read_scr() | SCR_NS_BIT); + isb(); + + /* PL2 present but unused, need to disable safely */ + write_hcr(0); + + /* HSCTLR : can be ignored when bypassing */ + + /* HCPTR : disable all traps TCPAC, TTA, TCP */ + hcptr = read_hcptr(); + hcptr &= ~(TCPAC_BIT | TTA_BIT | TCP11_BIT | TCP10_BIT); + write_hcptr(hcptr); + + /* Enable EL1 access to timer */ + write_cnthctl(PL1PCEN_BIT | PL1PCTEN_BIT); + + /* Reset CNTVOFF_EL2 */ + write64_cntvoff(0); + + /* Set VPIDR, VMPIDR to match MIDR, MPIDR */ + write_vpidr(read_midr()); + write_vmpidr(read_mpidr()); + + /* + * Reset VTTBR. + * Needed because cache maintenance operations depend on + * the VMID even when non-secure EL1&0 stage 2 address + * translation are disabled. + */ + write64_vttbr(0); + isb(); + + write_scr(read_scr() & ~SCR_NS_BIT); + isb(); + } + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch32/cpu_data.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch32/cpu_data.S new file mode 100644 index 0000000..b97911f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch32/cpu_data.S @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .globl _cpu_data + .globl _cpu_data_by_index + +/* ----------------------------------------------------------------- + * cpu_data_t *_cpu_data(void) + * + * Return the cpu_data structure for the current CPU. + * ----------------------------------------------------------------- + */ +func _cpu_data + push {lr} + bl plat_my_core_pos + pop {lr} + b _cpu_data_by_index +endfunc _cpu_data + +/* ----------------------------------------------------------------- + * cpu_data_t *_cpu_data_by_index(uint32_t cpu_index) + * + * Return the cpu_data structure for the CPU with given linear index + * + * This can be called without a valid stack. + * clobbers: r0, r1 + * ----------------------------------------------------------------- + */ +func _cpu_data_by_index + ldr r1, =percpu_data + add r0, r1, r0, LSL #CPU_DATA_LOG2SIZE + bx lr +endfunc _cpu_data_by_index diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch64/context.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch64/context.S new file mode 100644 index 0000000..7982e50 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch64/context.S @@ -0,0 +1,405 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .global el1_sysregs_context_save + .global el1_sysregs_context_restore +#if CTX_INCLUDE_FPREGS + .global fpregs_context_save + .global fpregs_context_restore +#endif + .global save_gp_registers + .global restore_gp_registers_eret + .global restore_gp_registers_callee_eret + .global el3_exit + +/* ----------------------------------------------------- + * The following function strictly follows the AArch64 + * PCS to use x9-x17 (temporary caller-saved registers) + * to save EL1 system register context. It assumes that + * 'x0' is pointing to a 'el1_sys_regs' structure where + * the register context will be saved. + * ----------------------------------------------------- + */ +func el1_sysregs_context_save + + mrs x9, spsr_el1 + mrs x10, elr_el1 + stp x9, x10, [x0, #CTX_SPSR_EL1] + + mrs x15, sctlr_el1 + mrs x16, actlr_el1 + stp x15, x16, [x0, #CTX_SCTLR_EL1] + + mrs x17, cpacr_el1 + mrs x9, csselr_el1 + stp x17, x9, [x0, #CTX_CPACR_EL1] + + mrs x10, sp_el1 + mrs x11, esr_el1 + stp x10, x11, [x0, #CTX_SP_EL1] + + mrs x12, ttbr0_el1 + mrs x13, ttbr1_el1 + stp x12, x13, [x0, #CTX_TTBR0_EL1] + + mrs x14, mair_el1 + mrs x15, amair_el1 + stp x14, x15, [x0, #CTX_MAIR_EL1] + + mrs x16, tcr_el1 + mrs x17, tpidr_el1 + stp x16, x17, [x0, #CTX_TCR_EL1] + + mrs x9, tpidr_el0 + mrs x10, tpidrro_el0 + stp x9, x10, [x0, #CTX_TPIDR_EL0] + + mrs x13, par_el1 + mrs x14, far_el1 + stp x13, x14, [x0, #CTX_PAR_EL1] + + mrs x15, afsr0_el1 + mrs x16, afsr1_el1 + stp x15, x16, [x0, #CTX_AFSR0_EL1] + + mrs x17, contextidr_el1 + mrs x9, vbar_el1 + stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] + + /* Save AArch32 system registers if the build has instructed so */ +#if CTX_INCLUDE_AARCH32_REGS + mrs x11, spsr_abt + mrs x12, spsr_und + stp x11, x12, [x0, #CTX_SPSR_ABT] + + mrs x13, spsr_irq + mrs x14, spsr_fiq + stp x13, x14, [x0, #CTX_SPSR_IRQ] + + mrs x15, dacr32_el2 + mrs x16, ifsr32_el2 + stp x15, x16, [x0, #CTX_DACR32_EL2] + + mrs x17, fpexc32_el2 + str x17, [x0, #CTX_FP_FPEXC32_EL2] +#endif + + /* Save NS timer registers if the build has instructed so */ +#if NS_TIMER_SWITCH + mrs x10, cntp_ctl_el0 + mrs x11, cntp_cval_el0 + stp x10, x11, [x0, #CTX_CNTP_CTL_EL0] + + mrs x12, cntv_ctl_el0 + mrs x13, cntv_cval_el0 + stp x12, x13, [x0, #CTX_CNTV_CTL_EL0] + + mrs x14, cntkctl_el1 + str x14, [x0, #CTX_CNTKCTL_EL1] +#endif + + ret +endfunc el1_sysregs_context_save + +/* ----------------------------------------------------- + * The following function strictly follows the AArch64 + * PCS to use x9-x17 (temporary caller-saved registers) + * to restore EL1 system register context. It assumes + * that 'x0' is pointing to a 'el1_sys_regs' structure + * from where the register context will be restored + * ----------------------------------------------------- + */ +func el1_sysregs_context_restore + + ldp x9, x10, [x0, #CTX_SPSR_EL1] + msr spsr_el1, x9 + msr elr_el1, x10 + + ldp x15, x16, [x0, #CTX_SCTLR_EL1] + msr sctlr_el1, x15 + msr actlr_el1, x16 + + ldp x17, x9, [x0, #CTX_CPACR_EL1] + msr cpacr_el1, x17 + msr csselr_el1, x9 + + ldp x10, x11, [x0, #CTX_SP_EL1] + msr sp_el1, x10 + msr esr_el1, x11 + + ldp x12, x13, [x0, #CTX_TTBR0_EL1] + msr ttbr0_el1, x12 + msr ttbr1_el1, x13 + + ldp x14, x15, [x0, #CTX_MAIR_EL1] + msr mair_el1, x14 + msr amair_el1, x15 + + ldp x16, x17, [x0, #CTX_TCR_EL1] + msr tcr_el1, x16 + msr tpidr_el1, x17 + + ldp x9, x10, [x0, #CTX_TPIDR_EL0] + msr tpidr_el0, x9 + msr tpidrro_el0, x10 + + ldp x13, x14, [x0, #CTX_PAR_EL1] + msr par_el1, x13 + msr far_el1, x14 + + ldp x15, x16, [x0, #CTX_AFSR0_EL1] + msr afsr0_el1, x15 + msr afsr1_el1, x16 + + ldp x17, x9, [x0, #CTX_CONTEXTIDR_EL1] + msr contextidr_el1, x17 + msr vbar_el1, x9 + + /* Restore AArch32 system registers if the build has instructed so */ +#if CTX_INCLUDE_AARCH32_REGS + ldp x11, x12, [x0, #CTX_SPSR_ABT] + msr spsr_abt, x11 + msr spsr_und, x12 + + ldp x13, x14, [x0, #CTX_SPSR_IRQ] + msr spsr_irq, x13 + msr spsr_fiq, x14 + + ldp x15, x16, [x0, #CTX_DACR32_EL2] + msr dacr32_el2, x15 + msr ifsr32_el2, x16 + + ldr x17, [x0, #CTX_FP_FPEXC32_EL2] + msr fpexc32_el2, x17 +#endif + /* Restore NS timer registers if the build has instructed so */ +#if NS_TIMER_SWITCH + ldp x10, x11, [x0, #CTX_CNTP_CTL_EL0] + msr cntp_ctl_el0, x10 + msr cntp_cval_el0, x11 + + ldp x12, x13, [x0, #CTX_CNTV_CTL_EL0] + msr cntv_ctl_el0, x12 + msr cntv_cval_el0, x13 + + ldr x14, [x0, #CTX_CNTKCTL_EL1] + msr cntkctl_el1, x14 +#endif + + /* No explict ISB required here as ERET covers it */ + ret +endfunc el1_sysregs_context_restore + +/* ----------------------------------------------------- + * The following function follows the aapcs_64 strictly + * to use x9-x17 (temporary caller-saved registers + * according to AArch64 PCS) to save floating point + * register context. It assumes that 'x0' is pointing to + * a 'fp_regs' structure where the register context will + * be saved. + * + * Access to VFP registers will trap if CPTR_EL3.TFP is + * set. However currently we don't use VFP registers + * nor set traps in Trusted Firmware, and assume it's + * cleared + * + * TODO: Revisit when VFP is used in secure world + * ----------------------------------------------------- + */ +#if CTX_INCLUDE_FPREGS +func fpregs_context_save + stp q0, q1, [x0, #CTX_FP_Q0] + stp q2, q3, [x0, #CTX_FP_Q2] + stp q4, q5, [x0, #CTX_FP_Q4] + stp q6, q7, [x0, #CTX_FP_Q6] + stp q8, q9, [x0, #CTX_FP_Q8] + stp q10, q11, [x0, #CTX_FP_Q10] + stp q12, q13, [x0, #CTX_FP_Q12] + stp q14, q15, [x0, #CTX_FP_Q14] + stp q16, q17, [x0, #CTX_FP_Q16] + stp q18, q19, [x0, #CTX_FP_Q18] + stp q20, q21, [x0, #CTX_FP_Q20] + stp q22, q23, [x0, #CTX_FP_Q22] + stp q24, q25, [x0, #CTX_FP_Q24] + stp q26, q27, [x0, #CTX_FP_Q26] + stp q28, q29, [x0, #CTX_FP_Q28] + stp q30, q31, [x0, #CTX_FP_Q30] + + mrs x9, fpsr + str x9, [x0, #CTX_FP_FPSR] + + mrs x10, fpcr + str x10, [x0, #CTX_FP_FPCR] + + ret +endfunc fpregs_context_save + +/* ----------------------------------------------------- + * The following function follows the aapcs_64 strictly + * to use x9-x17 (temporary caller-saved registers + * according to AArch64 PCS) to restore floating point + * register context. It assumes that 'x0' is pointing to + * a 'fp_regs' structure from where the register context + * will be restored. + * + * Access to VFP registers will trap if CPTR_EL3.TFP is + * set. However currently we don't use VFP registers + * nor set traps in Trusted Firmware, and assume it's + * cleared + * + * TODO: Revisit when VFP is used in secure world + * ----------------------------------------------------- + */ +func fpregs_context_restore + ldp q0, q1, [x0, #CTX_FP_Q0] + ldp q2, q3, [x0, #CTX_FP_Q2] + ldp q4, q5, [x0, #CTX_FP_Q4] + ldp q6, q7, [x0, #CTX_FP_Q6] + ldp q8, q9, [x0, #CTX_FP_Q8] + ldp q10, q11, [x0, #CTX_FP_Q10] + ldp q12, q13, [x0, #CTX_FP_Q12] + ldp q14, q15, [x0, #CTX_FP_Q14] + ldp q16, q17, [x0, #CTX_FP_Q16] + ldp q18, q19, [x0, #CTX_FP_Q18] + ldp q20, q21, [x0, #CTX_FP_Q20] + ldp q22, q23, [x0, #CTX_FP_Q22] + ldp q24, q25, [x0, #CTX_FP_Q24] + ldp q26, q27, [x0, #CTX_FP_Q26] + ldp q28, q29, [x0, #CTX_FP_Q28] + ldp q30, q31, [x0, #CTX_FP_Q30] + + ldr x9, [x0, #CTX_FP_FPSR] + msr fpsr, x9 + + ldr x10, [x0, #CTX_FP_FPCR] + msr fpcr, x10 + + /* + * No explict ISB required here as ERET to + * switch to secure EL1 or non-secure world + * covers it + */ + + ret +endfunc fpregs_context_restore +#endif /* CTX_INCLUDE_FPREGS */ + +/* ----------------------------------------------------- + * The following functions are used to save and restore + * all the general purpose registers. Ideally we would + * only save and restore the callee saved registers when + * a world switch occurs but that type of implementation + * is more complex. So currently we will always save and + * restore these registers on entry and exit of EL3. + * These are not macros to ensure their invocation fits + * within the 32 instructions per exception vector. + * clobbers: x18 + * ----------------------------------------------------- + */ +func save_gp_registers + stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] + stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] + stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] + stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] + stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] + stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] + stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] + stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] + stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] + stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] + stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] + stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] + mrs x18, sp_el0 + str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] + ret +endfunc save_gp_registers + +func restore_gp_registers_eret + ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] + ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] + b restore_gp_registers_callee_eret +endfunc restore_gp_registers_eret + +func restore_gp_registers_callee_eret + ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] + ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] + ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] + ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] + ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] + ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] + ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] + ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] + ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] + ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] + ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] + ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] + ldp x30, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] + msr sp_el0, x17 + ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] + eret +endfunc restore_gp_registers_callee_eret + + /* ----------------------------------------------------- + * This routine assumes that the SP_EL3 is pointing to + * a valid context structure from where the gp regs and + * other special registers can be retrieved. + * ----------------------------------------------------- + */ +func el3_exit + /* ----------------------------------------------------- + * Save the current SP_EL0 i.e. the EL3 runtime stack + * which will be used for handling the next SMC. Then + * switch to SP_EL3 + * ----------------------------------------------------- + */ + mov x17, sp + msr spsel, #1 + str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] + + /* ----------------------------------------------------- + * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET + * ----------------------------------------------------- + */ + ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] + ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] + msr scr_el3, x18 + msr spsr_el3, x16 + msr elr_el3, x17 + + /* Restore saved general purpose registers and return */ + b restore_gp_registers_eret +endfunc el3_exit diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch64/context_mgmt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch64/context_mgmt.c new file mode 100644 index 0000000..4527aa3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch64/context_mgmt.c @@ -0,0 +1,383 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/******************************************************************************* + * Context management library initialisation routine. This library is used by + * runtime services to share pointers to 'cpu_context' structures for the secure + * and non-secure states. Management of the structures and their associated + * memory is not done by the context management library e.g. the PSCI service + * manages the cpu context used for entry from and exit to the non-secure state. + * The Secure payload dispatcher service manages the context(s) corresponding to + * the secure state. It also uses this library to get access to the non-secure + * state cpu context pointers. + * Lastly, this library provides the api to make SP_EL3 point to the cpu context + * which will used for programming an entry into a lower EL. The same context + * will used to save state upon exception entry from that EL. + ******************************************************************************/ +void cm_init(void) +{ + /* + * The context management library has only global data to intialize, but + * that will be done when the BSS is zeroed out + */ +} + +/******************************************************************************* + * The following function initializes the cpu_context 'ctx' for + * first use, and sets the initial entrypoint state as specified by the + * entry_point_info structure. + * + * The security state to initialize is determined by the SECURE attribute + * of the entry_point_info. The function returns a pointer to the initialized + * context and sets this as the next context to return to. + * + * The EE and ST attributes are used to configure the endianess and secure + * timer availability for the new execution context. + * + * To prepare the register state for entry call cm_prepare_el3_exit() and + * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to + * cm_e1_sysreg_context_restore(). + ******************************************************************************/ +static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t *ep) +{ + unsigned int security_state; + uint32_t scr_el3; + el3_state_t *state; + gp_regs_t *gp_regs; + unsigned long sctlr_elx; + + assert(ctx); + + security_state = GET_SECURITY_STATE(ep->h.attr); + + /* Clear any residual register values from the context */ + memset(ctx, 0, sizeof(*ctx)); + + /* + * Base the context SCR on the current value, adjust for entry point + * specific requirements and set trap bits from the IMF + * TODO: provide the base/global SCR bits using another mechanism? + */ + scr_el3 = read_scr(); + scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT | + SCR_ST_BIT | SCR_HCE_BIT); + + if (security_state != SECURE) + scr_el3 |= SCR_NS_BIT; + + if (GET_RW(ep->spsr) == MODE_RW_64) + scr_el3 |= SCR_RW_BIT; + + if (EP_GET_ST(ep->h.attr)) + scr_el3 |= SCR_ST_BIT; + +#ifndef HANDLE_EA_EL3_FIRST + /* Explicitly stop to trap aborts from lower exception levels. */ + scr_el3 &= ~SCR_EA_BIT; +#endif + +#if IMAGE_BL31 + /* + * IRQ/FIQ bits only need setting if interrupt routing + * model has been set up for BL31. + */ + scr_el3 |= get_scr_el3_from_routing_model(security_state); +#endif + + /* + * Set up SCTLR_ELx for the target exception level: + * EE bit is taken from the entrypoint attributes + * M, C and I bits must be zero (as required by PSCI specification) + * + * The target exception level is based on the spsr mode requested. + * If execution is requested to EL2 or hyp mode, HVC is enabled + * via SCR_EL3.HCE. + * + * Always compute the SCTLR_EL1 value and save in the cpu_context + * - the EL2 registers are set up by cm_preapre_ns_entry() as they + * are not part of the stored cpu_context + * + * TODO: In debug builds the spsr should be validated and checked + * against the CPU support, security state, endianess and pc + */ + sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0; + if (GET_RW(ep->spsr) == MODE_RW_64) + sctlr_elx |= SCTLR_EL1_RES1; + else + sctlr_elx |= SCTLR_AARCH32_EL1_RES1; + write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); + + if ((GET_RW(ep->spsr) == MODE_RW_64 + && GET_EL(ep->spsr) == MODE_EL2) + || (GET_RW(ep->spsr) != MODE_RW_64 + && GET_M32(ep->spsr) == MODE32_hyp)) { + scr_el3 |= SCR_HCE_BIT; + } + + /* Populate EL3 state so that we've the right context before doing ERET */ + state = get_el3state_ctx(ctx); + write_ctx_reg(state, CTX_SCR_EL3, scr_el3); + write_ctx_reg(state, CTX_ELR_EL3, ep->pc); + write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr); + + /* + * Store the X0-X7 value from the entrypoint into the context + * Use memcpy as we are in control of the layout of the structures + */ + gp_regs = get_gpregs_ctx(ctx); + memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t)); +} + +/******************************************************************************* + * The following function initializes the cpu_context for a CPU specified by + * its `cpu_idx` for first use, and sets the initial entrypoint state as + * specified by the entry_point_info structure. + ******************************************************************************/ +void cm_init_context_by_index(unsigned int cpu_idx, + const entry_point_info_t *ep) +{ + cpu_context_t *ctx; + ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr)); + cm_init_context_common(ctx, ep); +} + +/******************************************************************************* + * The following function initializes the cpu_context for the current CPU + * for first use, and sets the initial entrypoint state as specified by the + * entry_point_info structure. + ******************************************************************************/ +void cm_init_my_context(const entry_point_info_t *ep) +{ + cpu_context_t *ctx; + ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr)); + cm_init_context_common(ctx, ep); +} + +/******************************************************************************* + * Prepare the CPU system registers for first entry into secure or normal world + * + * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized + * If execution is requested to non-secure EL1 or svc mode, and the CPU supports + * EL2 then EL2 is disabled by configuring all necessary EL2 registers. + * For all entries, the EL1 registers are initialized from the cpu_context + ******************************************************************************/ +void cm_prepare_el3_exit(uint32_t security_state) +{ + uint32_t sctlr_elx, scr_el3, cptr_el2; + cpu_context_t *ctx = cm_get_context(security_state); + + assert(ctx); + + if (security_state == NON_SECURE) { + scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3); + if (scr_el3 & SCR_HCE_BIT) { + /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */ + sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx), + CTX_SCTLR_EL1); + sctlr_elx &= ~SCTLR_EE_BIT; + sctlr_elx |= SCTLR_EL2_RES1; + write_sctlr_el2(sctlr_elx); + } else if (read_id_aa64pfr0_el1() & + (ID_AA64PFR0_ELX_MASK << ID_AA64PFR0_EL2_SHIFT)) { + /* EL2 present but unused, need to disable safely */ + + /* HCR_EL2 = 0, except RW bit set to match SCR_EL3 */ + write_hcr_el2((scr_el3 & SCR_RW_BIT) ? HCR_RW_BIT : 0); + + /* SCTLR_EL2 : can be ignored when bypassing */ + + /* CPTR_EL2 : disable all traps TCPAC, TTA, TFP */ + cptr_el2 = read_cptr_el2(); + cptr_el2 &= ~(TCPAC_BIT | TTA_BIT | TFP_BIT); + write_cptr_el2(cptr_el2); + + /* Enable EL1 access to timer */ + write_cnthctl_el2(EL1PCEN_BIT | EL1PCTEN_BIT); + + /* Reset CNTVOFF_EL2 */ + write_cntvoff_el2(0); + + /* Set VPIDR, VMPIDR to match MIDR, MPIDR */ + write_vpidr_el2(read_midr_el1()); + write_vmpidr_el2(read_mpidr_el1()); + + /* + * Reset VTTBR_EL2. + * Needed because cache maintenance operations depend on + * the VMID even when non-secure EL1&0 stage 2 address + * translation are disabled. + */ + write_vttbr_el2(0); + } + } + + el1_sysregs_context_restore(get_sysregs_ctx(ctx)); + + cm_set_next_context(ctx); +} + +/******************************************************************************* + * The next four functions are used by runtime services to save and restore + * EL1 context on the 'cpu_context' structure for the specified security + * state. + ******************************************************************************/ +void cm_el1_sysregs_context_save(uint32_t security_state) +{ + cpu_context_t *ctx; + + ctx = cm_get_context(security_state); + assert(ctx); + + el1_sysregs_context_save(get_sysregs_ctx(ctx)); +} + +void cm_el1_sysregs_context_restore(uint32_t security_state) +{ + cpu_context_t *ctx; + + ctx = cm_get_context(security_state); + assert(ctx); + + el1_sysregs_context_restore(get_sysregs_ctx(ctx)); +} + +/******************************************************************************* + * This function populates ELR_EL3 member of 'cpu_context' pertaining to the + * given security state with the given entrypoint + ******************************************************************************/ +void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint) +{ + cpu_context_t *ctx; + el3_state_t *state; + + ctx = cm_get_context(security_state); + assert(ctx); + + /* Populate EL3 state so that ERET jumps to the correct entry */ + state = get_el3state_ctx(ctx); + write_ctx_reg(state, CTX_ELR_EL3, entrypoint); +} + +/******************************************************************************* + * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context' + * pertaining to the given security state + ******************************************************************************/ +void cm_set_elr_spsr_el3(uint32_t security_state, + uintptr_t entrypoint, uint32_t spsr) +{ + cpu_context_t *ctx; + el3_state_t *state; + + ctx = cm_get_context(security_state); + assert(ctx); + + /* Populate EL3 state so that ERET jumps to the correct entry */ + state = get_el3state_ctx(ctx); + write_ctx_reg(state, CTX_ELR_EL3, entrypoint); + write_ctx_reg(state, CTX_SPSR_EL3, spsr); +} + +/******************************************************************************* + * This function updates a single bit in the SCR_EL3 member of the 'cpu_context' + * pertaining to the given security state using the value and bit position + * specified in the parameters. It preserves all other bits. + ******************************************************************************/ +void cm_write_scr_el3_bit(uint32_t security_state, + uint32_t bit_pos, + uint32_t value) +{ + cpu_context_t *ctx; + el3_state_t *state; + uint32_t scr_el3; + + ctx = cm_get_context(security_state); + assert(ctx); + + /* Ensure that the bit position is a valid one */ + assert((1 << bit_pos) & SCR_VALID_BIT_MASK); + + /* Ensure that the 'value' is only a bit wide */ + assert(value <= 1); + + /* + * Get the SCR_EL3 value from the cpu context, clear the desired bit + * and set it to its new value. + */ + state = get_el3state_ctx(ctx); + scr_el3 = read_ctx_reg(state, CTX_SCR_EL3); + scr_el3 &= ~(1 << bit_pos); + scr_el3 |= value << bit_pos; + write_ctx_reg(state, CTX_SCR_EL3, scr_el3); +} + +/******************************************************************************* + * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the + * given security state. + ******************************************************************************/ +uint32_t cm_get_scr_el3(uint32_t security_state) +{ + cpu_context_t *ctx; + el3_state_t *state; + + ctx = cm_get_context(security_state); + assert(ctx); + + /* Populate EL3 state so that ERET jumps to the correct entry */ + state = get_el3state_ctx(ctx); + return read_ctx_reg(state, CTX_SCR_EL3); +} + +/******************************************************************************* + * This function is used to program the context that's used for exception + * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for + * the required security state + ******************************************************************************/ +void cm_set_next_eret_context(uint32_t security_state) +{ + cpu_context_t *ctx; + + ctx = cm_get_context(security_state); + assert(ctx); + + cm_set_next_context(ctx); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch64/cpu_data.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch64/cpu_data.S new file mode 100644 index 0000000..2cc07ba --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/aarch64/cpu_data.S @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +.globl init_cpu_data_ptr +.globl _cpu_data_by_index + +/* ----------------------------------------------------------------- + * void init_cpu_data_ptr(void) + * + * Initialise the TPIDR_EL3 register to refer to the cpu_data_t + * for the calling CPU. This must be called before cm_get_cpu_data() + * + * This can be called without a valid stack. It assumes that + * plat_my_core_pos() does not clobber register x10. + * clobbers: x0, x1, x10 + * ----------------------------------------------------------------- + */ +func init_cpu_data_ptr + mov x10, x30 + bl plat_my_core_pos + bl _cpu_data_by_index + msr tpidr_el3, x0 + ret x10 +endfunc init_cpu_data_ptr + +/* ----------------------------------------------------------------- + * cpu_data_t *_cpu_data_by_index(uint32_t cpu_index) + * + * Return the cpu_data structure for the CPU with given linear index + * + * This can be called without a valid stack. + * clobbers: x0, x1 + * ----------------------------------------------------------------- + */ +func _cpu_data_by_index + adr x1, percpu_data + add x0, x1, x0, LSL #CPU_DATA_LOG2SIZE + ret +endfunc _cpu_data_by_index diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/cpu_data_array.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/cpu_data_array.c new file mode 100644 index 0000000..eba21a5 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/el3_runtime/cpu_data_array.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/* The per_cpu_ptr_cache_t space allocation */ +cpu_data_t percpu_data[PLATFORM_CORE_COUNT]; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt.c new file mode 100644 index 0000000..2ce6a44 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt.c @@ -0,0 +1,250 @@ +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "libfdt_env.h" + +#include +#include + +#include "libfdt_internal.h" + +int fdt_check_header(const void *fdt) +{ + if (fdt_magic(fdt) == FDT_MAGIC) { + /* Complete tree */ + if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION) + return -FDT_ERR_BADVERSION; + if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION) + return -FDT_ERR_BADVERSION; + } else if (fdt_magic(fdt) == FDT_SW_MAGIC) { + /* Unfinished sequential-write blob */ + if (fdt_size_dt_struct(fdt) == 0) + return -FDT_ERR_BADSTATE; + } else { + return -FDT_ERR_BADMAGIC; + } + + return 0; +} + +const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len) +{ + const char *p; + + if (fdt_version(fdt) >= 0x11) + if (((offset + len) < offset) + || ((offset + len) > fdt_size_dt_struct(fdt))) + return NULL; + + p = _fdt_offset_ptr(fdt, offset); + + if (p + len < p) + return NULL; + return p; +} + +uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset) +{ + const fdt32_t *tagp, *lenp; + uint32_t tag; + int offset = startoffset; + const char *p; + + *nextoffset = -FDT_ERR_TRUNCATED; + tagp = fdt_offset_ptr(fdt, offset, FDT_TAGSIZE); + if (!tagp) + return FDT_END; /* premature end */ + tag = fdt32_to_cpu(*tagp); + offset += FDT_TAGSIZE; + + *nextoffset = -FDT_ERR_BADSTRUCTURE; + switch (tag) { + case FDT_BEGIN_NODE: + /* skip name */ + do { + p = fdt_offset_ptr(fdt, offset++, 1); + } while (p && (*p != '\0')); + if (!p) + return FDT_END; /* premature end */ + break; + + case FDT_PROP: + lenp = fdt_offset_ptr(fdt, offset, sizeof(*lenp)); + if (!lenp) + return FDT_END; /* premature end */ + /* skip-name offset, length and value */ + offset += sizeof(struct fdt_property) - FDT_TAGSIZE + + fdt32_to_cpu(*lenp); + break; + + case FDT_END: + case FDT_END_NODE: + case FDT_NOP: + break; + + default: + return FDT_END; + } + + if (!fdt_offset_ptr(fdt, startoffset, offset - startoffset)) + return FDT_END; /* premature end */ + + *nextoffset = FDT_TAGALIGN(offset); + return tag; +} + +int _fdt_check_node_offset(const void *fdt, int offset) +{ + if ((offset < 0) || (offset % FDT_TAGSIZE) + || (fdt_next_tag(fdt, offset, &offset) != FDT_BEGIN_NODE)) + return -FDT_ERR_BADOFFSET; + + return offset; +} + +int _fdt_check_prop_offset(const void *fdt, int offset) +{ + if ((offset < 0) || (offset % FDT_TAGSIZE) + || (fdt_next_tag(fdt, offset, &offset) != FDT_PROP)) + return -FDT_ERR_BADOFFSET; + + return offset; +} + +int fdt_next_node(const void *fdt, int offset, int *depth) +{ + int nextoffset = 0; + uint32_t tag; + + if (offset >= 0) + if ((nextoffset = _fdt_check_node_offset(fdt, offset)) < 0) + return nextoffset; + + do { + offset = nextoffset; + tag = fdt_next_tag(fdt, offset, &nextoffset); + + switch (tag) { + case FDT_PROP: + case FDT_NOP: + break; + + case FDT_BEGIN_NODE: + if (depth) + (*depth)++; + break; + + case FDT_END_NODE: + if (depth && ((--(*depth)) < 0)) + return nextoffset; + break; + + case FDT_END: + if ((nextoffset >= 0) + || ((nextoffset == -FDT_ERR_TRUNCATED) && !depth)) + return -FDT_ERR_NOTFOUND; + else + return nextoffset; + } + } while (tag != FDT_BEGIN_NODE); + + return offset; +} + +int fdt_first_subnode(const void *fdt, int offset) +{ + int depth = 0; + + offset = fdt_next_node(fdt, offset, &depth); + if (offset < 0 || depth != 1) + return -FDT_ERR_NOTFOUND; + + return offset; +} + +int fdt_next_subnode(const void *fdt, int offset) +{ + int depth = 1; + + /* + * With respect to the parent, the depth of the next subnode will be + * the same as the last. + */ + do { + offset = fdt_next_node(fdt, offset, &depth); + if (offset < 0 || depth < 1) + return -FDT_ERR_NOTFOUND; + } while (depth > 1); + + return offset; +} + +const char *_fdt_find_string(const char *strtab, int tabsize, const char *s) +{ + int len = strlen(s) + 1; + const char *last = strtab + tabsize - len; + const char *p; + + for (p = strtab; p <= last; p++) + if (memcmp(p, s, len) == 0) + return p; + return NULL; +} + +int fdt_move(const void *fdt, void *buf, int bufsize) +{ + FDT_CHECK_HEADER(fdt); + + if (fdt_totalsize(fdt) > bufsize) + return -FDT_ERR_NOSPACE; + + memmove(buf, fdt, fdt_totalsize(fdt)); + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_addresses.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_addresses.c new file mode 100644 index 0000000..eff4dbc --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_addresses.c @@ -0,0 +1,96 @@ +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2014 David Gibson + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "libfdt_env.h" + +#include +#include + +#include "libfdt_internal.h" + +int fdt_address_cells(const void *fdt, int nodeoffset) +{ + const fdt32_t *ac; + int val; + int len; + + ac = fdt_getprop(fdt, nodeoffset, "#address-cells", &len); + if (!ac) + return 2; + + if (len != sizeof(*ac)) + return -FDT_ERR_BADNCELLS; + + val = fdt32_to_cpu(*ac); + if ((val <= 0) || (val > FDT_MAX_NCELLS)) + return -FDT_ERR_BADNCELLS; + + return val; +} + +int fdt_size_cells(const void *fdt, int nodeoffset) +{ + const fdt32_t *sc; + int val; + int len; + + sc = fdt_getprop(fdt, nodeoffset, "#size-cells", &len); + if (!sc) + return 2; + + if (len != sizeof(*sc)) + return -FDT_ERR_BADNCELLS; + + val = fdt32_to_cpu(*sc); + if ((val < 0) || (val > FDT_MAX_NCELLS)) + return -FDT_ERR_BADNCELLS; + + return val; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_empty_tree.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_empty_tree.c new file mode 100644 index 0000000..f72d13b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_empty_tree.c @@ -0,0 +1,84 @@ +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2012 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "libfdt_env.h" + +#include +#include + +#include "libfdt_internal.h" + +int fdt_create_empty_tree(void *buf, int bufsize) +{ + int err; + + err = fdt_create(buf, bufsize); + if (err) + return err; + + err = fdt_finish_reservemap(buf); + if (err) + return err; + + err = fdt_begin_node(buf, ""); + if (err) + return err; + + err = fdt_end_node(buf); + if (err) + return err; + + err = fdt_finish(buf); + if (err) + return err; + + return fdt_open_into(buf, buf, bufsize); +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_ro.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_ro.c new file mode 100644 index 0000000..50007f6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_ro.c @@ -0,0 +1,573 @@ +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "libfdt_env.h" + +#include +#include + +#include "libfdt_internal.h" + +static int _fdt_nodename_eq(const void *fdt, int offset, + const char *s, int len) +{ + const char *p = fdt_offset_ptr(fdt, offset + FDT_TAGSIZE, len+1); + + if (! p) + /* short match */ + return 0; + + if (memcmp(p, s, len) != 0) + return 0; + + if (p[len] == '\0') + return 1; + else if (!memchr(s, '@', len) && (p[len] == '@')) + return 1; + else + return 0; +} + +const char *fdt_string(const void *fdt, int stroffset) +{ + return (const char *)fdt + fdt_off_dt_strings(fdt) + stroffset; +} + +static int _fdt_string_eq(const void *fdt, int stroffset, + const char *s, int len) +{ + const char *p = fdt_string(fdt, stroffset); + + return (strlen(p) == len) && (memcmp(p, s, len) == 0); +} + +int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size) +{ + FDT_CHECK_HEADER(fdt); + *address = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->address); + *size = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->size); + return 0; +} + +int fdt_num_mem_rsv(const void *fdt) +{ + int i = 0; + + while (fdt64_to_cpu(_fdt_mem_rsv(fdt, i)->size) != 0) + i++; + return i; +} + +static int _nextprop(const void *fdt, int offset) +{ + uint32_t tag; + int nextoffset; + + do { + tag = fdt_next_tag(fdt, offset, &nextoffset); + + switch (tag) { + case FDT_END: + if (nextoffset >= 0) + return -FDT_ERR_BADSTRUCTURE; + else + return nextoffset; + + case FDT_PROP: + return offset; + } + offset = nextoffset; + } while (tag == FDT_NOP); + + return -FDT_ERR_NOTFOUND; +} + +int fdt_subnode_offset_namelen(const void *fdt, int offset, + const char *name, int namelen) +{ + int depth; + + FDT_CHECK_HEADER(fdt); + + for (depth = 0; + (offset >= 0) && (depth >= 0); + offset = fdt_next_node(fdt, offset, &depth)) + if ((depth == 1) + && _fdt_nodename_eq(fdt, offset, name, namelen)) + return offset; + + if (depth < 0) + return -FDT_ERR_NOTFOUND; + return offset; /* error */ +} + +int fdt_subnode_offset(const void *fdt, int parentoffset, + const char *name) +{ + return fdt_subnode_offset_namelen(fdt, parentoffset, name, strlen(name)); +} + +int fdt_path_offset(const void *fdt, const char *path) +{ + const char *end = path + strlen(path); + const char *p = path; + int offset = 0; + + FDT_CHECK_HEADER(fdt); + + /* see if we have an alias */ + if (*path != '/') { + const char *q = strchr(path, '/'); + + if (!q) + q = end; + + p = fdt_get_alias_namelen(fdt, p, q - p); + if (!p) + return -FDT_ERR_BADPATH; + offset = fdt_path_offset(fdt, p); + + p = q; + } + + while (*p) { + const char *q; + + while (*p == '/') + p++; + if (! *p) + return offset; + q = strchr(p, '/'); + if (! q) + q = end; + + offset = fdt_subnode_offset_namelen(fdt, offset, p, q-p); + if (offset < 0) + return offset; + + p = q; + } + + return offset; +} + +const char *fdt_get_name(const void *fdt, int nodeoffset, int *len) +{ + const struct fdt_node_header *nh = _fdt_offset_ptr(fdt, nodeoffset); + int err; + + if (((err = fdt_check_header(fdt)) != 0) + || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0)) + goto fail; + + if (len) + *len = strlen(nh->name); + + return nh->name; + + fail: + if (len) + *len = err; + return NULL; +} + +int fdt_first_property_offset(const void *fdt, int nodeoffset) +{ + int offset; + + if ((offset = _fdt_check_node_offset(fdt, nodeoffset)) < 0) + return offset; + + return _nextprop(fdt, offset); +} + +int fdt_next_property_offset(const void *fdt, int offset) +{ + if ((offset = _fdt_check_prop_offset(fdt, offset)) < 0) + return offset; + + return _nextprop(fdt, offset); +} + +const struct fdt_property *fdt_get_property_by_offset(const void *fdt, + int offset, + int *lenp) +{ + int err; + const struct fdt_property *prop; + + if ((err = _fdt_check_prop_offset(fdt, offset)) < 0) { + if (lenp) + *lenp = err; + return NULL; + } + + prop = _fdt_offset_ptr(fdt, offset); + + if (lenp) + *lenp = fdt32_to_cpu(prop->len); + + return prop; +} + +const struct fdt_property *fdt_get_property_namelen(const void *fdt, + int offset, + const char *name, + int namelen, int *lenp) +{ + for (offset = fdt_first_property_offset(fdt, offset); + (offset >= 0); + (offset = fdt_next_property_offset(fdt, offset))) { + const struct fdt_property *prop; + + if (!(prop = fdt_get_property_by_offset(fdt, offset, lenp))) { + offset = -FDT_ERR_INTERNAL; + break; + } + if (_fdt_string_eq(fdt, fdt32_to_cpu(prop->nameoff), + name, namelen)) + return prop; + } + + if (lenp) + *lenp = offset; + return NULL; +} + +const struct fdt_property *fdt_get_property(const void *fdt, + int nodeoffset, + const char *name, int *lenp) +{ + return fdt_get_property_namelen(fdt, nodeoffset, name, + strlen(name), lenp); +} + +const void *fdt_getprop_namelen(const void *fdt, int nodeoffset, + const char *name, int namelen, int *lenp) +{ + const struct fdt_property *prop; + + prop = fdt_get_property_namelen(fdt, nodeoffset, name, namelen, lenp); + if (! prop) + return NULL; + + return prop->data; +} + +const void *fdt_getprop_by_offset(const void *fdt, int offset, + const char **namep, int *lenp) +{ + const struct fdt_property *prop; + + prop = fdt_get_property_by_offset(fdt, offset, lenp); + if (!prop) + return NULL; + if (namep) + *namep = fdt_string(fdt, fdt32_to_cpu(prop->nameoff)); + return prop->data; +} + +const void *fdt_getprop(const void *fdt, int nodeoffset, + const char *name, int *lenp) +{ + return fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), lenp); +} + +uint32_t fdt_get_phandle(const void *fdt, int nodeoffset) +{ + const fdt32_t *php; + int len; + + /* FIXME: This is a bit sub-optimal, since we potentially scan + * over all the properties twice. */ + php = fdt_getprop(fdt, nodeoffset, "phandle", &len); + if (!php || (len != sizeof(*php))) { + php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len); + if (!php || (len != sizeof(*php))) + return 0; + } + + return fdt32_to_cpu(*php); +} + +const char *fdt_get_alias_namelen(const void *fdt, + const char *name, int namelen) +{ + int aliasoffset; + + aliasoffset = fdt_path_offset(fdt, "/aliases"); + if (aliasoffset < 0) + return NULL; + + return fdt_getprop_namelen(fdt, aliasoffset, name, namelen, NULL); +} + +const char *fdt_get_alias(const void *fdt, const char *name) +{ + return fdt_get_alias_namelen(fdt, name, strlen(name)); +} + +int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen) +{ + int pdepth = 0, p = 0; + int offset, depth, namelen; + const char *name; + + FDT_CHECK_HEADER(fdt); + + if (buflen < 2) + return -FDT_ERR_NOSPACE; + + for (offset = 0, depth = 0; + (offset >= 0) && (offset <= nodeoffset); + offset = fdt_next_node(fdt, offset, &depth)) { + while (pdepth > depth) { + do { + p--; + } while (buf[p-1] != '/'); + pdepth--; + } + + if (pdepth >= depth) { + name = fdt_get_name(fdt, offset, &namelen); + if (!name) + return namelen; + if ((p + namelen + 1) <= buflen) { + memcpy(buf + p, name, namelen); + p += namelen; + buf[p++] = '/'; + pdepth++; + } + } + + if (offset == nodeoffset) { + if (pdepth < (depth + 1)) + return -FDT_ERR_NOSPACE; + + if (p > 1) /* special case so that root path is "/", not "" */ + p--; + buf[p] = '\0'; + return 0; + } + } + + if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0)) + return -FDT_ERR_BADOFFSET; + else if (offset == -FDT_ERR_BADOFFSET) + return -FDT_ERR_BADSTRUCTURE; + + return offset; /* error from fdt_next_node() */ +} + +int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset, + int supernodedepth, int *nodedepth) +{ + int offset, depth; + int supernodeoffset = -FDT_ERR_INTERNAL; + + FDT_CHECK_HEADER(fdt); + + if (supernodedepth < 0) + return -FDT_ERR_NOTFOUND; + + for (offset = 0, depth = 0; + (offset >= 0) && (offset <= nodeoffset); + offset = fdt_next_node(fdt, offset, &depth)) { + if (depth == supernodedepth) + supernodeoffset = offset; + + if (offset == nodeoffset) { + if (nodedepth) + *nodedepth = depth; + + if (supernodedepth > depth) + return -FDT_ERR_NOTFOUND; + else + return supernodeoffset; + } + } + + if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0)) + return -FDT_ERR_BADOFFSET; + else if (offset == -FDT_ERR_BADOFFSET) + return -FDT_ERR_BADSTRUCTURE; + + return offset; /* error from fdt_next_node() */ +} + +int fdt_node_depth(const void *fdt, int nodeoffset) +{ + int nodedepth; + int err; + + err = fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, &nodedepth); + if (err) + return (err < 0) ? err : -FDT_ERR_INTERNAL; + return nodedepth; +} + +int fdt_parent_offset(const void *fdt, int nodeoffset) +{ + int nodedepth = fdt_node_depth(fdt, nodeoffset); + + if (nodedepth < 0) + return nodedepth; + return fdt_supernode_atdepth_offset(fdt, nodeoffset, + nodedepth - 1, NULL); +} + +int fdt_node_offset_by_prop_value(const void *fdt, int startoffset, + const char *propname, + const void *propval, int proplen) +{ + int offset; + const void *val; + int len; + + FDT_CHECK_HEADER(fdt); + + /* FIXME: The algorithm here is pretty horrible: we scan each + * property of a node in fdt_getprop(), then if that didn't + * find what we want, we scan over them again making our way + * to the next node. Still it's the easiest to implement + * approach; performance can come later. */ + for (offset = fdt_next_node(fdt, startoffset, NULL); + offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { + val = fdt_getprop(fdt, offset, propname, &len); + if (val && (len == proplen) + && (memcmp(val, propval, len) == 0)) + return offset; + } + + return offset; /* error from fdt_next_node() */ +} + +int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle) +{ + int offset; + + if ((phandle == 0) || (phandle == -1)) + return -FDT_ERR_BADPHANDLE; + + FDT_CHECK_HEADER(fdt); + + /* FIXME: The algorithm here is pretty horrible: we + * potentially scan each property of a node in + * fdt_get_phandle(), then if that didn't find what + * we want, we scan over them again making our way to the next + * node. Still it's the easiest to implement approach; + * performance can come later. */ + for (offset = fdt_next_node(fdt, -1, NULL); + offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { + if (fdt_get_phandle(fdt, offset) == phandle) + return offset; + } + + return offset; /* error from fdt_next_node() */ +} + +int fdt_stringlist_contains(const char *strlist, int listlen, const char *str) +{ + int len = strlen(str); + const char *p; + + while (listlen >= len) { + if (memcmp(str, strlist, len+1) == 0) + return 1; + p = memchr(strlist, '\0', listlen); + if (!p) + return 0; /* malformed strlist.. */ + listlen -= (p-strlist) + 1; + strlist = p + 1; + } + return 0; +} + +int fdt_node_check_compatible(const void *fdt, int nodeoffset, + const char *compatible) +{ + const void *prop; + int len; + + prop = fdt_getprop(fdt, nodeoffset, "compatible", &len); + if (!prop) + return len; + if (fdt_stringlist_contains(prop, len, compatible)) + return 0; + else + return 1; +} + +int fdt_node_offset_by_compatible(const void *fdt, int startoffset, + const char *compatible) +{ + int offset, err; + + FDT_CHECK_HEADER(fdt); + + /* FIXME: The algorithm here is pretty horrible: we scan each + * property of a node in fdt_node_check_compatible(), then if + * that didn't find what we want, we scan over them again + * making our way to the next node. Still it's the easiest to + * implement approach; performance can come later. */ + for (offset = fdt_next_node(fdt, startoffset, NULL); + offset >= 0; + offset = fdt_next_node(fdt, offset, NULL)) { + err = fdt_node_check_compatible(fdt, offset, compatible); + if ((err < 0) && (err != -FDT_ERR_NOTFOUND)) + return err; + else if (err == 0) + return offset; + } + + return offset; /* error from fdt_next_node() */ +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_rw.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_rw.c new file mode 100644 index 0000000..70adec6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_rw.c @@ -0,0 +1,492 @@ +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "libfdt_env.h" + +#include +#include + +#include "libfdt_internal.h" + +static int _fdt_blocks_misordered(const void *fdt, + int mem_rsv_size, int struct_size) +{ + return (fdt_off_mem_rsvmap(fdt) < FDT_ALIGN(sizeof(struct fdt_header), 8)) + || (fdt_off_dt_struct(fdt) < + (fdt_off_mem_rsvmap(fdt) + mem_rsv_size)) + || (fdt_off_dt_strings(fdt) < + (fdt_off_dt_struct(fdt) + struct_size)) + || (fdt_totalsize(fdt) < + (fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt))); +} + +static int _fdt_rw_check_header(void *fdt) +{ + FDT_CHECK_HEADER(fdt); + + if (fdt_version(fdt) < 17) + return -FDT_ERR_BADVERSION; + if (_fdt_blocks_misordered(fdt, sizeof(struct fdt_reserve_entry), + fdt_size_dt_struct(fdt))) + return -FDT_ERR_BADLAYOUT; + if (fdt_version(fdt) > 17) + fdt_set_version(fdt, 17); + + return 0; +} + +#define FDT_RW_CHECK_HEADER(fdt) \ + { \ + int __err; \ + if ((__err = _fdt_rw_check_header(fdt)) != 0) \ + return __err; \ + } + +static inline int _fdt_data_size(void *fdt) +{ + return fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt); +} + +static int _fdt_splice(void *fdt, void *splicepoint, int oldlen, int newlen) +{ + char *p = splicepoint; + char *end = (char *)fdt + _fdt_data_size(fdt); + + if (((p + oldlen) < p) || ((p + oldlen) > end)) + return -FDT_ERR_BADOFFSET; + if ((end - oldlen + newlen) > ((char *)fdt + fdt_totalsize(fdt))) + return -FDT_ERR_NOSPACE; + memmove(p + newlen, p + oldlen, end - p - oldlen); + return 0; +} + +static int _fdt_splice_mem_rsv(void *fdt, struct fdt_reserve_entry *p, + int oldn, int newn) +{ + int delta = (newn - oldn) * sizeof(*p); + int err; + err = _fdt_splice(fdt, p, oldn * sizeof(*p), newn * sizeof(*p)); + if (err) + return err; + fdt_set_off_dt_struct(fdt, fdt_off_dt_struct(fdt) + delta); + fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta); + return 0; +} + +static int _fdt_splice_struct(void *fdt, void *p, + int oldlen, int newlen) +{ + int delta = newlen - oldlen; + int err; + + if ((err = _fdt_splice(fdt, p, oldlen, newlen))) + return err; + + fdt_set_size_dt_struct(fdt, fdt_size_dt_struct(fdt) + delta); + fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta); + return 0; +} + +static int _fdt_splice_string(void *fdt, int newlen) +{ + void *p = (char *)fdt + + fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt); + int err; + + if ((err = _fdt_splice(fdt, p, 0, newlen))) + return err; + + fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) + newlen); + return 0; +} + +static int _fdt_find_add_string(void *fdt, const char *s) +{ + char *strtab = (char *)fdt + fdt_off_dt_strings(fdt); + const char *p; + char *new; + int len = strlen(s) + 1; + int err; + + p = _fdt_find_string(strtab, fdt_size_dt_strings(fdt), s); + if (p) + /* found it */ + return (p - strtab); + + new = strtab + fdt_size_dt_strings(fdt); + err = _fdt_splice_string(fdt, len); + if (err) + return err; + + memcpy(new, s, len); + return (new - strtab); +} + +int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size) +{ + struct fdt_reserve_entry *re; + int err; + + FDT_RW_CHECK_HEADER(fdt); + + re = _fdt_mem_rsv_w(fdt, fdt_num_mem_rsv(fdt)); + err = _fdt_splice_mem_rsv(fdt, re, 0, 1); + if (err) + return err; + + re->address = cpu_to_fdt64(address); + re->size = cpu_to_fdt64(size); + return 0; +} + +int fdt_del_mem_rsv(void *fdt, int n) +{ + struct fdt_reserve_entry *re = _fdt_mem_rsv_w(fdt, n); + int err; + + FDT_RW_CHECK_HEADER(fdt); + + if (n >= fdt_num_mem_rsv(fdt)) + return -FDT_ERR_NOTFOUND; + + err = _fdt_splice_mem_rsv(fdt, re, 1, 0); + if (err) + return err; + return 0; +} + +static int _fdt_resize_property(void *fdt, int nodeoffset, const char *name, + int len, struct fdt_property **prop) +{ + int oldlen; + int err; + + *prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen); + if (! (*prop)) + return oldlen; + + if ((err = _fdt_splice_struct(fdt, (*prop)->data, FDT_TAGALIGN(oldlen), + FDT_TAGALIGN(len)))) + return err; + + (*prop)->len = cpu_to_fdt32(len); + return 0; +} + +static int _fdt_add_property(void *fdt, int nodeoffset, const char *name, + int len, struct fdt_property **prop) +{ + int proplen; + int nextoffset; + int namestroff; + int err; + + if ((nextoffset = _fdt_check_node_offset(fdt, nodeoffset)) < 0) + return nextoffset; + + namestroff = _fdt_find_add_string(fdt, name); + if (namestroff < 0) + return namestroff; + + *prop = _fdt_offset_ptr_w(fdt, nextoffset); + proplen = sizeof(**prop) + FDT_TAGALIGN(len); + + err = _fdt_splice_struct(fdt, *prop, 0, proplen); + if (err) + return err; + + (*prop)->tag = cpu_to_fdt32(FDT_PROP); + (*prop)->nameoff = cpu_to_fdt32(namestroff); + (*prop)->len = cpu_to_fdt32(len); + return 0; +} + +int fdt_set_name(void *fdt, int nodeoffset, const char *name) +{ + char *namep; + int oldlen, newlen; + int err; + + FDT_RW_CHECK_HEADER(fdt); + + namep = (char *)(uintptr_t)fdt_get_name(fdt, nodeoffset, &oldlen); + if (!namep) + return oldlen; + + newlen = strlen(name); + + err = _fdt_splice_struct(fdt, namep, FDT_TAGALIGN(oldlen+1), + FDT_TAGALIGN(newlen+1)); + if (err) + return err; + + memcpy(namep, name, newlen+1); + return 0; +} + +int fdt_setprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len) +{ + struct fdt_property *prop; + int err; + + FDT_RW_CHECK_HEADER(fdt); + + err = _fdt_resize_property(fdt, nodeoffset, name, len, &prop); + if (err == -FDT_ERR_NOTFOUND) + err = _fdt_add_property(fdt, nodeoffset, name, len, &prop); + if (err) + return err; + + memcpy(prop->data, val, len); + return 0; +} + +int fdt_appendprop(void *fdt, int nodeoffset, const char *name, + const void *val, int len) +{ + struct fdt_property *prop; + int err, oldlen, newlen; + + FDT_RW_CHECK_HEADER(fdt); + + prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen); + if (prop) { + newlen = len + oldlen; + err = _fdt_splice_struct(fdt, prop->data, + FDT_TAGALIGN(oldlen), + FDT_TAGALIGN(newlen)); + if (err) + return err; + prop->len = cpu_to_fdt32(newlen); + memcpy(prop->data + oldlen, val, len); + } else { + err = _fdt_add_property(fdt, nodeoffset, name, len, &prop); + if (err) + return err; + memcpy(prop->data, val, len); + } + return 0; +} + +int fdt_delprop(void *fdt, int nodeoffset, const char *name) +{ + struct fdt_property *prop; + int len, proplen; + + FDT_RW_CHECK_HEADER(fdt); + + prop = fdt_get_property_w(fdt, nodeoffset, name, &len); + if (! prop) + return len; + + proplen = sizeof(*prop) + FDT_TAGALIGN(len); + return _fdt_splice_struct(fdt, prop, proplen, 0); +} + +int fdt_add_subnode_namelen(void *fdt, int parentoffset, + const char *name, int namelen) +{ + struct fdt_node_header *nh; + int offset, nextoffset; + int nodelen; + int err; + uint32_t tag; + fdt32_t *endtag; + + FDT_RW_CHECK_HEADER(fdt); + + offset = fdt_subnode_offset_namelen(fdt, parentoffset, name, namelen); + if (offset >= 0) + return -FDT_ERR_EXISTS; + else if (offset != -FDT_ERR_NOTFOUND) + return offset; + + /* Try to place the new node after the parent's properties */ + fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */ + do { + offset = nextoffset; + tag = fdt_next_tag(fdt, offset, &nextoffset); + } while ((tag == FDT_PROP) || (tag == FDT_NOP)); + + nh = _fdt_offset_ptr_w(fdt, offset); + nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE; + + err = _fdt_splice_struct(fdt, nh, 0, nodelen); + if (err) + return err; + + nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE); + memset(nh->name, 0, FDT_TAGALIGN(namelen+1)); + memcpy(nh->name, name, namelen); + endtag = (fdt32_t *)((char *)nh + nodelen - FDT_TAGSIZE); + *endtag = cpu_to_fdt32(FDT_END_NODE); + + return offset; +} + +int fdt_add_subnode(void *fdt, int parentoffset, const char *name) +{ + return fdt_add_subnode_namelen(fdt, parentoffset, name, strlen(name)); +} + +int fdt_del_node(void *fdt, int nodeoffset) +{ + int endoffset; + + FDT_RW_CHECK_HEADER(fdt); + + endoffset = _fdt_node_end_offset(fdt, nodeoffset); + if (endoffset < 0) + return endoffset; + + return _fdt_splice_struct(fdt, _fdt_offset_ptr_w(fdt, nodeoffset), + endoffset - nodeoffset, 0); +} + +static void _fdt_packblocks(const char *old, char *new, + int mem_rsv_size, int struct_size) +{ + int mem_rsv_off, struct_off, strings_off; + + mem_rsv_off = FDT_ALIGN(sizeof(struct fdt_header), 8); + struct_off = mem_rsv_off + mem_rsv_size; + strings_off = struct_off + struct_size; + + memmove(new + mem_rsv_off, old + fdt_off_mem_rsvmap(old), mem_rsv_size); + fdt_set_off_mem_rsvmap(new, mem_rsv_off); + + memmove(new + struct_off, old + fdt_off_dt_struct(old), struct_size); + fdt_set_off_dt_struct(new, struct_off); + fdt_set_size_dt_struct(new, struct_size); + + memmove(new + strings_off, old + fdt_off_dt_strings(old), + fdt_size_dt_strings(old)); + fdt_set_off_dt_strings(new, strings_off); + fdt_set_size_dt_strings(new, fdt_size_dt_strings(old)); +} + +int fdt_open_into(const void *fdt, void *buf, int bufsize) +{ + int err; + int mem_rsv_size, struct_size; + int newsize; + const char *fdtstart = fdt; + const char *fdtend = fdtstart + fdt_totalsize(fdt); + char *tmp; + + FDT_CHECK_HEADER(fdt); + + mem_rsv_size = (fdt_num_mem_rsv(fdt)+1) + * sizeof(struct fdt_reserve_entry); + + if (fdt_version(fdt) >= 17) { + struct_size = fdt_size_dt_struct(fdt); + } else { + struct_size = 0; + while (fdt_next_tag(fdt, struct_size, &struct_size) != FDT_END) + ; + if (struct_size < 0) + return struct_size; + } + + if (!_fdt_blocks_misordered(fdt, mem_rsv_size, struct_size)) { + /* no further work necessary */ + err = fdt_move(fdt, buf, bufsize); + if (err) + return err; + fdt_set_version(buf, 17); + fdt_set_size_dt_struct(buf, struct_size); + fdt_set_totalsize(buf, bufsize); + return 0; + } + + /* Need to reorder */ + newsize = FDT_ALIGN(sizeof(struct fdt_header), 8) + mem_rsv_size + + struct_size + fdt_size_dt_strings(fdt); + + if (bufsize < newsize) + return -FDT_ERR_NOSPACE; + + /* First attempt to build converted tree at beginning of buffer */ + tmp = buf; + /* But if that overlaps with the old tree... */ + if (((tmp + newsize) > fdtstart) && (tmp < fdtend)) { + /* Try right after the old tree instead */ + tmp = (char *)(uintptr_t)fdtend; + if ((tmp + newsize) > ((char *)buf + bufsize)) + return -FDT_ERR_NOSPACE; + } + + _fdt_packblocks(fdt, tmp, mem_rsv_size, struct_size); + memmove(buf, tmp, newsize); + + fdt_set_magic(buf, FDT_MAGIC); + fdt_set_totalsize(buf, bufsize); + fdt_set_version(buf, 17); + fdt_set_last_comp_version(buf, 16); + fdt_set_boot_cpuid_phys(buf, fdt_boot_cpuid_phys(fdt)); + + return 0; +} + +int fdt_pack(void *fdt) +{ + int mem_rsv_size; + + FDT_RW_CHECK_HEADER(fdt); + + mem_rsv_size = (fdt_num_mem_rsv(fdt)+1) + * sizeof(struct fdt_reserve_entry); + _fdt_packblocks(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt)); + fdt_set_totalsize(fdt, _fdt_data_size(fdt)); + + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_strerror.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_strerror.c new file mode 100644 index 0000000..e6c3cee --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_strerror.c @@ -0,0 +1,96 @@ +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "libfdt_env.h" + +#include +#include + +#include "libfdt_internal.h" + +struct fdt_errtabent { + const char *str; +}; + +#define FDT_ERRTABENT(val) \ + [(val)] = { .str = #val, } + +static struct fdt_errtabent fdt_errtable[] = { + FDT_ERRTABENT(FDT_ERR_NOTFOUND), + FDT_ERRTABENT(FDT_ERR_EXISTS), + FDT_ERRTABENT(FDT_ERR_NOSPACE), + + FDT_ERRTABENT(FDT_ERR_BADOFFSET), + FDT_ERRTABENT(FDT_ERR_BADPATH), + FDT_ERRTABENT(FDT_ERR_BADSTATE), + + FDT_ERRTABENT(FDT_ERR_TRUNCATED), + FDT_ERRTABENT(FDT_ERR_BADMAGIC), + FDT_ERRTABENT(FDT_ERR_BADVERSION), + FDT_ERRTABENT(FDT_ERR_BADSTRUCTURE), + FDT_ERRTABENT(FDT_ERR_BADLAYOUT), +}; +#define FDT_ERRTABSIZE (sizeof(fdt_errtable) / sizeof(fdt_errtable[0])) + +const char *fdt_strerror(int errval) +{ + if (errval > 0) + return ""; + else if (errval == 0) + return ""; + else if (errval > -FDT_ERRTABSIZE) { + const char *s = fdt_errtable[-errval].str; + + if (s) + return s; + } + + return ""; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_sw.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_sw.c new file mode 100644 index 0000000..6a80485 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_sw.c @@ -0,0 +1,288 @@ +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "libfdt_env.h" + +#include +#include + +#include "libfdt_internal.h" + +static int _fdt_sw_check_header(void *fdt) +{ + if (fdt_magic(fdt) != FDT_SW_MAGIC) + return -FDT_ERR_BADMAGIC; + /* FIXME: should check more details about the header state */ + return 0; +} + +#define FDT_SW_CHECK_HEADER(fdt) \ + { \ + int err; \ + if ((err = _fdt_sw_check_header(fdt)) != 0) \ + return err; \ + } + +static void *_fdt_grab_space(void *fdt, size_t len) +{ + int offset = fdt_size_dt_struct(fdt); + int spaceleft; + + spaceleft = fdt_totalsize(fdt) - fdt_off_dt_struct(fdt) + - fdt_size_dt_strings(fdt); + + if ((offset + len < offset) || (offset + len > spaceleft)) + return NULL; + + fdt_set_size_dt_struct(fdt, offset + len); + return _fdt_offset_ptr_w(fdt, offset); +} + +int fdt_create(void *buf, int bufsize) +{ + void *fdt = buf; + + if (bufsize < sizeof(struct fdt_header)) + return -FDT_ERR_NOSPACE; + + memset(buf, 0, bufsize); + + fdt_set_magic(fdt, FDT_SW_MAGIC); + fdt_set_version(fdt, FDT_LAST_SUPPORTED_VERSION); + fdt_set_last_comp_version(fdt, FDT_FIRST_SUPPORTED_VERSION); + fdt_set_totalsize(fdt, bufsize); + + fdt_set_off_mem_rsvmap(fdt, FDT_ALIGN(sizeof(struct fdt_header), + sizeof(struct fdt_reserve_entry))); + fdt_set_off_dt_struct(fdt, fdt_off_mem_rsvmap(fdt)); + fdt_set_off_dt_strings(fdt, bufsize); + + return 0; +} + +int fdt_resize(void *fdt, void *buf, int bufsize) +{ + size_t headsize, tailsize; + char *oldtail, *newtail; + + FDT_SW_CHECK_HEADER(fdt); + + headsize = fdt_off_dt_struct(fdt); + tailsize = fdt_size_dt_strings(fdt); + + if ((headsize + tailsize) > bufsize) + return -FDT_ERR_NOSPACE; + + oldtail = (char *)fdt + fdt_totalsize(fdt) - tailsize; + newtail = (char *)buf + bufsize - tailsize; + + /* Two cases to avoid clobbering data if the old and new + * buffers partially overlap */ + if (buf <= fdt) { + memmove(buf, fdt, headsize); + memmove(newtail, oldtail, tailsize); + } else { + memmove(newtail, oldtail, tailsize); + memmove(buf, fdt, headsize); + } + + fdt_set_off_dt_strings(buf, bufsize); + fdt_set_totalsize(buf, bufsize); + + return 0; +} + +int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size) +{ + struct fdt_reserve_entry *re; + int offset; + + FDT_SW_CHECK_HEADER(fdt); + + if (fdt_size_dt_struct(fdt)) + return -FDT_ERR_BADSTATE; + + offset = fdt_off_dt_struct(fdt); + if ((offset + sizeof(*re)) > fdt_totalsize(fdt)) + return -FDT_ERR_NOSPACE; + + re = (struct fdt_reserve_entry *)((char *)fdt + offset); + re->address = cpu_to_fdt64(addr); + re->size = cpu_to_fdt64(size); + + fdt_set_off_dt_struct(fdt, offset + sizeof(*re)); + + return 0; +} + +int fdt_finish_reservemap(void *fdt) +{ + return fdt_add_reservemap_entry(fdt, 0, 0); +} + +int fdt_begin_node(void *fdt, const char *name) +{ + struct fdt_node_header *nh; + int namelen = strlen(name) + 1; + + FDT_SW_CHECK_HEADER(fdt); + + nh = _fdt_grab_space(fdt, sizeof(*nh) + FDT_TAGALIGN(namelen)); + if (! nh) + return -FDT_ERR_NOSPACE; + + nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE); + memcpy(nh->name, name, namelen); + return 0; +} + +int fdt_end_node(void *fdt) +{ + fdt32_t *en; + + FDT_SW_CHECK_HEADER(fdt); + + en = _fdt_grab_space(fdt, FDT_TAGSIZE); + if (! en) + return -FDT_ERR_NOSPACE; + + *en = cpu_to_fdt32(FDT_END_NODE); + return 0; +} + +static int _fdt_find_add_string(void *fdt, const char *s) +{ + char *strtab = (char *)fdt + fdt_totalsize(fdt); + const char *p; + int strtabsize = fdt_size_dt_strings(fdt); + int len = strlen(s) + 1; + int struct_top, offset; + + p = _fdt_find_string(strtab - strtabsize, strtabsize, s); + if (p) + return p - strtab; + + /* Add it */ + offset = -strtabsize - len; + struct_top = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt); + if (fdt_totalsize(fdt) + offset < struct_top) + return 0; /* no more room :( */ + + memcpy(strtab + offset, s, len); + fdt_set_size_dt_strings(fdt, strtabsize + len); + return offset; +} + +int fdt_property(void *fdt, const char *name, const void *val, int len) +{ + struct fdt_property *prop; + int nameoff; + + FDT_SW_CHECK_HEADER(fdt); + + nameoff = _fdt_find_add_string(fdt, name); + if (nameoff == 0) + return -FDT_ERR_NOSPACE; + + prop = _fdt_grab_space(fdt, sizeof(*prop) + FDT_TAGALIGN(len)); + if (! prop) + return -FDT_ERR_NOSPACE; + + prop->tag = cpu_to_fdt32(FDT_PROP); + prop->nameoff = cpu_to_fdt32(nameoff); + prop->len = cpu_to_fdt32(len); + memcpy(prop->data, val, len); + return 0; +} + +int fdt_finish(void *fdt) +{ + char *p = (char *)fdt; + fdt32_t *end; + int oldstroffset, newstroffset; + uint32_t tag; + int offset, nextoffset; + + FDT_SW_CHECK_HEADER(fdt); + + /* Add terminator */ + end = _fdt_grab_space(fdt, sizeof(*end)); + if (! end) + return -FDT_ERR_NOSPACE; + *end = cpu_to_fdt32(FDT_END); + + /* Relocate the string table */ + oldstroffset = fdt_totalsize(fdt) - fdt_size_dt_strings(fdt); + newstroffset = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt); + memmove(p + newstroffset, p + oldstroffset, fdt_size_dt_strings(fdt)); + fdt_set_off_dt_strings(fdt, newstroffset); + + /* Walk the structure, correcting string offsets */ + offset = 0; + while ((tag = fdt_next_tag(fdt, offset, &nextoffset)) != FDT_END) { + if (tag == FDT_PROP) { + struct fdt_property *prop = + _fdt_offset_ptr_w(fdt, offset); + int nameoff; + + nameoff = fdt32_to_cpu(prop->nameoff); + nameoff += fdt_size_dt_strings(fdt); + prop->nameoff = cpu_to_fdt32(nameoff); + } + offset = nextoffset; + } + if (nextoffset < 0) + return nextoffset; + + /* Finally, adjust the header */ + fdt_set_totalsize(fdt, newstroffset + fdt_size_dt_strings(fdt)); + fdt_set_magic(fdt, FDT_MAGIC); + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_wip.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_wip.c new file mode 100644 index 0000000..c5bbb68 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/fdt_wip.c @@ -0,0 +1,118 @@ +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include "libfdt_env.h" + +#include +#include + +#include "libfdt_internal.h" + +int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name, + const void *val, int len) +{ + void *propval; + int proplen; + + propval = fdt_getprop_w(fdt, nodeoffset, name, &proplen); + if (! propval) + return proplen; + + if (proplen != len) + return -FDT_ERR_NOSPACE; + + memcpy(propval, val, len); + return 0; +} + +static void _fdt_nop_region(void *start, int len) +{ + fdt32_t *p; + + for (p = start; (char *)p < ((char *)start + len); p++) + *p = cpu_to_fdt32(FDT_NOP); +} + +int fdt_nop_property(void *fdt, int nodeoffset, const char *name) +{ + struct fdt_property *prop; + int len; + + prop = fdt_get_property_w(fdt, nodeoffset, name, &len); + if (! prop) + return len; + + _fdt_nop_region(prop, len + sizeof(*prop)); + + return 0; +} + +int _fdt_node_end_offset(void *fdt, int offset) +{ + int depth = 0; + + while ((offset >= 0) && (depth >= 0)) + offset = fdt_next_node(fdt, offset, &depth); + + return offset; +} + +int fdt_nop_node(void *fdt, int nodeoffset) +{ + int endoffset; + + endoffset = _fdt_node_end_offset(fdt, nodeoffset); + if (endoffset < 0) + return endoffset; + + _fdt_nop_region(fdt_offset_ptr_w(fdt, nodeoffset, 0), + endoffset - nodeoffset); + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/libfdt.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/libfdt.mk new file mode 100644 index 0000000..f2e8d09 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/libfdt.mk @@ -0,0 +1,41 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +LIBFDT_SRCS := $(addprefix lib/libfdt/, \ + fdt.c \ + fdt_addresses.c \ + fdt_empty_tree.c \ + fdt_ro.c \ + fdt_rw.c \ + fdt_strerror.c \ + fdt_sw.c \ + fdt_wip.c) \ + +INCLUDES += -Iinclude/lib/libfdt diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/libfdt_internal.h b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/libfdt_internal.h new file mode 100644 index 0000000..02cfa6f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/libfdt/libfdt_internal.h @@ -0,0 +1,95 @@ +#ifndef _LIBFDT_INTERNAL_H +#define _LIBFDT_INTERNAL_H +/* + * libfdt - Flat Device Tree manipulation + * Copyright (C) 2006 David Gibson, IBM Corporation. + * + * libfdt is dual licensed: you can use it either under the terms of + * the GPL, or the BSD license, at your option. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Alternatively, + * + * b) Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * 1. Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND + * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, + * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ +#include + +#define FDT_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) +#define FDT_TAGALIGN(x) (FDT_ALIGN((x), FDT_TAGSIZE)) + +#define FDT_CHECK_HEADER(fdt) \ + { \ + int __err; \ + if ((__err = fdt_check_header(fdt)) != 0) \ + return __err; \ + } + +int _fdt_check_node_offset(const void *fdt, int offset); +int _fdt_check_prop_offset(const void *fdt, int offset); +const char *_fdt_find_string(const char *strtab, int tabsize, const char *s); +int _fdt_node_end_offset(void *fdt, int nodeoffset); + +static inline const void *_fdt_offset_ptr(const void *fdt, int offset) +{ + return (const char *)fdt + fdt_off_dt_struct(fdt) + offset; +} + +static inline void *_fdt_offset_ptr_w(void *fdt, int offset) +{ + return (void *)(uintptr_t)_fdt_offset_ptr(fdt, offset); +} + +static inline const struct fdt_reserve_entry *_fdt_mem_rsv(const void *fdt, int n) +{ + const struct fdt_reserve_entry *rsv_table = + (const struct fdt_reserve_entry *) + ((const char *)fdt + fdt_off_mem_rsvmap(fdt)); + + return rsv_table + n; +} +static inline struct fdt_reserve_entry *_fdt_mem_rsv_w(void *fdt, int n) +{ + return (void *)(uintptr_t)_fdt_mem_rsv(fdt, n); +} + +#define FDT_SW_MAGIC (~FDT_MAGIC) + +#endif /* _LIBFDT_INTERNAL_H */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/bakery/bakery_lock_coherent.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/bakery/bakery_lock_coherent.c new file mode 100644 index 0000000..f221222 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/bakery/bakery_lock_coherent.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* + * Functions in this file implement Bakery Algorithm for mutual exclusion with the + * bakery lock data structures in coherent memory. + * + * ARM architecture offers a family of exclusive access instructions to + * efficiently implement mutual exclusion with hardware support. However, as + * well as depending on external hardware, the these instructions have defined + * behavior only on certain memory types (cacheable and Normal memory in + * particular; see ARMv8 Architecture Reference Manual section B2.10). Use cases + * in trusted firmware are such that mutual exclusion implementation cannot + * expect that accesses to the lock have the specific type required by the + * architecture for these primitives to function (for example, not all + * contenders may have address translation enabled). + * + * This implementation does not use mutual exclusion primitives. It expects + * memory regions where the locks reside to be fully ordered and coherent + * (either by disabling address translation, or by assigning proper attributes + * when translation is enabled). + * + * Note that the ARM architecture guarantees single-copy atomicity for aligned + * accesses regardless of status of address translation. + */ + +#define assert_bakery_entry_valid(entry, bakery) do { \ + assert(bakery); \ + assert(entry < BAKERY_LOCK_MAX_CPUS); \ +} while (0) + +/* Obtain a ticket for a given CPU */ +static unsigned int bakery_get_ticket(bakery_lock_t *bakery, unsigned int me) +{ + unsigned int my_ticket, their_ticket; + unsigned int they; + + /* Prevent recursive acquisition */ + assert(!bakery_ticket_number(bakery->lock_data[me])); + + /* + * Flag that we're busy getting our ticket. All CPUs are iterated in the + * order of their ordinal position to decide the maximum ticket value + * observed so far. Our priority is set to be greater than the maximum + * observed priority + * + * Note that it's possible that more than one contender gets the same + * ticket value. That's OK as the lock is acquired based on the priority + * value, not the ticket value alone. + */ + my_ticket = 0; + bakery->lock_data[me] = make_bakery_data(CHOOSING_TICKET, my_ticket); + for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { + their_ticket = bakery_ticket_number(bakery->lock_data[they]); + if (their_ticket > my_ticket) + my_ticket = their_ticket; + } + + /* + * Compute ticket; then signal to other contenders waiting for us to + * finish calculating our ticket value that we're done + */ + ++my_ticket; + bakery->lock_data[me] = make_bakery_data(CHOSEN_TICKET, my_ticket); + + return my_ticket; +} + + +/* + * Acquire bakery lock + * + * Contending CPUs need first obtain a non-zero ticket and then calculate + * priority value. A contending CPU iterate over all other CPUs in the platform, + * which may be contending for the same lock, in the order of their ordinal + * position (CPU0, CPU1 and so on). A non-contending CPU will have its ticket + * (and priority) value as 0. The contending CPU compares its priority with that + * of others'. The CPU with the highest priority (lowest numerical value) + * acquires the lock + */ +void bakery_lock_get(bakery_lock_t *bakery) +{ + unsigned int they, me; + unsigned int my_ticket, my_prio, their_ticket; + unsigned int their_bakery_data; + + me = plat_my_core_pos(); + + assert_bakery_entry_valid(me, bakery); + + /* Get a ticket */ + my_ticket = bakery_get_ticket(bakery, me); + + /* + * Now that we got our ticket, compute our priority value, then compare + * with that of others, and proceed to acquire the lock + */ + my_prio = PRIORITY(my_ticket, me); + for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { + if (me == they) + continue; + + /* Wait for the contender to get their ticket */ + do { + their_bakery_data = bakery->lock_data[they]; + } while (bakery_is_choosing(their_bakery_data)); + + /* + * If the other party is a contender, they'll have non-zero + * (valid) ticket value. If they do, compare priorities + */ + their_ticket = bakery_ticket_number(their_bakery_data); + if (their_ticket && (PRIORITY(their_ticket, they) < my_prio)) { + /* + * They have higher priority (lower value). Wait for + * their ticket value to change (either release the lock + * to have it dropped to 0; or drop and probably content + * again for the same lock to have an even higher value) + */ + do { + wfe(); + } while (their_ticket == + bakery_ticket_number(bakery->lock_data[they])); + } + } + /* Lock acquired */ +} + + +/* Release the lock and signal contenders */ +void bakery_lock_release(bakery_lock_t *bakery) +{ + unsigned int me = plat_my_core_pos(); + + assert_bakery_entry_valid(me, bakery); + assert(bakery_ticket_number(bakery->lock_data[me])); + + /* + * Release lock by resetting ticket. Then signal other + * waiting contenders + */ + bakery->lock_data[me] = 0; + dsb(); + sev(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/bakery/bakery_lock_normal.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/bakery/bakery_lock_normal.c new file mode 100644 index 0000000..efc1b57 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/bakery/bakery_lock_normal.c @@ -0,0 +1,230 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* + * Functions in this file implement Bakery Algorithm for mutual exclusion with the + * bakery lock data structures in cacheable and Normal memory. + * + * ARM architecture offers a family of exclusive access instructions to + * efficiently implement mutual exclusion with hardware support. However, as + * well as depending on external hardware, these instructions have defined + * behavior only on certain memory types (cacheable and Normal memory in + * particular; see ARMv8 Architecture Reference Manual section B2.10). Use cases + * in trusted firmware are such that mutual exclusion implementation cannot + * expect that accesses to the lock have the specific type required by the + * architecture for these primitives to function (for example, not all + * contenders may have address translation enabled). + * + * This implementation does not use mutual exclusion primitives. It expects + * memory regions where the locks reside to be cacheable and Normal. + * + * Note that the ARM architecture guarantees single-copy atomicity for aligned + * accesses regardless of status of address translation. + */ + +#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE +/* + * Verify that the platform defined value for the per-cpu space for bakery locks is + * a multiple of the cache line size, to prevent multiple CPUs writing to the same + * bakery lock cache line + * + * Using this value, if provided, rather than the linker generated value results in + * more efficient code + */ +CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \ + PLAT_PERCPU_BAKERY_LOCK_SIZE_not_cacheline_multiple); +#define PERCPU_BAKERY_LOCK_SIZE (PLAT_PERCPU_BAKERY_LOCK_SIZE) +#else +/* + * Use the linker defined symbol which has evaluated the size reqiurement. + * This is not as efficient as using a platform defined constant + */ +extern void *__PERCPU_BAKERY_LOCK_SIZE__; +#define PERCPU_BAKERY_LOCK_SIZE ((uintptr_t)&__PERCPU_BAKERY_LOCK_SIZE__) +#endif + +#define get_bakery_info(cpu_ix, lock) \ + (bakery_info_t *)((uintptr_t)lock + cpu_ix * PERCPU_BAKERY_LOCK_SIZE) + +#define write_cache_op(addr, cached) \ + do { \ + (cached ? dccvac((uintptr_t)addr) :\ + dcivac((uintptr_t)addr));\ + dsbish();\ + } while (0) + +#define read_cache_op(addr, cached) if (cached) \ + dccivac((uintptr_t)addr) + +static unsigned int bakery_get_ticket(bakery_lock_t *lock, + unsigned int me, int is_cached) +{ + unsigned int my_ticket, their_ticket; + unsigned int they; + bakery_info_t *my_bakery_info, *their_bakery_info; + + /* + * Obtain a reference to the bakery information for this cpu and ensure + * it is not NULL. + */ + my_bakery_info = get_bakery_info(me, lock); + assert(my_bakery_info); + + /* + * Prevent recursive acquisition. + * Since lock data is written to and cleaned by the owning cpu, it + * doesn't require any cache operations prior to reading the lock data. + */ + assert(!bakery_ticket_number(my_bakery_info->lock_data)); + + /* + * Tell other contenders that we are through the bakery doorway i.e. + * going to allocate a ticket for this cpu. + */ + my_ticket = 0; + my_bakery_info->lock_data = make_bakery_data(CHOOSING_TICKET, my_ticket); + + write_cache_op(my_bakery_info, is_cached); + + /* + * Iterate through the bakery information of each contender to allocate + * the highest ticket number for this cpu. + */ + for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { + if (me == they) + continue; + + /* + * Get a reference to the other contender's bakery info and + * ensure that a stale copy is not read. + */ + their_bakery_info = get_bakery_info(they, lock); + assert(their_bakery_info); + + read_cache_op(their_bakery_info, is_cached); + + /* + * Update this cpu's ticket number if a higher ticket number is + * seen + */ + their_ticket = bakery_ticket_number(their_bakery_info->lock_data); + if (their_ticket > my_ticket) + my_ticket = their_ticket; + } + + /* + * Compute ticket; then signal to other contenders waiting for us to + * finish calculating our ticket value that we're done + */ + ++my_ticket; + my_bakery_info->lock_data = make_bakery_data(CHOSEN_TICKET, my_ticket); + + write_cache_op(my_bakery_info, is_cached); + + return my_ticket; +} + +void bakery_lock_get(bakery_lock_t *lock) +{ + unsigned int they, me, is_cached; + unsigned int my_ticket, my_prio, their_ticket; + bakery_info_t *their_bakery_info; + unsigned int their_bakery_data; + + me = plat_my_core_pos(); + + is_cached = read_sctlr_el3() & SCTLR_C_BIT; + + /* Get a ticket */ + my_ticket = bakery_get_ticket(lock, me, is_cached); + + /* + * Now that we got our ticket, compute our priority value, then compare + * with that of others, and proceed to acquire the lock + */ + my_prio = PRIORITY(my_ticket, me); + for (they = 0; they < BAKERY_LOCK_MAX_CPUS; they++) { + if (me == they) + continue; + + /* + * Get a reference to the other contender's bakery info and + * ensure that a stale copy is not read. + */ + their_bakery_info = get_bakery_info(they, lock); + assert(their_bakery_info); + + /* Wait for the contender to get their ticket */ + do { + read_cache_op(their_bakery_info, is_cached); + their_bakery_data = their_bakery_info->lock_data; + } while (bakery_is_choosing(their_bakery_data)); + + /* + * If the other party is a contender, they'll have non-zero + * (valid) ticket value. If they do, compare priorities + */ + their_ticket = bakery_ticket_number(their_bakery_data); + if (their_ticket && (PRIORITY(their_ticket, they) < my_prio)) { + /* + * They have higher priority (lower value). Wait for + * their ticket value to change (either release the lock + * to have it dropped to 0; or drop and probably content + * again for the same lock to have an even higher value) + */ + do { + wfe(); + read_cache_op(their_bakery_info, is_cached); + } while (their_ticket + == bakery_ticket_number(their_bakery_info->lock_data)); + } + } + /* Lock acquired */ +} + +void bakery_lock_release(bakery_lock_t *lock) +{ + bakery_info_t *my_bakery_info; + unsigned int is_cached = read_sctlr_el3() & SCTLR_C_BIT; + + my_bakery_info = get_bakery_info(plat_my_core_pos(), lock); + assert(bakery_ticket_number(my_bakery_info->lock_data)); + + my_bakery_info->lock_data = 0; + write_cache_op(my_bakery_info, is_cached); + sev(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/exclusive/aarch32/spinlock.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/exclusive/aarch32/spinlock.S new file mode 100644 index 0000000..f3a2bc3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/exclusive/aarch32/spinlock.S @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + + .globl spin_lock + .globl spin_unlock + + +func spin_lock + mov r2, #1 +1: + ldrex r1, [r0] + cmp r1, #0 + wfene + strexeq r1, r2, [r0] + cmpeq r1, #0 + bne 1b + dmb + bx lr +endfunc spin_lock + + +func spin_unlock + mov r1, #0 + stl r1, [r0] + bx lr +endfunc spin_unlock diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/exclusive/aarch64/spinlock.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/exclusive/aarch64/spinlock.S new file mode 100644 index 0000000..1ca5912 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/exclusive/aarch64/spinlock.S @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + + .globl spin_lock + .globl spin_unlock + + +func spin_lock + mov w2, #1 + sevl +l1: wfe +l2: ldaxr w1, [x0] + cbnz w1, l1 + stxr w1, w2, [x0] + cbnz w1, l2 + ret +endfunc spin_lock + + +func spin_unlock + stlr wzr, [x0] + ret +endfunc spin_unlock diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/exclusive/spinlock.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/exclusive/spinlock.S new file mode 100644 index 0000000..9c945f9 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/locks/exclusive/spinlock.S @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#if !ERROR_DEPRECATED +#include "./aarch64/spinlock.S" +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/pmf/pmf_main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/pmf/pmf_main.c new file mode 100644 index 0000000..7ce1a9d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/pmf/pmf_main.c @@ -0,0 +1,280 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * The 'pmf_svc_descs' array holds the PMF service descriptors exported by + * services by placing them in the 'pmf_svc_descs' linker section. + * The 'pmf_svc_descs_indices' array holds the index of a descriptor in the + * 'pmf_svc_descs' array. The TIF[15:10] bits in the time-stamp id are used + * to get an index into the 'pmf_svc_descs_indices' array. This gives the + * index of the descriptor in the 'pmf_svc_descs' array which contains the + * service function pointers. + ******************************************************************************/ +extern uintptr_t __PMF_SVC_DESCS_START__; +extern uintptr_t __PMF_SVC_DESCS_END__; +#define PMF_SVC_DESCS_START ((uintptr_t)(&__PMF_SVC_DESCS_START__)) +#define PMF_SVC_DESCS_END ((uintptr_t)(&__PMF_SVC_DESCS_END__)) +extern void *__PERCPU_TIMESTAMP_SIZE__; +#define PMF_PERCPU_TIMESTAMP_SIZE ((uintptr_t)&__PERCPU_TIMESTAMP_SIZE__) +extern uintptr_t __PMF_TIMESTAMP_START__; +#define PMF_TIMESTAMP_ARRAY_START ((uintptr_t)&__PMF_TIMESTAMP_START__) +extern uintptr_t __PMF_TIMESTAMP_END__; +#define PMF_TIMESTAMP_ARRAY_END ((uintptr_t)&__PMF_TIMESTAMP_END__) + +#define PMF_SVC_DESCS_MAX 10 + +/* + * This is used to traverse through registered PMF services. + */ +static pmf_svc_desc_t *pmf_svc_descs; + +/* + * This array is used to store registered PMF services in sorted order. + */ +static int pmf_svc_descs_indices[PMF_SVC_DESCS_MAX]; + +/* + * This is used to track total number of successfully registered PMF services. + */ +static int pmf_num_services; + +/* + * This is the main PMF function that initialize registered + * PMF services and also sort them in ascending order. + */ +int pmf_setup(void) +{ + int rc, ii, jj = 0; + int pmf_svc_descs_num, temp_val; + + /* If no PMF services are registered then simply bail out */ + pmf_svc_descs_num = (PMF_SVC_DESCS_END - PMF_SVC_DESCS_START)/ + sizeof(pmf_svc_desc_t); + if (pmf_svc_descs_num == 0) + return 0; + + assert(pmf_svc_descs_num < PMF_SVC_DESCS_MAX); + + pmf_svc_descs = (pmf_svc_desc_t *) PMF_SVC_DESCS_START; + for (ii = 0; ii < pmf_svc_descs_num; ii++) { + + assert(pmf_svc_descs[ii].get_ts); + + /* + * Call the initialization routine for this + * PMF service, if it is defined. + */ + if (pmf_svc_descs[ii].init) { + rc = pmf_svc_descs[ii].init(); + if (rc) { + WARN("Could not initialize PMF" + "service %s - skipping \n", + pmf_svc_descs[ii].name); + continue; + } + } + + /* Update the pmf_svc_descs_indices array */ + pmf_svc_descs_indices[jj++] = ii; + } + + pmf_num_services = jj; + + /* + * Sort the successfully registered PMF services + * according to service ID + */ + for (ii = 1; ii < pmf_num_services; ii++) { + for (jj = 0; jj < (pmf_num_services - ii); jj++) { + if ((pmf_svc_descs[jj].svc_config & PMF_SVC_ID_MASK) > + (pmf_svc_descs[jj + 1].svc_config & + PMF_SVC_ID_MASK)) { + temp_val = pmf_svc_descs_indices[jj]; + pmf_svc_descs_indices[jj] = + pmf_svc_descs_indices[jj+1]; + pmf_svc_descs_indices[jj+1] = temp_val; + } + } + } + + return 0; +} + +/* + * This function implements binary search to find registered + * PMF service based on Service ID provided in `tid` argument. + */ +static pmf_svc_desc_t *get_service(unsigned int tid) +{ + int low = 0; + int mid; + int high = pmf_num_services; + unsigned int svc_id = tid & PMF_SVC_ID_MASK; + int index; + unsigned int desc_svc_id; + + if (pmf_num_services == 0) + return NULL; + + assert(pmf_svc_descs); + + do { + mid = (low + high) / 2; + index = pmf_svc_descs_indices[mid]; + + desc_svc_id = pmf_svc_descs[index].svc_config & PMF_SVC_ID_MASK; + if (svc_id < desc_svc_id) + high = mid - 1; + if (svc_id > desc_svc_id) + low = mid + 1; + } while ((svc_id != desc_svc_id) && (low <= high)); + + /* + * Make sure the Service found supports the tid range. + */ + if ((svc_id == desc_svc_id) && ((tid & PMF_TID_MASK) < + (pmf_svc_descs[index].svc_config & PMF_TID_MASK))) + return (pmf_svc_desc_t *)&pmf_svc_descs[index]; + + return NULL; +} + +/* + * This function gets the time-stamp value for the PMF services + * registered for SMC interface based on `tid` and `mpidr`. + */ +int pmf_get_timestamp_smc(unsigned int tid, + u_register_t mpidr, + unsigned int flags, + unsigned long long *ts_value) +{ + pmf_svc_desc_t *svc_desc; + assert(ts_value); + + /* Search for registered service. */ + svc_desc = get_service(tid); + + if ((svc_desc == NULL) || (plat_core_pos_by_mpidr(mpidr) < 0)) { + *ts_value = 0; + return -EINVAL; + } else { + /* Call the service time-stamp handler. */ + *ts_value = svc_desc->get_ts(tid, mpidr, flags); + return 0; + } +} + +/* + * This function can be used to dump `ts` value for given `tid`. + * Assumption is that the console is already initialized. + */ +void __pmf_dump_timestamp(unsigned int tid, unsigned long long ts) +{ + tf_printf("PMF:cpu %u tid %u ts %llu\n", + plat_my_core_pos(), tid, ts); +} + +/* + * This function calculate the address identified by + * `base_addr`, `tid` and `cpuid`. + */ +static inline uintptr_t calc_ts_addr(uintptr_t base_addr, + unsigned int tid, + unsigned int cpuid) +{ + assert(cpuid < PLATFORM_CORE_COUNT); + assert(base_addr >= PMF_TIMESTAMP_ARRAY_START); + assert(base_addr < ((PMF_TIMESTAMP_ARRAY_START + + PMF_PERCPU_TIMESTAMP_SIZE) - ((tid & PMF_TID_MASK) * + sizeof(unsigned long long)))); + + base_addr += ((cpuid * PMF_PERCPU_TIMESTAMP_SIZE) + + ((tid & PMF_TID_MASK) * sizeof(unsigned long long))); + + return base_addr; +} + +/* + * This function stores the `ts` value to the storage identified by + * `base_addr`, `tid` and current cpu id. + * Note: The timestamp addresses are cache line aligned per cpu + * and only the owning CPU would ever write into it. + */ +void __pmf_store_timestamp(uintptr_t base_addr, + unsigned int tid, + unsigned long long ts) +{ + unsigned long long *ts_addr = (unsigned long long *)calc_ts_addr(base_addr, + tid, plat_my_core_pos()); + *ts_addr = ts; +} + +/* + * This is the cached version of `pmf_store_my_timestamp` + * Note: The timestamp addresses are cache line aligned per cpu + * and only the owning CPU would ever write into it. + */ +void __pmf_store_timestamp_with_cache_maint(uintptr_t base_addr, + unsigned int tid, + unsigned long long ts) +{ + unsigned long long *ts_addr = (unsigned long long *)calc_ts_addr(base_addr, + tid, plat_my_core_pos()); + *ts_addr = ts; + flush_dcache_range((uintptr_t)ts_addr, sizeof(unsigned long long)); +} + +/* + * This function retrieves the `ts` value from the storage identified by + * `base_addr`, `tid` and `cpuid`. + * Note: The timestamp addresses are cache line aligned per cpu. + */ +unsigned long long __pmf_get_timestamp(uintptr_t base_addr, + unsigned int tid, + unsigned int cpuid, + unsigned int flags) +{ + assert(cpuid < PLATFORM_CORE_COUNT); + unsigned long long *ts_addr = (unsigned long long *)calc_ts_addr(base_addr, + tid, cpuid); + + if (flags & PMF_CACHE_MAINT) + inv_dcache_range((uintptr_t)ts_addr, sizeof(unsigned long long)); + + return *ts_addr; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/pmf/pmf_smc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/pmf/pmf_smc.c new file mode 100644 index 0000000..14190b7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/pmf/pmf_smc.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include + +/* + * This function is responsible for handling all PMF SMC calls. + */ +uintptr_t pmf_smc_handler(unsigned int smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + int rc; + unsigned long long ts_value; + + if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { + + x1 = (uint32_t)x1; + x2 = (uint32_t)x2; + x3 = (uint32_t)x3; + + switch (smc_fid) { + case PMF_SMC_GET_TIMESTAMP_32: + /* + * Return error code and the captured + * time-stamp to the caller. + * x0 --> error code. + * x1 - x2 --> time-stamp value. + */ + rc = pmf_get_timestamp_smc(x1, x2, x3, &ts_value); + SMC_RET3(handle, rc, (uint32_t)ts_value, + (uint32_t)(ts_value >> 32)); + + default: + break; + } + } else { + switch (smc_fid) { + case PMF_SMC_GET_TIMESTAMP_64: + /* + * Return error code and the captured + * time-stamp to the caller. + * x0 --> error code. + * x1 --> time-stamp value. + */ + rc = pmf_get_timestamp_smc(x1, x2, x3, &ts_value); + SMC_RET2(handle, rc, ts_value); + + default: + break; + } + } + + WARN("Unimplemented PMF Call: 0x%x \n", smc_fid); + SMC_RET1(handle, SMC_UNK); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/aarch32/psci_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/aarch32/psci_helpers.S new file mode 100644 index 0000000..36d5d7d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/aarch32/psci_helpers.S @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .globl psci_do_pwrdown_cache_maintenance + .globl psci_do_pwrup_cache_maintenance + .globl psci_power_down_wfi + +/* ----------------------------------------------------------------------- + * void psci_do_pwrdown_cache_maintenance(unsigned int power level); + * + * This function performs cache maintenance for the specified power + * level. The levels of cache affected are determined by the power + * level which is passed as the argument i.e. level 0 results + * in a flush of the L1 cache. Both the L1 and L2 caches are flushed + * for a higher power level. + * + * Additionally, this function also ensures that stack memory is correctly + * flushed out to avoid coherency issues due to a change in its memory + * attributes after the data cache is disabled. + * ----------------------------------------------------------------------- + */ +func psci_do_pwrdown_cache_maintenance + push {r4, lr} + + /* ---------------------------------------------- + * Turn OFF cache and do stack maintenance + * prior to cpu operations . This sequence is + * different from AArch64 because in AArch32 the + * assembler routines for cpu operations utilize + * the stack whereas in AArch64 it doesn't. + * ---------------------------------------------- + */ + mov r4, r0 + bl do_stack_maintenance + + /* --------------------------------------------- + * Determine how many levels of cache will be + * subject to cache maintenance. Power level + * 0 implies that only the cpu is being powered + * down. Only the L1 data cache needs to be + * flushed to the PoU in this case. For a higher + * power level we are assuming that a flush + * of L1 data and L2 unified cache is enough. + * This information should be provided by the + * platform. + * --------------------------------------------- + */ + cmp r4, #PSCI_CPU_PWR_LVL + pop {r4,lr} + + beq prepare_core_pwr_dwn + b prepare_cluster_pwr_dwn +endfunc psci_do_pwrdown_cache_maintenance + + +/* ----------------------------------------------------------------------- + * void psci_do_pwrup_cache_maintenance(void); + * + * This function performs cache maintenance after this cpu is powered up. + * Currently, this involves managing the used stack memory before turning + * on the data cache. + * ----------------------------------------------------------------------- + */ +func psci_do_pwrup_cache_maintenance + push {lr} + + /* --------------------------------------------- + * Ensure any inflight stack writes have made it + * to main memory. + * --------------------------------------------- + */ + dmb st + + /* --------------------------------------------- + * Calculate and store the size of the used + * stack memory in r1. Calculate and store the + * stack base address in r0. + * --------------------------------------------- + */ + bl plat_get_my_stack + mov r1, sp + sub r1, r0, r1 + mov r0, sp + bl inv_dcache_range + + /* --------------------------------------------- + * Enable the data cache. + * --------------------------------------------- + */ + ldcopr r0, SCTLR + orr r0, r0, #SCTLR_C_BIT + stcopr r0, SCTLR + isb + + pop {pc} +endfunc psci_do_pwrup_cache_maintenance + + /* --------------------------------------------- + * void do_stack_maintenance(void) + * Do stack maintenance by flushing the used + * stack to the main memory and invalidating the + * remainder. + * --------------------------------------------- + */ +func do_stack_maintenance + push {r4, lr} + bl plat_get_my_stack + + /* Turn off the D-cache */ + ldcopr r1, SCTLR + bic r1, #SCTLR_C_BIT + stcopr r1, SCTLR + isb + + /* --------------------------------------------- + * Calculate and store the size of the used + * stack memory in r1. + * --------------------------------------------- + */ + mov r4, r0 + mov r1, sp + sub r1, r0, r1 + mov r0, sp + bl flush_dcache_range + + /* --------------------------------------------- + * Calculate and store the size of the unused + * stack memory in r1. Calculate and store the + * stack base address in r0. + * --------------------------------------------- + */ + sub r0, r4, #PLATFORM_STACK_SIZE + sub r1, sp, r0 + bl inv_dcache_range + + pop {r4, pc} +endfunc do_stack_maintenance + +/* ----------------------------------------------------------------------- + * This function is called to indicate to the power controller that it + * is safe to power down this cpu. It should not exit the wfi and will + * be released from reset upon power up. + * ----------------------------------------------------------------------- + */ +func psci_power_down_wfi + dsb sy // ensure write buffer empty + wfi + bl plat_panic_handler +endfunc psci_power_down_wfi diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/aarch64/psci_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/aarch64/psci_helpers.S new file mode 100644 index 0000000..ff250a0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/aarch64/psci_helpers.S @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + .globl psci_do_pwrdown_cache_maintenance + .globl psci_do_pwrup_cache_maintenance + .globl psci_power_down_wfi +#if !ERROR_DEPRECATED + .globl psci_entrypoint +#endif + +/* ----------------------------------------------------------------------- + * void psci_do_pwrdown_cache_maintenance(unsigned int power level); + * + * This function performs cache maintenance for the specified power + * level. The levels of cache affected are determined by the power + * level which is passed as the argument i.e. level 0 results + * in a flush of the L1 cache. Both the L1 and L2 caches are flushed + * for a higher power level. + * + * Additionally, this function also ensures that stack memory is correctly + * flushed out to avoid coherency issues due to a change in its memory + * attributes after the data cache is disabled. + * ----------------------------------------------------------------------- + */ +func psci_do_pwrdown_cache_maintenance + stp x29, x30, [sp,#-16]! + stp x19, x20, [sp,#-16]! + + /* --------------------------------------------- + * Determine to how many levels of cache will be + * subject to cache maintenance. Power level + * 0 implies that only the cpu is being powered + * down. Only the L1 data cache needs to be + * flushed to the PoU in this case. For a higher + * power level we are assuming that a flush + * of L1 data and L2 unified cache is enough. + * This information should be provided by the + * platform. + * --------------------------------------------- + */ + cmp w0, #PSCI_CPU_PWR_LVL + b.eq do_core_pwr_dwn + bl prepare_cluster_pwr_dwn + b do_stack_maintenance + +do_core_pwr_dwn: + bl prepare_core_pwr_dwn + + /* --------------------------------------------- + * Do stack maintenance by flushing the used + * stack to the main memory and invalidating the + * remainder. + * --------------------------------------------- + */ +do_stack_maintenance: + bl plat_get_my_stack + + /* --------------------------------------------- + * Calculate and store the size of the used + * stack memory in x1. + * --------------------------------------------- + */ + mov x19, x0 + mov x1, sp + sub x1, x0, x1 + mov x0, sp + bl flush_dcache_range + + /* --------------------------------------------- + * Calculate and store the size of the unused + * stack memory in x1. Calculate and store the + * stack base address in x0. + * --------------------------------------------- + */ + sub x0, x19, #PLATFORM_STACK_SIZE + sub x1, sp, x0 + bl inv_dcache_range + + ldp x19, x20, [sp], #16 + ldp x29, x30, [sp], #16 + ret +endfunc psci_do_pwrdown_cache_maintenance + + +/* ----------------------------------------------------------------------- + * void psci_do_pwrup_cache_maintenance(void); + * + * This function performs cache maintenance after this cpu is powered up. + * Currently, this involves managing the used stack memory before turning + * on the data cache. + * ----------------------------------------------------------------------- + */ +func psci_do_pwrup_cache_maintenance + stp x29, x30, [sp,#-16]! + + /* --------------------------------------------- + * Ensure any inflight stack writes have made it + * to main memory. + * --------------------------------------------- + */ + dmb st + + /* --------------------------------------------- + * Calculate and store the size of the used + * stack memory in x1. Calculate and store the + * stack base address in x0. + * --------------------------------------------- + */ + bl plat_get_my_stack + mov x1, sp + sub x1, x0, x1 + mov x0, sp + bl inv_dcache_range + + /* --------------------------------------------- + * Enable the data cache. + * --------------------------------------------- + */ + mrs x0, sctlr_el3 + orr x0, x0, #SCTLR_C_BIT + msr sctlr_el3, x0 + isb + + ldp x29, x30, [sp], #16 + ret +endfunc psci_do_pwrup_cache_maintenance + +/* ----------------------------------------------------------------------- + * void psci_power_down_wfi(void); + * This function is called to indicate to the power controller that it + * is safe to power down this cpu. It should not exit the wfi and will + * be released from reset upon power up. + * ----------------------------------------------------------------------- + */ +func psci_power_down_wfi + dsb sy // ensure write buffer empty + wfi + bl plat_panic_handler +endfunc psci_power_down_wfi + +/* ----------------------------------------------------------------------- + * void psci_entrypoint(void); + * The deprecated entry point for PSCI on warm boot for AArch64. + * ----------------------------------------------------------------------- + */ +func_deprecated psci_entrypoint + b bl31_warm_entrypoint +endfunc_deprecated psci_entrypoint diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_common.c new file mode 100644 index 0000000..0e81865 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_common.c @@ -0,0 +1,971 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "psci_private.h" + +/* + * SPD power management operations, expected to be supplied by the registered + * SPD on successful SP initialization + */ +const spd_pm_ops_t *psci_spd_pm; + +/* + * PSCI requested local power state map. This array is used to store the local + * power states requested by a CPU for power levels from level 1 to + * PLAT_MAX_PWR_LVL. It does not store the requested local power state for power + * level 0 (PSCI_CPU_PWR_LVL) as the requested and the target power state for a + * CPU are the same. + * + * During state coordination, the platform is passed an array containing the + * local states requested for a particular non cpu power domain by each cpu + * within the domain. + * + * TODO: Dense packing of the requested states will cause cache thrashing + * when multiple power domains write to it. If we allocate the requested + * states at each power level in a cache-line aligned per-domain memory, + * the cache thrashing can be avoided. + */ +static plat_local_state_t + psci_req_local_pwr_states[PLAT_MAX_PWR_LVL][PLATFORM_CORE_COUNT]; + + +/******************************************************************************* + * Arrays that hold the platform's power domain tree information for state + * management of power domains. + * Each node in the array 'psci_non_cpu_pd_nodes' corresponds to a power domain + * which is an ancestor of a CPU power domain. + * Each node in the array 'psci_cpu_pd_nodes' corresponds to a cpu power domain + ******************************************************************************/ +non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS] +#if USE_COHERENT_MEM +__section("tzfw_coherent_mem") +#endif +; + +DEFINE_BAKERY_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); + +cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; + +/******************************************************************************* + * Pointer to functions exported by the platform to complete power mgmt. ops + ******************************************************************************/ +const plat_psci_ops_t *psci_plat_pm_ops; + +/****************************************************************************** + * Check that the maximum power level supported by the platform makes sense + *****************************************************************************/ +CASSERT(PLAT_MAX_PWR_LVL <= PSCI_MAX_PWR_LVL && \ + PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL, \ + assert_platform_max_pwrlvl_check); + +/* + * The plat_local_state used by the platform is one of these types: RUN, + * RETENTION and OFF. The platform can define further sub-states for each type + * apart from RUN. This categorization is done to verify the sanity of the + * psci_power_state passed by the platform and to print debug information. The + * categorization is done on the basis of the following conditions: + * + * 1. If (plat_local_state == 0) then the category is STATE_TYPE_RUN. + * + * 2. If (0 < plat_local_state <= PLAT_MAX_RET_STATE), then the category is + * STATE_TYPE_RETN. + * + * 3. If (plat_local_state > PLAT_MAX_RET_STATE), then the category is + * STATE_TYPE_OFF. + */ +typedef enum plat_local_state_type { + STATE_TYPE_RUN = 0, + STATE_TYPE_RETN, + STATE_TYPE_OFF +} plat_local_state_type_t; + +/* The macro used to categorize plat_local_state. */ +#define find_local_state_type(plat_local_state) \ + ((plat_local_state) ? ((plat_local_state > PLAT_MAX_RET_STATE) \ + ? STATE_TYPE_OFF : STATE_TYPE_RETN) \ + : STATE_TYPE_RUN) + +/****************************************************************************** + * Check that the maximum retention level supported by the platform is less + * than the maximum off level. + *****************************************************************************/ +CASSERT(PLAT_MAX_RET_STATE < PLAT_MAX_OFF_STATE, \ + assert_platform_max_off_and_retn_state_check); + +/****************************************************************************** + * This function ensures that the power state parameter in a CPU_SUSPEND request + * is valid. If so, it returns the requested states for each power level. + *****************************************************************************/ +int psci_validate_power_state(unsigned int power_state, + psci_power_state_t *state_info) +{ + /* Check SBZ bits in power state are zero */ + if (psci_check_power_state(power_state)) + return PSCI_E_INVALID_PARAMS; + + assert(psci_plat_pm_ops->validate_power_state); + + /* Validate the power_state using platform pm_ops */ + return psci_plat_pm_ops->validate_power_state(power_state, state_info); +} + +/****************************************************************************** + * This function retrieves the `psci_power_state_t` for system suspend from + * the platform. + *****************************************************************************/ +void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info) +{ + /* + * Assert that the required pm_ops hook is implemented to ensure that + * the capability detected during psci_setup() is valid. + */ + assert(psci_plat_pm_ops->get_sys_suspend_power_state); + + /* + * Query the platform for the power_state required for system suspend + */ + psci_plat_pm_ops->get_sys_suspend_power_state(state_info); +} + +/******************************************************************************* + * This function verifies that the all the other cores in the system have been + * turned OFF and the current CPU is the last running CPU in the system. + * Returns 1 (true) if the current CPU is the last ON CPU or 0 (false) + * otherwise. + ******************************************************************************/ +unsigned int psci_is_last_on_cpu(void) +{ + unsigned int cpu_idx, my_idx = plat_my_core_pos(); + + for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) { + if (cpu_idx == my_idx) { + assert(psci_get_aff_info_state() == AFF_STATE_ON); + continue; + } + + if (psci_get_aff_info_state_by_idx(cpu_idx) != AFF_STATE_OFF) + return 0; + } + + return 1; +} + +/******************************************************************************* + * Routine to return the maximum power level to traverse to after a cpu has + * been physically powered up. It is expected to be called immediately after + * reset from assembler code. + ******************************************************************************/ +static unsigned int get_power_on_target_pwrlvl(void) +{ + unsigned int pwrlvl; + + /* + * Assume that this cpu was suspended and retrieve its target power + * level. If it is invalid then it could only have been turned off + * earlier. PLAT_MAX_PWR_LVL will be the highest power level a + * cpu can be turned off to. + */ + pwrlvl = psci_get_suspend_pwrlvl(); + if (pwrlvl == PSCI_INVALID_PWR_LVL) + pwrlvl = PLAT_MAX_PWR_LVL; + return pwrlvl; +} + +/****************************************************************************** + * Helper function to update the requested local power state array. This array + * does not store the requested state for the CPU power level. Hence an + * assertion is added to prevent us from accessing the wrong index. + *****************************************************************************/ +static void psci_set_req_local_pwr_state(unsigned int pwrlvl, + unsigned int cpu_idx, + plat_local_state_t req_pwr_state) +{ + assert(pwrlvl > PSCI_CPU_PWR_LVL); + psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state; +} + +/****************************************************************************** + * This function initializes the psci_req_local_pwr_states. + *****************************************************************************/ +void psci_init_req_local_pwr_states(void) +{ + /* Initialize the requested state of all non CPU power domains as OFF */ + memset(&psci_req_local_pwr_states, PLAT_MAX_OFF_STATE, + sizeof(psci_req_local_pwr_states)); +} + +/****************************************************************************** + * Helper function to return a reference to an array containing the local power + * states requested by each cpu for a power domain at 'pwrlvl'. The size of the + * array will be the number of cpu power domains of which this power domain is + * an ancestor. These requested states will be used to determine a suitable + * target state for this power domain during psci state coordination. An + * assertion is added to prevent us from accessing the CPU power level. + *****************************************************************************/ +static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl, + unsigned int cpu_idx) +{ + assert(pwrlvl > PSCI_CPU_PWR_LVL); + + return &psci_req_local_pwr_states[pwrlvl - 1][cpu_idx]; +} + +/****************************************************************************** + * Helper function to return the current local power state of each power domain + * from the current cpu power domain to its ancestor at the 'end_pwrlvl'. This + * function will be called after a cpu is powered on to find the local state + * each power domain has emerged from. + *****************************************************************************/ +void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, + psci_power_state_t *target_state) +{ + unsigned int parent_idx, lvl; + plat_local_state_t *pd_state = target_state->pwr_domain_state; + + pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state(); + parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node; + + /* Copy the local power state from node to state_info */ + for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { +#if !USE_COHERENT_MEM + /* + * If using normal memory for psci_non_cpu_pd_nodes, we need + * to flush before reading the local power state as another + * cpu in the same power domain could have updated it and this + * code runs before caches are enabled. + */ + flush_dcache_range( + (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], + sizeof(psci_non_cpu_pd_nodes[parent_idx])); +#endif + pd_state[lvl] = psci_non_cpu_pd_nodes[parent_idx].local_state; + parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; + } + + /* Set the the higher levels to RUN */ + for (; lvl <= PLAT_MAX_PWR_LVL; lvl++) + target_state->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; +} + +/****************************************************************************** + * Helper function to set the target local power state that each power domain + * from the current cpu power domain to its ancestor at the 'end_pwrlvl' will + * enter. This function will be called after coordination of requested power + * states has been done for each power level. + *****************************************************************************/ +static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl, + const psci_power_state_t *target_state) +{ + unsigned int parent_idx, lvl; + const plat_local_state_t *pd_state = target_state->pwr_domain_state; + + psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]); + + /* + * Need to flush as local_state will be accessed with Data Cache + * disabled during power on + */ + flush_cpu_data(psci_svc_cpu_data.local_state); + + parent_idx = psci_cpu_pd_nodes[plat_my_core_pos()].parent_node; + + /* Copy the local_state from state_info */ + for (lvl = 1; lvl <= end_pwrlvl; lvl++) { + psci_non_cpu_pd_nodes[parent_idx].local_state = pd_state[lvl]; +#if !USE_COHERENT_MEM + flush_dcache_range( + (uintptr_t)&psci_non_cpu_pd_nodes[parent_idx], + sizeof(psci_non_cpu_pd_nodes[parent_idx])); +#endif + parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; + } +} + + +/******************************************************************************* + * PSCI helper function to get the parent nodes corresponding to a cpu_index. + ******************************************************************************/ +void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, + unsigned int end_lvl, + unsigned int node_index[]) +{ + unsigned int parent_node = psci_cpu_pd_nodes[cpu_idx].parent_node; + int i; + + for (i = PSCI_CPU_PWR_LVL + 1; i <= end_lvl; i++) { + *node_index++ = parent_node; + parent_node = psci_non_cpu_pd_nodes[parent_node].parent_node; + } +} + +/****************************************************************************** + * This function is invoked post CPU power up and initialization. It sets the + * affinity info state, target power state and requested power state for the + * current CPU and all its ancestor power domains to RUN. + *****************************************************************************/ +void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl) +{ + unsigned int parent_idx, cpu_idx = plat_my_core_pos(), lvl; + parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; + + /* Reset the local_state to RUN for the non cpu power domains. */ + for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { + psci_non_cpu_pd_nodes[parent_idx].local_state = + PSCI_LOCAL_STATE_RUN; +#if !USE_COHERENT_MEM + flush_dcache_range( + (uintptr_t) &psci_non_cpu_pd_nodes[parent_idx], + sizeof(psci_non_cpu_pd_nodes[parent_idx])); +#endif + psci_set_req_local_pwr_state(lvl, + cpu_idx, + PSCI_LOCAL_STATE_RUN); + parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; + } + + /* Set the affinity info state to ON */ + psci_set_aff_info_state(AFF_STATE_ON); + + psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); + flush_cpu_data(psci_svc_cpu_data); +} + +/****************************************************************************** + * This function is passed the local power states requested for each power + * domain (state_info) between the current CPU domain and its ancestors until + * the target power level (end_pwrlvl). It updates the array of requested power + * states with this information. + * + * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it + * retrieves the states requested by all the cpus of which the power domain at + * that level is an ancestor. It passes this information to the platform to + * coordinate and return the target power state. If the target state for a level + * is RUN then subsequent levels are not considered. At the CPU level, state + * coordination is not required. Hence, the requested and the target states are + * the same. + * + * The 'state_info' is updated with the target state for each level between the + * CPU and the 'end_pwrlvl' and returned to the caller. + * + * This function will only be invoked with data cache enabled and while + * powering down a core. + *****************************************************************************/ +void psci_do_state_coordination(unsigned int end_pwrlvl, + psci_power_state_t *state_info) +{ + unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos(); + unsigned int start_idx, ncpus; + plat_local_state_t target_state, *req_states; + + assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); + parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; + + /* For level 0, the requested state will be equivalent + to target state */ + for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { + + /* First update the requested power state */ + psci_set_req_local_pwr_state(lvl, cpu_idx, + state_info->pwr_domain_state[lvl]); + + /* Get the requested power states for this power level */ + start_idx = psci_non_cpu_pd_nodes[parent_idx].cpu_start_idx; + req_states = psci_get_req_local_pwr_states(lvl, start_idx); + + /* + * Let the platform coordinate amongst the requested states at + * this power level and return the target local power state. + */ + ncpus = psci_non_cpu_pd_nodes[parent_idx].ncpus; + target_state = plat_get_target_pwr_state(lvl, + req_states, + ncpus); + + state_info->pwr_domain_state[lvl] = target_state; + + /* Break early if the negotiated target power state is RUN */ + if (is_local_state_run(state_info->pwr_domain_state[lvl])) + break; + + parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; + } + + /* + * This is for cases when we break out of the above loop early because + * the target power state is RUN at a power level < end_pwlvl. + * We update the requested power state from state_info and then + * set the target state as RUN. + */ + for (lvl = lvl + 1; lvl <= end_pwrlvl; lvl++) { + psci_set_req_local_pwr_state(lvl, cpu_idx, + state_info->pwr_domain_state[lvl]); + state_info->pwr_domain_state[lvl] = PSCI_LOCAL_STATE_RUN; + + } + + /* Update the target state in the power domain nodes */ + psci_set_target_local_pwr_states(end_pwrlvl, state_info); +} + +/****************************************************************************** + * This function validates a suspend request by making sure that if a standby + * state is requested then no power level is turned off and the highest power + * level is placed in a standby/retention state. + * + * It also ensures that the state level X will enter is not shallower than the + * state level X + 1 will enter. + * + * This validation will be enabled only for DEBUG builds as the platform is + * expected to perform these validations as well. + *****************************************************************************/ +int psci_validate_suspend_req(const psci_power_state_t *state_info, + unsigned int is_power_down_state) +{ + unsigned int max_off_lvl, target_lvl, max_retn_lvl; + plat_local_state_t state; + plat_local_state_type_t req_state_type, deepest_state_type; + int i; + + /* Find the target suspend power level */ + target_lvl = psci_find_target_suspend_lvl(state_info); + if (target_lvl == PSCI_INVALID_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + /* All power domain levels are in a RUN state to begin with */ + deepest_state_type = STATE_TYPE_RUN; + + for (i = target_lvl; i >= PSCI_CPU_PWR_LVL; i--) { + state = state_info->pwr_domain_state[i]; + req_state_type = find_local_state_type(state); + + /* + * While traversing from the highest power level to the lowest, + * the state requested for lower levels has to be the same or + * deeper i.e. equal to or greater than the state at the higher + * levels. If this condition is true, then the requested state + * becomes the deepest state encountered so far. + */ + if (req_state_type < deepest_state_type) + return PSCI_E_INVALID_PARAMS; + deepest_state_type = req_state_type; + } + + /* Find the highest off power level */ + max_off_lvl = psci_find_max_off_lvl(state_info); + + /* The target_lvl is either equal to the max_off_lvl or max_retn_lvl */ + max_retn_lvl = PSCI_INVALID_PWR_LVL; + if (target_lvl != max_off_lvl) + max_retn_lvl = target_lvl; + + /* + * If this is not a request for a power down state then max off level + * has to be invalid and max retention level has to be a valid power + * level. + */ + if (!is_power_down_state && (max_off_lvl != PSCI_INVALID_PWR_LVL || + max_retn_lvl == PSCI_INVALID_PWR_LVL)) + return PSCI_E_INVALID_PARAMS; + + return PSCI_E_SUCCESS; +} + +/****************************************************************************** + * This function finds the highest power level which will be powered down + * amongst all the power levels specified in the 'state_info' structure + *****************************************************************************/ +unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info) +{ + int i; + + for (i = PLAT_MAX_PWR_LVL; i >= PSCI_CPU_PWR_LVL; i--) { + if (is_local_state_off(state_info->pwr_domain_state[i])) + return i; + } + + return PSCI_INVALID_PWR_LVL; +} + +/****************************************************************************** + * This functions finds the level of the highest power domain which will be + * placed in a low power state during a suspend operation. + *****************************************************************************/ +unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info) +{ + int i; + + for (i = PLAT_MAX_PWR_LVL; i >= PSCI_CPU_PWR_LVL; i--) { + if (!is_local_state_run(state_info->pwr_domain_state[i])) + return i; + } + + return PSCI_INVALID_PWR_LVL; +} + +/******************************************************************************* + * This function is passed a cpu_index and the highest level in the topology + * tree that the operation should be applied to. It picks up locks in order of + * increasing power domain level in the range specified. + ******************************************************************************/ +void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, + unsigned int cpu_idx) +{ + unsigned int parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; + unsigned int level; + + /* No locking required for level 0. Hence start locking from level 1 */ + for (level = PSCI_CPU_PWR_LVL + 1; level <= end_pwrlvl; level++) { + psci_lock_get(&psci_non_cpu_pd_nodes[parent_idx]); + parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; + } +} + +/******************************************************************************* + * This function is passed a cpu_index and the highest level in the topology + * tree that the operation should be applied to. It releases the locks in order + * of decreasing power domain level in the range specified. + ******************************************************************************/ +void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, + unsigned int cpu_idx) +{ + unsigned int parent_idx, parent_nodes[PLAT_MAX_PWR_LVL] = {0}; + int level; + + /* Get the parent nodes */ + psci_get_parent_pwr_domain_nodes(cpu_idx, end_pwrlvl, parent_nodes); + + /* Unlock top down. No unlocking required for level 0. */ + for (level = end_pwrlvl; level >= PSCI_CPU_PWR_LVL + 1; level--) { + parent_idx = parent_nodes[level - 1]; + psci_lock_release(&psci_non_cpu_pd_nodes[parent_idx]); + } +} + +/******************************************************************************* + * Simple routine to determine whether a mpidr is valid or not. + ******************************************************************************/ +int psci_validate_mpidr(u_register_t mpidr) +{ + if (plat_core_pos_by_mpidr(mpidr) < 0) + return PSCI_E_INVALID_PARAMS; + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * This function determines the full entrypoint information for the requested + * PSCI entrypoint on power on/resume and returns it. + ******************************************************************************/ +#ifdef AARCH32 +static int psci_get_ns_ep_info(entry_point_info_t *ep, + uintptr_t entrypoint, + u_register_t context_id) +{ + u_register_t ep_attr; + unsigned int aif, ee, mode; + u_register_t scr = read_scr(); + u_register_t ns_sctlr, sctlr; + + /* Switch to non secure state */ + write_scr(scr | SCR_NS_BIT); + isb(); + ns_sctlr = read_sctlr(); + + sctlr = scr & SCR_HCE_BIT ? read_hsctlr() : ns_sctlr; + + /* Return to original state */ + write_scr(scr); + isb(); + ee = 0; + + ep_attr = NON_SECURE | EP_ST_DISABLE; + if (sctlr & SCTLR_EE_BIT) { + ep_attr |= EP_EE_BIG; + ee = 1; + } + SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); + + ep->pc = entrypoint; + memset(&ep->args, 0, sizeof(ep->args)); + ep->args.arg0 = context_id; + + mode = scr & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; + + /* + * TODO: Choose async. exception bits if HYP mode is not + * implemented according to the values of SCR.{AW, FW} bits + */ + aif = SPSR_ABT_BIT | SPSR_IRQ_BIT | SPSR_FIQ_BIT; + + ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, aif); + + return PSCI_E_SUCCESS; +} + +#else +static int psci_get_ns_ep_info(entry_point_info_t *ep, + uintptr_t entrypoint, + u_register_t context_id) +{ + u_register_t ep_attr, sctlr; + unsigned int daif, ee, mode; + u_register_t ns_scr_el3 = read_scr_el3(); + u_register_t ns_sctlr_el1 = read_sctlr_el1(); + + sctlr = ns_scr_el3 & SCR_HCE_BIT ? read_sctlr_el2() : ns_sctlr_el1; + ee = 0; + + ep_attr = NON_SECURE | EP_ST_DISABLE; + if (sctlr & SCTLR_EE_BIT) { + ep_attr |= EP_EE_BIG; + ee = 1; + } + SET_PARAM_HEAD(ep, PARAM_EP, VERSION_1, ep_attr); + + ep->pc = entrypoint; + memset(&ep->args, 0, sizeof(ep->args)); + ep->args.arg0 = context_id; + + /* + * Figure out whether the cpu enters the non-secure address space + * in aarch32 or aarch64 + */ + if (ns_scr_el3 & SCR_RW_BIT) { + + /* + * Check whether a Thumb entry point has been provided for an + * aarch64 EL + */ + if (entrypoint & 0x1) + return PSCI_E_INVALID_ADDRESS; + + mode = ns_scr_el3 & SCR_HCE_BIT ? MODE_EL2 : MODE_EL1; + + ep->spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + } else { + + mode = ns_scr_el3 & SCR_HCE_BIT ? MODE32_hyp : MODE32_svc; + + /* + * TODO: Choose async. exception bits if HYP mode is not + * implemented according to the values of SCR.{AW, FW} bits + */ + daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT; + + ep->spsr = SPSR_MODE32(mode, entrypoint & 0x1, ee, daif); + } + + return PSCI_E_SUCCESS; +} +#endif + +/******************************************************************************* + * This function validates the entrypoint with the platform layer if the + * appropriate pm_ops hook is exported by the platform and returns the + * 'entry_point_info'. + ******************************************************************************/ +int psci_validate_entry_point(entry_point_info_t *ep, + uintptr_t entrypoint, + u_register_t context_id) +{ + int rc; + + /* Validate the entrypoint using platform psci_ops */ + if (psci_plat_pm_ops->validate_ns_entrypoint) { + rc = psci_plat_pm_ops->validate_ns_entrypoint(entrypoint); + if (rc != PSCI_E_SUCCESS) + return PSCI_E_INVALID_ADDRESS; + } + + /* + * Verify and derive the re-entry information for + * the non-secure world from the non-secure state from + * where this call originated. + */ + rc = psci_get_ns_ep_info(ep, entrypoint, context_id); + return rc; +} + +/******************************************************************************* + * Generic handler which is called when a cpu is physically powered on. It + * traverses the node information and finds the highest power level powered + * off and performs generic, architectural, platform setup and state management + * to power on that power level and power levels below it. + * e.g. For a cpu that's been powered on, it will call the platform specific + * code to enable the gic cpu interface and for a cluster it will enable + * coherency at the interconnect level in addition to gic cpu interface. + ******************************************************************************/ +void psci_warmboot_entrypoint(void) +{ + unsigned int end_pwrlvl, cpu_idx = plat_my_core_pos(); + psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; + + /* + * Verify that we have been explicitly turned ON or resumed from + * suspend. + */ + if (psci_get_aff_info_state() == AFF_STATE_OFF) { + ERROR("Unexpected affinity info state"); + panic(); + } + + /* + * Get the maximum power domain level to traverse to after this cpu + * has been physically powered up. + */ + end_pwrlvl = get_power_on_target_pwrlvl(); + + /* + * This function acquires the lock corresponding to each power level so + * that by the time all locks are taken, the system topology is snapshot + * and state management can be done safely. + */ + psci_acquire_pwr_domain_locks(end_pwrlvl, + cpu_idx); + +#if ENABLE_PSCI_STAT + /* + * Capture power up time-stamp. + * No cache maintenance is required as caches are off + * and writes are direct to the main memory. + */ + PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR, + PMF_NO_CACHE_MAINT); +#endif + + psci_get_target_local_pwr_states(end_pwrlvl, &state_info); + + /* + * This CPU could be resuming from suspend or it could have just been + * turned on. To distinguish between these 2 cases, we examine the + * affinity state of the CPU: + * - If the affinity state is ON_PENDING then it has just been + * turned on. + * - Else it is resuming from suspend. + * + * Depending on the type of warm reset identified, choose the right set + * of power management handler and perform the generic, architecture + * and platform specific handling. + */ + if (psci_get_aff_info_state() == AFF_STATE_ON_PENDING) + psci_cpu_on_finish(cpu_idx, &state_info); + else + psci_cpu_suspend_finish(cpu_idx, &state_info); + + /* + * Set the requested and target state of this CPU and all the higher + * power domains which are ancestors of this CPU to run. + */ + psci_set_pwr_domains_to_run(end_pwrlvl); + +#if ENABLE_PSCI_STAT + /* + * Update PSCI stats. + * Caches are off when writing stats data on the power down path. + * Since caches are now enabled, it's necessary to do cache + * maintenance before reading that same data. + */ + psci_stats_update_pwr_up(end_pwrlvl, &state_info, PMF_CACHE_MAINT); +#endif + + /* + * This loop releases the lock corresponding to each power level + * in the reverse order to which they were acquired. + */ + psci_release_pwr_domain_locks(end_pwrlvl, + cpu_idx); +} + +/******************************************************************************* + * This function initializes the set of hooks that PSCI invokes as part of power + * management operation. The power management hooks are expected to be provided + * by the SPD, after it finishes all its initialization + ******************************************************************************/ +void psci_register_spd_pm_hook(const spd_pm_ops_t *pm) +{ + assert(pm); + psci_spd_pm = pm; + + if (pm->svc_migrate) + psci_caps |= define_psci_cap(PSCI_MIG_AARCH64); + + if (pm->svc_migrate_info) + psci_caps |= define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) + | define_psci_cap(PSCI_MIG_INFO_TYPE); +} + +/******************************************************************************* + * This function invokes the migrate info hook in the spd_pm_ops. It performs + * the necessary return value validation. If the Secure Payload is UP and + * migrate capable, it returns the mpidr of the CPU on which the Secure payload + * is resident through the mpidr parameter. Else the value of the parameter on + * return is undefined. + ******************************************************************************/ +int psci_spd_migrate_info(u_register_t *mpidr) +{ + int rc; + + rc = (int)bl31_plat_cpu_migrate_info(mpidr); + + return rc; +} + + +/******************************************************************************* + * This function prints the state of all power domains present in the + * system + ******************************************************************************/ +void psci_print_power_domain_map(void) +{ +#if LOG_LEVEL >= LOG_LEVEL_INFO + unsigned int idx; + plat_local_state_t state; + plat_local_state_type_t state_type; + + /* This array maps to the PSCI_STATE_X definitions in psci.h */ + static const char * const psci_state_type_str[] = { + "ON", + "RETENTION", + "OFF", + }; + + INFO("PSCI Power Domain Map:\n"); + for (idx = 0; idx < (PSCI_NUM_PWR_DOMAINS - PLATFORM_CORE_COUNT); + idx++) { + state_type = find_local_state_type( + psci_non_cpu_pd_nodes[idx].local_state); + INFO(" Domain Node : Level %u, parent_node %d," + " State %s (0x%x)\n", + psci_non_cpu_pd_nodes[idx].level, + psci_non_cpu_pd_nodes[idx].parent_node, + psci_state_type_str[state_type], + psci_non_cpu_pd_nodes[idx].local_state); + } + + for (idx = 0; idx < PLATFORM_CORE_COUNT; idx++) { + state = psci_get_cpu_local_state_by_idx(idx); + state_type = find_local_state_type(state); + INFO(" CPU Node : MPID 0x%llx, parent_node %d," + " State %s (0x%x)\n", + (unsigned long long)psci_cpu_pd_nodes[idx].mpidr, + psci_cpu_pd_nodes[idx].parent_node, + psci_state_type_str[state_type], + psci_get_cpu_local_state_by_idx(idx)); + } +#endif +} + +#if ENABLE_PLAT_COMPAT +/******************************************************************************* + * PSCI Compatibility helper function to return the 'power_state' parameter of + * the PSCI CPU SUSPEND request for the current CPU. Returns PSCI_INVALID_DATA + * if not invoked within CPU_SUSPEND for the current CPU. + ******************************************************************************/ +int psci_get_suspend_powerstate(void) +{ + /* Sanity check to verify that CPU is within CPU_SUSPEND */ + if (psci_get_aff_info_state() == AFF_STATE_ON && + !is_local_state_run(psci_get_cpu_local_state())) + return psci_power_state_compat[plat_my_core_pos()]; + + return PSCI_INVALID_DATA; +} + +/******************************************************************************* + * PSCI Compatibility helper function to return the state id of the current + * cpu encoded in the 'power_state' parameter. Returns PSCI_INVALID_DATA + * if not invoked within CPU_SUSPEND for the current CPU. + ******************************************************************************/ +int psci_get_suspend_stateid(void) +{ + unsigned int power_state; + power_state = psci_get_suspend_powerstate(); + if (power_state != PSCI_INVALID_DATA) + return psci_get_pstate_id(power_state); + + return PSCI_INVALID_DATA; +} + +/******************************************************************************* + * PSCI Compatibility helper function to return the state id encoded in the + * 'power_state' parameter of the CPU specified by 'mpidr'. Returns + * PSCI_INVALID_DATA if the CPU is not in CPU_SUSPEND. + ******************************************************************************/ +int psci_get_suspend_stateid_by_mpidr(unsigned long mpidr) +{ + int cpu_idx = plat_core_pos_by_mpidr(mpidr); + + if (cpu_idx == -1) + return PSCI_INVALID_DATA; + + /* Sanity check to verify that the CPU is in CPU_SUSPEND */ + if (psci_get_aff_info_state_by_idx(cpu_idx) == AFF_STATE_ON && + !is_local_state_run(psci_get_cpu_local_state_by_idx(cpu_idx))) + return psci_get_pstate_id(psci_power_state_compat[cpu_idx]); + + return PSCI_INVALID_DATA; +} + +/******************************************************************************* + * This function returns highest affinity level which is in OFF + * state. The affinity instance with which the level is associated is + * determined by the caller. + ******************************************************************************/ +unsigned int psci_get_max_phys_off_afflvl(void) +{ + psci_power_state_t state_info; + + memset(&state_info, 0, sizeof(state_info)); + psci_get_target_local_pwr_states(PLAT_MAX_PWR_LVL, &state_info); + + return psci_find_target_suspend_lvl(&state_info); +} + +/******************************************************************************* + * PSCI Compatibility helper function to return target affinity level requested + * for the CPU_SUSPEND. This function assumes affinity levels correspond to + * power domain levels on the platform. + ******************************************************************************/ +int psci_get_suspend_afflvl(void) +{ + return psci_get_suspend_pwrlvl(); +} + +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_lib.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_lib.mk new file mode 100644 index 0000000..8daa831 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_lib.mk @@ -0,0 +1,57 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +PSCI_LIB_SOURCES := lib/el3_runtime/cpu_data_array.c \ + lib/el3_runtime/${ARCH}/cpu_data.S \ + lib/el3_runtime/${ARCH}/context_mgmt.c \ + lib/cpus/${ARCH}/cpu_helpers.S \ + lib/locks/exclusive/${ARCH}/spinlock.S \ + lib/psci/psci_off.c \ + lib/psci/psci_on.c \ + lib/psci/psci_suspend.c \ + lib/psci/psci_common.c \ + lib/psci/psci_main.c \ + lib/psci/psci_setup.c \ + lib/psci/psci_system_off.c \ + lib/psci/${ARCH}/psci_helpers.S + +ifeq (${ARCH}, aarch64) +PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S +endif + +ifeq (${USE_COHERENT_MEM}, 1) +PSCI_LIB_SOURCES += lib/locks/bakery/bakery_lock_coherent.c +else +PSCI_LIB_SOURCES += lib/locks/bakery/bakery_lock_normal.c +endif + +ifeq (${ENABLE_PSCI_STAT}, 1) +PSCI_LIB_SOURCES += lib/psci/psci_stat.c +endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_main.c new file mode 100644 index 0000000..15f4747 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_main.c @@ -0,0 +1,479 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "psci_private.h" + +/******************************************************************************* + * PSCI frontend api for servicing SMCs. Described in the PSCI spec. + ******************************************************************************/ +int psci_cpu_on(u_register_t target_cpu, + uintptr_t entrypoint, + u_register_t context_id) + +{ + int rc; + entry_point_info_t ep; + + /* Determine if the cpu exists of not */ + rc = psci_validate_mpidr(target_cpu); + if (rc != PSCI_E_SUCCESS) + return PSCI_E_INVALID_PARAMS; + + /* Validate the entry point and get the entry_point_info */ + rc = psci_validate_entry_point(&ep, entrypoint, context_id); + if (rc != PSCI_E_SUCCESS) + return rc; + + /* + * To turn this cpu on, specify which power + * levels need to be turned on + */ + return psci_cpu_on_start(target_cpu, &ep); +} + +unsigned int psci_version(void) +{ + return PSCI_MAJOR_VER | PSCI_MINOR_VER; +} + +int psci_cpu_suspend(unsigned int power_state, + uintptr_t entrypoint, + u_register_t context_id) +{ + int rc; + unsigned int target_pwrlvl, is_power_down_state; + entry_point_info_t ep; + psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; + plat_local_state_t cpu_pd_state; + + /* Validate the power_state parameter */ + rc = psci_validate_power_state(power_state, &state_info); + if (rc != PSCI_E_SUCCESS) { + assert(rc == PSCI_E_INVALID_PARAMS); + return rc; + } + + /* + * Get the value of the state type bit from the power state parameter. + */ + is_power_down_state = psci_get_pstate_type(power_state); + + /* Sanity check the requested suspend levels */ + assert(psci_validate_suspend_req(&state_info, is_power_down_state) + == PSCI_E_SUCCESS); + + target_pwrlvl = psci_find_target_suspend_lvl(&state_info); + if (target_pwrlvl == PSCI_INVALID_PWR_LVL) { + ERROR("Invalid target power level for suspend operation\n"); + panic(); + } + + /* Fast path for CPU standby.*/ + if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) { + if (!psci_plat_pm_ops->cpu_standby) + return PSCI_E_INVALID_PARAMS; + + /* + * Set the state of the CPU power domain to the platform + * specific retention state and enter the standby state. + */ + cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; + psci_set_cpu_local_state(cpu_pd_state); + +#if ENABLE_PSCI_STAT + /* + * Capture time-stamp before CPU standby + * No cache maintenance is needed as caches + * are ON through out the CPU standby operation. + */ + PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, + PMF_NO_CACHE_MAINT); +#endif + + psci_plat_pm_ops->cpu_standby(cpu_pd_state); + + /* Upon exit from standby, set the state back to RUN. */ + psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN); + +#if ENABLE_PSCI_STAT + /* Capture time-stamp after CPU standby */ + PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR, + PMF_NO_CACHE_MAINT); + + /* Update PSCI stats */ + psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info, + PMF_NO_CACHE_MAINT); +#endif + + return PSCI_E_SUCCESS; + } + + /* + * If a power down state has been requested, we need to verify entry + * point and program entry information. + */ + if (is_power_down_state) { + rc = psci_validate_entry_point(&ep, entrypoint, context_id); + if (rc != PSCI_E_SUCCESS) + return rc; + } + + /* + * Do what is needed to enter the power down state. Upon success, + * enter the final wfi which will power down this CPU. This function + * might return if the power down was abandoned for any reason, e.g. + * arrival of an interrupt + */ + psci_cpu_suspend_start(&ep, + target_pwrlvl, + &state_info, + is_power_down_state); + + return PSCI_E_SUCCESS; +} + + +int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id) +{ + int rc; + psci_power_state_t state_info; + entry_point_info_t ep; + + /* Check if the current CPU is the last ON CPU in the system */ + if (!psci_is_last_on_cpu()) + return PSCI_E_DENIED; + + /* Validate the entry point and get the entry_point_info */ + rc = psci_validate_entry_point(&ep, entrypoint, context_id); + if (rc != PSCI_E_SUCCESS) + return rc; + + /* Query the psci_power_state for system suspend */ + psci_query_sys_suspend_pwrstate(&state_info); + + /* Ensure that the psci_power_state makes sense */ + assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL); + assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN) + == PSCI_E_SUCCESS); + assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL])); + + /* + * Do what is needed to enter the system suspend state. This function + * might return if the power down was abandoned for any reason, e.g. + * arrival of an interrupt + */ + psci_cpu_suspend_start(&ep, + PLAT_MAX_PWR_LVL, + &state_info, + PSTATE_TYPE_POWERDOWN); + + return PSCI_E_SUCCESS; +} + +int psci_cpu_off(void) +{ + int rc; + unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL; + + rc = (int)bl31_plat_denied_cpu_off_chk(); + + if(PSCI_E_SUCCESS == rc) { + /* + * Do what is needed to power off this CPU and possible higher power + * levels if it able to do so. Upon success, enter the final wfi + * which will power down this CPU. + */ + rc = psci_do_cpu_off(target_pwrlvl); + } + + /* + * The only error cpu_off can return is E_DENIED. So check if that's + * indeed the case. + */ + assert(rc == PSCI_E_DENIED); + + return rc; +} + +int psci_affinity_info(u_register_t target_affinity, + unsigned int lowest_affinity_level) +{ + unsigned int target_idx; + + /* We dont support level higher than PSCI_CPU_PWR_LVL */ + if (lowest_affinity_level > PSCI_CPU_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + /* Calculate the cpu index of the target */ + target_idx = plat_core_pos_by_mpidr(target_affinity); + if (target_idx == -1) + return PSCI_E_INVALID_PARAMS; + + return psci_get_aff_info_state_by_idx(target_idx); +} + +int psci_migrate(u_register_t target_cpu) +{ + int rc; + u_register_t resident_cpu_mpidr; + + rc = psci_spd_migrate_info(&resident_cpu_mpidr); + if (rc != PSCI_TOS_UP_MIG_CAP) + return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ? + PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED; + + /* + * Migrate should only be invoked on the CPU where + * the Secure OS is resident. + */ + if (resident_cpu_mpidr != read_mpidr_el1()) + return PSCI_E_NOT_PRESENT; + + /* Check the validity of the specified target cpu */ + rc = psci_validate_mpidr(target_cpu); + if (rc != PSCI_E_SUCCESS) + return PSCI_E_INVALID_PARAMS; + + assert(psci_spd_pm && psci_spd_pm->svc_migrate); + + rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu); + assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); + + return rc; +} + +int psci_migrate_info_type(void) +{ + u_register_t resident_cpu_mpidr; + + return psci_spd_migrate_info(&resident_cpu_mpidr); +} + +long psci_migrate_info_up_cpu(void) +{ + u_register_t resident_cpu_mpidr; + int rc; + + /* + * Return value of this depends upon what + * psci_spd_migrate_info() returns. + */ + rc = psci_spd_migrate_info(&resident_cpu_mpidr); + if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP) + return PSCI_E_INVALID_PARAMS; + + return resident_cpu_mpidr; +} + +int psci_node_hw_state(u_register_t target_cpu, + unsigned int power_level) +{ + int rc; + + /* Validate target_cpu */ + rc = psci_validate_mpidr(target_cpu); + if (rc != PSCI_E_SUCCESS) + return PSCI_E_INVALID_PARAMS; + + /* Validate power_level against PLAT_MAX_PWR_LVL */ + if (power_level > PLAT_MAX_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + /* + * Dispatch this call to platform to query power controller, and pass on + * to the caller what it returns + */ + assert(psci_plat_pm_ops->get_node_hw_state); + rc = psci_plat_pm_ops->get_node_hw_state(target_cpu, power_level); + assert((rc >= HW_ON && rc <= HW_STANDBY) || rc == PSCI_E_NOT_SUPPORTED + || rc == PSCI_E_INVALID_PARAMS); + return rc; +} + +int psci_features(unsigned int psci_fid) +{ + unsigned int local_caps = psci_caps; + + /* Check if it is a 64 bit function */ + if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64) + local_caps &= PSCI_CAP_64BIT_MASK; + + /* Check for invalid fid */ + if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid) + && is_psci_fid(psci_fid))) + return PSCI_E_NOT_SUPPORTED; + + + /* Check if the psci fid is supported or not */ + if (!(local_caps & define_psci_cap(psci_fid))) + return PSCI_E_NOT_SUPPORTED; + + /* Format the feature flags */ + if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 || + psci_fid == PSCI_CPU_SUSPEND_AARCH64) { + /* + * The trusted firmware does not support OS Initiated Mode. + */ + return (FF_PSTATE << FF_PSTATE_SHIFT) | + ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT); + } + + /* Return 0 for all other fid's */ + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * PSCI top level handler for servicing SMCs. + ******************************************************************************/ +u_register_t psci_smc_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + if (is_caller_secure(flags)) + return SMC_UNK; + + /* Check the fid against the capabilities */ + if (!(psci_caps & define_psci_cap(smc_fid))) + return SMC_UNK; + + if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { + /* 32-bit PSCI function, clear top parameter bits */ + + x1 = (uint32_t)x1; + x2 = (uint32_t)x2; + x3 = (uint32_t)x3; + + switch (smc_fid) { + case PSCI_VERSION: + return psci_version(); + + case PSCI_CPU_OFF: + return psci_cpu_off(); + + case PSCI_CPU_SUSPEND_AARCH32: + return psci_cpu_suspend(x1, x2, x3); + + case PSCI_CPU_ON_AARCH32: + return psci_cpu_on(x1, x2, x3); + + case PSCI_AFFINITY_INFO_AARCH32: + return psci_affinity_info(x1, x2); + + case PSCI_MIG_AARCH32: + return psci_migrate(x1); + + case PSCI_MIG_INFO_TYPE: + return psci_migrate_info_type(); + + case PSCI_MIG_INFO_UP_CPU_AARCH32: + return psci_migrate_info_up_cpu(); + + case PSCI_NODE_HW_STATE_AARCH32: + return psci_node_hw_state(x1, x2); + + case PSCI_SYSTEM_SUSPEND_AARCH32: + return psci_system_suspend(x1, x2); + + case PSCI_SYSTEM_OFF: + psci_system_off(); + /* We should never return from psci_system_off() */ + + case PSCI_SYSTEM_RESET: + psci_system_reset(); + /* We should never return from psci_system_reset() */ + + case PSCI_FEATURES: + return psci_features(x1); + +#if ENABLE_PSCI_STAT + case PSCI_STAT_RESIDENCY_AARCH32: + return psci_stat_residency(x1, x2); + + case PSCI_STAT_COUNT_AARCH32: + return psci_stat_count(x1, x2); +#endif + + default: + break; + } + } else { + /* 64-bit PSCI function */ + + switch (smc_fid) { + case PSCI_CPU_SUSPEND_AARCH64: + return psci_cpu_suspend(x1, x2, x3); + + case PSCI_CPU_ON_AARCH64: + return psci_cpu_on(x1, x2, x3); + + case PSCI_AFFINITY_INFO_AARCH64: + return psci_affinity_info(x1, x2); + + case PSCI_MIG_AARCH64: + return psci_migrate(x1); + + case PSCI_MIG_INFO_UP_CPU_AARCH64: + return psci_migrate_info_up_cpu(); + + case PSCI_NODE_HW_STATE_AARCH64: + return psci_node_hw_state(x1, x2); + + case PSCI_SYSTEM_SUSPEND_AARCH64: + return psci_system_suspend(x1, x2); + +#if ENABLE_PSCI_STAT + case PSCI_STAT_RESIDENCY_AARCH64: + return psci_stat_residency(x1, x2); + + case PSCI_STAT_COUNT_AARCH64: + return psci_stat_count(x1, x2); +#endif + + default: + break; + } + } + + WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid); + return SMC_UNK; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_off.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_off.c new file mode 100644 index 0000000..471141d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_off.c @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "psci_private.h" + +/****************************************************************************** + * Construct the psci_power_state to request power OFF at all power levels. + ******************************************************************************/ +static void psci_set_power_off_state(psci_power_state_t *state_info) +{ + int lvl; + + for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) + state_info->pwr_domain_state[lvl] = PLAT_MAX_OFF_STATE; +} + +/****************************************************************************** + * Top level handler which is called when a cpu wants to power itself down. + * It's assumed that along with turning the cpu power domain off, power + * domains at higher levels will be turned off as far as possible. It finds + * the highest level where a domain has to be powered off by traversing the + * node information and then performs generic, architectural, platform setup + * and state management required to turn OFF that power domain and domains + * below it. e.g. For a cpu that's to be powered OFF, it could mean programming + * the power controller whereas for a cluster that's to be powered off, it will + * call the platform specific code which will disable coherency at the + * interconnect level if the cpu is the last in the cluster and also the + * program the power controller. + ******************************************************************************/ +int psci_do_cpu_off(unsigned int end_pwrlvl) +{ + int rc = PSCI_E_SUCCESS, idx = plat_my_core_pos(); + psci_power_state_t state_info; + + /* + * This function must only be called on platforms where the + * CPU_OFF platform hooks have been implemented. + */ + assert(psci_plat_pm_ops->pwr_domain_off); + + /* + * This function acquires the lock corresponding to each power + * level so that by the time all locks are taken, the system topology + * is snapshot and state management can be done safely. + */ + psci_acquire_pwr_domain_locks(end_pwrlvl, + idx); + + /* + * Call the cpu off handler registered by the Secure Payload Dispatcher + * to let it do any bookkeeping. Assume that the SPD always reports an + * E_DENIED error if SP refuse to power down + */ + if (psci_spd_pm && psci_spd_pm->svc_off) { + rc = psci_spd_pm->svc_off(0); + if (rc) + goto exit; + } + + /* Construct the psci_power_state for CPU_OFF */ + psci_set_power_off_state(&state_info); + + /* + * This function is passed the requested state info and + * it returns the negotiated state info for each power level upto + * the end level specified. + */ + psci_do_state_coordination(end_pwrlvl, &state_info); + +#if ENABLE_PSCI_STAT + /* Update the last cpu for each level till end_pwrlvl */ + psci_stats_update_pwr_down(end_pwrlvl, &state_info); +#endif + + /* + * Arch. management. Perform the necessary steps to flush all + * cpu caches. + */ + psci_do_pwrdown_cache_maintenance(psci_find_max_off_lvl(&state_info)); + + /* + * Plat. management: Perform platform specific actions to turn this + * cpu off e.g. exit cpu coherency, program the power controller etc. + */ + psci_plat_pm_ops->pwr_domain_off(&state_info); + +#if ENABLE_PSCI_STAT + /* + * Capture time-stamp while entering low power state. + * No cache maintenance needed because caches are off + * and writes are direct to main memory. + */ + PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, + PMF_NO_CACHE_MAINT); +#endif + +exit: + /* + * Release the locks corresponding to each power level in the + * reverse order to which they were acquired. + */ + psci_release_pwr_domain_locks(end_pwrlvl, + idx); + + /* + * Check if all actions needed to safely power down this cpu have + * successfully completed. + */ + if (rc == PSCI_E_SUCCESS) { + /* + * Set the affinity info state to OFF. This writes directly to + * main memory as caches are disabled, so cache maintenance is + * required to ensure that later cached reads of aff_info_state + * return AFF_STATE_OFF. A dsbish() ensures ordering of the + * update to the affinity info state prior to cache line + * invalidation. + */ + flush_cpu_data(psci_svc_cpu_data.aff_info_state); + psci_set_aff_info_state(AFF_STATE_OFF); + dsbish(); + inv_cpu_data(psci_svc_cpu_data.aff_info_state); + + if (psci_plat_pm_ops->pwr_domain_pwr_down_wfi) { + /* This function must not return */ + psci_plat_pm_ops->pwr_domain_pwr_down_wfi(&state_info); + } else { + /* + * Enter a wfi loop which will allow the power + * controller to physically power down this cpu. + */ + psci_power_down_wfi(); + } + } + + return rc; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_on.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_on.c new file mode 100644 index 0000000..f4bb797 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_on.c @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "psci_private.h" + +/******************************************************************************* + * This function checks whether a cpu which has been requested to be turned on + * is OFF to begin with. + ******************************************************************************/ +static int cpu_on_validate_state(aff_info_state_t aff_state) +{ + if (aff_state == AFF_STATE_ON) + return PSCI_E_ALREADY_ON; + + if (aff_state == AFF_STATE_ON_PENDING) + return PSCI_E_ON_PENDING; + + assert(aff_state == AFF_STATE_OFF); + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * Generic handler which is called to physically power on a cpu identified by + * its mpidr. It performs the generic, architectural, platform setup and state + * management to power on the target cpu e.g. it will ensure that + * enough information is stashed for it to resume execution in the non-secure + * security state. + * + * The state of all the relevant power domains are changed after calling the + * platform handler as it can return error. + ******************************************************************************/ +int psci_cpu_on_start(u_register_t target_cpu, + entry_point_info_t *ep) +{ + int rc; + unsigned int target_idx = plat_core_pos_by_mpidr(target_cpu); + aff_info_state_t target_aff_state; + + /* Calling function must supply valid input arguments */ + assert((int) target_idx >= 0); + assert(ep != NULL); + + /* + * This function must only be called on platforms where the + * CPU_ON platform hooks have been implemented. + */ + assert(psci_plat_pm_ops->pwr_domain_on && + psci_plat_pm_ops->pwr_domain_on_finish); + + /* Protect against multiple CPUs trying to turn ON the same target CPU */ + psci_spin_lock_cpu(target_idx); + + /* + * Generic management: Ensure that the cpu is off to be + * turned on. + */ + rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx)); + if (rc != PSCI_E_SUCCESS) + goto exit; + + /* + * Call the cpu on handler registered by the Secure Payload Dispatcher + * to let it do any bookeeping. If the handler encounters an error, it's + * expected to assert within + */ + if (psci_spd_pm && psci_spd_pm->svc_on) + psci_spd_pm->svc_on(target_cpu); + + /* + * Set the Affinity info state of the target cpu to ON_PENDING. + * Flush aff_info_state as it will be accessed with caches + * turned OFF. + */ + psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); + flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); + + /* + * The cache line invalidation by the target CPU after setting the + * state to OFF (see psci_do_cpu_off()), could cause the update to + * aff_info_state to be invalidated. Retry the update if the target + * CPU aff_info_state is not ON_PENDING. + */ + target_aff_state = psci_get_aff_info_state_by_idx(target_idx); + if (target_aff_state != AFF_STATE_ON_PENDING) { + assert(target_aff_state == AFF_STATE_OFF); + psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); + flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); + + assert(psci_get_aff_info_state_by_idx(target_idx) == AFF_STATE_ON_PENDING); + } + + /* + * Perform generic, architecture and platform specific handling. + */ + /* + * Plat. management: Give the platform the current state + * of the target cpu to allow it to perform the necessary + * steps to power on. + */ + rc = psci_plat_pm_ops->pwr_domain_on(target_cpu); + assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); + + if (rc == PSCI_E_SUCCESS) + /* Store the re-entry information for the non-secure world. */ + cm_init_context_by_index(target_idx, ep); + else { + /* Restore the state on error. */ + psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF); + flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); + } + +exit: + psci_spin_unlock_cpu(target_idx); + return rc; +} + +/******************************************************************************* + * The following function finish an earlier power on request. They + * are called by the common finisher routine in psci_common.c. The `state_info` + * is the psci_power_state from which this CPU has woken up from. + ******************************************************************************/ +void psci_cpu_on_finish(unsigned int cpu_idx, + psci_power_state_t *state_info) +{ + /* + * Plat. management: Perform the platform specific actions + * for this cpu e.g. enabling the gic or zeroing the mailbox + * register. The actual state of this cpu has already been + * changed. + */ + psci_plat_pm_ops->pwr_domain_on_finish(state_info); + + /* + * Arch. management: Enable data cache and manage stack memory + */ + psci_do_pwrup_cache_maintenance(); + + /* + * All the platform specific actions for turning this cpu + * on have completed. Perform enough arch.initialization + * to run in the non-secure address space. + */ + psci_arch_setup(); + + /* + * Lock the CPU spin lock to make sure that the context initialization + * is done. Since the lock is only used in this function to create + * a synchronization point with cpu_on_start(), it can be released + * immediately. + */ + psci_spin_lock_cpu(cpu_idx); + psci_spin_unlock_cpu(cpu_idx); + + /* Ensure we have been explicitly woken up by another cpu */ + assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING); + + /* + * Call the cpu on finish handler registered by the Secure Payload + * Dispatcher to let it do any bookeeping. If the handler encounters an + * error, it's expected to assert within + */ + if (psci_spd_pm && psci_spd_pm->svc_on_finish) + psci_spd_pm->svc_on_finish(0); + + /* Populate the mpidr field within the cpu node array */ + /* This needs to be done only once */ + psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK; + + /* + * Generic management: Now we just need to retrieve the + * information that we had stashed away during the cpu_on + * call to set this cpu on its way. + */ + cm_prepare_el3_exit(NON_SECURE); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_private.h new file mode 100644 index 0000000..8388cd7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_private.h @@ -0,0 +1,261 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PSCI_PRIVATE_H__ +#define __PSCI_PRIVATE_H__ + +#include +#include +#include +#include +#include +#include +#include + +/* + * The following helper macros abstract the interface to the Bakery + * Lock API. + */ +#define psci_lock_init(non_cpu_pd_node, idx) \ + ((non_cpu_pd_node)[(idx)].lock_index = (idx)) +#define psci_lock_get(non_cpu_pd_node) \ + bakery_lock_get(&psci_locks[(non_cpu_pd_node)->lock_index]) +#define psci_lock_release(non_cpu_pd_node) \ + bakery_lock_release(&psci_locks[(non_cpu_pd_node)->lock_index]) + +/* + * The PSCI capability which are provided by the generic code but does not + * depend on the platform or spd capabilities. + */ +#define PSCI_GENERIC_CAP \ + (define_psci_cap(PSCI_VERSION) | \ + define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ + define_psci_cap(PSCI_FEATURES)) + +/* + * The PSCI capabilities mask for 64 bit functions. + */ +#define PSCI_CAP_64BIT_MASK \ + (define_psci_cap(PSCI_CPU_SUSPEND_AARCH64) | \ + define_psci_cap(PSCI_CPU_ON_AARCH64) | \ + define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \ + define_psci_cap(PSCI_MIG_AARCH64) | \ + define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) | \ + define_psci_cap(PSCI_NODE_HW_STATE_AARCH64) | \ + define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64) | \ + define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64) | \ + define_psci_cap(PSCI_STAT_COUNT_AARCH64)) + +/* + * Helper macros to get/set the fields of PSCI per-cpu data. + */ +#define psci_set_aff_info_state(aff_state) \ + set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state) +#define psci_get_aff_info_state() \ + get_cpu_data(psci_svc_cpu_data.aff_info_state) +#define psci_get_aff_info_state_by_idx(idx) \ + get_cpu_data_by_index(idx, psci_svc_cpu_data.aff_info_state) +#define psci_set_aff_info_state_by_idx(idx, aff_state) \ + set_cpu_data_by_index(idx, psci_svc_cpu_data.aff_info_state,\ + aff_state) +#define psci_get_suspend_pwrlvl() \ + get_cpu_data(psci_svc_cpu_data.target_pwrlvl) +#define psci_set_suspend_pwrlvl(target_lvl) \ + set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl) +#define psci_set_cpu_local_state(state) \ + set_cpu_data(psci_svc_cpu_data.local_state, state) +#define psci_get_cpu_local_state() \ + get_cpu_data(psci_svc_cpu_data.local_state) +#define psci_get_cpu_local_state_by_idx(idx) \ + get_cpu_data_by_index(idx, psci_svc_cpu_data.local_state) + +/* + * Helper macros for the CPU level spinlocks + */ +#define psci_spin_lock_cpu(idx) spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock) +#define psci_spin_unlock_cpu(idx) spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock) + +/* Helper macro to identify a CPU standby request in PSCI Suspend call */ +#define is_cpu_standby_req(is_power_down_state, retn_lvl) \ + (((!(is_power_down_state)) && ((retn_lvl) == 0)) ? 1 : 0) + +/* Following are used as ID's to capture time-stamp */ +#define PSCI_STAT_ID_ENTER_LOW_PWR 0 +#define PSCI_STAT_ID_EXIT_LOW_PWR 1 +#define PSCI_STAT_TOTAL_IDS 2 + +/* Declare PMF service functions for PSCI */ +PMF_DECLARE_CAPTURE_TIMESTAMP(psci_svc) +PMF_DECLARE_GET_TIMESTAMP(psci_svc) + +/******************************************************************************* + * The following two data structures implement the power domain tree. The tree + * is used to track the state of all the nodes i.e. power domain instances + * described by the platform. The tree consists of nodes that describe CPU power + * domains i.e. leaf nodes and all other power domains which are parents of a + * CPU power domain i.e. non-leaf nodes. + ******************************************************************************/ +typedef struct non_cpu_pwr_domain_node { + /* + * Index of the first CPU power domain node level 0 which has this node + * as its parent. + */ + unsigned int cpu_start_idx; + + /* + * Number of CPU power domains which are siblings of the domain indexed + * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx + * -> cpu_start_idx + ncpus' have this node as their parent. + */ + unsigned int ncpus; + + /* + * Index of the parent power domain node. + * TODO: Figure out whether to whether using pointer is more efficient. + */ + unsigned int parent_node; + + plat_local_state_t local_state; + + unsigned char level; + + /* For indexing the psci_lock array*/ + unsigned char lock_index; +} non_cpu_pd_node_t; + +typedef struct cpu_pwr_domain_node { + u_register_t mpidr; + + /* + * Index of the parent power domain node. + * TODO: Figure out whether to whether using pointer is more efficient. + */ + unsigned int parent_node; + + /* + * A CPU power domain does not require state coordination like its + * parent power domains. Hence this node does not include a bakery + * lock. A spinlock is required by the CPU_ON handler to prevent a race + * when multiple CPUs try to turn ON the same target CPU. + */ + spinlock_t cpu_lock; +} cpu_pd_node_t; + +/******************************************************************************* + * Data prototypes + ******************************************************************************/ +extern const plat_psci_ops_t *psci_plat_pm_ops; +extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS]; +extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT]; +extern unsigned int psci_caps; + +/* One bakery lock is required for each non-cpu power domain */ +DECLARE_BAKERY_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]); + +/******************************************************************************* + * SPD's power management hooks registered with PSCI + ******************************************************************************/ +extern const spd_pm_ops_t *psci_spd_pm; + +/******************************************************************************* + * Function prototypes + ******************************************************************************/ +/* Private exported functions from psci_common.c */ +int psci_validate_power_state(unsigned int power_state, + psci_power_state_t *state_info); +void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info); +int psci_validate_mpidr(u_register_t mpidr); +void psci_init_req_local_pwr_states(void); +void psci_get_target_local_pwr_states(unsigned int end_pwrlvl, + psci_power_state_t *target_state); +int psci_validate_entry_point(entry_point_info_t *ep, + uintptr_t entrypoint, u_register_t context_id); +void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx, + unsigned int end_lvl, + unsigned int node_index[]); +void psci_do_state_coordination(unsigned int end_pwrlvl, + psci_power_state_t *state_info); +void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl, + unsigned int cpu_idx); +void psci_release_pwr_domain_locks(unsigned int end_pwrlvl, + unsigned int cpu_idx); +int psci_validate_suspend_req(const psci_power_state_t *state_info, + unsigned int is_power_down_state_req); +unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info); +unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info); +void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl); +void psci_print_power_domain_map(void); +unsigned int psci_is_last_on_cpu(void); +int psci_spd_migrate_info(u_register_t *mpidr); + +/* Private exported functions from psci_on.c */ +int psci_cpu_on_start(u_register_t target_cpu, + entry_point_info_t *ep); + +void psci_cpu_on_finish(unsigned int cpu_idx, + psci_power_state_t *state_info); + +/* Private exported functions from psci_off.c */ +int psci_do_cpu_off(unsigned int end_pwrlvl); + +/* Private exported functions from psci_suspend.c */ +void psci_cpu_suspend_start(entry_point_info_t *ep, + unsigned int end_pwrlvl, + psci_power_state_t *state_info, + unsigned int is_power_down_state_req); + +void psci_cpu_suspend_finish(unsigned int cpu_idx, + psci_power_state_t *state_info); + +/* Private exported functions from psci_helpers.S */ +void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level); +void psci_do_pwrup_cache_maintenance(void); + +/* Private exported functions from psci_system_off.c */ +void __dead2 psci_system_off(void); +void __dead2 psci_system_reset(void); + +/* Private exported functions from psci_stat.c */ +void psci_stats_update_pwr_down(unsigned int end_pwrlvl, + const psci_power_state_t *state_info); +void psci_stats_update_pwr_up(unsigned int end_pwrlvl, + const psci_power_state_t *state_info, + unsigned int flags); +u_register_t psci_stat_residency(u_register_t target_cpu, + unsigned int power_state); +u_register_t psci_stat_count(u_register_t target_cpu, + unsigned int power_state); + +#if PLAT_rcar +extern void rcar_bl31_set_suspend_to_ram(void); +#endif + +#endif /* __PSCI_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_setup.c new file mode 100644 index 0000000..cb8b77d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_setup.c @@ -0,0 +1,302 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "psci_private.h" + +/******************************************************************************* + * Per cpu non-secure contexts used to program the architectural state prior + * return to the normal world. + * TODO: Use the memory allocator to set aside memory for the contexts instead + * of relying on platform defined constants. + ******************************************************************************/ +static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT]; + +/****************************************************************************** + * Define the psci capability variable. + *****************************************************************************/ +unsigned int psci_caps; + +/******************************************************************************* + * Function which initializes the 'psci_non_cpu_pd_nodes' or the + * 'psci_cpu_pd_nodes' corresponding to the power level. + ******************************************************************************/ +static void psci_init_pwr_domain_node(unsigned int node_idx, + unsigned int parent_idx, + unsigned int level) +{ + if (level > PSCI_CPU_PWR_LVL) { + psci_non_cpu_pd_nodes[node_idx].level = level; + psci_lock_init(psci_non_cpu_pd_nodes, node_idx); + psci_non_cpu_pd_nodes[node_idx].parent_node = parent_idx; + psci_non_cpu_pd_nodes[node_idx].local_state = + PLAT_MAX_OFF_STATE; + } else { + psci_cpu_data_t *svc_cpu_data; + + psci_cpu_pd_nodes[node_idx].parent_node = parent_idx; + + /* Initialize with an invalid mpidr */ + psci_cpu_pd_nodes[node_idx].mpidr = PSCI_INVALID_MPIDR; + + svc_cpu_data = + &(_cpu_data_by_index(node_idx)->psci_svc_cpu_data); + + /* Set the Affinity Info for the cores as OFF */ + svc_cpu_data->aff_info_state = AFF_STATE_OFF; + + /* Invalidate the suspend level for the cpu */ + svc_cpu_data->target_pwrlvl = PSCI_INVALID_PWR_LVL; + + /* Set the power state to OFF state */ + svc_cpu_data->local_state = PLAT_MAX_OFF_STATE; + + flush_dcache_range((uintptr_t)svc_cpu_data, + sizeof(*svc_cpu_data)); + + cm_set_context_by_index(node_idx, + (void *) &psci_ns_context[node_idx], + NON_SECURE); + } +} + +/******************************************************************************* + * This functions updates cpu_start_idx and ncpus field for each of the node in + * psci_non_cpu_pd_nodes[]. It does so by comparing the parent nodes of each of + * the CPUs and check whether they match with the parent of the previous + * CPU. The basic assumption for this work is that children of the same parent + * are allocated adjacent indices. The platform should ensure this though proper + * mapping of the CPUs to indices via plat_core_pos_by_mpidr() and + * plat_my_core_pos() APIs. + *******************************************************************************/ +static void psci_update_pwrlvl_limits(void) +{ + int j; + unsigned int nodes_idx[PLAT_MAX_PWR_LVL] = {0}; + unsigned int temp_index[PLAT_MAX_PWR_LVL], cpu_idx; + + for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) { + psci_get_parent_pwr_domain_nodes(cpu_idx, + PLAT_MAX_PWR_LVL, + temp_index); + for (j = PLAT_MAX_PWR_LVL - 1; j >= 0; j--) { + if (temp_index[j] != nodes_idx[j]) { + nodes_idx[j] = temp_index[j]; + psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx + = cpu_idx; + } + psci_non_cpu_pd_nodes[nodes_idx[j]].ncpus++; + } + } +} + +/******************************************************************************* + * Core routine to populate the power domain tree. The tree descriptor passed by + * the platform is populated breadth-first and the first entry in the map + * informs the number of root power domains. The parent nodes of the root nodes + * will point to an invalid entry(-1). + ******************************************************************************/ +static void populate_power_domain_tree(const unsigned char *topology) +{ + unsigned int i, j = 0, num_nodes_at_lvl = 1, num_nodes_at_next_lvl; + unsigned int node_index = 0, parent_node_index = 0, num_children; + int level = PLAT_MAX_PWR_LVL; + + /* + * For each level the inputs are: + * - number of nodes at this level in plat_array i.e. num_nodes_at_level + * This is the sum of values of nodes at the parent level. + * - Index of first entry at this level in the plat_array i.e. + * parent_node_index. + * - Index of first free entry in psci_non_cpu_pd_nodes[] or + * psci_cpu_pd_nodes[] i.e. node_index depending upon the level. + */ + while (level >= PSCI_CPU_PWR_LVL) { + num_nodes_at_next_lvl = 0; + /* + * For each entry (parent node) at this level in the plat_array: + * - Find the number of children + * - Allocate a node in a power domain array for each child + * - Set the parent of the child to the parent_node_index - 1 + * - Increment parent_node_index to point to the next parent + * - Accumulate the number of children at next level. + */ + for (i = 0; i < num_nodes_at_lvl; i++) { + assert(parent_node_index <= + PSCI_NUM_NON_CPU_PWR_DOMAINS); + num_children = topology[parent_node_index]; + + for (j = node_index; + j < node_index + num_children; j++) + psci_init_pwr_domain_node(j, + parent_node_index - 1, + level); + + node_index = j; + num_nodes_at_next_lvl += num_children; + parent_node_index++; + } + + num_nodes_at_lvl = num_nodes_at_next_lvl; + level--; + + /* Reset the index for the cpu power domain array */ + if (level == PSCI_CPU_PWR_LVL) + node_index = 0; + } + + /* Validate the sanity of array exported by the platform */ + assert(j == PLATFORM_CORE_COUNT); +} + +/******************************************************************************* + * This function does the architectural setup and takes the warm boot + * entry-point `mailbox_ep` as an argument. The function also initializes the + * power domain topology tree by querying the platform. The power domain nodes + * higher than the CPU are populated in the array psci_non_cpu_pd_nodes[] and + * the CPU power domains are populated in psci_cpu_pd_nodes[]. The platform + * exports its static topology map through the + * populate_power_domain_topology_tree() API. The algorithm populates the + * psci_non_cpu_pd_nodes and psci_cpu_pd_nodes iteratively by using this + * topology map. On a platform that implements two clusters of 2 cpus each, + * and supporting 3 domain levels, the populated psci_non_cpu_pd_nodes would + * look like this: + * + * --------------------------------------------------- + * | system node | cluster 0 node | cluster 1 node | + * --------------------------------------------------- + * + * And populated psci_cpu_pd_nodes would look like this : + * <- cpus cluster0 -><- cpus cluster1 -> + * ------------------------------------------------ + * | CPU 0 | CPU 1 | CPU 2 | CPU 3 | + * ------------------------------------------------ + ******************************************************************************/ +int psci_setup(const psci_lib_args_t *lib_args) +{ + const unsigned char *topology_tree; + + assert(VERIFY_PSCI_LIB_ARGS_V1(lib_args)); + + /* Do the Architectural initialization */ + psci_arch_setup(); + + /* Query the topology map from the platform */ + topology_tree = plat_get_power_domain_tree_desc(); + + /* Populate the power domain arrays using the platform topology map */ + populate_power_domain_tree(topology_tree); + + /* Update the CPU limits for each node in psci_non_cpu_pd_nodes */ + psci_update_pwrlvl_limits(); + + /* Populate the mpidr field of cpu node for this CPU */ + psci_cpu_pd_nodes[plat_my_core_pos()].mpidr = + read_mpidr() & MPIDR_AFFINITY_MASK; + + psci_init_req_local_pwr_states(); + + /* + * Set the requested and target state of this CPU and all the higher + * power domain levels for this CPU to run. + */ + psci_set_pwr_domains_to_run(PLAT_MAX_PWR_LVL); + + plat_setup_psci_ops((uintptr_t)lib_args->mailbox_ep, &psci_plat_pm_ops); + assert(psci_plat_pm_ops); + + /* + * Flush `psci_plat_pm_ops` as it will be accessed by secondary CPUs + * during warm boot before data cache is enabled. + */ + flush_dcache_range((uintptr_t)&psci_plat_pm_ops, + sizeof(psci_plat_pm_ops)); + + /* Initialize the psci capability */ + psci_caps = PSCI_GENERIC_CAP; + + if (psci_plat_pm_ops->pwr_domain_off) + psci_caps |= define_psci_cap(PSCI_CPU_OFF); + if (psci_plat_pm_ops->pwr_domain_on && + psci_plat_pm_ops->pwr_domain_on_finish) + psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64); + if (psci_plat_pm_ops->pwr_domain_suspend && + psci_plat_pm_ops->pwr_domain_suspend_finish) { + psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64); + if (psci_plat_pm_ops->get_sys_suspend_power_state) + psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64); + } + if (psci_plat_pm_ops->system_off) + psci_caps |= define_psci_cap(PSCI_SYSTEM_OFF); + if (psci_plat_pm_ops->system_reset) + psci_caps |= define_psci_cap(PSCI_SYSTEM_RESET); + if (psci_plat_pm_ops->get_node_hw_state) + psci_caps |= define_psci_cap(PSCI_NODE_HW_STATE_AARCH64); + +#if ENABLE_PSCI_STAT + psci_caps |= define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64); + psci_caps |= define_psci_cap(PSCI_STAT_COUNT_AARCH64); +#endif + + return 0; +} + +/******************************************************************************* + * This duplicates what the primary cpu did after a cold boot in BL1. The same + * needs to be done when a cpu is hotplugged in. This function could also over- + * ride any EL3 setup done by BL1 as this code resides in rw memory. + ******************************************************************************/ +void psci_arch_setup(void) +{ + /* Program the counter frequency */ + write_cntfrq_el0(plat_get_syscnt_freq2()); + + /* Initialize the cpu_ops pointer. */ + init_cpu_ops(); +} + +/****************************************************************************** + * PSCI Library interface to initialize the cpu context for the next non + * secure image during cold boot. The relevant registers in the cpu context + * need to be retrieved and programmed on return from this interface. + *****************************************************************************/ +void psci_prepare_next_non_secure_ctx(entry_point_info_t *next_image_info) +{ + assert(GET_SECURITY_STATE(next_image_info->h.attr) == NON_SECURE); + cm_init_my_context(next_image_info); + cm_prepare_el3_exit(NON_SECURE); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_stat.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_stat.c new file mode 100644 index 0000000..ecbe592 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_stat.c @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "psci_private.h" + +#ifndef PLAT_MAX_PWR_LVL_STATES +#define PLAT_MAX_PWR_LVL_STATES 2 +#endif + +/* Ticks elapsed in one second by a signal of 1 MHz */ +#define MHZ_TICKS_PER_SEC 1000000 + +/* Following structure is used for PSCI STAT */ +typedef struct psci_stat { + u_register_t residency; + u_register_t count; +} psci_stat_t; + +/* + * Following is used to keep track of the last cpu + * that goes to power down in non cpu power domains. + */ +static int last_cpu_in_non_cpu_pd[PSCI_NUM_NON_CPU_PWR_DOMAINS] = {-1}; + +/* + * Following are used to store PSCI STAT values for + * CPU and non CPU power domains. + */ +static psci_stat_t psci_cpu_stat[PLATFORM_CORE_COUNT] + [PLAT_MAX_PWR_LVL_STATES]; +static psci_stat_t psci_non_cpu_stat[PSCI_NUM_NON_CPU_PWR_DOMAINS] + [PLAT_MAX_PWR_LVL_STATES]; + +/* Register PMF PSCI service */ +PMF_REGISTER_SERVICE(psci_svc, PMF_PSCI_STAT_SVC_ID, + PSCI_STAT_TOTAL_IDS, PMF_STORE_ENABLE) + +/* The divisor to use to convert raw timestamp into microseconds */ +u_register_t residency_div; + +/* + * This macro calculates the stats residency in microseconds, + * taking in account the wrap around condition. + */ +#define calc_stat_residency(_pwrupts, _pwrdnts, _res) \ + do { \ + if (_pwrupts < _pwrdnts) \ + _res = UINT64_MAX - _pwrdnts + _pwrupts;\ + else \ + _res = _pwrupts - _pwrdnts; \ + /* Convert timestamp into microseconds */ \ + _res = _res/residency_div; \ + } while (0) + +/* + * This functions returns the index into the `psci_stat_t` array given the + * local power state and power domain level. If the platform implements the + * `get_pwr_lvl_state_idx` pm hook, then that will be used to return the index. + */ +static int get_stat_idx(plat_local_state_t local_state, int pwr_lvl) +{ + int idx; + + if (psci_plat_pm_ops->get_pwr_lvl_state_idx == NULL) { + assert(PLAT_MAX_PWR_LVL_STATES == 2); + if (is_local_state_retn(local_state)) + return 0; + + assert(is_local_state_off(local_state)); + return 1; + } + + idx = psci_plat_pm_ops->get_pwr_lvl_state_idx(local_state, pwr_lvl); + assert((idx >= 0) && (idx < PLAT_MAX_PWR_LVL_STATES)); + return idx; +} + +/******************************************************************************* + * This function is passed the target local power states for each power + * domain (state_info) between the current CPU domain and its ancestors until + * the target power level (end_pwrlvl). + * + * Then, for each level (apart from the CPU level) until the 'end_pwrlvl', it + * updates the `last_cpu_in_non_cpu_pd[]` with last power down cpu id. + * + * This function will only be invoked with data cache enabled and while + * powering down a core. + ******************************************************************************/ +void psci_stats_update_pwr_down(unsigned int end_pwrlvl, + const psci_power_state_t *state_info) +{ + int lvl, parent_idx, cpu_idx = plat_my_core_pos(); + + assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); + assert(state_info); + + parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; + + for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { + + /* Break early if the target power state is RUN */ + if (is_local_state_run(state_info->pwr_domain_state[lvl])) + break; + + /* + * The power domain is entering a low power state, so this is + * the last CPU for this power domain + */ + last_cpu_in_non_cpu_pd[parent_idx] = cpu_idx; + + parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; + } + +} + +/******************************************************************************* + * This function updates the PSCI STATS(residency time and count) for CPU + * and NON-CPU power domains. + * It is called with caches enabled and locks acquired(for NON-CPU domain) + ******************************************************************************/ +void psci_stats_update_pwr_up(unsigned int end_pwrlvl, + const psci_power_state_t *state_info, + unsigned int flags) +{ + int parent_idx, cpu_idx = plat_my_core_pos(); + int lvl, stat_idx; + plat_local_state_t local_state; + unsigned long long pwrup_ts = 0, pwrdn_ts = 0; + u_register_t residency; + + assert(end_pwrlvl <= PLAT_MAX_PWR_LVL); + assert(state_info); + + /* Initialize the residency divisor if not already initialized */ + if (!residency_div) { + /* Pre-calculate divisor so that it can be directly used to + convert time-stamp into microseconds */ + residency_div = read_cntfrq_el0() / MHZ_TICKS_PER_SEC; + assert(residency_div); + } + + /* Get power down time-stamp for current CPU */ + PMF_GET_TIMESTAMP_BY_INDEX(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, + cpu_idx, flags, pwrdn_ts); + + /* In the case of 1st power on just return */ + if (!pwrdn_ts) + return; + + /* Get power up time-stamp for current CPU */ + PMF_GET_TIMESTAMP_BY_INDEX(psci_svc, PSCI_STAT_ID_EXIT_LOW_PWR, + cpu_idx, flags, pwrup_ts); + + /* Get the index into the stats array */ + local_state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; + stat_idx = get_stat_idx(local_state, PSCI_CPU_PWR_LVL); + + /* Calculate stats residency */ + calc_stat_residency(pwrup_ts, pwrdn_ts, residency); + + /* Update CPU stats. */ + psci_cpu_stat[cpu_idx][stat_idx].residency += residency; + psci_cpu_stat[cpu_idx][stat_idx].count++; + + /* + * Check what power domains above CPU were off + * prior to this CPU powering on. + */ + parent_idx = psci_cpu_pd_nodes[cpu_idx].parent_node; + for (lvl = PSCI_CPU_PWR_LVL + 1; lvl <= end_pwrlvl; lvl++) { + local_state = state_info->pwr_domain_state[lvl]; + if (is_local_state_run(local_state)) { + /* Break early */ + break; + } + + assert(last_cpu_in_non_cpu_pd[parent_idx] != -1); + + /* Get power down time-stamp for last CPU */ + PMF_GET_TIMESTAMP_BY_INDEX(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, + last_cpu_in_non_cpu_pd[parent_idx], + flags, pwrdn_ts); + + /* Initialize back to reset value */ + last_cpu_in_non_cpu_pd[parent_idx] = -1; + + /* Get the index into the stats array */ + stat_idx = get_stat_idx(local_state, lvl); + + /* Calculate stats residency */ + calc_stat_residency(pwrup_ts, pwrdn_ts, residency); + + /* Update non cpu stats */ + psci_non_cpu_stat[parent_idx][stat_idx].residency += residency; + psci_non_cpu_stat[parent_idx][stat_idx].count++; + + parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; + } + +} + +/******************************************************************************* + * This function returns the appropriate count and residency time of the + * local state for the highest power level expressed in the `power_state` + * for the node represented by `target_cpu`. + ******************************************************************************/ +int psci_get_stat(u_register_t target_cpu, unsigned int power_state, + psci_stat_t *psci_stat) +{ + int rc, pwrlvl, lvl, parent_idx, stat_idx, target_idx; + psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} }; + plat_local_state_t local_state; + + /* Validate the target_cpu parameter and determine the cpu index */ + target_idx = plat_core_pos_by_mpidr(target_cpu); + if (target_idx == -1) + return PSCI_E_INVALID_PARAMS; + + /* Validate the power_state parameter */ + if (!psci_plat_pm_ops->translate_power_state_by_mpidr) + rc = psci_validate_power_state(power_state, &state_info); + else + rc = psci_plat_pm_ops->translate_power_state_by_mpidr( + target_cpu, power_state, &state_info); + + if (rc != PSCI_E_SUCCESS) + return PSCI_E_INVALID_PARAMS; + + /* Find the highest power level */ + pwrlvl = psci_find_target_suspend_lvl(&state_info); + if (pwrlvl == PSCI_INVALID_PWR_LVL) { + ERROR("Invalid target power level for PSCI statistics operation\n"); + panic(); + } + + /* Get the index into the stats array */ + local_state = state_info.pwr_domain_state[pwrlvl]; + stat_idx = get_stat_idx(local_state, pwrlvl); + + if (pwrlvl > PSCI_CPU_PWR_LVL) { + /* Get the power domain index */ + parent_idx = psci_cpu_pd_nodes[target_idx].parent_node; + for (lvl = PSCI_CPU_PWR_LVL + 1; lvl < pwrlvl; lvl++) + parent_idx = psci_non_cpu_pd_nodes[parent_idx].parent_node; + + /* Get the non cpu power domain stats */ + *psci_stat = psci_non_cpu_stat[parent_idx][stat_idx]; + } else { + /* Get the cpu power domain stats */ + *psci_stat = psci_cpu_stat[target_idx][stat_idx]; + } + + return PSCI_E_SUCCESS; +} + +/* This is the top level function for PSCI_STAT_RESIDENCY SMC. */ +u_register_t psci_stat_residency(u_register_t target_cpu, + unsigned int power_state) +{ + psci_stat_t psci_stat; + + int rc = psci_get_stat(target_cpu, power_state, &psci_stat); + if (rc == PSCI_E_SUCCESS) + return psci_stat.residency; + else + return 0; +} + +/* This is the top level function for PSCI_STAT_COUNT SMC. */ +u_register_t psci_stat_count(u_register_t target_cpu, + unsigned int power_state) +{ + psci_stat_t psci_stat; + + int rc = psci_get_stat(target_cpu, power_state, &psci_stat); + if (rc == PSCI_E_SUCCESS) + return psci_stat.count; + else + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_suspend.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_suspend.c new file mode 100644 index 0000000..9a724c8 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_suspend.c @@ -0,0 +1,297 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "psci_private.h" + +/******************************************************************************* + * This function does generic and platform specific operations after a wake-up + * from standby/retention states at multiple power levels. + ******************************************************************************/ +static void psci_suspend_to_standby_finisher(unsigned int cpu_idx, + unsigned int end_pwrlvl) +{ + psci_power_state_t state_info; + + psci_acquire_pwr_domain_locks(end_pwrlvl, + cpu_idx); + + /* + * Find out which retention states this CPU has exited from until the + * 'end_pwrlvl'. The exit retention state could be deeper than the entry + * state as a result of state coordination amongst other CPUs post wfi. + */ + psci_get_target_local_pwr_states(end_pwrlvl, &state_info); + + /* + * Plat. management: Allow the platform to do operations + * on waking up from retention. + */ + psci_plat_pm_ops->pwr_domain_suspend_finish(&state_info); + + /* + * Set the requested and target state of this CPU and all the higher + * power domain levels for this CPU to run. + */ + psci_set_pwr_domains_to_run(end_pwrlvl); + + psci_release_pwr_domain_locks(end_pwrlvl, + cpu_idx); +} + +/******************************************************************************* + * This function does generic and platform specific suspend to power down + * operations. + ******************************************************************************/ +static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl, + entry_point_info_t *ep, + psci_power_state_t *state_info) +{ + unsigned int max_off_lvl = psci_find_max_off_lvl(state_info); + + /* Save PSCI target power level for the suspend finisher handler */ + psci_set_suspend_pwrlvl(end_pwrlvl); + + /* + * Flush the target power level as it will be accessed on power up with + * Data cache disabled. + */ + flush_cpu_data(psci_svc_cpu_data.target_pwrlvl); + + /* + * Call the cpu suspend handler registered by the Secure Payload + * Dispatcher to let it do any book-keeping. If the handler encounters an + * error, it's expected to assert within + */ + if (psci_spd_pm && psci_spd_pm->svc_suspend) + psci_spd_pm->svc_suspend(max_off_lvl); + + /* + * Store the re-entry information for the non-secure world. + */ + cm_init_my_context(ep); + + /* + * Arch. management. Perform the necessary steps to flush all + * cpu caches. Currently we assume that the power level correspond + * the cache level. + * TODO : Introduce a mechanism to query the cache level to flush + * and the cpu-ops power down to perform from the platform. + */ + psci_do_pwrdown_cache_maintenance(max_off_lvl); +} + +/******************************************************************************* + * Top level handler which is called when a cpu wants to suspend its execution. + * It is assumed that along with suspending the cpu power domain, power domains + * at higher levels until the target power level will be suspended as well. It + * coordinates with the platform to negotiate the target state for each of + * the power domain level till the target power domain level. It then performs + * generic, architectural, platform setup and state management required to + * suspend that power domain level and power domain levels below it. + * e.g. For a cpu that's to be suspended, it could mean programming the + * power controller whereas for a cluster that's to be suspended, it will call + * the platform specific code which will disable coherency at the interconnect + * level if the cpu is the last in the cluster and also the program the power + * controller. + * + * All the required parameter checks are performed at the beginning and after + * the state transition has been done, no further error is expected and it is + * not possible to undo any of the actions taken beyond that point. + ******************************************************************************/ +void psci_cpu_suspend_start(entry_point_info_t *ep, + unsigned int end_pwrlvl, + psci_power_state_t *state_info, + unsigned int is_power_down_state) +{ + int skip_wfi = 0; + unsigned int idx = plat_my_core_pos(); + + /* + * This function must only be called on platforms where the + * CPU_SUSPEND platform hooks have been implemented. + */ + assert(psci_plat_pm_ops->pwr_domain_suspend && + psci_plat_pm_ops->pwr_domain_suspend_finish); + + /* + * This function acquires the lock corresponding to each power + * level so that by the time all locks are taken, the system topology + * is snapshot and state management can be done safely. + */ + psci_acquire_pwr_domain_locks(end_pwrlvl, + idx); + + /* + * We check if there are any pending interrupts after the delay + * introduced by lock contention to increase the chances of early + * detection that a wake-up interrupt has fired. + */ + if (read_isr_el1()) { + skip_wfi = 1; + goto exit; + } + + /* + * This function is passed the requested state info and + * it returns the negotiated state info for each power level upto + * the end level specified. + */ + psci_do_state_coordination(end_pwrlvl, state_info); + +#if ENABLE_PSCI_STAT + /* Update the last cpu for each level till end_pwrlvl */ + psci_stats_update_pwr_down(end_pwrlvl, state_info); +#endif + + if (is_power_down_state) + psci_suspend_to_pwrdown_start(end_pwrlvl, ep, state_info); + + /* + * Plat. management: Allow the platform to perform the + * necessary actions to turn off this cpu e.g. set the + * platform defined mailbox with the psci entrypoint, + * program the power controller etc. + */ + psci_plat_pm_ops->pwr_domain_suspend(state_info); + +#if ENABLE_PSCI_STAT + /* + * Capture time-stamp while entering low power state. + * No cache maintenance needed because caches are off + * and writes are direct to main memory. + */ + PMF_CAPTURE_TIMESTAMP(psci_svc, PSCI_STAT_ID_ENTER_LOW_PWR, + PMF_NO_CACHE_MAINT); +#endif + +exit: + /* + * Release the locks corresponding to each power level in the + * reverse order to which they were acquired. + */ + psci_release_pwr_domain_locks(end_pwrlvl, + idx); + if (skip_wfi) + return; +#if (PLAT_rcar && PMIC_ON_BOARD) + if ((uint32_t)end_pwrlvl==(uint32_t)PLAT_MAX_PWR_LVL) { + rcar_bl31_set_suspend_to_ram(); + } +#endif + + if (is_power_down_state) { + /* The function calls below must not return */ + if (psci_plat_pm_ops->pwr_domain_pwr_down_wfi) + psci_plat_pm_ops->pwr_domain_pwr_down_wfi(state_info); + else + psci_power_down_wfi(); + } + + /* + * We will reach here if only retention/standby states have been + * requested at multiple power levels. This means that the cpu + * context will be preserved. + */ + wfi(); + + /* + * After we wake up from context retaining suspend, call the + * context retaining suspend finisher. + */ + psci_suspend_to_standby_finisher(idx, end_pwrlvl); +} + +/******************************************************************************* + * The following functions finish an earlier suspend request. They + * are called by the common finisher routine in psci_common.c. The `state_info` + * is the psci_power_state from which this CPU has woken up from. + ******************************************************************************/ +void psci_cpu_suspend_finish(unsigned int cpu_idx, + psci_power_state_t *state_info) +{ + unsigned int counter_freq; + unsigned int max_off_lvl; + + /* Ensure we have been woken up from a suspended state */ + assert(psci_get_aff_info_state() == AFF_STATE_ON && is_local_state_off(\ + state_info->pwr_domain_state[PSCI_CPU_PWR_LVL])); + + /* + * Plat. management: Perform the platform specific actions + * before we change the state of the cpu e.g. enabling the + * gic or zeroing the mailbox register. If anything goes + * wrong then assert as there is no way to recover from this + * situation. + */ + psci_plat_pm_ops->pwr_domain_suspend_finish(state_info); + + /* + * Arch. management: Enable the data cache, manage stack memory and + * restore the stashed EL3 architectural context from the 'cpu_context' + * structure for this cpu. + */ + psci_do_pwrup_cache_maintenance(); + + /* Re-init the cntfrq_el0 register */ + counter_freq = plat_get_syscnt_freq2(); + write_cntfrq_el0(counter_freq); + + /* + * Call the cpu suspend finish handler registered by the Secure Payload + * Dispatcher to let it do any bookeeping. If the handler encounters an + * error, it's expected to assert within + */ + if (psci_spd_pm && psci_spd_pm->svc_suspend) { + max_off_lvl = psci_find_max_off_lvl(state_info); + assert (max_off_lvl != PSCI_INVALID_PWR_LVL); + psci_spd_pm->svc_suspend_finish(max_off_lvl); + } + + /* Invalidate the suspend level for the cpu */ + psci_set_suspend_pwrlvl(PSCI_INVALID_PWR_LVL); + + /* + * Generic management: Now we just need to retrieve the + * information that we had stashed away during the suspend + * call to set this cpu on its way. + */ + cm_prepare_el3_exit(NON_SECURE); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_system_off.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_system_off.c new file mode 100644 index 0000000..de9ec64 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/psci/psci_system_off.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "psci_private.h" + +void psci_system_off(void) +{ + psci_print_power_domain_map(); + + assert(psci_plat_pm_ops->system_off); + + /* Notify the Secure Payload Dispatcher */ + if (psci_spd_pm && psci_spd_pm->svc_system_off) { + psci_spd_pm->svc_system_off(); + } + + /* Call the platform specific hook */ + psci_plat_pm_ops->system_off(); + + /* This function does not return. We should never get here */ +} + +void psci_system_reset(void) +{ + psci_print_power_domain_map(); + + assert(psci_plat_pm_ops->system_reset); + + /* Notify the Secure Payload Dispatcher */ + if (psci_spd_pm && psci_spd_pm->svc_system_reset) { + psci_spd_pm->svc_system_reset(); + } + + /* Call the platform specific hook */ + psci_plat_pm_ops->system_reset(); + + /* This function does not return. We should never get here */ +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/semihosting/aarch32/semihosting_call.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/semihosting/aarch32/semihosting_call.S new file mode 100644 index 0000000..0cc707a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/semihosting/aarch32/semihosting_call.S @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + + .globl semihosting_call + +func semihosting_call + svc #0x123456 + bx lr +endfunc semihosting_call diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/semihosting/aarch64/semihosting_call.S b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/semihosting/aarch64/semihosting_call.S new file mode 100644 index 0000000..9fa8141 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/semihosting/aarch64/semihosting_call.S @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + + .globl semihosting_call + +func semihosting_call + hlt #0xf000 + ret +endfunc semihosting_call diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/semihosting/semihosting.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/semihosting/semihosting.c new file mode 100644 index 0000000..b4f53d2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/semihosting/semihosting.c @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#ifndef SEMIHOSTING_SUPPORTED +#define SEMIHOSTING_SUPPORTED 1 +#endif + +long semihosting_call(unsigned long operation, + void *system_block_address); + +typedef struct { + const char *file_name; + unsigned long mode; + size_t name_length; +} smh_file_open_block_t; + +typedef struct { + long handle; + uintptr_t buffer; + size_t length; +} smh_file_read_write_block_t; + +typedef struct { + long handle; + ssize_t location; +} smh_file_seek_block_t; + +typedef struct { + char *command_line; + size_t command_length; +} smh_system_block_t; + +long semihosting_connection_supported(void) +{ + return SEMIHOSTING_SUPPORTED; +} + +long semihosting_file_open(const char *file_name, size_t mode) +{ + smh_file_open_block_t open_block; + + open_block.file_name = file_name; + open_block.mode = mode; + open_block.name_length = strlen(file_name); + + return semihosting_call(SEMIHOSTING_SYS_OPEN, + (void *) &open_block); +} + +long semihosting_file_seek(long file_handle, ssize_t offset) +{ + smh_file_seek_block_t seek_block; + long result; + + seek_block.handle = file_handle; + seek_block.location = offset; + + result = semihosting_call(SEMIHOSTING_SYS_SEEK, + (void *) &seek_block); + + if (result) + result = semihosting_call(SEMIHOSTING_SYS_ERRNO, 0); + + return result; +} + +long semihosting_file_read(long file_handle, size_t *length, uintptr_t buffer) +{ + smh_file_read_write_block_t read_block; + long result = -EINVAL; + + if ((length == NULL) || (buffer == (uintptr_t)NULL)) + return result; + + read_block.handle = file_handle; + read_block.buffer = buffer; + read_block.length = *length; + + result = semihosting_call(SEMIHOSTING_SYS_READ, + (void *) &read_block); + + if (result == *length) { + return -EINVAL; + } else if (result < *length) { + *length -= result; + return 0; + } else + return result; +} + +long semihosting_file_write(long file_handle, + size_t *length, + const uintptr_t buffer) +{ + smh_file_read_write_block_t write_block; + long result = -EINVAL; + + if ((length == NULL) || (buffer == (uintptr_t)NULL)) + return -EINVAL; + + write_block.handle = file_handle; + write_block.buffer = (uintptr_t)buffer; /* cast away const */ + write_block.length = *length; + + result = semihosting_call(SEMIHOSTING_SYS_WRITE, + (void *) &write_block); + + *length = result; + + return (result == 0) ? 0 : -EINVAL; +} + +long semihosting_file_close(long file_handle) +{ + return semihosting_call(SEMIHOSTING_SYS_CLOSE, + (void *) &file_handle); +} + +long semihosting_file_length(long file_handle) +{ + return semihosting_call(SEMIHOSTING_SYS_FLEN, + (void *) &file_handle); +} + +char semihosting_read_char(void) +{ + return semihosting_call(SEMIHOSTING_SYS_READC, NULL); +} + +void semihosting_write_char(char character) +{ + semihosting_call(SEMIHOSTING_SYS_WRITEC, (void *) &character); +} + +void semihosting_write_string(char *string) +{ + semihosting_call(SEMIHOSTING_SYS_WRITE0, (void *) string); +} + +long semihosting_system(char *command_line) +{ + smh_system_block_t system_block; + + system_block.command_line = command_line; + system_block.command_length = strlen(command_line); + + return semihosting_call(SEMIHOSTING_SYS_SYSTEM, + (void *) &system_block); +} + +long semihosting_get_flen(const char *file_name) +{ + long file_handle; + size_t length; + + assert(semihosting_connection_supported()); + + file_handle = semihosting_file_open(file_name, FOPEN_MODE_RB); + if (file_handle == -1) + return file_handle; + + /* Find the length of the file */ + length = semihosting_file_length(file_handle); + + return semihosting_file_close(file_handle) ? -1 : length; +} + +long semihosting_download_file(const char *file_name, + size_t buf_size, + uintptr_t buf) +{ + long ret = -EINVAL; + size_t length; + long file_handle; + + /* Null pointer check */ + if (!buf) + return ret; + + assert(semihosting_connection_supported()); + + file_handle = semihosting_file_open(file_name, FOPEN_MODE_RB); + if (file_handle == -1) + return ret; + + /* Find the actual length of the file */ + length = semihosting_file_length(file_handle); + if (length == -1) + goto semihosting_fail; + + /* Signal error if we do not have enough space for the file */ + if (length > buf_size) + goto semihosting_fail; + + /* + * A successful read will return 0 in which case we pass back + * the actual number of bytes read. Else we pass a negative + * value indicating an error. + */ + ret = semihosting_file_read(file_handle, &length, buf); + if (ret) + goto semihosting_fail; + else + ret = length; + +semihosting_fail: + semihosting_file_close(file_handle); + return ret; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/abort.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/abort.c new file mode 100644 index 0000000..862bf9c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/abort.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* + * This is a basic implementation. This could be improved. + */ +void abort (void) +{ + ERROR("ABORT\n"); + panic(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/assert.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/assert.c new file mode 100644 index 0000000..90a1afe --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/assert.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* + * This is a basic implementation. This could be improved. + */ +void __assert (const char *function, const char *file, unsigned int line, + const char *assertion) +{ + tf_printf("ASSERT: %s <%d> : %s\n", function, line, assertion); + while(1); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/exit.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/exit.c new file mode 100644 index 0000000..3e77591 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/exit.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +void exit(int v) +{ + ERROR("EXIT\n"); + panic(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/mem.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/mem.c new file mode 100644 index 0000000..f1f335a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/mem.c @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include /* size_t */ + +/* + * Fill @count bytes of memory pointed to by @dst with @val + */ +void *memset(void *dst, int val, size_t count) +{ + char *ptr = dst; + + while (count--) + *ptr++ = val; + + return dst; +} + +/* + * Compare @len bytes of @s1 and @s2 + */ +int memcmp(const void *s1, const void *s2, size_t len) +{ + const char *s = s1; + const char *d = s2; + char dc; + char sc; + + while (len--) { + sc = *s++; + dc = *d++; + if (sc - dc) + return (sc - dc); + } + + return 0; +} + +/* + * Copy @len bytes from @src to @dst + */ +void *memcpy(void *dst, const void *src, size_t len) +{ + const char *s = src; + char *d = dst; + + while (len--) + *d++ = *s++; + + return dst; +} + +/* + * Move @len bytes from @src to @dst + */ +void *memmove(void *dst, const void *src, size_t len) +{ + /* + * The following test makes use of unsigned arithmetic overflow to + * more efficiently test the condition !(src <= dst && dst < str+len). + * It also avoids the situation where the more explicit test would give + * incorrect results were the calculation str+len to overflow (though + * that issue is probably moot as such usage is probably undefined + * behaviour and a bug anyway. + */ + if ((size_t)dst - (size_t)src >= len) { + /* destination not in source data, so can safely use memcpy */ + return memcpy(dst, src, len); + } else { + /* copy backwards... */ + const char *end = dst; + const char *s = (const char *)src + len; + char *d = (char *)dst + len; + while (d != end) + *--d = *--s; + } + return dst; +} + +/* + * Scan @len bytes of @src for value @c + */ +void *memchr(const void *src, int c, size_t len) +{ + const char *s = src; + + while (len--) { + if (*s == c) + return (void *) s; + s++; + } + + return NULL; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/printf.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/printf.c new file mode 100644 index 0000000..323ec0f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/printf.c @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/* Choose max of 128 chars for now. */ +#define PRINT_BUFFER_SIZE 128 +int printf(const char *fmt, ...) +{ + va_list args; + char buf[PRINT_BUFFER_SIZE]; + int count; + + va_start(args, fmt); + vsnprintf(buf, sizeof(buf) - 1, fmt, args); + va_end(args); + + /* Use putchar directly as 'puts()' adds a newline. */ + buf[PRINT_BUFFER_SIZE - 1] = '\0'; + count = 0; + while (buf[count]) + { + if (putchar(buf[count]) != EOF) { + count++; + } else { + count = EOF; + break; + } + } + + return count; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/putchar.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/putchar.c new file mode 100644 index 0000000..85e4fbd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/putchar.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/* Putchar() should either return the character printed or EOF in case of error. + * Our current console_putc() function assumes success and returns the + * character. Write all other printing functions in terms of putchar(), if + * possible, so they all benefit when this is improved. + */ +int putchar(int c) +{ + int res; + if (console_putc((unsigned char)c) >= 0) + res = c; + else + res = EOF; + + return res; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/puts.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/puts.c new file mode 100644 index 0000000..ca88fc5 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/puts.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +int puts(const char *s) +{ + int count = 0; + while(*s) + { + if (putchar(*s++) != EOF) { + count++; + } else { + count = EOF; + break; + } + } + + /* According to the puts(3) manpage, the function should write a + * trailing newline. + */ + if ((count != EOF) && (putchar('\n') != EOF)) + count++; + else + count = EOF; + + return count; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/sscanf.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/sscanf.c new file mode 100644 index 0000000..e9f5c4a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/sscanf.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/* + * TODO: This is not a real implementation of the sscanf() function. It just + * returns the number of expected arguments based on the number of '%' found + * in the format string. + */ +int +sscanf(const char *__restrict str, char const *__restrict fmt, ...) +{ + int ret = 0; + + while (*fmt != '\0') { + if (*fmt++ == '%') { + ret++; + } + } + + return ret; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/stdlib.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/stdlib.mk new file mode 100644 index 0000000..cdf3d29 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/stdlib.mk @@ -0,0 +1,47 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +STDLIB_SRCS := $(addprefix lib/stdlib/, \ + abort.c \ + assert.c \ + exit.c \ + mem.c \ + printf.c \ + putchar.c \ + puts.c \ + sscanf.c \ + strchr.c \ + strcmp.c \ + strlen.c \ + strncmp.c \ + subr_prf.c) + +INCLUDES += -Iinclude/lib/stdlib \ + -Iinclude/lib/stdlib/sys diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/strchr.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/strchr.c new file mode 100644 index 0000000..4247dcd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/strchr.c @@ -0,0 +1,52 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Portions copyright (c) 2013-2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#include +#include +#include + +char * +strchr(const char *p, int ch) +{ + char c; + + c = ch; + for (;; ++p) { + if (*p == c) + return ((char *)p); + if (*p == '\0') + return (NULL); + } + /* NOTREACHED */ +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/strcmp.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/strcmp.c new file mode 100644 index 0000000..bb86e0f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/strcmp.c @@ -0,0 +1,66 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Portions copyright (c) 2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#include +#include +#include + +/* + * Compare strings. + */ +int +strcmp(const char *s1, const char *s2) +{ + while (*s1 == *s2++) + if (*s1++ == '\0') + return 0; + return *(const unsigned char *)s1 - *(const unsigned char *)(s2 - 1); +} + +int +strcasecmp(const char *s1, const char *s2) +{ + const unsigned char *us1 = (const unsigned char *)s1; + const unsigned char *us2 = (const unsigned char *)s2; + + while (tolower(*us1) == tolower(*us2)) { + if (*us1++ == '\0') + return 0; + us2++; + } + return tolower(*us1) - tolower(*us2); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/strlen.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/strlen.c new file mode 100644 index 0000000..23c3d39 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/strlen.c @@ -0,0 +1,44 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Portions copyright (c) 2009-2014, ARM Limited and Contributors. All rights reserved. + */ + +#include + +size_t +strlen(str) + const char *str; +{ + register const char *s; + + for (s = str; *s; ++s); + return(s - str); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/strncmp.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/strncmp.c new file mode 100644 index 0000000..f45f4a2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/strncmp.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 1989, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Portions copyright (c) 2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#include +#include + +int +strncmp(const char *s1, const char *s2, size_t n) +{ + + if (n == 0) + return 0; + do { + if (*s1 != *s2++) + return (*(const unsigned char *)s1 - + *(const unsigned char *)(s2 - 1)); + if (*s1++ == '\0') + break; + } while (--n != 0); + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/subr_prf.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/subr_prf.c new file mode 100644 index 0000000..c103562 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/stdlib/subr_prf.c @@ -0,0 +1,548 @@ +/*- + * Copyright (c) 1986, 1988, 1991, 1993 + * The Regents of the University of California. All rights reserved. + * (c) UNIX System Laboratories, Inc. + * All or some portions of this file are derived from material licensed + * to the University of California by American Telephone and Telegraph + * Co. or Unix System Laboratories, Inc. and are reproduced herein with + * the permission of UNIX System Laboratories, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)subr_prf.c 8.3 (Berkeley) 1/21/94 + */ + +/* + * Portions copyright (c) 2009-2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +typedef unsigned char u_char; +typedef unsigned int u_int; +typedef int64_t quad_t; +typedef uint64_t u_quad_t; +typedef unsigned long u_long; +typedef unsigned short u_short; + +static inline int imax(int a, int b) { return (a > b ? a : b); } + +/* + * Note that stdarg.h and the ANSI style va_start macro is used for both + * ANSI and traditional C compilers. + */ + +#define TOCONS 0x01 +#define TOTTY 0x02 +#define TOLOG 0x04 + +/* Max number conversion buffer length: a u_quad_t in base 2, plus NUL byte. */ +#define MAXNBUF (sizeof(intmax_t) * 8 + 1) + +struct putchar_arg { + int flags; + int pri; + struct tty *tty; + char *p_bufr; + size_t n_bufr; + char *p_next; + size_t remain; +}; + +struct snprintf_arg { + char *str; + size_t remain; +}; + +extern int log_open; + +static char *ksprintn(char *nbuf, uintmax_t num, int base, int *len, int upper); +static void snprintf_func(int ch, void *arg); +static int kvprintf(char const *fmt, void (*func)(int, void*), void *arg, int radix, va_list ap); + +int vsnprintf(char *str, size_t size, const char *format, va_list ap); + +static char const hex2ascii_data[] = "0123456789abcdefghijklmnopqrstuvwxyz"; +#define hex2ascii(hex) (hex2ascii_data[hex]) + +/* + * Scaled down version of sprintf(3). + */ +int +sprintf(char *buf, const char *cfmt, ...) +{ + int retval; + va_list ap; + + va_start(ap, cfmt); + retval = kvprintf(cfmt, NULL, (void *)buf, 10, ap); + buf[retval] = '\0'; + va_end(ap); + return (retval); +} + +/* + * Scaled down version of vsprintf(3). + */ +int +vsprintf(char *buf, const char *cfmt, va_list ap) +{ + int retval; + + retval = kvprintf(cfmt, NULL, (void *)buf, 10, ap); + buf[retval] = '\0'; + return (retval); +} + +/* + * Scaled down version of snprintf(3). + */ +int +snprintf(char *str, size_t size, const char *format, ...) +{ + int retval; + va_list ap; + + va_start(ap, format); + retval = vsnprintf(str, size, format, ap); + va_end(ap); + return(retval); +} + +/* + * Scaled down version of vsnprintf(3). + */ +int +vsnprintf(char *str, size_t size, const char *format, va_list ap) +{ + struct snprintf_arg info; + int retval; + + info.str = str; + info.remain = size; + retval = kvprintf(format, snprintf_func, &info, 10, ap); + if (info.remain >= 1) + *info.str++ = '\0'; + return (retval); +} + +static void +snprintf_func(int ch, void *arg) +{ + struct snprintf_arg *const info = arg; + + if (info->remain >= 2) { + *info->str++ = ch; + info->remain--; + } +} + + +/* + * Kernel version which takes radix argument vsnprintf(3). + */ +int +vsnrprintf(char *str, size_t size, int radix, const char *format, va_list ap) +{ + struct snprintf_arg info; + int retval; + + info.str = str; + info.remain = size; + retval = kvprintf(format, snprintf_func, &info, radix, ap); + if (info.remain >= 1) + *info.str++ = '\0'; + return (retval); +} + + +/* + * Put a NUL-terminated ASCII number (base <= 36) in a buffer in reverse + * order; return an optional length and a pointer to the last character + * written in the buffer (i.e., the first character of the string). + * The buffer pointed to by `nbuf' must have length >= MAXNBUF. + */ +static char * +ksprintn(char *nbuf, uintmax_t num, int base, int *lenp, int upper) +{ + char *p, c; + + p = nbuf; + *p = '\0'; + do { + c = hex2ascii(num % base); + *++p = upper ? toupper(c) : c; + } while (num /= base); + if (lenp) + *lenp = p - nbuf; + return (p); +} + +/* + * Scaled down version of printf(3). + * + * Two additional formats: + * + * The format %b is supported to decode error registers. + * Its usage is: + * + * printf("reg=%b\n", regval, "*"); + * + * where is the output base expressed as a control character, e.g. + * \10 gives octal; \20 gives hex. Each arg is a sequence of characters, + * the first of which gives the bit number to be inspected (origin 1), and + * the next characters (up to a control character, i.e. a character <= 32), + * give the name of the register. Thus: + * + * kvprintf("reg=%b\n", 3, "\10\2BITTWO\1BITONE\n"); + * + * would produce output: + * + * reg=3 + * + * XXX: %D -- Hexdump, takes pointer and separator string: + * ("%6D", ptr, ":") -> XX:XX:XX:XX:XX:XX + * ("%*D", len, ptr, " " -> XX XX XX XX ... + */ +int +kvprintf(char const *fmt, void (*func)(int, void*), void *arg, int radix, va_list ap) +{ +#define PCHAR(c) {int cc=(c); if (func) (*func)(cc,arg); else *d++ = cc; retval++; } + char nbuf[MAXNBUF]; + char *d; + const char *p, *percent, *q; + u_char *up; + int ch, n; + uintmax_t num; + int base, lflag, qflag, tmp, width, ladjust, sharpflag, neg, sign, dot; + int cflag, hflag, jflag, tflag, zflag; + int dwidth, upper; + char padc; + int stop = 0, retval = 0; + + num = 0; + if (!func) + d = (char *) arg; + else + d = NULL; + + if (fmt == NULL) + fmt = "(fmt null)\n"; + + if (radix < 2 || radix > 36) + radix = 10; + + for (;;) { + padc = ' '; + width = 0; + while ((ch = (u_char)*fmt++) != '%' || stop) { + if (ch == '\0') + return (retval); + PCHAR(ch); + } + percent = fmt - 1; + qflag = 0; lflag = 0; ladjust = 0; sharpflag = 0; neg = 0; + sign = 0; dot = 0; dwidth = 0; upper = 0; + cflag = 0; hflag = 0; jflag = 0; tflag = 0; zflag = 0; +reswitch: switch (ch = (u_char)*fmt++) { + case '.': + dot = 1; + goto reswitch; + case '#': + sharpflag = 1; + goto reswitch; + case '+': + sign = 1; + goto reswitch; + case '-': + ladjust = 1; + goto reswitch; + case '%': + PCHAR(ch); + break; + case '*': + if (!dot) { + width = va_arg(ap, int); + if (width < 0) { + ladjust = !ladjust; + width = -width; + } + } else { + dwidth = va_arg(ap, int); + } + goto reswitch; + case '0': + if (!dot) { + padc = '0'; + goto reswitch; + } + case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + for (n = 0;; ++fmt) { + n = n * 10 + ch - '0'; + ch = *fmt; + if (ch < '0' || ch > '9') + break; + } + if (dot) + dwidth = n; + else + width = n; + goto reswitch; + case 'b': + num = (u_int)va_arg(ap, int); + p = va_arg(ap, char *); + for (q = ksprintn(nbuf, num, *p++, NULL, 0); *q;) + PCHAR(*q--); + + if (num == 0) + break; + + for (tmp = 0; *p;) { + n = *p++; + if (num & (1 << (n - 1))) { + PCHAR(tmp ? ',' : '<'); + for (; (n = *p) > ' '; ++p) + PCHAR(n); + tmp = 1; + } else + for (; *p > ' '; ++p) + continue; + } + if (tmp) + PCHAR('>'); + break; + case 'c': + PCHAR(va_arg(ap, int)); + break; + case 'D': + up = va_arg(ap, u_char *); + p = va_arg(ap, char *); + if (!width) + width = 16; + while(width--) { + PCHAR(hex2ascii(*up >> 4)); + PCHAR(hex2ascii(*up & 0x0f)); + up++; + if (width) + for (q=p;*q;q++) + PCHAR(*q); + } + break; + case 'd': + case 'i': + base = 10; + sign = 1; + goto handle_sign; + case 'h': + if (hflag) { + hflag = 0; + cflag = 1; + } else + hflag = 1; + goto reswitch; + case 'j': + jflag = 1; + goto reswitch; + case 'l': + if (lflag) { + lflag = 0; + qflag = 1; + } else + lflag = 1; + goto reswitch; + case 'n': + if (jflag) + *(va_arg(ap, intmax_t *)) = retval; + else if (qflag) + *(va_arg(ap, quad_t *)) = retval; + else if (lflag) + *(va_arg(ap, long *)) = retval; + else if (zflag) + *(va_arg(ap, size_t *)) = retval; + else if (hflag) + *(va_arg(ap, short *)) = retval; + else if (cflag) + *(va_arg(ap, char *)) = retval; + else + *(va_arg(ap, int *)) = retval; + break; + case 'o': + base = 8; + goto handle_nosign; + case 'p': + base = 16; + sharpflag = (width == 0); + sign = 0; + num = (uintptr_t)va_arg(ap, void *); + goto number; + case 'q': + qflag = 1; + goto reswitch; + case 'r': + base = radix; + if (sign) + goto handle_sign; + goto handle_nosign; + case 's': + p = va_arg(ap, char *); + if (p == NULL) + p = "(null)"; + if (!dot) + n = strlen (p); + else + for (n = 0; n < dwidth && p[n]; n++) + continue; + + width -= n; + + if (!ladjust && width > 0) + while (width--) + PCHAR(padc); + while (n--) + PCHAR(*p++); + if (ladjust && width > 0) + while (width--) + PCHAR(padc); + break; + case 't': + tflag = 1; + goto reswitch; + case 'u': + base = 10; + goto handle_nosign; + case 'X': + upper = 1; + case 'x': + base = 16; + goto handle_nosign; + case 'y': + base = 16; + sign = 1; + goto handle_sign; + case 'z': + zflag = 1; + goto reswitch; +handle_nosign: + sign = 0; + if (jflag) + num = va_arg(ap, uintmax_t); + else if (qflag) + num = va_arg(ap, u_quad_t); + else if (tflag) + num = va_arg(ap, ptrdiff_t); + else if (lflag) + num = va_arg(ap, u_long); + else if (zflag) + num = va_arg(ap, size_t); + else if (hflag) + num = (u_short)va_arg(ap, int); + else if (cflag) + num = (u_char)va_arg(ap, int); + else + num = va_arg(ap, u_int); + goto number; +handle_sign: + if (jflag) + num = va_arg(ap, intmax_t); + else if (qflag) + num = va_arg(ap, quad_t); + else if (tflag) + num = va_arg(ap, ptrdiff_t); + else if (lflag) + num = va_arg(ap, long); + else if (zflag) + num = va_arg(ap, ssize_t); + else if (hflag) + num = (short)va_arg(ap, int); + else if (cflag) + num = (char)va_arg(ap, int); + else + num = va_arg(ap, int); +number: + if (sign && (intmax_t)num < 0) { + neg = 1; + num = -(intmax_t)num; + } + p = ksprintn(nbuf, num, base, &n, upper); + tmp = 0; + if (sharpflag && num != 0) { + if (base == 8) + tmp++; + else if (base == 16) + tmp += 2; + } + if (neg) + tmp++; + + if (!ladjust && padc == '0') + dwidth = width - tmp; + width -= tmp + imax(dwidth, n); + dwidth -= n; + if (!ladjust) + while (width-- > 0) + PCHAR(' '); + if (neg) + PCHAR('-'); + if (sharpflag && num != 0) { + if (base == 8) { + PCHAR('0'); + } else if (base == 16) { + PCHAR('0'); + PCHAR('x'); + } + } + while (dwidth-- > 0) + PCHAR('0'); + + while (*p) + PCHAR(*p--); + + if (ladjust) + while (width-- > 0) + PCHAR(' '); + + break; + default: + while (percent < fmt) + PCHAR(*percent++); + /* + * Since we ignore an formatting argument it is no + * longer safe to obey the remaining formatting + * arguments as the arguments will no longer match + * the format specs. + */ + stop = 1; + break; + } + } +#undef PCHAR +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/xlat_tables/aarch32/xlat_tables.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/xlat_tables/aarch32/xlat_tables.c new file mode 100644 index 0000000..d70a6ef --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/xlat_tables/aarch32/xlat_tables.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "../xlat_tables_private.h" + +/* + * Each platform can define the size of the virtual address space, which is + * defined in ADDR_SPACE_SIZE. TTBCR.TxSZ is calculated as 32 minus the width + * of said address space. The value of TTBCR.TxSZ must be in the range 0 to + * 7 [1], which means that the virtual address space width must be in the range + * 32 to 25 bits. + * + * Here we calculate the initial lookup level from the value of ADDR_SPACE_SIZE. + * For a 4 KB page size, level 1 supports virtual address spaces of widths 32 + * to 31 bits, and level 2 from 30 to 25. Wider or narrower address spaces are + * not supported. As a result, level 3 cannot be used as initial lookup level + * with 4 KB granularity [1]. + * + * For example, for a 31-bit address space (i.e. ADDR_SPACE_SIZE == 1 << 31), + * TTBCR.TxSZ will be programmed to (32 - 31) = 1. According to Table G4-5 in + * the ARM ARM, the initial lookup level for such an address space is 1. + * + * See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more + * information: + * [1] Section G4.6.5 + */ + +#if ADDR_SPACE_SIZE > (1ULL << (32 - TTBCR_TxSZ_MIN)) + +# error "ADDR_SPACE_SIZE is too big." + +#elif ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT) + +# define XLAT_TABLE_LEVEL_BASE 1 +# define NUM_BASE_LEVEL_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) + +#elif ADDR_SPACE_SIZE >= (1 << (32 - TTBCR_TxSZ_MAX)) + +# define XLAT_TABLE_LEVEL_BASE 2 +# define NUM_BASE_LEVEL_ENTRIES (ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT) + +#else + +# error "ADDR_SPACE_SIZE is too small." + +#endif + +static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES] + __aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t)); + +void init_xlat_tables(void) +{ + unsigned long long max_pa; + uintptr_t max_va; + print_mmap(); + init_xlation_table(0, base_xlation_table, XLAT_TABLE_LEVEL_BASE, + &max_va, &max_pa); + assert(max_va < ADDR_SPACE_SIZE); +} + +/******************************************************************************* + * Function for enabling the MMU in Secure PL1, assuming that the + * page-tables have already been created. + ******************************************************************************/ +void enable_mmu_secure(unsigned int flags) +{ + unsigned int mair0, ttbcr, sctlr; + uint64_t ttbr0; + + assert(IS_IN_SECURE()); + assert((read_sctlr() & SCTLR_M_BIT) == 0); + + /* Set attributes in the right indices of the MAIR */ + mair0 = MAIR0_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); + mair0 |= MAIR0_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, + ATTR_IWBWA_OWBWA_NTR_INDEX); + mair0 |= MAIR0_ATTR_SET(ATTR_NON_CACHEABLE, + ATTR_NON_CACHEABLE_INDEX); + write_mair0(mair0); + + /* Invalidate TLBs at the current exception level */ + tlbiall(); + + /* + * Set TTBCR bits as well. Set TTBR0 table properties as Inner + * & outer WBWA & shareable. Disable TTBR1. + */ + ttbcr = TTBCR_EAE_BIT | + TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA | + TTBCR_RGN0_INNER_WBA | + (32 - __builtin_ctzl((uintptr_t)ADDR_SPACE_SIZE)); + ttbcr |= TTBCR_EPD1_BIT; + write_ttbcr(ttbcr); + + /* Set TTBR0 bits as well */ + ttbr0 = (uintptr_t) base_xlation_table; + write64_ttbr0(ttbr0); + write64_ttbr1(0); + + /* + * Ensure all translation table writes have drained + * into memory, the TLB invalidation is complete, + * and translation register writes are committed + * before enabling the MMU + */ + dsb(); + isb(); + + sctlr = read_sctlr(); + sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; + + if (flags & DISABLE_DCACHE) + sctlr &= ~SCTLR_C_BIT; + else + sctlr |= SCTLR_C_BIT; + + write_sctlr(sctlr); + + /* Ensure the MMU enable takes effect immediately */ + isb(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/xlat_tables/aarch64/xlat_tables.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/xlat_tables/aarch64/xlat_tables.c new file mode 100644 index 0000000..5b639b7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/xlat_tables/aarch64/xlat_tables.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "../xlat_tables_private.h" + +/* + * Each platform can define the size of the virtual address space, which is + * defined in ADDR_SPACE_SIZE. TCR.TxSZ is calculated as 64 minus the width of + * said address space. The value of TCR.TxSZ must be in the range 16 to 39 [1], + * which means that the virtual address space width must be in the range 48 to + * 25 bits. + * + * Here we calculate the initial lookup level from the value of ADDR_SPACE_SIZE. + * For a 4 KB page size, level 0 supports virtual address spaces of widths 48 to + * 40 bits, level 1 from 39 to 31, and level 2 from 30 to 25. Wider or narrower + * address spaces are not supported. As a result, level 3 cannot be used as + * initial lookup level with 4 KB granularity. [2] + * + * For example, for a 35-bit address space (i.e. ADDR_SPACE_SIZE == 1 << 35), + * TCR.TxSZ will be programmed to (64 - 35) = 29. According to Table D4-11 in + * the ARM ARM, the initial lookup level for such an address space is 1. + * + * See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more + * information: + * [1] Page 1730: 'Input address size', 'For all translation stages'. + * [2] Section D4.2.5 + */ + +#if ADDR_SPACE_SIZE > (1ULL << (64 - TCR_TxSZ_MIN)) + +# error "ADDR_SPACE_SIZE is too big." + +#elif ADDR_SPACE_SIZE > (1ULL << L0_XLAT_ADDRESS_SHIFT) + +# define XLAT_TABLE_LEVEL_BASE 0 +# define NUM_BASE_LEVEL_ENTRIES (ADDR_SPACE_SIZE >> L0_XLAT_ADDRESS_SHIFT) + +#elif ADDR_SPACE_SIZE > (1 << L1_XLAT_ADDRESS_SHIFT) + +# define XLAT_TABLE_LEVEL_BASE 1 +# define NUM_BASE_LEVEL_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT) + +#elif ADDR_SPACE_SIZE >= (1 << (64 - TCR_TxSZ_MAX)) + +# define XLAT_TABLE_LEVEL_BASE 2 +# define NUM_BASE_LEVEL_ENTRIES (ADDR_SPACE_SIZE >> L2_XLAT_ADDRESS_SHIFT) + +#else + +# error "ADDR_SPACE_SIZE is too small." + +#endif + +static uint64_t base_xlation_table[NUM_BASE_LEVEL_ENTRIES] + __aligned(NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t)); + +static unsigned long long tcr_ps_bits; + +static unsigned long long calc_physical_addr_size_bits( + unsigned long long max_addr) +{ + /* Physical address can't exceed 48 bits */ + assert((max_addr & ADDR_MASK_48_TO_63) == 0); + + /* 48 bits address */ + if (max_addr & ADDR_MASK_44_TO_47) + return TCR_PS_BITS_256TB; + + /* 44 bits address */ + if (max_addr & ADDR_MASK_42_TO_43) + return TCR_PS_BITS_16TB; + + /* 42 bits address */ + if (max_addr & ADDR_MASK_40_TO_41) + return TCR_PS_BITS_4TB; + + /* 40 bits address */ + if (max_addr & ADDR_MASK_36_TO_39) + return TCR_PS_BITS_1TB; + + /* 36 bits address */ + if (max_addr & ADDR_MASK_32_TO_35) + return TCR_PS_BITS_64GB; + + return TCR_PS_BITS_4GB; +} + +void init_xlat_tables(void) +{ + unsigned long long max_pa; + uintptr_t max_va; + print_mmap(); + init_xlation_table(0, base_xlation_table, XLAT_TABLE_LEVEL_BASE, + &max_va, &max_pa); + tcr_ps_bits = calc_physical_addr_size_bits(max_pa); + assert(max_va < ADDR_SPACE_SIZE); +} + +/******************************************************************************* + * Macro generating the code for the function enabling the MMU in the given + * exception level, assuming that the pagetables have already been created. + * + * _el: Exception level at which the function will run + * _tcr_extra: Extra bits to set in the TCR register. This mask will + * be OR'ed with the default TCR value. + * _tlbi_fct: Function to invalidate the TLBs at the current + * exception level + ******************************************************************************/ +#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \ + void enable_mmu_el##_el(unsigned int flags) \ + { \ + uint64_t mair, tcr, ttbr; \ + uint32_t sctlr; \ + \ + assert(IS_IN_EL(_el)); \ + assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \ + \ + /* Set attributes in the right indices of the MAIR */ \ + mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \ + mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \ + ATTR_IWBWA_OWBWA_NTR_INDEX); \ + mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, \ + ATTR_NON_CACHEABLE_INDEX); \ + write_mair_el##_el(mair); \ + \ + /* Invalidate TLBs at the current exception level */ \ + _tlbi_fct(); \ + \ + /* Set TCR bits as well. */ \ + /* Inner & outer WBWA & shareable. */ \ + /* Set T0SZ to (64 - width of virtual address space) */ \ + tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \ + TCR_RGN_INNER_WBA | \ + (64 - __builtin_ctzl(ADDR_SPACE_SIZE)); \ + tcr |= _tcr_extra; \ + write_tcr_el##_el(tcr); \ + \ + /* Set TTBR bits as well */ \ + ttbr = (uint64_t) base_xlation_table; \ + write_ttbr0_el##_el(ttbr); \ + \ + /* Ensure all translation table writes have drained */ \ + /* into memory, the TLB invalidation is complete, */ \ + /* and translation register writes are committed */ \ + /* before enabling the MMU */ \ + dsb(); \ + isb(); \ + \ + sctlr = read_sctlr_el##_el(); \ + sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \ + \ + if (flags & DISABLE_DCACHE) \ + sctlr &= ~SCTLR_C_BIT; \ + else \ + sctlr |= SCTLR_C_BIT; \ + \ + write_sctlr_el##_el(sctlr); \ + \ + /* Ensure the MMU enable takes effect immediately */ \ + isb(); \ + } + +/* Define EL1 and EL3 variants of the function enabling the MMU */ +DEFINE_ENABLE_MMU_EL(1, + (tcr_ps_bits << TCR_EL1_IPS_SHIFT), + tlbivmalle1) +DEFINE_ENABLE_MMU_EL(3, + TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT), + tlbialle3) diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/xlat_tables/xlat_tables_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/xlat_tables/xlat_tables_common.c new file mode 100644 index 0000000..7391faf --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/xlat_tables/xlat_tables_common.c @@ -0,0 +1,393 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE +#define LVL0_SPACER "" +#define LVL1_SPACER " " +#define LVL2_SPACER " " +#define LVL3_SPACER " " +#define get_level_spacer(level) \ + (((level) == 0) ? LVL0_SPACER : \ + (((level) == 1) ? LVL1_SPACER : \ + (((level) == 2) ? LVL2_SPACER : LVL3_SPACER))) +#define debug_print(...) tf_printf(__VA_ARGS__) +#else +#define debug_print(...) ((void)0) +#endif + +#define UNSET_DESC ~0ull + +static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES] + __aligned(XLAT_TABLE_SIZE) __section("xlat_table"); + +static unsigned next_xlat; +static unsigned long long xlat_max_pa; +static uintptr_t xlat_max_va; + +/* + * Array of all memory regions stored in order of ascending base address. + * The list is terminated by the first entry with size == 0. + */ +static mmap_region_t mmap[MAX_MMAP_REGIONS + 1]; + + +void print_mmap(void) +{ +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE + debug_print("mmap:\n"); + mmap_region_t *mm = mmap; + while (mm->size) { + debug_print(" VA:%p PA:0x%llx size:0x%zx attr:0x%x\n", + (void *)mm->base_va, mm->base_pa, + mm->size, mm->attr); + ++mm; + }; + debug_print("\n"); +#endif +} + +void mmap_add_region(unsigned long long base_pa, uintptr_t base_va, + size_t size, unsigned int attr) +{ + mmap_region_t *mm = mmap; + mmap_region_t *mm_last = mm + ARRAY_SIZE(mmap) - 1; + unsigned long long end_pa = base_pa + size - 1; + uintptr_t end_va = base_va + size - 1; + + assert(IS_PAGE_ALIGNED(base_pa)); + assert(IS_PAGE_ALIGNED(base_va)); + assert(IS_PAGE_ALIGNED(size)); + + if (!size) + return; + + assert(base_pa < end_pa); /* Check for overflows */ + assert(base_va < end_va); + +#if DEBUG + + /* Check for PAs and VAs overlaps with all other regions */ + for (mm = mmap; mm->size; ++mm) { + + uintptr_t mm_end_va = mm->base_va + mm->size - 1; + + /* + * Check if one of the regions is completely inside the other + * one. + */ + int fully_overlapped_va = + ((base_va >= mm->base_va) && (end_va <= mm_end_va)) || + ((mm->base_va >= base_va) && (mm_end_va <= end_va)); + + /* + * Full VA overlaps are only allowed if both regions are + * identity mapped (zero offset) or have the same VA to PA + * offset. Also, make sure that it's not the exact same area. + */ + if (fully_overlapped_va) { + assert((mm->base_va - mm->base_pa) == + (base_va - base_pa)); + assert((base_va != mm->base_va) || (size != mm->size)); + } else { + /* + * If the regions do not have fully overlapping VAs, + * then they must have fully separated VAs and PAs. + * Partial overlaps are not allowed + */ + + unsigned long long mm_end_pa = + mm->base_pa + mm->size - 1; + + int separated_pa = + (end_pa < mm->base_pa) || (base_pa > mm_end_pa); + int separated_va = + (end_va < mm->base_va) || (base_va > mm_end_va); +#if (IMAGE_BL31 && PLAT_rcar) + separated_pa = (int)bl31_plat_mmu_pa_chk(separated_pa, base_va, mm->base_pa); +#endif /* IMAGE_BL31 && PLAT_rcar */ + + assert(separated_va && separated_pa); + } + } + + mm = mmap; /* Restore pointer to the start of the array */ + +#endif /* DEBUG */ + + /* Find correct place in mmap to insert new region */ + while (mm->base_va < base_va && mm->size) + ++mm; + + /* + * If a section is contained inside another one with the same base + * address, it must be placed after the one it is contained in: + * + * 1st |-----------------------| + * 2nd |------------| + * 3rd |------| + * + * This is required for mmap_region_attr() to get the attributes of the + * small region correctly. + */ + while ((mm->base_va == base_va) && (mm->size > size)) + ++mm; + + /* Make room for new region by moving other regions up by one place */ + memmove(mm + 1, mm, (uintptr_t)mm_last - (uintptr_t)mm); + + /* Check we haven't lost the empty sentinal from the end of the array */ + assert(mm_last->size == 0); + + mm->base_pa = base_pa; + mm->base_va = base_va; + mm->size = size; + mm->attr = attr; + + if (end_pa > xlat_max_pa) + xlat_max_pa = end_pa; + if (end_va > xlat_max_va) + xlat_max_va = end_va; +} + +void mmap_add(const mmap_region_t *mm) +{ + while (mm->size) { + mmap_add_region(mm->base_pa, mm->base_va, mm->size, mm->attr); + ++mm; + } +} + +static uint64_t mmap_desc(unsigned attr, unsigned long long addr_pa, + int level) +{ + uint64_t desc; + int mem_type; + + desc = addr_pa; + /* + * There are different translation table descriptors for level 3 and the + * rest. + */ + desc |= (level == XLAT_TABLE_LEVEL_MAX) ? PAGE_DESC : BLOCK_DESC; + desc |= (attr & MT_NS) ? LOWER_ATTRS(NS) : 0; + desc |= (attr & MT_RW) ? LOWER_ATTRS(AP_RW) : LOWER_ATTRS(AP_RO); + desc |= LOWER_ATTRS(ACCESS_FLAG); + + /* + * Deduce shareability domain and executability of the memory region + * from the memory type. + * + * Data accesses to device memory and non-cacheable normal memory are + * coherent for all observers in the system, and correspondingly are + * always treated as being Outer Shareable. Therefore, for these 2 types + * of memory, it is not strictly needed to set the shareability field + * in the translation tables. + */ + mem_type = MT_TYPE(attr); + if (mem_type == MT_DEVICE) { + desc |= LOWER_ATTRS(ATTR_DEVICE_INDEX | OSH); + /* + * Always map device memory as execute-never. + * This is to avoid the possibility of a speculative instruction + * fetch, which could be an issue if this memory region + * corresponds to a read-sensitive peripheral. + */ + desc |= UPPER_ATTRS(XN); + } else { /* Normal memory */ + /* + * Always map read-write normal memory as execute-never. + * (Trusted Firmware doesn't self-modify its code, therefore + * R/W memory is reserved for data storage, which must not be + * executable.) + * Note that setting the XN bit here is for consistency only. + * The enable_mmu_elx() function sets the SCTLR_EL3.WXN bit, + * which makes any writable memory region to be treated as + * execute-never, regardless of the value of the XN bit in the + * translation table. + * + * For read-only memory, rely on the MT_EXECUTE/MT_EXECUTE_NEVER + * attribute to figure out the value of the XN bit. + */ + if ((attr & MT_RW) || (attr & MT_EXECUTE_NEVER)) + desc |= UPPER_ATTRS(XN); + + if (mem_type == MT_MEMORY) { + desc |= LOWER_ATTRS(ATTR_IWBWA_OWBWA_NTR_INDEX | ISH); + } else { + assert(mem_type == MT_NON_CACHEABLE); + desc |= LOWER_ATTRS(ATTR_NON_CACHEABLE_INDEX | OSH); + } + } + + debug_print((mem_type == MT_MEMORY) ? "MEM" : + ((mem_type == MT_NON_CACHEABLE) ? "NC" : "DEV")); + debug_print(attr & MT_RW ? "-RW" : "-RO"); + debug_print(attr & MT_NS ? "-NS" : "-S"); + debug_print(attr & MT_EXECUTE_NEVER ? "-XN" : "-EXEC"); + return desc; +} + +/* + * Returns attributes of area at `base_va` with size `size`. It returns the + * attributes of the innermost region that contains it. If there are partial + * overlaps, it returns -1, as a smaller size is needed. + */ +static int mmap_region_attr(mmap_region_t *mm, uintptr_t base_va, + size_t size) +{ + /* Don't assume that the area is contained in the first region */ + int attr = -1; + + /* + * Get attributes from last (innermost) region that contains the + * requested area. Don't stop as soon as one region doesn't contain it + * because there may be other internal regions that contain this area: + * + * |-----------------------------1-----------------------------| + * |----2----| |-------3-------| |----5----| + * |--4--| + * + * |---| <- Area we want the attributes of. + * + * In this example, the area is contained in regions 1, 3 and 4 but not + * in region 2. The loop shouldn't stop at region 2 as inner regions + * have priority over outer regions, it should stop at region 5. + */ + for (;; ++mm) { + + if (!mm->size) + return attr; /* Reached end of list */ + + if (mm->base_va > base_va + size - 1) + return attr; /* Next region is after area so end */ + + if (mm->base_va + mm->size - 1 < base_va) + continue; /* Next region has already been overtaken */ + + if (mm->attr == attr) + continue; /* Region doesn't override attribs so skip */ + + if (mm->base_va > base_va || + mm->base_va + mm->size - 1 < base_va + size - 1) + return -1; /* Region doesn't fully cover our area */ + + attr = mm->attr; + } +} + +static mmap_region_t *init_xlation_table_inner(mmap_region_t *mm, + uintptr_t base_va, + uint64_t *table, + int level) +{ + assert(level >= XLAT_TABLE_LEVEL_MIN && level <= XLAT_TABLE_LEVEL_MAX); + + unsigned int level_size_shift = + L0_XLAT_ADDRESS_SHIFT - level * XLAT_TABLE_ENTRIES_SHIFT; + u_register_t level_size = (u_register_t)1 << level_size_shift; + u_register_t level_index_mask = + ((u_register_t)XLAT_TABLE_ENTRIES_MASK) << level_size_shift; + + debug_print("New xlat table:\n"); + + do { + uint64_t desc = UNSET_DESC; + + if (!mm->size) { + /* Done mapping regions; finish zeroing the table */ + desc = INVALID_DESC; + } else if (mm->base_va + mm->size - 1 < base_va) { + /* This area is after the region so get next region */ + ++mm; + continue; + } + + debug_print("%s VA:%p size:0x%llx ", get_level_spacer(level), + (void *)base_va, (unsigned long long)level_size); + + if (mm->base_va > base_va + level_size - 1) { + /* Next region is after this area. Nothing to map yet */ + desc = INVALID_DESC; + } else { + /* + * Try to get attributes of this area. It will fail if + * there are partially overlapping regions. On success, + * it will return the innermost region's attributes. + */ + int attr = mmap_region_attr(mm, base_va, level_size); + if (attr >= 0) { + desc = mmap_desc(attr, + base_va - mm->base_va + mm->base_pa, + level); + } + } + + if (desc == UNSET_DESC) { + /* Area not covered by a region so need finer table */ + uint64_t *new_table = xlat_tables[next_xlat++]; + assert(next_xlat <= MAX_XLAT_TABLES); + desc = TABLE_DESC | (uintptr_t)new_table; + + /* Recurse to fill in new table */ + mm = init_xlation_table_inner(mm, base_va, + new_table, level+1); + } + + debug_print("\n"); + + *table++ = desc; + base_va += level_size; + } while ((base_va & level_index_mask) && (base_va - 1 < ADDR_SPACE_SIZE - 1)); + + return mm; +} + +void init_xlation_table(uintptr_t base_va, uint64_t *table, + int level, uintptr_t *max_va, + unsigned long long *max_pa) +{ + + init_xlation_table_inner(mmap, base_va, table, level); + *max_va = xlat_max_va; + *max_pa = xlat_max_pa; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/lib/xlat_tables/xlat_tables_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/xlat_tables/xlat_tables_private.h new file mode 100644 index 0000000..159d071 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/lib/xlat_tables/xlat_tables_private.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __XLAT_TABLES_PRIVATE_H__ +#define __XLAT_TABLES_PRIVATE_H__ + +#include +#include + +/* The virtual address space size must be a power of two. */ +CASSERT(IS_POWER_OF_TWO(ADDR_SPACE_SIZE), assert_valid_addr_space_size); + +void print_mmap(void); +void init_xlation_table(uintptr_t base_va, uint64_t *table, + int level, uintptr_t *max_va, + unsigned long long *max_pa); + +#endif /* __XLAT_TABLES_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/license.md b/IPL/SDK/v3m/src/arm-trusted-firmware/license.md new file mode 100644 index 0000000..941b741 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/license.md @@ -0,0 +1,26 @@ +Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. + +* Neither the name of ARM nor the names of its contributors may be used to + endorse or promote products derived from this software without specific prior + written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/build_env.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/build_env.mk new file mode 100644 index 0000000..62c7f68 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/build_env.mk @@ -0,0 +1,96 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# This file contains the logic to identify and include any relevant +# build environment specific make include files. + +ifndef BUILD_ENV_MK + BUILD_ENV_MK := $(lastword $(MAKEFILE_LIST)) + + # Block possible built-in command definitions that are not fully portable. + # This traps occurences that need replacing with our OS portable macros + COPY := $$(error "Replace COPY with call to SHELL_COPY or SHELL_COPY_TREE.") + CP := $$(error "Replace CP with call to SHELL_COPY or SHELL_COPY_TREE.") + DEL := $$(error "Replace DEL with call to SHELL_DELETE.") + MD := $$(error "Replace MD with call to MAKE_PREREQ_DIR.") + MKDIR := $$(error "Replace MKDIR with call to MAKE_PREREQ_DIR.") + RD := $$(error "Replace RD with call to SHELL_REMOVE_DIR.") + RM := $$(error "Replace RM with call to SHELL_DELETE.") + RMDIR := $$(error "Replace RMDIR with call to SHELL_REMOVE_DIR.") + + ENV_FILE_TO_INCLUDE := unix.mk + ifdef OSTYPE + ifneq ($(findstring ${OSTYPE}, cygwin),) + ENV_FILE_TO_INCLUDE := cygwin.mk + else + ifneq ($(findstring ${OSTYPE}, MINGW32 mingw msys),) + ENV_FILE_TO_INCLUDE := msys.mk + endif + endif + else + ifdef MSYSTEM + # Although the MINGW MSYS shell sets OSTYPE as msys in its environment, + # it does not appear in the GNU make view of environment variables. + # We use MSYSTEM as an alternative, as that is seen by make + ifneq ($(findstring ${MSYSTEM}, MINGW32 mingw msys),) + OSTYPE ?= msys + ENV_FILE_TO_INCLUDE := msys.mk + endif + else + ifdef OS + ifneq ($(findstring ${OS}, Windows_NT),) + ENV_FILE_TO_INCLUDE := windows.mk + endif + endif + endif + endif + include ${MAKE_HELPERS_DIRECTORY}${ENV_FILE_TO_INCLUDE} + ENV_FILE_TO_INCLUDE := + + ifndef SHELL_COPY + $(error "SHELL_COPY not defined for build environment.") + endif + ifndef SHELL_COPY_TREE + $(error "SHELL_COPY_TREE not defined for build environment.") + endif + ifndef SHELL_DELETE_ALL + $(error "SHELL_DELETE_ALL not defined for build environment.") + endif + ifndef SHELL_DELETE + $(error "SHELL_DELETE not defined for build environment.") + endif + ifndef MAKE_PREREQ_DIR + $(error "MAKE_PREREQ_DIR not defined for build environment.") + endif + ifndef SHELL_REMOVE_DIR + $(error "SHELL_REMOVE_DIR not defined for build environment.") + endif + +endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/build_macros.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/build_macros.mk new file mode 100644 index 0000000..edb5212 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/build_macros.mk @@ -0,0 +1,397 @@ +# +# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# Report an error if the eval make function is not available. +$(eval eval_available := T) +ifneq (${eval_available},T) + $(error This makefile only works with a Make program that supports $$(eval)) +endif + +# Some utility macros for manipulating awkward (whitespace) characters. +blank := +space :=${blank} ${blank} + +# A user defined function to recursively search for a filename below a directory +# $1 is the directory root of the recursive search (blank for current directory). +# $2 is the file name to search for. +define rwildcard +$(strip $(foreach d,$(wildcard ${1}*),$(call rwildcard,${d}/,${2}) $(filter $(subst *,%,%${2}),${d}))) +endef + +# This table is used in converting lower case to upper case. +uppercase_table:=a,A b,B c,C d,D e,E f,F g,G h,H i,I j,J k,K l,L m,M n,N o,O p,P q,Q r,R s,S t,T u,U v,V w,W x,X y,Y z,Z + +# Internal macro used for converting lower case to upper case. +# $(1) = upper case table +# $(2) = String to convert +define uppercase_internal +$(if $(1),$$(subst $(firstword $(1)),$(call uppercase_internal,$(wordlist 2,$(words $(1)),$(1)),$(2))),$(2)) +endef + +# A macro for converting a string to upper case +# $(1) = String to convert +define uppercase +$(eval uppercase_result:=$(call uppercase_internal,$(uppercase_table),$(1)))$(uppercase_result) +endef + +# Convenience function for adding build definitions +# $(eval $(call add_define,FOO)) will have: +# -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise +define add_define + DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +# Convenience function for adding build definitions +# $(eval $(call add_define_val,FOO,BAR)) will have: +# -DFOO=BAR +define add_define_val + DEFINES += -D$(1)=$(2) +endef + +# Convenience function for verifying option has a boolean value +# $(eval $(call assert_boolean,FOO)) will assert FOO is 0 or 1 +define assert_boolean + $(and $(patsubst 0,,$(value $(1))),$(patsubst 1,,$(value $(1))),$(error $(1) must be boolean)) +endef + +# IMG_LINKERFILE defines the linker script corresponding to a BL stage +# $(1) = BL stage (2, 30, 31, 32, 33) +define IMG_LINKERFILE + ${BUILD_DIR}/bl$(1).ld +endef + +# IMG_MAPFILE defines the output file describing the memory map corresponding +# to a BL stage +# $(1) = BL stage (2, 30, 31, 32, 33) +define IMG_MAPFILE + ${BUILD_DIR}/bl$(1).map +endef + +# IMG_ELF defines the elf file corresponding to a BL stage +# $(1) = BL stage (2, 30, 31, 32, 33) +define IMG_ELF + ${BUILD_DIR}/bl$(1).elf +endef + +# IMG_DUMP defines the symbols dump file corresponding to a BL stage +# $(1) = BL stage (2, 30, 31, 32, 33) +define IMG_DUMP + ${BUILD_DIR}/bl$(1).dump +endef + +# IMG_BIN defines the default image file corresponding to a BL stage +# $(1) = BL stage (2, 30, 31, 32, 33) +define IMG_BIN + ${BUILD_PLAT}/bl$(1).bin +endef + +# IMG_SREC defines the default srec file corresponding to a BL stage +# $(1) = BL stage (2, 30, 31, 32, 33) +define IMG_SREC + ${BUILD_PLAT}/bl$(1).srec +endef + +# FIP_ADD_PAYLOAD appends the command line arguments required by fiptool +# to package a new payload. Optionally, it adds the dependency on this payload +# $(1) = payload filename (i.e. bl31.bin) +# $(2) = command line option for the specified payload (i.e. --bl31) +# $(3) = fip target dependency (optional) (i.e. bl31) +define FIP_ADD_PAYLOAD + $(eval FIP_ARGS += $(2) $(1)) + $(eval $(if $(3),FIP_DEPS += $(3))) +endef + +# CERT_ADD_CMD_OPT adds a new command line option to the cert_create invocation +# $(1) = parameter filename +# $(2) = cert_create command line option for the specified parameter +# $(3) = input parameter (false if empty) +define CERT_ADD_CMD_OPT + $(eval $(if $(3),CRT_DEPS += $(1))) + $(eval CRT_ARGS += $(2) $(1)) +endef + +# FIP_ADD_IMG allows the platform to specify an image to be packed in the FIP +# using a build option. It also adds a dependency on the image file, aborting +# the build if the file does not exist. +# $(1) = build option to specify the image filename (SCP_BL2, BL33, etc) +# $(2) = command line option for fiptool (scp_bl2, bl33, etc) +# Example: +# $(eval $(call FIP_ADD_IMG,BL33,--bl33)) +define FIP_ADD_IMG + CRT_DEPS += check_$(1) + FIP_DEPS += check_$(1) + $(call FIP_ADD_PAYLOAD,$(value $(1)),$(2)) + +check_$(1): + $$(if $(value $(1)),,$$(error "Platform '${PLAT}' requires $(1). Please set $(1) to point to the right file")) +endef + +# FWU_FIP_ADD_PAYLOAD appends the command line arguments required by fiptool +# to package a new FWU payload. Optionally, it adds the dependency on this payload +# $(1) = payload filename (e.g. ns_bl2u.bin) +# $(2) = command line option for the specified payload (e.g. --fwu) +# $(3) = fip target dependency (optional) (e.g. ns_bl2u) +define FWU_FIP_ADD_PAYLOAD + $(eval $(if $(3),FWU_FIP_DEPS += $(3))) + $(eval FWU_FIP_ARGS += $(2) $(1)) +endef + +# FWU_CERT_ADD_CMD_OPT adds a new command line option to the cert_create invocation +# $(1) = parameter filename +# $(2) = cert_create command line option for the specified parameter +# $(3) = input parameter (false if empty) +define FWU_CERT_ADD_CMD_OPT + $(eval $(if $(3),FWU_CRT_DEPS += $(1))) + $(eval FWU_CRT_ARGS += $(2) $(1)) +endef + +# FWU_FIP_ADD_IMG allows the platform to pack a binary image in the FWU FIP +# $(1) build option to specify the image filename (BL2U, NS_BL2U, etc) +# $(2) command line option for fiptool (bl2u, ns_bl2u, etc) +# Example: +# $(eval $(call FWU_FIP_ADD_IMG,BL2U,--bl2u)) +define FWU_FIP_ADD_IMG + FWU_CRT_DEPS += check_$(1) + FWU_FIP_DEPS += check_$(1) + $(call FWU_FIP_ADD_PAYLOAD,$(value $(1)),$(2)) + +check_$(1): + $$(if $(value $(1)),,$$(error "Platform '${PLAT}' requires $(1). Please set $(1) to point to the right file")) +endef + +################################################################################ +# Auxiliary macros to build TF images from sources +################################################################################ + +# If no goal is specified in the command line, .DEFAULT_GOAL is used. +# .DEFAULT_GOAL is defined in the main Makefile before including this file. +ifeq ($(MAKECMDGOALS),) +MAKECMDGOALS := $(.DEFAULT_GOAL) +endif + +define match_goals +$(strip $(foreach goal,$(1),$(filter $(goal),$(MAKECMDGOALS)))) +endef + +# List of rules that involve building things +BUILD_TARGETS := all bl1 bl2 bl2u bl31 bl32 certificates fip + +# Does the list of goals specified on the command line include a build target? +ifneq ($(call match_goals,${BUILD_TARGETS}),) +IS_ANYTHING_TO_BUILD := 1 +endif + + +# MAKE_C builds a C source file and generates the dependency file +# $(1) = output directory +# $(2) = source file (%.c) +# $(3) = BL stage (2, 2u, 30, 31, 32, 33) +define MAKE_C + +$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2)))) +$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ))) +$(eval IMAGE := IMAGE_BL$(call uppercase,$(3))) + +$(OBJ): $(2) + @echo " CC $$<" + $$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -D$(IMAGE) -c $$< -o $$@ + +$(PREREQUISITES): $(2) | bl$(3)_dirs + @echo " DEPS $$@" + $$(Q)$$(CC) $$(TF_CFLAGS) $$(CFLAGS) -M -MT $(OBJ) -MF $$@ $$< + +ifdef IS_ANYTHING_TO_BUILD +-include $(PREREQUISITES) +endif + +endef + + +# MAKE_S builds an assembly source file and generates the dependency file +# $(1) = output directory +# $(2) = assembly file (%.S) +# $(3) = BL stage (2, 2u, 30, 31, 32, 33) +define MAKE_S + +$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2)))) +$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ))) +$(eval IMAGE := IMAGE_BL$(call uppercase,$(3))) + +$(OBJ): $(2) + @echo " AS $$<" + $$(Q)$$(AS) $$(ASFLAGS) -D$(IMAGE) -c $$< -o $$@ + +$(PREREQUISITES): $(2) | bl$(3)_dirs + @echo " DEPS $$@" + $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(OBJ) -MF $$@ $$< + +ifdef IS_ANYTHING_TO_BUILD +-include $(PREREQUISITES) +endif + +endef + + +# MAKE_LD generate the linker script using the C preprocessor +# $(1) = output linker script +# $(2) = input template +define MAKE_LD + +$(eval PREREQUISITES := $(1).d) + +$(1): $(2) + @echo " PP $$<" + $$(Q)$$(AS) $$(ASFLAGS) -P -E -D__LINKER__ -o $$@ $$< + +$(PREREQUISITES): $(2) | $(dir ${1}) + @echo " DEPS $$@" + $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(1) -MF $$@ $$< + +ifdef IS_ANYTHING_TO_BUILD +-include $(PREREQUISITES) +endif + +endef + + +# MAKE_OBJS builds both C and assembly source files +# $(1) = output directory +# $(2) = list of source files (both C and assembly) +# $(3) = BL stage (2, 30, 31, 32, 33) +define MAKE_OBJS + $(eval C_OBJS := $(filter %.c,$(2))) + $(eval REMAIN := $(filter-out %.c,$(2))) + $(eval $(foreach obj,$(C_OBJS),$(call MAKE_C,$(1),$(obj),$(3)))) + + $(eval S_OBJS := $(filter %.S,$(REMAIN))) + $(eval REMAIN := $(filter-out %.S,$(REMAIN))) + $(eval $(foreach obj,$(S_OBJS),$(call MAKE_S,$(1),$(obj),$(3)))) + + $(and $(REMAIN),$(error Unexpected source files present: $(REMAIN))) +endef + + +# NOTE: The line continuation '\' is required in the next define otherwise we +# end up with a line-feed characer at the end of the last c filename. +# Also bear this issue in mind if extending the list of supported filetypes. +define SOURCES_TO_OBJS + $(notdir $(patsubst %.c,%.o,$(filter %.c,$(1)))) \ + $(notdir $(patsubst %.S,%.o,$(filter %.S,$(1)))) +endef + + +# MAKE_TOOL_ARGS macro defines the command line arguments for fiptool for +# each BL image. Arguments: +# $(1) = BL stage (2, 30, 31, 32, 33) +# $(2) = Binary file +# $(3) = FIP command line option (if empty, image will not be included in the FIP) +define MAKE_TOOL_ARGS + $(if $(3),$(eval $(call FIP_ADD_PAYLOAD,$(2),--$(3),bl$(1)))) +endef + +# Allow overriding the timestamp, for example for reproducible builds, or to +# synchronize timestamps across multiple projects. +# This must be set to a C string (including quotes where applicable). +BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__ + +# MAKE_BL macro defines the targets and options to build each BL image. +# Arguments: +# $(1) = BL stage (2, 2u, 30, 31, 32, 33) +# $(2) = FIP command line option (if empty, image will not be included in the FIP) +define MAKE_BL + $(eval BUILD_DIR := ${BUILD_PLAT}/bl$(1)) + $(eval BL_SOURCES := $(BL$(call uppercase,$(1))_SOURCES)) + $(eval SOURCES := $(BL_SOURCES) $(BL_COMMON_SOURCES) $(PLAT_BL_COMMON_SOURCES)) + $(eval OBJS := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES)))) + $(eval LINKERFILE := $(call IMG_LINKERFILE,$(1))) + $(eval MAPFILE := $(call IMG_MAPFILE,$(1))) + $(eval ELF := $(call IMG_ELF,$(1))) + $(eval DUMP := $(call IMG_DUMP,$(1))) + $(eval BIN := $(call IMG_BIN,$(1))) + $(eval SREC := $(call IMG_SREC,$(1))) + $(eval BL_LINKERFILE := $(BL$(call uppercase,$(1))_LINKERFILE)) + # We use sort only to get a list of unique object directory names. + # ordering is not relevant but sort removes duplicates. + $(eval TEMP_OBJ_DIRS := $(sort $(BUILD_DIR)/ $(dir ${OBJS}))) + # The $(dir ) function leaves a trailing / on the directory names + # We append a . then strip /. from each, to remove the trailing / characters + # This gives names suitable for use as make rule targets. + $(eval OBJ_DIRS := $(subst /.,,$(addsuffix .,$(TEMP_OBJ_DIRS)))) + +# Create generators for object directory structure + +$(eval $(foreach objd,${OBJ_DIRS},$(call MAKE_PREREQ_DIR,${objd},))) + +.PHONY : bl${1}_dirs + +# We use order-only prerequisites to ensure that directories are created, +# but do not cause re-builds every time a file is written. +bl${1}_dirs: | ${OBJ_DIRS} + +$(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES),$(1))) +$(eval $(call MAKE_LD,$(LINKERFILE),$(BL_LINKERFILE))) + +$(ELF): $(OBJS) $(LINKERFILE) | bl$(1)_dirs + @echo " LD $$@" +ifdef MAKE_BUILD_STRINGS + $(call MAKE_BUILD_STRINGS, $(BUILD_DIR)/build_message.o) +else + @echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP); \ + const char version_string[] = "${VERSION_STRING}";' | \ + $$(CC) $$(TF_CFLAGS) $$(CFLAGS) -xc - -o $(BUILD_DIR)/build_message.o +endif + $$(Q)$$(LD) -o $$@ $$(LDFLAGS) -Map=$(MAPFILE) --script $(LINKERFILE) \ + $(BUILD_DIR)/build_message.o $(OBJS) + +$(DUMP): $(ELF) + @echo " OD $$@" + $${Q}$${OD} -dx $$< > $$@ + +$(BIN): $(ELF) + @echo " BIN $$@" + $$(Q)$$(OC) -O binary $$< $$@ + @echo + @echo "Built $$@ successfully" + @echo + +$(SREC): $(ELF) + @echo " SREC $$@" + $$(Q)$$(OC) -O srec $$< $$@ + +.PHONY: bl$(1) +bl$(1): $(SREC) $(BIN) $(DUMP) + +all: bl$(1) + +$(eval $(call MAKE_TOOL_ARGS,$(1),$(BIN),$(2))) + +endef + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/cygwin.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/cygwin.mk new file mode 100644 index 0000000..e69c0b1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/cygwin.mk @@ -0,0 +1,43 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# + +# OS specific definitions for builds in a Cygwin environment. +# Cygwin allows us to use unix style commands on a windows platform. + +ifndef CYGWIN_MK + CYGWIN_MK := $(lastword $(MAKEFILE_LIST)) + + include ${MAKE_HELPERS_DIRECTORY}unix.mk + + # In cygwin executable files have the Windows .exe extension type. + BIN_EXT := .exe + +endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/msys.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/msys.mk new file mode 100644 index 0000000..188dc6c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/msys.mk @@ -0,0 +1,44 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# + +# OS specific definitions for builds in a Mingw32 MSYS environment. +# Mingw32 allows us to use some unix style commands on a windows platform. + +ifndef MSYS_MK + MSYS_MK := $(lastword $(MAKEFILE_LIST)) + + include ${MAKE_HELPERS_DIRECTORY}unix.mk + + # In MSYS executable files have the Windows .exe extension type. + BIN_EXT := .exe + +endif + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/plat_helpers.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/plat_helpers.mk new file mode 100644 index 0000000..85ba84f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/plat_helpers.mk @@ -0,0 +1,62 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +################################################################################ +# Helpers for finding and referencing platform directories +################################################################################ + +ifndef PLAT_HELPERS_MK + PLAT_HELPERS_MK := $(lastword $(MAKEFILE_LIST)) + + ifeq (${PLAT},) + $(error "Error: Unknown platform. Please use PLAT= to specify the platform") + endif + + # PLATFORM_ROOT can be overridden for when building tools directly + PLATFORM_ROOT ?= plat/ + PLAT_MAKEFILE := platform.mk + + # Generate the platforms list by recursively searching for all directories + # under /plat containing a PLAT_MAKEFILE. Append each platform with a `|` + # char and strip out the final '|'. + ALL_PLATFORM_MK_FILES := $(call rwildcard,${PLATFORM_ROOT},${PLAT_MAKEFILE}) + ALL_PLATFORM_DIRS := $(patsubst %/,%,$(dir ${ALL_PLATFORM_MK_FILES})) + ALL_PLATFORMS := $(sort $(notdir ${ALL_PLATFORM_DIRS})) + + PLAT_MAKEFILE_FULL := $(filter %/${PLAT}/${PLAT_MAKEFILE},${ALL_PLATFORM_MK_FILES}) + PLATFORM_LIST := $(subst ${space},|,${ALL_PLATFORMS}) + ifeq ($(PLAT_MAKEFILE_FULL),) + $(error "Error: Invalid platform. The following platforms are available: ${PLATFORM_LIST}") + endif + + # Record the directory where the platform make file was found. + PLAT_DIR := $(dir ${PLAT_MAKEFILE_FULL}) + +endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/tbbr/tbbr_tools.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/tbbr/tbbr_tools.mk new file mode 100644 index 0000000..8d3f14f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/tbbr/tbbr_tools.mk @@ -0,0 +1,144 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# This file defines the keys and certificates that must be created to establish +# a Chain of Trust following the TBBR document. These definitions include the +# command line options passed to the cert_create and fiptool commands. +# +# Expected environment: +# +# BUILD_PLAT: output directory +# NEED_BL32: indicates whether BL32 is needed by the platform +# BL2: image filename (optional). Default is IMG_BIN(2) (see macro IMG_BIN) +# SCP_BL2: image filename (optional). Default is IMG_BIN(30) +# BL31: image filename (optional). Default is IMG_BIN(31) +# BL32: image filename (optional). Default is IMG_BIN(32) +# BL33: image filename (optional). Default is IMG_BIN(33) +# +# Build options added by this file: +# +# KEY_ALG +# ROT_KEY +# TRUSTED_WORLD_KEY +# NON_TRUSTED_WORLD_KEY +# SCP_BL2_KEY +# BL31_KEY +# BL32_KEY +# BL33_KEY +# + +# Certificate generation tool default parameters +TRUSTED_KEY_CERT := ${BUILD_PLAT}/trusted_key.crt +FWU_CERT := ${BUILD_PLAT}/fwu_cert.crt + +# Default non-volatile counter values (overridable by the platform) +TFW_NVCTR_VAL ?= 0 +NTFW_NVCTR_VAL ?= 0 + +# Pass the non-volatile counters to the cert_create tool +$(eval $(call CERT_ADD_CMD_OPT,${TFW_NVCTR_VAL},--tfw-nvctr)) +$(eval $(call CERT_ADD_CMD_OPT,${NTFW_NVCTR_VAL},--ntfw-nvctr)) + +# Add Trusted Key certificate to the fiptool and cert_create command line options +$(eval $(call FIP_ADD_PAYLOAD,${TRUSTED_KEY_CERT},--trusted-key-cert)) +$(eval $(call CERT_ADD_CMD_OPT,${TRUSTED_KEY_CERT},--trusted-key-cert)) + +# Add fwu certificate to the fiptool and cert_create command line options +$(eval $(call FWU_FIP_ADD_PAYLOAD,${FWU_CERT},--fwu-cert)) +$(eval $(call FWU_CERT_ADD_CMD_OPT,${FWU_CERT},--fwu-cert)) + +# Add the keys to the cert_create command line options (private keys are NOT +# packed in the FIP). Developers can use their own keys by specifying the proper +# build option in the command line when building the Trusted Firmware +$(if ${KEY_ALG},$(eval $(call CERT_ADD_CMD_OPT,${KEY_ALG},--key-alg))) +$(if ${ROT_KEY},$(eval $(call CERT_ADD_CMD_OPT,${ROT_KEY},--rot-key))) +$(if ${ROT_KEY},$(eval $(call FWU_CERT_ADD_CMD_OPT,${ROT_KEY},--rot-key))) +$(if ${TRUSTED_WORLD_KEY},$(eval $(call CERT_ADD_CMD_OPT,${TRUSTED_WORLD_KEY},--trusted-world-key))) +$(if ${NON_TRUSTED_WORLD_KEY},$(eval $(call CERT_ADD_CMD_OPT,${NON_TRUSTED_WORLD_KEY},--non-trusted-world-key))) + +# Add the BL2 CoT (image cert + image) +$(if ${BL2},$(eval $(call CERT_ADD_CMD_OPT,${BL2},--tb-fw,true)),\ + $(eval $(call CERT_ADD_CMD_OPT,$(call IMG_BIN,2),--tb-fw,true))) +$(eval $(call CERT_ADD_CMD_OPT,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert)) +$(eval $(call FIP_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert)) + +# Add the SCP_BL2 CoT (key cert + img cert + image) +ifneq (${SCP_BL2},) + $(eval $(call CERT_ADD_CMD_OPT,${SCP_BL2},--scp-fw,true)) + $(if ${SCP_BL2_KEY},$(eval $(call CERT_ADD_CMD_OPT,${SCP_BL2_KEY},--scp-fw-key))) + $(eval $(call CERT_ADD_CMD_OPT,${BUILD_PLAT}/scp_fw_content.crt,--scp-fw-cert)) + $(eval $(call CERT_ADD_CMD_OPT,${BUILD_PLAT}/scp_fw_key.crt,--scp-fw-key-cert)) + $(eval $(call FIP_ADD_PAYLOAD,${BUILD_PLAT}/scp_fw_content.crt,--scp-fw-cert)) + $(eval $(call FIP_ADD_PAYLOAD,${BUILD_PLAT}/scp_fw_key.crt,--scp-fw-key-cert)) +endif + +# Add the BL31 CoT (key cert + img cert + image) +$(if ${BL31},$(eval $(call CERT_ADD_CMD_OPT,${BL31},--soc-fw,true)),\ + $(eval $(call CERT_ADD_CMD_OPT,$(call IMG_BIN,31),--soc-fw,true))) +$(if ${BL31_KEY},$(eval $(call CERT_ADD_CMD_OPT,${BL31_KEY},--soc-fw-key))) +$(eval $(call CERT_ADD_CMD_OPT,${BUILD_PLAT}/soc_fw_content.crt,--soc-fw-cert)) +$(eval $(call CERT_ADD_CMD_OPT,${BUILD_PLAT}/soc_fw_key.crt,--soc-fw-key-cert)) +$(eval $(call FIP_ADD_PAYLOAD,${BUILD_PLAT}/soc_fw_content.crt,--soc-fw-cert)) +$(eval $(call FIP_ADD_PAYLOAD,${BUILD_PLAT}/soc_fw_key.crt,--soc-fw-key-cert)) + +# Add the BL32 CoT (key cert + img cert + image) +ifeq (${NEED_BL32},yes) + $(if ${BL32},$(eval $(call CERT_ADD_CMD_OPT,${BL32},--tos-fw,true)),\ + $(if ${BL32_SOURCES},$(eval $(call CERT_ADD_CMD_OPT,$(call IMG_BIN,32),--tos-fw,true)))) + $(if ${BL32_KEY},$(eval $(call CERT_ADD_CMD_OPT,${BL32_KEY},--tos-fw-key))) + $(eval $(call CERT_ADD_CMD_OPT,${BUILD_PLAT}/tos_fw_content.crt,--tos-fw-cert)) + $(eval $(call CERT_ADD_CMD_OPT,${BUILD_PLAT}/tos_fw_key.crt,--tos-fw-key-cert)) + $(eval $(call FIP_ADD_PAYLOAD,${BUILD_PLAT}/tos_fw_content.crt,--tos-fw-cert)) + $(eval $(call FIP_ADD_PAYLOAD,${BUILD_PLAT}/tos_fw_key.crt,--tos-fw-key-cert)) +endif + +# Add the BL33 CoT (key cert + img cert + image) +ifneq (${BL33},) + $(eval $(call CERT_ADD_CMD_OPT,${BL33},--nt-fw,true)) + $(if ${BL33_KEY},$(eval $(call CERT_ADD_CMD_OPT,${BL33_KEY},--nt-fw-key))) + $(eval $(call CERT_ADD_CMD_OPT,${BUILD_PLAT}/nt_fw_content.crt,--nt-fw-cert)) + $(eval $(call CERT_ADD_CMD_OPT,${BUILD_PLAT}/nt_fw_key.crt,--nt-fw-key-cert)) + $(eval $(call FIP_ADD_PAYLOAD,${BUILD_PLAT}/nt_fw_content.crt,--nt-fw-cert)) + $(eval $(call FIP_ADD_PAYLOAD,${BUILD_PLAT}/nt_fw_key.crt,--nt-fw-key-cert)) +endif + +# Add the BL2U image +$(if ${BL2U},$(eval $(call FWU_CERT_ADD_CMD_OPT,${BL2U},--ap-fwu-cfg,true)),\ + $(eval $(call FWU_CERT_ADD_CMD_OPT,$(call IMG_BIN,2u),--ap-fwu-cfg,true))) + +# Add the SCP_BL2U image +ifneq (${SCP_BL2U},) + $(eval $(call FWU_CERT_ADD_CMD_OPT,${SCP_BL2U},--scp-fwu-cfg,true)) +endif + +# Add the NS_BL2U image +ifneq (${NS_BL2U},) + $(eval $(call FWU_CERT_ADD_CMD_OPT,${NS_BL2U},--fwu,true)) +endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/unix.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/unix.mk new file mode 100644 index 0000000..ab60435 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/unix.mk @@ -0,0 +1,81 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# + +# Trusted Firmware shell command definitions for a Unix style environment. + +ifndef UNIX_MK + UNIX_MK := $(lastword $(MAKEFILE_LIST)) + + ECHO_BLANK_LINE := echo + + DIR_DELIM := / + PATH_SEP := : + + # These defines provide Unix style equivalents of the shell commands + # required by the Trusted Firmware build environment. + + # ${1} is the file to be copied. + # ${2} is the destination file name. + define SHELL_COPY + ${Q}cp -f "${1}" "${2}" + endef + + # ${1} is the directory to be copied. + # ${2} is the destination directory path. + define SHELL_COPY_TREE + ${Q}cp -rf "${1}" "${2}" + endef + + # ${1} is the file to be deleted. + define SHELL_DELETE + -${Q}rm -f "${1}" + endef + + # ${1} is a space delimited list of files to be deleted. + # Note that we do not quote ${1}, as multiple parameters may be passed. + define SHELL_DELETE_ALL + -${Q}rm -rf ${1} + endef + + # ${1} is the directory to be generated. + # ${2} is optional, and allows a prerequisite to be specified. + define MAKE_PREREQ_DIR + +${1} : ${2} + ${Q}mkdir -p "${1}" + + endef + + define SHELL_REMOVE_DIR + -${Q}rm -rf "${1}" + endef + +endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/windows.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/windows.mk new file mode 100644 index 0000000..fe5e8c1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/make_helpers/windows.mk @@ -0,0 +1,109 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# + +# OS specific parts for builds in a Windows_NT environment. The +# environment variable OS is set to Windows_NT on all modern Windows platforms + +# Include generic windows command definitions. + +ifndef WINDOWS_MK + WINDOWS_MK := $(lastword $(MAKEFILE_LIST)) + + ECHO_BLANK_LINE := @cmd /c echo. + DIR_DELIM := $(strip \) + BIN_EXT := .exe + PATH_SEP := ; + + # For some Windows native commands there is a problem with the directory delimiter. + # Make uses / (slash) and the commands expect \ (backslash) + # We have to provide a means of translating these, so we define local functions. + + # ${1} is the file to be copied. + # ${2} is the destination file name. + define SHELL_COPY + $(eval tmp_from_file:=$(subst /,\,${1})) + $(eval tmp_to_file:=$(subst /,\,${2})) + copy "${tmp_from_file}" "${tmp_to_file}" + endef + + # ${1} is the directory to be copied. + # ${2} is the destination directory path. + define SHELL_COPY_TREE + $(eval tmp_from_dir:=$(subst /,\,${1})) + $(eval tmp_to_dir:=$(subst /,\,${2})) + xcopy /HIVE "${tmp_from_dir}" "${tmp_to_dir}" + endef + + # ${1} is the file to be deleted. + define SHELL_DELETE + $(eval tmp_del_file:=$(subst /,\,${*})) + -@if exist $(tmp_del_file) del /Q $(tmp_del_file) + endef + + # ${1} is a space delimited list of files to be deleted. + define SHELL_DELETE_ALL + $(eval $(foreach filename,$(wildcard ${1}),$(call DELETE_IF_THERE,${filename}))) + endef + + # ${1} is the directory to be generated. + # ${2} is optional, and allows prerequisites to be specified. + define MAKE_PREREQ_DIR + +${1} : ${2} + $(eval tmp_dir:=$(subst /,\,${1})) + -@if not exist "$(tmp_dir)" mkdir "${tmp_dir}" + + endef + + # ${1} is the directory to be removed. + define SHELL_REMOVE_DIR + $(eval tmp_dir:=$(subst /,\,${1})) + -@if exist "$(tmp_dir)" rd /Q /S "$(tmp_dir)" + endef + +endif + +# Because git is not available from CMD.EXE, we need to avoid +# the BUILD_STRING generation which uses git. +# For now we use "development build". +# This can be overridden from the command line or environment. +BUILD_STRING ?= development build + +# The DOS echo shell command does not strip ' characters from the command +# parameters before printing. We therefore use an alternative method invoked +# by defining the MAKE_BUILD_STRINGS macro. +BUILT_TIME_DATE_STRING = const char build_message[] = "Built : "${BUILD_MESSAGE_TIMESTAMP}; +VERSION_STRING_MESSAGE = const char version_string[] = "${VERSION_STRING}"; +define MAKE_BUILD_STRINGS + @echo $$(BUILT_TIME_DATE_STRING) $$(VERSION_STRING_MESSAGE) | \ + $$(CC) $$(TF_CFLAGS) $$(CFLAGS) -x c - -o $1 +endef + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/aarch32/board_arm_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/aarch32/board_arm_helpers.S new file mode 100644 index 0000000..893267b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/aarch32/board_arm_helpers.S @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + + .globl plat_report_exception + + + /* ------------------------------------------------------- + * void plat_report_exception(unsigned int type) + * Function to report an unhandled exception + * with platform-specific means. + * On FVP platform, it updates the LEDs + * to indicate where we are. + * SYS_LED[0] - 0x0 + * SYS_LED[2:1] - 0x0 + * SYS_LED[7:3] - Exception Mode. + * Clobbers: r0-r1 + * ------------------------------------------------------- + */ +func plat_report_exception + lsl r0, r0, #V2M_SYS_LED_EC_SHIFT + ldr r1, =V2M_SYSREGS_BASE + add r1, r1, #V2M_SYS_LED + str r0, [r1] + bx lr +endfunc plat_report_exception diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/aarch64/board_arm_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/aarch64/board_arm_helpers.S new file mode 100644 index 0000000..80c5759 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/aarch64/board_arm_helpers.S @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + + .globl plat_report_exception + + + /* --------------------------------------------- + * void plat_report_exception(unsigned int type) + * Function to report an unhandled exception + * with platform-specific means. + * On FVP platform, it updates the LEDs + * to indicate where we are + * --------------------------------------------- + */ +func plat_report_exception + mrs x1, CurrentEl + lsr x1, x1, #MODE_EL_SHIFT + lsl x1, x1, #V2M_SYS_LED_EL_SHIFT + lsl x0, x0, #V2M_SYS_LED_EC_SHIFT + mov x2, #(SECURE << V2M_SYS_LED_SS_SHIFT) + orr x0, x0, x2 + orr x0, x0, x1 + mov x1, #V2M_SYSREGS_BASE + add x1, x1, #V2M_SYS_LED + str w0, [x1] + ret +endfunc plat_report_exception diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/board_arm_trusted_boot.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/board_arm_trusted_boot.c new file mode 100644 index 0000000..fd9e9f6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/board_arm_trusted_boot.c @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* Weak definition may be overridden in specific platform */ +#pragma weak plat_match_rotpk +#pragma weak plat_get_nv_ctr +#pragma weak plat_set_nv_ctr + +/* SHA256 algorithm */ +#define SHA256_BYTES 32 + +/* ROTPK locations */ +#define ARM_ROTPK_REGS_ID 1 +#define ARM_ROTPK_DEVEL_RSA_ID 2 + +#if !ARM_ROTPK_LOCATION_ID + #error "ARM_ROTPK_LOCATION_ID not defined" +#endif + +static const unsigned char rotpk_hash_hdr[] = \ + "\x30\x31\x30\x0D\x06\x09\x60\x86\x48" \ + "\x01\x65\x03\x04\x02\x01\x05\x00\x04\x20"; +static const unsigned int rotpk_hash_hdr_len = sizeof(rotpk_hash_hdr) - 1; +static unsigned char rotpk_hash_der[sizeof(rotpk_hash_hdr) - 1 + SHA256_BYTES]; + +#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) +static const unsigned char arm_devel_rotpk_hash[] = \ + "\xB0\xF3\x82\x09\x12\x97\xD8\x3A" \ + "\x37\x7A\x72\x47\x1B\xEC\x32\x73" \ + "\xE9\x92\x32\xE2\x49\x59\xF6\x5E" \ + "\x8B\x4A\x4A\x46\xD8\x22\x9A\xDA"; +#endif + +/* + * Return the ROTPK hash in the following ASN.1 structure in DER format: + * + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL + * } + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm AlgorithmIdentifier, + * digest OCTET STRING + * } + */ +int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, + unsigned int *flags) +{ + uint8_t *dst; + + assert(key_ptr != NULL); + assert(key_len != NULL); + assert(flags != NULL); + + /* Copy the DER header */ + memcpy(rotpk_hash_der, rotpk_hash_hdr, rotpk_hash_hdr_len); + dst = (uint8_t *)&rotpk_hash_der[rotpk_hash_hdr_len]; + +#if (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) + memcpy(dst, arm_devel_rotpk_hash, SHA256_BYTES); +#elif (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_REGS_ID) + uint32_t *src, tmp; + unsigned int words, i; + + /* + * Append the hash from Trusted Root-Key Storage registers. The hash has + * not been written linearly into the registers, so we have to do a bit + * of byte swapping: + * + * 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C + * +---------------------------------------------------------------+ + * | Reg0 | Reg1 | Reg2 | Reg3 | Reg4 | Reg5 | Reg6 | Reg7 | + * +---------------------------------------------------------------+ + * | ... ... | | ... ... | + * | +--------------------+ | +-------+ + * | | | | + * +----------------------------+ +----------------------------+ + * | | | | + * +-------+ | +--------------------+ | + * | | | | + * v v v v + * +---------------------------------------------------------------+ + * | | | + * +---------------------------------------------------------------+ + * 0 15 16 31 + * + * Additionally, we have to access the registers in 32-bit words + */ + words = SHA256_BYTES >> 3; + + /* Swap bytes 0-15 (first four registers) */ + src = (uint32_t *)TZ_PUB_KEY_HASH_BASE; + for (i = 0 ; i < words ; i++) { + tmp = src[words - 1 - i]; + /* Words are read in little endian */ + *dst++ = (uint8_t)((tmp >> 24) & 0xFF); + *dst++ = (uint8_t)((tmp >> 16) & 0xFF); + *dst++ = (uint8_t)((tmp >> 8) & 0xFF); + *dst++ = (uint8_t)(tmp & 0xFF); + } + + /* Swap bytes 16-31 (last four registers) */ + src = (uint32_t *)(TZ_PUB_KEY_HASH_BASE + SHA256_BYTES / 2); + for (i = 0 ; i < words ; i++) { + tmp = src[words - 1 - i]; + *dst++ = (uint8_t)((tmp >> 24) & 0xFF); + *dst++ = (uint8_t)((tmp >> 16) & 0xFF); + *dst++ = (uint8_t)((tmp >> 8) & 0xFF); + *dst++ = (uint8_t)(tmp & 0xFF); + } +#endif /* (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) */ + + *key_ptr = (void *)rotpk_hash_der; + *key_len = (unsigned int)sizeof(rotpk_hash_der); + *flags = ROTPK_IS_HASH; + return 0; +} + +/* + * Return the non-volatile counter value stored in the platform. The cookie + * will contain the OID of the counter in the certificate. + * + * Return: 0 = success, Otherwise = error + */ +int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) +{ + const char *oid; + uint32_t *nv_ctr_addr; + + assert(cookie != NULL); + assert(nv_ctr != NULL); + + oid = (const char *)cookie; + if (strcmp(oid, TRUSTED_FW_NVCOUNTER_OID) == 0) { + nv_ctr_addr = (uint32_t *)TFW_NVCTR_BASE; + } else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) { + nv_ctr_addr = (uint32_t *)NTFW_CTR_BASE; + } else { + return 1; + } + + *nv_ctr = (unsigned int)(*nv_ctr_addr); + + return 0; +} + +/* + * Store a new non-volatile counter value. By default on ARM development + * platforms, the non-volatile counters are RO and cannot be modified. We expect + * the values in the certificates to always match the RO values so that this + * function is never called. + * + * Return: 0 = success, Otherwise = error + */ +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) +{ + return 1; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/board_common.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/board_common.mk new file mode 100644 index 0000000..a6d4ce7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/board_common.mk @@ -0,0 +1,68 @@ +# +# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +PLAT_INCLUDES += -Iinclude/plat/arm/board/common/ \ + -Iinclude/plat/arm/board/common/drivers + +PLAT_BL_COMMON_SOURCES += drivers/arm/pl011/${ARCH}/pl011_console.S \ + plat/arm/board/common/${ARCH}/board_arm_helpers.S + +BL1_SOURCES += plat/arm/board/common/drivers/norflash/norflash.c + +BL2_SOURCES += plat/arm/board/common/drivers/norflash/norflash.c + +#BL31_SOURCES += + +ifneq (${TRUSTED_BOARD_BOOT},0) + # ROTPK hash location + ifeq (${ARM_ROTPK_LOCATION}, regs) + ARM_ROTPK_LOCATION_ID = ARM_ROTPK_REGS_ID + else ifeq (${ARM_ROTPK_LOCATION}, devel_rsa) + ARM_ROTPK_LOCATION_ID = ARM_ROTPK_DEVEL_RSA_ID + else + $(error "Unsupported ARM_ROTPK_LOCATION value") + endif + $(eval $(call add_define,ARM_ROTPK_LOCATION_ID)) + + # Certificate NV-Counters. Use values corresponding to tied off values in + # ARM development platforms + TFW_NVCTR_VAL ?= 31 + NTFW_NVCTR_VAL ?= 223 + + BL1_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c + BL2_SOURCES += plat/arm/board/common/board_arm_trusted_boot.c +endif + +# This flag controls whether memory usage needs to be optimised +ARM_BOARD_OPTIMISE_MEM ?= 0 + +# Process flags +$(eval $(call assert_boolean,ARM_BOARD_OPTIMISE_MEM)) +$(eval $(call add_define,ARM_BOARD_OPTIMISE_MEM)) diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/board_css.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/board_css.mk new file mode 100644 index 0000000..67e794e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/board_css.mk @@ -0,0 +1,33 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +PLAT_BL_COMMON_SOURCES += plat/arm/board/common/board_css_common.c + +include plat/arm/board/common/board_common.mk diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/board_css_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/board_css_common.c new file mode 100644 index 0000000..69b744d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/board_css_common.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + +/* + * Table of memory regions for different BL stages to map using the MMU. + * This doesn't include Trusted SRAM as arm_setup_page_tables() already + * takes care of mapping it. + */ +#if IMAGE_BL1 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_FLASH0_RO, + V2M_MAP_IOFPGA, + CSS_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, +#if TRUSTED_BOARD_BOOT + ARM_MAP_NS_DRAM1, +#endif + {0} +}; +#endif +#if IMAGE_BL2 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_FLASH0_RO, + V2M_MAP_IOFPGA, + CSS_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, + ARM_MAP_NS_DRAM1, + ARM_MAP_TSP_SEC_MEM, + {0} +}; +#endif +#if IMAGE_BL2U +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + CSS_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, + {0} +}; +#endif +#if IMAGE_BL31 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_IOFPGA, + CSS_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, + {0} +}; +#endif +#if IMAGE_BL32 +const mmap_region_t plat_arm_mmap[] = { + V2M_MAP_IOFPGA, + CSS_MAP_DEVICE, + SOC_CSS_MAP_DEVICE, + {0} +}; +#endif + +ARM_CASSERT_MMAP + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/drivers/norflash/norflash.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/drivers/norflash/norflash.c new file mode 100644 index 0000000..8895461 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/drivers/norflash/norflash.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/* Helper macros to access two flash banks in parallel */ +#define NOR_2X16(d) ((d << 16) | (d & 0xffff)) + +/* + * DWS ready poll retries. The number of retries in this driver have been + * obtained empirically from Juno. FVP implements a zero wait state NOR flash + * model + */ +#define DWS_WORD_PROGRAM_RETRIES 1000 + +/* + * Poll Write State Machine. Return values: + * 0 = WSM ready + * -EBUSY = WSM busy after the number of retries + */ +static int nor_poll_dws(uintptr_t base_addr, unsigned int retries) +{ + uint32_t status; + int ret; + + for (;;) { + nor_send_cmd(base_addr, NOR_CMD_READ_STATUS_REG); + status = mmio_read_32(base_addr); + if ((status & NOR_DWS) && + (status & (NOR_DWS << 16))) { + ret = 0; + break; + } + if (retries-- == 0) { + ret = -EBUSY; + break; + } + } + + return ret; +} + +void nor_send_cmd(uintptr_t base_addr, unsigned long cmd) +{ + mmio_write_32(base_addr, NOR_2X16(cmd)); +} + +/* + * Return values: + * 0 = success + * -EBUSY = WSM not ready + * -EPERM = Device protected or Block locked + */ +int nor_word_program(uintptr_t base_addr, unsigned long data) +{ + uint32_t status; + int ret; + + /* Set the device in write word mode */ + nor_send_cmd(base_addr, NOR_CMD_WORD_PROGRAM); + mmio_write_32(base_addr, data); + + ret = nor_poll_dws(base_addr, DWS_WORD_PROGRAM_RETRIES); + if (ret != 0) { + goto word_program_end; + } + + /* Full status check */ + nor_send_cmd(base_addr, NOR_CMD_READ_STATUS_REG); + status = mmio_read_32(base_addr); + + if (status & (NOR_PS | NOR_BLS)) { + nor_send_cmd(base_addr, NOR_CMD_CLEAR_STATUS_REG); + ret = -EPERM; + } + +word_program_end: + nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY); + return ret; +} + +void nor_lock(uintptr_t base_addr) +{ + nor_send_cmd(base_addr, NOR_CMD_LOCK_UNLOCK); + mmio_write_32(base_addr, NOR_2X16(NOR_LOCK_BLOCK)); + nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY); +} + +void nor_unlock(uintptr_t base_addr) +{ + nor_send_cmd(base_addr, NOR_CMD_LOCK_UNLOCK); + mmio_write_32(base_addr, NOR_2X16(NOR_UNLOCK_BLOCK)); + nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY); +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/rotpk/arm_rotpk_rsa.der b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/rotpk/arm_rotpk_rsa.der new file mode 100644 index 0000000000000000000000000000000000000000..661f8998df780e571477691d8d53c2bbec19ae16 GIT binary patch literal 294 zcmV+>0ondAf&n5h4F(A+hDe6@4FLfG1potr0S^E$f&mHwf&l>l%Pe5kjbqdYd49(h zmc30RPOOIJw{hdeR14=69K9(T!9RMo0;;Pv#Mw4!Y~p3Zo3Xz=s8%M+{R9EJtUgpS z%6VS9vIXh}Sn_nb;q-^V844d}2X};np&al3C|T#jXniIiL+e&!^EoltD^aPuPtf+> zmE2!j!R?T5>?o0b7wveE^kApN$4^l0T@yMXD{#eOdk7(AI?aMsjCx0`iRh(BNHN(R zM&*Tun4smrrfR(hwp99JrTKdtiAy*L70s{d60nnC)o&W#< literal 0 HcmV?d00001 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem new file mode 100644 index 0000000..71410ec --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem @@ -0,0 +1,28 @@ +-----BEGIN PRIVATE KEY----- +MIIEvAIBADANBgkqhkiG9w0BAQEFAASCBKYwggSiAgEAAoIBAQDLLGDVjWPUB3l+ +xxaWvU0kTqyG5rdx48VUC+cUHL0pGsE/erYCqqs2xNk2aWziZcObsb89qFYmy/0E +AbqsPlQyynleu7IF6gZY8nS64fSHwBkKH2YHd4SDoRzv/yhZ58NofSYgQ+tWY/M5 +MdgrUam8T9D23pXcX1vB7ZBv7CiRfhfteJD0YKfEx09Q7V0TOiErcMVhewghZTrN +glaMekesieilSEgx2R1G5YWGmKDlwKZqvQfkkldhB499Wk3Krja5VgQQ8my+9jts +gD6+DqNNx9R+p0nU8tK8zzCo53SPZN+8XEdozEBM+IPMy0A1BGDKs6QXnwPKHVr6 +0a8hVxDTAgMBAAECggEAfwsc8ewbhDW4TwIGqfNtDUr0rtYN13VpqohW0ki2L8G/ +HQaKUViO/wxQFqoNn/OqQO0AfHmKhXAAokTCiXngBHJ/OjF7vB7+IRhazZEE6u2/ +uoivr/OYNQbFpXyTqsQ1eFzpPju6KKcPK7BzT4Mc89ek/vloFAi8w6LdMl8lbvOg +LBWqX+5A+UQoenPUTvYM4U22YNcEAWubkpsYAmViiWiac+a+uPRk39aKyfOedDNu ++ty9MtCwekivoUTfP/1+O+jFlDnPMJUOEkBmcBqxseYYAHu7blBpdHxYpAItC2pv +YwJJSvsE+HLBLPk177Jahg7sOUqcP0F/X+T65yuvIQKBgQDxdjXdJT5K8j7rG2fv +2bvF2H1GPaHaTYRk0EGI2Ql6Nn+ddfeCE6gaT7aPPgg87wAhNu93coFuYHw0p/sc +ZkXMJ+BmlstPV555cWXmwcxZLsni0fOXrt4YxwWkZwmh74m0NVM/cSFw56PU0oj1 +yDNeq3fgmsJocmuNTe1eG9qA7QKBgQDXaAGrNA5Xel5mqqMYTHHQWI6l2uzdNtt7 +eDn3K9+Eh3ywTqrwP845MAjKDU2Lq61I6t2H89dEifHq823VIcLCHd9BF04MrAH7 +qDPzrmPP2iB9g+YFmGBKe+K0HFE1t1KrTlo9VV6ZAC6RJNLAgwD4kvfIVYNkCGwe ++hoZBdhgvwKBgBrOsPQ4ak4PzwRzKnrqhXpVqrLdrNZ7vLMkm+IBlpfG7SwiKLR8 +UjF5oB8PGAML1cvaOYPdZplGhQOjkrF4eU9NLhC1tSS96Y46FMIlyfYsx6UzAgRZ +GbdOgUXbWqpr2bH0KaXlfXz3eqzqIuKGs41TJB//jo3iBibN/AhytzORAoGAeGov +5KDpE4XYl9Pz8HVremjG9Xh4yQENmOwQm1fvT4rd7UFM1ZkVk2qCv1DIdLe32vdQ +d9ucDzh+ADWsxGRnF1TTpPN+Mh9FzISu5h4qtdreJsxBHgecbIbsqHrb+wdMM29N +itPaWfV8Eq9fETcqp8qgsWD8XkNHDdoKFMrrtskCgYAoSt/Je1D3ZE/3HEjez7bq +fenS3J6KG2SEn2PNFn+R0R5vBo4DaV/cQysKh44GD2+sh0QDyh6nuWJufyhPzROP +DU6DCLbwNePj/yaGuzi36oLt6bBgfPWCiJY7jIdK8DmTLW25m7fRtCC5pxZlSzgl +KBf7R6cbaTvaFe05Y2FJXA== +-----END PRIVATE KEY----- diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/aarch32/fvp_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/aarch32/fvp_helpers.S new file mode 100644 index 0000000..4c750cb --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/aarch32/fvp_helpers.S @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "../drivers/pwrc/fvp_pwrc.h" +#include "../fvp_def.h" + + .globl plat_secondary_cold_boot_setup + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + + /* -------------------------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * For AArch32, cold-booting secondary CPUs is not yet + * implemented and they panic. + * -------------------------------------------------------------------- + */ +func plat_secondary_cold_boot_setup +cb_panic: + b cb_panic +endfunc plat_secondary_cold_boot_setup + + /* --------------------------------------------------------------------- + * unsigned long plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and warm + * boot. On FVP, this information can be queried from the power + * controller. The Power Control SYS Status Register (PSYSR) indicates + * the wake-up reason for the CPU. + * + * For a cold boot, return 0. + * For a warm boot, read the mailbox and return the address it contains. + * + * TODO: PSYSR is a common register and should be + * accessed using locks. Since it is not possible + * to use locks immediately after a cold reset + * we are relying on the fact that after a cold + * reset all cpus will read the same WK field + * --------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + /* --------------------------------------------------------------------- + * When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC + * WakeRequest signal" then it is a warm boot. + * --------------------------------------------------------------------- + */ + ldcopr r2, MPIDR + ldr r1, =PWRC_BASE + str r2, [r1, #PSYSR_OFF] + ldr r2, [r1, #PSYSR_OFF] + ubfx r2, r2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH + cmp r2, #WKUP_PPONR + beq warm_reset + cmp r2, #WKUP_GICREQ + beq warm_reset + + /* Cold reset */ + mov r0, #0 + bx lr + +warm_reset: + /* --------------------------------------------------------------------- + * A mailbox is maintained in the trusted SRAM. It is flushed out of the + * caches after every update using normal memory so it is safe to read + * it here with SO attributes. + * --------------------------------------------------------------------- + */ + ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE + ldr r0, [r0] + cmp r0, #0 + beq _panic + bx lr + + /* --------------------------------------------------------------------- + * The power controller indicates this is a warm reset but the mailbox + * is empty. This should never happen! + * --------------------------------------------------------------------- + */ +_panic: + b _panic +endfunc plat_get_my_entrypoint + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + ldcopr r0, MPIDR + ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + and r0, r1 + cmp r0, #FVP_PRIMARY_CPU + moveq r0, #1 + movne r0, #0 + bx lr +endfunc plat_is_my_cpu_primary diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/aarch64/fvp_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/aarch64/fvp_helpers.S new file mode 100644 index 0000000..6a7ad23 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/aarch64/fvp_helpers.S @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "../drivers/pwrc/fvp_pwrc.h" +#include "../fvp_def.h" + + .globl plat_secondary_cold_boot_setup + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + + .macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res + ldr \x_tmp, =V2M_SYSREGS_BASE + V2M_SYS_ID + ldr \w_tmp, [\x_tmp] + ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH + cmp \w_tmp, #BLD_GIC_VE_MMAP + csel \res, \param1, \param2, eq + .endm + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * TODO: Should we read the PSYS register to make sure + * that the request has gone through. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup +#ifndef EL3_PAYLOAD_BASE + /* --------------------------------------------- + * Power down this cpu. + * TODO: Do we need to worry about powering the + * cluster down as well here. That will need + * locks which we won't have unless an elf- + * loader zeroes out the zi section. + * --------------------------------------------- + */ + mrs x0, mpidr_el1 + ldr x1, =PWRC_BASE + str w0, [x1, #PPOFFR_OFF] + + /* --------------------------------------------- + * Disable GIC bypass as well + * --------------------------------------------- + */ + /* Check for GICv3 system register access */ + mrs x0, id_aa64pfr0_el1 + ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH + cmp x0, #1 + b.ne gicv2_bypass_disable + + /* Check for SRE enable */ + mrs x1, ICC_SRE_EL3 + tst x1, #ICC_SRE_SRE_BIT + b.eq gicv2_bypass_disable + + mrs x2, ICC_SRE_EL3 + orr x2, x2, #(ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT) + msr ICC_SRE_EL3, x2 + b secondary_cold_boot_wait + +gicv2_bypass_disable: + ldr x0, =VE_GICC_BASE + ldr x1, =BASE_GICC_BASE + fvp_choose_gicmmap x0, x1, x2, w2, x1 + mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1) + orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0) + str w0, [x1, #GICC_CTLR] + +secondary_cold_boot_wait: + /* --------------------------------------------- + * There is no sane reason to come out of this + * wfi so panic if we do. This cpu will be pow- + * ered on and reset by the cpu_on pm api + * --------------------------------------------- + */ + dsb sy + wfi + bl plat_panic_handler +#else + mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE + + /* Wait until the entrypoint gets populated */ +poll_mailbox: + ldr x1, [x0] + cbz x1, 1f + br x1 +1: + wfe + b poll_mailbox +#endif /* EL3_PAYLOAD_BASE */ +endfunc plat_secondary_cold_boot_setup + + /* --------------------------------------------------------------------- + * uintptr_t plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and warm + * boot. On FVP, this information can be queried from the power + * controller. The Power Control SYS Status Register (PSYSR) indicates + * the wake-up reason for the CPU. + * + * For a cold boot, return 0. + * For a warm boot, read the mailbox and return the address it contains. + * + * TODO: PSYSR is a common register and should be + * accessed using locks. Since it is not possible + * to use locks immediately after a cold reset + * we are relying on the fact that after a cold + * reset all cpus will read the same WK field + * --------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + /* --------------------------------------------------------------------- + * When bit PSYSR.WK indicates either "Wake by PPONR" or "Wake by GIC + * WakeRequest signal" then it is a warm boot. + * --------------------------------------------------------------------- + */ + mrs x2, mpidr_el1 + ldr x1, =PWRC_BASE + str w2, [x1, #PSYSR_OFF] + ldr w2, [x1, #PSYSR_OFF] + ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_WIDTH + cmp w2, #WKUP_PPONR + beq warm_reset + cmp w2, #WKUP_GICREQ + beq warm_reset + + /* Cold reset */ + mov x0, #0 + ret + +warm_reset: + /* --------------------------------------------------------------------- + * A mailbox is maintained in the trusted SRAM. It is flushed out of the + * caches after every update using normal memory so it is safe to read + * it here with SO attributes. + * --------------------------------------------------------------------- + */ + mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE + ldr x0, [x0] + cbz x0, _panic_handler + ret + + /* --------------------------------------------------------------------- + * The power controller indicates this is a warm reset but the mailbox + * is empty. This should never happen! + * --------------------------------------------------------------------- + */ +_panic_handler: + bl plat_panic_handler +endfunc plat_get_my_entrypoint + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #FVP_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c new file mode 100644 index 0000000..c8df78c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "../../fvp_def.h" +#include "../../fvp_private.h" +#include "fvp_pwrc.h" + +/* + * TODO: Someday there will be a generic power controller api. At the moment + * each platform has its own pwrc so just exporting functions is fine. + */ +ARM_INSTANTIATE_LOCK + +unsigned int fvp_pwrc_get_cpu_wkr(u_register_t mpidr) +{ + return PSYSR_WK(fvp_pwrc_read_psysr(mpidr)); +} + +unsigned int fvp_pwrc_read_psysr(u_register_t mpidr) +{ + unsigned int rc; + arm_lock_get(); + mmio_write_32(PWRC_BASE + PSYSR_OFF, (unsigned int) mpidr); + rc = mmio_read_32(PWRC_BASE + PSYSR_OFF); + arm_lock_release(); + return rc; +} + +void fvp_pwrc_write_pponr(u_register_t mpidr) +{ + arm_lock_get(); + mmio_write_32(PWRC_BASE + PPONR_OFF, (unsigned int) mpidr); + arm_lock_release(); +} + +void fvp_pwrc_write_ppoffr(u_register_t mpidr) +{ + arm_lock_get(); + mmio_write_32(PWRC_BASE + PPOFFR_OFF, (unsigned int) mpidr); + arm_lock_release(); +} + +void fvp_pwrc_set_wen(u_register_t mpidr) +{ + arm_lock_get(); + mmio_write_32(PWRC_BASE + PWKUPR_OFF, + (unsigned int) (PWKUPR_WEN | mpidr)); + arm_lock_release(); +} + +void fvp_pwrc_clr_wen(u_register_t mpidr) +{ + arm_lock_get(); + mmio_write_32(PWRC_BASE + PWKUPR_OFF, + (unsigned int) mpidr); + arm_lock_release(); +} + +void fvp_pwrc_write_pcoffr(u_register_t mpidr) +{ + arm_lock_get(); + mmio_write_32(PWRC_BASE + PCOFFR_OFF, (unsigned int) mpidr); + arm_lock_release(); +} + +/* Nothing else to do here apart from initializing the lock */ +void plat_arm_pwrc_setup(void) +{ + arm_lock_init(); +} + + + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h new file mode 100644 index 0000000..1dbf128 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FVP_PWRC_H__ +#define __FVP_PWRC_H__ + +/* FVP Power controller register offset etc */ +#define PPOFFR_OFF 0x0 +#define PPONR_OFF 0x4 +#define PCOFFR_OFF 0x8 +#define PWKUPR_OFF 0xc +#define PSYSR_OFF 0x10 + +#define PWKUPR_WEN (1ull << 31) + +#define PSYSR_AFF_L2 (1 << 31) +#define PSYSR_AFF_L1 (1 << 30) +#define PSYSR_AFF_L0 (1 << 29) +#define PSYSR_WEN (1 << 28) +#define PSYSR_PC (1 << 27) +#define PSYSR_PP (1 << 26) + +#define PSYSR_WK_SHIFT 24 +#define PSYSR_WK_WIDTH 0x2 +#define PSYSR_WK_MASK ((1 << PSYSR_WK_WIDTH) - 1) +#define PSYSR_WK(x) (x >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK + +#define WKUP_COLD 0x0 +#define WKUP_RESET 0x1 +#define WKUP_PPONR 0x2 +#define WKUP_GICREQ 0x3 + +#define PSYSR_INVALID 0xffffffff + +#ifndef __ASSEMBLY__ + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void fvp_pwrc_write_pcoffr(u_register_t); +void fvp_pwrc_write_ppoffr(u_register_t); +void fvp_pwrc_write_pponr(u_register_t); +void fvp_pwrc_set_wen(u_register_t); +void fvp_pwrc_clr_wen(u_register_t); +unsigned int fvp_pwrc_read_psysr(u_register_t); +unsigned int fvp_pwrc_get_cpu_wkr(u_register_t); + +#endif /*__ASSEMBLY__*/ + +#endif /* __FVP_PWRC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_bl1_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_bl1_setup.c new file mode 100644 index 0000000..cc7feae --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_bl1_setup.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "fvp_private.h" + + +/******************************************************************************* + * Perform any BL1 specific platform actions. + ******************************************************************************/ +void bl1_early_platform_setup(void) +{ + arm_bl1_early_platform_setup(); + + /* Initialize the platform config for future decision making */ + fvp_config_setup(); + + /* + * Initialize Interconnect for this cluster during cold boot. + * No need for locks as no other CPU is active. + */ + fvp_interconnect_init(); + /* + * Enable coherency in Interconnect for the primary CPU's cluster. + */ + fvp_interconnect_enable(); +} + +/******************************************************************************* + * The following function checks if Firmware update is needed, + * by checking if TOC in FIP image is valid or not. + ******************************************************************************/ +unsigned int bl1_plat_get_next_image_id(void) +{ + if (!arm_io_is_toc_valid()) + return NS_BL1U_IMAGE_ID; + + return BL2_IMAGE_ID; +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_bl2_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_bl2_setup.c new file mode 100644 index 0000000..ee49c30 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_bl2_setup.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "fvp_def.h" +#include "fvp_private.h" + + +void bl2_early_platform_setup(meminfo_t *mem_layout) +{ + arm_bl2_early_platform_setup(mem_layout); + + /* Initialize the platform config for future decision making */ + fvp_config_setup(); +} + +void bl2_platform_setup(void) +{ + arm_bl2_platform_setup(); + +#if FVP_USE_SP804_TIMER + /* Enable the clock override for SP804 timer 0, which means that no + * clock dividers are applied and the raw (35 MHz) clock will be used */ + mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); + + /* Initialize delay timer driver using SP804 dual timer 0 */ + sp804_timer_init(V2M_SP804_TIMER0_BASE, + SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); +#else + generic_delay_timer_init(); +#endif /* FVP_USE_SP804_TIMER */ +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_bl2u_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_bl2u_setup.c new file mode 100644 index 0000000..b26f0e0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_bl2u_setup.c @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "fvp_def.h" +#include "fvp_private.h" + +void bl2u_early_platform_setup(meminfo_t *mem_layout, void *plat_info) +{ + arm_bl2u_early_platform_setup(mem_layout, plat_info); + + /* Initialize the platform config for future decision making */ + fvp_config_setup(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_bl31_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_bl31_setup.c new file mode 100644 index 0000000..f16d6f0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_bl31_setup.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "fvp_private.h" + +#if LOAD_IMAGE_V2 +void bl31_early_platform_setup(void *from_bl2, + void *plat_params_from_bl2) +#else +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +#endif +{ + arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2); + + /* Initialize the platform config for future decision making */ + fvp_config_setup(); + + /* + * Initialize the correct interconnect for this cluster during cold + * boot. No need for locks as no other CPU is active. + */ + fvp_interconnect_init(); + + /* + * Enable coherency in interconnect for the primary CPU's cluster. + * Earlier bootloader stages might already do this (e.g. Trusted + * Firmware's BL1 does it) but we can't assume so. There is no harm in + * executing this code twice anyway. + * FVP PSCI code will enable coherency for other clusters. + */ + fvp_interconnect_enable(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_common.c new file mode 100644 index 0000000..3df472c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_common.c @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../fvp_def.h" + +/* Defines for GIC Driver build time selection */ +#define FVP_GICV2 1 +#define FVP_GICV3 2 +#define FVP_GICV3_LEGACY 3 + +/******************************************************************************* + * arm_config holds the characteristics of the differences between the three FVP + * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot + * at each boot stage by the primary before enabling the MMU (to allow + * interconnect configuration) & used thereafter. Each BL will have its own copy + * to allow independent operation. + ******************************************************************************/ +arm_config_t arm_config; + +#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ + DEVICE0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ + DEVICE1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ + DEVICE2_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + + +/* + * Table of memory regions for various BL stages to map using the MMU. + * This doesn't include Trusted SRAM as arm_setup_page_tables() already + * takes care of mapping it. + * + * The flash needs to be mapped as writable in order to erase the FIP's Table of + * Contents in case of unrecoverable error (see plat_error_handler()). + */ +#if IMAGE_BL1 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_FLASH0_RW, + V2M_MAP_IOFPGA, + MAP_DEVICE0, + MAP_DEVICE1, + MAP_DEVICE2, +#if TRUSTED_BOARD_BOOT + ARM_MAP_NS_DRAM1, +#endif + {0} +}; +#endif +#if IMAGE_BL2 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_FLASH0_RW, + V2M_MAP_IOFPGA, + MAP_DEVICE0, + MAP_DEVICE1, + MAP_DEVICE2, + ARM_MAP_NS_DRAM1, + ARM_MAP_TSP_SEC_MEM, +#if ARM_BL31_IN_DRAM + ARM_MAP_BL31_SEC_DRAM, +#endif + {0} +}; +#endif +#if IMAGE_BL2U +const mmap_region_t plat_arm_mmap[] = { + MAP_DEVICE0, + V2M_MAP_IOFPGA, + {0} +}; +#endif +#if IMAGE_BL31 +const mmap_region_t plat_arm_mmap[] = { + ARM_MAP_SHARED_RAM, + V2M_MAP_IOFPGA, + MAP_DEVICE0, + MAP_DEVICE1, + {0} +}; +#endif +#if IMAGE_BL32 +const mmap_region_t plat_arm_mmap[] = { +#ifdef AARCH32 + ARM_MAP_SHARED_RAM, +#endif + V2M_MAP_IOFPGA, + MAP_DEVICE0, + MAP_DEVICE1, + {0} +}; +#endif + +ARM_CASSERT_MMAP + + +/******************************************************************************* + * A single boot loader stack is expected to work on both the Foundation FVP + * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The + * SYS_ID register provides a mechanism for detecting the differences between + * these platforms. This information is stored in a per-BL array to allow the + * code to take the correct path.Per BL platform configuration. + ******************************************************************************/ +void fvp_config_setup(void) +{ + unsigned int rev, hbi, bld, arch, sys_id; + + sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); + rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; + hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; + bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; + arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; + + if (arch != ARCH_MODEL) { + ERROR("This firmware is for FVP models\n"); + panic(); + } + + /* + * The build field in the SYS_ID tells which variant of the GIC + * memory is implemented by the model. + */ + switch (bld) { + case BLD_GIC_VE_MMAP: + ERROR("Legacy Versatile Express memory map for GIC peripheral" + " is not supported\n"); + panic(); + break; + case BLD_GIC_A53A57_MMAP: + break; + default: + ERROR("Unsupported board build %x\n", bld); + panic(); + } + + /* + * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 + * for the Foundation FVP. + */ + switch (hbi) { + case HBI_FOUNDATION_FVP: + arm_config.flags = 0; + + /* + * Check for supported revisions of Foundation FVP + * Allow future revisions to run but emit warning diagnostic + */ + switch (rev) { + case REV_FOUNDATION_FVP_V2_0: + case REV_FOUNDATION_FVP_V2_1: + case REV_FOUNDATION_FVP_v9_1: + case REV_FOUNDATION_FVP_v9_6: + break; + default: + WARN("Unrecognized Foundation FVP revision %x\n", rev); + break; + } + break; + case HBI_BASE_FVP: + arm_config.flags |= ARM_CONFIG_BASE_MMAP | + ARM_CONFIG_HAS_INTERCONNECT | ARM_CONFIG_HAS_TZC; + + /* + * Check for supported revisions + * Allow future revisions to run but emit warning diagnostic + */ + switch (rev) { + case REV_BASE_FVP_V0: + break; + default: + WARN("Unrecognized Base FVP revision %x\n", rev); + break; + } + break; + default: + ERROR("Unsupported board HBI number 0x%x\n", hbi); + panic(); + } +} + + +void fvp_interconnect_init(void) +{ + if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) { +#if FVP_INTERCONNECT_DRIVER == FVP_CCN + if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { + ERROR("Unrecognized CCN variant detected. Only CCN-502" + " is supported"); + panic(); + } +#endif + plat_arm_interconnect_init(); + } +} + +void fvp_interconnect_enable(void) +{ + if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) + plat_arm_interconnect_enter_coherency(); +} + +void fvp_interconnect_disable(void) +{ + if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) + plat_arm_interconnect_exit_coherency(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_def.h new file mode 100644 index 0000000..edeb5b7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_def.h @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FVP_DEF_H__ +#define __FVP_DEF_H__ + +#include + +#ifndef FVP_CLUSTER_COUNT +#define FVP_CLUSTER_COUNT 2 +#endif +#define FVP_MAX_CPUS_PER_CLUSTER 4 + +#define FVP_PRIMARY_CPU 0x0 + +/* Defines for the Interconnect build selection */ +#define FVP_CCI 1 +#define FVP_CCN 2 + +/******************************************************************************* + * FVP memory map related constants + ******************************************************************************/ + +#define FLASH1_BASE 0x0c000000 +#define FLASH1_SIZE 0x04000000 + +#define PSRAM_BASE 0x14000000 +#define PSRAM_SIZE 0x04000000 + +#define VRAM_BASE 0x18000000 +#define VRAM_SIZE 0x02000000 + +/* Aggregate of all devices in the first GB */ +#define DEVICE0_BASE 0x20000000 +#define DEVICE0_SIZE 0x0c200000 + +/* + * In case of FVP models with CCN, the CCN register space overlaps into + * the NSRAM area. + */ +#if FVP_INTERCONNECT_DRIVER == FVP_CCN +#define DEVICE1_BASE 0x2e000000 +#define DEVICE1_SIZE 0x1A00000 +#else +#define DEVICE1_BASE 0x2f000000 +#define DEVICE1_SIZE 0x200000 +#define NSRAM_BASE 0x2e000000 +#define NSRAM_SIZE 0x10000 +#endif +/* Devices in the second GB */ +#define DEVICE2_BASE 0x7fe00000 +#define DEVICE2_SIZE 0x00200000 + +#define PCIE_EXP_BASE 0x40000000 +#define TZRNG_BASE 0x7fe60000 + +/* Non-volatile counters */ +#define TRUSTED_NVCTR_BASE 0x7fe70000 +#define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + 0x0000) +#define TFW_NVCTR_SIZE 4 +#define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + 0x0004) +#define NTFW_CTR_SIZE 4 + +/* Keys */ +#define SOC_KEYS_BASE 0x7fe80000 +#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) +#define TZ_PUB_KEY_HASH_SIZE 32 +#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) +#define HU_KEY_SIZE 16 +#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) +#define END_KEY_SIZE 32 + +/* Constants to distinguish FVP type */ +#define HBI_BASE_FVP 0x020 +#define REV_BASE_FVP_V0 0x0 + +#define HBI_FOUNDATION_FVP 0x010 +#define REV_FOUNDATION_FVP_V2_0 0x0 +#define REV_FOUNDATION_FVP_V2_1 0x1 +#define REV_FOUNDATION_FVP_v9_1 0x2 +#define REV_FOUNDATION_FVP_v9_6 0x3 + +#define BLD_GIC_VE_MMAP 0x0 +#define BLD_GIC_A53A57_MMAP 0x1 + +#define ARCH_MODEL 0x1 + +/* FVP Power controller base address*/ +#define PWRC_BASE 0x1c100000 + +/* FVP SP804 timer frequency is 35 MHz*/ +#define SP804_TIMER_CLKMULT 1 +#define SP804_TIMER_CLKDIV 35 + +/* SP810 controller. FVP specific flags */ +#define FVP_SP810_CTRL_TIM0_OV (1 << 16) +#define FVP_SP810_CTRL_TIM1_OV (1 << 18) +#define FVP_SP810_CTRL_TIM2_OV (1 << 20) +#define FVP_SP810_CTRL_TIM3_OV (1 << 22) + +/******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ +/* VE compatible GIC memory map */ +#define VE_GICD_BASE 0x2c001000 +#define VE_GICC_BASE 0x2c002000 +#define VE_GICH_BASE 0x2c004000 +#define VE_GICV_BASE 0x2c006000 + +/* Base FVP compatible GIC memory map */ +#define BASE_GICD_BASE 0x2f000000 +#define BASE_GICR_BASE 0x2f100000 +#define BASE_GICC_BASE 0x2c000000 +#define BASE_GICH_BASE 0x2c010000 +#define BASE_GICV_BASE 0x2c02f000 + +#define FVP_IRQ_TZ_WDOG 56 +#define FVP_IRQ_SEC_SYS_TIMER 57 + + +/******************************************************************************* + * TrustZone address space controller related constants + ******************************************************************************/ + +/* NSAIDs used by devices in TZC filter 0 on FVP */ +#define FVP_NSAID_DEFAULT 0 +#define FVP_NSAID_PCI 1 +#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ +#define FVP_NSAID_AP 9 /* Application Processors */ +#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ + +/* NSAIDs used by devices in TZC filter 2 on FVP */ +#define FVP_NSAID_HDLCD0 2 +#define FVP_NSAID_CLCD 7 + +#endif /* __FVP_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_err.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_err.c new file mode 100644 index 0000000..f8ea6a0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_err.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* + * FVP error handler + */ +void plat_error_handler(int err) +{ + int ret; + + switch (err) { + case -ENOENT: + case -EAUTH: + /* Image load or authentication error. Erase the ToC */ + INFO("Erasing FIP ToC from flash...\n"); + nor_unlock(PLAT_ARM_FIP_BASE); + ret = nor_word_program(PLAT_ARM_FIP_BASE, 0); + if (ret) { + ERROR("Cannot erase ToC\n"); + } else { + INFO("Done\n"); + } + break; + default: + /* Unexpected error */ + break; + } + + /* Loop until the watchdog resets the system */ + for (;;) + wfi(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_io_storage.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_io_storage.c new file mode 100644 index 0000000..bc3d7b1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_io_storage.c @@ -0,0 +1,163 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include /* For FOPEN_MODE_... */ + +/* Semihosting filenames */ +#define BL2_IMAGE_NAME "bl2.bin" +#define BL31_IMAGE_NAME "bl31.bin" +#define BL32_IMAGE_NAME "bl32.bin" +#define BL33_IMAGE_NAME "bl33.bin" + +#if TRUSTED_BOARD_BOOT +#define TRUSTED_BOOT_FW_CERT_NAME "tb_fw.crt" +#define TRUSTED_KEY_CERT_NAME "trusted_key.crt" +#define SOC_FW_KEY_CERT_NAME "soc_fw_key.crt" +#define TOS_FW_KEY_CERT_NAME "tos_fw_key.crt" +#define NT_FW_KEY_CERT_NAME "nt_fw_key.crt" +#define SOC_FW_CONTENT_CERT_NAME "soc_fw_content.crt" +#define TOS_FW_CONTENT_CERT_NAME "tos_fw_content.crt" +#define NT_FW_CONTENT_CERT_NAME "nt_fw_content.crt" +#endif /* TRUSTED_BOARD_BOOT */ + +/* IO devices */ +static const io_dev_connector_t *sh_dev_con; +static uintptr_t sh_dev_handle; + +static const io_file_spec_t sh_file_spec[] = { + [BL2_IMAGE_ID] = { + .path = BL2_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, + [BL31_IMAGE_ID] = { + .path = BL31_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, + [BL32_IMAGE_ID] = { + .path = BL32_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, + [BL33_IMAGE_ID] = { + .path = BL33_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, +#if TRUSTED_BOARD_BOOT + [TRUSTED_BOOT_FW_CERT_ID] = { + .path = TRUSTED_BOOT_FW_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [TRUSTED_KEY_CERT_ID] = { + .path = TRUSTED_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [SOC_FW_KEY_CERT_ID] = { + .path = SOC_FW_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [TRUSTED_OS_FW_KEY_CERT_ID] = { + .path = TOS_FW_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { + .path = NT_FW_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [SOC_FW_CONTENT_CERT_ID] = { + .path = SOC_FW_CONTENT_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { + .path = TOS_FW_CONTENT_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { + .path = NT_FW_CONTENT_CERT_NAME, + .mode = FOPEN_MODE_RB + }, +#endif /* TRUSTED_BOARD_BOOT */ +}; + + +static int open_semihosting(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + /* See if the file exists on semi-hosting.*/ + result = io_dev_init(sh_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(sh_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using Semi-hosting IO\n"); + io_close(local_image_handle); + } + } + return result; +} + +void plat_arm_io_setup(void) +{ + int io_result; + + arm_io_setup(); + + /* Register the additional IO devices on this platform */ + io_result = register_io_dev_sh(&sh_dev_con); + assert(io_result == 0); + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(sh_dev_con, (uintptr_t)NULL, &sh_dev_handle); + assert(io_result == 0); + + /* Ignore improbable errors in release builds */ + (void)io_result; +} + +/* + * FVP provides semihosting as an alternative to load images + */ +int plat_arm_get_alt_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result = open_semihosting((const uintptr_t)&sh_file_spec[image_id]); + if (result == 0) { + *dev_handle = sh_dev_handle; + *image_spec = (uintptr_t)&sh_file_spec[image_id]; + } + + return result; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_pm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_pm.c new file mode 100644 index 0000000..66c0c3d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_pm.c @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "drivers/pwrc/fvp_pwrc.h" +#include "fvp_def.h" +#include "fvp_private.h" + + +#if ARM_RECOM_STATE_ID_ENC +/* + * The table storing the valid idle power states. Ensure that the + * array entries are populated in ascending order of state-id to + * enable us to use binary search during power state validation. + * The table must be terminated by a NULL entry. + */ +const unsigned int arm_pm_idle_states[] = { + /* State-id - 0x01 */ + arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, + ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), + /* State-id - 0x02 */ + arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, + ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), + /* State-id - 0x22 */ + arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, + ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), + 0, +}; +#endif + +/******************************************************************************* + * Function which implements the common FVP specific operations to power down a + * cpu in response to a CPU_OFF or CPU_SUSPEND request. + ******************************************************************************/ +static void fvp_cpu_pwrdwn_common(void) +{ + /* Prevent interrupts from spuriously waking up this cpu */ + plat_arm_gic_cpuif_disable(); + + /* Program the power controller to power off this cpu. */ + fvp_pwrc_write_ppoffr(read_mpidr_el1()); +} + +/******************************************************************************* + * Function which implements the common FVP specific operations to power down a + * cluster in response to a CPU_OFF or CPU_SUSPEND request. + ******************************************************************************/ +static void fvp_cluster_pwrdwn_common(void) +{ + uint64_t mpidr = read_mpidr_el1(); + + /* Disable coherency if this cluster is to be turned off */ + fvp_interconnect_disable(); + + /* Program the power controller to turn the cluster off */ + fvp_pwrc_write_pcoffr(mpidr); +} + +static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state) +{ + unsigned long mpidr; + + assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_OFF); + + /* Get the mpidr for this cpu */ + mpidr = read_mpidr_el1(); + + /* Perform the common cluster specific operations */ + if (target_state->pwr_domain_state[ARM_PWR_LVL1] == + ARM_LOCAL_STATE_OFF) { + /* + * This CPU might have woken up whilst the cluster was + * attempting to power down. In this case the FVP power + * controller will have a pending cluster power off request + * which needs to be cleared by writing to the PPONR register. + * This prevents the power controller from interpreting a + * subsequent entry of this cpu into a simple wfi as a power + * down request. + */ + fvp_pwrc_write_pponr(mpidr); + + /* Enable coherency if this cluster was off */ + fvp_interconnect_enable(); + } + + /* + * Clear PWKUPR.WEN bit to ensure interrupts do not interfere + * with a cpu power down unless the bit is set again + */ + fvp_pwrc_clr_wen(mpidr); +} + + +/******************************************************************************* + * FVP handler called when a CPU is about to enter standby. + ******************************************************************************/ +void fvp_cpu_standby(plat_local_state_t cpu_state) +{ + + assert(cpu_state == ARM_LOCAL_STATE_RET); + + /* + * Enter standby state + * dsb is good practice before using wfi to enter low power states + */ + dsb(); + wfi(); +} + +/******************************************************************************* + * FVP handler called when a power domain is about to be turned on. The + * mpidr determines the CPU to be turned on. + ******************************************************************************/ +int fvp_pwr_domain_on(u_register_t mpidr) +{ + int rc = PSCI_E_SUCCESS; + unsigned int psysr; + + /* + * Ensure that we do not cancel an inflight power off request for the + * target cpu. That would leave it in a zombie wfi. Wait for it to power + * off and then program the power controller to turn that CPU on. + */ + do { + psysr = fvp_pwrc_read_psysr(mpidr); + } while (psysr & PSYSR_AFF_L0); + + fvp_pwrc_write_pponr(mpidr); + return rc; +} + +/******************************************************************************* + * FVP handler called when a power domain is about to be turned off. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void fvp_pwr_domain_off(const psci_power_state_t *target_state) +{ + assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_OFF); + + /* + * If execution reaches this stage then this power domain will be + * suspended. Perform at least the cpu specific actions followed + * by the cluster specific operations if applicable. + */ + fvp_cpu_pwrdwn_common(); + + if (target_state->pwr_domain_state[ARM_PWR_LVL1] == + ARM_LOCAL_STATE_OFF) + fvp_cluster_pwrdwn_common(); + +} + +/******************************************************************************* + * FVP handler called when a power domain is about to be suspended. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + unsigned long mpidr; + + /* + * FVP has retention only at cpu level. Just return + * as nothing is to be done for retention. + */ + if (target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_RET) + return; + + assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_OFF); + + /* Get the mpidr for this cpu */ + mpidr = read_mpidr_el1(); + + /* Program the power controller to enable wakeup interrupts. */ + fvp_pwrc_set_wen(mpidr); + + /* Perform the common cpu specific operations */ + fvp_cpu_pwrdwn_common(); + + /* Perform the common cluster specific operations */ + if (target_state->pwr_domain_state[ARM_PWR_LVL1] == + ARM_LOCAL_STATE_OFF) + fvp_cluster_pwrdwn_common(); +} + +/******************************************************************************* + * FVP handler called when a power domain has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. + ******************************************************************************/ +void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + fvp_power_domain_on_finish_common(target_state); + + /* Enable the gic cpu interface */ + plat_arm_gic_pcpu_init(); + + /* Program the gic per-cpu distributor or re-distributor interface */ + plat_arm_gic_cpuif_enable(); +} + +/******************************************************************************* + * FVP handler called when a power domain has just been powered on after + * having been suspended earlier. The target_state encodes the low power state + * that each level has woken up from. + * TODO: At the moment we reuse the on finisher and reinitialize the secure + * context. Need to implement a separate suspend finisher. + ******************************************************************************/ +void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ + /* + * Nothing to be done on waking up from retention from CPU level. + */ + if (target_state->pwr_domain_state[ARM_PWR_LVL0] == + ARM_LOCAL_STATE_RET) + return; + + fvp_power_domain_on_finish_common(target_state); + + /* Enable the gic cpu interface */ + plat_arm_gic_cpuif_enable(); +} + +/******************************************************************************* + * FVP handlers to shutdown/reboot the system + ******************************************************************************/ +static void __dead2 fvp_system_off(void) +{ + /* Write the System Configuration Control Register */ + mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, + V2M_CFGCTRL_START | + V2M_CFGCTRL_RW | + V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); + wfi(); + ERROR("FVP System Off: operation not handled.\n"); + panic(); +} + +static void __dead2 fvp_system_reset(void) +{ + /* Write the System Configuration Control Register */ + mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, + V2M_CFGCTRL_START | + V2M_CFGCTRL_RW | + V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); + wfi(); + ERROR("FVP System Reset: operation not handled.\n"); + panic(); +} + +static int fvp_node_hw_state(u_register_t target_cpu, + unsigned int power_level) +{ + unsigned int psysr; + int ret; + + /* + * The format of 'power_level' is implementation-defined, but 0 must + * mean a CPU. We also allow 1 to denote the cluster + */ + if (power_level != ARM_PWR_LVL0 && power_level != ARM_PWR_LVL1) + return PSCI_E_INVALID_PARAMS; + + /* + * Read the status of the given MPDIR from FVP power controller. The + * power controller only gives us on/off status, so map that to expected + * return values of the PSCI call + */ + psysr = fvp_pwrc_read_psysr(target_cpu); + if (psysr == PSYSR_INVALID) + return PSCI_E_INVALID_PARAMS; + + switch (power_level) { + case ARM_PWR_LVL0: + ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF; + break; + case ARM_PWR_LVL1: + ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF; + break; + default: + assert(0); + } + + return ret; +} + +/******************************************************************************* + * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard + * platform layer will take care of registering the handlers with PSCI. + ******************************************************************************/ +const plat_psci_ops_t plat_arm_psci_pm_ops = { + .cpu_standby = fvp_cpu_standby, + .pwr_domain_on = fvp_pwr_domain_on, + .pwr_domain_off = fvp_pwr_domain_off, + .pwr_domain_suspend = fvp_pwr_domain_suspend, + .pwr_domain_on_finish = fvp_pwr_domain_on_finish, + .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, + .system_off = fvp_system_off, + .system_reset = fvp_system_reset, + .validate_power_state = arm_validate_power_state, + .validate_ns_entrypoint = arm_validate_ns_entrypoint, + .get_node_hw_state = fvp_node_hw_state +}; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_private.h new file mode 100644 index 0000000..bb115e1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_private.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FVP_PRIVATE_H__ +#define __FVP_PRIVATE_H__ + +#include + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ + +void fvp_config_setup(void); + +void fvp_interconnect_init(void); +void fvp_interconnect_enable(void); +void fvp_interconnect_disable(void); + + +#endif /* __FVP_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_security.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_security.c new file mode 100644 index 0000000..b1de977 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_security.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/* + * We assume that all security programming is done by the primary core. + */ +void plat_arm_security_setup(void) +{ + /* + * The Base FVP has a TrustZone address space controller, the Foundation + * FVP does not. Trying to program the device on the foundation FVP will + * cause an abort. + * + * If the platform had additional peripheral specific security + * configurations, those would be configured here. + */ + + if (get_arm_config()->flags & ARM_CONFIG_HAS_TZC) + arm_tzc400_setup(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_topology.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_topology.c new file mode 100644 index 0000000..741aad6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_topology.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "drivers/pwrc/fvp_pwrc.h" + +/* The FVP power domain tree descriptor */ +unsigned char fvp_power_domain_tree_desc[FVP_CLUSTER_COUNT + 1]; + + +CASSERT(FVP_CLUSTER_COUNT && FVP_CLUSTER_COUNT <= 256, assert_invalid_fvp_cluster_count); + +/******************************************************************************* + * This function dynamically constructs the topology according to + * FVP_CLUSTER_COUNT and returns it. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + int i; + + /* + * The FVP power domain tree does not have a single system level power domain + * i.e. a single root node. The first entry in the power domain descriptor + * specifies the number of power domains at the highest power level. For the FVP + * this is the number of cluster power domains. + */ + fvp_power_domain_tree_desc[0] = FVP_CLUSTER_COUNT; + + for (i = 0; i < FVP_CLUSTER_COUNT; i++) + fvp_power_domain_tree_desc[i + 1] = FVP_MAX_CPUS_PER_CLUSTER; + + return fvp_power_domain_tree_desc; +} + +/******************************************************************************* + * This function returns the core count within the cluster corresponding to + * `mpidr`. + ******************************************************************************/ +unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) +{ + return FVP_MAX_CPUS_PER_CLUSTER; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + if (arm_check_mpidr(mpidr) == -1) + return -1; + + if (fvp_pwrc_read_psysr(mpidr) == PSYSR_INVALID) + return -1; + + return plat_arm_calc_core_pos(mpidr); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_trusted_boot.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_trusted_boot.c new file mode 100644 index 0000000..7db5051 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/fvp_trusted_boot.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "fvp_def.h" + +/* + * Store a new non-volatile counter value. On some FVP versions, the + * non-volatile counters are RO. On these versions we expect the values in the + * certificates to always match the RO values so that this function is never + * called. + * + * Return: 0 = success, Otherwise = error + */ +int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) +{ + const char *oid; + uint32_t *nv_ctr_addr; + + assert(cookie != NULL); + + oid = (const char *)cookie; + if (strcmp(oid, TRUSTED_FW_NVCOUNTER_OID) == 0) { + nv_ctr_addr = (uint32_t *)TFW_NVCTR_BASE; + } else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) { + nv_ctr_addr = (uint32_t *)NTFW_CTR_BASE; + } else { + return 1; + } + + *(unsigned int *)nv_ctr_addr = nv_ctr; + + /* Verify that the current value is the one we just wrote. */ + if (nv_ctr != (unsigned int)(*nv_ctr_addr)) + return 1; + + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/include/plat_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/include/plat_macros.S new file mode 100644 index 0000000..657a39b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/include/plat_macros.S @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __PLAT_MACROS_S__ +#define __PLAT_MACROS_S__ + +#include +#include +#include +#include "../fvp_def.h" + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + /* + * Detect if we're using the base memory map or + * the legacy VE memory map + */ + mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID) + ldr w16, [x0] + /* Extract BLD (12th - 15th bits) from the SYS_ID */ + ubfx x16, x16, #V2M_SYS_ID_BLD_SHIFT, #4 + /* Check if VE mmap */ + cmp w16, #BLD_GIC_VE_MMAP + b.eq use_ve_mmap + /* Assume Base Cortex mmap */ + mov_imm x17, BASE_GICC_BASE + mov_imm x16, BASE_GICD_BASE + b print_gic_regs +use_ve_mmap: + mov_imm x17, VE_GICC_BASE + mov_imm x16, VE_GICD_BASE +print_gic_regs: + arm_print_gic_regs +#if FVP_INTERCONNECT_DRIVER == FVP_CCI + print_cci_regs +#endif + .endm + +#endif /* __PLAT_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/include/platform_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/include/platform_def.h new file mode 100644 index 0000000..d0898ad --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/include/platform_def.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include +#include +#include +#include +#include +#include "../fvp_def.h" + +/* Required platform porting definitions */ +#define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) +#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 +#define PLATFORM_CORE_COUNT (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER) + +/* + * Other platform porting definitions are provided by included headers + */ + +/* + * Required ARM standard platform porting definitions + */ +#define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT + +#define PLAT_ARM_TRUSTED_ROM_BASE 0x00000000 +#define PLAT_ARM_TRUSTED_ROM_SIZE 0x04000000 /* 64 MB */ + +#define PLAT_ARM_TRUSTED_DRAM_BASE 0x06000000 +#define PLAT_ARM_TRUSTED_DRAM_SIZE 0x02000000 /* 32 MB */ + +/* No SCP in FVP */ +#define PLAT_ARM_SCP_TZC_DRAM1_SIZE MAKE_ULL(0x0) + +#define PLAT_ARM_DRAM2_SIZE MAKE_ULL(0x780000000) + +/* + * Load address of BL33 for this platform port + */ +#define PLAT_ARM_NS_IMAGE_OFFSET (ARM_DRAM1_BASE + 0x8000000) + + +/* + * PL011 related constants + */ +#define PLAT_ARM_BOOT_UART_BASE V2M_IOFPGA_UART0_BASE +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ + +#define PLAT_ARM_BL31_RUN_UART_BASE V2M_IOFPGA_UART1_BASE +#define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ + +#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ + +#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART2_BASE +#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART2_CLK_IN_HZ + +/* CCI related constants */ +#define PLAT_ARM_CCI_BASE 0x2c090000 +#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 +#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 + +/* CCN related constants. Only CCN 502 is currently supported */ +#define PLAT_ARM_CCN_BASE 0x2e000000 +#define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11 + +/* System timer related constants */ +#define PLAT_ARM_NSTIMER_FRAME_ID 1 + +/* Mailbox base address */ +#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE + + +/* TrustZone controller related constants + * + * Currently only filters 0 and 2 are connected on Base FVP. + * Filter 0 : CPU clusters (no access to DRAM by default) + * Filter 1 : not connected + * Filter 2 : LCDs (access to VRAM allowed by default) + * Filter 3 : not connected + * Programming unconnected filters will have no effect at the + * moment. These filter could, however, be connected in future. + * So care should be taken not to configure the unused filters. + * + * Allow only non-secure access to all DRAM to supported devices. + * Give access to the CPUs and Virtio. Some devices + * would normally use the default ID so allow that too. + */ +#define PLAT_ARM_TZC_BASE 0x2a4a0000 +#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) + +#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ + TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) | \ + TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) | \ + TZC_REGION_ACCESS_RDWR(FVP_NSAID_AP) | \ + TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) | \ + TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD)) + +/* + * GIC related constants to cater for both GICv2 and GICv3 instances of an + * FVP. They could be overriden at runtime in case the FVP implements the legacy + * VE memory map. + */ +#define PLAT_ARM_GICD_BASE BASE_GICD_BASE +#define PLAT_ARM_GICR_BASE BASE_GICR_BASE +#define PLAT_ARM_GICC_BASE BASE_GICC_BASE + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ + FVP_IRQ_TZ_WDOG, \ + FVP_IRQ_SEC_SYS_TIMER + +#define PLAT_ARM_G0_IRQS ARM_G0_IRQS + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/include/platform_oid.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/include/platform_oid.h new file mode 100644 index 0000000..1e44cf7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/include/platform_oid.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "../../../../../include/plat/arm/board/common/board_arm_oid.h" + +/* + * Required platform OIDs + * (Provided by included header) + */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/platform.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/platform.mk new file mode 100644 index 0000000..9b827a6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/platform.mk @@ -0,0 +1,161 @@ +# +# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# Use the GICv3 driver on the FVP by default +FVP_USE_GIC_DRIVER := FVP_GICV3 +# Use the SP804 timer instead of the generic one +FVP_USE_SP804_TIMER := 0 + +$(eval $(call assert_boolean,FVP_USE_SP804_TIMER)) +$(eval $(call add_define,FVP_USE_SP804_TIMER)) + +# The FVP platform depends on this macro to build with correct GIC driver. +$(eval $(call add_define,FVP_USE_GIC_DRIVER)) + +# Define default FVP_CLUSTER_COUNT to 2 and pass it into the build system. +FVP_CLUSTER_COUNT := 2 +$(eval $(call add_define,FVP_CLUSTER_COUNT)) + +# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, +# choose the CCI driver , else the CCN driver +ifeq ($(FVP_CLUSTER_COUNT), 0) +$(error "Incorrect cluster count specified for FVP port") +else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) +FVP_INTERCONNECT_DRIVER := FVP_CCI +else +FVP_INTERCONNECT_DRIVER := FVP_CCN +endif + +$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) + +# Choose the GIC sources depending upon the how the FVP will be invoked +ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) +FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v3/gicv3_main.c \ + drivers/arm/gic/v3/gicv3_helpers.c \ + plat/common/plat_gicv3.c \ + plat/arm/common/arm_gicv3.c +else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) +FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c \ + plat/arm/common/arm_gicv2.c +else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3_LEGACY) + ifeq (${ARCH}, aarch32) + $(error "GICV3 Legacy driver not supported for AArch32 build") + endif +FVP_GIC_SOURCES := drivers/arm/gic/arm_gic.c \ + drivers/arm/gic/gic_v2.c \ + drivers/arm/gic/gic_v3.c \ + plat/common/plat_gic.c \ + plat/arm/common/arm_gicv3_legacy.c +else +$(error "Incorrect GIC driver chosen on FVP port") +endif + +ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) +FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \ + plat/arm/common/arm_cci.c +else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) +FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ + plat/arm/common/arm_ccn.c +else +$(error "Incorrect CCN driver chosen on FVP port") +endif + +FVP_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ + plat/arm/board/fvp/fvp_security.c \ + plat/arm/common/arm_tzc400.c + + +PLAT_INCLUDES := -Iplat/arm/board/fvp/include + + +PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c + +FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S + +ifeq (${ARCH}, aarch64) +FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + lib/cpus/aarch64/cortex_a72.S \ + lib/cpus/aarch64/cortex_a73.S +else +FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S +endif + +BL1_SOURCES += drivers/io/io_semihosting.c \ + lib/semihosting/semihosting.c \ + lib/semihosting/${ARCH}/semihosting_call.S \ + plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ + plat/arm/board/fvp/fvp_bl1_setup.c \ + plat/arm/board/fvp/fvp_err.c \ + plat/arm/board/fvp/fvp_io_storage.c \ + plat/arm/board/fvp/fvp_trusted_boot.c \ + ${FVP_CPU_LIBS} \ + ${FVP_INTERCONNECT_SOURCES} + + +BL2_SOURCES += drivers/io/io_semihosting.c \ + drivers/delay_timer/delay_timer.c \ + lib/semihosting/semihosting.c \ + lib/semihosting/${ARCH}/semihosting_call.S \ + plat/arm/board/fvp/fvp_bl2_setup.c \ + plat/arm/board/fvp/fvp_err.c \ + plat/arm/board/fvp/fvp_io_storage.c \ + plat/arm/board/fvp/fvp_trusted_boot.c \ + ${FVP_SECURITY_SOURCES} + +ifeq (${FVP_USE_SP804_TIMER},1) +BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c +else +BL2_SOURCES += drivers/delay_timer/generic_delay_timer.c +endif + +BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ + ${FVP_SECURITY_SOURCES} + +BL31_SOURCES += plat/arm/board/fvp/fvp_bl31_setup.c \ + plat/arm/board/fvp/fvp_pm.c \ + plat/arm/board/fvp/fvp_topology.c \ + plat/arm/board/fvp/aarch64/fvp_helpers.S \ + plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c \ + ${FVP_CPU_LIBS} \ + ${FVP_GIC_SOURCES} \ + ${FVP_INTERCONNECT_SOURCES} \ + ${FVP_SECURITY_SOURCES} + +# Disable the PSCI platform compatibility layer +ENABLE_PLAT_COMPAT := 0 + +include plat/arm/board/common/board_common.mk +include plat/arm/common/arm_common.mk diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c new file mode 100644 index 0000000..735c4f0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "../fvp_private.h" + +void sp_min_early_platform_setup(void *from_bl2, + void *plat_params_from_bl2) +{ + arm_sp_min_early_platform_setup(from_bl2, plat_params_from_bl2); + + /* Initialize the platform config for future decision making */ + fvp_config_setup(); + + /* + * Initialize the correct interconnect for this cluster during cold + * boot. No need for locks as no other CPU is active. + */ + fvp_interconnect_init(); + + /* + * Enable coherency in interconnect for the primary CPU's cluster. + * Earlier bootloader stages might already do this (e.g. Trusted + * Firmware's BL1 does it) but we can't assume so. There is no harm in + * executing this code twice anyway. + * FVP PSCI code will enable coherency for other clusters. + */ + fvp_interconnect_enable(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/sp_min/sp_min-fvp.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/sp_min/sp_min-fvp.mk new file mode 100644 index 0000000..a788782 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/sp_min/sp_min-fvp.mk @@ -0,0 +1,42 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# SP_MIN source files specific to FVP platform +BL32_SOURCES += plat/arm/board/fvp/aarch32/fvp_helpers.S \ + plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c \ + plat/arm/board/fvp/fvp_pm.c \ + plat/arm/board/fvp/fvp_topology.c \ + plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c \ + ${FVP_CPU_LIBS} \ + ${FVP_GIC_SOURCES} \ + ${FVP_INTERCONNECT_SOURCES} \ + ${FVP_SECURITY_SOURCES} + +include plat/arm/common/sp_min/arm_sp_min.mk \ No newline at end of file diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/tsp/fvp_tsp_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/tsp/fvp_tsp_setup.c new file mode 100644 index 0000000..64246db --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/tsp/fvp_tsp_setup.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "../fvp_private.h" + +void tsp_early_platform_setup(void) +{ + arm_tsp_early_platform_setup(); + + /* Initialize the platform config for future decision making */ + fvp_config_setup(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/tsp/tsp-fvp.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/tsp/tsp-fvp.mk new file mode 100644 index 0000000..54a76fd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/fvp/tsp/tsp-fvp.mk @@ -0,0 +1,37 @@ +# +# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# TSP source files specific to FVP platform +BL32_SOURCES += plat/arm/board/fvp/fvp_topology.c \ + plat/arm/board/fvp/drivers/pwrc/fvp_pwrc.c \ + plat/arm/board/fvp/tsp/fvp_tsp_setup.c \ + ${FVP_GIC_SOURCES} + +include plat/arm/common/tsp/arm_tsp.mk diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/aarch64/juno_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/aarch64/juno_helpers.S new file mode 100644 index 0000000..9291fa4 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/aarch64/juno_helpers.S @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "../juno_def.h" + + + .globl plat_reset_handler + .globl plat_arm_calc_core_pos + +#define JUNO_REVISION(rev) REV_JUNO_R##rev +#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev +#define JUMP_TO_HANDLER_IF_JUNO_R(revision) \ + jump_to_handler JUNO_REVISION(revision), JUNO_HANDLER(revision) + + /* -------------------------------------------------------------------- + * Helper macro to jump to the given handler if the board revision + * matches. + * Expects the Juno board revision in x0. + * -------------------------------------------------------------------- + */ + .macro jump_to_handler _revision, _handler + cmp x0, #\_revision + b.eq \_handler + .endm + + /* -------------------------------------------------------------------- + * Helper macro that reads the part number of the current CPU and jumps + * to the given label if it matches the CPU MIDR provided. + * + * Clobbers x0. + * -------------------------------------------------------------------- + */ + .macro jump_if_cpu_midr _cpu_midr, _label + mrs x0, midr_el1 + ubfx x0, x0, MIDR_PN_SHIFT, #12 + cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) + b.eq \_label + .endm + + /* -------------------------------------------------------------------- + * Platform reset handler for Juno R0. + * + * Juno R0 has the following topology: + * - Quad core Cortex-A53 processor cluster; + * - Dual core Cortex-A57 processor cluster. + * + * This handler does the following: + * - Implement workaround for defect id 831273 by enabling an event + * stream every 65536 cycles. + * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 + * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 + * -------------------------------------------------------------------- + */ +func JUNO_HANDLER(0) + /* -------------------------------------------------------------------- + * Enable the event stream every 65536 cycles + * -------------------------------------------------------------------- + */ + mov x0, #(0xf << EVNTI_SHIFT) + orr x0, x0, #EVNTEN_BIT + msr CNTKCTL_EL1, x0 + + /* -------------------------------------------------------------------- + * Nothing else to do on Cortex-A53. + * -------------------------------------------------------------------- + */ + jump_if_cpu_midr CORTEX_A53_MIDR, 1f + + /* -------------------------------------------------------------------- + * Cortex-A57 specific settings + * -------------------------------------------------------------------- + */ + mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ + (L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) + msr L2CTLR_EL1, x0 +1: + isb + ret +endfunc JUNO_HANDLER(0) + + /* -------------------------------------------------------------------- + * Platform reset handler for Juno R1. + * + * Juno R1 has the following topology: + * - Quad core Cortex-A53 processor cluster; + * - Dual core Cortex-A57 processor cluster. + * + * This handler does the following: + * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 + * + * Note that: + * - The default value for the L2 Tag RAM latency for Cortex-A57 is + * suitable. + * - Defect #831273 doesn't affect Juno R1. + * -------------------------------------------------------------------- + */ +func JUNO_HANDLER(1) + /* -------------------------------------------------------------------- + * Nothing to do on Cortex-A53. + * -------------------------------------------------------------------- + */ + jump_if_cpu_midr CORTEX_A57_MIDR, A57 + ret + +A57: + /* -------------------------------------------------------------------- + * Cortex-A57 specific settings + * -------------------------------------------------------------------- + */ + mov x0, #(L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) + msr L2CTLR_EL1, x0 + isb + ret +endfunc JUNO_HANDLER(1) + + /* -------------------------------------------------------------------- + * Platform reset handler for Juno R2. + * + * Juno R2 has the following topology: + * - Quad core Cortex-A53 processor cluster; + * - Dual core Cortex-A72 processor cluster. + * + * This handler does the following: + * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72 + * - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72 + * + * Note that: + * - Defect #831273 doesn't affect Juno R2. + * -------------------------------------------------------------------- + */ +func JUNO_HANDLER(2) + /* -------------------------------------------------------------------- + * Nothing to do on Cortex-A53. + * -------------------------------------------------------------------- + */ + jump_if_cpu_midr CORTEX_A72_MIDR, A72 + ret + +A72: + /* -------------------------------------------------------------------- + * Cortex-A72 specific settings + * -------------------------------------------------------------------- + */ + mov x0, #((L2_DATA_RAM_LATENCY_3_CYCLES << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ + (L2_TAG_RAM_LATENCY_2_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)) + msr L2CTLR_EL1, x0 + isb + ret +endfunc JUNO_HANDLER(2) + + /* -------------------------------------------------------------------- + * void plat_reset_handler(void); + * + * Determine the Juno board revision and call the appropriate reset + * handler. + * -------------------------------------------------------------------- + */ +func plat_reset_handler + /* Read the V2M SYS_ID register */ + mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID) + ldr w1, [x0] + /* Extract board revision from the SYS_ID */ + ubfx x0, x1, #V2M_SYS_ID_REV_SHIFT, #4 + + JUMP_TO_HANDLER_IF_JUNO_R(0) + JUMP_TO_HANDLER_IF_JUNO_R(1) + JUMP_TO_HANDLER_IF_JUNO_R(2) + + /* Board revision is not supported */ + bl plat_panic_handler + +endfunc plat_reset_handler + + /* ----------------------------------------------------- + * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) + * Helper function to calculate the core position. + * ----------------------------------------------------- + */ +func plat_arm_calc_core_pos + b css_calc_core_pos_swap_cluster +endfunc plat_arm_calc_core_pos diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/include/plat_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/include/plat_macros.S new file mode 100644 index 0000000..bb42bca --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/include/plat_macros.S @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __PLAT_MACROS_S__ +#define __PLAT_MACROS_S__ + +#include +#include + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant platform registers + * whenever an unhandled exception is taken in + * BL31. + * --------------------------------------------- + */ + .macro plat_crash_print_regs + css_print_gic_regs + print_cci_regs + .endm + +#endif /* __PLAT_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/include/platform_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/include/platform_def.h new file mode 100644 index 0000000..691e2f7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/include/platform_def.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../juno_def.h" + +/* Required platform porting definitions */ +/* Juno supports system power domain */ +#define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 +#define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ + JUNO_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) +#define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ + JUNO_CLUSTER1_CORE_COUNT) + +/* + * Other platform porting definitions are provided by included headers + */ + +/* + * Required ARM standard platform porting definitions + */ +#define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT + +/* Use the bypass address */ +#define PLAT_ARM_TRUSTED_ROM_BASE V2M_FLASH0_BASE + BL1_ROM_BYPASS_OFFSET + +/* + * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB + * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of + * flash + */ +#if TRUSTED_BOARD_BOOT +#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00020000 +#else +#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00010000 +#endif /* TRUSTED_BOARD_BOOT */ + +/* + * If ARM_BOARD_OPTIMISE_MEM=0 then Juno uses the default, unoptimised values + * defined for ARM development platforms. + */ +#if ARM_BOARD_OPTIMISE_MEM +/* + * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the + * plat_arm_mmap array defined for each BL stage. + */ +#if IMAGE_BL1 +# define PLAT_ARM_MMAP_ENTRIES 7 +# define MAX_XLAT_TABLES 4 +#endif + +#if IMAGE_BL2 +# define PLAT_ARM_MMAP_ENTRIES 8 +# define MAX_XLAT_TABLES 3 +#endif + +#if IMAGE_BL2U +# define PLAT_ARM_MMAP_ENTRIES 4 +# define MAX_XLAT_TABLES 3 +#endif + +#if IMAGE_BL31 +# define PLAT_ARM_MMAP_ENTRIES 5 +# define MAX_XLAT_TABLES 2 +#endif + +#if IMAGE_BL32 +# define PLAT_ARM_MMAP_ENTRIES 4 +# define MAX_XLAT_TABLES 3 +#endif + +/* + * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size + * plus a little space for growth. + */ +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL1_RW_SIZE 0x9000 +#else +# define PLAT_ARM_MAX_BL1_RW_SIZE 0x6000 +#endif + +/* + * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a + * little space for growth. + */ +#if TRUSTED_BOARD_BOOT +# define PLAT_ARM_MAX_BL2_SIZE 0x1D000 +#else +# define PLAT_ARM_MAX_BL2_SIZE 0xC000 +#endif + +/* + * PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a + * little space for growth. + */ +#define PLAT_ARM_MAX_BL31_SIZE 0x1D000 + +#endif /* ARM_BOARD_OPTIMISE_MEM */ + +/* CCI related constants */ +#define PLAT_ARM_CCI_BASE 0x2c090000 +#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 +#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 + +/* System timer related constants */ +#define PLAT_ARM_NSTIMER_FRAME_ID 1 + +/* TZC related constants */ +#define PLAT_ARM_TZC_BASE 0x2a4a0000 +#define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ + TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) + +/* + * Required ARM CSS based platform porting definitions + */ + +/* GIC related constants (no GICR in GIC-400) */ +#define PLAT_ARM_GICD_BASE 0x2c010000 +#define PLAT_ARM_GICC_BASE 0x2c02f000 +#define PLAT_ARM_GICH_BASE 0x2c04f000 +#define PLAT_ARM_GICV_BASE 0x2c06f000 + +/* MHU related constants */ +#define PLAT_CSS_MHU_BASE 0x2b1f0000 + +/* + * Base address of the first memory region used for communication between AP + * and SCP. Used by the BOM and SCPI protocols. + * + * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which + * means the SCP/AP configuration data gets overwritten when the AP initiates + * communication with the SCP. The configuration data is expected to be a + * 32-bit word on all CSS platforms. On Juno, part of this configuration is + * which CPU is the primary, according to the shift and mask definitions below. + */ +#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) +#define PLAT_CSS_PRIMARY_CPU_SHIFT 8 +#define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 + +/* + * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current + * SCP_BL2 size plus a little space for growth. + */ +#define PLAT_CSS_MAX_SCP_BL2_SIZE 0x1D000 + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_ARM_G1S_IRQS CSS_G1S_IRQS, \ + ARM_G1S_IRQS, \ + JUNO_IRQ_DMA_SMMU, \ + JUNO_IRQ_HDLCD0_SMMU, \ + JUNO_IRQ_HDLCD1_SMMU, \ + JUNO_IRQ_USB_SMMU, \ + JUNO_IRQ_THIN_LINKS_SMMU, \ + JUNO_IRQ_SEC_I2C, \ + JUNO_IRQ_GPU_SMMU_1, \ + JUNO_IRQ_ETR_SMMU + +#define PLAT_ARM_G0_IRQS ARM_G0_IRQS + +/* + * Required ARM CSS SoC based platform porting definitions + */ + +/* CSS SoC NIC-400 Global Programmers View (GPV) */ +#define PLAT_SOC_CSS_NIC400_BASE 0x2a000000 + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/include/platform_oid.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/include/platform_oid.h new file mode 100644 index 0000000..1e44cf7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/include/platform_oid.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include "../../../../../include/plat/arm/board/common/board_arm_oid.h" + +/* + * Required platform OIDs + * (Provided by included header) + */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_bl1_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_bl1_setup.c new file mode 100644 index 0000000..e805c9a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_bl1_setup.c @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#define RESET_REASON_WDOG_RESET (0x2) + +/******************************************************************************* + * The following function checks if Firmware update is needed, + * by checking if TOC in FIP image is valid or watchdog reset happened. + ******************************************************************************/ +unsigned int bl1_plat_get_next_image_id(void) +{ + unsigned int *reset_flags_ptr = (unsigned int *)SSC_GPRETN; + unsigned int *nv_flags_ptr = (unsigned int *) + (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS); + /* + * Check if TOC is invalid or watchdog reset happened. + */ + if ((arm_io_is_toc_valid() != 1) || + ((*reset_flags_ptr & RESET_REASON_WDOG_RESET) && + ((*nv_flags_ptr == -EAUTH) || (*nv_flags_ptr == -ENOENT)))) + return NS_BL1U_IMAGE_ID; + + return BL2_IMAGE_ID; +} + +/******************************************************************************* + * On JUNO update the arg2 with address of SCP_BL2U image info. + ******************************************************************************/ +void bl1_plat_set_ep_info(unsigned int image_id, + entry_point_info_t *ep_info) +{ + if (image_id == BL2U_IMAGE_ID) { + image_desc_t *image_desc = bl1_plat_get_image_desc(SCP_BL2U_IMAGE_ID); + ep_info->args.arg2 = (unsigned long)&image_desc->image_info; + } +} + +/******************************************************************************* + * On Juno clear SYS_NVFLAGS and wait for watchdog reset. + ******************************************************************************/ +__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved) +{ + unsigned int *nv_flags_clr = (unsigned int *) + (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR); + unsigned int *nv_flags_ptr = (unsigned int *) + (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS); + + /* Clear the NV flags register. */ + *nv_flags_clr = *nv_flags_ptr; + + while (1) + wfi(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_def.h new file mode 100644 index 0000000..f27bbb2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_def.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __JUNO_DEF_H__ +#define __JUNO_DEF_H__ + + +/******************************************************************************* + * Juno memory map related constants + ******************************************************************************/ + +/* Board revisions */ +#define REV_JUNO_R0 0x1 /* Rev B */ +#define REV_JUNO_R1 0x2 /* Rev C */ +#define REV_JUNO_R2 0x3 /* Rev D */ + +/* Bypass offset from start of NOR flash */ +#define BL1_ROM_BYPASS_OFFSET 0x03EC0000 + +#define EMMC_BASE 0x0c000000 +#define EMMC_SIZE 0x04000000 + +#define PSRAM_BASE 0x14000000 +#define PSRAM_SIZE 0x02000000 + +#define JUNO_SSC_VER_PART_NUM 0x030 + +/******************************************************************************* + * Juno topology related constants + ******************************************************************************/ +#define JUNO_CLUSTER_COUNT 2 +#define JUNO_CLUSTER0_CORE_COUNT 2 +#define JUNO_CLUSTER1_CORE_COUNT 4 + +/******************************************************************************* + * TZC-400 related constants + ******************************************************************************/ +#define TZC400_NSAID_CCI400 0 /* Note: Same as default NSAID!! */ +#define TZC400_NSAID_PCIE 1 +#define TZC400_NSAID_HDLCD0 2 +#define TZC400_NSAID_HDLCD1 3 +#define TZC400_NSAID_USB 4 +#define TZC400_NSAID_DMA330 5 +#define TZC400_NSAID_THINLINKS 6 +#define TZC400_NSAID_AP 9 +#define TZC400_NSAID_GPU 10 +#define TZC400_NSAID_SCP 11 +#define TZC400_NSAID_CORESIGHT 12 + +/******************************************************************************* + * MMU-401 related constants + ******************************************************************************/ +#define MMU401_SSD_OFFSET 0x4000 +#define MMU401_DMA330_BASE 0x7fb00000 + +/******************************************************************************* + * Interrupt handling constants + ******************************************************************************/ +#define JUNO_IRQ_DMA_SMMU 126 +#define JUNO_IRQ_HDLCD0_SMMU 128 +#define JUNO_IRQ_HDLCD1_SMMU 130 +#define JUNO_IRQ_USB_SMMU 132 +#define JUNO_IRQ_THIN_LINKS_SMMU 134 +#define JUNO_IRQ_SEC_I2C 137 +#define JUNO_IRQ_GPU_SMMU_1 73 +#define JUNO_IRQ_ETR_SMMU 75 + +#endif /* __JUNO_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_err.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_err.c new file mode 100644 index 0000000..fa19da7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_err.c @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#define V2M_SYS_NVFLAGS_ADDR (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS) + +/* + * Juno error handler + */ +void plat_error_handler(int err) +{ + uint32_t *flags_ptr = (uint32_t *)V2M_SYS_NVFLAGS_ADDR; + + /* Propagate the err code in the NV-flags register */ + *flags_ptr = err; + + /* Loop until the watchdog resets the system */ + for (;;) + wfi(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_pm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_pm.c new file mode 100644 index 0000000..c355d94 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_pm.c @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + +/* + * Custom `validate_power_state` handler for Juno. According to PSCI + * Specification, interrupts targeted to cores in PSCI CPU SUSPEND should + * be able to resume it. On Juno, when the system power domain is suspended, + * the GIC is also powered down. The SCP resumes the final core to be suspend + * when an external wake-up event is received. But the other cores cannot be + * woken up by a targeted interrupt, because GIC doesn't forward these + * interrupts to the SCP. Due to this hardware limitation, we down-grade PSCI + * CPU SUSPEND requests targeted to the system power domain level + * to cluster power domain level. + * + * The system power domain suspend on Juno is only supported only via + * PSCI SYSTEM SUSPEND API. + */ +static int juno_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int rc; + rc = arm_validate_power_state(power_state, req_state); + + /* + * Ensure that the system power domain level is never suspended + * via PSCI CPU SUSPEND API. Currently system suspend is only + * supported via PSCI SYSTEM SUSPEND API. + */ + req_state->pwr_domain_state[ARM_PWR_LVL2] = ARM_LOCAL_STATE_RUN; + return rc; +} + +/* + * Custom `translate_power_state_by_mpidr` handler for Juno. Unlike in the + * `juno_validate_power_state`, we do not down-grade the system power + * domain level request in `power_state` as it will be used to query the + * PSCI_STAT_COUNT/RESIDENCY at the system power domain level. + */ +static int juno_translate_power_state_by_mpidr(u_register_t mpidr, + unsigned int power_state, + psci_power_state_t *output_state) +{ + return arm_validate_power_state(power_state, output_state); +} + +/******************************************************************************* + * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard + * platform will take care of registering the handlers with PSCI. + ******************************************************************************/ +const plat_psci_ops_t plat_arm_psci_pm_ops = { + .pwr_domain_on = css_pwr_domain_on, + .pwr_domain_on_finish = css_pwr_domain_on_finish, + .pwr_domain_off = css_pwr_domain_off, + .cpu_standby = css_cpu_standby, + .pwr_domain_suspend = css_pwr_domain_suspend, + .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish, + .system_off = css_system_off, + .system_reset = css_system_reset, + .validate_power_state = juno_validate_power_state, + .validate_ns_entrypoint = arm_validate_ns_entrypoint, + .get_sys_suspend_power_state = css_get_sys_suspend_power_state, + .translate_power_state_by_mpidr = juno_translate_power_state_by_mpidr, + .get_node_hw_state = css_node_hw_state +}; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_security.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_security.c new file mode 100644 index 0000000..202342a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_security.c @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "juno_def.h" + + +/******************************************************************************* + * Set up the MMU-401 SSD tables. The power-on configuration has all stream IDs + * assigned to Non-Secure except some for the DMA-330. Assign those back to the + * Non-Secure world as well, otherwise EL1 may end up erroneously generating + * (untranslated) Secure transactions if it turns the SMMU on. + ******************************************************************************/ +static void init_mmu401(void) +{ + uint32_t reg = mmio_read_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET); + reg |= 0x1FF; + mmio_write_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET, reg); +} + +/******************************************************************************* + * Program CSS-NIC400 to allow non-secure access to some CSS regions. + ******************************************************************************/ +static void css_init_nic400(void) +{ + /* Note: This is the NIC-400 device on the CSS */ + mmio_write_32(PLAT_SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE), + ~0); +} + +/******************************************************************************* + * Initialize the secure environment. + ******************************************************************************/ +void plat_arm_security_setup(void) +{ + /* Initialize the TrustZone Controller */ + arm_tzc400_setup(); + /* Do ARM CSS internal NIC setup */ + css_init_nic400(); + /* Do ARM CSS SoC security setup */ + soc_css_security_setup(); + /* Initialize the SMMU SSD tables*/ + init_mmu401(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_topology.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_topology.c new file mode 100644 index 0000000..ee4ec44 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/juno_topology.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "juno_def.h" + +/* + * On Juno, the system power level is the highest power level. + * The first entry in the power domain descriptor specifies the + * number of system power domains i.e. 1. + */ +#define JUNO_PWR_DOMAINS_AT_MAX_PWR_LVL ARM_SYSTEM_COUNT + +/* + * The Juno power domain tree descriptor. The cluster power domains + * are arranged so that when the PSCI generic code creates the power + * domain tree, the indices of the CPU power domain nodes it allocates + * match the linear indices returned by plat_core_pos_by_mpidr() + * i.e. CLUSTER1 CPUs are allocated indices from 0 to 3 and the higher + * indices for CLUSTER0 CPUs. + */ +const unsigned char juno_power_domain_tree_desc[] = { + /* No of root nodes */ + JUNO_PWR_DOMAINS_AT_MAX_PWR_LVL, + /* No of children for the root node */ + JUNO_CLUSTER_COUNT, + /* No of children for the first cluster node */ + JUNO_CLUSTER1_CORE_COUNT, + /* No of children for the second cluster node */ + JUNO_CLUSTER0_CORE_COUNT +}; + +/******************************************************************************* + * This function returns the Juno topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return juno_power_domain_tree_desc; +} + +/******************************************************************************* + * This function returns the core count within the cluster corresponding to + * `mpidr`. + ******************************************************************************/ +unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr) +{ + return (((mpidr) & 0x100) ? JUNO_CLUSTER1_CORE_COUNT :\ + JUNO_CLUSTER0_CORE_COUNT); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/platform.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/platform.mk new file mode 100644 index 0000000..c1cfffc --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/platform.mk @@ -0,0 +1,91 @@ +# +# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +JUNO_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c \ + plat/arm/common/arm_gicv2.c + +JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \ + plat/arm/common/arm_cci.c + +JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \ + plat/arm/board/juno/juno_security.c \ + plat/arm/common/arm_tzc400.c + + +PLAT_INCLUDES := -Iplat/arm/board/juno/include + +PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/aarch64/juno_helpers.S + +BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + lib/cpus/aarch64/cortex_a72.S \ + plat/arm/board/juno/juno_bl1_setup.c \ + plat/arm/board/juno/juno_err.c \ + ${JUNO_INTERCONNECT_SOURCES} + +BL2_SOURCES += plat/arm/board/juno/juno_err.c \ + ${JUNO_SECURITY_SOURCES} + +BL2U_SOURCES += ${JUNO_SECURITY_SOURCES} + +BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + lib/cpus/aarch64/cortex_a72.S \ + plat/arm/board/juno/juno_pm.c \ + plat/arm/board/juno/juno_topology.c \ + ${JUNO_GIC_SOURCES} \ + ${JUNO_INTERCONNECT_SOURCES} \ + ${JUNO_SECURITY_SOURCES} + +# Enable workarounds for selected Cortex-A57 erratas. +ERRATA_A57_806969 := 0 +ERRATA_A57_813420 := 1 + +# Enable option to skip L1 data cache flush during the Cortex-A57 cluster +# power down sequence +SKIP_A57_L1_FLUSH_PWR_DWN := 1 + +# Disable the PSCI platform compatibility layer +ENABLE_PLAT_COMPAT := 0 + +# Enable memory map related constants optimisation +ARM_BOARD_OPTIMISE_MEM := 1 + +include plat/arm/board/common/board_css.mk +include plat/arm/common/arm_common.mk +include plat/arm/soc/common/soc_css.mk +include plat/arm/css/common/css_common.mk + +ifeq (${KEY_ALG},ecdsa) + $(error "ECDSA key algorithm is not fully supported on Juno.") +endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/tsp/tsp-juno.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/tsp/tsp-juno.mk new file mode 100644 index 0000000..4e80607 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/board/juno/tsp/tsp-juno.mk @@ -0,0 +1,35 @@ +# +# Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +BL32_SOURCES += plat/arm/board/juno/juno_topology.c \ + plat/arm/css/common/css_topology.c \ + ${JUNO_GIC_SOURCES} + +include plat/arm/common/tsp/arm_tsp.mk diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c new file mode 100644 index 0000000..9c92e5e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + +/******************************************************************************* + * Following descriptor provides BL image/ep information that gets used + * by BL2 to load the images and also subset of this information is + * passed to next BL image. The image loading sequence is managed by + * populating the images in required loading order. The image execution + * sequence is managed by populating the `next_handoff_image_id` with + * the next executable image id. + ******************************************************************************/ +static bl_mem_params_node_t bl2_mem_params_descs[] = { +#ifdef SCP_BL2_BASE + /* Fill SCP_BL2 related information if it exists */ + { + .image_id = SCP_BL2_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = SCP_BL2_BASE, + .image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE, + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, +#endif /* SCP_BL2_BASE */ + + /* Fill BL32 related information */ + { + .image_id = BL32_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL32_BASE, + .ep_info.spsr = SPSR_MODE32(MODE32_mon, SPSR_T_ARM, + SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + + .next_handoff_image_id = BL33_IMAGE_ID, + }, + + /* Fill BL33 related information */ + { + .image_id = BL33_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), +#ifdef PRELOADED_BL33_BASE + .ep_info.pc = PRELOADED_BL33_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), +#else + .ep_info.pc = PLAT_ARM_NS_IMAGE_OFFSET, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = PLAT_ARM_NS_IMAGE_OFFSET, + .image_info.image_max_size = ARM_DRAM1_SIZE, +#endif /* PRELOADED_BL33_BASE */ + + .next_handoff_image_id = INVALID_IMAGE_ID, + } +}; + +REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/aarch32/arm_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/aarch32/arm_helpers.S new file mode 100644 index 0000000..0839913 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/aarch32/arm_helpers.S @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + + .weak plat_arm_calc_core_pos + .weak plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void) + * This function uses the plat_arm_calc_core_pos() + * definition to get the index of the calling CPU. + * ----------------------------------------------------- + */ +func plat_my_core_pos + ldcopr r0, MPIDR + b plat_arm_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_arm_calc_core_pos(uint64_t mpidr) + * Helper function to calculate the core position. + * With this function: CorePos = (ClusterId * 4) + + * CoreId + * ----------------------------------------------------- + */ +func plat_arm_calc_core_pos + and r1, r0, #MPIDR_CPU_MASK + and r0, r0, #MPIDR_CLUSTER_MASK + add r0, r1, r0, LSR #6 + bx lr +endfunc plat_arm_calc_core_pos diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c new file mode 100644 index 0000000..64315f7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c @@ -0,0 +1,152 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + +/******************************************************************************* + * Following descriptor provides BL image/ep information that gets used + * by BL2 to load the images and also subset of this information is + * passed to next BL image. The image loading sequence is managed by + * populating the images in required loading order. The image execution + * sequence is managed by populating the `next_handoff_image_id` with + * the next executable image id. + ******************************************************************************/ +static bl_mem_params_node_t bl2_mem_params_descs[] = { +#ifdef SCP_BL2_BASE + /* Fill SCP_BL2 related information if it exists */ + { + .image_id = SCP_BL2_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = SCP_BL2_BASE, + .image_info.image_max_size = PLAT_CSS_MAX_SCP_BL2_SIZE, + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, +#endif /* SCP_BL2_BASE */ + +#ifdef EL3_PAYLOAD_BASE + /* Fill EL3 payload related information (BL31 is EL3 payload)*/ + { + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = EL3_PAYLOAD_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, + IMAGE_ATTRIB_PLAT_SETUP | IMAGE_ATTRIB_SKIP_LOADING), + + .next_handoff_image_id = INVALID_IMAGE_ID, + }, + +#else /* EL3_PAYLOAD_BASE */ + + /* Fill BL31 related information */ + { + .image_id = BL31_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, + SECURE | EXECUTABLE | EP_FIRST_EXE), + .ep_info.pc = BL31_BASE, + .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS), +#if DEBUG + .ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL, +#endif + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP), + .image_info.image_base = BL31_BASE, + .image_info.image_max_size = BL31_LIMIT - BL31_BASE, + +# ifdef BL32_BASE + .next_handoff_image_id = BL32_IMAGE_ID, +# else + .next_handoff_image_id = BL33_IMAGE_ID, +# endif + }, + +# ifdef BL32_BASE + /* Fill BL32 related information */ + { + .image_id = BL32_IMAGE_ID, + + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), + .ep_info.pc = BL32_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = BL32_BASE, + .image_info.image_max_size = BL32_LIMIT - BL32_BASE, + + .next_handoff_image_id = BL33_IMAGE_ID, + }, +# endif /* BL32_BASE */ + + /* Fill BL33 related information */ + { + .image_id = BL33_IMAGE_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, + VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE), +# ifdef PRELOADED_BL33_BASE + .ep_info.pc = PRELOADED_BL33_BASE, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), +# else + .ep_info.pc = PLAT_ARM_NS_IMAGE_OFFSET, + + SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, + VERSION_2, image_info_t, 0), + .image_info.image_base = PLAT_ARM_NS_IMAGE_OFFSET, + .image_info.image_max_size = ARM_DRAM1_SIZE, +# endif /* PRELOADED_BL33_BASE */ + + .next_handoff_image_id = INVALID_IMAGE_ID, + } +#endif /* EL3_PAYLOAD_BASE */ +}; + +REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs) diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/aarch64/arm_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/aarch64/arm_helpers.S new file mode 100644 index 0000000..d782020 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/aarch64/arm_helpers.S @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + + .weak plat_arm_calc_core_pos + .weak plat_my_core_pos + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl platform_mem_init + + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void) + * This function uses the plat_arm_calc_core_pos() + * definition to get the index of the calling CPU. + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_arm_calc_core_pos +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) + * Helper function to calculate the core position. + * With this function: CorePos = (ClusterId * 4) + + * CoreId + * ----------------------------------------------------- + */ +func plat_arm_calc_core_pos + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc plat_arm_calc_core_pos + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0 - x4 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, PLAT_ARM_CRASH_UART_BASE + mov_imm x1, PLAT_ARM_CRASH_UART_CLK_IN_HZ + mov_imm x2, ARM_CONSOLE_BAUDRATE + b console_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, PLAT_ARM_CRASH_UART_BASE + b console_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------------------------------- + * We don't need to carry out any memory initialization on ARM + * platforms. The Secure RAM is accessible straight away. + * --------------------------------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl1_fwu.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl1_fwu.c new file mode 100644 index 0000000..2a18d34 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl1_fwu.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + + +/* Struct to keep track of usable memory */ +typedef struct bl1_mem_info { + uintptr_t mem_base; + unsigned int mem_size; +} bl1_mem_info_t; + +bl1_mem_info_t fwu_addr_map_secure[] = { + { + .mem_base = ARM_SHARED_RAM_BASE, + .mem_size = ARM_SHARED_RAM_SIZE + }, + { + .mem_size = 0 + } +}; + +bl1_mem_info_t fwu_addr_map_non_secure[] = { + { + .mem_base = ARM_NS_DRAM1_BASE, + .mem_size = ARM_NS_DRAM1_SIZE + }, + { + .mem_base = PLAT_ARM_NVM_BASE, + .mem_size = PLAT_ARM_NVM_SIZE + }, + { + .mem_size = 0 + } +}; + +int bl1_plat_mem_check(uintptr_t mem_base, + unsigned int mem_size, + unsigned int flags) +{ + unsigned int index = 0; + bl1_mem_info_t *mmap; + + assert(mem_base); + assert(mem_size); + + /* + * Check the given image source and size. + */ + if (GET_SECURITY_STATE(flags) == SECURE) + mmap = fwu_addr_map_secure; + else + mmap = fwu_addr_map_non_secure; + + while (mmap[index].mem_size) { + if ((mem_base >= mmap[index].mem_base) && + ((mem_base + mem_size) + <= (mmap[index].mem_base + + mmap[index].mem_size))) + return 0; + + index++; + } + + return -ENOMEM; +} + +/******************************************************************************* + * This function does linear search for image_id and returns image_desc. + ******************************************************************************/ +image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) +{ + unsigned int index = 0; + + while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { + if (bl1_tbbr_image_descs[index].image_id == image_id) + return &bl1_tbbr_image_descs[index]; + index++; + } + + return NULL; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl1_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl1_setup.c new file mode 100644 index 0000000..50d102a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl1_setup.c @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../bl1/bl1_private.h" + + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ +#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif + + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak bl1_early_platform_setup +#pragma weak bl1_plat_arch_setup +#pragma weak bl1_platform_setup +#pragma weak bl1_plat_sec_mem_layout + + +/* Data structure which holds the extents of the trusted SRAM for BL1*/ +static meminfo_t bl1_tzram_layout; + +meminfo_t *bl1_plat_sec_mem_layout(void) +{ + return &bl1_tzram_layout; +} + +/******************************************************************************* + * BL1 specific platform actions shared between ARM standard platforms. + ******************************************************************************/ +void arm_bl1_early_platform_setup(void) +{ + +#if !ARM_DISABLE_TRUSTED_WDOG + /* Enable watchdog */ + sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL); +#endif + + /* Initialize the console to provide early debug support */ + console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE); + + /* Allow BL1 to see the whole Trusted RAM */ + bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; + bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; + +#if !LOAD_IMAGE_V2 + /* Calculate how much RAM BL1 is using and how much remains free */ + bl1_tzram_layout.free_base = ARM_BL_RAM_BASE; + bl1_tzram_layout.free_size = ARM_BL_RAM_SIZE; + reserve_mem(&bl1_tzram_layout.free_base, + &bl1_tzram_layout.free_size, + BL1_RAM_BASE, + BL1_RAM_LIMIT - BL1_RAM_BASE); +#endif /* LOAD_IMAGE_V2 */ +} + +void bl1_early_platform_setup(void) +{ + arm_bl1_early_platform_setup(); + + /* + * Initialize Interconnect for this cluster during cold boot. + * No need for locks as no other CPU is active. + */ + plat_arm_interconnect_init(); + /* + * Enable Interconnect coherency for the primary CPU's cluster. + */ + plat_arm_interconnect_enter_coherency(); +} + +/****************************************************************************** + * Perform the very early platform specific architecture setup shared between + * ARM standard platforms. This only does basic initialization. Later + * architectural setup (bl1_arch_setup()) does not do anything platform + * specific. + *****************************************************************************/ +void arm_bl1_plat_arch_setup(void) +{ + arm_setup_page_tables(bl1_tzram_layout.total_base, + bl1_tzram_layout.total_size, + BL_CODE_BASE, + BL1_CODE_LIMIT, + BL1_RO_DATA_BASE, + BL1_RO_DATA_LIMIT +#if USE_COHERENT_MEM + , BL1_COHERENT_RAM_BASE, + BL1_COHERENT_RAM_LIMIT +#endif + ); +#ifdef AARCH32 + enable_mmu_secure(0); +#else + enable_mmu_el3(0); +#endif /* AARCH32 */ +} + +void bl1_plat_arch_setup(void) +{ + arm_bl1_plat_arch_setup(); +} + +/* + * Perform the platform specific architecture setup shared between + * ARM standard platforms. + */ +void arm_bl1_platform_setup(void) +{ + /* Initialise the IO layer and register platform IO devices */ + plat_arm_io_setup(); +} + +void bl1_platform_setup(void) +{ + arm_bl1_platform_setup(); +} + +void bl1_plat_prepare_exit(entry_point_info_t *ep_info) +{ +#if !ARM_DISABLE_TRUSTED_WDOG + /* Disable watchdog before leaving BL1 */ + sp805_stop(ARM_SP805_TWDG_BASE); +#endif + +#ifdef EL3_PAYLOAD_BASE + /* + * Program the EL3 payload's entry point address into the CPUs mailbox + * in order to release secondary CPUs from their holding pen and make + * them jump there. + */ + arm_program_trusted_mailbox(ep_info->pc); + dsbsy(); + sev(); +#endif +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl2_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl2_setup.c new file mode 100644 index 0000000..a4fac0d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl2_setup.c @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ +#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif + +/* Data structure which holds the extents of the trusted SRAM for BL2 */ +static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak bl2_early_platform_setup +#pragma weak bl2_platform_setup +#pragma weak bl2_plat_arch_setup +#pragma weak bl2_plat_sec_mem_layout + +#if LOAD_IMAGE_V2 + +#pragma weak bl2_plat_handle_post_image_load + +#else /* LOAD_IMAGE_V2 */ + +/******************************************************************************* + * This structure represents the superset of information that is passed to + * BL31, e.g. while passing control to it from BL2, bl31_params + * and other platform specific params + ******************************************************************************/ +typedef struct bl2_to_bl31_params_mem { + bl31_params_t bl31_params; + image_info_t bl31_image_info; + image_info_t bl32_image_info; + image_info_t bl33_image_info; + entry_point_info_t bl33_ep_info; + entry_point_info_t bl32_ep_info; + entry_point_info_t bl31_ep_info; +} bl2_to_bl31_params_mem_t; + + +static bl2_to_bl31_params_mem_t bl31_params_mem; + + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak bl2_plat_get_bl31_params +#pragma weak bl2_plat_get_bl31_ep_info +#pragma weak bl2_plat_flush_bl31_params +#pragma weak bl2_plat_set_bl31_ep_info +#pragma weak bl2_plat_get_scp_bl2_meminfo +#pragma weak bl2_plat_get_bl32_meminfo +#pragma weak bl2_plat_set_bl32_ep_info +#pragma weak bl2_plat_get_bl33_meminfo +#pragma weak bl2_plat_set_bl33_ep_info + +#if ARM_BL31_IN_DRAM +meminfo_t *bl2_plat_sec_mem_layout(void) +{ + static meminfo_t bl2_dram_layout + __aligned(CACHE_WRITEBACK_GRANULE) = { + .total_base = BL31_BASE, + .total_size = (ARM_AP_TZC_DRAM1_BASE + + ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE, + .free_base = BL31_BASE, + .free_size = (ARM_AP_TZC_DRAM1_BASE + + ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE + }; + + return &bl2_dram_layout; +} +#else +meminfo_t *bl2_plat_sec_mem_layout(void) +{ + return &bl2_tzram_layout; +} +#endif /* ARM_BL31_IN_DRAM */ + +/******************************************************************************* + * This function assigns a pointer to the memory that the platform has kept + * aside to pass platform specific and trusted firmware related information + * to BL31. This memory is allocated by allocating memory to + * bl2_to_bl31_params_mem_t structure which is a superset of all the + * structure whose information is passed to BL31 + * NOTE: This function should be called only once and should be done + * before generating params to BL31 + ******************************************************************************/ +bl31_params_t *bl2_plat_get_bl31_params(void) +{ + bl31_params_t *bl2_to_bl31_params; + + /* + * Initialise the memory for all the arguments that needs to + * be passed to BL31 + */ + memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); + + /* Assign memory for TF related information */ + bl2_to_bl31_params = &bl31_params_mem.bl31_params; + SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); + + /* Fill BL31 related information */ + bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, + VERSION_1, 0); + + /* Fill BL32 related information if it exists */ +#ifdef BL32_BASE + bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, + VERSION_1, 0); + bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, + VERSION_1, 0); +#endif /* BL32_BASE */ + + /* Fill BL33 related information */ + bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, + PARAM_EP, VERSION_1, 0); + + /* BL33 expects to receive the primary CPU MPID (through x0) */ + bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); + + bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, + VERSION_1, 0); + + return bl2_to_bl31_params; +} + +/* Flush the TF params and the TF plat params */ +void bl2_plat_flush_bl31_params(void) +{ + flush_dcache_range((unsigned long)&bl31_params_mem, + sizeof(bl2_to_bl31_params_mem_t)); +} + +/******************************************************************************* + * This function returns a pointer to the shared memory that the platform + * has kept to point to entry point information of BL31 to BL2 + ******************************************************************************/ +struct entry_point_info *bl2_plat_get_bl31_ep_info(void) +{ +#if DEBUG + bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL; +#endif + + return &bl31_params_mem.bl31_ep_info; +} +#endif /* LOAD_IMAGE_V2 */ + +/******************************************************************************* + * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 + * in x0. This memory layout is sitting at the base of the free trusted SRAM. + * Copy it to a safe location before its reclaimed by later BL2 functionality. + ******************************************************************************/ +void arm_bl2_early_platform_setup(meminfo_t *mem_layout) +{ + /* Initialize the console to provide early debug support */ + console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE); + + /* Setup the BL2 memory layout */ + bl2_tzram_layout = *mem_layout; + + /* Initialise the IO layer and register platform IO devices */ + plat_arm_io_setup(); +} + +void bl2_early_platform_setup(meminfo_t *mem_layout) +{ + arm_bl2_early_platform_setup(mem_layout); +} + +/* + * Perform ARM standard platform setup. + */ +void arm_bl2_platform_setup(void) +{ + /* Initialize the secure environment */ + plat_arm_security_setup(); +} + +void bl2_platform_setup(void) +{ + arm_bl2_platform_setup(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only initializes the mmu in a quick and dirty way. + ******************************************************************************/ +void arm_bl2_plat_arch_setup(void) +{ + arm_setup_page_tables(bl2_tzram_layout.total_base, + bl2_tzram_layout.total_size, + BL_CODE_BASE, + BL_CODE_LIMIT, + BL_RO_DATA_BASE, + BL_RO_DATA_LIMIT +#if USE_COHERENT_MEM + , BL2_COHERENT_RAM_BASE, + BL2_COHERENT_RAM_LIMIT +#endif + ); + +#ifdef AARCH32 + enable_mmu_secure(0); +#else + enable_mmu_el1(0); +#endif +} + +void bl2_plat_arch_setup(void) +{ + arm_bl2_plat_arch_setup(); +} + +#if LOAD_IMAGE_V2 +/******************************************************************************* + * This function can be used by the platforms to update/use image + * information for given `image_id`. + ******************************************************************************/ +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + int err = 0; + bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); + assert(bl_mem_params); + + switch (image_id) { +#ifdef AARCH64 + case BL32_IMAGE_ID: + bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry(); + break; +#endif + + case BL33_IMAGE_ID: + /* BL33 expects to receive the primary CPU MPID (through r0) */ + bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); + bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry(); + break; + +#ifdef SCP_BL2_BASE + case SCP_BL2_IMAGE_ID: + /* The subsequent handling of SCP_BL2 is platform specific */ + err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info); + if (err) { + WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); + } + break; +#endif + } + + return err; +} + +#else /* LOAD_IMAGE_V2 */ + +/******************************************************************************* + * Populate the extents of memory available for loading SCP_BL2 (if used), + * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. + ******************************************************************************/ +void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) +{ + *scp_bl2_meminfo = bl2_tzram_layout; +} + +/******************************************************************************* + * Before calling this function BL31 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL31 and set SPSR and security state. + * On ARM standard platforms we only set the security state of the entrypoint + ******************************************************************************/ +void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, + entry_point_info_t *bl31_ep_info) +{ + SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); + bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); +} + + +/******************************************************************************* + * Before calling this function BL32 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL32 and set SPSR and security state. + * On ARM standard platforms we only set the security state of the entrypoint + ******************************************************************************/ +#ifdef BL32_BASE +void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, + entry_point_info_t *bl32_ep_info) +{ + SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); + bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry(); +} + +/******************************************************************************* + * Populate the extents of memory available for loading BL32 + ******************************************************************************/ +void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) +{ + /* + * Populate the extents of memory available for loading BL32. + */ + bl32_meminfo->total_base = BL32_BASE; + bl32_meminfo->free_base = BL32_BASE; + bl32_meminfo->total_size = + (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; + bl32_meminfo->free_size = + (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; +} +#endif /* BL32_BASE */ + +/******************************************************************************* + * Before calling this function BL33 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL33 and set SPSR and security state. + * On ARM standard platforms we only set the security state of the entrypoint + ******************************************************************************/ +void bl2_plat_set_bl33_ep_info(image_info_t *image, + entry_point_info_t *bl33_ep_info) +{ + SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); + bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry(); +} + +/******************************************************************************* + * Populate the extents of memory available for loading BL33 + ******************************************************************************/ +void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) +{ + bl33_meminfo->total_base = ARM_NS_DRAM1_BASE; + bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE; + bl33_meminfo->free_base = ARM_NS_DRAM1_BASE; + bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE; +} + +#endif /* LOAD_IMAGE_V2 */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl2u_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl2u_setup.c new file mode 100644 index 0000000..de7d0c2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl2u_setup.c @@ -0,0 +1,113 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ +#define BL2U_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL2U_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak bl2u_platform_setup +#pragma weak bl2u_early_platform_setup +#pragma weak bl2u_plat_arch_setup + +/* + * Perform ARM standard platform setup for BL2U + */ +void arm_bl2u_platform_setup(void) +{ + /* Initialize the secure environment */ + plat_arm_security_setup(); +} + +void bl2u_platform_setup(void) +{ + arm_bl2u_platform_setup(); +} + +void arm_bl2u_early_platform_setup(meminfo_t *mem_layout, void *plat_info) +{ + /* Initialize the console to provide early debug support */ + console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE); +} + +/******************************************************************************* + * BL1 can pass platform dependent information to BL2U in x1. + * In case of ARM CSS platforms x1 contains SCP_BL2U image info. + * In case of ARM FVP platforms x1 is not used. + * In both cases, x0 contains the extents of the memory available to BL2U + ******************************************************************************/ +void bl2u_early_platform_setup(meminfo_t *mem_layout, void *plat_info) +{ + arm_bl2u_early_platform_setup(mem_layout, plat_info); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only initializes the mmu in a quick and dirty way. + * The memory that is used by BL2U is only mapped. + ******************************************************************************/ +void arm_bl2u_plat_arch_setup(void) +{ + arm_setup_page_tables(BL2U_BASE, + BL31_LIMIT, + BL_CODE_BASE, + BL_CODE_LIMIT, + BL_RO_DATA_BASE, + BL_RO_DATA_LIMIT +#if USE_COHERENT_MEM + , + BL2U_COHERENT_RAM_BASE, + BL2U_COHERENT_RAM_LIMIT +#endif + ); + enable_mmu_el1(0); +} + +void bl2u_plat_arch_setup(void) +{ + arm_bl2u_plat_arch_setup(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl31_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl31_setup.c new file mode 100644 index 0000000..bc1ec11 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_bl31_setup.c @@ -0,0 +1,305 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BL31_END (uintptr_t)(&__BL31_END__) + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__) +#endif + +/* + * Placeholder variables for copying the arguments that have been passed to + * BL31 from BL2. + */ +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak bl31_early_platform_setup +#pragma weak bl31_platform_setup +#pragma weak bl31_plat_arch_setup +#pragma weak bl31_plat_get_next_image_ep_info + + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for the + * security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + assert(sec_state_is_valid(type)); + next_image_info = (type == NON_SECURE) + ? &bl33_image_ep_info : &bl32_image_ep_info; + /* + * None of the images on the ARM development platforms can have 0x0 + * as the entrypoint + */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +/******************************************************************************* + * Perform any BL31 early platform setup common to ARM standard platforms. + * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 + * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be + * done before the MMU is initialized so that the memory layout can be used + * while creating page tables. BL2 has flushed this information to memory, so + * we are guaranteed to pick up good data. + ******************************************************************************/ +#if LOAD_IMAGE_V2 +void arm_bl31_early_platform_setup(void *from_bl2, + void *plat_params_from_bl2) +#else +void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +#endif +{ + /* Initialize the console to provide early debug support */ + console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE); + +#if RESET_TO_BL31 + /* There are no parameters from BL2 if BL31 is a reset vector */ + assert(from_bl2 == NULL); + assert(plat_params_from_bl2 == NULL); + +#ifdef BL32_BASE + /* Populate entry point information for BL32 */ + SET_PARAM_HEAD(&bl32_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); +#endif /* BL32_BASE */ + + /* Populate entry point information for BL33 */ + SET_PARAM_HEAD(&bl33_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + /* + * Tell BL31 where the non-trusted software image + * is located and the entry state information + */ + bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); + + bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + +#else /* RESET_TO_BL31 */ + + /* + * In debug builds, we pass a special value in 'plat_params_from_bl2' + * to verify platform parameters from BL2 to BL31. + * In release builds, it's not used. + */ + assert(((unsigned long long)plat_params_from_bl2) == + ARM_BL31_PLAT_PARAM_VAL); + +# if LOAD_IMAGE_V2 + /* + * Check params passed from BL2 should not be NULL, + */ + bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; + assert(params_from_bl2 != NULL); + assert(params_from_bl2->h.type == PARAM_BL_PARAMS); + assert(params_from_bl2->h.version >= VERSION_2); + + bl_params_node_t *bl_params = params_from_bl2->head; + + /* + * Copy BL33 and BL32 (if present), entry point information. + * They are stored in Secure RAM, in BL2's address space. + */ + while (bl_params) { + if (bl_params->image_id == BL32_IMAGE_ID) + bl32_image_ep_info = *bl_params->ep_info; + + if (bl_params->image_id == BL33_IMAGE_ID) + bl33_image_ep_info = *bl_params->ep_info; + + bl_params = bl_params->next_params_info; + } + + if (bl33_image_ep_info.pc == 0) + panic(); + +# else /* LOAD_IMAGE_V2 */ + + /* + * Check params passed from BL2 should not be NULL, + */ + assert(from_bl2 != NULL); + assert(from_bl2->h.type == PARAM_BL31); + assert(from_bl2->h.version >= VERSION_1); + + /* + * Copy BL32 (if populated by BL2) and BL33 entry point information. + * They are stored in Secure RAM, in BL2's address space. + */ + if (from_bl2->bl32_ep_info) + bl32_image_ep_info = *from_bl2->bl32_ep_info; + bl33_image_ep_info = *from_bl2->bl33_ep_info; + +# endif /* LOAD_IMAGE_V2 */ +#endif /* RESET_TO_BL31 */ +} + +#if LOAD_IMAGE_V2 +void bl31_early_platform_setup(void *from_bl2, + void *plat_params_from_bl2) +#else +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +#endif +{ + arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2); + + /* + * Initialize Interconnect for this cluster during cold boot. + * No need for locks as no other CPU is active. + */ + plat_arm_interconnect_init(); + + /* + * Enable Interconnect coherency for the primary CPU's cluster. + * Earlier bootloader stages might already do this (e.g. Trusted + * Firmware's BL1 does it) but we can't assume so. There is no harm in + * executing this code twice anyway. + * Platform specific PSCI code will enable coherency for other + * clusters. + */ + plat_arm_interconnect_enter_coherency(); +} + +/******************************************************************************* + * Perform any BL31 platform setup common to ARM standard platforms + ******************************************************************************/ +void arm_bl31_platform_setup(void) +{ + /* Initialize the GIC driver, cpu and distributor interfaces */ + plat_arm_gic_driver_init(); + plat_arm_gic_init(); + +#if RESET_TO_BL31 + /* + * Do initial security configuration to allow DRAM/device access + * (if earlier BL has not already done so). + */ + plat_arm_security_setup(); + +#endif /* RESET_TO_BL31 */ + + /* Enable and initialize the System level generic timer */ + mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, + CNTCR_FCREQ(0) | CNTCR_EN); + + /* Allow access to the System counter timer module */ + arm_configure_sys_timer(); + + /* Initialize power controller before setting up topology */ + plat_arm_pwrc_setup(); +} + +/******************************************************************************* + * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM + * standard platforms + ******************************************************************************/ +void arm_bl31_plat_runtime_setup(void) +{ + /* Initialize the runtime console */ + console_init(PLAT_ARM_BL31_RUN_UART_BASE, PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE); +} + +void bl31_platform_setup(void) +{ + arm_bl31_platform_setup(); +} + +void bl31_plat_runtime_setup(void) +{ + arm_bl31_plat_runtime_setup(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup shared between + * ARM standard platforms. This only does basic initialization. Later + * architectural setup (bl31_arch_setup()) does not do anything platform + * specific. + ******************************************************************************/ +void arm_bl31_plat_arch_setup(void) +{ + arm_setup_page_tables(BL31_BASE, + BL31_END - BL31_BASE, + BL_CODE_BASE, + BL_CODE_LIMIT, + BL_RO_DATA_BASE, + BL_RO_DATA_LIMIT +#if USE_COHERENT_MEM + , BL31_COHERENT_RAM_BASE, + BL31_COHERENT_RAM_LIMIT +#endif + ); + enable_mmu_el3(0); +} + +void bl31_plat_arch_setup(void) +{ + arm_bl31_plat_arch_setup(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_cci.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_cci.c new file mode 100644 index 0000000..40cfb48 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_cci.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +static const int cci_map[] = { + PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX, + PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX +}; + +/****************************************************************************** + * The following functions are defined as weak to allow a platform to override + * the way ARM CCI driver is initialised and used. + *****************************************************************************/ +#pragma weak plat_arm_interconnect_init +#pragma weak plat_arm_interconnect_enter_coherency +#pragma weak plat_arm_interconnect_exit_coherency + + +/****************************************************************************** + * Helper function to initialize ARM CCI driver. + *****************************************************************************/ +void plat_arm_interconnect_init(void) +{ + cci_init(PLAT_ARM_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); +} + +/****************************************************************************** + * Helper function to place current master into coherency + *****************************************************************************/ +void plat_arm_interconnect_enter_coherency(void) +{ + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); +} + +/****************************************************************************** + * Helper function to remove current master from coherency + *****************************************************************************/ +void plat_arm_interconnect_exit_coherency(void) +{ + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_ccn.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_ccn.c new file mode 100644 index 0000000..fe10d7b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_ccn.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +static const unsigned char master_to_rn_id_map[] = { + PLAT_ARM_CLUSTER_TO_CCN_ID_MAP +}; + +static const ccn_desc_t arm_ccn_desc = { + .periphbase = PLAT_ARM_CCN_BASE, + .num_masters = ARRAY_SIZE(master_to_rn_id_map), + .master_to_rn_id_map = master_to_rn_id_map +}; + +CASSERT(PLAT_ARM_CLUSTER_COUNT == ARRAY_SIZE(master_to_rn_id_map), + assert_invalid_cluster_count_for_ccn_variant); + +/****************************************************************************** + * The following functions are defined as weak to allow a platform to override + * the way ARM CCN driver is initialised and used. + *****************************************************************************/ +#pragma weak plat_arm_interconnect_init +#pragma weak plat_arm_interconnect_enter_coherency +#pragma weak plat_arm_interconnect_exit_coherency + + +/****************************************************************************** + * Helper function to initialize ARM CCN driver. + *****************************************************************************/ +void plat_arm_interconnect_init(void) +{ + ccn_init(&arm_ccn_desc); +} + +/****************************************************************************** + * Helper function to place current master into coherency + *****************************************************************************/ +void plat_arm_interconnect_enter_coherency(void) +{ + ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); +} + +/****************************************************************************** + * Helper function to remove current master from coherency + *****************************************************************************/ +void plat_arm_interconnect_exit_coherency(void) +{ + ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_common.c new file mode 100644 index 0000000..c53723d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_common.c @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +extern const mmap_region_t plat_arm_mmap[]; + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak plat_get_ns_image_entrypoint +#pragma weak plat_arm_get_mmap + +/* Conditionally provide a weak definition of plat_get_syscnt_freq2 to avoid + * conflicts with the definition in plat/common. */ +#if ERROR_DEPRECATED +#pragma weak plat_get_syscnt_freq2 +#endif + +/* + * Set up the page tables for the generic and platform-specific memory regions. + * The extents of the generic memory regions are specified by the function + * arguments and consist of: + * - Trusted SRAM seen by the BL image; + * - Code section; + * - Read-only data section; + * - Coherent memory region, if applicable. + */ +void arm_setup_page_tables(uintptr_t total_base, + size_t total_size, + uintptr_t code_start, + uintptr_t code_limit, + uintptr_t rodata_start, + uintptr_t rodata_limit +#if USE_COHERENT_MEM + , + uintptr_t coh_start, + uintptr_t coh_limit +#endif + ) +{ + /* + * Map the Trusted SRAM with appropriate memory attributes. + * Subsequent mappings will adjust the attributes for specific regions. + */ + VERBOSE("Trusted SRAM seen by this BL image: %p - %p\n", + (void *) total_base, (void *) (total_base + total_size)); + mmap_add_region(total_base, total_base, + total_size, + MT_MEMORY | MT_RW | MT_SECURE); + + /* Re-map the code section */ + VERBOSE("Code region: %p - %p\n", + (void *) code_start, (void *) code_limit); + mmap_add_region(code_start, code_start, + code_limit - code_start, + MT_CODE | MT_SECURE); + + /* Re-map the read-only data section */ + VERBOSE("Read-only data region: %p - %p\n", + (void *) rodata_start, (void *) rodata_limit); + mmap_add_region(rodata_start, rodata_start, + rodata_limit - rodata_start, + MT_RO_DATA | MT_SECURE); + +#if USE_COHERENT_MEM + /* Re-map the coherent memory region */ + VERBOSE("Coherent region: %p - %p\n", + (void *) coh_start, (void *) coh_limit); + mmap_add_region(coh_start, coh_start, + coh_limit - coh_start, + MT_DEVICE | MT_RW | MT_SECURE); +#endif + + /* Now (re-)map the platform-specific memory regions */ + mmap_add(plat_arm_get_mmap()); + + /* Create the page tables to reflect the above mappings */ + init_xlat_tables(); +} + +uintptr_t plat_get_ns_image_entrypoint(void) +{ +#ifdef PRELOADED_BL33_BASE + return PRELOADED_BL33_BASE; +#else + return PLAT_ARM_NS_IMAGE_OFFSET; +#endif +} + +/******************************************************************************* + * Gets SPSR for BL32 entry + ******************************************************************************/ +uint32_t arm_get_spsr_for_bl32_entry(void) +{ + /* + * The Secure Payload Dispatcher service is responsible for + * setting the SPSR prior to entry into the BL32 image. + */ + return 0; +} + +/******************************************************************************* + * Gets SPSR for BL33 entry + ******************************************************************************/ +#ifndef AARCH32 +uint32_t arm_get_spsr_for_bl33_entry(void) +{ + unsigned long el_status; + unsigned int mode; + uint32_t spsr; + + /* Figure out what mode we enter the non-secure world in */ + el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; + el_status &= ID_AA64PFR0_ELX_MASK; + + mode = (el_status) ? MODE_EL2 : MODE_EL1; + + /* + * TODO: Consider the possibility of specifying the SPSR in + * the FIP ToC and allowing the platform to have a say as + * well. + */ + spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + return spsr; +} +#else +/******************************************************************************* + * Gets SPSR for BL33 entry + ******************************************************************************/ +uint32_t arm_get_spsr_for_bl33_entry(void) +{ + unsigned int hyp_status, mode, spsr; + + hyp_status = GET_VIRT_EXT(read_id_pfr1()); + + mode = (hyp_status) ? MODE32_hyp : MODE32_svc; + + /* + * TODO: Consider the possibility of specifying the SPSR in + * the FIP ToC and allowing the platform to have a say as + * well. + */ + spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, + SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); + return spsr; +} +#endif /* AARCH32 */ + +/******************************************************************************* + * Configures access to the system counter timer module. + ******************************************************************************/ +#ifdef ARM_SYS_TIMCTL_BASE +void arm_configure_sys_timer(void) +{ + unsigned int reg_val; + +#if ARM_CONFIG_CNTACR + reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); + reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); + reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); + mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTACR_BASE(PLAT_ARM_NSTIMER_FRAME_ID), reg_val); +#endif /* ARM_CONFIG_CNTACR */ + + reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_ARM_NSTIMER_FRAME_ID)); + mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTNSAR, reg_val); +} +#endif /* ARM_SYS_TIMCTL_BASE */ + +/******************************************************************************* + * Returns ARM platform specific memory map regions. + ******************************************************************************/ +const mmap_region_t *plat_arm_get_mmap(void) +{ + return plat_arm_mmap; +} + +#ifdef ARM_SYS_CNTCTL_BASE + +unsigned int plat_get_syscnt_freq2(void) +{ + unsigned int counter_base_frequency; + + /* Read the frequency from Frequency modes table */ + counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); + + /* The first entry of the frequency modes table must not be 0 */ + if (counter_base_frequency == 0) + panic(); + + return counter_base_frequency; +} + +#endif /* ARM_SYS_CNTCTL_BASE */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_common.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_common.mk new file mode 100644 index 0000000..98d7219 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_common.mk @@ -0,0 +1,180 @@ +# +# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +ifeq (${ARCH}, aarch64) + # On ARM standard platorms, the TSP can execute from Trusted SRAM, Trusted + # DRAM (if available) or the TZC secured area of DRAM. + # Trusted SRAM is the default. + + ARM_TSP_RAM_LOCATION := tsram + ifeq (${ARM_TSP_RAM_LOCATION}, tsram) + ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_SRAM_ID + else ifeq (${ARM_TSP_RAM_LOCATION}, tdram) + ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_DRAM_ID + else ifeq (${ARM_TSP_RAM_LOCATION}, dram) + ARM_TSP_RAM_LOCATION_ID = ARM_DRAM_ID + else + $(error "Unsupported ARM_TSP_RAM_LOCATION value") + endif + + # Process flags + $(eval $(call add_define,ARM_TSP_RAM_LOCATION_ID)) + + # Process ARM_BL31_IN_DRAM flag + ARM_BL31_IN_DRAM := 0 + $(eval $(call assert_boolean,ARM_BL31_IN_DRAM)) + $(eval $(call add_define,ARM_BL31_IN_DRAM)) +endif + +# For the original power-state parameter format, the State-ID can be encoded +# according to the recommended encoding or zero. This flag determines which +# State-ID encoding to be parsed. +ARM_RECOM_STATE_ID_ENC := 0 + +# If the PSCI_EXTENDED_STATE_ID is set, then the recommended state ID need to +# be used. Else throw a build error. +ifeq (${PSCI_EXTENDED_STATE_ID}, 1) + ifeq (${ARM_RECOM_STATE_ID_ENC}, 0) + $(error "Incompatible STATE_ID build option specified") + endif +endif + +# Process ARM_RECOM_STATE_ID_ENC flag +$(eval $(call assert_boolean,ARM_RECOM_STATE_ID_ENC)) +$(eval $(call add_define,ARM_RECOM_STATE_ID_ENC)) + +# Process ARM_DISABLE_TRUSTED_WDOG flag +# By default, Trusted Watchdog is always enabled unless SPIN_ON_BL1_EXIT is set +ARM_DISABLE_TRUSTED_WDOG := 0 +ifeq (${SPIN_ON_BL1_EXIT}, 1) +ARM_DISABLE_TRUSTED_WDOG := 1 +endif +$(eval $(call assert_boolean,ARM_DISABLE_TRUSTED_WDOG)) +$(eval $(call add_define,ARM_DISABLE_TRUSTED_WDOG)) + +# Process ARM_CONFIG_CNTACR +ARM_CONFIG_CNTACR := 1 +$(eval $(call assert_boolean,ARM_CONFIG_CNTACR)) +$(eval $(call add_define,ARM_CONFIG_CNTACR)) + +# Process ARM_BL31_IN_DRAM flag +ARM_BL31_IN_DRAM := 0 +$(eval $(call assert_boolean,ARM_BL31_IN_DRAM)) +$(eval $(call add_define,ARM_BL31_IN_DRAM)) + +# Enable PSCI_STAT_COUNT/RESIDENCY APIs on ARM platforms +ENABLE_PSCI_STAT := 1 + +# On ARM platforms, separate the code and read-only data sections to allow +# mapping the former as executable and the latter as execute-never. +SEPARATE_CODE_AND_RODATA := 1 + + +PLAT_INCLUDES += -Iinclude/common/tbbr \ + -Iinclude/plat/arm/common + +ifeq (${ARCH}, aarch64) +PLAT_INCLUDES += -Iinclude/plat/arm/common/aarch64 +endif + +PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \ + lib/xlat_tables/${ARCH}/xlat_tables.c \ + plat/arm/common/${ARCH}/arm_helpers.S \ + plat/arm/common/arm_common.c \ + plat/common/${ARCH}/plat_common.c + +BL1_SOURCES += drivers/arm/sp805/sp805.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + drivers/io/io_storage.c \ + plat/arm/common/arm_bl1_setup.c \ + plat/arm/common/arm_io_storage.c \ + plat/common/${ARCH}/platform_up_stack.S +ifdef EL3_PAYLOAD_BASE +# Need the arm_program_trusted_mailbox() function to release secondary CPUs from +# their holding pen +BL1_SOURCES += plat/arm/common/arm_pm.c +endif + +BL2_SOURCES += drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + drivers/io/io_storage.c \ + plat/arm/common/arm_bl2_setup.c \ + plat/arm/common/arm_io_storage.c \ + plat/common/${ARCH}/platform_up_stack.S +ifeq (${LOAD_IMAGE_V2},1) +BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c\ + plat/arm/common/arm_image_load.c \ + common/desc_image_load.c +endif + +BL2U_SOURCES += plat/arm/common/arm_bl2u_setup.c \ + plat/common/aarch64/platform_up_stack.S + +BL31_SOURCES += plat/arm/common/arm_bl31_setup.c \ + plat/arm/common/arm_pm.c \ + plat/arm/common/arm_topology.c \ + plat/common/aarch64/platform_mp_stack.S \ + plat/common/plat_psci_common.c + +ifneq (${TRUSTED_BOARD_BOOT},0) + + # By default, ARM platforms use RSA keys + KEY_ALG := rsa + + # Include common TBB sources + AUTH_SOURCES := drivers/auth/auth_mod.c \ + drivers/auth/crypto_mod.c \ + drivers/auth/img_parser_mod.c \ + drivers/auth/tbbr/tbbr_cot.c \ + + PLAT_INCLUDES += -Iinclude/bl1/tbbr + + BL1_SOURCES += ${AUTH_SOURCES} \ + bl1/tbbr/tbbr_img_desc.c \ + plat/arm/common/arm_bl1_fwu.c + + BL2_SOURCES += ${AUTH_SOURCES} + + $(eval $(call FWU_FIP_ADD_IMG,NS_BL2U,--fwu)) + + MBEDTLS_KEY_ALG := ${KEY_ALG} + + # We expect to locate the *.mk files under the directories specified below + CRYPTO_LIB_MK := drivers/auth/mbedtls/mbedtls_crypto.mk + IMG_PARSER_LIB_MK := drivers/auth/mbedtls/mbedtls_x509.mk + + $(info Including ${CRYPTO_LIB_MK}) + include ${CRYPTO_LIB_MK} + + $(info Including ${IMG_PARSER_LIB_MK}) + include ${IMG_PARSER_LIB_MK} + +endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_gicv2.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_gicv2.c new file mode 100644 index 0000000..2636d1c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_gicv2.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +/****************************************************************************** + * The following functions are defined as weak to allow a platform to override + * the way the GICv2 driver is initialised and used. + *****************************************************************************/ +#pragma weak plat_arm_gic_driver_init +#pragma weak plat_arm_gic_init +#pragma weak plat_arm_gic_cpuif_enable +#pragma weak plat_arm_gic_cpuif_disable +#pragma weak plat_arm_gic_pcpu_init + +/****************************************************************************** + * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 + * interrupts. + *****************************************************************************/ +static const unsigned int g0_interrupt_array[] = { + PLAT_ARM_G1S_IRQS, + PLAT_ARM_G0_IRQS +}; + +static const gicv2_driver_data_t arm_gic_data = { + .gicd_base = PLAT_ARM_GICD_BASE, + .gicc_base = PLAT_ARM_GICC_BASE, + .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), + .g0_interrupt_array = g0_interrupt_array, +}; + +/****************************************************************************** + * ARM common helper to initialize the GICv2 only driver. + *****************************************************************************/ +void plat_arm_gic_driver_init(void) +{ + gicv2_driver_init(&arm_gic_data); +} + +void plat_arm_gic_init(void) +{ + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +/****************************************************************************** + * ARM common helper to enable the GICv2 CPU interface + *****************************************************************************/ +void plat_arm_gic_cpuif_enable(void) +{ + gicv2_cpuif_enable(); +} + +/****************************************************************************** + * ARM common helper to disable the GICv2 CPU interface + *****************************************************************************/ +void plat_arm_gic_cpuif_disable(void) +{ + gicv2_cpuif_disable(); +} + +/****************************************************************************** + * ARM common helper to initialize the per cpu distributor interface in GICv2 + *****************************************************************************/ +void plat_arm_gic_pcpu_init(void) +{ + gicv2_pcpu_distif_init(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_gicv3.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_gicv3.c new file mode 100644 index 0000000..ac309f2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_gicv3.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/****************************************************************************** + * The following functions are defined as weak to allow a platform to override + * the way the GICv3 driver is initialised and used. + *****************************************************************************/ +#pragma weak plat_arm_gic_driver_init +#pragma weak plat_arm_gic_init +#pragma weak plat_arm_gic_cpuif_enable +#pragma weak plat_arm_gic_cpuif_disable +#pragma weak plat_arm_gic_pcpu_init + +/* The GICv3 driver only needs to be initialized in EL3 */ +static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; + +/* Array of Group1 secure interrupts to be configured by the gic driver */ +static const unsigned int g1s_interrupt_array[] = { + PLAT_ARM_G1S_IRQS +}; + +/* Array of Group0 interrupts to be configured by the gic driver */ +static const unsigned int g0_interrupt_array[] = { + PLAT_ARM_G0_IRQS +}; + +const gicv3_driver_data_t arm_gic_data = { + .gicd_base = PLAT_ARM_GICD_BASE, + .gicr_base = PLAT_ARM_GICR_BASE, + .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), + .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array), + .g0_interrupt_array = g0_interrupt_array, + .g1s_interrupt_array = g1s_interrupt_array, + .rdistif_num = PLATFORM_CORE_COUNT, + .rdistif_base_addrs = rdistif_base_addrs, + .mpidr_to_core_pos = plat_arm_calc_core_pos +}; + +void plat_arm_gic_driver_init(void) +{ + /* + * The GICv3 driver is initialized in EL3 and does not need + * to be initialized again in SEL1. This is because the S-EL1 + * can use GIC system registers to manage interrupts and does + * not need GIC interface base addresses to be configured. + */ +#if (AARCH32 && IMAGE_BL32) || (IMAGE_BL31 && !AARCH32) + gicv3_driver_init(&arm_gic_data); +#endif +} + +/****************************************************************************** + * ARM common helper to initialize the GIC. Only invoked by BL31 + *****************************************************************************/ +void plat_arm_gic_init(void) +{ + gicv3_distif_init(); + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +/****************************************************************************** + * ARM common helper to enable the GIC CPU interface + *****************************************************************************/ +void plat_arm_gic_cpuif_enable(void) +{ + gicv3_cpuif_enable(plat_my_core_pos()); +} + +/****************************************************************************** + * ARM common helper to disable the GIC CPU interface + *****************************************************************************/ +void plat_arm_gic_cpuif_disable(void) +{ + gicv3_cpuif_disable(plat_my_core_pos()); +} + +/****************************************************************************** + * ARM common helper to initialize the per-cpu redistributor interface in GICv3 + *****************************************************************************/ +void plat_arm_gic_pcpu_init(void) +{ + gicv3_rdistif_init(plat_my_core_pos()); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_gicv3_legacy.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_gicv3_legacy.c new file mode 100644 index 0000000..8396b60 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_gicv3_legacy.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/****************************************************************************** + * The following function is defined as weak to allow a platform to override + * the way the Legacy GICv3 driver is initialised and used. + *****************************************************************************/ +#pragma weak plat_arm_gic_driver_init +#pragma weak plat_arm_gic_init +#pragma weak plat_arm_gic_cpuif_enable +#pragma weak plat_arm_gic_cpuif_disable +#pragma weak plat_arm_gic_pcpu_init + +/* + * In the GICv3 Legacy mode, the Group 1 secure interrupts are treated as Group + * 0 interrupts. + */ +static const unsigned int irq_sec_array[] = { + PLAT_ARM_G0_IRQS, + PLAT_ARM_G1S_IRQS +}; + +void plat_arm_gic_driver_init(void) +{ + arm_gic_init(PLAT_ARM_GICC_BASE, + PLAT_ARM_GICD_BASE, + PLAT_ARM_GICR_BASE, + irq_sec_array, + ARRAY_SIZE(irq_sec_array)); +} + +/****************************************************************************** + * ARM common helper to initialize the GIC. + *****************************************************************************/ +void plat_arm_gic_init(void) +{ + arm_gic_setup(); +} + +/****************************************************************************** + * ARM common helper to enable the GIC CPU interface + *****************************************************************************/ +void plat_arm_gic_cpuif_enable(void) +{ + arm_gic_cpuif_setup(); +} + +/****************************************************************************** + * ARM common helper to disable the GIC CPU interface + *****************************************************************************/ +void plat_arm_gic_cpuif_disable(void) +{ + arm_gic_cpuif_deactivate(); +} + +/****************************************************************************** + * ARM common helper to initialize the per-cpu distributor in GICv2 or + * redistributor interface in GICv3. + *****************************************************************************/ +void plat_arm_gic_pcpu_init(void) +{ + arm_gic_pcpu_distif_setup(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_image_load.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_image_load.c new file mode 100644 index 0000000..cb6db77 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_image_load.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + +#pragma weak plat_flush_next_bl_params +#pragma weak plat_get_bl_image_load_info +#pragma weak plat_get_next_bl_params + + +/******************************************************************************* + * This function flushes the data structures so that they are visible + * in memory for the next BL image. + ******************************************************************************/ +void plat_flush_next_bl_params(void) +{ + flush_bl_params_desc(); +} + +/******************************************************************************* + * This function returns the list of loadable images. + ******************************************************************************/ +bl_load_info_t *plat_get_bl_image_load_info(void) +{ + return get_bl_load_info_from_mem_params_desc(); +} + +/******************************************************************************* + * This function returns the list of executable images. + ******************************************************************************/ +bl_params_t *plat_get_next_bl_params(void) +{ + return get_next_bl_params_from_mem_params_desc(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_io_storage.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_io_storage.c new file mode 100644 index 0000000..42435a7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_io_storage.c @@ -0,0 +1,324 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* IO devices */ +static const io_dev_connector_t *fip_dev_con; +static uintptr_t fip_dev_handle; +static const io_dev_connector_t *memmap_dev_con; +static uintptr_t memmap_dev_handle; + +static const io_block_spec_t fip_block_spec = { + .offset = PLAT_ARM_FIP_BASE, + .length = PLAT_ARM_FIP_MAX_SIZE +}; + +static const io_uuid_spec_t bl2_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, +}; + +static const io_uuid_spec_t scp_bl2_uuid_spec = { + .uuid = UUID_SCP_FIRMWARE_SCP_BL2, +}; + +static const io_uuid_spec_t bl31_uuid_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, +}; + +static const io_uuid_spec_t bl32_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32, +}; + +static const io_uuid_spec_t bl33_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, +}; + +#if TRUSTED_BOARD_BOOT +static const io_uuid_spec_t tb_fw_cert_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FW_CERT, +}; + +static const io_uuid_spec_t trusted_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_KEY_CERT, +}; + +static const io_uuid_spec_t scp_fw_key_cert_uuid_spec = { + .uuid = UUID_SCP_FW_KEY_CERT, +}; + +static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = { + .uuid = UUID_SOC_FW_KEY_CERT, +}; + +static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_OS_FW_KEY_CERT, +}; + +static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FW_KEY_CERT, +}; + +static const io_uuid_spec_t scp_fw_cert_uuid_spec = { + .uuid = UUID_SCP_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t soc_fw_cert_uuid_spec = { + .uuid = UUID_SOC_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t tos_fw_cert_uuid_spec = { + .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT, +}; + +static const io_uuid_spec_t nt_fw_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT, +}; +#endif /* TRUSTED_BOARD_BOOT */ + + +static int open_fip(const uintptr_t spec); +static int open_memmap(const uintptr_t spec); + +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int (*check)(const uintptr_t spec); +}; + +/* By default, ARM platforms load images from the FIP */ +static const struct plat_io_policy policies[] = { + [FIP_IMAGE_ID] = { + &memmap_dev_handle, + (uintptr_t)&fip_block_spec, + open_memmap + }, + [BL2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl2_uuid_spec, + open_fip + }, + [SCP_BL2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&scp_bl2_uuid_spec, + open_fip + }, + [BL31_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl31_uuid_spec, + open_fip + }, + [BL32_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_uuid_spec, + open_fip + }, + [BL33_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl33_uuid_spec, + open_fip + }, +#if TRUSTED_BOARD_BOOT + [TRUSTED_BOOT_FW_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tb_fw_cert_uuid_spec, + open_fip + }, + [TRUSTED_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&trusted_key_cert_uuid_spec, + open_fip + }, + [SCP_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&scp_fw_key_cert_uuid_spec, + open_fip + }, + [SOC_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&soc_fw_key_cert_uuid_spec, + open_fip + }, + [TRUSTED_OS_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tos_fw_key_cert_uuid_spec, + open_fip + }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_key_cert_uuid_spec, + open_fip + }, + [SCP_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&scp_fw_cert_uuid_spec, + open_fip + }, + [SOC_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&soc_fw_cert_uuid_spec, + open_fip + }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&tos_fw_cert_uuid_spec, + open_fip + }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&nt_fw_cert_uuid_spec, + open_fip + }, +#endif /* TRUSTED_BOARD_BOOT */ +}; + + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak plat_arm_io_setup +#pragma weak plat_arm_get_alt_image_source + + +static int open_fip(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + /* See if a Firmware Image Package is available */ + result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); + if (result == 0) { + result = io_open(fip_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using FIP\n"); + io_close(local_image_handle); + } + } + return result; +} + + +static int open_memmap(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(memmap_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using Memmap\n"); + io_close(local_image_handle); + } + } + return result; +} + + +void arm_io_setup(void) +{ + int io_result; + + io_result = register_io_dev_fip(&fip_dev_con); + assert(io_result == 0); + + io_result = register_io_dev_memmap(&memmap_dev_con); + assert(io_result == 0); + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, + &fip_dev_handle); + assert(io_result == 0); + + io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, + &memmap_dev_handle); + assert(io_result == 0); + + /* Ignore improbable errors in release builds */ + (void)io_result; +} + +void plat_arm_io_setup(void) +{ + arm_io_setup(); +} + +int plat_arm_get_alt_image_source( + unsigned int image_id __unused, + uintptr_t *dev_handle __unused, + uintptr_t *image_spec __unused) +{ + /* By default do not try an alternative */ + return -ENOENT; +} + +/* Return an IO device handle and specification which can be used to access + * an image. Use this to enforce platform load policy */ +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result; + const struct plat_io_policy *policy; + + assert(image_id < ARRAY_SIZE(policies)); + + policy = &policies[image_id]; + result = policy->check(policy->image_spec); + if (result == 0) { + *image_spec = policy->image_spec; + *dev_handle = *(policy->dev_handle); + } else { + VERBOSE("Trying alternative IO\n"); + result = plat_arm_get_alt_image_source(image_id, dev_handle, + image_spec); + } + + return result; +} + +/* + * See if a Firmware Image Package is available, + * by checking if TOC is valid or not. + */ +int arm_io_is_toc_valid(void) +{ + int result; + + result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); + + return (result == 0); +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_pm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_pm.c new file mode 100644 index 0000000..1e756a9 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_pm.c @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Standard ARM platforms are expected to export plat_arm_psci_pm_ops */ +extern const plat_psci_ops_t plat_arm_psci_pm_ops; + +#if ARM_RECOM_STATE_ID_ENC +extern unsigned int arm_pm_idle_states[]; +#endif /* __ARM_RECOM_STATE_ID_ENC__ */ + +#if !ARM_RECOM_STATE_ID_ENC +/******************************************************************************* + * ARM standard platform handler called to check the validity of the power state + * parameter. + ******************************************************************************/ +int arm_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int pstate = psci_get_pstate_type(power_state); + int pwr_lvl = psci_get_pstate_pwrlvl(power_state); + int i; + + assert(req_state); + + if (pwr_lvl > PLAT_MAX_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + /* Sanity check the requested state */ + if (pstate == PSTATE_TYPE_STANDBY) { + /* + * It's possible to enter standby only on power level 0 + * Ignore any other power level. + */ + if (pwr_lvl != ARM_PWR_LVL0) + return PSCI_E_INVALID_PARAMS; + + req_state->pwr_domain_state[ARM_PWR_LVL0] = + ARM_LOCAL_STATE_RET; + } else { + for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++) + req_state->pwr_domain_state[i] = + ARM_LOCAL_STATE_OFF; + } + + /* + * We expect the 'state id' to be zero. + */ + if (psci_get_pstate_id(power_state)) + return PSCI_E_INVALID_PARAMS; + + return PSCI_E_SUCCESS; +} + +#else +/******************************************************************************* + * ARM standard platform handler called to check the validity of the power + * state parameter. The power state parameter has to be a composite power + * state. + ******************************************************************************/ +int arm_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + unsigned int state_id; + int i; + + assert(req_state); + + /* + * Currently we are using a linear search for finding the matching + * entry in the idle power state array. This can be made a binary + * search if the number of entries justify the additional complexity. + */ + for (i = 0; !!arm_pm_idle_states[i]; i++) { + if (power_state == arm_pm_idle_states[i]) + break; + } + + /* Return error if entry not found in the idle state array */ + if (!arm_pm_idle_states[i]) + return PSCI_E_INVALID_PARAMS; + + i = 0; + state_id = psci_get_pstate_id(power_state); + + /* Parse the State ID and populate the state info parameter */ + while (state_id) { + req_state->pwr_domain_state[i++] = state_id & + ARM_LOCAL_PSTATE_MASK; + state_id >>= ARM_LOCAL_PSTATE_WIDTH; + } + + return PSCI_E_SUCCESS; +} +#endif /* __ARM_RECOM_STATE_ID_ENC__ */ + +/******************************************************************************* + * ARM standard platform handler called to check the validity of the non secure + * entrypoint. + ******************************************************************************/ +int arm_validate_ns_entrypoint(uintptr_t entrypoint) +{ + /* + * Check if the non secure entrypoint lies within the non + * secure DRAM. + */ + if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < + (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) + return PSCI_E_SUCCESS; + if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < + (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) + return PSCI_E_SUCCESS; + + return PSCI_E_INVALID_ADDRESS; +} + +/****************************************************************************** + * Helper function to resume the platform from system suspend. Reinitialize + * the system components which are not in the Always ON power domain. + * TODO: Unify the platform setup when waking up from cold boot and system + * resume in arm_bl31_platform_setup(). + *****************************************************************************/ +void arm_system_pwr_domain_resume(void) +{ + console_init(PLAT_ARM_BL31_RUN_UART_BASE, PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE); + + /* Assert system power domain is available on the platform */ + assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); + + /* + * TODO: On GICv3 systems, figure out whether the core that wakes up + * first from system suspend need to initialize the re-distributor + * interface of all the other suspended cores. + */ + plat_arm_gic_init(); + plat_arm_security_setup(); + arm_configure_sys_timer(); +} + +/******************************************************************************* + * Private function to program the mailbox for a cpu before it is released + * from reset. This function assumes that the Trusted mail box base is within + * the ARM_SHARED_RAM region + ******************************************************************************/ +void arm_program_trusted_mailbox(uintptr_t address) +{ + uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE; + + *mailbox = address; + + /* + * Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within + * ARM_SHARED_RAM region. + */ + assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) && + ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \ + (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE))); +} + +/******************************************************************************* + * The ARM Standard platform definition of platform porting API + * `plat_setup_psci_ops`. + ******************************************************************************/ +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + *psci_ops = &plat_arm_psci_pm_ops; + + /* Setup mailbox with entry point. */ + arm_program_trusted_mailbox(sec_entrypoint); + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_topology.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_topology.c new file mode 100644 index 0000000..4430b13 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_topology.c @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/******************************************************************************* + * This function validates an MPIDR by checking whether it falls within the + * acceptable bounds. An error code (-1) is returned if an incorrect mpidr + * is passed. + ******************************************************************************/ +int arm_check_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) + return -1; + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLAT_ARM_CLUSTER_COUNT) + return -1; + + /* Validate cpu_id by checking whether it represents a CPU in + one of the two clusters present on the platform. */ + if (cpu_id >= plat_arm_get_cluster_core_count(mpidr)) + return -1; + + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_tzc400.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_tzc400.c new file mode 100644 index 0000000..3962940 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_tzc400.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak plat_arm_security_setup + + +/******************************************************************************* + * Initialize the TrustZone Controller for ARM standard platforms. + * Configure: + * - Region 0 with no access; + * - Region 1 with secure access only; + * - the remaining DRAM regions access from the given Non-Secure masters. + * + * When booting an EL3 payload, this is simplified: we configure region 0 with + * secure access only and do not enable any other region. + ******************************************************************************/ +void arm_tzc400_setup(void) +{ + INFO("Configuring TrustZone Controller\n"); + + tzc400_init(PLAT_ARM_TZC_BASE); + + /* Disable filters. */ + tzc400_disable_filters(); + +#ifndef EL3_PAYLOAD_BASE + /* Region 0 set to no access by default */ + tzc400_configure_region0(TZC_REGION_S_NONE, 0); + + /* Region 1 set to cover Secure part of DRAM */ + tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 1, + ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, + TZC_REGION_S_RDWR, + 0); + + /* Region 2 set to cover Non-Secure access to 1st DRAM address range. + * Apply the same configuration to given filters in the TZC. */ + tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 2, + ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, + TZC_REGION_S_NONE, + PLAT_ARM_TZC_NS_DEV_ACCESS); + + /* Region 3 set to cover Non-Secure access to 2nd DRAM address range */ + tzc400_configure_region(PLAT_ARM_TZC_FILTERS, 3, + ARM_DRAM2_BASE, ARM_DRAM2_END, + TZC_REGION_S_NONE, + PLAT_ARM_TZC_NS_DEV_ACCESS); +#else + /* Allow secure access only to DRAM for EL3 payloads. */ + tzc400_configure_region0(TZC_REGION_S_RDWR, 0); +#endif /* EL3_PAYLOAD_BASE */ + + /* + * Raise an exception if a NS device tries to access secure memory + * TODO: Add interrupt handling support. + */ + tzc400_set_action(TZC_ACTION_ERR); + + /* Enable filters. */ + tzc400_enable_filters(); +} + +void plat_arm_security_setup(void) +{ + arm_tzc400_setup(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_tzc_dmc500.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_tzc_dmc500.c new file mode 100644 index 0000000..f0ed9a6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/arm_tzc_dmc500.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/******************************************************************************* + * Initialize the DMC500-TrustZone Controller for ARM standard platforms. + * Configure both the interfaces on Region 0 with no access, Region 1 with + * secure access only, and the remaining DRAM regions access from the + * given Non-Secure masters. + * + * When booting an EL3 payload, this is simplified: we configure region 0 with + * secure access only and do not enable any other region. + ******************************************************************************/ +void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data) +{ + assert(plat_driver_data); + + INFO("Configuring DMC-500 TZ Settings\n"); + + tzc_dmc500_driver_init(plat_driver_data); + +#ifndef EL3_PAYLOAD_BASE + /* Region 0 set to no access by default */ + tzc_dmc500_configure_region0(TZC_REGION_S_NONE, 0); + + /* Region 1 set to cover Secure part of DRAM */ + tzc_dmc500_configure_region(1, ARM_AP_TZC_DRAM1_BASE, + ARM_AP_TZC_DRAM1_END, + TZC_REGION_S_RDWR, + 0); + + /* Region 2 set to cover Non-Secure access to 1st DRAM address range.*/ + tzc_dmc500_configure_region(2, + ARM_NS_DRAM1_BASE, + ARM_NS_DRAM1_END, + TZC_REGION_S_NONE, + PLAT_ARM_TZC_NS_DEV_ACCESS); + + /* Region 3 set to cover Non-Secure access to 2nd DRAM address range */ + tzc_dmc500_configure_region(3, + ARM_DRAM2_BASE, + ARM_DRAM2_END, + TZC_REGION_S_NONE, + PLAT_ARM_TZC_NS_DEV_ACCESS); +#else + /* Allow secure access only to DRAM for EL3 payloads */ + tzc_dmc500_configure_region0(TZC_REGION_S_RDWR, 0); +#endif + /* + * Raise an exception if a NS device tries to access secure memory + * TODO: Add interrupt handling support. + */ + tzc_dmc500_set_action(TZC_ACTION_RV_LOWERR); + + /* + * Flush the configuration settings to have an affect. Validate + * flush by checking FILTER_EN is set on region 1 attributes + * register. + */ + tzc_dmc500_config_complete(); + + /* + * Wait for the flush to complete. + * TODO: Have a timeout for this loop + */ + while (tzc_dmc500_verify_complete()) + ; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/sp_min/arm_sp_min.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/sp_min/arm_sp_min.mk new file mode 100644 index 0000000..8a4d598 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/sp_min/arm_sp_min.mk @@ -0,0 +1,37 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# SP MIN source files common to ARM standard platforms +BL32_SOURCES += plat/arm/common/arm_pm.c \ + plat/arm/common/arm_topology.c \ + plat/arm/common/sp_min/arm_sp_min_setup.c \ + plat/common/aarch32/platform_mp_stack.S \ + plat/common/plat_psci_common.c + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/sp_min/arm_sp_min_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/sp_min/arm_sp_min_setup.c new file mode 100644 index 0000000..d48556e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/sp_min/arm_sp_min_setup.c @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define BL32_END (uintptr_t)(&__BL32_END__) + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ +#define BL32_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__) +#define BL32_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__) +#endif + + +static entry_point_info_t bl33_image_ep_info; + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak sp_min_early_platform_setup +#pragma weak sp_min_platform_setup +#pragma weak sp_min_plat_arch_setup + + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for the + * security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) +{ + entry_point_info_t *next_image_info; + + next_image_info = &bl33_image_ep_info; + + /* + * None of the images on the ARM development platforms can have 0x0 + * as the entrypoint + */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +/******************************************************************************* + * Perform early platform setup. + ******************************************************************************/ +void arm_sp_min_early_platform_setup(void *from_bl2, + void *plat_params_from_bl2) +{ + /* Initialize the console to provide early debug support */ + console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE); + +#if RESET_TO_SP_MIN + /* There are no parameters from BL2 if SP_MIN is a reset vector */ + assert(from_bl2 == NULL); + assert(plat_params_from_bl2 == NULL); + + /* Populate entry point information for BL33 */ + SET_PARAM_HEAD(&bl33_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + /* + * Tell SP_MIN where the non-trusted software image + * is located and the entry state information + */ + bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); + bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + +#else /* RESET_TO_SP_MIN */ + + /* + * Check params passed from BL2 should not be NULL, + */ + bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; + assert(params_from_bl2 != NULL); + assert(params_from_bl2->h.type == PARAM_BL_PARAMS); + assert(params_from_bl2->h.version >= VERSION_2); + + bl_params_node_t *bl_params = params_from_bl2->head; + + /* + * Copy BL33 entry point information. + * They are stored in Secure RAM, in BL2's address space. + */ + while (bl_params) { + if (bl_params->image_id == BL33_IMAGE_ID) { + bl33_image_ep_info = *bl_params->ep_info; + break; + } + + bl_params = bl_params->next_params_info; + } + + if (bl33_image_ep_info.pc == 0) + panic(); + +#endif /* RESET_TO_SP_MIN */ + +} + +void sp_min_early_platform_setup(void *from_bl2, + void *plat_params_from_bl2) +{ + arm_sp_min_early_platform_setup(from_bl2, plat_params_from_bl2); + + /* + * Initialize Interconnect for this cluster during cold boot. + * No need for locks as no other CPU is active. + */ + plat_arm_interconnect_init(); + + /* + * Enable Interconnect coherency for the primary CPU's cluster. + * Earlier bootloader stages might already do this (e.g. Trusted + * Firmware's BL1 does it) but we can't assume so. There is no harm in + * executing this code twice anyway. + * Platform specific PSCI code will enable coherency for other + * clusters. + */ + plat_arm_interconnect_enter_coherency(); +} + +/******************************************************************************* + * Perform platform specific setup for SP_MIN + ******************************************************************************/ +void sp_min_platform_setup(void) +{ + /* Initialize the GIC driver, cpu and distributor interfaces */ + plat_arm_gic_driver_init(); + plat_arm_gic_init(); + + /* + * Do initial security configuration to allow DRAM/device access + * (if earlier BL has not already done so). + */ +#if RESET_TO_SP_MIN + plat_arm_security_setup(); +#endif + + /* Enable and initialize the System level generic timer */ + mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, + CNTCR_FCREQ(0) | CNTCR_EN); + + /* Allow access to the System counter timer module */ + arm_configure_sys_timer(); + + /* Initialize power controller before setting up topology */ + plat_arm_pwrc_setup(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this only initializes the MMU + ******************************************************************************/ +void sp_min_plat_arch_setup(void) +{ + + arm_setup_page_tables(BL32_BASE, + (BL32_END - BL32_BASE), + BL_CODE_BASE, + BL_CODE_LIMIT, + BL_RO_DATA_BASE, + BL_RO_DATA_LIMIT +#if USE_COHERENT_MEM + , BL32_COHERENT_RAM_BASE, + BL32_COHERENT_RAM_LIMIT +#endif + ); + + enable_mmu_secure(0); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/tsp/arm_tsp.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/tsp/arm_tsp.mk new file mode 100644 index 0000000..691a2ab --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/tsp/arm_tsp.mk @@ -0,0 +1,34 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +# TSP source files common to ARM standard platforms +BL32_SOURCES += plat/arm/common/arm_topology.c \ + plat/arm/common/tsp/arm_tsp_setup.c \ + plat/common/aarch64/platform_mp_stack.S diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/tsp/arm_tsp_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/tsp/arm_tsp_setup.c new file mode 100644 index 0000000..09029f4 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/common/tsp/arm_tsp_setup.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#define BL32_END (unsigned long)(&__BL32_END__) + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ +#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif + + +/* Weak definitions may be overridden in specific ARM standard platform */ +#pragma weak tsp_early_platform_setup +#pragma weak tsp_platform_setup +#pragma weak tsp_plat_arch_setup + + +/******************************************************************************* + * Initialize the UART + ******************************************************************************/ +void arm_tsp_early_platform_setup(void) +{ + /* + * Initialize a different console than already in use to display + * messages from TSP + */ + console_init(PLAT_ARM_TSP_UART_BASE, PLAT_ARM_TSP_UART_CLK_IN_HZ, + ARM_CONSOLE_BAUDRATE); +} + +void tsp_early_platform_setup(void) +{ + arm_tsp_early_platform_setup(); +} + +/******************************************************************************* + * Perform platform specific setup placeholder + ******************************************************************************/ +void tsp_platform_setup(void) +{ + plat_arm_gic_driver_init(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the MMU + ******************************************************************************/ +void tsp_plat_arch_setup(void) +{ + arm_setup_page_tables(BL32_BASE, + (BL32_END - BL32_BASE), + BL_CODE_BASE, + BL_CODE_LIMIT, + BL_RO_DATA_BASE, + BL_RO_DATA_LIMIT +#if USE_COHERENT_MEM + , BL32_COHERENT_RAM_BASE, + BL32_COHERENT_RAM_LIMIT +#endif + ); + enable_mmu_el1(0); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/aarch64/css_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/aarch64/css_helpers.S new file mode 100644 index 0000000..92b0e81 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/aarch64/css_helpers.S @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include + + .weak plat_secondary_cold_boot_setup + .weak plat_get_my_entrypoint + .globl css_calc_core_pos_swap_cluster + .weak plat_is_my_cpu_primary + + /* --------------------------------------------------------------------- + * void plat_secondary_cold_boot_setup(void); + * + * In the normal boot flow, cold-booting secondary CPUs is not yet + * implemented and they panic. + * + * When booting an EL3 payload, secondary CPUs are placed in a holding + * pen, waiting for their mailbox to be populated. Note that all CPUs + * share the same mailbox ; therefore, populating it will release all + * CPUs from their holding pen. If finer-grained control is needed then + * this should be handled in the code that secondary CPUs jump to. + * --------------------------------------------------------------------- + */ +func plat_secondary_cold_boot_setup +#ifndef EL3_PAYLOAD_BASE + /* TODO: Implement secondary CPU cold boot setup on CSS platforms */ +cb_panic: + b cb_panic +#else + mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE + + /* Wait until the mailbox gets populated */ +poll_mailbox: + ldr x1, [x0] + cbz x1, 1f + br x1 +1: + wfe + b poll_mailbox +#endif /* EL3_PAYLOAD_BASE */ +endfunc plat_secondary_cold_boot_setup + + /* --------------------------------------------------------------------- + * uintptr_t plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between a cold and a warm + * boot. On CSS platforms, this distinction is based on the contents of + * the Trusted Mailbox. It is initialised to zero by the SCP before the + * AP cores are released from reset. Therefore, a zero mailbox means + * it's a cold reset. + * + * This functions returns the contents of the mailbox, i.e.: + * - 0 for a cold boot; + * - the warm boot entrypoint for a warm boot. + * --------------------------------------------------------------------- + */ +func plat_get_my_entrypoint + mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE + ldr x0, [x0] + ret +endfunc plat_get_my_entrypoint + + /* ----------------------------------------------------------- + * unsigned int css_calc_core_pos_swap_cluster(u_register_t mpidr) + * Utility function to calculate the core position by + * swapping the cluster order. This is necessary in order to + * match the format of the boot information passed by the SCP + * and read in plat_is_my_cpu_primary below. + * ----------------------------------------------------------- + */ +func css_calc_core_pos_swap_cluster + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + eor x0, x0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order + add x0, x1, x0, LSR #6 + ret +endfunc css_calc_core_pos_swap_cluster + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu (applicable ony after a cold boot) + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mov x9, x30 + bl plat_my_core_pos + ldr x1, =SCP_BOOT_CFG_ADDR + ldr x1, [x1] + ubfx x1, x1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \ + #PLAT_CSS_PRIMARY_CPU_BIT_WIDTH + cmp x0, x1 + cset w0, eq + ret x9 +endfunc plat_is_my_cpu_primary diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_bl1_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_bl1_setup.c new file mode 100644 index 0000000..2abed3b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_bl1_setup.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +void bl1_platform_setup(void) +{ + arm_bl1_platform_setup(); + /* + * Do ARM CSS SoC security setup. + * BL1 needs to enable normal world access to memory. + */ + soc_css_security_setup(); +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_bl2_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_bl2_setup.c new file mode 100644 index 0000000..11ca342 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_bl2_setup.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "css_scp_bootloader.h" + +/* Weak definition may be overridden in specific CSS based platform */ +#if LOAD_IMAGE_V2 +#pragma weak plat_arm_bl2_handle_scp_bl2 +#else +#pragma weak bl2_plat_handle_scp_bl2 +#endif + +/******************************************************************************* + * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. + * Return 0 on success, -1 otherwise. + ******************************************************************************/ +#if LOAD_IMAGE_V2 +int plat_arm_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) +#else +int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info) +#endif +{ + int ret; + + INFO("BL2: Initiating SCP_BL2 transfer to SCP\n"); + + ret = scp_bootloader_transfer((void *)scp_bl2_image_info->image_base, + scp_bl2_image_info->image_size); + + if (ret == 0) + INFO("BL2: SCP_BL2 transferred to SCP\n"); + else + ERROR("BL2: SCP_BL2 transfer failure\n"); + + return ret; +} + +#ifdef EL3_PAYLOAD_BASE +/* + * We need to override some of the platform functions when booting an EL3 + * payload. + */ + +static unsigned int scp_boot_config; + +void bl2_early_platform_setup(meminfo_t *mem_layout) +{ + arm_bl2_early_platform_setup(mem_layout); + + /* Save SCP Boot config before it gets overwritten by SCP_BL2 loading */ + scp_boot_config = mmio_read_32(SCP_BOOT_CFG_ADDR); + VERBOSE("BL2: Saved SCP Boot config = 0x%x\n", scp_boot_config); +} + +void bl2_platform_setup(void) +{ + arm_bl2_platform_setup(); + + /* + * Before releasing the AP cores out of reset, the SCP writes some data + * at the beginning of the Trusted SRAM. It is is overwritten before + * reaching this function. We need to restore this data, as if the + * target had just come out of reset. This implies: + * - zeroing the first 128 bytes of Trusted SRAM; + * - restoring the SCP boot configuration. + */ + VERBOSE("BL2: Restoring SCP reset data in Trusted SRAM\n"); + memset((void *) ARM_TRUSTED_SRAM_BASE, 0, 128); + mmio_write_32(SCP_BOOT_CFG_ADDR, scp_boot_config); +} +#endif /* EL3_PAYLOAD_BASE */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_bl2u_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_bl2u_setup.c new file mode 100644 index 0000000..878b6fa --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_bl2u_setup.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "css_scp_bootloader.h" + +/* Weak definition may be overridden in specific CSS based platform */ +#pragma weak bl2u_plat_handle_scp_bl2u + +/* Data structure which holds the SCP_BL2U image info for BL2U */ +static image_info_t scp_bl2u_image_info; + +/******************************************************************************* + * BL1 can pass platform dependent information to BL2U in x1. + * In case of ARM CSS platforms x1 contains SCP_BL2U image info. + * In case of ARM FVP platforms x1 is not used. + * In both cases, x0 contains the extents of the memory available to BL2U + ******************************************************************************/ +void bl2u_early_platform_setup(meminfo_t *mem_layout, void *plat_info) +{ + if (!plat_info) + panic(); + + arm_bl2u_early_platform_setup(mem_layout, plat_info); + + scp_bl2u_image_info = *(image_info_t *)plat_info; +} + +/******************************************************************************* + * Transfer SCP_BL2U from Trusted RAM using the SCP Download protocol. + ******************************************************************************/ +int bl2u_plat_handle_scp_bl2u(void) +{ + int ret; + + INFO("BL2U: Initiating SCP_BL2U transfer to SCP\n"); + + ret = scp_bootloader_transfer((void *)scp_bl2u_image_info.image_base, + scp_bl2u_image_info.image_size); + + if (ret == 0) + INFO("BL2U: SCP_BL2U transferred to SCP\n"); + else + ERROR("BL2U: SCP_BL2U transfer failure\n"); + + return ret; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_common.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_common.mk new file mode 100644 index 0000000..65e125e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_common.mk @@ -0,0 +1,82 @@ +# +# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + + +# By default, SCP images are needed by CSS platforms. +CSS_LOAD_SCP_IMAGES ?= 1 + +PLAT_INCLUDES += -Iinclude/plat/arm/css/common \ + -Iinclude/plat/arm/css/common/aarch64 + + +PLAT_BL_COMMON_SOURCES += plat/arm/css/common/aarch64/css_helpers.S + +BL1_SOURCES += plat/arm/css/common/css_bl1_setup.c + +BL2_SOURCES += plat/arm/css/common/css_bl2_setup.c \ + plat/arm/css/common/css_mhu.c \ + plat/arm/css/common/css_scpi.c + +BL2U_SOURCES += plat/arm/css/common/css_bl2u_setup.c \ + plat/arm/css/common/css_mhu.c \ + plat/arm/css/common/css_scpi.c + +BL31_SOURCES += plat/arm/css/common/css_mhu.c \ + plat/arm/css/common/css_pm.c \ + plat/arm/css/common/css_scpi.c \ + plat/arm/css/common/css_topology.c + + +ifneq (${RESET_TO_BL31},0) + $(error "Using BL31 as the reset vector is not supported on CSS platforms. \ + Please set RESET_TO_BL31 to 0.") +endif + +# Process CSS_LOAD_SCP_IMAGES flag +$(eval $(call assert_boolean,CSS_LOAD_SCP_IMAGES)) +$(eval $(call add_define,CSS_LOAD_SCP_IMAGES)) + +ifeq (${CSS_LOAD_SCP_IMAGES},1) + $(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw)) + ifneq (${TRUSTED_BOARD_BOOT},0) + $(eval $(call FWU_FIP_ADD_IMG,SCP_BL2U,--scp-fwu-cfg)) + endif + + BL2U_SOURCES += plat/arm/css/common/css_scp_bootloader.c + BL2_SOURCES += plat/arm/css/common/css_scp_bootloader.c +endif + +# Enable option to detect whether the SCP ROM firmware in use predates version +# 1.7.0 and therefore, is incompatible. +CSS_DETECT_PRE_1_7_0_SCP := 1 + +# Process CSS_DETECT_PRE_1_7_0_SCP flag +$(eval $(call assert_boolean,CSS_DETECT_PRE_1_7_0_SCP)) +$(eval $(call add_define,CSS_DETECT_PRE_1_7_0_SCP)) diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_mhu.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_mhu.c new file mode 100644 index 0000000..265d6c2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_mhu.c @@ -0,0 +1,123 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "css_mhu.h" + +/* SCP MHU secure channel registers */ +#define SCP_INTR_S_STAT 0x200 +#define SCP_INTR_S_SET 0x208 +#define SCP_INTR_S_CLEAR 0x210 + +/* CPU MHU secure channel registers */ +#define CPU_INTR_S_STAT 0x300 +#define CPU_INTR_S_SET 0x308 +#define CPU_INTR_S_CLEAR 0x310 + +ARM_INSTANTIATE_LOCK + +/* Weak definition may be overridden in specific CSS based platform */ +#pragma weak plat_arm_pwrc_setup + + +/* + * Slot 31 is reserved because the MHU hardware uses this register bit to + * indicate a non-secure access attempt. The total number of available slots is + * therefore 31 [30:0]. + */ +#define MHU_MAX_SLOT_ID 30 + +void mhu_secure_message_start(unsigned int slot_id) +{ + assert(slot_id <= MHU_MAX_SLOT_ID); + + arm_lock_get(); + + /* Make sure any previous command has finished */ + while (mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & + (1 << slot_id)) + ; +} + +void mhu_secure_message_send(unsigned int slot_id) +{ + assert(slot_id <= MHU_MAX_SLOT_ID); + assert(!(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) & + (1 << slot_id))); + + /* Send command to SCP */ + mmio_write_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_SET, 1 << slot_id); +} + +uint32_t mhu_secure_message_wait(void) +{ + /* Wait for response from SCP */ + uint32_t response; + while (!(response = mmio_read_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_STAT))) + ; + + return response; +} + +void mhu_secure_message_end(unsigned int slot_id) +{ + assert(slot_id <= MHU_MAX_SLOT_ID); + + /* + * Clear any response we got by writing one in the relevant slot bit to + * the CLEAR register + */ + mmio_write_32(PLAT_CSS_MHU_BASE + SCP_INTR_S_CLEAR, 1 << slot_id); + + arm_lock_release(); +} + +void mhu_secure_init(void) +{ + arm_lock_init(); + + /* + * The STAT register resets to zero. Ensure it is in the expected state, + * as a stale or garbage value would make us think it's a message we've + * already sent. + */ + assert(mmio_read_32(PLAT_CSS_MHU_BASE + CPU_INTR_S_STAT) == 0); +} + +void plat_arm_pwrc_setup(void) +{ + mhu_secure_init(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_mhu.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_mhu.h new file mode 100644 index 0000000..2175cdf --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_mhu.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CSS_MHU_H__ +#define __CSS_MHU_H__ + +#include + +void mhu_secure_message_start(unsigned int slot_id); +void mhu_secure_message_send(unsigned int slot_id); +uint32_t mhu_secure_message_wait(void); +void mhu_secure_message_end(unsigned int slot_id); + +void mhu_secure_init(void); + +#endif /* __CSS_MHU_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_pm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_pm.c new file mode 100644 index 0000000..7607f61 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_pm.c @@ -0,0 +1,354 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "css_scpi.h" + +/* Macros to read the CSS power domain state */ +#define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0] +#define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1] +#define CSS_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > ARM_PWR_LVL1) ?\ + (state)->pwr_domain_state[ARM_PWR_LVL2] : 0) + +/* Allow CSS platforms to override `plat_arm_psci_pm_ops` */ +#pragma weak plat_arm_psci_pm_ops + +#if ARM_RECOM_STATE_ID_ENC +/* + * The table storing the valid idle power states. Ensure that the + * array entries are populated in ascending order of state-id to + * enable us to use binary search during power state validation. + * The table must be terminated by a NULL entry. + */ +const unsigned int arm_pm_idle_states[] = { + /* State-id - 0x001 */ + arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, + ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), + /* State-id - 0x002 */ + arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, + ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), + /* State-id - 0x022 */ + arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, + ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), +#if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1 + /* State-id - 0x222 */ + arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, + ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN), +#endif + 0, +}; +#endif /* __ARM_RECOM_STATE_ID_ENC__ */ + +/* + * All the power management helpers in this file assume at least cluster power + * level is supported. + */ +CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1, + assert_max_pwr_lvl_supported_mismatch); + +/******************************************************************************* + * Handler called when a power domain is about to be turned on. The + * level and mpidr determine the affinity instance. + ******************************************************************************/ +int css_pwr_domain_on(u_register_t mpidr) +{ + /* + * SCP takes care of powering up parent power domains so we + * only need to care about level 0 + */ + scpi_set_css_power_state(mpidr, scpi_power_on, scpi_power_on, + scpi_power_on); + + return PSCI_E_SUCCESS; +} + +static void css_pwr_domain_on_finisher_common( + const psci_power_state_t *target_state) +{ + assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); + + /* + * Perform the common cluster specific operations i.e enable coherency + * if this cluster was off. + */ + if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) + plat_arm_interconnect_enter_coherency(); +} + +/******************************************************************************* + * Handler called when a power level has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. This handler would never be invoked with + * the system power domain uninitialized as either the primary would have taken + * care of it as part of cold boot or the first core awakened from system + * suspend would have already initialized it. + ******************************************************************************/ +void css_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + /* Assert that the system power domain need not be initialized */ + assert(CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_RUN); + + css_pwr_domain_on_finisher_common(target_state); + + /* Program the gic per-cpu distributor or re-distributor interface */ + plat_arm_gic_pcpu_init(); + + /* Enable the gic cpu interface */ + plat_arm_gic_cpuif_enable(); +} + +/******************************************************************************* + * Common function called while turning a cpu off or suspending it. It is called + * from css_off() or css_suspend() when these functions in turn are called for + * power domain at the highest power level which will be powered down. It + * performs the actions common to the OFF and SUSPEND calls. + ******************************************************************************/ +static void css_power_down_common(const psci_power_state_t *target_state) +{ + uint32_t cluster_state = scpi_power_on; + uint32_t system_state = scpi_power_on; + + /* Prevent interrupts from spuriously waking up this cpu */ + plat_arm_gic_cpuif_disable(); + + /* Check if power down at system power domain level is requested */ + if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) + system_state = scpi_power_retention; + + /* Cluster is to be turned off, so disable coherency */ + if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) { + plat_arm_interconnect_exit_coherency(); + cluster_state = scpi_power_off; + } + + /* + * Ask the SCP to power down the appropriate components depending upon + * their state. + */ + scpi_set_css_power_state(read_mpidr_el1(), + scpi_power_off, + cluster_state, + system_state); +} + +/******************************************************************************* + * Handler called when a power domain is about to be turned off. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void css_pwr_domain_off(const psci_power_state_t *target_state) +{ + assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); + css_power_down_common(target_state); +} + +/******************************************************************************* + * Handler called when a power domain is about to be suspended. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void css_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + /* + * CSS currently supports retention only at cpu level. Just return + * as nothing is to be done for retention. + */ + if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) + return; + + assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); + css_power_down_common(target_state); +} + +/******************************************************************************* + * Handler called when a power domain has just been powered on after + * having been suspended earlier. The target_state encodes the low power state + * that each level has woken up from. + * TODO: At the moment we reuse the on finisher and reinitialize the secure + * context. Need to implement a separate suspend finisher. + ******************************************************************************/ +void css_pwr_domain_suspend_finish( + const psci_power_state_t *target_state) +{ + /* Return as nothing is to be done on waking up from retention. */ + if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) + return; + + /* Perform system domain restore if woken up from system suspend */ + if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) + arm_system_pwr_domain_resume(); + else + /* Enable the gic cpu interface */ + plat_arm_gic_cpuif_enable(); + + css_pwr_domain_on_finisher_common(target_state); +} + +/******************************************************************************* + * Handlers to shutdown/reboot the system + ******************************************************************************/ +void __dead2 css_system_off(void) +{ + uint32_t response; + + /* Send the power down request to the SCP */ + response = scpi_sys_power_state(scpi_system_shutdown); + + if (response != SCP_OK) { + ERROR("CSS System Off: SCP error %u.\n", response); + panic(); + } + wfi(); + ERROR("CSS System Off: operation not handled.\n"); + panic(); +} + +void __dead2 css_system_reset(void) +{ + uint32_t response; + + /* Send the system reset request to the SCP */ + response = scpi_sys_power_state(scpi_system_reboot); + + if (response != SCP_OK) { + ERROR("CSS System Reset: SCP error %u.\n", response); + panic(); + } + wfi(); + ERROR("CSS System Reset: operation not handled.\n"); + panic(); +} + +/******************************************************************************* + * Handler called when the CPU power domain is about to enter standby. + ******************************************************************************/ +void css_cpu_standby(plat_local_state_t cpu_state) +{ + unsigned int scr; + + assert(cpu_state == ARM_LOCAL_STATE_RET); + + scr = read_scr_el3(); + /* + * Enable the Non secure interrupt to wake the CPU. + * In GICv3 affinity routing mode, the non secure group1 interrupts use + * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ. + * Enabling both the bits works for both GICv2 mode and GICv3 affinity + * routing mode. + */ + write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); + isb(); + dsb(); + wfi(); + + /* + * Restore SCR to the original value, synchronisation of scr_el3 is + * done by eret while el3_exit to save some execution cycles. + */ + write_scr_el3(scr); +} + +/******************************************************************************* + * Handler called to return the 'req_state' for system suspend. + ******************************************************************************/ +void css_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + unsigned int i; + + /* + * System Suspend is supported only if the system power domain node + * is implemented. + */ + assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); + + for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) + req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; +} + +/******************************************************************************* + * Handler to query CPU/cluster power states from SCP + ******************************************************************************/ +int css_node_hw_state(u_register_t mpidr, unsigned int power_level) +{ + int rc, element; + unsigned int cpu_state, cluster_state; + + /* + * The format of 'power_level' is implementation-defined, but 0 must + * mean a CPU. We also allow 1 to denote the cluster + */ + if (power_level != ARM_PWR_LVL0 && power_level != ARM_PWR_LVL1) + return PSCI_E_INVALID_PARAMS; + + /* Query SCP */ + rc = scpi_get_css_power_state(mpidr, &cpu_state, &cluster_state); + if (rc != 0) + return PSCI_E_INVALID_PARAMS; + + /* Map power states of CPU and cluster to expected PSCI return codes */ + if (power_level == ARM_PWR_LVL0) { + /* + * The CPU state returned by SCP is an 8-bit bit mask + * corresponding to each CPU in the cluster + */ + element = mpidr & MPIDR_AFFLVL_MASK; + return CSS_CPU_PWR_STATE(cpu_state, element) == + CSS_CPU_PWR_STATE_ON ? HW_ON : HW_OFF; + } else { + assert(cluster_state == CSS_CLUSTER_PWR_STATE_ON || + cluster_state == CSS_CLUSTER_PWR_STATE_OFF); + return cluster_state == CSS_CLUSTER_PWR_STATE_ON ? HW_ON : + HW_OFF; + } +} + +/******************************************************************************* + * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard + * platform will take care of registering the handlers with PSCI. + ******************************************************************************/ +const plat_psci_ops_t plat_arm_psci_pm_ops = { + .pwr_domain_on = css_pwr_domain_on, + .pwr_domain_on_finish = css_pwr_domain_on_finish, + .pwr_domain_off = css_pwr_domain_off, + .cpu_standby = css_cpu_standby, + .pwr_domain_suspend = css_pwr_domain_suspend, + .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish, + .system_off = css_system_off, + .system_reset = css_system_reset, + .validate_power_state = arm_validate_power_state, + .validate_ns_entrypoint = arm_validate_ns_entrypoint, + .get_node_hw_state = css_node_hw_state +}; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_scp_bootloader.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_scp_bootloader.c new file mode 100644 index 0000000..d3f671e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_scp_bootloader.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "css_mhu.h" +#include "css_scp_bootloader.h" +#include "css_scpi.h" + +/* ID of the MHU slot used for the BOM protocol */ +#define BOM_MHU_SLOT_ID 0 + +/* Boot commands sent from AP -> SCP */ +#define BOOT_CMD_INFO 0x00 +#define BOOT_CMD_DATA 0x01 + +/* BOM command header */ +typedef struct { + uint32_t id : 8; + uint32_t reserved : 24; +} bom_cmd_t; + +typedef struct { + uint32_t image_size; + uint32_t checksum; +} cmd_info_payload_t; + +/* + * Unlike the SCPI protocol, the boot protocol uses the same memory region + * for both AP -> SCP and SCP -> AP transfers; define the address of this... + */ +#define BOM_SHARED_MEM PLAT_CSS_SCP_COM_SHARED_MEM_BASE +#define BOM_CMD_HEADER ((bom_cmd_t *) BOM_SHARED_MEM) +#define BOM_CMD_PAYLOAD ((void *) (BOM_SHARED_MEM + sizeof(bom_cmd_t))) + +typedef struct { + /* Offset from the base address of the Trusted RAM */ + uint32_t offset; + uint32_t block_size; +} cmd_data_payload_t; + +static void scp_boot_message_start(void) +{ + mhu_secure_message_start(BOM_MHU_SLOT_ID); +} + +static void scp_boot_message_send(size_t payload_size) +{ + /* Ensure that any write to the BOM payload area is seen by SCP before + * we write to the MHU register. If these 2 writes were reordered by + * the CPU then SCP would read stale payload data */ + dmbst(); + + /* Send command to SCP */ + mhu_secure_message_send(BOM_MHU_SLOT_ID); +} + +static uint32_t scp_boot_message_wait(size_t size) +{ + uint32_t mhu_status; + + mhu_status = mhu_secure_message_wait(); + + /* Expect an SCP Boot Protocol message, reject any other protocol */ + if (mhu_status != (1 << BOM_MHU_SLOT_ID)) { + ERROR("MHU: Unexpected protocol (MHU status: 0x%x)\n", + mhu_status); + panic(); + } + + /* Ensure that any read to the BOM payload area is done after reading + * the MHU register. If these 2 reads were reordered then the CPU would + * read invalid payload data */ + dmbld(); + + return *(uint32_t *) BOM_SHARED_MEM; +} + +static void scp_boot_message_end(void) +{ + mhu_secure_message_end(BOM_MHU_SLOT_ID); +} + +int scp_bootloader_transfer(void *image, unsigned int image_size) +{ + uint32_t response; + uint32_t checksum; + cmd_info_payload_t *cmd_info_payload; + cmd_data_payload_t *cmd_data_payload; + + assert((uintptr_t) image == SCP_BL2_BASE); + + if ((image_size == 0) || (image_size % 4 != 0)) { + ERROR("Invalid size for the SCP_BL2 image. Must be a multiple of " + "4 bytes and not zero (current size = 0x%x)\n", + image_size); + return -1; + } + + /* Extract the checksum from the image */ + checksum = *(uint32_t *) image; + image = (char *) image + sizeof(checksum); + image_size -= sizeof(checksum); + + mhu_secure_init(); + + VERBOSE("Send info about the SCP_BL2 image to be transferred to SCP\n"); + + /* + * Send information about the SCP firmware image about to be transferred + * to SCP + */ + scp_boot_message_start(); + + BOM_CMD_HEADER->id = BOOT_CMD_INFO; + cmd_info_payload = BOM_CMD_PAYLOAD; + cmd_info_payload->image_size = image_size; + cmd_info_payload->checksum = checksum; + + scp_boot_message_send(sizeof(*cmd_info_payload)); +#if CSS_DETECT_PRE_1_7_0_SCP + { + const uint32_t deprecated_scp_nack_cmd = 0x404; + uint32_t mhu_status; + + VERBOSE("Detecting SCP version incompatibility\n"); + + mhu_status = mhu_secure_message_wait(); + if (mhu_status == deprecated_scp_nack_cmd) { + ERROR("Detected an incompatible version of the SCP firmware.\n"); + ERROR("Only versions from v1.7.0 onwards are supported.\n"); + ERROR("Please update the SCP firmware.\n"); + return -1; + } + + VERBOSE("SCP version looks OK\n"); + } +#endif /* CSS_DETECT_PRE_1_7_0_SCP */ + response = scp_boot_message_wait(sizeof(response)); + scp_boot_message_end(); + + if (response != 0) { + ERROR("SCP BOOT_CMD_INFO returned error %u\n", response); + return -1; + } + + VERBOSE("Transferring SCP_BL2 image to SCP\n"); + + /* Transfer SCP_BL2 image to SCP */ + scp_boot_message_start(); + + BOM_CMD_HEADER->id = BOOT_CMD_DATA; + cmd_data_payload = BOM_CMD_PAYLOAD; + cmd_data_payload->offset = (uintptr_t) image - ARM_TRUSTED_SRAM_BASE; + cmd_data_payload->block_size = image_size; + + scp_boot_message_send(sizeof(*cmd_data_payload)); + response = scp_boot_message_wait(sizeof(response)); + scp_boot_message_end(); + + if (response != 0) { + ERROR("SCP BOOT_CMD_DATA returned error %u\n", response); + return -1; + } + + VERBOSE("Waiting for SCP to signal it is ready to go on\n"); + + /* Wait for SCP to signal it's ready */ + return scpi_wait_ready(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_scp_bootloader.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_scp_bootloader.h new file mode 100644 index 0000000..07b8972 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_scp_bootloader.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CSS_SCP_BOOTLOADER_H__ +#define __CSS_SCP_BOOTLOADER_H__ + +int scp_bootloader_transfer(void *image, unsigned int image_size); + +#endif /* __CSS_SCP_BOOTLOADER_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_scpi.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_scpi.c new file mode 100644 index 0000000..90a8939 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_scpi.c @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "css_mhu.h" +#include "css_scpi.h" + +#define SCPI_SHARED_MEM_SCP_TO_AP PLAT_CSS_SCP_COM_SHARED_MEM_BASE +#define SCPI_SHARED_MEM_AP_TO_SCP (PLAT_CSS_SCP_COM_SHARED_MEM_BASE \ + + 0x100) + +/* Header and payload addresses for commands from AP to SCP */ +#define SCPI_CMD_HEADER_AP_TO_SCP \ + ((scpi_cmd_t *) SCPI_SHARED_MEM_AP_TO_SCP) +#define SCPI_CMD_PAYLOAD_AP_TO_SCP \ + ((void *) (SCPI_SHARED_MEM_AP_TO_SCP + sizeof(scpi_cmd_t))) + +/* Header and payload addresses for responses from SCP to AP */ +#define SCPI_RES_HEADER_SCP_TO_AP \ + ((scpi_cmd_t *) SCPI_SHARED_MEM_SCP_TO_AP) +#define SCPI_RES_PAYLOAD_SCP_TO_AP \ + ((void *) (SCPI_SHARED_MEM_SCP_TO_AP + sizeof(scpi_cmd_t))) + +/* ID of the MHU slot used for the SCPI protocol */ +#define SCPI_MHU_SLOT_ID 0 + +static void scpi_secure_message_start(void) +{ + mhu_secure_message_start(SCPI_MHU_SLOT_ID); +} + +static void scpi_secure_message_send(size_t payload_size) +{ + /* Ensure that any write to the SCPI payload area is seen by SCP before + * we write to the MHU register. If these 2 writes were reordered by + * the CPU then SCP would read stale payload data */ + dmbst(); + + mhu_secure_message_send(SCPI_MHU_SLOT_ID); +} + +static void scpi_secure_message_receive(scpi_cmd_t *cmd) +{ + uint32_t mhu_status; + + assert(cmd != NULL); + + mhu_status = mhu_secure_message_wait(); + + /* Expect an SCPI message, reject any other protocol */ + if (mhu_status != (1 << SCPI_MHU_SLOT_ID)) { + ERROR("MHU: Unexpected protocol (MHU status: 0x%x)\n", + mhu_status); + panic(); + } + + /* Ensure that any read to the SCPI payload area is done after reading + * the MHU register. If these 2 reads were reordered then the CPU would + * read invalid payload data */ + dmbld(); + + memcpy(cmd, (void *) SCPI_SHARED_MEM_SCP_TO_AP, sizeof(*cmd)); +} + +static void scpi_secure_message_end(void) +{ + mhu_secure_message_end(SCPI_MHU_SLOT_ID); +} + +int scpi_wait_ready(void) +{ + scpi_cmd_t scpi_cmd; + + VERBOSE("Waiting for SCP_READY command...\n"); + + /* Get a message from the SCP */ + scpi_secure_message_start(); + scpi_secure_message_receive(&scpi_cmd); + scpi_secure_message_end(); + + /* We are expecting 'SCP Ready', produce correct error if it's not */ + scpi_status_t status = SCP_OK; + if (scpi_cmd.id != SCPI_CMD_SCP_READY) { + ERROR("Unexpected SCP command: expected command #%u, got command #%u\n", + SCPI_CMD_SCP_READY, scpi_cmd.id); + status = SCP_E_SUPPORT; + } else if (scpi_cmd.size != 0) { + ERROR("SCP_READY command has incorrect size: expected 0, got %u\n", + scpi_cmd.size); + status = SCP_E_SIZE; + } + + VERBOSE("Sending response for SCP_READY command\n"); + + /* + * Send our response back to SCP. + * We are using the same SCPI header, just update the status field. + */ + scpi_cmd.status = status; + scpi_secure_message_start(); + memcpy((void *) SCPI_SHARED_MEM_AP_TO_SCP, &scpi_cmd, sizeof(scpi_cmd)); + scpi_secure_message_send(0); + scpi_secure_message_end(); + + return status == SCP_OK ? 0 : -1; +} + +void scpi_set_css_power_state(unsigned mpidr, scpi_power_state_t cpu_state, + scpi_power_state_t cluster_state, scpi_power_state_t css_state) +{ + scpi_cmd_t *cmd; + uint32_t state = 0; + uint32_t *payload_addr; + + state |= mpidr & 0x0f; /* CPU ID */ + state |= (mpidr & 0xf00) >> 4; /* Cluster ID */ + state |= cpu_state << 8; + state |= cluster_state << 12; + state |= css_state << 16; + + scpi_secure_message_start(); + + /* Populate the command header */ + cmd = SCPI_CMD_HEADER_AP_TO_SCP; + cmd->id = SCPI_CMD_SET_CSS_POWER_STATE; + cmd->set = SCPI_SET_NORMAL; + cmd->sender = 0; + cmd->size = sizeof(state); + /* Populate the command payload */ + payload_addr = SCPI_CMD_PAYLOAD_AP_TO_SCP; + *payload_addr = state; + scpi_secure_message_send(sizeof(state)); + /* + * SCP does not reply to this command in order to avoid MHU interrupts + * from the sender, which could interfere with its power state request. + */ + + scpi_secure_message_end(); +} + +/* + * Query and obtain CSS power state from SCP. + * + * In response to the query, SCP returns power states of all CPUs in all + * clusters of the system. The returned response is then filtered based on the + * supplied MPIDR. Power states of requested cluster and CPUs within are updated + * via. supplied non-NULL pointer arguments. + * + * Returns 0 on success, or -1 on errors. + */ +int scpi_get_css_power_state(unsigned int mpidr, unsigned int *cpu_state_p, + unsigned int *cluster_state_p) +{ + scpi_cmd_t *cmd; + scpi_cmd_t response; + int power_state, cpu, cluster, rc = -1; + + /* + * Extract CPU and cluster membership of the given MPIDR. SCPI caters + * for only up to 0xf clusters, and 8 CPUs per cluster + */ + cpu = mpidr & MPIDR_AFFLVL_MASK; + cluster = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + if (cpu >= 8 || cluster >= 0xf) + return -1; + + scpi_secure_message_start(); + + /* Populate request headers */ + cmd = memset(SCPI_CMD_HEADER_AP_TO_SCP, 0, sizeof(*cmd)); + cmd->id = SCPI_CMD_GET_CSS_POWER_STATE; + + /* + * Send message and wait for SCP's response + */ + scpi_secure_message_send(0); + scpi_secure_message_receive(&response); + + if (response.status != SCP_OK) + goto exit; + + /* Validate SCP response */ + if (!CHECK_RESPONSE(response, cluster)) + goto exit; + + /* Extract power states for required cluster */ + power_state = *(((uint16_t *) SCPI_RES_PAYLOAD_SCP_TO_AP) + cluster); + if (CLUSTER_ID(power_state) != cluster) + goto exit; + + /* Update power state via. pointers */ + if (cluster_state_p) + *cluster_state_p = CLUSTER_POWER_STATE(power_state); + if (cpu_state_p) + *cpu_state_p = CPU_POWER_STATE(power_state); + rc = 0; + +exit: + scpi_secure_message_end(); + return rc; +} + +uint32_t scpi_sys_power_state(scpi_system_state_t system_state) +{ + scpi_cmd_t *cmd; + uint8_t *payload_addr; + scpi_cmd_t response; + + scpi_secure_message_start(); + + /* Populate the command header */ + cmd = SCPI_CMD_HEADER_AP_TO_SCP; + cmd->id = SCPI_CMD_SYS_POWER_STATE; + cmd->set = 0; + cmd->sender = 0; + cmd->size = sizeof(*payload_addr); + /* Populate the command payload */ + payload_addr = SCPI_CMD_PAYLOAD_AP_TO_SCP; + *payload_addr = system_state & 0xff; + scpi_secure_message_send(sizeof(*payload_addr)); + + scpi_secure_message_receive(&response); + + scpi_secure_message_end(); + + return response.status; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_scpi.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_scpi.h new file mode 100644 index 0000000..1fb55e4 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_scpi.h @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CSS_SCPI_H__ +#define __CSS_SCPI_H__ + +#include +#include + +/* + * An SCPI command consists of a header and a payload. + * The following structure describes the header. It is 64-bit long. + */ +typedef struct { + /* Command ID */ + uint32_t id : 7; + /* Set ID. Identifies whether this is a standard or extended command. */ + uint32_t set : 1; + /* Sender ID to match a reply. The value is sender specific. */ + uint32_t sender : 8; + /* Size of the payload in bytes (0 - 511) */ + uint32_t size : 9; + uint32_t reserved : 7; + /* + * Status indicating the success of a command. + * See the enum below. + */ + uint32_t status; +} scpi_cmd_t; + +typedef enum { + SCPI_SET_NORMAL = 0, /* Normal SCPI commands */ + SCPI_SET_EXTENDED /* Extended SCPI commands */ +} scpi_set_t; + +enum { + SCP_OK = 0, /* Success */ + SCP_E_PARAM, /* Invalid parameter(s) */ + SCP_E_ALIGN, /* Invalid alignment */ + SCP_E_SIZE, /* Invalid size */ + SCP_E_HANDLER, /* Invalid handler or callback */ + SCP_E_ACCESS, /* Invalid access or permission denied */ + SCP_E_RANGE, /* Value out of range */ + SCP_E_TIMEOUT, /* Time out has ocurred */ + SCP_E_NOMEM, /* Invalid memory area or pointer */ + SCP_E_PWRSTATE, /* Invalid power state */ + SCP_E_SUPPORT, /* Feature not supported or disabled */ + SCPI_E_DEVICE, /* Device error */ + SCPI_E_BUSY, /* Device is busy */ +}; + +typedef uint32_t scpi_status_t; + +typedef enum { + SCPI_CMD_SCP_READY = 0x01, + SCPI_CMD_SET_CSS_POWER_STATE = 0x03, + SCPI_CMD_GET_CSS_POWER_STATE = 0x04, + SCPI_CMD_SYS_POWER_STATE = 0x05 +} scpi_command_t; + +/* + * Macros to parse SCP response to GET_CSS_POWER_STATE command + * + * [3:0] : cluster ID + * [7:4] : cluster state: 0 = on; 3 = off; rest are reserved + * [15:8]: on/off state for individual CPUs in the cluster + * + * Payload is in little-endian + */ +#define CLUSTER_ID(_resp) ((_resp) & 0xf) +#define CLUSTER_POWER_STATE(_resp) (((_resp) >> 4) & 0xf) + +/* Result is a bit mask of CPU on/off states in the cluster */ +#define CPU_POWER_STATE(_resp) (((_resp) >> 8) & 0xff) + +/* + * For GET_CSS_POWER_STATE, SCP returns the power states of every cluster. The + * size of response depends on the number of clusters in the system. The + * SCP-to-AP payload contains 2 bytes per cluster. Make sure the response is + * large enough to contain power states of a given cluster + */ +#define CHECK_RESPONSE(_resp, _clus) \ + (_resp.size >= (((_clus) + 1) * 2)) + +typedef enum { + scpi_power_on = 0, + scpi_power_retention = 1, + scpi_power_off = 3, +} scpi_power_state_t; + +typedef enum { + scpi_system_shutdown = 0, + scpi_system_reboot = 1, + scpi_system_reset = 2 +} scpi_system_state_t; + +extern int scpi_wait_ready(void); +extern void scpi_set_css_power_state(unsigned mpidr, + scpi_power_state_t cpu_state, + scpi_power_state_t cluster_state, + scpi_power_state_t css_state); +int scpi_get_css_power_state(unsigned int mpidr, unsigned int *cpu_state_p, + unsigned int *cluster_state_p); +uint32_t scpi_sys_power_state(scpi_system_state_t system_state); + + +#endif /* __CSS_SCPI_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_topology.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_topology.c new file mode 100644 index 0000000..d5f0275 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/css/common/css_topology.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/****************************************************************************** + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is + * returned in case the MPIDR is invalid. + *****************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + if (arm_check_mpidr(mpidr) == 0) + return plat_arm_calc_core_pos(mpidr); + + return -1; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/soc/common/soc_css.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/soc/common/soc_css.mk new file mode 100644 index 0000000..7ae8fdb --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/soc/common/soc_css.mk @@ -0,0 +1,41 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +PLAT_INCLUDES += -Iinclude/plat/arm/soc/common/ + +#PLAT_BL_COMMON_SOURCES += + +BL1_SOURCES += plat/arm/soc/common/soc_css_security.c + +BL2_SOURCES += plat/arm/soc/common/soc_css_security.c + +BL2U_SOURCES += plat/arm/soc/common/soc_css_security.c + +BL31_SOURCES += plat/arm/soc/common/soc_css_security.c diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/soc/common/soc_css_security.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/soc/common/soc_css_security.c new file mode 100644 index 0000000..37fd37c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/arm/soc/common/soc_css_security.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +void soc_css_init_nic400(void) +{ + /* + * NIC-400 Access Control Initialization + * + * Define access privileges by setting each corresponding bit to: + * 0 = Secure access only + * 1 = Non-secure access allowed + */ + + /* + * Allow non-secure access to some SOC regions, excluding UART1, which + * remains secure. + * Note: This is the NIC-400 device on the SOC + */ + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_EHCI), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_TLX_MASTER), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_USB_OHCI), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_PL354_SMC), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_APB4_BRIDGE), ~0); + mmio_write_32(SOC_CSS_NIC400_BASE + + NIC400_ADDR_CTRL_SECURITY_REG(SOC_CSS_NIC400_BOOTSEC_BRIDGE), + ~SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1); + +} + + +#define PCIE_SECURE_REG 0x3000 +/* Mask uses REG and MEM access bits */ +#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) + +void soc_css_init_pcie(void) +{ +#if !PLAT_juno + /* + * Do not initialize PCIe in emulator environment. + * Platform ID register not supported on Juno + */ + if (BOARD_CSS_GET_PLAT_TYPE(BOARD_CSS_PLAT_ID_REG_ADDR) == + BOARD_CSS_PLAT_TYPE_EMULATOR) + return; +#endif /* PLAT_juno */ + + /* + * PCIE Root Complex Security settings to enable non-secure + * access to config registers. + */ + mmio_write_32(SOC_CSS_PCIE_CONTROL_BASE + PCIE_SECURE_REG, + PCIE_SEC_ACCESS_MASK); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch32/plat_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch32/plat_common.c new file mode 100644 index 0000000..a5b9535 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch32/plat_common.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/* + * The following platform setup functions are weakly defined. They + * provide typical implementations that may be re-used by multiple + * platforms but may also be overridden by a platform if required. + */ +#pragma weak bl32_plat_enable_mmu + +void bl32_plat_enable_mmu(uint32_t flags) +{ + enable_mmu_secure(flags); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch32/platform_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch32/platform_helpers.S new file mode 100644 index 0000000..069d96d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch32/platform_helpers.S @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + + .weak plat_my_core_pos + .weak plat_reset_handler + .weak plat_disable_acp + .weak platform_mem_init + .weak plat_panic_handler + + /* ----------------------------------------------------- + * int plat_my_core_pos(void); + * With this function: CorePos = (ClusterId * 4) + + * CoreId + * ----------------------------------------------------- + */ +func plat_my_core_pos + ldcopr r0, MPIDR + and r1, r0, #MPIDR_CPU_MASK + and r0, r0, #MPIDR_CLUSTER_MASK + add r0, r1, r0, LSR #6 + bx lr +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ +func plat_reset_handler + bx lr +endfunc plat_reset_handler + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ +func plat_disable_acp + bx lr +endfunc plat_disable_acp + + /* --------------------------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * --------------------------------------------------------------------- + */ +func platform_mem_init + bx lr +endfunc platform_mem_init + + /* ----------------------------------------------------- + * void plat_panic_handler(void) __dead2; + * Endless loop by default. + * ----------------------------------------------------- + */ +func plat_panic_handler + b plat_panic_handler +endfunc plat_panic_handler diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch32/platform_mp_stack.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch32/platform_mp_stack.S new file mode 100644 index 0000000..a015436 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch32/platform_mp_stack.S @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .globl plat_get_my_stack + .globl plat_set_my_stack + + /* ----------------------------------------------------- + * uintptr_t plat_get_my_stack (u_register_t mpidr) + * + * For a given CPU, this function returns the stack + * pointer for a stack allocated in device memory. + * ----------------------------------------------------- + */ +func plat_get_my_stack + mov r3, lr + get_my_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE + bx r3 +endfunc plat_get_my_stack + + /* ----------------------------------------------------- + * void plat_set_my_stack () + * + * For the current CPU, this function sets the stack + * pointer to a stack allocated in normal memory. + * ----------------------------------------------------- + */ +func plat_set_my_stack + mov r3, lr + get_my_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE + mov sp, r0 + bx r3 +endfunc plat_set_my_stack + + /* ----------------------------------------------------- + * Per-cpu stacks in normal memory. Each cpu gets a + * stack of PLATFORM_STACK_SIZE bytes. + * ----------------------------------------------------- + */ +declare_stack platform_normal_stacks, tzfw_normal_stacks, \ + PLATFORM_STACK_SIZE, PLATFORM_CORE_COUNT diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch32/platform_up_stack.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch32/platform_up_stack.S new file mode 100644 index 0000000..8275aec --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch32/platform_up_stack.S @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .globl plat_get_my_stack + .globl plat_set_my_stack + + /* ----------------------------------------------------- + * unsigned long plat_get_my_stack () + * + * For cold-boot BL images, only the primary CPU needs + * a stack. This function returns the stack pointer for + * a stack allocated in normal memory. + * ----------------------------------------------------- + */ +func plat_get_my_stack + get_up_stack platform_normal_stacks, PLATFORM_STACK_SIZE + bx lr +endfunc plat_get_my_stack + + /* ----------------------------------------------------- + * void plat_set_my_stack () + * + * For cold-boot BL images, only the primary CPU needs + * a stack. This function sets the stack pointer to a + * stack allocated in normal memory. + * ----------------------------------------------------- + */ +func plat_set_my_stack + get_up_stack platform_normal_stacks, PLATFORM_STACK_SIZE + mov sp, r0 + bx lr +endfunc plat_set_my_stack + + /* ----------------------------------------------------- + * Per-cpu stacks in normal memory. Each cpu gets a + * stack of PLATFORM_STACK_SIZE bytes. + * ----------------------------------------------------- + */ +declare_stack platform_normal_stacks, tzfw_normal_stacks, \ + PLATFORM_STACK_SIZE, 1, CACHE_WRITEBACK_GRANULE diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/plat_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/plat_common.c new file mode 100644 index 0000000..4322341 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/plat_common.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include + +/* + * The following platform setup functions are weakly defined. They + * provide typical implementations that may be re-used by multiple + * platforms but may also be overridden by a platform if required. + */ +#pragma weak bl31_plat_enable_mmu +#pragma weak bl32_plat_enable_mmu +#pragma weak bl31_plat_runtime_setup +#if !ERROR_DEPRECATED +#pragma weak plat_get_syscnt_freq2 +#endif /* ERROR_DEPRECATED */ + +void bl31_plat_enable_mmu(uint32_t flags) +{ + enable_mmu_el3(flags); +} + +void bl32_plat_enable_mmu(uint32_t flags) +{ + enable_mmu_el1(flags); +} + +void bl31_plat_runtime_setup(void) +{ + /* + * Finish the use of console driver in BL31 so that any runtime logs + * from BL31 will be suppressed. + */ + console_uninit(); +} + +#if !ENABLE_PLAT_COMPAT +/* + * Helper function for platform_get_pos() when platform compatibility is + * disabled. This is to enable SPDs using the older platform API to continue + * to work. + */ +unsigned int platform_core_pos_helper(unsigned long mpidr) +{ + int idx = plat_core_pos_by_mpidr(mpidr); + assert(idx >= 0); + return idx; +} +#endif + + +#if !ERROR_DEPRECATED +unsigned int plat_get_syscnt_freq2(void) +{ + unsigned long long freq = plat_get_syscnt_freq(); + + assert(freq >> 32 == 0); + + return (unsigned int)freq; +} +#endif /* ERROR_DEPRECATED */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/plat_psci_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/plat_psci_common.c new file mode 100644 index 0000000..804da93 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/plat_psci_common.c @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#if !ERROR_DEPRECATED +#include "../plat_psci_common.c" +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/platform_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/platform_helpers.S new file mode 100644 index 0000000..a134ded --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/platform_helpers.S @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .weak plat_report_exception + .weak plat_crash_console_init + .weak plat_crash_console_putc + .weak plat_reset_handler + .weak plat_disable_acp + .weak bl1_plat_prepare_exit + .weak plat_error_handler + .weak plat_panic_handler + +#if !ENABLE_PLAT_COMPAT + .globl platform_get_core_pos + +#define MPIDR_RES_BIT_MASK 0xff000000 + + /* ------------------------------------------------------------------ + * int platform_get_core_pos(int mpidr) + * Returns the CPU index of the CPU specified by mpidr. This is + * defined when platform compatibility is disabled to enable Trusted + * Firmware components like SPD using the old platform API to work. + * This API is deprecated and it assumes that the mpidr specified is + * that of a valid and present CPU. Instead, plat_my_core_pos() + * should be used for CPU index of the current CPU and + * plat_core_pos_by_mpidr() should be used for CPU index of a + * CPU specified by its mpidr. + * ------------------------------------------------------------------ + */ +func_deprecated platform_get_core_pos + bic x0, x0, #MPIDR_RES_BIT_MASK + mrs x1, mpidr_el1 + bic x1, x1, #MPIDR_RES_BIT_MASK + cmp x0, x1 + beq plat_my_core_pos + b platform_core_pos_helper +endfunc_deprecated platform_get_core_pos +#endif + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ +func plat_report_exception + ret +endfunc plat_report_exception + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ +func plat_crash_console_init + mov x0, #0 + ret +endfunc plat_crash_console_init + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. + * ----------------------------------------------------- + */ +func plat_crash_console_putc + ret +endfunc plat_crash_console_putc + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. This function should preserve x10. + * ----------------------------------------------------- + */ +func plat_reset_handler + ret +endfunc plat_reset_handler + + /* ----------------------------------------------------- + * Placeholder function which should be redefined by + * each platform. This function is allowed to use + * registers x0 - x17. + * ----------------------------------------------------- + */ +func plat_disable_acp + ret +endfunc plat_disable_acp + + /* ----------------------------------------------------- + * void bl1_plat_prepare_exit(entry_point_info_t *ep_info); + * Called before exiting BL1. Default: do nothing + * ----------------------------------------------------- + */ +func bl1_plat_prepare_exit + ret +endfunc bl1_plat_prepare_exit + + /* ----------------------------------------------------- + * void plat_error_handler(int err) __dead2; + * Endless loop by default. + * ----------------------------------------------------- + */ +func plat_error_handler + wfi + b plat_error_handler +endfunc plat_error_handler + + /* ----------------------------------------------------- + * void plat_panic_handler(void) __dead2; + * Endless loop by default. + * ----------------------------------------------------- + */ +func plat_panic_handler + wfi + b plat_panic_handler +endfunc plat_panic_handler diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/platform_mp_stack.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/platform_mp_stack.S new file mode 100644 index 0000000..e3063d1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/platform_mp_stack.S @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + .local platform_normal_stacks +#if ENABLE_PLAT_COMPAT + .globl plat_get_my_stack + .globl plat_set_my_stack + .weak platform_get_stack + .weak platform_set_stack +#else + .weak plat_get_my_stack + .weak plat_set_my_stack + .globl platform_get_stack + .globl platform_set_stack +#endif /* __ENABLE_PLAT_COMPAT__ */ + +#if ENABLE_PLAT_COMPAT + /* --------------------------------------------------------------------- + * When the compatility layer is enabled, the new platform APIs + * viz plat_get_my_stack() and plat_set_my_stack() need to be + * defined using the previous APIs platform_get_stack() and + * platform_set_stack(). Also we need to provide weak definitions + * of platform_get_stack() and platform_set_stack() for the platforms + * to reuse. + * -------------------------------------------------------------------- + */ + + /* ----------------------------------------------------- + * unsigned long plat_get_my_stack () + * + * For the current CPU, this function returns the stack + * pointer for a stack allocated in device memory. + * ----------------------------------------------------- + */ +func plat_get_my_stack + mrs x0, mpidr_el1 + b platform_get_stack +endfunc plat_get_my_stack + + /* ----------------------------------------------------- + * void plat_set_my_stack () + * + * For the current CPU, this function sets the stack + * pointer to a stack allocated in normal memory. + * ----------------------------------------------------- + */ +func plat_set_my_stack + mrs x0, mpidr_el1 + b platform_set_stack +endfunc plat_set_my_stack + + /* ----------------------------------------------------- + * unsigned long platform_get_stack (unsigned long mpidr) + * + * For a given CPU, this function returns the stack + * pointer for a stack allocated in device memory. + * ----------------------------------------------------- + */ +func platform_get_stack + mov x10, x30 // lr + get_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE + ret x10 +endfunc platform_get_stack + + /* ----------------------------------------------------- + * void platform_set_stack (unsigned long mpidr) + * + * For a given CPU, this function sets the stack pointer + * to a stack allocated in normal memory. + * ----------------------------------------------------- + */ +func platform_set_stack + mov x9, x30 // lr + bl platform_get_stack + mov sp, x0 + ret x9 +endfunc platform_set_stack + +#else + /* --------------------------------------------------------------------- + * When the compatility layer is disabled, the new platform APIs + * viz plat_get_my_stack() and plat_set_my_stack() are + * supported by the platform and the previous APIs platform_get_stack() + * and platform_set_stack() are defined in terms of new APIs making use + * of the fact that they are only ever invoked for the current CPU. + * This is to enable components of Trusted Firmware like SPDs using the + * old platform APIs to continue to work. + * -------------------------------------------------------------------- + */ + + /* ------------------------------------------------------- + * unsigned long platform_get_stack (unsigned long mpidr) + * + * For the current CPU, this function returns the stack + * pointer for a stack allocated in device memory. The + * 'mpidr' should correspond to that of the current CPU. + * This function is deprecated and plat_get_my_stack() + * should be used instead. + * ------------------------------------------------------- + */ +func_deprecated platform_get_stack +#if ASM_ASSERTION + mrs x1, mpidr_el1 + cmp x0, x1 + ASM_ASSERT(eq) +#endif + b plat_get_my_stack +endfunc_deprecated platform_get_stack + + /* ----------------------------------------------------- + * void platform_set_stack (unsigned long mpidr) + * + * For the current CPU, this function sets the stack pointer + * to a stack allocated in normal memory. The + * 'mpidr' should correspond to that of the current CPU. + * This function is deprecated and plat_get_my_stack() + * should be used instead. + * ----------------------------------------------------- + */ +func_deprecated platform_set_stack +#if ASM_ASSERTION + mrs x1, mpidr_el1 + cmp x0, x1 + ASM_ASSERT(eq) +#endif + b plat_set_my_stack +endfunc_deprecated platform_set_stack + + /* ----------------------------------------------------- + * uintptr_t plat_get_my_stack () + * + * For the current CPU, this function returns the stack + * pointer for a stack allocated in device memory. + * ----------------------------------------------------- + */ +func plat_get_my_stack + mov x10, x30 // lr + get_my_mp_stack platform_normal_stacks, PLATFORM_STACK_SIZE + ret x10 +endfunc plat_get_my_stack + + /* ----------------------------------------------------- + * void plat_set_my_stack () + * + * For the current CPU, this function sets the stack + * pointer to a stack allocated in normal memory. + * ----------------------------------------------------- + */ +func plat_set_my_stack + mov x9, x30 // lr + bl plat_get_my_stack + mov sp, x0 + ret x9 +endfunc plat_set_my_stack + +#endif /*__ENABLE_PLAT_COMPAT__*/ + + /* ----------------------------------------------------- + * Per-cpu stacks in normal memory. Each cpu gets a + * stack of PLATFORM_STACK_SIZE bytes. + * ----------------------------------------------------- + */ +declare_stack platform_normal_stacks, tzfw_normal_stacks, \ + PLATFORM_STACK_SIZE, PLATFORM_CORE_COUNT, \ + CACHE_WRITEBACK_GRANULE diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/platform_up_stack.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/platform_up_stack.S new file mode 100644 index 0000000..5b82630 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/aarch64/platform_up_stack.S @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + + .local platform_normal_stacks + .globl plat_set_my_stack + .globl plat_get_my_stack + .globl platform_set_stack + .globl platform_get_stack + + /* ----------------------------------------------------- + * uintptr_t plat_get_my_stack () + * + * For cold-boot BL images, only the primary CPU needs a + * stack. This function returns the stack pointer for a + * stack allocated in device memory. + * ----------------------------------------------------- + */ +func plat_get_my_stack + get_up_stack platform_normal_stacks, PLATFORM_STACK_SIZE + ret +endfunc plat_get_my_stack + + /* ----------------------------------------------------- + * void plat_set_my_stack () + * + * For cold-boot BL images, only the primary CPU needs a + * stack. This function sets the stack pointer to a stack + * allocated in normal memory. + * ----------------------------------------------------- + */ +func plat_set_my_stack + get_up_stack platform_normal_stacks, PLATFORM_STACK_SIZE + mov sp, x0 + ret +endfunc plat_set_my_stack + + /* ----------------------------------------------------- + * unsigned long platform_get_stack () + * + * For cold-boot BL images, only the primary CPU needs a + * stack. This function returns the stack pointer for a + * stack allocated in device memory. This function + * is deprecated. + * ----------------------------------------------------- + */ +func_deprecated platform_get_stack + b plat_get_my_stack +endfunc_deprecated platform_get_stack + + /* ----------------------------------------------------- + * void platform_set_stack () + * + * For cold-boot BL images, only the primary CPU needs a + * stack. This function sets the stack pointer to a stack + * allocated in normal memory.This function is + * deprecated. + * ----------------------------------------------------- + */ +func_deprecated platform_set_stack + b plat_set_my_stack +endfunc_deprecated platform_set_stack + + /* ----------------------------------------------------- + * Single cpu stack in normal memory. + * Used for C code during boot, PLATFORM_STACK_SIZE bytes + * are allocated + * ----------------------------------------------------- + */ +declare_stack platform_normal_stacks, tzfw_normal_stacks, \ + PLATFORM_STACK_SIZE, 1, CACHE_WRITEBACK_GRANULE diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_bl1_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_bl1_common.c new file mode 100644 index 0000000..e637aaf --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_bl1_common.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* + * The following platform functions are weakly defined. They + * are default implementations that allow BL1 to compile in + * absence of real definitions. The Platforms may override + * with more complex definitions. + */ +#pragma weak bl1_plat_get_next_image_id +#pragma weak bl1_plat_set_ep_info +#pragma weak bl1_plat_get_image_desc +#pragma weak bl1_plat_fwu_done + + +unsigned int bl1_plat_get_next_image_id(void) +{ + /* BL2 load will be done by default. */ + return BL2_IMAGE_ID; +} + +void bl1_plat_set_ep_info(unsigned int image_id, + entry_point_info_t *ep_info) +{ + +} + +/* + * Following is the default definition that always + * returns BL2 image details. + */ +image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) +{ + static image_desc_t bl2_img_desc = BL2_IMAGE_DESC; + return &bl2_img_desc; +} + +__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved) +{ + while (1) + wfi(); +} + +/* + * The Platforms must override with real definition. + */ +#pragma weak bl1_plat_mem_check + +int bl1_plat_mem_check(uintptr_t mem_base, unsigned int mem_size, + unsigned int flags) +{ + assert(0); + return -ENOMEM; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_gic.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_gic.c new file mode 100644 index 0000000..f736e55 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_gic.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include + +/* + * The following platform GIC functions are weakly defined. They + * provide typical implementations that may be re-used by multiple + * platforms but may also be overridden by a platform if required. + */ +#pragma weak plat_ic_get_pending_interrupt_id +#pragma weak plat_ic_get_pending_interrupt_type +#pragma weak plat_ic_acknowledge_interrupt +#pragma weak plat_ic_get_interrupt_type +#pragma weak plat_ic_end_of_interrupt +#pragma weak plat_interrupt_type_to_line + +uint32_t plat_ic_get_pending_interrupt_id(void) +{ + return arm_gic_get_pending_interrupt_id(); +} + +uint32_t plat_ic_get_pending_interrupt_type(void) +{ + return arm_gic_get_pending_interrupt_type(); +} + +uint32_t plat_ic_acknowledge_interrupt(void) +{ + return arm_gic_acknowledge_interrupt(); +} + +uint32_t plat_ic_get_interrupt_type(uint32_t id) +{ + return arm_gic_get_interrupt_type(id); +} + +void plat_ic_end_of_interrupt(uint32_t id) +{ + arm_gic_end_of_interrupt(id); +} + +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state) +{ + return arm_gic_interrupt_type_to_line(type, security_state); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_gicv2.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_gicv2.c new file mode 100644 index 0000000..65f89dc --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_gicv2.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include + +/* + * The following platform GIC functions are weakly defined. They + * provide typical implementations that may be re-used by multiple + * platforms but may also be overridden by a platform if required. + */ +#pragma weak plat_ic_get_pending_interrupt_id +#pragma weak plat_ic_get_pending_interrupt_type +#pragma weak plat_ic_acknowledge_interrupt +#pragma weak plat_ic_get_interrupt_type +#pragma weak plat_ic_end_of_interrupt +#pragma weak plat_interrupt_type_to_line + +/* + * This function returns the highest priority pending interrupt at + * the Interrupt controller + */ +uint32_t plat_ic_get_pending_interrupt_id(void) +{ + unsigned int id; + + id = gicv2_get_pending_interrupt_id(); + if (id == GIC_SPURIOUS_INTERRUPT) + return INTR_ID_UNAVAILABLE; + + return id; +} + +/* + * This function returns the type of the highest priority pending interrupt + * at the Interrupt controller. In the case of GICv2, the Highest Priority + * Pending interrupt register (`GICC_HPPIR`) is read to determine the id of + * the pending interrupt. The type of interrupt depends upon the id value + * as follows. + * 1. id < PENDING_G1_INTID (1022) is reported as a S-EL1 interrupt + * 2. id = PENDING_G1_INTID (1022) is reported as a Non-secure interrupt. + * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt + * type. + */ +uint32_t plat_ic_get_pending_interrupt_type(void) +{ + unsigned int id; + + id = gicv2_get_pending_interrupt_type(); + + /* Assume that all secure interrupts are S-EL1 interrupts */ + if (id < PENDING_G1_INTID) + return INTR_TYPE_S_EL1; + + if (id == GIC_SPURIOUS_INTERRUPT) + return INTR_TYPE_INVAL; + + return INTR_TYPE_NS; +} + +/* + * This function returns the highest priority pending interrupt at + * the Interrupt controller and indicates to the Interrupt controller + * that the interrupt processing has started. + */ +uint32_t plat_ic_acknowledge_interrupt(void) +{ + return gicv2_acknowledge_interrupt(); +} + +/* + * This function returns the type of the interrupt `id`, depending on how + * the interrupt has been configured in the interrupt controller + */ +uint32_t plat_ic_get_interrupt_type(uint32_t id) +{ + unsigned int type; + + type = gicv2_get_interrupt_group(id); + + /* Assume that all secure interrupts are S-EL1 interrupts */ + return (type) ? INTR_TYPE_NS : INTR_TYPE_S_EL1; +} + +/* + * This functions is used to indicate to the interrupt controller that + * the processing of the interrupt corresponding to the `id` has + * finished. + */ +void plat_ic_end_of_interrupt(uint32_t id) +{ + gicv2_end_of_interrupt(id); +} + +/* + * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. + * The interrupt controller knows which pin/line it uses to signal a type of + * interrupt. It lets the interrupt management framework determine + * for a type of interrupt and security state, which line should be used in the + * SCR_EL3 to control its routing to EL3. The interrupt line is represented + * as the bit position of the IRQ or FIQ bit in the SCR_EL3. + */ +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state) +{ + assert(type == INTR_TYPE_S_EL1 || + type == INTR_TYPE_EL3 || + type == INTR_TYPE_NS); + + /* Non-secure interrupts are signaled on the IRQ line always */ + if (type == INTR_TYPE_NS) + return __builtin_ctz(SCR_IRQ_BIT); + + /* + * Secure interrupts are signaled using the IRQ line if the FIQ is + * not enabled else they are signaled using the FIQ line. + */ + return ((gicv2_is_fiq_enabled()) ? __builtin_ctz(SCR_FIQ_BIT) : + __builtin_ctz(SCR_IRQ_BIT)); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_gicv3.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_gicv3.c new file mode 100644 index 0000000..c961d62 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_gicv3.c @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#if IMAGE_BL31 + +/* + * The following platform GIC functions are weakly defined. They + * provide typical implementations that may be re-used by multiple + * platforms but may also be overridden by a platform if required. + */ +#pragma weak plat_ic_get_pending_interrupt_id +#pragma weak plat_ic_get_pending_interrupt_type +#pragma weak plat_ic_acknowledge_interrupt +#pragma weak plat_ic_get_interrupt_type +#pragma weak plat_ic_end_of_interrupt +#pragma weak plat_interrupt_type_to_line + +CASSERT((INTR_TYPE_S_EL1 == INTR_GROUP1S) && + (INTR_TYPE_NS == INTR_GROUP1NS) && + (INTR_TYPE_EL3 == INTR_GROUP0), assert_interrupt_type_mismatch); + +/* + * This function returns the highest priority pending interrupt at + * the Interrupt controller + */ +uint32_t plat_ic_get_pending_interrupt_id(void) +{ + unsigned int irqnr; + + assert(IS_IN_EL3()); + irqnr = gicv3_get_pending_interrupt_id(); + return (gicv3_is_intr_id_special_identifier(irqnr)) ? + INTR_ID_UNAVAILABLE : irqnr; +} + +/* + * This function returns the type of the highest priority pending interrupt + * at the Interrupt controller. In the case of GICv3, the Highest Priority + * Pending interrupt system register (`ICC_HPPIR0_EL1`) is read to determine + * the id of the pending interrupt. The type of interrupt depends upon the + * id value as follows. + * 1. id = PENDING_G1S_INTID (1020) is reported as a S-EL1 interrupt + * 2. id = PENDING_G1NS_INTID (1021) is reported as a Non-secure interrupt. + * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt + * type. + * 4. All other interrupt id's are reported as EL3 interrupt. + */ +uint32_t plat_ic_get_pending_interrupt_type(void) +{ + unsigned int irqnr; + + assert(IS_IN_EL3()); + irqnr = gicv3_get_pending_interrupt_type(); + + switch (irqnr) { + case PENDING_G1S_INTID: + return INTR_TYPE_S_EL1; + case PENDING_G1NS_INTID: + return INTR_TYPE_NS; + case GIC_SPURIOUS_INTERRUPT: + return INTR_TYPE_INVAL; + default: + return INTR_TYPE_EL3; + } +} + +/* + * This function returns the highest priority pending interrupt at + * the Interrupt controller and indicates to the Interrupt controller + * that the interrupt processing has started. + */ +uint32_t plat_ic_acknowledge_interrupt(void) +{ + assert(IS_IN_EL3()); + return gicv3_acknowledge_interrupt(); +} + +/* + * This function returns the type of the interrupt `id`, depending on how + * the interrupt has been configured in the interrupt controller + */ +uint32_t plat_ic_get_interrupt_type(uint32_t id) +{ + assert(IS_IN_EL3()); + return gicv3_get_interrupt_type(id, plat_my_core_pos()); +} + +/* + * This functions is used to indicate to the interrupt controller that + * the processing of the interrupt corresponding to the `id` has + * finished. + */ +void plat_ic_end_of_interrupt(uint32_t id) +{ + assert(IS_IN_EL3()); + gicv3_end_of_interrupt(id); +} + +/* + * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. + * The interrupt controller knows which pin/line it uses to signal a type of + * interrupt. It lets the interrupt management framework determine for a type of + * interrupt and security state, which line should be used in the SCR_EL3 to + * control its routing to EL3. The interrupt line is represented as the bit + * position of the IRQ or FIQ bit in the SCR_EL3. + */ +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state) +{ + assert(type == INTR_TYPE_S_EL1 || + type == INTR_TYPE_EL3 || + type == INTR_TYPE_NS); + + assert(sec_state_is_valid(security_state)); + assert(IS_IN_EL3()); + + switch (type) { + case INTR_TYPE_S_EL1: + /* + * The S-EL1 interrupts are signaled as IRQ in S-EL0/1 contexts + * and as FIQ in the NS-EL0/1/2 contexts + */ + if (security_state == SECURE) + return __builtin_ctz(SCR_IRQ_BIT); + else + return __builtin_ctz(SCR_FIQ_BIT); + case INTR_TYPE_NS: + /* + * The Non secure interrupts will be signaled as FIQ in S-EL0/1 + * contexts and as IRQ in the NS-EL0/1/2 contexts. + */ + if (security_state == SECURE) + return __builtin_ctz(SCR_FIQ_BIT); + else + return __builtin_ctz(SCR_IRQ_BIT); + default: + assert(0); + /* Fall through in the release build */ + case INTR_TYPE_EL3: + /* + * The EL3 interrupts are signaled as FIQ in both S-EL0/1 and + * NS-EL0/1/2 contexts + */ + return __builtin_ctz(SCR_FIQ_BIT); + } +} +#endif +#if IMAGE_BL32 + +#pragma weak plat_ic_get_pending_interrupt_id +#pragma weak plat_ic_acknowledge_interrupt +#pragma weak plat_ic_end_of_interrupt + +/* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */ +#ifdef AARCH32 +#define IS_IN_EL1() IS_IN_SECURE() +#endif + +/* + * This function returns the highest priority pending interrupt at + * the Interrupt controller + */ +uint32_t plat_ic_get_pending_interrupt_id(void) +{ + unsigned int irqnr; + + assert(IS_IN_EL1()); + irqnr = gicv3_get_pending_interrupt_id_sel1(); + return (irqnr == GIC_SPURIOUS_INTERRUPT) ? + INTR_ID_UNAVAILABLE : irqnr; +} + +/* + * This function returns the highest priority pending interrupt at + * the Interrupt controller and indicates to the Interrupt controller + * that the interrupt processing has started. + */ +uint32_t plat_ic_acknowledge_interrupt(void) +{ + assert(IS_IN_EL1()); + return gicv3_acknowledge_interrupt_sel1(); +} + +/* + * This functions is used to indicate to the interrupt controller that + * the processing of the interrupt corresponding to the `id` has + * finished. + */ +void plat_ic_end_of_interrupt(uint32_t id) +{ + assert(IS_IN_EL1()); + gicv3_end_of_interrupt_sel1(id); +} +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_psci_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_psci_common.c new file mode 100644 index 0000000..3eb6886 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/common/plat_psci_common.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +/* + * The PSCI generic code uses this API to let the platform participate in state + * coordination during a power management operation. It compares the platform + * specific local power states requested by each cpu for a given power domain + * and returns the coordinated target power state that the domain should + * enter. A platform assigns a number to a local power state. This default + * implementation assumes that the platform assigns these numbers in order of + * increasing depth of the power state i.e. for two power states X & Y, if X < Y + * then X represents a shallower power state than Y. As a result, the + * coordinated target local power state for a power domain will be the minimum + * of the requested local power states. + */ +plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, + const plat_local_state_t *states, + unsigned int ncpu) +{ + plat_local_state_t target = PLAT_MAX_OFF_STATE, temp; + + assert(ncpu); + + do { + temp = *states++; + if (temp < target) + target = temp; + } while (--ncpu); + + return target; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/compat/aarch64/plat_helpers_compat.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/compat/aarch64/plat_helpers_compat.S new file mode 100644 index 0000000..6d83d23 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/compat/aarch64/plat_helpers_compat.S @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + .globl plat_my_core_pos + .globl plat_is_my_cpu_primary + .globl plat_get_my_entrypoint + .weak platform_get_core_pos + + /* ----------------------------------------------------- + * Compatibility wrappers for new platform APIs. + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + b platform_get_core_pos +endfunc plat_my_core_pos + +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + b platform_is_primary_cpu +endfunc plat_is_my_cpu_primary + +func plat_get_my_entrypoint + mrs x0, mpidr_el1 + b platform_get_entrypoint +endfunc plat_get_my_entrypoint + + /* ----------------------------------------------------- + * int platform_get_core_pos(int mpidr); + * With this function: CorePos = (ClusterId * 4) + + * CoreId + * ----------------------------------------------------- + */ +func platform_get_core_pos + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc platform_get_core_pos diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/compat/plat_compat.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/compat/plat_compat.mk new file mode 100644 index 0000000..a1cdd80 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/compat/plat_compat.mk @@ -0,0 +1,44 @@ +# +# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +ifeq (${PSCI_EXTENDED_STATE_ID}, 1) + $(error "PSCI Compatibility mode can be enabled only if \ + PSCI_EXTENDED_STATE_ID is not set") +endif + +ifneq (${ARCH}, aarch64) + $(error "PSCI Compatibility mode is only supported for AArch64 platforms") +endif + +PLAT_BL_COMMON_SOURCES += plat/compat/aarch64/plat_helpers_compat.S + +BL31_SOURCES += plat/common/plat_psci_common.c \ + plat/compat/plat_pm_compat.c \ + plat/compat/plat_topology_compat.c diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/compat/plat_pm_compat.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/compat/plat_pm_compat.c new file mode 100644 index 0000000..f51bb55 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/compat/plat_pm_compat.c @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/* + * The platform hooks exported by the platform using the earlier version of + * platform interface + */ +const plat_pm_ops_t *pm_ops; + +/* + * The hooks exported by the compatibility layer + */ +static plat_psci_ops_t compat_psci_ops; + +/* + * The secure entry point to be used on warm reset. + */ +static unsigned long secure_entrypoint; + +/* + * This array stores the 'power_state' requests of each CPU during + * CPU_SUSPEND and SYSTEM_SUSPEND to support querying of state-ID + * by the platform. + */ +unsigned int psci_power_state_compat[PLATFORM_CORE_COUNT]; + +/******************************************************************************* + * The PSCI compatibility helper to parse the power state and populate the + * 'pwr_domain_state' for each power level. It is assumed that, when in + * compatibility mode, the PSCI generic layer need to know only whether the + * affinity level will be OFF or in RETENTION and if the platform supports + * multiple power down and retention states, it will be taken care within + * the platform layer. + ******************************************************************************/ +static int parse_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int i; + int pstate = psci_get_pstate_type(power_state); + int aff_lvl = psci_get_pstate_pwrlvl(power_state); + + if (aff_lvl > PLATFORM_MAX_AFFLVL) + return PSCI_E_INVALID_PARAMS; + + /* Sanity check the requested state */ + if (pstate == PSTATE_TYPE_STANDBY) { + /* + * Set the CPU local state as retention and ignore the higher + * levels. This allows the generic PSCI layer to invoke + * plat_psci_ops 'cpu_standby' hook and the compatibility + * layer invokes the 'affinst_standby' handler with the + * correct power_state parameter thus preserving the correct + * behavior. + */ + req_state->pwr_domain_state[0] = + PLAT_MAX_RET_STATE; + } else { + for (i = 0; i <= aff_lvl; i++) + req_state->pwr_domain_state[i] = + PLAT_MAX_OFF_STATE; + } + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * The PSCI compatibility helper to set the 'power_state' in + * psci_power_state_compat[] at index corresponding to the current core. + ******************************************************************************/ +static void set_psci_power_state_compat(unsigned int power_state) +{ + unsigned int my_core_pos = plat_my_core_pos(); + + psci_power_state_compat[my_core_pos] = power_state; + flush_dcache_range((uintptr_t) &psci_power_state_compat[my_core_pos], + sizeof(psci_power_state_compat[my_core_pos])); +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'validate_power_state' + * hook. + ******************************************************************************/ +static int validate_power_state_compat(unsigned int power_state, + psci_power_state_t *req_state) +{ + int rc; + assert(req_state); + + if (pm_ops->validate_power_state) { + rc = pm_ops->validate_power_state(power_state); + if (rc != PSCI_E_SUCCESS) + return rc; + } + + /* Store the 'power_state' parameter for the current CPU. */ + set_psci_power_state_compat(power_state); + + return parse_power_state(power_state, req_state); +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t + * 'get_sys_suspend_power_state' hook. + ******************************************************************************/ +void get_sys_suspend_power_state_compat(psci_power_state_t *req_state) +{ + unsigned int power_state; + assert(req_state); + + power_state = pm_ops->get_sys_suspend_power_state(); + + /* Store the 'power_state' parameter for the current CPU. */ + set_psci_power_state_compat(power_state); + + if (parse_power_state(power_state, req_state) != PSCI_E_SUCCESS) + assert(0); +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'validate_ns_entrypoint' + * hook. + ******************************************************************************/ +static int validate_ns_entrypoint_compat(uintptr_t ns_entrypoint) +{ + return pm_ops->validate_ns_entrypoint(ns_entrypoint); +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'affinst_standby' hook. + ******************************************************************************/ +static void cpu_standby_compat(plat_local_state_t cpu_state) +{ + unsigned int powerstate = psci_get_suspend_powerstate(); + + assert(powerstate != PSCI_INVALID_DATA); + + pm_ops->affinst_standby(powerstate); +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'affinst_on' hook. + ******************************************************************************/ +static int pwr_domain_on_compat(u_register_t mpidr) +{ + int level, rc; + + /* + * The new PSCI framework does not hold the locks for higher level + * power domain nodes when this hook is invoked. Hence figuring out the + * target state of the parent power domains does not make much sense. + * Hence we hard-code the state as PSCI_STATE_OFF for all the levels. + * We expect the platform to perform the necessary CPU_ON operations + * when the 'affinst_on' is invoked only for level 0. + */ + for (level = PLATFORM_MAX_AFFLVL; level >= 0; level--) { + rc = pm_ops->affinst_on((unsigned long)mpidr, secure_entrypoint, + level, PSCI_STATE_OFF); + if (rc != PSCI_E_SUCCESS) + break; + } + + return rc; +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'affinst_off' hook. + ******************************************************************************/ +static void pwr_domain_off_compat(const psci_power_state_t *target_state) +{ + int level; + unsigned int plat_state; + + for (level = 0; level <= PLATFORM_MAX_AFFLVL; level++) { + plat_state = (is_local_state_run( + target_state->pwr_domain_state[level]) ? + PSCI_STATE_ON : PSCI_STATE_OFF); + pm_ops->affinst_off(level, plat_state); + } +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'affinst_suspend' hook. + ******************************************************************************/ +static void pwr_domain_suspend_compat(const psci_power_state_t *target_state) +{ + int level; + unsigned int plat_state; + + for (level = 0; level <= psci_get_suspend_afflvl(); level++) { + plat_state = (is_local_state_run( + target_state->pwr_domain_state[level]) ? + PSCI_STATE_ON : PSCI_STATE_OFF); + pm_ops->affinst_suspend(secure_entrypoint, level, plat_state); + } +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'affinst_on_finish' + * hook. + ******************************************************************************/ +static void pwr_domain_on_finish_compat(const psci_power_state_t *target_state) +{ + int level; + unsigned int plat_state; + + for (level = PLATFORM_MAX_AFFLVL; level >= 0; level--) { + plat_state = (is_local_state_run( + target_state->pwr_domain_state[level]) ? + PSCI_STATE_ON : PSCI_STATE_OFF); + pm_ops->affinst_on_finish(level, plat_state); + } +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t + * 'affinst_suspend_finish' hook. + ******************************************************************************/ +static void pwr_domain_suspend_finish_compat( + const psci_power_state_t *target_state) +{ + int level; + unsigned int plat_state; + + for (level = psci_get_suspend_afflvl(); level >= 0; level--) { + plat_state = (is_local_state_run( + target_state->pwr_domain_state[level]) ? + PSCI_STATE_ON : PSCI_STATE_OFF); + pm_ops->affinst_suspend_finish(level, plat_state); + } +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'system_off' hook. + ******************************************************************************/ +static void __dead2 system_off_compat(void) +{ + pm_ops->system_off(); +} + +/******************************************************************************* + * The PSCI compatibility helper for plat_pm_ops_t 'system_reset' hook. + ******************************************************************************/ +static void __dead2 system_reset_compat(void) +{ + pm_ops->system_reset(); +} + +/******************************************************************************* + * Export the compatibility compat_psci_ops. The assumption made is that the + * power domains correspond to affinity instances on the platform. + ******************************************************************************/ +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + platform_setup_pm(&pm_ops); + + secure_entrypoint = (unsigned long) sec_entrypoint; + + /* + * It is compulsory for the platform ports using the new porting + * interface to export a hook to validate the power state parameter + */ + compat_psci_ops.validate_power_state = validate_power_state_compat; + + /* + * Populate the compatibility plat_psci_ops_t hooks if available + */ + if (pm_ops->validate_ns_entrypoint) + compat_psci_ops.validate_ns_entrypoint = + validate_ns_entrypoint_compat; + + if (pm_ops->affinst_standby) + compat_psci_ops.cpu_standby = cpu_standby_compat; + + if (pm_ops->affinst_on) + compat_psci_ops.pwr_domain_on = pwr_domain_on_compat; + + if (pm_ops->affinst_off) + compat_psci_ops.pwr_domain_off = pwr_domain_off_compat; + + if (pm_ops->affinst_suspend) + compat_psci_ops.pwr_domain_suspend = pwr_domain_suspend_compat; + + if (pm_ops->affinst_on_finish) + compat_psci_ops.pwr_domain_on_finish = + pwr_domain_on_finish_compat; + + if (pm_ops->affinst_suspend_finish) + compat_psci_ops.pwr_domain_suspend_finish = + pwr_domain_suspend_finish_compat; + + if (pm_ops->system_off) + compat_psci_ops.system_off = system_off_compat; + + if (pm_ops->system_reset) + compat_psci_ops.system_reset = system_reset_compat; + + if (pm_ops->get_sys_suspend_power_state) + compat_psci_ops.get_sys_suspend_power_state = + get_sys_suspend_power_state_compat; + + *psci_ops = &compat_psci_ops; + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/compat/plat_topology_compat.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/compat/plat_topology_compat.c new file mode 100644 index 0000000..f65ad9d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/compat/plat_topology_compat.c @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/* The power domain tree descriptor */ +static unsigned char power_domain_tree_desc + [PLATFORM_NUM_AFFS - PLATFORM_CORE_COUNT + 1]; + +/******************************************************************************* + * Simple routine to set the id of an affinity instance at a given level + * in the mpidr. The assumption is that the affinity level and the power + * domain level are the same. + ******************************************************************************/ +unsigned long mpidr_set_aff_inst(unsigned long mpidr, + unsigned char aff_inst, + int aff_lvl) +{ + unsigned long aff_shift; + + assert(aff_lvl <= MPIDR_AFFLVL3); + + /* + * Decide the number of bits to shift by depending upon + * the power level + */ + aff_shift = get_afflvl_shift(aff_lvl); + + /* Clear the existing power instance & set the new one*/ + mpidr &= ~((unsigned long)MPIDR_AFFLVL_MASK << aff_shift); + mpidr |= (unsigned long)aff_inst << aff_shift; + + return mpidr; +} + +/****************************************************************************** + * This function uses insertion sort to sort a given list of mpidr's in the + * ascending order of the index returned by platform_get_core_pos. + *****************************************************************************/ +void sort_mpidr_by_cpu_idx(unsigned int aff_count, unsigned long mpidr_list[]) +{ + int i, j; + unsigned long temp_mpidr; + + for (i = 1; i < aff_count; i++) { + temp_mpidr = mpidr_list[i]; + + for (j = i; + j > 0 && + platform_get_core_pos(mpidr_list[j-1]) > + platform_get_core_pos(temp_mpidr); + j--) + mpidr_list[j] = mpidr_list[j-1]; + + mpidr_list[j] = temp_mpidr; + } +} + +/******************************************************************************* + * The compatibility routine to construct the power domain tree description. + * The assumption made is that the power domains correspond to affinity + * instances on the platform. This routine's aim is to traverse to the target + * affinity level and populate the number of siblings at that level in + * 'power_domain_tree_desc' array. It uses the current affinity level to keep + * track of how many levels from the root of the tree have been traversed. + * If the current affinity level != target affinity level, then the platform + * is asked to return the number of children that each affinity instance has + * at the current affinity level. Traversal is then done for each child at the + * next lower level i.e. current affinity level - 1. + * + * The power domain description needs to be constructed in such a way that + * affinity instances containing CPUs with lower cpu indices need to be + * described first. Hence when traversing the power domain levels, the list + * of mpidrs at that power domain level is sorted in the ascending order of CPU + * indices before the lower levels are recursively described. + * + * CAUTION: This routine assumes that affinity instance ids are allocated in a + * monotonically increasing manner at each affinity level in a mpidr starting + * from 0. If the platform breaks this assumption then this code will have to + * be reworked accordingly. + ******************************************************************************/ +static unsigned int init_pwr_domain_tree_desc(unsigned long mpidr, + unsigned int affmap_idx, + int cur_afflvl, + int tgt_afflvl) +{ + unsigned int ctr, aff_count; + + /* + * Temporary list to hold the MPIDR list at a particular power domain + * level so as to sort them. + */ + unsigned long mpidr_list[PLATFORM_CORE_COUNT]; + + assert(cur_afflvl >= tgt_afflvl); + + /* + * Find the number of siblings at the current power level & + * assert if there are none 'cause then we have been invoked with + * an invalid mpidr. + */ + aff_count = plat_get_aff_count(cur_afflvl, mpidr); + assert(aff_count); + + if (tgt_afflvl < cur_afflvl) { + for (ctr = 0; ctr < aff_count; ctr++) { + mpidr_list[ctr] = mpidr_set_aff_inst(mpidr, ctr, + cur_afflvl); + } + + /* Need to sort mpidr list according to CPU index */ + sort_mpidr_by_cpu_idx(aff_count, mpidr_list); + for (ctr = 0; ctr < aff_count; ctr++) { + affmap_idx = init_pwr_domain_tree_desc(mpidr_list[ctr], + affmap_idx, + cur_afflvl - 1, + tgt_afflvl); + } + } else { + power_domain_tree_desc[affmap_idx++] = aff_count; + } + return affmap_idx; +} + + +/******************************************************************************* + * This function constructs the topology tree description at runtime + * and returns it. The assumption made is that the power domains correspond + * to affinity instances on the platform. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + int afflvl, affmap_idx; + + /* + * We assume that the platform allocates affinity instance ids from + * 0 onwards at each affinity level in the mpidr. FIRST_MPIDR = 0.0.0.0 + */ + affmap_idx = 0; + for (afflvl = PLATFORM_MAX_AFFLVL; afflvl >= MPIDR_AFFLVL0; afflvl--) { + affmap_idx = init_pwr_domain_tree_desc(FIRST_MPIDR, + affmap_idx, + PLATFORM_MAX_AFFLVL, + afflvl); + } + + assert(affmap_idx == (PLATFORM_NUM_AFFS - PLATFORM_CORE_COUNT + 1)); + + return power_domain_tree_desc; +} + +/****************************************************************************** + * The compatibility helper function for plat_core_pos_by_mpidr(). It + * validates the 'mpidr' by making sure that it is within acceptable bounds + * for the platform and queries the platform layer whether the CPU specified + * by the mpidr is present or not. If present, it returns the index of the + * core corresponding to the 'mpidr'. Else it returns -1. + *****************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned long shift, aff_inst; + int i; + + /* Ignore the Reserved bits and U bit in MPIDR */ + mpidr &= MPIDR_AFFINITY_MASK; + + /* + * Check if any affinity field higher than + * the PLATFORM_MAX_AFFLVL is set. + */ + shift = get_afflvl_shift(PLATFORM_MAX_AFFLVL + 1); + if (mpidr >> shift) + return -1; + + for (i = PLATFORM_MAX_AFFLVL; i >= 0; i--) { + shift = get_afflvl_shift(i); + aff_inst = ((mpidr & + ((unsigned long)MPIDR_AFFLVL_MASK << shift)) >> shift); + if (aff_inst >= plat_get_aff_count(i, mpidr)) + return -1; + } + + if (plat_get_aff_state(0, mpidr) == PSCI_AFF_ABSENT) + return -1; + + return platform_get_core_pos(mpidr); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/custom/oem_svc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/custom/oem_svc.c new file mode 100644 index 0000000..6f31c53 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/custom/oem_svc.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* OEM Service UUID */ +DEFINE_SVC_UUID(oem_svc_uid, + 0xb943add0, 0x069d, 0x11e4, 0x91, 0x91, + 0x08, 0x00, 0x20, 0x0c, 0x9a, 0x66); + + +/* Setup OEM Services */ +static int32_t oem_svc_setup(void) +{ + /* + * Invoke related module setup from here + */ + + return 0; +} + +/******************************************************************************* + * OEM top level handler for servicing SMCs. + ******************************************************************************/ +uint64_t oem_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + uint64_t rc; + + switch (smc_fid) { + default: + rc = SMC_UNK; + WARN("Unimplemented OEM Call: 0x%x\n", smc_fid); + } + + SMC_RET1(handle, rc); +} + +/* + * Top-level OEM Service SMC handler. This handler will in turn dispatch + * calls to related SMC handler + */ +uint64_t oem_svc_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + /* + * Dispatch OEM calls to OEM Common handler and return its return value + */ + if (is_oem_fid(smc_fid)) { + return oem_smc_handler(smc_fid, x1, x2, x3, x4, cookie, + handle, flags); + } + + switch (smc_fid) { + case OEM_SVC_CALL_COUNT: + /* + * Return the number of OEM Service Calls. + */ + SMC_RET1(handle, OEM_SVC_NUM_CALLS); + + case OEM_SVC_UID: + /* Return UID to the caller */ + SMC_UUID_RET(handle, oem_svc_uid); + + case OEM_SVC_VERSION: + /* Return the version of current implementation */ + SMC_RET2(handle, OEM_VERSION_MAJOR, OEM_VERSION_MINOR); + + default: + WARN("Unimplemented OEM Service Call: 0x%x\n", smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} + +/* Register OEM Service Calls as runtime service */ +DECLARE_RT_SVC( + oem_svc, + OEN_OEM_START, + OEN_OEM_END, + SMC_TYPE_FAST, + oem_svc_setup, + oem_svc_smc_handler +); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/custom/oem_svc.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/custom/oem_svc.h new file mode 100644 index 0000000..3b15e15 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/custom/oem_svc.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __OEM_SVC_H__ +#define __OEM_SVC_H__ + +/******************************************************************************* + * Defines for runtime services func ids + ******************************************************************************/ +/* + * Number of OEM calls (above) implemented. + */ +#define OEM_SVC_NUM_CALLS 3 + +/******************************************************************************* + * Defines for OEM Service queries + ******************************************************************************/ +/* 0x83000000 - 0x8300FEFF is OEM service calls */ +#define OEM_SVC_CALL_COUNT 0x8300ff00 +#define OEM_SVC_UID 0x8300ff01 +/* 0x8300ff02 is reserved */ +#define OEM_SVC_VERSION 0x8300ff03 +/* 0x8300ff04 - 0x8300FFFF is reserved for future expansion */ + +/* OEM Service Calls version numbers */ +#define OEM_VERSION_MAJOR 0x0 +#define OEM_VERSION_MINOR 0x1 + +/* The macros below are used to identify OEM calls from the SMC function ID */ +/* SMC32 ID range from 0x83000000 to 0x83000FFF */ +/* SMC64 ID range from 0xC3000000 to 0xC3000FFF */ +#define OEM_FID_MASK 0xf000u +#define OEM_FID_VALUE 0u +#define is_oem_fid(_fid) \ + (((_fid) & OEM_FID_MASK) == OEM_FID_VALUE) + +#define OEM_SVC_E_SUCCESS 0 +#define OEM_SVC_E_NOT_SUPPORTED -1 +#define OEM_SVC_E_INVALID_PARAMS -2 + +#endif /* __OEM_SVC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/drivers/uart/8250_console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/drivers/uart/8250_console.S new file mode 100644 index 0000000..5b0ae6d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/drivers/uart/8250_console.S @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + + .globl console_core_init + .globl console_core_putc + .globl console_core_getc + + /* ----------------------------------------------- + * int console_core_init(unsigned long base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * Out: return 1 on success else 0 on error + * Clobber list : x1, x2, x3 + * ----------------------------------------------- + */ +func console_core_init + /* Check the input base address */ + cbz x0, core_init_fail + /* Check baud rate and uart clock for sanity */ + cbz w1, core_init_fail + cbz w2, core_init_fail + + /* Disable interrupt */ + str wzr, [x0, #UART_IER] + + /* Force DTR and RTS to high */ + mov w3, #(UART_MCR_DTR | UART_MCR_RTS) + str w3, [x0, #UART_MCR] + + /* Check high speed */ + movz w3, #:abs_g1:115200 + movk w3, #:abs_g0_nc:115200 + cmp w2, w3 + b.hi 1f + + /* Non high speed */ + lsl w2, w2, #4 + mov w3, wzr + b 2f + + /* High speed */ +1: lsl w2, w2, #2 + mov w3, #2 + + /* Set high speed UART register */ +2: str w3, [x0, #UART_HIGHSPEED] + + /* Calculate divisor */ + udiv w3, w1, w2 /* divisor = uartclk / (quot * baudrate) */ + msub w1, w3, w2, w1 /* remainder = uartclk % (quot * baudrate) */ + lsr w2, w2, #1 + cmp w1, w2 + cinc w3, w3, hs + + /* Set line configuration, access divisor latches */ + mov w1, #(UART_LCR_DLAB | UART_LCR_WLS_8) + str w1, [x0, #UART_LCR] + + /* Set the divisor */ + and w1, w3, #0xff + str w1, [x0, #UART_DLL] + lsr w1, w3, #8 + and w1, w1, #0xff + str w1, [x0, #UART_DLH] + + /* Hide the divisor latches */ + mov w1, #UART_LCR_WLS_8 + str w1, [x0, #UART_LCR] + + /* Enable FIFOs, and clear receive and transmit */ + mov w1, #(UART_FCR_FIFO_EN | UART_FCR_CLEAR_RCVR | \ + UART_FCR_CLEAR_XMIT) + str w1, [x0, #UART_FCR] + + mov w0, #1 + ret +core_init_fail: + mov w0, wzr + ret +endfunc console_core_init + + /* -------------------------------------------------------- + * int console_core_putc(int c, unsigned long base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_core_putc + /* Check the input parameter */ + cbz x1, putc_error + /* Prepend '\r' to '\n' */ + cmp w0, #0xA + b.ne 2f + + /* Check if the transmit FIFO is full */ +1: ldr w2, [x1, #UART_LSR] + and w2, w2, #UART_LSR_THRE + cbz w2, 1b + mov w2, #0xD + str w2, [x1, #UART_THR] + + /* Check if the transmit FIFO is full */ +2: ldr w2, [x1, #UART_LSR] + and w2, w2, #UART_LSR_THRE + cbz w2, 2b + str w0, [x1, #UART_THR] + ret +putc_error: + mov w0, #-1 + ret +endfunc console_core_putc + + /* --------------------------------------------- + * int console_core_getc(unsigned long base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * In : x0 - console base address + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_getc + cbz x0, getc_error + + /* Check if the receive FIFO is empty */ +1: ldr w1, [x0, #UART_LSR] + tbz w1, #UART_LSR_DR, 1b + ldr w0, [x0, #UART_RBR] + ret +getc_error: + mov w0, #-1 + ret +endfunc console_core_getc diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/drivers/uart/uart8250.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/drivers/uart/uart8250.h new file mode 100644 index 0000000..b0f5b8d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/drivers/uart/uart8250.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __UART8250_H__ +#define __UART8250_H__ + +/* UART register */ +#define UART_RBR 0x00 /* Receive buffer register */ +#define UART_DLL 0x00 /* Divisor latch lsb */ +#define UART_THR 0x00 /* Transmit holding register */ +#define UART_DLH 0x04 /* Divisor latch msb */ +#define UART_IER 0x04 /* Interrupt enable register */ +#define UART_FCR 0x08 /* FIFO control register */ +#define UART_LCR 0x0c /* Line control register */ +#define UART_MCR 0x10 /* Modem control register */ +#define UART_LSR 0x14 /* Line status register */ +#define UART_HIGHSPEED 0x24 /* High speed UART */ + +/* FCR */ +#define UART_FCR_FIFO_EN 0x01 /* enable FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /* clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* clear the XMIT FIFO */ + +/* LCR */ +#define UART_LCR_WLS_8 0x03 /* 8 bit character length */ +#define UART_LCR_DLAB 0x80 /* divisor latch access bit */ + +/* MCR */ +#define UART_MCR_DTR 0x01 +#define UART_MCR_RTS 0x02 + +/* LSR */ +#define UART_LSR_DR 0x01 /* Data ready */ +#define UART_LSR_THRE 0x20 /* Xmit holding register empty */ + +#endif /* __UART8250_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/mtk_plat_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/mtk_plat_common.c new file mode 100644 index 0000000..6ffbfe0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/mtk_plat_common.c @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct atf_arg_t gteearg; + +void clean_top_32b_of_param(uint32_t smc_fid, + uint64_t *px1, + uint64_t *px2, + uint64_t *px3, + uint64_t *px4) +{ + /* if parameters from SMC32. Clean top 32 bits */ + if (0 == (smc_fid & SMC_AARCH64_BIT)) { + *px1 = *px1 & SMC32_PARAM_MASK; + *px2 = *px2 & SMC32_PARAM_MASK; + *px3 = *px3 & SMC32_PARAM_MASK; + *px4 = *px4 & SMC32_PARAM_MASK; + } +} + +#if MTK_SIP_KERNEL_BOOT_ENABLE +static struct kernel_info k_info; + +static void save_kernel_info(uint64_t pc, + uint64_t r0, + uint64_t r1, + uint64_t k32_64) +{ + k_info.k32_64 = k32_64; + k_info.pc = pc; + + if (LINUX_KERNEL_32 == k32_64) { + /* for 32 bits kernel */ + k_info.r0 = 0; + /* machtype */ + k_info.r1 = r0; + /* tags */ + k_info.r2 = r1; + } else { + /* for 64 bits kernel */ + k_info.r0 = r0; + k_info.r1 = r1; + } +} + +uint64_t get_kernel_info_pc(void) +{ + return k_info.pc; +} + +uint64_t get_kernel_info_r0(void) +{ + return k_info.r0; +} + +uint64_t get_kernel_info_r1(void) +{ + return k_info.r1; +} + +uint64_t get_kernel_info_r2(void) +{ + return k_info.r2; +} + +void boot_to_kernel(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4) +{ + static uint8_t kernel_boot_once_flag; + /* only support in booting flow */ + if (0 == kernel_boot_once_flag) { + kernel_boot_once_flag = 1; + + console_init(gteearg.atf_log_port, + UART_CLOCK, UART_BAUDRATE); + INFO("save kernel info\n"); + save_kernel_info(x1, x2, x3, x4); + bl31_prepare_kernel_entry(x4); + INFO("el3_exit\n"); + console_uninit(); + } +} +#endif + +uint32_t plat_get_spsr_for_bl33_entry(void) +{ + unsigned int mode; + uint32_t spsr; + unsigned int ee; + unsigned long daif; + + INFO("Secondary bootloader is AArch32\n"); + mode = MODE32_svc; + ee = 0; + /* + * TODO: Choose async. exception bits if HYP mode is not + * implemented according to the values of SCR.{AW, FW} bits + */ + daif = DAIF_ABT_BIT | DAIF_IRQ_BIT | DAIF_FIQ_BIT; + + spsr = SPSR_MODE32(mode, 0, ee, daif); + return spsr; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/mtk_plat_common.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/mtk_plat_common.h new file mode 100644 index 0000000..a3420f3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/mtk_plat_common.h @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MTK_PLAT_COMMON_H__ +#define __MTK_PLAT_COMMON_H__ +#include +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +#define DEVINFO_SIZE 4 +#define LINUX_KERNEL_32 0 +#define SMC32_PARAM_MASK (0xFFFFFFFF) + +struct atf_arg_t { + unsigned int atf_magic; + unsigned int tee_support; + unsigned int tee_entry; + unsigned int tee_boot_arg_addr; + unsigned int hwuid[4]; /* HW Unique id for t-base used */ + unsigned int HRID[2]; /* HW random id for t-base used */ + unsigned int atf_log_port; + unsigned int atf_log_baudrate; + unsigned int atf_log_buf_start; + unsigned int atf_log_buf_size; + unsigned int atf_irq_num; + unsigned int devinfo[DEVINFO_SIZE]; + unsigned int atf_aee_debug_buf_start; + unsigned int atf_aee_debug_buf_size; +}; + +struct kernel_info { + uint64_t pc; + uint64_t r0; + uint64_t r1; + uint64_t r2; + uint64_t k32_64; +}; + +struct mtk_bl_param_t { + uint64_t bootarg_loc; + uint64_t bootarg_size; + uint64_t bl33_start_addr; + uint64_t tee_info_addr; +}; + +/* Declarations for mtk_plat_common.c */ +uint32_t plat_get_spsr_for_bl32_entry(void); +uint32_t plat_get_spsr_for_bl33_entry(void); +void clean_top_32b_of_param(uint32_t smc_fid, uint64_t *x1, + uint64_t *x2, + uint64_t *x3, + uint64_t *x4); +void bl31_prepare_kernel_entry(uint64_t k32_64); +void enable_ns_access_to_cpuectlr(void); +void boot_to_kernel(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4); +uint64_t get_kernel_info_pc(void); +uint64_t get_kernel_info_r0(void); +uint64_t get_kernel_info_r1(void); +uint64_t get_kernel_info_r2(void); + +extern struct atf_arg_t gteearg; +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/mtk_sip_svc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/mtk_sip_svc.c new file mode 100644 index 0000000..021511e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/mtk_sip_svc.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Mediatek SiP Service UUID */ +DEFINE_SVC_UUID(mtk_sip_svc_uid, + 0xf7582ba4, 0x4262, 0x4d7d, 0x80, 0xe5, + 0x8f, 0x95, 0x05, 0x00, 0x0f, 0x3d); + +#pragma weak mediatek_plat_sip_handler +uint64_t mediatek_plat_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + SMC_RET1(handle, SMC_UNK); +} + +/* + * This function handles Mediatek defined SiP Calls */ +uint64_t mediatek_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + uint32_t ns; + + /* if parameter is sent from SMC32. Clean top 32 bits */ + clean_top_32b_of_param(smc_fid, &x1, &x2, &x3, &x4); + + /* Determine which security state this SMC originated from */ + ns = is_caller_non_secure(flags); + if (!ns) { + /* SiP SMC service secure world's call */ + ; + } else { + /* SiP SMC service normal world's call */ + switch (smc_fid) { +#if MTK_SIP_SET_AUTHORIZED_SECURE_REG_ENABLE + case MTK_SIP_SET_AUTHORIZED_SECURE_REG: { + /* only use ret here */ + uint64_t ret; + + ret = mt_sip_set_authorized_sreg((uint32_t)x1, + (uint32_t)x2); + SMC_RET1(handle, ret); + } +#endif +#if MTK_SIP_KERNEL_BOOT_ENABLE + case MTK_SIP_KERNEL_BOOT_AARCH32: + boot_to_kernel(x1, x2, x3, x4); + SMC_RET0(handle); +#endif + } + } + + return mediatek_plat_sip_handler(smc_fid, x1, x2, x3, x4, + cookie, handle, flags); + +} + +/* + * This function is responsible for handling all SiP calls from the NS world + */ +uint64_t sip_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + switch (smc_fid) { + case SIP_SVC_CALL_COUNT: + /* Return the number of Mediatek SiP Service Calls. */ + SMC_RET1(handle, + MTK_COMMON_SIP_NUM_CALLS + MTK_PLAT_SIP_NUM_CALLS); + + case SIP_SVC_UID: + /* Return UID to the caller */ + SMC_UUID_RET(handle, mtk_sip_svc_uid); + + case SIP_SVC_VERSION: + /* Return the version of current implementation */ + SMC_RET2(handle, MTK_SIP_SVC_VERSION_MAJOR, + MTK_SIP_SVC_VERSION_MINOR); + + default: + return mediatek_sip_handler(smc_fid, x1, x2, x3, x4, + cookie, handle, flags); + } +} + +/* Define a runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + mediatek_sip_svc, + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + NULL, + sip_smc_handler +); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/mtk_sip_svc.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/mtk_sip_svc.h new file mode 100644 index 0000000..703e49a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/common/mtk_sip_svc.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __PLAT_SIP_SVC_H__ +#define __PLAT_SIP_SVC_H__ + +#include + +/* SMC function IDs for SiP Service queries */ +#define SIP_SVC_CALL_COUNT 0x8200ff00 +#define SIP_SVC_UID 0x8200ff01 +/* 0x8200ff02 is reserved */ +#define SIP_SVC_VERSION 0x8200ff03 + +/* Mediatek SiP Service Calls version numbers */ +#define MTK_SIP_SVC_VERSION_MAJOR 0x0 +#define MTK_SIP_SVC_VERSION_MINOR 0x1 + +#define SMC_AARCH64_BIT 0x40000000 + +/* Number of Mediatek SiP Calls implemented */ +#define MTK_COMMON_SIP_NUM_CALLS 4 + +/* Mediatek SiP Service Calls function IDs */ +#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001 + +/* For MTK SMC from Secure OS */ +/* 0x82000000 - 0x820000FF & 0xC2000000 - 0xC20000FF */ +#define MTK_SIP_KERNEL_BOOT_AARCH32 0x82000200 +#define MTK_SIP_KERNEL_BOOT_AARCH64 0xC2000200 + +/* Mediatek SiP Calls error code */ +enum { + MTK_SIP_E_SUCCESS = 0, + MTK_SIP_E_INVALID_PARAM = -1, + MTK_SIP_E_NOT_SUPPORTED = -2, + MTK_SIP_E_INVALID_RANGE = -3, + MTK_SIP_E_PERMISSION_DENY = -4, + MTK_SIP_E_LOCK_FAIL = -5 +}; + +/* + * This function should be implemented in Mediatek SOC directory. It fullfills + * MTK_SIP_SET_AUTHORIZED_SECURE_REG SiP call by checking the sreg with the + * predefined secure register list, if a match was found, set val to sreg. + * + * Return MTK_SIP_E_SUCCESS on success, and MTK_SIP_E_INVALID_PARAM on failure. + */ +uint64_t mt_sip_set_authorized_sreg(uint32_t sreg, uint32_t val); + +#endif /* __PLAT_SIP_SVC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/aarch64/plat_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/aarch64/plat_helpers.S new file mode 100644 index 0000000..eb0611a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/aarch64/plat_helpers.S @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + + .globl plat_secondary_cold_boot_setup + .globl plat_report_exception + .globl platform_is_primary_cpu + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl platform_mem_init + + + .macro crash_ram_log + /* + * Check teearg->atf_log_buf_size. + * Exit if atf_log_buf_size equals 0 + */ + adr x2, ptr_atf_crash_flag + ldr x2, [x2] + /* exit if ptr_atf_crash_flag equals NULL */ + cbz x2, exit_putc + + /* + * set atf crash magic number + */ +1: + adr x2, ptr_atf_crash_flag + ldr x2, [x2] + mov_imm x1, 0xdead1abf + /* p_atf_log_ctrl->atf_crash_flag = 0xdead1abf */ + str w1, [x2] + /* can't use w3 return addr, w4, start of buffer addr */ + ldr w2, [x2] + cmp w2, w1 + b.ne 1b + + /* + * get cpu id + */ + mrs x1, mpidr_el1 + /* refer to platform_get_core_pos */ + and x2, x1, #MPIDR_CPU_MASK + and x1, x1, #MPIDR_CLUSTER_MASK + /* x1 = cpu id (cpu id = aff0 + aff1*4 ) */ + add x1, x2, x1, LSR #6 + + adr x2, ptr_atf_except_write_pos_per_cpu + ldr x2, [x2] + /* + * plus (cpu_id * 8)--> + * &p_atf_log_ctrl->atf_except_write_pos_per_cpu[cpu_id] + * x2 = &p_atf_log_ctrl->atf_except_write_pos_per_cpu[cpu_id]; + */ + add x2, x2, x1, LSL # 3 + /* log write */ + /* w1 = p_atf_log_ctrl->atf_except_write_pos_per_cpu[cpu_id] */ + ldr x1, [x2] + /* *x1 = w0--> + * *(p_atf_log_ctrl->atf_except_write_pos_per_cpu[cpu_id]) = c) + */ + strb w0, [x1] + /* w1++ */ + add x1, x1, #1 + /* p_atf_log_ctrl->atf_except_write_pos_per_cpu[cpu_id] = w1 */ + str x1, [x2] +exit_putc: + .endm + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* Do not do cold boot for secondary CPU */ +cb_panic: + b cb_panic +endfunc plat_secondary_cold_boot_setup + +func platform_is_primary_cpu + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #PLAT_PRIMARY_CPU + cset x0, eq + ret +endfunc platform_is_primary_cpu + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0, x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, UART0_BASE + mov_imm x1, UART_CLOCK + mov_imm x2, UART_BAUDRATE + b console_init + ret +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(void) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, UART0_BASE + b console_core_putc + ret +endfunc plat_crash_console_putc + + /* -------------------------------------------------------- + * void platform_mem_init (void); + * + * Any memory init, relocation to be done before the + * platform boots. Called very early in the boot process. + * -------------------------------------------------------- + */ +func platform_mem_init + ret +endfunc platform_mem_init + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/bl31.ld.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/bl31.ld.S new file mode 100644 index 0000000..44510a7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/bl31.ld.S @@ -0,0 +1,198 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) +OUTPUT_ARCH(PLATFORM_LINKER_ARCH) +ENTRY(bl31_entrypoint) + + +MEMORY { + RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_TZRAM_SIZE + RAM2 (rwx): ORIGIN = TZRAM2_BASE, LENGTH = TZRAM2_SIZE +} + + +SECTIONS +{ + . = BL31_BASE; + + ASSERT(. == ALIGN(2048), + "vector base is not aligned on a 2K boundary.") + + __RO_START__ = .; + vector . : { + *(.vectors) + } >RAM + + ASSERT(. == ALIGN(4096), + "BL31_BASE address is not aligned on a page boundary.") + + ro . : { + *bl31_entrypoint.o(.text*) + *(.text*) + *(.rodata*) + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __RT_SVC_DESCS_START__ = .; + KEEP(*(rt_svc_descs)) + __RT_SVC_DESCS_END__ = .; + + /* + * Ensure 8-byte alignment for cpu_ops so that its fields are also + * aligned. Also ensure cpu_ops inclusion. + */ + . = ALIGN(8); + __CPU_OPS_START__ = .; + KEEP(*(cpu_ops)) + __CPU_OPS_END__ = .; + + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as read-only, + * executable. No RW data from the next section must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __RO_END__ = .; + } >RAM + + ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, + "cpu_ops not defined for this platform.") + + /* + * Define a linker symbol to mark start of the RW memory area for this + * image. + */ + __RW_START__ = . ; + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + +#ifdef BL31_PROGBITS_LIMIT + ASSERT(. <= BL31_PROGBITS_LIMIT, "BL3-1 progbits has exceeded its limit.") +#endif + + stacks (NOLOAD) : { + __STACKS_START__ = .; + *(tzfw_normal_stacks) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss (NOLOAD) : ALIGN(16) { + __BSS_START__ = .; + *(.bss*) + *(COMMON) +#if !USE_COHERENT_MEM + /* + * Bakery locks are stored in normal .bss memory + * + * Each lock's data is spread across multiple cache lines, one per CPU, + * but multiple locks can share the same cache line. + * The compiler will allocate enough memory for one CPU's bakery locks, + * the remaining cache lines are allocated by the linker script + */ + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __BAKERY_LOCK_START__ = .; + *(bakery_lock) + . = ALIGN(CACHE_WRITEBACK_GRANULE); + __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); + . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); + __BAKERY_LOCK_END__ = .; +#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE + ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, + "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); +#endif +#endif + __BSS_END__ = .; + __RW_END__ = .; + } >RAM + + ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.") + + /* + * The xlat_table section is for full, aligned page tables (4K). + * Removing them from .bss avoids forcing 4K alignment on + * the .bss section and eliminates the unecessary zero init + */ + xlat_table (NOLOAD) : { + *(xlat_table) + } >RAM2 + +#if USE_COHERENT_MEM + /* + * The base address of the coherent memory section must be page-aligned (4K) + * to guarantee that the coherent data are stored on their own pages and + * are not mixed with normal data. This is required to set up the correct + * memory attributes for the coherent data page tables. + */ + coherent_ram (NOLOAD) : ALIGN(4096) { + __COHERENT_RAM_START__ = .; + /* + * Bakery locks are stored in coherent memory + * + * Each lock's data is contiguous and fully allocated by the compiler + */ + *(bakery_lock) + *(tzfw_coherent_mem) + __COHERENT_RAM_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked + * as device memory. No other unexpected data must creep in. + * Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + __COHERENT_RAM_END__ = .; + } >RAM2 +#endif + + /* + * Define a linker symbol to mark end of the RW memory area for this + * image. + */ + __BL31_END__ = .; + + __BSS_SIZE__ = SIZEOF(.bss); +#if USE_COHERENT_MEM + __COHERENT_RAM_UNALIGNED_SIZE__ = + __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; +#endif + + ASSERT(. <= TZRAM2_LIMIT, "TZRAM2 image has exceeded its limit.") +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/bl31_plat_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/bl31_plat_setup.c new file mode 100644 index 0000000..3a8612d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/bl31_plat_setup.c @@ -0,0 +1,492 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/******************************************************************************* + * Declarations of linker defined symbols which will help us find the layout + * of trusted SRAM + ******************************************************************************/ +unsigned long __RO_START__; +unsigned long __RO_END__; + +unsigned long __COHERENT_RAM_START__; +unsigned long __COHERENT_RAM_END__; + +/* + * The next 2 constants identify the extents of the code & RO data region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. + */ +#define BL31_RO_BASE (unsigned long)(&__RO_START__) +#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) + +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) + +/* + * Placeholder variables for copying the arguments that have been passed to + * BL3-1 from BL2. + */ +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + +static const int cci_map[] = { + PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX, + PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX +}; + +static uint32_t cci_map_length = ARRAY_SIZE(cci_map); + +/* Table of regions to map using the MMU. */ +static const mmap_region_t plat_mmap[] = { + /* for TF text, RO, RW */ + MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(RAM_CONSOLE_BASE & ~(PAGE_SIZE_MASK), RAM_CONSOLE_SIZE, + MT_DEVICE | MT_RW | MT_NS), + { 0 } + +}; + +/******************************************************************************* + * Macro generating the code for the function setting up the pagetables as per + * the platform memory map & initialize the mmu, for the given exception level + ******************************************************************************/ +#define DEFINE_CONFIGURE_MMU_EL(_el) \ + void plat_configure_mmu_el ## _el(unsigned long total_base, \ + unsigned long total_size, \ + unsigned long ro_start, \ + unsigned long ro_limit, \ + unsigned long coh_start, \ + unsigned long coh_limit) \ + { \ + mmap_add_region(total_base, total_base, \ + total_size, \ + MT_MEMORY | MT_RW | MT_SECURE); \ + mmap_add_region(ro_start, ro_start, \ + ro_limit - ro_start, \ + MT_MEMORY | MT_RO | MT_SECURE); \ + mmap_add_region(coh_start, coh_start, \ + coh_limit - coh_start, \ + MT_DEVICE | MT_RW | MT_SECURE); \ + mmap_add(plat_mmap); \ + init_xlat_tables(); \ + \ + enable_mmu_el ## _el(0); \ + } + +/* Define EL3 variants of the function initialising the MMU */ +DEFINE_CONFIGURE_MMU_EL(3) + +unsigned int plat_get_syscnt_freq2(void) +{ + return SYS_COUNTER_FREQ_IN_TICKS; +} + +void plat_cci_init(void) +{ + /* Initialize CCI driver */ + cci_init(PLAT_MT_CCI_BASE, cci_map, cci_map_length); +} + +void plat_cci_enable(void) +{ + /* + * Enable CCI coherency for this cluster. + * No need for locks as no other cpu is active at the moment. + */ + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); +} + +void plat_cci_disable(void) +{ + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); +} + + +static void platform_setup_cpu(void) +{ + /* setup big cores */ + mmio_write_32((uintptr_t)&mt6795_mcucfg->mp1_config_res, + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK | + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK | + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK | + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK | + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK); + mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, MP1_AINACTS); + mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_clkenm_div, + MP1_SW_CG_GEN); + mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_rst_ctl, + MP1_L2RSTDISABLE); + + /* set big cores arm64 boot mode */ + mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_cpucfg, + MP1_CPUCFG_64BIT); + + /* set LITTLE cores arm64 boot mode */ + mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp0_rv_addr[0].rv_addr_hw, + MP0_CPUCFG_64BIT); +} + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + next_image_info = (type == NON_SECURE) ? + &bl33_image_ep_info : &bl32_image_ep_info; + + /* None of the images on this platform can have 0x0 as the entrypoint */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +/******************************************************************************* + * Perform any BL3-1 early platform setup. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they + * are lost (potentially). This needs to be done before the MMU is initialized + * so that the memory layout can be used while creating page tables. + * BL2 has flushed this information to memory, so we are guaranteed to pick up + * good data. + ******************************************************************************/ +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +{ + struct mtk_bl_param_t *pmtk_bl_param = + (struct mtk_bl_param_t *)from_bl2; + struct atf_arg_t *teearg; + unsigned long long normal_base; + unsigned long long atf_base; + + assert(from_bl2 != NULL); + /* + * Mediatek preloader(i.e, BL2) is in 32 bit state, high 32bits + * of 64 bit GP registers are UNKNOWN if CPU warm reset from 32 bit + * to 64 bit state. So we need to clear high 32bit, + * which may be random value. + */ + pmtk_bl_param = + (struct mtk_bl_param_t *)((uint64_t)pmtk_bl_param & 0x00000000ffffffff); + plat_params_from_bl2 = + (void *)((uint64_t)plat_params_from_bl2 & 0x00000000ffffffff); + + teearg = (struct atf_arg_t *)pmtk_bl_param->tee_info_addr; + + console_init(teearg->atf_log_port, UART_CLOCK, UART_BAUDRATE); + memcpy((void *)>eearg, (void *)teearg, sizeof(struct atf_arg_t)); + + normal_base = 0; + /* in ATF boot time, timer for cntpct_el0 is not initialized + * so it will not count now. + */ + atf_base = read_cntpct_el0(); + sched_clock_init(normal_base, atf_base); + + VERBOSE("bl31_setup\n"); + + /* Populate entry point information for BL3-2 and BL3-3 */ + SET_PARAM_HEAD(&bl32_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + + SET_PARAM_HEAD(&bl33_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + /* + * Tell BL3-1 where the non-trusted software image + * is located and the entry state information + */ + /* BL33_START_ADDRESS */ + bl33_image_ep_info.pc = pmtk_bl_param->bl33_start_addr; + bl33_image_ep_info.spsr = plat_get_spsr_for_bl33_entry(); + bl33_image_ep_info.args.arg4 = pmtk_bl_param->bootarg_loc; + bl33_image_ep_info.args.arg5 = pmtk_bl_param->bootarg_size; + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); +} +/******************************************************************************* + * Perform any BL3-1 platform setup code + ******************************************************************************/ + +void bl31_platform_setup(void) +{ + platform_setup_cpu(); + + generic_delay_timer_init(); + + plat_mt_gic_driver_init(); + /* Initialize the gic cpu and distributor interfaces */ + plat_mt_gic_init(); + + /* Topologies are best known to the platform. */ + mt_setup_topology(); +} +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the mmu in a quick and dirty way. + * Init MTK propiartary log buffer control field. + ******************************************************************************/ +void bl31_plat_arch_setup(void) +{ + /* Enable non-secure access to CCI-400 registers */ + mmio_write_32(CCI400_BASE + CCI_SEC_ACCESS_OFFSET, 0x1); + + plat_cci_init(); + plat_cci_enable(); + + if (gteearg.atf_log_buf_size != 0) { + INFO("mmap atf buffer : 0x%x, 0x%x\n\r", + gteearg.atf_log_buf_start, + gteearg.atf_log_buf_size); + + mmap_add_region( + gteearg.atf_log_buf_start & + ~(PAGE_SIZE_2MB_MASK), + gteearg.atf_log_buf_start & + ~(PAGE_SIZE_2MB_MASK), + PAGE_SIZE_2MB, + MT_DEVICE | MT_RW | MT_NS); + + INFO("mmap atf buffer (force 2MB aligned):0x%x, 0x%x\n", + (gteearg.atf_log_buf_start & ~(PAGE_SIZE_2MB_MASK)), + PAGE_SIZE_2MB); + } + /* + * add TZRAM_BASE to memory map + * then set RO and COHERENT to different attribute + */ + plat_configure_mmu_el3( + (TZRAM_BASE & ~(PAGE_SIZE_MASK)), + (TZRAM_SIZE & ~(PAGE_SIZE_MASK)), + (BL31_RO_BASE & ~(PAGE_SIZE_MASK)), + BL31_RO_LIMIT, + BL31_COHERENT_RAM_BASE, + BL31_COHERENT_RAM_LIMIT); + /* Initialize for ATF log buffer */ + if (gteearg.atf_log_buf_size != 0) { + gteearg.atf_aee_debug_buf_size = ATF_AEE_BUFFER_SIZE; + gteearg.atf_aee_debug_buf_start = + gteearg.atf_log_buf_start + + gteearg.atf_log_buf_size - ATF_AEE_BUFFER_SIZE; + INFO("ATF log service is registered (0x%x, aee:0x%x)\n", + gteearg.atf_log_buf_start, + gteearg.atf_aee_debug_buf_start); + } else{ + gteearg.atf_aee_debug_buf_size = 0; + gteearg.atf_aee_debug_buf_start = 0; + } + + /* Platform code before bl31_main */ + /* compatible to the earlier chipset */ + + /* Show to ATF log buffer & UART */ + INFO("BL3-1: %s\n", version_string); + INFO("BL3-1: %s\n", build_message); + +} +#if 0 +/* MTK Define */ +#define ACTLR_CPUECTLR_BIT (1 << 1) + +void enable_ns_access_to_cpuectlr(void) +{ + unsigned int next_actlr; + + + /* ACTLR_EL1 do not implement CUPECTLR */ + next_actlr = read_actlr_el2(); + next_actlr |= ACTLR_CPUECTLR_BIT; + write_actlr_el2(next_actlr); + + next_actlr = read_actlr_el3(); + next_actlr |= ACTLR_CPUECTLR_BIT; + write_actlr_el3(next_actlr); +} +#endif +/******************************************************************************* + * This function prepare boot argument for 64 bit kernel entry + ******************************************************************************/ +static entry_point_info_t *bl31_plat_get_next_kernel64_ep_info(void) +{ + entry_point_info_t *next_image_info; + unsigned long el_status; + unsigned int mode; + + el_status = 0; + mode = 0; + + /* Kernel image is always non-secured */ + next_image_info = &bl33_image_ep_info; + + /* Figure out what mode we enter the non-secure world in */ + el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; + el_status &= ID_AA64PFR0_ELX_MASK; + + if (el_status) { + INFO("Kernel_EL2\n"); + mode = MODE_EL2; + } else{ + INFO("Kernel_EL1\n"); + mode = MODE_EL1; + } + + INFO("Kernel is 64Bit\n"); + next_image_info->spsr = + SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + next_image_info->pc = get_kernel_info_pc(); + next_image_info->args.arg0 = get_kernel_info_r0(); + next_image_info->args.arg1 = get_kernel_info_r1(); + + INFO("pc=0x%lx, r0=0x%lx, r1=0x%lx\n", + next_image_info->pc, + next_image_info->args.arg0, + next_image_info->args.arg1); + + + SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE); + + /* None of the images on this platform can have 0x0 as the entrypoint */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +/******************************************************************************* + * This function prepare boot argument for 32 bit kernel entry + ******************************************************************************/ +static entry_point_info_t *bl31_plat_get_next_kernel32_ep_info(void) +{ + entry_point_info_t *next_image_info; + unsigned int mode; + + mode = 0; + + /* Kernel image is always non-secured */ + next_image_info = &bl33_image_ep_info; + + /* Figure out what mode we enter the non-secure world in */ + mode = MODE32_hyp; + /* + * TODO: Consider the possibility of specifying the SPSR in + * the FIP ToC and allowing the platform to have a say as + * well. + */ + + INFO("Kernel is 32Bit\n"); + next_image_info->spsr = + SPSR_MODE32(mode, SPSR_T_ARM, SPSR_E_LITTLE, + (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT)); + next_image_info->pc = get_kernel_info_pc(); + next_image_info->args.arg0 = get_kernel_info_r0(); + next_image_info->args.arg1 = get_kernel_info_r1(); + next_image_info->args.arg2 = get_kernel_info_r2(); + + INFO("pc=0x%lx, r0=0x%lx, r1=0x%lx, r2=0x%lx\n", + next_image_info->pc, + next_image_info->args.arg0, + next_image_info->args.arg1, + next_image_info->args.arg2); + + + SET_SECURITY_STATE(next_image_info->h.attr, NON_SECURE); + + /* None of the images on this platform can have 0x0 as the entrypoint */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +/******************************************************************************* + * This function prepare boot argument for kernel entrypoint + ******************************************************************************/ +void bl31_prepare_kernel_entry(uint64_t k32_64) +{ + entry_point_info_t *next_image_info; + uint32_t image_type; + + /* Determine which image to execute next */ + /* image_type = bl31_get_next_image_type(); */ + image_type = NON_SECURE; + + /* Program EL3 registers to enable entry into the next EL */ + if (k32_64 == 0) + next_image_info = bl31_plat_get_next_kernel32_ep_info(); + else + next_image_info = bl31_plat_get_next_kernel64_ep_info(); + + assert(next_image_info); + assert(image_type == GET_SECURITY_STATE(next_image_info->h.attr)); + + INFO("BL3-1: Preparing for EL3 exit to %s world, Kernel\n", + (image_type == SECURE) ? "secure" : "normal"); + INFO("BL3-1: Next image address = 0x%llx\n", + (unsigned long long) next_image_info->pc); + INFO("BL3-1: Next image spsr = 0x%x\n", next_image_info->spsr); + cm_init_context(read_mpidr_el1(), next_image_info); + cm_prepare_el3_exit(image_type); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/drivers/timer/mt_cpuxgpt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/drivers/timer/mt_cpuxgpt.c new file mode 100644 index 0000000..2430c47 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/drivers/timer/mt_cpuxgpt.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#define CPUXGPT_BASE 0x10200000 +#define INDEX_BASE (CPUXGPT_BASE+0x0674) +#define CTL_BASE (CPUXGPT_BASE+0x0670) + +uint64_t normal_time_base; +uint64_t atf_time_base; + +void sched_clock_init(uint64_t normal_base, uint64_t atf_base) +{ + normal_time_base = normal_base; + atf_time_base = atf_base; +} + +uint64_t sched_clock(void) +{ + uint64_t cval; + + cval = (((read_cntpct_el0() - atf_time_base)*1000)/ + SYS_COUNTER_FREQ_IN_MHZ) + normal_time_base; + return cval; +} + +/* + * Return: 0 - Trying to disable the CPUXGPT control bit, + * and not allowed to disable it. + * Return: 1 - reg_addr is not realted to disable the control bit. + */ +unsigned char check_cpuxgpt_write_permission(unsigned int reg_addr, + unsigned int reg_value) +{ + unsigned int idx; + unsigned int ctl_val; + + if (reg_addr == CTL_BASE) { + idx = mmio_read_32(INDEX_BASE); + + /* idx 0: CPUXGPT system control */ + if (idx == 0) { + ctl_val = mmio_read_32(CTL_BASE); + if (ctl_val & 1) { + /* + * if enable bit already set, + * then bit 0 is not allow to set as 0 + */ + if (!(reg_value & 1)) + return 0; + } + } + } + return 1; +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/drivers/timer/mt_cpuxgpt.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/drivers/timer/mt_cpuxgpt.h new file mode 100644 index 0000000..edd045c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/drivers/timer/mt_cpuxgpt.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MT_CPUXGPT_H__ +#define __MT_CPUXGPT_H__ + +/* REG */ +#define INDEX_CTL_REG 0x000 +#define INDEX_STA_REG 0x004 +#define INDEX_CNT_L_INIT 0x008 +#define INDEX_CNT_H_INIT 0x00C + +/* CTL_REG SET */ +#define EN_CPUXGPT 0x01 +#define EN_AHLT_DEBUG 0x02 +#define CLK_DIV1 (0x1 << 8) +#define CLK_DIV2 (0x2 << 8) +#define CLK_DIV4 (0x4 << 8) +#define CLK_DIV_MASK (~(0x7<<8)) + +void generic_timer_backup(void); +void sched_clock_init(uint64_t normal_base, uint64_t atf_base); +uint64_t sched_clock(void); + +#endif /* __MT_CPUXGPT_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/mcucfg.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/mcucfg.h new file mode 100644 index 0000000..879e7fa --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/mcucfg.h @@ -0,0 +1,180 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MCUCFG_H__ +#define __MCUCFG_H__ + +#include +#include + +struct mt6795_mcucfg_regs { + uint32_t mp0_ca7l_cache_config; + struct { + uint32_t mem_delsel0; + uint32_t mem_delsel1; + } mp0_cpu[4]; + uint32_t mp0_cache_mem_delsel0; + uint32_t mp0_cache_mem_delsel1; + uint32_t mp0_axi_config; + uint32_t mp0_misc_config[2]; + struct { + uint32_t rv_addr_lw; + uint32_t rv_addr_hw; + } mp0_rv_addr[4]; + uint32_t mp0_ca7l_cfg_dis; + uint32_t mp0_ca7l_clken_ctrl; + uint32_t mp0_ca7l_rst_ctrl; + uint32_t mp0_ca7l_misc_config; + uint32_t mp0_ca7l_dbg_pwr_ctrl; + uint32_t mp0_rw_rsvd0; + uint32_t mp0_rw_rsvd1; + uint32_t mp0_ro_rsvd; + uint32_t reserved0_0[100]; + uint32_t mp1_cpucfg; + uint32_t mp1_miscdbg; + uint32_t reserved0_1[13]; + uint32_t mp1_rst_ctl; + uint32_t mp1_clkenm_div; + uint32_t reserved0_2[7]; + uint32_t mp1_config_res; + uint32_t reserved0_3[13]; + struct { + uint32_t rv_addr_lw; + uint32_t rv_addr_hw; + } mp1_rv_addr[2]; + uint32_t reserved0_4[84]; + uint32_t mp0_rst_status; /* 0x400 */ + uint32_t mp0_dbg_ctrl; + uint32_t mp0_dbg_flag; + uint32_t mp0_ca7l_ir_mon; + struct { + uint32_t pc_lw; + uint32_t pc_hw; + uint32_t fp_arch32; + uint32_t sp_arch32; + uint32_t fp_arch64_lw; + uint32_t fp_arch64_hw; + uint32_t sp_arch64_lw; + uint32_t sp_arch64_hw; + } mp0_dbg_core[4]; + uint32_t dfd_ctrl; + uint32_t dfd_cnt_l; + uint32_t dfd_cnt_h; + uint32_t misccfg_mp0_rw_rsvd; + uint32_t misccfg_sec_vio_status0; + uint32_t misccfg_sec_vio_status1; + uint32_t reserved1[22]; + uint32_t misccfg_rw_rsvd; /* 0x500 */ + uint32_t mcusys_dbg_mon_sel_a; + uint32_t mcusys_dbg_mon; + uint32_t reserved2[61]; + uint32_t mcusys_config_a; /* 0x600 */ + uint32_t mcusys_config1_a; + uint32_t mcusys_gic_peribase_a; + uint32_t reserved3; + uint32_t sec_range0_start; /* 0x610 */ + uint32_t sec_range0_end; + uint32_t sec_range_enable; + uint32_t reserved4; + uint32_t int_pol_ctl[8]; /* 0x620 */ + uint32_t aclken_div; /* 0x640 */ + uint32_t pclken_div; + uint32_t l2c_sram_ctrl; + uint32_t armpll_jit_ctrl; + uint32_t cci_addrmap; /* 0x650 */ + uint32_t cci_config; + uint32_t cci_periphbase; + uint32_t cci_nevntcntovfl; + uint32_t cci_clk_ctrl; /* 0x660 */ + uint32_t cci_acel_s1_ctrl; + uint32_t bus_fabric_dcm_ctrl; + uint32_t reserved5; + uint32_t xgpt_ctl; /* 0x670 */ + uint32_t xgpt_idx; + uint32_t ptpod2_ctl0; + uint32_t ptpod2_ctl1; + uint32_t mcusys_revid; + uint32_t mcusys_rw_rsvd0; + uint32_t mcusys_rw_rsvd1; +}; + +static struct mt6795_mcucfg_regs *const mt6795_mcucfg = (void *)MCUCFG_BASE; + +/* cpu boot mode */ +enum { + MP0_CPUCFG_64BIT_SHIFT = 12, + MP1_CPUCFG_64BIT_SHIFT = 28, + MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT, + MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT +}; + +/* scu related */ +enum { + MP0_ACINACTM_SHIFT = 4, + MP1_ACINACTM_SHIFT = 0, + MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT, + MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT +}; + +enum { + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0, + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4, + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8, + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12, + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16, + + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT +}; + +enum { + MP1_AINACTS_SHIFT = 4, + MP1_AINACTS = 1 << MP1_AINACTS_SHIFT +}; + +enum { + MP1_SW_CG_GEN_SHIFT = 12, + MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT +}; + +enum { + MP1_L2RSTDISABLE_SHIFT = 14, + MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT +}; + +#endif /* __MCUCFG_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/plat_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/plat_macros.S new file mode 100644 index 0000000..ef9d1d8 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/plat_macros.S @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +.section .rodata.gic_reg_name, "aS" +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ + " Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL3-1. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + mov_imm x16, BASE_GICD_BASE + mov_imm x17, BASE_GICC_BASE + /* Load the gicc reg list to x6 */ + adr x6, gicc_regs + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + .endm + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* ------------------------------------------------ + * The below macro prints out relevant interconnect + * registers whenever an unhandled exception is + * taken in BL3-1. + * Clobbers: x0 - x9, sp + * ------------------------------------------------ + */ + .macro plat_print_interconnect_regs + adr x6, cci_iface_regs + /* Store in x7 the base address of the first interface */ + mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX)) + ldr w8, [x7, #SNOOP_CTRL_REG] + /* Store in x7 the base address of the second interface */ + mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX)) + ldr w9, [x7, #SNOOP_CTRL_REG] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + .endm diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/plat_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/plat_private.h new file mode 100644 index 0000000..7385c49 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/plat_private.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_PRIVATE_H__ +#define __PLAT_PRIVATE_H__ +#include +#include + +void plat_configure_mmu_el3(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long, + unsigned long, + unsigned long); + +void plat_cci_init(void); +void plat_cci_enable(void); +void plat_cci_disable(void); + +/* Declarations for plat_mt_gic.c */ +void plat_mt_gic_init(void); + +/* Declarations for plat_topology.c */ +int mt_setup_topology(void); +void plat_delay_timer_init(void); + +void plat_mt_gic_driver_init(void); +void plat_mt_gic_init(void); +void plat_mt_gic_cpuif_enable(void); +void plat_mt_gic_cpuif_disable(void); +void plat_mt_gic_pcpu_init(void); + +#endif /* __PLAT_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/plat_sip_calls.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/plat_sip_calls.h new file mode 100644 index 0000000..a4844f4 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/plat_sip_calls.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_SIP_CALLS_H__ +#define __PLAT_SIP_CALLS_H__ + +/******************************************************************************* + * Plat SiP function constants + ******************************************************************************/ +#define MTK_PLAT_SIP_NUM_CALLS 0 + +#endif /* __PLAT_SIP_CALLS_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/platform_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/platform_def.h new file mode 100644 index 0000000..275333f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/platform_def.h @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#define PLAT_PRIMARY_CPU 0x0 + +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define MT_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + +#define IO_PHYS (0x10000000) +#define INFRACFG_AO_BASE (IO_PHYS + 0x1000) +#define MCUCFG_BASE (IO_PHYS + 0x200000) +#define PERI_BASE (IO_PHYS + 0x1000000) + + +#define GPIO_BASE (IO_PHYS + 0x370000) +#define SPM_BASE (IO_PHYS + 0x6000) +#define RGU_BASE (MCUCFG_BASE + 0x11000) +#define PMIC_WRAP_BASE (IO_PHYS + 0x10000) + +#define TRNG_base (MCUCFG_BASE + 0x230000) +#define MT_GIC_BASE (0x10220000) +#define MCU_SYS_SIZE (0x700000) +#define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000) + +/* Aggregate of all devices in the first GB */ +#define MTK_DEV_RNG0_BASE IO_PHYS +#define MTK_DEV_RNG0_SIZE 0x400000 +#define MTK_DEV_RNG1_BASE (PERI_BASE) +#define MTK_DEV_RNG1_SIZE 0x4000000 + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define UART0_BASE (PERI_BASE + 0x2000) + +#define UART_BAUDRATE (921600) +#define UART_CLOCK (26000000) + +/******************************************************************************* + * System counter frequency related constants + ******************************************************************************/ +#define SYS_COUNTER_FREQ_IN_TICKS 13000000 +#define SYS_COUNTER_FREQ_IN_MHZ (SYS_COUNTER_FREQ_IN_TICKS/1000000) + +/******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ + +/* Base MTK_platform compatible GIC memory map */ +#define BASE_GICD_BASE (MT_GIC_BASE+0x1000) +#define BASE_GICC_BASE (MT_GIC_BASE + 0x2000) +#define BASE_GICR_BASE (MT_GIC_BASE + 0x200000) +#define BASE_GICH_BASE (MT_GIC_BASE + 0x4000) +#define BASE_GICV_BASE (MT_GIC_BASE + 0x6000) + +#define INT_POL_CTL0 0x10200620 +#define GIC_PRIVATE_SIGNALS (32) + +/******************************************************************************* + * CCI-400 related constants + ******************************************************************************/ +#define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4 +#define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3 + +/******************************************************************************* + * WDT Registers + ******************************************************************************/ +#define MTK_WDT_BASE (RGU_BASE) +#define MTK_WDT_SIZE (0x1000) +#define MTK_WDT_MODE (MTK_WDT_BASE+0x0000) +#define MTK_WDT_LENGTH (MTK_WDT_BASE+0x0004) +#define MTK_WDT_RESTART (MTK_WDT_BASE+0x0008) +#define MTK_WDT_STATUS (MTK_WDT_BASE+0x000C) +#define MTK_WDT_INTERVAL (MTK_WDT_BASE+0x0010) +#define MTK_WDT_SWRST (MTK_WDT_BASE+0x0014) +#define MTK_WDT_SWSYSRST (MTK_WDT_BASE+0x0018) +#define MTK_WDT_NONRST_REG (MTK_WDT_BASE+0x0020) +#define MTK_WDT_NONRST_REG2 (MTK_WDT_BASE+0x0024) +#define MTK_WDT_REQ_MODE (MTK_WDT_BASE+0x0030) +#define MTK_WDT_REQ_IRQ_EN (MTK_WDT_BASE+0x0034) +#define MTK_WDT_DEBUG_CTL (MTK_WDT_BASE+0x0040) + +/*WDT_STATUS*/ +#define MTK_WDT_STATUS_HWWDT_RST (0x80000000) +#define MTK_WDT_STATUS_SWWDT_RST (0x40000000) +#define MTK_WDT_STATUS_IRQWDT_RST (0x20000000) +#define MTK_WDT_STATUS_DEBUGWDT_RST (0x00080000) +#define MTK_WDT_STATUS_SPMWDT_RST (0x0002) +#define MTK_WDT_STATUS_SPM_THERMAL_RST (0x0001) +#define MTK_WDT_STATUS_THERMAL_DIRECT_RST (1<<18) +#define MTK_WDT_STATUS_SECURITY_RST (1<<28) + +#define MTK_WDT_MODE_DUAL_MODE 0x0040 +#define MTK_WDT_MODE_IRQ 0x0008 +#define MTK_WDT_MODE_KEY 0x22000000 +#define MTK_WDT_MODE_EXTEN 0x0004 +#define MTK_WDT_SWRST_KEY 0x1209 +#define MTK_WDT_RESTART_KEY (0x1971) + +/* FIQ platform related define */ +#define MT_IRQ_SEC_SGI_0 8 +#define MT_IRQ_SEC_SGI_1 9 +#define MT_IRQ_SEC_SGI_2 10 +#define MT_IRQ_SEC_SGI_3 11 +#define MT_IRQ_SEC_SGI_4 12 +#define MT_IRQ_SEC_SGI_5 13 +#define MT_IRQ_SEC_SGI_6 14 +#define MT_IRQ_SEC_SGI_7 15 + +#define FIQ_SMP_CALL_SGI MT_IRQ_SEC_SGI_5 + +#define PLAT_ARM_G0_IRQS FIQ_SMP_CALL_SGI + +#define DEBUG_XLAT_TABLE 0 + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#if DEBUG_XLAT_TABLE +#define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL1 +#define PLATFORM_STACK_SIZE 0x440 +#elif IMAGE_BL2 +#define PLATFORM_STACK_SIZE 0x400 +#elif IMAGE_BL31 +#define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL32 +#define PLATFORM_STACK_SIZE 0x440 +#endif + +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" +#if ENABLE_PLAT_COMPAT +#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 +#else +#define PLAT_MAX_PWR_LVL 2 /* MPIDR_AFFLVL2 */ +#endif + +#define PLATFORM_CACHE_LINE_SIZE 64 +#define PLATFORM_SYSTEM_COUNT 1 +#define PLATFORM_CLUSTER_COUNT 2 +#define PLATFORM_CLUSTER0_CORE_COUNT 4 +#define PLATFORM_CLUSTER1_CORE_COUNT 4 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ + PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ + PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +/* ATF Argument */ +#define ATF_ARG_SIZE (0x800) + +/* TF txet, ro, rw, internal SRAM, Size: release: 80KB, debug: 92KB */ +#define TZRAM_BASE (0x110000) +#if DEBUG +#define TZRAM_SIZE (0x1C400) +#else +#define TZRAM_SIZE (0x1C400) +#endif +#define TZRAM2_BASE 0x00100000 +#define TZRAM2_SIZE 0xDC00 +#define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE) + +#define RAM_CONSOLE_BASE 0x0012D000 +#define RAM_CONSOLE_SIZE 0x00001000 +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL3-1 debug size plus a + * little space for growth. + */ +#define BL31_BASE (TZRAM_BASE + 0x1000) +#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) +#define BSS1_STACK_LIMIT (TZRAM_BASE + TZRAM_SIZE) +#define BL31_TZRAM_SIZE (TZRAM_SIZE - ATF_ARG_SIZE) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define ADDR_SPACE_SIZE (1ull << 32) +#define MAX_XLAT_TABLES 7 +#define MAX_MMAP_REGIONS 16 + + +/******************************************************************************* + * CCI-400 related constants + ******************************************************************************/ +#define CCI400_BASE 0x10390000 +#define CCI400_SL_IFACE_CLUSTER0 4 +#define CCI400_SL_IFACE_CLUSTER1 3 +#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \ + CCI400_SL_IFACE_CLUSTER1 : \ + CCI400_SL_IFACE_CLUSTER0) +#define CCI_SEC_ACCESS_OFFSET (0x8) + + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#define BL32_BASE (0x0) + +/* + * Load address of BL3-3 for this platform port + */ +#define LK_SIZE_LIMIT (0x100000) +#define PLAT_MTK_NS_IMAGE_OFFSET (0x41E00000) +/* 16KB */ +#define ATF_AEE_BUFFER_SIZE (0x4000) +#define PAGE_SIZE_2MB_MASK (PAGE_SIZE_2MB - 1) +#define IS_PAGE_2MB_ALIGNED(addr) (((addr) & PAGE_SIZE_2MB_MASK) == 0) +#define PAGE_SIZE_2MB (1 << PAGE_SIZE_2MB_SHIFT) +#define PAGE_SIZE_2MB_SHIFT TWO_MB_SHIFT + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/power_tracer.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/power_tracer.h new file mode 100644 index 0000000..ab9390d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/power_tracer.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __POWER_TRACER_H__ +#define __POWER_TRACER_H__ + +#define CPU_UP 0 +#define CPU_DOWN 1 +#define CPU_SUSPEND 2 +#define CLUSTER_UP 3 +#define CLUSTER_DOWN 4 +#define CLUSTER_SUSPEND 5 + +void trace_power_flow(unsigned long mpidr, unsigned char mode); + +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/scu.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/scu.h new file mode 100644 index 0000000..e59fd43 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/scu.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SCU_H__ +#define __SCU_H__ + +void disable_scu(unsigned long mpidr); +void enable_scu(unsigned long mpidr); + +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/spm.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/spm.h new file mode 100644 index 0000000..32f8d8f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/include/spm.h @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SPM_H__ +#define __SPM_H__ + +#define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000) +#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010) +#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014) +#define SPM_CLK_SETTLE (SPM_BASE + 0x100) +#define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218) +#define SPM_CA7_CPU2_PWR_CON (SPM_BASE + 0x21c) +#define SPM_CA7_CPU3_PWR_CON (SPM_BASE + 0x220) +#define SPM_CA7_CPU1_L1_PDN (SPM_BASE + 0x264) +#define SPM_CA7_CPU2_L1_PDN (SPM_BASE + 0x26c) +#define SPM_CA7_CPU3_L1_PDN (SPM_BASE + 0x274) +#define SPM_MD32_SRAM_CON (SPM_BASE + 0x2c8) +#define SPM_PCM_CON0 (SPM_BASE + 0x310) +#define SPM_PCM_CON1 (SPM_BASE + 0x314) +#define SPM_PCM_IM_PTR (SPM_BASE + 0x318) +#define SPM_PCM_IM_LEN (SPM_BASE + 0x31c) +#define SPM_PCM_REG_DATA_INI (SPM_BASE + 0x320) +#define SPM_PCM_EVENT_VECTOR0 (SPM_BASE + 0x340) +#define SPM_PCM_EVENT_VECTOR1 (SPM_BASE + 0x344) +#define SPM_PCM_EVENT_VECTOR2 (SPM_BASE + 0x348) +#define SPM_PCM_EVENT_VECTOR3 (SPM_BASE + 0x34c) +#define SPM_PCM_MAS_PAUSE_MASK (SPM_BASE + 0x354) +#define SPM_PCM_PWR_IO_EN (SPM_BASE + 0x358) +#define SPM_PCM_TIMER_VAL (SPM_BASE + 0x35c) +#define SPM_PCM_TIMER_OUT (SPM_BASE + 0x360) +#define SPM_PCM_REG0_DATA (SPM_BASE + 0x380) +#define SPM_PCM_REG1_DATA (SPM_BASE + 0x384) +#define SPM_PCM_REG2_DATA (SPM_BASE + 0x388) +#define SPM_PCM_REG3_DATA (SPM_BASE + 0x38c) +#define SPM_PCM_REG4_DATA (SPM_BASE + 0x390) +#define SPM_PCM_REG5_DATA (SPM_BASE + 0x394) +#define SPM_PCM_REG6_DATA (SPM_BASE + 0x398) +#define SPM_PCM_REG7_DATA (SPM_BASE + 0x39c) +#define SPM_PCM_REG8_DATA (SPM_BASE + 0x3a0) +#define SPM_PCM_REG9_DATA (SPM_BASE + 0x3a4) +#define SPM_PCM_REG10_DATA (SPM_BASE + 0x3a8) +#define SPM_PCM_REG11_DATA (SPM_BASE + 0x3ac) +#define SPM_PCM_REG12_DATA (SPM_BASE + 0x3b0) +#define SPM_PCM_REG13_DATA (SPM_BASE + 0x3b4) +#define SPM_PCM_REG14_DATA (SPM_BASE + 0x3b8) +#define SPM_PCM_REG15_DATA (SPM_BASE + 0x3bc) +#define SPM_PCM_EVENT_REG_STA (SPM_BASE + 0x3c0) +#define SPM_PCM_FSM_STA (SPM_BASE + 0x3c4) +#define SPM_PCM_IM_HOST_RW_PTR (SPM_BASE + 0x3c8) +#define SPM_PCM_IM_HOST_RW_DAT (SPM_BASE + 0x3cc) +#define SPM_PCM_EVENT_VECTOR4 (SPM_BASE + 0x3d0) +#define SPM_PCM_EVENT_VECTOR5 (SPM_BASE + 0x3d4) +#define SPM_PCM_EVENT_VECTOR6 (SPM_BASE + 0x3d8) +#define SPM_PCM_EVENT_VECTOR7 (SPM_BASE + 0x3dc) +#define SPM_PCM_SW_INT_SET (SPM_BASE + 0x3e0) +#define SPM_PCM_SW_INT_CLEAR (SPM_BASE + 0x3e4) +#define SPM_CLK_CON (SPM_BASE + 0x400) +#define SPM_SLEEP_PTPOD2_CON (SPM_BASE + 0x408) +#define SPM_APMCU_PWRCTL (SPM_BASE + 0x600) +#define SPM_AP_DVFS_CON_SET (SPM_BASE + 0x604) +#define SPM_AP_STANBY_CON (SPM_BASE + 0x608) +#define SPM_PWR_STATUS (SPM_BASE + 0x60c) +#define SPM_PWR_STATUS_2ND (SPM_BASE + 0x610) +#define SPM_AP_BSI_REQ (SPM_BASE + 0x614) +#define SPM_SLEEP_TIMER_STA (SPM_BASE + 0x720) +#define SPM_SLEEP_WAKEUP_EVENT_MASK (SPM_BASE + 0x810) +#define SPM_SLEEP_CPU_WAKEUP_EVENT (SPM_BASE + 0x814) +#define SPM_SLEEP_MD32_WAKEUP_EVENT_MASK (SPM_BASE + 0x818) +#define SPM_PCM_WDT_TIMER_VAL (SPM_BASE + 0x824) +#define SPM_PCM_WDT_TIMER_OUT (SPM_BASE + 0x828) +#define SPM_PCM_MD32_MAILBOX (SPM_BASE + 0x830) +#define SPM_PCM_MD32_IRQ (SPM_BASE + 0x834) +#define SPM_SLEEP_ISR_MASK (SPM_BASE + 0x900) +#define SPM_SLEEP_ISR_STATUS (SPM_BASE + 0x904) +#define SPM_SLEEP_ISR_RAW_STA (SPM_BASE + 0x910) +#define SPM_SLEEP_MD32_ISR_RAW_STA (SPM_BASE + 0x914) +#define SPM_SLEEP_WAKEUP_MISC (SPM_BASE + 0x918) +#define SPM_SLEEP_BUS_PROTECT_RDY (SPM_BASE + 0x91c) +#define SPM_SLEEP_SUBSYS_IDLE_STA (SPM_BASE + 0x920) +#define SPM_PCM_RESERVE (SPM_BASE + 0xb00) +#define SPM_PCM_RESERVE2 (SPM_BASE + 0xb04) +#define SPM_PCM_FLAGS (SPM_BASE + 0xb08) +#define SPM_PCM_SRC_REQ (SPM_BASE + 0xb0c) +#define SPM_PCM_DEBUG_CON (SPM_BASE + 0xb20) +#define SPM_CA7_CPU0_IRQ_MASK (SPM_BASE + 0xb30) +#define SPM_CA7_CPU1_IRQ_MASK (SPM_BASE + 0xb34) +#define SPM_CA7_CPU2_IRQ_MASK (SPM_BASE + 0xb38) +#define SPM_CA7_CPU3_IRQ_MASK (SPM_BASE + 0xb3c) +#define SPM_CA15_CPU0_IRQ_MASK (SPM_BASE + 0xb40) +#define SPM_CA15_CPU1_IRQ_MASK (SPM_BASE + 0xb44) +#define SPM_CA15_CPU2_IRQ_MASK (SPM_BASE + 0xb48) +#define SPM_CA15_CPU3_IRQ_MASK (SPM_BASE + 0xb4c) +#define SPM_PCM_PASR_DPD_0 (SPM_BASE + 0xb60) +#define SPM_PCM_PASR_DPD_1 (SPM_BASE + 0xb64) +#define SPM_PCM_PASR_DPD_2 (SPM_BASE + 0xb68) +#define SPM_PCM_PASR_DPD_3 (SPM_BASE + 0xb6c) +#define SPM_SLEEP_CA7_WFI0_EN (SPM_BASE + 0xf00) +#define SPM_SLEEP_CA7_WFI1_EN (SPM_BASE + 0xf04) +#define SPM_SLEEP_CA7_WFI2_EN (SPM_BASE + 0xf08) +#define SPM_SLEEP_CA7_WFI3_EN (SPM_BASE + 0xf0c) +#define SPM_SLEEP_CA15_WFI0_EN (SPM_BASE + 0xf10) +#define SPM_SLEEP_CA15_WFI1_EN (SPM_BASE + 0xf14) +#define SPM_SLEEP_CA15_WFI2_EN (SPM_BASE + 0xf18) +#define SPM_SLEEP_CA15_WFI3_EN (SPM_BASE + 0xf1c) + +#define SPM_PROJECT_CODE 0xb16 + +#define SPM_REGWR_EN (1U << 0) +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +#define SPM_CPU_PDN_DIS (1U << 0) +#define SPM_INFRA_PDN_DIS (1U << 1) +#define SPM_DDRPHY_PDN_DIS (1U << 2) +#define SPM_DUALVCORE_PDN_DIS (1U << 3) +#define SPM_PASR_DIS (1U << 4) +#define SPM_DPD_DIS (1U << 5) +#define SPM_SODI_DIS (1U << 6) +#define SPM_MEMPLL_RESET (1U << 7) +#define SPM_MAINPLL_PDN_DIS (1U << 8) +#define SPM_CPU_DVS_DIS (1U << 9) +#define SPM_CPU_DORMANT (1U << 10) +#define SPM_EXT_VSEL_GPIO103 (1U << 11) +#define SPM_DDR_HIGH_SPEED (1U << 12) +#define SPM_OPT (1U << 13) + +#define POWER_ON_VAL1_DEF 0x01011820 +#define PCM_FSM_STA_DEF 0x48490 +#define PCM_END_FSM_STA_DEF 0x08490 +#define PCM_END_FSM_STA_MASK 0x3fff0 +#define PCM_HANDSHAKE_SEND1 0xbeefbeef + +#define PCM_WDT_TIMEOUT (30 * 32768) +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) + +#define CON0_PCM_KICK (1U << 0) +#define CON0_IM_KICK (1U << 1) +#define CON0_IM_SLEEP_DVS (1U << 3) +#define CON0_PCM_SW_RESET (1U << 15) +#define CON0_CFG_KEY (SPM_PROJECT_CODE << 16) + +#define CON1_IM_SLAVE (1U << 0) +#define CON1_MIF_APBEN (1U << 3) +#define CON1_PCM_TIMER_EN (1U << 5) +#define CON1_IM_NONRP_EN (1U << 6) +#define CON1_PCM_WDT_EN (1U << 8) +#define CON1_PCM_WDT_WAKE_MODE (1U << 9) +#define CON1_SPM_SRAM_SLP_B (1U << 10) +#define CON1_SPM_SRAM_ISO_B (1U << 11) +#define CON1_EVENT_LOCK_EN (1U << 12) +#define CON1_CFG_KEY (SPM_PROJECT_CODE << 16) + +#define PCM_PWRIO_EN_R0 (1U << 0) +#define PCM_PWRIO_EN_R7 (1U << 7) +#define PCM_RF_SYNC_R0 (1U << 16) +#define PCM_RF_SYNC_R2 (1U << 18) +#define PCM_RF_SYNC_R6 (1U << 22) +#define PCM_RF_SYNC_R7 (1U << 23) + +#define CC_SYSCLK0_EN_0 (1U << 0) +#define CC_SYSCLK0_EN_1 (1U << 1) +#define CC_SYSCLK1_EN_0 (1U << 2) +#define CC_SYSCLK1_EN_1 (1U << 3) +#define CC_SYSSETTLE_SEL (1U << 4) +#define CC_LOCK_INFRA_DCM (1U << 5) +#define CC_SRCLKENA_MASK_0 (1U << 6) +#define CC_CXO32K_RM_EN_MD1 (1U << 9) +#define CC_CXO32K_RM_EN_MD2 (1U << 10) +#define CC_CLKSQ1_SEL (1U << 12) +#define CC_DISABLE_DORM_PWR (1U << 14) +#define CC_MD32_DCM_EN (1U << 18) + +#define WFI_OP_AND 1 +#define WFI_OP_OR 0 + +#define WAKE_MISC_PCM_TIMER (1U << 19) +#define WAKE_MISC_CPU_WAKE (1U << 20) + +/* define WAKE_SRC_XXX */ +#define WAKE_SRC_SPM_MERGE (1 << 0) +#define WAKE_SRC_KP (1 << 2) +#define WAKE_SRC_WDT (1 << 3) +#define WAKE_SRC_GPT (1 << 4) +#define WAKE_SRC_EINT (1 << 6) +#define WAKE_SRC_LOW_BAT (1 << 9) +#define WAKE_SRC_MD32 (1 << 10) +#define WAKE_SRC_USB_CD (1 << 14) +#define WAKE_SRC_USB_PDN (1 << 15) +#define WAKE_SRC_AFE (1 << 20) +#define WAKE_SRC_THERM (1 << 21) +#define WAKE_SRC_SYSPWREQ (1 << 24) +#define WAKE_SRC_SEJ (1 << 27) +#define WAKE_SRC_ALL_MD32 (1 << 28) +#define WAKE_SRC_CPU_IRQ (1 << 29) + +#endif /* __SPM_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/plat_delay_timer.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/plat_delay_timer.c new file mode 100644 index 0000000..797ce05 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/plat_delay_timer.c @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +static uint32_t plat_get_timer_value(void) +{ + /* + * Generic delay timer implementation expects the timer to be a down + * counter. We apply bitwise NOT operator to the tick values returned + * by read_cntpct_el0() to simulate the down counter. + */ + return (uint32_t)(~read_cntpct_el0()); +} + +static const timer_ops_t plat_timer_ops = { + .get_timer_value = plat_get_timer_value, + .clk_mult = 1, + .clk_div = SYS_COUNTER_FREQ_IN_MHZ, +}; + +void plat_delay_timer_init(void) +{ + timer_init(&plat_timer_ops); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/plat_mt_gic.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/plat_mt_gic.c new file mode 100644 index 0000000..8679d07 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/plat_mt_gic.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +const unsigned int g0_interrupt_array[] = { + PLAT_ARM_G0_IRQS +}; + +gicv2_driver_data_t arm_gic_data = { + .gicd_base = BASE_GICD_BASE, + .gicc_base = BASE_GICC_BASE, + .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), + .g0_interrupt_array = g0_interrupt_array, +}; + +void plat_mt_gic_driver_init(void) +{ + gicv2_driver_init(&arm_gic_data); +} + +void plat_mt_gic_init(void) +{ + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +void plat_mt_gic_cpuif_enable(void) +{ + gicv2_cpuif_enable(); +} + +void plat_mt_gic_cpuif_disable(void) +{ + gicv2_cpuif_disable(); +} + +void plat_mt_gic_pcpu_init(void) +{ + gicv2_pcpu_distif_init(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/plat_pm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/plat_pm.c new file mode 100644 index 0000000..96fdab0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/plat_pm.c @@ -0,0 +1,495 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct core_context { + unsigned long timer_data[8]; + unsigned int count; + unsigned int rst; + unsigned int abt; + unsigned int brk; +}; + +struct cluster_context { + struct core_context core[PLATFORM_MAX_CPUS_PER_CLUSTER]; +}; + +/* + * Top level structure to hold the complete context of a multi cluster system + */ +struct system_context { + struct cluster_context cluster[PLATFORM_CLUSTER_COUNT]; +}; + +/* + * Top level structure which encapsulates the context of the entire system + */ +static struct system_context dormant_data[1]; + +static inline struct cluster_context *system_cluster( + struct system_context *system, + uint32_t clusterid) +{ + return &system->cluster[clusterid]; +} + +static inline struct core_context *cluster_core(struct cluster_context *cluster, + uint32_t cpuid) +{ + return &cluster->core[cpuid]; +} + +static struct cluster_context *get_cluster_data(unsigned long mpidr) +{ + uint32_t clusterid; + + clusterid = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; + + return system_cluster(dormant_data, clusterid); +} + +static struct core_context *get_core_data(unsigned long mpidr) +{ + struct cluster_context *cluster; + uint32_t cpuid; + + cluster = get_cluster_data(mpidr); + cpuid = mpidr & MPIDR_CPU_MASK; + + return cluster_core(cluster, cpuid); +} + +static void mt_save_generic_timer(unsigned long *container) +{ + uint64_t ctl; + uint64_t val; + + __asm__ volatile("mrs %x0, cntkctl_el1\n\t" + "mrs %x1, cntp_cval_el0\n\t" + "stp %x0, %x1, [%2, #0]" + : "=&r" (ctl), "=&r" (val) + : "r" (container) + : "memory"); + + __asm__ volatile("mrs %x0, cntp_tval_el0\n\t" + "mrs %x1, cntp_ctl_el0\n\t" + "stp %x0, %x1, [%2, #16]" + : "=&r" (val), "=&r" (ctl) + : "r" (container) + : "memory"); + + __asm__ volatile("mrs %x0, cntv_tval_el0\n\t" + "mrs %x1, cntv_ctl_el0\n\t" + "stp %x0, %x1, [%2, #32]" + : "=&r" (val), "=&r" (ctl) + : "r" (container) + : "memory"); +} + +static void mt_restore_generic_timer(unsigned long *container) +{ + uint64_t ctl; + uint64_t val; + + __asm__ volatile("ldp %x0, %x1, [%2, #0]\n\t" + "msr cntkctl_el1, %x0\n\t" + "msr cntp_cval_el0, %x1" + : "=&r" (ctl), "=&r" (val) + : "r" (container) + : "memory"); + + __asm__ volatile("ldp %x0, %x1, [%2, #16]\n\t" + "msr cntp_tval_el0, %x0\n\t" + "msr cntp_ctl_el0, %x1" + : "=&r" (val), "=&r" (ctl) + : "r" (container) + : "memory"); + + __asm__ volatile("ldp %x0, %x1, [%2, #32]\n\t" + "msr cntv_tval_el0, %x0\n\t" + "msr cntv_ctl_el0, %x1" + : "=&r" (val), "=&r" (ctl) + : "r" (container) + : "memory"); +} + +static void stop_generic_timer(void) +{ + /* + * Disable the timer and mask the irq to prevent + * suprious interrupts on this cpu interface. It + * will bite us when we come back if we don't. It + * will be replayed on the inbound cluster. + */ + uint64_t cntpctl = read_cntp_ctl_el0(); + + write_cntp_ctl_el0(clr_cntp_ctl_enable(cntpctl)); +} + +static void mt_cpu_save(unsigned long mpidr) +{ + struct core_context *core; + + core = get_core_data(mpidr); + mt_save_generic_timer(core->timer_data); + + /* disable timer irq, and upper layer should enable it again. */ + stop_generic_timer(); +} + +static void mt_cpu_restore(unsigned long mpidr) +{ + struct core_context *core; + + core = get_core_data(mpidr); + mt_restore_generic_timer(core->timer_data); +} + +static void mt_platform_save_context(unsigned long mpidr) +{ + /* mcusys_save_context: */ + mt_cpu_save(mpidr); +} + +static void mt_platform_restore_context(unsigned long mpidr) +{ + /* mcusys_restore_context: */ + mt_cpu_restore(mpidr); +} + +/******************************************************************************* +* Private function which is used to determine if any platform actions +* should be performed for the specified affinity instance given its +* state. Nothing needs to be done if the 'state' is not off or if this is not +* the highest affinity level which will enter the 'state'. +*******************************************************************************/ +static int32_t plat_do_plat_actions(unsigned int afflvl, unsigned int state) +{ + unsigned int max_phys_off_afflvl; + + assert(afflvl <= MPIDR_AFFLVL2); + + if (state != PSCI_STATE_OFF) + return -EAGAIN; + + /* + * Find the highest affinity level which will be suspended and postpone + * all the platform specific actions until that level is hit. + */ + max_phys_off_afflvl = psci_get_max_phys_off_afflvl(); + assert(max_phys_off_afflvl != PSCI_INVALID_DATA); + if (afflvl != max_phys_off_afflvl) + return -EAGAIN; + + return 0; +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance is about to enter + * standby. + ******************************************************************************/ +static void plat_affinst_standby(unsigned int power_state) +{ + unsigned int target_afflvl; + + /* Sanity check the requested state */ + target_afflvl = psci_get_pstate_afflvl(power_state); + + /* + * It's possible to enter standby only on affinity level 0 i.e. a cpu + * on the MTK_platform. Ignore any other affinity level. + */ + if (target_afflvl == MPIDR_AFFLVL0) { + /* + * Enter standby state. dsb is good practice before using wfi + * to enter low power states. + */ + dsb(); + wfi(); + } +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance is about to be turned + * on. The level and mpidr determine the affinity instance. + ******************************************************************************/ +static int plat_affinst_on(unsigned long mpidr, + unsigned long sec_entrypoint, + unsigned int afflvl, + unsigned int state) +{ + int rc = PSCI_E_SUCCESS; + unsigned long cpu_id; + unsigned long cluster_id; + uintptr_t rv; + + /* + * It's possible to turn on only affinity level 0 i.e. a cpu + * on the MTK_platform. Ignore any other affinity level. + */ + if (afflvl != MPIDR_AFFLVL0) + return rc; + + cpu_id = mpidr & MPIDR_CPU_MASK; + cluster_id = mpidr & MPIDR_CLUSTER_MASK; + + if (cluster_id) + rv = (uintptr_t)&mt6795_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw; + else + rv = (uintptr_t)&mt6795_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw; + + mmio_write_32(rv, sec_entrypoint); + INFO("mt_on[%ld:%ld], entry %x\n", + cluster_id, cpu_id, mmio_read_32(rv)); + + return rc; +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance is about to be turned + * off. The level and mpidr determine the affinity instance. The 'state' arg. + * allows the platform to decide whether the cluster is being turned off and + * take apt actions. + * + * CAUTION: This function is called with coherent stacks so that caches can be + * turned off, flushed and coherency disabled. There is no guarantee that caches + * will remain turned on across calls to this function as each affinity level is + * dealt with. So do not write & read global variables across calls. It will be + * wise to do flush a write to the global to prevent unpredictable results. + ******************************************************************************/ +static void plat_affinst_off(unsigned int afflvl, unsigned int state) +{ + unsigned long mpidr = read_mpidr_el1(); + + /* Determine if any platform actions need to be executed. */ + if (plat_do_plat_actions(afflvl, state) == -EAGAIN) + return; + + /* Prevent interrupts from spuriously waking up this cpu */ + plat_mt_gic_cpuif_disable(); + + trace_power_flow(mpidr, CPU_DOWN); + + if (afflvl != MPIDR_AFFLVL0) { + /* Disable coherency if this cluster is to be turned off */ + plat_cci_disable(); + + trace_power_flow(mpidr, CLUSTER_DOWN); + } +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance is about to be + * suspended. The level and mpidr determine the affinity instance. The 'state' + * arg. allows the platform to decide whether the cluster is being turned off + * and take apt actions. + * + * CAUTION: This function is called with coherent stacks so that caches can be + * turned off, flushed and coherency disabled. There is no guarantee that caches + * will remain turned on across calls to this function as each affinity level is + * dealt with. So do not write & read global variables across calls. It will be + * wise to do flush a write to the global to prevent unpredictable results. + ******************************************************************************/ +static void plat_affinst_suspend(unsigned long sec_entrypoint, + unsigned int afflvl, + unsigned int state) +{ + unsigned long mpidr = read_mpidr_el1(); + unsigned long cluster_id; + unsigned long cpu_id; + uintptr_t rv; + + /* Determine if any platform actions need to be executed. */ + if (plat_do_plat_actions(afflvl, state) == -EAGAIN) + return; + + cpu_id = mpidr & MPIDR_CPU_MASK; + cluster_id = mpidr & MPIDR_CLUSTER_MASK; + + if (cluster_id) + rv = (uintptr_t)&mt6795_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw; + else + rv = (uintptr_t)&mt6795_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw; + + mmio_write_32(rv, sec_entrypoint); + + if (afflvl >= MPIDR_AFFLVL0) + mt_platform_save_context(mpidr); + + /* Perform the common cluster specific operations */ + if (afflvl >= MPIDR_AFFLVL1) { + /* Disable coherency if this cluster is to be turned off */ + plat_cci_disable(); + disable_scu(mpidr); + + trace_power_flow(mpidr, CLUSTER_SUSPEND); + } + + if (afflvl >= MPIDR_AFFLVL2) { + /* Prevent interrupts from spuriously waking up this cpu */ + plat_mt_gic_cpuif_disable(); + } +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance has just been powered + * on after being turned off earlier. The level and mpidr determine the affinity + * instance. The 'state' arg. allows the platform to decide whether the cluster + * was turned off prior to wakeup and do what's necessary to setup it up + * correctly. + ******************************************************************************/ +static void plat_affinst_on_finish(unsigned int afflvl, unsigned int state) +{ + unsigned long mpidr = read_mpidr_el1(); + + /* Determine if any platform actions need to be executed. */ + if (plat_do_plat_actions(afflvl, state) == -EAGAIN) + return; + + /* Perform the common cluster specific operations */ + if (afflvl >= MPIDR_AFFLVL1) { + enable_scu(mpidr); + + /* Enable coherency if this cluster was off */ + plat_cci_enable(); + trace_power_flow(mpidr, CLUSTER_UP); + } + + /* Enable the gic cpu interface */ + plat_mt_gic_cpuif_enable(); + plat_mt_gic_pcpu_init(); + trace_power_flow(mpidr, CPU_UP); +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance has just been powered + * on after having been suspended earlier. The level and mpidr determine the + * affinity instance. + ******************************************************************************/ +static void plat_affinst_suspend_finish(unsigned int afflvl, unsigned int state) +{ + unsigned long mpidr = read_mpidr_el1(); + + /* Determine if any platform actions need to be executed. */ + if (plat_do_plat_actions(afflvl, state) == -EAGAIN) + return; + + if (afflvl >= MPIDR_AFFLVL2) { + /* Enable the gic cpu interface */ + plat_mt_gic_init(); + plat_mt_gic_cpuif_enable(); + } + + /* Perform the common cluster specific operations */ + if (afflvl >= MPIDR_AFFLVL1) { + enable_scu(mpidr); + + /* Enable coherency if this cluster was off */ + plat_cci_enable(); + trace_power_flow(mpidr, CLUSTER_UP); + } + + if (afflvl >= MPIDR_AFFLVL0) + mt_platform_restore_context(mpidr); + + plat_mt_gic_pcpu_init(); +} + +static unsigned int plat_get_sys_suspend_power_state(void) +{ + /* StateID: 0, StateType: 1(power down), PowerLevel: 2(system) */ + return psci_make_powerstate(0, 1, 2); +} + +/******************************************************************************* + * MTK handlers to shutdown/reboot the system + ******************************************************************************/ +static void __dead2 plat_system_off(void) +{ + INFO("MTK System Off\n"); + wfi(); + ERROR("MTK System Off: operation not handled.\n"); + panic(); +} + +static void __dead2 plat_system_reset(void) +{ + /* Write the System Configuration Control Register */ + INFO("MTK System Reset\n"); + + mmio_clrbits_32(MTK_WDT_BASE, + (MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ)); + mmio_setbits_32(MTK_WDT_BASE, (MTK_WDT_MODE_KEY | MTK_WDT_MODE_EXTEN)); + mmio_setbits_32(MTK_WDT_SWRST, MTK_WDT_SWRST_KEY); + + wfi(); + ERROR("MTK System Reset: operation not handled.\n"); + panic(); +} + +/******************************************************************************* + * Export the platform handlers to enable psci to invoke them + ******************************************************************************/ +static const plat_pm_ops_t plat_plat_pm_ops = { + .affinst_standby = plat_affinst_standby, + .affinst_on = plat_affinst_on, + .affinst_off = plat_affinst_off, + .affinst_suspend = plat_affinst_suspend, + .affinst_on_finish = plat_affinst_on_finish, + .affinst_suspend_finish = plat_affinst_suspend_finish, + .system_off = plat_system_off, + .system_reset = plat_system_reset, + .get_sys_suspend_power_state = plat_get_sys_suspend_power_state, +}; + +/******************************************************************************* + * Export the platform specific power ops & initialize the mtk_platform power + * controller + ******************************************************************************/ +int platform_setup_pm(const plat_pm_ops_t **plat_ops) +{ + *plat_ops = &plat_plat_pm_ops; + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/plat_topology.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/plat_topology.c new file mode 100644 index 0000000..b1feac0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/plat_topology.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr) +{ + /* Report 1 (absent) instance at levels higher that the cluster level */ + if (aff_lvl > MPIDR_AFFLVL1) + return PLATFORM_SYSTEM_COUNT; + + if (aff_lvl == MPIDR_AFFLVL1) + return PLATFORM_CLUSTER_COUNT; + + return mpidr & 0x100 ? PLATFORM_CLUSTER1_CORE_COUNT : + PLATFORM_CLUSTER0_CORE_COUNT; +} + +unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr) +{ + return aff_lvl <= MPIDR_AFFLVL2 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT; +} + +int mt_setup_topology(void) +{ + /* [TODO] Make topology configurable via SCC */ + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/platform.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/platform.mk new file mode 100644 index 0000000..e105dfe --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/platform.mk @@ -0,0 +1,94 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +MTK_PLAT := plat/mediatek +MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} + +# Add OEM customized codes +OEMS := true +MTK_SIP_KERNEL_BOOT_ENABLE := 1 + + +ifneq (${OEMS},none) + OEMS_INCLUDES := -I${MTK_PLAT}/common/custom/ + OEMS_SOURCES := ${MTK_PLAT}/common/custom/oem_svc.c +endif + +PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ + -I${MTK_PLAT}/common/drivers/uart \ + -I${MTK_PLAT_SOC}/ \ + -I${MTK_PLAT_SOC}/drivers/timer/ \ + -I${MTK_PLAT_SOC}/include/ \ + -Iinclude/plat/arm/common/ \ + -Iinclude/common/tbbr/ \ + ${OEMS_INCLUDES} + +PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \ + plat/common/aarch64/plat_common.c \ + plat/common/plat_gic.c + +BL31_SOURCES += drivers/arm/cci/cci.c \ + drivers/delay_timer/generic_delay_timer.c \ + drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c \ + drivers/console/console.S \ + drivers/delay_timer/delay_timer.c \ + lib/cpus/aarch64/cortex_a53.S \ + plat/common/aarch64/platform_mp_stack.S \ + ${MTK_PLAT_SOC}/bl31_plat_setup.c \ + ${MTK_PLAT_SOC}/plat_mt_gic.c \ + ${MTK_PLAT}/common/mtk_sip_svc.c \ + ${MTK_PLAT}/common/mtk_plat_common.c \ + ${MTK_PLAT}/common/drivers/uart/8250_console.S \ + ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ + ${MTK_PLAT_SOC}/drivers/timer/mt_cpuxgpt.c \ + ${MTK_PLAT_SOC}/plat_delay_timer.c \ + ${MTK_PLAT_SOC}/plat_pm.c \ + ${MTK_PLAT_SOC}/plat_topology.c \ + ${MTK_PLAT_SOC}/power_tracer.c \ + ${MTK_PLAT_SOC}/scu.c \ + ${OEMS_SOURCES} + +# Flag used by the MTK_platform port to determine the version of ARM GIC +# architecture to use for interrupt management in EL3. +ARM_GIC_ARCH := 2 +$(eval $(call add_define,ARM_GIC_ARCH)) + +# Enable workarounds for selected Cortex-A53 erratas. +ERRATA_A53_826319 := 1 +ERRATA_A53_836870 := 1 + +# indicate the reset vector address can be programmed +PROGRAMMABLE_RESET_ADDRESS := 1 + +$(eval $(call add_define,MTK_SIP_KERNEL_BOOT_ENABLE)) + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/power_tracer.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/power_tracer.c new file mode 100644 index 0000000..e6ea434 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/power_tracer.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#define trace_log(...) INFO("psci: " __VA_ARGS__) + +void trace_power_flow(unsigned long mpidr, unsigned char mode) +{ + switch (mode) { + case CPU_UP: + trace_log("core %ld:%ld ON\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, + (mpidr & MPIDR_CPU_MASK)); + break; + case CPU_DOWN: + trace_log("core %ld:%ld OFF\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, + (mpidr & MPIDR_CPU_MASK)); + break; + case CPU_SUSPEND: + trace_log("core %ld:%ld SUSPEND\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, + (mpidr & MPIDR_CPU_MASK)); + break; + case CLUSTER_UP: + trace_log("cluster %ld ON\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); + break; + case CLUSTER_DOWN: + trace_log("cluster %ld OFF\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); + break; + case CLUSTER_SUSPEND: + trace_log("cluster %ld SUSPEND\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); + break; + default: + trace_log("unknown power mode\n"); + break; + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/scu.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/scu.c new file mode 100644 index 0000000..1f4ae6e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt6795/scu.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +void disable_scu(unsigned long mpidr) +{ + if (mpidr & MPIDR_CLUSTER_MASK) + mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, + MP1_ACINACTM); + else + mmio_setbits_32((uintptr_t)&mt6795_mcucfg->mp0_axi_config, + MP0_ACINACTM); +} + +void enable_scu(unsigned long mpidr) +{ + if (mpidr & MPIDR_CLUSTER_MASK) + mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp1_miscdbg, + MP1_ACINACTM); + else + mmio_clrbits_32((uintptr_t)&mt6795_mcucfg->mp0_axi_config, + MP0_ACINACTM); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/aarch64/plat_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/aarch64/plat_helpers.S new file mode 100644 index 0000000..af3a407 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/aarch64/plat_helpers.S @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + + .globl plat_secondary_cold_boot_setup + .globl plat_report_exception + .globl platform_is_primary_cpu + .globl plat_crash_console_init + .globl plat_crash_console_putc + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* MT8173 Oak does not do cold boot for secondary CPU */ +cb_panic: + b cb_panic +endfunc plat_secondary_cold_boot_setup + +func platform_is_primary_cpu + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #MT8173_PRIMARY_CPU + cset x0, eq + ret +endfunc platform_is_primary_cpu + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0 - x4 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, MT8173_UART0_BASE + mov_imm x1, MT8173_UART_CLOCK + mov_imm x2, MT8173_BAUDRATE + b console_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(void) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, MT8173_UART0_BASE + b console_core_putc +endfunc plat_crash_console_putc diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/aarch64/platform_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/aarch64/platform_common.c new file mode 100644 index 0000000..70639ed --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/aarch64/platform_common.c @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static const int cci_map[] = { + PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX, + PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX +}; + +/* Table of regions to map using the MMU. */ +const mmap_region_t plat_mmap[] = { + /* for TF text, RO, RW */ + MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE, + MT_MEMORY | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + { 0 } + +}; + +/******************************************************************************* + * Macro generating the code for the function setting up the pagetables as per + * the platform memory map & initialize the mmu, for the given exception level + ******************************************************************************/ +#define DEFINE_CONFIGURE_MMU_EL(_el) \ + void plat_configure_mmu_el ## _el(unsigned long total_base, \ + unsigned long total_size, \ + unsigned long ro_start, \ + unsigned long ro_limit, \ + unsigned long coh_start, \ + unsigned long coh_limit) \ + { \ + mmap_add_region(total_base, total_base, \ + total_size, \ + MT_MEMORY | MT_RW | MT_SECURE); \ + mmap_add_region(ro_start, ro_start, \ + ro_limit - ro_start, \ + MT_MEMORY | MT_RO | MT_SECURE); \ + mmap_add_region(coh_start, coh_start, \ + coh_limit - coh_start, \ + MT_DEVICE | MT_RW | MT_SECURE); \ + mmap_add(plat_mmap); \ + init_xlat_tables(); \ + \ + enable_mmu_el ## _el(0); \ + } + +/* Define EL3 variants of the function initialising the MMU */ +DEFINE_CONFIGURE_MMU_EL(3) + +unsigned int plat_get_syscnt_freq2(void) +{ + return SYS_COUNTER_FREQ_IN_TICKS; +} + +void plat_cci_init(void) +{ + /* Initialize CCI driver */ + cci_init(PLAT_MT_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); +} + +void plat_cci_enable(void) +{ + /* + * Enable CCI coherency for this cluster. + * No need for locks as no other cpu is active at the moment. + */ + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); +} + +void plat_cci_disable(void) +{ + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/bl31_plat_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/bl31_plat_setup.c new file mode 100644 index 0000000..4626f81 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/bl31_plat_setup.c @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Declarations of linker defined symbols which will help us find the layout + * of trusted SRAM + ******************************************************************************/ +unsigned long __RO_START__; +unsigned long __RO_END__; + +unsigned long __COHERENT_RAM_START__; +unsigned long __COHERENT_RAM_END__; + +/* + * The next 3 constants identify the extents of the code, RO data region and the + * limit of the BL31 image. These addresses are used by the MMU setup code and + * therefore they must be page-aligned. It is the responsibility of the linker + * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_RO_BASE (unsigned long)(&__RO_START__) +#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +#define BL31_END (unsigned long)(&__BL31_END__) + +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) + +static entry_point_info_t bl32_ep_info; +static entry_point_info_t bl33_ep_info; + +static void platform_setup_cpu(void) +{ + /* turn off all the little core's power except cpu 0 */ + mtcmos_little_cpu_off(); + + /* setup big cores */ + mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res, + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK | + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK | + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK | + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK | + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK); + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS); + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div, + MP1_SW_CG_GEN); + mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl, + MP1_L2RSTDISABLE); + + /* set big cores arm64 boot mode */ + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg, + MP1_CPUCFG_64BIT); + + /* set LITTLE cores arm64 boot mode */ + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw, + MP0_CPUCFG_64BIT); + + /* enable dcm control */ + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->bus_fabric_dcm_ctrl, + ADB400_GRP_DCM_EN | CCI400_GRP_DCM_EN | ADBCLK_GRP_DCM_EN | + EMICLK_GRP_DCM_EN | ACLK_GRP_DCM_EN | L2C_IDLE_DCM_EN | + INFRACLK_PSYS_DYNAMIC_CG_EN); + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->l2c_sram_ctrl, + L2C_SRAM_DCM_EN); + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->cci_clk_ctrl, + MCU_BUS_DCM_EN); +} + +static void platform_setup_sram(void) +{ + /* protect BL31 memory from non-secure read/write access */ + mmio_write_32(SRAMROM_SEC_ADDR, (uint32_t)(BL31_END + 0x3ff) & 0x3fc00); + mmio_write_32(SRAMROM_SEC_CTRL, 0x10000ff9); +} + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; + + /* None of the images on this platform can have 0x0 as the entrypoint */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +/******************************************************************************* + * Perform any BL3-1 early platform setup. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they + * are lost (potentially). This needs to be done before the MMU is initialized + * so that the memory layout can be used while creating page tables. + * BL2 has flushed this information to memory, so we are guaranteed to pick up + * good data. + ******************************************************************************/ +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +{ + console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE); + + VERBOSE("bl31_setup\n"); + + assert(from_bl2 != NULL); + assert(from_bl2->h.type == PARAM_BL31); + assert(from_bl2->h.version >= VERSION_1); + + bl32_ep_info = *from_bl2->bl32_ep_info; + bl33_ep_info = *from_bl2->bl33_ep_info; +} + +/******************************************************************************* + * Perform any BL3-1 platform setup code + ******************************************************************************/ +void bl31_platform_setup(void) +{ + platform_setup_cpu(); + platform_setup_sram(); + + generic_delay_timer_init(); + + /* Initialize the gic cpu and distributor interfaces */ + plat_mt_gic_init(); + arm_gic_setup(); + + /* Topologies are best known to the platform. */ + mt_setup_topology(); + + /* Initialize spm at boot time */ + spm_boot_init(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the mmu in a quick and dirty way. + ******************************************************************************/ +void bl31_plat_arch_setup(void) +{ + plat_cci_init(); + plat_cci_enable(); + + plat_configure_mmu_el3(BL31_RO_BASE, + (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), + BL31_RO_BASE, + BL31_RO_LIMIT, + BL31_COHERENT_RAM_BASE, + BL31_COHERENT_RAM_LIMIT); +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/crypt/crypt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/crypt/crypt.c new file mode 100644 index 0000000..2fca0f5 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/crypt/crypt.c @@ -0,0 +1,144 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#define crypt_read32(offset) \ + mmio_read_32((uintptr_t)(CRYPT_BASE+((offset) * 4))) + +#define crypt_write32(offset, value) \ + mmio_write_32((uintptr_t)(CRYPT_BASE + ((offset) * 4)), (uint32_t)value) + +#define GET_L32(x) ((uint32_t)(x & 0xffffffff)) +#define GET_H32(x) ((uint32_t)((x >> 32) & 0xffffffff)) + +#define REG_INIT 0 +#define REG_MSC 4 +#define REG_TRIG 256 +#define REG_STAT 512 +#define REG_CLR 513 +#define REG_INT 514 +#define REG_P68 768 +#define REG_P69 769 +#define REG_P70 770 +#define REG_P71 771 +#define REG_P72 772 +#define REG_D20 820 +#define KEY_SIZE 160 +#define KEY_LEN 40 + +/* Wait until crypt is completed */ +uint64_t crypt_wait(void) +{ + crypt_write32(REG_TRIG, 0); + while (crypt_read32(REG_STAT) == 0) + ; + udelay(100); + crypt_write32(REG_CLR, crypt_read32(REG_STAT)); + crypt_write32(REG_INT, 0); + return MTK_SIP_E_SUCCESS; +} + +static uint32_t record[4]; +/* Copy encrypted key to crypt engine */ +uint64_t crypt_set_hdcp_key_ex(uint64_t x1, uint64_t x2, uint64_t x3) +{ + uint32_t i = (uint32_t)x1; + uint32_t j = 0; + + if (i > KEY_LEN) + return MTK_SIP_E_INVALID_PARAM; + + if (i < KEY_LEN) { + crypt_write32(REG_MSC, 0x80ff3800); + crypt_write32(REG_INIT, 0); + crypt_write32(REG_INIT, 0xF); + crypt_write32(REG_CLR, 1); + crypt_write32(REG_INT, 0); + + crypt_write32(REG_P68, 0x70); + crypt_write32(REG_P69, 0x1C0); + crypt_write32(REG_P70, 0x30); + crypt_write32(REG_P71, 0x4); + crypt_wait(); + + crypt_write32(REG_D20 + 4 * i, GET_L32(x2)); + crypt_write32(REG_D20 + 4 * i + 1, GET_H32(x2)); + crypt_write32(REG_D20 + 4 * i + 2, GET_L32(x3)); + crypt_write32(REG_D20 + 4 * i + 3, GET_H32(x3)); + + crypt_write32(REG_P69, 0); + crypt_write32(REG_P68, 0x20); + crypt_write32(REG_P71, 0x34 + 4 * i); + crypt_write32(REG_P72, 0x34 + 4 * i); + crypt_wait(); + + for (j = 0; j < 4; j++) { + crypt_write32(REG_P68, 0x71); + crypt_write32(REG_P69, 0x34 + 4 * i + j); + crypt_write32(REG_P70, record[j]); + crypt_wait(); + } + } + /* Prepare data for next iteration */ + record[0] = GET_L32(x2); + record[1] = GET_H32(x2); + record[2] = GET_L32(x3); + record[3] = GET_H32(x3); + return MTK_SIP_E_SUCCESS; +} + +/* Set key to hdcp */ +uint64_t crypt_set_hdcp_key_num(uint32_t num) +{ + if (num > KEY_LEN) + return MTK_SIP_E_INVALID_PARAM; + + crypt_write32(REG_P68, 0x6A); + crypt_write32(REG_P69, 0x34 + 4 * num); + crypt_wait(); + return MTK_SIP_E_SUCCESS; +} + +/* Clear key in crypt engine */ +uint64_t crypt_clear_hdcp_key(void) +{ + uint32_t i; + + for (i = 0; i < KEY_SIZE; i++) + crypt_write32(REG_D20 + i, 0); + return MTK_SIP_E_SUCCESS; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/crypt/crypt.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/crypt/crypt.h new file mode 100644 index 0000000..25e3077 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/crypt/crypt.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __CRYPT_H__ +#define __CRYPT_H__ + +#include + +/* crypt function prototype */ +uint64_t crypt_set_hdcp_key_ex(uint64_t x1, uint64_t x2, uint64_t x3); +uint64_t crypt_set_hdcp_key_num(uint32_t num); +uint64_t crypt_clear_hdcp_key(void); + +#endif /* __CRYPT_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.c new file mode 100644 index 0000000..5640fb3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.c @@ -0,0 +1,296 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include + +enum { + SRAM_ISOINT_B = 1U << 6, + SRAM_CKISO = 1U << 5, + PWR_CLK_DIS = 1U << 4, + PWR_ON_2ND = 1U << 3, + PWR_ON = 1U << 2, + PWR_ISO = 1U << 1, + PWR_RST_B = 1U << 0 +}; + +enum { + L1_PDN_ACK = 1U << 8, + L1_PDN = 1U << 0 +}; + +enum { + LITTLE_CPU3 = 1U << 12, + LITTLE_CPU2 = 1U << 11, + LITTLE_CPU1 = 1U << 10, +}; + +enum { + SRAM_PDN = 0xf << 8, + DIS_SRAM_ACK = 0x1 << 12, + AUD_SRAM_ACK = 0xf << 12, +}; + +enum { + DIS_PWR_STA_MASK = 0x1 << 3, + AUD_PWR_STA_MASK = 0x1 << 24, +}; + +#define SPM_VDE_PWR_CON 0x0210 +#define SPM_MFG_PWR_CON 0x0214 +#define SPM_VEN_PWR_CON 0x0230 +#define SPM_ISP_PWR_CON 0x0238 +#define SPM_DIS_PWR_CON 0x023c +#define SPM_VEN2_PWR_CON 0x0298 +#define SPM_AUDIO_PWR_CON 0x029c +#define SPM_MFG_2D_PWR_CON 0x02c0 +#define SPM_MFG_ASYNC_PWR_CON 0x02c4 +#define SPM_USB_PWR_CON 0x02cc + +#define MTCMOS_CTRL_SUCCESS 0 +#define MTCMOS_CTRL_ERROR -1 + +#define MTCMOS_CTRL_EN (0x1 << 18) + +#define VDE_PWR_ON 0 +#define VEN_PWR_ON 1 +#define ISP_PWR_ON 2 +#define DIS_PWR_ON 3 +#define VEN2_PWR_ON 4 +#define AUDIO_PWR_ON 5 +#define MFG_ASYNC_PWR_ON 6 +#define MFG_2D_PWR_ON 7 +#define MFG_PWR_ON 8 +#define USB_PWR_ON 9 + +#define VDE_PWR_OFF 10 +#define VEN_PWR_OFF 11 +#define ISP_PWR_OFF 12 +#define DIS_PWR_OFF 13 +#define VEN2_PWR_OFF 14 +#define AUDIO_PWR_OFF 15 +#define MFG_ASYNC_PWR_OFF 16 +#define MFG_2D_PWR_OFF 17 +#define MFG_PWR_OFF 18 +#define USB_PWR_OFF 19 + +#define VDE_PWR_CON_PWR_STA 7 +#define VEN_PWR_CON_PWR_STA 21 +#define ISP_PWR_CON_PWR_STA 5 +#define DIS_PWR_CON_PWR_STA 3 +#define VEN2_PWR_CON_PWR_STA 20 +#define AUDIO_PWR_CON_PWR_STA 24 +#define MFG_ASYNC_PWR_CON_PWR_STA 23 +#define MFG_2D_PWR_CON_PWR_STA 22 +#define MFG_PWR_CON_PWR_STA 4 +#define USB_PWR_CON_PWR_STA 25 + +/* + * Timeout if the ack is not signled after 1 second. + * According to designer, one mtcmos operation should be done + * around 10us. + */ +#define MTCMOS_ACK_POLLING_MAX_COUNT 10000 +#define MTCMOS_ACK_POLLING_INTERVAL 10 + +static void mtcmos_ctrl_little_off(unsigned int linear_id) +{ + uint32_t reg_pwr_con; + uint32_t reg_l1_pdn; + uint32_t bit_cpu; + + switch (linear_id) { + case 1: + reg_pwr_con = SPM_CA7_CPU1_PWR_CON; + reg_l1_pdn = SPM_CA7_CPU1_L1_PDN; + bit_cpu = LITTLE_CPU1; + break; + case 2: + reg_pwr_con = SPM_CA7_CPU2_PWR_CON; + reg_l1_pdn = SPM_CA7_CPU2_L1_PDN; + bit_cpu = LITTLE_CPU2; + break; + case 3: + reg_pwr_con = SPM_CA7_CPU3_PWR_CON; + reg_l1_pdn = SPM_CA7_CPU3_L1_PDN; + bit_cpu = LITTLE_CPU3; + break; + default: + /* should never come to here */ + return; + } + + /* enable register control */ + mmio_write_32(SPM_POWERON_CONFIG_SET, + (SPM_PROJECT_CODE << 16) | (1U << 0)); + + mmio_setbits_32(reg_pwr_con, PWR_ISO); + mmio_setbits_32(reg_pwr_con, SRAM_CKISO); + mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B); + mmio_setbits_32(reg_l1_pdn, L1_PDN); + + while (!(mmio_read_32(reg_l1_pdn) & L1_PDN_ACK)) + continue; + + mmio_clrbits_32(reg_pwr_con, PWR_RST_B); + mmio_setbits_32(reg_pwr_con, PWR_CLK_DIS); + mmio_clrbits_32(reg_pwr_con, PWR_ON); + mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND); + + while ((mmio_read_32(SPM_PWR_STATUS) & bit_cpu) || + (mmio_read_32(SPM_PWR_STATUS_2ND) & bit_cpu)) + continue; +} + +void mtcmos_little_cpu_off(void) +{ + /* turn off little cpu 1 - 3 */ + mtcmos_ctrl_little_off(1); + mtcmos_ctrl_little_off(2); + mtcmos_ctrl_little_off(3); +} + +uint32_t wait_mtcmos_ack(uint32_t on, uint32_t pwr_ctrl, uint32_t spm_pwr_sta) +{ + int i = 0; + uint32_t cmp, pwr_sta, pwr_sta_2nd; + + while (1) { + cmp = mmio_read_32(SPM_PCM_PASR_DPD_3) & pwr_ctrl; + pwr_sta = (mmio_read_32(SPM_PWR_STATUS) >> spm_pwr_sta) & 1; + pwr_sta_2nd = + (mmio_read_32(SPM_PWR_STATUS_2ND) >> spm_pwr_sta) & 1; + if (cmp && (pwr_sta == on) && (pwr_sta_2nd == on)) { + mmio_write_32(SPM_PCM_RESERVE2, 0); + return MTCMOS_CTRL_SUCCESS; + } + udelay(MTCMOS_ACK_POLLING_INTERVAL); + i++; + if (i > MTCMOS_ACK_POLLING_MAX_COUNT) { + INFO("MTCMOS control failed(%d), SPM_PWR_STA(%d),\n" + "SPM_PCM_RESERVE=0x%x,SPM_PCM_RESERVE2=0x%x,\n" + "SPM_PWR_STATUS=0x%x,SPM_PWR_STATUS_2ND=0x%x\n" + "SPM_PCM_PASR_DPD_3 = 0x%x\n", + on, spm_pwr_sta, mmio_read_32(SPM_PCM_RESERVE), + mmio_read_32(SPM_PCM_RESERVE2), + mmio_read_32(SPM_PWR_STATUS), + mmio_read_32(SPM_PWR_STATUS_2ND), + mmio_read_32(SPM_PCM_PASR_DPD_3)); + mmio_write_32(SPM_PCM_RESERVE2, 0); + return MTCMOS_CTRL_ERROR; + } + } +} + +uint32_t mtcmos_non_cpu_ctrl(uint32_t on, uint32_t mtcmos_num) +{ + uint32_t ret = MTCMOS_CTRL_SUCCESS; + uint32_t power_on; + uint32_t power_off; + uint32_t power_ctrl; + uint32_t power_status; + + spm_lock_get(); + spm_mcdi_prepare_for_mtcmos(); + mmio_setbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN); + + switch (mtcmos_num) { + case SPM_VDE_PWR_CON: + power_on = VDE_PWR_ON; + power_off = VDE_PWR_OFF; + power_status = VDE_PWR_CON_PWR_STA; + break; + case SPM_MFG_PWR_CON: + power_on = MFG_PWR_ON; + power_off = MFG_PWR_OFF; + power_status = MFG_PWR_CON_PWR_STA; + break; + case SPM_VEN_PWR_CON: + power_on = VEN_PWR_ON; + power_off = VEN_PWR_OFF; + power_status = VEN_PWR_CON_PWR_STA; + break; + case SPM_ISP_PWR_CON: + power_on = ISP_PWR_ON; + power_off = ISP_PWR_OFF; + power_status = ISP_PWR_CON_PWR_STA; + break; + case SPM_DIS_PWR_CON: + power_on = DIS_PWR_ON; + power_off = DIS_PWR_OFF; + power_status = DIS_PWR_CON_PWR_STA; + break; + case SPM_VEN2_PWR_CON: + power_on = VEN2_PWR_ON; + power_off = VEN2_PWR_OFF; + power_status = VEN2_PWR_CON_PWR_STA; + break; + case SPM_AUDIO_PWR_CON: + power_on = AUDIO_PWR_ON; + power_off = AUDIO_PWR_OFF; + power_status = AUDIO_PWR_CON_PWR_STA; + break; + case SPM_MFG_2D_PWR_CON: + power_on = MFG_2D_PWR_ON; + power_off = MFG_2D_PWR_OFF; + power_status = MFG_2D_PWR_CON_PWR_STA; + break; + case SPM_MFG_ASYNC_PWR_CON: + power_on = MFG_ASYNC_PWR_ON; + power_off = MFG_ASYNC_PWR_OFF; + power_status = MFG_ASYNC_PWR_CON_PWR_STA; + break; + case SPM_USB_PWR_CON: + power_on = USB_PWR_ON; + power_off = USB_PWR_OFF; + power_status = USB_PWR_CON_PWR_STA; + break; + default: + ret = MTCMOS_CTRL_ERROR; + INFO("No mapping MTCMOS(%d), ret = %d\n", mtcmos_num, ret); + break; + } + if (ret == MTCMOS_CTRL_SUCCESS) { + power_ctrl = on ? (1 << power_on) : (1 << power_off); + mmio_setbits_32(SPM_PCM_RESERVE2, power_ctrl); + ret = wait_mtcmos_ack(on, power_ctrl, power_status); + VERBOSE("0x%x(%d), PWR_STATUS(0x%x), ret(%d)\n", + power_ctrl, on, mmio_read_32(SPM_PWR_STATUS), ret); + } + + mmio_clrbits_32(SPM_PCM_RESERVE, MTCMOS_CTRL_EN); + spm_lock_release(); + + return ret; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.h new file mode 100644 index 0000000..4641f46 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/mtcmos/mtcmos.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MTCMOS_H__ +#define __MTCMOS_H__ + +/* + * This function will turn off all the little core's power except cpu 0. The + * cores in cluster 0 are all powered when the system power on. The System + * Power Manager (SPM) will do nothing if it found the core's power was on + * during CPU_ON psci call. + */ +void mtcmos_little_cpu_off(void); +uint32_t mtcmos_non_cpu_ctrl(uint32_t on, uint32_t mtcmos_num); + +#endif /* __MTCMOS_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.c new file mode 100644 index 0000000..48908c7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.c @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include + +/* pmic wrap module wait_idle and read polling interval (in microseconds) */ +enum { + WAIT_IDLE_POLLING_DELAY_US = 1, + READ_POLLING_DELAY_US = 2 +}; + +static inline uint32_t wait_for_state_idle(uint32_t timeout_us, + void *wacs_register, + void *wacs_vldclr_register, + uint32_t *read_reg) +{ + uint32_t reg_rdata; + uint32_t retry; + + retry = (timeout_us + WAIT_IDLE_POLLING_DELAY_US) / + WAIT_IDLE_POLLING_DELAY_US; + + do { + udelay(WAIT_IDLE_POLLING_DELAY_US); + reg_rdata = mmio_read_32((uintptr_t)wacs_register); + /* if last read command timeout,clear vldclr bit + read command state machine:FSM_REQ-->wfdle-->WFVLDCLR; + write:FSM_REQ-->idle */ + switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & + RDATA_WACS_FSM_MASK)) { + case WACS_FSM_WFVLDCLR: + mmio_write_32((uintptr_t)wacs_vldclr_register, 1); + ERROR("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n"); + break; + case WACS_FSM_WFDLE: + ERROR("WACS_FSM = WACS_FSM_WFDLE\n"); + break; + case WACS_FSM_REQ: + ERROR("WACS_FSM = WACS_FSM_REQ\n"); + break; + case WACS_FSM_IDLE: + goto done; + default: + break; + } + + retry--; + } while (retry); + +done: + if (!retry) /* timeout */ + return E_PWR_WAIT_IDLE_TIMEOUT; + + if (read_reg) + *read_reg = reg_rdata; + return 0; +} + +static inline uint32_t wait_for_state_ready(uint32_t timeout_us, + void *wacs_register, + uint32_t *read_reg) +{ + uint32_t reg_rdata; + uint32_t retry; + + retry = (timeout_us + READ_POLLING_DELAY_US) / READ_POLLING_DELAY_US; + + do { + udelay(READ_POLLING_DELAY_US); + reg_rdata = mmio_read_32((uintptr_t)wacs_register); + + if (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) + == WACS_FSM_WFVLDCLR) + break; + + retry--; + } while (retry); + + if (!retry) { /* timeout */ + ERROR("timeout when waiting for idle\n"); + return E_PWR_WAIT_IDLE_TIMEOUT_READ; + } + + if (read_reg) + *read_reg = reg_rdata; + return 0; +} + +static int32_t pwrap_wacs2(uint32_t write, + uint32_t adr, + uint32_t wdata, + uint32_t *rdata, + uint32_t init_check) +{ + uint32_t reg_rdata = 0; + uint32_t wacs_write = 0; + uint32_t wacs_adr = 0; + uint32_t wacs_cmd = 0; + uint32_t return_value = 0; + + if (init_check) { + reg_rdata = mmio_read_32((uintptr_t)&mt8173_pwrap->wacs2_rdata); + /* Prevent someone to used pwrap before pwrap init */ + if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) & + RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { + ERROR("initialization isn't finished\n"); + return E_PWR_NOT_INIT_DONE; + } + } + reg_rdata = 0; + /* Check IDLE in advance */ + return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE, + &mt8173_pwrap->wacs2_rdata, + &mt8173_pwrap->wacs2_vldclr, + 0); + if (return_value != 0) { + ERROR("wait_for_fsm_idle fail,return_value=%d\n", return_value); + goto FAIL; + } + wacs_write = write << 31; + wacs_adr = (adr >> 1) << 16; + wacs_cmd = wacs_write | wacs_adr | wdata; + + mmio_write_32((uintptr_t)&mt8173_pwrap->wacs2_cmd, wacs_cmd); + if (write == 0) { + if (NULL == rdata) { + ERROR("rdata is a NULL pointer\n"); + return_value = E_PWR_INVALID_ARG; + goto FAIL; + } + return_value = wait_for_state_ready(TIMEOUT_READ, + &mt8173_pwrap->wacs2_rdata, + ®_rdata); + if (return_value != 0) { + ERROR("wait_for_fsm_vldclr fail,return_value=%d\n", + return_value); + goto FAIL; + } + *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT) + & RDATA_WACS_RDATA_MASK); + mmio_write_32((uintptr_t)&mt8173_pwrap->wacs2_vldclr, 1); + } +FAIL: + return return_value; +} + +/* external API for pmic_wrap user */ + +int32_t pwrap_read(uint32_t adr, uint32_t *rdata) +{ + return pwrap_wacs2(0, adr, 0, rdata, 1); +} + +int32_t pwrap_write(uint32_t adr, uint32_t wdata) +{ + return pwrap_wacs2(1, adr, wdata, 0, 1); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h new file mode 100644 index 0000000..0b20500 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/pmic/pmic_wrap_init.h @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PMIC_WRAP_INIT_H__ +#define __PMIC_WRAP_INIT_H__ + +/* external API */ +int32_t pwrap_read(uint32_t adr, uint32_t *rdata); +int32_t pwrap_write(uint32_t adr, uint32_t wdata); + +static struct mt8173_pmic_wrap_regs *const mt8173_pwrap = + (void *)PMIC_WRAP_BASE; + +/* timeout setting */ +enum { + TIMEOUT_RESET = 50, /* us */ + TIMEOUT_READ = 50, /* us */ + TIMEOUT_WAIT_IDLE = 50 /* us */ +}; + +/* PMIC_WRAP registers */ +struct mt8173_pmic_wrap_regs { + uint32_t mux_sel; + uint32_t wrap_en; + uint32_t dio_en; + uint32_t sidly; + uint32_t rddmy; + uint32_t si_ck_con; + uint32_t cshext_write; + uint32_t cshext_read; + uint32_t cslext_start; + uint32_t cslext_end; + uint32_t staupd_prd; + uint32_t staupd_grpen; + uint32_t reserved[4]; + uint32_t staupd_man_trig; + uint32_t staupd_sta; + uint32_t wrap_sta; + uint32_t harb_init; + uint32_t harb_hprio; + uint32_t hiprio_arb_en; + uint32_t harb_sta0; + uint32_t harb_sta1; + uint32_t man_en; + uint32_t man_cmd; + uint32_t man_rdata; + uint32_t man_vldclr; + uint32_t wacs0_en; + uint32_t init_done0; + uint32_t wacs0_cmd; + uint32_t wacs0_rdata; + uint32_t wacs0_vldclr; + uint32_t wacs1_en; + uint32_t init_done1; + uint32_t wacs1_cmd; + uint32_t wacs1_rdata; + uint32_t wacs1_vldclr; + uint32_t wacs2_en; + uint32_t init_done2; + uint32_t wacs2_cmd; + uint32_t wacs2_rdata; + uint32_t wacs2_vldclr; + uint32_t int_en; + uint32_t int_flg_raw; + uint32_t int_flg; + uint32_t int_clr; + uint32_t sig_adr; + uint32_t sig_mode; + uint32_t sig_value; + uint32_t sig_errval; + uint32_t crc_en; + uint32_t timer_en; + uint32_t timer_sta; + uint32_t wdt_unit; + uint32_t wdt_src_en; + uint32_t wdt_flg; + uint32_t debug_int_sel; + uint32_t dvfs_adr0; + uint32_t dvfs_wdata0; + uint32_t dvfs_adr1; + uint32_t dvfs_wdata1; + uint32_t dvfs_adr2; + uint32_t dvfs_wdata2; + uint32_t dvfs_adr3; + uint32_t dvfs_wdata3; + uint32_t dvfs_adr4; + uint32_t dvfs_wdata4; + uint32_t dvfs_adr5; + uint32_t dvfs_wdata5; + uint32_t dvfs_adr6; + uint32_t dvfs_wdata6; + uint32_t dvfs_adr7; + uint32_t dvfs_wdata7; + uint32_t spminf_sta; + uint32_t cipher_key_sel; + uint32_t cipher_iv_sel; + uint32_t cipher_en; + uint32_t cipher_rdy; + uint32_t cipher_mode; + uint32_t cipher_swrst; + uint32_t dcm_en; + uint32_t dcm_dbc_prd; +}; + +enum { + RDATA_WACS_RDATA_SHIFT = 0, + RDATA_WACS_FSM_SHIFT = 16, + RDATA_WACS_REQ_SHIFT = 19, + RDATA_SYNC_IDLE_SHIFT, + RDATA_INIT_DONE_SHIFT, + RDATA_SYS_IDLE_SHIFT, +}; + +enum { + RDATA_WACS_RDATA_MASK = 0xffff, + RDATA_WACS_FSM_MASK = 0x7, + RDATA_WACS_REQ_MASK = 0x1, + RDATA_SYNC_IDLE_MASK = 0x1, + RDATA_INIT_DONE_MASK = 0x1, + RDATA_SYS_IDLE_MASK = 0x1, +}; + +/* WACS_FSM */ +enum { + WACS_FSM_IDLE = 0x00, + WACS_FSM_REQ = 0x02, + WACS_FSM_WFDLE = 0x04, + WACS_FSM_WFVLDCLR = 0x06, + WACS_INIT_DONE = 0x01, + WACS_SYNC_IDLE = 0x01, + WACS_SYNC_BUSY = 0x00 +}; + +/* error information flag */ +enum { + E_PWR_INVALID_ARG = 1, + E_PWR_INVALID_RW = 2, + E_PWR_INVALID_ADDR = 3, + E_PWR_INVALID_WDAT = 4, + E_PWR_INVALID_OP_MANUAL = 5, + E_PWR_NOT_IDLE_STATE = 6, + E_PWR_NOT_INIT_DONE = 7, + E_PWR_NOT_INIT_DONE_READ = 8, + E_PWR_WAIT_IDLE_TIMEOUT = 9, + E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, + E_PWR_INIT_SIDLY_FAIL = 11, + E_PWR_RESET_TIMEOUT = 12, + E_PWR_TIMEOUT = 13, + E_PWR_INIT_RESET_SPI = 20, + E_PWR_INIT_SIDLY = 21, + E_PWR_INIT_REG_CLOCK = 22, + E_PWR_INIT_ENABLE_PMIC = 23, + E_PWR_INIT_DIO = 24, + E_PWR_INIT_CIPHER = 25, + E_PWR_INIT_WRITE_TEST = 26, + E_PWR_INIT_ENABLE_CRC = 27, + E_PWR_INIT_ENABLE_DEWRAP = 28, + E_PWR_INIT_ENABLE_EVENT = 29, + E_PWR_READ_TEST_FAIL = 30, + E_PWR_WRITE_TEST_FAIL = 31, + E_PWR_SWITCH_DIO = 32 +}; + +#endif /* __PMIC_WRAP_INIT_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/rtc/rtc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/rtc/rtc.c new file mode 100644 index 0000000..daaac42 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/rtc/rtc.c @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include + +/* RTC busy status polling interval and retry count */ +enum { + RTC_WRTGR_POLLING_DELAY_MS = 10, + RTC_WRTGR_POLLING_CNT = 100 +}; + +static uint16_t RTC_Read(uint32_t addr) +{ + uint32_t rdata = 0; + + pwrap_read((uint32_t)addr, &rdata); + return (uint16_t)rdata; +} + +static void RTC_Write(uint32_t addr, uint16_t data) +{ + pwrap_write((uint32_t)addr, (uint32_t)data); +} + +static inline int32_t rtc_busy_wait(void) +{ + uint64_t retry = RTC_WRTGR_POLLING_CNT; + + do { + mdelay(RTC_WRTGR_POLLING_DELAY_MS); + if (!(RTC_Read(RTC_BBPU) & RTC_BBPU_CBUSY)) + return 1; + retry--; + } while (retry); + + ERROR("[RTC] rtc cbusy time out!\n"); + return 0; +} + +static int32_t Write_trigger(void) +{ + RTC_Write(RTC_WRTGR, 1); + return rtc_busy_wait(); +} + +static int32_t Writeif_unlock(void) +{ + RTC_Write(RTC_PROT, RTC_PROT_UNLOCK1); + if (!Write_trigger()) + return 0; + RTC_Write(RTC_PROT, RTC_PROT_UNLOCK2); + if (!Write_trigger()) + return 0; + + return 1; +} + +void rtc_bbpu_power_down(void) +{ + uint16_t bbpu; + + /* pull PWRBB low */ + bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_PWREN; + if (Writeif_unlock()) { + RTC_Write(RTC_BBPU, bbpu); + if (!Write_trigger()) + assert(0); + } else { + assert(0); + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/rtc/rtc.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/rtc/rtc.h new file mode 100644 index 0000000..c2138cd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/rtc/rtc.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_DRIVER_RTC_H__ +#define __PLAT_DRIVER_RTC_H__ + +/* RTC registers */ +enum { + RTC_BBPU = 0xE000, + RTC_IRQ_STA = 0xE002, + RTC_IRQ_EN = 0xE004, + RTC_CII_EN = 0xE006 +}; + +enum { + RTC_OSC32CON = 0xE026, + RTC_CON = 0xE03E, + RTC_WRTGR = 0xE03C +}; + +enum { + RTC_PDN1 = 0xE02C, + RTC_PDN2 = 0xE02E, + RTC_SPAR0 = 0xE030, + RTC_SPAR1 = 0xE032, + RTC_PROT = 0xE036, + RTC_DIFF = 0xE038, + RTC_CALI = 0xE03A +}; + +enum { + RTC_PROT_UNLOCK1 = 0x586A, + RTC_PROT_UNLOCK2 = 0x9136 +}; + +enum { + RTC_BBPU_PWREN = 1U << 0, + RTC_BBPU_BBPU = 1U << 2, + RTC_BBPU_AUTO = 1U << 3, + RTC_BBPU_CLRPKY = 1U << 4, + RTC_BBPU_RELOAD = 1U << 5, + RTC_BBPU_CBUSY = 1U << 6 +}; + +enum { + RTC_BBPU_KEY = 0x43 << 8 +}; + +void rtc_bbpu_power_down(void); + +#endif /* __PLAT_DRIVER_RTC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm.c new file mode 100644 index 0000000..75eb61a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm.c @@ -0,0 +1,392 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include + +/* + * System Power Manager (SPM) is a hardware module, which controls cpu or + * system power for different power scenarios using different firmware, i.e., + * - spm_hotplug.c for cpu power control in cpu hotplug flow. + * - spm_mcdi.c for cpu power control in cpu idle power saving state. + * - spm_suspend.c for system power control in system suspend scenario. + * + * This file provide utility functions common to hotplug, mcdi(idle), suspend + * power scenarios. A bakery lock (software lock) is incoporated to protect + * certain critical sections to avoid kicking different SPM firmware + * concurrently. + */ + +#define SPM_SYSCLK_SETTLE 128 /* 3.9ms */ + +DEFINE_BAKERY_LOCK(spm_lock); + +static int spm_hotplug_ready __section("tzfw_coherent_mem"); +static int spm_mcdi_ready __section("tzfw_coherent_mem"); +static int spm_suspend_ready __section("tzfw_coherent_mem"); + +void spm_lock_init(void) +{ + bakery_lock_init(&spm_lock); +} + +void spm_lock_get(void) +{ + bakery_lock_get(&spm_lock); +} + +void spm_lock_release(void) +{ + bakery_lock_release(&spm_lock); +} + +int is_mcdi_ready(void) +{ + return spm_mcdi_ready; +} + +int is_hotplug_ready(void) +{ + return spm_hotplug_ready; +} + +int is_suspend_ready(void) +{ + return spm_suspend_ready; +} + +void set_mcdi_ready(void) +{ + spm_mcdi_ready = 1; + spm_hotplug_ready = 0; + spm_suspend_ready = 0; +} + +void set_hotplug_ready(void) +{ + spm_mcdi_ready = 0; + spm_hotplug_ready = 1; + spm_suspend_ready = 0; +} + +void set_suspend_ready(void) +{ + spm_mcdi_ready = 0; + spm_hotplug_ready = 0; + spm_suspend_ready = 1; +} + +void clear_all_ready(void) +{ + spm_mcdi_ready = 0; + spm_hotplug_ready = 0; + spm_suspend_ready = 0; +} + +void spm_register_init(void) +{ + mmio_write_32(SPM_POWERON_CONFIG_SET, SPM_REGWR_CFG_KEY | SPM_REGWR_EN); + + mmio_write_32(SPM_POWER_ON_VAL0, 0); + mmio_write_32(SPM_POWER_ON_VAL1, POWER_ON_VAL1_DEF); + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); + + mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); + mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); + if (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) + WARN("PCM reset failed\n"); + + mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); + mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_EVENT_LOCK_EN | + CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | CON1_MIF_APBEN); + mmio_write_32(SPM_PCM_IM_PTR, 0); + mmio_write_32(SPM_PCM_IM_LEN, 0); + + mmio_write_32(SPM_CLK_CON, CC_SYSCLK0_EN_1 | CC_SYSCLK0_EN_0 | + CC_SYSCLK1_EN_0 | CC_SRCLKENA_MASK_0 | CC_CLKSQ1_SEL | + CC_CXO32K_RM_EN_MD2 | CC_CXO32K_RM_EN_MD1 | CC_MD32_DCM_EN); + + mmio_write_32(SPM_SLEEP_ISR_MASK, 0xff0c); + mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xc); + mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xff); + mmio_write_32(SPM_MD32_SRAM_CON, 0xff0); +} + +void spm_reset_and_init_pcm(void) +{ + unsigned int con1; + int i = 0; + + mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET); + mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY); + while (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) { + i++; + if (i > 1000) { + i = 0; + WARN("PCM reset failed\n"); + break; + } + } + + mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS); + + con1 = mmio_read_32(SPM_PCM_CON1) & + (CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN); + mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_EVENT_LOCK_EN | + CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | + CON1_IM_NONRP_EN | CON1_MIF_APBEN); +} + +void spm_init_pcm_register(void) +{ + mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL0)); + mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R0); + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); + + mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL1)); + mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R7); + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); +} + +void spm_set_power_control(const struct pwr_ctrl *pwrctrl) +{ + mmio_write_32(SPM_AP_STANBY_CON, (!pwrctrl->md32_req_mask << 21) | + (!pwrctrl->mfg_req_mask << 17) | + (!pwrctrl->disp_req_mask << 16) | + (!!pwrctrl->mcusys_idle_mask << 7) | + (!!pwrctrl->ca15top_idle_mask << 6) | + (!!pwrctrl->ca7top_idle_mask << 5) | + (!!pwrctrl->wfi_op << 4)); + mmio_write_32(SPM_PCM_SRC_REQ, (!!pwrctrl->pcm_apsrc_req << 0)); + mmio_write_32(SPM_PCM_PASR_DPD_2, 0); + + mmio_clrsetbits_32(SPM_CLK_CON, CC_SRCLKENA_MASK_0, + (pwrctrl->srclkenai_mask ? CC_SRCLKENA_MASK_0 : 0)); + + mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, !!pwrctrl->ca15_wfi0_en); + mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, !!pwrctrl->ca15_wfi1_en); + mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, !!pwrctrl->ca15_wfi2_en); + mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, !!pwrctrl->ca15_wfi3_en); + mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, !!pwrctrl->ca7_wfi0_en); + mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, !!pwrctrl->ca7_wfi1_en); + mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, !!pwrctrl->ca7_wfi2_en); + mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, !!pwrctrl->ca7_wfi3_en); +} + +void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl) +{ + unsigned int val, mask; + + if (pwrctrl->timer_val_cust == 0) + val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX; + else + val = pwrctrl->timer_val_cust; + + mmio_write_32(SPM_PCM_TIMER_VAL, val); + mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY); + + if (pwrctrl->wake_src_cust == 0) + mask = pwrctrl->wake_src; + else + mask = pwrctrl->wake_src_cust; + + if (pwrctrl->syspwreq_mask) + mask &= ~WAKE_SRC_SYSPWREQ; + + mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~mask); + mmio_write_32(SPM_SLEEP_ISR_MASK, 0xfe04); +} + +void spm_get_wakeup_status(struct wake_status *wakesta) +{ + wakesta->assert_pc = mmio_read_32(SPM_PCM_REG_DATA_INI); + wakesta->r12 = mmio_read_32(SPM_PCM_REG12_DATA); + wakesta->raw_sta = mmio_read_32(SPM_SLEEP_ISR_RAW_STA); + wakesta->wake_misc = mmio_read_32(SPM_SLEEP_WAKEUP_MISC); + wakesta->timer_out = mmio_read_32(SPM_PCM_TIMER_OUT); + wakesta->r13 = mmio_read_32(SPM_PCM_REG13_DATA); + wakesta->idle_sta = mmio_read_32(SPM_SLEEP_SUBSYS_IDLE_STA); + wakesta->debug_flag = mmio_read_32(SPM_PCM_PASR_DPD_3); + wakesta->event_reg = mmio_read_32(SPM_PCM_EVENT_REG_STA); + wakesta->isr = mmio_read_32(SPM_SLEEP_ISR_STATUS); +} + +void spm_init_event_vector(const struct pcm_desc *pcmdesc) +{ + /* init event vector register */ + mmio_write_32(SPM_PCM_EVENT_VECTOR0, pcmdesc->vec0); + mmio_write_32(SPM_PCM_EVENT_VECTOR1, pcmdesc->vec1); + mmio_write_32(SPM_PCM_EVENT_VECTOR2, pcmdesc->vec2); + mmio_write_32(SPM_PCM_EVENT_VECTOR3, pcmdesc->vec3); + mmio_write_32(SPM_PCM_EVENT_VECTOR4, pcmdesc->vec4); + mmio_write_32(SPM_PCM_EVENT_VECTOR5, pcmdesc->vec5); + mmio_write_32(SPM_PCM_EVENT_VECTOR6, pcmdesc->vec6); + mmio_write_32(SPM_PCM_EVENT_VECTOR7, pcmdesc->vec7); + + /* event vector will be enabled by PCM itself */ +} + +void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc) +{ + unsigned int ptr = 0, len, con0; + + ptr = (unsigned int)(unsigned long)(pcmdesc->base); + len = pcmdesc->size - 1; + if (mmio_read_32(SPM_PCM_IM_PTR) != ptr || + mmio_read_32(SPM_PCM_IM_LEN) != len || + pcmdesc->sess > 2) { + mmio_write_32(SPM_PCM_IM_PTR, ptr); + mmio_write_32(SPM_PCM_IM_LEN, len); + } else { + mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_IM_SLAVE); + } + + /* kick IM to fetch (only toggle IM_KICK) */ + con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK); + mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_IM_KICK); + mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY); + + /* kick IM to fetch (only toggle PCM_KICK) */ + con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK); + mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_PCM_KICK); + mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY); +} + +void spm_set_sysclk_settle(void) +{ + mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE); + + INFO("settle = %u\n", mmio_read_32(SPM_CLK_SETTLE)); +} + +void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl) +{ + unsigned int con1; + + con1 = mmio_read_32(SPM_PCM_CON1) & + ~(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN); + + mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | con1); + + if (mmio_read_32(SPM_PCM_TIMER_VAL) > PCM_TIMER_MAX) + mmio_write_32(SPM_PCM_TIMER_VAL, PCM_TIMER_MAX); + + mmio_write_32(SPM_PCM_WDT_TIMER_VAL, + mmio_read_32(SPM_PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); + + mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_PCM_WDT_EN); + mmio_write_32(SPM_PCM_PASR_DPD_0, 0); + + mmio_write_32(SPM_PCM_MAS_PAUSE_MASK, 0xffffffff); + mmio_write_32(SPM_PCM_REG_DATA_INI, 0); + mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR); + + mmio_write_32(SPM_PCM_FLAGS, pwrctrl->pcm_flags); + + mmio_clrsetbits_32(SPM_CLK_CON, CC_LOCK_INFRA_DCM, + (pwrctrl->infra_dcm_lock ? CC_LOCK_INFRA_DCM : 0)); + + mmio_write_32(SPM_PCM_PWR_IO_EN, + (pwrctrl->r0_ctrl_en ? PCM_PWRIO_EN_R0 : 0) | + (pwrctrl->r7_ctrl_en ? PCM_PWRIO_EN_R7 : 0)); +} + +void spm_clean_after_wakeup(void) +{ + mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_WDT_EN, CON1_CFG_KEY); + + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); + mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, 0); + mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_TIMER_EN, CON1_CFG_KEY); + + mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~0); + mmio_write_32(SPM_SLEEP_ISR_MASK, 0xFF0C); + mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xC); + mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xFF); +} + +enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta) +{ + enum wake_reason_t wr; + int i; + + wr = WR_UNKNOWN; + + if (wakesta->assert_pc != 0) { + ERROR("PCM ASSERT AT %u, r12=0x%x, r13=0x%x, debug_flag=0x%x\n", + wakesta->assert_pc, wakesta->r12, wakesta->r13, + wakesta->debug_flag); + return WR_PCM_ASSERT; + } + + if (wakesta->r12 & WAKE_SRC_SPM_MERGE) { + if (wakesta->wake_misc & WAKE_MISC_PCM_TIMER) + wr = WR_PCM_TIMER; + if (wakesta->wake_misc & WAKE_MISC_CPU_WAKE) + wr = WR_WAKE_SRC; + } + + for (i = 1; i < 32; i++) { + if (wakesta->r12 & (1U << i)) + wr = WR_WAKE_SRC; + } + + if ((wakesta->event_reg & 0x100000) == 0) { + INFO("pcm sleep abort!\n"); + wr = WR_PCM_ABORT; + } + + INFO("timer_out = %u, r12 = 0x%x, r13 = 0x%x, debug_flag = 0x%x\n", + wakesta->timer_out, wakesta->r12, wakesta->r13, + wakesta->debug_flag); + + INFO("raw_sta = 0x%x, idle_sta = 0x%x, event_reg = 0x%x, isr = 0x%x\n", + wakesta->raw_sta, wakesta->idle_sta, wakesta->event_reg, + wakesta->isr); + + return wr; +} + +void spm_boot_init(void) +{ + /* set spm transaction to secure mode */ + mmio_write_32(DEVAPC0_APC_CON, 0x0); + mmio_write_32(DEVAPC0_MAS_SEC_0, 0x200); + + /* Only CPU0 is online during boot, initialize cpu online reserve bit */ + mmio_write_32(SPM_PCM_RESERVE, 0xFE); + mmio_clrbits_32(AP_PLL_CON3, 0xFFFFF); + mmio_clrbits_32(AP_PLL_CON4, 0xF); + spm_lock_init(); + spm_register_init(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm.h new file mode 100644 index 0000000..f371fd8 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm.h @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __SPM_H__ +#define __SPM_H__ + +#define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000) +#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010) +#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014) +#define SPM_CLK_SETTLE (SPM_BASE + 0x100) +#define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218) +#define SPM_CA7_CPU2_PWR_CON (SPM_BASE + 0x21c) +#define SPM_CA7_CPU3_PWR_CON (SPM_BASE + 0x220) +#define SPM_CA7_CPU1_L1_PDN (SPM_BASE + 0x264) +#define SPM_CA7_CPU2_L1_PDN (SPM_BASE + 0x26c) +#define SPM_CA7_CPU3_L1_PDN (SPM_BASE + 0x274) +#define SPM_MD32_SRAM_CON (SPM_BASE + 0x2c8) +#define SPM_PCM_CON0 (SPM_BASE + 0x310) +#define SPM_PCM_CON1 (SPM_BASE + 0x314) +#define SPM_PCM_IM_PTR (SPM_BASE + 0x318) +#define SPM_PCM_IM_LEN (SPM_BASE + 0x31c) +#define SPM_PCM_REG_DATA_INI (SPM_BASE + 0x320) +#define SPM_PCM_EVENT_VECTOR0 (SPM_BASE + 0x340) +#define SPM_PCM_EVENT_VECTOR1 (SPM_BASE + 0x344) +#define SPM_PCM_EVENT_VECTOR2 (SPM_BASE + 0x348) +#define SPM_PCM_EVENT_VECTOR3 (SPM_BASE + 0x34c) +#define SPM_PCM_MAS_PAUSE_MASK (SPM_BASE + 0x354) +#define SPM_PCM_PWR_IO_EN (SPM_BASE + 0x358) +#define SPM_PCM_TIMER_VAL (SPM_BASE + 0x35c) +#define SPM_PCM_TIMER_OUT (SPM_BASE + 0x360) +#define SPM_PCM_REG0_DATA (SPM_BASE + 0x380) +#define SPM_PCM_REG1_DATA (SPM_BASE + 0x384) +#define SPM_PCM_REG2_DATA (SPM_BASE + 0x388) +#define SPM_PCM_REG3_DATA (SPM_BASE + 0x38c) +#define SPM_PCM_REG4_DATA (SPM_BASE + 0x390) +#define SPM_PCM_REG5_DATA (SPM_BASE + 0x394) +#define SPM_PCM_REG6_DATA (SPM_BASE + 0x398) +#define SPM_PCM_REG7_DATA (SPM_BASE + 0x39c) +#define SPM_PCM_REG8_DATA (SPM_BASE + 0x3a0) +#define SPM_PCM_REG9_DATA (SPM_BASE + 0x3a4) +#define SPM_PCM_REG10_DATA (SPM_BASE + 0x3a8) +#define SPM_PCM_REG11_DATA (SPM_BASE + 0x3ac) +#define SPM_PCM_REG12_DATA (SPM_BASE + 0x3b0) +#define SPM_PCM_REG13_DATA (SPM_BASE + 0x3b4) +#define SPM_PCM_REG14_DATA (SPM_BASE + 0x3b8) +#define SPM_PCM_REG15_DATA (SPM_BASE + 0x3bc) +#define SPM_PCM_EVENT_REG_STA (SPM_BASE + 0x3c0) +#define SPM_PCM_FSM_STA (SPM_BASE + 0x3c4) +#define SPM_PCM_IM_HOST_RW_PTR (SPM_BASE + 0x3c8) +#define SPM_PCM_IM_HOST_RW_DAT (SPM_BASE + 0x3cc) +#define SPM_PCM_EVENT_VECTOR4 (SPM_BASE + 0x3d0) +#define SPM_PCM_EVENT_VECTOR5 (SPM_BASE + 0x3d4) +#define SPM_PCM_EVENT_VECTOR6 (SPM_BASE + 0x3d8) +#define SPM_PCM_EVENT_VECTOR7 (SPM_BASE + 0x3dc) +#define SPM_PCM_SW_INT_SET (SPM_BASE + 0x3e0) +#define SPM_PCM_SW_INT_CLEAR (SPM_BASE + 0x3e4) +#define SPM_CLK_CON (SPM_BASE + 0x400) +#define SPM_SLEEP_PTPOD2_CON (SPM_BASE + 0x408) +#define SPM_APMCU_PWRCTL (SPM_BASE + 0x600) +#define SPM_AP_DVFS_CON_SET (SPM_BASE + 0x604) +#define SPM_AP_STANBY_CON (SPM_BASE + 0x608) +#define SPM_PWR_STATUS (SPM_BASE + 0x60c) +#define SPM_PWR_STATUS_2ND (SPM_BASE + 0x610) +#define SPM_AP_BSI_REQ (SPM_BASE + 0x614) +#define SPM_SLEEP_TIMER_STA (SPM_BASE + 0x720) +#define SPM_SLEEP_WAKEUP_EVENT_MASK (SPM_BASE + 0x810) +#define SPM_SLEEP_CPU_WAKEUP_EVENT (SPM_BASE + 0x814) +#define SPM_SLEEP_MD32_WAKEUP_EVENT_MASK (SPM_BASE + 0x818) +#define SPM_PCM_WDT_TIMER_VAL (SPM_BASE + 0x824) +#define SPM_PCM_WDT_TIMER_OUT (SPM_BASE + 0x828) +#define SPM_PCM_MD32_MAILBOX (SPM_BASE + 0x830) +#define SPM_PCM_MD32_IRQ (SPM_BASE + 0x834) +#define SPM_SLEEP_ISR_MASK (SPM_BASE + 0x900) +#define SPM_SLEEP_ISR_STATUS (SPM_BASE + 0x904) +#define SPM_SLEEP_ISR_RAW_STA (SPM_BASE + 0x910) +#define SPM_SLEEP_MD32_ISR_RAW_STA (SPM_BASE + 0x914) +#define SPM_SLEEP_WAKEUP_MISC (SPM_BASE + 0x918) +#define SPM_SLEEP_BUS_PROTECT_RDY (SPM_BASE + 0x91c) +#define SPM_SLEEP_SUBSYS_IDLE_STA (SPM_BASE + 0x920) +#define SPM_PCM_RESERVE (SPM_BASE + 0xb00) +#define SPM_PCM_RESERVE2 (SPM_BASE + 0xb04) +#define SPM_PCM_FLAGS (SPM_BASE + 0xb08) +#define SPM_PCM_SRC_REQ (SPM_BASE + 0xb0c) +#define SPM_PCM_DEBUG_CON (SPM_BASE + 0xb20) +#define SPM_CA7_CPU0_IRQ_MASK (SPM_BASE + 0xb30) +#define SPM_CA7_CPU1_IRQ_MASK (SPM_BASE + 0xb34) +#define SPM_CA7_CPU2_IRQ_MASK (SPM_BASE + 0xb38) +#define SPM_CA7_CPU3_IRQ_MASK (SPM_BASE + 0xb3c) +#define SPM_CA15_CPU0_IRQ_MASK (SPM_BASE + 0xb40) +#define SPM_CA15_CPU1_IRQ_MASK (SPM_BASE + 0xb44) +#define SPM_CA15_CPU2_IRQ_MASK (SPM_BASE + 0xb48) +#define SPM_CA15_CPU3_IRQ_MASK (SPM_BASE + 0xb4c) +#define SPM_PCM_PASR_DPD_0 (SPM_BASE + 0xb60) +#define SPM_PCM_PASR_DPD_1 (SPM_BASE + 0xb64) +#define SPM_PCM_PASR_DPD_2 (SPM_BASE + 0xb68) +#define SPM_PCM_PASR_DPD_3 (SPM_BASE + 0xb6c) +#define SPM_SLEEP_CA7_WFI0_EN (SPM_BASE + 0xf00) +#define SPM_SLEEP_CA7_WFI1_EN (SPM_BASE + 0xf04) +#define SPM_SLEEP_CA7_WFI2_EN (SPM_BASE + 0xf08) +#define SPM_SLEEP_CA7_WFI3_EN (SPM_BASE + 0xf0c) +#define SPM_SLEEP_CA15_WFI0_EN (SPM_BASE + 0xf10) +#define SPM_SLEEP_CA15_WFI1_EN (SPM_BASE + 0xf14) +#define SPM_SLEEP_CA15_WFI2_EN (SPM_BASE + 0xf18) +#define SPM_SLEEP_CA15_WFI3_EN (SPM_BASE + 0xf1c) + +#define AP_PLL_CON3 0x1020900c +#define AP_PLL_CON4 0x10209010 + +#define SPM_PROJECT_CODE 0xb16 + +#define SPM_REGWR_EN (1U << 0) +#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) + +#define SPM_CPU_PDN_DIS (1U << 0) +#define SPM_INFRA_PDN_DIS (1U << 1) +#define SPM_DDRPHY_PDN_DIS (1U << 2) +#define SPM_DUALVCORE_PDN_DIS (1U << 3) +#define SPM_PASR_DIS (1U << 4) +#define SPM_DPD_DIS (1U << 5) +#define SPM_SODI_DIS (1U << 6) +#define SPM_MEMPLL_RESET (1U << 7) +#define SPM_MAINPLL_PDN_DIS (1U << 8) +#define SPM_CPU_DVS_DIS (1U << 9) +#define SPM_CPU_DORMANT (1U << 10) +#define SPM_EXT_VSEL_GPIO103 (1U << 11) +#define SPM_DDR_HIGH_SPEED (1U << 12) +#define SPM_OPT (1U << 13) + +#define POWER_ON_VAL1_DEF 0x01011820 +#define PCM_FSM_STA_DEF 0x48490 +#define PCM_END_FSM_STA_DEF 0x08490 +#define PCM_END_FSM_STA_MASK 0x3fff0 +#define PCM_HANDSHAKE_SEND1 0xbeefbeef + +#define PCM_WDT_TIMEOUT (30 * 32768) +#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) + +#define CON0_PCM_KICK (1U << 0) +#define CON0_IM_KICK (1U << 1) +#define CON0_IM_SLEEP_DVS (1U << 3) +#define CON0_PCM_SW_RESET (1U << 15) +#define CON0_CFG_KEY (SPM_PROJECT_CODE << 16) + +#define CON1_IM_SLAVE (1U << 0) +#define CON1_MIF_APBEN (1U << 3) +#define CON1_PCM_TIMER_EN (1U << 5) +#define CON1_IM_NONRP_EN (1U << 6) +#define CON1_PCM_WDT_EN (1U << 8) +#define CON1_PCM_WDT_WAKE_MODE (1U << 9) +#define CON1_SPM_SRAM_SLP_B (1U << 10) +#define CON1_SPM_SRAM_ISO_B (1U << 11) +#define CON1_EVENT_LOCK_EN (1U << 12) +#define CON1_CFG_KEY (SPM_PROJECT_CODE << 16) + +#define PCM_PWRIO_EN_R0 (1U << 0) +#define PCM_PWRIO_EN_R7 (1U << 7) +#define PCM_RF_SYNC_R0 (1U << 16) +#define PCM_RF_SYNC_R2 (1U << 18) +#define PCM_RF_SYNC_R6 (1U << 22) +#define PCM_RF_SYNC_R7 (1U << 23) + +#define CC_SYSCLK0_EN_0 (1U << 0) +#define CC_SYSCLK0_EN_1 (1U << 1) +#define CC_SYSCLK1_EN_0 (1U << 2) +#define CC_SYSCLK1_EN_1 (1U << 3) +#define CC_SYSSETTLE_SEL (1U << 4) +#define CC_LOCK_INFRA_DCM (1U << 5) +#define CC_SRCLKENA_MASK_0 (1U << 6) +#define CC_CXO32K_RM_EN_MD1 (1U << 9) +#define CC_CXO32K_RM_EN_MD2 (1U << 10) +#define CC_CLKSQ1_SEL (1U << 12) +#define CC_DISABLE_DORM_PWR (1U << 14) +#define CC_MD32_DCM_EN (1U << 18) + +#define WFI_OP_AND 1 +#define WFI_OP_OR 0 + +#define WAKE_MISC_PCM_TIMER (1U << 19) +#define WAKE_MISC_CPU_WAKE (1U << 20) + +/* define WAKE_SRC_XXX */ +#define WAKE_SRC_SPM_MERGE (1 << 0) +#define WAKE_SRC_KP (1 << 2) +#define WAKE_SRC_WDT (1 << 3) +#define WAKE_SRC_GPT (1 << 4) +#define WAKE_SRC_EINT (1 << 6) +#define WAKE_SRC_LOW_BAT (1 << 9) +#define WAKE_SRC_MD32 (1 << 10) +#define WAKE_SRC_USB_CD (1 << 14) +#define WAKE_SRC_USB_PDN (1 << 15) +#define WAKE_SRC_AFE (1 << 20) +#define WAKE_SRC_THERM (1 << 21) +#define WAKE_SRC_CIRQ (1 << 22) +#define WAKE_SRC_SYSPWREQ (1 << 24) +#define WAKE_SRC_SEJ (1 << 27) +#define WAKE_SRC_ALL_MD32 (1 << 28) +#define WAKE_SRC_CPU_IRQ (1 << 29) + +enum wake_reason_t { + WR_NONE = 0, + WR_UART_BUSY = 1, + WR_PCM_ASSERT = 2, + WR_PCM_TIMER = 3, + WR_PCM_ABORT = 4, + WR_WAKE_SRC = 5, + WR_UNKNOWN = 6, +}; + +struct pwr_ctrl { + unsigned int pcm_flags; + unsigned int pcm_flags_cust; + unsigned int pcm_reserve; + unsigned int timer_val; + unsigned int timer_val_cust; + unsigned int wake_src; + unsigned int wake_src_cust; + unsigned int wake_src_md32; + unsigned short r0_ctrl_en; + unsigned short r7_ctrl_en; + unsigned short infra_dcm_lock; + unsigned short pcm_apsrc_req; + unsigned short mcusys_idle_mask; + unsigned short ca15top_idle_mask; + unsigned short ca7top_idle_mask; + unsigned short wfi_op; + unsigned short ca15_wfi0_en; + unsigned short ca15_wfi1_en; + unsigned short ca15_wfi2_en; + unsigned short ca15_wfi3_en; + unsigned short ca7_wfi0_en; + unsigned short ca7_wfi1_en; + unsigned short ca7_wfi2_en; + unsigned short ca7_wfi3_en; + unsigned short disp_req_mask; + unsigned short mfg_req_mask; + unsigned short md32_req_mask; + unsigned short syspwreq_mask; + unsigned short srclkenai_mask; +}; + +struct wake_status { + unsigned int assert_pc; + unsigned int r12; + unsigned int raw_sta; + unsigned int wake_misc; + unsigned int timer_out; + unsigned int r13; + unsigned int idle_sta; + unsigned int debug_flag; + unsigned int event_reg; + unsigned int isr; +}; + +struct pcm_desc { + const char *version; /* PCM code version */ + const unsigned int *base; /* binary array base */ + const unsigned int size; /* binary array size */ + const unsigned char sess; /* session number */ + const unsigned char replace; /* replace mode */ + + unsigned int vec0; /* event vector 0 config */ + unsigned int vec1; /* event vector 1 config */ + unsigned int vec2; /* event vector 2 config */ + unsigned int vec3; /* event vector 3 config */ + unsigned int vec4; /* event vector 4 config */ + unsigned int vec5; /* event vector 5 config */ + unsigned int vec6; /* event vector 6 config */ + unsigned int vec7; /* event vector 7 config */ +}; + +struct spm_lp_scen { + const struct pcm_desc *pcmdesc; + struct pwr_ctrl *pwrctrl; +}; + +#define EVENT_VEC(event, resume, imme, pc) \ + (((pc) << 16) | \ + (!!(imme) << 6) | \ + (!!(resume) << 5) | \ + ((event) & 0x1f)) + +#define spm_read(addr) mmio_read_32(addr) +#define spm_write(addr, val) mmio_write_32(addr, val) + +#define is_cpu_pdn(flags) (!((flags) & SPM_CPU_PDN_DIS)) +#define is_infra_pdn(flags) (!((flags) & SPM_INFRA_PDN_DIS)) +#define is_ddrphy_pdn(flags) (!((flags) & SPM_DDRPHY_PDN_DIS)) + +static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl, + unsigned int flags) +{ + flags &= ~SPM_EXT_VSEL_GPIO103; + + if (pwrctrl->pcm_flags_cust == 0) + pwrctrl->pcm_flags = flags; + else + pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust; +} + +static inline void set_pwrctrl_pcm_data(struct pwr_ctrl *pwrctrl, + unsigned int data) +{ + pwrctrl->pcm_reserve = data; +} + +void spm_reset_and_init_pcm(void); + +void spm_init_pcm_register(void); /* init r0 and r7 */ +void spm_set_power_control(const struct pwr_ctrl *pwrctrl); +void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); + +void spm_get_wakeup_status(struct wake_status *wakesta); +void spm_set_sysclk_settle(void); +void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl); +void spm_clean_after_wakeup(void); +enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta); +void spm_register_init(void); +void spm_go_to_hotplug(void); +void spm_init_event_vector(const struct pcm_desc *pcmdesc); +void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc); +void spm_set_sysclk_settle(void); +int is_mcdi_ready(void); +int is_hotplug_ready(void); +int is_suspend_ready(void); +void set_mcdi_ready(void); +void set_hotplug_ready(void); +void set_suspend_ready(void); +void clear_all_ready(void); +void spm_lock_init(void); +void spm_lock_get(void); +void spm_lock_release(void); +void spm_boot_init(void); + +#endif /* __SPM_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c new file mode 100644 index 0000000..b89cd97 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c @@ -0,0 +1,292 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include + +/* + * System Power Manager (SPM) is a hardware module, which controls cpu or + * system power for different power scenarios using different firmware. + * This driver controls the cpu power in cpu hotplug flow. + */ + +#define PCM_HOTPLUG_VALID_MASK 0x0000ff00 +#define PCM_HOTPLUG_VALID_SHIFT 0x8 + +/********************************************************** + * PCM sequence for CPU hotplug + **********************************************************/ +static const unsigned int hotplug_binary[] = { + 0x1900001f, 0x1020020c, 0x1950001f, 0x1020020c, 0xa9400005, 0x00000001, + 0xe1000005, 0x1910001f, 0x10006720, 0x814c9001, 0xd82000e5, 0x17c07c1f, + 0x1900001f, 0x10001220, 0x1950001f, 0x10001220, 0xa15f0405, 0xe1000005, + 0x1900001f, 0x10001228, 0x1950001f, 0x10001228, 0x810f1401, 0xd8200244, + 0x17c07c1f, 0xe2e0006d, 0xe2e0002d, 0x1a00001f, 0x100062b8, 0x1910001f, + 0x100062b8, 0xa9000004, 0x00000001, 0xe2000004, 0x1910001f, 0x100062b8, + 0x81142804, 0xd8200444, 0x17c07c1f, 0xe2e0002c, 0xe2e0003c, 0xe2e0003e, + 0xe2e0003a, 0xe2e00032, 0x1910001f, 0x1000660c, 0x81079001, 0x1950001f, + 0x10006610, 0x81479401, 0xa1001404, 0xd8000584, 0x17c07c1f, 0x1900001f, + 0x10006404, 0x1950001f, 0x10006404, 0xa1568405, 0xe1000005, 0xf0000000, + 0x17c07c1f, 0x1900001f, 0x10006404, 0x1950001f, 0x10006404, 0x89400005, + 0x0000dfff, 0xe1000005, 0xe2e00036, 0xe2e0003e, 0x1910001f, 0x1000660c, + 0x81079001, 0x1950001f, 0x10006610, 0x81479401, 0x81001404, 0xd82008c4, + 0x17c07c1f, 0xe2e0002e, 0x1a00001f, 0x100062b8, 0x1910001f, 0x100062b8, + 0x89000004, 0x0000fffe, 0xe2000004, 0x1910001f, 0x100062b8, 0x81142804, + 0xd8000ae4, 0x17c07c1f, 0xe2e0006e, 0xe2e0004e, 0xe2e0004c, 0xe2e0004d, + 0x1900001f, 0x10001220, 0x1950001f, 0x10001220, 0x89400005, 0xbfffffff, + 0xe1000005, 0x1900001f, 0x10001228, 0x1950001f, 0x10001228, 0x810f1401, + 0xd8000ce4, 0x17c07c1f, 0x1900001f, 0x1020020c, 0x1950001f, 0x1020020c, + 0x89400005, 0xfffffffe, 0xe1000005, 0xf0000000, 0x17c07c1f, 0x1212841f, + 0xe2e00036, 0xe2e0003e, 0x1380201f, 0xe2e0003c, 0xe2a00000, 0x1b80001f, + 0x20000080, 0xe2e0007c, 0x1b80001f, 0x20000003, 0xe2e0005c, 0xe2e0004c, + 0xe2e0004d, 0xf0000000, 0x17c07c1f, 0xe2e0004f, 0xe2e0006f, 0xe2e0002f, + 0xe2a00001, 0x1b80001f, 0x20000080, 0xe2e0002e, 0xe2e0003e, 0xe2e00032, + 0xf0000000, 0x17c07c1f, 0x1212841f, 0xe2e00026, 0xe2e0002e, 0x1380201f, + 0x1a00001f, 0x100062b4, 0x1910001f, 0x100062b4, 0x81322804, 0xe2000004, + 0x81202804, 0xe2000004, 0x1b80001f, 0x20000034, 0x1910001f, 0x100062b4, + 0x81142804, 0xd8001404, 0x17c07c1f, 0xe2e0000e, 0xe2e0000c, 0xe2e0000d, + 0xf0000000, 0x17c07c1f, 0xe2e0002d, 0x1a00001f, 0x100062b4, 0x1910001f, + 0x100062b4, 0xa1002804, 0xe2000004, 0xa1122804, 0xe2000004, 0x1b80001f, + 0x20000080, 0x1910001f, 0x100062b4, 0x81142804, 0xd82016a4, 0x17c07c1f, + 0xe2e0002f, 0xe2e0002b, 0xe2e00023, 0x1380201f, 0xe2e00022, 0xf0000000, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x1840001f, 0x00000001, 0x1840001f, 0x00000001, + 0x1840001f, 0x00000001, 0xa1d48407, 0x1b00001f, 0x2f7be75f, 0xe8208000, + 0x10006354, 0xfffe7b47, 0xa1d10407, 0x1b80001f, 0x20000020, 0x17c07c1f, + 0x1910001f, 0x10006b00, 0x81461001, 0xb14690a1, 0xd82044e5, 0x17c07c1f, + 0x1910001f, 0x10006610, 0x81079001, 0xd80044e4, 0x17c07c1f, 0x1990001f, + 0x10006b00, 0x81421801, 0x82429801, 0x81402405, 0xd80044e5, 0x17c07c1f, + 0x1a40001f, 0x100062b0, 0x1280041f, 0xc24007a0, 0x17c07c1f, 0x1910001f, + 0x10006b00, 0x81449001, 0xd8204be5, 0x17c07c1f, 0x1910001f, 0x10006b00, + 0x81009001, 0xd8204984, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81051001, + 0xd8204be4, 0x17c07c1f, 0x1910001f, 0x10006720, 0x81489001, 0xd82046c5, + 0x17c07c1f, 0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, 0xc24010e0, + 0x17c07c1f, 0x1910001f, 0x1000660c, 0x81051001, 0x1950001f, 0x10006610, + 0x81451401, 0xa1001404, 0xd8004824, 0x17c07c1f, 0xd0004b00, 0x17c07c1f, + 0x17c07c1f, 0x1910001f, 0x10006610, 0x81051001, 0xd8004be4, 0x17c07c1f, + 0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, 0xc2400ee0, 0x17c07c1f, + 0x1910001f, 0x10006b00, 0x89000004, 0xfffffdff, 0x1940001f, 0x10006b00, + 0xe1400004, 0x17c07c1f, 0x1910001f, 0x10006b00, 0x81451001, 0xd8205305, + 0x17c07c1f, 0x1910001f, 0x10006b00, 0x81011001, 0xd82050a4, 0x17c07c1f, + 0x1910001f, 0x10006610, 0x81059001, 0xd8205304, 0x17c07c1f, 0x1910001f, + 0x10006720, 0x81491001, 0xd8204de5, 0x17c07c1f, 0x1a40001f, 0x1000621c, + 0x1a80001f, 0x1000626c, 0xc24010e0, 0x17c07c1f, 0x1910001f, 0x1000660c, + 0x81059001, 0x1950001f, 0x10006610, 0x81459401, 0xa1001404, 0xd8004f44, + 0x17c07c1f, 0xd0005220, 0x17c07c1f, 0x17c07c1f, 0x1910001f, 0x10006610, + 0x81059001, 0xd8005304, 0x17c07c1f, 0x1a40001f, 0x1000621c, 0x1a80001f, + 0x1000626c, 0xc2400ee0, 0x17c07c1f, 0x1910001f, 0x10006b00, 0x89000004, + 0xfffffbff, 0x1940001f, 0x10006b00, 0xe1400004, 0x17c07c1f, 0x1910001f, + 0x10006b00, 0x81459001, 0xd8205a25, 0x17c07c1f, 0x1910001f, 0x10006b00, + 0x81019001, 0xd82057c4, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81061001, + 0xd8205a24, 0x17c07c1f, 0x1910001f, 0x10006720, 0x81499001, 0xd8205505, + 0x17c07c1f, 0x1a40001f, 0x10006220, 0x1a80001f, 0x10006274, 0xc24010e0, + 0x17c07c1f, 0x1910001f, 0x1000660c, 0x81061001, 0x1950001f, 0x10006610, + 0x81461401, 0xa1001404, 0xd8005664, 0x17c07c1f, 0xd0005940, 0x17c07c1f, + 0x17c07c1f, 0x1910001f, 0x10006610, 0x81061001, 0xd8005a24, 0x17c07c1f, + 0x1a40001f, 0x10006220, 0x1a80001f, 0x10006274, 0xc2400ee0, 0x17c07c1f, + 0x1910001f, 0x10006b00, 0x89000004, 0xfffff7ff, 0x1940001f, 0x10006b00, + 0xe1400004, 0x17c07c1f, 0x1910001f, 0x10006b00, 0x81461001, 0xd8206185, + 0x17c07c1f, 0x1910001f, 0x10006b00, 0x81021001, 0xd8205ec4, 0x17c07c1f, + 0x1910001f, 0x10006610, 0x81081001, 0xd8206184, 0x17c07c1f, 0x1910001f, + 0x10006720, 0x814a1001, 0xd8205c25, 0x17c07c1f, 0x1a40001f, 0x100062a0, + 0x1280041f, 0xc2401540, 0x17c07c1f, 0x1910001f, 0x1000660c, 0x81081001, + 0x1950001f, 0x10006610, 0x81481401, 0xa1001404, 0xd8005d64, 0x17c07c1f, + 0xd00060a0, 0x17c07c1f, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81479001, + 0x81881001, 0x69a00006, 0x00000000, 0x81401805, 0xd8206185, 0x17c07c1f, + 0x1a40001f, 0x100062a0, 0x1280041f, 0xc2401240, 0x17c07c1f, 0x1910001f, + 0x10006b00, 0x89000004, 0xffffefff, 0x1940001f, 0x10006b00, 0xe1400004, + 0x17c07c1f, 0x1910001f, 0x10006b00, 0x81469001, 0xd82068e5, 0x17c07c1f, + 0x1910001f, 0x10006b00, 0x81029001, 0xd8206624, 0x17c07c1f, 0x1910001f, + 0x10006610, 0x81089001, 0xd82068e4, 0x17c07c1f, 0x1910001f, 0x10006720, + 0x814a9001, 0xd8206385, 0x17c07c1f, 0x1a40001f, 0x100062a4, 0x1290841f, + 0xc2401540, 0x17c07c1f, 0x1910001f, 0x1000660c, 0x81089001, 0x1950001f, + 0x10006610, 0x81489401, 0xa1001404, 0xd80064c4, 0x17c07c1f, 0xd0006800, + 0x17c07c1f, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81479001, 0x81889001, + 0x69a00006, 0x00000000, 0x81401805, 0xd82068e5, 0x17c07c1f, 0x1a40001f, + 0x100062a4, 0x1290841f, 0xc2401240, 0x17c07c1f, 0x1910001f, 0x10006b00, + 0x89000004, 0xffffdfff, 0x1940001f, 0x10006b00, 0xe1400004, 0x1910001f, + 0x10006610, 0x81479001, 0x81881001, 0x69600005, 0x00000000, 0xa1401805, + 0x81889001, 0xa1401805, 0xd8006bc5, 0x17c07c1f, 0x1910001f, 0x10006b00, + 0x81421001, 0x82429001, 0x82802405, 0xd8206bca, 0x17c07c1f, 0x1a40001f, + 0x100062b0, 0x1280041f, 0xc2400000, 0x17c07c1f, 0x1990001f, 0x10006b00, + 0x89800006, 0x00003f00, 0x69200006, 0x00000000, 0xd82041e4, 0x17c07c1f, + 0x1990001f, 0x10006320, 0x69200006, 0xbeefbeef, 0xd8006dc4, 0x17c07c1f, + 0xd00041e0, 0x17c07c1f, 0x1910001f, 0x10006358, 0x810b1001, 0xd8006dc4, + 0x17c07c1f, 0x1980001f, 0xdeaddead, 0x19c0001f, 0x01411820, 0xf0000000 +}; +static const struct pcm_desc hotplug_pcm = { + .version = "pcm_power_down_mt8173_V37", + .base = hotplug_binary, + .size = 888, + .sess = 2, + .replace = 0, +}; + +static struct pwr_ctrl hotplug_ctrl = { + .wake_src = 0, + .wake_src_md32 = 0, + .wfi_op = WFI_OP_OR, + .mcusys_idle_mask = 1, + .ca7top_idle_mask = 1, + .ca15top_idle_mask = 1, + .disp_req_mask = 1, + .mfg_req_mask = 1, + .md32_req_mask = 1, + .syspwreq_mask = 1, + .pcm_flags = 0, +}; + +static const struct spm_lp_scen spm_hotplug = { + .pcmdesc = &hotplug_pcm, + .pwrctrl = &hotplug_ctrl, +}; + +void spm_go_to_hotplug(void) +{ + const struct pcm_desc *pcmdesc = spm_hotplug.pcmdesc; + struct pwr_ctrl *pwrctrl = spm_hotplug.pwrctrl; + + set_pwrctrl_pcm_flags(pwrctrl, 0); + spm_reset_and_init_pcm(); + spm_kick_im_to_fetch(pcmdesc); + spm_set_power_control(pwrctrl); + spm_set_wakeup_event(pwrctrl); + spm_kick_pcm_to_run(pwrctrl); +} + +void spm_clear_hotplug(void) +{ + /* Inform SPM that CPU wants to program CPU_WAKEUP_EVENT and + * DISABLE_CPU_DROM */ + + mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_HANDSHAKE_SEND1); + mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); + + /* Wait SPM's response, can't use sleep api */ + while ((mmio_read_32(SPM_PCM_FSM_STA) & PCM_END_FSM_STA_MASK) + != PCM_END_FSM_STA_DEF) + ; + + /* no hotplug pcm running */ + clear_all_ready(); +} + +void spm_hotplug_on(unsigned long mpidr) +{ + unsigned long linear_id; + + linear_id = platform_get_core_pos(mpidr); + spm_lock_get(); + if (is_hotplug_ready() == 0) { + spm_mcdi_wakeup_all_cores(); + mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK); + spm_go_to_hotplug(); + set_hotplug_ready(); + } + /* turn on CPUx */ + mmio_clrsetbits_32(SPM_PCM_RESERVE, + PCM_HOTPLUG_VALID_MASK | (1 << linear_id), + 1 << (linear_id + PCM_HOTPLUG_VALID_SHIFT)); + spm_lock_release(); +} + +void spm_hotplug_off(unsigned long mpidr) +{ + unsigned long linear_id; + + linear_id = platform_get_core_pos(mpidr); + spm_lock_get(); + if (is_hotplug_ready() == 0) { + spm_mcdi_wakeup_all_cores(); + mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK); + spm_go_to_hotplug(); + set_hotplug_ready(); + } + mmio_clrsetbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK, + (1 << linear_id) | + (1 << (linear_id + PCM_HOTPLUG_VALID_SHIFT))); + spm_lock_release(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.h new file mode 100644 index 0000000..fa90ab9 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __SPM_HOTPLUG_H__ +#define __SPM_HOTPLUG_H__ + +void spm_clear_hotplug(void); +void spm_hotplug_off(unsigned long mpidr); +void spm_hotplug_on(unsigned long mpidr); + +#endif /* __SPM_HOTPLUG_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c new file mode 100644 index 0000000..7aacdec --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c @@ -0,0 +1,521 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * System Power Manager (SPM) is a hardware module, which controls cpu or + * system power for different power scenarios using different firmware. + * This driver controls the cpu power in cpu idle power saving state. + */ + +#define WAKE_SRC_FOR_MCDI \ + (WAKE_SRC_KP | WAKE_SRC_GPT | WAKE_SRC_EINT | \ + WAKE_SRC_MD32 | WAKE_SRC_USB_CD | WAKE_SRC_USB_PDN | \ + WAKE_SRC_AFE | WAKE_SRC_THERM | WAKE_SRC_CIRQ | \ + WAKE_SRC_SYSPWREQ | WAKE_SRC_CPU_IRQ) +#define PCM_MCDI_HANDSHAKE_SYNC 0xbeefbeef +#define PCM_MCDI_HANDSHAKE_ACK 0xdeaddead +#define PCM_MCDI_UPDATE_INFORM 0xabcdabcd +#define PCM_MCDI_CKECK_DONE 0x12345678 +#define PCM_MCDI_ALL_CORE_AWAKE 0x0 +#define PCM_MCDI_OFFLOADED 0xaa55aa55 +#define PCM_MCDI_CA72_CPUTOP_PWRCTL (0x1 << 16) +#define PCM_MCDI_CA53_CPUTOP_PWRCTL (0x1 << 17) +#define PCM_MCDI_CA72_PWRSTA_SHIFT 16 +#define PCM_MCDI_CA53_PWRSTA_SHIFT 9 + +static const unsigned int mcdi_binary[] = { + 0x1a10001f, 0x10006b04, 0x1890001f, 0x10006b6c, 0x1a40001f, 0x10006210, + 0x18d0001f, 0x10006210, 0x81002001, 0xd82001c4, 0x17c07c1f, 0xa0900402, + 0xc2401540, 0x17c07c1f, 0x81052001, 0xd8200284, 0x17c07c1f, 0xa0950402, + 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x10006230, 0x18d0001f, 0x10006230, + 0x8100a001, 0xd82003c4, 0x17c07c1f, 0xa0908402, 0xc2401540, 0x17c07c1f, + 0x8105a001, 0xd8200484, 0x17c07c1f, 0xa0958402, 0xc2401b80, 0x17c07c1f, + 0x1a40001f, 0x10006238, 0x18d0001f, 0x10006238, 0x81012001, 0xd82005c4, + 0x17c07c1f, 0xa0910402, 0xc2401540, 0x17c07c1f, 0x81062001, 0xd8200684, + 0x17c07c1f, 0xa0960402, 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x1000623c, + 0x18d0001f, 0x1000623c, 0x8101a001, 0xd82007c4, 0x17c07c1f, 0xa0918402, + 0xc2401540, 0x17c07c1f, 0x8106a001, 0xd8200884, 0x17c07c1f, 0xa0968402, + 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x10006298, 0x18d0001f, 0x10006298, + 0x81022001, 0xd82009c4, 0x17c07c1f, 0xa0920402, 0xc2401540, 0x17c07c1f, + 0x81072001, 0xd8200a84, 0x17c07c1f, 0xa0970402, 0xc2401b80, 0x17c07c1f, + 0x1a40001f, 0x1000629c, 0x18d0001f, 0x1000629c, 0x8102a001, 0xd8200bc4, + 0x17c07c1f, 0xa0928402, 0xc2401540, 0x17c07c1f, 0x8107a001, 0xd8200c84, + 0x17c07c1f, 0xa0978402, 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x100062c4, + 0x18d0001f, 0x100062c4, 0x81032001, 0xd8200dc4, 0x17c07c1f, 0xa0930402, + 0xc2401540, 0x17c07c1f, 0x81082001, 0xd8200e84, 0x17c07c1f, 0xa0980402, + 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x100062c0, 0x18d0001f, 0x100062c0, + 0x8103a001, 0xd8200fc4, 0x17c07c1f, 0xa0938402, 0xc2401540, 0x17c07c1f, + 0x8108a001, 0xd8201084, 0x17c07c1f, 0xa0988402, 0xc2401b80, 0x17c07c1f, + 0x1a40001f, 0x10006214, 0x18d0001f, 0x10006214, 0x81042001, 0xd82011c4, + 0x17c07c1f, 0xa0940402, 0xc2401540, 0x17c07c1f, 0x81092001, 0xd8201284, + 0x17c07c1f, 0xa0990402, 0xc2401b80, 0x17c07c1f, 0x1a40001f, 0x100062cc, + 0x18d0001f, 0x100062cc, 0x8104a001, 0xd82013c4, 0x17c07c1f, 0xa0948402, + 0xc2401540, 0x17c07c1f, 0x8109a001, 0xd8201484, 0x17c07c1f, 0xa0998402, + 0xc2401b80, 0x17c07c1f, 0x1900001f, 0x10006b6c, 0x80802002, 0xe1000002, + 0xf0000000, 0x17c07c1f, 0xa8c00003, 0x00000004, 0xe2400003, 0xa8c00003, + 0x00000008, 0xe2400003, 0x1b80001f, 0x00000020, 0x88c00003, 0xffffffef, + 0xe2400003, 0x88c00003, 0xfffffffd, 0xe2400003, 0xa8c00003, 0x00000001, + 0xe2400003, 0x88c00003, 0xfffff0ff, 0xe2400003, 0x1b80001f, 0x20000080, + 0x1a90001f, 0x10001220, 0x69200009, 0x1000623c, 0xd8001984, 0x17c07c1f, + 0x69200009, 0x10006214, 0xd8001a64, 0x17c07c1f, 0xd0001b00, 0x17c07c1f, + 0x1900001f, 0x10001220, 0x8a80000a, 0xfffffff9, 0xe100000a, 0xd0001b00, + 0x17c07c1f, 0x1900001f, 0x10001220, 0x8a80000a, 0xff1fbfff, 0xe100000a, + 0x1b80001f, 0x20000080, 0xf0000000, 0x17c07c1f, 0x1a90001f, 0x10001220, + 0x69200009, 0x1000623c, 0xd8001d04, 0x17c07c1f, 0x69200009, 0x10006214, + 0xd8001de4, 0x17c07c1f, 0xd0001e80, 0x17c07c1f, 0x1900001f, 0x10001220, + 0xaa80000a, 0x00000006, 0xe100000a, 0xd0001e80, 0x17c07c1f, 0x1900001f, + 0x10001220, 0xaa80000a, 0x00e04000, 0xe100000a, 0x1b80001f, 0x20000080, + 0x69200009, 0x10006214, 0xd8001fe4, 0x17c07c1f, 0xa8c00003, 0x00000f00, + 0xe2400003, 0xd0002040, 0x17c07c1f, 0xa8c00003, 0x00003f00, 0xe2400003, + 0x1b80001f, 0x20000080, 0xa8c00003, 0x00000002, 0xe2400003, 0x88c00003, + 0xfffffffe, 0xe2400003, 0xa8c00003, 0x00000010, 0xe2400003, 0x88c00003, + 0xfffffffb, 0xe2400003, 0x88c00003, 0xfffffff7, 0xe2400003, 0xf0000000, + 0x17c07c1f, 0xe2e00036, 0xe2e0003e, 0x1b80001f, 0x00000020, 0xe2e0003c, + 0xe8208000, 0x10006244, 0x00000000, 0x1b80001f, 0x20000080, 0xe2e0007c, + 0x1b80001f, 0x20000003, 0xe2e0005c, 0xe2e0004c, 0xe2e0004d, 0xf0000000, + 0x17c07c1f, 0xe2e0004f, 0xe2e0006f, 0xe2e0002f, 0xe8208000, 0x10006244, + 0x00000001, 0x1b80001f, 0x20000080, 0xe2e0002e, 0xe2e0003e, 0xe2e0003a, + 0xe2e00032, 0x1b80001f, 0x00000020, 0xf0000000, 0x17c07c1f, 0xe2e00036, + 0xe2e0003e, 0x1b80001f, 0x00000020, 0xe2e0003c, 0xe2a00000, 0x1b80001f, + 0x20000080, 0xe2e0007c, 0x1b80001f, 0x20000003, 0xe2e0005c, 0xe2e0004c, + 0xe2e0004d, 0xf0000000, 0x17c07c1f, 0xe2e0004f, 0xe2e0006f, 0xe2e0002f, + 0xe2a00001, 0x1b80001f, 0x20000080, 0xe2e0002e, 0xe2e0003e, 0xe2e0003a, + 0xe2e00032, 0xf0000000, 0x17c07c1f, 0xe2e00026, 0xe2e0002e, 0x1b80001f, + 0x00000020, 0x1a00001f, 0x100062b4, 0x1910001f, 0x100062b4, 0x81322804, + 0xe2000004, 0x81202804, 0xe2000004, 0x1b80001f, 0x20000080, 0xe2e0000e, + 0xe2e0000c, 0xe2e0000d, 0xf0000000, 0x17c07c1f, 0xe2e0002d, 0x1a00001f, + 0x100062b4, 0x1910001f, 0x100062b4, 0xa1002804, 0xe2000004, 0xa1122804, + 0xe2000004, 0x1b80001f, 0x20000080, 0xe2e0002f, 0xe2e0002b, 0xe2e00023, + 0x1b80001f, 0x00000020, 0xe2e00022, 0xf0000000, 0x17c07c1f, 0x1910001f, + 0x1000660c, 0x1a10001f, 0x10006610, 0xa2002004, 0x89000008, 0x00030000, + 0xd80036c4, 0x17c07c1f, 0x8207a001, 0xd82036c8, 0x17c07c1f, 0x1900001f, + 0x1020020c, 0x1a10001f, 0x1020020c, 0xaa000008, 0x00000001, 0xe1000008, + 0x1910001f, 0x1020020c, 0x81001001, 0xd8203184, 0x17c07c1f, 0x1910001f, + 0x10006720, 0x820c9001, 0xd8203228, 0x17c07c1f, 0x1900001f, 0x10001220, + 0x1a10001f, 0x10001220, 0xa21f0408, 0xe1000008, 0x1b80001f, 0x20000080, + 0xe2e0006d, 0xe2e0002d, 0x1a00001f, 0x100062b8, 0x1910001f, 0x100062b8, + 0xa9000004, 0x00000001, 0xe2000004, 0x1b80001f, 0x20000080, 0xe2e0002c, + 0xe2e0003c, 0xe2e0003e, 0xe2e0003a, 0xe2e00032, 0x1b80001f, 0x00000020, + 0x1900001f, 0x10006404, 0x1a10001f, 0x10006404, 0xa2168408, 0xe1000008, + 0xf0000000, 0x17c07c1f, 0x1a10001f, 0x10006610, 0x8207a001, 0xd8003e68, + 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8a000008, 0x00003030, 0xb900010c, + 0x01000001, 0xd8203e64, 0x17c07c1f, 0x1900001f, 0x10006404, 0x1a10001f, + 0x10006404, 0x8a000008, 0x0000dfff, 0xe1000008, 0xe2e00036, 0xe2e0003e, + 0x1b80001f, 0x00000020, 0xe2e0002e, 0x1a00001f, 0x100062b8, 0x1910001f, + 0x100062b8, 0x89000004, 0x0000fffe, 0xe2000004, 0x1b80001f, 0x20000080, + 0xe2e0006e, 0xe2e0004e, 0xe2e0004c, 0xe2e0004d, 0x1900001f, 0x10001220, + 0x1a10001f, 0x10001220, 0x8a000008, 0xbfffffff, 0xe1000008, 0x1b80001f, + 0x20000080, 0x1900001f, 0x1020020c, 0x1a10001f, 0x1020020c, 0x8a000008, + 0xfffffffe, 0xe1000008, 0x1910001f, 0x1020020c, 0x81001001, 0xd8003dc4, + 0x17c07c1f, 0xf0000000, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x1840001f, 0x00000001, 0x11407c1f, 0xe8208000, + 0x10006310, 0x0b160008, 0x1900001f, 0x000f7bde, 0x1a00001f, 0x10200268, + 0xe2000004, 0xe8208000, 0x10006600, 0x00000000, 0x69200006, 0xbeefbeef, + 0xd8204584, 0x17c07c1f, 0x1910001f, 0x10006358, 0x810b1001, 0xd8004244, + 0x17c07c1f, 0x1980001f, 0xdeaddead, 0x69200006, 0xabcdabcd, 0xd8204324, + 0x17c07c1f, 0x88900001, 0x10006814, 0x1910001f, 0x10006400, 0x81271002, + 0x1880001f, 0x10006600, 0xe0800004, 0x1910001f, 0x10006358, 0x810b1001, + 0xd80044a4, 0x17c07c1f, 0x1980001f, 0x12345678, 0x60a07c05, 0x89100002, + 0x10006600, 0x80801001, 0xd8007bc2, 0x17c07c1f, 0x1890001f, 0x10006b00, + 0x82090801, 0xc8800008, 0x17c07c1f, 0x1b00001f, 0x3fffe7ff, 0x8a00000c, + 0x3fffe7ff, 0xd82041c8, 0x17c07c1f, 0x1b80001f, 0xd0010000, 0x1a10001f, + 0x10006720, 0x82002001, 0x82201408, 0xd8204988, 0x17c07c1f, 0x1a40001f, + 0x10006200, 0x1a80001f, 0x1000625c, 0xc24028e0, 0x17c07c1f, 0xa1400405, + 0x1a10001f, 0x10006720, 0x8200a001, 0x82209408, 0xd8204b28, 0x17c07c1f, + 0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, 0xc24028e0, 0x17c07c1f, + 0xa1508405, 0x1a10001f, 0x10006720, 0x82012001, 0x82211408, 0xd8204cc8, + 0x17c07c1f, 0x1a40001f, 0x1000621c, 0x1a80001f, 0x1000626c, 0xc24028e0, + 0x17c07c1f, 0xa1510405, 0x1a10001f, 0x10006720, 0x8201a001, 0x82219408, + 0xd8204e68, 0x17c07c1f, 0x1a40001f, 0x10006220, 0x1a80001f, 0x10006274, + 0xc24028e0, 0x17c07c1f, 0xa1518405, 0x1a10001f, 0x10006720, 0x82022001, + 0x82221408, 0xd8204fe8, 0x17c07c1f, 0x1a40001f, 0x100062a0, 0x1280041f, + 0xc2402cc0, 0x17c07c1f, 0xa1520405, 0x1a10001f, 0x10006720, 0x8202a001, + 0x82229408, 0xd8205168, 0x17c07c1f, 0x1a40001f, 0x100062a4, 0x1290841f, + 0xc2402cc0, 0x17c07c1f, 0xa1528405, 0x1a10001f, 0x10006720, 0x82032001, + 0x82231408, 0xd8205248, 0x17c07c1f, 0xa1530405, 0x1a10001f, 0x10006720, + 0x8203a001, 0x82239408, 0xd8205328, 0x17c07c1f, 0xa1538405, 0x1a10001f, + 0x10006b00, 0x8108a001, 0xd8205e84, 0x17c07c1f, 0x1910001f, 0x1000660c, + 0x1a10001f, 0x10006610, 0xa2002004, 0x89000008, 0x00001e00, 0xd8005944, + 0x17c07c1f, 0x82042001, 0xd8205948, 0x17c07c1f, 0x1900001f, 0x1020002c, + 0x1a10001f, 0x1020002c, 0xaa000008, 0x00000010, 0xe1000008, 0x1910001f, + 0x10006720, 0x820c1001, 0xd8205628, 0x17c07c1f, 0x1900001f, 0x10001250, + 0x1a10001f, 0x10001250, 0xa2110408, 0xe1000008, 0x1b80001f, 0x20000080, + 0x1900001f, 0x10001220, 0x1a10001f, 0x10001220, 0xa21e8408, 0xe1000008, + 0x1b80001f, 0x20000080, 0x1a40001f, 0x10006208, 0xc24024e0, 0x17c07c1f, + 0x1a10001f, 0x10006610, 0x82042001, 0xd8005e88, 0x17c07c1f, 0x1a10001f, + 0x10006918, 0x8a000008, 0x00000f0f, 0xba00010c, 0x1fffe7ff, 0xd8205e88, + 0x17c07c1f, 0x1a40001f, 0x10006208, 0xc24022a0, 0x17c07c1f, 0x1900001f, + 0x10001250, 0x1a10001f, 0x10001250, 0x8a000008, 0xfffffffb, 0xe1000008, + 0x1b80001f, 0x20000080, 0x1900001f, 0x10001220, 0x1a10001f, 0x10001220, + 0x8a000008, 0xdfffffff, 0xe1000008, 0x1b80001f, 0x20000080, 0x1900001f, + 0x1020002c, 0x1a10001f, 0x1020002c, 0x8a000008, 0xffffffef, 0xe1000008, + 0x1a10001f, 0x10006b00, 0x81082001, 0xd8205fa4, 0x17c07c1f, 0x1a40001f, + 0x100062b0, 0xc2402f20, 0x17c07c1f, 0x1b80001f, 0x20000208, 0xd8207b8c, + 0x17c07c1f, 0x1a40001f, 0x100062b0, 0xc2403700, 0x17c07c1f, 0x81001401, + 0xd8206424, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x81002001, 0xb1042081, + 0xb900008c, 0x1fffe7ff, 0xd8206424, 0x17c07c1f, 0x1a40001f, 0x10006200, + 0x1a80001f, 0x1000625c, 0xc24026e0, 0x17c07c1f, 0x89400005, 0xfffffffe, + 0xe8208000, 0x10006f00, 0x00000000, 0xe8208000, 0x10006b30, 0x00000000, + 0xe8208000, 0x100063e0, 0x00000001, 0x81009401, 0xd82067a4, 0x17c07c1f, + 0x1a10001f, 0x10006918, 0x8100a001, 0xb104a081, 0xb900008c, 0x01000001, + 0xd82067a4, 0x17c07c1f, 0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, + 0xc24026e0, 0x17c07c1f, 0x89400005, 0xfffffffd, 0xe8208000, 0x10006f04, + 0x00000000, 0xe8208000, 0x10006b34, 0x00000000, 0xe8208000, 0x100063e0, + 0x00000002, 0x81011401, 0xd8206b24, 0x17c07c1f, 0x1a10001f, 0x10006918, + 0x81012001, 0xb1052081, 0xb900008c, 0x01000001, 0xd8206b24, 0x17c07c1f, + 0x1a40001f, 0x1000621c, 0x1a80001f, 0x1000626c, 0xc24026e0, 0x17c07c1f, + 0x89400005, 0xfffffffb, 0xe8208000, 0x10006f08, 0x00000000, 0xe8208000, + 0x10006b38, 0x00000000, 0xe8208000, 0x100063e0, 0x00000004, 0x81019401, + 0xd8206ea4, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8101a001, 0xb105a081, + 0xb900008c, 0x01000001, 0xd8206ea4, 0x17c07c1f, 0x1a40001f, 0x10006220, + 0x1a80001f, 0x10006274, 0xc24026e0, 0x17c07c1f, 0x89400005, 0xfffffff7, + 0xe8208000, 0x10006f0c, 0x00000000, 0xe8208000, 0x10006b3c, 0x00000000, + 0xe8208000, 0x100063e0, 0x00000008, 0x1a10001f, 0x10006610, 0x8207a001, + 0xd8207608, 0x17c07c1f, 0x81021401, 0xd82072a4, 0x17c07c1f, 0x1a10001f, + 0x10006918, 0x81022001, 0xb1062081, 0xb900008c, 0x01000001, 0xd82072a4, + 0x17c07c1f, 0x1a40001f, 0x100062a0, 0x1280041f, 0xc2402a60, 0x17c07c1f, + 0x89400005, 0xffffffef, 0xe8208000, 0x10006f10, 0x00000000, 0xe8208000, + 0x10006b40, 0x00000000, 0xe8208000, 0x100063e0, 0x00000010, 0x81029401, + 0xd8207604, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8102a001, 0xb106a081, + 0xb900008c, 0x01000001, 0xd8207604, 0x17c07c1f, 0x1a40001f, 0x100062a4, + 0x1290841f, 0xc2402a60, 0x17c07c1f, 0x89400005, 0xffffffdf, 0xe8208000, + 0x10006f14, 0x00000000, 0xe8208000, 0x10006b44, 0x00000000, 0xe8208000, + 0x100063e0, 0x00000020, 0x81031401, 0xd82078c4, 0x17c07c1f, 0x1a10001f, + 0x10006918, 0x81032001, 0xb1072081, 0xb900008c, 0x01000001, 0xd82078c4, + 0x17c07c1f, 0x89400005, 0xffffffbf, 0xe8208000, 0x10006f18, 0x00000000, + 0xe8208000, 0x10006b48, 0x00000000, 0xe8208000, 0x100063e0, 0x00000040, + 0x81039401, 0xd8207b84, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8103a001, + 0xb107a081, 0xb900008c, 0x01000001, 0xd8207b84, 0x17c07c1f, 0x89400005, + 0xffffff7f, 0xe8208000, 0x10006f1c, 0x00000000, 0xe8208000, 0x10006b4c, + 0x00000000, 0xe8208000, 0x100063e0, 0x00000080, 0xd00041c0, 0x17c07c1f, + 0xe8208000, 0x10006600, 0x00000000, 0x1ac0001f, 0x55aa55aa, 0x1940001f, + 0xaa55aa55, 0x1b80001f, 0x00001000, 0xf0000000, 0x17c07c1f +}; + +static const struct pcm_desc mcdi_pcm = { + .version = "pcm_mcdi_mt8173_20160401_v1", + .base = mcdi_binary, + .size = 1019, + .sess = 2, + .replace = 0, +}; + +static struct pwr_ctrl mcdi_ctrl = { + .wake_src = WAKE_SRC_FOR_MCDI, + .wake_src_md32 = 0, + .wfi_op = WFI_OP_OR, + .mcusys_idle_mask = 1, + .ca7top_idle_mask = 1, + .ca15top_idle_mask = 1, + .disp_req_mask = 1, + .mfg_req_mask = 1, + .md32_req_mask = 1, +}; + +static const struct spm_lp_scen spm_mcdi = { + .pcmdesc = &mcdi_pcm, + .pwrctrl = &mcdi_ctrl, +}; + +void spm_mcdi_cpu_wake_up_event(int wake_up_event, int disable_dormant_power) +{ + if (((mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT) & 0x1) == 1) + && ((mmio_read_32(SPM_CLK_CON) & CC_DISABLE_DORM_PWR) == 0)) { + /* MCDI is offload? */ + INFO("%s: SPM_SLEEP_CPU_WAKEUP_EVENT:%x, SPM_CLK_CON %x", + __func__, mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT), + mmio_read_32(SPM_CLK_CON)); + return; + } + /* Inform SPM that CPU wants to program CPU_WAKEUP_EVENT and + * DISABLE_CPU_DROM */ + mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_HANDSHAKE_SYNC); + mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); + + /* Wait SPM's response, can't use sleep api */ + while (mmio_read_32(SPM_PCM_REG6_DATA) != PCM_MCDI_HANDSHAKE_ACK) + ; + + if (disable_dormant_power) { + mmio_setbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR); + while (mmio_read_32(SPM_CLK_CON) != + (mmio_read_32(SPM_CLK_CON) | CC_DISABLE_DORM_PWR)) + ; + + } else { + mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR); + while (mmio_read_32(SPM_CLK_CON) != + (mmio_read_32(SPM_CLK_CON) & ~CC_DISABLE_DORM_PWR)) + ; + } + + mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, wake_up_event); + + while (mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT) != wake_up_event) + ; + + /* Inform SPM to see updated setting */ + mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_UPDATE_INFORM); + mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); + + while (mmio_read_32(SPM_PCM_REG6_DATA) != PCM_MCDI_CKECK_DONE) + ; + /* END OF sequence */ + + mmio_write_32(SPM_PCM_REG_DATA_INI, 0x0); + mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6); + mmio_write_32(SPM_PCM_PWR_IO_EN, 0); +} + +void spm_mcdi_wakeup_all_cores(void) +{ + if (is_mcdi_ready() == 0) + return; + + spm_mcdi_cpu_wake_up_event(1, 1); + while (mmio_read_32(SPM_PCM_REG5_DATA) != PCM_MCDI_ALL_CORE_AWAKE) + ; + spm_mcdi_cpu_wake_up_event(1, 0); + while (mmio_read_32(SPM_PCM_REG5_DATA) != PCM_MCDI_OFFLOADED) + ; + + spm_clean_after_wakeup(); + clear_all_ready(); +} + +static void spm_mcdi_wfi_sel_enter(unsigned long mpidr) +{ + int core_id_val = mpidr & MPIDR_CPU_MASK; + int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; + + /* SPM WFI Select by core number */ + if (cluster_id) { + switch (core_id_val) { + case 0: + mmio_write_32(SPM_CA15_CPU0_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, 1); + break; + case 1: + mmio_write_32(SPM_CA15_CPU1_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, 1); + break; + case 2: + mmio_write_32(SPM_CA15_CPU2_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, 1); + break; + case 3: + mmio_write_32(SPM_CA15_CPU3_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, 1); + break; + default: + break; + } + } else { + switch (core_id_val) { + case 0: + mmio_write_32(SPM_CA7_CPU0_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, 1); + break; + case 1: + mmio_write_32(SPM_CA7_CPU1_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, 1); + break; + case 2: + mmio_write_32(SPM_CA7_CPU2_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, 1); + break; + case 3: + mmio_write_32(SPM_CA7_CPU3_IRQ_MASK, 1); + mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, 1); + break; + default: + break; + } + } +} + +static void spm_mcdi_wfi_sel_leave(unsigned long mpidr) +{ + int core_id_val = mpidr & MPIDR_CPU_MASK; + int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; + + /* SPM WFI Select by core number */ + if (cluster_id) { + switch (core_id_val) { + case 0: + mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, 0); + mmio_write_32(SPM_CA15_CPU0_IRQ_MASK, 0); + break; + case 1: + mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, 0); + mmio_write_32(SPM_CA15_CPU1_IRQ_MASK, 0); + break; + case 2: + mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, 0); + mmio_write_32(SPM_CA15_CPU2_IRQ_MASK, 0); + break; + case 3: + mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, 0); + mmio_write_32(SPM_CA15_CPU3_IRQ_MASK, 0); + break; + default: + break; + } + } else { + switch (core_id_val) { + case 0: + mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, 0); + mmio_write_32(SPM_CA7_CPU0_IRQ_MASK, 0); + break; + case 1: + mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, 0); + mmio_write_32(SPM_CA7_CPU1_IRQ_MASK, 0); + break; + case 2: + mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, 0); + mmio_write_32(SPM_CA7_CPU2_IRQ_MASK, 0); + break; + case 3: + mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, 0); + mmio_write_32(SPM_CA7_CPU3_IRQ_MASK, 0); + break; + default: + break; + } + } +} + +static void spm_mcdi_set_cputop_pwrctrl_for_cluster_off(unsigned long mpidr) +{ + unsigned long cluster_id = mpidr & MPIDR_CLUSTER_MASK; + unsigned long cpu_id = mpidr & MPIDR_CPU_MASK; + unsigned int pwr_status, shift, i, flag = 0; + + pwr_status = mmio_read_32(SPM_PWR_STATUS) | + mmio_read_32(SPM_PWR_STATUS_2ND); + + if (cluster_id) { + for (i = 0; i < PLATFORM_CLUSTER1_CORE_COUNT; i++) { + if (i == cpu_id) + continue; + shift = i + PCM_MCDI_CA72_PWRSTA_SHIFT; + flag |= (pwr_status & (1 << shift)) >> shift; + } + if (!flag) + mmio_setbits_32(SPM_PCM_RESERVE, + PCM_MCDI_CA72_CPUTOP_PWRCTL); + } else { + for (i = 0; i < PLATFORM_CLUSTER0_CORE_COUNT; i++) { + if (i == cpu_id) + continue; + shift = i + PCM_MCDI_CA53_PWRSTA_SHIFT; + flag |= (pwr_status & (1 << shift)) >> shift; + } + if (!flag) + mmio_setbits_32(SPM_PCM_RESERVE, + PCM_MCDI_CA53_CPUTOP_PWRCTL); + } +} + +static void spm_mcdi_clear_cputop_pwrctrl_for_cluster_on(unsigned long mpidr) +{ + unsigned long cluster_id = mpidr & MPIDR_CLUSTER_MASK; + + if (cluster_id) + mmio_clrbits_32(SPM_PCM_RESERVE, + PCM_MCDI_CA72_CPUTOP_PWRCTL); + else + mmio_clrbits_32(SPM_PCM_RESERVE, + PCM_MCDI_CA53_CPUTOP_PWRCTL); +} + +void spm_mcdi_prepare_for_mtcmos(void) +{ + const struct pcm_desc *pcmdesc = spm_mcdi.pcmdesc; + struct pwr_ctrl *pwrctrl = spm_mcdi.pwrctrl; + + if (is_mcdi_ready() == 0) { + if (is_hotplug_ready() == 1) + spm_clear_hotplug(); + set_pwrctrl_pcm_flags(pwrctrl, 0); + spm_reset_and_init_pcm(); + spm_kick_im_to_fetch(pcmdesc); + spm_set_power_control(pwrctrl); + spm_set_wakeup_event(pwrctrl); + spm_kick_pcm_to_run(pwrctrl); + set_mcdi_ready(); + } +} + +void spm_mcdi_prepare_for_off_state(unsigned long mpidr, unsigned int afflvl) +{ + const struct pcm_desc *pcmdesc = spm_mcdi.pcmdesc; + struct pwr_ctrl *pwrctrl = spm_mcdi.pwrctrl; + + spm_lock_get(); + if (is_mcdi_ready() == 0) { + if (is_hotplug_ready() == 1) + spm_clear_hotplug(); + set_pwrctrl_pcm_flags(pwrctrl, 0); + spm_reset_and_init_pcm(); + spm_kick_im_to_fetch(pcmdesc); + spm_set_power_control(pwrctrl); + spm_set_wakeup_event(pwrctrl); + spm_kick_pcm_to_run(pwrctrl); + set_mcdi_ready(); + } + spm_mcdi_wfi_sel_enter(mpidr); + if (afflvl == MPIDR_AFFLVL1) + spm_mcdi_set_cputop_pwrctrl_for_cluster_off(mpidr); + spm_lock_release(); +} + +void spm_mcdi_finish_for_on_state(unsigned long mpidr, unsigned int afflvl) +{ + unsigned long linear_id = platform_get_core_pos(mpidr); + + spm_lock_get(); + spm_mcdi_clear_cputop_pwrctrl_for_cluster_on(mpidr); + spm_mcdi_wfi_sel_leave(mpidr); + mmio_write_32(SPM_PCM_SW_INT_CLEAR, (0x1 << linear_id)); + spm_lock_release(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.h new file mode 100644 index 0000000..4d1f990 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.h @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __SPM_MCDI_H__ +#define __SPM_MCDI_H__ + +void spm_mcdi_wakeup_all_cores(void); +void spm_mcdi_prepare_for_mtcmos(void); +void spm_mcdi_prepare_for_off_state(unsigned long mpidr, unsigned int afflvl); +void spm_mcdi_finish_for_on_state(unsigned long mpidr, unsigned int afflvl); + +#endif /* __SPM_MCDI_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c new file mode 100644 index 0000000..843b5f9 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include + +/* + * System Power Manager (SPM) is a hardware module, which controls cpu or + * system power for different power scenarios using different firmware. + * This driver controls the system power in system suspend flow. + */ + +#define WAKE_SRC_FOR_SUSPEND \ + (WAKE_SRC_KP | WAKE_SRC_EINT | WAKE_SRC_MD32 | \ + WAKE_SRC_USB_CD | WAKE_SRC_USB_PDN | WAKE_SRC_THERM | \ + WAKE_SRC_SYSPWREQ | WAKE_SRC_ALL_MD32) + +#define WAKE_SRC_FOR_MD32 0 + +#define spm_is_wakesrc_invalid(wakesrc) \ + (!!((unsigned int)(wakesrc) & 0xc0003803)) + +#define ARMCA15PLL_CON0 (APMIXED_BASE + 0x200) +#define ARMCA15PLL_CON1 (APMIXED_BASE + 0x204) +#define ARMCA15PLL_PWR_CON0 (APMIXED_BASE + 0x20c) +#define ARMCA15PLL_PWR_ON (1U << 0) +#define ARMCA15PLL_ISO_EN (1U << 1) +#define ARMCA15PLL_EN (1U << 0) + +const unsigned int spm_flags = + SPM_DUALVCORE_PDN_DIS | SPM_PASR_DIS | SPM_DPD_DIS | + SPM_CPU_DVS_DIS | SPM_OPT | SPM_INFRA_PDN_DIS; + +enum wake_reason_t spm_wake_reason = WR_NONE; + +/********************************************************** + * PCM sequence for cpu suspend + **********************************************************/ +static const unsigned int suspend_binary_ca7[] = { + 0x81f58407, 0x81f68407, 0x803a0400, 0x803a8400, 0x1b80001f, 0x20000000, + 0x80300400, 0x80318400, 0x80328400, 0xa1d28407, 0x81f20407, 0x81009801, + 0xd8000244, 0x17c07c1f, 0x18c0001f, 0x10006234, 0xc0c032e0, 0x1200041f, + 0x80310400, 0x1b80001f, 0x2000000a, 0xa0110400, 0x18c0001f, 0x100062c8, + 0xe0e00010, 0xe0e00030, 0xe0e00070, 0xe0e000f0, 0x1b80001f, 0x2000001a, + 0xe0e00ff0, 0xe8208000, 0x10006354, 0xfffe7fff, 0xe8208000, 0x10006834, + 0x00000010, 0x81f00407, 0xa1dd0407, 0x81fd0407, 0xc2803800, 0x1290041f, + 0x8880000c, 0x2f7be75f, 0xd8200722, 0x17c07c1f, 0xd82006a9, 0x17c07c1f, + 0xe8208000, 0x10006814, 0x00000001, 0xc2803800, 0x1293841f, 0x1b00001f, + 0x7fffe7ff, 0xd0000760, 0x17c07c1f, 0x1b00001f, 0x7ffff7ff, 0xf0000000, + 0x17c07c1f, 0x80880001, 0xd8000842, 0x17c07c1f, 0xd00028e0, 0x1200041f, + 0xe8208000, 0x10006834, 0x00000000, 0x1b00001f, 0x3fffe7ff, 0x1b80001f, + 0x20000004, 0xd8200a0c, 0x17c07c1f, 0xe8208000, 0x10006834, 0x00000010, + 0xd0001280, 0x17c07c1f, 0x18c0001f, 0x10006608, 0x1910001f, 0x10006608, + 0x813b0404, 0xe0c00004, 0x1880001f, 0x10006320, 0xc0c03760, 0xe080000f, + 0xd8200c03, 0x17c07c1f, 0x1b00001f, 0x7ffff7ff, 0xd0001280, 0x17c07c1f, + 0xe080001f, 0xe8208000, 0x10006354, 0xffffffff, 0x18c0001f, 0x100062c8, + 0xe0e000f0, 0xe0e00030, 0xe0e00000, 0x81009801, 0xd80010c4, 0x17c07c1f, + 0x18c0001f, 0x10004094, 0x1910001f, 0x1020e374, 0xe0c00004, 0x18c0001f, + 0x10004098, 0x1910001f, 0x1020e378, 0xe0c00004, 0x18c0001f, 0x10011094, + 0x1910001f, 0x10213374, 0xe0c00004, 0x18c0001f, 0x10011098, 0x1910001f, + 0x10213378, 0xe0c00004, 0x1910001f, 0x10213378, 0x18c0001f, 0x10006234, + 0xc0c034a0, 0x17c07c1f, 0xc2803800, 0x1290841f, 0xa1d20407, 0x81f28407, + 0xa1d68407, 0xa0128400, 0xa0118400, 0xa0100400, 0xa01a8400, 0xa01a0400, + 0x19c0001f, 0x001c239f, 0x1b00001f, 0x3fffefff, 0xf0000000, 0x17c07c1f, + 0x808d8001, 0xd8201502, 0x17c07c1f, 0x803d8400, 0x1b80001f, 0x2000001a, + 0x80340400, 0x17c07c1f, 0x17c07c1f, 0x80310400, 0x81fa0407, 0x81f18407, + 0x81f08407, 0xa1dc0407, 0x1b80001f, 0x200000b6, 0xd0002220, 0x17c07c1f, + 0x1880001f, 0x20000208, 0x81011801, 0xd80016e4, 0x17c07c1f, 0xe8208000, + 0x1000f600, 0xd2000000, 0x1380081f, 0x18c0001f, 0x10006240, 0xe0e00016, + 0xe0e0001e, 0xe0e0000e, 0xe0e0000f, 0x80368400, 0x1380081f, 0x80370400, + 0x1380081f, 0x80360400, 0x803e0400, 0x1380081f, 0x80380400, 0x803b0400, + 0xa01d8400, 0x1b80001f, 0x20000034, 0x803d8400, 0x1b80001f, 0x20000152, + 0x803d0400, 0x1380081f, 0x18c0001f, 0x1000f5c8, 0x1910001f, 0x1000f5c8, + 0xa1000404, 0xe0c00004, 0x18c0001f, 0x100125c8, 0x1910001f, 0x100125c8, + 0xa1000404, 0xe0c00004, 0x1910001f, 0x100125c8, 0x80340400, 0x17c07c1f, + 0x17c07c1f, 0x80310400, 0xe8208000, 0x10000044, 0x00000100, 0x1b80001f, + 0x20000068, 0x1b80001f, 0x2000000a, 0x18c0001f, 0x10006240, 0xe0e0000d, + 0x81011801, 0xd8001f64, 0x17c07c1f, 0x18c0001f, 0x100040f4, 0x1910001f, + 0x100040f4, 0xa11c8404, 0xe0c00004, 0x1b80001f, 0x2000000a, 0x813c8404, + 0xe0c00004, 0x18c0001f, 0x100110f4, 0x1910001f, 0x100110f4, 0xa11c8404, + 0xe0c00004, 0x1b80001f, 0x2000000a, 0x813c8404, 0xe0c00004, 0x1b80001f, + 0x20000100, 0x81fa0407, 0x81f18407, 0x81f08407, 0xe8208000, 0x10006354, + 0xfffe7b47, 0x18c0001f, 0x65930003, 0xc0c031c0, 0x17c07c1f, 0xc2803800, + 0x1293041f, 0xa1d80407, 0xa1dc0407, 0x18c0001f, 0x10006608, 0x1910001f, + 0x10006608, 0xa11b0404, 0xe0c00004, 0xc2803800, 0x1291041f, 0x8880000c, + 0x2f7be75f, 0xd8202362, 0x17c07c1f, 0x1b00001f, 0x3fffe7ff, 0xd00023a0, + 0x17c07c1f, 0x1b00001f, 0xbfffe7ff, 0xf0000000, 0x17c07c1f, 0x1890001f, + 0x10006608, 0x808b0801, 0xd8202642, 0x17c07c1f, 0x1880001f, 0x10006320, + 0xc0c03540, 0xe080000f, 0xd80027a3, 0x17c07c1f, 0xe080001f, 0xa1da0407, + 0x81fc0407, 0xa0110400, 0xa0140400, 0xa01d8400, 0xd0003100, 0x17c07c1f, + 0x1b80001f, 0x20000fdf, 0x1890001f, 0x10006608, 0x80c98801, 0x810a8801, + 0x10918c1f, 0xa0939002, 0x8080080d, 0xd82028e2, 0x12007c1f, 0x1b00001f, + 0x3fffe7ff, 0x1b80001f, 0x20000004, 0xd800318c, 0x17c07c1f, 0x1b00001f, + 0xbfffe7ff, 0xd0003180, 0x17c07c1f, 0x81f80407, 0x81fc0407, 0x18c0001f, + 0x65930006, 0xc0c031c0, 0x17c07c1f, 0x18c0001f, 0x65930007, 0xc0c031c0, + 0x17c07c1f, 0x1880001f, 0x10006320, 0xc0c03540, 0xe080000f, 0xd80027a3, + 0x17c07c1f, 0xe080001f, 0x18c0001f, 0x65930005, 0xc0c031c0, 0x17c07c1f, + 0xa1da0407, 0xe8208000, 0x10000048, 0x00000100, 0x1b80001f, 0x20000068, + 0xa0110400, 0xa0140400, 0x18c0001f, 0x1000f5c8, 0x1910001f, 0x1000f5c8, + 0x81200404, 0xe0c00004, 0x18c0001f, 0x100125c8, 0x1910001f, 0x100125c8, + 0x81200404, 0xe0c00004, 0x1910001f, 0x100125c8, 0xa01d0400, 0xa01b0400, + 0xa0180400, 0x803d8400, 0xa01e0400, 0xa0160400, 0xa0170400, 0xa0168400, + 0x1b80001f, 0x20000104, 0x81011801, 0xd80030c4, 0x17c07c1f, 0x18c0001f, + 0x10006240, 0xc0c034a0, 0x17c07c1f, 0xe8208000, 0x1000f600, 0xd2000001, + 0xd8000848, 0x17c07c1f, 0xc2803800, 0x1291841f, 0x1b00001f, 0x7ffff7ff, + 0xf0000000, 0x17c07c1f, 0x1900001f, 0x10006830, 0xe1000003, 0x18c0001f, + 0x10006834, 0xe0e00000, 0xe0e00001, 0xf0000000, 0x17c07c1f, 0xe0f07f16, + 0x1380201f, 0xe0f07f1e, 0x1380201f, 0xe0f07f0e, 0x1b80001f, 0x20000104, + 0xe0f07f0c, 0xe0f07f0d, 0xe0f07e0d, 0xe0f07c0d, 0xe0f0780d, 0xf0000000, + 0xe0f0700d, 0xe0f07f0d, 0xe0f07f0f, 0xe0f07f1e, 0xf0000000, 0xe0f07f12, + 0x11407c1f, 0x81f08407, 0x81f18407, 0x1b80001f, 0x20000001, 0xa1d08407, + 0xa1d18407, 0x1392841f, 0x812ab401, 0x80ebb401, 0xa0c00c04, 0xd8203743, + 0x17c07c1f, 0x80c01403, 0xd8203563, 0x01400405, 0xf0000000, 0xa1d00407, + 0x1b80001f, 0x20000208, 0x80ea3401, 0xf0000000, 0x18c0001f, 0x10006b6c, + 0x1910001f, 0x10006b6c, 0xa1002804, 0xf0000000, 0xe0c00004, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, + 0x17c07c1f, 0x17c07c1f, 0x1840001f, 0x00000001, 0xa1d48407, 0x1990001f, + 0x10006b08, 0x1a50001f, 0x10006610, 0x8246a401, 0xe8208000, 0x10006b6c, + 0x00000000, 0x1b00001f, 0x2f7be75f, 0x81469801, 0xd8004305, 0x17c07c1f, + 0x1b80001f, 0xd00f0000, 0x8880000c, 0x2f7be75f, 0xd8005fa2, 0x17c07c1f, + 0xd0004340, 0x17c07c1f, 0x1b80001f, 0x500f0000, 0xe8208000, 0x10006354, + 0xfffe7b47, 0xc0c06c00, 0x81401801, 0xd80048e5, 0x17c07c1f, 0x81f60407, + 0x18c0001f, 0x10006200, 0xc0c06060, 0x12807c1f, 0xe8208000, 0x1000625c, + 0x00000001, 0x1b80001f, 0x20000080, 0xc0c06060, 0x1280041f, 0x18c0001f, + 0x10006204, 0xc0c06400, 0x1280041f, 0x18c0001f, 0x10006208, 0xc0c06060, + 0x12807c1f, 0xe8208000, 0x10006244, 0x00000001, 0x1b80001f, 0x20000080, + 0xc0c06060, 0x1280041f, 0x18d0001f, 0x10200200, 0x18c0001f, 0x10006290, + 0xc0c06060, 0x1280041f, 0xe8208000, 0x10006404, 0x00003101, 0xc2803800, + 0x1292041f, 0x81469801, 0xd8204a45, 0x17c07c1f, 0x1b00001f, 0x2f7be75f, + 0x1b80001f, 0x30000004, 0x8880000c, 0x2f7be75f, 0xd8005a02, 0x17c07c1f, + 0xc0c06780, 0x17c07c1f, 0x18c0001f, 0x10006294, 0xe0f07fff, 0xe0e00fff, + 0xe0e000ff, 0x81449801, 0xd8004c85, 0x17c07c1f, 0x1a00001f, 0x10006604, + 0xe2200003, 0xc0c06840, 0x17c07c1f, 0xe2200005, 0xc0c06840, 0x17c07c1f, + 0xa1d38407, 0xa1d98407, 0x1800001f, 0x00000012, 0x1800001f, 0x00000e12, + 0x1800001f, 0x03800e12, 0x1800001f, 0x038e0e12, 0xe8208000, 0x10006310, + 0x0b1600f8, 0x1940001f, 0x00000000, 0x12407c1f, 0x1b00001f, 0xbfffe7ff, + 0x1b80001f, 0x90100000, 0x17c07c1f, 0xd8004fc5, 0x17c07c1f, 0x8247b001, + 0x1940001f, 0xffffffff, 0x80c00400, 0xd82050c3, 0xa1d58407, 0xa1dd8407, + 0x1b00001f, 0x3fffefff, 0xd0004ec0, 0x17c07c1f, 0x1890001f, 0x100063e8, + 0x88c0000c, 0x2f7be75f, 0xd80052e3, 0x17c07c1f, 0x80c40001, 0xd8005263, + 0x17c07c1f, 0x1b00001f, 0xbfffe7ff, 0xd00052a0, 0x17c07c1f, 0x1b00001f, + 0x7ffff7ff, 0xd0004ec0, 0x17c07c1f, 0x80c40001, 0xd82053e3, 0x17c07c1f, + 0xa1de0407, 0x1b00001f, 0x7fffe7ff, 0xd0004ec0, 0x17c07c1f, 0xe8208000, + 0x10006814, 0x00000000, 0x18c0001f, 0x10006b00, 0xe0e00000, 0xe0c00009, + 0x18c0001f, 0x10006294, 0xe0e001fe, 0xe0e003fc, 0xe0e007f8, 0xe0e00ff0, + 0x1b80001f, 0x20000020, 0xe0f07ff0, 0xe0f07f00, 0x81449801, 0xd80057a5, + 0x17c07c1f, 0x1a00001f, 0x10006604, 0xe2200002, 0xc0c06840, 0x17c07c1f, + 0xe2200004, 0xc0c06840, 0x17c07c1f, 0x1b80001f, 0x200016a8, 0x1800001f, + 0x03800e12, 0x1b80001f, 0x20000300, 0x1800001f, 0x00000e12, 0x1b80001f, + 0x20000300, 0x1800001f, 0x00000012, 0x1b80001f, 0x20000104, 0x10007c1f, + 0x81f38407, 0x81f98407, 0x81f90407, 0x81f40407, 0x1b80001f, 0x200016a8, + 0x81401801, 0xd8005fa5, 0x17c07c1f, 0xe8208000, 0x10006404, 0x00002101, + 0x18c0001f, 0x10006290, 0x1212841f, 0xc0c061e0, 0x12807c1f, 0xc0c061e0, + 0x1280041f, 0x18c0001f, 0x10006208, 0x1212841f, 0xc0c061e0, 0x12807c1f, + 0xe8208000, 0x10006244, 0x00000000, 0x1b80001f, 0x20000080, 0xc0c061e0, + 0x1280041f, 0xe8208000, 0x10200268, 0x000ffffe, 0x18c0001f, 0x10006204, + 0x1212841f, 0xc0c065a0, 0x1280041f, 0x18c0001f, 0x10006200, 0x1212841f, + 0xc0c061e0, 0x12807c1f, 0xe8208000, 0x1000625c, 0x00000000, 0x1b80001f, + 0x20000080, 0xc0c061e0, 0x1280041f, 0x19c0001f, 0x01411820, 0x1ac0001f, + 0x55aa55aa, 0x10007c1f, 0xf0000000, 0xd800610a, 0x17c07c1f, 0xe2e0004f, + 0xe2e0006f, 0xe2e0002f, 0xd82061aa, 0x17c07c1f, 0xe2e0002e, 0xe2e0003e, + 0xe2e00032, 0xf0000000, 0x17c07c1f, 0xd80062aa, 0x17c07c1f, 0xe2e00036, + 0xe2e0003e, 0x1380201f, 0xe2e0003c, 0xd82063ca, 0x17c07c1f, 0x1380201f, + 0xe2e0007c, 0x1b80001f, 0x20000003, 0xe2e0005c, 0xe2e0004c, 0xe2e0004d, + 0xf0000000, 0x17c07c1f, 0x1a50001f, 0x10006610, 0x8246a401, 0xd8206569, + 0x17c07c1f, 0xe2e0000d, 0xe2e0000c, 0xe2e0001c, 0xe2e0001e, 0xe2e00016, + 0xe2e00012, 0xf0000000, 0x17c07c1f, 0x1a50001f, 0x10006610, 0x8246a401, + 0xd8206749, 0x17c07c1f, 0xe2e00016, 0x1380201f, 0xe2e0001e, 0x1380201f, + 0xe2e0001c, 0x1380201f, 0xe2e0000c, 0xe2e0000d, 0xf0000000, 0x17c07c1f, + 0xa1d40407, 0x1391841f, 0xa1d90407, 0x1393041f, 0xf0000000, 0x17c07c1f, + 0x18d0001f, 0x10006604, 0x10cf8c1f, 0xd8206843, 0x17c07c1f, 0xf0000000, + 0x17c07c1f, 0xe8208000, 0x11008014, 0x00000002, 0xe8208000, 0x11008020, + 0x00000101, 0xe8208000, 0x11008004, 0x000000d0, 0x1a00001f, 0x11008000, + 0xd8006b0a, 0xe220005d, 0xd8206b2a, 0xe2200000, 0xe2200001, 0xe8208000, + 0x11008024, 0x00000001, 0x1b80001f, 0x20000424, 0xf0000000, 0x17c07c1f, + 0xa1d10407, 0x1b80001f, 0x20000020, 0xf0000000, 0x17c07c1f +}; + +/* + * PCM binary for suspend scenario + */ +static const struct pcm_desc suspend_pcm_ca7 = { + .version = "pcm_suspend_20150917_V4", + .base = suspend_binary_ca7, + .size = 869, + .sess = 2, + .replace = 0, + .vec0 = EVENT_VEC(11, 1, 0, 0), + .vec1 = EVENT_VEC(12, 1, 0, 61), + .vec2 = EVENT_VEC(30, 1, 0, 150), + .vec3 = EVENT_VEC(31, 1, 0, 287), +}; + +/* + * SPM settings for suspend scenario + */ +static struct pwr_ctrl spm_ctrl = { + .wake_src = WAKE_SRC_FOR_SUSPEND, + .wake_src_md32 = WAKE_SRC_FOR_MD32, + .r0_ctrl_en = 1, + .r7_ctrl_en = 1, + .infra_dcm_lock = 1, + .wfi_op = WFI_OP_AND, + .pcm_apsrc_req = 0, + .ca7top_idle_mask = 0, + .ca15top_idle_mask = 0, + .mcusys_idle_mask = 0, + .disp_req_mask = 0, + .mfg_req_mask = 0, + .md32_req_mask = 1, + .srclkenai_mask = 1, + .ca7_wfi0_en = 1, + .ca7_wfi1_en = 1, + .ca7_wfi2_en = 1, + .ca7_wfi3_en = 1, + .ca15_wfi0_en = 1, + .ca15_wfi1_en = 1, + .ca15_wfi2_en = 1, + .ca15_wfi3_en = 1, +}; + +/* + * go_to_sleep_before_wfi() - trigger SPM to enter suspend scenario + */ +static void go_to_sleep_before_wfi(const unsigned int spm_flags) +{ + struct pwr_ctrl *pwrctrl; + + pwrctrl = &spm_ctrl; + + set_pwrctrl_pcm_flags(pwrctrl, spm_flags); + + spm_set_sysclk_settle(); + + INFO("sec = %u, wakesrc = 0x%x (%u)(%u)\n", + pwrctrl->timer_val, pwrctrl->wake_src, + is_cpu_pdn(pwrctrl->pcm_flags), + is_infra_pdn(pwrctrl->pcm_flags)); + + spm_reset_and_init_pcm(); + spm_init_pcm_register(); + spm_set_power_control(pwrctrl); + spm_set_wakeup_event(pwrctrl); + spm_kick_pcm_to_run(pwrctrl); + spm_init_event_vector(&suspend_pcm_ca7); + spm_kick_im_to_fetch(&suspend_pcm_ca7); +} + +/* + * go_to_sleep_after_wfi() - get wakeup reason after + * leaving suspend scenario and clean up SPM settings + */ +static enum wake_reason_t go_to_sleep_after_wfi(void) +{ + struct wake_status wakesta; + static enum wake_reason_t last_wr = WR_NONE; + + spm_get_wakeup_status(&wakesta); + spm_clean_after_wakeup(); + last_wr = spm_output_wake_reason(&wakesta); + + return last_wr; +} + +static void bigcore_pll_on(void) +{ + mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON); + mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN); + mmio_setbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN); +} + +static void bigcore_pll_off(void) +{ + mmio_clrbits_32(ARMCA15PLL_CON0, ARMCA15PLL_EN); + mmio_setbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_ISO_EN); + mmio_clrbits_32(ARMCA15PLL_PWR_CON0, ARMCA15PLL_PWR_ON); +} + +void spm_system_suspend(void) +{ + bigcore_pll_off(); + spm_lock_get(); + go_to_sleep_before_wfi(spm_flags); + set_suspend_ready(); + spm_lock_release(); +} + +void spm_system_suspend_finish(void) +{ + spm_lock_get(); + spm_wake_reason = go_to_sleep_after_wfi(); + INFO("spm_wake_reason=%d\n", spm_wake_reason); + clear_all_ready(); + spm_lock_release(); + bigcore_pll_on(); + /* Add 20us delay for turning on PLL*/ + udelay(20); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.h new file mode 100644 index 0000000..643713b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __SPM_SUSPEND_H__ +#define __SPM_SUSPEND_H__ + +/* cpu dormant return code */ +#define CPU_DORMANT_RESET 0 +#define CPU_DORMANT_ABORT 1 + +void spm_system_suspend(void); +void spm_system_suspend_finish(void); + +#endif /* __SPM_SUSPEND_H__*/ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.c new file mode 100644 index 0000000..63200bd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include + +static void write_cpuxgpt(unsigned int reg_index, unsigned int value) +{ + mmio_write_32((uintptr_t)&mt8173_mcucfg->xgpt_idx, reg_index); + mmio_write_32((uintptr_t)&mt8173_mcucfg->xgpt_ctl, value); +} + +static void cpuxgpt_set_init_cnt(unsigned int countH, unsigned int countL) +{ + write_cpuxgpt(INDEX_CNT_H_INIT, countH); + /* update count when countL programmed */ + write_cpuxgpt(INDEX_CNT_L_INIT, countL); +} + +void generic_timer_backup(void) +{ + uint64_t cval; + + cval = read_cntpct_el0(); + cpuxgpt_set_init_cnt((uint32_t)(cval >> 32), + (uint32_t)(cval & 0xffffffff)); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.h new file mode 100644 index 0000000..329a250 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/drivers/timer/mt_cpuxgpt.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MT_CPUXGPT_H__ +#define __MT_CPUXGPT_H__ + +/* REG */ +#define INDEX_CNT_L_INIT 0x008 +#define INDEX_CNT_H_INIT 0x00C + +void generic_timer_backup(void); + +#endif /* __MT_CPUXGPT_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/mcucfg.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/mcucfg.h new file mode 100644 index 0000000..7c837ba --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/mcucfg.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __MCUCFG_H__ +#define __MCUCFG_H__ + +#include +#include + +struct mt8173_mcucfg_regs { + uint32_t mp0_ca7l_cache_config; + struct { + uint32_t mem_delsel0; + uint32_t mem_delsel1; + } mp0_cpu[4]; + uint32_t mp0_cache_mem_delsel0; + uint32_t mp0_cache_mem_delsel1; + uint32_t mp0_axi_config; + uint32_t mp0_misc_config[2]; + struct { + uint32_t rv_addr_lw; + uint32_t rv_addr_hw; + } mp0_rv_addr[4]; + uint32_t mp0_ca7l_cfg_dis; + uint32_t mp0_ca7l_clken_ctrl; + uint32_t mp0_ca7l_rst_ctrl; + uint32_t mp0_ca7l_misc_config; + uint32_t mp0_ca7l_dbg_pwr_ctrl; + uint32_t mp0_rw_rsvd0; + uint32_t mp0_rw_rsvd1; + uint32_t mp0_ro_rsvd; + uint32_t reserved0_0[100]; + uint32_t mp1_cpucfg; + uint32_t mp1_miscdbg; + uint32_t reserved0_1[13]; + uint32_t mp1_rst_ctl; + uint32_t mp1_clkenm_div; + uint32_t reserved0_2[7]; + uint32_t mp1_config_res; + uint32_t reserved0_3[13]; + struct { + uint32_t rv_addr_lw; + uint32_t rv_addr_hw; + } mp1_rv_addr[2]; + uint32_t reserved0_4[84]; + uint32_t mp0_rst_status; /* 0x400 */ + uint32_t mp0_dbg_ctrl; + uint32_t mp0_dbg_flag; + uint32_t mp0_ca7l_ir_mon; + struct { + uint32_t pc_lw; + uint32_t pc_hw; + uint32_t fp_arch32; + uint32_t sp_arch32; + uint32_t fp_arch64_lw; + uint32_t fp_arch64_hw; + uint32_t sp_arch64_lw; + uint32_t sp_arch64_hw; + } mp0_dbg_core[4]; + uint32_t dfd_ctrl; + uint32_t dfd_cnt_l; + uint32_t dfd_cnt_h; + uint32_t misccfg_mp0_rw_rsvd; + uint32_t misccfg_sec_vio_status0; + uint32_t misccfg_sec_vio_status1; + uint32_t reserved1[22]; + uint32_t misccfg_rw_rsvd; /* 0x500 */ + uint32_t mcusys_dbg_mon_sel_a; + uint32_t mcusys_dbg_mon; + uint32_t reserved2[61]; + uint32_t mcusys_config_a; /* 0x600 */ + uint32_t mcusys_config1_a; + uint32_t mcusys_gic_peribase_a; + uint32_t reserved3; + uint32_t sec_range0_start; /* 0x610 */ + uint32_t sec_range0_end; + uint32_t sec_range_enable; + uint32_t reserved4; + uint32_t int_pol_ctl[8]; /* 0x620 */ + uint32_t aclken_div; /* 0x640 */ + uint32_t pclken_div; + uint32_t l2c_sram_ctrl; + uint32_t armpll_jit_ctrl; + uint32_t cci_addrmap; /* 0x650 */ + uint32_t cci_config; + uint32_t cci_periphbase; + uint32_t cci_nevntcntovfl; + uint32_t cci_clk_ctrl; /* 0x660 */ + uint32_t cci_acel_s1_ctrl; + uint32_t bus_fabric_dcm_ctrl; + uint32_t reserved5; + uint32_t xgpt_ctl; /* 0x670 */ + uint32_t xgpt_idx; + uint32_t ptpod2_ctl0; + uint32_t ptpod2_ctl1; + uint32_t mcusys_revid; + uint32_t mcusys_rw_rsvd0; + uint32_t mcusys_rw_rsvd1; +}; + +static struct mt8173_mcucfg_regs *const mt8173_mcucfg = (void *)MCUCFG_BASE; + +/* cpu boot mode */ +enum { + MP0_CPUCFG_64BIT_SHIFT = 12, + MP1_CPUCFG_64BIT_SHIFT = 28, + MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT, + MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT +}; + +/* scu related */ +enum { + MP0_ACINACTM_SHIFT = 4, + MP1_ACINACTM_SHIFT = 0, + MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT, + MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT +}; + +enum { + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0, + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4, + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8, + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12, + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16, + + MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT, + MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK = + 0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT +}; + +enum { + MP1_AINACTS_SHIFT = 4, + MP1_AINACTS = 1 << MP1_AINACTS_SHIFT +}; + +enum { + MP1_SW_CG_GEN_SHIFT = 12, + MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT +}; + +enum { + MP1_L2RSTDISABLE_SHIFT = 14, + MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT +}; + +/* cci clock control related */ +enum { + MCU_BUS_DCM_EN = 1 << 8 +}; + +/* l2c sram control related */ +enum { + L2C_SRAM_DCM_EN = 1 << 0 +}; + +/* bus fabric dcm control related */ +enum { + PSYS_ADB400_DCM_EN = 1 << 29, + GPU_ADB400_DCM_EN = 1 << 28, + + EMI1_ADB400_DCM_EN = 1 << 27, + EMI_ADB400_DCM_EN = 1 << 26, + INFRA_ADB400_DCM_EN = 1 << 25, + L2C_ADB400_DCM_EN = 1 << 24, + + MP0_ADB400_DCM_EN = 1 << 23, + CCI400_CK_ONLY_DCM_EN = 1 << 22, + L2C_IDLE_DCM_EN = 1 << 21, + + CA15U_ADB_DYNAMIC_CG_EN = 1 << 19, + CA7L_ADB_DYNAMIC_CG_EN = 1 << 18, + L2C_ADB_DYNAMIC_CG_EN = 1 << 17, + + EMICLK_EMI1_DYNAMIC_CG_EN = 1 << 12, + + INFRACLK_PSYS_DYNAMIC_CG_EN = 1 << 11, + EMICLK_GPU_DYNAMIC_CG_EN = 1 << 10, + EMICLK_EMI_DYNAMIC_CG_EN = 1 << 8, + + CCI400_SLV_RW_DCM_EN = 1 << 7, + CCI400_SLV_DCM_EN = 1 << 5, + + ACLK_PSYS_DYNAMIC_CG_EN = 1 << 3, + ACLK_GPU_DYNAMIC_CG_EN = 1 << 2, + ACLK_EMI_DYNAMIC_CG_EN = 1 << 1, + ACLK_INFRA_DYNAMIC_CG_EN = 1 << 0, + + /* adb400 related */ + ADB400_GRP_DCM_EN = PSYS_ADB400_DCM_EN | GPU_ADB400_DCM_EN | + EMI1_ADB400_DCM_EN | EMI_ADB400_DCM_EN | + INFRA_ADB400_DCM_EN | L2C_ADB400_DCM_EN | + MP0_ADB400_DCM_EN, + + /* cci400 related */ + CCI400_GRP_DCM_EN = CCI400_CK_ONLY_DCM_EN | CCI400_SLV_RW_DCM_EN | + CCI400_SLV_DCM_EN, + + /* adb clock related */ + ADBCLK_GRP_DCM_EN = CA15U_ADB_DYNAMIC_CG_EN | CA7L_ADB_DYNAMIC_CG_EN | + L2C_ADB_DYNAMIC_CG_EN, + + /* emi clock related */ + EMICLK_GRP_DCM_EN = EMICLK_EMI1_DYNAMIC_CG_EN | + EMICLK_GPU_DYNAMIC_CG_EN | + EMICLK_EMI_DYNAMIC_CG_EN, + + /* bus clock related */ + ACLK_GRP_DCM_EN = ACLK_PSYS_DYNAMIC_CG_EN | ACLK_GPU_DYNAMIC_CG_EN | + ACLK_EMI_DYNAMIC_CG_EN | ACLK_INFRA_DYNAMIC_CG_EN, +}; + +#endif /* __MCUCFG_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/mt8173_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/mt8173_def.h new file mode 100644 index 0000000..87e9c04 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/mt8173_def.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MT8173_DEF_H__ +#define __MT8173_DEF_H__ + +#if RESET_TO_BL31 +#error "MT8173 is incompatible with RESET_TO_BL31!" +#endif + +#define MT8173_PRIMARY_CPU 0x0 + +/* Register base address */ +#define IO_PHYS (0x10000000) +#define INFRACFG_AO_BASE (IO_PHYS + 0x1000) +#define SRAMROM_SEC_BASE (IO_PHYS + 0x1800) +#define PERI_CON_BASE (IO_PHYS + 0x3000) +#define GPIO_BASE (IO_PHYS + 0x5000) +#define SPM_BASE (IO_PHYS + 0x6000) +#define RGU_BASE (IO_PHYS + 0x7000) +#define PMIC_WRAP_BASE (IO_PHYS + 0xD000) +#define DEVAPC0_BASE (IO_PHYS + 0xE000) +#define MCUCFG_BASE (IO_PHYS + 0x200000) +#define APMIXED_BASE (IO_PHYS + 0x209000) +#define TRNG_BASE (IO_PHYS + 0x20F000) +#define CRYPT_BASE (IO_PHYS + 0x210000) +#define MT_GIC_BASE (IO_PHYS + 0x220000) +#define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000) + +/* Aggregate of all devices in the first GB */ +#define MTK_DEV_RNG0_BASE IO_PHYS +#define MTK_DEV_RNG0_SIZE 0x400000 +#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000) +#define MTK_DEV_RNG1_SIZE 0x4000000 + +/* SRAMROM related registers */ +#define SRAMROM_SEC_CTRL (SRAMROM_SEC_BASE + 0x4) +#define SRAMROM_SEC_ADDR (SRAMROM_SEC_BASE + 0x8) + +/* DEVAPC0 related registers */ +#define DEVAPC0_MAS_SEC_0 (DEVAPC0_BASE + 0x500) +#define DEVAPC0_APC_CON (DEVAPC0_BASE + 0xF00) + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define MT8173_UART0_BASE (IO_PHYS + 0x01002000) +#define MT8173_UART1_BASE (IO_PHYS + 0x01003000) +#define MT8173_UART2_BASE (IO_PHYS + 0x01004000) +#define MT8173_UART3_BASE (IO_PHYS + 0x01005000) + +#define MT8173_BAUDRATE (115200) +#define MT8173_UART_CLOCK (26000000) + +/******************************************************************************* + * System counter frequency related constants + ******************************************************************************/ +#define SYS_COUNTER_FREQ_IN_TICKS 13000000 + +/******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ + +/* Base MTK_platform compatible GIC memory map */ +#define BASE_GICD_BASE (MT_GIC_BASE + 0x1000) +#define BASE_GICC_BASE (MT_GIC_BASE + 0x2000) +#define BASE_GICR_BASE 0 /* no GICR in GIC-400 */ +#define BASE_GICH_BASE (MT_GIC_BASE + 0x4000) +#define BASE_GICV_BASE (MT_GIC_BASE + 0x6000) +#define INT_POL_CTL0 0x10200620 + +#define GIC_PRIVATE_SIGNALS (32) + +/******************************************************************************* + * CCI-400 related constants + ******************************************************************************/ +#define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4 +#define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3 + +/******************************************************************************* + * WDT related constants + ******************************************************************************/ +#define MTK_WDT_BASE (RGU_BASE + 0) +#define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014) + +#define MTK_WDT_MODE_DUAL_MODE 0x0040 +#define MTK_WDT_MODE_IRQ 0x0008 +#define MTK_WDT_MODE_KEY 0x22000000 +#define MTK_WDT_MODE_EXTEN 0x0004 +#define MTK_WDT_SWRST_KEY 0x1209 + +/* FIQ platform related define */ +#define MT_IRQ_SEC_SGI_0 8 +#define MT_IRQ_SEC_SGI_1 9 +#define MT_IRQ_SEC_SGI_2 10 +#define MT_IRQ_SEC_SGI_3 11 +#define MT_IRQ_SEC_SGI_4 12 +#define MT_IRQ_SEC_SGI_5 13 +#define MT_IRQ_SEC_SGI_6 14 +#define MT_IRQ_SEC_SGI_7 15 + +#endif /* __MT8173_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/plat_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/plat_macros.S new file mode 100644 index 0000000..018a790 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/plat_macros.S @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +.section .rodata.gic_reg_name, "aS" +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ + " Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* --------------------------------------------- + * The below macro prints out relevant GIC and + * CCI registers whenever an unhandled exception + * is taken in BL3-1. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + mov_imm x16, BASE_GICD_BASE + mov_imm x17, BASE_GICC_BASE + /* Load the gicc reg list to x6 */ + adr x6, gicc_regs + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + + adr x6, cci_iface_regs + /* Store in x7 the base address of the first interface */ + mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX)) + ldr w8, [x7, #SNOOP_CTRL_REG] + /* Store in x7 the base address of the second interface */ + mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX)) + ldr w9, [x7, #SNOOP_CTRL_REG] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + .endm diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/plat_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/plat_private.h new file mode 100644 index 0000000..ae50e44 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/plat_private.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_PRIVATE_H__ +#define __PLAT_PRIVATE_H__ + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void plat_configure_mmu_el3(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long, + unsigned long, + unsigned long); + +void plat_cci_init(void); +void plat_cci_enable(void); +void plat_cci_disable(void); + +/* Declarations for plat_mt_gic.c */ +void plat_mt_gic_init(void); + +/* Declarations for plat_topology.c */ +int mt_setup_topology(void); + +#endif /* __PLAT_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/plat_sip_calls.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/plat_sip_calls.h new file mode 100644 index 0000000..0fd84b2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/plat_sip_calls.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_SIP_CALLS_H__ +#define __PLAT_SIP_CALLS_H__ + +/******************************************************************************* + * Plat SiP function constants + ******************************************************************************/ +#define MTK_PLAT_SIP_NUM_CALLS 6 + +#define MTK_SIP_PWR_ON_MTCMOS 0x82000402 +#define MTK_SIP_PWR_OFF_MTCMOS 0x82000403 +#define MTK_SIP_PWR_MTCMOS_SUPPORT 0x82000404 +#define MTK_SIP_SET_HDCP_KEY_NUM 0x82000405 +#define MTK_SIP_CLR_HDCP_KEY 0x82000406 +#define MTK_SIP_SET_HDCP_KEY_EX 0x82000407 + +#endif /* __PLAT_SIP_CALLS_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/platform_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/platform_def.h new file mode 100644 index 0000000..dc5b000 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/platform_def.h @@ -0,0 +1,130 @@ +/* + * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#if IMAGE_BL1 +#define PLATFORM_STACK_SIZE 0x440 +#elif IMAGE_BL2 +#define PLATFORM_STACK_SIZE 0x400 +#elif IMAGE_BL31 +#define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL32 +#define PLATFORM_STACK_SIZE 0x440 +#endif + +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" + +#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 +#define PLATFORM_SYSTEM_COUNT 1 +#define PLATFORM_CLUSTER_COUNT 2 +#define PLATFORM_CLUSTER0_CORE_COUNT 4 +#define PLATFORM_CLUSTER1_CORE_COUNT 2 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ + PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ + PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +/* + * MT8173 SRAM memory layout + * 0x100000 +-------------------+ + * | shared mem (4KB) | + * 0x101000 +-------------------+ + * | | + * | BL3-1 (124KB) | + * | | + * 0x120000 +-------------------+ + * | reserved (64KB) | + * 0x130000 +-------------------+ + */ +/* TF txet, ro, rw, xlat table, coherent memory ... etc. + * Size: release: 128KB, debug: 128KB + */ +#define TZRAM_BASE (0x100000) +#if DEBUG +#define TZRAM_SIZE (0x20000) +#else +#define TZRAM_SIZE (0x20000) +#endif + +/* Reserved: 64KB */ +#define TZRAM2_BASE (TZRAM_BASE + TZRAM_SIZE) +#define TZRAM2_SIZE (0x10000) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL3-1 debug size plus a + * little space for growth. + */ +#define BL31_BASE (TZRAM_BASE + 0x1000) +#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) +#define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define ADDR_SPACE_SIZE (1ull << 32) +#define MAX_XLAT_TABLES 4 +#define MAX_MMAP_REGIONS 16 + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/power_tracer.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/power_tracer.h new file mode 100644 index 0000000..9c35ce0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/power_tracer.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __POWER_TRACER_H__ +#define __POWER_TRACER_H__ + +#define CPU_UP 0 +#define CPU_DOWN 1 +#define CPU_SUSPEND 2 +#define CLUSTER_UP 3 +#define CLUSTER_DOWN 4 +#define CLUSTER_SUSPEND 5 + +void trace_power_flow(unsigned long mpidr, unsigned char mode); + +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/scu.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/scu.h new file mode 100644 index 0000000..71f3929 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/include/scu.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SCU_H__ +#define __SCU_H__ + +void disable_scu(unsigned long mpidr); +void enable_scu(unsigned long mpidr); + +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/plat_mt_gic.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/plat_mt_gic.c new file mode 100644 index 0000000..402a0f4 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/plat_mt_gic.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include + +const unsigned int mt_irq_sec_array[] = { + MT_IRQ_SEC_SGI_0, + MT_IRQ_SEC_SGI_1, + MT_IRQ_SEC_SGI_2, + MT_IRQ_SEC_SGI_3, + MT_IRQ_SEC_SGI_4, + MT_IRQ_SEC_SGI_5, + MT_IRQ_SEC_SGI_6, + MT_IRQ_SEC_SGI_7 +}; + +void plat_mt_gic_init(void) +{ + arm_gic_init(BASE_GICC_BASE, + BASE_GICD_BASE, + BASE_GICR_BASE, + mt_irq_sec_array, + ARRAY_SIZE(mt_irq_sec_array)); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/plat_pm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/plat_pm.c new file mode 100644 index 0000000..6bb8a9b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/plat_pm.c @@ -0,0 +1,526 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* generic_timer_backup() */ +#include +#include +#include +#include +#include +#include +#include +#include + +struct core_context { + unsigned long timer_data[8]; + unsigned int count; + unsigned int rst; + unsigned int abt; + unsigned int brk; +}; + +struct cluster_context { + struct core_context core[PLATFORM_MAX_CPUS_PER_CLUSTER]; +}; + +/* + * Top level structure to hold the complete context of a multi cluster system + */ +struct system_context { + struct cluster_context cluster[PLATFORM_CLUSTER_COUNT]; +}; + +/* + * Top level structure which encapsulates the context of the entire system + */ +static struct system_context dormant_data[1]; + +static inline struct cluster_context *system_cluster( + struct system_context *system, + uint32_t clusterid) +{ + return &system->cluster[clusterid]; +} + +static inline struct core_context *cluster_core(struct cluster_context *cluster, + uint32_t cpuid) +{ + return &cluster->core[cpuid]; +} + +static struct cluster_context *get_cluster_data(unsigned long mpidr) +{ + uint32_t clusterid; + + clusterid = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS; + + return system_cluster(dormant_data, clusterid); +} + +static struct core_context *get_core_data(unsigned long mpidr) +{ + struct cluster_context *cluster; + uint32_t cpuid; + + cluster = get_cluster_data(mpidr); + cpuid = mpidr & MPIDR_CPU_MASK; + + return cluster_core(cluster, cpuid); +} + +static void mt_save_generic_timer(unsigned long *container) +{ + uint64_t ctl; + uint64_t val; + + __asm__ volatile("mrs %x0, cntkctl_el1\n\t" + "mrs %x1, cntp_cval_el0\n\t" + "stp %x0, %x1, [%2, #0]" + : "=&r" (ctl), "=&r" (val) + : "r" (container) + : "memory"); + + __asm__ volatile("mrs %x0, cntp_tval_el0\n\t" + "mrs %x1, cntp_ctl_el0\n\t" + "stp %x0, %x1, [%2, #16]" + : "=&r" (val), "=&r" (ctl) + : "r" (container) + : "memory"); + + __asm__ volatile("mrs %x0, cntv_tval_el0\n\t" + "mrs %x1, cntv_ctl_el0\n\t" + "stp %x0, %x1, [%2, #32]" + : "=&r" (val), "=&r" (ctl) + : "r" (container) + : "memory"); +} + +static void mt_restore_generic_timer(unsigned long *container) +{ + uint64_t ctl; + uint64_t val; + + __asm__ volatile("ldp %x0, %x1, [%2, #0]\n\t" + "msr cntkctl_el1, %x0\n\t" + "msr cntp_cval_el0, %x1" + : "=&r" (ctl), "=&r" (val) + : "r" (container) + : "memory"); + + __asm__ volatile("ldp %x0, %x1, [%2, #16]\n\t" + "msr cntp_tval_el0, %x0\n\t" + "msr cntp_ctl_el0, %x1" + : "=&r" (val), "=&r" (ctl) + : "r" (container) + : "memory"); + + __asm__ volatile("ldp %x0, %x1, [%2, #32]\n\t" + "msr cntv_tval_el0, %x0\n\t" + "msr cntv_ctl_el0, %x1" + : "=&r" (val), "=&r" (ctl) + : "r" (container) + : "memory"); +} + +static inline uint64_t read_cntpctl(void) +{ + uint64_t cntpctl; + + __asm__ volatile("mrs %x0, cntp_ctl_el0" + : "=r" (cntpctl) : : "memory"); + + return cntpctl; +} + +static inline void write_cntpctl(uint64_t cntpctl) +{ + __asm__ volatile("msr cntp_ctl_el0, %x0" : : "r"(cntpctl)); +} + +static void stop_generic_timer(void) +{ + /* + * Disable the timer and mask the irq to prevent + * suprious interrupts on this cpu interface. It + * will bite us when we come back if we don't. It + * will be replayed on the inbound cluster. + */ + uint64_t cntpctl = read_cntpctl(); + + write_cntpctl(clr_cntp_ctl_enable(cntpctl)); +} + +static void mt_cpu_save(unsigned long mpidr) +{ + struct core_context *core; + + core = get_core_data(mpidr); + mt_save_generic_timer(core->timer_data); + + /* disable timer irq, and upper layer should enable it again. */ + stop_generic_timer(); +} + +static void mt_cpu_restore(unsigned long mpidr) +{ + struct core_context *core; + + core = get_core_data(mpidr); + mt_restore_generic_timer(core->timer_data); +} + +static void mt_platform_save_context(unsigned long mpidr) +{ + /* mcusys_save_context: */ + mt_cpu_save(mpidr); +} + +static void mt_platform_restore_context(unsigned long mpidr) +{ + /* mcusys_restore_context: */ + mt_cpu_restore(mpidr); +} + +/******************************************************************************* +* Private function which is used to determine if any platform actions +* should be performed for the specified affinity instance given its +* state. Nothing needs to be done if the 'state' is not off or if this is not +* the highest affinity level which will enter the 'state'. +*******************************************************************************/ +static int32_t plat_do_plat_actions(unsigned int afflvl, unsigned int state) +{ + unsigned int max_phys_off_afflvl; + + assert(afflvl <= MPIDR_AFFLVL2); + + if (state != PSCI_STATE_OFF) + return -EAGAIN; + + /* + * Find the highest affinity level which will be suspended and postpone + * all the platform specific actions until that level is hit. + */ + max_phys_off_afflvl = psci_get_max_phys_off_afflvl(); + assert(max_phys_off_afflvl != PSCI_INVALID_DATA); + if (afflvl != max_phys_off_afflvl) + return -EAGAIN; + + return 0; +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance is about to enter + * standby. + ******************************************************************************/ +static void plat_affinst_standby(unsigned int power_state) +{ + unsigned int target_afflvl; + + /* Sanity check the requested state */ + target_afflvl = psci_get_pstate_afflvl(power_state); + + /* + * It's possible to enter standby only on affinity level 0 i.e. a cpu + * on the MTK_platform. Ignore any other affinity level. + */ + if (target_afflvl == MPIDR_AFFLVL0) { + /* + * Enter standby state. dsb is good practice before using wfi + * to enter low power states. + */ + dsb(); + wfi(); + } +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance is about to be turned + * on. The level and mpidr determine the affinity instance. + ******************************************************************************/ +static int plat_affinst_on(unsigned long mpidr, + unsigned long sec_entrypoint, + unsigned int afflvl, + unsigned int state) +{ + int rc = PSCI_E_SUCCESS; + unsigned long cpu_id; + unsigned long cluster_id; + uintptr_t rv; + + /* + * It's possible to turn on only affinity level 0 i.e. a cpu + * on the MTK_platform. Ignore any other affinity level. + */ + if (afflvl != MPIDR_AFFLVL0) + return rc; + + cpu_id = mpidr & MPIDR_CPU_MASK; + cluster_id = mpidr & MPIDR_CLUSTER_MASK; + + if (cluster_id) + rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw; + else + rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw; + + mmio_write_32(rv, sec_entrypoint); + INFO("mt_on[%ld:%ld], entry %x\n", + cluster_id, cpu_id, mmio_read_32(rv)); + + spm_hotplug_on(mpidr); + + return rc; +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance is about to be turned + * off. The level and mpidr determine the affinity instance. The 'state' arg. + * allows the platform to decide whether the cluster is being turned off and + * take apt actions. + * + * CAUTION: This function is called with coherent stacks so that caches can be + * turned off, flushed and coherency disabled. There is no guarantee that caches + * will remain turned on across calls to this function as each affinity level is + * dealt with. So do not write & read global variables across calls. It will be + * wise to do flush a write to the global to prevent unpredictable results. + ******************************************************************************/ +static void plat_affinst_off(unsigned int afflvl, unsigned int state) +{ + unsigned long mpidr = read_mpidr_el1(); + + /* Determine if any platform actions need to be executed. */ + if (plat_do_plat_actions(afflvl, state) == -EAGAIN) + return; + + /* Prevent interrupts from spuriously waking up this cpu */ + arm_gic_cpuif_deactivate(); + + spm_hotplug_off(mpidr); + + trace_power_flow(mpidr, CPU_DOWN); + + if (afflvl != MPIDR_AFFLVL0) { + /* Disable coherency if this cluster is to be turned off */ + plat_cci_disable(); + + trace_power_flow(mpidr, CLUSTER_DOWN); + } +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance is about to be + * suspended. The level and mpidr determine the affinity instance. The 'state' + * arg. allows the platform to decide whether the cluster is being turned off + * and take apt actions. + * + * CAUTION: This function is called with coherent stacks so that caches can be + * turned off, flushed and coherency disabled. There is no guarantee that caches + * will remain turned on across calls to this function as each affinity level is + * dealt with. So do not write & read global variables across calls. It will be + * wise to do flush a write to the global to prevent unpredictable results. + ******************************************************************************/ +static void plat_affinst_suspend(unsigned long sec_entrypoint, + unsigned int afflvl, + unsigned int state) +{ + unsigned long mpidr = read_mpidr_el1(); + unsigned long cluster_id; + unsigned long cpu_id; + uintptr_t rv; + + /* Determine if any platform actions need to be executed. */ + if (plat_do_plat_actions(afflvl, state) == -EAGAIN) + return; + + cpu_id = mpidr & MPIDR_CPU_MASK; + cluster_id = mpidr & MPIDR_CLUSTER_MASK; + + if (cluster_id) + rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw; + else + rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw; + + mmio_write_32(rv, sec_entrypoint); + + if (afflvl < MPIDR_AFFLVL2) + spm_mcdi_prepare_for_off_state(mpidr, afflvl); + + if (afflvl >= MPIDR_AFFLVL0) + mt_platform_save_context(mpidr); + + /* Perform the common cluster specific operations */ + if (afflvl >= MPIDR_AFFLVL1) { + /* Disable coherency if this cluster is to be turned off */ + plat_cci_disable(); + } + + if (afflvl >= MPIDR_AFFLVL2) { + disable_scu(mpidr); + generic_timer_backup(); + spm_system_suspend(); + /* Prevent interrupts from spuriously waking up this cpu */ + arm_gic_cpuif_deactivate(); + } +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance has just been powered + * on after being turned off earlier. The level and mpidr determine the affinity + * instance. The 'state' arg. allows the platform to decide whether the cluster + * was turned off prior to wakeup and do what's necessary to setup it up + * correctly. + ******************************************************************************/ +static void plat_affinst_on_finish(unsigned int afflvl, unsigned int state) +{ + unsigned long mpidr = read_mpidr_el1(); + + /* Determine if any platform actions need to be executed. */ + if (plat_do_plat_actions(afflvl, state) == -EAGAIN) + return; + + /* Perform the common cluster specific operations */ + if (afflvl >= MPIDR_AFFLVL1) { + /* Enable coherency if this cluster was off */ + plat_cci_enable(); + trace_power_flow(mpidr, CLUSTER_UP); + } + + /* Enable the gic cpu interface */ + arm_gic_cpuif_setup(); + arm_gic_pcpu_distif_setup(); + trace_power_flow(mpidr, CPU_UP); +} + +/******************************************************************************* + * MTK_platform handler called when an affinity instance has just been powered + * on after having been suspended earlier. The level and mpidr determine the + * affinity instance. + ******************************************************************************/ +static void plat_affinst_suspend_finish(unsigned int afflvl, unsigned int state) +{ + unsigned long mpidr = read_mpidr_el1(); + + /* Determine if any platform actions need to be executed. */ + if (plat_do_plat_actions(afflvl, state) == -EAGAIN) + return; + + if (afflvl >= MPIDR_AFFLVL2) { + /* Enable the gic cpu interface */ + arm_gic_setup(); + arm_gic_cpuif_setup(); + spm_system_suspend_finish(); + enable_scu(mpidr); + } + + /* Perform the common cluster specific operations */ + if (afflvl >= MPIDR_AFFLVL1) { + /* Enable coherency if this cluster was off */ + plat_cci_enable(); + } + + if (afflvl >= MPIDR_AFFLVL0) + mt_platform_restore_context(mpidr); + + if (afflvl < MPIDR_AFFLVL2) + spm_mcdi_finish_for_on_state(mpidr, afflvl); + + arm_gic_pcpu_distif_setup(); +} + +static unsigned int plat_get_sys_suspend_power_state(void) +{ + /* StateID: 0, StateType: 1(power down), PowerLevel: 2(system) */ + return psci_make_powerstate(0, 1, 2); +} + +/******************************************************************************* + * MTK handlers to shutdown/reboot the system + ******************************************************************************/ +static void __dead2 plat_system_off(void) +{ + INFO("MTK System Off\n"); + + rtc_bbpu_power_down(); + + wfi(); + ERROR("MTK System Off: operation not handled.\n"); + panic(); +} + +static void __dead2 plat_system_reset(void) +{ + /* Write the System Configuration Control Register */ + INFO("MTK System Reset\n"); + + mmio_clrsetbits_32(MTK_WDT_BASE, + (MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ), + MTK_WDT_MODE_KEY); + mmio_setbits_32(MTK_WDT_BASE, (MTK_WDT_MODE_KEY | MTK_WDT_MODE_EXTEN)); + mmio_setbits_32(MTK_WDT_SWRST, MTK_WDT_SWRST_KEY); + + wfi(); + ERROR("MTK System Reset: operation not handled.\n"); + panic(); +} + +/******************************************************************************* + * Export the platform handlers to enable psci to invoke them + ******************************************************************************/ +static const plat_pm_ops_t plat_plat_pm_ops = { + .affinst_standby = plat_affinst_standby, + .affinst_on = plat_affinst_on, + .affinst_off = plat_affinst_off, + .affinst_suspend = plat_affinst_suspend, + .affinst_on_finish = plat_affinst_on_finish, + .affinst_suspend_finish = plat_affinst_suspend_finish, + .system_off = plat_system_off, + .system_reset = plat_system_reset, + .get_sys_suspend_power_state = plat_get_sys_suspend_power_state, +}; + +/******************************************************************************* + * Export the platform specific power ops & initialize the mtk_platform power + * controller + ******************************************************************************/ +int platform_setup_pm(const plat_pm_ops_t **plat_ops) +{ + *plat_ops = &plat_plat_pm_ops; + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/plat_sip_calls.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/plat_sip_calls.c new file mode 100644 index 0000000..6969ee3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/plat_sip_calls.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include + +/* Authorized secure register list */ +enum { + SREG_HDMI_COLOR_EN = 0x14000904 +}; + +static const uint32_t authorized_sreg[] = { + SREG_HDMI_COLOR_EN +}; + +#define authorized_sreg_cnt \ + (sizeof(authorized_sreg) / sizeof(authorized_sreg[0])) + +uint64_t mt_sip_set_authorized_sreg(uint32_t sreg, uint32_t val) +{ + uint64_t i; + + for (i = 0; i < authorized_sreg_cnt; i++) { + if (authorized_sreg[i] == sreg) { + mmio_write_32(sreg, val); + return MTK_SIP_E_SUCCESS; + } + } + + return MTK_SIP_E_INVALID_PARAM; +} + +static uint64_t mt_sip_pwr_on_mtcmos(uint32_t val) +{ + uint32_t ret; + + ret = mtcmos_non_cpu_ctrl(1, val); + if (ret) + return MTK_SIP_E_INVALID_PARAM; + else + return MTK_SIP_E_SUCCESS; +} + +static uint64_t mt_sip_pwr_off_mtcmos(uint32_t val) +{ + uint32_t ret; + + ret = mtcmos_non_cpu_ctrl(0, val); + if (ret) + return MTK_SIP_E_INVALID_PARAM; + else + return MTK_SIP_E_SUCCESS; +} + +static uint64_t mt_sip_pwr_mtcmos_support(void) +{ + return MTK_SIP_E_SUCCESS; +} + +uint64_t mediatek_plat_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + uint64_t ret; + + switch (smc_fid) { + case MTK_SIP_PWR_ON_MTCMOS: + ret = mt_sip_pwr_on_mtcmos((uint32_t)x1); + SMC_RET1(handle, ret); + + case MTK_SIP_PWR_OFF_MTCMOS: + ret = mt_sip_pwr_off_mtcmos((uint32_t)x1); + SMC_RET1(handle, ret); + + case MTK_SIP_PWR_MTCMOS_SUPPORT: + ret = mt_sip_pwr_mtcmos_support(); + SMC_RET1(handle, ret); + + case MTK_SIP_SET_HDCP_KEY_EX: + ret = crypt_set_hdcp_key_ex(x1, x2, x3); + SMC_RET1(handle, ret); + + case MTK_SIP_SET_HDCP_KEY_NUM: + ret = crypt_set_hdcp_key_num((uint32_t)x1); + SMC_RET1(handle, ret); + + case MTK_SIP_CLR_HDCP_KEY: + ret = crypt_clear_hdcp_key(); + SMC_RET1(handle, ret); + + default: + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + break; + } + + SMC_RET1(handle, SMC_UNK); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/plat_topology.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/plat_topology.c new file mode 100644 index 0000000..96598b6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/plat_topology.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr) +{ + /* Report 1 (absent) instance at levels higher that the cluster level */ + if (aff_lvl > MPIDR_AFFLVL1) + return PLATFORM_SYSTEM_COUNT; + + if (aff_lvl == MPIDR_AFFLVL1) + return PLATFORM_CLUSTER_COUNT; + + return mpidr & 0x100 ? PLATFORM_CLUSTER1_CORE_COUNT : + PLATFORM_CLUSTER0_CORE_COUNT; +} + +unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr) +{ + return aff_lvl <= MPIDR_AFFLVL2 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT; +} + +int mt_setup_topology(void) +{ + /* [TODO] Make topology configurable via SCC */ + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/platform.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/platform.mk new file mode 100644 index 0000000..54ca475 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/platform.mk @@ -0,0 +1,95 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +MTK_PLAT := plat/mediatek +MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT} + +PLAT_INCLUDES := -I${MTK_PLAT}/common/ \ + -I${MTK_PLAT}/common/drivers/uart/ \ + -I${MTK_PLAT_SOC}/drivers/crypt/ \ + -I${MTK_PLAT_SOC}/drivers/mtcmos/ \ + -I${MTK_PLAT_SOC}/drivers/pmic/ \ + -I${MTK_PLAT_SOC}/drivers/rtc/ \ + -I${MTK_PLAT_SOC}/drivers/spm/ \ + -I${MTK_PLAT_SOC}/drivers/timer/ \ + -I${MTK_PLAT_SOC}/include/ + +PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ + lib/xlat_tables/aarch64/xlat_tables.c \ + plat/common/aarch64/plat_common.c \ + plat/common/plat_gic.c + +BL31_SOURCES += drivers/arm/cci/cci.c \ + drivers/arm/gic/arm_gic.c \ + drivers/arm/gic/gic_v2.c \ + drivers/arm/gic/gic_v3.c \ + drivers/console/aarch64/console.S \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + lib/cpus/aarch64/cortex_a72.S \ + plat/common/aarch64/platform_mp_stack.S \ + ${MTK_PLAT}/common/drivers/uart/8250_console.S \ + ${MTK_PLAT}/common/mtk_plat_common.c \ + ${MTK_PLAT}/common/mtk_sip_svc.c \ + ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \ + ${MTK_PLAT_SOC}/aarch64/platform_common.c \ + ${MTK_PLAT_SOC}/bl31_plat_setup.c \ + ${MTK_PLAT_SOC}/drivers/crypt/crypt.c \ + ${MTK_PLAT_SOC}/drivers/mtcmos/mtcmos.c \ + ${MTK_PLAT_SOC}/drivers/pmic/pmic_wrap_init.c \ + ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \ + ${MTK_PLAT_SOC}/drivers/spm/spm.c \ + ${MTK_PLAT_SOC}/drivers/spm/spm_hotplug.c \ + ${MTK_PLAT_SOC}/drivers/spm/spm_mcdi.c \ + ${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c \ + ${MTK_PLAT_SOC}/drivers/timer/mt_cpuxgpt.c \ + ${MTK_PLAT_SOC}/plat_mt_gic.c \ + ${MTK_PLAT_SOC}/plat_pm.c \ + ${MTK_PLAT_SOC}/plat_sip_calls.c \ + ${MTK_PLAT_SOC}/plat_topology.c \ + ${MTK_PLAT_SOC}/power_tracer.c \ + ${MTK_PLAT_SOC}/scu.c + +# Flag used by the MTK_platform port to determine the version of ARM GIC +# architecture to use for interrupt management in EL3. +ARM_GIC_ARCH := 2 +$(eval $(call add_define,ARM_GIC_ARCH)) + +# Enable workarounds for selected Cortex-A53 erratas. +ERRATA_A53_826319 := 1 +ERRATA_A53_836870 := 1 + +# indicate the reset vector address can be programmed +PROGRAMMABLE_RESET_ADDRESS := 1 + +$(eval $(call add_define,MTK_SIP_SET_AUTHORIZED_SECURE_REG_ENABLE)) diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/power_tracer.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/power_tracer.c new file mode 100644 index 0000000..15eb2ce --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/power_tracer.c @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#define trace_log(...) INFO("psci: " __VA_ARGS__) + +void trace_power_flow(unsigned long mpidr, unsigned char mode) +{ + switch (mode) { + case CPU_UP: + trace_log("core %ld:%ld ON\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, + (mpidr & MPIDR_CPU_MASK)); + break; + case CPU_DOWN: + trace_log("core %ld:%ld OFF\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, + (mpidr & MPIDR_CPU_MASK)); + break; + case CPU_SUSPEND: + trace_log("core %ld:%ld SUSPEND\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS, + (mpidr & MPIDR_CPU_MASK)); + break; + case CLUSTER_UP: + trace_log("cluster %ld ON\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); + break; + case CLUSTER_DOWN: + trace_log("cluster %ld OFF\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); + break; + case CLUSTER_SUSPEND: + trace_log("cluster %ld SUSPEND\n", + (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS); + break; + default: + trace_log("unknown power mode\n"); + break; + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/scu.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/scu.c new file mode 100644 index 0000000..88af787 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/mediatek/mt8173/scu.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +void disable_scu(unsigned long mpidr) +{ + if (mpidr & MPIDR_CLUSTER_MASK) + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, + MP1_ACINACTM); + else + mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, + MP0_ACINACTM); +} + +void enable_scu(unsigned long mpidr) +{ + if (mpidr & MPIDR_CLUSTER_MASK) + mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, + MP1_ACINACTM); + else + mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config, + MP0_ACINACTM); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/aarch64/tegra_helpers.S new file mode 100644 index 0000000..905c4c5 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -0,0 +1,368 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include + + /* Global functions */ + .globl plat_is_my_cpu_primary + .globl plat_my_core_pos + .globl plat_get_my_entrypoint + .globl plat_secondary_cold_boot_setup + .globl platform_mem_init + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl tegra_secure_entrypoint + .globl plat_reset_handler + + /* Global variables */ + .globl tegra_sec_entry_point + .globl ns_image_entrypoint + .globl tegra_bl31_phys_base + + /* --------------------- + * Common CPU init code + * --------------------- + */ +.macro cpu_init_common + +#if ENABLE_L2_DYNAMIC_RETENTION + /* --------------------------- + * Enable processor retention + * --------------------------- + */ + mrs x0, L2ECTLR_EL1 + mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT + bic x0, x0, #L2ECTLR_RET_CTRL_MASK + orr x0, x0, x1 + msr L2ECTLR_EL1, x0 + isb +#endif + +#if ENABLE_CPU_DYNAMIC_RETENTION + mrs x0, CPUECTLR_EL1 + mov x1, #RETENTION_ENTRY_TICKS_512 << CPUECTLR_CPU_RET_CTRL_SHIFT + bic x0, x0, #CPUECTLR_CPU_RET_CTRL_MASK + orr x0, x0, x1 + msr CPUECTLR_EL1, x0 + isb +#endif + +#if ENABLE_NS_L2_CPUECTRL_RW_ACCESS + /* ------------------------------------------------------- + * Enable L2 and CPU ECTLR RW access from non-secure world + * ------------------------------------------------------- + */ + mov x0, #ACTLR_EL3_ENABLE_ALL_ACCESS + msr actlr_el3, x0 + msr actlr_el2, x0 + isb +#endif + + /* -------------------------------- + * Enable the cycle count register + * -------------------------------- + */ + mrs x0, pmcr_el0 + ubfx x0, x0, #11, #5 // read PMCR.N field + mov x1, #1 + lsl x0, x1, x0 + sub x0, x0, #1 // mask of event counters + orr x0, x0, #0x80000000 // disable overflow intrs + msr pmintenclr_el1, x0 + msr pmuserenr_el0, x1 // enable user mode access + + /* ---------------------------------------------------------------- + * Allow non-privileged access to CNTVCT: Set CNTKCTL (Kernel Count + * register), bit 1 (EL0VCTEN) to enable access to CNTVCT/CNTFRQ + * registers from EL0. + * ---------------------------------------------------------------- + */ + mrs x0, cntkctl_el1 + orr x0, x0, #EL0VCTEN_BIT + msr cntkctl_el1, x0 +.endm + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary(void); + * + * This function checks if this is the Primary CPU + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #TEGRA_PRIMARY_CPU + cset x0, eq + ret +endfunc plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * unsigned int plat_my_core_pos(void); + * + * result: CorePos = CoreId + (ClusterId << 2) + * ----------------------------------------------------- + */ +func plat_my_core_pos + mrs x0, mpidr_el1 + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc plat_my_core_pos + + /* ----------------------------------------------------- + * unsigned long plat_get_my_entrypoint (void); + * + * Main job of this routine is to distinguish between + * a cold and warm boot. If the tegra_sec_entry_point for + * this CPU is present, then it's a warm boot. + * + * ----------------------------------------------------- + */ +func plat_get_my_entrypoint + adr x1, tegra_sec_entry_point + ldr x0, [x1] + ret +endfunc plat_get_my_entrypoint + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset. Right + * now this is a stub function. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + mov x0, #0 + ret +endfunc plat_secondary_cold_boot_setup + + /* -------------------------------------------------------- + * void platform_mem_init (void); + * + * Any memory init, relocation to be done before the + * platform boots. Called very early in the boot process. + * -------------------------------------------------------- + */ +func platform_mem_init + mov x0, #0 + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0 - x4 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, TEGRA_BOOT_UART_BASE + mov_imm x1, TEGRA_BOOT_UART_CLK_IN_HZ + mov_imm x2, TEGRA_CONSOLE_BAUDRATE + b console_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(void) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, TEGRA_BOOT_UART_BASE + b console_core_putc +endfunc plat_crash_console_putc + + /* --------------------------------------------------- + * Function to handle a platform reset and store + * input parameters passed by BL2. + * --------------------------------------------------- + */ +func plat_reset_handler + + /* ----------------------------------- + * derive and save the phys_base addr + * ----------------------------------- + */ + adr x17, tegra_bl31_phys_base + ldr x18, [x17] + cbnz x18, 1f + adr x18, bl31_entrypoint + str x18, [x17] + +1: cpu_init_common + + ret +endfunc plat_reset_handler + + /* ---------------------------------------- + * Secure entrypoint function for CPU boot + * ---------------------------------------- + */ + .align 6 +func tegra_secure_entrypoint + +#if ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT + + /* ------------------------------------------------------- + * Invalidate BTB along with I$ to remove any stale + * entries from the branch predictor array. + * ------------------------------------------------------- + */ + mrs x0, CPUACTLR_EL1 + orr x0, x0, #1 + msr CPUACTLR_EL1, x0 /* invalidate BTB and I$ together */ + dsb sy + isb + ic iallu /* actual invalidate */ + dsb sy + isb + + mrs x0, CPUACTLR_EL1 + bic x0, x0, #1 + msr CPUACTLR_EL1, X0 /* restore original CPUACTLR_EL1 */ + dsb sy + isb + + .rept 7 + nop /* wait */ + .endr + + /* ----------------------------------------------- + * Extract OSLK bit and check if it is '1'. This + * bit remains '0' for A53 on warm-resets. If '1', + * turn off regional clock gating and request warm + * reset. + * ----------------------------------------------- + */ + mrs x0, oslsr_el1 + and x0, x0, #2 + mrs x1, mpidr_el1 + bics xzr, x0, x1, lsr #7 /* 0 = slow cluster or warm reset */ + b.eq restore_oslock + mov x0, xzr + msr oslar_el1, x0 /* os lock stays 0 across warm reset */ + mov x3, #3 + movz x4, #0x8000, lsl #48 + msr CPUACTLR_EL1, x4 /* turn off RCG */ + isb + msr rmr_el3, x3 /* request warm reset */ + isb + dsb sy +1: wfi + b 1b + + /* -------------------------------------------------- + * These nops are here so that speculative execution + * won't harm us before we are done with warm reset. + * -------------------------------------------------- + */ + .rept 65 + nop + .endr + + /* -------------------------------------------------- + * Do not insert instructions here + * -------------------------------------------------- + */ +#endif + + /* -------------------------------------------------- + * Restore OS Lock bit + * -------------------------------------------------- + */ +restore_oslock: + mov x0, #1 + msr oslar_el1, x0 + + cpu_init_common + + /* --------------------------------------------------------------------- + * The initial state of the Architectural feature trap register + * (CPTR_EL3) is unknown and it must be set to a known state. All + * feature traps are disabled. Some bits in this register are marked as + * Reserved and should not be modified. + * + * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 + * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. + * CPTR_EL3.TTA: This causes access to the Trace functionality to trap + * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register + * access to trace functionality is not supported, this bit is RES0. + * CPTR_EL3.TFP: This causes instructions that access the registers + * associated with Floating Point and Advanced SIMD execution to trap + * to EL3 when executed from any exception level, unless trapped to EL1 + * or EL2. + * --------------------------------------------------------------------- + */ + mrs x1, cptr_el3 + bic w1, w1, #TCPAC_BIT + bic w1, w1, #TTA_BIT + bic w1, w1, #TFP_BIT + msr cptr_el3, x1 + + /* -------------------------------------------------- + * Get secure world's entry point and jump to it + * -------------------------------------------------- + */ + bl plat_get_my_entrypoint + br x0 +endfunc tegra_secure_entrypoint + + .data + .align 3 + + /* -------------------------------------------------- + * CPU Secure entry point - resume from suspend + * -------------------------------------------------- + */ +tegra_sec_entry_point: + .quad 0 + + /* -------------------------------------------------- + * NS world's cold boot entry point + * -------------------------------------------------- + */ +ns_image_entrypoint: + .quad 0 + + /* -------------------------------------------------- + * BL31's physical base address + * -------------------------------------------------- + */ +tegra_bl31_phys_base: + .quad 0 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c new file mode 100644 index 0000000..3571758 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/drivers/flowctrl/flowctrl.c @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CLK_RST_DEV_L_SET 0x300 +#define CLK_RST_DEV_L_CLR 0x304 +#define CLK_BPMP_RST (1 << 1) + +#define EVP_BPMP_RESET_VECTOR 0x200 + +static const uint64_t flowctrl_offset_cpu_csr[4] = { + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU0_CSR), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 8), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CPU1_CSR + 16) +}; + +static const uint64_t flowctrl_offset_halt_cpu[4] = { + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU0_EVENTS), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 8), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_HALT_CPU1_EVENTS + 16) +}; + +static const uint64_t flowctrl_offset_cc4_ctrl[4] = { + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 4), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 8), + (TEGRA_FLOWCTRL_BASE + FLOWCTRL_CC4_CORE0_CTRL + 12) +}; + +static inline void tegra_fc_cc4_ctrl(int cpu_id, uint32_t val) +{ + mmio_write_32(flowctrl_offset_cc4_ctrl[cpu_id], val); + val = mmio_read_32(flowctrl_offset_cc4_ctrl[cpu_id]); +} + +static inline void tegra_fc_cpu_csr(int cpu_id, uint32_t val) +{ + mmio_write_32(flowctrl_offset_cpu_csr[cpu_id], val); + val = mmio_read_32(flowctrl_offset_cpu_csr[cpu_id]); +} + +static inline void tegra_fc_halt_cpu(int cpu_id, uint32_t val) +{ + mmio_write_32(flowctrl_offset_halt_cpu[cpu_id], val); + val = mmio_read_32(flowctrl_offset_halt_cpu[cpu_id]); +} + +static void tegra_fc_prepare_suspend(int cpu_id, uint32_t csr) +{ + uint32_t val; + + val = FLOWCTRL_HALT_GIC_IRQ | FLOWCTRL_HALT_GIC_FIQ | + FLOWCTRL_HALT_LIC_IRQ | FLOWCTRL_HALT_LIC_FIQ | + FLOWCTRL_WAITEVENT; + tegra_fc_halt_cpu(cpu_id, val); + + val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG | + FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu_id); + tegra_fc_cpu_csr(cpu_id, val | csr); +} + +/******************************************************************************* + * Powerdn the current CPU + ******************************************************************************/ +void tegra_fc_cpu_powerdn(uint32_t mpidr) +{ + int cpu = mpidr & MPIDR_CPU_MASK; + + VERBOSE("CPU%d powering down...\n", cpu); + tegra_fc_prepare_suspend(cpu, 0); +} + +/******************************************************************************* + * Suspend the current CPU cluster + ******************************************************************************/ +void tegra_fc_cluster_idle(uint32_t mpidr) +{ + int cpu = mpidr & MPIDR_CPU_MASK; + uint32_t val; + + VERBOSE("Entering cluster idle state...\n"); + + tegra_fc_cc4_ctrl(cpu, 0); + + /* hardware L2 flush is faster for A53 only */ + tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, + !!MPIDR_AFFLVL1_VAL(mpidr)); + + /* suspend the CPU cluster */ + val = FLOWCTRL_PG_CPU_NONCPU << FLOWCTRL_ENABLE_EXT; + tegra_fc_prepare_suspend(cpu, val); +} + +/******************************************************************************* + * Power down the current CPU cluster + ******************************************************************************/ +void tegra_fc_cluster_powerdn(uint32_t mpidr) +{ + int cpu = mpidr & MPIDR_CPU_MASK; + uint32_t val; + + VERBOSE("Entering cluster powerdn state...\n"); + + tegra_fc_cc4_ctrl(cpu, 0); + + /* hardware L2 flush is faster for A53 only */ + tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, + read_midr() == CORTEX_A53_MIDR); + + /* power down the CPU cluster */ + val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT; + tegra_fc_prepare_suspend(cpu, val); +} + +/******************************************************************************* + * Suspend the entire SoC + ******************************************************************************/ +void tegra_fc_soc_powerdn(uint32_t mpidr) +{ + int cpu = mpidr & MPIDR_CPU_MASK; + uint32_t val; + + VERBOSE("Entering SoC powerdn state...\n"); + + tegra_fc_cc4_ctrl(cpu, 0); + + tegra_fc_write_32(FLOWCTRL_L2_FLUSH_CONTROL, 1); + + val = FLOWCTRL_TURNOFF_CPURAIL << FLOWCTRL_ENABLE_EXT; + tegra_fc_prepare_suspend(cpu, val); + + /* overwrite HALT register */ + tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT); +} + +/******************************************************************************* + * Power up the CPU + ******************************************************************************/ +void tegra_fc_cpu_on(int cpu) +{ + tegra_fc_cpu_csr(cpu, FLOWCTRL_CSR_ENABLE); + tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT | FLOWCTRL_HALT_SCLK); +} + +/******************************************************************************* + * Power down the CPU + ******************************************************************************/ +void tegra_fc_cpu_off(int cpu) +{ + uint32_t val; + + /* + * Flow controller powers down the CPU during wfi. The CPU would be + * powered on when it receives any interrupt. + */ + val = FLOWCTRL_CSR_INTR_FLAG | FLOWCTRL_CSR_EVENT_FLAG | + FLOWCTRL_CSR_ENABLE | (FLOWCTRL_WAIT_WFI_BITMAP << cpu); + tegra_fc_cpu_csr(cpu, val); + tegra_fc_halt_cpu(cpu, FLOWCTRL_WAITEVENT); + tegra_fc_cc4_ctrl(cpu, 0); +} + +/******************************************************************************* + * Inform the BPMP that we have completed the cluster power up + ******************************************************************************/ +void tegra_fc_lock_active_cluster(void) +{ + uint32_t val; + + val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL); + val |= FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK; + tegra_fc_write_32(FLOWCTRL_BPMP_CLUSTER_CONTROL, val); + val = tegra_fc_read_32(FLOWCTRL_BPMP_CLUSTER_CONTROL); +} + +/******************************************************************************* + * Reset BPMP processor + ******************************************************************************/ +void tegra_fc_reset_bpmp(void) +{ + uint32_t val; + + /* halt BPMP */ + tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, FLOWCTRL_WAITEVENT); + + /* Assert BPMP reset */ + mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_SET, CLK_BPMP_RST); + + /* Restore reset address (stored in PMC_SCRATCH39) */ + val = tegra_pmc_read_32(PMC_SCRATCH39); + mmio_write_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR, val); + while (val != mmio_read_32(TEGRA_EVP_BASE + EVP_BPMP_RESET_VECTOR)) + ; /* wait till value reaches EVP_BPMP_RESET_VECTOR */ + + /* Wait for 2us before de-asserting the reset signal. */ + udelay(2); + + /* De-assert BPMP reset */ + mmio_write_32(TEGRA_CAR_RESET_BASE + CLK_RST_DEV_L_CLR, CLK_BPMP_RST); + + /* Un-halt BPMP */ + tegra_fc_write_32(FLOWCTRL_HALT_BPMP_EVENTS, 0); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c new file mode 100644 index 0000000..40d1bab --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +extern void zeromem16(void *mem, unsigned int length); + +#define TEGRA_GPU_RESET_REG_OFFSET 0x28c +#define GPU_RESET_BIT (1 << 24) + +/* Video Memory base and size (live values) */ +static uintptr_t video_mem_base; +static uint64_t video_mem_size; + +/* + * Init SMMU. + */ +void tegra_memctrl_setup(void) +{ + /* + * Setup the Memory controller to allow only secure accesses to + * the TZDRAM carveout + */ + INFO("Configuring SMMU\n"); + + /* allow translations for all MC engines */ + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_1_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_2_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_3_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_4_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + + tegra_mc_write_32(MC_SMMU_ASID_SECURITY_0, MC_SMMU_ASID_SECURITY); + + tegra_mc_write_32(MC_SMMU_TLB_CONFIG_0, MC_SMMU_TLB_CONFIG_0_RESET_VAL); + tegra_mc_write_32(MC_SMMU_PTC_CONFIG_0, MC_SMMU_PTC_CONFIG_0_RESET_VAL); + + /* flush PTC and TLB */ + tegra_mc_write_32(MC_SMMU_PTC_FLUSH_0, MC_SMMU_PTC_FLUSH_ALL); + (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ + tegra_mc_write_32(MC_SMMU_TLB_FLUSH_0, MC_SMMU_TLB_FLUSH_ALL); + + /* enable SMMU */ + tegra_mc_write_32(MC_SMMU_CONFIG_0, + MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE); + (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ + + /* video memory carveout */ + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, video_mem_base); + tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); +} + +/* + * Secure the BL31 DRAM aperture. + * + * phys_base = physical base of TZDRAM aperture + * size_in_bytes = size of aperture in bytes + */ +void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) +{ + /* + * Setup the Memory controller to allow only secure accesses to + * the TZDRAM carveout + */ + INFO("Configuring TrustZone DRAM Memory Carveout\n"); + + tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base); + tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); +} + +static void tegra_clear_videomem(uintptr_t non_overlap_area_start, + unsigned long long non_overlap_area_size) +{ + /* + * Perform cache maintenance to ensure that the non-overlapping area is + * zeroed out. The first invalidation of this range ensures that + * possible evictions of dirty cache lines do not interfere with the + * 'zeromem16' operation. Other CPUs could speculatively prefetch the + * main memory contents of this area between the first invalidation and + * the 'zeromem16' operation. The second invalidation ensures that any + * such cache lines are removed as well. + */ + inv_dcache_range(non_overlap_area_start, non_overlap_area_size); + zeromem16((void *)non_overlap_area_start, non_overlap_area_size); + inv_dcache_range(non_overlap_area_start, non_overlap_area_size); +} + +/* + * Program the Video Memory carveout region + * + * phys_base = physical base of aperture + * size_in_bytes = size of aperture in bytes + */ +void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) +{ + uintptr_t vmem_end_old = video_mem_base + (video_mem_size << 20); + uintptr_t vmem_end_new = phys_base + size_in_bytes; + uint32_t regval; + unsigned long long non_overlap_area_size; + + /* + * The GPU is the user of the Video Memory region. In order to + * transition to the new memory region smoothly, we program the + * new base/size ONLY if the GPU is in reset mode. + */ + regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); + if ((regval & GPU_RESET_BIT) == 0) { + ERROR("GPU not in reset! Video Memory setup failed\n"); + return; + } + + /* + * Setup the Memory controller to restrict CPU accesses to the Video + * Memory region + */ + INFO("Configuring Video Memory Carveout\n"); + + /* + * Configure Memory Controller directly for the first time. + */ + if (video_mem_base == 0) + goto done; + + /* + * Clear the old regions now being exposed. The following cases + * can occur - + * + * 1. clear whole old region (no overlap with new region) + * 2. clear old sub-region below new base + * 3. clear old sub-region above new end + */ + INFO("Cleaning previous Video Memory Carveout\n"); + + disable_mmu_el3(); + if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) { + tegra_clear_videomem(video_mem_base, video_mem_size << 20); + } else { + if (video_mem_base < phys_base) { + non_overlap_area_size = phys_base - video_mem_base; + tegra_clear_videomem(video_mem_base, non_overlap_area_size); + } + if (vmem_end_old > vmem_end_new) { + non_overlap_area_size = vmem_end_old - vmem_end_new; + tegra_clear_videomem(vmem_end_new, non_overlap_area_size); + } + } + enable_mmu_el3(0); + +done: + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, phys_base); + tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); + + /* store new values */ + video_mem_base = phys_base; + video_mem_size = size_in_bytes >> 20; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/drivers/pmc/pmc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/drivers/pmc/pmc.c new file mode 100644 index 0000000..d48b575 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/drivers/pmc/pmc.c @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +/* Module IDs used during power ungate procedure */ +static const int pmc_cpu_powergate_id[4] = { + 0, /* CPU 0 */ + 9, /* CPU 1 */ + 10, /* CPU 2 */ + 11 /* CPU 3 */ +}; + +/******************************************************************************* + * Power ungate CPU to start the boot process. CPU reset vectors must be + * populated before calling this function. + ******************************************************************************/ +void tegra_pmc_cpu_on(int cpu) +{ + uint32_t val; + + /* + * Check if CPU is already power ungated + */ + val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); + if (val & (1 << pmc_cpu_powergate_id[cpu])) + return; + + /* + * The PMC deasserts the START bit when it starts the power + * ungate process. Loop till no power toggle is in progress. + */ + do { + val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); + } while (val & PMC_TOGGLE_START); + + /* + * Start the power ungate procedure + */ + val = pmc_cpu_powergate_id[cpu] | PMC_TOGGLE_START; + tegra_pmc_write_32(PMC_PWRGATE_TOGGLE, val); + + /* + * The PMC deasserts the START bit when it starts the power + * ungate process. Loop till powergate START bit is asserted. + */ + do { + val = tegra_pmc_read_32(PMC_PWRGATE_TOGGLE); + } while (val & (1 << 8)); + + /* loop till the CPU is power ungated */ + do { + val = tegra_pmc_read_32(PMC_PWRGATE_STATUS); + } while ((val & (1 << pmc_cpu_powergate_id[cpu])) == 0); +} + +/******************************************************************************* + * Setup CPU vectors for resume from deep sleep + ******************************************************************************/ +void tegra_pmc_cpu_setup(uint64_t reset_addr) +{ + uint32_t val; + + tegra_pmc_write_32(PMC_SECURE_SCRATCH34, (reset_addr & 0xFFFFFFFF) | 1); + val = reset_addr >> 32; + tegra_pmc_write_32(PMC_SECURE_SCRATCH35, val & 0x7FF); +} + +/******************************************************************************* + * Lock CPU vectors to restrict further writes + ******************************************************************************/ +void tegra_pmc_lock_cpu_vectors(void) +{ + uint32_t val; + + /* lock PMC_SECURE_SCRATCH22 */ + val = tegra_pmc_read_32(PMC_SECURE_DISABLE2); + val |= PMC_SECURE_DISABLE2_WRITE22_ON; + tegra_pmc_write_32(PMC_SECURE_DISABLE2, val); + + /* lock PMC_SECURE_SCRATCH34/35 */ + val = tegra_pmc_read_32(PMC_SECURE_DISABLE3); + val |= (PMC_SECURE_DISABLE3_WRITE34_ON | + PMC_SECURE_DISABLE3_WRITE35_ON); + tegra_pmc_write_32(PMC_SECURE_DISABLE3, val); +} + +/******************************************************************************* + * Restart the system + ******************************************************************************/ +__dead2 void tegra_pmc_system_reset(void) +{ + uint32_t reg; + + reg = tegra_pmc_read_32(PMC_CONFIG); + reg |= 0x10; /* restart */ + tegra_pmc_write_32(PMC_CONFIG, reg); + wfi(); + + ERROR("Tegra System Reset: operation not handled.\n"); + panic(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_bl31_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_bl31_setup.c new file mode 100644 index 0000000..7e2bebe --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_bl31_setup.c @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Declarations of linker defined symbols which will help us find the layout + * of trusted SRAM + ******************************************************************************/ +extern unsigned long __RO_START__; +extern unsigned long __RO_END__; +extern unsigned long __BL31_END__; + +#if USE_COHERENT_MEM +extern unsigned long __COHERENT_RAM_START__; +extern unsigned long __COHERENT_RAM_END__; +#endif + +extern uint64_t tegra_bl31_phys_base; + +/* + * The next 3 constants identify the extents of the code, RO data region and the + * limit of the BL3-1 image. These addresses are used by the MMU setup code and + * therefore they must be page-aligned. It is the responsibility of the linker + * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_RO_BASE (unsigned long)(&__RO_START__) +#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +#define BL31_END (unsigned long)(&__BL31_END__) + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif + +static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info; +static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { + .tzdram_size = (uint64_t)TZDRAM_SIZE +}; + +/******************************************************************************* + * This variable holds the non-secure image entry address + ******************************************************************************/ +extern uint64_t ns_image_entrypoint; + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + if (type == NON_SECURE) + return &bl33_image_ep_info; + + if (type == SECURE) + return &bl32_image_ep_info; + + return NULL; +} + +/******************************************************************************* + * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image + * passes this platform specific information. + ******************************************************************************/ +plat_params_from_bl2_t *bl31_get_plat_params(void) +{ + return &plat_bl31_params_from_bl2; +} + +/******************************************************************************* + * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image + * info. + ******************************************************************************/ +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +{ + plat_params_from_bl2_t *plat_params = + (plat_params_from_bl2_t *)plat_params_from_bl2; + + /* + * Configure the UART port to be used as the console + */ + console_init(TEGRA_BOOT_UART_BASE, TEGRA_BOOT_UART_CLK_IN_HZ, + TEGRA_CONSOLE_BAUDRATE); + + /* Initialise crash console */ + plat_crash_console_init(); + + /* + * Copy BL3-3, BL3-2 entry point information. + * They are stored in Secure RAM, in BL2's address space. + */ + bl33_image_ep_info = *from_bl2->bl33_ep_info; + bl32_image_ep_info = *from_bl2->bl32_ep_info; + + /* + * Parse platform specific parameters - TZDRAM aperture size + */ + if (plat_params) + plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size; +} + +/******************************************************************************* + * Initialize the gic, configure the SCR. + ******************************************************************************/ +void bl31_platform_setup(void) +{ + uint32_t tmp_reg; + + /* + * Initialize delay timer + */ + tegra_delay_timer_init(); + + /* + * Setup secondary CPU POR infrastructure. + */ + plat_secondary_setup(); + + /* + * Initial Memory Controller configuration. + */ + tegra_memctrl_setup(); + + /* + * Do initial security configuration to allow DRAM/device access. + */ + tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, + plat_bl31_params_from_bl2.tzdram_size); + + /* Set the next EL to be AArch64 */ + tmp_reg = SCR_RES1_BITS | SCR_RW_BIT; + write_scr(tmp_reg); + + /* Initialize the gic cpu and distributor interfaces */ + tegra_gic_setup(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this only intializes the mmu in a quick and dirty way. + ******************************************************************************/ +void bl31_plat_arch_setup(void) +{ + unsigned long bl31_base_pa = tegra_bl31_phys_base; + unsigned long total_base = bl31_base_pa; + unsigned long total_size = BL32_BASE - BL31_RO_BASE; + unsigned long ro_start = bl31_base_pa; + unsigned long ro_size = BL31_RO_LIMIT - BL31_RO_BASE; + const mmap_region_t *plat_mmio_map = NULL; +#if USE_COHERENT_MEM + unsigned long coh_start, coh_size; +#endif + + /* add memory regions */ + mmap_add_region(total_base, total_base, + total_size, + MT_MEMORY | MT_RW | MT_SECURE); + mmap_add_region(ro_start, ro_start, + ro_size, + MT_MEMORY | MT_RO | MT_SECURE); + +#if USE_COHERENT_MEM + coh_start = total_base + (BL31_COHERENT_RAM_BASE - BL31_RO_BASE); + coh_size = BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE; + + mmap_add_region(coh_start, coh_start, + coh_size, + MT_DEVICE | MT_RW | MT_SECURE); +#endif + + /* add MMIO space */ + plat_mmio_map = plat_get_mmio_map(); + if (plat_mmio_map) + mmap_add(plat_mmio_map); + else + WARN("MMIO map not available\n"); + + /* set up translation tables */ + init_xlat_tables(); + + /* enable the MMU */ + enable_mmu_el3(0); +} + +/******************************************************************************* + * Check if the given NS DRAM range is valid + ******************************************************************************/ +int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes) +{ + uint64_t end = base + size_in_bytes - 1; + + /* + * Check if the NS DRAM address is valid + */ + if ((base < TEGRA_DRAM_BASE) || (end > TEGRA_DRAM_END) || + (base >= end)) { + ERROR("NS address is out-of-bounds!\n"); + return -EFAULT; + } + + /* + * TZDRAM aperture contains the BL31 and BL32 images, so we need + * to check if the NS DRAM range overlaps the TZDRAM aperture. + */ + if ((base < TZDRAM_END) && (end > tegra_bl31_phys_base)) { + ERROR("NS address overlaps TZDRAM!\n"); + return -ENOTSUP; + } + + /* valid NS address */ + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_common.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_common.mk new file mode 100644 index 0000000..3c07032 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_common.mk @@ -0,0 +1,65 @@ +# +# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +CRASH_REPORTING := 1 +$(eval $(call add_define,CRASH_REPORTING)) + +ASM_ASSERTION := 1 +$(eval $(call add_define,ASM_ASSERTION)) + +USE_COHERENT_MEM := 0 + +PLAT_INCLUDES := -Iplat/nvidia/tegra/include/drivers \ + -Iplat/nvidia/tegra/include \ + -Iplat/nvidia/tegra/include/${TARGET_SOC} + +PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ + lib/xlat_tables/aarch64/xlat_tables.c \ + plat/common/aarch64/plat_common.c + +COMMON_DIR := plat/nvidia/tegra/common + +BL31_SOURCES += drivers/arm/gic/gic_v2.c \ + drivers/arm/gic/gic_v3.c \ + drivers/console/aarch64/console.S \ + drivers/delay_timer/delay_timer.c \ + drivers/ti/uart/aarch64/16550_console.S \ + plat/common/aarch64/platform_mp_stack.S \ + plat/common/plat_psci_common.c \ + ${COMMON_DIR}/aarch64/tegra_helpers.S \ + ${COMMON_DIR}/drivers/memctrl/memctrl.c \ + ${COMMON_DIR}/drivers/pmc/pmc.c \ + ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ + ${COMMON_DIR}/tegra_bl31_setup.c \ + ${COMMON_DIR}/tegra_delay_timer.c \ + ${COMMON_DIR}/tegra_gic.c \ + ${COMMON_DIR}/tegra_pm.c \ + ${COMMON_DIR}/tegra_sip_calls.c \ + ${COMMON_DIR}/tegra_topology.c diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_delay_timer.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_delay_timer.c new file mode 100644 index 0000000..e1f6ede --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_delay_timer.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +static uint32_t tegra_timerus_get_value(void) +{ + return mmio_read_32(TEGRA_TMRUS_BASE); +} + +static const timer_ops_t tegra_timer_ops = { + .get_timer_value = tegra_timerus_get_value, + .clk_mult = 1, + .clk_div = 1, +}; + +/* + * Initialise the on-chip free rolling us counter as the delay + * timer. + */ +void tegra_delay_timer_init(void) +{ + timer_init(&tegra_timer_ops); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gic.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gic.c new file mode 100644 index 0000000..ee12975 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_gic.c @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Value used to initialize Non-Secure IRQ priorities four at a time */ +#define GICD_IPRIORITYR_DEF_VAL \ + (GIC_HIGHEST_NS_PRIORITY | \ + (GIC_HIGHEST_NS_PRIORITY << 8) | \ + (GIC_HIGHEST_NS_PRIORITY << 16) | \ + (GIC_HIGHEST_NS_PRIORITY << 24)) + +/******************************************************************************* + * Place the cpu interface in a state where it can never make a cpu exit wfi as + * as result of an asserted interrupt. This is critical for powering down a cpu + ******************************************************************************/ +void tegra_gic_cpuif_deactivate(void) +{ + unsigned int val; + + /* Disable secure, non-secure interrupts and disable their bypass */ + val = gicc_read_ctlr(TEGRA_GICC_BASE); + val &= ~(ENABLE_GRP0 | ENABLE_GRP1); + val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; + val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; + gicc_write_ctlr(TEGRA_GICC_BASE, val); +} + +/******************************************************************************* + * Enable secure interrupts and set the priority mask register to allow all + * interrupts to trickle in. + ******************************************************************************/ +static void tegra_gic_cpuif_setup(unsigned int gicc_base) +{ + unsigned int val; + + val = ENABLE_GRP0 | ENABLE_GRP1 | FIQ_EN | FIQ_BYP_DIS_GRP0; + val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; + + gicc_write_ctlr(gicc_base, val); + gicc_write_pmr(gicc_base, GIC_PRI_MASK); +} + +/******************************************************************************* + * Per cpu gic distributor setup which will be done by all cpus after a cold + * boot/hotplug. This marks out the secure interrupts & enables them. + ******************************************************************************/ +static void tegra_gic_pcpu_distif_setup(unsigned int gicd_base) +{ + unsigned int index, sec_ppi_sgi_mask = 0; + + assert(gicd_base); + + /* Setup PPI priorities doing four at a time */ + for (index = 0; index < 32; index += 4) { + gicd_write_ipriorityr(gicd_base, index, + GICD_IPRIORITYR_DEF_VAL); + } + + /* + * Invert the bitmask to create a mask for non-secure PPIs and + * SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will + * update the GICR_IGROUPR0 as well in case we are running on a GICv3 + * system. This is critical if GICD_CTLR.ARE_NS=1. + */ + gicd_write_igroupr(gicd_base, 0, ~sec_ppi_sgi_mask); +} + +/******************************************************************************* + * Global gic distributor setup which will be done by the primary cpu after a + * cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them. + * It then enables the secure GIC distributor interface. + ******************************************************************************/ +static void tegra_gic_distif_setup(unsigned int gicd_base) +{ + unsigned int index, num_ints; + + /* + * Mark out non-secure interrupts. Calculate number of + * IGROUPR registers to consider. Will be equal to the + * number of IT_LINES + */ + num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK; + num_ints = (num_ints + 1) << 5; + for (index = MIN_SPI_ID; index < num_ints; index += 32) + gicd_write_igroupr(gicd_base, index, ~0); + + /* Setup SPI priorities doing four at a time */ + for (index = MIN_SPI_ID; index < num_ints; index += 4) { + gicd_write_ipriorityr(gicd_base, index, + GICD_IPRIORITYR_DEF_VAL); + } + + /* + * Configure the SGI and PPI. This is done in a separated function + * because each CPU is responsible for initializing its own private + * interrupts. + */ + tegra_gic_pcpu_distif_setup(gicd_base); + + /* enable distributor */ + gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1); +} + +void tegra_gic_setup(void) +{ + tegra_gic_cpuif_setup(TEGRA_GICC_BASE); + tegra_gic_distif_setup(TEGRA_GICD_BASE); +} + +/******************************************************************************* + * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. + * The interrupt controller knows which pin/line it uses to signal a type of + * interrupt. This function provides a common implementation of + * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use + * across platforms. It lets the interrupt management framework determine + * for a type of interrupt and security state, which line should be used in the + * SCR_EL3 to control its routing to EL3. The interrupt line is represented as + * the bit position of the IRQ or FIQ bit in the SCR_EL3. + ******************************************************************************/ +uint32_t tegra_gic_interrupt_type_to_line(uint32_t type, + uint32_t security_state) +{ + assert(type == INTR_TYPE_S_EL1 || + type == INTR_TYPE_EL3 || + type == INTR_TYPE_NS); + + assert(sec_state_is_valid(security_state)); + + /* + * We ignore the security state parameter under the assumption that + * both normal and secure worlds are using ARM GICv2. This parameter + * will be used when the secure world starts using GICv3. + */ +#if ARM_GIC_ARCH == 2 + return gicv2_interrupt_type_to_line(TEGRA_GICC_BASE, type); +#else +#error "Invalid ARM GIC architecture version specified for platform port" +#endif /* ARM_GIC_ARCH */ +} + +#if ARM_GIC_ARCH == 2 +/******************************************************************************* + * This function returns the type of the highest priority pending interrupt at + * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no + * interrupt pending. + ******************************************************************************/ +uint32_t tegra_gic_get_pending_interrupt_type(void) +{ + uint32_t id; + + id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK; + + /* Assume that all secure interrupts are S-EL1 interrupts */ + if (id < 1022) + return INTR_TYPE_S_EL1; + + if (id == GIC_SPURIOUS_INTERRUPT) + return INTR_TYPE_INVAL; + + return INTR_TYPE_NS; +} + +/******************************************************************************* + * This function returns the id of the highest priority pending interrupt at + * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no + * interrupt pending. + ******************************************************************************/ +uint32_t tegra_gic_get_pending_interrupt_id(void) +{ + uint32_t id; + + id = gicc_read_hppir(TEGRA_GICC_BASE) & INT_ID_MASK; + + if (id < 1022) + return id; + + if (id == 1023) + return INTR_ID_UNAVAILABLE; + + /* + * Find out which non-secure interrupt it is under the assumption that + * the GICC_CTLR.AckCtl bit is 0. + */ + return gicc_read_ahppir(TEGRA_GICC_BASE) & INT_ID_MASK; +} + +/******************************************************************************* + * This functions reads the GIC cpu interface Interrupt Acknowledge register + * to start handling the pending interrupt. It returns the contents of the IAR. + ******************************************************************************/ +uint32_t tegra_gic_acknowledge_interrupt(void) +{ + return gicc_read_IAR(TEGRA_GICC_BASE); +} + +/******************************************************************************* + * This functions writes the GIC cpu interface End Of Interrupt register with + * the passed value to finish handling the active interrupt + ******************************************************************************/ +void tegra_gic_end_of_interrupt(uint32_t id) +{ + gicc_write_EOIR(TEGRA_GICC_BASE, id); +} + +/******************************************************************************* + * This function returns the type of the interrupt id depending upon the group + * this interrupt has been configured under by the interrupt controller i.e. + * group0 or group1. + ******************************************************************************/ +uint32_t tegra_gic_get_interrupt_type(uint32_t id) +{ + uint32_t group; + + group = gicd_get_igroupr(TEGRA_GICD_BASE, id); + + /* Assume that all secure interrupts are S-EL1 interrupts */ + if (group == GRP0) + return INTR_TYPE_S_EL1; + else + return INTR_TYPE_NS; +} + +#else +#error "Invalid ARM GIC architecture version specified for platform port" +#endif /* ARM_GIC_ARCH */ + +uint32_t plat_ic_get_pending_interrupt_id(void) +{ + return tegra_gic_get_pending_interrupt_id(); +} + +uint32_t plat_ic_get_pending_interrupt_type(void) +{ + return tegra_gic_get_pending_interrupt_type(); +} + +uint32_t plat_ic_acknowledge_interrupt(void) +{ + return tegra_gic_acknowledge_interrupt(); +} + +uint32_t plat_ic_get_interrupt_type(uint32_t id) +{ + return tegra_gic_get_interrupt_type(id); +} + +void plat_ic_end_of_interrupt(uint32_t id) +{ + tegra_gic_end_of_interrupt(id); +} + +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state) +{ + return tegra_gic_interrupt_type_to_line(type, security_state); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_pm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_pm.c new file mode 100644 index 0000000..6fb3e9c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_pm.c @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern uint64_t tegra_bl31_phys_base; +extern uint64_t tegra_sec_entry_point; + +/* + * The following platform setup functions are weakly defined. They + * provide typical implementations that will be overridden by a SoC. + */ +#pragma weak tegra_soc_pwr_domain_suspend +#pragma weak tegra_soc_pwr_domain_on +#pragma weak tegra_soc_pwr_domain_off +#pragma weak tegra_soc_pwr_domain_on_finish +#pragma weak tegra_soc_prepare_system_reset + +int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + return PSCI_E_NOT_SUPPORTED; +} + +int tegra_soc_pwr_domain_on(u_register_t mpidr) +{ + return PSCI_E_SUCCESS; +} + +int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) +{ + return PSCI_E_SUCCESS; +} + +int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + return PSCI_E_SUCCESS; +} + +int tegra_soc_prepare_system_reset(void) +{ + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` + * call to get the `power_state` parameter. This allows the platform to encode + * the appropriate State-ID field within the `power_state` parameter which can + * be utilized in `pwr_domain_suspend()` to suspend to system affinity level. +******************************************************************************/ +void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + /* lower affinities use PLAT_MAX_OFF_STATE */ + for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) + req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; + + /* max affinity uses system suspend state id */ + req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSTATE_ID_SOC_POWERDN; +} + +/******************************************************************************* + * Handler called when an affinity instance is about to enter standby. + ******************************************************************************/ +void tegra_cpu_standby(plat_local_state_t cpu_state) +{ + /* + * Enter standby state + * dsb is good practice before using wfi to enter low power states + */ + dsb(); + wfi(); +} + +/******************************************************************************* + * Handler called when an affinity instance is about to be turned on. The + * level and mpidr determine the affinity instance. + ******************************************************************************/ +int tegra_pwr_domain_on(u_register_t mpidr) +{ + return tegra_soc_pwr_domain_on(mpidr); +} + +/******************************************************************************* + * Handler called when a power domain is about to be turned off. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void tegra_pwr_domain_off(const psci_power_state_t *target_state) +{ + tegra_soc_pwr_domain_off(target_state); +} + +/******************************************************************************* + * Handler called when called when a power domain is about to be suspended. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + tegra_soc_pwr_domain_suspend(target_state); + + /* disable GICC */ + tegra_gic_cpuif_deactivate(); +} + +/******************************************************************************* + * Handler called when a power domain has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. + ******************************************************************************/ +void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + plat_params_from_bl2_t *plat_params; + + /* + * Initialize the GIC cpu and distributor interfaces + */ + tegra_gic_setup(); + + /* + * Check if we are exiting from deep sleep. + */ + if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == + PSTATE_ID_SOC_POWERDN) { + + /* + * Lock scratch registers which hold the CPU vectors. + */ + tegra_pmc_lock_cpu_vectors(); + + /* + * SMMU configuration. + */ + tegra_memctrl_setup(); + + /* + * Security configuration to allow DRAM/device access. + */ + plat_params = bl31_get_plat_params(); + tegra_memctrl_tzdram_setup(tegra_bl31_phys_base, + plat_params->tzdram_size); + } + + /* + * Reset hardware settings. + */ + tegra_soc_pwr_domain_on_finish(target_state); +} + +/******************************************************************************* + * Handler called when a power domain has just been powered on after + * having been suspended earlier. The target_state encodes the low power state + * that each level has woken up from. + ******************************************************************************/ +void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ + tegra_pwr_domain_on_finish(target_state); +} + +/******************************************************************************* + * Handler called when the system wants to be powered off + ******************************************************************************/ +__dead2 void tegra_system_off(void) +{ + ERROR("Tegra System Off: operation not handled.\n"); + panic(); +} + +/******************************************************************************* + * Handler called when the system wants to be restarted. + ******************************************************************************/ +__dead2 void tegra_system_reset(void) +{ + /* per-SoC system reset handler */ + tegra_soc_prepare_system_reset(); + + /* + * Program the PMC in order to restart the system. + */ + tegra_pmc_system_reset(); +} + +/******************************************************************************* + * Handler called to check the validity of the power state parameter. + ******************************************************************************/ +int32_t tegra_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int pwr_lvl = psci_get_pstate_pwrlvl(power_state); + + assert(req_state); + + if (pwr_lvl > PLAT_MAX_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + return tegra_soc_validate_power_state(power_state, req_state); +} + +/******************************************************************************* + * Platform handler called to check the validity of the non secure entrypoint. + ******************************************************************************/ +int tegra_validate_ns_entrypoint(uintptr_t entrypoint) +{ + /* + * Check if the non secure entrypoint lies within the non + * secure DRAM. + */ + if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END)) + return PSCI_E_SUCCESS; + + return PSCI_E_INVALID_ADDRESS; +} + +/******************************************************************************* + * Export the platform handlers to enable psci to invoke them + ******************************************************************************/ +static const plat_psci_ops_t tegra_plat_psci_ops = { + .cpu_standby = tegra_cpu_standby, + .pwr_domain_on = tegra_pwr_domain_on, + .pwr_domain_off = tegra_pwr_domain_off, + .pwr_domain_suspend = tegra_pwr_domain_suspend, + .pwr_domain_on_finish = tegra_pwr_domain_on_finish, + .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish, + .system_off = tegra_system_off, + .system_reset = tegra_system_reset, + .validate_power_state = tegra_validate_power_state, + .validate_ns_entrypoint = tegra_validate_ns_entrypoint, + .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state, +}; + +/******************************************************************************* + * Export the platform specific power ops and initialize Power Controller + ******************************************************************************/ +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } }; + + /* + * Flush entrypoint variable to PoC since it will be + * accessed after a reset with the caches turned off. + */ + tegra_sec_entry_point = sec_entrypoint; + flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t)); + + /* + * Reset hardware settings. + */ + tegra_soc_pwr_domain_on_finish(&target_state); + + /* + * Initialize PSCI ops struct + */ + *psci_ops = &tegra_plat_psci_ops; + + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_sip_calls.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_sip_calls.c new file mode 100644 index 0000000..de36a3c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_sip_calls.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define NS_SWITCH_AARCH32 1 +#define SCR_RW_BITPOS __builtin_ctz(SCR_RW_BIT) + +/******************************************************************************* + * Tegra SiP SMCs + ******************************************************************************/ +#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003 +#define TEGRA_SIP_AARCH_SWITCH 0x82000004 + +/******************************************************************************* + * SPSR settings for AARCH32/AARCH64 modes + ******************************************************************************/ +#define SPSR32 SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, \ + DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT) +#define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS) + +/******************************************************************************* + * This function is responsible for handling all SiP calls from the NS world + ******************************************************************************/ +uint64_t tegra_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + uint32_t ns; + int err; + + /* Determine which security state this SMC originated from */ + ns = is_caller_non_secure(flags); + if (!ns) + SMC_RET1(handle, SMC_UNK); + + switch (smc_fid) { + + case TEGRA_SIP_NEW_VIDEOMEM_REGION: + + /* clean up the high bits */ + x1 = (uint32_t)x1; + x2 = (uint32_t)x2; + + /* + * Check if Video Memory overlaps TZDRAM (contains bl31/bl32) + * or falls outside of the valid DRAM range + */ + err = bl31_check_ns_address(x1, x2); + if (err) + SMC_RET1(handle, err); + + /* + * Check if Video Memory is aligned to 1MB. + */ + if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) { + ERROR("Unaligned Video Memory base address!\n"); + SMC_RET1(handle, -ENOTSUP); + } + + /* new video memory carveout settings */ + tegra_memctrl_videomem_setup(x1, x2); + + SMC_RET1(handle, 0); + break; + + case TEGRA_SIP_AARCH_SWITCH: + + /* clean up the high bits */ + x1 = (uint32_t)x1; + x2 = (uint32_t)x2; + + if (!x1 || x2 > NS_SWITCH_AARCH32) { + ERROR("%s: invalid parameters\n", __func__); + SMC_RET1(handle, SMC_UNK); + } + + /* x1 = ns entry point */ + cm_set_elr_spsr_el3(NON_SECURE, x1, + (x2 == NS_SWITCH_AARCH32) ? SPSR32 : SPSR64); + + /* switch NS world mode */ + cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2); + + INFO("CPU switched to AARCH%s mode\n", + (x2 == NS_SWITCH_AARCH32) ? "32" : "64"); + SMC_RET1(handle, 0); + break; + + default: + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + break; + } + + SMC_RET1(handle, SMC_UNK); +} + +/* Define a runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + tegra_sip_fast, + + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + NULL, + tegra_sip_handler +); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_topology.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_topology.c new file mode 100644 index 0000000..0431d98 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/common/tegra_topology.c @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +extern const unsigned char tegra_power_domain_tree_desc[]; + +/******************************************************************************* + * This function returns the Tegra default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return tegra_power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) + return -1; + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) + return -1; + + /* + * Validate cpu_id by checking whether it represents a CPU in + * one of the two clusters present on the platform. + */ + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) + return -1; + + return (cpu_id + (cluster_id * 4)); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/flowctrl.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/flowctrl.h new file mode 100644 index 0000000..23909e8 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/flowctrl.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FLOWCTRL_H__ +#define __FLOWCTRL_H__ + +#include +#include + +#define FLOWCTRL_HALT_CPU0_EVENTS 0x0 +#define FLOWCTRL_WAITEVENT (2 << 29) +#define FLOWCTRL_WAIT_FOR_INTERRUPT (4 << 29) +#define FLOWCTRL_JTAG_RESUME (1 << 28) +#define FLOWCTRL_HALT_SCLK (1 << 27) +#define FLOWCTRL_HALT_LIC_IRQ (1 << 11) +#define FLOWCTRL_HALT_LIC_FIQ (1 << 10) +#define FLOWCTRL_HALT_GIC_IRQ (1 << 9) +#define FLOWCTRL_HALT_GIC_FIQ (1 << 8) +#define FLOWCTRL_HALT_BPMP_EVENTS 0x4 +#define FLOWCTRL_CPU0_CSR 0x8 +#define FLOW_CTRL_CSR_PWR_OFF_STS (1 << 16) +#define FLOWCTRL_CSR_INTR_FLAG (1 << 15) +#define FLOWCTRL_CSR_EVENT_FLAG (1 << 14) +#define FLOWCTRL_CSR_IMMEDIATE_WAKE (1 << 3) +#define FLOWCTRL_CSR_ENABLE (1 << 0) +#define FLOWCTRL_HALT_CPU1_EVENTS 0x14 +#define FLOWCTRL_CPU1_CSR 0x18 +#define FLOWCTRL_CC4_CORE0_CTRL 0x6c +#define FLOWCTRL_WAIT_WFI_BITMAP 0x100 +#define FLOWCTRL_L2_FLUSH_CONTROL 0x94 +#define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98 +#define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1 << 2) + +#define FLOWCTRL_ENABLE_EXT 12 +#define FLOWCTRL_ENABLE_EXT_MASK 3 +#define FLOWCTRL_PG_CPU_NONCPU 0x1 +#define FLOWCTRL_TURNOFF_CPURAIL 0x2 + +static inline uint32_t tegra_fc_read_32(uint32_t off) +{ + return mmio_read_32(TEGRA_FLOWCTRL_BASE + off); +} + +static inline void tegra_fc_write_32(uint32_t off, uint32_t val) +{ + mmio_write_32(TEGRA_FLOWCTRL_BASE + off, val); +} + +void tegra_fc_cluster_idle(uint32_t midr); +void tegra_fc_cpu_powerdn(uint32_t mpidr); +void tegra_fc_cluster_powerdn(uint32_t midr); +void tegra_fc_soc_powerdn(uint32_t midr); +void tegra_fc_cpu_on(int cpu); +void tegra_fc_cpu_off(int cpu); +void tegra_fc_lock_active_cluster(void); +void tegra_fc_reset_bpmp(void); + +#endif /* __FLOWCTRL_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/memctrl.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/memctrl.h new file mode 100644 index 0000000..26c8057 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/memctrl.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MEMCTRL_H__ +#define __MEMCTRL_H__ + +#include +#include + +/* SMMU registers */ +#define MC_SMMU_CONFIG_0 0x10 +#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0 +#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1 +#define MC_SMMU_TLB_CONFIG_0 0x14 +#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010 +#define MC_SMMU_PTC_CONFIG_0 0x18 +#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f +#define MC_SMMU_TLB_FLUSH_0 0x30 +#define TLB_FLUSH_VA_MATCH_ALL 0 +#define TLB_FLUSH_ASID_MATCH_DISABLE 0 +#define TLB_FLUSH_ASID_MATCH_SHIFT 31 +#define MC_SMMU_TLB_FLUSH_ALL \ + (TLB_FLUSH_VA_MATCH_ALL | \ + (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) +#define MC_SMMU_PTC_FLUSH_0 0x34 +#define MC_SMMU_PTC_FLUSH_ALL 0 +#define MC_SMMU_ASID_SECURITY_0 0x38 +#define MC_SMMU_ASID_SECURITY 0 +#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228 +#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c +#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230 +#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234 +#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 +#define MC_SMMU_TRANSLATION_ENABLE (~0) + +/* TZDRAM carveout configuration registers */ +#define MC_SECURITY_CFG0_0 0x70 +#define MC_SECURITY_CFG1_0 0x74 + +/* Video Memory carveout configuration registers */ +#define MC_VIDEO_PROTECT_BASE 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c + +static inline uint32_t tegra_mc_read_32(uint32_t off) +{ + return mmio_read_32(TEGRA_MC_BASE + off); +} + +static inline void tegra_mc_write_32(uint32_t off, uint32_t val) +{ + mmio_write_32(TEGRA_MC_BASE + off, val); +} + +void tegra_memctrl_setup(void); +void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes); +void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes); + +#endif /* __MEMCTRL_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/pmc.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/pmc.h new file mode 100644 index 0000000..c0616d0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/drivers/pmc.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PMC_H__ +#define __PMC_H__ + +#include +#include + +#define PMC_CONFIG 0x0 +#define PMC_PWRGATE_STATUS 0x38 +#define PMC_PWRGATE_TOGGLE 0x30 +#define PMC_TOGGLE_START 0x100 +#define PMC_SCRATCH39 0x138 +#define PMC_SECURE_DISABLE2 0x2c4 +#define PMC_SECURE_DISABLE2_WRITE22_ON (1 << 28) +#define PMC_SECURE_SCRATCH22 0x338 +#define PMC_SECURE_DISABLE3 0x2d8 +#define PMC_SECURE_DISABLE3_WRITE34_ON (1 << 20) +#define PMC_SECURE_DISABLE3_WRITE35_ON (1 << 22) +#define PMC_SECURE_SCRATCH34 0x368 +#define PMC_SECURE_SCRATCH35 0x36c + +static inline uint32_t tegra_pmc_read_32(uint32_t off) +{ + return mmio_read_32(TEGRA_PMC_BASE + off); +} + +static inline void tegra_pmc_write_32(uint32_t off, uint32_t val) +{ + mmio_write_32(TEGRA_PMC_BASE + off, val); +} + +void tegra_pmc_cpu_setup(uint64_t reset_addr); +void tegra_pmc_lock_cpu_vectors(void); +void tegra_pmc_cpu_on(int cpu); +__dead2 void tegra_pmc_system_reset(void); + +#endif /* __PMC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/plat_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/plat_macros.S new file mode 100644 index 0000000..1afe454 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/plat_macros.S @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_MACROS_S__ +#define __PLAT_MACROS_S__ + +#include +#include + +.section .rodata.gic_reg_name, "aS" +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + +/* --------------------------------------------- + * The below macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL31. + * --------------------------------------------- + */ +.macro plat_crash_print_regs + mov_imm x16, TEGRA_GICC_BASE + cbz x16, 1f + /* gicc base address is now in x16 */ + adr x6, gicc_regs /* Load the gicc reg list to x6 */ + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x16, #GICC_HPPIR] + ldr w9, [x16, #GICC_AHPPIR] + ldr w10, [x16, #GICC_CTLR] + /* Store to the crash buf and print to cosole */ + bl str_in_crash_buf_print + + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +2: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq 1f + bl asm_print_hex + adr x4, spacer + bl asm_print_str + ldr x4, [x7], #8 + bl asm_print_hex + adr x4, newline + bl asm_print_str + b 2b +1: +.endm + +#endif /* __PLAT_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/platform_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/platform_def.h new file mode 100644 index 0000000..70ddaa9 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/platform_def.h @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include +#include +#include + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#if IMAGE_BL31 +#define PLATFORM_STACK_SIZE 0x400 +#endif + +#define TEGRA_PRIMARY_CPU 0x0 + +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ + PLATFORM_MAX_CPUS_PER_CLUSTER) +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ + PLATFORM_CLUSTER_COUNT + 1) + +/******************************************************************************* + * Platform power states + ******************************************************************************/ +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1) + +/******************************************************************************* + * Platform console related constants + ******************************************************************************/ +#define TEGRA_CONSOLE_BAUDRATE 115200 +#define TEGRA_BOOT_UART_CLK_IN_HZ 408000000 + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +/* Size of trusted dram */ +#define TZDRAM_SIZE 0x00400000 +#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +#define BL31_SIZE 0x20000 +#define BL31_BASE TZDRAM_BASE +#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) +#define BL32_BASE (TZDRAM_BASE + BL31_SIZE) +#define BL32_LIMIT TZDRAM_END + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define ADDR_SPACE_SIZE (1ull << 32) +#define MAX_XLAT_TABLES 3 +#define MAX_MMAP_REGIONS 8 + +/******************************************************************************* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/t132/tegra_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/t132/tegra_def.h new file mode 100644 index 0000000..683c903 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/t132/tegra_def.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TEGRA_DEF_H__ +#define __TEGRA_DEF_H__ + +#include + +/******************************************************************************* + * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` + * call as the `state-id` field in the 'power state' parameter. + ******************************************************************************/ +#define PSTATE_ID_SOC_POWERDN 0xD + +/******************************************************************************* + * GIC memory map + ******************************************************************************/ +#define TEGRA_GICD_BASE 0x50041000 +#define TEGRA_GICC_BASE 0x50042000 + +/******************************************************************************* + * Tegra micro-seconds timer constants + ******************************************************************************/ +#define TEGRA_TMRUS_BASE 0x60005010 + +/******************************************************************************* + * Tegra Clock and Reset Controller constants + ******************************************************************************/ +#define TEGRA_CAR_RESET_BASE 0x60006000 + +/******************************************************************************* + * Tegra Flow Controller constants + ******************************************************************************/ +#define TEGRA_FLOWCTRL_BASE 0x60007000 + +/******************************************************************************* + * Tegra Secure Boot Controller constants + ******************************************************************************/ +#define TEGRA_SB_BASE 0x6000C200 + +/******************************************************************************* + * Tegra Exception Vectors constants + ******************************************************************************/ +#define TEGRA_EVP_BASE 0x6000F000 + +/******************************************************************************* + * Tegra Power Mgmt Controller constants + ******************************************************************************/ +#define TEGRA_PMC_BASE 0x7000E400 + +/******************************************************************************* + * Tegra Memory Controller constants + ******************************************************************************/ +#define TEGRA_MC_BASE 0x70019000 + +#endif /* __TEGRA_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/t210/tegra_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/t210/tegra_def.h new file mode 100644 index 0000000..750e6e3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/t210/tegra_def.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TEGRA_DEF_H__ +#define __TEGRA_DEF_H__ + +#include + +/******************************************************************************* + * Power down state IDs + ******************************************************************************/ +#define PSTATE_ID_CORE_POWERDN 7 +#define PSTATE_ID_CLUSTER_IDLE 16 +#define PSTATE_ID_CLUSTER_POWERDN 17 +#define PSTATE_ID_SOC_POWERDN 27 + +/******************************************************************************* + * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND` + * call as the `state-id` field in the 'power state' parameter. + ******************************************************************************/ +#define PLAT_SYS_SUSPEND_STATE_ID PSTATE_ID_SOC_POWERDN + +/******************************************************************************* + * Implementation defined ACTLR_EL3 bit definitions + ******************************************************************************/ +#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) +#define ACTLR_EL3_L2ECTLR_BIT (1 << 5) +#define ACTLR_EL3_L2CTLR_BIT (1 << 4) +#define ACTLR_EL3_CPUECTLR_BIT (1 << 1) +#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) +#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ + ACTLR_EL3_L2ECTLR_BIT | \ + ACTLR_EL3_L2CTLR_BIT | \ + ACTLR_EL3_CPUECTLR_BIT | \ + ACTLR_EL3_CPUACTLR_BIT) + +/******************************************************************************* + * GIC memory map + ******************************************************************************/ +#define TEGRA_GICD_BASE 0x50041000 +#define TEGRA_GICC_BASE 0x50042000 + +/******************************************************************************* + * Tegra Memory Select Switch Controller constants + ******************************************************************************/ +#define TEGRA_MSELECT_BASE 0x50060000 + +#define MSELECT_CONFIG 0x0 +#define ENABLE_WRAP_INCR_MASTER2_BIT (1 << 29) +#define ENABLE_WRAP_INCR_MASTER1_BIT (1 << 28) +#define ENABLE_WRAP_INCR_MASTER0_BIT (1 << 27) +#define UNSUPPORTED_TX_ERR_MASTER2_BIT (1 << 25) +#define UNSUPPORTED_TX_ERR_MASTER1_BIT (1 << 24) +#define ENABLE_UNSUP_TX_ERRORS (UNSUPPORTED_TX_ERR_MASTER2_BIT | \ + UNSUPPORTED_TX_ERR_MASTER1_BIT) +#define ENABLE_WRAP_TO_INCR_BURSTS (ENABLE_WRAP_INCR_MASTER2_BIT | \ + ENABLE_WRAP_INCR_MASTER1_BIT | \ + ENABLE_WRAP_INCR_MASTER0_BIT) + +/******************************************************************************* + * Tegra micro-seconds timer constants + ******************************************************************************/ +#define TEGRA_TMRUS_BASE 0x60005010 + +/******************************************************************************* + * Tegra Clock and Reset Controller constants + ******************************************************************************/ +#define TEGRA_CAR_RESET_BASE 0x60006000 + +/******************************************************************************* + * Tegra Flow Controller constants + ******************************************************************************/ +#define TEGRA_FLOWCTRL_BASE 0x60007000 + +/******************************************************************************* + * Tegra Secure Boot Controller constants + ******************************************************************************/ +#define TEGRA_SB_BASE 0x6000C200 + +/******************************************************************************* + * Tegra Exception Vectors constants + ******************************************************************************/ +#define TEGRA_EVP_BASE 0x6000F000 + +/******************************************************************************* + * Tegra Power Mgmt Controller constants + ******************************************************************************/ +#define TEGRA_PMC_BASE 0x7000E400 + +/******************************************************************************* + * Tegra Memory Controller constants + ******************************************************************************/ +#define TEGRA_MC_BASE 0x70019000 + +#endif /* __TEGRA_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/tegra_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/tegra_private.h new file mode 100644 index 0000000..cf75d9f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/include/tegra_private.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TEGRA_PRIVATE_H__ +#define __TEGRA_PRIVATE_H__ + +#include +#include +#include +#include + +/******************************************************************************* + * Tegra DRAM memory base address + ******************************************************************************/ +#define TEGRA_DRAM_BASE 0x80000000 +#define TEGRA_DRAM_END 0x27FFFFFFF + +typedef struct plat_params_from_bl2 { + uint64_t tzdram_size; +} plat_params_from_bl2_t; + +/* Declarations for plat_psci_handlers.c */ +int32_t tegra_soc_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state); + +/* Declarations for plat_setup.c */ +const mmap_region_t *plat_get_mmio_map(void); + +/* Declarations for plat_secondary.c */ +void plat_secondary_setup(void); +int plat_lock_cpu_vectors(void); + +/* Declarations for tegra_gic.c */ +void tegra_gic_setup(void); +void tegra_gic_cpuif_deactivate(void); + +/* Declarations for tegra_security.c */ +void tegra_security_setup(void); +void tegra_security_setup_videomem(uintptr_t base, uint64_t size); + +/* Declarations for tegra_pm.c */ +void tegra_pm_system_suspend_entry(void); +void tegra_pm_system_suspend_exit(void); +int tegra_system_suspended(void); + +/* Declarations for tegraXXX_pm.c */ +int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); +int tegra_prepare_cpu_on_finish(unsigned long mpidr); + +/* Declarations for tegra_bl31_setup.c */ +plat_params_from_bl2_t *bl31_get_plat_params(void); +int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); + +/* Declarations for tegra_delay_timer.c */ +void tegra_delay_timer_init(void); + +#endif /* __TEGRA_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/platform.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/platform.mk new file mode 100644 index 0000000..cec7caf --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/platform.mk @@ -0,0 +1,40 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +SOC_DIR := plat/nvidia/tegra/soc/${TARGET_SOC} + +# Disable the PSCI platform compatibility layer +ENABLE_PLAT_COMPAT := 0 + +include plat/nvidia/tegra/common/tegra_common.mk +include ${SOC_DIR}/platform_${TARGET_SOC}.mk + +# modify BUILD_PLAT to point to SoC specific build directory +BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${TARGET_SOC}/${BUILD_TYPE} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c new file mode 100644 index 0000000..48a2fba --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Register used to clear CPU reset signals. Each CPU has two reset + * signals: CPU reset (3:0) and Core reset (19:16) + */ +#define CPU_CMPLX_RESET_CLR 0x344 +#define CPU_CORE_RESET_MASK 0x10001 + +/* Clock and Reset controller registers for system clock's settings */ +#define SCLK_RATE 0x30 +#define SCLK_BURST_POLICY 0x28 +#define SCLK_BURST_POLICY_DEFAULT 0x10000000 + +static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; + +int32_t tegra_soc_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int pwr_lvl = psci_get_pstate_pwrlvl(power_state); + int state_id = psci_get_pstate_id(power_state); + int cpu = read_mpidr() & MPIDR_CPU_MASK; + + if (pwr_lvl > PLAT_MAX_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + /* Sanity check the requested afflvl */ + if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { + /* + * It's possible to enter standby only on affinity level 0 i.e. + * a cpu on Tegra. Ignore any other affinity level. + */ + if (pwr_lvl != MPIDR_AFFLVL0) + return PSCI_E_INVALID_PARAMS; + + /* power domain in standby state */ + req_state->pwr_domain_state[pwr_lvl] = PLAT_MAX_RET_STATE; + + return PSCI_E_SUCCESS; + } + + /* + * Sanity check the requested state id, power level and CPU number. + * Currently T132 only supports SYSTEM_SUSPEND on last standing CPU + * i.e. CPU 0 + */ + if ((pwr_lvl != PLAT_MAX_PWR_LVL) || + (state_id != PSTATE_ID_SOC_POWERDN) || + (cpu != 0)) { + ERROR("unsupported state id @ power level\n"); + return PSCI_E_INVALID_PARAMS; + } + + /* Set lower power states to PLAT_MAX_OFF_STATE */ + for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) + req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; + + /* Set the SYSTEM_SUSPEND state-id */ + req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = + PSTATE_ID_SOC_POWERDN; + + return PSCI_E_SUCCESS; +} + +int tegra_soc_pwr_domain_on(u_register_t mpidr) +{ + int cpu = mpidr & MPIDR_CPU_MASK; + uint32_t mask = CPU_CORE_RESET_MASK << cpu; + + if (cpu_powergate_mask[cpu] == 0) { + + /* Deassert CPU reset signals */ + mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); + + /* Power on CPU using PMC */ + tegra_pmc_cpu_on(cpu); + + /* Fill in the CPU powergate mask */ + cpu_powergate_mask[cpu] = 1; + + } else { + /* Power on CPU using Flow Controller */ + tegra_fc_cpu_on(cpu); + } + + return PSCI_E_SUCCESS; +} + +int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) +{ + tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); + return PSCI_E_SUCCESS; +} + +int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) +{ +#if DEBUG + int cpu = read_mpidr() & MPIDR_CPU_MASK; + + /* SYSTEM_SUSPEND only on CPU0 */ + assert(cpu == 0); +#endif + + /* Allow restarting CPU #1 using PMC on suspend exit */ + cpu_powergate_mask[1] = 0; + + /* Program FC to enter suspend state */ + tegra_fc_cpu_powerdn(read_mpidr()); + + /* Suspend DCO operations */ + write_actlr_el1(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]); + + return PSCI_E_SUCCESS; +} + +int tegra_soc_prepare_system_reset(void) +{ + /* + * Set System Clock (SCLK) to POR default so that the clock source + * for the PMC APB clock would not be changed due to system reset. + */ + mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, + SCLK_BURST_POLICY_DEFAULT); + mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); + + /* Wait 1 ms to make sure clock source/device logic is stabilized. */ + mdelay(1); + + return PSCI_E_SUCCESS; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/plat_secondary.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/plat_secondary.c new file mode 100644 index 0000000..744dcb7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/plat_secondary.c @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SB_CSR 0x0 +#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1) + +/* AARCH64 CPU reset vector */ +#define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */ +#define SB_AA64_RESET_HI 0x34 /* width = 11:0 */ + +/* AARCH32 CPU reset vector */ +#define EVP_CPU_RESET_VECTOR 0x100 + +extern void tegra_secure_entrypoint(void); + +/* + * For T132, CPUs reset to AARCH32, so the reset vector is first + * armv8_trampoline which does a warm reset to AARCH64 and starts + * execution at the address in SB_AA64_RESET_LOW/SB_AA64_RESET_HI. + */ +__aligned(8) const uint32_t armv8_trampoline[] = { + 0xE3A00003, /* mov r0, #3 */ + 0xEE0C0F50, /* mcr p15, 0, r0, c12, c0, 2 */ + 0xEAFFFFFE, /* b . */ +}; + +/******************************************************************************* + * Setup secondary CPU vectors + ******************************************************************************/ +void plat_secondary_setup(void) +{ + uint32_t val; + uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint; + + /* + * For T132, CPUs reset to AARCH32, so the reset vector is first + * armv8_trampoline, which does a warm reset to AARCH64 and starts + * execution at the address in SCRATCH34/SCRATCH35. + */ + INFO("Setting up T132 CPU boot\n"); + + /* initial AARCH32 reset address */ + tegra_pmc_write_32(PMC_SECURE_SCRATCH22, + (unsigned long)&armv8_trampoline); + + /* set AARCH32 exception vector (read to flush) */ + mmio_write_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR, + (unsigned long)&armv8_trampoline); + val = mmio_read_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR); + + /* setup secondary CPU vector */ + mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW, + (reset_addr & 0xFFFFFFFF) | 1); + val = reset_addr >> 32; + mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF); + + /* configure PMC */ + tegra_pmc_cpu_setup(reset_addr); + tegra_pmc_lock_cpu_vectors(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/plat_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/plat_setup.c new file mode 100644 index 0000000..0d66413 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/plat_setup.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +/******************************************************************************* + * The Tegra power domain tree has a single system level power domain i.e. a + * single root node. The first entry in the power domain descriptor specifies + * the number of power domains at the highest power level. + ******************************************************************************* + */ +const unsigned char tegra_power_domain_tree_desc[] = { + /* No of root nodes */ + 1, + /* No of clusters */ + PLATFORM_CLUSTER_COUNT, + /* No of CPU cores */ + PLATFORM_CORE_COUNT, +}; + +/* sets of MMIO ranges setup */ +#define MMIO_RANGE_0_ADDR 0x50000000 +#define MMIO_RANGE_1_ADDR 0x60000000 +#define MMIO_RANGE_2_ADDR 0x70000000 +#define MMIO_RANGE_SIZE 0x200000 + +/* + * Table of regions to map using the MMU. + */ +static const mmap_region_t tegra_mmap[] = { + MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + {0} +}; + +/******************************************************************************* + * Set up the pagetables as per the platform memory map & initialize the MMU + ******************************************************************************/ +const mmap_region_t *plat_get_mmio_map(void) +{ + /* MMIO space */ + return tegra_mmap; +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return 12000000; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/platform_t132.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/platform_t132.mk new file mode 100644 index 0000000..69d6296 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t132/platform_t132.mk @@ -0,0 +1,46 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +TEGRA_BOOT_UART_BASE := 0x70006300 +$(eval $(call add_define,TEGRA_BOOT_UART_BASE)) + +TZDRAM_BASE := 0xF5C00000 +$(eval $(call add_define,TZDRAM_BASE)) + +PLATFORM_CLUSTER_COUNT := 1 +$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) + +PLATFORM_MAX_CPUS_PER_CLUSTER := 2 +$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) + +BL31_SOURCES += lib/cpus/aarch64/denver.S \ + ${SOC_DIR}/plat_psci_handlers.c \ + ${SOC_DIR}/plat_setup.c \ + ${SOC_DIR}/plat_secondary.c diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c new file mode 100644 index 0000000..b184063 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/plat_psci_handlers.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * Register used to clear CPU reset signals. Each CPU has two reset + * signals: CPU reset (3:0) and Core reset (19:16). + */ +#define CPU_CMPLX_RESET_CLR 0x454 +#define CPU_CORE_RESET_MASK 0x10001 + +/* Clock and Reset controller registers for system clock's settings */ +#define SCLK_RATE 0x30 +#define SCLK_BURST_POLICY 0x28 +#define SCLK_BURST_POLICY_DEFAULT 0x10000000 + +static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; + +int32_t tegra_soc_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int pwr_lvl = psci_get_pstate_pwrlvl(power_state); + int state_id = psci_get_pstate_id(power_state); + + if (pwr_lvl > PLAT_MAX_PWR_LVL) { + ERROR("%s: unsupported power_state (0x%x)\n", __func__, + power_state); + return PSCI_E_INVALID_PARAMS; + } + + /* Sanity check the requested afflvl */ + if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { + /* + * It's possible to enter standby only on affinity level 0 i.e. + * a cpu on Tegra. Ignore any other affinity level. + */ + if (pwr_lvl != MPIDR_AFFLVL0) + return PSCI_E_INVALID_PARAMS; + + /* power domain in standby state */ + req_state->pwr_domain_state[pwr_lvl] = PLAT_MAX_RET_STATE; + + return PSCI_E_SUCCESS; + } + + /* Sanity check the requested state id */ + switch (state_id) { + case PSTATE_ID_CORE_POWERDN: + /* + * Core powerdown request only for afflvl 0 + */ + if (pwr_lvl != MPIDR_AFFLVL0) + goto error; + + req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; + + break; + + case PSTATE_ID_CLUSTER_IDLE: + case PSTATE_ID_CLUSTER_POWERDN: + /* + * Cluster powerdown/idle request only for afflvl 1 + */ + if (pwr_lvl != MPIDR_AFFLVL1) + goto error; + + req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; + req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; + + break; + + case PSTATE_ID_SOC_POWERDN: + /* + * System powerdown request only for afflvl 2 + */ + if (pwr_lvl != PLAT_MAX_PWR_LVL) + goto error; + + for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) + req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; + + req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = + PLAT_SYS_SUSPEND_STATE_ID; + + break; + + default: + ERROR("%s: unsupported state id (%d)\n", __func__, state_id); + return PSCI_E_INVALID_PARAMS; + } + + return PSCI_E_SUCCESS; + +error: + ERROR("%s: unsupported state id (%d)\n", __func__, state_id); + return PSCI_E_INVALID_PARAMS; +} + +int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + u_register_t mpidr = read_mpidr(); + const plat_local_state_t *pwr_domain_state = + target_state->pwr_domain_state; + unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; + unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; + unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; + + if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { + + assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE); + assert(stateid_afflvl1 == PLAT_MAX_OFF_STATE); + + /* suspend the entire soc */ + tegra_fc_soc_powerdn(mpidr); + + } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { + + assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE); + + /* Prepare for cluster idle */ + tegra_fc_cluster_idle(mpidr); + + } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) { + + assert(stateid_afflvl0 == PLAT_MAX_OFF_STATE); + + /* Prepare for cluster powerdn */ + tegra_fc_cluster_powerdn(mpidr); + + } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { + + /* Prepare for cpu powerdn */ + tegra_fc_cpu_powerdn(mpidr); + + } else { + ERROR("%s: Unknown state id\n", __func__); + return PSCI_E_NOT_SUPPORTED; + } + + return PSCI_E_SUCCESS; +} + +int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + uint32_t val; + + /* + * Check if we are exiting from SOC_POWERDN. + */ + if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == + PLAT_SYS_SUSPEND_STATE_ID) { + + /* + * Enable WRAP to INCR burst type conversions for + * incoming requests on the AXI slave ports. + */ + val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); + val &= ~ENABLE_UNSUP_TX_ERRORS; + val |= ENABLE_WRAP_TO_INCR_BURSTS; + mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); + + /* + * Restore Boot and Power Management Processor (BPMP) reset + * address and reset it. + */ + tegra_fc_reset_bpmp(); + } + + /* + * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's + * used for power management and boot purposes. Inform the BPMP that + * we have completed the cluster power up. + */ + tegra_fc_lock_active_cluster(); + + return PSCI_E_SUCCESS; +} + +int tegra_soc_pwr_domain_on(u_register_t mpidr) +{ + int cpu = mpidr & MPIDR_CPU_MASK; + uint32_t mask = CPU_CORE_RESET_MASK << cpu; + + /* Deassert CPU reset signals */ + mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); + + /* Turn on CPU using flow controller or PMC */ + if (cpu_powergate_mask[cpu] == 0) { + tegra_pmc_cpu_on(cpu); + cpu_powergate_mask[cpu] = 1; + } else { + tegra_fc_cpu_on(cpu); + } + + return PSCI_E_SUCCESS; +} + +int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) +{ + tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); + return PSCI_E_SUCCESS; +} + +int tegra_soc_prepare_system_reset(void) +{ + /* + * Set System Clock (SCLK) to POR default so that the clock source + * for the PMC APB clock would not be changed due to system reset. + */ + mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, + SCLK_BURST_POLICY_DEFAULT); + mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); + + /* Wait 1 ms to make sure clock source/device logic is stabilized. */ + mdelay(1); + + return PSCI_E_SUCCESS; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/plat_secondary.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/plat_secondary.c new file mode 100644 index 0000000..b07f446 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/plat_secondary.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#define SB_CSR 0x0 +#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1) + +/* CPU reset vector */ +#define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */ +#define SB_AA64_RESET_HI 0x34 /* width = 11:0 */ + +extern void tegra_secure_entrypoint(void); + +/******************************************************************************* + * Setup secondary CPU vectors + ******************************************************************************/ +void plat_secondary_setup(void) +{ + uint32_t val; + uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint; + + INFO("Setting up secondary CPU boot\n"); + + /* setup secondary CPU vector */ + mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW, + (reset_addr & 0xFFFFFFFF) | 1); + val = reset_addr >> 32; + mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF); + + /* configure PMC */ + tegra_pmc_cpu_setup(reset_addr); + tegra_pmc_lock_cpu_vectors(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/plat_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/plat_setup.c new file mode 100644 index 0000000..70a55c6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/plat_setup.c @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +/******************************************************************************* + * The Tegra power domain tree has a single system level power domain i.e. a + * single root node. The first entry in the power domain descriptor specifies + * the number of power domains at the highest power level. + ******************************************************************************* + */ +const unsigned char tegra_power_domain_tree_desc[] = { + /* No of root nodes */ + 1, + /* No of clusters */ + PLATFORM_CLUSTER_COUNT, + /* No of CPU cores - cluster0 */ + PLATFORM_MAX_CPUS_PER_CLUSTER, + /* No of CPU cores - cluster1 */ + PLATFORM_MAX_CPUS_PER_CLUSTER +}; + +/* sets of MMIO ranges setup */ +#define MMIO_RANGE_0_ADDR 0x50000000 +#define MMIO_RANGE_1_ADDR 0x60000000 +#define MMIO_RANGE_2_ADDR 0x70000000 +#define MMIO_RANGE_SIZE 0x200000 + +/* + * Table of regions to map using the MMU. + */ +static const mmap_region_t tegra_mmap[] = { + MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + {0} +}; + +/******************************************************************************* + * Set up the pagetables as per the platform memory map & initialize the MMU + ******************************************************************************/ +const mmap_region_t *plat_get_mmio_map(void) +{ + /* MMIO space */ + return tegra_mmap; +} + +/******************************************************************************* + * Handler to get the System Counter Frequency + ******************************************************************************/ +unsigned int plat_get_syscnt_freq2(void) +{ + return 19200000; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/platform_t210.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/platform_t210.mk new file mode 100644 index 0000000..5001629 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/nvidia/tegra/soc/t210/platform_t210.mk @@ -0,0 +1,63 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +TEGRA_BOOT_UART_BASE := 0x70006000 +$(eval $(call add_define,TEGRA_BOOT_UART_BASE)) + +TZDRAM_BASE := 0xFDC00000 +$(eval $(call add_define,TZDRAM_BASE)) + +ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1 +$(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT)) + +ENABLE_NS_L2_CPUECTRL_RW_ACCESS := 1 +$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS)) + +ENABLE_L2_DYNAMIC_RETENTION := 1 +$(eval $(call add_define,ENABLE_L2_DYNAMIC_RETENTION)) + +ENABLE_CPU_DYNAMIC_RETENTION := 1 +$(eval $(call add_define,ENABLE_CPU_DYNAMIC_RETENTION)) + +PLATFORM_CLUSTER_COUNT := 2 +$(eval $(call add_define,PLATFORM_CLUSTER_COUNT)) + +PLATFORM_MAX_CPUS_PER_CLUSTER := 4 +$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) + +BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + ${SOC_DIR}/plat_psci_handlers.c \ + ${SOC_DIR}/plat_setup.c \ + ${SOC_DIR}/plat_secondary.c + +# Enable workarounds for selected Cortex-A53 erratas. +ERRATA_A53_826319 := 1 + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/aarch64/plat_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/aarch64/plat_helpers.S new file mode 100644 index 0000000..31d2c68 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/aarch64/plat_helpers.S @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + .globl plat_my_core_pos + .globl plat_get_my_entrypoint + .globl platform_mem_init + .globl plat_qemu_calc_core_pos + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_secondary_cold_boot_setup + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + + +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_qemu_calc_core_pos +endfunc plat_my_core_pos + +/* + * unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); + * With this function: CorePos = (ClusterId * 4) + CoreId + */ +func plat_qemu_calc_core_pos + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc plat_qemu_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #QEMU_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* Calculate address of our hold entry */ + bl plat_my_core_pos + mov_imm x2, PLAT_QEMU_HOLD_BASE + + /* Wait until we have a go */ +poll_mailbox: + ldr x1, [x2, x0] + cbz x1, 1f + mov_imm x0, PLAT_QEMU_TRUSTED_MAILBOX_BASE + ldr x1, [x0] + br x1 +1: + wfe + b poll_mailbox +endfunc plat_secondary_cold_boot_setup + +func plat_get_my_entrypoint + /* TODO support warm boot */ + mov x0, #0 + ret +endfunc plat_get_my_entrypoint + +func platform_mem_init + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0, x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, PLAT_QEMU_CRASH_UART_BASE + mov_imm x1, PLAT_QEMU_CRASH_UART_CLK_IN_HZ + mov_imm x2, PLAT_QEMU_CONSOLE_BAUDRATE + b console_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, PLAT_QEMU_CRASH_UART_BASE + b console_core_putc +endfunc plat_crash_console_putc + + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/dt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/dt.c new file mode 100644 index 0000000..647ee01 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/dt.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include "qemu_private.h" +#include + +static int append_psci_compatible(void *fdt, int offs, const char *str) +{ + return fdt_appendprop(fdt, offs, "compatible", str, strlen(str) + 1); +} + +int dt_add_psci_node(void *fdt) +{ + int offs; + + if (fdt_path_offset(fdt, "/psci") >= 0) { + WARN("PSCI Device Tree node already exists!\n"); + return 0; + } + + offs = fdt_path_offset(fdt, "/"); + if (offs < 0) + return -1; + offs = fdt_add_subnode(fdt, offs, "psci"); + if (offs < 0) + return -1; + if (append_psci_compatible(fdt, offs, "arm,psci-1.0")) + return -1; + if (append_psci_compatible(fdt, offs, "arm,psci-0.2")) + return -1; + if (append_psci_compatible(fdt, offs, "arm,psci")) + return -1; + if (fdt_setprop_string(fdt, offs, "method", "smc")) + return -1; + if (fdt_setprop_u32(fdt, offs, "cpu_suspend", PSCI_CPU_SUSPEND_AARCH64)) + return -1; + if (fdt_setprop_u32(fdt, offs, "cpu_off", PSCI_CPU_OFF)) + return -1; + if (fdt_setprop_u32(fdt, offs, "cpu_on", PSCI_CPU_ON_AARCH64)) + return -1; + if (fdt_setprop_u32(fdt, offs, "sys_poweroff", PSCI_SYSTEM_OFF)) + return -1; + if (fdt_setprop_u32(fdt, offs, "sys_reset", PSCI_SYSTEM_RESET)) + return -1; + return 0; +} + +static int check_node_compat_prefix(void *fdt, int offs, const char *prefix) +{ + const size_t prefix_len = strlen(prefix); + size_t l; + int plen; + const char *prop; + + prop = fdt_getprop(fdt, offs, "compatible", &plen); + if (!prop) + return -1; + + while (plen > 0) { + if (memcmp(prop, prefix, prefix_len) == 0) + return 0; /* match */ + + l = strlen(prop) + 1; + prop += l; + plen -= l; + } + + return -1; +} + +int dt_add_psci_cpu_enable_methods(void *fdt) +{ + int offs = 0; + + while (1) { + offs = fdt_next_node(fdt, offs, NULL); + if (offs < 0) + break; + if (fdt_getprop(fdt, offs, "enable-method", NULL)) + continue; /* already set */ + if (check_node_compat_prefix(fdt, offs, "arm,cortex-a")) + continue; /* no compatible */ + if (fdt_setprop_string(fdt, offs, "enable-method", "psci")) + return -1; + /* Need to restart scanning as offsets may have changed */ + offs = 0; + } + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/include/plat_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/include/plat_macros.S new file mode 100644 index 0000000..648d8ec --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/include/plat_macros.S @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __PLAT_MACROS_S__ +#define __PLAT_MACROS_S__ + +#include +#include + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + mov_imm x17, GICC_BASE + mov_imm x16, GICD_BASE + arm_print_gic_regs + .endm + +#endif /* __PLAT_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/include/platform_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/include/platform_def.h new file mode 100644 index 0000000..d983ce6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/include/platform_def.h @@ -0,0 +1,244 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include +#include +#include + +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define QEMU_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + +#define PLATFORM_STACK_SIZE 0x1000 + +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_CLUSTER_COUNT 2 +#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CLUSTER1_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ + PLATFORM_CLUSTER1_CORE_COUNT) + +#define QEMU_PRIMARY_CPU 0 + +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 + +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE 2 + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN 0 +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET 1 +/* + * Local power state for OFF/power-down. Valid for CPU and cluster power + * domains. + */ +#define PLAT_LOCAL_STATE_OFF 2 + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH 4 +#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +/* + * Partition memory into secure ROM, non-secure DRAM, secure "SRAM", + * and secure DRAM. + */ +#define SEC_ROM_BASE 0x00000000 +#define SEC_ROM_SIZE 0x00020000 + +#define NS_DRAM0_BASE 0x40000000 +#define NS_DRAM0_SIZE 0x3de00000 + +#define SEC_SRAM_BASE 0x0e000000 +#define SEC_SRAM_SIZE 0x00040000 + +#define SEC_DRAM_BASE 0x0e100000 +#define SEC_DRAM_SIZE 0x00f00000 + +/* + * ARM-TF lives in SRAM, partition it here + */ + +#define SHARED_RAM_BASE SEC_SRAM_BASE +#define SHARED_RAM_SIZE 0x00001000 + +#define PLAT_QEMU_TRUSTED_MAILBOX_BASE SHARED_RAM_BASE +#define PLAT_QEMU_TRUSTED_MAILBOX_SIZE (8 + PLAT_QEMU_HOLD_SIZE) +#define PLAT_QEMU_HOLD_BASE (PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8) +#define PLAT_QEMU_HOLD_SIZE (PLATFORM_CORE_COUNT * \ + PLAT_QEMU_HOLD_ENTRY_SIZE) +#define PLAT_QEMU_HOLD_ENTRY_SIZE 8 +#define PLAT_QEMU_HOLD_STATE_WAIT 0 +#define PLAT_QEMU_HOLD_STATE_GO 1 + +#define BL_RAM_BASE (SHARED_RAM_BASE + SHARED_RAM_SIZE) +#define BL_RAM_SIZE (SEC_SRAM_SIZE - SHARED_RAM_SIZE) + +/* + * BL1 specific defines. + * + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + * Put BL1 RW at the top of the Secure SRAM. BL1_RW_BASE is calculated using + * the current BL1 RW debug size plus a little space for growth. + */ +#define BL1_RO_BASE SEC_ROM_BASE +#define BL1_RO_LIMIT (SEC_ROM_BASE + SEC_ROM_SIZE) +#define BL1_RW_BASE (BL1_RW_LIMIT - 0x12000) +#define BL1_RW_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) + +/* + * BL2 specific defines. + * + * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug + * size plus a little space for growth. + */ +#define BL2_BASE (BL31_BASE - 0x1D000) +#define BL2_LIMIT BL31_BASE + +/* + * BL3-1 specific defines. + * + * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the + * current BL3-1 debug size plus a little space for growth. + */ +#define BL31_BASE (BL31_LIMIT - 0x20000) +#define BL31_LIMIT (BL_RAM_BASE + BL_RAM_SIZE) +#define BL31_PROGBITS_LIMIT BL1_RW_BASE + + +/* + * BL3-2 specific defines. + * + * BL3-2 can execute from Secure SRAM, or Secure DRAM. + */ +#define BL32_SRAM_BASE BL_RAM_BASE +#define BL32_SRAM_LIMIT BL31_BASE +#define BL32_DRAM_BASE SEC_DRAM_BASE +#define BL32_DRAM_LIMIT (SEC_DRAM_BASE + SEC_DRAM_SIZE) + +#define SEC_SRAM_ID 0 +#define SEC_DRAM_ID 1 + +#if BL32_RAM_LOCATION_ID == SEC_SRAM_ID +# define BL32_MEM_BASE BL_RAM_BASE +# define BL32_MEM_SIZE BL_RAM_SIZE +# define BL32_BASE BL32_SRAM_BASE +# define BL32_LIMIT BL32_SRAM_LIMIT +#elif BL32_RAM_LOCATION_ID == SEC_DRAM_ID +# define BL32_MEM_BASE SEC_DRAM_BASE +# define BL32_MEM_SIZE SEC_DRAM_SIZE +# define BL32_BASE BL32_DRAM_BASE +# define BL32_LIMIT BL32_DRAM_LIMIT +#else +# error "Unsupported BL32_RAM_LOCATION_ID value" +#endif +#define BL32_SIZE (BL32_LIMIT - BL32_BASE) + +#define NS_IMAGE_OFFSET 0x60000000 + +#define ADDR_SPACE_SIZE (1ull << 32) +#define MAX_MMAP_REGIONS 8 +#define MAX_XLAT_TABLES 6 +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +/* + * PL011 related constants + */ +#define UART0_BASE 0x09000000 +#define UART1_BASE 0x09040000 +#define UART0_CLK_IN_HZ 1 +#define UART1_CLK_IN_HZ 1 + +#define PLAT_QEMU_BOOT_UART_BASE UART0_BASE +#define PLAT_QEMU_BOOT_UART_CLK_IN_HZ UART0_CLK_IN_HZ + +#define PLAT_QEMU_CRASH_UART_BASE UART1_BASE +#define PLAT_QEMU_CRASH_UART_CLK_IN_HZ UART1_CLK_IN_HZ + +#define PLAT_QEMU_CONSOLE_BAUDRATE 115200 + +#define QEMU_FLASH0_BASE 0x04000000 +#define QEMU_FLASH0_SIZE 0x04000000 + +#define PLAT_QEMU_FIP_BASE QEMU_FLASH0_BASE +#define PLAT_QEMU_FIP_MAX_SIZE QEMU_FLASH0_SIZE + +#define DEVICE0_BASE 0x08000000 +#define DEVICE0_SIZE 0x00021000 +#define DEVICE1_BASE 0x09000000 +#define DEVICE1_SIZE 0x00011000 + +/* + * GIC related constants + */ + +#define GICD_BASE 0x8000000 +#define GICC_BASE 0x8010000 +#define GICR_BASE 0 + + +#define QEMU_IRQ_SEC_SGI_0 8 +#define QEMU_IRQ_SEC_SGI_1 9 +#define QEMU_IRQ_SEC_SGI_2 10 +#define QEMU_IRQ_SEC_SGI_3 11 +#define QEMU_IRQ_SEC_SGI_4 12 +#define QEMU_IRQ_SEC_SGI_5 13 +#define QEMU_IRQ_SEC_SGI_6 14 +#define QEMU_IRQ_SEC_SGI_7 15 + +/* + * DT related constants + */ +#define PLAT_QEMU_DT_BASE NS_DRAM0_BASE +#define PLAT_QEMU_DT_MAX_SIZE 0x10000 + +/* + * System counter + */ +#define SYS_COUNTER_FREQ_IN_TICKS ((1000 * 1000 * 1000) / 16) + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/platform.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/platform.mk new file mode 100644 index 0000000..aa08bd3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/platform.mk @@ -0,0 +1,99 @@ +# +# Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +include lib/libfdt/libfdt.mk + +PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ + -Iinclude/plat/arm/common/aarch64/ \ + -Iplat/qemu/include \ + -Iinclude/common/tbbr + + +PLAT_BL_COMMON_SOURCES := plat/qemu/qemu_common.c \ + drivers/arm/pl011/aarch64/pl011_console.S \ + lib/xlat_tables/xlat_tables_common.c \ + lib/xlat_tables/aarch64/xlat_tables.c + +BL1_SOURCES += drivers/io/io_semihosting.c \ + drivers/io/io_storage.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + lib/semihosting/semihosting.c \ + lib/semihosting/aarch64/semihosting_call.S \ + plat/qemu/qemu_io_storage.c \ + lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + plat/common/aarch64/platform_mp_stack.S \ + plat/qemu/aarch64/plat_helpers.S \ + plat/qemu/qemu_bl1_setup.c + +BL2_SOURCES += drivers/io/io_semihosting.c \ + drivers/io/io_storage.c \ + drivers/io/io_fip.c \ + drivers/io/io_memmap.c \ + plat/common/aarch64/platform_mp_stack.S \ + lib/semihosting/semihosting.c \ + lib/semihosting/aarch64/semihosting_call.S\ + plat/qemu/qemu_io_storage.c \ + plat/qemu/aarch64/plat_helpers.S \ + plat/qemu/qemu_bl2_setup.c \ + plat/qemu/dt.c \ + $(LIBFDT_SRCS) + +BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + drivers/arm/gic/v2/gicv2_helpers.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/common/gic_common.c \ + plat/common/aarch64/platform_mp_stack.S \ + plat/common/aarch64/plat_psci_common.c \ + plat/common/aarch64/plat_common.c \ + plat/qemu/qemu_pm.c \ + plat/qemu/topology.c \ + plat/qemu/aarch64/plat_helpers.S \ + plat/qemu/qemu_bl31_setup.c \ + plat/qemu/qemu_gic.c + +# Disable the PSCI platform compatibility layer +ENABLE_PLAT_COMPAT := 0 + +BL32_RAM_LOCATION := tdram +ifeq (${BL32_RAM_LOCATION}, tsram) + BL32_RAM_LOCATION_ID = SEC_SRAM_ID +else ifeq (${BL32_RAM_LOCATION}, tdram) + BL32_RAM_LOCATION_ID = SEC_DRAM_ID +else + $(error "Unsupported BL32_RAM_LOCATION value") +endif + +# Process flags +$(eval $(call add_define,BL32_RAM_LOCATION_ID)) diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_bl1_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_bl1_setup.c new file mode 100644 index 0000000..4438aac --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_bl1_setup.c @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "qemu_private.h" + + +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ +#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) + + +/******************************************************************************* + * Declarations of linker defined symbols which will tell us where BL1 lives + * in Trusted RAM + ******************************************************************************/ +extern uint64_t __BL1_RAM_START__; +extern uint64_t __BL1_RAM_END__; +#define BL1_RAM_BASE (uint64_t)(&__BL1_RAM_START__) +#define BL1_RAM_LIMIT (uint64_t)(&__BL1_RAM_END__) + +/* Data structure which holds the extents of the trusted SRAM for BL1*/ +static meminfo_t bl1_tzram_layout; + + +meminfo_t *bl1_plat_sec_mem_layout(void) +{ + return &bl1_tzram_layout; +} + +/******************************************************************************* + * Perform any BL1 specific platform actions. + ******************************************************************************/ +void bl1_early_platform_setup(void) +{ + const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; + + /* Initialize the console to provide early debug support */ + console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ, + PLAT_QEMU_CONSOLE_BAUDRATE); + + /* Allow BL1 to see the whole Trusted RAM */ + bl1_tzram_layout.total_base = BL_RAM_BASE; + bl1_tzram_layout.total_size = BL_RAM_SIZE; + + /* Calculate how much RAM BL1 is using and how much remains free */ + bl1_tzram_layout.free_base = BL_RAM_BASE; + bl1_tzram_layout.free_size = BL_RAM_SIZE; + reserve_mem(&bl1_tzram_layout.free_base, &bl1_tzram_layout.free_size, + BL1_RAM_BASE, bl1_size); +} + +/****************************************************************************** + * Perform the very early platform specific architecture setup. This only + * does basic initialization. Later architectural setup (bl1_arch_setup()) + * does not do anything platform specific. + *****************************************************************************/ +void bl1_plat_arch_setup(void) +{ + qemu_configure_mmu_el3(bl1_tzram_layout.total_base, + bl1_tzram_layout.total_size, + BL1_RO_BASE, BL1_RO_LIMIT, + BL1_COHERENT_RAM_BASE, BL1_COHERENT_RAM_LIMIT); +} + +void bl1_platform_setup(void) +{ + plat_qemu_io_setup(); +} + +/******************************************************************************* + * Function that takes a memory layout into which BL2 has been loaded and + * populates a new memory layout for BL2 that ensures that BL1's data sections + * resident in secure RAM are not visible to BL2. + ******************************************************************************/ +void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, + meminfo_t *bl2_mem_layout) +{ + const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; + + assert(bl1_mem_layout != NULL); + assert(bl2_mem_layout != NULL); + + /* Check that BL1's memory is lying outside of the free memory */ + assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) || + (BL1_RAM_BASE >= (bl1_mem_layout->free_base + + bl1_mem_layout->free_size))); + + /* Remove BL1 RW data from the scope of memory visible to BL2 */ + *bl2_mem_layout = *bl1_mem_layout; + reserve_mem(&bl2_mem_layout->total_base, + &bl2_mem_layout->total_size, + BL1_RAM_BASE, + bl1_size); + + flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); +} + +/******************************************************************************* + * Before calling this function BL2 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL2 and set SPSR and security state. + * On ARM standard platforms we only set the security state of the entrypoint + ******************************************************************************/ +void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image, + entry_point_info_t *bl2_ep) +{ + SET_SECURITY_STATE(bl2_ep->h.attr, SECURE); + bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_bl2_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_bl2_setup.c new file mode 100644 index 0000000..24da2b6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_bl2_setup.c @@ -0,0 +1,327 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include "qemu_private.h" +#include + + +/* + * The next 2 constants identify the extents of the code & RO data region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. + */ +#define BL2_RO_BASE (unsigned long)(&__RO_START__) +#define BL2_RO_LIMIT (unsigned long)(&__RO_END__) + +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ +#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) + +/******************************************************************************* + * This structure represents the superset of information that is passed to + * BL3-1, e.g. while passing control to it from BL2, bl31_params + * and other platform specific params + ******************************************************************************/ +typedef struct bl2_to_bl31_params_mem { + bl31_params_t bl31_params; + image_info_t bl31_image_info; + image_info_t bl32_image_info; + image_info_t bl33_image_info; + entry_point_info_t bl33_ep_info; + entry_point_info_t bl32_ep_info; + entry_point_info_t bl31_ep_info; +} bl2_to_bl31_params_mem_t; + + +static bl2_to_bl31_params_mem_t bl31_params_mem; + + + +/* Data structure which holds the extents of the trusted SRAM for BL2 */ +static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); + +meminfo_t *bl2_plat_sec_mem_layout(void) +{ + return &bl2_tzram_layout; +} + +/******************************************************************************* + * This function assigns a pointer to the memory that the platform has kept + * aside to pass platform specific and trusted firmware related information + * to BL31. This memory is allocated by allocating memory to + * bl2_to_bl31_params_mem_t structure which is a superset of all the + * structure whose information is passed to BL31 + * NOTE: This function should be called only once and should be done + * before generating params to BL31 + ******************************************************************************/ +bl31_params_t *bl2_plat_get_bl31_params(void) +{ + bl31_params_t *bl2_to_bl31_params; + + /* + * Initialise the memory for all the arguments that needs to + * be passed to BL3-1 + */ + memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); + + /* Assign memory for TF related information */ + bl2_to_bl31_params = &bl31_params_mem.bl31_params; + SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); + + /* Fill BL3-1 related information */ + bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, + VERSION_1, 0); + + /* Fill BL3-2 related information */ + bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, + VERSION_1, 0); + bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, + VERSION_1, 0); + + /* Fill BL3-3 related information */ + bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, + PARAM_EP, VERSION_1, 0); + + /* BL3-3 expects to receive the primary CPU MPID (through x0) */ + bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); + + bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, + VERSION_1, 0); + + return bl2_to_bl31_params; +} + +/* Flush the TF params and the TF plat params */ +void bl2_plat_flush_bl31_params(void) +{ + flush_dcache_range((unsigned long)&bl31_params_mem, + sizeof(bl2_to_bl31_params_mem_t)); +} + +/******************************************************************************* + * This function returns a pointer to the shared memory that the platform + * has kept to point to entry point information of BL31 to BL2 + ******************************************************************************/ +struct entry_point_info *bl2_plat_get_bl31_ep_info(void) +{ +#if DEBUG + bl31_params_mem.bl31_ep_info.args.arg1 = QEMU_BL31_PLAT_PARAM_VAL; +#endif + + return &bl31_params_mem.bl31_ep_info; +} + + + +void bl2_early_platform_setup(meminfo_t *mem_layout) +{ + /* Initialize the console to provide early debug support */ + console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ, + PLAT_QEMU_CONSOLE_BAUDRATE); + + /* Setup the BL2 memory layout */ + bl2_tzram_layout = *mem_layout; + + plat_qemu_io_setup(); +} + +static void security_setup(void) +{ + /* + * This is where a TrustZone address space controller and other + * security related peripherals, would be configured. + */ +} + +static void update_dt(void) +{ + int ret; + void *fdt = (void *)(uintptr_t)PLAT_QEMU_DT_BASE; + + ret = fdt_open_into(fdt, fdt, PLAT_QEMU_DT_MAX_SIZE); + if (ret < 0) { + ERROR("Invalid Device Tree at %p: error %d\n", fdt, ret); + return; + } + + if (dt_add_psci_node(fdt)) { + ERROR("Failed to add PSCI Device Tree node\n"); + return; + } + + if (dt_add_psci_cpu_enable_methods(fdt)) { + ERROR("Failed to add PSCI cpu enable methods in Device Tree\n"); + return; + } + + ret = fdt_pack(fdt); + if (ret < 0) + ERROR("Failed to pack Device Tree at %p: error %d\n", fdt, ret); +} + +void bl2_platform_setup(void) +{ + security_setup(); + update_dt(); + + /* TODO Initialize timer */ +} + +void bl2_plat_arch_setup(void) +{ + qemu_configure_mmu_el1(bl2_tzram_layout.total_base, + bl2_tzram_layout.total_size, + BL2_RO_BASE, BL2_RO_LIMIT, + BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT); +} + +/******************************************************************************* + * Gets SPSR for BL32 entry + ******************************************************************************/ +static uint32_t qemu_get_spsr_for_bl32_entry(void) +{ + /* + * The Secure Payload Dispatcher service is responsible for + * setting the SPSR prior to entry into the BL3-2 image. + */ + return 0; +} + +/******************************************************************************* + * Gets SPSR for BL33 entry + ******************************************************************************/ +static uint32_t qemu_get_spsr_for_bl33_entry(void) +{ + unsigned long el_status; + unsigned int mode; + uint32_t spsr; + + /* Figure out what mode we enter the non-secure world in */ + el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; + el_status &= ID_AA64PFR0_ELX_MASK; + + mode = (el_status) ? MODE_EL2 : MODE_EL1; + + /* + * TODO: Consider the possibility of specifying the SPSR in + * the FIP ToC and allowing the platform to have a say as + * well. + */ + spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + return spsr; +} + +/******************************************************************************* + * Before calling this function BL3-1 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL3-1 and set SPSR and security state. + * On ARM standard platforms we only set the security state of the entrypoint + ******************************************************************************/ +void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, + entry_point_info_t *bl31_ep_info) +{ + SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); + bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); +} + +/******************************************************************************* + * Before calling this function BL3-2 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL3-2 and set SPSR and security state. + * On ARM standard platforms we only set the security state of the entrypoint + ******************************************************************************/ +void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, + entry_point_info_t *bl32_ep_info) +{ + SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); + bl32_ep_info->spsr = qemu_get_spsr_for_bl32_entry(); +} + +/******************************************************************************* + * Before calling this function BL3-3 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL3-3 and set SPSR and security state. + * On ARM standard platforms we only set the security state of the entrypoint + ******************************************************************************/ +void bl2_plat_set_bl33_ep_info(image_info_t *image, + entry_point_info_t *bl33_ep_info) +{ + + SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); + bl33_ep_info->spsr = qemu_get_spsr_for_bl33_entry(); +} + +/******************************************************************************* + * Populate the extents of memory available for loading BL32 + ******************************************************************************/ +void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) +{ + /* + * Populate the extents of memory available for loading BL32. + */ + bl32_meminfo->total_base = BL32_BASE; + bl32_meminfo->free_base = BL32_BASE; + bl32_meminfo->total_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE; + bl32_meminfo->free_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE; +} + +/******************************************************************************* + * Populate the extents of memory available for loading BL33 + ******************************************************************************/ +void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) +{ + bl33_meminfo->total_base = NS_DRAM0_BASE; + bl33_meminfo->total_size = NS_DRAM0_SIZE; + bl33_meminfo->free_base = NS_DRAM0_BASE; + bl33_meminfo->free_size = NS_DRAM0_SIZE; +} + +unsigned long plat_get_ns_image_entrypoint(void) +{ + return NS_IMAGE_OFFSET; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_bl31_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_bl31_setup.c new file mode 100644 index 0000000..7a48358 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_bl31_setup.c @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "qemu_private.h" + +/* + * The next 3 constants identify the extents of the code, RO data region and the + * limit of the BL3-1 image. These addresses are used by the MMU setup code and + * therefore they must be page-aligned. It is the responsibility of the linker + * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_RO_BASE (unsigned long)(&__RO_START__) +#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +#define BL31_END (unsigned long)(&__BL31_END__) + +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) + +/* + * Placeholder variables for copying the arguments that have been passed to + * BL3-1 from BL2. + */ +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + +/******************************************************************************* + * Perform any BL3-1 early platform setup. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before + * they are lost (potentially). This needs to be done before the MMU is + * initialized so that the memory layout can be used while creating page + * tables. BL2 has flushed this information to memory, so we are guaranteed + * to pick up good data. + ******************************************************************************/ +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +{ + /* Initialize the console to provide early debug support */ + console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ, + PLAT_QEMU_CONSOLE_BAUDRATE); + + /* + * Check params passed from BL2 should not be NULL, + */ + assert(from_bl2 != NULL); + assert(from_bl2->h.type == PARAM_BL31); + assert(from_bl2->h.version >= VERSION_1); + /* + * In debug builds, we pass a special value in 'plat_params_from_bl2' + * to verify platform parameters from BL2 to BL3-1. + * In release builds, it's not used. + */ + assert(((unsigned long long)plat_params_from_bl2) == + QEMU_BL31_PLAT_PARAM_VAL); + + /* + * Copy BL3-2 (if populated by BL2) and BL3-3 entry point information. + * They are stored in Secure RAM, in BL2's address space. + */ + if (from_bl2->bl32_ep_info) + bl32_image_ep_info = *from_bl2->bl32_ep_info; + bl33_image_ep_info = *from_bl2->bl33_ep_info; +} + +void bl31_plat_arch_setup(void) +{ + qemu_configure_mmu_el3(BL31_RO_BASE, (BL31_END - BL31_RO_BASE), + BL31_RO_BASE, BL31_RO_LIMIT, + BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT); +} + +static const unsigned int irq_sec_array[] = { + QEMU_IRQ_SEC_SGI_0, + QEMU_IRQ_SEC_SGI_1, + QEMU_IRQ_SEC_SGI_2, + QEMU_IRQ_SEC_SGI_3, + QEMU_IRQ_SEC_SGI_4, + QEMU_IRQ_SEC_SGI_5, + QEMU_IRQ_SEC_SGI_6, + QEMU_IRQ_SEC_SGI_7, +}; + +static const struct gicv2_driver_data plat_gicv2_driver_data = { + .gicd_base = GICD_BASE, + .gicc_base = GICC_BASE, + .g0_interrupt_num = ARRAY_SIZE(irq_sec_array), + .g0_interrupt_array = irq_sec_array, +}; + +void bl31_platform_setup(void) +{ + /* Initialize the gic cpu and distributor interfaces */ + gicv2_driver_init(&plat_gicv2_driver_data); + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return SYS_COUNTER_FREQ_IN_TICKS; +} + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image + * for the security state specified. BL3-3 corresponds to the non-secure + * image type while BL3-2 corresponds to the secure image type. A NULL + * pointer is returned if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + assert(sec_state_is_valid(type)); + next_image_info = (type == NON_SECURE) + ? &bl33_image_ep_info : &bl32_image_ep_info; + /* + * None of the images on the ARM development platforms can have 0x0 + * as the entrypoint + */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_common.c new file mode 100644 index 0000000..7ba1d34 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_common.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "qemu_private.h" +#include + +#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ + DEVICE0_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#ifdef DEVICE1_BASE +#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ + DEVICE1_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) +#endif + +#ifdef DEVICE2_BASE +#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ + DEVICE2_SIZE, \ + MT_DEVICE | MT_RO | MT_SECURE) +#endif + +#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ + SHARED_RAM_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \ + MT_MEMORY | MT_RO | MT_SECURE) + +/* + * Table of regions for various BL stages to map using the MMU. + * This doesn't include TZRAM as the 'mem_layout' argument passed to + * arm_configure_mmu_elx() will give the available subset of that, + */ +#if IMAGE_BL1 +static const mmap_region_t plat_qemu_mmap[] = { + MAP_FLASH0, + MAP_SHARED_RAM, + MAP_DEVICE0, +#ifdef MAP_DEVICE1 + MAP_DEVICE1, +#endif +#ifdef MAP_DEVICE2 + MAP_DEVICE2, +#endif + {0} +}; +#endif +#if IMAGE_BL2 +static const mmap_region_t plat_qemu_mmap[] = { + MAP_FLASH0, + MAP_SHARED_RAM, + MAP_DEVICE0, +#ifdef MAP_DEVICE1 + MAP_DEVICE1, +#endif +#ifdef MAP_DEVICE2 + MAP_DEVICE2, +#endif + MAP_NS_DRAM0, + MAP_BL32_MEM, + {0} +}; +#endif +#if IMAGE_BL31 +static const mmap_region_t plat_qemu_mmap[] = { + MAP_SHARED_RAM, + MAP_DEVICE0, +#ifdef MAP_DEVICE1 + MAP_DEVICE1, +#endif + MAP_BL32_MEM, + {0} +}; +#endif + +/******************************************************************************* + * Macro generating the code for the function setting up the pagetables as per + * the platform memory map & initialize the mmu, for the given exception level + ******************************************************************************/ + +#define DEFINE_CONFIGURE_MMU_EL(_el) \ + void qemu_configure_mmu_el##_el(unsigned long total_base, \ + unsigned long total_size, \ + unsigned long ro_start, \ + unsigned long ro_limit, \ + unsigned long coh_start, \ + unsigned long coh_limit) \ + { \ + mmap_add_region(total_base, total_base, \ + total_size, \ + MT_MEMORY | MT_RW | MT_SECURE); \ + mmap_add_region(ro_start, ro_start, \ + ro_limit - ro_start, \ + MT_MEMORY | MT_RO | MT_SECURE); \ + mmap_add_region(coh_start, coh_start, \ + coh_limit - coh_start, \ + MT_DEVICE | MT_RW | MT_SECURE); \ + mmap_add(plat_qemu_mmap); \ + init_xlat_tables(); \ + \ + enable_mmu_el##_el(0); \ + } + +/* Define EL1 and EL3 variants of the function initialising the MMU */ +DEFINE_CONFIGURE_MMU_EL(1) +DEFINE_CONFIGURE_MMU_EL(3) + + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_gic.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_gic.c new file mode 100644 index 0000000..44ce19c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_gic.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +uint32_t plat_ic_get_pending_interrupt_id(void) +{ + return gicv2_get_pending_interrupt_id(); +} + +uint32_t plat_ic_get_pending_interrupt_type(void) +{ + return gicv2_get_pending_interrupt_type(); +} + +uint32_t plat_ic_acknowledge_interrupt(void) +{ + return gicv2_acknowledge_interrupt(); +} + +uint32_t plat_ic_get_interrupt_type(uint32_t id) +{ + uint32_t group; + + group = gicv2_get_interrupt_group(id); + + /* Assume that all secure interrupts are S-EL1 interrupts */ + if (!group) + return INTR_TYPE_S_EL1; + else + return INTR_TYPE_NS; + +} + +void plat_ic_end_of_interrupt(uint32_t id) +{ + gicv2_end_of_interrupt(id); +} + +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state) +{ + assert(type == INTR_TYPE_S_EL1 || + type == INTR_TYPE_EL3 || + type == INTR_TYPE_NS); + + assert(sec_state_is_valid(security_state)); + + /* Non-secure interrupts are signalled on the IRQ line always */ + if (type == INTR_TYPE_NS) + return __builtin_ctz(SCR_IRQ_BIT); + + /* + * Secure interrupts are signalled using the IRQ line if the FIQ_EN + * bit is not set else they are signalled using the FIQ line. + */ + if (gicv2_is_fiq_enabled()) + return __builtin_ctz(SCR_FIQ_BIT); + else + return __builtin_ctz(SCR_IRQ_BIT); +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_io_storage.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_io_storage.c new file mode 100644 index 0000000..b7951b7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_io_storage.c @@ -0,0 +1,378 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include /* For ARRAY_SIZE */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Semihosting filenames */ +#define BL2_IMAGE_NAME "bl2.bin" +#define BL31_IMAGE_NAME "bl31.bin" +#define BL32_IMAGE_NAME "bl32.bin" +#define BL33_IMAGE_NAME "bl33.bin" + +#if TRUSTED_BOARD_BOOT +#define BL2_CERT_NAME "bl2.crt" +#define TRUSTED_KEY_CERT_NAME "trusted_key.crt" +#define BL31_KEY_CERT_NAME "bl31_key.crt" +#define BL32_KEY_CERT_NAME "bl32_key.crt" +#define BL33_KEY_CERT_NAME "bl33_key.crt" +#define BL31_CERT_NAME "bl31.crt" +#define BL32_CERT_NAME "bl32.crt" +#define BL33_CERT_NAME "bl33.crt" +#endif /* TRUSTED_BOARD_BOOT */ + + + +/* IO devices */ +static const io_dev_connector_t *fip_dev_con; +static uintptr_t fip_dev_handle; +static const io_dev_connector_t *memmap_dev_con; +static uintptr_t memmap_dev_handle; +static const io_dev_connector_t *sh_dev_con; +static uintptr_t sh_dev_handle; + +static const io_block_spec_t fip_block_spec = { + .offset = PLAT_QEMU_FIP_BASE, + .length = PLAT_QEMU_FIP_MAX_SIZE +}; + +static const io_uuid_spec_t bl2_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2, +}; + +static const io_uuid_spec_t bl31_uuid_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31, +}; + +static const io_uuid_spec_t bl32_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32, +}; + +static const io_uuid_spec_t bl33_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, +}; + +#if TRUSTED_BOARD_BOOT +static const io_uuid_spec_t bl2_cert_uuid_spec = { + .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2_CERT, +}; + +static const io_uuid_spec_t trusted_key_cert_uuid_spec = { + .uuid = UUID_TRUSTED_KEY_CERT, +}; + +static const io_uuid_spec_t bl31_key_cert_uuid_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31_KEY_CERT, +}; + +static const io_uuid_spec_t bl32_key_cert_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_KEY_CERT, +}; + +static const io_uuid_spec_t bl33_key_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33_KEY_CERT, +}; + +static const io_uuid_spec_t bl31_cert_uuid_spec = { + .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31_CERT, +}; + +static const io_uuid_spec_t bl32_cert_uuid_spec = { + .uuid = UUID_SECURE_PAYLOAD_BL32_CERT, +}; + +static const io_uuid_spec_t bl33_cert_uuid_spec = { + .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33_CERT, +}; +#endif /* TRUSTED_BOARD_BOOT */ + +static const io_file_spec_t sh_file_spec[] = { + [BL2_IMAGE_ID] = { + .path = BL2_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, + [BL31_IMAGE_ID] = { + .path = BL31_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, + [BL32_IMAGE_ID] = { + .path = BL32_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, + [BL33_IMAGE_ID] = { + .path = BL33_IMAGE_NAME, + .mode = FOPEN_MODE_RB + }, +#if TRUSTED_BOARD_BOOT + [BL2_CERT_ID] = { + .path = BL2_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [TRUSTED_KEY_CERT_ID] = { + .path = TRUSTED_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [BL31_KEY_CERT_ID] = { + .path = BL31_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [BL32_KEY_CERT_ID] = { + .path = BL32_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [BL33_KEY_CERT_ID] = { + .path = BL33_KEY_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [BL31_CERT_ID] = { + .path = BL31_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [BL32_CERT_ID] = { + .path = BL32_CERT_NAME, + .mode = FOPEN_MODE_RB + }, + [BL33_CERT_ID] = { + .path = BL33_CERT_NAME, + .mode = FOPEN_MODE_RB + }, +#endif /* TRUSTED_BOARD_BOOT */ +}; + + + +static int open_fip(const uintptr_t spec); +static int open_memmap(const uintptr_t spec); + +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int (*check)(const uintptr_t spec); +}; + +/* By default, ARM platforms load images from the FIP */ +static const struct plat_io_policy policies[] = { + [FIP_IMAGE_ID] = { + &memmap_dev_handle, + (uintptr_t)&fip_block_spec, + open_memmap + }, + [BL2_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl2_uuid_spec, + open_fip + }, + [BL31_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl31_uuid_spec, + open_fip + }, + [BL32_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_uuid_spec, + open_fip + }, + [BL33_IMAGE_ID] = { + &fip_dev_handle, + (uintptr_t)&bl33_uuid_spec, + open_fip + }, +#if TRUSTED_BOARD_BOOT + [BL2_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl2_cert_uuid_spec, + open_fip + }, + [TRUSTED_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&trusted_key_cert_uuid_spec, + open_fip + }, + [BL31_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl31_key_cert_uuid_spec, + open_fip + }, + [BL32_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_key_cert_uuid_spec, + open_fip + }, + [BL33_KEY_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl33_key_cert_uuid_spec, + open_fip + }, + [BL31_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl31_cert_uuid_spec, + open_fip + }, + [BL32_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl32_cert_uuid_spec, + open_fip + }, + [BL33_CERT_ID] = { + &fip_dev_handle, + (uintptr_t)&bl33_cert_uuid_spec, + open_fip + }, +#endif /* TRUSTED_BOARD_BOOT */ +}; + +static int open_fip(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + /* See if a Firmware Image Package is available */ + result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); + if (result == 0) { + result = io_open(fip_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using FIP\n"); + io_close(local_image_handle); + } + } + return result; +} + +static int open_memmap(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(memmap_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using Memmap\n"); + io_close(local_image_handle); + } + } + return result; +} + +static int open_semihosting(const uintptr_t spec) +{ + int result; + uintptr_t local_image_handle; + + /* See if the file exists on semi-hosting.*/ + result = io_dev_init(sh_dev_handle, (uintptr_t)NULL); + if (result == 0) { + result = io_open(sh_dev_handle, spec, &local_image_handle); + if (result == 0) { + VERBOSE("Using Semi-hosting IO\n"); + io_close(local_image_handle); + } + } + return result; +} + +void plat_qemu_io_setup(void) +{ + int io_result; + + io_result = register_io_dev_fip(&fip_dev_con); + assert(io_result == 0); + + io_result = register_io_dev_memmap(&memmap_dev_con); + assert(io_result == 0); + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, + &fip_dev_handle); + assert(io_result == 0); + + io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, + &memmap_dev_handle); + assert(io_result == 0); + + /* Register the additional IO devices on this platform */ + io_result = register_io_dev_sh(&sh_dev_con); + assert(io_result == 0); + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(sh_dev_con, (uintptr_t)NULL, &sh_dev_handle); + assert(io_result == 0); + + /* Ignore improbable errors in release builds */ + (void)io_result; +} + +static int get_alt_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result = open_semihosting((const uintptr_t)&sh_file_spec[image_id]); + + if (result == 0) { + *dev_handle = sh_dev_handle; + *image_spec = (uintptr_t)&sh_file_spec[image_id]; + } + + return result; +} + +/* + * Return an IO device handle and specification which can be used to access + * an image. Use this to enforce platform load policy + */ +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result; + const struct plat_io_policy *policy; + + assert(image_id < ARRAY_SIZE(policies)); + + policy = &policies[image_id]; + result = policy->check(policy->image_spec); + if (result == 0) { + *image_spec = policy->image_spec; + *dev_handle = *(policy->dev_handle); + } else { + VERBOSE("Trying alternative IO\n"); + result = get_alt_image_source(image_id, dev_handle, image_spec); + } + + return result; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_pm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_pm.c new file mode 100644 index 0000000..8114c16 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_pm.c @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* + * The secure entry point to be used on warm reset. + */ +static unsigned long secure_entrypoint; + +/* Make composite power state parameter till power level 0 */ +#if PSCI_EXTENDED_STATE_ID + +#define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) +#else +#define qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ + (((lvl0_state) << PSTATE_ID_SHIFT) | \ + ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ + ((type) << PSTATE_TYPE_SHIFT)) +#endif /* PSCI_EXTENDED_STATE_ID */ + + +#define qemu_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ + (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \ + qemu_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) + + + +/* + * The table storing the valid idle power states. Ensure that the + * array entries are populated in ascending order of state-id to + * enable us to use binary search during power state validation. + * The table must be terminated by a NULL entry. + */ +static const unsigned int qemu_pm_idle_states[] = { + /* State-id - 0x01 */ + qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET, + MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY), + /* State-id - 0x02 */ + qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF, + MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN), + /* State-id - 0x22 */ + qemu_make_pwrstate_lvl1(PLAT_LOCAL_STATE_OFF, PLAT_LOCAL_STATE_OFF, + MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN), + 0, +}; + +/******************************************************************************* + * Platform handler called to check the validity of the power state + * parameter. The power state parameter has to be a composite power state. + ******************************************************************************/ +static int qemu_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + unsigned int state_id; + int i; + + assert(req_state); + + /* + * Currently we are using a linear search for finding the matching + * entry in the idle power state array. This can be made a binary + * search if the number of entries justify the additional complexity. + */ + for (i = 0; !!qemu_pm_idle_states[i]; i++) { + if (power_state == qemu_pm_idle_states[i]) + break; + } + + /* Return error if entry not found in the idle state array */ + if (!qemu_pm_idle_states[i]) + return PSCI_E_INVALID_PARAMS; + + i = 0; + state_id = psci_get_pstate_id(power_state); + + /* Parse the State ID and populate the state info parameter */ + while (state_id) { + req_state->pwr_domain_state[i++] = state_id & + PLAT_LOCAL_PSTATE_MASK; + state_id >>= PLAT_LOCAL_PSTATE_WIDTH; + } + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * Platform handler called to check the validity of the non secure + * entrypoint. + ******************************************************************************/ +static int qemu_validate_ns_entrypoint(uintptr_t entrypoint) +{ + /* + * Check if the non secure entrypoint lies within the non + * secure DRAM. + */ + if ((entrypoint >= NS_DRAM0_BASE) && + (entrypoint < (NS_DRAM0_BASE + NS_DRAM0_SIZE))) + return PSCI_E_SUCCESS; + return PSCI_E_INVALID_ADDRESS; +} + +/******************************************************************************* + * Platform handler called when a CPU is about to enter standby. + ******************************************************************************/ +static void qemu_cpu_standby(plat_local_state_t cpu_state) +{ + + assert(cpu_state == PLAT_LOCAL_STATE_RET); + + /* + * Enter standby state + * dsb is good practice before using wfi to enter low power states + */ + dsb(); + wfi(); +} + +/******************************************************************************* + * Platform handler called when a power domain is about to be turned on. The + * mpidr determines the CPU to be turned on. + ******************************************************************************/ +static int qemu_pwr_domain_on(u_register_t mpidr) +{ + int rc = PSCI_E_SUCCESS; + unsigned pos = plat_core_pos_by_mpidr(mpidr); + uint64_t *hold_base = (uint64_t *)PLAT_QEMU_HOLD_BASE; + + hold_base[pos] = PLAT_QEMU_HOLD_STATE_GO; + sev(); + + return rc; +} + +/******************************************************************************* + * Platform handler called when a power domain is about to be turned off. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void qemu_pwr_domain_off(const psci_power_state_t *target_state) +{ + assert(0); +} + +/******************************************************************************* + * Platform handler called when a power domain is about to be suspended. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void qemu_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + assert(0); +} + +/******************************************************************************* + * Platform handler called when a power domain has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. + ******************************************************************************/ +void qemu_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == + PLAT_LOCAL_STATE_OFF); + + /* TODO: This setup is needed only after a cold boot */ + gicv2_pcpu_distif_init(); + + /* Enable the gic cpu interface */ + gicv2_cpuif_enable(); +} + +/******************************************************************************* + * Platform handler called when a power domain has just been powered on after + * having been suspended earlier. The target_state encodes the low power state + * that each level has woken up from. + ******************************************************************************/ +void qemu_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ + assert(0); +} + +/******************************************************************************* + * Platform handlers to shutdown/reboot the system + ******************************************************************************/ +static void __dead2 qemu_system_off(void) +{ + ERROR("QEMU System Off: operation not handled.\n"); + panic(); +} + +static void __dead2 qemu_system_reset(void) +{ + ERROR("QEMU System Reset: operation not handled.\n"); + panic(); +} + +static const plat_psci_ops_t plat_qemu_psci_pm_ops = { + .cpu_standby = qemu_cpu_standby, + .pwr_domain_on = qemu_pwr_domain_on, + .pwr_domain_off = qemu_pwr_domain_off, + .pwr_domain_suspend = qemu_pwr_domain_suspend, + .pwr_domain_on_finish = qemu_pwr_domain_on_finish, + .pwr_domain_suspend_finish = qemu_pwr_domain_suspend_finish, + .system_off = qemu_system_off, + .system_reset = qemu_system_reset, + .validate_power_state = qemu_validate_power_state, + .validate_ns_entrypoint = qemu_validate_ns_entrypoint +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + uintptr_t *mailbox = (void *) PLAT_QEMU_TRUSTED_MAILBOX_BASE; + + *mailbox = sec_entrypoint; + secure_entrypoint = (unsigned long) sec_entrypoint; + *psci_ops = &plat_qemu_psci_pm_ops; + + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_private.h new file mode 100644 index 0000000..2595e66 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/qemu_private.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __QEMU_PRIVATE_H +#define __QEMU_PRIVATE_H + +#include + +void qemu_configure_mmu_el1(unsigned long total_base, unsigned long total_size, + unsigned long ro_start, unsigned long ro_limit, + unsigned long coh_start, unsigned long coh_limit); + +void qemu_configure_mmu_el3(unsigned long total_base, unsigned long total_size, + unsigned long ro_start, unsigned long ro_limit, + unsigned long coh_start, unsigned long coh_limit); + +void plat_qemu_io_setup(void); +unsigned int plat_qemu_calc_core_pos(u_register_t mpidr); + +int dt_add_psci_node(void *fdt); +int dt_add_psci_cpu_enable_methods(void *fdt); + +#endif /*__QEMU_PRIVATE_H*/ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/topology.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/topology.c new file mode 100644 index 0000000..ea546ac --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/qemu/topology.c @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "qemu_private.h" +#include + +/* The power domain tree descriptor */ +static unsigned char power_domain_tree_desc[] = { + /* Number of root nodes */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first node */ + PLATFORM_CLUSTER0_CORE_COUNT, + /* Number of children for the second node */ + PLATFORM_CLUSTER1_CORE_COUNT, +}; + +/******************************************************************************* + * This function returns the ARM default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) + return -1; + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) + return -1; + + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) + return -1; + + return plat_qemu_calc_core_pos(mpidr); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/aarch64/bl2_reset.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/aarch64/bl2_reset.S new file mode 100644 index 0000000..150210b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/aarch64/bl2_reset.S @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "platform_def.h" + + +#define RST_BASE (0xE6160000) +#define RST_CA53BAR2 (0x0034) +#define RST_CA57BAR2 (0x0024) +#define RST_CA53CPU0BARH (0x0080) +#define RST_CA53CPU0BARL (0x0084) +#define RST_CA53CPU1BARH (0x0090) +#define RST_CA53CPU1BARL (0x0094) +#define RST_CA53CPU2BARH (0x00A0) +#define RST_CA53CPU2BARL (0x00A4) +#define RST_CA53CPU3BARH (0x00B0) +#define RST_CA53CPU3BARL (0x00B4) +#define RST_CA57CPU0BARH (0x00C0) +#define RST_CA57CPU0BARL (0x00C4) +#define RST_CA57CPU1BARH (0x00D0) +#define RST_CA57CPU1BARL (0x00D4) +#define RST_CA57CPU2BARH (0x00E0) +#define RST_CA57CPU2BARL (0x00E4) +#define RST_CA57CPU3BARH (0x00F0) +#define RST_CA57CPU3BARL (0x00F4) + +#define RST_BAR2_MASK (0xFFFFFC00) +#define RST_BAR2_BAREN (0x00000010) +#define RST_BAR2_VLD (0x00000001) +#define RST_BAR2_SHIFT (18-10) +#define RST_CPUnBARH_SHIFT (32) +#define RST_CPUnBARH_MASK (0x000000FF) +#define RST_CPUnBARL_MASK (0xFFFFFFFC) + + + .global bl2_reset + .global bl2_secondly_reset + .global bl2_init_secondly_reset + .global bl2_init_generic_timer + +func bl2_reset + mov x0, #0 + mov x1, #0 + mov x2, #0 + mov x3, #0 + mov x4, #0 + mov x5, #0 + mov x6, #0 + mov x7, #0 + mov x8, #0 + mov x9, #0 + mov x10, #0 + mov x11, #0 + mov x12, #0 + mov x13, #0 + mov x14, #0 + mov x15, #0 + mov x16, #0 + mov x17, #0 + mov x18, #0 + mov x19, #0 + mov x20, #0 + mov x21, #0 + mov x22, #0 + mov x23, #0 + mov x24, #0 + mov x25, #0 + mov x26, #0 + mov x27, #0 + mov x28, #0 + mov x29, #0 + mov x30, #0 + + /* --------------------------------------------- + * Set the CPU endianness before doing anything + * that might involve memory reads or writes. + * --------------------------------------------- + */ + mrs x0, sctlr_el3 + bic x0, x0, #SCTLR_EE_BIT + msr sctlr_el3, x0 + isb + + /* --------------------------------------------- + * Set the exception vector to something sane. + * --------------------------------------------- + */ + adr x0, bl2_exceptions + msr vbar_el3, x0 + isb + + /* --------------------------------------------- + * If SError is vaild, enable SError exception(clear PSTATE.A bit) + * and clear SError exception. + * --------------------------------------------- + */ + mov x0, #(SCR_RES1_BITS | SCR_EA_BIT | SCR_SIF_BIT) + msr scr_el3, x0 + + msr daifclr, #DAIF_ABT_BIT + nop + msr daifset, #DAIF_ABT_BIT + + + /* --------------------------------------------------------------------- + * The initial state of the Architectural feature trap register + * (CPTR_EL3) is unknown and it must be set to a known state. All + * feature traps are disabled. Some bits in this register are marked as + * Reserved and should not be modified. + * + * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 + * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. + * CPTR_EL3.TTA: This causes access to the Trace functionality to trap + * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register + * access to trace functionality is not supported, this bit is RES0. + * CPTR_EL3.TFP: This causes instructions that access the registers + * associated with Floating Point and Advanced SIMD execution to trap + * to EL3 when executed from any exception level, unless trapped to EL1 + * or EL2. + * --------------------------------------------------------------------- + */ + mrs x0, cptr_el3 + bic w0, w0, #TCPAC_BIT + bic w0, w0, #TTA_BIT + bic w0, w0, #TFP_BIT + msr cptr_el3, x0 + + /* -------------------------------------------- + * Allocate a stack whose memory will be marked + * as Normal-IS-WBWA when the MMU is enabled. + * There is no risk of reading stale stack + * memory after enabling the MMU as only the + * primary cpu is running at the moment. + * -------------------------------------------- + */ + bl plat_set_my_stack + + /* -------------------------------------------- + * Enable the generic timer via memory mapped + * access. + * Enable it here quite early in the boot + * phase as long as we are still in EL3 + * -------------------------------------------- + */ + bl bl2_init_generic_timer + + mov x0, #(SCR_RES1_BITS | SCR_RW_BIT) + msr scr_el3, x0 + + ldr x0, =bl2_entrypoint + msr elr_el3, x0 + mov x1, #(DISABLE_ALL_EXCEPTIONS << SPSR_DAIF_SHIFT) | (MODE_RW_64 << MODE_RW_SHIFT) | (MODE_EL1 << MODE_EL_SHIFT) | (MODE_SP_ELX << MODE_SP_SHIFT) + msr spsr_el3, x1 + + adr x1, BL2_MEM_INFO + + eret +endfunc bl2_reset + + + .align 3 +BL2_MEM_INFO: /* meminfo_t */ + .quad BL31_BASE /* total_base */ + .quad (BL31_LIMIT - BL31_BASE) /* total_size */ + .quad BL31_BASE /* free_base */ + .quad (BL31_LIMIT - BL31_BASE) /* free_size */ + + + .section .vectors, "ax"; .align 11 + + /* ----------------------------------------------------- + * Very simple stackless exception handlers used by BL1. + * ----------------------------------------------------- + */ + .align 7 +bl2_exceptions: + /* ----------------------------------------------------- + * Current EL with SP0 : 0x0 - 0x200 + * ----------------------------------------------------- + */ +SynchronousExceptionSP0: + mov x0, #SYNC_EXCEPTION_SP_EL0 + bl plat_report_exception + b SynchronousExceptionSP0 + check_vector_size SynchronousExceptionSP0 + + .align 7 +IrqSP0: + mov x0, #IRQ_SP_EL0 + bl plat_report_exception + b IrqSP0 + check_vector_size IrqSP0 + + .align 7 +FiqSP0: + mov x0, #FIQ_SP_EL0 + bl plat_report_exception + b FiqSP0 + check_vector_size FiqSP0 + + .align 7 +SErrorSP0: + mov x0, #SERROR_SP_EL0 + bl plat_report_exception + b SErrorSP0 + check_vector_size SErrorSP0 + + /* ----------------------------------------------------- + * Current EL with SPx: 0x200 - 0x400 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionSPx: + mov x0, #SYNC_EXCEPTION_SP_ELX + bl plat_report_exception + b SynchronousExceptionSPx + check_vector_size SynchronousExceptionSPx + + .align 7 +IrqSPx: + mov x0, #IRQ_SP_ELX + bl plat_report_exception + b IrqSPx + check_vector_size IrqSPx + + .align 7 +FiqSPx: + mov x0, #FIQ_SP_ELX + bl plat_report_exception + b FiqSPx + check_vector_size FiqSPx + + .align 7 +SErrorSPx: + /* --------------------------------------------- + * If SError is vaild, clear SError exception. + * --------------------------------------------- + */ + eret + mov x0, #SERROR_SP_ELX + bl plat_report_exception + b SErrorSPx + check_vector_size SErrorSPx + + /* ----------------------------------------------------- + * Lower EL using AArch64 : 0x400 - 0x600 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionA64: + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + + /* ------------------------------------------------ + * Only a single SMC exception from BL2 to ask + * BL1 to pass EL3 control to BL31 is expected + * here. + * It expects X0 with RUN_IMAGE SMC function id + * X1 with address of a entry_point_info_t structure + * describing the BL3-1 entrypoint + * ------------------------------------------------ + */ + mov x19, x0 + mov x20, x1 + + mrs x0, esr_el3 + ubfx x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH + cmp x1, #EC_AARCH64_SMC + b.ne panic + + mov x0, #BL1_SMC_RUN_IMAGE + cmp x19, x0 + b.ne panic + + mov x0, x20 + ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] + msr elr_el3, x0 + msr spsr_el3, x1 + ubfx x0, x1, #MODE_EL_SHIFT, #2 + cmp x0, #MODE_EL3 + b.ne panic + + ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] + ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] + ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] + ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] + eret + +panic: + mov x0, #SYNC_EXCEPTION_AARCH64 + bl plat_report_exception + + wfi + b panic + check_vector_size SynchronousExceptionA64 + + + .align 7 +IrqA64: + mov x0, #IRQ_AARCH64 + bl plat_report_exception + b IrqA64 + check_vector_size IrqA64 + + .align 7 +FiqA64: + mov x0, #FIQ_AARCH64 + bl plat_report_exception + b FiqA64 + check_vector_size FiqA64 + + .align 7 +SErrorA64: + mov x0, #SERROR_AARCH64 + bl plat_report_exception + b SErrorA64 + check_vector_size SErrorA64 + + /* ----------------------------------------------------- + * Lower EL using AArch32 : 0x600 - 0x800 + * ----------------------------------------------------- + */ + .align 7 +SynchronousExceptionA32: + mov x0, #SYNC_EXCEPTION_AARCH32 + bl plat_report_exception + b SynchronousExceptionA32 + check_vector_size SynchronousExceptionA32 + + .align 7 +IrqA32: + mov x0, #IRQ_AARCH32 + bl plat_report_exception + b IrqA32 + check_vector_size IrqA32 + + .align 7 +FiqA32: + mov x0, #FIQ_AARCH32 + bl plat_report_exception + b FiqA32 + check_vector_size FiqA32 + + .align 7 +SErrorA32: + mov x0, #SERROR_AARCH32 + bl plat_report_exception + b SErrorA32 + check_vector_size SErrorA32 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/aarch64/rcar_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/aarch64/rcar_common.c new file mode 100644 index 0000000..a44b438 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/aarch64/rcar_common.c @@ -0,0 +1,356 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rcar_def.h" +#include "rcar_private.h" +#include "rcar_version.h" + +const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN] + __attribute__((__section__(".version"))) = VERSION_OF_RENESAS; + +#define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \ + RCAR_SHARED_MEM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \ + FLASH0_SIZE, \ + MT_MEMORY | MT_RO | MT_SECURE) + +#define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \ + DRAM1_NS_SIZE, \ + MT_MEMORY | MT_RW | MT_NS) + +#ifdef BL32_BASE +#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_BASE, \ + BL32_LIMIT - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) +#endif + +#define MAP_DEVICE_RCAR MAP_REGION_FLAT(DEVICE_RCAR_BASE, \ + DEVICE_RCAR_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_DEVICE_RCAR2 MAP_REGION_FLAT(DEVICE_RCAR_BASE2, \ + DEVICE_RCAR_SIZE2, \ + MT_DEVICE | MT_RW | MT_SECURE) + +#define MAP_SRAM MAP_REGION_FLAT(DEVICE_SRAM_BASE, \ + DEVICE_SRAM_SIZE, \ + MT_MEMORY | MT_RO | MT_SECURE) + +#define MAP_SRAM_SHADOW MAP_REGION(DEVICE_SRAM_BASE, \ + DEVICE_SRAM_SHADOW_BASE, \ + DEVICE_SRAM_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MAP_SRAM_STACK MAP_REGION_FLAT(DEVICE_SRAM_STACK_BASE, \ + DEVICE_SRAM_STACK_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MAP_ATFW_CRASH MAP_REGION_FLAT(RCAR_BL31_CRASH_BASE, \ + RCAR_BL31_CRASH_SIZE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define MAP_ATFW_LOG MAP_REGION_FLAT(RCAR_BL31_LOG_BASE, \ + RCAR_BL31_LOG_SIZE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/* + * Table of regions for various BL stages to map using the MMU. + * This doesn't include TZRAM as the 'mem_layout' argument passed to + * configure_mmu_elx() will give the available subset of that, + */ +#if IMAGE_BL1 +const mmap_region_t rcar_mmap[] = { + MAP_SHARED_RAM, + MAP_FLASH0, + MAP_DEVICE0, + MAP_DEVICE1, + { 0} +}; +#endif +#if IMAGE_BL2 +const mmap_region_t rcar_mmap[] = { + MAP_SHARED_RAM, + MAP_FLASH0, + MAP_DRAM1_NS, +#ifdef BL32_BASE + MAP_BL32_MEM, +#endif + MAP_DEVICE_RCAR, + { 0} +}; +#endif +#if IMAGE_BL31 +const mmap_region_t rcar_mmap[] = { + MAP_SHARED_RAM, + MAP_ATFW_CRASH, + MAP_ATFW_LOG, + MAP_DEVICE_RCAR, + MAP_DEVICE_RCAR2, + MAP_SRAM, + MAP_SRAM_SHADOW, + MAP_SRAM_STACK, + { 0} +}; +#endif +#if IMAGE_BL32 +const mmap_region_t rcar_mmap[] = { + MAP_DEVICE0, + MAP_DEVICE1, + { 0} +}; +#endif + +CASSERT(ARRAY_SIZE(rcar_mmap) + RCAR_BL_REGIONS \ + <= MAX_MMAP_REGIONS, assert_max_mmap_regions); + +/******************************************************************************* + * Macro generating the code for the function setting up the pagetables as per + * the platform memory map & initialize the mmu, for the given exception level + ******************************************************************************/ +#if USE_COHERENT_MEM +#define DEFINE_CONFIGURE_MMU_EL(_el) \ + void rcar_configure_mmu_el##_el(unsigned long total_base, \ + unsigned long total_size, \ + unsigned long ro_start, \ + unsigned long ro_limit, \ + unsigned long coh_start, \ + unsigned long coh_limit) \ + { \ + mmap_add_region(total_base, total_base, \ + total_size, \ + MT_MEMORY | MT_RW | MT_SECURE); \ + mmap_add_region(ro_start, ro_start, \ + ro_limit - ro_start, \ + MT_MEMORY | MT_RO | MT_SECURE); \ + mmap_add_region(coh_start, coh_start, \ + coh_limit - coh_start, \ + MT_DEVICE | MT_RW | MT_SECURE); \ + mmap_add(rcar_mmap); \ + init_xlat_tables(); \ + \ + enable_mmu_el##_el(0); \ + } +#else +#define DEFINE_CONFIGURE_MMU_EL(_el) \ + void rcar_configure_mmu_el##_el(unsigned long total_base, \ + unsigned long total_size, \ + unsigned long ro_start, \ + unsigned long ro_limit) \ + { \ + mmap_add_region(total_base, total_base, \ + total_size, \ + MT_MEMORY | MT_RW | MT_SECURE); \ + mmap_add_region(ro_start, ro_start, \ + ro_limit - ro_start, \ + MT_MEMORY | MT_RO | MT_SECURE); \ + mmap_add(rcar_mmap); \ + init_xlat_tables(); \ + \ + enable_mmu_el##_el(0); \ + } +#endif + +/* Define EL1 and EL3 variants of the function initialising the MMU */ +DEFINE_CONFIGURE_MMU_EL(1) +DEFINE_CONFIGURE_MMU_EL(3) + +#if (IMAGE_BL2) +extern int32_t file_to_cert(const int32_t filename, uint32_t *cert_addr); +extern void get_info_from_cert(uint64_t cert_addr, uint32_t *size, uintptr_t *dest_addr); +#endif /* (IMAGE_BL2) */ + +#if (IMAGE_BL2) +uintptr_t plat_get_bl31_bl32_image_entrypoint(int32_t content_cert_id) +{ + int32_t ret; + uint32_t cert_addr; + uint32_t l_image_size; + uintptr_t dest_addr; + ret = file_to_cert(content_cert_id, &cert_addr); + if (0 == ret) { + get_info_from_cert((uint64_t) cert_addr, &l_image_size, &dest_addr); + } else { + ERROR("%s : cert file load error", __func__); + panic(); + } + return dest_addr; +} +#endif /* (IMAGE_BL2) */ + +uintptr_t plat_get_ns_image_entrypoint(void) +{ +#if (IMAGE_BL2) + int32_t ret; + uint32_t cert_addr; + uint32_t l_image_size; + uintptr_t dest_addr; + ret = file_to_cert(NON_TRUSTED_FW_CONTENT_CERT_ID, &cert_addr); + if (0 == ret) { + get_info_from_cert((uint64_t) cert_addr, &l_image_size, &dest_addr); + } else { + ERROR("%s : cert file load error", __func__); + dest_addr = NS_IMAGE_OFFSET; + } + return dest_addr; +#else + return NS_IMAGE_OFFSET; +#endif +} + +unsigned int plat_get_syscnt_freq2(void) +{ + unsigned int counter_base_frequency; + + /* Read the frequency from Frequency modes table */ + counter_base_frequency = (unsigned int)mmio_read_32(ARM_SYS_CNTCTL_BASE + + (uint32_t)CNTFID_OFF); + + /* The first entry of the frequency modes table must not be 0 */ + if (counter_base_frequency == 0U) { + panic(); + } + + return counter_base_frequency; +} + +/* Map of CCI masters with the slave interfaces they are connected */ +static int cci_map[] = { + CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3, + CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3 +}; + +void rcar_cci_init(void) +{ + /* + * Initialize CCI-500 driver + */ + cci_init(RCAR_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); +} + +void rcar_cci_enable(void) +{ + cci_enable_snoop_dvm_reqs((unsigned int)MPIDR_AFFLVL1_VAL(read_mpidr())); +} + +void rcar_cci_disable(void) +{ + cci_disable_snoop_dvm_reqs((unsigned int)MPIDR_AFFLVL1_VAL(read_mpidr())); +} + +/******************************************************************************* + * Gets SPSR for BL32 entry + ******************************************************************************/ +uint32_t rcar_get_spsr_for_bl32_entry(void) +{ + /* + * The Secure Payload Dispatcher service is responsible for + * setting the SPSR prior to entry into the BL32 image. + */ + return 0U; +} + +/******************************************************************************* + * Gets SPSR for BL33 entry + ******************************************************************************/ +#define BL33_EL1 0 +#define BL33_EL2 1 + +uint32_t rcar_get_spsr_for_bl33_entry(void) +{ +#if (RCAR_BL33_EXECUTION_EL == BL33_EL1) + return (uint32_t)SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); +#elif (RCAR_BL33_EXECUTION_EL == BL33_EL2) + return (uint32_t)SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); +#else +#error +#endif +} + +/* Array of secure interrupts to be configured by the gic driver */ +#if IMAGE_BL2 +static const unsigned int irq_sec_array[] = { + ARM_IRQ_SEC_WDT /* 173 */ +}; +#endif +#if IMAGE_BL31 +static const unsigned int irq_sec_array[] = { + ARM_IRQ_SEC_PHY_TIMER, /* 29 */ + ARM_IRQ_SEC_SGI_0, /* 8 */ + ARM_IRQ_SEC_SGI_1, /* 9 */ + ARM_IRQ_SEC_SGI_2, /* 10 */ + ARM_IRQ_SEC_SGI_3, /* 11 */ + ARM_IRQ_SEC_SGI_4, /* 12 */ + ARM_IRQ_SEC_SGI_5, /* 13 */ + ARM_IRQ_SEC_SGI_6, /* 14 */ + ARM_IRQ_SEC_SGI_7, /* 15 */ + ARM_IRQ_SEC_RPC, /* 70 */ + ARM_IRQ_SEC_TIMER, /* 166 */ + ARM_IRQ_SEC_TIMER_UP, /* 171 */ + ARM_IRQ_SEC_WDT, /* 173 */ + ARM_IRQ_SEC_CRYPT, /* 102 */ + ARM_IRQ_SEC_CRYPT_SecPKA, /* 97 */ + ARM_IRQ_SEC_CRYPT_PubPKA /* 98 */ +}; +#endif + +static const struct gicv2_driver_data plat_gicv2_driver_data = { + .gicd_base = RCAR_GICD_BASE, + .gicc_base = RCAR_GICC_BASE, + .g0_interrupt_num = (uint32_t)ARRAY_SIZE(irq_sec_array), + .g0_interrupt_array = irq_sec_array, +}; + +/****************************************************************************** + * ARM common helper to initialize the GICv2 only driver. + *****************************************************************************/ +void plat_arm_gic_driver_init(void) +{ + gicv2_driver_init(&plat_gicv2_driver_data); +} + +void plat_arm_gic_init(void) +{ + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/aarch64/rcar_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/aarch64/rcar_helpers.S new file mode 100644 index 0000000..1ceb081 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/aarch64/rcar_helpers.S @@ -0,0 +1,465 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "rcar_def.h" + + + .globl platform_get_entrypoint + .globl plat_secondary_cold_boot_setup + .globl platform_mem_init + .globl plat_report_exception + .globl platform_is_primary_cpu + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_reset_handler + .globl iciallu + .globl bl31_secondly_reset + + .extern platform_set_stack + .extern rcar_log_init + .extern tf_printf +#if IMAGE_BL2 + .extern bl2_swdt_exec + .extern gicv2_acknowledge_interrupt + .extern bl2_interrupt_error_type + .extern bl2_interrupt_error_id + +#define INT_ID_MASK (0x3ff) +#endif + + .extern rcar_boot_kind_flag[data] + +.section .rodata.errorlog, "aS" +error_log_data: + .asciz "[Error log is in plat_secondary_cold_setup]","" + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs log output from the address of + * error_log_data and go to cb_panic. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* + * If timer is enabled, do not clear the freq register + */ + mrs x0, CNTP_CTL_EL0 + mov x1, #1 + and x2, x0, x1 + cbnz x2, log_output /* timer is enabled */ + /* + * Timer is disabled, then clear the freq register + */ + mov x0, #0 + msr CNTFRQ_EL0, x0 +log_output: + bl platform_set_stack /* set stack pointer */ + bl rcar_log_init /* log area initialize */ + ldr x0, =error_log_data /* argument of tf_printf function */ + bl tf_printf /* log output */ +cb_panic: + b cb_panic +endfunc plat_secondary_cold_boot_setup + + + /* ----------------------------------------------------- + * void platform_get_entrypoint (unsigned int mpid); + * + * Main job of this routine is to distinguish between + * a cold and warm boot. + * On a cold boot the secondaries first wait for the + * platform to be initialized after which they are + * hotplugged in. The primary proceeds to perform the + * platform initialization. + * On a warm boot, each cpu jumps to the address in its + * mailbox. + * + * TODO: Not a good idea to save lr in a temp reg + * ----------------------------------------------------- + */ +func platform_get_entrypoint + mov x9, x30 /* lr */ + + /* + * format of x21 + * 4 3 2 1 0 + * --------------------------------- + * | | | | | + * | reset info | boot kind | + * | | | | | + * --------------------------------- + * 00 : Usual | 00 : Cold boot + * 01 : Unusual | 01 : Warm boot + * 10 : Reserved | 10 : Reserved + * 11 : Reserved | 11 : Reserved + * + */ + + /* + * Check the reset info + */ + and x1, x21, #0x000c /* Get the reset info */ + cmp x1, #0x0008 /* Is reset info "10:Reserved" ? */ + beq el3_panic + cmp x1, #0x000c /* Is reset info "11:Reserved" ? */ + beq el3_panic + /* */ + /* Check the boot kind */ + /* */ + and x1, x21, #0x0003 /* Get the boot kind */ + cmp x1, #0x0002 /* Is boot kind "10:Reserved" ? */ + beq el3_panic + cmp x1, #0x0003 /* Is boot kind "11:Reserved" ? */ + beq el3_panic + /* */ + /* warm boot or cold boot */ + /* */ + and x1, x21, #1 /* warm boot ? */ + cmp x1, #0 /* If x1 is 0 then cold boot */ + bne warm_reset /* bit0 of x1 is 1 then warm boot */ + /* */ + /* Cold boot */ + /* */ + mov x0, #0 + b exit + +warm_reset: + /* --------------------------------------------- + * A per-cpu mailbox is maintained in the tru- + * sted SDRAM. Its flushed out of the caches + * after every update using normal memory so + * its safe to read it here with SO attributes + * --------------------------------------------- + */ + ldr x10, =MBOX_BASE /* top of mailbox address -> x10 */ + bl platform_get_core_pos /* restore cpu no to x0 as CA53=0-3, CA57=4-7 */ + lsl x0, x0, #CACHE_WRITEBACK_SHIFT /* 6bit left shift */ + /* because mailbox size is 0x40 byte per cpu */ + ldr x0, [x10, x0] /* top address of mailbox is entrypoint */ + cbz x0, _panic /* If warm boot and entrypoint is 0 then panic */ +exit: + ret x9 +_panic: b _panic +endfunc platform_get_entrypoint + + + /* ----------------------------------------------------- + * void platform_mem_init (void); + * + * Zero out the mailbox registers in the shared memory + * and set the rcar_boot_kind_flag. + * The mmu is turned off right now and only the primary can + * ever execute this code. Secondaries will read the + * mailboxes using SO accesses. + * ----------------------------------------------------- + */ +func platform_mem_init + ldr x0, =MBOX_BASE + mov w1, #PLATFORM_CORE_COUNT +loop: + str xzr, [x0], #CACHE_WRITEBACK_GRANULE + subs w1, w1, #1 + b.gt loop + /* for R-Car Gen3 */ + ldr x0, =rcar_boot_kind_flag + str w21, [x0] + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * void plat_report_exception(unsigned int type) + * Function to report an unhandled exception + * with platform-specific means. + * --------------------------------------------- + */ +func plat_report_exception + mrs x1, CurrentEl + + str w0, [x1] +#if IMAGE_BL2 + mov w1, #FIQ_SP_ELX + cmp w0, w1 + beq rep_exec_fiq_elx +/* + * Please imprement checking the other type of interrupt +*/ + b rep_exec_panic_type +rep_exec_fiq_elx: + bl gicv2_acknowledge_interrupt + mov x2, #INT_ID_MASK + and x0, x0, x2 + mov x1, #ARM_IRQ_SEC_WDT_A + cmp x0, x1 + bne rep_exec_panic_id + mrs x0, ELR_EL1 + b bl2_swdt_exec +rep_exec_panic_type: /* interrupt type error */ + /* x0 is interrupt TYPE */ + b bl2_interrupt_error_type +rep_exec_panic_id: /* interrupt id error */ + /* x0 is interrupt ID */ + b bl2_interrupt_error_id +rep_exec_end: +#endif + ret +endfunc plat_report_exception + + /* + * Starting CPU is ... + * MD7=1 and MD6=1 of MODEMR : CortexR7 + * MD7=1 and MD6=0 of MODEMR : Reserved + * MD7=0 and MD6=1 of MODEMR : CortexA53 + * MD7=0 and MD6=0 of MODEMR : CortexA57 + * + * Information of MPIDR_EL1 + * affinity level 1(bit15-8) = 1 : CortexA53 + * affinity level 1(bit15-8) = 0 : CortexA57 + * + */ + +func platform_is_primary_cpu + /* + * Get MD6 and MD7 of MODEMR, then move MD6 to bit0 and move MD7 to bit1 of x1 + */ + ldr x1, =RCAR_MODEMR_A /* x1 <- address of MODEMR register */ + ldr x2, [x1] /* Get the data of MODEMR -> x2 */ + mov x1, #0x00c0 /* move MD6(0x0040) and MD7(0x0080) */ + and x1, x2, x1 /* Get MD6 and MD7 information -> x1 */ + lsr x1, x1, #6 /* MD6->bit0, MD7->bit1 */ + /* + * Get data of affinity level 1 of MPIDR_EL1, then move data to bit7-0 of x2 + */ + mov x2, #MPIDR_CLUSTER_MASK /* MPIDR_CLUSTER_MASK=0xFF00 -> x2 */ + and x2, x0, x2 /* Get the affinity level 1 -> x2 */ + lsr x2, x2, #MPIDR_AFFINITY_BITS /* affinity level 1 -> bit7-0 of x2 */ + /* + * Check the starting CPU by MD7 + */ + mov x3, #0x0002 /* for test the MD7 */ + and x3, x1, x3 /* MD7 information -> x3(0 or not) */ + cbnz x3, primary_check /* Starting CPU is CortexR7 */ + /* + * CA53 check + */ + mov x3, #0x0003 /* MD6 and MD7 */ + and x3, x1, x3 + cmp x3, #0x0001 /* If starting CPU is CortexA53 */ + bne checkCA57 /* is not then branch to check CA57 */ + cmp x2, #0x0001 /* If affinity level 1 is CortexA53 */ + beq primary_check /* CPU is CortexA53 */ + b platform_is_secondary /* It is secondary */ + /* + * CA57 check + */ +checkCA57: + cmp x3, #0x0000 /* If starting CPU is CortexA57 */ + bne platform_is_secondary + cmp x2, #0x0000 /* If affinity level 1 is CortexA57 */ + beq primary_check /* CPU is CortexA57 */ + /* + * This CPU is secondary + */ +platform_is_secondary: + mov x0, #0 /* This cpu is secondary */ + b primary_check_exit /* return */ +primary_check: + and x0, x0, # MPIDR_CPU_MASK /* Get the bit7-0 of MPIDR_EL1 -> x0 */ + cmp x0, #RCAR_PRIMARY_CPU /* x0 = 0 (primary CPU)? */ + cset x0, eq /* If x0 is 0 carry bit set */ +primary_check_exit: + ret +endfunc platform_is_primary_cpu + + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize log area + * --------------------------------------------- + */ +func plat_crash_console_init +#if IMAGE_BL2 + mov x0, #0 +#else + mov x1, sp + mov_imm x2, RCAR_CRASH_STACK + mov sp, x2 + str x1, [sp, #-16]! + str x30, [sp, #-16]! + bl console_core_init + ldr x30, [sp], #16 + ldr x1, [sp], #16 + mov sp, x1 +#endif + ret +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to store a character to log area + * --------------------------------------------- + */ +func plat_crash_console_putc + mov x1, sp + mov_imm x2, RCAR_CRASH_STACK + mov sp, x2 + str x1, [sp, #-16]! + str x30, [sp, #-16]! + str x3, [sp, #-16]! + str x4, [sp, #-16]! + str x5, [sp, #-16]! + bl console_core_putc + ldr x5, [sp], #16 + ldr x4, [sp], #16 + ldr x3, [sp], #16 + ldr x30, [sp], #16 + ldr x1, [sp], #16 + mov sp, x1 + ret +endfunc plat_crash_console_putc + + + /* -------------------------------------------------------------------- + * void plat_reset_handler(void); + * + * Before adding code in this function, refer to the guidelines in + * docs/firmware-design.md to determine whether the code should reside + * within the FIRST_RESET_HANDLER_CALL block or not. + * + * For R-Car H3: + * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 + * - Set the L2 Data setup latency to 1 (i.e. 1 cycles) for Cortex-A57 + * - Set the L2 Data RAM latency to 3 (i.e. 4 cycles) for Cortex-A57 + * For R-Car M3: + * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 + * - Set the L2 Data setup latency to 0 (i.e. 0 cycles) for Cortex-A57 + * - Set the L2 Data RAM latency to 3 (i.e. 4 cycles) for Cortex-A57 + * + * -------------------------------------------------------------------- + */ +func plat_reset_handler + /* -------------------------------------------------------------------- + * Determine whether this code is running on R-Car H3 or R-Car M3. + * Keep this information in x2. + * -------------------------------------------------------------------- + */ + /* + * On R-Car H3: x2 := 0 + * On R-Car M3: x2 := 1 + */ + ldr x0, =0xFFF00044 /* read PRR */ + ldr w0, [x0] + ubfx w0, w0, 8, 8 + cmp w0, #0x4F /* H3? */ + b.eq H3 + mov x2, #1 /* set R-Car M3 */ + b CHK_A5x +H3: + mov x2, #0 /* set R-Car H3 */ + /* -------------------------------------------------------------------- + * Determine whether this code is executed on a Cortex-A53 or on a + * Cortex-A57 core. + * -------------------------------------------------------------------- + */ +CHK_A5x: + mrs x0, midr_el1 + ubfx x1, x0, MIDR_PN_SHIFT, #12 + cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK) + b.eq A57 + + ret + +A57: + /* -------------------------------------------------------------------- + * Cortex-A57 specific settings + * -------------------------------------------------------------------- + */ + mrs x0, L2CTLR_EL1 /* Get data from L2CTLR_EL1 */ + /* + * On R-Car H3/M3 + * + * L2 Tag RAM latency is bit8-6 of L2CTLR_EL1 + * L2 Data RAM setup is bit5 of L2CTLR_EL1 + * L2 Data RAM latency is bit2-0 of L2CTLR_EL1 + */ + mov x1, #0x1e7 /* for clear bit of L2 RAM */ + neg x1, x1 /* ~(0x1e7) -> x1 */ + and x0, x0, x1 /* clear bit of L2 RAM -> x0 */ + orr x0, x0, #0x2 << 6 /* L2 Tag RAM latency (3 cycles) */ + cbnz x2, M3_L2 /* If M3 then L2 Data RAM setup is 0 */ + orr x0, x0, #0x1 << 5 /* L2 Data RAM setup (1 cycle) */ +M3_L2: + orr x0, x0, #0x3 /* L2 Data RAM latency (4 cycles) */ + msr L2CTLR_EL1, x0 /* Store data to L2CTLR_EL1 */ + +apply_l2_ram_latencies: + + ret +endfunc plat_reset_handler + + + /* --------------------------------------------- + * void iciallu(void) + * Instruction Cache Invalidate All to PoU + * --------------------------------------------- + */ +func iciallu + ic iallu + + ret +endfunc iciallu + +func bl31_secondly_reset + mrs x0, sctlr_el3 + bic x0, x0, #SCTLR_EE_BIT + msr sctlr_el3, x0 + isb + + mrs x0, cptr_el3 + bic w0, w0, #TCPAC_BIT + bic w0, w0, #TTA_BIT + bic w0, w0, #TFP_BIT + msr cptr_el3, x0 + + mov_imm x0, PARAMS_BASE /* pointer to bl31_ep_info */ + mov_imm x2, BL31_BASE + mov x1, #0x00000001 /* warm boot */ + br x2 /* jump to BL31 */ + nop + nop + nop +endfunc bl31_secondly_reset diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/bl2_cpg_init.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/bl2_cpg_init.c new file mode 100644 index 0000000..cf58705 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/bl2_cpg_init.c @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "rcar_def.h" +#include "bl2_cpg_register.h" +#include "bl2_cpg_init.h" + +typedef struct { + uintptr_t adr; + uint32_t val; +} reg_setting_t; + +static const reg_setting_t reg_setting[] = { + + /* CPG (SECURITY) registers */ + + /* Secure Module Stop Control Register 0 */ + {SCMSTPCR0, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 1 */ + {SCMSTPCR1, 0xFFFFFFBFU}, + /* Secure Module Stop Control Register 2 */ + {SCMSTPCR2, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 3 */ + {SCMSTPCR3, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 4 */ + {SCMSTPCR4, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 5 */ + {SCMSTPCR5, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 6 */ + {SCMSTPCR6, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 7 */ + {SCMSTPCR7, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 8 */ + {SCMSTPCR8, 0xFFFFFFFFU}, + /* Secure Module Stop Control Register 9 */ + {SCMSTPCR9, 0xFFFDFFFFU}, + /* Secure Software Reset Access Enable Control Register 0 */ + {SCSRSTECR0, 0x00000000U}, + /* Secure Software Reset Access Enable Control Register 1 */ + {SCSRSTECR1, 0x00000000U}, + /* Secure Software Reset Access Enable Control Register 2 */ + {SCSRSTECR2, 0x14000000U}, + /* Secure Software Reset Access Enable Control Register 3 */ + {SCSRSTECR3, 0x00000000U}, + /* Secure Software Reset Access Enable Control Register 4 */ + {SCSRSTECR4, 0x80000003U}, + /* Secure Software Reset Access Enable Control Register 5 */ + {SCSRSTECR5, 0x00000000U}, + /* Secure Software Reset Access Enable Control Register 6 */ + {SCSRSTECR6, 0x00000000U}, + /* Secure Software Reset Access Enable Control Register 7 */ + {SCSRSTECR7, 0x00000000U}, + /* Secure Software Reset Access Enable Control Register 8 */ + {SCSRSTECR8, 0x00000000U}, + /* Secure Software Reset Access Enable Control Register 9 */ + {SCSRSTECR9, 0x00020000U} +}; + +static const reg_setting_t reg_setting_rt[] = { + + /* CPG (REALTIME) registers */ + + /* Realtime Module Stop Control Register 0 */ + {RMSTPCR0, 0x00230000U}, + /* Realtime Module Stop Control Register 1 */ + {RMSTPCR1, 0xFFFFFFFFU}, + /* Realtime Module Stop Control Register 2 */ + {RMSTPCR2, 0x14062FD8U}, + /* Realtime Module Stop Control Register 3 */ + {RMSTPCR3, 0xFFFFFFDFU}, + /* Realtime Module Stop Control Register 4 */ + {RMSTPCR4, 0x80000184U}, + /* Realtime Module Stop Control Register 5 */ + {RMSTPCR5, 0x83FFFFFFU}, + /* Realtime Module Stop Control Register 6 */ + {RMSTPCR6, 0xFFFFFFFFU}, + /* Realtime Module Stop Control Register 7 */ + {RMSTPCR7, 0xFFFFFFFFU}, + /* Realtime Module Stop Control Register 8 */ + {RMSTPCR8, 0x7FF3FFF4U}, + /* Realtime Module Stop Control Register 9 */ + {RMSTPCR9, 0xFFFFFFFEU} +}; + +static const reg_setting_t reg_setting_system[] = { + + /* CPG (SYSTEM) registers */ + + /* System Module Stop Control Register 0 */ + {SMSTPCR0, 0x00000000U}, + /* System Module Stop Control Register 1 */ + {SMSTPCR1, 0xF7FFFFFFU}, + /* System Module Stop Control Register 2 */ + {SMSTPCR2, 0x00000000U}, + /* System Module Stop Control Register 3 */ + {SMSTPCR3, 0xFFFFFFDFU}, + /* System Module Stop Control Register 4 */ + {SMSTPCR4, 0x00000000U}, + /* System Module Stop Control Register 5 */ + {SMSTPCR5, 0x83BFFFFFU}, + /* System Module Stop Control Register 6 */ + {SMSTPCR6, 0xFFFFFFFFU}, + /* System Module Stop Control Register 7 */ + {SMSTPCR7, 0xFFFFFFFFU}, + /* System Module Stop Control Register 8 */ + {SMSTPCR8, 0x0003FFF4U}, + /* System Module Stop Control Register 9 */ + {SMSTPCR9, 0x03F1E017U} +}; + +void bl2_cpg_init(void) +{ + uint32_t i; + uint32_t ie; + uint32_t modemr; + + /* CPG (SECURITY) registers */ + ie = (uint32_t)(sizeof(reg_setting) / sizeof(reg_setting_t)); + + for (i = 0U; i < ie; i++) { + cpg_write(reg_setting[i].adr, reg_setting[i].val); + } + + modemr = mmio_read_32(RCAR_MODEMR); + modemr &= MODEMR_BOOT_CPU_MASK; + +} + +void bl2_system_cpg_init(void) +{ + uint32_t i; + uint32_t ie; + + /* CPG (SYSTEM) registers */ + ie = (uint32_t)(sizeof(reg_setting_system) / sizeof(reg_setting_t)); + + for (i = 0U; i < ie; i++) { + cpg_write(reg_setting_system[i].adr, reg_setting_system[i].val); + } +} + +void cpg_write(uintptr_t regadr, uint32_t regval) +{ + uint32_t value = (regval); + mmio_write_32((uintptr_t)CPG_CPGWPR,~value); + mmio_write_32(regadr,value); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/bl2_rcar_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/bl2_rcar_setup.c new file mode 100644 index 0000000..20fef15 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/bl2_rcar_setup.c @@ -0,0 +1,728 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "rcar_def.h" +#include "rcar_private.h" +#include "io_common.h" +#include "io_driver.h" +#include "io_private.h" +#include "io_rcar.h" +#include "rpc_driver.h" +#include "dma_driver.h" +#include "bl2_cpg_register.h" +#include "bl2_cpg_init.h" +#include +#include +#include "rcar_version.h" +#include "bl2_swdt.h" +#include "avs_driver.h" +#include "scif.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_def.h" +#include "rom_api.h" +#include "board.h" + + +/* CPG write protect registers */ +/*#define CPG_CPGWPR (CPG_BASE + 0x900U)*/ +/*#define CPG_CPGWPCR (CPG_BASE + 0x904U)*/ +#define CPGWPR_PASSWORD (0x5A5AFFFFU) +#define CPGWPCR_PASSWORD (0xA5A50000U) + +/* CA5x Debug Resource control registers */ +#define CPG_CA53DBGRCR (CPG_BASE + 0x1180U) +#define DBGCPUPREN ((uint32_t)1U << 19U) +#define CPG_PLL0CR (CPG_BASE + 0x00D8U) +#define CPG_PLL2CR (CPG_BASE + 0x002CU) +#define CPG_PLL4CR (CPG_BASE + 0x01F4U) + +/* RST Registers */ +#define RST_BASE (0xE6160000U) +#define RST_WDTRSTCR (RST_BASE + 0x0054U) +#define WDTRSTCR_PASSWORD (0xA55A0000U) +#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U) + +/* MFIS Registers */ +#define MFISWPCNTR_PASSWORD (0xACCE0000U) +#define MFISWPCNTR (0xE6260900U) + +/* IPMMUregisters */ +#define IPMMU_MM_BASE (0xE67B0000U) /* IPMMU-MM */ +#define IPMMUMM_SYSCTRL (IPMMU_MM_BASE + 0x0500U) +#define IPMMUMM_SYSAUX (IPMMU_MM_BASE + 0x0504U) + +/* MIDR */ +#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT) + +/* R-Car Gen3 product check */ +#define TARGET_PRODUCT RCAR_PRODUCT_V3M +#define TARGET_NAME "R-Car V3M" + +/* for SuspendToRAM */ +#define GPIO_BASE (0xE6050000U) +#define GPIO_INDT1 (GPIO_BASE + 0x100CU) +#define BIT8 ((uint32_t)1U<<8) +static uint32_t isDdrBackupMode(void); + +/******************************************************************************* + * Declarations of linker defined symbols which will help us find the layout + * of trusted SRAM + ******************************************************************************/ +extern unsigned long __RO_START__; +extern unsigned long __RO_END__; + +#if USE_COHERENT_MEM +extern unsigned long __COHERENT_RAM_START__; +extern unsigned long __COHERENT_RAM_END__; +#endif + +/* + * The next 2 constants identify the extents of the code & RO data region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. + */ +#define BL2_RO_BASE (unsigned long)(&__RO_START__) +#define BL2_RO_LIMIT (unsigned long)(&__RO_END__) + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ +#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif + +/* Data structure which holds the extents of the trusted SRAM for BL2 */ +static meminfo_t bl2_tzram_layout +__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE))); + +/* Assert that BL3-1 parameters fit in shared memory */ +CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t)) < + (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE), + assert_bl31_params_do_not_fit_in_shared_memory); + +/******************************************************************************* + * Reference to structures which holds the arguments which need to be passed + * to BL31 + ******************************************************************************/ +static bl31_params_t *bl2_to_bl31_params; +static entry_point_info_t *bl31_ep_info; + +meminfo_t *bl2_plat_sec_mem_layout(void) +{ + return &bl2_tzram_layout; +} + +/******************************************************************************* + * This function assigns a pointer to the memory that the platform has kept + * aside to pass platform specific and trusted firmware related information + * to BL31. This memory is allocated by allocating memory to + * bl2_to_bl31_params_mem_t structure which is a superset of all the + * structure whose information is passed to BL31 + * NOTE: This function should be called only once and should be done + * before generating params to BL31 + ******************************************************************************/ +bl31_params_t *bl2_plat_get_bl31_params(void) +{ + bl2_to_bl31_params_mem_t *bl31_params_mem; + + /* + * Allocate the memory for all the arguments that needs to + * be passed to BL31 + */ + bl31_params_mem = (bl2_to_bl31_params_mem_t *)PARAMS_BASE; + memset((void *)PARAMS_BASE, 0, sizeof(bl2_to_bl31_params_mem_t)); + + /* Assign memory for TF related information */ + bl2_to_bl31_params = &bl31_params_mem->bl31_params; + SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); + + /* Fill BL31 related information */ + bl31_ep_info = &bl31_params_mem->bl31_ep_info; + bl2_to_bl31_params->bl31_image_info = &bl31_params_mem->bl31_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, + VERSION_1, 0); + + /* Fill BL32 related information if it exists */ +#ifdef BL32_BASE + if (BL32_BASE) { + bl2_to_bl31_params->bl32_ep_info = + &bl31_params_mem->bl32_ep_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, + PARAM_EP, VERSION_1, 0); + bl2_to_bl31_params->bl32_image_info = + &bl31_params_mem->bl32_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, + PARAM_IMAGE_BINARY, + VERSION_1, 0); + } +#endif + + /* Fill BL33 related information */ + bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem->bl33_ep_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, + PARAM_EP, VERSION_1, 0); + bl2_to_bl31_params->bl33_image_info = &bl31_params_mem->bl33_image_info; + SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, + VERSION_1, 0); + + return bl2_to_bl31_params; +} + + +/******************************************************************************* + * This function returns a pointer to the shared memory that the platform + * has kept to point to entry point information of BL31 to BL2 + ******************************************************************************/ +struct entry_point_info *bl2_plat_get_bl31_ep_info(void) +{ + uint32_t modemr; + uint32_t modemr_boot_dev; + int32_t ret; + + modemr = mmio_read_32(RCAR_MODEMR); + modemr_boot_dev = modemr & MODEMR_BOOT_DEV_MASK; + + if (isDdrBackupMode() != 0U) { + + NOTICE("BL2: Skip loading images. (SuspendToRAM)\n"); + + bl31_ep_info->args.arg0 = (unsigned long)bl2_plat_get_bl31_params(); + bl31_ep_info->args.arg1 = 0x00000001UL; /* warm boot */ + bl31_ep_info->pc = (uintptr_t)BL31_BASE; + SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); + bl31_ep_info->spsr = (uint32_t)SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + + /* Flush the params to be passed to memory */ + bl2_plat_flush_bl31_params(); + + /* + * Run BL3-1 via an SMC to BL1. + * Need to jumps entrypoint of Suspend to RAM at SMC handler. + */ + smc((unsigned long)BL1_SMC_RUN_IMAGE, (unsigned long)bl31_ep_info, + 0UL, 0UL, 0UL, 0UL, 0UL, 0UL); + + /* Jump to BL31 (Not come back here) */ + } else { + /* load header */ + if((modemr_boot_dev == MODEMR_BOOT_DEV_EMMC_25X1) || + (modemr_boot_dev == MODEMR_BOOT_DEV_EMMC_50X8)) { + /* boot device is eMMC */ + ret = rcar_dev_init(NULL, EMMC_DEV_ID); + } else { + /* boot device is Flash */ + ret = rcar_dev_init(NULL, FLASH_DEV_ID); + } + if (ret != IO_SUCCESS) { + ERROR("BL2: boot device initialization failed\n"); + panic(); + } + } + + bl31_ep_info->args.arg1 = 0x00000000UL; /* cold boot */ + return bl31_ep_info; +} + +#if (RCAR_LOSSY_ENABLE == 1) +/* Settings for Lossy Decompression */ +#define LOSSY_PARAMS_BASE (0x47FD7000U) + +#define AXI_DCMPAREACRA0 (0xE6784100U) +#define AXI_DCMPAREACRB0 (0xE6784104U) + +#define LOSSY_ENABLE (0x80000000U) +#define LOSSY_DISABLE (0x00000000U) + +#define LOSSY_FMT_YUVPLANAR (0x00000000U) +#define LOSSY_FMT_YUV422INTLV (0x20000000U) +#define LOSSY_FMT_ARGB8888 (0x40000000U) + +/* Settings of Entry 0 */ +#define LOSSY_ST_ADDR0 (0x54000000U) +#define LOSSY_END_ADDR0 (0x57000000U) +#define LOSSY_FMT0 LOSSY_FMT_YUVPLANAR +#define LOSSY_ENA_DIS0 LOSSY_ENABLE + +/* Settings of Entry 1 */ +#define LOSSY_ST_ADDR1 0x0U /* Undefined */ +#define LOSSY_END_ADDR1 0x0U /* Undefined */ +#define LOSSY_FMT1 LOSSY_FMT_ARGB8888 +#define LOSSY_ENA_DIS1 LOSSY_DISABLE + +/* Settings of Entry 2 */ +#define LOSSY_ST_ADDR2 0x0U /* Undefined */ +#define LOSSY_END_ADDR2 0x0U /* Undefined */ +#define LOSSY_FMT2 LOSSY_FMT_YUV422INTLV +#define LOSSY_ENA_DIS2 LOSSY_DISABLE + +static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, + uint64_t end_addr, uint32_t format, uint32_t enable); + +typedef struct bl2_lossy_info { + uint32_t magic; + uint32_t a0; + uint32_t b0; +} bl2_lossy_info_t; + +static void bl2_lossy_setting(uint32_t no, uint64_t start_addr, + uint64_t end_addr, uint32_t format, uint32_t enable) +{ + uint32_t reg; + bl2_lossy_info_t info; + + /* Setting of the start address and format */ + reg = (uint32_t)(format | (start_addr >> 20U)); + mmio_write_32(AXI_DCMPAREACRA0 + (0x8U * (uintptr_t)no), reg); + + /* Setting of the end address */ + mmio_write_32(AXI_DCMPAREACRB0 + (0x8U * (uintptr_t)no), + (uint32_t)(end_addr >> 20U)); + + /* Enable or Disable of Lossy setting */ + mmio_write_32(AXI_DCMPAREACRA0 + (0x8U * (uintptr_t)no), (reg | enable)); + + info.magic = 0x12345678U; + info.a0 = mmio_read_32(AXI_DCMPAREACRA0 + (0x8U * (uintptr_t)no)); + info.b0 = mmio_read_32(AXI_DCMPAREACRB0 + (0x8U * (uintptr_t)no)); + + mmio_write_32(LOSSY_PARAMS_BASE + + (sizeof(bl2_lossy_info_t) * (uintptr_t)no), info.magic); + mmio_write_32(LOSSY_PARAMS_BASE + + (sizeof(bl2_lossy_info_t) * (uintptr_t)no) + 0x4U, info.a0); + mmio_write_32(LOSSY_PARAMS_BASE + + (sizeof(bl2_lossy_info_t) * (uintptr_t)no) + 0x8U, info.b0); + + NOTICE(" Entry %d: DCMPAREACRAx:0x%x DCMPAREACRBx:0x%x\n", no, + mmio_read_32(AXI_DCMPAREACRA0 + (0x8U * (uintptr_t)no)), + mmio_read_32(AXI_DCMPAREACRB0 + (0x8U * (uintptr_t)no))); +} +#endif /* #if (RCAR_LOSSY_ENABLE == 1) */ + +/******************************************************************************* + * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 + * in x0. This memory layout is sitting at the base of the free trusted SRAM. + * Copy it to a safe loaction before its reclaimed by later BL2 functionality. + ******************************************************************************/ +void bl2_early_platform_setup(meminfo_t *mem_layout) +{ + uint32_t reg; + uint32_t lcs; + uint32_t modemr; + uint32_t modemr_boot_dev; + uint32_t board_type; + uint32_t board_rev; + uint32_t prr_val; + char msg[128]; + const char *str; + const char *cpu_ca53 = "CA53"; + const char *product_v3m = "V3M"; + const char *lcs_cm = "CM"; + const char *lcs_dm = "DM"; + const char *lcs_sd = "SD"; + const char *lcs_secure = "SE"; + const char *lcs_fa = "FA"; + const char *boot_hyper160 = "HyperFlash(160MHz)"; + const char *boot_hyper80 = "HyperFlash(80MHz)"; + const char *boot_qspi40 = "QSPI Flash(40MHz)"; + const char *boot_qspi80 = "QSPI Flash(80MHz)"; + const char *unknown = "unknown"; + + modemr = mmio_read_32(RCAR_MODEMR); + modemr_boot_dev = modemr & MODEMR_BOOT_DEV_MASK; + modemr &= MODEMR_BOOT_CPU_MASK; + + /* Initialize CPG configuration */ + bl2_cpg_init(); + + /* Initialize the console to provide early debug support */ + (void)console_init(0U, 0U, 0U); + /* Initialize the GIC driver, cpu and distributor interfaces */ + plat_arm_gic_driver_init(); + plat_arm_gic_init(); + + /* System WDT initialize */ + bl2_swdt_init(); + + /* Enable FIQ interrupt */ + write_daifclr(DAIF_FIQ_BIT); + + /* boot message */ + reg = (uint32_t)read_midr(); + switch (reg & (uint32_t)(MIDR_PN_MASK << MIDR_PN_SHIFT)) { + case MIDR_CA53: + str = cpu_ca53; + break; + default: + str = unknown; + break; + } + (void)sprintf(msg, "BL2: R-Car Gen3 Initial Program Loader(%s) Rev.%s\n" + , str, version_of_renesas); + NOTICE("%s", msg); + + /* R-Car Gen3 product display & check */ + reg = mmio_read_32(RCAR_PRR); + prr_val = reg; + switch (reg & RCAR_PRODUCT_MASK) { + case RCAR_PRODUCT_V3M: + str = product_v3m; + break; + default: + str = unknown; + break; + } + (void)sprintf(msg, "BL2: PRR is R-Car %s Ver%d.%d\n", str, + ((prr_val & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT) + + RCAR_MAJOR_OFFSET, (prr_val & RCAR_MINOR_MASK)); + NOTICE("%s", msg); + + /* Board ID detection */ + (void)get_board_type(&board_type, &board_rev); + + switch (board_type) { + case BOARD_EAGLE: + /* Do nothing. */ + break; + default: + board_type = BOARD_UNKNOWN; + break; + } + + (void)sprintf(msg, "BL2: Board is %s Rev%d.%d\n", + GET_BOARD_NAME(board_type), GET_BOARD_MAJOR(board_rev), + GET_BOARD_MINOR(board_rev)); + NOTICE("%s", msg); + + if((reg & RCAR_PRODUCT_MASK) != TARGET_PRODUCT) { + ERROR("BL2: This IPL has been built for the %s.\n", + TARGET_NAME); + ERROR("BL2: Please write the correct IPL to flash memory.\n"); + panic(); + } + + switch (modemr_boot_dev) { + case MODEMR_BOOT_DEV_HYPERFLASH160: + str = boot_hyper160; + break; + case MODEMR_BOOT_DEV_HYPERFLASH80: + str = boot_hyper80; + break; + case MODEMR_BOOT_DEV_QSPI_FLASH40: + str = boot_qspi40; + break; + case MODEMR_BOOT_DEV_QSPI_FLASH80: + str = boot_qspi80; + break; + default: + str = unknown; + break; + } + (void)sprintf(msg, "BL2: Boot device is %s\n", str); + NOTICE("%s", msg); + + + reg = ROM_GetLcs(&lcs); + if (reg == 0U) { + switch (lcs) { + case LCS_CM: + str = lcs_cm; + break; + case LCS_DM: + str = lcs_dm; + break; + case LCS_SD: + str = lcs_sd; + break; + case LCS_SE: + str = lcs_secure; + break; + case LCS_FA: + str = lcs_fa; + break; + default: + str = unknown; + break; + } + } else { + str = unknown; + } + (void)sprintf(msg, "BL2: LCM state is %s\n", str); + NOTICE("%s", msg); + + /* Save BKUP_TRG for SuspendToRAM */ + (void)isDdrBackupMode(); + + /* Setup the BL2 memory layout */ + bl2_tzram_layout = *mem_layout; + + /* Initialize RPC */ + initRPC(); + + /* Initialize DMA */ + initDMA(); + + /* unmask the detection of RWDT overflow */ + reg = mmio_read_32(RST_WDTRSTCR); + reg &= ~WDTRSTCR_RWDT_RSTMSK; + reg |= WDTRSTCR_PASSWORD; + mmio_write_32(RST_WDTRSTCR, reg); + + /* Release CPG write protect */ + mmio_write_32(CPG_CPGWPR, CPGWPR_PASSWORD); + mmio_write_32(CPG_CPGWPCR, CPGWPCR_PASSWORD); + + /* CA5x debug resource control */ + mmio_write_32(CPG_CA53DBGRCR, + DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); + +#if (RCAR_LOSSY_ENABLE == 1) + NOTICE("BL2: Lossy Decomp areas\n"); + /* Lossy setting : entry 0 */ + bl2_lossy_setting(0U, LOSSY_ST_ADDR0, LOSSY_END_ADDR0, + LOSSY_FMT0, LOSSY_ENA_DIS0); + + /* Lossy setting : entry 1 */ + bl2_lossy_setting(1U, LOSSY_ST_ADDR1, LOSSY_END_ADDR1, + LOSSY_FMT1, LOSSY_ENA_DIS1); + + /* Lossy setting : entry 2 */ + bl2_lossy_setting(2U, LOSSY_ST_ADDR2, LOSSY_END_ADDR2, + LOSSY_FMT2, LOSSY_ENA_DIS2); +#endif /* #if (RCAR_LOSSY_ENABLE == 1) */ + + rcar_io_setup(); +} + +/******************************************************************************* + * Get DDR Backup Mode from GPIO + * BKUP_TRG(IO port A8, GPIO GP-0-8): LOW=Cold boot, HIGH=Warm boot + * return: uint8_t + * 0: DDR is not backup mode. + * 1: DDR is backup mode. + ******************************************************************************/ +static uint32_t isDdrBackupMode(void) +{ +#if (PMIC_ON_BOARD==1) + static uint32_t backupTriggerOnce = 1U; + static uint32_t backupTrigger = 0U; + if (backupTriggerOnce == 1U) { + backupTriggerOnce = 0U; + /* Read and return BKUP_TRG(IO port B8, GPIO GP-1-8) */ + if ((mmio_read_32((uintptr_t)GPIO_INDT1) & BIT8) != 0U) { + backupTrigger = 1U; + } + } + return backupTrigger; +#else /* (PMIC_ON_BOARD==1) */ + return 0U; /* Cold boot only */ +#endif /* (PMIC_ON_BOARD==1) */ +} + +/******************************************************************************* + * Perform platform specific setup. For now just initialize the memory location + * to use for passing arguments to BL31. + ******************************************************************************/ +void bl2_platform_setup(void) +{ + /* + * Do initial security configuration to allow DRAM/device access. On + * Base RCAR only DRAM security is programmable (via TrustZone), but + * other platforms might have more programmable security devices + * present. + */ + + /* IPMMU-MM setting for linux */ + mmio_write_32(IPMMUMM_SYSCTRL, 0xC0000000U); + mmio_write_32(IPMMUMM_SYSAUX, 0x01000000U); +} + +/* Flush the TF params and the TF plat params */ +void bl2_plat_flush_bl31_params(void) +{ + uint32_t val; + + val = mmio_read_32(RCAR_MODEMR); + + /* Disable MFIS write protection */ + mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 0x1U); + + /* disable the System WDT, FIQ and GIC */ + bl2_swdt_release(); + + /* Finalize a console of provide early debug support */ + console_finalize(); + + /* Initialize the System Module stop registers */ + bl2_system_cpg_init(); + + /* Disable instruction cache */ + val = (uint32_t)read_sctlr_el1(); + val &= ~((uint32_t)SCTLR_I_BIT); + write_sctlr_el1((uint64_t)val); + isb(); + + /* Invalidate instruction cache */ + iciallu(); + dsb(); + isb(); +} + + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the mmu in a quick and dirty way. + ******************************************************************************/ +void bl2_plat_arch_setup(void) +{ +#if 0 + rcar_configure_mmu_el1(bl2_tzram_layout.total_base, + bl2_tzram_layout.total_size, + BL2_RO_BASE, + BL2_RO_LIMIT +#if USE_COHERENT_MEM + , BL2_COHERENT_RAM_BASE, + BL2_COHERENT_RAM_LIMIT +#endif + ); +#endif +} + +/******************************************************************************* + * Before calling this function BL31 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL31 and set SPSR and security state. + * On RCAR we are only setting the security state, entrypoint + ******************************************************************************/ +void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, + entry_point_info_t *bl31_ep_info) +{ + SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); + bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); +} + + +/******************************************************************************* + * Before calling this function BL32 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL32 and set SPSR and security state. + * On RCAR we are only setting the security state, entrypoint + ******************************************************************************/ +void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, + entry_point_info_t *bl32_ep_info) +{ + SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); + bl32_ep_info->spsr = rcar_get_spsr_for_bl32_entry(); +} + +/******************************************************************************* + * Before calling this function BL33 is loaded in memory and its entrypoint + * is set by load_image. This is a placeholder for the platform to change + * the entrypoint of BL33 and set SPSR and security state. + * On RCAR we are only setting the security state, entrypoint + ******************************************************************************/ +void bl2_plat_set_bl33_ep_info(image_info_t *image, + entry_point_info_t *bl33_ep_info) +{ + SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); + bl33_ep_info->spsr = rcar_get_spsr_for_bl33_entry(); +} + + +/******************************************************************************* + * Populate the extents of memory available for loading BL32 + ******************************************************************************/ +#ifdef BL32_BASE +void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) +{ + /* + * Populate the extents of memory available for loading BL32. + */ + bl32_meminfo->total_base = BL32_BASE; + bl32_meminfo->free_base = BL32_BASE; + bl32_meminfo->total_size = BL32_BASE; + bl32_meminfo->free_size = BL32_LIMIT - BL32_BASE; +} +#endif + +/******************************************************************************* + * Populate the extents of memory available for loading BL33 + ******************************************************************************/ +void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) +{ + /* Non-secure target programs loading area limit is 40-bits address. */ + bl33_meminfo->total_base = DRAM1_NS_BASE; + bl33_meminfo->total_size = DRAM_LIMIT - DRAM1_NS_BASE; + bl33_meminfo->free_base = AARCH64_SPACE_BASE; + bl33_meminfo->free_size = AARCH64_SPACE_SIZE; +} + +void bl2_init_generic_timer(void) +{ + uint32_t modemr; + uint32_t modemr_pll; + uint32_t pll_table[] = { 8333300U, /* MD14/MD13 : 0b00 */ + 10000000U, /* MD14/MD13 : 0b01 */ + 12500000U, /* MD14/MD13 : 0b10 */ + 16666600U}; /* MD14/MD13 : 0b11 */ + uint32_t reg_cntfid; + + modemr = mmio_read_32(RCAR_MODEMR); + modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK); + + /* Set frequency data in CNTFID0 */ + reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; + + /* Update memory mapped and register based freqency */ + write_cntfrq_el0((u_register_t )reg_cntfid); + mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); + /* Enable counter */ + mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF, + (uint32_t)CNTCR_EN); +} + + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/bl31_rcar_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/bl31_rcar_setup.c new file mode 100644 index 0000000..7bc4a18 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/bl31_rcar_setup.c @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "drivers/pwrc/rcar_pwrc.h" +#include "rcar_def.h" +#include "rcar_private.h" +#include "rcar_version.h" + +/******************************************************************************* + * Declarations of linker defined symbols which will help us find the layout + * of trusted SRAM + ******************************************************************************/ +extern unsigned long __RO_START__; +extern unsigned long __RO_END__; +extern unsigned long __BL31_END__; + +#if USE_COHERENT_MEM +extern unsigned long __COHERENT_RAM_START__; +extern unsigned long __COHERENT_RAM_END__; +#endif + +/* + * The next 3 constants identify the extents of the code, RO data region and the + * limit of the BL3-1 image. These addresses are used by the MMU setup code and + * therefore they must be page-aligned. It is the responsibility of the linker + * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_RO_BASE (uint64_t)(&__RO_START__) +#define BL31_RO_LIMIT (uint64_t)(&__RO_END__) +#define BL31_END (uint64_t)(&__BL31_END__) + +#if USE_COHERENT_MEM +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_COHERENT_RAM_BASE (uint64_t)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (uint64_t)(&__COHERENT_RAM_END__) +#endif + +/******************************************************************************* + * Reference to structure which holds the arguments that have been passed to + * BL31 from BL2. + ******************************************************************************/ +static bl31_params_t *bl2_to_bl31_params; + +uint32_t rcar_boot_kind_flag __attribute__((section("data"))); + +static uint64_t rcar_boot_mpidr; + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for the + * security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + next_image_info = + (type == NON_SECURE) ? + bl2_to_bl31_params->bl33_ep_info : + bl2_to_bl31_params->bl32_ep_info; + + /* None of the images on this platform can have 0x0 as the entrypoint */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +/******************************************************************************* + * Perform any BL31 specific platform actions. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2) before they + * are lost (potentially). This needs to be done before the MMU is initialized + * so that the memory layout can be used while creating page tables. On the RCAR + * we know that BL2 has populated the parameters. So we just use + * the reference passed in 'from_bl2' instead of copying. The 'data' parameter + * is not used since all the information is contained in 'from_bl2'. Also, BL2 + * has flushed this information to memory, so we are guaranteed to pick up good + * data + ******************************************************************************/ +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +{ + /* Initialize the log area to provide early debug support */ + console_init(1U, 0U, 0U); + + NOTICE("BL3-1 : Rev.%s\n",version_of_renesas); + + /* Check params passed from BL2 should not be NULL, + */ + if ((NULL == from_bl2) || ((uint8_t)PARAM_BL31 != from_bl2->h.type) || + ((uint8_t)VERSION_1 > from_bl2->h.version)) { + panic(); + } + + bl2_to_bl31_params = from_bl2; + +} + +/******************************************************************************* + * Initialize the gic, configure the CLCD and zero out variables needed by the + * secondaries to boot up correctly. + ******************************************************************************/ +void bl31_platform_setup(void) +{ + + /* Initialize the GIC driver, cpu and distributor interfaces */ + plat_arm_gic_driver_init(); + plat_arm_gic_init(); + + /* Enable and initialize the System level generic timer */ + mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); + + /* Intialize the power controller */ + rcar_pwrc_setup(); + + /* Topologies are best known to the platform. */ + rcar_setup_topology(); + + /* Get the mpidr for boot cpu */ + rcar_boot_mpidr = read_mpidr_el1() & 0x0000ffffU; +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the mmu in a quick and dirty way. + ******************************************************************************/ +void bl31_plat_arch_setup(void) +{ + rcar_configure_mmu_el3(BL31_RO_BASE, (BL31_END - BL31_RO_BASE), + BL31_RO_BASE, + BL31_RO_LIMIT +#if USE_COHERENT_MEM + , BL31_COHERENT_RAM_BASE, + BL31_COHERENT_RAM_LIMIT +#endif + ); + +} + +/******************************************************************************* + * There check whether duplication of physical address is valid or not. + ******************************************************************************/ +uint32_t bl31_plat_mmu_pa_chk(uint32_t pa_flg, uintptr_t chk_va, uint64_t chk_pa) +{ + if ((DEVICE_SRAM_SHADOW_BASE == chk_va) && + (DEVICE_SRAM_BASE_U == chk_pa)) { + pa_flg = 1U; + } + return pa_flg; +} + +/******************************************************************************* + * Instead of svc_migrate_info in RCAR. + * returned PSCI_TOS_NOT_UP_MIG_CAP and boot MPIDR. + ******************************************************************************/ +uint32_t bl31_plat_cpu_migrate_info(u_register_t *resident_cpu) +{ + *resident_cpu = rcar_boot_mpidr; + return (uint32_t)PSCI_TOS_NOT_UP_MIG_CAP; +} + +/******************************************************************************* + * There check whether CPU_OFF is OK or not. + ******************************************************************************/ +int32_t bl31_plat_denied_cpu_off_chk(void) +{ + int32_t rc = PSCI_E_SUCCESS; + uint64_t tmp_mpidr; + + tmp_mpidr = read_mpidr_el1() & 0x0000ffffU; + + if (tmp_mpidr == rcar_boot_mpidr) { + rc = PSCI_E_DENIED; + } + return rc; +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/auth/rcarboot.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/auth/rcarboot.c new file mode 100644 index 0000000..20e7e72 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/auth/rcarboot.c @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include +#include +#include +#include +#include + +#include "rcarboot.h" +#include "rom_api.h" + +#define RCAR_IMAGE_ID_MAX (10) +#define RCAR_CERT_MAGIC_NUM (0xE291F358U) +#define RCAR_BOOT_KEY_CERT (0xE6300C00U) +#define RCAR_BOOT_KEY_CERT_NEW (0xE6300F00U) +#define RST_BASE (0xE6160000U) +#define RST_MODEMR (RST_BASE + 0x0060U) +#define MFISSOFTMDR (0xE6260600U) /* SOFTMD register */ + +static SECURE_BOOT_API sbrom_SecureBootAPI; + +static int32_t local_verify(uint32_t a, uint32_t b, void *c); + +/* + * Return the parent id in the output parameter '*parent_id' + * + * Return value: + * 0 = Image has parent, 1 = Image has no parent or parent is authenticated + */ +int auth_mod_get_parent_id(unsigned int img_id, unsigned int *parent_id) +{ + return 1; +} + +/* + * Authenticate a certificate/image + * + * Return: 0 = success, Otherwise = error + */ +int auth_mod_verify_img(unsigned int img_id, void *img_ptr, + unsigned int img_len) +{ + int32_t ret = 0; + uint32_t cert_addr = 0U; + int32_t index = 0; + static const struct img_to_cert_t { + uint32_t image_id; + int32_t cert_id; + const char *image_name; + } img_to_cert[RCAR_IMAGE_ID_MAX] = { + { + (uint32_t)BL31_IMAGE_ID, + (int32_t)SOC_FW_CONTENT_CERT_ID, + "BL31" + }, + { + (uint32_t)BL32_IMAGE_ID, + (int32_t)TRUSTED_OS_FW_CONTENT_CERT_ID, + "BL32" + }, + { + (uint32_t)BL33_IMAGE_ID, + (int32_t)NON_TRUSTED_FW_CONTENT_CERT_ID, + "BL33" + }, + { + (uint32_t)BL332_IMAGE_ID, + (int32_t)BL332_CERT_ID, + "BL332" + }, + { + (uint32_t)BL333_IMAGE_ID, + (int32_t)BL333_CERT_ID, + "BL333" + }, + { + (uint32_t)BL334_IMAGE_ID, + (int32_t)BL334_CERT_ID, + "BL334" + }, + { + (uint32_t)BL335_IMAGE_ID, + (int32_t)BL335_CERT_ID, + "BL335" + }, + { + (uint32_t)BL336_IMAGE_ID, + (int32_t)BL336_CERT_ID, + "BL336" + }, + { + (uint32_t)BL337_IMAGE_ID, + (int32_t)BL337_CERT_ID, + "BL337" + }, + { + (uint32_t)BL338_IMAGE_ID, + (int32_t)BL338_CERT_ID, + "BL338" + }, + }; + + switch (img_id) { +#if IMAGE_BL2 + case (uint32_t)TRUSTED_KEY_CERT_ID: + case (uint32_t)SOC_FW_KEY_CERT_ID: + case (uint32_t)TRUSTED_OS_FW_KEY_CERT_ID: + case (uint32_t)NON_TRUSTED_FW_KEY_CERT_ID: + case (uint32_t)BL332_KEY_CERT_ID: + case (uint32_t)BL333_KEY_CERT_ID: + case (uint32_t)BL334_KEY_CERT_ID: + case (uint32_t)BL335_KEY_CERT_ID: + case (uint32_t)BL336_KEY_CERT_ID: + case (uint32_t)BL337_KEY_CERT_ID: + case (uint32_t)BL338_KEY_CERT_ID: + case (uint32_t)SOC_FW_CONTENT_CERT_ID: + case (uint32_t)TRUSTED_OS_FW_CONTENT_CERT_ID: + case (uint32_t)NON_TRUSTED_FW_CONTENT_CERT_ID: + case (uint32_t)BL332_CERT_ID: + case (uint32_t)BL333_CERT_ID: + case (uint32_t)BL334_CERT_ID: + case (uint32_t)BL335_CERT_ID: + case (uint32_t)BL336_CERT_ID: + case (uint32_t)BL337_CERT_ID: + case (uint32_t)BL338_CERT_ID: + /* no check */ + break; + case (uint32_t)BL31_IMAGE_ID: + case (uint32_t)BL32_IMAGE_ID: + case (uint32_t)BL33_IMAGE_ID: + case (uint32_t)BL332_IMAGE_ID: + case (uint32_t)BL333_IMAGE_ID: + case (uint32_t)BL334_IMAGE_ID: + case (uint32_t)BL335_IMAGE_ID: + case (uint32_t)BL336_IMAGE_ID: + case (uint32_t)BL337_IMAGE_ID: + case (uint32_t)BL338_IMAGE_ID: + { + for (index = 0; index < RCAR_IMAGE_ID_MAX; index++) { + if (img_id == img_to_cert[index].image_id) { + ret = file_to_cert( + img_to_cert[index].cert_id, + &cert_addr); + break; + } + } + if (RCAR_IMAGE_ID_MAX == index) { + ERROR("Verification Failed!!! (%s)\n", + "Unknown img_id !"); + break; + } + if (0 == ret) { + if (RCAR_CERT_MAGIC_NUM == + mmio_read_32((uint64_t)RCAR_BOOT_KEY_CERT_NEW)) { + ret = sbrom_SecureBootAPI( + RCAR_BOOT_KEY_CERT_NEW, + cert_addr, NULL); + } else { + ret = sbrom_SecureBootAPI( + RCAR_BOOT_KEY_CERT, + cert_addr, NULL); + } + if (0 != ret) { + ERROR( + "Verification Failed!!! 0x%x -> %s\n", + ret, + img_to_cert[index].image_name); + } + } + } + break; +#endif /* IMAGE_BL2 */ + default: + ret = -1; + break; + } + + return ret; +} + +static int32_t local_verify(uint32_t a, uint32_t b, void *c) +{ + return 0; +} + +/* + * Initialize the different modules in the authentication framework + */ +void auth_mod_init(void) +{ +#if RCAR_SECURE_BOOT + uint32_t lcs; + uint32_t md = (mmio_read_32(RST_MODEMR) & 0x00000020U) >> 5; + uint32_t softmd = (mmio_read_32(MFISSOFTMDR) & 0x00000001U); + uint32_t ret; + + /* default is Secure boot */ + sbrom_SecureBootAPI = (SECURE_BOOT_API)&ROM_SecureBootAPI; + + ret = ROM_GetLcs(&lcs); + if (ret != 0U) { + ERROR("BL2: Failed to get the LCS. (%d)\n", ret); + panic(); + } + if (lcs == LCS_SE) { + /* LCS=Secure */ + if (softmd == 0x1U) { + /* LCS=Secure + Normal boot (temp setting) */ + sbrom_SecureBootAPI = &local_verify; + } + /* else is LCS=Secure + Secure boot */ + } else if (lcs == LCS_SD) { + /* LCS=SD */ + sbrom_SecureBootAPI = &local_verify; + } else { + if (md != 0U) { + /* MD5=1 => LCS=CM/DM/SD/RMA + Normal boot */ + sbrom_SecureBootAPI = &local_verify; + } + /* else is MD5=0 => LCS=CM/DM/SD/RMA + Secure boot */ + } + + if (sbrom_SecureBootAPI == &local_verify) { + NOTICE("BL2: Normal boot\n"); + } else { + NOTICE("BL2: Secure boot\n"); + } +#else + sbrom_SecureBootAPI = &local_verify; + NOTICE("BL2: Normal boot\n"); +#endif +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/auth/rcarboot.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/auth/rcarboot.h new file mode 100644 index 0000000..2d015ca --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/auth/rcarboot.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_RCARBOOT_H_ +#define RCAR_RCARBOOT_H_ + +/* Define */ +typedef int32_t (*SECURE_BOOT_API)(uint32_t a, uint32_t b, void *c); + +/* Prototype */ +extern int32_t file_to_cert(const int32_t filename, uint32_t *cert_addr); + +#endif /* RCAR_RCARBOOT_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/avs/avs_driver.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/avs/avs_driver.c new file mode 100644 index 0000000..dc0ff8e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/avs/avs_driver.c @@ -0,0 +1,648 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "bl2_cpg_init.h" +#include "bl2_cpg_register.h" +#include "avs_driver.h" +#include "rcar_def.h" + +#if (AVS_SETTING_ENABLE==1) +#if (PMIC_ON_BOARD==1) +/* Read PMIC register for debug. 1:enable / 0:disable */ +#define AVS_READ_PMIC_REG_ENABLE 0 +/* The re-try number of times of the AVS setting. */ +#define AVS_RETRY_NUM (1U) + +/* Base address of ADVFS Module registers*/ +#define ADVFS_BASE (0xE60A0000U) +/* Register address in eFuse indicates individual R-Car information */ +#define ADVFS_KSEN_ADJCNTS (ADVFS_BASE + 0x013CU) + +/* Mask VOLCOND bit in KSEN_ADJCNTS registers */ +#define KSEN_ADJCNTS_VOLCOND_MASK (0x0000000FU) +#define VOLCOND_INVALID_VAL (0x7U) /* Invalid value */ +#define VOLCOND_CANCEL_BIT (0x8U) /* Cancel bit */ + +/* Mode Monitor Register */ +#define RCAR_MODEMR (0xE6160060U) /* Mode pin register */ + +/* I2C for DVFS bit in CPG registers for module standby and software reset*/ +#define CPG_SYS_DVFS_BIT (0x04000000U) +/* ADVFS Module bit in CPG registers for module standby and software reset*/ +#define CPG_SYS_ADVFS_BIT (0x02000000U) + +/* Base address of IICDVFS registers*/ +#define IIC_DVFS_BASE (0xE60B0000U) +/* IIC bus data register */ +#define IIC_ICDR (IIC_DVFS_BASE + 0x0000U) +/* IIC bus control register */ +#define IIC_ICCR (IIC_DVFS_BASE + 0x0004U) +/* IIC bus status register */ +#define IIC_ICSR (IIC_DVFS_BASE + 0x0008U) +/* IIC interrupt control register */ +#define IIC_ICIC (IIC_DVFS_BASE + 0x000CU) +/* IIC clock control register low */ +#define IIC_ICCL (IIC_DVFS_BASE + 0x0010U) +/* IIC clock control register high */ +#define IIC_ICCH (IIC_DVFS_BASE + 0x0014U) + +/* Bit in ICSR register */ +#define ICSR_BUSY (0x10U) +#define ICSR_AL (0x08U) +#define ICSR_TACK (0x04U) +#define ICSR_WAIT (0x02U) +#define ICSR_DTE (0x01U) + +/* Bit in ICIC register */ +#define ICIC_TACKE (0x04U) +#define ICIC_WAITE (0x02U) +#define ICIC_DTEE (0x01U) + +/* I2C bus interface enable */ +#define ICCR_ENABLE (0x80U) +/* Start condition */ +#define ICCR_START (0x94U) +/* Stop condition */ +#define ICCR_STOP (0x90U) +/* Restart condition with change to receive mode change */ +#define ICCR_START_RECV (0x81U) +/* Stop condition for receive mode */ +#define ICCR_STOP_RECV (0xC0U) + +/* Low-level period of SCL */ +#define ICCL_FREQ_8p33M (0x07U) /* for CP Phy 8.3333MHz */ +#define ICCL_FREQ_10M (0x09U) /* for CP Phy 10MHz */ +#define ICCL_FREQ_12p5M (0x0BU) /* for CP Phy 12.5MHz */ +#define ICCL_FREQ_16p66M (0x0EU) /* for CP Phy 16.6666MHz */ +/* High-level period of SCL */ +#define ICCH_FREQ_8p33M (0x01U) /* for CP Phy 8.3333MHz */ +#define ICCH_FREQ_10M (0x02U) /* for CP Phy 10MHz */ +#define ICCH_FREQ_12p5M (0x03U) /* for CP Phy 12.5MHz */ +#define ICCH_FREQ_16p66M (0x05U) /* for CP Phy 16.6666MHz */ + +#define PMIC_W_SLAVE_ADDRESS (0x60U) /* PMIC slave address + (W) */ +#define PMIC_R_SLAVE_ADDRESS (0x61U) /* PMIC slave address + (R) */ +#define PMIC_DVFS_SETVID (0x54U) /* PMIC DVFS SetVID register */ + +/* Individual information */ +#define EFUSE_AVS0 (0U) +#define EFUSE_AVS_NUM (7U) +static const uint8_t pmic_setvid_reg[EFUSE_AVS_NUM] = { + 0x52U, /* AVS0 0.82V */ + 0x52U, /* AVS1 0.82V */ + 0x52U, /* AVS2 0.82V */ + 0x4FU, /* AVS3 0.79V */ + 0x4FU, /* AVS4 0.79V */ + 0x4DU, /* AVS5 0.77V */ + 0x4BU /* AVS6 0.75V */ +}; + +/* Kind of AVS settings status */ +typedef enum +{ + avs_status_none = 0, + avs_status_init, + avs_status_start_condition, + avs_status_set_slave_addr, + avs_status_write_reg_addr, + avs_status_write_reg_data, + avs_status_stop_condition, + avs_status_end, + avs_status_complete, + avs_status_al_start, + avs_status_al_transfer, + avs_status_nack, + avs_status_error_stop, + ave_status_error_end +} avs_status_t; + +/* Kind of AVS error */ +typedef enum +{ + avs_error_none = 0, + avs_error_al, + avs_error_nack +} avs_error_t; + +static avs_status_t avs_status = avs_status_none; +static uint32_t avs_retry = 0U; +static uint32_t efuse_avs = EFUSE_AVS0; + +/* prototype */ +static avs_error_t avs_check_error(void); +static void avs_set_iic_clock(void); +#if AVS_READ_PMIC_REG_ENABLE == 1 +static uint8_t avs_read_pmic_reg(uint8_t addr); +static void avs_poll(uint8_t bit_pos, uint8_t val); +#endif +#endif /* (PMIC_ON_BOARD==1) */ +#endif /* (AVS_SETTING_ENABLE==1) */ + +/* + * Initialize to enable the AVS setting. + */ +void bl2_avs_init(void) +{ +#if (AVS_SETTING_ENABLE==1) +#if (PMIC_ON_BOARD==1) + uint32_t val; + uint32_t mstp; + + /* Initialize AVS status */ + avs_status = avs_status_init; + + /* Bit of the module which wants to enable clock supply. */ + mstp = CPG_SYS_DVFS_BIT | CPG_SYS_ADVFS_BIT; + /* Enables the clock supply to the CPG. */ + cpg_write(CPG_SMSTPCR9, mmio_read_32(CPG_SMSTPCR9) & (~mstp)); + /* Is the clock supply to the CPG disabled ? */ + while((mmio_read_32(CPG_MSTPSR9) & mstp) != 0U) { + /* Enables the clock supply to the CPG. */ + cpg_write(CPG_SMSTPCR9, + mmio_read_32(CPG_SMSTPCR9) & (~mstp)); + } + + /* Disable I2C module and All internal registers initialized. */ + mmio_write_8(IIC_ICCR, 0x00U); + while ((mmio_read_8(IIC_ICCR) & ICCR_ENABLE) != 0U) { + /* Disable I2C module and All internal registers initialized. */ + mmio_write_8(IIC_ICCR, 0x00U); + } + + /* Read eFuse indicates individual R-Car information */ + val = mmio_read_32(ADVFS_KSEN_ADJCNTS) & KSEN_ADJCNTS_VOLCOND_MASK; + + if ((val == VOLCOND_INVALID_VAL) + || ((val & VOLCOND_CANCEL_BIT) == VOLCOND_CANCEL_BIT)) { + efuse_avs = EFUSE_AVS0; + } else { + efuse_avs = val; + } + + /* Set next status */ + avs_status = avs_status_start_condition; + +#endif /* (PMIC_ON_BOARD==1) */ +#endif /* (AVS_SETTING_ENABLE==1) */ +} + +/* + * Set the value of register corresponding to the voltage + * by transfer of I2C to PIMC. + */ +void bl2_avs_setting(void) +{ +#if (AVS_SETTING_ENABLE==1) +#if (PMIC_ON_BOARD==1) + avs_error_t err; + + switch (avs_status) { + case avs_status_start_condition: + /* Set ICCR.ICE=1 to activate the I2C module. */ + mmio_write_8(IIC_ICCR, mmio_read_8(IIC_ICCR) | ICCR_ENABLE); + /* Set frequency of 400kHz */ + avs_set_iic_clock(); + /* Set ICIC.TACKE=1, ICIC.WAITE=1, ICIC.DTEE=1 to */ + /* enable interrupt control. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) + | ICIC_TACKE | ICIC_WAITE | ICIC_DTEE); + /* Write H'94 in ICCR to issue start condition */ + mmio_write_8(IIC_ICCR, ICCR_START); + /* Set next status */ + avs_status = avs_status_set_slave_addr; + break; + case avs_status_set_slave_addr: + /* Check error. */ + err = avs_check_error(); + if (err == avs_error_al) { + /* Recovery sequence of just after start. */ + avs_status = avs_status_al_start; + } else if (err == avs_error_nack) { + /* Recovery sequence of detected NACK */ + avs_status = avs_status_nack; + } else { + /* Was data transmission enabled ? */ + if ((mmio_read_8(IIC_ICSR) & ICSR_DTE) == ICSR_DTE) { + /* Clear ICIC.DTEE to disable a DTE interrupt */ + mmio_write_8(IIC_ICIC, + mmio_read_8(IIC_ICIC) + & (uint8_t)(~ICIC_DTEE)); + /* Send PMIC slave address + (W) */ + mmio_write_8(IIC_ICDR, PMIC_W_SLAVE_ADDRESS); + /* Set next status */ + avs_status = avs_status_write_reg_addr; + } + } + break; + case avs_status_write_reg_addr: + /* Check error. */ + err = avs_check_error(); + if (err == avs_error_al) { + /* Recovery sequence of during data transfer. */ + avs_status = avs_status_al_transfer; + } else if (err == avs_error_nack) { + /* Recovery sequence of detected NACK */ + avs_status = avs_status_nack; + } else { + /* If wait state after data transmission. */ + if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) { + /* Write PMIC DVFS_SetVID address */ + mmio_write_8(IIC_ICDR, PMIC_DVFS_SETVID); + /* Clear ICSR.WAIT to exit from wait state. */ + mmio_write_8(IIC_ICSR, + mmio_read_8(IIC_ICSR) + & (uint8_t)(~ICSR_WAIT)); + /* Set next status */ + avs_status = avs_status_write_reg_data; + } + } + break; + case avs_status_write_reg_data: + /* Check error. */ + err = avs_check_error(); + if (err == avs_error_al) { + /* Recovery sequence of during data transfer. */ + avs_status = avs_status_al_transfer; + } else if (err == avs_error_nack) { + /* Recovery sequence of detected NACK */ + avs_status = avs_status_nack; + } else { + /* If wait state after data transmission. */ + if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) { + /* Dose efuse_avs exceed the number of */ + /* the tables? */ + if (efuse_avs >= EFUSE_AVS_NUM) { + ERROR("BL2: AVS number of eFuse is out " + "of a range. number=%u\n", + efuse_avs); + /* Infinite loop */ + panic(); + } + /* Write PMIC DVFS_SetVID value */ + mmio_write_8(IIC_ICDR, + pmic_setvid_reg[efuse_avs]); + /* Clear ICSR.WAIT to exit from wait state. */ + mmio_write_8(IIC_ICSR, + mmio_read_8(IIC_ICSR) + & (uint8_t)(~ICSR_WAIT)); + /* Set next status */ + avs_status = avs_status_stop_condition; + } + } + break; + case avs_status_stop_condition: + err = avs_check_error(); + if (err == avs_error_al) { + /* Recovery sequence of during data transfer. */ + avs_status = avs_status_al_transfer; + } else if (err == avs_error_nack) { + /* Recovery sequence of detected NACK */ + avs_status = avs_status_nack; + } else { + /* If wait state after data transmission. */ + if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) { + /* Write H'90 in ICCR to issue stop condition */ + mmio_write_8(IIC_ICCR, ICCR_STOP); + /* Clear ICSR.WAIT to exit from wait state. */ + mmio_write_8(IIC_ICSR, + mmio_read_8(IIC_ICSR) + & (uint8_t)(~ICSR_WAIT)); + /* Set next status */ + avs_status = avs_status_end; + } + } + break; + case avs_status_end: + /* Is this module not busy?. */ + if ((mmio_read_8(IIC_ICSR) & ICSR_BUSY) == 0U) { + /* Set ICCR=H'00 to disable the I2C module. */ + mmio_write_8(IIC_ICCR, 0x00U); + /* Set next status */ + avs_status = avs_status_complete; + } + break; + case avs_status_al_start: + /* Clear ICSR.AL bit */ + mmio_write_8(IIC_ICSR, + (mmio_read_8(IIC_ICSR) + & (uint8_t)(~ICSR_AL))); + /* Transmit a clock pulse */ + mmio_write_8(IIC_ICDR, pmic_setvid_reg[EFUSE_AVS0]); + /* Set next status */ + avs_status = avs_status_error_stop; + break; + case avs_status_al_transfer: + /* Clear ICSR.AL bit */ + mmio_write_8(IIC_ICSR, + (mmio_read_8(IIC_ICSR) + & (uint8_t)(~ICSR_AL))); + /* Set next status */ + avs_status = avs_status_error_stop; + break; + case avs_status_nack: + /* Write H'90 in ICCR to issue stop condition */ + mmio_write_8(IIC_ICCR, ICCR_STOP); + /* Disable a WAIT and DTEE interrupt. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) + & (uint8_t)(~(ICIC_WAITE | ICIC_DTEE))); + /* Clear ICSR.TACK bit */ + mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) + & (uint8_t)(~ICSR_TACK)); + /* Set next status */ + avs_status = ave_status_error_end; + break; + case avs_status_error_stop: + /* If wait state after data transmission. */ + if ((mmio_read_8(IIC_ICSR) & ICSR_WAIT) == ICSR_WAIT) { + /* Write H'90 in ICCR to issue stop condition */ + mmio_write_8(IIC_ICCR, ICCR_STOP); + /* Clear ICSR.WAIT to exit from wait state. */ + mmio_write_8(IIC_ICSR, + mmio_read_8(IIC_ICSR) + & (uint8_t)(~ICSR_WAIT)); + /* Set next status */ + avs_status = ave_status_error_end; + } + break; + case ave_status_error_end: + /* Is this module not busy?. */ + if ((mmio_read_8(IIC_ICSR) & ICSR_BUSY) == 0U) { + /* Set ICCR=H'00 to disable the I2C module. */ + mmio_write_8(IIC_ICCR, 0x00U); + /* Increment the re-try number of times. */ + avs_retry++; + /* Set start a re-try to status. */ + avs_status = avs_status_start_condition; + } + break; + case avs_status_complete: + /* After "avs_status" became the "avs_status_complete", */ + /* "bl2_avs_setting()" function may be called. */ + break; + default: + /* This case is not possible. */ + ERROR("BL2: AVS setting is in invalid status. status=%u\n", + avs_status); + /* Infinite loop */ + panic(); + break; + } +#endif /* (PMIC_ON_BOARD==1) */ +#endif /* (AVS_SETTING_ENABLE==1) */ +} + +/* + * Finish the AVS setting. + */ +void bl2_avs_end(void) +{ +#if (AVS_SETTING_ENABLE==1) +#if (PMIC_ON_BOARD==1) + uint32_t mstp; + + /* While status is not completion, be repeated. */ + while (avs_status != avs_status_complete) { + bl2_avs_setting(); + } + NOTICE("BL2: AVS setting succeeded. DVFS_SetVID=0x%x\n", + pmic_setvid_reg[efuse_avs]); + +#if AVS_READ_PMIC_REG_ENABLE == 1 + { + uint8_t addr = PMIC_DVFS_SETVID; + uint8_t value; + value = avs_read_pmic_reg(addr); + NOTICE("BL2: Read PMIC register. address=0x%x value=0x%x \n", + addr, value); + } +#endif + + /* Bit of the module which wants to disable clock supply. */ + mstp = CPG_SYS_DVFS_BIT | CPG_SYS_ADVFS_BIT; + /* Disables the supply of clock signal to a module. */ + cpg_write(CPG_SMSTPCR9, + mmio_read_32(CPG_SMSTPCR9) | mstp); +#endif /* (PMIC_ON_BOARD==1) */ +#endif /* (AVS_SETTING_ENABLE==1) */ +} + +#if (AVS_SETTING_ENABLE==1) +#if (PMIC_ON_BOARD==1) +/* + * Check error and judge re-try. + */ +static avs_error_t avs_check_error(void) +{ + avs_error_t ret; + + if ((mmio_read_8(IIC_ICSR) & ICSR_AL) == ICSR_AL) { + NOTICE("BL2: Loss of arbitration is detected. " + "AVS status=%d Retry=%u\n", + avs_status, avs_retry); + /* Check of retry number of times*/ + if (avs_retry >= AVS_RETRY_NUM) { + ERROR("BL2: AVS setting failed in retry. max=%u\n", + AVS_RETRY_NUM); + /* Infinite loop */ + panic(); + } + /* Set the error detected to error status. */ + ret = avs_error_al; + } else if ((mmio_read_8(IIC_ICSR) & ICSR_TACK) == ICSR_TACK) { + NOTICE("BL2: Non-acknowledge is detected. " + "AVS status=%d Retry=%u\n", + avs_status, avs_retry); + /* Check of retry number of times*/ + if (avs_retry >= AVS_RETRY_NUM) { + ERROR("BL2: AVS setting failed in retry. max=%u\n", + AVS_RETRY_NUM); + /* Infinite loop */ + panic(); + } + /* Set the error detected to error status. */ + ret = avs_error_nack; + } else { + /* Not error. */ + ret = avs_error_none; + } + return ret; +} + +/* + * Set I2C for DVFS clock. + */ +static void avs_set_iic_clock(void) +{ + uint32_t md_pin; + + /* Read Mode pin register. */ + md_pin = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14; + /* Set the module clock (CP phy) for the IIC-DVFS. */ + /* CP phy is EXTAL / 2. */ + switch (md_pin) { + case MD14_MD13_TYPE_0: /* EXTAL = 16.6666MHz */ + mmio_write_8(IIC_ICCL, ICCL_FREQ_8p33M); + mmio_write_8(IIC_ICCH, ICCH_FREQ_8p33M); + break; + case MD14_MD13_TYPE_1: /* EXTAL = 20MHz */ + mmio_write_8(IIC_ICCL, ICCL_FREQ_10M); + mmio_write_8(IIC_ICCH, ICCH_FREQ_10M); + break; + case MD14_MD13_TYPE_2: /* EXTAL = 25MHz (H3/M3) */ + mmio_write_8(IIC_ICCL, ICCL_FREQ_12p5M); + mmio_write_8(IIC_ICCH, ICCH_FREQ_12p5M); + break; + case MD14_MD13_TYPE_3: /* EXTAL = 33.3333MHz */ + mmio_write_8(IIC_ICCL, ICCL_FREQ_16p66M); + mmio_write_8(IIC_ICCH, ICCH_FREQ_16p66M); + break; + default: /* This case is not possible. */ + /* CP Phy frequency is to be set for the 16.66MHz */ + mmio_write_8(IIC_ICCL, ICCL_FREQ_16p66M); + mmio_write_8(IIC_ICCH, ICCH_FREQ_16p66M); + break; + } +} + +#if AVS_READ_PMIC_REG_ENABLE == 1 +/* + * Read the value of the register of PMIC. + */ +static uint8_t avs_read_pmic_reg(uint8_t addr) +{ + uint8_t reg; + + /* Set ICCR.ICE=1 to activate the I2C module. */ + mmio_write_8(IIC_ICCR, mmio_read_8(IIC_ICCR) | ICCR_ENABLE); + + /* Set frequency of 400kHz */ + avs_set_iic_clock(); + + /* Set ICIC.WAITE=1, ICIC.DTEE=1 to enable data transmission */ + /* interrupt and wait interrupt. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_WAITE | ICIC_DTEE); + + /* Write H'94 in ICCR to issue start condition */ + mmio_write_8(IIC_ICCR, ICCR_START); + + /* Wait for a until ICSR.DTE becomes 1. */ + avs_poll( ICSR_DTE, 1U); + + /* Clear ICIC.DTEE to disable a DTE interrupt. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) & (uint8_t)(~ICIC_DTEE)); + /* Send slave address of PMIC */ + mmio_write_8(IIC_ICDR, PMIC_W_SLAVE_ADDRESS); + + /* Wait for a until ICSR.WAIT becomes 1. */ + avs_poll(ICSR_WAIT, 1U); + + /* write PMIC address */ + mmio_write_8(IIC_ICDR, addr); + /* Clear ICSR.WAIT to exit from WAIT status. */ + mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t)(~ICSR_WAIT)); + + /* Wait for a until ICSR.WAIT becomes 1. */ + avs_poll(ICSR_WAIT, 1U); + + /* Write H'94 in ICCR to issue restart condition */ + mmio_write_8(IIC_ICCR, ICCR_START); + /* Clear ICSR.WAIT to exit from WAIT status. */ + mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t)(~ICSR_WAIT)); + /* Set ICIC.DTEE=1 to enable data transmission interrupt. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_DTEE); + + /* Wait for a until ICSR.DTE becomes 1. */ + avs_poll( ICSR_DTE, 1U); + + /* Clear ICIC.DTEE to disable a DTE interrupt. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) & (uint8_t)(~ICIC_DTEE)); + /* Send slave address of PMIC */ + mmio_write_8(IIC_ICDR, PMIC_R_SLAVE_ADDRESS); + + /* Wait for a until ICSR.WAIT becomes 1. */ + avs_poll(ICSR_WAIT, 1U); + + /* Write H'81 to ICCR to issue the repeated START condition */ + /* for changing the transmission mode to the receive mode. */ + mmio_write_8(IIC_ICCR, ICCR_START_RECV); + /* Clear ICSR.WAIT to exit from WAIT status. */ + mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t)(~ICSR_WAIT)); + + /* Wait for a until ICSR.WAIT becomes 1. */ + avs_poll(ICSR_WAIT, 1U); + + /* Set ICCR to H'C0 for the STOP condition */ + mmio_write_8(IIC_ICCR, ICCR_STOP_RECV); + /* Clear ICSR.WAIT to exit from WAIT status. */ + mmio_write_8(IIC_ICSR, mmio_read_8(IIC_ICSR) & (uint8_t)(~ICSR_WAIT)); + /* Set ICIC.DTEE=1 to enable data transmission interrupt. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) | ICIC_DTEE); + + /* Wait for a until ICSR.DTE becomes 1. */ + avs_poll( ICSR_DTE, 1U); + + /* Receive DVFS SetVID register */ + /* Clear ICIC.DTEE to disable a DTE interrupt. */ + mmio_write_8(IIC_ICIC, mmio_read_8(IIC_ICIC) & (uint8_t)(~ICIC_DTEE)); + /* Receive DVFS SetVID register */ + reg = mmio_read_8(IIC_ICDR); + + /* Wait until ICSR.BUSY is cleared. */ + avs_poll( ICSR_BUSY, 0U); + + /* Set ICCR=H'00 to disable the I2C module. */ + mmio_write_8(IIC_ICCR, 0x00U); + + return reg; +} + +/* + * Wait processing by the polling. + */ +static void avs_poll(uint8_t bit_pos, uint8_t val) +{ + uint8_t bit_val = 0U; + + if (val != 0U) { + bit_val = bit_pos; + } + + while (1) { + if ((mmio_read_8(IIC_ICSR) & bit_pos) == bit_val) { + break; + } + } +} +#endif /* AVS_READ_PMIC_REG_ENABLE */ +#endif /* (PMIC_ON_BOARD==1) */ +#endif /* (AVS_SETTING_ENABLE==1) */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/board/board.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/board/board.c new file mode 100644 index 0000000..ebad233 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/board/board.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "board.h" + + +/************************************************************************ + * Defines + ************************************************************************/ +#ifndef BOARD_DEFAULT +#define BOARD_DEFAULT (BOARD_EAGLE << BOARD_CODE_SHIFT) +#endif + +#define SLAVE_ADDR_EEPROM (0x50U) +#define REG_ADDR_BOARD_ID (0x70U) + +#define BOARD_CODE_MASK (0xF8U) +#define BOARD_REV_MASK (0x07U) +#define BOARD_CODE_SHIFT (3U) + +#define BOARD_ID_UNKNOWN (0xFFU) + + +/************************************************************************ + * Global variables + ************************************************************************/ +const char *g_board_tbl[] = { + [BOARD_EAGLE] = "Eagle" +}; +const char *g_board_unknown = "unknown"; + + +int32_t get_board_type(uint32_t *type, uint32_t *rev) +{ + int32_t ret = 0; + uint8_t read_rev; + static uint8_t g_board_id = BOARD_ID_UNKNOWN; + const uint8_t board_tbl[][8U] = { + [BOARD_EAGLE] = {0x10U, 0xFFU, 0xFFU, 0xFFU, + 0xFFU, 0xFFU, 0xFFU, 0xFFU}, + }; + + if (BOARD_ID_UNKNOWN == g_board_id) { +#if PMIC_ON_BOARD + /* Board ID detection from EEPROM */ + ret = rcar_iic_dvfs_recieve(SLAVE_ADDR_EEPROM, + REG_ADDR_BOARD_ID, &g_board_id); + if (0 != ret) { + g_board_id = BOARD_ID_UNKNOWN; + } else if (BOARD_ID_UNKNOWN == g_board_id) { + /* Can't recognize the board */ + g_board_id = BOARD_DEFAULT; + } else { + /* none */ + } +#else + g_board_id = BOARD_DEFAULT; +#endif + } + + *type = ((uint32_t)g_board_id & BOARD_CODE_MASK) >> BOARD_CODE_SHIFT; + if (*type < (sizeof(board_tbl) / sizeof(board_tbl[0]))) { + read_rev = (uint8_t)(g_board_id & BOARD_REV_MASK); + *rev = board_tbl[*type][read_rev]; + } else { + /* If there is no revision information, set Rev0.0. */ + *rev = 0x00U; + } + + return ret; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/board/board.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/board/board.h new file mode 100644 index 0000000..fc351bf --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/board/board.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + + +/************************************************************************ + * Board type + ************************************************************************/ +#define BOARD_EAGLE (0x03U) + +#define BOARD_UNKNOWN (0x1FU) + +/************************************************************************ + * Board name + ************************************************************************/ +extern const char *g_board_tbl[]; +extern const char *g_board_unknown; + +/************************************************************************ + * Revisions are expressed in 8 bits. + * The upper 4 bits are major version. + * The lower 4 bits are minor version. + ************************************************************************/ +#define GET_BOARD_MAJOR(a) ((uint32_t)(a) >> 4U) +#define GET_BOARD_MINOR(a) ((uint32_t)(a) & 0xFU) + +#define GET_BOARD_NAME(a) ((BOARD_UNKNOWN != (a)) ?\ + g_board_tbl[(a)] : g_board_unknown) + +int32_t get_board_type(uint32_t *type, uint32_t *rev); + +#endif /* BOARD_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/cpld/ulcb_cpld.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/cpld/ulcb_cpld.c new file mode 100644 index 0000000..b0117ef --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/cpld/ulcb_cpld.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017, Renesas Electronics Corporation. All rights reserved. + * Copyright (C) 2017, Cogent Embedded, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#define SCLK 8 /* GP_6_8 */ +#define SSTBZ 3 /* GP_2_3 */ +#define MOSI 7 /* GP_6_7 */ + +#define CPLD_ADDR_RESET 0x80 /* RW */ + +/* LSI Multiplexed Pin Setting Mask Register */ +#define PFC_PMMR 0xE6060000 + +/* General output registers */ +#define GPIO_OUTDT2 0xE6052008 +#define GPIO_OUTDT6 0xE6055408 + +/* General input/output switching registers */ +#define GPIO_INOUTSEL2 0xE6052004 +#define GPIO_INOUTSEL6 0xE6055404 + +/* GPIO/perihperal function select */ +#define PFC_GPSR2 0xE6060108 +#define PFC_GPSR6 0xE6060118 + +static void gpio_set_value(uint32_t addr, uint8_t gpio, uint32_t val) +{ + uint32_t reg; + + reg = mmio_read_32(addr); + if (val) + reg |= (1 << gpio); + else + reg &= ~(1 << gpio); + mmio_write_32(addr, reg); +} + +static void gpio_direction_output(uint32_t addr, uint8_t gpio) +{ + uint32_t reg; + + reg = mmio_read_32(addr); + reg |= (1 << gpio); + mmio_write_32(addr, reg); +} + +static void gpio_pfc(uint32_t addr, uint8_t gpio) +{ + uint32_t reg; + + reg = mmio_read_32(addr); + reg &= ~(1 << gpio); + mmio_write_32(PFC_PMMR, ~reg); + mmio_write_32(addr, reg); +} + +static void cpld_write(uint8_t addr, uint32_t data) +{ + int i; + + for (i = 0; i < 32; i++) { + gpio_set_value(GPIO_OUTDT6, MOSI, data & (1 << 31)); /* MSB first */ + gpio_set_value(GPIO_OUTDT6, SCLK, 1); + data <<= 1; + gpio_set_value(GPIO_OUTDT6, SCLK, 0); + } + + for (i = 0; i < 8; i++) { + gpio_set_value(GPIO_OUTDT6, MOSI, addr & 0x80); /* MSB first */ + gpio_set_value(GPIO_OUTDT6, SCLK, 1); + addr <<= 1; + gpio_set_value(GPIO_OUTDT6, SCLK, 0); + } + + gpio_set_value(GPIO_OUTDT6, MOSI, 1); /* WRITE */ + gpio_set_value(GPIO_OUTDT2, SSTBZ, 0); + gpio_set_value(GPIO_OUTDT6, SCLK, 1); + gpio_set_value(GPIO_OUTDT6, SCLK, 0); + gpio_set_value(GPIO_OUTDT2, SSTBZ, 1); +} + +static void cpld_init(void) +{ + gpio_pfc(PFC_GPSR6, SCLK); + gpio_pfc(PFC_GPSR2, SSTBZ); + gpio_pfc(PFC_GPSR6, MOSI); + + gpio_set_value(GPIO_OUTDT6, SCLK, 0); + gpio_set_value(GPIO_OUTDT2, SSTBZ, 1); + gpio_set_value(GPIO_OUTDT6, MOSI, 0); + + gpio_direction_output(GPIO_INOUTSEL6, SCLK); + gpio_direction_output(GPIO_INOUTSEL2, SSTBZ); + gpio_direction_output(GPIO_INOUTSEL6, MOSI); +} + +void cpld_reset_cpu(void) +{ + cpld_init(); + + cpld_write(CPLD_ADDR_RESET, 1); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/dma/dma_driver.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/dma/dma_driver.c new file mode 100644 index 0000000..c690c04 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/dma/dma_driver.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "rcar_def.h" +#include "bl2_cpg_register.h" +#include "bl2_cpg_init.h" +#include "bl2_dma_register.h" +#include "dma_driver.h" +#include "debug.h" + + +static void enableDMA(void); +static void setupDMA(void); +static void startDMA(uintptr_t dst, uint32_t src, uint32_t len); +static void endDMA(void); + +static void enableDMA(void) +{ + /* Is the clock supply to the CPG disabled ? */ + while((mmio_read_32(CPG_MSTPSR2) & SYS_DMAC_BIT) != 0U) { + /* Enables the clock supply to the CPG. */ + cpg_write(CPG_SMSTPCR2, + mmio_read_32(CPG_SMSTPCR2) & (~SYS_DMAC_BIT)); + } +} + +static void setupDMA(void) +{ + /* DMA operation */ + mmio_write_16(DMA_DMAOR,0x0000U); + /* DMA channel clear */ + mmio_write_32(DMA_DMACHCLR,0x0000FFFFU); + mmio_write_32(DMA_DMACHCLR,0x00000000U); +} + +static void startDMA(uintptr_t dst, uint32_t src, uint32_t len) +{ + /* DMA operation */ + mmio_write_16(DMA_DMAOR,0x0301U); + /* DMA fixed destination address */ +#if RCAR_LSI != RCAR_V3M /* NOT V3M */ + mmio_write_32(DMA_DMAFIXDAR, + (uint32_t)((dst >> 32ULL) & 0x000000FFULL)); +#endif + /* DMA destination address */ + mmio_write_32(DMA_DMADAR, + (uint32_t)(dst & 0x0FFFFFFFFULL)); + /* DMA source address */ + mmio_write_32(DMA_DMASAR,src); + /* DMA 64bytes-unit transfer count */ + mmio_write_32(DMA_DMATCR,len >> 6); + /* DMA DMA Secure Control Register */ + mmio_write_32(DMA_DMASEC,0x00000001U); + /* DMA channel control */ + mmio_write_32(DMA_DMACHCR,0x00105409U); +} + +static void endDMA(void) +{ + /* DMA channel control */ + while((mmio_read_32(DMA_DMACHCR) & 0x00000002U) == 0x00000000U) { + /* DMA channel control */ + if ((mmio_read_32(DMA_DMACHCR) & 0x80000000U) != 0U) { + ERROR("BL2: DMA - Channel Address Error\n"); + panic(); + break; + } + } + /* DMA DMA Secure Control Register */ + mmio_write_32(DMA_DMASEC,0x00000000U); + /* DMA operation */ + mmio_write_16(DMA_DMAOR,0x0000U); + /* DMA channel clear */ + mmio_write_32(DMA_DMACHCLR,0x00000001U); + mmio_write_32(DMA_DMACHCLR,0x00000000U); +} + +void initDMA(void) +{ + enableDMA(); + setupDMA(); +} + +/* execDMA */ +/* note) Parameter len is interpret 0x40000000, If len is 0. */ +void execDMA(uintptr_t dst, uint32_t src, uint32_t len) +{ + uint32_t dmalen = 0U; + uint32_t memlen = 0U; + uintptr_t dst_l = 0U; + uint32_t divlen = 0U; + + /* fail safe */ + if (((src + len) < src) || + ((len == 0U) && ((src + 0x40000000U) < src))) { + /* source address invalid */ + if (len == 0U) { + len = 0x40000000U; + } + ERROR("BL2: DMA - Source address invalid\n" \ + " source address = 0x%x\n," \ + " transfer length = 0x%x\n", + src, len); + panic(); + } + /* fail safe */ + if ((dst >= DRAM_LIMIT) || + ((dst + (uintptr_t)len) >= DRAM_LIMIT) || + ((len == 0U) && + ((dst + 0x40000000ULL) >= DRAM_LIMIT))) { + /* destination address invalid */ + if (len == 0U) { + len = 0x40000000U; + } + ERROR("BL2: DMA - Destination address invalid\n" \ + " destination address = 0x%lx\n," \ + " transfer length = 0x%x\n", + dst, len); + panic(); + } + if (((dst & 0x3FU) != 0U) || ((src & 0x3FU) != 0U) || + ((len & 0xC0000000U) != 0U)) { + /* dst or src are not 64-bit alignment. */ + dmalen = 0U; + memlen = len; + } else { + /* dst and src are 64-bit alignment. */ + dmalen = len & 0x3FFFFFC0U; + memlen = len & 0x3FU; + } + if (dmalen != 0U) { + dst_l = dst & 0x0FFFFFFFFULL; + if ((dst_l + (uintptr_t)dmalen) >= 0x100000000ULL) { + /* transfer will over than the DMADAR range. */ + /* divide dma transfer */ + divlen = (uint32_t)(0x100000000ULL - dst_l); + startDMA(dst, src, divlen); + endDMA(); + dst += (uintptr_t)divlen; + src += divlen; + dmalen -= divlen; + } + startDMA(dst, src, dmalen); + endDMA(); + dst += dmalen; + src += dmalen; + } else { + if (memlen == 0U) { + dmalen = 0x40000000U; + dst_l = dst & 0x0FFFFFFFFULL; + if ((dst_l + (uintptr_t)dmalen) >= 0x100000000ULL) { + /* transfer will over than the DMADAR range. */ + /* divide dma transfer */ + divlen = (uint32_t)(0x100000000ULL - dst_l); + startDMA(dst, src, divlen); + endDMA(); + dst += (uintptr_t)divlen; + src += divlen; + dmalen -= divlen; + } + startDMA(dst, src, dmalen & 0x3FFFFFFFU); + endDMA(); + dst += dmalen; + src += dmalen; + } + } + if (memlen != 0U) { + (void)memcpy((void*)dst, + (const void*)((uintptr_t)src), + (size_t)memlen); + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_cmd.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_cmd.c new file mode 100644 index 0000000..33d8b09 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_cmd.c @@ -0,0 +1,672 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file emmc_cmd.c + * @brief MMC card send command operation. + * + */ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +#include +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "micro_wait.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static void emmc_read_response(uint32_t *response); +static void emmc_little_to_big(uint8_t *p, uint32_t value); +static void emmc_data_transfer_dma (void); +static EMMC_ERROR_CODE emmc_response_check(uint32_t *response, uint32_t error_mask); +static void emmc_softreset(void); +static void emmc_WaitCmd2Cmd_8Cycle(void); + +static void cmdErrSdInfo2Log(void); + +/* ********************************* CODE ********************************** */ + +/** @brief execute MMC command. + * + * - Pre-conditions:
+ * * Clock to memory card IF is enabled. + * - Post-conditions:
+ * Requested command is executed successfully + * + * @param[in] error_mask Errors to be checked (error values; HAL_MEMCARD_ERRORS) + * @param[in,out] *response Response from the card (virtual address) + * @return eMMC error code. + */ +EMMC_ERROR_CODE emmc_exec_cmd ( + uint32_t error_mask, + uint32_t *response /**< virtual address */ + ) +{ + EMMC_ERROR_CODE rtn_code = EMMC_SUCCESS; + HAL_MEMCARD_RESPONSE_TYPE response_type; + HAL_MEMCARD_COMMAND_TYPE cmd_type; + EMMC_INT_STATE state; + uint32_t err_not_care_flag = FALSE; + + /* parameter check */ + if (response == NULL) + { + emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.clock_enable != TRUE) + { + emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + if (mmc_drv_obj.state_machine_blocking == TRUE) + { + emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR); + return EMMC_ERR; + } + + state = ESTATE_BEGIN; + response_type = (HAL_MEMCARD_RESPONSE_TYPE)(mmc_drv_obj.cmd_info.cmd&HAL_MEMCARD_RESPONSE_TYPE_MASK); + cmd_type = (HAL_MEMCARD_COMMAND_TYPE)(mmc_drv_obj.cmd_info.cmd&HAL_MEMCARD_COMMAND_TYPE_MASK); + + /* state machine */ + while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) + { + /* The interrupt factor flag is observed. */ + emmc_interrupt(); + + /* wait interrupt */ + if (mmc_drv_obj.state_machine_blocking == TRUE) + { + continue; + } + + switch (state) + { + case ESTATE_BEGIN: + /* Busy check */ + if( ( mmc_drv_obj.error_info.info2 & SD_INFO2_CBSY ) != 0 ) + { + emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, EMMC_ERR_CARD_BUSY); + return EMMC_ERR_CARD_BUSY; + } + + /* clear register */ + SETR_32( SD_INFO1, 0x00000000U ); + SETR_32( SD_INFO2, SD_INFO2_CLEAR ); + SETR_32( SD_INFO1_MASK, SD_INFO1_INFO0 ); + SETR_32( SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ) ); + + state = ESTATE_ISSUE_CMD; + /* through */ + + case ESTATE_ISSUE_CMD: + /* ARG */ + SETR_32( SD_ARG, mmc_drv_obj.cmd_info.arg ); + /* issue cmd */ + SETR_32(SD_CMD, mmc_drv_obj.cmd_info.hw); + /* Set driver flag */ + mmc_drv_obj.during_cmd_processing = TRUE; + mmc_drv_obj.state_machine_blocking = TRUE; + + if (response_type == HAL_MEMCARD_RESPONSE_NONE) + { + state = ESTATE_NON_RESP_CMD; + } + else + { + state = ESTATE_RCV_RESP; + } + + break; + + case ESTATE_NON_RESP_CMD: + /* interrupt disable */ + SETR_32(SD_INFO1_MASK, 0x00000000U); + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR ); + + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) + { + /* error interrupt */ + cmdErrSdInfo2Log(); + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + } + else if((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 0) + { + /* not receive expected interrupt */ + rtn_code = EMMC_ERR_RESPONSE; + state = ESTATE_ERROR; + } + else + { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } + break; + + case ESTATE_RCV_RESP: + /* interrupt disable */ + SETR_32(SD_INFO1_MASK, 0x00000000U); + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR ); + + /* check interrupt */ + if((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) + { + if ((mmc_drv_obj.get_partition_access_flag == TRUE) && + ((mmc_drv_obj.int_event2 & SD_INFO2_ERR6) != 0U)) { + err_not_care_flag = TRUE; + rtn_code = EMMC_ERR_CMD_TIMEOUT; + } else { + /* error interrupt */ + cmdErrSdInfo2Log(); + rtn_code = EMMC_ERR_INFO2; + } + state = ESTATE_ERROR; + break; + } + else if((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 0) + { + /* not receive expected interrupt */ + rtn_code = EMMC_ERR_RESPONSE; + state = ESTATE_ERROR; + break; + } + + /* read response */ + emmc_read_response(response); + + /* check response */ + rtn_code = emmc_response_check(response, error_mask); + if (rtn_code != EMMC_SUCCESS) + { + state = ESTATE_ERROR; + break; + } + + if (response_type == HAL_MEMCARD_RESPONSE_R1b) + { + /* R1b */ + SETR_32( SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ) ); + state = ESTATE_RCV_RESPONSE_BUSY; + } + else + { + state = ESTATE_CHECK_RESPONSE_COMPLETE; + } + break; + + case ESTATE_RCV_RESPONSE_BUSY: + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0) + { + /* error interrupt */ + cmdErrSdInfo2Log(); + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + break; + } + /* DAT0 not Busy */ + if( (SD_INFO2_DAT0 & mmc_drv_obj.error_info.info2) != 0 ) + { + state = ESTATE_CHECK_RESPONSE_COMPLETE; + break; + } + break; + + case ESTATE_CHECK_RESPONSE_COMPLETE: + if (cmd_type >= HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE) + { + state = ESTATE_DATA_TRANSFER; + } + else + { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } + break; + + case ESTATE_DATA_TRANSFER: + /* ADTC command */ + mmc_drv_obj.during_transfer = TRUE; + mmc_drv_obj.state_machine_blocking = TRUE; + + if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) + { + /* DMA */ + emmc_data_transfer_dma(); + } + else + { + /* PIO */ + /* interrupt enable (FIFO read/write enable) */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) + { + SETR_32(SD_INFO2_MASK, ( SD_INFO2_BWE | SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ) ); + } + else + { + SETR_32(SD_INFO2_MASK, ( SD_INFO2_BRE | SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ) ); + } + } + state = ESTATE_DATA_TRANSFER_COMPLETE; + break; + + case ESTATE_DATA_TRANSFER_COMPLETE: + /* check interrupt */ + if( ( mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR ) != 0) + { + /* error interrupt */ + cmdErrSdInfo2Log(); + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_TRANSFER_ERROR; + break; + } + else + { + /* success. nothing to do. */ + } + + /* DMAC error ? */ + if (mmc_drv_obj.dma_error_flag == TRUE) + { + /* Error occurred in DMAC driver. */ + rtn_code = EMMC_ERR_FROM_DMAC_TRANSFER; + state = ESTATE_TRANSFER_ERROR; + } + else if (mmc_drv_obj.during_dma_transfer == TRUE) + { + /* DMAC not finished. unknown error */ + rtn_code = EMMC_ERR; + state = ESTATE_TRANSFER_ERROR; + } + else + { + SETR_32( SD_INFO1_MASK, SD_INFO1_INFO2 ); + SETR_32( SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ) ); + + mmc_drv_obj.state_machine_blocking = TRUE; + + state = ESTATE_ACCESS_END; + } + break; + + case ESTATE_ACCESS_END: + + /* clear flag */ + if(HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) + { + SETR_32( CC_EXT_MODE, CC_EXT_MODE_CLEAR ); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ + SETR_32( SD_STOP, 0x00000000U ); + mmc_drv_obj.during_dma_transfer = FALSE; + } + + SETR_32( SD_INFO1_MASK, 0x00000000U ); + SETR_32( SD_INFO2_MASK, SD_INFO2_CLEAR ); + SETR_32( SD_INFO1, 0x00000000U ); + SETR_32( SD_INFO2, SD_INFO2_CLEAR ); + + if(( mmc_drv_obj.int_event1 & SD_INFO1_INFO2 ) != 0 ) + { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } + else + { + state = ESTATE_ERROR; + } + break; + + case ESTATE_TRANSFER_ERROR: + /* The error occurred in the Data transfer. */ + if(HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) + { + SETR_32( CC_EXT_MODE, CC_EXT_MODE_CLEAR ); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ + SETR_32( SD_STOP, 0x00000000U ); + mmc_drv_obj.during_dma_transfer = FALSE; + } + /* through */ + + case ESTATE_ERROR: + if (err_not_care_flag == TRUE) { + mmc_drv_obj.during_cmd_processing = FALSE; + } else { + emmc_softreset(); + emmc_write_error_info(EMMC_FUNCNO_EXEC_CMD, rtn_code); + } + return rtn_code; + + default: + state = ESTATE_END; + break; + } /* switch (state) */ + } /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */ + + /* force terminate */ + if (mmc_drv_obj.force_terminate == TRUE) + { + /* timeout timer is expired. Or, PIO data transfer error. */ + /* Timeout occurred in the DMA transfer. */ + if (mmc_drv_obj.during_dma_transfer == TRUE) + { + mmc_drv_obj.during_dma_transfer = FALSE; + } + ERROR("BL2: emmc exec_cmd:EMMC_ERR_FORCE_TERMINATE\n"); + emmc_softreset(); + + return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */ + } + + /* success */ + mmc_drv_obj.during_cmd_processing = FALSE; + mmc_drv_obj.during_transfer = FALSE; + + return EMMC_SUCCESS; +} + +/** @brief host controller softreset. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * @param None. + * @return None. + */ +static void emmc_softreset(void) +{ + int32_t loop = 10000; + int32_t retry = 1000; + + /* flag clear */ + mmc_drv_obj.during_cmd_processing = FALSE; + mmc_drv_obj.during_transfer = FALSE; + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.state_machine_blocking = FALSE; + mmc_drv_obj.force_terminate = FALSE; + mmc_drv_obj.dma_error_flag = FALSE; + + /* during operation ? */ + if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0) + { + /* wait CMDSEQ = 0 */ + while (loop > 0) + { + if((GETR_32(SD_INFO2) & SD_INFO2_CBSY) == 0) + { + break; /* ready */ + } + + loop--; + if ((loop == 0) && (retry > 0) ) + { + micro_wait(1000U); /* wait 1ms */ + loop = 10000; + retry--; + } + } + } + + /* reset */ + SETR_32(SOFT_RST, ( GETR_32(SOFT_RST) & (~SOFT_RST_SDRST) ) ); /* Soft reset */ + SETR_32(SOFT_RST, ( GETR_32(SOFT_RST) | SOFT_RST_SDRST ) ); /* Soft reset released */ + + /* initialize */ + SETR_32(SD_INFO1, 0x00000000U); + SETR_32(SD_INFO2, SD_INFO2_CLEAR ); + SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR ); /* all interrupt disable */ + +} + +/** @brief read response + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * @param[in,out] *response Response from the card + * @return None. + */ +static void emmc_read_response( + uint32_t *response + ) +{ + + uint8_t *p; + + if (response == NULL) + { + return; + } + + /* read response */ + if (mmc_drv_obj.response_length == EMMC_MAX_RESPONSE_LENGTH) + { + /* CSD or CID */ + p = (uint8_t *)(response); + emmc_little_to_big(p , ((GETR_32(SD_RSP76)<<8)|(GETR_32(SD_RSP54)>>24))); /* [127:96] */ + emmc_little_to_big(p+4 , ((GETR_32(SD_RSP54)<<8)|(GETR_32(SD_RSP32)>>24))); /* [95:64] */ + emmc_little_to_big(p+8 , ((GETR_32(SD_RSP32)<<8)|(GETR_32(SD_RSP10)>>24))); /* [63:32] */ + emmc_little_to_big(p+12 , (GETR_32(SD_RSP10)<<8)); /* [31:0] */ + } + else + { + *response = GETR_32(SD_RSP10); /* [39:8] */ + } +} + +/** @brief response check + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * @param[in] *response Response from the card + * @param[in] error_mask Errors to be checked (for R1/R1b response) + * @return error code. + */ +static EMMC_ERROR_CODE emmc_response_check( + uint32_t *response, + uint32_t error_mask + ) +{ + + HAL_MEMCARD_RESPONSE_TYPE response_type = (HAL_MEMCARD_RESPONSE_TYPE)(mmc_drv_obj.cmd_info.cmd&HAL_MEMCARD_RESPONSE_TYPE_MASK); + + if (response == NULL) + { + return EMMC_ERR_PARAM; + } + + if (response_type == HAL_MEMCARD_RESPONSE_NONE) + { + return EMMC_SUCCESS; + } + + /* response check */ + if (response_type <= HAL_MEMCARD_RESPONSE_R1b) + { + /* R1 or R1b */ + mmc_drv_obj.current_state = (EMMC_R1_STATE)((*response & EMMC_R1_STATE_MASK) >> EMMC_R1_STATE_SHIFT); + if ( (*response & error_mask) != 0) + { + if((0x80 & *response) != 0) + { + ERROR("BL2: emmc SWITCH_ERROR\n"); + } + return EMMC_ERR_CARD_STATUS_BIT; + } + } + else if (response_type == HAL_MEMCARD_RESPONSE_R4) + { + /* R4 */ + if ( (*response & EMMC_R4_STATUS) != 0) + { + return EMMC_ERR_CARD_STATUS_BIT; + } + } + else + { + /* nothing to do. other type does not have status bit */ + } + + return EMMC_SUCCESS; +} + +/** @brief converts endian from little to big + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * @param[in,out] p destination buffer address. + * @param[in] value convert data.(little) + * @return None. + */ +static void emmc_little_to_big( + uint8_t *p, + uint32_t value + ) +{ + if (p == NULL) + { + return; + } + + p[0] = (uint8_t)(value >> 24); + p[1] = (uint8_t)(value >> 16); + p[2] = (uint8_t)(value >> 8); + p[3] = (uint8_t)value; +} + +/** @brief data transfer with DMA. + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * @return error code. + */ +static void emmc_data_transfer_dma(void) +{ + mmc_drv_obj.during_dma_transfer = TRUE; + mmc_drv_obj.dma_error_flag = FALSE; + + SETR_32( SD_INFO1_MASK, 0x00000000U ); + SETR_32( SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR ) ); + + /* DMAC setting */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) + { + /* transfer complete interrupt enable */ + SETR_32( DM_CM_INFO1_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE ) ); + SETR_32( DM_CM_INFO2_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE ) ); + /* BUFF --> FIFO */ + SETR_32( DM_CM_DTRAN_MODE, ( DM_CM_DTRAN_MODE_CH0 | DM_CM_DTRAN_MODE_BIT_WIDTH ) ); /* CH0(downstream), 64-bit width */ + } + else + { + /* transfer complete interrupt enable */ + SETR_32( DM_CM_INFO1_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE ) ); + SETR_32( DM_CM_INFO2_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE ) ); + /* FIFO --> BUFF */ + SETR_32( DM_CM_DTRAN_MODE, ( DM_CM_DTRAN_MODE_CH1 | DM_CM_DTRAN_MODE_BIT_WIDTH ) ); /* CH0(downstream), 64-bit width */ + } + SETR_32( DM_DTRAN_ADDR, ( ( (uintptr_t)mmc_drv_obj.buff_address_virtual & DM_DTRAN_ADDR_WRITE_MASK ) ) ); /* Set address */ + + SETR_32( DM_CM_DTRAN_CTRL, DM_CM_DTRAN_CTRL_START ); /* DMAC Start */ +} + +/** @brief wait cmd-cmd 8cycle + * + * - Pre-conditions:
+ * + * - Post-conditions:
+ * . + * + * @return None. + */ +static void emmc_WaitCmd2Cmd_8Cycle(void) +{ + uint32_t dataL,wait=0; + + dataL = GETR_32(SD_CLK_CTRL); + dataL &= 0x000000FF; + + switch(dataL){ + case 0xFF: wait = 10U; break; // 1/1 10 us wait ( 1/200MHz)*8= 0.04 us(min) + case 0x00: wait = 10U; break; // 1/2 10 us wait ( 2/200MHz)*8= 0.08 us(min) + case 0x01: wait = 10U; break; // 1/4 10 us wait ( 4/200MHz)*8= 0.16 us(min) + case 0x02: wait = 10U; break; // 1/8 10 us wait ( 8/200MHz)*8= 0.32 us(min) + case 0x04: wait = 10U; break; // 1/16 10 us wait ( 16/200MHz)*8= 0.64 us(min) + case 0x08: wait = 10U; break; // 1/32 10 us wait ( 32/200MHz)*8= 1.28 us(min) + case 0x10: wait = 10U; break; // 1/64 10 us wait ( 64/200MHz)*8= 2.56 us(min) + case 0x20: wait = 10U; break; // 1/128 10 us wait (128/200MHz)*8= 5.12 us(min) + case 0x40: wait = 20U; break; // 1/256 20 us wait (256/200MHz)*8= 10.24 us(min) + case 0x80: wait = 30U; break; // 1/512 30 us wait (512/200MHz)*8= 20.48 us(min) + } + micro_wait(wait); + +} + +/** @brief debug log SD_INFO2 + * + * - Pre-conditions:
+ * + * - Post-conditions:
+ * . + * + * @return None. + */ +static void cmdErrSdInfo2Log( void ) +{ + ERROR("BL2: emmc ERR SD_INFO2 = 0x%x\n", mmc_drv_obj.error_info.info2); +} +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_init.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_init.c new file mode 100644 index 0000000..4f0eafa --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_init.c @@ -0,0 +1,387 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file emmc_init.c + * @brief eMMC boot initialize program. + * + */ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include +#include +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ +st_mmc_base mmc_drv_obj; + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static void emmc_drv_init(void); +static EMMC_ERROR_CODE emmc_dev_init(void); +static EMMC_ERROR_CODE emmc_dev_finalize(void); +static void emmc_memset(uint8_t *buff, uint8_t data, uint32_t cnt); +static EMMC_ERROR_CODE emmc_reset_controller(void); +static void emmc_driver_config (void); +__inline static void emmc_set_retry_count(uint32_t retry); +__inline static void emmc_set_data_timeout(uint32_t data_timeout); + +/* ********************************* CODE ********************************** */ + +/** @brief eMMC initialize. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * @retval EMMC_SUCCESS successful. + * @retval EMMC_ERR error from interrupt API. + */ +EMMC_ERROR_CODE emmc_init(void) +{ + EMMC_ERROR_CODE retult; + /* initialize H/W */ + retult = emmc_reset_controller(); + if( EMMC_SUCCESS != retult ) + { + return retult; + } + + /* Configuration */ + emmc_driver_config(); + + return EMMC_SUCCESS; +} + +/** @brief terminate emmc driver + * + * EMMC H/W and S/W resource is released. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * @return None. + */ +EMMC_ERROR_CODE emmc_terminate (void) +{ + EMMC_ERROR_CODE result; + + /* H/W finalize */ + result = emmc_dev_finalize(); + if (result != EMMC_SUCCESS) + { + /* nothing to do. */ + } + + /* driver finalize */ + emmc_memset((uint8_t *)(&mmc_drv_obj), 0, sizeof(st_mmc_base)); /* clear global variable */ + + + return result; +} + +/** @brief Function executes full reset to MMC host controller without taking power out from the memory card. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * Reset MMC host controller without taking power out from the memory card. + * Memory card preserves its state. + * + * @return None + */ +static EMMC_ERROR_CODE emmc_reset_controller(void) +{ + EMMC_ERROR_CODE retult; + + /* initialize mmc driver */ + emmc_drv_init(); + + /* initialize H/W */ + retult = emmc_dev_init(); + if( EMMC_SUCCESS != retult ) + { + return retult; + } + + mmc_drv_obj.initialize = TRUE; + + return retult; + +} + +/** @brief Configuration eMMC driver + * + * - Pre-conditions:
+ * initialized eMMC driver. + * - Post-conditions:
+ * . + * + * @return None + */ +static void emmc_driver_config (void) +{ + /* retry */ + emmc_set_retry_count(EMMC_RETRY_COUNT); + + /* Read/Write data timeout */ + emmc_set_data_timeout(EMMC_RW_DATA_TIMEOUT); +} + + +/** @brief Registers configuration + * + * This function gives the configuration arguments to the driver. + * It must be possible to call this function multiple times. + * + * - Pre-conditions:
+ * initialized eMMC driver. + * + * - Post-conditions:
+ * Driver is using configuration values. + * + * @param[in] retry how many times to try after fail, for instance sending command. + * @return None + */ +__inline static void emmc_set_retry_count ( + uint32_t retry + ) +{ + mmc_drv_obj.retries_after_fail = retry; +} + +/** @brief Sets data timeout + * + * Sets the data timeout value for read and write operations. + * + * - Pre-conditions:
+ * initialized eMMC driver. + * + * - Post-conditions:
+ * After this function is called, the timeout value is set according to argument. + * + * @param[in] time_out The desired timeout value in milliseconds. + * @return None + */ +__inline static void emmc_set_data_timeout ( + uint32_t data_timeout + ) +{ + mmc_drv_obj.data_timeout = data_timeout; +} + +/** @brief eMMC driver initialize. (software) + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * @return None. + */ +static void emmc_drv_init(void) +{ + /* initialize */ + emmc_memset((uint8_t *)(&mmc_drv_obj), 0, sizeof(st_mmc_base)); + + mmc_drv_obj.card_present = HAL_MEMCARD_CARD_IS_IN; + mmc_drv_obj.data_timeout = EMMC_RW_DATA_TIMEOUT; + + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; +} + +/** @brief eMMC driver initialize. (H/W) + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * @return None. + */ +static EMMC_ERROR_CODE emmc_dev_init(void) +{ + uint32_t dataL; + + /* Power on eMMC */ + dataL = mmio_read_32(CPG_SMSTPCR3); + if ((dataL) & (BIT12)) { + dataL &= ~((uint32_t)(BIT12)); + mmio_write_32(CPG_CPGWPR, (~dataL)); + mmio_write_32(CPG_SMSTPCR3, dataL); + } + + dataL = mmio_read_32(CPG_MSTPSR3); + while ( (dataL & (BIT12)) != 0x0U ) { + dataL = mmio_read_32(CPG_MSTPSR3); + } + + /* Set SD clock */ + mmio_write_32(CPG_CPGWPR, ~((uint32_t)(BIT9|BIT0))); //SD phy 200MHz + /* Stop SDnH clock & SDn=200MHz */ + mmio_write_32(CPG_SD2CKCR, (BIT9|BIT0)); + + /* MMCIF initialize */ + SETR_32(SD_INFO1, 0x00000000U); /* all interrupt clear */ + SETR_32(SD_INFO2, SD_INFO2_CLEAR ); /* all interrupt clear */ + SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR ); /* all interrupt disable */ + + SETR_32(HOST_MODE, 0x00000000U); /* SD_BUF access width = 64-bit */ + SETR_32(SD_OPTION, 0x0000C0EEU); /* Bus width = 1bit, timeout=MAX */ + SETR_32(SD_CLK_CTRL, 0x00000000U); /* Automatic Control=Disable, Clock Output=Disable */ + + return EMMC_SUCCESS; +} + +/** @brief EMMC H/W finalize + * + * EMMC Host and Card hardware resource is released. + * + * - Pre-conditions:
+ * . + * + * - Post-conditions:
+ * . + * @return None. + */ +static EMMC_ERROR_CODE emmc_dev_finalize(void) +{ + EMMC_ERROR_CODE result; + uint32_t dataL; + + /* MMC power off + * the power supply of eMMC device is always turning on. + * RST_n : Hi --> Low level. + */ + result = emmc_memcard_power(FALSE); + if (result != EMMC_SUCCESS) + { + /* nothing to do. */ + } + + /* host controller reset */ +// SETR_32(SOFT_RST, ( GETR(SOFT_RST) & (~SOFT_RST_SDRST) ) ); /* Soft reset */ +// SETR_32(SOFT_RST, ( GETR(SOFT_RST) | SOFT_RST_SDRST ) ); /* Soft reset released */ + SETR_32(SD_INFO1, 0x00000000U); /* all interrupt clear */ + SETR_32(SD_INFO2, SD_INFO2_CLEAR ); /* all interrupt clear */ + SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR ); /* all interrupt disable */ + SETR_32(SD_CLK_CTRL, 0x00000000U); /* MMC clock stop */ + + dataL = mmio_read_32(CPG_SMSTPCR3); + if ((dataL & BIT12) == 0U) { + dataL |= (BIT12); + mmio_write_32(CPG_CPGWPR, (~dataL)); + mmio_write_32(CPG_SMSTPCR3, dataL); + } + + return result; +} + +/** @brief Set power to memory card IF. + * This function control Vcc and Vccq and RST_n. + * + * @attention + * CPU cannot control Vcc&Vccq. + * The power supply of eMMC device is always turning on. + * + * @param[in] mode TRUE = power on, FALSE = power off + * + * @retval EMMC_SUCCESS powering succeeded + * @retval EMMC_ERR_CARD_POWER powering failed + */ +EMMC_ERROR_CODE emmc_memcard_power + ( + uint8_t mode + ) +{ +// EMMC_ERROR_CODE result; + + if (mode == TRUE) + { + /* power on (Vcc&Vccq is always power on) */ + mmc_drv_obj.card_power_enable = TRUE; + } + else + { + /* power off (Vcc&Vccq is always power on) */ + mmc_drv_obj.card_power_enable = FALSE; + mmc_drv_obj.mount = FALSE; + mmc_drv_obj.selected = FALSE; + } + + return EMMC_SUCCESS; +} + +/** @brief memset(). no use C standard library. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * @param[in,out] buff pointer to buffer (virtual) + * @param[in] data fill data. + * @param[in] cnt fill size (number of bytes) + * @return None. + */ + +static void emmc_memset( + uint8_t *buff, + uint8_t data, + uint32_t cnt + ) +{ + if (buff == NULL) + { + return; + } + + while (cnt > 0) + { + *buff++ = data; + cnt--; + } +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_interrupt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_interrupt.c new file mode 100644 index 0000000..f085797 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_interrupt.c @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file emmc_interrupt.c + * @brief interrupt service for MMC boot driver. + * + */ + +#include +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include +#include "rcar_def.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static EMMC_ERROR_CODE emmc_trans_sector (uint32_t *buff_address_virtual); + + +/* ********************************* CODE ********************************** */ + + + +/** @brief emmc driver interrupt service routine. + * + * - Pre-conditions:
+ * Must be block emmc driver state machine. + * - Post-conditions:
+ * unblocking emmc driver state machine. + * + * @retval INT_SUCCESS + */ +uint32_t emmc_interrupt(void) +{ + EMMC_ERROR_CODE result; + uint32_t prr_data; + uint32_t cut_ver; + uint32_t end_bit; + + prr_data = mmio_read_32((uintptr_t)RCAR_PRR); + cut_ver = prr_data & RCAR_CUT_MASK; + if ((prr_data & RCAR_PRODUCT_MASK) == RCAR_PRODUCT_H3) { + if (cut_ver == RCAR_CUT_ES10) { + end_bit = BIT17; + } else if (cut_ver == RCAR_CUT_ES11) { + end_bit = BIT17; + } else { + end_bit = BIT20; + } + } else if ((prr_data & RCAR_PRODUCT_MASK) == RCAR_PRODUCT_M3) { + if (cut_ver == RCAR_CUT_ES10) { + end_bit = BIT17; + } else { + end_bit = BIT20; + } + } else { + end_bit = BIT20; + } + + /* SD_INFO */ + mmc_drv_obj.error_info.info1 = GETR_32(SD_INFO1); + mmc_drv_obj.error_info.info2 = GETR_32(SD_INFO2); + + /* SD_INFO EVENT */ + mmc_drv_obj.int_event1 = mmc_drv_obj.error_info.info1 & GETR_32(SD_INFO1_MASK); + mmc_drv_obj.int_event2 = mmc_drv_obj.error_info.info2 & GETR_32(SD_INFO2_MASK); + + /* ERR_STS */ + mmc_drv_obj.error_info.status1 = GETR_32(SD_ERR_STS1); + mmc_drv_obj.error_info.status2 = GETR_32(SD_ERR_STS2); + + /* DM_CM_INFO */ + mmc_drv_obj.error_info.dm_info1 = GETR_32(DM_CM_INFO1); + mmc_drv_obj.error_info.dm_info2 = GETR_32(DM_CM_INFO2); + + /* DM_CM_INFO EVENT */ + mmc_drv_obj.dm_event1 = mmc_drv_obj.error_info.dm_info1 & GETR_32(DM_CM_INFO1_MASK); + mmc_drv_obj.dm_event2 = mmc_drv_obj.error_info.dm_info2 & GETR_32(DM_CM_INFO2_MASK); + +/* ERR SD_INFO2 */ + if( (SD_INFO2_ALL_ERR & mmc_drv_obj.int_event2) != 0 ) + { + SETR_32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */ + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR ); /* interrupt disable */ + SETR_32(SD_INFO1, 0x00000000U); /* interrupt clear */ + SETR_32(SD_INFO2, SD_INFO2_CLEAR ); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } + +/* PIO Transfer */ + /* BWE/BRE */ + else if((( SD_INFO2_BWE | SD_INFO2_BRE ) & mmc_drv_obj.int_event2 ) != 0 ) + { + /* BWE */ + if( SD_INFO2_BWE & mmc_drv_obj.int_event2 ) + { + SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BWE) ); /* interrupt clear */ + } + /* BRE */ + else + { + SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BRE) ); /* interrupt clear */ + } + + result = emmc_trans_sector((uint32_t *)mmc_drv_obj.buff_address_virtual); /* sector R/W */ + mmc_drv_obj.buff_address_virtual += EMMC_BLOCK_LENGTH; + mmc_drv_obj.remain_size -= EMMC_BLOCK_LENGTH; + + if(result != EMMC_SUCCESS) + { + /* data transfer error */ + emmc_write_error_info(EMMC_FUNCNO_NONE, result); + + /* Panic */ + SETR_32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */ + SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR ); /* interrupt disable */ + SETR_32(SD_INFO1, 0x00000000U); /* interrupt clear */ + SETR_32(SD_INFO2, SD_INFO2_CLEAR ); /* interrupt clear */ + mmc_drv_obj.force_terminate = TRUE; + } + else + { + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; + } + +/* DMA_TRANSFER */ + /* DM_CM_INFO1: DMA-ch0 transfer complete or error occurred */ + else if( (BIT16 & mmc_drv_obj.dm_event1) != 0 ) + { + SETR_32(DM_CM_INFO1, 0x00000000U); + SETR_32(DM_CM_INFO2, 0x00000000U); + SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BWE) ); /* interrupt clear */ + /* DM_CM_INFO2: DMA-ch0 error occured */ + if( ( BIT16 & mmc_drv_obj.dm_event2 ) != 0 ) + { + mmc_drv_obj.dma_error_flag = TRUE; + } + else + { + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; /* wait next interrupt */ + } + /* DM_CM_INFO1: DMA-ch1 transfer complete or error occured */ + else if( (end_bit & mmc_drv_obj.dm_event1) != 0U ) + { + SETR_32(DM_CM_INFO1, 0x00000000U); + SETR_32(DM_CM_INFO2, 0x00000000U); + SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BRE) ); /* interrupt clear */ + /* DM_CM_INFO2: DMA-ch1 error occured */ + if( ( BIT17 & mmc_drv_obj.dm_event2 ) != 0 ) + { + mmc_drv_obj.dma_error_flag = TRUE; + } + else + { + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; /* wait next interrupt */ + } + + /* Response end */ + else if( (SD_INFO1_INFO0 & mmc_drv_obj.int_event1) != 0) + { + SETR_32(SD_INFO1, (GETR_32(SD_INFO1) & ~SD_INFO1_INFO0) ); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } + /* Access end */ + else if( (SD_INFO1_INFO2 & mmc_drv_obj.int_event1) != 0) + { + SETR_32(SD_INFO1, (GETR_32(SD_INFO1) & ~SD_INFO1_INFO2) ); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } + else + { + /* nothing to do. */ + } + + return (uint32_t)0; +} + +/** @brief Data transfer function with PIO (Single sector). + * + * - Pre-conditions:
+ * Called from interrupt service. + * - Post-conditions:
+ * . + * + * @param[in,out] buff_address_virtual Dest/Src buffer address(virtual). + * @retval EMMC_SUCCESS successful. + * @retval EMMC_ERR_PARAM parameter error. + * @retval EMMC_ERR_STATE state error. + */ +static EMMC_ERROR_CODE emmc_trans_sector ( + uint32_t *buff_address_virtual + ) +{ + uint32_t length,i; + uint64_t *bufPtrLL; + + if (buff_address_virtual == NULL) + { + return EMMC_ERR_PARAM; + } + + if ((mmc_drv_obj.during_transfer != TRUE) || (mmc_drv_obj.remain_size == 0) ) + { + return EMMC_ERR_STATE; + } + + bufPtrLL = (uint64_t*)buff_address_virtual; + length = mmc_drv_obj.remain_size; + + /* data transefer */ + for (i=0; i<(length>>3);i++) + { + /* Write */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) + { + SETR_64(SD_BUF0, *bufPtrLL); /* buffer --> FIFO */ + } + /* Read */ + else + { + *bufPtrLL = GETR_64(SD_BUF0); /* FIFO --> buffer */ + } + bufPtrLL++; + } + + return EMMC_SUCCESS; +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_mount.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_mount.c new file mode 100644 index 0000000..10ef6f4 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_mount.c @@ -0,0 +1,867 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file emmc_mount.c + * @brief MMC card mount operation. + * + */ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include +#include +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "micro_wait.h" +#include "rcar_def.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static EMMC_ERROR_CODE emmc_clock_ctrl(uint8_t mode); +static EMMC_ERROR_CODE emmc_card_init (void); +static EMMC_ERROR_CODE emmc_high_speed(void); +static EMMC_ERROR_CODE emmc_bus_width(uint32_t width); +//static EMMC_ERROR_CODE emmc_check_pattern(uint8_t *pat, uint32_t size); +static uint32_t emmc_set_timeout_register_value(uint32_t freq); +static void set_sd_clk(uint32_t clkDiv); +static uint32_t emmc_calc_tran_speed(uint32_t* freq); +static void emmc_get_partition_access(void); +static void emmc_set_bootpartition(void); + +/* ********************************* CODE ********************************** */ + +/** @brief eMMC mount operation. + * + * Sequence is the following. + * 1) Bus initialization (emmc_card_init()) + * 2) Switching to high speed mode. (emmc_high_speed()) + * 3) Changing the data bus width. (emmc_bus_width()) + * + * - Pre-conditions:
+ * eMMC driver is initialized. The power supply of MMC IF must be turning on. + * - Post-conditions:
+ * MMC card state changes to transfer state. + * + * @return eMMC error code. + */ +EMMC_ERROR_CODE emmc_mount(void) +{ + EMMC_ERROR_CODE result; + + /* state check */ + if ( (mmc_drv_obj.initialize != TRUE) + || (mmc_drv_obj.card_power_enable != TRUE) + || ( (GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0) + ) + { + emmc_write_error_info(EMMC_FUNCNO_MOUNT, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* initialize card (IDLE state --> Transfer state) */ + result = emmc_card_init(); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) + { + /* nothing to do. */ + } + return result; + } + + /* Switching high speed mode */ + result = emmc_high_speed(); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED); + if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) + { + /* nothing to do. */ + } + return result; + } + + /* Changing the data bus width */ + result = emmc_bus_width(8); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_BUS_WIDTH); + if (emmc_clock_ctrl(FALSE) != EMMC_SUCCESS) + { + /* nothing to do. */ + } + return result; + } + + /* mount complete */ + mmc_drv_obj.mount = TRUE; + + return EMMC_SUCCESS; +} + +/** @brief Bus initialization function + * + * - Pre-conditions:
+ * eMMC driver is initialized. The power supply of MMC IF must be turning on. + * - Post-conditions:
+ * MMC card state changes to transfer state. + * + * @retval EMMC_SUCCESS successful. + * @return eMMC error code. + * @attention upper layer must be check pre-conditions. + */ +static EMMC_ERROR_CODE emmc_card_init (void) +{ + int32_t retry; + uint32_t freq = MMC_400KHZ; /* 390KHz */ + EMMC_ERROR_CODE result; + uint32_t resultCalc; + + /* state check */ + if ( (mmc_drv_obj.initialize != TRUE) + || (mmc_drv_obj.card_power_enable != TRUE) + || ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0) + ) + { + emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* clock on (force change) */ + mmc_drv_obj.current_freq = 0; + mmc_drv_obj.max_freq = MMC_20MHZ; /* MMC_20MHZ = MMC_12MHZ = 12.187MHz */ + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return EMMC_ERR; + } + + micro_wait(1000U); /* wait 1ms */ + + /* Get current access partition */ + emmc_get_partition_access(); + + /* CMD0, arg=0x00000000 */ + result = emmc_send_idle_cmd (0x00000000); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + micro_wait(200U); /* wait 74clock 390kHz(189.74us)*/ + + /* CMD1 */ + emmc_make_nontrans_cmd(CMD1_SEND_OP_COND, EMMC_HOST_OCR_VALUE); + for (retry=300; retry > 0; retry--) + { + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + if ((mmc_drv_obj.r3_ocr & EMMC_OCR_STATUS_BIT) != 0) + { + break; /* card is ready. exit loop */ + } + micro_wait(1000U); /* wait 1ms */ + } + + if (retry == 0) + { + emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR_TIMEOUT); + return EMMC_ERR_TIMEOUT; + } + + switch (mmc_drv_obj.r3_ocr & EMMC_OCR_ACCESS_MODE_MASK) + { + case EMMC_OCR_ACCESS_MODE_SECT: + mmc_drv_obj.access_mode = TRUE; /* sector mode */ + break; + default: + /* unknown value */ + emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR); + return EMMC_ERR; + } + + /* CMD2 */ + emmc_make_nontrans_cmd(CMD2_ALL_SEND_CID_MMC, 0x00000000); + mmc_drv_obj.response = (uint32_t *)(&mmc_drv_obj.cid_data[0]); /* use CID special buffer */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + /* CMD3 */ + emmc_make_nontrans_cmd(CMD3_SET_RELATIVE_ADDR, EMMC_RCA<<16); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + /* CMD9 (CSD) */ + emmc_make_nontrans_cmd(CMD9_SEND_CSD, EMMC_RCA<<16); + mmc_drv_obj.response = (uint32_t *)(&mmc_drv_obj.csd_data[0]); /* use CSD special buffer */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + /* card version check */ + if (EMMC_CSD_SPEC_VARS() < 4) + { + emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR_ILLEGAL_CARD); + return EMMC_ERR_ILLEGAL_CARD; + } + + /* CMD7 (select card) */ + emmc_make_nontrans_cmd(CMD7_SELECT_CARD, EMMC_RCA<<16); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + mmc_drv_obj.selected = TRUE; + + /* card speed check */ + resultCalc = emmc_calc_tran_speed( &freq ); /* Card spec is calculated from TRAN_SPEED(CSD). */ + if (resultCalc == 0) + { + emmc_write_error_info(EMMC_FUNCNO_CARD_INIT, EMMC_ERR_ILLEGAL_CARD); + return EMMC_ERR_ILLEGAL_CARD; + } + mmc_drv_obj.max_freq = freq; /* max frequency (card spec) */ + + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return EMMC_ERR; + } + + /* set read/write timeout */ + mmc_drv_obj.data_timeout = emmc_set_timeout_register_value( freq ); + SETR_32( SD_OPTION,((GETR_32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) | mmc_drv_obj.data_timeout)); + + /* SET_BLOCKLEN(512byte) */ + /* CMD16 */ + emmc_make_nontrans_cmd(CMD16_SET_BLOCKLEN, EMMC_BLOCK_LENGTH); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + /* Transfer Data Length */ + SETR_32( SD_SIZE, EMMC_BLOCK_LENGTH ); + + /* CMD8 (EXT_CSD) */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0]), EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + /* CMD12 is not send. + * If BUS initialization is failed, user must be execute Bus initialization again. + * Bus initialization is start CMD0(soft reset command). + */ + emmc_write_error_info_func_no(EMMC_FUNCNO_CARD_INIT); + return result; + } + + /* Set boot partition */ + emmc_set_bootpartition(); + + return EMMC_SUCCESS; +} + +/** @brief Switching to high-speed mode + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * EXT_CSD data must be stored in mmc_drv_obj.ext_csd_data[]. + * + * - Post-conditions:
+ * Change the clock frequency to 26MHz or 52MHz. + * + * @retval EMMC_SUCCESS successful or aleady switching. + * @retval EMMC_ERR_STATE state error. + * @retval EMMC_ERR unknown error. + * @return emmc error code. + */ +static EMMC_ERROR_CODE emmc_high_speed(void) +{ + uint32_t freq; /**< High speed mode clock frequency */ + EMMC_ERROR_CODE result; + uint8_t cardType; + + /* state check */ + if (mmc_drv_obj.selected != TRUE) + { + emmc_write_error_info(EMMC_FUNCNO_HIGH_SPEED, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* max frequency */ + cardType = (uint8_t)mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_CARD_TYPE]; + if( (cardType & EMMC_EXT_CSD_CARD_TYPE_52MHZ ) != 0 ) + { + freq = MMC_52MHZ; + } + else if( (cardType & EMMC_EXT_CSD_CARD_TYPE_26MHZ ) != 0 ) + { + freq = MMC_26MHZ; + } + else + { + freq = MMC_20MHZ; + } + + /* Hi-Speed-mode selction */ + if( ( MMC_52MHZ == freq ) || + ( MMC_26MHZ == freq ) ) + { + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED); + return result; + } + + mmc_drv_obj.hs_timing = TIMING_HIGH_SPEED; /* High-Speed */ + } + + /* set mmc clock */ + mmc_drv_obj.max_freq = freq; + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED); + return EMMC_ERR; + } + + /* set read/write timeout */ + mmc_drv_obj.data_timeout = emmc_set_timeout_register_value( freq ); + SETR_32( SD_OPTION,((GETR_32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) | mmc_drv_obj.data_timeout)); + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA<<16); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK_WITHOUT_CRC, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + emmc_write_error_info_func_no(EMMC_FUNCNO_HIGH_SPEED); + return result; + } + + return EMMC_SUCCESS; +} + +/** @brief Changing the data bus width + * + * if changing the data bus width failed, card is reset by CMD0. + * Please do Bus initialization over again. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * + * - Post-conditions:
+ * Change the data bus width to 8bit or 4bit. + * mmc_drv_obj.ext_csd_data is updated. + * + * @param[in] width bus width (8 or 4) + * @retval EMMC_SUCCESS successful. + * @retval EMMC_ERR_PARAM parameter error + * @retval EMMC_ERR_STATE state error. + * + */ +static EMMC_ERROR_CODE emmc_bus_width( + uint32_t width + ) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* parameter check */ + if ( (width != 8) && (width != 4) && (width != 1) ) + { + emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.selected != TRUE) + { + emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH)(width>>2); /* 2 = 8bit, 1 = 4bit, 0 =1bit */ + + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, ( EMMC_SWITCH_BUS_WIDTH_1 | ( mmc_drv_obj.bus_width << 8 ) ) ); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + /* occurred error */ + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; + goto EXIT; + } + + switch(mmc_drv_obj.bus_width) + { + case HAL_MEMCARD_DATA_WIDTH_1_BIT: + SETR_32( SD_OPTION,((GETR_32(SD_OPTION) & ~(BIT15|BIT13)) | BIT15 )); + break; + case HAL_MEMCARD_DATA_WIDTH_4_BIT: + SETR_32( SD_OPTION,(GETR_32(SD_OPTION) & ~(BIT15|BIT13))); + break; + case HAL_MEMCARD_DATA_WIDTH_8_BIT: + SETR_32( SD_OPTION,((GETR_32(SD_OPTION) & ~(BIT15|BIT13)) | BIT13 )); + break; + default: + goto EXIT; + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA<<16); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + goto EXIT; + } + + /* CMD8 (EXT_CSD) */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0]), EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + goto EXIT; + } + + return EMMC_SUCCESS; + +EXIT: + + emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, result); + ERROR("BL2: emmc bus_width error end\n"); + return result; +} + +/** @brief select access partition + * + * This function write the EXT_CSD register(PARTITION_ACCESS: PARTITION_CONFIG[2:0]). + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * selected partition can access. + * + * @param[in] id user selects partitions to access. + * @retval EMMC_SUCCESS successful. + * @retval EMMC_ERR_STATE state error. + * @retval EMMC_ERR_PARAM parameter error. + * @return emmc error code. + */ +EMMC_ERROR_CODE emmc_select_partition( + EMMC_PARTITION_ID id + ) +{ + EMMC_ERROR_CODE result; + uint32_t arg; + uint32_t partition_config; + + /* state check */ + if (mmc_drv_obj.mount != TRUE) + { + emmc_write_error_info(EMMC_FUNCNO_NONE, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* id = PARTITION_ACCESS(Bit[2:0]) */ + if ((id & ~PARTITION_ID_MASK) != 0) + { + emmc_write_error_info(EMMC_FUNCNO_NONE, EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* EXT_CSD[179] value */ + partition_config = (uint32_t)mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_PARTITION_CONFIG]; + if ((partition_config & PARTITION_ID_MASK) == id) { + result = EMMC_SUCCESS; + } else { + + partition_config = (uint32_t)((partition_config & ~PARTITION_ID_MASK) | id); + arg = EMMC_SWITCH_PARTITION_CONFIG | (partition_config<<8); + + result = emmc_set_ext_csd(arg); + } + + return result; +} + +/** @brief set EXT CSD data + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * mmc_drv_obj.ext_csd_data[] is updated. + * + * @param[in] arg argument of CMD6 + * @return emmc error code. + */ +EMMC_ERROR_CODE emmc_set_ext_csd( + uint32_t arg + ) +{ + EMMC_ERROR_CODE result; +// st_error_info backup; + + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, arg); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA<<16); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + + /* CMD8 (EXT_CSD) */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0]), EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + return EMMC_SUCCESS; +} + +/** @brief set request MMC clock frequency. + * + * Function returns EMMC_SUCCESS if clock is already running in the desired frequency. + * EMMC_ERR is returned if the HW doesn't support requested clock frequency. + * If matching frequence cannot be set the closest frequence below should be selected. + * For example if 50MHz is requested, but HW supports only 48MHz then 48MHz should be returned in the freq parameter. + * + * - Pre-conditions:
+ * initialized eMMC driver with emmc_init(). + * Memory card and MMCSDIO host controller needs to be powered up beforehand. + * + * - Post-conditions:
+ * Desired clock frequency is set to memory card IF. + * + * @param[in] freq frequency [Hz] + * @retval EMMC_SUCCESS successful. + * @retval EMMC_ERR_STATE state error. + * @retval EMMC_ERR busy + */ +EMMC_ERROR_CODE emmc_set_request_mmc_clock( + uint32_t *freq + ) +{ + /* parameter check */ + if (freq == NULL) + { + emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if ( (mmc_drv_obj.initialize != TRUE) || (mmc_drv_obj.card_power_enable != TRUE) ) + { + emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* clock is already running in the desired frequency. */ + if ( (mmc_drv_obj.clock_enable == TRUE) && (mmc_drv_obj.current_freq == *freq) ) + { + return EMMC_SUCCESS; + } + + /* busy check */ + if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0) + { + emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, EMMC_ERR_CARD_BUSY); + return EMMC_ERR; + } + + set_sd_clk(*freq); + mmc_drv_obj.clock_enable = FALSE; + + return emmc_clock_ctrl(TRUE); /* clock on */ +} + +/** @brief set sd clock. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * set mmc clock. + * + * @param[in] clkDiv request freq + * @return None. + */ +static void set_sd_clk(uint32_t clkDiv) +{ + uint32_t dataL; + + dataL = (GETR_32(SD_CLK_CTRL) & (~SD_CLK_CTRL_CLKDIV_MASK) ); + + switch(clkDiv){ + case 1: dataL |= 0x000000FFU; break; /* 1/1 */ + case 2: dataL |= 0x00000000U; break; /* 1/2 */ + case 4: dataL |= 0x00000001U; break; /* 1/4 */ + case 8: dataL |= 0x00000002U; break; /* 1/8 */ + case 16: dataL |= 0x00000004U; break; /* 1/16 */ + case 32: dataL |= 0x00000008U; break; /* 1/32 */ + case 64: dataL |= 0x00000010U; break; /* 1/64 */ + case 128: dataL |= 0x00000020U; break; /* 1/128 */ + case 256: dataL |= 0x00000040U; break; /* 1/256 */ + case 512: dataL |= 0x00000080U; break; /* 1/512 */ + } + + SETR_32(SD_CLK_CTRL, dataL); + mmc_drv_obj.current_freq = (uint32_t)clkDiv; +} + + +/** @brief Enable/Disable MMC clock + * + * - Pre-conditions:
+ * Before enabling the clock for the first time the desired clock frequency must be set with + * emmc_set_clock_freq(). + * Berore setting mmc_drv_obj.data_timeout with emmc_set_data_timeout(). + * + * - Post-conditions:
+ * After this function is called, clock to memory card IF is on/off. + * + * @param[in] mode TRUE = clock on, FALSE = clock off + * @retval EMMC_SUCCESS succeeded + * @retval EMMC_ERR Busy + */ +static EMMC_ERROR_CODE emmc_clock_ctrl( + uint8_t mode + ) +{ + uint32_t value; + + /* busy check */ + if ((GETR_32(SD_INFO2) & SD_INFO2_CBSY) != 0) + { + emmc_write_error_info(EMMC_FUNCNO_SET_CLOCK, EMMC_ERR_CARD_BUSY); + return EMMC_ERR; + } + + if (mode == TRUE) + { + /* clock ON */ + value = ((GETR_32(SD_CLK_CTRL) | MMC_SD_CLK_START) & SD_CLK_WRITE_MASK); + SETR_32(SD_CLK_CTRL, value); /* on */ + mmc_drv_obj.clock_enable = TRUE; + } + else + { + /* clock OFF */ + value = ((GETR_32(SD_CLK_CTRL) & MMC_SD_CLK_STOP) & SD_CLK_WRITE_MASK); + SETR_32(SD_CLK_CTRL, value); /* off */ + mmc_drv_obj.clock_enable = FALSE; + } + + return EMMC_SUCCESS; +} + +/** @brief Calculate Card support frequency. + * TRAN_SPEED defines the clock frequency when not in high speed mode. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * None. + * @return Frquency[Hz] + */ +static uint32_t emmc_calc_tran_speed( uint32_t* freq ) +{ + const uint32_t unit[8] = {10000, 100000, 1000000, 10000000, 0, 0, 0, 0}; /**< frequency unit (1/10) */ + const uint32_t mult[16] = {0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45, 52, 55, 60, 70, 80}; /**< multiple factor (x10) */ + uint32_t maxFreq; + uint32_t result; + uint32_t tran_speed = EMMC_CSD_TRAN_SPEED(); + + /* tran_speed = 0x32 + * unit[tran_speed&0x7] = uint[0x2] = 1000000 + * mult[(tran_speed&0x78)>>3] = mult[0x30>>3] = mult[6] = 26 + * 1000000 * 26 = 26000000 (26MHz) + */ + + result= 1; + maxFreq = unit[tran_speed&EMMC_TRANSPEED_FREQ_UNIT_MASK] * mult[(tran_speed&EMMC_TRANSPEED_MULT_MASK)>>EMMC_TRANSPEED_MULT_SHIFT]; + + if( maxFreq == 0 ) + { + result= 0; + } + else if( MMC_FREQ_52MHZ <= maxFreq ) + { + *freq = MMC_52MHZ; + } + else if( MMC_FREQ_26MHZ <= maxFreq ) + { + *freq = MMC_26MHZ; + } + else if( MMC_FREQ_20MHZ <= maxFreq ) + { + *freq = MMC_20MHZ; + } + else + { + *freq = MMC_400KHZ; + } + + return result; +} + +/** @brief Calculate read/write timeout. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * set mmc clock. + * + * @param[in] freq Base clock Div + * @return SD_OPTION Timeout Counter + */ +static uint32_t emmc_set_timeout_register_value( + uint32_t freq + ) +{ + uint32_t timeoutCnt=0; /* SD_OPTION - Timeout Counter */ + + switch(freq){ + case 1: timeoutCnt = 0xB0U; break; /* SDCLK * 2^24 */ + case 2: timeoutCnt = 0xA0U; break; /* SDCLK * 2^23 */ + case 4: timeoutCnt = 0x90U; break; /* SDCLK * 2^22 */ + case 8: timeoutCnt = 0x80U; break; /* SDCLK * 2^21 */ + case 16: timeoutCnt = 0x70U; break; /* SDCLK * 2^20 */ + case 32: timeoutCnt = 0x60U; break; /* SDCLK * 2^19 */ + case 64: timeoutCnt = 0x50U; break; /* SDCLK * 2^18 */ + case 128: timeoutCnt = 0x40U; break; /* SDCLK * 2^17 */ + case 256: timeoutCnt = 0x30U; break; /* SDCLK * 2^16 */ + case 512: timeoutCnt = 0x30U; break; /* SDCLK * 2^16 */ + } + + return timeoutCnt; +} + +static void emmc_get_partition_access(void) +{ + uint32_t reg; + EMMC_ERROR_CODE result; + + reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); + if ((reg == RCAR_PRODUCT_H3_CUT20) || (reg == RCAR_PRODUCT_M3_CUT11)) { + SETR_32(SD_OPTION, 0x000060EEU); /* 8 bits width */ + /* CMD8 (EXT_CSD) */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U, + (uint32_t *)(&mmc_drv_obj.ext_csd_data[0]), + EMMC_MAX_EXT_CSD_LENGTH, + HAL_MEMCARD_READ, + HAL_MEMCARD_NOT_DMA); + mmc_drv_obj.get_partition_access_flag = TRUE; + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + mmc_drv_obj.get_partition_access_flag = FALSE; + if (result == EMMC_SUCCESS) + { + mmc_drv_obj.partition_access = + (EMMC_PARTITION_ID)(mmc_drv_obj.ext_csd_data[179] + & PARTITION_ID_MASK); + } else if (result == EMMC_ERR_CMD_TIMEOUT) { + mmc_drv_obj.partition_access = PARTITION_ID_BOOT_1; + } else { + emmc_write_error_info(EMMC_FUNCNO_GET_PERTITION_ACCESS, result); + panic(); + } + SETR_32(SD_OPTION, 0x0000C0EEU); /* Initialize */ + } +} + +static void emmc_set_bootpartition(void) +{ + uint32_t reg; + + reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); + if (reg == RCAR_PRODUCT_M3_CUT10) { + mmc_drv_obj.boot_partition_en = + (EMMC_PARTITION_ID)((mmc_drv_obj.ext_csd_data[179] & + EMMC_BOOT_PARTITION_EN_MASK) >> + EMMC_BOOT_PARTITION_EN_SHIFT); + } else if ((reg == RCAR_PRODUCT_H3_CUT20) || (reg == RCAR_PRODUCT_M3_CUT11)) { + mmc_drv_obj.boot_partition_en = mmc_drv_obj.partition_access; + } else { + if ((mmio_read_32(MFISBTSTSR) & MFISBTSTSR_BOOT_PARTITION) != 0U) { + mmc_drv_obj.boot_partition_en = PARTITION_ID_BOOT_2; + } else { + mmc_drv_obj.boot_partition_en = PARTITION_ID_BOOT_1; + } + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_read.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_read.c new file mode 100644 index 0000000..2ba19ef --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/emmc/emmc_read.c @@ -0,0 +1,212 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file emmc_read.c + * @brief read api + * + */ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +#define MIN(a,b) (((a) < (b)) ? (a) : (b)) + +#define EMMC_RW_SECTOR_COUNT_MAX 0x0000ffffUL + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +static EMMC_ERROR_CODE emmc_multiple_block_read (uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode); + + +/* ********************************* CODE ********************************** */ + +/** @brief function of read sector + * + * This function always use block read. + * Single block read is not used. + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * . + * + * @param[in,out] buff_address_virtual virtual address of read data buffer. + * @param[in] sector_number data address for MMC device (sector number). + * @param[in] count number of sector. + * @param[in] transfer_mode Mode of data transfer, DMA or not DMA. + */ +EMMC_ERROR_CODE emmc_read_sector ( + uint32_t *buff_address_virtual, + uint32_t sector_number, + uint32_t count, + uint32_t feature_flags + ) +{ + uint32_t trans_count; + uint32_t remain; + EMMC_ERROR_CODE result; + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; + + /* parameter check */ + if (count == 0) + { + emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.mount != TRUE) + { + emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* DMA? */ + if ((feature_flags & LOADIMAGE_FLAGS_DMA_ENABLE) != 0) + { + transfer_mode = HAL_MEMCARD_DMA; + } + else + { + transfer_mode = HAL_MEMCARD_NOT_DMA; + } + + remain = count; + while (remain != 0) + { + trans_count = MIN(remain, EMMC_RW_SECTOR_COUNT_MAX); + result = emmc_multiple_block_read(buff_address_virtual, sector_number, trans_count, transfer_mode); + if (result != EMMC_SUCCESS) + { + return result; + } + + buff_address_virtual += (EMMC_BLOCK_LENGTH_DW*trans_count); + sector_number += trans_count; + remain -= trans_count; + } + + return EMMC_SUCCESS; +} + +/** @brief multiple block read + * + * Multiple block read with pre-defined block count. + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * . + * + * @param[in,out] buff_address_virtual virtual address of read data buffer. + * @param[in] sector_number data address for MMC device (sector number). + * @param[in] count number of sector. (0x1 - 0xffff) + * @param[in] transfer_mode Mode of data transfer, DMA or not DMA. + */ +static EMMC_ERROR_CODE emmc_multiple_block_read + ( + uint32_t *buff_address_virtual, + uint32_t sector_number, + uint32_t count, + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode + ) +{ + EMMC_ERROR_CODE result; +// st_error_info backup; + + /* parameter check */ + if ((count > EMMC_RW_SECTOR_COUNT_MAX) + || (count == 0) + || ((transfer_mode != HAL_MEMCARD_DMA) && (transfer_mode != HAL_MEMCARD_NOT_DMA)) + ) + { + emmc_write_error_info(EMMC_FUNCNO_READ_SECTOR, EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* CMD23 */ + emmc_make_nontrans_cmd(CMD23_SET_BLOCK_COUNT, count); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + SETR_32( SD_SECCNT, count ); + SETR_32( SD_STOP, 0x00000100 ); + SETR_32( CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE) ); /* SD_BUF Read/Write DMA Transfer enable */ + + /* CMD18 */ + emmc_make_trans_cmd(CMD18_READ_MULTIPLE_BLOCK, sector_number, buff_address_virtual, count< +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +static const uint32_t cmd_reg_hw[EMMC_CMD_MAX+1]= { + 0x00000000, /* CMD0 */ + 0x00000701, /* CMD1 */ + 0x00000002, /* CMD2 */ + 0x00000003, /* CMD3 */ + 0x00000004, /* CMD4 */ + 0x00000505, /* CMD5 */ + 0x00000406, /* CMD6 */ + 0x00000007, /* CMD7 */ + 0x00001C08, /* CMD8 */ + 0x00000009, /* CMD9 */ + 0x0000000A, /* CMD10 */ + 0x00000000, /* reserved */ + 0x0000000C, /* CMD12 */ + 0x0000000D, /* CMD13 */ + 0x00001C0E, /* CMD14 */ + 0x0000000F, /* CMD15 */ + 0x00000010, /* CMD16 */ + 0x00000011, /* CMD17 */ + 0x00007C12, /* CMD18 */ + 0x00000C13, /* CMD19 */ + 0x00000000, + 0x00001C15, /* CMD21 */ + 0x00000000, + 0x00000017, /* CMD23 */ + 0x00000018, /* CMD24 */ + 0x00006C19, /* CMD25 */ + 0x00000C1A, /* CMD26 */ + 0x0000001B, /* CMD27 */ + 0x0000001C, /* CMD28 */ + 0x0000001D, /* CMD29 */ + 0x0000001E, /* CMD30 */ + 0x00001C1F, /* CMD31 */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000423, /* CMD35 */ + 0x00000424, /* CMD36 */ + 0x00000000, + 0x00000026, /* CMD38 */ + 0x00000427, /* CMD39 */ + 0x00000428, /* CMD40(send cmd) */ + 0x00000000, + 0x0000002A, /* CMD42 */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000C31, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00007C35, + 0x00006C36, + 0x00000037, /* CMD55 */ + 0x00000038, /* CMD56(Read) */ + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000 +}; +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +/** @brief make non-transfer command data + * + * Response data buffer is automatically selected. + * + * - Pre-conditions:
+ * Clock to memory card IF is enabled. + * + * - Post-conditions:
+ * After this function is called, command can be executed. + * + * @param[in] cmd command information. + * @param[in] arg command argument + * @return None. + */ +void emmc_make_nontrans_cmd ( + HAL_MEMCARD_COMMAND cmd, + uint32_t arg + ) +{ + /* command information */ + mmc_drv_obj.cmd_info.cmd = cmd; + mmc_drv_obj.cmd_info.arg = arg; + mmc_drv_obj.cmd_info.dir = HAL_MEMCARD_READ; + mmc_drv_obj.cmd_info.hw = cmd_reg_hw[cmd&HAL_MEMCARD_COMMAND_INDEX_MASK]; + + /* clear data transfer information */ + mmc_drv_obj.trans_size = 0; + mmc_drv_obj.remain_size = 0; + mmc_drv_obj.buff_address_virtual = NULL; + mmc_drv_obj.buff_address_physical = NULL; + + /* response information */ + mmc_drv_obj.response_length = 6; + + switch (mmc_drv_obj.cmd_info.cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK) + { + case HAL_MEMCARD_RESPONSE_NONE: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + mmc_drv_obj.response_length = 0; + break; + case HAL_MEMCARD_RESPONSE_R1: + mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; + break; + case HAL_MEMCARD_RESPONSE_R1b: + mmc_drv_obj.cmd_info.hw |= BIT10; /* bit10 = R1 busy bit */ + mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; + break; + case HAL_MEMCARD_RESPONSE_R2: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + mmc_drv_obj.response_length = 17; + break; + case HAL_MEMCARD_RESPONSE_R3: + mmc_drv_obj.response = &mmc_drv_obj.r3_ocr; + break; + case HAL_MEMCARD_RESPONSE_R4: + mmc_drv_obj.response = &mmc_drv_obj.r4_resp; + break; + case HAL_MEMCARD_RESPONSE_R5: + mmc_drv_obj.response = &mmc_drv_obj.r5_resp; + break; + default : + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + break; + } +} + +/** @brief Making command information for data transfer command. + * + * - Pre-conditions:
+ * None. + * + * - Post-conditions:
+ * After this function is called, command can be executed. + * + * @param[in] cmd command + * @param[in] arg command argument + * @param[in] buff_address_virtual Pointer to buffer where data is/will be stored. (virtual address) + * Client is responsible of allocation and deallocation of the buffer. + * @param[in] len transfer length in bytes + * @param[in] dir direction + * @param[in] transfer_mode Mode of data transfer, DMA or not DMA. + * @return None. + */ +void emmc_make_trans_cmd ( + HAL_MEMCARD_COMMAND cmd, + uint32_t arg, + uint32_t *buff_address_virtual, /* virtual address */ + uint32_t len, + HAL_MEMCARD_OPERATION dir, + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode + ) +{ + emmc_make_nontrans_cmd(cmd, arg); /* update common information */ + + /* for data transfer command */ + mmc_drv_obj.cmd_info.dir = dir; + mmc_drv_obj.buff_address_virtual = buff_address_virtual; + mmc_drv_obj.buff_address_physical = buff_address_virtual; + mmc_drv_obj.trans_size = len; + mmc_drv_obj.remain_size = len; + mmc_drv_obj.transfer_mode = transfer_mode; +} + +/** @brief Send idle command. + * Function execute CMD0. + * + * - Pre-conditions:
+ * Clock to MMC I/F enabled. + * + * - Post-conditions:
+ * Card reset to idle or pre-idle state. + * + * @param[in] arg CMD0 argument. + * @return error code + */ +EMMC_ERROR_CODE emmc_send_idle_cmd ( + uint32_t arg + ) +{ + EMMC_ERROR_CODE result; + uint32_t freq; + + /* initialize state */ + mmc_drv_obj.mount = FALSE; + mmc_drv_obj.selected = FALSE; + mmc_drv_obj.during_transfer = FALSE; + mmc_drv_obj.during_cmd_processing = FALSE; + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.dma_error_flag = FALSE; + mmc_drv_obj.force_terminate = FALSE; + mmc_drv_obj.state_machine_blocking = FALSE; + + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; + mmc_drv_obj.max_freq = MMC_20MHZ; /* 20MHz */ + mmc_drv_obj.current_state = EMMC_R1_STATE_IDLE; + + /* CMD0 (MMC clock is current frequency. if Data transfer mode, 20MHz or higher.) */ + emmc_make_nontrans_cmd(CMD0_GO_IDLE_STATE, arg); /* CMD0 */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + + /* change MMC clock(400KHz) */ + freq = MMC_400KHZ; + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) + { + return result; + } + + return EMMC_SUCCESS; +} + +/** @brief get bit field data for 16bytes data(CSD register). + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * @param[in] data 16bytes data. + * @param[in] top bit number(top). 128>top + * @param[in] bottom bit number(bottom). (0<=bottom<=top) + * @return bit field. + */ +uint32_t emmc_bit_field (uint8_t *data, uint32_t top, uint32_t bottom) +{ + uint32_t value; + + uint32_t index_top = (uint32_t)(15-(top>>3)); + uint32_t index_bottom = (uint32_t)(15-(bottom>>3)); + + if (index_top == index_bottom) + { + value = data[index_top]; + } + else if ((index_top+1) == index_bottom) + { + value = (uint32_t)((data[index_top]<<8) | data[index_bottom]); + } + else if ((index_top+2) == index_bottom) + { + value = (uint32_t)((data[index_top]<<16) | (data[index_top+1]<<8) | data[index_top+2]); + } + else + { + value = (uint32_t)((data[index_top]<<24) | (data[index_top+1]<<16) | (data[index_top+2]<<8) | data[index_top+3]); + } + + value = ((value >> (bottom&0x07)) & ((1<<(top-bottom+1))-1)); + + return value; +} + +/** @brief set error information + * + * eMMC driver's error information is 16bytes. + * Format is the following, + * + * - Function No (2byte) + * - Error code (2byte) + * - Interrupt flag (4byte) + * - Interrupt status1 (4byte) + * - Interrupt status2 (4byte) + * + * - Pre-conditions:
+ * . + * + * - Post-conditions:
+ * . + * + * @param[in] func_no function number. + * @param[in] error_code EMMC error code. + * @return None. + */ +void emmc_write_error_info( + uint16_t func_no, + EMMC_ERROR_CODE error_code + ) +{ + + mmc_drv_obj.error_info.num = func_no; + mmc_drv_obj.error_info.code = (uint16_t)error_code; + + ERROR("BL2: emmc err:func_no=0x%x code=0x%x\n", func_no, error_code); +} + + +/** @brief set error function number + * + * Write function Number only. + * eMMC driver's error information is 16bytes. + * Format is the following, + * + * - Function No (2byte) + * - Error code (2byte) + * - Interrupt flag (4byte) + * - Interrupt status1 (4byte) + * - Interrupt status2 (4byte) + * + * - Pre-conditions:
+ * . + * + * - Post-conditions:
+ * . + * + * @param[in] func_no function number + * @return None. + */ +void emmc_write_error_info_func_no ( + uint16_t func_no + ) +{ + + mmc_drv_obj.error_info.num = func_no; + + ERROR("BL2: emmc err:func_no=0x%x\n", func_no); +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/error/bl2_int_error.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/error/bl2_int_error.c new file mode 100644 index 0000000..3090a95 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/error/bl2_int_error.c @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "bl2_int_error.h" +#include "rcar_def.h" + +#define SWDT_ERROR_ID (1024U) +#define SWDT_ERROR_TYPE (16U) +#define SWDT_CHAR_MAX (13U) + +void bl2_interrupt_error_id(uint32_t int_id) +{ + ERROR("\n"); + if (int_id >= SWDT_ERROR_ID) { + ERROR("BL2: Unhandled exception occurred.\n"); + ERROR(" Exception type = FIQ_SP_ELX\n"); + /* Endless loop */ + panic(); + } + /* Clear the interrupt request */ + gicv2_end_of_interrupt((uint32_t)int_id); + bl2_swdt_release(); + ERROR("BL2: Unhandled exception occurred.\n"); + ERROR(" Exception type = FIQ_SP_ELX\n"); + ERROR(" SPSR_EL1 = 0x%x\n", + (uint32_t)(read_spsr_el1() & 0x0FFFFFFFFU)); + ERROR(" ELR_EL1 = 0x%x\n", + (uint32_t)(read_elr_el1() & 0x0FFFFFFFFU)); + ERROR(" ESR_EL1 = 0x%x\n", + (uint32_t)(read_esr_el1() & 0x0FFFFFFFFU)); + ERROR(" FAR_EL1 = 0x%x\n", + (uint32_t)(read_far_el1() & 0x0FFFFFFFFU)); + ERROR("\n"); + /* Endless loop */ + panic(); +} + +void bl2_interrupt_error_type(uint32_t ex_type) +{ + const uint8_t interrupt_ex[SWDT_ERROR_TYPE][SWDT_CHAR_MAX] = { + "SYNC SP EL0", + "IRQ SP EL0", + "FIQ SP EL0", + "SERR SP EL0", + "SYNC SP ELx", + "IRQ SP ELx", + "FIQ SP ELx", + "SERR SP ELx", + "SYNC AARCH64", + "IRQ AARCH64", + "FIQ AARCH64", + "SERR AARCH64", + "SYNC AARCH32", + "IRQ AARCH32", + "FIQ AARCH32", + "SERR AARCH32" + }; + char msg[128]; + + /* Clear the interrupt request */ + if (ex_type >= SWDT_ERROR_TYPE) { + ERROR("\n"); + ERROR("BL2: Unhandled exception occurred.\n"); + ERROR(" Exception type = Unknown (%d)\n", ex_type); + } else { + bl2_swdt_release(); + ERROR("\n"); + ERROR("BL2: Unhandled exception occurred.\n"); + (void)sprintf(msg, " Exception type = %s\n", + &interrupt_ex[ex_type][0]); + ERROR("%s", msg); + switch(ex_type) + { + case SYNC_EXCEPTION_SP_ELX: + ERROR(" SPSR_EL1 = 0x%x\n", + (uint32_t)(read_spsr_el1() & 0x0FFFFFFFFU)); + ERROR(" ELR_EL1 = 0x%x\n", + (uint32_t)(read_elr_el1() & 0x0FFFFFFFFU)); + ERROR(" ESR_EL1 = 0x%x\n", + (uint32_t)(read_esr_el1() & 0x0FFFFFFFFU)); + ERROR(" FAR_EL1 = 0x%x\n", + (uint32_t)(read_far_el1() & 0x0FFFFFFFFU)); + break; + case IRQ_SP_ELX: + ERROR(" SPSR_EL1 = 0x%x\n", + (uint32_t)(read_spsr_el1() & 0x0FFFFFFFFU)); + ERROR(" ELR_EL1 = 0x%x\n", + (uint32_t)(read_elr_el1() & 0x0FFFFFFFFU)); + ERROR(" IAR_EL1 = 0x%x\n", + gicv2_acknowledge_interrupt()); + break; + case FIQ_SP_ELX: + ERROR(" SPSR_EL1 = 0x%x\n", + (uint32_t)(read_spsr_el1() & 0x0FFFFFFFFU)); + ERROR(" ELR_EL1 = 0x%x\n", + (uint32_t)(read_elr_el1() & 0x0FFFFFFFFU)); + ERROR(" IAR_EL1 = 0x%x\n", + gicv2_acknowledge_interrupt()); + break; + case SERROR_SP_ELX: + ERROR(" SPSR_EL1 = 0x%x\n", + (uint32_t)(read_spsr_el1() & 0x0FFFFFFFFU)); + ERROR(" ELR_EL1 = 0x%x\n", + (uint32_t)(read_elr_el1() & 0x0FFFFFFFFU)); + ERROR(" ESR_EL1 = 0x%x\n", + (uint32_t)(read_esr_el1() & 0x0FFFFFFFFU)); + ERROR(" FAR_EL1 = 0x%x\n", + (uint32_t)(read_far_el1() & 0x0FFFFFFFFU)); + break; + default: + break; + } + } + ERROR("\n"); + /* Endless loop */ + panic(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.c new file mode 100644 index 0000000..9ecc8f6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.c @@ -0,0 +1,700 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "rcar_def.h" +#include "bl2_cpg_register.h" +#include "iic_dvfs.h" + +#define DVFS_RETRY_MAX (2U) + +#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_0 (0x07U) +#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_1 (0x09U) +#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_2 (0x0BU) +#define IIC_DVFS_SET_ICCL_EXTAL_TYPE_3 (0x0EU) + +#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_0 (0x01U) +#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_1 (0x02U) +#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_2 (0x03U) +#define IIC_DVFS_SET_ICCH_EXTAL_TYPE_3 (0x05U) + +#define CPG_BIT_SMSTPCR9_DVFS (0x04000000U) + +#define IIC_DVFS_REG_BASE (0xE60B0000U) +#define IIC_DVFS_REG_ICDR (IIC_DVFS_REG_BASE + 0x0000U) +#define IIC_DVFS_REG_ICCR (IIC_DVFS_REG_BASE + 0x0004U) +#define IIC_DVFS_REG_ICSR (IIC_DVFS_REG_BASE + 0x0008U) +#define IIC_DVFS_REG_ICIC (IIC_DVFS_REG_BASE + 0x000CU) +#define IIC_DVFS_REG_ICCL (IIC_DVFS_REG_BASE + 0x0010U) +#define IIC_DVFS_REG_ICCH (IIC_DVFS_REG_BASE + 0x0014U) + +#define IIC_DVFS_BIT_ICSR_BUSY (0x10U) +#define IIC_DVFS_BIT_ICSR_AL (0x08U) +#define IIC_DVFS_BIT_ICSR_TACK (0x04U) +#define IIC_DVFS_BIT_ICSR_WAIT (0x02U) +#define IIC_DVFS_BIT_ICSR_DTE (0x01U) + +#define IIC_DVFS_BIT_ICCR_ENABLE (0x80U) +#define IIC_DVFS_SET_ICCR_START (0x94U) +#define IIC_DVFS_SET_ICCR_STOP (0x90U) +#define IIC_DVFS_SET_ICCR_RETRANSMISSION (0x94U) +#define IIC_DVFS_SET_ICCR_CHANGE (0x81U) +#define IIC_DVFS_SET_ICCR_STOP_READ (0xC0U) + +#define IIC_DVFS_BIT_ICIC_TACKE (0x04U) +#define IIC_DVFS_BIT_ICIC_WAITE (0x02U) +#define IIC_DVFS_BIT_ICIC_DTEE (0x01U) + +#define DVFS_READ_MODE (0x01U) +#define DVFS_WRITE_MODE (0x00U) + +#define IIC_DVFS_SET_DUMMY (0x52U) +#define IIC_DVFS_SET_BUSY_LOOP (500000000U) + +typedef enum { + DVFS_START_CONDITION = 0, + DVFS_SET_SLAVE_ADDR, + DVFS_WRITE_REG_ADDR, + DVFS_WRITE_REG_DATA, + DVFS_STOP_CONDITION, + DVFS_PROCESS_COMPLETE, + DVFS_SET_RETRANSMISSION_CONDITION, + DVFS_SET_SLAVE_ADDR_READ, + DVFS_CHANGE_SEND_TO_RECIEVE, + DVFS_STOP_CONDITION_READ, + DVFS_READ_REG_DATA +}DVFS_STATUS_T; + +#define DVFS_PROCESS (1) +#define DVFS_COMPLETE (0) +#define DVFS_ERROR (-1) + +static int32_t dvfs_check_error(DVFS_STATUS_T *status, uint32_t *err_count, uint8_t mode); +static int32_t dvfs_start_condition(DVFS_STATUS_T *status); +static int32_t dvfs_set_slave_addr(DVFS_STATUS_T *status, uint32_t *err_count, uint8_t slave_addr); +static int32_t dvfs_write_reg_addr(DVFS_STATUS_T *status, uint32_t *err_count, uint8_t reg_addr); +static int32_t dvfs_write_reg_data(DVFS_STATUS_T *status, uint32_t *err_count, uint8_t reg_data); +static int32_t dvfs_stop_condition(DVFS_STATUS_T *status, uint32_t *err_count); +static int32_t dvfs_process_complete(void); +static int32_t dvfs_write_reg_addr_read(DVFS_STATUS_T *status, uint32_t *err_count, uint8_t reg_addr); +static int32_t dvfs_set_retransmission_condition(DVFS_STATUS_T *status, uint32_t *err_count); +static int32_t dvfs_set_slave_addr_read(DVFS_STATUS_T *status, uint32_t *err_count, uint8_t slave_addr); +static int32_t dvfs_change_send_to_recieve(DVFS_STATUS_T *status, uint32_t *err_count); +static int32_t dvfs_stop_condition_read(DVFS_STATUS_T *status, uint32_t *err_count); +static int32_t dvfs_read_reg_data(DVFS_STATUS_T *status, uint8_t *reg_data); + +int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + rcar_iic_dvfs_send( + uint8_t slave_addr, uint8_t reg_addr, uint8_t reg_data) +{ + int32_t result; + uint32_t reg; + DVFS_STATUS_T status; + uint32_t err_count; + + /* Clock supply of DVFS is enabled */ + reg = mmio_read_32(SCMSTPCR9) & ~CPG_BIT_SMSTPCR9_DVFS; + mmio_write_32(RCAR_CPGWPR, ~reg); + mmio_write_32(SCMSTPCR9, reg); + while ((mmio_read_32(SCMSTPCR9) & CPG_BIT_SMSTPCR9_DVFS) + != 0x00000000U) { + } + + /* Disable IIC-DVFS module */ + mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U); + + status = DVFS_START_CONDITION; + result = DVFS_PROCESS; + err_count = 0U; + + while (result == DVFS_PROCESS) { + switch (status) { + case DVFS_START_CONDITION: + result = dvfs_start_condition(&status); + break; + case DVFS_SET_SLAVE_ADDR: + result = dvfs_set_slave_addr(&status, &err_count, slave_addr); + break; + case DVFS_WRITE_REG_ADDR: + result = dvfs_write_reg_addr(&status, &err_count, reg_addr); + break; + case DVFS_WRITE_REG_DATA: + result = dvfs_write_reg_data(&status, &err_count, reg_data); + break; + case DVFS_STOP_CONDITION: + result = dvfs_stop_condition(&status, &err_count); + break; + case DVFS_PROCESS_COMPLETE: + result = dvfs_process_complete(); + break; + default: + panic(); + break; + } + } + + return result; +} + +int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + rcar_iic_dvfs_recieve( + uint8_t slave_addr, uint8_t reg_addr, uint8_t *reg_data) +{ + int32_t result; + uint32_t reg; + DVFS_STATUS_T status; + uint32_t err_count; + + /* Clock supply of DVFS is enabled */ + reg = mmio_read_32(SCMSTPCR9) & ~CPG_BIT_SMSTPCR9_DVFS; + mmio_write_32(RCAR_CPGWPR, ~reg); + mmio_write_32(SCMSTPCR9, reg); + while ((mmio_read_32(SCMSTPCR9) & CPG_BIT_SMSTPCR9_DVFS) + != 0x00000000U) { + } + + /* Disable IIC-DVFS module */ + mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U); + + status = DVFS_START_CONDITION; + result = DVFS_PROCESS; + err_count = 0U; + + while (result == DVFS_PROCESS) { + switch (status) { + case DVFS_START_CONDITION: + result = dvfs_start_condition(&status); + break; + case DVFS_SET_SLAVE_ADDR: + result = dvfs_set_slave_addr(&status, &err_count, slave_addr); + break; + case DVFS_WRITE_REG_ADDR: + result = dvfs_write_reg_addr_read(&status, &err_count, reg_addr); + break; + case DVFS_SET_RETRANSMISSION_CONDITION: + result = dvfs_set_retransmission_condition(&status, &err_count); + break; + case DVFS_SET_SLAVE_ADDR_READ: + result = dvfs_set_slave_addr_read(&status, &err_count, slave_addr); + break; + case DVFS_CHANGE_SEND_TO_RECIEVE: + result = dvfs_change_send_to_recieve(&status, &err_count); + break; + case DVFS_STOP_CONDITION_READ: + result = dvfs_stop_condition_read(&status, &err_count); + break; + case DVFS_READ_REG_DATA: + result = dvfs_read_reg_data(&status, reg_data); + break; + case DVFS_PROCESS_COMPLETE: + result = dvfs_process_complete(); + break; + default: + panic(); + break; + } + } + + return result; +} + +static int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + dvfs_check_error( + DVFS_STATUS_T *status, uint32_t *err_count, uint8_t mode) +{ + int32_t error; + uint8_t reg; + uint32_t loop_cnt; + uint8_t stop_code; + + stop_code = IIC_DVFS_SET_ICCR_STOP; + if (mode == DVFS_READ_MODE) { + stop_code = IIC_DVFS_SET_ICCR_STOP_READ; + } + reg = mmio_read_8(IIC_DVFS_REG_ICSR); + if ((reg & IIC_DVFS_BIT_ICSR_AL) == IIC_DVFS_BIT_ICSR_AL) { + reg = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_AL)); + /* Clear the AL flag */ + mmio_write_8(IIC_DVFS_REG_ICSR, reg); + if (*status == DVFS_SET_SLAVE_ADDR) { + mmio_write_8(IIC_DVFS_REG_ICDR, IIC_DVFS_SET_DUMMY); + } + while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_WAIT) + == 0x00U) { + } + /* Write stop condition */ + mmio_write_8(IIC_DVFS_REG_ICCR, stop_code); + /* Clear the WAIT flag */ + reg = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_WAIT)); + mmio_write_8(IIC_DVFS_REG_ICSR, reg); + loop_cnt = 0U; + while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) + != 0x00U) { + loop_cnt++; + if (loop_cnt > IIC_DVFS_SET_BUSY_LOOP) { + panic(); + } + } + mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U); + /* error count increment */ + (*err_count)++; + if (*err_count >= DVFS_RETRY_MAX) { + error = DVFS_ERROR; + } else { + /* status initialize */ + *status = DVFS_START_CONDITION; + error = DVFS_PROCESS; + } + } else if ((reg & IIC_DVFS_BIT_ICSR_TACK) == IIC_DVFS_BIT_ICSR_TACK) { + /* Write stop condition */ + mmio_write_8(IIC_DVFS_REG_ICCR, stop_code); + /* Disable WAIT and DTE interrupt */ + reg = mmio_read_8(IIC_DVFS_REG_ICIC); + reg &= ((uint8_t)(~(IIC_DVFS_BIT_ICIC_WAITE | IIC_DVFS_BIT_ICIC_DTEE))); + mmio_write_8(IIC_DVFS_REG_ICIC, reg); + /* Clear the TACK flag */ + reg = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_TACK)); + mmio_write_8(IIC_DVFS_REG_ICSR, reg); + loop_cnt = 0U; + while ((mmio_read_8(IIC_DVFS_REG_ICSR) & IIC_DVFS_BIT_ICSR_BUSY) + != 0x00U) { + loop_cnt++; + if (loop_cnt > IIC_DVFS_SET_BUSY_LOOP) { + panic(); + } + } + mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U); + (*err_count)++; + if (*err_count >= DVFS_RETRY_MAX) { + error = DVFS_ERROR; + } else { + /* status initialize */ + *status = DVFS_START_CONDITION; + error = DVFS_PROCESS; + } + } else { + error = DVFS_PROCESS; + } + + return error; +} + +static int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + dvfs_start_condition( + DVFS_STATUS_T *status) +{ + uint32_t reg; + uint8_t mode; + int32_t result; + + result = DVFS_PROCESS; + /* Set ICCR.ICE */ + mode = mmio_read_8(IIC_DVFS_REG_ICCR) + | ((uint8_t)(IIC_DVFS_BIT_ICCR_ENABLE)); + mmio_write_8(IIC_DVFS_REG_ICCR, mode); + /* Set clock */ + reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14; + switch (reg) { + case MD14_MD13_TYPE_0: + mmio_write_8(IIC_DVFS_REG_ICCL, IIC_DVFS_SET_ICCL_EXTAL_TYPE_0); + mmio_write_8(IIC_DVFS_REG_ICCH, IIC_DVFS_SET_ICCH_EXTAL_TYPE_0); + break; + case MD14_MD13_TYPE_1: + mmio_write_8(IIC_DVFS_REG_ICCL, IIC_DVFS_SET_ICCL_EXTAL_TYPE_1); + mmio_write_8(IIC_DVFS_REG_ICCH, IIC_DVFS_SET_ICCH_EXTAL_TYPE_1); + break; + case MD14_MD13_TYPE_2: + mmio_write_8(IIC_DVFS_REG_ICCL, IIC_DVFS_SET_ICCL_EXTAL_TYPE_2); + mmio_write_8(IIC_DVFS_REG_ICCH, IIC_DVFS_SET_ICCH_EXTAL_TYPE_2); + break; + case MD14_MD13_TYPE_3: + mmio_write_8(IIC_DVFS_REG_ICCL, IIC_DVFS_SET_ICCL_EXTAL_TYPE_3); + mmio_write_8(IIC_DVFS_REG_ICCH, IIC_DVFS_SET_ICCH_EXTAL_TYPE_3); + break; + default: + mmio_write_8(IIC_DVFS_REG_ICCL, IIC_DVFS_SET_ICCL_EXTAL_TYPE_3); + mmio_write_8(IIC_DVFS_REG_ICCH, IIC_DVFS_SET_ICCH_EXTAL_TYPE_3); + break; + } + /* Set ICIC.TACKE, ICIC.WAITE and ICIC.DTEE */ + mode = mmio_read_8(IIC_DVFS_REG_ICIC) + | IIC_DVFS_BIT_ICIC_TACKE + | IIC_DVFS_BIT_ICIC_WAITE + | IIC_DVFS_BIT_ICIC_DTEE; + mmio_write_8(IIC_DVFS_REG_ICIC, mode); + /* Write start condition */ + mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_START); + /* Next status */ + *status = DVFS_SET_SLAVE_ADDR; + + return result; +} + +static int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + dvfs_set_slave_addr( + DVFS_STATUS_T *status, uint32_t *err_count, uint8_t slave_addr) +{ + uint8_t mode; + int32_t result; + uint8_t address; + + /* error check */ + result = dvfs_check_error(status, err_count, DVFS_WRITE_MODE); + if (result != DVFS_ERROR) { + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)IIC_DVFS_BIT_ICSR_DTE); + if (mode == ((uint8_t)IIC_DVFS_BIT_ICSR_DTE)) { + /* Clear ICIC.DTEE */ + mode = mmio_read_8(IIC_DVFS_REG_ICIC) + & ((uint8_t)(~IIC_DVFS_BIT_ICIC_DTEE)); + mmio_write_8(IIC_DVFS_REG_ICIC, mode); + /* Send 7bit slave address + write mode bit */ + address = (uint8_t)(slave_addr << 1); + mmio_write_8(IIC_DVFS_REG_ICDR, address); + /* Next status */ + *status = DVFS_WRITE_REG_ADDR; + } + } + + return result; +} + +static int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + dvfs_write_reg_addr( + DVFS_STATUS_T *status, uint32_t *err_count, uint8_t reg_addr) +{ + uint8_t mode; + int32_t result; + + result = dvfs_check_error(status, err_count, DVFS_WRITE_MODE); + if (result != DVFS_ERROR) { + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT); + if (mode == ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT)) { + /* Send register address */ + mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr); + /* Clear ICSR.WAIT */ + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_WAIT)); + mmio_write_8(IIC_DVFS_REG_ICSR, mode); + /* Next status */ + *status = DVFS_WRITE_REG_DATA; + } + } + + return result; +} + +static int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + dvfs_write_reg_data( + DVFS_STATUS_T *status, uint32_t *err_count, uint8_t reg_data) +{ + uint8_t mode; + int32_t result; + + result = dvfs_check_error(status, err_count, DVFS_WRITE_MODE); + if (result != DVFS_ERROR) { + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT); + if (mode == ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT)) { + /* Send data */ + mmio_write_8(IIC_DVFS_REG_ICDR, reg_data); + /* Clear ICSR.WAIT */ + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_WAIT)); + mmio_write_8(IIC_DVFS_REG_ICSR, mode); + /* Next status */ + *status = DVFS_STOP_CONDITION; + } + } + + return result; +} + +static int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + dvfs_stop_condition( + DVFS_STATUS_T *status, uint32_t *err_count) +{ + uint8_t mode; + int32_t result; + + result = dvfs_check_error(status, err_count, DVFS_WRITE_MODE); + if (result != DVFS_ERROR) { + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT); + if (mode == ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT)) { + /* Write stop condition */ + mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP); + /* Clear ICSR.WAIT */ + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_WAIT)); + mmio_write_8(IIC_DVFS_REG_ICSR, mode); + /* Next status */ + *status = DVFS_PROCESS_COMPLETE; + } + } + + return result; +} + +static int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + dvfs_process_complete( + void) +{ + int32_t result; + uint32_t loop_cnt; + + loop_cnt = 0U; + while ((mmio_read_8(IIC_DVFS_REG_ICSR) & ((uint8_t)IIC_DVFS_BIT_ICSR_BUSY)) + != 0x00U) { + loop_cnt++; + if (loop_cnt > IIC_DVFS_SET_BUSY_LOOP) { + panic(); + } + } + + /* Disable IIC for DVFS */ + mmio_write_8(IIC_DVFS_REG_ICCR, 0x00U); + /* process complete */ + result = DVFS_COMPLETE; + + return result; +} + +static int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + dvfs_write_reg_addr_read( + DVFS_STATUS_T *status, uint32_t *err_count, uint8_t reg_addr) +{ + uint8_t mode; + int32_t result; + + result = dvfs_check_error(status, err_count, DVFS_WRITE_MODE); + if (result != DVFS_ERROR) { + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT); + if (mode == ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT)) { + /* Send register address */ + mmio_write_8(IIC_DVFS_REG_ICDR, reg_addr); + /* Clear ICSR.WAIT */ + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_WAIT)); + mmio_write_8(IIC_DVFS_REG_ICSR, mode); + /* Next status */ + *status = DVFS_SET_RETRANSMISSION_CONDITION; + } + } + + return result; +} + +static int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + dvfs_set_retransmission_condition( + DVFS_STATUS_T *status, uint32_t *err_count) +{ + uint8_t mode; + int32_t result; + + result = dvfs_check_error(status, err_count, DVFS_WRITE_MODE); + if (result != DVFS_ERROR) { + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT); + if (mode == ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT)) { + /* set ReTransmission condition */ + mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_RETRANSMISSION); + /* Clear ICSR.WAIT */ + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_WAIT)); + mmio_write_8(IIC_DVFS_REG_ICSR, mode); + /* Set ICIC.DTEE */ + mode = mmio_read_8(IIC_DVFS_REG_ICIC) | IIC_DVFS_BIT_ICIC_DTEE; + mmio_write_8(IIC_DVFS_REG_ICIC, mode); + /* Next status */ + *status = DVFS_SET_SLAVE_ADDR_READ; + } + } + + return result; +} + +static int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + dvfs_set_slave_addr_read( + DVFS_STATUS_T *status, uint32_t *err_count, uint8_t slave_addr) +{ + uint8_t mode; + int32_t result; + uint8_t address; + + /* error check */ + result = dvfs_check_error(status, err_count, DVFS_WRITE_MODE); + if (result != DVFS_ERROR) { + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)IIC_DVFS_BIT_ICSR_DTE); + if (mode == ((uint8_t)IIC_DVFS_BIT_ICSR_DTE)) { + /* Clear ICIC.DTEE */ + mode = mmio_read_8(IIC_DVFS_REG_ICIC) + & ((uint8_t)(~IIC_DVFS_BIT_ICIC_DTEE)); + mmio_write_8(IIC_DVFS_REG_ICIC, mode); + /* Send 7bit slave address + read mode bit */ + address = ((uint8_t)(slave_addr << 1) + DVFS_READ_MODE); + mmio_write_8(IIC_DVFS_REG_ICDR, address); + /* Next status */ + *status = DVFS_CHANGE_SEND_TO_RECIEVE; + } + } + + return result; +} + +static int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + dvfs_change_send_to_recieve( + DVFS_STATUS_T *status, uint32_t *err_count) +{ + uint8_t mode; + int32_t result; + + result = dvfs_check_error(status, err_count, DVFS_WRITE_MODE); + if (result != DVFS_ERROR) { + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT); + if (mode == ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT)) { + /* Set the change transmission to reception */ + mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_CHANGE); + /* Clear ICSR.WAIT */ + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_WAIT)); + mmio_write_8(IIC_DVFS_REG_ICSR, mode); + /* Next status */ + *status = DVFS_STOP_CONDITION_READ; + } + } + + return result; +} + +static int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + dvfs_stop_condition_read( + DVFS_STATUS_T *status, uint32_t *err_count) +{ + uint8_t mode; + int32_t result; + + result = dvfs_check_error(status, err_count, DVFS_READ_MODE); + if (result != DVFS_ERROR) { + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT); + if (mode == ((uint8_t)IIC_DVFS_BIT_ICSR_WAIT)) { + /* Write stop condition */ + mmio_write_8(IIC_DVFS_REG_ICCR, IIC_DVFS_SET_ICCR_STOP_READ); + /* Clear ICSR.WAIT */ + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)(~IIC_DVFS_BIT_ICSR_WAIT)); + mmio_write_8(IIC_DVFS_REG_ICSR, mode); + /* Set ICIC.DTEE */ + mode = mmio_read_8(IIC_DVFS_REG_ICIC) | IIC_DVFS_BIT_ICIC_DTEE; + mmio_write_8(IIC_DVFS_REG_ICIC, mode); + /* Next status */ + *status = DVFS_READ_REG_DATA; + } + } + + return result; +} + +static int32_t +#if IMAGE_BL31 + __attribute__ ((section (".system_ram"))) +#endif + dvfs_read_reg_data( + DVFS_STATUS_T *status, uint8_t *reg_data) +{ + uint8_t mode; + + mode = mmio_read_8(IIC_DVFS_REG_ICSR) + & ((uint8_t)IIC_DVFS_BIT_ICSR_DTE); + if (mode == ((uint8_t)IIC_DVFS_BIT_ICSR_DTE)) { + /* Clear ICIC.DTEE */ + mode = mmio_read_8(IIC_DVFS_REG_ICIC) + & ((uint8_t)(~IIC_DVFS_BIT_ICIC_DTEE)); + mmio_write_8(IIC_DVFS_REG_ICIC, mode); + /* Recieve data */ + *reg_data = mmio_read_8(IIC_DVFS_REG_ICDR); + /* Next status */ + *status = DVFS_PROCESS_COMPLETE; + } + + return DVFS_PROCESS; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.h new file mode 100644 index 0000000..6e72734 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef IIC_DVFS_H__ +#define IIC_DVFS_H__ + +#define SLAVE_ADDR_PMIC (0x30U) + +#define REG_ADDR_DVFS_SetVID (0x54U) +#define REG_DATA_DVFS_SetVID_0V (0x00U) + +#define REG_ADDR_BKUP_Mode_Cnt (0x20U) +#define REG_DATA_P_ALL_OFF (0x80U) + +int32_t rcar_iic_dvfs_send(uint8_t slave_addr, uint8_t reg_addr, uint8_t reg_data); +int32_t rcar_iic_dvfs_recieve(uint8_t slave_addr, uint8_t reg_addr, uint8_t *reg_data); + +#endif /* IIC_DVFS_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/io/io_emmcdrv.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/io/io_emmcdrv.c new file mode 100644 index 0000000..2429b5a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/io/io_emmcdrv.c @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "io_common.h" +#include "io_private.h" +#include "io_emmcdrv.h" +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_def.h" + +/* As we need to be able to keep state for seek, only one file can be open + * at a time. Make this a structure and point to the entity->info. When we + * can malloc memory we can change this to support more open files. + */ +typedef struct +{ + /* Use the 'in_use' flag as any value for base and file_pos could be + * valid. + */ + uint32_t in_use; + uintptr_t base; + ssize_t file_pos; + EMMC_PARTITION_ID partition; +} file_state_t; + +static file_state_t current_file = {0U}; +/* Initialize to defualt partition */ +static EMMC_PARTITION_ID emmcdrv_bootpartition = PARTITION_ID_USER; + +/* emmcdrv device functions */ +static io_type_t device_type_emmcdrv(void); +static int32_t emmcdrv_dev_open(const uintptr_t dev_spec, + io_dev_info_t **dev_info); +static int32_t emmcdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); +static int32_t emmcdrv_block_seek(io_entity_t *entity, int32_t mode, + ssize_t offset); +static int32_t emmcdrv_block_read(io_entity_t *entity, uintptr_t buffer, + size_t length, size_t *length_read); +static int32_t emmcdrv_block_close(io_entity_t *entity); +static int32_t emmcdrv_dev_close(io_dev_info_t *dev_info); + +static const io_dev_connector_t emmcdrv_dev_connector = { + &emmcdrv_dev_open +}; + +static const io_dev_funcs_t emmcdrv_dev_funcs = { + &device_type_emmcdrv, + &emmcdrv_block_open, + &emmcdrv_block_seek, + NULL, + &emmcdrv_block_read, + NULL, + &emmcdrv_block_close, + NULL, + &emmcdrv_dev_close +}; + +/* No state associated with this device so structure can be const */ +static const io_dev_info_t emmcdrv_dev_info = { + &emmcdrv_dev_funcs, + (uintptr_t)0 +}; + +/* Identify the device type as emmcdrv */ +static io_type_t device_type_emmcdrv(void) +{ + return IO_TYPE_MEMMAP; +} + +/* Open a connection to the emmcdrv device */ +static int32_t emmcdrv_dev_open( + const uintptr_t dev_spec __attribute__((unused)), + io_dev_info_t **dev_info) +{ + assert(dev_info != NULL); + *dev_info = (io_dev_info_t *)&emmcdrv_dev_info; + + return IO_SUCCESS; +} + +/* Close a connection to the emmcdrv device */ +static int32_t emmcdrv_dev_close(io_dev_info_t *dev_info) +{ + /* NOP */ + /* TODO: Consider tracking open files and cleaning them up here */ + return IO_SUCCESS; +} + +/* Open a file on the emmcdrv device */ +/* TODO: Can we do any sensible limit checks on requested memory */ +static int32_t emmcdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity) +{ + int32_t result = IO_SUCCESS; + const io_drv_spec_t *block_spec = (io_drv_spec_t *)spec; + + /* Since we need to track open state for seek() we only allow one open + * spec at a time. When we have dynamic memory we can malloc and set + * entity->info. + */ + if (current_file.in_use == 0U) { + assert(block_spec != NULL); + assert(entity != NULL); + + current_file.in_use = 1U; + /* File cursor offset for seek and incremental reads etc. */ + current_file.file_pos = 0; + + if (emmcdrv_bootpartition == PARTITION_ID_USER) { + emmcdrv_bootpartition = mmc_drv_obj.boot_partition_en; + /* Partition check */ + if ((PARTITION_ID_BOOT_1==emmcdrv_bootpartition) || + (PARTITION_ID_BOOT_2==emmcdrv_bootpartition)) { + current_file.partition = emmcdrv_bootpartition; + NOTICE("BL2: eMMC boot from partition %d\n", + emmcdrv_bootpartition); + } else { + /* eMMC boot partition error */ + result = IO_FAIL; + } + } else { + if ((PARTITION_ID_USER + == (EMMC_PARTITION_ID) + (block_spec->partition)) + || (PARTITION_ID_BOOT_1 + == (EMMC_PARTITION_ID) + (block_spec->partition)) + || (PARTITION_ID_BOOT_2 + == (EMMC_PARTITION_ID) + (block_spec->partition))) { + current_file.partition = + (EMMC_PARTITION_ID) + (block_spec->partition); + } else { + /* Set boot partition */ + current_file.partition = emmcdrv_bootpartition; + } + } + if (IO_SUCCESS == result) { + if (emmc_select_partition(current_file.partition) + != EMMC_SUCCESS) { + result = IO_FAIL; + } + entity->info = (uintptr_t)¤t_file; + } + } else { + /* A emmcdrv device is already active. Close first. */ + result = IO_RESOURCES_EXHAUSTED; + } + + return result; +} + +/* Seek to a particular file offset on the emmcdrv device */ +static int32_t emmcdrv_block_seek(io_entity_t *entity, int32_t mode, + ssize_t offset) +{ + int32_t result; + + /* We only support IO_SEEK_SET for the moment. */ + if ((io_seek_mode_t)mode == IO_SEEK_SET) { + assert(entity != NULL); + assert(entity->info != (uintptr_t)NULL); + + /* TODO: can we do some basic limit checks on seek? */ + ((file_state_t *)entity->info)->file_pos = offset; + result = IO_SUCCESS; + } else { + result = IO_FAIL; + } + + return result; +} + +/* Read data from a file on the emmcdrv device */ +static int32_t emmcdrv_block_read(io_entity_t *entity, uintptr_t buffer, + size_t length, size_t *length_read) +{ + file_state_t *fp; + uint32_t sector_add; + uint32_t sector_num; + uint32_t emmc_dma = 0U; + int32_t result = IO_SUCCESS; + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_read != NULL); + assert(entity->info != (uintptr_t)NULL); + + fp = (file_state_t *)entity->info; + + NOTICE("BL2: Load dst=0x%lx src=(p:%d)0x%lx(%d) len=0x%lx(%d)\n", + buffer, + (uint32_t)(current_file.partition), + (current_file.file_pos), + (uint32_t)(current_file.file_pos) >> EMMC_SECTOR_SIZE_SHIFT, + length, + (uint32_t)((length + (EMMC_SECTOR_SIZE - 1U)) + >> EMMC_SECTOR_SIZE_SHIFT)); + + sector_add = (uint32_t)(current_file.file_pos) + >> EMMC_SECTOR_SIZE_SHIFT; + sector_num = (uint32_t)((length + (EMMC_SECTOR_SIZE - 1U)) + >> EMMC_SECTOR_SIZE_SHIFT); + if ((uint64_t)(buffer + length) <= UINT32_MAX ) { + emmc_dma = LOADIMAGE_FLAGS_DMA_ENABLE; + } + + if (emmc_read_sector((uint32_t *)buffer, sector_add, sector_num, + emmc_dma) != EMMC_SUCCESS) { + result = IO_FAIL; + } + + *length_read = length; + /* advance the file 'cursor' for incremental reads */ + fp->file_pos += (ssize_t)length; + + return result; +} + +/* Close a file on the emmcdrv device */ +static int32_t emmcdrv_block_close(io_entity_t *entity) +{ + assert(entity != NULL); + + entity->info = 0U; + + /* This would be a mem free() if we had malloc.*/ + (void)memset((void *)¤t_file, 0, sizeof(current_file)); + + return IO_SUCCESS; +} + +/* Exported functions */ + +/* Register the emmcdrv driver with the IO abstraction */ +int32_t register_io_dev_emmcdrv(const io_dev_connector_t **dev_con) +{ + int32_t result; + assert(dev_con != NULL); + + result = io_register_device(&emmcdrv_dev_info); + if (result == IO_SUCCESS) { + *dev_con = &emmcdrv_dev_connector; + } + + return result; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/io/io_memdrv.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/io/io_memdrv.c new file mode 100644 index 0000000..c42e9a0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/io/io_memdrv.c @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "io_common.h" +#include "io_private.h" +#include "io_memdrv.h" +#include "dma_driver.h" + +/* As we need to be able to keep state for seek, only one file can be open + * at a time. Make this a structure and point to the entity->info. When we + * can malloc memory we can change this to support more open files. + */ +typedef struct { + /* Use the 'in_use' flag as any value for base and file_pos could be + * valid. + */ + uint32_t in_use; + uintptr_t base; + ssize_t file_pos; +} file_state_t; + +static file_state_t current_file = {0}; + +/* memdrv device functions */ +static io_type_t device_type_memdrv(void); +static int32_t memdrv_dev_open(const uintptr_t dev_spec, + io_dev_info_t **dev_info); +static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); +static int32_t memdrv_block_seek(io_entity_t *entity, int32_t mode, + ssize_t offset); +static int32_t memdrv_block_read(io_entity_t *entity, uintptr_t buffer, + size_t length, size_t *length_read); +static int32_t memdrv_block_close(io_entity_t *entity); +static int32_t memdrv_dev_close(io_dev_info_t *dev_info); + + +static const io_dev_connector_t memdrv_dev_connector = { + .dev_open = &memdrv_dev_open +}; + + +static const io_dev_funcs_t memdrv_dev_funcs = { + .type = &device_type_memdrv, + .open = &memdrv_block_open, + .seek = &memdrv_block_seek, + .size = NULL, + .read = &memdrv_block_read, + .write = NULL, + .close = &memdrv_block_close, + .dev_init = NULL, + .dev_close = &memdrv_dev_close, +}; + + +/* No state associated with this device so structure can be const */ +static const io_dev_info_t memdrv_dev_info = { + .funcs = &memdrv_dev_funcs, + .info = (uintptr_t)0 +}; + +/* Identify the device type as memdrv */ +static io_type_t device_type_memdrv(void) +{ + return IO_TYPE_MEMMAP; +} + + +/* Open a connection to the memdrv device */ +static int32_t memdrv_dev_open( + const uintptr_t dev_spec __attribute__((unused)), + io_dev_info_t **dev_info) +{ + assert(dev_info != NULL); + *dev_info = (io_dev_info_t *)&memdrv_dev_info; /* cast away const */ + + return IO_SUCCESS; +} + + + +/* Close a connection to the memdrv device */ +static int32_t memdrv_dev_close(io_dev_info_t *dev_info) +{ + /* NOP */ + /* TODO: Consider tracking open files and cleaning them up here */ + return IO_SUCCESS; +} + + +/* Open a file on the memdrv device */ +/* TODO: Can we do any sensible limit checks on requested memory */ +static int32_t memdrv_block_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity) +{ + int32_t result; + const io_drv_spec_t *block_spec = (io_drv_spec_t *)spec; + + /* Since we need to track open state for seek() we only allow one open + * spec at a time. When we have dynamic memory we can malloc and set + * entity->info. + */ + if (current_file.in_use == 0U) { + assert(block_spec != NULL); + assert(entity != NULL); + + current_file.in_use = 1U; + current_file.base = block_spec->offset; + /* File cursor offset for seek and incremental reads etc. */ + current_file.file_pos = 0; + entity->info = (uintptr_t)¤t_file; + result = IO_SUCCESS; + } else { + /* A memdrv device is already active. Close first. */ + result = IO_RESOURCES_EXHAUSTED; + } + + return result; +} + + +/* Seek to a particular file offset on the memdrv device */ +static int32_t memdrv_block_seek(io_entity_t *entity, int32_t mode, + ssize_t offset) +{ + int32_t result; + + /* We only support IO_SEEK_SET for the moment. */ + if ((io_seek_mode_t)mode == IO_SEEK_SET) { + assert(entity != NULL); + assert(entity->info != (uintptr_t)NULL); + + /* TODO: can we do some basic limit checks on seek? */ + ((file_state_t *)entity->info)->file_pos = offset; + result = IO_SUCCESS; + } else { + result = IO_FAIL; + } + + return result; +} + + +/* Read data from a file on the memdrv device */ +static int32_t memdrv_block_read(io_entity_t *entity, uintptr_t buffer, + size_t length, size_t *length_read) +{ + file_state_t *fp; + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_read != NULL); + + fp = (file_state_t *)entity->info; + + NOTICE("BL2: dst=0x%lx src=0x%lx len=%ld(0x%lx)\n", + buffer, + fp->base + fp->file_pos, + length, length); + +#if 1 /* DMA driver */ + execDMA(buffer, (uint32_t)(fp->base + fp->file_pos), + (uint32_t)length); +#else + (void)memcpy((void *)buffer, (void *)(fp->base + fp->file_pos), + length); +#endif + + *length_read = length; + /* advance the file 'cursor' for incremental reads */ + fp->file_pos += (ssize_t)length; + + return IO_SUCCESS; +} + + +/* Close a file on the memdrv device */ +static int32_t memdrv_block_close(io_entity_t *entity) +{ + assert(entity != NULL); + + entity->info = 0U; + + /* This would be a mem free() if we had malloc.*/ + (void)memset((void *)¤t_file, 0, sizeof(current_file)); + + return IO_SUCCESS; +} + + +/* Exported functions */ + +/* Register the memdrv driver with the IO abstraction */ +int32_t register_io_dev_memdrv(const io_dev_connector_t **dev_con) +{ + int32_t result; + assert(dev_con != NULL); + + result = io_register_device(&memdrv_dev_info); + if (result == IO_SUCCESS) { + *dev_con = &memdrv_dev_connector; + } + + return result; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/io/io_rcar.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/io/io_rcar.c new file mode 100644 index 0000000..dd0e2e9 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/io/io_rcar.c @@ -0,0 +1,904 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "io_rcar.h" +#include "io_common.h" +#include "io_private.h" + +typedef struct { + const int32_t name; + const uint32_t offset; + const uint32_t attr; +} plat_rcar_name_offset_t; + +typedef struct { + /* Put file_pos above the struct to allow {0} on static init. + * It is a workaround for a known bug in GCC + * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=53119 + */ + uint32_t file_pos; + uint32_t is_noload; + uintptr_t offset_address; + uint32_t size; + uintptr_t dest_address; + uintptr_t partition; /* for eMMC */ + /* RCAR_EMMC_PARTITION_BOOT_0 */ + /* RCAR_EMMC_PARTITION_BOOT_1 */ + /* RCAR_EMMC_PARTITION_USER */ +} file_state_t; + +#define RCAR_GET_FLASH_ADR(a,b) ((uint32_t)((0x40000U*(a)) + (b))) +#define RCAR_ATTR_SET_CALCADDR(a) ((a) & 0xF) /* lower 4bit use */ +#define RCAR_ATTR_SET_ISNOLOAD(a) (((a) & 0x1) << 16U) /* 16bit use */ +#define RCAR_ATTR_SET_CERTOFF(a) (((a) & 0xF) << 8U) /* 11-8bit use */ +#define RCAR_ATTR_SET_ALL(a,b,c) ((uint32_t)(RCAR_ATTR_SET_CALCADDR(a) |\ + RCAR_ATTR_SET_ISNOLOAD(b) | RCAR_ATTR_SET_CERTOFF(c))) + +#define RCAR_ATTR_GET_CALCADDR(a) ((a) & 0xFU) /* lower 4bit use */ +#define RCAR_ATTR_GET_ISNOLOAD(a) (((a) >> 16) & 0x1U) /* 16bit use */ +#define RCAR_ATTR_GET_CERTOFF(a) (((a) >> 8) & 0xFU) /* 11-8bit use */ + +#define RCAR_MAX_BL3X_IMAGE (8U) +#define RCAR_SECTOR6_CERT_OFFSET (0x400U) +#define RCAR_SDRAM_CERT_ADDRESS (0x46200000U) +#define RCAR_CERT_SIZE (0x800U) /* cert field size*/ +#define RCAR_CERT_INFO_SIZE_OFFSET (0x264U) /* byte address set : must 4byte alignment */ +#define RCAR_CERT_INFO_DST_OFFSET (0x154U) /* byte address set : must 4byte alignment */ +#define RCAR_CERT_INFO_SIZE_OFFSET1 (0x364U) /* for Map Type-1 */ +#define RCAR_CERT_INFO_DST_OFFSET1 (0x1D4U) /* for Map Type-1 */ +#define RCAR_CERT_INFO_SIZE_OFFSET2 (0x464U) /* for Map Type-2 */ +#define RCAR_CERT_INFO_DST_OFFSET2 (0x254U) /* for Map Type-2 */ +#define RCAR_CERT_LOAD (1U) + +#define RCAR_FLASH_CERT_HEADER RCAR_GET_FLASH_ADR(6U, 0U) +#define RCAR_EMMC_CERT_HEADER (0x00030000U) + +static const plat_rcar_name_offset_t name_offset[] = { /* calc addr, no load, cert offset */ + {BL31_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(0,0,0)}, + /* BL3-2 is optional in the platform */ + {BL32_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(1,0,1)}, + {BL33_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(2,0,2)}, + {BL332_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(3,0,3)}, + {BL333_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(4,0,4)}, + {BL334_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(5,0,5)}, + {BL335_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(6,0,6)}, + {BL336_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(7,0,7)}, + {BL337_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(8,0,8)}, + {BL338_IMAGE_ID, 0U, RCAR_ATTR_SET_ALL(9,0,9)}, +}; +#if TRUSTED_BOARD_BOOT +static const plat_rcar_name_offset_t cert_offset[] = { + /* Certificates */ + {TRUSTED_KEY_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,0)}, + {SOC_FW_KEY_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,0)}, + {TRUSTED_OS_FW_KEY_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,0)}, + {NON_TRUSTED_FW_KEY_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,0)}, + {SOC_FW_CONTENT_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,0)}, + {TRUSTED_OS_FW_CONTENT_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,1)}, + {NON_TRUSTED_FW_CONTENT_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,2)}, + {BL332_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,3)}, + {BL333_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,4)}, + {BL334_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,5)}, + {BL335_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,6)}, + {BL336_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,7)}, + {BL337_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,8)}, + {BL338_CERT_ID, 0U, RCAR_ATTR_SET_ALL(0,1,9)}, +}; +#endif /* TRUSTED_BOARD_BOOT */ + + +static file_state_t current_file = {0}; +static uintptr_t backend_dev_handle; +static uintptr_t backend_image_spec; +static uint64_t rcar_image_header_tmp[64] = {0U}; +static uint64_t rcar_image_header[RCAR_MAX_BL3X_IMAGE + 2U] = {0U}; +static uint64_t rcar_image_header_prttn[RCAR_MAX_BL3X_IMAGE + 2U] = {0U}; +static uint64_t rcar_image_number = {0U}; +static uint32_t rcar_cert_load = {0U}; + + +/* prototype */ +static io_type_t device_type_rcar(void); +static int32_t rcar_dev_open(const uintptr_t dev_spec, io_dev_info_t **dev_info); +static int32_t rcar_file_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity); +static int32_t rcar_file_len(io_entity_t *entity, size_t *length); +static int32_t rcar_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read); +static int32_t rcar_file_close(io_entity_t *entity); +static int32_t rcar_dev_close(io_dev_info_t *dev_info); +static int32_t file_to_offset(const int32_t file, uintptr_t *offset, + uint32_t *cert_addr, uint32_t *is_noload, uintptr_t *partition); +static int32_t load_bl33x(void); +static int32_t check_load_area(uintptr_t src, uintptr_t dst, uintptr_t len); +static int32_t skip_check_load_src = 0; + +/* Identify the device type as a virtual driver */ +static io_type_t device_type_rcar(void) +{ + return IO_TYPE_FIRMWARE_IMAGE_PACKAGE; +} + + +static const io_dev_connector_t rcar_dev_connector = { + .dev_open = &rcar_dev_open +}; + + +static const io_dev_funcs_t rcar_dev_funcs = { + .type = &device_type_rcar, + .open = &rcar_file_open, + .seek = NULL, + .size = &rcar_file_len, + .read = &rcar_file_read, + .write = NULL, + .close = &rcar_file_close, + .dev_init = &rcar_dev_init, + .dev_close = &rcar_dev_close, +}; + + +/* No state associated with this device so structure can be const */ +static const io_dev_info_t rcar_dev_info = { + .funcs = &rcar_dev_funcs, + .info = (uintptr_t)0 +}; + + +/* Open a connection to the FIP device */ +static int32_t rcar_dev_open(const uintptr_t dev_spec __attribute__((unused)), + io_dev_info_t **dev_info) +{ + assert(dev_info != NULL); + *dev_info = (io_dev_info_t *)&rcar_dev_info; /* cast away const */ + + return IO_SUCCESS; +} + +int32_t file_to_cert(const int32_t filename, uint32_t *cert_addr) +{ + int32_t i; + int32_t status = -EINVAL; + + for (i = 0; i < (int32_t)ARRAY_SIZE(cert_offset); i++) { + if (filename == cert_offset[i].name) { + *cert_addr = RCAR_CERT_SIZE; + *cert_addr *= (uint32_t)RCAR_ATTR_GET_CERTOFF(cert_offset[i].attr); + *cert_addr += RCAR_SDRAM_CERT_ADDRESS; + status = 0; + break; + } + } + return status; +} + +static int32_t file_to_offset(const int32_t file, uintptr_t *offset, + uint32_t *cert_addr, uint32_t *is_noload, uintptr_t *partition) +{ + int32_t i; + int32_t status = -EINVAL; + uint32_t is_calc_addr; + + assert(offset != NULL); + assert(cert_addr != NULL); + assert(is_noload != NULL); + assert(partition != NULL); + + for (i = 0; i < (int32_t)ARRAY_SIZE(name_offset); i++) { + if (file == name_offset[i].name) { + is_calc_addr = RCAR_ATTR_GET_CALCADDR(name_offset[i].attr); + if ((rcar_image_number + 2U) >= is_calc_addr) + { + *offset = rcar_image_header[is_calc_addr]; + *cert_addr = RCAR_CERT_SIZE; + *cert_addr *= RCAR_ATTR_GET_CERTOFF(name_offset[i].attr); + *cert_addr += RCAR_SDRAM_CERT_ADDRESS; + *is_noload = RCAR_ATTR_GET_ISNOLOAD(name_offset[i].attr); + *partition = rcar_image_header_prttn[is_calc_addr]; + status = IO_SUCCESS; + break; + } + } + } + + if (IO_SUCCESS != status) { + for (i = 0; i < (int32_t)ARRAY_SIZE(cert_offset); i++) { + if (file == cert_offset[i].name) { + *offset = 0U; + *cert_addr = 0U; + *is_noload = RCAR_ATTR_GET_ISNOLOAD(cert_offset[i].attr); + *partition = 0U; + status = IO_SUCCESS; + break; + } + } + } + return status; +} + +#define RCAR_BOOT_KEY_CERT_NEW (0xE6300F00U) +#define RCAR_CERT_MAGIC_NUM (0xE291F358U) +void get_info_from_cert(uint64_t cert_addr, uint32_t *size, uintptr_t *dest_addr) +{ + uint32_t val; + uint32_t magicNumber; + uint32_t certInfo1; + uint32_t certInfo2; + uintptr_t pSize; + uintptr_t pDestH; + uintptr_t pDestL; + + assert(size != NULL); + assert(dest_addr != NULL); + + cert_addr &= 0xFFFFFFFFU; /* need? */ + + magicNumber = mmio_read_32((uintptr_t)RCAR_BOOT_KEY_CERT_NEW); + val = mmio_read_32((uintptr_t)RCAR_BOOT_KEY_CERT_NEW+0xCU); + certInfo1 = (val >> 18) & 0x3U; + val = mmio_read_32((uintptr_t)cert_addr+0xCU); + certInfo2 = (val >> 21) & 0x3U; + if (RCAR_CERT_MAGIC_NUM == magicNumber) { + if (0x1U != certInfo1) { + ERROR("BL2: Cert is invalid.\n"); + *size = 0x0U; + *dest_addr = 0x0U; + } else { + if (0x2U == certInfo2) { + pSize = cert_addr + RCAR_CERT_INFO_SIZE_OFFSET2; + *size = mmio_read_32(pSize) * 4U; + pDestL = cert_addr + RCAR_CERT_INFO_DST_OFFSET2; + pDestH = pDestL + 4U; + *dest_addr = + ((uintptr_t)mmio_read_32(pDestH) << 32) + + ((uintptr_t)mmio_read_32(pDestL)); + } else if (0x1U == certInfo2) { + pSize = cert_addr + RCAR_CERT_INFO_SIZE_OFFSET1; + *size = mmio_read_32(pSize) * 4U; + pDestL = cert_addr + RCAR_CERT_INFO_DST_OFFSET1; + pDestH = pDestL + 4U; + *dest_addr = + ((uintptr_t)mmio_read_32(pDestH) << 32) + + ((uintptr_t)mmio_read_32(pDestL)); + } else if (0x0U == certInfo2) { + pSize = cert_addr + RCAR_CERT_INFO_SIZE_OFFSET; + *size = mmio_read_32(pSize) * 4U; + pDestL = cert_addr + RCAR_CERT_INFO_DST_OFFSET; + pDestH = pDestL + 4U; + *dest_addr = + ((uintptr_t)mmio_read_32(pDestH) << 32) + + ((uintptr_t)mmio_read_32(pDestL)); + } else /* if (0x3U == certInfo2) */ { + ERROR("BL2: Cert is invalid.\n"); + *size = 0x0U; + *dest_addr = 0x0U; + } + } + } else { + pSize = cert_addr + RCAR_CERT_INFO_SIZE_OFFSET; + *size = mmio_read_32(pSize) * 4U; + pDestL = cert_addr + RCAR_CERT_INFO_DST_OFFSET; + pDestH = pDestL + 4U; + *dest_addr = + ((uintptr_t)mmio_read_32(pDestH) << 32) + + ((uintptr_t)mmio_read_32(pDestL)); + } +} + +static int32_t load_bl33x(void) +{ + int32_t result = IO_SUCCESS; + uint32_t loop = 1U; /* start is BL332 */ + uintptr_t file_offset; + uint32_t noload; + uint32_t cert_addr; + uint32_t l_image_size; + uintptr_t dest_addr; + uintptr_t emmc_prttn; + size_t bytes_read; + uintptr_t backend_handle; + const int32_t load_names[] = { + BL33_IMAGE_ID, + BL332_IMAGE_ID, + BL333_IMAGE_ID, + BL334_IMAGE_ID, + BL335_IMAGE_ID, + BL336_IMAGE_ID, + BL337_IMAGE_ID, + BL338_IMAGE_ID + }; + static uint32_t load_bl33x_firsttime_flag = 0U; + + for (; (loop < rcar_image_number) && + (0U == load_bl33x_firsttime_flag); loop++) { + + if (IO_SUCCESS != result){ + break; + } + + result = file_to_offset(load_names[loop], &file_offset, + &cert_addr, &noload, &emmc_prttn); + if (IO_SUCCESS != result) { + WARN("load_bl33x: failed to get offset\n"); + result = IO_FAIL; + } else { + + get_info_from_cert((uint64_t) cert_addr, &l_image_size, + &dest_addr); + + /* set eMMC partition */ + ((io_drv_spec_t *)backend_image_spec)->partition = + (uint32_t)emmc_prttn; /* needs 32-bits only */ + + /* Open the backend, attempt to access the blob image */ + result = io_open(backend_dev_handle, backend_image_spec, + &backend_handle); + if (result != IO_SUCCESS) { + WARN("Failed to open FIP (%i)\n", result); + result = IO_FAIL; + } else { + result = io_seek(backend_handle, IO_SEEK_SET, + (ssize_t) file_offset); + if (IO_SUCCESS != result) { + WARN("load_bl33x: failed to seek\n"); + result = IO_FAIL; + } + } + + if (IO_SUCCESS == result) { + + result = check_load_area((uintptr_t)file_offset, + dest_addr, + (uintptr_t)l_image_size); + if (result != IO_SUCCESS) { + WARN("load_bl33x: check load area\n"); + result = IO_FAIL; + } + } + + if (IO_SUCCESS == result) { + + result = io_read(backend_handle, + dest_addr, + (size_t)l_image_size, + (size_t *)&bytes_read); + if (IO_SUCCESS != result) { + WARN("load_bl33x: failed to read\n"); + result = IO_FAIL; + } +#if TRUSTED_BOARD_BOOT + else { + /* Authenticate it */ + result = (int32_t)auth_mod_verify_img( + (unsigned int)load_names[loop], + (void *)dest_addr, + (unsigned int)l_image_size); + if (0 != result) { + (void)memset( + (void *)dest_addr, + 0x00, + (size_t)l_image_size); + result = IO_FAIL; + } + } +#endif /* TRUSTED_BOARD_BOOT */ + } + /* Close the backend. */ + (void) io_close(backend_handle); + } + } + + load_bl33x_firsttime_flag = 1U; + + return result; +} + +static int32_t check_load_area(uintptr_t src, uintptr_t dst, uintptr_t len) +{ + int32_t result = IO_SUCCESS; + uint32_t src_end; + uint64_t dst_end; + + /* check source range */ + if (skip_check_load_src == 0) { + /* check whether source is overflow */ + if ((FLASH0_BASE > (UINT32_MAX - src)) + || ((FLASH0_BASE + src) > (UINT32_MAX - len))) { + ERROR("BL2: overflow is occurred at source\n"); + ERROR("BL2: source address = 0x%lx image size = 0x%lx\n", + (FLASH0_BASE + src), len); + result = IO_FAIL; + } + src_end = (uint32_t)((FLASH0_BASE + src) + len); + if ((src_end < FLASH0_BASE) + || (src_end < (FLASH0_BASE + src))) { + ERROR("BL2: overflow is occurred at source\n"); + ERROR("BL2: source address = 0x%lx image size = 0x%lx\n", + (FLASH0_BASE + src), len); + result = IO_FAIL; + } + /* check whether offset + image size is over flash size */ + if (FLASH_MEMORY_SIZE <= (src + len)) { + ERROR("BL2: check_load_area (source address)\n"); + result = IO_FAIL; + } + } + + /* check destination range */ + /* check whether destination is overflow */ + if (dst > (UINT64_MAX - len)) { + ERROR("BL2: overflow is occurred at destination\n"); + ERROR("BL2: destination address = 0x%lx image size = 0x%lx\n", + dst, len); + result = IO_FAIL; + } + dst_end = (uint64_t)(dst + len); + if (dst_end < dst) { + ERROR("BL2: overflow is occurred at destination\n"); + ERROR("BL2: destination address = 0x%lx image size = 0x%lx\n", + dst, len); + result = IO_FAIL; + } + if ((dst + len) < 0x100000000U) { + /* check legacy range */ + /* destination address is lower than the SDRAM top address */ + if (dst < DRAM1_BASE) { + ERROR("BL2: check_load_area (destination address)\n"); + result = IO_FAIL; + } + /* destination address is on the protected area */ + if ((DRAM_PROTECTED_BASE <= dst) && + (dst < (DRAM_PROTECTED_BASE + DRAM_PROTECTED_SIZE))) { + ERROR("BL2: check_load_area (destination address)\n"); + result = IO_FAIL; + } + /* destination address is higher than the SDRAM last address */ + if ((DRAM1_BASE + DRAM1_SIZE) <= dst) { + ERROR("BL2: check_load_area (destination address)\n"); + result = IO_FAIL; + } + if (dst < DRAM_PROTECTED_BASE) { + if (DRAM_PROTECTED_BASE <= (dst + len)) { + ERROR("BL2: check_load_area (destination address)\n"); + result = IO_FAIL; + } + } + if ((DRAM1_BASE + DRAM1_SIZE) <= (dst + len)) { + ERROR("BL2: check_load_area (destination address)\n"); + result = IO_FAIL; + } + /* check whether not overwrite IPL */ + if (((dst >= BL2_BASE) && (dst < BL2_LIMIT)) + || ((dst_end > BL2_BASE) && (dst_end < BL2_LIMIT)) + || ((dst < BL2_BASE) && (BL2_LIMIT <= dst_end))) { + ERROR("BL2: it is prohibited overwrite CA53 Loader area\n"); + ERROR("BL2: destination address = 0x%lx image size = 0x%lx\n", + dst, len); + result = IO_FAIL; + } + } else { + /* check 40 bit range */ + /* destination address is lower than the SDRAM top address */ + if (dst < DRAM_40BIT_BASE) { + ERROR("BL2: check_load_area (destination address)\n"); + result = IO_FAIL; + } + /* destination address is on the protected area */ + if ((DRAM_40BIT_PROTECTED_BASE <= dst) && + (dst < (DRAM_40BIT_PROTECTED_BASE + DRAM_PROTECTED_SIZE))) { + ERROR("BL2: check_load_area (destination address)\n"); + result = IO_FAIL; + } + /* destination address is higher than the SDRAM last address */ + if ((DRAM_40BIT_BASE + DRAM_40BIT_SIZE) <= dst) { + ERROR("BL2: check_load_area (destination address)\n"); + result = IO_FAIL; + } + if (dst < DRAM_40BIT_PROTECTED_BASE) { + if (DRAM_40BIT_PROTECTED_BASE <= (dst + len)) { + ERROR("BL2: check_load_area (destination address)\n"); + result = IO_FAIL; + } + } + if ((DRAM_40BIT_BASE + DRAM_40BIT_SIZE) <= (dst + len)) { + ERROR("BL2: check_load_area (destination address)\n"); + result = IO_FAIL; + } + /* check whether not overwrite IPL */ + if (((dst >= BL2_40BIT_BASE) && (dst < BL2_40BIT_LIMIT)) + || ((dst_end > BL2_40BIT_BASE) && (dst_end < BL2_40BIT_LIMIT)) + || ((dst < BL2_40BIT_BASE) && (BL2_40BIT_LIMIT <= dst_end))) { + ERROR("BL2: it is prohibited overwrite CA53 Loader area\n"); + ERROR("BL2: destination address = 0x%lx image size = 0x%lx\n", + dst, len); + result = IO_FAIL; + } + } + return result; +} + +/* Do some basic package checks. */ +int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params) +{ + int32_t result; + uint32_t image_name = (uint32_t)init_params; + uintptr_t backend_handle; + size_t bytes_read; + ssize_t offset; + uint32_t loop; + + /* Obtain a reference to the image by querying the platform layer */ + /* get rcar flash memory address... (certain BL2, BL31, BL32, BL33... max 64MB:RPC LBSC address) */ + result = plat_get_drv_source(image_name, &backend_dev_handle, + &backend_image_spec); + if (result != IO_SUCCESS) { + WARN("Failed to obtain reference to image '%d' (%i)\n", + image_name, result); + result = IO_FAIL; + } else { + + if (RCAR_CERT_LOAD == rcar_cert_load) { + /* not load certificate file after 1st initialize */ + result = IO_SUCCESS; + } else { + + /* Attempt to access the RCAR image */ + /* open memory driver (certain SYS-DMAC2 initialize) */ + result = io_open(backend_dev_handle, backend_image_spec, + &backend_handle); + if (result != IO_SUCCESS) { + WARN("Failed to access image '%d' (%i)\n", + image_name, result); + result = IO_FAIL; + } + + /* get start address list */ + /* [0] address num */ + /* [1] BL33-1 image address */ + /* [2] BL33-2 image address */ + /* [3] BL33-3 image address */ + /* [4] BL33-4 image address */ + /* [5] BL33-5 image address */ + /* [6] BL33-6 image address */ + /* [7] BL33-7 image address */ + /* [8] BL33-8 image address */ + if (IO_SUCCESS == result) { + if ( image_name == EMMC_DEV_ID) { + offset = + (ssize_t)RCAR_EMMC_CERT_HEADER; + skip_check_load_src = 1; + } else { + offset = + (ssize_t)RCAR_FLASH_CERT_HEADER; + skip_check_load_src = 0; + } + result = io_seek(backend_handle, + IO_SEEK_SET, offset); + if (result != IO_SUCCESS) { + WARN("Firmware Image Package header "\ + "failed to seek\n"); + result = IO_FAIL; + (void) io_close(backend_handle); + } + } + if (IO_SUCCESS == result) { + result = io_read(backend_handle, + (uintptr_t) &rcar_image_header_tmp, + sizeof(rcar_image_header_tmp), + &bytes_read); + if (result == IO_SUCCESS) { + /* 32 bits array to 64 bits array */ + rcar_image_number = + rcar_image_header_tmp[0U]; + for (loop = 0U; loop < + (rcar_image_number + 2U); + loop++) { + rcar_image_header[loop] = + rcar_image_header_tmp + [loop * 2U + 1U]; + rcar_image_header_prttn[loop] = + rcar_image_header_tmp + [loop * 2U + 2U]; + } + result = IO_SUCCESS; + if ((rcar_image_number == 0U) + || (rcar_image_number > 8U)) { + WARN("Firmware Image Package "\ + "header check failed.\n"); + result = IO_FAIL; + (void) io_close(backend_handle); + } else { + VERBOSE("header looks OK.\n"); + } + } + } + /* load cert file */ + if (IO_SUCCESS == result) { + result = io_seek(backend_handle, IO_SEEK_SET, + (offset + + (ssize_t) + RCAR_SECTOR6_CERT_OFFSET)); + if (result != IO_SUCCESS) { + WARN("Firmware Image Package "\ + "header failed to seek\n"); + result = IO_FAIL; + (void) io_close(backend_handle); + } + } + if (IO_SUCCESS == result) { + result = io_read(backend_handle, + (uintptr_t) + RCAR_SDRAM_CERT_ADDRESS, + (size_t) (RCAR_CERT_SIZE * + (2U + + (size_t) rcar_image_number)), + &bytes_read); + if (result != IO_SUCCESS) { + WARN("cert file read error.\n"); + result = IO_FAIL; + } else { + + rcar_cert_load = RCAR_CERT_LOAD; + } + (void) io_close(backend_handle); + } + } + } + + return result; +} + +/* Close a connection to the FIP device */ +static int32_t rcar_dev_close(io_dev_info_t *dev_info) +{ + /* TODO: Consider tracking open files and cleaning them up here */ + + /* Clear the backend. */ + backend_dev_handle = (uintptr_t)0; + backend_image_spec = (uintptr_t)0; + + return IO_SUCCESS; +} + + +/* Open a file for access from package. */ +static int32_t rcar_file_open(io_dev_info_t *dev_info, const uintptr_t spec, + io_entity_t *entity) +{ + int32_t result; + uintptr_t file_offset; + uint32_t noload; + uint32_t cert_addr; + uint32_t l_image_size; + uintptr_t dest_addr; + uintptr_t emmc_prttn; + const io_drv_spec_t *file_spec = (io_drv_spec_t *)spec; + + assert(file_spec != NULL); + assert(entity != NULL); + + /* Can only have one file open at a time for the moment. We need to + * track state like file cursor position. We know the header lives at + * offset zero, so this entry should never be zero for an active file. + * When the system supports dynamic memory allocation we can allow more + * than one open file at a time if needed. + */ + if (current_file.offset_address != 0U) { + WARN("rcar_file_open : Only one open file at a time.\n"); + result = IO_RESOURCES_EXHAUSTED; + } else { + + /* get file offset(but BL33 image id not get) */ + result = file_to_offset(file_spec->offset, + &file_offset, &cert_addr, &noload, &emmc_prttn); + if (result != IO_SUCCESS) { + WARN("Failed to open file name %ld (%i)\n", + file_spec->offset, result); + result = IO_FAIL; + } else { + if (0U != noload) { + current_file.offset_address = 1U; + current_file.dest_address = 0U; + current_file.size = 1U; + current_file.file_pos = 0U; + current_file.is_noload = noload; + current_file.partition = 0U; + entity->info = (uintptr_t) ¤t_file; + + } else { + + /* get image size and destination address */ + get_info_from_cert((uint64_t) cert_addr, + &l_image_size, &dest_addr); + + current_file.offset_address = file_offset; + current_file.dest_address = dest_addr; + current_file.size = l_image_size; + current_file.file_pos = 0U; + current_file.is_noload = noload; + current_file.partition = emmc_prttn; + entity->info = (uintptr_t) ¤t_file; + } + } + } + + return result; +} + + +/* Return the size of a file in package */ +static int32_t rcar_file_len(io_entity_t *entity, size_t *length) +{ + assert(entity != NULL); + assert(length != NULL); + + *length = ((file_state_t *)entity->info)->size; + + return IO_SUCCESS; +} + + +/* Read data from a file in package */ +static int32_t rcar_file_read(io_entity_t *entity, uintptr_t buffer, size_t length, + size_t *length_read) +{ + int32_t result; + file_state_t *fp; + ssize_t file_offset; + size_t bytes_read; + uintptr_t backend_handle; +#ifdef SPD_NONE + static uint32_t load_bl33x_counter = 1U; +#else + static uint32_t load_bl33x_counter = 0U; +#endif /* SPD_NONE */ + + assert(entity != NULL); + assert(buffer != (uintptr_t)NULL); + assert(length_read != NULL); + assert(entity->info != (uintptr_t)NULL); + + /* cert image no load */ + if ( 0U != current_file.is_noload ) { + result = IO_SUCCESS; + *length_read = length; + } else { + fp = (file_state_t *) entity->info; + /* set eMMC partition */ + ((io_drv_spec_t *)backend_image_spec)->partition = + (uint32_t)fp->partition;/* needs 32-bits only */ + + + /* Open the backend, attempt to access the blob image */ + result = io_open(backend_dev_handle, backend_image_spec, + &backend_handle); + if (result != IO_SUCCESS) { + WARN("Failed to open FIP (%i)\n", result); + result = IO_FAIL; + } else { + + /* Seek to the position in the FIP where the payload lives */ + file_offset = (ssize_t) fp->offset_address + + (ssize_t) fp->file_pos; + result = io_seek(backend_handle, IO_SEEK_SET, + file_offset); + if (result != IO_SUCCESS) { + WARN("rcar_file_read: failed to seek\n"); + result = IO_FAIL; + } + + if (load_bl33x_counter == 2U) { + /* Loading target is BL33 */ + result = check_load_area((uintptr_t)file_offset, + buffer, + (uintptr_t)length); + if (result != IO_SUCCESS) { + WARN("rcar_file_read: load area err\n"); + result = IO_FAIL; + } + } + + if (result == IO_SUCCESS) { + result = io_read(backend_handle, buffer, length, + &bytes_read); + if (result != IO_SUCCESS) { + /* We cannot read our data. Fail. */ + WARN("Failed to read payload (%i)\n", + result); + result = IO_FAIL; + } else { + /* Set caller length and new file position. */ + *length_read = bytes_read; + fp->file_pos += (uint32_t) bytes_read; + } + } + /* Close the backend. */ + (void) io_close(backend_handle); + + if (result == IO_SUCCESS) { + load_bl33x_counter += 1U; + if (load_bl33x_counter == 3U) { + result = load_bl33x(); + } + } + } + } + + return result; +} + + +/* Close a file in package */ +static int32_t rcar_file_close(io_entity_t *entity) +{ + /* Clear our current file pointer. + * If we had malloc() we would free() here. + */ + assert(entity != NULL); + if (current_file.offset_address != 0U) { + (void)memset(¤t_file, 0, sizeof(current_file)); + } + + /* Clear the Entity info. */ + entity->info = 0U; + + return IO_SUCCESS; +} + +/* Exported functions */ + +/* Register the Firmware Image Package driver with the IO abstraction */ +int32_t register_io_dev_rcar(const io_dev_connector_t **dev_con) +{ + int32_t result; + assert(dev_con != NULL); + + result = io_register_device(&rcar_dev_info); + if (result == IO_SUCCESS) { + *dev_con = &rcar_dev_connector; + } + + return result; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/memdrv/rcar_console.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/memdrv/rcar_console.S new file mode 100644 index 0000000..8b3689f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/memdrv/rcar_console.S @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include + + .globl console_init + .globl console_putc + .globl console_uninit + .globl console_core_init + .globl console_core_putc + .globl console_core_getc + + .extern rcar_log_init + .extern rcar_set_log_data + + /* ----------------------------------------------- + * int console_core_init(unsigned long base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the log area. This + * function will be accessed by console_init and + * crash reporting. + * Return 1 on SUCCESS, 0 on error + * In: x0 - Not used + * w1 - Not used + * w2 - Not used + * ----------------------------------------------- + */ +func console_core_init + b rcar_log_init +endfunc console_core_init +func console_init + b console_core_init +endfunc console_init + + /* -------------------------------------------------------- + * int console_core_putc(int c, unsigned long base_addr) + * Function to output a character over the log area. + * Return 1 on SUCCESS, 0 on error + * In : w0 - Not used + * x1 - Not used + * -------------------------------------------------------- + */ +func console_core_putc + b rcar_set_log_data +endfunc console_core_putc +func console_putc + b console_core_putc +endfunc console_putc + + /* --------------------------------------------- + * int console_core_getc(unsigned long base_addr) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * In : x0 - console base address + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_core_getc + ret +endfunc console_core_getc + + /* ----------------------------------------------- + * void console_uninit(void) + * Function to finish the use of console driver. + * ----------------------------------------------- + */ +func console_uninit + ret +endfunc console_uninit diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/memdrv/rcar_printf.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/memdrv/rcar_printf.c new file mode 100644 index 0000000..6b31138 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/memdrv/rcar_printf.c @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include "rcar_def.h" +#include "rcar_private.h" +#include "rcar_printf.h" + +#define INDEX_TIMER_COUNT (4U) + +extern RCAR_INSTANTIATE_LOCK + +typedef struct log_head +{ + uint8_t head[4]; + uint32_t index; + uint32_t size; + uint8_t res[4]; +} loghead_t; + +typedef struct log_map +{ + loghead_t header; + uint8_t log_data[RCAR_BL31_LOG_MAX]; + uint8_t res_data[RCAR_LOG_RES_SIZE]; +} logmap_t; + +void rcar_set_log_time(void) +{ + uint64_t now_time; + uint64_t freq; + uint64_t second; + uint64_t micro_sec; + uint64_t t_log[2][15]; + int32_t i; + int32_t start_counter; + + now_time = (uint64_t)read_cntpct_el0(); +#ifndef IMAGE_BL2 + now_time += rcar_stack_generic_timer[INDEX_TIMER_COUNT]; +#endif + freq = read_cntfrq_el0(); /* get the frequency */ + if (freq == 0U) { /* for zero division */ + second = 0U; + micro_sec = 0U; + } else { + second = now_time / freq; + micro_sec = ((now_time % freq) * 1000000U) / freq; + } + i = 14; /* counter initialize */ + do { + t_log[0][i] = second % 10U; + second = second / 10U; + i--; + } while (second != 0U); + for (; i >= 10; i--) { + t_log[0][i] = (int)' '; + } + start_counter = i + 1; + t_log[1][0] = micro_sec / 100000U; + micro_sec %= 100000U; + t_log[1][1] = micro_sec / 10000U; + micro_sec %= 10000U; + t_log[1][2] = micro_sec / 1000U; + micro_sec %= 1000U; + t_log[1][3] = micro_sec / 100U; + micro_sec %= 100U; + t_log[1][4] = micro_sec / 10U; + t_log[1][5] = micro_sec % 10U; + + (void)putchar((int)'['); + for (i = start_counter; i < 15; i++) { + if (t_log[0][i] <= 9) { + (void)putchar((int)((int)t_log[0][i] + (int)0x30)); + } else { + (void)putchar((int)' '); + } + } + (void)putchar((int)'.'); + for (i = 0; i < 6; i++) { + (void)putchar((int)((int)t_log[1][i] + (int)0x30)); + } + (void)putchar((int)']'); + (void)putchar((int)' '); +} + +int32_t rcar_set_log_data(int32_t c) +{ + logmap_t *t_log; + + t_log = (logmap_t *)RCAR_BL31_LOG_BASE; + + rcar_lock_get(); + + /* + * If index is broken, then index and size initialize + */ + if (t_log->header.index >= (uint32_t)RCAR_BL31_LOG_MAX) { + t_log->header.index = 0U; + t_log->header.size = 0U; + } + /* + * data store to log area then index and size renewal + */ + t_log->log_data[t_log->header.index] = (uint8_t)c; + t_log->header.index++; + if (t_log->header.size < t_log->header.index) { + t_log->header.size = t_log->header.index; + } + if (t_log->header.index >= (uint32_t)RCAR_BL31_LOG_MAX) { + t_log->header.index = 0U; + } + + rcar_lock_release(); + + return(1); +} + +int32_t rcar_log_init(void) +{ + + static const uint8_t const_header[] = "TLOG"; + logmap_t *t_log; + int16_t init_flag = 0; + + t_log = (logmap_t *)RCAR_BL31_LOG_BASE; + if (memcmp((const void *)t_log->header.head, (const void *)const_header, sizeof(t_log->header.head)) != 0) { + /* + * Log header is not "TLOG", then log area initialize + */ + init_flag = 1; + } + if (t_log->header.index >= (uint32_t)RCAR_BL31_LOG_MAX) { + /* + * index is broken, then log area initialize + */ + init_flag = 1; + } + if (init_flag == 1) { + (void)memset((void *)t_log->log_data, 0, (size_t)RCAR_BL31_LOG_MAX); + (void)memcpy((void *)t_log->header.head, (const void *)const_header, sizeof(t_log->header.head)); + t_log->header.index = 0U; + t_log->header.size = 0U; +#ifndef IMAGE_BL2 + rcar_stack_generic_timer[INDEX_TIMER_COUNT] = 0U; +#endif + } + rcar_lock_init(); + + return(1); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/memdrv/rcar_printf.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/memdrv/rcar_printf.h new file mode 100644 index 0000000..2b8b505 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/memdrv/rcar_printf.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_PRINTF_H__ +#define RCAR_PRINTF_H__ + +#include + +void rcar_set_log_time(void); +int32_t rcar_set_log_data(int32_t c); +int32_t rcar_log_init(void); + +#if IMAGE_BL31 +extern uint64_t rcar_stack_generic_timer[5]; +#endif + +#endif /* RCAR_PRINTF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/pwrc/rcar_call_sram.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/pwrc/rcar_call_sram.S new file mode 100644 index 0000000..0a2dac2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/pwrc/rcar_call_sram.S @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "rcar_def.h" + +.global rcar_bl31_asm_switch_stack_pointer +.global rcar_bl31_save_generic_timer +.global rcar_bl31_restore_generic_timer + +#define OFFSET_SP_X9_X10 (0x00) +#define OFFSET_CNTFID0 (0x10) +#define OFFSET_CNTPCT_EL0 (0x18) +#define OFFSET_TIMER_COUNT (0x20) + +/* X0 : Jump address */ +/* X1 : Stack address */ +/* X2 : arg */ +/* X3 : Stack address temporary */ +func rcar_bl31_asm_switch_stack_pointer + + /* lr to stack */ + stp x29, x30, [sp,#-16] + + /* change stack pointer */ + mov x3, sp + mov sp, x1 + + /* save stack pointer */ + sub sp, sp, #16 + stp x0, x3, [sp] + + /* data synchronization barrier */ + dsb sy + + /* jump to code */ + mov x1, x0 + mov x0, x2 + blr x1 + + /* load stack pointer */ + ldp x0, x2, [sp,#0] + + /* change stack pointer */ + mov sp, x2 + + /* return */ + ldp x29, x30, [sp,#-16] + ret +endfunc rcar_bl31_asm_switch_stack_pointer + +/* X0 : Stack pointer base addrtess */ +func rcar_bl31_save_generic_timer + + stp x9, x10, [x0, #OFFSET_SP_X9_X10] + + /* stop the generic timer */ + mov_imm x10, (RCAR_CNTC_BASE_A + CNTCR_OFF) + mov x9, #0 + str w9, [x10] + + /* save CNTFID0 and cntpct_el0 */ + mov_imm x10, (RCAR_CNTC_BASE_A + CNTFID_OFF) + ldr x9, [x10] + mrs x10, cntpct_el0 + stp x9, x10, [x0, #OFFSET_CNTFID0] + + ldp x9, x10, [x0, #OFFSET_SP_X9_X10] + + ret +endfunc rcar_bl31_save_generic_timer + +/* X0 : Stack pointer base addrtess */ +func rcar_bl31_restore_generic_timer + + stp x9, x10, [x0, #OFFSET_SP_X9_X10] + + /* restore CNTFID0 and cntpct_el0 */ + ldr x10, [x0, #OFFSET_CNTFID0] + mov_imm x9, (RCAR_CNTC_BASE_A + CNTFID_OFF) + str x10, [x9] + ldp x9, x10, [x0, #OFFSET_CNTPCT_EL0] + add x9, x9, x10 + str x9, [x0, #OFFSET_TIMER_COUNT] + + ldp x9, x10, [x0, #OFFSET_SP_X9_X10] + + ret +endfunc rcar_bl31_restore_generic_timer diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/pwrc/rcar_pwrc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/pwrc/rcar_pwrc.c new file mode 100644 index 0000000..ffe40e2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/pwrc/rcar_pwrc.c @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "rcar_def.h" +#include "rcar_private.h" +#include "rcar_pwrc.h" +#include "iic_dvfs.h" + +/* + * TODO: Someday there will be a generic power controller api. At the moment + * each platform has its own pwrc so just exporting functions is fine. + */ +RCAR_INSTANTIATE_LOCK + +#define WUP_IRQ_SHIFT (0U) +#define WUP_FIQ_SHIFT (8U) + +#define BIT_SOFTRESET ((uint32_t)1U<<15) + +#define STATE_CA53_CPU (22U) + +#define STATUS_L2RST ((uint32_t)0U<<4) +#define MODE_L2_DOWN (0x00000002U) +#define CPU_PWR_OFF (0x00000003U) + +/* for suspend to ram */ +/* DBSC Defines */ +#define DBSC4_REG_BASE (0xE6790000U) +#define DBSC4_REG_DBACEN (DBSC4_REG_BASE + 0x0200U) +#define DBSC4_REG_DBCMD (DBSC4_REG_BASE + 0x0208U) +#define DBSC4_REG_DBRFEN (DBSC4_REG_BASE + 0x0204U) +#define DBSC4_REG_DBWAIT (DBSC4_REG_BASE + 0x0210U) + +#define DBSC4_BIT_DBACEN_ACCEN ((uint32_t)(1U << 0)) +#define DBSC4_BIT_DBRFEN_ARFEN ((uint32_t)(1U << 0)) +#define DBSC4_SET_DBCMD_OPC_PRE (0x04000000U) +#define DBSC4_SET_DBCMD_OPC_SR (0x0A000000U) +#define DBSC4_SET_DBCMD_OPC_PD (0x08000000U) +#define DBSC4_SET_DBCMD_CH_ALL (0x00800000U) +#define DBSC4_SET_DBCMD_RANK_ALL (0x00040000U) +#define DBSC4_SET_DBCMD_ARG_ALL (0x00000010U) +#define DBSC4_SET_DBCMD_ARG_ENTER (0x00000000U) + +/* PMIC for BD9571MWV-M*/ +#define PMIC_SLAVE_ADDR (0x30U) +#define PMIC_BKUP_MODE_CNT (0x20U) +#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4)) + +#define PMIC_RETRY_MAX (100U) + +/* sctlr_el3 M bit (for QAC) */ +#define SCTLR_EL3_M_BIT ((uint32_t)1U << 0) + +/* prototype */ +#if PMIC_ON_BOARD +static void rcar_bl31_set_self_refresh(void); +#endif /* PMIC_ON_BOARD */ + +uint32_t rcar_pwrc_status(uint64_t mpidr) +{ + uint32_t rc; + uint64_t cpu_no; + uint32_t prr_data; + + rcar_lock_get(); + prr_data = mmio_read_32((uintptr_t)RCAR_PRR); + cpu_no = mpidr & (uint64_t)MPIDR_CPU_MASK; + if ((mpidr & ((uint64_t)MPIDR_CLUSTER_MASK)) == 0U) { + /* A53 side */ + if ((prr_data & ((uint32_t)1U << (STATE_CA53_CPU + cpu_no))) + == 0U) { + rc = 0U; + } else { + rc = RCAR_INVALID; + } + } else { + rc = RCAR_INVALID; + } + rcar_lock_release(); + + return rc; +} + +void rcar_pwrc_cpuon(uint64_t mpidr) +{ + + uintptr_t res_reg; + uint32_t res_data; + uintptr_t on_reg; + uint64_t cpu_no; + uint32_t upper_value; + uint32_t wup_data; + + rcar_lock_get(); + + cpu_no = mpidr & (uint64_t)MPIDR_CPU_MASK; + if ((mpidr & ((uint64_t)MPIDR_CLUSTER_MASK)) == 0U) { + /* A53 side */ + res_reg = (uintptr_t)RCAR_CA53RESCNT; + on_reg = (uintptr_t)RCAR_CA53WUPCR; + upper_value = 0x5A5A0000U; + } else { + panic(); + } + res_data = mmio_read_32(res_reg) | upper_value; + wup_data = (uint32_t)((uint32_t)1U << cpu_no); + mmio_write_32(RCAR_CPGWPR, ~wup_data); + mmio_write_32(on_reg, wup_data); + /* Dessert to CPU reset */ + mmio_write_32(res_reg, (res_data & (~((uint32_t)1U << (3U - cpu_no))))); + rcar_lock_release(); +} + +void rcar_pwrc_cpuoff(uint64_t mpidr) +{ + uintptr_t off_reg; + uint64_t cpu_no; + + rcar_lock_get(); + cpu_no = mpidr & (uint64_t)MPIDR_CPU_MASK; + if ((mpidr & ((uint64_t)MPIDR_CLUSTER_MASK)) == 0U) { + /* A53 side */ + off_reg = (uintptr_t)RCAR_CA53CPU0CR; + } else { + panic(); + } + if (read_mpidr_el1() == mpidr) { + mmio_write_32(RCAR_CPGWPR, ~((uint32_t)CPU_PWR_OFF)); + mmio_write_32(off_reg + (cpu_no * 0x0010U), + (uint32_t)CPU_PWR_OFF); + } else { + panic(); + } + rcar_lock_release(); +} + +void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr) +{ + uintptr_t reg; + uint64_t cpu_no; + uint32_t shift_irq; + uint32_t shift_fiq; + + rcar_lock_get(); + cpu_no = mpidr & (uint64_t)MPIDR_CPU_MASK; + if ((mpidr & ((uint64_t)MPIDR_CLUSTER_MASK)) == 0U) { + /* A53 side */ + reg = (uintptr_t)RCAR_WUPMSKCA53; + } else { + panic(); + } + shift_irq = WUP_IRQ_SHIFT + (uint32_t)cpu_no; + shift_fiq = WUP_FIQ_SHIFT + (uint32_t)cpu_no; + mmio_write_32(reg, (uint32_t)((~((uint32_t)1U << shift_irq)) + & (~((uint32_t)1U << shift_fiq)))); + rcar_lock_release(); +} + +void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr) +{ + uintptr_t reg; + uint64_t cpu_no; + uint32_t shift_irq; + uint32_t shift_fiq; + + rcar_lock_get(); + cpu_no = mpidr & (uint64_t)MPIDR_CPU_MASK; + if ((mpidr & ((uint64_t)MPIDR_CLUSTER_MASK)) == 0U) { + /* A53 side */ + reg = (uintptr_t)RCAR_WUPMSKCA53; + } else { + panic(); + } + shift_irq = WUP_IRQ_SHIFT + (uint32_t)cpu_no; + shift_fiq = WUP_FIQ_SHIFT + (uint32_t)cpu_no; + mmio_write_32(reg, (uint32_t)(((uint32_t)1U << shift_irq) + | ((uint32_t)1U << shift_fiq))); + rcar_lock_release(); +} + +void rcar_pwrc_clusteroff(uint64_t mpidr) +{ + uint64_t target_core; + uintptr_t reg_CPUCMCR; + + rcar_lock_get(); + target_core = mpidr & ((uint64_t)MPIDR_CLUSTER_MASK); + if (target_core == 0U) { + reg_CPUCMCR = (uintptr_t)RCAR_CA53CPUCMCR; + } else { + panic(); + } + /* all of the CPUs in the cluster is in the CoreStandby mode */ + mmio_write_32(reg_CPUCMCR, (uint32_t)(STATUS_L2RST | MODE_L2_DOWN)); + rcar_lock_release(); +} + +#if !PMIC_ON_BOARD +void rcar_pwrc_system_reset(void) +{ + mmio_write_32(RCAR_SRESCR, (0x5AA50000U | BIT_SOFTRESET)); +} +#endif + +#define RST_CA53CPU0BARH (0xE6160080U) +#define RST_CA53CPU0BARL (0xE6160084U) + +/* Nothing else to do here apart from initializing the lock */ +void rcar_pwrc_setup(void) +{ + uintptr_t rst_CA5xCPUxBARH = RST_CA53CPU0BARH; + uintptr_t rst_CA5xCPUxBARL = RST_CA53CPU0BARL; + uint32_t loop; + uint32_t loop_max = 2U; + + for (loop = 0U; loop < loop_max; loop ++) { + mmio_write_32(rst_CA5xCPUxBARH, 0U); + mmio_write_32(rst_CA5xCPUxBARL, + (uint32_t)((uint64_t)&bl31_secondly_reset + & 0xFFFFFFFFU)); + rst_CA5xCPUxBARH += 0x10U; + rst_CA5xCPUxBARL += 0x10U; + } + + rcar_lock_init(); +} + +#if PMIC_ON_BOARD +void __attribute__ ((section (".system_ram"))) __attribute__ ((noinline)) rcar_bl31_go_suspend_to_ram(void) +{ + + rcar_bl31_set_self_refresh(); /* Self-Refresh */ + + wfi(); + + /* no return */ + while(1){} +} + +static void __attribute__ ((section (".system_ram"))) rcar_bl31_set_self_refresh(void) +{ + uint32_t reg; + uint32_t i; + + /* Set the Self-Refresh mode */ + mmio_write_32(DBSC4_REG_DBACEN, 0U); /* Set the ACCEN bit to 0 in the DBACEN */ + /* Wait until the processing in response to the SDRAM access request in the DBSC4 is completed. */ + for ( i=0U; i<10000U ;i++ ){ + } + + reg = DBSC4_SET_DBCMD_OPC_PRE | + DBSC4_SET_DBCMD_CH_ALL | + DBSC4_SET_DBCMD_RANK_ALL | + DBSC4_SET_DBCMD_ARG_ALL; + mmio_write_32(DBSC4_REG_DBCMD, reg); /* PREA command */ + /* Poll the operation completion waiting register (DBWAIT) to check when the issuing of manual commands is complete. */ + while (mmio_read_32(DBSC4_REG_DBWAIT) != 0U){ + } + + reg = DBSC4_SET_DBCMD_OPC_SR | + DBSC4_SET_DBCMD_CH_ALL | + DBSC4_SET_DBCMD_RANK_ALL | + DBSC4_SET_DBCMD_ARG_ENTER; + mmio_write_32(DBSC4_REG_DBCMD, reg); /* Self-Refresh entry command */ + /* Poll the operation completion waiting register (DBWAIT) to check when the issuing of manual commands is complete. */ + while (mmio_read_32(DBSC4_REG_DBWAIT) != 0U){ + } + + reg = DBSC4_SET_DBCMD_OPC_PD | + DBSC4_SET_DBCMD_CH_ALL | + DBSC4_SET_DBCMD_RANK_ALL | + DBSC4_SET_DBCMD_ARG_ENTER; + mmio_write_32(DBSC4_REG_DBCMD, reg); /* Power Down entry command */ + /* Poll the operation completion waiting register (DBWAIT) to check when the issuing of manual commands is complete. */ + while (mmio_read_32(DBSC4_REG_DBWAIT) != 0U){ + } + + mmio_write_32(DBSC4_REG_DBRFEN, 0U); /* Set the ARFEN bit to 0 in the DBRFEN */ + + /* Wait for the tCKELPD period. */ + for ( i=0U; i<10000U; i++ ){ + } + /* DDR PHY must be entered "deep sleep" mode (details are T.B.D.). */ + /* MxBKUP is set High Level. */ + /* The power except the DDR IO are removed. */ +} + +void rcar_bl31_code_copy_to_system_ram(void) +{ + (void)memcpy((void *)DEVICE_SRAM_SHADOW_BASE, &__SRAM_COPY_START__, + (size_t)((uint64_t)__system_ram_end__ - (uint64_t)__system_ram_start__)); + + flush_dcache_range((uint64_t)DEVICE_SRAM_SHADOW_BASE, + ((uint64_t)__system_ram_end__ - (uint64_t)__system_ram_start__)); + + /* Invalidate instruction cache */ + iciallu(); + dsb(); + isb(); +} + +void rcar_bl31_set_suspend_to_ram(void) +{ + uint32_t sctlr; + + rcar_bl31_code_copy_to_system_ram(); + + rcar_bl31_save_generic_timer(rcar_stack_generic_timer); + + /* disable MMU */ + sctlr = (uint32_t)read_sctlr_el3(); + sctlr &= (uint32_t)~SCTLR_EL3_M_BIT; + write_sctlr_el3((uint64_t)sctlr); + + (void)rcar_bl31_asm_switch_stack_pointer((uintptr_t)&rcar_bl31_go_suspend_to_ram, + (uintptr_t)(DEVICE_SRAM_STACK_BASE\ + + DEVICE_SRAM_STACK_SIZE_U), NULL); +} + +void rcar_bl31_init_suspend_to_ram(void) +{ + + rcar_bl31_code_copy_to_system_ram(); + +} +#endif /* PMIC_ON_BOARD */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/pwrc/rcar_pwrc.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/pwrc/rcar_pwrc.h new file mode 100644 index 0000000..80e52a3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/pwrc/rcar_pwrc.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_PWRC_H__ +#define RCAR_PWRC_H__ + +/* RCAR Power controller register offset etc */ +#define PPOFFR_OFF 0x0 +#define PPONR_OFF 0x4 +#define PCOFFR_OFF 0x8 +#define PWKUPR_OFF 0xc +#define PSYSR_OFF 0x10 + +#define PWKUPR_WEN (1ull << 31) + +#define PSYSR_AFF_L2 (1 << 31) +#define PSYSR_AFF_L1 (1 << 30) +#define PSYSR_AFF_L0 (1 << 29) +#define PSYSR_WEN (1 << 28) +#define PSYSR_PC (1 << 27) +#define PSYSR_PP (1 << 26) + +#define PSYSR_WK_SHIFT (24) +#define PSYSR_WK_MASK (0x3) +#define PSYSR_WK(x) (((x) >> PSYSR_WK_SHIFT) & PSYSR_WK_MASK) + +#define WKUP_COLD 0x0 +#define WKUP_RESET 0x1 +#define WKUP_PPONR 0x2 +#define WKUP_GICREQ 0x3 + +#define RCAR_INVALID (0xffffffffU) +#define PSYSR_INVALID 0xffffffff + +#ifndef __ASSEMBLY__ + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void rcar_pwrc_setup(void); +void rcar_pwrc_clusteroff(uint64_t mpidr); +void rcar_pwrc_cpuoff(uint64_t mpidr); +void rcar_pwrc_cpuon(uint64_t mpidr); +void rcar_pwrc_enable_interrupt_wakeup(uint64_t mpidr); +void rcar_pwrc_disable_interrupt_wakeup(uint64_t mpidr); +uint32_t rcar_pwrc_status(uint64_t mpidr); +uint32_t rcar_pwrc_get_cpu_wkr(uint64_t mpidr); +#if !PMIC_ON_BOARD +void rcar_pwrc_system_reset(void); +#endif +void bl31_secondly_reset(void); + +#if PMIC_ON_BOARD +/* for Suspend to RAM */ +void rcar_bl31_go_suspend_to_ram(void); +void rcar_bl31_set_suspend_to_ram(void); +void rcar_bl31_code_copy_to_system_ram(void); +void rcar_bl31_init_suspend_to_ram(void); +#endif /* PMIC_ON_BOARD */ + +extern uint32_t rcar_bl31_asm_switch_stack_pointer(uintptr_t jump, uintptr_t stack, + void *arg); + +extern void rcar_bl31_save_generic_timer(uint64_t *rcar_stack_generic_timer); + +extern uint8_t __system_ram_start__[1]; +extern uint8_t __system_ram_end__[1]; +extern uint8_t __SRAM_COPY_START__[1]; + +extern uint64_t rcar_stack_generic_timer[5]; + +#endif /*__ASSEMBLY__*/ + +#endif /* RCAR_PWRC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/rom/rom_api.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/rom/rom_api.c new file mode 100644 index 0000000..82fddf7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/rom/rom_api.c @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "rcar_def.h" +#include "rom_api.h" + + +typedef uint32_t (*ROM_SECURE_BOOT_API)(uint32_t *pKeyCert, + uint32_t *pContentCert, + ROM_FuncReadFlash pFuncReadFlash); +typedef uint32_t (*ROM_GETLCS_API)(uint32_t *pLcs); + +static uint32_t get_table_index(void); + +#define V3M_API_TABLE (0U) /* V3M ES1.0 */ +#define NEW_API_TABLE (1U) /* V3M ES2.0 */ +#define API_TABLE_MAX (2U) /* table max */ + +uint32_t ROM_SecureBootAPI( uint32_t *pKeyCert, + uint32_t *pContentCert, + ROM_FuncReadFlash pFuncReadFlash) +{ + /* Secure Boot API address table */ + static const uintptr_t ROM_SecureBootAPI_table[API_TABLE_MAX] = { + 0xEB110128U, /* V3M ES1.0 */ + 0xEB100180U /* V3M ES2.0 or later */ + }; + + ROM_SECURE_BOOT_API func; + uint32_t index; + + index = get_table_index(); + func = (ROM_SECURE_BOOT_API)ROM_SecureBootAPI_table[index]; + + return func(pKeyCert, pContentCert, pFuncReadFlash); +} + + +uint32_t ROM_GetLcs(uint32_t *pLcs) +{ + /* Get LCS stete API address table */ + static const uintptr_t ROM_GetLcs_table[API_TABLE_MAX] = { + 0xEB1103A4U, /* V3M ES1.0 */ + 0xEB10018CU /* V3M ES2.0 or later */ + }; + + ROM_GETLCS_API func; + uint32_t index; + + index = get_table_index(); + func = (ROM_GETLCS_API)ROM_GetLcs_table[index]; + + return func(pLcs); +} + + +static uint32_t get_table_index(void) +{ + uint32_t cut_ver; + uint32_t index; + + cut_ver = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK; + + if (cut_ver == RCAR_CUT_ES10) { + index = V3M_API_TABLE; /* V3M ES1.0 */ + } else { + index = NEW_API_TABLE; /* V3M ES2.0 or later */ + } + + return index; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/rpc/rpc_driver.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/rpc/rpc_driver.c new file mode 100644 index 0000000..2cf9895 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/rpc/rpc_driver.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2015-2018, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "bl2_cpg_register.h" +#include "bl2_cpg_init.h" +#include "bl2_rpc_register.h" +#include "rpc_driver.h" +#include "debug.h" + +static void enableRPC(void); +static void setupRPC(void); + +static void enableRPC(void) +{ + while((mmio_read_32(CPG_MSTPSR9) & 0x00020000U) != 0U) { + cpg_write(CPG_SMSTPCR9, + mmio_read_32(CPG_SMSTPCR9) & (~0x00020000U)); + } +} + +static void setupRPC(void) +{ + /* manual mode */ + if ((mmio_read_32(RPC_CMNCR) & 0x80000000U) != 0U) { + /* external address space read mode */ + mmio_write_32(RPC_CMNCR, + mmio_read_32(RPC_CMNCR) & (~0x80000000U)); + } + + /* check the transfer end flag */ + while((mmio_read_32(RPC_CMNSR) & 0x1U) != 1U){ + } + +} + +void initRPC(void) +{ + enableRPC(); + setupRPC(); +} + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/scif/scif.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/scif/scif.S new file mode 100644 index 0000000..ed91dbf --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/scif/scif.S @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "scif.h" + +/* Product Register */ +#define PRR (0xFFF00044) +#define PRR_PRODUCT_MASK (0x00007FFF) + +/* module stop */ +#define CPG_BASE (0xE6150000) +#define CPG_SMSTPCR3 (0x013C) +#define MSTP310 (1 << 10) +#define MSTP207 (1 << 7) +#define CPG_CPGWPR (0x0900) +#define CPG_MSTPSR2 (0x0040) +#define CPG_SMSTPCR2 (0x0138) + +/* SCIF_BASE */ +#define SCIF0_BASE (0xE6E60000) /* SCIF-0 base address */ + +#define SCIF_SCSMR (0x00) /* Serial mode register */ +#define SCIF_SCBRR (0x04) /* Bit rate register */ +#define SCIF_SCSCR (0x08) /* Serial control register */ +#define SCIF_SCFTDR (0x0C) /* Transmit FIFO data register */ +#define SCIF_SCFSR (0x10) /* Serial status register */ +#define SCIF_SCFRDR (0x14) /* Receive FIFO data register */ +#define SCIF_SCFCR (0x18) /* FIFO control register */ +#define SCIF_SCFDR (0x1C) /* FIFO data count register */ +#define SCIF_SCSPTR (0x20) /* Serial port register */ +#define SCIF_SCLSR (0x24) /* Line status register */ +#define SCIF_DL (0x30) /* Frequency division register */ +#define SCIF_CKS (0x34) /* Clock Select register */ +#define SCIF_SCSMRIR (0x40) /* Serial mode register */ + + +#define SCSMR_CA_MASK (1 << 7) +#define SCSMR_CA_ASYNC (0x0000) +#define SCSMR_CHR_MASK (1 << 6) +#define SCSMR_CHR_8 (0x0000) +#define SCSMR_PE_MASK (1 << 5) +#define SCSMR_PE_DIS (0x0000) +#define SCSMR_STOP_MASK (1 << 3) +#define SCSMR_STOP_1 (0x0000) +#define SCSMR_CKS_MASK (3 << 0) +#define SCSMR_CKS_DIV1 (0x0000) +#define SCSMR_INIT_DATA (SCSMR_CA_ASYNC + SCSMR_CHR_8 + \ + SCSMR_PE_DIS + SCSMR_STOP_1 + \ + SCSMR_CKS_DIV1) + +#define SCBRR_115200BPS (17) /* 115200bps@66MHz */ +#define SCBRR_230400BPS (8) /* 230400bps@66MHz */ + +#define SCSCR_TE_MASK (1 << 5) +#define SCSCR_TE_DIS (0x0000) +#define SCSCR_TE_EN (0x0020) +#define SCSCR_RE_MASK (1 << 4) +#define SCSCR_RE_DIS (0x0000) +#define SCSCR_RE_EN (0x0010) +#define SCSCR_CKE_MASK (3 << 0) +#define SCSCR_CKE_INT (0x0000) +#define SCSCR_CKE_BRG (0x0002) +#if SCIF_CLK == SCIF_EXTARNAL_CLK +#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG) +#else +#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT) +#endif + +#define SCFSR_INIT_DATA (0x0000) + +#define SCFCR_TTRG_MASK (3 << 4) +#define SCFCR_TTRG_8 (0x0000) +#define SCFCR_TTRG_0 (0x0030) +#define SCFCR_TFRST_MASK (1 << 2) +#define SCFCR_TFRST_DIS (0x0000) +#define SCFCR_TFRST_EN (0x0004) +#define SCFCR_RFRS_MASK (1 << 1) +#define SCFCR_RFRS_DIS (0x0000) +#define SCFCR_RFRS_EN (0x0002) +#define SCFCR_INIT_DATA (SCFCR_TTRG_8) + +#define SCFDR_T_MASK (0x1f << 8) + +#define DL_INIT_DATA (8) /* 14.7456MHz/(115200bps*16)*/ + +#define CKS_CKS_DIV_MASK (1 << 15) +#define CKS_CKS_DIV_CLK (0x0000) +#define CKS_XIN_MASK (1 << 14) +#define CKS_XIN_SCIF_CLK (0x0000) +#define CKS_INIT_DATA (CKS_CKS_DIV_CLK + CKS_XIN_SCIF_CLK) + + .globl console_init + .globl console_putc + .globl console_core_init + .globl console_core_putc + .globl console_getc + .globl console_finalize + .globl micro_wait + + /* + * The console base is in the data section and not in .bss + * even though it is zero-init. In particular, this allows + * the console functions to start using this variable before + * the runtime memory is initialized for images which do not + * need to copy the .data section from ROM to RAM. + */ + /* ----------------------------------------------- + * int console_init(unsigned long base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. It saves + * the console base to the data section. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * out: return 1 on success. + * Clobber list : x1 - x3 + * ----------------------------------------------- + */ +func console_init + b console_core_init +endfunc console_init + + /* ----------------------------------------------- + * int console_core_init(unsigned long base_addr, + * unsigned int uart_clk, unsigned int baud_rate) + * Function to initialize the console without a + * C Runtime to print debug information. This + * function will be accessed by console_init and + * crash reporting. + * In: x0 - console base address + * w1 - Uart clock in Hz + * w2 - Baud rate + * Out: return 1 on success + * Clobber list : x1, x2 + * ----------------------------------------------- + */ +func console_core_init + ldr x0, =CPG_BASE + + ldr w1, [x0, #CPG_SMSTPCR2] + and w1, w1, #~MSTP207 /* MSTP207=0 */ + mvn w2, w1 + str w2, [x0, #CPG_CPGWPR] + str w1, [x0, #CPG_SMSTPCR2] +4: + ldr w1, [x0, #CPG_MSTPSR2] + and w1, w1, #MSTP207 + cmp w1, #0 + bne 4b + ldr x0, =SCIF0_BASE + mov w1, #0 + strh w1, [x0, #SCIF_SCSMRIR] + /* Clear bits TE and RE in SCSCR to 0 */ + mov w1, #(SCSCR_TE_DIS + SCSCR_RE_DIS) /* TE=0,RE=0 */ + strh w1, [x0, #SCIF_SCSCR] + /* Set bits TFRST and RFRST in SCFCR to 1 */ + ldrh w1, [x0, #SCIF_SCFCR] + orr w1, w1, #(SCFCR_TFRST_EN + SCFCR_RFRS_EN) /* TFRESET=1,RFRESET=1 */ + strh w1, [x0, #SCIF_SCFCR] + /* Read flags of ER, DR, BRK, and RDF in SCFSR and those of TO and ORER in SCLSR, then clear them to 0 */ + mov w1, #SCFSR_INIT_DATA + strh w1, [x0, #SCIF_SCFSR] + mov w1, #0 + strh w1, [x0, #SCIF_SCLSR] + /* Set bits CKE[1:0] in SCSCR */ + ldrh w1, [x0, #SCIF_SCSCR] + and w1, w1, #~SCSCR_CKE_MASK + mov w2, #SCSCR_CKE_INT_CLK /* CKE=00 */ + orr w1, w1, w2 + strh w1, [x0, #SCIF_SCSCR] + /* Set data transfer format in SCSMR */ + mov w1, #SCSMR_INIT_DATA + strh w1, [x0, #SCIF_SCSMR] /* CA=0,CHR=0,PE=0,STOP=0,CKS=P */ + /* Set value in SCBRR */ +#if SCIF_CLK == SCIF_INTERNAL_CLK + mov w1, #SCBRR_115200BPS /* 115200bps */ + strb w1, [x0, #SCIF_SCBRR] +#else + mov w1, #DL_INIT_DATA + strh w1, [x0, #SCIF_DL] + mov w1, #CKS_INIT_DATA /* CKS=0,XIN=0 */ + strh w1, [x0, #SCIF_CKS] +#endif + /* 1-bit interval elapsed */ + mov w1, #100 /* 100 times */ +1: + subs w1, w1, #1 + cbnz w1, 1b + /* Set bits RTRG[1:0], TTRG[1:0], and MCE in SCFCR, and clear bits FRST and RFRST to 0 */ + mov w1, #SCFCR_INIT_DATA + strh w1, [x0, #SCIF_SCFCR] + /* Set bits TE and RE in SCSCR to 1 */ + ldrh w1, [x0, #SCIF_SCSCR] + orr w1, w1, #(SCSCR_TE_EN + SCSCR_RE_EN) /* TE=1,RE=1 */ + strh w1, [x0, #SCIF_SCSCR] + mov x1, #1 + + ret +endfunc console_core_init + + /* --------------------------------------------- + * int console_putc(int c) + * Function to output a character over the + * console. It returns the character printed on + * success or -1 on error. + * In : x0 - character to be printed + * Out : return -1 on error else return character. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func console_putc + b console_core_putc +endfunc console_putc + + /* -------------------------------------------------------- + * int console_core_putc(int c, unsigned int base_addr) + * Function to output a character over the console. It + * returns the character printed on success or -1 on error. + * In : w0 - character to be printed + * x1 - console base address + * Out : return -1 on error else return character. + * Clobber list : x2 + * -------------------------------------------------------- + */ +func console_core_putc + ldr x1, =SCIF0_BASE + cmp w0, #0xA + /* Prepend '\r' to '\n' */ + bne 2f +1: + /* Check if the transmit FIFO is full */ + ldrh w2, [x1, #SCIF_SCFDR] + ubfx w2, w2, #8, #5 + cmp w2, #16 + bcs 1b + mov w2, #0x0D + strb w2, [x1, #SCIF_SCFTDR] +2: + /* Check if the transmit FIFO is full */ + ldrh w2, [x1, #SCIF_SCFDR] + ubfx w2, w2, #8, #5 + cmp w2, #16 + bcs 2b + strb w0, [x1, #SCIF_SCFTDR] + + ret +endfunc console_core_putc + + /* --------------------------------------------- + * int console_getc(void) + * Function to get a character from the console. + * It returns the character grabbed on success + * or -1 on error. + * Clobber list : x0, x1 + * --------------------------------------------- + */ +func console_getc + mov w0, #-1 /* no support */ + ret +endfunc console_getc + + /* ----------------------------------------------- + * void console_finalize(void) + * ----------------------------------------------- + */ +func console_finalize + ldr x0, =SCIF0_BASE +1: + ldrh w1, [x0, #SCIF_SCFDR] + ubfx w1, w1, #8, #5 + cmp w1, #0 + bne 1b + + mov x0, #100 + mov x3, x30 + bl micro_wait + mov x30, x3 + + ldr x0, =SCIF0_BASE + ldrh w1, [x0, #SCIF_SCSCR] + and w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN) /* TE=0,RE=0 */ + strh w1, [x0, #SCIF_SCSCR] + + ret +endfunc console_finalize + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/timer/bl2_swdt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/timer/bl2_swdt.c new file mode 100644 index 0000000..7064181 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/drivers/timer/bl2_swdt.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "bl2_swdt.h" +#include "rcar_def.h" + +#define RST_BASE (0xE6160000U) +#define RST_WDTRSTCR (RST_BASE + 0x0054U) +#define SWDT_BASE (0xE6030000U) +#define SWDT_WTCNT (SWDT_BASE + 0x0000U) +#define SWDT_WTCSRA (SWDT_BASE + 0x0004U) +#define SWDT_WTCSRB (SWDT_BASE + 0x0008U) +#define SWDT_GICD_BASE (0xF1010000U) +#define SWDT_GICC_BASE (0xF1020000U) +#define SWDT_GICD_CTLR (SWDT_GICD_BASE + 0x0000U) +#define SWDT_GICD_IGROUPR (SWDT_GICD_BASE + 0x0080U) +#define SWDT_GICD_ISPRIORITYR (SWDT_GICD_BASE + 0x0400U) +#define SWDT_GICC_CTLR (SWDT_GICC_BASE + 0x0000U) +#define SWDT_GICC_PMR (SWDT_GICC_BASE + 0x0004U) +#define SWDT_GICD_ITARGETSR (SWDT_GICD_BASE + 0x0800U) +#define IGROUPR_NUM (16U) +#define ISPRIORITY_NUM (128U) +#define ITARGET_MASK ((uint32_t)0x03U) + +#define WDTRSTCR_UPPER_BYTE (0xA55A0000U) +#define WTCSRA_UPPER_BYTE (0xA5A5A500U) +#define WTCSRB_UPPER_BYTE (0xA5A5A500U) +#define WTCNT_UPPER_BYTE (0x5A5A0000U) +#define WTCNT_RESET_VALUE (0xF488U) +#define WTCSRA_BIT_CKS (0x0007U) +#define WTCSRB_BIT_CKS (0x003FU) +#define SWDT_RSTMSK ((uint32_t)1U << 1) +#define WTCSRA_WOVFE ((uint32_t)1U << 3) +#define WTCSRA_WRFLG ((uint32_t)1U << 5) +#define SWDT_ENABLE ((uint32_t)1U << 7) + +#define WDTRSTCR_MASK_ALL (0x0000FFFFU) +#define WTCSRA_MASK_ALL (0x000000FFU) +#define WTCNT_INIT_DATA (WTCNT_UPPER_BYTE + WTCNT_RESET_VALUE) +#define WTCSRA_INIT_DATA (WTCSRA_UPPER_BYTE + 0x0FU) +#define WTCSRB_INIT_DATA (WTCSRB_UPPER_BYTE + 0x21U) + +#define WTCNT_COUNT_8p13k (0x10000U - 40687U) +#define WTCNT_COUNT_8p13k_H3ES1p0 (0x10000U - 20343U) +#define WTCNT_COUNT_8p22k (0x10000U - 41115U) +#define WTCSRA_CKS_DIV16 (0x00000002U) + +static void bl2_swdt_disable(void); + +void bl2_swdt_init(void) +{ + uint32_t sr; + uint32_t rmsk; +// uint32_t product_cut = mmio_read_32((uintptr_t)RCAR_PRR) +// & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); + uint32_t chk_data = mmio_read_32((uintptr_t)RCAR_MODEMR) + & CHECK_MD13_MD14; + + if ((mmio_read_32(SWDT_WTCSRA) & SWDT_ENABLE) != 0U) { + /* Stop SWDT */ + mmio_write_32(SWDT_WTCSRA,WTCSRA_UPPER_BYTE); + } + + /* clock is OSC/16 and overflow interrupt is enabled */ + mmio_write_32(SWDT_WTCSRA,(WTCSRA_UPPER_BYTE | WTCSRA_WOVFE + | WTCSRA_CKS_DIV16)); + + /* Set the overflow counter */ + /* The System Watchdog timer is a single-channel timer */ + /* that uses the OSCCLK as an input clock and can be */ + /* used as a watchdog timer. */ + switch (chk_data) { + case MD14_MD13_TYPE_0: /* MD13=0 and MD14=0 */ + case MD14_MD13_TYPE_2: /* MD13=0 and MD14=1 */ + /* OSCCLK=130.2kHz count=40687, set 0x5A5A6111 */ + mmio_write_32(SWDT_WTCNT,(WTCNT_UPPER_BYTE | + WTCNT_COUNT_8p13k)); + break; + case MD14_MD13_TYPE_1: /* MD13=1 and MD14=0 */ + /* OSCCLK=131.57kHz count=41115, set 0x5A5A5F65 */ + mmio_write_32(SWDT_WTCNT,(WTCNT_UPPER_BYTE | + WTCNT_COUNT_8p22k)); + break; + case MD14_MD13_TYPE_3: /* MD13=1 and MD14=1 */ + /* OSCCLK=130.2kHz */ +// if (product_cut==(RCAR_PRODUCT_H3 | RCAR_CUT_ES10)) { +// /* R-car H3 ES1.0 */ +// /* count=20343, set 0x5A5AB089 */ +// mmio_write_32(SWDT_WTCNT,(WTCNT_UPPER_BYTE | +// WTCNT_COUNT_8p13k_H3ES1p0)); +// } else { + /* count=40687, set 0x5A5A6111 */ + mmio_write_32(SWDT_WTCNT,(WTCNT_UPPER_BYTE | + WTCNT_COUNT_8p13k)); +// } + break; + default: + /* Error */ + ERROR("BL2: MODEMR ERROR value=%x\n", chk_data); + panic(); + break; + } + + rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL; + mmio_write_32(RST_WDTRSTCR,(WDTRSTCR_UPPER_BYTE + | (rmsk | SWDT_RSTMSK))); + while ((mmio_read_8(SWDT_WTCSRA) & WTCSRA_WRFLG) != 0U) { + /* Wait until the WTCNT is reflected */ + ; + } + sr = mmio_read_32(SWDT_WTCSRA) & WTCSRA_MASK_ALL; + /* Start the System WatchDog Timer */ + mmio_write_32(SWDT_WTCSRA,(WTCSRA_UPPER_BYTE | sr | SWDT_ENABLE)); +} + +static void bl2_swdt_disable(void) +{ + uint32_t rmsk; + uintptr_t base = (uintptr_t)RCAR_GICD_BASE; + uint32_t id = (uint32_t)ARM_IRQ_SEC_WDT; + + /* Initialize the HW initial data, but SWDT is not moved */ + rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL; + mmio_write_32(RST_WDTRSTCR,(WDTRSTCR_UPPER_BYTE + | (rmsk | SWDT_RSTMSK))); + mmio_write_32(SWDT_WTCNT,WTCNT_INIT_DATA); + mmio_write_32(SWDT_WTCSRA,WTCSRA_INIT_DATA); + mmio_write_32(SWDT_WTCSRB,WTCSRB_INIT_DATA); + /* Set the interrupt clear enable register */ + gicd_set_icenabler(base, id); +} + +void bl2_swdt_release(void) +{ + uintptr_t p_gicd_ctlr = (uintptr_t)SWDT_GICD_CTLR; + uintptr_t p_igroupr = (uintptr_t)SWDT_GICD_IGROUPR; + uintptr_t p_ispriorityr = (uintptr_t)SWDT_GICD_ISPRIORITYR; + uintptr_t p_gicc_ctlr = (uintptr_t)SWDT_GICC_CTLR; + uintptr_t p_pmr = (uintptr_t)SWDT_GICC_PMR; + uintptr_t p_itargetsr = (uintptr_t)(SWDT_GICD_ITARGETSR + + (ARM_IRQ_SEC_WDT & (uint32_t)(~ITARGET_MASK))); + uint32_t i; + + write_daifset(DAIF_FIQ_BIT); + bl2_swdt_disable(); + gicv2_cpuif_disable(); + for (i=0U; i +#include +#include "micro_wait.h" + + +#define CPG_BASE (0xE6150000) +#define CPG_SMSTPCR1 (0x0134) +#define CPG_CPGWPR (0x0900) + +#define MSTPCR1_TMU1 (1 << 24) + +#define TMU3_BASE (0xE6FC0000) +#define TMU_TSTR (0x0004) +#define TMU_TCOR (0x0008) +#define TMU_TCNT (0x000C) +#define TMU_TCR (0x0010) + +#define TSTR1_TMU3 (1 << 0) + +#define MIDR_CA57 (0x0D07 << MIDR_PN_SHIFT) +#define MIDR_CA53 (0x0D03 << MIDR_PN_SHIFT) + + + .globl micro_wait +#if (TMU3_MEASUREMENT == 1) + .globl init_TMU3 + .globl start_TMU3 + .globl snapshot_TCNT3 + .globl stop_TMU3 +#endif /* TMU3_MEASUREMENT */ + + .align 6 /* Aligned with the cache line */ + +func micro_wait + cbz x0, micro_wait_e + mrs x1, midr_el1 + and x1, x1, #MIDR_PN_MASK << MIDR_PN_SHIFT + mov w2, #MIDR_CA53 + cmp w1, w2 + b.eq micro_wait_ca53 + b micro_wait_ca57 +micro_wait_e: + ret +endfunc micro_wait + + +func micro_wait_ca57 /* Cortex-A57 1.5GHz */ +ca57_loop_1: + mov x1, #185 +ca57_loop_2: + subs x1, x1, #1 + b.ne ca57_loop_2 + subs x0, x0, #1 + b.ne ca57_loop_1 + ret +endfunc micro_wait_ca57 + + +func micro_wait_ca53 /* Cortex-A53 1.2GHz */ +ca53_loop_1: + mov x1, #134 +ca53_loop_2: + subs x1, x1, #1 + b.ne ca53_loop_2 + subs x0, x0, #1 + b.ne ca53_loop_1 + ret +endfunc micro_wait_ca53 + + +/* Time measurement function using the TMU3. */ +#if (TMU3_MEASUREMENT == 1) +func init_TMU3 + ldr x0, =CPG_BASE + ldr w1, [x0, #CPG_SMSTPCR1] + and w1, w1, #~MSTPCR1_TMU1 + mvn w2, w1 + str w2, [x0, #CPG_CPGWPR] + str w1, [x0, #CPG_SMSTPCR1] + dsb sy + ret +endfunc init_TMU3 + + +func start_TMU3 + ldr x0, =TMU3_BASE + mov w1, #0xFFFFFFFF + str w1, [x0, TMU_TCNT] + + ldr x0, =TMU3_BASE + ldrb w1, [x0, TMU_TSTR] + orr w1, w1, #TSTR1_TMU3 + strb w1, [x0, TMU_TSTR] + ret +endfunc start_TMU3 + + +func snapshot_TCNT3 + ldr x0, =TMU3_BASE + ldr w0, [x0, TMU_TCNT] + ret +endfunc snapshot_TCNT3 + + +func stop_TMU3 + ldr x0, =TMU3_BASE + ldrb w1, [x0, TMU_TSTR] + and w1, w1, #~TSTR1_TMU3 + strb w1, [x0, TMU_TSTR] + ret +endfunc stop_TMU3 +#endif /* TMU3_MEASUREMENT */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/avs_driver.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/avs_driver.h new file mode 100644 index 0000000..287853d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/avs_driver.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef AVS_DRIVER_H__ +#define AVS_DRIVER_H__ + +/* AVS Setting. 1:enable / 0:disable */ +#ifndef AVS_SETTING_ENABLE +#define AVS_SETTING_ENABLE 1 +#endif /* AVS_SETTING_ENABLE */ + +void bl2_avs_init(void); +void bl2_avs_setting(void); +void bl2_avs_end(void); + +#endif /* AVS_DRIVER_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_cpg_init.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_cpg_init.h new file mode 100644 index 0000000..e30ae29 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_cpg_init.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef BL2_CPG_INIT_H__ +#define BL2_CPG_INIT_H__ + +void bl2_cpg_init(void); +void bl2_system_cpg_init(void); +void cpg_write(uintptr_t regadr, uint32_t regval); + +#endif /* BL2_CPG_INIT_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_cpg_register.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_cpg_register.h new file mode 100644 index 0000000..90f5bfb --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_cpg_register.h @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef BL2_CPG_REGISTER_H__ +#define BL2_CPG_REGISTER_H__ + +/* CPG base address */ +#define CPG_BASE (0xE6150000U) + +/* CPG system module stop control 2 */ +#define CPG_SMSTPCR2 (CPG_BASE + 0x0138U) +/* CPG software reset 2 */ +#define CPG_SRCR2 (CPG_BASE + 0x00B0U) +/* CPG module stop status 2 */ +#define CPG_MSTPSR2 (CPG_BASE + 0x0040U) +/* CPG write protect */ +#define CPG_CPGWPR (CPG_BASE + 0x0900U) +/* CPG write protect control */ +#define CPG_CPGWPCR (CPG_BASE + 0x0904U) +/* CPG system module stop control 9 */ +#define CPG_SMSTPCR9 (CPG_BASE + 0x0994U) +/* CPG module stop status 9 */ +#define CPG_MSTPSR9 (CPG_BASE + 0x09A4U) + +/* CPG (SECURITY) registers */ + +/* Secure Module Stop Control Register 0 */ +#define SCMSTPCR0 (CPG_BASE + 0x0B20U) +/* Secure Module Stop Control Register 1 */ +#define SCMSTPCR1 (CPG_BASE + 0x0B24U) +/* Secure Module Stop Control Register 2 */ +#define SCMSTPCR2 (CPG_BASE + 0x0B28U) +/* Secure Module Stop Control Register 3 */ +#define SCMSTPCR3 (CPG_BASE + 0x0B2CU) +/* Secure Module Stop Control Register 4 */ +#define SCMSTPCR4 (CPG_BASE + 0x0B30U) +/* Secure Module Stop Control Register 5 */ +#define SCMSTPCR5 (CPG_BASE + 0x0B34U) +/* Secure Module Stop Control Register 6 */ +#define SCMSTPCR6 (CPG_BASE + 0x0B38U) +/* Secure Module Stop Control Register 7 */ +#define SCMSTPCR7 (CPG_BASE + 0x0B3CU) +/* Secure Module Stop Control Register 8 */ +#define SCMSTPCR8 (CPG_BASE + 0x0B40U) +/* Secure Module Stop Control Register 9 */ +#define SCMSTPCR9 (CPG_BASE + 0x0B44U) +/* Secure Module Stop Control Register 10 */ +#define SCMSTPCR10 (CPG_BASE + 0x0B48U) +/* Secure Module Stop Control Register 11 */ +#define SCMSTPCR11 (CPG_BASE + 0x0B4CU) + +/* CPG (SECURITY) registers */ + +/* Secure Software Reset Access Enable Control Register 0 */ +#define SCSRSTECR0 (CPG_BASE + 0x0B80U) +/* Secure Software Reset Access Enable Control Register 1 */ +#define SCSRSTECR1 (CPG_BASE + 0x0B84U) +/* Secure Software Reset Access Enable Control Register 2 */ +#define SCSRSTECR2 (CPG_BASE + 0x0B88U) +/* Secure Software Reset Access Enable Control Register 3 */ +#define SCSRSTECR3 (CPG_BASE + 0x0B8CU) +/* Secure Software Reset Access Enable Control Register 4 */ +#define SCSRSTECR4 (CPG_BASE + 0x0B90U) +/* Secure Software Reset Access Enable Control Register 5 */ +#define SCSRSTECR5 (CPG_BASE + 0x0B94U) +/* Secure Software Reset Access Enable Control Register 6 */ +#define SCSRSTECR6 (CPG_BASE + 0x0B98U) +/* Secure Software Reset Access Enable Control Register 7 */ +#define SCSRSTECR7 (CPG_BASE + 0x0B9CU) +/* Secure Software Reset Access Enable Control Register 8 */ +#define SCSRSTECR8 (CPG_BASE + 0x0BA0U) +/* Secure Software Reset Access Enable Control Register 9 */ +#define SCSRSTECR9 (CPG_BASE + 0x0BA4U) +/* Secure Software Reset Access Enable Control Register 10 */ +#define SCSRSTECR10 (CPG_BASE + 0x0BA8U) +/* Secure Software Reset Access Enable Control Register 11 */ +#define SCSRSTECR11 (CPG_BASE + 0x0BACU) + +/* CPG (REALTIME) registers */ + +/* Realtime Module Stop Control Register 0 */ +#define RMSTPCR0 (CPG_BASE + 0x0110U) +/* Realtime Module Stop Control Register 1 */ +#define RMSTPCR1 (CPG_BASE + 0x0114U) +/* Realtime Module Stop Control Register 2 */ +#define RMSTPCR2 (CPG_BASE + 0x0118U) +/* Realtime Module Stop Control Register 3 */ +#define RMSTPCR3 (CPG_BASE + 0x011CU) +/* Realtime Module Stop Control Register 4 */ +#define RMSTPCR4 (CPG_BASE + 0x0120U) +/* Realtime Module Stop Control Register 5 */ +#define RMSTPCR5 (CPG_BASE + 0x0124U) +/* Realtime Module Stop Control Register 6 */ +#define RMSTPCR6 (CPG_BASE + 0x0128U) +/* Realtime Module Stop Control Register 7 */ +#define RMSTPCR7 (CPG_BASE + 0x012CU) +/* Realtime Module Stop Control Register 8 */ +#define RMSTPCR8 (CPG_BASE + 0x0980U) +/* Realtime Module Stop Control Register 9 */ +#define RMSTPCR9 (CPG_BASE + 0x0984U) +/* Realtime Module Stop Control Register 10 */ +#define RMSTPCR10 (CPG_BASE + 0x0988U) +/* Realtime Module Stop Control Register 11 */ +#define RMSTPCR11 (CPG_BASE + 0x098CU) + +/* CPG (SYSTEM) registers */ + +/* System Module Stop Control Register 0 */ +#define SMSTPCR0 (CPG_BASE + 0x0130U) +/* System Module Stop Control Register 1 */ +#define SMSTPCR1 (CPG_BASE + 0x0134U) +/* System Module Stop Control Register 2 */ +#define SMSTPCR2 (CPG_BASE + 0x0138U) +/* System Module Stop Control Register 3 */ +#define SMSTPCR3 (CPG_BASE + 0x013CU) +/* System Module Stop Control Register 4 */ +#define SMSTPCR4 (CPG_BASE + 0x0140U) +/* System Module Stop Control Register 5 */ +#define SMSTPCR5 (CPG_BASE + 0x0144U) +/* System Module Stop Control Register 6 */ +#define SMSTPCR6 (CPG_BASE + 0x0148U) +/* System Module Stop Control Register 7 */ +#define SMSTPCR7 (CPG_BASE + 0x014CU) +/* System Module Stop Control Register 8 */ +#define SMSTPCR8 (CPG_BASE + 0x0990U) +/* System Module Stop Control Register 9 */ +#define SMSTPCR9 (CPG_BASE + 0x0994U) +/* System Module Stop Control Register 10 */ +#define SMSTPCR10 (CPG_BASE + 0x0998U) +/* System Module Stop Control Register 11 */ +#define SMSTPCR11 (CPG_BASE + 0x099CU) + +#endif /* BL2_CPG_REGISTER_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_dma_register.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_dma_register.h new file mode 100644 index 0000000..576b584 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_dma_register.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef BL2_DMA_REGISTER_H__ +#define BL2_DMA_REGISTER_H__ + +#define DMACH 16 /* DMA CH setting (0/16/32) */ + +#if (DMACH==0) /* SYS-DMAC0 (CH0) */ +#define SYS_DMAC_BIT ((uint32_t)1U << 19U) +#define DMA_BASE (0xE6700000U) +#elif (DMACH==16) /* SYS-DMAC1 (CH16) */ +#define SYS_DMAC_BIT ((uint32_t)1U << 18U) +#define DMA_BASE (0xE7300000U) +#elif (DMACH==32) /* SYS-DMAC2 (CH32) */ +#define SYS_DMAC_BIT ((uint32_t)1U << 17U) +#define DMA_BASE (0xE7320000U) +#else +#define SYS_DMAC_BIT ((uint32_t)1U << 19U) +#define DMA_BASE (0xE6700000U) +#endif + +/* DMA operation */ +#define DMA_DMAOR (DMA_BASE + 0x0060U) +/* DMA secure control */ +#define DMA_DMASEC (DMA_BASE + 0x0030U) +/* DMA channel clear */ +#define DMA_DMACHCLR (DMA_BASE + 0x0080U) +/* DMA source address */ +#define DMA_DMASAR (DMA_BASE + 0x8000U) +/* DMA destination address */ +#define DMA_DMADAR (DMA_BASE + 0x8004U) +/* DMA transfer count */ +#define DMA_DMATCR (DMA_BASE + 0x8008U) +/* DMA channel control */ +#define DMA_DMACHCR (DMA_BASE + 0x800CU) + +#endif /* BL2_DMA_REGISTER_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_int_error.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_int_error.h new file mode 100644 index 0000000..acabfac --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_int_error.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef BL2_INT_ERROR_H__ +#define BL2_INT_ERROR_H__ + +extern void bl2_swdt_release(void); + +/* int_id : IAR.Interrupt ID */ +void bl2_interrupt_error_id(uint32_t int_id); + +/* ex_type : vector index */ +void bl2_interrupt_error_type(uint32_t ex_type); + +#endif /* BL2_INT_ERROR_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_rpc_register.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_rpc_register.h new file mode 100644 index 0000000..f9d4532 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_rpc_register.h @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef BL2_RPC_REGISTER_H__ +#define BL2_RPC_REGISTER_H__ + +/* RPC base address */ +#define RPC_BASE (0xEE200000U) + +/* RPC common control */ +#define RPC_CMNCR (RPC_BASE + 0x0000U) +/* RPC ssl delay */ +#define RPC_SSLDR (RPC_BASE + 0x0004U) +/* RPC data read control */ +#define RPC_DRCR (RPC_BASE + 0x000CU) +/* RPC data read command setting */ +#define RPC_DRCMR (RPC_BASE + 0x0010U) +/* RPC data read enable setting */ +#define RPC_DRENR (RPC_BASE + 0x001CU) + +/* RPC manual mode control */ +#define RPC_SMCR (RPC_BASE + 0x0020U) +/* RPC manual mode command setting */ +#define RPC_SMCMR (RPC_BASE + 0x0024U) +/* RPC manual mode enable setting */ +#define RPC_SMENR (RPC_BASE + 0x0030U) + +/* RPC common status */ +#define RPC_CMNSR (RPC_BASE + 0x0048U) +/* RPC data read dummy cycle setting */ +#define RPC_DRDMCR (RPC_BASE + 0x0058U) +/* RPC data read ddr enable */ +#define RPC_DRDRENR (RPC_BASE + 0x005CU) + +/* RPC phy control */ +#define RPC_PHYCNT (RPC_BASE + 0x007CU) +/* RPC phy interrupt */ +#define RPC_PHYINT (RPC_BASE + 0x0088U) + +#endif /* BL2_RPC_REGISTER_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_swdt.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_swdt.h new file mode 100644 index 0000000..6332c35 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/bl2_swdt.h @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef BL2_SWDT_H__ +#define BL2_SWDT_H__ + +void bl2_swdt_init(void); + +void bl2_swdt_enable(void); + +void bl2_swdt_release(void); + +void bl2_swdt_exec(uint64_t addr); + +extern void gicd_set_icenabler(uintptr_t base, unsigned int id); + +#endif /* BL2_SWDT_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/dma_driver.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/dma_driver.h new file mode 100644 index 0000000..2c6dedc --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/dma_driver.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DMA_DRIVER_H__ +#define DMA_DRIVER_H__ + +#include + +void initDMA(void); +void execDMA(uintptr_t dst, uint32_t src, uint32_t len); + +#endif /* DMA_DRIVER_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_config.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_config.h new file mode 100644 index 0000000..8519312 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_config.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file emmc_config.h + * @brief Configuration file + * + */ + +#ifndef __EMMC_CONFIG_H__ +#define __EMMC_CONFIG_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/** @brief MMC driver config + */ +#define EMMC_RCA 1UL /* RCA */ +#define EMMC_RW_DATA_TIMEOUT 0x40UL /* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */ +#define EMMC_RETRY_COUNT 0 /* how many times to try after fail. Don't change. */ +#define EMMC_CMD_MAX 60UL /* Don't change. */ + +/** @brief etc + */ +#define LOADIMAGE_FLAGS_DMA_ENABLE 0x00000001UL + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* #ifndef __EMMC_CONFIG_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_def.h new file mode 100644 index 0000000..9b867d3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_def.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file emmc_def.h + * @brief eMMC boot is expecting this header file + * + */ + +#ifndef __EMMC_DEF_H__ +#define __EMMC_DEF_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +#define EMMC_POWER_ON (1U) + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ +extern st_mmc_base mmc_drv_obj; + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/** @brief for assembler program + */ +uint32_t _rom_emmc_finalize (void); + +/** @brief eMMC driver API + */ +EMMC_ERROR_CODE emmc_init(void); +EMMC_ERROR_CODE emmc_terminate(void); +EMMC_ERROR_CODE emmc_memcard_power(uint8_t mode); +EMMC_ERROR_CODE emmc_mount(void); +EMMC_ERROR_CODE emmc_set_request_mmc_clock(uint32_t *freq); +EMMC_ERROR_CODE emmc_send_idle_cmd (uint32_t arg); +EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id); +EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, uint32_t feature_flags); +EMMC_ERROR_CODE emmc_write_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, uint32_t feature_flags); +EMMC_ERROR_CODE emmc_erase_sector(uint32_t *start_address,uint32_t *end_address ); +uint32_t emmc_bit_field (uint8_t *data, uint32_t top, uint32_t bottom); + + +/** @brief interrupt service + */ +uint32_t emmc_interrupt(void); + +/** @brief DMA + */ + + +/** @brief send command API + */ +EMMC_ERROR_CODE emmc_exec_cmd (uint32_t error_mask, uint32_t *response); +void emmc_make_nontrans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg); +void emmc_make_trans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual, + uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode); +EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg); + +/** @brief for error information + */ +void emmc_write_error_info(uint16_t func_no, EMMC_ERROR_CODE error_code); +void emmc_write_error_info_func_no (uint16_t func_no); + +/* ********************************* CODE ********************************** */ + +#endif /* #define __EMMC_DEF_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_hal.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_hal.h new file mode 100644 index 0000000..6731088 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_hal.h @@ -0,0 +1,336 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file emmc_hal.h + * @brief emmc boot driver is expecting this header file + * + */ + +#ifndef __EMMC_HAL_H__ +#define __EMMC_HAL_H__ +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/** @brief memory card error/status types + */ +#define HAL_MEMCARD_OUT_OF_RANGE 0x80000000L +#define HAL_MEMCARD_ADDRESS_ERROR 0x40000000L +#define HAL_MEMCARD_BLOCK_LEN_ERROR 0x20000000L +#define HAL_MEMCARD_ERASE_SEQ_ERROR 0x10000000L +#define HAL_MEMCARD_ERASE_PARAM 0x08000000L +#define HAL_MEMCARD_WP_VIOLATION 0x04000000L +#define HAL_MEMCARD_CARD_IS_LOCKED 0x02000000L +#define HAL_MEMCARD_LOCK_UNLOCK_FAILED 0x01000000L +#define HAL_MEMCARD_COM_CRC_ERROR 0x00800000L +#define HAL_MEMCARD_ILEGAL_COMMAND 0x00400000L +#define HAL_MEMCARD_CARD_ECC_FAILED 0x00200000L +#define HAL_MEMCARD_CC_ERROR 0x00100000L +#define HAL_MEMCARD_ERROR 0x00080000L +#define HAL_MEMCARD_UNDERRUN 0x00040000L +#define HAL_MEMCARD_OVERRUN 0x00020000L +#define HAL_MEMCARD_CIDCSD_OVERWRITE 0x00010000L +#define HAL_MEMCARD_WP_ERASE_SKIP 0x00008000L +#define HAL_MEMCARD_CARD_ECC_DISABLED 0x00004000L +#define HAL_MEMCARD_ERASE_RESET 0x00002000L +#define HAL_MEMCARD_CARD_STATE 0x00001E00L +#define HAL_MEMCARD_CARD_READY_FOR_DATA 0x00000100L +#define HAL_MEMCARD_APP_CMD 0x00000020L +#define HAL_MEMCARD_SWITCH_ERROR 0x00000080L +#define HAL_MEMCARD_AKE_SEQ_ERROR 0x00000008L +#define HAL_MEMCARD_NO_ERRORS 0x00000000L + +/** @brief Memory card response types + */ +#define HAL_MEMCARD_COMMAND_INDEX_MASK 0x0003f + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/** @brief Type of the return value. + */ +typedef enum +{ + HAL_MEMCARD_FAIL = 0U, + HAL_MEMCARD_OK = 1U, + HAL_MEMCARD_DMA_ALLOC_FAIL = 2U, /**< DMA channel allocation failed */ + HAL_MEMCARD_DMA_TRANSFER_FAIL = 3U, /**< DMA transfer failed */ + HAL_MEMCARD_CARD_STATUS_ERROR = 4U, /**< A non-masked error bit was set in the card status */ + HAL_MEMCARD_CMD_TIMEOUT = 5U, /**< Command timeout occurred */ + HAL_MEMCARD_DATA_TIMEOUT = 6U, /**< Data timeout occurred */ + HAL_MEMCARD_CMD_CRC_ERROR = 7U, /**< Command CRC error occurred */ + HAL_MEMCARD_DATA_CRC_ERROR = 8U /**< Data CRC error occurred */ +} HAL_MEMCARD_RETURN; + +/** @brief memory access operation + */ +typedef enum +{ + HAL_MEMCARD_READ = 0U, /**< read */ + HAL_MEMCARD_WRITE = 1U /**< write */ +} HAL_MEMCARD_OPERATION; + +/** @brief Type of data width on memorycard bus + */ +typedef enum +{ + HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U, + HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U, + HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U +} HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */ + +/** @brief Presence of the memory card + */ +typedef enum +{ + HAL_MEMCARD_CARD_IS_IN = 0U, + HAL_MEMCARD_CARD_IS_OUT = 1U +} HAL_MEMCARD_PRESENCE_STATUS; /* presence status of the memory card*/ + +/** @brief mode of data transfer + */ +typedef enum +{ + HAL_MEMCARD_DMA = 0U, + HAL_MEMCARD_NOT_DMA = 1U +} HAL_MEMCARD_DATA_TRANSFER_MODE; + + +/** @brief Memory card response types. + */ +typedef enum hal_memcard_response_type +{ + HAL_MEMCARD_RESPONSE_NONE = 0x00000U, + HAL_MEMCARD_RESPONSE_R1 = 0x00100U, + HAL_MEMCARD_RESPONSE_R1b = 0x00200U, + HAL_MEMCARD_RESPONSE_R2 = 0x00300U, + HAL_MEMCARD_RESPONSE_R3 = 0x00400U, + HAL_MEMCARD_RESPONSE_R4 = 0x00500U, + HAL_MEMCARD_RESPONSE_R5 = 0x00600U, + HAL_MEMCARD_RESPONSE_R6 = 0x00700U, + HAL_MEMCARD_RESPONSE_R7 = 0x00800U, + HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U +} HAL_MEMCARD_RESPONSE_TYPE; + + +/** @brief Memory card command types. + */ +typedef enum hal_memcard_command_type +{ + HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U, + HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U, + HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U, + HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U, + HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U, + HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U +} HAL_MEMCARD_COMMAND_TYPE; + +/** @brief Type of memory card + */ +typedef enum hal_memcard_command_card_type +{ + HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U +} HAL_MEMCARD_COMMAND_CARD_TYPE; + +/** @brief Memory card application command. + */ +typedef enum hal_memcard_command_app_norm +{ + HAL_MEMCARD_COMMAND_NORMAL = 0x00000U, + HAL_MEMCARD_COMMAND_APP = 0x20000U, + HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U +} HAL_MEMCARD_COMMAND_APP_NORM; + + +/** @brief Memory card command codes. + */ +typedef enum +{ +/* class 0 and class 1 */ + CMD0_GO_IDLE_STATE = 0 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD0 */ + CMD1_SEND_OP_COND = 1 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD1 */ + CMD2_ALL_SEND_CID_MMC = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD2 */ + CMD2_ALL_SEND_CID_SD = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD3_SET_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD3 */ + CMD3_SEND_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R6 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD4_SET_DSR = 4 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD4 */ + CMD5_SLEEP_AWAKE = 5 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD5 */ + CMD6_SWITCH = 6 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD6 */ + CMD6_SWITCH_FUNC = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + ACMD6_SET_BUS_WIDTH = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + CMD7_SELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7 */ + CMD7_SELECT_CARD_PROG = 7 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7(from Disconnected State to Programming State) */ + CMD7_DESELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, + CMD8_SEND_EXT_CSD = 8 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD8 */ + CMD8_SEND_IF_COND = 8 | HAL_MEMCARD_RESPONSE_R7 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD9_SEND_CSD = 9 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD9 */ + CMD10_SEND_CID = 10 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD10 */ + CMD11_READ_DAT_UNTIL_STOP = 11 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD11 */ + CMD12_STOP_TRANSMISSION = 12 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 */ + CMD12_STOP_TRANSMISSION_WRITE = 12 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12(R1b : write case) */ + CMD13_SEND_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD13 */ + ACMD13_SD_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + CMD14_BUSTEST_R = 14 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD14 */ + CMD15_GO_INACTIVE_STATE = 15 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD15 */ + +/* class 2 */ + CMD16_SET_BLOCKLEN = 16 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD16 */ + CMD17_READ_SINGLE_BLOCK = 17 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD17 */ + CMD18_READ_MULTIPLE_BLOCK = 18 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD18 */ + CMD19_BUS_TEST_W = 19 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD19 */ + +/* class 3 */ + CMD20_WRITE_DAT_UNTIL_STOP = 20 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD20 */ + CMD21 = 21, /* CMD21 */ + CMD22 = 22, /* CMD22 */ + ACMD22_SEND_NUM_WR_BLOCKS = 22 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + +/* class 4 */ + CMD23_SET_BLOCK_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD23 */ + ACMD23_SET_WR_BLK_ERASE_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + CMD24_WRITE_BLOCK = 24 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD24 */ + CMD25_WRITE_MULTIPLE_BLOCK = 25 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD25 */ + CMD26_PROGRAM_CID = 26 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD26 */ + CMD27_PROGRAM_CSD = 27 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD27 */ + +/* class 6 */ + CMD28_SET_WRITE_PROT = 28 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD28 */ + CMD29_CLR_WRITE_PROT = 29 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD29 */ + CMD30_SEND_WRITE_PROT = 30 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD30 */ + CMD30_SEND_WRITE_PROT_TYPE = 31 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD31 */ + +/* class 5 */ + CMD32_ERASE_WR_BLK_START = 32 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD32 */ + CMD33_ERASE_WR_BLK_END = 33 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD33 */ + CMD34 = 34, /* CMD34 */ + CMD35_ERASE_GROUP_START = 35 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD35 */ + CMD36_ERASE_GROUP_END = 36 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD36 */ + CMD37 = 37, /* CMD37 */ + CMD38_ERASE = 38 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD38 */ + +/* class 9 */ + CMD39_FASTIO = 39 | HAL_MEMCARD_RESPONSE_R4 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD39 */ + CMD40_GO_IRQSTATE = 40 | HAL_MEMCARD_RESPONSE_R5 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD40 */ + CMD41 = 41, /* CMD41 */ + ACMD41_SD_SEND_OP_COND = 41 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + +/* class 7 */ + CMD42_LOCK_UNLOCK = 42 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD42 */ + ACMD42_SET_CLR_CARD_DETECT = 42 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + CMD43 = 43, /* CMD43 */ + CMD44 = 44, /* CMD44 */ + CMD45 = 45, /* CMD45 */ + CMD46 = 46, /* CMD46 */ + CMD47 = 47, /* CMD47 */ + CMD48 = 48, /* CMD48 */ + CMD49 = 49, /* CMD49 */ + CMD50 = 50, /* CMD50 */ + CMD51 = 51, /* CMD51 */ + ACMD51_SEND_SCR = 51 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + CMD52 = 52, /* CMD52 */ + CMD53 = 53, /* CMD53 */ + CMD54 = 54, /* CMD54 */ + +/* class 8 */ + CMD55_APP_CMD = 55 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD55 */ + CMD56_GEN_CMD = 56 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD56 */ + CMD57 = 57, /* CMD57 */ + CMD58 = 58, /* CMD58 */ + CMD59 = 59, /* CMD59 */ + CMD60 = 60, /* CMD60 */ + CMD61 = 61, /* CMD61 */ + CMD62 = 62, /* CMD62 */ + CMD63 = 63 /* CMD63 */ +} HAL_MEMCARD_COMMAND; + + +/** @brief Configuration structure from HAL layer. + * + * If some field is not available it should be filled with 0xFF. + * The API version is 32-bit unsigned integer telling the version of the API. The integer is divided to four sections which each can be treated as a 8-bit unsigned number: + * Bits 31-24 make the most significant part of the version number. This number starts from 1 i.e. the second version of the API will be 0x02xxxxxx. This number changes only, if the API itself changes so much that it is not compatible anymore with older releases. + * Bits 23-16 API minor version number. For example API version 2.1 would be 0x0201xxxx. + * Bits 15-8 are the number of the year when release is done. The 0 is year 2000, 1 is year 2001 and so on + * Bits 7- are the week number when release is done. First full week of the year is 1 + * + * @note Example: let's assume that release 2.1 is done on week 10 year 2008 the version will get the value 0x0201080A + */ +typedef struct +{ + /** + * Version of the chipset API implementation + * + * bits [31:24] API specification major version number.
+ * bits [23:16] API specification minor version number.
+ * bits [15:8] API implemention year. (2000 = 0, 2001 = 1, ...)
+ * bits [7:0] API implemention week.
+ * Example: API specification version 4.0, implementation w46 2008 => 0x0400082E + */ + uint32_t api_version; + + /** maximum block count which can be transferred at once */ + uint32_t max_block_count; + + /** maximum clock frequence in Hz supported by HW */ + uint32_t max_clock_freq; + + /** maximum data bus width supported by HW */ + uint16_t max_data_width; + + /** Is high-speed mode supported by HW (yes=1, no=0) */ + uint8_t hs_mode_supported; + + /** Is memory card removable (yes=1, no=0) */ + uint8_t card_removable; + +} HAL_MEMCARD_HW_CONF; + +/** @brief Configuration structure to HAL layer. + */ +typedef struct +{ + /** how many times to try after fail, for instance sending command */ + uint32_t retries_after_fail; +} HAL_MEMCARD_INIT_CONF; + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* __EMMC_HAL_H__ */ + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_registers.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_registers.h new file mode 100644 index 0000000..b18f498 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_registers.h @@ -0,0 +1,275 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file emmc_registers.h + * @brief emmc boot driver is expecting this header file. HS-MMC module header file. + * + */ + +#ifndef __EMMC_REGISTERS_H__ +#define __EMMC_REGISTERS_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +#define BIT0 (0x00000001U) +#define BIT1 (0x00000002U) +#define BIT2 (0x00000004U) +#define BIT3 (0x00000008U) +#define BIT4 (0x00000010U) +#define BIT5 (0x00000020U) +#define BIT6 (0x00000040U) +#define BIT7 (0x00000080U) +#define BIT8 (0x00000100U) +#define BIT9 (0x00000200U) +#define BIT10 (0x00000400U) +#define BIT11 (0x00000800U) +#define BIT12 (0x00001000U) +#define BIT13 (0x00002000U) +#define BIT14 (0x00004000U) +#define BIT15 (0x00008000U) +#define BIT16 (0x00010000U) +#define BIT17 (0x00020000U) +#define BIT18 (0x00040000U) +#define BIT19 (0x00080000U) +#define BIT20 (0x00100000U) +#define BIT21 (0x00200000U) +#define BIT22 (0x00400000U) +#define BIT23 (0x00800000U) +#define BIT24 (0x01000000U) +#define BIT25 (0x02000000U) +#define BIT26 (0x04000000U) +#define BIT27 (0x08000000U) +#define BIT28 (0x10000000U) +#define BIT29 (0x20000000U) +#define BIT30 (0x40000000U) +#define BIT31 (0x80000000U) + +/** @brief LIFEC0 (SECURITY) registers + */ +#define LIFEC_SEC_BASE (0xE6110000U) +/* Security group 0 attribute setting for master ports 3 */ +#define SEC_GRP0CR3 (LIFEC_SEC_BASE + 0x0150U) +/* Security group 1 attribute setting for master ports 3 */ +#define SEC_GRP1CR3 (LIFEC_SEC_BASE + 0x0154U) + + +/** @brief Clock Pulse Generator (CPG) registers + */ +#define CPG_BASE (0xE6150000U) + +#define CPG_MSTPSR3 (CPG_BASE+0x0048U) // Module stop status register 3 +#define CPG_MSTPSR7 (CPG_BASE+0x01C4U) // Module stop status register 7 + +#define CPG_SMSTPCR3 (CPG_BASE+0x013CU) // System module stop control register 3 +#define CPG_SMSTPCR7 (CPG_BASE+0x014CU) // System module stop control register 7 + +#define CPG_SD2CKCR (CPG_BASE+0x0268U) // SDHI2 clock frequency control register + +#define CPG_CPGWPR (CPG_BASE+0x0900U) // CPG Write Protect Register + + +/** Boot Status register + */ +#define MFISBTSTSR (0xE6260604U) + +#define MFISBTSTSR_BOOT_PARTITION (0x00000010U) + + +/** brief eMMC(SDHI2/MMC0) registers + */ +#define MMC0_SD_BASE (0xEE140000U) +#define SD_CMD (MMC0_SD_BASE + 0x0000U) +#define SD_PORTSEL (MMC0_SD_BASE + 0x0008U) +#define SD_ARG (MMC0_SD_BASE + 0x0010U) +#define SD_ARG1 (MMC0_SD_BASE + 0x0018U) +#define SD_STOP (MMC0_SD_BASE + 0x0020U) +#define SD_SECCNT (MMC0_SD_BASE + 0x0028U) +#define SD_RSP10 (MMC0_SD_BASE + 0x0030U) +#define SD_RSP1 (MMC0_SD_BASE + 0x0038U) +#define SD_RSP32 (MMC0_SD_BASE + 0x0040U) +#define SD_RSP3 (MMC0_SD_BASE + 0x0048U) +#define SD_RSP54 (MMC0_SD_BASE + 0x0050U) +#define SD_RSP5 (MMC0_SD_BASE + 0x0058U) +#define SD_RSP76 (MMC0_SD_BASE + 0x0060U) +#define SD_RSP7 (MMC0_SD_BASE + 0x0068U) +#define SD_INFO1 (MMC0_SD_BASE + 0x0070U) +#define SD_INFO2 (MMC0_SD_BASE + 0x0078U) +#define SD_INFO1_MASK (MMC0_SD_BASE + 0x0080U) +#define SD_INFO2_MASK (MMC0_SD_BASE + 0x0088U) +#define SD_CLK_CTRL (MMC0_SD_BASE + 0x0090U) +#define SD_SIZE (MMC0_SD_BASE + 0x0098U) +#define SD_OPTION (MMC0_SD_BASE + 0x00A0U) +#define SD_ERR_STS1 (MMC0_SD_BASE + 0x00B0U) +#define SD_ERR_STS2 (MMC0_SD_BASE + 0x00B8U) +#define SD_BUF0 (MMC0_SD_BASE + 0x00C0U) +#define SDIO_MODE (MMC0_SD_BASE + 0x00D0U) +#define SDIO_INFO1 (MMC0_SD_BASE + 0x00D8U) +#define SDIO_INFO1_MASK (MMC0_SD_BASE + 0x00E0U) +#define CC_EXT_MODE (MMC0_SD_BASE + 0x0360U) +#define SOFT_RST (MMC0_SD_BASE + 0x0380U) +#define VERSION (MMC0_SD_BASE + 0x0388U) +#define HOST_MODE (MMC0_SD_BASE + 0x0390U) +#define DM_CM_DTRAN_MODE (MMC0_SD_BASE + 0x0820U) +#define DM_CM_DTRAN_CTRL (MMC0_SD_BASE + 0x0828U) +#define DM_CM_RST (MMC0_SD_BASE + 0x0830U) +#define DM_CM_INFO1 (MMC0_SD_BASE + 0x0840U) +#define DM_CM_INFO1_MASK (MMC0_SD_BASE + 0x0848U) +#define DM_CM_INFO2 (MMC0_SD_BASE + 0x0850U) +#define DM_CM_INFO2_MASK (MMC0_SD_BASE + 0x0858U) +#define DM_DTRAN_ADDR (MMC0_SD_BASE + 0x0880U) + + + +/** @brief SD_INFO1 Registers + */ +#define SD_INFO1_HPIRES 0x00010000UL /* Response Reception Completion */ +#define SD_INFO1_INFO10 0x00000400UL /* Indicates the SDDAT3 state */ +#define SD_INFO1_INFO9 0x00000200UL /* SDDAT3 Card Insertion */ +#define SD_INFO1_INFO8 0x00000100UL /* SDDAT3 Card Removal */ +#define SD_INFO1_INFO7 0x00000080UL /* Write Protect */ +#define SD_INFO1_INFO5 0x00000020UL /* Indicates the ISDCD state */ +#define SD_INFO1_INFO4 0x00000010UL /* ISDCD Card Insertion */ +#define SD_INFO1_INFO3 0x00000008UL /* ISDCD Card Removal */ +#define SD_INFO1_INFO2 0x00000004UL /* Access end */ +#define SD_INFO1_INFO0 0x00000001UL /* Response end */ + +/** @brief SD_INFO2 Registers + */ +#define SD_INFO2_ILA 0x00008000UL /* Illegal Access Error */ +#define SD_INFO2_CBSY 0x00004000UL /* Command Type Register Busy */ +#define SD_INFO2_SCLKDIVEN 0x00002000UL +#define SD_INFO2_BWE 0x00000200UL /* SD_BUF Write Enable */ +#define SD_INFO2_BRE 0x00000100UL /* SD_BUF Read Enable */ +#define SD_INFO2_DAT0 0x00000080UL /* SDDAT0 */ +#define SD_INFO2_ERR6 0x00000040UL /* Response Timeout */ +#define SD_INFO2_ERR5 0x00000020UL /* SD_BUF Illegal Read Access */ +#define SD_INFO2_ERR4 0x00000010UL /* SD_BUF Illegal Write Access */ +#define SD_INFO2_ERR3 0x00000008UL /* Data Timeout */ +#define SD_INFO2_ERR2 0x00000004UL /* END Error */ +#define SD_INFO2_ERR1 0x00000002UL /* CRC Error */ +#define SD_INFO2_ERR0 0x00000001UL /* CMD Error */ +#define SD_INFO2_ALL_ERR 0x0000807FUL +#define SD_INFO2_CLEAR 0x00000800UL /* BIT11 The write value should always be 1. HWM_0003 */ + +/** @brief SOFT_RST + */ +#define SOFT_RST_SDRST 0x00000001UL + +/** @brief SD_CLK_CTRL + */ +#define SD_CLK_CTRL_SDCLKOFFEN 0x00000200UL +#define SD_CLK_CTRL_SCLKEN 0x00000100UL +#define SD_CLK_CTRL_CLKDIV_MASK 0x000000FFUL +#define SD_CLOCK_ENABLE 0x00000100UL +#define SD_CLOCK_DISABLE 0x00000000UL +#define SD_CLK_WRITE_MASK 0x000003FFUL +#define SD_CLK_CLKDIV_CLEAR_MASK 0xFFFFFF0FUL + +/** @brief SD_OPTION + */ +#define SD_OPTION_TIMEOUT_CNT_MASK 0x000000F0UL + + +/** @brief MMC Clock Frequency + * 200MHz * 1/x = output clock + */ +#define MMC_CLK_OFF 0UL /* Clock output is disabled */ +#define MMC_400KHZ 512UL /* 200MHz * 1/512 = 390 KHz */ +#define MMC_20MHZ 16UL /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */ +#define MMC_26MHZ 8UL /* 200MHz * 1/8 = 25 MHz High speed mode 26Mhz */ +#define MMC_52MHZ 4UL /* 200MHz * 1/4 = 50 MHz High speed mode 52Mhz */ +#define MMC_100MHZ 2UL /* 200MHz * 1/2 = 100 MHz */ +#define MMC_200MHZ 1UL /* 200MHz * 1/1 = 200 MHz */ + + +#define MMC_FREQ_52MHZ 52000000UL +#define MMC_FREQ_26MHZ 26000000UL +#define MMC_FREQ_20MHZ 20000000UL + + +/** @brief MMC Clock DIV + */ +#define MMC_SD_CLK_START 0x00000100UL /* CLOCK On */ +#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */ +#define MMC_SD_CLK_DIV1 0x000000FFUL /* 1/1 */ +#define MMC_SD_CLK_DIV2 0x00000000UL /* 1/2 */ +#define MMC_SD_CLK_DIV4 0x00000001UL /* 1/4 */ +#define MMC_SD_CLK_DIV8 0x00000002UL /* 1/8 */ +#define MMC_SD_CLK_DIV16 0x00000004UL /* 1/16 */ +#define MMC_SD_CLK_DIV32 0x00000008UL /* 1/32 */ +#define MMC_SD_CLK_DIV64 0x00000010UL /* 1/64 */ +#define MMC_SD_CLK_DIV128 0x00000020UL /* 1/128 */ +#define MMC_SD_CLK_DIV256 0x00000040UL /* 1/256 */ +#define MMC_SD_CLK_DIV512 0x00000080UL /* 1/512 */ + +/** @brief DM_CM_DTRAN_MODE + */ +#define DM_CM_DTRAN_MODE_CH0 0x00000000UL /* CH0(downstream) */ +#define DM_CM_DTRAN_MODE_CH1 0x00010000UL /* CH1(upstream) */ +#define DM_CM_DTRAN_MODE_BIT_WIDTH 0x00000030UL + +/** @brief CC_EXT_MODE + */ +#define CC_EXT_MODE_DMASDRW_ENABLE 0x00000002UL /* SD_BUF Read/Write DMA Transfer */ +#define CC_EXT_MODE_CLEAR 0x00001010UL /* BIT 12 & 4 always 1. */ + +/** @brief DM_CM_INFO_MASK + */ +#define DM_CM_INFO_MASK_CLEAR 0xFFFCFFFEUL +#define DM_CM_INFO_CH0_ENABLE 0x00010001UL +#define DM_CM_INFO_CH1_ENABLE 0x00020001UL + +/** @brief DM_DTRAN_ADDR + */ +#define DM_DTRAN_ADDR_WRITE_MASK 0xFFFFFFF8UL + +/** @brief DM_CM_DTRAN_CTRL + */ +#define DM_CM_DTRAN_CTRL_START 0x00000001UL + +/** @brief SYSC Registers + */ +#define CPG_MSTP_MMC (0x00001000U) + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* __EMMC_REGISTERS_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_std.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_std.h new file mode 100644 index 0000000..6b57124 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/emmc_std.h @@ -0,0 +1,504 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/** + * @file emmc_std.h + * @brief eMMC boot is expecting this header file + * + */ + +#ifndef __EMMC_STD_H__ +#define __EMMC_STD_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +#ifndef FALSE +#define FALSE 0U +#endif +#ifndef TRUE +#define TRUE 1U +#endif + +/** @brief 64bit registers + **/ +#define SETR_64(r, v) (*(volatile uint64_t *)(r) = (v)) +#define GETR_64(r) (*(volatile uint64_t *)(r)) + +/** @brief 32bit registers + **/ +#define SETR_32(r, v) (*(volatile uint32_t *)(r) = (v)) +#define GETR_32(r) (*(volatile uint32_t *)(r)) + +/** @brief 16bit registers + */ +#define SETR_16(r, v) (*(volatile uint16_t *)(r) = (v)) +#define GETR_16(r) (*(volatile uint16_t *)(r)) + +/** @brief 8bit registers + */ +#define SETR_8(r, v) (*(volatile uint8_t *)(r) = (v)) +#define GETR_8(r) (*(volatile uint8_t *)(r)) + +/** @brief CSD register Macros + */ +#define EMMC_GET_CID(x,y) (emmc_bit_field(mmc_drv_obj.cid_data, (x), (y))) + +#if 0 +#define EMMC_CID_MID() (EMMC_GET_CID(127,120)) +#define EMMC_CID_CBX() (EMMC_GET_CID(113,112)) +#define EMMC_CID_OID() (EMMC_GET_CID(111,104)) +#define EMMC_CID_PNM1() (EMMC_GET_CID(103,88)) +#define EMMC_CID_PNM2() (EMMC_GET_CID(87,56)) +#define EMMC_CID_PRV() (EMMC_GET_CID(55,48)) +#define EMMC_CID_PSN() (EMMC_GET_CID(47,16)) +#define EMMC_CID_MDT() (EMMC_GET_CID(15,8)) +#define EMMC_CID_CRC() (EMMC_GET_CID(7,1)) +#endif + + +/** @brief CSD register Macros + */ +#define EMMC_GET_CSD(x,y) (emmc_bit_field(mmc_drv_obj.csd_data, (x), (y))) +#define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125,122)) +#define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103,96)) + +#if 0 +#define EMMC_CSD_CSD_STRUCTURE() (EMMC_GET_CSD(127,126)) +#define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125,122)) +#define EMMC_CSD_TAAC() (EMMC_GET_CSD(119,112)) +#define EMMC_CSD_NSAC() (EMMC_GET_CSD(111,104)) +#define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103,96)) +#define EMMC_CSD_CCC() (EMMC_GET_CSD(95,84)) +#define EMMC_CSD_READ_BL_LEN() (EMMC_GET_CSD(83,80)) +#define EMMC_CSD_READ_BL_PARTIAL() (EMMC_GET_CSD(79,79)) +#define EMMC_CSD_WRITE_BLK_MISALIGN() (EMMC_GET_CSD(78,78)) +#define EMMC_CSD_READ_BLK_MISALIGN() (EMMC_GET_CSD(77,77)) +#define EMMC_CSD_DSR_IMP() (EMMC_GET_CSD(76,76)) +#define EMMC_CSD_C_SIZE() (EMMC_GET_CSD(73,62)) +#define EMMC_CSD_VDD_R_CURR_MIN() (EMMC_GET_CSD(61,59)) +#define EMMC_CSD_VDD_R_CURR_MAX() (EMMC_GET_CSD(58,56)) +#define EMMC_CSD_VDD_W_CURR_MIN() (EMMC_GET_CSD(55,53)) +#define EMMC_CSD_VDD_W_CURR_MAX() (EMMC_GET_CSD(52,50)) +#define EMMC_CSD_C_SIZE_MULT() (EMMC_GET_CSD(49,47)) +#define EMMC_CSD_ERASE_GRP_SIZE() (EMMC_GET_CSD(46,42)) +#define EMMC_CSD_ERASE_GRP_MULT() (EMMC_GET_CSD(41,37)) +#define EMMC_CSD_WP_GRP_SIZE() (EMMC_GET_CSD(36,32)) +#define EMMC_CSD_WP_GRP_ENABLE() (EMMC_GET_CSD(31,31)) +#define EMMC_CSD_DEFALT_ECC() (EMMC_GET_CSD(30,29)) +#define EMMC_CSD_R2W_FACTOR() (EMMC_GET_CSD(28,26)) +#define EMMC_CSD_WRITE_BL_LEN() (EMMC_GET_CSD(25,22)) +#define EMMC_CSD_WRITE_BL_PARTIAL() (EMMC_GET_CSD(21,21)) +#define EMMC_CSD_CONTENT_PROT_APP() (EMMC_GET_CSD(16,16)) +#define EMMC_CSD_FILE_FORMAT_GRP() (EMMC_GET_CSD(15,15)) +#define EMMC_CSD_COPY() (EMMC_GET_CSD(14,14)) +#define EMMC_CSD_PERM_WRITE_PROTECT() (EMMC_GET_CSD(13,13)) +#define EMMC_CSD_TMP_WRITE_PROTECT() (EMMC_GET_CSD(12,12)) +#define EMMC_CSD_FILE_FORMAT() (EMMC_GET_CSD(11,10)) +#define EMMC_CSD_ECC() (EMMC_GET_CSD(9,8)) +#define EMMC_CSD_CRC() (EMMC_GET_CSD(7,1)) +#endif + +/** @brief for sector access + */ +#define EMMC_4B_BOUNDARY_CHECK_MASK 0x00000003 /* 4Bytes boundary check mask */ +#define EMMC_SECTOR_SIZE_SHIFT 9 /* 512 = 2^9 */ +#define EMMC_SECTOR_SIZE 512 +#define EMMC_BLOCK_LENGTH 512 +#define EMMC_BLOCK_LENGTH_DW 128 + +/** @brief eMMC specification clock + */ +#define EMMC_CLOCK_SPEC_400K 400000UL /**< initialize clock 400KHz */ +#define EMMC_CLOCK_SPEC_20M 20000000UL /**< normal speed 20MHz */ +#define EMMC_CLOCK_SPEC_26M 26000000UL /**< high speed 26MHz */ +#define EMMC_CLOCK_SPEC_52M 52000000UL /**< high speed 52MHz */ +#define EMMC_CLOCK_SPEC_100M 100000000UL /**< high speed 100MHz */ + +/** @brief EMMC driver error code. (extended HAL_MEMCARD_RETURN) + */ +typedef enum +{ + EMMC_ERR = 0, /**< unknown error */ + EMMC_SUCCESS , /**< OK */ + EMMC_ERR_FROM_DMAC , /**< DMAC allocation error */ + EMMC_ERR_FROM_DMAC_TRANSFER , /**< DMAC transfer error */ + EMMC_ERR_CARD_STATUS_BIT , /**< card status error. Non-masked error bit was set in the card status */ + EMMC_ERR_CMD_TIMEOUT , /**< command timeout error */ + EMMC_ERR_DATA_TIMEOUT , /**< data timeout error */ + EMMC_ERR_CMD_CRC , /**< command CRC error */ + EMMC_ERR_DATA_CRC , /**< data CRC error */ + EMMC_ERR_PARAM , /**< parameter error */ + EMMC_ERR_RESPONSE , /**< response error */ + EMMC_ERR_RESPONSE_BUSY , /**< response busy error */ + EMMC_ERR_TRANSFER , /**< data transfer error */ + EMMC_ERR_READ_SECTOR , /**< read sector error */ + EMMC_ERR_WRITE_SECTOR , /**< write sector error */ + EMMC_ERR_STATE , /**< state error */ + EMMC_ERR_TIMEOUT , /**< timeout error */ + EMMC_ERR_ILLEGAL_CARD , /**< illegal card */ + EMMC_ERR_CARD_BUSY , /**< Busy state */ + EMMC_ERR_CARD_STATE , /**< card state error */ + EMMC_ERR_SET_TRACE , /**< trace information error */ + EMMC_ERR_FROM_TIMER , /**< Timer error */ + EMMC_ERR_FORCE_TERMINATE , /**< Force terminate */ + EMMC_ERR_CARD_POWER , /**< card power fail */ + EMMC_ERR_ERASE_SECTOR , /**< erase sector error */ + EMMC_ERR_INFO2 /**< exec cmd error info2 */ +} EMMC_ERROR_CODE; + +/** @brief Function number */ +#define EMMC_FUNCNO_NONE 0U +#define EMMC_FUNCNO_DRIVER_INIT 1U +#define EMMC_FUNCNO_CARD_POWER_ON 2U +#define EMMC_FUNCNO_MOUNT 3U +#define EMMC_FUNCNO_CARD_INIT 4U +#define EMMC_FUNCNO_HIGH_SPEED 5U +#define EMMC_FUNCNO_BUS_WIDTH 6U +#define EMMC_FUNCNO_MULTI_BOOT_SELECT_PARTITION 7U +#define EMMC_FUNCNO_MULTI_BOOT_READ_SECTOR 8U +#define EMMC_FUNCNO_TRANS_DATA_READ_SECTOR 9U +#define EMMC_FUNCNO_UBOOT_IMAGE_SELECT_PARTITION 10U +#define EMMC_FUNCNO_UBOOT_IMAGE_READ_SECTOR 11U +#define EMMC_FUNCNO_SET_CLOCK 12U +#define EMMC_FUNCNO_EXEC_CMD 13U +#define EMMC_FUNCNO_READ_SECTOR 14U +#define EMMC_FUNCNO_WRITE_SECTOR 15U +#define EMMC_FUNCNO_ERASE_SECTOR 16U +#define EMMC_FUNCNO_GET_PERTITION_ACCESS 17U +/** @brief Response + */ +/** R1 */ +#define EMMC_R1_ERROR_MASK 0xFDBFE080U /* Type 'E' bit and bit14(must be 0). ignore bit22 */ +#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) /* Ignore bit23 (Not check CRC error) */ +#define EMMC_R1_STATE_MASK 0x00001E00U /* [12:9] */ +#define EMMC_R1_READY 0x00000100U /* bit8 */ +#define EMMC_R1_STATE_SHIFT 9 + +/** R4 */ +#define EMMC_R4_RCA_MASK 0xFFFF0000UL +#define EMMC_R4_STATUS 0x00008000UL + +/** CSD */ +#define EMMC_TRANSPEED_FREQ_UNIT_MASK 0x07 /* bit[2:0] */ +#define EMMC_TRANSPEED_FREQ_UNIT_SHIFT 0 +#define EMMC_TRANSPEED_MULT_MASK 0x78 /* bit[6:3] */ +#define EMMC_TRANSPEED_MULT_SHIFT 3 + +/** OCR */ +#define EMMC_HOST_OCR_VALUE 0x40FF8080 +#define EMMC_OCR_STATUS_BIT 0x80000000L /* Card power up status bit */ +#define EMMC_OCR_ACCESS_MODE_MASK 0x60000000L /* bit[30:29] */ +#define EMMC_OCR_ACCESS_MODE_SECT 0x40000000L +#define EMMC_OCR_ACCESS_MODE_BYTE 0x00000000L + +/** EXT_CSD */ +#define EMMC_EXT_CSD_S_CMD_SET 504 +#define EMMC_EXT_CSD_INI_TIMEOUT_AP 241 +#define EMMC_EXT_CSD_PWR_CL_DDR_52_360 239 +#define EMMC_EXT_CSD_PWR_CL_DDR_52_195 238 +#define EMMC_EXT_CSD_MIN_PERF_DDR_W_8_52 235 +#define EMMC_EXT_CSD_MIN_PERF_DDR_R_8_52 234 +#define EMMC_EXT_CSD_TRIM_MULT 232 +#define EMMC_EXT_CSD_SEC_FEATURE_SUPPORT 231 +#define EMMC_EXT_CSD_SEC_ERASE_MULT 229 +#define EMMC_EXT_CSD_BOOT_INFO 228 +#define EMMC_EXT_CSD_BOOT_SIZE_MULTI 226 +#define EMMC_EXT_CSD_ACC_SIZE 225 +#define EMMC_EXT_CSD_HC_ERASE_GRP_SIZE 224 +#define EMMC_EXT_CSD_ERASE_TIMEOUT_MULT 223 +#define EMMC_EXT_CSD_PEL_WR_SEC_C 222 +#define EMMC_EXT_CSD_HC_WP_GRP_SIZE 221 +#define EMMC_EXT_CSD_S_C_VCC 220 +#define EMMC_EXT_CSD_S_C_VCCQ 219 +#define EMMC_EXT_CSD_S_A_TIMEOUT 217 +#define EMMC_EXT_CSD_SEC_COUNT 215 +#define EMMC_EXT_CSD_MIN_PERF_W_8_52 210 +#define EMMC_EXT_CSD_MIN_PERF_R_8_52 209 +#define EMMC_EXT_CSD_MIN_PERF_W_8_26_4_52 208 +#define EMMC_EXT_CSD_MIN_PERF_R_8_26_4_52 207 +#define EMMC_EXT_CSD_MIN_PERF_W_4_26 206 +#define EMMC_EXT_CSD_MIN_PERF_R_4_26 205 +#define EMMC_EXT_CSD_PWR_CL_26_360 203 +#define EMMC_EXT_CSD_PWR_CL_52_360 202 +#define EMMC_EXT_CSD_PWR_CL_26_195 201 +#define EMMC_EXT_CSD_PWR_CL_52_195 200 +#define EMMC_EXT_CSD_CARD_TYPE 196 +#define EMMC_EXT_CSD_CSD_STRUCTURE 194 +#define EMMC_EXT_CSD_EXT_CSD_REV 192 +#define EMMC_EXT_CSD_CMD_SET 191 +#define EMMC_EXT_CSD_CMD_SET_REV 189 +#define EMMC_EXT_CSD_POWER_CLASS 187 +#define EMMC_EXT_CSD_HS_TIMING 185 +#define EMMC_EXT_CSD_BUS_WIDTH 183 +#define EMMC_EXT_CSD_ERASED_MEM_CONT 181 +#define EMMC_EXT_CSD_PARTITION_CONFIG 179 +#define EMMC_EXT_CSD_BOOT_CONFIG_PROT 178 +#define EMMC_EXT_CSD_BOOT_BUS_WIDTH 177 +#define EMMC_EXT_CSD_ERASE_GROUP_DEF 175 +#define EMMC_EXT_CSD_BOOT_WP 173 +#define EMMC_EXT_CSD_USER_WP 171 +#define EMMC_EXT_CSD_FW_CONFIG 169 +#define EMMC_EXT_CSD_RPMB_SIZE_MULT 168 +#define EMMC_EXT_CSD_RST_n_FUNCTION 162 +#define EMMC_EXT_CSD_PARTITIONING_SUPPORT 160 +#define EMMC_EXT_CSD_MAX_ENH_SIZE_MULT 159 +#define EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE 156 +#define EMMC_EXT_CSD_PARTITION_SETTING_COMPLETED 155 +#define EMMC_EXT_CSD_GP_SIZE_MULT 154 +#define EMMC_EXT_CSD_ENH_SIZE_MULT 142 +#define EMMC_EXT_CSD_ENH_START_ADDR 139 +#define EMMC_EXT_CSD_SEC_BAD_BLK_MGMNT 134 + +#define EMMC_EXT_CSD_CARD_TYPE_26MHZ 0x01 +#define EMMC_EXT_CSD_CARD_TYPE_52MHZ 0x02 +#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_12V 0x04 +#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_18V 0x08 +#define EMMC_EXT_CSD_CARD_TYPE_52MHZ_MASK 0x0e + +/** SWITCH (CMD6) argument */ +#define EXTCSD_ACCESS_BYTE (BIT25|BIT24) +#define EXTCSD_SET_BITS BIT24 + +#define HS_TIMING_ADD (185<<16) /* H'b9 */ +#define HS_TIMING_1 (1<<8) +#define HS_TIMING_HS200 (2<<8) +#define HS_TIMING_HS400 (3<<8) + +#define BUS_WIDTH_ADD (183<<16) /* H'b7 */ +#define BUS_WIDTH_1 (0<<8) +#define BUS_WIDTH_4 (1<<8) +#define BUS_WIDTH_8 (2<<8) +#define BUS_WIDTH_4DDR (5<<8) +#define BUS_WIDTH_8DDR (6<<8) + +#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1) /**< H'03b90100 */ +#define EMMC_SWITCH_HS_TIMING_OFF (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD) /**< H'03b90000 */ + +#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1) /**< H'03b70000 */ +#define EMMC_SWITCH_BUS_WIDTH_4 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4) /**< H'03b70100 */ +#define EMMC_SWITCH_BUS_WIDTH_8 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8) /**< H'03b70200 */ +#define EMMC_SWITCH_BUS_WIDTH_4DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4DDR) /**< H'03b70500 */ +#define EMMC_SWITCH_BUS_WIDTH_8DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8DDR) /**< H'03b70600 */ +#define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL /**< Partition config = 0x00 */ + +#define TIMING_HIGH_SPEED 1UL +#define EMMC_BOOT_PARTITION_EN_MASK 0x38U +#define EMMC_BOOT_PARTITION_EN_SHIFT 3U + +/** Bus width */ +#define EMMC_BUSWIDTH_1BIT CE_CMD_SET_DATW_1BIT +#define EMMC_BUSWIDTH_4BIT CE_CMD_SET_DATW_4BIT +#define EMMC_BUSWIDTH_8BIT CE_CMD_SET_DATW_8BIT + +/** for st_mmc_base */ +#define EMMC_MAX_RESPONSE_LENGTH 17 +#define EMMC_MAX_CID_LENGTH 16 +#define EMMC_MAX_CSD_LENGTH 16 +#define EMMC_MAX_EXT_CSD_LENGTH 512U +#define EMMC_RES_REG_ALIGNED 4U +#define EMMC_BUF_REG_ALIGNED 8U + +/** @brief for TAAC mask + */ +#define TAAC_TIME_UNIT_MASK (0x07) +#define TAAC_MULTIPLIER_FACTOR_MASK (0x0F) + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/** @brief Partition id + */ +typedef enum +{ + PARTITION_ID_USER = 0x0, /**< User Area */ + PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */ + PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */ + PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */ + PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */ + PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */ + PARTITION_ID_GP_3 = 0x6, /**< General Purpose partition 3 */ + PARTITION_ID_GP_4 = 0x7, /**< General Purpose partition 4 */ + PARTITION_ID_MASK = 0x7 /**< [2:0] */ +} EMMC_PARTITION_ID; + +/** @brief card state in R1 response [12:9] + */ +typedef enum +{ + EMMC_R1_STATE_IDLE = 0, + EMMC_R1_STATE_READY, + EMMC_R1_STATE_IDENT, + EMMC_R1_STATE_STBY, + EMMC_R1_STATE_TRAN, + EMMC_R1_STATE_DATA, + EMMC_R1_STATE_RCV, + EMMC_R1_STATE_PRG, + EMMC_R1_STATE_DIS, + EMMC_R1_STATE_BTST, + EMMC_R1_STATE_SLEP +} EMMC_R1_STATE; + +typedef enum{ + ESTATE_BEGIN = 0, + ESTATE_ISSUE_CMD, + ESTATE_NON_RESP_CMD, + ESTATE_RCV_RESP, + ESTATE_RCV_RESPONSE_BUSY, + ESTATE_CHECK_RESPONSE_COMPLETE, + ESTATE_DATA_TRANSFER, + ESTATE_DATA_TRANSFER_COMPLETE, + ESTATE_ACCESS_END, + ESTATE_TRANSFER_ERROR, + ESTATE_ERROR, + ESTATE_END +}EMMC_INT_STATE; + +/** @brief eMMC boot driver error information + */ +typedef struct { + uint16_t num; /**< error no */ + uint16_t code; /**< error code */ + volatile uint32_t info1; /**< SD_INFO1 register value. (hardware dependence) */ + volatile uint32_t info2; /**< SD_INFO2 register value. (hardware dependence) */ + volatile uint32_t status1; /**< SD_ERR_STS1 register value. (hardware dependence) */ + volatile uint32_t status2; /**< SD_ERR_STS2 register value. (hardware dependence) */ + volatile uint32_t dm_info1; /**< DM_CM_INFO1 register value. (hardware dependence) */ + volatile uint32_t dm_info2; /**< DM_CM_INFO2 register value. (hardware dependence) */ +} st_error_info; + + +/** @brief Command information + */ +typedef struct { + HAL_MEMCARD_COMMAND cmd; /**< Command information */ + uint32_t arg; /**< argument */ + HAL_MEMCARD_OPERATION dir; /**< direction */ + uint32_t hw; /**< H/W dependence. SD_CMD register value. */ +} st_command_info; + + +/** @brief MMC driver base + */ +typedef struct { + st_error_info error_info; /**< error information */ + st_command_info cmd_info; /**< command information */ + + /* for data transfer */ + uint32_t *buff_address_virtual; /**< Dest or Src buff */ + uint32_t *buff_address_physical; /**< Dest or Src buff */ + HAL_MEMCARD_DATA_WIDTH bus_width; /**< bus width */ + uint32_t trans_size; /**< transfer size for this command */ + uint32_t remain_size; /**< remain size for this command */ + uint32_t response_length; /**< response length for this command */ + uint32_t sector_size; /**< sector_size */ + + /* clock */ + uint32_t base_clock; /**< MMC host controller clock */ + uint32_t max_freq; /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */ + uint32_t request_freq; /**< request freq [Hz] (400K, 26MHz, 52MHz, etc) */ + uint32_t current_freq; /**< current MMC clock[Hz] (the closest frequency supported by HW) */ + + /* state flag */ + HAL_MEMCARD_PRESENCE_STATUS card_present; /**< presence status of the memory card */ + uint32_t card_power_enable; /**< True : Power ON */ + uint32_t clock_enable; /**< True : Clock ON */ + uint32_t initialize; /**< True : initialize complete. */ + uint32_t access_mode; /**< True : sector access, FALSE : byte access */ + uint32_t mount; /**< True : mount complete. */ + uint32_t selected; /**< True : selected card. */ + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; /**< 0: DMA, 1:PIO */ + uint32_t image_num; /**< loaded ISSW image No. ISSW have copy image. */ + EMMC_R1_STATE current_state; /**< card state */ + volatile uint32_t during_cmd_processing; /**< True : during command processing */ + volatile uint32_t during_transfer; /**< True : during transfer */ + volatile uint32_t during_dma_transfer; /**< True : during transfer (DMA)*/ + volatile uint32_t dma_error_flag; /**< True : occurred DMAC error */ + volatile uint32_t force_terminate; /**< force terminate flag */ + volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */ + volatile uint32_t get_partition_access_flag; /**< True : get partition access processing */ + + EMMC_PARTITION_ID boot_partition_en; /**< Boot partition */ + EMMC_PARTITION_ID partition_access; /**< Current access partition */ + + /* timeout */ + uint32_t hs_timing; /**< high speed */ + + /* timeout */ + uint32_t data_timeout; /**< read and write data timeout.*/ + + /* retry */ + uint32_t retries_after_fail; /**< how many times to try after fail, for instance sending command */ + + /* interrupt */ + volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */ + volatile uint32_t int_event2; /**< interrupt SD_INFO2 Event */ + volatile uint32_t dm_event1; /**< interrupt DM_CM_INFO1 Event */ + volatile uint32_t dm_event2; /**< interrupt DM_CM_INFO2 Event */ + + /* response */ + uint32_t *response; /**< pointer to buffer for executing command. */ + uint32_t r1_card_status; /**< R1 response data */ + uint32_t r3_ocr; /**< R3 response data */ + uint32_t r4_resp; /**< R4 response data */ + uint32_t r5_resp; /**< R5 response data */ + + uint32_t low_clock_mode_enable; /**< True : clock mode is low. (MMC clock = Max26MHz) */ + uint32_t reserved2; + uint32_t reserved3; + uint32_t reserved4; + + /* CSD registers (4byte align) */ + uint8_t csd_data[EMMC_MAX_CSD_LENGTH] /**< CSD */ + __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); + /* CID registers (4byte align) */ + uint8_t cid_data[EMMC_MAX_CID_LENGTH] /**< CID */ + __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); + /* EXT CSD registers (8byte align) */ + uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH] /**< EXT_CSD */ + __attribute__ ((aligned(EMMC_BUF_REG_ALIGNED))); + /* Response registers (4byte align) */ + uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH] /**< other response */ + __attribute__ ((aligned(EMMC_RES_REG_ALIGNED))); +} st_mmc_base; + +typedef int (*func)(void); + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +uint32_t emmc_get_csd_time(void); + +#define MMC_DEBUG +/* ********************************* CODE ********************************** */ + +/* ******************************** END ************************************ */ +#endif /* __EMMC_STD_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_common.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_common.h new file mode 100644 index 0000000..f5bbd97 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_common.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2014 ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef IO_COMMON_H__ +#define IO_COMMON_H__ + +/* io driver specification - used to refer to data on a device supporting */ +typedef struct io_drv_spec { + size_t offset; + size_t length; + uint32_t partition; +} io_drv_spec_t; + +extern void rcar_io_setup (void); +extern void rcar_io_emmc_setup (void); +extern int32_t plat_get_drv_source(uint32_t io_drv_id, + uintptr_t *dev_handle, + uintptr_t *image_spec); + + +#endif /* IO_COMMON_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_emmcdrv.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_emmcdrv.h new file mode 100644 index 0000000..442899b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_emmcdrv.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef IO_EMMCDRV_H__ +#define IO_EMMCDRV_H__ + +struct io_dev_connector; + +int32_t register_io_dev_emmcdrv(const io_dev_connector_t **dev_con); + +#endif /* IO_EMMCDRV_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_memdrv.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_memdrv.h new file mode 100644 index 0000000..4eafa5e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_memdrv.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef IO_MEMDRV_H__ +#define IO_MEMDRV_H__ + +struct io_dev_connector; + +int32_t register_io_dev_memdrv(const io_dev_connector_t **dev_con); + +#endif /* IO_MEMDRV_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_private.h new file mode 100644 index 0000000..2b7ce82 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_private.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef IO_PRIVATE_H_ +#define IO_PRIVATE_H_ + +/* Return codes reported by 'io_*' APIs */ +/* The value of fail should not overlap with define of the errno. */ +/* The errno is in "include/lib/stdlib/sys/errno.h". */ +#define IO_SUCCESS (0) +#define IO_FAIL (-0x81) +#define IO_NOT_SUPPORTED (-0x82) +#define IO_RESOURCES_EXHAUSTED (-0x83) + +#endif /* IO_PRIVATE_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_rcar.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_rcar.h new file mode 100644 index 0000000..f317236 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/io_rcar.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2014 ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef IO_RCAR_H__ +#define IO_RCAR_H__ + +int32_t register_io_dev_rcar(const io_dev_connector_t **dev_con); +int32_t file_to_cert(const int32_t filename, uint32_t *cert_addr); +void get_info_from_cert(uint64_t cert_addr, uint32_t *size, uintptr_t *dest_addr); +int32_t rcar_dev_init(io_dev_info_t *dev_info, const uintptr_t init_params); + +#endif /* IO_FIP_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/micro_wait.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/micro_wait.h new file mode 100644 index 0000000..2199764 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/micro_wait.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef MICRO_WAIT_H__ +#define MICRO_WAIT_H__ + +#define TMU3_MEASUREMENT (0) /* for time measurement */ + +#ifndef __ASSEMBLY__ +void micro_wait(uint32_t count_us); + +/* Time measurement function using the TMU3. */ +#if (TMU3_MEASUREMENT == 1) +void init_TMU3(void); +void start_TMU3(void); +uint32_t snapshot_TCNT3(void); +void stop_TMU3(void); +#endif /* TMU3_MEASUREMENT */ + +#endif /* __ASSEMBLY__ */ + +#endif /* MICRO_TWAIT_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/plat_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/plat_macros.S new file mode 100644 index 0000000..1520823 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/plat_macros.S @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include "rcar_def.h" + +.section .rodata.gic_reg_name, "aS" +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + + /* --------------------------------------------- + * The below macro prints out relevant GIC + * registers whenever an unhandled exception is + * taken in BL3-1. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_print_gic_regs + mov_imm x17, RCAR_GICC_BASE_A + mov_imm x16, RCAR_GICD_BASE_A +print_gicc_regs: + /* gicc base address is now in x17 */ + adr x6, gicc_regs /* Load the gicc reg list to x6 */ + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + adr x4, spacer + bl asm_print_str + ldr x4, [x7], #8 + bl asm_print_hex + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + .endm + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* ------------------------------------------------ + * The below macro prints out relevant interconnect + * registers whenever an unhandled exception is + * taken in BL3-1. + * Clobbers: x0 - x9, sp + * ------------------------------------------------ + */ + .macro plat_print_interconnect_regs + adr x6, cci_iface_regs + /* Store in x7 the base address of the first interface */ + mov_imm x7, (CCI500_BASE + SLAVE_IFACE3_OFFSET) + ldr w8, [x7, #SNOOP_CTRL_REG] + /* Store in x7 the base address of the second interface */ + mov_imm x7, (CCI500_BASE + SLAVE_IFACE4_OFFSET) + ldr w9, [x7, #SNOOP_CTRL_REG] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + .endm + + .macro plat_crash_print_regs + plat_print_gic_regs + plat_print_interconnect_regs + .endm diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/platform.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/platform.h new file mode 100644 index 0000000..09f0578 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/platform.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_PLATFORM_H__ +#define RCAR_PLATFORM_H__ + +#include + + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct plat_pm_ops; +struct meminfo; +struct image_info; +struct entry_point_info; +struct bl31_params; + +/******************************************************************************* + * Function declarations + ******************************************************************************/ +/******************************************************************************* + * Mandatory common functions + ******************************************************************************/ +uint64_t plat_get_syscnt_freq(void); +int plat_get_image_source(unsigned int image_id, + uintptr_t *dev_handle, + uintptr_t *image_spec); +unsigned long plat_get_ns_image_entrypoint(void); + +/******************************************************************************* + * Mandatory interrupt management functions + ******************************************************************************/ +uint32_t plat_ic_get_pending_interrupt_id(void); +uint32_t plat_ic_get_pending_interrupt_type(void); +uint32_t plat_ic_acknowledge_interrupt(void); +uint32_t plat_ic_get_interrupt_type(uint32_t id); +void plat_ic_end_of_interrupt(uint32_t id); +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state); + +/******************************************************************************* + * Optional common functions (may be overridden) + ******************************************************************************/ +unsigned int platform_get_core_pos(unsigned long mpidr); +unsigned long platform_get_stack(unsigned long mpidr); +void plat_report_exception(unsigned long); +int plat_crash_console_init(void); +int plat_crash_console_putc(int c); + +/******************************************************************************* + * Mandatory BL1 functions + ******************************************************************************/ +void bl1_early_platform_setup(void); +void bl1_plat_arch_setup(void); +void bl1_platform_setup(void); +struct meminfo *bl1_plat_sec_mem_layout(void); + +/* + * This function allows the platform to change the entrypoint information for + * BL2, after BL1 has loaded BL2 into memory but before BL2 is executed. + */ +void bl1_plat_set_bl2_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/******************************************************************************* + * Optional BL1 functions (may be overridden) + ******************************************************************************/ +void bl1_init_bl2_mem_layout(const struct meminfo *bl1_mem_layout, + struct meminfo *bl2_mem_layout); + +/******************************************************************************* + * Mandatory BL2 functions + ******************************************************************************/ +void bl2_early_platform_setup(struct meminfo *mem_layout); +void bl2_plat_arch_setup(void); +void bl2_platform_setup(void); +struct meminfo *bl2_plat_sec_mem_layout(void); + +/* + * This function returns a pointer to the shared memory that the platform has + * kept aside to pass trusted firmware related information that BL3-1 + * could need + */ +struct bl31_params *bl2_plat_get_bl31_params(void); + +/* + * This function returns a pointer to the shared memory that the platform + * has kept to point to entry point information of BL31 to BL2 + */ +struct entry_point_info *bl2_plat_get_bl31_ep_info(void); + +/* + * This function flushes to main memory all the params that are + * passed to BL3-1 + */ +void bl2_plat_flush_bl31_params(void); + +/* + * The next 2 functions allow the platform to change the entrypoint information + * for the mandatory 3rd level BL images, BL3-1 and BL3-3. This is done after + * BL2 has loaded those images into memory but before BL3-1 is executed. + */ +void bl2_plat_set_bl31_ep_info(struct image_info *image, + struct entry_point_info *ep); + +void bl2_plat_set_bl33_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* Gets the memory layout for BL3-3 */ +void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info); + +/******************************************************************************* + * Conditionally mandatory BL2 functions: must be implemented if BL3-0 image + * is supported + ******************************************************************************/ +/* Gets the memory layout for BL3-0 */ +void bl2_plat_get_bl30_meminfo(struct meminfo *mem_info); + +/* + * This function is called after loading BL3-0 image and it is used to perform + * any platform-specific actions required to handle the SCP firmware. + */ +int bl2_plat_handle_bl30(struct image_info *bl30_image_info); + +/******************************************************************************* + * Conditionally mandatory BL2 functions: must be implemented if BL3-2 image + * is supported + ******************************************************************************/ +void bl2_plat_set_bl32_ep_info(struct image_info *image, + struct entry_point_info *ep); + +/* Gets the memory layout for BL3-2 */ +void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info); + +/******************************************************************************* + * Optional BL2 functions (may be overridden) + ******************************************************************************/ +void bl2_init_generic_timer(void); + +/******************************************************************************* + * Mandatory BL3-1 functions + ******************************************************************************/ +void bl31_early_platform_setup(struct bl31_params *from_bl2, + void *plat_params_from_bl2); +void bl31_plat_arch_setup(void); +void bl31_platform_setup(void); +struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type); + +/******************************************************************************* + * Mandatory PSCI functions (BL3-1) + ******************************************************************************/ +int platform_setup_pm(const struct plat_pm_ops **); +unsigned int plat_get_aff_count(unsigned int, unsigned long); +unsigned int plat_get_aff_state(unsigned int, unsigned long); + +/******************************************************************************* + * Optional BL3-1 functions (may be overridden) + ******************************************************************************/ +void bl31_plat_enable_mmu(uint32_t flags); + +/******************************************************************************* + * Optional BL3-2 functions (may be overridden) + ******************************************************************************/ +void bl32_plat_enable_mmu(uint32_t flags); + +/******************************************************************************* + * Trusted Boot functions + ******************************************************************************/ +int plat_match_rotpk(const unsigned char *, unsigned int); + +#endif /* RCAR_PLATFORM_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/platform_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/platform_def.h new file mode 100644 index 0000000..01d4d4a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/platform_def.h @@ -0,0 +1,225 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_PLATFORM_DEF_H__ +#define RCAR_PLATFORM_DEF_H__ + +#include +#ifndef __ASSEMBLY__ +#include +#endif +#include "rcar_def.h" + + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Align the storing version code for BL2 and BL31 */ +#define ALIGN_VERSION (0x400) + +/* Size of cacheable stacks */ +#if IMAGE_BL1 +#if TRUSTED_BOARD_BOOT +#define PLATFORM_STACK_SIZE 0x1000 +#else +#define PLATFORM_STACK_SIZE 0x440 +#endif +#elif IMAGE_BL2 +#if TRUSTED_BOARD_BOOT +#define PLATFORM_STACK_SIZE 0x1000 +#else +#define PLATFORM_STACK_SIZE 0x400 +#endif +#elif IMAGE_BL31 +#define PLATFORM_STACK_SIZE 0x400 +#elif IMAGE_BL32 +#define PLATFORM_STACK_SIZE 0x440 +#endif + +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" + +#define BL332_IMAGE_ID (NS_BL2U_IMAGE_ID + 1) +#define BL333_IMAGE_ID (NS_BL2U_IMAGE_ID + 2) +#define BL334_IMAGE_ID (NS_BL2U_IMAGE_ID + 3) +#define BL335_IMAGE_ID (NS_BL2U_IMAGE_ID + 4) +#define BL336_IMAGE_ID (NS_BL2U_IMAGE_ID + 5) +#define BL337_IMAGE_ID (NS_BL2U_IMAGE_ID + 6) +#define BL338_IMAGE_ID (NS_BL2U_IMAGE_ID + 7) + +#define BL332_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 8) +#define BL333_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 9) +#define BL334_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 10) +#define BL335_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 11) +#define BL336_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 12) +#define BL337_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 13) +#define BL338_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 14) + +#define BL332_CERT_ID (NS_BL2U_IMAGE_ID + 15) +#define BL333_CERT_ID (NS_BL2U_IMAGE_ID + 16) +#define BL334_CERT_ID (NS_BL2U_IMAGE_ID + 17) +#define BL335_CERT_ID (NS_BL2U_IMAGE_ID + 18) +#define BL336_CERT_ID (NS_BL2U_IMAGE_ID + 19) +#define BL337_CERT_ID (NS_BL2U_IMAGE_ID + 20) +#define BL338_CERT_ID (NS_BL2U_IMAGE_ID + 21) + +/* io drivers id */ +#define FLASH_DEV_ID (0U) +#define EMMC_DEV_ID (1U) + +/* + * R-Car H3 Cortex-A57 + * L1:I/48KB(16KBx3way) D/32KB(16KBx2way) L2:2MB(128KBx16way) + * Cortex-A53 + * L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way) + */ +#define PLATFORM_CACHE_LINE_SIZE 64 +#define PLATFORM_CLUSTER_COUNT 1ull +#define PLATFORM_CLUSTER0_CORE_COUNT 2 +#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT + +#define PLATFORM_MAX_CPUS_PER_CLUSTER 2 +#define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT + 1) +#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +/******************************************************************************* + * BL1 specific defines. + * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of + * addresses. + ******************************************************************************/ +#define BL1_RO_BASE RCAR_TRUSTED_ROM_BASE +#define BL1_RO_LIMIT (RCAR_TRUSTED_ROM_BASE \ + + RCAR_TRUSTED_ROM_SIZE) +/* + * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using + * the current BL1 RW debug size plus a little space for growth. + */ +#if TRUSTED_BOARD_BOOT +#define BL1_RW_BASE (RCAR_TRUSTED_SRAM_BASE \ + + RCAR_TRUSTED_SRAM_SIZE - 0x8000) +#else +#define BL1_RW_BASE (RCAR_TRUSTED_SRAM_BASE \ + + RCAR_TRUSTED_SRAM_SIZE - 0x6000) +#endif +#define BL1_RW_LIMIT (RCAR_TRUSTED_SRAM_BASE \ + + RCAR_TRUSTED_SRAM_SIZE) + +/******************************************************************************* + * BL2 specific defines. + ******************************************************************************/ +/* + * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug + * size plus a little space for growth. + */ +#define RCAR_SECRAM_BASE (0xE6300000) +#define BL2_BASE (0x40008000) +#define BL2_LIMIT (0x40032800) +#define BL2_40BIT_BASE (0x0400008000ULL) +#define BL2_40BIT_LIMIT (0x0400032800ULL) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the + * current BL3-1 debug size plus a little space for growth. + */ +#define BL31_BASE (RCAR_TRUSTED_SRAM_BASE) +#define BL31_LIMIT (RCAR_TRUSTED_SRAM_BASE \ + + RCAR_TRUSTED_SRAM_SIZE) +#define RCAR_BL31_LOG_BASE (0x46800000) +#define RCAR_BL31_SDRAM_BTM (RCAR_BL31_LOG_BASE + 0x14000) +#define RCAR_BL31_LOG_SIZE (RCAR_BL31_SDRAM_BTM \ + - RCAR_BL31_LOG_BASE) + +#define BL31_SRAM_BASE (DEVICE_SRAM_BASE) +#define BL31_SRAM_LIMIT (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE) +#define BL31_SRAM_CODE_MAX (0x1000) + +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ +#ifndef SPD_NONE +# define BL32_BASE (0x44100000) +# define BL32_LIMIT (BL32_BASE + 0x100000) +#endif +/* + * ID of the secure physical generic timer interrupt used by the TSP. + */ + + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define ADDR_SPACE_SIZE (1ull << 32) + +#if IMAGE_BL1 +# define MAX_XLAT_TABLES 2 +#elif IMAGE_BL2 +# define MAX_XLAT_TABLES 3 +#elif IMAGE_BL31 +# define MAX_XLAT_TABLES 4 +#elif IMAGE_BL32 +# define MAX_XLAT_TABLES 3 +#endif + +#define MAX_MMAP_REGIONS (RCAR_MMAP_ENTRIES + RCAR_BL_REGIONS) + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#if !USE_COHERENT_MEM +/******************************************************************************* + * Size of the per-cpu data in bytes that should be reserved in the generic + * per-cpu data structure for the RCAR port. + ******************************************************************************/ +#define PLAT_PCPU_DATA_SIZE 2 +#endif + +#endif /* RCAR_PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/rcar_pm.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/rcar_pm.h new file mode 100644 index 0000000..0fd3765 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/rcar_pm.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_PM_H__ +#define RCAR_PM_H__ + +extern void rcar_bl31_restore_generic_timer(uint64_t *stack); + +#endif /* RCAR_PM_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/rom_api.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/rom_api.h new file mode 100644 index 0000000..6efd475 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/rom_api.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef ROM_API_H__ +#define ROM_API_H__ + +#include + +#define SBROM_OK (0x00000000U) +#define SBROM_ILLEGAL_INPUT_PARAM_ERR (0x0B000001U) +#define SBROM_ILLEGAL_OEM_HASH_VALUE_ERR (0x0B000008U) +#define SBROM_ILLEGAL_LCS_FOR_OPERATION_ERR (0x0B000010U) +#define SBROM_HASH_NOT_PROGRAMMED_ERR (0x0B000100U) +#define SBROM_PUB_KEY_HASH_VALIDATION_FAILURE (0xF1000006U) +#define SBROM_RSA_SIG_VERIFICATION_FAILED (0xF1000007U) + +#define LCS_CM (0x0U) /* CM */ +#define LCS_DM (0x1U) /* DM */ +#define LCS_SD (0x3U) /* SD */ +#define LCS_SE (0x5U) /* SE */ +#define LCS_FA (0x7U) /* FA */ + +typedef uint32_t (*ROM_FuncReadFlash)(uint64_t srcAddr, + uint8_t *pDest, + uint32_t sizeToRead); + +uint32_t ROM_SecureBootAPI(uint32_t *pKeyCert, + uint32_t *pContentCert, + ROM_FuncReadFlash pFuncReadFlash); +uint32_t ROM_GetLcs(uint32_t *pLcs); + + +#endif /* ROM_API_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/rpc_driver.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/rpc_driver.h new file mode 100644 index 0000000..c7006dd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/rpc_driver.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RPC_DRIVER_H__ +#define RPC_DRIVER_H__ + +void initRPC(void); + +#endif /* RPC_DRIVER_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/scif.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/scif.h new file mode 100644 index 0000000..fe1fb25 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/include/scif.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef SCIF_H__ +#define SCIF_H__ + + +#define SCIF_INTERNAL_CLK 0 /* Internal clock(S3D4:66.66MHz) */ +#define SCIF_EXTARNAL_CLK 1 /* External clock(SCK2:14.7456MHz) */ +#define SCIF_CLK SCIF_INTERNAL_CLK + + +#ifndef __ASSEMBLY__ + +void console_finalize(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* SCIF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/platform.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/platform.mk new file mode 100644 index 0000000..2a2379e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/platform.mk @@ -0,0 +1,181 @@ +# +# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + + +# Process flags + +PLAT_INCLUDES := -Iinclude/common/tbbr \ + -Iinclude/plat/arm/common \ + -Iplat/renesas/rcar/drivers/iic_dvfs/ \ + -Iplat/renesas/rcar/drivers/board/ \ + -Iplat/renesas/rcar/include \ + -Iplat/renesas/rcar + +PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ + lib/xlat_tables/aarch64/xlat_tables.c \ + plat/common/aarch64/plat_common.c + +RCAR_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c + +BL2_SOURCES += ${RCAR_GIC_SOURCES} \ + plat/common/${ARCH}/platform_up_stack.S \ + plat/renesas/rcar/drivers/timer/bl2_swdt.c \ + plat/renesas/rcar/drivers/error/bl2_int_error.c \ + plat/renesas/rcar/aarch64/rcar_helpers.S \ + plat/renesas/rcar/bl2_rcar_setup.c \ + plat/renesas/rcar/aarch64/rcar_common.c \ + plat/renesas/rcar/drivers/io/io_rcar.c \ + plat/renesas/rcar/drivers/io/io_memdrv.c \ + plat/renesas/rcar/drivers/io/io_emmcdrv.c \ + plat/renesas/rcar/drivers/scif/scif.S \ + plat/renesas/rcar/drivers/memdrv/rcar_printf.c \ + plat/renesas/rcar/drivers/auth/rcarboot.c \ + plat/renesas/rcar/rcar_io_storage.c \ + drivers/io/io_storage.c \ + plat/renesas/rcar/drivers/rpc/rpc_driver.c \ + plat/renesas/rcar/drivers/dma/dma_driver.c \ + plat/renesas/rcar/drivers/wait/micro_wait.S \ + plat/renesas/rcar/drivers/rom/rom_api.c \ + plat/renesas/rcar/drivers/board/board.c \ + plat/renesas/rcar/bl2_cpg_init.c \ + plat/renesas/rcar/aarch64/bl2_reset.S + +BL31_SOURCES += ${RCAR_GIC_SOURCES} \ + drivers/arm/cci/cci.c \ + lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a57.S \ + plat/common/aarch64/platform_mp_stack.S \ + plat/renesas/rcar/bl31_rcar_setup.c \ + plat/renesas/rcar/rcar_pm.c \ + plat/renesas/rcar/drivers/memdrv/rcar_console.S \ + plat/renesas/rcar/drivers/memdrv/rcar_printf.c \ + plat/renesas/rcar/rcar_topology.c \ + plat/renesas/rcar/aarch64/rcar_helpers.S \ + plat/renesas/rcar/aarch64/rcar_common.c \ + plat/renesas/rcar/drivers/pwrc/rcar_call_sram.S \ + plat/renesas/rcar/drivers/pwrc/rcar_pwrc.c \ + plat/renesas/rcar/drivers/cpld/ulcb_cpld.c + +# compile option setting +ARM_CCI_PRODUCT_ID := 500 +TRUSTED_BOARD_BOOT := 1 +ERROR_DEPRECATED := 1 + +ifeq (${SPD},none) + SPD_NONE:=1 + $(eval $(call add_define,SPD_NONE)) +endif + +# LSI setting common define +RCAR_V3M:=0 +$(eval $(call add_define,RCAR_V3M)) +RCAR_CUT_10:=0 +$(eval $(call add_define,RCAR_CUT_10)) + +ifndef LSI + $(error "Error: Unknown LSI. Please use LSI= to specify the LSI") +else + ifeq (${LSI},V3M) + RCAR_LSI:=${RCAR_V3M} + else + $(error "Error: ${LSI} is not supported.") + endif + $(eval $(call add_define,RCAR_LSI)) +endif + +# Process RCAR_SECURE_BOOT flag +ifndef RCAR_SECURE_BOOT +RCAR_SECURE_BOOT := 1 +endif +$(eval $(call add_define,RCAR_SECURE_BOOT)) + + +# Process RCAR_BL33_EXECUTION_EL flag +ifndef RCAR_BL33_EXECUTION_EL +RCAR_BL33_EXECUTION_EL := 0 +endif +$(eval $(call add_define,RCAR_BL33_EXECUTION_EL)) + +# Process PSCI_DISABLE_BIGLITTLE_IN_CA57BOOT flag +ifndef PSCI_DISABLE_BIGLITTLE_IN_CA57BOOT +PSCI_DISABLE_BIGLITTLE_IN_CA57BOOT := 1 +endif +$(eval $(call add_define,PSCI_DISABLE_BIGLITTLE_IN_CA57BOOT)) + +# Process RCAR_AVS_SETTING_ENABLE flag +ifeq (${RCAR_AVS_SETTING_ENABLE},0) +AVS_SETTING_ENABLE := 0 +else +AVS_SETTING_ENABLE := 1 +endif +$(eval $(call add_define,AVS_SETTING_ENABLE)) + +# Process RCAR_LOSSY_ENABLE flag +ifndef RCAR_LOSSY_ENABLE +RCAR_LOSSY_ENABLE := 0 +endif +$(eval $(call add_define,RCAR_LOSSY_ENABLE)) + +# Process LIFEC_DBSC_PROTECT_ENABLE flag +ifndef LIFEC_DBSC_PROTECT_ENABLE +LIFEC_DBSC_PROTECT_ENABLE := 1 +endif +$(eval $(call add_define,LIFEC_DBSC_PROTECT_ENABLE)) + +# Process PMIC_ON_BOARD flag +ifndef PMIC_ON_BOARD +PMIC_ON_BOARD := 0 +endif +ifeq (${PMIC_ON_BOARD},1) +BL2_SOURCES += plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.c +BL31_SOURCES += plat/renesas/rcar/drivers/iic_dvfs/iic_dvfs.c +endif +$(eval $(call add_define,PMIC_ON_BOARD)) + +# Process PMIC_LEVEL_MODE flag +ifndef PMIC_LEVEL_MODE +PMIC_LEVEL_MODE := 1 +endif +$(eval $(call add_define,PMIC_LEVEL_MODE)) + +# Process RCAR_GEN3_ULCB flag +ifndef RCAR_GEN3_ULCB +RCAR_GEN3_ULCB := 0 +endif +ifeq (${RCAR_GEN3_ULCB},1) + BOARD_DEFAULT := 0x10 + $(eval $(call add_define,BOARD_DEFAULT)) +endif +$(eval $(call add_define,RCAR_GEN3_ULCB)) diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_def.h new file mode 100644 index 0000000..6e05bd3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_def.h @@ -0,0 +1,316 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_DEF_H__ +#define RCAR_DEF_H__ + +#include + +/* Firmware Image Package */ +#define RCAR_PRIMARY_CPU 0x0 + +/* + * Some of the definitions in this file use the 'ull' suffix in order to avoid + * subtle integer overflow errors due to implicit integer type promotion when + * working with 32-bit values. + * + * The TSP linker script includes some of these definitions to define the BL3-2 + * memory map, but the GNU LD does not support the 'ull' suffix, causing the + * build process to fail. To solve this problem, the auxiliary macro MAKE_ULL(x) + * will add the 'ull' suffix only when the macro __LINKER__ is not defined + * (__LINKER__ is defined in the command line to preprocess the linker script). + * Constants in the linker script will not have the 'ull' suffix, but this is + * not a problem since the linker evaluates all constant expressions to 64 bit + * (assuming the target architecture is 64 bit). + */ +#ifndef __LINKER__ + #define MAKE_ULL(x) x##ull +#else + #define MAKE_ULL(x) x +#endif + +/******************************************************************************* + * RCAR memory map related constants + ******************************************************************************/ + +/* The first 4KB of Trusted SRAM are used as shared memory */ +#define RCAR_SHARED_MEM_BASE (RCAR_TRUSTED_SRAM_BASE + RCAR_TRUSTED_SRAM_SIZE) +#define RCAR_SHARED_MEM_SIZE 0x00001000U /* 4 KB */ + +/* The remaining Trusted SRAM is used to load the BL images */ +#define RCAR_TRUSTED_SRAM_BASE 0x46400000 /* Trusted Firmware Image */ +#define RCAR_TRUSTED_SRAM_SIZE 0x00022000 /* 136 KB */ + +#define FLASH0_BASE 0x08000000U /* LBSC RPC address */ +#define FLASH0_SIZE 0x04000000U /* 64MB */ +#define FLASH_MEMORY_SIZE 0x04000000U /* HyperFlash 64MB */ + +/* Aggregate of all devices in the first GB */ +#define DEVICE_RCAR_BASE 0xE6000000U +#define DEVICE_RCAR_SIZE 0x00300000U + +#define DEVICE_RCAR_BASE2 0xE6360000U +#define DEVICE_RCAR_SIZE2 0x19CA0000U + +#define DEVICE_SRAM_BASE 0xE6310000 +#define DEVICE_SRAM_SIZE 0x00001000 +#define DEVICE_SRAM_BASE_U 0xE6310000U /* for QAC */ +#define DEVICE_SRAM_SIZE_U 0x00001000U /* for QAC */ +#define DEVICE_SRAM_SHADOW_BASE (DEVICE_SRAM_BASE_U + DEVICE_SRAM_SIZE_U) + +#define DEVICE_SRAM_STACK_BASE (DEVICE_SRAM_SHADOW_BASE + DEVICE_SRAM_SIZE_U) +#define DEVICE_SRAM_STACK_SIZE 0x00001000 +#define DEVICE_SRAM_STACK_SIZE_U 0x00001000U /* for QAC */ + + +#define DRAM1_BASE MAKE_ULL(0x40000000) +#define DRAM1_SIZE MAKE_ULL(0x80000000) + +#define DRAM1_NS_BASE (DRAM1_BASE + 0x8000000U) +#define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_NS_BASE) +#define DRAM1_NS_END ((DRAM1_NS_BASE + DRAM1_NS_SIZE) - 0x00000001U) + +#define DRAM_LIMIT MAKE_ULL(0x0000010000000000) /* AArch64 */ + +#define SYS_CNTCTL_BASE 0xE6080000U + + +/* for Loading BL33-BL33x source/destination address range check */ +#define DRAM_40BIT_BASE MAKE_ULL(0x0400000000) +#define DRAM_40BIT_SIZE MAKE_ULL(0x0400000000) + +#define DRAM_PROTECTED_BASE MAKE_ULL(0x43F00000) +#define DRAM_40BIT_PROTECTED_BASE MAKE_ULL(0x0403F00000) +#define DRAM_PROTECTED_SIZE MAKE_ULL(0x03F00000) + +#define AARCH64_SPACE_BASE MAKE_ULL(0x00000000000) +#define AARCH64_SPACE_SIZE MAKE_ULL(0x10000000000) + +/* + * The number of regions like RO(code), coherent and data required by + * different BL stages which need to be mapped in the MMU. + */ +#if USE_COHERENT_MEM +#define RCAR_BL_REGIONS 3 +#else +#define RCAR_BL_REGIONS 2 +#endif + +/* + * The RCAR_MAX_MMAP_REGIONS depend on the number of entries in rcar_mmap[] + * defined for each BL stage in rcar_common.c. + */ +#if IMAGE_BL2 +#define RCAR_MMAP_ENTRIES 7 +#endif +#if IMAGE_BL31 +#define RCAR_MMAP_ENTRIES 9 +#endif + +/* Load address of BL33 in the RCAR port */ +#define NS_IMAGE_OFFSET (DRAM1_BASE + 0x09000000U) /* DRAM */ + +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define RCAR_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + + +/******************************************************************************* + * CCI-400 related constants + ******************************************************************************/ +#define CCI500_BASE 0xF1200000 +#define CCI500_CLUSTER0_SL_IFACE_IX 2 +#define CCI500_CLUSTER1_SL_IFACE_IX 3 +#define CCI500_CLUSTER0_SL_IFACE_IX_FOR_M3 1 +#define CCI500_CLUSTER1_SL_IFACE_IX_FOR_M3 2 + +/* CCI-500 */ +#define RCAR_CCI_BASE (0xF1200000U) /* The base address of CCI-500 */ + +/******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ +#define RCAR_GICD_BASE (0xF1010000U) +#define RCAR_GICD_BASE_A (0xF1010000) +#define RCAR_GICR_BASE (0xF1010000U) /* not use */ +#define RCAR_GICC_BASE (0xF1020000U) +#define RCAR_GICC_BASE_A (0xF1020000) +#define RCAR_GICH_BASE (0xF1040000U) /* not use */ +#define RCAR_GICV_BASE (0xF1060000U) /* not use */ + +#define ARM_IRQ_SEC_PHY_TIMER 29U + +#define ARM_IRQ_SEC_SGI_0 8U +#define ARM_IRQ_SEC_SGI_1 9U +#define ARM_IRQ_SEC_SGI_2 10U +#define ARM_IRQ_SEC_SGI_3 11U +#define ARM_IRQ_SEC_SGI_4 12U +#define ARM_IRQ_SEC_SGI_5 13U +#define ARM_IRQ_SEC_SGI_6 14U +#define ARM_IRQ_SEC_SGI_7 15U + +/****************************************************************************************************************************************************************/ +/* */ +/* Interrupt ID for Secure world */ +/* */ +/****************************************************************************************************************************************************************/ +#define ARM_IRQ_SEC_RPC ( 70U) /* RPC */ +#define ARM_IRQ_SEC_TIMER (166U) /* Secure timer */ +#define ARM_IRQ_SEC_TIMER_UP (171U) /* Secure timer UP */ +#define ARM_IRQ_SEC_WDT (173U) /* System watch dog timer */ +#define ARM_IRQ_SEC_WDT_A (173) /* System watch dog timer for Assembly language */ +#define ARM_IRQ_SEC_CRYPT (102U) /* Crypt Engine sec */ +#define ARM_IRQ_SEC_CRYPT_SecPKA ( 97U) /* Crypt Engine PKA sec */ +#define ARM_IRQ_SEC_CRYPT_PubPKA ( 98U) /* Crypt Engine PKA pub */ + +/****************************************************************************************************************************************************************/ +/* */ +/* New definition for R-CarGen3 */ +/* */ +/****************************************************************************************************************************************************************/ +#define RCAR_DEVICE_BASE (0xE6000000) /* Start address of BL31 register area */ +#define RCAR_DEVICE_SIZE (0x1A000000) /* Size of BL31 register area */ +#define RCAR_LOG_RES_SIZE (512/8) /* Size of reservation in log area */ +#define RCAR_LOG_HEADER_SIZE (16) /* Size of LOG header */ +#define RCAR_LOG_OTHER_SIZE (RCAR_LOG_HEADER_SIZE+RCAR_LOG_RES_SIZE) /* Size of write pointer, log header, reservation */ +#define RCAR_BL31_LOG_MAX (RCAR_BL31_LOG_SIZE - RCAR_LOG_OTHER_SIZE) /* MAX log size */ + +#define RCAR_CRASH_STACK (0x5043F800) + +/****************************************************************************************************************************************************************/ +/* */ +/* Definition of R-CarGen3 register address */ +/* */ +/****************************************************************************************************************************************************************/ +/* Timer */ +#define RCAR_CNTC_BASE (0xE6080000U) /* The base addess of generic timer control register */ +#define RCAR_CNTC_BASE_A (0xE6080000) /* The base addess of generic timer control register for Assenbly */ +/* Reset */ +#define RCAR_CPGWPR (0xE6150900U) /* CPG write protect register */ +#define RCAR_MODEMR (0xE6160060U) /* Mode pin register */ +#define RCAR_MODEMR_A (0xE6160060) /* Mode pin register for Assembly language */ +#define RCAR_CA57RESCNT (0xE6160040U) /* Reset control register for A57 */ +#define RCAR_CA53RESCNT (0xE6160044U) /* Reset control register for A53 */ +#define RCAR_SRESCR (0xE6160110U) /* Soft Power On Reset Control Register */ +#define RCAR_CA53WUPCR (0xE6151010U) /* Wake-up control register for A53 */ +#define RCAR_CA57WUPCR (0xE6152010U) /* Wake-up control register for A57 */ +#define RCAR_CA53PSTR (0xE6151040U) /* Power status register for A53 */ +#define RCAR_CA57PSTR (0xE6152040U) /* Power status register for A57 */ +#define RCAR_CA53CPU0CR (0xE6151100U) /* The base address of CPU power status control register for A53 */ +#define RCAR_CA57CPU0CR (0xE6152100U) /* The base address of CPU power status control register for A57 */ +#define RCAR_CA53CPUCMCR (0xE6151184U) /* Common power control register for A53 */ +#define RCAR_CA57CPUCMCR (0xE6152184U) /* Common power control register for A57 */ +#define RCAR_WUPMSKCA57 (0xE6180014U) /* Wake-up mask register for A57 */ +#define RCAR_WUPMSKCA53 (0xE6180018U) /* Wake-up mask register for A53 */ +/* SYSC */ +#define RCAR_PWRSR3 (0xE6180140U) /* Power status register CA53-SCU */ +#define RCAR_PWRSR5 (0xE61801C0U) /* Power status register CA57-SCU */ +#define RCAR_SYSCIER (0xE618000CU) /* Interrupt enable register */ +#define RCAR_SYSCIMR (0xE6180010U) /* Interrupt mask register */ +#define RCAR_SYSCSR (0xE6180000U) /* SYSC status register */ +#define RCAR_PWRONCR3 (0xE618014CU) /* Power resume control register CA53-SCU */ +#define RCAR_PWRONCR5 (0xE61801CCU) /* Power resume control register CA57-SCU */ +#define RCAR_PWROFFCR3 (0xE6180144U) /* Power shutoff control register CA53-SCU */ +#define RCAR_PWROFFCR5 (0xE61801C4U) /* Power shutoff control register CA57-SCU */ +#define RCAR_PWRER3 (0xE6180154U) /* Power shutoff/resume error register CA53-SCU */ +#define RCAR_PWRER5 (0xE61801D4U) /* Power shutoff/resume error register CA57-SCU */ +#define RCAR_SYSCISR (0xE6180004U) /* Interrupt status register */ +#define RCAR_SYSCISCR (0xE6180008U) /* Interrupt status clear register */ +/* Product register */ +#define RCAR_PRR (0xFFF00044U) /* Product register */ + +/******************************************************************************* + * RCAR product and cut information + ******************************************************************************/ +#define RCAR_PRODUCT_MASK (0x00007F00U) +#define RCAR_CUT_MASK (0x000000FFU) +#define RCAR_PRODUCT_V3M (0x00005400U) +#define RCAR_CUT_ES10 (0x00000000U) +#define RCAR_CUT_ES11 (0x00000001U) +#define RCAR_CUT_ES20 (0x00000010U) +#define RCAR_MAJOR_MASK (0x000000F0U) +#define RCAR_MINOR_MASK (0x0000000FU) +#define RCAR_PRODUCT_SHIFT (8U) +#define RCAR_MAJOR_SHIFT (4U) +#define RCAR_MINOR_SHIFT (0U) +#define RCAR_MAJOR_OFFSET (1U) + +/******************************************************************************* + * RCAR MD pin information + ******************************************************************************/ +#define MODEMR_BOOT_CPU_MASK (0x000000C0U) +#define MODEMR_BOOT_CPU_CR7 (0x000000C0U) +#define MODEMR_BOOT_CPU_CA57 (0x00000000U) +#define MODEMR_BOOT_CPU_CA53 (0x00000040U) +#define MODEMR_BOOT_DEV_MASK (0x0000001EU) +#define MODEMR_BOOT_DEV_HYPERFLASH160 (0x00000004U) +#define MODEMR_BOOT_DEV_HYPERFLASH80 (0x00000006U) +#define MODEMR_BOOT_DEV_QSPI_FLASH40 (0x00000008U) +#define MODEMR_BOOT_DEV_QSPI_FLASH80 (0x0000000CU) +#define MODEMR_BOOT_DEV_EMMC_25X1 (0x0000000AU) +#define MODEMR_BOOT_DEV_EMMC_50X8 (0x0000001AU) +#define MODEMR_BOOT_PLL_MASK (0x00006000U) +#define MODEMR_BOOT_PLL_SHIFT (13U) + +/****************************************************************************************************************************************************************/ +/* Memory mapped Generic timer interfaces */ +/****************************************************************************************************************************************************************/ +#define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE + +/******************************************************************************* + * Boot CPU + ******************************************************************************/ +#define RCAR_BOOT_CA5X (0U) /* Master boot CPU is CA57/53 */ +#define RCAR_BOOT_CR7 (1U) /* Master boot CPU is CR7 */ + +/******************************************************************************* + * Shared Data + ******************************************************************************/ + +#define RCAR_BL31_CRASH_BASE (0x5043F000U) +#define RCAR_BL31_CRASH_SIZE (0x00001000U) + +/* Entrypoint mailboxes */ +#define MBOX_BASE RCAR_SHARED_MEM_BASE +#define MBOX_SIZE 0x200 + +/* Base address where parameters to BL31 are stored */ +#define PARAMS_BASE (MBOX_BASE + MBOX_SIZE) + +/******************************************************************************* + * MODEMR PLL masks and bitfield values + ******************************************************************************/ +#define CHECK_MD13_MD14 (0x6000U) +#define MD14_MD13_TYPE_0 (0x0000U) /* MD14=0 MD13=0 */ +#define MD14_MD13_TYPE_1 (0x2000U) /* MD14=0 MD13=1 */ +#define MD14_MD13_TYPE_2 (0x4000U) /* MD14=1 MD13=0 */ +#define MD14_MD13_TYPE_3 (0x6000U) /* MD14=1 MD13=1 */ + +#endif /* RCAR_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_io_storage.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_io_storage.c new file mode 100644 index 0000000..e4df976 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_io_storage.c @@ -0,0 +1,526 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include /* For ARRAY_SIZE */ +#include +#include +#include +#include +#include +#include +#include "io_common.h" +#include "io_rcar.h" +#include "io_memdrv.h" +#include "io_emmcdrv.h" +#include "io_private.h" + +/* IO devices */ +static uintptr_t rcar_dev_handle; +static uintptr_t memdrv_dev_handle; +static uintptr_t emmcdrv_dev_handle; +static uintptr_t boot_io_drv_id; + + +static const io_block_spec_t rcar_block_spec = { + .offset = FLASH0_BASE, + .length = FLASH0_SIZE +}; + +static const io_block_spec_t bl2_file_spec = { + .offset = BL2_IMAGE_ID, +}; + +static const io_block_spec_t bl31_file_spec = { + .offset = BL31_IMAGE_ID, +}; + +static const io_block_spec_t bl32_file_spec = { + .offset = BL32_IMAGE_ID, +}; + +static const io_block_spec_t bl33_file_spec = { + .offset = BL33_IMAGE_ID, +}; + +static const io_block_spec_t bl332_file_spec = { + .offset = BL332_IMAGE_ID, +}; + +static const io_block_spec_t bl333_file_spec = { + .offset = BL333_IMAGE_ID, +}; + +static const io_block_spec_t bl334_file_spec = { + .offset = BL334_IMAGE_ID, +}; + +static const io_block_spec_t bl335_file_spec = { + .offset = BL335_IMAGE_ID, +}; + +static const io_block_spec_t bl336_file_spec = { + .offset = BL336_IMAGE_ID, +}; + +static const io_block_spec_t bl337_file_spec = { + .offset = BL337_IMAGE_ID, +}; + +static const io_block_spec_t bl338_file_spec = { + .offset = BL338_IMAGE_ID, +}; + + +#if TRUSTED_BOARD_BOOT +static const io_block_spec_t trusted_key_cert_file_spec = { + .offset = TRUSTED_KEY_CERT_ID, +}; + +static const io_block_spec_t bl31_key_cert_file_spec = { + .offset = SOC_FW_KEY_CERT_ID, +}; + +static const io_block_spec_t bl32_key_cert_file_spec = { + .offset = TRUSTED_OS_FW_KEY_CERT_ID, +}; + +static const io_block_spec_t bl33_key_cert_file_spec = { + .offset = NON_TRUSTED_FW_KEY_CERT_ID, +}; + +static const io_block_spec_t bl332_key_cert_file_spec = { + .offset = BL332_KEY_CERT_ID, +}; + +static const io_block_spec_t bl333_key_cert_file_spec = { + .offset = BL333_KEY_CERT_ID, +}; + +static const io_block_spec_t bl334_key_cert_file_spec = { + .offset = BL334_KEY_CERT_ID, +}; + +static const io_block_spec_t bl335_key_cert_file_spec = { + .offset = BL335_KEY_CERT_ID, +}; + +static const io_block_spec_t bl336_key_cert_file_spec = { + .offset = BL336_KEY_CERT_ID, +}; + +static const io_block_spec_t bl337_key_cert_file_spec = { + .offset = BL337_KEY_CERT_ID, +}; + +static const io_block_spec_t bl338_key_cert_file_spec = { + .offset = BL338_KEY_CERT_ID, +}; + +static const io_block_spec_t bl31_cert_file_spec = { + .offset = SOC_FW_CONTENT_CERT_ID, +}; + +static const io_block_spec_t bl32_cert_file_spec = { + .offset = TRUSTED_OS_FW_CONTENT_CERT_ID, +}; + +static const io_block_spec_t bl33_cert_file_spec = { + .offset = NON_TRUSTED_FW_CONTENT_CERT_ID, +}; + +static const io_block_spec_t bl332_cert_file_spec = { + .offset = BL332_CERT_ID, +}; + +static const io_block_spec_t bl333_cert_file_spec = { + .offset = BL333_CERT_ID, +}; + +static const io_block_spec_t bl334_cert_file_spec = { + .offset = BL334_CERT_ID, +}; + +static const io_block_spec_t bl335_cert_file_spec = { + .offset = BL335_CERT_ID, +}; + +static const io_block_spec_t bl336_cert_file_spec = { + .offset = BL336_CERT_ID, +}; + +static const io_block_spec_t bl337_cert_file_spec = { + .offset = BL337_CERT_ID, +}; + +static const io_block_spec_t bl338_cert_file_spec = { + .offset = BL338_CERT_ID, +}; +#endif /* TRUSTED_BOARD_BOOT */ + +static int32_t open_rcar(const uintptr_t spec); +static int32_t open_memmap(const uintptr_t spec); +static int32_t open_emmcdrv(const uintptr_t spec); + +struct plat_io_policy { + uintptr_t *dev_handle; + uintptr_t image_spec; + int32_t (*check)(const uintptr_t spec); +}; + +static const struct plat_io_policy policies[] = { + [FIP_IMAGE_ID] = { + &memdrv_dev_handle, + (uintptr_t)&rcar_block_spec, + &open_memmap + }, + [BL2_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl2_file_spec, + &open_rcar + }, + [BL31_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl31_file_spec, + &open_rcar + }, + [BL32_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl32_file_spec, + &open_rcar + }, + [BL33_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl33_file_spec, + &open_rcar + }, + [BL332_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl332_file_spec, + &open_rcar + }, + [BL333_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl333_file_spec, + &open_rcar + }, + [BL334_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl334_file_spec, + &open_rcar + }, + [BL335_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl335_file_spec, + &open_rcar + }, + [BL336_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl336_file_spec, + &open_rcar + }, + [BL337_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl337_file_spec, + &open_rcar + }, + [BL338_IMAGE_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl338_file_spec, + &open_rcar + }, +#if TRUSTED_BOARD_BOOT + [TRUSTED_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&trusted_key_cert_file_spec, + &open_rcar + }, + [SOC_FW_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl31_key_cert_file_spec, + &open_rcar + }, + [TRUSTED_OS_FW_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl32_key_cert_file_spec, + &open_rcar + }, + [NON_TRUSTED_FW_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl33_key_cert_file_spec, + &open_rcar + }, + [BL332_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl332_key_cert_file_spec, + &open_rcar + }, + [BL333_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl333_key_cert_file_spec, + &open_rcar + }, + [BL334_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl334_key_cert_file_spec, + &open_rcar + }, + [BL335_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl335_key_cert_file_spec, + &open_rcar + }, + [BL336_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl336_key_cert_file_spec, + &open_rcar + }, + [BL337_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl337_key_cert_file_spec, + &open_rcar + }, + [BL338_KEY_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl338_key_cert_file_spec, + &open_rcar + }, + [SOC_FW_CONTENT_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl31_cert_file_spec, + &open_rcar + }, + [TRUSTED_OS_FW_CONTENT_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl32_cert_file_spec, + &open_rcar + }, + [NON_TRUSTED_FW_CONTENT_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl33_cert_file_spec, + &open_rcar + }, + [BL332_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl332_cert_file_spec, + &open_rcar + }, + [BL333_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl333_cert_file_spec, + &open_rcar + }, + [BL334_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl334_cert_file_spec, + &open_rcar + }, + [BL335_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl335_cert_file_spec, + &open_rcar + }, + [BL336_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl336_cert_file_spec, + &open_rcar + }, + [BL337_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl337_cert_file_spec, + &open_rcar + }, + [BL338_CERT_ID] = { + &rcar_dev_handle, + (uintptr_t)&bl338_cert_file_spec, + &open_rcar + },{ +#endif /* TRUSTED_BOARD_BOOT */ + 0, 0, 0 + } +}; + +static const io_drv_spec_t io_drv_spec_memdrv = { + FLASH0_BASE, + FLASH0_SIZE, + 0U +}; + +static const io_drv_spec_t io_drv_spec_emmcdrv = { + 0U, + 0U, + 0U +}; + +static const struct plat_io_policy drv_policies[] = { + /* FLASH_DEV_ID */ + { + &memdrv_dev_handle, + (uintptr_t)&io_drv_spec_memdrv, + &open_memmap + }, + /* EMMC_DEV_ID */ + { + &emmcdrv_dev_handle, + (uintptr_t)&io_drv_spec_emmcdrv, + &open_emmcdrv + } +}; + +static int32_t open_rcar(const uintptr_t spec) +{ + int32_t result; + + /* See if a Firmware Image Package is available */ + result = io_dev_init(rcar_dev_handle, (uintptr_t)boot_io_drv_id); + + return result; +} + + +static int32_t open_memmap(const uintptr_t spec) +{ + int32_t result; + uintptr_t local_image_handle; + + result = io_dev_init(memdrv_dev_handle, 0U); + if (result == IO_SUCCESS) { + result = io_open(memdrv_dev_handle, spec, &local_image_handle); + if (result == IO_SUCCESS) { + (void)io_close(local_image_handle); + } + } + return result; +} + +static int32_t open_emmcdrv(const uintptr_t spec) +{ + int32_t result; + + result = io_dev_init(emmcdrv_dev_handle, 0U); + + return result; +} + + +void rcar_io_setup (void) +{ + int32_t io_result; + const io_dev_connector_t *rcar_dev_con; + const io_dev_connector_t *memmap_dev_con; + + boot_io_drv_id = FLASH_DEV_ID; + + /* Register the IO devices on this platform */ + io_result = register_io_dev_rcar(&rcar_dev_con); + assert(io_result == IO_SUCCESS); + + io_result = register_io_dev_memdrv(&memmap_dev_con); + assert(io_result == IO_SUCCESS); + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(rcar_dev_con, 0U, &rcar_dev_handle); + assert(io_result == IO_SUCCESS); + + io_result = io_dev_open(memmap_dev_con, 0U, + &memdrv_dev_handle); + assert(io_result == IO_SUCCESS); + + /* Ignore improbable errors in release builds */ + (void)io_result; +} +#if RCAR_LSI != RCAR_V3M +void rcar_io_emmc_setup (void) +{ + int32_t io_result; + const io_dev_connector_t *rcar_dev_con; + const io_dev_connector_t *emmc_dev_con; + + boot_io_drv_id = EMMC_DEV_ID; + + /* Register the IO devices on this platform */ + io_result = register_io_dev_rcar(&rcar_dev_con); + assert(io_result == IO_SUCCESS); + + io_result = register_io_dev_emmcdrv(&emmc_dev_con); + assert(io_result == IO_SUCCESS); + + /* Open connections to devices and cache the handles */ + io_result = io_dev_open(rcar_dev_con, 0U, &rcar_dev_handle); + assert(io_result == IO_SUCCESS); + + io_result = io_dev_open(emmc_dev_con, 0U, + &emmcdrv_dev_handle); + + assert(io_result == IO_SUCCESS); + + /* Ignore improbable errors in release builds */ + (void)io_result; +} +#endif + +/* Return an IO device handle and specification which can be used to access + * an image. Use this to enforce platform load policy */ +int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int result = IO_FAIL; + const struct plat_io_policy *policy; + + assert(image_id < ARRAY_SIZE(policies)); + + policy = &policies[image_id]; + result = policy->check(policy->image_spec); + if (result == IO_SUCCESS) { + *image_spec = policy->image_spec; + *dev_handle = *(policy->dev_handle); + } + + return result; +} + +int32_t plat_get_drv_source(uint32_t io_drv_id, uintptr_t *dev_handle, + uintptr_t *image_spec) +{ + int32_t result; + const struct plat_io_policy *policy; + + assert(io_drv_id < ARRAY_SIZE(drv_policies)); + + policy = &drv_policies[io_drv_id]; + result = policy->check(policy->image_spec); + if (result == IO_SUCCESS) { + *image_spec = policy->image_spec; + *dev_handle = *(policy->dev_handle); + } + + return result; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_pm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_pm.c new file mode 100644 index 0000000..aaa3951 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_pm.c @@ -0,0 +1,509 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "drivers/pwrc/rcar_pwrc.h" +#include "drivers/iic_dvfs/iic_dvfs.h" +#include "rcar_def.h" +#include "rcar_private.h" +#include "rcar_pm.h" + +static void rcar_program_mailbox(uint64_t mpidr, uint64_t address); +static int32_t rcar_do_plat_actions(unsigned int afflvl, unsigned int state); +static void rcar_cpu_pwrdwn_common(void); +static void rcar_cluster_pwrdwn_common(void); +static void __dead2 rcar_system_off(void); +static void __dead2 rcar_system_reset(void); + +#if !PMIC_ON_BOARD +static int32_t cpu_on_check(uint64_t mpidr); +extern int32_t platform_is_primary_cpu(uint64_t mpidr); +#endif + +extern void cpld_reset_cpu(void); + +#define RCAR_GENERIC_TIMER_STACK (0x300) +#define RCAR_BOOT_MODE (0x01U) +#define RCAR_BOOT_COLD (0x00U) + +#define RCAR_MPIDR_CA57_CPU0 ((uint64_t)0x0000U) +#define RCAR_MPIDR_CA53_CPU0 ((uint64_t)0x0100U) + +uint64_t rcar_stack_generic_timer[5] __attribute__((section("data"))); +/******************************************************************************* + * Private RCAR function to program the mailbox for a cpu before it is released + * from reset. + ******************************************************************************/ +static void rcar_program_mailbox(uint64_t mpidr, uint64_t address) +{ + uint64_t linear_id; + mailbox_t *rcar_mboxes; + + linear_id = platform_get_core_pos(mpidr); + rcar_mboxes = (mailbox_t *)MBOX_BASE; + rcar_mboxes[linear_id].value = address; + flush_dcache_range((unsigned long)&rcar_mboxes[linear_id], + sizeof(unsigned long)); +} + +/******************************************************************************* + * Function which implements the common RCAR specific operations to power down a + * cpu in response to a CPU_OFF or CPU_SUSPEND request. + ******************************************************************************/ +static void rcar_cpu_pwrdwn_common(void) +{ + /* Prevent interrupts from spuriously waking up this cpu */ + gicv2_cpuif_disable(); + + /* Program the power controller to power off this cpu. */ + rcar_pwrc_cpuoff (read_mpidr_el1()); +} + +/******************************************************************************* + * Function which implements the common RCAR specific operations to power down a + * cluster in response to a CPU_OFF or CPU_SUSPEND request. + ******************************************************************************/ +static void rcar_cluster_pwrdwn_common(void) +{ + uint64_t mpidr = read_mpidr_el1(); + + /* Disable coherency if this cluster is to be turned off */ + rcar_cci_disable(); + + /* Program the power controller to turn the cluster off */ + rcar_pwrc_clusteroff(mpidr); +} + +/******************************************************************************* + * Private RCAR function which is used to determine if any platform actions + * should be performed for the specified affinity instance given its + * state. Nothing needs to be done if the 'state' is not off or if this is not + * the highest affinity level which will enter the 'state'. + ******************************************************************************/ +static int32_t rcar_do_plat_actions(unsigned int afflvl, unsigned int state) +{ + unsigned int max_phys_off_afflvl; + + if (state != PSCI_STATE_OFF) { + return -EAGAIN; + } + + /* + * Find the highest affinity level which will be suspended and postpone + * all the platform specific actions until that level is hit. + */ + max_phys_off_afflvl = psci_get_max_phys_off_afflvl(); + if (afflvl != max_phys_off_afflvl) { + return -EAGAIN; + } + + return 0; +} + +/******************************************************************************* + * RCAR handler called when an affinity instance is about to enter standby. + ******************************************************************************/ +void rcar_affinst_standby(unsigned int power_state) +{ + /* + * Enter standby state + * dsb is good practice before using wfi to enter low power states + */ + uint32_t scr_el3; + + scr_el3 = read_scr_el3(); + write_scr_el3(scr_el3 | SCR_IRQ_BIT); + dsb(); + wfi(); + write_scr_el3(scr_el3); +} + +/******************************************************************************* + * RCAR handler called when an affinity instance is about to be turned on. The + * level and mpidr determine the affinity instance. + ******************************************************************************/ +int rcar_affinst_on(unsigned long mpidr, unsigned long sec_entrypoint, + unsigned int afflvl, unsigned int state) +{ + int rc = PSCI_E_SUCCESS; + +#if PSCI_DISABLE_BIGLITTLE_IN_CA57BOOT + uint64_t boot_cluster = read_mpidr_el1() & ((uint64_t)MPIDR_CLUSTER_MASK); + if (boot_cluster == 0x0000U) { + if ((mpidr & ((uint64_t)MPIDR_CLUSTER_MASK)) != boot_cluster) { + return PSCI_E_INTERN_FAIL; + } + } +#endif + /* + * It's possible to turn on only affinity level 0 i.e. a cpu + * on the RCAR. Ignore any other affinity level. + */ + if (afflvl != MPIDR_AFFLVL0) { + return rc; + } + + /* + * Ensure that we do not cancel an inflight power off request + * for the target cpu. That would leave it in a zombie wfi. + * Wait for it to power off, program the jump address for the + * target cpu and then program the power controller to turn + * that cpu on + */ + + rcar_program_mailbox(mpidr, sec_entrypoint); + rcar_pwrc_cpuon(mpidr); + + return rc; +} + +/******************************************************************************* + * RCAR handler called when an affinity instance is about to be turned off. The + * level and mpidr determine the affinity instance. The 'state' arg. allows the + * platform to decide whether the cluster is being turned off and take apt + * actions. + * + * CAUTION: There is no guarantee that caches will remain turned on across calls + * to this function as each affinity level is dealt with. So do not write & read + * global variables across calls. It will be wise to do flush a write to the + * global to prevent unpredictable results. + ******************************************************************************/ +void rcar_affinst_off(unsigned int afflvl, unsigned int state) +{ + /* Determine if any platform actions need to be executed */ + if (rcar_do_plat_actions(afflvl, state) == -EAGAIN) { + return; + } + + /* + * If execution reaches this stage then this affinity level will be + * suspended. Perform at least the cpu specific actions followed the + * cluster specific operations if applicable. + */ + rcar_cpu_pwrdwn_common(); + + if (afflvl != MPIDR_AFFLVL0) { + rcar_cluster_pwrdwn_common(); + } +} + +/******************************************************************************* + * RCAR handler called when an affinity instance is about to be suspended. The + * level and mpidr determine the affinity instance. The 'state' arg. allows the + * platform to decide whether the cluster is being turned off and take apt + * actions. + * + * CAUTION: There is no guarantee that caches will remain turned on across calls + * to this function as each affinity level is dealt with. So do not write & read + * global variables across calls. It will be wise to do flush a write to the + * global to prevent unpredictable results. + ******************************************************************************/ +void rcar_affinst_suspend(unsigned long sec_entrypoint, unsigned int afflvl, + unsigned int state) +{ + unsigned long mpidr; + + /* Determine if any platform actions need to be executed. */ + if (rcar_do_plat_actions(afflvl, state) == -EAGAIN) { + return; + } + + /* Get the mpidr for this cpu */ + mpidr = read_mpidr_el1(); + + /* Program the jump address for the this cpu */ + rcar_program_mailbox(mpidr, sec_entrypoint); + + /* Program the power controller to enable wakeup interrupts. */ + rcar_pwrc_enable_interrupt_wakeup(mpidr); + + /* Perform the common cpu specific operations */ + rcar_cpu_pwrdwn_common(); + + /* Perform the common cluster specific operations */ + if (afflvl != MPIDR_AFFLVL0) { + rcar_cluster_pwrdwn_common(); + } +} + +/******************************************************************************* + * RCAR handler called when an affinity instance has just been powered on after + * being turned off earlier. The level and mpidr determine the affinity + * instance. The 'state' arg. allows the platform to decide whether the cluster + * was turned off prior to wakeup and do what's necessary to setup it up + * correctly. + ******************************************************************************/ +void rcar_affinst_on_finish(unsigned int afflvl, unsigned int state) +{ + unsigned long mpidr; + + /* Determine if any platform actions need to be executed. */ + if (rcar_do_plat_actions(afflvl, state) == -EAGAIN) { + return; + } + + /* Get the mpidr for this cpu */ + mpidr = read_mpidr_el1(); + + /* Perform the common cluster specific operations */ + if (afflvl != MPIDR_AFFLVL0) { + /* Enable coherency if this cluster was off */ + rcar_cci_enable(); + } + + /* + * Prohibit cpu wake up by interrupt + */ + rcar_pwrc_disable_interrupt_wakeup(mpidr); + + /* Zero the jump address in the mailbox for this cpu */ + rcar_program_mailbox(mpidr, 0U); + + /* Enable the gic cpu interface */ + gicv2_cpuif_enable(); + + /* Program the gic per-cpu distributor or re-distributor interface */ + gicv2_pcpu_distif_init(); +} + +/******************************************************************************* + * RCAR handler called when an affinity instance has just been powered on after + * having been suspended earlier. The level and mpidr determine the affinity + * instance. + * TODO: At the moment we reuse the on finisher and reinitialize the secure + * context. Need to implement a separate suspend finisher. + ******************************************************************************/ +void rcar_affinst_suspend_finish(unsigned int afflvl, unsigned int state) +{ + if ((uint32_t)afflvl >= (uint32_t)PLATFORM_MAX_AFFLVL) { + plat_arm_gic_driver_init(); + plat_arm_gic_init(); + rcar_cci_init(); + /* restore generic timer register */ + rcar_bl31_restore_generic_timer(rcar_stack_generic_timer); + /* start generic timer */ + write_cntfrq_el0((unsigned long)plat_get_syscnt_freq2()); + mmio_write_32((uintptr_t)(RCAR_CNTC_BASE+(uint32_t)CNTCR_OFF), + (uint32_t)(CNTCR_FCREQ(0)|CNTCR_EN)); + rcar_pwrc_setup(); +#if PMIC_ON_BOARD + rcar_bl31_init_suspend_to_ram(); +#endif /* PMIC_ON_BOARD */ + } + + rcar_affinst_on_finish(afflvl, state); + +} + +/******************************************************************************* + * RCAR handlers to shutdown/reboot the system + ******************************************************************************/ +static void __dead2 rcar_system_off(void) +{ +#if PMIC_ON_BOARD +#if PMIC_LEVEL_MODE + + /* The code of iic for DVFS driver is copied to system ram */ + rcar_bl31_code_copy_to_system_ram(); + +#else /* pulse mode */ + int32_t error; + + /* The code of iic for DVFS driver is copied to system ram */ + rcar_bl31_code_copy_to_system_ram(); + + error = rcar_iic_dvfs_send(SLAVE_ADDR_PMIC + ,REG_ADDR_BKUP_Mode_Cnt + ,REG_DATA_P_ALL_OFF); + if (error != 0) { + ERROR("BL3-1:Failed the SYSTEM-RESET.\n"); + } +#endif +#else /* not PMIC_ON_BOARD */ + uint64_t my_cpu; + int32_t rtn_primary; + int32_t rtn_on; + + my_cpu = read_mpidr_el1(); + rtn_primary = platform_is_primary_cpu(my_cpu); + rtn_on = cpu_on_check(my_cpu); + if ((rtn_primary != 0) && (rtn_on == 0)) { + rcar_pwrc_cpuoff(my_cpu); + rcar_pwrc_clusteroff(my_cpu); + } else { + panic(); + } +#endif + wfi(); + ERROR("RCAR System Off: operation not handled.\n"); + panic(); +} + +static void __dead2 rcar_system_reset(void) +{ +#if PMIC_ON_BOARD +#if PMIC_LEVEL_MODE + + /* The code of iic for DVFS driver is copied to system ram */ + rcar_bl31_code_copy_to_system_ram(); + +#else /* pulse mode */ + #if (RCAR_GEN3_ULCB==1) + /* Starter Kit */ + cpld_reset_cpu(); + #endif +#endif +#else /* not PMIC_ON_BOARD */ + rcar_pwrc_system_reset(); +#endif + wfi(); + ERROR("RCAR System Reset: operation not handled.\n"); + panic(); +} + +#if !PMIC_ON_BOARD +static int32_t cpu_on_check(uint64_t mpidr) +{ + uint64_t i; + uint64_t j; + uint64_t cpu_count; + uintptr_t reg_PSTR; + uint32_t status; + uint64_t my_cpu; + int32_t rtn; + + const uint64_t cpu_num_in_core[PLATFORM_CLUSTER_COUNT] = { + (uint64_t)PLATFORM_CLUSTER0_CORE_COUNT + }; + const uintptr_t registerPSTR[PLATFORM_CLUSTER_COUNT] = { + RCAR_CA53PSTR + }; + + rtn = 0; + my_cpu = mpidr & ((uint64_t)((MPIDR_CLUSTER_MASK) | (MPIDR_CPU_MASK))); + for (i = 0U; i < ((uint64_t)(PLATFORM_CLUSTER_COUNT)); i++) { + cpu_count = cpu_num_in_core[i]; + reg_PSTR = registerPSTR[i]; + for (j = 0U; j < cpu_count; j++) { + if (my_cpu != ((i * 0x100U) + j)) { + status = mmio_read_32(reg_PSTR) >> (j * 4U); + if ((status & 0x00000003U) == 0U) { + rtn--; + } + } + } + } + return (rtn); + +} +#endif + +/******************************************************************************* + * RCAR handler called to check the validity of the power state parameter. + ******************************************************************************/ +int rcar_validate_power_state(unsigned int power_state) +{ + /* Sanity check the requested state */ + if (psci_get_pstate_type(power_state) == PSTATE_TYPE_STANDBY) { + /* + * It's possible to enter standby only on affinity level 0 + * i.e. a cpu on the rcar. Ignore any other affinity level. + */ + if (psci_get_pstate_pwrlvl(power_state) != PSCI_CPU_PWR_LVL) { + return PSCI_E_INVALID_PARAMS; + } + } else { + /* + * System suspend is only supported via PSCI SYSTEM_SUSPEND. + */ + if (psci_get_pstate_pwrlvl(power_state) == PLAT_MAX_PWR_LVL) { + return PSCI_E_INVALID_PARAMS; + } + } + + /* + * We expect the 'state id' to be zero. + */ + if (psci_get_pstate_id(power_state) != 0U) { + return PSCI_E_INVALID_PARAMS; + } + + return PSCI_E_SUCCESS; +} +#if PMIC_ON_BOARD +unsigned int rcar_get_sys_suspend_power_state(void) +{ + return psci_make_powerstate(0, PSTATE_TYPE_POWERDOWN, + PLATFORM_MAX_AFFLVL); +} +#endif /* PMIC_ON_BOARD */ +/******************************************************************************* + * Export the platform handlers to enable psci to invoke them + ******************************************************************************/ +static const plat_pm_ops_t rcar_plat_pm_ops = { + .affinst_standby = rcar_affinst_standby, + .affinst_on = rcar_affinst_on, + .affinst_off = rcar_affinst_off, + .affinst_suspend = rcar_affinst_suspend, + .affinst_on_finish = rcar_affinst_on_finish, + .affinst_suspend_finish = rcar_affinst_suspend_finish, + .system_off = rcar_system_off, + .system_reset = rcar_system_reset, + .validate_power_state = rcar_validate_power_state, +#if PMIC_ON_BOARD + .get_sys_suspend_power_state = rcar_get_sys_suspend_power_state +#endif /* PMIC_ON_BOARD */ +}; + +/******************************************************************************* + * Export the platform specific power ops & initialize the rcar power controller + ******************************************************************************/ +int platform_setup_pm(const plat_pm_ops_t **plat_ops) +{ + *plat_ops = &rcar_plat_pm_ops; + +#if PMIC_ON_BOARD + rcar_bl31_init_suspend_to_ram(); +#endif /* PMIC_ON_BOARD */ + + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_private.h new file mode 100644 index 0000000..37db28d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_private.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_PRIVATE_H__ +#define RCAR_PRIVATE_H__ + +#include +#include +#include +#include + + +typedef volatile struct mailbox { + unsigned long value + __attribute__((__aligned__(CACHE_WRITEBACK_GRANULE))); +} mailbox_t; + +/******************************************************************************* + * This structure represents the superset of information that is passed to + * BL31 e.g. while passing control to it from BL2 which is bl31_params + * and bl31_plat_params and its elements + ******************************************************************************/ +typedef struct bl2_to_bl31_params_mem { + bl31_params_t bl31_params; + image_info_t bl31_image_info; + image_info_t bl32_image_info; + image_info_t bl33_image_info; + entry_point_info_t bl33_ep_info; + entry_point_info_t bl32_ep_info; + entry_point_info_t bl31_ep_info; +} bl2_to_bl31_params_mem_t; + +#if USE_COHERENT_MEM +/* + * Use this macro to instantiate lock before it is used in below + * rcar_lock_xxx() macros + */ +#define RCAR_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(rcar_lock); + +/* + * These are wrapper macros to the Coherent Memory Bakery Lock API. + */ +#define rcar_lock_init() bakery_lock_init(&rcar_lock) +#define rcar_lock_get() bakery_lock_get(&rcar_lock) +#define rcar_lock_release() bakery_lock_release(&rcar_lock) + + +#else + +/******************************************************************************* + * Constants to specify how many bakery locks this platform implements. These + * are used if the platform chooses not to use coherent memory for bakery lock + * data structures. + ******************************************************************************/ +#define RCAR_MAX_BAKERIES 2 +#define RCAR_PWRC_BAKERY_ID 0 + +/******************************************************************************* + * Definition of structure which holds platform specific per-cpu data. Currently + * it holds only the bakery lock information for each cpu. Constants to + * specify how many bakeries this platform implements and bakery ids are + * specified in rcar_def.h + ******************************************************************************/ +typedef struct rcar_cpu_data { + bakery_info_t pcpu_bakery_info[RCAR_MAX_BAKERIES]; +} rcar_cpu_data_t; + +/* Macro to define the offset of bakery_info_t in rcar_cpu_data_t */ +#define RCAR_CPU_DATA_LOCK_OFFSET __builtin_offsetof\ + (rcar_cpu_data_t, pcpu_bakery_info) + + +/******************************************************************************* + * Helper macros for bakery lock api when using the above rcar_cpu_data_t for + * bakery lock data structures. It assumes that the bakery_info is at the + * beginning of the platform specific per-cpu data. + ******************************************************************************/ +#define rcar_lock_init(_lock_arg) /* No init required */ +#define rcar_lock_get(_lock_arg) bakery_lock_get(_lock_arg, \ + CPU_DATA_PLAT_PCPU_OFFSET + \ + RCAR_CPU_DATA_LOCK_OFFSET) +#define rcar_lock_release(_lock_arg) bakery_lock_release(_lock_arg, \ + CPU_DATA_PLAT_PCPU_OFFSET + \ + RCAR_CPU_DATA_LOCK_OFFSET) + +/* + * Ensure that the size of the RCAR specific per-cpu data structure and the size + * of the memory allocated in generic per-cpu data for the platform are the same. + */ +CASSERT(PLAT_PCPU_DATA_SIZE == sizeof(rcar_cpu_data_t), \ + rcar_pcpu_data_size_mismatch); + +#endif /* __USE_COHERENT_MEM__ */ + +/******************************************************************************* + * Function and variable prototypes + ******************************************************************************/ +void rcar_configure_mmu_el1(unsigned long total_base, + unsigned long total_size, + unsigned long ro_start, + unsigned long ro_limit +#if USE_COHERENT_MEM + , unsigned long coh_start, + unsigned long coh_limit +#endif + ); +void rcar_configure_mmu_el3(unsigned long total_base, + unsigned long total_size, + unsigned long ro_start, + unsigned long ro_limit +#if USE_COHERENT_MEM + , unsigned long coh_start, + unsigned long coh_limit +#endif + ); + +void rcar_cci_init(void); +void rcar_cci_enable(void); +void rcar_cci_disable(void); + +/* Declarations for rcar_topology.c */ +void rcar_setup_topology(void); + +/* Gets the SPR for BL32 entry */ +uint32_t rcar_get_spsr_for_bl32_entry(void); + +/* Gets the SPSR for BL33 entry */ +uint32_t rcar_get_spsr_for_bl33_entry(void); + +/* Prototype function for power management */ +void rcar_affinst_standby(unsigned int power_state); +int rcar_affinst_on(unsigned long mpidr, unsigned long sec_entrypoint, + unsigned int afflvl, unsigned int state); +void rcar_affinst_off(unsigned int afflvl, unsigned int state); +void rcar_affinst_suspend(unsigned long sec_entrypoint, unsigned int afflvl, + unsigned int state); +void rcar_affinst_on_finish(unsigned int afflvl, unsigned int state); +void rcar_affinst_suspend_finish(unsigned int afflvl, unsigned int state); +int rcar_validate_power_state(unsigned int power_state); + +/* Function prototypes for read and write to the CPU system registers */ +void iciallu(void); + +#endif /* RCAR_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_topology.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_topology.c new file mode 100644 index 0000000..8ea33f1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_topology.c @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +/* TODO: Reusing psci error codes & state information. Get our own! */ +#include +#include "drivers/pwrc/rcar_pwrc.h" + +/* We treat '255' as an invalid affinity instance */ +#define AFFINST_INVAL 0xff + +typedef struct affinity_info { + unsigned char sibling; + unsigned char child; + unsigned char state; + unsigned int data; +} affinity_info_t; + +/******************************************************************************* + * The following two data structures store the topology tree for the rcar. There + * is a separate array for each affinity level i.e. cpus and clusters. The child + * and sibling references allow traversal inside and in between the two arrays. + ******************************************************************************/ +static affinity_info_t rcar_aff1_topology_map[PLATFORM_CLUSTER_COUNT]; +static affinity_info_t rcar_aff0_topology_map[PLATFORM_CORE_COUNT]; + + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform to allow the former to detect the platform + * topology. psci queries the platform to determine how many affinity instances + * are present at a particular level for a given mpidr e.g. consider a dual + * cluster platform where each cluster has 4 cpus. A call to this function with + * (0, 0x100) will return the number of cpus implemented under cluster 1 i.e. 4. + * Similarly a call with (1, 0x100) will return 2 i.e. the number of clusters. + * This is 'cause we are effectively asking how many affinity level 1 instances + * are implemented under affinity level 2 instance 0. + ******************************************************************************/ +unsigned int plat_get_aff_count(unsigned int aff_lvl, + unsigned long mpidr) +{ + unsigned int aff_count = 1, ctr; + unsigned char parent_aff_id; + + switch (aff_lvl) { + case 3: + case 2: + /* + * Report that we implement a single instance of + * affinity levels 2 & 3 which are AFF_ABSENT + */ + break; + case 1: + /* Fetch the starting index in the aff1 array */ + for (ctr = 0; + rcar_aff1_topology_map[ctr].sibling != AFFINST_INVAL; + ctr = rcar_aff1_topology_map[ctr].sibling) { + aff_count++; + } + + break; + case 0: + /* Panic if the cluster id is anything apart from 0 or 1 */ + parent_aff_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + if (PLATFORM_CLUSTER_COUNT <= parent_aff_id) { + panic(); + } + + /* Fetch the starting index in the aff0 array */ + for (ctr = rcar_aff1_topology_map[parent_aff_id].child; + rcar_aff0_topology_map[ctr].sibling != AFFINST_INVAL; + ctr = rcar_aff0_topology_map[ctr].sibling) { + aff_count++; + } + + break; + default: + panic(); + break; + } + + return aff_count; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform to allow the former to detect the state of a + * affinity instance in the platform topology. psci queries the platform to + * determine whether an affinity instance is present or absent. This caters for + * topologies where an intermediate affinity level instance is missing e.g. + * consider a platform which implements a single cluster with 4 cpus and there + * is another cpu sitting directly on the interconnect along with the cluster. + * The mpidrs of the cluster would range from 0x0-0x3. The mpidr of the single + * cpu would be 0x100 to highlight that it does not belong to cluster 0. Cluster + * 1 is however missing but needs to be accounted to reach this single cpu in + * the topology tree. Hence it will be marked as PSCI_AFF_ABSENT. This is not + * applicable to the RCAR but depicted as an example. + ******************************************************************************/ +unsigned int plat_get_aff_state(unsigned int aff_lvl, + unsigned long mpidr) +{ + unsigned int aff_state = PSCI_AFF_ABSENT, idx; + idx = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + + switch (aff_lvl) { + case 3: + case 2: + /* Report affinity levels 2 & 3 as absent */ + break; + case 1: + aff_state = rcar_aff1_topology_map[idx].state; + break; + case 0: + /* + * First get start index of the aff0 in its array & then add + * to it the affinity id that we want the state of + */ + idx = rcar_aff1_topology_map[idx].child; + idx += (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + aff_state = rcar_aff0_topology_map[idx].state; + break; + default: + panic(); + break; + } + + return aff_state; +} + +/******************************************************************************* + * This function populates the RCAR specific topology information depending upon + * the RCAR flavour its running on. We construct all the mpidrs we can handle + * and rely on the PRR to flag absent cpus when their status is queried. + ******************************************************************************/ +void rcar_setup_topology(void) +{ + unsigned char aff0, aff1, aff_state, aff0_offset = 0; + unsigned long mpidr; + + for (aff1 = 0; aff1 < PLATFORM_CLUSTER_COUNT; aff1++) { + + rcar_aff1_topology_map[aff1].child = aff0_offset; + rcar_aff1_topology_map[aff1].sibling = aff1 + 1; + + for (aff0 = 0; aff0 < PLATFORM_MAX_CPUS_PER_CLUSTER; aff0++) { + + mpidr = aff1 << MPIDR_AFF1_SHIFT; + mpidr |= aff0 << MPIDR_AFF0_SHIFT; + + if (rcar_pwrc_status(mpidr) != RCAR_INVALID) { + /* + * Presence of even a single aff0 indicates + * presence of parent aff1 on the RCAR. + */ + aff_state = PSCI_AFF_PRESENT; + rcar_aff1_topology_map[aff1].state = + PSCI_AFF_PRESENT; + } else { + aff_state = PSCI_AFF_ABSENT; + } + + rcar_aff0_topology_map[aff0_offset].child = AFFINST_INVAL; + rcar_aff0_topology_map[aff0_offset].state = aff_state; + rcar_aff0_topology_map[aff0_offset].sibling = + aff0_offset + 1; + + /* Increment the absolute number of aff0s traversed */ + aff0_offset++; + } + + /* Tie-off the last aff0 sibling to -1 to avoid overflow */ + rcar_aff0_topology_map[aff0_offset - 1].sibling = AFFINST_INVAL; + } + + /* Tie-off the last aff1 sibling to AFFINST_INVAL to avoid overflow */ + rcar_aff1_topology_map[aff1 - 1].sibling = AFFINST_INVAL; + +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_version.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_version.h new file mode 100644 index 0000000..a063d89 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/renesas/rcar/rcar_version.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2015-2018, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RCAR_VERSION_H__ +#define RCAR_VERSION_H__ + +#include + +#define VERSION_OF_RENESAS "1.0.0" +#define VERSION_OF_RENESAS_MAXLEN (128) + +extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]; + +#endif /* RCAR_VERSION_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/aarch64/plat_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/aarch64/plat_helpers.S new file mode 100644 index 0000000..d06d4cb --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/aarch64/plat_helpers.S @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + .globl cpuson_entry_point + .globl cpuson_flags + .globl platform_cpu_warmboot + .globl plat_secondary_cold_boot_setup + .globl plat_report_exception + .globl platform_is_primary_cpu + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_my_core_pos + .globl plat_reset_handler + + /* + * void plat_reset_handler(void); + * + * Determine the SOC type and call the appropriate reset + * handler. + * + */ +func plat_reset_handler + mrs x0, midr_el1 + ubfx x0, x0, MIDR_PN_SHIFT, #12 + cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK) + b.eq handler_a72 + b handler_end +handler_a72: + /* + * This handler does the following: + * Set the L2 Data RAM latency for Cortex-A72. + * Set the L2 Tag RAM latency to for Cortex-A72. + */ + mov x0, #((2 << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ + (0x1 << 5)) + msr L2CTLR_EL1, x0 + isb +handler_end: + ret +endfunc plat_reset_handler + +func plat_my_core_pos + mrs x0, mpidr_el1 + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT + ret +endfunc plat_my_core_pos + + /* -------------------------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * -------------------------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + /* rk3368 does not do cold boot for secondary CPU */ +cb_panic: + b cb_panic +endfunc plat_secondary_cold_boot_setup + +func platform_is_primary_cpu + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #PLAT_RK_PRIMARY_CPU + cset x0, eq + ret +endfunc platform_is_primary_cpu + + /* -------------------------------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0, x1, x2 + * -------------------------------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, PLAT_RK_UART_BASE + mov_imm x1, PLAT_RK_UART_CLOCK + mov_imm x2, PLAT_RK_UART_BAUDRATE + b console_core_init +endfunc plat_crash_console_init + + /* -------------------------------------------------------------------- + * int plat_crash_console_putc(void) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * -------------------------------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, PLAT_RK_UART_BASE + b console_core_putc +endfunc plat_crash_console_putc + + /* -------------------------------------------------------------------- + * void platform_cpu_warmboot (void); + * cpus online or resume enterpoint + * -------------------------------------------------------------------- + */ + .align 16 +func platform_cpu_warmboot + mrs x0, MPIDR_EL1 + and x19, x0, #MPIDR_CPU_MASK + and x20, x0, #MPIDR_CLUSTER_MASK + mov x0, x20 + func_rockchip_clst_warmboot + /* -------------------------------------------------------------------- + * big cluster id is 1 + * big cores id is from 0-3, little cores id 4-7 + * -------------------------------------------------------------------- + */ + add x21, x19, x20, lsr #PLAT_RK_CLST_TO_CPUID_SHIFT + /* -------------------------------------------------------------------- + * get per cpuup flag + * -------------------------------------------------------------------- + */ + adr x4, cpuson_flags + add x4, x4, x21, lsl #2 + ldr w1, [x4] + /* -------------------------------------------------------------------- + * check cpuon reason + * -------------------------------------------------------------------- + */ + cmp w1, PMU_CPU_AUTO_PWRDN + b.eq boot_entry + cmp w1, PMU_CPU_HOTPLUG + b.eq boot_entry + /* -------------------------------------------------------------------- + * If the boot core cpuson_flags or cpuson_entry_point is not + * expection. force the core into wfe. + * -------------------------------------------------------------------- + */ +wfe_loop: + wfe + b wfe_loop +boot_entry: + str wzr, [x4] + /* -------------------------------------------------------------------- + * get per cpuup boot addr + * -------------------------------------------------------------------- + */ + adr x5, cpuson_entry_point + ldr x2, [x5, x21, lsl #3] + br x2 +endfunc platform_cpu_warmboot + + /* -------------------------------------------------------------------- + * Per-CPU Secure entry point - resume or power up + * -------------------------------------------------------------------- + */ + .section tzfw_coherent_mem, "a" + .align 3 +cpuson_entry_point: + .rept PLATFORM_CORE_COUNT + .quad 0 + .endr +cpuson_flags: + .rept PLATFORM_CORE_COUNT + .word 0 + .endr +rockchip_clst_warmboot_data diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/aarch64/platform_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/aarch64/platform_common.c new file mode 100644 index 0000000..40cd29e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/aarch64/platform_common.c @@ -0,0 +1,108 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef PLAT_RK_CCI_BASE +static const int cci_map[] = { + PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX, + PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX +}; +#endif + +/****************************************************************************** + * Macro generating the code for the function setting up the pagetables as per + * the platform memory map & initialize the mmu, for the given exception level + ******************************************************************************/ +#define DEFINE_CONFIGURE_MMU_EL(_el) \ + void plat_configure_mmu_el ## _el(unsigned long total_base, \ + unsigned long total_size, \ + unsigned long ro_start, \ + unsigned long ro_limit, \ + unsigned long coh_start, \ + unsigned long coh_limit) \ + { \ + mmap_add_region(total_base, total_base, \ + total_size, \ + MT_MEMORY | MT_RW | MT_SECURE); \ + mmap_add_region(ro_start, ro_start, \ + ro_limit - ro_start, \ + MT_MEMORY | MT_RO | MT_SECURE); \ + mmap_add_region(coh_start, coh_start, \ + coh_limit - coh_start, \ + MT_DEVICE | MT_RW | MT_SECURE); \ + mmap_add(plat_rk_mmap); \ + init_xlat_tables(); \ + \ + enable_mmu_el ## _el(0); \ + } + +/* Define EL3 variants of the function initialising the MMU */ +DEFINE_CONFIGURE_MMU_EL(3) + +unsigned int plat_get_syscnt_freq2(void) +{ + return SYS_COUNTER_FREQ_IN_TICKS; +} + +void plat_cci_init(void) +{ +#ifdef PLAT_RK_CCI_BASE + /* Initialize CCI driver */ + cci_init(PLAT_RK_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); +#endif +} + +void plat_cci_enable(void) +{ + /* + * Enable CCI coherency for this cluster. + * No need for locks as no other cpu is active at the moment. + */ +#ifdef PLAT_RK_CCI_BASE + cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); +#endif +} + +void plat_cci_disable(void) +{ +#ifdef PLAT_RK_CCI_BASE + cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); +#endif +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/bl31_plat_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/bl31_plat_setup.c new file mode 100644 index 0000000..47a245a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/bl31_plat_setup.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/******************************************************************************* + * Declarations of linker defined symbols which will help us find the layout + * of trusted SRAM + ******************************************************************************/ +unsigned long __RO_START__; +unsigned long __RO_END__; + +unsigned long __COHERENT_RAM_START__; +unsigned long __COHERENT_RAM_END__; + +/* + * The next 2 constants identify the extents of the code & RO data region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. + */ +#define BL31_RO_BASE (unsigned long)(&__RO_START__) +#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) + +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) + +static entry_point_info_t bl32_ep_info; +static entry_point_info_t bl33_ep_info; + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; + + /* None of the images on this platform can have 0x0 as the entrypoint */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +/******************************************************************************* + * Perform any BL3-1 early platform setup. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they + * are lost (potentially). This needs to be done before the MMU is initialized + * so that the memory layout can be used while creating page tables. + * BL2 has flushed this information to memory, so we are guaranteed to pick up + * good data. + ******************************************************************************/ +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +{ + console_init(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK, + PLAT_RK_UART_BAUDRATE); + + VERBOSE("bl31_setup\n"); + + /* Passing a NULL context is a critical programming error */ + assert(from_bl2); + + assert(from_bl2->h.type == PARAM_BL31); + assert(from_bl2->h.version >= VERSION_1); + + bl32_ep_info = *from_bl2->bl32_ep_info; + bl33_ep_info = *from_bl2->bl33_ep_info; + + /* + * The code for resuming cpu from suspend must be excuted in pmusram. + * Copy the code into pmusram. + */ + plat_rockchip_pmusram_prepare(); + + /* there may have some board sepcific message need to initialize */ + params_early_setup(plat_params_from_bl2); +} + +/******************************************************************************* + * Perform any BL3-1 platform setup code + ******************************************************************************/ +void bl31_platform_setup(void) +{ + generic_delay_timer_init(); + plat_rockchip_soc_init(); + + /* Initialize the gic cpu and distributor interfaces */ + plat_rockchip_gic_driver_init(); + plat_rockchip_gic_init(); + plat_rockchip_pmu_init(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the mmu in a quick and dirty way. + ******************************************************************************/ +void bl31_plat_arch_setup(void) +{ + plat_cci_init(); + plat_cci_enable(); + plat_configure_mmu_el3(BL31_RO_BASE, + (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE), + BL31_RO_BASE, + BL31_RO_LIMIT, + BL31_COHERENT_RAM_BASE, + BL31_COHERENT_RAM_LIMIT); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/drivers/pmu/pmu_com.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/drivers/pmu/pmu_com.h new file mode 100644 index 0000000..a6d3186 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/drivers/pmu/pmu_com.h @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PMU_COM_H__ +#define __PMU_COM_H__ + +/* + * Use this macro to instantiate lock before it is used in below + * rockchip_pd_lock_xxx() macros + */ +DECLARE_BAKERY_LOCK(rockchip_pd_lock); + +/* + * These are wrapper macros to the powe domain Bakery Lock API. + */ +#define rockchip_pd_lock_init() bakery_lock_init(&rockchip_pd_lock) +#define rockchip_pd_lock_get() bakery_lock_get(&rockchip_pd_lock) +#define rockchip_pd_lock_rls() bakery_lock_release(&rockchip_pd_lock) + +/***************************************************************************** + * power domain on or off + *****************************************************************************/ +enum pmu_pd_state { + pmu_pd_on = 0, + pmu_pd_off = 1 +}; + +#pragma weak plat_ic_get_pending_interrupt_id +#pragma weak pmu_power_domain_ctr +#pragma weak check_cpu_wfie + +static inline uint32_t pmu_power_domain_st(uint32_t pd) +{ + uint32_t pwrdn_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd); + + if (pwrdn_st) + return pmu_pd_off; + else + return pmu_pd_on; +} + +static int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state) +{ + uint32_t val; + uint32_t loop = 0; + int ret = 0; + + rockchip_pd_lock_get(); + + val = mmio_read_32(PMU_BASE + PMU_PWRDN_CON); + if (pd_state == pmu_pd_off) + val |= BIT(pd); + else + val &= ~BIT(pd); + + mmio_write_32(PMU_BASE + PMU_PWRDN_CON, val); + dsb(); + + while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) { + udelay(1); + loop++; + } + + if (pmu_power_domain_st(pd) != pd_state) { + WARN("%s: %d, %d, error!\n", __func__, pd, pd_state); + ret = -EINVAL; + } + + rockchip_pd_lock_rls(); + + return ret; +} + +static int check_cpu_wfie(uint32_t cpu_id, uint32_t wfie_msk) +{ + uint32_t cluster_id, loop = 0; + + if (cpu_id >= PLATFORM_CLUSTER0_CORE_COUNT) { + cluster_id = 1; + cpu_id -= PLATFORM_CLUSTER0_CORE_COUNT; + } else { + cluster_id = 0; + } + + if (cluster_id) + wfie_msk <<= (clstb_cpu_wfe + cpu_id); + else + wfie_msk <<= (clstl_cpu_wfe + cpu_id); + + while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & wfie_msk) && + (loop < CHK_CPU_LOOP)) { + udelay(1); + loop++; + } + + if ((mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & wfie_msk) == 0) { + WARN("%s: %d, %d, %d, error!\n", __func__, + cluster_id, cpu_id, wfie_msk); + return -EINVAL; + } + + return 0; +} + +#endif /* __PMU_COM_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/include/plat_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/include/plat_macros.S new file mode 100644 index 0000000..dcc959f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/include/plat_macros.S @@ -0,0 +1,142 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __ROCKCHIP_PLAT_MACROS_S__ +#define __ROCKCHIP_PLAT_MACROS_S__ + +#include +#include +#include +#include +#include + +.section .rodata.gic_reg_name, "aS" +/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ +gicc_regs: + .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" + +/* Applicable only to GICv3 with SRE enabled */ +icc_regs: + .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" + +/* Registers common to both GICv2 and GICv3 */ +gicd_pend_reg: + .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ + " Offset:\t\t\tvalue\n" +newline: + .asciz "\n" +spacer: + .asciz ":\t\t0x" + +.section .rodata.cci_reg_name, "aS" +cci_iface_regs: + .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" + + /* --------------------------------------------- + * The below utility macro prints out relevant GIC + * and CCI registers whenever an unhandled + * exception is taken in BL31. + * Expects: GICD base in x16, GICC base in x17 + * Clobbers: x0 - x10, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + + mov_imm x16, PLAT_RK_GICD_BASE + mov_imm x17, PLAT_RK_GICC_BASE + + /* Check for GICv3 system register access */ + mrs x7, id_aa64pfr0_el1 + ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH + cmp x7, #1 + b.ne print_gicv2 + + /* Check for SRE enable */ + mrs x8, ICC_SRE_EL3 + tst x8, #ICC_SRE_SRE_BIT + b.eq print_gicv2 + + /* Load the icc reg list to x6 */ + adr x6, icc_regs + /* Load the icc regs to gp regs used by str_in_crash_buf_print */ + mrs x8, ICC_HPPIR0_EL1 + mrs x9, ICC_HPPIR1_EL1 + mrs x10, ICC_CTLR_EL3 + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + b print_gic_common + +print_gicv2: + /* Load the gicc reg list to x6 */ + adr x6, gicc_regs + /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ + ldr w8, [x17, #GICC_HPPIR] + ldr w9, [x17, #GICC_AHPPIR] + ldr w10, [x17, #GICC_CTLR] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print + +print_gic_common: + /* Print the GICD_ISPENDR regs */ + add x7, x16, #GICD_ISPENDR + adr x4, gicd_pend_reg + bl asm_print_str +gicd_ispendr_loop: + sub x4, x7, x16 + cmp x4, #0x280 + b.eq exit_print_gic_regs + bl asm_print_hex + + adr x4, spacer + bl asm_print_str + + ldr x4, [x7], #8 + bl asm_print_hex + + adr x4, newline + bl asm_print_str + b gicd_ispendr_loop +exit_print_gic_regs: + +#if PLATFORM_CLUSTER_COUNT > 1 + adr x6, cci_iface_regs + /* Store in x7 the base address of the first interface */ + mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX)) + ldr w8, [x7, #SNOOP_CTRL_REG] + /* Store in x7 the base address of the second interface */ + mov_imm x7, (PLAT_RK_CCI_BASE + SLAVE_IFACE_OFFSET( \ + PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX)) + ldr w9, [x7, #SNOOP_CTRL_REG] + /* Store to the crash buf and print to console */ + bl str_in_crash_buf_print +#endif + .endm + +#endif /* __ROCKCHIP_PLAT_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/include/plat_params.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/include/plat_params.h new file mode 100644 index 0000000..8c64796 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/include/plat_params.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_PARAMS_H__ +#define __PLAT_PARAMS_H__ + +#include + +/* + * We defined several plat parameter structs for BL2 to pass platform related + * parameters to Rockchip BL31 platform code. All plat parameters start with + * a common header, which has a type field to indicate the parameter type, and + * a next pointer points to next parameter. If the parameter is the last one in + * the list, next pointer will points to NULL. After the header comes the + * variable-sized members that describe the parameter. The picture below shows + * how the parameters are kept in memory. + * + * head of list ---> +----------------+ --+ + * | type | | + * +----------------+ |--> struct bl31_plat_param + * +----| next | | + * | +----------------+ --+ + * | | parameter data | + * | +----------------+ + * | + * +--> +----------------+ --+ + * | type | | + * +----------------+ |--> struct bl31_plat_param + * NULL <---| next | | + * +----------------+ --+ + * | parameter data | + * +----------------+ + * + * Note: The SCTLR_EL3.A bit (Alignment fault check enable) of ARM TF is set, + * so be sure each parameter struct starts on 64-bit aligned address. If not, + * alignment fault will occur during accessing its data member. + */ + +#define BL31_GPIO_DIR_OUT 0 +#define BL31_GPIO_DIR_IN 1 + +#define BL31_GPIO_LEVEL_LOW 0 +#define BL31_GPIO_LEVEL_HIGH 1 + +#define BL31_GPIO_PULL_NONE 0 +#define BL31_GPIO_PULL_UP 1 +#define BL31_GPIO_PULL_DOWN 2 + +/* param type */ +enum { + PARAM_NONE = 0, + PARAM_RESET, + PARAM_POWEROFF, + PARAM_SUSPEND_GPIO, + PARAM_SUSPEND_APIO, +}; + +struct apio_info { + uint8_t apio1 : 1; + uint8_t apio2 : 1; + uint8_t apio3 : 1; + uint8_t apio4 : 1; + uint8_t apio5 : 1; +}; + +struct gpio_info { + uint8_t polarity; + uint8_t direction; + uint8_t pull_mode; + uint32_t index; +}; + +/* common header for all plat parameter type */ +struct bl31_plat_param { + uint64_t type; + void *next; +}; + +struct bl31_gpio_param { + struct bl31_plat_param h; + struct gpio_info gpio; +}; + +struct bl31_apio_param { + struct bl31_plat_param h; + struct apio_info apio; +}; + +#endif /* __PLAT_PARAMS_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/include/plat_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/include/plat_private.h new file mode 100644 index 0000000..ad01266 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/include/plat_private.h @@ -0,0 +1,148 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_PRIVATE_H__ +#define __PLAT_PRIVATE_H__ + +#ifndef __ASSEMBLY__ +#include +#include +#include +#include + +/****************************************************************************** + * For rockchip socs pm ops + ******************************************************************************/ +struct rockchip_pm_ops_cb { + int (*cores_pwr_dm_on)(unsigned long mpidr, uint64_t entrypoint); + int (*cores_pwr_dm_off)(void); + int (*cores_pwr_dm_on_finish)(void); + int (*cores_pwr_dm_suspend)(void); + int (*cores_pwr_dm_resume)(void); + /* hlvl is used for clusters or system level */ + int (*hlvl_pwr_dm_suspend)(uint32_t lvl, plat_local_state_t lvl_state); + int (*hlvl_pwr_dm_resume)(uint32_t lvl, plat_local_state_t lvl_state); + int (*hlvl_pwr_dm_off)(uint32_t lvl, plat_local_state_t lvl_state); + int (*hlvl_pwr_dm_on_finish)(uint32_t lvl, + plat_local_state_t lvl_state); + int (*sys_pwr_dm_suspend)(void); + int (*sys_pwr_dm_resume)(void); + void (*sys_gbl_soft_reset)(void) __dead2; + void (*system_off)(void) __dead2; + void (*sys_pwr_down_wfi)(const psci_power_state_t *state_info) __dead2; +}; + +/****************************************************************************** + * The register have write-mask bits, it is mean, if you want to set the bits, + * you needs set the write-mask bits at the same time, + * The write-mask bits is in high 16-bits. + * The fllowing macro definition helps access write-mask bits reg efficient! + ******************************************************************************/ +#define REG_MSK_SHIFT 16 + +#ifndef BIT +#define BIT(nr) (1 << (nr)) +#endif + +#ifndef WMSK_BIT +#define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) +#endif + +/* set one bit with write mask */ +#ifndef BIT_WITH_WMSK +#define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) +#endif + +#ifndef BITS_SHIFT +#define BITS_SHIFT(bits, shift) (bits << (shift)) +#endif + +#ifndef BITS_WITH_WMASK +#define BITS_WITH_WMASK(bits, msk, shift)\ + (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT))) +#endif + +/****************************************************************************** + * Function and variable prototypes + *****************************************************************************/ +void plat_configure_mmu_el3(unsigned long total_base, + unsigned long total_size, + unsigned long, + unsigned long, + unsigned long, + unsigned long); + +void plat_cci_init(void); +void plat_cci_enable(void); +void plat_cci_disable(void); + +void plat_delay_timer_init(void); + +void params_early_setup(void *plat_params_from_bl2); + +void plat_rockchip_gic_driver_init(void); +void plat_rockchip_gic_init(void); +void plat_rockchip_gic_cpuif_enable(void); +void plat_rockchip_gic_cpuif_disable(void); +void plat_rockchip_gic_pcpu_init(void); + +void plat_rockchip_pmusram_prepare(void); +void plat_rockchip_pmu_init(void); +void plat_rockchip_soc_init(void); +void plat_setup_rockchip_pm_ops(struct rockchip_pm_ops_cb *ops); +uintptr_t plat_get_sec_entrypoint(void); + +void platform_cpu_warmboot(void); + +struct gpio_info *plat_get_rockchip_gpio_reset(void); +struct gpio_info *plat_get_rockchip_gpio_poweroff(void); +struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count); +struct apio_info *plat_get_rockchip_suspend_apio(void); +void plat_rockchip_gpio_init(void); + +extern const unsigned char rockchip_power_domain_tree_desc[]; + +extern void *pmu_cpuson_entrypoint_start; +extern void *pmu_cpuson_entrypoint_end; +extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT]; +extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; + +extern const mmap_region_t plat_rk_mmap[]; +#endif /* __ASSEMBLY__ */ + +/****************************************************************************** + * cpu up status + * The bits of macro value is not more than 12 bits for cmp instruction! + ******************************************************************************/ +#define PMU_CPU_HOTPLUG 0xf00 +#define PMU_CPU_AUTO_PWRDN 0xf0 +#define PMU_CLST_RET 0xa5 + +#endif /* __PLAT_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/include/rockchip_sip_svc.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/include/rockchip_sip_svc.h new file mode 100644 index 0000000..9e31082 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/include/rockchip_sip_svc.h @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ROCKCHIP_SIP_SVC_H__ +#define __ROCKCHIP_SIP_SVC_H__ + +/* SMC function IDs for SiP Service queries */ +#define SIP_SVC_CALL_COUNT 0x8200ff00 +#define SIP_SVC_UID 0x8200ff01 +#define SIP_SVC_VERSION 0x8200ff03 + +/* rockchip SiP Service Calls version numbers */ +#define RK_SIP_SVC_VERSION_MAJOR 0x0 +#define RK_SIP_SVC_VERSION_MINOR 0x1 + +/* Number of ROCKCHIP SiP Calls implemented */ +#define RK_COMMON_SIP_NUM_CALLS 0x3 + +enum { + RK_SIP_E_SUCCESS = 0, + RK_SIP_E_INVALID_PARAM = -1 +}; + +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/params_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/params_setup.c new file mode 100644 index 0000000..646c1e1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/params_setup.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct gpio_info param_reset; +static struct gpio_info param_poweroff; +static struct bl31_apio_param param_apio; +static struct gpio_info *rst_gpio; +static struct gpio_info *poweroff_gpio; +static struct gpio_info suspend_gpio[10]; +uint32_t suspend_gpio_cnt; +static struct apio_info *suspend_apio; + +struct gpio_info *plat_get_rockchip_gpio_reset(void) +{ + return rst_gpio; +} + +struct gpio_info *plat_get_rockchip_gpio_poweroff(void) +{ + return poweroff_gpio; +} + +struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count) +{ + *count = suspend_gpio_cnt; + + return &suspend_gpio[0]; +} + +struct apio_info *plat_get_rockchip_suspend_apio(void) +{ + return suspend_apio; +} + +void params_early_setup(void *plat_param_from_bl2) +{ + struct bl31_plat_param *bl2_param; + struct bl31_gpio_param *gpio_param; + + /* keep plat parameters for later processing if need */ + bl2_param = (struct bl31_plat_param *)plat_param_from_bl2; + while (bl2_param) { + switch (bl2_param->type) { + case PARAM_RESET: + gpio_param = (struct bl31_gpio_param *)bl2_param; + memcpy(¶m_reset, &gpio_param->gpio, + sizeof(struct gpio_info)); + rst_gpio = ¶m_reset; + break; + case PARAM_POWEROFF: + gpio_param = (struct bl31_gpio_param *)bl2_param; + memcpy(¶m_poweroff, &gpio_param->gpio, + sizeof(struct gpio_info)); + poweroff_gpio = ¶m_poweroff; + break; + case PARAM_SUSPEND_GPIO: + if (suspend_gpio_cnt >= ARRAY_SIZE(suspend_gpio)) { + ERROR("exceed support suspend gpio number\n"); + break; + } + gpio_param = (struct bl31_gpio_param *)bl2_param; + memcpy(&suspend_gpio[suspend_gpio_cnt], + &gpio_param->gpio, + sizeof(struct gpio_info)); + suspend_gpio_cnt++; + break; + case PARAM_SUSPEND_APIO: + memcpy(¶m_apio, bl2_param, + sizeof(struct bl31_apio_param)); + suspend_apio = ¶m_apio.apio; + break; + default: + ERROR("not expected type found %ld\n", + bl2_param->type); + break; + } + bl2_param = bl2_param->next; + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/plat_pm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/plat_pm.c new file mode 100644 index 0000000..d28100d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/plat_pm.c @@ -0,0 +1,368 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Macros to read the rk power domain state */ +#define RK_CORE_PWR_STATE(state) \ + ((state)->pwr_domain_state[MPIDR_AFFLVL0]) +#define RK_CLUSTER_PWR_STATE(state) \ + ((state)->pwr_domain_state[MPIDR_AFFLVL1]) +#define RK_SYSTEM_PWR_STATE(state) \ + ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) + +static uintptr_t rockchip_sec_entrypoint; + +static struct rockchip_pm_ops_cb *rockchip_ops; + +/******************************************************************************* + * Rockchip standard platform handler called to check the validity of the power + * state parameter. + ******************************************************************************/ +int rockchip_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int pstate = psci_get_pstate_type(power_state); + int pwr_lvl = psci_get_pstate_pwrlvl(power_state); + int i; + + assert(req_state); + + if (pwr_lvl > PLAT_MAX_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + /* Sanity check the requested state */ + if (pstate == PSTATE_TYPE_STANDBY) { + /* + * It's probably to enter standby only on power level 0 + * ignore any other power level. + */ + if (pwr_lvl != MPIDR_AFFLVL0) + return PSCI_E_INVALID_PARAMS; + + req_state->pwr_domain_state[MPIDR_AFFLVL0] = + PLAT_MAX_RET_STATE; + } else { + for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) + req_state->pwr_domain_state[i] = + PLAT_MAX_OFF_STATE; + + for (i = (pwr_lvl + 1); i <= PLAT_MAX_PWR_LVL; i++) + req_state->pwr_domain_state[i] = + PLAT_MAX_RET_STATE; + } + + /* We expect the 'state id' to be zero */ + if (psci_get_pstate_id(power_state)) + return PSCI_E_INVALID_PARAMS; + + return PSCI_E_SUCCESS; +} + +void rockchip_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + int i; + + for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) + req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; +} + +/******************************************************************************* + * RockChip handler called when a CPU is about to enter standby. + ******************************************************************************/ +void rockchip_cpu_standby(plat_local_state_t cpu_state) +{ + unsigned int scr; + + assert(cpu_state == PLAT_MAX_RET_STATE); + + scr = read_scr_el3(); + /* Enable PhysicalIRQ bit for NS world to wake the CPU */ + write_scr_el3(scr | SCR_IRQ_BIT); + isb(); + dsb(); + wfi(); + + /* + * Restore SCR to the original value, synchronisation of scr_el3 is + * done by eret while el3_exit to save some execution cycles. + */ + write_scr_el3(scr); +} + +/******************************************************************************* + * RockChip handler called when a power domain is about to be turned on. The + * mpidr determines the CPU to be turned on. + ******************************************************************************/ +int rockchip_pwr_domain_on(u_register_t mpidr) +{ + if (rockchip_ops && rockchip_ops->cores_pwr_dm_on) + rockchip_ops->cores_pwr_dm_on(mpidr, rockchip_sec_entrypoint); + + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * RockChip handler called when a power domain is about to be turned off. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void rockchip_pwr_domain_off(const psci_power_state_t *target_state) +{ + uint32_t lvl; + plat_local_state_t lvl_state; + + assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); + + plat_rockchip_gic_cpuif_disable(); + + if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) + plat_cci_disable(); + + if (!rockchip_ops || !rockchip_ops->cores_pwr_dm_off) + return; + + rockchip_ops->cores_pwr_dm_off(); + + if (!rockchip_ops->hlvl_pwr_dm_off) + return; + + for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { + lvl_state = target_state->pwr_domain_state[lvl]; + rockchip_ops->hlvl_pwr_dm_off(lvl, lvl_state); + } +} + +/******************************************************************************* + * RockChip handler called when a power domain is about to be suspended. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void rockchip_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + uint32_t lvl; + plat_local_state_t lvl_state; + + if (RK_CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) + return; + + if (rockchip_ops) { + if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE && + rockchip_ops->sys_pwr_dm_suspend) { + rockchip_ops->sys_pwr_dm_suspend(); + } else if (rockchip_ops->cores_pwr_dm_suspend) { + rockchip_ops->cores_pwr_dm_suspend(); + } + } + + /* Prevent interrupts from spuriously waking up this cpu */ + plat_rockchip_gic_cpuif_disable(); + + /* Perform the common cluster specific operations */ + if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) + plat_cci_disable(); + + if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) + return; + + if (!rockchip_ops || !rockchip_ops->hlvl_pwr_dm_suspend) + return; + + for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { + lvl_state = target_state->pwr_domain_state[lvl]; + rockchip_ops->hlvl_pwr_dm_suspend(lvl, lvl_state); + } +} + +/******************************************************************************* + * RockChip handler called when a power domain has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. + ******************************************************************************/ +void rockchip_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + uint32_t lvl; + plat_local_state_t lvl_state; + + assert(RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE); + + if (!rockchip_ops) + goto comm_finish; + + if (rockchip_ops->hlvl_pwr_dm_on_finish) { + for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { + lvl_state = target_state->pwr_domain_state[lvl]; + rockchip_ops->hlvl_pwr_dm_on_finish(lvl, lvl_state); + } + } + + if (rockchip_ops->cores_pwr_dm_on_finish) + rockchip_ops->cores_pwr_dm_on_finish(); +comm_finish: + + /* Perform the common cluster specific operations */ + if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { + /* Enable coherency if this cluster was off */ + plat_cci_enable(); + } + + /* Enable the gic cpu interface */ + plat_rockchip_gic_pcpu_init(); + + /* Program the gic per-cpu distributor or re-distributor interface */ + plat_rockchip_gic_cpuif_enable(); +} + +/******************************************************************************* + * RockChip handler called when a power domain has just been powered on after + * having been suspended earlier. The target_state encodes the low power state + * that each level has woken up from. + * TODO: At the moment we reuse the on finisher and reinitialize the secure + * context. Need to implement a separate suspend finisher. + ******************************************************************************/ +void rockchip_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ + uint32_t lvl; + plat_local_state_t lvl_state; + + /* Nothing to be done on waking up from retention from CPU level */ + if (RK_CORE_PWR_STATE(target_state) != PLAT_MAX_OFF_STATE) + return; + + /* Perform system domain restore if woken up from system suspend */ + if (!rockchip_ops) + goto comm_finish; + + if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { + if (rockchip_ops->sys_pwr_dm_resume) + rockchip_ops->sys_pwr_dm_resume(); + goto comm_finish; + } + + if (rockchip_ops->hlvl_pwr_dm_resume) { + for (lvl = MPIDR_AFFLVL1; lvl <= PLAT_MAX_PWR_LVL; lvl++) { + lvl_state = target_state->pwr_domain_state[lvl]; + rockchip_ops->hlvl_pwr_dm_resume(lvl, lvl_state); + } + } + + if (rockchip_ops->cores_pwr_dm_resume) + rockchip_ops->cores_pwr_dm_resume(); + /* + * Program the gic per-cpu distributor or re-distributor interface. + * For sys power domain operation, resuming of the gic needs to operate + * in rockchip_ops->sys_pwr_dm_resume, according to the sys power mode + * implements. + */ + plat_rockchip_gic_cpuif_enable(); + +comm_finish: + /* Perform the common cluster specific operations */ + if (RK_CLUSTER_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) { + /* Enable coherency if this cluster was off */ + plat_cci_enable(); + } +} + +/******************************************************************************* + * RockChip handlers to reboot the system + ******************************************************************************/ +static void __dead2 rockchip_system_reset(void) +{ + assert(rockchip_ops && rockchip_ops->sys_gbl_soft_reset); + + rockchip_ops->sys_gbl_soft_reset(); +} + +/******************************************************************************* + * RockChip handlers to power off the system + ******************************************************************************/ +static void __dead2 rockchip_system_poweroff(void) +{ + assert(rockchip_ops && rockchip_ops->system_off); + + rockchip_ops->system_off(); +} + +static void +__dead2 rockchip_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) +{ + if ((RK_CORE_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE) && + (rockchip_ops)) { + if (RK_SYSTEM_PWR_STATE(target_state) == PLAT_MAX_OFF_STATE && + rockchip_ops->sys_pwr_down_wfi) + rockchip_ops->sys_pwr_down_wfi(target_state); + } + psci_power_down_wfi(); +} + +/******************************************************************************* + * Export the platform handlers via plat_rockchip_psci_pm_ops. The rockchip + * standard + * platform layer will take care of registering the handlers with PSCI. + ******************************************************************************/ +const plat_psci_ops_t plat_rockchip_psci_pm_ops = { + .cpu_standby = rockchip_cpu_standby, + .pwr_domain_on = rockchip_pwr_domain_on, + .pwr_domain_off = rockchip_pwr_domain_off, + .pwr_domain_suspend = rockchip_pwr_domain_suspend, + .pwr_domain_on_finish = rockchip_pwr_domain_on_finish, + .pwr_domain_suspend_finish = rockchip_pwr_domain_suspend_finish, + .pwr_domain_pwr_down_wfi = rockchip_pwr_domain_pwr_down_wfi, + .system_reset = rockchip_system_reset, + .system_off = rockchip_system_poweroff, + .validate_power_state = rockchip_validate_power_state, + .get_sys_suspend_power_state = rockchip_get_sys_suspend_power_state +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + *psci_ops = &plat_rockchip_psci_pm_ops; + rockchip_sec_entrypoint = sec_entrypoint; + return 0; +} + +uintptr_t plat_get_sec_entrypoint(void) +{ + assert(rockchip_sec_entrypoint); + return rockchip_sec_entrypoint; +} + +void plat_setup_rockchip_pm_ops(struct rockchip_pm_ops_cb *ops) +{ + rockchip_ops = ops; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/plat_topology.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/plat_topology.c new file mode 100644 index 0000000..8a13945 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/plat_topology.c @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +/******************************************************************************* + * This function returns the RockChip default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return rockchip_power_domain_tree_desc; +} + +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + cpu_id = mpidr & MPIDR_AFFLVL_MASK; + cluster_id = mpidr & MPIDR_CLUSTER_MASK; + + cpu_id += (cluster_id >> PLAT_RK_CLST_TO_CPUID_SHIFT); + + if (cpu_id >= PLATFORM_CORE_COUNT) + return -1; + + return cpu_id; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/pmusram/pmu_sram.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/pmusram/pmu_sram.c new file mode 100644 index 0000000..bea4875 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/pmusram/pmu_sram.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +/***************************************************************************** + * sram only surpport 32-bits access + ******************************************************************************/ +void u32_align_cpy(uint32_t *dst, const uint32_t *src, size_t bytes) +{ + uint32_t i; + + for (i = 0; i < bytes; i++) + dst[i] = src[i]; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/pmusram/pmu_sram.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/pmusram/pmu_sram.h new file mode 100644 index 0000000..f290461 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/pmusram/pmu_sram.h @@ -0,0 +1,81 @@ +/* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PMU_SRAM_H__ +#define __PMU_SRAM_H__ + +/***************************************************************************** + * define data offset in struct psram_data + *****************************************************************************/ +#define PSRAM_DT_SP 0x0 +#define PSRAM_DT_DDR_FUNC 0x8 +#define PSRAM_DT_DDR_DATA 0x10 +#define PSRAM_DT_DDRFLAG 0x18 +#define PSRAM_DT_MPIDR 0x1c +#define PSRAM_DT_END 0x20 +/****************************************************************************** + * Allocate data region for struct psram_data_t in pmusram + ******************************************************************************/ +/* Needed aligned 16 bytes for sp stack top */ +#define PSRAM_DT_SIZE (((PSRAM_DT_END + 16) / 16) * 16) +#define PSRAM_DT_BASE ((PMUSRAM_BASE + PMUSRAM_RSIZE) - PSRAM_DT_SIZE) +#define PSRAM_SP_TOP PSRAM_DT_BASE + +#ifndef __ASSEMBLY__ + +/* + * The struct is used in pmu_cpus_on.S which + * gets the data of the struct by the following index + * #define PSRAM_DT_SP 0x0 + * #define PSRAM_DT_DDR_FUNC 0x8 + * #define PSRAM_DT_DDR_DATA 0x10 + * #define PSRAM_DT_DDRFLAG 0x18 + * #define PSRAM_DT_SYS_MODE 0x1c + * #define PSRAM_DT_MPIDR 0x20 + */ +struct psram_data_t { + uint64_t sp; + uint64_t ddr_func; + uint64_t ddr_data; + uint32_t ddr_flag; + uint32_t boot_mpidr; +}; + +CASSERT(sizeof(struct psram_data_t) <= PSRAM_DT_SIZE, + assert_psram_dt_size_mismatch); +CASSERT(__builtin_offsetof(struct psram_data_t, sp) == PSRAM_DT_SP, + assert_psram_dt_sp_offset_mistmatch); +CASSERT(__builtin_offsetof(struct psram_data_t, ddr_func) == PSRAM_DT_DDR_FUNC, + assert_psram_dt_ddr_func_offset_mistmatch); +CASSERT(__builtin_offsetof(struct psram_data_t, ddr_data) == PSRAM_DT_DDR_DATA, + assert_psram_dt_ddr_data_offset_mistmatch); +CASSERT(__builtin_offsetof(struct psram_data_t, ddr_flag) == PSRAM_DT_DDRFLAG, + assert_psram_dt_ddr_flag_offset_mistmatch); +CASSERT(__builtin_offsetof(struct psram_data_t, boot_mpidr) == PSRAM_DT_MPIDR, + assert_psram_dt_mpidr_offset_mistmatch); +void u32_align_cpy(uint32_t *dst, const uint32_t *src, size_t bytes); +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S new file mode 100644 index 0000000..9f94b0c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + + .globl pmu_cpuson_entrypoint_start + .globl pmu_cpuson_entrypoint_end + +func pmu_cpuson_entrypoint +pmu_cpuson_entrypoint_start: + ldr x5, psram_data +check_wake_cpus: + mrs x0, MPIDR_EL1 + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + orr x0, x0, x1 + /* primary_cpu */ + ldr w1, [x5, #PSRAM_DT_MPIDR] + cmp w0, w1 + b.eq sys_wakeup + /* + * If the core is not the primary cpu, + * force the core into wfe. + */ +wfe_loop: + wfe + b wfe_loop +sys_wakeup: + /* check ddr flag for resume ddr */ + ldr w2, [x5, #PSRAM_DT_DDRFLAG] + cmp w2, #0x0 + b.eq sys_resume +ddr_resume: + ldr x2, [x5, #PSRAM_DT_SP] + mov sp, x2 + ldr x1, [x5, #PSRAM_DT_DDR_FUNC] + ldr x0, [x5, #PSRAM_DT_DDR_DATA] + blr x1 +sys_resume: + ldr x1, sys_wakeup_entry + br x1 + + .align 3 +psram_data: + .quad PSRAM_DT_BASE +sys_wakeup_entry: + .quad psci_entrypoint +pmu_cpuson_entrypoint_end: + .word 0 +endfunc pmu_cpuson_entrypoint diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/rockchip_gicv2.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/rockchip_gicv2.c new file mode 100644 index 0000000..c2dca1f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/rockchip_gicv2.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +/****************************************************************************** + * The following functions are defined as weak to allow a platform to override + * the way the GICv2 driver is initialised and used. + *****************************************************************************/ +#pragma weak plat_rockchip_gic_driver_init +#pragma weak plat_rockchip_gic_init +#pragma weak plat_rockchip_gic_cpuif_enable +#pragma weak plat_rockchip_gic_cpuif_disable +#pragma weak plat_rockchip_gic_pcpu_init + +/****************************************************************************** + * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 + * interrupts. + *****************************************************************************/ +const unsigned int g0_interrupt_array[] = { + PLAT_RK_G1S_IRQS, +}; + +/* + * Ideally `rockchip_gic_data` structure definition should be a `const` but it + * is kept as modifiable for overwriting with different GICD and GICC base when + * running on FVP with VE memory map. + */ +gicv2_driver_data_t rockchip_gic_data = { + .gicd_base = PLAT_RK_GICD_BASE, + .gicc_base = PLAT_RK_GICC_BASE, + .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), + .g0_interrupt_array = g0_interrupt_array, +}; + +/****************************************************************************** + * RockChip common helper to initialize the GICv2 only driver. + *****************************************************************************/ +void plat_rockchip_gic_driver_init(void) +{ + gicv2_driver_init(&rockchip_gic_data); +} + +void plat_rockchip_gic_init(void) +{ + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +/****************************************************************************** + * RockChip common helper to enable the GICv2 CPU interface + *****************************************************************************/ +void plat_rockchip_gic_cpuif_enable(void) +{ + gicv2_cpuif_enable(); +} + +/****************************************************************************** + * RockChip common helper to disable the GICv2 CPU interface + *****************************************************************************/ +void plat_rockchip_gic_cpuif_disable(void) +{ + gicv2_cpuif_disable(); +} + +/****************************************************************************** + * RockChip common helper to initialize the per cpu distributor interface + * in GICv2 + *****************************************************************************/ +void plat_rockchip_gic_pcpu_init(void) +{ + gicv2_pcpu_distif_init(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/rockchip_gicv3.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/rockchip_gicv3.c new file mode 100644 index 0000000..7730896 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/rockchip_gicv3.c @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +/****************************************************************************** + * The following functions are defined as weak to allow a platform to override + * the way the GICv3 driver is initialised and used. + *****************************************************************************/ +#pragma weak plat_rockchip_gic_driver_init +#pragma weak plat_rockchip_gic_init +#pragma weak plat_rockchip_gic_cpuif_enable +#pragma weak plat_rockchip_gic_cpuif_disable +#pragma weak plat_rockchip_gic_pcpu_init + +/* The GICv3 driver only needs to be initialized in EL3 */ +uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT]; + +/* Array of Group1 secure interrupts to be configured by the gic driver */ +const unsigned int g1s_interrupt_array[] = { + PLAT_RK_G1S_IRQS +}; + +/* Array of Group0 interrupts to be configured by the gic driver */ +const unsigned int g0_interrupt_array[] = { + PLAT_RK_G0_IRQS +}; + +static unsigned int plat_rockchip_mpidr_to_core_pos(unsigned long mpidr) +{ + return (unsigned int)plat_core_pos_by_mpidr(mpidr); +} + +const gicv3_driver_data_t rockchip_gic_data = { + .gicd_base = PLAT_RK_GICD_BASE, + .gicr_base = PLAT_RK_GICR_BASE, + .g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array), + .g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array), + .g0_interrupt_array = g0_interrupt_array, + .g1s_interrupt_array = g1s_interrupt_array, + .rdistif_num = PLATFORM_CORE_COUNT, + .rdistif_base_addrs = rdistif_base_addrs, + .mpidr_to_core_pos = plat_rockchip_mpidr_to_core_pos, +}; + +void plat_rockchip_gic_driver_init(void) +{ + /* + * The GICv3 driver is initialized in EL3 and does not need + * to be initialized again in SEL1. This is because the S-EL1 + * can use GIC system registers to manage interrupts and does + * not need GIC interface base addresses to be configured. + */ +#if IMAGE_BL31 + gicv3_driver_init(&rockchip_gic_data); +#endif +} + +/****************************************************************************** + * RockChip common helper to initialize the GIC. Only invoked + * by BL31 + *****************************************************************************/ +void plat_rockchip_gic_init(void) +{ + gicv3_distif_init(); + gicv3_rdistif_init(plat_my_core_pos()); + gicv3_cpuif_enable(plat_my_core_pos()); +} + +/****************************************************************************** + * RockChip common helper to enable the GIC CPU interface + *****************************************************************************/ +void plat_rockchip_gic_cpuif_enable(void) +{ + gicv3_cpuif_enable(plat_my_core_pos()); +} + +/****************************************************************************** + * RockChip common helper to disable the GIC CPU interface + *****************************************************************************/ +void plat_rockchip_gic_cpuif_disable(void) +{ + gicv3_cpuif_disable(plat_my_core_pos()); +} + +/****************************************************************************** + * RockChip common helper to initialize the per-cpu redistributor interface + * in GICv3 + *****************************************************************************/ +void plat_rockchip_gic_pcpu_init(void) +{ + gicv3_rdistif_init(plat_my_core_pos()); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/rockchip_sip_svc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/rockchip_sip_svc.c new file mode 100644 index 0000000..cbc9105 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/common/rockchip_sip_svc.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Rockchip SiP Service UUID */ +DEFINE_SVC_UUID(rk_sip_svc_uid, + 0xe86fc7e2, 0x313e, 0x11e6, 0xb7, 0x0d, + 0x8f, 0x88, 0xee, 0x74, 0x7b, 0x72); + +#pragma weak rockchip_plat_sip_handler +uint64_t rockchip_plat_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + SMC_RET1(handle, SMC_UNK); +} + +/* + * This function is responsible for handling all SiP calls from the NS world + */ +uint64_t sip_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + uint32_t ns; + + /* Determine which security state this SMC originated from */ + ns = is_caller_non_secure(flags); + if (!ns) + SMC_RET1(handle, SMC_UNK); + + switch (smc_fid) { + case SIP_SVC_CALL_COUNT: + /* Return the number of Rockchip SiP Service Calls. */ + SMC_RET1(handle, + RK_COMMON_SIP_NUM_CALLS + RK_PLAT_SIP_NUM_CALLS); + + case SIP_SVC_UID: + /* Return UID to the caller */ + SMC_UUID_RET(handle, rk_sip_svc_uid); + break; + + case SIP_SVC_VERSION: + /* Return the version of current implementation */ + SMC_RET2(handle, RK_SIP_SVC_VERSION_MAJOR, + RK_SIP_SVC_VERSION_MINOR); + break; + + default: + return rockchip_plat_sip_handler(smc_fid, x1, x2, x3, x4, + cookie, handle, flags); + } +} + +/* Define a runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + rockchip_sip_svc, + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + NULL, + sip_smc_handler +); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.c new file mode 100644 index 0000000..cb89575 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.c @@ -0,0 +1,499 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* GRF_SOC_STATUS0 */ +#define DPLL_LOCK (0x1 << 2) + +/* GRF_DDRC0_CON0 */ +#define GRF_DDR_16BIT_EN (((0x1 << 3) << 16) | (0x1 << 3)) +#define GRF_DDR_32BIT_EN (((0x1 << 3) << 16) | (0x0 << 3)) +#define GRF_MOBILE_DDR_EN (((0x1 << 4) << 16) | (0x1 << 4)) +#define GRF_MOBILE_DDR_DISB (((0x1 << 4) << 16) | (0x0 << 4)) +#define GRF_DDR3_EN (((0x1 << 2) << 16) | (0x1 << 2)) +#define GRF_LPDDR2_3_EN (((0x1 << 2) << 16) | (0x0 << 2)) + +/* PMUGRF_SOC_CON0 */ +#define ddrphy_bufferen_io_en(n) ((0x1 << (9 + 16)) | (n << 9)) +#define ddrphy_bufferen_core_en(n) ((0x1 << (8 + 16)) | (n << 8)) + +struct PCTRL_TIMING_TAG { + uint32_t ddrfreq; + uint32_t TOGCNT1U; + uint32_t TINIT; + uint32_t TRSTH; + uint32_t TOGCNT100N; + uint32_t TREFI; + uint32_t TMRD; + uint32_t TRFC; + uint32_t TRP; + uint32_t TRTW; + uint32_t TAL; + uint32_t TCL; + uint32_t TCWL; + uint32_t TRAS; + uint32_t TRC; + uint32_t TRCD; + uint32_t TRRD; + uint32_t TRTP; + uint32_t TWR; + uint32_t TWTR; + uint32_t TEXSR; + uint32_t TXP; + uint32_t TXPDLL; + uint32_t TZQCS; + uint32_t TZQCSI; + uint32_t TDQS; + uint32_t TCKSRE; + uint32_t TCKSRX; + uint32_t TCKE; + uint32_t TMOD; + uint32_t TRSTL; + uint32_t TZQCL; + uint32_t TMRR; + uint32_t TCKESR; + uint32_t TDPD; + uint32_t TREFI_MEM_DDR3; +}; + +struct MSCH_SAVE_REG_TAG { + uint32_t ddrconf; + uint32_t ddrtiming; + uint32_t ddrmode; + uint32_t readlatency; + uint32_t activate; + uint32_t devtodev; +}; + +/* ddr suspend need save reg */ +struct PCTL_SAVE_REG_TAG { + uint32_t SCFG; + uint32_t CMDTSTATEN; + uint32_t MCFG1; + uint32_t MCFG; + uint32_t PPCFG; + struct PCTRL_TIMING_TAG pctl_timing; + /* DFI Control Registers */ + uint32_t DFITCTRLDELAY; + uint32_t DFIODTCFG; + uint32_t DFIODTCFG1; + uint32_t DFIODTRANKMAP; + /* DFI Write Data Registers */ + uint32_t DFITPHYWRDATA; + uint32_t DFITPHYWRLAT; + uint32_t DFITPHYWRDATALAT; + /* DFI Read Data Registers */ + uint32_t DFITRDDATAEN; + uint32_t DFITPHYRDLAT; + /* DFI Update Registers */ + uint32_t DFITPHYUPDTYPE0; + uint32_t DFITPHYUPDTYPE1; + uint32_t DFITPHYUPDTYPE2; + uint32_t DFITPHYUPDTYPE3; + uint32_t DFITCTRLUPDMIN; + uint32_t DFITCTRLUPDMAX; + uint32_t DFITCTRLUPDDLY; + uint32_t DFIUPDCFG; + uint32_t DFITREFMSKI; + uint32_t DFITCTRLUPDI; + /* DFI Status Registers */ + uint32_t DFISTCFG0; + uint32_t DFISTCFG1; + uint32_t DFITDRAMCLKEN; + uint32_t DFITDRAMCLKDIS; + uint32_t DFISTCFG2; + /* DFI Low Power Register */ + uint32_t DFILPCFG0; +}; + +struct DDRPHY_SAVE_REG_TAG { + uint32_t PHY_REG0; + uint32_t PHY_REG1; + uint32_t PHY_REGB; + uint32_t PHY_REGC; + uint32_t PHY_REG11; + uint32_t PHY_REG13; + uint32_t PHY_REG14; + uint32_t PHY_REG16; + uint32_t PHY_REG20; + uint32_t PHY_REG21; + uint32_t PHY_REG26; + uint32_t PHY_REG27; + uint32_t PHY_REG28; + uint32_t PHY_REG30; + uint32_t PHY_REG31; + uint32_t PHY_REG36; + uint32_t PHY_REG37; + uint32_t PHY_REG38; + uint32_t PHY_REG40; + uint32_t PHY_REG41; + uint32_t PHY_REG46; + uint32_t PHY_REG47; + uint32_t PHY_REG48; + uint32_t PHY_REG50; + uint32_t PHY_REG51; + uint32_t PHY_REG56; + uint32_t PHY_REG57; + uint32_t PHY_REG58; + uint32_t PHY_REGDLL; + uint32_t PHY_REGEC; + uint32_t PHY_REGED; + uint32_t PHY_REGEE; + uint32_t PHY_REGEF; + uint32_t PHY_REGFB; + uint32_t PHY_REGFC; + uint32_t PHY_REGFD; + uint32_t PHY_REGFE; +}; + +struct BACKUP_REG_TAG { + uint32_t tag; + uint32_t pctladdr; + struct PCTL_SAVE_REG_TAG pctl; + uint32_t phyaddr; + struct DDRPHY_SAVE_REG_TAG phy; + uint32_t nocaddr; + struct MSCH_SAVE_REG_TAG noc; + uint32_t pllselect; + uint32_t phypllockaddr; + uint32_t phyplllockmask; + uint32_t phyplllockval; + uint32_t pllpdstat; + uint32_t dpllmodeaddr; + uint32_t dpllslowmode; + uint32_t dpllnormalmode; + uint32_t dpllresetaddr; + uint32_t dpllreset; + uint32_t dplldereset; + uint32_t dpllconaddr; + uint32_t dpllcon[4]; + uint32_t dplllockaddr; + uint32_t dplllockmask; + uint32_t dplllockval; + uint32_t ddrpllsrcdivaddr; + uint32_t ddrpllsrcdiv; + uint32_t retendisaddr; + uint32_t retendisval; + uint32_t grfregaddr; + uint32_t grfddrcreg; + uint32_t crupctlphysoftrstaddr; + uint32_t cruresetpctlphy; + uint32_t cruderesetphy; + uint32_t cruderesetpctlphy; + uint32_t physoftrstaddr; + uint32_t endtag; +}; + +static uint32_t ddr_get_phy_pll_freq(void) +{ + uint32_t ret = 0; + uint32_t fb_div, pre_div; + + fb_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC); + fb_div |= (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED) & 0x1) << 8; + + pre_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) & 0xff; + ret = 2 * 24 * fb_div / (4 * pre_div); + + return ret; +} + +static void ddr_copy(uint32_t *pdest, uint32_t *psrc, uint32_t words) +{ + uint32_t i; + + for (i = 0; i < words; i++) + pdest[i] = psrc[i]; +} + +static void ddr_get_dpll_cfg(uint32_t *p) +{ + uint32_t nmhz, NO, NF, NR; + + nmhz = ddr_get_phy_pll_freq(); + if (nmhz <= 150) + NO = 6; + else if (nmhz <= 250) + NO = 4; + else if (nmhz <= 500) + NO = 2; + else + NO = 1; + + NR = 1; + NF = 2 * nmhz * NR * NO / 24; + + p[0] = SET_NR(NR) | SET_NO(NO); + p[1] = SET_NF(NF); + p[2] = SET_NB(NF / 2); +} + +void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr) +{ + struct BACKUP_REG_TAG *p_ddr_reg = (struct BACKUP_REG_TAG *)base_addr; + struct PCTL_SAVE_REG_TAG *pctl_tim = &p_ddr_reg->pctl; + + p_ddr_reg->tag = 0x56313031; + p_ddr_reg->pctladdr = DDR_PCTL_BASE; + p_ddr_reg->phyaddr = DDR_PHY_BASE; + p_ddr_reg->nocaddr = SERVICE_BUS_BASE; + + /* PCTLR */ + ddr_copy((uint32_t *)&pctl_tim->pctl_timing.TOGCNT1U, + (uint32_t *)(DDR_PCTL_BASE + DDR_PCTL_TOGCNT1U), 35); + pctl_tim->pctl_timing.TREFI |= DDR_UPD_REF_ENABLE; + pctl_tim->SCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_SCFG); + pctl_tim->CMDTSTATEN = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_CMDTSTATEN); + pctl_tim->MCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG1); + pctl_tim->MCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG); + pctl_tim->PPCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_PPCFG); + pctl_tim->pctl_timing.ddrfreq = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_TOGCNT1U * 2); + pctl_tim->DFITCTRLDELAY = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITCTRLDELAY); + pctl_tim->DFIODTCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIODTCFG); + pctl_tim->DFIODTCFG1 = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFIODTCFG1); + pctl_tim->DFIODTRANKMAP = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFIODTRANKMAP); + pctl_tim->DFITPHYWRDATA = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITPHYWRDATA); + pctl_tim->DFITPHYWRLAT = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITPHYWRLAT); + pctl_tim->DFITPHYWRDATALAT = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITPHYWRDATALAT); + pctl_tim->DFITRDDATAEN = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITRDDATAEN); + pctl_tim->DFITPHYRDLAT = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITPHYRDLAT); + pctl_tim->DFITPHYUPDTYPE0 = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITPHYUPDTYPE0); + pctl_tim->DFITPHYUPDTYPE1 = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITPHYUPDTYPE1); + pctl_tim->DFITPHYUPDTYPE2 = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITPHYUPDTYPE2); + pctl_tim->DFITPHYUPDTYPE3 = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITPHYUPDTYPE3); + pctl_tim->DFITCTRLUPDMIN = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITCTRLUPDMIN); + pctl_tim->DFITCTRLUPDMAX = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITCTRLUPDMAX); + pctl_tim->DFITCTRLUPDDLY = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITCTRLUPDDLY); + + pctl_tim->DFIUPDCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIUPDCFG); + pctl_tim->DFITREFMSKI = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITREFMSKI); + pctl_tim->DFITCTRLUPDI = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITCTRLUPDI); + pctl_tim->DFISTCFG0 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG0); + pctl_tim->DFISTCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG1); + pctl_tim->DFITDRAMCLKEN = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITDRAMCLKEN); + pctl_tim->DFITDRAMCLKDIS = mmio_read_32(DDR_PCTL_BASE + + DDR_PCTL_DFITDRAMCLKDIS); + pctl_tim->DFISTCFG2 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG2); + pctl_tim->DFILPCFG0 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFILPCFG0); + + /* PHY */ + p_ddr_reg->phy.PHY_REG0 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG0); + p_ddr_reg->phy.PHY_REG1 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG1); + p_ddr_reg->phy.PHY_REGB = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGB); + p_ddr_reg->phy.PHY_REGC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGC); + p_ddr_reg->phy.PHY_REG11 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG11); + p_ddr_reg->phy.PHY_REG13 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG13); + p_ddr_reg->phy.PHY_REG14 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG14); + p_ddr_reg->phy.PHY_REG16 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG16); + p_ddr_reg->phy.PHY_REG20 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG20); + p_ddr_reg->phy.PHY_REG21 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG21); + p_ddr_reg->phy.PHY_REG26 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG26); + p_ddr_reg->phy.PHY_REG27 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG27); + p_ddr_reg->phy.PHY_REG28 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG28); + p_ddr_reg->phy.PHY_REG30 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG30); + p_ddr_reg->phy.PHY_REG31 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG31); + p_ddr_reg->phy.PHY_REG36 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG36); + p_ddr_reg->phy.PHY_REG37 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG37); + p_ddr_reg->phy.PHY_REG38 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG38); + p_ddr_reg->phy.PHY_REG40 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG40); + p_ddr_reg->phy.PHY_REG41 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG41); + p_ddr_reg->phy.PHY_REG46 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG46); + p_ddr_reg->phy.PHY_REG47 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG47); + p_ddr_reg->phy.PHY_REG48 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG48); + p_ddr_reg->phy.PHY_REG50 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG50); + p_ddr_reg->phy.PHY_REG51 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG51); + p_ddr_reg->phy.PHY_REG56 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG56); + p_ddr_reg->phy.PHY_REG57 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG57); + p_ddr_reg->phy.PHY_REG58 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG58); + p_ddr_reg->phy.PHY_REGDLL = mmio_read_32(DDR_PHY_BASE + + DDR_PHY_REGDLL); + p_ddr_reg->phy.PHY_REGEC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC); + p_ddr_reg->phy.PHY_REGED = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED); + p_ddr_reg->phy.PHY_REGEE = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE); + p_ddr_reg->phy.PHY_REGEF = 0; + + if (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG2) & 0x2) { + p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE + + DDR_PHY_REG2C); + p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE + + DDR_PHY_REG3C); + p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE + + DDR_PHY_REG4C); + p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE + + DDR_PHY_REG5C); + } else { + p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE + + DDR_PHY_REGFB); + p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE + + DDR_PHY_REGFC); + p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE + + DDR_PHY_REGFD); + p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE + + DDR_PHY_REGFE); + } + + /* NOC */ + p_ddr_reg->noc.ddrconf = mmio_read_32(SERVICE_BUS_BASE + MSCH_DDRCONF); + p_ddr_reg->noc.ddrtiming = mmio_read_32(SERVICE_BUS_BASE + + MSCH_DDRTIMING); + p_ddr_reg->noc.ddrmode = mmio_read_32(SERVICE_BUS_BASE + MSCH_DDRMODE); + p_ddr_reg->noc.readlatency = mmio_read_32(SERVICE_BUS_BASE + + MSCH_READLATENCY); + p_ddr_reg->noc.activate = mmio_read_32(SERVICE_BUS_BASE + + MSCH_ACTIVATE); + p_ddr_reg->noc.devtodev = mmio_read_32(SERVICE_BUS_BASE + + MSCH_DEVTODEV); + + p_ddr_reg->pllselect = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) * 0x1; + p_ddr_reg->phypllockaddr = GRF_BASE + GRF_SOC_STATUS0; + p_ddr_reg->phyplllockmask = GRF_DDRPHY_LOCK; + p_ddr_reg->phyplllockval = 0; + + /* PLLPD */ + p_ddr_reg->pllpdstat = pllpdstat; + /* DPLL */ + p_ddr_reg->dpllmodeaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3); + /* slow mode and power on */ + p_ddr_reg->dpllslowmode = DPLL_WORK_SLOW_MODE | DPLL_POWER_DOWN; + p_ddr_reg->dpllnormalmode = DPLL_WORK_NORMAL_MODE; + p_ddr_reg->dpllresetaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3); + p_ddr_reg->dpllreset = DPLL_RESET_CONTROL_NORMAL; + p_ddr_reg->dplldereset = DPLL_RESET_CONTROL_RESET; + p_ddr_reg->dpllconaddr = CRU_BASE + PLL_CONS(DPLL_ID, 0); + + if (p_ddr_reg->pllselect == 0) { + p_ddr_reg->dpllcon[0] = (mmio_read_32(CRU_BASE + + PLL_CONS(DPLL_ID, 0)) + & 0xffff) | + (0xFFFF << 16); + p_ddr_reg->dpllcon[1] = (mmio_read_32(CRU_BASE + + PLL_CONS(DPLL_ID, 1)) + & 0xffff); + p_ddr_reg->dpllcon[2] = (mmio_read_32(CRU_BASE + + PLL_CONS(DPLL_ID, 2)) + & 0xffff); + p_ddr_reg->dpllcon[3] = (mmio_read_32(CRU_BASE + + PLL_CONS(DPLL_ID, 3)) + & 0xffff) | + (0xFFFF << 16); + } else { + ddr_get_dpll_cfg(&p_ddr_reg->dpllcon[0]); + } + + p_ddr_reg->pllselect = 0; + p_ddr_reg->dplllockaddr = CRU_BASE + PLL_CONS(DPLL_ID, 1); + p_ddr_reg->dplllockmask = DPLL_STATUS_LOCK; + p_ddr_reg->dplllockval = DPLL_STATUS_LOCK; + + /* SET_DDR_PLL_SRC */ + p_ddr_reg->ddrpllsrcdivaddr = CRU_BASE + CRU_CLKSELS_CON(13); + p_ddr_reg->ddrpllsrcdiv = (mmio_read_32(CRU_BASE + CRU_CLKSELS_CON(13)) + & DDR_PLL_SRC_MASK) + | (DDR_PLL_SRC_MASK << 16); + p_ddr_reg->retendisaddr = PMU_BASE + PMU_PWRMD_COM; + p_ddr_reg->retendisval = PD_PERI_PWRDN_ENABLE; + p_ddr_reg->grfregaddr = GRF_BASE + GRF_DDRC0_CON0; + p_ddr_reg->grfddrcreg = (mmio_read_32(GRF_BASE + GRF_DDRC0_CON0) & + DDR_PLL_SRC_MASK) | + (DDR_PLL_SRC_MASK << 16); + + /* pctl phy soft reset */ + p_ddr_reg->crupctlphysoftrstaddr = CRU_BASE + CRU_SOFTRSTS_CON(10); + p_ddr_reg->cruresetpctlphy = DDRCTRL0_PSRSTN_REQ(1) | + DDRCTRL0_SRSTN_REQ(1) | + DDRPHY0_PSRSTN_REQ(1) | + DDRPHY0_SRSTN_REQ(1); + p_ddr_reg->cruderesetphy = DDRCTRL0_PSRSTN_REQ(1) | + DDRCTRL0_SRSTN_REQ(1) | + DDRPHY0_PSRSTN_REQ(0) | + DDRPHY0_SRSTN_REQ(0); + + p_ddr_reg->cruderesetpctlphy = DDRCTRL0_PSRSTN_REQ(0) | + DDRCTRL0_SRSTN_REQ(0) | + DDRPHY0_PSRSTN_REQ(0) | + DDRPHY0_SRSTN_REQ(0); + + p_ddr_reg->physoftrstaddr = DDR_PHY_BASE + DDR_PHY_REG0; + + p_ddr_reg->endtag = 0xFFFFFFFF; +} + +/* + * "rk3368_ddr_reg_resume_V1.05.bin" is an executable bin which is generated + * by ARM DS5 for resuming ddr controller. If the soc wakes up from system + * suspend, ddr needs to be resumed and the resuming code needs to be run in + * sram. But there is not a way to pointing the resuming code to the PMUSRAM + * when linking .o files of bl31, so we use the + * "rk3368_ddr_reg_resume_V1.05.bin" whose code is position-independent and + * it can be loaded anywhere and run. + */ +static __aligned(4) unsigned int ddr_reg_resume[] = { + #include "rk3368_ddr_reg_resume_V1.05.bin" +}; + +uint32_t ddr_get_resume_code_size(void) +{ + return sizeof(ddr_reg_resume); +} + +uint32_t ddr_get_resume_data_size(void) +{ + return sizeof(struct BACKUP_REG_TAG); +} + +uint32_t *ddr_get_resume_code_base(void) +{ + return (unsigned int *)ddr_reg_resume; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.h new file mode 100644 index 0000000..c9d6c25 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.h @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DDR_RK3368_H__ +#define __DDR_RK3368_H__ + +#define DDR_PCTL_SCFG 0x0 +#define DDR_PCTL_SCTL 0x4 +#define DDR_PCTL_STAT 0x8 +#define DDR_PCTL_INTRSTAT 0xc + +#define DDR_PCTL_MCMD 0x40 +#define DDR_PCTL_POWCTL 0x44 +#define DDR_PCTL_POWSTAT 0x48 +#define DDR_PCTL_CMDTSTAT 0x4c +#define DDR_PCTL_CMDTSTATEN 0x50 +#define DDR_PCTL_MRRCFG0 0x60 +#define DDR_PCTL_MRRSTAT0 0x64 +#define DDR_PCTL_MRRSTAT1 0x68 +#define DDR_PCTL_MCFG1 0x7c +#define DDR_PCTL_MCFG 0x80 +#define DDR_PCTL_PPCFG 0x84 +#define DDR_PCTL_MSTAT 0x88 +#define DDR_PCTL_LPDDR2ZQCFG 0x8c +#define DDR_PCTL_DTUPDES 0x94 +#define DDR_PCTL_DTUNA 0x98 +#define DDR_PCTL_DTUNE 0x9c +#define DDR_PCTL_DTUPRD0 0xa0 +#define DDR_PCTL_DTUPRD1 0xa4 +#define DDR_PCTL_DTUPRD2 0xa8 +#define DDR_PCTL_DTUPRD3 0xac +#define DDR_PCTL_DTUAWDT 0xb0 +#define DDR_PCTL_TOGCNT1U 0xc0 +#define DDR_PCTL_TINIT 0xc4 +#define DDR_PCTL_TRSTH 0xc8 +#define DDR_PCTL_TOGCNT100N 0xcc +#define DDR_PCTL_TREFI 0xd0 +#define DDR_PCTL_TMRD 0xd4 +#define DDR_PCTL_TRFC 0xd8 +#define DDR_PCTL_TRP 0xdc +#define DDR_PCTL_TRTW 0xe0 +#define DDR_PCTL_TAL 0xe4 +#define DDR_PCTL_TCL 0xe8 +#define DDR_PCTL_TCWL 0xec +#define DDR_PCTL_TRAS 0xf0 +#define DDR_PCTL_TRC 0xf4 +#define DDR_PCTL_TRCD 0xf8 +#define DDR_PCTL_TRRD 0xfc +#define DDR_PCTL_TRTP 0x100 +#define DDR_PCTL_TWR 0x104 +#define DDR_PCTL_TWTR 0x108 +#define DDR_PCTL_TEXSR 0x10c +#define DDR_PCTL_TXP 0x110 +#define DDR_PCTL_TXPDLL 0x114 +#define DDR_PCTL_TZQCS 0x118 +#define DDR_PCTL_TZQCSI 0x11c +#define DDR_PCTL_TDQS 0x120 +#define DDR_PCTL_TCKSRE 0x124 +#define DDR_PCTL_TCKSRX 0x128 +#define DDR_PCTL_TCKE 0x12c +#define DDR_PCTL_TMOD 0x130 +#define DDR_PCTL_TRSTL 0x134 +#define DDR_PCTL_TZQCL 0x138 +#define DDR_PCTL_TMRR 0x13c +#define DDR_PCTL_TCKESR 0x140 +#define DDR_PCTL_TDPD 0x144 +#define DDR_PCTL_TREFI_MEM_DDR3 0x148 +#define DDR_PCTL_ECCCFG 0x180 +#define DDR_PCTL_ECCTST 0x184 +#define DDR_PCTL_ECCCLR 0x188 +#define DDR_PCTL_ECCLOG 0x18c +#define DDR_PCTL_DTUWACTL 0x200 +#define DDR_PCTL_DTURACTL 0x204 +#define DDR_PCTL_DTUCFG 0x208 +#define DDR_PCTL_DTUECTL 0x20c +#define DDR_PCTL_DTUWD0 0x210 +#define DDR_PCTL_DTUWD1 0x214 +#define DDR_PCTL_DTUWD2 0x218 +#define DDR_PCTL_DTUWD3 0x21c +#define DDR_PCTL_DTUWDM 0x220 +#define DDR_PCTL_DTURD0 0x224 +#define DDR_PCTL_DTURD1 0x228 +#define DDR_PCTL_DTURD2 0x22c +#define DDR_PCTL_DTURD3 0x230 +#define DDR_PCTL_DTULFSRWD 0x234 +#define DDR_PCTL_DTULFSRRD 0x238 +#define DDR_PCTL_DTUEAF 0x23c +#define DDR_PCTL_DFITCTRLDELAY 0x240 +#define DDR_PCTL_DFIODTCFG 0x244 +#define DDR_PCTL_DFIODTCFG1 0x248 +#define DDR_PCTL_DFIODTRANKMAP 0x24c +#define DDR_PCTL_DFITPHYWRDATA 0x250 +#define DDR_PCTL_DFITPHYWRLAT 0x254 +#define DDR_PCTL_DFITPHYWRDATALAT 0x258 +#define DDR_PCTL_DFITRDDATAEN 0x260 +#define DDR_PCTL_DFITPHYRDLAT 0x264 +#define DDR_PCTL_DFITPHYUPDTYPE0 0x270 +#define DDR_PCTL_DFITPHYUPDTYPE1 0x274 +#define DDR_PCTL_DFITPHYUPDTYPE2 0x278 +#define DDR_PCTL_DFITPHYUPDTYPE3 0x27c +#define DDR_PCTL_DFITCTRLUPDMIN 0x280 +#define DDR_PCTL_DFITCTRLUPDMAX 0x284 +#define DDR_PCTL_DFITCTRLUPDDLY 0x288 +#define DDR_PCTL_DFIUPDCFG 0x290 +#define DDR_PCTL_DFITREFMSKI 0x294 +#define DDR_PCTL_DFITCTRLUPDI 0x298 +#define DDR_PCTL_DFITRCFG0 0x2ac +#define DDR_PCTL_DFITRSTAT0 0x2b0 +#define DDR_PCTL_DFITRWRLVLEN 0x2b4 +#define DDR_PCTL_DFITRRDLVLEN 0x2b8 +#define DDR_PCTL_DFITRRDLVLGATEEN 0x2bc +#define DDR_PCTL_DFISTSTAT0 0x2c0 +#define DDR_PCTL_DFISTCFG0 0x2c4 +#define DDR_PCTL_DFISTCFG1 0x2c8 +#define DDR_PCTL_DFITDRAMCLKEN 0x2d0 +#define DDR_PCTL_DFITDRAMCLKDIS 0x2d4 +#define DDR_PCTL_DFISTCFG2 0x2d8 +#define DDR_PCTL_DFISTPARCLR 0x2dc +#define DDR_PCTL_DFISTPARLOG 0x2e0 +#define DDR_PCTL_DFILPCFG0 0x2f0 +#define DDR_PCTL_DFITRWRLVLRESP0 0x300 +#define DDR_PCTL_DFITRWRLVLRESP1 0x304 +#define DDR_PCTL_DFITRWRLVLRESP2 0x308 +#define DDR_PCTL_DFITRRDLVLRESP0 0x30c +#define DDR_PCTL_DFITRRDLVLRESP1 0x310 +#define DDR_PCTL_DFITRRDLVLRESP2 0x314 +#define DDR_PCTL_DFITRWRLVLDELAY0 0x318 +#define DDR_PCTL_DFITRWRLVLDELAY1 0x31c +#define DDR_PCTL_DFITRWRLVLDELAY2 0x320 +#define DDR_PCTL_DFITRRDLVLDELAY0 0x324 +#define DDR_PCTL_DFITRRDLVLDELAY1 0x328 +#define DDR_PCTL_DFITRRDLVLDELAY2 0x32c +#define DDR_PCTL_DFITRRDLVLGATEDELAY0 0x330 +#define DDR_PCTL_DFITRRDLVLGATEDELAY1 0x334 +#define DDR_PCTL_DFITRRDLVLGATEDELAY2 0x338 +#define DDR_PCTL_DFITRCMD 0x33c +#define DDR_PCTL_IPVR 0x3f8 +#define DDR_PCTL_IPTR 0x3fc + +/* DDR PHY REG */ +#define DDR_PHY_REG0 0x0 +#define DDR_PHY_REG1 0x4 +#define DDR_PHY_REG2 0x8 +#define DDR_PHY_REG3 0xc +#define DDR_PHY_REG4 0x10 +#define DDR_PHY_REG5 0x14 +#define DDR_PHY_REG6 0x18 +#define DDR_PHY_REGB 0x2c +#define DDR_PHY_REGC 0x30 +#define DDR_PHY_REG11 0x44 +#define DDR_PHY_REG12 0x48 +#define DDR_PHY_REG13 0x4c +#define DDR_PHY_REG14 0x50 +#define DDR_PHY_REG16 0x58 +#define DDR_PHY_REG20 0x80 +#define DDR_PHY_REG21 0x84 +#define DDR_PHY_REG26 0x98 +#define DDR_PHY_REG27 0x9c +#define DDR_PHY_REG28 0xa0 +#define DDR_PHY_REG2C 0xb0 +#define DDR_PHY_REG30 0xc0 +#define DDR_PHY_REG31 0xc4 +#define DDR_PHY_REG36 0xd8 +#define DDR_PHY_REG37 0xdc +#define DDR_PHY_REG38 0xe0 +#define DDR_PHY_REG3C 0xf0 +#define DDR_PHY_REG40 0x100 +#define DDR_PHY_REG41 0x104 +#define DDR_PHY_REG46 0x118 +#define DDR_PHY_REG47 0x11c +#define DDR_PHY_REG48 0x120 +#define DDR_PHY_REG4C 0x130 +#define DDR_PHY_REG50 0x140 +#define DDR_PHY_REG51 0x144 +#define DDR_PHY_REG56 0x158 +#define DDR_PHY_REG57 0x15c +#define DDR_PHY_REG58 0x160 +#define DDR_PHY_REG5C 0x170 +#define DDR_PHY_REGDLL 0x290 +#define DDR_PHY_REGEC 0x3b0 +#define DDR_PHY_REGED 0x3b4 +#define DDR_PHY_REGEE 0x3b8 +#define DDR_PHY_REGEF 0x3bc +#define DDR_PHY_REGF0 0x3c0 +#define DDR_PHY_REGF1 0x3c4 +#define DDR_PHY_REGF2 0x3c8 +#define DDR_PHY_REGFA 0x3e8 +#define DDR_PHY_REGFB 0x3ec +#define DDR_PHY_REGFC 0x3f0 +#define DDR_PHY_REGFD 0x3f4 +#define DDR_PHY_REGFE 0x3f8 +#define DDR_PHY_REGFF 0x3fc + +/* MSCH REG define */ +#define MSCH_COREID 0x0 +#define MSCH_DDRCONF 0x8 +#define MSCH_DDRTIMING 0xc +#define MSCH_DDRMODE 0x10 +#define MSCH_READLATENCY 0x14 +#define MSCH_ACTIVATE 0x38 +#define MSCH_DEVTODEV 0x3c + +#define SET_NR(n) ((0x3f << (8 + 16)) | ((n - 1) << 8)) +#define SET_NO(n) ((0xf << (0 + 16)) | ((n - 1) << 0)) +#define SET_NF(n) ((n - 1) & 0x1fff) +#define SET_NB(n) ((n - 1) & 0xfff) +#define PLLMODE(n) ((0x3 << (8 + 16)) | (n << 8)) + +/* GRF REG define */ +#define GRF_SOC_STATUS0 0x480 +#define GRF_DDRPHY_LOCK (0x1 << 15) +#define GRF_DDRC0_CON0 0x600 + +/* CRU softreset ddr pctl, phy */ +#define DDRMSCH0_SRSTN_REQ(n) (((0x1 << 10) << 16) | (n << 10)) +#define DDRCTRL0_PSRSTN_REQ(n) (((0x1 << 3) << 16) | (n << 3)) +#define DDRCTRL0_SRSTN_REQ(n) (((0x1 << 2) << 16) | (n << 2)) +#define DDRPHY0_PSRSTN_REQ(n) (((0x1 << 1) << 16) | (n << 1)) +#define DDRPHY0_SRSTN_REQ(n) (((0x1 << 0) << 16) | (n << 0)) + +/* CRU_DPLL_CON2 */ +#define DPLL_STATUS_LOCK (1 << 31) + +/* CRU_DPLL_CON3 */ +#define DPLL_POWER_DOWN ((0x1 << (1 + 16)) | (0 << 1)) +#define DPLL_WORK_NORMAL_MODE ((0x3 << (8 + 16)) | (0 << 8)) +#define DPLL_WORK_SLOW_MODE ((0x3 << (8 + 16)) | (1 << 8)) +#define DPLL_RESET_CONTROL_NORMAL ((0x1 << (5 + 16)) | (0x0 << 5)) +#define DPLL_RESET_CONTROL_RESET ((0x1 << (5 + 16)) | (0x1 << 5)) + +/* PMU_PWRDN_CON */ +#define PD_PERI_PWRDN_ENABLE (1 << 13) + +#define DDR_PLL_SRC_MASK 0x13 + +/* DDR_PCTL_TREFI */ +#define DDR_UPD_REF_ENABLE (0X1 << 31) + +uint32_t ddr_get_resume_code_size(void); +uint32_t ddr_get_resume_data_size(void); +uint32_t *ddr_get_resume_code_base(void); +void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr); + +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/plat_pmu_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/plat_pmu_macros.S new file mode 100644 index 0000000..5fd3c41 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/plat_pmu_macros.S @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +.macro func_rockchip_clst_warmboot + /* Nothing to do for rk3368 */ +.endm + +.macro rockchip_clst_warmboot_data + /* Nothing to do for rk3368 */ +.endm diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/pmu.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/pmu.c new file mode 100644 index 0000000..fc44a4c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/pmu.c @@ -0,0 +1,428 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DEFINE_BAKERY_LOCK(rockchip_pd_lock); + +static struct psram_data_t *psram_sleep_cfg = + (struct psram_data_t *)PSRAM_DT_BASE; + +static uint32_t cpu_warm_boot_addr; + +void rk3368_flash_l2_b(void) +{ + uint32_t wait_cnt = 0; + + regs_updata_bit_set(PMU_BASE + PMU_SFT_CON, pmu_sft_l2flsh_clst_b); + dsb(); + + while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) + & BIT(clst_b_l2_flsh_done))) { + wait_cnt++; + if (!(wait_cnt % MAX_WAIT_CONUT)) + WARN("%s:reg %x,wait\n", __func__, + mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); + } + + regs_updata_bit_clr(PMU_BASE + PMU_SFT_CON, pmu_sft_l2flsh_clst_b); +} + +static inline int rk3368_pmu_bus_idle(uint32_t req, uint32_t idle) +{ + uint32_t mask = BIT(req); + uint32_t idle_mask = 0; + uint32_t idle_target = 0; + uint32_t val; + uint32_t wait_cnt = 0; + + switch (req) { + case bus_ide_req_clst_l: + idle_mask = BIT(pmu_idle_ack_cluster_l); + idle_target = (idle << pmu_idle_ack_cluster_l); + break; + + case bus_ide_req_clst_b: + idle_mask = BIT(pmu_idle_ack_cluster_b); + idle_target = (idle << pmu_idle_ack_cluster_b); + break; + + case bus_ide_req_cxcs: + idle_mask = BIT(pmu_idle_ack_cxcs); + idle_target = ((!idle) << pmu_idle_ack_cxcs); + break; + + case bus_ide_req_cci400: + idle_mask = BIT(pmu_idle_ack_cci400); + idle_target = ((!idle) << pmu_idle_ack_cci400); + break; + + case bus_ide_req_gpu: + idle_mask = BIT(pmu_idle_ack_gpu) | BIT(pmu_idle_gpu); + idle_target = (idle << pmu_idle_ack_gpu) | + (idle << pmu_idle_gpu); + break; + + case bus_ide_req_core: + idle_mask = BIT(pmu_idle_ack_core) | BIT(pmu_idle_core); + idle_target = (idle << pmu_idle_ack_core) | + (idle << pmu_idle_core); + break; + + case bus_ide_req_bus: + idle_mask = BIT(pmu_idle_ack_bus) | BIT(pmu_idle_bus); + idle_target = (idle << pmu_idle_ack_bus) | + (idle << pmu_idle_bus); + break; + case bus_ide_req_dma: + idle_mask = BIT(pmu_idle_ack_dma) | BIT(pmu_idle_dma); + idle_target = (idle << pmu_idle_ack_dma) | + (idle << pmu_idle_dma); + break; + + case bus_ide_req_peri: + idle_mask = BIT(pmu_idle_ack_peri) | BIT(pmu_idle_peri); + idle_target = (idle << pmu_idle_ack_peri) | + (idle << pmu_idle_peri); + break; + + case bus_ide_req_video: + idle_mask = BIT(pmu_idle_ack_video) | BIT(pmu_idle_video); + idle_target = (idle << pmu_idle_ack_video) | + (idle << pmu_idle_video); + break; + + case bus_ide_req_vio: + idle_mask = BIT(pmu_idle_ack_vio) | BIT(pmu_idle_vio); + idle_target = (pmu_idle_ack_vio) | + (idle << pmu_idle_vio); + break; + + case bus_ide_req_alive: + idle_mask = BIT(pmu_idle_ack_alive) | BIT(pmu_idle_alive); + idle_target = (idle << pmu_idle_ack_alive) | + (idle << pmu_idle_alive); + break; + + case bus_ide_req_pmu: + idle_mask = BIT(pmu_idle_ack_pmu) | BIT(pmu_idle_pmu); + idle_target = (idle << pmu_idle_ack_pmu) | + (idle << pmu_idle_pmu); + break; + + case bus_ide_req_msch: + idle_mask = BIT(pmu_idle_ack_msch) | BIT(pmu_idle_msch); + idle_target = (idle << pmu_idle_ack_msch) | + (idle << pmu_idle_msch); + break; + + case bus_ide_req_cci: + idle_mask = BIT(pmu_idle_ack_cci) | BIT(pmu_idle_cci); + idle_target = (idle << pmu_idle_ack_cci) | + (idle << pmu_idle_cci); + break; + + default: + ERROR("%s: Unsupported the idle request\n", __func__); + break; + } + + val = mmio_read_32(PMU_BASE + PMU_BUS_IDE_REQ); + if (idle) + val |= mask; + else + val &= ~mask; + + mmio_write_32(PMU_BASE + PMU_BUS_IDE_REQ, val); + + while ((mmio_read_32(PMU_BASE + + PMU_BUS_IDE_ST) & idle_mask) != idle_target) { + wait_cnt++; + if (!(wait_cnt % MAX_WAIT_CONUT)) + WARN("%s:st=%x(%x)\n", __func__, + mmio_read_32(PMU_BASE + PMU_BUS_IDE_ST), + idle_mask); + } + + return 0; +} + +void pmu_scu_b_pwrup(void) +{ + regs_updata_bit_clr(PMU_BASE + PMU_SFT_CON, pmu_sft_acinactm_clst_b); + rk3368_pmu_bus_idle(bus_ide_req_clst_b, 0); +} + +static void pmu_scu_b_pwrdn(void) +{ + uint32_t wait_cnt = 0; + + if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & + PM_PWRDM_CPUSB_MSK) != PM_PWRDM_CPUSB_MSK) { + ERROR("%s: not all cpus is off\n", __func__); + return; + } + + rk3368_flash_l2_b(); + + regs_updata_bit_set(PMU_BASE + PMU_SFT_CON, pmu_sft_acinactm_clst_b); + + while (!(mmio_read_32(PMU_BASE + + PMU_CORE_PWR_ST) & BIT(clst_b_l2_wfi))) { + wait_cnt++; + if (!(wait_cnt % MAX_WAIT_CONUT)) + ERROR("%s:wait cluster-b l2(%x)\n", __func__, + mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); + } + rk3368_pmu_bus_idle(bus_ide_req_clst_b, 1); +} + +static void pmu_sleep_mode_config(void) +{ + uint32_t pwrmd_core, pwrmd_com; + + pwrmd_core = BIT(pmu_mdcr_cpu0_pd) | + BIT(pmu_mdcr_scu_l_pd) | + BIT(pmu_mdcr_l2_flush) | + BIT(pmu_mdcr_l2_idle) | + BIT(pmu_mdcr_clr_clst_l) | + BIT(pmu_mdcr_clr_core) | + BIT(pmu_mdcr_clr_cci) | + BIT(pmu_mdcr_core_pd); + + pwrmd_com = BIT(pmu_mode_en) | + BIT(pmu_mode_sref_enter) | + BIT(pmu_mode_pwr_off); + + regs_updata_bit_set(PMU_BASE + PMU_WKUP_CFG2, pmu_cluster_l_wkup_en); + regs_updata_bit_set(PMU_BASE + PMU_WKUP_CFG2, pmu_cluster_b_wkup_en); + regs_updata_bit_clr(PMU_BASE + PMU_WKUP_CFG2, pmu_gpio_wkup_en); + + mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_24M_CNT_MS(2)); + mmio_write_32(PMU_BASE + PMU_PLLRST_CNT, CYCL_24M_CNT_US(100)); + mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_24M_CNT_MS(2)); + mmio_write_32(PMU_BASE + PMU_PWRMD_CORE, pwrmd_core); + mmio_write_32(PMU_BASE + PMU_PWRMD_COM, pwrmd_com); + dsb(); +} + +static void ddr_suspend_save(void) +{ + ddr_reg_save(1, psram_sleep_cfg->ddr_data); +} + +static void pmu_set_sleep_mode(void) +{ + ddr_suspend_save(); + pmu_sleep_mode_config(); + soc_sleep_config(); + regs_updata_bit_set(PMU_BASE + PMU_PWRMD_CORE, pmu_mdcr_global_int_dis); + regs_updata_bit_set(PMU_BASE + PMU_SFT_CON, pmu_sft_glbl_int_dis_b); + pmu_scu_b_pwrdn(); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), + (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) | + CPU_BOOT_ADDR_WMASK); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), + (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) | + CPU_BOOT_ADDR_WMASK); +} + +void plat_rockchip_pmusram_prepare(void) +{ + uint32_t *sram_dst, *sram_src; + size_t sram_size = 2; + uint32_t code_size; + + /* pmu sram code and data prepare */ + sram_dst = (uint32_t *)PMUSRAM_BASE; + sram_src = (uint32_t *)&pmu_cpuson_entrypoint_start; + sram_size = (uint32_t *)&pmu_cpuson_entrypoint_end - + (uint32_t *)sram_src; + u32_align_cpy(sram_dst, sram_src, sram_size); + + /* ddr code */ + sram_dst += sram_size; + sram_src = ddr_get_resume_code_base(); + code_size = ddr_get_resume_code_size(); + u32_align_cpy(sram_dst, sram_src, code_size / 4); + psram_sleep_cfg->ddr_func = (uint64_t)sram_dst; + + /* ddr data */ + sram_dst += (code_size / 4); + psram_sleep_cfg->ddr_data = (uint64_t)sram_dst; + + assert((uint64_t)(sram_dst + ddr_get_resume_data_size() / 4) + < PSRAM_SP_BOTTOM); + psram_sleep_cfg->sp = PSRAM_SP_TOP; +} + +static int cpus_id_power_domain(uint32_t cluster, + uint32_t cpu, + uint32_t pd_state, + uint32_t wfie_msk) +{ + uint32_t pd; + uint64_t mpidr; + + if (cluster) + pd = PD_CPUB0 + cpu; + else + pd = PD_CPUL0 + cpu; + + if (pmu_power_domain_st(pd) == pd_state) + return 0; + + if (pd_state == pmu_pd_off) { + mpidr = (cluster << MPIDR_AFF1_SHIFT) | cpu; + if (check_cpu_wfie(mpidr, wfie_msk)) + return -EINVAL; + } + + return pmu_power_domain_ctr(pd, pd_state); +} + +static void nonboot_cpus_off(void) +{ + uint32_t boot_cpu, boot_cluster, cpu; + + boot_cpu = MPIDR_AFFLVL0_VAL(read_mpidr_el1()); + boot_cluster = MPIDR_AFFLVL1_VAL(read_mpidr_el1()); + + /* turn off noboot cpus */ + for (cpu = 0; cpu < PLATFORM_CLUSTER0_CORE_COUNT; cpu++) { + if (!boot_cluster && (cpu == boot_cpu)) + continue; + cpus_id_power_domain(0, cpu, pmu_pd_off, CKECK_WFEI_MSK); + } + + for (cpu = 0; cpu < PLATFORM_CLUSTER1_CORE_COUNT; cpu++) { + if (boot_cluster && (cpu == boot_cpu)) + continue; + cpus_id_power_domain(1, cpu, pmu_pd_off, CKECK_WFEI_MSK); + } +} + +static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint) +{ + uint32_t cpu, cluster; + uint32_t cpuon_id; + + cpu = MPIDR_AFFLVL0_VAL(mpidr); + cluster = MPIDR_AFFLVL1_VAL(mpidr); + + /* Make sure the cpu is off,Before power up the cpu! */ + cpus_id_power_domain(cluster, cpu, pmu_pd_off, CKECK_WFEI_MSK); + + cpuon_id = (cluster * PLATFORM_CLUSTER0_CORE_COUNT) + cpu; + assert(cpuon_id < PLATFORM_CORE_COUNT); + assert(cpuson_flags[cpuon_id] == 0); + cpuson_flags[cpuon_id] = PMU_CPU_HOTPLUG; + cpuson_entry_point[cpuon_id] = entrypoint; + + /* Switch boot addr to pmusram */ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1 + cluster), + (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | + CPU_BOOT_ADDR_WMASK); + dsb(); + + cpus_id_power_domain(cluster, cpu, pmu_pd_on, CKECK_WFEI_MSK); + + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1 + cluster), + (COLD_BOOT_BASE >> CPU_BOOT_ADDR_ALIGN) | + CPU_BOOT_ADDR_WMASK); + + return 0; +} + +static int cores_pwr_domain_on_finish(void) +{ + return 0; +} + +static int sys_pwr_domain_resume(void) +{ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), + (COLD_BOOT_BASE >> CPU_BOOT_ADDR_ALIGN) | + CPU_BOOT_ADDR_WMASK); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(2), + (COLD_BOOT_BASE >> CPU_BOOT_ADDR_ALIGN) | + CPU_BOOT_ADDR_WMASK); + pm_plls_resume(); + pmu_scu_b_pwrup(); + + return 0; +} + +static int sys_pwr_domain_suspend(void) +{ + nonboot_cpus_off(); + pmu_set_sleep_mode(); + + psram_sleep_cfg->ddr_flag = 0; + + return 0; +} + +static struct rockchip_pm_ops_cb pm_ops = { + .cores_pwr_dm_on = cores_pwr_domain_on, + .cores_pwr_dm_on_finish = cores_pwr_domain_on_finish, + .sys_pwr_dm_suspend = sys_pwr_domain_suspend, + .sys_pwr_dm_resume = sys_pwr_domain_resume, + .sys_gbl_soft_reset = soc_sys_global_soft_reset, +}; + +void plat_rockchip_pmu_init(void) +{ + uint32_t cpu; + + plat_setup_rockchip_pm_ops(&pm_ops); + + /* register requires 32bits mode, switch it to 32 bits */ + cpu_warm_boot_addr = (uint64_t)platform_cpu_warmboot; + + for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) + cpuson_flags[cpu] = 0; + + psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; + + nonboot_cpus_off(); + INFO("%s(%d): pd status %x\n", __func__, __LINE__, + mmio_read_32(PMU_BASE + PMU_PWRDN_ST)); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/pmu.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/pmu.h new file mode 100644 index 0000000..2cf60fd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/pmu/pmu.h @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PMU_H__ +#define __PMU_H__ + +/* Allocate sp reginon in pmusram */ +#define PSRAM_SP_SIZE 0x80 +#define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE) + +/***************************************************************************** + * pmu con,reg + *****************************************************************************/ +#define PMU_WKUP_CFG0 0x0 +#define PMU_WKUP_CFG1 0x4 +#define PMU_WKUP_CFG2 0x8 +#define PMU_TIMEOUT_CNT 0x7c +#define PMU_PWRDN_CON 0xc +#define PMU_PWRDN_ST 0x10 +#define PMU_CORE_PWR_ST 0x38 + +#define PMU_PWRMD_CORE 0x14 +#define PMU_PWRMD_COM 0x18 +#define PMU_SFT_CON 0x1c +#define PMU_BUS_IDE_REQ 0x3c +#define PMU_BUS_IDE_ST 0x40 +#define PMU_OSC_CNT 0x48 +#define PMU_PLLLOCK_CNT 0x4c +#define PMU_PLLRST_CNT 0x50 +#define PMU_STABLE_CNT 0x54 +#define PMU_DDRIO_PWR_CNT 0x58 +#define PMU_WKUPRST_CNT 0x5c + +enum pmu_powermode_core { + pmu_mdcr_global_int_dis = 0, + pmu_mdcr_core_src_gt, + pmu_mdcr_clr_cci, + pmu_mdcr_cpu0_pd, + pmu_mdcr_clr_clst_l = 4, + pmu_mdcr_clr_core, + pmu_mdcr_scu_l_pd, + pmu_mdcr_core_pd, + pmu_mdcr_l2_idle = 8, + pmu_mdcr_l2_flush +}; + +/* + * the shift of bits for cores status + */ +enum pmu_core_pwrst_shift { + clstl_cpu_wfe = 2, + clstl_cpu_wfi = 6, + clstb_cpu_wfe = 12, + clstb_cpu_wfi = 16 +}; + +enum pmu_pdid { + PD_CPUL0 = 0, + PD_CPUL1, + PD_CPUL2, + PD_CPUL3, + PD_SCUL, + PD_CPUB0 = 5, + PD_CPUB1, + PD_CPUB2, + PD_CPUB3, + PD_SCUB = 9, + PD_PERI = 13, + PD_VIDEO, + PD_VIO, + PD_GPU0, + PD_GPU1, + PD_END +}; + +enum pmu_bus_ide { + bus_ide_req_clst_l = 0, + bus_ide_req_clst_b, + bus_ide_req_gpu, + bus_ide_req_core, + bus_ide_req_bus = 4, + bus_ide_req_dma, + bus_ide_req_peri, + bus_ide_req_video, + bus_ide_req_vio = 8, + bus_ide_req_res0, + bus_ide_req_cxcs, + bus_ide_req_alive, + bus_ide_req_pmu = 12, + bus_ide_req_msch, + bus_ide_req_cci, + bus_ide_req_cci400 = 15, + bus_ide_req_end +}; + +enum pmu_powermode_common { + pmu_mode_en = 0, + pmu_mode_res0, + pmu_mode_bus_pd, + pmu_mode_wkup_rst, + pmu_mode_pll_pd = 4, + pmu_mode_pwr_off, + pmu_mode_pmu_use_if, + pmu_mode_pmu_alive_use_if, + pmu_mode_osc_dis = 8, + pmu_mode_input_clamp, + pmu_mode_sref_enter, + pmu_mode_ddrc_gt, + pmu_mode_ddrio_ret = 12, + pmu_mode_ddrio_ret_deq, + pmu_mode_clr_pmu, + pmu_mode_clr_alive, + pmu_mode_clr_bus = 16, + pmu_mode_clr_dma, + pmu_mode_clr_msch, + pmu_mode_clr_peri, + pmu_mode_clr_video = 20, + pmu_mode_clr_vio, + pmu_mode_clr_gpu, + pmu_mode_clr_mcu, + pmu_mode_clr_cxcs = 24, + pmu_mode_clr_cci400, + pmu_mode_res1, + pmu_mode_res2, + pmu_mode_res3 = 28, + pmu_mode_mclst +}; + +enum pmu_core_power_st { + clst_l_cpu_wfe = 2, + clst_l_cpu_wfi = 6, + clst_b_l2_flsh_done = 10, + clst_b_l2_wfi = 11, + clst_b_cpu_wfe = 12, + clst_b_cpu_wfi = 16, + mcu_sleeping = 20, +}; + +enum pmu_sft_con { + pmu_sft_acinactm_clst_b = 5, + pmu_sft_l2flsh_clst_b, + pmu_sft_glbl_int_dis_b = 9, + pmu_sft_ddrio_ret_cfg = 11, +}; + +enum pmu_wkup_cfg2 { + pmu_cluster_l_wkup_en = 0, + pmu_cluster_b_wkup_en, + pmu_gpio_wkup_en, + pmu_sdio_wkup_en, + pmu_sdmmc_wkup_en, + pmu_sim_wkup_en, + pmu_timer_wkup_en, + pmu_usbdev_wkup_en, + pmu_sft_wkup_en, + pmu_wdt_mcu_wkup_en, + pmu_timeout_wkup_en, +}; + +enum pmu_bus_idle_st { + pmu_idle_ack_cluster_l = 0, + pmu_idle_ack_cluster_b, + pmu_idle_ack_gpu, + pmu_idle_ack_core, + pmu_idle_ack_bus, + pmu_idle_ack_dma, + pmu_idle_ack_peri, + pmu_idle_ack_video, + pmu_idle_ack_vio, + pmu_idle_ack_cci = 10, + pmu_idle_ack_msch, + pmu_idle_ack_alive, + pmu_idle_ack_pmu, + pmu_idle_ack_cxcs, + pmu_idle_ack_cci400, + pmu_inactive_cluster_l, + pmu_inactive_cluster_b, + pmu_idle_gpu, + pmu_idle_core, + pmu_idle_bus, + pmu_idle_dma, + pmu_idle_peri, + pmu_idle_video, + pmu_idle_vio, + pmu_idle_cci = 26, + pmu_idle_msch, + pmu_idle_alive, + pmu_idle_pmu, + pmu_active_cxcs, + pmu_active_cci, +}; + +#define PM_PWRDM_CPUSB_MSK (0xf << 5) + +#define CKECK_WFE_MSK 0x1 +#define CKECK_WFI_MSK 0x10 +#define CKECK_WFEI_MSK 0x11 + +#define PD_CTR_LOOP 500 +#define CHK_CPU_LOOP 500 + +#define MAX_WAIT_CONUT 1000 + +#endif /* __PMU_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/soc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/soc.c new file mode 100644 index 0000000..3630828 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/soc.c @@ -0,0 +1,219 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +static uint32_t plls_con[END_PLL_ID][4]; + +/* Table of regions to map using the MMU. */ +const mmap_region_t plat_rk_mmap[] = { + MAP_REGION_FLAT(CCI400_BASE, CCI400_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(STIME_BASE, STIME_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, + MT_MEMORY | MT_RW | MT_SECURE), + MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(UART_DBG_BASE, UART_DBG_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(CRU_BASE, CRU_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(DDR_PCTL_BASE, DDR_PCTL_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(DDR_PHY_BASE, DDR_PHY_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(GRF_BASE, GRF_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(SERVICE_BUS_BASE, SERVICE_BUS_SISE, + MT_DEVICE | MT_RW | MT_SECURE), + { 0 } +}; + +/* The RockChip power domain tree descriptor */ +const unsigned char rockchip_power_domain_tree_desc[] = { + /* No of root nodes */ + PLATFORM_SYSTEM_COUNT, + /* No of children for the root node */ + PLATFORM_CLUSTER_COUNT, + /* No of children for the first cluster node */ + PLATFORM_CLUSTER0_CORE_COUNT, + /* No of children for the second cluster node */ + PLATFORM_CLUSTER1_CORE_COUNT +}; + +void secure_timer_init(void) +{ + mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT0, 0xffffffff); + mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT1, 0xffffffff); + + /* auto reload & enable the timer */ + mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); +} + +void sgrf_init(void) +{ + /* setting all configurable ip into no-secure */ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SOC_CON7_BITS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SOC_CON_NS); + + /* secure dma to no sesure */ + mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(0), SGRF_BUSDMAC_CON0_NS); + mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(1), SGRF_BUSDMAC_CON1_NS); + dsb(); + + /* rst dma1 */ + mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), + RST_DMA1_MSK | (RST_DMA1_MSK << 16)); + /* rst dma2 */ + mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), + RST_DMA2_MSK | (RST_DMA2_MSK << 16)); + + dsb(); + + /* release dma1 rst*/ + mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16)); + /* release dma2 rst*/ + mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16)); +} + +void plat_rockchip_soc_init(void) +{ + secure_timer_init(); + sgrf_init(); +} + +void regs_updata_bits(uintptr_t addr, uint32_t val, + uint32_t mask, uint32_t shift) +{ + uint32_t tmp, orig; + + orig = mmio_read_32(addr); + + tmp = orig & ~(mask << shift); + tmp |= (val & mask) << shift; + + if (tmp != orig) + mmio_write_32(addr, tmp); + dsb(); +} + +static void plls_suspend(uint32_t pll_id) +{ + plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); + plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); + plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); + plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); + + mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS); + mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_BYPASS); +} + +static void pm_plls_suspend(void) +{ + plls_suspend(NPLL_ID); + plls_suspend(CPLL_ID); + plls_suspend(GPLL_ID); + plls_suspend(ABPLL_ID); + plls_suspend(ALPLL_ID); +} + +static inline void plls_resume(void) +{ + mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), + plls_con[ABPLL_ID][3] | PLL_BYPASS_W_MSK); + mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), + plls_con[ALPLL_ID][3] | PLL_BYPASS_W_MSK); + mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), + plls_con[GPLL_ID][3] | PLL_BYPASS_W_MSK); + mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), + plls_con[CPLL_ID][3] | PLL_BYPASS_W_MSK); + mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), + plls_con[NPLL_ID][3] | PLL_BYPASS_W_MSK); +} + +void soc_sleep_config(void) +{ + int i = 0; + + for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) + mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000); + pm_plls_suspend(); + + for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) + mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000); +} + +void pm_plls_resume(void) +{ + plls_resume(); + + mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), + plls_con[ABPLL_ID][3] | PLLS_MODE_WMASK); + mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), + plls_con[ALPLL_ID][3] | PLLS_MODE_WMASK); + mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), + plls_con[GPLL_ID][3] | PLLS_MODE_WMASK); + mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), + plls_con[CPLL_ID][3] | PLLS_MODE_WMASK); + mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), + plls_con[NPLL_ID][3] | PLLS_MODE_WMASK); +} + +void __dead2 soc_sys_global_soft_reset(void) +{ + uint32_t temp_val; + + mmio_write_32(CRU_BASE + PLL_CONS((GPLL_ID), 3), PLL_SLOW_BITS); + mmio_write_32(CRU_BASE + PLL_CONS((CPLL_ID), 3), PLL_SLOW_BITS); + mmio_write_32(CRU_BASE + PLL_CONS((NPLL_ID), 3), PLL_SLOW_BITS); + mmio_write_32(CRU_BASE + PLL_CONS((ABPLL_ID), 3), PLL_SLOW_BITS); + mmio_write_32(CRU_BASE + PLL_CONS((ALPLL_ID), 3), PLL_SLOW_BITS); + + temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON) | + PMU_RST_BY_SECOND_SFT; + + mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val); + mmio_write_32(CRU_BASE + CRU_GLB_SRST_SND, 0xeca8); + + /* + * Maybe the HW needs some times to reset the system, + * so we do not hope the core to excute valid codes. + */ + while (1) + ; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/soc.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/soc.h new file mode 100644 index 0000000..6e2c3fe --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/drivers/soc/soc.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SOC_H__ +#define __SOC_H__ + +enum plls_id { + ABPLL_ID = 0, + ALPLL_ID, + DPLL_ID, + CPLL_ID, + GPLL_ID, + NPLL_ID, + END_PLL_ID, +}; + +/***************************************************************************** + * secure timer + *****************************************************************************/ +#define TIMER_LOADE_COUNT0 0x00 +#define TIMER_LOADE_COUNT1 0x04 +#define TIMER_CURRENT_VALUE0 0x08 +#define TIMER_CURRENT_VALUE1 0x0C +#define TIMER_CONTROL_REG 0x10 +#define TIMER_INTSTATUS 0x18 + +#define TIMER_EN 0x1 + +#define STIMER1_BASE (STIME_BASE + 0x20) + +#define CYCL_24M_CNT_US(us) (24 * us) +#define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000)) + +/***************************************************************************** + * sgrf reg, offset + *****************************************************************************/ +#define SGRF_SOC_CON(n) (0x0 + (n) * 4) +#define SGRF_BUSDMAC_CON(n) (0x100 + (n) * 4) + +#define SGRF_SOC_CON_NS 0xffff0000 + +/***************************************************************************** + * con6[2]pmusram is security. + * con6[6]stimer is security. + *****************************************************************************/ +#define PMUSRAM_S_SHIFT 2 +#define PMUSRAM_S 1 +#define STIMER_S_SHIFT 6 +#define STIMER_S 1 +#define SGRF_SOC_CON7_BITS ((0xffff << 16) | \ + (PMUSRAM_S << PMUSRAM_S_SHIFT) | \ + (STIMER_S << STIMER_S_SHIFT)) + +#define SGRF_BUSDMAC_CON0_NS 0xfffcfff8 +#define SGRF_BUSDMAC_CON1_NS 0xffff0fff + +/* + * sgrf_soc_con1~2, mask and offset + */ +#define CPU_BOOT_ADDR_WMASK 0xffff0000 +#define CPU_BOOT_ADDR_ALIGN 16 + +/***************************************************************************** + * cru reg, offset + *****************************************************************************/ +#define CRU_SOFTRST_CON 0x300 +#define CRU_SOFTRSTS_CON(n) (CRU_SOFTRST_CON + ((n) * 4)) +#define CRU_SOFTRSTS_CON_CNT 15 + +#define SOFTRST_DMA1 0x40004 +#define SOFTRST_DMA2 0x10001 + +#define RST_DMA1_MSK 0x4 +#define RST_DMA2_MSK 0x0 + +#define CRU_CLKSEL_CON 0x100 +#define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4)) +#define CRU_CLKSEL_CON_CNT 56 + +#define CRU_CLKGATE_CON 0x200 +#define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4)) +#define CRU_CLKGATES_CON_CNT 25 + +#define CRU_GLB_SRST_FST 0x280 +#define CRU_GLB_SRST_SND 0x284 +#define CRU_GLB_RST_CON 0x388 + +#define CRU_CONS_GATEID(i) (16 * (i)) +#define GATE_ID(reg, bit) ((reg * 16) + bit) + +#define PMU_RST_BY_SECOND_SFT (BIT(1) << 2) +#define PMU_RST_NOT_BY_SFT (BIT(1) << 2) + +/*************************************************************************** + * pll + ***************************************************************************/ +#define PLL_PWR_DN_MSK (0x1 << 1) +#define PLL_PWR_DN REG_WMSK_BITS(1, 1, 0x1) +#define PLL_PWR_ON REG_WMSK_BITS(0, 1, 0x1) +#define PLL_RESET REG_WMSK_BITS(1, 5, 0x1) +#define PLL_RESET_RESUME REG_WMSK_BITS(0, 5, 0x1) +#define PLL_BYPASS_MSK (0x1 << 0) +#define PLL_BYPASS_W_MSK (PLL_BYPASS_MSK << 16) +#define PLL_BYPASS REG_WMSK_BITS(1, 0, 0x1) +#define PLL_NO_BYPASS REG_WMSK_BITS(0, 0, 0x1) +#define PLL_MODE_SHIFT 8 +#define PLL_MODE_MSK 0x3 +#define PLLS_MODE_WMASK (PLL_MODE_MSK << (16 + PLL_MODE_SHIFT)) +#define PLL_SLOW 0x0 +#define PLL_NORM 0x1 +#define PLL_DEEP 0x2 +#define PLL_SLOW_BITS REG_WMSK_BITS(PLL_SLOW, 8, 0x3) +#define PLL_NORM_BITS REG_WMSK_BITS(PLL_NORM, 8, 0x3) +#define PLL_DEEP_BITS REG_WMSK_BITS(PLL_DEEP, 8, 0x3) + +#define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4)) + +#define REG_W_MSK(bits_shift, msk) \ + ((msk) << ((bits_shift) + 16)) +#define REG_VAL_CLRBITS(val, bits_shift, msk) \ + (val & (~(msk << bits_shift))) +#define REG_SET_BITS(bits, bits_shift, msk) \ + (((bits) & (msk)) << (bits_shift)) +#define REG_WMSK_BITS(bits, bits_shift, msk) \ + (REG_W_MSK(bits_shift, msk) | \ + REG_SET_BITS(bits, bits_shift, msk)) + +#define regs_updata_bit_set(addr, shift) \ + regs_updata_bits((addr), 0x1, 0x1, (shift)) +#define regs_updata_bit_clr(addr, shift) \ + regs_updata_bits((addr), 0x0, 0x1, (shift)) + +void __dead2 soc_sys_global_soft_reset(void); +void regs_updata_bits(uintptr_t addr, uint32_t val, + uint32_t mask, uint32_t shift); +void soc_sleep_config(void); +void pm_plls_resume(void); + +#endif /* __SOC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/include/plat_sip_calls.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/include/plat_sip_calls.h new file mode 100644 index 0000000..a778f49 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/include/plat_sip_calls.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_SIP_CALLS_H__ +#define __PLAT_SIP_CALLS_H__ + +#define RK_PLAT_SIP_NUM_CALLS 0 + +#endif /* __PLAT_SIP_CALLS_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/include/platform_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/include/platform_def.h new file mode 100644 index 0000000..5d801cf --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/include/platform_def.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include +#include +#include + +#define DEBUG_XLAT_TABLE 0 + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#if DEBUG_XLAT_TABLE +#define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL1 +#define PLATFORM_STACK_SIZE 0x440 +#elif IMAGE_BL2 +#define PLATFORM_STACK_SIZE 0x400 +#elif IMAGE_BL31 +#define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL32 +#define PLATFORM_STACK_SIZE 0x440 +#endif + +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" + +#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 +#define PLATFORM_SYSTEM_COUNT 1 +#define PLATFORM_CLUSTER_COUNT 2 +#define PLATFORM_CLUSTER0_CORE_COUNT 4 +#define PLATFORM_CLUSTER1_CORE_COUNT 4 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ + PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ + PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) + +#define PLAT_RK_CLST_TO_CPUID_SHIFT 8 + +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 + +/* + * This macro defines the deepest retention state possible. A higher state + * id will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE 1 + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE 2 + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +/* TF txet, ro, rw, Size: 512KB */ +#define TZRAM_BASE (0x0) +#define TZRAM_SIZE (0x80000) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted RAM + */ +#define BL31_BASE (TZRAM_BASE + 0x10000) +#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define ADDR_SPACE_SIZE (1ull << 32) +#define MAX_XLAT_TABLES 8 +#define MAX_MMAP_REGIONS 16 + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +/* + * Define GICD and GICC and GICR base + */ +#define PLAT_RK_GICD_BASE RK3368_GICD_BASE +#define PLAT_RK_GICC_BASE RK3368_GICC_BASE + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_RK_G1S_IRQS RK_G1S_IRQS + +#define PLAT_RK_UART_BASE RK3368_UART2_BASE +#define PLAT_RK_UART_CLOCK RK3368_UART_CLOCK +#define PLAT_RK_UART_BAUDRATE RK3368_BAUDRATE + +#define PLAT_RK_CCI_BASE CCI400_BASE + +#define PLAT_RK_PRIMARY_CPU 0x0 + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/plat_sip_calls.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/plat_sip_calls.c new file mode 100644 index 0000000..3d2f39a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/plat_sip_calls.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include + +uint64_t rockchip_plat_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + switch (smc_fid) { + default: + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/platform.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/platform.mk new file mode 100644 index 0000000..73a56e3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/platform.mk @@ -0,0 +1,78 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +RK_PLAT := plat/rockchip +RK_PLAT_SOC := ${RK_PLAT}/${PLAT} +RK_PLAT_COMMON := ${RK_PLAT}/common + +PLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \ + -I${RK_PLAT_COMMON}/include/ \ + -I${RK_PLAT_COMMON}/pmusram \ + -I${RK_PLAT_COMMON}/drivers/pmu/ \ + -I${RK_PLAT_SOC}/ \ + -I${RK_PLAT_SOC}/drivers/pmu/ \ + -I${RK_PLAT_SOC}/drivers/soc/ \ + -I${RK_PLAT_SOC}/drivers/ddr/ \ + -I${RK_PLAT_SOC}/include/ + +RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + plat/common/plat_gicv2.c \ + ${RK_PLAT}/common/rockchip_gicv2.c + +PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ + lib/xlat_tables/aarch64/xlat_tables.c \ + plat/common/aarch64/plat_common.c \ + plat/common/plat_psci_common.c + +BL31_SOURCES += ${RK_GIC_SOURCES} \ + drivers/arm/cci/cci.c \ + drivers/console/aarch64/console.S \ + drivers/ti/uart/aarch64/16550_console.S \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + lib/cpus/aarch64/cortex_a53.S \ + plat/common/aarch64/platform_mp_stack.S \ + ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \ + ${RK_PLAT_COMMON}/bl31_plat_setup.c \ + ${RK_PLAT_COMMON}/params_setup.c \ + ${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \ + ${RK_PLAT_COMMON}/pmusram/pmu_sram.c \ + ${RK_PLAT_COMMON}/plat_pm.c \ + ${RK_PLAT_COMMON}/plat_topology.c \ + ${RK_PLAT_COMMON}/aarch64/platform_common.c \ + ${RK_PLAT_COMMON}/rockchip_sip_svc.c \ + ${RK_PLAT_SOC}/plat_sip_calls.c \ + ${RK_PLAT_SOC}/drivers/pmu/pmu.c \ + ${RK_PLAT_SOC}/drivers/soc/soc.c \ + ${RK_PLAT_SOC}/drivers/ddr/ddr_rk3368.c \ + +ENABLE_PLAT_COMPAT := 0 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/rk3368_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/rk3368_def.h new file mode 100644 index 0000000..01e4910 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3368/rk3368_def.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_DEF_H__ +#define __PLAT_DEF_H__ + +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + +#define CCI400_BASE 0xffb90000 +#define CCI400_SIZE 0x10000 + +#define GIC400_BASE 0xffb70000 +#define GIC400_SIZE 0x10000 + +#define STIME_BASE 0xff830000 +#define STIME_SIZE 0x10000 + +#define CRU_BASE 0xff760000 +#define CRU_SIZE 0x10000 + +#define GRF_BASE 0xff770000 +#define GRF_SIZE 0x10000 + +#define SGRF_BASE 0xff740000 +#define SGRF_SIZE 0x10000 + +#define PMU_BASE 0xff730000 +#define PMU_GRF_BASE 0xff738000 +#define PMU_SIZE 0x10000 + +#define RK_INTMEM_BASE 0xff8c0000 +#define RK_INTMEM_SIZE 0x10000 + +#define UART_DBG_BASE 0xff690000 +#define UART_DBG_SIZE 0x10000 + +#define CRU_BASE 0xff760000 + +#define PMUSRAM_BASE 0xff720000 +#define PMUSRAM_SIZE 0x10000 +#define PMUSRAM_RSIZE 0x1000 + +#define DDR_PCTL_BASE 0xff610000 +#define DDR_PCTL_SIZE 0x10000 + +#define DDR_PHY_BASE 0xff620000 +#define DDR_PHY_SIZE 0x10000 + +#define SERVICE_BUS_BASE 0xffac0000 +#define SERVICE_BUS_SISE 0x50000 + +#define COLD_BOOT_BASE 0xffff0000 +/************************************************************************** + * UART related constants + **************************************************************************/ +#define RK3368_UART2_BASE UART_DBG_BASE +#define RK3368_BAUDRATE 115200 +#define RK3368_UART_CLOCK 24000000 + +/****************************************************************************** + * System counter frequency related constants + ******************************************************************************/ +#define SYS_COUNTER_FREQ_IN_TICKS 24000000 + +/****************************************************************************** + * GIC-400 & interrupt handling related constants + ******************************************************************************/ + +/* Base rk_platform compatible GIC memory map */ +#define RK3368_GICD_BASE (GIC400_BASE + 0x1000) +#define RK3368_GICC_BASE (GIC400_BASE + 0x2000) +#define RK3368_GICR_BASE 0 /* no GICR in GIC-400 */ + +/***************************************************************************** + * CCI-400 related constants + ******************************************************************************/ +#define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 3 +#define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 4 + +/****************************************************************************** + * sgi, ppi + ******************************************************************************/ +#define RK_IRQ_SEC_PHY_TIMER 29 + +#define RK_IRQ_SEC_SGI_0 8 +#define RK_IRQ_SEC_SGI_1 9 +#define RK_IRQ_SEC_SGI_2 10 +#define RK_IRQ_SEC_SGI_3 11 +#define RK_IRQ_SEC_SGI_4 12 +#define RK_IRQ_SEC_SGI_5 13 +#define RK_IRQ_SEC_SGI_6 14 +#define RK_IRQ_SEC_SGI_7 15 + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define RK_G1S_IRQS (RK_IRQ_SEC_PHY_TIMER) + +#endif /* __PLAT_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dcf_code.inc b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dcf_code.inc new file mode 100644 index 0000000..53196a0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dcf_code.inc @@ -0,0 +1,364 @@ + 0x0 , + 0x4f8c120c , + 0x0 , + 0x4f8c1210 , + 0x100000 , + 0x1f310019 , + 0x0 , + 0xb0000001 , + 0x58 , + 0xd0000000 , + 0x1300 , + 0x1f760329 , + 0x0 , + 0xb0000001 , + 0x40 , + 0xd0000000 , + 0xc , + 0x1f760371 , + 0x0 , + 0xb0000001 , + 0x28 , + 0xd0000000 , + 0x400000 , + 0x1f900009 , + 0x0 , + 0xb0000001 , + 0x10 , + 0xd0000000 , + 0x1 , + 0x4f8c120c , + 0x100000 , + 0x1f310019 , + 0x0 , + 0xb0000001 , + 0x58 , + 0xd0000000 , + 0x2c00 , + 0x1f760329 , + 0x0 , + 0xb0000001 , + 0x40 , + 0xd0000000 , + 0xc0 , + 0x1f760371 , + 0x0 , + 0xb0000001 , + 0x28 , + 0xd0000000 , + 0x400000 , + 0x1f8f0009 , + 0x0 , + 0xb0000001 , + 0x10 , + 0xd0000000 , + 0x1 , + 0x4f8c1210 , + 0x0 , + 0x4f8c1220 , + 0x0 , + 0x4f8c121c , + 0x0 , + 0xaf8c120d , + 0x108 , + 0xd0000000 , + 0x2000 , + 0x1f900009 , + 0x0 , + 0xa0000001 , + 0x30 , + 0xd0000000 , + 0x0 , + 0x4f8c1220 , + 0x0 , + 0x4f8c121c , + 0x0 , + 0x10000001 , + 0x0 , + 0xa0000001 , + 0xb0 , + 0xd0000000 , + 0x8000 , + 0x1f900009 , + 0x0 , + 0xa0000001 , + 0x30 , + 0xd0000000 , + 0x1 , + 0x4f8c1220 , + 0x1 , + 0x4f8c121c , + 0x0 , + 0x10000001 , + 0x0 , + 0xa0000001 , + 0x70 , + 0xd0000000 , + 0x4000 , + 0x1f900009 , + 0x0 , + 0xa0000001 , + 0x30 , + 0xd0000000 , + 0x0 , + 0x4f8c1220 , + 0x1 , + 0x4f8c121c , + 0x0 , + 0x10000001 , + 0x0 , + 0xa0000001 , + 0x30 , + 0xd0000000 , + 0x1000 , + 0x1f900009 , + 0x0 , + 0xa0000001 , + 0x18 , + 0xd0000000 , + 0x0 , + 0x4f8c1220 , + 0x1 , + 0x4f8c121c , + 0x0 , + 0x10000001 , + 0x0 , + 0xa0000001 , + 0x100 , + 0xd0000000 , + 0x0 , + 0xaf8c1211 , + 0xf0 , + 0xd0000000 , + 0x2000 , + 0x1f8f0009 , + 0x0 , + 0xa0000001 , + 0x30 , + 0xd0000000 , + 0x0 , + 0x4f8c1220 , + 0x0 , + 0x4f8c121c , + 0x0 , + 0x10000001 , + 0x0 , + 0xa0000001 , + 0xb0 , + 0xd0000000 , + 0x8000 , + 0x1f8f0009 , + 0x0 , + 0xa0000001 , + 0x30 , + 0xd0000000 , + 0x1 , + 0x4f8c1220 , + 0x1 , + 0x4f8c121c , + 0x0 , + 0x10000001 , + 0x0 , + 0xa0000001 , + 0x70 , + 0xd0000000 , + 0x4000 , + 0x1f8f0009 , + 0x0 , + 0xa0000001 , + 0x30 , + 0xd0000000 , + 0x0 , + 0x4f8c1220 , + 0x1 , + 0x4f8c121c , + 0x0 , + 0x10000001 , + 0x0 , + 0xa0000001 , + 0x30 , + 0xd0000000 , + 0x1000 , + 0x1f8f0009 , + 0x0 , + 0xa0000001 , + 0x18 , + 0xd0000000 , + 0x0 , + 0x4f8c1220 , + 0x1 , + 0x4f8c121c , + 0x0 , + 0xaf8c120d , + 0x40 , + 0xd0000000 , + 0x80008000 , + 0x7f900284 , + 0x1 , + 0x0 , + 0x8000 , + 0x1f90028d , + 0x0 , + 0x60000001 , + 0x0 , + 0x10000001 , + 0x0 , + 0xa0000001 , + 0x38 , + 0xd0000000 , + 0x0 , + 0xaf8c1211 , + 0x28 , + 0xd0000000 , + 0x80008000 , + 0x7f8f0284 , + 0x1 , + 0x0 , + 0x8000 , + 0x1f8f028d , + 0x0 , + 0x60000001 , + 0xffffffff , + 0x4f77e200 , + 0xffffffff , + 0x4f77e204 , + 0xffffffff , + 0x4f77e208 , + 0xffffffff , + 0x4f77e20c , + 0x70007000 , + 0x4f77e210 , + 0x3fffffff , + 0x7f750130 , + 0x0 , + 0x2f310061 , + 0xc0000 , + 0x20000001 , + 0x0 , + 0x4f310061 , + 0xc0000 , + 0x1f310065 , + 0xc0000 , + 0xb0000001 , + 0x10 , + 0xc0000000 , + 0x0 , + 0xaf8c121d , + 0x48 , + 0xd0000000 , + 0x0 , + 0xaf8c120d , + 0x18 , + 0xd0000000 , + 0x80000000 , + 0x2f90000d , + 0x0 , + 0x4f90000d , + 0x0 , + 0xaf8c1211 , + 0x18 , + 0xd0000000 , + 0x80000000 , + 0x2f90000d , + 0x0 , + 0x4f8f000d , + 0x0 , + 0x2f8c101d , + 0x350005 , + 0x20000001 , + 0x0 , + 0x4f620001 , + 0x1 , + 0x0 , + 0x4 , + 0x1f620011 , + 0x0 , + 0x60000001 , + 0x3000000 , + 0x7f76004c , + 0x18 , + 0x0 , + 0x10001 , + 0x7f76004c , + 0x0 , + 0x2f8c1005 , + 0x0 , + 0x4f760041 , + 0x0 , + 0x2f8c1009 , + 0x0 , + 0x4f760045 , + 0x10000 , + 0x7f76004c , + 0x18 , + 0x0 , + 0x1 , + 0x0 , + 0x80000000 , + 0x1f760049 , + 0x0 , + 0x60000001 , + 0x3000100 , + 0x7f76004c , + 0x3e8 , + 0x0 , + 0x20002 , + 0x4f620000 , + 0x1 , + 0x0 , + 0x1 , + 0x1f620011 , + 0x0 , + 0x60000001 , + 0x0 , + 0xaf8c121d , + 0x48 , + 0xd0000000 , + 0x0 , + 0xaf8c120d , + 0x18 , + 0xd0000000 , + 0x7fffffff , + 0x1f90000d , + 0x0 , + 0x4f90000d , + 0x0 , + 0xaf8c1211 , + 0x18 , + 0xd0000000 , + 0x7fffffff , + 0x1f90000d , + 0x0 , + 0x4f8f000d , + 0xfff3ffff , + 0x1f310061 , + 0x0 , + 0x7f310061 , + 0xc0000 , + 0x1f310065 , + 0x0 , + 0xb0000001 , + 0x10 , + 0xc0000000 , + 0x0 , + 0x7f750130 , + 0x1 , + 0x0 , + 0x1 , + 0x0 , + 0x1 , + 0x0 , + 0x1 , + 0x0 , + 0x1 , + 0x0 , + 0x1 , + 0x0 , + 0x1 , + 0x0 , + 0x1 , + 0x0 , + 0x1 , + 0x0 , + 0x0 , + 0xe0000000 , diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram.c new file mode 100644 index 0000000..94aa076 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram.c @@ -0,0 +1,2567 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include "dram.h" +#include "dram_spec_timing.h" +#include "string.h" +#include "soc.h" +#include "pmu.h" + +#include + +#define CTL_TRAINING (1) +#define PI_TRAINING (!CTL_TRAINING) + +#define EN_READ_GATE_TRAINING (1) +#define EN_CA_TRAINING (0) +#define EN_WRITE_LEVELING (0) +#define EN_READ_LEVELING (0) +#define EN_WDQ_LEVELING (0) + +#define ENPER_CS_TRAINING_FREQ (933) + +struct pll_div { + unsigned int mhz; + unsigned int refdiv; + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int postdiv2; + unsigned int frac; + unsigned int freq; +}; + +static const struct pll_div dpll_rates_table[] = { + + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2 */ + {.mhz = 933, .refdiv = 3, .fbdiv = 350, .postdiv1 = 3, .postdiv2 = 1}, + {.mhz = 800, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}, + {.mhz = 732, .refdiv = 1, .fbdiv = 61, .postdiv1 = 2, .postdiv2 = 1}, + {.mhz = 666, .refdiv = 1, .fbdiv = 111, .postdiv1 = 4, .postdiv2 = 1}, + {.mhz = 600, .refdiv = 1, .fbdiv = 50, .postdiv1 = 2, .postdiv2 = 1}, + {.mhz = 528, .refdiv = 1, .fbdiv = 66, .postdiv1 = 3, .postdiv2 = 1}, + {.mhz = 400, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}, + {.mhz = 300, .refdiv = 1, .fbdiv = 50, .postdiv1 = 4, .postdiv2 = 1}, + {.mhz = 200, .refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2}, +}; + +static struct rk3399_ddr_cic_regs *const rk3399_ddr_cic = (void *)CIC_BASE; +static struct rk3399_ddr_pctl_regs *const rk3399_ddr_pctl[2] = { + (void *)DDRC0_BASE, (void *)DDRC1_BASE +}; + +static struct rk3399_ddr_pi_regs *const rk3399_ddr_pi[2] = { + (void *)DDRC0_PI_BASE, (void *)DDRC1_PI_BASE +}; + +static struct rk3399_ddr_publ_regs *const rk3399_ddr_publ[2] = { + (void *)DDRC0_PHY_BASE, (void *)DDRC1_PHY_BASE +}; + +struct rk3399_dram_status { + uint32_t current_index; + uint32_t index_freq[2]; + uint32_t low_power_stat; + struct timing_related_config timing_config; + struct drv_odt_lp_config drv_odt_lp_cfg; +}; + +static struct rk3399_dram_status rk3399_dram_status; +static struct ddr_dts_config_timing dts_parameter = { + .available = 0 +}; + +static struct rk3399_sdram_default_config ddr3_default_config = { + .bl = 8, + .ap = 0, + .dramds = 40, + .dramodt = 120, + .burst_ref_cnt = 1, + .zqcsi = 0 +}; + +static struct drv_odt_lp_config ddr3_drv_odt_default_config = { + .ddr3_speed_bin = DDR3_DEFAULT, + .pd_idle = 0, + .sr_idle = 0, + .sr_mc_gate_idle = 0, + .srpd_lite_idle = 0, + .standby_idle = 0, + + .ddr3_dll_dis_freq = 300, + .phy_dll_dis_freq = 125, + .odt_dis_freq = 933, + + .dram_side_drv = 40, + .dram_side_dq_odt = 120, + .dram_side_ca_odt = 120, + + .phy_side_ca_drv = 40, + .phy_side_ck_cs_drv = 40, + .phy_side_dq_drv = 40, + .phy_side_odt = 240, +}; + +static struct rk3399_sdram_default_config lpddr3_default_config = { + .bl = 8, + .ap = 0, + .dramds = 34, + .dramodt = 240, + .burst_ref_cnt = 1, + .zqcsi = 0 +}; + +static struct drv_odt_lp_config lpddr3_drv_odt_default_config = { + .ddr3_speed_bin = DDR3_DEFAULT, + .pd_idle = 0, + .sr_idle = 0, + .sr_mc_gate_idle = 0, + .srpd_lite_idle = 0, + .standby_idle = 0, + + .ddr3_dll_dis_freq = 300, + .phy_dll_dis_freq = 125, + .odt_dis_freq = 666, + + .dram_side_drv = 40, + .dram_side_dq_odt = 120, + .dram_side_ca_odt = 120, + + .phy_side_ca_drv = 40, + .phy_side_ck_cs_drv = 40, + .phy_side_dq_drv = 40, + .phy_side_odt = 240, +}; + +static struct rk3399_sdram_default_config lpddr4_default_config = { + .bl = 16, + .ap = 0, + .dramds = 40, + .dramodt = 240, + .caodt = 240, + .burst_ref_cnt = 1, + .zqcsi = 0 +}; + +static struct drv_odt_lp_config lpddr4_drv_odt_default_config = { + .ddr3_speed_bin = DDR3_DEFAULT, + .pd_idle = 0, + .sr_idle = 0, + .sr_mc_gate_idle = 0, + .srpd_lite_idle = 0, + .standby_idle = 0, + + .ddr3_dll_dis_freq = 300, + .phy_dll_dis_freq = 125, + .odt_dis_freq = 933, + + .dram_side_drv = 60, + .dram_side_dq_odt = 40, + .dram_side_ca_odt = 40, + + .phy_side_ca_drv = 40, + .phy_side_ck_cs_drv = 80, + .phy_side_dq_drv = 80, + .phy_side_odt = 60, +}; + +uint32_t dcf_code[] = { +#include "dcf_code.inc" +}; + + +#define write_32(addr, value)\ + mmio_write_32((uintptr_t)(addr), (uint32_t)(value)) + +#define read_32(addr) \ + mmio_read_32((uintptr_t)(addr)) +#define clrbits_32(addr, clear)\ + mmio_clrbits_32((uintptr_t)(addr), (uint32_t)(clear)) +#define setbits_32(addr, set)\ + mmio_setbits_32((uintptr_t)(addr), (uint32_t)(set)) +#define clrsetbits_32(addr, clear, set)\ + mmio_clrsetbits_32((uintptr_t)(addr), (uint32_t)(clear),\ + (uint32_t)(set)) + +#define DCF_START_ADDR (SRAM_BASE + 0x1400) +#define DCF_PARAM_ADDR (SRAM_BASE + 0x1000) + +/* DCF_PAMET */ +#define PARAM_DRAM_FREQ (0) +#define PARAM_DPLL_CON0 (4) +#define PARAM_DPLL_CON1 (8) +#define PARAM_DPLL_CON2 (0xc) +#define PARAM_DPLL_CON3 (0x10) +#define PARAM_DPLL_CON4 (0x14) +#define PARAM_DPLL_CON5 (0x18) +/* equal to fn<<4 */ +#define PARAM_FREQ_SELECT (0x1c) + +static unsigned int get_cs_die_capability(struct rk3399_sdram_config + *psdram_config, unsigned int channel, + unsigned int cs) +{ + unsigned int die; + unsigned int cs_cap; + unsigned int row[2]; + + row[0] = psdram_config->ch[channel].cs0_row; + row[1] = psdram_config->ch[channel].cs1_row; + die = psdram_config->ch[channel].bus_width / + psdram_config->ch[channel].each_die_bus_width; + cs_cap = (1 << (row[cs] + + (psdram_config->ch[channel].bank / 4 + 1) + + psdram_config->ch[channel].col + + (psdram_config->ch[channel].bus_width / 16))); + if (psdram_config->ch[channel].each_die_6gb_or_12gb) + cs_cap = cs_cap * 3 / 4; + + return (cs_cap / die); +} + +static void sdram_config_init(struct rk3399_sdram_config *psdram_config) +{ + uint32_t os_reg2_val, i; + + os_reg2_val = read_32(PMUGRF_BASE + PMUGRF_OSREG(2)); + + for (i = 0; i < READ_CH_CNT(os_reg2_val); i++) { + psdram_config->ch[i].bank = 1 << READ_BK_INFO(os_reg2_val, i); + psdram_config->ch[i].bus_width = + 8 * (1 << READ_BW_INFO(os_reg2_val, i)); + psdram_config->ch[i].col = READ_COL_INFO(os_reg2_val, i); + psdram_config->ch[i].cs0_row = + READ_CS0_ROW_INFO(os_reg2_val, i); + psdram_config->ch[i].cs1_row = + READ_CS1_ROW_INFO(os_reg2_val, i); + psdram_config->ch[i].cs_cnt = READ_CS_INFO(os_reg2_val, i); + psdram_config->ch[i].each_die_6gb_or_12gb = + READ_CH_ROW_INFO(os_reg2_val, i); + psdram_config->ch[i].each_die_bus_width = + 8 * (1 << READ_DIE_BW_INFO(os_reg2_val, i)); + } + psdram_config->dramtype = READ_DRAMTYPE_INFO(os_reg2_val); + psdram_config->channal_num = READ_CH_CNT(os_reg2_val); +} + +static void drv_odt_lp_cfg_init(uint32_t dram_type, + struct ddr_dts_config_timing *dts_timing, + struct drv_odt_lp_config *drv_config) +{ + if ((dts_timing) && (dts_timing->available)) { + drv_config->ddr3_speed_bin = dts_timing->ddr3_speed_bin; + drv_config->pd_idle = dts_timing->pd_idle; + drv_config->sr_idle = dts_timing->sr_idle; + drv_config->sr_mc_gate_idle = dts_timing->sr_mc_gate_idle; + drv_config->srpd_lite_idle = dts_timing->srpd_lite_idle; + drv_config->standby_idle = dts_timing->standby_idle; + drv_config->ddr3_dll_dis_freq = dts_timing->ddr3_dll_dis_freq; + drv_config->phy_dll_dis_freq = dts_timing->phy_dll_dis_freq; + } + + switch (dram_type) { + case DDR3: + if ((dts_timing) && (dts_timing->available)) { + drv_config->odt_dis_freq = + dts_timing->ddr3_odt_dis_freq; + drv_config->dram_side_drv = dts_timing->ddr3_drv; + drv_config->dram_side_dq_odt = dts_timing->ddr3_odt; + drv_config->phy_side_ca_drv = + dts_timing->phy_ddr3_ca_drv; + drv_config->phy_side_ck_cs_drv = + dts_timing->phy_ddr3_ca_drv; + drv_config->phy_side_dq_drv = + dts_timing->phy_ddr3_dq_drv; + drv_config->phy_side_odt = dts_timing->phy_ddr3_odt; + } else { + memcpy(drv_config, &ddr3_drv_odt_default_config, + sizeof(struct drv_odt_lp_config)); + } + break; + case LPDDR3: + if ((dts_timing) && (dts_timing->available)) { + drv_config->odt_dis_freq = + dts_timing->lpddr3_odt_dis_freq; + drv_config->dram_side_drv = dts_timing->lpddr3_drv; + drv_config->dram_side_dq_odt = dts_timing->lpddr3_odt; + drv_config->phy_side_ca_drv = + dts_timing->phy_lpddr3_ca_drv; + drv_config->phy_side_ck_cs_drv = + dts_timing->phy_lpddr3_ca_drv; + drv_config->phy_side_dq_drv = + dts_timing->phy_lpddr3_dq_drv; + drv_config->phy_side_odt = dts_timing->phy_lpddr3_odt; + + } else { + memcpy(drv_config, &lpddr3_drv_odt_default_config, + sizeof(struct drv_odt_lp_config)); + } + break; + case LPDDR4: + default: + if ((dts_timing) && (dts_timing->available)) { + drv_config->odt_dis_freq = + dts_timing->lpddr4_odt_dis_freq; + drv_config->dram_side_drv = dts_timing->lpddr4_drv; + drv_config->dram_side_dq_odt = + dts_timing->lpddr4_dq_odt; + drv_config->dram_side_ca_odt = + dts_timing->lpddr4_ca_odt; + drv_config->phy_side_ca_drv = + dts_timing->phy_lpddr4_ca_drv; + drv_config->phy_side_ck_cs_drv = + dts_timing->phy_lpddr4_ck_cs_drv; + drv_config->phy_side_dq_drv = + dts_timing->phy_lpddr4_dq_drv; + drv_config->phy_side_odt = dts_timing->phy_lpddr4_odt; + } else { + memcpy(drv_config, &lpddr4_drv_odt_default_config, + sizeof(struct drv_odt_lp_config)); + } + break; + } + + switch (drv_config->phy_side_ca_drv) { + case 240: + drv_config->phy_side_ca_drv = PHY_DRV_ODT_240; + break; + case 120: + drv_config->phy_side_ca_drv = PHY_DRV_ODT_120; + break; + case 80: + drv_config->phy_side_ca_drv = PHY_DRV_ODT_80; + break; + case 60: + drv_config->phy_side_ca_drv = PHY_DRV_ODT_60; + break; + case 48: + drv_config->phy_side_ca_drv = PHY_DRV_ODT_48; + break; + case 40: + drv_config->phy_side_ca_drv = PHY_DRV_ODT_40; + break; + default: + drv_config->phy_side_ca_drv = PHY_DRV_ODT_34_3; + break; + }; + + switch (drv_config->phy_side_ck_cs_drv) { + case 240: + drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_240; + break; + case 120: + drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_120; + break; + case 80: + drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_80; + break; + case 60: + drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_60; + break; + case 48: + drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_48; + break; + case 40: + drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_40; + break; + default: + drv_config->phy_side_ck_cs_drv = PHY_DRV_ODT_34_3; + break; + } + + switch (drv_config->phy_side_dq_drv) { + case 240: + drv_config->phy_side_dq_drv = PHY_DRV_ODT_240; + break; + case 120: + drv_config->phy_side_dq_drv = PHY_DRV_ODT_120; + break; + case 80: + drv_config->phy_side_dq_drv = PHY_DRV_ODT_80; + break; + case 60: + drv_config->phy_side_dq_drv = PHY_DRV_ODT_60; + break; + case 48: + drv_config->phy_side_dq_drv = PHY_DRV_ODT_48; + break; + case 40: + drv_config->phy_side_dq_drv = PHY_DRV_ODT_40; + break; + default: + drv_config->phy_side_dq_drv = PHY_DRV_ODT_34_3; + break; + } + + switch (drv_config->phy_side_odt) { + case 240: + drv_config->phy_side_odt = PHY_DRV_ODT_240; + break; + case 120: + drv_config->phy_side_odt = PHY_DRV_ODT_120; + break; + case 80: + drv_config->phy_side_odt = PHY_DRV_ODT_80; + break; + case 60: + drv_config->phy_side_odt = PHY_DRV_ODT_60; + break; + case 48: + drv_config->phy_side_odt = PHY_DRV_ODT_48; + break; + case 40: + drv_config->phy_side_odt = PHY_DRV_ODT_40; + break; + default: + drv_config->phy_side_odt = PHY_DRV_ODT_34_3; + break; + } +} + +static void sdram_timing_cfg_init(struct timing_related_config *ptiming_config, + struct rk3399_sdram_config *psdram_config, + struct drv_odt_lp_config *drv_config) +{ + uint32_t i, j; + + for (i = 0; i < psdram_config->channal_num; i++) { + ptiming_config->dram_info[i].speed_rate = + drv_config->ddr3_speed_bin; + ptiming_config->dram_info[i].cs_cnt = + psdram_config->ch[i].cs_cnt; + for (j = 0; j < psdram_config->ch[i].cs_cnt; j++) { + ptiming_config->dram_info[i].per_die_capability[j] = + get_cs_die_capability(psdram_config, i, j); + } + } + ptiming_config->dram_type = psdram_config->dramtype; + ptiming_config->ch_cnt = psdram_config->channal_num; + switch (psdram_config->dramtype) { + case DDR3: + ptiming_config->bl = ddr3_default_config.bl; + ptiming_config->ap = ddr3_default_config.ap; + break; + case LPDDR3: + ptiming_config->bl = lpddr3_default_config.bl; + ptiming_config->ap = lpddr3_default_config.ap; + break; + case LPDDR4: + ptiming_config->bl = lpddr4_default_config.bl; + ptiming_config->ap = lpddr4_default_config.ap; + ptiming_config->rdbi = 0; + ptiming_config->wdbi = 0; + break; + } + ptiming_config->dramds = drv_config->dram_side_drv; + ptiming_config->dramodt = drv_config->dram_side_dq_odt; + ptiming_config->caodt = drv_config->dram_side_ca_odt; +} + +struct lat_adj_pair { + uint32_t cl; + uint32_t rdlat_adj; + uint32_t cwl; + uint32_t wrlat_adj; +}; + +const struct lat_adj_pair ddr3_lat_adj[] = { + {6, 5, 5, 4}, + {8, 7, 6, 5}, + {10, 9, 7, 6}, + {11, 9, 8, 7}, + {13, 0xb, 9, 8}, + {14, 0xb, 0xa, 9} +}; + +const struct lat_adj_pair lpddr3_lat_adj[] = { + {3, 2, 1, 0}, + {6, 5, 3, 2}, + {8, 7, 4, 3}, + {9, 8, 5, 4}, + {10, 9, 6, 5}, + {11, 9, 6, 5}, + {12, 0xa, 6, 5}, + {14, 0xc, 8, 7}, + {16, 0xd, 8, 7} +}; + +const struct lat_adj_pair lpddr4_lat_adj[] = { + {6, 5, 4, 2}, + {10, 9, 6, 4}, + {14, 0xc, 8, 6}, + {20, 0x11, 0xa, 8}, + {24, 0x15, 0xc, 0xa}, + {28, 0x18, 0xe, 0xc}, + {32, 0x1b, 0x10, 0xe}, + {36, 0x1e, 0x12, 0x10} +}; + +static uint32_t get_rdlat_adj(uint32_t dram_type, uint32_t cl) +{ + const struct lat_adj_pair *p; + uint32_t cnt; + uint32_t i; + + if (dram_type == DDR3) { + p = ddr3_lat_adj; + cnt = ARRAY_SIZE(ddr3_lat_adj); + } else if (dram_type == LPDDR3) { + p = lpddr3_lat_adj; + cnt = ARRAY_SIZE(lpddr3_lat_adj); + } else { + p = lpddr4_lat_adj; + cnt = ARRAY_SIZE(lpddr4_lat_adj); + } + + for (i = 0; i < cnt; i++) { + if (cl == p[i].cl) + return p[i].rdlat_adj; + } + /* fail */ + return 0xff; +} + +static uint32_t get_wrlat_adj(uint32_t dram_type, uint32_t cwl) +{ + const struct lat_adj_pair *p; + uint32_t cnt; + uint32_t i; + + if (dram_type == DDR3) { + p = ddr3_lat_adj; + cnt = ARRAY_SIZE(ddr3_lat_adj); + } else if (dram_type == LPDDR3) { + p = lpddr3_lat_adj; + cnt = ARRAY_SIZE(lpddr3_lat_adj); + } else { + p = lpddr4_lat_adj; + cnt = ARRAY_SIZE(lpddr4_lat_adj); + } + + for (i = 0; i < cnt; i++) { + if (cwl == p[i].cwl) + return p[i].wrlat_adj; + } + /* fail */ + return 0xff; +} + +#define PI_REGS_DIMM_SUPPORT (0) +#define PI_ADD_LATENCY (0) +#define PI_DOUBLEFREEK (1) + +#define PI_PAD_DELAY_PS_VALUE (1000) +#define PI_IE_ENABLE_VALUE (3000) +#define PI_TSEL_ENABLE_VALUE (700) + +static uint32_t get_pi_rdlat_adj(struct dram_timing_t *pdram_timing) +{ + /*[DLLSUBTYPE2] == "STD_DENALI_HS" */ + uint32_t rdlat, delay_adder, ie_enable, hs_offset, tsel_adder, + extra_adder, tsel_enable; + + ie_enable = PI_IE_ENABLE_VALUE; + tsel_enable = PI_TSEL_ENABLE_VALUE; + + rdlat = pdram_timing->cl + PI_ADD_LATENCY; + delay_adder = ie_enable / (1000000 / pdram_timing->mhz); + if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) + delay_adder++; + hs_offset = 0; + tsel_adder = 0; + extra_adder = 0; + /* rdlat = rdlat - (PREAMBLE_SUPPORT & 0x1); */ + tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); + if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) + tsel_adder++; + delay_adder = delay_adder - 1; + if (tsel_adder > delay_adder) + extra_adder = tsel_adder - delay_adder; + else + extra_adder = 0; + if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) + hs_offset = 2; + else + hs_offset = 1; + + if (delay_adder > (rdlat - 1 - hs_offset)) { + rdlat = rdlat - tsel_adder; + } else { + if ((rdlat - delay_adder) < 2) + rdlat = 2; + else + rdlat = rdlat - delay_adder - extra_adder; + } + + return rdlat; +} + +static uint32_t get_pi_wrlat(struct dram_timing_t *pdram_timing, + struct timing_related_config *timing_config) +{ + uint32_t tmp; + + if (timing_config->dram_type == LPDDR3) { + tmp = pdram_timing->cl; + if (tmp >= 14) + tmp = 8; + else if (tmp >= 10) + tmp = 6; + else if (tmp == 9) + tmp = 5; + else if (tmp == 8) + tmp = 4; + else if (tmp == 6) + tmp = 3; + else + tmp = 1; + } else { + tmp = 1; + } + + return tmp; +} + +static uint32_t get_pi_wrlat_adj(struct dram_timing_t *pdram_timing, + struct timing_related_config *timing_config) +{ + return get_pi_wrlat(pdram_timing, timing_config) + PI_ADD_LATENCY - 1; +} + +static uint32_t get_pi_tdfi_phy_rdlat(struct dram_timing_t *pdram_timing, + struct timing_related_config *timing_config) +{ + /* [DLLSUBTYPE2] == "STD_DENALI_HS" */ + uint32_t cas_lat, delay_adder, ie_enable, hs_offset, ie_delay_adder; + uint32_t mem_delay_ps, round_trip_ps; + uint32_t phy_internal_delay, lpddr_adder, dfi_adder, rdlat_delay; + + ie_enable = PI_IE_ENABLE_VALUE; + + delay_adder = ie_enable / (1000000 / pdram_timing->mhz); + if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) + delay_adder++; + delay_adder = delay_adder - 1; + if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) + hs_offset = 2; + else + hs_offset = 1; + + cas_lat = pdram_timing->cl + PI_ADD_LATENCY; + + if (delay_adder > (cas_lat - 1 - hs_offset)) { + ie_delay_adder = 0; + } else { + ie_delay_adder = ie_enable / (1000000 / pdram_timing->mhz); + if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) + ie_delay_adder++; + } + + if (timing_config->dram_type == DDR3) { + mem_delay_ps = 0; + } else if (timing_config->dram_type == LPDDR4) { + mem_delay_ps = 3600; + } else if (timing_config->dram_type == LPDDR3) { + mem_delay_ps = 5500; + } else { + printf("get_pi_tdfi_phy_rdlat:dramtype unsupport\n"); + return 0; + } + round_trip_ps = 1100 + 500 + mem_delay_ps + 500 + 600; + delay_adder = round_trip_ps / (1000000 / pdram_timing->mhz); + if ((round_trip_ps % (1000000 / pdram_timing->mhz)) != 0) + delay_adder++; + + phy_internal_delay = 5 + 2 + 4; + lpddr_adder = mem_delay_ps / (1000000 / pdram_timing->mhz); + if ((mem_delay_ps % (1000000 / pdram_timing->mhz)) != 0) + lpddr_adder++; + dfi_adder = 0; + phy_internal_delay = phy_internal_delay + 2; + rdlat_delay = delay_adder + phy_internal_delay + + ie_delay_adder + lpddr_adder + dfi_adder; + + rdlat_delay = rdlat_delay + 2; + return rdlat_delay; +} + +static uint32_t get_pi_todtoff_min(struct dram_timing_t *pdram_timing, + struct timing_related_config *timing_config) +{ + uint32_t tmp, todtoff_min_ps; + + if (timing_config->dram_type == LPDDR3) + todtoff_min_ps = 2500; + else if (timing_config->dram_type == LPDDR4) + todtoff_min_ps = 1500; + else + todtoff_min_ps = 0; + /* todtoff_min */ + tmp = todtoff_min_ps / (1000000 / pdram_timing->mhz); + if ((todtoff_min_ps % (1000000 / pdram_timing->mhz)) != 0) + tmp++; + return tmp; +} + +static uint32_t get_pi_todtoff_max(struct dram_timing_t *pdram_timing, + struct timing_related_config *timing_config) +{ + uint32_t tmp, todtoff_max_ps; + + if ((timing_config->dram_type == LPDDR4) + || (timing_config->dram_type == LPDDR3)) + todtoff_max_ps = 3500; + else + todtoff_max_ps = 0; + + /* todtoff_max */ + tmp = todtoff_max_ps / (1000000 / pdram_timing->mhz); + if ((todtoff_max_ps % (1000000 / pdram_timing->mhz)) != 0) + tmp++; + return tmp; +} + +static void gen_rk3399_ctl_params_f0(struct timing_related_config + *timing_config, + struct dram_timing_t *pdram_timing) +{ + uint32_t i; + uint32_t tmp, tmp1; + + for (i = 0; i < timing_config->ch_cnt; i++) { + if (timing_config->dram_type == DDR3) { + tmp = ((700000 + 10) * timing_config->freq + + 999) / 1000; + tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) + + pdram_timing->tmod + pdram_timing->tzqinit; + write_32(&rk3399_ddr_pctl[i]->denali_ctl[5], tmp); + + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[22], + 0xffff, pdram_timing->tdllk); + + write_32(&rk3399_ddr_pctl[i]->denali_ctl[32], + (pdram_timing->tmod << 8) | + pdram_timing->tmrd); + + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[59], + 0xffff << 16, + (pdram_timing->txsr - + pdram_timing->trcd) << 16); + } else if (timing_config->dram_type == LPDDR4) { + write_32(&rk3399_ddr_pctl[i]->denali_ctl[5], + pdram_timing->tinit1 + pdram_timing->tinit3); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[32], + (pdram_timing->tmrd << 8) | + pdram_timing->tmrd); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[59], + 0xffff << 16, pdram_timing->txsr << 16); + } else { + write_32(&rk3399_ddr_pctl[i]->denali_ctl[5], + pdram_timing->tinit1); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[7], + pdram_timing->tinit4); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[32], + (pdram_timing->tmrd << 8) | + pdram_timing->tmrd); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[59], + 0xffff << 16, pdram_timing->txsr << 16); + } + write_32(&rk3399_ddr_pctl[i]->denali_ctl[6], + pdram_timing->tinit3); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[8], + pdram_timing->tinit5); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[23], (0x7f << 16), + ((pdram_timing->cl * 2) << 16)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[23], (0x1f << 24), + (pdram_timing->cwl << 24)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], 0x3f, + pdram_timing->al); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[26], 0xffff << 16, + (pdram_timing->trc << 24) | + (pdram_timing->trrd << 16)); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[27], + (pdram_timing->tfaw << 24) | + (pdram_timing->trppb << 16) | + (pdram_timing->twtr << 8) | pdram_timing->tras_min); + + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[31], 0xff << 24, + max(4, pdram_timing->trtp) << 24); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[33], + (pdram_timing->tcke << 24) | pdram_timing->tras_max); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34], 0xff, + max(1, pdram_timing->tckesr)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[39], + (0x3f << 16) | (0xff << 8), + (pdram_timing->twr << 16) | + (pdram_timing->trcd << 8)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[42], 0x1f << 16, + pdram_timing->tmrz << 16); + tmp = pdram_timing->tdal ? pdram_timing->tdal : + (pdram_timing->twr + pdram_timing->trp); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[44], 0xff, tmp); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[45], 0xff, + pdram_timing->trp); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[48], + ((pdram_timing->trefi - 8) << 16) | + pdram_timing->trfc); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[52], 0xffff, + pdram_timing->txp); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[53], 0xffff << 16, + pdram_timing->txpdll << 16); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[55], 0xf << 24, + pdram_timing->tcscke << 24); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[55], 0xff, + pdram_timing->tmrri); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[56], + (pdram_timing->tzqcke << 24) | + (pdram_timing->tmrwckel << 16) | + (pdram_timing->tckehcs << 8) | pdram_timing->tckelcs); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60], 0xffff, + pdram_timing->txsnr); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[62], 0xffff << 16, + (pdram_timing->tckehcmd << 24) | + (pdram_timing->tckelcmd << 16)); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[63], + (pdram_timing->tckelpd << 24) | + (pdram_timing->tescke << 16) | + (pdram_timing->tsr << 8) | pdram_timing->tckckel); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[64], 0xfff, + (pdram_timing->tcmdcke << 8) | + pdram_timing->tcsckeh); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[92], + (0xffff << 8), + (pdram_timing->tcksrx << 16) | + (pdram_timing->tcksre << 8)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[108], (0x1 << 24), + (timing_config->dllbp << 24)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[122], + (0x3FF << 16), + (pdram_timing->tvrcg_enable << 16)); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[123], + (pdram_timing->tfc_long << 16) | + pdram_timing->tvrcg_disable); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[124], + (pdram_timing->tvref_long << 16) | + (pdram_timing->tckfspx << 8) | + pdram_timing->tckfspe); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[133], + (pdram_timing->mr[1] << 16) | pdram_timing->mr[0]); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[134], 0xffff, + pdram_timing->mr[2]); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[138], 0xffff, + pdram_timing->mr[3]); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[139], 0xff << 24, + pdram_timing->mr11 << 24); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[147], + (pdram_timing->mr[1] << 16) | pdram_timing->mr[0]); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[148], 0xffff, + pdram_timing->mr[2]); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[152], 0xffff, + pdram_timing->mr[3]); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[153], 0xff << 24, + pdram_timing->mr11 << 24); + if (timing_config->dram_type == LPDDR4) { + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[140], + 0xffff << 16, pdram_timing->mr12 << 16); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[142], + 0xffff << 16, pdram_timing->mr14 << 16); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[145], + 0xffff << 16, pdram_timing->mr22 << 16); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[154], + 0xffff << 16, pdram_timing->mr12 << 16); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[156], + 0xffff << 16, pdram_timing->mr14 << 16); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[159], + 0xffff << 16, pdram_timing->mr22 << 16); + } + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[179], 0xfff << 8, + pdram_timing->tzqinit << 8); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[180], + (pdram_timing->tzqcs << 16) | + (pdram_timing->tzqinit / 2)); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[181], + (pdram_timing->tzqlat << 16) | pdram_timing->tzqcal); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[212], 0xff << 8, + pdram_timing->todton << 8); + + if (timing_config->odt) { + setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213], + 1 << 16); + if (timing_config->freq < 400) + tmp = 4 << 24; + else + tmp = 8 << 24; + } else { + clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213], + 1 << 16); + tmp = 2 << 24; + } + + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[216], + 0x1f << 24, tmp); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[221], + (0x3 << 16) | (0xf << 8), + (pdram_timing->tdqsck << 16) | + (pdram_timing->tdqsck_max << 8)); + tmp = + (get_wrlat_adj(timing_config->dram_type, pdram_timing->cwl) + << 8) | get_rdlat_adj(timing_config->dram_type, + pdram_timing->cl); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[284], 0xffff, + tmp); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[82], 0xffff << 16, + (4 * pdram_timing->trefi) << 16); + + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[83], 0xffff, + (2 * pdram_timing->trefi) & 0xffff); + + if ((timing_config->dram_type == LPDDR3) || + (timing_config->dram_type == LPDDR4)) { + tmp = get_pi_wrlat(pdram_timing, timing_config); + tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); + tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; + } else { + tmp = 0; + } + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[214], 0x3f << 16, + (tmp & 0x3f) << 16); + + if ((timing_config->dram_type == LPDDR3) || + (timing_config->dram_type == LPDDR4)) { + /* min_rl_preamble= cl+TDQSCK_MIN-1 */ + tmp = pdram_timing->cl + + get_pi_todtoff_min(pdram_timing, timing_config) - 1; + /* todtoff_max */ + tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); + tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; + } else { + tmp = pdram_timing->cl - pdram_timing->cwl; + } + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[215], 0x3f << 8, + (tmp & 0x3f) << 8); + + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[275], 0xff << 16, + (get_pi_tdfi_phy_rdlat + (pdram_timing, timing_config) + & 0xff) << 16); + + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[277], 0xffff, + (2 * pdram_timing->trefi) & 0xffff); + + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[282], 0xffff, + (2 * pdram_timing->trefi) & 0xffff); + + write_32(&rk3399_ddr_pctl[i]->denali_ctl[283], + 20 * pdram_timing->trefi); + + /* CTL_308 TDFI_CALVL_CAPTURE_F0:RW:16:10 */ + tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; + if ((20000 % (1000000 / pdram_timing->mhz)) != 0) + tmp1++; + tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[308], 0x3ff << 16, + tmp << 16); + + /* CTL_308 TDFI_CALVL_CC_F0:RW:0:10 */ + tmp = tmp + 18; + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[308], 0x3ff, + tmp); + + /* CTL_314 TDFI_WRCSLAT_F0:RW:8:8 */ + tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); + if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { + if (tmp1 < 5) { + if (tmp1 == 0) + tmp = 0; + else + tmp = tmp1 - 1; + } else { + tmp = tmp1 - 5; + } + } else { + tmp = tmp1 - 2; + } + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff << 8, + tmp << 8); + + /* CTL_314 TDFI_RDCSLAT_F0:RW:0:8 */ + if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && + (pdram_timing->cl >= 5)) + tmp = pdram_timing->cl - 5; + else + tmp = pdram_timing->cl - 2; + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff, + tmp); + } +} + +static void gen_rk3399_ctl_params_f1(struct timing_related_config + *timing_config, + struct dram_timing_t *pdram_timing) +{ + uint32_t i; + uint32_t tmp, tmp1; + + for (i = 0; i < timing_config->ch_cnt; i++) { + if (timing_config->dram_type == DDR3) { + tmp = + ((700000 + 10) * timing_config->freq + + 999) / 1000; + tmp += + pdram_timing->txsnr + (pdram_timing->tmrd * 3) + + pdram_timing->tmod + pdram_timing->tzqinit; + write_32(&rk3399_ddr_pctl[i]->denali_ctl[9], tmp); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[22], + 0xffff << 16, pdram_timing->tdllk << 16); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34], + 0xffffff00, + (pdram_timing->tmod << 24) | + (pdram_timing->tmrd << 16) | + (pdram_timing->trtp << 8)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60], + 0xffff << 16, + (pdram_timing->txsr - + pdram_timing->trcd) << 16); + } else if (timing_config->dram_type == LPDDR4) { + write_32(&rk3399_ddr_pctl[i]->denali_ctl[9], + pdram_timing->tinit1 + pdram_timing->tinit3); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34], + 0xffffff00, + (pdram_timing->tmrd << 24) | + (pdram_timing->tmrd << 16) | + (pdram_timing->trtp << 8)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60], + 0xffff << 16, pdram_timing->txsr << 16); + } else { + write_32(&rk3399_ddr_pctl[i]->denali_ctl[9], + pdram_timing->tinit1); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[11], + pdram_timing->tinit4); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[34], + 0xffffff00, + (pdram_timing->tmrd << 24) | + (pdram_timing->tmrd << 16) | + (pdram_timing->trtp << 8)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[60], + 0xffff << 16, pdram_timing->txsr << 16); + } + write_32(&rk3399_ddr_pctl[i]->denali_ctl[10], + pdram_timing->tinit3); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[12], + pdram_timing->tinit5); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], (0x7f << 8), + ((pdram_timing->cl * 2) << 8)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], (0x1f << 16), + (pdram_timing->cwl << 16)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[24], 0x3f << 24, + pdram_timing->al << 24); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[28], 0xffffff00, + (pdram_timing->tras_min << 24) | + (pdram_timing->trc << 16) | + (pdram_timing->trrd << 8)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[29], 0xffffff, + (pdram_timing->tfaw << 16) | + (pdram_timing->trppb << 8) | pdram_timing->twtr); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[35], + (pdram_timing->tcke << 24) | pdram_timing->tras_max); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[36], 0xff, + max(1, pdram_timing->tckesr)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[39], + (0xff << 24), (pdram_timing->trcd << 24)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[40], + 0x3f, pdram_timing->twr); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[42], 0x1f << 24, + pdram_timing->tmrz << 24); + tmp = pdram_timing->tdal ? pdram_timing->tdal : + (pdram_timing->twr + pdram_timing->trp); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[44], 0xff << 8, + tmp << 8); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[45], 0xff << 8, + pdram_timing->trp << 8); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[49], + ((pdram_timing->trefi - 8) << 16) | + pdram_timing->trfc); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[52], 0xffff << 16, + pdram_timing->txp << 16); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[54], 0xffff, + pdram_timing->txpdll); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[55], 0xff << 8, + pdram_timing->tmrri << 8); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[57], + (pdram_timing->tmrwckel << 24) | + (pdram_timing->tckehcs << 16) | + (pdram_timing->tckelcs << 8) | pdram_timing->tcscke); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[58], 0xf, + pdram_timing->tzqcke); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[61], 0xffff, + pdram_timing->txsnr); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[64], 0xffff << 16, + (pdram_timing->tckehcmd << 24) | + (pdram_timing->tckelcmd << 16)); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[65], + (pdram_timing->tckelpd << 24) | + (pdram_timing->tescke << 16) | + (pdram_timing->tsr << 8) | pdram_timing->tckckel); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[66], 0xfff, + (pdram_timing->tcmdcke << 8) | + pdram_timing->tcsckeh); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[92], (0xff << 24), + (pdram_timing->tcksre << 24)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[93], 0xff, + pdram_timing->tcksrx); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[108], (0x1 << 25), + (timing_config->dllbp << 25)); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[125], + (pdram_timing->tvrcg_disable << 16) | + pdram_timing->tvrcg_enable); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[126], + (pdram_timing->tckfspx << 24) | + (pdram_timing->tckfspe << 16) | + pdram_timing->tfc_long); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[127], 0xffff, + pdram_timing->tvref_long); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[134], + 0xffff << 16, pdram_timing->mr[0] << 16); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[135], + (pdram_timing->mr[2] << 16) | pdram_timing->mr[1]); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[138], + 0xffff << 16, pdram_timing->mr[3] << 16); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[140], 0xff, + pdram_timing->mr11); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[148], + 0xffff << 16, pdram_timing->mr[0] << 16); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[149], + (pdram_timing->mr[2] << 16) | pdram_timing->mr[1]); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[152], + 0xffff << 16, pdram_timing->mr[3] << 16); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[154], 0xff, + pdram_timing->mr11); + if (timing_config->dram_type == LPDDR4) { + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[141], + 0xffff, pdram_timing->mr12); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[143], + 0xffff, pdram_timing->mr14); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[146], + 0xffff, pdram_timing->mr22); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[155], + 0xffff, pdram_timing->mr12); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[157], + 0xffff, pdram_timing->mr14); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[160], + 0xffff, pdram_timing->mr22); + } + write_32(&rk3399_ddr_pctl[i]->denali_ctl[182], + ((pdram_timing->tzqinit / 2) << 16) | + pdram_timing->tzqinit); + write_32(&rk3399_ddr_pctl[i]->denali_ctl[183], + (pdram_timing->tzqcal << 16) | pdram_timing->tzqcs); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[184], 0x3f, + pdram_timing->tzqlat); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[188], 0xfff, + pdram_timing->tzqreset); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[212], 0xff << 16, + pdram_timing->todton << 16); + + if (timing_config->odt) { + setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213], + (1 << 24)); + if (timing_config->freq < 400) + tmp = 4 << 24; + else + tmp = 8 << 24; + } else { + clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[213], + (1 << 24)); + tmp = 2 << 24; + } + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[217], 0x1f << 24, + tmp); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[221], 0xf << 24, + (pdram_timing->tdqsck_max << 24)); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[222], 0x3, + pdram_timing->tdqsck); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[291], 0xffff, + (get_wrlat_adj(timing_config->dram_type, + pdram_timing->cwl) << 8) | + get_rdlat_adj(timing_config->dram_type, + pdram_timing->cl)); + + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[84], 0xffff, + (4 * pdram_timing->trefi) & 0xffff); + + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[84], 0xffff << 16, + ((2 * pdram_timing->trefi) & 0xffff) << 16); + + if ((timing_config->dram_type == LPDDR3) || + (timing_config->dram_type == LPDDR4)) { + tmp = get_pi_wrlat(pdram_timing, timing_config); + tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); + tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; + } else { + tmp = 0; + } + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[214], 0x3f << 24, + (tmp & 0x3f) << 24); + + if ((timing_config->dram_type == LPDDR3) || + (timing_config->dram_type == LPDDR4)) { + /* min_rl_preamble= cl+TDQSCK_MIN-1 */ + tmp = pdram_timing->cl + + get_pi_todtoff_min(pdram_timing, timing_config) - 1; + /* todtoff_max */ + tmp1 = get_pi_todtoff_max(pdram_timing, timing_config); + tmp = (tmp > tmp1) ? (tmp - tmp1) : 0; + } else { + tmp = pdram_timing->cl - pdram_timing->cwl; + } + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[215], 0x3f << 16, + (tmp & 0x3f) << 16); + + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[275], 0xff << 24, + (get_pi_tdfi_phy_rdlat + (pdram_timing, timing_config) + & 0xff) << 24); + + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[284], + 0xffff << 16, + ((2 * pdram_timing->trefi) & 0xffff) << 16); + + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[289], 0xffff, + (2 * pdram_timing->trefi) & 0xffff); + + write_32(&rk3399_ddr_pctl[i]->denali_ctl[290], + 20 * pdram_timing->trefi); + + /* CTL_309 TDFI_CALVL_CAPTURE_F1:RW:16:10 */ + tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; + if ((20000 % (1000000 / pdram_timing->mhz)) != 0) + tmp1++; + tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[309], 0x3ff << 16, + tmp << 16); + + /* CTL_309 TDFI_CALVL_CC_F1:RW:0:10 */ + tmp = tmp + 18; + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[309], 0x3ff, + tmp); + + /* CTL_314 TDFI_WRCSLAT_F1:RW:24:8 */ + tmp1 = get_pi_wrlat_adj(pdram_timing, timing_config); + if (timing_config->freq <= ENPER_CS_TRAINING_FREQ) { + if (tmp1 < 5) { + if (tmp1 == 0) + tmp = 0; + else + tmp = tmp1 - 1; + } else { + tmp = tmp1 - 5; + } + } else { + tmp = tmp1 - 2; + } + + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff << 24, + tmp << 24); + + /* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */ + if ((timing_config->freq <= ENPER_CS_TRAINING_FREQ) && + (pdram_timing->cl >= 5)) + tmp = pdram_timing->cl - 5; + else + tmp = pdram_timing->cl - 2; + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[314], 0xff << 16, + tmp << 16); + } +} + +static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, + struct dram_timing_t *pdram_timing, + uint32_t fn) +{ + if (fn == 0) + gen_rk3399_ctl_params_f0(timing_config, pdram_timing); + else + gen_rk3399_ctl_params_f1(timing_config, pdram_timing); + +#if CTL_TRAINING + uint32_t i, tmp0, tmp1; + + tmp0 = tmp1 = 0; +#if EN_READ_GATE_TRAINING + tmp1 = 1; +#endif + +#if EN_CA_TRAINING + tmp0 |= (1 << 8); +#endif + +#if EN_WRITE_LEVELING + tmp0 |= (1 << 16); +#endif + +#if EN_READ_LEVELING + tmp0 |= (1 << 24); +#endif + for (i = 0; i < timing_config->ch_cnt; i++) { + if (tmp0 | tmp1) + setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[305], + 1 << 16); + if (tmp0) + setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[70], tmp0); + if (tmp1) + setbits_32(&rk3399_ddr_pctl[i]->denali_ctl[71], tmp1); + } +#endif +} + +static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config, + struct dram_timing_t *pdram_timing) +{ + uint32_t tmp, tmp1, tmp2; + uint32_t i; + + for (i = 0; i < timing_config->ch_cnt; i++) { + /* PI_02 PI_TDFI_PHYMSTR_MAX_F0:RW:0:32 */ + tmp = 4 * pdram_timing->trefi; + write_32(&rk3399_ddr_pi[i]->denali_pi[2], tmp); + /* PI_03 PI_TDFI_PHYMSTR_RESP_F0:RW:0:16 */ + tmp = 2 * pdram_timing->trefi; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[3], 0xffff, tmp); + /* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[7], 0xffff << 16, + tmp << 16); + + /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */ + if (timing_config->dram_type == LPDDR4) + tmp = 2; + else + tmp = 0; + tmp = (pdram_timing->bl / 2) + 4 + + (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + + get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[42], 0xff, tmp); + /* PI_43 PI_WRLAT_F0:RW:0:5 */ + if (timing_config->dram_type == LPDDR3) { + tmp = get_pi_wrlat(pdram_timing, timing_config); + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], 0x1f, + tmp); + } + /* PI_43 PI_ADDITIVE_LAT_F0:RW:8:6 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], 0x3f << 8, + PI_ADD_LATENCY << 8); + + /* PI_43 PI_CASLAT_LIN_F0:RW:16:7 */ + tmp = pdram_timing->cl * 2; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], 0x7f << 16, + tmp << 16); + /* PI_46 PI_TREF_F0:RW:16:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[46], 0xffff << 16, + pdram_timing->trefi << 16); + /* PI_46 PI_TRFC_F0:RW:0:10 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[46], 0x3ff, + pdram_timing->trfc); + /* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */ + if (timing_config->dram_type == LPDDR3) { + tmp = get_pi_todtoff_max(pdram_timing, timing_config); + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[66], + 0xff << 24, tmp << 24); + } + /* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */ + if ((timing_config->dram_type == LPDDR3) || + (timing_config->dram_type == LPDDR4)) { + tmp1 = get_pi_wrlat(pdram_timing, timing_config); + tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); + if (tmp1 > tmp2) + tmp = tmp1 - tmp2; + else + tmp = 0; + } else if (timing_config->dram_type == DDR3) { + tmp = 0; + } + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[72], 0x3f << 16, + tmp << 16); + /* PI_73 PI_RD_TO_ODTH_F0:RW:8:6 */ + if ((timing_config->dram_type == LPDDR3) || + (timing_config->dram_type == LPDDR4)) { + /* min_rl_preamble= cl+TDQSCK_MIN-1 */ + tmp1 = pdram_timing->cl + + get_pi_todtoff_min(pdram_timing, timing_config) - 1; + /* todtoff_max */ + tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); + if (tmp1 > tmp2) + tmp = tmp1 - tmp2; + else + tmp = 0; + } else if (timing_config->dram_type == DDR3) { + tmp = pdram_timing->cl - pdram_timing->cwl; + } + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[73], 0x3f << 8, + tmp << 8); + /* PI_89 PI_RDLAT_ADJ_F0:RW:16:8 */ + tmp = get_pi_rdlat_adj(pdram_timing); + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[89], 0xff << 16, + tmp << 16); + /* PI_90 PI_WRLAT_ADJ_F0:RW:16:8 */ + tmp = get_pi_wrlat_adj(pdram_timing, timing_config); + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[90], 0xff << 16, + tmp << 16); + /* PI_91 PI_TDFI_WRCSLAT_F0:RW:16:8 */ + tmp1 = tmp; + if (tmp1 < 5) { + if (tmp1 == 0) + tmp = 0; + else + tmp = tmp1 - 1; + } else { + tmp = tmp1 - 5; + } + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[91], 0xff << 16, + tmp << 16); + /* PI_95 PI_TDFI_CALVL_CAPTURE_F0:RW:16:10 */ + tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; + if ((20000 % (1000000 / pdram_timing->mhz)) != 0) + tmp1++; + tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[95], 0x3ff << 16, + tmp << 16); + /* PI_95 PI_TDFI_CALVL_CC_F0:RW:0:10 */ + tmp = tmp + 18; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[95], 0x3ff, tmp); + /* PI_102 PI_TMRZ_F0:RW:8:5 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[102], 0x1f << 8, + pdram_timing->tmrz << 8); + /* PI_111 PI_TDFI_CALVL_STROBE_F0:RW:8:4 */ + tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); + if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) + tmp1++; + /* pi_tdfi_calvl_strobe=tds_train+5 */ + tmp = tmp1 + 5; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[111], 0xf << 8, + tmp << 8); + /* PI_116 PI_TCKEHDQS_F0:RW:16:6 */ + tmp = 10000 / (1000000 / pdram_timing->mhz); + if ((10000 % (1000000 / pdram_timing->mhz)) != 0) + tmp++; + if (pdram_timing->mhz <= 100) + tmp = tmp + 1; + else + tmp = tmp + 8; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[116], 0x3f << 16, + tmp << 16); + /* PI_125 PI_MR1_DATA_F0_0:RW+:8:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[125], 0xffff << 8, + pdram_timing->mr[1] << 8); + /* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[133], 0xffff, + pdram_timing->mr[1]); + /* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[140], 0xffff << 16, + pdram_timing->mr[1] << 16); + /* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[148], 0xffff, + pdram_timing->mr[1]); + /* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[126], 0xffff, + pdram_timing->mr[2]); + /* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[133], 0xffff << 16, + pdram_timing->mr[2] << 16); + /* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[141], 0xffff, + pdram_timing->mr[2]); + /* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[148], 0xffff << 16, + pdram_timing->mr[2] << 16); + /* PI_156 PI_TFC_F0:RW:0:10 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[156], 0x3ff, + pdram_timing->trfc); + /* PI_158 PI_TWR_F0:RW:24:6 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0x3f << 24, + pdram_timing->twr << 24); + /* PI_158 PI_TWTR_F0:RW:16:6 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0x3f << 16, + pdram_timing->twtr << 16); + /* PI_158 PI_TRCD_F0:RW:8:8 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0xff << 8, + pdram_timing->trcd << 8); + /* PI_158 PI_TRP_F0:RW:0:8 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[158], 0xff, + pdram_timing->trp); + /* PI_157 PI_TRTP_F0:RW:24:8 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[157], 0xff << 24, + pdram_timing->trtp << 24); + /* PI_159 PI_TRAS_MIN_F0:RW:24:8 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[159], 0xff << 24, + pdram_timing->tras_min << 24); + /* PI_159 PI_TRAS_MAX_F0:RW:0:17 */ + tmp = pdram_timing->tras_max * 99 / 100; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[159], 0x1ffff, tmp); + /* PI_160 PI_TMRD_F0:RW:16:6 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[160], 0x3f << 16, + pdram_timing->tmrd << 16); + /*PI_160 PI_TDQSCK_MAX_F0:RW:0:4 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[160], 0xf, + pdram_timing->tdqsck_max); + /* PI_187 PI_TDFI_CTRLUPD_MAX_F0:RW:8:16 */ + tmp = 2 * pdram_timing->trefi; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[187], 0xffff << 8, + tmp << 8); + /* PI_188 PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32 */ + tmp = 20 * pdram_timing->trefi; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[188], 0xffffffff, + tmp); + } +} + +static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config, + struct dram_timing_t *pdram_timing) +{ + uint32_t tmp, tmp1, tmp2; + uint32_t i; + + for (i = 0; i < timing_config->ch_cnt; i++) { + /* PI_04 PI_TDFI_PHYMSTR_MAX_F1:RW:0:32 */ + tmp = 4 * pdram_timing->trefi; + write_32(&rk3399_ddr_pi[i]->denali_pi[4], tmp); + /* PI_05 PI_TDFI_PHYMSTR_RESP_F1:RW:0:16 */ + tmp = 2 * pdram_timing->trefi; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[5], 0xffff, tmp); + /* PI_12 PI_TDFI_PHYUPD_RESP_F1:RW:0:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[12], 0xffff, tmp); + + /* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:8:8 */ + if (timing_config->dram_type == LPDDR4) + tmp = 2; + else + tmp = 0; + tmp = (pdram_timing->bl / 2) + 4 + + (get_pi_rdlat_adj(pdram_timing) - 2) + tmp + + get_pi_tdfi_phy_rdlat(pdram_timing, timing_config); + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[42], 0xff << 8, + tmp << 8); + /* PI_43 PI_WRLAT_F1:RW:24:5 */ + if (timing_config->dram_type == LPDDR3) { + tmp = get_pi_wrlat(pdram_timing, timing_config); + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[43], + 0x1f << 24, tmp << 24); + } + /* PI_44 PI_ADDITIVE_LAT_F1:RW:0:6 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[44], 0x3f, + PI_ADD_LATENCY); + /* PI_44 PI_CASLAT_LIN_F1:RW:8:7:=0x18 */ + tmp = pdram_timing->cl * 2; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[44], 0x7f << 8, + tmp << 8); + /* PI_47 PI_TREF_F1:RW:16:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[47], 0xffff << 16, + pdram_timing->trefi << 16); + /* PI_47 PI_TRFC_F1:RW:0:10 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[47], 0x3ff, + pdram_timing->trfc); + /* PI_67 PI_TODTL_2CMD_F1:RW:8:8 */ + if (timing_config->dram_type == LPDDR3) { + tmp = get_pi_todtoff_max(pdram_timing, timing_config); + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[67], + 0xff << 8, tmp << 8); + } + /* PI_72 PI_WR_TO_ODTH_F1:RW:24:6 */ + if ((timing_config->dram_type == LPDDR3) + || (timing_config->dram_type == LPDDR4)) { + tmp1 = get_pi_wrlat(pdram_timing, timing_config); + tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); + if (tmp1 > tmp2) + tmp = tmp1 - tmp2; + else + tmp = 0; + } else if (timing_config->dram_type == DDR3) { + tmp = 0; + } + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[72], 0x3f << 24, + tmp << 24); + /* PI_73 PI_RD_TO_ODTH_F1:RW:16:6 */ + if ((timing_config->dram_type == LPDDR3) + || (timing_config->dram_type == LPDDR4)) { + /* min_rl_preamble= cl+TDQSCK_MIN-1 */ + tmp1 = + pdram_timing->cl + get_pi_todtoff_min(pdram_timing, + timing_config) + - 1; + /* todtoff_max */ + tmp2 = get_pi_todtoff_max(pdram_timing, timing_config); + if (tmp1 > tmp2) + tmp = tmp1 - tmp2; + else + tmp = 0; + } else if (timing_config->dram_type == DDR3) { + tmp = pdram_timing->cl - pdram_timing->cwl; + } + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[73], 0x3f << 16, + tmp << 16); + /*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */ + tmp = get_pi_rdlat_adj(pdram_timing); + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[89], 0xff << 24, + tmp << 24); + /* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */ + tmp = get_pi_wrlat_adj(pdram_timing, timing_config); + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[90], 0xff << 24, + tmp << 24); + /* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */ + tmp1 = tmp; + if (tmp1 < 5) { + if (tmp1 == 0) + tmp = 0; + else + tmp = tmp1 - 1; + } else { + tmp = tmp1 - 5; + } + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[91], 0xff << 24, + tmp << 24); + /*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */ + /* tadr=20ns */ + tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1; + if ((20000 % (1000000 / pdram_timing->mhz)) != 0) + tmp1++; + tmp = (tmp1 >> 1) + (tmp1 % 2) + 5; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[96], 0x3ff << 16, + tmp << 16); + /* PI_96 PI_TDFI_CALVL_CC_F1:RW:0:10 */ + tmp = tmp + 18; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[96], 0x3ff, tmp); + /*PI_103 PI_TMRZ_F1:RW:0:5 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[103], 0x1f, + pdram_timing->tmrz); + /*PI_111 PI_TDFI_CALVL_STROBE_F1:RW:16:4 */ + /* tds_train=ceil(2/ns) */ + tmp1 = 2 * 1000 / (1000000 / pdram_timing->mhz); + if ((2 * 1000 % (1000000 / pdram_timing->mhz)) != 0) + tmp1++; + /* pi_tdfi_calvl_strobe=tds_train+5 */ + tmp = tmp1 + 5; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[111], 0xf << 16, + tmp << 16); + /* PI_116 PI_TCKEHDQS_F1:RW:24:6 */ + tmp = 10000 / (1000000 / pdram_timing->mhz); + if ((10000 % (1000000 / pdram_timing->mhz)) != 0) + tmp++; + if (pdram_timing->mhz <= 100) + tmp = tmp + 1; + else + tmp = tmp + 8; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[116], 0x3f << 24, + tmp << 24); + /* PI_128 PI_MR1_DATA_F1_0:RW+:0:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[128], 0xffff, + pdram_timing->mr[1]); + /* PI_135 PI_MR1_DATA_F1_1:RW+:8:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[135], 0xffff << 8, + pdram_timing->mr[1] << 8); + /* PI_143 PI_MR1_DATA_F1_2:RW+:0:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[143], 0xffff, + pdram_timing->mr[1]); + /* PI_150 PI_MR1_DATA_F1_3:RW+:8:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[150], 0xffff << 8, + pdram_timing->mr[1] << 8); + /* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[128], 0xffff << 16, + pdram_timing->mr[2] << 16); + /* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[136], 0xffff, + pdram_timing->mr[2]); + /* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[143], 0xffff << 16, + pdram_timing->mr[2] << 16); + /* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[151], 0xffff, + pdram_timing->mr[2]); + /* PI_156 PI_TFC_F1:RW:16:10 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[156], 0x3ff << 16, + pdram_timing->trfc << 16); + /* PI_162 PI_TWR_F1:RW:8:6 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[162], 0x3f << 8, + pdram_timing->twr << 8); + /* PI_162 PI_TWTR_F1:RW:0:6 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[162], 0x3f, + pdram_timing->twtr); + /* PI_161 PI_TRCD_F1:RW:24:8 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[161], 0xff << 24, + pdram_timing->trcd << 24); + /* PI_161 PI_TRP_F1:RW:16:8 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[161], 0xff << 16, + pdram_timing->trp << 16); + /* PI_161 PI_TRTP_F1:RW:8:8 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[161], 0xff << 8, + pdram_timing->trtp << 8); + /* PI_163 PI_TRAS_MIN_F1:RW:24:8 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[163], 0xff << 24, + pdram_timing->tras_min << 24); + /* PI_163 PI_TRAS_MAX_F1:RW:0:17 */ + tmp = pdram_timing->tras_max * 99 / 100; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[163], 0x1ffff, tmp); + /* PI_164 PI_TMRD_F1:RW:16:6 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[164], 0x3f << 16, + pdram_timing->tmrd << 16); + /* PI_164 PI_TDQSCK_MAX_F1:RW:0:4 */ + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[164], 0xf, + pdram_timing->tdqsck_max); + /* PI_189 PI_TDFI_CTRLUPD_MAX_F1:RW:0:16 */ + tmp = 2 * pdram_timing->trefi; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[189], 0xffff, tmp); + /* PI_190 PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32 */ + tmp = 20 * pdram_timing->trefi; + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[190], 0xffffffff, + tmp); + } +} + +static void gen_rk3399_pi_params(struct timing_related_config *timing_config, + struct dram_timing_t *pdram_timing, + uint32_t fn) +{ + if (fn == 0) + gen_rk3399_pi_params_f0(timing_config, pdram_timing); + else + gen_rk3399_pi_params_f1(timing_config, pdram_timing); + +#if PI_TRAINING + uint32_t i; + + for (i = 0; i < timing_config->ch_cnt; i++) { +#if EN_READ_GATE_TRAINING + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[80], 3 << 24, + 2 << 24); +#endif + +#if EN_CA_TRAINING + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[100], 3 << 8, + 2 << 8); +#endif + +#if EN_WRITE_LEVELING + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[60], 3 << 8, + 2 << 8); +#endif + +#if EN_READ_LEVELING + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[80], 3 << 16, + 2 << 16); +#endif + +#if EN_WDQ_LEVELING + clrsetbits_32(&rk3399_ddr_pi[i]->denali_pi[124], 3 << 16, + 2 << 16); +#endif + } +#endif +} + +static void gen_rk3399_set_odt(uint32_t odt_en) +{ + uint32_t drv_odt_val; + uint32_t i; + + for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { + drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 16; + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[5], + 0x7 << 16, drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[133], + 0x7 << 16, drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[261], + 0x7 << 16, drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[389], + 0x7 << 16, drv_odt_val); + drv_odt_val = (odt_en | (0 << 1) | (0 << 2)) << 24; + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[6], + 0x7 << 24, drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[134], + 0x7 << 24, drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[262], + 0x7 << 24, drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[390], + 0x7 << 24, drv_odt_val); + } +} + +static void gen_rk3399_set_ds_odt(struct timing_related_config *timing_config, + struct drv_odt_lp_config *drv_config) +{ + uint32_t i, drv_odt_val; + + for (i = 0; i < timing_config->ch_cnt; i++) { + if (timing_config->dram_type == LPDDR4) + drv_odt_val = drv_config->phy_side_odt | + (PHY_DRV_ODT_Hi_Z << 4) | + (drv_config->phy_side_dq_drv << 8) | + (drv_config->phy_side_dq_drv << 12); + else if (timing_config->dram_type == LPDDR3) + drv_odt_val = PHY_DRV_ODT_Hi_Z | + (drv_config->phy_side_odt << 4) | + (drv_config->phy_side_dq_drv << 8) | + (drv_config->phy_side_dq_drv << 12); + else + drv_odt_val = drv_config->phy_side_odt | + (drv_config->phy_side_odt << 4) | + (drv_config->phy_side_dq_drv << 8) | + (drv_config->phy_side_dq_drv << 12); + + /* DQ drv odt set */ + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[6], 0xffffff, + drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[134], 0xffffff, + drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[262], 0xffffff, + drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[390], 0xffffff, + drv_odt_val); + /* DQS drv odt set */ + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[7], 0xffffff, + drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[135], 0xffffff, + drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[263], 0xffffff, + drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[391], 0xffffff, + drv_odt_val); + + gen_rk3399_set_odt(timing_config->odt); + + /* CA drv set */ + drv_odt_val = drv_config->phy_side_ca_drv | + (drv_config->phy_side_ca_drv << 4); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[544], 0xff, + drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[672], 0xff, + drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[800], 0xff, + drv_odt_val); + + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[928], 0xff, + drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[937], 0xff, + drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[935], 0xff, + drv_odt_val); + + drv_odt_val = drv_config->phy_side_ck_cs_drv | + (drv_config->phy_side_ck_cs_drv << 4); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[929], 0xff, + drv_odt_val); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[939], 0xff, + drv_odt_val); + } +} + +static void gen_rk3399_phy_params(struct timing_related_config *timing_config, + struct drv_odt_lp_config *drv_config, + struct dram_timing_t *pdram_timing, + uint32_t fn) +{ + uint32_t tmp, i, div, j; + uint32_t mem_delay_ps, pad_delay_ps, total_delay_ps, delay_frac_ps; + uint32_t trpre_min_ps, gate_delay_ps, gate_delay_frac_ps; + uint32_t ie_enable, tsel_enable, cas_lat, rddata_en_ie_dly, tsel_adder; + uint32_t extra_adder, delta, hs_offset; + + for (i = 0; i < timing_config->ch_cnt; i++) { + + pad_delay_ps = PI_PAD_DELAY_PS_VALUE; + ie_enable = PI_IE_ENABLE_VALUE; + tsel_enable = PI_TSEL_ENABLE_VALUE; + + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[896], + (0x3 << 8) | 1, fn << 8); + + /* PHY_LOW_FREQ_SEL */ + /* DENALI_PHY_913 1bit offset_0 */ + if (timing_config->freq > 400) + clrbits_32(&rk3399_ddr_publ[i]->denali_phy[913], 1); + else + setbits_32(&rk3399_ddr_publ[i]->denali_phy[913], 1); + + /* PHY_RPTR_UPDATE_x */ + /* DENALI_PHY_87/215/343/471 4bit offset_16 */ + tmp = 2500 / (1000000 / pdram_timing->mhz) + 3; + if ((2500 % (1000000 / pdram_timing->mhz)) != 0) + tmp++; + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[87], 0xf << 16, + tmp << 16); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[215], 0xf << 16, + tmp << 16); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[343], 0xf << 16, + tmp << 16); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[471], 0xf << 16, + tmp << 16); + + /* PHY_PLL_CTRL */ + /* DENALI_PHY_911 13bits offset_0 */ + /* PHY_LP4_BOOT_PLL_CTRL */ + /* DENALI_PHY_919 13bits offset_0 */ + if (pdram_timing->mhz <= 150) + tmp = 3; + else if (pdram_timing->mhz <= 300) + tmp = 2; + else if (pdram_timing->mhz <= 600) + tmp = 1; + else + tmp = 0; + tmp = (1 << 12) | (tmp << 9) | (2 << 7) | (1 << 1); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[911], 0x1fff, + tmp); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[919], 0x1fff, + tmp); + + /* PHY_PLL_CTRL_CA */ + /* DENALI_PHY_911 13bits offset_16 */ + /* PHY_LP4_BOOT_PLL_CTRL_CA */ + /* DENALI_PHY_919 13bits offset_16 */ + if (pdram_timing->mhz <= 150) + tmp = 3; + else if (pdram_timing->mhz <= 300) + tmp = 2; + else if (pdram_timing->mhz <= 600) + tmp = 1; + else + tmp = 0; + tmp = (tmp << 9) | (2 << 7) | (1 << 5) | (1 << 1); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[911], + 0x1fff << 16, tmp << 16); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[919], + 0x1fff << 16, tmp << 16); + + /* PHY_TCKSRE_WAIT */ + /* DENALI_PHY_922 4bits offset_24 */ + if (pdram_timing->mhz <= 400) + tmp = 1; + else if (pdram_timing->mhz <= 800) + tmp = 3; + else if (pdram_timing->mhz <= 1000) + tmp = 4; + else + tmp = 5; + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[922], 0xf << 24, + tmp << 24); + /* PHY_CAL_CLK_SELECT_0:RW8:3 */ + div = pdram_timing->mhz / (2 * 20); + for (j = 2, tmp = 1; j <= 128; j <<= 1, tmp++) { + if (div < j) + break; + } + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[947], 0x7 << 8, + tmp << 8); + setbits_32(&rk3399_ddr_publ[i]->denali_phy[927], (1 << 22)); + + if (timing_config->dram_type == DDR3) { + mem_delay_ps = 0; + trpre_min_ps = 1000; + } else if (timing_config->dram_type == LPDDR4) { + mem_delay_ps = 1500; + trpre_min_ps = 900; + } else if (timing_config->dram_type == LPDDR3) { + mem_delay_ps = 2500; + trpre_min_ps = 900; + } else { + ERROR("gen_rk3399_phy_params:dramtype unsupport\n"); + return; + } + total_delay_ps = mem_delay_ps + pad_delay_ps; + delay_frac_ps = + 1000 * total_delay_ps / (1000000 / pdram_timing->mhz); + gate_delay_ps = delay_frac_ps + 1000 - (trpre_min_ps / 2); + gate_delay_frac_ps = + gate_delay_ps - gate_delay_ps / 1000 * 1000; + tmp = gate_delay_frac_ps * 0x200 / 1000; + /* PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY */ + /* DENALI_PHY_2/130/258/386 10bits offset_0 */ + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[2], 0x2ff, tmp); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[130], 0x2ff, tmp); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[258], 0x2ff, tmp); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[386], 0x2ff, tmp); + /* PHY_RDDQS_GATE_SLAVE_DELAY */ + /* DENALI_PHY_77/205/333/461 10bits offset_16 */ + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[77], 0x2ff << 16, + tmp << 16); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[205], 0x2ff << 16, + tmp << 16); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[333], 0x2ff << 16, + tmp << 16); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[461], 0x2ff << 16, + tmp << 16); + + tmp = gate_delay_ps / 1000; + /* PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST */ + /* DENALI_PHY_10/138/266/394 4bit offset_0 */ + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[10], 0xf, tmp); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[138], 0xf, tmp); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[266], 0xf, tmp); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[394], 0xf, tmp); + /* PHY_RDDQS_LATENCY_ADJUST */ + /* DENALI_PHY_78/206/334/462 4bits offset_0 */ + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[78], 0xf, tmp); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[206], 0xf, tmp); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[334], 0xf, tmp); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[462], 0xf, tmp); + /* PHY_GTLVL_LAT_ADJ_START */ + /* DENALI_PHY_80/208/336/464 4bits offset_16 */ + tmp = delay_frac_ps / 1000; + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[80], 0xf << 16, + tmp << 16); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[208], 0xf << 16, + tmp << 16); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[336], 0xf << 16, + tmp << 16); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[464], 0xf << 16, + tmp << 16); + + cas_lat = pdram_timing->cl + PI_ADD_LATENCY; + rddata_en_ie_dly = ie_enable / (1000000 / pdram_timing->mhz); + if ((ie_enable % (1000000 / pdram_timing->mhz)) != 0) + rddata_en_ie_dly++; + rddata_en_ie_dly = rddata_en_ie_dly - 1; + tsel_adder = tsel_enable / (1000000 / pdram_timing->mhz); + if ((tsel_enable % (1000000 / pdram_timing->mhz)) != 0) + tsel_adder++; + if (rddata_en_ie_dly > tsel_adder) + extra_adder = rddata_en_ie_dly - tsel_adder; + else + extra_adder = 0; + delta = cas_lat - rddata_en_ie_dly; + if (PI_REGS_DIMM_SUPPORT && PI_DOUBLEFREEK) + hs_offset = 2; + else + hs_offset = 1; + if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) { + tmp = 0; + } else { + if ((delta == 2) || (delta == 1)) + tmp = rddata_en_ie_dly - 0 - extra_adder; + else + tmp = extra_adder; + } + /* PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY */ + /* DENALI_PHY_9/137/265/393 4bit offset_16 */ + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[9], 0xf << 16, + tmp << 16); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[137], 0xf << 16, + tmp << 16); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[265], 0xf << 16, + tmp << 16); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[393], 0xf << 16, + tmp << 16); + /* PHY_RDDATA_EN_TSEL_DLY */ + /* DENALI_PHY_86/214/342/470 4bit offset_0 */ + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[86], 0xf, tmp); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[214], 0xf, tmp); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[342], 0xf, tmp); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[470], 0xf, tmp); + + if (tsel_adder > rddata_en_ie_dly) + extra_adder = tsel_adder - rddata_en_ie_dly; + else + extra_adder = 0; + if (rddata_en_ie_dly > (cas_lat - 1 - hs_offset)) + tmp = tsel_adder; + else + tmp = rddata_en_ie_dly - 0 + extra_adder; + /* PHY_LP4_BOOT_RDDATA_EN_DLY */ + /* DENALI_PHY_9/137/265/393 4bit offset_8 */ + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[9], 0xf << 8, + tmp << 8); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[137], 0xf << 8, + tmp << 8); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[265], 0xf << 8, + tmp << 8); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[393], 0xf << 8, + tmp << 8); + /* PHY_RDDATA_EN_DLY */ + /* DENALI_PHY_85/213/341/469 4bit offset_24 */ + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[85], 0xf << 24, + tmp << 24); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[213], 0xf << 24, + tmp << 24); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[341], 0xf << 24, + tmp << 24); + clrsetbits_32(&rk3399_ddr_publ[i]->denali_phy[469], 0xf << 24, + tmp << 24); + + if (pdram_timing->mhz <= ENPER_CS_TRAINING_FREQ) { + + /* + * Note:Per-CS Training is not compatible at speeds + * under 533 MHz. If the PHY is running at a speed + * less than 533MHz, all phy_per_cs_training_en_X + * parameters must be cleared to 0. + */ + + /*DENALI_PHY_84/212/340/468 1bit offset_16 */ + clrbits_32(&rk3399_ddr_publ[i]->denali_phy[84], + 0x1 << 16); + clrbits_32(&rk3399_ddr_publ[i]->denali_phy[212], + 0x1 << 16); + clrbits_32(&rk3399_ddr_publ[i]->denali_phy[340], + 0x1 << 16); + clrbits_32(&rk3399_ddr_publ[i]->denali_phy[468], + 0x1 << 16); + } else { + setbits_32(&rk3399_ddr_publ[i]->denali_phy[84], + 0x1 << 16); + setbits_32(&rk3399_ddr_publ[i]->denali_phy[212], + 0x1 << 16); + setbits_32(&rk3399_ddr_publ[i]->denali_phy[340], + 0x1 << 16); + setbits_32(&rk3399_ddr_publ[i]->denali_phy[468], + 0x1 << 16); + } + } +} + +static int to_get_clk_index(unsigned int mhz) +{ + int pll_cnt, i; + + pll_cnt = ARRAY_SIZE(dpll_rates_table); + + /* Assumming rate_table is in descending order */ + for (i = 0; i < pll_cnt; i++) { + if (mhz >= dpll_rates_table[i].mhz) + break; + } + + /* if mhz lower than lowest frequency in table, use lowest frequency */ + if (i == pll_cnt) + i = pll_cnt - 1; + + return i; +} + +uint32_t rkclk_prepare_pll_timing(unsigned int mhz) +{ + unsigned int refdiv, postdiv1, fbdiv, postdiv2; + int index; + + index = to_get_clk_index(mhz); + refdiv = dpll_rates_table[index].refdiv; + fbdiv = dpll_rates_table[index].fbdiv; + postdiv1 = dpll_rates_table[index].postdiv1; + postdiv2 = dpll_rates_table[index].postdiv2; + write_32(DCF_PARAM_ADDR + PARAM_DPLL_CON0, FBDIV(fbdiv)); + write_32(DCF_PARAM_ADDR + PARAM_DPLL_CON1, POSTDIV2(postdiv2) | + POSTDIV1(postdiv1) | REFDIV(refdiv)); + return (24 * fbdiv) / refdiv / postdiv1 / postdiv2; +} + +uint32_t ddr_get_rate(void) +{ + uint32_t refdiv, postdiv1, fbdiv, postdiv2; + + refdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) & 0x3f; + fbdiv = mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 0)) & 0xfff; + postdiv1 = + (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 8) & 0x7; + postdiv2 = + (mmio_read_32(CRU_BASE + CRU_PLL_CON(DPLL_ID, 1)) >> 12) & 0x7; + + return (24 / refdiv * fbdiv / postdiv1 / postdiv2) * 1000 * 1000; +} + +/* + * return: bit12: channel 1, external self-refresh + * bit11: channel 1, stdby_mode + * bit10: channel 1, self-refresh with controller and memory clock gate + * bit9: channel 1, self-refresh + * bit8: channel 1, power-down + * + * bit4: channel 1, external self-refresh + * bit3: channel 0, stdby_mode + * bit2: channel 0, self-refresh with controller and memory clock gate + * bit1: channel 0, self-refresh + * bit0: channel 0, power-down + */ +uint32_t exit_low_power(void) +{ + struct rk3399_ddr_pctl_regs *ddr_pctl_regs; + uint32_t low_power = 0; + uint32_t channel_mask; + uint32_t channel; + uint32_t tmp; + + channel_mask = (read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 0x3; + for (channel = 0; channel < 2; channel++) { + ddr_pctl_regs = rk3399_ddr_pctl[channel]; + if (!(channel_mask & (1 << channel))) + continue; + + /* exit stdby mode */ + write_32(&rk3399_ddr_cic->cic_ctrl1, + (1 << (channel + 16)) | (0 << channel)); + /* exit external self-refresh */ + tmp = channel ? 12 : 8; + low_power |= ((read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & 0x1) + << (4 + 8 * channel); + clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp); + while (!(read_32(PMU_BASE + PMU_DDR_SREF_ST) & + (1 << channel))) + ; + /* exit auto low-power */ + clrbits_32(&ddr_pctl_regs->denali_ctl[101], 0x7); + /* lp_cmd to exit */ + if (((read_32(&ddr_pctl_regs->denali_ctl[100]) >> 24) & + 0x7f) != 0x40) { + while (read_32(&ddr_pctl_regs->denali_ctl[200]) & 0x1) + ; + clrsetbits_32(&ddr_pctl_regs->denali_ctl[93], + 0xff << 24, 0x69 << 24); + while (((read_32(&ddr_pctl_regs->denali_ctl[100]) >> + 24) & 0x7f) != 0x40) + ; + } + } + return low_power; +} + +void resume_low_power(uint32_t low_power) +{ + struct rk3399_ddr_pctl_regs *ddr_pctl_regs; + uint32_t channel_mask; + uint32_t channel; + uint32_t tmp; + uint32_t val; + + channel_mask = (read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & 0x3; + for (channel = 0; channel < 2; channel++) { + ddr_pctl_regs = rk3399_ddr_pctl[channel]; + if (!(channel_mask & (1 << channel))) + continue; + + /* resume external self-refresh */ + tmp = channel ? 12 : 8; + val = (low_power >> (4 + 8 * channel)) & 0x1; + setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp); + /* resume auto low-power */ + val = (low_power >> (8 * channel)) & 0x7; + setbits_32(&ddr_pctl_regs->denali_ctl[101], val); + /* resume stdby mode */ + val = (low_power >> (3 + 8 * channel)) & 0x1; + write_32(&rk3399_ddr_cic->cic_ctrl1, + (1 << (channel + 16)) | (val << channel)); + } +} + +static void wait_dcf_done(void) +{ + while ((read_32(DCF_BASE + DCF_DCF_ISR) & (DCF_DONE)) == 0) + continue; +} + +void clr_dcf_irq(void) +{ + /* clear dcf irq status */ + mmio_write_32(DCF_BASE + DCF_DCF_ISR, DCF_TIMEOUT | DCF_ERR | DCF_DONE); +} + +static void enable_dcf(uint32_t dcf_addr) +{ + /* config DCF start addr */ + write_32(DCF_BASE + DCF_DCF_ADDR, dcf_addr); + /* wait dcf done */ + while (read_32(DCF_BASE + DCF_DCF_CTRL) & 1) + continue; + /* clear dcf irq status */ + write_32(DCF_BASE + DCF_DCF_ISR, DCF_TIMEOUT | DCF_ERR | DCF_DONE); + /* DCF start */ + setbits_32(DCF_BASE + DCF_DCF_CTRL, DCF_START); +} + +void dcf_code_init(void) +{ + memcpy((void *)DCF_START_ADDR, (void *)dcf_code, sizeof(dcf_code)); + /* set dcf master secure */ + write_32(SGRF_BASE + 0xe01c, ((0x3 << 0) << 16) | (0 << 0)); + write_32(DCF_BASE + DCF_DCF_TOSET, 0x80000000); +} + +static void dcf_start(uint32_t freq, uint32_t index) +{ + write_32(CRU_BASE + CRU_SOFTRST_CON(10), (0x1 << (1 + 16)) | (1 << 1)); + write_32(CRU_BASE + CRU_SOFTRST_CON(11), (0x1 << (0 + 16)) | (1 << 0)); + write_32(DCF_PARAM_ADDR + PARAM_FREQ_SELECT, index << 4); + + write_32(DCF_PARAM_ADDR + PARAM_DRAM_FREQ, freq); + + rkclk_prepare_pll_timing(freq); + udelay(10); + write_32(CRU_BASE + CRU_SOFTRST_CON(10), (0x1 << (1 + 16)) | (0 << 1)); + write_32(CRU_BASE + CRU_SOFTRST_CON(11), (0x1 << (0 + 16)) | (0 << 0)); + udelay(10); + enable_dcf(DCF_START_ADDR); +} + +static void dram_low_power_config(struct drv_odt_lp_config *lp_config) +{ + uint32_t tmp, tmp1, i; + uint32_t ch_cnt = rk3399_dram_status.timing_config.ch_cnt; + uint32_t dram_type = rk3399_dram_status.timing_config.dram_type; + uint32_t *low_power = &rk3399_dram_status.low_power_stat; + + if (dram_type == LPDDR4) + tmp = (lp_config->srpd_lite_idle << 16) | + lp_config->pd_idle; + else + tmp = lp_config->pd_idle; + + if (dram_type == DDR3) + tmp1 = (2 << 16) | (0x7 << 8) | 7; + else + tmp1 = (3 << 16) | (0x7 << 8) | 7; + + *low_power = 0; + + for (i = 0; i < ch_cnt; i++) { + write_32(&rk3399_ddr_pctl[i]->denali_ctl[102], tmp); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[103], 0xffff, + (lp_config->sr_mc_gate_idle << 8) | + lp_config->sr_idle); + clrsetbits_32(&rk3399_ddr_pctl[i]->denali_ctl[101], + 0x70f0f, tmp1); + *low_power |= (7 << (8 * i)); + } + + /* standby idle */ + write_32(&rk3399_ddr_cic->cic_idle_th, lp_config->standby_idle); + write_32(&rk3399_ddr_cic->cic_cg_wait_th, 0x640008); + + if (ch_cnt == 2) { + write_32(GRF_BASE + GRF_DDRC1_CON1, + (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | + ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); + if (lp_config->standby_idle) { + tmp = 0x002a002a; + *low_power |= (1 << 11); + } else { + tmp = 0; + } + write_32(&rk3399_ddr_cic->cic_ctrl1, tmp); + } + + write_32(GRF_BASE + GRF_DDRC0_CON1, + (((0x1<<4) | (0x1<<5) | (0x1<<6) | (0x1<<7)) << 16) | + ((0x1<<4) | (0x0<<5) | (0x1<<6) | (0x1<<7))); + if (lp_config->standby_idle) { + tmp = 0x00150015; + *low_power |= (1 << 3); + } else { + tmp = 0; + } + write_32(&rk3399_ddr_cic->cic_ctrl1, tmp); +} + + +static void dram_related_init(struct ddr_dts_config_timing *dts_timing) +{ + uint32_t trefi0, trefi1; + uint32_t i; + struct rk3399_sdram_config sdram_config; + + dcf_code_init(); + + /* get sdram config for os reg */ + sdram_config_init(&sdram_config); + drv_odt_lp_cfg_init(sdram_config.dramtype, dts_timing, + &rk3399_dram_status.drv_odt_lp_cfg); + sdram_timing_cfg_init(&rk3399_dram_status.timing_config, + &sdram_config, + &rk3399_dram_status.drv_odt_lp_cfg); + + trefi0 = ((read_32(&rk3399_ddr_pctl[0]->denali_ctl[48]) >> + 16) & 0xffff) + 8; + trefi1 = ((read_32(&rk3399_ddr_pctl[0]->denali_ctl[49]) >> + 16) & 0xffff) + 8; + + rk3399_dram_status.index_freq[0] = trefi0 * 10 / 39; + rk3399_dram_status.index_freq[1] = trefi1 * 10 / 39; + rk3399_dram_status.current_index = + (read_32(&rk3399_ddr_pctl[0]->denali_ctl[111]) + >> 16) & 0x3; + if (rk3399_dram_status.timing_config.dram_type == DDR3) { + rk3399_dram_status.index_freq[0] /= 2; + rk3399_dram_status.index_freq[1] /= 2; + } + rk3399_dram_status.index_freq[(rk3399_dram_status.current_index + 1) + & 0x1] = 0; + + /* disable all training by ctl and pi */ + for (i = 0; i < rk3399_dram_status.timing_config.ch_cnt; i++) { + clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[70], (1 << 24) | + (1 << 16) | (1 << 8) | 1); + clrbits_32(&rk3399_ddr_pctl[i]->denali_ctl[71], 1); + + clrbits_32(&rk3399_ddr_pi[i]->denali_pi[60], 0x3 << 8); + clrbits_32(&rk3399_ddr_pi[i]->denali_pi[80], (0x3 << 24) | + (0x3 << 16)); + clrbits_32(&rk3399_ddr_pi[i]->denali_pi[100], 0x3 << 8); + clrbits_32(&rk3399_ddr_pi[i]->denali_pi[124], 0x3 << 16); + } + + /* init drv odt */ + if (rk3399_dram_status.index_freq[rk3399_dram_status.current_index] < + rk3399_dram_status.drv_odt_lp_cfg.odt_dis_freq) + rk3399_dram_status.timing_config.odt = 0; + else + rk3399_dram_status.timing_config.odt = 1; + gen_rk3399_set_ds_odt(&rk3399_dram_status.timing_config, + &rk3399_dram_status.drv_odt_lp_cfg); + dram_low_power_config(&rk3399_dram_status.drv_odt_lp_cfg); +} + +static uint32_t prepare_ddr_timing(uint32_t mhz) +{ + uint32_t index; + struct dram_timing_t dram_timing; + + rk3399_dram_status.timing_config.freq = mhz; + + if (mhz < rk3399_dram_status.drv_odt_lp_cfg.ddr3_dll_dis_freq) + rk3399_dram_status.timing_config.dllbp = 1; + else + rk3399_dram_status.timing_config.dllbp = 0; + if (mhz < rk3399_dram_status.drv_odt_lp_cfg.odt_dis_freq) { + rk3399_dram_status.timing_config.odt = 0; + } else { + rk3399_dram_status.timing_config.odt = 1; + gen_rk3399_set_odt(1); + } + + index = (rk3399_dram_status.current_index + 1) & 0x1; + if (rk3399_dram_status.index_freq[index] == mhz) + goto out; + + /* + * checking if having available gate traiing timing for + * target freq. + */ + dram_get_parameter(&rk3399_dram_status.timing_config, &dram_timing); + gen_rk3399_ctl_params(&rk3399_dram_status.timing_config, + &dram_timing, index); + gen_rk3399_pi_params(&rk3399_dram_status.timing_config, + &dram_timing, index); + gen_rk3399_phy_params(&rk3399_dram_status.timing_config, + &rk3399_dram_status.drv_odt_lp_cfg, + &dram_timing, index); + rk3399_dram_status.index_freq[index] = mhz; + + +out: + return index; +} + +void print_dram_status_info(void) +{ + uint32_t *p; + uint32_t i; + + p = (uint32_t *) &rk3399_dram_status.timing_config; + INFO("rk3399_dram_status.timing_config:\n"); + for (i = 0; i < sizeof(struct timing_related_config) / 4; i++) + tf_printf("%u\n", p[i]); + p = (uint32_t *) &rk3399_dram_status.drv_odt_lp_cfg; + INFO("rk3399_dram_status.drv_odt_lp_cfg:\n"); + for (i = 0; i < sizeof(struct drv_odt_lp_config) / 4; i++) + tf_printf("%u\n", p[i]); +} + +uint32_t ddr_set_rate(uint32_t hz) +{ + uint32_t low_power, index; + uint32_t mhz = hz / (1000 * 1000); + + if (mhz == + rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) + goto out; + + index = to_get_clk_index(mhz); + mhz = dpll_rates_table[index].mhz; + + low_power = exit_low_power(); + index = prepare_ddr_timing(mhz); + if (index > 1) + goto out; + + dcf_start(mhz, index); + wait_dcf_done(); + if (rk3399_dram_status.timing_config.odt == 0) + gen_rk3399_set_odt(0); + + rk3399_dram_status.current_index = index; + + if (mhz < dts_parameter.auto_pd_dis_freq) + low_power |= rk3399_dram_status.low_power_stat; + + resume_low_power(low_power); +out: + return mhz; +} + +uint32_t ddr_round_rate(uint32_t hz) +{ + int index; + uint32_t mhz = hz / (1000 * 1000); + + index = to_get_clk_index(mhz); + + return dpll_rates_table[index].mhz * 1000 * 1000; +} + +uint32_t dts_timing_receive(uint32_t timing, uint32_t index) +{ + uint32_t *p = (uint32_t *) &dts_parameter; + static uint32_t receive_nums; + + if (index < (sizeof(dts_parameter) / sizeof(uint32_t) - 1)) { + p[index] = (uint32_t)timing; + receive_nums++; + } else { + dts_parameter.available = 0; + return -1; + } + + /* receive all parameter */ + if (receive_nums == (sizeof(dts_parameter) / sizeof(uint32_t) - 1)) { + dts_parameter.available = 1; + receive_nums = 0; + } + + return index; +} + +void ddr_init(void) +{ + dram_related_init(&dts_parameter); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram.h new file mode 100644 index 0000000..4f99070 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram.h @@ -0,0 +1,329 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_SDRAM_H__ +#define __SOC_ROCKCHIP_RK3399_SDRAM_H__ + +struct rk3399_ddr_cic_regs { + uint32_t cic_ctrl0; + uint32_t cic_ctrl1; + uint32_t cic_idle_th; + uint32_t cic_cg_wait_th; + uint32_t cic_status0; + uint32_t cic_status1; + uint32_t cic_ctrl2; + uint32_t cic_ctrl3; + uint32_t cic_ctrl4; +}; + +/* DENALI_CTL_00 */ +#define START (1) + +/* DENALI_CTL_68 */ +#define PWRUP_SREFRESH_EXIT (1 << 16) + +/* DENALI_CTL_274 */ +#define MEM_RST_VALID (1) + +struct rk3399_ddr_pctl_regs { + uint32_t denali_ctl[332]; +}; + +struct rk3399_ddr_publ_regs { + uint32_t denali_phy[959]; +}; + +#define PHY_DRV_ODT_Hi_Z (0x0) +#define PHY_DRV_ODT_240 (0x1) +#define PHY_DRV_ODT_120 (0x8) +#define PHY_DRV_ODT_80 (0x9) +#define PHY_DRV_ODT_60 (0xc) +#define PHY_DRV_ODT_48 (0xd) +#define PHY_DRV_ODT_40 (0xe) +#define PHY_DRV_ODT_34_3 (0xf) + +struct rk3399_ddr_pi_regs { + uint32_t denali_pi[200]; +}; +union noc_ddrtiminga0 { + uint32_t d32; + struct { + unsigned acttoact : 6; + unsigned reserved0 : 2; + unsigned rdtomiss : 6; + unsigned reserved1 : 2; + unsigned wrtomiss : 6; + unsigned reserved2 : 2; + unsigned readlatency : 8; + } b; +}; + +union noc_ddrtimingb0 { + uint32_t d32; + struct { + unsigned rdtowr : 5; + unsigned reserved0 : 3; + unsigned wrtord : 5; + unsigned reserved1 : 3; + unsigned rrd : 4; + unsigned reserved2 : 4; + unsigned faw : 6; + unsigned reserved3 : 2; + } b; +}; + +union noc_ddrtimingc0 { + uint32_t d32; + struct { + unsigned burstpenalty : 4; + unsigned reserved0 : 4; + unsigned wrtomwr : 6; + unsigned reserved1 : 18; + } b; +}; + +union noc_devtodev0 { + uint32_t d32; + struct { + unsigned busrdtord : 3; + unsigned reserved0 : 1; + unsigned busrdtowr : 3; + unsigned reserved1 : 1; + unsigned buswrtord : 3; + unsigned reserved2 : 1; + unsigned buswrtowr : 3; + unsigned reserved3 : 17; + } b; +}; + +union noc_ddrmode { + uint32_t d32; + struct { + unsigned autoprecharge : 1; + unsigned bypassfiltering : 1; + unsigned fawbank : 1; + unsigned burstsize : 2; + unsigned mwrsize : 2; + unsigned reserved2 : 1; + unsigned forceorder : 8; + unsigned forceorderstate : 8; + unsigned reserved3 : 8; + } b; +}; + +struct rk3399_msch_regs { + uint32_t coreid; + uint32_t revisionid; + uint32_t ddrconf; + uint32_t ddrsize; + union noc_ddrtiminga0 ddrtiminga0; + union noc_ddrtimingb0 ddrtimingb0; + union noc_ddrtimingc0 ddrtimingc0; + union noc_devtodev0 devtodev0; + uint32_t reserved0[(0x110-0x20)/4]; + union noc_ddrmode ddrmode; + uint32_t reserved1[(0x1000-0x114)/4]; + uint32_t agingx0; +}; + +struct rk3399_msch_timings { + union noc_ddrtiminga0 ddrtiminga0; + union noc_ddrtimingb0 ddrtimingb0; + union noc_ddrtimingc0 ddrtimingc0; + union noc_devtodev0 devtodev0; + union noc_ddrmode ddrmode; + uint32_t agingx0; +}; +#if 1 +struct rk3399_sdram_channel { + unsigned char rank; + /* col = 0, means this channel is invalid */ + unsigned char col; + /* 3:8bank, 2:4bank */ + unsigned char bk; + /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned char bw; + /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ + unsigned char dbw; + /* row_3_4 = 1: 6Gb or 12Gb die + * row_3_4 = 0: normal die, power of 2 + */ + unsigned char row_3_4; + unsigned char cs0_row; + unsigned char cs1_row; + uint32_t ddrconfig; + struct rk3399_msch_timings noc_timings; +}; + +struct rk3399_sdram_params { + struct rk3399_sdram_channel ch[2]; + uint32_t ddr_freq; + unsigned char dramtype; + unsigned char num_channels; + unsigned char stride; + unsigned char odt; + struct rk3399_ddr_pctl_regs pctl_regs; + struct rk3399_ddr_pi_regs pi_regs; + struct rk3399_ddr_publ_regs phy_regs; +}; +#endif +struct rk3399_sdram_channel_config { + uint32_t bus_width; + uint32_t cs_cnt; + uint32_t cs0_row; + uint32_t cs1_row; + uint32_t bank; + uint32_t col; + uint32_t each_die_bus_width; + uint32_t each_die_6gb_or_12gb; +}; + +struct rk3399_sdram_config { + struct rk3399_sdram_channel_config ch[2]; + uint32_t dramtype; + uint32_t channal_num; +}; + +struct rk3399_sdram_default_config { + unsigned char bl; + /* 1:auto precharge, 0:never auto precharge */ + unsigned char ap; + /* dram driver strength */ + unsigned char dramds; + /* dram ODT, if odt=0, this parameter invalid */ + unsigned char dramodt; + /* ca ODT, if odt=0, this parameter invalid + * only used by LPDDR4 + */ + unsigned char caodt; + unsigned char burst_ref_cnt; + /* zqcs period, unit(s) */ + unsigned char zqcsi; +}; + +struct ddr_dts_config_timing { + unsigned int ddr3_speed_bin; + unsigned int pd_idle; + unsigned int sr_idle; + unsigned int sr_mc_gate_idle; + unsigned int srpd_lite_idle; + unsigned int standby_idle; + unsigned int auto_pd_dis_freq; + unsigned int ddr3_dll_dis_freq; + unsigned int phy_dll_dis_freq; + unsigned int ddr3_odt_dis_freq; + unsigned int ddr3_drv; + unsigned int ddr3_odt; + unsigned int phy_ddr3_ca_drv; + unsigned int phy_ddr3_dq_drv; + unsigned int phy_ddr3_odt; + unsigned int lpddr3_odt_dis_freq; + unsigned int lpddr3_drv; + unsigned int lpddr3_odt; + unsigned int phy_lpddr3_ca_drv; + unsigned int phy_lpddr3_dq_drv; + unsigned int phy_lpddr3_odt; + unsigned int lpddr4_odt_dis_freq; + unsigned int lpddr4_drv; + unsigned int lpddr4_dq_odt; + unsigned int lpddr4_ca_odt; + unsigned int phy_lpddr4_ca_drv; + unsigned int phy_lpddr4_ck_cs_drv; + unsigned int phy_lpddr4_dq_drv; + unsigned int phy_lpddr4_odt; + uint32_t available; +}; + +struct drv_odt_lp_config { + uint32_t ddr3_speed_bin; + uint32_t pd_idle; + uint32_t sr_idle; + uint32_t sr_mc_gate_idle; + uint32_t srpd_lite_idle; + uint32_t standby_idle; + + uint32_t ddr3_dll_dis_freq;/* for ddr3 only */ + uint32_t phy_dll_dis_freq; + uint32_t odt_dis_freq; + + uint32_t dram_side_drv; + uint32_t dram_side_dq_odt; + uint32_t dram_side_ca_odt; + + uint32_t phy_side_ca_drv; + uint32_t phy_side_ck_cs_drv; + uint32_t phy_side_dq_drv; + uint32_t phy_side_odt; +}; + +#define KHz (1000) +#define MHz (1000*KHz) +#define GHz (1000*MHz) + +#define PI_CA_TRAINING (1 << 0) +#define PI_WRITE_LEVELING (1 << 1) +#define PI_READ_GATE_TRAINING (1 << 2) +#define PI_READ_LEVELING (1 << 3) +#define PI_WDQ_LEVELING (1 << 4) +#define PI_FULL_TARINING (0xff) + +#define READ_CH_CNT(val) (1+((val>>12)&0x1)) +#define READ_CH_INFO(val) ((val>>28)&0x3) +/* row_3_4:0=normal, 1=6Gb or 12Gb */ +#define READ_CH_ROW_INFO(val, ch) ((val>>(30+(ch)))&0x1) + +#define READ_DRAMTYPE_INFO(val) ((val>>13)&0x7) +#define READ_CS_INFO(val, ch) ((((val)>>(11+(ch)*16))&0x1)+1) +#define READ_BW_INFO(val, ch) (2>>(((val)>>(2+(ch)*16))&0x3)) +#define READ_COL_INFO(val, ch) (9+(((val)>>(9+(ch)*16))&0x3)) +#define READ_BK_INFO(val, ch) (3-(((val)>>(8+(ch)*16))&0x1)) +#define READ_CS0_ROW_INFO(val, ch) (13+(((val)>>(6+(ch)*16))&0x3)) +#define READ_CS1_ROW_INFO(val, ch) (13+(((val)>>(4+(ch)*16))&0x3)) +#define READ_DIE_BW_INFO(val, ch) (2>>((val>>((ch)*16))&0x3)) + +#define __sramdata __attribute__((section(".sram.data"))) +#define __sramconst __attribute__((section(".sram.rodata"))) +#define __sramlocalfunc __attribute__((section(".sram.text"))) +#define __sramfunc __attribute__((section(".sram.text"))) \ + __attribute__((noinline)) + + +#define DDR_SAVE_SP(save_sp) (save_sp = ddr_save_sp(((uint32_t)\ + (SRAM_CODE_BASE + 0x2000) & (~7)))) + +#define DDR_RESTORE_SP(save_sp) ddr_save_sp(save_sp) + +void ddr_init(void); +uint32_t ddr_set_rate(uint32_t hz); +uint32_t ddr_round_rate(uint32_t hz); +uint32_t ddr_get_rate(void); +void clr_dcf_irq(void); +uint32_t dts_timing_receive(uint32_t timing, uint32_t index); +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c new file mode 100644 index 0000000..b015db7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.c @@ -0,0 +1,1323 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "dram_spec_timing.h" + +static const uint8_t ddr3_cl_cwl[][7] = { + /* + * speed 0~330 331 ~ 400 401 ~ 533 534~666 667~800 801~933 934~1066 + * tCK>3 2.5~3 1.875~2.5 1.5~1.875 1.25~1.5 1.07~1.25 0.938~1.07 + * cl<<4, cwl cl<<4, cwl cl<<4, cwl + */ + /* DDR3_800D (5-5-5) */ + {((5 << 4) | 5), ((5 << 4) | 5), 0, 0, 0, 0, 0}, + /* DDR3_800E (6-6-6) */ + {((5 << 4) | 5), ((6 << 4) | 5), 0, 0, 0, 0, 0}, + /* DDR3_1066E (6-6-6) */ + {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), 0, 0, 0, 0}, + /* DDR3_1066F (7-7-7) */ + {((5 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), 0, 0, 0, 0}, + /* DDR3_1066G (8-8-8) */ + {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), 0, 0, 0, 0}, + /* DDR3_1333F (7-7-7) */ + {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), + 0, 0, 0}, + /* DDR3_1333G (8-8-8) */ + {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7), + 0, 0, 0}, + /* DDR3_1333H (9-9-9) */ + {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((9 << 4) | 7), + 0, 0, 0}, + /* DDR3_1333J (10-10-10) */ + {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), + 0, 0, 0}, + /* DDR3_1600G (8-8-8) */ + {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), + ((8 << 4) | 8), 0, 0}, + /* DDR3_1600H (9-9-9) */ + {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), + ((9 << 4) | 8), 0, 0}, + /* DDR3_1600J (10-10-10) */ + {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), + ((10 << 4) | 8), 0, 0}, + /* DDR3_1600K (11-11-11) */ + {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), + ((11 << 4) | 8), 0, 0}, + /* DDR3_1866J (10-10-10) */ + {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), + ((9 << 4) | 8), ((11 << 4) | 9), 0}, + /* DDR3_1866K (11-11-11) */ + {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7), + ((10 << 4) | 8), ((11 << 4) | 9), 0}, + /* DDR3_1866L (12-12-12) */ + {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), + ((11 << 4) | 8), ((12 << 4) | 9), 0}, + /* DDR3_1866M (13-13-13) */ + {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), + ((11 << 4) | 8), ((13 << 4) | 9), 0}, + /* DDR3_2133K (11-11-11) */ + {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), + ((9 << 4) | 8), ((10 << 4) | 9), ((11 << 4) | 10)}, + /* DDR3_2133L (12-12-12) */ + {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), + ((9 << 4) | 8), ((11 << 4) | 9), ((12 << 4) | 10)}, + /* DDR3_2133M (13-13-13) */ + {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), + ((10 << 4) | 8), ((12 << 4) | 9), ((13 << 4) | 10)}, + /* DDR3_2133N (14-14-14) */ + {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), + ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)}, + /* DDR3_DEFAULT */ + {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), + ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)} +}; + +static const uint16_t ddr3_trc_tfaw[] = { + /* tRC tFAW */ + ((50 << 8) | 50), /* DDR3_800D (5-5-5) */ + ((53 << 8) | 50), /* DDR3_800E (6-6-6) */ + + ((49 << 8) | 50), /* DDR3_1066E (6-6-6) */ + ((51 << 8) | 50), /* DDR3_1066F (7-7-7) */ + ((53 << 8) | 50), /* DDR3_1066G (8-8-8) */ + + ((47 << 8) | 45), /* DDR3_1333F (7-7-7) */ + ((48 << 8) | 45), /* DDR3_1333G (8-8-8) */ + ((50 << 8) | 45), /* DDR3_1333H (9-9-9) */ + ((51 << 8) | 45), /* DDR3_1333J (10-10-10) */ + + ((45 << 8) | 40), /* DDR3_1600G (8-8-8) */ + ((47 << 8) | 40), /* DDR3_1600H (9-9-9)*/ + ((48 << 8) | 40), /* DDR3_1600J (10-10-10) */ + ((49 << 8) | 40), /* DDR3_1600K (11-11-11) */ + + ((45 << 8) | 35), /* DDR3_1866J (10-10-10) */ + ((46 << 8) | 35), /* DDR3_1866K (11-11-11) */ + ((47 << 8) | 35), /* DDR3_1866L (12-12-12) */ + ((48 << 8) | 35), /* DDR3_1866M (13-13-13) */ + + ((44 << 8) | 35), /* DDR3_2133K (11-11-11) */ + ((45 << 8) | 35), /* DDR3_2133L (12-12-12) */ + ((46 << 8) | 35), /* DDR3_2133M (13-13-13) */ + ((47 << 8) | 35), /* DDR3_2133N (14-14-14) */ + + ((53 << 8) | 50) /* DDR3_DEFAULT */ +}; + +static uint32_t get_max_speed_rate(struct timing_related_config *timing_config) +{ + if (timing_config->ch_cnt > 1) + return max(timing_config->dram_info[0].speed_rate, + timing_config->dram_info[1].speed_rate); + else + return timing_config->dram_info[0].speed_rate; +} + +static uint32_t +get_max_die_capability(struct timing_related_config *timing_config) +{ + uint32_t die_cap = 0; + uint32_t cs, ch; + + for (ch = 0; ch < timing_config->ch_cnt; ch++) { + for (cs = 0; cs < timing_config->dram_info[ch].cs_cnt; cs++) { + die_cap = max(die_cap, + timing_config-> + dram_info[ch].per_die_capability[cs]); + } + } + return die_cap; +} + +/* tRSTL, 100ns */ +#define DDR3_TRSTL (100) +/* trsth, 500us */ +#define DDR3_TRSTH (500000) +/* trefi, 7.8us */ +#define DDR3_TREFI_7_8_US (7800) +/* tWR, 15ns */ +#define DDR3_TWR (15) +/* tRTP, max(4 tCK,7.5ns) */ +#define DDR3_TRTP (7) +/* tRRD = max(4nCK, 10ns) */ +#define DDR3_TRRD (10) +/* tCK */ +#define DDR3_TCCD (4) +/*tWTR, max(4 tCK,7.5ns)*/ +#define DDR3_TWTR (7) +/* tCK */ +#define DDR3_TRTW (0) +/* tRAS, 37.5ns(400MHz) 37.5ns(533MHz) */ +#define DDR3_TRAS (37) +/* ns */ +#define DDR3_TRFC_512MBIT (90) +/* ns */ +#define DDR3_TRFC_1GBIT (110) +/* ns */ +#define DDR3_TRFC_2GBIT (160) +/* ns */ +#define DDR3_TRFC_4GBIT (300) +/* ns */ +#define DDR3_TRFC_8GBIT (350) + +/*pd and sr*/ +#define DDR3_TXP (7) /* tXP, max(3 tCK, 7.5ns)( < 933MHz) */ +#define DDR3_TXPDLL (24) /* tXPDLL, max(10 tCK, 24ns) */ +#define DDR3_TDLLK (512) /* tXSR, tDLLK=512 tCK */ +#define DDR3_TCKE_400MHZ (7) /* tCKE, max(3 tCK,7.5ns)(400MHz) */ +#define DDR3_TCKE_533MHZ (6) /* tCKE, max(3 tCK,5.625ns)(533MHz) */ +#define DDR3_TCKSRE (10) /* tCKSRX, max(5 tCK, 10ns) */ + +/*mode register timing*/ +#define DDR3_TMOD (15) /* tMOD, max(12 tCK,15ns) */ +#define DDR3_TMRD (4) /* tMRD, 4 tCK */ + +/* ZQ */ +#define DDR3_TZQINIT (640) /* tZQinit, max(512 tCK, 640ns) */ +#define DDR3_TZQCS (80) /* tZQCS, max(64 tCK, 80ns) */ +#define DDR3_TZQOPER (320) /* tZQoper, max(256 tCK, 320ns) */ + +/* Write leveling */ +#define DDR3_TWLMRD (40) /* tCK */ +#define DDR3_TWLO (9) /* max 7.5ns */ +#define DDR3_TWLDQSEN (25) /* tCK */ + +/* + * Description: depend on input parameter "timing_config", + * and calculate all ddr3 + * spec timing to "pdram_timing" + * parameters: + * input: timing_config + * output: pdram_timing + */ +static void ddr3_get_parameter(struct timing_related_config *timing_config, + struct dram_timing_t *pdram_timing) +{ + uint32_t nmhz = timing_config->freq; + uint32_t ddr_speed_bin = get_max_speed_rate(timing_config); + uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); + uint32_t tmp; + + memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); + pdram_timing->mhz = nmhz; + pdram_timing->al = 0; + pdram_timing->bl = timing_config->bl; + if (nmhz <= 330) + tmp = 0; + else if (nmhz <= 400) + tmp = 1; + else if (nmhz <= 533) + tmp = 2; + else if (nmhz <= 666) + tmp = 3; + else if (nmhz <= 800) + tmp = 4; + else if (nmhz <= 933) + tmp = 5; + else + tmp = 6; + + /* when dll bypss cl = cwl = 6 */ + if (nmhz < 300) { + pdram_timing->cl = 6; + pdram_timing->cwl = 6; + } else { + pdram_timing->cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4) & 0xf; + pdram_timing->cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf; + } + + switch (timing_config->dramds) { + case 40: + tmp = DDR3_DS_40; + break; + case 34: + default: + tmp = DDR3_DS_34; + break; + } + + switch (timing_config->dramodt) { + case 60: + pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60; + break; + case 40: + pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40; + break; + case 120: + pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120; + break; + case 0: + default: + pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; + break; + } + + pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl); + pdram_timing->mr[3] = 0; + + pdram_timing->trstl = ((DDR3_TRSTL * nmhz + 999) / 1000); + pdram_timing->trsth = ((DDR3_TRSTH * nmhz + 999) / 1000); + /* tREFI, average periodic refresh interval, 7.8us */ + pdram_timing->trefi = ((DDR3_TREFI_7_8_US * nmhz + 999) / 1000); + /* base timing */ + pdram_timing->trcd = pdram_timing->cl; + pdram_timing->trp = pdram_timing->cl; + pdram_timing->trppb = pdram_timing->cl; + tmp = ((DDR3_TWR * nmhz + 999) / 1000); + pdram_timing->twr = tmp; + pdram_timing->tdal = tmp + pdram_timing->trp; + if (tmp < 9) { + tmp = tmp - 4; + } else { + tmp += (tmp & 0x1) ? 1 : 0; + tmp = tmp >> 1; + } + if (pdram_timing->bl == 4) + pdram_timing->mr[0] = DDR3_BC4 + | DDR3_CL(pdram_timing->cl) + | DDR3_WR(tmp); + else + pdram_timing->mr[0] = DDR3_BL8 + | DDR3_CL(pdram_timing->cl) + | DDR3_WR(tmp); + tmp = ((DDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); + pdram_timing->trtp = max(4, tmp); + pdram_timing->trc = + (((ddr3_trc_tfaw[ddr_speed_bin] >> 8) * nmhz + 999) / 1000); + tmp = ((DDR3_TRRD * nmhz + 999) / 1000); + pdram_timing->trrd = max(4, tmp); + pdram_timing->tccd = DDR3_TCCD; + tmp = ((DDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000); + pdram_timing->twtr = max(4, tmp); + pdram_timing->trtw = DDR3_TRTW; + pdram_timing->tras_max = 9 * pdram_timing->trefi; + pdram_timing->tras_min = ((DDR3_TRAS * nmhz + (nmhz >> 1) + 999) + / 1000); + pdram_timing->tfaw = + (((ddr3_trc_tfaw[ddr_speed_bin] & 0x0ff) * nmhz + 999) + / 1000); + /* tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb) */ + if (ddr_capability_per_die <= 0x4000000) + tmp = DDR3_TRFC_512MBIT; + else if (ddr_capability_per_die <= 0x8000000) + tmp = DDR3_TRFC_1GBIT; + else if (ddr_capability_per_die <= 0x10000000) + tmp = DDR3_TRFC_2GBIT; + else if (ddr_capability_per_die <= 0x20000000) + tmp = DDR3_TRFC_4GBIT; + else + tmp = DDR3_TRFC_8GBIT; + pdram_timing->trfc = (tmp * nmhz + 999) / 1000; + pdram_timing->txsnr = max(5, (((tmp + 10) * nmhz + 999) / 1000)); + pdram_timing->tdqsck_max = 0; + /*pd and sr*/ + pdram_timing->txsr = DDR3_TDLLK; + tmp = ((DDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000); + pdram_timing->txp = max(3, tmp); + tmp = ((DDR3_TXPDLL * nmhz + 999) / 1000); + pdram_timing->txpdll = max(10, tmp); + pdram_timing->tdllk = DDR3_TDLLK; + if (nmhz >= 533) + tmp = ((DDR3_TCKE_533MHZ * nmhz + 999) / 1000); + else + tmp = ((DDR3_TCKE_400MHZ * nmhz + (nmhz >> 1) + 999) / 1000); + pdram_timing->tcke = max(3, tmp); + pdram_timing->tckesr = (pdram_timing->tcke + 1); + tmp = ((DDR3_TCKSRE * nmhz + 999) / 1000); + pdram_timing->tcksre = max(5, tmp); + pdram_timing->tcksrx = max(5, tmp); + /*mode register timing*/ + tmp = ((DDR3_TMOD * nmhz + 999) / 1000); + pdram_timing->tmod = max(12, tmp); + pdram_timing->tmrd = DDR3_TMRD; + pdram_timing->tmrr = 0; + /*ODT*/ + pdram_timing->todton = pdram_timing->cwl - 2; + /*ZQ*/ + tmp = ((DDR3_TZQINIT * nmhz + 999) / 1000); + pdram_timing->tzqinit = max(512, tmp); + tmp = ((DDR3_TZQCS * nmhz + 999) / 1000); + pdram_timing->tzqcs = max(64, tmp); + tmp = ((DDR3_TZQOPER * nmhz + 999) / 1000); + pdram_timing->tzqoper = max(256, tmp); + /* write leveling */ + pdram_timing->twlmrd = DDR3_TWLMRD; + pdram_timing->twldqsen = DDR3_TWLDQSEN; + pdram_timing->twlo = ((DDR3_TWLO * nmhz + (nmhz >> 1) + 999) / 1000); +} + +#define LPDDR2_TINIT1 (100) /* ns */ +#define LPDDR2_TINIT2 (5) /* tCK */ +#define LPDDR2_TINIT3 (200000) /* 200us */ +#define LPDDR2_TINIT4 (1000) /* 1us */ +#define LPDDR2_TINIT5 (10000) /* 10us */ +#define LPDDR2_TRSTL (0) /* tCK */ +#define LPDDR2_TRSTH (500000) /* 500us */ +#define LPDDR2_TREFI_3_9_US (3900) /* 3.9us */ +#define LPDDR2_TREFI_7_8_US (7800) /* 7.8us */ + +/* base timing */ +#define LPDDR2_TRCD (24) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */ +#define LPDDR2_TRP_PB (18) /* tRPpb,15ns(Fast)18ns(Typ)24ns(Slow) */ +#define LPDDR2_TRP_AB_8_BANK (21) /* tRPab,18ns(Fast)21ns(Typ)27ns(Slow) */ +#define LPDDR2_TWR (15) /* tWR, max(3tCK,15ns) */ +#define LPDDR2_TRTP (7) /* tRTP, max(2tCK, 7.5ns) */ +#define LPDDR2_TRRD (10) /* tRRD, max(2tCK,10ns) */ +#define LPDDR2_TCCD (2) /* tCK */ +#define LPDDR2_TWTR_GREAT_200MHZ (7) /* ns */ +#define LPDDR2_TWTR_LITTLE_200MHZ (10) /* ns */ +#define LPDDR2_TRTW (0) /* tCK */ +#define LPDDR2_TRAS_MAX (70000) /* 70us */ +#define LPDDR2_TRAS (42) /* tRAS, max(3tCK,42ns) */ +#define LPDDR2_TFAW_GREAT_200MHZ (50) /* max(8tCK,50ns) */ +#define LPDDR2_TFAW_LITTLE_200MHZ (60) /* max(8tCK,60ns) */ +#define LPDDR2_TRFC_8GBIT (210) /* ns */ +#define LPDDR2_TRFC_4GBIT (130) /* ns */ +#define LPDDR2_TDQSCK_MIN (2) /* tDQSCKmin, 2.5ns */ +#define LPDDR2_TDQSCK_MAX (5) /* tDQSCKmax, 5.5ns */ + +/*pd and sr*/ +#define LPDDR2_TXP (7) /* tXP, max(2tCK,7.5ns) */ +#define LPDDR2_TXPDLL (0) +#define LPDDR2_TDLLK (0) /* tCK */ +#define LPDDR2_TCKE (3) /* tCK */ +#define LPDDR2_TCKESR (15) /* tCKESR, max(3tCK,15ns) */ +#define LPDDR2_TCKSRE (1) /* tCK */ +#define LPDDR2_TCKSRX (2) /* tCK */ + +/*mode register timing*/ +#define LPDDR2_TMOD (0) +#define LPDDR2_TMRD (5) /* tMRD, (=tMRW), 5 tCK */ +#define LPDDR2_TMRR (2) /* tCK */ + +/*ZQ*/ +#define LPDDR2_TZQINIT (1000) /* ns */ +#define LPDDR2_TZQCS (90) /* tZQCS, max(6tCK,90ns) */ +#define LPDDR2_TZQCL (360) /* tZQCL, max(6tCK,360ns) */ +#define LPDDR2_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ + +/* + * Description: depend on input parameter "timing_config", + * and calculate all lpddr2 + * spec timing to "pdram_timing" + * parameters: + * input: timing_config + * output: pdram_timing + */ +static void lpddr2_get_parameter(struct timing_related_config *timing_config, + struct dram_timing_t *pdram_timing) +{ + uint32_t nmhz = timing_config->freq; + uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); + uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; + + memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); + pdram_timing->mhz = nmhz; + pdram_timing->al = 0; + pdram_timing->bl = timing_config->bl; + + /* 1066 933 800 667 533 400 333 + * RL, 8 7 6 5 4 3 3 + * WL, 4 4 3 2 2 1 1 + */ + if (nmhz <= 266) { + pdram_timing->cl = 4; + pdram_timing->cwl = 2; + pdram_timing->mr[2] = LPDDR2_RL4_WL2; + } else if (nmhz <= 333) { + pdram_timing->cl = 5; + pdram_timing->cwl = 2; + pdram_timing->mr[2] = LPDDR2_RL5_WL2; + } else if (nmhz <= 400) { + pdram_timing->cl = 6; + pdram_timing->cwl = 3; + pdram_timing->mr[2] = LPDDR2_RL6_WL3; + } else if (nmhz <= 466) { + pdram_timing->cl = 7; + pdram_timing->cwl = 4; + pdram_timing->mr[2] = LPDDR2_RL7_WL4; + } else { + pdram_timing->cl = 8; + pdram_timing->cwl = 4; + pdram_timing->mr[2] = LPDDR2_RL8_WL4; + } + switch (timing_config->dramds) { + case 120: + pdram_timing->mr[3] = LPDDR2_DS_120; + break; + case 80: + pdram_timing->mr[3] = LPDDR2_DS_80; + break; + case 60: + pdram_timing->mr[3] = LPDDR2_DS_60; + break; + case 48: + pdram_timing->mr[3] = LPDDR2_DS_48; + break; + case 40: + pdram_timing->mr[3] = LPDDR2_DS_40; + break; + case 34: + default: + pdram_timing->mr[3] = LPDDR2_DS_34; + break; + } + pdram_timing->mr[0] = 0; + + pdram_timing->tinit1 = (LPDDR2_TINIT1 * nmhz + 999) / 1000; + pdram_timing->tinit2 = LPDDR2_TINIT2; + pdram_timing->tinit3 = (LPDDR2_TINIT3 * nmhz + 999) / 1000; + pdram_timing->tinit4 = (LPDDR2_TINIT4 * nmhz + 999) / 1000; + pdram_timing->tinit5 = (LPDDR2_TINIT5 * nmhz + 999) / 1000; + pdram_timing->trstl = LPDDR2_TRSTL; + pdram_timing->trsth = (LPDDR2_TRSTH * nmhz + 999) / 1000; + /* + * tREFI, average periodic refresh interval, + * 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb) + */ + if (ddr_capability_per_die >= 0x10000000) + pdram_timing->trefi = (LPDDR2_TREFI_3_9_US * nmhz + 999) + / 1000; + else + pdram_timing->trefi = (LPDDR2_TREFI_7_8_US * nmhz + 999) + / 1000; + /* base timing */ + tmp = ((LPDDR2_TRCD * nmhz + 999) / 1000); + pdram_timing->trcd = max(3, tmp); + /* + * tRPpb, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow), + */ + trppb_tmp = ((LPDDR2_TRP_PB * nmhz + 999) / 1000); + trppb_tmp = max(3, trppb_tmp); + pdram_timing->trppb = trppb_tmp; + /* + * tRPab, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), + * 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow)) + */ + trp_tmp = ((LPDDR2_TRP_AB_8_BANK * nmhz + 999) / 1000); + trp_tmp = max(3, trp_tmp); + pdram_timing->trp = trp_tmp; + twr_tmp = ((LPDDR2_TWR * nmhz + 999) / 1000); + twr_tmp = max(3, twr_tmp); + pdram_timing->twr = twr_tmp; + bl_tmp = (pdram_timing->bl == 16) ? LPDDR2_BL16 : + ((pdram_timing->bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4); + pdram_timing->mr[1] = bl_tmp | LPDDR2_N_WR(twr_tmp); + tmp = ((LPDDR2_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); + pdram_timing->trtp = max(2, tmp); + tras_tmp = ((LPDDR2_TRAS * nmhz + 999) / 1000); + tras_tmp = max(3, tras_tmp); + pdram_timing->tras_min = tras_tmp; + pdram_timing->tras_max = ((LPDDR2_TRAS_MAX * nmhz + 999) / 1000); + pdram_timing->trc = (tras_tmp + trp_tmp); + tmp = ((LPDDR2_TRRD * nmhz + 999) / 1000); + pdram_timing->trrd = max(2, tmp); + pdram_timing->tccd = LPDDR2_TCCD; + /* tWTR, max(2tCK, 7.5ns(533-266MHz) 10ns(200-166MHz)) */ + if (nmhz > 200) + tmp = ((LPDDR2_TWTR_GREAT_200MHZ * nmhz + (nmhz >> 1) + + 999) / 1000); + else + tmp = ((LPDDR2_TWTR_LITTLE_200MHZ * nmhz + 999) / 1000); + pdram_timing->twtr = max(2, tmp); + pdram_timing->trtw = LPDDR2_TRTW; + if (nmhz <= 200) + pdram_timing->tfaw = (LPDDR2_TFAW_LITTLE_200MHZ * nmhz + 999) + / 1000; + else + pdram_timing->tfaw = (LPDDR2_TFAW_GREAT_200MHZ * nmhz + 999) + / 1000; + /* tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb) */ + if (ddr_capability_per_die >= 0x40000000) { + pdram_timing->trfc = + (LPDDR2_TRFC_8GBIT * nmhz + 999) / 1000; + tmp = (((LPDDR2_TRFC_8GBIT + 10) * nmhz + 999) / 1000); + } else { + pdram_timing->trfc = + (LPDDR2_TRFC_4GBIT * nmhz + 999) / 1000; + tmp = (((LPDDR2_TRFC_4GBIT + 10) * nmhz + 999) / 1000); + } + if (tmp < 2) + tmp = 2; + pdram_timing->txsr = tmp; + pdram_timing->txsnr = tmp; + /* tdqsck use rounded down */ + pdram_timing->tdqsck = ((LPDDR2_TDQSCK_MIN * nmhz + (nmhz >> 1)) + / 1000); + pdram_timing->tdqsck_max = + ((LPDDR2_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999) + / 1000); + /* pd and sr */ + tmp = ((LPDDR2_TXP * nmhz + (nmhz >> 1) + 999) / 1000); + pdram_timing->txp = max(2, tmp); + pdram_timing->txpdll = LPDDR2_TXPDLL; + pdram_timing->tdllk = LPDDR2_TDLLK; + pdram_timing->tcke = LPDDR2_TCKE; + tmp = ((LPDDR2_TCKESR * nmhz + 999) / 1000); + pdram_timing->tckesr = max(3, tmp); + pdram_timing->tcksre = LPDDR2_TCKSRE; + pdram_timing->tcksrx = LPDDR2_TCKSRX; + /* mode register timing */ + pdram_timing->tmod = LPDDR2_TMOD; + pdram_timing->tmrd = LPDDR2_TMRD; + pdram_timing->tmrr = LPDDR2_TMRR; + /* ZQ */ + pdram_timing->tzqinit = (LPDDR2_TZQINIT * nmhz + 999) / 1000; + tmp = ((LPDDR2_TZQCS * nmhz + 999) / 1000); + pdram_timing->tzqcs = max(6, tmp); + tmp = ((LPDDR2_TZQCL * nmhz + 999) / 1000); + pdram_timing->tzqoper = max(6, tmp); + tmp = ((LPDDR2_TZQRESET * nmhz + 999) / 1000); + pdram_timing->tzqreset = max(3, tmp); +} + +#define LPDDR3_TINIT1 (100) /* ns */ +#define LPDDR3_TINIT2 (5) /* tCK */ +#define LPDDR3_TINIT3 (200000) /* 200us */ +#define LPDDR3_TINIT4 (1000) /* 1us */ +#define LPDDR3_TINIT5 (10000) /* 10us */ +#define LPDDR3_TRSTL (0) +#define LPDDR3_TRSTH (0) /* 500us */ +#define LPDDR3_TREFI_3_9_US (3900) /* 3.9us */ + +/* base timging */ +#define LPDDR3_TRCD (18) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */ +#define LPDDR3_TRP_PB (18) /* tRPpb, 15ns(Fast) 18ns(Typ) 24ns(Slow) */ +#define LPDDR3_TRP_AB (21) /* tRPab, 18ns(Fast) 21ns(Typ) 27ns(Slow) */ +#define LPDDR3_TWR (15) /* tWR, max(4tCK,15ns) */ +#define LPDDR3_TRTP (7) /* tRTP, max(4tCK, 7.5ns) */ +#define LPDDR3_TRRD (10) /* tRRD, max(2tCK,10ns) */ +#define LPDDR3_TCCD (4) /* tCK */ +#define LPDDR3_TWTR (7) /* tWTR, max(4tCK, 7.5ns) */ +#define LPDDR3_TRTW (0) /* tCK register min valid value */ +#define LPDDR3_TRAS_MAX (70000) /* 70us */ +#define LPDDR3_TRAS (42) /* tRAS, max(3tCK,42ns) */ +#define LPDDR3_TFAW (50) /* tFAW,max(8tCK, 50ns) */ +#define LPDDR3_TRFC_8GBIT (210) /* tRFC, 130ns(4Gb) 210ns(>4Gb) */ +#define LPDDR3_TRFC_4GBIT (130) /* ns */ +#define LPDDR3_TDQSCK_MIN (2) /* tDQSCKmin,2.5ns */ +#define LPDDR3_TDQSCK_MAX (5) /* tDQSCKmax,5.5ns */ + +/* pd and sr */ +#define LPDDR3_TXP (7) /* tXP, max(3tCK,7.5ns) */ +#define LPDDR3_TXPDLL (0) +#define LPDDR3_TCKE (7) /* tCKE, (max 7.5ns,3 tCK) */ +#define LPDDR3_TCKESR (15) /* tCKESR, max(3tCK,15ns) */ +#define LPDDR3_TCKSRE (2) /* tCKSRE=tCPDED, 2 tCK */ +#define LPDDR3_TCKSRX (2) /* tCKSRX, 2 tCK */ + +/* mode register timing */ +#define LPDDR3_TMOD (0) +#define LPDDR3_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */ +#define LPDDR3_TMRR (4) /* tMRR, 4 tCK */ +#define LPDDR3_TMRRI LPDDR3_TRCD + +/* ODT */ +#define LPDDR3_TODTON (3) /* 3.5ns */ + +/* ZQ */ +#define LPDDR3_TZQINIT (1000) /* 1us */ +#define LPDDR3_TZQCS (90) /* tZQCS, 90ns */ +#define LPDDR3_TZQCL (360) /* 360ns */ +#define LPDDR3_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ +/* write leveling */ +#define LPDDR3_TWLMRD (40) /* ns */ +#define LPDDR3_TWLO (20) /* ns */ +#define LPDDR3_TWLDQSEN (25) /* ns */ +/* CA training */ +#define LPDDR3_TCACKEL (10) /* tCK */ +#define LPDDR3_TCAENT (10) /* tCK */ +#define LPDDR3_TCAMRD (20) /* tCK */ +#define LPDDR3_TCACKEH (10) /* tCK */ +#define LPDDR3_TCAEXT (10) /* tCK */ +#define LPDDR3_TADR (20) /* ns */ +#define LPDDR3_TMRZ (3) /* ns */ + +/* + * Description: depend on input parameter "timing_config", + * and calculate all lpddr3 + * spec timing to "pdram_timing" + * parameters: + * input: timing_config + * output: pdram_timing + */ +static void lpddr3_get_parameter(struct timing_related_config *timing_config, + struct dram_timing_t *pdram_timing) +{ + uint32_t nmhz = timing_config->freq; + uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); + uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; + + memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); + pdram_timing->mhz = nmhz; + pdram_timing->al = 0; + pdram_timing->bl = timing_config->bl; + + /* + * Only support Write Latency Set A here + * 1066 933 800 733 667 600 533 400 166 + * RL, 16 14 12 11 10 9 8 6 3 + * WL, 8 8 6 6 6 5 4 3 1 + */ + if (nmhz <= 400) { + pdram_timing->cl = 6; + pdram_timing->cwl = 3; + pdram_timing->mr[2] = LPDDR3_RL6_WL3; + } else if (nmhz <= 533) { + pdram_timing->cl = 8; + pdram_timing->cwl = 4; + pdram_timing->mr[2] = LPDDR3_RL8_WL4; + } else if (nmhz <= 600) { + pdram_timing->cl = 9; + pdram_timing->cwl = 5; + pdram_timing->mr[2] = LPDDR3_RL9_WL5; + } else if (nmhz <= 667) { + pdram_timing->cl = 10; + pdram_timing->cwl = 6; + pdram_timing->mr[2] = LPDDR3_RL10_WL6; + } else if (nmhz <= 733) { + pdram_timing->cl = 11; + pdram_timing->cwl = 6; + pdram_timing->mr[2] = LPDDR3_RL11_WL6; + } else if (nmhz <= 800) { + pdram_timing->cl = 12; + pdram_timing->cwl = 6; + pdram_timing->mr[2] = LPDDR3_RL12_WL6; + } else if (nmhz <= 933) { + pdram_timing->cl = 14; + pdram_timing->cwl = 8; + pdram_timing->mr[2] = LPDDR3_RL14_WL8; + } else { + pdram_timing->cl = 16; + pdram_timing->cwl = 8; + pdram_timing->mr[2] = LPDDR3_RL16_WL8; + } + switch (timing_config->dramds) { + case 80: + pdram_timing->mr[3] = LPDDR3_DS_80; + break; + case 60: + pdram_timing->mr[3] = LPDDR3_DS_60; + break; + case 48: + pdram_timing->mr[3] = LPDDR3_DS_48; + break; + case 40: + pdram_timing->mr[3] = LPDDR3_DS_40; + break; + case 3440: + pdram_timing->mr[3] = LPDDR3_DS_34D_40U; + break; + case 4048: + pdram_timing->mr[3] = LPDDR3_DS_40D_48U; + break; + case 3448: + pdram_timing->mr[3] = LPDDR3_DS_34D_48U; + break; + case 34: + default: + pdram_timing->mr[3] = LPDDR3_DS_34; + break; + } + pdram_timing->mr[0] = 0; + switch (timing_config->dramodt) { + case 60: + pdram_timing->mr11 = LPDDR3_ODT_60; + break; + case 120: + pdram_timing->mr11 = LPDDR3_ODT_120; + break; + case 240: + default: + pdram_timing->mr11 = LPDDR3_ODT_240; + break; + } + + pdram_timing->tinit1 = (LPDDR3_TINIT1 * nmhz + 999) / 1000; + pdram_timing->tinit2 = LPDDR3_TINIT2; + pdram_timing->tinit3 = (LPDDR3_TINIT3 * nmhz + 999) / 1000; + pdram_timing->tinit4 = (LPDDR3_TINIT4 * nmhz + 999) / 1000; + pdram_timing->tinit5 = (LPDDR3_TINIT5 * nmhz + 999) / 1000; + pdram_timing->trstl = LPDDR3_TRSTL; + pdram_timing->trsth = (LPDDR3_TRSTH * nmhz + 999) / 1000; + /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */ + pdram_timing->trefi = (LPDDR3_TREFI_3_9_US * nmhz + 999) / 1000; + /* base timing */ + tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000); + pdram_timing->trcd = max(3, tmp); + trppb_tmp = ((LPDDR3_TRP_PB * nmhz + 999) / 1000); + trppb_tmp = max(3, trppb_tmp); + pdram_timing->trppb = trppb_tmp; + trp_tmp = ((LPDDR3_TRP_AB * nmhz + 999) / 1000); + trp_tmp = max(3, trp_tmp); + pdram_timing->trp = trp_tmp; + twr_tmp = ((LPDDR3_TWR * nmhz + 999) / 1000); + twr_tmp = max(4, twr_tmp); + pdram_timing->twr = twr_tmp; + if (twr_tmp <= 6) + twr_tmp = 6; + else if (twr_tmp <= 8) + twr_tmp = 8; + else if (twr_tmp <= 12) + twr_tmp = twr_tmp; + else if (twr_tmp <= 14) + twr_tmp = 14; + else + twr_tmp = 16; + if (twr_tmp > 9) + pdram_timing->mr[2] |= (1 << 4); /*enable nWR > 9*/ + twr_tmp = (twr_tmp > 9) ? (twr_tmp - 10) : (twr_tmp - 2); + bl_tmp = LPDDR3_BL8; + pdram_timing->mr[1] = bl_tmp | LPDDR3_N_WR(twr_tmp); + tmp = ((LPDDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); + pdram_timing->trtp = max(4, tmp); + tras_tmp = ((LPDDR3_TRAS * nmhz + 999) / 1000); + tras_tmp = max(3, tras_tmp); + pdram_timing->tras_min = tras_tmp; + pdram_timing->trc = (tras_tmp + trp_tmp); + tmp = ((LPDDR3_TRRD * nmhz + 999) / 1000); + pdram_timing->trrd = max(2, tmp); + pdram_timing->tccd = LPDDR3_TCCD; + tmp = ((LPDDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000); + pdram_timing->twtr = max(4, tmp); + pdram_timing->trtw = ((LPDDR3_TRTW * nmhz + 999) / 1000); + pdram_timing->tras_max = ((LPDDR3_TRAS_MAX * nmhz + 999) / 1000); + tmp = (LPDDR3_TFAW * nmhz + 999) / 1000; + pdram_timing->tfaw = max(8, tmp); + if (ddr_capability_per_die > 0x20000000) { + pdram_timing->trfc = + (LPDDR3_TRFC_8GBIT * nmhz + 999) / 1000; + tmp = (((LPDDR3_TRFC_8GBIT + 10) * nmhz + 999) / 1000); + } else { + pdram_timing->trfc = + (LPDDR3_TRFC_4GBIT * nmhz + 999) / 1000; + tmp = (((LPDDR3_TRFC_4GBIT + 10) * nmhz + 999) / 1000); + } + pdram_timing->txsr = max(2, tmp); + pdram_timing->txsnr = max(2, tmp); + /* tdqsck use rounded down */ + pdram_timing->tdqsck = + ((LPDDR3_TDQSCK_MIN * nmhz + (nmhz >> 1)) + / 1000); + pdram_timing->tdqsck_max = + ((LPDDR3_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999) + / 1000); + /*pd and sr*/ + tmp = ((LPDDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000); + pdram_timing->txp = max(3, tmp); + pdram_timing->txpdll = LPDDR3_TXPDLL; + tmp = ((LPDDR3_TCKE * nmhz + (nmhz >> 1) + 999) / 1000); + pdram_timing->tcke = max(3, tmp); + tmp = ((LPDDR3_TCKESR * nmhz + 999) / 1000); + pdram_timing->tckesr = max(3, tmp); + pdram_timing->tcksre = LPDDR3_TCKSRE; + pdram_timing->tcksrx = LPDDR3_TCKSRX; + /*mode register timing*/ + pdram_timing->tmod = LPDDR3_TMOD; + tmp = ((LPDDR3_TMRD * nmhz + 999) / 1000); + pdram_timing->tmrd = max(10, tmp); + pdram_timing->tmrr = LPDDR3_TMRR; + tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000); + pdram_timing->tmrri = max(3, tmp); + /* ODT */ + pdram_timing->todton = (LPDDR3_TODTON * nmhz + (nmhz >> 1) + 999) + / 1000; + /* ZQ */ + pdram_timing->tzqinit = (LPDDR3_TZQINIT * nmhz + 999) / 1000; + pdram_timing->tzqcs = + ((LPDDR3_TZQCS * nmhz + 999) / 1000); + pdram_timing->tzqoper = + ((LPDDR3_TZQCL * nmhz + 999) / 1000); + tmp = ((LPDDR3_TZQRESET * nmhz + 999) / 1000); + pdram_timing->tzqreset = max(3, tmp); + /* write leveling */ + pdram_timing->twlmrd = (LPDDR3_TWLMRD * nmhz + 999) / 1000; + pdram_timing->twlo = (LPDDR3_TWLO * nmhz + 999) / 1000; + pdram_timing->twldqsen = (LPDDR3_TWLDQSEN * nmhz + 999) / 1000; + /* CA training */ + pdram_timing->tcackel = LPDDR3_TCACKEL; + pdram_timing->tcaent = LPDDR3_TCAENT; + pdram_timing->tcamrd = LPDDR3_TCAMRD; + pdram_timing->tcackeh = LPDDR3_TCACKEH; + pdram_timing->tcaext = LPDDR3_TCAEXT; + pdram_timing->tadr = (LPDDR3_TADR * nmhz + 999) / 1000; + pdram_timing->tmrz = (LPDDR3_TMRZ * nmhz + 999) / 1000; + pdram_timing->tcacd = pdram_timing->tadr + 2; +} + +#define LPDDR4_TINIT1 (200000) /* 200us */ +#define LPDDR4_TINIT2 (10) /* 10ns */ +#define LPDDR4_TINIT3 (2000000) /* 2ms */ +#define LPDDR4_TINIT4 (5) /* tCK */ +#define LPDDR4_TINIT5 (2000) /* 2us */ +#define LPDDR4_TRSTL LPDDR4_TINIT1 +#define LPDDR4_TRSTH LPDDR4_TINIT3 +#define LPDDR4_TREFI_3_9_US (3900) /* 3.9us */ + +/* base timging */ +#define LPDDR4_TRCD (18) /* tRCD, max(18ns,4tCK) */ +#define LPDDR4_TRP_PB (18) /* tRPpb, max(18ns, 4tCK) */ +#define LPDDR4_TRP_AB (21) /* tRPab, max(21ns, 4tCK) */ +#define LPDDR4_TRRD (10) /* tRRD, max(4tCK,10ns) */ +#define LPDDR4_TCCD_BL16 (8) /* tCK */ +#define LPDDR4_TCCD_BL32 (16) /* tCK */ +#define LPDDR4_TWTR (10) /* tWTR, max(8tCK, 10ns) */ +#define LPDDR4_TRTW (0) /* tCK register min valid value */ +#define LPDDR4_TRAS_MAX (70000) /* 70us */ +#define LPDDR4_TRAS (42) /* tRAS, max(3tCK,42ns) */ +#define LPDDR4_TFAW (40) /* tFAW,min 40ns) */ +#define LPDDR4_TRFC_12GBIT (280) /* tRFC, 280ns(>=12Gb) */ +#define LPDDR4_TRFC_6GBIT (180) /* 6Gb/8Gb 180ns */ +#define LPDDR4_TRFC_4GBIT (130) /* 4Gb 130ns */ +#define LPDDR4_TDQSCK_MIN (1) /* tDQSCKmin,1.5ns */ +#define LPDDR4_TDQSCK_MAX (3) /* tDQSCKmax,3.5ns */ +#define LPDDR4_TPPD (4) /* tCK */ + +/* pd and sr */ +#define LPDDR4_TXP (7) /* tXP, max(5tCK,7.5ns) */ +#define LPDDR4_TCKE (7) /* tCKE, max(7.5ns,4 tCK) */ +#define LPDDR4_TESCKE (1) /* tESCKE, max(1.75ns, 3tCK) */ +#define LPDDR4_TSR (15) /* tSR, max(15ns, 3tCK) */ +#define LPDDR4_TCMDCKE (1) /* max(1.75ns, 3tCK) */ +#define LPDDR4_TCSCKE (1) /* 1.75ns */ +#define LPDDR4_TCKELCS (5) /* max(5ns, 5tCK) */ +#define LPDDR4_TCSCKEH (1) /* 1.75ns */ +#define LPDDR4_TCKEHCS (7) /* max(7.5ns, 5tCK) */ +#define LPDDR4_TMRWCKEL (14) /* max(14ns, 10tCK) */ +#define LPDDR4_TCKELCMD (7) /* max(7.5ns, 3tCK) */ +#define LPDDR4_TCKEHCMD (7) /* max(7.5ns, 3tCK) */ +#define LPDDR4_TCKELPD (7) /* max(7.5ns, 3tCK) */ +#define LPDDR4_TCKCKEL (7) /* max(7.5ns, 3tCK) */ + +/* mode register timing */ +#define LPDDR4_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */ +#define LPDDR4_TMRR (8) /* tMRR, 8 tCK */ + +/* ODT */ +#define LPDDR4_TODTON (3) /* 3.5ns */ + +/* ZQ */ +#define LPDDR4_TZQCAL (1000) /* 1us */ +#define LPDDR4_TZQLAT (30) /* tZQLAT, max(30ns,8tCK) */ +#define LPDDR4_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ +#define LPDDR4_TZQCKE (1) /* tZQCKE, max(1.75ns, 3tCK) */ + +/* write leveling */ +#define LPDDR4_TWLMRD (40) /* tCK */ +#define LPDDR4_TWLO (20) /* ns */ +#define LPDDR4_TWLDQSEN (20) /* tCK */ + +/* CA training */ +#define LPDDR4_TCAENT (250) /* ns */ +#define LPDDR4_TADR (20) /* ns */ +#define LPDDR4_TMRZ (1) /* 1.5ns */ +#define LPDDR4_TVREF_LONG (250) /* ns */ +#define LPDDR4_TVREF_SHORT (100) /* ns */ + +/* VRCG */ +#define LPDDR4_TVRCG_ENABLE (200) /* ns */ +#define LPDDR4_TVRCG_DISABLE (100) /* ns */ + +/* FSP */ +#define LPDDR4_TFC_LONG (250) /* ns */ +#define LPDDR4_TCKFSPE (7) /* max(7.5ns, 4tCK) */ +#define LPDDR4_TCKFSPX (7) /* max(7.5ns, 4tCK) */ + +/* + * Description: depend on input parameter "timing_config", + * and calculate all lpddr4 + * spec timing to "pdram_timing" + * parameters: + * input: timing_config + * output: pdram_timing + */ +static void lpddr4_get_parameter(struct timing_related_config *timing_config, + struct dram_timing_t *pdram_timing) +{ + uint32_t nmhz = timing_config->freq; + uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); + uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp; + + memset((void *)pdram_timing, 0, sizeof(struct dram_timing_t)); + pdram_timing->mhz = nmhz; + pdram_timing->al = 0; + pdram_timing->bl = timing_config->bl; + + /* + * Only support Write Latency Set A here + * 2133 1866 1600 1333 1066 800 533 266 + * RL, 36 32 28 24 20 14 10 6 + * WL, 18 16 14 12 10 8 6 4 + * nWR, 40 34 30 24 20 16 10 6 + * nRTP,16 14 12 10 8 8 8 8 + */ + tmp = (timing_config->bl == 32) ? 1 : 0; + + /* + * we always use WR preamble = 2tCK + * RD preamble = Static + */ + tmp |= (1 << 2); + if (nmhz <= 266) { + pdram_timing->cl = 6; + pdram_timing->cwl = 4; + pdram_timing->twr = 6; + pdram_timing->trtp = 8; + pdram_timing->mr[2] = LPDDR4_RL6_NRTP8 | LPDDR4_A_WL4; + } else if (nmhz <= 533) { + if (timing_config->rdbi) { + pdram_timing->cl = 12; + pdram_timing->mr[2] = LPDDR4_RL12_NRTP8 | LPDDR4_A_WL6; + } else { + pdram_timing->cl = 10; + pdram_timing->mr[2] = LPDDR4_RL10_NRTP8 | LPDDR4_A_WL6; + } + pdram_timing->cwl = 6; + pdram_timing->twr = 10; + pdram_timing->trtp = 8; + tmp |= (1 << 4); + } else if (nmhz <= 800) { + if (timing_config->rdbi) { + pdram_timing->cl = 16; + pdram_timing->mr[2] = LPDDR4_RL16_NRTP8 | LPDDR4_A_WL8; + } else { + pdram_timing->cl = 14; + pdram_timing->mr[2] = LPDDR4_RL14_NRTP8 | LPDDR4_A_WL8; + } + pdram_timing->cwl = 8; + pdram_timing->twr = 16; + pdram_timing->trtp = 8; + tmp |= (2 << 4); + } else if (nmhz <= 1066) { + if (timing_config->rdbi) { + pdram_timing->cl = 22; + pdram_timing->mr[2] = LPDDR4_RL22_NRTP8 | LPDDR4_A_WL10; + } else { + pdram_timing->cl = 20; + pdram_timing->mr[2] = LPDDR4_RL20_NRTP8 | LPDDR4_A_WL10; + } + pdram_timing->cwl = 10; + pdram_timing->twr = 20; + pdram_timing->trtp = 8; + tmp |= (3 << 4); + } else if (nmhz <= 1333) { + if (timing_config->rdbi) { + pdram_timing->cl = 28; + pdram_timing->mr[2] = LPDDR4_RL28_NRTP10 | + LPDDR4_A_WL12; + } else { + pdram_timing->cl = 24; + pdram_timing->mr[2] = LPDDR4_RL24_NRTP10 | + LPDDR4_A_WL12; + } + pdram_timing->cwl = 12; + pdram_timing->twr = 24; + pdram_timing->trtp = 10; + tmp |= (4 << 4); + } else if (nmhz <= 1600) { + if (timing_config->rdbi) { + pdram_timing->cl = 32; + pdram_timing->mr[2] = LPDDR4_RL32_NRTP12 | + LPDDR4_A_WL14; + } else { + pdram_timing->cl = 28; + pdram_timing->mr[2] = LPDDR4_RL28_NRTP12 | + LPDDR4_A_WL14; + } + pdram_timing->cwl = 14; + pdram_timing->twr = 30; + pdram_timing->trtp = 12; + tmp |= (5 << 4); + } else if (nmhz <= 1866) { + if (timing_config->rdbi) { + pdram_timing->cl = 36; + pdram_timing->mr[2] = LPDDR4_RL36_NRTP14 | + LPDDR4_A_WL16; + } else { + pdram_timing->cl = 32; + pdram_timing->mr[2] = LPDDR4_RL32_NRTP14 | + LPDDR4_A_WL16; + } + pdram_timing->cwl = 16; + pdram_timing->twr = 34; + pdram_timing->trtp = 14; + tmp |= (6 << 4); + } else { + if (timing_config->rdbi) { + pdram_timing->cl = 40; + pdram_timing->mr[2] = LPDDR4_RL40_NRTP16 | + LPDDR4_A_WL18; + } else { + pdram_timing->cl = 36; + pdram_timing->mr[2] = LPDDR4_RL36_NRTP16 | + LPDDR4_A_WL18; + } + pdram_timing->cwl = 18; + pdram_timing->twr = 40; + pdram_timing->trtp = 16; + tmp |= (7 << 4); + } + pdram_timing->mr[1] = tmp; + tmp = (timing_config->rdbi ? LPDDR4_DBI_RD_EN : 0) | + (timing_config->wdbi ? LPDDR4_DBI_WR_EN : 0); + switch (timing_config->dramds) { + case 240: + pdram_timing->mr[3] = LPDDR4_PDDS_240 | tmp; + break; + case 120: + pdram_timing->mr[3] = LPDDR4_PDDS_120 | tmp; + break; + case 80: + pdram_timing->mr[3] = LPDDR4_PDDS_80 | tmp; + break; + case 60: + pdram_timing->mr[3] = LPDDR4_PDDS_60 | tmp; + break; + case 48: + pdram_timing->mr[3] = LPDDR4_PDDS_48 | tmp; + break; + case 40: + default: + pdram_timing->mr[3] = LPDDR4_PDDS_40 | tmp; + break; + } + pdram_timing->mr[0] = 0; + switch (timing_config->dramodt) { + case 240: + tmp = LPDDR4_DQODT_240; + break; + case 120: + tmp = LPDDR4_DQODT_120; + break; + case 80: + tmp = LPDDR4_DQODT_80; + break; + case 60: + tmp = LPDDR4_DQODT_60; + break; + case 48: + tmp = LPDDR4_DQODT_48; + break; + case 40: + default: + tmp = LPDDR4_DQODT_40; + break; + } + switch (timing_config->caodt) { + case 240: + pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp; + break; + case 120: + pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp; + break; + case 80: + pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp; + break; + case 60: + pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp; + break; + case 48: + pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp; + break; + case 40: + default: + pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp; + break; + } + + pdram_timing->tinit1 = (LPDDR4_TINIT1 * nmhz + 999) / 1000; + pdram_timing->tinit2 = (LPDDR4_TINIT2 * nmhz + 999) / 1000; + pdram_timing->tinit3 = (LPDDR4_TINIT3 * nmhz + 999) / 1000; + pdram_timing->tinit4 = (LPDDR4_TINIT4 * nmhz + 999) / 1000; + pdram_timing->tinit5 = (LPDDR4_TINIT5 * nmhz + 999) / 1000; + pdram_timing->trstl = (LPDDR4_TRSTL * nmhz + 999) / 1000; + pdram_timing->trsth = (LPDDR4_TRSTH * nmhz + 999) / 1000; + /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */ + pdram_timing->trefi = (LPDDR4_TREFI_3_9_US * nmhz + 999) / 1000; + /* base timing */ + tmp = ((LPDDR4_TRCD * nmhz + 999) / 1000); + pdram_timing->trcd = max(4, tmp); + trppb_tmp = ((LPDDR4_TRP_PB * nmhz + 999) / 1000); + trppb_tmp = max(4, trppb_tmp); + pdram_timing->trppb = trppb_tmp; + trp_tmp = ((LPDDR4_TRP_AB * nmhz + 999) / 1000); + trp_tmp = max(4, trp_tmp); + pdram_timing->trp = trp_tmp; + tras_tmp = ((LPDDR4_TRAS * nmhz + 999) / 1000); + tras_tmp = max(3, tras_tmp); + pdram_timing->tras_min = tras_tmp; + pdram_timing->trc = (tras_tmp + trp_tmp); + tmp = ((LPDDR4_TRRD * nmhz + 999) / 1000); + pdram_timing->trrd = max(4, tmp); + if (timing_config->bl == 32) + pdram_timing->tccd = LPDDR4_TCCD_BL16; + else + pdram_timing->tccd = LPDDR4_TCCD_BL32; + pdram_timing->tccdmw = 4 * pdram_timing->tccd; + tmp = ((LPDDR4_TWTR * nmhz + 999) / 1000); + pdram_timing->twtr = max(8, tmp); + pdram_timing->trtw = ((LPDDR4_TRTW * nmhz + 999) / 1000); + pdram_timing->tras_max = ((LPDDR4_TRAS_MAX * nmhz + 999) / 1000); + pdram_timing->tfaw = (LPDDR4_TFAW * nmhz + 999) / 1000; + if (ddr_capability_per_die > 0x60000000) { + /* >= 12Gb */ + pdram_timing->trfc = + (LPDDR4_TRFC_12GBIT * nmhz + 999) / 1000; + tmp = (((LPDDR4_TRFC_12GBIT + 7) * nmhz + (nmhz >> 1) + + 999) / 1000); + } else if (ddr_capability_per_die > 0x30000000) { + pdram_timing->trfc = + (LPDDR4_TRFC_6GBIT * nmhz + 999) / 1000; + tmp = (((LPDDR4_TRFC_6GBIT + 7) * nmhz + (nmhz >> 1) + + 999) / 1000); + } else { + pdram_timing->trfc = + (LPDDR4_TRFC_4GBIT * nmhz + 999) / 1000; + tmp = (((LPDDR4_TRFC_4GBIT + 7) * nmhz + (nmhz >> 1) + + 999) / 1000); + } + pdram_timing->txsr = max(2, tmp); + pdram_timing->txsnr = max(2, tmp); + /* tdqsck use rounded down */ + pdram_timing->tdqsck = ((LPDDR4_TDQSCK_MIN * nmhz + + (nmhz >> 1)) / 1000); + pdram_timing->tdqsck_max = ((LPDDR4_TDQSCK_MAX * nmhz + + (nmhz >> 1) + 999) / 1000); + pdram_timing->tppd = LPDDR4_TPPD; + /* pd and sr */ + tmp = ((LPDDR4_TXP * nmhz + (nmhz >> 1) + 999) / 1000); + pdram_timing->txp = max(5, tmp); + tmp = ((LPDDR4_TCKE * nmhz + (nmhz >> 1) + 999) / 1000); + pdram_timing->tcke = max(4, tmp); + tmp = ((LPDDR4_TESCKE * nmhz + + ((nmhz * 3) / 4) + + 999) / 1000); + pdram_timing->tescke = max(3, tmp); + tmp = ((LPDDR4_TSR * nmhz + 999) / 1000); + pdram_timing->tsr = max(3, tmp); + tmp = ((LPDDR4_TCMDCKE * nmhz + + ((nmhz * 3) / 4) + + 999) / 1000); + pdram_timing->tcmdcke = max(3, tmp); + pdram_timing->tcscke = ((LPDDR4_TCSCKE * nmhz + + ((nmhz * 3) / 4) + + 999) / 1000); + tmp = ((LPDDR4_TCKELCS * nmhz + 999) / 1000); + pdram_timing->tckelcs = max(5, tmp); + pdram_timing->tcsckeh = ((LPDDR4_TCSCKEH * nmhz + + ((nmhz * 3) / 4) + + 999) / 1000); + tmp = ((LPDDR4_TCKEHCS * nmhz + + (nmhz >> 1) + 999) / 1000); + pdram_timing->tckehcs = max(5, tmp); + tmp = ((LPDDR4_TMRWCKEL * nmhz + 999) / 1000); + pdram_timing->tmrwckel = max(10, tmp); + tmp = ((LPDDR4_TCKELCMD * nmhz + (nmhz >> 1) + + 999) / 1000); + pdram_timing->tckelcmd = max(3, tmp); + tmp = ((LPDDR4_TCKEHCMD * nmhz + (nmhz >> 1) + + 999) / 1000); + pdram_timing->tckehcmd = max(3, tmp); + tmp = ((LPDDR4_TCKELPD * nmhz + (nmhz >> 1) + + 999) / 1000); + pdram_timing->tckelpd = max(3, tmp); + tmp = ((LPDDR4_TCKCKEL * nmhz + (nmhz >> 1) + + 999) / 1000); + pdram_timing->tckckel = max(3, tmp); + /* mode register timing */ + tmp = ((LPDDR4_TMRD * nmhz + 999) / 1000); + pdram_timing->tmrd = max(10, tmp); + pdram_timing->tmrr = LPDDR4_TMRR; + pdram_timing->tmrri = pdram_timing->trcd + 3; + /* ODT */ + pdram_timing->todton = (LPDDR4_TODTON * nmhz + (nmhz >> 1) + 999) + / 1000; + /* ZQ */ + pdram_timing->tzqcal = (LPDDR4_TZQCAL * nmhz + 999) / 1000; + tmp = ((LPDDR4_TZQLAT * nmhz + 999) / 1000); + pdram_timing->tzqlat = max(8, tmp); + tmp = ((LPDDR4_TZQRESET * nmhz + 999) / 1000); + pdram_timing->tzqreset = max(3, tmp); + tmp = ((LPDDR4_TZQCKE * nmhz + + ((nmhz * 3) / 4) + + 999) / 1000); + pdram_timing->tzqcke = max(3, tmp); + /* write leveling */ + pdram_timing->twlmrd = LPDDR4_TWLMRD; + pdram_timing->twlo = (LPDDR4_TWLO * nmhz + 999) / 1000; + pdram_timing->twldqsen = LPDDR4_TWLDQSEN; + /* CA training */ + pdram_timing->tcaent = (LPDDR4_TCAENT * nmhz + 999) / 1000; + pdram_timing->tadr = (LPDDR4_TADR * nmhz + 999) / 1000; + pdram_timing->tmrz = (LPDDR4_TMRZ * nmhz + (nmhz >> 1) + 999) / 1000; + pdram_timing->tvref_long = (LPDDR4_TVREF_LONG * nmhz + 999) / 1000; + pdram_timing->tvref_short = (LPDDR4_TVREF_SHORT * nmhz + 999) / 1000; + /* VRCG */ + pdram_timing->tvrcg_enable = (LPDDR4_TVRCG_ENABLE * nmhz + + 999) / 1000; + pdram_timing->tvrcg_disable = (LPDDR4_TVRCG_DISABLE * nmhz + + 999) / 1000; + /* FSP */ + pdram_timing->tfc_long = (LPDDR4_TFC_LONG * nmhz + 999) / 1000; + tmp = (LPDDR4_TCKFSPE * nmhz + (nmhz >> 1) + 999) / 1000; + pdram_timing->tckfspe = max(4, tmp); + tmp = (LPDDR4_TCKFSPX * nmhz + (nmhz >> 1) + 999) / 1000; + pdram_timing->tckfspx = max(4, tmp); +} + +/* + * Description: depend on input parameter "timing_config", + * and calculate correspond "dram_type" + * spec timing to "pdram_timing" + * parameters: + * input: timing_config + * output: pdram_timing + * NOTE: MR ODT is set, need to disable by controller + */ +void dram_get_parameter(struct timing_related_config *timing_config, + struct dram_timing_t *pdram_timing) +{ + switch (timing_config->dram_type) { + case DDR3: + ddr3_get_parameter(timing_config, pdram_timing); + break; + case LPDDR2: + lpddr2_get_parameter(timing_config, pdram_timing); + break; + case LPDDR3: + lpddr3_get_parameter(timing_config, pdram_timing); + break; + case LPDDR4: + lpddr4_get_parameter(timing_config, pdram_timing); + break; + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h new file mode 100644 index 0000000..2008332 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dram_spec_timing.h @@ -0,0 +1,538 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _DRAM_SPEC_TIMING_HEAD_ +#define _DRAM_SPEC_TIMING_HEAD_ +#include + +enum { + DDR3 = 3, + LPDDR2 = 5, + LPDDR3 = 6, + LPDDR4 = 7, + UNUSED = 0xFF +}; + +enum ddr3_speed_rate { + /* 5-5-5 */ + DDR3_800D = 0, + /* 6-6-6 */ + DDR3_800E = 1, + /* 6-6-6 */ + DDR3_1066E = 2, + /* 7-7-7 */ + DDR3_1066F = 3, + /* 8-8-8 */ + DDR3_1066G = 4, + /* 7-7-7 */ + DDR3_1333F = 5, + /* 8-8-8 */ + DDR3_1333G = 6, + /* 9-9-9 */ + DDR3_1333H = 7, + /* 10-10-10 */ + DDR3_1333J = 8, + /* 8-8-8 */ + DDR3_1600G = 9, + /* 9-9-9 */ + DDR3_1600H = 10, + /* 10-10-10 */ + DDR3_1600J = 11, + /* 11-11-11 */ + DDR3_1600K = 12, + /* 10-10-10 */ + DDR3_1866J = 13, + /* 11-11-11 */ + DDR3_1866K = 14, + /* 12-12-12 */ + DDR3_1866L = 15, + /* 13-13-13 */ + DDR3_1866M = 16, + /* 11-11-11 */ + DDR3_2133K = 17, + /* 12-12-12 */ + DDR3_2133L = 18, + /* 13-13-13 */ + DDR3_2133M = 19, + /* 14-14-14 */ + DDR3_2133N = 20, + DDR3_DEFAULT = 21, +}; + +#define max(a, b) (((a) > (b)) ? (a) : (b)) +#define range(mi, val, ma) (((ma) > (val)) ? (max(mi, val)) : (ma)) + +struct dram_timing_t { + /* unit MHz */ + uint32_t mhz; + /* some timing unit is us */ + uint32_t tinit1; + uint32_t tinit2; + uint32_t tinit3; + uint32_t tinit4; + uint32_t tinit5; + /* reset low, DDR3:200us */ + uint32_t trstl; + /* reset high to CKE high, DDR3:500us */ + uint32_t trsth; + uint32_t trefi; + /* base */ + uint32_t trcd; + /* trp per bank */ + uint32_t trppb; + /* trp all bank */ + uint32_t trp; + uint32_t twr; + uint32_t tdal; + uint32_t trtp; + uint32_t trc; + uint32_t trrd; + uint32_t tccd; + uint32_t twtr; + uint32_t trtw; + uint32_t tras_max; + uint32_t tras_min; + uint32_t tfaw; + uint32_t trfc; + uint32_t tdqsck; + uint32_t tdqsck_max; + /* pd or sr */ + uint32_t txsr; + uint32_t txsnr; + uint32_t txp; + uint32_t txpdll; + uint32_t tdllk; + uint32_t tcke; + uint32_t tckesr; + uint32_t tcksre; + uint32_t tcksrx; + uint32_t tdpd; + /* mode regiter timing */ + uint32_t tmod; + uint32_t tmrd; + uint32_t tmrr; + uint32_t tmrri; + /* ODT */ + uint32_t todton; + /* ZQ */ + uint32_t tzqinit; + uint32_t tzqcs; + uint32_t tzqoper; + uint32_t tzqreset; + /* Write Leveling */ + uint32_t twlmrd; + uint32_t twlo; + uint32_t twldqsen; + /* CA Training */ + uint32_t tcackel; + uint32_t tcaent; + uint32_t tcamrd; + uint32_t tcackeh; + uint32_t tcaext; + uint32_t tadr; + uint32_t tmrz; + uint32_t tcacd; + /* mode register */ + uint32_t mr[4]; + uint32_t mr11; + /* lpddr4 spec */ + uint32_t mr12; + uint32_t mr13; + uint32_t mr14; + uint32_t mr16; + uint32_t mr17; + uint32_t mr20; + uint32_t mr22; + uint32_t tccdmw; + uint32_t tppd; + uint32_t tescke; + uint32_t tsr; + uint32_t tcmdcke; + uint32_t tcscke; + uint32_t tckelcs; + uint32_t tcsckeh; + uint32_t tckehcs; + uint32_t tmrwckel; + uint32_t tzqcal; + uint32_t tzqlat; + uint32_t tzqcke; + uint32_t tvref_long; + uint32_t tvref_short; + uint32_t tvrcg_enable; + uint32_t tvrcg_disable; + uint32_t tfc_long; + uint32_t tckfspe; + uint32_t tckfspx; + uint32_t tckehcmd; + uint32_t tckelcmd; + uint32_t tckelpd; + uint32_t tckckel; + /* other */ + uint32_t al; + uint32_t cl; + uint32_t cwl; + uint32_t bl; +}; + +struct dram_info_t { + /* speed_rate only used when DDR3 */ + enum ddr3_speed_rate speed_rate; + /* 1: use CS0, 2: use CS0 and CS1 */ + uint32_t cs_cnt; + /* give the max per-die capability on each rank/cs */ + uint32_t per_die_capability[2]; +}; + +struct timing_related_config { + struct dram_info_t dram_info[2]; + uint32_t dram_type; + /* MHz */ + uint32_t freq; + uint32_t ch_cnt; + uint32_t bl; + /* 1:auto precharge, 0:never auto precharge */ + uint32_t ap; + /* + * 1:dll bypass, 0:dll normal + * dram and controller dll bypass at the same time + */ + uint32_t dllbp; + /* 1:odt enable, 0:odt disable */ + uint32_t odt; + /* 1:enable, 0:disabe */ + uint32_t rdbi; + uint32_t wdbi; + /* dram driver strength */ + uint32_t dramds; + /* dram ODT, if odt=0, this parameter invalid */ + uint32_t dramodt; + /* + * ca ODT, if odt=0, this parameter invalid + * it only used by LPDDR4 + */ + uint32_t caodt; +}; + +/* mr0 for ddr3 */ +#define DDR3_BL8 (0) +#define DDR3_BC4_8 (1) +#define DDR3_BC4 (2) +#define DDR3_CL(n) (((((n) - 4) & 0x7) << 4)\ + | ((((n) - 4) & 0x8) >> 1)) +#define DDR3_WR(n) (((n) & 0x7) << 9) +#define DDR3_DLL_RESET (1 << 8) +#define DDR3_DLL_DERESET (0 << 8) + +/* mr1 for ddr3 */ +#define DDR3_DLL_ENABLE (0) +#define DDR3_DLL_DISABLE (1) +#define DDR3_MR1_AL(n) (((n) & 0x3) << 3) + +#define DDR3_DS_40 (0) +#define DDR3_DS_34 (1 << 1) +#define DDR3_RTT_NOM_DIS (0) +#define DDR3_RTT_NOM_60 (1 << 2) +#define DDR3_RTT_NOM_120 (1 << 6) +#define DDR3_RTT_NOM_40 ((1 << 2) | (1 << 6)) +#define DDR3_TDQS (1 << 11) + +/* mr2 for ddr3 */ +#define DDR3_MR2_CWL(n) ((((n) - 5) & 0x7) << 3) +#define DDR3_RTT_WR_DIS (0) +#define DDR3_RTT_WR_60 (1 << 9) +#define DDR3_RTT_WR_120 (2 << 9) + +/* + * MR0 (Device Information) + * 0:DAI complete, 1:DAI still in progress + */ +#define LPDDR2_DAI (0x1) +/* 0:S2 or S4 SDRAM, 1:NVM */ +#define LPDDR2_DI (0x1 << 1) +/* 0:DNV not supported, 1:DNV supported */ +#define LPDDR2_DNVI (0x1 << 2) +#define LPDDR2_RZQI (0x3 << 3) + +/* + * 00:RZQ self test not supported, + * 01:ZQ-pin may connect to VDDCA or float + * 10:ZQ-pin may short to GND. + * 11:ZQ-pin self test completed, no error condition detected. + */ + +/* MR1 (Device Feature) */ +#define LPDDR2_BL4 (0x2) +#define LPDDR2_BL8 (0x3) +#define LPDDR2_BL16 (0x4) +#define LPDDR2_N_WR(n) (((n) - 2) << 5) + +/* MR2 (Device Feature 2) */ +#define LPDDR2_RL3_WL1 (0x1) +#define LPDDR2_RL4_WL2 (0x2) +#define LPDDR2_RL5_WL2 (0x3) +#define LPDDR2_RL6_WL3 (0x4) +#define LPDDR2_RL7_WL4 (0x5) +#define LPDDR2_RL8_WL4 (0x6) + +/* MR3 (IO Configuration 1) */ +#define LPDDR2_DS_34 (0x1) +#define LPDDR2_DS_40 (0x2) +#define LPDDR2_DS_48 (0x3) +#define LPDDR2_DS_60 (0x4) +#define LPDDR2_DS_80 (0x6) +/* optional */ +#define LPDDR2_DS_120 (0x7) + +/* MR4 (Device Temperature) */ +#define LPDDR2_TREF_MASK (0x7) +#define LPDDR2_4_TREF (0x1) +#define LPDDR2_2_TREF (0x2) +#define LPDDR2_1_TREF (0x3) +#define LPDDR2_025_TREF (0x5) +#define LPDDR2_025_TREF_DERATE (0x6) + +#define LPDDR2_TUF (0x1 << 7) + +/* MR8 (Basic configuration 4) */ +#define LPDDR2_S4 (0x0) +#define LPDDR2_S2 (0x1) +#define LPDDR2_N (0x2) +/* Unit:MB */ +#define LPDDR2_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf)) +#define LPDDR2_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3)) + +/* MR10 (Calibration) */ +#define LPDDR2_ZQINIT (0xff) +#define LPDDR2_ZQCL (0xab) +#define LPDDR2_ZQCS (0x56) +#define LPDDR2_ZQRESET (0xc3) + +/* MR16 (PASR Bank Mask), S2 SDRAM Only */ +#define LPDDR2_PASR_FULL (0x0) +#define LPDDR2_PASR_1_2 (0x1) +#define LPDDR2_PASR_1_4 (0x2) +#define LPDDR2_PASR_1_8 (0x3) + +/* + * MR0 (Device Information) + * 0:DAI complete, + * 1:DAI still in progress + */ +#define LPDDR3_DAI (0x1) +/* + * 00:RZQ self test not supported, + * 01:ZQ-pin may connect to VDDCA or float + * 10:ZQ-pin may short to GND. + * 11:ZQ-pin self test completed, no error condition detected. + */ +#define LPDDR3_RZQI (0x3 << 3) +/* + * 0:DRAM does not support WL(Set B), + * 1:DRAM support WL(Set B) + */ +#define LPDDR3_WL_SUPOT (1 << 6) +/* + * 0:DRAM does not support RL=3,nWR=3,WL=1; + * 1:DRAM supports RL=3,nWR=3,WL=1 for frequencies <=166 + */ +#define LPDDR3_RL3_SUPOT (1 << 7) + +/* MR1 (Device Feature) */ +#define LPDDR3_BL8 (0x3) +#define LPDDR3_N_WR(n) ((n) << 5) + +/* MR2 (Device Feature 2), WL Set A,default */ +/* <=166MHz,optional*/ +#define LPDDR3_RL3_WL1 (0x1) +/* <=400MHz*/ +#define LPDDR3_RL6_WL3 (0x4) +/* <=533MHz*/ +#define LPDDR3_RL8_WL4 (0x6) +/* <=600MHz*/ +#define LPDDR3_RL9_WL5 (0x7) +/* <=667MHz,default*/ +#define LPDDR3_RL10_WL6 (0x8) +/* <=733MHz*/ +#define LPDDR3_RL11_WL6 (0x9) +/* <=800MHz*/ +#define LPDDR3_RL12_WL6 (0xa) +/* <=933MHz*/ +#define LPDDR3_RL14_WL8 (0xc) +/* <=1066MHz*/ +#define LPDDR3_RL16_WL8 (0xe) + +/* WL Set B, optional */ +/* <=667MHz,default*/ +#define LPDDR3_RL10_WL8 (0x8) +/* <=733MHz*/ +#define LPDDR3_RL11_WL9 (0x9) +/* <=800MHz*/ +#define LPDDR3_RL12_WL9 (0xa) +/* <=933MHz*/ +#define LPDDR3_RL14_WL11 (0xc) +/* <=1066MHz*/ +#define LPDDR3_RL16_WL13 (0xe) + +/* 1:enable nWR programming > 9(default)*/ +#define LPDDR3_N_WRE (1 << 4) +/* 1:Select WL Set B*/ +#define LPDDR3_WL_S (1 << 6) +/* 1:enable*/ +#define LPDDR3_WR_LEVEL (1 << 7) + +/* MR3 (IO Configuration 1) */ +#define LPDDR3_DS_34 (0x1) +#define LPDDR3_DS_40 (0x2) +#define LPDDR3_DS_48 (0x3) +#define LPDDR3_DS_60 (0x4) +#define LPDDR3_DS_80 (0x6) +#define LPDDR3_DS_34D_40U (0x9) +#define LPDDR3_DS_40D_48U (0xa) +#define LPDDR3_DS_34D_48U (0xb) + +/* MR4 (Device Temperature) */ +#define LPDDR3_TREF_MASK (0x7) +/* SDRAM Low temperature operating limit exceeded */ +#define LPDDR3_LT_EXED (0x0) +#define LPDDR3_4_TREF (0x1) +#define LPDDR3_2_TREF (0x2) +#define LPDDR3_1_TREF (0x3) +#define LPDDR3_05_TREF (0x4) +#define LPDDR3_025_TREF (0x5) +#define LPDDR3_025_TREF_DERATE (0x6) +/* SDRAM High temperature operating limit exceeded */ +#define LPDDR3_HT_EXED (0x7) + +/* 1:value has changed since last read of MR4 */ +#define LPDDR3_TUF (0x1 << 7) + +/* MR8 (Basic configuration 4) */ +#define LPDDR3_S8 (0x3) +#define LPDDR3_DENSITY(mr8) (8 << (((mr8) >> 2) & 0xf)) +#define LPDDR3_IO_WIDTH(mr8) (32 >> (((mr8) >> 6) & 0x3)) + +/* MR10 (Calibration) */ +#define LPDDR3_ZQINIT (0xff) +#define LPDDR3_ZQCL (0xab) +#define LPDDR3_ZQCS (0x56) +#define LPDDR3_ZQRESET (0xc3) + +/* MR11 (ODT Control) */ +#define LPDDR3_ODT_60 (1) +#define LPDDR3_ODT_120 (2) +#define LPDDR3_ODT_240 (3) +#define LPDDR3_ODT_DIS (0) + +/* MR2 (Device Feature 2) */ +/* RL & nRTP for DBI-RD Disabled */ +#define LPDDR4_RL6_NRTP8 (0x0) +#define LPDDR4_RL10_NRTP8 (0x1) +#define LPDDR4_RL14_NRTP8 (0x2) +#define LPDDR4_RL20_NRTP8 (0x3) +#define LPDDR4_RL24_NRTP10 (0x4) +#define LPDDR4_RL28_NRTP12 (0x5) +#define LPDDR4_RL32_NRTP14 (0x6) +#define LPDDR4_RL36_NRTP16 (0x7) +/* RL & nRTP for DBI-RD Disabled */ +#define LPDDR4_RL12_NRTP8 (0x1) +#define LPDDR4_RL16_NRTP8 (0x2) +#define LPDDR4_RL22_NRTP8 (0x3) +#define LPDDR4_RL28_NRTP10 (0x4) +#define LPDDR4_RL32_NRTP12 (0x5) +#define LPDDR4_RL36_NRTP14 (0x6) +#define LPDDR4_RL40_NRTP16 (0x7) +/* WL Set A,default */ +#define LPDDR4_A_WL4 (0x0) +#define LPDDR4_A_WL6 (0x1) +#define LPDDR4_A_WL8 (0x2) +#define LPDDR4_A_WL10 (0x3) +#define LPDDR4_A_WL12 (0x4) +#define LPDDR4_A_WL14 (0x5) +#define LPDDR4_A_WL16 (0x6) +#define LPDDR4_A_WL18 (0x7) +/* WL Set B, optional */ +#define LPDDR4_B_WL4 (0x0 << 3) +#define LPDDR4_B_WL8 (0x1 << 3) +#define LPDDR4_B_WL12 (0x2 << 3) +#define LPDDR4_B_WL18 (0x3 << 3) +#define LPDDR4_B_WL22 (0x4 << 3) +#define LPDDR4_B_WL26 (0x5 << 3) +#define LPDDR4_B_WL30 (0x6 << 3) +#define LPDDR4_B_WL34 (0x7 << 3) +/* 1:Select WL Set B*/ +#define LPDDR4_WL_B (1 << 6) +/* 1:enable*/ +#define LPDDR4_WR_LEVEL (1 << 7) + +/* MR3 */ +#define LPDDR4_VDDQ_2_5 (0) +#define LPDDR4_VDDQ_3 (1) +#define LPDDR4_WRPST_0_5_TCK (0 << 1) +#define LPDDR4_WRPST_1_5_TCK (1 << 1) +#define LPDDR4_PPR_EN (1 << 2) +/* PDDS */ +#define LPDDR4_PDDS_240 (0x1 << 3) +#define LPDDR4_PDDS_120 (0x2 << 3) +#define LPDDR4_PDDS_80 (0x3 << 3) +#define LPDDR4_PDDS_60 (0x4 << 3) +#define LPDDR4_PDDS_48 (0x5 << 3) +#define LPDDR4_PDDS_40 (0x6 << 3) +#define LPDDR4_DBI_RD_EN (1 << 6) +#define LPDDR4_DBI_WR_EN (1 << 7) + +/* MR11 (ODT Control) */ +#define LPDDR4_DQODT_240 (1) +#define LPDDR4_DQODT_120 (2) +#define LPDDR4_DQODT_80 (3) +#define LPDDR4_DQODT_60 (4) +#define LPDDR4_DQODT_48 (5) +#define LPDDR4_DQODT_40 (6) +#define LPDDR4_DQODT_DIS (0) +#define LPDDR4_CAODT_240 (1 << 4) +#define LPDDR4_CAODT_120 (2 << 4) +#define LPDDR4_CAODT_80 (3 << 4) +#define LPDDR4_CAODT_60 (4 << 4) +#define LPDDR4_CAODT_48 (5 << 4) +#define LPDDR4_CAODT_40 (6 << 4) +#define LPDDR4_CAODT_DIS (0 << 4) + +/* + * Description: depend on input parameter "timing_config", + * and calculate correspond "dram_type" + * spec timing to "pdram_timing" + * parameters: + * input: timing_config + * output: pdram_timing + * NOTE: MR ODT is set, need to disable by controller + */ +void dram_get_parameter(struct timing_related_config *timing_config, + struct dram_timing_t *pdram_timing); + +#endif /* _DRAM_SPEC_TIMING_HEAD_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c new file mode 100644 index 0000000..4995d56 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c @@ -0,0 +1,329 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +uint32_t gpio_port[] = { + GPIO0_BASE, + GPIO1_BASE, + GPIO2_BASE, + GPIO3_BASE, + GPIO4_BASE, +}; + +#define SWPORTA_DR 0x00 +#define SWPORTA_DDR 0x04 +#define EXT_PORTA 0x50 + +#define PMU_GPIO_PORT0 0 +#define PMU_GPIO_PORT1 1 +#define GPIO_PORT2 2 +#define GPIO_PORT3 3 +#define GPIO_PORT4 4 + +#define PMU_GRF_GPIO0A_P 0x40 +#define GRF_GPIO2A_P 0xe040 +#define GPIO_P_MASK 0x03 + +#define GET_GPIO_PORT(pin) (pin / 32) +#define GET_GPIO_NUM(pin) (pin % 32) +#define GET_GPIO_BANK(pin) ((pin % 32) / 8) +#define GET_GPIO_ID(pin) ((pin % 32) % 8) + +/* returns old clock state, enables clock, in order to do GPIO access */ +static int gpio_get_clock(uint32_t gpio_number) +{ + uint32_t port = GET_GPIO_PORT(gpio_number); + uint32_t clock_state = 0; + + assert(port < 5); + + switch (port) { + case PMU_GPIO_PORT0: + clock_state = (mmio_read_32(PMUCRU_BASE + + CRU_PMU_CLKGATE_CON(1)) >> + PCLK_GPIO0_GATE_SHIFT) & 0x01; + mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1), + BITS_WITH_WMASK(0, CLK_GATE_MASK, + PCLK_GPIO0_GATE_SHIFT)); + break; + case PMU_GPIO_PORT1: + clock_state = (mmio_read_32(PMUCRU_BASE + + CRU_PMU_CLKGATE_CON(1)) >> + PCLK_GPIO1_GATE_SHIFT) & 0x01; + mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1), + BITS_WITH_WMASK(0, CLK_GATE_MASK, + PCLK_GPIO1_GATE_SHIFT)); + break; + case GPIO_PORT2: + clock_state = (mmio_read_32(CRU_BASE + + CRU_CLKGATE_CON(31)) >> + PCLK_GPIO2_GATE_SHIFT) & 0x01; + mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), + BITS_WITH_WMASK(0, CLK_GATE_MASK, + PCLK_GPIO2_GATE_SHIFT)); + break; + case GPIO_PORT3: + clock_state = (mmio_read_32(CRU_BASE + + CRU_CLKGATE_CON(31)) >> + PCLK_GPIO3_GATE_SHIFT) & 0x01; + mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), + BITS_WITH_WMASK(0, CLK_GATE_MASK, + PCLK_GPIO3_GATE_SHIFT)); + break; + case GPIO_PORT4: + clock_state = (mmio_read_32(CRU_BASE + + CRU_CLKGATE_CON(31)) >> + PCLK_GPIO4_GATE_SHIFT) & 0x01; + mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), + BITS_WITH_WMASK(0, CLK_GATE_MASK, + PCLK_GPIO4_GATE_SHIFT)); + break; + default: + break; + } + + return clock_state; +} + +/* restores old state of gpio clock */ +void gpio_put_clock(uint32_t gpio_number, uint32_t clock_state) +{ + uint32_t port = GET_GPIO_PORT(gpio_number); + + switch (port) { + case PMU_GPIO_PORT0: + mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1), + BITS_WITH_WMASK(clock_state, CLK_GATE_MASK, + PCLK_GPIO0_GATE_SHIFT)); + break; + case PMU_GPIO_PORT1: + mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1), + BITS_WITH_WMASK(clock_state, CLK_GATE_MASK, + PCLK_GPIO1_GATE_SHIFT)); + break; + case GPIO_PORT2: + mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), + BITS_WITH_WMASK(clock_state, CLK_GATE_MASK, + PCLK_GPIO2_GATE_SHIFT)); + break; + case GPIO_PORT3: + mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), + BITS_WITH_WMASK(clock_state, CLK_GATE_MASK, + PCLK_GPIO3_GATE_SHIFT)); + + break; + case GPIO_PORT4: + mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), + BITS_WITH_WMASK(clock_state, CLK_GATE_MASK, + PCLK_GPIO4_GATE_SHIFT)); + break; + default: + break; + } +} + +static int get_pull(int gpio) +{ + uint32_t port = GET_GPIO_PORT(gpio); + uint32_t bank = GET_GPIO_BANK(gpio); + uint32_t id = GET_GPIO_ID(gpio); + uint32_t val, clock_state; + + assert((port < 5) && (bank < 4)); + + clock_state = gpio_get_clock(gpio); + + if (port == PMU_GPIO_PORT0 || port == PMU_GPIO_PORT1) { + val = mmio_read_32(PMUGRF_BASE + PMU_GRF_GPIO0A_P + + port * 16 + bank * 4); + val = (val >> (id * 2)) & GPIO_P_MASK; + } else { + val = mmio_read_32(GRF_BASE + GRF_GPIO2A_P + + (port - 2) * 16 + bank * 4); + val = (val >> (id * 2)) & GPIO_P_MASK; + } + gpio_put_clock(gpio, clock_state); + + /* + * in gpio0a, gpio0b, gpio2c, gpio2d, + * 00: Z + * 01: pull down + * 10: Z + * 11: pull up + * different with other gpio, so need to correct it + */ + if (((port == 0) && (bank < 2)) || ((port == 2) && (bank > 1))) { + if (val == 3) + val = GPIO_PULL_UP; + else if (val == 1) + val = GPIO_PULL_DOWN; + else + val = 0; + } + + return val; +} + +static void set_pull(int gpio, int pull) +{ + uint32_t port = GET_GPIO_PORT(gpio); + uint32_t bank = GET_GPIO_BANK(gpio); + uint32_t id = GET_GPIO_ID(gpio); + uint32_t clock_state; + + assert((port < 5) && (bank < 4)); + + clock_state = gpio_get_clock(gpio); + + /* + * in gpio0a, gpio0b, gpio2c, gpio2d, + * 00: Z + * 01: pull down + * 10: Z + * 11: pull up + * different with other gpio, so need to correct it + */ + if (((port == 0) && (bank < 2)) || ((port == 2) && (bank > 1))) { + if (pull == GPIO_PULL_UP) + pull = 3; + else if (pull == GPIO_PULL_DOWN) + pull = 1; + else + pull = 0; + } + + if (port == PMU_GPIO_PORT0 || port == PMU_GPIO_PORT1) { + mmio_write_32(PMUGRF_BASE + PMU_GRF_GPIO0A_P + + port * 16 + bank * 4, + BITS_WITH_WMASK(pull, GPIO_P_MASK, id * 2)); + } else { + mmio_write_32(GRF_BASE + GRF_GPIO2A_P + + (port - 2) * 16 + bank * 4, + BITS_WITH_WMASK(pull, GPIO_P_MASK, id * 2)); + } + gpio_put_clock(gpio, clock_state); +} + +static void set_direction(int gpio, int direction) +{ + uint32_t port = GET_GPIO_PORT(gpio); + uint32_t num = GET_GPIO_NUM(gpio); + uint32_t clock_state; + + assert((port < 5) && (num < 32)); + + clock_state = gpio_get_clock(gpio); + + /* + * in gpio.h + * #define GPIO_DIR_OUT 0 + * #define GPIO_DIR_IN 1 + * but rk3399 gpio direction 1: output, 0: input + * so need to revert direction value + */ + mmio_setbits_32(gpio_port[port] + SWPORTA_DDR, !direction << num); + gpio_put_clock(gpio, clock_state); +} + +static int get_direction(int gpio) +{ + uint32_t port = GET_GPIO_PORT(gpio); + uint32_t num = GET_GPIO_NUM(gpio); + int direction, clock_state; + + assert((port < 5) && (num < 32)); + + clock_state = gpio_get_clock(gpio); + + /* + * in gpio.h + * #define GPIO_DIR_OUT 0 + * #define GPIO_DIR_IN 1 + * but rk3399 gpio direction 1: output, 0: input + * so need to revert direction value + */ + direction = !((mmio_read_32(gpio_port[port] + + SWPORTA_DDR) >> num) & 0x1); + gpio_put_clock(gpio, clock_state); + + return direction; +} + +static int get_value(int gpio) +{ + uint32_t port = GET_GPIO_PORT(gpio); + uint32_t num = GET_GPIO_NUM(gpio); + int value, clock_state; + + assert((port < 5) && (num < 32)); + + clock_state = gpio_get_clock(gpio); + value = (mmio_read_32(gpio_port[port] + EXT_PORTA) >> num) & 0x1; + gpio_put_clock(gpio, clock_state); + + return value; +} + +static void set_value(int gpio, int value) +{ + uint32_t port = GET_GPIO_PORT(gpio); + uint32_t num = GET_GPIO_NUM(gpio); + uint32_t clock_state; + + assert((port < 5) && (num < 32)); + + clock_state = gpio_get_clock(gpio); + mmio_clrsetbits_32(gpio_port[port] + SWPORTA_DR, 1 << num, + !!value << num); + gpio_put_clock(gpio, clock_state); +} + +const gpio_ops_t rk3399_gpio_ops = { + .get_direction = get_direction, + .set_direction = set_direction, + .get_value = get_value, + .set_value = set_value, + .set_pull = set_pull, + .get_pull = get_pull, +}; + +void plat_rockchip_gpio_init(void) +{ + gpio_init(&rk3399_gpio_ops); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/plat_pmu_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/plat_pmu_macros.S new file mode 100644 index 0000000..7241964 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/plat_pmu_macros.S @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .globl clst_warmboot_data + +#define PLL_MODE_SHIFT (0x8) +#define PLL_NORMAL_MODE ((0x3 << (PLL_MODE_SHIFT + 16)) | \ + (0x1 << PLL_MODE_SHIFT)) +#define MPIDR_CLST_L_BITS 0x0 + /* + * For different socs, if we want to speed up warmboot, + * we need to config some regs here. + * If scu was suspend, we must resume related clk + * from slow (24M) mode to normal mode first. + * X0: MPIDR_EL1 & MPIDR_CLUSTER_MASK + */ +.macro func_rockchip_clst_warmboot + adr x4, clst_warmboot_data + lsr x5, x0, #6 + ldr w3, [x4, x5] + str wzr, [x4, x5] + cmp w3, #PMU_CLST_RET + b.ne clst_warmboot_end + ldr w6, =(PLL_NORMAL_MODE) + /* + * core_l offset is CRU_BASE + 0xc, + * core_b offset is CRU_BASE + 0x2c + */ + ldr x7, =(CRU_BASE + 0xc) + lsr x2, x0, #3 + str w6, [x7, x2] +clst_warmboot_end: +.endm + +.macro rockchip_clst_warmboot_data +clst_warmboot_data: + .rept PLATFORM_CLUSTER_COUNT + .word 0 + .endr +.endm diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c new file mode 100644 index 0000000..07a5b1e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.c @@ -0,0 +1,1332 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DEFINE_BAKERY_LOCK(rockchip_pd_lock); + +static struct psram_data_t *psram_sleep_cfg = + (struct psram_data_t *)PSRAM_DT_BASE; + +static uint32_t cpu_warm_boot_addr; + +/* + * There are two ways to powering on or off on core. + * 1) Control it power domain into on or off in PMU_PWRDN_CON reg, + * it is core_pwr_pd mode + * 2) Enable the core power manage in PMU_CORE_PM_CON reg, + * then, if the core enter into wfi, it power domain will be + * powered off automatically. it is core_pwr_wfi or core_pwr_wfi_int mode + * so we need core_pm_cfg_info to distinguish which method be used now. + */ + +static uint32_t core_pm_cfg_info[PLATFORM_CORE_COUNT] +#if USE_COHERENT_MEM +__attribute__ ((section("tzfw_coherent_mem"))) +#endif +;/* coheront */ + +static void pmu_bus_idle_req(uint32_t bus, uint32_t state) +{ + uint32_t bus_id = BIT(bus); + uint32_t bus_req; + uint32_t wait_cnt = 0; + uint32_t bus_state, bus_ack; + + if (state) + bus_req = BIT(bus); + else + bus_req = 0; + + mmio_clrsetbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, bus_id, bus_req); + + do { + bus_state = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & bus_id; + bus_ack = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK) & bus_id; + wait_cnt++; + } while ((bus_state != bus_req || bus_ack != bus_req) && + (wait_cnt < MAX_WAIT_COUNT)); + + if (bus_state != bus_req || bus_ack != bus_req) { + INFO("%s:st=%x(%x)\n", __func__, + mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST), + bus_state); + INFO("%s:st=%x(%x)\n", __func__, + mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK), + bus_ack); + } + +} + +struct pmu_slpdata_s pmu_slpdata; + +static void qos_save(void) +{ + if (pmu_power_domain_st(PD_GPU) == pmu_pd_on) + RESTORE_QOS(pmu_slpdata.gpu_qos, GPU); + if (pmu_power_domain_st(PD_ISP0) == pmu_pd_on) { + RESTORE_QOS(pmu_slpdata.isp0_m0_qos, ISP0_M0); + RESTORE_QOS(pmu_slpdata.isp0_m1_qos, ISP0_M1); + } + if (pmu_power_domain_st(PD_ISP1) == pmu_pd_on) { + RESTORE_QOS(pmu_slpdata.isp1_m0_qos, ISP1_M0); + RESTORE_QOS(pmu_slpdata.isp1_m1_qos, ISP1_M1); + } + if (pmu_power_domain_st(PD_VO) == pmu_pd_on) { + RESTORE_QOS(pmu_slpdata.vop_big_r, VOP_BIG_R); + RESTORE_QOS(pmu_slpdata.vop_big_w, VOP_BIG_W); + RESTORE_QOS(pmu_slpdata.vop_little, VOP_LITTLE); + } + if (pmu_power_domain_st(PD_HDCP) == pmu_pd_on) + RESTORE_QOS(pmu_slpdata.hdcp_qos, HDCP); + if (pmu_power_domain_st(PD_GMAC) == pmu_pd_on) + RESTORE_QOS(pmu_slpdata.gmac_qos, GMAC); + if (pmu_power_domain_st(PD_CCI) == pmu_pd_on) { + RESTORE_QOS(pmu_slpdata.cci_m0_qos, CCI_M0); + RESTORE_QOS(pmu_slpdata.cci_m1_qos, CCI_M1); + } + if (pmu_power_domain_st(PD_SD) == pmu_pd_on) + RESTORE_QOS(pmu_slpdata.sdmmc_qos, SDMMC); + if (pmu_power_domain_st(PD_EMMC) == pmu_pd_on) + RESTORE_QOS(pmu_slpdata.emmc_qos, EMMC); + if (pmu_power_domain_st(PD_SDIOAUDIO) == pmu_pd_on) + RESTORE_QOS(pmu_slpdata.sdio_qos, SDIO); + if (pmu_power_domain_st(PD_GIC) == pmu_pd_on) + RESTORE_QOS(pmu_slpdata.gic_qos, GIC); + if (pmu_power_domain_st(PD_RGA) == pmu_pd_on) { + RESTORE_QOS(pmu_slpdata.rga_r_qos, RGA_R); + RESTORE_QOS(pmu_slpdata.rga_w_qos, RGA_W); + } + if (pmu_power_domain_st(PD_IEP) == pmu_pd_on) + RESTORE_QOS(pmu_slpdata.iep_qos, IEP); + if (pmu_power_domain_st(PD_USB3) == pmu_pd_on) { + RESTORE_QOS(pmu_slpdata.usb_otg0_qos, USB_OTG0); + RESTORE_QOS(pmu_slpdata.usb_otg1_qos, USB_OTG1); + } + if (pmu_power_domain_st(PD_PERIHP) == pmu_pd_on) { + RESTORE_QOS(pmu_slpdata.usb_host0_qos, USB_HOST0); + RESTORE_QOS(pmu_slpdata.usb_host1_qos, USB_HOST1); + RESTORE_QOS(pmu_slpdata.perihp_nsp_qos, PERIHP_NSP); + } + if (pmu_power_domain_st(PD_PERILP) == pmu_pd_on) { + RESTORE_QOS(pmu_slpdata.dmac0_qos, DMAC0); + RESTORE_QOS(pmu_slpdata.dmac1_qos, DMAC1); + RESTORE_QOS(pmu_slpdata.dcf_qos, DCF); + RESTORE_QOS(pmu_slpdata.crypto0_qos, CRYPTO0); + RESTORE_QOS(pmu_slpdata.crypto1_qos, CRYPTO1); + RESTORE_QOS(pmu_slpdata.perilp_nsp_qos, PERILP_NSP); + RESTORE_QOS(pmu_slpdata.perilpslv_nsp_qos, PERILPSLV_NSP); + RESTORE_QOS(pmu_slpdata.peri_cm1_qos, PERI_CM1); + } + if (pmu_power_domain_st(PD_VDU) == pmu_pd_on) + RESTORE_QOS(pmu_slpdata.video_m0_qos, VIDEO_M0); + if (pmu_power_domain_st(PD_VCODEC) == pmu_pd_on) { + RESTORE_QOS(pmu_slpdata.video_m1_r_qos, VIDEO_M1_R); + RESTORE_QOS(pmu_slpdata.video_m1_w_qos, VIDEO_M1_W); + } +} + +static void qos_restore(void) +{ + if (pmu_power_domain_st(PD_GPU) == pmu_pd_on) + SAVE_QOS(pmu_slpdata.gpu_qos, GPU); + if (pmu_power_domain_st(PD_ISP0) == pmu_pd_on) { + SAVE_QOS(pmu_slpdata.isp0_m0_qos, ISP0_M0); + SAVE_QOS(pmu_slpdata.isp0_m1_qos, ISP0_M1); + } + if (pmu_power_domain_st(PD_ISP1) == pmu_pd_on) { + SAVE_QOS(pmu_slpdata.isp1_m0_qos, ISP1_M0); + SAVE_QOS(pmu_slpdata.isp1_m1_qos, ISP1_M1); + } + if (pmu_power_domain_st(PD_VO) == pmu_pd_on) { + SAVE_QOS(pmu_slpdata.vop_big_r, VOP_BIG_R); + SAVE_QOS(pmu_slpdata.vop_big_w, VOP_BIG_W); + SAVE_QOS(pmu_slpdata.vop_little, VOP_LITTLE); + } + if (pmu_power_domain_st(PD_HDCP) == pmu_pd_on) + SAVE_QOS(pmu_slpdata.hdcp_qos, HDCP); + if (pmu_power_domain_st(PD_GMAC) == pmu_pd_on) + SAVE_QOS(pmu_slpdata.gmac_qos, GMAC); + if (pmu_power_domain_st(PD_CCI) == pmu_pd_on) { + SAVE_QOS(pmu_slpdata.cci_m0_qos, CCI_M0); + SAVE_QOS(pmu_slpdata.cci_m1_qos, CCI_M1); + } + if (pmu_power_domain_st(PD_SD) == pmu_pd_on) + SAVE_QOS(pmu_slpdata.sdmmc_qos, SDMMC); + if (pmu_power_domain_st(PD_EMMC) == pmu_pd_on) + SAVE_QOS(pmu_slpdata.emmc_qos, EMMC); + if (pmu_power_domain_st(PD_SDIOAUDIO) == pmu_pd_on) + SAVE_QOS(pmu_slpdata.sdio_qos, SDIO); + if (pmu_power_domain_st(PD_GIC) == pmu_pd_on) + SAVE_QOS(pmu_slpdata.gic_qos, GIC); + if (pmu_power_domain_st(PD_RGA) == pmu_pd_on) { + SAVE_QOS(pmu_slpdata.rga_r_qos, RGA_R); + SAVE_QOS(pmu_slpdata.rga_w_qos, RGA_W); + } + if (pmu_power_domain_st(PD_IEP) == pmu_pd_on) + SAVE_QOS(pmu_slpdata.iep_qos, IEP); + if (pmu_power_domain_st(PD_USB3) == pmu_pd_on) { + SAVE_QOS(pmu_slpdata.usb_otg0_qos, USB_OTG0); + SAVE_QOS(pmu_slpdata.usb_otg1_qos, USB_OTG1); + } + if (pmu_power_domain_st(PD_PERIHP) == pmu_pd_on) { + SAVE_QOS(pmu_slpdata.usb_host0_qos, USB_HOST0); + SAVE_QOS(pmu_slpdata.usb_host1_qos, USB_HOST1); + SAVE_QOS(pmu_slpdata.perihp_nsp_qos, PERIHP_NSP); + } + if (pmu_power_domain_st(PD_PERILP) == pmu_pd_on) { + SAVE_QOS(pmu_slpdata.dmac0_qos, DMAC0); + SAVE_QOS(pmu_slpdata.dmac1_qos, DMAC1); + SAVE_QOS(pmu_slpdata.dcf_qos, DCF); + SAVE_QOS(pmu_slpdata.crypto0_qos, CRYPTO0); + SAVE_QOS(pmu_slpdata.crypto1_qos, CRYPTO1); + SAVE_QOS(pmu_slpdata.perilp_nsp_qos, PERILP_NSP); + SAVE_QOS(pmu_slpdata.perilpslv_nsp_qos, PERILPSLV_NSP); + SAVE_QOS(pmu_slpdata.peri_cm1_qos, PERI_CM1); + } + if (pmu_power_domain_st(PD_VDU) == pmu_pd_on) + SAVE_QOS(pmu_slpdata.video_m0_qos, VIDEO_M0); + if (pmu_power_domain_st(PD_VCODEC) == pmu_pd_on) { + SAVE_QOS(pmu_slpdata.video_m1_r_qos, VIDEO_M1_R); + SAVE_QOS(pmu_slpdata.video_m1_w_qos, VIDEO_M1_W); + } +} + +static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state) +{ + uint32_t state; + + if (pmu_power_domain_st(pd_id) == pd_state) + goto out; + + if (pd_state == pmu_pd_on) + pmu_power_domain_ctr(pd_id, pd_state); + + state = (pd_state == pmu_pd_off) ? BUS_IDLE : BUS_ACTIVE; + + switch (pd_id) { + case PD_GPU: + pmu_bus_idle_req(BUS_ID_GPU, state); + break; + case PD_VIO: + pmu_bus_idle_req(BUS_ID_VIO, state); + break; + case PD_ISP0: + pmu_bus_idle_req(BUS_ID_ISP0, state); + break; + case PD_ISP1: + pmu_bus_idle_req(BUS_ID_ISP1, state); + break; + case PD_VO: + pmu_bus_idle_req(BUS_ID_VOPB, state); + pmu_bus_idle_req(BUS_ID_VOPL, state); + break; + case PD_HDCP: + pmu_bus_idle_req(BUS_ID_HDCP, state); + break; + case PD_TCPD0: + break; + case PD_TCPD1: + break; + case PD_GMAC: + pmu_bus_idle_req(BUS_ID_GMAC, state); + break; + case PD_CCI: + pmu_bus_idle_req(BUS_ID_CCIM0, state); + pmu_bus_idle_req(BUS_ID_CCIM1, state); + break; + case PD_SD: + pmu_bus_idle_req(BUS_ID_SD, state); + break; + case PD_EMMC: + pmu_bus_idle_req(BUS_ID_EMMC, state); + break; + case PD_EDP: + pmu_bus_idle_req(BUS_ID_EDP, state); + break; + case PD_SDIOAUDIO: + pmu_bus_idle_req(BUS_ID_SDIOAUDIO, state); + break; + case PD_GIC: + pmu_bus_idle_req(BUS_ID_GIC, state); + break; + case PD_RGA: + pmu_bus_idle_req(BUS_ID_RGA, state); + break; + case PD_VCODEC: + pmu_bus_idle_req(BUS_ID_VCODEC, state); + break; + case PD_VDU: + pmu_bus_idle_req(BUS_ID_VDU, state); + break; + case PD_IEP: + pmu_bus_idle_req(BUS_ID_IEP, state); + break; + case PD_USB3: + pmu_bus_idle_req(BUS_ID_USB3, state); + break; + case PD_PERIHP: + pmu_bus_idle_req(BUS_ID_PERIHP, state); + break; + default: + break; + } + + if (pd_state == pmu_pd_off) + pmu_power_domain_ctr(pd_id, pd_state); + +out: + return 0; +} + +static uint32_t pmu_powerdomain_state; + +static void pmu_power_domains_suspend(void) +{ + clk_gate_con_save(); + clk_gate_con_disable(); + qos_save(); + pmu_powerdomain_state = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); + pmu_set_power_domain(PD_GPU, pmu_pd_off); + pmu_set_power_domain(PD_TCPD0, pmu_pd_off); + pmu_set_power_domain(PD_TCPD1, pmu_pd_off); + pmu_set_power_domain(PD_VO, pmu_pd_off); + pmu_set_power_domain(PD_ISP0, pmu_pd_off); + pmu_set_power_domain(PD_ISP1, pmu_pd_off); + pmu_set_power_domain(PD_HDCP, pmu_pd_off); + pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_off); + pmu_set_power_domain(PD_GMAC, pmu_pd_off); + pmu_set_power_domain(PD_EDP, pmu_pd_off); + pmu_set_power_domain(PD_IEP, pmu_pd_off); + pmu_set_power_domain(PD_RGA, pmu_pd_off); + pmu_set_power_domain(PD_VCODEC, pmu_pd_off); + pmu_set_power_domain(PD_VDU, pmu_pd_off); + clk_gate_con_restore(); +} + +static void pmu_power_domains_resume(void) +{ + clk_gate_con_save(); + clk_gate_con_disable(); + if (!(pmu_powerdomain_state & BIT(PD_VDU))) + pmu_set_power_domain(PD_VDU, pmu_pd_on); + if (!(pmu_powerdomain_state & BIT(PD_VCODEC))) + pmu_set_power_domain(PD_VCODEC, pmu_pd_on); + if (!(pmu_powerdomain_state & BIT(PD_RGA))) + pmu_set_power_domain(PD_RGA, pmu_pd_on); + if (!(pmu_powerdomain_state & BIT(PD_IEP))) + pmu_set_power_domain(PD_IEP, pmu_pd_on); + if (!(pmu_powerdomain_state & BIT(PD_EDP))) + pmu_set_power_domain(PD_EDP, pmu_pd_on); + if (!(pmu_powerdomain_state & BIT(PD_GMAC))) + pmu_set_power_domain(PD_GMAC, pmu_pd_on); + if (!(pmu_powerdomain_state & BIT(PD_SDIOAUDIO))) + pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_on); + if (!(pmu_powerdomain_state & BIT(PD_HDCP))) + pmu_set_power_domain(PD_HDCP, pmu_pd_on); + if (!(pmu_powerdomain_state & BIT(PD_ISP1))) + pmu_set_power_domain(PD_ISP1, pmu_pd_on); + if (!(pmu_powerdomain_state & BIT(PD_ISP0))) + pmu_set_power_domain(PD_ISP0, pmu_pd_on); + if (!(pmu_powerdomain_state & BIT(PD_VO))) + pmu_set_power_domain(PD_VO, pmu_pd_on); + if (!(pmu_powerdomain_state & BIT(PD_TCPD1))) + pmu_set_power_domain(PD_TCPD1, pmu_pd_on); + if (!(pmu_powerdomain_state & BIT(PD_TCPD0))) + pmu_set_power_domain(PD_TCPD0, pmu_pd_on); + if (!(pmu_powerdomain_state & BIT(PD_GPU))) + pmu_set_power_domain(PD_GPU, pmu_pd_on); + qos_restore(); + clk_gate_con_restore(); +} + +void rk3399_flash_l2_b(void) +{ + uint32_t wait_cnt = 0; + + mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); + dsb(); + + while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & + BIT(L2_FLUSHDONE_CLUSTER_B))) { + wait_cnt++; + if (wait_cnt >= MAX_WAIT_COUNT) + WARN("%s:reg %x,wait\n", __func__, + mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); + } + + mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); +} + +static void pmu_scu_b_pwrdn(void) +{ + uint32_t wait_cnt = 0; + + if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & + (BIT(PMU_A72_B0_PWRDWN_ST) | BIT(PMU_A72_B1_PWRDWN_ST))) != + (BIT(PMU_A72_B0_PWRDWN_ST) | BIT(PMU_A72_B1_PWRDWN_ST))) { + ERROR("%s: not all cpus is off\n", __func__); + return; + } + + rk3399_flash_l2_b(); + + mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG)); + + while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & + BIT(STANDBY_BY_WFIL2_CLUSTER_B))) { + wait_cnt++; + if (wait_cnt >= MAX_WAIT_COUNT) + ERROR("%s:wait cluster-b l2(%x)\n", __func__, + mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); + } +} + +static void pmu_scu_b_pwrup(void) +{ + mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG)); +} + +void plat_rockchip_pmusram_prepare(void) +{ + uint32_t *sram_dst, *sram_src; + size_t sram_size = 2; + + /* + * pmu sram code and data prepare + */ + sram_dst = (uint32_t *)PMUSRAM_BASE; + sram_src = (uint32_t *)&pmu_cpuson_entrypoint_start; + sram_size = (uint32_t *)&pmu_cpuson_entrypoint_end - + (uint32_t *)sram_src; + + u32_align_cpy(sram_dst, sram_src, sram_size); + + psram_sleep_cfg->sp = PSRAM_DT_BASE; +} + +static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id) +{ + assert(cpu_id < PLATFORM_CORE_COUNT); + return core_pm_cfg_info[cpu_id]; +} + +static inline void set_cpus_pwr_domain_cfg_info(uint32_t cpu_id, uint32_t value) +{ + assert(cpu_id < PLATFORM_CORE_COUNT); + core_pm_cfg_info[cpu_id] = value; +#if !USE_COHERENT_MEM + flush_dcache_range((uintptr_t)&core_pm_cfg_info[cpu_id], + sizeof(uint32_t)); +#endif +} + +static int cpus_power_domain_on(uint32_t cpu_id) +{ + uint32_t cfg_info; + uint32_t cpu_pd = PD_CPUL0 + cpu_id; + /* + * There are two ways to powering on or off on core. + * 1) Control it power domain into on or off in PMU_PWRDN_CON reg + * 2) Enable the core power manage in PMU_CORE_PM_CON reg, + * then, if the core enter into wfi, it power domain will be + * powered off automatically. + */ + + cfg_info = get_cpus_pwr_domain_cfg_info(cpu_id); + + if (cfg_info == core_pwr_pd) { + /* disable core_pm cfg */ + mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), + CORES_PM_DISABLE); + /* if the cores have be on, power off it firstly */ + if (pmu_power_domain_st(cpu_pd) == pmu_pd_on) { + mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 0); + pmu_power_domain_ctr(cpu_pd, pmu_pd_off); + } + + pmu_power_domain_ctr(cpu_pd, pmu_pd_on); + } else { + if (pmu_power_domain_st(cpu_pd) == pmu_pd_on) { + WARN("%s: cpu%d is not in off,!\n", __func__, cpu_id); + return -EINVAL; + } + + mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), + BIT(core_pm_sft_wakeup_en)); + dsb(); + } + + return 0; +} + +static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg) +{ + uint32_t cpu_pd; + uint32_t core_pm_value; + + cpu_pd = PD_CPUL0 + cpu_id; + if (pmu_power_domain_st(cpu_pd) == pmu_pd_off) + return 0; + + if (pd_cfg == core_pwr_pd) { + if (check_cpu_wfie(cpu_id, CKECK_WFEI_MSK)) + return -EINVAL; + + /* disable core_pm cfg */ + mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), + CORES_PM_DISABLE); + + set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg); + pmu_power_domain_ctr(cpu_pd, pmu_pd_off); + } else { + set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg); + + core_pm_value = BIT(core_pm_en); + if (pd_cfg == core_pwr_wfi_int) + core_pm_value |= BIT(core_pm_int_wakeup_en); + mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), + core_pm_value); + dsb(); + } + + return 0; +} + +static inline void clst_pwr_domain_suspend(plat_local_state_t lvl_state) +{ + uint32_t cpu_id = plat_my_core_pos(); + uint32_t pll_id, clst_st_msk, clst_st_chk_msk, pmu_st; + + assert(cpu_id < PLATFORM_CORE_COUNT); + + if (lvl_state == PLAT_MAX_OFF_STATE) { + if (cpu_id < PLATFORM_CLUSTER0_CORE_COUNT) { + pll_id = ALPLL_ID; + clst_st_msk = CLST_L_CPUS_MSK; + } else { + pll_id = ABPLL_ID; + clst_st_msk = CLST_B_CPUS_MSK << + PLATFORM_CLUSTER0_CORE_COUNT; + } + + clst_st_chk_msk = clst_st_msk & ~(BIT(cpu_id)); + + pmu_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); + + pmu_st &= clst_st_msk; + + if (pmu_st == clst_st_chk_msk) { + mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), + PLL_SLOW_MODE); + + clst_warmboot_data[pll_id] = PMU_CLST_RET; + + pmu_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); + pmu_st &= clst_st_msk; + if (pmu_st == clst_st_chk_msk) + return; + /* + * it is mean that others cpu is up again, + * we must resume the cfg at once. + */ + mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), + PLL_NOMAL_MODE); + clst_warmboot_data[pll_id] = 0; + } + } +} + +static int clst_pwr_domain_resume(plat_local_state_t lvl_state) +{ + uint32_t cpu_id = plat_my_core_pos(); + uint32_t pll_id, pll_st; + + assert(cpu_id < PLATFORM_CORE_COUNT); + + if (lvl_state == PLAT_MAX_OFF_STATE) { + if (cpu_id < PLATFORM_CLUSTER0_CORE_COUNT) + pll_id = ALPLL_ID; + else + pll_id = ABPLL_ID; + + pll_st = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 3)) >> + PLL_MODE_SHIFT; + + if (pll_st != NORMAL_MODE) { + WARN("%s: clst (%d) is in error mode (%d)\n", + __func__, pll_id, pll_st); + return -1; + } + } + + return 0; +} + +static void nonboot_cpus_off(void) +{ + uint32_t boot_cpu, cpu; + + boot_cpu = plat_my_core_pos(); + + /* turn off noboot cpus */ + for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) { + if (cpu == boot_cpu) + continue; + cpus_power_domain_off(cpu, core_pwr_pd); + } +} + +static int cores_pwr_domain_on(unsigned long mpidr, uint64_t entrypoint) +{ + uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr); + + assert(cpu_id < PLATFORM_CORE_COUNT); + assert(cpuson_flags[cpu_id] == 0); + cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG; + cpuson_entry_point[cpu_id] = entrypoint; + dsb(); + + cpus_power_domain_on(cpu_id); + + return 0; +} + +static int cores_pwr_domain_off(void) +{ + uint32_t cpu_id = plat_my_core_pos(); + + cpus_power_domain_off(cpu_id, core_pwr_wfi); + + return 0; +} + +static int hlvl_pwr_domain_off(uint32_t lvl, plat_local_state_t lvl_state) +{ + switch (lvl) { + case MPIDR_AFFLVL1: + clst_pwr_domain_suspend(lvl_state); + break; + default: + break; + } + + return 0; +} + +static int cores_pwr_domain_suspend(void) +{ + uint32_t cpu_id = plat_my_core_pos(); + + assert(cpu_id < PLATFORM_CORE_COUNT); + assert(cpuson_flags[cpu_id] == 0); + cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN; + cpuson_entry_point[cpu_id] = plat_get_sec_entrypoint(); + dsb(); + + cpus_power_domain_off(cpu_id, core_pwr_wfi_int); + + return 0; +} + +static int hlvl_pwr_domain_suspend(uint32_t lvl, plat_local_state_t lvl_state) +{ + switch (lvl) { + case MPIDR_AFFLVL1: + clst_pwr_domain_suspend(lvl_state); + break; + default: + break; + } + + return 0; +} + +static int cores_pwr_domain_on_finish(void) +{ + uint32_t cpu_id = plat_my_core_pos(); + + mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), + CORES_PM_DISABLE); + return 0; +} + +static int hlvl_pwr_domain_on_finish(uint32_t lvl, + plat_local_state_t lvl_state) +{ + switch (lvl) { + case MPIDR_AFFLVL1: + clst_pwr_domain_resume(lvl_state); + break; + default: + break; + } + + return 0; +} + +static int cores_pwr_domain_resume(void) +{ + uint32_t cpu_id = plat_my_core_pos(); + + /* Disable core_pm */ + mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE); + + return 0; +} + +static int hlvl_pwr_domain_resume(uint32_t lvl, plat_local_state_t lvl_state) +{ + switch (lvl) { + case MPIDR_AFFLVL1: + clst_pwr_domain_resume(lvl_state); + default: + break; + } + + return 0; +} + +/** + * init_pmu_counts - Init timing counts in the PMU register area + * + * At various points when we power up or down parts of the system we need + * a delay to wait for power / clocks to become stable. The PMU has counters + * to help software do the delay properly. Basically, it works like this: + * - Software sets up counter values + * - When software turns on something in the PMU, the counter kicks off + * - The hardware sets a bit automatically when the counter has finished and + * software knows that the initialization is done. + * + * It's software's job to setup these counters. The hardware power on default + * for these settings is conservative, setting everything to 0x5dc0 + * (750 ms in 32 kHz counts or 1 ms in 24 MHz counts). + * + * Note that some of these counters are only really used at suspend/resume + * time (for instance, that's the only time we turn off/on the oscillator) and + * others are used during normal runtime (like turning on/off a CPU or GPU) but + * it doesn't hurt to init everything at boot. + * + * Also note that these counters can run off the 32 kHz clock or the 24 MHz + * clock. While the 24 MHz clock can give us more precision, it's not always + * available (like when we turn the oscillator off at sleep time). The + * pmu_use_lf (lf: low freq) is available in power mode. Current understanding + * is that counts work like this: + * IF (pmu_use_lf == 0) || (power_mode_en == 0) + * use the 24M OSC for counts + * ELSE + * use the 32K OSC for counts + * + * Notes: + * - There is a separate bit for the PMU called PMU_24M_EN_CFG. At the moment + * we always keep that 0. This apparently choose between using the PLL as + * the source for the PMU vs. the 24M clock. If we ever set it to 1 we + * should consider how it affects these counts (if at all). + * - The power_mode_en is documented to auto-clear automatically when we leave + * "power mode". That's why most clocks are on 24M. Only timings used when + * in "power mode" are 32k. + * - In some cases the kernel may override these counts. + * + * The PMU_STABLE_CNT / PMU_OSC_CNT / PMU_PLLLOCK_CNT are important CNTs + * in power mode, we need to ensure that they are available. + */ +static void init_pmu_counts(void) +{ + /* COUNTS FOR INSIDE POWER MODE */ + + /* + * From limited testing, need PMU stable >= 2ms, but go overkill + * and choose 30 ms to match testing on past SoCs. Also let + * OSC have 30 ms for stabilization. + */ + mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_32K_CNT_MS(30)); + mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_32K_CNT_MS(30)); + + /* Unclear what these should be; try 3 ms */ + mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_32K_CNT_MS(3)); + + /* Unclear what this should be, but set the default explicitly */ + mmio_write_32(PMU_BASE + PMU_TIMEOUT_CNT, 0x5dc0); + + /* COUNTS FOR OUTSIDE POWER MODE */ + + /* Put something sorta conservative here until we know better */ + mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_24M_CNT_MS(3)); + mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_24M_CNT_MS(1)); + mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_24M_CNT_MS(1)); + mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_24M_CNT_MS(1)); + + /* + * Set CPU/GPU to 1 us. + * + * NOTE: Even though ATF doesn't configure the GPU we'll still setup + * counts here. After all ATF controls all these other bits and also + * chooses which clock these counters use. + */ + mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_24M_CNT_US(1)); + mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_24M_CNT_US(1)); + mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_24M_CNT_US(1)); + mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_24M_CNT_US(1)); + mmio_write_32(PMU_BASE + PMU_GPU_PWRDN_CNT, CYCL_24M_CNT_US(1)); + mmio_write_32(PMU_BASE + PMU_GPU_PWRUP_CNT, CYCL_24M_CNT_US(1)); +} + +static void sys_slp_config(void) +{ + uint32_t slp_mode_cfg = 0; + + mmio_write_32(GRF_BASE + GRF_SOC_CON4, CCI_FORCE_WAKEUP); + mmio_write_32(PMU_BASE + PMU_CCI500_CON, + BIT_WITH_WMSK(PMU_CLR_PREQ_CCI500_HW) | + BIT_WITH_WMSK(PMU_CLR_QREQ_CCI500_HW) | + BIT_WITH_WMSK(PMU_QGATING_CCI500_CFG)); + + mmio_write_32(PMU_BASE + PMU_ADB400_CON, + BIT_WITH_WMSK(PMU_CLR_CORE_L_HW) | + BIT_WITH_WMSK(PMU_CLR_CORE_L_2GIC_HW) | + BIT_WITH_WMSK(PMU_CLR_GIC2_CORE_L_HW)); + + slp_mode_cfg = BIT(PMU_PWR_MODE_EN) | + BIT(PMU_POWER_OFF_REQ_CFG) | + BIT(PMU_CPU0_PD_EN) | + BIT(PMU_L2_FLUSH_EN) | + BIT(PMU_L2_IDLE_EN) | + BIT(PMU_SCU_PD_EN) | + BIT(PMU_CCI_PD_EN) | + BIT(PMU_CLK_CORE_SRC_GATE_EN) | + BIT(PMU_PERILP_PD_EN) | + BIT(PMU_CLK_PERILP_SRC_GATE_EN) | + BIT(PMU_ALIVE_USE_LF) | + BIT(PMU_SREF0_ENTER_EN) | + BIT(PMU_SREF1_ENTER_EN) | + BIT(PMU_DDRC0_GATING_EN) | + BIT(PMU_DDRC1_GATING_EN) | + BIT(PMU_DDRIO0_RET_EN) | + BIT(PMU_DDRIO1_RET_EN) | + BIT(PMU_DDRIO_RET_HW_DE_REQ) | + BIT(PMU_PLL_PD_EN) | + BIT(PMU_CLK_CENTER_SRC_GATE_EN) | + BIT(PMU_OSC_DIS) | + BIT(PMU_PMU_USE_LF); + + mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, BIT(PMU_GPIO_WKUP_EN)); + mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, slp_mode_cfg); + + + mmio_write_32(PMU_BASE + PMU_PLL_CON, PLL_PD_HW); + mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON0, EXTERNAL_32K); + mmio_write_32(PMUGRF_BASE, IOMUX_CLK_32K); /* 32k iomux */ +} + +static void set_hw_idle(uint32_t hw_idle) +{ + mmio_setbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle); +} + +static void clr_hw_idle(uint32_t hw_idle) +{ + mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle); +} + +static uint32_t iomux_status[12]; +static uint32_t pull_mode_status[12]; +static uint32_t gpio_direction[3]; +static uint32_t gpio_2_4_clk_gate; + +static void suspend_apio(void) +{ + struct apio_info *suspend_apio; + int i; + + suspend_apio = plat_get_rockchip_suspend_apio(); + + if (!suspend_apio) + return; + + /* save gpio2 ~ gpio4 iomux and pull mode */ + for (i = 0; i < 12; i++) { + iomux_status[i] = mmio_read_32(GRF_BASE + + GRF_GPIO2A_IOMUX + i * 4); + pull_mode_status[i] = mmio_read_32(GRF_BASE + + GRF_GPIO2A_P + i * 4); + } + + /* store gpio2 ~ gpio4 clock gate state */ + gpio_2_4_clk_gate = (mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)) >> + PCLK_GPIO2_GATE_SHIFT) & 0x07; + + /* enable gpio2 ~ gpio4 clock gate */ + mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), + BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT)); + + /* save gpio2 ~ gpio4 direction */ + gpio_direction[0] = mmio_read_32(GPIO2_BASE + 0x04); + gpio_direction[1] = mmio_read_32(GPIO3_BASE + 0x04); + gpio_direction[2] = mmio_read_32(GPIO4_BASE + 0x04); + + /* apio1 charge gpio3a0 ~ gpio3c7 */ + if (suspend_apio->apio1) { + + /* set gpio3a0 ~ gpio3c7 iomux to gpio */ + mmio_write_32(GRF_BASE + GRF_GPIO3A_IOMUX, + REG_SOC_WMSK | GRF_IOMUX_GPIO); + mmio_write_32(GRF_BASE + GRF_GPIO3B_IOMUX, + REG_SOC_WMSK | GRF_IOMUX_GPIO); + mmio_write_32(GRF_BASE + GRF_GPIO3C_IOMUX, + REG_SOC_WMSK | GRF_IOMUX_GPIO); + + /* set gpio3a0 ~ gpio3c7 pull mode to pull none */ + mmio_write_32(GRF_BASE + GRF_GPIO3A_P, REG_SOC_WMSK | 0); + mmio_write_32(GRF_BASE + GRF_GPIO3B_P, REG_SOC_WMSK | 0); + mmio_write_32(GRF_BASE + GRF_GPIO3C_P, REG_SOC_WMSK | 0); + + /* set gpio3a0 ~ gpio3c7 to input */ + mmio_clrbits_32(GPIO3_BASE + 0x04, 0x00ffffff); + } + + /* apio2 charge gpio2a0 ~ gpio2b4 */ + if (suspend_apio->apio2) { + + /* set gpio2a0 ~ gpio2b4 iomux to gpio */ + mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX, + REG_SOC_WMSK | GRF_IOMUX_GPIO); + mmio_write_32(GRF_BASE + GRF_GPIO2B_IOMUX, + REG_SOC_WMSK | GRF_IOMUX_GPIO); + + /* set gpio2a0 ~ gpio2b4 pull mode to pull none */ + mmio_write_32(GRF_BASE + GRF_GPIO2A_P, REG_SOC_WMSK | 0); + mmio_write_32(GRF_BASE + GRF_GPIO2B_P, REG_SOC_WMSK | 0); + + /* set gpio2a0 ~ gpio2b4 to input */ + mmio_clrbits_32(GPIO2_BASE + 0x04, 0x00001fff); + } + + /* apio3 charge gpio2c0 ~ gpio2d4*/ + if (suspend_apio->apio3) { + + /* set gpio2a0 ~ gpio2b4 iomux to gpio */ + mmio_write_32(GRF_BASE + GRF_GPIO2C_IOMUX, + REG_SOC_WMSK | GRF_IOMUX_GPIO); + mmio_write_32(GRF_BASE + GRF_GPIO2D_IOMUX, + REG_SOC_WMSK | GRF_IOMUX_GPIO); + + /* set gpio2c0 ~ gpio2d4 pull mode to pull none */ + mmio_write_32(GRF_BASE + GRF_GPIO2C_P, REG_SOC_WMSK | 0); + mmio_write_32(GRF_BASE + GRF_GPIO2D_P, REG_SOC_WMSK | 0); + + /* set gpio2c0 ~ gpio2d4 to input */ + mmio_clrbits_32(GPIO2_BASE + 0x04, 0x1fff0000); + } + + /* apio4 charge gpio4c0 ~ gpio4c7, gpio4d0 ~ gpio4d6 */ + if (suspend_apio->apio4) { + + /* set gpio4c0 ~ gpio4d6 iomux to gpio */ + mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, + REG_SOC_WMSK | GRF_IOMUX_GPIO); + mmio_write_32(GRF_BASE + GRF_GPIO4D_IOMUX, + REG_SOC_WMSK | GRF_IOMUX_GPIO); + + /* set gpio4c0 ~ gpio4d6 pull mode to pull none */ + mmio_write_32(GRF_BASE + GRF_GPIO4C_P, REG_SOC_WMSK | 0); + mmio_write_32(GRF_BASE + GRF_GPIO4D_P, REG_SOC_WMSK | 0); + + /* set gpio4c0 ~ gpio4d6 to input */ + mmio_clrbits_32(GPIO4_BASE + 0x04, 0x7fff0000); + } + + /* apio5 charge gpio3d0 ~ gpio3d7, gpio4a0 ~ gpio4a7*/ + if (suspend_apio->apio5) { + /* set gpio3d0 ~ gpio4a7 iomux to gpio */ + mmio_write_32(GRF_BASE + GRF_GPIO3D_IOMUX, + REG_SOC_WMSK | GRF_IOMUX_GPIO); + mmio_write_32(GRF_BASE + GRF_GPIO4A_IOMUX, + REG_SOC_WMSK | GRF_IOMUX_GPIO); + + /* set gpio3d0 ~ gpio4a7 pull mode to pull none */ + mmio_write_32(GRF_BASE + GRF_GPIO3D_P, REG_SOC_WMSK | 0); + mmio_write_32(GRF_BASE + GRF_GPIO4A_P, REG_SOC_WMSK | 0); + + /* set gpio4c0 ~ gpio4d6 to input */ + mmio_clrbits_32(GPIO3_BASE + 0x04, 0xff000000); + mmio_clrbits_32(GPIO4_BASE + 0x04, 0x000000ff); + } +} + +static void resume_apio(void) +{ + struct apio_info *suspend_apio; + int i; + + suspend_apio = plat_get_rockchip_suspend_apio(); + + if (!suspend_apio) + return; + + for (i = 0; i < 12; i++) { + mmio_write_32(GRF_BASE + GRF_GPIO2A_P + i * 4, + REG_SOC_WMSK | pull_mode_status[i]); + mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4, + REG_SOC_WMSK | iomux_status[i]); + } + + /* set gpio2 ~ gpio4 direction back to store value */ + mmio_write_32(GPIO2_BASE + 0x04, gpio_direction[0]); + mmio_write_32(GPIO3_BASE + 0x04, gpio_direction[1]); + mmio_write_32(GPIO4_BASE + 0x04, gpio_direction[2]); + + /* set gpio2 ~ gpio4 clock gate back to store value */ + mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), + BITS_WITH_WMASK(gpio_2_4_clk_gate, 0x07, + PCLK_GPIO2_GATE_SHIFT)); +} + +static void suspend_gpio(void) +{ + struct gpio_info *suspend_gpio; + uint32_t count; + int i; + + suspend_gpio = plat_get_rockchip_suspend_gpio(&count); + + for (i = 0; i < count; i++) { + gpio_set_value(suspend_gpio[i].index, suspend_gpio[i].polarity); + gpio_set_direction(suspend_gpio[i].index, GPIO_DIR_OUT); + udelay(1); + } +} + +static void resume_gpio(void) +{ + struct gpio_info *suspend_gpio; + uint32_t count; + int i; + + suspend_gpio = plat_get_rockchip_suspend_gpio(&count); + + for (i = count - 1; i >= 0; i--) { + gpio_set_value(suspend_gpio[i].index, + !suspend_gpio[i].polarity); + gpio_set_direction(suspend_gpio[i].index, GPIO_DIR_OUT); + udelay(1); + } +} + +static int sys_pwr_domain_suspend(void) +{ + uint32_t wait_cnt = 0; + uint32_t status = 0; + + pmu_power_domains_suspend(); + set_hw_idle(BIT(PMU_CLR_CENTER1) | + BIT(PMU_CLR_ALIVE) | + BIT(PMU_CLR_MSCH0) | + BIT(PMU_CLR_MSCH1) | + BIT(PMU_CLR_CCIM0) | + BIT(PMU_CLR_CCIM1) | + BIT(PMU_CLR_CENTER) | + BIT(PMU_CLR_PERILP) | + BIT(PMU_CLR_PMU) | + BIT(PMU_CLR_PERILPM0) | + BIT(PMU_CLR_GIC)); + + sys_slp_config(); + pmu_sgrf_rst_hld(); + + mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1), + (PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) | + CPU_BOOT_ADDR_WMASK); + + pmu_scu_b_pwrdn(); + + mmio_write_32(PMU_BASE + PMU_ADB400_CON, + BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) | + BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_SW) | + BIT_WITH_WMSK(PMU_PWRDWN_REQ_GIC2_CORE_B_SW)); + dsb(); + status = BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST) | + BIT(PMU_PWRDWN_REQ_CORE_B_SW_ST) | + BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST); + while ((mmio_read_32(PMU_BASE + + PMU_ADB400_ST) & status) != status) { + wait_cnt++; + if (wait_cnt >= MAX_WAIT_COUNT) { + ERROR("%s:wait cluster-b l2(%x)\n", __func__, + mmio_read_32(PMU_BASE + PMU_ADB400_ST)); + panic(); + } + } + mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN)); + /* + * Disabling PLLs/PWM/DVFS is approaching WFI which is + * the last steps in suspend. + */ + plls_suspend_prepare(); + disable_dvfs_plls(); + disable_pwms(); + disable_nodvfs_plls(); + suspend_apio(); + suspend_gpio(); + + return 0; +} + +static int sys_pwr_domain_resume(void) +{ + uint32_t wait_cnt = 0; + uint32_t status = 0; + + resume_apio(); + resume_gpio(); + enable_nodvfs_plls(); + enable_pwms(); + /* PWM regulators take time to come up; give 300us to be safe. */ + udelay(300); + enable_dvfs_plls(); + plls_resume_finish(); + + /* + * The wakeup status is not cleared by itself, we need to clear it + * manually. Otherwise we will alway query some interrupt next time. + * + * NOTE: If the kernel needs to query this, we might want to stash it + * somewhere. + */ + mmio_write_32(PMU_BASE + PMU_WAKEUP_STATUS, 0xffffffff); + mmio_write_32(PMU_BASE + PMU_WKUP_CFG4, 0x00); + + mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1), + (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | + CPU_BOOT_ADDR_WMASK); + + mmio_write_32(PMU_BASE + PMU_CCI500_CON, + WMSK_BIT(PMU_CLR_PREQ_CCI500_HW) | + WMSK_BIT(PMU_CLR_QREQ_CCI500_HW) | + WMSK_BIT(PMU_QGATING_CCI500_CFG)); + dsb(); + mmio_clrbits_32(PMU_BASE + PMU_PWRDN_CON, + BIT(PMU_SCU_B_PWRDWN_EN)); + + mmio_write_32(PMU_BASE + PMU_ADB400_CON, + WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) | + WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_SW) | + WMSK_BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW) | + WMSK_BIT(PMU_CLR_CORE_L_HW) | + WMSK_BIT(PMU_CLR_CORE_L_2GIC_HW) | + WMSK_BIT(PMU_CLR_GIC2_CORE_L_HW)); + + status = BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST) | + BIT(PMU_PWRDWN_REQ_CORE_B_SW_ST) | + BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST); + + while ((mmio_read_32(PMU_BASE + + PMU_ADB400_ST) & status)) { + wait_cnt++; + if (wait_cnt >= MAX_WAIT_COUNT) { + ERROR("%s:wait cluster-b l2(%x)\n", __func__, + mmio_read_32(PMU_BASE + PMU_ADB400_ST)); + panic(); + } + } + + pmu_sgrf_rst_hld_release(); + pmu_scu_b_pwrup(); + + pmu_power_domains_resume(); + clr_hw_idle(BIT(PMU_CLR_CENTER1) | + BIT(PMU_CLR_ALIVE) | + BIT(PMU_CLR_MSCH0) | + BIT(PMU_CLR_MSCH1) | + BIT(PMU_CLR_CCIM0) | + BIT(PMU_CLR_CCIM1) | + BIT(PMU_CLR_CENTER) | + BIT(PMU_CLR_PERILP) | + BIT(PMU_CLR_PMU) | + BIT(PMU_CLR_GIC)); + + plat_rockchip_gic_cpuif_enable(); + + return 0; +} + +void __dead2 soc_soft_reset(void) +{ + struct gpio_info *rst_gpio; + + rst_gpio = plat_get_rockchip_gpio_reset(); + + if (rst_gpio) { + gpio_set_direction(rst_gpio->index, GPIO_DIR_OUT); + gpio_set_value(rst_gpio->index, rst_gpio->polarity); + } else { + soc_global_soft_reset(); + } + + while (1) + ; +} + +void __dead2 soc_system_off(void) +{ + struct gpio_info *poweroff_gpio; + + poweroff_gpio = plat_get_rockchip_gpio_poweroff(); + + if (poweroff_gpio) { + /* + * if use tsadc over temp pin(GPIO1A6) as shutdown gpio, + * need to set this pin iomux back to gpio function + */ + if (poweroff_gpio->index == TSADC_INT_PIN) { + mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX, + GPIO1A6_IOMUX); + } + gpio_set_direction(poweroff_gpio->index, GPIO_DIR_OUT); + gpio_set_value(poweroff_gpio->index, poweroff_gpio->polarity); + } else { + WARN("Do nothing when system off\n"); + } + + while (1) + ; +} +static void __dead2 sys_pwr_down_wfi(const psci_power_state_t *target_state) +{ + uint32_t wakeup_status; + + /* + * Check wakeup status and abort suspend early if we see a wakeup + * event. + * + * NOTE: technically I we're supposed to just execute a wfi here and + * we'll either execute a normal suspend/resume or the wfi will be + * treated as a no-op if a wake event was present and caused an abort + * of the suspend/resume. For some reason that's not happening and if + * we execute the wfi while a wake event is pending then the whole + * system wedges. + * + * Until the above is solved this extra check prevents system wedges in + * most cases but there is still a small race condition between checking + * PMU_WAKEUP_STATUS and executing wfi. If a wake event happens in + * there then we will die. + */ + wakeup_status = mmio_read_32(PMU_BASE + PMU_WAKEUP_STATUS); + if (wakeup_status) { + WARN("early wake, will not enter power mode.\n"); + + mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, 0); + + disable_mmu_icache_el3(); + bl31_warm_entrypoint(); + + while (1) + ; + } else { + /* Enter WFI */ + psci_power_down_wfi(); + } +} + +static struct rockchip_pm_ops_cb pm_ops = { + .cores_pwr_dm_on = cores_pwr_domain_on, + .cores_pwr_dm_off = cores_pwr_domain_off, + .cores_pwr_dm_on_finish = cores_pwr_domain_on_finish, + .cores_pwr_dm_suspend = cores_pwr_domain_suspend, + .cores_pwr_dm_resume = cores_pwr_domain_resume, + .hlvl_pwr_dm_suspend = hlvl_pwr_domain_suspend, + .hlvl_pwr_dm_resume = hlvl_pwr_domain_resume, + .hlvl_pwr_dm_off = hlvl_pwr_domain_off, + .hlvl_pwr_dm_on_finish = hlvl_pwr_domain_on_finish, + .sys_pwr_dm_suspend = sys_pwr_domain_suspend, + .sys_pwr_dm_resume = sys_pwr_domain_resume, + .sys_gbl_soft_reset = soc_soft_reset, + .system_off = soc_system_off, + .sys_pwr_down_wfi = sys_pwr_down_wfi, +}; + +void plat_rockchip_pmu_init(void) +{ + uint32_t cpu; + + rockchip_pd_lock_init(); + plat_setup_rockchip_pm_ops(&pm_ops); + + /* register requires 32bits mode, switch it to 32 bits */ + cpu_warm_boot_addr = (uint64_t)platform_cpu_warmboot; + + for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) + cpuson_flags[cpu] = 0; + + for (cpu = 0; cpu < PLATFORM_CLUSTER_COUNT; cpu++) + clst_warmboot_data[cpu] = 0; + + psram_sleep_cfg->ddr_func = 0x00; + psram_sleep_cfg->ddr_data = 0x00; + psram_sleep_cfg->ddr_flag = 0x00; + psram_sleep_cfg->boot_mpidr = read_mpidr_el1() & 0xffff; + + /* config cpu's warm boot address */ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1), + (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) | + CPU_BOOT_ADDR_WMASK); + mmio_write_32(PMU_BASE + PMU_NOC_AUTO_ENA, NOC_AUTO_ENABLE); + + /* + * Enable Schmitt trigger for better 32 kHz input signal, which is + * important for suspend/resume reliability among other things. + */ + mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_SMT, GPIO0A0_SMT_ENABLE); + + init_pmu_counts(); + + nonboot_cpus_off(); + + INFO("%s(%d): pd status %x\n", __func__, __LINE__, + mmio_read_32(PMU_BASE + PMU_PWRDN_ST)); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.h new file mode 100644 index 0000000..ab2896b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/pmu.h @@ -0,0 +1,980 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PMU_H__ +#define __PMU_H__ + +/* Allocate sp reginon in pmusram */ +#define PSRAM_SP_SIZE 0x80 +#define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE) + +/***************************************************************************** + * Common define for per soc pmu.h + *****************************************************************************/ +/* The ways of cores power domain contorlling */ +enum cores_pm_ctr_mode { + core_pwr_pd = 0, + core_pwr_wfi = 1, + core_pwr_wfi_int = 2 +}; + +/***************************************************************************** + * pmu con,reg + *****************************************************************************/ +#define PMU_WKUP_CFG(n) ((n) * 4) + +#define PMU_CORE_PM_CON(cpu) (0xc0 + (cpu * 4)) + +/* the shift of bits for cores status */ +enum pmu_core_pwrst_shift { + clstl_cpu_wfe = 2, + clstl_cpu_wfi = 6, + clstb_cpu_wfe = 12, + clstb_cpu_wfi = 16 +}; + +#define CKECK_WFE_MSK 0x1 +#define CKECK_WFI_MSK 0x10 +#define CKECK_WFEI_MSK 0x11 + +enum pmu_powerdomain_id { + PD_CPUL0 = 0, + PD_CPUL1, + PD_CPUL2, + PD_CPUL3, + PD_CPUB0, + PD_CPUB1, + PD_SCUL, + PD_SCUB, + PD_TCPD0, + PD_TCPD1, + PD_CCI, + PD_PERILP, + PD_PERIHP, + PD_CENTER, + PD_VIO, + PD_GPU, + PD_VCODEC, + PD_VDU, + PD_RGA, + PD_IEP, + PD_VO, + PD_ISP0 = 22, + PD_ISP1, + PD_HDCP, + PD_GMAC, + PD_EMMC, + PD_USB3, + PD_EDP, + PD_GIC, + PD_SD, + PD_SDIOAUDIO, + PD_END +}; + +enum powerdomain_state { + PMU_POWER_ON = 0, + PMU_POWER_OFF, +}; + +enum pmu_bus_id { + BUS_ID_GPU = 0, + BUS_ID_PERILP, + BUS_ID_PERIHP, + BUS_ID_VCODEC, + BUS_ID_VDU, + BUS_ID_RGA, + BUS_ID_IEP, + BUS_ID_VOPB, + BUS_ID_VOPL, + BUS_ID_ISP0, + BUS_ID_ISP1, + BUS_ID_HDCP, + BUS_ID_USB3, + BUS_ID_PERILPM0, + BUS_ID_CENTER, + BUS_ID_CCIM0, + BUS_ID_CCIM1, + BUS_ID_VIO, + BUS_ID_MSCH0, + BUS_ID_MSCH1, + BUS_ID_ALIVE, + BUS_ID_PMU, + BUS_ID_EDP, + BUS_ID_GMAC, + BUS_ID_EMMC, + BUS_ID_CENTER1, + BUS_ID_PMUM0, + BUS_ID_GIC, + BUS_ID_SD, + BUS_ID_SDIOAUDIO, +}; + +enum pmu_bus_state { + BUS_ACTIVE, + BUS_IDLE, +}; + +/* pmu_cpuapm bit */ +enum pmu_cores_pm_by_wfi { + core_pm_en = 0, + core_pm_int_wakeup_en, + core_pm_resv, + core_pm_sft_wakeup_en +}; + +enum pmu_wkup_cfg0 { + PMU_GPIO0A_POSE_WKUP_EN = 0, + PMU_GPIO0B_POSE_WKUP_EN = 8, + PMU_GPIO0C_POSE_WKUP_EN = 16, + PMU_GPIO0D_POSE_WKUP_EN = 24, +}; + +enum pmu_wkup_cfg1 { + PMU_GPIO0A_NEGEDGE_WKUP_EN = 0, + PMU_GPIO0B_NEGEDGE_WKUP_EN = 7, + PMU_GPIO0C_NEGEDGE_WKUP_EN = 16, + PMU_GPIO0D_NEGEDGE_WKUP_EN = 24, +}; + +enum pmu_wkup_cfg2 { + PMU_GPIO1A_POSE_WKUP_EN = 0, + PMU_GPIO1B_POSE_WKUP_EN = 7, + PMU_GPIO1C_POSE_WKUP_EN = 16, + PMU_GPIO1D_POSE_WKUP_EN = 24, +}; + +enum pmu_wkup_cfg3 { + PMU_GPIO1A_NEGEDGE_WKUP_EN = 0, + PMU_GPIO1B_NEGEDGE_WKUP_EN = 7, + PMU_GPIO1C_NEGEDGE_WKUP_EN = 16, + PMU_GPIO1D_NEGEDGE_WKUP_EN = 24, +}; + +/* pmu_wkup_cfg4 */ +enum pmu_wkup_cfg4 { + PMU_CLUSTER_L_WKUP_EN = 0, + PMU_CLUSTER_B_WKUP_EN, + PMU_GPIO_WKUP_EN, + PMU_SDIO_WKUP_EN, + + PMU_SDMMC_WKUP_EN, + PMU_TIMER_WKUP_EN = 6, + PMU_USBDEV_WKUP_EN, + + PMU_SFT_WKUP_EN, + PMU_M0_WDT_WKUP_EN, + PMU_TIMEOUT_WKUP_EN, + PMU_PWM_WKUP_EN, + + PMU_PCIE_WKUP_EN = 13, +}; + +enum pmu_pwrdn_con { + PMU_A53_L0_PWRDWN_EN = 0, + PMU_A53_L1_PWRDWN_EN, + PMU_A53_L2_PWRDWN_EN, + PMU_A53_L3_PWRDWN_EN, + + PMU_A72_B0_PWRDWN_EN, + PMU_A72_B1_PWRDWN_EN, + PMU_SCU_L_PWRDWN_EN, + PMU_SCU_B_PWRDWN_EN, + + PMU_TCPD0_PWRDWN_EN, + PMU_TCPD1_PWRDWN_EN, + PMU_CCI_PWRDWN_EN, + PMU_PERILP_PWRDWN_EN, + + PMU_PERIHP_PWRDWN_EN, + PMU_CENTER_PWRDWN_EN, + PMU_VIO_PWRDWN_EN, + PMU_GPU_PWRDWN_EN, + + PMU_VCODEC_PWRDWN_EN, + PMU_VDU_PWRDWN_EN, + PMU_RGA_PWRDWN_EN, + PMU_IEP_PWRDWN_EN, + + PMU_VO_PWRDWN_EN, + PMU_ISP0_PWRDWN_EN = 22, + PMU_ISP1_PWRDWN_EN, + + PMU_HDCP_PWRDWN_EN, + PMU_GMAC_PWRDWN_EN, + PMU_EMMC_PWRDWN_EN, + PMU_USB3_PWRDWN_EN, + + PMU_EDP_PWRDWN_EN, + PMU_GIC_PWRDWN_EN, + PMU_SD_PWRDWN_EN, + PMU_SDIOAUDIO_PWRDWN_EN, +}; + +enum pmu_pwrdn_st { + PMU_A53_L0_PWRDWN_ST = 0, + PMU_A53_L1_PWRDWN_ST, + PMU_A53_L2_PWRDWN_ST, + PMU_A53_L3_PWRDWN_ST, + + PMU_A72_B0_PWRDWN_ST, + PMU_A72_B1_PWRDWN_ST, + PMU_SCU_L_PWRDWN_ST, + PMU_SCU_B_PWRDWN_ST, + + PMU_TCPD0_PWRDWN_ST, + PMU_TCPD1_PWRDWN_ST, + PMU_CCI_PWRDWN_ST, + PMU_PERILP_PWRDWN_ST, + + PMU_PERIHP_PWRDWN_ST, + PMU_CENTER_PWRDWN_ST, + PMU_VIO_PWRDWN_ST, + PMU_GPU_PWRDWN_ST, + + PMU_VCODEC_PWRDWN_ST, + PMU_VDU_PWRDWN_ST, + PMU_RGA_PWRDWN_ST, + PMU_IEP_PWRDWN_ST, + + PMU_VO_PWRDWN_ST, + PMU_ISP0_PWRDWN_ST = 22, + PMU_ISP1_PWRDWN_ST, + + PMU_HDCP_PWRDWN_ST, + PMU_GMAC_PWRDWN_ST, + PMU_EMMC_PWRDWN_ST, + PMU_USB3_PWRDWN_ST, + + PMU_EDP_PWRDWN_ST, + PMU_GIC_PWRDWN_ST, + PMU_SD_PWRDWN_ST, + PMU_SDIOAUDIO_PWRDWN_ST, + +}; + +enum pmu_pll_con { + PMU_PLL_PD_CFG = 0, + PMU_SFT_PLL_PD = 8, +}; + +enum pmu_pwermode_con { + PMU_PWR_MODE_EN = 0, + PMU_WKUP_RST_EN, + PMU_INPUT_CLAMP_EN, + PMU_OSC_DIS, + + PMU_ALIVE_USE_LF, + PMU_PMU_USE_LF, + PMU_POWER_OFF_REQ_CFG, + PMU_CHIP_PD_EN, + + PMU_PLL_PD_EN, + PMU_CPU0_PD_EN, + PMU_L2_FLUSH_EN, + PMU_L2_IDLE_EN, + + PMU_SCU_PD_EN, + PMU_CCI_PD_EN, + PMU_PERILP_PD_EN, + PMU_CENTER_PD_EN, + + PMU_SREF0_ENTER_EN, + PMU_DDRC0_GATING_EN, + PMU_DDRIO0_RET_EN, + PMU_DDRIO0_RET_DE_REQ, + + PMU_SREF1_ENTER_EN, + PMU_DDRC1_GATING_EN, + PMU_DDRIO1_RET_EN, + PMU_DDRIO1_RET_DE_REQ, + + PMU_CLK_CENTER_SRC_GATE_EN = 26, + PMU_CLK_PERILP_SRC_GATE_EN, + + PMU_CLK_CORE_SRC_GATE_EN, + PMU_DDRIO_RET_HW_DE_REQ, + PMU_SLP_OUTPUT_CFG, + PMU_MAIN_CLUSTER, +}; + +enum pmu_sft_con { + PMU_WKUP_SFT = 0, + PMU_INPUT_CLAMP_CFG, + PMU_OSC_DIS_CFG, + PMU_PMU_LF_EN_CFG, + + PMU_ALIVE_LF_EN_CFG, + PMU_24M_EN_CFG, + PMU_DBG_PWRUP_L0_CFG, + PMU_WKUP_SFT_M0, + + PMU_DDRCTL0_C_SYSREQ_CFG, + PMU_DDR0_IO_RET_CFG, + + PMU_DDRCTL1_C_SYSREQ_CFG = 12, + PMU_DDR1_IO_RET_CFG, + DBG_PWRUP_B0_CFG = 15, + + DBG_NOPWERDWN_L0_EN, + DBG_NOPWERDWN_L1_EN, + DBG_NOPWERDWN_L2_EN, + DBG_NOPWERDWN_L3_EN, + + DBG_PWRUP_REQ_L_EN = 20, + CLUSTER_L_CLK_SRC_GATING_CFG, + L2_FLUSH_REQ_CLUSTER_L, + ACINACTM_CLUSTER_L_CFG, + + DBG_NO_PWERDWN_B0_EN, + DBG_NO_PWERDWN_B1_EN, + + DBG_PWRUP_REQ_B_EN = 28, + CLUSTER_B_CLK_SRC_GATING_CFG, + L2_FLUSH_REQ_CLUSTER_B, + ACINACTM_CLUSTER_B_CFG, +}; + +enum pmu_int_con { + PMU_PMU_INT_EN = 0, + PMU_PWRMD_WKUP_INT_EN, + PMU_WKUP_GPIO0_NEG_INT_EN, + PMU_WKUP_GPIO0_POS_INT_EN, + PMU_WKUP_GPIO1_NEG_INT_EN, + PMU_WKUP_GPIO1_POS_INT_EN, +}; + +enum pmu_int_st { + PMU_PWRMD_WKUP_INT_ST = 1, + PMU_WKUP_GPIO0_NEG_INT_ST, + PMU_WKUP_GPIO0_POS_INT_ST, + PMU_WKUP_GPIO1_NEG_INT_ST, + PMU_WKUP_GPIO1_POS_INT_ST, +}; + +enum pmu_gpio0_pos_int_con { + PMU_GPIO0A_POS_INT_EN = 0, + PMU_GPIO0B_POS_INT_EN = 8, + PMU_GPIO0C_POS_INT_EN = 16, + PMU_GPIO0D_POS_INT_EN = 24, +}; + +enum pmu_gpio0_neg_int_con { + PMU_GPIO0A_NEG_INT_EN = 0, + PMU_GPIO0B_NEG_INT_EN = 8, + PMU_GPIO0C_NEG_INT_EN = 16, + PMU_GPIO0D_NEG_INT_EN = 24, +}; + +enum pmu_gpio1_pos_int_con { + PMU_GPIO1A_POS_INT_EN = 0, + PMU_GPIO1B_POS_INT_EN = 8, + PMU_GPIO1C_POS_INT_EN = 16, + PMU_GPIO1D_POS_INT_EN = 24, +}; + +enum pmu_gpio1_neg_int_con { + PMU_GPIO1A_NEG_INT_EN = 0, + PMU_GPIO1B_NEG_INT_EN = 8, + PMU_GPIO1C_NEG_INT_EN = 16, + PMU_GPIO1D_NEG_INT_EN = 24, +}; + +enum pmu_gpio0_pos_int_st { + PMU_GPIO0A_POS_INT_ST = 0, + PMU_GPIO0B_POS_INT_ST = 8, + PMU_GPIO0C_POS_INT_ST = 16, + PMU_GPIO0D_POS_INT_ST = 24, +}; + +enum pmu_gpio0_neg_int_st { + PMU_GPIO0A_NEG_INT_ST = 0, + PMU_GPIO0B_NEG_INT_ST = 8, + PMU_GPIO0C_NEG_INT_ST = 16, + PMU_GPIO0D_NEG_INT_ST = 24, +}; + +enum pmu_gpio1_pos_int_st { + PMU_GPIO1A_POS_INT_ST = 0, + PMU_GPIO1B_POS_INT_ST = 8, + PMU_GPIO1C_POS_INT_ST = 16, + PMU_GPIO1D_POS_INT_ST = 24, +}; + +enum pmu_gpio1_neg_int_st { + PMU_GPIO1A_NEG_INT_ST = 0, + PMU_GPIO1B_NEG_INT_ST = 8, + PMU_GPIO1C_NEG_INT_ST = 16, + PMU_GPIO1D_NEG_INT_ST = 24, +}; + +/* pmu power down configure register 0x0050 */ +enum pmu_pwrdn_inten { + PMU_A53_L0_PWR_SWITCH_INT_EN = 0, + PMU_A53_L1_PWR_SWITCH_INT_EN, + PMU_A53_L2_PWR_SWITCH_INT_EN, + PMU_A53_L3_PWR_SWITCH_INT_EN, + + PMU_A72_B0_PWR_SWITCH_INT_EN, + PMU_A72_B1_PWR_SWITCH_INT_EN, + PMU_SCU_L_PWR_SWITCH_INT_EN, + PMU_SCU_B_PWR_SWITCH_INT_EN, + + PMU_TCPD0_PWR_SWITCH_INT_EN, + PMU_TCPD1_PWR_SWITCH_INT_EN, + PMU_CCI_PWR_SWITCH_INT_EN, + PMU_PERILP_PWR_SWITCH_INT_EN, + + PMU_PERIHP_PWR_SWITCH_INT_EN, + PMU_CENTER_PWR_SWITCH_INT_EN, + PMU_VIO_PWR_SWITCH_INT_EN, + PMU_GPU_PWR_SWITCH_INT_EN, + + PMU_VCODEC_PWR_SWITCH_INT_EN, + PMU_VDU_PWR_SWITCH_INT_EN, + PMU_RGA_PWR_SWITCH_INT_EN, + PMU_IEP_PWR_SWITCH_INT_EN, + + PMU_VO_PWR_SWITCH_INT_EN, + PMU_ISP0_PWR_SWITCH_INT_EN = 22, + PMU_ISP1_PWR_SWITCH_INT_EN, + + PMU_HDCP_PWR_SWITCH_INT_EN, + PMU_GMAC_PWR_SWITCH_INT_EN, + PMU_EMMC_PWR_SWITCH_INT_EN, + PMU_USB3_PWR_SWITCH_INT_EN, + + PMU_EDP_PWR_SWITCH_INT_EN, + PMU_GIC_PWR_SWITCH_INT_EN, + PMU_SD_PWR_SWITCH_INT_EN, + PMU_SDIOAUDIO_PWR_SWITCH_INT_EN, +}; + +enum pmu_wkup_status { + PMU_WKUP_BY_CLSTER_L_INT = 0, + PMU_WKUP_BY_CLSTER_b_INT, + PMU_WKUP_BY_GPIO_INT, + PMU_WKUP_BY_SDIO_DET, + + PMU_WKUP_BY_SDMMC_DET, + PMU_WKUP_BY_TIMER = 6, + PMU_WKUP_BY_USBDEV_DET, + + PMU_WKUP_BY_M0_SFT, + PMU_WKUP_BY_M0_WDT_INT, + PMU_WKUP_BY_TIMEOUT, + PMU_WKUP_BY_PWM, + + PMU_WKUP_BY_PCIE = 13, +}; + +enum pmu_bus_clr { + PMU_CLR_GPU = 0, + PMU_CLR_PERILP, + PMU_CLR_PERIHP, + PMU_CLR_VCODEC, + + PMU_CLR_VDU, + PMU_CLR_RGA, + PMU_CLR_IEP, + PMU_CLR_VOPB, + + PMU_CLR_VOPL, + PMU_CLR_ISP0, + PMU_CLR_ISP1, + PMU_CLR_HDCP, + + PMU_CLR_USB3, + PMU_CLR_PERILPM0, + PMU_CLR_CENTER, + PMU_CLR_CCIM1, + + PMU_CLR_CCIM0, + PMU_CLR_VIO, + PMU_CLR_MSCH0, + PMU_CLR_MSCH1, + + PMU_CLR_ALIVE, + PMU_CLR_PMU, + PMU_CLR_EDP, + PMU_CLR_GMAC, + + PMU_CLR_EMMC, + PMU_CLR_CENTER1, + PMU_CLR_PMUM0, + PMU_CLR_GIC, + + PMU_CLR_SD, + PMU_CLR_SDIOAUDIO, +}; + +/* PMU bus idle request register */ +enum pmu_bus_idle_req { + PMU_IDLE_REQ_GPU = 0, + PMU_IDLE_REQ_PERILP, + PMU_IDLE_REQ_PERIHP, + PMU_IDLE_REQ_VCODEC, + + PMU_IDLE_REQ_VDU, + PMU_IDLE_REQ_RGA, + PMU_IDLE_REQ_IEP, + PMU_IDLE_REQ_VOPB, + + PMU_IDLE_REQ_VOPL, + PMU_IDLE_REQ_ISP0, + PMU_IDLE_REQ_ISP1, + PMU_IDLE_REQ_HDCP, + + PMU_IDLE_REQ_USB3, + PMU_IDLE_REQ_PERILPM0, + PMU_IDLE_REQ_CENTER, + PMU_IDLE_REQ_CCIM0, + + PMU_IDLE_REQ_CCIM1, + PMU_IDLE_REQ_VIO, + PMU_IDLE_REQ_MSCH0, + PMU_IDLE_REQ_MSCH1, + + PMU_IDLE_REQ_ALIVE, + PMU_IDLE_REQ_PMU, + PMU_IDLE_REQ_EDP, + PMU_IDLE_REQ_GMAC, + + PMU_IDLE_REQ_EMMC, + PMU_IDLE_REQ_CENTER1, + PMU_IDLE_REQ_PMUM0, + PMU_IDLE_REQ_GIC, + + PMU_IDLE_REQ_SD, + PMU_IDLE_REQ_SDIOAUDIO, +}; + +/* pmu bus idle status register */ +enum pmu_bus_idle_st { + PMU_IDLE_ST_GPU = 0, + PMU_IDLE_ST_PERILP, + PMU_IDLE_ST_PERIHP, + PMU_IDLE_ST_VCODEC, + + PMU_IDLE_ST_VDU, + PMU_IDLE_ST_RGA, + PMU_IDLE_ST_IEP, + PMU_IDLE_ST_VOPB, + + PMU_IDLE_ST_VOPL, + PMU_IDLE_ST_ISP0, + PMU_IDLE_ST_ISP1, + PMU_IDLE_ST_HDCP, + + PMU_IDLE_ST_USB3, + PMU_IDLE_ST_PERILPM0, + PMU_IDLE_ST_CENTER, + PMU_IDLE_ST_CCIM0, + + PMU_IDLE_ST_CCIM1, + PMU_IDLE_ST_VIO, + PMU_IDLE_ST_MSCH0, + PMU_IDLE_ST_MSCH1, + + PMU_IDLE_ST_ALIVE, + PMU_IDLE_ST_PMU, + PMU_IDLE_ST_EDP, + PMU_IDLE_ST_GMAC, + + PMU_IDLE_ST_EMMC, + PMU_IDLE_ST_CENTER1, + PMU_IDLE_ST_PMUM0, + PMU_IDLE_ST_GIC, + + PMU_IDLE_ST_SD, + PMU_IDLE_ST_SDIOAUDIO, +}; + +enum pmu_bus_idle_ack { + PMU_IDLE_ACK_GPU = 0, + PMU_IDLE_ACK_PERILP, + PMU_IDLE_ACK_PERIHP, + PMU_IDLE_ACK_VCODEC, + + PMU_IDLE_ACK_VDU, + PMU_IDLE_ACK_RGA, + PMU_IDLE_ACK_IEP, + PMU_IDLE_ACK_VOPB, + + PMU_IDLE_ACK_VOPL, + PMU_IDLE_ACK_ISP0, + PMU_IDLE_ACK_ISP1, + PMU_IDLE_ACK_HDCP, + + PMU_IDLE_ACK_USB3, + PMU_IDLE_ACK_PERILPM0, + PMU_IDLE_ACK_CENTER, + PMU_IDLE_ACK_CCIM0, + + PMU_IDLE_ACK_CCIM1, + PMU_IDLE_ACK_VIO, + PMU_IDLE_ACK_MSCH0, + PMU_IDLE_ACK_MSCH1, + + PMU_IDLE_ACK_ALIVE, + PMU_IDLE_ACK_PMU, + PMU_IDLE_ACK_EDP, + PMU_IDLE_ACK_GMAC, + + PMU_IDLE_ACK_EMMC, + PMU_IDLE_ACK_CENTER1, + PMU_IDLE_ACK_PMUM0, + PMU_IDLE_ACK_GIC, + + PMU_IDLE_ACK_SD, + PMU_IDLE_ACK_SDIOAUDIO, +}; + +enum pmu_cci500_con { + PMU_PREQ_CCI500_CFG_SW = 0, + PMU_CLR_PREQ_CCI500_HW, + PMU_PSTATE_CCI500_0, + PMU_PSTATE_CCI500_1, + + PMU_PSTATE_CCI500_2, + PMU_QREQ_CCI500_CFG_SW, + PMU_CLR_QREQ_CCI500_HW, + PMU_QGATING_CCI500_CFG, + + PMU_PREQ_CCI500_CFG_SW_WMSK = 16, + PMU_CLR_PREQ_CCI500_HW_WMSK, + PMU_PSTATE_CCI500_0_WMSK, + PMU_PSTATE_CCI500_1_WMSK, + + PMU_PSTATE_CCI500_2_WMSK, + PMU_QREQ_CCI500_CFG_SW_WMSK, + PMU_CLR_QREQ_CCI500_HW_WMSK, + PMU_QGATING_CCI500_CFG_WMSK, +}; + +enum pmu_adb400_con { + PMU_PWRDWN_REQ_CXCS_SW = 0, + PMU_PWRDWN_REQ_CORE_L_SW, + PMU_PWRDWN_REQ_CORE_L_2GIC_SW, + PMU_PWRDWN_REQ_GIC2_CORE_L_SW, + + PMU_PWRDWN_REQ_CORE_B_SW, + PMU_PWRDWN_REQ_CORE_B_2GIC_SW, + PMU_PWRDWN_REQ_GIC2_CORE_B_SW, + + PMU_CLR_CXCS_HW = 8, + PMU_CLR_CORE_L_HW, + PMU_CLR_CORE_L_2GIC_HW, + PMU_CLR_GIC2_CORE_L_HW, + + PMU_CLR_CORE_B_HW, + PMU_CLR_CORE_B_2GIC_HW, + PMU_CLR_GIC2_CORE_B_HW, + + PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16, + PMU_PWRDWN_REQ_CORE_L_SW_WMSK, + PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK, + PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK, + + PMU_PWRDWN_REQ_CORE_B_SW_WMSK, + PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK, + PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK, + + PMU_CLR_CXCS_HW_WMSK = 24, + PMU_CLR_CORE_L_HW_WMSK, + PMU_CLR_CORE_L_2GIC_HW_WMSK, + PMU_CLR_GIC2_CORE_L_HW_WMSK, + + PMU_CLR_CORE_B_HW_WMSK, + PMU_CLR_CORE_B_2GIC_HW_WMSK, + PMU_CLR_GIC2_CORE_B_HW_WMSK, +}; + +enum pmu_adb400_st { + PMU_PWRDWN_REQ_CXCS_SW_ST = 0, + PMU_PWRDWN_REQ_CORE_L_SW_ST, + PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST, + PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST, + + PMU_PWRDWN_REQ_CORE_B_SW_ST, + PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST, + PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST, + + PMU_CLR_CXCS_HW_ST = 8, + PMU_CLR_CORE_L_HW_ST, + PMU_CLR_CORE_L_2GIC_HW_ST, + PMU_CLR_GIC2_CORE_L_HW_ST, + + PMU_CLR_CORE_B_HW_ST, + PMU_CLR_CORE_B_2GIC_HW_ST, + PMU_CLR_GIC2_CORE_B_HW_ST, +}; + +enum pmu_pwrdn_con1 { + PMU_VD_SCU_L_PWRDN_EN = 0, + PMU_VD_SCU_B_PWRDN_EN, + PMU_VD_CENTER_PWRDN_EN, +}; + +enum pmu_core_pwr_st { + L2_FLUSHDONE_CLUSTER_L = 0, + STANDBY_BY_WFIL2_CLUSTER_L, + + L2_FLUSHDONE_CLUSTER_B = 10, + STANDBY_BY_WFIL2_CLUSTER_B, +}; + +#define PMU_WKUP_CFG0 0x00 +#define PMU_WKUP_CFG1 0x04 +#define PMU_WKUP_CFG2 0x08 +#define PMU_WKUP_CFG3 0x0c +#define PMU_WKUP_CFG4 0x10 +#define PMU_PWRDN_CON 0x14 +#define PMU_PWRDN_ST 0x18 +#define PMU_PLL_CON 0x1c +#define PMU_PWRMODE_CON 0x20 +#define PMU_SFT_CON 0x24 +#define PMU_INT_CON 0x28 +#define PMU_INT_ST 0x2c +#define PMU_GPIO0_POS_INT_CON 0x30 +#define PMU_GPIO0_NEG_INT_CON 0x34 +#define PMU_GPIO1_POS_INT_CON 0x38 +#define PMU_GPIO1_NEG_INT_CON 0x3c +#define PMU_GPIO0_POS_INT_ST 0x40 +#define PMU_GPIO0_NEG_INT_ST 0x44 +#define PMU_GPIO1_POS_INT_ST 0x48 +#define PMU_GPIO1_NEG_INT_ST 0x4c +#define PMU_PWRDN_INTEN 0x50 +#define PMU_PWRDN_STATUS 0x54 +#define PMU_WAKEUP_STATUS 0x58 +#define PMU_BUS_CLR 0x5c +#define PMU_BUS_IDLE_REQ 0x60 +#define PMU_BUS_IDLE_ST 0x64 +#define PMU_BUS_IDLE_ACK 0x68 +#define PMU_CCI500_CON 0x6c +#define PMU_ADB400_CON 0x70 +#define PMU_ADB400_ST 0x74 +#define PMU_POWER_ST 0x78 +#define PMU_CORE_PWR_ST 0x7c +#define PMU_OSC_CNT 0x80 +#define PMU_PLLLOCK_CNT 0x84 +#define PMU_PLLRST_CNT 0x88 +#define PMU_STABLE_CNT 0x8c +#define PMU_DDRIO_PWRON_CNT 0x90 +#define PMU_WAKEUP_RST_CLR_CNT 0x94 +#define PMU_DDR_SREF_ST 0x98 +#define PMU_SCU_L_PWRDN_CNT 0x9c +#define PMU_SCU_L_PWRUP_CNT 0xa0 +#define PMU_SCU_B_PWRDN_CNT 0xa4 +#define PMU_SCU_B_PWRUP_CNT 0xa8 +#define PMU_GPU_PWRDN_CNT 0xac +#define PMU_GPU_PWRUP_CNT 0xb0 +#define PMU_CENTER_PWRDN_CNT 0xb4 +#define PMU_CENTER_PWRUP_CNT 0xb8 +#define PMU_TIMEOUT_CNT 0xbc +#define PMU_CPU0APM_CON 0xc0 +#define PMU_CPU1APM_CON 0xc4 +#define PMU_CPU2APM_CON 0xc8 +#define PMU_CPU3APM_CON 0xcc +#define PMU_CPU0BPM_CON 0xd0 +#define PMU_CPU1BPM_CON 0xd4 +#define PMU_NOC_AUTO_ENA 0xd8 +#define PMU_PWRDN_CON1 0xdc + +#define PMUGRF_GPIO0A_IOMUX 0x00 +#define PMUGRF_GPIO1A_IOMUX 0x10 +#define PMUGRF_GPIO1C_IOMUX 0x18 + +#define PMUGRF_GPIO0A6_IOMUX_SHIFT 12 +#define PMUGRF_GPIO0A6_IOMUX_PWM 0x1 +#define PMUGRF_GPIO1C3_IOMUX_SHIFT 6 +#define PMUGRF_GPIO1C3_IOMUX_PWM 0x1 + +#define AP_PWROFF 0x0a + +#define GPIO0A0_SMT_ENABLE BITS_WITH_WMASK(1, 3, 0) +#define GPIO1A6_IOMUX BITS_WITH_WMASK(0, 3, 12) + +#define TSADC_INT_PIN 38 +#define CORES_PM_DISABLE 0x0 +#define CPU_AXI_QOS_ID_COREID 0x00 +#define CPU_AXI_QOS_REVISIONID 0x04 +#define CPU_AXI_QOS_PRIORITY 0x08 +#define CPU_AXI_QOS_MODE 0x0c +#define CPU_AXI_QOS_BANDWIDTH 0x10 +#define CPU_AXI_QOS_SATURATION 0x14 +#define CPU_AXI_QOS_EXTCONTROL 0x18 +#define CPU_AXI_QOS_NUM_REGS 0x07 + +#define CPU_AXI_CCI_M0_QOS_BASE 0xffa50000 +#define CPU_AXI_CCI_M1_QOS_BASE 0xffad8000 +#define CPU_AXI_DMAC0_QOS_BASE 0xffa64200 +#define CPU_AXI_DMAC1_QOS_BASE 0xffa64280 +#define CPU_AXI_DCF_QOS_BASE 0xffa64180 +#define CPU_AXI_CRYPTO0_QOS_BASE 0xffa64100 +#define CPU_AXI_CRYPTO1_QOS_BASE 0xffa64080 +#define CPU_AXI_PMU_CM0_QOS_BASE 0xffa68000 +#define CPU_AXI_PERI_CM1_QOS_BASE 0xffa64300 +#define CPU_AXI_GIC_QOS_BASE 0xffa78000 +#define CPU_AXI_SDIO_QOS_BASE 0xffa76000 +#define CPU_AXI_SDMMC_QOS_BASE 0xffa74000 +#define CPU_AXI_EMMC_QOS_BASE 0xffa58000 +#define CPU_AXI_GMAC_QOS_BASE 0xffa5c000 +#define CPU_AXI_USB_OTG0_QOS_BASE 0xffa70000 +#define CPU_AXI_USB_OTG1_QOS_BASE 0xffa70080 +#define CPU_AXI_USB_HOST0_QOS_BASE 0xffa60100 +#define CPU_AXI_USB_HOST1_QOS_BASE 0xffa60180 +#define CPU_AXI_GPU_QOS_BASE 0xffae0000 +#define CPU_AXI_VIDEO_M0_QOS_BASE 0xffab8000 +#define CPU_AXI_VIDEO_M1_R_QOS_BASE 0xffac0000 +#define CPU_AXI_VIDEO_M1_W_QOS_BASE 0xffac0080 +#define CPU_AXI_RGA_R_QOS_BASE 0xffab0000 +#define CPU_AXI_RGA_W_QOS_BASE 0xffab0080 +#define CPU_AXI_IEP_QOS_BASE 0xffa98000 +#define CPU_AXI_VOP_BIG_R_QOS_BASE 0xffac8000 +#define CPU_AXI_VOP_BIG_W_QOS_BASE 0xffac8080 +#define CPU_AXI_VOP_LITTLE_QOS_BASE 0xffad0000 +#define CPU_AXI_ISP0_M0_QOS_BASE 0xffaa0000 +#define CPU_AXI_ISP0_M1_QOS_BASE 0xffaa0080 +#define CPU_AXI_ISP1_M0_QOS_BASE 0xffaa8000 +#define CPU_AXI_ISP1_M1_QOS_BASE 0xffaa8080 +#define CPU_AXI_HDCP_QOS_BASE 0xffa90000 +#define CPU_AXI_PERIHP_NSP_QOS_BASE 0xffad8080 +#define CPU_AXI_PERILP_NSP_QOS_BASE 0xffad8180 +#define CPU_AXI_PERILPSLV_NSP_QOS_BASE 0xffad8100 + +#define PD_CTR_LOOP 500 +#define CHK_CPU_LOOP 500 +#define MAX_WAIT_COUNT 1000 + +#define GRF_SOC_CON4 0x0e210 + +#define GRF_GPIO2A_IOMUX 0xe000 +#define GRF_GPIO2B_IOMUX 0xe004 +#define GRF_GPIO2C_IOMUX 0xe008 +#define GRF_GPIO2D_IOMUX 0xe00c +#define GRF_GPIO3A_IOMUX 0xe010 +#define GRF_GPIO3B_IOMUX 0xe014 +#define GRF_GPIO3C_IOMUX 0xe018 +#define GRF_GPIO3D_IOMUX 0xe01c +#define GRF_GPIO4A_IOMUX 0xe020 +#define GRF_GPIO4B_IOMUX 0xe024 +#define GRF_GPIO4C_IOMUX 0xe028 +#define GRF_GPIO4D_IOMUX 0xe02c + +#define GRF_GPIO2A_P 0xe040 +#define GRF_GPIO2B_P 0xe044 +#define GRF_GPIO2C_P 0xe048 +#define GRF_GPIO2D_P 0xe04C +#define GRF_GPIO3A_P 0xe050 +#define GRF_GPIO3B_P 0xe054 +#define GRF_GPIO3C_P 0xe058 +#define GRF_GPIO3D_P 0xe05C +#define GRF_GPIO4A_P 0xe060 +#define GRF_GPIO4B_P 0xe064 +#define GRF_GPIO4C_P 0xe068 +#define GRF_GPIO4D_P 0xe06C + +#define PMUGRF_GPIO0A_SMT 0x0120 +#define PMUGRF_SOC_CON0 0x0180 + +#define CCI_FORCE_WAKEUP WMSK_BIT(8) +#define EXTERNAL_32K WMSK_BIT(0) + +#define PLL_PD_HW 0xff +#define IOMUX_CLK_32K 0x00030002 +#define NOC_AUTO_ENABLE 0x3fffffff + +#define SAVE_QOS(array, NAME) \ + RK3399_CPU_AXI_SAVE_QOS(array, CPU_AXI_##NAME##_QOS_BASE) +#define RESTORE_QOS(array, NAME) \ + RK3399_CPU_AXI_RESTORE_QOS(array, CPU_AXI_##NAME##_QOS_BASE) + +#define RK3399_CPU_AXI_SAVE_QOS(array, base) do { \ + array[0] = mmio_read_32(base + CPU_AXI_QOS_ID_COREID); \ + array[1] = mmio_read_32(base + CPU_AXI_QOS_REVISIONID); \ + array[2] = mmio_read_32(base + CPU_AXI_QOS_PRIORITY); \ + array[3] = mmio_read_32(base + CPU_AXI_QOS_MODE); \ + array[4] = mmio_read_32(base + CPU_AXI_QOS_BANDWIDTH); \ + array[5] = mmio_read_32(base + CPU_AXI_QOS_SATURATION); \ + array[6] = mmio_read_32(base + CPU_AXI_QOS_EXTCONTROL); \ +} while (0) + +#define RK3399_CPU_AXI_RESTORE_QOS(array, base) do { \ + mmio_write_32(base + CPU_AXI_QOS_ID_COREID, array[0]); \ + mmio_write_32(base + CPU_AXI_QOS_REVISIONID, array[1]); \ + mmio_write_32(base + CPU_AXI_QOS_PRIORITY, array[2]); \ + mmio_write_32(base + CPU_AXI_QOS_MODE, array[3]); \ + mmio_write_32(base + CPU_AXI_QOS_BANDWIDTH, array[4]); \ + mmio_write_32(base + CPU_AXI_QOS_SATURATION, array[5]); \ + mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \ +} while (0) + +struct pmu_slpdata_s { + uint32_t cci_m0_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t cci_m1_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t dmac0_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t dmac1_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t dcf_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t crypto0_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t crypto1_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t pmu_cm0_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t peri_cm1_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t gic_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t sdmmc_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t gmac_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t emmc_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t usb_otg0_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t usb_otg1_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t usb_host0_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t usb_host1_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t gpu_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t video_m0_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t video_m1_r_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t video_m1_w_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t rga_r_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t rga_w_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t vop_big_r[CPU_AXI_QOS_NUM_REGS]; + uint32_t vop_big_w[CPU_AXI_QOS_NUM_REGS]; + uint32_t vop_little[CPU_AXI_QOS_NUM_REGS]; + uint32_t iep_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t isp1_m0_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t isp1_m1_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t isp0_m0_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t isp0_m1_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t hdcp_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t perihp_nsp_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t perilp_nsp_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t perilpslv_nsp_qos[CPU_AXI_QOS_NUM_REGS]; + uint32_t sdio_qos[CPU_AXI_QOS_NUM_REGS]; +}; + +extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT]; +#endif /* __PMU_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pwm/pwm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pwm/pwm.c new file mode 100644 index 0000000..7845c63 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pwm/pwm.c @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#define PWM0_IOMUX_PWM_EN (1 << 0) +#define PWM1_IOMUX_PWM_EN (1 << 1) +#define PWM2_IOMUX_PWM_EN (1 << 2) +#define PWM3_IOMUX_PWM_EN (1 << 3) + +struct pwm_data_s { + uint32_t iomux_bitmask; + uint32_t enable_bitmask; +}; + +static struct pwm_data_s pwm_data; + +/* + * Disable the PWMs. + */ +void disable_pwms(void) +{ + uint32_t i, val; + + pwm_data.iomux_bitmask = 0; + + /* Save PWMs pinmux and change PWMs pinmux to GPIOs */ + val = mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX); + if (((val >> GRF_GPIO4C2_IOMUX_SHIFT) & + GRF_IOMUX_2BIT_MASK) == GRF_GPIO4C2_IOMUX_PWM) { + pwm_data.iomux_bitmask |= PWM0_IOMUX_PWM_EN; + val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK, + GRF_GPIO4C2_IOMUX_SHIFT); + mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); + } + + val = mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX); + if (((val >> GRF_GPIO4C6_IOMUX_SHIFT) & + GRF_IOMUX_2BIT_MASK) == GRF_GPIO4C6_IOMUX_PWM) { + pwm_data.iomux_bitmask |= PWM1_IOMUX_PWM_EN; + val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK, + GRF_GPIO4C6_IOMUX_SHIFT); + mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); + } + + val = mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX); + if (((val >> PMUGRF_GPIO1C3_IOMUX_SHIFT) & + GRF_IOMUX_2BIT_MASK) == PMUGRF_GPIO1C3_IOMUX_PWM) { + pwm_data.iomux_bitmask |= PWM2_IOMUX_PWM_EN; + val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK, + PMUGRF_GPIO1C3_IOMUX_SHIFT); + mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val); + } + + val = mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX); + if (((val >> PMUGRF_GPIO0A6_IOMUX_SHIFT) & + GRF_IOMUX_2BIT_MASK) == PMUGRF_GPIO0A6_IOMUX_PWM) { + pwm_data.iomux_bitmask |= PWM3_IOMUX_PWM_EN; + val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK, + PMUGRF_GPIO0A6_IOMUX_SHIFT); + mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val); + } + + /* Disable the pwm channel */ + pwm_data.enable_bitmask = 0; + for (i = 0; i < 4; i++) { + val = mmio_read_32(PWM_BASE + PWM_CTRL(i)); + if ((val & PWM_ENABLE) != PWM_ENABLE) + continue; + pwm_data.enable_bitmask |= (1 << i); + mmio_write_32(PWM_BASE + PWM_CTRL(i), val & ~PWM_ENABLE); + } +} + +/* + * Enable the PWMs. + */ +void enable_pwms(void) +{ + uint32_t i, val; + + for (i = 0; i < 4; i++) { + val = mmio_read_32(PWM_BASE + PWM_CTRL(i)); + if (!(pwm_data.enable_bitmask & (1 << i))) + continue; + mmio_write_32(PWM_BASE + PWM_CTRL(i), val | PWM_ENABLE); + } + + /* Restore all IOMUXes */ + if (pwm_data.iomux_bitmask & PWM3_IOMUX_PWM_EN) { + val = BITS_WITH_WMASK(PMUGRF_GPIO0A6_IOMUX_PWM, + GRF_IOMUX_2BIT_MASK, + PMUGRF_GPIO0A6_IOMUX_SHIFT); + mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val); + } + + if (pwm_data.iomux_bitmask & PWM2_IOMUX_PWM_EN) { + val = BITS_WITH_WMASK(PMUGRF_GPIO1C3_IOMUX_PWM, + GRF_IOMUX_2BIT_MASK, + PMUGRF_GPIO1C3_IOMUX_SHIFT); + mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val); + } + + if (pwm_data.iomux_bitmask & PWM1_IOMUX_PWM_EN) { + val = BITS_WITH_WMASK(GRF_GPIO4C6_IOMUX_PWM, + GRF_IOMUX_2BIT_MASK, + GRF_GPIO4C6_IOMUX_SHIFT); + mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); + } + + if (pwm_data.iomux_bitmask & PWM0_IOMUX_PWM_EN) { + val = BITS_WITH_WMASK(GRF_GPIO4C2_IOMUX_PWM, + GRF_IOMUX_2BIT_MASK, + GRF_GPIO4C2_IOMUX_SHIFT); + mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val); + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pwm/pwm.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pwm/pwm.h new file mode 100644 index 0000000..0f75a8d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pwm/pwm.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PWM_H__ +#define __PWM_H__ + +void disable_pwms(void); +void enable_pwms(void); + +#endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/soc.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/soc.c new file mode 100644 index 0000000..29bf6dd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/soc.c @@ -0,0 +1,390 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Table of regions to map using the MMU. */ +const mmap_region_t plat_rk_mmap[] = { + MAP_REGION_FLAT(RK3399_DEV_RNG0_BASE, RK3399_DEV_RNG0_SIZE, + MT_DEVICE | MT_RW | MT_SECURE), + + { 0 } +}; + +/* The RockChip power domain tree descriptor */ +const unsigned char rockchip_power_domain_tree_desc[] = { + /* No of root nodes */ + PLATFORM_SYSTEM_COUNT, + /* No of children for the root node */ + PLATFORM_CLUSTER_COUNT, + /* No of children for the first cluster node */ + PLATFORM_CLUSTER0_CORE_COUNT, + /* No of children for the second cluster node */ + PLATFORM_CLUSTER1_CORE_COUNT +}; + +void secure_timer_init(void) +{ + mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT0, 0xffffffff); + mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_END_COUNT1, 0xffffffff); + + mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); + mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_INIT_COUNT0, 0x0); + + /* auto reload & enable the timer */ + mmio_write_32(STIMER1_CHN_BASE(5) + TIMER_CONTROL_REG, + TIMER_EN | TIMER_FMODE); +} + +void sgrf_init(void) +{ + /* security config for master */ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(5), + SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(6), + SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(7), + SGRF_SOC_CON_WMSK | SGRF_SOC_ALLMST_NS); + + /* security config for slave */ + mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(0), + SGRF_PMU_SLV_S_CFGED | + SGRF_PMU_SLV_CRYPTO1_NS); + mmio_write_32(SGRF_BASE + SGRF_PMU_SLV_CON0_1(1), + SGRF_PMU_SLV_CON1_CFG); + mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(0), + SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); + mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(1), + SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); + mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(2), + SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); + mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(3), + SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); + mmio_write_32(SGRF_BASE + SGRF_SLV_SECURE_CON0_4(4), + SGRF_SLV_S_WMSK | SGRF_SLV_S_ALL_NS); + + /* security config for ddr memery */ + mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON0_16(16), + SGRF_DDR_RGN_BYPS); +} + +static void dma_secure_cfg(uint32_t secure) +{ + if (secure) { + /* rgn0 secure for dmac0 and dmac1 */ + mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), + SGRF_L_MST_S_DDR_RGN(0) | /* dmac0 */ + SGRF_H_MST_S_DDR_RGN(0) /* dmac1 */ + ); + + /* set dmac0 boot, under secure state */ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), + SGRF_DMAC_CFG_S); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), + SGRF_DMAC_CFG_S); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), + SGRF_DMAC_CFG_S); + + /* dmac0 soft reset */ + mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), + CRU_DMAC0_RST); + udelay(5); + mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), + CRU_DMAC0_RST_RLS); + + /* set dmac1 boot, under secure state */ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), + SGRF_DMAC_CFG_S); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), + SGRF_DMAC_CFG_S); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), + SGRF_DMAC_CFG_S); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), + SGRF_DMAC_CFG_S); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), + SGRF_DMAC_CFG_S); + + /* dmac1 soft reset */ + mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), + CRU_DMAC1_RST); + udelay(5); + mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), + CRU_DMAC1_RST_RLS); + } else { + /* rgn non-secure for dmac0 and dmac1 */ + mmio_write_32(SGRF_BASE + SGRF_DDRRGN_CON20_34(22), + DMAC1_RGN_NS | DMAC0_RGN_NS); + + /* set dmac0 boot, under non-secure state */ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(8), + DMAC0_BOOT_CFG_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(9), + DMAC0_BOOT_PERIPH_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(10), + DMAC0_BOOT_ADDR_NS); + + /* dmac0 soft reset */ + mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), + CRU_DMAC0_RST); + udelay(5); + mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), + CRU_DMAC0_RST_RLS); + + /* set dmac1 boot, under non-secure state */ + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(11), + DMAC1_BOOT_CFG_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(12), + DMAC1_BOOT_PERIPH_L_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(13), + DMAC1_BOOT_ADDR_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(14), + DMAC1_BOOT_PERIPH_H_NS); + mmio_write_32(SGRF_BASE + SGRF_SOC_CON8_15(15), + DMAC1_BOOT_IRQ_NS); + + /* dmac1 soft reset */ + mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), + CRU_DMAC1_RST); + udelay(5); + mmio_write_32(CRU_BASE + CRU_SOFTRST_CON(10), + CRU_DMAC1_RST_RLS); + } +} + +/* pll suspend */ +struct deepsleep_data_s slp_data; + +static void pll_suspend_prepare(uint32_t pll_id) +{ + int i; + + if (pll_id == PPLL_ID) + for (i = 0; i < PLL_CON_COUNT; i++) + slp_data.plls_con[pll_id][i] = + mmio_read_32(PMUCRU_BASE + PMUCRU_PPLL_CON(i)); + else + for (i = 0; i < PLL_CON_COUNT; i++) + slp_data.plls_con[pll_id][i] = + mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i)); +} + +static void set_pll_slow_mode(uint32_t pll_id) +{ + if (pll_id == PPLL_ID) + mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); + else + mmio_write_32((CRU_BASE + + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); +} + +static void set_pll_normal_mode(uint32_t pll_id) +{ + if (pll_id == PPLL_ID) + mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE); + else + mmio_write_32(CRU_BASE + + CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE); +} + +static void set_pll_bypass(uint32_t pll_id) +{ + if (pll_id == PPLL_ID) + mmio_write_32(PMUCRU_BASE + + PMUCRU_PPLL_CON(3), PLL_BYPASS_MODE); + else + mmio_write_32(CRU_BASE + + CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE); +} + +static void _pll_suspend(uint32_t pll_id) +{ + set_pll_slow_mode(pll_id); + set_pll_bypass(pll_id); +} + +void disable_dvfs_plls(void) +{ + _pll_suspend(CPLL_ID); + _pll_suspend(NPLL_ID); + _pll_suspend(VPLL_ID); + _pll_suspend(GPLL_ID); + _pll_suspend(ABPLL_ID); + _pll_suspend(ALPLL_ID); +} + +void disable_nodvfs_plls(void) +{ + _pll_suspend(PPLL_ID); +} + +void plls_suspend_prepare(void) +{ + uint32_t i, pll_id; + + for (pll_id = ALPLL_ID; pll_id < END_PLL_ID; pll_id++) + pll_suspend_prepare(pll_id); + + for (i = 0; i < CRU_CLKSEL_COUNT; i++) + slp_data.cru_clksel_con[i] = + mmio_read_32(CRU_BASE + CRU_CLKSEL_CON(i)); + + for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) + slp_data.pmucru_clksel_con[i] = + mmio_read_32(PMUCRU_BASE + + PMUCRU_CLKSEL_OFFSET + i * REG_SIZE); +} + +void clk_gate_con_save(void) +{ + uint32_t i = 0; + + for (i = 0; i < PMUCRU_GATE_COUNT; i++) + slp_data.pmucru_gate_con[i] = + mmio_read_32(PMUCRU_BASE + PMUCRU_GATE_CON(i)); + + for (i = 0; i < CRU_GATE_COUNT; i++) + slp_data.cru_gate_con[i] = + mmio_read_32(CRU_BASE + CRU_GATE_CON(i)); +} + +void clk_gate_con_disable(void) +{ + uint32_t i; + + for (i = 0; i < PMUCRU_GATE_COUNT; i++) + mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), REG_SOC_WMSK); + + for (i = 0; i < CRU_GATE_COUNT; i++) + mmio_write_32(CRU_BASE + CRU_GATE_CON(i), REG_SOC_WMSK); +} + +void clk_gate_con_restore(void) +{ + uint32_t i; + + for (i = 0; i < PMUCRU_GATE_COUNT; i++) + mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), + REG_SOC_WMSK | slp_data.pmucru_gate_con[i]); + + for (i = 0; i < CRU_GATE_COUNT; i++) + mmio_write_32(CRU_BASE + CRU_GATE_CON(i), + REG_SOC_WMSK | slp_data.cru_gate_con[i]); +} + +static void set_plls_nobypass(uint32_t pll_id) +{ + if (pll_id == PPLL_ID) + mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), + PLL_NO_BYPASS_MODE); + else + mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), + PLL_NO_BYPASS_MODE); +} + +static void _pll_resume(uint32_t pll_id) +{ + set_plls_nobypass(pll_id); + set_pll_normal_mode(pll_id); +} + +void plls_resume_finish(void) +{ + int i; + + for (i = 0; i < CRU_CLKSEL_COUNT; i++) + mmio_write_32((CRU_BASE + CRU_CLKSEL_CON(i)), + REG_SOC_WMSK | slp_data.cru_clksel_con[i]); + for (i = 0; i < PMUCRU_CLKSEL_CONUT; i++) + mmio_write_32((PMUCRU_BASE + + PMUCRU_CLKSEL_OFFSET + i * REG_SIZE), + REG_SOC_WMSK | slp_data.pmucru_clksel_con[i]); +} + +void enable_dvfs_plls(void) +{ + _pll_resume(ALPLL_ID); + _pll_resume(ABPLL_ID); + _pll_resume(GPLL_ID); + _pll_resume(VPLL_ID); + _pll_resume(NPLL_ID); + _pll_resume(CPLL_ID); +} + +void enable_nodvfs_plls(void) +{ + _pll_resume(PPLL_ID); +} + +void soc_global_soft_reset_init(void) +{ + mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), + CRU_PMU_SGRF_RST_RLS); + + mmio_clrbits_32(CRU_BASE + CRU_GLB_RST_CON, + CRU_PMU_WDTRST_MSK | CRU_PMU_FIRST_SFTRST_MSK); +} + +void __dead2 soc_global_soft_reset(void) +{ + set_pll_slow_mode(VPLL_ID); + set_pll_slow_mode(NPLL_ID); + set_pll_slow_mode(GPLL_ID); + set_pll_slow_mode(CPLL_ID); + set_pll_slow_mode(PPLL_ID); + set_pll_slow_mode(ABPLL_ID); + set_pll_slow_mode(ALPLL_ID); + + dsb(); + + mmio_write_32(CRU_BASE + CRU_GLB_SRST_FST, GLB_SRST_FST_CFG_VAL); + + /* + * Maybe the HW needs some times to reset the system, + * so we do not hope the core to excute valid codes. + */ + while (1) + ; +} + +void plat_rockchip_soc_init(void) +{ + secure_timer_init(); + dma_secure_cfg(0); + sgrf_init(); + soc_global_soft_reset_init(); + plat_rockchip_gpio_init(); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/soc.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/soc.h new file mode 100644 index 0000000..906452a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/drivers/soc/soc.h @@ -0,0 +1,328 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SOC_H__ +#define __SOC_H__ + +#define GLB_SRST_FST_CFG_VAL 0xfdb9 +#define GLB_SRST_SND_CFG_VAL 0xeca8 + +#define PMUCRU_PPLL_CON(n) ((n) * 4) +#define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) +#define PLL_MODE_MSK 0x03 +#define PLL_MODE_SHIFT 0x08 +#define PLL_BYPASS_MSK 0x01 +#define PLL_BYPASS_SHIFT 0x01 +#define PLL_PWRDN_MSK 0x01 +#define PLL_PWRDN_SHIFT 0x0 +#define PLL_BYPASS BIT(1) +#define PLL_PWRDN BIT(0) + +#define NO_PLL_BYPASS (0x00) +#define NO_PLL_PWRDN (0x00) + +#define FBDIV(n) ((0xfff << 16) | n) +#define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12)) +#define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8)) +#define REFDIV(n) ((0x3F << 16) | n) +#define PLL_LOCK(n) ((n >> 31) & 0x1) + +#define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\ + PLL_MODE_MSK, PLL_MODE_SHIFT) + +#define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\ + PLL_MODE_MSK, PLL_MODE_SHIFT) + +#define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT) +#define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT) + +#define PLL_CON_COUNT 0x06 +#define CRU_CLKSEL_COUNT 0x108 +#define CRU_CLKSEL_CON(n) (0x80 + (n) * 4) + +#define PMUCRU_CLKSEL_CONUT 0x06 +#define PMUCRU_CLKSEL_OFFSET 0x080 +#define REG_SIZE 0x04 +#define REG_SOC_WMSK 0xffff0000 +#define CLK_GATE_MASK 0x01 + +#define PMUCRU_GATE_COUNT 0x03 +#define CRU_GATE_COUNT 0x23 +#define PMUCRU_GATE_CON(n) (0x100 + (n) * 4) +#define CRU_GATE_CON(n) (0x300 + (n) * 4) + +enum plls_id { + ALPLL_ID = 0, + ABPLL_ID, + DPLL_ID, + CPLL_ID, + GPLL_ID, + NPLL_ID, + VPLL_ID, + PPLL_ID, + END_PLL_ID, +}; + +#define CLST_L_CPUS_MSK (0xf) +#define CLST_B_CPUS_MSK (0x3) + +enum pll_work_mode { + SLOW_MODE = 0x00, + NORMAL_MODE = 0x01, + DEEP_SLOW_MODE = 0x02, +}; + +enum glb_sft_reset { + PMU_RST_BY_FIRST_SFT, + PMU_RST_BY_SECOND_SFT = BIT(2), + PMU_RST_NOT_BY_SFT = BIT(3), +}; + +struct deepsleep_data_s { + uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT]; + uint32_t pmucru_clksel_con[PMUCRU_CLKSEL_CONUT]; + uint32_t cru_clksel_con[CRU_CLKSEL_COUNT]; + uint32_t cru_gate_con[CRU_GATE_COUNT]; + uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT]; +}; + +/************************************************** + * pmugrf reg, offset + **************************************************/ +#define PMUGRF_OSREG(n) (0x300 + (n) * 4) + +/************************************************** + * DCF reg, offset + **************************************************/ +#define DCF_DCF_CTRL 0x0 +#define DCF_DCF_ADDR 0x8 +#define DCF_DCF_ISR 0xc +#define DCF_DCF_TOSET 0x14 +#define DCF_DCF_TOCMD 0x18 +#define DCF_DCF_CMD_CFG 0x1c + +/* DCF_DCF_ISR */ +#define DCF_TIMEOUT (1 << 2) +#define DCF_ERR (1 << 1) +#define DCF_DONE (1 << 0) + +/* DCF_DCF_CTRL */ +#define DCF_VOP_HW_EN (1 << 2) +#define DCF_STOP (1 << 1) +#define DCF_START (1 << 0) + +#define CYCL_24M_CNT_US(us) (24 * us) +#define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000)) +#define CYCL_32K_CNT_MS(ms) (ms * 32) + +/************************************************** + * secure timer + **************************************************/ + +/* chanal0~5 */ +#define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) +/* chanal6~11 */ +#define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n)) + + /* low 32 bits */ +#define TIMER_END_COUNT0 0x00 + /* high 32 bits */ +#define TIMER_END_COUNT1 0x04 + +#define TIMER_CURRENT_VALUE0 0x08 +#define TIMER_CURRENT_VALUE1 0x0C + + /* low 32 bits */ +#define TIMER_INIT_COUNT0 0x10 + /* high 32 bits */ +#define TIMER_INIT_COUNT1 0x14 + +#define TIMER_INTSTATUS 0x18 +#define TIMER_CONTROL_REG 0x1c + +#define TIMER_EN 0x1 + +#define TIMER_FMODE (0x0 << 1) +#define TIMER_RMODE (0x1 << 1) + +/************************************************** + * cru reg, offset + **************************************************/ +#define CRU_SOFTRST_CON(n) (0x400 + (n) * 4) + +#define CRU_DMAC0_RST BIT_WITH_WMSK(3) + /* reset release*/ +#define CRU_DMAC0_RST_RLS WMSK_BIT(3) + +#define CRU_DMAC1_RST BIT_WITH_WMSK(4) + /* reset release*/ +#define CRU_DMAC1_RST_RLS WMSK_BIT(4) + +#define CRU_GLB_RST_CON 0x0510 +#define CRU_GLB_SRST_FST 0x0500 +#define CRU_GLB_SRST_SND 0x0504 + +#define CRU_CLKGATE_CON(n) (0x300 + n * 4) +#define PCLK_GPIO2_GATE_SHIFT 3 +#define PCLK_GPIO3_GATE_SHIFT 4 +#define PCLK_GPIO4_GATE_SHIFT 5 + +/************************************************** + * pmu cru reg, offset + **************************************************/ +#define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4) +/* reset hold*/ +#define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6) +/* reset hold release*/ +#define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6) + +#define CRU_PMU_WDTRST_MSK (0x1 << 4) +#define CRU_PMU_WDTRST_EN 0x0 + +#define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2) +#define CRU_PMU_FIRST_SFTRST_EN 0x0 + +#define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4) +#define PCLK_GPIO0_GATE_SHIFT 3 +#define PCLK_GPIO1_GATE_SHIFT 4 + +/************************************************** + * sgrf reg, offset + **************************************************/ +#define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) +#define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) +#define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) +#define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) +#define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) +#define SGRF_DDRRGN_CON0_16(n) ((n) * 4) +#define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) + +/* security config for master */ +#define SGRF_SOC_CON_WMSK 0xffff0000 +/* All of master in ns */ +#define SGRF_SOC_ALLMST_NS 0xffff + +/* security config for slave */ +#define SGRF_SLV_S_WMSK 0xffff0000 +#define SGRF_SLV_S_ALL_NS 0x0 + +/* security config pmu slave ip */ +/* All of slaves is ns */ +#define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) +/* slaves secure attr is configed */ +#define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) +#define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) + +#define SGRF_PMUSRAM_S BIT(8) + +#define SGRF_PMU_SLV_CON1_CFG (SGRF_SLV_S_WMSK | \ + SGRF_PMUSRAM_S) +/* ddr region */ +#define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) /* All of ddr rgn is ns */ + +/* The MST access the ddr rgn n with secure attribution */ +#define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) +/* bits[16:8]*/ +#define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8) + +/* dmac to periph s or ns*/ +#define SGRF_DMAC_CFG_S 0xffff0000 + +#define DMAC1_RGN_NS 0xff000000 +#define DMAC0_RGN_NS 0x00ff0000 + +#define DMAC0_BOOT_CFG_NS 0xfffffff8 +#define DMAC0_BOOT_PERIPH_NS 0xffff0fff +#define DMAC0_BOOT_ADDR_NS 0xffff0000 + +#define DMAC1_BOOT_CFG_NS 0xffff0008 +#define DMAC1_BOOT_PERIPH_L_NS 0xffff0fff +#define DMAC1_BOOT_ADDR_NS 0xffff0000 +#define DMAC1_BOOT_PERIPH_H_NS 0xffffffff +#define DMAC1_BOOT_IRQ_NS 0xffffffff + +#define CPU_BOOT_ADDR_WMASK 0xffff0000 +#define CPU_BOOT_ADDR_ALIGN 16 + +#define GRF_IOMUX_2BIT_MASK 0x3 +#define GRF_IOMUX_GPIO 0x0 + +#define GRF_GPIO4C2_IOMUX_SHIFT 4 +#define GRF_GPIO4C2_IOMUX_PWM 0x1 +#define GRF_GPIO4C6_IOMUX_SHIFT 12 +#define GRF_GPIO4C6_IOMUX_PWM 0x1 + +#define PWM_CNT(n) (0x0000 + 0x10 * (n)) +#define PWM_PERIOD_HPR(n) (0x0004 + 0x10 * (n)) +#define PWM_DUTY_LPR(n) (0x0008 + 0x10 * (n)) +#define PWM_CTRL(n) (0x000c + 0x10 * (n)) + +#define PWM_DISABLE (0 << 0) +#define PWM_ENABLE (1 << 0) + +/* grf reg offset */ +#define GRF_DDRC0_CON0 0xe380 +#define GRF_DDRC0_CON1 0xe384 +#define GRF_DDRC1_CON0 0xe388 +#define GRF_DDRC1_CON1 0xe38c + +/* + * When system reset in running state, we want the cpus to be reboot + * from maskrom (system reboot), + * the pmusgrf reset-hold bits needs to be released. + * When system wake up from system deep suspend, some soc will be reset + * when waked up, + * we want the bootcpu to be reboot from pmusram, + * the pmusgrf reset-hold bits needs to be held. + */ +static inline void pmu_sgrf_rst_hld_release(void) +{ + mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), + CRU_PMU_SGRF_RST_RLS); +} + +static inline void pmu_sgrf_rst_hld(void) +{ + mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), + CRU_PMU_SGRF_RST_HOLD); +} + +/* funciton*/ +void __dead2 soc_global_soft_reset(void); +void plls_suspend_prepare(void); +void disable_dvfs_plls(void); +void disable_nodvfs_plls(void); +void plls_resume_finish(void); +void enable_dvfs_plls(void); +void enable_nodvfs_plls(void); +void clk_gate_con_save(void); +void clk_gate_con_disable(void); +void clk_gate_con_restore(void); +#endif /* __SOC_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/include/plat_sip_calls.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/include/plat_sip_calls.h new file mode 100644 index 0000000..a778f49 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/include/plat_sip_calls.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_SIP_CALLS_H__ +#define __PLAT_SIP_CALLS_H__ + +#define RK_PLAT_SIP_NUM_CALLS 0 + +#endif /* __PLAT_SIP_CALLS_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/include/platform_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/include/platform_def.h new file mode 100644 index 0000000..b494824 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/include/platform_def.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include +#include +#include + +#define DEBUG_XLAT_TABLE 0 + +/******************************************************************************* + * Platform binary types for linking + ******************************************************************************/ +#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" +#define PLATFORM_LINKER_ARCH aarch64 + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#if DEBUG_XLAT_TABLE +#define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL1 +#define PLATFORM_STACK_SIZE 0x440 +#elif IMAGE_BL2 +#define PLATFORM_STACK_SIZE 0x400 +#elif IMAGE_BL31 +#define PLATFORM_STACK_SIZE 0x800 +#elif IMAGE_BL32 +#define PLATFORM_STACK_SIZE 0x440 +#endif + +#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" + +#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 +#define PLATFORM_SYSTEM_COUNT 1 +#define PLATFORM_CLUSTER_COUNT 2 +#define PLATFORM_CLUSTER0_CORE_COUNT 4 +#define PLATFORM_CLUSTER1_CORE_COUNT 2 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ + PLATFORM_CLUSTER0_CORE_COUNT) +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ + PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) +#define PLAT_RK_CLST_TO_CPUID_SHIFT 6 +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 + +/* + * This macro defines the deepest retention state possible. A higher state + * id will represent an invalid or a power down state. + */ +#define PLAT_MAX_RET_STATE 1 + +/* + * This macro defines the deepest power down states possible. Any state ID + * higher than this is invalid. + */ +#define PLAT_MAX_OFF_STATE 2 + +/******************************************************************************* + * Platform memory map related constants + ******************************************************************************/ +/* TF txet, ro, rw, Size: 512KB */ +#define TZRAM_BASE (0x0) +#define TZRAM_SIZE (0x80000) + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL3-1 at the top of the Trusted RAM + */ +#define BL31_BASE (TZRAM_BASE + 0x10000) +#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define ADDR_SPACE_SIZE (1ull << 32) +#define MAX_XLAT_TABLES 20 +#define MAX_MMAP_REGIONS 25 + +/******************************************************************************* + * Declarations and constants to access the mailboxes safely. Each mailbox is + * aligned on the biggest cache line size in the platform. This is known only + * to the platform as it might have a combination of integrated and external + * caches. Such alignment ensures that two maiboxes do not sit on the same cache + * line at any cache level. They could belong to different cpus/clusters & + * get written while being protected by different locks causing corruption of + * a valid mailbox address. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +/* + * Define GICD and GICC and GICR base + */ +#define PLAT_RK_GICD_BASE BASE_GICD_BASE +#define PLAT_RK_GICR_BASE BASE_GICR_BASE +#define PLAT_RK_GICC_BASE 0 + +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_RK_G1S_IRQS RK3399_G1S_IRQS +#define PLAT_RK_G0_IRQS RK3399_G0_IRQS + +#define PLAT_RK_UART_BASE RK3399_UART2_BASE +#define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK +#define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE + +#define PLAT_RK_CCI_BASE CCI500_BASE + +#define PLAT_RK_PRIMARY_CPU 0x0 + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/plat_sip_calls.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/plat_sip_calls.c new file mode 100644 index 0000000..a20ee2d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/plat_sip_calls.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#define RK_SIP_DDR_CFG 0x82000008 +#define DRAM_INIT 0x00 +#define DRAM_SET_RATE 0x01 +#define DRAM_ROUND_RATE 0x02 +#define DRAM_SET_AT_SR 0x03 +#define DRAM_GET_BW 0x04 +#define DRAM_GET_RATE 0x05 +#define DRAM_CLR_IRQ 0x06 +#define DRAM_SET_PARAM 0x07 + +uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, uint64_t id) +{ + switch (id) { + case DRAM_INIT: + ddr_init(); + break; + case DRAM_SET_RATE: + return ddr_set_rate((uint32_t)arg0); + case DRAM_ROUND_RATE: + return ddr_round_rate((uint32_t)arg0); + case DRAM_GET_RATE: + return ddr_get_rate(); + case DRAM_CLR_IRQ: + clr_dcf_irq(); + break; + case DRAM_SET_PARAM: + dts_timing_receive((uint32_t)arg0, (uint32_t)arg1); + break; + default: + break; + } + + return 0; +} + +uint64_t rockchip_plat_sip_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + switch (smc_fid) { + case RK_SIP_DDR_CFG: + SMC_RET1(handle, ddr_smc_handler(x1, x2, x3)); + default: + ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/platform.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/platform.mk new file mode 100644 index 0000000..3627857 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/platform.mk @@ -0,0 +1,84 @@ +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +RK_PLAT := plat/rockchip +RK_PLAT_SOC := ${RK_PLAT}/${PLAT} +RK_PLAT_COMMON := ${RK_PLAT}/common + +PLAT_INCLUDES := -I${RK_PLAT_COMMON}/ \ + -I${RK_PLAT_COMMON}/include/ \ + -I${RK_PLAT_COMMON}/pmusram \ + -I${RK_PLAT_COMMON}/drivers/pmu/ \ + -I${RK_PLAT_SOC}/ \ + -I${RK_PLAT_SOC}/drivers/pmu/ \ + -I${RK_PLAT_SOC}/drivers/pwm/ \ + -I${RK_PLAT_SOC}/drivers/soc/ \ + -I${RK_PLAT_SOC}/drivers/dram/ \ + -I${RK_PLAT_SOC}/include/ \ + +RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v3/gicv3_main.c \ + drivers/arm/gic/v3/gicv3_helpers.c \ + plat/common/plat_gicv3.c \ + ${RK_PLAT}/common/rockchip_gicv3.c + +PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ + lib/xlat_tables/aarch64/xlat_tables.c \ + plat/common/aarch64/plat_common.c \ + plat/common/plat_psci_common.c + +BL31_SOURCES += ${RK_GIC_SOURCES} \ + drivers/arm/cci/cci.c \ + drivers/console/aarch64/console.S \ + drivers/ti/uart/aarch64/16550_console.S \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + drivers/gpio/gpio.c \ + lib/cpus/aarch64/cortex_a53.S \ + lib/cpus/aarch64/cortex_a72.S \ + plat/common/aarch64/platform_mp_stack.S \ + ${RK_PLAT_COMMON}/aarch64/plat_helpers.S \ + ${RK_PLAT_COMMON}/bl31_plat_setup.c \ + ${RK_PLAT_COMMON}/params_setup.c \ + ${RK_PLAT_COMMON}/pmusram/pmu_sram_cpus_on.S \ + ${RK_PLAT_COMMON}/pmusram/pmu_sram.c \ + ${RK_PLAT_COMMON}/plat_pm.c \ + ${RK_PLAT_COMMON}/plat_topology.c \ + ${RK_PLAT_COMMON}/aarch64/platform_common.c \ + ${RK_PLAT_COMMON}/rockchip_sip_svc.c \ + ${RK_PLAT_SOC}/plat_sip_calls.c \ + ${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \ + ${RK_PLAT_SOC}/drivers/pmu/pmu.c \ + ${RK_PLAT_SOC}/drivers/pwm/pwm.c \ + ${RK_PLAT_SOC}/drivers/soc/soc.c \ + ${RK_PLAT_SOC}/drivers/dram/dram.c \ + ${RK_PLAT_SOC}/drivers/dram/dram_spec_timing.c + +ENABLE_PLAT_COMPAT := 0 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/rk3399_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/rk3399_def.h new file mode 100644 index 0000000..fdf93fd --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/rockchip/rk3399/rk3399_def.h @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLAT_DEF_H__ +#define __PLAT_DEF_H__ + +#define RK3399_PRIMARY_CPU 0x0 + +/* Special value used to verify platform parameters from BL2 to BL3-1 */ +#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL + +#define SIZE_K(n) ((n) * 1024) +#define SIZE_M(n) ((n) * 1024 * 1024) + +/* Register base address and size */ +#define MMIO_BASE 0xfe000000 + +#define GIC500_BASE (MMIO_BASE + 0xe00000) +#define GIC500_SIZE SIZE_M(2) + +#define PMU_BASE (MMIO_BASE + 0x1310000) +#define PMU_SIZE SIZE_K(64) + +#define PMUGRF_BASE (MMIO_BASE + 0x1320000) +#define PMUGRF_SIZE SIZE_K(64) + +#define SGRF_BASE (MMIO_BASE + 0x1330000) +#define SGRF_SIZE SIZE_K(64) + +#define PMUSRAM_BASE (MMIO_BASE + 0x13b0000) +#define PMUSRAM_SIZE SIZE_K(64) +#define PMUSRAM_RSIZE SIZE_K(8) + +#define PWM_BASE (MMIO_BASE + 0x1420000) +#define PWM_SIZE SIZE_K(64) + +#define CIC_BASE (MMIO_BASE + 0x1620000) +#define CIC_SIZE SIZE_K(4) + +#define DCF_BASE (MMIO_BASE + 0x16a0000) +#define DCF_SIZE SIZE_K(4) + +#define GPIO0_BASE (MMIO_BASE + 0x1720000) +#define GPIO0_SIZE SIZE_K(64) + +#define GPIO1_BASE (MMIO_BASE + 0x1730000) +#define GPIO1_SIZE SIZE_K(64) + +#define CRUS_BASE (MMIO_BASE + 0x1750000) +#define CRUS_SIZE SIZE_K(128) + +#define GRF_BASE (MMIO_BASE + 0x1770000) +#define GRF_SIZE SIZE_K(64) + +#define GPIO2_BASE (MMIO_BASE + 0x1780000) +#define GPIO2_SIZE SIZE_K(32) + +#define GPIO3_BASE (MMIO_BASE + 0x1788000) +#define GPIO3_SIZE SIZE_K(32) + +#define GPIO4_BASE (MMIO_BASE + 0x1790000) +#define GPIO4_SIZE SIZE_K(32) + +#define STIME_BASE (MMIO_BASE + 0x1860000) +#define STIME_SIZE SIZE_K(64) + +#define SRAM_BASE (MMIO_BASE + 0x18c0000) +#define SRAM_SIZE SIZE_K(192) + +#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x1a50000) +#define NOC_0_SIZE SIZE_K(192) + +#define DDRC0_BASE (MMIO_BASE + 0x1a80000) +#define DDRC0_SIZE SIZE_K(32) + +#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x1a84000) +#define NOC_1_SIZE SIZE_K(16) + +#define DDRC1_BASE (MMIO_BASE + 0x1a88000) +#define DDRC1_SIZE SIZE_K(32) + +#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x1a8c000) +#define NOC_2_SIZE SIZE_K(16) + +#define SERVICE_NOC_3_BASE (MMIO_BASE + 0x1a90000) +#define NOC_3_SIZE SIZE_K(448) + +#define CCI500_BASE (MMIO_BASE + 0x1b00000) +#define CCI500_SIZE SIZE_M(1) + +#define DDR_PI_OFFSET 0x800 +#define DDR_PHY_OFFSET 0x2000 + +#define DDRC0_PI_BASE (DDRC0_BASE + DDR_PI_OFFSET) +#define DDRC0_PHY_BASE (DDRC0_BASE + DDR_PHY_OFFSET) +#define DDRC1_PI_BASE (DDRC1_BASE + DDR_PI_OFFSET) +#define DDRC1_PHY_BASE (DDRC1_BASE + DDR_PHY_OFFSET) + +/* Aggregate of all devices in the first GB */ +#define RK3399_DEV_RNG0_BASE MMIO_BASE +#define RK3399_DEV_RNG0_SIZE 0x1d00000 + +/* + * include i2c pmu/audio, pwm0-3 rkpwm0-3 uart_dbg,mailbox scr + * 0xff650000 -0xff6c0000 + */ +#define PD_BUS0_BASE (MMIO_BASE + 0x1650000) +#define PD_BUS0_SIZE SIZE_K(448) + +#define PMUCRU_BASE (MMIO_BASE + 0x1750000) +#define CRU_BASE (MMIO_BASE + 0x1760000) + +#define COLD_BOOT_BASE (MMIO_BASE + 0x1ff0000) + +/************************************************************************** + * UART related constants + **************************************************************************/ +#define RK3399_UART2_BASE (0xff1a0000) +#define RK3399_UART2_SIZE SIZE_K(64) + +#define RK3399_BAUDRATE (115200) +#define RK3399_UART_CLOCK (24000000) + +/****************************************************************************** + * System counter frequency related constants + ******************************************************************************/ +#define SYS_COUNTER_FREQ_IN_TICKS 24000000 + +/* Base rockchip_platform compatible GIC memory map */ +#define BASE_GICD_BASE (GIC500_BASE) +#define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1)) + +/***************************************************************************** + * CCI-400 related constants + ******************************************************************************/ +#define PLAT_RK_CCI_CLUSTER0_SL_IFACE_IX 0 +#define PLAT_RK_CCI_CLUSTER1_SL_IFACE_IX 1 + +/****************************************************************************** + * sgi, ppi + ******************************************************************************/ +#define ARM_IRQ_SEC_PHY_TIMER 29 + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define RK3399_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER +#define RK3399_G0_IRQS ARM_IRQ_SEC_SGI_6 + +#endif /* __PLAT_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/aarch64/zynqmp_common.c new file mode 100644 index 0000000..60a1605 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/aarch64/zynqmp_common.c @@ -0,0 +1,305 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "../zynqmp_private.h" + +/* + * Table of regions to map using the MMU. + * This doesn't include TZRAM as the 'mem_layout' argument passed to + * configure_mmu_elx() will give the available subset of that, + */ +const mmap_region_t plat_arm_mmap[] = { + { DEVICE0_BASE, DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, + { DEVICE1_BASE, DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, + { CRF_APB_BASE, CRF_APB_BASE, CRF_APB_SIZE, MT_DEVICE | MT_RW | MT_SECURE }, + {0} +}; + +static unsigned int zynqmp_get_silicon_ver(void) +{ + unsigned int ver; + + ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET); + ver &= ZYNQMP_SILICON_VER_MASK; + ver >>= ZYNQMP_SILICON_VER_SHIFT; + + return ver; +} + +unsigned int zynqmp_get_uart_clk(void) +{ + unsigned int ver = zynqmp_get_silicon_ver(); + + switch (ver) { + case ZYNQMP_CSU_VERSION_VELOCE: + return 48000; + case ZYNQMP_CSU_VERSION_EP108: + return 25000000; + case ZYNQMP_CSU_VERSION_QEMU: + return 133000000; + } + + return 100000000; +} + +static unsigned int zynqmp_get_system_timer_freq(void) +{ + unsigned int ver = zynqmp_get_silicon_ver(); + + switch (ver) { + case ZYNQMP_CSU_VERSION_VELOCE: + return 10000; + case ZYNQMP_CSU_VERSION_EP108: + return 4000000; + case ZYNQMP_CSU_VERSION_QEMU: + return 50000000; + } + + return 100000000; +} + +unsigned int zynqmp_get_silicon_id(void) +{ + uint32_t id; + + id = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET); + + id &= ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK | ZYNQMP_CSU_IDCODE_SVD_MASK; + id >>= ZYNQMP_CSU_IDCODE_SVD_SHIFT; + + return id; +} + +#if LOG_LEVEL >= LOG_LEVEL_NOTICE +static const struct { + unsigned int id; + char *name; +} zynqmp_devices[] = { + { + .id = 0x10, + .name = "3EG", + }, + { + .id = 0x11, + .name = "2EG", + }, + { + .id = 0x20, + .name = "5EV", + }, + { + .id = 0x21, + .name = "4EV", + }, + { + .id = 0x30, + .name = "7EV", + }, + { + .id = 0x38, + .name = "9EG", + }, + { + .id = 0x39, + .name = "6EG", + }, + { + .id = 0x40, + .name = "11EG", + }, + { + .id = 0x50, + .name = "15EG", + }, + { + .id = 0x58, + .name = "19EG", + }, + { + .id = 0x59, + .name = "17EG", + }, +}; + +static char *zynqmp_get_silicon_idcode_name(void) +{ + unsigned int id; + + id = zynqmp_get_silicon_id(); + for (size_t i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { + if (zynqmp_devices[i].id == id) + return zynqmp_devices[i].name; + } + return "UNKN"; +} + +static unsigned int zynqmp_get_rtl_ver(void) +{ + uint32_t ver; + + ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET); + ver &= ZYNQMP_RTL_VER_MASK; + ver >>= ZYNQMP_RTL_VER_SHIFT; + + return ver; +} + +static char *zynqmp_print_silicon_idcode(void) +{ + uint32_t id, maskid, tmp; + + id = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET); + + tmp = id; + tmp &= ZYNQMP_CSU_IDCODE_XILINX_ID_MASK | + ZYNQMP_CSU_IDCODE_FAMILY_MASK; + maskid = ZYNQMP_CSU_IDCODE_XILINX_ID << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT | + ZYNQMP_CSU_IDCODE_FAMILY << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT; + if (tmp != maskid) { + ERROR("Incorrect XILINX IDCODE 0x%x, maskid 0x%x\n", id, maskid); + return "UNKN"; + } + VERBOSE("Xilinx IDCODE 0x%x\n", id); + return zynqmp_get_silicon_idcode_name(); +} + +static unsigned int zynqmp_get_ps_ver(void) +{ + uint32_t ver = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_VERSION_OFFSET); + + ver &= ZYNQMP_PS_VER_MASK; + ver >>= ZYNQMP_PS_VER_SHIFT; + + return ver + 1; +} + +static void zynqmp_print_platform_name(void) +{ + unsigned int ver = zynqmp_get_silicon_ver(); + unsigned int rtl = zynqmp_get_rtl_ver(); + char *label = "Unknown"; + + switch (ver) { + case ZYNQMP_CSU_VERSION_VELOCE: + label = "VELOCE"; + break; + case ZYNQMP_CSU_VERSION_EP108: + label = "EP108"; + break; + case ZYNQMP_CSU_VERSION_QEMU: + label = "QEMU"; + break; + case ZYNQMP_CSU_VERSION_SILICON: + label = "silicon"; + break; + } + + NOTICE("ATF running on XCZU%s/%s v%d/RTL%d.%d at 0x%x%s\n", + zynqmp_print_silicon_idcode(), label, zynqmp_get_ps_ver(), + (rtl & 0xf0) >> 4, rtl & 0xf, BL31_BASE, + zynqmp_is_pmu_up() ? ", with PMU firmware" : ""); +} +#else +static inline void zynqmp_print_platform_name(void) { } +#endif + +/* + * Indicator for PMUFW discovery: + * 0 = No FW found + * non-zero = FW is present + */ +static int zynqmp_pmufw_present; + +/* + * zynqmp_discover_pmufw - Discover presence of PMUFW + * + * Discover the presence of PMUFW and store it for later run-time queries + * through zynqmp_is_pmu_up. + * NOTE: This discovery method is fragile and will break if: + * - setting FW_PRESENT is done by PMUFW itself and could be left out in PMUFW + * (be it by error or intentionally) + * - XPPU/XMPU may restrict ATF's access to the PMU address space + */ +static int zynqmp_discover_pmufw(void) +{ + zynqmp_pmufw_present = mmio_read_32(PMU_GLOBAL_CNTRL); + zynqmp_pmufw_present &= PMU_GLOBAL_CNTRL_FW_IS_PRESENT; + + return !!zynqmp_pmufw_present; +} + +/* + * zynqmp_is_pmu_up - Find if PMU firmware is up and running + * + * Return 0 if firmware is not available, non 0 otherwise + */ +int zynqmp_is_pmu_up(void) +{ + return zynqmp_pmufw_present; +} + +unsigned int zynqmp_get_bootmode(void) +{ + uint32_t r = mmio_read_32(CRL_APB_BOOT_MODE_USER); + + return r & CRL_APB_BOOT_MODE_MASK; +} + +void zynqmp_config_setup(void) +{ + zynqmp_discover_pmufw(); + zynqmp_print_platform_name(); + + /* Global timer init - Program time stamp reference clk */ + uint32_t val = mmio_read_32(CRL_APB_TIMESTAMP_REF_CTRL); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + mmio_write_32(CRL_APB_TIMESTAMP_REF_CTRL, val); + + /* Program freq register in System counter and enable system counter. */ + mmio_write_32(IOU_SCNTRS_BASEFREQ, zynqmp_get_system_timer_freq()); + mmio_write_32(IOU_SCNTRS_CONTROL, IOU_SCNTRS_CONTROL_EN); + + generic_delay_timer_init(); +} + +unsigned int plat_get_syscnt_freq2(void) +{ + unsigned int counter_base_frequency; + + /* FIXME: Read the frequency from Frequency modes table */ + counter_base_frequency = zynqmp_get_system_timer_freq(); + + return counter_base_frequency; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S new file mode 100644 index 0000000..0afed47 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + + .globl plat_secondary_cold_boot_setup + .globl plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * TODO: Should we read the PSYS register to make sure + * that the request has gone through. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + mrs x0, mpidr_el1 + + /* Deactivate the gic cpu interface */ + ldr x1, =BASE_GICC_BASE + mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1) + orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0) + str w0, [x1, #GICC_CTLR] + + /* + * There is no sane reason to come out of this wfi. This + * cpu will be powered on and reset by the cpu_on pm api + */ + dsb sy +1: + bl plat_panic_handler +endfunc plat_secondary_cold_boot_setup + +func plat_is_my_cpu_primary + mov x9, x30 + bl plat_my_core_pos + cmp x0, #ZYNQMP_PRIMARY_CPU + cset x0, eq + ret x9 +endfunc plat_is_my_cpu_primary diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/bl31_zynqmp_setup.c new file mode 100644 index 0000000..c05b094 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/bl31_zynqmp_setup.c @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "zynqmp_private.h" + +#define BL31_END (unsigned long)(&__BL31_END__) + +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols + * refer to page-aligned addresses. + */ +#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) + +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + +/* + * Return a pointer to the 'entry_point_info' structure of the next image for + * the security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + */ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + assert(sec_state_is_valid(type)); + + if (type == NON_SECURE) + return &bl33_image_ep_info; + + return &bl32_image_ep_info; +} + +/* + * Perform any BL31 specific platform actions. Here is an opportunity to copy + * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they + * are lost (potentially). This needs to be done before the MMU is initialized + * so that the memory layout can be used while creating page tables. + */ +void bl31_early_platform_setup(bl31_params_t *from_bl2, + void *plat_params_from_bl2) +{ + /* Initialize the console to provide early debug support */ + console_init(ZYNQMP_UART_BASE, zynqmp_get_uart_clk(), + ZYNQMP_UART_BAUDRATE); + + /* Initialize the platform config for future decision making */ + zynqmp_config_setup(); + + /* There are no parameters from BL2 if BL31 is a reset vector */ + assert(from_bl2 == NULL); + assert(plat_params_from_bl2 == NULL); + + /* + * Do initial security configuration to allow DRAM/device access. On + * Base ZYNQMP only DRAM security is programmable (via TrustZone), but + * other platforms might have more programmable security devices + * present. + */ + + /* Populate common information for BL32 and BL33 */ + SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + + if (zynqmp_get_bootmode() == ZYNQMP_BOOTMODE_JTAG) { + /* use build time defaults in JTAG boot mode */ + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); + bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); + bl33_image_ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + } else { + /* use parameters from FSBL */ + fsbl_atf_handover(&bl32_image_ep_info, &bl33_image_ep_info); + } + + NOTICE("BL31: Secure code at 0x%lx\n", bl32_image_ep_info.pc); + NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc); +} + +/* Enable the test setup */ +#ifndef ZYNQMP_TESTING +static void zynqmp_testing_setup(void) { } +#else +static void zynqmp_testing_setup(void) +{ + uint32_t actlr_el3, actlr_el2; + + /* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */ + actlr_el3 = read_actlr_el3(); + actlr_el2 = read_actlr_el2(); + + actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; + actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT; + write_actlr_el3(actlr_el3); + write_actlr_el2(actlr_el2); +} +#endif + +void bl31_platform_setup(void) +{ + /* Initialize the gic cpu and distributor interfaces */ + plat_arm_gic_driver_init(); + plat_arm_gic_init(); + zynqmp_testing_setup(); +} + +void bl31_plat_runtime_setup(void) +{ +} + +/* + * Perform the very early platform specific architectural setup here. + */ +void bl31_plat_arch_setup(void) +{ + plat_arm_interconnect_init(); + plat_arm_interconnect_enter_coherency(); + + arm_setup_page_tables(BL31_BASE, + BL31_END - BL31_BASE, + BL_CODE_BASE, + BL_CODE_LIMIT, + BL_RO_DATA_BASE, + BL_RO_DATA_LIMIT, + BL31_COHERENT_RAM_BASE, + BL31_COHERENT_RAM_LIMIT); + enable_mmu_el3(0); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/include/plat_macros.S b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/include/plat_macros.S new file mode 100644 index 0000000..f40beba --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/include/plat_macros.S @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __PLAT_MACROS_S__ +#define __PLAT_MACROS_S__ + +#include +#include +#include "../zynqmp_def.h" + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + mov_imm x17, BASE_GICC_BASE + mov_imm x16, BASE_GICD_BASE + arm_print_gic_regs + print_cci_regs + .endm + +#endif /* __PLAT_MACROS_S__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/include/platform_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/include/platform_def.h new file mode 100644 index 0000000..3c1a9e5 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/include/platform_def.h @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +#include +#include "../zynqmp_def.h" + +/******************************************************************************* + * Generic platform constants + ******************************************************************************/ + +/* Size of cacheable stacks */ +#define PLATFORM_STACK_SIZE 0x440 + +#define PLATFORM_CORE_COUNT 4 +#define PLAT_NUM_POWER_DOMAINS 5 +#define PLAT_MAX_PWR_LVL 1 +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE 2 + +/******************************************************************************* + * BL31 specific defines. + ******************************************************************************/ +/* + * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if + * present). BL31_BASE is calculated using the current BL31 debug size plus a + * little space for growth. + */ +#ifndef ZYNQMP_ATF_MEM_BASE +# define BL31_BASE 0xfffea000 +# define BL31_LIMIT 0xffffffff +#else +# define BL31_BASE (ZYNQMP_ATF_MEM_BASE) +# define BL31_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_SIZE - 1) +# ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE +# define BL31_PROGBITS_LIMIT (ZYNQMP_ATF_MEM_BASE + ZYNQMP_ATF_MEM_PROGBITS_SIZE - 1) +# endif +#endif + +/******************************************************************************* + * BL32 specific defines. + ******************************************************************************/ +#ifndef ZYNQMP_BL32_MEM_BASE +# define BL32_BASE 0x60000000 +# define BL32_LIMIT 0x7fffffff +#else +# define BL32_BASE (ZYNQMP_BL32_MEM_BASE) +# define BL32_LIMIT (ZYNQMP_BL32_MEM_BASE + ZYNQMP_BL32_MEM_SIZE - 1) +#endif + +/******************************************************************************* + * BL33 specific defines. + ******************************************************************************/ +#ifndef PRELOADED_BL33_BASE +# define PLAT_ARM_NS_IMAGE_OFFSET 0x8000000 +#else +# define PLAT_ARM_NS_IMAGE_OFFSET PRELOADED_BL33_BASE +#endif + +/******************************************************************************* + * TSP specific defines. + ******************************************************************************/ +#define TSP_SEC_MEM_BASE BL32_BASE +#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1) + +/* ID of the secure physical generic timer interrupt used by the TSP */ +#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER + +/******************************************************************************* + * Platform specific page table and MMU setup constants + ******************************************************************************/ +#define ADDR_SPACE_SIZE (1ull << 32) +#define MAX_MMAP_REGIONS 7 +#define MAX_XLAT_TABLES 5 + +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#define PLAT_ARM_GICD_BASE BASE_GICD_BASE +#define PLAT_ARM_GICC_BASE BASE_GICC_BASE +/* + * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 + * terminology. On a GICv2 system or mode, the lists will be merged and treated + * as Group 0 interrupts. + */ +#define PLAT_ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ + IRQ_SEC_IPI_APU, \ + ARM_IRQ_SEC_SGI_0, \ + ARM_IRQ_SEC_SGI_1, \ + ARM_IRQ_SEC_SGI_2, \ + ARM_IRQ_SEC_SGI_3, \ + ARM_IRQ_SEC_SGI_4, \ + ARM_IRQ_SEC_SGI_5, \ + ARM_IRQ_SEC_SGI_6, \ + ARM_IRQ_SEC_SGI_7 + +#define PLAT_ARM_G0_IRQS + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/plat_psci.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/plat_psci.c new file mode 100644 index 0000000..55227ea --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/plat_psci.c @@ -0,0 +1,394 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pm_api_sys.h" +#include "pm_client.h" +#include "zynqmp_private.h" + +uintptr_t zynqmp_sec_entry; + +void zynqmp_cpu_standby(plat_local_state_t cpu_state) +{ + VERBOSE("%s: cpu_state: 0x%x\n", __func__, cpu_state); + + dsb(); + wfi(); +} + +static int zynqmp_nopmu_pwr_domain_on(u_register_t mpidr) +{ + uint32_t r; + unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); + + VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); + + if (cpu_id == -1) + return PSCI_E_INTERN_FAIL; + + /* program RVBAR */ + mmio_write_32(APU_RVBAR_L_0 + (cpu_id << 3), zynqmp_sec_entry); + mmio_write_32(APU_RVBAR_H_0 + (cpu_id << 3), zynqmp_sec_entry >> 32); + + /* clear VINITHI */ + r = mmio_read_32(APU_CONFIG_0); + r &= ~(1 << APU_CONFIG_0_VINITHI_SHIFT << cpu_id); + mmio_write_32(APU_CONFIG_0, r); + + /* clear power down request */ + r = mmio_read_32(APU_PWRCTL); + r &= ~(1 << cpu_id); + mmio_write_32(APU_PWRCTL, r); + + /* power up island */ + mmio_write_32(PMU_GLOBAL_REQ_PWRUP_EN, 1 << cpu_id); + mmio_write_32(PMU_GLOBAL_REQ_PWRUP_TRIG, 1 << cpu_id); + /* FIXME: we should have a way to break out */ + while (mmio_read_32(PMU_GLOBAL_REQ_PWRUP_STATUS) & (1 << cpu_id)) + ; + + /* release core reset */ + r = mmio_read_32(CRF_APB_RST_FPD_APU); + r &= ~((CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET | + CRF_APB_RST_FPD_APU_ACPU_RESET) << cpu_id); + mmio_write_32(CRF_APB_RST_FPD_APU, r); + + return PSCI_E_SUCCESS; +} + +static int zynqmp_pwr_domain_on(u_register_t mpidr) +{ + unsigned int cpu_id = plat_core_pos_by_mpidr(mpidr); + const struct pm_proc *proc; + + VERBOSE("%s: mpidr: 0x%lx\n", __func__, mpidr); + + if (cpu_id == -1) + return PSCI_E_INTERN_FAIL; + + proc = pm_get_proc(cpu_id); + + /* Send request to PMU to wake up selected APU CPU core */ + pm_req_wakeup(proc->node_id, 1, zynqmp_sec_entry, REQ_ACK_BLOCKING); + + return PSCI_E_SUCCESS; +} + +static void zynqmp_nopmu_pwr_domain_off(const psci_power_state_t *target_state) +{ + uint32_t r; + unsigned int cpu_id = plat_my_core_pos(); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + /* Prevent interrupts from spuriously waking up this cpu */ + gicv2_cpuif_disable(); + + /* set power down request */ + r = mmio_read_32(APU_PWRCTL); + r |= (1 << cpu_id); + mmio_write_32(APU_PWRCTL, r); +} + +static void zynqmp_pwr_domain_off(const psci_power_state_t *target_state) +{ + unsigned int cpu_id = plat_my_core_pos(); + const struct pm_proc *proc = pm_get_proc(cpu_id); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + /* Prevent interrupts from spuriously waking up this cpu */ + gicv2_cpuif_disable(); + + /* + * Send request to PMU to power down the appropriate APU CPU + * core. + * According to PSCI specification, CPU_off function does not + * have resume address and CPU core can only be woken up + * invoking CPU_on function, during which resume address will + * be set. + */ + pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0); +} + +static void zynqmp_nopmu_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + uint32_t r; + unsigned int cpu_id = plat_my_core_pos(); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + /* set power down request */ + r = mmio_read_32(APU_PWRCTL); + r |= (1 << cpu_id); + mmio_write_32(APU_PWRCTL, r); + + /* program RVBAR */ + mmio_write_32(APU_RVBAR_L_0 + (cpu_id << 3), zynqmp_sec_entry); + mmio_write_32(APU_RVBAR_H_0 + (cpu_id << 3), zynqmp_sec_entry >> 32); + + /* clear VINITHI */ + r = mmio_read_32(APU_CONFIG_0); + r &= ~(1 << APU_CONFIG_0_VINITHI_SHIFT << cpu_id); + mmio_write_32(APU_CONFIG_0, r); + + /* enable power up on IRQ */ + mmio_write_32(PMU_GLOBAL_REQ_PWRUP_EN, 1 << cpu_id); +} + +static void zynqmp_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + unsigned int state; + unsigned int cpu_id = plat_my_core_pos(); + const struct pm_proc *proc = pm_get_proc(cpu_id); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + state = target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE ? + PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE; + + /* Send request to PMU to suspend this core */ + pm_self_suspend(proc->node_id, MAX_LATENCY, state, zynqmp_sec_entry); + + /* APU is to be turned off */ + if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { + /* disable coherency */ + plat_arm_interconnect_exit_coherency(); + } +} + +static void zynqmp_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + gicv2_cpuif_enable(); + gicv2_pcpu_distif_init(); +} + +static void zynqmp_nopmu_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ + uint32_t r; + unsigned int cpu_id = plat_my_core_pos(); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + /* disable power up on IRQ */ + mmio_write_32(PMU_GLOBAL_REQ_PWRUP_DIS, 1 << cpu_id); + + /* clear powerdown bit */ + r = mmio_read_32(APU_PWRCTL); + r &= ~(1 << cpu_id); + mmio_write_32(APU_PWRCTL, r); +} + +static void zynqmp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ + unsigned int cpu_id = plat_my_core_pos(); + const struct pm_proc *proc = pm_get_proc(cpu_id); + + for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) + VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", + __func__, i, target_state->pwr_domain_state[i]); + + /* Clear the APU power control register for this cpu */ + pm_client_wakeup(proc); + + /* enable coherency */ + plat_arm_interconnect_enter_coherency(); + /* APU was turned off */ + if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) { + plat_arm_gic_init(); + } else { + gicv2_cpuif_enable(); + gicv2_pcpu_distif_init(); + } +} + +/******************************************************************************* + * ZynqMP handlers to shutdown/reboot the system + ******************************************************************************/ +static void __dead2 zynqmp_nopmu_system_off(void) +{ + ERROR("ZynqMP System Off: operation not handled.\n"); + + /* disable coherency */ + plat_arm_interconnect_exit_coherency(); + + panic(); +} + +static void __dead2 zynqmp_system_off(void) +{ + /* disable coherency */ + plat_arm_interconnect_exit_coherency(); + + /* Send the power down request to the PMU */ + pm_system_shutdown(0); + + while (1) + wfi(); +} + +static void __dead2 zynqmp_nopmu_system_reset(void) +{ + /* + * This currently triggers a system reset. I.e. the whole + * system will be reset! Including RPUs, PMU, PL, etc. + */ + + /* disable coherency */ + plat_arm_interconnect_exit_coherency(); + + /* bypass RPLL (needed on 1.0 silicon) */ + uint32_t reg = mmio_read_32(CRL_APB_RPLL_CTRL); + reg |= CRL_APB_RPLL_CTRL_BYPASS; + mmio_write_32(CRL_APB_RPLL_CTRL, reg); + + /* trigger system reset */ + mmio_write_32(CRL_APB_RESET_CTRL, CRL_APB_RESET_CTRL_SOFT_RESET); + + while (1) + wfi(); +} + +static void __dead2 zynqmp_system_reset(void) +{ + /* disable coherency */ + plat_arm_interconnect_exit_coherency(); + + /* Send the system reset request to the PMU */ + pm_system_shutdown(1); + + while (1) + wfi(); +} + +int zynqmp_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + VERBOSE("%s: power_state: 0x%x\n", __func__, power_state); + + int pstate = psci_get_pstate_type(power_state); + + assert(req_state); + + /* Sanity check the requested state */ + if (pstate == PSTATE_TYPE_STANDBY) + req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; + else + req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; + + /* We expect the 'state id' to be zero */ + if (psci_get_pstate_id(power_state)) + return PSCI_E_INVALID_PARAMS; + + return PSCI_E_SUCCESS; +} + +int zynqmp_validate_ns_entrypoint(unsigned long ns_entrypoint) +{ + VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint); + + /* FIXME: Actually validate */ + return PSCI_E_SUCCESS; +} + +void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; + req_state->pwr_domain_state[1] = PLAT_MAX_OFF_STATE; +} + +/******************************************************************************* + * Export the platform handlers to enable psci to invoke them + ******************************************************************************/ +static const struct plat_psci_ops zynqmp_psci_ops = { + .cpu_standby = zynqmp_cpu_standby, + .pwr_domain_on = zynqmp_pwr_domain_on, + .pwr_domain_off = zynqmp_pwr_domain_off, + .pwr_domain_suspend = zynqmp_pwr_domain_suspend, + .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish, + .pwr_domain_suspend_finish = zynqmp_pwr_domain_suspend_finish, + .system_off = zynqmp_system_off, + .system_reset = zynqmp_system_reset, + .validate_power_state = zynqmp_validate_power_state, + .validate_ns_entrypoint = zynqmp_validate_ns_entrypoint, + .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state, +}; + +static const struct plat_psci_ops zynqmp_nopmu_psci_ops = { + .cpu_standby = zynqmp_cpu_standby, + .pwr_domain_on = zynqmp_nopmu_pwr_domain_on, + .pwr_domain_off = zynqmp_nopmu_pwr_domain_off, + .pwr_domain_suspend = zynqmp_nopmu_pwr_domain_suspend, + .pwr_domain_on_finish = zynqmp_pwr_domain_on_finish, + .pwr_domain_suspend_finish = zynqmp_nopmu_pwr_domain_suspend_finish, + .system_off = zynqmp_nopmu_system_off, + .system_reset = zynqmp_nopmu_system_reset, + .validate_power_state = zynqmp_validate_power_state, + .validate_ns_entrypoint = zynqmp_validate_ns_entrypoint, + .get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state, +}; + +/******************************************************************************* + * Export the platform specific power ops. + ******************************************************************************/ +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const struct plat_psci_ops **psci_ops) +{ + zynqmp_sec_entry = sec_entrypoint; + + if (zynqmp_is_pmu_up()) + *psci_ops = &zynqmp_psci_ops; + else + *psci_ops = &zynqmp_nopmu_psci_ops; + + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/plat_startup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/plat_startup.c new file mode 100644 index 0000000..c2c9bfb --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/plat_startup.c @@ -0,0 +1,288 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "zynqmp_def.h" + +/* + * ATFHandoffParams + * Parameter bitfield encoding + * ----------------------------------------------------------------------------- + * Exec State 0 0 -> Aarch64, 1-> Aarch32 + * endianness 1 0 -> LE, 1 -> BE + * secure (TZ) 2 0 -> Non secure, 1 -> secure + * EL 3:4 00 -> EL0, 01 -> EL1, 10 -> EL2, 11 -> EL3 + * CPU# 5:6 00 -> A53_0, 01 -> A53_1, 10 -> A53_2, 11 -> A53_3 + */ + +#define FSBL_FLAGS_ESTATE_SHIFT 0 +#define FSBL_FLAGS_ESTATE_MASK (1 << FSBL_FLAGS_ESTATE_SHIFT) +#define FSBL_FLAGS_ESTATE_A64 0 +#define FSBL_FLAGS_ESTATE_A32 1 + +#define FSBL_FLAGS_ENDIAN_SHIFT 1 +#define FSBL_FLAGS_ENDIAN_MASK (1 << FSBL_FLAGS_ENDIAN_SHIFT) +#define FSBL_FLAGS_ENDIAN_LE 0 +#define FSBL_FLAGS_ENDIAN_BE 1 + +#define FSBL_FLAGS_TZ_SHIFT 2 +#define FSBL_FLAGS_TZ_MASK (1 << FSBL_FLAGS_TZ_SHIFT) +#define FSBL_FLAGS_NON_SECURE 0 +#define FSBL_FLAGS_SECURE 1 + +#define FSBL_FLAGS_EL_SHIFT 3 +#define FSBL_FLAGS_EL_MASK (3 << FSBL_FLAGS_EL_SHIFT) +#define FSBL_FLAGS_EL0 0 +#define FSBL_FLAGS_EL1 1 +#define FSBL_FLAGS_EL2 2 +#define FSBL_FLAGS_EL3 3 + +#define FSBL_FLAGS_CPU_SHIFT 5 +#define FSBL_FLAGS_CPU_MASK (3 << FSBL_FLAGS_CPU_SHIFT) +#define FSBL_FLAGS_A53_0 0 +#define FSBL_FLAGS_A53_1 1 +#define FSBL_FLAGS_A53_2 2 +#define FSBL_FLAGS_A53_3 3 + +#define FSBL_MAX_PARTITIONS 8 + +/* Structure corresponding to each partition entry */ +struct xfsbl_partition { + uint64_t entry_point; + uint64_t flags; +}; + +/* Structure for handoff parameters to ARM Trusted Firmware (ATF) */ +struct xfsbl_atf_handoff_params { + uint8_t magic[4]; + uint32_t num_entries; + struct xfsbl_partition partition[FSBL_MAX_PARTITIONS]; +}; + +/** + * @partition: Pointer to partition struct + * + * Get the target CPU for @partition. + * + * Return: FSBL_FLAGS_A53_0, FSBL_FLAGS_A53_1, FSBL_FLAGS_A53_2 or FSBL_FLAGS_A53_3 + */ +static int get_fsbl_cpu(const struct xfsbl_partition *partition) +{ + uint64_t flags = partition->flags & FSBL_FLAGS_CPU_MASK; + + return flags >> FSBL_FLAGS_CPU_SHIFT; +} + +/** + * @partition: Pointer to partition struct + * + * Get the target exception level for @partition. + * + * Return: FSBL_FLAGS_EL0, FSBL_FLAGS_EL1, FSBL_FLAGS_EL2 or FSBL_FLAGS_EL3 + */ +static int get_fsbl_el(const struct xfsbl_partition *partition) +{ + uint64_t flags = partition->flags & FSBL_FLAGS_EL_MASK; + + return flags >> FSBL_FLAGS_EL_SHIFT; +} + +/** + * @partition: Pointer to partition struct + * + * Get the target security state for @partition. + * + * Return: FSBL_FLAGS_NON_SECURE or FSBL_FLAGS_SECURE + */ +static int get_fsbl_ss(const struct xfsbl_partition *partition) +{ + uint64_t flags = partition->flags & FSBL_FLAGS_TZ_MASK; + + return flags >> FSBL_FLAGS_TZ_SHIFT; +} + +/** + * @partition: Pointer to partition struct + * + * Get the target endianness for @partition. + * + * Return: SPSR_E_LITTLE or SPSR_E_BIG + */ +static int get_fsbl_endian(const struct xfsbl_partition *partition) +{ + uint64_t flags = partition->flags & FSBL_FLAGS_ENDIAN_MASK; + + flags >>= FSBL_FLAGS_ENDIAN_SHIFT; + + if (flags == FSBL_FLAGS_ENDIAN_BE) + return SPSR_E_BIG; + else + return SPSR_E_LITTLE; +} + +/** + * @partition: Pointer to partition struct + * + * Get the target execution state for @partition. + * + * Return: FSBL_FLAGS_ESTATE_A32 or FSBL_FLAGS_ESTATE_A64 + */ +static int get_fsbl_estate(const struct xfsbl_partition *partition) +{ + uint64_t flags = partition->flags & FSBL_FLAGS_ESTATE_MASK; + + return flags >> FSBL_FLAGS_ESTATE_SHIFT; +} + +/** + * Populates the bl32 and bl33 image info structures + * @bl32: BL32 image info structure + * @bl33: BL33 image info structure + * + * Process the handoff paramters from the FSBL and populate the BL32 and BL33 + * image info structures accordingly. + */ +void fsbl_atf_handover(entry_point_info_t *bl32, entry_point_info_t *bl33) +{ + uint64_t atf_handoff_addr; + const struct xfsbl_atf_handoff_params *ATFHandoffParams; + + atf_handoff_addr = mmio_read_32(PMU_GLOBAL_GEN_STORAGE6); + assert((atf_handoff_addr < BL31_BASE) || + (atf_handoff_addr > (uint64_t)&__BL31_END__)); + if (!atf_handoff_addr) { + ERROR("BL31: No ATF handoff structure passed\n"); + panic(); + } + + ATFHandoffParams = (struct xfsbl_atf_handoff_params *)atf_handoff_addr; + if ((ATFHandoffParams->magic[0] != 'X') || + (ATFHandoffParams->magic[1] != 'L') || + (ATFHandoffParams->magic[2] != 'N') || + (ATFHandoffParams->magic[3] != 'X')) { + ERROR("BL31: invalid ATF handoff structure at %lx\n", + atf_handoff_addr); + panic(); + } + + VERBOSE("BL31: ATF handoff params at:0x%lx, entries:%u\n", + atf_handoff_addr, ATFHandoffParams->num_entries); + if (ATFHandoffParams->num_entries > FSBL_MAX_PARTITIONS) { + ERROR("BL31: ATF handoff params: too many partitions (%u/%u)\n", + ATFHandoffParams->num_entries, FSBL_MAX_PARTITIONS); + panic(); + } + + /* + * we loop over all passed entries but only populate two image structs + * (bl32, bl33). I.e. the last applicable images in the handoff + * structure will be used for the hand off + */ + for (size_t i = 0; i < ATFHandoffParams->num_entries; i++) { + entry_point_info_t *image; + int target_estate, target_secure; + int target_cpu, target_endianness, target_el; + + VERBOSE("BL31: %zd: entry:0x%lx, flags:0x%lx\n", i, + ATFHandoffParams->partition[i].entry_point, + ATFHandoffParams->partition[i].flags); + + target_cpu = get_fsbl_cpu(&ATFHandoffParams->partition[i]); + if (target_cpu != FSBL_FLAGS_A53_0) { + WARN("BL31: invalid target CPU (%i)\n", target_cpu); + continue; + } + + target_el = get_fsbl_el(&ATFHandoffParams->partition[i]); + if ((target_el == FSBL_FLAGS_EL3) || + (target_el == FSBL_FLAGS_EL0)) { + WARN("BL31: invalid exception level (%i)\n", target_el); + continue; + } + + target_secure = get_fsbl_ss(&ATFHandoffParams->partition[i]); + if (target_secure == FSBL_FLAGS_SECURE && + target_el == FSBL_FLAGS_EL2) { + WARN("BL31: invalid security state (%i) for exception level (%i)\n", + target_secure, target_el); + continue; + } + + target_estate = get_fsbl_estate(&ATFHandoffParams->partition[i]); + target_endianness = get_fsbl_endian(&ATFHandoffParams->partition[i]); + + if (target_secure == FSBL_FLAGS_SECURE) { + image = bl32; + + if (target_estate == FSBL_FLAGS_ESTATE_A32) + bl32->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, + target_endianness, + DISABLE_ALL_EXCEPTIONS); + else + bl32->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + } else { + image = bl33; + + if (target_estate == FSBL_FLAGS_ESTATE_A32) { + if (target_el == FSBL_FLAGS_EL2) + target_el = MODE32_hyp; + else + target_el = MODE32_sys; + + bl33->spsr = SPSR_MODE32(target_el, SPSR_T_ARM, + target_endianness, + DISABLE_ALL_EXCEPTIONS); + } else { + if (target_el == FSBL_FLAGS_EL2) + target_el = MODE_EL2; + else + target_el = MODE_EL1; + + bl33->spsr = SPSR_64(target_el, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + } + } + + VERBOSE("Setting up %s entry point to:%lx, el:%x\n", + target_secure == FSBL_FLAGS_SECURE ? "BL32" : "BL33", + ATFHandoffParams->partition[i].entry_point, + target_el); + image->pc = ATFHandoffParams->partition[i].entry_point; + + if (target_endianness == SPSR_E_BIG) + EP_SET_EE(image->h.attr, EP_EE_BIG); + else + EP_SET_EE(image->h.attr, EP_EE_LITTLE); + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/plat_topology.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/plat_topology.c new file mode 100644 index 0000000..e1263e0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/plat_topology.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +static const unsigned char plat_power_domain_tree_desc[] = {1, 4}; + +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return plat_power_domain_tree_desc; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/plat_zynqmp.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/plat_zynqmp.c new file mode 100644 index 0000000..38fa20f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/plat_zynqmp.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + if (mpidr & MPIDR_CLUSTER_MASK) + return -1; + + if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT) + return -1; + + return plat_arm_calc_core_pos(mpidr); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/platform.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/platform.mk new file mode 100644 index 0000000..33c55a0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/platform.mk @@ -0,0 +1,102 @@ +# Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. + +ENABLE_PLAT_COMPAT := 0 +PROGRAMMABLE_RESET_ADDRESS := 1 +PSCI_EXTENDED_STATE_ID := 1 +A53_DISABLE_NON_TEMPORAL_HINT := 0 +SEPARATE_CODE_AND_RODATA := 1 +RESET_TO_BL31 := 1 + +ifdef ZYNQMP_ATF_MEM_BASE + $(eval $(call add_define,ZYNQMP_ATF_MEM_BASE)) + + ifndef ZYNQMP_ATF_MEM_SIZE + $(error "ZYNQMP_ATF_BASE defined without ZYNQMP_ATF_SIZE") + endif + $(eval $(call add_define,ZYNQMP_ATF_MEM_SIZE)) + + ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE + $(eval $(call add_define,ZYNQMP_ATF_MEM_PROGBITS_SIZE)) + endif +endif + +ifdef ZYNQMP_BL32_MEM_BASE + $(eval $(call add_define,ZYNQMP_BL32_MEM_BASE)) + + ifndef ZYNQMP_BL32_MEM_SIZE + $(error "ZYNQMP_BL32_BASE defined without ZYNQMP_BL32_SIZE") + endif + $(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE)) +endif + +ZYNQMP_CONSOLE ?= cadence +$(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE})) + +PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ + -Iinclude/plat/arm/common/aarch64/ \ + -Iplat/xilinx/zynqmp/include/ \ + -Iplat/xilinx/zynqmp/pm_service/ + +PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \ + lib/xlat_tables/aarch64/xlat_tables.c \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + drivers/arm/gic/common/gic_common.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/v2/gicv2_helpers.c \ + drivers/cadence/uart/aarch64/cdns_console.S \ + drivers/console/aarch64/console.S \ + plat/arm/common/aarch64/arm_helpers.S \ + plat/arm/common/arm_cci.c \ + plat/arm/common/arm_common.c \ + plat/arm/common/arm_gicv2.c \ + plat/common/plat_gicv2.c \ + plat/common/aarch64/plat_common.c \ + plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \ + plat/xilinx/zynqmp/aarch64/zynqmp_common.c + +BL31_SOURCES += drivers/arm/cci/cci.c \ + lib/cpus/aarch64/aem_generic.S \ + lib/cpus/aarch64/cortex_a53.S \ + plat/common/plat_psci_common.c \ + plat/common/aarch64/platform_mp_stack.S \ + plat/xilinx/zynqmp/bl31_zynqmp_setup.c \ + plat/xilinx/zynqmp/plat_psci.c \ + plat/xilinx/zynqmp/plat_zynqmp.c \ + plat/xilinx/zynqmp/plat_startup.c \ + plat/xilinx/zynqmp/plat_topology.c \ + plat/xilinx/zynqmp/sip_svc_setup.c \ + plat/xilinx/zynqmp/pm_service/pm_svc_main.c \ + plat/xilinx/zynqmp/pm_service/pm_api_sys.c \ + plat/xilinx/zynqmp/pm_service/pm_ipi.c \ + plat/xilinx/zynqmp/pm_service/pm_client.c + +ifneq (${RESET_TO_BL31},1) + $(error "Using BL31 as the reset vector is only one option supported on ZynqMP. Please set RESET_TO_BL31 to 1.") +endif diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_sys.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_sys.c new file mode 100644 index 0000000..e859ee3 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_sys.c @@ -0,0 +1,543 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * ZynqMP system level PM-API functions and communication with PMU via + * IPI interrupts + */ + +#include +#include +#include "pm_client.h" +#include "pm_ipi.h" +#include "pm_common.h" +#include "pm_api_sys.h" + +/** + * Assigning of argument values into array elements. + */ +#define PM_PACK_PAYLOAD1(pl, arg0) { \ + pl[0] = (uint32_t)(arg0); \ +} + +#define PM_PACK_PAYLOAD2(pl, arg0, arg1) { \ + pl[1] = (uint32_t)(arg1); \ + PM_PACK_PAYLOAD1(pl, arg0); \ +} + +#define PM_PACK_PAYLOAD3(pl, arg0, arg1, arg2) { \ + pl[2] = (uint32_t)(arg2); \ + PM_PACK_PAYLOAD2(pl, arg0, arg1); \ +} + +#define PM_PACK_PAYLOAD4(pl, arg0, arg1, arg2, arg3) { \ + pl[3] = (uint32_t)(arg3); \ + PM_PACK_PAYLOAD3(pl, arg0, arg1, arg2); \ +} + +#define PM_PACK_PAYLOAD5(pl, arg0, arg1, arg2, arg3, arg4) { \ + pl[4] = (uint32_t)(arg4); \ + PM_PACK_PAYLOAD4(pl, arg0, arg1, arg2, arg3); \ +} + +#define PM_PACK_PAYLOAD6(pl, arg0, arg1, arg2, arg3, arg4, arg5) { \ + pl[5] = (uint32_t)(arg5); \ + PM_PACK_PAYLOAD5(pl, arg0, arg1, arg2, arg3, arg4); \ +} + +/** + * pm_self_suspend() - PM call for processor to suspend itself + * @nid Node id of the processor or subsystem + * @latency Requested maximum wakeup latency (not supported) + * @state Requested state + * @address Resume address + * + * This is a blocking call, it will return only once PMU has responded. + * On a wakeup, resume address will be automatically set by PMU. + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_self_suspend(enum pm_node_id nid, + unsigned int latency, + unsigned int state, + uintptr_t address) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + unsigned int cpuid = plat_my_core_pos(); + const struct pm_proc *proc = pm_get_proc(cpuid); + + /* + * Do client specific suspend operations + * (e.g. set powerdown request bit) + */ + pm_client_suspend(proc, state); + /* Send request to the PMU */ + PM_PACK_PAYLOAD6(payload, PM_SELF_SUSPEND, proc->node_id, latency, + state, address, (address >> 32)); + return pm_ipi_send_sync(proc, payload, NULL); +} + +/** + * pm_req_suspend() - PM call to request for another PU or subsystem to + * be suspended gracefully. + * @target Node id of the targeted PU or subsystem + * @ack Flag to specify whether acknowledge is requested + * @latency Requested wakeup latency (not supported) + * @state Requested state (not supported) + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_req_suspend(enum pm_node_id target, + enum pm_request_ack ack, + unsigned int latency, unsigned int state) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PM_PACK_PAYLOAD5(payload, PM_REQ_SUSPEND, target, ack, latency, state); + if (ack == REQ_ACK_BLOCKING) + return pm_ipi_send_sync(primary_proc, payload, NULL); + else + return pm_ipi_send(primary_proc, payload); +} + +/** + * pm_req_wakeup() - PM call for processor to wake up selected processor + * or subsystem + * @target Node id of the processor or subsystem to wake up + * @ack Flag to specify whether acknowledge requested + * @set_address Resume address presence indicator + * 1 resume address specified, 0 otherwise + * @address Resume address + * + * This API function is either used to power up another APU core for SMP + * (by PSCI) or to power up an entirely different PU or subsystem, such + * as RPU0, RPU, or PL_CORE_xx. Resume address for the target PU will be + * automatically set by PMU. + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_req_wakeup(enum pm_node_id target, + unsigned int set_address, + uintptr_t address, + enum pm_request_ack ack) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + uint64_t encoded_address; + const struct pm_proc *proc = pm_get_proc_by_node(target); + + /* invoke APU-specific code for waking up another APU core */ + pm_client_wakeup(proc); + + /* encode set Address into 1st bit of address */ + encoded_address = address; + encoded_address |= !!set_address; + + /* Send request to the PMU to perform the wake of the PU */ + PM_PACK_PAYLOAD5(payload, PM_REQ_WAKEUP, target, encoded_address, + encoded_address >> 32, ack); + + if (ack == REQ_ACK_BLOCKING) + return pm_ipi_send_sync(primary_proc, payload, NULL); + else + return pm_ipi_send(primary_proc, payload); +} + +/** + * pm_force_powerdown() - PM call to request for another PU or subsystem to + * be powered down forcefully + * @target Node id of the targeted PU or subsystem + * @ack Flag to specify whether acknowledge is requested + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_force_powerdown(enum pm_node_id target, + enum pm_request_ack ack) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PM_PACK_PAYLOAD3(payload, PM_FORCE_POWERDOWN, target, ack); + + if (ack == REQ_ACK_BLOCKING) + return pm_ipi_send_sync(primary_proc, payload, NULL); + else + return pm_ipi_send(primary_proc, payload); +} + +/** + * pm_abort_suspend() - PM call to announce that a prior suspend request + * is to be aborted. + * @reason Reason for the abort + * + * Calling PU expects the PMU to abort the initiated suspend procedure. + * This is a non-blocking call without any acknowledge. + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* + * Do client specific abort suspend operations + * (e.g. enable interrupts and clear powerdown request bit) + */ + pm_client_abort_suspend(); + /* Send request to the PMU */ + /* TODO: allow passing the node ID of the affected CPU */ + PM_PACK_PAYLOAD3(payload, PM_ABORT_SUSPEND, reason, + primary_proc->node_id); + return pm_ipi_send(primary_proc, payload); +} + +/** + * pm_set_wakeup_source() - PM call to specify the wakeup source while suspended + * @target Node id of the targeted PU or subsystem + * @wkup_node Node id of the wakeup peripheral + * @enable Enable or disable the specified peripheral as wake source + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_set_wakeup_source(enum pm_node_id target, + enum pm_node_id wkup_node, + unsigned int enable) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + PM_PACK_PAYLOAD4(payload, PM_SET_WAKEUP_SOURCE, target, wkup_node, + enable); + return pm_ipi_send(primary_proc, payload); +} + +/** + * pm_system_shutdown() - PM call to request a system shutdown or restart + * @restart Shutdown or restart? 0 for shutdown, 1 for restart + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_system_shutdown(unsigned int restart) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + PM_PACK_PAYLOAD2(payload, PM_SYSTEM_SHUTDOWN, restart); + return pm_ipi_send(primary_proc, payload); +} + +/* APIs for managing PM slaves: */ + +/** + * pm_req_node() - PM call to request a node with specific capabilities + * @nid Node id of the slave + * @capabilities Requested capabilities of the slave + * @qos Quality of service (not supported) + * @ack Flag to specify whether acknowledge is requested + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_req_node(enum pm_node_id nid, + unsigned int capabilities, + unsigned int qos, + enum pm_request_ack ack) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + PM_PACK_PAYLOAD5(payload, PM_REQ_NODE, nid, capabilities, qos, ack); + + if (ack == REQ_ACK_BLOCKING) + return pm_ipi_send_sync(primary_proc, payload, NULL); + else + return pm_ipi_send(primary_proc, payload); +} + +/** + * pm_set_requirement() - PM call to set requirement for PM slaves + * @nid Node id of the slave + * @capabilities Requested capabilities of the slave + * @qos Quality of service (not supported) + * @ack Flag to specify whether acknowledge is requested + * + * This API function is to be used for slaves a PU already has requested + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_set_requirement(enum pm_node_id nid, + unsigned int capabilities, + unsigned int qos, + enum pm_request_ack ack) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + PM_PACK_PAYLOAD5(payload, PM_SET_REQUIREMENT, nid, capabilities, qos, + ack); + + if (ack == REQ_ACK_BLOCKING) + return pm_ipi_send_sync(primary_proc, payload, NULL); + else + return pm_ipi_send(primary_proc, payload); +} + +/** + * pm_release_node() - PM call to release a node + * @nid Node id of the slave + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_release_node(enum pm_node_id nid) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + PM_PACK_PAYLOAD2(payload, PM_RELEASE_NODE, nid); + return pm_ipi_send(primary_proc, payload); +} + +/** + * pm_set_max_latency() - PM call to set wakeup latency requirements + * @nid Node id of the slave + * @latency Requested maximum wakeup latency + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_set_max_latency(enum pm_node_id nid, + unsigned int latency) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + PM_PACK_PAYLOAD3(payload, PM_SET_MAX_LATENCY, nid, latency); + return pm_ipi_send(primary_proc, payload); +} + +/* Miscellaneous API functions */ + +/** + * pm_get_api_version() - Get version number of PMU PM firmware + * @version Returns 32-bit version number of PMU Power Management Firmware + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_get_api_version(unsigned int *version) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PM_PACK_PAYLOAD1(payload, PM_GET_API_VERSION); + return pm_ipi_send_sync(primary_proc, payload, version); +} + +/** + * pm_set_configuration() - PM call to set system configuration + * @phys_addr Physical 32-bit address of data structure in memory + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_set_configuration(unsigned int phys_addr) +{ + return PM_RET_ERROR_NOTSUPPORTED; +} + +/** + * pm_get_node_status() - PM call to request a node's current power state + * @nid Node id of the slave + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_get_node_status(enum pm_node_id nid) +{ + /* TODO: Add power state argument!! */ + uint32_t payload[PAYLOAD_ARG_CNT]; + + PM_PACK_PAYLOAD2(payload, PM_GET_NODE_STATUS, nid); + return pm_ipi_send(primary_proc, payload); +} + +/** + * pm_register_notifier() - Register the PU to be notified of PM events + * @nid Node id of the slave + * @event The event to be notified about + * @wake Wake up on event + * @enable Enable or disable the notifier + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_register_notifier(enum pm_node_id nid, + unsigned int event, + unsigned int wake, + unsigned int enable) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + PM_PACK_PAYLOAD5(payload, PM_REGISTER_NOTIFIER, + nid, event, wake, enable); + + return pm_ipi_send(primary_proc, payload); +} + +/** + * pm_get_op_characteristic() - PM call to request operating characteristics + * of a node + * @nid Node id of the slave + * @type Type of the operating characteristic + * (power, temperature and latency) + * @result Returns the operating characteristic for the requested node, + * specified by the type + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_get_op_characteristic(enum pm_node_id nid, + enum pm_opchar_type type, + uint32_t *result) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PM_PACK_PAYLOAD3(payload, PM_GET_OP_CHARACTERISTIC, nid, type); + return pm_ipi_send_sync(primary_proc, payload, result); +} + +/* Direct-Control API functions */ + +/** + * pm_reset_assert() - Assert reset + * @reset Reset ID + * @assert Assert (1) or de-assert (0) + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_reset_assert(unsigned int reset, + unsigned int assert) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PM_PACK_PAYLOAD3(payload, PM_RESET_ASSERT, reset, assert); + return pm_ipi_send(primary_proc, payload); +} + +/** + * pm_reset_get_status() - Get current status of a reset line + * @reset Reset ID + * @reset_status Returns current status of selected reset line + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_reset_get_status(unsigned int reset, + unsigned int *reset_status) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PM_PACK_PAYLOAD2(payload, PM_RESET_GET_STATUS, reset); + return pm_ipi_send_sync(primary_proc, payload, reset_status); +} + +/** + * pm_mmio_write() - Perform write to protected mmio + * @address Address to write to + * @mask Mask to apply + * @value Value to write + * + * This function provides access to PM-related control registers + * that may not be directly accessible by a particular PU. + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_mmio_write(uintptr_t address, + unsigned int mask, + unsigned int value) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PM_PACK_PAYLOAD4(payload, PM_MMIO_WRITE, address, mask, value); + return pm_ipi_send_sync(primary_proc, payload, NULL); +} + +/** + * pm_mmio_read() - Read value from protected mmio + * @address Address to write to + * @value Value to write + * + * This function provides access to PM-related control registers + * that may not be directly accessible by a particular PU. + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_mmio_read(uintptr_t address, unsigned int *value) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PM_PACK_PAYLOAD2(payload, PM_MMIO_READ, address); + return pm_ipi_send_sync(primary_proc, payload, value); +} + +/** + * pm_fpga_load() - Load the bitstream into the PL. + * + * This function provides access to the xilfpga library to load + * the Bit-stream into PL. + * + * address_low: lower 32-bit Linear memory space address + * + * address_high: higher 32-bit Linear memory space address + * + * size: Number of 32bit words + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_fpga_load(uint32_t address_low, + uint32_t address_high, + uint32_t size, + uint32_t flags) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PM_PACK_PAYLOAD5(payload, PM_FPGA_LOAD, address_high, address_low, + size, flags); + return pm_ipi_send(primary_proc, payload); +} + +/** + * pm_fpga_get_status() - Read value from fpga status register + * @value Value to read + * + * This function provides access to the xilfpga library to get + * the fpga status + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_fpga_get_status(unsigned int *value) +{ + uint32_t payload[PAYLOAD_ARG_CNT]; + + /* Send request to the PMU */ + PM_PACK_PAYLOAD1(payload, PM_FPGA_GET_STATUS); + return pm_ipi_send_sync(primary_proc, payload, value); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_sys.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_sys.h new file mode 100644 index 0000000..26d83e7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_api_sys.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PM_API_SYS_H_ +#define _PM_API_SYS_H_ + +#include +#include "pm_defs.h" + +/********************************************************** + * System-level API function declarations + **********************************************************/ +enum pm_ret_status pm_req_suspend(enum pm_node_id nid, + enum pm_request_ack ack, + unsigned int latency, + unsigned int state); + +enum pm_ret_status pm_self_suspend(enum pm_node_id nid, + unsigned int latency, + unsigned int state, + uintptr_t address); + +enum pm_ret_status pm_force_powerdown(enum pm_node_id nid, + enum pm_request_ack ack); + +enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason); + +enum pm_ret_status pm_req_wakeup(enum pm_node_id nid, + unsigned int set_address, + uintptr_t address, + enum pm_request_ack ack); + +enum pm_ret_status pm_set_wakeup_source(enum pm_node_id target, + enum pm_node_id wkup_node, + unsigned int enable); + +enum pm_ret_status pm_system_shutdown(unsigned int restart); + +enum pm_ret_status pm_init_suspend_cb(enum pm_suspend_reason reason, + unsigned int latency, + unsigned int state, + unsigned int timeout); + +/* API functions for managing PM Slaves */ +enum pm_ret_status pm_req_node(enum pm_node_id nid, + unsigned int capabilities, + unsigned int qos, + enum pm_request_ack ack); +enum pm_ret_status pm_release_node(enum pm_node_id nid); + +enum pm_ret_status pm_set_requirement(enum pm_node_id nid, + unsigned int capabilities, + unsigned int qos, + enum pm_request_ack ack); +enum pm_ret_status pm_set_max_latency(enum pm_node_id nid, + unsigned int latency); + +/* Miscellaneous API functions */ +enum pm_ret_status pm_get_api_version(unsigned int *version); +enum pm_ret_status pm_set_configuration(unsigned int phys_addr); +enum pm_ret_status pm_get_node_status(enum pm_node_id node); +enum pm_ret_status pm_register_notifier(enum pm_node_id nid, + unsigned int event, + unsigned int wake, + unsigned int enable); +enum pm_ret_status pm_get_op_characteristic(enum pm_node_id nid, + enum pm_opchar_type type, + uint32_t *result); +enum pm_ret_status pm_acknowledge_cb(enum pm_node_id nid, + enum pm_ret_status status, + unsigned int oppoint); +enum pm_ret_status pm_notify_cb(enum pm_node_id nid, + unsigned int event, + unsigned int oppoint); + +/* Direct-Control API functions */ +enum pm_ret_status pm_reset_assert(unsigned int reset_id, + unsigned int assert); +enum pm_ret_status pm_reset_get_status(unsigned int reset_id, + unsigned int *reset_status); +enum pm_ret_status pm_mmio_write(uintptr_t address, + unsigned int mask, + unsigned int value); +enum pm_ret_status pm_mmio_read(uintptr_t address, unsigned int *value); +enum pm_ret_status pm_fpga_load(uint32_t address_high, + uint32_t address_low, + uint32_t size, + uint32_t flags); +enum pm_ret_status pm_fpga_get_status(unsigned int *value); + +#endif /* _PM_API_SYS_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_client.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_client.c new file mode 100644 index 0000000..b77a1cf --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_client.c @@ -0,0 +1,331 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * APU specific definition of processors in the subsystem as well as functions + * for getting information about and changing state of the APU. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "pm_api_sys.h" +#include "pm_client.h" +#include "pm_ipi.h" +#include "../zynqmp_def.h" + +#define IRQ_MAX 84 +#define NUM_GICD_ISENABLER ((IRQ_MAX >> 5) + 1) +#define UNDEFINED_CPUID (~0) + +DEFINE_BAKERY_LOCK(pm_client_secure_lock); + +extern const struct pm_ipi apu_ipi; + +/* Order in pm_procs_all array must match cpu ids */ +static const struct pm_proc const pm_procs_all[] = { + { + .node_id = NODE_APU_0, + .pwrdn_mask = APU_0_PWRCTL_CPUPWRDWNREQ_MASK, + .ipi = &apu_ipi, + }, + { + .node_id = NODE_APU_1, + .pwrdn_mask = APU_1_PWRCTL_CPUPWRDWNREQ_MASK, + .ipi = &apu_ipi, + }, + { + .node_id = NODE_APU_2, + .pwrdn_mask = APU_2_PWRCTL_CPUPWRDWNREQ_MASK, + .ipi = &apu_ipi, + }, + { + .node_id = NODE_APU_3, + .pwrdn_mask = APU_3_PWRCTL_CPUPWRDWNREQ_MASK, + .ipi = &apu_ipi, + }, +}; + +/* Interrupt to PM node ID map */ +static enum pm_node_id irq_node_map[IRQ_MAX + 1] = { + NODE_UNKNOWN, + NODE_UNKNOWN, + NODE_UNKNOWN, + NODE_UNKNOWN, /* 3 */ + NODE_UNKNOWN, + NODE_UNKNOWN, + NODE_UNKNOWN, + NODE_UNKNOWN, /* 7 */ + NODE_UNKNOWN, + NODE_UNKNOWN, + NODE_UNKNOWN, + NODE_UNKNOWN, /* 11 */ + NODE_UNKNOWN, + NODE_UNKNOWN, + NODE_NAND, + NODE_QSPI, /* 15 */ + NODE_GPIO, + NODE_I2C_0, + NODE_I2C_1, + NODE_SPI_0, /* 19 */ + NODE_SPI_1, + NODE_UART_0, + NODE_UART_1, + NODE_CAN_0, /* 23 */ + NODE_CAN_1, + NODE_UNKNOWN, + NODE_RTC, + NODE_RTC, /* 27 */ + NODE_UNKNOWN, + NODE_UNKNOWN, + NODE_UNKNOWN, + NODE_UNKNOWN, /* 31 */ + NODE_UNKNOWN, + NODE_UNKNOWN, + NODE_UNKNOWN, + NODE_UNKNOWN, /* 35, NODE_IPI_APU */ + NODE_TTC_0, + NODE_TTC_0, + NODE_TTC_0, + NODE_TTC_1, /* 39 */ + NODE_TTC_1, + NODE_TTC_1, + NODE_TTC_2, + NODE_TTC_2, /* 43 */ + NODE_TTC_2, + NODE_TTC_3, + NODE_TTC_3, + NODE_TTC_3, /* 47 */ + NODE_SD_0, + NODE_SD_1, + NODE_SD_0, + NODE_SD_1, /* 51 */ + NODE_UNKNOWN, + NODE_UNKNOWN, + NODE_UNKNOWN, + NODE_UNKNOWN, /* 55 */ + NODE_UNKNOWN, + NODE_ETH_0, + NODE_ETH_0, + NODE_ETH_1, /* 59 */ + NODE_ETH_1, + NODE_ETH_2, + NODE_ETH_2, + NODE_ETH_3, /* 63 */ + NODE_ETH_3, + NODE_USB_0, + NODE_USB_0, + NODE_USB_0, /* 67 */ + NODE_USB_0, + NODE_USB_0, + NODE_USB_1, + NODE_USB_1, /* 71 */ + NODE_USB_1, + NODE_USB_1, + NODE_USB_1, + NODE_USB_0, /* 75 */ + NODE_USB_0, + NODE_ADMA, + NODE_ADMA, + NODE_ADMA, /* 79 */ + NODE_ADMA, + NODE_ADMA, + NODE_ADMA, + NODE_ADMA, /* 83 */ + NODE_ADMA, +}; + +/** + * irq_to_pm_node - Get PM node ID corresponding to the interrupt number + * @irq: Interrupt number + * + * Return: PM node ID corresponding to the specified interrupt + */ +static enum pm_node_id irq_to_pm_node(unsigned int irq) +{ + assert(irq <= IRQ_MAX); + return irq_node_map[irq]; +} + +/** + * pm_client_set_wakeup_sources - Set all slaves with enabled interrupts as wake + * sources in the PMU firmware + */ +static void pm_client_set_wakeup_sources(void) +{ + uint32_t reg_num; + uint8_t pm_wakeup_nodes_set[NODE_MAX]; + uintptr_t isenabler1 = BASE_GICD_BASE + GICD_ISENABLER + 4; + + memset(&pm_wakeup_nodes_set, 0, sizeof(pm_wakeup_nodes_set)); + + for (reg_num = 0; reg_num < NUM_GICD_ISENABLER; reg_num++) { + uint32_t base_irq = reg_num << ISENABLER_SHIFT; + uint32_t reg = mmio_read_32(isenabler1 + (reg_num << 2)); + + if (!reg) + continue; + + while (reg) { + enum pm_node_id node; + uint32_t idx, ret, irq, lowest_set = reg & (-reg); + + idx = __builtin_ctz(lowest_set); + irq = base_irq + idx; + + if (irq > IRQ_MAX) + break; + + node = irq_to_pm_node(irq); + reg &= ~lowest_set; + + if ((node != NODE_UNKNOWN) && + (!pm_wakeup_nodes_set[node])) { + ret = pm_set_wakeup_source(NODE_APU, node, 1); + pm_wakeup_nodes_set[node] = !ret; + } + } + } +} + +/** + * pm_get_proc() - returns pointer to the proc structure + * @cpuid: id of the cpu whose proc struct pointer should be returned + * + * Return: pointer to a proc structure if proc is found, otherwise NULL + */ +const struct pm_proc *pm_get_proc(unsigned int cpuid) +{ + if (cpuid < ARRAY_SIZE(pm_procs_all)) + return &pm_procs_all[cpuid]; + + return NULL; +} + +/** + * pm_get_proc_by_node() - returns pointer to the proc structure + * @nid: node id of the processor + * + * Return: pointer to a proc structure if proc is found, otherwise NULL + */ +const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid) +{ + for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) { + if (nid == pm_procs_all[i].node_id) + return &pm_procs_all[i]; + } + return NULL; +} + +/** + * pm_get_cpuid() - get the local cpu ID for a global node ID + * @nid: node id of the processor + * + * Return: the cpu ID (starting from 0) for the subsystem + */ +static unsigned int pm_get_cpuid(enum pm_node_id nid) +{ + for (size_t i = 0; i < ARRAY_SIZE(pm_procs_all); i++) { + if (pm_procs_all[i].node_id == nid) + return i; + } + return UNDEFINED_CPUID; +} + +const struct pm_proc *primary_proc = &pm_procs_all[0]; + +/** + * pm_client_suspend() - Client-specific suspend actions + * + * This function should contain any PU-specific actions + * required prior to sending suspend request to PMU + * Actions taken depend on the state system is suspending to. + */ +void pm_client_suspend(const struct pm_proc *proc, unsigned int state) +{ + bakery_lock_get(&pm_client_secure_lock); + + if (state == PM_STATE_SUSPEND_TO_RAM) + pm_client_set_wakeup_sources(); + + /* Set powerdown request */ + mmio_write_32(APU_PWRCTL, mmio_read_32(APU_PWRCTL) | proc->pwrdn_mask); + + bakery_lock_release(&pm_client_secure_lock); +} + + +/** + * pm_client_abort_suspend() - Client-specific abort-suspend actions + * + * This function should contain any PU-specific actions + * required for aborting a prior suspend request + */ +void pm_client_abort_suspend(void) +{ + /* Enable interrupts at processor level (for current cpu) */ + gicv2_cpuif_enable(); + + bakery_lock_get(&pm_client_secure_lock); + + /* Clear powerdown request */ + mmio_write_32(APU_PWRCTL, + mmio_read_32(APU_PWRCTL) & ~primary_proc->pwrdn_mask); + + bakery_lock_release(&pm_client_secure_lock); +} + +/** + * pm_client_wakeup() - Client-specific wakeup actions + * + * This function should contain any PU-specific actions + * required for waking up another APU core + */ +void pm_client_wakeup(const struct pm_proc *proc) +{ + unsigned int cpuid = pm_get_cpuid(proc->node_id); + + if (cpuid == UNDEFINED_CPUID) + return; + + bakery_lock_get(&pm_client_secure_lock); + + /* clear powerdown bit for affected cpu */ + uint32_t val = mmio_read_32(APU_PWRCTL); + val &= ~(proc->pwrdn_mask); + mmio_write_32(APU_PWRCTL, val); + + bakery_lock_release(&pm_client_secure_lock); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_client.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_client.h new file mode 100644 index 0000000..7f80d5b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_client.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Contains APU specific macros and macros to be defined depending on + * the execution environment. + */ + +#ifndef _PM_CLIENT_H_ +#define _PM_CLIENT_H_ + +#include "pm_defs.h" +#include "pm_common.h" + +/* Functions to be implemented by each PU */ +void pm_client_suspend(const struct pm_proc *proc, unsigned int state); +void pm_client_abort_suspend(void); +void pm_client_wakeup(const struct pm_proc *proc); +enum pm_ret_status set_ocm_retention(void); + +/* Global variables to be set in pm_client.c */ +extern const struct pm_proc *primary_proc; + +#endif /* _PM_CLIENT_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_common.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_common.h new file mode 100644 index 0000000..b432a83 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_common.h @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Contains definitions of commonly used macros and data types needed + * for PU Power Management. This file should be common for all PU's. + */ + +#ifndef _PM_COMMON_H_ +#define _PM_COMMON_H_ + +#include +#include +#include "pm_defs.h" + +#define PAYLOAD_ARG_CNT 6U +#define PAYLOAD_ARG_SIZE 4U /* size in bytes */ + +/** + * pm_ipi - struct for capturing IPI-channel specific info + * @mask mask for enabling/disabling and triggering the IPI + * @base base address for IPI + * @buffer_base base address for payload buffer + */ +struct pm_ipi { + const unsigned int mask; + const uintptr_t base; + const uintptr_t buffer_base; +}; + +/** + * pm_proc - struct for capturing processor related info + * @node_id node-ID of the processor + * @pwrdn_mask cpu-specific mask to be used for power control register + * @ipi pointer to IPI channel structure + * (in APU all processors share one IPI channel) + */ +struct pm_proc { + const enum pm_node_id node_id; + const unsigned int pwrdn_mask; + const struct pm_ipi *ipi; +}; + +const struct pm_proc *pm_get_proc(unsigned int cpuid); +const struct pm_proc *pm_get_proc_by_node(enum pm_node_id nid); + +#endif /* _PM_COMMON_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_defs.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_defs.h new file mode 100644 index 0000000..aec335a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_defs.h @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* ZynqMP power management enums and defines */ + +#ifndef _PM_DEFS_H_ +#define _PM_DEFS_H_ + +/********************************************************************* + * Macro definitions + ********************************************************************/ + +/* + * Version number is a 32bit value, like: + * (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR + */ +#define PM_VERSION_MAJOR 0 +#define PM_VERSION_MINOR 2 + +#define PM_VERSION ((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR) + +/* Capabilities for RAM */ +#define PM_CAP_ACCESS 0x1U +#define PM_CAP_CONTEXT 0x2U + +#define MAX_LATENCY (~0U) +#define MAX_QOS 100U + +/* State arguments of the self suspend */ +#define PM_STATE_CPU_IDLE 0x0U +#define PM_STATE_SUSPEND_TO_RAM 0xFU + +/********************************************************************* + * Enum definitions + ********************************************************************/ + +enum pm_api_id { + /* Miscellaneous API functions: */ + PM_GET_API_VERSION = 1, /* Do not change or move */ + PM_SET_CONFIGURATION, + PM_GET_NODE_STATUS, + PM_GET_OP_CHARACTERISTIC, + PM_REGISTER_NOTIFIER, + /* API for suspending of PUs: */ + PM_REQ_SUSPEND, + PM_SELF_SUSPEND, + PM_FORCE_POWERDOWN, + PM_ABORT_SUSPEND, + PM_REQ_WAKEUP, + PM_SET_WAKEUP_SOURCE, + PM_SYSTEM_SHUTDOWN, + /* API for managing PM slaves: */ + PM_REQ_NODE, + PM_RELEASE_NODE, + PM_SET_REQUIREMENT, + PM_SET_MAX_LATENCY, + /* Direct control API functions: */ + PM_RESET_ASSERT, + PM_RESET_GET_STATUS, + PM_MMIO_WRITE, + PM_MMIO_READ, + PM_INIT, + PM_FPGA_LOAD, + PM_FPGA_GET_STATUS, + PM_GET_CHIPID, + PM_API_MAX +}; + +enum pm_node_id { + NODE_UNKNOWN = 0, + NODE_APU, + NODE_APU_0, + NODE_APU_1, + NODE_APU_2, + NODE_APU_3, + NODE_RPU, + NODE_RPU_0, + NODE_RPU_1, + NODE_PL, + NODE_FPD, + NODE_OCM_BANK_0, + NODE_OCM_BANK_1, + NODE_OCM_BANK_2, + NODE_OCM_BANK_3, + NODE_TCM_0_A, + NODE_TCM_0_B, + NODE_TCM_1_A, + NODE_TCM_1_B, + NODE_L2, + NODE_GPU_PP_0, + NODE_GPU_PP_1, + NODE_USB_0, + NODE_USB_1, + NODE_TTC_0, + NODE_TTC_1, + NODE_TTC_2, + NODE_TTC_3, + NODE_SATA, + NODE_ETH_0, + NODE_ETH_1, + NODE_ETH_2, + NODE_ETH_3, + NODE_UART_0, + NODE_UART_1, + NODE_SPI_0, + NODE_SPI_1, + NODE_I2C_0, + NODE_I2C_1, + NODE_SD_0, + NODE_SD_1, + NODE_DP, + NODE_GDMA, + NODE_ADMA, + NODE_NAND, + NODE_QSPI, + NODE_GPIO, + NODE_CAN_0, + NODE_CAN_1, + NODE_AFI, + NODE_APLL, + NODE_VPLL, + NODE_DPLL, + NODE_RPLL, + NODE_IOPLL, + NODE_DDR, + NODE_IPI_APU, + NODE_IPI_RPU_0, + NODE_GPU, + NODE_PCIE, + NODE_PCAP, + NODE_RTC, + NODE_MAX +}; + +enum pm_request_ack { + REQ_ACK_NO = 1, + REQ_ACK_BLOCKING, + REQ_ACK_NON_BLOCKING, +}; + +enum pm_abort_reason { + ABORT_REASON_WKUP_EVENT = 100, + ABORT_REASON_PU_BUSY, + ABORT_REASON_NO_PWRDN, + ABORT_REASON_UNKNOWN, +}; + +enum pm_suspend_reason { + SUSPEND_REASON_PU_REQ = 201, + SUSPEND_REASON_ALERT, + SUSPEND_REASON_SYS_SHUTDOWN, +}; + +enum pm_ram_state { + PM_RAM_STATE_OFF = 1, + PM_RAM_STATE_RETENTION, + PM_RAM_STATE_ON, +}; + +enum pm_opchar_type { + PM_OPCHAR_TYPE_POWER = 1, + PM_OPCHAR_TYPE_TEMP, + PM_OPCHAR_TYPE_LATENCY, +}; + +/** + * @PM_RET_SUCCESS: success + * @PM_RET_ERROR_ARGS: illegal arguments provided + * @PM_RET_ERROR_ACCESS: access rights violation + * @PM_RET_ERROR_TIMEOUT: timeout in communication with PMU + * @PM_RET_ERROR_NOTSUPPORTED: feature not supported + * @PM_RET_ERROR_PROC: node is not a processor node + * @PM_RET_ERROR_API_ID: illegal API ID + * @PM_RET_ERROR_OTHER: other error + */ +enum pm_ret_status { + PM_RET_SUCCESS, + PM_RET_ERROR_ARGS, + PM_RET_ERROR_ACCESS, + PM_RET_ERROR_TIMEOUT, + PM_RET_ERROR_NOTSUPPORTED, + PM_RET_ERROR_PROC, + PM_RET_ERROR_API_ID, + PM_RET_ERROR_FAILURE, + PM_RET_ERROR_COMMUNIC, + PM_RET_ERROR_DOUBLEREQ, + PM_RET_ERROR_OTHER, +}; + +/** + * @PM_INITIAL_BOOT: boot is a fresh system startup + * @PM_RESUME: boot is a resume + * @PM_BOOT_ERROR: error, boot cause cannot be identified + */ +enum pm_boot_status { + PM_INITIAL_BOOT, + PM_RESUME, + PM_BOOT_ERROR, +}; + +#endif /* _PM_DEFS_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_ipi.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_ipi.c new file mode 100644 index 0000000..c3e7ccb --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_ipi.c @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "pm_ipi.h" +#include "../zynqmp_private.h" + +/* IPI message buffers */ +#define IPI_BUFFER_BASEADDR 0xFF990000U + +#define IPI_BUFFER_RPU_0_BASE (IPI_BUFFER_BASEADDR + 0x0U) +#define IPI_BUFFER_RPU_1_BASE (IPI_BUFFER_BASEADDR + 0x200U) +#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U) +#define IPI_BUFFER_PL_0_BASE (IPI_BUFFER_BASEADDR + 0x600U) +#define IPI_BUFFER_PL_1_BASE (IPI_BUFFER_BASEADDR + 0x800U) +#define IPI_BUFFER_PL_2_BASE (IPI_BUFFER_BASEADDR + 0xA00U) +#define IPI_BUFFER_PL_3_BASE (IPI_BUFFER_BASEADDR + 0xC00U) +#define IPI_BUFFER_PMU_BASE (IPI_BUFFER_BASEADDR + 0xE00U) + +#define IPI_BUFFER_TARGET_RPU_0_OFFSET 0x0U +#define IPI_BUFFER_TARGET_RPU_1_OFFSET 0x40U +#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U +#define IPI_BUFFER_TARGET_PL_0_OFFSET 0xC0U +#define IPI_BUFFER_TARGET_PL_1_OFFSET 0x100U +#define IPI_BUFFER_TARGET_PL_2_OFFSET 0x140U +#define IPI_BUFFER_TARGET_PL_3_OFFSET 0x180U +#define IPI_BUFFER_TARGET_PMU_OFFSET 0x1C0U + +#define IPI_BUFFER_REQ_OFFSET 0x0U +#define IPI_BUFFER_RESP_OFFSET 0x20U + +/* IPI Base Address */ +#define IPI_BASEADDR 0XFF300000 + +/* APU's IPI registers */ +#define IPI_APU_ISR (IPI_BASEADDR + 0X00000010) +#define IPI_APU_IER (IPI_BASEADDR + 0X00000018) +#define IPI_APU_IDR (IPI_BASEADDR + 0X0000001C) +#define IPI_APU_IXR_PMU_0_MASK (1 << 16) + +#define IPI_TRIG_OFFSET 0 +#define IPI_OBS_OFFSET 4 + +/* Power Management IPI interrupt number */ +#define PM_INT_NUM 0 +#define IPI_PMU_PM_INT_BASE (IPI_PMU_0_TRIG + (PM_INT_NUM * 0x1000)) +#define IPI_PMU_PM_INT_MASK (IPI_APU_IXR_PMU_0_MASK << PM_INT_NUM) +#if (PM_INT_NUM < 0 || PM_INT_NUM > 3) + #error PM_INT_NUM value out of range +#endif + +#define IPI_APU_MASK 1U + +DEFINE_BAKERY_LOCK(pm_secure_lock); + +const struct pm_ipi apu_ipi = { + .mask = IPI_APU_MASK, + .base = IPI_BASEADDR, + .buffer_base = IPI_BUFFER_APU_BASE, +}; + +/** + * pm_ipi_init() - Initialize IPI peripheral for communication with PMU + * + * @return On success, the initialization function must return 0. + * Any other return value will cause the framework to ignore + * the service + * + * Enable interrupts at registered entrance in IPI peripheral + * Called from pm_setup initialization function + */ +int pm_ipi_init(void) +{ + bakery_lock_init(&pm_secure_lock); + + /* IPI Interrupts Clear & Disable */ + mmio_write_32(IPI_APU_ISR, 0xffffffff); + mmio_write_32(IPI_APU_IDR, 0xffffffff); + + return 0; +} + +/** + * pm_ipi_wait() - wait for pmu to handle request + * @proc proc which is waiting for PMU to handle request + */ +static enum pm_ret_status pm_ipi_wait(const struct pm_proc *proc) +{ + int status; + + /* Wait until previous interrupt is handled by PMU */ + do { + status = mmio_read_32(proc->ipi->base + IPI_OBS_OFFSET) & + IPI_PMU_PM_INT_MASK; + /* TODO: 1) Use timer to add delay between read attempts */ + /* TODO: 2) Return PM_RET_ERR_TIMEOUT if this times out */ + } while (status); + + return PM_RET_SUCCESS; +} + +/** + * pm_ipi_send_common() - Sends IPI request to the PMU + * @proc Pointer to the processor who is initiating request + * @payload API id and call arguments to be written in IPI buffer + * + * Send an IPI request to the power controller. Caller needs to hold + * the 'pm_secure_lock' lock. + * + * @return Returns status, either success or error+reason + */ +static enum pm_ret_status pm_ipi_send_common(const struct pm_proc *proc, + uint32_t payload[PAYLOAD_ARG_CNT]) +{ + unsigned int offset = 0; + uintptr_t buffer_base = proc->ipi->buffer_base + + IPI_BUFFER_TARGET_PMU_OFFSET + + IPI_BUFFER_REQ_OFFSET; + + /* Wait until previous interrupt is handled by PMU */ + pm_ipi_wait(proc); + + /* Write payload into IPI buffer */ + for (size_t i = 0; i < PAYLOAD_ARG_CNT; i++) { + mmio_write_32(buffer_base + offset, payload[i]); + offset += PAYLOAD_ARG_SIZE; + } + /* Generate IPI to PMU */ + mmio_write_32(proc->ipi->base + IPI_TRIG_OFFSET, IPI_PMU_PM_INT_MASK); + + return PM_RET_SUCCESS; +} + +/** + * pm_ipi_send() - Sends IPI request to the PMU + * @proc Pointer to the processor who is initiating request + * @payload API id and call arguments to be written in IPI buffer + * + * Send an IPI request to the power controller. + * + * @return Returns status, either success or error+reason + */ +enum pm_ret_status pm_ipi_send(const struct pm_proc *proc, + uint32_t payload[PAYLOAD_ARG_CNT]) +{ + enum pm_ret_status ret; + + bakery_lock_get(&pm_secure_lock); + + ret = pm_ipi_send_common(proc, payload); + + bakery_lock_release(&pm_secure_lock); + + return ret; +} + + +/** + * pm_ipi_buff_read() - Reads IPI response after PMU has handled interrupt + * @proc Pointer to the processor who is waiting and reading response + * @value Used to return value from 2nd IPI buffer element (optional) + * + * @return Returns status, either success or error+reason + */ +static enum pm_ret_status pm_ipi_buff_read(const struct pm_proc *proc, + unsigned int *value) +{ + uintptr_t buffer_base = proc->ipi->buffer_base + + IPI_BUFFER_TARGET_PMU_OFFSET + + IPI_BUFFER_RESP_OFFSET; + + pm_ipi_wait(proc); + + /* + * Read response from IPI buffer + * buf-0: success or error+reason + * buf-1: value + * buf-2: unused + * buf-3: unused + */ + if (value != NULL) + *value = mmio_read_32(buffer_base + PAYLOAD_ARG_SIZE); + + return mmio_read_32(buffer_base); +} + +/** + * pm_ipi_send_sync() - Sends IPI request to the PMU + * @proc Pointer to the processor who is initiating request + * @payload API id and call arguments to be written in IPI buffer + * @value Used to return value from 2nd IPI buffer element (optional) + * + * Send an IPI request to the power controller and wait for it to be handled. + * + * @return Returns status, either success or error+reason and, optionally, + * @value + */ +enum pm_ret_status pm_ipi_send_sync(const struct pm_proc *proc, + uint32_t payload[PAYLOAD_ARG_CNT], + unsigned int *value) +{ + enum pm_ret_status ret; + + bakery_lock_get(&pm_secure_lock); + + ret = pm_ipi_send_common(proc, payload); + if (ret != PM_RET_SUCCESS) + goto unlock; + + ret = pm_ipi_buff_read(proc, value); + +unlock: + bakery_lock_release(&pm_secure_lock); + + return ret; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_ipi.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_ipi.h new file mode 100644 index 0000000..d92e648 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_ipi.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PM_IPI_H_ +#define _PM_IPI_H_ + +#include "pm_common.h" + +int pm_ipi_init(void); + +enum pm_ret_status pm_ipi_send(const struct pm_proc *proc, + uint32_t payload[PAYLOAD_ARG_CNT]); +enum pm_ret_status pm_ipi_send_sync(const struct pm_proc *proc, + uint32_t payload[PAYLOAD_ARG_CNT], + unsigned int *value); + +#endif /* _PM_IPI_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_svc_main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_svc_main.c new file mode 100644 index 0000000..9c08ffb --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_svc_main.c @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * Top-level SMC handler for ZynqMP power management calls and + * IPI setup functions for communication with PMU. + */ + +#include +#include +#include +#include +#include "pm_api_sys.h" +#include "pm_client.h" +#include "pm_ipi.h" +#include "../zynqmp_private.h" + +/* 0 - UP, !0 - DOWN */ +static int32_t pm_down = !0; + +/** + * pm_context - Structure which contains data for power management + * @api_version version of PM API, must match with one on PMU side + * @payload payload array used to store received + * data from ipi buffer registers + */ +static struct { + uint32_t api_version; + uint32_t payload[PAYLOAD_ARG_CNT]; +} pm_ctx; + +/** + * pm_setup() - PM service setup + * + * @return On success, the initialization function must return 0. + * Any other return value will cause the framework to ignore + * the service + * + * Initialization functions for ZynqMP power management for + * communicaton with PMU. + * + * Called from sip_svc_setup initialization function with the + * rt_svc_init signature. + * + */ +int pm_setup(void) +{ + int status; + + if (!zynqmp_is_pmu_up()) + return -ENODEV; + + status = pm_ipi_init(); + + if (status == 0) + INFO("BL31: PM Service Init Complete: API v%d.%d\n", + PM_VERSION_MAJOR, PM_VERSION_MINOR); + else + INFO("BL31: PM Service Init Failed, Error Code %d!\n", status); + + pm_down = status; + + return status; +} + +/** + * pm_smc_handler() - SMC handler for PM-API calls coming from EL1/EL2. + * @smc_fid - Function Identifier + * @x1 - x4 - Arguments + * @cookie - Unused + * @handler - Pointer to caller's context structure + * + * @return - Unused + * + * Determines that smc_fid is valid and supported PM SMC Function ID from the + * list of pm_api_ids, otherwise completes the request with + * the unknown SMC Function ID + * + * The SMC calls for PM service are forwarded from SIP Service SMC handler + * function with rt_svc_handle signature + */ +uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, void *cookie, void *handle, uint64_t flags) +{ + enum pm_ret_status ret; + + uint32_t pm_arg[4]; + + /* Handle case where PM wasn't initialized properly */ + if (pm_down) + SMC_RET1(handle, SMC_UNK); + + pm_arg[0] = (uint32_t)x1; + pm_arg[1] = (uint32_t)(x1 >> 32); + pm_arg[2] = (uint32_t)x2; + pm_arg[3] = (uint32_t)(x2 >> 32); + + switch (smc_fid & FUNCID_NUM_MASK) { + /* PM API Functions */ + case PM_SELF_SUSPEND: + ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2], + pm_arg[3]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_REQ_SUSPEND: + ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2], + pm_arg[3]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_REQ_WAKEUP: + ret = pm_req_wakeup(pm_arg[0], pm_arg[1], pm_arg[2], + pm_arg[3]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_FORCE_POWERDOWN: + ret = pm_force_powerdown(pm_arg[0], pm_arg[1]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_ABORT_SUSPEND: + ret = pm_abort_suspend(pm_arg[0]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_SET_WAKEUP_SOURCE: + ret = pm_set_wakeup_source(pm_arg[0], pm_arg[1], pm_arg[2]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_SYSTEM_SHUTDOWN: + ret = pm_system_shutdown(pm_arg[0]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_REQ_NODE: + ret = pm_req_node(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_RELEASE_NODE: + ret = pm_release_node(pm_arg[0]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_SET_REQUIREMENT: + ret = pm_set_requirement(pm_arg[0], pm_arg[1], pm_arg[2], + pm_arg[3]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_SET_MAX_LATENCY: + ret = pm_set_max_latency(pm_arg[0], pm_arg[1]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_GET_API_VERSION: + /* Check is PM API version already verified */ + if (pm_ctx.api_version == PM_VERSION) + SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS | + ((uint64_t)PM_VERSION << 32)); + + ret = pm_get_api_version(&pm_ctx.api_version); + SMC_RET1(handle, (uint64_t)ret | + ((uint64_t)pm_ctx.api_version << 32)); + + case PM_SET_CONFIGURATION: + ret = pm_set_configuration(pm_arg[0]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_GET_NODE_STATUS: + ret = pm_get_node_status(pm_arg[0]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_GET_OP_CHARACTERISTIC: + { + uint32_t result; + + ret = pm_get_op_characteristic(pm_arg[0], pm_arg[1], &result); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)result << 32)); + } + + case PM_REGISTER_NOTIFIER: + ret = pm_register_notifier(pm_arg[0], pm_arg[1], pm_arg[2], + pm_arg[3]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_RESET_ASSERT: + ret = pm_reset_assert(pm_arg[0], pm_arg[1]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_RESET_GET_STATUS: + { + uint32_t reset_status; + + ret = pm_reset_get_status(pm_arg[0], &reset_status); + SMC_RET1(handle, (uint64_t)ret | + ((uint64_t)reset_status << 32)); + } + + /* PM memory access functions */ + case PM_MMIO_WRITE: + ret = pm_mmio_write(pm_arg[0], pm_arg[1], pm_arg[2]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_MMIO_READ: + { + uint32_t value; + + ret = pm_mmio_read(pm_arg[0], &value); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + } + + case PM_FPGA_LOAD: + ret = pm_fpga_load(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]); + SMC_RET1(handle, (uint64_t)ret); + + case PM_FPGA_GET_STATUS: + { + uint32_t value; + + ret = pm_fpga_get_status(&value); + SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32); + } + + case PM_GET_CHIPID: + SMC_RET1(handle, zynqmp_get_silicon_id()); + + default: + WARN("Unimplemented PM Service Call: 0x%x\n", smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_svc_main.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_svc_main.h new file mode 100644 index 0000000..26985a2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/pm_service/pm_svc_main.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PM_SVC_MAIN_H_ +#define _PM_SVC_MAIN_H_ + +#include "pm_common.h" + +int pm_setup(void); +uint64_t pm_smc_handler(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3, + uint64_t x4, void *cookie, void *handle, + uint64_t flags); + +#endif /* _PM_SVC_MAIN_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/sip_svc_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/sip_svc_setup.c new file mode 100644 index 0000000..8bcfa6e --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/sip_svc_setup.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* Top level SMC handler for SiP calls. Dispatch PM calls to PM SMC handler. */ + +#include +#include +#include "pm_svc_main.h" + +/* SMC function IDs for SiP Service queries */ +#define ZYNQMP_SIP_SVC_CALL_COUNT 0x8200ff00 +#define ZYNQMP_SIP_SVC_UID 0x8200ff01 +#define ZYNQMP_SIP_SVC_VERSION 0x8200ff03 + +/* SiP Service Calls version numbers */ +#define SIP_SVC_VERSION_MAJOR 0 +#define SIP_SVC_VERSION_MINOR 1 + +/* These macros are used to identify PM calls from the SMC function ID */ +#define PM_FID_MASK 0xf000u +#define PM_FID_VALUE 0u +#define is_pm_fid(_fid) (((_fid) & PM_FID_MASK) == PM_FID_VALUE) + +/* SiP Service UUID */ +DEFINE_SVC_UUID(zynqmp_sip_uuid, + 0x2a1d9b5c, 0x8605, 0x4023, 0xa6, 0x1b, + 0xb9, 0x25, 0x82, 0x2d, 0xe3, 0xa5); + +/** + * sip_svc_setup() - Setup SiP Service + * + * Invokes PM setup + */ +static int32_t sip_svc_setup(void) +{ + /* PM implementation as SiP Service */ + pm_setup(); + + return 0; +} + +/** + * sip_svc_smc_handler() - Top-level SiP Service SMC handler + * + * Handler for all SiP SMC calls. Handles standard SIP requests + * and calls PM SMC handler if the call is for a PM-API function. + */ +uint64_t sip_svc_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + /* Let PM SMC handler deal with PM-related requests */ + if (is_pm_fid(smc_fid)) { + return pm_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle, + flags); + } + + switch (smc_fid) { + case ZYNQMP_SIP_SVC_CALL_COUNT: + /* PM functions + default functions */ + SMC_RET1(handle, PM_API_MAX + 2); + + case ZYNQMP_SIP_SVC_UID: + SMC_UUID_RET(handle, zynqmp_sip_uuid); + + case ZYNQMP_SIP_SVC_VERSION: + SMC_RET2(handle, SIP_SVC_VERSION_MAJOR, SIP_SVC_VERSION_MINOR); + + default: + WARN("Unimplemented SiP Service Call: 0x%x\n", smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} + +/* Register PM Service Calls as runtime service */ +DECLARE_RT_SVC( + sip_svc, + OEN_SIP_START, + OEN_SIP_END, + SMC_TYPE_FAST, + sip_svc_setup, + sip_svc_smc_handler); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/tsp/tsp-zynqmp.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/tsp/tsp-zynqmp.mk new file mode 100644 index 0000000..a9ebe60 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/tsp/tsp-zynqmp.mk @@ -0,0 +1,31 @@ +# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. + +# TSP source files specific to ZynqMP platform +BL32_SOURCES += plat/common/aarch64/platform_mp_stack.S \ + plat/xilinx/zynqmp/tsp/tsp_plat_setup.c diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c new file mode 100644 index 0000000..8e3ca62 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "../zynqmp_private.h" + +#define BL32_END (unsigned long)(&__BL32_END__) + +/* + * The next 2 constants identify the extents of the coherent memory region. + * These addresses are used by the MMU setup code and therefore they must be + * page-aligned. It is the responsibility of the linker script to ensure that + * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to + * page-aligned addresses. + */ +#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) + +/******************************************************************************* + * Initialize the UART + ******************************************************************************/ +void tsp_early_platform_setup(void) +{ + /* + * Initialize a different console than already in use to display + * messages from TSP + */ + console_init(ZYNQMP_UART_BASE, zynqmp_get_uart_clk(), + ZYNQMP_UART_BAUDRATE); + + /* Initialize the platform config for future decision making */ + zynqmp_config_setup(); +} + +/******************************************************************************* + * Perform platform specific setup placeholder + ******************************************************************************/ +void tsp_platform_setup(void) +{ + plat_arm_gic_driver_init(); + plat_arm_gic_init(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup here. At the + * moment this is only intializes the MMU + ******************************************************************************/ +void tsp_plat_arch_setup(void) +{ + arm_setup_page_tables(BL32_BASE, + BL32_END - BL32_BASE, + BL_CODE_BASE, + BL_CODE_LIMIT, + BL_RO_DATA_BASE, + BL_RO_DATA_LIMIT, + BL32_COHERENT_RAM_BASE, + BL32_COHERENT_RAM_LIMIT + ); + enable_mmu_el1(0); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/zynqmp_def.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/zynqmp_def.h new file mode 100644 index 0000000..65bc25f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/zynqmp_def.h @@ -0,0 +1,208 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ZYNQMP_DEF_H__ +#define __ZYNQMP_DEF_H__ + +#include + +#define ZYNQMP_CONSOLE_ID_cadence 1 +#define ZYNQMP_CONSOLE_ID_cadence0 1 +#define ZYNQMP_CONSOLE_ID_cadence1 2 +#define ZYNQMP_CONSOLE_ID_dcc 3 + +#define ZYNQMP_CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE) + +/* Firmware Image Package */ +#define ZYNQMP_PRIMARY_CPU 0 + +/* Memory location options for Shared data and TSP in ZYNQMP */ +#define ZYNQMP_IN_TRUSTED_SRAM 0 +#define ZYNQMP_IN_TRUSTED_DRAM 1 + +/******************************************************************************* + * ZYNQMP memory map related constants + ******************************************************************************/ +/* Aggregate of all devices in the first GB */ +#define DEVICE0_BASE 0xFF000000 +#define DEVICE0_SIZE 0x00E00000 +#define DEVICE1_BASE 0xF9000000 +#define DEVICE1_SIZE 0x00800000 + +/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ +#define CRF_APB_BASE 0xFD1A0000 +#define CRF_APB_SIZE 0x00600000 + +/* CRF registers and bitfields */ +#define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104) + +#define CRF_APB_RST_FPD_APU_ACPU_RESET (1 << 0) +#define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (1 << 10) + +/* CRL registers and bitfields */ +#define CRL_APB_BASE 0xFF5E0000 +#define CRL_APB_RPLL_CTRL (CRL_APB_BASE + 0x30) +#define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_BASE + 0x128) +#define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200) +#define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218) + +#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1 << 24) + +#define CRL_APB_RPLL_CTRL_BYPASS (1 << 3) + +#define CRL_APB_RESET_CTRL_SOFT_RESET (1 << 4) + +#define CRL_APB_BOOT_MODE_MASK (0xf << 0) +#define ZYNQMP_BOOTMODE_JTAG 0 + +/* system counter registers and bitfields */ +#define IOU_SCNTRS_BASE 0xFF260000 +#define IOU_SCNTRS_CONTROL (IOU_SCNTRS_BASE + 0) +#define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20) + +#define IOU_SCNTRS_CONTROL_EN (1 << 0) + +/* APU registers and bitfields */ +#define APU_BASE 0xFD5C0000 +#define APU_CONFIG_0 (APU_BASE + 0x20) +#define APU_RVBAR_L_0 (APU_BASE + 0x40) +#define APU_RVBAR_H_0 (APU_BASE + 0x44) +#define APU_PWRCTL (APU_BASE + 0x90) + +#define APU_CONFIG_0_VINITHI_SHIFT 8 +#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1 +#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2 +#define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4 +#define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8 + +/* PMU registers and bitfields */ +#define PMU_GLOBAL_BASE 0xFFD80000 +#define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0) +#define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48) +#define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110) +#define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118) +#define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c) +#define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120) + +#define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4) + +/******************************************************************************* + * CCI-400 related constants + ******************************************************************************/ +#define PLAT_ARM_CCI_BASE 0xFD6E0000 +#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3 +#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4 + +/******************************************************************************* + * GIC-400 & interrupt handling related constants + ******************************************************************************/ +#define BASE_GICD_BASE 0xF9010000 +#define BASE_GICC_BASE 0xF9020000 +#define BASE_GICH_BASE 0xF9040000 +#define BASE_GICV_BASE 0xF9060000 + +#define IRQ_SEC_IPI_APU 67 +#define ARM_IRQ_SEC_PHY_TIMER 29 + +#define ARM_IRQ_SEC_SGI_0 8 +#define ARM_IRQ_SEC_SGI_1 9 +#define ARM_IRQ_SEC_SGI_2 10 +#define ARM_IRQ_SEC_SGI_3 11 +#define ARM_IRQ_SEC_SGI_4 12 +#define ARM_IRQ_SEC_SGI_5 13 +#define ARM_IRQ_SEC_SGI_6 14 +#define ARM_IRQ_SEC_SGI_7 15 + +#define MAX_INTR_EL3 128 + +/******************************************************************************* + * UART related constants + ******************************************************************************/ +#define ZYNQMP_UART0_BASE 0xFF000000 +#define ZYNQMP_UART1_BASE 0xFF001000 + +#if ZYNQMP_CONSOLE_IS(cadence) +# define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE +#elif ZYNQMP_CONSOLE_IS(cadence1) +# define ZYNQMP_UART_BASE ZYNQMP_UART1_BASE +#else +# error "invalid ZYNQMP_CONSOLE" +#endif + +#define PLAT_ARM_CRASH_UART_BASE ZYNQMP_UART_BASE +/* impossible to call C routine how it is done now - hardcode any value */ +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ 100000000 /* FIXME */ + +/* Must be non zero */ +#define ZYNQMP_UART_BAUDRATE 115200 +#define ARM_CONSOLE_BAUDRATE ZYNQMP_UART_BAUDRATE + +/* Silicon version detection */ +#define ZYNQMP_SILICON_VER_MASK 0xF000 +#define ZYNQMP_SILICON_VER_SHIFT 12 +#define ZYNQMP_CSU_VERSION_SILICON 0 +#define ZYNQMP_CSU_VERSION_EP108 1 +#define ZYNQMP_CSU_VERSION_VELOCE 2 +#define ZYNQMP_CSU_VERSION_QEMU 3 + +#define ZYNQMP_RTL_VER_MASK 0xFF0 +#define ZYNQMP_RTL_VER_SHIFT 4 + +#define ZYNQMP_PS_VER_MASK 0xF +#define ZYNQMP_PS_VER_SHIFT 0 + +#define ZYNQMP_CSU_BASEADDR 0xFFCA0000 +#define ZYNQMP_CSU_IDCODE_OFFSET 0x40 + +#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0 +#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFF << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT) +#define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093 + +#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12 +#define ZYNQMP_CSU_IDCODE_SVD_MASK (0xE << ZYNQMP_CSU_IDCODE_SVD_SHIFT) +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15 +#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xF << ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT) +#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19 +#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3 << ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT) +#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21 +#define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7F << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT) +#define ZYNQMP_CSU_IDCODE_FAMILY 0x23 + +#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28 +#define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xF << ZYNQMP_CSU_IDCODE_REVISION_SHIFT) +#define ZYNQMP_CSU_IDCODE_REVISION 0 + +#define ZYNQMP_CSU_VERSION_OFFSET 0x44 + +/* Access control register defines */ +#define ACTLR_EL3_L2ACTLR_BIT (1 << 6) +#define ACTLR_EL3_CPUACTLR_BIT (1 << 0) + +#endif /* __ZYNQMP_DEF_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/zynqmp_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/zynqmp_private.h new file mode 100644 index 0000000..abcdebc --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/plat/xilinx/zynqmp/zynqmp_private.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ZYNQMP_PRIVATE_H__ +#define __ZYNQMP_PRIVATE_H__ + +#include + +void zynqmp_config_setup(void); + +/* ZynqMP specific functions */ +unsigned int zynqmp_get_uart_clk(void); +int zynqmp_is_pmu_up(void); +unsigned int zynqmp_get_bootmode(void); +unsigned int zynqmp_get_silicon_id(void); + +/* For FSBL handover */ +void fsbl_atf_handover(entry_point_info_t *bl32_image_ep_info, + entry_point_info_t *bl33_image_ep_info); + +#endif /* __ZYNQMP_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/readme.md b/IPL/SDK/v3m/src/arm-trusted-firmware/readme.md new file mode 100644 index 0000000..d9a1714 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/readme.md @@ -0,0 +1,197 @@ +ARM Trusted Firmware - version 1.3 +================================== + +ARM Trusted Firmware provides a reference implementation of secure world +software for [ARMv8-A], including a [Secure Monitor] [TEE-SMC] executing at +Exception Level 3 (EL3). It implements various ARM interface standards, such as +the Power State Coordination Interface ([PSCI]), Trusted Board Boot Requirements +(TBBR, ARM DEN0006C-1) and [SMC Calling Convention][SMCCC]. As far as possible +the code is designed for reuse or porting to other ARMv8-A model and hardware +platforms. + +ARM will continue development in collaboration with interested parties to +provide a full reference implementation of PSCI, TBBR and Secure Monitor code +to the benefit of all developers working with ARMv8-A TrustZone technology. + + +License +------- + +The software is provided under a BSD-3-Clause [license]. Contributions to this +project are accepted under the same license with developer sign-off as +described in the [Contributing Guidelines]. + +This project contains code from other projects as listed below. The original +license text is included in those source files. + +* The stdlib source code is derived from FreeBSD code. + +* The libfdt source code is dual licensed. It is used by this project under + the terms of the BSD-2-Clause license. + + +This Release +------------ + +This release provides a suitable starting point for productization of secure +world boot and runtime firmware, executing in either the AArch32 or AArch64 +execution state. + +Users are encouraged to do their own security validation, including penetration +testing, on any secure world code derived from ARM Trusted Firmware. + +### Functionality + +* Initialization of the secure world (for example, exception vectors, control + registers, interrupt controller and interrupts for the platform), before + transitioning into the normal world at the Exception Level and Register + Width specified by the platform. + +* Library support for CPU specific reset and power down sequences. This + includes support for errata workarounds. + +* Drivers for both versions 2.0 and 3.0 of the ARM Generic Interrupt + Controller specifications (GICv2 and GICv3). The latter also enables GICv3 + hardware systems that do not contain legacy GICv2 support. + +* Drivers to enable standard initialization of ARM System IP, for example + Cache Coherent Interconnect (CCI), Cache Coherent Network (CCN), Network + Interconnect (NIC) and TrustZone Controller (TZC). + +* SMC (Secure Monitor Call) handling, conforming to the [SMC Calling + Convention][SMCCC] using an EL3 runtime services framework. + +* [PSCI] library support for the Secondary CPU Boot, CPU Hotplug, CPU Idle + and System Shutdown/Reset/Suspend use-cases. + This library is pre-integrated with the provided AArch64 EL3 Runtime + Software, and is also suitable for integration into other EL3 Runtime + Software. + +* A minimal AArch32 Secure Payload to demonstrate [PSCI] library integration + on platforms with AArch32 EL3 Runtime Software. + +* Secure Monitor library code such as world switching, EL1 context management + and interrupt routing. + When using the provided AArch64 EL3 Runtime Software, this must be + integrated with a Secure-EL1 Payload Dispatcher (SPD) component to + customize the interaction with a Secure-EL1 Payload (SP), for example a + Secure OS. + +* A Test Secure-EL1 Payload and Dispatcher to demonstrate AArch64 Secure + Monitor functionality and Secure-EL1 interaction with PSCI. + +* AArch64 SPDs for the [OP-TEE Secure OS] and [NVidia Trusted Little Kernel] + [NVidia TLK]. + +* A Trusted Board Boot implementation, conforming to all mandatory TBBR + requirements. This includes image authentication using certificates, a + Firmware Update (or recovery mode) boot flow, and packaging of the various + firmware images into a Firmware Image Package (FIP) to be loaded from + non-volatile storage. + The TBBR implementation is currently only supported in the AArch64 build. + +* Support for alternative boot flows. Some platforms have their own boot + firmware and only require the AArch64 EL3 Runtime Software provided by this + project. Other platforms require minimal initialization before booting + into an arbitrary EL3 payload. + +For a full description of functionality and implementation details, please +see the [Firmware Design] and supporting documentation. The [Change Log] +provides details of changes made since the last release. + +### Platforms + +The AArch64 build of this release has been tested on variants r0, r1 and r2 +of the [Juno ARM Development Platform] [Juno] with [Linaro Release 16.06]. + +The AArch64 build of this release has been tested on the following ARM +[FVP]s (64-bit host machine only): + +* `Foundation_Platform` (Version 10.1, Build 10.1.32) +* `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701) +* `FVP_Base_Cortex-A57x4-A53x4` (Version 7.7, Build 0.8.7701) +* `FVP_Base_Cortex-A57x1-A53x1` (Version 7.7, Build 0.8.7701) +* `FVP_Base_Cortex-A57x2-A53x4` (Version 7.7, Build 0.8.7701) + +The AArch32 build of this release has been tested on the following ARM +[FVP]s (64-bit host machine only): + +* `FVP_Base_AEMv8A-AEMv8A` (Version 7.7, Build 0.8.7701) +* `FVP_Base_Cortex-A32x4` (Version 10.1, Build 10.1.32) + +The Foundation FVP can be downloaded free of charge. The Base FVPs can be +licensed from ARM: see [www.arm.com/fvp] [FVP]. + +This release also contains the following platform support: + +* MediaTek MT6795 and MT8173 SoCs +* NVidia T210 and T132 SoCs +* QEMU emulator +* RockChip RK3368 and RK3399 SoCs +* Xilinx Zynq UltraScale + MPSoC + +### Still to Come + +* AArch32 TBBR support and ongoing TBBR alignment. + +* More platform support. + +* Ongoing support for new architectural features, CPUs and System IP. + +* Ongoing [PSCI] alignment and feature support. + +* Ongoing security hardening, optimization and quality improvements. + +For a full list of detailed issues in the current code, please see the [Change +Log] and the [GitHub issue tracker]. + + +Getting Started +--------------- + +Get the Trusted Firmware source code from +[GitHub](https://www.github.com/ARM-software/arm-trusted-firmware). + +See the [User Guide] for instructions on how to install, build and use +the Trusted Firmware with the ARM [FVP]s. + +See the [Firmware Design] for information on how the ARM Trusted Firmware works. + +See the [Porting Guide] as well for information about how to use this +software on another ARMv8-A platform. + +See the [Contributing Guidelines] for information on how to contribute to this +project and the [Acknowledgments] file for a list of contributors to the +project. + +### Feedback and support + +ARM welcomes any feedback on the Trusted Firmware. Please send feedback using +the [GitHub issue tracker]. + +ARM licensees may contact ARM directly via their partner managers. + + +- - - - - - - - - - - - - - - - - - - - - - - - - - + +_Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved._ + + +[License]: ./license.md "BSD license for ARM Trusted Firmware" +[Contributing Guidelines]: ./contributing.md "Guidelines for contributors" +[Acknowledgments]: ./acknowledgements.md "Contributor acknowledgments" +[Change Log]: ./docs/change-log.md +[User Guide]: ./docs/user-guide.md +[Firmware Design]: ./docs/firmware-design.md +[Porting Guide]: ./docs/porting-guide.md + +[ARMv8-A]: http://www.arm.com/products/processors/armv8-architecture.php "ARMv8-A Architecture" +[FVP]: http://www.arm.com/fvp "ARM's Fixed Virtual Platforms" +[Juno]: http://www.arm.com/products/tools/development-boards/versatile-express/juno-arm-development-platform.php "Juno ARM Development Platform" +[PSCI]: http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf "Power State Coordination Interface PDD (ARM DEN 0022C)" +[SMCCC]: http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html "SMC Calling Convention PDD (ARM DEN 0028A)" +[TEE-SMC]: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php "Secure Monitor and TEEs" +[GitHub issue tracker]: https://github.com/ARM-software/tf-issues/issues +[OP-TEE Secure OS]: https://github.com/OP-TEE/optee_os +[NVidia TLK]: http://nv-tegra.nvidia.com/gitweb/?p=3rdparty/ote_partner/tlk.git;a=summary +[Linaro Release 16.06]: https://community.arm.com/docs/DOC-10952#jive_content_id_Linaro_Release_1606 diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed.mk new file mode 100644 index 0000000..5a0854b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed.mk @@ -0,0 +1,40 @@ +# +# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2015-2016, Renesas Electronics Corporation. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +OPTEED_DIR := services/spd/opteed +SPD_INCLUDES := + +SPD_SOURCES := services/spd/opteed/opteed_common.c \ + services/spd/opteed/opteed_helpers.S \ + services/spd/opteed/opteed_main.c \ + services/spd/opteed/opteed_pm.c + +NEED_BL32 := no diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_common.c new file mode 100644 index 0000000..2f20b7c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_common.c @@ -0,0 +1,128 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "opteed_private.h" + +/******************************************************************************* + * Given a OPTEE entrypoint info pointer, entry point PC, register width, + * cpu id & pointer to a context data structure, this function will + * initialize OPTEE context and entry point info for OPTEE. + ******************************************************************************/ +void opteed_init_optee_ep_state(struct entry_point_info *optee_entry_point, + uint32_t rw, uint64_t pc, + optee_context_t *optee_ctx) +{ + uint32_t ep_attr; + + /* Passing a NULL context is a critical programming error */ + assert(optee_ctx); + assert(optee_entry_point); + assert(pc); + + /* Associate this context with the cpu specified */ + optee_ctx->mpidr = read_mpidr_el1(); + optee_ctx->state = 0; + set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_OFF); + + cm_set_context(&optee_ctx->cpu_ctx, SECURE); + + /* initialise an entrypoint to set up the CPU context */ + ep_attr = SECURE | EP_ST_ENABLE; + if (read_sctlr_el3() & SCTLR_EE_BIT) + ep_attr |= EP_EE_BIG; + SET_PARAM_HEAD(optee_entry_point, PARAM_EP, VERSION_1, ep_attr); + optee_entry_point->pc = pc; + if (rw == OPTEE_AARCH64) + optee_entry_point->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + else + optee_entry_point->spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM, + SPSR_E_LITTLE, + DAIF_FIQ_BIT | + DAIF_IRQ_BIT | + DAIF_ABT_BIT); + memset(&optee_entry_point->args, 0, sizeof(optee_entry_point->args)); +} + +/******************************************************************************* + * This function takes an OPTEE context pointer and: + * 1. Applies the S-EL1 system register context from optee_ctx->cpu_ctx. + * 2. Saves the current C runtime state (callee saved registers) on the stack + * frame and saves a reference to this state. + * 3. Calls el3_exit() so that the EL3 system and general purpose registers + * from the optee_ctx->cpu_ctx are used to enter the OPTEE image. + ******************************************************************************/ +uint64_t opteed_synchronous_sp_entry(optee_context_t *optee_ctx) +{ + uint64_t rc; + + assert(optee_ctx != NULL); + assert(optee_ctx->c_rt_ctx == 0); + + /* Apply the Secure EL1 system register context and switch to it */ + assert(cm_get_context(SECURE) == &optee_ctx->cpu_ctx); + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + + rc = opteed_enter_sp(&optee_ctx->c_rt_ctx); +#if DEBUG + optee_ctx->c_rt_ctx = 0; +#endif + + return rc; +} + + +/******************************************************************************* + * This function takes an OPTEE context pointer and: + * 1. Saves the S-EL1 system register context tp optee_ctx->cpu_ctx. + * 2. Restores the current C runtime state (callee saved registers) from the + * stack frame using the reference to this state saved in opteed_enter_sp(). + * 3. It does not need to save any general purpose or EL3 system register state + * as the generic smc entry routine should have saved those. + ******************************************************************************/ +void opteed_synchronous_sp_exit(optee_context_t *optee_ctx, uint64_t ret) +{ + assert(optee_ctx != NULL); + /* Save the Secure EL1 system register context */ + assert(cm_get_context(SECURE) == &optee_ctx->cpu_ctx); + cm_el1_sysregs_context_save(SECURE); + + assert(optee_ctx->c_rt_ctx != 0); + opteed_exit_sp(optee_ctx->c_rt_ctx, ret); + + /* Should never reach here */ + assert(0); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_helpers.S new file mode 100644 index 0000000..32c38f1 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_helpers.S @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "opteed_private.h" + + .global opteed_enter_sp + /* --------------------------------------------- + * This function is called with SP_EL0 as stack. + * Here we stash our EL3 callee-saved registers + * on to the stack as a part of saving the C + * runtime and enter the secure payload. + * 'x0' contains a pointer to the memory where + * the address of the C runtime context is to be + * saved. + * --------------------------------------------- + */ +func opteed_enter_sp + /* Make space for the registers that we're going to save */ + mov x3, sp + str x3, [x0, #0] + sub sp, sp, #OPTEED_C_RT_CTX_SIZE + + /* Save callee-saved registers on to the stack */ + stp x19, x20, [sp, #OPTEED_C_RT_CTX_X19] + stp x21, x22, [sp, #OPTEED_C_RT_CTX_X21] + stp x23, x24, [sp, #OPTEED_C_RT_CTX_X23] + stp x25, x26, [sp, #OPTEED_C_RT_CTX_X25] + stp x27, x28, [sp, #OPTEED_C_RT_CTX_X27] + stp x29, x30, [sp, #OPTEED_C_RT_CTX_X29] + + /* --------------------------------------------- + * Everything is setup now. el3_exit() will + * use the secure context to restore to the + * general purpose and EL3 system registers to + * ERET into OPTEE. + * --------------------------------------------- + */ + b el3_exit +endfunc opteed_enter_sp + + /* --------------------------------------------- + * This function is called 'x0' pointing to a C + * runtime context saved in opteed_enter_sp(). It + * restores the saved registers and jumps to + * that runtime with 'x0' as the new sp. This + * destroys the C runtime context that had been + * built on the stack below the saved context by + * the caller. Later the second parameter 'x1' + * is passed as return value to the caller + * --------------------------------------------- + */ + .global opteed_exit_sp +func opteed_exit_sp + /* Restore the previous stack */ + mov sp, x0 + + /* Restore callee-saved registers on to the stack */ + ldp x19, x20, [x0, #(OPTEED_C_RT_CTX_X19 - OPTEED_C_RT_CTX_SIZE)] + ldp x21, x22, [x0, #(OPTEED_C_RT_CTX_X21 - OPTEED_C_RT_CTX_SIZE)] + ldp x23, x24, [x0, #(OPTEED_C_RT_CTX_X23 - OPTEED_C_RT_CTX_SIZE)] + ldp x25, x26, [x0, #(OPTEED_C_RT_CTX_X25 - OPTEED_C_RT_CTX_SIZE)] + ldp x27, x28, [x0, #(OPTEED_C_RT_CTX_X27 - OPTEED_C_RT_CTX_SIZE)] + ldp x29, x30, [x0, #(OPTEED_C_RT_CTX_X29 - OPTEED_C_RT_CTX_SIZE)] + + /* --------------------------------------------- + * This should take us back to the instruction + * after the call to the last opteed_enter_sp(). + * Place the second parameter to x0 so that the + * caller will see it as a return value from the + * original entry call + * --------------------------------------------- + */ + mov x0, x1 + ret +endfunc opteed_exit_sp \ No newline at end of file diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_main.c new file mode 100644 index 0000000..9770fb9 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_main.c @@ -0,0 +1,437 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +/******************************************************************************* + * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a + * plug-in component to the Secure Monitor, registered as a runtime service. The + * SPD is expected to be a functional extension of the Secure Payload (SP) that + * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting + * the Trusted OS/Applications range to the dispatcher. The SPD will either + * handle the request locally or delegate it to the Secure Payload. It is also + * responsible for initialising and maintaining communication with the SP. + ******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "opteed_private.h" +#include "teesmc_opteed_macros.h" +#include "teesmc_opteed.h" + +/******************************************************************************* + * Address of the entrypoint vector table in OPTEE. It is + * initialised once on the primary core after a cold boot. + ******************************************************************************/ +optee_vectors_t *optee_vectors; + +/******************************************************************************* + * Array to keep track of per-cpu OPTEE state + ******************************************************************************/ +optee_context_t opteed_sp_context[OPTEED_CORE_COUNT]; +uint32_t opteed_rw; + + + +static int32_t opteed_init(void); + +/******************************************************************************* + * This function is the handler registered for S-EL1 interrupts by the + * OPTEED. It validates the interrupt and upon success arranges entry into + * the OPTEE at 'optee_fiq_entry()' for handling the interrupt. + ******************************************************************************/ +static uint64_t opteed_sel1_interrupt_handler(uint32_t id, + uint32_t flags, + void *handle, + void *cookie) +{ + uint32_t linear_id; + optee_context_t *optee_ctx; + + /* Check the security state when the exception was generated */ + assert(get_interrupt_src_ss(flags) == NON_SECURE); + + /* Sanity check the pointer to this cpu's context */ + assert(handle == cm_get_context(NON_SECURE)); + + /* Save the non-secure context before entering the OPTEE */ + cm_el1_sysregs_context_save(NON_SECURE); + + /* Get a reference to this cpu's OPTEE context */ + linear_id = plat_my_core_pos(); + optee_ctx = &opteed_sp_context[linear_id]; + assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE)); + + cm_set_elr_el3(SECURE, (uint64_t)&optee_vectors->fiq_entry); + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + + /* + * Tell the OPTEE that it has to handle an FIQ (synchronously). + * Also the instruction in normal world where the interrupt was + * generated is passed for debugging purposes. It is safe to + * retrieve this address from ELR_EL3 as the secure context will + * not take effect until el3_exit(). + */ + SMC_RET1(&optee_ctx->cpu_ctx, read_elr_el3()); +} + +/******************************************************************************* + * OPTEE Dispatcher setup. The OPTEED finds out the OPTEE entrypoint and type + * (aarch32/aarch64) if not already known and initialises the context for entry + * into OPTEE for its initialization. + ******************************************************************************/ +int32_t opteed_setup(void) +{ + entry_point_info_t *optee_ep_info; + uint32_t linear_id; + + linear_id = plat_my_core_pos(); + + /* + * Get information about the Secure Payload (BL32) image. Its + * absence is a critical failure. TODO: Add support to + * conditionally include the SPD service + */ + optee_ep_info = bl31_plat_get_next_image_ep_info(SECURE); + if (!optee_ep_info) { + WARN("No OPTEE provided by BL2 boot loader, Booting device" + " without OPTEE initialization. SMC`s destined for OPTEE" + " will return SMC_UNK\n"); + return 1; + } + + /* + * If there's no valid entry point for SP, we return a non-zero value + * signalling failure initializing the service. We bail out without + * registering any handlers + */ + if (!optee_ep_info->pc) + return 1; + + /* + * We could inspect the SP image and determine it's execution + * state i.e whether AArch32 or AArch64. Assuming it's AArch32 + * for the time being. + */ + opteed_rw = OPTEE_AARCH64; + opteed_init_optee_ep_state(optee_ep_info, + opteed_rw, + optee_ep_info->pc, + &opteed_sp_context[linear_id]); + + /* + * All OPTEED initialization done. Now register our init function with + * BL31 for deferred invocation + */ + bl31_register_bl32_init(&opteed_init); + + return 0; +} + +/******************************************************************************* + * This function passes control to the OPTEE image (BL32) for the first time + * on the primary cpu after a cold boot. It assumes that a valid secure + * context has already been created by opteed_setup() which can be directly + * used. It also assumes that a valid non-secure context has been + * initialised by PSCI so it does not need to save and restore any + * non-secure state. This function performs a synchronous entry into + * OPTEE. OPTEE passes control back to this routine through a SMC. + ******************************************************************************/ +static int32_t opteed_init(void) +{ + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + entry_point_info_t *optee_entry_point; + uint64_t rc; + + /* + * Get information about the OPTEE (BL32) image. Its + * absence is a critical failure. + */ + optee_entry_point = bl31_plat_get_next_image_ep_info(SECURE); + assert(optee_entry_point); + + cm_init_my_context(optee_entry_point); + + /* + * Arrange for an entry into OPTEE. It will be returned via + * OPTEE_ENTRY_DONE case + */ + rc = opteed_synchronous_sp_entry(optee_ctx); + assert(rc != 0); + + return rc; +} + + +/******************************************************************************* + * This function is responsible for handling all SMCs in the Trusted OS/App + * range from the non-secure state as defined in the SMC Calling Convention + * Document. It is also responsible for communicating with the Secure + * payload to delegate work and return results back to the non-secure + * state. Lastly it will also return any information that OPTEE needs to do + * the work assigned to it. + ******************************************************************************/ +uint64_t opteed_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + cpu_context_t *ns_cpu_context; + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + uint64_t rc; + + /* + * Determine which security state this SMC originated from + */ + + if (is_caller_non_secure(flags)) { + /* + * This is a fresh request from the non-secure client. + * The parameters are in x1 and x2. Figure out which + * registers need to be preserved, save the non-secure + * state and send the request to the secure payload. + */ + assert(handle == cm_get_context(NON_SECURE)); + + cm_el1_sysregs_context_save(NON_SECURE); + + /* + * We are done stashing the non-secure context. Ask the + * OPTEE to do the work now. + */ + + /* + * Verify if there is a valid context to use, copy the + * operation type and parameters to the secure context + * and jump to the fast smc entry point in the secure + * payload. Entry into S-EL1 will take place upon exit + * from this function. + */ + assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE)); + + /* Set appropriate entry for SMC. + * We expect OPTEE to manage the PSTATE.I and PSTATE.F + * flags as appropriate. + */ + if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) { + cm_set_elr_el3(SECURE, (uint64_t) + &optee_vectors->fast_smc_entry); + } else { + cm_set_elr_el3(SECURE, (uint64_t) + &optee_vectors->std_smc_entry); + } + + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + + write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), + CTX_GPREG_X4, + read_ctx_reg(get_gpregs_ctx(handle), + CTX_GPREG_X4)); + write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), + CTX_GPREG_X5, + read_ctx_reg(get_gpregs_ctx(handle), + CTX_GPREG_X5)); + write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), + CTX_GPREG_X6, + read_ctx_reg(get_gpregs_ctx(handle), + CTX_GPREG_X6)); + /* Propagate hypervisor client ID */ + write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), + CTX_GPREG_X7, + read_ctx_reg(get_gpregs_ctx(handle), + CTX_GPREG_X7)); + + SMC_RET4(&optee_ctx->cpu_ctx, smc_fid, x1, x2, x3); + } + + /* + * Returning from OPTEE + */ + + switch (smc_fid) { + /* + * OPTEE has finished initialising itself after a cold boot + */ + case TEESMC_OPTEED_RETURN_ENTRY_DONE: + /* + * Stash the OPTEE entry points information. This is done + * only once on the primary cpu + */ + assert(optee_vectors == NULL); + optee_vectors = (optee_vectors_t *) x1; + + if (optee_vectors) { + set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_ON); + + /* + * OPTEE has been successfully initialized. + * Register power management hooks with PSCI + */ + psci_register_spd_pm_hook(&opteed_pm); + + /* + * Register an interrupt handler for S-EL1 interrupts + * when generated during code executing in the + * non-secure state. + */ + flags = 0; + set_interrupt_rm_flag(flags, NON_SECURE); + rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, + opteed_sel1_interrupt_handler, + flags); + if (rc) + panic(); + } + + /* + * OPTEE reports completion. The OPTEED must have initiated + * the original request through a synchronous entry into + * OPTEE. Jump back to the original C runtime context. + */ + opteed_synchronous_sp_exit(optee_ctx, x1); + + + /* + * These function IDs is used only by OP-TEE to indicate it has + * finished: + * 1. turning itself on in response to an earlier psci + * cpu_on request + * 2. resuming itself after an earlier psci cpu_suspend + * request. + */ + case TEESMC_OPTEED_RETURN_ON_DONE: + case TEESMC_OPTEED_RETURN_RESUME_DONE: + + + /* + * These function IDs is used only by the SP to indicate it has + * finished: + * 1. suspending itself after an earlier psci cpu_suspend + * request. + * 2. turning itself off in response to an earlier psci + * cpu_off request. + */ + case TEESMC_OPTEED_RETURN_OFF_DONE: + case TEESMC_OPTEED_RETURN_SUSPEND_DONE: + case TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE: + case TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE: + + /* + * OPTEE reports completion. The OPTEED must have initiated the + * original request through a synchronous entry into OPTEE. + * Jump back to the original C runtime context, and pass x1 as + * return value to the caller + */ + opteed_synchronous_sp_exit(optee_ctx, x1); + + /* + * OPTEE is returning from a call or being preempted from a call, in + * either case execution should resume in the normal world. + */ + case TEESMC_OPTEED_RETURN_CALL_DONE: + /* + * This is the result from the secure client of an + * earlier request. The results are in x0-x3. Copy it + * into the non-secure context, save the secure state + * and return to the non-secure state. + */ + assert(handle == cm_get_context(SECURE)); + cm_el1_sysregs_context_save(SECURE); + + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* Restore non-secure state */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + + SMC_RET4(ns_cpu_context, x1, x2, x3, x4); + + /* + * OPTEE has finished handling a S-EL1 FIQ interrupt. Execution + * should resume in the normal world. + */ + case TEESMC_OPTEED_RETURN_FIQ_DONE: + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* + * Restore non-secure state. There is no need to save the + * secure system register context since OPTEE was supposed + * to preserve it during S-EL1 interrupt handling. + */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + + SMC_RET0((uint64_t) ns_cpu_context); + + default: + panic(); + } +} + +/* Define an OPTEED runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + opteed_fast, + + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_FAST, + opteed_setup, + opteed_smc_handler +); + +/* Define an OPTEED runtime service descriptor for standard SMC calls */ +DECLARE_RT_SVC( + opteed_std, + + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_STD, + NULL, + opteed_smc_handler +); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_pm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_pm.c new file mode 100644 index 0000000..273cbe6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_pm.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include "opteed_private.h" + +/******************************************************************************* + * The target cpu is being turned on. Allow the OPTEED/OPTEE to perform any + * actions needed. Nothing at the moment. + ******************************************************************************/ +static void opteed_cpu_on_handler(uint64_t target_cpu) +{ +} + +/******************************************************************************* + * This cpu is being turned off. Allow the OPTEED/OPTEE to perform any actions + * needed + ******************************************************************************/ +static int32_t opteed_cpu_off_handler(uint64_t unused) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + + assert(optee_vectors); + assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); + + /* Program the entry point and enter OPTEE */ + cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_off_entry); + rc = opteed_synchronous_sp_entry(optee_ctx); + + /* + * Read the response from OPTEE. A non-zero return means that + * something went wrong while communicating with OPTEE. + */ + if (rc != 0) + panic(); + + /* + * Reset OPTEE's context for a fresh start when this cpu is turned on + * subsequently. + */ + set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_OFF); + + return 0; +} + +/******************************************************************************* + * This cpu is being suspended. S-EL1 state must have been saved in the + * resident cpu (mpidr format) if it is a UP/UP migratable OPTEE. + ******************************************************************************/ +static void opteed_cpu_suspend_handler(uint64_t max_off_pwrlvl) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; +#if PLAT_rcar + uint64_t psci_func; +#endif + + assert(optee_vectors); + assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); + +#if PLAT_rcar + if (max_off_pwrlvl == (uint64_t)PLAT_MAX_PWR_LVL) { + psci_func = TFW_ARG_SYSTEM_SUSPEND; + } else { + psci_func = TFW_ARG_CPU_SUSPEND; + } + write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), + CTX_GPREG_X0, psci_func); +#endif + + /* Program the entry point and enter OPTEE */ + cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_suspend_entry); + rc = opteed_synchronous_sp_entry(optee_ctx); + + /* + * Read the response from OPTEE. A non-zero return means that + * something went wrong while communicating with OPTEE. + */ + if (rc != 0) + panic(); + + /* Update its context to reflect the state OPTEE is in */ + set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_SUSPEND); +} + +/******************************************************************************* + * This cpu has been turned on. Enter OPTEE to initialise S-EL1 and other bits + * before passing control back to the Secure Monitor. Entry in S-El1 is done + * after initialising minimal architectural state that guarantees safe + * execution. + ******************************************************************************/ +static void opteed_cpu_on_finish_handler(uint64_t unused) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + entry_point_info_t optee_on_entrypoint; + + assert(optee_vectors); + assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_OFF); + + opteed_init_optee_ep_state(&optee_on_entrypoint, opteed_rw, + (uint64_t)&optee_vectors->cpu_on_entry, + optee_ctx); + + /* Initialise this cpu's secure context */ + cm_init_my_context(&optee_on_entrypoint); + + /* Enter OPTEE */ + rc = opteed_synchronous_sp_entry(optee_ctx); + + /* + * Read the response from OPTEE. A non-zero return means that + * something went wrong while communicating with OPTEE. + */ + if (rc != 0) + panic(); + + /* Update its context to reflect the state OPTEE is in */ + set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_ON); +} + +/******************************************************************************* + * This cpu has resumed from suspend. The OPTEED saved the OPTEE context when it + * completed the preceding suspend call. Use that context to program an entry + * into OPTEE to allow it to do any remaining book keeping + ******************************************************************************/ +static void opteed_cpu_suspend_finish_handler(uint64_t max_off_pwrlvl) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + + assert(optee_vectors); + assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_SUSPEND); + + /* Program the entry point, max_off_pwrlvl and enter the SP */ + write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx), + CTX_GPREG_X0, + max_off_pwrlvl); + cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_resume_entry); + rc = opteed_synchronous_sp_entry(optee_ctx); + + /* + * Read the response from OPTEE. A non-zero return means that + * something went wrong while communicating with OPTEE. + */ + if (rc != 0) + panic(); + + /* Update its context to reflect the state OPTEE is in */ + set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_ON); +} + +/******************************************************************************* + * Return the type of OPTEE the OPTEED is dealing with. Report the current + * resident cpu (mpidr format) if it is a UP/UP migratable OPTEE. + ******************************************************************************/ +static int32_t opteed_cpu_migrate_info(uint64_t *resident_cpu) +{ + return OPTEE_MIGRATE_INFO; +} + +/******************************************************************************* + * System is about to be switched off. Allow the OPTEED/OPTEE to perform + * any actions needed. + ******************************************************************************/ +static void opteed_system_off(void) +{ + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + + assert(optee_vectors); + assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); + + /* Program the entry point */ + cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->system_off_entry); + + /* Enter OPTEE. We do not care about the return value because we + * must continue the shutdown anyway */ + opteed_synchronous_sp_entry(optee_ctx); +} + +/******************************************************************************* + * System is about to be reset. Allow the OPTEED/OPTEE to perform + * any actions needed. + ******************************************************************************/ +static void opteed_system_reset(void) +{ + uint32_t linear_id = plat_my_core_pos(); + optee_context_t *optee_ctx = &opteed_sp_context[linear_id]; + + assert(optee_vectors); + assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON); + + /* Program the entry point */ + cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->system_reset_entry); + + /* Enter OPTEE. We do not care about the return value because we + * must continue the reset anyway */ + opteed_synchronous_sp_entry(optee_ctx); +} + + +/******************************************************************************* + * Structure populated by the OPTEE Dispatcher to be given a chance to + * perform any OPTEE bookkeeping before PSCI executes a power mgmt. + * operation. + ******************************************************************************/ +const spd_pm_ops_t opteed_pm = { + .svc_on = opteed_cpu_on_handler, + .svc_off = opteed_cpu_off_handler, + .svc_suspend = opteed_cpu_suspend_handler, + .svc_on_finish = opteed_cpu_on_finish_handler, + .svc_suspend_finish = opteed_cpu_suspend_finish_handler, + .svc_migrate = NULL, + .svc_migrate_info = opteed_cpu_migrate_info, + .svc_system_off = opteed_system_off, + .svc_system_reset = opteed_system_reset, +}; + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_private.h new file mode 100644 index 0000000..26cf976 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/opteed_private.h @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __OPTEED_PRIVATE_H__ +#define __OPTEED_PRIVATE_H__ + +#include +#include +#include +#include +#include + +/******************************************************************************* + * OPTEE PM state information e.g. OPTEE is suspended, uninitialised etc + * and macros to access the state information in the per-cpu 'state' flags + ******************************************************************************/ +#define OPTEE_PSTATE_OFF 0 +#define OPTEE_PSTATE_ON 1 +#define OPTEE_PSTATE_SUSPEND 2 +#define OPTEE_PSTATE_SHIFT 0 +#define OPTEE_PSTATE_MASK 0x3 +#define get_optee_pstate(state) ((state >> OPTEE_PSTATE_SHIFT) & \ + OPTEE_PSTATE_MASK) +#define clr_optee_pstate(state) (state &= ~(OPTEE_PSTATE_MASK \ + << OPTEE_PSTATE_SHIFT)) +#define set_optee_pstate(st, pst) do { \ + clr_optee_pstate(st); \ + st |= (pst & OPTEE_PSTATE_MASK) << \ + OPTEE_PSTATE_SHIFT; \ + } while (0) + + +/******************************************************************************* + * OPTEE execution state information i.e. aarch32 or aarch64 + ******************************************************************************/ +#define OPTEE_AARCH32 MODE_RW_32 +#define OPTEE_AARCH64 MODE_RW_64 + +/******************************************************************************* + * The OPTEED should know the type of OPTEE + ******************************************************************************/ +#define OPTEE_TYPE_UP PSCI_TOS_NOT_UP_MIG_CAP +#define OPTEE_TYPE_UPM PSCI_TOS_UP_MIG_CAP +#define OPTEE_TYPE_MP PSCI_TOS_NOT_PRESENT_MP + +/******************************************************************************* + * OPTEE migrate type information as known to the OPTEED. We assume that + * the OPTEED is dealing with an MP Secure Payload. + ******************************************************************************/ +#define OPTEE_MIGRATE_INFO OPTEE_TYPE_MP + +/******************************************************************************* + * Number of cpus that the present on this platform. TODO: Rely on a topology + * tree to determine this in the future to avoid assumptions about mpidr + * allocation + ******************************************************************************/ +#define OPTEED_CORE_COUNT PLATFORM_CORE_COUNT + +/******************************************************************************* + * Constants that allow assembler code to preserve callee-saved registers of the + * C runtime context while performing a security state switch. + ******************************************************************************/ +#define OPTEED_C_RT_CTX_X19 0x0 +#define OPTEED_C_RT_CTX_X20 0x8 +#define OPTEED_C_RT_CTX_X21 0x10 +#define OPTEED_C_RT_CTX_X22 0x18 +#define OPTEED_C_RT_CTX_X23 0x20 +#define OPTEED_C_RT_CTX_X24 0x28 +#define OPTEED_C_RT_CTX_X25 0x30 +#define OPTEED_C_RT_CTX_X26 0x38 +#define OPTEED_C_RT_CTX_X27 0x40 +#define OPTEED_C_RT_CTX_X28 0x48 +#define OPTEED_C_RT_CTX_X29 0x50 +#define OPTEED_C_RT_CTX_X30 0x58 +#define OPTEED_C_RT_CTX_SIZE 0x60 +#define OPTEED_C_RT_CTX_ENTRIES (OPTEED_C_RT_CTX_SIZE >> DWORD_SHIFT) + +/******************************************************************************* + * Parameter value to be passed from ARM Trusted FW to OP-TEE + ******************************************************************************/ +#if PLAT_rcar +/* optee_vector:cpu_suspend x0 */ +#define TFW_ARG_CPU_SUSPEND (0x0UL) +#define TFW_ARG_SYSTEM_SUSPEND (0x1UL) +#endif + +#ifndef __ASSEMBLY__ + +#include +#include + +typedef uint32_t optee_vector_isn_t; + +typedef struct optee_vectors { + optee_vector_isn_t std_smc_entry; + optee_vector_isn_t fast_smc_entry; + optee_vector_isn_t cpu_on_entry; + optee_vector_isn_t cpu_off_entry; + optee_vector_isn_t cpu_resume_entry; + optee_vector_isn_t cpu_suspend_entry; + optee_vector_isn_t fiq_entry; + optee_vector_isn_t system_off_entry; + optee_vector_isn_t system_reset_entry; +} optee_vectors_t; + +/* + * The number of arguments to save during a SMC call for OPTEE. + * Currently only x1 and x2 are used by OPTEE. + */ +#define OPTEE_NUM_ARGS 0x2 + +/* AArch64 callee saved general purpose register context structure. */ +DEFINE_REG_STRUCT(c_rt_regs, OPTEED_C_RT_CTX_ENTRIES); + +/* + * Compile time assertion to ensure that both the compiler and linker + * have the same double word aligned view of the size of the C runtime + * register context. + */ +CASSERT(OPTEED_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ + assert_spd_c_rt_regs_size_mismatch); + +/******************************************************************************* + * Structure which helps the OPTEED to maintain the per-cpu state of OPTEE. + * 'state' - collection of flags to track OPTEE state e.g. on/off + * 'mpidr' - mpidr to associate a context with a cpu + * 'c_rt_ctx' - stack address to restore C runtime context from after + * returning from a synchronous entry into OPTEE. + * 'cpu_ctx' - space to maintain OPTEE architectural state + ******************************************************************************/ +typedef struct optee_context { + uint32_t state; + uint64_t mpidr; + uint64_t c_rt_ctx; + cpu_context_t cpu_ctx; +} optee_context_t; + +/* OPTEED power management handlers */ +extern const spd_pm_ops_t opteed_pm; + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct optee_vectors; + +/******************************************************************************* + * Function & Data prototypes + ******************************************************************************/ +uint64_t opteed_enter_sp(uint64_t *c_rt_ctx); +void __dead2 opteed_exit_sp(uint64_t c_rt_ctx, uint64_t ret); +uint64_t opteed_synchronous_sp_entry(optee_context_t *optee_ctx); +void __dead2 opteed_synchronous_sp_exit(optee_context_t *optee_ctx, uint64_t ret); +void opteed_init_optee_ep_state(struct entry_point_info *optee_ep, + uint32_t rw, + uint64_t pc, + optee_context_t *optee_ctx); + +extern optee_context_t opteed_sp_context[OPTEED_CORE_COUNT]; +extern uint32_t opteed_rw; +extern struct optee_vectors *optee_vectors; +#endif /*__ASSEMBLY__*/ + +#endif /* __OPTEED_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/teesmc_opteed.h b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/teesmc_opteed.h new file mode 100644 index 0000000..7968d1f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/teesmc_opteed.h @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* Copyright (c) 2014, Linaro Limited. All rights reserved. */ + +#ifndef TEESMC_OPTEED_H +#define TEESMC_OPTEED_H + +/* + * This file specify SMC function IDs used when returning from TEE to the + * secure monitor. + * + * All SMC Function IDs indicates SMC32 Calling Convention but will carry + * full 64 bit values in the argument registers if invoked from Aarch64 + * mode. This violates the SMC Calling Convention, but since this + * convention only coveres API towards Normwal World it's something that + * only concerns the OP-TEE Dispatcher in ARM Trusted Firmware and OP-TEE + * OS at Secure EL1. + */ + +/* + * Issued when returning from initial entry. + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_ENTRY_DONE + * r1/x1 Pointer to entry vector + */ +#define TEESMC_OPTEED_FUNCID_RETURN_ENTRY_DONE 0 +#define TEESMC_OPTEED_RETURN_ENTRY_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_ENTRY_DONE) + + + +/* + * Issued when returning from "cpu_on" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_ON_DONE + * r1/x1 0 on success and anything else to indicate error condition + */ +#define TEESMC_OPTEED_FUNCID_RETURN_ON_DONE 1 +#define TEESMC_OPTEED_RETURN_ON_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_ON_DONE) + +/* + * Issued when returning from "cpu_off" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_OFF_DONE + * r1/x1 0 on success and anything else to indicate error condition + */ +#define TEESMC_OPTEED_FUNCID_RETURN_OFF_DONE 2 +#define TEESMC_OPTEED_RETURN_OFF_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_OFF_DONE) + +/* + * Issued when returning from "cpu_suspend" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_SUSPEND_DONE + * r1/x1 0 on success and anything else to indicate error condition + */ +#define TEESMC_OPTEED_FUNCID_RETURN_SUSPEND_DONE 3 +#define TEESMC_OPTEED_RETURN_SUSPEND_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_SUSPEND_DONE) + +/* + * Issued when returning from "cpu_resume" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_RESUME_DONE + * r1/x1 0 on success and anything else to indicate error condition + */ +#define TEESMC_OPTEED_FUNCID_RETURN_RESUME_DONE 4 +#define TEESMC_OPTEED_RETURN_RESUME_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_RESUME_DONE) + +/* + * Issued when returning from "std_smc" or "fast_smc" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_CALL_DONE + * r1-4/x1-4 Return value 0-3 which will passed to normal world in + * r0-3/x0-3 + */ +#define TEESMC_OPTEED_FUNCID_RETURN_CALL_DONE 5 +#define TEESMC_OPTEED_RETURN_CALL_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_CALL_DONE) + +/* + * Issued when returning from "fiq" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_FIQ_DONE + */ +#define TEESMC_OPTEED_FUNCID_RETURN_FIQ_DONE 6 +#define TEESMC_OPTEED_RETURN_FIQ_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_FIQ_DONE) + +/* + * Issued when returning from "system_off" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE + */ +#define TEESMC_OPTEED_FUNCID_RETURN_SYSTEM_OFF_DONE 7 +#define TEESMC_OPTEED_RETURN_SYSTEM_OFF_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_SYSTEM_OFF_DONE) + +/* + * Issued when returning from "system_reset" vector + * + * Register usage: + * r0/x0 SMC Function ID, TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE + */ +#define TEESMC_OPTEED_FUNCID_RETURN_SYSTEM_RESET_DONE 8 +#define TEESMC_OPTEED_RETURN_SYSTEM_RESET_DONE \ + TEESMC_OPTEED_RV(TEESMC_OPTEED_FUNCID_RETURN_SYSTEM_RESET_DONE) + +#endif /*TEESMC_OPTEED_H*/ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/teesmc_opteed_macros.h b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/teesmc_opteed_macros.h new file mode 100644 index 0000000..2453c9a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/opteed/teesmc_opteed_macros.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef __TEESMC_OPTEED_MACROS_H__ +#define __TEESMC_OPTEED_MACROS_H__ + +#include + +#define TEESMC_OPTEED_RV(func_num) \ + ((SMC_TYPE_FAST << FUNCID_TYPE_SHIFT) | \ + ((SMC_32) << FUNCID_CC_SHIFT) | \ + (62 << FUNCID_OEN_SHIFT) | \ + ((func_num) & FUNCID_NUM_MASK)) + +#endif /*__TEESMC_OPTEED_MACROS_H__*/ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd.mk new file mode 100644 index 0000000..b1159e7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd.mk @@ -0,0 +1,36 @@ +# +# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +SPD_INCLUDES := -Iinclude/bl32/payloads + +SPD_SOURCES := services/spd/tlkd/tlkd_common.c \ + services/spd/tlkd/tlkd_helpers.S \ + services/spd/tlkd/tlkd_main.c \ + services/spd/tlkd/tlkd_pm.c diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_common.c new file mode 100644 index 0000000..b19e27d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_common.c @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "tlkd_private.h" + +#define AT_MASK 3 + +/******************************************************************************* + * This function helps the SP to translate NS/S virtual addresses. + ******************************************************************************/ +uint64_t tlkd_va_translate(uintptr_t va, int type) +{ + uint64_t pa; + + if (type & TLK_TRANSLATE_NS_VADDR) { + + /* save secure context */ + cm_el1_sysregs_context_save(SECURE); + + /* restore non-secure context */ + cm_el1_sysregs_context_restore(NON_SECURE); + + /* switch NS bit to start using 64-bit, non-secure mappings */ + write_scr(cm_get_scr_el3(NON_SECURE)); + isb(); + } + + int at = type & AT_MASK; + switch (at) { + case 0: + ats12e1r(va); + break; + case 1: + ats12e1w(va); + break; + case 2: + ats12e0r(va); + break; + case 3: + ats12e0w(va); + break; + default: + assert(0); + } + + /* get the (NS/S) physical address */ + isb(); + pa = read_par_el1(); + + /* Restore secure state */ + if (type & TLK_TRANSLATE_NS_VADDR) { + + /* restore secure context */ + cm_el1_sysregs_context_restore(SECURE); + + /* switch NS bit to start using 32-bit, secure mappings */ + write_scr(cm_get_scr_el3(SECURE)); + isb(); + } + + return pa; +} + +/******************************************************************************* + * Given a secure payload entrypoint, register width, cpu id & pointer to a + * context data structure, this function will create a secure context ready for + * programming an entry into the secure payload. + ******************************************************************************/ +void tlkd_init_tlk_ep_state(struct entry_point_info *tlk_entry_point, + uint32_t rw, + uint64_t pc, + tlk_context_t *tlk_ctx) +{ + uint32_t ep_attr, spsr; + + /* Passing a NULL context is a critical programming error */ + assert(tlk_ctx); + assert(tlk_entry_point); + assert(pc); + + /* Associate this context with the cpu specified */ + tlk_ctx->mpidr = read_mpidr_el1(); + clr_std_smc_active_flag(tlk_ctx->state); + cm_set_context(&tlk_ctx->cpu_ctx, SECURE); + + if (rw == SP_AARCH64) + spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + else + spsr = SPSR_MODE32(MODE32_svc, + SPSR_T_ARM, + read_sctlr_el3() & SCTLR_EE_BIT, + DISABLE_ALL_EXCEPTIONS); + + /* initialise an entrypoint to set up the CPU context */ + ep_attr = SECURE | EP_ST_ENABLE; + if (read_sctlr_el3() & SCTLR_EE_BIT) + ep_attr |= EP_EE_BIG; + SET_PARAM_HEAD(tlk_entry_point, PARAM_EP, VERSION_1, ep_attr); + + tlk_entry_point->pc = pc; + tlk_entry_point->spsr = spsr; +} + +/******************************************************************************* + * This function takes a TLK context pointer and: + * 1. Applies the S-EL1 system register context from tlk_ctx->cpu_ctx. + * 2. Saves the current C runtime state (callee saved registers) on the stack + * frame and saves a reference to this state. + * 3. Calls el3_exit() so that the EL3 system and general purpose registers + * from the tlk_ctx->cpu_ctx are used to enter the secure payload image. + ******************************************************************************/ +uint64_t tlkd_synchronous_sp_entry(tlk_context_t *tlk_ctx) +{ + uint64_t rc; + + /* Passing a NULL context is a critical programming error */ + assert(tlk_ctx); + assert(tlk_ctx->c_rt_ctx == 0); + + /* Apply the Secure EL1 system register context and switch to it */ + assert(cm_get_context(SECURE) == &tlk_ctx->cpu_ctx); + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + + rc = tlkd_enter_sp(&tlk_ctx->c_rt_ctx); +#if DEBUG + tlk_ctx->c_rt_ctx = 0; +#endif + + return rc; +} + +/******************************************************************************* + * This function takes a TLK context pointer and: + * 1. Saves the S-EL1 system register context to tlk_ctx->cpu_ctx. + * 2. Restores the current C runtime state (callee saved registers) from the + * stack frame using reference to this state saved in tlkd_enter_sp(). + * 3. It does not need to save any general purpose or EL3 system register state + * as the generic smc entry routine should have saved those. + ******************************************************************************/ +void tlkd_synchronous_sp_exit(tlk_context_t *tlk_ctx, uint64_t ret) +{ + /* Passing a NULL context is a critical programming error */ + assert(tlk_ctx); + + /* Save the Secure EL1 system register context */ + assert(cm_get_context(SECURE) == &tlk_ctx->cpu_ctx); + cm_el1_sysregs_context_save(SECURE); + + assert(tlk_ctx->c_rt_ctx != 0); + tlkd_exit_sp(tlk_ctx->c_rt_ctx, ret); + + /* Should never reach here */ + assert(0); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_helpers.S new file mode 100644 index 0000000..e6fb9ea --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_helpers.S @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "tlkd_private.h" + + .global tlkd_enter_sp + .global tlkd_exit_sp + + /* --------------------------------------------- + * This function is called with SP_EL0 as stack. + * Here we stash our EL3 callee-saved registers + * on to the stack as a part of saving the C + * runtime and enter the secure payload. + * 'x0' contains a pointer to the memory where + * the address of the C runtime context is to be + * saved. + * --------------------------------------------- + */ +func tlkd_enter_sp + /* Make space for the registers that we're going to save */ + mov x3, sp + str x3, [x0, #0] + sub sp, sp, #TLKD_C_RT_CTX_SIZE + + /* Save callee-saved registers on to the stack */ + stp x19, x20, [sp, #TLKD_C_RT_CTX_X19] + stp x21, x22, [sp, #TLKD_C_RT_CTX_X21] + stp x23, x24, [sp, #TLKD_C_RT_CTX_X23] + stp x25, x26, [sp, #TLKD_C_RT_CTX_X25] + stp x27, x28, [sp, #TLKD_C_RT_CTX_X27] + stp x29, x30, [sp, #TLKD_C_RT_CTX_X29] + + /* ---------------------------------------------- + * Everything is setup now. el3_exit() will + * use the secure context to restore to the + * general purpose and EL3 system registers to + * ERET into the secure payload. + * ---------------------------------------------- + */ + b el3_exit +endfunc tlkd_enter_sp + + /* ---------------------------------------------- + * This function is called with 'x0' pointing to + * a C runtime context saved in tlkd_enter_sp(). + * It restores the saved registers and jumps to + * that runtime with 'x0' as the new sp. This + * destroys the C runtime context that had been + * built on the stack below the saved context by + * the caller. Later the second parameter 'x1' + * is passed as return value to the caller + * ---------------------------------------------- + */ +func tlkd_exit_sp + /* Restore the previous stack */ + mov sp, x0 + + /* Restore callee-saved registers on to the stack */ + ldp x19, x20, [x0, #(TLKD_C_RT_CTX_X19 - TLKD_C_RT_CTX_SIZE)] + ldp x21, x22, [x0, #(TLKD_C_RT_CTX_X21 - TLKD_C_RT_CTX_SIZE)] + ldp x23, x24, [x0, #(TLKD_C_RT_CTX_X23 - TLKD_C_RT_CTX_SIZE)] + ldp x25, x26, [x0, #(TLKD_C_RT_CTX_X25 - TLKD_C_RT_CTX_SIZE)] + ldp x27, x28, [x0, #(TLKD_C_RT_CTX_X27 - TLKD_C_RT_CTX_SIZE)] + ldp x29, x30, [x0, #(TLKD_C_RT_CTX_X29 - TLKD_C_RT_CTX_SIZE)] + + /* ------------------------------------------------ + * This should take us back to the instruction + * after the call to the last tlkd_enter_sp(). + * Place the second parameter to x0 so that the + * caller will see it as a return value from the + * original entry call + * ------------------------------------------------ + */ + mov x0, x1 + ret +endfunc tlkd_exit_sp diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_main.c new file mode 100644 index 0000000..0fddcb2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_main.c @@ -0,0 +1,458 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/******************************************************************************* + * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a + * plug-in component to the Secure Monitor, registered as a runtime service. The + * SPD is expected to be a functional extension of the Secure Payload (SP) that + * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting + * the Trusted OS/Applications range to the dispatcher. The SPD will either + * handle the request locally or delegate it to the Secure Payload. It is also + * responsible for initialising and maintaining communication with the SP. + ******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "tlkd_private.h" + +extern const spd_pm_ops_t tlkd_pm_ops; + +/******************************************************************************* + * Per-cpu Secure Payload state + ******************************************************************************/ +tlk_context_t tlk_ctx; + +/* TLK UID: RFC-4122 compliant UUID (version-5, sha-1) */ +DEFINE_SVC_UUID(tlk_uuid, + 0xbd11e9c9, 0x2bba, 0x52ee, 0xb1, 0x72, + 0x46, 0x1f, 0xba, 0x97, 0x7f, 0x63); + +int32_t tlkd_init(void); + +/******************************************************************************* + * Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type + * (aarch32/aarch64) if not already known and initialises the context for entry + * into the SP for its initialisation. + ******************************************************************************/ +int32_t tlkd_setup(void) +{ + entry_point_info_t *tlk_ep_info; + + /* + * Get information about the Secure Payload (BL32) image. Its + * absence is a critical failure. + */ + tlk_ep_info = bl31_plat_get_next_image_ep_info(SECURE); + if (!tlk_ep_info) { + WARN("No SP provided. Booting device without SP" + " initialization. SMC`s destined for SP" + " will return SMC_UNK\n"); + return 1; + } + + /* + * If there's no valid entry point for SP, we return a non-zero value + * signalling failure initializing the service. We bail out without + * registering any handlers + */ + if (!tlk_ep_info->pc) + return 1; + + /* + * Inspect the SP image's SPSR and determine it's execution state + * i.e whether AArch32 or AArch64. + */ + tlkd_init_tlk_ep_state(tlk_ep_info, + (tlk_ep_info->spsr >> MODE_RW_SHIFT) & MODE_RW_MASK, + tlk_ep_info->pc, + &tlk_ctx); + + /* + * All TLK SPD initialization done. Now register our init function + * with BL31 for deferred invocation + */ + bl31_register_bl32_init(&tlkd_init); + + return 0; +} + +/******************************************************************************* + * This function passes control to the Secure Payload image (BL32) for the first + * time on the primary cpu after a cold boot. It assumes that a valid secure + * context has already been created by tlkd_setup() which can be directly + * used. This function performs a synchronous entry into the Secure payload. + * The SP passes control back to this routine through a SMC. + ******************************************************************************/ +int32_t tlkd_init(void) +{ + entry_point_info_t *tlk_entry_point; + + /* + * Get information about the Secure Payload (BL32) image. Its + * absence is a critical failure. + */ + tlk_entry_point = bl31_plat_get_next_image_ep_info(SECURE); + assert(tlk_entry_point); + + cm_init_my_context(tlk_entry_point); + + /* + * Arrange for an entry into the test secure payload. + */ + return tlkd_synchronous_sp_entry(&tlk_ctx); +} + +/******************************************************************************* + * This function is responsible for handling all SMCs in the Trusted OS/App + * range from the non-secure state as defined in the SMC Calling Convention + * Document. It is also responsible for communicating with the Secure payload + * to delegate work and return results back to the non-secure state. Lastly it + * will also return any information that the secure payload needs to do the + * work assigned to it. + ******************************************************************************/ +uint64_t tlkd_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + cpu_context_t *ns_cpu_context; + gp_regs_t *gp_regs; + uint32_t ns; + uint64_t par; + + /* Passing a NULL context is a critical programming error */ + assert(handle); + + /* These SMCs are only supported by CPU0 */ + if ((read_mpidr() & MPIDR_CPU_MASK) != 0) + SMC_RET1(handle, SMC_UNK); + + /* Determine which security state this SMC originated from */ + ns = is_caller_non_secure(flags); + + switch (smc_fid) { + + /* + * This function ID is used by SP to indicate that it was + * preempted by a non-secure world IRQ. + */ + case TLK_PREEMPTED: + + if (ns) + SMC_RET1(handle, SMC_UNK); + + assert(handle == cm_get_context(SECURE)); + cm_el1_sysregs_context_save(SECURE); + + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* + * Restore non-secure state. There is no need to save the + * secure system register context since the SP was supposed + * to preserve it during S-EL1 interrupt handling. + */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + + SMC_RET1(ns_cpu_context, x1); + + /* + * This is a request from the non-secure context to: + * + * a. register shared memory with the SP for storing it's + * activity logs. + * b. register shared memory with the SP for passing args + * required for maintaining sessions with the Trusted + * Applications. + * c. open/close sessions + * d. issue commands to the Trusted Apps + * e. resume the preempted standard SMC call. + */ + case TLK_REGISTER_LOGBUF: + case TLK_REGISTER_REQBUF: + case TLK_OPEN_TA_SESSION: + case TLK_CLOSE_TA_SESSION: + case TLK_TA_LAUNCH_OP: + case TLK_TA_SEND_EVENT: + case TLK_RESUME_FID: + + if (!ns) + SMC_RET1(handle, SMC_UNK); + + /* + * This is a fresh request from the non-secure client. + * The parameters are in x1 and x2. Figure out which + * registers need to be preserved, save the non-secure + * state and send the request to the secure payload. + */ + assert(handle == cm_get_context(NON_SECURE)); + + /* + * Check if we are already processing a standard SMC + * call. Of all the supported fids, only the "resume" + * fid expects the flag to be set. + */ + if (smc_fid == TLK_RESUME_FID) { + if (!get_std_smc_active_flag(tlk_ctx.state)) + SMC_RET1(handle, SMC_UNK); + } else { + if (get_std_smc_active_flag(tlk_ctx.state)) + SMC_RET1(handle, SMC_UNK); + } + + cm_el1_sysregs_context_save(NON_SECURE); + + /* + * Verify if there is a valid context to use. + */ + assert(&tlk_ctx.cpu_ctx == cm_get_context(SECURE)); + + /* + * Mark the SP state as active. + */ + set_std_smc_active_flag(tlk_ctx.state); + + /* + * We are done stashing the non-secure context. Ask the + * secure payload to do the work now. + */ + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + + /* + * TLK is a 32-bit Trusted OS and so expects the SMC + * arguments via r0-r7. TLK expects the monitor frame + * registers to be 64-bits long. Hence, we pass x0 in + * r0-r1, x1 in r2-r3, x3 in r4-r5 and x4 in r6-r7. + * + * As smc_fid is a uint32 value, r1 contains 0. + */ + gp_regs = get_gpregs_ctx(&tlk_ctx.cpu_ctx); + write_ctx_reg(gp_regs, CTX_GPREG_X4, (uint32_t)x2); + write_ctx_reg(gp_regs, CTX_GPREG_X5, (uint32_t)(x2 >> 32)); + write_ctx_reg(gp_regs, CTX_GPREG_X6, (uint32_t)x3); + write_ctx_reg(gp_regs, CTX_GPREG_X7, (uint32_t)(x3 >> 32)); + SMC_RET4(&tlk_ctx.cpu_ctx, smc_fid, 0, (uint32_t)x1, + (uint32_t)(x1 >> 32)); + + /* + * Translate NS/EL1-S virtual addresses. + * + * x1 = virtual address + * x3 = type (NS/S) + * + * Returns PA:lo in r0, PA:hi in r1. + */ + case TLK_VA_TRANSLATE: + + /* Should be invoked only by secure world */ + if (ns) + SMC_RET1(handle, SMC_UNK); + + /* NS virtual addresses are 64-bit long */ + if (x3 & TLK_TRANSLATE_NS_VADDR) + x1 = (uint32_t)x1 | (x2 << 32); + + if (!x1) + SMC_RET1(handle, SMC_UNK); + + /* + * TODO: Sanity check x1. This would require platform + * support. + */ + + /* virtual address and type: ns/s */ + par = tlkd_va_translate(x1, x3); + + /* return physical address in r0-r1 */ + SMC_RET4(handle, (uint32_t)par, (uint32_t)(par >> 32), 0, 0); + + /* + * This is a request from the SP to mark completion of + * a standard function ID. + */ + case TLK_REQUEST_DONE: + if (ns) + SMC_RET1(handle, SMC_UNK); + + /* + * Mark the SP state as inactive. + */ + clr_std_smc_active_flag(tlk_ctx.state); + + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* + * This is a request completion SMC and we must switch to + * the non-secure world to pass the result. + */ + cm_el1_sysregs_context_save(SECURE); + + /* + * We are done stashing the secure context. Switch to the + * non-secure context and return the result. + */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + SMC_RET1(ns_cpu_context, x1); + + /* + * This function ID is used only by the SP to indicate it has + * finished initialising itself after a cold boot + */ + case TLK_ENTRY_DONE: + if (ns) + SMC_RET1(handle, SMC_UNK); + + /* + * SP has been successfully initialized. Register power + * managemnt hooks with PSCI + */ + psci_register_spd_pm_hook(&tlkd_pm_ops); + + /* + * TLK reports completion. The SPD must have initiated + * the original request through a synchronous entry + * into the SP. Jump back to the original C runtime + * context. + */ + tlkd_synchronous_sp_exit(&tlk_ctx, x1); + + /* + * These function IDs are used only by TLK to indicate it has + * finished: + * 1. suspending itself after an earlier psci cpu_suspend + * request. + * 2. resuming itself after an earlier psci cpu_suspend + * request. + * 3. powering down after an earlier psci system_off/system_reset + * request. + */ + case TLK_SUSPEND_DONE: + case TLK_RESUME_DONE: + case TLK_SYSTEM_OFF_DONE: + + if (ns) + SMC_RET1(handle, SMC_UNK); + + /* + * TLK reports completion. TLKD must have initiated the + * original request through a synchronous entry into the SP. + * Jump back to the original C runtime context, and pass x1 as + * return value to the caller + */ + tlkd_synchronous_sp_exit(&tlk_ctx, x1); + + /* + * Return the number of service function IDs implemented to + * provide service to non-secure + */ + case TOS_CALL_COUNT: + SMC_RET1(handle, TLK_NUM_FID); + + /* + * Return TLK's UID to the caller + */ + case TOS_UID: + SMC_UUID_RET(handle, tlk_uuid); + + /* + * Return the version of current implementation + */ + case TOS_CALL_VERSION: + SMC_RET2(handle, TLK_VERSION_MAJOR, TLK_VERSION_MINOR); + + default: + break; + } + + SMC_RET1(handle, SMC_UNK); +} + +/* Define a SPD runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + tlkd_tos_fast, + + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_FAST, + tlkd_setup, + tlkd_smc_handler +); + +/* Define a SPD runtime service descriptor for standard SMC calls */ +DECLARE_RT_SVC( + tlkd_tos_std, + + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_STD, + NULL, + tlkd_smc_handler +); + +/* Define a SPD runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + tlkd_tap_fast, + + OEN_TAP_START, + OEN_TAP_END, + SMC_TYPE_FAST, + NULL, + tlkd_smc_handler +); + +/* Define a SPD runtime service descriptor for standard SMC calls */ +DECLARE_RT_SVC( + tlkd_tap_std, + + OEN_TAP_START, + OEN_TAP_END, + SMC_TYPE_STD, + NULL, + tlkd_smc_handler +); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_pm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_pm.c new file mode 100644 index 0000000..1eff0aa --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_pm.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "tlkd_private.h" + +extern tlk_context_t tlk_ctx; + +#define MPIDR_CPU0 0x80000000 + +/******************************************************************************* + * Return the type of payload TLKD is dealing with. Report the current + * resident cpu (mpidr format) if it is a UP/UP migratable payload. + ******************************************************************************/ +static int32_t cpu_migrate_info(uint64_t *resident_cpu) +{ + /* the payload runs only on CPU0 */ + *resident_cpu = MPIDR_CPU0; + + /* Uniprocessor, not migrate capable payload */ + return PSCI_TOS_NOT_UP_MIG_CAP; +} + +/******************************************************************************* + * This cpu is being suspended. Inform TLK of the SYSTEM_SUSPEND event, so + * that it can pass this information to its Trusted Apps. + ******************************************************************************/ +static void cpu_suspend_handler(uint64_t suspend_level) +{ + gp_regs_t *gp_regs; + int cpu = read_mpidr() & MPIDR_CPU_MASK; + int32_t rc = 0; + + /* + * TLK runs only on CPU0 and suspends its Trusted Apps during + * SYSTEM_SUSPEND. It has no role to play during CPU_SUSPEND. + */ + if ((cpu != 0) || (suspend_level != PLAT_MAX_PWR_LVL)) + return; + + /* pass system suspend event to TLK */ + gp_regs = get_gpregs_ctx(&tlk_ctx.cpu_ctx); + write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_SUSPEND); + + /* Program the entry point and enter TLK */ + rc = tlkd_synchronous_sp_entry(&tlk_ctx); + + /* + * Read the response from TLK. A non-zero return means that + * something went wrong while communicating with it. + */ + if (rc != 0) + panic(); +} + +/******************************************************************************* + * This cpu is being resumed. Inform TLK of the SYSTEM_SUSPEND exit, so + * that it can pass this information to its Trusted Apps. + ******************************************************************************/ +static void cpu_resume_handler(uint64_t suspend_level) +{ + gp_regs_t *gp_regs; + int cpu = read_mpidr() & MPIDR_CPU_MASK; + int32_t rc = 0; + + /* + * TLK runs only on CPU0 and resumes its Trusted Apps during + * SYSTEM_SUSPEND exit. It has no role to play during CPU_SUSPEND + * exit. + */ + if ((cpu != 0) || (suspend_level != PLAT_MAX_PWR_LVL)) + return; + + /* pass system resume event to TLK */ + gp_regs = get_gpregs_ctx(&tlk_ctx.cpu_ctx); + write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_RESUME); + + /* Program the entry point and enter TLK */ + rc = tlkd_synchronous_sp_entry(&tlk_ctx); + + /* + * Read the response from TLK. A non-zero return means that + * something went wrong while communicating with it. + */ + if (rc != 0) + panic(); +} + +/******************************************************************************* + * System is about to be reset. Inform the SP to allow any book-keeping + ******************************************************************************/ +static void system_off_handler(void) +{ + int cpu = read_mpidr() & MPIDR_CPU_MASK; + gp_regs_t *gp_regs; + + /* TLK runs only on CPU0 */ + if (cpu != 0) + return; + + /* pass system off/reset events to TLK */ + gp_regs = get_gpregs_ctx(&tlk_ctx.cpu_ctx); + write_ctx_reg(gp_regs, CTX_GPREG_X0, TLK_SYSTEM_OFF); + + /* + * Enter the SP. We do not care about the return value because we + * must continue with the shutdown anyway. + */ + (void)tlkd_synchronous_sp_entry(&tlk_ctx); +} + +/******************************************************************************* + * Structure populated by the Dispatcher to be given a chance to perform any + * bookkeeping before PSCI executes a power mgmt. operation. + ******************************************************************************/ +const spd_pm_ops_t tlkd_pm_ops = { + .svc_migrate_info = cpu_migrate_info, + .svc_suspend = cpu_suspend_handler, + .svc_suspend_finish = cpu_resume_handler, + .svc_system_off = system_off_handler, + .svc_system_reset = system_off_handler +}; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_private.h new file mode 100644 index 0000000..271c24c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tlkd/tlkd_private.h @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TLKD_PRIVATE_H__ +#define __TLKD_PRIVATE_H__ + +#include +#include +#include +#include +#include + +/* + * This flag is used by the TLKD to determine if the SP is servicing a standard + * SMC request prior to programming the next entry into the SP e.g. if SP + * execution is preempted by a non-secure interrupt and handed control to the + * normal world. If another request which is distinct from what the SP was + * previously doing arrives, then this flag will be help the TLKD to either + * reject the new request or service it while ensuring that the previous context + * is not corrupted. + */ +#define STD_SMC_ACTIVE_FLAG_SHIFT 2 +#define STD_SMC_ACTIVE_FLAG_MASK 1 +#define get_std_smc_active_flag(state) (((state) >> STD_SMC_ACTIVE_FLAG_SHIFT) \ + & STD_SMC_ACTIVE_FLAG_MASK) +#define set_std_smc_active_flag(state) ((state) |= \ + (1 << STD_SMC_ACTIVE_FLAG_SHIFT)) +#define clr_std_smc_active_flag(state) ((state) &= \ + ~(STD_SMC_ACTIVE_FLAG_MASK \ + << STD_SMC_ACTIVE_FLAG_SHIFT)) + +/******************************************************************************* + * Translate virtual address received from the NS world + ******************************************************************************/ +#define TLK_TRANSLATE_NS_VADDR 4 + +/******************************************************************************* + * Secure Payload execution state information i.e. aarch32 or aarch64 + ******************************************************************************/ +#define SP_AARCH32 MODE_RW_32 +#define SP_AARCH64 MODE_RW_64 + +/******************************************************************************* + * Number of cpus that the present on this platform. TODO: Rely on a topology + * tree to determine this in the future to avoid assumptions about mpidr + * allocation + ******************************************************************************/ +#define TLKD_CORE_COUNT PLATFORM_CORE_COUNT + +/******************************************************************************* + * Constants that allow assembler code to preserve callee-saved registers of the + * C runtime context while performing a security state switch. + ******************************************************************************/ +#define TLKD_C_RT_CTX_X19 0x0 +#define TLKD_C_RT_CTX_X20 0x8 +#define TLKD_C_RT_CTX_X21 0x10 +#define TLKD_C_RT_CTX_X22 0x18 +#define TLKD_C_RT_CTX_X23 0x20 +#define TLKD_C_RT_CTX_X24 0x28 +#define TLKD_C_RT_CTX_X25 0x30 +#define TLKD_C_RT_CTX_X26 0x38 +#define TLKD_C_RT_CTX_X27 0x40 +#define TLKD_C_RT_CTX_X28 0x48 +#define TLKD_C_RT_CTX_X29 0x50 +#define TLKD_C_RT_CTX_X30 0x58 +#define TLKD_C_RT_CTX_SIZE 0x60 +#define TLKD_C_RT_CTX_ENTRIES (TLKD_C_RT_CTX_SIZE >> DWORD_SHIFT) + +#ifndef __ASSEMBLY__ + +#include +#include + +/* AArch64 callee saved general purpose register context structure. */ +DEFINE_REG_STRUCT(c_rt_regs, TLKD_C_RT_CTX_ENTRIES); + +/* + * Compile time assertion to ensure that both the compiler and linker + * have the same double word aligned view of the size of the C runtime + * register context. + */ +CASSERT(TLKD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ + assert_tlkd_c_rt_regs_size_mismatch); + +/******************************************************************************* + * Structure which helps the SPD to maintain the per-cpu state of the SP. + * 'state' - collection of flags to track SP state e.g. on/off + * 'mpidr' - mpidr to associate a context with a cpu + * 'c_rt_ctx' - stack address to restore C runtime context from after + * returning from a synchronous entry into the SP. + * 'cpu_ctx' - space to maintain SP architectural state + * 'saved_tsp_args' - space to store arguments for TSP arithmetic operations + * which will queried using the TSP_GET_ARGS SMC by TSP. + ******************************************************************************/ +typedef struct tlk_context { + uint32_t state; + uint64_t mpidr; + uint64_t c_rt_ctx; + cpu_context_t cpu_ctx; +} tlk_context_t; + +/******************************************************************************* + * Function & Data prototypes + ******************************************************************************/ +uint64_t tlkd_va_translate(uintptr_t va, int type); +uint64_t tlkd_enter_sp(uint64_t *c_rt_ctx); +void __dead2 tlkd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); +uint64_t tlkd_synchronous_sp_entry(tlk_context_t *tlk_ctx); +void __dead2 tlkd_synchronous_sp_exit(tlk_context_t *tlk_ctx, + uint64_t ret); +void tlkd_init_tlk_ep_state(struct entry_point_info *tlk_entry_point, + uint32_t rw, + uint64_t pc, + tlk_context_t *tlk_ctx); + +#endif /*__ASSEMBLY__*/ + +#endif /* __TLKD_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd.mk b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd.mk new file mode 100644 index 0000000..ede2504 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd.mk @@ -0,0 +1,71 @@ +# +# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +TSPD_DIR := services/spd/tspd +SPD_INCLUDES := -Iinclude/bl32/tsp + +SPD_SOURCES := services/spd/tspd/tspd_common.c \ + services/spd/tspd/tspd_helpers.S \ + services/spd/tspd/tspd_main.c \ + services/spd/tspd/tspd_pm.c + +# This dispatcher is paired with a Test Secure Payload source and we intend to +# build the Test Secure Payload along with this dispatcher. +# +# In cases where an associated Secure Payload lies outside this build +# system/source tree, the the dispatcher Makefile can either invoke an external +# build command or assume it pre-built + +BL32_ROOT := bl32/tsp + +# Include SP's Makefile. The assumption is that the TSP's build system is +# compatible with that of Trusted Firmware, and it'll add and populate necessary +# build targets and variables +include ${BL32_ROOT}/tsp.mk + +# Let the top-level Makefile know that we intend to build the SP from source +NEED_BL32 := yes + +# Flag used to enable routing of non-secure interrupts to EL3 when they are +# generated while the code is executing in S-EL1/0. +TSP_NS_INTR_ASYNC_PREEMPT := 0 + +# If TSPD_ROUTE_IRQ_TO_EL3 build flag is defined, use it to define value for +# TSP_NS_INTR_ASYNC_PREEMPT for backward compatibility. +ifdef TSPD_ROUTE_IRQ_TO_EL3 +ifeq (${ERROR_DEPRECATED},1) +$(error "TSPD_ROUTE_IRQ_TO_EL3 is deprecated. Please use the new build flag TSP_NS_INTR_ASYNC_PREEMPT") +endif +$(warning "TSPD_ROUTE_IRQ_TO_EL3 is deprecated. Please use the new build flag TSP_NS_INTR_ASYNC_PREEMPT") +TSP_NS_INTR_ASYNC_PREEMPT := ${TSPD_ROUTE_IRQ_TO_EL3} +endif + +$(eval $(call assert_boolean,TSP_NS_INTR_ASYNC_PREEMPT)) +$(eval $(call add_define,TSP_NS_INTR_ASYNC_PREEMPT)) diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_common.c b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_common.c new file mode 100644 index 0000000..322413c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_common.c @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "tspd_private.h" + +/******************************************************************************* + * Given a secure payload entrypoint info pointer, entry point PC, register + * width, cpu id & pointer to a context data structure, this function will + * initialize tsp context and entry point info for the secure payload + ******************************************************************************/ +void tspd_init_tsp_ep_state(struct entry_point_info *tsp_entry_point, + uint32_t rw, + uint64_t pc, + tsp_context_t *tsp_ctx) +{ + uint32_t ep_attr; + + /* Passing a NULL context is a critical programming error */ + assert(tsp_ctx); + assert(tsp_entry_point); + assert(pc); + + /* + * We support AArch64 TSP for now. + * TODO: Add support for AArch32 TSP + */ + assert(rw == TSP_AARCH64); + + /* Associate this context with the cpu specified */ + tsp_ctx->mpidr = read_mpidr_el1(); + tsp_ctx->state = 0; + set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); + clr_std_smc_active_flag(tsp_ctx->state); + + cm_set_context(&tsp_ctx->cpu_ctx, SECURE); + + /* initialise an entrypoint to set up the CPU context */ + ep_attr = SECURE | EP_ST_ENABLE; + if (read_sctlr_el3() & SCTLR_EE_BIT) + ep_attr |= EP_EE_BIG; + SET_PARAM_HEAD(tsp_entry_point, PARAM_EP, VERSION_1, ep_attr); + + tsp_entry_point->pc = pc; + tsp_entry_point->spsr = SPSR_64(MODE_EL1, + MODE_SP_ELX, + DISABLE_ALL_EXCEPTIONS); + memset(&tsp_entry_point->args, 0, sizeof(tsp_entry_point->args)); +} + +/******************************************************************************* + * This function takes an SP context pointer and: + * 1. Applies the S-EL1 system register context from tsp_ctx->cpu_ctx. + * 2. Saves the current C runtime state (callee saved registers) on the stack + * frame and saves a reference to this state. + * 3. Calls el3_exit() so that the EL3 system and general purpose registers + * from the tsp_ctx->cpu_ctx are used to enter the secure payload image. + ******************************************************************************/ +uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx) +{ + uint64_t rc; + + assert(tsp_ctx != NULL); + assert(tsp_ctx->c_rt_ctx == 0); + + /* Apply the Secure EL1 system register context and switch to it */ + assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + + rc = tspd_enter_sp(&tsp_ctx->c_rt_ctx); +#if DEBUG + tsp_ctx->c_rt_ctx = 0; +#endif + + return rc; +} + + +/******************************************************************************* + * This function takes an SP context pointer and: + * 1. Saves the S-EL1 system register context tp tsp_ctx->cpu_ctx. + * 2. Restores the current C runtime state (callee saved registers) from the + * stack frame using the reference to this state saved in tspd_enter_sp(). + * 3. It does not need to save any general purpose or EL3 system register state + * as the generic smc entry routine should have saved those. + ******************************************************************************/ +void tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret) +{ + assert(tsp_ctx != NULL); + /* Save the Secure EL1 system register context */ + assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); + cm_el1_sysregs_context_save(SECURE); + + assert(tsp_ctx->c_rt_ctx != 0); + tspd_exit_sp(tsp_ctx->c_rt_ctx, ret); + + /* Should never reach here */ + assert(0); +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_helpers.S b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_helpers.S new file mode 100644 index 0000000..515e824 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_helpers.S @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "tspd_private.h" + + .global tspd_enter_sp + /* --------------------------------------------- + * This function is called with SP_EL0 as stack. + * Here we stash our EL3 callee-saved registers + * on to the stack as a part of saving the C + * runtime and enter the secure payload. + * 'x0' contains a pointer to the memory where + * the address of the C runtime context is to be + * saved. + * --------------------------------------------- + */ +func tspd_enter_sp + /* Make space for the registers that we're going to save */ + mov x3, sp + str x3, [x0, #0] + sub sp, sp, #TSPD_C_RT_CTX_SIZE + + /* Save callee-saved registers on to the stack */ + stp x19, x20, [sp, #TSPD_C_RT_CTX_X19] + stp x21, x22, [sp, #TSPD_C_RT_CTX_X21] + stp x23, x24, [sp, #TSPD_C_RT_CTX_X23] + stp x25, x26, [sp, #TSPD_C_RT_CTX_X25] + stp x27, x28, [sp, #TSPD_C_RT_CTX_X27] + stp x29, x30, [sp, #TSPD_C_RT_CTX_X29] + + /* --------------------------------------------- + * Everything is setup now. el3_exit() will + * use the secure context to restore to the + * general purpose and EL3 system registers to + * ERET into the secure payload. + * --------------------------------------------- + */ + b el3_exit +endfunc tspd_enter_sp + + /* --------------------------------------------- + * This function is called 'x0' pointing to a C + * runtime context saved in tspd_enter_sp(). It + * restores the saved registers and jumps to + * that runtime with 'x0' as the new sp. This + * destroys the C runtime context that had been + * built on the stack below the saved context by + * the caller. Later the second parameter 'x1' + * is passed as return value to the caller + * --------------------------------------------- + */ + .global tspd_exit_sp +func tspd_exit_sp + /* Restore the previous stack */ + mov sp, x0 + + /* Restore callee-saved registers on to the stack */ + ldp x19, x20, [x0, #(TSPD_C_RT_CTX_X19 - TSPD_C_RT_CTX_SIZE)] + ldp x21, x22, [x0, #(TSPD_C_RT_CTX_X21 - TSPD_C_RT_CTX_SIZE)] + ldp x23, x24, [x0, #(TSPD_C_RT_CTX_X23 - TSPD_C_RT_CTX_SIZE)] + ldp x25, x26, [x0, #(TSPD_C_RT_CTX_X25 - TSPD_C_RT_CTX_SIZE)] + ldp x27, x28, [x0, #(TSPD_C_RT_CTX_X27 - TSPD_C_RT_CTX_SIZE)] + ldp x29, x30, [x0, #(TSPD_C_RT_CTX_X29 - TSPD_C_RT_CTX_SIZE)] + + /* --------------------------------------------- + * This should take us back to the instruction + * after the call to the last tspd_enter_sp(). + * Place the second parameter to x0 so that the + * caller will see it as a return value from the + * original entry call + * --------------------------------------------- + */ + mov x0, x1 + ret +endfunc tspd_exit_sp diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_main.c new file mode 100644 index 0000000..1a06459 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_main.c @@ -0,0 +1,700 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +/******************************************************************************* + * This is the Secure Payload Dispatcher (SPD). The dispatcher is meant to be a + * plug-in component to the Secure Monitor, registered as a runtime service. The + * SPD is expected to be a functional extension of the Secure Payload (SP) that + * executes in Secure EL1. The Secure Monitor will delegate all SMCs targeting + * the Trusted OS/Applications range to the dispatcher. The SPD will either + * handle the request locally or delegate it to the Secure Payload. It is also + * responsible for initialising and maintaining communication with the SP. + ******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "tspd_private.h" + +/******************************************************************************* + * Address of the entrypoint vector table in the Secure Payload. It is + * initialised once on the primary core after a cold boot. + ******************************************************************************/ +tsp_vectors_t *tsp_vectors; + +/******************************************************************************* + * Array to keep track of per-cpu Secure Payload state + ******************************************************************************/ +tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; + + +/* TSP UID */ +DEFINE_SVC_UUID(tsp_uuid, + 0x5b3056a0, 0x3291, 0x427b, 0x98, 0x11, + 0x71, 0x68, 0xca, 0x50, 0xf3, 0xfa); + +int32_t tspd_init(void); + +/* + * This helper function handles Secure EL1 preemption. The preemption could be + * due Non Secure interrupts or EL3 interrupts. In both the cases we context + * switch to the normal world and in case of EL3 interrupts, it will again be + * routed to EL3 which will get handled at the exception vectors. + */ +uint64_t tspd_handle_sp_preemption(void *handle) +{ + cpu_context_t *ns_cpu_context; + + assert(handle == cm_get_context(SECURE)); + cm_el1_sysregs_context_save(SECURE); + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* + * To allow Secure EL1 interrupt handler to re-enter TSP while TSP + * is preempted, the secure system register context which will get + * overwritten must be additionally saved. This is currently done + * by the TSPD S-EL1 interrupt handler. + */ + + /* + * Restore non-secure state. + */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + + /* + * The TSP was preempted during STD SMC execution. + * Return back to the normal world with SMC_PREEMPTED as error + * code in x0. + */ + SMC_RET1(ns_cpu_context, SMC_PREEMPTED); +} + +/******************************************************************************* + * This function is the handler registered for S-EL1 interrupts by the TSPD. It + * validates the interrupt and upon success arranges entry into the TSP at + * 'tsp_sel1_intr_entry()' for handling the interrupt. + ******************************************************************************/ +static uint64_t tspd_sel1_interrupt_handler(uint32_t id, + uint32_t flags, + void *handle, + void *cookie) +{ + uint32_t linear_id; + tsp_context_t *tsp_ctx; + + /* Check the security state when the exception was generated */ + assert(get_interrupt_src_ss(flags) == NON_SECURE); + + /* Sanity check the pointer to this cpu's context */ + assert(handle == cm_get_context(NON_SECURE)); + + /* Save the non-secure context before entering the TSP */ + cm_el1_sysregs_context_save(NON_SECURE); + + /* Get a reference to this cpu's TSP context */ + linear_id = plat_my_core_pos(); + tsp_ctx = &tspd_sp_context[linear_id]; + assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); + + /* + * Determine if the TSP was previously preempted. Its last known + * context has to be preserved in this case. + * The TSP should return control to the TSPD after handling this + * S-EL1 interrupt. Preserve essential EL3 context to allow entry into + * the TSP at the S-EL1 interrupt entry point using the 'cpu_context' + * structure. There is no need to save the secure system register + * context since the TSP is supposed to preserve it during S-EL1 + * interrupt handling. + */ + if (get_std_smc_active_flag(tsp_ctx->state)) { + tsp_ctx->saved_spsr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, + CTX_SPSR_EL3); + tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx, + CTX_ELR_EL3); +#if TSP_NS_INTR_ASYNC_PREEMPT + /*Need to save the previously interrupted secure context */ + memcpy(&tsp_ctx->sp_ctx, &tsp_ctx->cpu_ctx, TSPD_SP_CTX_SIZE); +#endif + } + + cm_el1_sysregs_context_restore(SECURE); + cm_set_elr_spsr_el3(SECURE, (uint64_t) &tsp_vectors->sel1_intr_entry, + SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)); + + cm_set_next_eret_context(SECURE); + + /* + * Tell the TSP that it has to handle a S-EL1 interrupt synchronously. + * Also the instruction in normal world where the interrupt was + * generated is passed for debugging purposes. It is safe to retrieve + * this address from ELR_EL3 as the secure context will not take effect + * until el3_exit(). + */ + SMC_RET2(&tsp_ctx->cpu_ctx, TSP_HANDLE_SEL1_INTR_AND_RETURN, read_elr_el3()); +} + +#if TSP_NS_INTR_ASYNC_PREEMPT +/******************************************************************************* + * This function is the handler registered for Non secure interrupts by the + * TSPD. It validates the interrupt and upon success arranges entry into the + * normal world for handling the interrupt. + ******************************************************************************/ +static uint64_t tspd_ns_interrupt_handler(uint32_t id, + uint32_t flags, + void *handle, + void *cookie) +{ + /* Check the security state when the exception was generated */ + assert(get_interrupt_src_ss(flags) == SECURE); + + /* + * Disable the routing of NS interrupts from secure world to EL3 while + * interrupted on this core. + */ + disable_intr_rm_local(INTR_TYPE_NS, SECURE); + + return tspd_handle_sp_preemption(handle); +} +#endif + +/******************************************************************************* + * Secure Payload Dispatcher setup. The SPD finds out the SP entrypoint and type + * (aarch32/aarch64) if not already known and initialises the context for entry + * into the SP for its initialisation. + ******************************************************************************/ +int32_t tspd_setup(void) +{ + entry_point_info_t *tsp_ep_info; + uint32_t linear_id; + + linear_id = plat_my_core_pos(); + + /* + * Get information about the Secure Payload (BL32) image. Its + * absence is a critical failure. TODO: Add support to + * conditionally include the SPD service + */ + tsp_ep_info = bl31_plat_get_next_image_ep_info(SECURE); + if (!tsp_ep_info) { + WARN("No TSP provided by BL2 boot loader, Booting device" + " without TSP initialization. SMC`s destined for TSP" + " will return SMC_UNK\n"); + return 1; + } + + /* + * If there's no valid entry point for SP, we return a non-zero value + * signalling failure initializing the service. We bail out without + * registering any handlers + */ + if (!tsp_ep_info->pc) + return 1; + + /* + * We could inspect the SP image and determine its execution + * state i.e whether AArch32 or AArch64. Assuming it's AArch64 + * for the time being. + */ + tspd_init_tsp_ep_state(tsp_ep_info, + TSP_AARCH64, + tsp_ep_info->pc, + &tspd_sp_context[linear_id]); + +#if TSP_INIT_ASYNC + bl31_set_next_image_type(SECURE); +#else + /* + * All TSPD initialization done. Now register our init function with + * BL31 for deferred invocation + */ + bl31_register_bl32_init(&tspd_init); +#endif + return 0; +} + +/******************************************************************************* + * This function passes control to the Secure Payload image (BL32) for the first + * time on the primary cpu after a cold boot. It assumes that a valid secure + * context has already been created by tspd_setup() which can be directly used. + * It also assumes that a valid non-secure context has been initialised by PSCI + * so it does not need to save and restore any non-secure state. This function + * performs a synchronous entry into the Secure payload. The SP passes control + * back to this routine through a SMC. + ******************************************************************************/ +int32_t tspd_init(void) +{ + uint32_t linear_id = plat_my_core_pos(); + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + entry_point_info_t *tsp_entry_point; + uint64_t rc; + + /* + * Get information about the Secure Payload (BL32) image. Its + * absence is a critical failure. + */ + tsp_entry_point = bl31_plat_get_next_image_ep_info(SECURE); + assert(tsp_entry_point); + + cm_init_my_context(tsp_entry_point); + + /* + * Arrange for an entry into the test secure payload. It will be + * returned via TSP_ENTRY_DONE case + */ + rc = tspd_synchronous_sp_entry(tsp_ctx); + assert(rc != 0); + + return rc; +} + + +/******************************************************************************* + * This function is responsible for handling all SMCs in the Trusted OS/App + * range from the non-secure state as defined in the SMC Calling Convention + * Document. It is also responsible for communicating with the Secure payload + * to delegate work and return results back to the non-secure state. Lastly it + * will also return any information that the secure payload needs to do the + * work assigned to it. + ******************************************************************************/ +uint64_t tspd_smc_handler(uint32_t smc_fid, + uint64_t x1, + uint64_t x2, + uint64_t x3, + uint64_t x4, + void *cookie, + void *handle, + uint64_t flags) +{ + cpu_context_t *ns_cpu_context; + uint32_t linear_id = plat_my_core_pos(), ns; + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + uint64_t rc; +#if TSP_INIT_ASYNC + entry_point_info_t *next_image_info; +#endif + + /* Determine which security state this SMC originated from */ + ns = is_caller_non_secure(flags); + + switch (smc_fid) { + + /* + * This function ID is used by TSP to indicate that it was + * preempted by a normal world IRQ. + * + */ + case TSP_PREEMPTED: + if (ns) + SMC_RET1(handle, SMC_UNK); + + return tspd_handle_sp_preemption(handle); + + /* + * This function ID is used only by the TSP to indicate that it has + * finished handling a S-EL1 interrupt or was preempted by a higher + * priority pending EL3 interrupt. Execution should resume + * in the normal world. + */ + case TSP_HANDLED_S_EL1_INTR: + if (ns) + SMC_RET1(handle, SMC_UNK); + + assert(handle == cm_get_context(SECURE)); + + /* + * Restore the relevant EL3 state which saved to service + * this SMC. + */ + if (get_std_smc_active_flag(tsp_ctx->state)) { + SMC_SET_EL3(&tsp_ctx->cpu_ctx, + CTX_SPSR_EL3, + tsp_ctx->saved_spsr_el3); + SMC_SET_EL3(&tsp_ctx->cpu_ctx, + CTX_ELR_EL3, + tsp_ctx->saved_elr_el3); +#if TSP_NS_INTR_ASYNC_PREEMPT + /* + * Need to restore the previously interrupted + * secure context. + */ + memcpy(&tsp_ctx->cpu_ctx, &tsp_ctx->sp_ctx, + TSPD_SP_CTX_SIZE); +#endif + } + + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* + * Restore non-secure state. There is no need to save the + * secure system register context since the TSP was supposed + * to preserve it during S-EL1 interrupt handling. + */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + + SMC_RET0((uint64_t) ns_cpu_context); + + /* + * This function ID is used only by the SP to indicate it has + * finished initialising itself after a cold boot + */ + case TSP_ENTRY_DONE: + if (ns) + SMC_RET1(handle, SMC_UNK); + + /* + * Stash the SP entry points information. This is done + * only once on the primary cpu + */ + assert(tsp_vectors == NULL); + tsp_vectors = (tsp_vectors_t *) x1; + + if (tsp_vectors) { + set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); + + /* + * TSP has been successfully initialized. Register power + * managemnt hooks with PSCI + */ + psci_register_spd_pm_hook(&tspd_pm); + + /* + * Register an interrupt handler for S-EL1 interrupts + * when generated during code executing in the + * non-secure state. + */ + flags = 0; + set_interrupt_rm_flag(flags, NON_SECURE); + rc = register_interrupt_type_handler(INTR_TYPE_S_EL1, + tspd_sel1_interrupt_handler, + flags); + if (rc) + panic(); + +#if TSP_NS_INTR_ASYNC_PREEMPT + /* + * Register an interrupt handler for NS interrupts when + * generated during code executing in secure state are + * routed to EL3. + */ + flags = 0; + set_interrupt_rm_flag(flags, SECURE); + + rc = register_interrupt_type_handler(INTR_TYPE_NS, + tspd_ns_interrupt_handler, + flags); + if (rc) + panic(); + + /* + * Disable the NS interrupt locally. + */ + disable_intr_rm_local(INTR_TYPE_NS, SECURE); +#endif + } + + +#if TSP_INIT_ASYNC + /* Save the Secure EL1 system register context */ + assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx); + cm_el1_sysregs_context_save(SECURE); + + /* Program EL3 registers to enable entry into the next EL */ + next_image_info = bl31_plat_get_next_image_ep_info(NON_SECURE); + assert(next_image_info); + assert(NON_SECURE == + GET_SECURITY_STATE(next_image_info->h.attr)); + + cm_init_my_context(next_image_info); + cm_prepare_el3_exit(NON_SECURE); + SMC_RET0(cm_get_context(NON_SECURE)); +#else + /* + * SP reports completion. The SPD must have initiated + * the original request through a synchronous entry + * into the SP. Jump back to the original C runtime + * context. + */ + tspd_synchronous_sp_exit(tsp_ctx, x1); +#endif + + /* + * These function IDs are used only by the SP to indicate it has + * finished: + * 1. turning itself on in response to an earlier psci + * cpu_on request + * 2. resuming itself after an earlier psci cpu_suspend + * request. + */ + case TSP_ON_DONE: + case TSP_RESUME_DONE: + + /* + * These function IDs are used only by the SP to indicate it has + * finished: + * 1. suspending itself after an earlier psci cpu_suspend + * request. + * 2. turning itself off in response to an earlier psci + * cpu_off request. + */ + case TSP_OFF_DONE: + case TSP_SUSPEND_DONE: + case TSP_SYSTEM_OFF_DONE: + case TSP_SYSTEM_RESET_DONE: + if (ns) + SMC_RET1(handle, SMC_UNK); + + /* + * SP reports completion. The SPD must have initiated the + * original request through a synchronous entry into the SP. + * Jump back to the original C runtime context, and pass x1 as + * return value to the caller + */ + tspd_synchronous_sp_exit(tsp_ctx, x1); + + /* + * Request from non-secure client to perform an + * arithmetic operation or response from secure + * payload to an earlier request. + */ + case TSP_FAST_FID(TSP_ADD): + case TSP_FAST_FID(TSP_SUB): + case TSP_FAST_FID(TSP_MUL): + case TSP_FAST_FID(TSP_DIV): + + case TSP_STD_FID(TSP_ADD): + case TSP_STD_FID(TSP_SUB): + case TSP_STD_FID(TSP_MUL): + case TSP_STD_FID(TSP_DIV): + if (ns) { + /* + * This is a fresh request from the non-secure client. + * The parameters are in x1 and x2. Figure out which + * registers need to be preserved, save the non-secure + * state and send the request to the secure payload. + */ + assert(handle == cm_get_context(NON_SECURE)); + + /* Check if we are already preempted */ + if (get_std_smc_active_flag(tsp_ctx->state)) + SMC_RET1(handle, SMC_UNK); + + cm_el1_sysregs_context_save(NON_SECURE); + + /* Save x1 and x2 for use by TSP_GET_ARGS call below */ + store_tsp_args(tsp_ctx, x1, x2); + + /* + * We are done stashing the non-secure context. Ask the + * secure payload to do the work now. + */ + + /* + * Verify if there is a valid context to use, copy the + * operation type and parameters to the secure context + * and jump to the fast smc entry point in the secure + * payload. Entry into S-EL1 will take place upon exit + * from this function. + */ + assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE)); + + /* Set appropriate entry for SMC. + * We expect the TSP to manage the PSTATE.I and PSTATE.F + * flags as appropriate. + */ + if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) { + cm_set_elr_el3(SECURE, (uint64_t) + &tsp_vectors->fast_smc_entry); + } else { + set_std_smc_active_flag(tsp_ctx->state); + cm_set_elr_el3(SECURE, (uint64_t) + &tsp_vectors->std_smc_entry); +#if TSP_NS_INTR_ASYNC_PREEMPT + /* + * Enable the routing of NS interrupts to EL3 + * during STD SMC processing on this core. + */ + enable_intr_rm_local(INTR_TYPE_NS, SECURE); +#endif + } + + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + SMC_RET3(&tsp_ctx->cpu_ctx, smc_fid, x1, x2); + } else { + /* + * This is the result from the secure client of an + * earlier request. The results are in x1-x3. Copy it + * into the non-secure context, save the secure state + * and return to the non-secure state. + */ + assert(handle == cm_get_context(SECURE)); + cm_el1_sysregs_context_save(SECURE); + + /* Get a reference to the non-secure context */ + ns_cpu_context = cm_get_context(NON_SECURE); + assert(ns_cpu_context); + + /* Restore non-secure state */ + cm_el1_sysregs_context_restore(NON_SECURE); + cm_set_next_eret_context(NON_SECURE); + if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_STD) { + clr_std_smc_active_flag(tsp_ctx->state); +#if TSP_NS_INTR_ASYNC_PREEMPT + /* + * Disable the routing of NS interrupts to EL3 + * after STD SMC processing is finished on this + * core. + */ + disable_intr_rm_local(INTR_TYPE_NS, SECURE); +#endif + } + + SMC_RET3(ns_cpu_context, x1, x2, x3); + } + + break; + + /* + * Request from non secure world to resume the preempted + * Standard SMC call. + */ + case TSP_FID_RESUME: + /* RESUME should be invoked only by normal world */ + if (!ns) { + assert(0); + break; + } + + /* + * This is a resume request from the non-secure client. + * save the non-secure state and send the request to + * the secure payload. + */ + assert(handle == cm_get_context(NON_SECURE)); + + /* Check if we are already preempted before resume */ + if (!get_std_smc_active_flag(tsp_ctx->state)) + SMC_RET1(handle, SMC_UNK); + + cm_el1_sysregs_context_save(NON_SECURE); + + /* + * We are done stashing the non-secure context. Ask the + * secure payload to do the work now. + */ +#if TSP_NS_INTR_ASYNC_PREEMPT + /* + * Enable the routing of NS interrupts to EL3 during resumption + * of STD SMC call on this core. + */ + enable_intr_rm_local(INTR_TYPE_NS, SECURE); +#endif + + + + /* We just need to return to the preempted point in + * TSP and the execution will resume as normal. + */ + cm_el1_sysregs_context_restore(SECURE); + cm_set_next_eret_context(SECURE); + SMC_RET0(&tsp_ctx->cpu_ctx); + + /* + * This is a request from the secure payload for more arguments + * for an ongoing arithmetic operation requested by the + * non-secure world. Simply return the arguments from the non- + * secure client in the original call. + */ + case TSP_GET_ARGS: + if (ns) + SMC_RET1(handle, SMC_UNK); + + get_tsp_args(tsp_ctx, x1, x2); + SMC_RET2(handle, x1, x2); + + case TOS_CALL_COUNT: + /* + * Return the number of service function IDs implemented to + * provide service to non-secure + */ + SMC_RET1(handle, TSP_NUM_FID); + + case TOS_UID: + /* Return TSP UID to the caller */ + SMC_UUID_RET(handle, tsp_uuid); + + case TOS_CALL_VERSION: + /* Return the version of current implementation */ + SMC_RET2(handle, TSP_VERSION_MAJOR, TSP_VERSION_MINOR); + + default: + break; + } + + SMC_RET1(handle, SMC_UNK); +} + +/* Define a SPD runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + tspd_fast, + + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_FAST, + tspd_setup, + tspd_smc_handler +); + +/* Define a SPD runtime service descriptor for standard SMC calls */ +DECLARE_RT_SVC( + tspd_std, + + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_STD, + NULL, + tspd_smc_handler +); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_pm.c b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_pm.c new file mode 100644 index 0000000..55562ba --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_pm.c @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "tspd_private.h" + +/******************************************************************************* + * The target cpu is being turned on. Allow the TSPD/TSP to perform any actions + * needed. Nothing at the moment. + ******************************************************************************/ +static void tspd_cpu_on_handler(uint64_t target_cpu) +{ +} + +/******************************************************************************* + * This cpu is being turned off. Allow the TSPD/TSP to perform any actions + * needed + ******************************************************************************/ +static int32_t tspd_cpu_off_handler(uint64_t unused) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + + assert(tsp_vectors); + assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); + + /* Program the entry point and enter the TSP */ + cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_off_entry); + rc = tspd_synchronous_sp_entry(tsp_ctx); + + /* + * Read the response from the TSP. A non-zero return means that + * something went wrong while communicating with the TSP. + */ + if (rc != 0) + panic(); + + /* + * Reset TSP's context for a fresh start when this cpu is turned on + * subsequently. + */ + set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_OFF); + + return 0; +} + +/******************************************************************************* + * This cpu is being suspended. S-EL1 state must have been saved in the + * resident cpu (mpidr format) if it is a UP/UP migratable TSP. + ******************************************************************************/ +static void tspd_cpu_suspend_handler(uint64_t max_off_pwrlvl) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + + assert(tsp_vectors); + assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); + + /* Program the entry point and enter the TSP */ + cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_suspend_entry); + rc = tspd_synchronous_sp_entry(tsp_ctx); + + /* + * Read the response from the TSP. A non-zero return means that + * something went wrong while communicating with the TSP. + */ + if (rc != 0) + panic(); + + /* Update its context to reflect the state the TSP is in */ + set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_SUSPEND); +} + +/******************************************************************************* + * This cpu has been turned on. Enter the TSP to initialise S-EL1 and other bits + * before passing control back to the Secure Monitor. Entry in S-El1 is done + * after initialising minimal architectural state that guarantees safe + * execution. + ******************************************************************************/ +static void tspd_cpu_on_finish_handler(uint64_t unused) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + entry_point_info_t tsp_on_entrypoint; + + assert(tsp_vectors); + assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_OFF); + + tspd_init_tsp_ep_state(&tsp_on_entrypoint, + TSP_AARCH64, + (uint64_t) &tsp_vectors->cpu_on_entry, + tsp_ctx); + + /* Initialise this cpu's secure context */ + cm_init_my_context(&tsp_on_entrypoint); + +#if TSP_NS_INTR_ASYNC_PREEMPT + /* + * Disable the NS interrupt locally since it will be enabled globally + * within cm_init_my_context. + */ + disable_intr_rm_local(INTR_TYPE_NS, SECURE); +#endif + + /* Enter the TSP */ + rc = tspd_synchronous_sp_entry(tsp_ctx); + + /* + * Read the response from the TSP. A non-zero return means that + * something went wrong while communicating with the SP. + */ + if (rc != 0) + panic(); + + /* Update its context to reflect the state the SP is in */ + set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); +} + +/******************************************************************************* + * This cpu has resumed from suspend. The SPD saved the TSP context when it + * completed the preceding suspend call. Use that context to program an entry + * into the TSP to allow it to do any remaining book keeping + ******************************************************************************/ +static void tspd_cpu_suspend_finish_handler(uint64_t max_off_pwrlvl) +{ + int32_t rc = 0; + uint32_t linear_id = plat_my_core_pos(); + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + + assert(tsp_vectors); + assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND); + + /* Program the entry point, max_off_pwrlvl and enter the SP */ + write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx), + CTX_GPREG_X0, + max_off_pwrlvl); + cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry); + rc = tspd_synchronous_sp_entry(tsp_ctx); + + /* + * Read the response from the TSP. A non-zero return means that + * something went wrong while communicating with the TSP. + */ + if (rc != 0) + panic(); + + /* Update its context to reflect the state the SP is in */ + set_tsp_pstate(tsp_ctx->state, TSP_PSTATE_ON); +} + +/******************************************************************************* + * Return the type of TSP the TSPD is dealing with. Report the current resident + * cpu (mpidr format) if it is a UP/UP migratable TSP. + ******************************************************************************/ +static int32_t tspd_cpu_migrate_info(uint64_t *resident_cpu) +{ + return TSP_MIGRATE_INFO; +} + +/******************************************************************************* + * System is about to be switched off. Allow the TSPD/TSP to perform + * any actions needed. + ******************************************************************************/ +static void tspd_system_off(void) +{ + uint32_t linear_id = plat_my_core_pos(); + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + + assert(tsp_vectors); + assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); + + /* Program the entry point */ + cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_off_entry); + + /* Enter the TSP. We do not care about the return value because we + * must continue the shutdown anyway */ + tspd_synchronous_sp_entry(tsp_ctx); +} + +/******************************************************************************* + * System is about to be reset. Allow the TSPD/TSP to perform + * any actions needed. + ******************************************************************************/ +static void tspd_system_reset(void) +{ + uint32_t linear_id = plat_my_core_pos(); + tsp_context_t *tsp_ctx = &tspd_sp_context[linear_id]; + + assert(tsp_vectors); + assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_ON); + + /* Program the entry point */ + cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->system_reset_entry); + + /* Enter the TSP. We do not care about the return value because we + * must continue the reset anyway */ + tspd_synchronous_sp_entry(tsp_ctx); +} + +/******************************************************************************* + * Structure populated by the TSP Dispatcher to be given a chance to perform any + * TSP bookkeeping before PSCI executes a power mgmt. operation. + ******************************************************************************/ +const spd_pm_ops_t tspd_pm = { + .svc_on = tspd_cpu_on_handler, + .svc_off = tspd_cpu_off_handler, + .svc_suspend = tspd_cpu_suspend_handler, + .svc_on_finish = tspd_cpu_on_finish_handler, + .svc_suspend_finish = tspd_cpu_suspend_finish_handler, + .svc_migrate = NULL, + .svc_migrate_info = tspd_cpu_migrate_info, + .svc_system_off = tspd_system_off, + .svc_system_reset = tspd_system_reset +}; diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_private.h b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_private.h new file mode 100644 index 0000000..cadc6aa --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/spd/tspd/tspd_private.h @@ -0,0 +1,250 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TSPD_PRIVATE_H__ +#define __TSPD_PRIVATE_H__ + +#include +#include +#include +#include +#include + +/******************************************************************************* + * Secure Payload PM state information e.g. SP is suspended, uninitialised etc + * and macros to access the state information in the per-cpu 'state' flags + ******************************************************************************/ +#define TSP_PSTATE_OFF 0 +#define TSP_PSTATE_ON 1 +#define TSP_PSTATE_SUSPEND 2 +#define TSP_PSTATE_SHIFT 0 +#define TSP_PSTATE_MASK 0x3 +#define get_tsp_pstate(state) ((state >> TSP_PSTATE_SHIFT) & TSP_PSTATE_MASK) +#define clr_tsp_pstate(state) (state &= ~(TSP_PSTATE_MASK \ + << TSP_PSTATE_SHIFT)) +#define set_tsp_pstate(st, pst) do { \ + clr_tsp_pstate(st); \ + st |= (pst & TSP_PSTATE_MASK) << \ + TSP_PSTATE_SHIFT; \ + } while (0); + + +/* + * This flag is used by the TSPD to determine if the TSP is servicing a standard + * SMC request prior to programming the next entry into the TSP e.g. if TSP + * execution is preempted by a non-secure interrupt and handed control to the + * normal world. If another request which is distinct from what the TSP was + * previously doing arrives, then this flag will be help the TSPD to either + * reject the new request or service it while ensuring that the previous context + * is not corrupted. + */ +#define STD_SMC_ACTIVE_FLAG_SHIFT 2 +#define STD_SMC_ACTIVE_FLAG_MASK 1 +#define get_std_smc_active_flag(state) ((state >> STD_SMC_ACTIVE_FLAG_SHIFT) \ + & STD_SMC_ACTIVE_FLAG_MASK) +#define set_std_smc_active_flag(state) (state |= \ + 1 << STD_SMC_ACTIVE_FLAG_SHIFT) +#define clr_std_smc_active_flag(state) (state &= \ + ~(STD_SMC_ACTIVE_FLAG_MASK \ + << STD_SMC_ACTIVE_FLAG_SHIFT)) + +/******************************************************************************* + * Secure Payload execution state information i.e. aarch32 or aarch64 + ******************************************************************************/ +#define TSP_AARCH32 MODE_RW_32 +#define TSP_AARCH64 MODE_RW_64 + +/******************************************************************************* + * The SPD should know the type of Secure Payload. + ******************************************************************************/ +#define TSP_TYPE_UP PSCI_TOS_NOT_UP_MIG_CAP +#define TSP_TYPE_UPM PSCI_TOS_UP_MIG_CAP +#define TSP_TYPE_MP PSCI_TOS_NOT_PRESENT_MP + +/******************************************************************************* + * Secure Payload migrate type information as known to the SPD. We assume that + * the SPD is dealing with an MP Secure Payload. + ******************************************************************************/ +#define TSP_MIGRATE_INFO TSP_TYPE_MP + +/******************************************************************************* + * Number of cpus that the present on this platform. TODO: Rely on a topology + * tree to determine this in the future to avoid assumptions about mpidr + * allocation + ******************************************************************************/ +#define TSPD_CORE_COUNT PLATFORM_CORE_COUNT + +/******************************************************************************* + * Constants that allow assembler code to preserve callee-saved registers of the + * C runtime context while performing a security state switch. + ******************************************************************************/ +#define TSPD_C_RT_CTX_X19 0x0 +#define TSPD_C_RT_CTX_X20 0x8 +#define TSPD_C_RT_CTX_X21 0x10 +#define TSPD_C_RT_CTX_X22 0x18 +#define TSPD_C_RT_CTX_X23 0x20 +#define TSPD_C_RT_CTX_X24 0x28 +#define TSPD_C_RT_CTX_X25 0x30 +#define TSPD_C_RT_CTX_X26 0x38 +#define TSPD_C_RT_CTX_X27 0x40 +#define TSPD_C_RT_CTX_X28 0x48 +#define TSPD_C_RT_CTX_X29 0x50 +#define TSPD_C_RT_CTX_X30 0x58 +#define TSPD_C_RT_CTX_SIZE 0x60 +#define TSPD_C_RT_CTX_ENTRIES (TSPD_C_RT_CTX_SIZE >> DWORD_SHIFT) + +/******************************************************************************* + * Constants that allow assembler code to preserve caller-saved registers of the + * SP context while performing a TSP preemption. + * Note: These offsets have to match with the offsets for the corresponding + * registers in cpu_context as we are using memcpy to copy the values from + * cpu_context to sp_ctx. + ******************************************************************************/ +#define TSPD_SP_CTX_X0 0x0 +#define TSPD_SP_CTX_X1 0x8 +#define TSPD_SP_CTX_X2 0x10 +#define TSPD_SP_CTX_X3 0x18 +#define TSPD_SP_CTX_X4 0x20 +#define TSPD_SP_CTX_X5 0x28 +#define TSPD_SP_CTX_X6 0x30 +#define TSPD_SP_CTX_X7 0x38 +#define TSPD_SP_CTX_X8 0x40 +#define TSPD_SP_CTX_X9 0x48 +#define TSPD_SP_CTX_X10 0x50 +#define TSPD_SP_CTX_X11 0x58 +#define TSPD_SP_CTX_X12 0x60 +#define TSPD_SP_CTX_X13 0x68 +#define TSPD_SP_CTX_X14 0x70 +#define TSPD_SP_CTX_X15 0x78 +#define TSPD_SP_CTX_X16 0x80 +#define TSPD_SP_CTX_X17 0x88 +#define TSPD_SP_CTX_SIZE 0x90 +#define TSPD_SP_CTX_ENTRIES (TSPD_SP_CTX_SIZE >> DWORD_SHIFT) + +#ifndef __ASSEMBLY__ + +#include +#include + +/* + * The number of arguments to save during a SMC call for TSP. + * Currently only x1 and x2 are used by TSP. + */ +#define TSP_NUM_ARGS 0x2 + +/* AArch64 callee saved general purpose register context structure. */ +DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES); + +/* + * Compile time assertion to ensure that both the compiler and linker + * have the same double word aligned view of the size of the C runtime + * register context. + */ +CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ + assert_spd_c_rt_regs_size_mismatch); + +/* SEL1 Secure payload (SP) caller saved register context structure. */ +DEFINE_REG_STRUCT(sp_ctx_regs, TSPD_SP_CTX_ENTRIES); + +/* + * Compile time assertion to ensure that both the compiler and linker + * have the same double word aligned view of the size of the C runtime + * register context. + */ +CASSERT(TSPD_SP_CTX_SIZE == sizeof(sp_ctx_regs_t), \ + assert_spd_sp_regs_size_mismatch); + +/******************************************************************************* + * Structure which helps the SPD to maintain the per-cpu state of the SP. + * 'saved_spsr_el3' - temporary copy to allow S-EL1 interrupt handling when + * the TSP has been preempted. + * 'saved_elr_el3' - temporary copy to allow S-EL1 interrupt handling when + * the TSP has been preempted. + * 'state' - collection of flags to track SP state e.g. on/off + * 'mpidr' - mpidr to associate a context with a cpu + * 'c_rt_ctx' - stack address to restore C runtime context from after + * returning from a synchronous entry into the SP. + * 'cpu_ctx' - space to maintain SP architectural state + * 'saved_tsp_args' - space to store arguments for TSP arithmetic operations + * which will queried using the TSP_GET_ARGS SMC by TSP. + * 'sp_ctx' - space to save the SEL1 Secure Payload(SP) caller saved + * register context after it has been preempted by an EL3 + * routed NS interrupt and when a Secure Interrupt is taken + * to SP. + ******************************************************************************/ +typedef struct tsp_context { + uint64_t saved_elr_el3; + uint32_t saved_spsr_el3; + uint32_t state; + uint64_t mpidr; + uint64_t c_rt_ctx; + cpu_context_t cpu_ctx; + uint64_t saved_tsp_args[TSP_NUM_ARGS]; +#if TSP_NS_INTR_ASYNC_PREEMPT + sp_ctx_regs_t sp_ctx; +#endif +} tsp_context_t; + +/* Helper macros to store and retrieve tsp args from tsp_context */ +#define store_tsp_args(tsp_ctx, x1, x2) do {\ + tsp_ctx->saved_tsp_args[0] = x1;\ + tsp_ctx->saved_tsp_args[1] = x2;\ + } while (0) + +#define get_tsp_args(tsp_ctx, x1, x2) do {\ + x1 = tsp_ctx->saved_tsp_args[0];\ + x2 = tsp_ctx->saved_tsp_args[1];\ + } while (0) + +/* TSPD power management handlers */ +extern const spd_pm_ops_t tspd_pm; + +/******************************************************************************* + * Forward declarations + ******************************************************************************/ +struct tsp_vectors; + +/******************************************************************************* + * Function & Data prototypes + ******************************************************************************/ +uint64_t tspd_enter_sp(uint64_t *c_rt_ctx); +void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); +uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx); +void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret); +void tspd_init_tsp_ep_state(struct entry_point_info *tsp_ep, + uint32_t rw, + uint64_t pc, + tsp_context_t *tsp_ctx); + +extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; +extern struct tsp_vectors *tsp_vectors; +#endif /*__ASSEMBLY__*/ + +#endif /* __TSPD_PRIVATE_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/services/std_svc/std_svc_setup.c b/IPL/SDK/v3m/src/arm-trusted-firmware/services/std_svc/std_svc_setup.c new file mode 100644 index 0000000..e096601 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/services/std_svc/std_svc_setup.c @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Standard Service UUID */ +DEFINE_SVC_UUID(arm_svc_uid, + 0x108d905b, 0xf863, 0x47e8, 0xae, 0x2d, + 0xc0, 0xfb, 0x56, 0x41, 0xf6, 0xe2); + +/* Setup Standard Services */ +static int32_t std_svc_setup(void) +{ + uintptr_t svc_arg; + + svc_arg = get_arm_std_svc_args(PSCI_FID_MASK); + assert(svc_arg); + + /* + * PSCI is the only specification implemented as a Standard Service. + * The `psci_setup()` also does EL3 architectural setup. + */ + return psci_setup((const psci_lib_args_t *)svc_arg); +} + +/* + * Top-level Standard Service SMC handler. This handler will in turn dispatch + * calls to PSCI SMC handler + */ +uintptr_t std_svc_smc_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + /* + * Dispatch PSCI calls to PSCI SMC handler and return its return + * value + */ + if (is_psci_fid(smc_fid)) { + SMC_RET1(handle, + psci_smc_handler(smc_fid, x1, x2, x3, x4, + cookie, handle, flags)); + } + + switch (smc_fid) { + case ARM_STD_SVC_CALL_COUNT: + /* + * Return the number of Standard Service Calls. PSCI is the only + * standard service implemented; so return number of PSCI calls + */ + SMC_RET1(handle, PSCI_NUM_CALLS); + + case ARM_STD_SVC_UID: + /* Return UID to the caller */ + SMC_UUID_RET(handle, arm_svc_uid); + + case ARM_STD_SVC_VERSION: + /* Return the version of current implementation */ + SMC_RET2(handle, STD_SVC_VERSION_MAJOR, STD_SVC_VERSION_MINOR); + + default: + WARN("Unimplemented Standard Service Call: 0x%x \n", smc_fid); + SMC_RET1(handle, SMC_UNK); + } +} + +/* Register Standard Service Calls as runtime service */ +DECLARE_RT_SVC( + std_svc, + + OEN_STD_START, + OEN_STD_END, + SMC_TYPE_FAST, + std_svc_setup, + std_svc_smc_handler +); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/Makefile b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/Makefile new file mode 100644 index 0000000..27545ba --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/Makefile @@ -0,0 +1,102 @@ +# +# Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +PROJECT := cert_create +PLAT := none +V := 0 +DEBUG := 0 +BINARY := ${PROJECT}${BIN_EXT} +OPENSSL_DIR := /usr + +OBJECTS := src/cert.o \ + src/cmd_opt.o \ + src/ext.o \ + src/key.o \ + src/main.o \ + src/sha.o \ + src/tbbr/tbb_cert.o \ + src/tbbr/tbb_ext.o \ + src/tbbr/tbb_key.o + +CFLAGS := -Wall -std=c99 + +MAKE_HELPERS_DIRECTORY := ../../make_helpers/ +include ${MAKE_HELPERS_DIRECTORY}build_macros.mk +include ${MAKE_HELPERS_DIRECTORY}build_env.mk + +PLATFORM_ROOT := ../../plat/ +include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk + +PLAT_INCLUDE := $(wildcard ${PLAT_DIR}include) + +ifeq ($(PLAT_INCLUDE),) + $(error "Error: Invalid platform '${PLAT}' has no include directory.") +endif + +ifeq (${DEBUG},1) + CFLAGS += -g -O0 -DDEBUG -DLOG_LEVEL=40 +else + CFLAGS += -O2 -DLOG_LEVEL=20 +endif +ifeq (${V},0) + Q := @ +else + Q := +endif + +# Make soft links and include from local directory otherwise wrong headers +# could get pulled in from firmware tree. +INC_DIR := -I ./include -I ${PLAT_INCLUDE} -I ${OPENSSL_DIR}/include +LIB_DIR := -L ${OPENSSL_DIR}/lib +LIB := -lssl -lcrypto + +CC := gcc + +.PHONY: all clean realclean + +all: clean ${BINARY} + +${BINARY}: ${OBJECTS} Makefile + @echo " LD $@" + @echo 'const char build_msg[] = "Built : "__TIME__", "__DATE__; \ + const char platform_msg[] = "${PLAT}";' | \ + ${CC} -c ${CFLAGS} -xc - -o src/build_msg.o + ${Q}${CC} src/build_msg.o ${OBJECTS} ${LIB_DIR} ${LIB} -o $@ + +%.o: %.c + @echo " CC $<" + ${Q}${CC} -c ${CFLAGS} ${INC_DIR} $< -o $@ + +clean: + $(call SHELL_DELETE_ALL, src/build_msg.o ${OBJECTS}) + +realclean: clean + $(call SHELL_DELETE, ${BINARY}) + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/cert.h b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/cert.h new file mode 100644 index 0000000..6b1ae95 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/cert.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef CERT_H_ +#define CERT_H_ + +#include +#include +#include "ext.h" +#include "key.h" + +#define CERT_MAX_EXT 4 + +/* + * This structure contains information related to the generation of the + * certificates. All these fields must be known and specified at build time + * except for the file name, which is picked up from the command line at + * run time. + * + * One instance of this structure must be created for each of the certificates + * present in the chain of trust. + * + * If the issuer points to this same instance, the generated certificate will + * be self-signed. + */ +typedef struct cert_s cert_t; +struct cert_s { + int id; /* Unique identifier */ + + const char *opt; /* Command line option to pass filename */ + const char *fn; /* Filename to save the certificate */ + const char *cn; /* Subject CN (Company Name) */ + const char *help_msg; /* Help message */ + + /* These fields must be defined statically */ + int key; /* Key to be signed */ + int issuer; /* Issuer certificate */ + int ext[CERT_MAX_EXT]; /* Certificate extensions */ + int num_ext; /* Number of extensions in the certificate */ + + X509 *x; /* X509 certificate container */ +}; + +/* Exported API */ +int cert_init(void); +cert_t *cert_get_by_opt(const char *opt); +int cert_add_ext(X509 *issuer, X509 *subject, int nid, char *value); +int cert_new(cert_t *cert, int days, int ca, STACK_OF(X509_EXTENSION) * sk); + +/* Macro to register the certificates used in the CoT */ +#define REGISTER_COT(_certs) \ + cert_t *certs = &_certs[0]; \ + const unsigned int num_certs = sizeof(_certs)/sizeof(_certs[0]) + +/* Exported variables */ +extern cert_t *certs; +extern const unsigned int num_certs; + +#endif /* CERT_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/cmd_opt.h b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/cmd_opt.h new file mode 100644 index 0000000..389aa23 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/cmd_opt.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef CMD_OPT_H_ +#define CMD_OPT_H_ + +#include + +#define CMD_OPT_MAX_NUM 64 + +/* Supported long command line option types */ +enum { + CMD_OPT_CERT, + CMD_OPT_KEY, + CMD_OPT_EXT +}; + +/* Structure to define a command line option */ +typedef struct cmd_opt_s { + struct option long_opt; + const char *help_msg; +} cmd_opt_t; + +/* Exported API*/ +void cmd_opt_add(const cmd_opt_t *cmd_opt); +const struct option *cmd_opt_get_array(void); +const char *cmd_opt_get_name(int idx); +const char *cmd_opt_get_help_msg(int idx); + +#endif /* CMD_OPT_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/debug.h b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/debug.h new file mode 100644 index 0000000..dd0510a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/debug.h @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +#include + +/* The log output macros print output to the console. These macros produce + * compiled log output only if the LOG_LEVEL defined in the makefile (or the + * make command line) is greater or equal than the level required for that + * type of log output. + * The format expected is the same as for printf(). For example: + * INFO("Info %s.\n", "message") -> INFO: Info message. + * WARN("Warning %s.\n", "message") -> WARNING: Warning message. + */ + +#define LOG_LEVEL_NONE 0 +#define LOG_LEVEL_ERROR 10 +#define LOG_LEVEL_NOTICE 20 +#define LOG_LEVEL_WARNING 30 +#define LOG_LEVEL_INFO 40 +#define LOG_LEVEL_VERBOSE 50 + + +#if LOG_LEVEL >= LOG_LEVEL_NOTICE +# define NOTICE(...) printf("NOTICE: " __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_ERROR +# define ERROR(...) printf("ERROR: " __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_WARNING +# define WARN(...) printf("WARNING: " __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_INFO +# define INFO(...) printf("INFO: " __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE +# define VERBOSE(...) printf("VERBOSE: " __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + +#endif /* __DEBUG_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/ext.h b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/ext.h new file mode 100644 index 0000000..95bde6c --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/ext.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef EXT_H_ +#define EXT_H_ + +#include "key.h" +#include + +/* Extension types supported */ +enum ext_type_e { + EXT_TYPE_NVCOUNTER, + EXT_TYPE_PKEY, + EXT_TYPE_HASH +}; + +/* NV-Counter types */ +enum nvctr_type_e { + NVCTR_TYPE_TFW, + NVCTR_TYPE_NTFW +}; + +/* + * This structure contains the relevant information to create the extensions + * to be included in the certificates. This extensions will be used to + * establish the chain of trust. + */ +typedef struct ext_s { + const char *oid; /* OID of the extension */ + const char *sn; /* Short name */ + const char *ln; /* Long description */ + const char *opt; /* Command line option to specify data */ + const char *help_msg; /* Help message */ + const char *arg; /* Argument passed from command line */ + int asn1_type; /* OpenSSL ASN1 type of the extension data. + * Supported types are: + * - V_ASN1_INTEGER + * - V_ASN1_OCTET_STRING + */ + int type; /* See ext_type_e */ + + /* Extension attributes (depends on extension type) */ + union { + int nvctr_type; /* See nvctr_type_e */ + int key; /* Index into array of registered public keys */ + } attr; + + int alias; /* In case OpenSSL provides an standard + * extension of the same type, add the new + * extension as an alias of this one + */ + + X509V3_EXT_METHOD method; /* This field may be used to define a custom + * function to print the contents of the + * extension */ + + int optional; /* This field may be used optionally to exclude an image */ +} ext_t; + +enum { + EXT_NON_CRIT = 0, + EXT_CRIT = !EXT_NON_CRIT, +}; + +/* Exported API */ +int ext_init(void); +ext_t *ext_get_by_opt(const char *opt); +X509_EXTENSION *ext_new_hash(int nid, int crit, const EVP_MD *md, + unsigned char *buf, size_t len); +X509_EXTENSION *ext_new_nvcounter(int nid, int crit, int value); +X509_EXTENSION *ext_new_key(int nid, int crit, EVP_PKEY *k); + +/* Macro to register the extensions used in the CoT */ +#define REGISTER_EXTENSIONS(_ext) \ + ext_t *extensions = &_ext[0]; \ + const unsigned int num_extensions = sizeof(_ext)/sizeof(_ext[0]) + +/* Exported variables */ +extern ext_t *extensions; +extern const unsigned int num_extensions; + +#endif /* EXT_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/key.h b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/key.h new file mode 100644 index 0000000..f60997f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/key.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef KEY_H_ +#define KEY_H_ + +#include + +#define RSA_KEY_BITS 2048 + +/* Error codes */ +enum { + KEY_ERR_NONE, + KEY_ERR_MALLOC, + KEY_ERR_FILENAME, + KEY_ERR_OPEN, + KEY_ERR_LOAD +}; + +/* Supported key algorithms */ +enum { + KEY_ALG_RSA, +#ifndef OPENSSL_NO_EC + KEY_ALG_ECDSA, +#endif /* OPENSSL_NO_EC */ + KEY_ALG_MAX_NUM +}; + +/* + * This structure contains the relevant information to create the keys + * required to sign the certificates. + * + * One instance of this structure must be created for each key, usually in an + * array fashion. The filename is obtained at run time from the command line + * parameters + */ +typedef struct key_s { + int id; /* Key id */ + const char *opt; /* Command line option to specify a key */ + const char *help_msg; /* Help message */ + const char *desc; /* Key description (debug purposes) */ + char *fn; /* Filename to load/store the key */ + EVP_PKEY *key; /* Key container */ +} key_t; + +/* Exported API */ +int key_init(void); +key_t *key_get_by_opt(const char *opt); +int key_create(key_t *key, int type); +int key_load(key_t *key, unsigned int *err_code); +int key_store(key_t *key); + +/* Macro to register the keys used in the CoT */ +#define REGISTER_KEYS(_keys) \ + key_t *keys = &_keys[0]; \ + const unsigned int num_keys = sizeof(_keys)/sizeof(_keys[0]) + +/* Exported variables */ +extern key_t *keys; +extern const unsigned int num_keys; + +#endif /* KEY_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/sha.h b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/sha.h new file mode 100644 index 0000000..466d668 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/sha.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef SHA_H_ +#define SHA_H_ + +int sha_file(const char *filename, unsigned char *md); + +#endif /* SHA_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/tbbr/tbb_cert.h b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/tbbr/tbb_cert.h new file mode 100644 index 0000000..c0f7ba2 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/tbbr/tbb_cert.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef TBB_CERT_H_ +#define TBB_CERT_H_ + +#include "cert.h" + +/* + * Enumerate the certificates that are used to establish the chain of trust + */ +enum { + TRUSTED_BOOT_FW_CERT, + TRUSTED_KEY_CERT, + SCP_FW_KEY_CERT, + SCP_FW_CONTENT_CERT, + SOC_FW_KEY_CERT, + SOC_FW_CONTENT_CERT, + TRUSTED_OS_FW_KEY_CERT, + TRUSTED_OS_FW_CONTENT_CERT, + NON_TRUSTED_FW_KEY_CERT, + NON_TRUSTED_FW_CONTENT_CERT, + FWU_CERT +}; + +#endif /* TBB_CERT_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/tbbr/tbb_ext.h b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/tbbr/tbb_ext.h new file mode 100644 index 0000000..8589cf7 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/tbbr/tbb_ext.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#ifndef TBB_EXT_H_ +#define TBB_EXT_H_ + +#include "ext.h" + +/* TBBR extensions */ +enum { + TRUSTED_FW_NVCOUNTER_EXT, + NON_TRUSTED_FW_NVCOUNTER_EXT, + TRUSTED_BOOT_FW_HASH_EXT, + TRUSTED_WORLD_PK_EXT, + NON_TRUSTED_WORLD_PK_EXT, + SCP_FW_CONTENT_CERT_PK_EXT, + SCP_FW_HASH_EXT, + SOC_FW_CONTENT_CERT_PK_EXT, + SOC_AP_FW_HASH_EXT, + TRUSTED_OS_FW_CONTENT_CERT_PK_EXT, + TRUSTED_OS_FW_HASH_EXT, + NON_TRUSTED_FW_CONTENT_CERT_PK_EXT, + NON_TRUSTED_WORLD_BOOTLOADER_HASH_EXT, + SCP_FWU_CFG_HASH_EXT, + AP_FWU_CFG_HASH_EXT, + FWU_HASH_EXT +}; + +#endif /* TBB_EXT_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/tbbr/tbb_key.h b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/tbbr/tbb_key.h new file mode 100644 index 0000000..0becf3f --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/include/tbbr/tbb_key.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef TBB_KEY_H_ +#define TBB_KEY_H_ + +#include "key.h" + +/* + * Enumerate the keys that are used to establish the chain of trust + */ +enum { + ROT_KEY, + TRUSTED_WORLD_KEY, + NON_TRUSTED_WORLD_KEY, + SCP_FW_CONTENT_CERT_KEY, + SOC_FW_CONTENT_CERT_KEY, + TRUSTED_OS_FW_CONTENT_CERT_KEY, + NON_TRUSTED_FW_CONTENT_CERT_KEY +}; + +#endif /* TBB_KEY_H_ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/cert.c b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/cert.c new file mode 100644 index 0000000..a559832 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/cert.c @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "cert.h" +#include "cmd_opt.h" +#include "debug.h" +#include "key.h" +#include "platform_oid.h" +#include "sha.h" + +#define SERIAL_RAND_BITS 64 + +int rand_serial(BIGNUM *b, ASN1_INTEGER *ai) +{ + BIGNUM *btmp; + int ret = 0; + if (b) + btmp = b; + else + btmp = BN_new(); + + if (!btmp) + return 0; + + if (!BN_pseudo_rand(btmp, SERIAL_RAND_BITS, 0, 0)) + goto error; + if (ai && !BN_to_ASN1_INTEGER(btmp, ai)) + goto error; + + ret = 1; + +error: + + if (!b) + BN_free(btmp); + + return ret; +} + +int cert_add_ext(X509 *issuer, X509 *subject, int nid, char *value) +{ + X509_EXTENSION *ex; + X509V3_CTX ctx; + + /* No configuration database */ + X509V3_set_ctx_nodb(&ctx); + + /* Set issuer and subject certificates in the context */ + X509V3_set_ctx(&ctx, issuer, subject, NULL, NULL, 0); + ex = X509V3_EXT_conf_nid(NULL, &ctx, nid, value); + if (!ex) { + ERR_print_errors_fp(stdout); + return 0; + } + + X509_add_ext(subject, ex, -1); + X509_EXTENSION_free(ex); + + return 1; +} + + +int cert_new(cert_t *cert, int days, int ca, STACK_OF(X509_EXTENSION) * sk) +{ + EVP_PKEY *pkey = keys[cert->key].key; + cert_t *issuer_cert = &certs[cert->issuer]; + EVP_PKEY *ikey = keys[issuer_cert->key].key; + X509 *issuer = issuer_cert->x; + X509 *x = NULL; + X509_EXTENSION *ex = NULL; + X509_NAME *name = NULL; + ASN1_INTEGER *sno = NULL; + int i, num; + + /* Create the certificate structure */ + x = X509_new(); + if (!x) { + return 0; + } + + /* If we do not have a key, use the issuer key (the certificate will + * become self signed). This happens in content certificates. */ + if (!pkey) { + pkey = ikey; + } + + /* If we do not have an issuer certificate, use our own (the certificate + * will become self signed) */ + if (!issuer) { + issuer = x; + } + + /* x509.v3 */ + X509_set_version(x, 2); + + /* Random serial number */ + sno = ASN1_INTEGER_new(); + rand_serial(NULL, sno); + X509_set_serialNumber(x, sno); + ASN1_INTEGER_free(sno); + + X509_gmtime_adj(X509_get_notBefore(x), 0); + X509_gmtime_adj(X509_get_notAfter(x), (long)60*60*24*days); + X509_set_pubkey(x, pkey); + + /* Subject name */ + name = X509_get_subject_name(x); + X509_NAME_add_entry_by_txt(name, "CN", MBSTRING_ASC, + (const unsigned char *)cert->cn, -1, -1, 0); + X509_set_subject_name(x, name); + + /* Issuer name */ + name = X509_get_issuer_name(x); + X509_NAME_add_entry_by_txt(name, "CN", MBSTRING_ASC, + (const unsigned char *)issuer_cert->cn, -1, -1, 0); + X509_set_issuer_name(x, name); + + /* Add various extensions: standard extensions */ + cert_add_ext(issuer, x, NID_subject_key_identifier, "hash"); + cert_add_ext(issuer, x, NID_authority_key_identifier, "keyid:always"); + if (ca) { + cert_add_ext(issuer, x, NID_basic_constraints, "CA:TRUE"); + cert_add_ext(issuer, x, NID_key_usage, "keyCertSign"); + } else { + cert_add_ext(issuer, x, NID_basic_constraints, "CA:FALSE"); + } + + /* Add custom extensions */ + if (sk != NULL) { + num = sk_X509_EXTENSION_num(sk); + for (i = 0; i < num; i++) { + ex = sk_X509_EXTENSION_value(sk, i); + X509_add_ext(x, ex, -1); + } + } + + /* Sign the certificate with the issuer key */ + if (!X509_sign(x, ikey, EVP_sha256())) { + ERR_print_errors_fp(stdout); + return 0; + } + + cert->x = x; + return 1; +} + +int cert_init(void) +{ + cmd_opt_t cmd_opt; + cert_t *cert; + unsigned int i; + + for (i = 0; i < num_certs; i++) { + cert = &certs[i]; + cmd_opt.long_opt.name = cert->opt; + cmd_opt.long_opt.has_arg = required_argument; + cmd_opt.long_opt.flag = NULL; + cmd_opt.long_opt.val = CMD_OPT_CERT; + cmd_opt.help_msg = cert->help_msg; + cmd_opt_add(&cmd_opt); + } + + return 0; +} + +cert_t *cert_get_by_opt(const char *opt) +{ + cert_t *cert = NULL; + unsigned int i; + + for (i = 0; i < num_certs; i++) { + cert = &certs[i]; + if (0 == strcmp(cert->opt, opt)) { + return cert; + } + } + + return NULL; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/cmd_opt.c b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/cmd_opt.c new file mode 100644 index 0000000..ecf84ab --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/cmd_opt.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include "debug.h" + +/* Command line options */ +static struct option long_opt[CMD_OPT_MAX_NUM+1]; +static const char *help_msg[CMD_OPT_MAX_NUM+1]; +static int num_reg_opt; + +void cmd_opt_add(const cmd_opt_t *cmd_opt) +{ + assert(cmd_opt != NULL); + + if (num_reg_opt >= CMD_OPT_MAX_NUM) { + ERROR("Out of memory. Please increase CMD_OPT_MAX_NUM\n"); + exit(1); + } + + long_opt[num_reg_opt].name = cmd_opt->long_opt.name; + long_opt[num_reg_opt].has_arg = cmd_opt->long_opt.has_arg; + long_opt[num_reg_opt].flag = 0; + long_opt[num_reg_opt].val = cmd_opt->long_opt.val; + + help_msg[num_reg_opt] = cmd_opt->help_msg; + + num_reg_opt++; +} + +const struct option *cmd_opt_get_array(void) +{ + return long_opt; +} + +const char *cmd_opt_get_name(int idx) +{ + if (idx >= num_reg_opt) { + return NULL; + } + + return long_opt[idx].name; +} + +const char *cmd_opt_get_help_msg(int idx) +{ + if (idx >= num_reg_opt) { + return NULL; + } + + return help_msg[idx]; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/ext.c b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/ext.c new file mode 100644 index 0000000..3f56edb --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/ext.c @@ -0,0 +1,332 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "cmd_opt.h" +#include "ext.h" + +DECLARE_ASN1_ITEM(ASN1_INTEGER) +DECLARE_ASN1_ITEM(X509_ALGOR) +DECLARE_ASN1_ITEM(ASN1_OCTET_STRING) + +typedef struct { + X509_ALGOR *hashAlgorithm; + ASN1_OCTET_STRING *dataHash; +} HASH; + +ASN1_SEQUENCE(HASH) = { + ASN1_SIMPLE(HASH, hashAlgorithm, X509_ALGOR), + ASN1_SIMPLE(HASH, dataHash, ASN1_OCTET_STRING), +} ASN1_SEQUENCE_END(HASH) + +DECLARE_ASN1_FUNCTIONS(HASH) +IMPLEMENT_ASN1_FUNCTIONS(HASH) + +/* + * This function adds the TBB extensions to the internal extension list + * maintained by OpenSSL so they can be used later. + * + * It also initializes the methods to print the contents of the extension. If an + * alias is specified in the TBB extension, we reuse the methods of the alias. + * Otherwise, only methods for V_ASN1_INTEGER and V_ASN1_OCTET_STRING are + * provided. Any other type will be printed as a raw ascii string. + * + * Return: 0 = success, Otherwise: error + */ +int ext_init(void) +{ + cmd_opt_t cmd_opt; + ext_t *ext; + X509V3_EXT_METHOD *m; + int nid, ret; + unsigned int i; + + for (i = 0; i < num_extensions; i++) { + ext = &extensions[i]; + /* Register command line option */ + if (ext->opt) { + cmd_opt.long_opt.name = ext->opt; + cmd_opt.long_opt.has_arg = required_argument; + cmd_opt.long_opt.flag = NULL; + cmd_opt.long_opt.val = CMD_OPT_EXT; + cmd_opt.help_msg = ext->help_msg; + cmd_opt_add(&cmd_opt); + } + /* Register the extension OID in OpenSSL */ + if (ext->oid == NULL) { + continue; + } + nid = OBJ_create(ext->oid, ext->sn, ext->ln); + if (ext->alias) { + X509V3_EXT_add_alias(nid, ext->alias); + } else { + m = &ext->method; + memset(m, 0x0, sizeof(X509V3_EXT_METHOD)); + switch (ext->asn1_type) { + case V_ASN1_INTEGER: + m->it = ASN1_ITEM_ref(ASN1_INTEGER); + m->i2s = (X509V3_EXT_I2S)i2s_ASN1_INTEGER; + m->s2i = (X509V3_EXT_S2I)s2i_ASN1_INTEGER; + break; + case V_ASN1_OCTET_STRING: + m->it = ASN1_ITEM_ref(ASN1_OCTET_STRING); + m->i2s = (X509V3_EXT_I2S)i2s_ASN1_OCTET_STRING; + m->s2i = (X509V3_EXT_S2I)s2i_ASN1_OCTET_STRING; + break; + default: + continue; + } + m->ext_nid = nid; + ret = X509V3_EXT_add(m); + if (!ret) { + ERR_print_errors_fp(stdout); + return 1; + } + } + } + return 0; +} + +/* + * Create a new extension + * + * Extension ::= SEQUENCE { + * id OBJECT IDENTIFIER, + * critical BOOLEAN DEFAULT FALSE, + * value OCTET STRING } + * + * Parameters: + * pex: OpenSSL extension pointer (output parameter) + * nid: extension identifier + * crit: extension critical (EXT_NON_CRIT, EXT_CRIT) + * data: extension data. This data will be encapsulated in an Octet String + * + * Return: Extension address, NULL if error + */ +static +X509_EXTENSION *ext_new(int nid, int crit, unsigned char *data, int len) +{ + X509_EXTENSION *ex; + ASN1_OCTET_STRING *ext_data; + + /* Octet string containing the extension data */ + ext_data = ASN1_OCTET_STRING_new(); + ASN1_OCTET_STRING_set(ext_data, data, len); + + /* Create the extension */ + ex = X509_EXTENSION_create_by_NID(NULL, nid, crit, ext_data); + + /* The extension makes a copy of the data, so we can free this object */ + ASN1_OCTET_STRING_free(ext_data); + + return ex; +} + +/* + * Creates a x509v3 extension containing a hash + * + * DigestInfo ::= SEQUENCE { + * digestAlgorithm AlgorithmIdentifier, + * digest OCTET STRING + * } + * + * AlgorithmIdentifier ::= SEQUENCE { + * algorithm OBJECT IDENTIFIER, + * parameters ANY DEFINED BY algorithm OPTIONAL + * } + * + * Parameters: + * nid: extension identifier + * crit: extension critical (EXT_NON_CRIT, EXT_CRIT) + * md: hash algorithm + * buf: pointer to the buffer that contains the hash + * len: size of the hash in bytes + * + * Return: Extension address, NULL if error + */ +X509_EXTENSION *ext_new_hash(int nid, int crit, const EVP_MD *md, + unsigned char *buf, size_t len) +{ + X509_EXTENSION *ex = NULL; + ASN1_OCTET_STRING *octet = NULL; + HASH *hash = NULL; + ASN1_OBJECT *algorithm = NULL; + X509_ALGOR *x509_algor = NULL; + unsigned char *p = NULL; + int sz = -1; + + /* OBJECT_IDENTIFIER with hash algorithm */ + algorithm = OBJ_nid2obj(md->type); + if (algorithm == NULL) { + return NULL; + } + + /* Create X509_ALGOR */ + x509_algor = X509_ALGOR_new(); + if (x509_algor == NULL) { + return NULL; + } + x509_algor->algorithm = algorithm; + x509_algor->parameter = ASN1_TYPE_new(); + ASN1_TYPE_set(x509_algor->parameter, V_ASN1_NULL, NULL); + + /* OCTET_STRING with the actual hash */ + octet = ASN1_OCTET_STRING_new(); + if (octet == NULL) { + X509_ALGOR_free(x509_algor); + return NULL; + } + ASN1_OCTET_STRING_set(octet, buf, len); + + /* HASH structure containing algorithm + hash */ + hash = HASH_new(); + if (hash == NULL) { + ASN1_OCTET_STRING_free(octet); + X509_ALGOR_free(x509_algor); + return NULL; + } + hash->hashAlgorithm = x509_algor; + hash->dataHash = octet; + + /* DER encoded HASH */ + sz = i2d_HASH(hash, &p); + if ((sz <= 0) || (p == NULL)) { + HASH_free(hash); + X509_ALGOR_free(x509_algor); + return NULL; + } + + /* Create the extension */ + ex = ext_new(nid, crit, p, sz); + + /* Clean up */ + OPENSSL_free(p); + HASH_free(hash); + + return ex; +} + +/* + * Creates a x509v3 extension containing a nvcounter encapsulated in an ASN1 + * Integer + * + * Parameters: + * pex: OpenSSL extension pointer (output parameter) + * nid: extension identifier + * crit: extension critical (EXT_NON_CRIT, EXT_CRIT) + * value: nvcounter value + * + * Return: Extension address, NULL if error + */ +X509_EXTENSION *ext_new_nvcounter(int nid, int crit, int value) +{ + X509_EXTENSION *ex = NULL; + ASN1_INTEGER *counter = NULL; + unsigned char *p = NULL; + int sz = -1; + + /* Encode counter */ + counter = ASN1_INTEGER_new(); + ASN1_INTEGER_set(counter, value); + sz = i2d_ASN1_INTEGER(counter, NULL); + i2d_ASN1_INTEGER(counter, &p); + + /* Create the extension */ + ex = ext_new(nid, crit, p, sz); + + /* Free objects */ + OPENSSL_free(p); + ASN1_INTEGER_free(counter); + + return ex; +} + +/* + * Creates a x509v3 extension containing a public key in DER format: + * + * SubjectPublicKeyInfo ::= SEQUENCE { + * algorithm AlgorithmIdentifier, + * subjectPublicKey BIT STRING } + * + * Parameters: + * pex: OpenSSL extension pointer (output parameter) + * nid: extension identifier + * crit: extension critical (EXT_NON_CRIT, EXT_CRIT) + * k: key + * + * Return: Extension address, NULL if error + */ +X509_EXTENSION *ext_new_key(int nid, int crit, EVP_PKEY *k) +{ + X509_EXTENSION *ex = NULL; + unsigned char *p = NULL; + int sz = -1; + + /* Encode key */ + BIO *mem = BIO_new(BIO_s_mem()); + if (i2d_PUBKEY_bio(mem, k) <= 0) { + ERR_print_errors_fp(stderr); + return NULL; + } + p = (unsigned char *)OPENSSL_malloc(4096); + sz = BIO_read(mem, p, 4096); + + /* Create the extension */ + ex = ext_new(nid, crit, p, sz); + + /* Clean up */ + OPENSSL_free(p); + + return ex; +} + +ext_t *ext_get_by_opt(const char *opt) +{ + ext_t *ext = NULL; + unsigned int i; + + /* Sequential search. This is not a performance concern since the number + * of extensions is bounded and the code runs on a host machine */ + for (i = 0; i < num_extensions; i++) { + ext = &extensions[i]; + if (ext->opt && !strcmp(ext->opt, opt)) { + return ext; + } + } + + return NULL; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/key.c b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/key.c new file mode 100644 index 0000000..a7ee759 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/key.c @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include "cert.h" +#include "cmd_opt.h" +#include "debug.h" +#include "key.h" +#include "platform_oid.h" +#include "sha.h" + +#define MAX_FILENAME_LEN 1024 + +/* + * Create a new key container + */ +static int key_new(key_t *key) +{ + /* Create key pair container */ + key->key = EVP_PKEY_new(); + if (key->key == NULL) { + return 0; + } + + return 1; +} + +static int key_create_rsa(key_t *key) +{ + RSA *rsa = NULL; + + rsa = RSA_generate_key(RSA_KEY_BITS, RSA_F4, NULL, NULL); + if (rsa == NULL) { + printf("Cannot create RSA key\n"); + goto err; + } + if (!EVP_PKEY_assign_RSA(key->key, rsa)) { + printf("Cannot assign RSA key\n"); + goto err; + } + + return 1; +err: + RSA_free(rsa); + return 0; +} + +#ifndef OPENSSL_NO_EC +static int key_create_ecdsa(key_t *key) +{ + EC_KEY *ec = NULL; + + ec = EC_KEY_new_by_curve_name(NID_X9_62_prime256v1); + if (ec == NULL) { + printf("Cannot create EC key\n"); + goto err; + } + if (!EC_KEY_generate_key(ec)) { + printf("Cannot generate EC key\n"); + goto err; + } + EC_KEY_set_flags(ec, EC_PKEY_NO_PARAMETERS); + EC_KEY_set_asn1_flag(ec, OPENSSL_EC_NAMED_CURVE); + if (!EVP_PKEY_assign_EC_KEY(key->key, ec)) { + printf("Cannot assign EC key\n"); + goto err; + } + + return 1; +err: + EC_KEY_free(ec); + return 0; +} +#endif /* OPENSSL_NO_EC */ + +typedef int (*key_create_fn_t)(key_t *key); +static const key_create_fn_t key_create_fn[KEY_ALG_MAX_NUM] = { + key_create_rsa, +#ifndef OPENSSL_NO_EC + key_create_ecdsa, +#endif /* OPENSSL_NO_EC */ +}; + +int key_create(key_t *key, int type) +{ + if (type >= KEY_ALG_MAX_NUM) { + printf("Invalid key type\n"); + return 0; + } + + /* Create OpenSSL key container */ + if (!key_new(key)) { + return 0; + } + + if (key_create_fn[type]) { + return key_create_fn[type](key); + } + + return 0; +} + +int key_load(key_t *key, unsigned int *err_code) +{ + FILE *fp = NULL; + EVP_PKEY *k = NULL; + + /* Create OpenSSL key container */ + if (!key_new(key)) { + *err_code = KEY_ERR_MALLOC; + return 0; + } + + if (key->fn) { + /* Load key from file */ + fp = fopen(key->fn, "r"); + if (fp) { + k = PEM_read_PrivateKey(fp, &key->key, NULL, NULL); + fclose(fp); + if (k) { + *err_code = KEY_ERR_NONE; + return 1; + } else { + ERROR("Cannot load key from %s\n", key->fn); + *err_code = KEY_ERR_LOAD; + } + } else { + WARN("Cannot open file %s\n", key->fn); + *err_code = KEY_ERR_OPEN; + } + } else { + WARN("Key filename not specified\n"); + *err_code = KEY_ERR_FILENAME; + } + + return 0; +} + +int key_store(key_t *key) +{ + FILE *fp = NULL; + + if (key->fn) { + fp = fopen(key->fn, "w"); + if (fp) { + PEM_write_PrivateKey(fp, key->key, + NULL, NULL, 0, NULL, NULL); + fclose(fp); + return 1; + } else { + ERROR("Cannot create file %s\n", key->fn); + } + } else { + ERROR("Key filename not specified\n"); + } + + return 0; +} + +int key_init(void) +{ + cmd_opt_t cmd_opt; + key_t *key; + int rc = 0; + unsigned int i; + + for (i = 0; i < num_keys; i++) { + key = &keys[i]; + if (key->opt != NULL) { + cmd_opt.long_opt.name = key->opt; + cmd_opt.long_opt.has_arg = required_argument; + cmd_opt.long_opt.flag = NULL; + cmd_opt.long_opt.val = CMD_OPT_KEY; + cmd_opt.help_msg = key->help_msg; + cmd_opt_add(&cmd_opt); + } + } + + return rc; +} + +key_t *key_get_by_opt(const char *opt) +{ + key_t *key = NULL; + unsigned int i; + + /* Sequential search. This is not a performance concern since the number + * of keys is bounded and the code runs on a host machine */ + for (i = 0; i < num_keys; i++) { + key = &keys[i]; + if (0 == strcmp(key->opt, opt)) { + return key; + } + } + + return NULL; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/main.c b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/main.c new file mode 100644 index 0000000..c58f41d --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/main.c @@ -0,0 +1,521 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "cert.h" +#include "cmd_opt.h" +#include "debug.h" +#include "ext.h" +#include "key.h" +#include "platform_oid.h" +#include "sha.h" +#include "tbbr/tbb_ext.h" +#include "tbbr/tbb_cert.h" +#include "tbbr/tbb_key.h" + +/* + * Helper macros to simplify the code. This macro assigns the return value of + * the 'fn' function to 'v' and exits if the value is NULL. + */ +#define CHECK_NULL(v, fn) \ + do { \ + v = fn; \ + if (v == NULL) { \ + ERROR("NULL object at %s:%d\n", __FILE__, __LINE__); \ + exit(1); \ + } \ + } while (0) + +/* + * This macro assigns the NID corresponding to 'oid' to 'v' and exits if the + * NID is undefined. + */ +#define CHECK_OID(v, oid) \ + do { \ + v = OBJ_txt2nid(oid); \ + if (v == NID_undef) { \ + ERROR("Cannot find TBB extension %s\n", oid); \ + exit(1); \ + } \ + } while (0) + +#define MAX_FILENAME_LEN 1024 +#define VAL_DAYS 7300 +#define ID_TO_BIT_MASK(id) (1 << id) +#define NUM_ELEM(x) ((sizeof(x)) / (sizeof(x[0]))) +#define HELP_OPT_MAX_LEN 128 + +/* Global options */ +static int key_alg; +static int new_keys; +static int save_keys; +static int print_cert; + +/* Info messages created in the Makefile */ +extern const char build_msg[]; +extern const char platform_msg[]; + + +static char *strdup(const char *str) +{ + int n = strlen(str) + 1; + char *dup = malloc(n); + if (dup) { + strcpy(dup, str); + } + return dup; +} + +static const char *key_algs_str[] = { + [KEY_ALG_RSA] = "rsa", +#ifndef OPENSSL_NO_EC + [KEY_ALG_ECDSA] = "ecdsa" +#endif /* OPENSSL_NO_EC */ +}; + +static void print_help(const char *cmd, const struct option *long_opt) +{ + int rem, i = 0; + const struct option *opt; + char line[HELP_OPT_MAX_LEN]; + char *p; + + assert(cmd != NULL); + assert(long_opt != NULL); + + printf("\n\n"); + printf("The certificate generation tool loads the binary images and\n" + "optionally the RSA keys, and outputs the key and content\n" + "certificates properly signed to implement the chain of trust.\n" + "If keys are provided, they must be in PEM format.\n" + "Certificates are generated in DER format.\n"); + printf("\n"); + printf("Usage:\n"); + printf("\t%s [OPTIONS]\n\n", cmd); + + printf("Available options:\n"); + i = 0; + opt = long_opt; + while (opt->name) { + p = line; + rem = HELP_OPT_MAX_LEN; + if (isalpha(opt->val)) { + /* Short format */ + sprintf(p, "-%c,", (char)opt->val); + p += 3; + rem -= 3; + } + snprintf(p, rem, "--%s %s", opt->name, + (opt->has_arg == required_argument) ? "" : ""); + printf("\t%-32s %s\n", line, cmd_opt_get_help_msg(i)); + opt++; + i++; + } + printf("\n"); + + exit(0); +} + +static int get_key_alg(const char *key_alg_str) +{ + int i; + + for (i = 0 ; i < NUM_ELEM(key_algs_str) ; i++) { + if (0 == strcmp(key_alg_str, key_algs_str[i])) { + return i; + } + } + + return -1; +} + +static void check_cmd_params(void) +{ + cert_t *cert; + ext_t *ext; + key_t *key; + int i, j; + + /* Only save new keys */ + if (save_keys && !new_keys) { + ERROR("Only new keys can be saved to disk\n"); + exit(1); + } + + /* Check that all required options have been specified in the + * command line */ + for (i = 0; i < num_certs; i++) { + cert = &certs[i]; + if (cert->fn == NULL) { + /* Certificate not requested. Skip to the next one */ + continue; + } + + /* Check that all parameters required to create this certificate + * have been specified in the command line */ + for (j = 0; j < cert->num_ext; j++) { + ext = &extensions[cert->ext[j]]; + switch (ext->type) { + case EXT_TYPE_NVCOUNTER: + /* Counter value must be specified */ + if ((!ext->optional) && (ext->arg == NULL)) { + ERROR("Value for '%s' not specified\n", + ext->ln); + exit(1); + } + break; + case EXT_TYPE_PKEY: + /* Key filename must be specified */ + key = &keys[ext->attr.key]; + if (!new_keys && key->fn == NULL) { + ERROR("Key '%s' required by '%s' not " + "specified\n", key->desc, + cert->cn); + exit(1); + } + break; + case EXT_TYPE_HASH: + /* + * Binary image must be specified + * unless it is explicitly made optional. + */ + if ((!ext->optional) && (ext->arg == NULL)) { + ERROR("Image for '%s' not specified\n", + ext->ln); + exit(1); + } + break; + default: + ERROR("Unknown extension type '%d' in '%s'\n", + ext->type, ext->ln); + exit(1); + break; + } + } + } +} + +/* Common command line options */ +static const cmd_opt_t common_cmd_opt[] = { + { + { "help", no_argument, NULL, 'h' }, + "Print this message and exit" + }, + { + { "key-alg", required_argument, NULL, 'a' }, + "Key algorithm: 'rsa' (default), 'ecdsa'" + }, + { + { "save-keys", no_argument, NULL, 'k' }, + "Save key pairs into files. Filenames must be provided" + }, + { + { "new-keys", no_argument, NULL, 'n' }, + "Generate new key pairs if no key files are provided" + }, + { + { "print-cert", no_argument, NULL, 'p' }, + "Print the certificates in the standard output" + } +}; + +int main(int argc, char *argv[]) +{ + STACK_OF(X509_EXTENSION) * sk = NULL; + X509_EXTENSION *cert_ext = NULL; + ext_t *ext = NULL; + key_t *key = NULL; + cert_t *cert = NULL; + FILE *file = NULL; + int i, j, ext_nid, nvctr; + int c, opt_idx = 0; + const struct option *cmd_opt; + const char *cur_opt; + unsigned int err_code; + unsigned char md[SHA256_DIGEST_LENGTH]; + const EVP_MD *md_info; + + NOTICE("CoT Generation Tool: %s\n", build_msg); + NOTICE("Target platform: %s\n", platform_msg); + + /* Set default options */ + key_alg = KEY_ALG_RSA; + + /* Add common command line options */ + for (i = 0; i < NUM_ELEM(common_cmd_opt); i++) { + cmd_opt_add(&common_cmd_opt[i]); + } + + /* Initialize the certificates */ + if (cert_init() != 0) { + ERROR("Cannot initialize certificates\n"); + exit(1); + } + + /* Initialize the keys */ + if (key_init() != 0) { + ERROR("Cannot initialize keys\n"); + exit(1); + } + + /* Initialize the new types and register OIDs for the extensions */ + if (ext_init() != 0) { + ERROR("Cannot initialize TBB extensions\n"); + exit(1); + } + + /* Get the command line options populated during the initialization */ + cmd_opt = cmd_opt_get_array(); + + while (1) { + /* getopt_long stores the option index here. */ + c = getopt_long(argc, argv, "a:hknp", cmd_opt, &opt_idx); + + /* Detect the end of the options. */ + if (c == -1) { + break; + } + + switch (c) { + case 'a': + key_alg = get_key_alg(optarg); + if (key_alg < 0) { + ERROR("Invalid key algorithm '%s'\n", optarg); + exit(1); + } + break; + case 'h': + print_help(argv[0], cmd_opt); + break; + case 'k': + save_keys = 1; + break; + case 'n': + new_keys = 1; + break; + case 'p': + print_cert = 1; + break; + case CMD_OPT_EXT: + cur_opt = cmd_opt_get_name(opt_idx); + ext = ext_get_by_opt(cur_opt); + ext->arg = strdup(optarg); + break; + case CMD_OPT_KEY: + cur_opt = cmd_opt_get_name(opt_idx); + key = key_get_by_opt(cur_opt); + key->fn = strdup(optarg); + break; + case CMD_OPT_CERT: + cur_opt = cmd_opt_get_name(opt_idx); + cert = cert_get_by_opt(cur_opt); + cert->fn = strdup(optarg); + break; + case '?': + default: + print_help(argv[0], cmd_opt); + exit(1); + } + } + + /* Check command line arguments */ + check_cmd_params(); + + /* Indicate SHA256 as image hash algorithm in the certificate + * extension */ + md_info = EVP_sha256(); + + /* Load private keys from files (or generate new ones) */ + for (i = 0 ; i < num_keys ; i++) { + /* First try to load the key from disk */ + if (key_load(&keys[i], &err_code)) { + /* Key loaded successfully */ + continue; + } + + /* Key not loaded. Check the error code */ + if (err_code == KEY_ERR_MALLOC) { + /* Cannot allocate memory. Abort. */ + ERROR("Malloc error while loading '%s'\n", keys[i].fn); + exit(1); + } else if (err_code == KEY_ERR_LOAD) { + /* File exists, but it does not contain a valid private + * key. Abort. */ + ERROR("Error loading '%s'\n", keys[i].fn); + exit(1); + } + + /* File does not exist, could not be opened or no filename was + * given */ + if (new_keys) { + /* Try to create a new key */ + NOTICE("Creating new key for '%s'\n", keys[i].desc); + if (!key_create(&keys[i], key_alg)) { + ERROR("Error creating key '%s'\n", keys[i].desc); + exit(1); + } + } else { + if (err_code == KEY_ERR_OPEN) { + ERROR("Error opening '%s'\n", keys[i].fn); + } else { + ERROR("Key '%s' not specified\n", keys[i].desc); + } + exit(1); + } + } + + /* Create the certificates */ + for (i = 0 ; i < num_certs ; i++) { + + cert = &certs[i]; + + /* Create a new stack of extensions. This stack will be used + * to create the certificate */ + CHECK_NULL(sk, sk_X509_EXTENSION_new_null()); + + for (j = 0 ; j < cert->num_ext ; j++) { + + ext = &extensions[cert->ext[j]]; + + /* Get OpenSSL internal ID for this extension */ + CHECK_OID(ext_nid, ext->oid); + + /* + * Three types of extensions are currently supported: + * - EXT_TYPE_NVCOUNTER + * - EXT_TYPE_HASH + * - EXT_TYPE_PKEY + */ + switch (ext->type) { + case EXT_TYPE_NVCOUNTER: + if (ext->arg) { + nvctr = atoi(ext->arg); + CHECK_NULL(cert_ext, ext_new_nvcounter(ext_nid, + EXT_CRIT, nvctr)); + } + break; + case EXT_TYPE_HASH: + if (ext->arg == NULL) { + if (ext->optional) { + /* Include a hash filled with zeros */ + memset(md, 0x0, SHA256_DIGEST_LENGTH); + } else { + /* Do not include this hash in the certificate */ + break; + } + } else { + /* Calculate the hash of the file */ + if (!sha_file(ext->arg, md)) { + ERROR("Cannot calculate hash of %s\n", + ext->arg); + exit(1); + } + } + CHECK_NULL(cert_ext, ext_new_hash(ext_nid, + EXT_CRIT, md_info, md, + SHA256_DIGEST_LENGTH)); + break; + case EXT_TYPE_PKEY: + CHECK_NULL(cert_ext, ext_new_key(ext_nid, + EXT_CRIT, keys[ext->attr.key].key)); + break; + default: + ERROR("Unknown extension type '%d' in %s\n", + ext->type, cert->cn); + exit(1); + } + + /* Push the extension into the stack */ + sk_X509_EXTENSION_push(sk, cert_ext); + } + + /* Create certificate. Signed with ROT key */ + if (cert->fn && !cert_new(cert, VAL_DAYS, 0, sk)) { + ERROR("Cannot create %s\n", cert->cn); + exit(1); + } + + sk_X509_EXTENSION_free(sk); + } + + + /* Print the certificates */ + if (print_cert) { + for (i = 0 ; i < num_certs ; i++) { + if (!certs[i].x) { + continue; + } + printf("\n\n=====================================\n\n"); + X509_print_fp(stdout, certs[i].x); + } + } + + /* Save created certificates to files */ + for (i = 0 ; i < num_certs ; i++) { + if (certs[i].x && certs[i].fn) { + file = fopen(certs[i].fn, "w"); + if (file != NULL) { + i2d_X509_fp(file, certs[i].x); + fclose(file); + } else { + ERROR("Cannot create file %s\n", certs[i].fn); + } + } + } + + /* Save keys */ + if (save_keys) { + for (i = 0 ; i < num_keys ; i++) { + if (!key_store(&keys[i])) { + ERROR("Cannot save %s\n", keys[i].desc); + } + } + } + +#ifndef OPENSSL_NO_ENGINE + ENGINE_cleanup(); +#endif + CRYPTO_cleanup_all_ex_data(); + + return 0; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/sha.c b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/sha.c new file mode 100644 index 0000000..57026b5 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/sha.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include "debug.h" + +#define BUFFER_SIZE 256 + +int sha_file(const char *filename, unsigned char *md) +{ + FILE *inFile; + SHA256_CTX shaContext; + int bytes; + unsigned char data[BUFFER_SIZE]; + + if ((filename == NULL) || (md == NULL)) { + ERROR("%s(): NULL argument\n", __FUNCTION__); + return 0; + } + + inFile = fopen(filename, "rb"); + if (inFile == NULL) { + ERROR("Cannot read %s\n", filename); + return 0; + } + + SHA256_Init(&shaContext); + while ((bytes = fread(data, 1, BUFFER_SIZE, inFile)) != 0) { + SHA256_Update(&shaContext, data, bytes); + } + SHA256_Final(md, &shaContext); + + fclose(inFile); + return 1; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/tbbr/tbb_cert.c b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/tbbr/tbb_cert.c new file mode 100644 index 0000000..8f7feb5 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/tbbr/tbb_cert.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "tbbr/tbb_cert.h" +#include "tbbr/tbb_ext.h" +#include "tbbr/tbb_key.h" + +/* + * Certificates used in the chain of trust + * + * The order of the certificates must follow the enumeration specified in + * tbb_cert.h. All certificates are self-signed, so the issuer certificate + * field points to itself. + */ +static cert_t tbb_certs[] = { + [TRUSTED_BOOT_FW_CERT] = { + .id = TRUSTED_BOOT_FW_CERT, + .opt = "tb-fw-cert", + .help_msg = "Trusted Boot FW Certificate (output file)", + .fn = NULL, + .cn = "Trusted Boot FW Certificate", + .key = ROT_KEY, + .issuer = TRUSTED_BOOT_FW_CERT, + .ext = { + TRUSTED_FW_NVCOUNTER_EXT, + TRUSTED_BOOT_FW_HASH_EXT + }, + .num_ext = 2 + }, + [TRUSTED_KEY_CERT] = { + .id = TRUSTED_KEY_CERT, + .opt = "trusted-key-cert", + .help_msg = "Trusted Key Certificate (output file)", + .fn = NULL, + .cn = "Trusted Key Certificate", + .key = ROT_KEY, + .issuer = TRUSTED_KEY_CERT, + .ext = { + TRUSTED_FW_NVCOUNTER_EXT, + TRUSTED_WORLD_PK_EXT, + NON_TRUSTED_WORLD_PK_EXT + }, + .num_ext = 3 + }, + [SCP_FW_KEY_CERT] = { + .id = SCP_FW_KEY_CERT, + .opt = "scp-fw-key-cert", + .help_msg = "SCP Firmware Key Certificate (output file)", + .fn = NULL, + .cn = "SCP Firmware Key Certificate", + .key = TRUSTED_WORLD_KEY, + .issuer = SCP_FW_KEY_CERT, + .ext = { + TRUSTED_FW_NVCOUNTER_EXT, + SCP_FW_CONTENT_CERT_PK_EXT + }, + .num_ext = 2 + }, + [SCP_FW_CONTENT_CERT] = { + .id = SCP_FW_CONTENT_CERT, + .opt = "scp-fw-cert", + .help_msg = "SCP Firmware Content Certificate (output file)", + .fn = NULL, + .cn = "SCP Firmware Content Certificate", + .key = SCP_FW_CONTENT_CERT_KEY, + .issuer = SCP_FW_CONTENT_CERT, + .ext = { + TRUSTED_FW_NVCOUNTER_EXT, + SCP_FW_HASH_EXT + }, + .num_ext = 2 + }, + [SOC_FW_KEY_CERT] = { + .id = SOC_FW_KEY_CERT, + .opt = "soc-fw-key-cert", + .help_msg = "SoC Firmware Key Certificate (output file)", + .fn = NULL, + .cn = "SoC Firmware Key Certificate", + .key = TRUSTED_WORLD_KEY, + .issuer = SOC_FW_KEY_CERT, + .ext = { + TRUSTED_FW_NVCOUNTER_EXT, + SOC_FW_CONTENT_CERT_PK_EXT + }, + .num_ext = 2 + }, + [SOC_FW_CONTENT_CERT] = { + .id = SOC_FW_CONTENT_CERT, + .opt = "soc-fw-cert", + .help_msg = "SoC Firmware Content Certificate (output file)", + .fn = NULL, + .cn = "SoC Firmware Content Certificate", + .key = SOC_FW_CONTENT_CERT_KEY, + .issuer = SOC_FW_CONTENT_CERT, + .ext = { + TRUSTED_FW_NVCOUNTER_EXT, + SOC_AP_FW_HASH_EXT + }, + .num_ext = 2 + }, + [TRUSTED_OS_FW_KEY_CERT] = { + .id = TRUSTED_OS_FW_KEY_CERT, + .opt = "tos-fw-key-cert", + .help_msg = "Trusted OS Firmware Key Certificate (output file)", + .fn = NULL, + .cn = "Trusted OS Firmware Key Certificate", + .key = TRUSTED_WORLD_KEY, + .issuer = TRUSTED_OS_FW_KEY_CERT, + .ext = { + TRUSTED_FW_NVCOUNTER_EXT, + TRUSTED_OS_FW_CONTENT_CERT_PK_EXT + }, + .num_ext = 2 + }, + [TRUSTED_OS_FW_CONTENT_CERT] = { + .id = TRUSTED_OS_FW_CONTENT_CERT, + .opt = "tos-fw-cert", + .help_msg = "Trusted OS Firmware Content Certificate (output file)", + .fn = NULL, + .cn = "Trusted OS Firmware Content Certificate", + .key = TRUSTED_OS_FW_CONTENT_CERT_KEY, + .issuer = TRUSTED_OS_FW_CONTENT_CERT, + .ext = { + TRUSTED_FW_NVCOUNTER_EXT, + TRUSTED_OS_FW_HASH_EXT + }, + .num_ext = 2 + }, + [NON_TRUSTED_FW_KEY_CERT] = { + .id = NON_TRUSTED_FW_KEY_CERT, + .opt = "nt-fw-key-cert", + .help_msg = "Non-Trusted Firmware Key Certificate (output file)", + .fn = NULL, + .cn = "Non-Trusted Firmware Key Certificate", + .key = NON_TRUSTED_WORLD_KEY, + .issuer = NON_TRUSTED_FW_KEY_CERT, + .ext = { + NON_TRUSTED_FW_NVCOUNTER_EXT, + NON_TRUSTED_FW_CONTENT_CERT_PK_EXT + }, + .num_ext = 2 + }, + [NON_TRUSTED_FW_CONTENT_CERT] = { + .id = NON_TRUSTED_FW_CONTENT_CERT, + .opt = "nt-fw-cert", + .help_msg = "Non-Trusted Firmware Content Certificate (output file)", + .fn = NULL, + .cn = "Non-Trusted Firmware Content Certificate", + .key = NON_TRUSTED_FW_CONTENT_CERT_KEY, + .issuer = NON_TRUSTED_FW_CONTENT_CERT, + .ext = { + NON_TRUSTED_FW_NVCOUNTER_EXT, + NON_TRUSTED_WORLD_BOOTLOADER_HASH_EXT + }, + .num_ext = 2 + }, + [FWU_CERT] = { + .id = FWU_CERT, + .opt = "fwu-cert", + .help_msg = "Firmware Update Certificate (output file)", + .fn = NULL, + .cn = "Firmware Update Certificate", + .key = ROT_KEY, + .issuer = FWU_CERT, + .ext = { + SCP_FWU_CFG_HASH_EXT, + AP_FWU_CFG_HASH_EXT, + FWU_HASH_EXT + }, + .num_ext = 3 + } +}; + +REGISTER_COT(tbb_certs); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/tbbr/tbb_ext.c b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/tbbr/tbb_ext.c new file mode 100644 index 0000000..5304bd5 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/tbbr/tbb_ext.c @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include "ext.h" +#include "platform_oid.h" +#include "tbbr/tbb_ext.h" +#include "tbbr/tbb_key.h" + +/* TODO: get these values from the command line */ +#define TRUSTED_WORLD_NVCTR_VALUE 0 +#define NORMAL_WORLD_NVCTR_VALUE 0 + +static ext_t tbb_ext[] = { + [TRUSTED_FW_NVCOUNTER_EXT] = { + .oid = TRUSTED_FW_NVCOUNTER_OID, + .opt = "tfw-nvctr", + .help_msg = "Trusted Firmware Non-Volatile counter value", + .sn = "TrustedWorldNVCounter", + .ln = "Trusted World Non-Volatile counter", + .asn1_type = V_ASN1_INTEGER, + .type = EXT_TYPE_NVCOUNTER, + .attr.nvctr_type = NVCTR_TYPE_TFW + }, + [NON_TRUSTED_FW_NVCOUNTER_EXT] = { + .oid = NON_TRUSTED_FW_NVCOUNTER_OID, + .opt = "ntfw-nvctr", + .help_msg = "Non-Trusted Firmware Non-Volatile counter value", + .sn = "NormalWorldNVCounter", + .ln = "Non-Trusted Firmware Non-Volatile counter", + .asn1_type = V_ASN1_INTEGER, + .type = EXT_TYPE_NVCOUNTER, + .attr.nvctr_type = NVCTR_TYPE_NTFW + }, + [TRUSTED_BOOT_FW_HASH_EXT] = { + .oid = TRUSTED_BOOT_FW_HASH_OID, + .opt = "tb-fw", + .help_msg = "Trusted Boot Firmware image file", + .sn = "TrustedBootFirmwareHash", + .ln = "Trusted Boot Firmware hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + }, + [TRUSTED_WORLD_PK_EXT] = { + .oid = TRUSTED_WORLD_PK_OID, + .sn = "TrustedWorldPublicKey", + .ln = "Trusted World Public Key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .attr.key = TRUSTED_WORLD_KEY + }, + [NON_TRUSTED_WORLD_PK_EXT] = { + .oid = NON_TRUSTED_WORLD_PK_OID, + .sn = "NonTrustedWorldPublicKey", + .ln = "Non-Trusted World Public Key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .attr.key = NON_TRUSTED_WORLD_KEY + }, + [SCP_FW_CONTENT_CERT_PK_EXT] = { + .oid = SCP_FW_CONTENT_CERT_PK_OID, + .sn = "SCPFirmwareContentCertPK", + .ln = "SCP Firmware content certificate public key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .attr.key = SCP_FW_CONTENT_CERT_KEY + }, + [SCP_FW_HASH_EXT] = { + .oid = SCP_FW_HASH_OID, + .opt = "scp-fw", + .help_msg = "SCP Firmware image file", + .sn = "SCPFirmwareHash", + .ln = "SCP Firmware hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + }, + [SOC_FW_CONTENT_CERT_PK_EXT] = { + .oid = SOC_FW_CONTENT_CERT_PK_OID, + .sn = "SoCFirmwareContentCertPK", + .ln = "SoC Firmware content certificate public key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .attr.key = SOC_FW_CONTENT_CERT_KEY + }, + [SOC_AP_FW_HASH_EXT] = { + .oid = SOC_AP_FW_HASH_OID, + .opt = "soc-fw", + .help_msg = "SoC AP Firmware image file", + .sn = "SoCAPFirmwareHash", + .ln = "SoC AP Firmware hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + }, + [TRUSTED_OS_FW_CONTENT_CERT_PK_EXT] = { + .oid = TRUSTED_OS_FW_CONTENT_CERT_PK_OID, + .sn = "TrustedOSFirmwareContentCertPK", + .ln = "Trusted OS Firmware content certificate public key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .attr.key = TRUSTED_OS_FW_CONTENT_CERT_KEY + }, + [TRUSTED_OS_FW_HASH_EXT] = { + .oid = TRUSTED_OS_FW_HASH_OID, + .opt = "tos-fw", + .help_msg = "Trusted OS image file", + .sn = "TrustedOSHash", + .ln = "Trusted OS hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + }, + [NON_TRUSTED_FW_CONTENT_CERT_PK_EXT] = { + .oid = NON_TRUSTED_FW_CONTENT_CERT_PK_OID, + .sn = "NonTrustedFirmwareContentCertPK", + .ln = "Non-Trusted Firmware content certificate public key", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_PKEY, + .attr.key = NON_TRUSTED_FW_CONTENT_CERT_KEY + }, + [NON_TRUSTED_WORLD_BOOTLOADER_HASH_EXT] = { + .oid = NON_TRUSTED_WORLD_BOOTLOADER_HASH_OID, + .opt = "nt-fw", + .help_msg = "Non-Trusted World Bootloader image file", + .sn = "NonTrustedWorldBootloaderHash", + .ln = "Non-Trusted World hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH + }, + [SCP_FWU_CFG_HASH_EXT] = { + .oid = SCP_FWU_CFG_HASH_OID, + .opt = "scp-fwu-cfg", + .help_msg = "SCP Firmware Update Config image file", + .sn = "SCPFWUpdateConfig", + .ln = "SCP Firmware Update Config hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + [AP_FWU_CFG_HASH_EXT] = { + .oid = AP_FWU_CFG_HASH_OID, + .opt = "ap-fwu-cfg", + .help_msg = "AP Firmware Update Config image file", + .sn = "APFWUpdateConfig", + .ln = "AP Firmware Update Config hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + [FWU_HASH_EXT] = { + .oid = FWU_HASH_OID, + .opt = "fwu", + .help_msg = "Firmware Updater image file", + .sn = "FWUpdaterHash", + .ln = "Firmware Updater hash (SHA256)", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + } +}; + +REGISTER_EXTENSIONS(tbb_ext); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/tbbr/tbb_key.c b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/tbbr/tbb_key.c new file mode 100644 index 0000000..1d2f789 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/cert_create/src/tbbr/tbb_key.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "tbbr/tbb_key.h" + +/* + * Keys used to establish the chain of trust + * + * The order of the keys must follow the enumeration specified in tbb_key.h + */ +static key_t tbb_keys[] = { + [ROT_KEY] = { + .id = ROT_KEY, + .opt = "rot-key", + .help_msg = "Root Of Trust key (input/output file)", + .desc = "Root Of Trust key" + }, + [TRUSTED_WORLD_KEY] = { + .id = TRUSTED_WORLD_KEY, + .opt = "trusted-world-key", + .help_msg = "Trusted World key (input/output file)", + .desc = "Trusted World key" + }, + [NON_TRUSTED_WORLD_KEY] = { + .id = NON_TRUSTED_WORLD_KEY, + .opt = "non-trusted-world-key", + .help_msg = "Non Trusted World key (input/output file)", + .desc = "Non Trusted World key" + }, + [SCP_FW_CONTENT_CERT_KEY] = { + .id = SCP_FW_CONTENT_CERT_KEY, + .opt = "scp-fw-key", + .help_msg = "SCP Firmware Content Certificate key (input/output file)", + .desc = "SCP Firmware Content Certificate key" + }, + [SOC_FW_CONTENT_CERT_KEY] = { + .id = SOC_FW_CONTENT_CERT_KEY, + .opt = "soc-fw-key", + .help_msg = "SoC Firmware Content Certificate key (input/output file)", + .desc = "SoC Firmware Content Certificate key" + }, + [TRUSTED_OS_FW_CONTENT_CERT_KEY] = { + .id = TRUSTED_OS_FW_CONTENT_CERT_KEY, + .opt = "tos-fw-key", + .help_msg = "Trusted OS Firmware Content Certificate key (input/output file)", + .desc = "Trusted OS Firmware Content Certificate key" + }, + [NON_TRUSTED_FW_CONTENT_CERT_KEY] = { + .id = NON_TRUSTED_FW_CONTENT_CERT_KEY, + .opt = "nt-fw-key", + .help_msg = "Non Trusted Firmware Content Certificate key (input/output file)", + .desc = "Non Trusted Firmware Content Certificate key" + } +}; + +REGISTER_KEYS(tbb_keys); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/makefile b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/makefile new file mode 100644 index 0000000..f73dc30 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/makefile @@ -0,0 +1,125 @@ +# +# Copyright (c) 2015-2016, Renesas Electronics Corporation +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# - Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# - Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# +# - Neither the name of Renesas nor the names of its contributors may be +# used to endorse or promote products derived from this software without +# specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +################################################### +# makefile +################################################### + +#output file name +FILE_NAME_SA0 = bootparam_sa0 +FILE_NAME_SA6 = cert_header_sa6 + +OUTPUT_FILE_SA0 = $(FILE_NAME_SA0).elf +OUTPUT_FILE_SA6 = $(FILE_NAME_SA6).elf + +#object file name +OBJ_FILE_SA0 = sa0.o +OBJ_FILE_SA6 = sa6.o + +#linker script name +MEMORY_DEF_SA0 = sa0.ld.S +MEMORY_DEF_SA6 = sa6.ld.S + +################################################### +# Convenience function for adding build definitions +# $(eval $(call add_define,FOO)) will have: +# -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +# Process RCAR_SA6_TYPE flag +ifndef RCAR_SA6_TYPE +RCAR_SA6_TYPE := 0 +else +ifeq (${RCAR_SA6_TYPE},0) +RCAR_SA6_TYPE := 0 +else +RCAR_SA6_TYPE := 1 +endif +endif +$(eval $(call add_define,RCAR_SA6_TYPE)) + +################################################### + +#c compiler +CC = $(CROSS_COMPILE)gcc +CFLAGS += ${DEFINES} +CFLAGS += -I../../include/lib/stdlib + +#Linker +LD = $(CROSS_COMPILE)ld + +#objcopy +objcopy = $(CROSS_COMPILE)objcopy + +#clean +CL = rm -f + +################################################### +.SUFFIXES : .s .c .o + +################################################### +# command + +.PHONY: all +all: $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA6) +################################################### +# Linker +################################################### +$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0) + $(LD) $(OBJ_FILE_SA0) \ + -T $(MEMORY_DEF_SA0) \ + -o $(OUTPUT_FILE_SA0) \ + -Map $(FILE_NAME_SA0).map \ + + $(objcopy) -O srec --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).srec + $(objcopy) -O binary --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA0) $(FILE_NAME_SA0).bin + +$(OUTPUT_FILE_SA6) : $(MEMORY_DEF_SA6) $(OBJ_FILE_SA6) + $(LD) $(OBJ_FILE_SA6) \ + -T $(MEMORY_DEF_SA6) \ + -o $(OUTPUT_FILE_SA6) \ + -Map $(FILE_NAME_SA6).map \ + + $(objcopy) -O srec --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).srec + $(objcopy) -O binary --adjust-vma=0xE6320000 --srec-forceS3 $(OUTPUT_FILE_SA6) $(FILE_NAME_SA6).bin + +################################################### +# Compile +################################################### + +%.o:../%.c + $(CC) -c -I $< -o $@ + +.PHONY: clean +clean: + $(CL) *.bin *.map *.srec *.elf *.o diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/sa0.c b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/sa0.c new file mode 100644 index 0000000..91e4bee --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/sa0.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +/* SA0 */ +/* 0x00000000 */ +const unsigned int __attribute__ ((section (".sa0_bootrom"))) bootrom_paramA = 0x00000100; +/* 0x00000080 (New Map)*/ +/* 0x000001D4 */ +const unsigned int __attribute__ ((section (".sa0_bl2cert_addr0a"))) bl2cert_addr1a = 0xE6304000; +/* 0x000002E4 */ +const unsigned int __attribute__ ((section (".sa0_bl2cert_size0a"))) bl2cert_size2a = 0x00008000; +/* 0x00000C00 (Old Map)*/ +/* 0x00000D54 */ +const unsigned int __attribute__ ((section (".sa0_bl2cert_addr1a"))) bl2cert_addr = 0xE6304000; +/* 0x00000E64 */ +const unsigned int __attribute__ ((section (".sa0_bl2cert_size1a"))) bl2cert_size = 0x00008000; + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/sa0.ld.S b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/sa0.ld.S new file mode 100644 index 0000000..98c7d05 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/sa0.ld.S @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +SECTIONS +{ + . = 0x00000000; + .rodata : { + KEEP(*(.sa0_bootrom)) + /* A-side IPL content cert "Start Address"(New Map) */ + . = 0x000001D4; /* H'00000080 + H'00000154 */ + KEEP(*(.sa0_bl2cert_addr0a)) + /* A-side IPL content cert "Size"(New Map) */ + . = 0x000002E4; /* H'00000080 + H'00000264 */ + KEEP(*(.sa0_bl2cert_size0a)) + /* A-side IPL content cert "Start Address"(Old Map) */ + . = 0x00000D54; /* H'00000C00 + H'00000154 */ + KEEP(*(.sa0_bl2cert_addr1a)) + /* A-side IPL content cert "Size"(Old Map) */ + . = 0x00000E64; /* H'00000C00 + H'00000264 */ + KEEP(*(.sa0_bl2cert_size1a)) + } + +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/sa6.c b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/sa6.c new file mode 100644 index 0000000..d3b0dfb --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/sa6.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2015-2018, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#define RCAR_SA6_TYPE_HYPERFLASH (0) +#define RCAR_SA6_TYPE_EMMC (1) + +#if (RCAR_SA6_TYPE == RCAR_SA6_TYPE_HYPERFLASH) + +/* Number of content cert for Non-secure Target Program(BL33x) */ +#define RCAR_IMAGE_NUM (0x00000001U) +/* Source address on flash for BL31 */ +#define RCAR_BL31SRC_ADDRESS (0x001C0000U) +/* Reserved */ +#define RCAR_BL31_PARTITION (0x00000000U) +/* Source address on flash for BL32 */ +#define RCAR_BL32SRC_ADDRESS (0x00200000U) +/* Reserved */ +#define RCAR_BL32_PARTITION (0x00000000U) +/* Source address on flash for BL33 */ +#define RCAR_BL33SRC_ADDRESS (0x00840000U) +/* Reserved */ +#define RCAR_BL33_PARTITION (0x00000000U) +#define RCAR_BL332SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define RCAR_BL332_PARTITION (0x00000000U) +#define RCAR_BL333SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define RCAR_BL333_PARTITION (0x00000000U) +#define RCAR_BL334SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define RCAR_BL334_PARTITION (0x00000000U) +#define RCAR_BL335SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define RCAR_BL335_PARTITION (0x00000000U) +#define RCAR_BL336SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define RCAR_BL336_PARTITION (0x00000000U) +#define RCAR_BL337SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define RCAR_BL337_PARTITION (0x00000000U) +#define RCAR_BL338SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define RCAR_BL338_PARTITION (0x00000000U) + +#else /* RCAR_SA6_TYPE == RCAR_SA6_TYPE_HYPERFLASH */ + +/* Number of content cert for Non-secure Target Program(BL33x) */ +#define RCAR_IMAGE_NUM (0x00000001U) +/* Source address on eMMC for BL31 */ +#define RCAR_BL31SRC_ADDRESS (0x00040000U) +/* Source partition on eMMC for BL31 */ +#define RCAR_BL31_PARTITION (0x00000001U) +/* Source address on eMMC for BL32 */ +#define RCAR_BL32SRC_ADDRESS (0x00200000U) +/* Source partition on eMMC for BL32 */ +#define RCAR_BL32_PARTITION (0x00000001U) +/* Source address on eMMC for BL33 */ +#define RCAR_BL33SRC_ADDRESS (0x00000000U) +/* Source partition on eMMC for BL33 */ +#define RCAR_BL33_PARTITION (0x00000002U) +/* Reserved */ +#define RCAR_BL332SRC_ADDRESS (0x00000000U) +#define RCAR_BL332_PARTITION (0x00000000U) +/* Reserved */ +#define RCAR_BL333SRC_ADDRESS (0x00000000U) +#define RCAR_BL333_PARTITION (0x00000000U) +/* Reserved */ +#define RCAR_BL334SRC_ADDRESS (0x00000000U) +#define RCAR_BL334_PARTITION (0x00000000U) +/* Reserved */ +#define RCAR_BL335SRC_ADDRESS (0x00000000U) +#define RCAR_BL335_PARTITION (0x00000000U) +/* Reserved */ +#define RCAR_BL336SRC_ADDRESS (0x00000000U) +#define RCAR_BL336_PARTITION (0x00000000U) +/* Reserved */ +#define RCAR_BL337SRC_ADDRESS (0x00000000U) +#define RCAR_BL337_PARTITION (0x00000000U) +/* Reserved */ +#define RCAR_BL338SRC_ADDRESS (0x00000000U) +#define RCAR_BL338_PARTITION (0x00000000U) + +#endif /* RCAR_SA6_TYPE == RCAR_SA6_TYPE_HYPERFLASH */ + +/* Destination address for BL31 */ +#define RCAR_BL31DST_ADDRESS (0x46400000U) +#define RCAR_BL31DST_ADDRESSH (0x00000000U) +/* Destination size for BL31 */ +#define RCAR_BL31DST_SIZE (0x00004000U) +/* Destination address for BL32 */ +#define RCAR_BL32DST_ADDRESS (0x44100000U) +#define RCAR_BL32DST_ADDRESSH (0x00000000U) +/* Destination size for BL32 */ +#define RCAR_BL32DST_SIZE (0x00020000U) +/* Destination address for BL33 */ +#define RCAR_BL33DST_ADDRESS (0x50000000U) +#define RCAR_BL33DST_ADDRESSH (0x00000000U) +/* Destination size for BL33 */ +#define RCAR_BL33DST_SIZE (0x00040000U) +/* Reserved */ +#define RCAR_BL332DST_ADDRESS (0x00000000U) +#define RCAR_BL332DST_ADDRESSH (0x00000000U) +#define RCAR_BL332DST_SIZE (0x00000000U) +/* Reserved */ +#define RCAR_BL333DST_ADDRESS (0x00000000U) +#define RCAR_BL333DST_ADDRESSH (0x00000000U) +#define RCAR_BL333DST_SIZE (0x00000000U) +/* Reserved */ +#define RCAR_BL334DST_ADDRESS (0x00000000U) +#define RCAR_BL334DST_ADDRESSH (0x00000000U) +#define RCAR_BL334DST_SIZE (0x00000000U) +/* Reserved */ +#define RCAR_BL335DST_ADDRESS (0x00000000U) +#define RCAR_BL335DST_ADDRESSH (0x00000000U) +#define RCAR_BL335DST_SIZE (0x00000000U) +/* Reserved */ +#define RCAR_BL336DST_ADDRESS (0x00000000U) +#define RCAR_BL336DST_ADDRESSH (0x00000000U) +#define RCAR_BL336DST_SIZE (0x00000000U) +/* Reserved */ +#define RCAR_BL337DST_ADDRESS (0x00000000U) +#define RCAR_BL337DST_ADDRESSH (0x00000000U) +#define RCAR_BL337DST_SIZE (0x00000000U) +/* Reserved */ +#define RCAR_BL338DST_ADDRESS (0x00000000U) +#define RCAR_BL338DST_ADDRESSH (0x00000000U) +#define RCAR_BL338DST_SIZE (0x00000000U) + +/* SA6 */ +const uint64_t __attribute__ ((section (".sa6_image_num"))) image_num = RCAR_IMAGE_NUM; +const uint64_t __attribute__ ((section (".sa6_bl31src_addr"))) bl31src_addr = RCAR_BL31SRC_ADDRESS; +const uint64_t __attribute__ ((section (".sa6_bl31partition"))) bl31partition = RCAR_BL31_PARTITION; +const uint64_t __attribute__ ((section (".sa6_bl32src_addr"))) bl32src_addr = RCAR_BL32SRC_ADDRESS; +const uint64_t __attribute__ ((section (".sa6_bl32partition"))) bl32partition = RCAR_BL32_PARTITION; +const uint64_t __attribute__ ((section (".sa6_bl33src_addr"))) bl33src_addr = RCAR_BL33SRC_ADDRESS; +const uint64_t __attribute__ ((section (".sa6_bl33partition"))) bl33partition = RCAR_BL33_PARTITION; +const uint64_t __attribute__ ((section (".sa6_bl332src_addr"))) bl332src_addr = RCAR_BL332SRC_ADDRESS; +const uint64_t __attribute__ ((section (".sa6_bl332partition")))bl332partition = RCAR_BL332_PARTITION; +const uint64_t __attribute__ ((section (".sa6_bl333src_addr"))) bl333src_addr = RCAR_BL333SRC_ADDRESS; +const uint64_t __attribute__ ((section (".sa6_bl333partition")))bl333partition = RCAR_BL333_PARTITION; +const uint64_t __attribute__ ((section (".sa6_bl334src_addr"))) bl334src_addr = RCAR_BL334SRC_ADDRESS; +const uint64_t __attribute__ ((section (".sa6_bl334partition")))bl334partition = RCAR_BL334_PARTITION; +const uint64_t __attribute__ ((section (".sa6_bl335src_addr"))) bl335src_addr = RCAR_BL335SRC_ADDRESS; +const uint64_t __attribute__ ((section (".sa6_bl335partition")))bl335partition = RCAR_BL335_PARTITION; +const uint64_t __attribute__ ((section (".sa6_bl336src_addr"))) bl336src_addr = RCAR_BL336SRC_ADDRESS; +const uint64_t __attribute__ ((section (".sa6_bl336partition")))bl336partition = RCAR_BL336_PARTITION; +const uint64_t __attribute__ ((section (".sa6_bl337src_addr"))) bl337src_addr = RCAR_BL337SRC_ADDRESS; +const uint64_t __attribute__ ((section (".sa6_bl337partition")))bl337partition = RCAR_BL337_PARTITION; +const uint64_t __attribute__ ((section (".sa6_bl338src_addr"))) bl338src_addr = RCAR_BL338SRC_ADDRESS; +const uint64_t __attribute__ ((section (".sa6_bl338partition")))bl338partition = RCAR_BL338_PARTITION; +const uint32_t __attribute__ ((section (".sa6_bl31dst_addr"))) bl31dst_addr = RCAR_BL31DST_ADDRESS; +const uint32_t __attribute__ ((section (".sa6_bl31dst_addrh"))) bl31dst_addrh = RCAR_BL31DST_ADDRESSH; +const uint32_t __attribute__ ((section (".sa6_bl31dst_size"))) bl31dst_size = RCAR_BL31DST_SIZE; +const uint32_t __attribute__ ((section (".sa6_bl32dst_addr"))) bl32dst_addr = RCAR_BL32DST_ADDRESS; +const uint32_t __attribute__ ((section (".sa6_bl32dst_addrh"))) bl32dst_addrh = RCAR_BL32DST_ADDRESSH; +const uint32_t __attribute__ ((section (".sa6_bl32dst_size"))) bl32dst_size = RCAR_BL32DST_SIZE; +const uint32_t __attribute__ ((section (".sa6_bl33dst_addr"))) bl33dst_addr = RCAR_BL33DST_ADDRESS; +const uint32_t __attribute__ ((section (".sa6_bl33dst_addrh"))) bl33dst_addrh = RCAR_BL33DST_ADDRESSH; +const uint32_t __attribute__ ((section (".sa6_bl33dst_size"))) bl33dst_size = RCAR_BL33DST_SIZE; +const uint32_t __attribute__ ((section (".sa6_bl332dst_addr"))) bl332dst_addr = RCAR_BL332DST_ADDRESS; +const uint32_t __attribute__ ((section (".sa6_bl332dst_addrh")))bl332dst_addrh = RCAR_BL332DST_ADDRESSH; +const uint32_t __attribute__ ((section (".sa6_bl332dst_size"))) bl332dst_size = RCAR_BL332DST_SIZE; +const uint32_t __attribute__ ((section (".sa6_bl333dst_addr"))) bl333dst_addr = RCAR_BL333DST_ADDRESS; +const uint32_t __attribute__ ((section (".sa6_bl333dst_addrh")))bl333dst_addrh = RCAR_BL333DST_ADDRESSH; +const uint32_t __attribute__ ((section (".sa6_bl333dst_size"))) bl333dst_size = RCAR_BL333DST_SIZE; +const uint32_t __attribute__ ((section (".sa6_bl334dst_addr"))) bl334dst_addr = RCAR_BL334DST_ADDRESS; +const uint32_t __attribute__ ((section (".sa6_bl334dst_addrh")))bl334dst_addrh = RCAR_BL334DST_ADDRESSH; +const uint32_t __attribute__ ((section (".sa6_bl334dst_size"))) bl334dst_size = RCAR_BL334DST_SIZE; +const uint32_t __attribute__ ((section (".sa6_bl335dst_addr"))) bl335dst_addr = RCAR_BL335DST_ADDRESS; +const uint32_t __attribute__ ((section (".sa6_bl335dst_addrh")))bl335dst_addrh = RCAR_BL335DST_ADDRESSH; +const uint32_t __attribute__ ((section (".sa6_bl335dst_size"))) bl335dst_size = RCAR_BL335DST_SIZE; +const uint32_t __attribute__ ((section (".sa6_bl336dst_addr"))) bl336dst_addr = RCAR_BL336DST_ADDRESS; +const uint32_t __attribute__ ((section (".sa6_bl336dst_addrh")))bl336dst_addrh = RCAR_BL336DST_ADDRESSH; +const uint32_t __attribute__ ((section (".sa6_bl336dst_size"))) bl336dst_size = RCAR_BL336DST_SIZE; +const uint32_t __attribute__ ((section (".sa6_bl337dst_addr"))) bl337dst_addr = RCAR_BL337DST_ADDRESS; +const uint32_t __attribute__ ((section (".sa6_bl337dst_addrh")))bl337dst_addrh = RCAR_BL337DST_ADDRESSH; +const uint32_t __attribute__ ((section (".sa6_bl337dst_size"))) bl337dst_size = RCAR_BL337DST_SIZE; +const uint32_t __attribute__ ((section (".sa6_bl338dst_addr"))) bl338dst_addr = RCAR_BL338DST_ADDRESS; +const uint32_t __attribute__ ((section (".sa6_bl338dst_addrh")))bl338dst_addrh = RCAR_BL338DST_ADDRESSH; +const uint32_t __attribute__ ((section (".sa6_bl338dst_size"))) bl338dst_size = RCAR_BL338DST_SIZE; + diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/sa6.ld.S b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/sa6.ld.S new file mode 100644 index 0000000..04c265a --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/dummy_create/sa6.ld.S @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +SECTIONS +{ + . = 0x00000000; + .rodata : { + KEEP(*(.sa6_image_num)) + . = 0x00000008; + KEEP(*(.sa6_bl31src_addr)) + . = 0x00000010; + KEEP(*(.sa6_bl31partition)) + . = 0x00000018; + KEEP(*(.sa6_bl32src_addr)) + . = 0x00000020; + KEEP(*(.sa6_bl32partition)) + . = 0x00000028; + KEEP(*(.sa6_bl33src_addr)) + . = 0x00000030; + KEEP(*(.sa6_bl33partition)) + . = 0x00000038; + KEEP(*(.sa6_bl332src_addr)) + . = 0x00000040; + KEEP(*(.sa6_bl332partition)) + . = 0x00000048; + KEEP(*(.sa6_bl333src_addr)) + . = 0x00000050; + KEEP(*(.sa6_bl333partition)) + . = 0x00000058; + KEEP(*(.sa6_bl334src_addr)) + . = 0x00000060; + KEEP(*(.sa6_bl334partition)) + . = 0x00000068; + KEEP(*(.sa6_bl335src_addr)) + . = 0x00000070; + KEEP(*(.sa6_bl335partition)) + . = 0x00000078; + KEEP(*(.sa6_bl336src_addr)) + . = 0x00000080; + KEEP(*(.sa6_bl336partition)) + . = 0x00000088; + KEEP(*(.sa6_bl337src_addr)) + . = 0x00000090; + KEEP(*(.sa6_bl337partition)) + . = 0x00000098; + KEEP(*(.sa6_bl338src_addr)) + . = 0x000000A0; + KEEP(*(.sa6_bl338partition)) + . = 0x00000554; + KEEP(*(.sa6_bl31dst_addr)) + . = 0x00000558; + KEEP(*(.sa6_bl31dst_addrh)) + . = 0x00000664; + KEEP(*(.sa6_bl31dst_size)) + . = 0x00000D54; + KEEP(*(.sa6_bl32dst_addr)) + . = 0x00000D58; + KEEP(*(.sa6_bl32dst_addrh)) + . = 0x00000E64; + KEEP(*(.sa6_bl32dst_size)) + . = 0x00001554; + KEEP(*(.sa6_bl33dst_addr)) + . = 0x00001558; + KEEP(*(.sa6_bl33dst_addrh)) + . = 0x00001664; + KEEP(*(.sa6_bl33dst_size)) + . = 0x00001D54; + KEEP(*(.sa6_bl332dst_addr)) + . = 0x00001D58; + KEEP(*(.sa6_bl332dst_addrh)) + . = 0x00001E64; + KEEP(*(.sa6_bl332dst_size)) + . = 0x00002554; + KEEP(*(.sa6_bl333dst_addr)) + . = 0x00002558; + KEEP(*(.sa6_bl333dst_addrh)) + . = 0x00002664; + KEEP(*(.sa6_bl333dst_size)) + . = 0x00002D54; + KEEP(*(.sa6_bl334dst_addr)) + . = 0x00002D58; + KEEP(*(.sa6_bl334dst_addrh)) + . = 0x00002E64; + KEEP(*(.sa6_bl334dst_size)) + . = 0x00003554; + KEEP(*(.sa6_bl335dst_addr)) + . = 0x00003558; + KEEP(*(.sa6_bl335dst_addrh)) + . = 0x00003664; + KEEP(*(.sa6_bl335dst_size)) + . = 0x00003D54; + KEEP(*(.sa6_bl336dst_addr)) + . = 0x00003D58; + KEEP(*(.sa6_bl336dst_addrh)) + . = 0x00003E64; + KEEP(*(.sa6_bl336dst_size)) + . = 0x00004554; + KEEP(*(.sa6_bl337dst_addr)) + . = 0x00004558; + KEEP(*(.sa6_bl337dst_addrh)) + . = 0x00004664; + KEEP(*(.sa6_bl337dst_size)) + . = 0x00004D54; + KEEP(*(.sa6_bl338dst_addr)) + . = 0x00004D58; + KEEP(*(.sa6_bl338dst_addrh)) + . = 0x00004E64; + KEEP(*(.sa6_bl338dst_size)) + } + +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/Makefile b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/Makefile new file mode 100644 index 0000000..df76a75 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/Makefile @@ -0,0 +1,95 @@ +# +# Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +MAKE_HELPERS_DIRECTORY := ../../make_helpers/ +include ${MAKE_HELPERS_DIRECTORY}build_macros.mk +include ${MAKE_HELPERS_DIRECTORY}build_env.mk + +PROJECT := fiptool${BIN_EXT} +OBJECTS := fiptool.o tbbr_config.o +V := 0 +COPIED_H_FILES := uuid.h firmware_image_package.h + +override CPPFLAGS += -D_GNU_SOURCE -D_XOPEN_SOURCE=700 +CFLAGS := -Wall -Werror -pedantic -std=c99 +ifeq (${DEBUG},1) + CFLAGS += -g -O0 -DDEBUG +else + CFLAGS += -O2 +endif +LDLIBS := -lcrypto + +ifeq (${V},0) + Q := @ +else + Q := +endif + +# Only include from local directory (see comment below). +INCLUDE_PATHS := -I. + +CC := gcc + +.PHONY: all clean distclean + +all: ${PROJECT} fip_create + +${PROJECT}: ${OBJECTS} Makefile + @echo " LD $@" + ${Q}${CC} ${OBJECTS} -o $@ ${LDLIBS} + @${ECHO_BLANK_LINE} + @echo "Built $@ successfully" + @${ECHO_BLANK_LINE} + +fip_create: fip_create.sh + ${Q}mkdir -p ../fip_create + ${Q}install -m 755 fip_create.sh ../fip_create/fip_create + +%.o: %.c %.h ${COPIED_H_FILES} Makefile + @echo " CC $<" + ${Q}${CC} -c ${CPPFLAGS} ${CFLAGS} ${INCLUDE_PATHS} $< -o $@ + +# +# Copy required library headers to a local directory so they can be included +# by this project without adding the library directories to the system include +# path. This avoids conflicts with definitions in the compiler standard +# include path. +# +uuid.h : ../../include/lib/stdlib/sys/uuid.h + $(call SHELL_COPY,$<,$@) + +firmware_image_package.h : ../../include/common/firmware_image_package.h + $(call SHELL_COPY,$<,$@) + +clean: + $(call SHELL_DELETE_ALL, ${PROJECT} ${OBJECTS} fip_create) + +distclean: clean + $(call SHELL_DELETE_ALL, ${COPIED_H_FILES}) diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/fip_create.sh b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/fip_create.sh new file mode 100644 index 0000000..207f238 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/fip_create.sh @@ -0,0 +1,148 @@ +#!/bin/sh +# +# Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of ARM nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# This script implements the old fip_create tool on top of +# the new fiptool. + +usage() { + cat << EOF +This tool is used to create a Firmware Image Package. + +Usage: + fip_create [options] FIP_FILENAME + +Options: + -h,--help: Print this help message and exit + -d,--dump: Print contents of FIP after update + -u,--unpack: Unpack images from an existing FIP + -f,--force: Overwrite existing files when unpacking images + +Components that can be added/updated: + --scp-fwu-cfg FILENAME SCP Firmware Updater Configuration FWU SCP_BL2U + --ap-fwu-cfg FILENAME AP Firmware Updater Configuration BL2U + --fwu FILENAME Firmware Updater NS_BL2U + --fwu-cert FILENAME Non-Trusted Firmware Updater certificate + --tb-fw FILENAME Trusted Boot Firmware BL2 + --scp-fw FILENAME SCP Firmware SCP_BL2 + --soc-fw FILENAME EL3 Runtime Firmware BL31 + --tos-fw FILENAME Secure Payload BL32 (Trusted OS) + --nt-fw FILENAME Non-Trusted Firmware BL33 + --rot-cert FILENAME Root Of Trust key certificate + --trusted-key-cert FILENAME Trusted key certificate + --scp-fw-key-cert FILENAME SCP Firmware key certificate + --soc-fw-key-cert FILENAME SoC Firmware key certificate + --tos-fw-key-cert FILENAME Trusted OS Firmware key certificate + --nt-fw-key-cert FILENAME Non-Trusted Firmware key certificate + --tb-fw-cert FILENAME Trusted Boot Firmware BL2 certificate + --scp-fw-cert FILENAME SCP Firmware content certificate + --soc-fw-cert FILENAME SoC Firmware content certificate + --tos-fw-cert FILENAME Trusted OS Firmware content certificate + --nt-fw-cert FILENAME Non-Trusted Firmware content certificate +EOF + exit +} + +echo "!! The fip_create tool is deprecated. Use the new fiptool. !!" +basedir="$(dirname $0)/../fiptool" +fiptool_args= +while :; do + case "$1" in + -h | --help ) + usage + break ;; + -d | --dump ) + fiptool_args="info $fiptool_args" + shift ;; + -u | --unpack ) + fiptool_args="unpack $fiptool_args" + shift ;; + -f | --force ) + fiptool_args="$fiptool_args --force" + shift ;; + --scp-fwu-cfg | \ + --ap-fwu-cfg | \ + --fwu | \ + --fwu-cert | \ + --tb-fw | \ + --scp-fw | \ + --soc-fw | \ + --tos-fw | \ + --nt-fw | \ + --rot-cert | \ + --trusted-key-cert | \ + --scp-fw-key-cert | \ + --soc-fw-key-cert | \ + --tos-fw-key-cert | \ + --nt-fw-key-cert | \ + --tb-fw-cert | \ + --scp-fw-cert | \ + --soc-fw-cert | \ + --tos-fw-cert | \ + --nt-fw-cert ) + fiptool_args="$fiptool_args $1" + shift + if test -z $1; then + usage + fi + fiptool_args="$fiptool_args $1" + shift ;; + * ) + break ;; + esac +done + +# expect a FIP filename +if test -z $1; then + usage +fi + +is_pack_cmd=1 +for arg in $fiptool_args; do + case "$arg" in + unpack ) + is_pack_cmd=0 + break ;; + info ) + is_pack_cmd=0 + break ;; + * ) + esac +done + +# if --unpack and --dump were not specified +# the default action is to pack +if test "$is_pack_cmd" -eq 1; then + fiptool_args="update $fiptool_args" +fi + +# append FIP filename +fiptool_args="$fiptool_args $1" +echo "Invoking fiptool with args: $fiptool_args" +"$basedir/fiptool" $fiptool_args diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/fiptool.c b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/fiptool.c new file mode 100644 index 0000000..b3f02f6 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/fiptool.c @@ -0,0 +1,997 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "fiptool.h" +#include "firmware_image_package.h" +#include "tbbr_config.h" + +#define OPT_TOC_ENTRY 0 +#define OPT_PLAT_TOC_FLAGS 1 + +static int info_cmd(int argc, char *argv[]); +static void info_usage(void); +static int create_cmd(int argc, char *argv[]); +static void create_usage(void); +static int update_cmd(int argc, char *argv[]); +static void update_usage(void); +static int unpack_cmd(int argc, char *argv[]); +static void unpack_usage(void); +static int remove_cmd(int argc, char *argv[]); +static void remove_usage(void); +static int version_cmd(int argc, char *argv[]); +static void version_usage(void); +static int help_cmd(int argc, char *argv[]); +static void usage(void); + +/* Available subcommands. */ +static cmd_t cmds[] = { + { .name = "info", .handler = info_cmd, .usage = info_usage }, + { .name = "create", .handler = create_cmd, .usage = create_usage }, + { .name = "update", .handler = update_cmd, .usage = update_usage }, + { .name = "unpack", .handler = unpack_cmd, .usage = unpack_usage }, + { .name = "remove", .handler = remove_cmd, .usage = remove_usage }, + { .name = "version", .handler = version_cmd, .usage = version_usage }, + { .name = "help", .handler = help_cmd, .usage = NULL }, +}; + +static image_t *images[MAX_IMAGES]; +static size_t nr_images; +static uuid_t uuid_null = { 0 }; +static int verbose; + +static void vlog(int prio, char *msg, va_list ap) +{ + char *prefix[] = { "DEBUG", "WARN", "ERROR" }; + + fprintf(stderr, "%s: ", prefix[prio]); + vfprintf(stderr, msg, ap); + fputc('\n', stderr); +} + +static void log_dbgx(char *msg, ...) +{ + va_list ap; + + va_start(ap, msg); + vlog(LOG_DBG, msg, ap); + va_end(ap); +} + +static void log_warnx(char *msg, ...) +{ + va_list ap; + + va_start(ap, msg); + vlog(LOG_WARN, msg, ap); + va_end(ap); +} + +static void log_err(char *msg, ...) +{ + char buf[512]; + va_list ap; + + va_start(ap, msg); + snprintf(buf, sizeof(buf), "%s: %s", msg, strerror(errno)); + vlog(LOG_ERR, buf, ap); + va_end(ap); + exit(1); +} + +static void log_errx(char *msg, ...) +{ + va_list ap; + + va_start(ap, msg); + vlog(LOG_ERR, msg, ap); + va_end(ap); + exit(1); +} + +static void add_image(image_t *image) +{ + if (nr_images + 1 > MAX_IMAGES) + log_errx("Too many images"); + images[nr_images++] = image; +} + +static void free_image(image_t *image) +{ + free(image->buffer); + free(image); +} + +static void replace_image(image_t *image_dst, image_t *image_src) +{ + int i; + + for (i = 0; i < nr_images; i++) { + if (images[i] == image_dst) { + free_image(images[i]); + images[i] = image_src; + break; + } + } + assert(i != nr_images); +} + +static void remove_image(image_t *image) +{ + int i; + + for (i = 0; i < nr_images; i++) { + if (images[i] == image) { + free_image(images[i]); + images[i] = NULL; + break; + } + } + assert(i != nr_images); + + /* Compact array. */ + memmove(&images[i], &images[i + 1], + (nr_images - i - 1) * sizeof(*images)); + nr_images--; +} + +static void free_images(void) +{ + int i; + + for (i = 0; i < nr_images; i++) { + free_image(images[i]); + images[i] = NULL; + } +} + +static toc_entry_t *get_entry_lookup_from_uuid(const uuid_t *uuid) +{ + toc_entry_t *toc_entry = toc_entries; + + for (; toc_entry->cmdline_name != NULL; toc_entry++) + if (memcmp(&toc_entry->uuid, uuid, sizeof(uuid_t)) == 0) + return toc_entry; + return NULL; +} + +static int parse_fip(char *filename, fip_toc_header_t *toc_header_out) +{ + struct stat st; + FILE *fp; + char *buf, *bufend; + fip_toc_header_t *toc_header; + fip_toc_entry_t *toc_entry; + image_t *image; + int terminated = 0; + + fp = fopen(filename, "r"); + if (fp == NULL) + log_err("fopen %s", filename); + + if (fstat(fileno(fp), &st) == -1) + log_err("fstat %s", filename); + + buf = malloc(st.st_size); + if (buf == NULL) + log_err("malloc"); + + if (fread(buf, 1, st.st_size, fp) != st.st_size) + log_errx("Failed to read %s", filename); + bufend = buf + st.st_size; + fclose(fp); + + if (st.st_size < sizeof(fip_toc_header_t)) + log_errx("FIP %s is truncated", filename); + + toc_header = (fip_toc_header_t *)buf; + toc_entry = (fip_toc_entry_t *)(toc_header + 1); + + if (toc_header->name != TOC_HEADER_NAME) + log_errx("%s is not a FIP file", filename); + + /* Return the ToC header if the caller wants it. */ + if (toc_header_out != NULL) + *toc_header_out = *toc_header; + + /* Walk through each ToC entry in the file. */ + while ((char *)toc_entry + sizeof(*toc_entry) - 1 < bufend) { + /* Found the ToC terminator, we are done. */ + if (memcmp(&toc_entry->uuid, &uuid_null, sizeof(uuid_t)) == 0) { + terminated = 1; + break; + } + + /* + * Build a new image out of the ToC entry and add it to the + * table of images. + */ + image = malloc(sizeof(*image)); + if (image == NULL) + log_err("malloc"); + + memcpy(&image->uuid, &toc_entry->uuid, sizeof(uuid_t)); + + image->buffer = malloc(toc_entry->size); + if (image->buffer == NULL) + log_err("malloc"); + + /* Overflow checks before memory copy. */ + if (toc_entry->size > (uint64_t)-1 - toc_entry->offset_address) + log_errx("FIP %s is corrupted", filename); + if (toc_entry->size + toc_entry->offset_address > st.st_size) + log_errx("FIP %s is corrupted", filename); + + memcpy(image->buffer, buf + toc_entry->offset_address, + toc_entry->size); + image->size = toc_entry->size; + + image->toc_entry = get_entry_lookup_from_uuid(&toc_entry->uuid); + if (image->toc_entry == NULL) { + add_image(image); + toc_entry++; + continue; + } + + assert(image->toc_entry->image == NULL); + /* Link backpointer from lookup entry. */ + image->toc_entry->image = image; + add_image(image); + + toc_entry++; + } + + if (terminated == 0) + log_errx("FIP %s does not have a ToC terminator entry", + filename); + free(buf); + return 0; +} + +static image_t *read_image_from_file(toc_entry_t *toc_entry, char *filename) +{ + struct stat st; + image_t *image; + FILE *fp; + + fp = fopen(filename, "r"); + if (fp == NULL) + log_err("fopen %s", filename); + + if (fstat(fileno(fp), &st) == -1) + log_errx("fstat %s", filename); + + image = malloc(sizeof(*image)); + if (image == NULL) + log_err("malloc"); + + memcpy(&image->uuid, &toc_entry->uuid, sizeof(uuid_t)); + + image->buffer = malloc(st.st_size); + if (image->buffer == NULL) + log_err("malloc"); + if (fread(image->buffer, 1, st.st_size, fp) != st.st_size) + log_errx("Failed to read %s", filename); + image->size = st.st_size; + image->toc_entry = toc_entry; + + fclose(fp); + return image; +} + +static int write_image_to_file(image_t *image, char *filename) +{ + FILE *fp; + + fp = fopen(filename, "w"); + if (fp == NULL) + log_err("fopen"); + if (fwrite(image->buffer, 1, image->size, fp) != image->size) + log_errx("Failed to write %s", filename); + fclose(fp); + return 0; +} + +static int fill_common_opts(struct option *opts, int has_arg) +{ + int i; + + for (i = 0; toc_entries[i].cmdline_name != NULL; i++) { + opts[i].name = toc_entries[i].cmdline_name; + opts[i].has_arg = has_arg; + opts[i].flag = NULL; + opts[i].val = 0; + } + return i; +} + +static void add_opt(struct option *opts, int idx, char *name, + int has_arg, int val) +{ + opts[idx].name = name; + opts[idx].has_arg = has_arg; + opts[idx].flag = NULL; + opts[idx].val = val; +} + +static void md_print(unsigned char *md, size_t len) +{ + size_t i; + + for (i = 0; i < len; i++) + printf("%02x", md[i]); +} + +static int info_cmd(int argc, char *argv[]) +{ + image_t *image; + uint64_t image_offset; + uint64_t image_size = 0; + fip_toc_header_t toc_header; + int i; + + if (argc != 2) + info_usage(); + argc--, argv++; + + parse_fip(argv[0], &toc_header); + + if (verbose) { + log_dbgx("toc_header[name]: 0x%llX", + (unsigned long long)toc_header.name); + log_dbgx("toc_header[serial_number]: 0x%llX", + (unsigned long long)toc_header.serial_number); + log_dbgx("toc_header[flags]: 0x%llX", + (unsigned long long)toc_header.flags); + } + + image_offset = sizeof(fip_toc_header_t) + + (sizeof(fip_toc_entry_t) * (nr_images + 1)); + + for (i = 0; i < nr_images; i++) { + image = images[i]; + if (image->toc_entry != NULL) + printf("%s: ", image->toc_entry->name); + else + printf("Unknown entry: "); + image_size = image->size; + printf("offset=0x%llX, size=0x%llX", + (unsigned long long)image_offset, + (unsigned long long)image_size); + if (image->toc_entry != NULL) + printf(", cmdline=\"--%s\"", + image->toc_entry->cmdline_name); + if (verbose) { + unsigned char md[SHA256_DIGEST_LENGTH]; + + SHA256(image->buffer, image_size, md); + printf(", sha256="); + md_print(md, sizeof(md)); + } + putchar('\n'); + image_offset += image_size; + } + + free_images(); + return 0; +} + +static void info_usage(void) +{ + printf("fiptool info FIP_FILENAME\n"); + exit(1); +} + +static int pack_images(char *filename, uint64_t toc_flags) +{ + FILE *fp; + image_t *image; + fip_toc_header_t *toc_header; + fip_toc_entry_t *toc_entry; + char *buf; + uint64_t entry_offset, buf_size, payload_size; + int i; + + /* Calculate total payload size and allocate scratch buffer. */ + payload_size = 0; + for (i = 0; i < nr_images; i++) + payload_size += images[i]->size; + + buf_size = sizeof(fip_toc_header_t) + + sizeof(fip_toc_entry_t) * (nr_images + 1); + buf = calloc(1, buf_size); + if (buf == NULL) + log_err("calloc"); + + /* Build up header and ToC entries from the image table. */ + toc_header = (fip_toc_header_t *)buf; + toc_header->name = TOC_HEADER_NAME; + toc_header->serial_number = TOC_HEADER_SERIAL_NUMBER; + toc_header->flags = toc_flags; + + toc_entry = (fip_toc_entry_t *)(toc_header + 1); + + entry_offset = buf_size; + for (i = 0; i < nr_images; i++) { + image = images[i]; + memcpy(&toc_entry->uuid, &image->uuid, sizeof(uuid_t)); + toc_entry->offset_address = entry_offset; + toc_entry->size = image->size; + toc_entry->flags = 0; + entry_offset += toc_entry->size; + toc_entry++; + } + + /* Append a null uuid entry to mark the end of ToC entries. */ + memcpy(&toc_entry->uuid, &uuid_null, sizeof(uuid_t)); + toc_entry->offset_address = entry_offset; + toc_entry->size = 0; + toc_entry->flags = 0; + + /* Generate the FIP file. */ + fp = fopen(filename, "w"); + if (fp == NULL) + log_err("fopen %s", filename); + + if (verbose) + log_dbgx("Metadata size: %zu bytes", buf_size); + + if (fwrite(buf, 1, buf_size, fp) != buf_size) + log_errx("Failed to write image to %s", filename); + free(buf); + + if (verbose) + log_dbgx("Payload size: %zu bytes", payload_size); + + for (i = 0; i < nr_images; i++) { + image = images[i]; + if (fwrite(image->buffer, 1, image->size, fp) != image->size) + log_errx("Failed to write image to %s", filename); + } + + fclose(fp); + return 0; +} + +/* + * This function is shared between the create and update subcommands. + * The difference between the two subcommands is that when the FIP file + * is created, the parsing of an existing FIP is skipped. This results + * in update_fip() creating the new FIP file from scratch because the + * internal image table is not populated. + */ +static void update_fip(void) +{ + toc_entry_t *toc_entry; + image_t *image; + + /* Add or replace images in the FIP file. */ + for (toc_entry = toc_entries; + toc_entry->cmdline_name != NULL; + toc_entry++) { + if (toc_entry->action != DO_PACK) + continue; + + image = read_image_from_file(toc_entry, toc_entry->action_arg); + if (toc_entry->image != NULL) { + if (verbose) + log_dbgx("Replacing image %s.bin with %s", + toc_entry->cmdline_name, + toc_entry->action_arg); + replace_image(toc_entry->image, image); + } else { + if (verbose) + log_dbgx("Adding image %s", + toc_entry->action_arg); + add_image(image); + } + /* Link backpointer from lookup entry. */ + toc_entry->image = image; + + free(toc_entry->action_arg); + toc_entry->action_arg = NULL; + } +} + +static void parse_plat_toc_flags(char *arg, unsigned long long *toc_flags) +{ + unsigned long long flags; + char *endptr; + + errno = 0; + flags = strtoull(arg, &endptr, 16); + if (*endptr != '\0' || flags > UINT16_MAX || errno != 0) + log_errx("Invalid platform ToC flags: %s", arg); + /* Platform ToC flags is a 16-bit field occupying bits [32-47]. */ + *toc_flags |= flags << 32; +} + +static int create_cmd(int argc, char *argv[]) +{ + struct option opts[toc_entries_len + 1]; + unsigned long long toc_flags = 0; + int i; + + if (argc < 2) + create_usage(); + + i = fill_common_opts(opts, required_argument); + add_opt(opts, i, "plat-toc-flags", required_argument, + OPT_PLAT_TOC_FLAGS); + add_opt(opts, ++i, NULL, 0, 0); + + while (1) { + int c, opt_index; + + c = getopt_long(argc, argv, "o:", opts, &opt_index); + if (c == -1) + break; + + switch (c) { + case OPT_TOC_ENTRY: { + toc_entry_t *toc_entry; + + toc_entry = &toc_entries[opt_index]; + toc_entry->action = DO_PACK; + toc_entry->action_arg = strdup(optarg); + if (toc_entry->action_arg == NULL) + log_err("strdup"); + break; + } + case OPT_PLAT_TOC_FLAGS: + parse_plat_toc_flags(optarg, &toc_flags); + break; + default: + create_usage(); + } + } + argc -= optind; + argv += optind; + + if (argc == 0) + create_usage(); + + update_fip(); + + pack_images(argv[0], toc_flags); + free_images(); + return 0; +} + +static void create_usage(void) +{ + toc_entry_t *toc_entry = toc_entries; + + printf("fiptool create [--plat-toc-flags ] [opts] FIP_FILENAME\n"); + printf(" --plat-toc-flags \t16-bit platform specific flag field " + "occupying bits 32-47 in 64-bit ToC header.\n"); + fputc('\n', stderr); + printf("Specific images are packed with the following options:\n"); + for (; toc_entry->cmdline_name != NULL; toc_entry++) + printf(" --%-16s FILENAME\t%s\n", toc_entry->cmdline_name, + toc_entry->name); + exit(1); +} + +static int update_cmd(int argc, char *argv[]) +{ + struct option opts[toc_entries_len + 2]; + char outfile[FILENAME_MAX] = { 0 }; + fip_toc_header_t toc_header = { 0 }; + unsigned long long toc_flags = 0; + int pflag = 0; + int i; + + if (argc < 2) + update_usage(); + + i = fill_common_opts(opts, required_argument); + add_opt(opts, i, "out", required_argument, 'o'); + add_opt(opts, ++i, "plat-toc-flags", required_argument, + OPT_PLAT_TOC_FLAGS); + add_opt(opts, ++i, NULL, 0, 0); + + while (1) { + int c, opt_index; + + c = getopt_long(argc, argv, "o:", opts, &opt_index); + if (c == -1) + break; + + switch (c) { + case OPT_TOC_ENTRY: { + toc_entry_t *toc_entry; + + toc_entry = &toc_entries[opt_index]; + toc_entry->action = DO_PACK; + toc_entry->action_arg = strdup(optarg); + if (toc_entry->action_arg == NULL) + log_err("strdup"); + break; + } + case OPT_PLAT_TOC_FLAGS: { + parse_plat_toc_flags(optarg, &toc_flags); + pflag = 1; + break; + } + case 'o': + snprintf(outfile, sizeof(outfile), "%s", optarg); + break; + default: + update_usage(); + } + } + argc -= optind; + argv += optind; + + if (argc == 0) + update_usage(); + + if (outfile[0] == '\0') + snprintf(outfile, sizeof(outfile), "%s", argv[0]); + + if (access(outfile, F_OK) == 0) + parse_fip(argv[0], &toc_header); + + if (pflag) + toc_header.flags &= ~(0xffffULL << 32); + toc_flags = (toc_header.flags |= toc_flags); + + update_fip(); + + pack_images(outfile, toc_flags); + free_images(); + return 0; +} + +static void update_usage(void) +{ + toc_entry_t *toc_entry = toc_entries; + + printf("fiptool update [--out FIP_FILENAME] " + "[--plat-toc-flags ] [opts] FIP_FILENAME\n"); + printf(" --out FIP_FILENAME\t\tSet an alternative output FIP file.\n"); + printf(" --plat-toc-flags \t16-bit platform specific flag field " + "occupying bits 32-47 in 64-bit ToC header.\n"); + fputc('\n', stderr); + printf("Specific images are packed with the following options:\n"); + for (; toc_entry->cmdline_name != NULL; toc_entry++) + printf(" --%-16s FILENAME\t%s\n", toc_entry->cmdline_name, + toc_entry->name); + exit(1); +} + +static int unpack_cmd(int argc, char *argv[]) +{ + struct option opts[toc_entries_len + 3]; + char file[FILENAME_MAX], outdir[PATH_MAX] = { 0 }; + toc_entry_t *toc_entry; + int fflag = 0; + int unpack_all = 1; + int i; + + if (argc < 2) + unpack_usage(); + + i = fill_common_opts(opts, required_argument); + add_opt(opts, i, "force", no_argument, 'f'); + add_opt(opts, ++i, "out", required_argument, 'o'); + add_opt(opts, ++i, NULL, 0, 0); + + while (1) { + int c, opt_index; + + c = getopt_long(argc, argv, "fo:", opts, &opt_index); + if (c == -1) + break; + + switch (c) { + case OPT_TOC_ENTRY: + unpack_all = 0; + toc_entry = &toc_entries[opt_index]; + toc_entry->action = DO_UNPACK; + toc_entry->action_arg = strdup(optarg); + if (toc_entry->action_arg == NULL) + log_err("strdup"); + break; + case 'f': + fflag = 1; + break; + case 'o': + snprintf(outdir, sizeof(outdir), "%s", optarg); + break; + default: + unpack_usage(); + } + } + argc -= optind; + argv += optind; + + if (argc == 0) + unpack_usage(); + + parse_fip(argv[0], NULL); + + if (outdir[0] != '\0') + if (chdir(outdir) == -1) + log_err("chdir %s", outdir); + + /* Mark all images to be unpacked. */ + if (unpack_all) { + for (toc_entry = toc_entries; + toc_entry->cmdline_name != NULL; + toc_entry++) { + if (toc_entry->image != NULL) { + toc_entry->action = DO_UNPACK; + toc_entry->action_arg = NULL; + } + } + } + + /* Unpack all specified images. */ + for (toc_entry = toc_entries; + toc_entry->cmdline_name != NULL; + toc_entry++) { + if (toc_entry->action != DO_UNPACK) + continue; + + /* Build filename. */ + if (toc_entry->action_arg == NULL) + snprintf(file, sizeof(file), "%s.bin", + toc_entry->cmdline_name); + else + snprintf(file, sizeof(file), "%s", + toc_entry->action_arg); + + if (toc_entry->image == NULL) { + log_warnx("Requested image %s is not in %s", + file, argv[0]); + free(toc_entry->action_arg); + toc_entry->action_arg = NULL; + continue; + } + + if (access(file, F_OK) != 0 || fflag) { + if (verbose) + log_dbgx("Unpacking %s", file); + write_image_to_file(toc_entry->image, file); + } else { + log_warnx("File %s already exists, use --force to overwrite it", + file); + } + + free(toc_entry->action_arg); + toc_entry->action_arg = NULL; + } + + free_images(); + return 0; +} + +static void unpack_usage(void) +{ + toc_entry_t *toc_entry = toc_entries; + + printf("fiptool unpack [--force] [--out ] [opts] FIP_FILENAME\n"); + printf(" --force\tIf the output file already exists, use --force to " + "overwrite it.\n"); + printf(" --out path\tSet the output directory path.\n"); + fputc('\n', stderr); + printf("Specific images are unpacked with the following options:\n"); + for (; toc_entry->cmdline_name != NULL; toc_entry++) + printf(" --%-16s FILENAME\t%s\n", toc_entry->cmdline_name, + toc_entry->name); + fputc('\n', stderr); + printf("If no options are provided, all images will be unpacked.\n"); + exit(1); +} + +static int remove_cmd(int argc, char *argv[]) +{ + struct option opts[toc_entries_len + 2]; + char outfile[FILENAME_MAX] = { 0 }; + fip_toc_header_t toc_header; + toc_entry_t *toc_entry; + int fflag = 0; + int i; + + if (argc < 2) + remove_usage(); + + i = fill_common_opts(opts, no_argument); + add_opt(opts, i, "force", no_argument, 'f'); + add_opt(opts, ++i, "out", required_argument, 'o'); + add_opt(opts, ++i, NULL, 0, 0); + + while (1) { + int c, opt_index; + + c = getopt_long(argc, argv, "fo:", opts, &opt_index); + if (c == -1) + break; + + switch (c) { + case OPT_TOC_ENTRY: + toc_entry = &toc_entries[opt_index]; + toc_entry->action = DO_REMOVE; + break; + case 'f': + fflag = 1; + break; + case 'o': + snprintf(outfile, sizeof(outfile), "%s", optarg); + break; + default: + remove_usage(); + } + } + argc -= optind; + argv += optind; + + if (argc == 0) + remove_usage(); + + if (outfile[0] != '\0' && access(outfile, F_OK) == 0 && !fflag) + log_errx("File %s already exists, use --force to overwrite it", + outfile); + + if (outfile[0] == '\0') + snprintf(outfile, sizeof(outfile), "%s", argv[0]); + + parse_fip(argv[0], &toc_header); + + for (toc_entry = toc_entries; + toc_entry->cmdline_name != NULL; + toc_entry++) { + if (toc_entry->action != DO_REMOVE) + continue; + if (toc_entry->image != NULL) { + if (verbose) + log_dbgx("Removing %s.bin", + toc_entry->cmdline_name); + remove_image(toc_entry->image); + } else { + log_warnx("Requested image %s.bin is not in %s", + toc_entry->cmdline_name, argv[0]); + } + } + + pack_images(outfile, toc_header.flags); + free_images(); + return 0; +} + +static void remove_usage(void) +{ + toc_entry_t *toc_entry = toc_entries; + + printf("fiptool remove [--force] [--out FIP_FILENAME] [opts] FIP_FILENAME\n"); + printf(" --force\t\tIf the output FIP file already exists, use --force to " + "overwrite it.\n"); + printf(" --out FIP_FILENAME\tSet an alternative output FIP file.\n"); + fputc('\n', stderr); + printf("Specific images are removed with the following options:\n"); + for (; toc_entry->cmdline_name != NULL; toc_entry++) + printf(" --%-16s\t%s\n", toc_entry->cmdline_name, + toc_entry->name); + exit(1); +} + +static int version_cmd(int argc, char *argv[]) +{ +#ifdef VERSION + puts(VERSION); +#else + /* If built from fiptool directory, VERSION is not set. */ + puts("Unknown version"); +#endif + return 0; +} + +static void version_usage(void) +{ + printf("fiptool version\n"); + exit(1); +} + +static int help_cmd(int argc, char *argv[]) +{ + int i; + + if (argc < 2) + usage(); + argc--, argv++; + + for (i = 0; i < NELEM(cmds); i++) { + if (strcmp(cmds[i].name, argv[0]) == 0 && + cmds[i].usage != NULL) + cmds[i].usage(); + } + if (i == NELEM(cmds)) + printf("No help for subcommand '%s'\n", argv[0]); + return 0; +} + +static void usage(void) +{ + printf("usage: [--verbose] fiptool []\n"); + printf("Global options supported:\n"); + printf(" --verbose\tEnable verbose output for all commands.\n"); + fputc('\n', stderr); + printf("Commands supported:\n"); + printf(" info\t\tList images contained in FIP.\n"); + printf(" create\tCreate a new FIP with the given images.\n"); + printf(" update\tUpdate an existing FIP with the given images.\n"); + printf(" unpack\tUnpack images from FIP.\n"); + printf(" remove\tRemove images from FIP.\n"); + printf(" version\tShow fiptool version.\n"); + printf(" help\t\tShow help for given command.\n"); + exit(1); +} + +int main(int argc, char *argv[]) +{ + int i, ret = 0; + + if (argc < 2) + usage(); + argc--, argv++; + + if (strcmp(argv[0], "-v") == 0 || + strcmp(argv[0], "--verbose") == 0) { + verbose = 1; + argc--, argv++; + } + + for (i = 0; i < NELEM(cmds); i++) { + if (strcmp(cmds[i].name, argv[0]) == 0) { + ret = cmds[i].handler(argc, argv); + break; + } + } + if (i == NELEM(cmds)) + usage(); + return ret; +} diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/fiptool.h b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/fiptool.h new file mode 100644 index 0000000..0fe64c0 --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/fiptool.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FIPTOOL_H__ +#define __FIPTOOL_H__ + +#include +#include + +#include "uuid.h" + +#define NELEM(x) (sizeof (x) / sizeof *(x)) + +/* TODO: Do not hardcode, use realloc() */ +#define MAX_IMAGES 32 + +enum { + DO_PACK = 1, + DO_UNPACK = 2, + DO_REMOVE = 3 +}; + +enum { + LOG_DBG, + LOG_WARN, + LOG_ERR +}; + +typedef struct image { + uuid_t uuid; + size_t size; + void *buffer; + struct toc_entry *toc_entry; +} image_t; + +typedef struct cmd { + char *name; + int (*handler)(int, char **); + void (*usage)(void); +} cmd_t; + +#endif /* __FIPTOOL_H__ */ diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/tbbr_config.c b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/tbbr_config.c new file mode 100644 index 0000000..e8fbbba --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/tbbr_config.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include + +#include "firmware_image_package.h" +#include "tbbr_config.h" + +/* The images used depends on the platform. */ +toc_entry_t toc_entries[] = { + { "SCP Firmware Updater Configuration FWU SCP_BL2U", UUID_TRUSTED_UPDATE_FIRMWARE_SCP_BL2U, + "scp-fwu-cfg", NULL, 0, NULL }, + { "AP Firmware Updater Configuration BL2U", UUID_TRUSTED_UPDATE_FIRMWARE_BL2U, + "ap-fwu-cfg", NULL, 0, NULL }, + { "Firmware Updater NS_BL2U", UUID_TRUSTED_UPDATE_FIRMWARE_NS_BL2U, + "fwu", NULL, 0, NULL }, + { "Non-Trusted Firmware Updater certificate", UUID_TRUSTED_FWU_CERT, + "fwu-cert", NULL, 0, NULL }, + { "Trusted Boot Firmware BL2", UUID_TRUSTED_BOOT_FIRMWARE_BL2, + "tb-fw", NULL, 0, NULL }, + { "SCP Firmware SCP_BL2", UUID_SCP_FIRMWARE_SCP_BL2, + "scp-fw", NULL, 0, NULL }, + { "EL3 Runtime Firmware BL31", UUID_EL3_RUNTIME_FIRMWARE_BL31, + "soc-fw", NULL, 0, NULL }, + { "Secure Payload BL32 (Trusted OS)", UUID_SECURE_PAYLOAD_BL32, + "tos-fw", NULL, 0, NULL }, + { "Non-Trusted Firmware BL33", UUID_NON_TRUSTED_FIRMWARE_BL33, + "nt-fw", NULL, 0, NULL }, + /* Key Certificates */ + { "Root Of Trust key certificate", UUID_ROT_KEY_CERT, + "rot-cert", NULL, 0, NULL }, + { "Trusted key certificate", UUID_TRUSTED_KEY_CERT, + "trusted-key-cert", NULL, 0, NULL }, + { "SCP Firmware key certificate", UUID_SCP_FW_KEY_CERT, + "scp-fw-key-cert", NULL, 0, NULL }, + { "SoC Firmware key certificate", UUID_SOC_FW_KEY_CERT, + "soc-fw-key-cert", NULL, 0, NULL }, + { "Trusted OS Firmware key certificate", UUID_TRUSTED_OS_FW_KEY_CERT, + "tos-fw-key-cert", NULL, 0, NULL }, + { "Non-Trusted Firmware key certificate", UUID_NON_TRUSTED_FW_KEY_CERT, + "nt-fw-key-cert", NULL, 0, NULL }, + /* Content certificates */ + { "Trusted Boot Firmware BL2 certificate", UUID_TRUSTED_BOOT_FW_CERT, + "tb-fw-cert", NULL, 0, NULL }, + { "SCP Firmware content certificate", UUID_SCP_FW_CONTENT_CERT, + "scp-fw-cert", NULL, 0, NULL }, + { "SoC Firmware content certificate", UUID_SOC_FW_CONTENT_CERT, + "soc-fw-cert", NULL, 0, NULL }, + { "Trusted OS Firmware content certificate", UUID_TRUSTED_OS_FW_CONTENT_CERT, + "tos-fw-cert", NULL, 0, NULL }, + { "Non-Trusted Firmware content certificate", UUID_NON_TRUSTED_FW_CONTENT_CERT, + "nt-fw-cert", NULL, 0, NULL }, + { NULL, { 0 }, NULL, NULL, 0, NULL } +}; + +size_t toc_entries_len = sizeof(toc_entries) / sizeof(toc_entries[0]); diff --git a/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/tbbr_config.h b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/tbbr_config.h new file mode 100644 index 0000000..d771a9b --- /dev/null +++ b/IPL/SDK/v3m/src/arm-trusted-firmware/tools/fiptool/tbbr_config.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __TBBR_CONFIG_H__ +#define __TBBR_CONFIG_H__ + +#include + +#include "uuid.h" + +/* TODO: Update this number as required */ +#define TOC_HEADER_SERIAL_NUMBER 0x12345678 + +typedef struct toc_entry { + const char *name; + uuid_t uuid; + const char *cmdline_name; + struct image *image; + int action; + char *action_arg; +} toc_entry_t; + +extern toc_entry_t toc_entries[]; +extern size_t toc_entries_len; + +#endif /* __TBBR_CONFIG_H__ */ diff --git a/IPL/SDK/v4h/src/Dummy_CA76/AArch32_boot/boot_mon.h b/IPL/SDK/v4h/src/Dummy_CA76/AArch32_boot/boot_mon.h new file mode 100644 index 0000000..8f87711 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/AArch32_boot/boot_mon.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +;##### Stack Pointer (Memory Image) ##################### +;## # +;## H'E632F600 System_stack (MiniMon) # +;## H'E632F800 UND_stack # +;## H'E632FA00 SVC(SWI)_stack # +;## H'E632FC00 ABT_stack # +;## H'E632FE00 FIQ_stack # +;## H'E6323000 IRQ_stack # +;## # +;######################################################## + +;#System RAM +.EQU STACK_IRQ_ADR, __STACKS_END__ ;# IRQ mode (unused) +.EQU STACK_FIQ_ADR, __STACKS_END__ ;# FIQ mode (unused) +.EQU STACK_ABT_ADR, __STACKS_END__ ;# ABT mode (unused) +.EQU STACK_SVC_ADR, __STACKS_END__ ;# SVC(SWI) mode (unused) +.EQU STACK_UND_ADR, __STACKS_END__ ;# UND mode(unused) +.EQU STACK_SYS_ADR, __STACKS_END__ ;# SYS mode + + +;#################### CPSR bit ########################## +.EQU PSR_MODE_USER, 0x10 ;#USR mode +.EQU PSR_MODE_FIQ, 0x11 ;#FIQ mode +.EQU PSR_MODE_IRQ, 0x12 ;#IRQ mode +.EQU PSR_MODE_SVC, 0x13 ;#SVC mode +.EQU PSR_MODE_ABT, 0x17 ;#ABT mode +.EQU PSR_MODE_UND, 0x1B ;#UND mode +.EQU PSR_MODE_SYS, 0x1F ;#SYS mode + +;# PRR +.EQU PRR , 0xFFF00044 ;#Product Register + +;#RWDT +;#R-CarH3 77. RCLK Watchdog Timer +.EQU RWDT_RWTCNT , 0xE6020000 ;#RCLK watchdog timer counter +.EQU RWDT_RWTCSRA , 0xE6020004 ;#RCLK watchdog timer control/status register A +.EQU RWDT_RWTCSRB , 0xE6020008 ;#RCLK watchdog timer control/status register B + +;#SystemWDT +;#R-CarH3 78. System Watchdog Timer +.EQU SYSWDT_WTCNT , 0xE6030000 ;#watchdog timer counter +.EQU SYSWDT_WTCSRA , 0xE6030004 ;#watchdog timer control/status register A +.EQU SYSWDT_WTCSRB , 0xE6030008 ;#watchdog timer control/status register B + + diff --git a/IPL/SDK/v4h/src/Dummy_CA76/AArch32_boot/boot_mon.s b/IPL/SDK/v4h/src/Dummy_CA76/AArch32_boot/boot_mon.s new file mode 100644 index 0000000..7f030dd --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/AArch32_boot/boot_mon.s @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + + .INCLUDE "boot_mon.h" + .ALIGN 4 + +;#---CACHE_SET-------------------------------------------------------------------------------------- +.equ CACHE_MODE,ENABLE ;# ENABLE +;#.equ CACHE_MODE,DISABLE ;# DISABLE +;#-------------------------------------------------------------------------------------------------- + + +;#################################################################################################### +;# Vector table +;#################################################################################################### +Vector_Table: + LDR PC,=Reset_Handler + LDR PC,=Undefined_Handler + LDR PC,=SVC_Handler + LDR PC,=Prefetch_Handler + LDR PC,=Abort_Handler + NOP + LDR PC,=IRQ_Handler + LDR PC,=FIQ_Handler + +;#################################################################################################### +;# Exception handler +;#################################################################################################### +Undefined_Handler: + STMFD SP!, {R0-R12,LR} + LDMFD SP!, {R0-R12,PC}^ + +SVC_Handler: + STMFD SP!, {R0-R12,LR} + LDMFD SP!, {R0-R12,PC}^ + +Prefetch_Handler: + SUB R14, R14 , #4 + STMFD SP!, {R0-R12,LR} + LDMFD SP!, {R0-R12,PC}^ + +Abort_Handler: + SUB R14,R14,#8 + STMFD SP!, {R0-R12,LR} + LDMFD SP!, {R0-R12,PC}^ + +IRQ_Handler: + SUB R14, R14 , #4 + STMFD SP!, {R0-R12,LR} + LDMFD SP!, {R0-R12,PC}^ + +FIQ_Handler: + SUB R14,R14,#4 + STMFD SP!, {R0-R7,LR} + LDMFD SP!, {R0-R7,PC}^ + +;#################################################################################################### +;#################################################################################################### +;###### +;###### reset handler +;###### +;#################################################################################################### +;#################################################################################################### +Reset_Handler: +Register_init: + LDR R0, =0 + LDR R1, =0 + LDR R2, =0 + LDR R3, =0 + LDR R4, =0 + LDR R5, =0 + LDR R6, =0 + LDR R7, =0 + LDR R8, =0 + LDR R9, =0 + LDR R10, =0 + LDR R11, =0 + LDR R12, =0 + LDR R13, =0 + LDR R14, =0 +;# LDR R15, =0 + +Set_EnableRAM: + LDR R0, =0xE67F0018 + LDR R1, =0x00000001 ;#Resource Alloc On + STR R1, [R0] + + +Stack_init: +;#-------------------------------------------------------------------------------------------------- +Stack_init_irq: + MRS R1, CPSR + BIC R1, R1, #0x1F + ORR R1, R1, #PSR_MODE_IRQ + MSR CPSR_c, R1 + LDR R0, =STACK_IRQ_ADR + MOV SP, R0 + +;#-------------------------------------------------------------------------------------------------- +Stack_init_frq: + MRS R1, CPSR + BIC R1, R1, #0x1F + ORR R1, R1, #PSR_MODE_FIQ + MSR CPSR_c, R1 + LDR R0, =STACK_FIQ_ADR + MOV SP, R0 + +;#-------------------------------------------------------------------------------------------------- +Stack_init_abt: + MRS R1, CPSR + BIC R1, R1, #0x1F + ORR R1, R1, #PSR_MODE_ABT + MSR CPSR_c, R1 + LDR R0, =STACK_ABT_ADR + MOV SP, R0 + +;#-------------------------------------------------------------------------------------------------- +Stack_init_svc: + MRS R1, CPSR + BIC R1, R1, #0x1F + ORR R1, R1, #PSR_MODE_SVC + MSR CPSR_c, R1 + LDR R0, =STACK_SVC_ADR + MOV SP, R0 + +;#-------------------------------------------------------------------------------------------------- +Stack_init_und: + MRS R1, CPSR + BIC R1, R1, #0x1F + ORR R1, R1, #PSR_MODE_UND + MSR CPSR_c, R1 + LDR R0, =STACK_UND_ADR + MOV SP, R0 + +;#-------------------------------------------------------------------------------------------------- +Stack_init_sys: + MRS R1, CPSR + BIC R1, R1, #0x1F + ORR R1, R1, #PSR_MODE_SYS + MSR CPSR_c, R1 + LDR R0, =STACK_SYS_ADR + MOV SP, R0 + + +;#################################################################################################### +;# +;# board initialize +;# +;#################################################################################################### + +;#################################################################################################### +;#### RWDT,SystemWDT setting (Timer Disable setting) +;#################################################################################################### +.ifdef Area0Boot +Init_set_WDT: + LDR R0, =RWDT_RWTCSRA + LDR R1, =0xA5A5A500 ;#Timer disabled + STR R1, [R0] + +Init_set_SYSWDT: + LDR R0, =SYSWDT_WTCSRA + LDR R1, =0xA5A5A500 ;#Timer disabled (Enable -> disabled) + STR R1, [R0] +.endif + + +.IF CACHE_MODE == ENABLE +;#################################################################################################### +;##### enable I cache +;#################################################################################################### + +CACHE_ENABLE: + MRC p15, 0, R1, c1, c0, 0 ;# Read System Control Register configuration data + ORR R1, R1, #0x1 <<12 ;# instruction cache enable + MCR p15, 0, r0, c7, c5, 0 ;# Invalidate entire instruction cache + MCR p15, 0, R1, c1, c0, 0 ;# enabled instruction cache + ISB + B CACHE_ENABLE_END +.ENDIF + +CACHE_ENABLE_END: + + /* clear bss section */ + mov r0, #0x0 + ldr r1, =__BSS_START__ + ldr r2, =__BSS_SIZE__ +bss_loop: + subs r2, r2, #4 + bcc bss_end + str r0, [r1, +r2] + b bss_loop +bss_end: + +.ifdef Area0Boot + /* copy data section */ + ldr r0, =__DATA_COPY_START__ + ldr r1, =__DATA_START__ + ldr r2, =__DATA_SIZE__ +data_loop: + subs r2, r2, #4 + bcc data_end + ldr r3, [r0, +r2] + str r3, [r1, +r2] + b data_loop +data_end: +.endif + + BL InitScif + +;#################################################################################################### +;#### go to main +;#################################################################################################### +Jmp_MAIN_C: + BL Main + + .END diff --git a/IPL/SDK/v4h/src/Dummy_CA76/AArch32_boot/stack.s b/IPL/SDK/v4h/src/Dummy_CA76/AArch32_boot/stack.s new file mode 100644 index 0000000..a450de9 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/AArch32_boot/stack.s @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + + + .section writer_stack, "aw", %nobits + .align 5 +stacks: + .space (8*1024), 0 + + .end diff --git a/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/boot_mon.h b/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/boot_mon.h new file mode 100644 index 0000000..0d727bd --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/boot_mon.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2018-2025 Renesas Electronics Corporation. All rights reserved. + */ + +;#RWDT +;#R-CarH3 77. RCLK Watchdog Timer +.EQU RWDT_RWTCNT , 0xE6020000 ;#RCLK watchdog timer counter +#if ACC_PROT_ENABLE == 0 +.EQU RWDT_RWTCSRA , 0xE6020004 ;#RCLK watchdog timer control/status register A +#else +.EQU RWDT_RWTCSRA , 0x20E6020004 ;#RCLK watchdog timer control/status register A + ;#Change to RGID2 when ACC_PROT_ENABLE == 1 +#endif +.EQU RWDT_RWTCSRB , 0xE6020008 ;#RCLK watchdog timer control/status register B + +;#SystemWDT +;#R-CarH3 78. System Watchdog Timer +.EQU SYSWDT_WTCNT , 0xE6030000 ;#watchdog timer counter +#if ACC_PROT_ENABLE == 0 +.EQU SYSWDT_WTCSRA , 0xE6030004 ;#watchdog timer control/status register A +#else +.EQU SYSWDT_WTCSRA , 0x20E6030004 ;#watchdog timer control/status register A + ;#Change to RGID2 when ACC_PROT_ENABLE == 1 +#endif +.EQU SYSWDT_WTCSRB , 0xE6030008 ;#watchdog timer control/status register B + +.EQU PRR , 0xFFF00044 ;#Product Register + +.macro STARTFUNC name + .global \name + .func \name + \name: +.endm + +.macro ENDFUNC name + .type \name, %function + .endfunc +.endm + diff --git a/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/boot_mon.s b/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/boot_mon.s new file mode 100644 index 0000000..bb2931e --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/boot_mon.s @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2018-2025 Renesas Electronics Corporation. All rights reserved. + */ + +;# W0-W30 : 32bit Register (W30=Link Register) +;# X0-X30 : 64bit Register (X30=Link Register) +;# WZR : 32bit Zero Register +;# XZR : 64bit Zero Register +;# WSP : 32bit Stack Pointer +;# SP : 64bit Stack Pointer + + .INCLUDE "boot_mon.h" + .ALIGN 4 + +;# Initialize registers +Register_init: + LDR X0, =0 + LDR X1, =0 + LDR X2, =0 + LDR X3, =0 + LDR X4, =0 + LDR X5, =0 + LDR X6, =0 + LDR X7, =0 + LDR X8, =0 + LDR X9, =0 + LDR X10, =0 + LDR X11, =0 + LDR X12, =0 + LDR X13, =0 + LDR X14, =0 + LDR X15, =0 + LDR X16, =0 + LDR X17, =0 + LDR X18, =0 + LDR X19, =0 + LDR X20, =0 + LDR X21, =0 + LDR X22, =0 + LDR X23, =0 + LDR X24, =0 + LDR X25, =0 + LDR X26, =0 + LDR X27, =0 + LDR X28, =0 + LDR X29, =0 + LDR X30, =0 + +Set_EnableRAM: +;# LDR X0, =0xE67F0018 +;# LDR W1, =0x00000001 ;#Enable DRAM/SECRAM/PUBRAM +;# STR W1, [X0] + + MRS X0, CurrentEL + CMP X0, #0x0000000C + BEQ current_EL3 + + +current_EL1: +;# Loader + LDR x0, =__STACKS_END__ +;# MSR SP_EL0,x0 +;# MSR SP_EL1,x0 +;# MSR SP_EL2,x0 + MOV sp,x0 + MOV x0, #0x50000000 +.if ACC_PROT_ENABLE == 1 + MOVK x0, #0x0020, LSL #32 ;#mov address #0x2050000000 +.endif + MSR ELR_EL1,x0 +;# MSR ELR_EL2,x0 +;# MSR ELR_EL3,x0 + MOV x0, #0x03C5 + MSR SPSR_EL1,x0 +;# MSR SPSR_EL2,x0 +;# MSR SPSR_EL3,x0 + +;# Enable cache +;# mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el1 + orr x0, x0, #(0x1 << 12) + orr x0, x0, #(0x1 << 1) + orr x0, x0, #(0x1 << 3) + msr sctlr_el1, x0 + isb + b bss_clr + +current_EL3: +;# Loader + LDR x0, =__STACKS_END__ +;# MSR SP_EL0,x0 +;# MSR SP_EL1,x0 +;# MSR SP_EL2,x0 + MOV sp,x0 +.if OPTEE_LOAD_ENABLE == 0 + MOV x0, #0xE38 + MSR SCR_EL3, x0 + MOV x0, #0x50000000 +.if ACC_PROT_ENABLE == 1 + MOVK x0, #0x0020, LSL #32 ;#mov address #0x2050000000 +.endif +;# MSR ELR_EL1,x0 +;# MSR ELR_EL2,x0 + MSR ELR_EL3,x0 + MOV x0, #0x03C5 +;# MSR SPSR_EL1,x0 +;# MSR SPSR_EL2,x0 + MSR SPSR_EL3,x0 +.else + MOV x0, #0xE38 + MSR SCR_EL3, x0 + MOV x0, #0x44100000 +.if ACC_PROT_ENABLE == 1 + MOVK x0, #0x0020, LSL #32 ;#mov address #0x2044100000 +.endif + MSR ELR_EL3,x0 + MOV x0, #0x03C5 + MSR SPSR_EL3,x0 +.endif + +;# Board Initialize +.ifdef Area0Boot + +Init_set_WDT: + LDR W0, =RWDT_RWTCSRA + LDR W1, =0xA5A5A500 ;#Timer disabled + STR W1, [X0] + +Init_set_SYSWDT: + LDR W0, =SYSWDT_WTCSRA + LDR W1, =0xA5A5A500 ;#Timer disabled (Enable -> disabled) + STR W1, [X0] + +.endif + + + +;# Enable cache +;# mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el3 + orr x0, x0, #(0x1 << 12) + orr x0, x0, #(0x1 << 1) + orr x0, x0, #(0x1 << 3) + msr sctlr_el3, x0 + isb + + + /* clear bss section */ +bss_clr: + mov X0, #0x0 + ldr X1, =__BSS_START__ + ldr X2, =__BSS_SIZE__ +bss_loop: + subs X2, X2, #4 + bcc bss_end + str W0, [X1, X2] + b bss_loop +bss_end: + +.ifdef Area0Boot + /* copy data section */ + ldr X0, =__DATA_COPY_START__ + ldr X1, =__DATA_START__ + ldr X2, =__DATA_SIZE__ +data_loop: + subs X2, X2, #4 + bcc data_end + ldr W3, [X0, X2] + str W3, [X1, X2] + b data_loop +.endif + +data_end: + +;# BL InitScif + + BL Main + eret + + .END + diff --git a/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/d_armasm.h b/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/d_armasm.h new file mode 100644 index 0000000..e0b9461 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/d_armasm.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2021 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef D_ARMASM_H +#define D_ARMASM_H + +void DCacheEnable(); +void WriteTCR_EL3(uint64_t data); +void WriteMAIR_EL3(uint64_t data); +void WriteTTBR0_EL3(uint64_t data); + +#endif /* D_ARMASM_H */ + diff --git a/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/d_armasm.s b/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/d_armasm.s new file mode 100644 index 0000000..a6e51e8 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/d_armasm.s @@ -0,0 +1,288 @@ +/**********************************************************/ +/* Sample program : Debug ARM Assembly Program */ +/* File Name : d_armasm.s */ +/* Copyright (C) Renesas Electronics Corp. 2015. */ +/**********************************************************/ + + .INCLUDE "boot_mon.h" + .ALIGN 4 + + +;# uint32_t MonCp15Mpidr(void); +STARTFUNC MonCp15Mpidr + MRS X0, VMPIDR_EL2 ;# read Multiprocessor ID register + RET +ENDFUNC MonCp15Mpidr + + +;# uint32_t MonCp15Midr(void); +STARTFUNC MonCp15Midr + MRS X0, VPIDR_EL2 ;# read Processor ID Register + RET +ENDFUNC MonCp15Midr + + +;# void WriteTCR_EL3( uint64_t data ); +;# data[63:39]=RES0 +;# data[38][37][36][35][34:32]=TBI1,TBI0,AS,RES0,IPS +;# data[31:30][29:28][27:26][25:24][23][22][21:16]=TG1,SH1,ORGN1,IRGN1,EPD1,A1 ,T1SZ +;# data[15:14][13:12][11:10][09:08][07][06][05:00]=TG0,SH0,ORGN0,IRGN0,EPD0,RES0,T0SZ +STARTFUNC WriteTCR_EL3 + MSR TCR_EL3, X0 + RET +ENDFUNC WriteTCR_EL3 + + +;# void WriteMAIR_EL3( uint64_t data ); +;# data[63:56][55:48][47:40][39:32]=Attr7,Attr6,Attr5,Attr4 +;# data[31:24][23:16][15: 8][ 7: 0]=Attr3,Attr2,Attr1,Attr0 +STARTFUNC WriteMAIR_EL3 + MSR MAIR_EL3, X0 + RET +ENDFUNC WriteMAIR_EL3 + + +;# void WriteTTBR0_EL3( uint64_t data ); +;# data[63:48]=ASID +;# data[47: 0]=BADDR +STARTFUNC WriteTTBR0_EL3 + MSR TTBR0_EL3, X0 + RET +ENDFUNC WriteTTBR0_EL3 + + +;# void CleaningAndInvalidateICache(void); +STARTFUNC CleaningAndInvalidateICache + IC IALLUIS + ISB SY + RET +ENDFUNC CleaningAndInvalidateICache + + +;# Refer: DEN0024A_v8_architecture_PG.pdf +;# void CleaningDCache(void); +STARTFUNC CleaningDCache + MRS X0, CLIDR_EL1 + AND W3, W0, #0x07000000 // Get 2 x Level of Coherence + LSR W3, W3, #23 + CBZ W3, DC_Finished + MOV W10, #0 // W10 = 2 x cache level + MOV W8, #1 // W8 = constant 0b1 +DC_Loop1: + ADD W2, W10, W10, LSR #1 // Calculate 3 x cache level + LSR W1, W0, W2 // extract 3-bit cache type for this level + AND W1, W1, #0x7 + CMP W1, #2 + B.LT DC_Skip // No data or unified cache at this level + MSR CSSELR_EL1, X10 // Select this cache level + ISB // Synchronize change of CSSELR + MRS X1, CCSIDR_EL1 // Read CCSIDR + AND W2, W1, #7 // W2 = log2(linelen)-4 + ADD W2, W2, #4 // W2 = log2(linelen) + UBFX W4, W1, #3, #10 // W4 = max way number, right aligned + CLZ W5, W4 // W5 = 32-log2(ways), bit position of way in DC operand + LSL W9, W4, W5 // W9 = max way number, aligned to position in DC operand + LSL W16, W8, W5 // W16 = amount to decrement way number per iteration +DC_Loop2: + UBFX W7, W1, #13, #15 // W7 = max set number, right aligned + LSL W7, W7, W2 // W7 = max set number, aligned to position in DC operand + LSL W17, W8, W2 // W17 = amount to decrement set number per iteration +DC_Loop3: + ORR W11, W10, W9 // W11 = combine way number and cache number... + ORR W11, W11, W7 // ... and set number for DC operand + DC CSW, X11 // Do data cache clean by set and way + SUBS W7, W7, W17 // Decrement set number + B.GE DC_Loop3 + SUBS X9, X9, X16 // Decrement way number + B.GE DC_Loop2 +DC_Skip: + ADD W10, W10, #2 // Increment 2 x cache level + CMP W3, W10 + DSB SY // Ensure completion of previous cache maintenance operation + B.GT DC_Loop1 +DC_Finished: + DSB SY ;# Add DSB + ISB ;# Add ISB + RET +ENDFUNC CleaningDCache + + +;# Refer: DEN0024A_v8_architecture_PG.pdf +;# uint32_t CleaningAndInvalidateDCache(void); +STARTFUNC CleaningAndInvalidateDCache + MRS X0, CLIDR_EL1 + AND W3, W0, #0x07000000 // Get 2 x Level of Coherence + LSR W3, W3, #23 + CBZ W3, DCI_Finished + MOV W10, #0 // W10 = 2 x cache level + MOV W8, #1 // W8 = constant 0b1 +DCI_Loop1: + ADD W2, W10, W10, LSR #1 // Calculate 3 x cache level + LSR W1, W0, W2 // extract 3-bit cache type for this level + AND W1, W1, #0x7 + CMP W1, #2 + B.LT DCI_Skip // No data or unified cache at this level + MSR CSSELR_EL1, X10 // Select this cache level + ISB // Synchronize change of CSSELR + MRS X1, CCSIDR_EL1 // Read CCSIDR + AND W2, W1, #7 // W2 = log2(linelen)-4 + ADD W2, W2, #4 // W2 = log2(linelen) + UBFX W4, W1, #3, #10 // W4 = max way number, right aligned + CLZ W5, W4 // W5 = 32-log2(ways), bit position of way in DC operand + LSL W9, W4, W5 // W9 = max way number, aligned to position in DC operand + LSL W16, W8, W5 // W16 = amount to decrement way number per iteration +DCI_Loop2: + UBFX W7, W1, #13, #15 // W7 = max set number, right aligned + LSL W7, W7, W2 // W7 = max set number, aligned to position in DC operand + LSL W17, W8, W2 // W17 = amount to decrement set number per iteration +DCI_Loop3: + ORR W11, W10, W9 // W11 = combine way number and cache number... + ORR W11, W11, W7 // ... and set number for DC operand + DC CISW, X11 // Do data cache clean and invalidate by set and way + SUBS W7, W7, W17 // Decrement set number + B.GE DCI_Loop3 + SUBS X9, X9, X16 // Decrement way number + B.GE DCI_Loop2 +DCI_Skip: + ADD W10, W10, #2 // Increment 2 x cache level + CMP W3, W10 + DSB SY // Ensure completion of previous cache maintenance operation + B.GT DCI_Loop1 +DCI_Finished: + DSB SY ;# Add DSB + ISB ;# Add ISB + RET +ENDFUNC CleaningAndInvalidateDCache + + +;# void DCacheEnable(void); +STARTFUNC DCacheEnable + MOV X20, X30 ;# Save LR data to X20 + + BL SetVmsaTable ;# MMU Table setting + + ISB ;# The ISB forces these changes to be seen before the MMU is enabled. + MRS X0, SCTLR_EL3 ;# Read System Control Register configuration data + ORR X0, X0, #1 ;# Set [M] bit and enable the MMU. + ORR X0, X0, #4 ;# Set [C] bit and enable the Data Cache. + DSB SY + MSR SCTLR_EL3, X0 ;# Write System Control Register configuration data + ISB ;# The ISB forces these changes to be seen by the next instruction + + MOV X30, X20 ;# Load LR data from X20 + RET +ENDFUNC DCacheEnable + + +;# void DCacheDisable(void); +STARTFUNC DCacheDisable + MOV X20, X30 ;# Save LR data to X20 + + DSB SY + ISB ;# + MRS X0, SCTLR_EL3 ;# +;# ORR X0, X0, #1 ;# Set [M] bit and enable the MMU. +;# ORR X0, X0, #4 ;# Set [C] bit and enable the Data Cache. + bic X0, X0, #1 ;# Set [M] bit and disable the MMU. + bic X0, X0, #4 ;# Set [C] bit and disable the Data Cache. + DSB SY + MSR SCTLR_EL3, X0 ;# + DSB SY + ISB ;# + + BL CleaningDCache + BL CleaningAndInvalidateDCache + DSB SY + ISB ;# + + MOV X30, X20 ;# Load LR data from X20 + RET +ENDFUNC DCacheDisable + + +STARTFUNC InterruptDisableDAIF + MRS X0, DAIF ;# Read DAIF + LDR W2, =0xC0 ;# bit[7]:IRQ mask bit, bit[6]:FIQ mask bit + ORR X0,X0,X2 ;# => 0:Exception not masked, 1: Exception masked + MSR DAIF, X0 ;# Write DAIF + RET +ENDFUNC InterruptDisableDAIF + + +STARTFUNC ReadSCR_EL3 + MRS X0, SCR_EL3 ;# Read SCR_EL3 + RET +ENDFUNC ReadSCR_EL3 + + +STARTFUNC InterruptDisableSCR_EL3 + MRS X0, SCR_EL3 ;# Read SCR_EL3 + LDR W2, =0x6 ;# bit[2]:Physical FIQ Routing, bit[1]:Physical IRQ Routing + BIC X0,X0,X2 ;# => 0:Interrupt not taken, 1: Interrupt are taken + MSR SCR_EL3, X0 ;# Write SCR_EL3 + RET +ENDFUNC InterruptDisableSCR_EL3 + + +STARTFUNC DropToEl1 + MRS X0, HCR_EL2 ;# Read HCR_EL2 + LDR W2, =0x80000000 ;# bit[31]:EL1 is AArch64 + ORR X0,X0,X2 ;# => 0:Lower levels are all AArch32 1:EL1 is AArch64 + MSR HCR_EL2, X0 ;# Write HCR_EL2 + + MRS X0, SCR_EL3 ;# Read SCR_EL3 + LDR W2, =0x400 ;# bit[10]:EL1 is AArch64 + ORR X0,X0,X2 ;# => 0:Lower levels are all AArch32 1:EL2/1 are AArch64 + MSR SCR_EL3, X0 ;# Write SCR_EL3 + + LDR W0, =0x3C5 ;# bit[3:0]:EL1h + MSR SPSR_EL3, X0 ;# Write SPSR_EL3 + + MOV X0, SP + MSR SP_EL1,X0 + MOV X0, X30 + MSR ELR_EL3,X0 + ERET +ENDFUNC DropToEl1 + +STARTFUNC UpToEl3 + LDR W0, =0x3CD ;# bit[3:0]:EL3h + MSR SPSR_EL3, X0 ;# Write SPSR_EL3 + + MRS X0, SP_EL1 ;# Read SP_EL1 + MOV SP, X0 +;# MOV X0, X30 +;# MRS X0, ELR_EL1 ;# Read ELR_EL1 +;# MSR ELR_EL3,X0 + RET +ENDFUNC UpToEl3 + + +STARTFUNC ChangeNonSecure + MRS X0, SCR_EL3 ;# Read SCR_EL3 + LDR W2, =0x1 ;# bit[0]:Non-secure bit +;# LDR W2, =0x481 ;# bit[0]:Non-secure bit + ORR X0,X0,X2 ;# => 0:Secure, 1:Non-secure + MSR SCR_EL3, X0 ;# Write SCR_EL3 + RET +ENDFUNC ChangeNonSecure + + +STARTFUNC ChangeSecure + MRS X0, SCR_EL3 ;# Read SCR_EL3 + LDR W2, =0x0 ;# bit[0]:Non-secure bit + ORR X0,X0,X2 ;# => 0:Secure, 1:Non-secure + MSR SCR_EL3, X0 ;# Write SCR_EL3 + RET +ENDFUNC ChangeSecure + + +;# void SoftDelayAsm(uint32_t count); ƒLƒƒƒbƒVƒ…ON‚Ìê‡A2clock‚Å1Žü‰Â”\ (AArch64) +STARTFUNC SoftDelayAsm ;# ˆø”‚ð‚»‚Ì‚Ü‚ÜŒ¸ŽZ‚ÉŽg—p‚·‚é + SUBS W0, W0, #1 ;# ƒtƒ‰ƒO‚ðXV‚µ‚‚Œ¸ŽZ 1step + BNE SoftDelayAsm ;# R0==0‚É‚È‚é‚܂Ń‹[ƒv 1step + RET ;# ŒÄ‚Ño‚µŒ³‚É–ß‚é +ENDFUNC SoftDelayAsm + + + .END diff --git a/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/stack.s b/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/stack.s new file mode 100644 index 0000000..a450de9 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/AArch64_boot/stack.s @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + + + .section writer_stack, "aw", %nobits + .align 5 +stacks: + .space (8*1024), 0 + + .end diff --git a/IPL/SDK/v4h/src/Dummy_CA76/LICENSE.md b/IPL/SDK/v4h/src/Dummy_CA76/LICENSE.md new file mode 100644 index 0000000..af0ee77 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/LICENSE.md @@ -0,0 +1 @@ +Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. diff --git a/IPL/SDK/v4h/src/Dummy_CA76/cert_param.c b/IPL/SDK/v4h/src/Dummy_CA76/cert_param.c new file mode 100644 index 0000000..80bdfb9 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/cert_param.c @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +/* 0xE6300400 */ +const unsigned int __attribute__ ((section (".boot_param"))) boot_param = 0x00000000; +/* 0xE630048C */ +const unsigned int __attribute__ ((section (".cert_offset"))) reserved = 0x00000000; +/* 0xE63005D4 */ +const unsigned int __attribute__ ((section (".cert_addr"))) cert_addr = 0xE6304000; +/* 0xE63006E4 */ +const unsigned int __attribute__ ((section (".cert_size"))) cert_size = 0x00001000; +/* 0xE6301154 */ +const unsigned int __attribute__ ((section (".cert_addr2"))) cert_addr2 = 0xE6304000; +/* 0xE6301264 */ +const unsigned int __attribute__ ((section (".cert_size2"))) cert_size2 = 0x00001000; diff --git a/IPL/SDK/v4h/src/Dummy_CA76/common.c b/IPL/SDK/v4h/src/Dummy_CA76/common.c new file mode 100644 index 0000000..5459bb3 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/common.c @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#include "types.h" +#include "common.h" +#include "devdrv.h" + +__attribute__((aligned(32))) uint8_t gCOMMAND_Area[COMMAND_BUFFER_SIZE]; + +/************************************************************************/ +/*NAME : PutMes */ +/************************************************************************/ +int32_t PutMess(const char *const mess[]) +{ + int32_t i=0; + while(mess[i]){ + PutStr(mess[i],ENB_RTN); + i++; + } + return(0); +} + +/************************************************************************/ +/*NAME : PutStr */ +/************************************************************************/ +int32_t PutStr(const char *str,char rtn) +{ + while(*str){ + PutChar(*str); + str++; + } + if(rtn == 1){ + PutChar(CR_CODE); + PutChar(LF_CODE); + } + return(0); + +} + + +/************************************************************************/ +/*NAME : Hex2Ascii */ +/************************************************************************/ +uint32_t Hex2Ascii(int32_t hexdata,char *str,int32_t *chcnt) +{ + + long i; + char ch; + + for( i = 7; i >= 0; i-- ) { + ch = (char)(hexdata & 0x0F); + if( ch > 9 ) + ch += 7; + ch += 0x30; + hexdata >>= 4; + + *(str + i) = ch; + } + *(str + 8) = '\0'; + *chcnt = 8; + + return 0U; +} + + +uint32_t Hex2DecAscii(int32_t hexdata,char *str,int32_t *chcnt) +{ + char Count; + char countstart; + uint32_t Compdata; + + unsigned char dataB; + uint32_t dataL; + uint32_t i; + + Count = 0; + countstart = 0x0; + dataB = 0; + dataL = 10; + while( dataL > 0 ){ + Compdata = 1; + i = 1; + while( i < dataL ){ + Compdata *= 10; + i++; + } + while( hexdata >= Compdata ){ + hexdata -= Compdata; + dataB++; + countstart = 1; + } + if( countstart == 1 ){ + *(str++) = dataB + '0'; + Count++; + } + dataB = 0; + dataL--; + } + + if(Count==0){ + *str = '0'; + str++; + Count++; + } + *str = '\0'; + *chcnt = Count; + return(0); + +} + + +/************************************************************************/ + +void ChgLtl2Lrg(char *str) +{ + while(*str!=0){ + if(('a' <= *str)&&(*str<='z')) + *str -= 0x20; + str++; + } +} +char HexAscii2Data(unsigned char *buf,uint32_t *data) +{ + char chCnt; + uint32_t tmpData; + *data = 0; + chCnt = 0; + + ChgLtl2Lrg(buf); + + if(*buf=='@') return(3); + while(*buf){ + if(('0'<= *buf)&&(*buf<='9')){ + tmpData = (uint32_t)(*buf - '0'); + *data <<= 4; + *data |= tmpData; + }else if(('A'<= *buf)&&(*buf<='F')){ + tmpData = (uint32_t)(*buf - 55); + *data <<= 4; + *data |= tmpData; + }else{ + return(1); + } + buf++; + chCnt++; + if(chCnt>(SIZE_32BIT*2)) return(1); + } + return(0); +} + +char HexAscii2Data_64(unsigned char *buf,uintptr_t *data) +{ + char chCnt; + uintptr_t tmpData; + *data = 0; + chCnt = 0; + + ChgLtl2Lrg(buf); + + if(*buf=='@') return(3); + while(*buf){ + if(('0'<= *buf)&&(*buf<='9')){ + tmpData = (uintptr_t)(*buf - '0'); + *data <<= 4; + *data |= tmpData; + }else if(('A'<= *buf)&&(*buf<='F')){ + tmpData = (uintptr_t)(*buf - 55); + *data <<= 4; + *data |= tmpData; + }else{ + return(1); + } + buf++; + chCnt++; + if(chCnt>(CPU_BYTE_SIZE*2)) return(1); + } + return(0); +} + + + +char Data2HexAscii(uint32_t data,char *buf,char size) +{ + char loopCnt,i; + uint32_t tmpData; + switch(size){ + case SIZE_8BIT: + data <<= (SIZE_32BIT*8-8); + loopCnt=2; + break; + case SIZE_16BIT: + data <<= (SIZE_32BIT*8-16); + loopCnt=4; + break; + case SIZE_32BIT: + data <<= (SIZE_32BIT*8-32); + loopCnt=8; + break; + } + for(i=0;i> (SIZE_32BIT*8-4)); + if(tmpData < 0x0a){ /* case 1 to 9 */ + *buf = (char)(tmpData + '0'); + }else{ /* case A to F */ + *buf = (char)(tmpData + 55); + } + data <<= 4; + } + *buf = 0; + return(0); +} + +char Data2HexAscii_64(uintptr_t data,char *buf,char size) +{ + char loopCnt,i; + uintptr_t tmpData; + switch(size){ + case SIZE_8BIT: + data <<= (CPU_BYTE_SIZE*8-8); + loopCnt=2; + break; + case SIZE_16BIT: + data <<= (CPU_BYTE_SIZE*8-16); + loopCnt=4; + break; + case SIZE_32BIT: + data <<= (CPU_BYTE_SIZE*8-32); + loopCnt=8; + break; +#ifdef AArch64 + case SIZE_64BIT: + data <<= (CPU_BYTE_SIZE*8-64); + loopCnt=16; + break; +#endif + } + for(i=0;i> (CPU_BYTE_SIZE*8-4)); + if(tmpData < 0x0a){ /* case 1 to 9 */ + *buf = (char)(tmpData + '0'); + }else{ /* case A to F */ + *buf = (char)(tmpData + 55); + } + data <<= 4; + } + *buf = 0; + return(0); +} + +void SoftDelay(uint32_t loop) +{ + uint32_t i; + for(i=0;i +#include +#include +#include "common.h" +#include "devdrv.h" + +#define RCAR_CNTC_EXTAL (16666600U) /* V4H/V4M : 16.666600MHz */ + +#define RCAR_CONV_MICROSEC (1000000U) + +static inline uint64_t get_cntfrq(void) +{ + uint64_t freq; + __asm__ volatile ("mrs %0, cntfrq_el0" : "=r" (freq)); + + return(freq); +} + +static inline void set_cntfrq(uint64_t reg_cntfid) +{ + __asm__ volatile ("msr cntfrq_el0, %0" :: "r" (reg_cntfid)); +} + +static inline uint64_t get_cntpct(void) +{ + uint64_t base_count; + __asm__ volatile ("mrs %0, cntpct_el0" : "=r" (base_count)); + + return(base_count); +} + +void generic_timer_init(void) +{ + /* Update memory mapped and register based freqency */ + /* AArch64:cntfrq_el0 */ + set_cntfrq(RCAR_CNTC_EXTAL); +} +/* End of function generic_timer_init(void) */ + +void micro_wait(uint64_t micro_sec) +{ + uint64_t base_count = 0U; + uint64_t get_count = 0U; + uint64_t wait_time = 0U; + uint64_t freq = 0U; + + /* cntfrq_el0 */ + freq = get_cntfrq(); + /* cntpct_el0 */ + base_count = get_cntpct(); + + micro_sec *= freq; + while (micro_sec > wait_time) + { + /* cntpct */ + get_count = get_cntpct(); + + /* INT30-C Pre confirmation */ + if (get_count < base_count) + { + PutStr("micro_wait(Timer value error!!).", 1U); + while(1U); /* panic */ + } + else + { + wait_time = ((get_count - base_count) * RCAR_CONV_MICROSEC); + } + } +} +/* End of function micro_wait(uint64_t micro_sec) */ + diff --git a/IPL/SDK/v4h/src/Dummy_CA76/hscifdrv0.c b/IPL/SDK/v4h/src/Dummy_CA76/hscifdrv0.c new file mode 100644 index 0000000..8208022 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/hscifdrv0.c @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2020, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "common.h" +#include "hscifdrv0.h" +#include "bit.h" +#include "reg_rcargen3.h" + + +/********************************************************************************/ +/* */ +/* Debug Seirial(HSCIF0) */ +/* */ +/********************************************************************************/ +int32_t PutCharHSCIF0(char outChar) +{ + while(!(0x60U & *((volatile uint16_t*)HSCIF0_HSFSR) )); + *((volatile uint8_t*)HSCIF0_HSFTDR) = outChar; + *((volatile uint16_t*)HSCIF0_HSFSR) &= ~0x60U; /* TEND,TDFE clear */ + return(0); +} + +int32_t GetCharHSCIF0(char *inChar) +{ + do{ + if(0x91 & *((volatile uint16_t *)HSCIF0_HSFSR)) + *((volatile uint16_t *)HSCIF0_HSFSR) &= ~0x91; + if(0x01 & *((volatile uint16_t *)HSCIF0_HSLSR)) + { + PutStr("ORER",1); + *((volatile uint16_t *)HSCIF0_HSLSR) &= ~0x01; + } + }while( !(0x02 & *((volatile uint16_t *)HSCIF0_HSFSR)) ); + *inChar = *((volatile unsigned char*)HSCIF0_HSFRDR); + *((volatile uint16_t*)HSCIF0_HSFSR) &= ~0x02; + return(0); +} + +void PowerOnHscif0(void) +{ + uint32_t dataL; +#ifdef RCAR_GEN3_CONDOR + dataL = *((volatile uint32_t*)CPG_MSTPSR5); + if(dataL & BIT20){ /* case HSCIF0 */ + dataL &= ~BIT20; + *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; + *((volatile uint32_t*)CPG_SMSTPCR5) = dataL; + while( BIT20 & *((volatile uint32_t*)CPG_MSTPSR5) ); /* wait bit=0 */ + } +#endif /* RCAR_GEN3_CONDOR */ +#ifdef RCAR_GEN3_FALCON + dataL = *((volatile uint32_t*)CPG_MSTPSR5); + if(dataL & BIT14){ /* case HSCIF0 */ + dataL &= ~BIT14; + *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; + *((volatile uint32_t*)CPG_MSTPCR5) = dataL; + while( BIT14 & *((volatile uint32_t*)CPG_MSTPSR5) ); /* wait bit=0 */ + } +#endif /* RCAR_GEN3_FALCON */ +} + +void WaitPutHscif0SendEnd(void) +{ + uint16_t dataW; + uint32_t loop; + + loop=1U; + while(loop){ + dataW = *((volatile uint16_t*)HSCIF0_HSFSR); + if(dataW & BIT6) { + loop = 0U; + } + } +} + +void InitHscif0PinFunction(void) +{ + uint32_t dataL; +#ifdef RCAR_GEN3_CONDOR + /* HSCIF0 */ + dataL = *((volatile uint32_t*)PFC_IPSR7); + dataL &= ~(0x0FF00000U); + dataL |= 0x05500000U; /* IPSR7[27:24]=4'b0101, IPSR7[23:20]=4'b0101 */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_IPSR7) = dataL; + + dataL = *((volatile uint32_t*)PFC_GPSR4); + dataL |= 0x00000030U; /* GPSR4[5],GPSR4[4] */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_GPSR4) = dataL; +#endif /* RCAR_GEN3_CONDOR */ +#ifdef RCAR_GEN3_FALCON + /* HSCIF0 */ + dataL = *((volatile uint32_t*)PFC_IP0SR1); + dataL &= ~(0x00F000F0U); + dataL |= 0x00000000U; /* IP0SR1[23:20]=4'b0000(HTX0), IP0SR1[4:7]=4'b0000(HRX0) */ + dataL &= 0x0; /* bit0:SCIF_CLK=0 */ + *((volatile uint32_t*)PFC_PMMR1) = ~dataL; + *((volatile uint32_t*)PFC_IP0SR1) = dataL; + + dataL = *((volatile uint32_t*)PFC_GPSR1); /* SDA2/SCL2 is not found in V3U TS */ + dataL |= 0x00000022U; /* GPSR4[5],GPSR4[4] */ + *((volatile uint32_t*)PFC_PMMR1) = ~dataL; + *((volatile uint32_t*)PFC_GPSR1) = dataL; + +#endif /* RCAR_GEN3_FALCON */ +} + +void InitHscif0_SCIFCLK(void) +{ + uint16_t dataW; +#if RCAR_GEN3_FALCON + uint32_t modemr0; + uint32_t modemr1; +#endif /* RCAR_GEN3_FALCON */ + + PowerOnHscif0(); + + InitHscif0PinFunction(); + + dataW = *((volatile uint16_t*)HSCIF0_HSLSR); /* dummy read */ + *((volatile uint16_t*)HSCIF0_HSLSR) = 0x0000U; /* clear ORER bit */ + *((volatile uint16_t*)HSCIF0_HSFSR) = 0x0000U; /* clear all error bit */ + *((volatile uint16_t*)HSCIF0_HSSCR) = 0x0000U; /* clear SCR.TE & SCR.RE*/ + *((volatile uint16_t*)HSCIF0_HSFCR) = 0x0006U; /* reset tx-fifo, reset rx-fifo. */ + *((volatile uint16_t*)HSCIF0_HSFSR) = 0x0000U; /* clear ER, TEND, TDFE, BRK, RDF, DR */ + *((volatile uint16_t*)HSCIF0_HSSCR) = 0x0000U; /* internal clock, SCK pin is not used */ + *((volatile uint16_t*)HSCIF0_HSSMR) = 0x0000U; /* 8bit data, no-parity, 1 stop, Po/1 */ + +#if defined(RCAR_GEN3_CONDOR) + *((volatile uint16_t*)HSCIF0_HSSRR) = 0x8007U; /* SRE=1,SRCYC[4:0]=S(8)-1=7 */ + SoftDelay(100U); + *((volatile uint8_t*)HSCIF0_HSBRR) = 0x11U; /* 921600bps@266.6MHz */ + +#elif defined(RCAR_GEN3_FALCON) + modemr0 = *((volatile uint32_t*)RST_MODEMR0) & MODEMR0_MD31_V3U; /* bit31 */ + modemr1 = *((volatile uint32_t*)RST_MODEMR1) & MODEMR1_MD32_V3U; /* bit0 */ + + switch(modemr0 | modemr1){ + case MODEMR_SCIF_921600_V3U: + *((volatile uint16_t*)HSCIF0_HSSRR) = 0x8007U; /* SRE=1,SRCYC[4:0]=S(8)-1=7 */ + SoftDelay(100U); + *((volatile uint8_t*)HSCIF0_HSBRR) = 0x11U; /* 921600bps@266.6MHz */ + break; + case MODEMR_SCIF_1843200_V3U: + *((volatile uint16_t*)HSCIF0_HSSRR) = 0x8007U; /* SRE=1,SRCYC[4:0]=S(8)-1=7 */ + SoftDelay(100U); + *((volatile uint8_t*)HSCIF0_HSBRR) = 0x08U; /* 1843200bps@266.6MHz */ + break; + case MODEMR_SCIF_3000000_V3U: + *((volatile uint16_t*)HSCIF0_HSSRR) = 0x8007; /* 3000000bps with SCIF_CLK */ + *((volatile uint16_t*)HSCIF0_HSSCR) = 0x0002; /* external clock, SC_CLK pin used for input pin */ + *((volatile uint16_t*)HSCIF0_DL) = 0x0001; /* Frequency Division is 1 */ + *((volatile uint16_t*)HSCIF0_CKS) = 0x0000; /* select scif_clk */ + break; + default: + break; + } + +#endif /* defined(RCAR_GEN3_CONDOR) */ + + SoftDelay(100U); + *((volatile uint16_t*)HSCIF0_HSFCR) = 0x0000U; /* reset-off tx-fifo, rx-fifo. */ + *((volatile uint16_t*)HSCIF0_HSSCR) = 0x0030U; /* enable TE, RE; SCK pin is not used */ + SoftDelay(100U); +} + + +uint32_t HSCIF0_TerminalInputCheck(char* str) +{ + char result = 0; + + if(0x91 & *((volatile uint16_t *)HSCIF0_HSFSR)) + *((volatile uint16_t *)HSCIF0_HSFSR) &= ~0x91; + if(0x01 & *((volatile uint16_t *)HSCIF0_HSLSR)) + { + PutStr("ORER",1); + *((volatile uint16_t *)HSCIF0_HSLSR) &= ~0x01; + } + if(0x02 & *((volatile uint16_t *)HSCIF0_HSFSR)) + { + *str = *((volatile unsigned char*)HSCIF0_HSFRDR); + *((volatile uint16_t*)HSCIF0_HSFSR) &= ~0x02; + result = 1; + } + return result; +} diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/bit.h b/IPL/SDK/v4h/src/Dummy_CA76/include/bit.h new file mode 100644 index 0000000..6ca2ca5 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/bit.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef BIT_H +#define BIT_H + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#endif /* BIT_H */ diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/common.h b/IPL/SDK/v4h/src/Dummy_CA76/include/common.h new file mode 100644 index 0000000..c2600fe --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/common.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef COMMON_H +#define COMMON_H + +#include + + +#ifdef AArch64 +//typedef uint64_t uintptr_t; +#define CPU_BYTE_SIZE SIZE_64BIT +#endif + +#ifdef AArch32 +//typedef uint32_t uintptr_t; +#define CPU_BYTE_SIZE SIZE_32BIT +#endif + + +#define DIS_RTN 0 /* Disable Return */ +#define ENB_RTN 1 /* Enable Return */ +#define OK 0x1 + +#ifndef NULL +#define NULL 0x0 +#endif + +#define INT_CODE 0x25 /* "%" */ +#define BS_CODE 0x08 /* "BS" */ +#define CR_CODE 0x0d /* "CR" */ +#define SP_CODE 0x20 /* "LF" */ +#define LF_CODE 0x0a /* "LF" */ + +#define SIZE_8BIT 1 // Old name : BYTE_SIZE +#define SIZE_16BIT 2 // Old name : WORD_SIZE +#define SIZE_32BIT 4 // Old name : LONG_SIZE +#define SIZE_64BIT 8 // New + +#define COMMAND_BUFFER_SIZE 1024 + + +/**************************** + Module Proto Type * +****************************/ +int32_t PutMess(const char *const mess[]); +int32_t PutStr(const char *str,char rtn); +uint32_t Hex2Ascii(int32_t hexdata,char *str,int32_t *chcnt); +uint32_t Hex2DecAscii(int32_t hexdata,char *str,int32_t *chcnt); +void ChgLtl2Lrg(char *str); +char HexAscii2Data(unsigned char *buf,uint32_t *data); +char HexAscii2Data_64(unsigned char *buf,uintptr_t *data); +char Data2HexAscii(uint32_t data,char *buf,char size); +char Data2HexAscii_64(uintptr_t data,char *buf,char size); +void SoftDelay(uint32_t roop); + +#endif diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/devdrv.h b/IPL/SDK/v4h/src/Dummy_CA76/include/devdrv.h new file mode 100644 index 0000000..b6906c5 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/devdrv.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef DEVDRV_H +#define DEVDRV_H + +int32_t PutChar(char outChar); +int32_t WaitPutCharSendEnd(void); + +#endif /* DEVDRV_H */ diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/hscifdrv0.h b/IPL/SDK/v4h/src/Dummy_CA76/include/hscifdrv0.h new file mode 100644 index 0000000..efa10c7 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/hscifdrv0.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2020, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef HSCIFDRV0_H +#define HSCIFDRV0_H + +int32_t PutCharHSCIF0(char outChar); +int32_t GetCharHSCIF0(char *inChar); +void PowerOnHscif0(void); +void WaitPutHscif0SendEnd(void); +void InitHscif0_SCIFCLK(void); +uint32_t HSCIF0_TerminalInputCheck(char* str); + +#endif /* HSCIFDRV0_H */ diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/init_scif.h b/IPL/SDK/v4h/src/Dummy_CA76/include/init_scif.h new file mode 100644 index 0000000..4a87d81 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/init_scif.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef INITSCIF_H +#define INITSCIF_H + +void InitScif(void); + +#endif /* INITSCIF_H */ diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/main.h b/IPL/SDK/v4h/src/Dummy_CA76/include/main.h new file mode 100644 index 0000000..1cc16c4 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/main.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef MAIN_H +#define MAIN_H + +void Main(void); + +#endif /* MAIN_H */ diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/mem_io.h b/IPL/SDK/v4h/src/Dummy_CA76/include/mem_io.h new file mode 100644 index 0000000..7402255 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/mem_io.h @@ -0,0 +1,54 @@ +/******************************************************************************* + * Copyright (c) 2018-2020 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Memory access driver header + ******************************************************************************/ +#ifndef MEM_IO_H_ +#define MEM_IO_H_ + +#include + +/* Prototype */ +void mem_write8(uintptr_t addr, uint8_t data); +uint8_t mem_read8(uintptr_t addr); +void mem_write16(uintptr_t addr, uint16_t data); +uint16_t mem_read16(uintptr_t addr); +void mem_write32(uintptr_t addr, uint32_t data); +uint32_t mem_read32(uintptr_t addr); +void mem_write64(uintptr_t addr, uint64_t data); +void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set); +void mem_bitset32(uintptr_t addr, uint32_t set); +#if defined(__RH850G3K__) +#define mmio_write_32(a,b) mem_write32(a,b) +#define mmio_read_32(a) mem_read32(a) +#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c) +#endif + + +#endif /* MEM_IO_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/reg_rcargen3.h b/IPL/SDK/v4h/src/Dummy_CA76/include/reg_rcargen3.h new file mode 100644 index 0000000..81e32b6 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/reg_rcargen3.h @@ -0,0 +1,608 @@ +/* + * Copyright (c) 2018-2025 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef REG_RCARGEN3_H +#define REG_RCARGEN3_H + +#define RCAR_CNTC_BASE (0xE6080000) /* The base addess of generic timer control register */ +#define CNTFID_OFF 0x020 +#define CNTCR_OFF 0x000 + + +//CPG for S4 +#define CPG_BASE (0xE6150000U) +#define CPG_CPGWPCR (CPG_BASE + 0x0004U) // R/W 32 CPG Write Protect Control Register +#define CPG_CPGWPR (CPG_BASE + 0x0000U) // R/W 32 CPG Write Protect Register +#define CPG_SD0CKCR (CPG_BASE + 0x0870U) // R/W 32 SD-IF0 clock frequency control register +#define CPG_RPCCKCR (CPG_BASE + 0x0874U) // R/W 32 RPC clock frequency control register +//MSTPRST +#define CPG_SRCR0 (CPG_BASE + 0x2C00U) // R/W 32 Software reset register 0 +#define CPG_SRCR1 (CPG_BASE + 0x2C04U) // R/W 32 Software reset register 1 +#define CPG_SRCR2 (CPG_BASE + 0x2C08U) // R/W 32 Software reset register 2 +#define CPG_SRCR3 (CPG_BASE + 0x2C0CU) // R/W 32 Software reset register 3 +#define CPG_SRCR4 (CPG_BASE + 0x2C10U) // R/W 32 Software reset register 4 +#define CPG_SRCR5 (CPG_BASE + 0x2C14U) // R/W 32 Software reset register 5 +#define CPG_SRCR6 (CPG_BASE + 0x2C18U) // R/W 32 Software reset register 6 +#define CPG_SRCR7 (CPG_BASE + 0x2C1CU) // R/W 32 Software reset register 7 +#define CPG_SRCR8 (CPG_BASE + 0x2C20U) // R/W 32 Software reset register 8 +#define CPG_SRCR9 (CPG_BASE + 0x2C24U) // R/W 32 Software reset register 9 +#define CPG_SRCR10 (CPG_BASE + 0x2C28U) // R/W 32 Software reset register 10 +#define CPG_SRCR11 (CPG_BASE + 0x2C2CU) // R/W 32 Software reset register 11 +#define CPG_SRCR12 (CPG_BASE + 0x2C30U) // R/W 32 Software reset register 12 +#define CPG_SRCR13 (CPG_BASE + 0x2C34U) // R/W 32 Software reset register 13 +#define CPG_SRCR14 (CPG_BASE + 0x2C38U) // R/W 32 Software reset register 14 +#define CPG_SRCR15 (CPG_BASE + 0x2C3CU) // R/W 32 Software reset register 15 +#define CPG_SRCR16 (CPG_BASE + 0x2C40U) // R/W 32 Software reset register 16 +#define CPG_SRCR17 (CPG_BASE + 0x2C44U) // R/W 32 Software reset register 17 +#define CPG_SRCR18 (CPG_BASE + 0x2C48U) // R/W 32 Software reset register 18 +#define CPG_SRCR19 (CPG_BASE + 0x2C4CU) // R/W 32 Software reset register 19 +#define CPG_SRCR20 (CPG_BASE + 0x2C50U) // R/W 32 Software reset register 20 +#define CPG_SRCR21 (CPG_BASE + 0x2C54U) // R/W 32 Software reset register 21 +#define CPG_SRCR22 (CPG_BASE + 0x2C58U) // R/W 32 Software reset register 22 +#define CPG_SRCR23 (CPG_BASE + 0x2C5CU) // R/W 32 Software reset register 23 +#define CPG_SRSTCLR0 (CPG_BASE + 0x2C80U) // W 32 Software reset clearing register 0 +#define CPG_SRSTCLR1 (CPG_BASE + 0x2C84U) // W 32 Software reset clearing register 1 +#define CPG_SRSTCLR2 (CPG_BASE + 0x2C88U) // W 32 Software reset clearing register 2 +#define CPG_SRSTCLR3 (CPG_BASE + 0x2C8CU) // W 32 Software reset clearing register 3 +#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U) // W 32 Software reset clearing register 4 +#define CPG_SRSTCLR5 (CPG_BASE + 0x2C94U) // W 32 Software reset clearing register 5 +#define CPG_SRSTCLR6 (CPG_BASE + 0x2C98U) // W 32 Software reset clearing register 6 +#define CPG_SRSTCLR7 (CPG_BASE + 0x2C9CU) // W 32 Software reset clearing register 7 +#define CPG_SRSTCLR8 (CPG_BASE + 0x2CA0U) // W 32 Software reset clearing register 8 +#define CPG_SRSTCLR9 (CPG_BASE + 0x2CA4U) // W 32 Software reset clearing register 9 +#define CPG_SRSTCLR10 (CPG_BASE + 0x2CA8U) // W 32 Software reset clearing register 10 +#define CPG_SRSTCLR11 (CPG_BASE + 0x2CACU) // W 32 Software reset clearing register 11 +#define CPG_SRSTCLR12 (CPG_BASE + 0x2CB0U) // W 32 Software reset clearing register 12 +#define CPG_SRSTCLR13 (CPG_BASE + 0x2CB4U) // W 32 Software reset clearing register 13 +#define CPG_SRSTCLR14 (CPG_BASE + 0x2CB8U) // W 32 Software reset clearing register 14 +#define CPG_SRSTCLR15 (CPG_BASE + 0x2CBCU) // W 32 Software reset clearing register 15 +#define CPG_SRSTCLR16 (CPG_BASE + 0x2CC0U) // W 32 Software reset clearing register 16 +#define CPG_SRSTCLR17 (CPG_BASE + 0x2CC4U) // W 32 Software reset clearing register 17 +#define CPG_SRSTCLR18 (CPG_BASE + 0x2CC8U) // W 32 Software reset clearing register 18 +#define CPG_SRSTCLR19 (CPG_BASE + 0x2CCCU) // W 32 Software reset clearing register 19 +#define CPG_SRSTCLR20 (CPG_BASE + 0x2CD0U) // W 32 Software reset clearing register 20 +#define CPG_SRSTCLR21 (CPG_BASE + 0x2CD4U) // W 32 Software reset clearing register 21 +#define CPG_SRSTCLR22 (CPG_BASE + 0x2CD8U) // W 32 Software reset clearing register 22 +#define CPG_SRSTCLR23 (CPG_BASE + 0x2CDCU) // W 32 Software reset clearing register 23 +#define CPG_MSTPCR0 (CPG_BASE + 0x2D00U) // R/W 32 Domain0 module stop control register 0 +#define CPG_MSTPCR1 (CPG_BASE + 0x2D04U) // R/W 32 Domain0 module stop control register 1 +#define CPG_MSTPCR2 (CPG_BASE + 0x2D08U) // R/W 32 Domain0 module stop control register 2 +#define CPG_MSTPCR3 (CPG_BASE + 0x2D0CU) // R/W 32 Domain0 module stop control register 3 +#define CPG_MSTPCR4 (CPG_BASE + 0x2D10U) // R/W 32 Domain0 module stop control register 4 +#define CPG_MSTPCR5 (CPG_BASE + 0x2D14U) // R/W 32 Domain0 module stop control register 5 +#define CPG_MSTPCR6 (CPG_BASE + 0x2D18U) // R/W 32 Domain0 module stop control register 6 +#define CPG_MSTPCR7 (CPG_BASE + 0x2D1CU) // R/W 32 Domain0 module stop control register 7 +#define CPG_MSTPCR8 (CPG_BASE + 0x2D20U) // R/W 32 Domain0 module stop control register 8 +#define CPG_MSTPCR9 (CPG_BASE + 0x2D24U) // R/W 32 Domain0 module stop control register 9 +#define CPG_MSTPCR10 (CPG_BASE + 0x2D28U) // R/W 32 Domain0 module stop control register 10 +#define CPG_MSTPCR11 (CPG_BASE + 0x2D2CU) // R/W 32 Domain0 module stop control register 11 +#define CPG_MSTPCR12 (CPG_BASE + 0x2D30U) // R/W 32 Domain0 module stop control register 12 +#define CPG_MSTPCR13 (CPG_BASE + 0x2D34U) // R/W 32 Domain0 module stop control register 13 +#define CPG_MSTPCR14 (CPG_BASE + 0x2D38U) // R/W 32 Domain0 module stop control register 14 +#define CPG_MSTPCR15 (CPG_BASE + 0x2D3CU) // R/W 32 Domain0 module stop control register 15 +#define CPG_MSTPCR16 (CPG_BASE + 0x2D40U) // R/W 32 Domain0 module stop control register 16 +#define CPG_MSTPCR17 (CPG_BASE + 0x2D44U) // R/W 32 Domain0 module stop control register 17 +#define CPG_MSTPCR18 (CPG_BASE + 0x2D48U) // R/W 32 Domain0 module stop control register 18 +#define CPG_MSTPCR19 (CPG_BASE + 0x2D4CU) // R/W 32 Domain0 module stop control register 19 +#define CPG_MSTPCR20 (CPG_BASE + 0x2D50U) // R/W 32 Domain0 module stop control register 20 +#define CPG_MSTPCR21 (CPG_BASE + 0x2D54U) // R/W 32 Domain0 module stop control register 21 +#define CPG_MSTPCR22 (CPG_BASE + 0x2D58U) // R/W 32 Domain0 module stop control register 22 +#define CPG_MSTPCR23 (CPG_BASE + 0x2D5CU) // R/W 32 Domain0 module stop control register 23 +#define CPG_MSTPSR0 (CPG_BASE + 0x2E00U) // R 32 Module stop status register 0 +#define CPG_MSTPSR1 (CPG_BASE + 0x2E04U) // R 32 Module stop status register 1 +#define CPG_MSTPSR2 (CPG_BASE + 0x2E08U) // R 32 Module stop status register 2 +#define CPG_MSTPSR3 (CPG_BASE + 0x2E0CU) // R 32 Module stop status register 3 +#define CPG_MSTPSR4 (CPG_BASE + 0x2E10U) // R 32 Module stop status register 4 +#define CPG_MSTPSR5 (CPG_BASE + 0x2E14U) // R 32 Module stop status register 5 +#define CPG_MSTPSR6 (CPG_BASE + 0x2E18U) // R 32 Module stop status register 6 +#define CPG_MSTPSR7 (CPG_BASE + 0x2E1CU) // R 32 Module stop status register 7 +#define CPG_MSTPSR8 (CPG_BASE + 0x2E20U) // R 32 Module stop status register 8 +#define CPG_MSTPSR9 (CPG_BASE + 0x2E24U) // R 32 Module stop status register 9 +#define CPG_MSTPSR10 (CPG_BASE + 0x2E28U) // R 32 Module stop status register 10 +#define CPG_MSTPSR11 (CPG_BASE + 0x2E2CU) // R 32 Module stop status register 11 +#define CPG_MSTPSR12 (CPG_BASE + 0x2E30U) // R 32 Module stop status register 12 +#define CPG_MSTPSR13 (CPG_BASE + 0x2E34U) // R 32 Module stop status register 13 +#define CPG_MSTPSR14 (CPG_BASE + 0x2E38U) // R 32 Module stop status register 14 +#define CPG_MSTPSR15 (CPG_BASE + 0x2E3CU) // R 32 Module stop status register 15 +#define CPG_MSTPSR16 (CPG_BASE + 0x2E40U) // R 32 Module stop status register 16 +#define CPG_MSTPSR17 (CPG_BASE + 0x2E44U) // R 32 Module stop status register 17 +#define CPG_MSTPSR18 (CPG_BASE + 0x2E48U) // R 32 Module stop status register 18 +#define CPG_MSTPSR19 (CPG_BASE + 0x2E4CU) // R 32 Module stop status register 19 +#define CPG_MSTPSR20 (CPG_BASE + 0x2E50U) // R 32 Module stop status register 20 +#define CPG_MSTPSR21 (CPG_BASE + 0x2E54U) // R 32 Module stop status register 21 +#define CPG_MSTPSR22 (CPG_BASE + 0x2E58U) // R 32 Module stop status register 22 +#define CPG_MSTPSR23 (CPG_BASE + 0x2E5CU) // R 32 Module stop status register 23 + + +//LBSC.h +#define LBSC_CS0CTRL 0xEE220200 // R/W 32 Area 0 control register +#define LBSC_CS1CTRL 0xEE220204 // R/W 32 Area 1 control register +#define LBSC_CSWCR0 0xEE220230 // R/W 32 Area 0 RD/WE pulse control register +#define LBSC_CSWCR1 0xEE220234 // R/W 32 Area 1 RD/WE pulse control register +#define LBSC_CSPWCR0 0xEE220280 // R/W 32 Area 0 external wait control register +#define LBSC_CSPWCR1 0xEE220284 // R/W 32 Area 1 external wait control register +#define LBSC_EXWTSYNC 0xEE2202A0 // R/W 32 External wait input control register +#define LBSC_CS0BSTCTL 0xEE2202B0 // R/W 32 Area 0 burst control register +#define LBSC_CS0BTPH 0xEE2202B4 // R/W 32 Area 0 burst pitch set register +#define LBSC_CS1GDST 0xEE2202C0 // R/W 32 Area 1 guard setting register +#define LBSC_BCINTSR 0xEE220330 // R 32 BSC interrupt source status register +#define LBSC_BCINTCR 0xEE220334 // -/WC1 32 BSC interrupt source clear register +#define LBSC_BCINTMR 0xEE220338 // R/W 32 BSC interrupt enable register +#define LBSC_EXWTSTS 0xEE220344 // R 32 External wait status register +#define LBSC_EXBCT 0xEE2203C0 // R/W 32 EX-BUS wait timeout detection base counter register +#define LBSC_EXTCT 0xEE2203C4 // R/W 32 EX-BUS wait timeout detection counter register +#define LBSC_EXTSR 0xEE220010 // R/WC1 32 EX-BUS wait timeout detection access source indication register +#define LBSC_EXTADR 0xEE220014 // R/W 32 EX-BUS wait timeout detection address indication register + + + +//PFC for S4 +#define PFC_BASE (0xE6050000) +#define PFC_MCU_BASE (0xFFD90000) + +#define PFC_PORT_GRP0 (0x00000000U) /* Port Group0/4 */ +#define PFC_PORT_GRP1 (0x00000800U) /* Port Group1/5 */ +#define PFC_PORT_GRP2 (0x00001000U) /* Port Group2/6 */ +#define PFC_PORT_GRP3 (0x00001800U) /* Port Group3/7 */ +#define PFC_SYS_GRP (0x00008000U) +#define PFC_PORT_GRP_MASK (0xFFFFF800U) +#define PFC_PMMR(addr) ((addr) & PFC_PORT_GRP_MASK + 0x0000U) + +/* Port Group0 */ +#define PFC_PMMR0 (PFC_BASE + PFC_PORT_GRP0 + 0x0000U) +#define PFC_GPSR0 (PFC_BASE + PFC_PORT_GRP0 + 0x0040U) +#define PFC_IP0SR0 (PFC_BASE + PFC_PORT_GRP0 + 0x0060U) +#define PFC_IP1SR0 (PFC_BASE + PFC_PORT_GRP0 + 0x0064U) +#define PFC_IP2SR0 (PFC_BASE + PFC_PORT_GRP0 + 0x0068U) +#define PFC_IP3SR0 (PFC_BASE + PFC_PORT_GRP0 + 0x006CU) +#define PFC_DRV0CTRL0 (PFC_BASE + PFC_PORT_GRP0 + 0x0080U) +#define PFC_DRV1CTRL0 (PFC_BASE + PFC_PORT_GRP0 + 0x0084U) +#define PFC_DRV2CTRL0 (PFC_BASE + PFC_PORT_GRP0 + 0x0088U) +#define PFC_DRV3CTRL0 (PFC_BASE + PFC_PORT_GRP0 + 0x008CU) +#define PFC_POC0 (PFC_BASE + PFC_PORT_GRP0 + 0x00A0U) +#define PFC_PUEN0 (PFC_BASE + PFC_PORT_GRP0 + 0x00C0U) +#define PFC_PUD0 (PFC_BASE + PFC_PORT_GRP0 + 0x00E0U) +#define PFC_MOD_SEL0 (PFC_BASE + PFC_PORT_GRP0 + 0x0100U) +#define GPIO_IOINTSEL0 (PFC_BASE + PFC_PORT_GRP0 + 0x0180U) +#define GPIO_INOUTSEL0 (PFC_BASE + PFC_PORT_GRP0 + 0x0184U) +#define GPIO_OUTDT0 (PFC_BASE + PFC_PORT_GRP0 + 0x0188U) +#define GPIO_INDT0 (PFC_BASE + PFC_PORT_GRP0 + 0x018CU) +#define GPIO_INTDT0 (PFC_BASE + PFC_PORT_GRP0 + 0x0190U) +#define GPIO_INTCLR0 (PFC_BASE + PFC_PORT_GRP0 + 0x0194U) +#define GPIO_INTMSK0 (PFC_BASE + PFC_PORT_GRP0 + 0x0198U) +#define GPIO_MSKCLR0 (PFC_BASE + PFC_PORT_GRP0 + 0x019CU) +#define GPIO_POSNEG0 (PFC_BASE + PFC_PORT_GRP0 + 0x01A0U) +/* Port Group1 */ +#define PFC_PMMR1 (PFC_BASE + PFC_PORT_GRP1 + 0x0000U) +#define PFC_GPSR1 (PFC_BASE + PFC_PORT_GRP1 + 0x0040U) +#define PFC_IP0SR1 (PFC_BASE + PFC_PORT_GRP1 + 0x0060U) +#define PFC_IP1SR1 (PFC_BASE + PFC_PORT_GRP1 + 0x0064U) +#define PFC_IP2SR1 (PFC_BASE + PFC_PORT_GRP1 + 0x0068U) +#define PFC_IP3SR1 (PFC_BASE + PFC_PORT_GRP1 + 0x006CU) +#define PFC_DRV0CTRL1 (PFC_BASE + PFC_PORT_GRP1 + 0x0080U) +#define PFC_DRV1CTRL1 (PFC_BASE + PFC_PORT_GRP1 + 0x0084U) +#define PFC_DRV2CTRL1 (PFC_BASE + PFC_PORT_GRP1 + 0x0088U) +#define PFC_DRV3CTRL1 (PFC_BASE + PFC_PORT_GRP1 + 0x008CU) +#define PFC_POC1 (PFC_BASE + PFC_PORT_GRP1 + 0x00A0U) +#define PFC_PUEN1 (PFC_BASE + PFC_PORT_GRP1 + 0x00C0U) +#define PFC_PUD1 (PFC_BASE + PFC_PORT_GRP1 + 0x00E0U) +#define PFC_MOD_SEL1 (PFC_BASE + PFC_PORT_GRP1 + 0x0100U) +#define GPIO_IOINTSEL1 (PFC_BASE + PFC_PORT_GRP1 + 0x0180U) +#define GPIO_INOUTSEL1 (PFC_BASE + PFC_PORT_GRP1 + 0x0184U) +#define GPIO_OUTDT1 (PFC_BASE + PFC_PORT_GRP1 + 0x0188U) +#define GPIO_INDT1 (PFC_BASE + PFC_PORT_GRP1 + 0x018CU) +#define GPIO_INTDT1 (PFC_BASE + PFC_PORT_GRP1 + 0x0190U) +#define GPIO_INTCLR1 (PFC_BASE + PFC_PORT_GRP1 + 0x0194U) +#define GPIO_INTMSK1 (PFC_BASE + PFC_PORT_GRP1 + 0x0198U) +#define GPIO_MSKCLR1 (PFC_BASE + PFC_PORT_GRP1 + 0x019CU) +#define GPIO_POSNEG1 (PFC_BASE + PFC_PORT_GRP1 + 0x01A0U) +/* Port Group2 */ +#define PFC_PMMR2 (PFC_BASE + PFC_PORT_GRP2 + 0x0000U) +#define PFC_GPSR2 (PFC_BASE + PFC_PORT_GRP2 + 0x0040U) +#define PFC_IP0SR2 (PFC_BASE + PFC_PORT_GRP2 + 0x0060U) +#define PFC_IP1SR2 (PFC_BASE + PFC_PORT_GRP2 + 0x0064U) +#define PFC_IP2SR2 (PFC_BASE + PFC_PORT_GRP2 + 0x0068U) +#define PFC_IP3SR2 (PFC_BASE + PFC_PORT_GRP2 + 0x006CU) +#define PFC_DRV0CTRL2 (PFC_BASE + PFC_PORT_GRP2 + 0x0080U) +#define PFC_DRV1CTRL2 (PFC_BASE + PFC_PORT_GRP2 + 0x0084U) +#define PFC_DRV2CTRL2 (PFC_BASE + PFC_PORT_GRP2 + 0x0088U) +#define PFC_DRV3CTRL2 (PFC_BASE + PFC_PORT_GRP2 + 0x008CU) +#define PFC_POC2 (PFC_BASE + PFC_PORT_GRP2 + 0x00A0U) +#define PFC_PUEN2 (PFC_BASE + PFC_PORT_GRP2 + 0x00C0U) +#define PFC_PUD2 (PFC_BASE + PFC_PORT_GRP2 + 0x00E0U) +#define PFC_MOD_SEL2 (PFC_BASE + PFC_PORT_GRP2 + 0x0100U) +#define GPIO_IOINTSEL2 (PFC_BASE + PFC_PORT_GRP2 + 0x0180U) +#define GPIO_INOUTSEL2 (PFC_BASE + PFC_PORT_GRP2 + 0x0184U) +#define GPIO_OUTDT2 (PFC_BASE + PFC_PORT_GRP2 + 0x0188U) +#define GPIO_INDT2 (PFC_BASE + PFC_PORT_GRP2 + 0x018CU) +#define GPIO_INTDT2 (PFC_BASE + PFC_PORT_GRP2 + 0x0190U) +#define GPIO_INTCLR2 (PFC_BASE + PFC_PORT_GRP2 + 0x0194U) +#define GPIO_INTMSK2 (PFC_BASE + PFC_PORT_GRP2 + 0x0198U) +#define GPIO_MSKCLR2 (PFC_BASE + PFC_PORT_GRP2 + 0x019CU) +#define GPIO_POSNEG2 (PFC_BASE + PFC_PORT_GRP2 + 0x01A0U) +/* Port Group3 */ +#define PFC_PMMR3 (PFC_BASE + PFC_PORT_GRP3 + 0x0000U) +#define PFC_GPSR3 (PFC_BASE + PFC_PORT_GRP3 + 0x0040U) +#define PFC_IP0SR3 (PFC_BASE + PFC_PORT_GRP3 + 0x0060U) +#define PFC_IP1SR3 (PFC_BASE + PFC_PORT_GRP3 + 0x0064U) +#define PFC_IP2SR3 (PFC_BASE + PFC_PORT_GRP3 + 0x0068U) +#define PFC_IP3SR3 (PFC_BASE + PFC_PORT_GRP3 + 0x006CU) +#define PFC_DRV0CTRL3 (PFC_BASE + PFC_PORT_GRP3 + 0x0080U) +#define PFC_DRV1CTRL3 (PFC_BASE + PFC_PORT_GRP3 + 0x0084U) +#define PFC_DRV2CTRL3 (PFC_BASE + PFC_PORT_GRP3 + 0x0088U) +#define PFC_DRV3CTRL3 (PFC_BASE + PFC_PORT_GRP3 + 0x008CU) +#define PFC_POC3 (PFC_BASE + PFC_PORT_GRP3 + 0x00A0U) +#define PFC_PUEN3 (PFC_BASE + PFC_PORT_GRP3 + 0x00C0U) +#define PFC_PUD3 (PFC_BASE + PFC_PORT_GRP3 + 0x00E0U) +#define PFC_MOD_SEL3 (PFC_BASE + PFC_PORT_GRP3 + 0x0100U) +#define GPIO_IOINTSEL3 (PFC_BASE + PFC_PORT_GRP3 + 0x0180U) +#define GPIO_INOUTSEL3 (PFC_BASE + PFC_PORT_GRP3 + 0x0184U) +#define GPIO_OUTDT3 (PFC_BASE + PFC_PORT_GRP3 + 0x0188U) +#define GPIO_INDT3 (PFC_BASE + PFC_PORT_GRP3 + 0x018CU) +#define GPIO_INTDT3 (PFC_BASE + PFC_PORT_GRP3 + 0x0190U) +#define GPIO_INTCLR3 (PFC_BASE + PFC_PORT_GRP3 + 0x0194U) +#define GPIO_INTMSK3 (PFC_BASE + PFC_PORT_GRP3 + 0x0198U) +#define GPIO_MSKCLR3 (PFC_BASE + PFC_PORT_GRP3 + 0x019CU) +#define GPIO_POSNEG3 (PFC_BASE + PFC_PORT_GRP3 + 0x01A0U) +/* Port Group4 */ +#define PFC_PMMR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0000U) +#define PFC_GPSR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0040U) +#define PFC_IP0SR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0060U) +#define PFC_IP1SR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0064U) +#define PFC_IP2SR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0068U) +#define PFC_IP3SR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x006CU) +#define PFC_DRV0CTRL4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0080U) +#define PFC_DRV1CTRL4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0084U) +#define PFC_DRV2CTRL4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0088U) +#define PFC_DRV3CTRL4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x008CU) +#define PFC_POC4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x00A0U) +#define PFC_PUEN4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x00C0U) +#define PFC_PUD4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x00E0U) +#define PFC_MOD_SEL4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0100U) +#define GPIO_IOINTSEL4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0180U) +#define GPIO_INOUTSEL4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0184U) +#define GPIO_OUTDT4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0188U) +#define GPIO_INDT4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x018CU) +#define GPIO_INTDT4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0190U) +#define GPIO_INTCLR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0194U) +#define GPIO_INTMSK4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x0198U) +#define GPIO_MSKCLR4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x019CU) +#define GPIO_POSNEG4 (PFC_MCU_BASE + PFC_PORT_GRP0 + 0x01A0U) +/* Port Group5 */ +#define PFC_PMMR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0000U) +#define PFC_GPSR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0040U) +#define PFC_IP0SR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0060U) +#define PFC_IP1SR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0064U) +#define PFC_IP2SR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0068U) +#define PFC_IP3SR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x006CU) +#define PFC_DRV0CTRL5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0080U) +#define PFC_DRV1CTRL5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0084U) +#define PFC_DRV2CTRL5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0088U) +#define PFC_DRV3CTRL5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x008CU) +#define PFC_POC5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x00A0U) +#define PFC_PUEN5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x00C0U) +#define PFC_PUD5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x00E0U) +#define PFC_MOD_SEL5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0100U) +#define GPIO_IOINTSEL5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0180U) +#define GPIO_INOUTSEL5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0184U) +#define GPIO_OUTDT5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0188U) +#define GPIO_INDT5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x018CU) +#define GPIO_INTDT5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0190U) +#define GPIO_INTCLR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0194U) +#define GPIO_INTMSK5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x0198U) +#define GPIO_MSKCLR5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x019CU) +#define GPIO_POSNEG5 (PFC_MCU_BASE + PFC_PORT_GRP1 + 0x01A0U) +/* Port Group6 */ +#define PFC_PMMR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0000U) +#define PFC_GPSR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0040U) +#define PFC_IP0SR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0060U) +#define PFC_IP1SR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0064U) +#define PFC_IP2SR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0068U) +#define PFC_IP3SR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x006CU) +#define PFC_DRV0CTRL6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0080U) +#define PFC_DRV1CTRL6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0084U) +#define PFC_DRV2CTRL6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0088U) +#define PFC_DRV3CTRL6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x008CU) +#define PFC_POC6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x00A0U) +#define PFC_PUEN6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x00C0U) +#define PFC_PUD6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x00E0U) +#define PFC_MOD_SEL6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0100U) +#define GPIO_IOINTSEL6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0180U) +#define GPIO_INOUTSEL6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0184U) +#define GPIO_OUTDT6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0188U) +#define GPIO_INDT6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x018CU) +#define GPIO_INTDT6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0190U) +#define GPIO_INTCLR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0194U) +#define GPIO_INTMSK6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x0198U) +#define GPIO_MSKCLR6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x019CU) +#define GPIO_POSNEG6 (PFC_MCU_BASE + PFC_PORT_GRP2 + 0x01A0U) +/* Port Group7 */ +#define PFC_PMMR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0000U) +#define PFC_GPSR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0040U) +#define PFC_IP0SR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0060U) +#define PFC_IP1SR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0064U) +#define PFC_IP2SR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0068U) +#define PFC_IP3SR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x006CU) +#define PFC_DRV0CTRL7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0080U) +#define PFC_DRV1CTRL7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0084U) +#define PFC_DRV2CTRL7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0088U) +#define PFC_DRV3CTRL7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x008CU) +#define PFC_POC7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x00A0U) +#define PFC_PUEN7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x00C0U) +#define PFC_PUD7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x00E0U) +#define PFC_MOD_SEL7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0100U) +#define GPIO_IOINTSEL7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0180U) +#define GPIO_INOUTSEL7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0184U) +#define GPIO_OUTDT7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0188U) +#define GPIO_INDT7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x018CU) +#define GPIO_INTDT7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0190U) +#define GPIO_INTCLR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0194U) +#define GPIO_INTMSK7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x0198U) +#define GPIO_MSKCLR7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x019CU) +#define GPIO_POSNEG7 (PFC_MCU_BASE + PFC_PORT_GRP3 + 0x01A0U) +/* System Group0 */ +#define PFC_PMMR8 (PFC_BASE + PFC_SYS_GRP + 0x0000U) +#define PFC_GPSR8 (PFC_BASE + PFC_SYS_GRP + 0x0040U) +#define PFC_IP0SR8 (PFC_BASE + PFC_SYS_GRP + 0x0060U) +#define PFC_IP1SR8 (PFC_BASE + PFC_SYS_GRP + 0x0064U) +#define PFC_IP2SR8 (PFC_BASE + PFC_SYS_GRP + 0x0068U) +#define PFC_IP3SR8 (PFC_BASE + PFC_SYS_GRP + 0x006CU) +#define PFC_DRV0CTRL8 (PFC_BASE + PFC_SYS_GRP + 0x0080U) +#define PFC_DRV1CTRL8 (PFC_BASE + PFC_SYS_GRP + 0x0084U) +#define PFC_DRV2CTRL8 (PFC_BASE + PFC_SYS_GRP + 0x0088U) +#define PFC_DRV3CTRL8 (PFC_BASE + PFC_SYS_GRP + 0x008CU) +#define PFC_POC8 (PFC_BASE + PFC_SYS_GRP + 0x00A0U) +#define PFC_PUEN8 (PFC_BASE + PFC_SYS_GRP + 0x00C0U) +#define PFC_PUD8 (PFC_BASE + PFC_SYS_GRP + 0x00E0U) +#define PFC_MOD_SEL8 (PFC_BASE + PFC_SYS_GRP + 0x0100U) +#define GPIO_IOINTSEL8 (PFC_BASE + PFC_SYS_GRP + 0x0180U) +#define GPIO_INOUTSEL8 (PFC_BASE + PFC_SYS_GRP + 0x0184U) +#define GPIO_OUTDT8 (PFC_BASE + PFC_SYS_GRP + 0x0188U) +#define GPIO_INDT8 (PFC_BASE + PFC_SYS_GRP + 0x018CU) +#define GPIO_INTDT8 (PFC_BASE + PFC_SYS_GRP + 0x0190U) +#define GPIO_INTCLR8 (PFC_BASE + PFC_SYS_GRP + 0x0194U) +#define GPIO_INTMSK8 (PFC_BASE + PFC_SYS_GRP + 0x0198U) +#define GPIO_MSKCLR8 (PFC_BASE + PFC_SYS_GRP + 0x019CU) +#define GPIO_POSNEG8 (PFC_BASE + PFC_SYS_GRP + 0x01A0U) +/* System Group1 */ +#define PFC_PMMR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0000U) +#define PFC_GPSR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0040U) +#define PFC_IP0SR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0060U) +#define PFC_IP1SR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0064U) +#define PFC_IP2SR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0068U) +#define PFC_IP3SR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x006CU) +#define PFC_DRV0CTRL9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0080U) +#define PFC_DRV1CTRL9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0084U) +#define PFC_DRV2CTRL9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0088U) +#define PFC_DRV3CTRL9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x008CU) +#define PFC_POC9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x00A0U) +#define PFC_PUEN9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x00C0U) +#define PFC_PUD9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x00E0U) +#define PFC_MOD_SEL9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0100U) +#define GPIO_IOINTSEL9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0180U) +#define GPIO_INOUTSEL9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0184U) +#define GPIO_OUTDT9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0188U) +#define GPIO_INDT9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x018CU) +#define GPIO_INTDT9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0190U) +#define GPIO_INTCLR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0194U) +#define GPIO_INTMSK9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x0198U) +#define GPIO_MSKCLR9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x019CU) +#define GPIO_POSNEG9 (PFC_MCU_BASE + PFC_SYS_GRP + 0x01A0U) + +//V3M +#define PFC_IOCTRL30 0xE6060380 // R/W 32 MPOC control register 0 +#define PFC_IOCTRL31 0xE6060384 // R/W 32 MPOC control register 0 +#define PFC_IOCTRL32 0xE6060388 // R/W 32 MPOC control register 0 +#define PFC_IOCTRL40 0xE60603C0 // R/W 32 MPOC control register 0 + + +//RST +#if ACC_PROT_ENABLE == 0 +#define RST_MODEMR0 0xE6160000 // R 32 Mode Monitor Register +#define RST_MODEMR1 0xE6160004 // R 32 Mode Monitor Register2 +#else +/* Change to RGID2 when ACC_PROT_ENABLE ==1 */ +#define RST_MODEMR0 0x20E6160000 // R 32 Mode Monitor Register +#define RST_MODEMR1 0x20E6160004 // R 32 Mode Monitor Register2 +#endif /* ACC_PROT_ENABLE == 0 */ +#define RST_MODEMR 0xE6160060 // R 32 Mode Monitor Register +#define RST_CA57RESCNT 0xE6160040 // R/W 32 CA57 Reset Control Register +#define RST_CA53RESCNT 0xE6160044 // R/W 32 CA53 Reset Control Register +#define RST_WDTRSTCR 0xE6160054 // R/W 32 Watchdog Timer Reset Control Register +#define RST_RSTOUTCR 0xE6160058 // R/W 32 PRESETOUT# Control Register +#define RST_SBAR 0xE6160010 // R/W 32 SYS Boot Address Register +#define RST_SBAR2 0xE6160014 // R/W 32 SYS Boot Address Register2 +#define RST_CA53BAR 0xE6160030 // R/W 32 CA53 Boot Address Register +#define RST_CA53BAR2 0xE6160034 // R/W 32 CA53 Boot Address Register2 +#define RST_CA57BAR 0xE6160020 // R/W 32 CA57 Boot Address Register +#define RST_CA57BAR2 0xE6160024 // R/W 32 CA57 Boot Address Register2 +#define RST_CR7BAR 0xE6160070 // R/W 32 CR7 Boot Address Register +#define RST_CR7BAR2 0xE6160074 // R/W 32 CR7 Boot Address Register2 +#define RST_CA57CPU0BARH 0xE61600C0 // R/W 32 CA57 CPU0 Boot Address Register for 64-bit mode H +#define RST_CA57CPU0BARL 0xE61600C4 // R/W 32 CA57 CPU0 Boot Address Register for 64-bit mode L +#define RST_CA57CPU1BARH 0xE61600D0 // R/W 32 CA57 CPU1 Boot Address Register for 64-bit mode H +#define RST_CA57CPU1BARL 0xE61600D4 // R/W 32 CA57 CPU1 Boot Address Register for 64-bit mode L +#define RST_CA57CPU2BARH 0xE61600E0 // R/W 32 CA57 CPU2 Boot Address Register for 64-bit mode H +#define RST_CA57CPU2BARL 0xE61600E4 // R/W 32 CA57 CPU2 Boot Address Register for 64-bit mode L +#define RST_CA57CPU3BARH 0xE61600F0 // R/W 32 CA57 CPU3 Boot Address Register for 64-bit mode H +#define RST_CA57CPU3BARL 0xE61600F4 // R/W 32 CA57 CPU3 Boot Address Register for 64-bit mode L +#define RST_CA53CPU0BARH 0xE6160080 // R/W 32 CA53 CPU0 Boot Address Register for 64-bit mode H +#define RST_CA53CPU0BARL 0xE6160084 // R/W 32 CA53 CPU0 Boot Address Register for 64-bit mode L +#define RST_CA53CPU1BARH 0xE6160090 // R/W 32 CA53 CPU1 Boot Address Register for 64-bit mode H +#define RST_CA53CPU1BARL 0xE6160094 // R/W 32 CA53 CPU1 Boot Address Register for 64-bit mode L +#define RST_CA53CPU2BARH 0xE61600A0 // R/W 32 CA53 CPU2 Boot Address Register for 64-bit mode H +#define RST_CA53CPU2BARL 0xE61600A4 // R/W 32 CA53 CPU2 Boot Address Register for 64-bit mode L +#define RST_CA53CPU3BARH 0xE61600B0 // R/W 32 CA53 CPU3 Boot Address Register for 64-bit mode H +#define RST_CA53CPU3BARL 0xE61600B4 // R/W 32 CA53 CPU3 Boot Address Register for 64-bit mode L +#define RST_APBSFTYCHKR 0xE616005C // R/W 32 APB bus Safety Check Register +#define RST_STBCHR0 0xE6160100 // R/W 32 Standby Flag Register 0 +#define RST_STBCHR1 0xE6160104 // R/W 32 Standby Flag Register 1 +#define RST_STBCHR2 0xE6160108 // R/W 32 Standby Flag Register 2 +#define RST_STBCHR3 0xE616010C // R/W 32 Standby Flag Register 3 +#define RST_STBCHR4 0xE6160120 // R/W 32 Standby Flag Register 4 +#define RST_STBCHR5 0xE6160124 // R/W 32 Standby Flag Register 5 +#define RST_STBCHR6 0xE6160128 // R/W 32 Standby Flag Register 6 +#define RST_STBCHR7 0xE616012C // R/W 32 Standby Flag Register 7 +#define RST_SRESCR 0xE6160110 // R/W 32 Soft Power On Reset Control Register +#define RST_RRSTFR 0xE6160114 // R/W 32 RT Reset Flag Register +#define RST_SRSTFR 0xE6160118 // R/W 32 SYS Reset Flag Register +#define RST_SCPTCSR 0xE6160180 // R/W 32 Secure Protect Control/Status Register +#define RST_SCERMIDR 0xE6160184 // R 32 Secure Error Master ID Register +#define RST_SCERADR 0xE6160188 // R 32 Secure Error Address Register +#define RST_SAPTCSR 0xE6160190 // R/W 32 Safety Protect Control/Status Register +#define RST_SAERMIDR 0xE6160194 // R 32 Safety Error Master ID Register +#define RST_SAERADR 0xE6160198 // R 32 Safety Error Address Register + +#define MODEMR_BOOT_CPU_MASK (0x000000C0U) +#define MODEMR_BOOT_CPU_CR7 (0x000000C0U) +#define MODEMR_BOOT_CPU_CA57 (0x00000000U) +#define MODEMR_BOOT_CPU_CA53 (0x00000040U) +#define MODEMR_BOOT_DEV_MASK (0x0000001EU) +#define MODEMR_BOOT_DEV_HYPERFLASH160 (0x00000004U) +#define MODEMR_BOOT_DEV_HYPERFLASH80 (0x00000006U) +#define MODEMR_BOOT_DEV_QSPI_FLASH40 (0x00000008U) +#define MODEMR_BOOT_DEV_QSPI_FLASH80 (0x0000000CU) +#define MODEMR_BOOT_DEV_OCTAL_FLASH (0x0000000EU) +#define MODEMR_BOOT_DEV_EMMC_25X1 (0x0000000AU) +#define MODEMR_BOOT_DEV_EMMC_50X8 (0x0000001AU) +#define MODEMR_BOOT_DEV_SCIF_DOWNLOAD (0x0000001EU) +#define MODEMR_BOOT_DEV_USB_DOWNLOAD (0x0000001CU) +#define MODEMR_BOOT_PLL_MASK (0x00006000U) +#define MODEMR_BOOT_PLL_SHIFT (13U) + + +#define MD14_MD13_TYPE_0 U(0x0000) /* MD14=0 MD13=0 */ +#define MD14_MD13_TYPE_1 U(0x2000) /* MD14=0 MD13=1 */ +#define MD14_MD13_TYPE_2 U(0x4000) /* MD14=1 MD13=0 */ +#define MD14_MD13_TYPE_3 U(0x6000) /* MD14=1 MD13=1 */ + +#define MODEMR0_MD31_V3U (0x80000000U) +#define MODEMR1_MD32_V3U (0x00000001U) +#define MODEMR_SCIF_115200_V3U (0x00000000U) +#define MODEMR_SCIF_921600_V3U (0x80000000U) +#define MODEMR_SCIF_1843200_V3U (0x00000001U) +#define MODEMR_SCIF_3000000_V3U (0x80000001U) + +#define MODEMR0_MD31_GEN4 (0x80000000U) +#define MODEMR1_MD32_GEN4 (0x00000001U) +#define MODEMR_SCIF_115200_GEN4 (0x00000000U) +#define MODEMR_SCIF_921600_GEN4 (0x80000000U) +#define MODEMR_SCIF_1843200_GEN4 (0x00000001U) +#define MODEMR_SCIF_3000000_GEN4 (0x80000001U) + + +// +#define MFIS_SOFTMDR (0xE6260600U) + + +//SCIF0 +#define SCIF0_SCSMR 0xE6E60000 // R/W 16 Serial mode register +#define SCIF0_SCBRR 0xE6E60004 // R/W 8 Bit rate register +#define SCIF0_SCSCR 0xE6E60008 // R/W 16 Serial control register +#if ACC_PROT_ENABLE == 0 +#define SCIF0_SCFTDR 0xE6E6000C // W 8 Transmit FIFO data register +#define SCIF0_SCFSR 0xE6E60010 // R/W 16 Serial status register +#else +/* Change to RGID2 when ACC_PROT_ENABLE ==1 */ +#define SCIF0_SCFTDR 0x20E6E6000C // W 8 Transmit FIFO data register +#define SCIF0_SCFSR 0x20E6E60010 // R/W 16 Serial status register +#endif /* ACC_PROT_ENABLE == 0 */ +#define SCIF0_SCFRDR 0xE6E60014 // R 8 Receive FIFO data register +#define SCIF0_SCFCR 0xE6E60018 // R/W 16 FIFO control register +#define SCIF0_SCFDR 0xE6E6001C // R 16 FIFO data count register +#define SCIF0_SCSPTR 0xE6E60020 // R/W 16 Serial port register +#define SCIF0_SCLSR 0xE6E60024 // R/W 16 Line status register +#define SCIF0_DL 0xE6E60030 // R/W 16 Frequency division register +#define SCIF0_CKS 0xE6E60034 // R/W 16 Clock Select register + + +//SCIF2 +#define SCIF2_SCSMR 0xE6E88000 // R/W 16 Serial mode register +#define SCIF2_SCBRR 0xE6E88004 // R/W 8 Bit rate register +#define SCIF2_SCSCR 0xE6E88008 // R/W 16 Serial control register +#define SCIF2_SCFTDR 0xE6E8800C // W 8 Transmit FIFO data register +#define SCIF2_SCFSR 0xE6E88010 // R/W 16 Serial status register +#define SCIF2_SCFRDR 0xE6E88014 // R 8 Receive FIFO data register +#define SCIF2_SCFCR 0xE6E88018 // R/W 16 FIFO control register +#define SCIF2_SCFDR 0xE6E8801C // R 16 FIFO data count register +#define SCIF2_SCSPTR 0xE6E88020 // R/W 16 Serial port register +#define SCIF2_SCLSR 0xE6E88024 // R/W 16 Line status register +#define SCIF2_DL 0xE6E88030 // R/W 16 Frequency division register +#define SCIF2_CKS 0xE6E88034 // R/W 16 Clock Select register + +//SCIF3 +#if ACC_PROT_ENABLE == 0 +#define SCIF3_BASE (0xE6C50000) +#else +/* Change to RGID2 when ACC_PROT_ENABLE ==1 */ +#define SCIF3_BASE (0x20E6C50000) +#endif /* ACC_PROT_ENABLE == 0 */ +#define SCIF3_SCSMR (SCIF3_BASE + 0x0000U) // R/W 16 Serial mode register +#define SCIF3_SCBRR (SCIF3_BASE + 0x0004U) // R/W 8 Bit rate register +#define SCIF3_SCSCR (SCIF3_BASE + 0x0008U) // R/W 16 Serial control register +#define SCIF3_SCFTDR (SCIF3_BASE + 0x000CU) // W 8 Transmit FIFO data register +#define SCIF3_SCFSR (SCIF3_BASE + 0x0010U) // R/W 16 Serial status register +#define SCIF3_SCFRDR (SCIF3_BASE + 0x0014U) // R 8 Receive FIFO data register +#define SCIF3_SCFCR (SCIF3_BASE + 0x0018U) // R/W 16 FIFO control register +#define SCIF3_SCFDR (SCIF3_BASE + 0x001CU) // R 16 FIFO data count register +#define SCIF3_SCSPTR (SCIF3_BASE + 0x0020U) // R/W 16 Serial port register +#define SCIF3_SCLSR (SCIF3_BASE + 0x0024U) // R/W 16 Line status register +#define SCIF3_DL (SCIF3_BASE + 0x0030U) // R/W 16 Frequency division register +#define SCIF3_CKS (SCIF3_BASE + 0x0034U) // R/W 16 Clock Select register + +/* HSCIF0 */ +#define HSCIF0_HSSMR (0xE6540000U) // R/W 16 Serial mode register +#define HSCIF0_HSBRR (0xE6540004U) // R/W 8 Bit rate register +#define HSCIF0_HSSCR (0xE6540008U) // R/W 16 Serial control register +#if ACC_PROT_ENABLE == 0 +#define HSCIF0_HSFTDR (0xE654000CU) // W 8 Transmit FIFO data register +#define HSCIF0_HSFSR (0xE6540010U) // R/W 16 Serial status register +#else +/* Change to RGID2 when ACC_PROT_ENABLE ==1 */ +#define HSCIF0_HSFTDR (0x20E654000CU) // W 8 Transmit FIFO data register +#define HSCIF0_HSFSR (0x20E6540010U) // R/W 16 Serial status register +#endif /* ACC_PROT_ENABLE == 0 */ +#define HSCIF0_HSFRDR (0xE6540014U) // R 8 Receive FIFO data register +#define HSCIF0_HSFCR (0xE6540018U) // R/W 16 FIFO control register +#define HSCIF0_HSFDR (0xE654001CU) // R 16 FIFO data count register +#define HSCIF0_HSSPTR (0xE6540020U) // R/W 16 Serial port register +#define HSCIF0_HSLSR (0xE6540024U) // R/W 16 Line status register +#define HSCIF0_HSSRR (0xE6540040U) // R/W 16 Sampling rate register +/* BRG */ +#define HSCIF0_DL (0xE6540030U) // R/W 16 Frequency division register +#define HSCIF0_CKS (0xE6540034U) // R/W 16 Clock select register + + +/* Appendix A. */ +#if ACC_PROT_ENABLE == 0 +#define PRR (0xFFF00044) /* Product Register */ +#else +/* Change to RGID2 when ACC_PROT_ENABLE ==1 */ +#define PRR (0x20FFF00044) /* Product Register */ +#endif /* ACC_PROT_ENABLE == 0 */ +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) +#define PRR_PRODUCT_H3 (0x00004F00U) /* R-Car H3 */ +#define PRR_PRODUCT_M3 (0x00005200U) /* R-Car M3 */ +#define PRR_PRODUCT_M3N (0x00005500U) /* R-Car M3N */ +#define PRR_PRODUCT_E3 (0x00005700U) /* R-Car E3 */ +#define PRR_PRODUCT_D3 (0x00005800U) /* R-Car D3 */ +#define PRR_PRODUCT_V3M (0x00005400U) /* R-Car V3M */ +#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */ +#define PRR_PRODUCT_V3U (0x00005900U) /* R-Car V3U */ +#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */ +#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */ +#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */ +#define PRR_CUT_10 (0x00U) +#define PRR_CUT_11 (0x01U) +#define PRR_CUT_20 (0x10U) +#define PRR_CUT_30 (0x20U) +#define PRR_CUT_MAJOR_MASK (0x000000F0U) +#define PRR_CUT_MINOR_MASK (0x0000000FU) +#define PRR_PRODUCT_SHIFT (8U) +#define PRR_MAJOR_SHIFT (4U) +#define PRR_MINOR_SHIFT (0U) +#define PRR_MAJOR_OFFSET (1U) + +#endif /* REG_RCARGEN3_H */ diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv0.h b/IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv0.h new file mode 100644 index 0000000..31af5d2 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv0.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef SCIFDRV0_H +#define SCIFDRV0_H + +int32_t PutCharSCIF0(char outChar); +void PowerOnScif0(void); +void WaitPutScif0SendEnd(void); +void InitScif0_SCIFCLK(void); + +#endif /* SCIFDRV0_H */ diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv0_v3h.h b/IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv0_v3h.h new file mode 100644 index 0000000..152310b --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv0_v3h.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef SCIFDRV0_V3H_H +#define SCIFDRV0_V3H_H + +int32_t PutCharSCIF0_v3h(char outChar); +void PowerOnScif0_v3h(void); +void WaitPutScif0_v3h_SendEnd(void); +void InitScif0_v3h_SCIFCLK(void); + +#endif /* SCIFDRV0_V3H_H */ diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv2.h b/IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv2.h new file mode 100644 index 0000000..582caf2 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv2.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef SCIFDRV2_H +#define SCIFDRV2_H + +int32_t PutCharSCIF2(char outChar); +void PowerOnScif2(void); +void WaitPutScif2SendEnd(void); +void InitScif2_SCIFCLK(void); +void InitScif2_SCIFCLK_D3(void); + +#endif /* SCIFDRV2_H */ diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv3.h b/IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv3.h new file mode 100644 index 0000000..a5f74ad --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/scifdrv3.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2021, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef SCIFDRV3_H +#define SCIFDRV3_H + +#include + +int32_t PutCharSCIF3(char outChar); +int32_t GetCharSCIF3(char *inChar); +void PowerOnScif3(void); +void WaitPutScif3SendEnd(void); +void InitScif3_SCIFCLK(void); +void SetScif3_DL(uint16_t setData); +uint32_t SCIF3_TerminalInputCheck(char* str); +void pfc_reg_write(uintptr_t addr, uint32_t data); + +#endif /* SCIFDRV3_H */ diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/timer.h b/IPL/SDK/v4h/src/Dummy_CA76/include/timer.h new file mode 100644 index 0000000..9f6e291 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/timer.h @@ -0,0 +1,48 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : timer header + ******************************************************************************/ +/****************************************************************************** + * @file timer.h + * - Version : 0.01 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 19.09.2023 0.01 First Release + *****************************************************************************/ +#ifndef TIMER_H_ +#define TIMER_H_ + +#include + +/* Prototype */ +void generic_timer_init(void); +void micro_wait(uint64_t micro_sec); + +#endif /* TIMER_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/types.h b/IPL/SDK/v4h/src/Dummy_CA76/include/types.h new file mode 100644 index 0000000..c7f91b8 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/types.h @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#ifndef TYPES_H +#define TYPES_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include +/**************************************************************************** + * File Name: types.h + * Contents : Types Define + ****************************************************************************/ + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef SUCCESS +#define SUCCESS 0UL +#endif + +#ifndef YES +#define YES 1 +#endif + +#ifndef NO +#define NO 0 +#endif + +#ifndef NULL +#define NULL (void *)0UL +#endif + +#define PFAR /**/ +#define FFAR /**/ + +typedef signed char BYTE; +typedef signed short WORD; +typedef signed long DWORD; + +#if 0 +typedef unsigned long uint32; +typedef long int32; +typedef unsigned short uint16; +typedef short int16; +typedef unsigned char uint8; +typedef char int8; +typedef unsigned int uint; +typedef unsigned char bool8; +typedef unsigned long long uint64; + +typedef signed char int8_t; +typedef unsigned char uint8_t; +typedef signed short int16_t; +typedef unsigned short uint16_t; +typedef signed long int32_t; +typedef unsigned long uint32_t; +typedef unsigned long long int uint64_t; +#endif + +typedef signed char B; /* signed 8-bit integer */ +typedef long W; /* signed 32-bit integer */ +typedef unsigned char UB; /* unsigned 8-bit integer */ +typedef unsigned long UW; /* unsigned 32-bit integer */ + +typedef short H; /* signed 16-bit integer */ +typedef unsigned short UH; /* unsigned 16-bit integer */ + +typedef int INT; +typedef unsigned int UINT; + +typedef INT BOOL; + +typedef void (FFAR *FP)(); +typedef INT FN; +typedef INT ID; +typedef INT BOOL_ID; +typedef INT HNO; +typedef INT RNO; +typedef INT RDVNO; +typedef UINT RDVPTN; +typedef UINT ATR; +typedef UINT MODE; +typedef INT ER; +typedef INT PRI; +typedef ER ER_ID; +typedef UINT STAT; +typedef INT ER_UINT; +typedef UINT TEXPTN; +typedef UINT FLGPTN; +typedef UINT INHNO; +typedef UINT INTNO; + +typedef unsigned long SIZE; +typedef W TMO; +typedef W DLYTIME; +typedef DLYTIME RELTIM; +typedef void PFAR *VP; +typedef VP VP_INT; + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/IPL/SDK/v4h/src/Dummy_CA76/include/vmsatable.h b/IPL/SDK/v4h/src/Dummy_CA76/include/vmsatable.h new file mode 100644 index 0000000..cf1056f --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/include/vmsatable.h @@ -0,0 +1,12 @@ +/**********************************************************/ +/* Sample program : VMSA Table Header */ +/* File Name : vmsatable.h */ +/* Copyright (C) Renesas Electronics Corp. 2015. */ +/**********************************************************/ + +#ifndef _VMSATABLE_H_ +#define _VMSATABLE_H_ + +uint32_t SetVmsaTable(void); + +#endif diff --git a/IPL/SDK/v4h/src/Dummy_CA76/init_scif.c b/IPL/SDK/v4h/src/Dummy_CA76/init_scif.c new file mode 100644 index 0000000..26dae66 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/init_scif.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + + +#include "reg_rcargen3.h" +#include "common.h" +#include "scifdrv0.h" +#include "scifdrv3.h" +#include "init_scif.h" +#include "hscifdrv0.h" + + +void InitScif(void) +{ + uint32_t product; + uint32_t modemr0; + uint32_t modemr1; + + product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; + switch (product) { + case PRR_PRODUCT_S4: + modemr0 = *((volatile uint32_t*)RST_MODEMR0) & MODEMR0_MD31_GEN4; /* bit31 */ + modemr1 = *((volatile uint32_t*)RST_MODEMR1) & MODEMR1_MD32_GEN4; /* bit0 */ + switch (modemr0 | modemr1) { + case MODEMR_SCIF_115200_GEN4: /* 0x00000000 */ + InitScif3_SCIFCLK(); + break; + case MODEMR_SCIF_921600_GEN4: /* 0x80000000 */ + case MODEMR_SCIF_1843200_GEN4: /* 0x00000001 */ + case MODEMR_SCIF_3000000_GEN4: /* 0x80000001 */ + InitHscif0_SCIFCLK(); + break; + default: + break; + } + case PRR_PRODUCT_V4H: + case PRR_PRODUCT_V4M: + modemr0 = *((volatile uint32_t*)RST_MODEMR0) & MODEMR0_MD31_GEN4; /* bit31 */ + modemr1 = *((volatile uint32_t*)RST_MODEMR1) & MODEMR1_MD32_GEN4; /* bit0 */ + switch (modemr0 | modemr1) { + case MODEMR_SCIF_115200_GEN4: /* 0x00000000 */ + InitScif0_SCIFCLK(); + break; + case MODEMR_SCIF_921600_GEN4: /* 0x80000000 */ + case MODEMR_SCIF_1843200_GEN4: /* 0x00000001 */ + case MODEMR_SCIF_3000000_GEN4: /* 0x80000001 */ + InitHscif0_SCIFCLK(); + break; + default: + break; + } + default: + break; + } +} diff --git a/IPL/SDK/v4h/src/Dummy_CA76/main.c b/IPL/SDK/v4h/src/Dummy_CA76/main.c new file mode 100644 index 0000000..7201ec7 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/main.c @@ -0,0 +1,286 @@ +/* + * Copyright (c) 2018-2023 Renesas Electronics Corporation. All rights reserved. + */ + +#include +#include "common.h" +#include "main.h" +#include "devdrv.h" +#include "reg_rcargen3.h" +#include "d_armasm.h" +#include "timer.h" + +#define DUMMY_SECURE_MONITOR 1U +#define DUMMY_U_BOOT 2U +#define DUMMY_TEE 3U + +#define NORMAL_END (0U) +#define ERROR_END (1U) + +#define CL16MPHY (16660000U) + +/* Input Dummy Program waiting time (us) */ +#define WAIT_TIME_US (3000000U) + +uint64_t gErrDdrAdd; +uint32_t gErrDdrData; +uint32_t gTrueDdrData; + +static void StartMess(void); +static uint32_t CkExtendDdrRamCheck(void* ramAddr, uint64_t ramSize); +void bl2_init_generic_timer(void); +void rcar_set_log_time(void); + +extern const uint8_t __RO_START__[1]; +extern const uint8_t __STACKS_END__[1]; + +void Main(void) +{ + volatile uint32_t i; + uint32_t ret; + char str[64]; + uint32_t product; + +#if (DUMMY == DUMMY_SECURE_MONITOR) + /* Generic Timer initialization is performed at only once. */ + generic_timer_init(); +#endif /* (DUMMY == DUMMY_SECURE_MONITOR) */ + + micro_wait(WAIT_TIME_US); + + product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; + +#if DUMMY == DUMMY_U_BOOT + #if SDRAM_CHECK == 1 + #if DCACHE == 1 + DCacheEnable(); + #endif + /* 0x04_20000000 -- 0x04_FFFFFFFF */ + rcar_set_log_time(); + /* V4H DDR0 area: H'04_0000 0000 ~ H'04_7FFF FFFF (2 Gbytes) */ + /* V4H DDR1 area: H'04_8000 0000 ~ H'04_FFFF FFFF (2 Gbytes) */ + /* V4M DDR0 area: H'04_0000 0000 ~ H'04_FFFF FFFF (4 Gbytes) */ + PutStr("SDRAM verify test 0x04_20000000 -- 0x04_CCCCFFFF",1); + ret = CkExtendDdrRamCheck((void*)0x0420000000U, 0xACCD0000U); + if (ret != NORMAL_END) + { + rcar_set_log_time(); + PutStr("SDRAM verify NG",1); + rcar_set_log_time(); + PutStr("Error Address:0x",0); + Data2HexAscii_64(gErrDdrAdd,str,8); + PutStr(str,1); + rcar_set_log_time(); + PutStr("Error Data :0x",0); + Data2HexAscii(gErrDdrData,str,4); + PutStr(str,1); + rcar_set_log_time(); + PutStr("Expected Data :0x",0); + Data2HexAscii(gTrueDdrData,str,4); + PutStr(str,1); + } + else + { + rcar_set_log_time(); + PutStr("SDRAM verify OK",1); + } + + rcar_set_log_time(); + + if (product == PRR_PRODUCT_V4H) + { + /* V4H DDR2 area: H'06_0000 0000 ~ H'06_7FFF FFFF (2 Gbytes) */ + /* V4H DDR3 area: H'06_8000 0000 ~ H'06_FFFF FFFF (2 Gbytes) */ + PutStr("SDRAM verify test 0x06_00000000 -- 0x06_CCCCFFFF",1); + ret = CkExtendDdrRamCheck((void*)0x0600000000U, 0x00CCCD0000U); + } else { /* (product == PRR_PRODUCT_V4M) */ + /* V4M DDR1 area: H'05_0000 0000 ~ H'05_FFFF FFFF (4 Gbytes) */ + PutStr("SDRAM verify test 0x05_00000000 -- 0x05_CCCCFFFF",1); + ret = CkExtendDdrRamCheck((void*)0x0500000000U, 0x00CCCD0000U); + } + if (ret != NORMAL_END) + { + rcar_set_log_time(); + PutStr("SDRAM verify NG",1); + rcar_set_log_time(); + PutStr("Error Address:0x",0); + Data2HexAscii_64(gErrDdrAdd,str,8); + PutStr(str,1); + rcar_set_log_time(); + PutStr("Error Data :0x",0); + Data2HexAscii(gErrDdrData,str,4); + PutStr(str,1); + rcar_set_log_time(); + PutStr("Expected Data :0x",0); + Data2HexAscii(gTrueDdrData,str,4); + PutStr(str,1); + } + else + { + rcar_set_log_time(); + PutStr("SDRAM verify OK",1); + } + + #endif /* SDRAM_CHECK == 1 */ +#endif /* DUMMY == DUMMY_U_BOOT */ + + StartMess(); + +#if DUMMY == DUMMY_U_BOOT + while(1) { + __asm__ volatile ("wfi"); + } +#elif DUMMY == DUMMY_TEE + +#elif DUMMY == DUMMY_SECURE_MONITOR + +#endif + +} + + +static void StartMess(void) +{ +#if DUMMY == DUMMY_SECURE_MONITOR + PutStr(" ",1); + rcar_set_log_time(); + PutStr("Dummy Secure Monitor",1); + rcar_set_log_time(); + PutStr("Dummy Secure Monitor boot end",1); +#elif DUMMY == DUMMY_TEE + PutStr(" ",1); + rcar_set_log_time(); + PutStr("Dummy TEE",1); + rcar_set_log_time(); + PutStr("Dummy TEE boot end",1); +#else + PutStr(" ",1); + rcar_set_log_time(); + PutStr("Dummy U-Boot",1); + rcar_set_log_time(); + PutStr("Dummy U-Boot boot end",1); +#endif +} + +uint32_t CkExtendDdrRamCheck(void* ramAddr, uint64_t ramSize) +{ +//#ifdef COM_DDRCK_ON + + volatile uint64_t *read_adr; + uint64_t data; + uint32_t loop, i; + char str[64]; + + read_adr = (uintptr_t *)ramAddr; + + /* Write */ + data = 0x5A5A5A5A5A5A5A5A; + for (loop = 0; loop < ramSize/8; loop++) { + read_adr[loop] = data; + } + + /* Verify */ + data = 0x5A5A5A5A5A5A5A5A; + for (loop = 0; loop < ramSize/8; loop++) { + if (read_adr[loop] != data) { + gErrDdrAdd = (uintptr_t)&read_adr[loop]; + gErrDdrData = read_adr[loop]; + gTrueDdrData = data; + return(ERROR_END); + } + } + + /* Write */ + data = 0xA5A5A5A5A5A5A5A5; + for (loop = 0; loop < ramSize/8; loop++) { + read_adr[loop] = data; + } + + /* Verify */ + data = 0xA5A5A5A5A5A5A5A5; + for (loop = 0; loop < ramSize/8; loop++) { + if (read_adr[loop] != data) { + gErrDdrAdd = (uintptr_t)&read_adr[loop]; + gErrDdrData = read_adr[loop]; + gTrueDdrData = data; + return(ERROR_END); + } + } + + /* Write */ + data = 0x0123456789ABCDEF; + for (loop = 0; loop < ramSize/8; loop++) { + read_adr[loop] = data; + data += 0x1111111111111111; + } + + /* Verify */ + data = 0x0123456789ABCDEF; + for (loop = 0; loop < ramSize/8; loop++) { + if (read_adr[loop] != data) { + gErrDdrAdd = (uintptr_t)&read_adr[loop]; + gErrDdrData = read_adr[loop]; + gTrueDdrData = data; + return(ERROR_END); + } + data += 0x1111111111111111; + } + + return(NORMAL_END); +} + +void rcar_set_log_time(void) +{ + uint64_t now_time; + uint64_t freq; + uint64_t second; + uint64_t micro_sec; + uint64_t t_log[2][15]; + int32_t i; + int32_t start_counter; + + __asm__ volatile ("mrs %0, cntpct_el0" : "=r" (now_time)); + __asm__ volatile ("mrs %0, cntfrq_el0" : "=r" (freq)); + if (freq == 0U) { /* for zero division */ + second = 0U; + micro_sec = 0U; + } else { + second = now_time / freq; + micro_sec = ((now_time % freq) * 1000000U) / freq; + } + i = 14; /* counter initialize */ + do { + t_log[0][i] = second % 10U; + second = second / 10U; + i--; + } while (second != 0U); + for (; i >= 10; i--) { + t_log[0][i] = (int)' '; + } + start_counter = i + 1; + t_log[1][0] = micro_sec / 100000U; + micro_sec %= 100000U; + t_log[1][1] = micro_sec / 10000U; + micro_sec %= 10000U; + t_log[1][2] = micro_sec / 1000U; + micro_sec %= 1000U; + t_log[1][3] = micro_sec / 100U; + micro_sec %= 100U; + t_log[1][4] = micro_sec / 10U; + t_log[1][5] = micro_sec % 10U; + + (void)PutChar((int)'['); + for (i = start_counter; i < 15; i++) { + if (t_log[0][i] <= 9) { + (void)PutChar((int)((int)t_log[0][i] + (int)0x30)); + } else { + (void)PutChar((int)' '); + } + } + (void)PutChar((int)'.'); + for (i = 0; i < 6; i++) { + (void)PutChar((int)((int)t_log[1][i] + (int)0x30)); + } + (void)PutChar((int)']'); + (void)PutChar((int)' '); +} diff --git a/IPL/SDK/v4h/src/Dummy_CA76/makefile b/IPL/SDK/v4h/src/Dummy_CA76/makefile new file mode 100644 index 0000000..adf9f9a --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/makefile @@ -0,0 +1,234 @@ +# +# Copyright (c) 2020-2025 Renesas Electronics Corporation. All rights reserved. +# + +#/* Select BOOT("CR7"or"ICUMXA")************************* +ifeq ("$(BOOT)", "") +BOOT = ICUMXA +endif + +#/* Select dummy program(1:Secure Monitor/2:U-boot)************************* +ifeq ("$(DUMMY)", "1") +else + ifeq ("$(DUMMY)", "2") + DUMMY_FILE = 2 + else ifeq ("$(DUMMY)", "3") + DUMMY_FILE = 3 + else + DUMMY:=1 + endif +endif + +#/* Select AArch("64"or"32" )*************************************************** +ifeq ("$(AArch)", "") +AArch = 64 +endif + +#/* Select D-Cache(0:Disable/1:Enable)****************************************** +ifndef DCACHE +DCACHE := 0 +endif +$(eval $(call add_define,DCACHE)) + +ifndef SDRAM_CHECK +SDRAM_CHECK := 0 +endif +$(eval $(call add_define,SDRAM_CHECK)) + +ifndef ACC_PROT_ENABLE +ACC_PROT_ENABLE := 0 +endif +$(eval $(call add_define,ACC_PROT_ENABLE)) + +ifndef OPTEE_LOAD_ENABLE +OPTEE_LOAD_ENABLE := 1 +endif +$(eval $(call add_define,OPTEE_LOAD_ENABLE)) + +#CPU +ifeq ("$(AArch)", "64") +CPU = -march=armv8-a +endif +ifeq ("$(AArch)", "32") +CPU = -mcpu=cortex-r7 +endif + +ifeq ("$(AArch)", "32") + THUMB = -marm + AS_NEON = + CC_NEON = + ALIGN = -mno-unaligned-access +endif +ifeq ("$(AArch)", "64") + THUMB = + AS_NEON = + CC_NEON = -mgeneral-regs-only + ALIGN = -mstrict-align +endif + +ifeq ("$(AArch)", "32") + AArch32_64 = AArch32 + BOOTDIR = AArch32_boot + OUTPUT_DIR = AArch32_output + OBJECT_DIR = AArch32_obj + CROSS_COMPILE ?= arm-eabi- +endif +ifeq ("$(AArch)", "64") + AArch32_64 = AArch64 + BOOTDIR = AArch64_boot + OUTPUT_DIR = AArch64_output + OBJECT_DIR = AArch64_obj + CROSS_COMPILE ?= aarch64-elf- +endif + +ifeq ("$(BOOT)", "CR7") +# BOOT_DEF = Writer + MEMORY_DEF = memory_cr7.def + FILE_NAME = $(OUTPUT_DIR)/AArch$(AArch)_Dummy_CA76_Program$(FILENAME_ADD) +endif + +ifeq ("$(BOOT)", "ICUMXA") +# BOOT_DEF = Writer + ifeq ("$(DUMMY)", "2") + ifeq ("$(ACC_PROT_ENABLE)", "0") + MEMORY_DEF = memory_u_boot.def + else + MEMORY_DEF = memory_u_boot_rgid_on.def + endif + else ifeq ("$(DUMMY)", "3") + ifeq ("$(ACC_PROT_ENABLE)", "0") + ifeq ("$(OPTEE_LOAD_ENABLE)", "1") + MEMORY_DEF = memory_tee.def + else + $(error "Error:DUMMY=${DUMMY} && OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.") + endif + else + ifeq ("$(OPTEE_LOAD_ENABLE)", "1") + MEMORY_DEF = memory_tee_rgid_on.def + else + $(error "Error:DUMMY=${DUMMY} && OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.") + endif + endif + else + ifeq ("$(ACC_PROT_ENABLE)", "0") + MEMORY_DEF = memory_smon.def + else + MEMORY_DEF = memory_smon_rgid_on.def + endif + endif + FILE_NAME = $(OUTPUT_DIR)/AArch$(AArch)_Dummy_CA76_Program$(DUMMY_FILE)$(FILENAME_ADD) +endif + +LIBS = -L$(subst libc.a, ,$(shell $(CC) -print-file-name=libc.a 2> /dev/null)) -lc +LIBS += -L$(subst libgcc.a, ,$(shell $(CC) -print-libgcc-file-name 2> /dev/null)) -lgcc + +INCLUDE_DIR = include + +OUTPUT_FILE = $(FILE_NAME).axf + +#Object file +OBJ_FILE_BOOT = \ + $(OBJECT_DIR)/boot_mon.o \ + $(OBJECT_DIR)/stack.o + +SRC_FILE := \ + main.c \ + init_scif.c \ + hscifdrv0.c \ + scifdrv0.c \ + scifdrv3.c \ + devdrv.c \ + common.c \ + mem_io.c \ + generic_timer.c + +ifeq ("$(DCACHE)", "1") + OBJ_FILE_BOOT += $(OBJECT_DIR)/d_armasm.o + SRC_FILE += vmsatable.c +endif + +ifeq ("$(BOOT)", "WRITER_WITH_CERT") + SRC_FILE += cert_param.c +endif + +OBJ_FILE := $(addprefix $(OBJECT_DIR)/,$(patsubst %.c,%.o,$(SRC_FILE))) + +#Dependency File +DEPEND_FILE = $(patsubst %.lib, ,$(OBJ_FILE:%.o=%.d)) + +################################################### +#C compiler +CC = $(CROSS_COMPILE)gcc +#Assembler +AS = $(CROSS_COMPILE)as +#Linker +LD = $(CROSS_COMPILE)ld +#Liblary +AR = $(CROSS_COMPILE)ar +#Object dump +OBJDMP = $(CROSS_COMPILE)objdump +#Object copy +OBJCOPY = $(CROSS_COMPILE)objcopy + +#clean +CL = rm -rf + +################################################### +# Suffixes +.SUFFIXES : .s .c .o + +################################################### +# Command + +.PHONY: all +all: $(OBJECT_DIR) $(OUTPUT_DIR) $(OBJ_FILE_BOOT) $(OBJ_FILE) $(OUTPUT_FILE) + +#------------------------------------------ +# Make Directory +#------------------------------------------ +$(OBJECT_DIR): + -mkdir "$(OBJECT_DIR)" + +$(OUTPUT_DIR): + -mkdir "$(OUTPUT_DIR)" + +#------------------------------------------ +# Compile +#------------------------------------------ +$(OBJECT_DIR)/%.o:$(BOOTDIR)/%.s + $(AS) -g $(CPU) $(AS_NEON) --MD $(patsubst %.o,%.d,$@) -I $(BOOTDIR) -I $(INCLUDE_DIR) $< -o $@ --defsym $(AArch32_64)=0 --defsym DUMMY=$(DUMMY) --defsym ACC_PROT_ENABLE=$(ACC_PROT_ENABLE) --defsym OPTEE_LOAD_ENABLE=$(OPTEE_LOAD_ENABLE) + +$(OBJECT_DIR)/%.o:%.c + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + $(CC) -g -Os $(ALIGN) $(CPU) $(CC_NEON) $(THUMB) -MMD -MP -c -I $(BOOTDIR) -I $(INCLUDE_DIR) $< -o $@ -D$(AArch32_64)=0 -DDUMMY=$(DUMMY) -DSDRAM_CHECK=$(SDRAM_CHECK) -DDCACHE=$(DCACHE) $(CFLAGS) -DACC_PROT_ENABLE=$(ACC_PROT_ENABLE) -DOPTEE_LOAD_ENABLE=$(OPTEE_LOAD_ENABLE) + +#------------------------------------------ +# Linker +#------------------------------------------ +$(OUTPUT_FILE): $(OBJ_FILE_BOOT) $(OBJ_FILE) $(MEMORY_DEF) + $(LD) $(OBJ_FILE_BOOT) $(OBJ_FILE) \ + -T '$(MEMORY_DEF)' \ + -o '$(OUTPUT_FILE)' \ + -Map '$(FILE_NAME).map' \ + -static \ + $(LIBS) + +# Make SREC file + $(OBJCOPY) -O srec --srec-forceS3 "$(OUTPUT_FILE)" "$(FILE_NAME).srec" + +# Make Binary file + $(OBJCOPY) -O binary "$(OUTPUT_FILE)" "$(FILE_NAME).bin" + +# Dis assemble + $(OBJDMP) -d -S "$(OUTPUT_FILE)" > "$(FILE_NAME)_disasm.txt" + +# Time Stamp + @echo ========== %date% %time% ========== + @echo ========== !!! Compile Complete !!! ========== + + +.PHONY: clean +clean: + $(CL) $(OBJECT_DIR)/* $(OUTPUT_DIR)/* + +-include $(DEPEND_FILE) diff --git a/IPL/SDK/v4h/src/Dummy_CA76/mem_io.c b/IPL/SDK/v4h/src/Dummy_CA76/mem_io.c new file mode 100644 index 0000000..8d0bcfa --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/mem_io.c @@ -0,0 +1,74 @@ +/******************************************************************************* + * Copyright (c) 2018-2020 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : memory access driver + ******************************************************************************/ + +#include +#include + +void mem_write8(uintptr_t addr, uint8_t data) +{ + *(volatile uint8_t*)addr = data; +} +uint8_t mem_read8(uintptr_t addr) +{ + return (*(volatile uint8_t*)addr); +} + +void mem_write16(uintptr_t addr, uint16_t data) +{ + *(volatile uint16_t*)addr = data; +} +uint16_t mem_read16(uintptr_t addr) +{ + return (*(volatile uint16_t*)addr); +} + +void mem_write32(uintptr_t addr, uint32_t data) +{ + *(volatile uint32_t*)addr = data; +} +uint32_t mem_read32(uintptr_t addr) +{ + return (*(volatile uint32_t*)addr); +} + +void mem_write64(uintptr_t addr, uint64_t data) +{ + *(volatile uint64_t*)addr = data; +} + +void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set) +{ + mem_write32(addr, (mem_read32(addr) & ~clr) | set); +} void mem_bitset32(uintptr_t addr, uint32_t set) +{ + mem_write32(addr, (mem_read32(addr) | set) ); +} diff --git a/IPL/SDK/v4h/src/Dummy_CA76/memory_cr7.def b/IPL/SDK/v4h/src/Dummy_CA76/memory_cr7.def new file mode 100644 index 0000000..8a9297e --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/memory_cr7.def @@ -0,0 +1,38 @@ +MEMORY { + RAM (rwxa): ORIGIN = 0x44000000, LENGTH = 0x00014000 +} + +SECTIONS +{ + .text : { + *(.text*) + *(.rodata*) + . = NEXT(64); + __RO_END__ = .; + } > RAM + + .data : { + __DATA_START__ = .; + *(.data) + . = NEXT(64); + __DATA_END__ = .; + } > RAM + + __DATA_SIZE__ = SIZEOF(.data); + + .bss : { + __BSS_START__ = .; + *(.bss) + *(COMMON) + . = NEXT(64); + __BSS_END__ = .; + } > RAM + + stacks (NOLOAD) : ALIGN(64) { + __STACKS_START__ = .; + KEEP(*(writer_stack)) + __STACKS_END__ = .; + } > RAM + + __BSS_SIZE__ = SIZEOF(.bss); +} diff --git a/IPL/SDK/v4h/src/Dummy_CA76/memory_smon.def b/IPL/SDK/v4h/src/Dummy_CA76/memory_smon.def new file mode 100644 index 0000000..b6a8ff8 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/memory_smon.def @@ -0,0 +1,39 @@ +MEMORY { + RAM (rwxa): ORIGIN = 0x46400000, LENGTH = 0x00080000 +} + +SECTIONS +{ + .text : { + __RO_START__ = .; + *(.text*) + *(.rodata*) + . = NEXT(64); + __RO_END__ = .; + } > RAM + + .data : { + __DATA_START__ = .; + *(.data) + . = NEXT(64); + __DATA_END__ = .; + } > RAM + + __DATA_SIZE__ = SIZEOF(.data); + + .bss : { + __BSS_START__ = .; + *(.bss) + *(COMMON) + . = NEXT(64); + __BSS_END__ = .; + } > RAM + + stacks (NOLOAD) : ALIGN(64) { + __STACKS_START__ = .; + KEEP(*(writer_stack)) + __STACKS_END__ = .; + } > RAM + + __BSS_SIZE__ = SIZEOF(.bss); +} diff --git a/IPL/SDK/v4h/src/Dummy_CA76/memory_smon_rgid_on.def b/IPL/SDK/v4h/src/Dummy_CA76/memory_smon_rgid_on.def new file mode 100644 index 0000000..82cb1e5 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/memory_smon_rgid_on.def @@ -0,0 +1,39 @@ +MEMORY { + RAM (rwxa): ORIGIN = 0x2046400000, LENGTH = 0x00080000 +} + +SECTIONS +{ + .text : { + __RO_START__ = .; + *(.text*) + *(.rodata*) + . = NEXT(64); + __RO_END__ = .; + } > RAM + + .data : { + __DATA_START__ = .; + *(.data) + . = NEXT(64); + __DATA_END__ = .; + } > RAM + + __DATA_SIZE__ = SIZEOF(.data); + + .bss : { + __BSS_START__ = .; + *(.bss) + *(COMMON) + . = NEXT(64); + __BSS_END__ = .; + } > RAM + + stacks (NOLOAD) : ALIGN(64) { + __STACKS_START__ = .; + KEEP(*(writer_stack)) + __STACKS_END__ = .; + } > RAM + + __BSS_SIZE__ = SIZEOF(.bss); +} diff --git a/IPL/SDK/v4h/src/Dummy_CA76/memory_tee.def b/IPL/SDK/v4h/src/Dummy_CA76/memory_tee.def new file mode 100644 index 0000000..99c1668 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/memory_tee.def @@ -0,0 +1,43 @@ +MEMORY { + RAM (rwxa): ORIGIN = 0x44100000, LENGTH = 0x00100000 + MMU_CPU0 : ORIGIN = 0x50080000, LENGTH = 16K +} + +SECTIONS +{ + .text : { + __RO_START__ = .; + *(.text*) + *(.rodata*) + . = NEXT(64); + __RO_END__ = .; + } > RAM + + .data : { + __DATA_START__ = .; + *(.data) + . = NEXT(64); + __DATA_END__ = .; + } > RAM + + __DATA_SIZE__ = SIZEOF(.data); + + .bss : { + __BSS_START__ = .; + *(.bss) + *(COMMON) + . = NEXT(64); + __BSS_END__ = .; + } > RAM + + stacks (NOLOAD) : ALIGN(64) { + __STACKS_START__ = .; + KEEP(*(writer_stack)) + __STACKS_END__ = .; + } > RAM + + __BSS_SIZE__ = SIZEOF(.bss); +} + + MMU_BASE_CPU0 = ORIGIN(MMU_CPU0); + diff --git a/IPL/SDK/v4h/src/Dummy_CA76/memory_tee_rgid_on.def b/IPL/SDK/v4h/src/Dummy_CA76/memory_tee_rgid_on.def new file mode 100644 index 0000000..236d242 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/memory_tee_rgid_on.def @@ -0,0 +1,43 @@ +MEMORY { + RAM (rwxa): ORIGIN = 0x2044100000, LENGTH = 0x00100000 + MMU_CPU0 : ORIGIN = 0x2050080000, LENGTH = 16K +} + +SECTIONS +{ + .text : { + __RO_START__ = .; + *(.text*) + *(.rodata*) + . = NEXT(64); + __RO_END__ = .; + } > RAM + + .data : { + __DATA_START__ = .; + *(.data) + . = NEXT(64); + __DATA_END__ = .; + } > RAM + + __DATA_SIZE__ = SIZEOF(.data); + + .bss : { + __BSS_START__ = .; + *(.bss) + *(COMMON) + . = NEXT(64); + __BSS_END__ = .; + } > RAM + + stacks (NOLOAD) : ALIGN(64) { + __STACKS_START__ = .; + KEEP(*(writer_stack)) + __STACKS_END__ = .; + } > RAM + + __BSS_SIZE__ = SIZEOF(.bss); +} + + MMU_BASE_CPU0 = ORIGIN(MMU_CPU0); + diff --git a/IPL/SDK/v4h/src/Dummy_CA76/memory_u_boot.def b/IPL/SDK/v4h/src/Dummy_CA76/memory_u_boot.def new file mode 100644 index 0000000..8fe8548 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/memory_u_boot.def @@ -0,0 +1,43 @@ +MEMORY { + RAM (rwxa): ORIGIN = 0x50000000, LENGTH = 0x00100000 + MMU_CPU0 : ORIGIN = 0x50080000, LENGTH = 16K +} + +SECTIONS +{ + .text : { + __RO_START__ = .; + *(.text*) + *(.rodata*) + . = NEXT(64); + __RO_END__ = .; + } > RAM + + .data : { + __DATA_START__ = .; + *(.data) + . = NEXT(64); + __DATA_END__ = .; + } > RAM + + __DATA_SIZE__ = SIZEOF(.data); + + .bss : { + __BSS_START__ = .; + *(.bss) + *(COMMON) + . = NEXT(64); + __BSS_END__ = .; + } > RAM + + stacks (NOLOAD) : ALIGN(64) { + __STACKS_START__ = .; + KEEP(*(writer_stack)) + __STACKS_END__ = .; + } > RAM + + __BSS_SIZE__ = SIZEOF(.bss); +} + + MMU_BASE_CPU0 = ORIGIN(MMU_CPU0); + diff --git a/IPL/SDK/v4h/src/Dummy_CA76/memory_u_boot_rgid_on.def b/IPL/SDK/v4h/src/Dummy_CA76/memory_u_boot_rgid_on.def new file mode 100644 index 0000000..f0b5f77 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/memory_u_boot_rgid_on.def @@ -0,0 +1,43 @@ +MEMORY { + RAM (rwxa): ORIGIN = 0x2050000000, LENGTH = 0x00100000 + MMU_CPU0 : ORIGIN = 0x2050080000, LENGTH = 16K +} + +SECTIONS +{ + .text : { + __RO_START__ = .; + *(.text*) + *(.rodata*) + . = NEXT(64); + __RO_END__ = .; + } > RAM + + .data : { + __DATA_START__ = .; + *(.data) + . = NEXT(64); + __DATA_END__ = .; + } > RAM + + __DATA_SIZE__ = SIZEOF(.data); + + .bss : { + __BSS_START__ = .; + *(.bss) + *(COMMON) + . = NEXT(64); + __BSS_END__ = .; + } > RAM + + stacks (NOLOAD) : ALIGN(64) { + __STACKS_START__ = .; + KEEP(*(writer_stack)) + __STACKS_END__ = .; + } > RAM + + __BSS_SIZE__ = SIZEOF(.bss); +} + + MMU_BASE_CPU0 = ORIGIN(MMU_CPU0); + diff --git a/IPL/SDK/v4h/src/Dummy_CA76/scifdrv0.c b/IPL/SDK/v4h/src/Dummy_CA76/scifdrv0.c new file mode 100644 index 0000000..18de886 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/scifdrv0.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#include "common.h" +#include "scifdrv0.h" +#include "bit.h" +#include "reg_rcargen3.h" + + +////////////////////////////////////////////////////////////////////////////////// +// // +// Debug Seirial(SCIF0) // +// // +////////////////////////////////////////////////////////////////////////////////// +int32_t PutCharSCIF0(char outChar) +{ + while(!(0x60 & *((volatile uint16_t*)SCIF0_SCFSR) )); + *((volatile uint8_t*)SCIF0_SCFTDR) = outChar; + *((volatile uint16_t*)SCIF0_SCFSR) &= ~0x60; /* TEND,TDFE clear */ + return(0); +} + +void PowerOnScif0(void) +{ + uint32_t dataL; + + dataL = *((volatile uint32_t*)CPG_MSTPSR2); + if(dataL & BIT7){ // case SCIF0 + dataL &= ~BIT7; + *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; + *((volatile uint32_t*)CPG_MSTPCR2) = dataL; + while( BIT7 & *((volatile uint32_t*)CPG_MSTPSR2) ); // wait bit=0 + } +} + +void WaitPutScif0SendEnd(void) +{ + uint16_t dataW; + uint32_t loop; + + loop=1; + while(loop){ + dataW = *((volatile uint16_t*)SCIF0_SCFSR); + if(dataW & BIT6) loop = 0; + } +} + +void InitScif0PinFunction(void) +{ + uint32_t dataL; + + /* SCIF0 */ + dataL = *((volatile uint32_t*)PFC_IP3SR7); + dataL &= ~(0x0FF00000); + dataL |= 0x04400000; /* IPSR7[27:24]=4'b0100, IPSR7[23:20]=4'b0100 */ + *((volatile uint32_t*)PFC_IP3SR7) = ~dataL; + *((volatile uint32_t*)PFC_IP3SR7) = dataL; + + dataL = *((volatile uint32_t*)PFC_GPSR4); + dataL |= 0x00000030; /* GPSR4[5],GPSR4[4] */ + *((volatile uint32_t*)PFC_IP3SR7) = ~dataL; + *((volatile uint32_t*)PFC_GPSR4) = dataL; +} + +void InitScif0_SCIFCLK(void) +{ + uint16_t dataW; + + PowerOnScif0(); + + InitScif0PinFunction(); + + dataW = *((volatile uint16_t*)SCIF0_SCLSR); /* dummy read */ + *((volatile uint16_t*)SCIF0_SCLSR) = 0x0000; /* clear ORER bit */ + *((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear all error bit */ + + *((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/ + *((volatile uint16_t*)SCIF0_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */ + *((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */ + + *((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */ + *((volatile uint16_t*)SCIF0_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, Po/1 */ + SoftDelay(100); + *((volatile uint8_t*)SCIF0_SCBRR) = 0x11; /* 115200bps@66MHz */ + SoftDelay(100); + *((volatile uint16_t*)SCIF0_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */ + *((volatile uint16_t*)SCIF0_SCSCR) = 0x0030; /* enable TE, RE; SC_CLK=input */ + + SoftDelay(100); +} diff --git a/IPL/SDK/v4h/src/Dummy_CA76/scifdrv0_v3h.c b/IPL/SDK/v4h/src/Dummy_CA76/scifdrv0_v3h.c new file mode 100644 index 0000000..aa3d2af --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/scifdrv0_v3h.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#include "common.h" +#include "scifdrv0.h" +#include "bit.h" +#include "reg_rcargen3.h" + + +////////////////////////////////////////////////////////////////////////////////// +// // +// Debug Seirial(SCIF0) // +// // +////////////////////////////////////////////////////////////////////////////////// +int32_t PutCharSCIF0_v3h(char outChar) +{ + while(!(0x60 & *((volatile uint16_t*)SCIF0_SCFSR) )); + *((volatile uint8_t*)SCIF0_SCFTDR) = outChar; + *((volatile uint16_t*)SCIF0_SCFSR) &= ~0x60; /* TEND,TDFE clear */ + return(0); +} + +void PowerOnScif0_v3h(void) +{ + uint32_t dataL; + + dataL = *((volatile uint32_t*)CPG_MSTPSR2); + if(dataL & BIT7){ // case SCIF0 + dataL &= ~BIT7; + *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; + *((volatile uint32_t*)CPG_SMSTPCR2) = dataL; + while( BIT7 & *((volatile uint32_t*)CPG_MSTPSR2) ); // wait bit=0 + } +} + +void WaitPutScif0_v3h_SendEnd(void) +{ + uint16_t dataW; + uint32_t loop; + + loop=1; + while(loop){ + dataW = *((volatile uint16_t*)SCIF0_SCFSR); + if(dataW & BIT6) loop = 0; + } +} + +void InitScif0_v3h_PinFunction(void) +{ + uint32_t dataL; + + /* SCIF0 */ + dataL = *((volatile uint32_t*)PFC_IPSR7); + dataL &= ~(0x0FF00000); + dataL |= 0x04400000; /* IPSR7[27:24]=4'b0100, IPSR7[23:20]=4'b0100 */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_IPSR7) = dataL; + + dataL = *((volatile uint32_t*)PFC_GPSR4); + dataL |= 0x00000030; /* GPSR4[5],GPSR4[4] */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_GPSR4) = dataL; +} + +void InitScif0_v3h_SCIFCLK(void) +{ + uint16_t dataW; + + PowerOnScif0_v3h(); + + InitScif0_v3h_PinFunction(); + + dataW = *((volatile uint16_t*)SCIF0_SCLSR); /* dummy read */ + *((volatile uint16_t*)SCIF0_SCLSR) = 0x0000; /* clear ORER bit */ + *((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear all error bit */ + + *((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/ + *((volatile uint16_t*)SCIF0_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */ + *((volatile uint16_t*)SCIF0_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */ + + *((volatile uint16_t*)SCIF0_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */ + *((volatile uint16_t*)SCIF0_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, Po/1 */ + SoftDelay(100); + *((volatile uint8_t*)SCIF0_SCBRR) = 0x11; /* 115200bps@66MHz */ + SoftDelay(100); + *((volatile uint16_t*)SCIF0_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */ + *((volatile uint16_t*)SCIF0_SCSCR) = 0x0030; /* enable TE, RE; SC_CLK=input */ + + SoftDelay(100); +} diff --git a/IPL/SDK/v4h/src/Dummy_CA76/scifdrv2.c b/IPL/SDK/v4h/src/Dummy_CA76/scifdrv2.c new file mode 100644 index 0000000..6e087dd --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/scifdrv2.c @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + */ + +#include "common.h" +#include "scifdrv2.h" +#include "bit.h" +#include "reg_rcargen3.h" + + +////////////////////////////////////////////////////////////////////////////////// +// // +// Debug Seirial(SCIF2) // +// // +////////////////////////////////////////////////////////////////////////////////// +int32_t PutCharSCIF2(char outChar) +{ + while(!(0x60 & *((volatile uint16_t*)SCIF2_SCFSR) )); + *((volatile unsigned char*)SCIF2_SCFTDR) = outChar; + *((volatile uint16_t*)SCIF2_SCFSR) &= ~0x60; /* TEND,TDFE clear */ + return(0); +} + +void PowerOnScif2(void) +{ + uint32_t dataL; + + dataL = *((volatile uint32_t*)CPG_MSTPSR3); + if(dataL & BIT10){ // case SCIF2(IrDA) Standby + dataL &= ~BIT10; + *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; + *((volatile uint32_t*)CPG_SMSTPCR3) = dataL; + while( BIT10 & *((volatile uint32_t*)CPG_MSTPSR3) ); // wait bit=0 + } +} + +void WaitPutScif2SendEnd(void) +{ + uint16_t dataW; + uint32_t loop; + + loop=1; + while(loop){ + dataW = *((volatile uint16_t*)SCIF2_SCFSR); + if(dataW & BIT6) loop = 0; + } +} + +void InitScif2PinFunction(void) +{ + uint32_t dataL; + + /* SCIF2 */ + dataL = *((volatile uint32_t*)PFC_IPSR13); + dataL &= ~0x000000FF; /* IP13[7:4]=4'b0000, IP13[3:0]=4'b0000 */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_IPSR13) = dataL; + + dataL = *((volatile uint32_t*)PFC_GPSR5); + dataL |= 0x00000C00; /* GP5[11],GP5[10] */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_GPSR5) = dataL; +} + +void InitScif2_SCIFCLK(void) +{ + uint16_t dataW; + uint32_t prr; + + PowerOnScif2(); + + InitScif2PinFunction(); + + dataW = *((volatile uint16_t*)SCIF2_SCLSR); /* dummy read */ + *((volatile uint16_t*)SCIF2_SCLSR) = 0x0000; /* clear ORER bit */ + *((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear all error bit */ + + *((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/ + *((volatile uint16_t*)SCIF2_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */ + *((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */ + + *((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */ + *((volatile uint16_t*)SCIF2_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, Po/1 */ + SoftDelay(100); + +#ifdef Writer + *((volatile uint8_t*)SCIF2_SCBRR) = 0x11; /* 115200bps@66MHz */ +#else /* Writer */ + prr = *((volatile uint32_t*)PRR); + prr &= (PRR_PRODUCT_MASK | PRR_CUT_MASK); + + if (prr == PRR_PRODUCT_H3 | PRR_CUT_10) { + *((volatile uint8_t*)SCIF2_SCBRR) = 0x08; /* 115200bps@33MHz */ + } else { + *((volatile uint8_t*)SCIF2_SCBRR) = 0x11; /* 115200bps@66MHz */ + } +#endif /* Writer */ + + SoftDelay(100); + *((volatile uint16_t*)SCIF2_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */ + *((volatile uint16_t*)SCIF2_SCSCR) = 0x0030; /* enable TE, RE; SC_CLK=input */ + + SoftDelay(100); +} + +void InitScif2PinFunction_D3(void) +{ + uint32_t dataL; + + /* SCIF2 */ + dataL = *((volatile uint32_t*)PFC_IPSR12); + dataL &= ~0x00000F00U; /* IP12[11:8]=4'b0000 */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_IPSR12) = dataL; + + dataL = *((volatile uint32_t*)PFC_GPSR4); + dataL |= 0x0C000000U; /* GP4[27],GP4[26] */ + *((volatile uint32_t*)PFC_PMMR) = ~dataL; + *((volatile uint32_t*)PFC_GPSR4) = dataL; + +} + +void InitScif2_SCIFCLK_D3(void) +{ + uint16_t dataW; + uint32_t md; + uint32_t sscg; + + PowerOnScif2(); + + InitScif2PinFunction_D3(); + + md = *((volatile uint32_t*)RST_MODEMR); + sscg = (md & 0x00001000) >> 12; + + dataW = *((volatile uint16_t*)SCIF2_SCLSR); /* dummy read */ + *((volatile uint16_t*)SCIF2_SCLSR) = 0x0000; /* clear ORER bit */ + *((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear all error bit */ + + *((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* clear SCR.TE & SCR.RE*/ + *((volatile uint16_t*)SCIF2_SCFCR) = 0x0006; /* reset tx-fifo, reset rx-fifo. */ + *((volatile uint16_t*)SCIF2_SCFSR) = 0x0000; /* clear ER, TEND, TDFE, BRK, RDF, DR */ + + *((volatile uint16_t*)SCIF2_SCSCR) = 0x0000; /* internal clock, SC_CLK pin used for input pin */ + *((volatile uint16_t*)SCIF2_SCSMR) = 0x0000; /* 8bit data, no-parity, 1 stop, S3D4/1 */ + SoftDelay(100); + + if(sscg == 0x0){ //MD12=0 (SSCG off) : S3D4C=66.6MHz + *((volatile uint8_t*)SCIF2_SCBRR) = 0x11; /* 115200 bit-rate */ + } + else if(sscg == 0x1){ //MD12=1 (SSCG on) : S3D4C=62.5MHz + *((volatile uint8_t*)SCIF2_SCBRR) = 0x10; /* 115200 bit-rate */ + } + SoftDelay(100); + *((volatile uint16_t*)SCIF2_SCFCR) = 0x0000; /* reset-off tx-fifo, rx-fifo. */ + *((volatile uint16_t*)SCIF2_SCSCR) = 0x0030; /* enable TE, RE; SCK pin is not used */ + SoftDelay(100); +} diff --git a/IPL/SDK/v4h/src/Dummy_CA76/scifdrv3.c b/IPL/SDK/v4h/src/Dummy_CA76/scifdrv3.c new file mode 100644 index 0000000..788318c --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/scifdrv3.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2021, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "common.h" +#include "scifdrv3.h" +#include "bit.h" +#include "reg_rcargen3.h" +#include "mem_io.h" + +/* Pin function setting value */ +#define POC_TX ((uint32_t)1U << 3U) /* TX3 */ +#define POC_RX ((uint32_t)1U << 2U) /* RX3 */ +#define GPSR_TX ((uint32_t)1U << 3U) /* TX3 */ +#define GPSR_RX ((uint32_t)1U << 2U) /* RX3 */ +#define POC_TX_33V ((uint32_t)1U << 3U) /* TX3 3.3V setting value */ +#define POC_RX_33V ((uint32_t)1U << 2U) /* RX3 3.3V setting value */ +#define POC_TX_18V ((uint32_t)0U << 3U) /* TX3 1.8V setting value */ +#define POC_RX_18V ((uint32_t)0U << 2U) /* RX3 1.8V setting value */ +#define IPSR_RX_VAL ((uint32_t)1U << 8U) /* RX3 */ +#define IPSR_TX_VAL ((uint32_t)1U << 12U) /* TX3 */ +#define IPSR_RX_MASK ((uint32_t)0xFU << 8U) /* IPSR bit[11:8] */ +#define IPSR_TX_MASK ((uint32_t)0xFU << 12U) /* IPSR bit[15:12] */ +#define PFC_POC_SCIF_MASK (uint32_t)(0x0000000CU) /* SCIF3 RX/TX */ +#define PFC_POC_SCIF_18V (uint32_t)(POC_TX_18V | POC_RX_18V) /* SCIF3 RX/TX */ +#define PFC_POC_SCIF_33V (uint32_t)(POC_TX_33V | POC_RX_33V) /* SCIF3 RX/TX */ +#define PFC_GPSR_SCIF_MASK (uint32_t)(0x0000000CU) /* SCIF3 RX/TX */ +#define PFC_GPSR_SCIF_VAL (uint32_t)(GPSR_TX | GPSR_RX) /* SCIF3 RX/TX */ +#define PFC_IPSR_SCIF_MASK (uint32_t)(IPSR_RX_MASK | IPSR_TX_MASK) /* Mask value of IPSR (SCIF3 RX/TX) */ +#define PFC_IPSR_SCIF_VAL (uint32_t)(IPSR_RX_VAL | IPSR_TX_VAL) /* SCIF3 RX/TX */ + +/********************************************************************************/ +/* */ +/* Debug Seirial(SCIF3) */ +/* */ +/********************************************************************************/ +int32_t PutCharSCIF3(char outChar) +{ + while(!(0x60U & *((volatile uint16_t*)SCIF3_SCFSR) )); + *((volatile uint8_t*)SCIF3_SCFTDR) = outChar; + *((volatile uint16_t*)SCIF3_SCFSR) &= ~0x60U; /* TEND,TDFE clear */ + return(0); +} + +int32_t GetCharSCIF3(char *inChar) +{ + do{ + if(0x91U & *((volatile uint16_t *)SCIF3_SCFSR)) + *((volatile uint16_t *)SCIF3_SCFSR) &= ~0x91U; + if(0x01U & *((volatile uint16_t *)SCIF3_SCLSR)) + { + PutStr("ORER",1U); + *((volatile uint16_t *)SCIF3_SCLSR) &= ~0x01U; + } + }while( !(0x02U & *((volatile uint16_t *)SCIF3_SCFSR)) ); + *inChar = *((volatile char*)SCIF3_SCFRDR); + *((volatile uint16_t*)SCIF3_SCFSR) &= ~0x02U; + return(0); +} + +void PowerOnSCIF3(void) +{ + uint32_t dataL; + + dataL = *((volatile uint32_t*)CPG_MSTPSR7); + if(dataL & BIT4){ + dataL &= ~BIT4; + *((volatile uint32_t*)CPG_CPGWPR) = ~dataL; + *((volatile uint32_t*)CPG_MSTPCR7) = dataL; + } +} + +void WaitPutScif3SendEnd(void) +{ + uint16_t dataW; + uint32_t loop; + + loop=1U; + while(loop){ + dataW = *((volatile uint16_t*)SCIF3_SCFSR); + if(dataW & BIT6) { + loop = 0U; + } + } +} + +static void InitScif3PinFunction(void) +{ + uint32_t dataL; + + /* Set Voltage setting to 3.3V */ + dataL = mem_read32(PFC_POC0); + dataL &= ~(PFC_POC_SCIF_MASK); + dataL |= PFC_POC_SCIF_33V; + pfc_reg_write(PFC_POC0, dataL); + + /* Set RX / TX of SCIF3 */ + dataL = mem_read32(PFC_IP0SR0); + dataL &= ~(PFC_IPSR_SCIF_MASK); + dataL |= PFC_IPSR_SCIF_VAL; + pfc_reg_write(PFC_IP0SR0, dataL); + + dataL = mem_read32(PFC_GPSR0); + dataL &= ~(PFC_GPSR_SCIF_MASK); + dataL |= PFC_GPSR_SCIF_VAL; + pfc_reg_write(PFC_GPSR0, dataL); +} + +void InitScif3_SCIFCLK(void) +{ + PowerOnSCIF3(); + + InitScif3PinFunction(); + + (void)(*((volatile uint16_t*)SCIF3_SCLSR)); /* dummy read */ + *((volatile uint16_t*)SCIF3_SCLSR) = 0x0000U; /* clear ORER bit */ + *((volatile uint16_t*)SCIF3_SCFSR) = 0x0000U; /* clear all error bit */ + + *((volatile uint16_t*)SCIF3_SCSCR) = 0x0000U; /* clear SCR.TE & SCR.RE*/ + *((volatile uint16_t*)SCIF3_SCFCR) = 0x0006U; /* reset tx-fifo, reset rx-fifo. */ + *((volatile uint16_t*)SCIF3_SCFSR) = 0x0000U; /* clear ER, TEND, TDFE, BRK, RDF, DR */ + + *((volatile uint16_t*)SCIF3_SCSCR) = 0x0002U; /* external clock, SC_CLK pin used for input pin */ + *((volatile uint16_t*)SCIF3_SCSMR) = 0x0000U; /* 8bit data, no-parity, 1 stop, S3D4/1 */ + SoftDelay(100U); + *((volatile uint16_t*)SCIF3_DL) = 0x0091U; /* 266.66MHz / (115200*16) = 144.67 */ + *((volatile uint16_t*)SCIF3_CKS) = 0x4000U; /* select S3D1-Clock */ + SoftDelay(100U); + *((volatile uint16_t*)SCIF3_SCFCR) = 0x0000U; /* reset-off tx-fifo, rx-fifo. */ + *((volatile uint16_t*)SCIF3_SCSCR) = 0x0032U; /* enable TE, RE; SCK SC_CLK=input */ + + SoftDelay(100U); +} + +void SetScif3_DL(uint16_t setData) +{ + *((volatile uint16_t*)SCIF3_DL) = setData; +} + +uint32_t SCIF3_TerminalInputCheck(char* str) +{ + char result = 0; + + if(0x91U & *((volatile uint16_t *)SCIF3_SCFSR)) + *((volatile uint16_t *)SCIF3_SCFSR) &= ~0x91U; + if(0x01U & *((volatile uint16_t *)SCIF3_SCLSR)) + { + PutStr("ORER",1U); + *((volatile uint16_t *)SCIF3_SCLSR) &= ~0x01U; + } + if(0x02 & *((volatile uint16_t *)SCIF3_SCFSR)) + { + *str = *((volatile unsigned char*)SCIF3_SCFRDR); + *((volatile uint16_t*)SCIF3_SCFSR) &= ~0x02U; + result = 1U; + } + return result; +} + +void pfc_reg_write(uintptr_t addr, uint32_t data) +{ + mem_write32(PFC_PMMR(addr), ~data); + mem_write32(addr, data); +} + diff --git a/IPL/SDK/v4h/src/Dummy_CA76/vmsatable.c b/IPL/SDK/v4h/src/Dummy_CA76/vmsatable.c new file mode 100644 index 0000000..0b17ae1 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_CA76/vmsatable.c @@ -0,0 +1,283 @@ +/**********************************************************/ +/* Sample program : VMSA Table Generate */ +/* File Name : vmsatable.c */ +/* Copyright (C) Renesas Electronics Corp. 2015. */ +/**********************************************************/ + +#include "common.h" +#include "vmsatable.h" +#include "d_armasm.h" + +#ifdef AArch64 +extern const char MMU_BASE_CPU0[]; +#endif +#ifdef AArch32 +#define MMU_BASE_CPU0 0xE6300000 +#endif + +#define TBL_SIZE 4096 +#define TBL_NUM (TBL_SIZE/8) + +#define Lvl1VmsaTbl ((uintptr_t)MMU_BASE_CPU0+0x0000) // +0kB +#define Lvl2VmsaTbl ((uintptr_t)MMU_BASE_CPU0+0x1000) // +4kB +#define Lvl3VmsaTbl ((uintptr_t)MMU_BASE_CPU0+0x2000) // +8kB + +#define Lvl1StartAddr (0x0000000000) +#define Lvl1BlockSize (0x0040000000) // 1GB +#define Lvl1BlockShift (30) // BIT30 +#define Lvl2StartAddr (0x00C0000000) +#define Lvl2BlockSize (0x0000200000) // 2MB +#define Lvl2BlockShift (21) // BIT21 +#define Lvl3StartAddr (0x00E6200000) +#define Lvl3BlockSize (0x0000001000) // 4KB +#define Lvl3BlockShift (12) // BIT12 + +#define BIT47_12 0x0000FFFFFFFFF000 + +typedef struct vmsaTable{ + uint64_t vAddr; + uint64_t pAddr; + uint64_t unit; + uint64_t upperAttr; + uint64_t lowerAttr; +}vmsaTable; + + +//------------------------------------------------------------------ +// Referenced: DDI0487A_f_armv8_arm.pdf +// D4.4 VMSAv8-64 translation table format descriptors +//------------------------------------------------------------------ + +#define ATTR_TBL 0x444444FF0C080400 // MAIR_EL1 +// // [63:56]Attr7=0x44 : ----------------- (Blank) +// // [55:48]Attr6=0x44 : ----------------- (Blank) +// // [47:40]Attr5=0x44 : NORMAL_NON_CACHEABLE Normal Memory Non-Cacheable +// // [39:32]Attr4=0x77 : NORMAL_WRITE_BACK Normal Memory Write-back transient +// // [31:24]Attr3=0x0C : DEVICE_GRE_MEM Device-GRE memory +// // [23:16]Attr2=0x08 : DEVICE_NGRE_MEM Device-nGRE memory +// // [15: 8]Attr1=0x04 : DEVICE_NGNRE_MEM Device-nGnRE memory +// // [ 7: 0]Attr0=0x00 : DEVICE_NGNRNE_MEM Device-nGnRnE memory + +// CPU0 VMSA table Level1 (4kB) +// Virtual address == Physical Address +const vmsaTable ArmVmsaTblLvl1Cpu0ForDDR4ch[] = { + // [MEM]Memory Address ...BIT[1:0]=01 + // [TBL]Next Level Table Address ...BIT[1:0]=11 + // Virtual Address Physical Address BLOCK Upper Lower Attr + // (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0] + // Next Level Table (1GBxN) [63:52] [11:00] [1:0][2:1] [2:0] + { 0x0000000000, 0x0000000000, 1, 0x000, 0x411 }, // [MEM]CS0/1,PCIe 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x0040000000, 0x0040000000, 1, 0x000, 0x411 }, // [MEM]DRAM 1st 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x0080000000, 0x0080000000, 1, 0x000, 0x411 }, // [MEM]DRAM 2nd 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x00C0000000, Lvl2VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 1GB 0 0 00 00 0 000 11 (Next Level Table) + { 0x0400000000, 0x0400000000, 4, 0x000, 0x411 }, // [MEM]DDR0 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient) + { 0x0500000000, 0x0500000000, 4, 0x000, 0x411 }, // [MEM]DDR1 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient) + { 0x0600000000, 0x0600000000, 4, 0x000, 0x411 }, // [MEM]DDR2 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient) + { 0x0700000000, 0x0700000000, 4, 0x000, 0x411 }, // [MEM]DDR3 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient) + { 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ---------- +}; + +// CPU0 VMSA table Level1 (4kB) +// Virtual address == Physical Address +const vmsaTable ArmVmsaTblLvl1Cpu0ForDDR2ch[] = { + // [MEM]Memory Address ...BIT[1:0]=01 + // [TBL]Next Level Table Address ...BIT[1:0]=11 + // Virtual Address Physical Address BLOCK Upper Lower Attr + // (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0] + // Next Level Table (1GBxN) [63:52] [11:00] [1:0][2:1] [2:0] + { 0x0000000000, 0x0000000000, 1, 0x000, 0x411 }, // [MEM]CS0/1,PCIe 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x0040000000, 0x0040000000, 1, 0x000, 0x411 }, // [MEM]DRAM 1st 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x0080000000, 0x0080000000, 1, 0x000, 0x411 }, // [MEM]DRAM 2nd 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x00C0000000, Lvl2VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 1GB 0 0 00 00 0 000 11 (Next Level Table) + { 0x0400000000, 0x0400000000, 4, 0x000, 0x411 }, // [MEM]DDR0 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient) + { 0x0600000000, 0x0600000000, 4, 0x000, 0x411 }, // [MEM]DDR2 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient) + { 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ---------- +}; + +// CPU0 VMSA table Level1 (4kB) +// Virtual address == Physical Address +const vmsaTable ArmVmsaTblLvl1Cpu0ForDDR1ch[] = { + // [MEM]Memory Address ...BIT[1:0]=01 + // [TBL]Next Level Table Address ...BIT[1:0]=11 + // Virtual Address Physical Address BLOCK Upper Lower Attr + // (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0] + // Next Level Table (1GBxN) [63:52] [11:00] [1:0][2:1] [2:0] + { 0x0000000000, 0x0000000000, 1, 0x000, 0x411 }, // [MEM]CS0/1,PCIe 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x0040000000, 0x0040000000, 1, 0x000, 0x411 }, // [MEM]DRAM 1st 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x0080000000, 0x0080000000, 1, 0x000, 0x411 }, // [MEM]DRAM 2nd 1GB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) + { 0x00C0000000, Lvl2VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 1GB 0 0 00 00 0 000 11 (Next Level Table) + { 0x0400000000, 0x0400000000, 4, 0x000, 0x411 }, // [MEM]DDR0 4GB 0 1 10 00 0 100 01 (Normal Memory Write-back transient) + { 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ---------- +}; + +// CPU0 VMSA table Level2 (4kB) +// Virtual address == Physical Address +const vmsaTable ArmVmsaTblLvl2Cpu0[] = { + // [MEM]Memory Address ...BIT[1:0]=01 + // [TBL]Next Level Table Address ...BIT[1:0]=11 + // Virtual Address Physical Address BLOCK Upper Lower Attr + // (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0] + // Next Level Table (2MBxN) [63:52] [11:00] [1:0][2:1] [2:0] + { 0x00E6200000, Lvl3VmsaTbl , 1, 0x000, 0x003 }, // [TBL]IPs 2MB 0 0 00 00 0 000 11 (Next Level Table) + { 0x00EB200000, 0x00EB200000, 1, 0x000, 0x411 }, // [MEM]RT-SRAM 2MB 0 1 00 00 0 100 01 (Normal Memory Write-back transient) @V3U + { 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ---------- +}; + +#ifdef SYSTEM_DEF_FALCON +// CPU0 VMSA table Level3 (4kB) @V3U CPUボード到ç€å¾Œã«ä¸Šã®vmsaTable ArmVmsaTblLvl3Cpu0[]ã¨å…¥ã‚Œæ›¿ãˆ +// Virtual address == Physical Address +const vmsaTable ArmVmsaTblLvl3Cpu0[] = { + // [INV]Invalid ...BIT[1:0]=x0 + // [RES]Reserved ...BIT[1:0]=01 + // [MEM]Memory Address ...BIT[1:0]=11 <-- Select + // Virtual Address Physical Address BLOCK Upper Lower Attr + // (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0] + // Next Level Table (4KBxN) [63:52] [11:00] [1:0][2:1] [2:0] + { 0x00E6200000, 0x00E6200000, 256, 0x000, 0x403 }, // [MEM]IPs 1MB 0 1 00 00 0 000 11 (Device-nGnRnE memory) + { 0x00E6300000, 0x00E6300000, 256, 0x000, 0x413 }, // [MEM]SystemRAM 1MB 0 1 00 00 0 100 11 (Normal Memory Write-back transient) @V3U + { 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ---------- +}; + +#else +// CPU0 VMSA table Level3 (4kB) @V3H +// Virtual address == Physical Address +const vmsaTable ArmVmsaTblLvl3Cpu0[] = { + // [INV]Invalid ...BIT[1:0]=x0 + // [RES]Reserved ...BIT[1:0]=01 + // [MEM]Memory Address ...BIT[1:0]=11 <-- Select + // Virtual Address Physical Address BLOCK Upper Lower Attr + // (Input) or units, Attributes Attributes nG AF SH AP NS Indx [1:0] + // Next Level Table (4KBxN) [63:52] [11:00] [1:0][2:1] [2:0] + { 0x00E6200000, 0x00E6200000, 256, 0x000, 0x403 }, // [MEM]IPs 1MB 0 1 00 00 0 000 11 (Device-nGnRnE memory) + { 0x00E6300000, 0x00E6300000, 48, 0x000, 0x413 }, // [MEM]SystemRAM 192KB 0 1 00 00 0 100 11 (Normal Memory Write-back transient) + { 0x00E6330000, 0x00E6330000, 48, 0x000, 0x413 }, // [MEM]SystemRAM 192KB 0 1 00 00 0 100 11 (Normal Memory Write-back transient) + { 0x00E6360000, 0x00E6360000, 160, 0x000, 0x403 }, // [MEM]SystemRAM 640KB 0 1 00 00 0 000 11 (Device-nGnRnE memory) + { 0x0000000000, 0x0000000000, 0, 0x000, 0x000 }, // ---------- END of Table ---------- +}; +#endif + +static void MakeVmsaTable(uint64_t *vmsaTblSadd, vmsaTable *vmsaSrcTbl, uint64_t startAddr, uint64_t blockShift); + +uint32_t SetVmsaTable(void) +{ + uint64_t *vmsaTblSadd; + vmsaTable *vmsaSrcTbl; + uint64_t startAddr; + uint64_t blockShift; + + // TCR_EL3, Translation Control Register (EL3) + // [31] Reserved-1: 1 + // [30:29] Reserved-0: 0 + // + // When ARMv8.2-TTPBHA is implemented + // [28] HWU62 : 0 :Bit[62] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. + // [27] HWU61 : 0 :Bit[61] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. + // [26] HWU60 : 0 :Bit[60] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. + // [25] HWU59 : 0 :Bit[59] of each stage 1 translation table Block or Page entry cannot be used by hardware for an IMPLEMENTATION DEFINED purpose. + // -The Effective value of this field is 0 if the value of TCR_EL3.HPD is 0. + // -This field resets to an architecturally UNKNOWN value. + // [24] HPD : 0 :Hierarchical Permission Disables. + // Otherwise + // [28:24] Reserved-0: 00000 + // + // [23] Reserved-1: 1 + // When ARMv8.1-TTHM is implemented + // [22] HD : 0 :Hardware management of dirty state in stage 1 translations from EL3. + // [21] HA : 0 :Hardware Access flag update in stage 1 translations from EL3. + // Otherwise + // [22:21] Reserved-0: 00 + // + // [20] TBI : 0 : Top Byte used in the address calculation. + // [19] Reserved-0: 0 + // [18:16] PS : 001 : Physical Address Size 000=32bit, 001=36bit, 010=40bit, 011=42bit, 100=44bit, 101=48bit + // [15:14] TG0 : 00 : translation table 00=4KB, 01=64KB, 10=16KB + // [13:12] SH0 : 10 : translation table memory 00=Non-shareable, 10=Outer Shareable, 11=Inner Shareable + // [11:10] ORGN0 : 01 : Outer 01=Write-Back Write-Allocate Cacheable + // [09:08] IRGN0 : 01 : Inner 01=Write-Back Write-Allocate Cacheable + // [07:06] Reserved : 00 + // [05:00] T0SZ : 011100 : The region size is 2^(64-T0SZ) byte. 2^(64-28)=2^36=0x10_0000_0000 + WriteTCR_EL3(0x8081251C); + WriteMAIR_EL3(ATTR_TBL); + WriteTTBR0_EL3((uint64_t)Lvl1VmsaTbl); // ASID=0 +#ifdef SYSTEM_DEF_FALCON + // VMSA Table Level1 for Main + vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR4ch; +#else + // VMSA Table Level1 for Main +// if( CHK_H3 && (!CHK_H3N) ){ vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR4ch; } // 4ch : H3 +// else if( CHK_M3 ){ vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR2ch; } // 2ch : M3 +// else if( CHK_H3N ){ vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR2ch; } // 2ch : H3N +// else { vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR1ch; } // 1ch : M3N,V3H,V3M,D3,E3 +#endif + vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl1Cpu0ForDDR4ch; + + vmsaTblSadd = (uint64_t*)Lvl1VmsaTbl; + startAddr = Lvl1StartAddr; + blockShift = Lvl1BlockShift; + MakeVmsaTable(vmsaTblSadd, vmsaSrcTbl, startAddr, blockShift); + + // VMSA Table Level2 for IPs + vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl2Cpu0; + vmsaTblSadd = (uint64_t*)Lvl2VmsaTbl; + startAddr = Lvl2StartAddr; + blockShift = Lvl2BlockShift; + MakeVmsaTable(vmsaTblSadd, vmsaSrcTbl, startAddr, blockShift); + + // VMSA Table Level3 for IPs + vmsaSrcTbl = (vmsaTable*)ArmVmsaTblLvl3Cpu0; + vmsaTblSadd = (uint64_t*)Lvl3VmsaTbl; + startAddr = Lvl3StartAddr; + blockShift = Lvl3BlockShift; + MakeVmsaTable(vmsaTblSadd, vmsaSrcTbl, startAddr, blockShift); + + return 0; +} + +static void MakeVmsaTable(uint64_t *vmsaTblSadd, vmsaTable *vmsaSrcTbl, uint64_t startAddr, uint64_t blockShift) +{ + uint32_t i,j; + uint64_t setData; + uint64_t *setAddr; + uint64_t upperAttr; // Attribute fields for VMSAv8-64 ([63:52]) + uint64_t lowerAttr; // Attribute fields for VMSAv8-64 ([11:0]) + uint64_t virAdd; + uint64_t phyAdd; + uint64_t block; + uint64_t blockSize; + + blockSize = (1<>(blockShift-3))); + setData = vmsaSrcTbl[i].upperAttr<<52; // [63:52] + setData |= phyAdd; // [47:12] + setData |= vmsaSrcTbl[i].lowerAttr; // [11:00] + + block = vmsaSrcTbl[i].unit; + for(j=0; j $(OUTDIR_OBJ)/build_message.c + @$(CC) $(CFLAGS) -o $(OUTDIR_OBJ)/build_message.o -c $(OUTDIR_OBJ)/build_message.c + + @$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \ + -T $(MEMORY_DEF) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE) \ + $(LDFLAGS) \ + -map=$(OUTDIR_REL)/$(FILE_NAME).map + + @$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).srec + @$(OD) -full -ytext $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE) -o $(OUTDIR_REL)/$(OUTPUT_FILE:%.elf=%.bin) + + +################################################### +# Compile +################################################### + +$(OUTDIR_OBJ)/%.o:%.c + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + @$(CC) $(CFLAGS) -o $@ -c $< + +$(OUTDIR_OBJ)/%.o:%.S + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + @$(AS) $(ASFLAGS) -o $@ -c $< + + +.PHONY: clean +clean: + @rm -rf $(OUTDIR) diff --git a/IPL/SDK/v4h/src/Dummy_FW/common/log.c b/IPL/SDK/v4h/src/Dummy_FW/common/log.c new file mode 100644 index 0000000..e857dfb --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/common/log.c @@ -0,0 +1,34 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Log driver + ******************************************************************************/ + +#include +#include +#include +#include + +void local_printf(const char *fmt, ...) +{ + va_list ap; + static char buffer[1024]; + int32_t num; + uint32_t loop; + + va_start(ap, fmt); + num = vsprintf(buffer, fmt, ap); + va_end(ap); + + if (0 < num) { + for (loop = 0; loop < num; loop++) { + (void)console_putc(buffer[loop]); + if (buffer[loop] == '\n') { + (void)console_putc('\r'); + } + } + } else { + panic(); + } +} + diff --git a/IPL/SDK/v4h/src/Dummy_FW/common/mem_io.c b/IPL/SDK/v4h/src/Dummy_FW/common/mem_io.c new file mode 100644 index 0000000..397be39 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/common/mem_io.c @@ -0,0 +1,48 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : memory access driver + ******************************************************************************/ + +#include + +void mem_write8(uintptr_t addr, uint8_t data) +{ + *(volatile uint8_t*)addr = data; +} +uint8_t mem_read8(uintptr_t addr) +{ + return (*(volatile uint8_t*)addr); +} + +void mem_write16(uintptr_t addr, uint16_t data) +{ + *(volatile uint16_t*)addr = data; +} +uint16_t mem_read16(uintptr_t addr) +{ + return (*(volatile uint16_t*)addr); +} + +void mem_write32(uintptr_t addr, uint32_t data) +{ + *(volatile uint32_t*)addr = data; +} +uint32_t mem_read32(uintptr_t addr) +{ + return (*(volatile uint32_t*)addr); +} + +void mem_write64(uintptr_t addr, uint64_t data) +{ + *(volatile uint64_t*)addr = data; +} +uint64_t mem_read64(uintptr_t addr) +{ + return (*(volatile uint64_t*)addr); +} + +void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set) +{ + mem_write32(addr, (mem_read32(addr) & ~clr) | set); +} diff --git a/IPL/SDK/v4h/src/Dummy_FW/common/micro_wait.c b/IPL/SDK/v4h/src/Dummy_FW/common/micro_wait.c new file mode 100644 index 0000000..9fd8659 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/common/micro_wait.c @@ -0,0 +1,72 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Time wait driver + ******************************************************************************/ + +#include +#include + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + +#define INTICUOSTM0 (*(volatile uint16_t*)0xFFFEEA14U) +#define INTCR_RF (1U <<12) + +#define OSTM0_BASE (0xFFFEE000UL) +#define OSTM0CMP (*(volatile uint32_t*)(OSTM0_BASE)) +#define OSTM0CNT (*(volatile uint32_t*)(OSTM0_BASE + 0x4UL)) +#define OSTM0TE (*(volatile uint8_t*)(OSTM0_BASE + 0x10UL)) +#define OSTM0TS (*(volatile uint8_t*)(OSTM0_BASE + 0x14UL)) +#define OSTM0TT (*(volatile uint8_t*)(OSTM0_BASE + 0x18UL)) +#define OSTM0CTL (*(volatile uint8_t*)(OSTM0_BASE + 0x20L)) +#define OSTM0EMU (*(volatile uint32_t*)(OSTM0_BASE + 0x24L)) + +#define OSTM0TS_TS (1U) /* b0:1: Start */ +#define OSTM0TT_TT (1U) /* b0:1: Stop */ +#define OSTM0TE_TE (1U) /* b0:1: Counter enabled */ +#define OSTM0CMP_MICRO_VALUE (0x190UL) /* PCLK=400MHz(400=0x190 = 1us) */ + +#define OSTM0CTL_MD10 (0x2U) /* b1:1: Free-run compare mode(Start:0 Counting Direction:up) */ + /* b0:0: Interrupts when counting starts are enabled */ + +/************************************************************************************************/ +/* Prototypes */ +/************************************************************************************************/ +static void start_microtimer(uint32_t val); +static void stop_microtimer(void); + +static void start_microtimer(uint32_t val) +{ + OSTM0TT = OSTM0TT_TT; + OSTM0CMP = val; + OSTM0CTL = OSTM0CTL_MD10; + OSTM0TS = OSTM0TS_TS; +} + +static void stop_microtimer(void) +{ + OSTM0TT = OSTM0TT_TT; +} + +void micro_wait(uint32_t count_us) +{ + uint32_t val; + + if (count_us == 0) { + return; + } + val = count_us * OSTM0CMP_MICRO_VALUE; + start_microtimer(val); + + while (1) { + if (INTICUOSTM0 & INTCR_RF) { + INTICUOSTM0 &= (uint16_t)(~INTCR_RF); + stop_microtimer(); + break; + } + + } +} + diff --git a/IPL/SDK/v4h/src/Dummy_FW/common/remap.c b/IPL/SDK/v4h/src/Dummy_FW/common/remap.c new file mode 100644 index 0000000..fa2cdeb --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/common/remap.c @@ -0,0 +1,171 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : remap driver + ******************************************************************************/ + +#include +#include +#include +#include +#include + + +typedef struct { + uint8_t number; + uint32_t address; +}REMAP_ADDRESS_TABLE; + +#define REMAP_TBL_MAX (sizeof(remap_tbl)/sizeof(remap_tbl[0])) + +static REMAP_ADDRESS_TABLE remap_tbl[] = { + [0] = {0xFF, 0x00000000U}, + [1] = {0xFF, 0x00000000U}, + [2] = {0xFF, 0x00000000U}, + [3] = {0xFF, 0x00000000U}, + [4] = {0xFF, 0x00000000U}, + [5] = {0xFF, 0x00000000U}, + [6] = {6, 0xE7200000U}, + [7] = {7, 0xE6400000U}, + [8] = {8, 0xFFC10000U}, + [9] = {9, 0xE6C00000U}, + [10] = {10, 0xFFC10000U}, + [11] = {11, 0xEE200000U}, + [12] = {12, 0xE6200000U}, + [13] = {13, 0xE6000000U}, + [14] = {14, 0xE6600000U}, + [15] = {15, 0xEB200000U}, +}; + +void remap_write_SICREMAP2M(uint32_t num, uint32_t value) +{ + /* Write-Protected Register Write Procedure */ + do { + mem_write32(ICUMX_PROT0PCMD, PROTCMD_START); + mem_write32(SICREMAP2M(num), value); + mem_write32(SICREMAP2M(num), ~value); + mem_write32(SICREMAP2M(num), value); + } while (mem_read32(ICUMX_PROT0PS) == PROTS0ERR); +} + +uint32_t remap_register(uint32_t addr, uint32_t size, uint32_t *remap_addr) +{ + uint32_t loop; + uint32_t loop2; + uint32_t map_num; + uint32_t set_addr; + + for (loop = 0; loop < REMAP_TBL_MAX; ++loop) { + if (0xFF == remap_tbl[loop].number) { + map_num = (addr & REMAP_2M_MASK) + size; + map_num = (map_num + REMAP_2M_MASK) + / (1 << REMAP_2M_BITS); + for (loop2 = 0; loop2 < map_num; ++loop2) { + if (0xFF != remap_tbl[loop].number) { + break; + } + } + if (map_num <= loop2) { + break; + } + } + } + + if (REMAP_TBL_MAX <= loop) { + return 2; + } + + __asm__ __volatile__ ("SYNCM"); + + set_addr = addr & ~REMAP_2M_MASK; + for (loop2 = loop; loop2 < (map_num + loop); ++loop2) { + remap_tbl[loop2].address = set_addr; + remap_tbl[loop2].number = loop; + remap_write_SICREMAP2M(loop2, set_addr); + set_addr += (1 << REMAP_2M_BITS); + } + + __asm__ __volatile__ ("SYNCM"); + + *remap_addr = ICU_REMAP_CALC(loop); + *remap_addr += addr & REMAP_2M_MASK; + return 0; +} + +uint32_t remap_unregister(uint32_t remap_addr) +{ + uint32_t loop; + uint32_t loop2; + uint32_t remove_num; + + for (loop = 0; loop < REMAP_TBL_MAX; ++loop) { + if ((0xFF != remap_tbl[loop].number) + && ((ICU_REMAP_CALC(loop) <= remap_addr) + && (remap_addr < ICU_REMAP_CALC(loop+1)))) { + break; + } + } + + if (REMAP_TBL_MAX <= loop) { + return 1; + } + __asm__ __volatile__ ("SYNCM"); + + remove_num = remap_tbl[loop].number; + for (loop2 = remove_num; loop2 < REMAP_TBL_MAX; ++loop2) { + if (remap_tbl[loop2].number != remove_num) { + break; + } + remap_tbl[loop2].address = 0; + remap_tbl[loop2].number = 0xFF; + remap_write_SICREMAP2M(loop2, ICU_REMAP_CALC(loop2)); + } + + __asm__ __volatile__ ("SYNCM"); + return 0; +} + +uint32_t remap_get_phys_addr(uint32_t remap_addr) +{ + uint32_t phys_addr; + uint32_t reg; + + if ((ICU_REMAP0 > remap_addr) + || (ICU_REMAP_CALC(REMAP_REG_MAX) <= remap_addr)) { + ERROR("remap address Error\n"); + panic(); + } + + phys_addr = remap_addr - ICU_REMAP0; + phys_addr >>= REMAP_2M_BITS; + reg = SICREMAP2M(phys_addr); + reg = mem_read32(reg); + phys_addr = reg + (remap_addr & REMAP_2M_MASK); + + return phys_addr; +} + +uint32_t remap_get_remap_addr(uint32_t phys_addr) +{ + uint32_t remap_addr; + uint32_t reg; + uint32_t loop; + + for (loop = 0; loop < REMAP_REG_MAX; loop++) { + reg = mem_read32(SICREMAP2M(loop)); + if ((reg <= phys_addr) + && (phys_addr <= (reg + REMAP_2M_MASK))) { + break; + } + } + + if (REMAP_REG_MAX <= loop) { + ERROR("remap address Error\n"); + panic(); + } + + remap_addr = ICU_REMAP_CALC(loop); + remap_addr += phys_addr - reg; + + return remap_addr; +} diff --git a/IPL/SDK/v4h/src/Dummy_FW/common/scif.c b/IPL/SDK/v4h/src/Dummy_FW/common/scif.c new file mode 100644 index 0000000..7bc1c27 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/common/scif.c @@ -0,0 +1,416 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : SCIF driver + ******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Define */ +#define SCIF_SCSCR_TE_EN (uint16_t)((uint16_t)1U << 5U) +#define SCIF_SCSCR_RE_EN (uint16_t)((uint16_t)1U << 4U) +#define SCIF_SCSCR_CKE_EXT_CLK (uint16_t)((uint16_t)2U << 0U) +#define SCIF_SCSCR_INIT_DATA (uint16_t)(SCIF_SCSCR_TE_EN | SCIF_SCSCR_RE_EN) +#define SCIF_SCSCR_HW_INIT (uint16_t)(0x0000U) + +#define SCIF_SCFCR_TFRST_EN (uint16_t)((uint16_t)1U << 2U) +#define SCIF_SCFCR_RFRS_EN (uint16_t)((uint16_t)1U << 1U) +#define SCIF_SCFCR_RESET_FIFO (uint16_t)(SCIF_SCFCR_TFRST_EN | SCIF_SCFCR_RFRS_EN) +#define SCIF_SCFCR_INIT_DATA (uint16_t)(0x0000U) + +#define SCIF_SCFSR_TEND (uint16_t)((uint16_t)1U << 6U) +#define SCIF_SCFSR_TDFE (uint16_t)((uint16_t)1U << 5U) +#define TRANS_END_CHECK (uint16_t)(SCIF_SCFSR_TEND | SCIF_SCFSR_TDFE) +#define SCIF_SCFSR_INIT_DATA (uint16_t)(0x0000U) + +#define SCIF_SCLSR_INIT_DATA (uint16_t)(0x0000U) + +#define SCIF_SCSMR_INIT_DATA (uint16_t)(0x0000U) + +/* Pclk(66MHz)/1, 115.2kBps*/ +/* N = 66/(66/2*115200)*10^4-1 =17=> 0x11 */ +#define SCIF_SCBRR_115200BPS (uint8_t)(0x11U) +/* Pclk(266MHz)/1, 921.6kBps*/ +/* N = 266/(8*2*921600)*10^6-1 =17=> 0x11 */ +#define HSCIF_SCBRR_921600BPS (uint8_t)(0x11U) +/* Pclk(266MHz)/1, 1.8432MBps*/ +/* N = 266/(8*2*1843200)*10^6-1 =8=> 0x08 */ +#define HSCIF_SCBRR_1843200BPS (uint8_t)(0x08U) +#define SCIF_SCBRR_HW_INIT (uint8_t)(0xFFU) + +#define HSCIF_HSSRR_SRE (uint16_t)(1U << 15U) +#define HSCIF_HSSRR_SRCYC8 (uint16_t)(7U << 0U) /* Sampling rate 8-1 */ +#define HSCIF_HSSRR_VAL (uint16_t)(HSCIF_HSSRR_SRE | HSCIF_HSSRR_SRCYC8) + +#define HSCIF_DL_DIV1 (uint16_t)(1U << 0U) +#define HSCIF_CKS_SC_CLK_EXT (uint16_t)(0x0000U) + + +#define MODEMR_SCIF_DLMODE (0x00000000U) +#define MODEMR_HSCIF_DLMODE_921600 (0x00000001U) +#define MODEMR_HSCIF_DLMODE_1843200 (0x00000002U) +#define MODEMR_HSCIF_DLMODE_3000000 (0x00000003U) + +static void (*put_char)(uint8_t); + +static void scif_console_putc(uint8_t outchar); +static void hscif_console_putc(uint8_t outchar); + +void scif_init(void) +{ +// volatile uint16_t reg; + uint32_t modemr; + uint32_t product; + + product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; + + switch (product) { + case PRR_PRODUCT_S4: + modemr = (((mem_read32(RST_MODEMR0) & RST_MODEMR0_MD31) >> 31U) + | ((mem_read32(RST_MODEMR1) & RST_MODEMR1_MD32) << 1U)); + if(modemr == MODEMR_SCIF_DLMODE) + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(SCIF_SCSCR_3, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + mem_write16(SCIF_SCFCR_3, SCIF_SCFCR_RESET_FIFO); + + /* clear ORER bit */ + mem_write16(SCIF_SCLSR_3, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(SCIF_SCFSR_3, SCIF_SCFSR_INIT_DATA); + + /* internal clock, SC_CLK pin unused for output pin */ + mem_write16(SCIF_SCSCR_3, SCIF_SCSCR_HW_INIT); + /* 8bit data, no-parity, 1 stop, Po/1 */ + mem_write16(SCIF_SCSMR_3, SCIF_SCSMR_INIT_DATA); + + /* Baud rate 115200bps*/ + mem_write16(SCIF_SCBRR_3, SCIF_SCBRR_115200BPS); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + mem_write16(SCIF_SCFCR_3, SCIF_SCFCR_INIT_DATA); + /* enable TE, RE; SC_CLK=no output */ + mem_write16(SCIF_SCSCR_3, SCIF_SCSCR_INIT_DATA); + + /* Set the pointer to a function that outputs one character. */ + put_char = scif_console_putc; + } + else if(modemr == MODEMR_HSCIF_DLMODE_921600) + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + mem_write16(HSCIF_HSFCR, SCIF_SCFCR_RESET_FIFO); + + /* clear ORER bit */ + mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA); + + /* internal clock, SC_CLK pin unused for output pin */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* 8bit data, no-parity, 1 stop, Po/1 */ + mem_write16(HSCIF_HSSMR, SCIF_SCSMR_INIT_DATA); + + /* Sampling rate 8 */ + mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL); + /* Baud rate 921600bps*/ + mem_write16(HSCIF_HSBRR, HSCIF_SCBRR_921600BPS); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + mem_write16(HSCIF_HSFCR, SCIF_SCFCR_INIT_DATA); + /* enable TE, RE; SC_CLK=no output */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_INIT_DATA); + + /* Set the pointer to a function that outputs one character. */ + put_char = hscif_console_putc; + } + else if(modemr == MODEMR_HSCIF_DLMODE_1843200) + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + mem_write16(HSCIF_HSFCR, SCIF_SCFCR_RESET_FIFO); + + /* clear ORER bit */ + mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA); + + /* internal clock, SC_CLK pin unused for output pin */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* 8bit data, no-parity, 1 stop, Po/1 */ + mem_write16(HSCIF_HSSMR, SCIF_SCSMR_INIT_DATA); + + /* Sampling rate 8 */ + mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL); + /* Baud rate 1843200bps*/ + mem_write16(HSCIF_HSBRR, HSCIF_SCBRR_1843200BPS); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + mem_write16(HSCIF_HSFCR, SCIF_SCFCR_INIT_DATA); + /* enable TE, RE; SC_CLK=no output */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_INIT_DATA); + + /* Set the pointer to a function that outputs one character. */ + put_char = hscif_console_putc; + } + else if(modemr == MODEMR_HSCIF_DLMODE_3000000) + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + mem_write16(HSCIF_HSFCR, SCIF_SCFCR_RESET_FIFO); + + /* clear ORER bit */ + mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA); + + /* external clock, SC_CLK pin used for output pin */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_CKE_EXT_CLK); + /* 8bit data, no-parity, 1 stop, Po/1 */ + mem_write16(HSCIF_HSSMR, SCIF_SCSMR_INIT_DATA); + + /* 24MHz / (3000000 * 8) = 1 */ + mem_write16(HSCIF_DL, HSCIF_DL_DIV1); + + mem_write16(HSCIF_CKS, HSCIF_CKS_SC_CLK_EXT); + /* Sampling rate 8 */ + mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + mem_write16(HSCIF_HSFCR, SCIF_SCFCR_INIT_DATA); + /* enable TE, RE; SC_CLK=external */ + mem_write16(HSCIF_HSSCR, mem_read16(HSCIF_HSSCR) | SCIF_SCSCR_INIT_DATA); + + /* Set the pointer to a function that outputs one character. */ + put_char = hscif_console_putc; + } + else + { + /* No process */ + } + break; + case PRR_PRODUCT_V4H: + case PRR_PRODUCT_V4M: + modemr = (((mem_read32(RST_MODEMR0) & RST_MODEMR0_MD31) >> 31U) + | ((mem_read32(RST_MODEMR1) & RST_MODEMR1_MD32) << 1U)); + if(modemr == MODEMR_SCIF_DLMODE) + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(SCIF_SCSCR_0, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + mem_write16(SCIF_SCFCR_0, SCIF_SCFCR_RESET_FIFO); + + /* clear ORER bit */ + mem_write16(SCIF_SCLSR_0, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(SCIF_SCFSR_0, SCIF_SCFSR_INIT_DATA); + + /* internal clock, SC_CLK pin unused for output pin */ + mem_write16(SCIF_SCSCR_0, SCIF_SCSCR_HW_INIT); + /* 8bit data, no-parity, 1 stop, Po/1 */ + mem_write16(SCIF_SCSMR_0, SCIF_SCSMR_INIT_DATA); + + /* Baud rate 115200bps*/ + mem_write16(SCIF_SCBRR_0, SCIF_SCBRR_115200BPS); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + mem_write16(SCIF_SCFCR_0, SCIF_SCFCR_INIT_DATA); + /* enable TE, RE; SC_CLK=no output */ + mem_write16(SCIF_SCSCR_0, SCIF_SCSCR_INIT_DATA); + + /* Set the pointer to a function that outputs one character. */ + put_char = scif_console_putc; + } + else if(modemr == MODEMR_HSCIF_DLMODE_921600) + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + mem_write16(HSCIF_HSFCR, SCIF_SCFCR_RESET_FIFO); + + /* clear ORER bit */ + mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA); + + /* internal clock, SC_CLK pin unused for output pin */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* 8bit data, no-parity, 1 stop, Po/1 */ + mem_write16(HSCIF_HSSMR, SCIF_SCSMR_INIT_DATA); + + /* Sampling rate 8 */ + mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL); + /* Baud rate 921600bps*/ + mem_write16(HSCIF_HSBRR, HSCIF_SCBRR_921600BPS); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + mem_write16(HSCIF_HSFCR, SCIF_SCFCR_INIT_DATA); + /* enable TE, RE; SC_CLK=no output */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_INIT_DATA); + + /* Set the pointer to a function that outputs one character. */ + put_char = hscif_console_putc; + } + else if(modemr == MODEMR_HSCIF_DLMODE_1843200) + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + mem_write16(HSCIF_HSFCR, SCIF_SCFCR_RESET_FIFO); + + /* clear ORER bit */ + mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA); + + /* internal clock, SC_CLK pin unused for output pin */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* 8bit data, no-parity, 1 stop, Po/1 */ + mem_write16(HSCIF_HSSMR, SCIF_SCSMR_INIT_DATA); + + /* Sampling rate 8 */ + mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL); + /* Baud rate 1843200bps*/ + mem_write16(HSCIF_HSBRR, HSCIF_SCBRR_1843200BPS); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + mem_write16(HSCIF_HSFCR, SCIF_SCFCR_INIT_DATA); + /* enable TE, RE; SC_CLK=no output */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_INIT_DATA); + + /* Set the pointer to a function that outputs one character. */ + put_char = hscif_console_putc; + } + else if(modemr == MODEMR_HSCIF_DLMODE_3000000) + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + mem_write16(HSCIF_HSFCR, SCIF_SCFCR_RESET_FIFO); + + /* clear ORER bit */ + mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA); + + /* external clock, SC_CLK pin used for output pin */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_CKE_EXT_CLK); + /* 8bit data, no-parity, 1 stop, Po/1 */ + mem_write16(HSCIF_HSSMR, SCIF_SCSMR_INIT_DATA); + + /* 24MHz / (3000000 * 8) = 1 */ + mem_write16(HSCIF_DL, HSCIF_DL_DIV1); + + mem_write16(HSCIF_CKS, HSCIF_CKS_SC_CLK_EXT); + /* Sampling rate 8 */ + mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + mem_write16(HSCIF_HSFCR, SCIF_SCFCR_INIT_DATA); + /* enable TE, RE; SC_CLK=external */ + mem_write16(HSCIF_HSSCR, mem_read16(HSCIF_HSSCR) | SCIF_SCSCR_INIT_DATA); + + /* Set the pointer to a function that outputs one character. */ + put_char = hscif_console_putc; + } + else + { + /* No process */ + } + break; + default: + break; + } +} + +void console_puts(char *str,char rtn) +{ + while (*str) { + console_putc(*str); + str++; + } + + if(rtn == 1){ + console_putc(CR_CODE); + console_putc(LF_CODE); + } +} + +void console_putc(uint8_t outchar) +{ + put_char(outchar); +} + + +static void scif_console_putc(uint8_t outchar) +{ + uint16_t reg; + uint32_t product; + + product = *((volatile uint32_t*)PRR) & PRR_PRODUCT_MASK; + + switch (product) { + case PRR_PRODUCT_S4: + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR_3)) == TRANS_END_CHECK)){ + } + + mem_write8(SCIF_SCFTDR_3, outchar); /* Transfer one character */ + reg = mem_read16(SCIF_SCFSR_3); + reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */ + mem_write16(SCIF_SCFSR_3, reg); + break; + case PRR_PRODUCT_V4H: + case PRR_PRODUCT_V4M: + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR_0)) == TRANS_END_CHECK)){ + } + + mem_write8(SCIF_SCFTDR_0, outchar); /* Transfer one character */ + reg = mem_read16(SCIF_SCFSR_0); + reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */ + mem_write16(SCIF_SCFSR_0, reg); + break; + } +} + +static void hscif_console_putc(uint8_t outchar) +{ + uint16_t reg; + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK)){ + } + + mem_write8(HSCIF_HSFTDR, outchar); /* Transfer one character */ + reg = mem_read16(HSCIF_HSFSR); + reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */ + mem_write16(HSCIF_HSFSR, reg); +} diff --git a/IPL/SDK/v4h/src/Dummy_FW/common/wdt.c b/IPL/SDK/v4h/src/Dummy_FW/common/wdt.c new file mode 100644 index 0000000..01ba2f7 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/common/wdt.c @@ -0,0 +1,59 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : window watchdog timer driver + ******************************************************************************/ +/****************************************************************************** + * @file wdt.c + * - Version : 0.01 + * @brief Window Watchdog Timer driver + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + *****************************************************************************/ + +#include +#include +#include + +#define ICUMX_WDTA0_BASE (0xFFFEE080U) /* Watchdog Timer base */ +#define ICUMX_WDTA0EVAC (ICUMX_WDTA0_BASE+0x0004U) +#define ICUMX_WDTA0REF (ICUMX_WDTA0_BASE+0x0008U) + +/* Activation code */ +#define WDT_ACT_CODE (0xACU) + +void wdt_restart(void) +{ + uint8_t reg; + + reg = mem_read8(ICUMX_WDTA0REF); + /* Watchdog Timer restart. */ + /* Subtract ICUMX_WDTA0REF from activation code when VAC(Variable Activation Code) is enabled. */ + mem_write8(ICUMX_WDTA0EVAC, WDT_ACT_CODE - reg); +} +/* End of function wdt_restart(void) */ + diff --git a/IPL/SDK/v4h/src/Dummy_FW/fw/dummy_fw.S b/IPL/SDK/v4h/src/Dummy_FW/fw/dummy_fw.S new file mode 100644 index 0000000..97be1b9 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/fw/dummy_fw.S @@ -0,0 +1,59 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Dummy FW start code + ******************************************************************************/ + + .global code_start + .global _dummy_fw_main + .global ___ghsend_RT_stack /* RT-SRAM stack Logical end address */ + + .section ".text" + .align 2 +code_start: + + mov r0, r1 + mov r0, r2 + mov r0, r3 + mov r0, r4 + mov r0, r5 + mov r0, r6 + mov r0, r7 + mov r0, r8 + mov r0, r9 + mov r0, r10 + mov r0, r11 + mov r0, r12 + mov r0, r13 + mov r0, r14 + mov r0, r15 + mov r0, r16 + mov r0, r17 + mov r0, r18 + mov r0, r19 + mov r0, r20 + mov r0, r21 + mov r0, r22 + mov r0, r23 + mov r0, r24 + mov r0, r25 + mov r0, r26 + mov r0, r27 + mov r0, r28 + mov r0, r29 + ldsr r0, 0, 0 + ldsr r0, 16, 0 + + mov ___ghsend_RT_stack, sp + + jarl _dummy_fw_main, lp + + jmp [r10] + nop + halt + + + .section ".padding" + .align 4 + + diff --git a/IPL/SDK/v4h/src/Dummy_FW/fw/dummy_fw.ld b/IPL/SDK/v4h/src/Dummy_FW/fw/dummy_fw.ld new file mode 100644 index 0000000..d950c93 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/fw/dummy_fw.ld @@ -0,0 +1,79 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Dummy FW linker directive + ******************************************************************************/ + +DEFAULTS { + remap_addr = 0xFDE00000 //remap15 address(target address = 0xEB200000) + remap_size = 1M //RT-SRAM size + rt_sram_addr = 0xEB200000 //RT-SRAM address +// fw_size = 110K //Dummy FW size + fw_size = 93K //Dummy FW size + fw_rom_size = 89K + fw_stack_size = 4K //Dummy FW stack size + + fw_addr = 0xFDE40000 //Dummy FW start address + fw_stack_addr = fw_addr + fw_rom_size //Dummy FW stack address + + fw_phy_addr = 0xEB240000 //Dummy FW physical start address + fw_phy_stack_addr = fw_phy_addr + fw_rom_size //Dummy FW physical stack address + +} +MEMORY +{ + fw_start : ORIGIN = fw_addr, LENGTH = fw_rom_size //Dummy FW ROM(Start address) + stack : ORIGIN = fw_stack_addr, LENGTH = fw_stack_size//Dummy FW stack + fw_phys_start : ORIGIN = fw_phy_addr, LENGTH = fw_rom_size //Dummy FW(RT-SRAM) +} + +// +// Program layout for starting in ROM, copying data to RAM, +// and continuing to execute out of ROM. +// +SECTIONS +{ +// +// ROM SECTIONS(Remap) +// +// Place .text into fast_memory. Fail if it does not fit. + .reset ALIGN(4) : > fw_start + .EIINTTBL_ICU ALIGN(4) : > . + .version ALIGN(1024) :{*(.version)} > . + .text ALIGN(16) : > . + .data ALIGN(4) : > . + .rosdata ALIGN(4) : > . + .rodata ALIGN(4) : > . + .bss ALIGN(4) : > . + .sdata ALIGN(4) : > . + .tdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . + .padding ALIGN(16) MIN_SIZE(16): > . +// .note.renesas ALIGN(4) : > . +// .linfix ALIGN(4) : > . +// .gstackfix ALIGN(4) : > . + +// ROM mirror SECTIONS(RT-SRAM) + _start = fw_phy_addr; + .ROM_NOCOPY.reset ROM_NOCOPY(.reset) ALIGN(4) : > fw_phys_start + .ROM_NOCOPY.EIINTTBL_ICU ROM_NOCOPY(.EIINTTBL_ICU) ALIGN(4) : > . + .ROM_NOCOPY.version ROM_NOCOPY(.version) ALIGN(1024) : > . + .ROM_NOCOPY.text ROM_NOCOPY(.text) ALIGN(4) : > . + .ROM_NOCOPY.data ROM_NOCOPY(.data) ALIGN(4) : > . + .ROM_NOCOPY.rosdata ROM_NOCOPY(.rosdata) ALIGN(4) : > . + .ROM_NOCOPY.rodata ROM_NOCOPY(.rodata) ALIGN(4) : > . + .ROM_NOCOPY.bss ROM_NOCOPY(.bss) ALIGN(4) : > . + .ROM_NOCOPY.sdata ROM_NOCOPY(.sdata) ALIGN(4) : > . + .ROM_NOCOPY.tdata ROM_NOCOPY(.tdata) ALIGN(4) : > . + .ROM_NOCOPY.sdabase ROM_NOCOPY(.sdabase) ALIGN(4) : > . + .ROM_NOCOPY.secinfo ROM_NOCOPY(.secinfo) ALIGN(4) : > . + .ROM_NOCOPY.padding ROM_NOCOPY(.padding) ALIGN(16) : > . + + +// +// RAM SECTIONS +// + + .RT.stack ALIGN(4) PAD(fw_stack_size) ABS : > stack +} diff --git a/IPL/SDK/v4h/src/Dummy_FW/fw/dummy_fw_main.c b/IPL/SDK/v4h/src/Dummy_FW/fw/dummy_fw_main.c new file mode 100644 index 0000000..271f8f5 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/fw/dummy_fw_main.c @@ -0,0 +1,45 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : dummy fw main function + ******************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Software version */ +#define SW_VERSION_DUMMY_FW (0x00000001U) + +/* Global */ +extern const char build_message[]; + +static void boot_message(void); + +__attribute__ ((section (".version"))) const uint32_t sw_version[1] = { + [0] = SW_VERSION_DUMMY_FW, +}; + +uint32_t dummy_fw_main(void) +{ + scif_init(); + boot_message(); + while(1){ + wdt_restart(); + } +} + +static void boot_message(void) +{ + /* boot message */ + console_puts("",1); + console_puts("Dummy FW Program",1); + console_puts("Dummy FW Program boot end",1); +} diff --git a/IPL/SDK/v4h/src/Dummy_FW/fw/vecttbl.S b/IPL/SDK/v4h/src/Dummy_FW/fw/vecttbl.S new file mode 100644 index 0000000..952e7ff --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/fw/vecttbl.S @@ -0,0 +1,98 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Dummy FW vector table + ******************************************************************************/ + + .global code_start + + .section ".reset" + .align 512 + .align 16 +_start: + jr32 code_start //RESET + .align 16 + jr32 _Dummy //SYSERR + .align 16 + jr32 _Dummy //HVTRAP + .align 16 + jr32 _Dummy //FETRAP + .align 16 + jr32 _Dummy //TRAP0 + .align 16 + jr32 _Dummy //TRAP1 + .align 16 + jr32 _Dummy //RIE + .align 16 + jr32 _Dummy //FPP/FPI + .align 16 + jr32 _Dummy //UCPOP + .align 16 + jr32 _Dummy //MIP/MDP + .align 16 + jr32 _Dummy //PIE + .align 16 + jr32 _Dummy //Debug + .align 16 + jr32 _Dummy //MAE + .align 16 + jr32 _Dummy //(R.F.U) + .align 16 + jr32 _Dummy //FENMI + .align 16 + jr32 _Dummy //FEINT + .align 16 + jr32 _Dummy //INTn(priority0) + .align 16 + jr32 _Dummy //INTn(priority1) + .align 16 + jr32 _Dummy //INTn(priority2) + .align 16 + jr32 _Dummy //INTn(priority3) + .align 16 + jr32 _Dummy //INTn(priority4) + .align 16 + jr32 _Dummy //INTn(priority5) + .align 16 + jr32 _Dummy //INTn(priority6) + .align 16 + jr32 _Dummy //INTn(priority7) + .align 16 + jr32 _Dummy //INTn(priority8) + .align 16 + jr32 _Dummy //INTn(priority9) + .align 16 + jr32 _Dummy //INTn(priority10) + .align 16 + jr32 _Dummy //INTn(priority11) + .align 16 + jr32 _Dummy //INTn(priority12) + .align 16 + jr32 _Dummy //INTn(priority13) + .align 16 + jr32 _Dummy //INTn(priority14) + .align 16 + jr32 _Dummy //INTn(priority15) + + .section ".EIINTTBL_ICU", const + .align 512 + .rept 7 + .word _Dummy_EI //INTn + .endr + .word _Dummy_EI //OSTM0 + .rept 20 + .word _Dummy_EI //INTn + .endr + .word _Dummy_EI //_Dummy + .word _Dummy_EI //_Dummy + .rept 98 + .word _Dummy_EI //INTn + .endr + + .section ".text" + .align 2 +_Dummy: + br _Dummy + +_Dummy_EI: + br _Dummy_EI diff --git a/IPL/SDK/v4h/src/Dummy_FW/include/dummy_fw_main.h b/IPL/SDK/v4h/src/Dummy_FW/include/dummy_fw_main.h new file mode 100644 index 0000000..c95421a --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/include/dummy_fw_main.h @@ -0,0 +1,16 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Dummy FW main header + ******************************************************************************/ + +#ifndef DUMMY_FW_MAIN_H_ +#define DUMMY_FW_MAIN_H_ + +/* define */ +#define VERSION "1.0.0" + +/* prototype */ +uint32_t dummy_fw_main(void); + +#endif /* DUMMY_FW_MAIN_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_FW/include/log.h b/IPL/SDK/v4h/src/Dummy_FW/include/log.h new file mode 100644 index 0000000..1af9fa4 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/include/log.h @@ -0,0 +1,64 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Log driver header + ******************************************************************************/ + +#ifndef LOG_H__ +#define LOG_H__ + +#include +#include + +#define LOG_NONE (0) +#define LOG_ERROR (1) +#define LOG_NOTICE (2) +#define LOG_WARNING (3) +#define LOG_INFO (4) +#define LOG_VERBOSE (5) + +#ifndef LOG_LEVEL + #define LOG_LEVEL (LOG_WARNING) +#endif + +#if LOG_LEVEL >= LOG_VERBOSE +# define VERBOSE(...) local_printf("V:" __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + +#if LOG_LEVEL >= LOG_INFO +# define INFO(...) local_printf("I:" __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_WARNING +# define WARN(...) local_printf("W:" __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_ERROR +# define ERROR(...) local_printf("E:" __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_NOTICE +# define NOTICE(...) local_printf("N:" __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#define panic(...) \ + do { \ + local_printf("P:%s[%d]\n", __func__, __LINE__); \ + while(1); \ + } while (0) + +#define FORCE(...) local_printf(__VA_ARGS__) + +void local_printf(const char *fmt, ...); + +#endif /* LOG_H__ */ diff --git a/IPL/SDK/v4h/src/Dummy_FW/include/mem_io.h b/IPL/SDK/v4h/src/Dummy_FW/include/mem_io.h new file mode 100644 index 0000000..b306d21 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/include/mem_io.h @@ -0,0 +1,29 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Memory access driver header + ******************************************************************************/ +#ifndef MEM_IO_H_ +#define MEM_IO_H_ + +#include + +/* Prototype */ +void mem_write8(uintptr_t addr, uint8_t data); +uint8_t mem_read8(uintptr_t addr); +void mem_write16(uintptr_t addr, uint16_t data); +uint16_t mem_read16(uintptr_t addr); +void mem_write32(uintptr_t addr, uint32_t data); +uint32_t mem_read32(uintptr_t addr); +void mem_write64(uintptr_t addr, uint64_t data); +uint64_t mem_read64(uintptr_t addr); +void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set); + +#if defined(__RH850G3K__) +#define mmio_write_32(a,b) mem_write32(a,b) +#define mmio_read_32(a) mem_read32(a) +#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c) +#endif + + +#endif /* MEM_IO_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_FW/include/micro_wait.h b/IPL/SDK/v4h/src/Dummy_FW/include/micro_wait.h new file mode 100644 index 0000000..c5b9acc --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/include/micro_wait.h @@ -0,0 +1,18 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : Time wait driver header + ******************************************************************************/ + +#ifndef MICRO_WAIT_H_ +#define MICRO_WAIT_H_ + +#include + +/* Define */ + +/* Prototype */ +void micro_wait(uint32_t count_us); + + +#endif /* MICRO_WAIT_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_FW/include/rcar_def.h b/IPL/SDK/v4h/src/Dummy_FW/include/rcar_def.h new file mode 100644 index 0000000..74e8c0c --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/include/rcar_def.h @@ -0,0 +1,28 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : R-Car common header + ******************************************************************************/ + +#ifndef RCAR_DEF_H_ +#define RCAR_DEF_H_ + +/* Product Register */ +#define PRR (0xFFF00044U) /* PRR register */ +#define PRR_PRODUCT_MASK (0x00007F00U) /* Product mask */ +#define PRR_CUT_MASK (0x000000FFU) /* Cut Number bit mask */ +#define PRR_MAJOR_MASK (0x000000F0U) /* Major bit mask */ +#define PRR_MINOR_MASK (0x0000000FU) /* Minor bit mask */ +#define PRR_PRODUCT_SHIFT (8U) /* PRR bit shift */ +#define PRR_MAJOR_SHIFT (4U) /* Major bit shift */ +#define PRR_MINOR_SHIFT (0U) /* Minor bit shift */ +#define PRR_MAJOR_OFFSET (1U) + +#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */ +#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */ +#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */ +#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */ +#define PRR_PRODUCT_10 (0x00U) + +#endif /* RCAR_DEF_H_ */ + diff --git a/IPL/SDK/v4h/src/Dummy_FW/include/remap.h b/IPL/SDK/v4h/src/Dummy_FW/include/remap.h new file mode 100644 index 0000000..38df3fb --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/include/remap.h @@ -0,0 +1,20 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : remap driver header + ******************************************************************************/ +#ifndef REMAP_H_ +#define REMAP_H_ + +#define REMAP_SIZE_MIN (2*1024*1024) +#define REMAP_ALIGN_MASK (~((1 << 21) - 1)) + +void remap_write_SICREMAP2M(uint32_t num, uint32_t value); + +uint32_t remap_get_phys_addr(uint32_t remap_addr); +uint32_t remap_get_remap_addr(uint32_t phys_addr); + +uint32_t remap_register(uint32_t addr, uint32_t size, uint32_t *remap_addr); +uint32_t remap_unregister(uint32_t remap_addr); + +#endif /* REMAP_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_FW/include/remap_register.h b/IPL/SDK/v4h/src/Dummy_FW/include/remap_register.h new file mode 100644 index 0000000..5af8bbb --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/include/remap_register.h @@ -0,0 +1,195 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : remap register header + ******************************************************************************/ + +#ifndef REMAP_REGISTER_H_ +#define REMAP_REGISTER_H_ + + +#define REMAP_BASE (0xFF1FC400U) + +#define REMAP_2M_BITS (21U) +#define REMAP_2M_MASK ((1 << REMAP_2M_BITS) - 1U) + +#define REMAP_REG_MAX (16U) +#define SICREMAP2M(a) (REMAP_BASE + ((a) * (0x4U))) + +#define ICUMX_PROT0PCMD (0xFFFEE090U) +#define ICUMX_PROT0PS (0xFFFEE094U) +#define PROTCMD_START (0x000000A5U) +#define PROTS0ERR (0x00000001U) + +/* REMAP setting */ +/* Remap ID(0 -- 15) */ +#define ICU_REMAP_NUM_RTRAM (15U) /* RTRAM */ +#define ICU_REMAP_NUM_CC (14U) /* CC63S */ +#define ICU_REMAP_NUM_PFC (13U) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */ +#define ICU_REMAP_NUM_MFIS (12U) /* MFIS */ +#define ICU_REMAP_NUM_RPC (11U) /* RPC */ +#define ICU_REMAP_NUM_RTDMAC (10U) /* RT-DMAC0 */ +#define ICU_REMAP_NUM_SCIF (9U) /* SCIF */ +#define ICU_REMAP_NUM_MMC (8U) /* MMC */ +#define ICU_REMAP_NUM_HSCIF (7U) /* HSCIF */ +#define ICU_REMAP_NUM_DMAC (6U) /* SYS-DMAC0 */ +#define ICU_REMAP_NUM_PRR (5U) /* PRR */ +#define ICU_REMAP_NUM_RTACT (4U) /* RT-ACT */ + +/* SICREMAP2M15 */ +#define ICU_REMAP_RTRAM (0xEB200000U) /* RTRAM */ +/* SICREMAP2M14 */ +#define ICU_REMAP_CC (0xE6600000U) /* CC63S,System DMA */ +/* SICREMAP2M13 */ +#define ICU_REMAP_PFC (0xE6000000U) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */ +/* SICREMAP2M12 */ +#define ICU_REMAP_MFIS (0xE6200000U) /* MFIS */ +/* SICREMAP2M11 */ +#define ICU_REMAP_RPC (0xEE200000U) /* RPC */ +/* SICREMAP2M10 */ +#define ICU_REMAP_SCIF (0xE6C00000U) /* SCIF */ +/* SICREMAP2M9 */ +#define ICU_REMAP_MMC (0xEE000000U) /* MMC */ +/* SICREMAP2M8 */ +#define ICU_REMAP_RTDMAC (0xFFC00000U) /* RT-DMAC0 */ +/* SICREMAP2M7 */ +#define ICU_REMAP_HSCIF (0xE6400000U) /* HSCIF */ +/* SICREMAP2M6 */ +#define ICU_REMAP_DMAC (0xE7200000U) /* SYS-DMAC0 */ +/* SICREMAP2M5 */ +#define ICU_REMAP_PRR (0xFFE00000U) /* PRR */ +/* SICREMAP2M4 */ +#define ICU_REMAP_RTACT (0xFFC00000U) /* RT-ACT */ + +#define ICU_REMAP15_BASE (ICU_REMAP_RTRAM) /* RTRAM */ +#define ICU_REMAP14_BASE (ICU_REMAP_CC) /* CC63S */ +#define ICU_REMAP13_BASE (ICU_REMAP_PFC) /* PFC,GPIO,LIFC,CPGA,RESET,SYSC */ +#define ICU_REMAP12_BASE (ICU_REMAP_MFIS) /* MFIS */ +#define ICU_REMAP11_BASE (ICU_REMAP_RPC) /* RPC */ +#define ICU_REMAP10_BASE (ICU_REMAP_RTDMAC) /* RT-DMAC0 */ +#define ICU_REMAP9_BASE (ICU_REMAP_SCIF) /* SCIF */ +#define ICU_REMAP8_BASE (ICU_REMAP_MMC) /* MMC */ +#define ICU_REMAP7_BASE (ICU_REMAP_HSCIF) /* HSCIF */ +#define ICU_REMAP6_BASE (ICU_REMAP_DMAC) /* SYS-DMAC0 */ +#define ICU_REMAP5_BASE (ICU_REMAP_PRR) /* PRR,INTC,RT-SRAM protection*/ +#define ICU_REMAP4_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP3_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP2_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP1_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP0_BASE (0x00000000U) /* Reserved */ + +/* Base address offset of each register after remap */ +/* REMAP15(0xEB200000U) */ +/* RT-SRAM */ +#define ICU_REMAP_OFFSET_RTRAM (0x000000U) + +/* REMAP14(0xE6600000U) */ +#define ICU_REMAP_OFFSET_CC63S (0x000000U) +#define ICU_REMAP_OFFSET_AXI (0x184000U) /* (0xE6784000U) */ +#define ICU_REMAP_OFFSET_DBSC (0x190000U) /* (0xE6790000U) */ +#define ICU_REMAP_OFFSET_MSTAT (0x1e0000U) /* (0xE67e0000U) */ +#define ICU_REMAP_OFFSET_QOS (0x1F0000U) /* (0xE67F0000U) */ + +/* REMAP13(0xE6000000U) */ +/* GPIO */ +#define ICU_REMAP_OFFSET_GPIO0 (0x050000U) +#define ICU_REMAP_OFFSET_GPIO1 (0x051000U) +#define ICU_REMAP_OFFSET_GPIO2 (0x052000U) +#define ICU_REMAP_OFFSET_GPIO3 (0x053000U) +#define ICU_REMAP_OFFSET_GPIO4 (0x054000U) +#define ICU_REMAP_OFFSET_GPIO5 (0x055000U) +/* PFC */ +#define ICU_REMAP_OFFSET_PFC (0x060000U) +/* LIFEC */ +#define ICU_REMAP_OFFSET_LIFEC (0x110000U) +/* CPGA */ +#define ICU_REMAP_OFFSET_CPGA (0x150000U) +/* RESET */ +#define ICU_REMAP_OFFSET_RESET (0x160000U) +/* SYSC */ +#define ICU_REMAP_OFFSET_SYSC (0x180000U) +/* THS1 */ +#define ICU_REMAP_OFFSET_THS1 (0x198000U) /* (0xE6198000U) */ + +/* REMAP12(0xE6200000U) */ +/* MFIS */ +#define ICU_REMAP_OFFSET_MFIS (0x060000U) + +/* REMAP11(0xEE200000U) */ +/*RPC*/ +#define ICU_REMAP_OFFSET_RPC (0x000000U) + +/* REMAP10(0xFFC00000U) */ +/* RT-DMA */ +#define ICU_REMAP_OFFSET_RTDMA (0x010000U) + +/* REMAP9(0xE6C00000U) */ +/*SCIF*/ +#define ICU_REMAP_OFFSET_SCIF_0 (0x060000U) +#define ICU_REMAP_OFFSET_SCIF_3 (0x050000U) + +/* REMAP8(0xEE000000U) */ +/* SDHI2/MMC0 */ +#define ICU_REMAP_OFFSET_SDHI (0x140000U) + +/* REMAP7(0xE6400000U) */ +/* HSCIF */ +#define ICU_REMAP_OFFSET_HSCIF0 (0x140000U) + +/* REMAP6(0xE7200000U) */ +/* SYS-DMAC */ +#define ICU_REMAP_OFFSET_SYSDMAC (0x100000U) + +/* REMAP5(0xFFE00000U) */ +/* PRR */ +#define ICU_REMAP_OFFSET_PRR (0x100044U) + +/* REMAP4(0xFFE00000U) */ +/* RT-ACT */ +#define ICU_REMAP_OFFSET_RTACT (0x050800U) + +/* Calculate the base address of each register after remapping */ +#define ICU_REMAP0 (0xFC000000U) +#define ICU_REMAP_CALC( val ) (ICU_REMAP0 + (val * 0x200000U)) + +/* REMAP15(0xEB200000U) */ +#define BASE_RTRAM_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTRAM) + ICU_REMAP_OFFSET_RTRAM) +/* REMAP14(0xE6600000U) */ +#define BASE_AXI_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_AXI) +#define BASE_DBSC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_DBSC) +#define BASE_MSTAT_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_MSTAT) +#define BASE_QOS_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_QOS) +/* REMAP13(0xE6000000U) */ +#define BASE_GPIO_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_GPIO0) +#define BASE_PFC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_PFC) +#define BASE_LIFEC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_LIFEC) +#define BASE_CPG_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_CPGA) +#define BASE_RESET_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_RESET) +#define BASE_SYSC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_SYSC) +#define BASE_THS1_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_THS1) +/* REMAP12(0xE6200000U) */ +#define BASE_MFIS_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_MFIS) + ICU_REMAP_OFFSET_MFIS) +/* REMAP11(0xEE200000U) */ +#define BASE_RPC_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RPC) + ICU_REMAP_OFFSET_RPC) +/* REMAP10(0xFFC00000U) */ +#define BASE_RTDMA_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMA) +/* REMAP9(0xE6C00000U or 0xE6E00000U) */ +#define BASE_SCIF_ADDR_0 (ICU_REMAP_CALC(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF_0) +#define BASE_SCIF_ADDR_3 (ICU_REMAP_CALC(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF_3) +/* REMAP8(0xEE000000U) */ +#define BASE_MMC0_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_MMC) + ICU_REMAP_OFFSET_SDHI) +/* REMAP7(0xE6400000U) */ +#define BASE_HSCIF_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_HSCIF) + ICU_REMAP_OFFSET_HSCIF0) +/* REMAP6(0xE7200000U) */ +#define BASE_DMA_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_DMAC) + ICU_REMAP_OFFSET_SYSDMAC) +/* REMAP5(0xFFE00000U) */ +#define BASE_PRR_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_PRR) + ICU_REMAP_OFFSET_PRR) +/* REMAP4(0xFFE00000U) */ +#define BASE_RTACT_ADDR (ICU_REMAP_CALC(ICU_REMAP_NUM_RTACT) + ICU_REMAP_OFFSET_RTACT) + +/* MFIS */ +#define MFIS_MFISSOFTMDR (BASE_MFIS_ADDR + 0x0600U) /* SOFTMD register */ +#define MFIS_MFISBTSTSR (BASE_MFIS_ADDR + 0x0604U) /* (0xE6260604U) */ +#define MFIS_MFISWACNTR (BASE_MFIS_ADDR + 0x0904U) /* (0xE6260904U) */ /* Write Access Control Register */ + +#endif /* REMAP_REGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_FW/include/rst_register.h b/IPL/SDK/v4h/src/Dummy_FW/include/rst_register.h new file mode 100644 index 0000000..821ecc1 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/include/rst_register.h @@ -0,0 +1,25 @@ +/******************************************************************************* + * Copyright (c) 2020 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : RST register header + ******************************************************************************/ + +#ifndef RST_REGISTER_H_ +#define RST_REGISTER_H_ + +#include + +#define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */ + +#define RST_MODEMR0 (RST_BASE + 0x0000U) /* Mode pin register0 */ +#define RST_MODEMR1 (RST_BASE + 0x0004U) /* Mode pin register1 */ +#define RST_MODEMR0_MD31 (1U << 31U) +#define RST_MODEMR1_MD32 (1U << 0U) + +#define RST_MODEMR0_BOOT_DEV_MASK (0x0000001EU) +#define RST_MODEMR0_BOOT_DEV_HYPERFLASH160 (0x00000004U) +#define RST_MODEMR0_BOOT_DEV_HYPERFLASH80 (0x00000006U) +#define RST_MODEMR0_BOOT_DEV_QSPI_FLASH40 (0x00000008U) +#define RST_MODEMR0_BOOT_DEV_EMMC_50X8 (0x0000001AU) + +#endif /* RST_REGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_FW/include/scif.h b/IPL/SDK/v4h/src/Dummy_FW/include/scif.h new file mode 100644 index 0000000..5a94ed4 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/include/scif.h @@ -0,0 +1,25 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : SCIF driver header + ******************************************************************************/ + +#ifndef SCIF_H_ +#define SCIF_H_ + +/* Define */ +#define PFC_GPSR_SCIF_MASK (0x00000030UL) /* SCIF0/HSCIF0_B RX/TX */ +#define PFC_GPSR_SCIF_VAL (0x00000030UL) /* SCIF0/HSCIF0_B RX/TX */ +#define PFC_IPSR_SCIF_MASK (0x0FF00000UL) /* SCIF0 RX/TX */ +#define PFC_IPSR_SCIF_VAL (0x04400000UL) /* SCIF0 RX/TX */ +#define BIT7 (uint32_t)(1U << 7U) /* Module Stop 2 bit7(SCIF0) */ + +#define CR_CODE (0x0DU) +#define LF_CODE (0x0AU) + +/* Prototype */ +void scif_init(void); +void console_puts(char* str,char rtn); +void console_putc(uint8_t outchar); + +#endif /* SCIF_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_FW/include/scif_register.h b/IPL/SDK/v4h/src/Dummy_FW/include/scif_register.h new file mode 100644 index 0000000..2b06d8e --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/include/scif_register.h @@ -0,0 +1,77 @@ +/******************************************************************************* + * Copyright (c) 2018 Renesas Electronics Corporation. All rights reserved. + * + * DESCRIPTION : SCIF register header + ******************************************************************************/ + + +#ifndef SCIF_REGISTER_H_ +#define SCIF_REGISTER_H_ + +#include + +/* SCIF0 base address */ +/* 0xE6E60000 */ +#define SCIF_BASE_0 (BASE_SCIF_ADDR_0) + +#define SCIF_SCSMR_0 (SCIF_BASE_0 + 0x00U) /* 16 Serial mode register */ +#define SCIF_SCBRR_0 (SCIF_BASE_0 + 0x04U) /* 8 Bit rate register */ +#define SCIF_SCSCR_0 (SCIF_BASE_0 + 0x08U) /* 16 Serial control register */ +#define SCIF_SCFTDR_0 (SCIF_BASE_0 + 0x0CU) /* 8 Transmit FIFO data register */ +#define SCIF_SCFSR_0 (SCIF_BASE_0 + 0x10U) /* 16 Serial status register */ +#define SCIF_SCFRDR_0 (SCIF_BASE_0 + 0x14U) /* 8 Receive FIFO data register */ +#define SCIF_SCFCR_0 (SCIF_BASE_0 + 0x18U) /* 16 FIFO control register */ +#define SCIF_SCFDR_0 (SCIF_BASE_0 + 0x1CU) /* 16 FIFO data count register */ +#define SCIF_SCSPTR_0 (SCIF_BASE_0 + 0x20U) /* 16 Serial port register */ +#define SCIF_SCLSR_0 (SCIF_BASE_0 + 0x24U) /* 16 Line status register */ +#define SCIF_DL_0 (SCIF_BASE_0 + 0x30U) /* 16 Frequency division register */ +#define SCIF_CKS_0 (SCIF_BASE_0 + 0x34U) /* 16 Clock Select register */ +#define SCIF_SCFER_0 (SCIF_BASE_0 + 0x44U) /* 16 FIFO error count register */ +#define SCIF_SCSMRIR_0 (SCIF_BASE_0 + 0x40U) /* 16 Serial mode register */ + +/* SCIF3 base address */ +/* 0xE6C50000 */ +#define SCIF_BASE_3 (BASE_SCIF_ADDR_3) + +#define SCIF_SCSMR_3 (SCIF_BASE_3 + 0x00U) /* 16 Serial mode register */ +#define SCIF_SCBRR_3 (SCIF_BASE_3 + 0x04U) /* 8 Bit rate register */ +#define SCIF_SCSCR_3 (SCIF_BASE_3 + 0x08U) /* 16 Serial control register */ +#define SCIF_SCFTDR_3 (SCIF_BASE_3 + 0x0CU) /* 8 Transmit FIFO data register */ +#define SCIF_SCFSR_3 (SCIF_BASE_3 + 0x10U) /* 16 Serial status register */ +#define SCIF_SCFRDR_3 (SCIF_BASE_3 + 0x14U) /* 8 Receive FIFO data register */ +#define SCIF_SCFCR_3 (SCIF_BASE_3 + 0x18U) /* 16 FIFO control register */ +#define SCIF_SCFDR_3 (SCIF_BASE_3 + 0x1CU) /* 16 FIFO data count register */ +#define SCIF_SCSPTR_3 (SCIF_BASE_3 + 0x20U) /* 16 Serial port register */ +#define SCIF_SCLSR_3 (SCIF_BASE_3 + 0x24U) /* 16 Line status register */ +#define SCIF_DL_3 (SCIF_BASE_3 + 0x30U) /* 16 Frequency division register */ +#define SCIF_CKS_3 (SCIF_BASE_3 + 0x34U) /* 16 Clock Select register */ +#define SCIF_SCFER_3 (SCIF_BASE_3 + 0x44U) /* 16 FIFO error count register */ +#define SCIF_SCSMRIR_3 (SCIF_BASE_3 + 0x40U) /* 16 Serial mode register */ + + +/*HSCIF0 base address*/ +/* 0xE6540000 */ +#define HSCIF_BASE (BASE_HSCIF_ADDR) + +#define HSCIF_HSSMR (HSCIF_BASE + 0x00U) /* 16 Serial mode register */ +#define HSCIF_HSBRR (HSCIF_BASE + 0x04U) /* 8 Bit rate register */ +#define HSCIF_HSSCR (HSCIF_BASE + 0x08U) /* 16 Serial control register */ +#define HSCIF_HSFTDR (HSCIF_BASE + 0x0CU) /* 8 Transmit FIFO data register */ +#define HSCIF_HSFSR (HSCIF_BASE + 0x10U) /* 16 Serial status register */ +#define HSCIF_HSFRDR (HSCIF_BASE + 0x14U) /* 8 Receive FIFO data register */ +#define HSCIF_HSFCR (HSCIF_BASE + 0x18U) /* 16 FIFO control register */ +#define HSCIF_HSFDR (HSCIF_BASE + 0x1CU) /* 16 FIFO data count register */ +#define HSCIF_HSSPTR (HSCIF_BASE + 0x20U) /* 16 Serial port register */ +#define HSCIF_HSLSR (HSCIF_BASE + 0x24U) /* 16 Line status register */ + +#define HSCIF_HSSRR (HSCIF_BASE + 0x40U) /* 16 Sampling rate register */ +#define HSCIF_HSRER (HSCIF_BASE + 0x44U) /* 16 Serial error register */ +#define HSCIF_HSRTGR (HSCIF_BASE + 0x50U) /* 16 RTS output active trigger register */ +#define HSCIF_HSRTRGR (HSCIF_BASE + 0x54U) /* 16 Receive FIFO data count trigger register */ +#define HSCIF_HSTTRGR (HSCIF_BASE + 0x58U) /* 16 Transmit FIFO data count trigger register */ + +#define HSCIF_DL (HSCIF_BASE + 0x30U) /* 16 Frequency division register */ +#define HSCIF_CKS (HSCIF_BASE + 0x34U) /* 16 Clock Select register */ + + +#endif /* SCIF_REGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_FW/include/wdt.h b/IPL/SDK/v4h/src/Dummy_FW/include/wdt.h new file mode 100644 index 0000000..6700ff5 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_FW/include/wdt.h @@ -0,0 +1,33 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : window watchdog timer function header + ******************************************************************************/ + +#ifndef WDT_H__ +#define WDT_H__ + +void wdt_restart(void); + +#endif /* WDT_H__ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/Makefile b/IPL/SDK/v4h/src/Dummy_RTOS/Makefile new file mode 100644 index 0000000..7da2b07 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/Makefile @@ -0,0 +1,138 @@ +################################################### +# makefile +################################################### + +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +INCLUDE_DIR = -Iinclude + +# Process CR52_CORE flag +# 0:core0 1:core1 2:core2 +ifndef CR52_CORE + CR52_CORE := 0 + $(eval $(call add_define,CR52_CORE)) +else + ifeq (${CR52_CORE},0) + $(eval $(call add_define,CR52_CORE)) + else ifeq (${CR52_CORE},1) + $(eval $(call add_define,CR52_CORE)) + else ifeq (${CR52_CORE},2) + $(eval $(call add_define,CR52_CORE)) + else + $(error "Error:CR52_CORE=${CR52_CORE} is not supported.") + endif +endif + +#output file name +ifeq (${CR52_CORE},0) +FILE_NAME = dummy_rtos +else ifeq (${CR52_CORE},1) +FILE_NAME = dummy_rtos1 +else ifeq (${CR52_CORE},2) +FILE_NAME = dummy_rtos2 +endif + +OUTPUT_FILE = $(FILE_NAME).elf + +OUTPUT_DIR = output +OBJECT_DIR = obj + +#object file name +OBJ_FILE = common/scif.o \ + common/div.o \ + common/generic_timer.o \ + rtos/rtos.o \ + rtos/rtos_main.o + +#linker script name +ifeq (${CR52_CORE},0) +MEMORY_DEF = rtos/rtos.ld.S +else ifeq (${CR52_CORE},1) +MEMORY_DEF = rtos/rtos_core1.ld.S +else ifeq (${CR52_CORE},2) +MEMORY_DEF = rtos/rtos_core2.ld.S +endif + +################################################### +# Process LOG_LEVEL flag +ifndef LOG_LEVEL +LOG_LEVEL := 20 +endif +$(eval $(call add_define,LOG_LEVEL)) + +################################################### + +CC = $(CROSS_COMPILE)gcc +CPP = ${CROSS_COMPILE}cpp +AS = ${CROSS_COMPILE}gcc +AR = ${CROSS_COMPILE}ar +LD = $(CROSS_COMPILE)ld +OC = ${CROSS_COMPILE}objcopy +OD = ${CROSS_COMPILE}objdump + +ASFLAGS = -marm -march=armv8-r \ + -nostdinc -ffreestanding -Wa,--fatal-warnings \ + -Werror -Wmissing-include-dirs \ + -c -D__ASSEMBLY \ + $(INCLUDE_DIR) $(DEFINES) + +CFLAGS = -marm -march=armv8-r \ + -nostdinc -ffreestanding -Wall \ + -Werror -Wmissing-include-dirs \ + -std=c99 -c -Os \ + -ffunction-sections -fdata-sections \ + $(INCLUDE_DIR) $(DEFINES) + +CFLAGS += -g +ASFLAGS += -g -Wa,--gdwarf-2 + +LDFLAGS = --fatal-warnings -O1 --gc-sections + +################################################### +.SUFFIXES : .s .c .o + +################################################### +# command + +.PHONY: all +all: $(OBJECT_DIR) $(OUTPUT_DIR) $(OUTPUT_FILE) +################################################### +# Make Directory +################################################### +$(OBJECT_DIR): + mkdir -p $(OBJECT_DIR) + +$(OUTPUT_DIR): + mkdir -p $(OUTPUT_DIR) + +################################################### +# Linker +################################################### +$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE) + $(LD) $(OBJ_FILE) \ + -T $(MEMORY_DEF) \ + -o $(OUTPUT_FILE) \ + $(LDFLAGS) \ + -Map $(FILE_NAME).map + + $(OC) -O srec --srec-forceS3 $(OUTPUT_FILE) $(FILE_NAME).srec + $(OC) -O binary $(OUTPUT_FILE) $(FILE_NAME).bin + $(OD) -dx $(OUTPUT_FILE) > $(FILE_NAME).dump + + +################################################### +# Compile +################################################### + +%.o:../%.c + $(CC) $(CFLAGS) -o $@ $< + +%.o:../%.s + $(AS) $(ASFLAGS) -o $@ $< + + +.PHONY: clean +clean: + $(RM) $(OBJ_FILE) $(OUTPUT_FILE) $(FILE_NAME)* diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/common/div.s b/IPL/SDK/v4h/src/Dummy_RTOS/common/div.s new file mode 100644 index 0000000..b6f4113 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/common/div.s @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2015-2016, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + .global __aeabi_uidivmod + +/***************************************************************************** + * input: + * r0: divided + * r1: divisor + * + * output + * r0: quot + * r1: rem + *****************************************************************************/ + +__aeabi_uidivmod: + push {r4, r5} + mov r4, #0 + mov r5, #1 + + clz r2, r1 + mov r3, r1, LSL r2 +1: + cmp r3, r0 + subls r0, r0, r3 + addls r4, r5, LSL r2 + + lsr r3, r3, #1 + subs r2, r2, #1 + bpl 1b + + mov r1, r0 + mov r0, r4 + + pop {r4, r5} + bx lr + + .end diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/common/generic_timer.c b/IPL/SDK/v4h/src/Dummy_RTOS/common/generic_timer.c new file mode 100644 index 0000000..8faf9b2 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/common/generic_timer.c @@ -0,0 +1,108 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + +/******************************************************************************* + * DESCRIPTION : generic timer + ******************************************************************************/ +/****************************************************************************** + * @file generic_timer.c + * - Version : 0.01 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 14.09.2023 0.01 First Release + *****************************************************************************/ + +#include +#include +#include "scif.h" + +#define RCAR_CNTC_EXTAL (16666600U) /* V4H/V4M : 16.666600MHz */ + +#define RCAR_CONV_MICROSEC (1000000U) + +static inline uint32_t get_cntfrq(void) +{ + uint32_t freq; + __asm__ volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); + + return(freq); +} + +static inline void set_cntfrq(uint32_t reg_cntfid) +{ + __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (reg_cntfid)); +} + +static inline uint64_t get_cntpct(void) +{ + uint64_t base_count; + __asm__ volatile ("mrrc p15, 0, %Q0, %R0, c14" : "=r" (base_count)); + + return(base_count); +} + +void generic_timer_init(void) +{ + /* Update memory mapped and register based freqency */ + /* AArch32:cntfrq */ + set_cntfrq(RCAR_CNTC_EXTAL); +} +/* End of function generic_timer_init(void) */ + +void micro_wait(uint64_t micro_sec) +{ + uint64_t base_count = 0U; + uint64_t get_count = 0U; + uint64_t wait_time = 0U; + uint32_t freq = 0U; + + + /* cntfrq */ + freq = get_cntfrq(); + /* cntpct */ + base_count = get_cntpct(); + + micro_sec *= freq; + while (micro_sec > wait_time) + { + /* cntpct */ + get_count = get_cntpct(); + + /* INT30-C Pre confirmation */ + if (get_count < base_count) + { + PutStr("micro_wait(Timer value error!!).", 1U); + while(1U); /* panic */ + } + else + { + wait_time = ((get_count - base_count) * RCAR_CONV_MICROSEC); + } + } +} +/* End of function micro_wait(uint64_t micro_sec) */ + diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/common/scif.c b/IPL/SDK/v4h/src/Dummy_RTOS/common/scif.c new file mode 100644 index 0000000..5139b20 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/common/scif.c @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2015-2018, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include "reg_rcar_gen3.h" + +#define RST_MODEMR0 0xE6160000 // R 32 Mode Monitor Register +#define RST_MODEMR1 0xE6160004 // R 32 Mode Monitor Register2 + +#define MODEMR0_MD31_V3U (0x80000000U) +#define MODEMR1_MD32_V3U (0x00000001U) +#define MODEMR_SCIF_115200_V3U (0x00000000U) +#define MODEMR_SCIF_921600_V3U (0x80000000U) +#define MODEMR_SCIF_1843200_V3U (0x00000001U) +#define MODEMR_SCIF_3000000_V3U (0x80000001U) + +static void (*putc)(char); + +static void scif0_PutChar(char outchar); +static void scif3_PutChar(char outchar); +static void hscif_PutChar(char outchar); + +/************************************************************************/ +/*NAME : PutStr */ +/************************************************************************/ +void PutStr(const char *str,char rtn) +{ + while(*str){ + PutChar(*str); + str++; + } + if(rtn == 1){ + PutChar(CR_CODE); + PutChar(LF_CODE); + } +} + +void scif_init(void) +{ + uint32_t product; + uint32_t modemr0; + uint32_t modemr1; + + product = *((volatile uint32_t*)RCAR_PRR) & RCAR_PRODUCT_MASK; + switch (product) { + case RCAR_PRODUCT_S4: + modemr0 = *((volatile uint32_t*)RST_MODEMR0) & MODEMR0_MD31_V3U; /* bit31 */ + modemr1 = *((volatile uint32_t*)RST_MODEMR1) & MODEMR1_MD32_V3U; /* bit0 */ + + switch (modemr0 | modemr1) { + case MODEMR_SCIF_115200_V3U: /* 0x00000000 */ + putc = scif3_PutChar; + break; + case MODEMR_SCIF_921600_V3U: /* 0x80000000 */ + case MODEMR_SCIF_1843200_V3U: /* 0x00000001 */ + case MODEMR_SCIF_3000000_V3U: /* 0x80000001 */ + putc = hscif_PutChar; + break; + default: + break; + } + break; + case RCAR_PRODUCT_V4H: + case RCAR_PRODUCT_V4M: + modemr0 = *((volatile uint32_t*)RST_MODEMR0) & MODEMR0_MD31_V3U; /* bit31 */ + modemr1 = *((volatile uint32_t*)RST_MODEMR1) & MODEMR1_MD32_V3U; /* bit0 */ + + switch (modemr0 | modemr1) { + case MODEMR_SCIF_115200_V3U: /* 0x00000000 */ + putc = scif0_PutChar; + break; + case MODEMR_SCIF_921600_V3U: /* 0x80000000 */ + case MODEMR_SCIF_1843200_V3U: /* 0x00000001 */ + case MODEMR_SCIF_3000000_V3U: /* 0x80000001 */ + putc = hscif_PutChar; + break; + default: + break; + } + break; + default: + break; + } +} + +void PutChar(char outChar) +{ + putc(outChar); +} + +static void scif0_PutChar(char outChar) +{ + while(!(0x60 & *((volatile uint16_t*)SCIF_SCFSR_0) )); + *((volatile uint8_t*)SCIF_SCFTDR_0) = outChar; + *((volatile uint16_t*)SCIF_SCFSR_0) &= ~0x60; /* TEND,TDFE clear */ +} + +static void scif3_PutChar(char outChar) +{ + while(!(0x60 & *((volatile uint16_t*)SCIF_SCFSR_3) )); + *((volatile uint8_t*)SCIF_SCFTDR_3) = outChar; + *((volatile uint16_t*)SCIF_SCFSR_3) &= ~0x60; /* TEND,TDFE clear */ +} + +static void hscif_PutChar(char outChar) +{ + while(!(0x60 & *((volatile uint16_t*)HSCIF_HSFSR) )); + *((volatile uint8_t*)HSCIF_HSFTDR) = outChar; + *((volatile uint16_t*)HSCIF_HSFSR) &= ~0x60; /* TEND,TDFE clear */ +} diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/debug.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/debug.h new file mode 100644 index 0000000..d198c32 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/debug.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +#include + +/* The log output macros print output to the console. These macros produce + * compiled log output only if the LOG_LEVEL defined in the makefile (or the + * make command line) is greater or equal than the level required for that + * type of log output. + * The format expected is the same as for printf(). For example: + * INFO("Info %s.\n", "message") -> INFO: Info message. + * WARN("Warning %s.\n", "message") -> WARNING: Warning message. + */ + +#define LOG_LEVEL_NONE 0 +#define LOG_LEVEL_ERROR 10 +#define LOG_LEVEL_NOTICE 20 +#define LOG_LEVEL_WARNING 30 +#define LOG_LEVEL_INFO 40 +#define LOG_LEVEL_VERBOSE 50 + + +#if LOG_LEVEL >= LOG_LEVEL_NOTICE +# define NOTICE(...) tf_printf("NOTICE: " __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_ERROR +# define ERROR(...) tf_printf("ERROR: " __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_WARNING +# define WARN(...) tf_printf("WARNING: " __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_INFO +# define INFO(...) tf_printf("INFO: " __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_LEVEL_VERBOSE +# define VERBOSE(...) tf_printf("VERBOSE: " __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + + +void __dead2 do_panic(void); +#define panic() do_panic() + +void tf_printf(const char *fmt, ...) __printflike(1, 2); + +#endif /* __DEBUG_H__ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/machine/_stdint.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/machine/_stdint.h new file mode 100644 index 0000000..e36c659 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/machine/_stdint.h @@ -0,0 +1,164 @@ +/*- + * Copyright (c) 2001, 2002 Mike Barcroft + * Copyright (c) 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Klaus Klein. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE__STDINT_H_ +#define _MACHINE__STDINT_H_ + +#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) + +#define INT8_C(c) (c) +#define INT16_C(c) (c) +#define INT32_C(c) (c) +#define INT64_C(c) (c ## L) + +#define UINT8_C(c) (c) +#define UINT16_C(c) (c) +#define UINT32_C(c) (c ## U) +#define UINT64_C(c) (c ## UL) + +#define INTMAX_C(c) INT64_C(c) +#define UINTMAX_C(c) UINT64_C(c) + +#endif /* !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) */ + +#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) + +/* + * ISO/IEC 9899:1999 + * 7.18.2.1 Limits of exact-width integer types + */ +/* Minimum values of exact-width signed integer types. */ +#define INT8_MIN (-0x7f-1) +#define INT16_MIN (-0x7fff-1) +#define INT32_MIN (-0x7fffffff-1) +#define INT64_MIN (-0x7fffffffffffffffL-1) + +/* Maximum values of exact-width signed integer types. */ +#define INT8_MAX 0x7f +#define INT16_MAX 0x7fff +#define INT32_MAX 0x7fffffff +#define INT64_MAX 0x7fffffffffffffffL + +/* Maximum values of exact-width unsigned integer types. */ +#define UINT8_MAX 0xff +#define UINT16_MAX 0xffff +#define UINT32_MAX 0xffffffffU +#define UINT64_MAX 0xffffffffffffffffUL + +/* + * ISO/IEC 9899:1999 + * 7.18.2.2 Limits of minimum-width integer types + */ +/* Minimum values of minimum-width signed integer types. */ +#define INT_LEAST8_MIN INT8_MIN +#define INT_LEAST16_MIN INT16_MIN +#define INT_LEAST32_MIN INT32_MIN +#define INT_LEAST64_MIN INT64_MIN + +/* Maximum values of minimum-width signed integer types. */ +#define INT_LEAST8_MAX INT8_MAX +#define INT_LEAST16_MAX INT16_MAX +#define INT_LEAST32_MAX INT32_MAX +#define INT_LEAST64_MAX INT64_MAX + +/* Maximum values of minimum-width unsigned integer types. */ +#define UINT_LEAST8_MAX UINT8_MAX +#define UINT_LEAST16_MAX UINT16_MAX +#define UINT_LEAST32_MAX UINT32_MAX +#define UINT_LEAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.3 Limits of fastest minimum-width integer types + */ +/* Minimum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MIN INT32_MIN +#define INT_FAST16_MIN INT32_MIN +#define INT_FAST32_MIN INT32_MIN +#define INT_FAST64_MIN INT64_MIN + +/* Maximum values of fastest minimum-width signed integer types. */ +#define INT_FAST8_MAX INT32_MAX +#define INT_FAST16_MAX INT32_MAX +#define INT_FAST32_MAX INT32_MAX +#define INT_FAST64_MAX INT64_MAX + +/* Maximum values of fastest minimum-width unsigned integer types. */ +#define UINT_FAST8_MAX UINT32_MAX +#define UINT_FAST16_MAX UINT32_MAX +#define UINT_FAST32_MAX UINT32_MAX +#define UINT_FAST64_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.4 Limits of integer types capable of holding object pointers + */ +#define INTPTR_MIN INT64_MIN +#define INTPTR_MAX INT64_MAX +#define UINTPTR_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.2.5 Limits of greatest-width integer types + */ +#define INTMAX_MIN INT64_MIN +#define INTMAX_MAX INT64_MAX +#define UINTMAX_MAX UINT64_MAX + +/* + * ISO/IEC 9899:1999 + * 7.18.3 Limits of other integer types + */ +/* Limits of ptrdiff_t. */ +#define PTRDIFF_MIN INT64_MIN +#define PTRDIFF_MAX INT64_MAX + +/* Limits of sig_atomic_t. */ +#define SIG_ATOMIC_MIN INT32_MIN +#define SIG_ATOMIC_MAX INT32_MAX + +/* Limit of size_t. */ +#define SIZE_MAX UINT64_MAX + +#ifndef WCHAR_MIN /* Also possibly defined in */ +/* Limits of wchar_t. */ +#define WCHAR_MIN INT32_MIN +#define WCHAR_MAX INT32_MAX +#endif + +/* Limits of wint_t. */ +#define WINT_MIN INT32_MIN +#define WINT_MAX INT32_MAX + +#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ + +#endif /* !_MACHINE__STDINT_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/machine/_types.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/machine/_types.h new file mode 100644 index 0000000..0f1e14e --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/machine/_types.h @@ -0,0 +1,110 @@ +/*- + * Copyright (c) 2002 Mike Barcroft + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * From: @(#)ansi.h 8.2 (Berkeley) 1/4/94 + * From: @(#)types.h 8.3 (Berkeley) 1/5/94 + * $FreeBSD$ + */ + +#ifndef _MACHINE__TYPES_H_ +#define _MACHINE__TYPES_H_ + +#ifndef _SYS_CDEFS_H_ +#error this file needs sys/cdefs.h as a prerequisite +#endif + +/* + * Basic types upon which most other types are built. + */ +typedef __signed char __int8_t; +typedef unsigned char __uint8_t; +typedef short __int16_t; +typedef unsigned short __uint16_t; +typedef int __int32_t; +typedef unsigned int __uint32_t; +typedef long long __int64_t; +typedef unsigned long long __uint64_t; + +/* + * Standard type definitions. + */ +typedef __int32_t __clock_t; /* clock()... */ +typedef __int32_t __critical_t; +typedef double __double_t; +typedef float __float_t; +typedef __int32_t __intfptr_t; +typedef __int32_t __intmax_t; +typedef __int32_t __intptr_t; +typedef __int32_t __int_fast8_t; +typedef __int32_t __int_fast16_t; +typedef __int32_t __int_fast32_t; +typedef __int32_t __int_fast64_t; +typedef __int8_t __int_least8_t; +typedef __int16_t __int_least16_t; +typedef __int32_t __int_least32_t; +typedef __int64_t __int_least64_t; +typedef __int32_t __ptrdiff_t; /* ptr1 - ptr2 */ +typedef __int32_t __register_t; +typedef __int32_t __segsz_t; /* segment size (in pages) */ +typedef __uint32_t __size_t; /* sizeof() */ +typedef __int32_t __ssize_t; /* byte count or error */ +typedef __int32_t __time_t; /* time()... */ +typedef __uint32_t __uintfptr_t; +typedef __uint64_t __uintmax_t; +typedef __uint32_t __uintptr_t; +typedef __uint32_t __uint_fast8_t; +typedef __uint32_t __uint_fast16_t; +typedef __uint32_t __uint_fast32_t; +typedef __uint64_t __uint_fast64_t; +typedef __uint8_t __uint_least8_t; +typedef __uint16_t __uint_least16_t; +typedef __uint32_t __uint_least32_t; +typedef __uint64_t __uint_least64_t; +typedef __uint32_t __u_register_t; +typedef __uint32_t __vm_offset_t; +typedef __int32_t __vm_ooffset_t; +typedef __uint32_t __vm_paddr_t; +typedef __uint32_t __vm_pindex_t; +typedef __uint32_t __vm_size_t; + +/* + * Unusual type definitions. + */ +#ifdef __GNUCLIKE_BUILTIN_VARARGS +typedef __builtin_va_list __va_list; /* internally known to gcc */ +#else +typedef char * __va_list; +#endif /* __GNUCLIKE_BUILTIN_VARARGS */ +#if defined(__GNUCLIKE_BUILTIN_VAALIST) && !defined(__GNUC_VA_LIST) \ + && !defined(__NO_GNUC_VA_LIST) +#define __GNUC_VA_LIST +typedef __va_list __gnuc_va_list; /* compatibility w/GNU headers*/ +#endif + +#endif /* !_MACHINE__TYPES_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/reg_rcar_gen3.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/reg_rcar_gen3.h new file mode 100644 index 0000000..917f7e3 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/reg_rcar_gen3.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __H_REG_RCAR_GEN3_ +#define __H_REG_RCAR_GEN3_ + +/*********************** RCarGen3_MFI *************************/ +#define MFISSOFTMDR 0xE6260600 //SOFTMD register +#define MFISSHESTSR 0xE6260604 //SHE status register + +/*********************** RCarGen3_LIFEC *************************/ +#define LIFEC_CC_LCS 0xE6110028 // cc_lcs Life cycle state read + +/*********************** RCarGen3_RST *************************/ +#define RST_MODEMR 0xE6160060 // Mode Monitor Register + +/*********************** RCarGen3_DMA *************************/ +#define DMA_DMAOR 0xE6700060 //DMA operation register (for west channel) +#define DMA_CHCLR 0xE6700080 //DMA channel clear register (for west channel) +#define DMA_SAR0 0xE6708000 //DMA source address register +#define DMA_DAR0 0xE6708004 //DMA destination address register +#define DMA_TCR0 0xE6708008 //DMA transfer count register +#define DMA_CHCR0 0xE670800C //DMA channel control register +#define DMA_DMARS0 0xE6708040 //DMA extended resource register + +/*********************** RCarGen3_RPC/QSPI *************************/ +//RPC/QSPI + +#define RPC_BASE 0xEE200000 +#define RPC_CMNCR (RPC_BASE + 0x0000) // +//#define RPC_DRCR (RPC_BASE + 0x000C) // +//#define RPC_DRCMR (RPC_BASE + 0x0010) // +//#define RPC_DRENR (RPC_BASE + 0x001C) // +#define RPC_SMCR (RPC_BASE + 0x0020) // +#define RPC_SMCMR (RPC_BASE + 0x0024) // +#define RPC_SMENR (RPC_BASE + 0x0030) // +#define RPC_CMNSR (RPC_BASE + 0x0048) // +//#define RPC_DRDMCR (RPC_BASE + 0x0058) // +//#define RPC_DRDRENR (RPC_BASE + 0x005C) // +//#define RPC_PHY_OFFSET1 (RPC_BASE + 0x0080) // +#define RPC_PHY_INT (RPC_BASE + 0x0088) // + + +/*********************** RCarH3_PFC *************************/ +// 5 . PFC + +#define PFC_BASE 0xE6060000 +#define RCarH3_PFC_PMMR (PFC_BASE + 0x0000) // LSI Multiplexed Pin Setting Mask Register +#define RCarH3_PFC_GPSR5 (PFC_BASE + 0x0114) // GPIO/peripheral function select register 5 +#define RCarH3_PFC_IPSR12 (PFC_BASE + 0x0230) // Peripheral function select register 12 +#define RCarH3_PFC_MOD_SEL1 (PFC_BASE + 0x0504) // Module select register 1 + + + +/*********************** RCarH3_SCIF ****************************************************/ +// 51 . Serial Communication Interface with FIFO (SCIF) +/* H3 SCIF2 */ +#define H3_SCIF2_BASE 0xE6E88000 + +#define RCarH3_SCIF2_SCSMR (H3_SCIF2_BASE + 0x00) // 16 Serial mode register +#define RCarH3_SCIF2_SCBRR (H3_SCIF2_BASE + 0x04) // 8 Bit rate register +#define RCarH3_SCIF2_SCSCR (H3_SCIF2_BASE + 0x08) // 16 Serial control register +#define RCarH3_SCIF2_SCFTDR (H3_SCIF2_BASE + 0x0C) // 8 Transmit FIFO data register +#define RCarH3_SCIF2_SCFSR (H3_SCIF2_BASE + 0x10) // 16 Serial status register +#define RCarH3_SCIF2_SCFRDR (H3_SCIF2_BASE + 0x14) // 8 Receive FIFO data register +#define RCarH3_SCIF2_SCFCR (H3_SCIF2_BASE + 0x18) // 16 FIFO control register +#define RCarH3_SCIF2_SCFDR (H3_SCIF2_BASE + 0x1C) // 16 FIFO data count register +#define RCarH3_SCIF2_SCSPTR (H3_SCIF2_BASE + 0x20) // 16 Serial port register +#define RCarH3_SCIF2_SCLSR (H3_SCIF2_BASE + 0x24) // 16 Line status register +#define RCarH3_SCIF2_DL (H3_SCIF2_BASE + 0x30) // 16 Frequency division register +#define RCarH3_SCIF2_CKS (H3_SCIF2_BASE + 0x34) // 16 Clock Select register +#define RCarH3_SCIF2_SCFER (H3_SCIF2_BASE + 0x44) // 16 FIFO error count register + +#define RCarH3_SCIF2_SCSMRIR (H3_SCIF2_BASE + 0x40) // 16 Serial mode register + + + +/*********************** RCarH3_CPG_Module Standby, Software Reset *************************/ +// 7A . Module Standby, Software Reset + +#define H3_CPG_MSTPRST_BASE 0xE6150000 + +#define RCarH3_CPG_MSTPSR3 (H3_CPG_MSTPRST_BASE+0x0048) // Module stop status register 3 +#define RCarH3_CPG_SMSTPCR3 (H3_CPG_MSTPRST_BASE+0x013C) // System module stop control register 3 +//#define RCarH3_CPG_SRCR3 (H3_CPG_MSTPRST_BASE+0x00B8) // Software reset register 3 + +#define RCarH3_CPG_CPGWPCR (H3_CPG_MSTPRST_BASE+0x0904) // CPG Write Protect Control Register +#define RCarH3_CPG_CPGWPR (H3_CPG_MSTPRST_BASE+0x0900) // CPG Write Protect Register + +/*********************** RCarGen4_PRR *************************/ +#define RCAR_PRR (0xFFF00044U) /* Product register */ +#define RCAR_PRODUCT_MASK (0x00007F00U) +#define RCAR_CUT_MASK (0x000000FFU) +#define RCAR_PRODUCT_H3 (0x00004F00U) +#define RCAR_PRODUCT_M3 (0x00005200U) +#define RCAR_PRODUCT_S4 (0x00005A00U) +#define RCAR_PRODUCT_V4H (0x00005C00U) +#define RCAR_PRODUCT_V4M (0x00005D00U) +#define RCAR_CUT_ES10 (0x00000000U) +#define RCAR_CUT_ES11 (0x00000001U) +#define RCAR_MAJOR_MASK (0x000000F0U) +#define RCAR_MINOR_MASK (0x0000000FU) +#define RCAR_PRODUCT_SHIFT (8U) +#define RCAR_MAJOR_SHIFT (4U) +#define RCAR_MINOR_SHIFT (0U) +#define RCAR_MAJOR_OFFSET (1U) + + +#endif /* __H_REG_RCAR_GEN3_ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/scif.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/scif.h new file mode 100644 index 0000000..4ceb77a --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/scif.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2015-2018, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SCIF_H__ +#define __SCIF_H__ + + +//SCIF0 +#define SCIF_BASE_0 (0xE6E60000U) +#define SCIF_SCSMR_0 (SCIF_BASE_0 + 0x0000) // R/W 16 Serial mode register +#define SCIF_SCBRR_0 (SCIF_BASE_0 + 0x0004) // R/W 8 Bit rate register +#define SCIF_SCSCR_0 (SCIF_BASE_0 + 0x0008) // R/W 16 Serial control register +#define SCIF_SCFTDR_0 (SCIF_BASE_0 + 0x000C) // W 8 Transmit FIFO data register +#define SCIF_SCFSR_0 (SCIF_BASE_0 + 0x0010) // R/W 16 Serial status register +#define SCIF_SCFRDR_0 (SCIF_BASE_0 + 0x0014) // R 8 Receive FIFO data register +#define SCIF_SCFCR_0 (SCIF_BASE_0 + 0x0018) // R/W 16 FIFO control register +#define SCIF_SCFDR_0 (SCIF_BASE_0 + 0x001C) // R 16 FIFO data count register +#define SCIF_SCSPTR_0 (SCIF_BASE_0 + 0x0020) // R/W 16 Serial port register +#define SCIF_SCLSR_0 (SCIF_BASE_0 + 0x0024) // R/W 16 Line status register +#define SCIF_DL_0 (SCIF_BASE_0 + 0x0030) // R/W 16 Frequency division register +#define SCIF_CKS_0 (SCIF_BASE_0 + 0x0034) // R/W 16 Clock Select register + +//SCIF3 +#define SCIF_BASE_3 (0xE6C50000U) +#define SCIF_SCSMR_3 (SCIF_BASE_3 + 0x0000) // R/W 16 Serial mode register +#define SCIF_SCBRR_3 (SCIF_BASE_3 + 0x0004) // R/W 8 Bit rate register +#define SCIF_SCSCR_3 (SCIF_BASE_3 + 0x0008) // R/W 16 Serial control register +#define SCIF_SCFTDR_3 (SCIF_BASE_3 + 0x000C) // W 8 Transmit FIFO data register +#define SCIF_SCFSR_3 (SCIF_BASE_3 + 0x0010) // R/W 16 Serial status register +#define SCIF_SCFRDR_3 (SCIF_BASE_3 + 0x0014) // R 8 Receive FIFO data register +#define SCIF_SCFCR_3 (SCIF_BASE_3 + 0x0018) // R/W 16 FIFO control register +#define SCIF_SCFDR_3 (SCIF_BASE_3 + 0x001C) // R 16 FIFO data count register +#define SCIF_SCSPTR_3 (SCIF_BASE_3 + 0x0020) // R/W 16 Serial port register +#define SCIF_SCLSR_3 (SCIF_BASE_3 + 0x0024) // R/W 16 Line status register +#define SCIF_DL_3 (SCIF_BASE_3 + 0x0030) // R/W 16 Frequency division register +#define SCIF_CKS_3 (SCIF_BASE_3 + 0x0034) // R/W 16 Clock Select register + +/* HSCIF0 */ +#define HSCIF_BASE (0xE6540000U) +#define HSCIF_HSSMR (HSCIF_BASE + 0x0000U) // R/W 16 Serial mode register +#define HSCIF_HSBRR (HSCIF_BASE + 0x0004U) // R/W 8 Bit rate register +#define HSCIF_HSSCR (HSCIF_BASE + 0x0008U) // R/W 16 Serial control register +#define HSCIF_HSFTDR (HSCIF_BASE + 0x000CU) // W 8 Transmit FIFO data register +#define HSCIF_HSFSR (HSCIF_BASE + 0x0010U) // R/W 16 Serial status register +#define HSCIF_HSFRDR (HSCIF_BASE + 0x0014U) // R 8 Receive FIFO data register +#define HSCIF_HSFCR (HSCIF_BASE + 0x0018U) // R/W 16 FIFO control register +#define HSCIF_HSFDR (HSCIF_BASE + 0x001CU) // R 16 FIFO data count register +#define HSCIF_HSSPTR (HSCIF_BASE + 0x0020U) // R/W 16 Serial port register +#define HSCIF_HSLSR (HSCIF_BASE + 0x0024U) // R/W 16 Line status register +#define HSCIF_HSSRR (HSCIF_BASE + 0x0040U) // R/W 16 Sampling rate register +/* BRG */ +#define HSCIF_DL (HSCIF_BASE + 0x0030U) // R/W 16 Frequency division register +#define HSCIF_CKS (HSCIF_BASE + 0x0034U) // R/W 16 Clock select register + +#define CR_CODE (0x0DU) +#define LF_CODE (0x0AU) + +void scif_init(void); +void PutStr(const char *str,char rtn); +void PutChar(char outChar); + + +#endif /* __SCIF_H__ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/stdarg.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/stdarg.h new file mode 100644 index 0000000..c315dfc --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/stdarg.h @@ -0,0 +1,75 @@ +/*- + * Copyright (c) 2002 David E. O'Brien. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _MACHINE_STDARG_H_ +#define _MACHINE_STDARG_H_ + +#include +#include + +#ifndef _VA_LIST_DECLARED +#define _VA_LIST_DECLARED +typedef __va_list va_list; +#endif + +#ifdef __GNUCLIKE_BUILTIN_STDARG + +#define va_start(ap, last) \ + __builtin_va_start((ap), (last)) + +#define va_arg(ap, type) \ + __builtin_va_arg((ap), type) + +#define __va_copy(dest, src) \ + __builtin_va_copy((dest), (src)) + +#if __ISO_C_VISIBLE >= 1999 +#define va_copy(dest, src) \ + __va_copy(dest, src) +#endif + +#define va_end(ap) \ + __builtin_va_end(ap) + +#elif defined(lint) +/* Provide a fake implementation for lint's benefit */ +#define __va_size(type) \ + (((sizeof(type) + sizeof(long) - 1) / sizeof(long)) * sizeof(long)) +#define va_start(ap, last) \ + ((ap) = (va_list)&(last) + __va_size(last)) +#define va_arg(ap, type) \ + (*(type *)((ap) += __va_size(type), (ap) - __va_size(type))) +#define va_end(ap) + +#else +#error this file needs to be ported to your compiler +#endif + +#endif /* !_MACHINE_STDARG_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/stddef.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/stddef.h new file mode 100644 index 0000000..ea88214 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/stddef.h @@ -0,0 +1,64 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stddef.h 8.1 (Berkeley) 6/2/93 + * + * $FreeBSD$ + */ + +#ifndef _STDDEF_H_ +#define _STDDEF_H_ + +#include +#include +#include + +typedef __ptrdiff_t ptrdiff_t; + +#if __BSD_VISIBLE +#ifndef _RUNE_T_DECLARED +typedef __rune_t rune_t; +#define _RUNE_T_DECLARED +#endif +#endif + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#ifndef __cplusplus +#ifndef _WCHAR_T_DECLARED +typedef __wchar_t wchar_t; +#define _WCHAR_T_DECLARED +#endif +#endif + +#define offsetof(type, member) __offsetof(type, member) + +#endif /* _STDDEF_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/stdint.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/stdint.h new file mode 100644 index 0000000..aa5ac81 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/stdint.h @@ -0,0 +1,74 @@ +/*- + * Copyright (c) 2001 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS_STDINT_H_ +#define _SYS_STDINT_H_ + +#include +#include + +#include +#include + +typedef __int_least8_t int_least8_t; +typedef __int_least16_t int_least16_t; +typedef __int_least32_t int_least32_t; +typedef __int_least64_t int_least64_t; + +typedef __uint_least8_t uint_least8_t; +typedef __uint_least16_t uint_least16_t; +typedef __uint_least32_t uint_least32_t; +typedef __uint_least64_t uint_least64_t; + +typedef __int_fast8_t int_fast8_t; +typedef __int_fast16_t int_fast16_t; +typedef __int_fast32_t int_fast32_t; +typedef __int_fast64_t int_fast64_t; + +typedef __uint_fast8_t uint_fast8_t; +typedef __uint_fast16_t uint_fast16_t; +typedef __uint_fast32_t uint_fast32_t; +typedef __uint_fast64_t uint_fast64_t; + +#ifndef _INTMAX_T_DECLARED +typedef __intmax_t intmax_t; +#define _INTMAX_T_DECLARED +#endif +#ifndef _UINTMAX_T_DECLARED +typedef __uintmax_t uintmax_t; +#define _UINTMAX_T_DECLARED +#endif + +/* GNU and Darwin define this and people seem to think it's portable */ +#if defined(UINTPTR_MAX) && defined(UINT64_MAX) && (UINTPTR_MAX == UINT64_MAX) +#define __WORDSIZE 64 +#else +#define __WORDSIZE 32 +#endif + +#endif /* !_SYS_STDINT_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/stdio.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/stdio.h new file mode 100644 index 0000000..57e5c7f --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/stdio.h @@ -0,0 +1,78 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Chris Torek. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)stdio.h 8.5 (Berkeley) 4/29/95 + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2013-2014, ARM Limited and Contributors. + * All rights reserved. + */ + + +#ifndef _STDIO_H_ +#define _STDIO_H_ + +#include +#include +#include + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +#ifndef _SSIZE_T_DECLARED +#define _SSIZE_T_DECLARED +typedef __ssize_t ssize_t; +#endif + +#define EOF (-1) + +int printf(const char * __restrict, ...) __printflike(1, 2); +int putchar(int); +int puts(const char *); +int sprintf(char * __restrict, const char * __restrict, ...) + __printflike(2, 3); +int vsprintf(char * __restrict, const char * __restrict, + __va_list) __printflike(2, 0); + +int sscanf(const char *__restrict, char const *__restrict, ...); + +#if __ISO_C_VISIBLE >= 1999 +int snprintf(char * __restrict, size_t, const char * __restrict, + ...) __printflike(3, 4); +int vsnprintf(char * __restrict, size_t, const char * __restrict, + __va_list) __printflike(3, 0); +#endif + +#endif /* !_STDIO_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/string.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/string.h new file mode 100644 index 0000000..61e8102 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/string.h @@ -0,0 +1,66 @@ +/*- + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)string.h 8.1 (Berkeley) 6/2/93 + * $FreeBSD$ + */ + +/* + * Portions copyright (c) 2013-2014, ARM Limited and Contributors. + * All rights reserved. + */ + +#ifndef _STRING_H_ +#define _STRING_H_ + +#include +#include +#include + +#ifndef _SIZE_T_DECLARED +typedef __size_t size_t; +#define _SIZE_T_DECLARED +#endif + +__BEGIN_DECLS + +void *memchr(const void *, int, size_t) __pure; +int memcmp(const void *, const void *, size_t) __pure; +void *memcpy(void * __restrict, const void * __restrict, size_t); +void *memmove(void *, const void *, size_t); +void *memset(void *, int, size_t); + +char *strchr(const char *, int) __pure; +int strcmp(const char *, const char *) __pure; +size_t strlen(const char *) __pure; +int strncmp(const char *, const char *, size_t) __pure; +int strcasecmp(const char *, const char *); + +__END_DECLS + +#endif /* _STRING_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/sys/_null.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/sys/_null.h new file mode 100644 index 0000000..92706c6 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/sys/_null.h @@ -0,0 +1,47 @@ +/*- + * Copyright (c) 2003 Marcel Moolenaar + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef NULL + +#if !defined(__cplusplus) +#define NULL ((void *)0) +#else +#if __cplusplus >= 201103L +#define NULL nullptr +#elif defined(__GNUG__) && defined(__GNUC__) && __GNUC__ >= 4 +#define NULL __null +#else +#if defined(__LP64__) +#define NULL (0L) +#else +#define NULL 0 +#endif /* __LP64__ */ +#endif /* __GNUG__ */ +#endif /* !__cplusplus */ + +#endif diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/sys/_stdint.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/sys/_stdint.h new file mode 100644 index 0000000..d0f9249 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/sys/_stdint.h @@ -0,0 +1,82 @@ +/*- + * Copyright (c) 2011 David E. O'Brien + * Copyright (c) 2001 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS__STDINT_H_ +#define _SYS__STDINT_H_ + +#ifndef _INT8_T_DECLARED +typedef __int8_t int8_t; +#define _INT8_T_DECLARED +#endif + +#ifndef _INT16_T_DECLARED +typedef __int16_t int16_t; +#define _INT16_T_DECLARED +#endif + +#ifndef _INT32_T_DECLARED +typedef __int32_t int32_t; +#define _INT32_T_DECLARED +#endif + +#ifndef _INT64_T_DECLARED +typedef __int64_t int64_t; +#define _INT64_T_DECLARED +#endif + +#ifndef _UINT8_T_DECLARED +typedef __uint8_t uint8_t; +#define _UINT8_T_DECLARED +#endif + +#ifndef _UINT16_T_DECLARED +typedef __uint16_t uint16_t; +#define _UINT16_T_DECLARED +#endif + +#ifndef _UINT32_T_DECLARED +typedef __uint32_t uint32_t; +#define _UINT32_T_DECLARED +#endif + +#ifndef _UINT64_T_DECLARED +typedef __uint64_t uint64_t; +#define _UINT64_T_DECLARED +#endif + +#ifndef _INTPTR_T_DECLARED +typedef __intptr_t intptr_t; +#define _INTPTR_T_DECLARED +#endif +#ifndef _UINTPTR_T_DECLARED +typedef __uintptr_t uintptr_t; +#define _UINTPTR_T_DECLARED +#endif + +#endif /* !_SYS__STDINT_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/sys/_types.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/sys/_types.h new file mode 100644 index 0000000..1afeaea --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/sys/_types.h @@ -0,0 +1,106 @@ +/*- + * Copyright (c) 2002 Mike Barcroft + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SYS__TYPES_H_ +#define _SYS__TYPES_H_ + +#include +#include + +/* + * Standard type definitions. + */ +typedef __uint32_t __blksize_t; /* file block size */ +typedef __int64_t __blkcnt_t; /* file block count */ +typedef __int32_t __clockid_t; /* clock_gettime()... */ +typedef __uint32_t __cap_rights_t; /* capability rights */ +typedef __uint32_t __fflags_t; /* file flags */ +typedef __uint32_t __fsblkcnt_t; +typedef __uint32_t __fsfilcnt_t; +typedef __uint32_t __gid_t; +typedef __int32_t __id_t; /* can hold a gid_t, pid_t, or uid_t */ +typedef __uint32_t __ino_t; /* inode number */ +typedef long __key_t; /* IPC key (for Sys V IPC) */ +typedef __int32_t __lwpid_t; /* Thread ID (a.k.a. LWP) */ +typedef __uint16_t __mode_t; /* permissions */ +typedef int __accmode_t; /* access permissions */ +typedef int __nl_item; +typedef __uint16_t __nlink_t; /* link count */ +typedef __int32_t __off_t; /* file offset */ +typedef __int32_t __pid_t; /* process [group] */ +typedef __int32_t __rlim_t; /* resource limit - intentionally */ + /* signed, because of legacy code */ + /* that uses -1 for RLIM_INFINITY */ +typedef __uint8_t __sa_family_t; +typedef __uint32_t __socklen_t; +typedef long __suseconds_t; /* microseconds (signed) */ +typedef struct __timer *__timer_t; /* timer_gettime()... */ +typedef struct __mq *__mqd_t; /* mq_open()... */ +typedef __uint32_t __uid_t; +typedef unsigned int __useconds_t; /* microseconds (unsigned) */ +typedef int __cpuwhich_t; /* which parameter for cpuset. */ +typedef int __cpulevel_t; /* level parameter for cpuset. */ +typedef int __cpusetid_t; /* cpuset identifier. */ + +/* + * Unusual type definitions. + */ +/* + * rune_t is declared to be an ``int'' instead of the more natural + * ``unsigned long'' or ``long''. Two things are happening here. It is not + * unsigned so that EOF (-1) can be naturally assigned to it and used. Also, + * it looks like 10646 will be a 31 bit standard. This means that if your + * ints cannot hold 32 bits, you will be in trouble. The reason an int was + * chosen over a long is that the is*() and to*() routines take ints (says + * ANSI C), but they use __ct_rune_t instead of int. + * + * NOTE: rune_t is not covered by ANSI nor other standards, and should not + * be instantiated outside of lib/libc/locale. Use wchar_t. wchar_t and + * rune_t must be the same type. Also, wint_t must be no narrower than + * wchar_t, and should be able to hold all members of the largest + * character set plus one extra value (WEOF), and must be at least 16 bits. + */ +typedef int __ct_rune_t; /* arg type for ctype funcs */ +typedef __ct_rune_t __rune_t; /* rune_t (see above) */ +typedef __ct_rune_t __wchar_t; /* wchar_t (see above) */ +typedef __ct_rune_t __wint_t; /* wint_t (see above) */ + +typedef __uint32_t __dev_t; /* device number */ + +typedef __uint32_t __fixpt_t; /* fixed point number */ + +/* + * mbstate_t is an opaque object to keep conversion state during multibyte + * stream conversions. + */ +typedef union { + char __mbstate8[128]; + __int64_t _mbstateL; /* for alignment */ +} __mbstate_t; + +#endif /* !_SYS__TYPES_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/sys/cdefs.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/sys/cdefs.h new file mode 100644 index 0000000..16fb151 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/sys/cdefs.h @@ -0,0 +1,686 @@ +/*- + * Copyright (c) 1991, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Berkeley Software Design, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 4. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * @(#)cdefs.h 8.8 (Berkeley) 1/9/95 + * $FreeBSD$ + */ + +#ifndef _SYS_CDEFS_H_ +#define _SYS_CDEFS_H_ + +#if defined(__cplusplus) +#define __BEGIN_DECLS extern "C" { +#define __END_DECLS } +#else +#define __BEGIN_DECLS +#define __END_DECLS +#endif + +/* + * This code has been put in place to help reduce the addition of + * compiler specific defines in FreeBSD code. It helps to aid in + * having a compiler-agnostic source tree. + */ + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) + +#if __GNUC__ >= 3 || defined(__INTEL_COMPILER) +#define __GNUCLIKE_ASM 3 +#define __GNUCLIKE_MATH_BUILTIN_CONSTANTS +#else +#define __GNUCLIKE_ASM 2 +#endif +#define __GNUCLIKE___TYPEOF 1 +#define __GNUCLIKE___OFFSETOF 1 +#define __GNUCLIKE___SECTION 1 + +#ifndef __INTEL_COMPILER +# define __GNUCLIKE_CTOR_SECTION_HANDLING 1 +#endif + +#define __GNUCLIKE_BUILTIN_CONSTANT_P 1 +# if defined(__INTEL_COMPILER) && defined(__cplusplus) \ + && __INTEL_COMPILER < 800 +# undef __GNUCLIKE_BUILTIN_CONSTANT_P +# endif + +#if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3) && !defined(__INTEL_COMPILER) +# define __GNUCLIKE_BUILTIN_VARARGS 1 +# define __GNUCLIKE_BUILTIN_STDARG 1 +# define __GNUCLIKE_BUILTIN_VAALIST 1 +#endif + +#if defined(__GNUC__) +# define __GNUC_VA_LIST_COMPATIBILITY 1 +#endif + +#ifndef __INTEL_COMPILER +# define __GNUCLIKE_BUILTIN_NEXT_ARG 1 +# define __GNUCLIKE_MATH_BUILTIN_RELOPS +#endif + +#define __GNUCLIKE_BUILTIN_MEMCPY 1 + +/* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */ +#define __CC_SUPPORTS_INLINE 1 +#define __CC_SUPPORTS___INLINE 1 +#define __CC_SUPPORTS___INLINE__ 1 + +#define __CC_SUPPORTS___FUNC__ 1 +#define __CC_SUPPORTS_WARNING 1 + +#define __CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */ + +#define __CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1 + +#endif /* __GNUC__ || __INTEL_COMPILER */ + +/* + * Macro to test if we're using a specific version of gcc or later. + */ +#if defined(__GNUC__) && !defined(__INTEL_COMPILER) +#define __GNUC_PREREQ__(ma, mi) \ + (__GNUC__ > (ma) || __GNUC__ == (ma) && __GNUC_MINOR__ >= (mi)) +#else +#define __GNUC_PREREQ__(ma, mi) 0 +#endif + +/* + * The __CONCAT macro is used to concatenate parts of symbol names, e.g. + * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo. + * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI + * mode -- there must be no spaces between its arguments, and for nested + * __CONCAT's, all the __CONCAT's must be at the left. __CONCAT can also + * concatenate double-quoted strings produced by the __STRING macro, but + * this only works with ANSI C. + * + * __XSTRING is like __STRING, but it expands any macros in its argument + * first. It is only available with ANSI C. + */ +#if defined(__STDC__) || defined(__cplusplus) +#define __P(protos) protos /* full-blown ANSI C */ +#define __CONCAT1(x,y) x ## y +#define __CONCAT(x,y) __CONCAT1(x,y) +#define __STRING(x) #x /* stringify without expanding x */ +#define __XSTRING(x) __STRING(x) /* expand x, then stringify */ + +#define __const const /* define reserved names to standard */ +#define __signed signed +#define __volatile volatile +#if defined(__cplusplus) +#define __inline inline /* convert to C++ keyword */ +#else +#if !(defined(__CC_SUPPORTS___INLINE)) +#define __inline /* delete GCC keyword */ +#endif /* ! __CC_SUPPORTS___INLINE */ +#endif /* !__cplusplus */ + +#else /* !(__STDC__ || __cplusplus) */ +#define __P(protos) () /* traditional C preprocessor */ +#define __CONCAT(x,y) x/**/y +#define __STRING(x) "x" + +#if !defined(__CC_SUPPORTS___INLINE) +#define __const /* delete pseudo-ANSI C keywords */ +#define __inline +#define __signed +#define __volatile +/* + * In non-ANSI C environments, new programs will want ANSI-only C keywords + * deleted from the program and old programs will want them left alone. + * When using a compiler other than gcc, programs using the ANSI C keywords + * const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS. + * When using "gcc -traditional", we assume that this is the intent; if + * __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone. + */ +#ifndef NO_ANSI_KEYWORDS +#define const /* delete ANSI C keywords */ +#define inline +#define signed +#define volatile +#endif /* !NO_ANSI_KEYWORDS */ +#endif /* !__CC_SUPPORTS___INLINE */ +#endif /* !(__STDC__ || __cplusplus) */ + +/* + * Compiler-dependent macros to help declare dead (non-returning) and + * pure (no side effects) functions, and unused variables. They are + * null except for versions of gcc that are known to support the features + * properly (old versions of gcc-2 supported the dead and pure features + * in a different (wrong) way). If we do not provide an implementation + * for a given compiler, let the compile fail if it is told to use + * a feature that we cannot live without. + */ +#ifdef lint +#define __dead2 +#define __pure2 +#define __unused +#define __packed +#define __aligned(x) +#define __section(x) +#else +#if !__GNUC_PREREQ__(2, 5) && !defined(__INTEL_COMPILER) +#define __dead2 +#define __pure2 +#define __unused +#endif +#if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 && !defined(__INTEL_COMPILER) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused +/* XXX Find out what to do for __packed, __aligned and __section */ +#endif +#if __GNUC_PREREQ__(2, 7) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) +#endif +#if defined(__INTEL_COMPILER) +#define __dead2 __attribute__((__noreturn__)) +#define __pure2 __attribute__((__const__)) +#define __unused __attribute__((__unused__)) +#define __used __attribute__((__used__)) +#define __packed __attribute__((__packed__)) +#define __aligned(x) __attribute__((__aligned__(x))) +#define __section(x) __attribute__((__section__(x))) +#endif +#endif + +#if !__GNUC_PREREQ__(2, 95) +#define __alignof(x) __offsetof(struct { char __a; x __b; }, __b) +#endif + +/* + * Keywords added in C11. + */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define _Alignas(e) alignas(e) +#define _Alignof(e) alignof(e) +#define _Noreturn [[noreturn]] +#define _Static_assert(e, s) static_assert(e, s) +/* FIXME: change this to thread_local when clang in base supports it */ +#define _Thread_local __thread +#elif defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +/* Do nothing. They are language keywords. */ +#else +/* Not supported. Implement them using our versions. */ +#define _Alignas(x) __aligned(x) +#define _Alignof(x) __alignof(x) +#define _Noreturn __dead2 +#define _Thread_local __thread +#ifdef __COUNTER__ +#define _Static_assert(x, y) __Static_assert(x, __COUNTER__) +#define __Static_assert(x, y) ___Static_assert(x, y) +#define ___Static_assert(x, y) typedef char __assert_ ## y[(x) ? 1 : -1] +#else +#define _Static_assert(x, y) struct __hack +#endif +#endif + +/* + * Emulation of C11 _Generic(). Unlike the previously defined C11 + * keywords, it is not possible to implement this using exactly the same + * syntax. Therefore implement something similar under the name + * __generic(). Unlike _Generic(), this macro can only distinguish + * between a single type, so it requires nested invocations to + * distinguish multiple cases. + */ + +#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L +#define __generic(expr, t, yes, no) \ + _Generic(expr, t: yes, default: no) +#elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus) +#define __generic(expr, t, yes, no) \ + __builtin_choose_expr( \ + __builtin_types_compatible_p(__typeof(expr), t), yes, no) +#endif + +#if __GNUC_PREREQ__(2, 96) +#define __malloc_like __attribute__((__malloc__)) +#define __pure __attribute__((__pure__)) +#else +#define __malloc_like +#define __pure +#endif + +#if __GNUC_PREREQ__(3, 1) || (defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 800) +#define __always_inline __attribute__((__always_inline__)) +#else +#define __always_inline +#endif + +#if __GNUC_PREREQ__(3, 1) +#define __noinline __attribute__ ((__noinline__)) +#else +#define __noinline +#endif + +#if __GNUC_PREREQ__(3, 3) +#define __nonnull(x) __attribute__((__nonnull__(x))) +#else +#define __nonnull(x) +#endif + +#if __GNUC_PREREQ__(3, 4) +#define __fastcall __attribute__((__fastcall__)) +#else +#define __fastcall +#endif + +#if __GNUC_PREREQ__(4, 1) +#define __returns_twice __attribute__((__returns_twice__)) +#else +#define __returns_twice +#endif + +/* XXX: should use `#if __STDC_VERSION__ < 199901'. */ +#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER) +#define __func__ NULL +#endif + +#if (defined(__INTEL_COMPILER) || (defined(__GNUC__) && __GNUC__ >= 2)) && !defined(__STRICT_ANSI__) || __STDC_VERSION__ >= 199901 +#define __LONG_LONG_SUPPORTED +#endif + +/* C++11 exposes a load of C99 stuff */ +#if defined(__cplusplus) && __cplusplus >= 201103L +#define __LONG_LONG_SUPPORTED +#ifndef __STDC_LIMIT_MACROS +#define __STDC_LIMIT_MACROS +#endif +#ifndef __STDC_CONSTANT_MACROS +#define __STDC_CONSTANT_MACROS +#endif +#endif + +/* + * GCC 2.95 provides `__restrict' as an extension to C90 to support the + * C99-specific `restrict' type qualifier. We happen to use `__restrict' as + * a way to define the `restrict' type qualifier without disturbing older + * software that is unaware of C99 keywords. + */ +#if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95) +#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901 || defined(lint) +#define __restrict +#else +#define __restrict restrict +#endif +#endif + +/* + * GNU C version 2.96 adds explicit branch prediction so that + * the CPU back-end can hint the processor and also so that + * code blocks can be reordered such that the predicted path + * sees a more linear flow, thus improving cache behavior, etc. + * + * The following two macros provide us with a way to utilize this + * compiler feature. Use __predict_true() if you expect the expression + * to evaluate to true, and __predict_false() if you expect the + * expression to evaluate to false. + * + * A few notes about usage: + * + * * Generally, __predict_false() error condition checks (unless + * you have some _strong_ reason to do otherwise, in which case + * document it), and/or __predict_true() `no-error' condition + * checks, assuming you want to optimize for the no-error case. + * + * * Other than that, if you don't know the likelihood of a test + * succeeding from empirical or other `hard' evidence, don't + * make predictions. + * + * * These are meant to be used in places that are run `a lot'. + * It is wasteful to make predictions in code that is run + * seldomly (e.g. at subsystem initialization time) as the + * basic block reordering that this affects can often generate + * larger code. + */ +#if __GNUC_PREREQ__(2, 96) +#define __predict_true(exp) __builtin_expect((exp), 1) +#define __predict_false(exp) __builtin_expect((exp), 0) +#else +#define __predict_true(exp) (exp) +#define __predict_false(exp) (exp) +#endif + +#if __GNUC_PREREQ__(4, 2) +#define __hidden __attribute__((__visibility__("hidden"))) +#define __exported __attribute__((__visibility__("default"))) +#else +#define __hidden +#define __exported +#endif + +/* + * We define this here since , , and + * require it. + */ +#if __GNUC_PREREQ__(4, 1) +#define __offsetof(type, field) __builtin_offsetof(type, field) +#else +#ifndef __cplusplus +#define __offsetof(type, field) \ + ((__size_t)(__uintptr_t)((const volatile void *)&((type *)0)->field)) +#else +#define __offsetof(type, field) \ + (__offsetof__ (reinterpret_cast <__size_t> \ + (&reinterpret_cast \ + (static_cast (0)->field)))) +#endif +#endif +#define __rangeof(type, start, end) \ + (__offsetof(type, end) - __offsetof(type, start)) + +/* + * Given the pointer x to the member m of the struct s, return + * a pointer to the containing structure. When using GCC, we first + * assign pointer x to a local variable, to check that its type is + * compatible with member m. + */ +#if __GNUC_PREREQ__(3, 1) +#define __containerof(x, s, m) ({ \ + const volatile __typeof(((s *)0)->m) *__x = (x); \ + __DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\ +}) +#else +#define __containerof(x, s, m) \ + __DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m)) +#endif + +/* + * Compiler-dependent macros to declare that functions take printf-like + * or scanf-like arguments. They are null except for versions of gcc + * that are known to support the features properly (old versions of gcc-2 + * didn't permit keeping the keywords out of the application namespace). + */ +#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER) +#define __printflike(fmtarg, firstvararg) +#define __scanflike(fmtarg, firstvararg) +#define __format_arg(fmtarg) +#define __strfmonlike(fmtarg, firstvararg) +#define __strftimelike(fmtarg, firstvararg) +#else +#define __printflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf__, fmtarg, firstvararg))) +#define __scanflike(fmtarg, firstvararg) \ + __attribute__((__format__ (__scanf__, fmtarg, firstvararg))) +#define __format_arg(fmtarg) __attribute__((__format_arg__ (fmtarg))) +#define __strfmonlike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strfmon__, fmtarg, firstvararg))) +#define __strftimelike(fmtarg, firstvararg) \ + __attribute__((__format__ (__strftime__, fmtarg, firstvararg))) +#endif + +/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */ +#if __FreeBSD_cc_version >= 300001 && defined(__GNUC__) && !defined(__INTEL_COMPILER) +#define __printf0like(fmtarg, firstvararg) \ + __attribute__((__format__ (__printf0__, fmtarg, firstvararg))) +#else +#define __printf0like(fmtarg, firstvararg) +#endif + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) +#ifndef __INTEL_COMPILER +#define __strong_reference(sym,aliassym) \ + extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym))) +#endif +#ifdef __STDC__ +#define __weak_reference(sym,alias) \ + __asm__(".weak " #alias); \ + __asm__(".equ " #alias ", " #sym) +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning." #sym); \ + __asm__(".asciz \"" msg "\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@" #verid) +#define __sym_default(sym,impl,verid) \ + __asm__(".symver " #impl ", " #sym "@@" #verid) +#else +#define __weak_reference(sym,alias) \ + __asm__(".weak alias"); \ + __asm__(".equ alias, sym") +#define __warn_references(sym,msg) \ + __asm__(".section .gnu.warning.sym"); \ + __asm__(".asciz \"msg\""); \ + __asm__(".previous") +#define __sym_compat(sym,impl,verid) \ + __asm__(".symver impl, sym@verid") +#define __sym_default(impl,sym,verid) \ + __asm__(".symver impl, sym@@verid") +#endif /* __STDC__ */ +#endif /* __GNUC__ || __INTEL_COMPILER */ + +#define __GLOBL1(sym) __asm__(".globl " #sym) +#define __GLOBL(sym) __GLOBL1(sym) + +#if defined(__GNUC__) || defined(__INTEL_COMPILER) +#define __IDSTRING(name,string) __asm__(".ident\t\"" string "\"") +#else +/* + * The following definition might not work well if used in header files, + * but it should be better than nothing. If you want a "do nothing" + * version, then it should generate some harmless declaration, such as: + * #define __IDSTRING(name,string) struct __hack + */ +#define __IDSTRING(name,string) static const char name[] __unused = string +#endif + +/* + * Embed the rcs id of a source file in the resulting library. Note that in + * more recent ELF binutils, we use .ident allowing the ID to be stripped. + * Usage: + * __FBSDID("$FreeBSD$"); + */ +#ifndef __FBSDID +#if !defined(lint) && !defined(STRIP_FBSDID) +#define __FBSDID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __FBSDID(s) struct __hack +#endif +#endif + +#ifndef __RCSID +#ifndef NO__RCSID +#define __RCSID(s) __IDSTRING(__CONCAT(__rcsid_,__LINE__),s) +#else +#define __RCSID(s) struct __hack +#endif +#endif + +#ifndef __RCSID_SOURCE +#ifndef NO__RCSID_SOURCE +#define __RCSID_SOURCE(s) __IDSTRING(__CONCAT(__rcsid_source_,__LINE__),s) +#else +#define __RCSID_SOURCE(s) struct __hack +#endif +#endif + +#ifndef __SCCSID +#ifndef NO__SCCSID +#define __SCCSID(s) __IDSTRING(__CONCAT(__sccsid_,__LINE__),s) +#else +#define __SCCSID(s) struct __hack +#endif +#endif + +#ifndef __COPYRIGHT +#ifndef NO__COPYRIGHT +#define __COPYRIGHT(s) __IDSTRING(__CONCAT(__copyright_,__LINE__),s) +#else +#define __COPYRIGHT(s) struct __hack +#endif +#endif + +#ifndef __DECONST +#define __DECONST(type, var) ((type)(__uintptr_t)(const void *)(var)) +#endif + +#ifndef __DEVOLATILE +#define __DEVOLATILE(type, var) ((type)(__uintptr_t)(volatile void *)(var)) +#endif + +#ifndef __DEQUALIFY +#define __DEQUALIFY(type, var) ((type)(__uintptr_t)(const volatile void *)(var)) +#endif + +/*- + * The following definitions are an extension of the behavior originally + * implemented in , but with a different level of granularity. + * POSIX.1 requires that the macros we test be defined before any standard + * header file is included. + * + * Here's a quick run-down of the versions: + * defined(_POSIX_SOURCE) 1003.1-1988 + * _POSIX_C_SOURCE == 1 1003.1-1990 + * _POSIX_C_SOURCE == 2 1003.2-1992 C Language Binding Option + * _POSIX_C_SOURCE == 199309 1003.1b-1993 + * _POSIX_C_SOURCE == 199506 1003.1c-1995, 1003.1i-1995, + * and the omnibus ISO/IEC 9945-1: 1996 + * _POSIX_C_SOURCE == 200112 1003.1-2001 + * _POSIX_C_SOURCE == 200809 1003.1-2008 + * + * In addition, the X/Open Portability Guide, which is now the Single UNIX + * Specification, defines a feature-test macro which indicates the version of + * that specification, and which subsumes _POSIX_C_SOURCE. + * + * Our macros begin with two underscores to avoid namespace screwage. + */ + +/* Deal with IEEE Std. 1003.1-1990, in which _POSIX_C_SOURCE == 1. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 1 +#undef _POSIX_C_SOURCE /* Probably illegal, but beyond caring now. */ +#define _POSIX_C_SOURCE 199009 +#endif + +/* Deal with IEEE Std. 1003.2-1992, in which _POSIX_C_SOURCE == 2. */ +#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE == 2 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199209 +#endif + +/* Deal with various X/Open Portability Guides and Single UNIX Spec. */ +#ifdef _XOPEN_SOURCE +#if _XOPEN_SOURCE - 0 >= 700 +#define __XSI_VISIBLE 700 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200809 +#elif _XOPEN_SOURCE - 0 >= 600 +#define __XSI_VISIBLE 600 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 200112 +#elif _XOPEN_SOURCE - 0 >= 500 +#define __XSI_VISIBLE 500 +#undef _POSIX_C_SOURCE +#define _POSIX_C_SOURCE 199506 +#endif +#endif + +/* + * Deal with all versions of POSIX. The ordering relative to the tests above is + * important. + */ +#if defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE) +#define _POSIX_C_SOURCE 198808 +#endif +#ifdef _POSIX_C_SOURCE +#if _POSIX_C_SOURCE >= 200809 +#define __POSIX_VISIBLE 200809 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 200112 +#define __POSIX_VISIBLE 200112 +#define __ISO_C_VISIBLE 1999 +#elif _POSIX_C_SOURCE >= 199506 +#define __POSIX_VISIBLE 199506 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199309 +#define __POSIX_VISIBLE 199309 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199209 +#define __POSIX_VISIBLE 199209 +#define __ISO_C_VISIBLE 1990 +#elif _POSIX_C_SOURCE >= 199009 +#define __POSIX_VISIBLE 199009 +#define __ISO_C_VISIBLE 1990 +#else +#define __POSIX_VISIBLE 198808 +#define __ISO_C_VISIBLE 0 +#endif /* _POSIX_C_SOURCE */ +#else +/*- + * Deal with _ANSI_SOURCE: + * If it is defined, and no other compilation environment is explicitly + * requested, then define our internal feature-test macros to zero. This + * makes no difference to the preprocessor (undefined symbols in preprocessing + * expressions are defined to have value zero), but makes it more convenient for + * a test program to print out the values. + * + * If a program mistakenly defines _ANSI_SOURCE and some other macro such as + * _POSIX_C_SOURCE, we will assume that it wants the broader compilation + * environment (and in fact we will never get here). + */ +#if defined(_ANSI_SOURCE) /* Hide almost everything. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1990 +#elif defined(_C99_SOURCE) /* Localism to specify strict C99 env. */ +#define __POSIX_VISIBLE 0 +#define __XSI_VISIBLE 0 +#define __BSD_VISIBLE 0 +#define __ISO_C_VISIBLE 1999 +#else /* Default environment: show everything. */ +#define __POSIX_VISIBLE 200809 +#define __XSI_VISIBLE 700 +#define __BSD_VISIBLE 1 +#define __ISO_C_VISIBLE 1999 +#endif +#endif + +#ifndef __has_feature +#define __has_feature(x) 0 +#endif +#ifndef __has_include +#define __has_include(x) 0 +#endif +#ifndef __has_builtin +#define __has_builtin(x) 0 +#endif + +#if defined(__mips) || defined(__powerpc64__) || defined(__arm__) +#define __NO_TLS 1 +#endif + +#endif /* !_SYS_CDEFS_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/include/timer.h b/IPL/SDK/v4h/src/Dummy_RTOS/include/timer.h new file mode 100644 index 0000000..9f6e291 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/include/timer.h @@ -0,0 +1,48 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : timer header + ******************************************************************************/ +/****************************************************************************** + * @file timer.h + * - Version : 0.01 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 19.09.2023 0.01 First Release + *****************************************************************************/ +#ifndef TIMER_H_ +#define TIMER_H_ + +#include + +/* Prototype */ +void generic_timer_init(void); +void micro_wait(uint64_t micro_sec); + +#endif /* TIMER_H_ */ diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos.S b/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos.S new file mode 100644 index 0000000..8e7c2d5 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos.S @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2015-2024, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#define DRAM_BASE (0x40000000) +#define SYSRAM_BASE (0xE6300000) +#define DTCM_BASE (0xE2020000) + +#define STACK_BASE_ABT (DTCM_BASE | 0x7080) +#define STACK_BASE_UND (DTCM_BASE | 0x7100) +#define STACK_BASE_FIQ (DTCM_BASE | 0x7180) +#define STACK_BASE_IRQ (DTCM_BASE | 0x7200) +#define STACK_BASE_SVC (DTCM_BASE | 0x8000) + + + .global Vector + .global Start + .local rtos_stacks + +/***************************************************************************** + * Vector table + *****************************************************************************/ + .align 5 + +Vector: + b Start /* Reset */ + b Undef /* Undefined Instruction */ + b SWI /* Supervisor Call */ + b PAbort /* Prefetch Abort */ + b DAbort /* Data Abort */ + nop /* Not used */ + b IRQ /* IRQ interrupt */ + b FIQ /* FIQ interrupt */ + + +/***************************************************************************** + * Reset Hander + *****************************************************************************/ +Start: + /* initialize registers*/ + mov r0, #0 + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 + mov r8, #0 + mov r9, #0 + mov r10, #0 + mov r11, #0 + mov r12, #0 + mov lr, #0 + +#if ((CR52_CORE == 0) || (CR52_CORE == 2)) +/* MPU setting is required only for RTOS#0 and RTOS#2. */ + + /* CR52_CONFIGURE_MPU */ +;# MPU setting was given from BootROM team +;# Memory Attribute setting + LDR r0, =0xFF00 ;# Attr1[15:8]=FF:Write-Back, Attr0[7:0]=00:Device-nGnRnE memory + MCR p15, 0, r0, c10, c2, 0 ;# MAIR0 + MCR p15, 4, r0, c10, c2, 0 ;# HMAIR0 + +;# region 0: 0x00000000--0x3FFFFFFF AttrIndx=1(Write-Back) + LDR r0, =0x00000002 ;# SH=b'00/AP=b'01/XN=b'0 + MCR p15, 0, r0, c6, c8, 0 ;# PRBAR0 + MCR p15, 4, r0, c6, c8, 0 ;# HPRBAR0 + LDR r0, =0x3FFFFFC3 ;# AttrIndx=1(Write-Back) + MCR p15, 0, r0, c6, c8, 1 ;# PRLAR0 + MCR p15, 4, r0, c6, c8, 1 ;# HPRLAR0 + +;# region 1: 0x40000000--0xBFFFFFFF AttrIndx=1(Write-Back) + LDR r0, =0x40000002 ;# SH=b'00/AP=b'01/XN=b'0 + MCR p15, 0, r0, c6, c8, 4 ;# PRBAR1 + MCR p15, 4, r0, c6, c8, 4 ;# HPRBAR1 + LDR r0, =0xBFFFFFC3 ;# AttrIndx=1(Write-Back) + MCR p15, 0, r0, c6, c8, 5 ;# PRLAR1 + MCR p15, 4, r0, c6, c8, 5 ;# HPRLAR1 + +;# region 2: 0xC0000000--0xDFFFFFFF AttrIndx=0(Device) + LDR r0, =0xC0000003 ;# SH=b'00/AP=b'01/XN=b'1 + MCR p15, 0, r0, c6, c9, 0 ;# PRBAR2 + MCR p15, 4, r0, c6, c9, 0 ;# HPRBAR2 + LDR r0, =0xDFFFFFC1 ;# AttrIndx=0(Device) + MCR p15, 0, r0, c6, c9, 1 ;# PRLAR2 + MCR p15, 4, r0, c6, c9, 1 ;# HPRLAR2 + +;# region 3: 0xE0000000--0xE1FFFFFF AttrIndx=0(Device) +;# LDR r0, =0xE0000003 ;# SH=b'00/AP=b'01/XN=b'1 + LDR r0, =0xE0000002 ;# SH=b'00/AP=b'01/XN=b'0 ;# Enable RT-VRAM1 for V4H + MCR p15, 0, r0, c6, c9, 4 ;# PRBAR3 + MCR p15, 4, r0, c6, c9, 4 ;# HPRBAR3 + LDR r0, =0xE1FFFFC1 ;# AttrIndx=0(Device) + MCR p15, 0, r0, c6, c9, 5 ;# PRLAR3 + MCR p15, 4, r0, c6, c9, 5 ;# HPRLAR3 + +;# region 4: 0xE2000000--0xE42FFFFF AttrIndx=1(Write-Back) + LDR r0, =0xE2000002 ;# SH=b'00/AP=b'01/XN=b'0 + MCR p15, 0, r0, c6, c10, 0 ;# PRBAR4 + MCR p15, 4, r0, c6, c10, 0 ;# HPRBAR4 + LDR r0, =0xE42FFFC3 ;# AttrIndx=(Write-Back) + MCR p15, 0, r0, c6, c10, 1 ;# PRLAR4 + MCR p15, 4, r0, c6, c10, 1 ;# HPRLAR4 + +;# region 5: 0xE4300000--0xE62FFFFF AttrIndx=0(Device) + LDR r0, =0xE4300003 ;# SH=b'00/AP=b'01/XN=b'1 + MCR p15, 0, r0, c6, c10, 4 ;# PRBAR5 + MCR p15, 4, r0, c6, c10, 4 ;# HPRBAR5 + LDR r0, =0xE62FFFC1 ;# AttrIndx=0(Device) + MCR p15, 0, r0, c6, c10, 5 ;# PRLAR5 + MCR p15, 4, r0, c6, c10, 5 ;# HPRLAR5 + +;# region 6: 0xE6300000--0xE63FFFFF AttrIndx=1(Write-Back) + LDR r0, =0xE6300002 ;# SH=b'00/AP=b'01/XN=b'0 + MCR p15, 0, r0, c6, c11, 0 ;# PRBAR6 + MCR p15, 4, r0, c6, c11, 0 ;# HPRBAR6 + LDR r0, =0xE63FFFC3 ;# AttrIndx=(Write-Back) + MCR p15, 0, r0, c6, c11, 1 ;# PRLAR6 + MCR p15, 4, r0, c6, c11, 1 ;# HPRLAR6 + +;# region 7: 0xE6400000--0xEB0FFFFF AttrIndx=0(Device) + LDR r0, =0xE6400003 ;# SH=b'00/AP=b'01/XN=b'1 + MCR p15, 0, r0, c6, c11, 4 ;# PRBAR7 + MCR p15, 4, r0, c6, c11, 4 ;# HPRBAR7 + LDR r0, =0xEB0FFFC1 ;# AttrIndx=0(Device) + MCR p15, 0, r0, c6, c11, 5 ;# PRLAR7 + MCR p15, 4, r0, c6, c11, 5 ;# HPRLAR7 + +;# region 8: 0xEB100000--0xEB127FFF AttrIndx=1(Write-Back) + LDR r0, =0xEB100006 ;# SH=b'00/AP=b'10/XN=b'0 + MCR p15, 0, r0, c6, c12, 0 ;# PRBAR8 + MCR p15, 4, r0, c6, c12, 0 ;# HPRBAR8 + LDR r0, =0xEB127FC3 ;# AttrIndx=(Write-Back) + MCR p15, 0, r0, c6, c12, 1 ;# PRLAR8 + MCR p15, 4, r0, c6, c12, 1 ;# HPRLAR8 + +;# region 9: 0xEB128000--0xEB1FFFFF AttrIndx=0(Device) + LDR r0, =0xEB128003 ;# SH=b'00/AP=b'01/XN=b'1 + MCR p15, 0, r0, c6, c12, 4 ;# PRBAR9 + MCR p15, 4, r0, c6, c12, 4 ;# HPRBAR9 + LDR r0, =0xEB1FFFC1 ;# AttrIndx=0(Device) + MCR p15, 0, r0, c6, c12, 5 ;# PRLAR9 + MCR p15, 4, r0, c6, c12, 5 ;# HPRLAR9 + +;# region 10: 0xEB200000--0xEB3FFFFF AttrIndx=1(Write-Back) + LDR r0, =0xEB200002 ;# SH=b'00/AP=b'01/XN=b'0 + MCR p15, 0, r0, c6, c13, 0 ;# PRBAR10 + MCR p15, 4, r0, c6, c13, 0 ;# HPRBAR10 + LDR r0, =0xEB3FFFC3 ;# AttrIndx=(Write-Back) + MCR p15, 0, r0, c6, c13, 1 ;# PRLAR10 + MCR p15, 4, r0, c6, c13, 1 ;# HPRLAR10 + +;# region 11: 0xEB400000--0xFFFFFFFF AttrIndx=0(Device) + LDR r0, =0xEB400003 ;# SH=b'00/AP=b'01/XN=b'1 + MCR p15, 0, r0, c6, c13, 4 ;# PRBAR11 + MCR p15, 4, r0, c6, c13, 4 ;# HPRBAR11 + LDR r0, =0xFFFFFFC1 ;# AttrIndx=0(Device) + MCR p15, 0, r0, c6, c13, 5 ;# PRLAR11 + MCR p15, 4, r0, c6, c13, 5 ;# HPRLAR11 + +;#CR52_SET_MPU_ON + MRC p15, 4, r0, c1, c0, 0 ;# HSCTLR + ORR r0, r0, #0x00000001 ;# EL2-controlled MPU enable + DSB + MCR p15, 4, r0, c1, c0, 0 + ISB + + MRC p15, 0, r0, c1, c0, 0 ;# SCTLR + ORR r0, r0, #0x00000001 ;# EL1-controlled MPU enable + DSB + MCR p15, 0, r0, c1, c0, 0 + ISB + +#endif /* ((CR52_CORE == 0) || (CR52_CORE == 2)) */ + + LDR PC, =STACK_INIT + +STACK_INIT: + /* stack initialize */ + ldr r0, =__STACKS_END__ + +;# msr CPSR_c, #(0x17 | 0x80 | 0x40) /* ABT */ +;# mov sp, r0 /* STACK_BASE_ABT */ + +;# msr CPSR_c, #(0x1B | 0x80 | 0x40) /* UND */ +;# sub r0, r0, #0x80 /* STACK_BASE_UND */ +;# mov sp, r0 + +;# msr CPSR_c, #(0x11 | 0x80 | 0x40) /* FIQ */ +;# sub r0, r0, #0x80 /* STACK_BASE_FIQ */ +;# mov sp, r0 + +;# msr CPSR_c, #(0x12 | 0x80 | 0x40) /* IRQ */ +;# sub r0, r0, #0x80 /* STACK_BASE_IRQ */ +;# mov sp, r0 + +;# msr CPSR_c, #(0x13 | 0x80 | 0x40) /* SVC */ +;# sub r0, r0, #0x80 /* STACK_BASE_SVC */ + mov sp, r0 + + + /* Loader Main */ + BL rtos_main + +NO_BOOT: + nop +1: +;# wfe + b 1b + + +/***************************************************************************** + * Exception Handers + *****************************************************************************/ + + /* Undefined Instruction */ +Undef: + nop +1: + wfe + b 1b + + /* Supervisor Call */ +SWI: + nop +1: + wfe + b 1b + + /* Prefetch Abort */ +PAbort: + nop +1: + wfe + b 1b + + /* Data Abort */ +DAbort: + nop +1: + wfe + b 1b + + /* IRQ interrupt */ +IRQ: + nop +1: + wfe + b 1b + + /* FIQ interrupt */ +FIQ: + nop +1: + wfe + b 1b + + +/***************************************************************************** + * Define stack + *****************************************************************************/ + .section tzfw_normal_stacks, "aw" + .align 6 + +rtos_stacks: + .space 4 * 1024 + + .end diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos.ld.S b/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos.ld.S new file mode 100644 index 0000000..102df7c --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos.ld.S @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2015-2017, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(Vector) + +MEMORY { + RAM (rwxa): ORIGIN = 0xE2100000, LENGTH = 0x00400000 +} + + +SECTIONS +{ + . = 0xE2100000; + ASSERT(. == ALIGN(4096), + "CR7 dummy rtos address is not aligned on a page boundary.") + + ro . : { + __RO_START__ = .; + *rtos.o(.text*) + *rtos_main.o(.text*) + . = NEXT(32768); + *(.text*) + *(.rodata*) + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as + * read-only, executable. No RW data from the next section must + * creep in. Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + . = NEXT(16384); + __RO_END__ = .; + } >RAM + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + + stacks (NOLOAD) : ALIGN(16) { + __STACKS_START__ = .; + KEEP(*(tzfw_normal_stacks)) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } >RAM + + __BSS_SIZE__ = SIZEOF(.bss); + + ASSERT(. <= 0xE24FE800, "CR7 dummy rtos has exceeded its limit.") +} diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos_core1.ld.S b/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos_core1.ld.S new file mode 100644 index 0000000..33dc96b --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos_core1.ld.S @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2015-2024, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(Vector) + +MEMORY { + RAM (rwxa): ORIGIN = 0xE3100000, LENGTH = 0x00200000 /* 2MiB */ +} + + +SECTIONS +{ + . = 0xE3100000; + ASSERT(. == ALIGN(4096), + "CR7 dummy rtos address is not aligned on a page boundary.") + + ro . : { + __RO_START__ = .; + *rtos.o(.text*) + *rtos_main.o(.text*) + . = NEXT(32768); + *(.text*) + *(.rodata*) + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as + * read-only, executable. No RW data from the next section must + * creep in. Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + . = NEXT(16384); + __RO_END__ = .; + } >RAM + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + + stacks (NOLOAD) : ALIGN(16) { + __STACKS_START__ = .; + KEEP(*(tzfw_normal_stacks)) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } >RAM + + __BSS_SIZE__ = SIZEOF(.bss); + + ASSERT(. <= 0xE32FF800, "CR7 dummy rtos has exceeded its limit.") +} diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos_core2.ld.S b/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos_core2.ld.S new file mode 100644 index 0000000..b12ef7d --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos_core2.ld.S @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2015-2024, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +OUTPUT_FORMAT("elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(Vector) + +MEMORY { + RAM (rwxa): ORIGIN = 0xE2000000, LENGTH = 0x00010000 /* 64KiB */ +} + + +SECTIONS +{ + . = 0xE2000000; + ASSERT(. == ALIGN(4096), + "CR7 dummy rtos address is not aligned on a page boundary.") + + ro . : { + __RO_START__ = .; + *rtos.o(.text*) + *rtos_main.o(.text*) + . = NEXT(32768); + *(.text*) + *(.rodata*) + __RO_END_UNALIGNED__ = .; + /* + * Memory page(s) mapped to this section will be marked as + * read-only, executable. No RW data from the next section must + * creep in. Ensure the rest of the current memory page is unused. + */ + . = NEXT(4096); + . = NEXT(16384); + __RO_END__ = .; + } >RAM + + .data . : { + __DATA_START__ = .; + *(.data*) + __DATA_END__ = .; + } >RAM + + stacks (NOLOAD) : ALIGN(16) { + __STACKS_START__ = .; + KEEP(*(tzfw_normal_stacks)) + __STACKS_END__ = .; + } >RAM + + /* + * The .bss section gets initialised to 0 at runtime. + * Its base address must be 16-byte aligned. + */ + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } >RAM + + __BSS_SIZE__ = SIZEOF(.bss); + + ASSERT(. <= 0xE200F800, "CR7 dummy rtos has exceeded its limit.") +} diff --git a/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos_main.c b/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos_main.c new file mode 100644 index 0000000..c419a22 --- /dev/null +++ b/IPL/SDK/v4h/src/Dummy_RTOS/rtos/rtos_main.c @@ -0,0 +1,103 @@ +/* + * Copyright (c) 2015-2024, Renesas Electronics Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * - Neither the name of Renesas nor the names of its contributors may be + * used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + + +#include +#include "scif.h" +#include "timer.h" + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Unions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Structs */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Globals */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Macros */ +/************************************************************************************************/ +#define MIDR_PN_SHIFT (0x4U) +#define MIDR_PN_MASK (0X0FFFU) +#define MIDR_CA57 (0x0D07U << MIDR_PN_SHIFT) +#define MIDR_CA53 (0x0D03U << MIDR_PN_SHIFT) +#define MIDR_CR7 (0x0C17U << MIDR_PN_SHIFT) +/* Input Dummy Program waiting time (us) */ +#if (CR52_CORE == 0) /* RTOS#0 */ +#define WAIT_TIME_US (2000000U) /* 3.0[s] */ +#elif (CR52_CORE == 1) /* RTOS#1 */ +#define WAIT_TIME_US (1U) /* 1.0[us] */ +#elif (CR52_CORE == 2) /* RTOS#2 */ +#define WAIT_TIME_US (1000000U) /* 2.0[s] */ +#endif + +/************************************************************************************************/ +/* Prototypes */ +/************************************************************************************************/ +uint32_t rtos_main(void); + + +uint32_t rtos_main(void) +{ + scif_init(); + + generic_timer_init(); + + micro_wait(WAIT_TIME_US); + +#if (CR52_CORE == 0) /* RTOS#0 */ + PutStr(" ",1); + PutStr("Dummy RTOS#0 Program",1); + PutStr("Dummy RTOS#0 Program boot end",1); +#elif (CR52_CORE == 1) /* RTOS#1 */ + PutStr(" ",1); + PutStr("Dummy RTOS#1 Program",1); + PutStr("Dummy RTOS#1 Program boot end",1); +#elif (CR52_CORE == 2) /* RTOS#2 */ + PutStr(" ",1); + PutStr("Dummy RTOS#2 Program",1); + PutStr("Dummy RTOS#2 Program boot end",1); +#endif + + return 0U; +} diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/Makefile b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/Makefile new file mode 100644 index 0000000..e7df9fb --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/Makefile @@ -0,0 +1,646 @@ +#/******************************************************************************* +# * DISCLAIMER +# * This software is supplied by Renesas Electronics Corporation and is only +# * intended for use with Renesas products. No other uses are authorized. This +# * software is owned by Renesas Electronics Corporation and is protected under +# * all applicable laws, including copyright laws. +# * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +# * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +# * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +# * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +# * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +# * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +# * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +# * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +# * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +# * Renesas reserves the right, without notice, to make changes to this software +# * and to discontinue the availability of this software. By using this software, +# * you agree to the additional terms and conditions found by accessing the +# * following link: +# * http://www.renesas.com/disclaimer +# * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved. +# *******************************************************************************/ +# +# ******************************************************************************* +# * DESCRIPTION : makefile for Loader +# ****************************************************************************** + +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +INCLUDE_DIR = -Iinclude \ + -Iip/ddr + +OUTDIR := build + +# LSI setting common define +RCAR_S4 := 0 +RCAR_V4H := 1 +RCAR_V4M := 2 +$(eval $(call add_define,RCAR_S4)) +$(eval $(call add_define,RCAR_V4H)) +$(eval $(call add_define,RCAR_V4M)) + +#/* Select LSI("S4" or "V4H" or "V4M" )******************************** +ifeq ("$(LSI)", "") +LSI = S4 +endif + +ifeq (${LSI},S4) + RCAR_LSI:=${RCAR_S4} + DIR_NAME_SA9 = s4 + OBJ_FILE += loader/loader_main_s4.o \ + cnf_tbl/cnf_tbl_s4.o \ + ip/qos/qos.o \ + ip/rtvram/rtvram.o \ + ip/ddr/s4/lpddr4x/ecc_enable_s4.o + INCLUDE_DIR += -Imcu + include ip/ddr/ddr.mk +else ifeq (${LSI},V4H) + RCAR_LSI:=${RCAR_V4H} + DIR_NAME_SA9 = v4h + OBJ_FILE += loader/loader_main_v4h.o \ + ip/fcpr/fcpr.o \ + cnf_tbl/cnf_tbl_v4h.o \ + ip/ddr/v4h/lpddr5/ecc_enable_v4h.o \ + ip/ddr/v4h/lpddr5/ecm_enable_v4h.o +else ifeq (${LSI},V4M) + RCAR_LSI:=${RCAR_V4M} + DIR_NAME_SA9 = v4m + OBJ_FILE += loader/loader_main_v4m.o \ + ip/fcpr/fcpr.o \ + cnf_tbl/cnf_tbl_v4m.o \ + ip/sysc/sysc.o \ + ip/avs/avs.o \ + ip/i2c/i2c.o \ + ip/ddr/v4m/lpddr5/ecc_enable_v4m.o \ + ip/ddr/v4m/lpddr5/ecm_enable_v4m.o +else + $(error "Error: ${LSI} is not supported.") +endif +$(eval $(call add_define,RCAR_LSI)) + + + + +#output file name +FILE_NAME = icumx_loader +FILE_NAME_SA0 = bootparam_sa0 +FILE_NAME_SA9 = cert_header_sa9 +FILE_NAME_TFMV_TBL = tfmv_ver_tbl +FILE_NAME_NTFMV_TBL = ntfmv_ver_tbl + +OUTPUT_FILE = $(FILE_NAME).elf +OUTPUT_FILE_SA0 = $(FILE_NAME_SA0).elf +OUTPUT_FILE_SA9 = $(FILE_NAME_SA9).elf +OUTPUT_FILE_TFMV_TBL = $(FILE_NAME_TFMV_TBL).elf +OUTPUT_FILE_NTFMV_TBL = $(FILE_NAME_NTFMV_TBL).elf + +#object file name +OBJ_FILE += cpu_on/cpu_on.o \ + common/log/log.o \ + common/log/scif.o \ + common/timer/micro_wait.o \ + image_load/image_load.o \ + intc/intc.o \ + intc/vecttbl.o \ + intc/vect_set.o \ + ip/ip_control.o \ + ip/cpg/cpg.o \ + ip/emmc/emmc_boot.o \ + ip/wdt/wdt.o \ + loader/loader.o \ + loader/loader_main_common.o \ + protect/ram_protection.o \ + protect/region_id.o \ + protect/stack_protect.o \ + remap/remap.o \ + rom_api/rom_api.o + + +OBJ_FILE_SA0 = tools/dummy_create/sa0.o +OBJ_FILE_SA9 = tools/dummy_create/$(DIR_NAME_SA9)/sa9.o +OBJ_FILE_TFMV_TBL = tools/sw_min_ver_tbl/tfmv_ver_tbl.o +OBJ_FILE_NTFMV_TBL = tools/sw_min_ver_tbl/ntfmv_ver_tbl.o + +#linker script name +ifeq (${LSI},V4M) + MEMORY_DEF = loader/icumx_loader_v4m.ld +else + MEMORY_DEF = loader/icumx_loader.ld +endif + +MEMORY_DEF_SA0 = tools/dummy_create/sa0.ld +MEMORY_DEF_SA9 = tools/dummy_create/$(DIR_NAME_SA9)/sa9.ld +MEMORY_DEF_TFMV_TBL = tools/sw_min_ver_tbl/tfmv_ver_tbl.ld +MEMORY_DEF_NTFMV_TBL = tools/sw_min_ver_tbl/ntfmv_ver_tbl.ld + +################################################### + +# Debug build +DEBUG:=0 + +# Process DEBUG flag +$(eval $(call assert_boolean,DEBUG)) +$(eval $(call add_define,DEBUG)) +ifeq (${DEBUG},0) + $(eval $(call add_define,NDEBUG)) +CFLAGS += -Onone +else +ASFLAGS += -G -dwarf2 +CFLAGS += -G -dwarf2 -Odebug +endif + +# MISRA Option +#------ MISRA ------ +ifndef MISRA +MISRA := MANDATORY +endif +ifeq ("$(MISRA)", "DISABLE") + MISRA_OPTION = DISABLE +else ifeq ("$(MISRA)", "FULL") + MISRA_OPTION = FULL +else ifeq ("$(MISRA)", "MANDATORY") + MISRA_OPTION = MANDATORY +else ifeq ("$(MISRA)", "REQUIRED") + MISRA_OPTION = REQUIRED +endif +CFLAGS_MISRA_FULL = \ + --misra_adv=warn \ + --misra_req=warn \ + --misra_mand=warn \ + --no_misra_runtime \ + --misra_2012=all,-R1.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later +CFLAGS_MISRA_REQUIRED = \ + --misra_adv=silent \ + --misra_req=warn \ + --misra_mand=warn \ + --no_misra_runtime \ + --misra_2012=all,-R1.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later +CFLAGS_MISRA_MANDATORY = \ + --misra_adv=silent \ + --misra_req=silent \ + --misra_mand=warn \ + --no_misra_runtime \ + --misra_2012=all,-R1.1,-R3.1 # MISRA 2012 Rule 1.1 not allowed with non-strict -c99 or later + # MISRA 2012 Rule 3.1 is confirmed with static analysis +ifeq ("$(MISRA_OPTION)", "FULL") +CFLAGS += $(CFLAGS_MISRA_FULL) +else ifeq ("$(MISRA)", "REQUIRED") +CFLAGS += $(CFLAGS_MISRA_REQUIRED) +else ifeq ("$(MISRA)", "MANDATORY") +CFLAGS += $(CFLAGS_MISRA_MANDATORY) +endif + +# Process LOG_LEVEL +ifndef LOG_LEVEL +LOG_LEVEL := 2 +endif +$(eval $(call add_define,LOG_LEVEL)) +ifeq (${LOG_LEVEL},0) + LDFLAGS += -nostdlib +endif + +# Process SET_FCPR_PARAM flag +# 0:Disable, 1:Enable (Support V4H / V4M Linux OS) +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef SET_FCPR_PARAM + SET_FCPR_PARAM := 0 + $(eval $(call add_define,SET_FCPR_PARAM)) + else + ifeq (${SET_FCPR_PARAM},0) + $(eval $(call add_define,SET_FCPR_PARAM)) + else ifeq (${SET_FCPR_PARAM},1) + $(eval $(call add_define,SET_FCPR_PARAM)) + else + $(error "Error:SET_FCPR_PARAM=${SET_FCPR_PARAM} is not supported.") + endif + endif +else + SET_FCPR_PARAM := 0 + $(eval $(call add_define,SET_FCPR_PARAM)) +endif + +# Process BOOT_MCU flag (S4 only) +# 0:None, 1:G4MH, 2:Reserved, 3:G4MH+ICUMH +ifeq (${LSI},S4) + ifndef BOOT_MCU + BOOT_MCU :=3 + $(eval $(call add_define,BOOT_MCU)) + else + ifeq (${BOOT_MCU},0) + $(eval $(call add_define,BOOT_MCU)) + else ifeq (${BOOT_MCU},1) + $(eval $(call add_define,BOOT_MCU)) + else ifeq (${BOOT_MCU},2) + $(eval $(call add_define,BOOT_MCU)) + else ifeq (${BOOT_MCU},3) + $(eval $(call add_define,BOOT_MCU)) + else + $(error "Error:BOOT_MCU=${BOOT_MCU} is not supported.") + endif + endif +else + BOOT_MCU :=0 + $(eval $(call add_define,BOOT_MCU)) +endif + +ifneq (${BOOT_MCU},0) +OBJ_FILE += mcu/cpu_on_for_mcu.o \ + mcu/sdmac.o \ + mcu/loader_main_mcu.o \ + mcu/image_load_for_mcu.o \ + mcu/codesram_ecc.o +endif + +# Process RTVRAM_EXTEND flag +ifeq (${LSI},S4) + ifndef RTVRAM_EXTEND + RTVRAM_EXTEND := 1 + $(eval $(call add_define,RTVRAM_EXTEND)) + else + ifeq (${RTVRAM_EXTEND},0) + $(eval $(call add_define,RTVRAM_EXTEND)) + else ifeq (${RTVRAM_EXTEND},1) + $(eval $(call add_define,RTVRAM_EXTEND)) + else + $(error "Error:RTVRAM_EXTEND=${RTVRAM_EXTEND} is not supported.") + endif + endif +endif + +# Process QSPI_DDR_MODE flag +# 0:SDR, 1:DDR +ifndef QSPI_DDR_MODE +QSPI_DDR_MODE := 0 +$(eval $(call add_define,QSPI_DDR_MODE)) +else + ifeq (${QSPI_DDR_MODE},0) + $(eval $(call add_define,QSPI_DDR_MODE)) + else ifeq (${QSPI_DDR_MODE},1) + $(eval $(call add_define,QSPI_DDR_MODE)) + else + $(error "Error:QSPI_DDR_MODE=${QSPI_DDR_MODE} is not supported.") + endif +endif + +# RCAR_QSPI_DDR_DUMMY_CYCLE +ifndef RCAR_QSPI_DDR_DUMMY_CYCLE +RCAR_QSPI_DDR_DUMMY_CYCLE := 9 +endif +$(eval $(call add_define,RCAR_QSPI_DDR_DUMMY_CYCLE)) + +# Process RCAR_SA9_TYPE flag +# 0:Flash, 1:eMMC +ifeq (${LSI},S4) + ifndef RCAR_SA9_TYPE + RCAR_SA9_TYPE := 0 + $(eval $(call add_define,RCAR_SA9_TYPE)) + else + ifeq (${RCAR_SA9_TYPE},0) + $(eval $(call add_define,RCAR_SA9_TYPE)) + else ifeq (${RCAR_SA9_TYPE},1) + $(eval $(call add_define,RCAR_SA9_TYPE)) + else + $(error "Error:RCAR_SA9_TYPE=${RCAR_SA9_TYPE} is not supported.") + endif + endif +else ifeq ($(filter ${LSI},V4H V4M),${LSI}) + RCAR_SA9_TYPE := 0 + $(eval $(call add_define,RCAR_SA9_TYPE)) +endif + + +ifeq (${RCAR_SA9_TYPE},1) +OBJ_FILE += image_load/image_load_emmc.o \ + ip/emmc/emmc_cmd.o \ + ip/emmc/emmc_init.o \ + ip/emmc/emmc_interrupt.o \ + ip/emmc/emmc_mount.o \ + ip/emmc/emmc_multiboot.o \ + ip/emmc/emmc_read.o \ + ip/emmc/emmc_utility.o +else ifeq (${RCAR_SA9_TYPE},0) +OBJ_FILE += image_load/image_load_flash.o \ + ip/dma/dma.o \ + ip/rpc/rpc.o \ + ip/mfis/mfis.o +endif + +# Process CA_LOAD_TYPE flag +# 0:CA Loader 1:BL31 (or Secure Monitor) +ifeq (${LSI},S4) + ifndef CA_LOAD_TYPE + CA_LOAD_TYPE := 0 + $(eval $(call add_define,CA_LOAD_TYPE)) + else + ifeq (${CA_LOAD_TYPE},0) + $(eval $(call add_define,CA_LOAD_TYPE)) + else ifeq (${CA_LOAD_TYPE},1) + $(eval $(call add_define,CA_LOAD_TYPE)) + else + $(error "Error:CA_LOAD_TYPE=${CA_LOAD_TYPE} is not supported.") + endif + endif +else ifeq ($(filter ${LSI},V4H V4M),${LSI}) + CA_LOAD_TYPE := 0 + $(eval $(call add_define,CA_LOAD_TYPE)) +endif + +ifeq (${RCAR_SA9_TYPE},1) + ifeq (${CA_LOAD_TYPE},0) + $(error "Error:RCAR_SA9_TYPE=1 and CA_LOAD_TYPE=0 is not supported.") + endif +endif + +# Process MCU_SECURE_BOOT flag (S4 only) +ifndef MCU_SECURE_BOOT + MCU_SECURE_BOOT := 0 + $(eval $(call add_define,MCU_SECURE_BOOT)) +else + ifeq (${MCU_SECURE_BOOT},0) + $(eval $(call add_define,MCU_SECURE_BOOT)) + else ifeq (${MCU_SECURE_BOOT},1) + ifeq (${BOOT_MCU},0) + $(error "Error:MCU_SECURE_BOOT=${MCU_SECURE_BOOT} and BOOT_MCU=${BOOT_MCU} is not supported.") + else + $(eval $(call add_define,MCU_SECURE_BOOT)) + endif + else + $(error "Error:MCU_SECURE_BOOT=${MCU_SECURE_BOOT} is not supported.") + endif +endif + +# Process SW_VERSION_CHECK flag +# 0:Disable 1:Enable +ifndef SW_VERSION_CHECK +SW_VERSION_CHECK := 0 +$(eval $(call add_define,SW_VERSION_CHECK)) +else + ifeq (${SW_VERSION_CHECK},0) + $(eval $(call add_define,SW_VERSION_CHECK)) + else ifeq (${SW_VERSION_CHECK},1) + $(eval $(call add_define,SW_VERSION_CHECK)) + else + $(error "Error:SW_VERSION_CHECK=${SW_VERSION_CHECK} is not supported.") + endif +endif + +# Process access protection flag +# 0:Disable 1:Enable +ifndef ACC_PROT_ENABLE +ACC_PROT_ENABLE := 0 +$(eval $(call add_define,ACC_PROT_ENABLE)) +else + ifeq (${ACC_PROT_ENABLE},0) + $(eval $(call add_define,ACC_PROT_ENABLE)) + else ifeq (${ACC_PROT_ENABLE},1) + $(eval $(call add_define,ACC_PROT_ENABLE)) + else + $(error "Error:ACC_PROT_ENABLE=${ACC_PROT_ENABLE} is not supported.") + endif +endif + +ifeq (${MCU_SECURE_BOOT},1) +include mcu_secureboot/mcu_secureboot.mk +endif + +# Process ADD_HOTPLUG_MAGIC flag +ifndef ADD_HOTPLUG_MAGIC + ADD_HOTPLUG_MAGIC := 0 + $(eval $(call add_define,ADD_HOTPLUG_MAGIC)) +else + ifeq (${ADD_HOTPLUG_MAGIC},0) + $(eval $(call add_define,ADD_HOTPLUG_MAGIC)) + else ifeq (${ADD_HOTPLUG_MAGIC},1) + $(eval $(call add_define,ADD_HOTPLUG_MAGIC)) + else + $(error "Error:ADD_HOTPLUG_MAGIC=${ADD_HOTPLUG_MAGIC} is not supported.") + endif +endif + +# Process STACK_PROTECT flag +ifndef STACK_PROTECT + STACK_PROTECT := 0 + $(eval $(call add_define,STACK_PROTECT)) +else + ifeq (${STACK_PROTECT},0) + $(eval $(call add_define,STACK_PROTECT)) + else ifeq (${STACK_PROTECT},1) + $(eval $(call add_define,STACK_PROTECT)) + CFLAGS += -stack_protector + else + $(error "Error:STACK_PROTECT=${STACK_PROTECT} is not supported.") + endif +endif + +# Process RTOS_LOAD_NUM flag +# 1:RTOS#0 only 3:RTOS#0,#1,#2 +ifndef RTOS_LOAD_NUM + RTOS_LOAD_NUM := 1 + $(eval $(call add_define,RTOS_LOAD_NUM)) +else + ifeq (${RTOS_LOAD_NUM},1) + $(eval $(call add_define,RTOS_LOAD_NUM)) + else ifeq (${RTOS_LOAD_NUM},3) + $(eval $(call add_define,RTOS_LOAD_NUM)) + else + $(error "Error:RTOS_LOAD_NUM=${RTOS_LOAD_NUM} is not supported.") + endif +endif + +# Process OPTEE_LOAD_ENABLE flag +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef OPTEE_LOAD_ENABLE + OPTEE_LOAD_ENABLE := 1 + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else + ifeq (${OPTEE_LOAD_ENABLE},0) + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else ifeq (${OPTEE_LOAD_ENABLE},1) + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else + $(error "Error:OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.") + endif + endif +endif + +################################################### +# pass SecureMonitor parametor +################################################### +# Process SET_CA_PARAM flag +ifeq (${LSI},S4) + ifndef SET_CA_PARAM + SET_CA_PARAM := 1 + $(eval $(call add_define,SET_CA_PARAM)) + else + ifeq (${SET_CA_PARAM},0) + $(eval $(call add_define,SET_CA_PARAM)) + else ifeq (${SET_CA_PARAM},1) + $(eval $(call add_define,SET_CA_PARAM)) + else + $(error "Error:SET_CA_PARAM=${SET_CA_PARAM} is not supported.") + endif + endif +endif + +# Process ECM_ENABLE +ifndef ECM_ENABLE + ECM_ENABLE:= 0 + $(eval $(call add_define,ECM_ENABLE)) +else + ifeq (${ECM_ENABLE},0) + $(eval $(call add_define,ECM_ENABLE)) + else ifeq (${ECM_ENABLE},1) + $(eval $(call add_define,ECM_ENABLE)) + else + $(error "Error: ECM_ENABLE=${ECM_ENABLE} is not supported.") + endif +endif + +# Process ECM_ERROR_ENABLE flag +ifndef ECM_ERROR_ENABLE + ECM_ERROR_ENABLE := 1 + $(eval $(call add_define,ECM_ERROR_ENABLE)) +else + ifeq (${ECM_ERROR_ENABLE},0) + $(eval $(call add_define,ECM_ERROR_ENABLE)) + else ifeq (${ECM_ERROR_ENABLE},1) + $(eval $(call add_define,ECM_ERROR_ENABLE)) + else + $(error "Error:ECM_ERROR_ENABLE=${ECM_ERROR_ENABLE} is not supported.") + endif +endif + + +# Process DBSC HUNGUP WA +ifndef WA_OTLINT5579 + WA_OTLINT5579:= 1 +endif +$(eval $(call add_define,WA_OTLINT5579)) + +################################################### + +OUTDIR_REL := $(OUTDIR)/release +OUTDIR_OBJ := $(OUTDIR)/obj + +OBJ_FILE := $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o) +OBJ_FILE_SA0 := $(OBJ_FILE_SA0:%.o=$(OUTDIR_OBJ)/%.o) +OBJ_FILE_SA9 := $(OBJ_FILE_SA9:%.o=$(OUTDIR_OBJ)/%.o) +OBJ_FILE_TFMV_TBL := $(OBJ_FILE_TFMV_TBL:%.o=$(OUTDIR_OBJ)/%.o) +OBJ_FILE_NTFMV_TBL := $(OBJ_FILE_NTFMV_TBL:%.o=$(OUTDIR_OBJ)/%.o) + +CC = cxrh850 +AS = cxrh850 +LD = cxrh850 +OC = gsrec +OD = gdump + +ASFLAGS += -asm="-preprocess_assembly_files" \ + -asm="-nostartfiles" \ + -D__ASSEMBLY \ + $(INCLUDE_DIR) $(DEFINES) + +CFLAGS += -nostartfiles \ + -c99 \ + $(INCLUDE_DIR) $(DEFINES) \ + --ghstd=last \ + -Wundef \ + --diag_error=193 \ + --prototype_errors +# --ghstd=last : Enable Green Hills Standard Mode +# -Wundef : Output warning if there are any undefined symbols +# --diag_error=193 : Error if zero is applied to undefined symbol +# --prototype_errors : Error if there are no any prototype declaration + +ifeq (${LOG_LEVEL},0) +# There are no any additional options +else +CFLAGS += --diag_suppress=1932 # There is warning that format string parameter in sprintf is not constant +endif + +LDFLAGS += -nostartfiles -Mu + +BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__ + +################################################### +.SUFFIXES : .s .c .o + +################################################### +# command + +.PHONY: all +all: $(OUTPUT_FILE) $(OUTPUT_FILE_SA0) $(OUTPUT_FILE_SA9) $(OUTPUT_FILE_TFMV_TBL) $(OUTPUT_FILE_NTFMV_TBL) + +################################################### +# Linker +################################################### +$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE) + @echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' > $(OUTDIR_OBJ)/build_message.c + @$(CC) $(CFLAGS) -o $(OUTDIR_OBJ)/build_message.o -c $(OUTDIR_OBJ)/build_message.c + + @$(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \ + -T $(MEMORY_DEF) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE) \ + $(LDFLAGS) \ + -map=$(OUTDIR_REL)/$(FILE_NAME).map + + @$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).srec + @$(OD) -full -ysec $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE) -o $(OUTDIR_REL)/$(OUTPUT_FILE:%.elf=%.bin) + +$(OUTPUT_FILE_SA0) : $(MEMORY_DEF_SA0) $(OBJ_FILE_SA0) + @$(LD) $(OBJ_FILE_SA0) \ + -T $(MEMORY_DEF_SA0) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) \ + -map=$(OUTDIR_REL)/$(FILE_NAME_SA0).map \ + -nostdlib + + @$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) > $(OUTDIR_REL)/$(FILE_NAME_SA0).srec + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA0) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA0:%.elf=%.bin) + +$(OUTPUT_FILE_SA9) : $(MEMORY_DEF_SA9) $(OBJ_FILE_SA9) + @$(LD) $(OBJ_FILE_SA9) \ + -T $(MEMORY_DEF_SA9) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) \ + -map=$(OUTDIR_REL)/$(FILE_NAME_SA9).map \ + -nostdlib + + @$(OC) -S3 -bytes 16 -noS5 $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) > $(OUTDIR_REL)/$(FILE_NAME_SA9).srec + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_SA9) -o $(OUTDIR_REL)/$(OUTPUT_FILE_SA9:%.elf=%.bin) + +$(OUTPUT_FILE_TFMV_TBL) : $(MEMORY_DEF_TFMV_TBL) $(OBJ_FILE_TFMV_TBL) + @$(LD) $(OBJ_FILE_TFMV_TBL) \ + -T $(MEMORY_DEF_TFMV_TBL) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL) \ + -map=$(OUTDIR_REL)/$(FILE_NAME_TFMV_TBL).map \ + -nostdlib + + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL) -o $(OUTDIR_REL)/$(OUTPUT_FILE_TFMV_TBL:%.elf=%.bin) + +$(OUTPUT_FILE_NTFMV_TBL) : $(MEMORY_DEF_NTFMV_TBL) $(OBJ_FILE_NTFMV_TBL) + @$(LD) $(OBJ_FILE_NTFMV_TBL) \ + -T $(MEMORY_DEF_NTFMV_TBL) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL) \ + -map=$(OUTDIR_REL)/$(FILE_NAME_NTFMV_TBL).map \ + -nostdlib + + @gmemfile $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL) -o $(OUTDIR_REL)/$(OUTPUT_FILE_NTFMV_TBL:%.elf=%.bin) + +################################################### +# Compile +################################################### + +$(OUTDIR_OBJ)/%.o:%.c + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + @$(CC) $(CFLAGS) -o $@ -c $< + +$(OUTDIR_OBJ)/%.o:%.S + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + @$(AS) $(ASFLAGS) -o $@ -c $< + + +.PHONY: clean +clean: + @rm -rf $(OUTDIR) diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_s4.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_s4.c new file mode 100644 index 0000000..2d38556 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_s4.c @@ -0,0 +1,2468 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table + ******************************************************************************/ +/****************************************************************************** + * @file cnf_tbl.c + * - Version : 0.02 + * @brief Configuration table for S4. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 23.05.2022 0.02 Integration of S4 and V4H + * Renamed from conf_tbl.c to cnf_tbl_s4.c. + * : 23.01.2023 0.03 Update the set value of Region ID. + * Add the RAM access protection + * setting value tables. + *****************************************************************************/ + +#include +#include +#include +#include +#include + +#define RTDMA_EN (0x00000002U) +#define SYSDMA_EN (0x0000BFC4U) + +#pragma ghs section rodata=".qosbw_tbl" +const QOS_SETTING_TABLE g_qosbw_tbl[] = { + [0] = {0x000C04020000FFFFULL, 0x00100000031FFC01ULL}, + [1] = {0x000C04080000FFFFULL, 0x00100000031FFC01ULL}, + [2] = {0x000C08100000FFFFULL, 0x00100000031FFC01ULL}, + [3] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [4] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [5] = {0x000C04020000FFFFULL, 0x00100000031FFC01ULL}, + [6] = {0x000C04080000FFFFULL, 0x00100000031FFC01ULL}, + [7] = {0x000C08100000FFFFULL, 0x00200000031FFC01ULL}, + [8] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [9] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [10] = {0x000C04020000FFFFULL, 0x00100000031FFC01ULL}, + [11] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [12] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [13] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [14] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [15] = {0x000C04020000FFFFULL, 0x00100000031FFC01ULL}, + [16] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [17] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [18] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [19] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [20] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [21] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [22] = {0x000C04280000FFFFULL, 0x00100000031FFC01ULL}, + [23] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [24] = {0x000C08280000FFFFULL, 0x00100000031FFC01ULL}, + [25] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [26] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [27] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [28] = {0x000C14280000FFFFULL, 0x00100000031FFC01ULL}, + [29] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [30] = {0x001008280000FFFFULL, 0x00100000031FFC01ULL}, + [31] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [32] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [33] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [34] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [35] = {0x000C04020000FFFFULL, 0x00100000031FFC01ULL}, + [36] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [37] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [38] = {0x001404100000FFFFULL, 0x00100000031FFC01ULL}, + [39] = {0x001404100000FFFFULL, 0x00100000031FFC01ULL}, + [40] = {0x000C1C6F0000FFFFULL, 0x00100000031FFC01ULL}, + [41] = {0x000C103F0000FFFFULL, 0x00100000031FFC01ULL}, + [42] = {0x000C04100000FFFFULL, 0x00100000031FFC01ULL}, + [43] = {0x000C144F0000FFFFULL, 0x00100000031FFC01ULL}, + [44] = {0x001408200000FFFFULL, 0x00100000031FFC01ULL}, + [45] = {0x0014185F0000FFFFULL, 0x00100000031FFC01ULL}, + [46] = {0x000C0C300000FFFFULL, 0x00100000031FFC01ULL}, + [47] = {0x000C1C6F0000FFFFULL, 0x00100000031FFC01ULL} +}; + + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".qoswt_tbl" +const QOS_SETTING_TABLE g_qoswt_tbl[] = { + [0] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [1] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [2] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [3] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [4] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [5] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [6] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [7] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [8] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [9] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [10] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [11] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [12] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [13] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [14] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [15] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [16] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [17] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [18] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [19] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [20] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [21] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [22] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [23] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [24] = {0x000C08280000FFF0ULL, 0x0000000000000000ULL}, + [25] = {0x000C00000000FFF0ULL, 0x0000000000000000ULL}, + [26] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [27] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [28] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [29] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [30] = {0x001008280000C010ULL, 0x0000000000000000ULL}, + [31] = {0x000C00000000C010ULL, 0x0000000000000000ULL}, + [32] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [33] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [34] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [35] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [36] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [37] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [38] = {0x001404100000FFF0ULL, 0x0000000000000000ULL}, + [39] = {0x001404100000C010ULL, 0x0000000000000000ULL}, + [40] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [41] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [42] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [43] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [44] = {0x0014000000000000ULL, 0x0000000000000000ULL}, + [45] = {0x0014000000000000ULL, 0x0000000000000000ULL}, + [46] = {0x000C000000000000ULL, 0x0000000000000000ULL}, + [47] = {0x000C000000000000ULL, 0x0000000000000000ULL} +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + + +#pragma ghs section rodata=".rgid_m_tbl" +const REGION_ID_SETTING_TABLE g_rgid_m_tbl[] = { + [0] = {0xFCF81000U, 0x00000002U}, /* RGIDM_MODID[0]:PCI0 */ + [1] = {0xFCF81020U, 0x00000002U}, /* RGIDM_MODID[1]:PCI1 */ + [2] = {0xFCF81024U, 0x00000002U}, /* RGIDM_MODID[2]:PCI2 */ + [3] = {0xFCF81034U, 0x00000002U}, /* RGIDM_MODID[3]:PCI3 */ + [4] = {0xFCF81038U, 0x00000002U}, /* RGIDM_MODID[4]:RSW2 */ + [5] = {0xFCF8103CU, 0x00000001U}, /* RGIDM_MODID[5]:RSW2SEC */ + [6] = {0xFCF81044U, 0x00000002U}, /* RGIDM_MODID[6]:UFS */ + [7] = {0xFDC21004U, 0x00000000U}, /* RGIDM_MODID[7]:CR0 */ + [8] = {0xFDC2100CU, 0x00000000U}, /* RGIDM_MODID[8]:ICUMX */ + [9] = {0xFDC21010U, 0x00000000U}, /* RGIDM_MODID[9]:ICUMX */ + [10] = {0xFDC21014U, 0x00000000U}, /* RGIDM_MODID[10]:ICUMX */ + [11] = {0xFD441018U, 0x00000001U}, /* RGIDM_MODID[11]:CR52SS */ + [12] = {0xFD44101CU, 0x00000003U}, /* RGIDM_MODID[12]:CSD */ + [13] = {0xFD441024U, 0x00000002U}, /* RGIDM_MODID[13]:INTAP0 */ + [14] = {0xFD441068U, 0x00000005U}, /* RGIDM_MODID[14]:ControlDomain0 */ + [15] = {0xFD44106CU, 0x00000005U}, /* RGIDM_MODID[15]:ControlDomain1 */ + [16] = {0xFD4410A0U, 0x00000005U}, /* RGIDM_MODID[16]:ControlDomain2 */ + [17] = {0xFD4410ACU, 0x00000005U}, /* RGIDM_MODID[17]:ControlDomain3 */ + [18] = {0xFD4410B0U, 0x00000005U}, /* RGIDM_MODID[18]:ControlDomain4 */ + [19] = {0xFD4410B4U, 0x00000005U}, /* RGIDM_MODID[19]:ControlDomain5 */ + [20] = {0xFD4410B8U, 0x00000005U}, /* RGIDM_MODID[20]:ControlDomain6 */ + [21] = {0xFD4410BCU, 0x00000005U}, /* RGIDM_MODID[21]:ControlDomain7 */ + [22] = {0xFD4410C0U, 0x00000005U}, /* RGIDM_MODID[22]:ControlDomain8 */ + [23] = {0xFD4410C4U, 0x00000005U}, /* RGIDM_MODID[23]:ControlDomain9 */ + [24] = {0xFD441078U, 0x00000005U}, /* RGIDM_MODID[24]:ControlDomain10 */ + [25] = {0xFD44107CU, 0x00000005U}, /* RGIDM_MODID[25]:ControlDomain11 */ + [26] = {0xFD441080U, 0x00000005U}, /* RGIDM_MODID[26]:ControlDomain12 */ + [27] = {0xFD441084U, 0x00000004U}, /* RGIDM_MODID[27]:ControlDomain13 */ + [28] = {0xFD441088U, 0x00000004U}, /* RGIDM_MODID[28]:ControlDomain14 */ + [29] = {0xFD44108CU, 0x00000005U}, /* RGIDM_MODID[29]:ControlDomain15 */ + [30] = {0xFD441090U, 0x00000005U}, /* RGIDM_MODID[30]:ControlDomain16 */ + [31] = {0xFD441094U, 0x00000005U}, /* RGIDM_MODID[31]:ControlDomain17 */ + [32] = {0xFD441098U, 0x00000005U}, /* RGIDM_MODID[32]:ControlDomain18 */ + [33] = {0xFD44109CU, 0x00000005U}, /* RGIDM_MODID[33]:ControlDomain19 */ + [34] = {0xFD4410A4U, 0x00000005U}, /* RGIDM_MODID[34]:ControlDomain20 */ + [35] = {0xFD4410A8U, 0x00000003U}, /* RGIDM_MODID[35]:ControlDomain21 */ + [36] = {0xFF861018U, 0x00000002U}, /* RGIDM_MODID[36]:FBABUSTOP0 */ + [37] = {0xFF86101CU, 0x00000002U}, /* RGIDM_MODID[37]:FBABUSTOP1 */ + [38] = {0xFCB51020U, 0x00000002U}, /* RGIDM_MODID[38]:SDHI0 */ + [39] = {0xFF811000U, 0x00000002U}, /* RGIDM_MODID[39]:AXMM2AXSTM */ + [40] = {0xFF811004U, 0x00000003U}, /* RGIDM_MODID[40]:CSDE0 */ + [41] = {0xFF811008U, 0x00000003U}, /* RGIDM_MODID[41]:CSDE1 */ + [42] = {0xFDDBF500U, 0x0000000EU}, /* RGIDM_MODID[42]:VRAM_R */ + [43] = {0xFDDBF504U, 0x0000000EU}, /* RGIDM_MODID[43]:VRAM_W */ + +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_r_tbl" +const REGION_ID_SETTING_TABLE g_rgid_r_tbl[] = { + [0] = {0xFD482000U, 0x0000002EU}, /* RGIDR_MODID[0]:ARMGC0 */ + [1] = {0xFD482004U, 0x0000002EU}, /* RGIDR_MODID[1]:ARMGC1 */ + [2] = {0xFD482008U, 0x00000000U}, /* RGIDR_MODID[2]:ARMGC2 */ + [3] = {0xFD48200CU, 0x0000003FU}, /* RGIDR_MODID[3]:ARRT00 */ + /* After setting */ /* RGIDR_MODID[4]:ARRT01 */ + /* After setting */ /* RGIDR_MODID[5]:ARRT02 */ + [4] = {0xFD482018U, 0x0000003FU}, /* RGIDR_MODID[6]:ARRT03 */ + [5] = {0xFD48201CU, 0x0000003FU}, /* RGIDR_MODID[7]:ARRT04 */ + [6] = {0xFD482020U, 0x0000003FU}, /* RGIDR_MODID[8]:ARRT05 */ + [7] = {0xFD482024U, 0x0000003FU}, /* RGIDR_MODID[9]:ARRT06 */ + [8] = {0xFD482028U, 0x0000003FU}, /* RGIDR_MODID[10]:ARRT07 */ + [9] = {0xFD48202CU, 0x00000000U}, /* RGIDR_MODID[11]:ARRT08 */ + [10] = {0xFD482030U, 0x00000011U}, /* RGIDR_MODID[12]:LIFEC0 */ + [11] = {0xFD482034U, 0x00000026U}, /* RGIDR_MODID[13]:SWDT */ + [12] = {0xFD482038U, 0x0000003FU}, /* RGIDR_MODID[14]:TMU0 */ + [13] = {0xFD48203CU, 0x00000026U}, /* RGIDR_MODID[15]:WDT */ + [14] = {0xFD482040U, 0x00000026U}, /* RGIDR_MODID[16]:WWDT0 */ + [15] = {0xFD482044U, 0x00000026U}, /* RGIDR_MODID[17]:WWDT1 */ + [16] = {0xFD482048U, 0x00000026U}, /* RGIDR_MODID[18]:WWDT2 */ + [17] = {0xFD48204CU, 0x00000026U}, /* RGIDR_MODID[19]:WWDT3 */ + [18] = {0xFD482050U, 0x00000026U}, /* RGIDR_MODID[20]:WWDT4 */ + [19] = {0xFD482054U, 0x00000026U}, /* RGIDR_MODID[21]:WWDT5 */ + [20] = {0xFD482058U, 0x00000026U}, /* RGIDR_MODID[22]:WWDT6 */ + [21] = {0xFD48205CU, 0x00000026U}, /* RGIDR_MODID[23]:WWDT7 */ + [22] = {0xFD482060U, 0x00000026U}, /* RGIDR_MODID[24]:WWDT8 */ + [23] = {0xFD482064U, 0x00000026U}, /* RGIDR_MODID[25]:WWDT9 */ + [24] = {0xFD482068U, 0x0000003FU}, /* RGIDR_MODID[26]:ECMRT3 */ + [25] = {0xFDA02000U, 0x0000002EU}, /* RGIDR_MODID[27]:ADVFSC */ + [26] = {0xFDA02004U, 0x0000003FU}, /* RGIDR_MODID[28]:APMU0 */ + [27] = {0xFDA02008U, 0x00000002U}, /* RGIDR_MODID[29]:APMU1 */ + [28] = {0xFDA0200CU, 0x00000000U}, /* RGIDR_MODID[30]:APMU10 */ + [29] = {0xFDA02010U, 0x00000000U}, /* RGIDR_MODID[31]:APMU11 */ + [30] = {0xFDA02014U, 0x00000000U}, /* RGIDR_MODID[32]:APMU12 */ + [31] = {0xFDA02018U, 0x00000000U}, /* RGIDR_MODID[33]:APMU13 */ + [32] = {0xFDA0201CU, 0x00000000U}, /* RGIDR_MODID[34]:APMU14 */ + [33] = {0xFDA02020U, 0x00000000U}, /* RGIDR_MODID[35]:APMU15 */ + [34] = {0xFDA02024U, 0x00000004U}, /* RGIDR_MODID[36]:APMU2 */ + [35] = {0xFDA02028U, 0x00000004U}, /* RGIDR_MODID[37]:APMU3 */ + [36] = {0xFDA0202CU, 0x00000000U}, /* RGIDR_MODID[38]:APMU4 */ + [37] = {0xFDA02030U, 0x00000000U}, /* RGIDR_MODID[39]:APMU5 */ + [38] = {0xFDA02034U, 0x00000000U}, /* RGIDR_MODID[40]:APMU6 */ + [39] = {0xFDA02038U, 0x00000000U}, /* RGIDR_MODID[41]:APMU7 */ + [40] = {0xFDA0203CU, 0x00000000U}, /* RGIDR_MODID[42]:APMU8 */ + [41] = {0xFDA02040U, 0x00000000U}, /* RGIDR_MODID[43]:APMU9 */ + [42] = {0xFDA02044U, 0x0000003FU}, /* RGIDR_MODID[44]:ARS00 */ + /* After setting */ /* RGIDR_MODID[45]:ARS01 */ + /* After setting */ /* RGIDR_MODID[46]:ARS02 */ + [43] = {0xFDA02050U, 0x0000003FU}, /* RGIDR_MODID[47]:ARS03 */ + [44] = {0xFDA02054U, 0x0000003FU}, /* RGIDR_MODID[48]:ARS04 */ + [45] = {0xFDA02058U, 0x0000003FU}, /* RGIDR_MODID[49]:ARS05 */ + [46] = {0xFDA0205CU, 0x0000003FU}, /* RGIDR_MODID[50]:ARS06 */ + [47] = {0xFDA02060U, 0x0000003FU}, /* RGIDR_MODID[51]:ARS07 */ + [48] = {0xFDA02064U, 0x00000000U}, /* RGIDR_MODID[52]:ARS08 */ + [49] = {0xFDA02068U, 0x0000002EU}, /* RGIDR_MODID[53]:CMT0 */ + [50] = {0xFDA0206CU, 0x0000002EU}, /* RGIDR_MODID[54]:CMT1 */ + [51] = {0xFDA02070U, 0x0000002EU}, /* RGIDR_MODID[55]:CMT2 */ + [52] = {0xFDA02074U, 0x0000002EU}, /* RGIDR_MODID[56]:CMT3 */ + [53] = {0xFDA02078U, 0x0000002AU}, /* RGIDR_MODID[57]:CKM */ + [54] = {0xFDA0207CU, 0x0000002EU}, /* RGIDR_MODID[58]:DBE */ + [55] = {0xFDA02080U, 0x0000002EU}, /* RGIDR_MODID[59]:IRQC */ + [56] = {0xFDA02084U, 0x0000003BU}, /* RGIDR_MODID[60]:ECMPS0 */ + [57] = {0xFDA0209CU, 0x0000002EU}, /* RGIDR_MODID[61]:SCMT */ + [58] = {0xFDA020A8U, 0x0000002EU}, /* RGIDR_MODID[62]:TSC1 */ + [59] = {0xFDA020ACU, 0x0000002EU}, /* RGIDR_MODID[63]:TSC2 */ + [60] = {0xFDA020B0U, 0x0000002EU}, /* RGIDR_MODID[64]:TSC3 */ + [61] = {0xFDA020B4U, 0x0000002EU}, /* RGIDR_MODID[65]:TSC4 */ + [62] = {0xFDA020B8U, 0x00000026U}, /* RGIDR_MODID[66]:UCMT */ + [63] = {0xFDA02100U, 0x0000003FU}, /* RGIDR_MODID[67]:CPG0 */ + [64] = {0xFDA02104U, 0x0000002AU}, /* RGIDR_MODID[68]:CPG1 */ + [65] = {0xFDA02108U, 0x0000000CU}, /* RGIDR_MODID[69]:CPG2 */ + [66] = {0xFDA0210CU, 0x0000000CU}, /* RGIDR_MODID[70]:CPG3 */ + [67] = {0xFDA02110U, 0x0000003FU}, /* RGIDR_MODID[71]:PFC00 */ + [68] = {0xFDA02114U, 0x0000002AU}, /* RGIDR_MODID[72]:PFC01 */ + [69] = {0xFDA02118U, 0x0000000CU}, /* RGIDR_MODID[73]:PFC02 */ + [70] = {0xFDA0211CU, 0x0000000CU}, /* RGIDR_MODID[74]:PFC03 */ + [71] = {0xFDA02150U, 0x0000003FU}, /* RGIDR_MODID[75]:PFCS0 */ + [72] = {0xFDA02154U, 0x0000002AU}, /* RGIDR_MODID[76]:PFCS1 */ + [73] = {0xFDA02158U, 0x0000000CU}, /* RGIDR_MODID[77]:PFCS2 */ + [74] = {0xFDA0215CU, 0x0000000CU}, /* RGIDR_MODID[78]:PFCS3 */ + [75] = {0xFDA02160U, 0x0000003FU}, /* RGIDR_MODID[79]:RESET0 */ + [76] = {0xFDA02164U, 0x0000002AU}, /* RGIDR_MODID[80]:RESET1 */ + [77] = {0xFDA02168U, 0x0000000CU}, /* RGIDR_MODID[81]:RESET2 */ + [78] = {0xFDA0216CU, 0x0000000CU}, /* RGIDR_MODID[82]:RESET3 */ + [79] = {0xFDA02170U, 0x0000003FU}, /* RGIDR_MODID[83]:SYS0 */ + [80] = {0xFDA02174U, 0x0000002AU}, /* RGIDR_MODID[84]:SYS1 */ + [81] = {0xFDA02178U, 0x0000000CU}, /* RGIDR_MODID[85]:SYS2 */ + [82] = {0xFDA0217CU, 0x0000000CU}, /* RGIDR_MODID[86]:SYS3 */ + [83] = {0xFCB62000U, 0x0000002EU}, /* RGIDR_MODID[87]:DMAMSI0 */ + [84] = {0xFCB62004U, 0x0000002EU}, /* RGIDR_MODID[88]:DMAMSI1 */ + [85] = {0xFCB62008U, 0x0000002EU}, /* RGIDR_MODID[89]:DMAMSI2 */ + [86] = {0xFCB6200CU, 0x0000002EU}, /* RGIDR_MODID[90]:DMAMSI3 */ + [87] = {0xFCB62018U, 0x0000003BU}, /* RGIDR_MODID[91]:ECMSP3 */ + [88] = {0xFCB62024U, 0x0000003FU}, /* RGIDR_MODID[92]:ARSP30 */ + /* After setting */ /* RGIDR_MODID[93]:ARSP31 */ + /* After setting */ /* RGIDR_MODID[94]:ARSP32 */ + [89] = {0xFCB62030U, 0x0000003FU}, /* RGIDR_MODID[95]:ARSP33 */ + [90] = {0xFCB62034U, 0x0000003FU}, /* RGIDR_MODID[96]:ARSP34 */ + [91] = {0xFCB62038U, 0x0000003FU}, /* RGIDR_MODID[97]:ARSP35 */ + [92] = {0xFCB6203CU, 0x0000003FU}, /* RGIDR_MODID[98]:ARSP36 */ + [93] = {0xFCB62040U, 0x0000003FU}, /* RGIDR_MODID[99]:ARSP37 */ + [94] = {0xFCB62044U, 0x00000000U}, /* RGIDR_MODID[100]:ARSP38 */ + [95] = {0xFCB62048U, 0x0000002EU}, /* RGIDR_MODID[101]:MSI0 */ + [96] = {0xFCB6204CU, 0x0000002EU}, /* RGIDR_MODID[102]:MSI1 */ + [97] = {0xFCB62050U, 0x0000002EU}, /* RGIDR_MODID[103]:MSI2 */ + [98] = {0xFCB62054U, 0x0000002EU}, /* RGIDR_MODID[104]:MSI3 */ + [99] = {0xFCB92000U, 0x0000003FU}, /* RGIDR_MODID[105]:ARSP40 */ + /* After setting */ /* RGIDR_MODID[106]:ARSP41 */ + /* After setting */ /* RGIDR_MODID[107]:ARSP42 */ + [100] = {0xFCB9200CU, 0x0000003FU}, /* RGIDR_MODID[108]:ARSP43 */ + [101] = {0xFCB92010U, 0x0000003FU}, /* RGIDR_MODID[109]:ARSP44 */ + [102] = {0xFCB92014U, 0x0000003FU}, /* RGIDR_MODID[110]:ARSP45 */ + [103] = {0xFCB92018U, 0x0000003FU}, /* RGIDR_MODID[111]:ARSP46 */ + [104] = {0xFCB9201CU, 0x0000003FU}, /* RGIDR_MODID[112]:ARSP47 */ + [105] = {0xFCB92020U, 0x00000000U}, /* RGIDR_MODID[113]:ARSP48 */ + [106] = {0xFCB92024U, 0x0000003FU}, /* RGIDR_MODID[114]:DMAHSCIF0 */ + [107] = {0xFCB92028U, 0x0000003FU}, /* RGIDR_MODID[115]:DMAHSCIF1 */ + [108] = {0xFCB9202CU, 0x0000003FU}, /* RGIDR_MODID[116]:DMAHSCIF2 */ + [109] = {0xFCB92030U, 0x0000003FU}, /* RGIDR_MODID[117]:DMAHSCIF3 */ + [110] = {0xFCB92034U, 0x0000003FU}, /* RGIDR_MODID[118]:DMASCIF0 */ + [111] = {0xFCB92038U, 0x0000003FU}, /* RGIDR_MODID[119]:DMASCIF1 */ + [112] = {0xFCB9203CU, 0x0000003FU}, /* RGIDR_MODID[120]:DMASCIF3 */ + [113] = {0xFCB92040U, 0x0000003FU}, /* RGIDR_MODID[121]:DMASCIF4 */ + [114] = {0xFCB92044U, 0x0000003BU}, /* RGIDR_MODID[122]:ECMSP4 */ + [115] = {0xFCB92048U, 0x0000003FU}, /* RGIDR_MODID[123]:HSCIF0 */ + [116] = {0xFCB9204CU, 0x0000003FU}, /* RGIDR_MODID[124]:HSCIF1 */ + [117] = {0xFCB92050U, 0x0000003FU}, /* RGIDR_MODID[125]:HSCIF2 */ + [118] = {0xFCB92054U, 0x0000003FU}, /* RGIDR_MODID[126]:HSCIF3 */ + [119] = {0xFCB92058U, 0x0000003FU}, /* RGIDR_MODID[127]:SCIF0 */ + [120] = {0xFCB9205CU, 0x0000003FU}, /* RGIDR_MODID[128]:SCIF1 */ + [121] = {0xFCB92060U, 0x0000003FU}, /* RGIDR_MODID[129]:SCIF3 */ + [122] = {0xFCB92064U, 0x0000003FU}, /* RGIDR_MODID[130]:SCIF4 */ + [123] = {0xFCB92068U, 0x0000003FU}, /* RGIDR_MODID[131]:TMU1 */ + [124] = {0xFCB9206CU, 0x0000003FU}, /* RGIDR_MODID[132]:TMU2 */ + [125] = {0xFCB92070U, 0x0000003FU}, /* RGIDR_MODID[133]:TMU3 */ + [126] = {0xFCB92074U, 0x0000003FU}, /* RGIDR_MODID[134]:TMU4 */ + [127] = {0xFCF82000U, 0x0000002AU}, /* RGIDR_MODID[135]:CKMHSC */ + [128] = {0xFCF82004U, 0x0000000CU}, /* RGIDR_MODID[136]:AXIPCI001 */ + [129] = {0xFCF82008U, 0x0000000CU}, /* RGIDR_MODID[137]:AXIPCI002 */ + [130] = {0xFCF8200CU, 0x0000000CU}, /* RGIDR_MODID[138]:AXIPCI003 */ + [131] = {0xFCF82010U, 0x0000002EU}, /* RGIDR_MODID[139]:ETHPHY */ + [132] = {0xFCF82014U, 0x0000000CU}, /* RGIDR_MODID[140]:AXIPCI005 */ + [133] = {0xFCF82018U, 0x0000000CU}, /* RGIDR_MODID[141]:AXIPCI006 */ + [134] = {0xFCF8201CU, 0x0000000CU}, /* RGIDR_MODID[142]:AXIPCI007 */ + [135] = {0xFCF82020U, 0x0000000CU}, /* RGIDR_MODID[143]:AXIPCI008 */ + [136] = {0xFCF82024U, 0x0000000CU}, /* RGIDR_MODID[144]:AXIPCI009 */ + [137] = {0xFCF82028U, 0x0000000CU}, /* RGIDR_MODID[145]:AXIPCI010 */ + [138] = {0xFCF8202CU, 0x0000000CU}, /* RGIDR_MODID[146]:AXIPCI011 */ + [139] = {0xFCF82030U, 0x0000000CU}, /* RGIDR_MODID[147]:AXIPCI012 */ + [140] = {0xFCF82034U, 0x0000000CU}, /* RGIDR_MODID[148]:AXIPCI013 */ + [141] = {0xFCF82038U, 0x0000000CU}, /* RGIDR_MODID[149]:AXIPCI014 */ + [142] = {0xFCF8203CU, 0x0000000CU}, /* RGIDR_MODID[150]:AXIPCI015 */ + [143] = {0xFCF82040U, 0x0000000CU}, /* RGIDR_MODID[151]:AXIPCI100 */ + [144] = {0xFCF82044U, 0x0000000CU}, /* RGIDR_MODID[152]:AXIPCI101 */ + [145] = {0xFCF82048U, 0x0000000CU}, /* RGIDR_MODID[153]:AXIPCI102 */ + [146] = {0xFCF8204CU, 0x0000000CU}, /* RGIDR_MODID[154]:AXIPCI103 */ + [147] = {0xFCF82050U, 0x0000000CU}, /* RGIDR_MODID[155]:AXIPCI104 */ + [148] = {0xFCF82054U, 0x0000000CU}, /* RGIDR_MODID[156]:AXIPCI105 */ + [149] = {0xFCF82058U, 0x0000000CU}, /* RGIDR_MODID[157]:AXIPCI106 */ + [150] = {0xFCF8205CU, 0x0000000CU}, /* RGIDR_MODID[158]:AXIPCI107 */ + [151] = {0xFCF82060U, 0x0000000CU}, /* RGIDR_MODID[159]:AXIPCI108 */ + [152] = {0xFCF82064U, 0x0000000CU}, /* RGIDR_MODID[160]:AXIPCI109 */ + [153] = {0xFCF82068U, 0x0000000CU}, /* RGIDR_MODID[161]:AXIPCI110 */ + [154] = {0xFCF8206CU, 0x0000000CU}, /* RGIDR_MODID[162]:AXIPCI111 */ + [155] = {0xFCF82070U, 0x0000000CU}, /* RGIDR_MODID[163]:AXIPCI112 */ + [156] = {0xFCF82074U, 0x0000000CU}, /* RGIDR_MODID[164]:AXIPCI113 */ + [157] = {0xFCF82078U, 0x0000000CU}, /* RGIDR_MODID[165]:AXIPCI114 */ + [158] = {0xFCF8207CU, 0x0000000CU}, /* RGIDR_MODID[166]:AXIPCI115 */ + [159] = {0xFCF82080U, 0x0000002EU}, /* RGIDR_MODID[167]:ETHPHYRAM */ + [160] = {0xFCF82088U, 0x0000000CU}, /* RGIDR_MODID[168]:IPMMUHC00 */ + [161] = {0xFCF8208CU, 0x0000002EU}, /* RGIDR_MODID[169]:RSW200 */ + [162] = {0xFCF82090U, 0x0000002EU}, /* RGIDR_MODID[170]:RSW201 */ + [163] = {0xFCF82094U, 0x0000002EU}, /* RGIDR_MODID[171]:RSW210 */ + [164] = {0xFCF82098U, 0x0000002EU}, /* RGIDR_MODID[172]:RSW211 */ + [165] = {0xFCF8209CU, 0x0000002EU}, /* RGIDR_MODID[173]:RSW202 */ + [166] = {0xFCF820A0U, 0x0000002EU}, /* RGIDR_MODID[174]:RSW203 */ + [167] = {0xFCF820A4U, 0x0000002EU}, /* RGIDR_MODID[175]:RSW204 */ + [168] = {0xFCF820A8U, 0x0000002EU}, /* RGIDR_MODID[176]:RSW205 */ + [169] = {0xFCF820ACU, 0x0000002EU}, /* RGIDR_MODID[177]:RSW206 */ + [170] = {0xFCF820B0U, 0x0000002EU}, /* RGIDR_MODID[178]:RSW207 */ + [171] = {0xFCF820B4U, 0x0000002EU}, /* RGIDR_MODID[179]:RSW208 */ + [172] = {0xFCF820B8U, 0x0000002EU}, /* RGIDR_MODID[180]:RSW209 */ + [173] = {0xFCF820BCU, 0x0000002EU}, /* RGIDR_MODID[181]:RSW2RAM */ + [174] = {0xFCF820C0U, 0x0000002AU}, /* RGIDR_MODID[182]:RSW2SEC00 */ + [175] = {0xFCF820C4U, 0x0000002AU}, /* RGIDR_MODID[183]:RSW2SEC01 */ + [176] = {0xFCF820C8U, 0x0000002AU}, /* RGIDR_MODID[184]:RSW2SEC10 */ + [177] = {0xFCF820CCU, 0x0000002AU}, /* RGIDR_MODID[185]:RSW2SEC11 */ + [178] = {0xFCF820D0U, 0x0000002AU}, /* RGIDR_MODID[186]:RSW2SEC02 */ + [179] = {0xFCF820D4U, 0x0000002AU}, /* RGIDR_MODID[187]:RSW2SEC03 */ + [180] = {0xFCF820D8U, 0x0000002AU}, /* RGIDR_MODID[188]:RSW2SEC04 */ + [181] = {0xFCF820DCU, 0x0000002AU}, /* RGIDR_MODID[189]:RSW2SEC05 */ + [182] = {0xFCF820E0U, 0x0000002AU}, /* RGIDR_MODID[190]:RSW2SEC06 */ + [183] = {0xFCF820E4U, 0x0000002AU}, /* RGIDR_MODID[191]:RSW2SEC07 */ + [184] = {0xFCF820E8U, 0x0000002AU}, /* RGIDR_MODID[192]:RSW2SEC08 */ + [185] = {0xFCF820ECU, 0x0000002AU}, /* RGIDR_MODID[193]:RSW2SEC09 */ + [186] = {0xFCF820F4U, 0x0000000CU}, /* RGIDR_MODID[194]:AXIPCI000 */ + [187] = {0xFCF820F8U, 0x0000000CU}, /* RGIDR_MODID[195]:AXIPCI004 */ + [188] = {0xFCF820FCU, 0x0000000CU}, /* RGIDR_MODID[196]:IPMMUHC01 */ + [189] = {0xFCF8210CU, 0x0000000CU}, /* RGIDR_MODID[197]:IPMMUHC10 */ + [190] = {0xFCF82110U, 0x0000000CU}, /* RGIDR_MODID[198]:IPMMUHC11 */ + [191] = {0xFCF82114U, 0x0000000CU}, /* RGIDR_MODID[199]:IPMMUHC12 */ + [192] = {0xFCF82118U, 0x0000000CU}, /* RGIDR_MODID[200]:IPMMUHC13 */ + [193] = {0xFCF8211CU, 0x0000000CU}, /* RGIDR_MODID[201]:PPHY0 */ + [194] = {0xFCF82120U, 0x0000000CU}, /* RGIDR_MODID[202]:PPHY1 */ + [195] = {0xFCF82124U, 0x0000000CU}, /* RGIDR_MODID[203]:IPMMUHC14 */ + [196] = {0xFCF82128U, 0x0000000CU}, /* RGIDR_MODID[204]:IPMMUHC15 */ + [197] = {0xFCF8212CU, 0x0000002EU}, /* RGIDR_MODID[205]:FBAHSC */ + [198] = {0xFCF82130U, 0x0000000CU}, /* RGIDR_MODID[206]:IPMMUHC02 */ + [199] = {0xFCF82134U, 0x0000003FU}, /* RGIDR_MODID[207]:AXIUFSS */ + [200] = {0xFCF82138U, 0x0000003BU}, /* RGIDR_MODID[208]:ECMHSC */ + [201] = {0xFCF8213CU, 0x0000003FU}, /* RGIDR_MODID[209]:ARHC0 */ + /* After setting */ /* RGIDR_MODID[210]:ARHC1 */ + /* After setting */ /* RGIDR_MODID[211]:ARHC2 */ + [202] = {0xFCF82148U, 0x0000003FU}, /* RGIDR_MODID[212]:ARHC3 */ + [203] = {0xFCF8214CU, 0x0000003FU}, /* RGIDR_MODID[213]:ARHC4 */ + [204] = {0xFCF82150U, 0x0000003FU}, /* RGIDR_MODID[214]:ARHC5 */ + [205] = {0xFCF82154U, 0x0000003FU}, /* RGIDR_MODID[215]:ARHC6 */ + [206] = {0xFCF82158U, 0x0000003FU}, /* RGIDR_MODID[216]:ARHC7 */ + [207] = {0xFCF8215CU, 0x00000000U}, /* RGIDR_MODID[217]:ARHC8 */ + [208] = {0xFCF82160U, 0x0000000CU}, /* RGIDR_MODID[218]:IPMMUHC03 */ + [209] = {0xFCF82164U, 0x0000000CU}, /* RGIDR_MODID[219]:IPMMUHC04 */ + [210] = {0xFCF82168U, 0x0000000CU}, /* RGIDR_MODID[220]:IPMMUHC05 */ + [211] = {0xFCF8216CU, 0x0000000CU}, /* RGIDR_MODID[221]:IPMMUHC06 */ + [212] = {0xFCF82170U, 0x0000000CU}, /* RGIDR_MODID[222]:IPMMUHC07 */ + [213] = {0xFCF82174U, 0x0000000CU}, /* RGIDR_MODID[223]:IPMMUHC08 */ + [214] = {0xFCF82178U, 0x0000000CU}, /* RGIDR_MODID[224]:IPMMUHC09 */ + [215] = {0xFDC22000U, 0x0000003FU}, /* RGIDR_MODID[225]:ARRC0 */ + /* After setting */ /* RGIDR_MODID[226]:ARRC1 */ + /* After setting */ /* RGIDR_MODID[227]:ARRC2 */ + [216] = {0xFDC2200CU, 0x0000003FU}, /* RGIDR_MODID[228]:ARRC3 */ + [217] = {0xFDC22010U, 0x0000003FU}, /* RGIDR_MODID[229]:ARRC4 */ + [218] = {0xFDC22014U, 0x0000003FU}, /* RGIDR_MODID[230]:ARRC5 */ + [219] = {0xFDC22018U, 0x0000003FU}, /* RGIDR_MODID[231]:ARRC6 */ + [220] = {0xFDC2201CU, 0x0000003FU}, /* RGIDR_MODID[232]:ARRC7 */ + [221] = {0xFDC22020U, 0x00000000U}, /* RGIDR_MODID[233]:ARRC8 */ + [222] = {0xFDC22024U, 0x00000019U}, /* RGIDR_MODID[234]:CR0 */ + [223] = {0xFDC22028U, 0x0000003FU}, /* RGIDR_MODID[235]:ICUMX */ + [224] = {0xFDC2202CU, 0x0000003BU}, /* RGIDR_MODID[236]:ECMRC */ + [225] = {0xFD432000U, 0x0000002EU}, /* RGIDR_MODID[237]:DMAWCRC0 */ + [226] = {0xFD432004U, 0x0000002EU}, /* RGIDR_MODID[238]:DMAWCRC1 */ + [227] = {0xFD432008U, 0x0000002EU}, /* RGIDR_MODID[239]:DMAWCRC2 */ + [228] = {0xFD43200CU, 0x0000002EU}, /* RGIDR_MODID[240]:DMAWCRC3 */ + [229] = {0xFD432010U, 0x0000000CU}, /* RGIDR_MODID[241]:DMATSIP0 */ + [230] = {0xFD432014U, 0x0000000CU}, /* RGIDR_MODID[242]:DMATSIP1 */ + [231] = {0xFD432018U, 0x0000000CU}, /* RGIDR_MODID[243]:DMATSIP2 */ + [232] = {0xFD442000U, 0x0000003FU}, /* RGIDR_MODID[244]:ARMREG00 */ + [233] = {0xFD442004U, 0x0000000CU}, /* RGIDR_MODID[245]:ARMREG01 */ + [234] = {0xFD442008U, 0x00000000U}, /* RGIDR_MODID[246]:ARMREG10 */ + [235] = {0xFD44200CU, 0x00000000U}, /* RGIDR_MODID[247]:ARMREG11 */ + [236] = {0xFD442010U, 0x0000002AU}, /* RGIDR_MODID[248]:ARMREG12 */ + [237] = {0xFD442014U, 0x0000003FU}, /* RGIDR_MODID[249]:ARMREG13 */ + [238] = {0xFD442018U, 0x0000002AU}, /* RGIDR_MODID[250]:ARMREG14 */ + [239] = {0xFD44201CU, 0x00000022U}, /* RGIDR_MODID[251]:AXICR52SS */ + [240] = {0xFD442020U, 0x0000002EU}, /* RGIDR_MODID[252]:AXICSD0 */ + [241] = {0xFD442024U, 0x0000002EU}, /* RGIDR_MODID[253]:AXIINTAP0 */ + [242] = {0xFD442028U, 0x0000002EU}, /* RGIDR_MODID[254]:AXIINTAP1 */ + [243] = {0xFD44202CU, 0x00000019U}, /* RGIDR_MODID[255]:AXISECROM */ + [244] = {0xFD442030U, 0x0000003FU}, /* RGIDR_MODID[256]:AXISYSRAM0 */ + [245] = {0xFD442034U, 0x0000003FU}, /* RGIDR_MODID[257]:AXISYSRAM1 */ + [246] = {0xFD442038U, 0x00000000U}, /* RGIDR_MODID[258]:ARGREG15 */ + [247] = {0xFD44203CU, 0x00000000U}, /* RGIDR_MODID[259]:ARMREG2 */ + [248] = {0xFD442040U, 0x00000000U}, /* RGIDR_MODID[260]:ARMREG3 */ + [249] = {0xFD442044U, 0x00000000U}, /* RGIDR_MODID[261]:ARMREG4 */ + [250] = {0xFD442048U, 0x0000003FU}, /* RGIDR_MODID[262]:ARMREG5 */ + [251] = {0xFD44204CU, 0x0000002AU}, /* RGIDR_MODID[263]:ARMREG6 */ + [252] = {0xFD442050U, 0x00000000U}, /* RGIDR_MODID[264]:ARMREG7 */ + [253] = {0xFD442054U, 0x0000000CU}, /* RGIDR_MODID[265]:ARMREG8 */ + [254] = {0xFD442058U, 0x0000000CU}, /* RGIDR_MODID[266]:ARMREG9 */ + [255] = {0xFD44205CU, 0x0000003FU}, /* RGIDR_MODID[267]:ARRD0 */ + /* After setting */ /* RGIDR_MODID[268]:ARRD1 */ + /* After setting */ /* RGIDR_MODID[269]:ARRD2 */ + [256] = {0xFD442068U, 0x0000003FU}, /* RGIDR_MODID[270]:ARRD3 */ + [257] = {0xFD44206CU, 0x0000003FU}, /* RGIDR_MODID[271]:ARRD4 */ + [258] = {0xFD442070U, 0x0000003FU}, /* RGIDR_MODID[272]:ARRD5 */ + [259] = {0xFD442074U, 0x0000003FU}, /* RGIDR_MODID[273]:ARRD6 */ + [260] = {0xFD442078U, 0x0000003FU}, /* RGIDR_MODID[274]:ARRD7 */ + [261] = {0xFD44207CU, 0x00000000U}, /* RGIDR_MODID[275]:ARRD8 */ + [262] = {0xFD442080U, 0x0000003FU}, /* RGIDR_MODID[276]:ARRT0 */ + /* After setting */ /* RGIDR_MODID[277]:ARRT1 */ + /* After setting */ /* RGIDR_MODID[278]:ARRT2 */ + [263] = {0xFD44208CU, 0x0000003FU}, /* RGIDR_MODID[279]:ARRT3 */ + [264] = {0xFD442090U, 0x0000003FU}, /* RGIDR_MODID[280]:ARRT4 */ + [265] = {0xFD442094U, 0x0000003FU}, /* RGIDR_MODID[281]:ARRT5 */ + [266] = {0xFD442098U, 0x0000003FU}, /* RGIDR_MODID[282]:ARRT6 */ + [267] = {0xFD44209CU, 0x0000003FU}, /* RGIDR_MODID[283]:ARRT7 */ + [268] = {0xFD4420A0U, 0x00000000U}, /* RGIDR_MODID[284]:ARRT8 */ + [269] = {0xFD4420A4U, 0x0000002AU}, /* RGIDR_MODID[285]:CKMRT */ + [270] = {0xFD4420A8U, 0x0000002EU}, /* RGIDR_MODID[286]:CRC0 */ + [271] = {0xFD4420ACU, 0x0000002EU}, /* RGIDR_MODID[287]:CRC1 */ + [272] = {0xFD4420B0U, 0x0000002EU}, /* RGIDR_MODID[288]:CRC2 */ + [273] = {0xFD4420B4U, 0x0000002EU}, /* RGIDR_MODID[289]:CRC3 */ + [274] = {0xFD4420B8U, 0x0000002EU}, /* RGIDR_MODID[290]:CSD */ + [275] = {0xFD4420BCU, 0x0000003BU}, /* RGIDR_MODID[291]:ECM */ + [276] = {0xFD4420C0U, 0x0000003BU}, /* RGIDR_MODID[292]:ECMRT */ + [277] = {0xFD4420C4U, 0x0000002EU}, /* RGIDR_MODID[293]:FBACR52 */ + [278] = {0xFD4420C8U, 0x0000002EU}, /* RGIDR_MODID[294]:FBART */ + [279] = {0xFD4420CCU, 0x0000002EU}, /* RGIDR_MODID[295]:INTTP */ + [280] = {0xFD4420D0U, 0x0000000CU}, /* RGIDR_MODID[296]:IPMMURT000 */ + [281] = {0xFD4420D4U, 0x0000000CU}, /* RGIDR_MODID[297]:IPMMURT100 */ + [282] = {0xFD4420D8U, 0x0000002EU}, /* RGIDR_MODID[298]:KCRC4 */ + [283] = {0xFD4420DCU, 0x0000002EU}, /* RGIDR_MODID[299]:KCRC5 */ + [284] = {0xFD4420E0U, 0x0000002EU}, /* RGIDR_MODID[300]:KCRC6 */ + [285] = {0xFD4420E4U, 0x0000002EU}, /* RGIDR_MODID[301]:KCRC7 */ + [286] = {0xFD4420E8U, 0x0000003FU}, /* RGIDR_MODID[302]:MFI00 */ + [287] = {0xFD4420ECU, 0x0000002EU}, /* RGIDR_MODID[303]:MFI01 */ + [288] = {0xFD4420F0U, 0x0000002EU}, /* RGIDR_MODID[304]:MFI10 */ + [289] = {0xFD4420F4U, 0x0000002EU}, /* RGIDR_MODID[305]:MFI02 */ + [290] = {0xFD4420F8U, 0x0000002EU}, /* RGIDR_MODID[306]:MFI03 */ + [291] = {0xFD4420FCU, 0x0000002EU}, /* RGIDR_MODID[307]:MFI04 */ + [292] = {0xFD442100U, 0x00000000U}, /* RGIDR_MODID[308]:MFI05 */ + [293] = {0xFD442104U, 0x00000000U}, /* RGIDR_MODID[309]:MFI06 */ + [294] = {0xFD442108U, 0x00000000U}, /* RGIDR_MODID[310]:MFI07 */ + [295] = {0xFD44210CU, 0x00000000U}, /* RGIDR_MODID[311]:MFI08 */ + [296] = {0xFD442110U, 0x0000002EU}, /* RGIDR_MODID[312]:MFI09 */ + [297] = {0xFD442114U, 0x0000003FU}, /* RGIDR_MODID[313]:MFI15 */ + [298] = {0xFD442118U, 0x0000002AU}, /* RGIDR_MODID[314]:CKMCR52 */ + [299] = {0xFD44211CU, 0x0000003BU}, /* RGIDR_MODID[315]:RTDM0P */ + [300] = {0xFD442120U, 0x0000003BU}, /* RGIDR_MODID[316]:ECMRD */ + [301] = {0xFD442124U, 0x0000003BU}, /* RGIDR_MODID[317]:RTDM1P */ + [302] = {0xFD44212CU, 0x0000003BU}, /* RGIDR_MODID[318]:RTDM2P */ + [303] = {0xFD442130U, 0x0000003BU}, /* RGIDR_MODID[319]:SYSRAM10 */ + [304] = {0xFD442134U, 0x0000003BU}, /* RGIDR_MODID[320]:RTDM3P */ + [305] = {0xFD442138U, 0x00000003U}, /* RGIDR_MODID[321]:SYSRAM00 */ + [306] = {0xFD44213CU, 0x0000002EU}, /* RGIDR_MODID[322]:TSIPL0 */ + [307] = {0xFD442140U, 0x0000002EU}, /* RGIDR_MODID[323]:TSIPL1 */ + [308] = {0xFD442144U, 0x0000002EU}, /* RGIDR_MODID[324]:TSIPL2 */ + [309] = {0xFD442148U, 0x0000002EU}, /* RGIDR_MODID[325]:TSIPL3 */ + [310] = {0xFD44214CU, 0x0000002EU}, /* RGIDR_MODID[326]:TSIPL4 */ + [311] = {0xFD442150U, 0x0000002EU}, /* RGIDR_MODID[327]:TSIPL5 */ + [312] = {0xFD442154U, 0x0000002EU}, /* RGIDR_MODID[328]:TSIPL6 */ + [313] = {0xFD442158U, 0x0000002EU}, /* RGIDR_MODID[329]:TSIPL7 */ + [314] = {0xFD44215CU, 0x0000002EU}, /* RGIDR_MODID[330]:WCRC0 */ + [315] = {0xFD442160U, 0x0000002EU}, /* RGIDR_MODID[331]:WCRC1 */ + [316] = {0xFD442164U, 0x0000002EU}, /* RGIDR_MODID[332]:WCRC2 */ + [317] = {0xFD442168U, 0x0000002EU}, /* RGIDR_MODID[333]:WCRC3 */ + [318] = {0xFD442174U, 0x0000000CU}, /* RGIDR_MODID[334]:TSIP0 */ + [319] = {0xFD442178U, 0x0000000CU}, /* RGIDR_MODID[335]:TSIP1 */ + [320] = {0xFD44217CU, 0x0000000CU}, /* RGIDR_MODID[336]:TSIP2 */ + [321] = {0xFD442180U, 0x0000002EU}, /* RGIDR_MODID[337]:MFI11 */ + [322] = {0xFD442184U, 0x00000000U}, /* RGIDR_MODID[338]:MFI12 */ + [323] = {0xFD442188U, 0x00000000U}, /* RGIDR_MODID[339]:MFI13 */ + [324] = {0xFD44218CU, 0x00000000U}, /* RGIDR_MODID[340]:MFI14 */ + [325] = {0xFD442190U, 0x0000000CU}, /* RGIDR_MODID[341]:IPMMURT001 */ + [326] = {0xFD442194U, 0x0000000CU}, /* RGIDR_MODID[342]:IPMMURT010 */ + [327] = {0xFD442198U, 0x0000000CU}, /* RGIDR_MODID[343]:IPMMURT011 */ + [328] = {0xFD44219CU, 0x0000000CU}, /* RGIDR_MODID[344]:IPMMURT012 */ + [329] = {0xFD4421A0U, 0x0000000CU}, /* RGIDR_MODID[345]:IPMMURT013 */ + [330] = {0xFD4421A4U, 0x0000000CU}, /* RGIDR_MODID[346]:IPMMURT014 */ + [331] = {0xFD4421A8U, 0x0000000CU}, /* RGIDR_MODID[347]:IPMMURT015 */ + [332] = {0xFD4421ACU, 0x0000000CU}, /* RGIDR_MODID[348]:IPMMURT002 */ + [333] = {0xFD4421B0U, 0x0000000CU}, /* RGIDR_MODID[349]:IPMMURT003 */ + [334] = {0xFD4421B4U, 0x0000000CU}, /* RGIDR_MODID[350]:IPMMURT004 */ + [335] = {0xFD4421B8U, 0x0000000CU}, /* RGIDR_MODID[351]:IPMMURT005 */ + [336] = {0xFD4421BCU, 0x0000000CU}, /* RGIDR_MODID[352]:IPMMURT006 */ + [337] = {0xFD4421C0U, 0x0000000CU}, /* RGIDR_MODID[353]:IPMMURT007 */ + [338] = {0xFD4421C4U, 0x0000000CU}, /* RGIDR_MODID[354]:IPMMURT008 */ + [339] = {0xFD4421C8U, 0x0000000CU}, /* RGIDR_MODID[355]:IPMMURT009 */ + [340] = {0xFD4421CCU, 0x0000000CU}, /* RGIDR_MODID[356]:IPMMURT101 */ + [341] = {0xFD4421D0U, 0x0000000CU}, /* RGIDR_MODID[357]:IPMMURT110 */ + [342] = {0xFD4421D4U, 0x0000000CU}, /* RGIDR_MODID[358]:IPMMURT111 */ + [343] = {0xFD4421D8U, 0x0000000CU}, /* RGIDR_MODID[359]:IPMMURT112 */ + [344] = {0xFD4421DCU, 0x0000000CU}, /* RGIDR_MODID[360]:IPMMURT113 */ + [345] = {0xFD4421E0U, 0x0000000CU}, /* RGIDR_MODID[361]:IPMMURT114 */ + [346] = {0xFD4421E4U, 0x0000000CU}, /* RGIDR_MODID[362]:IPMMURT115 */ + [347] = {0xFD4421E8U, 0x0000000CU}, /* RGIDR_MODID[363]:IPMMURT102 */ + [348] = {0xFD4421ECU, 0x0000000CU}, /* RGIDR_MODID[364]:IPMMURT103 */ + [349] = {0xFD4421F0U, 0x0000000CU}, /* RGIDR_MODID[365]:IPMMURT104 */ + [350] = {0xFD4421F4U, 0x0000000CU}, /* RGIDR_MODID[366]:IPMMURT105 */ + [351] = {0xFD4421F8U, 0x0000000CU}, /* RGIDR_MODID[367]:IPMMURT106 */ + [352] = {0xFD4421FCU, 0x0000000CU}, /* RGIDR_MODID[368]:IPMMURT107 */ + [353] = {0xFD442200U, 0x0000003BU}, /* RGIDR_MODID[369]:RTDM000 */ + [354] = {0xFD442204U, 0x0000003BU}, /* RGIDR_MODID[370]:RTDM001 */ + [355] = {0xFD442208U, 0x0000003BU}, /* RGIDR_MODID[371]:RTDM010 */ + [356] = {0xFD44220CU, 0x0000003BU}, /* RGIDR_MODID[372]:RTDM011 */ + [357] = {0xFD442210U, 0x0000003BU}, /* RGIDR_MODID[373]:RTDM012 */ + [358] = {0xFD442214U, 0x0000003BU}, /* RGIDR_MODID[374]:RTDM013 */ + [359] = {0xFD442218U, 0x0000003BU}, /* RGIDR_MODID[375]:RTDM014 */ + [360] = {0xFD44221CU, 0x0000003BU}, /* RGIDR_MODID[376]:RTDM015 */ + [361] = {0xFD442220U, 0x0000003BU}, /* RGIDR_MODID[377]:RTDM002 */ + [362] = {0xFD442224U, 0x0000003BU}, /* RGIDR_MODID[378]:RTDM003 */ + [363] = {0xFD442228U, 0x0000003BU}, /* RGIDR_MODID[379]:RTDM004 */ + [364] = {0xFD44222CU, 0x0000003BU}, /* RGIDR_MODID[380]:RTDM005 */ + [365] = {0xFD442230U, 0x0000003BU}, /* RGIDR_MODID[381]:RTDM006 */ + [366] = {0xFD442234U, 0x0000003BU}, /* RGIDR_MODID[382]:RTDM007 */ + [367] = {0xFD442238U, 0x0000003BU}, /* RGIDR_MODID[383]:RTDM008 */ + [368] = {0xFD44223CU, 0x0000003BU}, /* RGIDR_MODID[384]:RTDM009 */ + [369] = {0xFD442240U, 0x0000003BU}, /* RGIDR_MODID[385]:RTDM100 */ + [370] = {0xFD442244U, 0x0000003BU}, /* RGIDR_MODID[386]:RTDM101 */ + [371] = {0xFD442248U, 0x0000003BU}, /* RGIDR_MODID[387]:RTDM110 */ + [372] = {0xFD44224CU, 0x0000003BU}, /* RGIDR_MODID[388]:RTDM111 */ + [373] = {0xFD442250U, 0x0000003BU}, /* RGIDR_MODID[389]:RTDM112 */ + [374] = {0xFD442254U, 0x0000003BU}, /* RGIDR_MODID[390]:RTDM113 */ + [375] = {0xFD442258U, 0x0000003BU}, /* RGIDR_MODID[391]:RTDM114 */ + [376] = {0xFD44225CU, 0x0000003BU}, /* RGIDR_MODID[392]:RTDM115 */ + [377] = {0xFD442260U, 0x0000003BU}, /* RGIDR_MODID[393]:RTDM102 */ + [378] = {0xFD442264U, 0x0000003BU}, /* RGIDR_MODID[394]:RTDM103 */ + [379] = {0xFD442268U, 0x0000003BU}, /* RGIDR_MODID[395]:RTDM104 */ + [380] = {0xFD44226CU, 0x0000003BU}, /* RGIDR_MODID[396]:RTDM105 */ + [381] = {0xFD442270U, 0x0000003BU}, /* RGIDR_MODID[397]:RTDM106 */ + [382] = {0xFD442274U, 0x0000003BU}, /* RGIDR_MODID[398]:RTDM107 */ + [383] = {0xFD442278U, 0x0000003BU}, /* RGIDR_MODID[399]:RTDM108 */ + [384] = {0xFD44227CU, 0x0000003BU}, /* RGIDR_MODID[400]:RTDM109 */ + [385] = {0xFD442280U, 0x0000003BU}, /* RGIDR_MODID[401]:RTDM200 */ + [386] = {0xFD442284U, 0x0000003BU}, /* RGIDR_MODID[402]:RTDM201 */ + [387] = {0xFD442288U, 0x0000003BU}, /* RGIDR_MODID[403]:RTDM210 */ + [388] = {0xFD44228CU, 0x0000003BU}, /* RGIDR_MODID[404]:RTDM211 */ + [389] = {0xFD442290U, 0x0000003BU}, /* RGIDR_MODID[405]:RTDM212 */ + [390] = {0xFD442294U, 0x0000003BU}, /* RGIDR_MODID[406]:RTDM213 */ + [391] = {0xFD442298U, 0x0000003BU}, /* RGIDR_MODID[407]:RTDM214 */ + [392] = {0xFD44229CU, 0x0000003BU}, /* RGIDR_MODID[408]:RTDM215 */ + [393] = {0xFD4422A0U, 0x0000003BU}, /* RGIDR_MODID[409]:RTDM202 */ + [394] = {0xFD4422A4U, 0x0000003BU}, /* RGIDR_MODID[410]:RTDM203 */ + [395] = {0xFD4422A8U, 0x0000003BU}, /* RGIDR_MODID[411]:RTDM204 */ + [396] = {0xFD4422ACU, 0x0000003BU}, /* RGIDR_MODID[412]:RTDM205 */ + [397] = {0xFD4422B0U, 0x0000003BU}, /* RGIDR_MODID[413]:RTDM206 */ + [398] = {0xFD4422B4U, 0x0000003BU}, /* RGIDR_MODID[414]:RTDM207 */ + [399] = {0xFD4422B8U, 0x0000003BU}, /* RGIDR_MODID[415]:RTDM208 */ + [400] = {0xFD4422BCU, 0x0000003BU}, /* RGIDR_MODID[416]:RTDM209 */ + [401] = {0xFD4422C0U, 0x0000003BU}, /* RGIDR_MODID[417]:RTDM300 */ + [402] = {0xFD4422C4U, 0x0000003BU}, /* RGIDR_MODID[418]:RTDM301 */ + [403] = {0xFD4422C8U, 0x0000003BU}, /* RGIDR_MODID[419]:RTDM310 */ + [404] = {0xFD4422CCU, 0x0000003BU}, /* RGIDR_MODID[420]:RTDM311 */ + [405] = {0xFD4422D0U, 0x0000003BU}, /* RGIDR_MODID[421]:RTDM312 */ + [406] = {0xFD4422D4U, 0x0000003BU}, /* RGIDR_MODID[422]:RTDM313 */ + [407] = {0xFD4422D8U, 0x0000003BU}, /* RGIDR_MODID[423]:RTDM314 */ + [408] = {0xFD4422DCU, 0x0000003BU}, /* RGIDR_MODID[424]:RTDM315 */ + [409] = {0xFD4422E0U, 0x0000003BU}, /* RGIDR_MODID[425]:RTDM302 */ + [410] = {0xFD4422E4U, 0x0000003BU}, /* RGIDR_MODID[426]:RTDM303 */ + [411] = {0xFD4422E8U, 0x0000003BU}, /* RGIDR_MODID[427]:RTDM304 */ + [412] = {0xFD4422ECU, 0x0000003BU}, /* RGIDR_MODID[428]:RTDM305 */ + [413] = {0xFD4422F0U, 0x0000003BU}, /* RGIDR_MODID[429]:RTDM306 */ + [414] = {0xFD4422F4U, 0x0000003BU}, /* RGIDR_MODID[430]:RTDM307 */ + [415] = {0xFD4422F8U, 0x0000003BU}, /* RGIDR_MODID[431]:RTDM308 */ + [416] = {0xFD4422FCU, 0x0000003BU}, /* RGIDR_MODID[432]:RTDM309 */ + [417] = {0xFD442300U, 0x0000000CU}, /* RGIDR_MODID[433]:IPMMURT108 */ + [418] = {0xFD442304U, 0x0000000CU}, /* RGIDR_MODID[434]:IPMMURT109 */ + [419] = {0xFD442308U, 0x00000011U}, /* RGIDR_MODID[435]:SYSRAM01 */ + [420] = {0xFD44230CU, 0x0000003BU}, /* RGIDR_MODID[436]:SYSRAM02 */ + [421] = {0xFD442310U, 0x00000011U}, /* RGIDR_MODID[437]:SYSRAM03 */ + [422] = {0xFD442314U, 0x00000011U}, /* RGIDR_MODID[438]:SYSRAM04 */ + [423] = {0xFD442318U, 0x00000011U}, /* RGIDR_MODID[439]:SYSRAM05 */ + [424] = {0xFD44231CU, 0x00000011U}, /* RGIDR_MODID[440]:SYSRAM06 */ + [425] = {0xFD442320U, 0x00000000U}, /* RGIDR_MODID[441]:SYSRAM07 */ + [426] = {0xFD442324U, 0x0000003BU}, /* RGIDR_MODID[442]:SYSRAM11 */ + [427] = {0xFD442328U, 0x0000003BU}, /* RGIDR_MODID[443]:SYSRAM12 */ + [428] = {0xFD44232CU, 0x0000003BU}, /* RGIDR_MODID[444]:SYSRAM13 */ + [429] = {0xFD442330U, 0x0000003BU}, /* RGIDR_MODID[445]:SYSRAM14 */ + [430] = {0xFD442334U, 0x0000003BU}, /* RGIDR_MODID[446]:SYSRAM15 */ + [431] = {0xFD442338U, 0x0000003BU}, /* RGIDR_MODID[447]:SYSRAM16 */ + [432] = {0xFD44233CU, 0x00000000U}, /* RGIDR_MODID[448]:SYSRAM17 */ + [433] = {0xFD442360U, 0x00000022U}, /* RGIDR_MODID[449]:BKBUF */ + [434] = {0xFD44236CU, 0x0000003FU}, /* RGIDR_MODID[450]:MCU */ + [435] = {0xFF862000U, 0x0000003FU}, /* RGIDR_MODID[451]:ARSC0 */ + /* After setting */ /* RGIDR_MODID[452]:ARSC1 */ + /* After setting */ /* RGIDR_MODID[453]:ARSC2 */ + [436] = {0xFF86200CU, 0x0000003FU}, /* RGIDR_MODID[454]:ARSC3 */ + [437] = {0xFF862010U, 0x0000003FU}, /* RGIDR_MODID[455]:ARSC4 */ + [438] = {0xFF862014U, 0x0000003FU}, /* RGIDR_MODID[456]:ARSC5 */ + [439] = {0xFF862018U, 0x0000003FU}, /* RGIDR_MODID[457]:ARSC6 */ + [440] = {0xFF86201CU, 0x0000003FU}, /* RGIDR_MODID[458]:ARSC7 */ + [441] = {0xFF862020U, 0x00000000U}, /* RGIDR_MODID[459]:ARSC8 */ + [442] = {0xFF862024U, 0x0000003FU}, /* RGIDR_MODID[460]:ARSTM0 */ + /* After setting */ /* RGIDR_MODID[461]:ARSTM1 */ + [443] = {0xFF862030U, 0x0000002EU}, /* RGIDR_MODID[462]:AXIFBABUSTOP0 */ + [444] = {0xFF862034U, 0x0000002EU}, /* RGIDR_MODID[463]:AXIFBABUSTOP1 */ + /* After setting */ /* RGIDR_MODID[464]:ARSTM2 */ + [445] = {0xFF86203CU, 0x0000003FU}, /* RGIDR_MODID[465]:ARSTM3 */ + [446] = {0xFF862040U, 0x0000003FU}, /* RGIDR_MODID[466]:ARSTM4 */ + [447] = {0xFF862044U, 0x0000003FU}, /* RGIDR_MODID[467]:ARSTM5 */ + [448] = {0xFF862048U, 0x0000003FU}, /* RGIDR_MODID[468]:ARSTM6 */ + [449] = {0xFF86204CU, 0x0000003FU}, /* RGIDR_MODID[469]:ARSTM7 */ + [450] = {0xFF862050U, 0x00000000U}, /* RGIDR_MODID[470]:ARSTM8 */ + [451] = {0xFF862054U, 0x0000003BU}, /* RGIDR_MODID[471]:ECMTOP */ + [452] = {0xFF862058U, 0x0000002EU}, /* RGIDR_MODID[472]:FBA */ + [453] = {0xFF86205CU, 0x0000002EU}, /* RGIDR_MODID[473]:FBC */ + [454] = {0xFF862060U, 0x0000000CU}, /* RGIDR_MODID[474]:AXICCI00 */ + [455] = {0xFF862064U, 0x0000000CU}, /* RGIDR_MODID[475]:AXICCI01 */ + [456] = {0xFF862068U, 0x0000000CU}, /* RGIDR_MODID[476]:AXICCI10 */ + [457] = {0xFF86206CU, 0x0000000CU}, /* RGIDR_MODID[477]:AXICCI11 */ + [458] = {0xFF862070U, 0x0000000CU}, /* RGIDR_MODID[478]:AXICCI12 */ + [459] = {0xFF862074U, 0x0000000CU}, /* RGIDR_MODID[479]:AXICCI13 */ + [460] = {0xFF862078U, 0x0000000CU}, /* RGIDR_MODID[480]:AXICCI14 */ + [461] = {0xFF86207CU, 0x0000000CU}, /* RGIDR_MODID[481]:AXICCI15 */ + [462] = {0xFF862080U, 0x0000000CU}, /* RGIDR_MODID[482]:AXICCI2 */ + [463] = {0xFF862084U, 0x0000000CU}, /* RGIDR_MODID[483]:AXICCI3 */ + [464] = {0xFF862088U, 0x0000000CU}, /* RGIDR_MODID[484]:AXICCI4 */ + [465] = {0xFF86208CU, 0x0000000CU}, /* RGIDR_MODID[485]:AXICCI5 */ + [466] = {0xFF862090U, 0x0000000CU}, /* RGIDR_MODID[486]:AXICCI6 */ + [467] = {0xFF862094U, 0x0000000CU}, /* RGIDR_MODID[487]:AXICCI7 */ + [468] = {0xFF862098U, 0x0000000CU}, /* RGIDR_MODID[488]:AXICCI8 */ + [469] = {0xFF86209CU, 0x0000003FU}, /* RGIDR_MODID[489]:AXICCI9 */ + [470] = {0xFF8620A0U, 0x0000003FU}, /* RGIDR_MODID[490]:ECMSTM */ + [471] = {0xFCB82014U, 0x0000002EU}, /* RGIDR_MODID[491]:DMAI2C0 */ + [472] = {0xFCB82018U, 0x0000002EU}, /* RGIDR_MODID[492]:DMAI2C1 */ + [473] = {0xFCB8201CU, 0x0000002EU}, /* RGIDR_MODID[493]:DMAI2C2 */ + [474] = {0xFCB82020U, 0x0000002EU}, /* RGIDR_MODID[494]:DMAI2C3 */ + [475] = {0xFCB82024U, 0x0000002EU}, /* RGIDR_MODID[495]:DMAI2C4 */ + [476] = {0xFCB82028U, 0x0000002EU}, /* RGIDR_MODID[496]:DMAI2C5 */ + [477] = {0xFDDC2000U, 0x00000000U}, /* RGIDR_MODID[497]:ARMM */ + /* After setting */ /* RGIDR_MODID[498]:AXIARNMM */ + [478] = {0xFDDC2008U, 0x0000003FU}, /* RGIDR_MODID[499]:ARSM0 */ + /* After setting */ /* RGIDR_MODID[500]:ARSM1 */ + /* After setting */ /* RGIDR_MODID[501]:ARSM2 */ + [479] = {0xFDDC2014U, 0x0000003FU}, /* RGIDR_MODID[502]:AXIQOS0 */ + [480] = {0xFDDC2018U, 0x0000003FU}, /* RGIDR_MODID[503]:AXIQOS1 */ + [481] = {0xFDDC201CU, 0x0000003FU}, /* RGIDR_MODID[504]:AXIQOS2 */ + [482] = {0xFDDC2020U, 0x0000003FU}, /* RGIDR_MODID[505]:AXIQOS3 */ + [483] = {0xFDDC2024U, 0x0000003FU}, /* RGIDR_MODID[506]:AXIQOS4 */ + [484] = {0xFDDC2030U, 0x0000003FU}, /* RGIDR_MODID[507]:AXIQOS5 */ + [485] = {0xFDDC2034U, 0x0000003FU}, /* RGIDR_MODID[508]:ARSM3 */ + [486] = {0xFDDC2038U, 0x0000003FU}, /* RGIDR_MODID[509]:ARSM4 */ + [487] = {0xFDDC203CU, 0x0000003FU}, /* RGIDR_MODID[510]:ARSM5 */ + [488] = {0xFDDC2040U, 0x0000003FU}, /* RGIDR_MODID[511]:ARSM6 */ + [489] = {0xFDDC2044U, 0x0000003FU}, /* RGIDR_MODID[512]:ARSM7 */ + [490] = {0xFDDC2048U, 0x00000000U}, /* RGIDR_MODID[513]:ARSM8 */ + [491] = {0xFDDC204CU, 0x0000003FU}, /* RGIDR_MODID[514]:AXMM0 */ + [492] = {0xFDDC2050U, 0x0000003FU}, /* RGIDR_MODID[515]:AXMM1 */ + [493] = {0xFDDC2054U, 0x00000000U}, /* RGIDR_MODID[516]:AXMMPMON */ + [494] = {0xFDDC2058U, 0x0000002AU}, /* RGIDR_MODID[517]:CKMMM */ + [495] = {0xFDDC205CU, 0x0000003BU}, /* RGIDR_MODID[518]:ECMMM */ + [496] = {0xFDDC2068U, 0x0000002EU}, /* RGIDR_MODID[519]:FBAMM */ + [497] = {0xFDDC206CU, 0x0000000CU}, /* RGIDR_MODID[520]:IPMMUMM00 */ + [498] = {0xFDDC2070U, 0x0000003FU}, /* RGIDR_MODID[521]:DBS00 */ + [499] = {0xFDDC2074U, 0x0000002AU}, /* RGIDR_MODID[522]:DBS01 */ + [500] = {0xFDDC2080U, 0x0000003FU}, /* RGIDR_MODID[523]:AXCIDBS */ + [501] = {0xFDDC209CU, 0x0000000CU}, /* RGIDR_MODID[524]:IPMMUMM01 */ + [502] = {0xFDDC20A0U, 0x0000000CU}, /* RGIDR_MODID[525]:IPMMUMM10 */ + [503] = {0xFDDC20A4U, 0x0000000CU}, /* RGIDR_MODID[526]:IPMMUMM11 */ + [504] = {0xFDDC20A8U, 0x0000000CU}, /* RGIDR_MODID[527]:IPMMUMM12 */ + [505] = {0xFDDC20ACU, 0x0000000CU}, /* RGIDR_MODID[528]:IPMMUMM13 */ + [506] = {0xFDDC20B0U, 0x0000000CU}, /* RGIDR_MODID[529]:IPMMUMM14 */ + [507] = {0xFDDC20B4U, 0x0000000CU}, /* RGIDR_MODID[530]:IPMMUMM15 */ + [508] = {0xFDDC20B8U, 0x0000000CU}, /* RGIDR_MODID[531]:IPMMUMM02 */ + [509] = {0xFDDC20BCU, 0x0000000CU}, /* RGIDR_MODID[532]:IPMMUMM03 */ + [510] = {0xFDDC20C0U, 0x0000000CU}, /* RGIDR_MODID[533]:IPMMUMM04 */ + [511] = {0xFDDC20C4U, 0x0000000CU}, /* RGIDR_MODID[534]:IPMMUMM05 */ + [512] = {0xFDDC20C8U, 0x0000000CU}, /* RGIDR_MODID[535]:IPMMUMM06 */ + [513] = {0xFDDC20CCU, 0x0000000CU}, /* RGIDR_MODID[536]:IPMMUMM07 */ + [514] = {0xFDDC20D0U, 0x0000000CU}, /* RGIDR_MODID[537]:IPMMUMM08 */ + [515] = {0xFDDC20D4U, 0x0000000CU}, /* RGIDR_MODID[538]:IPMMUMM09 */ + [516] = {0xFCB52000U, 0x0000003FU}, /* RGIDR_MODID[539]:ARSD00 */ + /* After setting */ /* RGIDR_MODID[540]:ARSD01 */ + /* After setting */ /* RGIDR_MODID[541]:ARSD02 */ + [517] = {0xFCB5200CU, 0x0000003FU}, /* RGIDR_MODID[542]:ARSD03 */ + [518] = {0xFCB52010U, 0x0000003FU}, /* RGIDR_MODID[543]:ARSD04 */ + [519] = {0xFCB52014U, 0x0000003FU}, /* RGIDR_MODID[544]:ARSD05 */ + [520] = {0xFCB52018U, 0x0000003FU}, /* RGIDR_MODID[545]:ARSD06 */ + [521] = {0xFCB52028U, 0x0000003FU}, /* RGIDR_MODID[546]:AXIRPC */ + [522] = {0xFCB5202CU, 0x0000003FU}, /* RGIDR_MODID[547]:AXISDHI0 */ + [523] = {0xFCB52030U, 0x0000003FU}, /* RGIDR_MODID[548]:ARSD07 */ + [524] = {0xFCB52034U, 0x00000000U}, /* RGIDR_MODID[549]:ARSD07 */ + [525] = {0xFCB52038U, 0x0000003FU}, /* RGIDR_MODID[550]:ARSP00 */ + /* After setting */ /* RGIDR_MODID[551]:ARSP01 */ + /* After setting */ /* RGIDR_MODID[552]:ARSP02 */ + [526] = {0xFCB52044U, 0x0000003FU}, /* RGIDR_MODID[553]:ARSP03 */ + [527] = {0xFCB52048U, 0x0000003FU}, /* RGIDR_MODID[554]:ARSP04 */ + [528] = {0xFCB5204CU, 0x0000003FU}, /* RGIDR_MODID[555]:ARSP05 */ + [529] = {0xFCB52050U, 0x0000003FU}, /* RGIDR_MODID[556]:ARSP06 */ + [530] = {0xFCB52054U, 0x00000022U}, /* RGIDR_MODID[557]:ARSP07 */ + [531] = {0xFCB52058U, 0x00000000U}, /* RGIDR_MODID[558]:ARSP08 */ + [532] = {0xFCB5205CU, 0x0000000CU}, /* RGIDR_MODID[559]:IPMMUDS001 */ + [533] = {0xFCB52060U, 0x0000002AU}, /* RGIDR_MODID[560]:CKMPER0 */ + [534] = {0xFCB52064U, 0x0000003BU}, /* RGIDR_MODID[561]:ECMPER0 */ + [535] = {0xFCB52068U, 0x0000002EU}, /* RGIDR_MODID[562]:FBAPER0 */ + [536] = {0xFCB5206CU, 0x0000002EU}, /* RGIDR_MODID[563]:FSO0 */ + [537] = {0xFCB52070U, 0x0000002EU}, /* RGIDR_MODID[564]:FSO1 */ + [538] = {0xFCB52074U, 0x0000002EU}, /* RGIDR_MODID[565]:FSO10 */ + [539] = {0xFCB52078U, 0x0000002EU}, /* RGIDR_MODID[566]:FSO2 */ + [540] = {0xFCB5207CU, 0x0000002EU}, /* RGIDR_MODID[567]:FSO3 */ + [541] = {0xFCB52080U, 0x0000002EU}, /* RGIDR_MODID[568]:FSO4 */ + [542] = {0xFCB52084U, 0x0000002EU}, /* RGIDR_MODID[569]:FSO5 */ + [543] = {0xFCB52088U, 0x0000002EU}, /* RGIDR_MODID[570]:FSO6 */ + [544] = {0xFCB5208CU, 0x0000002EU}, /* RGIDR_MODID[571]:FSO7 */ + [545] = {0xFCB52090U, 0x0000002EU}, /* RGIDR_MODID[572]:FSO8 */ + [546] = {0xFCB52094U, 0x0000002EU}, /* RGIDR_MODID[573]:FSO9 */ + [547] = {0xFCB5209CU, 0x0000003BU}, /* RGIDR_MODID[574]:ECMSD0 */ + [548] = {0xFCB520A0U, 0x0000000CU}, /* RGIDR_MODID[575]:IPMMUDS010 */ + [549] = {0xFCB520A4U, 0x0000000CU}, /* RGIDR_MODID[576]:IPMMUDS011 */ + [550] = {0xFCB520A8U, 0x0000002EU}, /* RGIDR_MODID[577]:I2C0 */ + [551] = {0xFCB520ACU, 0x0000002EU}, /* RGIDR_MODID[578]:I2C1 */ + [552] = {0xFCB520B0U, 0x0000002EU}, /* RGIDR_MODID[579]:I2C2 */ + [553] = {0xFCB520B4U, 0x0000002EU}, /* RGIDR_MODID[580]:I2C3 */ + [554] = {0xFCB520B8U, 0x0000002EU}, /* RGIDR_MODID[581]:I2C4 */ + [555] = {0xFCB520BCU, 0x0000002EU}, /* RGIDR_MODID[582]:I2C5 */ + [556] = {0xFCB520C0U, 0x0000000CU}, /* RGIDR_MODID[583]:IPMMUDS012 */ + [557] = {0xFCB520C8U, 0x0000000CU}, /* RGIDR_MODID[584]:IPMMUDS000 */ + [558] = {0xFCB520CCU, 0x0000000CU}, /* RGIDR_MODID[585]:IPMMUDS013 */ + [559] = {0xFCB520D0U, 0x0000000CU}, /* RGIDR_MODID[586]:IPMMUDS014 */ + [560] = {0xFCB520D4U, 0x0000000CU}, /* RGIDR_MODID[587]:IPMMUDS015 */ + [561] = {0xFCB520D8U, 0x0000000CU}, /* RGIDR_MODID[588]:IPMMUDS002 */ + [562] = {0xFCB520DCU, 0x0000000CU}, /* RGIDR_MODID[589]:IPMMUDS003 */ + [563] = {0xFCB520E0U, 0x0000000CU}, /* RGIDR_MODID[590]:IPMMUDS004 */ + [564] = {0xFCB520E4U, 0x0000000CU}, /* RGIDR_MODID[591]:IPMMUDS005 */ + [565] = {0xFCB520ECU, 0x0000000CU}, /* RGIDR_MODID[592]:IPMMUDS006 */ + [566] = {0xFCB520F0U, 0x0000000CU}, /* RGIDR_MODID[593]:IPMMUDS007 */ + [567] = {0xFCB520F4U, 0x0000000CU}, /* RGIDR_MODID[594]:SYDM1P */ + [568] = {0xFCB520F8U, 0x0000000CU}, /* RGIDR_MODID[595]:IPMMUDS008 */ + [569] = {0xFCB520FCU, 0x0000000CU}, /* RGIDR_MODID[596]:SYDM2P */ + [570] = {0xFCB52100U, 0x0000000CU}, /* RGIDR_MODID[597]:IPMMUDS009 */ + [571] = {0xFCB52240U, 0x0000000CU}, /* RGIDR_MODID[598]:SYDM100 */ + [572] = {0xFCB52244U, 0x0000000CU}, /* RGIDR_MODID[599]:SYDM101 */ + [573] = {0xFCB52248U, 0x0000000CU}, /* RGIDR_MODID[600]:SYDM110 */ + [574] = {0xFCB5224CU, 0x0000000CU}, /* RGIDR_MODID[601]:SYDM111 */ + [575] = {0xFCB52250U, 0x0000000CU}, /* RGIDR_MODID[602]:SYDM112 */ + [576] = {0xFCB52254U, 0x0000000CU}, /* RGIDR_MODID[603]:SYDM113 */ + [577] = {0xFCB52258U, 0x0000000CU}, /* RGIDR_MODID[604]:SYDM114 */ + [578] = {0xFCB5225CU, 0x0000000CU}, /* RGIDR_MODID[605]:SYDM115 */ + [579] = {0xFCB52260U, 0x0000000CU}, /* RGIDR_MODID[606]:SYDM102 */ + [580] = {0xFCB52264U, 0x0000000CU}, /* RGIDR_MODID[607]:SYDM103 */ + [581] = {0xFCB52268U, 0x0000000CU}, /* RGIDR_MODID[608]:SYDM104 */ + [582] = {0xFCB5226CU, 0x0000000CU}, /* RGIDR_MODID[609]:SYDM105 */ + [583] = {0xFCB52270U, 0x0000000CU}, /* RGIDR_MODID[610]:SYDM106 */ + [584] = {0xFCB52274U, 0x0000000CU}, /* RGIDR_MODID[611]:SYDM107 */ + [585] = {0xFCB52278U, 0x0000000CU}, /* RGIDR_MODID[612]:SYDM108 */ + [586] = {0xFCB5227CU, 0x0000000CU}, /* RGIDR_MODID[613]:SYDM109 */ + [587] = {0xFCB52280U, 0x0000000CU}, /* RGIDR_MODID[614]:SYDM200 */ + [588] = {0xFCB52284U, 0x0000000CU}, /* RGIDR_MODID[615]:SYDM201 */ + [589] = {0xFCB52288U, 0x0000000CU}, /* RGIDR_MODID[616]:SYDM210 */ + [590] = {0xFCB5228CU, 0x0000000CU}, /* RGIDR_MODID[617]:SYDM211 */ + [591] = {0xFCB52290U, 0x0000000CU}, /* RGIDR_MODID[618]:SYDM212 */ + [592] = {0xFCB52294U, 0x0000000CU}, /* RGIDR_MODID[619]:SYDM213 */ + [593] = {0xFCB52298U, 0x0000000CU}, /* RGIDR_MODID[620]:SYDM214 */ + [594] = {0xFCB5229CU, 0x0000000CU}, /* RGIDR_MODID[621]:SYDM215 */ + [595] = {0xFCB522A0U, 0x0000000CU}, /* RGIDR_MODID[622]:SYDM202 */ + [596] = {0xFCB522A4U, 0x0000000CU}, /* RGIDR_MODID[623]:SYDM203 */ + [597] = {0xFCB522A8U, 0x0000000CU}, /* RGIDR_MODID[624]:SYDM204 */ + [598] = {0xFCB522ACU, 0x0000000CU}, /* RGIDR_MODID[625]:SYDM205 */ + [599] = {0xFCB522B0U, 0x0000000CU}, /* RGIDR_MODID[626]:SYDM206 */ + [600] = {0xFCB522B4U, 0x0000000CU}, /* RGIDR_MODID[627]:SYDM207 */ + [601] = {0xFCB522B8U, 0x0000000CU}, /* RGIDR_MODID[628]:SYDM208 */ + [602] = {0xFCB522BCU, 0x0000000CU}, /* RGIDR_MODID[629]:SYDM209 */ + [604] = {0xFDDB9660U, 0x0000003FU}, /* RGIDR_MODID[630]:ARCC */ + [603] = {0xFDDB9674U, 0x0000003FU}, /* RGIDR_MODID[631]:ARRTRAM */ + [605] = {0xFCB52024U, 0x00000000U}, /* RGIDR_MODID[632]:RSV0 */ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_w_tbl" +const REGION_ID_SETTING_TABLE g_rgid_w_tbl[] = { + [0] = {0xFD482400U, 0x0000002EU}, /* RGIDW_MODID[0]:ARMGC0 */ + [1] = {0xFD482404U, 0x0000002EU}, /* RGIDW_MODID[1]:ARMGC1 */ + [2] = {0xFD482408U, 0x00000000U}, /* RGIDW_MODID[2]:ARMGC2 */ + [3] = {0xFD48240CU, 0x00000022U}, /* RGIDW_MODID[3]:ARRT00 */ + /* After setting */ /* RGIDW_MODID[4]:ARRT01 */ + /* After setting */ /* RGIDW_MODID[5]:ARRT02 */ + [4] = {0xFD482418U, 0x00000011U}, /* RGIDW_MODID[6]:ARRT03 */ + [5] = {0xFD48241CU, 0x00000022U}, /* RGIDW_MODID[7]:ARRT04 */ + [6] = {0xFD482420U, 0x00000011U}, /* RGIDW_MODID[8]:ARRT05 */ + [7] = {0xFD482424U, 0x00000022U}, /* RGIDW_MODID[9]:ARRT06 */ + [8] = {0xFD482428U, 0x00000022U}, /* RGIDW_MODID[10]:ARRT07 */ + [9] = {0xFD48242CU, 0x00000000U}, /* RGIDW_MODID[11]:ARRT08 */ + [10] = {0xFD482430U, 0x00000011U}, /* RGIDW_MODID[12]:LIFEC0 */ + [11] = {0xFD482434U, 0x00000026U}, /* RGIDW_MODID[13]:SWDT */ + [12] = {0xFD482438U, 0x0000003FU}, /* RGIDW_MODID[14]:TMU0 */ + [13] = {0xFD48243CU, 0x00000026U}, /* RGIDW_MODID[15]:WDT */ + [14] = {0xFD482440U, 0x00000026U}, /* RGIDW_MODID[16]:WWDT0 */ + [15] = {0xFD482444U, 0x00000026U}, /* RGIDW_MODID[17]:WWDT1 */ + [16] = {0xFD482448U, 0x00000026U}, /* RGIDW_MODID[18]:WWDT2 */ + [17] = {0xFD48244CU, 0x00000026U}, /* RGIDW_MODID[19]:WWDT3 */ + [18] = {0xFD482450U, 0x00000026U}, /* RGIDW_MODID[20]:WWDT4 */ + [19] = {0xFD482454U, 0x00000026U}, /* RGIDW_MODID[21]:WWDT5 */ + [20] = {0xFD482458U, 0x00000026U}, /* RGIDW_MODID[22]:WWDT6 */ + [21] = {0xFD48245CU, 0x00000026U}, /* RGIDW_MODID[23]:WWDT7 */ + [22] = {0xFD482460U, 0x00000026U}, /* RGIDW_MODID[24]:WWDT8 */ + [23] = {0xFD482464U, 0x00000026U}, /* RGIDW_MODID[25]:WWDT9 */ + [24] = {0xFD482468U, 0x0000003FU}, /* RGIDW_MODID[26]:ECMRT3 */ + [25] = {0xFDA02400U, 0x00000026U}, /* RGIDW_MODID[27]:ADVFSC */ + [26] = {0xFDA02404U, 0x0000003FU}, /* RGIDW_MODID[28]:APMU0 */ + [27] = {0xFDA02408U, 0x00000002U}, /* RGIDW_MODID[29]:APMU1 */ + [28] = {0xFDA0240CU, 0x00000000U}, /* RGIDW_MODID[30]:APMU10 */ + [29] = {0xFDA02410U, 0x00000000U}, /* RGIDW_MODID[31]:APMU11 */ + [30] = {0xFDA02414U, 0x00000000U}, /* RGIDW_MODID[32]:APMU12 */ + [31] = {0xFDA02418U, 0x00000000U}, /* RGIDW_MODID[33]:APMU13 */ + [32] = {0xFDA0241CU, 0x00000000U}, /* RGIDW_MODID[34]:APMU14 */ + [33] = {0xFDA02420U, 0x00000000U}, /* RGIDW_MODID[35]:APMU15 */ + [34] = {0xFDA02424U, 0x00000004U}, /* RGIDW_MODID[36]:APMU2 */ + [35] = {0xFDA02428U, 0x00000004U}, /* RGIDW_MODID[37]:APMU3 */ + [36] = {0xFDA0242CU, 0x00000000U}, /* RGIDW_MODID[38]:APMU4 */ + [37] = {0xFDA02430U, 0x00000000U}, /* RGIDW_MODID[39]:APMU5 */ + [38] = {0xFDA02434U, 0x00000000U}, /* RGIDW_MODID[40]:APMU6 */ + [39] = {0xFDA02438U, 0x00000000U}, /* RGIDW_MODID[41]:APMU7 */ + [40] = {0xFDA0243CU, 0x00000000U}, /* RGIDW_MODID[42]:APMU8 */ + [41] = {0xFDA02440U, 0x00000000U}, /* RGIDW_MODID[43]:APMU9 */ + [42] = {0xFDA02444U, 0x00000022U}, /* RGIDW_MODID[44]:ARS00 */ + /* After setting */ /* RGIDW_MODID[45]:ARS01 */ + /* After setting */ /* RGIDW_MODID[46]:ARS02 */ + [43] = {0xFDA02450U, 0x00000011U}, /* RGIDW_MODID[47]:ARS03 */ + [44] = {0xFDA02454U, 0x00000022U}, /* RGIDW_MODID[48]:ARS04 */ + [45] = {0xFDA02458U, 0x00000011U}, /* RGIDW_MODID[49]:ARS05 */ + [46] = {0xFDA0245CU, 0x00000022U}, /* RGIDW_MODID[50]:ARS06 */ + [47] = {0xFDA02460U, 0x00000022U}, /* RGIDW_MODID[51]:ARS07 */ + [48] = {0xFDA02464U, 0x00000000U}, /* RGIDW_MODID[52]:ARS08 */ + [49] = {0xFDA02468U, 0x0000002EU}, /* RGIDW_MODID[53]:CMT0 */ + [50] = {0xFDA0246CU, 0x0000002EU}, /* RGIDW_MODID[54]:CMT1 */ + [51] = {0xFDA02470U, 0x0000002EU}, /* RGIDW_MODID[55]:CMT2 */ + [52] = {0xFDA02474U, 0x0000002EU}, /* RGIDW_MODID[56]:CMT3 */ + [53] = {0xFDA02478U, 0x0000002AU}, /* RGIDW_MODID[57]:CKM */ + [54] = {0xFDA0247CU, 0x0000002EU}, /* RGIDW_MODID[58]:DBE */ + [55] = {0xFDA02480U, 0x0000002EU}, /* RGIDW_MODID[59]:IRQC */ + [56] = {0xFDA02484U, 0x0000003BU}, /* RGIDW_MODID[60]:ECMPS0 */ + [57] = {0xFDA0249CU, 0x0000002EU}, /* RGIDW_MODID[61]:SCMT */ + [58] = {0xFDA024A8U, 0x0000002EU}, /* RGIDW_MODID[62]:TSC1 */ + [59] = {0xFDA024ACU, 0x0000002EU}, /* RGIDW_MODID[63]:TSC2 */ + [60] = {0xFDA024B0U, 0x0000002EU}, /* RGIDW_MODID[64]:TSC3 */ + [61] = {0xFDA024B4U, 0x0000002EU}, /* RGIDW_MODID[65]:TSC4 */ + [62] = {0xFDA024B8U, 0x00000026U}, /* RGIDW_MODID[66]:UCMT */ + [63] = {0xFDA02500U, 0x0000003FU}, /* RGIDW_MODID[67]:CPG0 */ + [64] = {0xFDA02504U, 0x0000002AU}, /* RGIDW_MODID[68]:CPG1 */ + [65] = {0xFDA02508U, 0x0000000CU}, /* RGIDW_MODID[69]:CPG2 */ + [66] = {0xFDA0250CU, 0x0000000CU}, /* RGIDW_MODID[70]:CPG3 */ + [67] = {0xFDA02510U, 0x0000003FU}, /* RGIDW_MODID[71]:PFC00 */ + [68] = {0xFDA02514U, 0x0000002AU}, /* RGIDW_MODID[72]:PFC01 */ + [69] = {0xFDA02518U, 0x0000000CU}, /* RGIDW_MODID[73]:PFC02 */ + [70] = {0xFDA0251CU, 0x0000000CU}, /* RGIDW_MODID[74]:PFC03 */ + [71] = {0xFDA02550U, 0x0000003FU}, /* RGIDW_MODID[75]:PFCS0 */ + [72] = {0xFDA02554U, 0x0000002AU}, /* RGIDW_MODID[76]:PFCS1 */ + [73] = {0xFDA02558U, 0x0000000CU}, /* RGIDW_MODID[77]:PFCS2 */ + [74] = {0xFDA0255CU, 0x0000000CU}, /* RGIDW_MODID[78]:PFCS3 */ + [75] = {0xFDA02560U, 0x0000003FU}, /* RGIDW_MODID[79]:RESET0 */ + [76] = {0xFDA02564U, 0x0000002AU}, /* RGIDW_MODID[80]:RESET1 */ + [77] = {0xFDA02568U, 0x0000000CU}, /* RGIDW_MODID[81]:RESET2 */ + [78] = {0xFDA0256CU, 0x0000000CU}, /* RGIDW_MODID[82]:RESET3 */ + [79] = {0xFDA02570U, 0x0000003FU}, /* RGIDW_MODID[83]:SYS0 */ + [80] = {0xFDA02574U, 0x0000002AU}, /* RGIDW_MODID[84]:SYS1 */ + [81] = {0xFDA02578U, 0x0000000CU}, /* RGIDW_MODID[85]:SYS2 */ + [82] = {0xFDA0257CU, 0x0000000CU}, /* RGIDW_MODID[86]:SYS3 */ + [83] = {0xFCB62400U, 0x0000002EU}, /* RGIDW_MODID[87]:DMAMSI0 */ + [84] = {0xFCB62404U, 0x0000002EU}, /* RGIDW_MODID[88]:DMAMSI1 */ + [85] = {0xFCB62408U, 0x0000002EU}, /* RGIDW_MODID[89]:DMAMSI2 */ + [86] = {0xFCB6240CU, 0x0000002EU}, /* RGIDW_MODID[90]:DMAMSI3 */ + [87] = {0xFCB62418U, 0x0000003BU}, /* RGIDW_MODID[91]:ECMSP3 */ + [88] = {0xFCB62424U, 0x00000022U}, /* RGIDW_MODID[92]:ARSP30 */ + /* After setting */ /* RGIDW_MODID[93]:ARSP31 */ + /* After setting */ /* RGIDW_MODID[94]:ARSP32 */ + [89] = {0xFCB62430U, 0x00000011U}, /* RGIDW_MODID[95]:ARSP33 */ + [90] = {0xFCB62434U, 0x00000022U}, /* RGIDW_MODID[96]:ARSP34 */ + [91] = {0xFCB62438U, 0x00000011U}, /* RGIDW_MODID[97]:ARSP35 */ + [92] = {0xFCB6243CU, 0x00000022U}, /* RGIDW_MODID[98]:ARSP36 */ + [93] = {0xFCB62440U, 0x00000022U}, /* RGIDW_MODID[99]:ARSP37 */ + [94] = {0xFCB62444U, 0x00000000U}, /* RGIDW_MODID[100]:ARSP38 */ + [95] = {0xFCB62448U, 0x0000002EU}, /* RGIDW_MODID[101]:MSI0 */ + [96] = {0xFCB6244CU, 0x0000002EU}, /* RGIDW_MODID[102]:MSI1 */ + [97] = {0xFCB62450U, 0x0000002EU}, /* RGIDW_MODID[103]:MSI2 */ + [98] = {0xFCB62454U, 0x0000002EU}, /* RGIDW_MODID[104]:MSI3 */ + [99] = {0xFCB92400U, 0x00000022U}, /* RGIDW_MODID[105]:ARSP40 */ + /* After setting */ /* RGIDW_MODID[106]:ARSP41 */ + /* After setting */ /* RGIDW_MODID[107]:ARSP42 */ + [100] = {0xFCB9240CU, 0x00000011U}, /* RGIDW_MODID[108]:ARSP43 */ + [101] = {0xFCB92410U, 0x00000022U}, /* RGIDW_MODID[109]:ARSP44 */ + [102] = {0xFCB92414U, 0x00000011U}, /* RGIDW_MODID[110]:ARSP45 */ + [103] = {0xFCB92418U, 0x00000022U}, /* RGIDW_MODID[111]:ARSP46 */ + [104] = {0xFCB9241CU, 0x00000022U}, /* RGIDW_MODID[112]:ARSP47 */ + [105] = {0xFCB92420U, 0x00000000U}, /* RGIDW_MODID[113]:ARSP48 */ + [106] = {0xFCB92424U, 0x0000003FU}, /* RGIDW_MODID[114]:DMAHSCIF0 */ + [107] = {0xFCB92428U, 0x0000003FU}, /* RGIDW_MODID[115]:DMAHSCIF1 */ + [108] = {0xFCB9242CU, 0x0000003FU}, /* RGIDW_MODID[116]:DMAHSCIF2 */ + [109] = {0xFCB92430U, 0x0000003FU}, /* RGIDW_MODID[117]:DMAHSCIF3 */ + [110] = {0xFCB92434U, 0x0000003FU}, /* RGIDW_MODID[118]:DMASCIF0 */ + [111] = {0xFCB92438U, 0x0000003FU}, /* RGIDW_MODID[119]:DMASCIF1 */ + [112] = {0xFCB9243CU, 0x0000003FU}, /* RGIDW_MODID[120]:DMASCIF3 */ + [113] = {0xFCB92440U, 0x0000003FU}, /* RGIDW_MODID[121]:DMASCIF4 */ + [114] = {0xFCB92444U, 0x0000003BU}, /* RGIDW_MODID[122]:ECMSP4 */ + [115] = {0xFCB92448U, 0x0000003FU}, /* RGIDW_MODID[123]:HSCIF0 */ + [116] = {0xFCB9244CU, 0x0000003FU}, /* RGIDW_MODID[124]:HSCIF1 */ + [117] = {0xFCB92450U, 0x0000003FU}, /* RGIDW_MODID[125]:HSCIF2 */ + [118] = {0xFCB92454U, 0x0000003FU}, /* RGIDW_MODID[126]:HSCIF3 */ + [119] = {0xFCB92458U, 0x0000003FU}, /* RGIDW_MODID[127]:SCIF0 */ + [120] = {0xFCB9245CU, 0x0000003FU}, /* RGIDW_MODID[128]:SCIF1 */ + [121] = {0xFCB92460U, 0x0000003FU}, /* RGIDW_MODID[129]:SCIF3 */ + [122] = {0xFCB92464U, 0x0000003FU}, /* RGIDW_MODID[130]:SCIF4 */ + [123] = {0xFCB92468U, 0x0000003FU}, /* RGIDW_MODID[131]:TMU1 */ + [124] = {0xFCB9246CU, 0x0000003FU}, /* RGIDW_MODID[132]:TMU2 */ + [125] = {0xFCB92470U, 0x0000003FU}, /* RGIDW_MODID[133]:TMU3 */ + [126] = {0xFCB92474U, 0x0000003FU}, /* RGIDW_MODID[134]:TMU4 */ + [127] = {0xFCF82400U, 0x0000002AU}, /* RGIDW_MODID[135]:CKMHSC */ + [128] = {0xFCF82404U, 0x0000000CU}, /* RGIDW_MODID[136]:AXIPCI001 */ + [129] = {0xFCF82408U, 0x0000000CU}, /* RGIDW_MODID[137]:AXIPCI002 */ + [130] = {0xFCF8240CU, 0x0000000CU}, /* RGIDW_MODID[138]:AXIPCI003 */ + [131] = {0xFCF82410U, 0x0000002EU}, /* RGIDW_MODID[139]:ETHPHY */ + [132] = {0xFCF82414U, 0x0000000CU}, /* RGIDW_MODID[140]:AXIPCI005 */ + [133] = {0xFCF82418U, 0x0000000CU}, /* RGIDW_MODID[141]:AXIPCI006 */ + [134] = {0xFCF8241CU, 0x0000000CU}, /* RGIDW_MODID[142]:AXIPCI007 */ + [135] = {0xFCF82420U, 0x0000000CU}, /* RGIDW_MODID[143]:AXIPCI008 */ + [136] = {0xFCF82424U, 0x0000000CU}, /* RGIDW_MODID[144]:AXIPCI009 */ + [137] = {0xFCF82428U, 0x0000000CU}, /* RGIDW_MODID[145]:AXIPCI010 */ + [138] = {0xFCF8242CU, 0x0000000CU}, /* RGIDW_MODID[146]:AXIPCI011 */ + [139] = {0xFCF82430U, 0x0000000CU}, /* RGIDW_MODID[147]:AXIPCI012 */ + [140] = {0xFCF82434U, 0x0000000CU}, /* RGIDW_MODID[148]:AXIPCI013 */ + [141] = {0xFCF82438U, 0x0000000CU}, /* RGIDW_MODID[149]:AXIPCI014 */ + [142] = {0xFCF8243CU, 0x0000000CU}, /* RGIDW_MODID[150]:AXIPCI015 */ + [143] = {0xFCF82440U, 0x0000000CU}, /* RGIDW_MODID[151]:AXIPCI100 */ + [144] = {0xFCF82444U, 0x0000000CU}, /* RGIDW_MODID[152]:AXIPCI101 */ + [145] = {0xFCF82448U, 0x0000000CU}, /* RGIDW_MODID[153]:AXIPCI102 */ + [146] = {0xFCF8244CU, 0x0000000CU}, /* RGIDW_MODID[154]:AXIPCI103 */ + [147] = {0xFCF82450U, 0x0000000CU}, /* RGIDW_MODID[155]:AXIPCI104 */ + [148] = {0xFCF82454U, 0x0000000CU}, /* RGIDW_MODID[156]:AXIPCI105 */ + [149] = {0xFCF82458U, 0x0000000CU}, /* RGIDW_MODID[157]:AXIPCI106 */ + [150] = {0xFCF8245CU, 0x0000000CU}, /* RGIDW_MODID[158]:AXIPCI107 */ + [151] = {0xFCF82460U, 0x0000000CU}, /* RGIDW_MODID[159]:AXIPCI108 */ + [152] = {0xFCF82464U, 0x0000000CU}, /* RGIDW_MODID[160]:AXIPCI109 */ + [153] = {0xFCF82468U, 0x0000000CU}, /* RGIDW_MODID[161]:AXIPCI110 */ + [154] = {0xFCF8246CU, 0x0000000CU}, /* RGIDW_MODID[162]:AXIPCI111 */ + [155] = {0xFCF82470U, 0x0000000CU}, /* RGIDW_MODID[163]:AXIPCI112 */ + [156] = {0xFCF82474U, 0x0000000CU}, /* RGIDW_MODID[164]:AXIPCI113 */ + [157] = {0xFCF82478U, 0x0000000CU}, /* RGIDW_MODID[165]:AXIPCI114 */ + [158] = {0xFCF8247CU, 0x0000000CU}, /* RGIDW_MODID[166]:AXIPCI115 */ + [159] = {0xFCF82480U, 0x0000002EU}, /* RGIDW_MODID[167]:ETHPHYRAM */ + [160] = {0xFCF82488U, 0x0000000CU}, /* RGIDW_MODID[168]:IPMMUHC00 */ + [161] = {0xFCF8248CU, 0x0000002EU}, /* RGIDW_MODID[169]:RSW200 */ + [162] = {0xFCF82490U, 0x0000002EU}, /* RGIDW_MODID[170]:RSW201 */ + [163] = {0xFCF82494U, 0x0000002EU}, /* RGIDW_MODID[171]:RSW210 */ + [164] = {0xFCF82498U, 0x0000002EU}, /* RGIDW_MODID[172]:RSW211 */ + [165] = {0xFCF8249CU, 0x0000002EU}, /* RGIDW_MODID[173]:RSW202 */ + [166] = {0xFCF824A0U, 0x0000002EU}, /* RGIDW_MODID[174]:RSW203 */ + [167] = {0xFCF824A4U, 0x0000002EU}, /* RGIDW_MODID[175]:RSW204 */ + [168] = {0xFCF824A8U, 0x0000002EU}, /* RGIDW_MODID[176]:RSW205 */ + [169] = {0xFCF824ACU, 0x0000002EU}, /* RGIDW_MODID[177]:RSW206 */ + [170] = {0xFCF824B0U, 0x0000002EU}, /* RGIDW_MODID[178]:RSW207 */ + [171] = {0xFCF824B4U, 0x0000002EU}, /* RGIDW_MODID[179]:RSW208 */ + [172] = {0xFCF824B8U, 0x0000002EU}, /* RGIDW_MODID[180]:RSW209 */ + [173] = {0xFCF824BCU, 0x0000002EU}, /* RGIDW_MODID[181]:RSW2RAM */ + [174] = {0xFCF824C0U, 0x0000002AU}, /* RGIDW_MODID[182]:RSW2SEC00 */ + [175] = {0xFCF824C4U, 0x0000002AU}, /* RGIDW_MODID[183]:RSW2SEC01 */ + [176] = {0xFCF824C8U, 0x0000002AU}, /* RGIDW_MODID[184]:RSW2SEC10 */ + [177] = {0xFCF824CCU, 0x0000002AU}, /* RGIDW_MODID[185]:RSW2SEC11 */ + [178] = {0xFCF824D0U, 0x0000002AU}, /* RGIDW_MODID[186]:RSW2SEC02 */ + [179] = {0xFCF824D4U, 0x0000002AU}, /* RGIDW_MODID[187]:RSW2SEC03 */ + [180] = {0xFCF824D8U, 0x0000002AU}, /* RGIDW_MODID[188]:RSW2SEC04 */ + [181] = {0xFCF824DCU, 0x0000002AU}, /* RGIDW_MODID[189]:RSW2SEC05 */ + [182] = {0xFCF824E0U, 0x0000002AU}, /* RGIDW_MODID[190]:RSW2SEC06 */ + [183] = {0xFCF824E4U, 0x0000002AU}, /* RGIDW_MODID[191]:RSW2SEC07 */ + [184] = {0xFCF824E8U, 0x0000002AU}, /* RGIDW_MODID[192]:RSW2SEC08 */ + [185] = {0xFCF824ECU, 0x0000002AU}, /* RGIDW_MODID[193]:RSW2SEC09 */ + [186] = {0xFCF824F4U, 0x0000000CU}, /* RGIDW_MODID[194]:AXIPCI000 */ + [187] = {0xFCF824F8U, 0x0000000CU}, /* RGIDW_MODID[195]:AXIPCI004 */ + [188] = {0xFCF824FCU, 0x0000000CU}, /* RGIDW_MODID[196]:IPMMUHC01 */ + [189] = {0xFCF8250CU, 0x0000000CU}, /* RGIDW_MODID[197]:IPMMUHC10 */ + [190] = {0xFCF82510U, 0x0000000CU}, /* RGIDW_MODID[198]:IPMMUHC11 */ + [191] = {0xFCF82514U, 0x0000000CU}, /* RGIDW_MODID[199]:IPMMUHC12 */ + [192] = {0xFCF82518U, 0x0000000CU}, /* RGIDW_MODID[200]:IPMMUHC13 */ + [193] = {0xFCF8251CU, 0x0000000CU}, /* RGIDW_MODID[201]:PPHY0 */ + [194] = {0xFCF82520U, 0x0000000CU}, /* RGIDW_MODID[202]:PPHY1 */ + [195] = {0xFCF82524U, 0x0000000CU}, /* RGIDW_MODID[203]:IPMMUHC14 */ + [196] = {0xFCF82528U, 0x0000000CU}, /* RGIDW_MODID[204]:IPMMUHC15 */ + [197] = {0xFCF8252CU, 0x0000002EU}, /* RGIDW_MODID[205]:FBAHSC */ + [198] = {0xFCF82530U, 0x0000000CU}, /* RGIDW_MODID[206]:IPMMUHC02 */ + [199] = {0xFCF82534U, 0x0000003FU}, /* RGIDW_MODID[207]:AXIUFSS */ + [200] = {0xFCF82538U, 0x0000003BU}, /* RGIDW_MODID[208]:ECMHSC */ + [201] = {0xFCF8253CU, 0x00000022U}, /* RGIDW_MODID[209]:ARHC0 */ + /* After setting */ /* RGIDW_MODID[210]:ARHC1 */ + /* After setting */ /* RGIDW_MODID[211]:ARHC2 */ + [202] = {0xFCF82548U, 0x00000011U}, /* RGIDW_MODID[212]:ARHC3 */ + [203] = {0xFCF8254CU, 0x00000022U}, /* RGIDW_MODID[213]:ARHC4 */ + [204] = {0xFCF82550U, 0x00000011U}, /* RGIDW_MODID[214]:ARHC5 */ + [205] = {0xFCF82554U, 0x00000022U}, /* RGIDW_MODID[215]:ARHC6 */ + [206] = {0xFCF82558U, 0x00000022U}, /* RGIDW_MODID[216]:ARHC7 */ + [207] = {0xFCF8255CU, 0x00000000U}, /* RGIDW_MODID[217]:ARHC8 */ + [208] = {0xFCF82560U, 0x0000000CU}, /* RGIDW_MODID[218]:IPMMUHC03 */ + [209] = {0xFCF82564U, 0x0000000CU}, /* RGIDW_MODID[219]:IPMMUHC04 */ + [210] = {0xFCF82568U, 0x0000000CU}, /* RGIDW_MODID[220]:IPMMUHC05 */ + [211] = {0xFCF8256CU, 0x0000000CU}, /* RGIDW_MODID[221]:IPMMUHC06 */ + [212] = {0xFCF82570U, 0x0000000CU}, /* RGIDW_MODID[222]:IPMMUHC07 */ + [213] = {0xFCF82574U, 0x0000000CU}, /* RGIDW_MODID[223]:IPMMUHC08 */ + [214] = {0xFCF82578U, 0x0000000CU}, /* RGIDW_MODID[224]:IPMMUHC09 */ + [215] = {0xFDC22400U, 0x00000022U}, /* RGIDW_MODID[225]:ARRC0 */ + [216] = {0xFDC22404U, 0x00000000U}, /* RGIDW_MODID[226]:ARRC1 */ + /* After setting */ /* RGIDW_MODID[227]:ARRC2 */ + /* After setting */ /* RGIDW_MODID[228]:ARRC3 */ + [217] = {0xFDC22410U, 0x00000022U}, /* RGIDW_MODID[229]:ARRC4 */ + [218] = {0xFDC22414U, 0x00000011U}, /* RGIDW_MODID[230]:ARRC5 */ + [219] = {0xFDC22418U, 0x00000022U}, /* RGIDW_MODID[231]:ARRC6 */ + [220] = {0xFDC2241CU, 0x00000022U}, /* RGIDW_MODID[232]:ARRC7 */ + [221] = {0xFDC22420U, 0x00000000U}, /* RGIDW_MODID[233]:ARRC8 */ + [222] = {0xFDC22424U, 0x00000019U}, /* RGIDW_MODID[234]:CR0 */ + [223] = {0xFDC22428U, 0x0000003FU}, /* RGIDW_MODID[235]:ICUMX */ + [224] = {0xFDC2242CU, 0x0000003BU}, /* RGIDW_MODID[236]:ECMRC */ + [225] = {0xFD432400U, 0x0000002EU}, /* RGIDW_MODID[237]:DMAWCRC0 */ + [226] = {0xFD432404U, 0x0000002EU}, /* RGIDW_MODID[238]:DMAWCRC1 */ + [227] = {0xFD432408U, 0x0000002EU}, /* RGIDW_MODID[239]:DMAWCRC2 */ + [228] = {0xFD43240CU, 0x0000002EU}, /* RGIDW_MODID[240]:DMAWCRC3 */ + [229] = {0xFD432410U, 0x0000000CU}, /* RGIDW_MODID[241]:DMATSIP0 */ + [230] = {0xFD432414U, 0x0000000CU}, /* RGIDW_MODID[242]:DMATSIP1 */ + [231] = {0xFD432418U, 0x0000000CU}, /* RGIDW_MODID[243]:DMATSIP2 */ + [232] = {0xFD442400U, 0x0000003FU}, /* RGIDW_MODID[244]:ARMREG00 */ + [233] = {0xFD442404U, 0x0000000CU}, /* RGIDW_MODID[245]:ARMREG01 */ + [234] = {0xFD442408U, 0x00000000U}, /* RGIDW_MODID[246]:ARMREG10 */ + [235] = {0xFD44240CU, 0x00000000U}, /* RGIDW_MODID[247]:ARMREG11 */ + [236] = {0xFD442410U, 0x0000002AU}, /* RGIDW_MODID[248]:ARMREG12 */ + [237] = {0xFD442414U, 0x0000003FU}, /* RGIDW_MODID[249]:ARMREG13 */ + [238] = {0xFD442418U, 0x0000002AU}, /* RGIDW_MODID[250]:ARMREG14 */ + [239] = {0xFD44241CU, 0x00000033U}, /* RGIDW_MODID[251]:AXICR52SS */ + [240] = {0xFD442420U, 0x0000002EU}, /* RGIDW_MODID[252]:AXICSD0 */ + [241] = {0xFD442424U, 0x0000002EU}, /* RGIDW_MODID[253]:AXIINTAP0 */ + [242] = {0xFD442428U, 0x0000002EU}, /* RGIDW_MODID[254]:AXIINTAP1 */ + [243] = {0xFD44242CU, 0x00000019U}, /* RGIDW_MODID[255]:AXISECROM */ + [244] = {0xFD442430U, 0x0000003FU}, /* RGIDW_MODID[256]:AXISYSRAM0 */ + [245] = {0xFD442434U, 0x0000003FU}, /* RGIDW_MODID[257]:AXISYSRAM1 */ + [246] = {0xFD442438U, 0x00000000U}, /* RGIDW_MODID[258]:ARGREG15 */ + [247] = {0xFD44243CU, 0x00000000U}, /* RGIDW_MODID[259]:ARMREG2 */ + [248] = {0xFD442440U, 0x00000000U}, /* RGIDW_MODID[260]:ARMREG3 */ + [249] = {0xFD442444U, 0x00000000U}, /* RGIDW_MODID[261]:ARMREG4 */ + [250] = {0xFD442448U, 0x0000003FU}, /* RGIDW_MODID[262]:ARMREG5 */ + [251] = {0xFD44244CU, 0x0000002AU}, /* RGIDW_MODID[263]:ARMREG6 */ + [252] = {0xFD442450U, 0x00000000U}, /* RGIDW_MODID[264]:ARMREG7 */ + [253] = {0xFD442454U, 0x0000000CU}, /* RGIDW_MODID[265]:ARMREG8 */ + [254] = {0xFD442458U, 0x0000000CU}, /* RGIDW_MODID[266]:ARMREG9 */ + [255] = {0xFD44245CU, 0x00000022U}, /* RGIDW_MODID[267]:ARRD0 */ + /* After setting */ /* RGIDW_MODID[268]:ARRD1 */ + /* After setting */ /* RGIDW_MODID[269]:ARRD2 */ + [256] = {0xFD442468U, 0x00000011U}, /* RGIDW_MODID[270]:ARRD3 */ + [257] = {0xFD44246CU, 0x00000022U}, /* RGIDW_MODID[271]:ARRD4 */ + [258] = {0xFD442470U, 0x00000011U}, /* RGIDW_MODID[272]:ARRD5 */ + [259] = {0xFD442474U, 0x00000022U}, /* RGIDW_MODID[273]:ARRD6 */ + [260] = {0xFD442478U, 0x00000022U}, /* RGIDW_MODID[274]:ARRD7 */ + [261] = {0xFD44247CU, 0x00000000U}, /* RGIDW_MODID[275]:ARRD8 */ + [262] = {0xFD442480U, 0x00000022U}, /* RGIDW_MODID[276]:ARRT0 */ + /* After setting */ /* RGIDW_MODID[277]:ARRT1 */ + /* After setting */ /* RGIDW_MODID[278]:ARRT2 */ + [263] = {0xFD44248CU, 0x00000011U}, /* RGIDW_MODID[279]:ARRT3 */ + [264] = {0xFD442490U, 0x00000022U}, /* RGIDW_MODID[280]:ARRT4 */ + [265] = {0xFD442494U, 0x00000011U}, /* RGIDW_MODID[281]:ARRT5 */ + [266] = {0xFD442498U, 0x00000022U}, /* RGIDW_MODID[282]:ARRT6 */ + [267] = {0xFD44249CU, 0x00000022U}, /* RGIDW_MODID[283]:ARRT7 */ + [268] = {0xFD4424A0U, 0x00000000U}, /* RGIDW_MODID[284]:ARRT8 */ + [269] = {0xFD4424A4U, 0x0000002AU}, /* RGIDW_MODID[285]:CKMRT */ + [270] = {0xFD4424A8U, 0x0000002EU}, /* RGIDW_MODID[286]:CRC0 */ + [271] = {0xFD4424ACU, 0x0000002EU}, /* RGIDW_MODID[287]:CRC1 */ + [272] = {0xFD4424B0U, 0x0000002EU}, /* RGIDW_MODID[288]:CRC2 */ + [273] = {0xFD4424B4U, 0x0000002EU}, /* RGIDW_MODID[289]:CRC3 */ + [274] = {0xFD4424B8U, 0x0000002EU}, /* RGIDW_MODID[290]:CSD */ + [275] = {0xFD4424BCU, 0x0000003BU}, /* RGIDW_MODID[291]:ECM */ + [276] = {0xFD4424C0U, 0x0000003BU}, /* RGIDW_MODID[292]:ECMRT */ + [277] = {0xFD4424C4U, 0x0000002EU}, /* RGIDW_MODID[293]:FBACR52 */ + [278] = {0xFD4424C8U, 0x0000002EU}, /* RGIDW_MODID[294]:FBART */ + [279] = {0xFD4424CCU, 0x0000002EU}, /* RGIDW_MODID[295]:INTTP */ + [280] = {0xFD4424D0U, 0x0000000CU}, /* RGIDW_MODID[296]:IPMMURT000 */ + [281] = {0xFD4424D4U, 0x0000000CU}, /* RGIDW_MODID[297]:IPMMURT100 */ + [282] = {0xFD4424D8U, 0x0000002EU}, /* RGIDW_MODID[298]:KCRC4 */ + [283] = {0xFD4424DCU, 0x0000002EU}, /* RGIDW_MODID[299]:KCRC5 */ + [284] = {0xFD4424E0U, 0x0000002EU}, /* RGIDW_MODID[300]:KCRC6 */ + [285] = {0xFD4424E4U, 0x0000002EU}, /* RGIDW_MODID[301]:KCRC7 */ + [286] = {0xFD4424E8U, 0x0000003FU}, /* RGIDW_MODID[302]:MFI00 */ + [287] = {0xFD4424ECU, 0x0000002EU}, /* RGIDW_MODID[303]:MFI01 */ + [288] = {0xFD4424F0U, 0x0000002EU}, /* RGIDW_MODID[304]:MFI10 */ + [289] = {0xFD4424F4U, 0x0000002EU}, /* RGIDW_MODID[305]:MFI02 */ + [290] = {0xFD4424F8U, 0x0000002EU}, /* RGIDW_MODID[306]:MFI03 */ + [291] = {0xFD4424FCU, 0x0000002EU}, /* RGIDW_MODID[307]:MFI04 */ + [292] = {0xFD442500U, 0x00000000U}, /* RGIDW_MODID[308]:MFI05 */ + [293] = {0xFD442504U, 0x00000000U}, /* RGIDW_MODID[309]:MFI06 */ + [294] = {0xFD442508U, 0x00000000U}, /* RGIDW_MODID[310]:MFI07 */ + [295] = {0xFD44250CU, 0x00000000U}, /* RGIDW_MODID[311]:MFI08 */ + [296] = {0xFD442510U, 0x0000002EU}, /* RGIDW_MODID[312]:MFI09 */ + [297] = {0xFD442514U, 0x0000003FU}, /* RGIDW_MODID[313]:MFI15 */ + [298] = {0xFD442518U, 0x0000002AU}, /* RGIDW_MODID[314]:CKMCR52 */ + [299] = {0xFD44251CU, 0x0000003BU}, /* RGIDW_MODID[315]:RTDM0P */ + [300] = {0xFD442520U, 0x0000003BU}, /* RGIDW_MODID[316]:ECMRD */ + [301] = {0xFD442524U, 0x0000003BU}, /* RGIDW_MODID[317]:RTDM1P */ + [302] = {0xFD44252CU, 0x0000003BU}, /* RGIDW_MODID[318]:RTDM2P */ + [303] = {0xFD442530U, 0x0000003BU}, /* RGIDW_MODID[319]:SYSRAM10 */ + [304] = {0xFD442534U, 0x0000003BU}, /* RGIDW_MODID[320]:RTDM3P */ + [305] = {0xFD442538U, 0x00000003U}, /* RGIDW_MODID[321]:SYSRAM00 */ + [306] = {0xFD44253CU, 0x0000002EU}, /* RGIDW_MODID[322]:TSIPL0 */ + [307] = {0xFD442540U, 0x0000002EU}, /* RGIDW_MODID[323]:TSIPL1 */ + [308] = {0xFD442544U, 0x0000002EU}, /* RGIDW_MODID[324]:TSIPL2 */ + [309] = {0xFD442548U, 0x0000002EU}, /* RGIDW_MODID[325]:TSIPL3 */ + [310] = {0xFD44254CU, 0x0000002EU}, /* RGIDW_MODID[326]:TSIPL4 */ + [311] = {0xFD442550U, 0x0000002EU}, /* RGIDW_MODID[327]:TSIPL5 */ + [312] = {0xFD442554U, 0x0000002EU}, /* RGIDW_MODID[328]:TSIPL6 */ + [313] = {0xFD442558U, 0x0000002EU}, /* RGIDW_MODID[329]:TSIPL7 */ + [314] = {0xFD44255CU, 0x0000002EU}, /* RGIDW_MODID[330]:WCRC0 */ + [315] = {0xFD442560U, 0x0000002EU}, /* RGIDW_MODID[331]:WCRC1 */ + [316] = {0xFD442564U, 0x0000002EU}, /* RGIDW_MODID[332]:WCRC2 */ + [317] = {0xFD442568U, 0x0000002EU}, /* RGIDW_MODID[333]:WCRC3 */ + [318] = {0xFD442574U, 0x0000000CU}, /* RGIDW_MODID[334]:TSIP0 */ + [319] = {0xFD442578U, 0x0000000CU}, /* RGIDW_MODID[335]:TSIP1 */ + [320] = {0xFD44257CU, 0x0000000CU}, /* RGIDW_MODID[336]:TSIP2 */ + [321] = {0xFD442580U, 0x0000002EU}, /* RGIDW_MODID[337]:MFI11 */ + [322] = {0xFD442584U, 0x00000000U}, /* RGIDW_MODID[338]:MFI12 */ + [323] = {0xFD442588U, 0x00000000U}, /* RGIDW_MODID[339]:MFI13 */ + [324] = {0xFD44258CU, 0x00000000U}, /* RGIDW_MODID[340]:MFI14 */ + [325] = {0xFD442590U, 0x0000000CU}, /* RGIDW_MODID[341]:IPMMURT001 */ + [326] = {0xFD442594U, 0x0000000CU}, /* RGIDW_MODID[342]:IPMMURT010 */ + [327] = {0xFD442598U, 0x0000000CU}, /* RGIDW_MODID[343]:IPMMURT011 */ + [328] = {0xFD44259CU, 0x0000000CU}, /* RGIDW_MODID[344]:IPMMURT012 */ + [329] = {0xFD4425A0U, 0x0000000CU}, /* RGIDW_MODID[345]:IPMMURT013 */ + [330] = {0xFD4425A4U, 0x0000000CU}, /* RGIDW_MODID[346]:IPMMURT014 */ + [331] = {0xFD4425A8U, 0x0000000CU}, /* RGIDW_MODID[347]:IPMMURT015 */ + [332] = {0xFD4425ACU, 0x0000000CU}, /* RGIDW_MODID[348]:IPMMURT002 */ + [333] = {0xFD4425B0U, 0x0000000CU}, /* RGIDW_MODID[349]:IPMMURT003 */ + [334] = {0xFD4425B4U, 0x0000000CU}, /* RGIDW_MODID[350]:IPMMURT004 */ + [335] = {0xFD4425B8U, 0x0000000CU}, /* RGIDW_MODID[351]:IPMMURT005 */ + [336] = {0xFD4425BCU, 0x0000000CU}, /* RGIDW_MODID[352]:IPMMURT006 */ + [337] = {0xFD4425C0U, 0x0000000CU}, /* RGIDW_MODID[353]:IPMMURT007 */ + [338] = {0xFD4425C4U, 0x0000000CU}, /* RGIDW_MODID[354]:IPMMURT008 */ + [339] = {0xFD4425C8U, 0x0000000CU}, /* RGIDW_MODID[355]:IPMMURT009 */ + [340] = {0xFD4425CCU, 0x0000000CU}, /* RGIDW_MODID[356]:IPMMURT101 */ + [341] = {0xFD4425D0U, 0x0000000CU}, /* RGIDW_MODID[357]:IPMMURT110 */ + [342] = {0xFD4425D4U, 0x0000000CU}, /* RGIDW_MODID[358]:IPMMURT111 */ + [343] = {0xFD4425D8U, 0x0000000CU}, /* RGIDW_MODID[359]:IPMMURT112 */ + [344] = {0xFD4425DCU, 0x0000000CU}, /* RGIDW_MODID[360]:IPMMURT113 */ + [345] = {0xFD4425E0U, 0x0000000CU}, /* RGIDW_MODID[361]:IPMMURT114 */ + [346] = {0xFD4425E4U, 0x0000000CU}, /* RGIDW_MODID[362]:IPMMURT115 */ + [347] = {0xFD4425E8U, 0x0000000CU}, /* RGIDW_MODID[363]:IPMMURT102 */ + [348] = {0xFD4425ECU, 0x0000000CU}, /* RGIDW_MODID[364]:IPMMURT103 */ + [349] = {0xFD4425F0U, 0x0000000CU}, /* RGIDW_MODID[365]:IPMMURT104 */ + [350] = {0xFD4425F4U, 0x0000000CU}, /* RGIDW_MODID[366]:IPMMURT105 */ + [351] = {0xFD4425F8U, 0x0000000CU}, /* RGIDW_MODID[367]:IPMMURT106 */ + [352] = {0xFD4425FCU, 0x0000000CU}, /* RGIDW_MODID[368]:IPMMURT107 */ + [353] = {0xFD442600U, 0x0000003BU}, /* RGIDW_MODID[369]:RTDM000 */ + [354] = {0xFD442604U, 0x0000003BU}, /* RGIDW_MODID[370]:RTDM001 */ + [355] = {0xFD442608U, 0x0000003BU}, /* RGIDW_MODID[371]:RTDM010 */ + [356] = {0xFD44260CU, 0x0000003BU}, /* RGIDW_MODID[372]:RTDM011 */ + [357] = {0xFD442610U, 0x0000003BU}, /* RGIDW_MODID[373]:RTDM012 */ + [358] = {0xFD442614U, 0x0000003BU}, /* RGIDW_MODID[374]:RTDM013 */ + [359] = {0xFD442618U, 0x0000003BU}, /* RGIDW_MODID[375]:RTDM014 */ + [360] = {0xFD44261CU, 0x0000003BU}, /* RGIDW_MODID[376]:RTDM015 */ + [361] = {0xFD442620U, 0x0000003BU}, /* RGIDW_MODID[377]:RTDM002 */ + [362] = {0xFD442624U, 0x0000003BU}, /* RGIDW_MODID[378]:RTDM003 */ + [363] = {0xFD442628U, 0x0000003BU}, /* RGIDW_MODID[379]:RTDM004 */ + [364] = {0xFD44262CU, 0x0000003BU}, /* RGIDW_MODID[380]:RTDM005 */ + [365] = {0xFD442630U, 0x0000003BU}, /* RGIDW_MODID[381]:RTDM006 */ + [366] = {0xFD442634U, 0x0000003BU}, /* RGIDW_MODID[382]:RTDM007 */ + [367] = {0xFD442638U, 0x0000003BU}, /* RGIDW_MODID[383]:RTDM008 */ + [368] = {0xFD44263CU, 0x0000003BU}, /* RGIDW_MODID[384]:RTDM009 */ + [369] = {0xFD442640U, 0x0000003BU}, /* RGIDW_MODID[385]:RTDM100 */ + [370] = {0xFD442644U, 0x0000003BU}, /* RGIDW_MODID[386]:RTDM101 */ + [371] = {0xFD442648U, 0x0000003BU}, /* RGIDW_MODID[387]:RTDM110 */ + [372] = {0xFD44264CU, 0x0000003BU}, /* RGIDW_MODID[388]:RTDM111 */ + [373] = {0xFD442650U, 0x0000003BU}, /* RGIDW_MODID[389]:RTDM112 */ + [374] = {0xFD442654U, 0x0000003BU}, /* RGIDW_MODID[390]:RTDM113 */ + [375] = {0xFD442658U, 0x0000003BU}, /* RGIDW_MODID[391]:RTDM114 */ + [376] = {0xFD44265CU, 0x0000003BU}, /* RGIDW_MODID[392]:RTDM115 */ + [377] = {0xFD442660U, 0x0000003BU}, /* RGIDW_MODID[393]:RTDM102 */ + [378] = {0xFD442664U, 0x0000003BU}, /* RGIDW_MODID[394]:RTDM103 */ + [379] = {0xFD442668U, 0x0000003BU}, /* RGIDW_MODID[395]:RTDM104 */ + [380] = {0xFD44266CU, 0x0000003BU}, /* RGIDW_MODID[396]:RTDM105 */ + [381] = {0xFD442670U, 0x0000003BU}, /* RGIDW_MODID[397]:RTDM106 */ + [382] = {0xFD442674U, 0x0000003BU}, /* RGIDW_MODID[398]:RTDM107 */ + [383] = {0xFD442678U, 0x0000003BU}, /* RGIDW_MODID[399]:RTDM108 */ + [384] = {0xFD44267CU, 0x0000003BU}, /* RGIDW_MODID[400]:RTDM109 */ + [385] = {0xFD442680U, 0x0000003BU}, /* RGIDW_MODID[401]:RTDM200 */ + [386] = {0xFD442684U, 0x0000003BU}, /* RGIDW_MODID[402]:RTDM201 */ + [387] = {0xFD442688U, 0x0000003BU}, /* RGIDW_MODID[403]:RTDM210 */ + [388] = {0xFD44268CU, 0x0000003BU}, /* RGIDW_MODID[404]:RTDM211 */ + [389] = {0xFD442690U, 0x0000003BU}, /* RGIDW_MODID[405]:RTDM212 */ + [390] = {0xFD442694U, 0x0000003BU}, /* RGIDW_MODID[406]:RTDM213 */ + [391] = {0xFD442698U, 0x0000003BU}, /* RGIDW_MODID[407]:RTDM214 */ + [392] = {0xFD44269CU, 0x0000003BU}, /* RGIDW_MODID[408]:RTDM215 */ + [393] = {0xFD4426A0U, 0x0000003BU}, /* RGIDW_MODID[409]:RTDM202 */ + [394] = {0xFD4426A4U, 0x0000003BU}, /* RGIDW_MODID[410]:RTDM203 */ + [395] = {0xFD4426A8U, 0x0000003BU}, /* RGIDW_MODID[411]:RTDM204 */ + [396] = {0xFD4426ACU, 0x0000003BU}, /* RGIDW_MODID[412]:RTDM205 */ + [397] = {0xFD4426B0U, 0x0000003BU}, /* RGIDW_MODID[413]:RTDM206 */ + [398] = {0xFD4426B4U, 0x0000003BU}, /* RGIDW_MODID[414]:RTDM207 */ + [399] = {0xFD4426B8U, 0x0000003BU}, /* RGIDW_MODID[415]:RTDM208 */ + [400] = {0xFD4426BCU, 0x0000003BU}, /* RGIDW_MODID[416]:RTDM209 */ + [401] = {0xFD4426C0U, 0x0000003BU}, /* RGIDW_MODID[417]:RTDM300 */ + [402] = {0xFD4426C4U, 0x0000003BU}, /* RGIDW_MODID[418]:RTDM301 */ + [403] = {0xFD4426C8U, 0x0000003BU}, /* RGIDW_MODID[419]:RTDM310 */ + [404] = {0xFD4426CCU, 0x0000003BU}, /* RGIDW_MODID[420]:RTDM311 */ + [405] = {0xFD4426D0U, 0x0000003BU}, /* RGIDW_MODID[421]:RTDM312 */ + [406] = {0xFD4426D4U, 0x0000003BU}, /* RGIDW_MODID[422]:RTDM313 */ + [407] = {0xFD4426D8U, 0x0000003BU}, /* RGIDW_MODID[423]:RTDM314 */ + [408] = {0xFD4426DCU, 0x0000003BU}, /* RGIDW_MODID[424]:RTDM315 */ + [409] = {0xFD4426E0U, 0x0000003BU}, /* RGIDW_MODID[425]:RTDM302 */ + [410] = {0xFD4426E4U, 0x0000003BU}, /* RGIDW_MODID[426]:RTDM303 */ + [411] = {0xFD4426E8U, 0x0000003BU}, /* RGIDW_MODID[427]:RTDM304 */ + [412] = {0xFD4426ECU, 0x0000003BU}, /* RGIDW_MODID[428]:RTDM305 */ + [413] = {0xFD4426F0U, 0x0000003BU}, /* RGIDW_MODID[429]:RTDM306 */ + [414] = {0xFD4426F4U, 0x0000003BU}, /* RGIDW_MODID[430]:RTDM307 */ + [415] = {0xFD4426F8U, 0x0000003BU}, /* RGIDW_MODID[431]:RTDM308 */ + [416] = {0xFD4426FCU, 0x0000003BU}, /* RGIDW_MODID[432]:RTDM309 */ + [417] = {0xFD442700U, 0x0000000CU}, /* RGIDW_MODID[433]:IPMMURT108 */ + [418] = {0xFD442704U, 0x0000000CU}, /* RGIDW_MODID[434]:IPMMURT109 */ + [419] = {0xFD442708U, 0x00000011U}, /* RGIDW_MODID[435]:SYSRAM01 */ + [420] = {0xFD44270CU, 0x0000003BU}, /* RGIDW_MODID[436]:SYSRAM02 */ + [421] = {0xFD442710U, 0x00000011U}, /* RGIDW_MODID[437]:SYSRAM03 */ + [422] = {0xFD442714U, 0x00000011U}, /* RGIDW_MODID[438]:SYSRAM04 */ + [423] = {0xFD442718U, 0x00000011U}, /* RGIDW_MODID[439]:SYSRAM05 */ + [424] = {0xFD44271CU, 0x00000011U}, /* RGIDW_MODID[440]:SYSRAM06 */ + [425] = {0xFD442720U, 0x00000000U}, /* RGIDW_MODID[441]:SYSRAM07 */ + [426] = {0xFD442724U, 0x0000003BU}, /* RGIDW_MODID[442]:SYSRAM11 */ + [427] = {0xFD442728U, 0x0000002AU}, /* RGIDW_MODID[443]:SYSRAM12 */ + [428] = {0xFD44272CU, 0x0000003BU}, /* RGIDW_MODID[444]:SYSRAM13 */ + [429] = {0xFD442730U, 0x0000003BU}, /* RGIDW_MODID[445]:SYSRAM14 */ + [430] = {0xFD442734U, 0x0000003BU}, /* RGIDW_MODID[446]:SYSRAM15 */ + [431] = {0xFD442738U, 0x0000003BU}, /* RGIDW_MODID[447]:SYSRAM16 */ + [432] = {0xFD44273CU, 0x00000000U}, /* RGIDW_MODID[448]:SYSRAM17 */ + [433] = {0xFD442760U, 0x00000022U}, /* RGIDW_MODID[449]:BKBUF */ + [434] = {0xFD44276CU, 0x0000003FU}, /* RGIDW_MODID[450]:MCU */ + [435] = {0xFF862400U, 0x00000022U}, /* RGIDW_MODID[451]:ARSC0 */ + /* After setting */ /* RGIDW_MODID[452]:ARSC1 */ + /* After setting */ /* RGIDW_MODID[453]:ARSC2 */ + [436] = {0xFF86240CU, 0x00000011U}, /* RGIDW_MODID[454]:ARSC3 */ + [437] = {0xFF862410U, 0x00000022U}, /* RGIDW_MODID[455]:ARSC4 */ + [438] = {0xFF862414U, 0x00000011U}, /* RGIDW_MODID[456]:ARSC5 */ + [439] = {0xFF862418U, 0x00000022U}, /* RGIDW_MODID[457]:ARSC6 */ + [440] = {0xFF86241CU, 0x00000022U}, /* RGIDW_MODID[458]:ARSC7 */ + [441] = {0xFF862420U, 0x00000000U}, /* RGIDW_MODID[459]:ARSC8 */ + [442] = {0xFF862424U, 0x00000022U}, /* RGIDW_MODID[460]:ARSTM0 */ + /* After setting */ /* RGIDW_MODID[461]:ARSTM1 */ + [443] = {0xFF862430U, 0x0000002EU}, /* RGIDW_MODID[462]:AXIFBABUSTOP0 */ + [444] = {0xFF862434U, 0x0000002EU}, /* RGIDW_MODID[463]:AXIFBABUSTOP1 */ + /* After setting */ /* RGIDW_MODID[464]:ARSTM2 */ + [445] = {0xFF86243CU, 0x00000011U}, /* RGIDW_MODID[465]:ARSTM3 */ + [446] = {0xFF862440U, 0x00000022U}, /* RGIDW_MODID[466]:ARSTM4 */ + [447] = {0xFF862444U, 0x00000011U}, /* RGIDW_MODID[467]:ARSTM5 */ + [448] = {0xFF862448U, 0x00000022U}, /* RGIDW_MODID[468]:ARSTM6 */ + [449] = {0xFF86244CU, 0x00000022U}, /* RGIDW_MODID[469]:ARSTM7 */ + [450] = {0xFF862450U, 0x00000000U}, /* RGIDW_MODID[470]:ARSTM8 */ + [451] = {0xFF862454U, 0x0000003BU}, /* RGIDW_MODID[471]:ECMTOP */ + [452] = {0xFF862458U, 0x0000002EU}, /* RGIDW_MODID[472]:FBA */ + [453] = {0xFF86245CU, 0x0000002EU}, /* RGIDW_MODID[473]:FBC */ + [454] = {0xFF862460U, 0x0000000CU}, /* RGIDW_MODID[474]:AXICCI00 */ + [455] = {0xFF862464U, 0x0000000CU}, /* RGIDW_MODID[475]:AXICCI01 */ + [456] = {0xFF862468U, 0x0000000CU}, /* RGIDW_MODID[476]:AXICCI10 */ + [457] = {0xFF86246CU, 0x0000000CU}, /* RGIDW_MODID[477]:AXICCI11 */ + [458] = {0xFF862470U, 0x0000000CU}, /* RGIDW_MODID[478]:AXICCI12 */ + [459] = {0xFF862474U, 0x0000000CU}, /* RGIDW_MODID[479]:AXICCI13 */ + [460] = {0xFF862478U, 0x0000000CU}, /* RGIDW_MODID[480]:AXICCI14 */ + [461] = {0xFF86247CU, 0x0000000CU}, /* RGIDW_MODID[481]:AXICCI15 */ + [462] = {0xFF862480U, 0x0000000CU}, /* RGIDW_MODID[482]:AXICCI2 */ + [463] = {0xFF862484U, 0x0000000CU}, /* RGIDW_MODID[483]:AXICCI3 */ + [464] = {0xFF862488U, 0x0000000CU}, /* RGIDW_MODID[484]:AXICCI4 */ + [465] = {0xFF86248CU, 0x0000000CU}, /* RGIDW_MODID[485]:AXICCI5 */ + [466] = {0xFF862490U, 0x0000000CU}, /* RGIDW_MODID[486]:AXICCI6 */ + [467] = {0xFF862494U, 0x0000000CU}, /* RGIDW_MODID[487]:AXICCI7 */ + [468] = {0xFF862498U, 0x0000000CU}, /* RGIDW_MODID[488]:AXICCI8 */ + [469] = {0xFF86249CU, 0x0000003BU}, /* RGIDW_MODID[489]:AXICCI9 */ + [470] = {0xFF8624A0U, 0x0000003FU}, /* RGIDW_MODID[490]:ECMSTM */ + [471] = {0xFCB82414U, 0x0000002EU}, /* RGIDW_MODID[491]:DMAI2C0 */ + [472] = {0xFCB82418U, 0x0000002EU}, /* RGIDW_MODID[492]:DMAI2C1 */ + [473] = {0xFCB8241CU, 0x0000002EU}, /* RGIDW_MODID[493]:DMAI2C2 */ + [474] = {0xFCB82420U, 0x0000002EU}, /* RGIDW_MODID[494]:DMAI2C3 */ + [475] = {0xFCB82424U, 0x0000002EU}, /* RGIDW_MODID[495]:DMAI2C4 */ + [476] = {0xFCB82428U, 0x0000002EU}, /* RGIDW_MODID[496]:DMAI2C5 */ + [477] = {0xFDDC2400U, 0x00000000U}, /* RGIDW_MODID[497]:ARMM */ + /* After setting */ /* RGIDW_MODID[498]:AXIARNMM */ + [478] = {0xFDDC2408U, 0x00000022U}, /* RGIDW_MODID[499]:ARSM0 */ + /* After setting */ /* RGIDW_MODID[500]:ARSM1 */ + /* After setting */ /* RGIDW_MODID[501]:ARSM2 */ + [479] = {0xFDDC2414U, 0x0000003FU}, /* RGIDW_MODID[502]:AXIQOS0 */ + [480] = {0xFDDC2418U, 0x0000003FU}, /* RGIDW_MODID[503]:AXIQOS1 */ + [481] = {0xFDDC241CU, 0x0000003FU}, /* RGIDW_MODID[504]:AXIQOS2 */ + [482] = {0xFDDC2420U, 0x0000003FU}, /* RGIDW_MODID[505]:AXIQOS3 */ + [483] = {0xFDDC2424U, 0x0000003FU}, /* RGIDW_MODID[506]:AXIQOS4 */ + [484] = {0xFDDC2430U, 0x0000003FU}, /* RGIDW_MODID[507]:AXIQOS5 */ + [485] = {0xFDDC2434U, 0x00000011U}, /* RGIDW_MODID[508]:ARSM3 */ + [486] = {0xFDDC2438U, 0x00000022U}, /* RGIDW_MODID[509]:ARSM4 */ + [487] = {0xFDDC243CU, 0x00000011U}, /* RGIDW_MODID[510]:ARSM5 */ + [488] = {0xFDDC2440U, 0x00000022U}, /* RGIDW_MODID[511]:ARSM6 */ + [489] = {0xFDDC2444U, 0x00000022U}, /* RGIDW_MODID[512]:ARSM7 */ + [490] = {0xFDDC2448U, 0x00000000U}, /* RGIDW_MODID[513]:ARSM8 */ + [491] = {0xFDDC244CU, 0x0000003FU}, /* RGIDW_MODID[514]:AXMM0 */ + [492] = {0xFDDC2450U, 0x0000003FU}, /* RGIDW_MODID[515]:AXMM1 */ + [493] = {0xFDDC2454U, 0x00000000U}, /* RGIDW_MODID[516]:AXMMPMON */ + [494] = {0xFDDC2458U, 0x0000002AU}, /* RGIDW_MODID[517]:CKMMM */ + [495] = {0xFDDC245CU, 0x0000003BU}, /* RGIDW_MODID[518]:ECMMM */ + [496] = {0xFDDC2468U, 0x0000002EU}, /* RGIDW_MODID[519]:FBAMM */ + [497] = {0xFDDC246CU, 0x0000000CU}, /* RGIDW_MODID[520]:IPMMUMM00 */ + [498] = {0xFDDC2470U, 0x0000003FU}, /* RGIDW_MODID[521]:DBS00 */ + [499] = {0xFDDC2474U, 0x0000002AU}, /* RGIDW_MODID[522]:DBS01 */ + [500] = {0xFDDC2480U, 0x0000003FU}, /* RGIDW_MODID[523]:AXCIDBS */ + [501] = {0xFDDC249CU, 0x0000000CU}, /* RGIDW_MODID[524]:IPMMUMM01 */ + [502] = {0xFDDC24A0U, 0x0000000CU}, /* RGIDW_MODID[525]:IPMMUMM10 */ + [503] = {0xFDDC24A4U, 0x0000000CU}, /* RGIDW_MODID[526]:IPMMUMM11 */ + [504] = {0xFDDC24A8U, 0x0000000CU}, /* RGIDW_MODID[527]:IPMMUMM12 */ + [505] = {0xFDDC24ACU, 0x0000000CU}, /* RGIDW_MODID[528]:IPMMUMM13 */ + [506] = {0xFDDC24B0U, 0x0000000CU}, /* RGIDW_MODID[529]:IPMMUMM14 */ + [507] = {0xFDDC24B4U, 0x0000000CU}, /* RGIDW_MODID[530]:IPMMUMM15 */ + [508] = {0xFDDC24B8U, 0x0000000CU}, /* RGIDW_MODID[531]:IPMMUMM02 */ + [509] = {0xFDDC24BCU, 0x0000000CU}, /* RGIDW_MODID[532]:IPMMUMM03 */ + [510] = {0xFDDC24C0U, 0x0000000CU}, /* RGIDW_MODID[533]:IPMMUMM04 */ + [511] = {0xFDDC24C4U, 0x0000000CU}, /* RGIDW_MODID[534]:IPMMUMM05 */ + [512] = {0xFDDC24C8U, 0x0000000CU}, /* RGIDW_MODID[535]:IPMMUMM06 */ + [513] = {0xFDDC24CCU, 0x0000000CU}, /* RGIDW_MODID[536]:IPMMUMM07 */ + [514] = {0xFDDC24D0U, 0x0000000CU}, /* RGIDW_MODID[537]:IPMMUMM08 */ + [515] = {0xFDDC24D4U, 0x0000000CU}, /* RGIDW_MODID[538]:IPMMUMM09 */ + [516] = {0xFCB52400U, 0x00000022U}, /* RGIDW_MODID[539]:ARSD00 */ + /* After setting */ /* RGIDW_MODID[540]:ARSD01 */ + /* After setting */ /* RGIDW_MODID[541]:ARSD02 */ + [517] = {0xFCB5240CU, 0x00000011U}, /* RGIDW_MODID[542]:ARSD03 */ + [518] = {0xFCB52410U, 0x00000022U}, /* RGIDW_MODID[543]:ARSD04 */ + [519] = {0xFCB52414U, 0x00000011U}, /* RGIDW_MODID[544]:ARSD05 */ + [520] = {0xFCB52418U, 0x00000022U}, /* RGIDW_MODID[545]:ARSD06 */ + [521] = {0xFCB52428U, 0x0000003FU}, /* RGIDW_MODID[546]:AXIRPC */ + [522] = {0xFCB5242CU, 0x0000003FU}, /* RGIDW_MODID[547]:AXISDHI0 */ + [523] = {0xFCB52430U, 0x00000022U}, /* RGIDW_MODID[548]:ARSD07 */ + [524] = {0xFCB52434U, 0x00000000U}, /* RGIDW_MODID[549]:ARSD07 */ + [525] = {0xFCB52438U, 0x00000022U}, /* RGIDW_MODID[550]:ARSP00 */ + /* After setting */ /* RGIDW_MODID[551]:ARSP01 */ + /* After setting */ /* RGIDW_MODID[552]:ARSP02 */ + [526] = {0xFCB52444U, 0x00000011U}, /* RGIDW_MODID[553]:ARSP03 */ + [527] = {0xFCB52448U, 0x00000022U}, /* RGIDW_MODID[554]:ARSP04 */ + [528] = {0xFCB5244CU, 0x00000011U}, /* RGIDW_MODID[555]:ARSP05 */ + [529] = {0xFCB52450U, 0x00000022U}, /* RGIDW_MODID[556]:ARSP06 */ + [530] = {0xFCB52454U, 0x00000022U}, /* RGIDW_MODID[557]:ARSP07 */ + [531] = {0xFCB52458U, 0x00000000U}, /* RGIDW_MODID[558]:ARSP08 */ + [532] = {0xFCB5245CU, 0x0000000CU}, /* RGIDW_MODID[559]:IPMMUDS001 */ + [533] = {0xFCB52460U, 0x0000002AU}, /* RGIDW_MODID[560]:CKMPER0 */ + [534] = {0xFCB52464U, 0x0000003BU}, /* RGIDW_MODID[561]:ECMPER0 */ + [535] = {0xFCB52468U, 0x0000002EU}, /* RGIDW_MODID[562]:FBAPER0 */ + [536] = {0xFCB5246CU, 0x0000002EU}, /* RGIDW_MODID[563]:FSO0 */ + [537] = {0xFCB52470U, 0x0000002EU}, /* RGIDW_MODID[564]:FSO1 */ + [538] = {0xFCB52474U, 0x0000002EU}, /* RGIDW_MODID[565]:FSO10 */ + [539] = {0xFCB52478U, 0x0000002EU}, /* RGIDW_MODID[566]:FSO2 */ + [540] = {0xFCB5247CU, 0x0000002EU}, /* RGIDW_MODID[567]:FSO3 */ + [541] = {0xFCB52480U, 0x0000002EU}, /* RGIDW_MODID[568]:FSO4 */ + [542] = {0xFCB52484U, 0x0000002EU}, /* RGIDW_MODID[569]:FSO5 */ + [543] = {0xFCB52488U, 0x0000002EU}, /* RGIDW_MODID[570]:FSO6 */ + [544] = {0xFCB5248CU, 0x0000002EU}, /* RGIDW_MODID[571]:FSO7 */ + [545] = {0xFCB52490U, 0x0000002EU}, /* RGIDW_MODID[572]:FSO8 */ + [546] = {0xFCB52494U, 0x0000002EU}, /* RGIDW_MODID[573]:FSO9 */ + [547] = {0xFCB5249CU, 0x0000003BU}, /* RGIDW_MODID[574]:ECMSD0 */ + [548] = {0xFCB524A0U, 0x0000000CU}, /* RGIDW_MODID[575]:IPMMUDS010 */ + [549] = {0xFCB524A4U, 0x0000000CU}, /* RGIDW_MODID[576]:IPMMUDS011 */ + [550] = {0xFCB524A8U, 0x0000002EU}, /* RGIDW_MODID[577]:I2C0 */ + [551] = {0xFCB524ACU, 0x0000002EU}, /* RGIDW_MODID[578]:I2C1 */ + [552] = {0xFCB524B0U, 0x0000002EU}, /* RGIDW_MODID[579]:I2C2 */ + [553] = {0xFCB524B4U, 0x0000002EU}, /* RGIDW_MODID[580]:I2C3 */ + [554] = {0xFCB524B8U, 0x0000002EU}, /* RGIDW_MODID[581]:I2C4 */ + [555] = {0xFCB524BCU, 0x0000002EU}, /* RGIDW_MODID[582]:I2C5 */ + [556] = {0xFCB524C0U, 0x0000000CU}, /* RGIDW_MODID[583]:IPMMUDS012 */ + [557] = {0xFCB524C8U, 0x0000000CU}, /* RGIDW_MODID[584]:IPMMUDS000 */ + [558] = {0xFCB524CCU, 0x0000000CU}, /* RGIDW_MODID[585]:IPMMUDS013 */ + [559] = {0xFCB524D0U, 0x0000000CU}, /* RGIDW_MODID[586]:IPMMUDS014 */ + [560] = {0xFCB524D4U, 0x0000000CU}, /* RGIDW_MODID[587]:IPMMUDS015 */ + [561] = {0xFCB524D8U, 0x0000000CU}, /* RGIDW_MODID[588]:IPMMUDS002 */ + [562] = {0xFCB524DCU, 0x0000000CU}, /* RGIDW_MODID[589]:IPMMUDS003 */ + [563] = {0xFCB524E0U, 0x0000000CU}, /* RGIDW_MODID[590]:IPMMUDS004 */ + [564] = {0xFCB524E4U, 0x0000000CU}, /* RGIDW_MODID[591]:IPMMUDS005 */ + [565] = {0xFCB524ECU, 0x0000000CU}, /* RGIDW_MODID[592]:IPMMUDS006 */ + [566] = {0xFCB524F0U, 0x0000000CU}, /* RGIDW_MODID[593]:IPMMUDS007 */ + [567] = {0xFCB524F4U, 0x0000000CU}, /* RGIDW_MODID[594]:SYDM1P */ + [568] = {0xFCB524F8U, 0x0000000CU}, /* RGIDW_MODID[595]:IPMMUDS008 */ + [569] = {0xFCB524FCU, 0x0000000CU}, /* RGIDW_MODID[596]:SYDM2P */ + [570] = {0xFCB52500U, 0x0000000CU}, /* RGIDW_MODID[597]:IPMMUDS009 */ + [571] = {0xFCB52640U, 0x0000000CU}, /* RGIDW_MODID[598]:SYDM100 */ + [572] = {0xFCB52644U, 0x0000000CU}, /* RGIDW_MODID[599]:SYDM101 */ + [573] = {0xFCB52648U, 0x0000000CU}, /* RGIDW_MODID[600]:SYDM110 */ + [574] = {0xFCB5264CU, 0x0000000CU}, /* RGIDW_MODID[601]:SYDM111 */ + [575] = {0xFCB52650U, 0x0000000CU}, /* RGIDW_MODID[602]:SYDM112 */ + [576] = {0xFCB52654U, 0x0000000CU}, /* RGIDW_MODID[603]:SYDM113 */ + [577] = {0xFCB52658U, 0x0000000CU}, /* RGIDW_MODID[604]:SYDM114 */ + [578] = {0xFCB5265CU, 0x0000000CU}, /* RGIDW_MODID[605]:SYDM115 */ + [579] = {0xFCB52660U, 0x0000000CU}, /* RGIDW_MODID[606]:SYDM102 */ + [580] = {0xFCB52664U, 0x0000000CU}, /* RGIDW_MODID[607]:SYDM103 */ + [581] = {0xFCB52668U, 0x0000000CU}, /* RGIDW_MODID[608]:SYDM104 */ + [582] = {0xFCB5266CU, 0x0000000CU}, /* RGIDW_MODID[609]:SYDM105 */ + [583] = {0xFCB52670U, 0x0000000CU}, /* RGIDW_MODID[610]:SYDM106 */ + [584] = {0xFCB52674U, 0x0000000CU}, /* RGIDW_MODID[611]:SYDM107 */ + [585] = {0xFCB52678U, 0x0000000CU}, /* RGIDW_MODID[612]:SYDM108 */ + [586] = {0xFCB5267CU, 0x0000000CU}, /* RGIDW_MODID[613]:SYDM109 */ + [587] = {0xFCB52680U, 0x0000000CU}, /* RGIDW_MODID[614]:SYDM200 */ + [588] = {0xFCB52684U, 0x0000000CU}, /* RGIDW_MODID[615]:SYDM201 */ + [589] = {0xFCB52688U, 0x0000000CU}, /* RGIDW_MODID[616]:SYDM210 */ + [590] = {0xFCB5268CU, 0x0000000CU}, /* RGIDW_MODID[617]:SYDM211 */ + [591] = {0xFCB52690U, 0x0000000CU}, /* RGIDW_MODID[618]:SYDM212 */ + [592] = {0xFCB52694U, 0x0000000CU}, /* RGIDW_MODID[619]:SYDM213 */ + [593] = {0xFCB52698U, 0x0000000CU}, /* RGIDW_MODID[620]:SYDM214 */ + [594] = {0xFCB5269CU, 0x0000000CU}, /* RGIDW_MODID[621]:SYDM215 */ + [595] = {0xFCB526A0U, 0x0000000CU}, /* RGIDW_MODID[622]:SYDM202 */ + [596] = {0xFCB526A4U, 0x0000000CU}, /* RGIDW_MODID[623]:SYDM203 */ + [597] = {0xFCB526A8U, 0x0000000CU}, /* RGIDW_MODID[624]:SYDM204 */ + [598] = {0xFCB526ACU, 0x0000000CU}, /* RGIDW_MODID[625]:SYDM205 */ + [599] = {0xFCB526B0U, 0x0000000CU}, /* RGIDW_MODID[626]:SYDM206 */ + [600] = {0xFCB526B4U, 0x0000000CU}, /* RGIDW_MODID[627]:SYDM207 */ + [601] = {0xFCB526B8U, 0x0000000CU}, /* RGIDW_MODID[628]:SYDM208 */ + [602] = {0xFCB526BCU, 0x0000000CU}, /* RGIDW_MODID[629]:SYDM209 */ + [604] = {0xFDDB969CU, 0x00000000U}, /* RGIDW_MODID[630]:ARCC */ + [603] = {0xFDDB96B0U, 0x00000000U}, /* RGIDW_MODID[631]:ARRTRAM */ + [605] = {0xFCB52424U, 0x00000000U}, /* RGIDW_MODID[632]:RSV0 */ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_sec_tbl" +const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[] = { + [0] = {0xFD483400U, 0x00000000U}, /* RGIDSEC_MODID[0]:ARMGC0 */ + [1] = {0xFD483404U, 0x00000002U}, /* RGIDSEC_MODID[1]:ARMGC1 */ + [2] = {0xFD483408U, 0x00000002U}, /* RGIDSEC_MODID[2]:ARMGC2 */ + [3] = {0xFD48340CU, 0x00000002U}, /* RGIDSEC_MODID[3]:ARRT00 */ + [4] = {0xFD483410U, 0x00000002U}, /* RGIDSEC_MODID[4]:ARRT01 */ + [5] = {0xFD483414U, 0x00000002U}, /* RGIDSEC_MODID[5]:ARRT02 */ + [6] = {0xFD483418U, 0x00000002U}, /* RGIDSEC_MODID[6]:ARRT03 */ + [7] = {0xFD48341CU, 0x00000002U}, /* RGIDSEC_MODID[7]:ARRT04 */ + [8] = {0xFD483420U, 0x00000002U}, /* RGIDSEC_MODID[8]:ARRT05 */ + [9] = {0xFD483424U, 0x00000002U}, /* RGIDSEC_MODID[9]:ARRT06 */ + [10] = {0xFD483428U, 0x00000002U}, /* RGIDSEC_MODID[10]:ARRT07 */ + [11] = {0xFD48342CU, 0x00000002U}, /* RGIDSEC_MODID[11]:ARRT08 */ + [12] = {0xFD483430U, 0x00000000U}, /* RGIDSEC_MODID[12]:LIFEC0 */ + [13] = {0xFD483434U, 0x00000002U}, /* RGIDSEC_MODID[13]:SWDT */ + [14] = {0xFD483438U, 0x00000002U}, /* RGIDSEC_MODID[14]:TMU0 */ + [15] = {0xFD48343CU, 0x00000002U}, /* RGIDSEC_MODID[15]:WDT */ + [16] = {0xFD483440U, 0x00000002U}, /* RGIDSEC_MODID[16]:WWDT0 */ + [17] = {0xFD483444U, 0x00000002U}, /* RGIDSEC_MODID[17]:WWDT1 */ + [18] = {0xFD483448U, 0x00000002U}, /* RGIDSEC_MODID[18]:WWDT2 */ + [19] = {0xFD48344CU, 0x00000002U}, /* RGIDSEC_MODID[19]:WWDT3 */ + [20] = {0xFD483450U, 0x00000002U}, /* RGIDSEC_MODID[20]:WWDT4 */ + [21] = {0xFD483454U, 0x00000002U}, /* RGIDSEC_MODID[21]:WWDT5 */ + [22] = {0xFD483458U, 0x00000002U}, /* RGIDSEC_MODID[22]:WWDT6 */ + [23] = {0xFD48345CU, 0x00000002U}, /* RGIDSEC_MODID[23]:WWDT7 */ + [24] = {0xFD483460U, 0x00000002U}, /* RGIDSEC_MODID[24]:WWDT8 */ + [25] = {0xFD483464U, 0x00000002U}, /* RGIDSEC_MODID[25]:WWDT9 */ + [26] = {0xFD483468U, 0x00000002U}, /* RGIDSEC_MODID[26]:ECMRT3 */ + [27] = {0xFDA03400U, 0x00000002U}, /* RGIDSEC_MODID[27]:ADVFSC */ + [28] = {0xFDA03404U, 0x00000002U}, /* RGIDSEC_MODID[28]:APMU0 */ + [29] = {0xFDA03408U, 0x00000002U}, /* RGIDSEC_MODID[29]:APMU1 */ + [30] = {0xFDA0340CU, 0x00000002U}, /* RGIDSEC_MODID[30]:APMU10 */ + [31] = {0xFDA03410U, 0x00000002U}, /* RGIDSEC_MODID[31]:APMU11 */ + [32] = {0xFDA03414U, 0x00000002U}, /* RGIDSEC_MODID[32]:APMU12 */ + [33] = {0xFDA03418U, 0x00000002U}, /* RGIDSEC_MODID[33]:APMU13 */ + [34] = {0xFDA0341CU, 0x00000002U}, /* RGIDSEC_MODID[34]:APMU14 */ + [35] = {0xFDA03420U, 0x00000002U}, /* RGIDSEC_MODID[35]:APMU15 */ + [36] = {0xFDA03424U, 0x00000002U}, /* RGIDSEC_MODID[36]:APMU2 */ + [37] = {0xFDA03428U, 0x00000002U}, /* RGIDSEC_MODID[37]:APMU3 */ + [38] = {0xFDA0342CU, 0x00000002U}, /* RGIDSEC_MODID[38]:APMU4 */ + [39] = {0xFDA03430U, 0x00000002U}, /* RGIDSEC_MODID[39]:APMU5 */ + [40] = {0xFDA03434U, 0x00000002U}, /* RGIDSEC_MODID[40]:APMU6 */ + [41] = {0xFDA03438U, 0x00000002U}, /* RGIDSEC_MODID[41]:APMU7 */ + [42] = {0xFDA0343CU, 0x00000002U}, /* RGIDSEC_MODID[42]:APMU8 */ + [43] = {0xFDA03440U, 0x00000002U}, /* RGIDSEC_MODID[43]:APMU9 */ + [44] = {0xFDA03444U, 0x00000002U}, /* RGIDSEC_MODID[44]:ARS00 */ + [45] = {0xFDA03448U, 0x00000002U}, /* RGIDSEC_MODID[45]:ARS01 */ + [46] = {0xFDA0344CU, 0x00000002U}, /* RGIDSEC_MODID[46]:ARS02 */ + [47] = {0xFDA03450U, 0x00000002U}, /* RGIDSEC_MODID[47]:ARS03 */ + [48] = {0xFDA03454U, 0x00000002U}, /* RGIDSEC_MODID[48]:ARS04 */ + [49] = {0xFDA03458U, 0x00000002U}, /* RGIDSEC_MODID[49]:ARS05 */ + [50] = {0xFDA0345CU, 0x00000002U}, /* RGIDSEC_MODID[50]:ARS06 */ + [51] = {0xFDA03460U, 0x00000002U}, /* RGIDSEC_MODID[51]:ARS07 */ + [52] = {0xFDA03464U, 0x00000002U}, /* RGIDSEC_MODID[52]:ARS08 */ + [53] = {0xFDA03468U, 0x00000002U}, /* RGIDSEC_MODID[53]:CMT0 */ + [54] = {0xFDA0346CU, 0x00000002U}, /* RGIDSEC_MODID[54]:CMT1 */ + [55] = {0xFDA03470U, 0x00000002U}, /* RGIDSEC_MODID[55]:CMT2 */ + [56] = {0xFDA03474U, 0x00000002U}, /* RGIDSEC_MODID[56]:CMT3 */ + [57] = {0xFDA03478U, 0x00000002U}, /* RGIDSEC_MODID[57]:CKM */ + [58] = {0xFDA0347CU, 0x00000002U}, /* RGIDSEC_MODID[58]:DBE */ + [59] = {0xFDA03480U, 0x00000002U}, /* RGIDSEC_MODID[59]:IRQC */ + [60] = {0xFDA03484U, 0x00000002U}, /* RGIDSEC_MODID[60]:ECMPS0 */ + [61] = {0xFDA0349CU, 0x00000002U}, /* RGIDSEC_MODID[61]:SCMT */ + [62] = {0xFDA034A8U, 0x00000002U}, /* RGIDSEC_MODID[62]:TSC1 */ + [63] = {0xFDA034ACU, 0x00000002U}, /* RGIDSEC_MODID[63]:TSC2 */ + [64] = {0xFDA034B0U, 0x00000002U}, /* RGIDSEC_MODID[64]:TSC3 */ + [65] = {0xFDA034B4U, 0x00000002U}, /* RGIDSEC_MODID[65]:TSC4 */ + [66] = {0xFDA034B8U, 0x00000002U}, /* RGIDSEC_MODID[66]:UCMT */ + [67] = {0xFDA03500U, 0x00000002U}, /* RGIDSEC_MODID[67]:CPG0 */ + [68] = {0xFDA03504U, 0x00000002U}, /* RGIDSEC_MODID[68]:CPG1 */ + [69] = {0xFDA03508U, 0x00000002U}, /* RGIDSEC_MODID[69]:CPG2 */ + [70] = {0xFDA0350CU, 0x00000002U}, /* RGIDSEC_MODID[70]:CPG3 */ + [71] = {0xFDA03510U, 0x00000002U}, /* RGIDSEC_MODID[71]:PFC00 */ + [72] = {0xFDA03514U, 0x00000002U}, /* RGIDSEC_MODID[72]:PFC01 */ + [73] = {0xFDA03518U, 0x00000002U}, /* RGIDSEC_MODID[73]:PFC02 */ + [74] = {0xFDA0351CU, 0x00000002U}, /* RGIDSEC_MODID[74]:PFC03 */ + [75] = {0xFDA03550U, 0x00000002U}, /* RGIDSEC_MODID[75]:PFCS0 */ + [76] = {0xFDA03554U, 0x00000002U}, /* RGIDSEC_MODID[76]:PFCS1 */ + [77] = {0xFDA03558U, 0x00000002U}, /* RGIDSEC_MODID[77]:PFCS2 */ + [78] = {0xFDA0355CU, 0x00000002U}, /* RGIDSEC_MODID[78]:PFCS3 */ + [79] = {0xFDA03560U, 0x00000002U}, /* RGIDSEC_MODID[79]:RESET0 */ + [80] = {0xFDA03564U, 0x00000002U}, /* RGIDSEC_MODID[80]:RESET1 */ + [81] = {0xFDA03568U, 0x00000002U}, /* RGIDSEC_MODID[81]:RESET2 */ + [82] = {0xFDA0356CU, 0x00000002U}, /* RGIDSEC_MODID[82]:RESET3 */ + [83] = {0xFDA03570U, 0x00000002U}, /* RGIDSEC_MODID[83]:SYS0 */ + [84] = {0xFDA03574U, 0x00000002U}, /* RGIDSEC_MODID[84]:SYS1 */ + [85] = {0xFDA03578U, 0x00000002U}, /* RGIDSEC_MODID[85]:SYS2 */ + [86] = {0xFDA0357CU, 0x00000002U}, /* RGIDSEC_MODID[86]:SYS3 */ + [87] = {0xFCB63400U, 0x00000002U}, /* RGIDSEC_MODID[87]:DMAMSI0 */ + [88] = {0xFCB63404U, 0x00000002U}, /* RGIDSEC_MODID[88]:DMAMSI1 */ + [89] = {0xFCB63408U, 0x00000002U}, /* RGIDSEC_MODID[89]:DMAMSI2 */ + [90] = {0xFCB6340CU, 0x00000002U}, /* RGIDSEC_MODID[90]:DMAMSI3 */ + [91] = {0xFCB63418U, 0x00000002U}, /* RGIDSEC_MODID[91]:ECMSP3 */ + [92] = {0xFCB63424U, 0x00000002U}, /* RGIDSEC_MODID[92]:ARSP30 */ + [93] = {0xFCB63428U, 0x00000002U}, /* RGIDSEC_MODID[93]:ARSP31 */ + [94] = {0xFCB6342CU, 0x00000002U}, /* RGIDSEC_MODID[94]:ARSP32 */ + [95] = {0xFCB63430U, 0x00000002U}, /* RGIDSEC_MODID[95]:ARSP33 */ + [96] = {0xFCB63434U, 0x00000002U}, /* RGIDSEC_MODID[96]:ARSP34 */ + [97] = {0xFCB63438U, 0x00000002U}, /* RGIDSEC_MODID[97]:ARSP35 */ + [98] = {0xFCB6343CU, 0x00000002U}, /* RGIDSEC_MODID[98]:ARSP36 */ + [99] = {0xFCB63440U, 0x00000002U}, /* RGIDSEC_MODID[99]:ARSP37 */ + [100] = {0xFCB63444U, 0x00000002U}, /* RGIDSEC_MODID[100]:ARSP38 */ + [101] = {0xFCB63448U, 0x00000002U}, /* RGIDSEC_MODID[101]:MSI0 */ + [102] = {0xFCB6344CU, 0x00000002U}, /* RGIDSEC_MODID[102]:MSI1 */ + [103] = {0xFCB63450U, 0x00000002U}, /* RGIDSEC_MODID[103]:MSI2 */ + [104] = {0xFCB63454U, 0x00000002U}, /* RGIDSEC_MODID[104]:MSI3 */ + [105] = {0xFCB93400U, 0x00000002U}, /* RGIDSEC_MODID[105]:ARSP40 */ + [106] = {0xFCB93404U, 0x00000002U}, /* RGIDSEC_MODID[106]:ARSP41 */ + [107] = {0xFCB93408U, 0x00000002U}, /* RGIDSEC_MODID[107]:ARSP42 */ + [108] = {0xFCB9340CU, 0x00000002U}, /* RGIDSEC_MODID[108]:ARSP43 */ + [109] = {0xFCB93410U, 0x00000002U}, /* RGIDSEC_MODID[109]:ARSP44 */ + [110] = {0xFCB93414U, 0x00000002U}, /* RGIDSEC_MODID[110]:ARSP45 */ + [111] = {0xFCB93418U, 0x00000002U}, /* RGIDSEC_MODID[111]:ARSP46 */ + [112] = {0xFCB9341CU, 0x00000002U}, /* RGIDSEC_MODID[112]:ARSP47 */ + [113] = {0xFCB93420U, 0x00000002U}, /* RGIDSEC_MODID[113]:ARSP48 */ + [114] = {0xFCB93424U, 0x00000002U}, /* RGIDSEC_MODID[114]:DMAHSCIF0 */ + [115] = {0xFCB93428U, 0x00000002U}, /* RGIDSEC_MODID[115]:DMAHSCIF1 */ + [116] = {0xFCB9342CU, 0x00000002U}, /* RGIDSEC_MODID[116]:DMAHSCIF2 */ + [117] = {0xFCB93430U, 0x00000002U}, /* RGIDSEC_MODID[117]:DMAHSCIF3 */ + [118] = {0xFCB93434U, 0x00000002U}, /* RGIDSEC_MODID[118]:DMASCIF0 */ + [119] = {0xFCB93438U, 0x00000002U}, /* RGIDSEC_MODID[119]:DMASCIF1 */ + [120] = {0xFCB9343CU, 0x00000002U}, /* RGIDSEC_MODID[120]:DMASCIF3 */ + [121] = {0xFCB93440U, 0x00000002U}, /* RGIDSEC_MODID[121]:DMASCIF4 */ + [122] = {0xFCB93444U, 0x00000002U}, /* RGIDSEC_MODID[122]:ECMSP4 */ + [123] = {0xFCB93448U, 0x00000002U}, /* RGIDSEC_MODID[123]:HSCIF0 */ + [124] = {0xFCB9344CU, 0x00000002U}, /* RGIDSEC_MODID[124]:HSCIF1 */ + [125] = {0xFCB93450U, 0x00000002U}, /* RGIDSEC_MODID[125]:HSCIF2 */ + [126] = {0xFCB93454U, 0x00000002U}, /* RGIDSEC_MODID[126]:HSCIF3 */ + [127] = {0xFCB93458U, 0x00000002U}, /* RGIDSEC_MODID[127]:SCIF0 */ + [128] = {0xFCB9345CU, 0x00000002U}, /* RGIDSEC_MODID[128]:SCIF1 */ + [129] = {0xFCB93460U, 0x00000002U}, /* RGIDSEC_MODID[129]:SCIF3 */ + [130] = {0xFCB93464U, 0x00000002U}, /* RGIDSEC_MODID[130]:SCIF4 */ + [131] = {0xFCB93468U, 0x00000002U}, /* RGIDSEC_MODID[131]:TMU1 */ + [132] = {0xFCB9346CU, 0x00000002U}, /* RGIDSEC_MODID[132]:TMU2 */ + [133] = {0xFCB93470U, 0x00000002U}, /* RGIDSEC_MODID[133]:TMU3 */ + [134] = {0xFCB93474U, 0x00000002U}, /* RGIDSEC_MODID[134]:TMU4 */ + [135] = {0xFCF83400U, 0x00000002U}, /* RGIDSEC_MODID[135]:CKMHSC */ + [136] = {0xFCF83404U, 0x00000002U}, /* RGIDSEC_MODID[136]:AXIPCI001 */ + [137] = {0xFCF83408U, 0x00000002U}, /* RGIDSEC_MODID[137]:AXIPCI002 */ + [138] = {0xFCF8340CU, 0x00000002U}, /* RGIDSEC_MODID[138]:AXIPCI003 */ + [139] = {0xFCF83410U, 0x00000002U}, /* RGIDSEC_MODID[139]:ETHPHY */ + [140] = {0xFCF83414U, 0x00000002U}, /* RGIDSEC_MODID[140]:AXIPCI005 */ + [141] = {0xFCF83418U, 0x00000002U}, /* RGIDSEC_MODID[141]:AXIPCI006 */ + [142] = {0xFCF8341CU, 0x00000002U}, /* RGIDSEC_MODID[142]:AXIPCI007 */ + [143] = {0xFCF83420U, 0x00000002U}, /* RGIDSEC_MODID[143]:AXIPCI008 */ + [144] = {0xFCF83424U, 0x00000002U}, /* RGIDSEC_MODID[144]:AXIPCI009 */ + [145] = {0xFCF83428U, 0x00000002U}, /* RGIDSEC_MODID[145]:AXIPCI010 */ + [146] = {0xFCF8342CU, 0x00000002U}, /* RGIDSEC_MODID[146]:AXIPCI011 */ + [147] = {0xFCF83430U, 0x00000002U}, /* RGIDSEC_MODID[147]:AXIPCI012 */ + [148] = {0xFCF83434U, 0x00000002U}, /* RGIDSEC_MODID[148]:AXIPCI013 */ + [149] = {0xFCF83438U, 0x00000002U}, /* RGIDSEC_MODID[149]:AXIPCI014 */ + [150] = {0xFCF8343CU, 0x00000002U}, /* RGIDSEC_MODID[150]:AXIPCI015 */ + [151] = {0xFCF83440U, 0x00000002U}, /* RGIDSEC_MODID[151]:AXIPCI100 */ + [152] = {0xFCF83444U, 0x00000002U}, /* RGIDSEC_MODID[152]:AXIPCI101 */ + [153] = {0xFCF83448U, 0x00000002U}, /* RGIDSEC_MODID[153]:AXIPCI102 */ + [154] = {0xFCF8344CU, 0x00000002U}, /* RGIDSEC_MODID[154]:AXIPCI103 */ + [155] = {0xFCF83450U, 0x00000002U}, /* RGIDSEC_MODID[155]:AXIPCI104 */ + [156] = {0xFCF83454U, 0x00000002U}, /* RGIDSEC_MODID[156]:AXIPCI105 */ + [157] = {0xFCF83458U, 0x00000002U}, /* RGIDSEC_MODID[157]:AXIPCI106 */ + [158] = {0xFCF8345CU, 0x00000002U}, /* RGIDSEC_MODID[158]:AXIPCI107 */ + [159] = {0xFCF83460U, 0x00000002U}, /* RGIDSEC_MODID[159]:AXIPCI108 */ + [160] = {0xFCF83464U, 0x00000002U}, /* RGIDSEC_MODID[160]:AXIPCI109 */ + [161] = {0xFCF83468U, 0x00000002U}, /* RGIDSEC_MODID[161]:AXIPCI110 */ + [162] = {0xFCF8346CU, 0x00000002U}, /* RGIDSEC_MODID[162]:AXIPCI111 */ + [163] = {0xFCF83470U, 0x00000002U}, /* RGIDSEC_MODID[163]:AXIPCI112 */ + [164] = {0xFCF83474U, 0x00000002U}, /* RGIDSEC_MODID[164]:AXIPCI113 */ + [165] = {0xFCF83478U, 0x00000002U}, /* RGIDSEC_MODID[165]:AXIPCI114 */ + [166] = {0xFCF8347CU, 0x00000002U}, /* RGIDSEC_MODID[166]:AXIPCI115 */ + [167] = {0xFCF83480U, 0x00000002U}, /* RGIDSEC_MODID[167]:ETHPHYRAM */ + [168] = {0xFCF83488U, 0x00000002U}, /* RGIDSEC_MODID[168]:IPMMUHC00 */ + [169] = {0xFCF8348CU, 0x00000002U}, /* RGIDSEC_MODID[169]:RSW200 */ + [170] = {0xFCF83490U, 0x00000002U}, /* RGIDSEC_MODID[170]:RSW201 */ + [171] = {0xFCF83494U, 0x00000002U}, /* RGIDSEC_MODID[171]:RSW210 */ + [172] = {0xFCF83498U, 0x00000002U}, /* RGIDSEC_MODID[172]:RSW211 */ + [173] = {0xFCF8349CU, 0x00000002U}, /* RGIDSEC_MODID[173]:RSW202 */ + [174] = {0xFCF834A0U, 0x00000002U}, /* RGIDSEC_MODID[174]:RSW203 */ + [175] = {0xFCF834A4U, 0x00000002U}, /* RGIDSEC_MODID[175]:RSW204 */ + [176] = {0xFCF834A8U, 0x00000002U}, /* RGIDSEC_MODID[176]:RSW205 */ + [177] = {0xFCF834ACU, 0x00000002U}, /* RGIDSEC_MODID[177]:RSW206 */ + [178] = {0xFCF834B0U, 0x00000002U}, /* RGIDSEC_MODID[178]:RSW207 */ + [179] = {0xFCF834B4U, 0x00000002U}, /* RGIDSEC_MODID[179]:RSW208 */ + [180] = {0xFCF834B8U, 0x00000002U}, /* RGIDSEC_MODID[180]:RSW209 */ + [181] = {0xFCF834BCU, 0x00000002U}, /* RGIDSEC_MODID[181]:RSW2RAM */ + [182] = {0xFCF834C0U, 0x00000002U}, /* RGIDSEC_MODID[182]:RSW2SEC00 */ + [183] = {0xFCF834C4U, 0x00000002U}, /* RGIDSEC_MODID[183]:RSW2SEC01 */ + [184] = {0xFCF834C8U, 0x00000002U}, /* RGIDSEC_MODID[184]:RSW2SEC10 */ + [185] = {0xFCF834CCU, 0x00000002U}, /* RGIDSEC_MODID[185]:RSW2SEC11 */ + [186] = {0xFCF834D0U, 0x00000002U}, /* RGIDSEC_MODID[186]:RSW2SEC02 */ + [187] = {0xFCF834D4U, 0x00000002U}, /* RGIDSEC_MODID[187]:RSW2SEC03 */ + [188] = {0xFCF834D8U, 0x00000002U}, /* RGIDSEC_MODID[188]:RSW2SEC04 */ + [189] = {0xFCF834DCU, 0x00000002U}, /* RGIDSEC_MODID[189]:RSW2SEC05 */ + [190] = {0xFCF834E0U, 0x00000002U}, /* RGIDSEC_MODID[190]:RSW2SEC06 */ + [191] = {0xFCF834E4U, 0x00000002U}, /* RGIDSEC_MODID[191]:RSW2SEC07 */ + [192] = {0xFCF834E8U, 0x00000002U}, /* RGIDSEC_MODID[192]:RSW2SEC08 */ + [193] = {0xFCF834ECU, 0x00000002U}, /* RGIDSEC_MODID[193]:RSW2SEC09 */ + [194] = {0xFCF834F4U, 0x00000002U}, /* RGIDSEC_MODID[194]:AXIPCI000 */ + [195] = {0xFCF834F8U, 0x00000002U}, /* RGIDSEC_MODID[195]:AXIPCI004 */ + [196] = {0xFCF834FCU, 0x00000002U}, /* RGIDSEC_MODID[196]:IPMMUHC01 */ + [197] = {0xFCF8350CU, 0x00000002U}, /* RGIDSEC_MODID[197]:IPMMUHC10 */ + [198] = {0xFCF83510U, 0x00000002U}, /* RGIDSEC_MODID[198]:IPMMUHC11 */ + [199] = {0xFCF83514U, 0x00000002U}, /* RGIDSEC_MODID[199]:IPMMUHC12 */ + [200] = {0xFCF83518U, 0x00000002U}, /* RGIDSEC_MODID[200]:IPMMUHC13 */ + [201] = {0xFCF8351CU, 0x00000002U}, /* RGIDSEC_MODID[201]:PPHY0 */ + [202] = {0xFCF83520U, 0x00000002U}, /* RGIDSEC_MODID[202]:PPHY1 */ + [203] = {0xFCF83524U, 0x00000002U}, /* RGIDSEC_MODID[203]:IPMMUHC14 */ + [204] = {0xFCF83528U, 0x00000002U}, /* RGIDSEC_MODID[204]:IPMMUHC15 */ + [205] = {0xFCF8352CU, 0x00000002U}, /* RGIDSEC_MODID[205]:FBAHSC */ + [206] = {0xFCF83530U, 0x00000002U}, /* RGIDSEC_MODID[206]:IPMMUHC02 */ + [207] = {0xFCF83534U, 0x00000002U}, /* RGIDSEC_MODID[207]:AXIUFSS */ + [208] = {0xFCF83538U, 0x00000002U}, /* RGIDSEC_MODID[208]:ECMHSC */ + [209] = {0xFCF8353CU, 0x00000002U}, /* RGIDSEC_MODID[209]:ARHC0 */ + [210] = {0xFCF83540U, 0x00000002U}, /* RGIDSEC_MODID[210]:ARHC1 */ + [211] = {0xFCF83544U, 0x00000002U}, /* RGIDSEC_MODID[211]:ARHC2 */ + [212] = {0xFCF83548U, 0x00000002U}, /* RGIDSEC_MODID[212]:ARHC3 */ + [213] = {0xFCF8354CU, 0x00000002U}, /* RGIDSEC_MODID[213]:ARHC4 */ + [214] = {0xFCF83550U, 0x00000002U}, /* RGIDSEC_MODID[214]:ARHC5 */ + [215] = {0xFCF83554U, 0x00000002U}, /* RGIDSEC_MODID[215]:ARHC6 */ + [216] = {0xFCF83558U, 0x00000002U}, /* RGIDSEC_MODID[216]:ARHC7 */ + [217] = {0xFCF8355CU, 0x00000002U}, /* RGIDSEC_MODID[217]:ARHC8 */ + [218] = {0xFCF83560U, 0x00000002U}, /* RGIDSEC_MODID[218]:IPMMUHC03 */ + [219] = {0xFCF83564U, 0x00000002U}, /* RGIDSEC_MODID[219]:IPMMUHC04 */ + [220] = {0xFCF83568U, 0x00000002U}, /* RGIDSEC_MODID[220]:IPMMUHC05 */ + [221] = {0xFCF8356CU, 0x00000002U}, /* RGIDSEC_MODID[221]:IPMMUHC06 */ + [222] = {0xFCF83570U, 0x00000002U}, /* RGIDSEC_MODID[222]:IPMMUHC07 */ + [223] = {0xFCF83574U, 0x00000002U}, /* RGIDSEC_MODID[223]:IPMMUHC08 */ + [224] = {0xFCF83578U, 0x00000002U}, /* RGIDSEC_MODID[224]:IPMMUHC09 */ + [225] = {0xFDC23400U, 0x00000002U}, /* RGIDSEC_MODID[225]:ARRC0 */ + [226] = {0xFDC23404U, 0x00000002U}, /* RGIDSEC_MODID[226]:ARRC1 */ + [227] = {0xFDC23408U, 0x00000002U}, /* RGIDSEC_MODID[227]:ARRC2 */ + [228] = {0xFDC2340CU, 0x00000002U}, /* RGIDSEC_MODID[228]:ARRC3 */ + [229] = {0xFDC23410U, 0x00000002U}, /* RGIDSEC_MODID[229]:ARRC4 */ + [230] = {0xFDC23414U, 0x00000002U}, /* RGIDSEC_MODID[230]:ARRC5 */ + [231] = {0xFDC23418U, 0x00000002U}, /* RGIDSEC_MODID[231]:ARRC6 */ + [232] = {0xFDC2341CU, 0x00000002U}, /* RGIDSEC_MODID[232]:ARRC7 */ + [233] = {0xFDC23420U, 0x00000002U}, /* RGIDSEC_MODID[233]:ARRC8 */ + [234] = {0xFDC23424U, 0x00000000U}, /* RGIDSEC_MODID[234]:CR0 */ + [235] = {0xFDC23428U, 0x00000002U}, /* RGIDSEC_MODID[235]:ICUMX */ + [236] = {0xFDC2342CU, 0x00000002U}, /* RGIDSEC_MODID[236]:ECMRC */ + [237] = {0xFD433400U, 0x00000002U}, /* RGIDSEC_MODID[237]:DMAWCRC0 */ + [238] = {0xFD433404U, 0x00000002U}, /* RGIDSEC_MODID[238]:DMAWCRC1 */ + [239] = {0xFD433408U, 0x00000002U}, /* RGIDSEC_MODID[239]:DMAWCRC2 */ + [240] = {0xFD43340CU, 0x00000002U}, /* RGIDSEC_MODID[240]:DMAWCRC3 */ + [241] = {0xFD433410U, 0x00000002U}, /* RGIDSEC_MODID[241]:DMATSIP0 */ + [242] = {0xFD433414U, 0x00000002U}, /* RGIDSEC_MODID[242]:DMATSIP1 */ + [243] = {0xFD433418U, 0x00000002U}, /* RGIDSEC_MODID[243]:DMATSIP2 */ + [244] = {0xFD443400U, 0x00000002U}, /* RGIDSEC_MODID[244]:ARMREG00 */ + [245] = {0xFD443404U, 0x00000002U}, /* RGIDSEC_MODID[245]:ARMREG01 */ + [246] = {0xFD443408U, 0x00000002U}, /* RGIDSEC_MODID[246]:ARMREG10 */ + [247] = {0xFD44340CU, 0x00000002U}, /* RGIDSEC_MODID[247]:ARMREG11 */ + [248] = {0xFD443410U, 0x00000002U}, /* RGIDSEC_MODID[248]:ARMREG12 */ + [249] = {0xFD443414U, 0x00000000U}, /* RGIDSEC_MODID[249]:ARMREG13 */ + [250] = {0xFD443418U, 0x00000000U}, /* RGIDSEC_MODID[250]:ARMREG14 */ + [251] = {0xFD44341CU, 0x00000002U}, /* RGIDSEC_MODID[251]:AXICR52SS */ + [252] = {0xFD443420U, 0x00000002U}, /* RGIDSEC_MODID[252]:AXICSD0 */ + [253] = {0xFD443424U, 0x00000002U}, /* RGIDSEC_MODID[253]:AXIINTAP0 */ + [254] = {0xFD443428U, 0x00000002U}, /* RGIDSEC_MODID[254]:AXIINTAP1 */ + [255] = {0xFD44342CU, 0x00000002U}, /* RGIDSEC_MODID[255]:AXISECROM */ + [256] = {0xFD443430U, 0x00000002U}, /* RGIDSEC_MODID[256]:AXISYSRAM0 */ + [257] = {0xFD443434U, 0x00000002U}, /* RGIDSEC_MODID[257]:AXISYSRAM1 */ + [258] = {0xFD443438U, 0x00000002U}, /* RGIDSEC_MODID[258]:ARGREG15 */ + [259] = {0xFD44343CU, 0x00000002U}, /* RGIDSEC_MODID[259]:ARMREG2 */ + [260] = {0xFD443440U, 0x00000002U}, /* RGIDSEC_MODID[260]:ARMREG3 */ + [261] = {0xFD443444U, 0x00000002U}, /* RGIDSEC_MODID[261]:ARMREG4 */ + [262] = {0xFD443448U, 0x00000002U}, /* RGIDSEC_MODID[262]:ARMREG5 */ + [263] = {0xFD44344CU, 0x00000002U}, /* RGIDSEC_MODID[263]:ARMREG6 */ + [264] = {0xFD443450U, 0x00000002U}, /* RGIDSEC_MODID[264]:ARMREG7 */ + [265] = {0xFD443454U, 0x00000000U}, /* RGIDSEC_MODID[265]:ARMREG8 */ + [266] = {0xFD443458U, 0x00000000U}, /* RGIDSEC_MODID[266]:ARMREG9 */ + [267] = {0xFD44345CU, 0x00000002U}, /* RGIDSEC_MODID[267]:ARRD0 */ + [268] = {0xFD443460U, 0x00000002U}, /* RGIDSEC_MODID[268]:ARRD1 */ + [269] = {0xFD443464U, 0x00000002U}, /* RGIDSEC_MODID[269]:ARRD2 */ + [270] = {0xFD443468U, 0x00000002U}, /* RGIDSEC_MODID[270]:ARRD3 */ + [271] = {0xFD44346CU, 0x00000002U}, /* RGIDSEC_MODID[271]:ARRD4 */ + [272] = {0xFD443470U, 0x00000002U}, /* RGIDSEC_MODID[272]:ARRD5 */ + [273] = {0xFD443474U, 0x00000002U}, /* RGIDSEC_MODID[273]:ARRD6 */ + [274] = {0xFD443478U, 0x00000002U}, /* RGIDSEC_MODID[274]:ARRD7 */ + [275] = {0xFD44347CU, 0x00000002U}, /* RGIDSEC_MODID[275]:ARRD8 */ + [276] = {0xFD443480U, 0x00000002U}, /* RGIDSEC_MODID[276]:ARRT0 */ + [277] = {0xFD443484U, 0x00000002U}, /* RGIDSEC_MODID[277]:ARRT1 */ + [278] = {0xFD443488U, 0x00000002U}, /* RGIDSEC_MODID[278]:ARRT2 */ + [279] = {0xFD44348CU, 0x00000002U}, /* RGIDSEC_MODID[279]:ARRT3 */ + [280] = {0xFD443490U, 0x00000002U}, /* RGIDSEC_MODID[280]:ARRT4 */ + [281] = {0xFD443494U, 0x00000002U}, /* RGIDSEC_MODID[281]:ARRT5 */ + [282] = {0xFD443498U, 0x00000002U}, /* RGIDSEC_MODID[282]:ARRT6 */ + [283] = {0xFD44349CU, 0x00000002U}, /* RGIDSEC_MODID[283]:ARRT7 */ + [284] = {0xFD4434A0U, 0x00000002U}, /* RGIDSEC_MODID[284]:ARRT8 */ + [285] = {0xFD4434A4U, 0x00000002U}, /* RGIDSEC_MODID[285]:CKMRT */ + [286] = {0xFD4434A8U, 0x00000002U}, /* RGIDSEC_MODID[286]:CRC0 */ + [287] = {0xFD4434ACU, 0x00000002U}, /* RGIDSEC_MODID[287]:CRC1 */ + [288] = {0xFD4434B0U, 0x00000002U}, /* RGIDSEC_MODID[288]:CRC2 */ + [289] = {0xFD4434B4U, 0x00000002U}, /* RGIDSEC_MODID[289]:CRC3 */ + [290] = {0xFD4434B8U, 0x00000002U}, /* RGIDSEC_MODID[290]:CSD */ + [291] = {0xFD4434BCU, 0x00000002U}, /* RGIDSEC_MODID[291]:ECM */ + [292] = {0xFD4434C0U, 0x00000002U}, /* RGIDSEC_MODID[292]:ECMRT */ + [293] = {0xFD4434C4U, 0x00000002U}, /* RGIDSEC_MODID[293]:FBACR52 */ + [294] = {0xFD4434C8U, 0x00000002U}, /* RGIDSEC_MODID[294]:FBART */ + [295] = {0xFD4434CCU, 0x00000002U}, /* RGIDSEC_MODID[295]:INTTP */ + [296] = {0xFD4434D0U, 0x00000002U}, /* RGIDSEC_MODID[296]:IPMMURT000 */ + [297] = {0xFD4434D4U, 0x00000002U}, /* RGIDSEC_MODID[297]:IPMMURT100 */ + [298] = {0xFD4434D8U, 0x00000002U}, /* RGIDSEC_MODID[298]:KCRC4 */ + [299] = {0xFD4434DCU, 0x00000002U}, /* RGIDSEC_MODID[299]:KCRC5 */ + [300] = {0xFD4434E0U, 0x00000002U}, /* RGIDSEC_MODID[300]:KCRC6 */ + [301] = {0xFD4434E4U, 0x00000002U}, /* RGIDSEC_MODID[301]:KCRC7 */ + [302] = {0xFD4434E8U, 0x00000002U}, /* RGIDSEC_MODID[302]:MFI00 */ + [303] = {0xFD4434ECU, 0x00000002U}, /* RGIDSEC_MODID[303]:MFI01 */ + [304] = {0xFD4434F0U, 0x00000002U}, /* RGIDSEC_MODID[304]:MFI10 */ + [305] = {0xFD4434F4U, 0x00000002U}, /* RGIDSEC_MODID[305]:MFI02 */ + [306] = {0xFD4434F8U, 0x00000002U}, /* RGIDSEC_MODID[306]:MFI03 */ + [307] = {0xFD4434FCU, 0x00000002U}, /* RGIDSEC_MODID[307]:MFI04 */ + [308] = {0xFD443500U, 0x00000002U}, /* RGIDSEC_MODID[308]:MFI05 */ + [309] = {0xFD443504U, 0x00000002U}, /* RGIDSEC_MODID[309]:MFI06 */ + [310] = {0xFD443508U, 0x00000002U}, /* RGIDSEC_MODID[310]:MFI07 */ + [311] = {0xFD44350CU, 0x00000002U}, /* RGIDSEC_MODID[311]:MFI08 */ + [312] = {0xFD443510U, 0x00000002U}, /* RGIDSEC_MODID[312]:MFI09 */ + [313] = {0xFD443514U, 0x00000002U}, /* RGIDSEC_MODID[313]:MFI15 */ + [314] = {0xFD443518U, 0x00000002U}, /* RGIDSEC_MODID[314]:CKMCR52 */ + [315] = {0xFD44351CU, 0x00000002U}, /* RGIDSEC_MODID[315]:RTDM0P */ + [316] = {0xFD443520U, 0x00000002U}, /* RGIDSEC_MODID[316]:ECMRD */ + [317] = {0xFD443524U, 0x00000002U}, /* RGIDSEC_MODID[317]:RTDM1P */ + [318] = {0xFD44352CU, 0x00000002U}, /* RGIDSEC_MODID[318]:RTDM2P */ + [319] = {0xFD443530U, 0x00000002U}, /* RGIDSEC_MODID[319]:SYSRAM10 */ + [320] = {0xFD443534U, 0x00000002U}, /* RGIDSEC_MODID[320]:RTDM3P */ + [321] = {0xFD443538U, 0x00000000U}, /* RGIDSEC_MODID[321]:SYSRAM00 */ + [322] = {0xFD44353CU, 0x00000002U}, /* RGIDSEC_MODID[322]:TSIPL0 */ + [323] = {0xFD443540U, 0x00000002U}, /* RGIDSEC_MODID[323]:TSIPL1 */ + [324] = {0xFD443544U, 0x00000002U}, /* RGIDSEC_MODID[324]:TSIPL2 */ + [325] = {0xFD443548U, 0x00000002U}, /* RGIDSEC_MODID[325]:TSIPL3 */ + [326] = {0xFD44354CU, 0x00000002U}, /* RGIDSEC_MODID[326]:TSIPL4 */ + [327] = {0xFD443550U, 0x00000002U}, /* RGIDSEC_MODID[327]:TSIPL5 */ + [328] = {0xFD443554U, 0x00000002U}, /* RGIDSEC_MODID[328]:TSIPL6 */ + [329] = {0xFD443558U, 0x00000002U}, /* RGIDSEC_MODID[329]:TSIPL7 */ + [330] = {0xFD44355CU, 0x00000002U}, /* RGIDSEC_MODID[330]:WCRC0 */ + [331] = {0xFD443560U, 0x00000002U}, /* RGIDSEC_MODID[331]:WCRC1 */ + [332] = {0xFD443564U, 0x00000002U}, /* RGIDSEC_MODID[332]:WCRC2 */ + [333] = {0xFD443568U, 0x00000002U}, /* RGIDSEC_MODID[333]:WCRC3 */ + [334] = {0xFD443574U, 0x00000002U}, /* RGIDSEC_MODID[334]:TSIP0 */ + [335] = {0xFD443578U, 0x00000002U}, /* RGIDSEC_MODID[335]:TSIP1 */ + [336] = {0xFD44357CU, 0x00000002U}, /* RGIDSEC_MODID[336]:TSIP2 */ + [337] = {0xFD443580U, 0x00000002U}, /* RGIDSEC_MODID[337]:MFI11 */ + [338] = {0xFD443584U, 0x00000002U}, /* RGIDSEC_MODID[338]:MFI12 */ + [339] = {0xFD443588U, 0x00000002U}, /* RGIDSEC_MODID[339]:MFI13 */ + [340] = {0xFD44358CU, 0x00000002U}, /* RGIDSEC_MODID[340]:MFI14 */ + [341] = {0xFD443590U, 0x00000002U}, /* RGIDSEC_MODID[341]:IPMMURT001 */ + [342] = {0xFD443594U, 0x00000002U}, /* RGIDSEC_MODID[342]:IPMMURT010 */ + [343] = {0xFD443598U, 0x00000002U}, /* RGIDSEC_MODID[343]:IPMMURT011 */ + [344] = {0xFD44359CU, 0x00000002U}, /* RGIDSEC_MODID[344]:IPMMURT012 */ + [345] = {0xFD4435A0U, 0x00000002U}, /* RGIDSEC_MODID[345]:IPMMURT013 */ + [346] = {0xFD4435A4U, 0x00000002U}, /* RGIDSEC_MODID[346]:IPMMURT014 */ + [347] = {0xFD4435A8U, 0x00000002U}, /* RGIDSEC_MODID[347]:IPMMURT015 */ + [348] = {0xFD4435ACU, 0x00000002U}, /* RGIDSEC_MODID[348]:IPMMURT002 */ + [349] = {0xFD4435B0U, 0x00000002U}, /* RGIDSEC_MODID[349]:IPMMURT003 */ + [350] = {0xFD4435B4U, 0x00000002U}, /* RGIDSEC_MODID[350]:IPMMURT004 */ + [351] = {0xFD4435B8U, 0x00000002U}, /* RGIDSEC_MODID[351]:IPMMURT005 */ + [352] = {0xFD4435BCU, 0x00000002U}, /* RGIDSEC_MODID[352]:IPMMURT006 */ + [353] = {0xFD4435C0U, 0x00000002U}, /* RGIDSEC_MODID[353]:IPMMURT007 */ + [354] = {0xFD4435C4U, 0x00000002U}, /* RGIDSEC_MODID[354]:IPMMURT008 */ + [355] = {0xFD4435C8U, 0x00000002U}, /* RGIDSEC_MODID[355]:IPMMURT009 */ + [356] = {0xFD4435CCU, 0x00000002U}, /* RGIDSEC_MODID[356]:IPMMURT101 */ + [357] = {0xFD4435D0U, 0x00000002U}, /* RGIDSEC_MODID[357]:IPMMURT110 */ + [358] = {0xFD4435D4U, 0x00000002U}, /* RGIDSEC_MODID[358]:IPMMURT111 */ + [359] = {0xFD4435D8U, 0x00000002U}, /* RGIDSEC_MODID[359]:IPMMURT112 */ + [360] = {0xFD4435DCU, 0x00000002U}, /* RGIDSEC_MODID[360]:IPMMURT113 */ + [361] = {0xFD4435E0U, 0x00000002U}, /* RGIDSEC_MODID[361]:IPMMURT114 */ + [362] = {0xFD4435E4U, 0x00000002U}, /* RGIDSEC_MODID[362]:IPMMURT115 */ + [363] = {0xFD4435E8U, 0x00000002U}, /* RGIDSEC_MODID[363]:IPMMURT102 */ + [364] = {0xFD4435ECU, 0x00000002U}, /* RGIDSEC_MODID[364]:IPMMURT103 */ + [365] = {0xFD4435F0U, 0x00000002U}, /* RGIDSEC_MODID[365]:IPMMURT104 */ + [366] = {0xFD4435F4U, 0x00000002U}, /* RGIDSEC_MODID[366]:IPMMURT105 */ + [367] = {0xFD4435F8U, 0x00000002U}, /* RGIDSEC_MODID[367]:IPMMURT106 */ + [368] = {0xFD4435FCU, 0x00000002U}, /* RGIDSEC_MODID[368]:IPMMURT107 */ + [369] = {0xFD443600U, 0x00000002U}, /* RGIDSEC_MODID[369]:RTDM000 */ + [370] = {0xFD443604U, 0x00000002U}, /* RGIDSEC_MODID[370]:RTDM001 */ + [371] = {0xFD443608U, 0x00000002U}, /* RGIDSEC_MODID[371]:RTDM010 */ + [372] = {0xFD44360CU, 0x00000002U}, /* RGIDSEC_MODID[372]:RTDM011 */ + [373] = {0xFD443610U, 0x00000002U}, /* RGIDSEC_MODID[373]:RTDM012 */ + [374] = {0xFD443614U, 0x00000002U}, /* RGIDSEC_MODID[374]:RTDM013 */ + [375] = {0xFD443618U, 0x00000002U}, /* RGIDSEC_MODID[375]:RTDM014 */ + [376] = {0xFD44361CU, 0x00000002U}, /* RGIDSEC_MODID[376]:RTDM015 */ + [377] = {0xFD443620U, 0x00000002U}, /* RGIDSEC_MODID[377]:RTDM002 */ + [378] = {0xFD443624U, 0x00000002U}, /* RGIDSEC_MODID[378]:RTDM003 */ + [379] = {0xFD443628U, 0x00000002U}, /* RGIDSEC_MODID[379]:RTDM004 */ + [380] = {0xFD44362CU, 0x00000002U}, /* RGIDSEC_MODID[380]:RTDM005 */ + [381] = {0xFD443630U, 0x00000002U}, /* RGIDSEC_MODID[381]:RTDM006 */ + [382] = {0xFD443634U, 0x00000002U}, /* RGIDSEC_MODID[382]:RTDM007 */ + [383] = {0xFD443638U, 0x00000002U}, /* RGIDSEC_MODID[383]:RTDM008 */ + [384] = {0xFD44363CU, 0x00000002U}, /* RGIDSEC_MODID[384]:RTDM009 */ + [385] = {0xFD443640U, 0x00000002U}, /* RGIDSEC_MODID[385]:RTDM100 */ + [386] = {0xFD443644U, 0x00000002U}, /* RGIDSEC_MODID[386]:RTDM101 */ + [387] = {0xFD443648U, 0x00000002U}, /* RGIDSEC_MODID[387]:RTDM110 */ + [388] = {0xFD44364CU, 0x00000002U}, /* RGIDSEC_MODID[388]:RTDM111 */ + [389] = {0xFD443650U, 0x00000002U}, /* RGIDSEC_MODID[389]:RTDM112 */ + [390] = {0xFD443654U, 0x00000002U}, /* RGIDSEC_MODID[390]:RTDM113 */ + [391] = {0xFD443658U, 0x00000002U}, /* RGIDSEC_MODID[391]:RTDM114 */ + [392] = {0xFD44365CU, 0x00000002U}, /* RGIDSEC_MODID[392]:RTDM115 */ + [393] = {0xFD443660U, 0x00000002U}, /* RGIDSEC_MODID[393]:RTDM102 */ + [394] = {0xFD443664U, 0x00000002U}, /* RGIDSEC_MODID[394]:RTDM103 */ + [395] = {0xFD443668U, 0x00000002U}, /* RGIDSEC_MODID[395]:RTDM104 */ + [396] = {0xFD44366CU, 0x00000002U}, /* RGIDSEC_MODID[396]:RTDM105 */ + [397] = {0xFD443670U, 0x00000002U}, /* RGIDSEC_MODID[397]:RTDM106 */ + [398] = {0xFD443674U, 0x00000002U}, /* RGIDSEC_MODID[398]:RTDM107 */ + [399] = {0xFD443678U, 0x00000002U}, /* RGIDSEC_MODID[399]:RTDM108 */ + [400] = {0xFD44367CU, 0x00000002U}, /* RGIDSEC_MODID[400]:RTDM109 */ + [401] = {0xFD443680U, 0x00000002U}, /* RGIDSEC_MODID[401]:RTDM200 */ + [402] = {0xFD443684U, 0x00000002U}, /* RGIDSEC_MODID[402]:RTDM201 */ + [403] = {0xFD443688U, 0x00000002U}, /* RGIDSEC_MODID[403]:RTDM210 */ + [404] = {0xFD44368CU, 0x00000002U}, /* RGIDSEC_MODID[404]:RTDM211 */ + [405] = {0xFD443690U, 0x00000002U}, /* RGIDSEC_MODID[405]:RTDM212 */ + [406] = {0xFD443694U, 0x00000002U}, /* RGIDSEC_MODID[406]:RTDM213 */ + [407] = {0xFD443698U, 0x00000002U}, /* RGIDSEC_MODID[407]:RTDM214 */ + [408] = {0xFD44369CU, 0x00000002U}, /* RGIDSEC_MODID[408]:RTDM215 */ + [409] = {0xFD4436A0U, 0x00000002U}, /* RGIDSEC_MODID[409]:RTDM202 */ + [410] = {0xFD4436A4U, 0x00000002U}, /* RGIDSEC_MODID[410]:RTDM203 */ + [411] = {0xFD4436A8U, 0x00000002U}, /* RGIDSEC_MODID[411]:RTDM204 */ + [412] = {0xFD4436ACU, 0x00000002U}, /* RGIDSEC_MODID[412]:RTDM205 */ + [413] = {0xFD4436B0U, 0x00000002U}, /* RGIDSEC_MODID[413]:RTDM206 */ + [414] = {0xFD4436B4U, 0x00000002U}, /* RGIDSEC_MODID[414]:RTDM207 */ + [415] = {0xFD4436B8U, 0x00000002U}, /* RGIDSEC_MODID[415]:RTDM208 */ + [416] = {0xFD4436BCU, 0x00000002U}, /* RGIDSEC_MODID[416]:RTDM209 */ + [417] = {0xFD4436C0U, 0x00000002U}, /* RGIDSEC_MODID[417]:RTDM300 */ + [418] = {0xFD4436C4U, 0x00000002U}, /* RGIDSEC_MODID[418]:RTDM301 */ + [419] = {0xFD4436C8U, 0x00000002U}, /* RGIDSEC_MODID[419]:RTDM310 */ + [420] = {0xFD4436CCU, 0x00000002U}, /* RGIDSEC_MODID[420]:RTDM311 */ + [421] = {0xFD4436D0U, 0x00000002U}, /* RGIDSEC_MODID[421]:RTDM312 */ + [422] = {0xFD4436D4U, 0x00000002U}, /* RGIDSEC_MODID[422]:RTDM313 */ + [423] = {0xFD4436D8U, 0x00000002U}, /* RGIDSEC_MODID[423]:RTDM314 */ + [424] = {0xFD4436DCU, 0x00000002U}, /* RGIDSEC_MODID[424]:RTDM315 */ + [425] = {0xFD4436E0U, 0x00000002U}, /* RGIDSEC_MODID[425]:RTDM302 */ + [426] = {0xFD4436E4U, 0x00000002U}, /* RGIDSEC_MODID[426]:RTDM303 */ + [427] = {0xFD4436E8U, 0x00000002U}, /* RGIDSEC_MODID[427]:RTDM304 */ + [428] = {0xFD4436ECU, 0x00000002U}, /* RGIDSEC_MODID[428]:RTDM305 */ + [429] = {0xFD4436F0U, 0x00000002U}, /* RGIDSEC_MODID[429]:RTDM306 */ + [430] = {0xFD4436F4U, 0x00000002U}, /* RGIDSEC_MODID[430]:RTDM307 */ + [431] = {0xFD4436F8U, 0x00000002U}, /* RGIDSEC_MODID[431]:RTDM308 */ + [432] = {0xFD4436FCU, 0x00000002U}, /* RGIDSEC_MODID[432]:RTDM309 */ + [433] = {0xFD443700U, 0x00000002U}, /* RGIDSEC_MODID[433]:IPMMURT108 */ + [434] = {0xFD443704U, 0x00000002U}, /* RGIDSEC_MODID[434]:IPMMURT109 */ + [435] = {0xFD443708U, 0x00000000U}, /* RGIDSEC_MODID[435]:SYSRAM01 */ + [436] = {0xFD44370CU, 0x00000002U}, /* RGIDSEC_MODID[436]:SYSRAM02 */ + [437] = {0xFD443710U, 0x00000000U}, /* RGIDSEC_MODID[437]:SYSRAM03 */ + [438] = {0xFD443714U, 0x00000000U}, /* RGIDSEC_MODID[438]:SYSRAM04 */ + [439] = {0xFD443718U, 0x00000000U}, /* RGIDSEC_MODID[439]:SYSRAM05 */ + [440] = {0xFD44371CU, 0x00000000U}, /* RGIDSEC_MODID[440]:SYSRAM06 */ + [441] = {0xFD443720U, 0x00000002U}, /* RGIDSEC_MODID[441]:SYSRAM07 */ + [442] = {0xFD443724U, 0x00000002U}, /* RGIDSEC_MODID[442]:SYSRAM11 */ + [443] = {0xFD443728U, 0x00000002U}, /* RGIDSEC_MODID[443]:SYSRAM12 */ + [444] = {0xFD44372CU, 0x00000002U}, /* RGIDSEC_MODID[444]:SYSRAM13 */ + [445] = {0xFD443730U, 0x00000002U}, /* RGIDSEC_MODID[445]:SYSRAM14 */ + [446] = {0xFD443734U, 0x00000002U}, /* RGIDSEC_MODID[446]:SYSRAM15 */ + [447] = {0xFD443738U, 0x00000002U}, /* RGIDSEC_MODID[447]:SYSRAM16 */ + [448] = {0xFD44373CU, 0x00000002U}, /* RGIDSEC_MODID[448]:SYSRAM17 */ + [449] = {0xFD443760U, 0x00000002U}, /* RGIDSEC_MODID[449]:BKBUF */ + [450] = {0xFD44376CU, 0x00000002U}, /* RGIDSEC_MODID[450]:MCU */ + [451] = {0xFF863400U, 0x00000002U}, /* RGIDSEC_MODID[451]:ARSC0 */ + [452] = {0xFF863404U, 0x00000002U}, /* RGIDSEC_MODID[452]:ARSC1 */ + [453] = {0xFF863408U, 0x00000002U}, /* RGIDSEC_MODID[453]:ARSC2 */ + [454] = {0xFF86340CU, 0x00000002U}, /* RGIDSEC_MODID[454]:ARSC3 */ + [455] = {0xFF863410U, 0x00000002U}, /* RGIDSEC_MODID[455]:ARSC4 */ + [456] = {0xFF863414U, 0x00000002U}, /* RGIDSEC_MODID[456]:ARSC5 */ + [457] = {0xFF863418U, 0x00000002U}, /* RGIDSEC_MODID[457]:ARSC6 */ + [458] = {0xFF86341CU, 0x00000002U}, /* RGIDSEC_MODID[458]:ARSC7 */ + [459] = {0xFF863420U, 0x00000002U}, /* RGIDSEC_MODID[459]:ARSC8 */ + [460] = {0xFF863424U, 0x00000002U}, /* RGIDSEC_MODID[460]:ARSTM0 */ + [461] = {0xFF863428U, 0x00000002U}, /* RGIDSEC_MODID[461]:ARSTM1 */ + [462] = {0xFF863430U, 0x00000002U}, /* RGIDSEC_MODID[462]:AXIFBABUSTOP0 */ + [463] = {0xFF863434U, 0x00000002U}, /* RGIDSEC_MODID[463]:AXIFBABUSTOP1 */ + [464] = {0xFF863438U, 0x00000002U}, /* RGIDSEC_MODID[464]:ARSTM2 */ + [465] = {0xFF86343CU, 0x00000002U}, /* RGIDSEC_MODID[465]:ARSTM3 */ + [466] = {0xFF863440U, 0x00000002U}, /* RGIDSEC_MODID[466]:ARSTM4 */ + [467] = {0xFF863444U, 0x00000002U}, /* RGIDSEC_MODID[467]:ARSTM5 */ + [468] = {0xFF863448U, 0x00000002U}, /* RGIDSEC_MODID[468]:ARSTM6 */ + [469] = {0xFF86344CU, 0x00000002U}, /* RGIDSEC_MODID[469]:ARSTM7 */ + [470] = {0xFF863450U, 0x00000002U}, /* RGIDSEC_MODID[470]:ARSTM8 */ + [471] = {0xFF863454U, 0x00000002U}, /* RGIDSEC_MODID[471]:ECMTOP */ + [472] = {0xFF863458U, 0x00000002U}, /* RGIDSEC_MODID[472]:FBA */ + [473] = {0xFF86345CU, 0x00000002U}, /* RGIDSEC_MODID[473]:FBC */ + [474] = {0xFF863460U, 0x00000002U}, /* RGIDSEC_MODID[474]:AXICCI00 */ + [475] = {0xFF863464U, 0x00000002U}, /* RGIDSEC_MODID[475]:AXICCI01 */ + [476] = {0xFF863468U, 0x00000002U}, /* RGIDSEC_MODID[476]:AXICCI10 */ + [477] = {0xFF86346CU, 0x00000002U}, /* RGIDSEC_MODID[477]:AXICCI11 */ + [478] = {0xFF863470U, 0x00000002U}, /* RGIDSEC_MODID[478]:AXICCI12 */ + [479] = {0xFF863474U, 0x00000002U}, /* RGIDSEC_MODID[479]:AXICCI13 */ + [480] = {0xFF863478U, 0x00000002U}, /* RGIDSEC_MODID[480]:AXICCI14 */ + [481] = {0xFF86347CU, 0x00000002U}, /* RGIDSEC_MODID[481]:AXICCI15 */ + [482] = {0xFF863480U, 0x00000002U}, /* RGIDSEC_MODID[482]:AXICCI2 */ + [483] = {0xFF863484U, 0x00000002U}, /* RGIDSEC_MODID[483]:AXICCI3 */ + [484] = {0xFF863488U, 0x00000002U}, /* RGIDSEC_MODID[484]:AXICCI4 */ + [485] = {0xFF86348CU, 0x00000002U}, /* RGIDSEC_MODID[485]:AXICCI5 */ + [486] = {0xFF863490U, 0x00000002U}, /* RGIDSEC_MODID[486]:AXICCI6 */ + [487] = {0xFF863494U, 0x00000002U}, /* RGIDSEC_MODID[487]:AXICCI7 */ + [488] = {0xFF863498U, 0x00000002U}, /* RGIDSEC_MODID[488]:AXICCI8 */ + [489] = {0xFF86349CU, 0x00000002U}, /* RGIDSEC_MODID[489]:AXICCI9 */ + [490] = {0xFF8634A0U, 0x00000002U}, /* RGIDSEC_MODID[490]:ECMSTM */ + [491] = {0xFCB83414U, 0x00000002U}, /* RGIDSEC_MODID[491]:DMAI2C0 */ + [492] = {0xFCB83418U, 0x00000002U}, /* RGIDSEC_MODID[492]:DMAI2C1 */ + [493] = {0xFCB8341CU, 0x00000002U}, /* RGIDSEC_MODID[493]:DMAI2C2 */ + [494] = {0xFCB83420U, 0x00000002U}, /* RGIDSEC_MODID[494]:DMAI2C3 */ + [495] = {0xFCB83424U, 0x00000002U}, /* RGIDSEC_MODID[495]:DMAI2C4 */ + [496] = {0xFCB83428U, 0x00000002U}, /* RGIDSEC_MODID[496]:DMAI2C5 */ + [497] = {0xFDDC3400U, 0x00000002U}, /* RGIDSEC_MODID[497]:ARMM */ + [498] = {0xFDDC3404U, 0x00000002U}, /* RGIDSEC_MODID[498]:AXIARNMM */ + [499] = {0xFDDC3408U, 0x00000002U}, /* RGIDSEC_MODID[499]:ARSM0 */ + [500] = {0xFDDC340CU, 0x00000002U}, /* RGIDSEC_MODID[500]:ARSM1 */ + [501] = {0xFDDC3410U, 0x00000002U}, /* RGIDSEC_MODID[501]:ARSM2 */ + [502] = {0xFDDC3414U, 0x00000002U}, /* RGIDSEC_MODID[502]:AXIQOS0 */ + [503] = {0xFDDC3418U, 0x00000002U}, /* RGIDSEC_MODID[503]:AXIQOS1 */ + [504] = {0xFDDC341CU, 0x00000002U}, /* RGIDSEC_MODID[504]:AXIQOS2 */ + [505] = {0xFDDC3420U, 0x00000002U}, /* RGIDSEC_MODID[505]:AXIQOS3 */ + [506] = {0xFDDC3424U, 0x00000002U}, /* RGIDSEC_MODID[506]:AXIQOS4 */ + [507] = {0xFDDC3430U, 0x00000002U}, /* RGIDSEC_MODID[507]:AXIQOS5 */ + [508] = {0xFDDC3434U, 0x00000002U}, /* RGIDSEC_MODID[508]:ARSM3 */ + [509] = {0xFDDC3438U, 0x00000002U}, /* RGIDSEC_MODID[509]:ARSM4 */ + [510] = {0xFDDC343CU, 0x00000002U}, /* RGIDSEC_MODID[510]:ARSM5 */ + [511] = {0xFDDC3440U, 0x00000002U}, /* RGIDSEC_MODID[511]:ARSM6 */ + [512] = {0xFDDC3444U, 0x00000002U}, /* RGIDSEC_MODID[512]:ARSM7 */ + [513] = {0xFDDC3448U, 0x00000002U}, /* RGIDSEC_MODID[513]:ARSM8 */ + [514] = {0xFDDC344CU, 0x00000000U}, /* RGIDSEC_MODID[514]:AXMM0 */ + [515] = {0xFDDC3450U, 0x00000000U}, /* RGIDSEC_MODID[515]:AXMM1 */ + [516] = {0xFDDC3454U, 0x00000002U}, /* RGIDSEC_MODID[516]:AXMMPMON */ + [517] = {0xFDDC3458U, 0x00000002U}, /* RGIDSEC_MODID[517]:CKMMM */ + [518] = {0xFDDC345CU, 0x00000002U}, /* RGIDSEC_MODID[518]:ECMMM */ + [519] = {0xFDDC3468U, 0x00000002U}, /* RGIDSEC_MODID[519]:FBAMM */ + [520] = {0xFDDC346CU, 0x00000002U}, /* RGIDSEC_MODID[520]:IPMMUMM00 */ + [521] = {0xFDDC3470U, 0x00000002U}, /* RGIDSEC_MODID[521]:DBS00 */ + [522] = {0xFDDC3474U, 0x00000002U}, /* RGIDSEC_MODID[522]:DBS01 */ + [523] = {0xFDDC3480U, 0x00000002U}, /* RGIDSEC_MODID[523]:AXCIDBS */ + [524] = {0xFDDC349CU, 0x00000002U}, /* RGIDSEC_MODID[524]:IPMMUMM01 */ + [525] = {0xFDDC34A0U, 0x00000002U}, /* RGIDSEC_MODID[525]:IPMMUMM10 */ + [526] = {0xFDDC34A4U, 0x00000002U}, /* RGIDSEC_MODID[526]:IPMMUMM11 */ + [527] = {0xFDDC34A8U, 0x00000002U}, /* RGIDSEC_MODID[527]:IPMMUMM12 */ + [528] = {0xFDDC34ACU, 0x00000002U}, /* RGIDSEC_MODID[528]:IPMMUMM13 */ + [529] = {0xFDDC34B0U, 0x00000002U}, /* RGIDSEC_MODID[529]:IPMMUMM14 */ + [530] = {0xFDDC34B4U, 0x00000002U}, /* RGIDSEC_MODID[530]:IPMMUMM15 */ + [531] = {0xFDDC34B8U, 0x00000002U}, /* RGIDSEC_MODID[531]:IPMMUMM02 */ + [532] = {0xFDDC34BCU, 0x00000002U}, /* RGIDSEC_MODID[532]:IPMMUMM03 */ + [533] = {0xFDDC34C0U, 0x00000002U}, /* RGIDSEC_MODID[533]:IPMMUMM04 */ + [534] = {0xFDDC34C4U, 0x00000002U}, /* RGIDSEC_MODID[534]:IPMMUMM05 */ + [535] = {0xFDDC34C8U, 0x00000002U}, /* RGIDSEC_MODID[535]:IPMMUMM06 */ + [536] = {0xFDDC34CCU, 0x00000002U}, /* RGIDSEC_MODID[536]:IPMMUMM07 */ + [537] = {0xFDDC34D0U, 0x00000002U}, /* RGIDSEC_MODID[537]:IPMMUMM08 */ + [538] = {0xFDDC34D4U, 0x00000002U}, /* RGIDSEC_MODID[538]:IPMMUMM09 */ + [539] = {0xFCB53400U, 0x00000002U}, /* RGIDSEC_MODID[539]:ARSD00 */ + [540] = {0xFCB53404U, 0x00000002U}, /* RGIDSEC_MODID[540]:ARSD01 */ + [541] = {0xFCB53408U, 0x00000002U}, /* RGIDSEC_MODID[541]:ARSD02 */ + [542] = {0xFCB5340CU, 0x00000002U}, /* RGIDSEC_MODID[542]:ARSD03 */ + [543] = {0xFCB53410U, 0x00000002U}, /* RGIDSEC_MODID[543]:ARSD04 */ + [544] = {0xFCB53414U, 0x00000002U}, /* RGIDSEC_MODID[544]:ARSD05 */ + [545] = {0xFCB53418U, 0x00000002U}, /* RGIDSEC_MODID[545]:ARSD06 */ + [546] = {0xFCB53428U, 0x00000002U}, /* RGIDSEC_MODID[546]:AXIRPC */ + [547] = {0xFCB5342CU, 0x00000002U}, /* RGIDSEC_MODID[547]:AXISDHI0 */ + [548] = {0xFCB53430U, 0x00000002U}, /* RGIDSEC_MODID[548]:ARSD07 */ + [549] = {0xFCB53434U, 0x00000002U}, /* RGIDSEC_MODID[549]:ARSD07 */ + [550] = {0xFCB53438U, 0x00000002U}, /* RGIDSEC_MODID[550]:ARSP00 */ + [551] = {0xFCB5343CU, 0x00000002U}, /* RGIDSEC_MODID[551]:ARSP01 */ + [552] = {0xFCB53440U, 0x00000002U}, /* RGIDSEC_MODID[552]:ARSP02 */ + [553] = {0xFCB53444U, 0x00000002U}, /* RGIDSEC_MODID[553]:ARSP03 */ + [554] = {0xFCB53448U, 0x00000002U}, /* RGIDSEC_MODID[554]:ARSP04 */ + [555] = {0xFCB5344CU, 0x00000002U}, /* RGIDSEC_MODID[555]:ARSP05 */ + [556] = {0xFCB53450U, 0x00000002U}, /* RGIDSEC_MODID[556]:ARSP06 */ + [557] = {0xFCB53454U, 0x00000002U}, /* RGIDSEC_MODID[557]:ARSP07 */ + [558] = {0xFCB53458U, 0x00000002U}, /* RGIDSEC_MODID[558]:ARSP08 */ + [559] = {0xFCB5345CU, 0x00000002U}, /* RGIDSEC_MODID[559]:IPMMUDS001 */ + [560] = {0xFCB53460U, 0x00000002U}, /* RGIDSEC_MODID[560]:CKMPER0 */ + [561] = {0xFCB53464U, 0x00000002U}, /* RGIDSEC_MODID[561]:ECMPER0 */ + [562] = {0xFCB53468U, 0x00000002U}, /* RGIDSEC_MODID[562]:FBAPER0 */ + [563] = {0xFCB5346CU, 0x00000002U}, /* RGIDSEC_MODID[563]:FSO0 */ + [564] = {0xFCB53470U, 0x00000002U}, /* RGIDSEC_MODID[564]:FSO1 */ + [565] = {0xFCB53474U, 0x00000002U}, /* RGIDSEC_MODID[565]:FSO10 */ + [566] = {0xFCB53478U, 0x00000002U}, /* RGIDSEC_MODID[566]:FSO2 */ + [567] = {0xFCB5347CU, 0x00000002U}, /* RGIDSEC_MODID[567]:FSO3 */ + [568] = {0xFCB53480U, 0x00000002U}, /* RGIDSEC_MODID[568]:FSO4 */ + [569] = {0xFCB53484U, 0x00000002U}, /* RGIDSEC_MODID[569]:FSO5 */ + [570] = {0xFCB53488U, 0x00000002U}, /* RGIDSEC_MODID[570]:FSO6 */ + [571] = {0xFCB5348CU, 0x00000002U}, /* RGIDSEC_MODID[571]:FSO7 */ + [572] = {0xFCB53490U, 0x00000002U}, /* RGIDSEC_MODID[572]:FSO8 */ + [573] = {0xFCB53494U, 0x00000002U}, /* RGIDSEC_MODID[573]:FSO9 */ + [574] = {0xFCB5349CU, 0x00000002U}, /* RGIDSEC_MODID[574]:ECMSD0 */ + [575] = {0xFCB534A0U, 0x00000002U}, /* RGIDSEC_MODID[575]:IPMMUDS010 */ + [576] = {0xFCB534A4U, 0x00000002U}, /* RGIDSEC_MODID[576]:IPMMUDS011 */ + [577] = {0xFCB534A8U, 0x00000002U}, /* RGIDSEC_MODID[577]:I2C0 */ + [578] = {0xFCB534ACU, 0x00000002U}, /* RGIDSEC_MODID[578]:I2C1 */ + [579] = {0xFCB534B0U, 0x00000002U}, /* RGIDSEC_MODID[579]:I2C2 */ + [580] = {0xFCB534B4U, 0x00000002U}, /* RGIDSEC_MODID[580]:I2C3 */ + [581] = {0xFCB534B8U, 0x00000002U}, /* RGIDSEC_MODID[581]:I2C4 */ + [582] = {0xFCB534BCU, 0x00000002U}, /* RGIDSEC_MODID[582]:I2C5 */ + [583] = {0xFCB534C0U, 0x00000002U}, /* RGIDSEC_MODID[583]:IPMMUDS012 */ + [584] = {0xFCB534C8U, 0x00000002U}, /* RGIDSEC_MODID[584]:IPMMUDS000 */ + [585] = {0xFCB534CCU, 0x00000002U}, /* RGIDSEC_MODID[585]:IPMMUDS013 */ + [586] = {0xFCB534D0U, 0x00000002U}, /* RGIDSEC_MODID[586]:IPMMUDS014 */ + [587] = {0xFCB534D4U, 0x00000002U}, /* RGIDSEC_MODID[587]:IPMMUDS015 */ + [588] = {0xFCB534D8U, 0x00000002U}, /* RGIDSEC_MODID[588]:IPMMUDS002 */ + [589] = {0xFCB534DCU, 0x00000002U}, /* RGIDSEC_MODID[589]:IPMMUDS003 */ + [590] = {0xFCB534E0U, 0x00000002U}, /* RGIDSEC_MODID[590]:IPMMUDS004 */ + [591] = {0xFCB534E4U, 0x00000002U}, /* RGIDSEC_MODID[591]:IPMMUDS005 */ + [592] = {0xFCB534ECU, 0x00000002U}, /* RGIDSEC_MODID[592]:IPMMUDS006 */ + [593] = {0xFCB534F0U, 0x00000002U}, /* RGIDSEC_MODID[593]:IPMMUDS007 */ + [594] = {0xFCB534F4U, 0x00000002U}, /* RGIDSEC_MODID[594]:SYDM1P */ + [595] = {0xFCB534F8U, 0x00000002U}, /* RGIDSEC_MODID[595]:IPMMUDS008 */ + [596] = {0xFCB534FCU, 0x00000002U}, /* RGIDSEC_MODID[596]:SYDM2P */ + [597] = {0xFCB53500U, 0x00000002U}, /* RGIDSEC_MODID[597]:IPMMUDS009 */ + [598] = {0xFCB53640U, 0x00000002U}, /* RGIDSEC_MODID[598]:SYDM100 */ + [599] = {0xFCB53644U, 0x00000002U}, /* RGIDSEC_MODID[599]:SYDM101 */ + [600] = {0xFCB53648U, 0x00000002U}, /* RGIDSEC_MODID[600]:SYDM110 */ + [601] = {0xFCB5364CU, 0x00000002U}, /* RGIDSEC_MODID[601]:SYDM111 */ + [602] = {0xFCB53650U, 0x00000002U}, /* RGIDSEC_MODID[602]:SYDM112 */ + [603] = {0xFCB53654U, 0x00000002U}, /* RGIDSEC_MODID[603]:SYDM113 */ + [604] = {0xFCB53658U, 0x00000002U}, /* RGIDSEC_MODID[604]:SYDM114 */ + [605] = {0xFCB5365CU, 0x00000002U}, /* RGIDSEC_MODID[605]:SYDM115 */ + [606] = {0xFCB53660U, 0x00000002U}, /* RGIDSEC_MODID[606]:SYDM102 */ + [607] = {0xFCB53664U, 0x00000002U}, /* RGIDSEC_MODID[607]:SYDM103 */ + [608] = {0xFCB53668U, 0x00000002U}, /* RGIDSEC_MODID[608]:SYDM104 */ + [609] = {0xFCB5366CU, 0x00000002U}, /* RGIDSEC_MODID[609]:SYDM105 */ + [610] = {0xFCB53670U, 0x00000002U}, /* RGIDSEC_MODID[610]:SYDM106 */ + [611] = {0xFCB53674U, 0x00000002U}, /* RGIDSEC_MODID[611]:SYDM107 */ + [612] = {0xFCB53678U, 0x00000002U}, /* RGIDSEC_MODID[612]:SYDM108 */ + [613] = {0xFCB5367CU, 0x00000002U}, /* RGIDSEC_MODID[613]:SYDM109 */ + [614] = {0xFCB53680U, 0x00000002U}, /* RGIDSEC_MODID[614]:SYDM200 */ + [615] = {0xFCB53684U, 0x00000002U}, /* RGIDSEC_MODID[615]:SYDM201 */ + [616] = {0xFCB53688U, 0x00000002U}, /* RGIDSEC_MODID[616]:SYDM210 */ + [617] = {0xFCB5368CU, 0x00000002U}, /* RGIDSEC_MODID[617]:SYDM211 */ + [618] = {0xFCB53690U, 0x00000002U}, /* RGIDSEC_MODID[618]:SYDM212 */ + [619] = {0xFCB53694U, 0x00000002U}, /* RGIDSEC_MODID[619]:SYDM213 */ + [620] = {0xFCB53698U, 0x00000002U}, /* RGIDSEC_MODID[620]:SYDM214 */ + [621] = {0xFCB5369CU, 0x00000002U}, /* RGIDSEC_MODID[621]:SYDM215 */ + [622] = {0xFCB536A0U, 0x00000002U}, /* RGIDSEC_MODID[622]:SYDM202 */ + [623] = {0xFCB536A4U, 0x00000002U}, /* RGIDSEC_MODID[623]:SYDM203 */ + [624] = {0xFCB536A8U, 0x00000002U}, /* RGIDSEC_MODID[624]:SYDM204 */ + [625] = {0xFCB536ACU, 0x00000002U}, /* RGIDSEC_MODID[625]:SYDM205 */ + [626] = {0xFCB536B0U, 0x00000002U}, /* RGIDSEC_MODID[626]:SYDM206 */ + [627] = {0xFCB536B4U, 0x00000002U}, /* RGIDSEC_MODID[627]:SYDM207 */ + [628] = {0xFCB536B8U, 0x00000002U}, /* RGIDSEC_MODID[628]:SYDM208 */ + [629] = {0xFCB536BCU, 0x00000002U}, /* RGIDSEC_MODID[629]:SYDM209 */ + [631] = {0xFDDB9624U, 0x00000001U}, /* RGIDSEC_MODID[630]:ARCC */ + [630] = {0xFDDB9638U, 0x00000001U}, /* RGIDSEC_MODID[631]:ARRTRAM */ + [632] = {0xFCB53424U, 0x00000002U}, /* RGIDSEC_MODID[632]:RSV0 */ +}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +/* T.B.D. */ +#pragma ghs section rodata=".rgid_axi_tbl" +const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[] = { + [0] = {0xFD482010U, 0x0000003FU}, /* RGIDR_MODID[4]:ARRT01 */ + [1] = {0xFD482014U, 0x0000003FU}, /* RGIDR_MODID[5]:ARRT02 */ + [2] = {0xFDA02048U, 0x0000003FU}, /* RGIDR_MODID[45]:ARS01 */ + [3] = {0xFDA0204CU, 0x0000003FU}, /* RGIDR_MODID[46]:ARS02 */ + [4] = {0xFCB62028U, 0x0000003FU}, /* RGIDR_MODID[93]:ARSP31 */ + [5] = {0xFCB6202CU, 0x0000003FU}, /* RGIDR_MODID[94]:ARSP32 */ + [6] = {0xFCB92004U, 0x0000003FU}, /* RGIDR_MODID[106]:ARSP41 */ + [7] = {0xFCB92008U, 0x0000003FU}, /* RGIDR_MODID[107]:ARSP42 */ + [8] = {0xFCF82140U, 0x0000003FU}, /* RGIDR_MODID[210]:ARHC1 */ + [9] = {0xFCF82144U, 0x0000003FU}, /* RGIDR_MODID[211]:ARHC2 */ + [10] = {0xFDC22004U, 0x0000003FU}, /* RGIDR_MODID[226]:ARRC1 */ + [11] = {0xFDC22008U, 0x0000003FU}, /* RGIDR_MODID[227]:ARRC2 */ + [12] = {0xFD442060U, 0x0000003FU}, /* RGIDR_MODID[268]:ARRD1 */ + [13] = {0xFD442064U, 0x0000003FU}, /* RGIDR_MODID[269]:ARRD2 */ + [14] = {0xFD442084U, 0x0000003FU}, /* RGIDR_MODID[277]:ARRT1 */ + [15] = {0xFD442088U, 0x0000003FU}, /* RGIDR_MODID[278]:ARRT2 */ + [18] = {0xFF862004U, 0x0000003FU}, /* RGIDR_MODID[452]:ARSC1 */ + [19] = {0xFF862008U, 0x0000003FU}, /* RGIDR_MODID[453]:ARSC2 */ + [16] = {0xFF862028U, 0x0000003FU}, /* RGIDR_MODID[461]:ARSTM1 */ + [17] = {0xFF862038U, 0x0000003FU}, /* RGIDR_MODID[464]:ARSTM2 */ + [20] = {0xFDDC2004U, 0x0000003FU}, /* RGIDR_MODID[498]:AXIARNMM */ + [21] = {0xFDDC200CU, 0x0000003FU}, /* RGIDR_MODID[500]:ARSM1 */ + [22] = {0xFDDC2010U, 0x0000003FU}, /* RGIDR_MODID[501]:ARSM2 */ + [23] = {0xFCB52004U, 0x0000003FU}, /* RGIDR_MODID[540]:ARSD01 */ + [24] = {0xFCB52008U, 0x0000003FU}, /* RGIDR_MODID[541]:ARSD02 */ + [25] = {0xFCB5203CU, 0x0000003FU}, /* RGIDR_MODID[551]:ARSP01 */ + [26] = {0xFCB52040U, 0x0000003FU}, /* RGIDR_MODID[552]:ARSP02 */ + [27] = {0xFD482410U, 0x00000000U}, /* RGIDW_MODID[4]:ARRT01 */ + [28] = {0xFD482414U, 0x00000000U}, /* RGIDW_MODID[5]:ARRT02 */ + [29] = {0xFDA02448U, 0x00000000U}, /* RGIDW_MODID[45]:ARS01 */ + [30] = {0xFDA0244CU, 0x00000000U}, /* RGIDW_MODID[46]:ARS02 */ + [31] = {0xFCB62428U, 0x00000000U}, /* RGIDW_MODID[93]:ARSP31 */ + [32] = {0xFCB6242CU, 0x00000000U}, /* RGIDW_MODID[94]:ARSP32 */ + [33] = {0xFCB92404U, 0x00000000U}, /* RGIDW_MODID[106]:ARSP41 */ + [34] = {0xFCB92408U, 0x00000000U}, /* RGIDW_MODID[107]:ARSP42 */ + [35] = {0xFCF82540U, 0x00000000U}, /* RGIDW_MODID[210]:ARHC1 */ + [36] = {0xFCF82544U, 0x00000000U}, /* RGIDW_MODID[211]:ARHC2 */ + [37] = {0xFDC22404U, 0x00000000U}, /* RGIDW_MODID[226]:ARRC1 */ + [38] = {0xFDC22408U, 0x00000011U}, /* RGIDW_MODID[227]:ARRC2 */ + [39] = {0xFD442460U, 0x00000000U}, /* RGIDW_MODID[268]:ARRD1 */ + [40] = {0xFD442464U, 0x00000000U}, /* RGIDW_MODID[269]:ARRD2 */ + [41] = {0xFD442484U, 0x00000000U}, /* RGIDW_MODID[277]:ARRT1 */ + [42] = {0xFD442488U, 0x00000000U}, /* RGIDW_MODID[278]:ARRT2 */ + [45] = {0xFF862404U, 0x00000000U}, /* RGIDW_MODID[452]:ARSC1 */ + [46] = {0xFF862408U, 0x00000000U}, /* RGIDW_MODID[453]:ARSC2 */ + [43] = {0xFF862428U, 0x00000000U}, /* RGIDW_MODID[461]:ARSTM1 */ + [44] = {0xFF862438U, 0x00000000U}, /* RGIDW_MODID[464]:ARSTM2 */ + [47] = {0xFDDC2404U, 0x00000000U}, /* RGIDW_MODID[498]:AXIARNMM */ + [48] = {0xFDDC240CU, 0x00000000U}, /* RGIDW_MODID[500]:ARSM1 */ + [49] = {0xFDDC2410U, 0x00000000U}, /* RGIDW_MODID[501]:ARSM2 */ + [50] = {0xFCB52404U, 0x00000000U}, /* RGIDW_MODID[540]:ARSD01 */ + [51] = {0xFCB52408U, 0x00000000U}, /* RGIDW_MODID[541]:ARSD02 */ + [52] = {0xFCB5243CU, 0x00000000U}, /* RGIDW_MODID[551]:ARSP01 */ + [53] = {0xFCB52440U, 0x00000000U}, /* RGIDW_MODID[552]:ARSP02 */ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +const uint32_t g_rgid_rtdma_setting_value[RTDMA_MODULE_MAX][RTDMA_CH_MAX][2U] = { + {/* Module0 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, + {/* Module1 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, + {/* Module2 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, + {/* Module3 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + } +}; + +const uint32_t g_rgid_sysdma_setting_value[SYSDMA_MODULE_MAX][SYSDMA_CH_MAX][2U] = { + {/* Module0 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {SYSDMA_EN, RGID_2}, /* CH0 */ + [1] = {SYSDMA_EN, RGID_2}, /* CH1 */ + [2] = {SYSDMA_EN, RGID_2}, /* CH2 */ + [3] = {SYSDMA_EN, RGID_2}, /* CH3 */ + [4] = {SYSDMA_EN, RGID_2}, /* CH4 */ + [5] = {SYSDMA_EN, RGID_2}, /* CH5 */ + [6] = {SYSDMA_EN, RGID_2}, /* CH6 */ + [7] = {SYSDMA_EN, RGID_2}, /* CH7 */ + [8] = {SYSDMA_EN, RGID_2}, /* CH8 */ + [9] = {SYSDMA_EN, RGID_2}, /* CH9 */ + [10] = {SYSDMA_EN, RGID_2}, /* CH10 */ + [11] = {SYSDMA_EN, RGID_2}, /* CH11 */ + [12] = {SYSDMA_EN, RGID_2}, /* CH12 */ + [13] = {SYSDMA_EN, RGID_2}, /* CH13 */ + [14] = {SYSDMA_EN, RGID_2}, /* CH14 */ + [15] = {SYSDMA_EN, RGID_2} /* CH15 */ + }, + {/* Module1 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {SYSDMA_EN, RGID_2}, /* CH0 */ + [1] = {SYSDMA_EN, RGID_2}, /* CH1 */ + [2] = {SYSDMA_EN, RGID_2}, /* CH2 */ + [3] = {SYSDMA_EN, RGID_2}, /* CH3 */ + [4] = {SYSDMA_EN, RGID_2}, /* CH4 */ + [5] = {SYSDMA_EN, RGID_2}, /* CH5 */ + [6] = {SYSDMA_EN, RGID_2}, /* CH6 */ + [7] = {SYSDMA_EN, RGID_2}, /* CH7 */ + [8] = {SYSDMA_EN, RGID_2}, /* CH8 */ + [9] = {SYSDMA_EN, RGID_2}, /* CH9 */ + [10] = {SYSDMA_EN, RGID_2}, /* CH10 */ + [11] = {SYSDMA_EN, RGID_2}, /* CH11 */ + [12] = {SYSDMA_EN, RGID_2}, /* CH12 */ + [13] = {SYSDMA_EN, RGID_2}, /* CH13 */ + [14] = {SYSDMA_EN, RGID_2}, /* CH14 */ + [15] = {SYSDMA_EN, RGID_2} /* CH15 */ + }, +}; + +/* When V4H, this table is used as RT-VRAM0. */ +const RTRAM_PROTECTION_STRUCTUR g_rtsram_protection_table[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTSRAM_ICUMX_IPL_AREA] = {NOT_USED_VALUE, {0x0000FFCAU, 0x0000FFEEU}}, /* not used for address value */ + [RTSRAM_ICUMX_FW_AREA] = {0xEB240000U, {0x0004FFEEU, 0x0004FFEEU}}, + [2] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [3] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* this table is temporary setting for RT-VRAM protection */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table_1[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM_BLANK_AREA] = {NOT_USED_VALUE, {0x0000FFF8U, 0x0000FFF8U}}, /* not used for address value */ + [RTVRAM_EXTEND_CACHE_AREA] = {0xE2010000U, {0x0000BFF8U, 0x0000BFF8U}}, + [RTVRAM_RTOS_AREA] = {0xE2100000U, {0x0000FFD9U, 0x0000FFD9U}}, + [3] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* this table is finaly setting for RT-VRAM protection */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table_2[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM_BLANK_AREA] = {NOT_USED_VALUE, {0x0000FFF8U, 0x0000FFF8U}}, /* not used for address value */ + [RTVRAM_EXTEND_CACHE_AREA] = {0xE2010000U, {0x0000BFFFU, 0x0000BFFFU}}, + [RTVRAM_RTOS_AREA] = {0xE2100000U, {0x0000FFD9U, 0x0000FFD9U}}, + [3] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX] = { + /* access Secure */ + /* address R | W R|W */ + [SYSTEM_RAM_ALL] = {NOT_USED_VALUE, {0xFFD0FFD0U, 0x00000000U}}, /* not used for address value */ + [1] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [2] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [3] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX] = { + /* access secure */ + /* address R | W R|W */ + [RTVRAM_EXTEND_AREA] = {NOT_USED_VALUE, {0xBFFFBFFFU, 0x00000000U}}, /* not used for address value */ + [SDRAM_BLANK_AREA] = {0x0401C00000U, {0xFFC0FFC0U, 0x00000000U}}, + [SDRAM_PROTECT_AREA] = {0x0406400000U, {0xFFC8FFC8U, 0x00000000U}}, + [SDRAM_PUBLIC_AREA] = {0x0407E00000U, {0xFFC0FFC0U, 0x00000000U}}, + [4] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [16] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [17] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [18] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [19] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [20] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [21] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [22] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [23] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [24] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [25] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [26] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [27] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [28] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [29] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [30] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [31] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [32] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [33] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [34] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [35] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [36] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [37] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [38] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [39] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [40] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [41] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [42] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [43] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [44] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [45] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [46] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [47] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [48] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [49] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [50] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [51] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [52] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [53] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [54] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [55] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [56] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [57] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [58] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [59] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [60] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [61] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [62] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [63] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4h.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4h.c new file mode 100644 index 0000000..6aa72f0 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4h.c @@ -0,0 +1,4084 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table + ******************************************************************************/ +/****************************************************************************** + * @file cnf_tbl.c + * - Version : 0.11 + * @brief Configuration table for V4H. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 23.05.2022 0.02 Integration of S4 and V4H + * Renamed from conf_tbl.c to cnf_tbl_v4h.c. + * : 22.11.2022 0.03 Removed QoS configuration table + * : 13.11.2023 0.04 Added setting table for CCI MPU GID register. + * : 11.01.2024 0.05 Updated writing privilege to System RAM. + * Fixed setting value of read/write permissions + * for RT-VRAM1 area2. + * Update Region ID settings. + * The divided areas of SDRAM have been changed. + * : 11.07.2024 0.06 Updated AXI timeout setting value. + * Removed FDT_PAP in g_fdt_tbl. + * : 29.08.2024 0.07 Updated Region ID and RAM protection setting + * for QNX. + * : 05.12.2024 0.08 Update RAM protection settings for ICCOM + * memory area (SDRAM Area5). + * Update Region ID settings for VSPD and VSPX. + * Update Region ID settings for IPMMU. + * : 16.12.2024 0.09 Updated Region ID setting. + * Updated Region ID setting and RAM protection + * setting for booting CR52 3 cores. + * Updated AXI timeout setting value. + * Added IMP Region ID table. + * Added IPMMU Region ID table. + * : 17.03.2025 0.10 Updated AXI timeout setting value. + * : 26.05.2025 0.11 Updated RAM protection settings for + * protection area. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#define RTDMA_EN (0x00000002U) +#define SYSDMA_EN (0x00003FF4U) + +#pragma ghs section rodata=".qosbw_tbl" +/* not used for V4H */ +const QOS_SETTING_TABLE g_qosbw_tbl[] = {0}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".qoswt_tbl" +/* not used for V4H */ +const QOS_SETTING_TABLE g_qoswt_tbl[] = {0}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_m_tbl" +const REGION_ID_SETTING_TABLE g_rgid_m_tbl[] = { + [0] = {0xFCF81000U, 0x00000002U}, /* RGIDM_MODID[0]:PCI0 */ + [1] = {0xFCF81020U, 0x00000002U}, /* RGIDM_MODID[1]:PCI1 */ + [2] = {0xFCF81024U, 0x00000002U}, /* RGIDM_MODID[2]:PCI2 */ + [3] = {0xFCF81034U, 0x00000002U}, /* RGIDM_MODID[3]:PCI3 */ + [4] = {0xFCF81010U, 0x00000002U}, /* RGIDM_MODID[4]:AVB0 */ + [5] = {0xFCF81014U, 0x00000001U}, /* RGIDM_MODID[5]:AVB1 */ + [6] = {0xFCF81018U, 0x00000001U}, /* RGIDM_MODID[6]:AVB2 */ + [7] = {0xFCF81040U, 0x00000002U}, /* RGIDM_MODID[7]:TSN */ + [8] = {0xFDC21004U, 0x00000000U}, /* RGIDM_MODID[8]:CR0 */ + [9] = {0xFDC2100CU, 0x00000000U}, /* RGIDM_MODID[9]:DCLS_ICUMX */ + [10] = {0xFDC21010U, 0x00000000U}, /* RGIDM_MODID[10]:ICUMX */ + [11] = {0xFDC21014U, 0x00000000U}, /* RGIDM_MODID[11]:SDMAC_ICUMX */ + [12] = {0xFD441018U, 0x00000001U}, /* RGIDM_MODID[12]:CR52SS0 */ + [13] = {0xFD44105CU, 0x00000001U}, /* RGIDM_MODID[13]:CR52SS1 */ + [14] = {0xFD441060U, 0x00000006U}, /* RGIDM_MODID[14]:CR52SS2 */ + [15] = {0xFD44101CU, 0x00000003U}, /* RGIDM_MODID[15]:CSD */ + [16] = {0xFD441024U, 0x00000002U}, /* RGIDM_MODID[16]:INTAP0 */ + [17] = {0xFC861018U, 0x00000002U}, /* RGIDM_MODID[17]:FBABUSTOP0 */ + [18] = {0xFC86101CU, 0x00000002U}, /* RGIDM_MODID[18]:FBABUSTOP1 */ + [19] = {0xFCB51020U, 0x00000002U}, /* RGIDM_MODID[19]:SDHI0 */ + [20] = {0xFCB51010U, 0x00000001U}, /* RGIDM_MODID[20]:FRAY */ + [21] = {0xFCB51014U, 0x00000002U}, /* RGIDM_MODID[21]:IPC */ + [22] = {0xFC811000U, 0x00000002U}, /* RGIDM_MODID[22]:AXMM2AXSTM */ + [23] = {0xFC811004U, 0x00000003U}, /* RGIDM_MODID[23]:CSDE0 */ + [24] = {0xFC811008U, 0x00000003U}, /* RGIDM_MODID[24]:CSDE1 */ + [25] = {0xFC881004U, 0x00000002U}, /* RGIDM_MODID[25]:FBABUSIR0 */ + [26] = {0xFC881008U, 0x00000002U}, /* RGIDM_MODID[26]:FBABUSIR1 */ + [27] = {0xFC88100CU, 0x00000002U}, /* RGIDM_MODID[27]:FBABUSIR2 */ + [28] = {0xFC881010U, 0x00000002U}, /* RGIDM_MODID[28]:FBABUSIR3 */ + [29] = {0xFC881014U, 0x00000002U}, /* RGIDM_MODID[29]:FBABUSIR4 */ + [30] = {0xFC011014U, 0x00000002U}, /* RGIDM_MODID[30]:RGX0 */ + [31] = {0xFC681004U, 0x00000002U}, /* RGIDM_MODID[31]:FBABUSVC */ + [32] = {0xFC681008U, 0x00000005U}, /* RGIDM_MODID[32]:FCPCS */ + [33] = {0xFC681010U, 0x00000002U}, /* RGIDM_MODID[33]:IMR00 */ + [34] = {0xFC681014U, 0x00000002U}, /* RGIDM_MODID[34]:IMR01 */ + [35] = {0xFC681024U, 0x00000002U}, /* RGIDM_MODID[35]:IMR10 */ + [36] = {0xFC681028U, 0x00000002U}, /* RGIDM_MODID[36]:IMR11 */ + [37] = {0xFC68100CU, 0x00000002U}, /* RGIDM_MODID[37]:IMR20 */ + [38] = {0xFC681018U, 0x00000002U}, /* RGIDM_MODID[38]:IMR21 */ + [39] = {0xFC681040U, 0x00000002U}, /* RGIDM_MODID[39]:IMS0 */ + [40] = {0xFC681044U, 0x00000002U}, /* RGIDM_MODID[40]:IMS1 */ + [41] = {0xFC681048U, 0x00000005U}, /* RGIDM_MODID[41]:IV1ES */ + [42] = {0xFEBE1000U, 0x00000002U}, /* RGIDM_MODID[42]:DSITLINK0 */ + [43] = {0xFEBE1004U, 0x00000002U}, /* RGIDM_MODID[43]:DSTLINK1 */ + [44] = {0xFEBE1008U, 0x00000002U}, /* RGIDM_MODID[44]:FBABUSVIO */ + [45] = {0xFEBE1014U, 0x00000002U}, /* RGIDM_MODID[45]:FCPVD0 */ + [46] = {0xFEBE1018U, 0x00000002U}, /* RGIDM_MODID[46]:FCPVD1 */ + [47] = {0xFEBE101CU, 0x00000002U}, /* RGIDM_MODID[47]:FCPVX0 */ + [48] = {0xFEBE1020U, 0x00000002U}, /* RGIDM_MODID[48]:FCPVX1 */ + [49] = {0xFEBF1020U, 0x00000002U}, /* RGIDM_MODID[49]:ISP00 */ + [50] = {0xFEBF1024U, 0x00000002U}, /* RGIDM_MODID[50]:ISP01 */ + [51] = {0xFEBF1000U, 0x00000002U}, /* RGIDM_MODID[51]:ISP02 */ + [52] = {0xFEBF1004U, 0x00000002U}, /* RGIDM_MODID[52]:ISP03 */ + [53] = {0xFEBF1008U, 0x00000002U}, /* RGIDM_MODID[53]:ISP04 */ + [54] = {0xFEBF1028U, 0x00000002U}, /* RGIDM_MODID[54]:ISP10 */ + [55] = {0xFEBF102CU, 0x00000002U}, /* RGIDM_MODID[55]:ISP11 */ + [56] = {0xFEBF1044U, 0x00000002U}, /* RGIDM_MODID[56]:ISP12 */ + [57] = {0xFEBF104CU, 0x00000002U}, /* RGIDM_MODID[57]:ISP13 */ + [58] = {0xFEBF1050U, 0x00000002U}, /* RGIDM_MODID[58]:ISP14 */ + [59] = {0xFEBF1010U, 0x00000002U}, /* RGIDM_MODID[59]:VIN0 */ + [60] = {0xFEBF1014U, 0x00000002U}, /* RGIDM_MODID[60]:VIN1 */ + [61] = {0xFC311004U, 0x00000002U}, /* RGIDM_MODID[61]:FBABUSVIP0 */ + [62] = {0xFC311010U, 0x00000002U}, /* RGIDM_MODID[62]:SMPO */ + [63] = {0xFC311018U, 0x00000002U}, /* RGIDM_MODID[63]:SMPS */ + [64] = {0xFC31101CU, 0x00000002U}, /* RGIDM_MODID[64]:UMFL */ + [65] = {0xFC341018U, 0x00000002U}, /* RGIDM_MODID[65]:PAP */ + [66] = {0xFC341028U, 0x00000002U}, /* RGIDM_MODID[66]:FBABUSVIP1 */ + [67] = {0xFC401000U, 0x00000002U}, /* RGIDM_MODID[67]:DSP00 */ + [68] = {0xFC401004U, 0x00000002U}, /* RGIDM_MODID[68]:DSP01 */ + [69] = {0xFC401008U, 0x00000002U}, /* RGIDM_MODID[69]:DSP10 */ + [70] = {0xFC40100CU, 0x00000002U}, /* RGIDM_MODID[70]:DSP11 */ + [71] = {0xFC401010U, 0x00000002U}, /* RGIDM_MODID[71]:DSP20 */ + [72] = {0xFC401014U, 0x00000002U}, /* RGIDM_MODID[72]:DSP21 */ + [73] = {0xFC401018U, 0x00000002U}, /* RGIDM_MODID[73]:DSP30 */ + [74] = {0xFC40101CU, 0x00000002U}, /* RGIDM_MODID[74]:DSP31 */ + [75] = {0xFDDBF500U, 0x0000000EU}, /* RGIDM_MODID[75]:VRAM_R */ + [76] = {0xFDDBF504U, 0x0000000EU}, /* RGIDM_MODID[76]:VRAM_W */ +}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_r_tbl" +const REGION_ID_SETTING_TABLE g_rgid_r_tbl[] = { + [0] = {0xFD482000U, 0x0000000FU}, /* RGIDR_MODID[0]:ARMGC0*/ + [1] = {0xFD482004U, 0x0000000FU}, /* RGIDR_MODID[1]:ARMGC1*/ + [2] = {0xFD482008U, 0x00000000U}, /* RGIDR_MODID[2]:ARMGC2*/ + [3] = {0xFD48200CU, 0x0000000FU}, /* RGIDR_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDR_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDR_MODID[5]:ARRT02*/ + [4] = {0xFD482018U, 0x0000000FU}, /* RGIDR_MODID[6]:ARRT03*/ + [5] = {0xFD48201CU, 0x0000000FU}, /* RGIDR_MODID[7]:ARRT04*/ + [6] = {0xFD482020U, 0x0000000FU}, /* RGIDR_MODID[8]:ARRT05*/ + [7] = {0xFD482024U, 0x0000000FU}, /* RGIDR_MODID[9]:ARRT06*/ + [8] = {0xFD482028U, 0x0000000FU}, /* RGIDR_MODID[10]:ARRT07*/ + [9] = {0xFD48202CU, 0x00000000U}, /* RGIDR_MODID[11]:ARRT08*/ + [10] = {0xFD482030U, 0x00000001U}, /* RGIDR_MODID[12]:LIFEC0*/ + [11] = {0xFD482034U, 0x0000000EU}, /* RGIDR_MODID[13]:SWDT*/ + [12] = {0xFD482038U, 0x0000006EU}, /* RGIDR_MODID[14]:TMU0*/ + [13] = {0xFD48203CU, 0x0000000EU}, /* RGIDR_MODID[15]:WDT*/ + [14] = {0xFD482040U, 0x0000000EU}, /* RGIDR_MODID[16]:WWDT0*/ + [15] = {0xFD482044U, 0x0000000EU}, /* RGIDR_MODID[17]:WWDT1*/ + [16] = {0xFD482048U, 0x0000000EU}, /* RGIDR_MODID[18]:WWDT2*/ + [17] = {0xFD48204CU, 0x0000000EU}, /* RGIDR_MODID[19]:WWDT3*/ + [18] = {0xFD482050U, 0x0000000EU}, /* RGIDR_MODID[20]:WWDT4*/ + [19] = {0xFD482054U, 0x0000000EU}, /* RGIDR_MODID[21]:WWDT5*/ + [20] = {0xFD482058U, 0x0000000EU}, /* RGIDR_MODID[22]:WWDT6*/ + [21] = {0xFD482068U, 0x0000000FU}, /* RGIDR_MODID[23]:ECMRT3*/ + [22] = {0xFDA02000U, 0x0000000EU}, /* RGIDR_MODID[24]:ADVFSC*/ + [23] = {0xFDA02004U, 0x0000000FU}, /* RGIDR_MODID[25]:APMU0*/ + [24] = {0xFDA02008U, 0x00000002U}, /* RGIDR_MODID[26]:APMU1*/ + [25] = {0xFDA0200CU, 0x00000000U}, /* RGIDR_MODID[27]:APMU10*/ + [26] = {0xFDA02010U, 0x00000000U}, /* RGIDR_MODID[28]:APMU11*/ + [27] = {0xFDA02014U, 0x00000000U}, /* RGIDR_MODID[29]:APMU12*/ + [28] = {0xFDA02018U, 0x00000000U}, /* RGIDR_MODID[30]:APMU13*/ + [29] = {0xFDA0201CU, 0x00000000U}, /* RGIDR_MODID[31]:APMU14*/ + [30] = {0xFDA02020U, 0x00000000U}, /* RGIDR_MODID[32]:APMU15*/ + [31] = {0xFDA02024U, 0x00000004U}, /* RGIDR_MODID[33]:APMU2*/ + [32] = {0xFDA02028U, 0x00000004U}, /* RGIDR_MODID[34]:APMU3*/ + [33] = {0xFDA0202CU, 0x00000000U}, /* RGIDR_MODID[35]:APMU4*/ + [34] = {0xFDA02030U, 0x00000000U}, /* RGIDR_MODID[36]:APMU5*/ + [35] = {0xFDA02034U, 0x00000000U}, /* RGIDR_MODID[37]:APMU6*/ + [36] = {0xFDA02038U, 0x00000000U}, /* RGIDR_MODID[38]:APMU7*/ + [37] = {0xFDA0203CU, 0x00000000U}, /* RGIDR_MODID[39]:APMU8*/ + [38] = {0xFDA02040U, 0x00000000U}, /* RGIDR_MODID[40]:APMU9*/ + [39] = {0xFDA02044U, 0x0000000FU}, /* RGIDR_MODID[41]:ARS00*/ + /* After setting */ /* RGIDR_MODID[42]:ARS01*/ + /* After setting */ /* RGIDR_MODID[43]:ARS02*/ + [40] = {0xFDA02050U, 0x0000000FU}, /* RGIDR_MODID[44]:ARS03*/ + [41] = {0xFDA02054U, 0x0000000FU}, /* RGIDR_MODID[45]:ARS04*/ + [42] = {0xFDA02058U, 0x0000000FU}, /* RGIDR_MODID[46]:ARS05*/ + [43] = {0xFDA0205CU, 0x0000000FU}, /* RGIDR_MODID[47]:ARS06*/ + [44] = {0xFDA02060U, 0x0000000FU}, /* RGIDR_MODID[48]:ARS07*/ + [45] = {0xFDA02064U, 0x00000000U}, /* RGIDR_MODID[49]:ARS08*/ + [46] = {0xFDA02068U, 0x0000000EU}, /* RGIDR_MODID[50]:CMT0*/ + [47] = {0xFDA0206CU, 0x0000000EU}, /* RGIDR_MODID[51]:CMT1*/ + [48] = {0xFDA02070U, 0x0000000EU}, /* RGIDR_MODID[52]:CMT2*/ + [49] = {0xFDA02074U, 0x0000000EU}, /* RGIDR_MODID[53]:CMT3*/ + [50] = {0xFDA02078U, 0x0000000AU}, /* RGIDR_MODID[54]:CKM*/ + [51] = {0xFDA0207CU, 0x0000000EU}, /* RGIDR_MODID[55]:DBE*/ + [52] = {0xFDA02080U, 0x0000000EU}, /* RGIDR_MODID[56]:IRQC*/ + [53] = {0xFDA02084U, 0x0000000FU}, /* RGIDR_MODID[57]:ECMPS0*/ + [54] = {0xFDA02088U, 0x0000000BU}, /* RGIDR_MODID[58]:OTP0*/ + [55] = {0xFDA0208CU, 0x0000000FU}, /* RGIDR_MODID[59]:OTP1*/ + [56] = {0xFDA0209CU, 0x0000000EU}, /* RGIDR_MODID[60]:SCMT*/ + [57] = {0xFDA020A8U, 0x0000004EU}, /* RGIDR_MODID[61]:TSC1*/ + [58] = {0xFDA020ACU, 0x0000004EU}, /* RGIDR_MODID[62]:TSC2*/ + [59] = {0xFDA020B0U, 0x0000004EU}, /* RGIDR_MODID[63]:TSC3*/ + [60] = {0xFDA020B4U, 0x0000004EU}, /* RGIDR_MODID[64]:TSC4*/ + [61] = {0xFDA020B8U, 0x00000006U}, /* RGIDR_MODID[65]:UCMT*/ + [62] = {0xFDA02100U, 0x0000006FU}, /* RGIDR_MODID[66]:CPG0*/ + [63] = {0xFDA02104U, 0x0000000AU}, /* RGIDR_MODID[67]:CPG1*/ + [64] = {0xFDA02108U, 0x0000004EU}, /* RGIDR_MODID[68]:CPG2*/ + [65] = {0xFDA0210CU, 0x00000028U}, /* RGIDR_MODID[69]:CPG3*/ + [66] = {0xFDA02110U, 0x0000006FU}, /* RGIDR_MODID[70]:PFC00*/ + [67] = {0xFDA02114U, 0x0000000AU}, /* RGIDR_MODID[71]:PFC01*/ + [68] = {0xFDA02118U, 0x0000004EU}, /* RGIDR_MODID[72]:PFC02*/ + [69] = {0xFDA0211CU, 0x00000028U}, /* RGIDR_MODID[73]:PFC03*/ + [70] = {0xFDA02120U, 0x0000006FU}, /* RGIDR_MODID[74]:PFC10*/ + [71] = {0xFDA02124U, 0x0000000AU}, /* RGIDR_MODID[75]:PFC11*/ + [72] = {0xFDA02128U, 0x0000004EU}, /* RGIDR_MODID[76]:PFC12*/ + [73] = {0xFDA0212CU, 0x00000028U}, /* RGIDR_MODID[77]:PFC13*/ + [74] = {0xFDA02130U, 0x0000006FU}, /* RGIDR_MODID[78]:PFC20*/ + [75] = {0xFDA02134U, 0x0000000AU}, /* RGIDR_MODID[79]:PFC21*/ + [76] = {0xFDA02138U, 0x0000004EU}, /* RGIDR_MODID[80]:PFC22*/ + [77] = {0xFDA0213CU, 0x00000028U}, /* RGIDR_MODID[81]:PFC23*/ + [78] = {0xFDA02140U, 0x0000006FU}, /* RGIDR_MODID[82]:PFC30*/ + [79] = {0xFDA02144U, 0x0000000AU}, /* RGIDR_MODID[83]:PFC31*/ + [80] = {0xFDA02148U, 0x0000004EU}, /* RGIDR_MODID[84]:PFC32*/ + [81] = {0xFDA0214CU, 0x00000028U}, /* RGIDR_MODID[85]:PFC33*/ + [82] = {0xFDA02150U, 0x0000006FU}, /* RGIDR_MODID[86]:PFCS0*/ + [83] = {0xFDA02154U, 0x0000000AU}, /* RGIDR_MODID[87]:PFCS1*/ + [84] = {0xFDA02158U, 0x0000004EU}, /* RGIDR_MODID[88]:PFCS2*/ + [85] = {0xFDA0215CU, 0x00000028U}, /* RGIDR_MODID[89]:PFCS3*/ + [86] = {0xFDA02160U, 0x0000006FU}, /* RGIDR_MODID[90]:RESET0*/ + [87] = {0xFDA02164U, 0x0000000AU}, /* RGIDR_MODID[91]:RESET1*/ + [88] = {0xFDA02168U, 0x0000004EU}, /* RGIDR_MODID[92]:RESET2*/ + [89] = {0xFDA0216CU, 0x00000028U}, /* RGIDR_MODID[93]:RESET3*/ + [90] = {0xFDA02170U, 0x0000006FU}, /* RGIDR_MODID[94]:SYS0*/ + [91] = {0xFDA02174U, 0x0000000AU}, /* RGIDR_MODID[95]:SYS1*/ + [92] = {0xFDA02178U, 0x0000004EU}, /* RGIDR_MODID[96]:SYS2*/ + [93] = {0xFDA0217CU, 0x00000028U}, /* RGIDR_MODID[97]:SYS3*/ + [94] = {0xFCB62000U, 0x0000000EU}, /* RGIDR_MODID[98]:DMAMSI0*/ + [95] = {0xFCB62004U, 0x0000000EU}, /* RGIDR_MODID[99]:DMAMSI1*/ + [96] = {0xFCB62008U, 0x0000000EU}, /* RGIDR_MODID[100]:DMAMSI2*/ + [97] = {0xFCB6200CU, 0x0000000EU}, /* RGIDR_MODID[101]:DMAMSI3*/ + [98] = {0xFCB62010U, 0x0000000EU}, /* RGIDR_MODID[102]:DMAMSI4*/ + [99] = {0xFCB62014U, 0x0000000EU}, /* RGIDR_MODID[103]:DMAMSI5*/ + [100] = {0xFCB62018U, 0x0000000FU}, /* RGIDR_MODID[104]:ECMSP3*/ + [101] = {0xFCB62024U, 0x0000000FU}, /* RGIDR_MODID[105]:ARSP30*/ + /* After setting */ /* RGIDR_MODID[106]:ARSP31*/ + /* After setting */ /* RGIDR_MODID[107]:ARSP32*/ + [102] = {0xFCB62030U, 0x0000000FU}, /* RGIDR_MODID[108]:ARSP33*/ + [103] = {0xFCB62034U, 0x0000000FU}, /* RGIDR_MODID[109]:ARSP34*/ + [104] = {0xFCB62038U, 0x0000000FU}, /* RGIDR_MODID[110]:ARSP35*/ + [105] = {0xFCB6203CU, 0x0000000FU}, /* RGIDR_MODID[111]:ARSP36*/ + [106] = {0xFCB62040U, 0x0000000FU}, /* RGIDR_MODID[112]:ARSP37*/ + [107] = {0xFCB62044U, 0x00000000U}, /* RGIDR_MODID[113]:ARSP38*/ + [108] = {0xFCB62048U, 0x0000000EU}, /* RGIDR_MODID[114]:MSI0*/ + [109] = {0xFCB6204CU, 0x0000000EU}, /* RGIDR_MODID[115]:MSI1*/ + [110] = {0xFCB62050U, 0x0000000EU}, /* RGIDR_MODID[116]:MSI2*/ + [111] = {0xFCB62054U, 0x0000000EU}, /* RGIDR_MODID[117]:MSI3*/ + [112] = {0xFCB62058U, 0x0000000EU}, /* RGIDR_MODID[118]:MSI4*/ + [113] = {0xFCB6205CU, 0x0000000EU}, /* RGIDR_MODID[119]:MSI5*/ + [114] = {0xFCB92000U, 0x0000000FU}, /* RGIDR_MODID[120]:ARSP40*/ + /* After setting */ /* RGIDR_MODID[121]:ARSP41*/ + /* After setting */ /* RGIDR_MODID[122]:ARSP42*/ + [115] = {0xFCB9200CU, 0x0000000FU}, /* RGIDR_MODID[123]:ARSP43*/ + [116] = {0xFCB92010U, 0x0000000FU}, /* RGIDR_MODID[124]:ARSP44*/ + [117] = {0xFCB92014U, 0x0000000FU}, /* RGIDR_MODID[125]:ARSP45*/ + [118] = {0xFCB92018U, 0x0000000FU}, /* RGIDR_MODID[126]:ARSP46*/ + [119] = {0xFCB9201CU, 0x0000000FU}, /* RGIDR_MODID[127]:ARSP47*/ + [120] = {0xFCB92020U, 0x00000000U}, /* RGIDR_MODID[128]:ARSP48*/ + [121] = {0xFCB92024U, 0x0000004FU}, /* RGIDR_MODID[129]:DMAHSCIF0*/ + [122] = {0xFCB92028U, 0x0000004FU}, /* RGIDR_MODID[130]:DMAHSCIF1*/ + [123] = {0xFCB9202CU, 0x0000004FU}, /* RGIDR_MODID[131]:DMAHSCIF2*/ + [124] = {0xFCB92030U, 0x0000004FU}, /* RGIDR_MODID[132]:DMAHSCIF3*/ + [125] = {0xFCB92034U, 0x0000004FU}, /* RGIDR_MODID[133]:DMASCIF0*/ + [126] = {0xFCB92038U, 0x0000004FU}, /* RGIDR_MODID[134]:DMASCIF1*/ + [127] = {0xFCB9203CU, 0x0000004FU}, /* RGIDR_MODID[135]:DMASCIF3*/ + [128] = {0xFCB92040U, 0x0000004FU}, /* RGIDR_MODID[136]:DMASCIF4*/ + [129] = {0xFCB92044U, 0x0000000FU}, /* RGIDR_MODID[137]:ECMSP4*/ + [130] = {0xFCB92048U, 0x0000004FU}, /* RGIDR_MODID[138]:HSCIF0*/ + [131] = {0xFCB9204CU, 0x0000004FU}, /* RGIDR_MODID[139]:HSCIF1*/ + [132] = {0xFCB92050U, 0x0000004FU}, /* RGIDR_MODID[140]:HSCIF2*/ + [133] = {0xFCB92054U, 0x0000004FU}, /* RGIDR_MODID[141]:HSCIF3*/ + [134] = {0xFCB92058U, 0x0000004FU}, /* RGIDR_MODID[142]:SCIF0*/ + [135] = {0xFCB9205CU, 0x0000004FU}, /* RGIDR_MODID[143]:SCIF1*/ + [136] = {0xFCB92060U, 0x0000004FU}, /* RGIDR_MODID[144]:SCIF3*/ + [137] = {0xFCB92064U, 0x0000004FU}, /* RGIDR_MODID[145]:SCIF4*/ + [138] = {0xFCB92068U, 0x0000006EU}, /* RGIDR_MODID[146]:TMU1*/ + [139] = {0xFCB9206CU, 0x0000006EU}, /* RGIDR_MODID[147]:TMU2*/ + [140] = {0xFCB92070U, 0x0000006EU}, /* RGIDR_MODID[148]:TMU3*/ + [141] = {0xFCB92074U, 0x0000006EU}, /* RGIDR_MODID[149]:TMU4*/ + [142] = {0xFCB92078U, 0x0000004AU}, /* RGIDR_MODID[150]:CANFD*/ + [143] = {0xFCB9207CU, 0x0000004AU}, /* RGIDR_MODID[151]:DMACANFD*/ + [144] = {0xFCB92080U, 0x00000002U}, /* RGIDR_MODID[152]:DMATPU0*/ + [145] = {0xFCB92084U, 0x00000002U}, /* RGIDR_MODID[153]:PWM0*/ + [146] = {0xFCB92088U, 0x00000002U}, /* RGIDR_MODID[154]:PWM1*/ + [147] = {0xFCB9208CU, 0x00000002U}, /* RGIDR_MODID[155]:PWM2*/ + [148] = {0xFCB92090U, 0x00000002U}, /* RGIDR_MODID[156]:PWM3*/ + [149] = {0xFCB92094U, 0x00000002U}, /* RGIDR_MODID[157]:PWM4*/ + [150] = {0xFCB92098U, 0x00000002U}, /* RGIDR_MODID[158]:PWM5*/ + [151] = {0xFCB9209CU, 0x00000002U}, /* RGIDR_MODID[159]:PWM6*/ + [152] = {0xFCB920A0U, 0x00000002U}, /* RGIDR_MODID[160]:PWM7*/ + [153] = {0xFCB920A4U, 0x00000002U}, /* RGIDR_MODID[161]:PWM8*/ + [154] = {0xFCB920A8U, 0x00000002U}, /* RGIDR_MODID[162]:PWM9*/ + [155] = {0xFCB920ACU, 0x00000002U}, /* RGIDR_MODID[163]:TPU0*/ + [156] = {0xFC672000U, 0x0000002FU}, /* RGIDR_MODID[164]:ARVC10*/ + /* After setting */ /* RGIDR_MODID[165]:ARVC11*/ + /* After setting */ /* RGIDR_MODID[166]:ARVC12*/ + [157] = {0xFC67200CU, 0x0000002FU}, /* RGIDR_MODID[167]:ARVC13*/ + [158] = {0xFC672010U, 0x0000002FU}, /* RGIDR_MODID[168]:ARVC14*/ + [159] = {0xFC672014U, 0x0000002FU}, /* RGIDR_MODID[169]:ARVC15*/ + [160] = {0xFC672018U, 0x0000002FU}, /* RGIDR_MODID[170]:ARVC16*/ + [161] = {0xFC67201CU, 0x0000002FU}, /* RGIDR_MODID[171]:ARVC17*/ + [162] = {0xFC672020U, 0x00000000U}, /* RGIDR_MODID[172]:ARVC18*/ + [163] = {0xFC672024U, 0x0000000FU}, /* RGIDR_MODID[173]:ECMVC1*/ + [164] = {0xFC672028U, 0x00000028U}, /* RGIDR_MODID[174]:FCPCS*/ + [165] = {0xFC67202CU, 0x00000028U}, /* RGIDR_MODID[175]:VCP4LC*/ + [166] = {0xFC672030U, 0x00000028U}, /* RGIDR_MODID[176]:VCP4LV*/ + [167] = {0xFEBD2000U, 0x0000000FU}, /* RGIDR_MODID[177]:ARVI40*/ + /* After setting */ /* RGIDR_MODID[178]:ARVI41*/ + /* After setting */ /* RGIDR_MODID[179]:ARVI42*/ + [168] = {0xFEBD200CU, 0x0000000FU}, /* RGIDR_MODID[180]:ARVI43*/ + [169] = {0xFEBD2010U, 0x0000000FU}, /* RGIDR_MODID[181]:ARVI44*/ + [170] = {0xFEBD2014U, 0x0000000FU}, /* RGIDR_MODID[182]:ARVI45*/ + [171] = {0xFEBD2018U, 0x0000000FU}, /* RGIDR_MODID[183]:ARVI46*/ + [172] = {0xFEBD201CU, 0x0000000FU}, /* RGIDR_MODID[184]:ARVI47*/ + [173] = {0xFEBD2020U, 0x00000000U}, /* RGIDR_MODID[185]:ARVI48*/ + [174] = {0xFEBD2024U, 0x0000000FU}, /* RGIDR_MODID[186]:DIS0*/ + [175] = {0xFEBD202CU, 0x0000000FU}, /* RGIDR_MODID[187]:DSC*/ + [176] = {0xFEBD2030U, 0x0000000FU}, /* RGIDR_MODID[188]:ECMVIO2*/ + [177] = {0xFEBD2034U, 0x0000000FU}, /* RGIDR_MODID[189]:FCPVD0*/ + [178] = {0xFEBD2038U, 0x0000000FU}, /* RGIDR_MODID[190]:FCPVD1*/ + [179] = {0xFEBD203CU, 0x0000004EU}, /* RGIDR_MODID[191]:VSPD0*/ + [180] = {0xFEBD2040U, 0x0000004EU}, /* RGIDR_MODID[192]:VSPD1*/ + [181] = {0xFCF82000U, 0x0000000AU}, /* RGIDR_MODID[193]:CKMHSC*/ + [182] = {0xFCF82004U, 0x0000000CU}, /* RGIDR_MODID[194]:AXIPCI001*/ + [183] = {0xFCF82008U, 0x0000000CU}, /* RGIDR_MODID[195]:AXIPCI002*/ + [184] = {0xFCF8200CU, 0x0000000CU}, /* RGIDR_MODID[196]:AXIPCI003*/ + [185] = {0xFCF82014U, 0x0000000CU}, /* RGIDR_MODID[197]:AXIPCI005*/ + [186] = {0xFCF82018U, 0x0000000CU}, /* RGIDR_MODID[198]:AXIPCI006*/ + [187] = {0xFCF8201CU, 0x0000000CU}, /* RGIDR_MODID[199]:AXIPCI007*/ + [188] = {0xFCF82020U, 0x0000000CU}, /* RGIDR_MODID[200]:AXIPCI008*/ + [189] = {0xFCF82024U, 0x0000000CU}, /* RGIDR_MODID[201]:AXIPCI009*/ + [190] = {0xFCF82028U, 0x0000000CU}, /* RGIDR_MODID[202]:AXIPCI010*/ + [191] = {0xFCF8202CU, 0x0000000CU}, /* RGIDR_MODID[203]:AXIPCI011*/ + [192] = {0xFCF82030U, 0x0000000CU}, /* RGIDR_MODID[204]:AXIPCI012*/ + [193] = {0xFCF82034U, 0x0000000CU}, /* RGIDR_MODID[205]:AXIPCI013*/ + [194] = {0xFCF82038U, 0x0000000CU}, /* RGIDR_MODID[206]:AXIPCI014*/ + [195] = {0xFCF8203CU, 0x0000000CU}, /* RGIDR_MODID[207]:AXIPCI015*/ + [196] = {0xFCF82040U, 0x0000000CU}, /* RGIDR_MODID[208]:AXIPCI100*/ + [197] = {0xFCF82044U, 0x0000000CU}, /* RGIDR_MODID[209]:AXIPCI101*/ + [198] = {0xFCF82048U, 0x0000000CU}, /* RGIDR_MODID[210]:AXIPCI102*/ + [199] = {0xFCF8204CU, 0x0000000CU}, /* RGIDR_MODID[211]:AXIPCI103*/ + [200] = {0xFCF82050U, 0x0000000CU}, /* RGIDR_MODID[212]:AXIPCI104*/ + [201] = {0xFCF82054U, 0x0000000CU}, /* RGIDR_MODID[213]:AXIPCI105*/ + [202] = {0xFCF82058U, 0x0000000CU}, /* RGIDR_MODID[214]:AXIPCI106*/ + [203] = {0xFCF8205CU, 0x0000000CU}, /* RGIDR_MODID[215]:AXIPCI107*/ + [204] = {0xFCF82060U, 0x0000000CU}, /* RGIDR_MODID[216]:AXIPCI108*/ + [205] = {0xFCF82064U, 0x0000000CU}, /* RGIDR_MODID[217]:AXIPCI109*/ + [206] = {0xFCF82068U, 0x0000000CU}, /* RGIDR_MODID[218]:AXIPCI110*/ + [207] = {0xFCF8206CU, 0x0000000CU}, /* RGIDR_MODID[219]:AXIPCI111*/ + [208] = {0xFCF82070U, 0x0000000CU}, /* RGIDR_MODID[220]:AXIPCI112*/ + [209] = {0xFCF82074U, 0x0000000CU}, /* RGIDR_MODID[221]:AXIPCI113*/ + [210] = {0xFCF82078U, 0x0000000CU}, /* RGIDR_MODID[222]:AXIPCI114*/ + [211] = {0xFCF8207CU, 0x0000000CU}, /* RGIDR_MODID[223]:AXIPCI115*/ + [212] = {0xFCF82084U, 0x0000000EU}, /* RGIDR_MODID[224]:GPTP*/ + [213] = {0xFCF82088U, 0x0000004EU}, /* RGIDR_MODID[225]:IPMMUHC00*/ + [214] = {0xFCF820F0U, 0x0000000EU}, /* RGIDR_MODID[226]:TSN0*/ + [215] = {0xFCF820F4U, 0x0000000CU}, /* RGIDR_MODID[227]:AXIPCI000*/ + [216] = {0xFCF820F8U, 0x0000000CU}, /* RGIDR_MODID[228]:AXIPCI004*/ + [217] = {0xFCF820FCU, 0x0000004EU}, /* RGIDR_MODID[229]:IPMMUHC01*/ + [218] = {0xFCF82100U, 0x0000004EU}, /* RGIDR_MODID[230]:AVB0*/ + [219] = {0xFCF82104U, 0x0000004EU}, /* RGIDR_MODID[231]:AVB1*/ + [220] = {0xFCF82108U, 0x0000004EU}, /* RGIDR_MODID[232]:AVB2*/ + [221] = {0xFCF8210CU, 0x0000004EU}, /* RGIDR_MODID[233]:IPMMUHC10*/ + [222] = {0xFCF82110U, 0x0000004EU}, /* RGIDR_MODID[234]:IPMMUHC11*/ + [223] = {0xFCF82114U, 0x0000004EU}, /* RGIDR_MODID[235]:IPMMUHC12*/ + [224] = {0xFCF82118U, 0x0000004EU}, /* RGIDR_MODID[236]:IPMMUHC13*/ + [225] = {0xFCF8211CU, 0x0000000CU}, /* RGIDR_MODID[237]:PPHY0*/ + [226] = {0xFCF82120U, 0x0000000CU}, /* RGIDR_MODID[238]:PPHY1*/ + [227] = {0xFCF82124U, 0x0000004EU}, /* RGIDR_MODID[239]:IPMMUHC14*/ + [228] = {0xFCF82128U, 0x0000004EU}, /* RGIDR_MODID[240]:IPMMUHC15*/ + [229] = {0xFCF8212CU, 0x0000000EU}, /* RGIDR_MODID[241]:FBAHSC*/ + [230] = {0xFCF82130U, 0x0000004EU}, /* RGIDR_MODID[242]:IPMMUHC02*/ + [231] = {0xFCF82138U, 0x0000000FU}, /* RGIDR_MODID[243]:ECMHSC*/ + [232] = {0xFCF8213CU, 0x0000000FU}, /* RGIDR_MODID[244]:ARHC0*/ + /* After setting */ /* RGIDR_MODID[245]:ARHC1*/ + /* After setting */ /* RGIDR_MODID[246]:ARHC2*/ + [233] = {0xFCF82148U, 0x0000000FU}, /* RGIDR_MODID[247]:ARHC3*/ + [234] = {0xFCF8214CU, 0x0000000FU}, /* RGIDR_MODID[248]:ARHC4*/ + [235] = {0xFCF82150U, 0x0000000FU}, /* RGIDR_MODID[249]:ARHC5*/ + [236] = {0xFCF82154U, 0x0000000FU}, /* RGIDR_MODID[250]:ARHC6*/ + [237] = {0xFCF82158U, 0x0000000FU}, /* RGIDR_MODID[251]:ARHC7*/ + [238] = {0xFCF8215CU, 0x00000000U}, /* RGIDR_MODID[252]:ARHC8*/ + [239] = {0xFCF82160U, 0x0000004EU}, /* RGIDR_MODID[253]:IPMMUHC03*/ + [240] = {0xFCF82164U, 0x0000004EU}, /* RGIDR_MODID[254]:IPMMUHC04*/ + [241] = {0xFCF82168U, 0x0000004EU}, /* RGIDR_MODID[255]:IPMMUHC05*/ + [242] = {0xFCF8216CU, 0x0000004EU}, /* RGIDR_MODID[256]:IPMMUHC06*/ + [243] = {0xFCF82170U, 0x0000004EU}, /* RGIDR_MODID[257]:IPMMUHC07*/ + [244] = {0xFCF82174U, 0x0000004EU}, /* RGIDR_MODID[258]:IPMMUHC08*/ + [245] = {0xFCF82178U, 0x0000004EU}, /* RGIDR_MODID[259]:IPMMUHC09*/ + [246] = {0xFC882000U, 0x0000000FU}, /* RGIDR_MODID[260]:ARIMP00*/ + /* After setting */ /* RGIDR_MODID[261]:ARIMP01*/ + /* After setting */ /* RGIDR_MODID[262]:ARIMP02*/ + [247] = {0xFC88200CU, 0x0000000FU}, /* RGIDR_MODID[263]:ARIMP03*/ + [248] = {0xFC882010U, 0x0000000FU}, /* RGIDR_MODID[264]:ARIMP04*/ + [249] = {0xFC882014U, 0x0000004EU}, /* RGIDR_MODID[265]:AXIFBABUSIR0*/ + [250] = {0xFC882018U, 0x0000004EU}, /* RGIDR_MODID[266]:AXIFBABUSIR1*/ + [251] = {0xFC88201CU, 0x0000004EU}, /* RGIDR_MODID[267]:AXIFBABUSIR2*/ + [252] = {0xFC882020U, 0x0000004EU}, /* RGIDR_MODID[268]:AXIFBABUSIR3*/ + [253] = {0xFC882024U, 0x0000004EU}, /* RGIDR_MODID[269]:AXIFBABUSIR4*/ + [254] = {0xFC882028U, 0x0000004EU}, /* RGIDR_MODID[270]:AXIIMP0*/ + [255] = {0xFC88202CU, 0x0000004EU}, /* RGIDR_MODID[271]:CKMCNR*/ + [256] = {0xFC882030U, 0x0000004EU}, /* RGIDR_MODID[272]:CKMDSP*/ + [257] = {0xFC882034U, 0x0000000FU}, /* RGIDR_MODID[273]:ARIMP05*/ + [258] = {0xFC882038U, 0x0000000FU}, /* RGIDR_MODID[274]:ARIMP06*/ + [259] = {0xFC88203CU, 0x0000000FU}, /* RGIDR_MODID[275]:ARIMP07*/ + [260] = {0xFC882040U, 0x00000000U}, /* RGIDR_MODID[276]:ARIMP08*/ + [261] = {0xFC882044U, 0x0000004EU}, /* RGIDR_MODID[277]:CKMIR*/ + [262] = {0xFC882048U, 0x0000000FU}, /* RGIDR_MODID[278]:ECMIR*/ + [263] = {0xFC88204CU, 0x0000000FU}, /* RGIDR_MODID[279]:DSPPS*/ + [264] = {0xFC882050U, 0x0000004EU}, /* RGIDR_MODID[280]:IPMMUIR1*/ + [265] = {0xFC882054U, 0x0000004EU}, /* RGIDR_MODID[281]:IPMMUIR0*/ + [266] = {0xFC882058U, 0x0000004EU}, /* RGIDR_MODID[282]:IPMMUIR10*/ + [267] = {0xFC88205CU, 0x0000004EU}, /* RGIDR_MODID[283]:IPMMUIR11*/ + [268] = {0xFC882060U, 0x0000004EU}, /* RGIDR_MODID[284]:IPMMUIR12*/ + [269] = {0xFC882064U, 0x0000004EU}, /* RGIDR_MODID[285]:IPMMUIR13*/ + [270] = {0xFC882068U, 0x0000004EU}, /* RGIDR_MODID[286]:IPMMUIR14*/ + [271] = {0xFC88206CU, 0x0000004EU}, /* RGIDR_MODID[287]:IPMMUIR15*/ + [272] = {0xFC882070U, 0x0000004EU}, /* RGIDR_MODID[288]:IPMMUIR2*/ + [273] = {0xFC882074U, 0x0000004EU}, /* RGIDR_MODID[289]:IPMMUIR3*/ + [274] = {0xFC882078U, 0x0000004EU}, /* RGIDR_MODID[290]:IPMMUIR4*/ + [275] = {0xFC88207CU, 0x0000004EU}, /* RGIDR_MODID[291]:IPMMUIR5*/ + [276] = {0xFC882080U, 0x0000004EU}, /* RGIDR_MODID[292]:IPMMUIR6*/ + [277] = {0xFC882084U, 0x0000004EU}, /* RGIDR_MODID[293]:IPMMUIR7*/ + [278] = {0xFC882088U, 0x0000004EU}, /* RGIDR_MODID[294]:IPMMUIR8*/ + [279] = {0xFC88208CU, 0x0000004EU}, /* RGIDR_MODID[295]:IPMMUIR9*/ + [280] = {0xFC012000U, 0x0000000FU}, /* RGIDR_MODID[296]:ARPV0*/ + /* After setting */ /* RGIDR_MODID[297]:ARPV1*/ + [281] = {0xFC012008U, 0x0000002CU}, /* RGIDR_MODID[298]:AXIRGXS*/ + /* After setting */ /* RGIDR_MODID[299]:ARPV2*/ + [282] = {0xFC012010U, 0x0000000FU}, /* RGIDR_MODID[300]:ARPV3*/ + [283] = {0xFC012014U, 0x0000000FU}, /* RGIDR_MODID[301]:ARPV4*/ + [284] = {0xFC012018U, 0x0000000FU}, /* RGIDR_MODID[302]:ARPV5*/ + [285] = {0xFC01201CU, 0x0000000FU}, /* RGIDR_MODID[303]:ARPV6*/ + [286] = {0xFC012020U, 0x0000000FU}, /* RGIDR_MODID[304]:ARPV7*/ + [287] = {0xFC012024U, 0x00000000U}, /* RGIDR_MODID[305]:ARPV8*/ + [288] = {0xFC012028U, 0x0000000AU}, /* RGIDR_MODID[306]:CKM3DG*/ + [289] = {0xFC01202CU, 0x0000000FU}, /* RGIDR_MODID[307]:ECM3DG*/ + [290] = {0xFC012030U, 0x0000000EU}, /* RGIDR_MODID[308]:FBAPVC*/ + [291] = {0xFC012034U, 0x0000000EU}, /* RGIDR_MODID[309]:FBAPVD0*/ + [292] = {0xFC012038U, 0x0000000EU}, /* RGIDR_MODID[310]:FBAPVD1*/ + [293] = {0xFC01203CU, 0x0000000EU}, /* RGIDR_MODID[311]:FBAPVD2*/ + [294] = {0xFC012040U, 0x0000000EU}, /* RGIDR_MODID[312]:FBAPVE*/ + [295] = {0xFC012044U, 0x0000004EU}, /* RGIDR_MODID[313]:IPMMUPV000*/ + [296] = {0xFC012048U, 0x0000004EU}, /* RGIDR_MODID[314]:IPMMUPV001*/ + [297] = {0xFC01204CU, 0x0000004EU}, /* RGIDR_MODID[315]:IPMMUPV010*/ + [298] = {0xFC012050U, 0x0000004EU}, /* RGIDR_MODID[316]:IPMMUPV011*/ + [299] = {0xFC012054U, 0x0000004EU}, /* RGIDR_MODID[317]:IPMMUPV012*/ + [300] = {0xFC012058U, 0x0000004EU}, /* RGIDR_MODID[318]:IPMMUPV013*/ + [301] = {0xFC01205CU, 0x0000004EU}, /* RGIDR_MODID[319]:IPMMUPV014*/ + [302] = {0xFC012060U, 0x0000004EU}, /* RGIDR_MODID[320]:IPMMUPV015*/ + [303] = {0xFC012064U, 0x0000004EU}, /* RGIDR_MODID[321]:IPMMUPV002*/ + [304] = {0xFC012068U, 0x0000004EU}, /* RGIDR_MODID[322]:IPMMUPV003*/ + [305] = {0xFC01206CU, 0x0000004EU}, /* RGIDR_MODID[323]:IPMMUPV004*/ + [306] = {0xFC012070U, 0x0000004EU}, /* RGIDR_MODID[324]:IPMMUPV005*/ + [307] = {0xFC012074U, 0x0000004EU}, /* RGIDR_MODID[325]:IPMMUPV006*/ + [308] = {0xFC012078U, 0x0000004EU}, /* RGIDR_MODID[326]:IPMMUPV007*/ + [309] = {0xFC01207CU, 0x0000004EU}, /* RGIDR_MODID[327]:IPMMUPV008*/ + [310] = {0xFC012080U, 0x0000004EU}, /* RGIDR_MODID[328]:IPMMUPV009*/ + [311] = {0xFDC22000U, 0x0000000FU}, /* RGIDR_MODID[329]:ARRC0*/ + /* After setting */ /* RGIDR_MODID[330]:ARRC1*/ + /* After setting */ /* RGIDR_MODID[331]:ARRC2*/ + [312] = {0xFDC2200CU, 0x0000000FU}, /* RGIDR_MODID[332]:ARRC3*/ + [313] = {0xFDC22010U, 0x0000000FU}, /* RGIDR_MODID[333]:ARRC4*/ + [314] = {0xFDC22014U, 0x0000000FU}, /* RGIDR_MODID[334]:ARRC5*/ + [315] = {0xFDC22018U, 0x0000000FU}, /* RGIDR_MODID[335]:ARRC6*/ + [316] = {0xFDC2201CU, 0x0000000FU}, /* RGIDR_MODID[336]:ARRC7*/ + [317] = {0xFDC22020U, 0x00000000U}, /* RGIDR_MODID[337]:ARRC8*/ + [318] = {0xFDC22024U, 0x00000009U}, /* RGIDR_MODID[338]:CR0*/ + [319] = {0xFDC22028U, 0x0000004FU}, /* RGIDR_MODID[339]:ICUMX*/ + [320] = {0xFDC2202CU, 0x0000000FU}, /* RGIDR_MODID[340]:ECMRC*/ + [321] = {0xFD432000U, 0x0000004EU}, /* RGIDR_MODID[341]:DMAWCRC0*/ + [322] = {0xFD432004U, 0x0000004EU}, /* RGIDR_MODID[342]:DMAWCRC1*/ + [323] = {0xFD432008U, 0x0000004EU}, /* RGIDR_MODID[343]:DMAWCRC2*/ + [324] = {0xFD43200CU, 0x0000004EU}, /* RGIDR_MODID[344]:DMAWCRC3*/ + [325] = {0xFD442000U, 0x0000000FU}, /* RGIDR_MODID[345]:ARMREG00*/ + [326] = {0xFD442004U, 0x0000000DU}, /* RGIDR_MODID[346]:ARMREG01*/ + [327] = {0xFD442008U, 0x00000000U}, /* RGIDR_MODID[347]:ARMREG10*/ + [328] = {0xFD44200CU, 0x00000000U}, /* RGIDR_MODID[348]:ARMREG11*/ + [329] = {0xFD442010U, 0x0000000BU}, /* RGIDR_MODID[349]:ARMREG12*/ + [330] = {0xFD442014U, 0x0000000FU}, /* RGIDR_MODID[350]:ARMREG13*/ + [331] = {0xFD442018U, 0x0000000BU}, /* RGIDR_MODID[351]:ARMREG14*/ + [332] = {0xFD44201CU, 0x00000002U}, /* RGIDR_MODID[352]:AXICR52SS0*/ + [333] = {0xFD442020U, 0x0000000EU}, /* RGIDR_MODID[353]:AXICSD0*/ + [334] = {0xFD442024U, 0x0000000EU}, /* RGIDR_MODID[354]:AXIINTAP0*/ + [335] = {0xFD442028U, 0x00000000U}, /* RGIDR_MODID[355]:AXIINTAP1*/ + [336] = {0xFD44202CU, 0x00000009U}, /* RGIDR_MODID[356]:AXISECROM*/ + [337] = {0xFD442030U, 0x0000000FU}, /* RGIDR_MODID[357]:AXISYSRAM0*/ + [338] = {0xFD442034U, 0x0000004FU}, /* RGIDR_MODID[358]:AXISYSRAM1*/ + [339] = {0xFD442038U, 0x00000000U}, /* RGIDR_MODID[359]:ARGREG15*/ + [340] = {0xFD44203CU, 0x00000000U}, /* RGIDR_MODID[360]:ARMREG2*/ + [341] = {0xFD442040U, 0x00000000U}, /* RGIDR_MODID[361]:ARMREG3*/ + [342] = {0xFD442044U, 0x00000000U}, /* RGIDR_MODID[362]:ARMREG4*/ + [343] = {0xFD442048U, 0x0000000FU}, /* RGIDR_MODID[363]:ARMREG5*/ + [344] = {0xFD44204CU, 0x0000000FU}, /* RGIDR_MODID[364]:ARMREG6*/ + [345] = {0xFD442050U, 0x00000000U}, /* RGIDR_MODID[365]:ARMREG7*/ + [346] = {0xFD442054U, 0x0000000DU}, /* RGIDR_MODID[366]:ARMREG8*/ + [347] = {0xFD442058U, 0x0000000DU}, /* RGIDR_MODID[367]:ARMREG9*/ + [348] = {0xFD44205CU, 0x0000000FU}, /* RGIDR_MODID[368]:ARRD0*/ + /* After setting */ /* RGIDR_MODID[369]:ARRD1*/ + /* After setting */ /* RGIDR_MODID[370]:ARRD2*/ + [349] = {0xFD442068U, 0x0000000FU}, /* RGIDR_MODID[371]:ARRD3*/ + [350] = {0xFD44206CU, 0x0000000FU}, /* RGIDR_MODID[372]:ARRD4*/ + [351] = {0xFD442070U, 0x0000000FU}, /* RGIDR_MODID[373]:ARRD5*/ + [352] = {0xFD442074U, 0x0000000FU}, /* RGIDR_MODID[374]:ARRD6*/ + [353] = {0xFD442078U, 0x0000000FU}, /* RGIDR_MODID[375]:ARRD7*/ + [354] = {0xFD44207CU, 0x00000000U}, /* RGIDR_MODID[376]:ARRD8*/ + [355] = {0xFD442080U, 0x0000000FU}, /* RGIDR_MODID[377]:ARRT0*/ + /* After setting */ /* RGIDR_MODID[378]:ARRT1*/ + /* After setting */ /* RGIDR_MODID[379]:ARRT2*/ + [356] = {0xFD44208CU, 0x0000000FU}, /* RGIDR_MODID[380]:ARRT3*/ + [357] = {0xFD442090U, 0x0000000FU}, /* RGIDR_MODID[381]:ARRT4*/ + [358] = {0xFD442094U, 0x0000000FU}, /* RGIDR_MODID[382]:ARRT5*/ + [359] = {0xFD442098U, 0x0000000FU}, /* RGIDR_MODID[383]:ARRT6*/ + [360] = {0xFD44209CU, 0x0000000FU}, /* RGIDR_MODID[384]:ARRT7*/ + [361] = {0xFD4420A0U, 0x00000000U}, /* RGIDR_MODID[385]:ARRT8*/ + [362] = {0xFD4420A4U, 0x0000000AU}, /* RGIDR_MODID[386]:CKMRT*/ + [363] = {0xFD4420A8U, 0x0000004EU}, /* RGIDR_MODID[387]:CRC0*/ + [364] = {0xFD4420ACU, 0x0000004EU}, /* RGIDR_MODID[388]:CRC1*/ + [365] = {0xFD4420B0U, 0x0000004EU}, /* RGIDR_MODID[389]:CRC2*/ + [366] = {0xFD4420B4U, 0x0000004EU}, /* RGIDR_MODID[390]:CRC3*/ + [367] = {0xFD4420B8U, 0x0000000EU}, /* RGIDR_MODID[391]:CSD*/ + [368] = {0xFD4420BCU, 0x0000000FU}, /* RGIDR_MODID[392]:ECM*/ + [369] = {0xFD4420C0U, 0x0000000FU}, /* RGIDR_MODID[393]:ECMRT*/ + [370] = {0xFD4420C4U, 0x0000000EU}, /* RGIDR_MODID[394]:FBACR52*/ + [371] = {0xFD4420C8U, 0x0000000EU}, /* RGIDR_MODID[395]:FBART*/ + [372] = {0xFD4420CCU, 0x0000000EU}, /* RGIDR_MODID[396]:INTTP*/ + [373] = {0xFD4420D0U, 0x0000004EU}, /* RGIDR_MODID[397]:IPMMURT000*/ + [374] = {0xFD4420D4U, 0x0000004EU}, /* RGIDR_MODID[398]:IPMMURT100*/ + [375] = {0xFD4420D8U, 0x0000004EU}, /* RGIDR_MODID[399]:KCRC4*/ + [376] = {0xFD4420DCU, 0x0000004EU}, /* RGIDR_MODID[400]:KCRC5*/ + [377] = {0xFD4420E0U, 0x0000004EU}, /* RGIDR_MODID[401]:KCRC6*/ + [378] = {0xFD4420E4U, 0x0000004EU}, /* RGIDR_MODID[402]:KCRC7*/ + [379] = {0xFD4420E8U, 0x0000004FU}, /* RGIDR_MODID[403]:MFI00*/ + [380] = {0xFD4420ECU, 0x0000004EU}, /* RGIDR_MODID[404]:MFI01*/ + [381] = {0xFD4420F0U, 0x0000004EU}, /* RGIDR_MODID[405]:MFI10*/ + [382] = {0xFD4420F4U, 0x0000004EU}, /* RGIDR_MODID[406]:MFI02*/ + [383] = {0xFD4420F8U, 0x0000004EU}, /* RGIDR_MODID[407]:MFI03*/ + [384] = {0xFD4420FCU, 0x0000004EU}, /* RGIDR_MODID[408]:MFI04*/ + [385] = {0xFD442100U, 0x00000000U}, /* RGIDR_MODID[409]:MFI05*/ + [386] = {0xFD442104U, 0x00000000U}, /* RGIDR_MODID[410]:MFI06*/ + [387] = {0xFD442108U, 0x00000000U}, /* RGIDR_MODID[411]:MFI07*/ + [388] = {0xFD44210CU, 0x00000000U}, /* RGIDR_MODID[412]:MFI08*/ + [389] = {0xFD442110U, 0x0000004EU}, /* RGIDR_MODID[413]:MFI09*/ + [390] = {0xFD442114U, 0x0000004FU}, /* RGIDR_MODID[414]:MFI15*/ + [391] = {0xFD442118U, 0x0000000AU}, /* RGIDR_MODID[415]:CKMCR52*/ + [392] = {0xFD44211CU, 0x0000004BU}, /* RGIDR_MODID[416]:RTDM0P*/ + [393] = {0xFD442120U, 0x0000000FU}, /* RGIDR_MODID[417]:ECMRD*/ + [394] = {0xFD442124U, 0x0000004BU}, /* RGIDR_MODID[418]:RTDM1P*/ + [395] = {0xFD44212CU, 0x0000004BU}, /* RGIDR_MODID[419]:RTDM2P*/ + [396] = {0xFD442130U, 0x0000000BU}, /* RGIDR_MODID[420]:SYSRAM10*/ + [397] = {0xFD442134U, 0x0000004BU}, /* RGIDR_MODID[421]:RTDM3P*/ + [398] = {0xFD442138U, 0x00000003U}, /* RGIDR_MODID[422]:SYSRAM00*/ + [399] = {0xFD44213CU, 0x0000004EU}, /* RGIDR_MODID[423]:TSIPL0*/ + [400] = {0xFD442140U, 0x0000004EU}, /* RGIDR_MODID[424]:TSIPL1*/ + [401] = {0xFD442144U, 0x0000004EU}, /* RGIDR_MODID[425]:TSIPL2*/ + [402] = {0xFD442148U, 0x0000004EU}, /* RGIDR_MODID[426]:TSIPL3*/ + [403] = {0xFD44214CU, 0x0000004EU}, /* RGIDR_MODID[427]:TSIPL4*/ + [404] = {0xFD442150U, 0x0000004EU}, /* RGIDR_MODID[428]:TSIPL5*/ + [405] = {0xFD442154U, 0x0000004EU}, /* RGIDR_MODID[429]:TSIPL6*/ + [406] = {0xFD442158U, 0x0000004EU}, /* RGIDR_MODID[430]:TSIPL7*/ + [407] = {0xFD44215CU, 0x0000004EU}, /* RGIDR_MODID[431]:WCRC0*/ + [408] = {0xFD442160U, 0x0000004EU}, /* RGIDR_MODID[432]:WCRC1*/ + [409] = {0xFD442164U, 0x0000004EU}, /* RGIDR_MODID[433]:WCRC2*/ + [410] = {0xFD442168U, 0x0000004EU}, /* RGIDR_MODID[434]:WCRC3*/ + [411] = {0xFD442180U, 0x0000004EU}, /* RGIDR_MODID[435]:MFI11*/ + [412] = {0xFD442184U, 0x00000000U}, /* RGIDR_MODID[436]:MFI12*/ + [413] = {0xFD442188U, 0x00000000U}, /* RGIDR_MODID[437]:MFI13*/ + [414] = {0xFD44218CU, 0x00000000U}, /* RGIDR_MODID[438]:MFI14*/ + [415] = {0xFD442190U, 0x0000004EU}, /* RGIDR_MODID[439]:IPMMURT001*/ + [416] = {0xFD442194U, 0x0000004EU}, /* RGIDR_MODID[440]:IPMMURT010*/ + [417] = {0xFD442198U, 0x0000004EU}, /* RGIDR_MODID[441]:IPMMURT011*/ + [418] = {0xFD44219CU, 0x0000004EU}, /* RGIDR_MODID[442]:IPMMURT012*/ + [419] = {0xFD4421A0U, 0x0000004EU}, /* RGIDR_MODID[443]:IPMMURT013*/ + [420] = {0xFD4421A4U, 0x0000004EU}, /* RGIDR_MODID[444]:IPMMURT014*/ + [421] = {0xFD4421A8U, 0x0000004EU}, /* RGIDR_MODID[445]:IPMMURT015*/ + [422] = {0xFD4421ACU, 0x0000004EU}, /* RGIDR_MODID[446]:IPMMURT002*/ + [423] = {0xFD4421B0U, 0x0000004EU}, /* RGIDR_MODID[447]:IPMMURT003*/ + [424] = {0xFD4421B4U, 0x0000004EU}, /* RGIDR_MODID[448]:IPMMURT004*/ + [425] = {0xFD4421B8U, 0x0000004EU}, /* RGIDR_MODID[449]:IPMMURT005*/ + [426] = {0xFD4421BCU, 0x0000004EU}, /* RGIDR_MODID[450]:IPMMURT006*/ + [427] = {0xFD4421C0U, 0x0000004EU}, /* RGIDR_MODID[451]:IPMMURT007*/ + [428] = {0xFD4421C4U, 0x0000004EU}, /* RGIDR_MODID[452]:IPMMURT008*/ + [429] = {0xFD4421C8U, 0x0000004EU}, /* RGIDR_MODID[453]:IPMMURT009*/ + [430] = {0xFD4421CCU, 0x0000004EU}, /* RGIDR_MODID[454]:IPKMURT101*/ + [431] = {0xFD4421D0U, 0x0000004EU}, /* RGIDR_MODID[455]:IPMMURT110*/ + [432] = {0xFD4421D4U, 0x0000004EU}, /* RGIDR_MODID[456]:IPMMURT111*/ + [433] = {0xFD4421D8U, 0x0000004EU}, /* RGIDR_MODID[457]:IPMMURT112*/ + [434] = {0xFD4421DCU, 0x0000004EU}, /* RGIDR_MODID[458]:IPMMURT113*/ + [435] = {0xFD4421E0U, 0x0000004EU}, /* RGIDR_MODID[459]:IPMMURT114*/ + [436] = {0xFD4421E4U, 0x0000004EU}, /* RGIDR_MODID[460]:IPMMURT115*/ + [437] = {0xFD4421E8U, 0x0000004EU}, /* RGIDR_MODID[461]:IPMMURT102*/ + [438] = {0xFD4421ECU, 0x0000004EU}, /* RGIDR_MODID[462]:IPMMURT103*/ + [439] = {0xFD4421F0U, 0x0000004EU}, /* RGIDR_MODID[463]:IPMMURT104*/ + [440] = {0xFD4421F4U, 0x0000004EU}, /* RGIDR_MODID[464]:IPMMURT105*/ + [441] = {0xFD4421F8U, 0x0000004EU}, /* RGIDR_MODID[465]:IPMMURT106*/ + [442] = {0xFD4421FCU, 0x0000004EU}, /* RGIDR_MODID[466]:IPMMURT107*/ + [443] = {0xFD442200U, 0x0000004BU}, /* RGIDR_MODID[467]:RTDM000*/ + [444] = {0xFD442204U, 0x0000004BU}, /* RGIDR_MODID[468]:RTDM001*/ + [445] = {0xFD442208U, 0x0000004BU}, /* RGIDR_MODID[469]:RTDM010*/ + [446] = {0xFD44220CU, 0x0000004BU}, /* RGIDR_MODID[470]:RTDM011*/ + [447] = {0xFD442210U, 0x0000004BU}, /* RGIDR_MODID[471]:RTDM012*/ + [448] = {0xFD442214U, 0x0000004BU}, /* RGIDR_MODID[472]:RTDM013*/ + [449] = {0xFD442218U, 0x0000004BU}, /* RGIDR_MODID[473]:RTDM014*/ + [450] = {0xFD44221CU, 0x0000004BU}, /* RGIDR_MODID[474]:RTDM015*/ + [451] = {0xFD442220U, 0x0000004BU}, /* RGIDR_MODID[475]:RTDM002*/ + [452] = {0xFD442224U, 0x0000004BU}, /* RGIDR_MODID[476]:RTDM003*/ + [453] = {0xFD442228U, 0x0000004BU}, /* RGIDR_MODID[477]:RTDM004*/ + [454] = {0xFD44222CU, 0x0000004BU}, /* RGIDR_MODID[478]:RTDM005*/ + [455] = {0xFD442230U, 0x0000004BU}, /* RGIDR_MODID[479]:RTDM006*/ + [456] = {0xFD442234U, 0x0000004BU}, /* RGIDR_MODID[480]:RTDM007*/ + [457] = {0xFD442238U, 0x0000004BU}, /* RGIDR_MODID[481]:RTDM008*/ + [458] = {0xFD44223CU, 0x0000004BU}, /* RGIDR_MODID[482]:RTDM009*/ + [459] = {0xFD442240U, 0x0000004BU}, /* RGIDR_MODID[483]:RTDM100*/ + [460] = {0xFD442244U, 0x0000004BU}, /* RGIDR_MODID[484]:RTDM101*/ + [461] = {0xFD442248U, 0x0000004BU}, /* RGIDR_MODID[485]:RTDM110*/ + [462] = {0xFD44224CU, 0x0000004BU}, /* RGIDR_MODID[486]:RTDM111*/ + [463] = {0xFD442250U, 0x0000004BU}, /* RGIDR_MODID[487]:RTDM112*/ + [464] = {0xFD442254U, 0x0000004BU}, /* RGIDR_MODID[488]:RTDM113*/ + [465] = {0xFD442258U, 0x0000004BU}, /* RGIDR_MODID[489]:RTDM114*/ + [466] = {0xFD44225CU, 0x0000004BU}, /* RGIDR_MODID[490]:RTDM115*/ + [467] = {0xFD442260U, 0x0000004BU}, /* RGIDR_MODID[491]:RTDM102*/ + [468] = {0xFD442264U, 0x0000004BU}, /* RGIDR_MODID[492]:RTDM103*/ + [469] = {0xFD442268U, 0x0000004BU}, /* RGIDR_MODID[493]:RTDM104*/ + [470] = {0xFD44226CU, 0x0000004BU}, /* RGIDR_MODID[494]:RTDM105*/ + [471] = {0xFD442270U, 0x0000004BU}, /* RGIDR_MODID[495]:RTDM106*/ + [472] = {0xFD442274U, 0x0000004BU}, /* RGIDR_MODID[496]:RTDM107*/ + [473] = {0xFD442278U, 0x0000004BU}, /* RGIDR_MODID[497]:RTDM108*/ + [474] = {0xFD44227CU, 0x0000004BU}, /* RGIDR_MODID[498]:RTDM109*/ + [475] = {0xFD442280U, 0x0000004BU}, /* RGIDR_MODID[499]:RTDM200*/ + [476] = {0xFD442284U, 0x0000004BU}, /* RGIDR_MODID[500]:RTDM201*/ + [477] = {0xFD442288U, 0x0000004BU}, /* RGIDR_MODID[501]:RTDM210*/ + [478] = {0xFD44228CU, 0x0000004BU}, /* RGIDR_MODID[502]:RTDM211*/ + [479] = {0xFD442290U, 0x0000004BU}, /* RGIDR_MODID[503]:RTDM212*/ + [480] = {0xFD442294U, 0x0000004BU}, /* RGIDR_MODID[504]:RTDM213*/ + [481] = {0xFD442298U, 0x0000004BU}, /* RGIDR_MODID[505]:RTDM214*/ + [482] = {0xFD44229CU, 0x0000004BU}, /* RGIDR_MODID[506]:RTDM215*/ + [483] = {0xFD4422A0U, 0x0000004BU}, /* RGIDR_MODID[507]:RTDM202*/ + [484] = {0xFD4422A4U, 0x0000004BU}, /* RGIDR_MODID[508]:RTDM203*/ + [485] = {0xFD4422A8U, 0x0000004BU}, /* RGIDR_MODID[509]:RTDM204*/ + [486] = {0xFD4422ACU, 0x0000004BU}, /* RGIDR_MODID[510]:RTDM205*/ + [487] = {0xFD4422B0U, 0x0000004BU}, /* RGIDR_MODID[511]:RTDM206*/ + [488] = {0xFD4422B4U, 0x0000004BU}, /* RGIDR_MODID[512]:RTDM207*/ + [489] = {0xFD4422B8U, 0x0000004BU}, /* RGIDR_MODID[513]:RTDM208*/ + [490] = {0xFD4422BCU, 0x0000004BU}, /* RGIDR_MODID[514]:RTDM209*/ + [491] = {0xFD4422C0U, 0x0000004BU}, /* RGIDR_MODID[515]:RTDM300*/ + [492] = {0xFD4422C4U, 0x0000004BU}, /* RGIDR_MODID[516]:RTDM301*/ + [493] = {0xFD4422C8U, 0x0000004BU}, /* RGIDR_MODID[517]:RTDM310*/ + [494] = {0xFD4422CCU, 0x0000004BU}, /* RGIDR_MODID[518]:RTDM311*/ + [495] = {0xFD4422D0U, 0x0000004BU}, /* RGIDR_MODID[519]:RTDM312*/ + [496] = {0xFD4422D4U, 0x0000004BU}, /* RGIDR_MODID[520]:RTDM313*/ + [497] = {0xFD4422D8U, 0x0000004BU}, /* RGIDR_MODID[521]:RTDM314*/ + [498] = {0xFD4422DCU, 0x0000004BU}, /* RGIDR_MODID[522]:RTDM315*/ + [499] = {0xFD4422E0U, 0x0000004BU}, /* RGIDR_MODID[523]:RTDM302*/ + [500] = {0xFD4422E4U, 0x0000004BU}, /* RGIDR_MODID[524]:RTDM303*/ + [501] = {0xFD4422E8U, 0x0000004BU}, /* RGIDR_MODID[525]:RTDM304*/ + [502] = {0xFD4422ECU, 0x0000004BU}, /* RGIDR_MODID[526]:RTDM305*/ + [503] = {0xFD4422F0U, 0x0000004BU}, /* RGIDR_MODID[527]:RTDM306*/ + [504] = {0xFD4422F4U, 0x0000004BU}, /* RGIDR_MODID[528]:RTDM307*/ + [505] = {0xFD4422F8U, 0x0000004BU}, /* RGIDR_MODID[529]:RTDM308*/ + [506] = {0xFD4422FCU, 0x0000004BU}, /* RGIDR_MODID[530]:RTDM309*/ + [507] = {0xFD442300U, 0x0000004EU}, /* RGIDR_MODID[531]:IPMMURT108*/ + [508] = {0xFD442304U, 0x0000004EU}, /* RGIDR_MODID[532]:IPMMURT109*/ + [509] = {0xFD442308U, 0x00000001U}, /* RGIDR_MODID[533]:SYSRAM01*/ + [510] = {0xFD44230CU, 0x0000000BU}, /* RGIDR_MODID[534]:SYSRAM02*/ + [511] = {0xFD442310U, 0x00000001U}, /* RGIDR_MODID[535]:SYSRAM03*/ + [512] = {0xFD442314U, 0x00000001U}, /* RGIDR_MODID[536]:SYSRAM04*/ + [513] = {0xFD442318U, 0x00000001U}, /* RGIDR_MODID[537]:SYSRAM05*/ + [514] = {0xFD44231CU, 0x00000001U}, /* RGIDR_MODID[538]:SYSRAM06*/ + [515] = {0xFD442320U, 0x00000000U}, /* RGIDR_MODID[539]:SYSRAM07*/ + [516] = {0xFD442324U, 0x0000000BU}, /* RGIDR_MODID[540]:SYSRAM11*/ + [517] = {0xFD442328U, 0x0000000BU}, /* RGIDR_MODID[541]:SYSRAM12*/ + [518] = {0xFD44232CU, 0x0000000BU}, /* RGIDR_MODID[542]:SYSRAM13*/ + [519] = {0xFD442330U, 0x0000000BU}, /* RGIDR_MODID[543]:SYSRAM14*/ + [520] = {0xFD442334U, 0x0000000BU}, /* RGIDR_MODID[544]:SYSRAM15*/ + [521] = {0xFD442338U, 0x0000000BU}, /* RGIDR_MODID[545]:SYSRAM16*/ + [522] = {0xFD44233CU, 0x00000000U}, /* RGIDR_MODID[546]:SYSRAM17*/ + [523] = {0xFD442360U, 0x00000002U}, /* RGIDR_MODID[547]:BKBUF*/ + [524] = {0xFD442364U, 0x00000002U}, /* RGIDR_MODID[548]:AXICR52SS1*/ + [525] = {0xFD442368U, 0x00000002U}, /* RGIDR_MODID[549]:AXICR52SS2*/ + [526] = {0xFC862000U, 0x0000000FU}, /* RGIDR_MODID[550]:ARSC0*/ + /* After setting */ /* RGIDR_MODID[551]:ARSC1*/ + /* After setting */ /* RGIDR_MODID[552]:ARSC2*/ + [527] = {0xFC86200CU, 0x0000000FU}, /* RGIDR_MODID[553]:ARSC3*/ + [528] = {0xFC862010U, 0x0000000FU}, /* RGIDR_MODID[554]:ARSC4*/ + [529] = {0xFC862014U, 0x0000000FU}, /* RGIDR_MODID[555]:ARSC5*/ + [530] = {0xFC862018U, 0x0000000FU}, /* RGIDR_MODID[556]:ARSC6*/ + [531] = {0xFC86201CU, 0x0000000FU}, /* RGIDR_MODID[557]:ARSC7*/ + [532] = {0xFC862020U, 0x00000000U}, /* RGIDR_MODID[558]:ARSC8*/ + [533] = {0xFC862024U, 0x0000000FU}, /* RGIDR_MODID[559]:ARSTM0*/ + /* After setting */ /* RGIDR_MODID[560]:ARSTM1*/ + [534] = {0xFC86202CU, 0x0000000EU}, /* RGIDR_MODID[561]:CSD1S*/ + [535] = {0xFC862030U, 0x0000000EU}, /* RGIDR_MODID[562]:AXIFBABUSTOP0*/ + [536] = {0xFC862034U, 0x0000000EU}, /* RGIDR_MODID[563]:AXIFBABUSTOP1*/ + /* After setting */ /* RGIDR_MODID[564]:ARSTM2*/ + [537] = {0xFC86203CU, 0x0000000FU}, /* RGIDR_MODID[565]:ARSTM3*/ + [538] = {0xFC862040U, 0x0000000FU}, /* RGIDR_MODID[566]:ARSTM4*/ + [539] = {0xFC862044U, 0x0000000FU}, /* RGIDR_MODID[567]:ARSTM5*/ + [540] = {0xFC862048U, 0x0000000FU}, /* RGIDR_MODID[568]:ARSTM6*/ + [541] = {0xFC86204CU, 0x0000000FU}, /* RGIDR_MODID[569]:ARSTM7*/ + [542] = {0xFC862050U, 0x00000000U}, /* RGIDR_MODID[570]:ARSTM8*/ + [543] = {0xFC862054U, 0x0000000FU}, /* RGIDR_MODID[571]:ECMTOP*/ + [544] = {0xFC862058U, 0x0000000EU}, /* RGIDR_MODID[572]:FBA*/ + [545] = {0xFC86205CU, 0x0000000EU}, /* RGIDR_MODID[573]:FBC*/ + [546] = {0xFC862060U, 0x0000000CU}, /* RGIDR_MODID[574]:AXICCI00*/ + [547] = {0xFC862064U, 0x0000000CU}, /* RGIDR_MODID[575]:AXICCI01*/ + [548] = {0xFC862068U, 0x0000000CU}, /* RGIDR_MODID[576]:AXICCI10*/ + [549] = {0xFC86206CU, 0x0000000CU}, /* RGIDR_MODID[577]:AXICCI11*/ + [550] = {0xFC862070U, 0x0000000CU}, /* RGIDR_MODID[578]:AXICCI12*/ + [551] = {0xFC862074U, 0x0000000CU}, /* RGIDR_MODID[579]:AXICCI13*/ + [552] = {0xFC862078U, 0x0000000CU}, /* RGIDR_MODID[580]:AXICCI14*/ + [553] = {0xFC86207CU, 0x0000000CU}, /* RGIDR_MODID[581]:AXICCI15*/ + [554] = {0xFC862080U, 0x0000000CU}, /* RGIDR_MODID[582]:AXICCI2*/ + [555] = {0xFC862084U, 0x0000000CU}, /* RGIDR_MODID[583]:AXICCI3*/ + [556] = {0xFC862088U, 0x0000000CU}, /* RGIDR_MODID[584]:AXICCI4*/ + [557] = {0xFC86208CU, 0x0000000CU}, /* RGIDR_MODID[585]:AXICCI5*/ + [558] = {0xFC862090U, 0x0000000CU}, /* RGIDR_MODID[586]:AXICCI6*/ + [559] = {0xFC862094U, 0x0000000CU}, /* RGIDR_MODID[587]:AXICCI7*/ + [560] = {0xFC862098U, 0x0000000CU}, /* RGIDR_MODID[588]:AXICCI8*/ + [561] = {0xFC86209CU, 0x0000000FU}, /* RGIDR_MODID[589]:AXICCI9*/ + [562] = {0xFC8620A0U, 0x0000000FU}, /* RGIDR_MODID[590]:ECMSTM*/ + [563] = {0xFCB82000U, 0x0000002CU}, /* RGIDR_MODID[591]:DMASSI00*/ + [564] = {0xFCB82004U, 0x0000002CU}, /* RGIDR_MODID[592]:DMASSI01*/ + [565] = {0xFCB82008U, 0x0000002CU}, /* RGIDR_MODID[593]:DMASSI02*/ + [566] = {0xFCB8200CU, 0x0000002CU}, /* RGIDR_MODID[594]:DMASSI03*/ + [567] = {0xFCB82010U, 0x0000002CU}, /* RGIDR_MODID[595]:DMASSI04*/ + [568] = {0xFCB82014U, 0x0000004EU}, /* RGIDR_MODID[596]:DMAI2C0*/ + [569] = {0xFCB82018U, 0x0000004EU}, /* RGIDR_MODID[597]:DMAI2C1*/ + [570] = {0xFCB8201CU, 0x0000004EU}, /* RGIDR_MODID[598]:DMAI2C2*/ + [571] = {0xFCB82020U, 0x0000004EU}, /* RGIDR_MODID[599]:DMAI2C3*/ + [572] = {0xFCB82024U, 0x0000004EU}, /* RGIDR_MODID[600]:DMAI2C4*/ + [573] = {0xFCB82028U, 0x0000004EU}, /* RGIDR_MODID[601]:DMAI2C5*/ + [574] = {0xFCB8202CU, 0x0000002CU}, /* RGIDR_MODID[602]:DMASSI05*/ + [575] = {0xFCB82030U, 0x0000002CU}, /* RGIDR_MODID[603]:DMASSI06*/ + [576] = {0xFCB82034U, 0x0000002CU}, /* RGIDR_MODID[604]:DMASSI07*/ + [577] = {0xFDDC2000U, 0x00000007U}, /* RGIDR_MODID[605]:ARMM*/ + /* After setting */ /* RGIDR_MODID[606]:AXIARNMM*/ + [578] = {0xFDDC2008U, 0x0000000FU}, /* RGIDR_MODID[607]:ARSM0*/ + /* After setting */ /* RGIDR_MODID[608]:ARSM1*/ + /* After setting */ /* RGIDR_MODID[609]:ARSM2*/ + [579] = {0xFDDC2014U, 0x0000000FU}, /* RGIDR_MODID[610]:AXIQOS0*/ + [580] = {0xFDDC2018U, 0x0000000FU}, /* RGIDR_MODID[611]:AXIQOS1*/ + [581] = {0xFDDC201CU, 0x0000000FU}, /* RGIDR_MODID[612]:AXIQOS2*/ + [582] = {0xFDDC2020U, 0x0000000FU}, /* RGIDR_MODID[613]:AXIQOS3*/ + [583] = {0xFDDC2024U, 0x0000000FU}, /* RGIDR_MODID[614]:AXIQOS4*/ + [584] = {0xFDDC2028U, 0x0000000FU}, /* RGIDR_MODID[615]:AXIQOS5*/ + [585] = {0xFDDC202CU, 0x0000000FU}, /* RGIDR_MODID[616]:AXIQOS6*/ + [586] = {0xFDDC2030U, 0x0000000FU}, /* RGIDR_MODID[617]:AXIQOS7*/ + [587] = {0xFDDC2034U, 0x0000000FU}, /* RGIDR_MODID[618]:ARSM3*/ + [588] = {0xFDDC2038U, 0x0000000FU}, /* RGIDR_MODID[619]:ARSM4*/ + [589] = {0xFDDC203CU, 0x0000000FU}, /* RGIDR_MODID[620]:ARSM5*/ + [590] = {0xFDDC2040U, 0x0000000FU}, /* RGIDR_MODID[621]:ARSM6*/ + [591] = {0xFDDC2044U, 0x0000000FU}, /* RGIDR_MODID[622]:ARSM7*/ + [592] = {0xFDDC2048U, 0x00000000U}, /* RGIDR_MODID[623]:ARSM8*/ + [593] = {0xFDDC204CU, 0x0000000BU}, /* RGIDR_MODID[624]:AXMM0*/ + [594] = {0xFDDC2050U, 0x0000000BU}, /* RGIDR_MODID[625]:AXMM1*/ + [595] = {0xFDDC2054U, 0x00000000U}, /* RGIDR_MODID[626]:AXMMPMON*/ + [596] = {0xFDDC2058U, 0x0000000AU}, /* RGIDR_MODID[627]:CKMMM*/ + [597] = {0xFDDC205CU, 0x0000000FU}, /* RGIDR_MODID[628]:ECMMM*/ + [598] = {0xFDDC2060U, 0x0000000EU}, /* RGIDR_MODID[629]:FBADBSC0*/ + [599] = {0xFDDC2064U, 0x0000000EU}, /* RGIDR_MODID[630]:FBADBSC1*/ + [600] = {0xFDDC2068U, 0x0000000EU}, /* RGIDR_MODID[631]:FBAMM*/ + [601] = {0xFDDC206CU, 0x0000004EU}, /* RGIDR_MODID[632]:IPMMUMM00*/ + [602] = {0xFDDC2070U, 0x0000000FU}, /* RGIDR_MODID[633]:DBS0A0*/ + [603] = {0xFDDC2074U, 0x0000000AU}, /* RGIDR_MODID[634]:DBS0A1*/ + [604] = {0xFDDC2078U, 0x0000000FU}, /* RGIDR_MODID[635]:DBS1A0*/ + [605] = {0xFDDC207CU, 0x0000000AU}, /* RGIDR_MODID[636]:DBS1A1*/ + [606] = {0xFDDC2080U, 0x0000000FU}, /* RGIDR_MODID[637]:AXCIDBS*/ + [607] = {0xFDDC2084U, 0x00000009U}, /* RGIDR_MODID[638]:FCPRC*/ + [608] = {0xFDDC2088U, 0x0000000FU}, /* RGIDR_MODID[639]:DBS0D0*/ + [609] = {0xFDDC208CU, 0x0000000AU}, /* RGIDR_MODID[640]:DBS0D1*/ + [610] = {0xFDDC2090U, 0x0000000FU}, /* RGIDR_MODID[641]:DBS1D0*/ + [611] = {0xFDDC2094U, 0x0000000AU}, /* RGIDR_MODID[642]:DBS1D1*/ + [612] = {0xFDDC2098U, 0x0000000EU}, /* RGIDR_MODID[643]:FBADDR*/ + [613] = {0xFDDC209CU, 0x0000004EU}, /* RGIDR_MODID[644]:IPMMUMM01*/ + [614] = {0xFDDC20A0U, 0x0000004EU}, /* RGIDR_MODID[645]:IPMMUMM10*/ + [615] = {0xFDDC20A4U, 0x0000004EU}, /* RGIDR_MODID[646]:IPMMUMM11*/ + [616] = {0xFDDC20A8U, 0x0000004EU}, /* RGIDR_MODID[647]:IPMMUMM12*/ + [617] = {0xFDDC20ACU, 0x0000004EU}, /* RGIDR_MODID[648]:IPMMUMM13*/ + [618] = {0xFDDC20B0U, 0x0000004EU}, /* RGIDR_MODID[649]:IPMMUMM14*/ + [619] = {0xFDDC20B4U, 0x0000004EU}, /* RGIDR_MODID[650]:IPMMUMM15*/ + [620] = {0xFDDC20B8U, 0x0000004EU}, /* RGIDR_MODID[651]:IPMMUMM02*/ + [621] = {0xFDDC20BCU, 0x0000004EU}, /* RGIDR_MODID[652]:IPMMUMM03*/ + [622] = {0xFDDC20C0U, 0x0000004EU}, /* RGIDR_MODID[653]:IPMMUMM04*/ + [623] = {0xFDDC20C4U, 0x0000004EU}, /* RGIDR_MODID[654]:IPMMUMM05*/ + [624] = {0xFDDC20C8U, 0x0000004EU}, /* RGIDR_MODID[655]:IPMMUMM06*/ + [625] = {0xFDDC20CCU, 0x0000004EU}, /* RGIDR_MODID[656]:IPMMUMM07*/ + [626] = {0xFDDC20D0U, 0x0000004EU}, /* RGIDR_MODID[657]:IPMMUMM08*/ + [627] = {0xFDDC20D4U, 0x0000004EU}, /* RGIDR_MODID[658]:IPMMUMM09*/ + [628] = {0xFC802000U, 0x0000000FU}, /* RGIDR_MODID[659]:ARSN0*/ + /* After setting */ /* RGIDR_MODID[660]:ARSN1*/ + /* After setting */ /* RGIDR_MODID[661]:ARSN2*/ + [629] = {0xFC80200CU, 0x0000000FU}, /* RGIDR_MODID[662]:ARSN3*/ + [630] = {0xFC802010U, 0x0000000FU}, /* RGIDR_MODID[663]:ARSN4*/ + [631] = {0xFC802014U, 0x0000000FU}, /* RGIDR_MODID[664]:ARSN5*/ + [632] = {0xFC802018U, 0x0000000FU}, /* RGIDR_MODID[665]:ARSN6*/ + [633] = {0xFC80201CU, 0x00000007U}, /* RGIDR_MODID[666]:ARSN7*/ + [634] = {0xFC802020U, 0x00000000U}, /* RGIDR_MODID[667]:ARSN8*/ + [635] = {0xFC802024U, 0x0000000FU}, /* RGIDR_MODID[668]:ECMTOP3*/ + [636] = {0xFCB52000U, 0x0000000FU}, /* RGIDR_MODID[669]:ARSD00*/ + /* After setting */ /* RGIDR_MODID[670]:ARSD01*/ + /* After setting */ /* RGIDR_MODID[671]:ARSD02*/ + [637] = {0xFCB5200CU, 0x0000000FU}, /* RGIDR_MODID[672]:ARSD03*/ + [638] = {0xFCB52010U, 0x0000000FU}, /* RGIDR_MODID[673]:ARSD04*/ + [639] = {0xFCB52014U, 0x0000000FU}, /* RGIDR_MODID[674]:ARSD05*/ + [640] = {0xFCB52018U, 0x0000000FU}, /* RGIDR_MODID[675]:ARSD06*/ + [641] = {0xFCB5201CU, 0x0000004AU}, /* RGIDR_MODID[676]:AXIFRAY*/ + [642] = {0xFCB52020U, 0x0000000FU}, /* RGIDR_MODID[677]:AXIIPC*/ + [643] = {0xFCB52028U, 0x0000004FU}, /* RGIDR_MODID[678]:AXIRPC*/ + [644] = {0xFCB5202CU, 0x0000000FU}, /* RGIDR_MODID[679]:AXISDHI0*/ + [645] = {0xFCB52030U, 0x0000000FU}, /* RGIDR_MODID[680]:ARSD07*/ + [646] = {0xFCB52034U, 0x00000000U}, /* RGIDR_MODID[681]:ARSD08*/ + [647] = {0xFCB52038U, 0x0000000FU}, /* RGIDR_MODID[682]:ARSP00*/ + /* After setting */ /* RGIDR_MODID[683]:ARSP01*/ + /* After setting */ /* RGIDR_MODID[684]:ARSP02*/ + [648] = {0xFCB52044U, 0x0000000FU}, /* RGIDR_MODID[685]:ARSP03*/ + [649] = {0xFCB52048U, 0x0000000FU}, /* RGIDR_MODID[686]:ARSP04*/ + [650] = {0xFCB5204CU, 0x0000000FU}, /* RGIDR_MODID[687]:ARSP05*/ + [651] = {0xFCB52050U, 0x0000000FU}, /* RGIDR_MODID[688]:ARSP06*/ + [652] = {0xFCB52054U, 0x00000007U}, /* RGIDR_MODID[689]:ARSP07*/ + [653] = {0xFCB52058U, 0x00000000U}, /* RGIDR_MODID[690]:ARSP08*/ + [654] = {0xFCB5205CU, 0x0000004EU}, /* RGIDR_MODID[691]:IPMMUDS001*/ + [655] = {0xFCB52060U, 0x0000000AU}, /* RGIDR_MODID[692]:CKMPER0*/ + [656] = {0xFCB52064U, 0x0000000FU}, /* RGIDR_MODID[693]:ECMPER0*/ + [657] = {0xFCB52068U, 0x0000000EU}, /* RGIDR_MODID[694]:FBAPER0*/ + [658] = {0xFCB5206CU, 0x0000004EU}, /* RGIDR_MODID[695]:FSO0*/ + [659] = {0xFCB52070U, 0x0000004EU}, /* RGIDR_MODID[696]:FSO1*/ + [660] = {0xFCB52074U, 0x0000004EU}, /* RGIDR_MODID[697]:FSO10*/ + [661] = {0xFCB52078U, 0x0000004EU}, /* RGIDR_MODID[698]:FSO2*/ + [662] = {0xFCB5207CU, 0x0000004EU}, /* RGIDR_MODID[699]:FSO3*/ + [663] = {0xFCB52080U, 0x0000004EU}, /* RGIDR_MODID[700]:FSO4*/ + [664] = {0xFCB52084U, 0x0000004EU}, /* RGIDR_MODID[701]:FSO5*/ + [665] = {0xFCB52088U, 0x0000004EU}, /* RGIDR_MODID[702]:FSO6*/ + [666] = {0xFCB5208CU, 0x0000004EU}, /* RGIDR_MODID[703]:FSO7*/ + [667] = {0xFCB52090U, 0x0000004EU}, /* RGIDR_MODID[704]:FSO8*/ + [668] = {0xFCB52094U, 0x0000004EU}, /* RGIDR_MODID[705]:FSO9*/ + [669] = {0xFCB52098U, 0x0000002CU}, /* RGIDR_MODID[706]:ADG*/ + [670] = {0xFCB5209CU, 0x0000000FU}, /* RGIDR_MODID[707]:ECMSD0*/ + [671] = {0xFCB520A0U, 0x0000004EU}, /* RGIDR_MODID[708]:IPMMUDS010*/ + [672] = {0xFCB520A4U, 0x0000004EU}, /* RGIDR_MODID[709]:IPMMUDS011*/ + [673] = {0xFCB520A8U, 0x0000004EU}, /* RGIDR_MODID[710]:I2C0*/ + [674] = {0xFCB520ACU, 0x0000004EU}, /* RGIDR_MODID[711]:I2C1*/ + [675] = {0xFCB520B0U, 0x0000004EU}, /* RGIDR_MODID[712]:I2C2*/ + [676] = {0xFCB520B4U, 0x0000004EU}, /* RGIDR_MODID[713]:I2C3*/ + [677] = {0xFCB520B8U, 0x0000004EU}, /* RGIDR_MODID[714]:I2C4*/ + [678] = {0xFCB520BCU, 0x0000004EU}, /* RGIDR_MODID[715]:I2C5*/ + [679] = {0xFCB520C0U, 0x0000004EU}, /* RGIDR_MODID[716]:IPMMUDS012*/ + [680] = {0xFCB520C4U, 0x0000000FU}, /* RGIDR_MODID[717]:IPC*/ + [681] = {0xFCB520C8U, 0x0000004EU}, /* RGIDR_MODID[718]:IPMMUDS000*/ + [682] = {0xFCB520CCU, 0x0000004EU}, /* RGIDR_MODID[719]:IPMMUDS013*/ + [683] = {0xFCB520D0U, 0x0000004EU}, /* RGIDR_MODID[720]:IPMMUDS014*/ + [684] = {0xFCB520D4U, 0x0000004EU}, /* RGIDR_MODID[721]:IPMMUDS015*/ + [685] = {0xFCB520D8U, 0x0000004EU}, /* RGIDR_MODID[722]:IPMMUDS002*/ + [686] = {0xFCB520DCU, 0x0000004EU}, /* RGIDR_MODID[723]:IPMMUDS003*/ + [687] = {0xFCB520E0U, 0x0000004EU}, /* RGIDR_MODID[724]:IPMMUDS004*/ + [688] = {0xFCB520E4U, 0x0000004EU}, /* RGIDR_MODID[725]:IPMMUDS005*/ + [689] = {0xFCB520E8U, 0x0000002CU}, /* RGIDR_MODID[726]:SSI*/ + [690] = {0xFCB520ECU, 0x0000004EU}, /* RGIDR_MODID[727]:IPMMUDS006*/ + [691] = {0xFCB520F0U, 0x0000004EU}, /* RGIDR_MODID[728]:IPMMUDS007*/ + [692] = {0xFCB520F4U, 0x0000000CU}, /* RGIDR_MODID[729]:SYDM1P*/ + [693] = {0xFCB520F8U, 0x0000004EU}, /* RGIDR_MODID[730]:IPMMUDS008*/ + [694] = {0xFCB520FCU, 0x0000000CU}, /* RGIDR_MODID[731]:SYDM2P*/ + [695] = {0xFCB52100U, 0x0000004EU}, /* RGIDR_MODID[732]:IPMMUDS009*/ + [696] = {0xFCB52240U, 0x0000000CU}, /* RGIDR_MODID[733]:SYDM100*/ + [697] = {0xFCB52244U, 0x0000000CU}, /* RGIDR_MODID[734]:SYDM101*/ + [698] = {0xFCB52248U, 0x0000000CU}, /* RGIDR_MODID[735]:SYDM110*/ + [699] = {0xFCB5224CU, 0x0000000CU}, /* RGIDR_MODID[736]:SYDM111*/ + [700] = {0xFCB52250U, 0x0000000CU}, /* RGIDR_MODID[737]:SYDM112*/ + [701] = {0xFCB52254U, 0x0000000CU}, /* RGIDR_MODID[738]:SYDM113*/ + [702] = {0xFCB52258U, 0x0000000CU}, /* RGIDR_MODID[739]:SYDM114*/ + [703] = {0xFCB5225CU, 0x0000000CU}, /* RGIDR_MODID[740]:SYDM115*/ + [704] = {0xFCB52260U, 0x0000000CU}, /* RGIDR_MODID[741]:SYDM102*/ + [705] = {0xFCB52264U, 0x0000000CU}, /* RGIDR_MODID[742]:SYDM103*/ + [706] = {0xFCB52268U, 0x0000000CU}, /* RGIDR_MODID[743]:SYDM104*/ + [707] = {0xFCB5226CU, 0x0000000CU}, /* RGIDR_MODID[744]:SYDM105*/ + [708] = {0xFCB52270U, 0x0000000CU}, /* RGIDR_MODID[745]:SYDM106*/ + [709] = {0xFCB52274U, 0x0000000CU}, /* RGIDR_MODID[746]:SYDM107*/ + [710] = {0xFCB52278U, 0x0000000CU}, /* RGIDR_MODID[747]:SYDM108*/ + [711] = {0xFCB5227CU, 0x0000000CU}, /* RGIDR_MODID[748]:SYDM109*/ + [712] = {0xFCB52280U, 0x0000000CU}, /* RGIDR_MODID[749]:SYDM200*/ + [713] = {0xFCB52284U, 0x0000000CU}, /* RGIDR_MODID[750]:SYDM201*/ + [714] = {0xFCB52288U, 0x0000000CU}, /* RGIDR_MODID[751]:SYDM210*/ + [715] = {0xFCB5228CU, 0x0000000CU}, /* RGIDR_MODID[752]:SYDM211*/ + [716] = {0xFCB52290U, 0x0000000CU}, /* RGIDR_MODID[753]:SYDM212*/ + [717] = {0xFCB52294U, 0x0000000CU}, /* RGIDR_MODID[754]:SYDM213*/ + [718] = {0xFCB52298U, 0x0000000CU}, /* RGIDR_MODID[755]:SYDM214*/ + [719] = {0xFCB5229CU, 0x0000000CU}, /* RGIDR_MODID[756]:SYDM215*/ + [720] = {0xFCB522A0U, 0x0000000CU}, /* RGIDR_MODID[757]:SYDM202*/ + [721] = {0xFCB522A4U, 0x0000000CU}, /* RGIDR_MODID[758]:SYDM203*/ + [722] = {0xFCB522A8U, 0x0000000CU}, /* RGIDR_MODID[759]:SYDM204*/ + [723] = {0xFCB522ACU, 0x0000000CU}, /* RGIDR_MODID[760]:SYDM205*/ + [724] = {0xFCB522B0U, 0x0000000CU}, /* RGIDR_MODID[761]:SYDM206*/ + [725] = {0xFCB522B4U, 0x0000000CU}, /* RGIDR_MODID[762]:SYDM207*/ + [726] = {0xFCB522B8U, 0x0000000CU}, /* RGIDR_MODID[763]:SYDM208*/ + [727] = {0xFCB522BCU, 0x0000000CU}, /* RGIDR_MODID[764]:SYDM209*/ + [728] = {0xFC682000U, 0x0000000FU}, /* RGIDR_MODID[765]:ARVC0*/ + /* After setting */ /* RGIDR_MODID[766]:ARVC1*/ + /* After setting */ /* RGIDR_MODID[767]:ARVC2*/ + [729] = {0xFC68200CU, 0x0000000FU}, /* RGIDR_MODID[768]:ARVC3*/ + [730] = {0xFC682010U, 0x0000000EU}, /* RGIDR_MODID[769]:AXIFBABUSVC*/ + [731] = {0xFC682014U, 0x0000000FU}, /* RGIDR_MODID[770]:ARVC4*/ + [732] = {0xFC682018U, 0x0000000FU}, /* RGIDR_MODID[771]:ARVC5*/ + [733] = {0xFC68201CU, 0x0000000FU}, /* RGIDR_MODID[772]:ARVC6*/ + [734] = {0xFC682020U, 0x0000000FU}, /* RGIDR_MODID[773]:ARVC7*/ + [735] = {0xFC682024U, 0x00000000U}, /* RGIDR_MODID[774]:ARVC8*/ + [736] = {0xFC682028U, 0x0000000AU}, /* RGIDR_MODID[775]:CKMVC*/ + [737] = {0xFC68202CU, 0x0000000FU}, /* RGIDR_MODID[776]:ECMVC0*/ + [738] = {0xFC682030U, 0x0000004EU}, /* RGIDR_MODID[777]:IMR2*/ + [739] = {0xFC682034U, 0x0000004EU}, /* RGIDR_MODID[778]:IMR0*/ + [740] = {0xFC682038U, 0x0000004EU}, /* RGIDR_MODID[779]:IMR1*/ + [741] = {0xFC68203CU, 0x0000004EU}, /* RGIDR_MODID[780]:IPMMUVC01*/ + [742] = {0xFC682040U, 0x0000004EU}, /* RGIDR_MODID[781]:IPMMUVC10*/ + [743] = {0xFC682044U, 0x0000000CU}, /* RGIDR_MODID[782]:IMS0*/ + [744] = {0xFC682048U, 0x0000000CU}, /* RGIDR_MODID[783]:IMS1*/ + [745] = {0xFC68204CU, 0x0000004EU}, /* RGIDR_MODID[784]:IPMMUVC00*/ + [746] = {0xFC682050U, 0x0000004EU}, /* RGIDR_MODID[785]:IPMMUVC11*/ + [747] = {0xFC682054U, 0x0000004EU}, /* RGIDR_MODID[786]:IPMMUVC12*/ + [748] = {0xFC682058U, 0x0000004EU}, /* RGIDR_MODID[787]:IPMMUVC13*/ + [749] = {0xFC68205CU, 0x0000004EU}, /* RGIDR_MODID[788]:IPMMUVC14*/ + [750] = {0xFC682060U, 0x0000004EU}, /* RGIDR_MODID[789]:IPMMUVC15*/ + [751] = {0xFC682064U, 0x0000004EU}, /* RGIDR_MODID[790]:IPMMUVC02*/ + [752] = {0xFC682068U, 0x0000004EU}, /* RGIDR_MODID[791]:IPMMUVC03*/ + [753] = {0xFC68206CU, 0x0000004EU}, /* RGIDR_MODID[792]:IPMMUVC04*/ + [754] = {0xFC682070U, 0x0000004EU}, /* RGIDR_MODID[793]:IPMMUVC05*/ + [755] = {0xFC682074U, 0x0000004EU}, /* RGIDR_MODID[794]:IPMMUVC06*/ + [756] = {0xFC682078U, 0x0000004EU}, /* RGIDR_MODID[795]:IPMMUVC07*/ + [757] = {0xFC68207CU, 0x0000004EU}, /* RGIDR_MODID[796]:IPMMUVC08*/ + [758] = {0xFC682080U, 0x0000004EU}, /* RGIDR_MODID[797]:IPMMUVC09*/ + [759] = {0xFC682084U, 0x00000028U}, /* RGIDR_MODID[798]:IV1ES*/ + [760] = {0xFEBE2000U, 0x0000004EU}, /* RGIDR_MODID[799]:CSITOP0*/ + [761] = {0xFEBE2004U, 0x0000000FU}, /* RGIDR_MODID[800]:ARVI10*/ + /* After setting */ /* RGIDR_MODID[801]:ARVI11*/ + /* After setting */ /* RGIDR_MODID[802]:ARVI12*/ + [762] = {0xFEBE2010U, 0x0000000FU}, /* RGIDR_MODID[803]:ARVI13*/ + [763] = {0xFEBE2014U, 0x0000000FU}, /* RGIDR_MODID[804]:ARVI14*/ + [764] = {0xFEBE2018U, 0x0000000FU}, /* RGIDR_MODID[805]:ARVI15*/ + [765] = {0xFEBE201CU, 0x0000000FU}, /* RGIDR_MODID[806]:ARVI16*/ + [766] = {0xFEBE2020U, 0x0000000FU}, /* RGIDR_MODID[807]:ARVI17*/ + [767] = {0xFEBE2024U, 0x00000000U}, /* RGIDR_MODID[808]:ARVI18*/ + [768] = {0xFEBE2028U, 0x0000000AU}, /* RGIDR_MODID[809]:CKMVIO*/ + [769] = {0xFEBE202CU, 0x0000004EU}, /* RGIDR_MODID[810]:CSITOP1*/ + [770] = {0xFEBE2034U, 0x0000004EU}, /* RGIDR_MODID[811]:DSITLINK0*/ + [771] = {0xFEBE2038U, 0x0000004EU}, /* RGIDR_MODID[812]:DSITLINK1*/ + [772] = {0xFEBE203CU, 0x0000000FU}, /* RGIDR_MODID[813]:ECMVIO1*/ + [773] = {0xFEBE2044U, 0x0000004EU}, /* RGIDR_MODID[814]:IPMMUVI001*/ + [774] = {0xFEBE2048U, 0x0000000CU}, /* RGIDR_MODID[815]:FCPVX0*/ + [775] = {0xFEBE204CU, 0x0000000CU}, /* RGIDR_MODID[816]:FCPVX1*/ + [776] = {0xFEBE2058U, 0x0000004EU}, /* RGIDR_MODID[817]:IPMMUVI000*/ + [777] = {0xFEBE205CU, 0x0000004EU}, /* RGIDR_MODID[818]:IPMMUVI100*/ + [778] = {0xFEBE2060U, 0x0000004EU}, /* RGIDR_MODID[819]:IPMMUVI010*/ + [779] = {0xFEBE2064U, 0x0000004EU}, /* RGIDR_MODID[820]:IPMMUVI011*/ + [780] = {0xFEBE2068U, 0x0000004EU}, /* RGIDR_MODID[821]:VSPX0*/ + [781] = {0xFEBE206CU, 0x0000004EU}, /* RGIDR_MODID[822]:VSPX1*/ + [782] = {0xFEBE2078U, 0x0000004EU}, /* RGIDR_MODID[823]:IPMMUVI012*/ + [783] = {0xFEBE207CU, 0x0000004EU}, /* RGIDR_MODID[824]:IPMMUVI013*/ + [784] = {0xFEBE2080U, 0x0000004EU}, /* RGIDR_MODID[825]:IPMMUVI014*/ + [785] = {0xFEBE2084U, 0x0000004EU}, /* RGIDR_MODID[826]:IPMMUVI015*/ + [786] = {0xFEBE2088U, 0x0000004EU}, /* RGIDR_MODID[827]:IPMMUVI002*/ + [787] = {0xFEBE208CU, 0x0000004EU}, /* RGIDR_MODID[828]:IPMMUVI003*/ + [788] = {0xFEBE2090U, 0x0000004EU}, /* RGIDR_MODID[829]:IPMMUVI004*/ + [789] = {0xFEBE2094U, 0x0000004EU}, /* RGIDR_MODID[830]:IPMMUVI005*/ + [790] = {0xFEBE2098U, 0x0000004EU}, /* RGIDR_MODID[831]:IPMMUVI006*/ + [791] = {0xFEBE209CU, 0x0000004EU}, /* RGIDR_MODID[832]:IPMMUVI007*/ + [792] = {0xFEBE20A0U, 0x0000004EU}, /* RGIDR_MODID[833]:IPMMUVI008*/ + [793] = {0xFEBE20A4U, 0x0000004EU}, /* RGIDR_MODID[834]:IPMMUVI009*/ + [794] = {0xFEBE20A8U, 0x0000004EU}, /* RGIDR_MODID[835]:IPMMUVI101*/ + [795] = {0xFEBE20ACU, 0x0000004EU}, /* RGIDR_MODID[836]:IPMMUVI110*/ + [796] = {0xFEBE20B0U, 0x0000004EU}, /* RGIDR_MODID[837]:IPMMUVI111*/ + [797] = {0xFEBE20B4U, 0x0000004EU}, /* RGIDR_MODID[838]:IPMMUVI112*/ + [798] = {0xFEBE20B8U, 0x0000004EU}, /* RGIDR_MODID[839]:IPMMUVI113*/ + [799] = {0xFEBE20BCU, 0x0000004EU}, /* RGIDR_MODID[840]:IPMMUVI114*/ + [800] = {0xFEBE20C0U, 0x0000004EU}, /* RGIDR_MODID[841]:IPMMUVI115*/ + [801] = {0xFEBE20C4U, 0x0000004EU}, /* RGIDR_MODID[842]:IPMMUVI102*/ + [802] = {0xFEBE20C8U, 0x0000004EU}, /* RGIDR_MODID[843]:IPMMUVI103*/ + [803] = {0xFEBE20CCU, 0x0000004EU}, /* RGIDR_MODID[844]:IPMMUVI104*/ + [804] = {0xFEBE20D0U, 0x0000004EU}, /* RGIDR_MODID[845]:IPMMUVI105*/ + [805] = {0xFEBE20D4U, 0x0000004EU}, /* RGIDR_MODID[846]:IPMMUVI106*/ + [806] = {0xFEBE20D8U, 0x0000004EU}, /* RGIDR_MODID[847]:IPMMUVI107*/ + [807] = {0xFEBE20DCU, 0x0000004EU}, /* RGIDR_MODID[848]:IPMMUVI108*/ + [808] = {0xFEBE20E0U, 0x0000004EU}, /* RGIDR_MODID[849]:IPMMUVI109*/ + [809] = {0xFEBE2104U, 0x0000000EU}, /* RGIDR_MODID[850]:AXIFBABUSVIO*/ + [810] = {0xFEBF2000U, 0x0000000FU}, /* RGIDR_MODID[851]:ARVI0*/ + /* After setting */ /* RGIDR_MODID[852]:ARVI1*/ + /* After setting */ /* RGIDR_MODID[853]:ARVI2*/ + [811] = {0xFEBF200CU, 0x0000000FU}, /* RGIDR_MODID[854]:ARVI3*/ + [812] = {0xFEBF2010U, 0x0000000FU}, /* RGIDR_MODID[855]:ARVI4*/ + [813] = {0xFEBF2014U, 0x0000000FU}, /* RGIDR_MODID[856]:ARVI5*/ + [814] = {0xFEBF2018U, 0x0000000FU}, /* RGIDR_MODID[857]:ARVI6*/ + [815] = {0xFEBF201CU, 0x0000000FU}, /* RGIDR_MODID[858]:ARVI7*/ + [816] = {0xFEBF2020U, 0x00000000U}, /* RGIDR_MODID[859]:ARVI8*/ + [817] = {0xFEBF2024U, 0x0000000FU}, /* RGIDR_MODID[860]:ECMVIO0*/ + [818] = {0xFEBF2028U, 0x0000004EU}, /* RGIDR_MODID[861]:ISP0*/ + [819] = {0xFEBF202CU, 0x0000004EU}, /* RGIDR_MODID[862]:ISP0CORE*/ + [820] = {0xFEBF2030U, 0x0000004EU}, /* RGIDR_MODID[863]:ISP1*/ + [821] = {0xFEBF2034U, 0x0000004EU}, /* RGIDR_MODID[864]:ISP1CORE*/ + [822] = {0xFEBF2054U, 0x0000004EU}, /* RGIDR_MODID[865]:VIN00*/ + [823] = {0xFEBF2058U, 0x0000004EU}, /* RGIDR_MODID[866]:VIN01*/ + [824] = {0xFEBF205CU, 0x0000004EU}, /* RGIDR_MODID[867]:VIN02*/ + [825] = {0xFEBF2060U, 0x0000004EU}, /* RGIDR_MODID[868]:VIN03*/ + [826] = {0xFEBF2064U, 0x0000004EU}, /* RGIDR_MODID[869]:VIN04*/ + [827] = {0xFEBF2068U, 0x0000004EU}, /* RGIDR_MODID[870]:VIN05*/ + [828] = {0xFEBF206CU, 0x0000004EU}, /* RGIDR_MODID[871]:VIN06*/ + [829] = {0xFEBF2070U, 0x0000004EU}, /* RGIDR_MODID[872]:VIN07*/ + [830] = {0xFEBF2074U, 0x0000004EU}, /* RGIDR_MODID[873]:VIN10*/ + [831] = {0xFEBF2078U, 0x0000004EU}, /* RGIDR_MODID[874]:VIN11*/ + [832] = {0xFEBF207CU, 0x0000004EU}, /* RGIDR_MODID[875]:VIN12*/ + [833] = {0xFEBF2080U, 0x0000004EU}, /* RGIDR_MODID[876]:VIN13*/ + [834] = {0xFEBF2084U, 0x0000004EU}, /* RGIDR_MODID[877]:VIN14*/ + [835] = {0xFEBF2088U, 0x0000004EU}, /* RGIDR_MODID[878]:VIN15*/ + [836] = {0xFEBF208CU, 0x0000004EU}, /* RGIDR_MODID[879]:VIN16*/ + [837] = {0xFEBF2090U, 0x0000004EU}, /* RGIDR_MODID[880]:VIN17*/ + [838] = {0xFC312000U, 0x0000000FU}, /* RGIDR_MODID[881]:ARVIP00*/ + /* After setting */ /* RGIDR_MODID[882]:ARVIP01*/ + /* After setting */ /* RGIDR_MODID[883]:ARVIP02*/ + [839] = {0xFC31200CU, 0x0000000FU}, /* RGIDR_MODID[884]:ARVIP03*/ + [840] = {0xFC312010U, 0x0000000EU}, /* RGIDR_MODID[885]:AXIFBABUSVIP0*/ + [841] = {0xFC312014U, 0x0000000FU}, /* RGIDR_MODID[886]:ARVIP04*/ + [842] = {0xFC312018U, 0x0000000FU}, /* RGIDR_MODID[887]:ARVIP05*/ + [843] = {0xFC31201CU, 0x0000000FU}, /* RGIDR_MODID[888]:ARVIP06*/ + [844] = {0xFC312020U, 0x00000007U}, /* RGIDR_MODID[889]:ARVIP07*/ + [845] = {0xFC312024U, 0x00000000U}, /* RGIDR_MODID[890]:ARVIP08*/ + [846] = {0xFC312028U, 0x0000000AU}, /* RGIDR_MODID[891]:CKMVIP*/ + [847] = {0xFC31202CU, 0x0000000FU}, /* RGIDR_MODID[892]:ECMVIP0*/ + [848] = {0xFC312030U, 0x0000004EU}, /* RGIDR_MODID[893]:IPMMUVIP000*/ + [849] = {0xFC312038U, 0x0000004EU}, /* RGIDR_MODID[894]:SMPO0*/ + [850] = {0xFC31203CU, 0x0000004EU}, /* RGIDR_MODID[895]:SMPS0*/ + [851] = {0xFC312040U, 0x0000000CU}, /* RGIDR_MODID[896]:UMFL0*/ + [852] = {0xFC312044U, 0x0000004EU}, /* RGIDR_MODID[897]:IPMMUVIP001*/ + [853] = {0xFC312048U, 0x0000004EU}, /* RGIDR_MODID[898]:IPMMUVIP010*/ + [854] = {0xFC31204CU, 0x0000004EU}, /* RGIDR_MODID[899]:IPMMUVIP011*/ + [855] = {0xFC312050U, 0x0000004EU}, /* RGIDR_MODID[900]:UMFL0M_W*/ + [856] = {0xFC312054U, 0x0000004EU}, /* RGIDR_MODID[901]:IPMMUVIP012*/ + [857] = {0xFC312058U, 0x0000004EU}, /* RGIDR_MODID[902]:IPMMUVIP013*/ + [858] = {0xFC31205CU, 0x0000004EU}, /* RGIDR_MODID[903]:IPMMUVIP014*/ + [859] = {0xFC312060U, 0x0000004EU}, /* RGIDR_MODID[904]:IPMMUVIP015*/ + [860] = {0xFC312064U, 0x0000004EU}, /* RGIDR_MODID[905]:IPMMUVIP002*/ + [861] = {0xFC312068U, 0x0000004EU}, /* RGIDR_MODID[906]:IPMMUVIP003*/ + [862] = {0xFC31206CU, 0x0000004EU}, /* RGIDR_MODID[907]:IPMMUVIP004*/ + [863] = {0xFC312070U, 0x0000004EU}, /* RGIDR_MODID[908]:IPMMUVIP005*/ + [864] = {0xFC312074U, 0x0000004EU}, /* RGIDR_MODID[909]:IPMMUVIP006*/ + [865] = {0xFC312078U, 0x0000004EU}, /* RGIDR_MODID[910]:IPMMUVIP007*/ + [866] = {0xFC31207CU, 0x0000004EU}, /* RGIDR_MODID[911]:IPMMUVIP008*/ + [867] = {0xFC312080U, 0x0000004EU}, /* RGIDR_MODID[912]:IPMMUVIP009*/ + [868] = {0xFC342000U, 0x0000000FU}, /* RGIDR_MODID[913]:ARVIP10*/ + /* After setting */ /* RGIDR_MODID[914]:ARVIP11*/ + /* After setting */ /* RGIDR_MODID[915]:ARVIP12*/ + [869] = {0xFC34200CU, 0x0000000FU}, /* RGIDR_MODID[916]:ARVIP13*/ + [870] = {0xFC342010U, 0x0000000EU}, /* RGIDR_MODID[917]:AXIFBABUSVIP1*/ + [871] = {0xFC342014U, 0x0000000FU}, /* RGIDR_MODID[918]:ARVIIP14*/ + [872] = {0xFC342018U, 0x0000000FU}, /* RGIDR_MODID[919]:ARVIIP15*/ + [873] = {0xFC34201CU, 0x0000000FU}, /* RGIDR_MODID[920]:ARVIIP16*/ + [874] = {0xFC342020U, 0x0000000FU}, /* RGIDR_MODID[921]:ARVIIP17*/ + [875] = {0xFC342024U, 0x00000000U}, /* RGIDR_MODID[922]:ARVIIP18*/ + [876] = {0xFC342038U, 0x0000000FU}, /* RGIDR_MODID[923]:ECMVIP1*/ + [877] = {0xFC34203CU, 0x0000004EU}, /* RGIDR_MODID[924]:IPMMUVIP101*/ + [878] = {0xFC342040U, 0x0000004EU}, /* RGIDR_MODID[925]:IPMMUVIP100*/ + [879] = {0xFC342044U, 0x0000004EU}, /* RGIDR_MODID[926]:IPMMUVIP110*/ + [880] = {0xFC342048U, 0x0000004EU}, /* RGIDR_MODID[927]:IPMMUVIP111*/ + [881] = {0xFC34204CU, 0x0000004EU}, /* RGIDR_MODID[928]:IPMMUVIP112*/ + [882] = {0xFC342050U, 0x0000004EU}, /* RGIDR_MODID[929]:IPMMUVIP113*/ + [883] = {0xFC342054U, 0x0000004EU}, /* RGIDR_MODID[930]:IPMMUVIP114*/ + [884] = {0xFC342058U, 0x0000004EU}, /* RGIDR_MODID[931]:IPMMUVIP115*/ + [885] = {0xFC34205CU, 0x0000004EU}, /* RGIDR_MODID[932]:IPMMUVIP102*/ + [886] = {0xFC342060U, 0x0000004EU}, /* RGIDR_MODID[933]:IPMMUVIP103*/ + [887] = {0xFC342064U, 0x0000004EU}, /* RGIDR_MODID[934]:IPMMUVIP104*/ + [888] = {0xFC342068U, 0x0000004EU}, /* RGIDR_MODID[935]:IPMMUVIP105*/ + [889] = {0xFC34206CU, 0x0000004EU}, /* RGIDR_MODID[936]:IPMMUVIP106*/ + [890] = {0xFC342070U, 0x0000004EU}, /* RGIDR_MODID[937]:IPMMUVIP107*/ + [891] = {0xFC342074U, 0x0000004EU}, /* RGIDR_MODID[938]:IPMMUVIP108*/ + [892] = {0xFC342078U, 0x0000004EU}, /* RGIDR_MODID[939]:IPMMUVIP109*/ + [893] = {0xFC342118U, 0x00000004U}, /* RGIDR_MODID[940]:PAP*/ + [894] = {0xFC402000U, 0x0000000FU}, /* RGIDR_MODID[941]:ARDSP0*/ + /* After setting */ /* RGIDR_MODID[942]:ARDSP1*/ + /* After setting */ /* RGIDR_MODID[943]:ARDSP2*/ + [895] = {0xFC40200CU, 0x0000000FU}, /* RGIDR_MODID[944]:ARDSP3*/ + [896] = {0xFC402010U, 0x0000000FU}, /* RGIDR_MODID[945]:ARDSP4*/ + [897] = {0xFC402014U, 0x0000000FU}, /* RGIDR_MODID[946]:ARDSP5*/ + [898] = {0xFC402018U, 0x0000000FU}, /* RGIDR_MODID[947]:ARDSP6*/ + [899] = {0xFC40201CU, 0x0000000FU}, /* RGIDR_MODID[948]:ARDSP7*/ + [900] = {0xFC402020U, 0x0000000FU}, /* RGIDR_MODID[949]:ECMDSP*/ + [901] = {0xFC402024U, 0x0000000CU}, /* RGIDR_MODID[950]:AXIDSP0*/ + [902] = {0xFC402028U, 0x0000000CU}, /* RGIDR_MODID[951]:AXIDSP1*/ + [903] = {0xFC40202CU, 0x0000000CU}, /* RGIDR_MODID[952]:AXIDSP2*/ + [904] = {0xFC402030U, 0x0000000CU}, /* RGIDR_MODID[953]:AXIDSP3*/ + [906] = {0xFDDB9660U, 0x0000000FU}, /* RGIDR_MODID[954]:ARCC*/ + [905] = {0xFDDB9674U, 0x0000000FU}, /* RGIDR_MODID[955]:ARRTRAM*/ + [907] = {0xFCB52024U, 0x00000000U}, /* RGIDR_MODID[956]:RSV0*/ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_w_tbl" +const REGION_ID_SETTING_TABLE g_rgid_w_tbl[] = { + [0] = {0xFD482400U, 0x0000000EU}, /* RGIDW_MODID[0]:ARMGC0*/ + [1] = {0xFD482404U, 0x0000000EU}, /* RGIDW_MODID[1]:ARMGC1*/ + [2] = {0xFD482408U, 0x00000000U}, /* RGIDW_MODID[2]:ARMGC2*/ + [3] = {0xFD48240CU, 0x00000002U}, /* RGIDW_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDW_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDW_MODID[5]:ARRT02*/ + [4] = {0xFD482418U, 0x00000001U}, /* RGIDW_MODID[6]:ARRT03*/ + [5] = {0xFD48241CU, 0x00000002U}, /* RGIDW_MODID[7]:ARRT04*/ + [6] = {0xFD482420U, 0x00000001U}, /* RGIDW_MODID[8]:ARRT05*/ + [7] = {0xFD482424U, 0x00000002U}, /* RGIDW_MODID[9]:ARRT06*/ + [8] = {0xFD482428U, 0x00000002U}, /* RGIDW_MODID[10]:ARRT07*/ + [9] = {0xFD48242CU, 0x00000000U}, /* RGIDW_MODID[11]:ARRT08*/ + [10] = {0xFD482430U, 0x00000001U}, /* RGIDW_MODID[12]:LIFEC0*/ + [11] = {0xFD482434U, 0x0000000EU}, /* RGIDW_MODID[13]:SWDT*/ + [12] = {0xFD482438U, 0x0000006EU}, /* RGIDW_MODID[14]:TMU0*/ + [13] = {0xFD48243CU, 0x0000000EU}, /* RGIDW_MODID[15]:WDT*/ + [14] = {0xFD482440U, 0x0000000EU}, /* RGIDW_MODID[16]:WWDT0*/ + [15] = {0xFD482444U, 0x0000000EU}, /* RGIDW_MODID[17]:WWDT1*/ + [16] = {0xFD482448U, 0x0000000EU}, /* RGIDW_MODID[18]:WWDT2*/ + [17] = {0xFD48244CU, 0x0000000EU}, /* RGIDW_MODID[19]:WWDT3*/ + [18] = {0xFD482450U, 0x0000000EU}, /* RGIDW_MODID[20]:WWDT4*/ + [19] = {0xFD482454U, 0x0000000EU}, /* RGIDW_MODID[21]:WWDT5*/ + [20] = {0xFD482458U, 0x0000000EU}, /* RGIDW_MODID[22]:WWDT6*/ + [21] = {0xFD482468U, 0x0000000AU}, /* RGIDW_MODID[23]:ECMRT3*/ + [22] = {0xFDA02400U, 0x00000006U}, /* RGIDW_MODID[24]:ADVFSC*/ + [23] = {0xFDA02404U, 0x0000000FU}, /* RGIDW_MODID[25]:APMU0*/ + [24] = {0xFDA02408U, 0x00000002U}, /* RGIDW_MODID[26]:APMU1*/ + [25] = {0xFDA0240CU, 0x00000000U}, /* RGIDW_MODID[27]:APMU10*/ + [26] = {0xFDA02410U, 0x00000000U}, /* RGIDW_MODID[28]:APMU11*/ + [27] = {0xFDA02414U, 0x00000000U}, /* RGIDW_MODID[29]:APMU12*/ + [28] = {0xFDA02418U, 0x00000000U}, /* RGIDW_MODID[30]:APMU13*/ + [29] = {0xFDA0241CU, 0x00000000U}, /* RGIDW_MODID[31]:APMU14*/ + [30] = {0xFDA02420U, 0x00000000U}, /* RGIDW_MODID[32]:APMU15*/ + [31] = {0xFDA02424U, 0x00000004U}, /* RGIDW_MODID[33]:APMU2*/ + [32] = {0xFDA02428U, 0x00000004U}, /* RGIDW_MODID[34]:APMU3*/ + [33] = {0xFDA0242CU, 0x00000000U}, /* RGIDW_MODID[35]:APMU4*/ + [34] = {0xFDA02430U, 0x00000000U}, /* RGIDW_MODID[36]:APMU5*/ + [35] = {0xFDA02434U, 0x00000000U}, /* RGIDW_MODID[37]:APMU6*/ + [36] = {0xFDA02438U, 0x00000000U}, /* RGIDW_MODID[38]:APMU7*/ + [37] = {0xFDA0243CU, 0x00000000U}, /* RGIDW_MODID[39]:APMU8*/ + [38] = {0xFDA02440U, 0x00000000U}, /* RGIDW_MODID[40]:APMU9*/ + [39] = {0xFDA02444U, 0x00000002U}, /* RGIDW_MODID[41]:ARS00*/ + /* After setting */ /* RGIDW_MODID[42]:ARS01*/ + /* After setting */ /* RGIDW_MODID[43]:ARS02*/ + [40] = {0xFDA02450U, 0x00000001U}, /* RGIDW_MODID[44]:ARS03*/ + [41] = {0xFDA02454U, 0x00000002U}, /* RGIDW_MODID[45]:ARS04*/ + [42] = {0xFDA02458U, 0x00000001U}, /* RGIDW_MODID[46]:ARS05*/ + [43] = {0xFDA0245CU, 0x00000002U}, /* RGIDW_MODID[47]:ARS06*/ + [44] = {0xFDA02460U, 0x00000002U}, /* RGIDW_MODID[48]:ARS07*/ + [45] = {0xFDA02464U, 0x00000000U}, /* RGIDW_MODID[49]:ARS08*/ + [46] = {0xFDA02468U, 0x0000000EU}, /* RGIDW_MODID[50]:CMT0*/ + [47] = {0xFDA0246CU, 0x0000000EU}, /* RGIDW_MODID[51]:CMT1*/ + [48] = {0xFDA02470U, 0x0000000EU}, /* RGIDW_MODID[52]:CMT2*/ + [49] = {0xFDA02474U, 0x0000000EU}, /* RGIDW_MODID[53]:CMT3*/ + [50] = {0xFDA02478U, 0x0000000AU}, /* RGIDW_MODID[54]:CKM*/ + [51] = {0xFDA0247CU, 0x0000000EU}, /* RGIDW_MODID[55]:DBE*/ + [52] = {0xFDA02480U, 0x0000000EU}, /* RGIDW_MODID[56]:IRQC*/ + [53] = {0xFDA02484U, 0x0000000AU}, /* RGIDW_MODID[57]:ECMPS0*/ + [54] = {0xFDA02488U, 0x0000000BU}, /* RGIDW_MODID[58]:OTP0*/ + [55] = {0xFDA0248CU, 0x0000000FU}, /* RGIDW_MODID[59]:OTP1*/ + [56] = {0xFDA0249CU, 0x0000000EU}, /* RGIDW_MODID[60]:SCMT*/ + [57] = {0xFDA024A8U, 0x0000004AU}, /* RGIDW_MODID[61]:TSC1*/ + [58] = {0xFDA024ACU, 0x0000004AU}, /* RGIDW_MODID[62]:TSC2*/ + [59] = {0xFDA024B0U, 0x0000004AU}, /* RGIDW_MODID[63]:TSC3*/ + [60] = {0xFDA024B4U, 0x0000004AU}, /* RGIDW_MODID[64]:TSC4*/ + [61] = {0xFDA024B8U, 0x00000006U}, /* RGIDW_MODID[65]:UCMT*/ + [62] = {0xFDA02500U, 0x0000006FU}, /* RGIDW_MODID[66]:CPG0*/ + [63] = {0xFDA02504U, 0x0000000AU}, /* RGIDW_MODID[67]:CPG1*/ + [64] = {0xFDA02508U, 0x0000004EU}, /* RGIDW_MODID[68]:CPG2*/ + [65] = {0xFDA0250CU, 0x00000028U}, /* RGIDW_MODID[69]:CPG3*/ + [66] = {0xFDA02510U, 0x0000006FU}, /* RGIDW_MODID[70]:PFC00*/ + [67] = {0xFDA02514U, 0x0000000AU}, /* RGIDW_MODID[71]:PFC01*/ + [68] = {0xFDA02518U, 0x0000004EU}, /* RGIDW_MODID[72]:PFC02*/ + [69] = {0xFDA0251CU, 0x00000028U}, /* RGIDW_MODID[73]:PFC03*/ + [70] = {0xFDA02520U, 0x0000006FU}, /* RGIDW_MODID[74]:PFC10*/ + [71] = {0xFDA02524U, 0x0000000AU}, /* RGIDW_MODID[75]:PFC11*/ + [72] = {0xFDA02528U, 0x0000004EU}, /* RGIDW_MODID[76]:PFC12*/ + [73] = {0xFDA0252CU, 0x00000028U}, /* RGIDW_MODID[77]:PFC13*/ + [74] = {0xFDA02530U, 0x0000006FU}, /* RGIDW_MODID[78]:PFC20*/ + [75] = {0xFDA02534U, 0x0000000AU}, /* RGIDW_MODID[79]:PFC21*/ + [76] = {0xFDA02538U, 0x0000004EU}, /* RGIDW_MODID[80]:PFC22*/ + [77] = {0xFDA0253CU, 0x00000028U}, /* RGIDW_MODID[81]:PFC23*/ + [78] = {0xFDA02540U, 0x0000006FU}, /* RGIDW_MODID[82]:PFC30*/ + [79] = {0xFDA02544U, 0x0000000AU}, /* RGIDW_MODID[83]:PFC31*/ + [80] = {0xFDA02548U, 0x0000004EU}, /* RGIDW_MODID[84]:PFC32*/ + [81] = {0xFDA0254CU, 0x00000028U}, /* RGIDW_MODID[85]:PFC33*/ + [82] = {0xFDA02550U, 0x0000006FU}, /* RGIDW_MODID[86]:PFCS0*/ + [83] = {0xFDA02554U, 0x0000000AU}, /* RGIDW_MODID[87]:PFCS1*/ + [84] = {0xFDA02558U, 0x0000004EU}, /* RGIDW_MODID[88]:PFCS2*/ + [85] = {0xFDA0255CU, 0x00000028U}, /* RGIDW_MODID[89]:PFCS3*/ + [86] = {0xFDA02560U, 0x0000006FU}, /* RGIDW_MODID[90]:RESET0*/ + [87] = {0xFDA02564U, 0x0000000AU}, /* RGIDW_MODID[91]:RESET1*/ + [88] = {0xFDA02568U, 0x0000004EU}, /* RGIDW_MODID[92]:RESET2*/ + [89] = {0xFDA0256CU, 0x00000028U}, /* RGIDW_MODID[93]:RESET3*/ + [90] = {0xFDA02570U, 0x0000006FU}, /* RGIDW_MODID[94]:SYS0*/ + [91] = {0xFDA02574U, 0x0000000AU}, /* RGIDW_MODID[95]:SYS1*/ + [92] = {0xFDA02578U, 0x0000004EU}, /* RGIDW_MODID[96]:SYS2*/ + [93] = {0xFDA0257CU, 0x00000028U}, /* RGIDW_MODID[97]:SYS3*/ + [94] = {0xFCB62400U, 0x0000000EU}, /* RGIDW_MODID[98]:DMAMSI0*/ + [95] = {0xFCB62404U, 0x0000000EU}, /* RGIDW_MODID[99]:DMAMSI1*/ + [96] = {0xFCB62408U, 0x0000000EU}, /* RGIDW_MODID[100]:DMAMSI2*/ + [97] = {0xFCB6240CU, 0x0000000EU}, /* RGIDW_MODID[101]:DMAMSI3*/ + [98] = {0xFCB62410U, 0x0000000EU}, /* RGIDW_MODID[102]:DMAMSI4*/ + [99] = {0xFCB62414U, 0x0000000EU}, /* RGIDW_MODID[103]:DMAMSI5*/ + [100] = {0xFCB62418U, 0x0000000AU}, /* RGIDW_MODID[104]:ECMSP3*/ + [101] = {0xFCB62424U, 0x00000002U}, /* RGIDW_MODID[105]:ARSP30*/ + /* After setting */ /* RGIDW_MODID[106]:ARSP31*/ + /* After setting */ /* RGIDW_MODID[107]:ARSP32*/ + [102] = {0xFCB62430U, 0x00000001U}, /* RGIDW_MODID[108]:ARSP33*/ + [103] = {0xFCB62434U, 0x00000002U}, /* RGIDW_MODID[109]:ARSP34*/ + [104] = {0xFCB62438U, 0x00000001U}, /* RGIDW_MODID[110]:ARSP35*/ + [105] = {0xFCB6243CU, 0x00000002U}, /* RGIDW_MODID[111]:ARSP36*/ + [106] = {0xFCB62440U, 0x00000002U}, /* RGIDW_MODID[112]:ARSP37*/ + [107] = {0xFCB62444U, 0x00000000U}, /* RGIDW_MODID[113]:ARSP38*/ + [108] = {0xFCB62448U, 0x0000000EU}, /* RGIDW_MODID[114]:MSI0*/ + [109] = {0xFCB6244CU, 0x0000000EU}, /* RGIDW_MODID[115]:MSI1*/ + [110] = {0xFCB62450U, 0x0000000EU}, /* RGIDW_MODID[116]:MSI2*/ + [111] = {0xFCB62454U, 0x0000000EU}, /* RGIDW_MODID[117]:MSI3*/ + [112] = {0xFCB62458U, 0x0000000EU}, /* RGIDW_MODID[118]:MSI4*/ + [113] = {0xFCB6245CU, 0x0000000EU}, /* RGIDW_MODID[119]:MSI5*/ + [114] = {0xFCB92400U, 0x00000002U}, /* RGIDW_MODID[120]:ARSP40*/ + /* After setting */ /* RGIDW_MODID[121]:ARSP41*/ + /* After setting */ /* RGIDW_MODID[122]:ARSP42*/ + [115] = {0xFCB9240CU, 0x00000001U}, /* RGIDW_MODID[123]:ARSP43*/ + [116] = {0xFCB92410U, 0x00000002U}, /* RGIDW_MODID[124]:ARSP44*/ + [117] = {0xFCB92414U, 0x00000001U}, /* RGIDW_MODID[125]:ARSP45*/ + [118] = {0xFCB92418U, 0x00000002U}, /* RGIDW_MODID[126]:ARSP46*/ + [119] = {0xFCB9241CU, 0x00000002U}, /* RGIDW_MODID[127]:ARSP47*/ + [120] = {0xFCB92420U, 0x00000000U}, /* RGIDW_MODID[128]:ARSP48*/ + [121] = {0xFCB92424U, 0x0000004FU}, /* RGIDW_MODID[129]:DMAHSCIF0*/ + [122] = {0xFCB92428U, 0x0000004FU}, /* RGIDW_MODID[130]:DMAHSCIF1*/ + [123] = {0xFCB9242CU, 0x0000004FU}, /* RGIDW_MODID[131]:DMAHSCIF2*/ + [124] = {0xFCB92430U, 0x0000004FU}, /* RGIDW_MODID[132]:DMAHSCIF3*/ + [125] = {0xFCB92434U, 0x0000004FU}, /* RGIDW_MODID[133]:DMASCIF0*/ + [126] = {0xFCB92438U, 0x0000004FU}, /* RGIDW_MODID[134]:DMASCIF1*/ + [127] = {0xFCB9243CU, 0x0000004FU}, /* RGIDW_MODID[135]:DMASCIF3*/ + [128] = {0xFCB92440U, 0x0000004FU}, /* RGIDW_MODID[136]:DMASCIF4*/ + [129] = {0xFCB92444U, 0x0000000AU}, /* RGIDW_MODID[137]:ECMSP4*/ + [130] = {0xFCB92448U, 0x0000004FU}, /* RGIDW_MODID[138]:HSCIF0*/ + [131] = {0xFCB9244CU, 0x0000004FU}, /* RGIDW_MODID[139]:HSCIF1*/ + [132] = {0xFCB92450U, 0x0000004FU}, /* RGIDW_MODID[140]:HSCIF2*/ + [133] = {0xFCB92454U, 0x0000004FU}, /* RGIDW_MODID[141]:HSCIF3*/ + [134] = {0xFCB92458U, 0x0000004FU}, /* RGIDW_MODID[142]:SCIF0*/ + [135] = {0xFCB9245CU, 0x0000004FU}, /* RGIDW_MODID[143]:SCIF1*/ + [136] = {0xFCB92460U, 0x0000004FU}, /* RGIDW_MODID[144]:SCIF3*/ + [137] = {0xFCB92464U, 0x0000004FU}, /* RGIDW_MODID[145]:SCIF4*/ + [138] = {0xFCB92468U, 0x0000006EU}, /* RGIDW_MODID[146]:TMU1*/ + [139] = {0xFCB9246CU, 0x0000006EU}, /* RGIDW_MODID[147]:TMU2*/ + [140] = {0xFCB92470U, 0x0000006EU}, /* RGIDW_MODID[148]:TMU3*/ + [141] = {0xFCB92474U, 0x0000006EU}, /* RGIDW_MODID[149]:TMU4*/ + [142] = {0xFCB92478U, 0x0000004AU}, /* RGIDW_MODID[150]:CANFD*/ + [143] = {0xFCB9247CU, 0x0000004AU}, /* RGIDW_MODID[151]:DMACANFD*/ + [144] = {0xFCB92480U, 0x00000002U}, /* RGIDW_MODID[152]:DMATPU0*/ + [145] = {0xFCB92484U, 0x00000002U}, /* RGIDW_MODID[153]:PWM0*/ + [146] = {0xFCB92488U, 0x00000002U}, /* RGIDW_MODID[154]:PWM1*/ + [147] = {0xFCB9248CU, 0x00000002U}, /* RGIDW_MODID[155]:PWM2*/ + [148] = {0xFCB92490U, 0x00000002U}, /* RGIDW_MODID[156]:PWM3*/ + [149] = {0xFCB92494U, 0x00000002U}, /* RGIDW_MODID[157]:PWM4*/ + [150] = {0xFCB92498U, 0x00000002U}, /* RGIDW_MODID[158]:PWM5*/ + [151] = {0xFCB9249CU, 0x00000002U}, /* RGIDW_MODID[159]:PWM6*/ + [152] = {0xFCB924A0U, 0x00000002U}, /* RGIDW_MODID[160]:PWM7*/ + [153] = {0xFCB924A4U, 0x00000002U}, /* RGIDW_MODID[161]:PWM8*/ + [154] = {0xFCB924A8U, 0x00000002U}, /* RGIDW_MODID[162]:PWM9*/ + [155] = {0xFCB924ACU, 0x00000002U}, /* RGIDW_MODID[163]:TPU0*/ + [156] = {0xFC672400U, 0x00000002U}, /* RGIDW_MODID[164]:ARVC10*/ + /* After setting */ /* RGIDW_MODID[165]:ARVC11*/ + /* After setting */ /* RGIDW_MODID[166]:ARVC12*/ + [157] = {0xFC67240CU, 0x00000001U}, /* RGIDW_MODID[167]:ARVC13*/ + [158] = {0xFC672410U, 0x00000002U}, /* RGIDW_MODID[168]:ARVC14*/ + [159] = {0xFC672414U, 0x00000001U}, /* RGIDW_MODID[169]:ARVC15*/ + [160] = {0xFC672418U, 0x00000002U}, /* RGIDW_MODID[170]:ARVC16*/ + [161] = {0xFC67241CU, 0x00000002U}, /* RGIDW_MODID[171]:ARVC17*/ + [162] = {0xFC672420U, 0x00000000U}, /* RGIDW_MODID[172]:ARVC18*/ + [163] = {0xFC672424U, 0x0000000AU}, /* RGIDW_MODID[173]:ECMVC1*/ + [164] = {0xFC672428U, 0x00000028U}, /* RGIDW_MODID[174]:FCPCS*/ + [165] = {0xFC67242CU, 0x00000028U}, /* RGIDW_MODID[175]:VCP4LC*/ + [166] = {0xFC672430U, 0x00000028U}, /* RGIDW_MODID[176]:VCP4LV*/ + [167] = {0xFEBD2400U, 0x00000002U}, /* RGIDW_MODID[177]:ARVI40*/ + /* After setting */ /* RGIDW_MODID[178]:ARVI41*/ + /* After setting */ /* RGIDW_MODID[179]:ARVI42*/ + [168] = {0xFEBD240CU, 0x00000001U}, /* RGIDW_MODID[180]:ARVI43*/ + [169] = {0xFEBD2410U, 0x00000002U}, /* RGIDW_MODID[181]:ARVI44*/ + [170] = {0xFEBD2414U, 0x00000001U}, /* RGIDW_MODID[182]:ARVI45*/ + [171] = {0xFEBD2418U, 0x00000002U}, /* RGIDW_MODID[183]:ARVI46*/ + [172] = {0xFEBD241CU, 0x00000002U}, /* RGIDW_MODID[184]:ARVI47*/ + [173] = {0xFEBD2420U, 0x00000000U}, /* RGIDW_MODID[185]:ARVI48*/ + [174] = {0xFEBD2424U, 0x0000000FU}, /* RGIDW_MODID[186]:DIS0*/ + [175] = {0xFEBD242CU, 0x0000000FU}, /* RGIDW_MODID[187]:DSC*/ + [176] = {0xFEBD2430U, 0x0000000EU}, /* RGIDW_MODID[188]:ECMVIO2*/ + [177] = {0xFEBD2434U, 0x0000000FU}, /* RGIDW_MODID[189]:FCPVD0*/ + [178] = {0xFEBD2438U, 0x0000000FU}, /* RGIDW_MODID[190]:FCPVD1*/ + [179] = {0xFEBD243CU, 0x0000004EU}, /* RGIDW_MODID[191]:VSPD0*/ + [180] = {0xFEBD2440U, 0x0000004EU}, /* RGIDW_MODID[192]:VSPD1*/ + [181] = {0xFCF82400U, 0x0000000AU}, /* RGIDW_MODID[193]:CKMHSC*/ + [182] = {0xFCF82404U, 0x0000000CU}, /* RGIDW_MODID[194]:AXIPCI001*/ + [183] = {0xFCF82408U, 0x0000000CU}, /* RGIDW_MODID[195]:AXIPCI002*/ + [184] = {0xFCF8240CU, 0x0000000CU}, /* RGIDW_MODID[196]:AXIPCI003*/ + [185] = {0xFCF82414U, 0x0000000CU}, /* RGIDW_MODID[197]:AXIPCI005*/ + [186] = {0xFCF82418U, 0x0000000CU}, /* RGIDW_MODID[198]:AXIPCI006*/ + [187] = {0xFCF8241CU, 0x0000000CU}, /* RGIDW_MODID[199]:AXIPCI007*/ + [188] = {0xFCF82420U, 0x0000000CU}, /* RGIDW_MODID[200]:AXIPCI008*/ + [189] = {0xFCF82424U, 0x0000000CU}, /* RGIDW_MODID[201]:AXIPCI009*/ + [190] = {0xFCF82428U, 0x0000000CU}, /* RGIDW_MODID[202]:AXIPCI010*/ + [191] = {0xFCF8242CU, 0x0000000CU}, /* RGIDW_MODID[203]:AXIPCI011*/ + [192] = {0xFCF82430U, 0x0000000CU}, /* RGIDW_MODID[204]:AXIPCI012*/ + [193] = {0xFCF82434U, 0x0000000CU}, /* RGIDW_MODID[205]:AXIPCI013*/ + [194] = {0xFCF82438U, 0x0000000CU}, /* RGIDW_MODID[206]:AXIPCI014*/ + [195] = {0xFCF8243CU, 0x0000000CU}, /* RGIDW_MODID[207]:AXIPCI015*/ + [196] = {0xFCF82440U, 0x0000000CU}, /* RGIDW_MODID[208]:AXIPCI100*/ + [197] = {0xFCF82444U, 0x0000000CU}, /* RGIDW_MODID[209]:AXIPCI101*/ + [198] = {0xFCF82448U, 0x0000000CU}, /* RGIDW_MODID[210]:AXIPCI102*/ + [199] = {0xFCF8244CU, 0x0000000CU}, /* RGIDW_MODID[211]:AXIPCI103*/ + [200] = {0xFCF82450U, 0x0000000CU}, /* RGIDW_MODID[212]:AXIPCI104*/ + [201] = {0xFCF82454U, 0x0000000CU}, /* RGIDW_MODID[213]:AXIPCI105*/ + [202] = {0xFCF82458U, 0x0000000CU}, /* RGIDW_MODID[214]:AXIPCI106*/ + [203] = {0xFCF8245CU, 0x0000000CU}, /* RGIDW_MODID[215]:AXIPCI107*/ + [204] = {0xFCF82460U, 0x0000000CU}, /* RGIDW_MODID[216]:AXIPCI108*/ + [205] = {0xFCF82464U, 0x0000000CU}, /* RGIDW_MODID[217]:AXIPCI109*/ + [206] = {0xFCF82468U, 0x0000000CU}, /* RGIDW_MODID[218]:AXIPCI110*/ + [207] = {0xFCF8246CU, 0x0000000CU}, /* RGIDW_MODID[219]:AXIPCI111*/ + [208] = {0xFCF82470U, 0x0000000CU}, /* RGIDW_MODID[220]:AXIPCI112*/ + [209] = {0xFCF82474U, 0x0000000CU}, /* RGIDW_MODID[221]:AXIPCI113*/ + [210] = {0xFCF82478U, 0x0000000CU}, /* RGIDW_MODID[222]:AXIPCI114*/ + [211] = {0xFCF8247CU, 0x0000000CU}, /* RGIDW_MODID[223]:AXIPCI115*/ + [212] = {0xFCF82484U, 0x0000000EU}, /* RGIDW_MODID[224]:GPTP*/ + [213] = {0xFCF82488U, 0x0000004EU}, /* RGIDW_MODID[225]:IPMMUHC00*/ + [214] = {0xFCF824F0U, 0x0000000EU}, /* RGIDW_MODID[226]:TSN0*/ + [215] = {0xFCF824F4U, 0x0000000CU}, /* RGIDW_MODID[227]:AXIPCI000*/ + [216] = {0xFCF824F8U, 0x0000000CU}, /* RGIDW_MODID[228]:AXIPCI004*/ + [217] = {0xFCF824FCU, 0x0000004EU}, /* RGIDW_MODID[229]:IPMMUHC01*/ + [218] = {0xFCF82500U, 0x0000004EU}, /* RGIDW_MODID[230]:AVB0*/ + [219] = {0xFCF82504U, 0x0000004EU}, /* RGIDW_MODID[231]:AVB1*/ + [220] = {0xFCF82508U, 0x0000004EU}, /* RGIDW_MODID[232]:AVB2*/ + [221] = {0xFCF8250CU, 0x0000004EU}, /* RGIDW_MODID[233]:IPMMUHC10*/ + [222] = {0xFCF82510U, 0x0000004EU}, /* RGIDW_MODID[234]:IPMMUHC11*/ + [223] = {0xFCF82514U, 0x0000004EU}, /* RGIDW_MODID[235]:IPMMUHC12*/ + [224] = {0xFCF82518U, 0x0000004EU}, /* RGIDW_MODID[236]:IPMMUHC13*/ + [225] = {0xFCF8251CU, 0x0000000CU}, /* RGIDW_MODID[237]:PPHY0*/ + [226] = {0xFCF82520U, 0x0000000CU}, /* RGIDW_MODID[238]:PPHY1*/ + [227] = {0xFCF82524U, 0x0000004EU}, /* RGIDW_MODID[239]:IPMMUHC14*/ + [228] = {0xFCF82528U, 0x0000004EU}, /* RGIDW_MODID[240]:IPMMUHC15*/ + [229] = {0xFCF8252CU, 0x0000000EU}, /* RGIDW_MODID[241]:FBAHSC*/ + [230] = {0xFCF82530U, 0x0000004EU}, /* RGIDW_MODID[242]:IPMMUHC02*/ + [231] = {0xFCF82538U, 0x0000000AU}, /* RGIDW_MODID[243]:ECMHSC*/ + [232] = {0xFCF8253CU, 0x00000002U}, /* RGIDW_MODID[244]:ARHC0*/ + /* After setting */ /* RGIDW_MODID[245]:ARHC1*/ + /* After setting */ /* RGIDW_MODID[246]:ARHC2*/ + [233] = {0xFCF82548U, 0x00000001U}, /* RGIDW_MODID[247]:ARHC3*/ + [234] = {0xFCF8254CU, 0x00000002U}, /* RGIDW_MODID[248]:ARHC4*/ + [235] = {0xFCF82550U, 0x00000001U}, /* RGIDW_MODID[249]:ARHC5*/ + [236] = {0xFCF82554U, 0x00000002U}, /* RGIDW_MODID[250]:ARHC6*/ + [237] = {0xFCF82558U, 0x00000002U}, /* RGIDW_MODID[251]:ARHC7*/ + [238] = {0xFCF8255CU, 0x00000000U}, /* RGIDW_MODID[252]:ARHC8*/ + [239] = {0xFCF82560U, 0x0000004EU}, /* RGIDW_MODID[253]:IPMMUHC03*/ + [240] = {0xFCF82564U, 0x0000004EU}, /* RGIDW_MODID[254]:IPMMUHC04*/ + [241] = {0xFCF82568U, 0x0000004EU}, /* RGIDW_MODID[255]:IPMMUHC05*/ + [242] = {0xFCF8256CU, 0x0000004EU}, /* RGIDW_MODID[256]:IPMMUHC06*/ + [243] = {0xFCF82570U, 0x0000004EU}, /* RGIDW_MODID[257]:IPMMUHC07*/ + [244] = {0xFCF82574U, 0x0000004EU}, /* RGIDW_MODID[258]:IPMMUHC08*/ + [245] = {0xFCF82578U, 0x0000004EU}, /* RGIDW_MODID[259]:IPMMUHC09*/ + [246] = {0xFC882400U, 0x00000002U}, /* RGIDW_MODID[260]:ARIMP00*/ + /* After setting */ /* RGIDW_MODID[261]:ARIMP01*/ + /* After setting */ /* RGIDW_MODID[262]:ARIMP02*/ + [247] = {0xFC88240CU, 0x00000001U}, /* RGIDW_MODID[263]:ARIMP03*/ + [248] = {0xFC882410U, 0x00000002U}, /* RGIDW_MODID[264]:ARIMP04*/ + [249] = {0xFC882414U, 0x0000004EU}, /* RGIDW_MODID[265]:AXIFBABUSIR0*/ + [250] = {0xFC882418U, 0x0000004EU}, /* RGIDW_MODID[266]:AXIFBABUSIR1*/ + [251] = {0xFC88241CU, 0x0000004EU}, /* RGIDW_MODID[267]:AXIFBABUSIR2*/ + [252] = {0xFC882420U, 0x0000004EU}, /* RGIDW_MODID[268]:AXIFBABUSIR3*/ + [253] = {0xFC882424U, 0x0000004EU}, /* RGIDW_MODID[269]:AXIFBABUSIR4*/ + [254] = {0xFC882428U, 0x0000004EU}, /* RGIDW_MODID[270]:AXIIMP0*/ + [255] = {0xFC88242CU, 0x0000004EU}, /* RGIDW_MODID[271]:CKMCNR*/ + [256] = {0xFC882430U, 0x0000004EU}, /* RGIDW_MODID[272]:CKMDSP*/ + [257] = {0xFC882434U, 0x00000001U}, /* RGIDW_MODID[273]:ARIMP05*/ + [258] = {0xFC882438U, 0x00000002U}, /* RGIDW_MODID[274]:ARIMP06*/ + [259] = {0xFC88243CU, 0x00000002U}, /* RGIDW_MODID[275]:ARIMP07*/ + [260] = {0xFC882440U, 0x00000000U}, /* RGIDW_MODID[276]:ARIMP08*/ + [261] = {0xFC882444U, 0x0000004EU}, /* RGIDW_MODID[277]:CKMIR*/ + [262] = {0xFC882448U, 0x0000000AU}, /* RGIDW_MODID[278]:ECMIR*/ + [263] = {0xFC88244CU, 0x0000000FU}, /* RGIDW_MODID[279]:DSPPS*/ + [264] = {0xFC882450U, 0x0000004EU}, /* RGIDW_MODID[280]:IPMMUIR1*/ + [265] = {0xFC882454U, 0x0000004EU}, /* RGIDW_MODID[281]:IPMMUIR0*/ + [266] = {0xFC882458U, 0x0000004EU}, /* RGIDW_MODID[282]:IPMMUIR10*/ + [267] = {0xFC88245CU, 0x0000004EU}, /* RGIDW_MODID[283]:IPMMUIR11*/ + [268] = {0xFC882460U, 0x0000004EU}, /* RGIDW_MODID[284]:IPMMUIR12*/ + [269] = {0xFC882464U, 0x0000004EU}, /* RGIDW_MODID[285]:IPMMUIR13*/ + [270] = {0xFC882468U, 0x0000004EU}, /* RGIDW_MODID[286]:IPMMUIR14*/ + [271] = {0xFC88246CU, 0x0000004EU}, /* RGIDW_MODID[287]:IPMMUIR15*/ + [272] = {0xFC882470U, 0x0000004EU}, /* RGIDW_MODID[288]:IPMMUIR2*/ + [273] = {0xFC882474U, 0x0000004EU}, /* RGIDW_MODID[289]:IPMMUIR3*/ + [274] = {0xFC882478U, 0x0000004EU}, /* RGIDW_MODID[290]:IPMMUIR4*/ + [275] = {0xFC88247CU, 0x0000004EU}, /* RGIDW_MODID[291]:IPMMUIR5*/ + [276] = {0xFC882480U, 0x0000004EU}, /* RGIDW_MODID[292]:IPMMUIR6*/ + [277] = {0xFC882484U, 0x0000004EU}, /* RGIDW_MODID[293]:IPMMUIR7*/ + [278] = {0xFC882488U, 0x0000004EU}, /* RGIDW_MODID[294]:IPMMUIR8*/ + [279] = {0xFC88248CU, 0x0000004EU}, /* RGIDW_MODID[295]:IPMMUIR9*/ + [280] = {0xFC012400U, 0x00000002U}, /* RGIDW_MODID[296]:ARPV0*/ + /* After setting */ /* RGIDW_MODID[297]:ARPV1*/ + [281] = {0xFC012408U, 0x0000002CU}, /* RGIDW_MODID[298]:AXIRGXS*/ + /* After setting */ /* RGIDW_MODID[299]:ARPV2*/ + [282] = {0xFC012410U, 0x00000001U}, /* RGIDW_MODID[300]:ARPV3*/ + [283] = {0xFC012414U, 0x00000002U}, /* RGIDW_MODID[301]:ARPV4*/ + [284] = {0xFC012418U, 0x00000001U}, /* RGIDW_MODID[302]:ARPV5*/ + [285] = {0xFC01241CU, 0x00000002U}, /* RGIDW_MODID[303]:ARPV6*/ + [286] = {0xFC012420U, 0x00000002U}, /* RGIDW_MODID[304]:ARPV7*/ + [287] = {0xFC012424U, 0x00000000U}, /* RGIDW_MODID[305]:ARPV8*/ + [288] = {0xFC012428U, 0x0000000AU}, /* RGIDW_MODID[306]:CKM3DG*/ + [289] = {0xFC01242CU, 0x0000000AU}, /* RGIDW_MODID[307]:ECM3DG*/ + [290] = {0xFC012430U, 0x0000000EU}, /* RGIDW_MODID[308]:FBAPVC*/ + [291] = {0xFC012434U, 0x0000000EU}, /* RGIDW_MODID[309]:FBAPVD0*/ + [292] = {0xFC012438U, 0x0000000EU}, /* RGIDW_MODID[310]:FBAPVD1*/ + [293] = {0xFC01243CU, 0x0000000EU}, /* RGIDW_MODID[311]:FBAPVD2*/ + [294] = {0xFC012440U, 0x0000000EU}, /* RGIDW_MODID[312]:FBAPVE*/ + [295] = {0xFC012444U, 0x0000004EU}, /* RGIDW_MODID[313]:IPMMUPV000*/ + [296] = {0xFC012448U, 0x0000004EU}, /* RGIDW_MODID[314]:IPMMUPV001*/ + [297] = {0xFC01244CU, 0x0000004EU}, /* RGIDW_MODID[315]:IPMMUPV010*/ + [298] = {0xFC012450U, 0x0000004EU}, /* RGIDW_MODID[316]:IPMMUPV011*/ + [299] = {0xFC012454U, 0x0000004EU}, /* RGIDW_MODID[317]:IPMMUPV012*/ + [300] = {0xFC012458U, 0x0000004EU}, /* RGIDW_MODID[318]:IPMMUPV013*/ + [301] = {0xFC01245CU, 0x0000004EU}, /* RGIDW_MODID[319]:IPMMUPV014*/ + [302] = {0xFC012460U, 0x0000004EU}, /* RGIDW_MODID[320]:IPMMUPV015*/ + [303] = {0xFC012464U, 0x0000004EU}, /* RGIDW_MODID[321]:IPMMUPV002*/ + [304] = {0xFC012468U, 0x0000004EU}, /* RGIDW_MODID[322]:IPMMUPV003*/ + [305] = {0xFC01246CU, 0x0000004EU}, /* RGIDW_MODID[323]:IPMMUPV004*/ + [306] = {0xFC012470U, 0x0000004EU}, /* RGIDW_MODID[324]:IPMMUPV005*/ + [307] = {0xFC012474U, 0x0000004EU}, /* RGIDW_MODID[325]:IPMMUPV006*/ + [308] = {0xFC012478U, 0x0000004EU}, /* RGIDW_MODID[326]:IPMMUPV007*/ + [309] = {0xFC01247CU, 0x0000004EU}, /* RGIDW_MODID[327]:IPMMUPV008*/ + [310] = {0xFC012480U, 0x0000004EU}, /* RGIDW_MODID[328]:IPMMUPV009*/ + [311] = {0xFDC22400U, 0x00000002U}, /* RGIDW_MODID[329]:ARRC0*/ + /* After setting */ /* RGIDW_MODID[330]:ARRC1*/ + /* After setting */ /* RGIDW_MODID[331]:ARRC2*/ + [312] = {0xFDC2240CU, 0x00000001U}, /* RGIDW_MODID[332]:ARRC3*/ + [313] = {0xFDC22410U, 0x00000002U}, /* RGIDW_MODID[333]:ARRC4*/ + [314] = {0xFDC22414U, 0x00000001U}, /* RGIDW_MODID[334]:ARRC5*/ + [315] = {0xFDC22418U, 0x00000002U}, /* RGIDW_MODID[335]:ARRC6*/ + [316] = {0xFDC2241CU, 0x00000002U}, /* RGIDW_MODID[336]:ARRC7*/ + [317] = {0xFDC22420U, 0x00000000U}, /* RGIDW_MODID[337]:ARRC8*/ + [318] = {0xFDC22424U, 0x00000009U}, /* RGIDW_MODID[338]:CR0*/ + [319] = {0xFDC22428U, 0x0000004FU}, /* RGIDW_MODID[339]:ICUMX*/ + [320] = {0xFDC2242CU, 0x0000000AU}, /* RGIDW_MODID[340]:ECMRC*/ + [321] = {0xFD432400U, 0x0000004EU}, /* RGIDW_MODID[341]:DMAWCRC0*/ + [322] = {0xFD432404U, 0x0000004EU}, /* RGIDW_MODID[342]:DMAWCRC1*/ + [323] = {0xFD432408U, 0x0000004EU}, /* RGIDW_MODID[343]:DMAWCRC2*/ + [324] = {0xFD43240CU, 0x0000004EU}, /* RGIDW_MODID[344]:DMAWCRC3*/ + [325] = {0xFD442400U, 0x0000000FU}, /* RGIDW_MODID[345]:ARMREG00*/ + [326] = {0xFD442404U, 0x0000000CU}, /* RGIDW_MODID[346]:ARMREG01*/ + [327] = {0xFD442408U, 0x00000000U}, /* RGIDW_MODID[347]:ARMREG10*/ + [328] = {0xFD44240CU, 0x00000000U}, /* RGIDW_MODID[348]:ARMREG11*/ + [329] = {0xFD442410U, 0x0000000AU}, /* RGIDW_MODID[349]:ARMREG12*/ + [330] = {0xFD442414U, 0x0000000FU}, /* RGIDW_MODID[350]:ARMREG13*/ + [331] = {0xFD442418U, 0x0000000AU}, /* RGIDW_MODID[351]:ARMREG14*/ + [332] = {0xFD44241CU, 0x00000003U}, /* RGIDW_MODID[352]:AXICR52SS0*/ + [333] = {0xFD442420U, 0x0000000EU}, /* RGIDW_MODID[353]:AXICSD0*/ + [334] = {0xFD442424U, 0x0000000EU}, /* RGIDW_MODID[354]:AXIINTAP0*/ + [335] = {0xFD442428U, 0x00000000U}, /* RGIDW_MODID[355]:AXIINTAP1*/ + [336] = {0xFD442430U, 0x0000000FU}, /* RGIDW_MODID[356]:AXISYSRAM0*/ + [337] = {0xFD442434U, 0x0000004FU}, /* RGIDW_MODID[357]:AXISYSRAM1*/ + [338] = {0xFD442438U, 0x00000000U}, /* RGIDW_MODID[358]:ARGREG15*/ + [339] = {0xFD44243CU, 0x00000000U}, /* RGIDW_MODID[359]:ARMREG2*/ + [340] = {0xFD442440U, 0x00000000U}, /* RGIDW_MODID[360]:ARMREG3*/ + [341] = {0xFD442444U, 0x00000000U}, /* RGIDW_MODID[361]:ARMREG4*/ + [342] = {0xFD442448U, 0x0000000FU}, /* RGIDW_MODID[362]:ARMREG5*/ + [343] = {0xFD44244CU, 0x0000000AU}, /* RGIDW_MODID[363]:ARMREG6*/ + [344] = {0xFD442450U, 0x00000000U}, /* RGIDW_MODID[364]:ARMREG7*/ + [345] = {0xFD442454U, 0x0000000CU}, /* RGIDW_MODID[365]:ARMREG8*/ + [346] = {0xFD442458U, 0x0000000CU}, /* RGIDW_MODID[366]:ARMREG9*/ + [347] = {0xFD44245CU, 0x00000002U}, /* RGIDW_MODID[367]:ARRD0*/ + /* After setting */ /* RGIDW_MODID[368]:ARRD1*/ + /* After setting */ /* RGIDW_MODID[369]:ARRD2*/ + [348] = {0xFD442468U, 0x00000001U}, /* RGIDW_MODID[370]:ARRD3*/ + [349] = {0xFD44246CU, 0x00000002U}, /* RGIDW_MODID[371]:ARRD4*/ + [350] = {0xFD442470U, 0x00000001U}, /* RGIDW_MODID[372]:ARRD5*/ + [351] = {0xFD442474U, 0x00000002U}, /* RGIDW_MODID[373]:ARRD6*/ + [352] = {0xFD442478U, 0x00000002U}, /* RGIDW_MODID[374]:ARRD7*/ + [353] = {0xFD44247CU, 0x00000000U}, /* RGIDW_MODID[375]:ARRD8*/ + [354] = {0xFD442480U, 0x00000002U}, /* RGIDW_MODID[376]:ARRT0*/ + /* After setting */ /* RGIDW_MODID[377]:ARRT1*/ + /* After setting */ /* RGIDW_MODID[378]:ARRT2*/ + [355] = {0xFD44248CU, 0x00000001U}, /* RGIDW_MODID[379]:ARRT3*/ + [356] = {0xFD442490U, 0x00000002U}, /* RGIDW_MODID[380]:ARRT4*/ + [357] = {0xFD442494U, 0x00000001U}, /* RGIDW_MODID[381]:ARRT5*/ + [358] = {0xFD442498U, 0x00000002U}, /* RGIDW_MODID[382]:ARRT6*/ + [359] = {0xFD44249CU, 0x00000002U}, /* RGIDW_MODID[383]:ARRT7*/ + [360] = {0xFD4424A0U, 0x00000000U}, /* RGIDW_MODID[384]:ARRT8*/ + [361] = {0xFD4424A4U, 0x0000000AU}, /* RGIDW_MODID[385]:CKMRT*/ + [362] = {0xFD4424A8U, 0x0000004EU}, /* RGIDW_MODID[386]:CRC0*/ + [363] = {0xFD4424ACU, 0x0000004EU}, /* RGIDW_MODID[387]:CRC1*/ + [364] = {0xFD4424B0U, 0x0000004EU}, /* RGIDW_MODID[388]:CRC2*/ + [365] = {0xFD4424B4U, 0x0000004EU}, /* RGIDW_MODID[389]:CRC3*/ + [366] = {0xFD4424B8U, 0x0000000EU}, /* RGIDW_MODID[390]:CSD*/ + [367] = {0xFD4424BCU, 0x0000000EU}, /* RGIDW_MODID[391]:ECM*/ + [368] = {0xFD4424C0U, 0x0000000AU}, /* RGIDW_MODID[392]:ECMRT*/ + [369] = {0xFD4424C4U, 0x0000000EU}, /* RGIDW_MODID[393]:FBACR52*/ + [370] = {0xFD4424C8U, 0x0000000EU}, /* RGIDW_MODID[394]:FBART*/ + [371] = {0xFD4424CCU, 0x0000000EU}, /* RGIDW_MODID[395]:INTTP*/ + [372] = {0xFD4424D0U, 0x0000004EU}, /* RGIDW_MODID[396]:IPMMURT000*/ + [373] = {0xFD4424D4U, 0x0000004EU}, /* RGIDW_MODID[397]:IPMMURT100*/ + [374] = {0xFD4424D8U, 0x0000004EU}, /* RGIDW_MODID[398]:KCRC4*/ + [375] = {0xFD4424DCU, 0x0000004EU}, /* RGIDW_MODID[399]:KCRC5*/ + [376] = {0xFD4424E0U, 0x0000004EU}, /* RGIDW_MODID[400]:KCRC6*/ + [377] = {0xFD4424E4U, 0x0000004EU}, /* RGIDW_MODID[401]:KCRC7*/ + [378] = {0xFD4424E8U, 0x0000004FU}, /* RGIDW_MODID[402]:MFI00*/ + [379] = {0xFD4424ECU, 0x0000004EU}, /* RGIDW_MODID[403]:MFI01*/ + [380] = {0xFD4424F0U, 0x0000004EU}, /* RGIDW_MODID[404]:MFI10*/ + [381] = {0xFD4424F4U, 0x0000004EU}, /* RGIDW_MODID[405]:MFI02*/ + [382] = {0xFD4424F8U, 0x0000004EU}, /* RGIDW_MODID[406]:MFI03*/ + [383] = {0xFD4424FCU, 0x0000004EU}, /* RGIDW_MODID[407]:MFI04*/ + [384] = {0xFD442500U, 0x00000000U}, /* RGIDW_MODID[408]:MFI05*/ + [385] = {0xFD442504U, 0x00000000U}, /* RGIDW_MODID[409]:MFI06*/ + [386] = {0xFD442508U, 0x00000000U}, /* RGIDW_MODID[410]:MFI07*/ + [387] = {0xFD44250CU, 0x00000000U}, /* RGIDW_MODID[411]:MFI08*/ + [388] = {0xFD442510U, 0x0000004EU}, /* RGIDW_MODID[412]:MFI09*/ + [389] = {0xFD442514U, 0x0000004FU}, /* RGIDW_MODID[413]:MFI15*/ + [390] = {0xFD442518U, 0x0000000AU}, /* RGIDW_MODID[414]:CKMCR52*/ + [391] = {0xFD44251CU, 0x0000004BU}, /* RGIDW_MODID[415]:RTDM0P*/ + [392] = {0xFD442520U, 0x0000000AU}, /* RGIDW_MODID[416]:ECMRD*/ + [393] = {0xFD442524U, 0x0000004BU}, /* RGIDW_MODID[417]:RTDM1P*/ + [394] = {0xFD44252CU, 0x0000004BU}, /* RGIDW_MODID[418]:RTDM2P*/ + [395] = {0xFD442530U, 0x0000000BU}, /* RGIDW_MODID[419]:SYSRAM10*/ + [396] = {0xFD442534U, 0x0000004BU}, /* RGIDW_MODID[420]:RTDM3P*/ + [397] = {0xFD442538U, 0x00000001U}, /* RGIDW_MODID[421]:SYSRAM00*/ + [398] = {0xFD44253CU, 0x0000004EU}, /* RGIDW_MODID[422]:TSIPL0*/ + [399] = {0xFD442540U, 0x0000004EU}, /* RGIDW_MODID[423]:TSIPL1*/ + [400] = {0xFD442544U, 0x0000004EU}, /* RGIDW_MODID[424]:TSIPL2*/ + [401] = {0xFD442548U, 0x0000004EU}, /* RGIDW_MODID[425]:TSIPL3*/ + [402] = {0xFD44254CU, 0x0000004EU}, /* RGIDW_MODID[426]:TSIPL4*/ + [403] = {0xFD442550U, 0x0000004EU}, /* RGIDW_MODID[427]:TSIPL5*/ + [404] = {0xFD442554U, 0x0000004EU}, /* RGIDW_MODID[428]:TSIPL6*/ + [405] = {0xFD442558U, 0x0000004EU}, /* RGIDW_MODID[429]:TSIPL7*/ + [406] = {0xFD44255CU, 0x0000004EU}, /* RGIDW_MODID[430]:WCRC0*/ + [407] = {0xFD442560U, 0x0000004EU}, /* RGIDW_MODID[431]:WCRC1*/ + [408] = {0xFD442564U, 0x0000004EU}, /* RGIDW_MODID[432]:WCRC2*/ + [409] = {0xFD442568U, 0x0000004EU}, /* RGIDW_MODID[433]:WCRC3*/ + [410] = {0xFD442580U, 0x0000004EU}, /* RGIDW_MODID[434]:MFI11*/ + [411] = {0xFD442584U, 0x00000000U}, /* RGIDW_MODID[435]:MFI12*/ + [412] = {0xFD442588U, 0x00000000U}, /* RGIDW_MODID[436]:MFI13*/ + [413] = {0xFD44258CU, 0x00000000U}, /* RGIDW_MODID[437]:MFI14*/ + [414] = {0xFD442590U, 0x0000004EU}, /* RGIDW_MODID[438]:IPMMURT001*/ + [415] = {0xFD442594U, 0x0000004EU}, /* RGIDW_MODID[439]:IPMMURT010*/ + [416] = {0xFD442598U, 0x0000004EU}, /* RGIDW_MODID[440]:IPMMURT011*/ + [417] = {0xFD44259CU, 0x0000004EU}, /* RGIDW_MODID[441]:IPMMURT012*/ + [418] = {0xFD4425A0U, 0x0000004EU}, /* RGIDW_MODID[442]:IPMMURT013*/ + [419] = {0xFD4425A4U, 0x0000004EU}, /* RGIDW_MODID[443]:IPMMURT014*/ + [420] = {0xFD4425A8U, 0x0000004EU}, /* RGIDW_MODID[444]:IPMMURT015*/ + [421] = {0xFD4425ACU, 0x0000004EU}, /* RGIDW_MODID[445]:IPMMURT002*/ + [422] = {0xFD4425B0U, 0x0000004EU}, /* RGIDW_MODID[446]:IPMMURT003*/ + [423] = {0xFD4425B4U, 0x0000004EU}, /* RGIDW_MODID[447]:IPMMURT004*/ + [424] = {0xFD4425B8U, 0x0000004EU}, /* RGIDW_MODID[448]:IPMMURT005*/ + [425] = {0xFD4425BCU, 0x0000004EU}, /* RGIDW_MODID[449]:IPMMURT006*/ + [426] = {0xFD4425C0U, 0x0000004EU}, /* RGIDW_MODID[450]:IPMMURT007*/ + [427] = {0xFD4425C4U, 0x0000004EU}, /* RGIDW_MODID[451]:IPMMURT008*/ + [428] = {0xFD4425C8U, 0x0000004EU}, /* RGIDW_MODID[452]:IPMMURT009*/ + [429] = {0xFD4425CCU, 0x0000004EU}, /* RGIDW_MODID[453]:IPKMURT101*/ + [430] = {0xFD4425D0U, 0x0000004EU}, /* RGIDW_MODID[454]:IPMMURT110*/ + [431] = {0xFD4425D4U, 0x0000004EU}, /* RGIDW_MODID[455]:IPMMURT111*/ + [432] = {0xFD4425D8U, 0x0000004EU}, /* RGIDW_MODID[456]:IPMMURT112*/ + [433] = {0xFD4425DCU, 0x0000004EU}, /* RGIDW_MODID[457]:IPMMURT113*/ + [434] = {0xFD4425E0U, 0x0000004EU}, /* RGIDW_MODID[458]:IPMMURT114*/ + [435] = {0xFD4425E4U, 0x0000004EU}, /* RGIDW_MODID[459]:IPMMURT115*/ + [436] = {0xFD4425E8U, 0x0000004EU}, /* RGIDW_MODID[460]:IPMMURT102*/ + [437] = {0xFD4425ECU, 0x0000004EU}, /* RGIDW_MODID[461]:IPMMURT103*/ + [438] = {0xFD4425F0U, 0x0000004EU}, /* RGIDW_MODID[462]:IPMMURT104*/ + [439] = {0xFD4425F4U, 0x0000004EU}, /* RGIDW_MODID[463]:IPMMURT105*/ + [440] = {0xFD4425F8U, 0x0000004EU}, /* RGIDW_MODID[464]:IPMMURT106*/ + [441] = {0xFD4425FCU, 0x0000004EU}, /* RGIDW_MODID[465]:IPMMURT107*/ + [442] = {0xFD442600U, 0x0000004BU}, /* RGIDW_MODID[466]:RTDM000*/ + [443] = {0xFD442604U, 0x0000004BU}, /* RGIDW_MODID[467]:RTDM001*/ + [444] = {0xFD442608U, 0x0000004BU}, /* RGIDW_MODID[468]:RTDM010*/ + [445] = {0xFD44260CU, 0x0000004BU}, /* RGIDW_MODID[469]:RTDM011*/ + [446] = {0xFD442610U, 0x0000004BU}, /* RGIDW_MODID[470]:RTDM012*/ + [447] = {0xFD442614U, 0x0000004BU}, /* RGIDW_MODID[471]:RTDM013*/ + [448] = {0xFD442618U, 0x0000004BU}, /* RGIDW_MODID[472]:RTDM014*/ + [449] = {0xFD44261CU, 0x0000004BU}, /* RGIDW_MODID[473]:RTDM015*/ + [450] = {0xFD442620U, 0x0000004BU}, /* RGIDW_MODID[474]:RTDM002*/ + [451] = {0xFD442624U, 0x0000004BU}, /* RGIDW_MODID[475]:RTDM003*/ + [452] = {0xFD442628U, 0x0000004BU}, /* RGIDW_MODID[476]:RTDM004*/ + [453] = {0xFD44262CU, 0x0000004BU}, /* RGIDW_MODID[477]:RTDM005*/ + [454] = {0xFD442630U, 0x0000004BU}, /* RGIDW_MODID[478]:RTDM006*/ + [455] = {0xFD442634U, 0x0000004BU}, /* RGIDW_MODID[479]:RTDM007*/ + [456] = {0xFD442638U, 0x0000004BU}, /* RGIDW_MODID[480]:RTDM008*/ + [457] = {0xFD44263CU, 0x0000004BU}, /* RGIDW_MODID[481]:RTDM009*/ + [458] = {0xFD442640U, 0x0000004BU}, /* RGIDW_MODID[482]:RTDM100*/ + [459] = {0xFD442644U, 0x0000004BU}, /* RGIDW_MODID[483]:RTDM101*/ + [460] = {0xFD442648U, 0x0000004BU}, /* RGIDW_MODID[484]:RTDM110*/ + [461] = {0xFD44264CU, 0x0000004BU}, /* RGIDW_MODID[485]:RTDM111*/ + [462] = {0xFD442650U, 0x0000004BU}, /* RGIDW_MODID[486]:RTDM112*/ + [463] = {0xFD442654U, 0x0000004BU}, /* RGIDW_MODID[487]:RTDM113*/ + [464] = {0xFD442658U, 0x0000004BU}, /* RGIDW_MODID[488]:RTDM114*/ + [465] = {0xFD44265CU, 0x0000004BU}, /* RGIDW_MODID[489]:RTDM115*/ + [466] = {0xFD442660U, 0x0000004BU}, /* RGIDW_MODID[490]:RTDM102*/ + [467] = {0xFD442664U, 0x0000004BU}, /* RGIDW_MODID[491]:RTDM103*/ + [468] = {0xFD442668U, 0x0000004BU}, /* RGIDW_MODID[492]:RTDM104*/ + [469] = {0xFD44266CU, 0x0000004BU}, /* RGIDW_MODID[493]:RTDM105*/ + [470] = {0xFD442670U, 0x0000004BU}, /* RGIDW_MODID[494]:RTDM106*/ + [471] = {0xFD442674U, 0x0000004BU}, /* RGIDW_MODID[495]:RTDM107*/ + [472] = {0xFD442678U, 0x0000004BU}, /* RGIDW_MODID[496]:RTDM108*/ + [473] = {0xFD44267CU, 0x0000004BU}, /* RGIDW_MODID[497]:RTDM109*/ + [474] = {0xFD442680U, 0x0000004BU}, /* RGIDW_MODID[498]:RTDM200*/ + [475] = {0xFD442684U, 0x0000004BU}, /* RGIDW_MODID[499]:RTDM201*/ + [476] = {0xFD442688U, 0x0000004BU}, /* RGIDW_MODID[500]:RTDM210*/ + [477] = {0xFD44268CU, 0x0000004BU}, /* RGIDW_MODID[501]:RTDM211*/ + [478] = {0xFD442690U, 0x0000004BU}, /* RGIDW_MODID[502]:RTDM212*/ + [479] = {0xFD442694U, 0x0000004BU}, /* RGIDW_MODID[503]:RTDM213*/ + [480] = {0xFD442698U, 0x0000004BU}, /* RGIDW_MODID[504]:RTDM214*/ + [481] = {0xFD44269CU, 0x0000004BU}, /* RGIDW_MODID[505]:RTDM215*/ + [482] = {0xFD4426A0U, 0x0000004BU}, /* RGIDW_MODID[506]:RTDM202*/ + [483] = {0xFD4426A4U, 0x0000004BU}, /* RGIDW_MODID[507]:RTDM203*/ + [484] = {0xFD4426A8U, 0x0000004BU}, /* RGIDW_MODID[508]:RTDM204*/ + [485] = {0xFD4426ACU, 0x0000004BU}, /* RGIDW_MODID[509]:RTDM205*/ + [486] = {0xFD4426B0U, 0x0000004BU}, /* RGIDW_MODID[510]:RTDM206*/ + [487] = {0xFD4426B4U, 0x0000004BU}, /* RGIDW_MODID[511]:RTDM207*/ + [488] = {0xFD4426B8U, 0x0000004BU}, /* RGIDW_MODID[512]:RTDM208*/ + [489] = {0xFD4426BCU, 0x0000004BU}, /* RGIDW_MODID[513]:RTDM209*/ + [490] = {0xFD4426C0U, 0x0000004BU}, /* RGIDW_MODID[514]:RTDM300*/ + [491] = {0xFD4426C4U, 0x0000004BU}, /* RGIDW_MODID[515]:RTDM301*/ + [492] = {0xFD4426C8U, 0x0000004BU}, /* RGIDW_MODID[516]:RTDM310*/ + [493] = {0xFD4426CCU, 0x0000004BU}, /* RGIDW_MODID[517]:RTDM311*/ + [494] = {0xFD4426D0U, 0x0000004BU}, /* RGIDW_MODID[518]:RTDM312*/ + [495] = {0xFD4426D4U, 0x0000004BU}, /* RGIDW_MODID[519]:RTDM313*/ + [496] = {0xFD4426D8U, 0x0000004BU}, /* RGIDW_MODID[520]:RTDM314*/ + [497] = {0xFD4426DCU, 0x0000004BU}, /* RGIDW_MODID[521]:RTDM315*/ + [498] = {0xFD4426E0U, 0x0000004BU}, /* RGIDW_MODID[522]:RTDM302*/ + [499] = {0xFD4426E4U, 0x0000004BU}, /* RGIDW_MODID[523]:RTDM303*/ + [500] = {0xFD4426E8U, 0x0000004BU}, /* RGIDW_MODID[524]:RTDM304*/ + [501] = {0xFD4426ECU, 0x0000004BU}, /* RGIDW_MODID[525]:RTDM305*/ + [502] = {0xFD4426F0U, 0x0000004BU}, /* RGIDW_MODID[526]:RTDM306*/ + [503] = {0xFD4426F4U, 0x0000004BU}, /* RGIDW_MODID[527]:RTDM307*/ + [504] = {0xFD4426F8U, 0x0000004BU}, /* RGIDW_MODID[528]:RTDM308*/ + [505] = {0xFD4426FCU, 0x0000004BU}, /* RGIDW_MODID[529]:RTDM309*/ + [506] = {0xFD442700U, 0x0000004EU}, /* RGIDW_MODID[530]:IPMMURT108*/ + [507] = {0xFD442704U, 0x0000004EU}, /* RGIDW_MODID[531]:IPMMURT109*/ + [508] = {0xFD442708U, 0x00000001U}, /* RGIDW_MODID[532]:SYSRAM01*/ + [509] = {0xFD44270CU, 0x0000000BU}, /* RGIDW_MODID[533]:SYSRAM02*/ + [510] = {0xFD442710U, 0x00000001U}, /* RGIDW_MODID[534]:SYSRAM03*/ + [511] = {0xFD442714U, 0x00000001U}, /* RGIDW_MODID[535]:SYSRAM04*/ + [512] = {0xFD442718U, 0x00000001U}, /* RGIDW_MODID[536]:SYSRAM05*/ + [513] = {0xFD44271CU, 0x00000001U}, /* RGIDW_MODID[537]:SYSRAM06*/ + [514] = {0xFD442720U, 0x00000000U}, /* RGIDW_MODID[538]:SYSRAM07*/ + [515] = {0xFD442724U, 0x0000000BU}, /* RGIDW_MODID[539]:SYSRAM11*/ + [516] = {0xFD442728U, 0x0000000AU}, /* RGIDW_MODID[540]:SYSRAM12*/ + [517] = {0xFD44272CU, 0x0000000BU}, /* RGIDW_MODID[541]:SYSRAM13*/ + [518] = {0xFD442730U, 0x0000000BU}, /* RGIDW_MODID[542]:SYSRAM14*/ + [519] = {0xFD442734U, 0x0000000BU}, /* RGIDW_MODID[543]:SYSRAM15*/ + [520] = {0xFD442738U, 0x0000000BU}, /* RGIDW_MODID[544]:SYSRAM16*/ + [521] = {0xFD44273CU, 0x00000000U}, /* RGIDW_MODID[545]:SYSRAM17*/ + [522] = {0xFD442760U, 0x00000002U}, /* RGIDW_MODID[546]:BKBUF*/ + [523] = {0xFD442764U, 0x00000003U}, /* RGIDW_MODID[547]:AXICR52SS1*/ + [524] = {0xFD442768U, 0x00000003U}, /* RGIDW_MODID[548]:AXICR52SS2*/ + [525] = {0xFC862400U, 0x00000002U}, /* RGIDW_MODID[549]:ARSC0*/ + /* After setting */ /* RGIDW_MODID[550]:ARSC1*/ + /* After setting */ /* RGIDW_MODID[551]:ARSC2*/ + [526] = {0xFC86240CU, 0x00000001U}, /* RGIDW_MODID[552]:ARSC3*/ + [527] = {0xFC862410U, 0x00000002U}, /* RGIDW_MODID[553]:ARSC4*/ + [528] = {0xFC862414U, 0x00000001U}, /* RGIDW_MODID[554]:ARSC5*/ + [529] = {0xFC862418U, 0x00000002U}, /* RGIDW_MODID[555]:ARSC6*/ + [530] = {0xFC86241CU, 0x00000002U}, /* RGIDW_MODID[556]:ARSC7*/ + [531] = {0xFC862420U, 0x00000000U}, /* RGIDW_MODID[557]:ARSC8*/ + [532] = {0xFC862424U, 0x00000002U}, /* RGIDW_MODID[558]:ARSTM0*/ + /* After setting */ /* RGIDW_MODID[559]:ARSTM1*/ + [533] = {0xFC86242CU, 0x0000000EU}, /* RGIDW_MODID[560]:CSD1S*/ + [534] = {0xFC862430U, 0x0000000EU}, /* RGIDW_MODID[561]:AXIFBABUSTOP0*/ + [535] = {0xFC862434U, 0x0000000EU}, /* RGIDW_MODID[562]:AXIFBABUSTOP1*/ + /* After setting */ /* RGIDW_MODID[563]:ARSTM2*/ + [536] = {0xFC86243CU, 0x00000001U}, /* RGIDW_MODID[564]:ARSTM3*/ + [537] = {0xFC862440U, 0x00000002U}, /* RGIDW_MODID[565]:ARSTM4*/ + [538] = {0xFC862444U, 0x00000001U}, /* RGIDW_MODID[566]:ARSTM5*/ + [539] = {0xFC862448U, 0x00000002U}, /* RGIDW_MODID[567]:ARSTM6*/ + [540] = {0xFC86244CU, 0x00000002U}, /* RGIDW_MODID[568]:ARSTM7*/ + [541] = {0xFC862450U, 0x00000000U}, /* RGIDW_MODID[569]:ARSTM8*/ + [542] = {0xFC862454U, 0x0000000AU}, /* RGIDW_MODID[570]:ECMTOP*/ + [543] = {0xFC862458U, 0x0000000EU}, /* RGIDW_MODID[571]:FBA*/ + [544] = {0xFC86245CU, 0x0000000EU}, /* RGIDW_MODID[572]:FBC*/ + [545] = {0xFC862460U, 0x0000000CU}, /* RGIDW_MODID[573]:AXICCI00*/ + [546] = {0xFC862464U, 0x0000000EU}, /* RGIDW_MODID[574]:AXICCI01*/ + [547] = {0xFC862468U, 0x0000000CU}, /* RGIDW_MODID[575]:AXICCI10*/ + [548] = {0xFC86246CU, 0x0000000CU}, /* RGIDW_MODID[576]:AXICCI11*/ + [549] = {0xFC862470U, 0x0000000CU}, /* RGIDW_MODID[577]:AXICCI12*/ + [550] = {0xFC862474U, 0x0000000CU}, /* RGIDW_MODID[578]:AXICCI13*/ + [551] = {0xFC862478U, 0x0000000CU}, /* RGIDW_MODID[579]:AXICCI14*/ + [552] = {0xFC86247CU, 0x0000000CU}, /* RGIDW_MODID[580]:AXICCI15*/ + [553] = {0xFC862480U, 0x0000000EU}, /* RGIDW_MODID[581]:AXICCI2*/ + [554] = {0xFC862484U, 0x0000000CU}, /* RGIDW_MODID[582]:AXICCI3*/ + [555] = {0xFC862488U, 0x0000000CU}, /* RGIDW_MODID[583]:AXICCI4*/ + [556] = {0xFC86248CU, 0x0000000CU}, /* RGIDW_MODID[584]:AXICCI5*/ + [557] = {0xFC862490U, 0x0000000CU}, /* RGIDW_MODID[585]:AXICCI6*/ + [558] = {0xFC862494U, 0x0000000CU}, /* RGIDW_MODID[586]:AXICCI7*/ + [559] = {0xFC862498U, 0x0000000CU}, /* RGIDW_MODID[587]:AXICCI8*/ + [560] = {0xFC86249CU, 0x00000009U}, /* RGIDW_MODID[588]:AXICCI9*/ + [561] = {0xFC8624A0U, 0x0000000AU}, /* RGIDW_MODID[589]:ECMSTM*/ + [562] = {0xFCB82400U, 0x0000002CU}, /* RGIDW_MODID[590]:DMASSI00*/ + [563] = {0xFCB82404U, 0x0000002CU}, /* RGIDW_MODID[591]:DMASSI01*/ + [564] = {0xFCB82408U, 0x0000002CU}, /* RGIDW_MODID[592]:DMASSI02*/ + [565] = {0xFCB8240CU, 0x0000002CU}, /* RGIDW_MODID[593]:DMASSI03*/ + [566] = {0xFCB82410U, 0x0000002CU}, /* RGIDW_MODID[594]:DMASSI04*/ + [567] = {0xFCB82414U, 0x0000004EU}, /* RGIDW_MODID[595]:DMAI2C0*/ + [568] = {0xFCB82418U, 0x0000004EU}, /* RGIDW_MODID[596]:DMAI2C1*/ + [569] = {0xFCB8241CU, 0x0000004EU}, /* RGIDW_MODID[597]:DMAI2C2*/ + [570] = {0xFCB82420U, 0x0000004EU}, /* RGIDW_MODID[598]:DMAI2C3*/ + [571] = {0xFCB82424U, 0x0000004EU}, /* RGIDW_MODID[599]:DMAI2C4*/ + [572] = {0xFCB82428U, 0x0000004EU}, /* RGIDW_MODID[600]:DMAI2C5*/ + [573] = {0xFCB8242CU, 0x0000002CU}, /* RGIDW_MODID[601]:DMASSI05*/ + [574] = {0xFCB82430U, 0x0000002CU}, /* RGIDW_MODID[602]:DMASSI06*/ + [575] = {0xFCB82434U, 0x0000002CU}, /* RGIDW_MODID[603]:DMASSI07*/ + [576] = {0xFDDC2400U, 0x00000002U}, /* RGIDW_MODID[604]:ARMM*/ + /* After setting */ /* RGIDW_MODID[605]:AXIARNMM*/ + [577] = {0xFDDC2408U, 0x00000002U}, /* RGIDW_MODID[606]:ARSM0*/ + /* After setting */ /* RGIDW_MODID[607]:ARSM1*/ + /* After setting */ /* RGIDW_MODID[608]:ARSM2*/ + [578] = {0xFDDC2414U, 0x0000000FU}, /* RGIDW_MODID[609]:AXIQOS0*/ + [579] = {0xFDDC2418U, 0x0000000FU}, /* RGIDW_MODID[610]:AXIQOS1*/ + [580] = {0xFDDC241CU, 0x0000000FU}, /* RGIDW_MODID[611]:AXIQOS2*/ + [581] = {0xFDDC2420U, 0x0000000FU}, /* RGIDW_MODID[612]:AXIQOS3*/ + [582] = {0xFDDC2424U, 0x0000000FU}, /* RGIDW_MODID[613]:AXIQOS4*/ + [583] = {0xFDDC2428U, 0x0000000FU}, /* RGIDW_MODID[614]:AXIQOS5*/ + [584] = {0xFDDC242CU, 0x0000000FU}, /* RGIDW_MODID[615]:AXIQOS6*/ + [585] = {0xFDDC2430U, 0x0000000FU}, /* RGIDW_MODID[616]:AXIQOS7*/ + [586] = {0xFDDC2434U, 0x00000001U}, /* RGIDW_MODID[617]:ARSM3*/ + [587] = {0xFDDC2438U, 0x00000002U}, /* RGIDW_MODID[618]:ARSM4*/ + [588] = {0xFDDC243CU, 0x00000001U}, /* RGIDW_MODID[619]:ARSM5*/ + [589] = {0xFDDC2440U, 0x00000002U}, /* RGIDW_MODID[620]:ARSM6*/ + [590] = {0xFDDC2444U, 0x00000002U}, /* RGIDW_MODID[621]:ARSM7*/ + [591] = {0xFDDC2448U, 0x00000000U}, /* RGIDW_MODID[622]:ARSM8*/ + [592] = {0xFDDC244CU, 0x0000000BU}, /* RGIDW_MODID[623]:AXMM0*/ + [593] = {0xFDDC2450U, 0x0000000BU}, /* RGIDW_MODID[624]:AXMM1*/ + [594] = {0xFDDC2454U, 0x00000000U}, /* RGIDW_MODID[625]:AXMMPMON*/ + [595] = {0xFDDC2458U, 0x0000000AU}, /* RGIDW_MODID[626]:CKMMM*/ + [596] = {0xFDDC245CU, 0x0000000AU}, /* RGIDW_MODID[627]:ECMMM*/ + [597] = {0xFDDC2460U, 0x0000000EU}, /* RGIDW_MODID[628]:FBADBSC0*/ + [598] = {0xFDDC2464U, 0x0000000EU}, /* RGIDW_MODID[629]:FBADBSC1*/ + [599] = {0xFDDC2468U, 0x0000000EU}, /* RGIDW_MODID[630]:FBAMM*/ + [600] = {0xFDDC246CU, 0x0000004EU}, /* RGIDW_MODID[631]:IPMMUMM00*/ + [601] = {0xFDDC2470U, 0x0000000FU}, /* RGIDW_MODID[632]:DBS0A0*/ + [602] = {0xFDDC2474U, 0x0000000AU}, /* RGIDW_MODID[633]:DBS0A1*/ + [603] = {0xFDDC2478U, 0x0000000FU}, /* RGIDW_MODID[634]:DBS1A0*/ + [604] = {0xFDDC247CU, 0x0000000AU}, /* RGIDW_MODID[635]:DBS1A1*/ + [605] = {0xFDDC2480U, 0x0000000FU}, /* RGIDW_MODID[636]:AXCIDBS*/ + [606] = {0xFDDC2484U, 0x00000009U}, /* RGIDW_MODID[637]:FCPRC*/ + [607] = {0xFDDC2488U, 0x0000000FU}, /* RGIDW_MODID[638]:DBS0D0*/ + [608] = {0xFDDC248CU, 0x0000000AU}, /* RGIDW_MODID[639]:DBS0D1*/ + [609] = {0xFDDC2490U, 0x0000000FU}, /* RGIDW_MODID[640]:DBS1D0*/ + [610] = {0xFDDC2494U, 0x0000000AU}, /* RGIDW_MODID[641]:DBS1D1*/ + [611] = {0xFDDC2498U, 0x0000000EU}, /* RGIDW_MODID[642]:FBADDR*/ + [612] = {0xFDDC249CU, 0x0000004EU}, /* RGIDW_MODID[643]:IPMMUMM01*/ + [613] = {0xFDDC24A0U, 0x0000004EU}, /* RGIDW_MODID[644]:IPMMUMM10*/ + [614] = {0xFDDC24A4U, 0x0000004EU}, /* RGIDW_MODID[645]:IPMMUMM11*/ + [615] = {0xFDDC24A8U, 0x0000004EU}, /* RGIDW_MODID[646]:IPMMUMM12*/ + [616] = {0xFDDC24ACU, 0x0000004EU}, /* RGIDW_MODID[647]:IPMMUMM13*/ + [617] = {0xFDDC24B0U, 0x0000004EU}, /* RGIDW_MODID[648]:IPMMUMM14*/ + [618] = {0xFDDC24B4U, 0x0000004EU}, /* RGIDW_MODID[649]:IPMMUMM15*/ + [619] = {0xFDDC24B8U, 0x0000004EU}, /* RGIDW_MODID[650]:IPMMUMM02*/ + [620] = {0xFDDC24BCU, 0x0000004EU}, /* RGIDW_MODID[651]:IPMMUMM03*/ + [621] = {0xFDDC24C0U, 0x0000004EU}, /* RGIDW_MODID[652]:IPMMUMM04*/ + [622] = {0xFDDC24C4U, 0x0000004EU}, /* RGIDW_MODID[653]:IPMMUMM05*/ + [623] = {0xFDDC24C8U, 0x0000004EU}, /* RGIDW_MODID[654]:IPMMUMM06*/ + [624] = {0xFDDC24CCU, 0x0000004EU}, /* RGIDW_MODID[655]:IPMMUMM07*/ + [625] = {0xFDDC24D0U, 0x0000004EU}, /* RGIDW_MODID[656]:IPMMUMM08*/ + [626] = {0xFDDC24D4U, 0x0000004EU}, /* RGIDW_MODID[657]:IPMMUMM09*/ + [627] = {0xFC802400U, 0x00000002U}, /* RGIDW_MODID[658]:ARSN0*/ + /* After setting */ /* RGIDW_MODID[659]:ARSN1*/ + /* After setting */ /* RGIDW_MODID[660]:ARSN2*/ + [628] = {0xFC80240CU, 0x00000001U}, /* RGIDW_MODID[661]:ARSN3*/ + [629] = {0xFC802410U, 0x00000002U}, /* RGIDW_MODID[662]:ARSN4*/ + [630] = {0xFC802414U, 0x00000001U}, /* RGIDW_MODID[663]:ARSN5*/ + [631] = {0xFC802418U, 0x00000002U}, /* RGIDW_MODID[664]:ARSN6*/ + [632] = {0xFC80241CU, 0x00000002U}, /* RGIDW_MODID[665]:ARSN7*/ + [633] = {0xFC802420U, 0x00000000U}, /* RGIDW_MODID[666]:ARSN8*/ + [634] = {0xFC802424U, 0x0000000AU}, /* RGIDW_MODID[667]:ECMTOP3*/ + [635] = {0xFCB52400U, 0x00000002U}, /* RGIDW_MODID[668]:ARSD00*/ + /* After setting */ /* RGIDW_MODID[669]:ARSD01*/ + /* After setting */ /* RGIDW_MODID[670]:ARSD02*/ + [636] = {0xFCB5240CU, 0x00000001U}, /* RGIDW_MODID[671]:ARSD03*/ + [637] = {0xFCB52410U, 0x00000002U}, /* RGIDW_MODID[672]:ARSD04*/ + [638] = {0xFCB52414U, 0x00000001U}, /* RGIDW_MODID[673]:ARSD05*/ + [639] = {0xFCB52418U, 0x00000002U}, /* RGIDW_MODID[674]:ARSD06*/ + [640] = {0xFCB5241CU, 0x0000004AU}, /* RGIDW_MODID[675]:AXIFRAY*/ + [641] = {0xFCB52420U, 0x0000000FU}, /* RGIDW_MODID[676]:AXIIPC*/ + [642] = {0xFCB52428U, 0x0000004FU}, /* RGIDW_MODID[677]:AXIRPC*/ + [643] = {0xFCB5242CU, 0x0000000FU}, /* RGIDW_MODID[678]:AXISDHI0*/ + [644] = {0xFCB52430U, 0x00000002U}, /* RGIDW_MODID[679]:ARSD07*/ + [645] = {0xFCB52434U, 0x00000000U}, /* RGIDW_MODID[680]:ARSD08*/ + [646] = {0xFCB52438U, 0x00000002U}, /* RGIDW_MODID[681]:ARSP00*/ + /* After setting */ /* RGIDW_MODID[682]:ARSP01*/ + /* After setting */ /* RGIDW_MODID[683]:ARSP02*/ + [647] = {0xFCB52444U, 0x00000001U}, /* RGIDW_MODID[684]:ARSP03*/ + [648] = {0xFCB52448U, 0x00000002U}, /* RGIDW_MODID[685]:ARSP04*/ + [649] = {0xFCB5244CU, 0x00000001U}, /* RGIDW_MODID[686]:ARSP05*/ + [650] = {0xFCB52450U, 0x00000002U}, /* RGIDW_MODID[687]:ARSP06*/ + [651] = {0xFCB52454U, 0x00000002U}, /* RGIDW_MODID[688]:ARSP07*/ + [652] = {0xFCB52458U, 0x00000000U}, /* RGIDW_MODID[689]:ARSP08*/ + [653] = {0xFCB5245CU, 0x0000004EU}, /* RGIDW_MODID[690]:IPMMUDS001*/ + [654] = {0xFCB52460U, 0x0000000AU}, /* RGIDW_MODID[691]:CKMPER0*/ + [655] = {0xFCB52464U, 0x0000000AU}, /* RGIDW_MODID[692]:ECMPER0*/ + [656] = {0xFCB52468U, 0x0000000EU}, /* RGIDW_MODID[693]:FBAPER0*/ + [657] = {0xFCB5246CU, 0x0000004EU}, /* RGIDW_MODID[694]:FSO0*/ + [658] = {0xFCB52470U, 0x0000004EU}, /* RGIDW_MODID[695]:FSO1*/ + [659] = {0xFCB52474U, 0x0000004EU}, /* RGIDW_MODID[696]:FSO10*/ + [660] = {0xFCB52478U, 0x0000004EU}, /* RGIDW_MODID[697]:FSO2*/ + [661] = {0xFCB5247CU, 0x0000004EU}, /* RGIDW_MODID[698]:FSO3*/ + [662] = {0xFCB52480U, 0x0000004EU}, /* RGIDW_MODID[699]:FSO4*/ + [663] = {0xFCB52484U, 0x0000004EU}, /* RGIDW_MODID[700]:FSO5*/ + [664] = {0xFCB52488U, 0x0000004EU}, /* RGIDW_MODID[701]:FSO6*/ + [665] = {0xFCB5248CU, 0x0000004EU}, /* RGIDW_MODID[702]:FSO7*/ + [666] = {0xFCB52490U, 0x0000004EU}, /* RGIDW_MODID[703]:FSO8*/ + [667] = {0xFCB52494U, 0x0000004EU}, /* RGIDW_MODID[704]:FSO9*/ + [668] = {0xFCB52498U, 0x0000002CU}, /* RGIDW_MODID[705]:ADG*/ + [669] = {0xFCB5249CU, 0x0000000AU}, /* RGIDW_MODID[706]:ECMSD0*/ + [670] = {0xFCB524A0U, 0x0000004EU}, /* RGIDW_MODID[707]:IPMMUDS010*/ + [671] = {0xFCB524A4U, 0x0000004EU}, /* RGIDW_MODID[708]:IPMMUDS011*/ + [672] = {0xFCB524A8U, 0x0000004EU}, /* RGIDW_MODID[709]:I2C0*/ + [673] = {0xFCB524ACU, 0x0000004EU}, /* RGIDW_MODID[710]:I2C1*/ + [674] = {0xFCB524B0U, 0x0000004EU}, /* RGIDW_MODID[711]:I2C2*/ + [675] = {0xFCB524B4U, 0x0000004EU}, /* RGIDW_MODID[712]:I2C3*/ + [676] = {0xFCB524B8U, 0x0000004EU}, /* RGIDW_MODID[713]:I2C4*/ + [677] = {0xFCB524BCU, 0x0000004EU}, /* RGIDW_MODID[714]:I2C5*/ + [678] = {0xFCB524C0U, 0x0000004EU}, /* RGIDW_MODID[715]:IPMMUDS012*/ + [679] = {0xFCB524C4U, 0x0000000FU}, /* RGIDW_MODID[716]:IPC*/ + [680] = {0xFCB524C8U, 0x0000004EU}, /* RGIDW_MODID[717]:IPMMUDS000*/ + [681] = {0xFCB524CCU, 0x0000004EU}, /* RGIDW_MODID[718]:IPMMUDS013*/ + [682] = {0xFCB524D0U, 0x0000004EU}, /* RGIDW_MODID[719]:IPMMUDS014*/ + [683] = {0xFCB524D4U, 0x0000004EU}, /* RGIDW_MODID[720]:IPMMUDS015*/ + [684] = {0xFCB524D8U, 0x0000004EU}, /* RGIDW_MODID[721]:IPMMUDS002*/ + [685] = {0xFCB524DCU, 0x0000004EU}, /* RGIDW_MODID[722]:IPMMUDS003*/ + [686] = {0xFCB524E0U, 0x0000004EU}, /* RGIDW_MODID[723]:IPMMUDS004*/ + [687] = {0xFCB524E4U, 0x0000004EU}, /* RGIDW_MODID[724]:IPMMUDS005*/ + [688] = {0xFCB524E8U, 0x0000002CU}, /* RGIDW_MODID[725]:SSI*/ + [689] = {0xFCB524ECU, 0x0000004EU}, /* RGIDW_MODID[726]:IPMMUDS006*/ + [690] = {0xFCB524F0U, 0x0000004EU}, /* RGIDW_MODID[727]:IPMMUDS007*/ + [691] = {0xFCB524F4U, 0x0000000CU}, /* RGIDW_MODID[728]:SYDM1P*/ + [692] = {0xFCB524F8U, 0x0000004EU}, /* RGIDW_MODID[729]:IPMMUDS008*/ + [693] = {0xFCB524FCU, 0x0000000CU}, /* RGIDW_MODID[730]:SYDM2P*/ + [694] = {0xFCB52500U, 0x0000004EU}, /* RGIDW_MODID[731]:IPMMUDS009*/ + [695] = {0xFCB52640U, 0x0000000CU}, /* RGIDW_MODID[732]:SYDM100*/ + [696] = {0xFCB52644U, 0x0000000CU}, /* RGIDW_MODID[733]:SYDM101*/ + [697] = {0xFCB52648U, 0x0000000CU}, /* RGIDW_MODID[734]:SYDM110*/ + [698] = {0xFCB5264CU, 0x0000000CU}, /* RGIDW_MODID[735]:SYDM111*/ + [699] = {0xFCB52650U, 0x0000000CU}, /* RGIDW_MODID[736]:SYDM112*/ + [700] = {0xFCB52654U, 0x0000000CU}, /* RGIDW_MODID[737]:SYDM113*/ + [701] = {0xFCB52658U, 0x0000000CU}, /* RGIDW_MODID[738]:SYDM114*/ + [702] = {0xFCB5265CU, 0x0000000CU}, /* RGIDW_MODID[739]:SYDM115*/ + [703] = {0xFCB52660U, 0x0000000CU}, /* RGIDW_MODID[740]:SYDM102*/ + [704] = {0xFCB52664U, 0x0000000CU}, /* RGIDW_MODID[741]:SYDM103*/ + [705] = {0xFCB52668U, 0x0000000CU}, /* RGIDW_MODID[742]:SYDM104*/ + [706] = {0xFCB5266CU, 0x0000000CU}, /* RGIDW_MODID[743]:SYDM105*/ + [707] = {0xFCB52670U, 0x0000000CU}, /* RGIDW_MODID[744]:SYDM106*/ + [708] = {0xFCB52674U, 0x0000000CU}, /* RGIDW_MODID[745]:SYDM107*/ + [709] = {0xFCB52678U, 0x0000000CU}, /* RGIDW_MODID[746]:SYDM108*/ + [710] = {0xFCB5267CU, 0x0000000CU}, /* RGIDW_MODID[747]:SYDM109*/ + [711] = {0xFCB52680U, 0x0000000CU}, /* RGIDW_MODID[748]:SYDM200*/ + [712] = {0xFCB52684U, 0x0000000CU}, /* RGIDW_MODID[749]:SYDM201*/ + [713] = {0xFCB52688U, 0x0000000CU}, /* RGIDW_MODID[750]:SYDM210*/ + [714] = {0xFCB5268CU, 0x0000000CU}, /* RGIDW_MODID[751]:SYDM211*/ + [715] = {0xFCB52690U, 0x0000000CU}, /* RGIDW_MODID[752]:SYDM212*/ + [716] = {0xFCB52694U, 0x0000000CU}, /* RGIDW_MODID[753]:SYDM213*/ + [717] = {0xFCB52698U, 0x0000000CU}, /* RGIDW_MODID[754]:SYDM214*/ + [718] = {0xFCB5269CU, 0x0000000CU}, /* RGIDW_MODID[755]:SYDM215*/ + [719] = {0xFCB526A0U, 0x0000000CU}, /* RGIDW_MODID[756]:SYDM202*/ + [720] = {0xFCB526A4U, 0x0000000CU}, /* RGIDW_MODID[757]:SYDM203*/ + [721] = {0xFCB526A8U, 0x0000000CU}, /* RGIDW_MODID[758]:SYDM204*/ + [722] = {0xFCB526ACU, 0x0000000CU}, /* RGIDW_MODID[759]:SYDM205*/ + [723] = {0xFCB526B0U, 0x0000000CU}, /* RGIDW_MODID[760]:SYDM206*/ + [724] = {0xFCB526B4U, 0x0000000CU}, /* RGIDW_MODID[761]:SYDM207*/ + [725] = {0xFCB526B8U, 0x0000000CU}, /* RGIDW_MODID[762]:SYDM208*/ + [726] = {0xFCB526BCU, 0x0000000CU}, /* RGIDW_MODID[763]:SYDM209*/ + [727] = {0xFC682400U, 0x00000002U}, /* RGIDW_MODID[764]:ARVC0*/ + /* After setting */ /* RGIDW_MODID[765]:ARVC1*/ + /* After setting */ /* RGIDW_MODID[766]:ARVC2*/ + [728] = {0xFC68240CU, 0x00000001U}, /* RGIDW_MODID[767]:ARVC3*/ + [729] = {0xFC682410U, 0x0000000EU}, /* RGIDW_MODID[768]:AXIFBABUSVC*/ + [730] = {0xFC682414U, 0x00000002U}, /* RGIDW_MODID[769]:ARVC4*/ + [731] = {0xFC682418U, 0x00000001U}, /* RGIDW_MODID[770]:ARVC5*/ + [732] = {0xFC68241CU, 0x00000002U}, /* RGIDW_MODID[771]:ARVC6*/ + [733] = {0xFC682420U, 0x00000002U}, /* RGIDW_MODID[772]:ARVC7*/ + [734] = {0xFC682424U, 0x00000000U}, /* RGIDW_MODID[773]:ARVC8*/ + [735] = {0xFC682428U, 0x0000000AU}, /* RGIDW_MODID[774]:CKMVC*/ + [736] = {0xFC68242CU, 0x0000000AU}, /* RGIDW_MODID[775]:ECMVC0*/ + [737] = {0xFC682430U, 0x0000004EU}, /* RGIDW_MODID[776]:IMR2*/ + [738] = {0xFC682434U, 0x0000004EU}, /* RGIDW_MODID[777]:IMR0*/ + [739] = {0xFC682438U, 0x0000004EU}, /* RGIDW_MODID[778]:IMR1*/ + [740] = {0xFC68243CU, 0x0000004EU}, /* RGIDW_MODID[779]:IPMMUVC01*/ + [741] = {0xFC682440U, 0x0000004EU}, /* RGIDW_MODID[780]:IPMMUVC10*/ + [742] = {0xFC682444U, 0x0000000CU}, /* RGIDW_MODID[781]:IMS0*/ + [743] = {0xFC682448U, 0x0000000CU}, /* RGIDW_MODID[782]:IMS1*/ + [744] = {0xFC68244CU, 0x0000004EU}, /* RGIDW_MODID[783]:IPMMUVC00*/ + [745] = {0xFC682450U, 0x0000004EU}, /* RGIDW_MODID[784]:IPMMUVC11*/ + [746] = {0xFC682454U, 0x0000004EU}, /* RGIDW_MODID[785]:IPMMUVC12*/ + [747] = {0xFC682458U, 0x0000004EU}, /* RGIDW_MODID[786]:IPMMUVC13*/ + [748] = {0xFC68245CU, 0x0000004EU}, /* RGIDW_MODID[787]:IPMMUVC14*/ + [749] = {0xFC682460U, 0x0000004EU}, /* RGIDW_MODID[788]:IPMMUVC15*/ + [750] = {0xFC682464U, 0x0000004EU}, /* RGIDW_MODID[789]:IPMMUVC02*/ + [751] = {0xFC682468U, 0x0000004EU}, /* RGIDW_MODID[790]:IPMMUVC03*/ + [752] = {0xFC68246CU, 0x0000004EU}, /* RGIDW_MODID[791]:IPMMUVC04*/ + [753] = {0xFC682470U, 0x0000004EU}, /* RGIDW_MODID[792]:IPMMUVC05*/ + [754] = {0xFC682474U, 0x0000004EU}, /* RGIDW_MODID[793]:IPMMUVC06*/ + [755] = {0xFC682478U, 0x0000004EU}, /* RGIDW_MODID[794]:IPMMUVC07*/ + [756] = {0xFC68247CU, 0x0000004EU}, /* RGIDW_MODID[795]:IPMMUVC08*/ + [757] = {0xFC682480U, 0x0000004EU}, /* RGIDW_MODID[796]:IPMMUVC09*/ + [758] = {0xFC682484U, 0x00000028U}, /* RGIDW_MODID[797]:IV1ES*/ + [759] = {0xFEBE2400U, 0x0000004EU}, /* RGIDW_MODID[798]:CSITOP0*/ + [760] = {0xFEBE2404U, 0x00000002U}, /* RGIDW_MODID[799]:ARVI10*/ + /* After setting */ /* RGIDW_MODID[800]:ARVI11*/ + /* After setting */ /* RGIDW_MODID[801]:ARVI12*/ + [761] = {0xFEBE2410U, 0x00000001U}, /* RGIDW_MODID[802]:ARVI13*/ + [762] = {0xFEBE2414U, 0x00000002U}, /* RGIDW_MODID[803]:ARVI14*/ + [763] = {0xFEBE2418U, 0x00000001U}, /* RGIDW_MODID[804]:ARVI15*/ + [764] = {0xFEBE241CU, 0x00000002U}, /* RGIDW_MODID[805]:ARVI16*/ + [765] = {0xFEBE2420U, 0x00000002U}, /* RGIDW_MODID[806]:ARVI17*/ + [766] = {0xFEBE2424U, 0x00000000U}, /* RGIDW_MODID[807]:ARVI18*/ + [767] = {0xFEBE2428U, 0x0000000AU}, /* RGIDW_MODID[808]:CKMVIO*/ + [768] = {0xFEBE242CU, 0x0000004EU}, /* RGIDW_MODID[809]:CSITOP1*/ + [769] = {0xFEBE2434U, 0x0000004EU}, /* RGIDW_MODID[810]:DSITLINK0*/ + [770] = {0xFEBE2438U, 0x0000004EU}, /* RGIDW_MODID[811]:DSITLINK1*/ + [771] = {0xFEBE243CU, 0x0000000AU}, /* RGIDW_MODID[812]:ECMVIO1*/ + [772] = {0xFEBE2444U, 0x0000004EU}, /* RGIDW_MODID[813]:IPMMUVI001*/ + [773] = {0xFEBE2448U, 0x0000000CU}, /* RGIDW_MODID[814]:FCPVX0*/ + [774] = {0xFEBE244CU, 0x0000000CU}, /* RGIDW_MODID[815]:FCPVX1*/ + [775] = {0xFEBE2458U, 0x0000004EU}, /* RGIDW_MODID[816]:IPMMUVI000*/ + [776] = {0xFEBE245CU, 0x0000004EU}, /* RGIDW_MODID[817]:IPMMUVI100*/ + [777] = {0xFEBE2460U, 0x0000004EU}, /* RGIDW_MODID[818]:IPMMUVI010*/ + [778] = {0xFEBE2464U, 0x0000004EU}, /* RGIDW_MODID[819]:IPMMUVI011*/ + [779] = {0xFEBE2468U, 0x0000004EU}, /* RGIDW_MODID[820]:VSPX0*/ + [780] = {0xFEBE246CU, 0x0000004EU}, /* RGIDW_MODID[821]:VSPX1*/ + [781] = {0xFEBE2478U, 0x0000004EU}, /* RGIDW_MODID[822]:IPMMUVI012*/ + [782] = {0xFEBE247CU, 0x0000004EU}, /* RGIDW_MODID[823]:IPMMUVI013*/ + [783] = {0xFEBE2480U, 0x0000004EU}, /* RGIDW_MODID[824]:IPMMUVI014*/ + [784] = {0xFEBE2484U, 0x0000004EU}, /* RGIDW_MODID[825]:IPMMUVI015*/ + [785] = {0xFEBE2488U, 0x0000004EU}, /* RGIDW_MODID[826]:IPMMUVI002*/ + [786] = {0xFEBE248CU, 0x0000004EU}, /* RGIDW_MODID[827]:IPMMUVI003*/ + [787] = {0xFEBE2490U, 0x0000004EU}, /* RGIDW_MODID[828]:IPMMUVI004*/ + [788] = {0xFEBE2494U, 0x0000004EU}, /* RGIDW_MODID[829]:IPMMUVI005*/ + [789] = {0xFEBE2498U, 0x0000004EU}, /* RGIDW_MODID[830]:IPMMUVI006*/ + [790] = {0xFEBE249CU, 0x0000004EU}, /* RGIDW_MODID[831]:IPMMUVI007*/ + [791] = {0xFEBE24A0U, 0x0000004EU}, /* RGIDW_MODID[832]:IPMMUVI008*/ + [792] = {0xFEBE24A4U, 0x0000004EU}, /* RGIDW_MODID[833]:IPMMUVI009*/ + [793] = {0xFEBE24A8U, 0x0000004EU}, /* RGIDW_MODID[834]:IPMMUVI101*/ + [794] = {0xFEBE24ACU, 0x0000004EU}, /* RGIDW_MODID[835]:IPMMUVI110*/ + [795] = {0xFEBE24B0U, 0x0000004EU}, /* RGIDW_MODID[836]:IPMMUVI111*/ + [796] = {0xFEBE24B4U, 0x0000004EU}, /* RGIDW_MODID[837]:IPMMUVI112*/ + [797] = {0xFEBE24B8U, 0x0000004EU}, /* RGIDW_MODID[838]:IPMMUVI113*/ + [798] = {0xFEBE24BCU, 0x0000004EU}, /* RGIDW_MODID[839]:IPMMUVI114*/ + [799] = {0xFEBE24C0U, 0x0000004EU}, /* RGIDW_MODID[840]:IPMMUVI115*/ + [800] = {0xFEBE24C4U, 0x0000004EU}, /* RGIDW_MODID[841]:IPMMUVI102*/ + [801] = {0xFEBE24C8U, 0x0000004EU}, /* RGIDW_MODID[842]:IPMMUVI103*/ + [802] = {0xFEBE24CCU, 0x0000004EU}, /* RGIDW_MODID[843]:IPMMUVI104*/ + [803] = {0xFEBE24D0U, 0x0000004EU}, /* RGIDW_MODID[844]:IPMMUVI105*/ + [804] = {0xFEBE24D4U, 0x0000004EU}, /* RGIDW_MODID[845]:IPMMUVI106*/ + [805] = {0xFEBE24D8U, 0x0000004EU}, /* RGIDW_MODID[846]:IPMMUVI107*/ + [806] = {0xFEBE24DCU, 0x0000004EU}, /* RGIDW_MODID[847]:IPMMUVI108*/ + [807] = {0xFEBE24E0U, 0x0000004EU}, /* RGIDW_MODID[848]:IPMMUVI109*/ + [808] = {0xFEBE2504U, 0x0000000EU}, /* RGIDW_MODID[849]:AXIFBABUSVIO*/ + [809] = {0xFEBF2400U, 0x00000002U}, /* RGIDW_MODID[850]:ARVI0*/ + /* After setting */ /* RGIDW_MODID[851]:ARVI1*/ + /* After setting */ /* RGIDW_MODID[852]:ARVI2*/ + [810] = {0xFEBF240CU, 0x00000001U}, /* RGIDW_MODID[853]:ARVI3*/ + [811] = {0xFEBF2410U, 0x00000002U}, /* RGIDW_MODID[854]:ARVI4*/ + [812] = {0xFEBF2414U, 0x00000001U}, /* RGIDW_MODID[855]:ARVI5*/ + [813] = {0xFEBF2418U, 0x00000002U}, /* RGIDW_MODID[856]:ARVI6*/ + [814] = {0xFEBF241CU, 0x00000002U}, /* RGIDW_MODID[857]:ARVI7*/ + [815] = {0xFEBF2420U, 0x00000000U}, /* RGIDW_MODID[858]:ARVI8*/ + [816] = {0xFEBF2424U, 0x0000000AU}, /* RGIDW_MODID[859]:ECMVIO0*/ + [817] = {0xFEBF2428U, 0x0000004EU}, /* RGIDW_MODID[860]:ISP0*/ + [818] = {0xFEBF242CU, 0x0000004EU}, /* RGIDW_MODID[861]:ISP0CORE*/ + [819] = {0xFEBF2430U, 0x0000004EU}, /* RGIDW_MODID[862]:ISP1*/ + [820] = {0xFEBF2434U, 0x0000004EU}, /* RGIDW_MODID[863]:ISP1CORE*/ + [821] = {0xFEBF2454U, 0x0000004EU}, /* RGIDW_MODID[864]:VIN00*/ + [822] = {0xFEBF2458U, 0x0000004EU}, /* RGIDW_MODID[865]:VIN01*/ + [823] = {0xFEBF245CU, 0x0000004EU}, /* RGIDW_MODID[866]:VIN02*/ + [824] = {0xFEBF2460U, 0x0000004EU}, /* RGIDW_MODID[867]:VIN03*/ + [825] = {0xFEBF2464U, 0x0000004EU}, /* RGIDW_MODID[868]:VIN04*/ + [826] = {0xFEBF2468U, 0x0000004EU}, /* RGIDW_MODID[869]:VIN05*/ + [827] = {0xFEBF246CU, 0x0000004EU}, /* RGIDW_MODID[870]:VIN06*/ + [828] = {0xFEBF2470U, 0x0000004EU}, /* RGIDW_MODID[871]:VIN07*/ + [829] = {0xFEBF2474U, 0x0000004EU}, /* RGIDW_MODID[872]:VIN10*/ + [830] = {0xFEBF2478U, 0x0000004EU}, /* RGIDW_MODID[873]:VIN11*/ + [831] = {0xFEBF247CU, 0x0000004EU}, /* RGIDW_MODID[874]:VIN12*/ + [832] = {0xFEBF2480U, 0x0000004EU}, /* RGIDW_MODID[875]:VIN13*/ + [833] = {0xFEBF2484U, 0x0000004EU}, /* RGIDW_MODID[876]:VIN14*/ + [834] = {0xFEBF2488U, 0x0000004EU}, /* RGIDW_MODID[877]:VIN15*/ + [835] = {0xFEBF248CU, 0x0000004EU}, /* RGIDW_MODID[878]:VIN16*/ + [836] = {0xFEBF2490U, 0x0000004EU}, /* RGIDW_MODID[879]:VIN17*/ + [837] = {0xFC312400U, 0x00000002U}, /* RGIDW_MODID[880]:ARVIP00*/ + /* After setting */ /* RGIDW_MODID[881]:ARVIP01*/ + /* After setting */ /* RGIDW_MODID[882]:ARVIP02*/ + [838] = {0xFC31240CU, 0x00000001U}, /* RGIDW_MODID[883]:ARVIP03*/ + [839] = {0xFC312410U, 0x0000000EU}, /* RGIDW_MODID[884]:AXIFBABUSVIP0*/ + [840] = {0xFC312414U, 0x00000002U}, /* RGIDW_MODID[885]:ARVIP04*/ + [841] = {0xFC312418U, 0x00000001U}, /* RGIDW_MODID[886]:ARVIP05*/ + [842] = {0xFC31241CU, 0x00000002U}, /* RGIDW_MODID[887]:ARVIP06*/ + [843] = {0xFC312420U, 0x00000002U}, /* RGIDW_MODID[888]:ARVIP07*/ + [844] = {0xFC312424U, 0x00000000U}, /* RGIDW_MODID[889]:ARVIP08*/ + [845] = {0xFC312428U, 0x0000000AU}, /* RGIDW_MODID[890]:CKMVIP*/ + [846] = {0xFC31242CU, 0x0000000AU}, /* RGIDW_MODID[891]:ECMVIP0*/ + [847] = {0xFC312430U, 0x0000004EU}, /* RGIDW_MODID[892]:IPMMUVIP000*/ + [848] = {0xFC312438U, 0x0000004EU}, /* RGIDW_MODID[893]:SMPO0*/ + [849] = {0xFC31243CU, 0x0000004EU}, /* RGIDW_MODID[894]:SMPS0*/ + [850] = {0xFC312440U, 0x0000000CU}, /* RGIDW_MODID[895]:UMFL0*/ + [851] = {0xFC312444U, 0x0000004EU}, /* RGIDW_MODID[896]:IPMMUVIP001*/ + [852] = {0xFC312448U, 0x0000004EU}, /* RGIDW_MODID[897]:IPMMUVIP010*/ + [853] = {0xFC31244CU, 0x0000004EU}, /* RGIDW_MODID[898]:IPMMUVIP011*/ + [854] = {0xFC312450U, 0x0000004EU}, /* RGIDW_MODID[899]:UMFL0M_W*/ + [855] = {0xFC312454U, 0x0000004EU}, /* RGIDW_MODID[900]:IPMMUVIP012*/ + [856] = {0xFC312458U, 0x0000004EU}, /* RGIDW_MODID[901]:IPMMUVIP013*/ + [857] = {0xFC31245CU, 0x0000004EU}, /* RGIDW_MODID[902]:IPMMUVIP014*/ + [858] = {0xFC312460U, 0x0000004EU}, /* RGIDW_MODID[903]:IPMMUVIP015*/ + [859] = {0xFC312464U, 0x0000004EU}, /* RGIDW_MODID[904]:IPMMUVIP002*/ + [860] = {0xFC312468U, 0x0000004EU}, /* RGIDW_MODID[905]:IPMMUVIP003*/ + [861] = {0xFC31246CU, 0x0000004EU}, /* RGIDW_MODID[906]:IPMMUVIP004*/ + [862] = {0xFC312470U, 0x0000004EU}, /* RGIDW_MODID[907]:IPMMUVIP005*/ + [863] = {0xFC312474U, 0x0000004EU}, /* RGIDW_MODID[908]:IPMMUVIP006*/ + [864] = {0xFC312478U, 0x0000004EU}, /* RGIDW_MODID[909]:IPMMUVIP007*/ + [865] = {0xFC31247CU, 0x0000004EU}, /* RGIDW_MODID[910]:IPMMUVIP008*/ + [866] = {0xFC312480U, 0x0000004EU}, /* RGIDW_MODID[911]:IPMMUVIP009*/ + [867] = {0xFC342400U, 0x00000002U}, /* RGIDW_MODID[912]:ARVIP10*/ + /* After setting */ /* RGIDW_MODID[913]:ARVIP11*/ + /* After setting */ /* RGIDW_MODID[914]:ARVIP12*/ + [868] = {0xFC34240CU, 0x00000001U}, /* RGIDW_MODID[915]:ARVIP13*/ + [869] = {0xFC342410U, 0x0000000EU}, /* RGIDW_MODID[916]:AXIFBABUSVIP1*/ + [870] = {0xFC342414U, 0x00000002U}, /* RGIDW_MODID[917]:ARVIIP14*/ + [871] = {0xFC342418U, 0x00000001U}, /* RGIDW_MODID[918]:ARVIIP15*/ + [872] = {0xFC34241CU, 0x00000002U}, /* RGIDW_MODID[919]:ARVIIP16*/ + [873] = {0xFC342420U, 0x00000002U}, /* RGIDW_MODID[920]:ARVIIP17*/ + [874] = {0xFC342424U, 0x00000000U}, /* RGIDW_MODID[921]:ARVIIP18*/ + [875] = {0xFC342438U, 0x0000000AU}, /* RGIDW_MODID[922]:ECMVIP1*/ + [876] = {0xFC34243CU, 0x0000004EU}, /* RGIDW_MODID[923]:IPMMUVIP101*/ + [877] = {0xFC342440U, 0x0000004EU}, /* RGIDW_MODID[924]:IPMMUVIP100*/ + [878] = {0xFC342444U, 0x0000004EU}, /* RGIDW_MODID[925]:IPMMUVIP110*/ + [879] = {0xFC342448U, 0x0000004EU}, /* RGIDW_MODID[926]:IPMMUVIP111*/ + [880] = {0xFC34244CU, 0x0000004EU}, /* RGIDW_MODID[927]:IPMMUVIP112*/ + [881] = {0xFC342450U, 0x0000004EU}, /* RGIDW_MODID[928]:IPMMUVIP113*/ + [882] = {0xFC342454U, 0x0000004EU}, /* RGIDW_MODID[929]:IPMMUVIP114*/ + [883] = {0xFC342458U, 0x0000004EU}, /* RGIDW_MODID[930]:IPMMUVIP115*/ + [884] = {0xFC34245CU, 0x0000004EU}, /* RGIDW_MODID[931]:IPMMUVIP102*/ + [885] = {0xFC342460U, 0x0000004EU}, /* RGIDW_MODID[932]:IPMMUVIP103*/ + [886] = {0xFC342464U, 0x0000004EU}, /* RGIDW_MODID[933]:IPMMUVIP104*/ + [887] = {0xFC342468U, 0x0000004EU}, /* RGIDW_MODID[934]:IPMMUVIP105*/ + [888] = {0xFC34246CU, 0x0000004EU}, /* RGIDW_MODID[935]:IPMMUVIP106*/ + [889] = {0xFC342470U, 0x0000004EU}, /* RGIDW_MODID[936]:IPMMUVIP107*/ + [890] = {0xFC342474U, 0x0000004EU}, /* RGIDW_MODID[937]:IPMMUVIP108*/ + [891] = {0xFC342478U, 0x0000004EU}, /* RGIDW_MODID[938]:IPMMUVIP109*/ + [892] = {0xFC342518U, 0x00000004U}, /* RGIDW_MODID[939]:PAP*/ + [893] = {0xFC402400U, 0x00000002U}, /* RGIDW_MODID[940]:ARDSP0*/ + /* After setting */ /* RGIDW_MODID[941]:ARDSP1*/ + /* After setting */ /* RGIDW_MODID[942]:ARDSP2*/ + [894] = {0xFC40240CU, 0x00000001U}, /* RGIDW_MODID[943]:ARDSP3*/ + [895] = {0xFC402410U, 0x00000002U}, /* RGIDW_MODID[944]:ARDSP4*/ + [896] = {0xFC402414U, 0x00000001U}, /* RGIDW_MODID[945]:ARDSP5*/ + [897] = {0xFC402418U, 0x00000002U}, /* RGIDW_MODID[946]:ARDSP6*/ + [898] = {0xFC40241CU, 0x00000002U}, /* RGIDW_MODID[947]:ARDSP7*/ + [899] = {0xFC402420U, 0x0000000AU}, /* RGIDW_MODID[948]:ECMDSP*/ + [900] = {0xFC402424U, 0x0000000CU}, /* RGIDW_MODID[949]:AXIDSP0*/ + [901] = {0xFC402428U, 0x0000000CU}, /* RGIDW_MODID[950]:AXIDSP1*/ + [902] = {0xFC40242CU, 0x0000000CU}, /* RGIDW_MODID[951]:AXIDSP2*/ + [903] = {0xFC402430U, 0x0000000CU}, /* RGIDW_MODID[952]:AXIDSP3*/ + [905] = {0xFDDB969CU, 0x00000000U}, /* RGIDW_MODID[953]:ARCC*/ + [904] = {0xFDDB96B0U, 0x00000000U}, /* RGIDW_MODID[954]:ARRTRAM*/ + [906] = {0xFCB52424U, 0x00000000U}, /* RGIDW_MODID[955]:RSV0*/ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_sec_tbl" +const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[] = { + [0] = {0xFD483400U, 0x00000000U}, /* SEC_MODID[0]:ARMGC0*/ + [1] = {0xFD483404U, 0x00000002U}, /* SEC_MODID[1]:ARMGC1*/ + [2] = {0xFD483408U, 0x00000002U}, /* SEC_MODID[2]:ARMGC2*/ + [3] = {0xFD48340CU, 0x00000002U}, /* SEC_MODID[3]:ARRT00*/ + [4] = {0xFD483410U, 0x00000002U}, /* SEC_MODID[4]:ARRT01*/ + [5] = {0xFD483414U, 0x00000002U}, /* SEC_MODID[5]:ARRT02*/ + [6] = {0xFD483418U, 0x00000002U}, /* SEC_MODID[6]:ARRT03*/ + [7] = {0xFD48341CU, 0x00000002U}, /* SEC_MODID[7]:ARRT04*/ + [8] = {0xFD483420U, 0x00000002U}, /* SEC_MODID[8]:ARRT05*/ + [9] = {0xFD483424U, 0x00000002U}, /* SEC_MODID[9]:ARRT06*/ + [10] = {0xFD483428U, 0x00000002U}, /* SEC_MODID[10]:ARRT07*/ + [11] = {0xFD48342CU, 0x00000002U}, /* SEC_MODID[11]:ARRT08*/ + [12] = {0xFD483430U, 0x00000000U}, /* SEC_MODID[12]:LIFEC0*/ + [13] = {0xFD483434U, 0x00000002U}, /* SEC_MODID[13]:SWDT*/ + [14] = {0xFD483438U, 0x00000002U}, /* SEC_MODID[14]:TMU0*/ + [15] = {0xFD48343CU, 0x00000002U}, /* SEC_MODID[15]:WDT*/ + [16] = {0xFD483440U, 0x00000002U}, /* SEC_MODID[16]:WWDT0*/ + [17] = {0xFD483444U, 0x00000002U}, /* SEC_MODID[17]:WWDT1*/ + [18] = {0xFD483448U, 0x00000002U}, /* SEC_MODID[18]:WWDT2*/ + [19] = {0xFD48344CU, 0x00000002U}, /* SEC_MODID[19]:WWDT3*/ + [20] = {0xFD483450U, 0x00000002U}, /* SEC_MODID[20]:WWDT4*/ + [21] = {0xFD483454U, 0x00000002U}, /* SEC_MODID[21]:WWDT5*/ + [22] = {0xFD483458U, 0x00000002U}, /* SEC_MODID[22]:WWDT6*/ + [23] = {0xFD483468U, 0x00000002U}, /* SEC_MODID[23]:ECMRT3*/ + [24] = {0xFDA03400U, 0x00000002U}, /* SEC_MODID[24]:ADVFSC*/ + [25] = {0xFDA03404U, 0x00000002U}, /* SEC_MODID[25]:APMU0*/ + [26] = {0xFDA03408U, 0x00000002U}, /* SEC_MODID[26]:APMU1*/ + [27] = {0xFDA0340CU, 0x00000002U}, /* SEC_MODID[27]:APMU10*/ + [28] = {0xFDA03410U, 0x00000002U}, /* SEC_MODID[28]:APMU11*/ + [29] = {0xFDA03414U, 0x00000002U}, /* SEC_MODID[29]:APMU12*/ + [30] = {0xFDA03418U, 0x00000002U}, /* SEC_MODID[30]:APMU13*/ + [31] = {0xFDA0341CU, 0x00000002U}, /* SEC_MODID[31]:APMU14*/ + [32] = {0xFDA03420U, 0x00000002U}, /* SEC_MODID[32]:APMU15*/ + [33] = {0xFDA03424U, 0x00000002U}, /* SEC_MODID[33]:APMU2*/ + [34] = {0xFDA03428U, 0x00000002U}, /* SEC_MODID[34]:APMU3*/ + [35] = {0xFDA0342CU, 0x00000002U}, /* SEC_MODID[35]:APMU4*/ + [36] = {0xFDA03430U, 0x00000002U}, /* SEC_MODID[36]:APMU5*/ + [37] = {0xFDA03434U, 0x00000002U}, /* SEC_MODID[37]:APMU6*/ + [38] = {0xFDA03438U, 0x00000002U}, /* SEC_MODID[38]:APMU7*/ + [39] = {0xFDA0343CU, 0x00000002U}, /* SEC_MODID[39]:APMU8*/ + [40] = {0xFDA03440U, 0x00000002U}, /* SEC_MODID[40]:APMU9*/ + [41] = {0xFDA03444U, 0x00000002U}, /* SEC_MODID[41]:ARS00*/ + [42] = {0xFDA03448U, 0x00000002U}, /* SEC_MODID[42]:ARS01*/ + [43] = {0xFDA0344CU, 0x00000002U}, /* SEC_MODID[43]:ARS02*/ + [44] = {0xFDA03450U, 0x00000002U}, /* SEC_MODID[44]:ARS03*/ + [45] = {0xFDA03454U, 0x00000002U}, /* SEC_MODID[45]:ARS04*/ + [46] = {0xFDA03458U, 0x00000002U}, /* SEC_MODID[46]:ARS05*/ + [47] = {0xFDA0345CU, 0x00000002U}, /* SEC_MODID[47]:ARS06*/ + [48] = {0xFDA03460U, 0x00000002U}, /* SEC_MODID[48]:ARS07*/ + [49] = {0xFDA03464U, 0x00000002U}, /* SEC_MODID[49]:ARS08*/ + [50] = {0xFDA03468U, 0x00000002U}, /* SEC_MODID[50]:CMT0*/ + [51] = {0xFDA0346CU, 0x00000002U}, /* SEC_MODID[51]:CMT1*/ + [52] = {0xFDA03470U, 0x00000002U}, /* SEC_MODID[52]:CMT2*/ + [53] = {0xFDA03474U, 0x00000002U}, /* SEC_MODID[53]:CMT3*/ + [54] = {0xFDA03478U, 0x00000002U}, /* SEC_MODID[54]:CKM*/ + [55] = {0xFDA0347CU, 0x00000002U}, /* SEC_MODID[55]:DBE*/ + [56] = {0xFDA03480U, 0x00000002U}, /* SEC_MODID[56]:IRQC*/ + [57] = {0xFDA03484U, 0x00000002U}, /* SEC_MODID[57]:ECMPS0*/ + [58] = {0xFDA03488U, 0x00000002U}, /* SEC_MODID[58]:OTP0*/ + [59] = {0xFDA0348CU, 0x00000002U}, /* SEC_MODID[59]:OTP1*/ + [60] = {0xFDA0349CU, 0x00000002U}, /* SEC_MODID[60]:SCMT*/ + [61] = {0xFDA034A8U, 0x00000002U}, /* SEC_MODID[61]:TSC1*/ + [62] = {0xFDA034ACU, 0x00000002U}, /* SEC_MODID[62]:TSC2*/ + [63] = {0xFDA034B0U, 0x00000002U}, /* SEC_MODID[63]:TSC3*/ + [64] = {0xFDA034B4U, 0x00000002U}, /* SEC_MODID[64]:TSC4*/ + [65] = {0xFDA034B8U, 0x00000002U}, /* SEC_MODID[65]:UCMT*/ + [66] = {0xFDA03500U, 0x00000002U}, /* SEC_MODID[66]:CPG0*/ + [67] = {0xFDA03504U, 0x00000002U}, /* SEC_MODID[67]:CPG1*/ + [68] = {0xFDA03508U, 0x00000002U}, /* SEC_MODID[68]:CPG2*/ + [69] = {0xFDA0350CU, 0x00000002U}, /* SEC_MODID[69]:CPG3*/ + [70] = {0xFDA03510U, 0x00000002U}, /* SEC_MODID[70]:PFC00*/ + [71] = {0xFDA03514U, 0x00000002U}, /* SEC_MODID[71]:PFC01*/ + [72] = {0xFDA03518U, 0x00000002U}, /* SEC_MODID[72]:PFC02*/ + [73] = {0xFDA0351CU, 0x00000002U}, /* SEC_MODID[73]:PFC03*/ + [74] = {0xFDA03520U, 0x00000002U}, /* SEC_MODID[74]:PFC10*/ + [75] = {0xFDA03524U, 0x00000002U}, /* SEC_MODID[75]:PFC11*/ + [76] = {0xFDA03528U, 0x00000002U}, /* SEC_MODID[76]:PFC12*/ + [77] = {0xFDA0352CU, 0x00000002U}, /* SEC_MODID[77]:PFC13*/ + [78] = {0xFDA03530U, 0x00000002U}, /* SEC_MODID[78]:PFC20*/ + [79] = {0xFDA03534U, 0x00000002U}, /* SEC_MODID[79]:PFC21*/ + [80] = {0xFDA03538U, 0x00000002U}, /* SEC_MODID[80]:PFC22*/ + [81] = {0xFDA0353CU, 0x00000002U}, /* SEC_MODID[81]:PFC23*/ + [82] = {0xFDA03540U, 0x00000002U}, /* SEC_MODID[82]:PFC30*/ + [83] = {0xFDA03544U, 0x00000002U}, /* SEC_MODID[83]:PFC31*/ + [84] = {0xFDA03548U, 0x00000002U}, /* SEC_MODID[84]:PFC32*/ + [85] = {0xFDA0354CU, 0x00000002U}, /* SEC_MODID[85]:PFC33*/ + [86] = {0xFDA03550U, 0x00000002U}, /* SEC_MODID[86]:PFCS0*/ + [87] = {0xFDA03554U, 0x00000002U}, /* SEC_MODID[87]:PFCS1*/ + [88] = {0xFDA03558U, 0x00000002U}, /* SEC_MODID[88]:PFCS2*/ + [89] = {0xFDA0355CU, 0x00000002U}, /* SEC_MODID[89]:PFCS3*/ + [90] = {0xFDA03560U, 0x00000002U}, /* SEC_MODID[90]:RESET0*/ + [91] = {0xFDA03564U, 0x00000002U}, /* SEC_MODID[91]:RESET1*/ + [92] = {0xFDA03568U, 0x00000002U}, /* SEC_MODID[92]:RESET2*/ + [93] = {0xFDA0356CU, 0x00000002U}, /* SEC_MODID[93]:RESET3*/ + [94] = {0xFDA03570U, 0x00000002U}, /* SEC_MODID[94]:SYS0*/ + [95] = {0xFDA03574U, 0x00000002U}, /* SEC_MODID[95]:SYS1*/ + [96] = {0xFDA03578U, 0x00000002U}, /* SEC_MODID[96]:SYS2*/ + [97] = {0xFDA0357CU, 0x00000002U}, /* SEC_MODID[97]:SYS3*/ + [98] = {0xFCB63400U, 0x00000002U}, /* SEC_MODID[98]:DMAMSI0*/ + [99] = {0xFCB63404U, 0x00000002U}, /* SEC_MODID[99]:DMAMSI1*/ + [100] = {0xFCB63408U, 0x00000002U}, /* SEC_MODID[100]:DMAMSI2*/ + [101] = {0xFCB6340CU, 0x00000002U}, /* SEC_MODID[101]:DMAMSI3*/ + [102] = {0xFCB63410U, 0x00000002U}, /* SEC_MODID[102]:DMAMSI4*/ + [103] = {0xFCB63414U, 0x00000002U}, /* SEC_MODID[103]:DMAMSI5*/ + [104] = {0xFCB63418U, 0x00000002U}, /* SEC_MODID[104]:ECMSP3*/ + [105] = {0xFCB63424U, 0x00000002U}, /* SEC_MODID[105]:ARSP30*/ + [106] = {0xFCB63428U, 0x00000002U}, /* SEC_MODID[106]:ARSP31*/ + [107] = {0xFCB6342CU, 0x00000002U}, /* SEC_MODID[107]:ARSP32*/ + [108] = {0xFCB63430U, 0x00000002U}, /* SEC_MODID[108]:ARSP33*/ + [109] = {0xFCB63434U, 0x00000002U}, /* SEC_MODID[109]:ARSP34*/ + [110] = {0xFCB63438U, 0x00000002U}, /* SEC_MODID[110]:ARSP35*/ + [111] = {0xFCB6343CU, 0x00000002U}, /* SEC_MODID[111]:ARSP36*/ + [112] = {0xFCB63440U, 0x00000002U}, /* SEC_MODID[112]:ARSP37*/ + [113] = {0xFCB63444U, 0x00000002U}, /* SEC_MODID[113]:ARSP38*/ + [114] = {0xFCB63448U, 0x00000002U}, /* SEC_MODID[114]:MSI0*/ + [115] = {0xFCB6344CU, 0x00000002U}, /* SEC_MODID[115]:MSI1*/ + [116] = {0xFCB63450U, 0x00000002U}, /* SEC_MODID[116]:MSI2*/ + [117] = {0xFCB63454U, 0x00000002U}, /* SEC_MODID[117]:MSI3*/ + [118] = {0xFCB63458U, 0x00000002U}, /* SEC_MODID[118]:MSI4*/ + [119] = {0xFCB6345CU, 0x00000002U}, /* SEC_MODID[119]:MSI5*/ + [120] = {0xFCB93400U, 0x00000002U}, /* SEC_MODID[120]:ARSP40*/ + [121] = {0xFCB93404U, 0x00000002U}, /* SEC_MODID[121]:ARSP41*/ + [122] = {0xFCB93408U, 0x00000002U}, /* SEC_MODID[122]:ARSP42*/ + [123] = {0xFCB9340CU, 0x00000002U}, /* SEC_MODID[123]:ARSP43*/ + [124] = {0xFCB93410U, 0x00000002U}, /* SEC_MODID[124]:ARSP44*/ + [125] = {0xFCB93414U, 0x00000002U}, /* SEC_MODID[125]:ARSP45*/ + [126] = {0xFCB93418U, 0x00000002U}, /* SEC_MODID[126]:ARSP46*/ + [127] = {0xFCB9341CU, 0x00000002U}, /* SEC_MODID[127]:ARSP47*/ + [128] = {0xFCB93420U, 0x00000002U}, /* SEC_MODID[128]:ARSP48*/ + [129] = {0xFCB93424U, 0x00000002U}, /* SEC_MODID[129]:DMAHSCIF0*/ + [130] = {0xFCB93428U, 0x00000002U}, /* SEC_MODID[130]:DMAHSCIF1*/ + [131] = {0xFCB9342CU, 0x00000002U}, /* SEC_MODID[131]:DMAHSCIF2*/ + [132] = {0xFCB93430U, 0x00000002U}, /* SEC_MODID[132]:DMAHSCIF3*/ + [133] = {0xFCB93434U, 0x00000002U}, /* SEC_MODID[133]:DMASCIF0*/ + [134] = {0xFCB93438U, 0x00000002U}, /* SEC_MODID[134]:DMASCIF1*/ + [135] = {0xFCB9343CU, 0x00000002U}, /* SEC_MODID[135]:DMASCIF3*/ + [136] = {0xFCB93440U, 0x00000002U}, /* SEC_MODID[136]:DMASCIF4*/ + [137] = {0xFCB93444U, 0x00000002U}, /* SEC_MODID[137]:ECMSP4*/ + [138] = {0xFCB93448U, 0x00000002U}, /* SEC_MODID[138]:HSCIF0*/ + [139] = {0xFCB9344CU, 0x00000002U}, /* SEC_MODID[139]:HSCIF1*/ + [140] = {0xFCB93450U, 0x00000002U}, /* SEC_MODID[140]:HSCIF2*/ + [141] = {0xFCB93454U, 0x00000002U}, /* SEC_MODID[141]:HSCIF3*/ + [142] = {0xFCB93458U, 0x00000002U}, /* SEC_MODID[142]:SCIF0*/ + [143] = {0xFCB9345CU, 0x00000002U}, /* SEC_MODID[143]:SCIF1*/ + [144] = {0xFCB93460U, 0x00000002U}, /* SEC_MODID[144]:SCIF3*/ + [145] = {0xFCB93464U, 0x00000002U}, /* SEC_MODID[145]:SCIF4*/ + [146] = {0xFCB93468U, 0x00000002U}, /* SEC_MODID[146]:TMU1*/ + [147] = {0xFCB9346CU, 0x00000002U}, /* SEC_MODID[147]:TMU2*/ + [148] = {0xFCB93470U, 0x00000002U}, /* SEC_MODID[148]:TMU3*/ + [149] = {0xFCB93474U, 0x00000002U}, /* SEC_MODID[149]:TMU4*/ + [150] = {0xFCB93478U, 0x00000002U}, /* SEC_MODID[150]:CANFD*/ + [151] = {0xFCB9347CU, 0x00000002U}, /* SEC_MODID[151]:DMACANFD*/ + [152] = {0xFCB93480U, 0x00000002U}, /* SEC_MODID[152]:DMATPU0*/ + [153] = {0xFCB93484U, 0x00000002U}, /* SEC_MODID[153]:PWM0*/ + [154] = {0xFCB93488U, 0x00000002U}, /* SEC_MODID[154]:PWM1*/ + [155] = {0xFCB9348CU, 0x00000002U}, /* SEC_MODID[155]:PWM2*/ + [156] = {0xFCB93490U, 0x00000002U}, /* SEC_MODID[156]:PWM3*/ + [157] = {0xFCB93494U, 0x00000002U}, /* SEC_MODID[157]:PWM4*/ + [158] = {0xFCB93498U, 0x00000002U}, /* SEC_MODID[158]:PWM5*/ + [159] = {0xFCB9349CU, 0x00000002U}, /* SEC_MODID[159]:PWM6*/ + [160] = {0xFCB934A0U, 0x00000002U}, /* SEC_MODID[160]:PWM7*/ + [161] = {0xFCB934A4U, 0x00000002U}, /* SEC_MODID[161]:PWM8*/ + [162] = {0xFCB934A8U, 0x00000002U}, /* SEC_MODID[162]:PWM9*/ + [163] = {0xFCB934ACU, 0x00000002U}, /* SEC_MODID[163]:TPU0*/ + [164] = {0xFC673400U, 0x00000002U}, /* SEC_MODID[164]:ARVC10*/ + [165] = {0xFC673404U, 0x00000002U}, /* SEC_MODID[165]:ARVC11*/ + [166] = {0xFC673408U, 0x00000002U}, /* SEC_MODID[166]:ARVC12*/ + [167] = {0xFC67340CU, 0x00000002U}, /* SEC_MODID[167]:ARVC13*/ + [168] = {0xFC673410U, 0x00000002U}, /* SEC_MODID[168]:ARVC14*/ + [169] = {0xFC673414U, 0x00000002U}, /* SEC_MODID[169]:ARVC15*/ + [170] = {0xFC673418U, 0x00000002U}, /* SEC_MODID[170]:ARVC16*/ + [171] = {0xFC67341CU, 0x00000002U}, /* SEC_MODID[171]:ARVC17*/ + [172] = {0xFC673420U, 0x00000002U}, /* SEC_MODID[172]:ARVC18*/ + [173] = {0xFC673424U, 0x00000002U}, /* SEC_MODID[173]:ECMVC1*/ + [174] = {0xFC673428U, 0x00000002U}, /* SEC_MODID[174]:FCPCS*/ + [175] = {0xFC67342CU, 0x00000002U}, /* SEC_MODID[175]:VCP4LC*/ + [176] = {0xFC673430U, 0x00000002U}, /* SEC_MODID[176]:VCP4LV*/ + [177] = {0xFEBD3400U, 0x00000002U}, /* SEC_MODID[177]:ARVI40*/ + [178] = {0xFEBD3404U, 0x00000002U}, /* SEC_MODID[178]:ARVI41*/ + [179] = {0xFEBD3408U, 0x00000002U}, /* SEC_MODID[179]:ARVI42*/ + [180] = {0xFEBD340CU, 0x00000002U}, /* SEC_MODID[180]:ARVI43*/ + [181] = {0xFEBD3410U, 0x00000002U}, /* SEC_MODID[181]:ARVI44*/ + [182] = {0xFEBD3414U, 0x00000002U}, /* SEC_MODID[182]:ARVI45*/ + [183] = {0xFEBD3418U, 0x00000002U}, /* SEC_MODID[183]:ARVI46*/ + [184] = {0xFEBD341CU, 0x00000002U}, /* SEC_MODID[184]:ARVI47*/ + [185] = {0xFEBD3420U, 0x00000002U}, /* SEC_MODID[185]:ARVI48*/ + [186] = {0xFEBD3424U, 0x00000002U}, /* SEC_MODID[186]:DIS0*/ + [187] = {0xFEBD342CU, 0x00000002U}, /* SEC_MODID[187]:DSC*/ + [188] = {0xFEBD3430U, 0x00000002U}, /* SEC_MODID[188]:ECMVIO2*/ + [189] = {0xFEBD3434U, 0x00000002U}, /* SEC_MODID[189]:FCPVD0*/ + [190] = {0xFEBD3438U, 0x00000002U}, /* SEC_MODID[190]:FCPVD1*/ + [191] = {0xFEBD343CU, 0x00000002U}, /* SEC_MODID[191]:VSPD0*/ + [192] = {0xFEBD3440U, 0x00000002U}, /* SEC_MODID[192]:VSPD1*/ + [193] = {0xFCF83400U, 0x00000002U}, /* SEC_MODID[193]:CKMHSC*/ + [194] = {0xFCF83404U, 0x00000002U}, /* SEC_MODID[194]:AXIPCI001*/ + [195] = {0xFCF83408U, 0x00000002U}, /* SEC_MODID[195]:AXIPCI002*/ + [196] = {0xFCF8340CU, 0x00000002U}, /* SEC_MODID[196]:AXIPCI003*/ + [197] = {0xFCF83414U, 0x00000002U}, /* SEC_MODID[197]:AXIPCI005*/ + [198] = {0xFCF83418U, 0x00000002U}, /* SEC_MODID[198]:AXIPCI006*/ + [199] = {0xFCF8341CU, 0x00000002U}, /* SEC_MODID[199]:AXIPCI007*/ + [200] = {0xFCF83420U, 0x00000002U}, /* SEC_MODID[200]:AXIPCI008*/ + [201] = {0xFCF83424U, 0x00000002U}, /* SEC_MODID[201]:AXIPCI009*/ + [202] = {0xFCF83428U, 0x00000002U}, /* SEC_MODID[202]:AXIPCI010*/ + [203] = {0xFCF8342CU, 0x00000002U}, /* SEC_MODID[203]:AXIPCI011*/ + [204] = {0xFCF83430U, 0x00000002U}, /* SEC_MODID[204]:AXIPCI012*/ + [205] = {0xFCF83434U, 0x00000002U}, /* SEC_MODID[205]:AXIPCI013*/ + [206] = {0xFCF83438U, 0x00000002U}, /* SEC_MODID[206]:AXIPCI014*/ + [207] = {0xFCF8343CU, 0x00000002U}, /* SEC_MODID[207]:AXIPCI015*/ + [208] = {0xFCF83440U, 0x00000002U}, /* SEC_MODID[208]:AXIPCI100*/ + [209] = {0xFCF83444U, 0x00000002U}, /* SEC_MODID[209]:AXIPCI101*/ + [210] = {0xFCF83448U, 0x00000002U}, /* SEC_MODID[210]:AXIPCI102*/ + [211] = {0xFCF8344CU, 0x00000002U}, /* SEC_MODID[211]:AXIPCI103*/ + [212] = {0xFCF83450U, 0x00000002U}, /* SEC_MODID[212]:AXIPCI104*/ + [213] = {0xFCF83454U, 0x00000002U}, /* SEC_MODID[213]:AXIPCI105*/ + [214] = {0xFCF83458U, 0x00000002U}, /* SEC_MODID[214]:AXIPCI106*/ + [215] = {0xFCF8345CU, 0x00000002U}, /* SEC_MODID[215]:AXIPCI107*/ + [216] = {0xFCF83460U, 0x00000002U}, /* SEC_MODID[216]:AXIPCI108*/ + [217] = {0xFCF83464U, 0x00000002U}, /* SEC_MODID[217]:AXIPCI109*/ + [218] = {0xFCF83468U, 0x00000002U}, /* SEC_MODID[218]:AXIPCI110*/ + [219] = {0xFCF8346CU, 0x00000002U}, /* SEC_MODID[219]:AXIPCI111*/ + [220] = {0xFCF83470U, 0x00000002U}, /* SEC_MODID[220]:AXIPCI112*/ + [221] = {0xFCF83474U, 0x00000002U}, /* SEC_MODID[221]:AXIPCI113*/ + [222] = {0xFCF83478U, 0x00000002U}, /* SEC_MODID[222]:AXIPCI114*/ + [223] = {0xFCF8347CU, 0x00000002U}, /* SEC_MODID[223]:AXIPCI115*/ + [224] = {0xFCF83484U, 0x00000002U}, /* SEC_MODID[224]:GPTP*/ + [225] = {0xFCF83488U, 0x00000002U}, /* SEC_MODID[225]:IPMMUHC00*/ + [226] = {0xFCF834F0U, 0x00000002U}, /* SEC_MODID[226]:TSN0*/ + [227] = {0xFCF834F4U, 0x00000002U}, /* SEC_MODID[227]:AXIPCI000*/ + [228] = {0xFCF834F8U, 0x00000002U}, /* SEC_MODID[228]:AXIPCI004*/ + [229] = {0xFCF834FCU, 0x00000002U}, /* SEC_MODID[229]:IPMMUHC01*/ + [230] = {0xFCF83500U, 0x00000002U}, /* SEC_MODID[230]:AVB0*/ + [231] = {0xFCF83504U, 0x00000002U}, /* SEC_MODID[231]:AVB1*/ + [232] = {0xFCF83508U, 0x00000002U}, /* SEC_MODID[232]:AVB2*/ + [233] = {0xFCF8350CU, 0x00000002U}, /* SEC_MODID[233]:IPMMUHC10*/ + [234] = {0xFCF83510U, 0x00000002U}, /* SEC_MODID[234]:IPMMUHC11*/ + [235] = {0xFCF83514U, 0x00000002U}, /* SEC_MODID[235]:IPMMUHC12*/ + [236] = {0xFCF83518U, 0x00000002U}, /* SEC_MODID[236]:IPMMUHC13*/ + [237] = {0xFCF8351CU, 0x00000002U}, /* SEC_MODID[237]:PPHY0*/ + [238] = {0xFCF83520U, 0x00000002U}, /* SEC_MODID[238]:PPHY1*/ + [239] = {0xFCF83524U, 0x00000002U}, /* SEC_MODID[239]:IPMMUHC14*/ + [240] = {0xFCF83528U, 0x00000002U}, /* SEC_MODID[240]:IPMMUHC15*/ + [241] = {0xFCF8352CU, 0x00000002U}, /* SEC_MODID[241]:FBAHSC*/ + [242] = {0xFCF83530U, 0x00000002U}, /* SEC_MODID[242]:IPMMUHC02*/ + [243] = {0xFCF83538U, 0x00000002U}, /* SEC_MODID[243]:ECMHSC*/ + [244] = {0xFCF8353CU, 0x00000002U}, /* SEC_MODID[244]:ARHC0*/ + [245] = {0xFCF83540U, 0x00000002U}, /* SEC_MODID[245]:ARHC1*/ + [246] = {0xFCF83544U, 0x00000002U}, /* SEC_MODID[246]:ARHC2*/ + [247] = {0xFCF83548U, 0x00000002U}, /* SEC_MODID[247]:ARHC3*/ + [248] = {0xFCF8354CU, 0x00000002U}, /* SEC_MODID[248]:ARHC4*/ + [249] = {0xFCF83550U, 0x00000002U}, /* SEC_MODID[249]:ARHC5*/ + [250] = {0xFCF83554U, 0x00000002U}, /* SEC_MODID[250]:ARHC6*/ + [251] = {0xFCF83558U, 0x00000002U}, /* SEC_MODID[251]:ARHC7*/ + [252] = {0xFCF8355CU, 0x00000002U}, /* SEC_MODID[252]:ARHC8*/ + [253] = {0xFCF83560U, 0x00000002U}, /* SEC_MODID[253]:IPMMUHC03*/ + [254] = {0xFCF83564U, 0x00000002U}, /* SEC_MODID[254]:IPMMUHC04*/ + [255] = {0xFCF83568U, 0x00000002U}, /* SEC_MODID[255]:IPMMUHC05*/ + [256] = {0xFCF8356CU, 0x00000002U}, /* SEC_MODID[256]:IPMMUHC06*/ + [257] = {0xFCF83570U, 0x00000002U}, /* SEC_MODID[257]:IPMMUHC07*/ + [258] = {0xFCF83574U, 0x00000002U}, /* SEC_MODID[258]:IPMMUHC08*/ + [259] = {0xFCF83578U, 0x00000002U}, /* SEC_MODID[259]:IPMMUHC09*/ + [260] = {0xFC883400U, 0x00000002U}, /* SEC_MODID[260]:ARIMP00*/ + [261] = {0xFC883404U, 0x00000002U}, /* SEC_MODID[261]:ARIMP01*/ + [262] = {0xFC883408U, 0x00000002U}, /* SEC_MODID[262]:ARIMP02*/ + [263] = {0xFC88340CU, 0x00000002U}, /* SEC_MODID[263]:ARIMP03*/ + [264] = {0xFC883410U, 0x00000002U}, /* SEC_MODID[264]:ARIMP04*/ + [265] = {0xFC883414U, 0x00000002U}, /* SEC_MODID[265]:AXIFBABUSIR0*/ + [266] = {0xFC883418U, 0x00000002U}, /* SEC_MODID[266]:AXIFBABUSIR1*/ + [267] = {0xFC88341CU, 0x00000002U}, /* SEC_MODID[267]:AXIFBABUSIR2*/ + [268] = {0xFC883420U, 0x00000002U}, /* SEC_MODID[268]:AXIFBABUSIR3*/ + [269] = {0xFC883424U, 0x00000002U}, /* SEC_MODID[269]:AXIFBABUSIR4*/ + [270] = {0xFC883428U, 0x00000002U}, /* SEC_MODID[270]:AXIIMP0*/ + [271] = {0xFC88342CU, 0x00000002U}, /* SEC_MODID[271]:CKMCNR*/ + [272] = {0xFC883430U, 0x00000002U}, /* SEC_MODID[272]:CKMDSP*/ + [273] = {0xFC883434U, 0x00000002U}, /* SEC_MODID[273]:ARIMP05*/ + [274] = {0xFC883438U, 0x00000002U}, /* SEC_MODID[274]:ARIMP06*/ + [275] = {0xFC88343CU, 0x00000002U}, /* SEC_MODID[275]:ARIMP07*/ + [276] = {0xFC883440U, 0x00000002U}, /* SEC_MODID[276]:ARIMP08*/ + [277] = {0xFC883444U, 0x00000002U}, /* SEC_MODID[277]:CKMIR*/ + [278] = {0xFC883448U, 0x00000002U}, /* SEC_MODID[278]:ECMIR*/ + [279] = {0xFC88344CU, 0x00000002U}, /* SEC_MODID[279]:DSPPS*/ + [280] = {0xFC883450U, 0x00000002U}, /* SEC_MODID[280]:IPMMUIR1*/ + [281] = {0xFC883454U, 0x00000002U}, /* SEC_MODID[281]:IPMMUIR0*/ + [282] = {0xFC883458U, 0x00000002U}, /* SEC_MODID[282]:IPMMUIR10*/ + [283] = {0xFC88345CU, 0x00000002U}, /* SEC_MODID[283]:IPMMUIR11*/ + [284] = {0xFC883460U, 0x00000002U}, /* SEC_MODID[284]:IPMMUIR12*/ + [285] = {0xFC883464U, 0x00000002U}, /* SEC_MODID[285]:IPMMUIR13*/ + [286] = {0xFC883468U, 0x00000002U}, /* SEC_MODID[286]:IPMMUIR14*/ + [287] = {0xFC88346CU, 0x00000002U}, /* SEC_MODID[287]:IPMMUIR15*/ + [288] = {0xFC883470U, 0x00000002U}, /* SEC_MODID[288]:IPMMUIR2*/ + [289] = {0xFC883474U, 0x00000002U}, /* SEC_MODID[289]:IPMMUIR3*/ + [290] = {0xFC883478U, 0x00000002U}, /* SEC_MODID[290]:IPMMUIR4*/ + [291] = {0xFC88347CU, 0x00000002U}, /* SEC_MODID[291]:IPMMUIR5*/ + [292] = {0xFC883480U, 0x00000002U}, /* SEC_MODID[292]:IPMMUIR6*/ + [293] = {0xFC883484U, 0x00000002U}, /* SEC_MODID[293]:IPMMUIR7*/ + [294] = {0xFC883488U, 0x00000002U}, /* SEC_MODID[294]:IPMMUIR8*/ + [295] = {0xFC88348CU, 0x00000002U}, /* SEC_MODID[295]:IPMMUIR9*/ + [296] = {0xFC013400U, 0x00000002U}, /* SEC_MODID[296]:ARPV0*/ + [297] = {0xFC013404U, 0x00000002U}, /* SEC_MODID[297]:ARPV1*/ + [298] = {0xFC013408U, 0x00000002U}, /* SEC_MODID[298]:AXIRGXS*/ + [299] = {0xFC01340CU, 0x00000002U}, /* SEC_MODID[299]:ARPV2*/ + [300] = {0xFC013410U, 0x00000002U}, /* SEC_MODID[300]:ARPV3*/ + [301] = {0xFC013414U, 0x00000002U}, /* SEC_MODID[301]:ARPV4*/ + [302] = {0xFC013418U, 0x00000002U}, /* SEC_MODID[302]:ARPV5*/ + [303] = {0xFC01341CU, 0x00000002U}, /* SEC_MODID[303]:ARPV6*/ + [304] = {0xFC013420U, 0x00000002U}, /* SEC_MODID[304]:ARPV7*/ + [305] = {0xFC013424U, 0x00000002U}, /* SEC_MODID[305]:ARPV8*/ + [306] = {0xFC013428U, 0x00000002U}, /* SEC_MODID[306]:CKM3DG*/ + [307] = {0xFC01342CU, 0x00000002U}, /* SEC_MODID[307]:ECM3DG*/ + [308] = {0xFC013430U, 0x00000002U}, /* SEC_MODID[308]:FBAPVC*/ + [309] = {0xFC013434U, 0x00000002U}, /* SEC_MODID[309]:FBAPVD0*/ + [310] = {0xFC013438U, 0x00000002U}, /* SEC_MODID[310]:FBAPVD1*/ + [311] = {0xFC01343CU, 0x00000002U}, /* SEC_MODID[311]:FBAPVD2*/ + [312] = {0xFC013440U, 0x00000002U}, /* SEC_MODID[312]:FBAPVE*/ + [313] = {0xFC013444U, 0x00000002U}, /* SEC_MODID[313]:IPMMUPV000*/ + [314] = {0xFC013448U, 0x00000002U}, /* SEC_MODID[314]:IPMMUPV001*/ + [315] = {0xFC01344CU, 0x00000002U}, /* SEC_MODID[315]:IPMMUPV010*/ + [316] = {0xFC013450U, 0x00000002U}, /* SEC_MODID[316]:IPMMUPV011*/ + [317] = {0xFC013454U, 0x00000002U}, /* SEC_MODID[317]:IPMMUPV012*/ + [318] = {0xFC013458U, 0x00000002U}, /* SEC_MODID[318]:IPMMUPV013*/ + [319] = {0xFC01345CU, 0x00000002U}, /* SEC_MODID[319]:IPMMUPV014*/ + [320] = {0xFC013460U, 0x00000002U}, /* SEC_MODID[320]:IPMMUPV015*/ + [321] = {0xFC013464U, 0x00000002U}, /* SEC_MODID[321]:IPMMUPV002*/ + [322] = {0xFC013468U, 0x00000002U}, /* SEC_MODID[322]:IPMMUPV003*/ + [323] = {0xFC01346CU, 0x00000002U}, /* SEC_MODID[323]:IPMMUPV004*/ + [324] = {0xFC013470U, 0x00000002U}, /* SEC_MODID[324]:IPMMUPV005*/ + [325] = {0xFC013474U, 0x00000002U}, /* SEC_MODID[325]:IPMMUPV006*/ + [326] = {0xFC013478U, 0x00000002U}, /* SEC_MODID[326]:IPMMUPV007*/ + [327] = {0xFC01347CU, 0x00000002U}, /* SEC_MODID[327]:IPMMUPV008*/ + [328] = {0xFC013480U, 0x00000002U}, /* SEC_MODID[328]:IPMMUPV009*/ + [329] = {0xFDC23400U, 0x00000002U}, /* SEC_MODID[329]:ARRC0*/ + [330] = {0xFDC23404U, 0x00000002U}, /* SEC_MODID[330]:ARRC1*/ + [331] = {0xFDC23408U, 0x00000002U}, /* SEC_MODID[331]:ARRC2*/ + [332] = {0xFDC2340CU, 0x00000002U}, /* SEC_MODID[332]:ARRC3*/ + [333] = {0xFDC23410U, 0x00000002U}, /* SEC_MODID[333]:ARRC4*/ + [334] = {0xFDC23414U, 0x00000002U}, /* SEC_MODID[334]:ARRC5*/ + [335] = {0xFDC23418U, 0x00000002U}, /* SEC_MODID[335]:ARRC6*/ + [336] = {0xFDC2341CU, 0x00000002U}, /* SEC_MODID[336]:ARRC7*/ + [337] = {0xFDC23420U, 0x00000002U}, /* SEC_MODID[337]:ARRC8*/ + [338] = {0xFDC23424U, 0x00000000U}, /* SEC_MODID[338]:CR0*/ + [339] = {0xFDC23428U, 0x00000002U}, /* SEC_MODID[339]:ICUMX*/ + [340] = {0xFDC2342CU, 0x00000002U}, /* SEC_MODID[340]:ECMRC*/ + [341] = {0xFD433400U, 0x00000002U}, /* SEC_MODID[341]:DMAWCRC0*/ + [342] = {0xFD433404U, 0x00000002U}, /* SEC_MODID[342]:DMAWCRC1*/ + [343] = {0xFD433408U, 0x00000002U}, /* SEC_MODID[343]:DMAWCRC2*/ + [344] = {0xFD43340CU, 0x00000002U}, /* SEC_MODID[344]:DMAWCRC3*/ + [345] = {0xFD443400U, 0x00000002U}, /* SEC_MODID[345]:ARMREG00*/ + [346] = {0xFD443404U, 0x00000002U}, /* SEC_MODID[346]:ARMREG01*/ + [347] = {0xFD443408U, 0x00000002U}, /* SEC_MODID[347]:ARMREG10*/ + [348] = {0xFD44340CU, 0x00000002U}, /* SEC_MODID[348]:ARMREG11*/ + [349] = {0xFD443410U, 0x00000002U}, /* SEC_MODID[349]:ARMREG12*/ + [350] = {0xFD443414U, 0x00000000U}, /* SEC_MODID[350]:ARMREG13*/ + [351] = {0xFD443418U, 0x00000000U}, /* SEC_MODID[351]:ARMREG14*/ + [352] = {0xFD44341CU, 0x00000002U}, /* SEC_MODID[352]:AXICR52SS0*/ + [353] = {0xFD443420U, 0x00000002U}, /* SEC_MODID[353]:AXICSD0*/ + [354] = {0xFD443424U, 0x00000002U}, /* SEC_MODID[354]:AXIINTAP0*/ + [355] = {0xFD443428U, 0x00000002U}, /* SEC_MODID[355]:AXIINTAP1*/ + [356] = {0xFD44342CU, 0x00000002U}, /* SEC_MODID[356]:AXISECROM*/ + [357] = {0xFD443430U, 0x00000002U}, /* SEC_MODID[357]:AXISYSRAM0*/ + [358] = {0xFD443434U, 0x00000002U}, /* SEC_MODID[358]:AXISYSRAM1*/ + [359] = {0xFD443438U, 0x00000002U}, /* SEC_MODID[359]:ARGREG15*/ + [360] = {0xFD44343CU, 0x00000002U}, /* SEC_MODID[360]:ARMREG2*/ + [361] = {0xFD443440U, 0x00000002U}, /* SEC_MODID[361]:ARMREG3*/ + [362] = {0xFD443444U, 0x00000002U}, /* SEC_MODID[362]:ARMREG4*/ + [363] = {0xFD443448U, 0x00000002U}, /* SEC_MODID[363]:ARMREG5*/ + [364] = {0xFD44344CU, 0x00000002U}, /* SEC_MODID[364]:ARMREG6*/ + [365] = {0xFD443450U, 0x00000002U}, /* SEC_MODID[365]:ARMREG7*/ + [366] = {0xFD443454U, 0x00000000U}, /* SEC_MODID[366]:ARMREG8*/ + [367] = {0xFD443458U, 0x00000000U}, /* SEC_MODID[367]:ARMREG9*/ + [368] = {0xFD44345CU, 0x00000002U}, /* SEC_MODID[368]:ARRD0*/ + [369] = {0xFD443460U, 0x00000002U}, /* SEC_MODID[369]:ARRD1*/ + [370] = {0xFD443464U, 0x00000002U}, /* SEC_MODID[370]:ARRD2*/ + [371] = {0xFD443468U, 0x00000002U}, /* SEC_MODID[371]:ARRD3*/ + [372] = {0xFD44346CU, 0x00000002U}, /* SEC_MODID[372]:ARRD4*/ + [373] = {0xFD443470U, 0x00000002U}, /* SEC_MODID[373]:ARRD5*/ + [374] = {0xFD443474U, 0x00000002U}, /* SEC_MODID[374]:ARRD6*/ + [375] = {0xFD443478U, 0x00000002U}, /* SEC_MODID[375]:ARRD7*/ + [376] = {0xFD44347CU, 0x00000002U}, /* SEC_MODID[376]:ARRD8*/ + [377] = {0xFD443480U, 0x00000002U}, /* SEC_MODID[377]:ARRT0*/ + [378] = {0xFD443484U, 0x00000002U}, /* SEC_MODID[378]:ARRT1*/ + [379] = {0xFD443488U, 0x00000002U}, /* SEC_MODID[379]:ARRT2*/ + [380] = {0xFD44348CU, 0x00000002U}, /* SEC_MODID[380]:ARRT3*/ + [381] = {0xFD443490U, 0x00000002U}, /* SEC_MODID[381]:ARRT4*/ + [382] = {0xFD443494U, 0x00000002U}, /* SEC_MODID[382]:ARRT5*/ + [383] = {0xFD443498U, 0x00000002U}, /* SEC_MODID[383]:ARRT6*/ + [384] = {0xFD44349CU, 0x00000002U}, /* SEC_MODID[384]:ARRT7*/ + [385] = {0xFD4434A0U, 0x00000002U}, /* SEC_MODID[385]:ARRT8*/ + [386] = {0xFD4434A4U, 0x00000002U}, /* SEC_MODID[386]:CKMRT*/ + [387] = {0xFD4434A8U, 0x00000002U}, /* SEC_MODID[387]:CRC0*/ + [388] = {0xFD4434ACU, 0x00000002U}, /* SEC_MODID[388]:CRC1*/ + [389] = {0xFD4434B0U, 0x00000002U}, /* SEC_MODID[389]:CRC2*/ + [390] = {0xFD4434B4U, 0x00000002U}, /* SEC_MODID[390]:CRC3*/ + [391] = {0xFD4434B8U, 0x00000002U}, /* SEC_MODID[391]:CSD*/ + [392] = {0xFD4434BCU, 0x00000002U}, /* SEC_MODID[392]:ECM*/ + [393] = {0xFD4434C0U, 0x00000002U}, /* SEC_MODID[393]:ECMRT*/ + [394] = {0xFD4434C4U, 0x00000002U}, /* SEC_MODID[394]:FBACR52*/ + [395] = {0xFD4434C8U, 0x00000002U}, /* SEC_MODID[395]:FBART*/ + [396] = {0xFD4434CCU, 0x00000002U}, /* SEC_MODID[396]:INTTP*/ + [397] = {0xFD4434D0U, 0x00000002U}, /* SEC_MODID[397]:IPMMURT000*/ + [398] = {0xFD4434D4U, 0x00000002U}, /* SEC_MODID[398]:IPMMURT100*/ + [399] = {0xFD4434D8U, 0x00000002U}, /* SEC_MODID[399]:KCRC4*/ + [400] = {0xFD4434DCU, 0x00000002U}, /* SEC_MODID[400]:KCRC5*/ + [401] = {0xFD4434E0U, 0x00000002U}, /* SEC_MODID[401]:KCRC6*/ + [402] = {0xFD4434E4U, 0x00000002U}, /* SEC_MODID[402]:KCRC7*/ + [403] = {0xFD4434E8U, 0x00000002U}, /* SEC_MODID[403]:MFI00*/ + [404] = {0xFD4434ECU, 0x00000002U}, /* SEC_MODID[404]:MFI01*/ + [405] = {0xFD4434F0U, 0x00000002U}, /* SEC_MODID[405]:MFI10*/ + [406] = {0xFD4434F4U, 0x00000002U}, /* SEC_MODID[406]:MFI02*/ + [407] = {0xFD4434F8U, 0x00000002U}, /* SEC_MODID[407]:MFI03*/ + [408] = {0xFD4434FCU, 0x00000002U}, /* SEC_MODID[408]:MFI04*/ + [409] = {0xFD443500U, 0x00000002U}, /* SEC_MODID[409]:MFI05*/ + [410] = {0xFD443504U, 0x00000002U}, /* SEC_MODID[410]:MFI06*/ + [411] = {0xFD443508U, 0x00000002U}, /* SEC_MODID[411]:MFI07*/ + [412] = {0xFD44350CU, 0x00000002U}, /* SEC_MODID[412]:MFI08*/ + [413] = {0xFD443510U, 0x00000002U}, /* SEC_MODID[413]:MFI09*/ + [414] = {0xFD443514U, 0x00000002U}, /* SEC_MODID[414]:MFI15*/ + [415] = {0xFD443518U, 0x00000002U}, /* SEC_MODID[415]:CKMCR52*/ + [416] = {0xFD44351CU, 0x00000002U}, /* SEC_MODID[416]:RTDM0P*/ + [417] = {0xFD443520U, 0x00000002U}, /* SEC_MODID[417]:ECMRD*/ + [418] = {0xFD443524U, 0x00000002U}, /* SEC_MODID[418]:RTDM1P*/ + [419] = {0xFD44352CU, 0x00000002U}, /* SEC_MODID[419]:RTDM2P*/ + [420] = {0xFD443530U, 0x00000002U}, /* SEC_MODID[420]:SYSRAM10*/ + [421] = {0xFD443534U, 0x00000002U}, /* SEC_MODID[421]:RTDM3P*/ + [422] = {0xFD443538U, 0x00000000U}, /* SEC_MODID[422]:SYSRAM00*/ + [423] = {0xFD44353CU, 0x00000002U}, /* SEC_MODID[423]:TSIPL0*/ + [424] = {0xFD443540U, 0x00000002U}, /* SEC_MODID[424]:TSIPL1*/ + [425] = {0xFD443544U, 0x00000002U}, /* SEC_MODID[425]:TSIPL2*/ + [426] = {0xFD443548U, 0x00000002U}, /* SEC_MODID[426]:TSIPL3*/ + [427] = {0xFD44354CU, 0x00000002U}, /* SEC_MODID[427]:TSIPL4*/ + [428] = {0xFD443550U, 0x00000002U}, /* SEC_MODID[428]:TSIPL5*/ + [429] = {0xFD443554U, 0x00000002U}, /* SEC_MODID[429]:TSIPL6*/ + [430] = {0xFD443558U, 0x00000002U}, /* SEC_MODID[430]:TSIPL7*/ + [431] = {0xFD44355CU, 0x00000002U}, /* SEC_MODID[431]:WCRC0*/ + [432] = {0xFD443560U, 0x00000002U}, /* SEC_MODID[432]:WCRC1*/ + [433] = {0xFD443564U, 0x00000002U}, /* SEC_MODID[433]:WCRC2*/ + [434] = {0xFD443568U, 0x00000002U}, /* SEC_MODID[434]:WCRC3*/ + [435] = {0xFD443580U, 0x00000002U}, /* SEC_MODID[435]:MFI11*/ + [436] = {0xFD443584U, 0x00000002U}, /* SEC_MODID[436]:MFI12*/ + [437] = {0xFD443588U, 0x00000002U}, /* SEC_MODID[437]:MFI13*/ + [438] = {0xFD44358CU, 0x00000002U}, /* SEC_MODID[438]:MFI14*/ + [439] = {0xFD443590U, 0x00000002U}, /* SEC_MODID[439]:IPMMURT001*/ + [440] = {0xFD443594U, 0x00000002U}, /* SEC_MODID[440]:IPMMURT010*/ + [441] = {0xFD443598U, 0x00000002U}, /* SEC_MODID[441]:IPMMURT011*/ + [442] = {0xFD44359CU, 0x00000002U}, /* SEC_MODID[442]:IPMMURT012*/ + [443] = {0xFD4435A0U, 0x00000002U}, /* SEC_MODID[443]:IPMMURT013*/ + [444] = {0xFD4435A4U, 0x00000002U}, /* SEC_MODID[444]:IPMMURT014*/ + [445] = {0xFD4435A8U, 0x00000002U}, /* SEC_MODID[445]:IPMMURT015*/ + [446] = {0xFD4435ACU, 0x00000002U}, /* SEC_MODID[446]:IPMMURT002*/ + [447] = {0xFD4435B0U, 0x00000002U}, /* SEC_MODID[447]:IPMMURT003*/ + [448] = {0xFD4435B4U, 0x00000002U}, /* SEC_MODID[448]:IPMMURT004*/ + [449] = {0xFD4435B8U, 0x00000002U}, /* SEC_MODID[449]:IPMMURT005*/ + [450] = {0xFD4435BCU, 0x00000002U}, /* SEC_MODID[450]:IPMMURT006*/ + [451] = {0xFD4435C0U, 0x00000002U}, /* SEC_MODID[451]:IPMMURT007*/ + [452] = {0xFD4435C4U, 0x00000002U}, /* SEC_MODID[452]:IPMMURT008*/ + [453] = {0xFD4435C8U, 0x00000002U}, /* SEC_MODID[453]:IPMMURT009*/ + [454] = {0xFD4435CCU, 0x00000002U}, /* SEC_MODID[454]:IPKMURT101*/ + [455] = {0xFD4435D0U, 0x00000002U}, /* SEC_MODID[455]:IPMMURT110*/ + [456] = {0xFD4435D4U, 0x00000002U}, /* SEC_MODID[456]:IPMMURT111*/ + [457] = {0xFD4435D8U, 0x00000002U}, /* SEC_MODID[457]:IPMMURT112*/ + [458] = {0xFD4435DCU, 0x00000002U}, /* SEC_MODID[458]:IPMMURT113*/ + [459] = {0xFD4435E0U, 0x00000002U}, /* SEC_MODID[459]:IPMMURT114*/ + [460] = {0xFD4435E4U, 0x00000002U}, /* SEC_MODID[460]:IPMMURT115*/ + [461] = {0xFD4435E8U, 0x00000002U}, /* SEC_MODID[461]:IPMMURT102*/ + [462] = {0xFD4435ECU, 0x00000002U}, /* SEC_MODID[462]:IPMMURT103*/ + [463] = {0xFD4435F0U, 0x00000002U}, /* SEC_MODID[463]:IPMMURT104*/ + [464] = {0xFD4435F4U, 0x00000002U}, /* SEC_MODID[464]:IPMMURT105*/ + [465] = {0xFD4435F8U, 0x00000002U}, /* SEC_MODID[465]:IPMMURT106*/ + [466] = {0xFD4435FCU, 0x00000002U}, /* SEC_MODID[466]:IPMMURT107*/ + [467] = {0xFD443600U, 0x00000002U}, /* SEC_MODID[467]:RTDM000*/ + [468] = {0xFD443604U, 0x00000002U}, /* SEC_MODID[468]:RTDM001*/ + [469] = {0xFD443608U, 0x00000002U}, /* SEC_MODID[469]:RTDM010*/ + [470] = {0xFD44360CU, 0x00000002U}, /* SEC_MODID[470]:RTDM011*/ + [471] = {0xFD443610U, 0x00000002U}, /* SEC_MODID[471]:RTDM012*/ + [472] = {0xFD443614U, 0x00000002U}, /* SEC_MODID[472]:RTDM013*/ + [473] = {0xFD443618U, 0x00000002U}, /* SEC_MODID[473]:RTDM014*/ + [474] = {0xFD44361CU, 0x00000002U}, /* SEC_MODID[474]:RTDM015*/ + [475] = {0xFD443620U, 0x00000002U}, /* SEC_MODID[475]:RTDM002*/ + [476] = {0xFD443624U, 0x00000002U}, /* SEC_MODID[476]:RTDM003*/ + [477] = {0xFD443628U, 0x00000002U}, /* SEC_MODID[477]:RTDM004*/ + [478] = {0xFD44362CU, 0x00000002U}, /* SEC_MODID[478]:RTDM005*/ + [479] = {0xFD443630U, 0x00000002U}, /* SEC_MODID[479]:RTDM006*/ + [480] = {0xFD443634U, 0x00000002U}, /* SEC_MODID[480]:RTDM007*/ + [481] = {0xFD443638U, 0x00000002U}, /* SEC_MODID[481]:RTDM008*/ + [482] = {0xFD44363CU, 0x00000002U}, /* SEC_MODID[482]:RTDM009*/ + [483] = {0xFD443640U, 0x00000002U}, /* SEC_MODID[483]:RTDM100*/ + [484] = {0xFD443644U, 0x00000002U}, /* SEC_MODID[484]:RTDM101*/ + [485] = {0xFD443648U, 0x00000002U}, /* SEC_MODID[485]:RTDM110*/ + [486] = {0xFD44364CU, 0x00000002U}, /* SEC_MODID[486]:RTDM111*/ + [487] = {0xFD443650U, 0x00000002U}, /* SEC_MODID[487]:RTDM112*/ + [488] = {0xFD443654U, 0x00000002U}, /* SEC_MODID[488]:RTDM113*/ + [489] = {0xFD443658U, 0x00000002U}, /* SEC_MODID[489]:RTDM114*/ + [490] = {0xFD44365CU, 0x00000002U}, /* SEC_MODID[490]:RTDM115*/ + [491] = {0xFD443660U, 0x00000002U}, /* SEC_MODID[491]:RTDM102*/ + [492] = {0xFD443664U, 0x00000002U}, /* SEC_MODID[492]:RTDM103*/ + [493] = {0xFD443668U, 0x00000002U}, /* SEC_MODID[493]:RTDM104*/ + [494] = {0xFD44366CU, 0x00000002U}, /* SEC_MODID[494]:RTDM105*/ + [495] = {0xFD443670U, 0x00000002U}, /* SEC_MODID[495]:RTDM106*/ + [496] = {0xFD443674U, 0x00000002U}, /* SEC_MODID[496]:RTDM107*/ + [497] = {0xFD443678U, 0x00000002U}, /* SEC_MODID[497]:RTDM108*/ + [498] = {0xFD44367CU, 0x00000002U}, /* SEC_MODID[498]:RTDM109*/ + [499] = {0xFD443680U, 0x00000002U}, /* SEC_MODID[499]:RTDM200*/ + [500] = {0xFD443684U, 0x00000002U}, /* SEC_MODID[500]:RTDM201*/ + [501] = {0xFD443688U, 0x00000002U}, /* SEC_MODID[501]:RTDM210*/ + [502] = {0xFD44368CU, 0x00000002U}, /* SEC_MODID[502]:RTDM211*/ + [503] = {0xFD443690U, 0x00000002U}, /* SEC_MODID[503]:RTDM212*/ + [504] = {0xFD443694U, 0x00000002U}, /* SEC_MODID[504]:RTDM213*/ + [505] = {0xFD443698U, 0x00000002U}, /* SEC_MODID[505]:RTDM214*/ + [506] = {0xFD44369CU, 0x00000002U}, /* SEC_MODID[506]:RTDM215*/ + [507] = {0xFD4436A0U, 0x00000002U}, /* SEC_MODID[507]:RTDM202*/ + [508] = {0xFD4436A4U, 0x00000002U}, /* SEC_MODID[508]:RTDM203*/ + [509] = {0xFD4436A8U, 0x00000002U}, /* SEC_MODID[509]:RTDM204*/ + [510] = {0xFD4436ACU, 0x00000002U}, /* SEC_MODID[510]:RTDM205*/ + [511] = {0xFD4436B0U, 0x00000002U}, /* SEC_MODID[511]:RTDM206*/ + [512] = {0xFD4436B4U, 0x00000002U}, /* SEC_MODID[512]:RTDM207*/ + [513] = {0xFD4436B8U, 0x00000002U}, /* SEC_MODID[513]:RTDM208*/ + [514] = {0xFD4436BCU, 0x00000002U}, /* SEC_MODID[514]:RTDM209*/ + [515] = {0xFD4436C0U, 0x00000002U}, /* SEC_MODID[515]:RTDM300*/ + [516] = {0xFD4436C4U, 0x00000002U}, /* SEC_MODID[516]:RTDM301*/ + [517] = {0xFD4436C8U, 0x00000002U}, /* SEC_MODID[517]:RTDM310*/ + [518] = {0xFD4436CCU, 0x00000002U}, /* SEC_MODID[518]:RTDM311*/ + [519] = {0xFD4436D0U, 0x00000002U}, /* SEC_MODID[519]:RTDM312*/ + [520] = {0xFD4436D4U, 0x00000002U}, /* SEC_MODID[520]:RTDM313*/ + [521] = {0xFD4436D8U, 0x00000002U}, /* SEC_MODID[521]:RTDM314*/ + [522] = {0xFD4436DCU, 0x00000002U}, /* SEC_MODID[522]:RTDM315*/ + [523] = {0xFD4436E0U, 0x00000002U}, /* SEC_MODID[523]:RTDM302*/ + [524] = {0xFD4436E4U, 0x00000002U}, /* SEC_MODID[524]:RTDM303*/ + [525] = {0xFD4436E8U, 0x00000002U}, /* SEC_MODID[525]:RTDM304*/ + [526] = {0xFD4436ECU, 0x00000002U}, /* SEC_MODID[526]:RTDM305*/ + [527] = {0xFD4436F0U, 0x00000002U}, /* SEC_MODID[527]:RTDM306*/ + [528] = {0xFD4436F4U, 0x00000002U}, /* SEC_MODID[528]:RTDM307*/ + [529] = {0xFD4436F8U, 0x00000002U}, /* SEC_MODID[529]:RTDM308*/ + [530] = {0xFD4436FCU, 0x00000002U}, /* SEC_MODID[530]:RTDM309*/ + [531] = {0xFD443700U, 0x00000002U}, /* SEC_MODID[531]:IPMMURT108*/ + [532] = {0xFD443704U, 0x00000002U}, /* SEC_MODID[532]:IPMMURT109*/ + [533] = {0xFD443708U, 0x00000000U}, /* SEC_MODID[533]:SYSRAM01*/ + [534] = {0xFD44370CU, 0x00000002U}, /* SEC_MODID[534]:SYSRAM02*/ + [535] = {0xFD443710U, 0x00000000U}, /* SEC_MODID[535]:SYSRAM03*/ + [536] = {0xFD443714U, 0x00000000U}, /* SEC_MODID[536]:SYSRAM04*/ + [537] = {0xFD443718U, 0x00000000U}, /* SEC_MODID[537]:SYSRAM05*/ + [538] = {0xFD44371CU, 0x00000000U}, /* SEC_MODID[538]:SYSRAM06*/ + [539] = {0xFD443720U, 0x00000002U}, /* SEC_MODID[539]:SYSRAM07*/ + [540] = {0xFD443724U, 0x00000002U}, /* SEC_MODID[540]:SYSRAM11*/ + [541] = {0xFD443728U, 0x00000002U}, /* SEC_MODID[541]:SYSRAM12*/ + [542] = {0xFD44372CU, 0x00000002U}, /* SEC_MODID[542]:SYSRAM13*/ + [543] = {0xFD443730U, 0x00000002U}, /* SEC_MODID[543]:SYSRAM14*/ + [544] = {0xFD443734U, 0x00000002U}, /* SEC_MODID[544]:SYSRAM15*/ + [545] = {0xFD443738U, 0x00000002U}, /* SEC_MODID[545]:SYSRAM16*/ + [546] = {0xFD44373CU, 0x00000002U}, /* SEC_MODID[546]:SYSRAM17*/ + [547] = {0xFD443760U, 0x00000002U}, /* SEC_MODID[547]:BKBUF*/ + [548] = {0xFD443764U, 0x00000002U}, /* SEC_MODID[548]:AXICR52SS1*/ + [549] = {0xFD443768U, 0x00000002U}, /* SEC_MODID[549]:AXICR52SS2*/ + [550] = {0xFC863400U, 0x00000002U}, /* SEC_MODID[550]:ARSC0*/ + [551] = {0xFC863404U, 0x00000002U}, /* SEC_MODID[551]:ARSC1*/ + [552] = {0xFC863408U, 0x00000002U}, /* SEC_MODID[552]:ARSC2*/ + [553] = {0xFC86340CU, 0x00000002U}, /* SEC_MODID[553]:ARSC3*/ + [554] = {0xFC863410U, 0x00000002U}, /* SEC_MODID[554]:ARSC4*/ + [555] = {0xFC863414U, 0x00000002U}, /* SEC_MODID[555]:ARSC5*/ + [556] = {0xFC863418U, 0x00000002U}, /* SEC_MODID[556]:ARSC6*/ + [557] = {0xFC86341CU, 0x00000002U}, /* SEC_MODID[557]:ARSC7*/ + [558] = {0xFC863420U, 0x00000002U}, /* SEC_MODID[558]:ARSC8*/ + [559] = {0xFC863424U, 0x00000002U}, /* SEC_MODID[559]:ARSTM0*/ + [560] = {0xFC863428U, 0x00000002U}, /* SEC_MODID[560]:ARSTM1*/ + [561] = {0xFC86342CU, 0x00000002U}, /* SEC_MODID[561]:CSD1S*/ + [562] = {0xFC863430U, 0x00000002U}, /* SEC_MODID[562]:AXIFBABUSTOP0*/ + [563] = {0xFC863434U, 0x00000002U}, /* SEC_MODID[563]:AXIFBABUSTOP1*/ + [564] = {0xFC863438U, 0x00000002U}, /* SEC_MODID[564]:ARSTM2*/ + [565] = {0xFC86343CU, 0x00000002U}, /* SEC_MODID[565]:ARSTM3*/ + [566] = {0xFC863440U, 0x00000002U}, /* SEC_MODID[566]:ARSTM4*/ + [567] = {0xFC863444U, 0x00000002U}, /* SEC_MODID[567]:ARSTM5*/ + [568] = {0xFC863448U, 0x00000002U}, /* SEC_MODID[568]:ARSTM6*/ + [569] = {0xFC86344CU, 0x00000002U}, /* SEC_MODID[569]:ARSTM7*/ + [570] = {0xFC863450U, 0x00000002U}, /* SEC_MODID[570]:ARSTM8*/ + [571] = {0xFC863454U, 0x00000002U}, /* SEC_MODID[571]:ECMTOP*/ + [572] = {0xFC863458U, 0x00000002U}, /* SEC_MODID[572]:FBA*/ + [573] = {0xFC86345CU, 0x00000002U}, /* SEC_MODID[573]:FBC*/ + [574] = {0xFC863460U, 0x00000002U}, /* SEC_MODID[574]:AXICCI00*/ + [575] = {0xFC863464U, 0x00000002U}, /* SEC_MODID[575]:AXICCI01*/ + [576] = {0xFC863468U, 0x00000002U}, /* SEC_MODID[576]:AXICCI10*/ + [577] = {0xFC86346CU, 0x00000002U}, /* SEC_MODID[577]:AXICCI11*/ + [578] = {0xFC863470U, 0x00000002U}, /* SEC_MODID[578]:AXICCI12*/ + [579] = {0xFC863474U, 0x00000002U}, /* SEC_MODID[579]:AXICCI13*/ + [580] = {0xFC863478U, 0x00000002U}, /* SEC_MODID[580]:AXICCI14*/ + [581] = {0xFC86347CU, 0x00000002U}, /* SEC_MODID[581]:AXICCI15*/ + [582] = {0xFC863480U, 0x00000002U}, /* SEC_MODID[582]:AXICCI2*/ + [583] = {0xFC863484U, 0x00000002U}, /* SEC_MODID[583]:AXICCI3*/ + [584] = {0xFC863488U, 0x00000002U}, /* SEC_MODID[584]:AXICCI4*/ + [585] = {0xFC86348CU, 0x00000002U}, /* SEC_MODID[585]:AXICCI5*/ + [586] = {0xFC863490U, 0x00000002U}, /* SEC_MODID[586]:AXICCI6*/ + [587] = {0xFC863494U, 0x00000002U}, /* SEC_MODID[587]:AXICCI7*/ + [588] = {0xFC863498U, 0x00000002U}, /* SEC_MODID[588]:AXICCI8*/ + [589] = {0xFC86349CU, 0x00000002U}, /* SEC_MODID[589]:AXICCI9*/ + [590] = {0xFC8634A0U, 0x00000002U}, /* SEC_MODID[590]:ECMSTM*/ + [591] = {0xFCB83400U, 0x00000002U}, /* SEC_MODID[591]:DMASSI00*/ + [592] = {0xFCB83404U, 0x00000002U}, /* SEC_MODID[592]:DMASSI01*/ + [593] = {0xFCB83408U, 0x00000002U}, /* SEC_MODID[593]:DMASSI02*/ + [594] = {0xFCB8340CU, 0x00000002U}, /* SEC_MODID[594]:DMASSI03*/ + [595] = {0xFCB83410U, 0x00000002U}, /* SEC_MODID[595]:DMASSI04*/ + [596] = {0xFCB83414U, 0x00000002U}, /* SEC_MODID[596]:DMAI2C0*/ + [597] = {0xFCB83418U, 0x00000002U}, /* SEC_MODID[597]:DMAI2C1*/ + [598] = {0xFCB8341CU, 0x00000002U}, /* SEC_MODID[598]:DMAI2C2*/ + [599] = {0xFCB83420U, 0x00000002U}, /* SEC_MODID[599]:DMAI2C3*/ + [600] = {0xFCB83424U, 0x00000002U}, /* SEC_MODID[600]:DMAI2C4*/ + [601] = {0xFCB83428U, 0x00000002U}, /* SEC_MODID[601]:DMAI2C5*/ + [602] = {0xFCB8342CU, 0x00000002U}, /* SEC_MODID[602]:DMASSI05*/ + [603] = {0xFCB83430U, 0x00000002U}, /* SEC_MODID[603]:DMASSI06*/ + [604] = {0xFCB83434U, 0x00000002U}, /* SEC_MODID[604]:DMASSI07*/ + [605] = {0xFDDC3400U, 0x00000002U}, /* SEC_MODID[605]:ARMM*/ + [606] = {0xFDDC3404U, 0x00000002U}, /* SEC_MODID[606]:AXIARNMM*/ + [607] = {0xFDDC3408U, 0x00000002U}, /* SEC_MODID[607]:ARSM0*/ + [608] = {0xFDDC340CU, 0x00000002U}, /* SEC_MODID[608]:ARSM1*/ + [609] = {0xFDDC3410U, 0x00000002U}, /* SEC_MODID[609]:ARSM2*/ + [610] = {0xFDDC3414U, 0x00000002U}, /* SEC_MODID[610]:AXIQOS0*/ + [611] = {0xFDDC3418U, 0x00000002U}, /* SEC_MODID[611]:AXIQOS1*/ + [612] = {0xFDDC341CU, 0x00000002U}, /* SEC_MODID[612]:AXIQOS2*/ + [613] = {0xFDDC3420U, 0x00000002U}, /* SEC_MODID[613]:AXIQOS3*/ + [614] = {0xFDDC3424U, 0x00000002U}, /* SEC_MODID[614]:AXIQOS4*/ + [615] = {0xFDDC3428U, 0x00000002U}, /* SEC_MODID[615]:AXIQOS5*/ + [616] = {0xFDDC342CU, 0x00000002U}, /* SEC_MODID[616]:AXIQOS6*/ + [617] = {0xFDDC3430U, 0x00000002U}, /* SEC_MODID[617]:AXIQOS7*/ + [618] = {0xFDDC3434U, 0x00000002U}, /* SEC_MODID[618]:ARSM3*/ + [619] = {0xFDDC3438U, 0x00000002U}, /* SEC_MODID[619]:ARSM4*/ + [620] = {0xFDDC343CU, 0x00000002U}, /* SEC_MODID[620]:ARSM5*/ + [621] = {0xFDDC3440U, 0x00000002U}, /* SEC_MODID[621]:ARSM6*/ + [622] = {0xFDDC3444U, 0x00000002U}, /* SEC_MODID[622]:ARSM7*/ + [623] = {0xFDDC3448U, 0x00000002U}, /* SEC_MODID[623]:ARSM8*/ + [624] = {0xFDDC344CU, 0x00000000U}, /* SEC_MODID[624]:AXMM0*/ + [625] = {0xFDDC3450U, 0x00000000U}, /* SEC_MODID[625]:AXMM1*/ + [626] = {0xFDDC3454U, 0x00000002U}, /* SEC_MODID[626]:AXMMPMON*/ + [627] = {0xFDDC3458U, 0x00000002U}, /* SEC_MODID[627]:CKMMM*/ + [628] = {0xFDDC345CU, 0x00000002U}, /* SEC_MODID[628]:ECMMM*/ + [629] = {0xFDDC3460U, 0x00000002U}, /* SEC_MODID[629]:FBADBSC0*/ + [630] = {0xFDDC3464U, 0x00000002U}, /* SEC_MODID[630]:FBADBSC1*/ + [631] = {0xFDDC3468U, 0x00000002U}, /* SEC_MODID[631]:FBAMM*/ + [632] = {0xFDDC346CU, 0x00000002U}, /* SEC_MODID[632]:IPMMUMM00*/ + [633] = {0xFDDC3470U, 0x00000002U}, /* SEC_MODID[633]:DBS0A0*/ + [634] = {0xFDDC3474U, 0x00000002U}, /* SEC_MODID[634]:DBS0A1*/ + [635] = {0xFDDC3478U, 0x00000002U}, /* SEC_MODID[635]:DBS1A0*/ + [636] = {0xFDDC347CU, 0x00000002U}, /* SEC_MODID[636]:DBS1A1*/ + [637] = {0xFDDC3480U, 0x00000002U}, /* SEC_MODID[637]:AXCIDBS*/ + [638] = {0xFDDC3484U, 0x00000002U}, /* SEC_MODID[638]:FCPRC*/ + [639] = {0xFDDC3488U, 0x00000002U}, /* SEC_MODID[639]:DBS0D0*/ + [640] = {0xFDDC348CU, 0x00000002U}, /* SEC_MODID[640]:DBS0D1*/ + [641] = {0xFDDC3490U, 0x00000002U}, /* SEC_MODID[641]:DBS1D0*/ + [642] = {0xFDDC3494U, 0x00000002U}, /* SEC_MODID[642]:DBS1D1*/ + [643] = {0xFDDC3498U, 0x00000002U}, /* SEC_MODID[643]:FBADDR*/ + [644] = {0xFDDC349CU, 0x00000002U}, /* SEC_MODID[644]:IPMMUMM01*/ + [645] = {0xFDDC34A0U, 0x00000002U}, /* SEC_MODID[645]:IPMMUMM10*/ + [646] = {0xFDDC34A4U, 0x00000002U}, /* SEC_MODID[646]:IPMMUMM11*/ + [647] = {0xFDDC34A8U, 0x00000002U}, /* SEC_MODID[647]:IPMMUMM12*/ + [648] = {0xFDDC34ACU, 0x00000002U}, /* SEC_MODID[648]:IPMMUMM13*/ + [649] = {0xFDDC34B0U, 0x00000002U}, /* SEC_MODID[649]:IPMMUMM14*/ + [650] = {0xFDDC34B4U, 0x00000002U}, /* SEC_MODID[650]:IPMMUMM15*/ + [651] = {0xFDDC34B8U, 0x00000002U}, /* SEC_MODID[651]:IPMMUMM02*/ + [652] = {0xFDDC34BCU, 0x00000002U}, /* SEC_MODID[652]:IPMMUMM03*/ + [653] = {0xFDDC34C0U, 0x00000002U}, /* SEC_MODID[653]:IPMMUMM04*/ + [654] = {0xFDDC34C4U, 0x00000002U}, /* SEC_MODID[654]:IPMMUMM05*/ + [655] = {0xFDDC34C8U, 0x00000002U}, /* SEC_MODID[655]:IPMMUMM06*/ + [656] = {0xFDDC34CCU, 0x00000002U}, /* SEC_MODID[656]:IPMMUMM07*/ + [657] = {0xFDDC34D0U, 0x00000002U}, /* SEC_MODID[657]:IPMMUMM08*/ + [658] = {0xFDDC34D4U, 0x00000002U}, /* SEC_MODID[658]:IPMMUMM09*/ + [659] = {0xFC803400U, 0x00000002U}, /* SEC_MODID[659]:ARSN0*/ + [660] = {0xFC803404U, 0x00000002U}, /* SEC_MODID[660]:ARSN1*/ + [661] = {0xFC803408U, 0x00000002U}, /* SEC_MODID[661]:ARSN2*/ + [662] = {0xFC80340CU, 0x00000002U}, /* SEC_MODID[662]:ARSN3*/ + [663] = {0xFC803410U, 0x00000002U}, /* SEC_MODID[663]:ARSN4*/ + [664] = {0xFC803414U, 0x00000002U}, /* SEC_MODID[664]:ARSN5*/ + [665] = {0xFC803418U, 0x00000002U}, /* SEC_MODID[665]:ARSN6*/ + [666] = {0xFC80341CU, 0x00000002U}, /* SEC_MODID[666]:ARSN7*/ + [667] = {0xFC803420U, 0x00000002U}, /* SEC_MODID[667]:ARSN8*/ + [668] = {0xFC803424U, 0x00000002U}, /* SEC_MODID[668]:ECMTOP3*/ + [669] = {0xFCB53400U, 0x00000002U}, /* SEC_MODID[669]:ARSD00*/ + [670] = {0xFCB53404U, 0x00000002U}, /* SEC_MODID[670]:ARSD01*/ + [671] = {0xFCB53408U, 0x00000002U}, /* SEC_MODID[671]:ARSD02*/ + [672] = {0xFCB5340CU, 0x00000002U}, /* SEC_MODID[672]:ARSD03*/ + [673] = {0xFCB53410U, 0x00000002U}, /* SEC_MODID[673]:ARSD04*/ + [674] = {0xFCB53414U, 0x00000002U}, /* SEC_MODID[674]:ARSD05*/ + [675] = {0xFCB53418U, 0x00000002U}, /* SEC_MODID[675]:ARSD06*/ + [676] = {0xFCB5341CU, 0x00000002U}, /* SEC_MODID[676]:AXIFRAY*/ + [677] = {0xFCB53420U, 0x00000002U}, /* SEC_MODID[677]:AXIIPC*/ + [678] = {0xFCB53428U, 0x00000002U}, /* SEC_MODID[678]:AXIRPC*/ + [679] = {0xFCB5342CU, 0x00000002U}, /* SEC_MODID[679]:AXISDHI0*/ + [680] = {0xFCB53430U, 0x00000002U}, /* SEC_MODID[680]:ARSD07*/ + [681] = {0xFCB53434U, 0x00000002U}, /* SEC_MODID[681]:ARSD08*/ + [682] = {0xFCB53438U, 0x00000002U}, /* SEC_MODID[682]:ARSP00*/ + [683] = {0xFCB5343CU, 0x00000002U}, /* SEC_MODID[683]:ARSP01*/ + [684] = {0xFCB53440U, 0x00000002U}, /* SEC_MODID[684]:ARSP02*/ + [685] = {0xFCB53444U, 0x00000002U}, /* SEC_MODID[685]:ARSP03*/ + [686] = {0xFCB53448U, 0x00000002U}, /* SEC_MODID[686]:ARSP04*/ + [687] = {0xFCB5344CU, 0x00000002U}, /* SEC_MODID[687]:ARSP05*/ + [688] = {0xFCB53450U, 0x00000002U}, /* SEC_MODID[688]:ARSP06*/ + [689] = {0xFCB53454U, 0x00000002U}, /* SEC_MODID[689]:ARSP07*/ + [690] = {0xFCB53458U, 0x00000002U}, /* SEC_MODID[690]:ARSP08*/ + [691] = {0xFCB5345CU, 0x00000002U}, /* SEC_MODID[691]:IPMMUDS001*/ + [692] = {0xFCB53460U, 0x00000002U}, /* SEC_MODID[692]:CKMPER0*/ + [693] = {0xFCB53464U, 0x00000002U}, /* SEC_MODID[693]:ECMPER0*/ + [694] = {0xFCB53468U, 0x00000002U}, /* SEC_MODID[694]:FBAPER0*/ + [695] = {0xFCB5346CU, 0x00000002U}, /* SEC_MODID[695]:FSO0*/ + [696] = {0xFCB53470U, 0x00000002U}, /* SEC_MODID[696]:FSO1*/ + [697] = {0xFCB53474U, 0x00000002U}, /* SEC_MODID[697]:FSO10*/ + [698] = {0xFCB53478U, 0x00000002U}, /* SEC_MODID[698]:FSO2*/ + [699] = {0xFCB5347CU, 0x00000002U}, /* SEC_MODID[699]:FSO3*/ + [700] = {0xFCB53480U, 0x00000002U}, /* SEC_MODID[700]:FSO4*/ + [701] = {0xFCB53484U, 0x00000002U}, /* SEC_MODID[701]:FSO5*/ + [702] = {0xFCB53488U, 0x00000002U}, /* SEC_MODID[702]:FSO6*/ + [703] = {0xFCB5348CU, 0x00000002U}, /* SEC_MODID[703]:FSO7*/ + [704] = {0xFCB53490U, 0x00000002U}, /* SEC_MODID[704]:FSO8*/ + [705] = {0xFCB53494U, 0x00000002U}, /* SEC_MODID[705]:FSO9*/ + [706] = {0xFCB53498U, 0x00000002U}, /* SEC_MODID[706]:ADG*/ + [707] = {0xFCB5349CU, 0x00000002U}, /* SEC_MODID[707]:ECMSD0*/ + [708] = {0xFCB534A0U, 0x00000002U}, /* SEC_MODID[708]:IPMMUDS010*/ + [709] = {0xFCB534A4U, 0x00000002U}, /* SEC_MODID[709]:IPMMUDS011*/ + [710] = {0xFCB534A8U, 0x00000002U}, /* SEC_MODID[710]:I2C0*/ + [711] = {0xFCB534ACU, 0x00000002U}, /* SEC_MODID[711]:I2C1*/ + [712] = {0xFCB534B0U, 0x00000002U}, /* SEC_MODID[712]:I2C2*/ + [713] = {0xFCB534B4U, 0x00000002U}, /* SEC_MODID[713]:I2C3*/ + [714] = {0xFCB534B8U, 0x00000002U}, /* SEC_MODID[714]:I2C4*/ + [715] = {0xFCB534BCU, 0x00000002U}, /* SEC_MODID[715]:I2C5*/ + [716] = {0xFCB534C0U, 0x00000002U}, /* SEC_MODID[716]:IPMMUDS012*/ + [717] = {0xFCB534C4U, 0x00000002U}, /* SEC_MODID[717]:IPC*/ + [718] = {0xFCB534C8U, 0x00000002U}, /* SEC_MODID[718]:IPMMUDS000*/ + [719] = {0xFCB534CCU, 0x00000002U}, /* SEC_MODID[719]:IPMMUDS013*/ + [720] = {0xFCB534D0U, 0x00000002U}, /* SEC_MODID[720]:IPMMUDS014*/ + [721] = {0xFCB534D4U, 0x00000002U}, /* SEC_MODID[721]:IPMMUDS015*/ + [722] = {0xFCB534D8U, 0x00000002U}, /* SEC_MODID[722]:IPMMUDS002*/ + [723] = {0xFCB534DCU, 0x00000002U}, /* SEC_MODID[723]:IPMMUDS003*/ + [724] = {0xFCB534E0U, 0x00000002U}, /* SEC_MODID[724]:IPMMUDS004*/ + [725] = {0xFCB534E4U, 0x00000002U}, /* SEC_MODID[725]:IPMMUDS005*/ + [726] = {0xFCB534E8U, 0x00000002U}, /* SEC_MODID[726]:SSI*/ + [727] = {0xFCB534ECU, 0x00000002U}, /* SEC_MODID[727]:IPMMUDS006*/ + [728] = {0xFCB534F0U, 0x00000002U}, /* SEC_MODID[728]:IPMMUDS007*/ + [729] = {0xFCB534F4U, 0x00000002U}, /* SEC_MODID[729]:SYDM1P*/ + [730] = {0xFCB534F8U, 0x00000002U}, /* SEC_MODID[730]:IPMMUDS008*/ + [731] = {0xFCB534FCU, 0x00000002U}, /* SEC_MODID[731]:SYDM2P*/ + [732] = {0xFCB53500U, 0x00000002U}, /* SEC_MODID[732]:IPMMUDS009*/ + [733] = {0xFCB53640U, 0x00000002U}, /* SEC_MODID[733]:SYDM100*/ + [734] = {0xFCB53644U, 0x00000002U}, /* SEC_MODID[734]:SYDM101*/ + [735] = {0xFCB53648U, 0x00000002U}, /* SEC_MODID[735]:SYDM110*/ + [736] = {0xFCB5364CU, 0x00000002U}, /* SEC_MODID[736]:SYDM111*/ + [737] = {0xFCB53650U, 0x00000002U}, /* SEC_MODID[737]:SYDM112*/ + [738] = {0xFCB53654U, 0x00000002U}, /* SEC_MODID[738]:SYDM113*/ + [739] = {0xFCB53658U, 0x00000002U}, /* SEC_MODID[739]:SYDM114*/ + [740] = {0xFCB5365CU, 0x00000002U}, /* SEC_MODID[740]:SYDM115*/ + [741] = {0xFCB53660U, 0x00000002U}, /* SEC_MODID[741]:SYDM102*/ + [742] = {0xFCB53664U, 0x00000002U}, /* SEC_MODID[742]:SYDM103*/ + [743] = {0xFCB53668U, 0x00000002U}, /* SEC_MODID[743]:SYDM104*/ + [744] = {0xFCB5366CU, 0x00000002U}, /* SEC_MODID[744]:SYDM105*/ + [745] = {0xFCB53670U, 0x00000002U}, /* SEC_MODID[745]:SYDM106*/ + [746] = {0xFCB53674U, 0x00000002U}, /* SEC_MODID[746]:SYDM107*/ + [747] = {0xFCB53678U, 0x00000002U}, /* SEC_MODID[747]:SYDM108*/ + [748] = {0xFCB5367CU, 0x00000002U}, /* SEC_MODID[748]:SYDM109*/ + [749] = {0xFCB53680U, 0x00000002U}, /* SEC_MODID[749]:SYDM200*/ + [750] = {0xFCB53684U, 0x00000002U}, /* SEC_MODID[750]:SYDM201*/ + [751] = {0xFCB53688U, 0x00000002U}, /* SEC_MODID[751]:SYDM210*/ + [752] = {0xFCB5368CU, 0x00000002U}, /* SEC_MODID[752]:SYDM211*/ + [753] = {0xFCB53690U, 0x00000002U}, /* SEC_MODID[753]:SYDM212*/ + [754] = {0xFCB53694U, 0x00000002U}, /* SEC_MODID[754]:SYDM213*/ + [755] = {0xFCB53698U, 0x00000002U}, /* SEC_MODID[755]:SYDM214*/ + [756] = {0xFCB5369CU, 0x00000002U}, /* SEC_MODID[756]:SYDM215*/ + [757] = {0xFCB536A0U, 0x00000002U}, /* SEC_MODID[757]:SYDM202*/ + [758] = {0xFCB536A4U, 0x00000002U}, /* SEC_MODID[758]:SYDM203*/ + [759] = {0xFCB536A8U, 0x00000002U}, /* SEC_MODID[759]:SYDM204*/ + [760] = {0xFCB536ACU, 0x00000002U}, /* SEC_MODID[760]:SYDM205*/ + [761] = {0xFCB536B0U, 0x00000002U}, /* SEC_MODID[761]:SYDM206*/ + [762] = {0xFCB536B4U, 0x00000002U}, /* SEC_MODID[762]:SYDM207*/ + [763] = {0xFCB536B8U, 0x00000002U}, /* SEC_MODID[763]:SYDM208*/ + [764] = {0xFCB536BCU, 0x00000002U}, /* SEC_MODID[764]:SYDM209*/ + [765] = {0xFC683400U, 0x00000002U}, /* SEC_MODID[765]:ARVC0*/ + [766] = {0xFC683404U, 0x00000002U}, /* SEC_MODID[766]:ARVC1*/ + [767] = {0xFC683408U, 0x00000002U}, /* SEC_MODID[767]:ARVC2*/ + [768] = {0xFC68340CU, 0x00000002U}, /* SEC_MODID[768]:ARVC3*/ + [769] = {0xFC683410U, 0x00000002U}, /* SEC_MODID[769]:AXIFBABUSVC*/ + [770] = {0xFC683414U, 0x00000002U}, /* SEC_MODID[770]:ARVC4*/ + [771] = {0xFC683418U, 0x00000002U}, /* SEC_MODID[771]:ARVC5*/ + [772] = {0xFC68341CU, 0x00000002U}, /* SEC_MODID[772]:ARVC6*/ + [773] = {0xFC683420U, 0x00000002U}, /* SEC_MODID[773]:ARVC7*/ + [774] = {0xFC683424U, 0x00000002U}, /* SEC_MODID[774]:ARVC8*/ + [775] = {0xFC683428U, 0x00000002U}, /* SEC_MODID[775]:CKMVC*/ + [776] = {0xFC68342CU, 0x00000002U}, /* SEC_MODID[776]:ECMVC0*/ + [777] = {0xFC683430U, 0x00000002U}, /* SEC_MODID[777]:IMR2*/ + [778] = {0xFC683434U, 0x00000002U}, /* SEC_MODID[778]:IMR0*/ + [779] = {0xFC683438U, 0x00000002U}, /* SEC_MODID[779]:IMR1*/ + [780] = {0xFC68343CU, 0x00000002U}, /* SEC_MODID[780]:IPMMUVC01*/ + [781] = {0xFC683440U, 0x00000002U}, /* SEC_MODID[781]:IPMMUVC10*/ + [782] = {0xFC683444U, 0x00000002U}, /* SEC_MODID[782]:IMS0*/ + [783] = {0xFC683448U, 0x00000002U}, /* SEC_MODID[783]:IMS1*/ + [784] = {0xFC68344CU, 0x00000002U}, /* SEC_MODID[784]:IPMMUVC00*/ + [785] = {0xFC683450U, 0x00000002U}, /* SEC_MODID[785]:IPMMUVC11*/ + [786] = {0xFC683454U, 0x00000002U}, /* SEC_MODID[786]:IPMMUVC12*/ + [787] = {0xFC683458U, 0x00000002U}, /* SEC_MODID[787]:IPMMUVC13*/ + [788] = {0xFC68345CU, 0x00000002U}, /* SEC_MODID[788]:IPMMUVC14*/ + [789] = {0xFC683460U, 0x00000002U}, /* SEC_MODID[789]:IPMMUVC15*/ + [790] = {0xFC683464U, 0x00000002U}, /* SEC_MODID[790]:IPMMUVC02*/ + [791] = {0xFC683468U, 0x00000002U}, /* SEC_MODID[791]:IPMMUVC03*/ + [792] = {0xFC68346CU, 0x00000002U}, /* SEC_MODID[792]:IPMMUVC04*/ + [793] = {0xFC683470U, 0x00000002U}, /* SEC_MODID[793]:IPMMUVC05*/ + [794] = {0xFC683474U, 0x00000002U}, /* SEC_MODID[794]:IPMMUVC06*/ + [795] = {0xFC683478U, 0x00000002U}, /* SEC_MODID[795]:IPMMUVC07*/ + [796] = {0xFC68347CU, 0x00000002U}, /* SEC_MODID[796]:IPMMUVC08*/ + [797] = {0xFC683480U, 0x00000002U}, /* SEC_MODID[797]:IPMMUVC09*/ + [798] = {0xFC683484U, 0x00000002U}, /* SEC_MODID[798]:IV1ES*/ + [799] = {0xFEBE3400U, 0x00000002U}, /* SEC_MODID[799]:CSITOP0*/ + [800] = {0xFEBE3404U, 0x00000002U}, /* SEC_MODID[800]:ARVI10*/ + [801] = {0xFEBE3408U, 0x00000002U}, /* SEC_MODID[801]:ARVI11*/ + [802] = {0xFEBE340CU, 0x00000002U}, /* SEC_MODID[802]:ARVI12*/ + [803] = {0xFEBE3410U, 0x00000002U}, /* SEC_MODID[803]:ARVI13*/ + [804] = {0xFEBE3414U, 0x00000002U}, /* SEC_MODID[804]:ARVI14*/ + [805] = {0xFEBE3418U, 0x00000002U}, /* SEC_MODID[805]:ARVI15*/ + [806] = {0xFEBE341CU, 0x00000002U}, /* SEC_MODID[806]:ARVI16*/ + [807] = {0xFEBE3420U, 0x00000002U}, /* SEC_MODID[807]:ARVI17*/ + [808] = {0xFEBE3424U, 0x00000002U}, /* SEC_MODID[808]:ARVI18*/ + [809] = {0xFEBE3428U, 0x00000002U}, /* SEC_MODID[809]:CKMVIO*/ + [810] = {0xFEBE342CU, 0x00000002U}, /* SEC_MODID[810]:CSITOP1*/ + [811] = {0xFEBE3434U, 0x00000002U}, /* SEC_MODID[811]:DSITLINK0*/ + [812] = {0xFEBE3438U, 0x00000002U}, /* SEC_MODID[812]:DSITLINK1*/ + [813] = {0xFEBE343CU, 0x00000002U}, /* SEC_MODID[813]:ECMVIO1*/ + [814] = {0xFEBE3444U, 0x00000002U}, /* SEC_MODID[814]:IPMMUVI001*/ + [815] = {0xFEBE3448U, 0x00000002U}, /* SEC_MODID[815]:FCPVX0*/ + [816] = {0xFEBE344CU, 0x00000002U}, /* SEC_MODID[816]:FCPVX1*/ + [817] = {0xFEBE3458U, 0x00000002U}, /* SEC_MODID[817]:IPMMUVI000*/ + [818] = {0xFEBE345CU, 0x00000002U}, /* SEC_MODID[818]:IPMMUVI100*/ + [819] = {0xFEBE3460U, 0x00000002U}, /* SEC_MODID[819]:IPMMUVI010*/ + [820] = {0xFEBE3464U, 0x00000002U}, /* SEC_MODID[820]:IPMMUVI011*/ + [821] = {0xFEBE3468U, 0x00000002U}, /* SEC_MODID[821]:VSPX0*/ + [822] = {0xFEBE346CU, 0x00000002U}, /* SEC_MODID[822]:VSPX1*/ + [823] = {0xFEBE3478U, 0x00000002U}, /* SEC_MODID[823]:IPMMUVI012*/ + [824] = {0xFEBE347CU, 0x00000002U}, /* SEC_MODID[824]:IPMMUVI013*/ + [825] = {0xFEBE3480U, 0x00000002U}, /* SEC_MODID[825]:IPMMUVI014*/ + [826] = {0xFEBE3484U, 0x00000002U}, /* SEC_MODID[826]:IPMMUVI015*/ + [827] = {0xFEBE3488U, 0x00000002U}, /* SEC_MODID[827]:IPMMUVI002*/ + [828] = {0xFEBE348CU, 0x00000002U}, /* SEC_MODID[828]:IPMMUVI003*/ + [829] = {0xFEBE3490U, 0x00000002U}, /* SEC_MODID[829]:IPMMUVI004*/ + [830] = {0xFEBE3494U, 0x00000002U}, /* SEC_MODID[830]:IPMMUVI005*/ + [831] = {0xFEBE3498U, 0x00000002U}, /* SEC_MODID[831]:IPMMUVI006*/ + [832] = {0xFEBE349CU, 0x00000002U}, /* SEC_MODID[832]:IPMMUVI007*/ + [833] = {0xFEBE34A0U, 0x00000002U}, /* SEC_MODID[833]:IPMMUVI008*/ + [834] = {0xFEBE34A4U, 0x00000002U}, /* SEC_MODID[834]:IPMMUVI009*/ + [835] = {0xFEBE34A8U, 0x00000002U}, /* SEC_MODID[835]:IPMMUVI101*/ + [836] = {0xFEBE34ACU, 0x00000002U}, /* SEC_MODID[836]:IPMMUVI110*/ + [837] = {0xFEBE34B0U, 0x00000002U}, /* SEC_MODID[837]:IPMMUVI111*/ + [838] = {0xFEBE34B4U, 0x00000002U}, /* SEC_MODID[838]:IPMMUVI112*/ + [839] = {0xFEBE34B8U, 0x00000002U}, /* SEC_MODID[839]:IPMMUVI113*/ + [840] = {0xFEBE34BCU, 0x00000002U}, /* SEC_MODID[840]:IPMMUVI114*/ + [841] = {0xFEBE34C0U, 0x00000002U}, /* SEC_MODID[841]:IPMMUVI115*/ + [842] = {0xFEBE34C4U, 0x00000002U}, /* SEC_MODID[842]:IPMMUVI102*/ + [843] = {0xFEBE34C8U, 0x00000002U}, /* SEC_MODID[843]:IPMMUVI103*/ + [844] = {0xFEBE34CCU, 0x00000002U}, /* SEC_MODID[844]:IPMMUVI104*/ + [845] = {0xFEBE34D0U, 0x00000002U}, /* SEC_MODID[845]:IPMMUVI105*/ + [846] = {0xFEBE34D4U, 0x00000002U}, /* SEC_MODID[846]:IPMMUVI106*/ + [847] = {0xFEBE34D8U, 0x00000002U}, /* SEC_MODID[847]:IPMMUVI107*/ + [848] = {0xFEBE34DCU, 0x00000002U}, /* SEC_MODID[848]:IPMMUVI108*/ + [849] = {0xFEBE34E0U, 0x00000002U}, /* SEC_MODID[849]:IPMMUVI109*/ + [850] = {0xFEBE3504U, 0x00000002U}, /* SEC_MODID[850]:AXIFBABUSVIO*/ + [851] = {0xFEBF3400U, 0x00000002U}, /* SEC_MODID[851]:ARVI0*/ + [852] = {0xFEBF3404U, 0x00000002U}, /* SEC_MODID[852]:ARVI1*/ + [853] = {0xFEBF3408U, 0x00000002U}, /* SEC_MODID[853]:ARVI2*/ + [854] = {0xFEBF340CU, 0x00000002U}, /* SEC_MODID[854]:ARVI3*/ + [855] = {0xFEBF3410U, 0x00000002U}, /* SEC_MODID[855]:ARVI4*/ + [856] = {0xFEBF3414U, 0x00000002U}, /* SEC_MODID[856]:ARVI5*/ + [857] = {0xFEBF3418U, 0x00000002U}, /* SEC_MODID[857]:ARVI6*/ + [858] = {0xFEBF341CU, 0x00000002U}, /* SEC_MODID[858]:ARVI7*/ + [859] = {0xFEBF3420U, 0x00000002U}, /* SEC_MODID[859]:ARVI8*/ + [860] = {0xFEBF3424U, 0x00000002U}, /* SEC_MODID[860]:ECMVIO0*/ + [861] = {0xFEBF3428U, 0x00000002U}, /* SEC_MODID[861]:ISP0*/ + [862] = {0xFEBF342CU, 0x00000002U}, /* SEC_MODID[862]:ISP0CORE*/ + [863] = {0xFEBF3430U, 0x00000002U}, /* SEC_MODID[863]:ISP1*/ + [864] = {0xFEBF3434U, 0x00000002U}, /* SEC_MODID[864]:ISP1CORE*/ + [865] = {0xFEBF3454U, 0x00000002U}, /* SEC_MODID[865]:VIN00*/ + [866] = {0xFEBF3458U, 0x00000002U}, /* SEC_MODID[866]:VIN01*/ + [867] = {0xFEBF345CU, 0x00000002U}, /* SEC_MODID[867]:VIN02*/ + [868] = {0xFEBF3460U, 0x00000002U}, /* SEC_MODID[868]:VIN03*/ + [869] = {0xFEBF3464U, 0x00000002U}, /* SEC_MODID[869]:VIN04*/ + [870] = {0xFEBF3468U, 0x00000002U}, /* SEC_MODID[870]:VIN05*/ + [871] = {0xFEBF346CU, 0x00000002U}, /* SEC_MODID[871]:VIN06*/ + [872] = {0xFEBF3470U, 0x00000002U}, /* SEC_MODID[872]:VIN07*/ + [873] = {0xFEBF3474U, 0x00000002U}, /* SEC_MODID[873]:VIN10*/ + [874] = {0xFEBF3478U, 0x00000002U}, /* SEC_MODID[874]:VIN11*/ + [875] = {0xFEBF347CU, 0x00000002U}, /* SEC_MODID[875]:VIN12*/ + [876] = {0xFEBF3480U, 0x00000002U}, /* SEC_MODID[876]:VIN13*/ + [877] = {0xFEBF3484U, 0x00000002U}, /* SEC_MODID[877]:VIN14*/ + [878] = {0xFEBF3488U, 0x00000002U}, /* SEC_MODID[878]:VIN15*/ + [879] = {0xFEBF348CU, 0x00000002U}, /* SEC_MODID[879]:VIN16*/ + [880] = {0xFEBF3490U, 0x00000002U}, /* SEC_MODID[880]:VIN17*/ + [881] = {0xFC313400U, 0x00000002U}, /* SEC_MODID[881]:ARVIP00*/ + [882] = {0xFC313404U, 0x00000002U}, /* SEC_MODID[882]:ARVIP01*/ + [883] = {0xFC313408U, 0x00000002U}, /* SEC_MODID[883]:ARVIP02*/ + [884] = {0xFC31340CU, 0x00000002U}, /* SEC_MODID[884]:ARVIP03*/ + [885] = {0xFC313410U, 0x00000002U}, /* SEC_MODID[885]:AXIFBABUSVIP0*/ + [886] = {0xFC313414U, 0x00000002U}, /* SEC_MODID[886]:ARVIP04*/ + [887] = {0xFC313418U, 0x00000002U}, /* SEC_MODID[887]:ARVIP05*/ + [888] = {0xFC31341CU, 0x00000002U}, /* SEC_MODID[888]:ARVIP06*/ + [889] = {0xFC313420U, 0x00000002U}, /* SEC_MODID[889]:ARVIP07*/ + [890] = {0xFC313424U, 0x00000002U}, /* SEC_MODID[890]:ARVIP08*/ + [891] = {0xFC313428U, 0x00000002U}, /* SEC_MODID[891]:CKMVIP*/ + [892] = {0xFC31342CU, 0x00000002U}, /* SEC_MODID[892]:ECMVIP0*/ + [893] = {0xFC313430U, 0x00000002U}, /* SEC_MODID[893]:IPMMUVIP000*/ + [894] = {0xFC313438U, 0x00000002U}, /* SEC_MODID[894]:SMPO0*/ + [895] = {0xFC31343CU, 0x00000002U}, /* SEC_MODID[895]:SMPS0*/ + [896] = {0xFC313440U, 0x00000002U}, /* SEC_MODID[896]:UMFL0*/ + [897] = {0xFC313444U, 0x00000002U}, /* SEC_MODID[897]:IPMMUVIP001*/ + [898] = {0xFC313448U, 0x00000002U}, /* SEC_MODID[898]:IPMMUVIP010*/ + [899] = {0xFC31344CU, 0x00000002U}, /* SEC_MODID[899]:IPMMUVIP011*/ + [900] = {0xFC313450U, 0x00000002U}, /* SEC_MODID[900]:UMFL0M_W*/ + [901] = {0xFC313454U, 0x00000002U}, /* SEC_MODID[901]:IPMMUVIP012*/ + [902] = {0xFC313458U, 0x00000002U}, /* SEC_MODID[902]:IPMMUVIP013*/ + [903] = {0xFC31345CU, 0x00000002U}, /* SEC_MODID[903]:IPMMUVIP014*/ + [904] = {0xFC313460U, 0x00000002U}, /* SEC_MODID[904]:IPMMUVIP015*/ + [905] = {0xFC313464U, 0x00000002U}, /* SEC_MODID[905]:IPMMUVIP002*/ + [906] = {0xFC313468U, 0x00000002U}, /* SEC_MODID[906]:IPMMUVIP003*/ + [907] = {0xFC31346CU, 0x00000002U}, /* SEC_MODID[907]:IPMMUVIP004*/ + [908] = {0xFC313470U, 0x00000002U}, /* SEC_MODID[908]:IPMMUVIP005*/ + [909] = {0xFC313474U, 0x00000002U}, /* SEC_MODID[909]:IPMMUVIP006*/ + [910] = {0xFC313478U, 0x00000002U}, /* SEC_MODID[910]:IPMMUVIP007*/ + [911] = {0xFC31347CU, 0x00000002U}, /* SEC_MODID[911]:IPMMUVIP008*/ + [912] = {0xFC313480U, 0x00000002U}, /* SEC_MODID[912]:IPMMUVIP009*/ + [913] = {0xFC343400U, 0x00000002U}, /* SEC_MODID[913]:ARVIP10*/ + [914] = {0xFC343404U, 0x00000002U}, /* SEC_MODID[914]:ARVIP11*/ + [915] = {0xFC343408U, 0x00000002U}, /* SEC_MODID[915]:ARVIP12*/ + [916] = {0xFC34340CU, 0x00000002U}, /* SEC_MODID[916]:ARVIP13*/ + [917] = {0xFC343410U, 0x00000002U}, /* SEC_MODID[917]:AXIFBABUSVIP1*/ + [918] = {0xFC343414U, 0x00000002U}, /* SEC_MODID[918]:ARVIIP14*/ + [919] = {0xFC343418U, 0x00000002U}, /* SEC_MODID[919]:ARVIIP15*/ + [920] = {0xFC34341CU, 0x00000002U}, /* SEC_MODID[920]:ARVIIP16*/ + [921] = {0xFC343420U, 0x00000002U}, /* SEC_MODID[921]:ARVIIP17*/ + [922] = {0xFC343424U, 0x00000002U}, /* SEC_MODID[922]:ARVIIP18*/ + [923] = {0xFC343438U, 0x00000002U}, /* SEC_MODID[923]:ECMVIP1*/ + [924] = {0xFC34343CU, 0x00000002U}, /* SEC_MODID[924]:IPMMUVIP101*/ + [925] = {0xFC343440U, 0x00000002U}, /* SEC_MODID[925]:IPMMUVIP100*/ + [926] = {0xFC343444U, 0x00000002U}, /* SEC_MODID[926]:IPMMUVIP110*/ + [927] = {0xFC343448U, 0x00000002U}, /* SEC_MODID[927]:IPMMUVIP111*/ + [928] = {0xFC34344CU, 0x00000002U}, /* SEC_MODID[928]:IPMMUVIP112*/ + [929] = {0xFC343450U, 0x00000002U}, /* SEC_MODID[929]:IPMMUVIP113*/ + [930] = {0xFC343454U, 0x00000002U}, /* SEC_MODID[930]:IPMMUVIP114*/ + [931] = {0xFC343458U, 0x00000002U}, /* SEC_MODID[931]:IPMMUVIP115*/ + [932] = {0xFC34345CU, 0x00000002U}, /* SEC_MODID[932]:IPMMUVIP102*/ + [933] = {0xFC343460U, 0x00000002U}, /* SEC_MODID[933]:IPMMUVIP103*/ + [934] = {0xFC343464U, 0x00000002U}, /* SEC_MODID[934]:IPMMUVIP104*/ + [935] = {0xFC343468U, 0x00000002U}, /* SEC_MODID[935]:IPMMUVIP105*/ + [936] = {0xFC34346CU, 0x00000002U}, /* SEC_MODID[936]:IPMMUVIP106*/ + [937] = {0xFC343470U, 0x00000002U}, /* SEC_MODID[937]:IPMMUVIP107*/ + [938] = {0xFC343474U, 0x00000002U}, /* SEC_MODID[938]:IPMMUVIP108*/ + [939] = {0xFC343478U, 0x00000002U}, /* SEC_MODID[939]:IPMMUVIP109*/ + [940] = {0xFC343518U, 0x00000002U}, /* SEC_MODID[940]:PAP*/ + [941] = {0xFC403400U, 0x00000002U}, /* SEC_MODID[941]:ARDSP0*/ + [942] = {0xFC403404U, 0x00000002U}, /* SEC_MODID[942]:ARDSP1*/ + [943] = {0xFC403408U, 0x00000002U}, /* SEC_MODID[943]:ARDSP2*/ + [944] = {0xFC40340CU, 0x00000002U}, /* SEC_MODID[944]:ARDSP3*/ + [945] = {0xFC403410U, 0x00000002U}, /* SEC_MODID[945]:ARDSP4*/ + [946] = {0xFC403414U, 0x00000002U}, /* SEC_MODID[946]:ARDSP5*/ + [947] = {0xFC403418U, 0x00000002U}, /* SEC_MODID[947]:ARDSP6*/ + [948] = {0xFC40341CU, 0x00000002U}, /* SEC_MODID[948]:ARDSP7*/ + [949] = {0xFC403420U, 0x00000002U}, /* SEC_MODID[949]:ECMDSP*/ + [950] = {0xFC403424U, 0x00000002U}, /* SEC_MODID[950]:AXIDSP0*/ + [951] = {0xFC403428U, 0x00000002U}, /* SEC_MODID[951]:AXIDSP1*/ + [952] = {0xFC40342CU, 0x00000002U}, /* SEC_MODID[952]:AXIDSP2*/ + [953] = {0xFC403430U, 0x00000002U}, /* SEC_MODID[953]:AXIDSP3*/ + [955] = {0xFDDB9624U, 0x00000001U}, /* SEC_MODID[954]:ARCC*/ + [954] = {0xFDDB9638U, 0x00000001U}, /* SEC_MODID[955]:ARRTRAM*/ + [956] = {0xFCB53424U, 0x00000002U}, /* SEC_MODID[956]:RSV0*/ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_axi_tbl" +const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[] = { + [0] = {0xFD482010U, 0x0000000FU}, /* RGIDR_MODID[4]:ARRT01*/ + [1] = {0xFD482014U, 0x0000000FU}, /* RGIDR_MODID[5]:ARRT02*/ + [2] = {0xFDA02048U, 0x0000000FU}, /* RGIDR_MODID[42]:ARS01*/ + [3] = {0xFDA0204CU, 0x0000000FU}, /* RGIDR_MODID[43]:ARS02*/ + [4] = {0xFCB62028U, 0x0000000FU}, /* RGIDR_MODID[106]:ARSP31*/ + [5] = {0xFCB6202CU, 0x0000000FU}, /* RGIDR_MODID[107]:ARSP32*/ + [6] = {0xFCB92004U, 0x0000000FU}, /* RGIDR_MODID[121]:ARSP41*/ + [7] = {0xFCB92008U, 0x0000000FU}, /* RGIDR_MODID[122]:ARSP42*/ + [8] = {0xFC672004U, 0x0000002FU}, /* RGIDR_MODID[165]:ARVC11*/ + [9] = {0xFC672008U, 0x0000002FU}, /* RGIDR_MODID[166]:ARVC12*/ + [10] = {0xFEBD2004U, 0x0000000FU}, /* RGIDR_MODID[178]:ARVI41*/ + [11] = {0xFEBD2008U, 0x0000000FU}, /* RGIDR_MODID[179]:ARVI42*/ + [12] = {0xFCF82140U, 0x0000000FU}, /* RGIDR_MODID[245]:ARHC1*/ + [13] = {0xFCF82144U, 0x0000000FU}, /* RGIDR_MODID[246]:ARHC2*/ + [14] = {0xFC882004U, 0x0000000FU}, /* RGIDR_MODID[261]:ARIMP01*/ + [15] = {0xFC882008U, 0x0000000FU}, /* RGIDR_MODID[262]:ARIMP02*/ + [16] = {0xFC012004U, 0x0000000FU}, /* RGIDR_MODID[297]:ARPV1*/ + [17] = {0xFC01200CU, 0x0000000FU}, /* RGIDR_MODID[299]:ARPV2*/ + [18] = {0xFDC22004U, 0x0000000FU}, /* RGIDR_MODID[330]:ARRC1*/ + [19] = {0xFDC22008U, 0x0000000FU}, /* RGIDR_MODID[331]:ARRC2*/ + [20] = {0xFD442060U, 0x0000000FU}, /* RGIDR_MODID[369]:ARRD1*/ + [21] = {0xFD442064U, 0x0000000FU}, /* RGIDR_MODID[370]:ARRD2*/ + [22] = {0xFD442084U, 0x0000000FU}, /* RGIDR_MODID[378]:ARRT1*/ + [23] = {0xFD442088U, 0x0000000FU}, /* RGIDR_MODID[379]:ARRT2*/ + [26] = {0xFC862004U, 0x0000000FU}, /* RGIDR_MODID[551]:ARSC1*/ + [27] = {0xFC862008U, 0x0000000FU}, /* RGIDR_MODID[552]:ARSC2*/ + [24] = {0xFC862028U, 0x0000000FU}, /* RGIDR_MODID[560]:ARSTM1*/ + [25] = {0xFC862038U, 0x0000000FU}, /* RGIDR_MODID[564]:ARSTM2*/ + [28] = {0xFDDC2004U, 0x0000000FU}, /* RGIDR_MODID[606]:AXIARNMM*/ + [29] = {0xFDDC200CU, 0x0000000FU}, /* RGIDR_MODID[608]:ARSM1*/ + [30] = {0xFDDC2010U, 0x0000000FU}, /* RGIDR_MODID[609]:ARSM2*/ + [31] = {0xFC802004U, 0x0000000FU}, /* RGIDR_MODID[660]:ARSN1*/ + [32] = {0xFC802008U, 0x0000000FU}, /* RGIDR_MODID[661]:ARSN2*/ + [33] = {0xFCB52004U, 0x0000000FU}, /* RGIDR_MODID[670]:ARSD01*/ + [34] = {0xFCB52008U, 0x0000000FU}, /* RGIDR_MODID[671]:ARSD02*/ + [35] = {0xFCB5203CU, 0x0000000FU}, /* RGIDR_MODID[683]:ARSP01*/ + [36] = {0xFCB52040U, 0x0000000FU}, /* RGIDR_MODID[684]:ARSP02*/ + [37] = {0xFC682004U, 0x0000000FU}, /* RGIDR_MODID[766]:ARVC1*/ + [38] = {0xFC682008U, 0x0000000FU}, /* RGIDR_MODID[767]:ARVC2*/ + [39] = {0xFEBE2008U, 0x0000000FU}, /* RGIDR_MODID[801]:ARVI11*/ + [40] = {0xFEBE200CU, 0x0000000FU}, /* RGIDR_MODID[802]:ARVI12*/ + [41] = {0xFEBF2004U, 0x0000000FU}, /* RGIDR_MODID[852]:ARVI1*/ + [42] = {0xFEBF2008U, 0x0000000FU}, /* RGIDR_MODID[853]:ARVI2*/ + [43] = {0xFC312004U, 0x0000000FU}, /* RGIDR_MODID[882]:ARVIP01*/ + [44] = {0xFC312008U, 0x0000000FU}, /* RGIDR_MODID[883]:ARVIP02*/ + [45] = {0xFC342004U, 0x0000000FU}, /* RGIDR_MODID[914]:ARVIP11*/ + [46] = {0xFC342008U, 0x0000000FU}, /* RGIDR_MODID[915]:ARVIP12*/ + [47] = {0xFC402004U, 0x0000000FU}, /* RGIDR_MODID[942]:ARDSP1*/ + [48] = {0xFC402008U, 0x0000000FU}, /* RGIDR_MODID[943]:ARDSP2*/ + [49] = {0xFD482410U, 0x00000000U}, /* RGIDW_MODID[4]:ARRT01*/ + [50] = {0xFD482414U, 0x00000000U}, /* RGIDW_MODID[5]:ARRT02*/ + [51] = {0xFDA02448U, 0x00000000U}, /* RGIDW_MODID[42]:ARS01*/ + [52] = {0xFDA0244CU, 0x00000000U}, /* RGIDW_MODID[43]:ARS02*/ + [53] = {0xFCB62428U, 0x00000000U}, /* RGIDW_MODID[106]:ARSP31*/ + [54] = {0xFCB6242CU, 0x00000000U}, /* RGIDW_MODID[107]:ARSP32*/ + [55] = {0xFCB92404U, 0x00000000U}, /* RGIDW_MODID[121]:ARSP41*/ + [56] = {0xFCB92408U, 0x00000000U}, /* RGIDW_MODID[122]:ARSP42*/ + [57] = {0xFC672404U, 0x00000000U}, /* RGIDW_MODID[165]:ARVC11*/ + [58] = {0xFC672408U, 0x00000000U}, /* RGIDW_MODID[166]:ARVC12*/ + [59] = {0xFEBD2404U, 0x00000000U}, /* RGIDW_MODID[178]:ARVI41*/ + [60] = {0xFEBD2408U, 0x00000000U}, /* RGIDW_MODID[179]:ARVI42*/ + [61] = {0xFCF82540U, 0x00000000U}, /* RGIDW_MODID[245]:ARHC1*/ + [62] = {0xFCF82544U, 0x00000000U}, /* RGIDW_MODID[246]:ARHC2*/ + [63] = {0xFC882404U, 0x00000000U}, /* RGIDW_MODID[261]:ARIMP01*/ + [64] = {0xFC882408U, 0x00000000U}, /* RGIDW_MODID[262]:ARIMP02*/ + [65] = {0xFC012404U, 0x00000000U}, /* RGIDW_MODID[297]:ARPV1*/ + [66] = {0xFC01240CU, 0x00000000U}, /* RGIDW_MODID[299]:ARPV2*/ + [67] = {0xFDC22404U, 0x00000000U}, /* RGIDW_MODID[330]:ARRC1*/ + [68] = {0xFDC22408U, 0x00000000U}, /* RGIDW_MODID[331]:ARRC2*/ + [69] = {0xFD442460U, 0x00000000U}, /* RGIDW_MODID[368]:ARRD1*/ + [70] = {0xFD442464U, 0x00000000U}, /* RGIDW_MODID[369]:ARRD2*/ + [71] = {0xFD442484U, 0x00000000U}, /* RGIDW_MODID[377]:ARRT1*/ + [72] = {0xFD442488U, 0x00000000U}, /* RGIDW_MODID[378]:ARRT2*/ + [75] = {0xFC862404U, 0x00000000U}, /* RGIDW_MODID[550]:ARSC1*/ + [76] = {0xFC862408U, 0x00000000U}, /* RGIDW_MODID[551]:ARSC2*/ + [73] = {0xFC862428U, 0x00000000U}, /* RGIDW_MODID[559]:ARSTM1*/ + [74] = {0xFC862438U, 0x00000000U}, /* RGIDW_MODID[563]:ARSTM2*/ + [77] = {0xFDDC2404U, 0x00000000U}, /* RGIDW_MODID[605]:AXIARNMM*/ + [78] = {0xFDDC240CU, 0x00000000U}, /* RGIDW_MODID[607]:ARSM1*/ + [79] = {0xFDDC2410U, 0x00000000U}, /* RGIDW_MODID[608]:ARSM2*/ + [80] = {0xFC802404U, 0x00000000U}, /* RGIDW_MODID[659]:ARSN1*/ + [81] = {0xFC802408U, 0x00000000U}, /* RGIDW_MODID[660]:ARSN2*/ + [82] = {0xFCB52404U, 0x00000000U}, /* RGIDW_MODID[669]:ARSD01*/ + [83] = {0xFCB52408U, 0x00000000U}, /* RGIDW_MODID[670]:ARSD02*/ + [84] = {0xFCB5243CU, 0x00000000U}, /* RGIDW_MODID[682]:ARSP01*/ + [85] = {0xFCB52440U, 0x00000000U}, /* RGIDW_MODID[683]:ARSP02*/ + [86] = {0xFC682404U, 0x00000000U}, /* RGIDW_MODID[765]:ARVC1*/ + [87] = {0xFC682408U, 0x00000000U}, /* RGIDW_MODID[766]:ARVC2*/ + [88] = {0xFEBE2408U, 0x00000000U}, /* RGIDW_MODID[800]:ARVI11*/ + [89] = {0xFEBE240CU, 0x00000000U}, /* RGIDW_MODID[801]:ARVI12*/ + [90] = {0xFEBF2404U, 0x00000000U}, /* RGIDW_MODID[851]:ARVI1*/ + [91] = {0xFEBF2408U, 0x00000000U}, /* RGIDW_MODID[852]:ARVI2*/ + [92] = {0xFC312404U, 0x00000000U}, /* RGIDW_MODID[881]:ARVIP01*/ + [93] = {0xFC312408U, 0x00000000U}, /* RGIDW_MODID[882]:ARVIP02*/ + [94] = {0xFC342404U, 0x00000000U}, /* RGIDW_MODID[913]:ARVIP11*/ + [95] = {0xFC342408U, 0x00000000U}, /* RGIDW_MODID[914]:ARVIP12*/ + [96] = {0xFC402404U, 0x00000000U}, /* RGIDW_MODID[941]:ARDSP1*/ + [97] = {0xFC402408U, 0x00000000U}, /* RGIDW_MODID[942]:ARDSP2*/ +}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_gid_tbl" +const REGION_ID_SETTING_TABLE g_rgid_gid_tbl[] = { + [0] = {0xFC0F0000U, 0x000F0024U}, /* CCI MPU GID register 0 */ + /* Physical address:0xF12F0000, Logical address 0x0xFC0F0000 */ + [1] = {0xFC0F0004U, 0x000F0024U}, /* CCI MPU GID register 1 */ + /* Physical address:0xF12F0004, Logical address 0x0xFC0F0004 */ +}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +const uint32_t g_rgid_rtdma_setting_value[RTDMA_MODULE_MAX][RTDMA_CH_MAX][2U] = { + {/* Module0 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, + {/* Module1 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, + {/* Module2 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, + {/* Module3 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + } +}; + +const uint32_t g_rgid_sysdma_setting_value[SYSDMA_MODULE_MAX][SYSDMA_CH_MAX][2U] = { + {/* Module0 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {SYSDMA_EN, RGID_2}, /* CH0 */ + [1] = {SYSDMA_EN, RGID_2}, /* CH1 */ + [2] = {SYSDMA_EN, RGID_2}, /* CH2 */ + [3] = {SYSDMA_EN, RGID_2}, /* CH3 */ + [4] = {SYSDMA_EN, RGID_2}, /* CH4 */ + [5] = {SYSDMA_EN, RGID_2}, /* CH5 */ + [6] = {SYSDMA_EN, RGID_2}, /* CH6 */ + [7] = {SYSDMA_EN, RGID_2}, /* CH7 */ + [8] = {SYSDMA_EN, RGID_2}, /* CH8 */ + [9] = {SYSDMA_EN, RGID_2}, /* CH9 */ + [10] = {SYSDMA_EN, RGID_2}, /* CH10 */ + [11] = {SYSDMA_EN, RGID_2}, /* CH11 */ + [12] = {SYSDMA_EN, RGID_2}, /* CH12 */ + [13] = {SYSDMA_EN, RGID_2}, /* CH13 */ + [14] = {SYSDMA_EN, RGID_2}, /* CH14 */ + [15] = {SYSDMA_EN, RGID_2} /* CH15 */ + }, + {/* Module1 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {SYSDMA_EN, RGID_2}, /* CH0 */ + [1] = {SYSDMA_EN, RGID_2}, /* CH1 */ + [2] = {SYSDMA_EN, RGID_2}, /* CH2 */ + [3] = {SYSDMA_EN, RGID_2}, /* CH3 */ + [4] = {SYSDMA_EN, RGID_2}, /* CH4 */ + [5] = {SYSDMA_EN, RGID_2}, /* CH5 */ + [6] = {SYSDMA_EN, RGID_2}, /* CH6 */ + [7] = {SYSDMA_EN, RGID_2}, /* CH7 */ + [8] = {SYSDMA_EN, RGID_2}, /* CH8 */ + [9] = {SYSDMA_EN, RGID_2}, /* CH9 */ + [10] = {SYSDMA_EN, RGID_2}, /* CH10 */ + [11] = {SYSDMA_EN, RGID_2}, /* CH11 */ + [12] = {SYSDMA_EN, RGID_2}, /* CH12 */ + [13] = {SYSDMA_EN, RGID_2}, /* CH13 */ + [14] = {SYSDMA_EN, RGID_2}, /* CH14 */ + [15] = {SYSDMA_EN, RGID_2} /* CH15 */ + }, +}; + +/* When V4H, this table is used as RT-VRAM0. */ +/* RAM protection setting for SECDIV[n]D_0 / SECCTRR[m]D_0 / SECCTRW[m]D_0 */ +const RTRAM_PROTECTION_STRUCTUR g_rtsram_protection_table[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTSRAM_ICUMX_IPL_AREA] = {NOT_USED_VALUE, {0x0000FFFCU, 0x0000FFFEU}}, /* not used for address value */ + /* Area0 phys:0xE0000000-0xE003FFFF R:RGID0/1 W:RGID0 */ + [RTSRAM_ICUMX_FW_AREA] = {RTSRAM_AREA1_TOP, {0x0004FFFEU, 0x0004FFFEU}}, /* Area1 phys:0xE0040000-0xE00FFFFF R:RGID0 W:RGID0 */ + [2] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [3] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* this table is finaly setting for RT-VRAM protection */ +/* RAM protection setting for SECDIV[n]D_1 / SECCTRR[m]D_1 / SECCTRW[m]D_1 */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table_1[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM_BLANK_AREA] = {NOT_USED_VALUE, {0x0000FFB6U, 0x0000FFB2U}}, /* not used for address value */ + /* Area0 phys:0xE2000000-0xE200FFFF R:RGID0/3/6 W:RGID0/2/3/6 */ + [RTVRAM_EXTEND_CACHE_AREA] = {RTVRAM_AREA1_TOP, {0x0000BFFFU, 0x0000BFFFU}}, /* Area1 phys:0xE2010000-0xE20FFFFF R:RGID14 W:RGID14 */ + [RTVRAM_RTOS_AREA] = {RTVRAM_AREA2_TOP, {0x0000FFF4U, 0x0000FFF0U}}, /* Area2 phys:0xE2100000-0xE3BFFFFF R:RGID0/1/3 W:RGID0/1/2/3 */ + [3] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for SPTDIVCR[n] / SPTRGNCR[n] / SPTSECCR[n] */ +const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX] = { + /* access Secure */ + /* address R | W R|W */ + [SYSTEM_RAM_CX_2ND_IPL] = {NOT_USED_VALUE, {0xFFD8FFD8U, 0x00000000U}}, /* not used for address value */ + /* Area0 phys:0xE6300000-0xE635DFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [SYSTEM_RAM_SHARED_MEM] = {SYSTEM_RAM_AREA1_TOP, {0xFFD8FFD8U, 0x00000000U}}, /* Area1 phys:0xE635E000-0xE635FFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [2] = {SYSTEM_RAM_AREA2_TOP, {0xFFDAFFDAU, 0x00000000U}}, /* Area2 phys:0xE6360000-0xE63FFFFF R:RGID0/2/5 W:RGID0/2/5 */ + [3] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for DPTDIVCR[n] / DPTRGNCR[n] / DPTSECCR[n] */ +const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX] = { + /* access secure */ + /* address R | W R|W */ + [RTVRAM_EXTEND_AREA] = {NOT_USED_VALUE, {0xBFFFBFFFU, 0x00000000U}}, /* not used for address value */ + /* Area0 phys:0x04_00000000-0x04_01BFFFFF R:RGID14 W:RGID14 */ + [CR_FW_SHARED_AREA] = {DRAM_ADDR_AREA1, {0xFFBCFFBCU, 0x00000000U}}, /* Area1 phys:0x04_01C00000-0x04_01CFFFFF R:RGID0/1/6 W:RGID0/1/6 */ + [SDRAM_BLANK_AREA] = {DRAM_ADDR_AREA2, {0xFF90FF90U, 0x00000000U}}, /* Area2:OPTEE_DISABLE phys:0x04_01D00000-0x04_063FFFFF + * Area2:OPTEE_ENABLE phys:0x04_01D00000-0x04_040FFFFF + * R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFAFFF8U, 0x00000000U}}, /* Area3 phys:0x04_06400000-0x04_0643FFFF R:RGID0/2 W:RGID0/1/2 */ + [SDRAM_PUBLIC_AREA] = {DRAM_ADDR_AREA4, {0xFF90FF90U, 0x00000000U}}, /* Area4 phys:0x04_06440000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA5, {0xFFB9FFB9U, 0x00000000U}}, /* Area5 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA6, {0xFFB0FFB0U, 0x00000000U}}, /* Area6 phys:0x04_08000000-0x04_1DBFFFFF R:RGID0/1/2/3/6 W:RGID0/1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA7, {0xFFB9FFB9U, 0x00000000U}}, /* Area7 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFBDFFBDU, 0x00000000U}}, /* Area8 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFDDFFDDU, 0x00000000U}}, /* Area9 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA11,{0xBF90BF90U, 0x00000000U}}, /* Area11 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA12,{0xFFFFFFFFU, 0x00000000U}}, /* Area12 phys:0x05_00000000-0x05_FFFFFFFF */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFF9FFF9U, 0x00000000U}}, /* Area13 phys:0x06_00000000-0x06_FFFFFFFF R:RGID1/2 W:RGID1/2 */ + [14] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [16] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +#else + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFAFFFAU, 0x00000000U}}, /* Area3 phys:0x04_04100000-0x04_063FFFFF R:RGID0/2 W:RGID0/2 */ + [SDRAM_PROTECT_AREA2]= {DRAM_ADDR_AREA4, {0xFFFAFFF8U, 0x00000000U}}, /* Area4 phys:0x04_06400000-0x04_0643FFFF R:RGID0/2 W:RGID0/1/2 */ + [SDRAM_BLANK_AREA2] = {DRAM_ADDR_AREA5, {0xFF90FF90U, 0x00000000U}}, /* Area5 phys:0x04_06440000-0x04_07DFFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [OPTEE_SHARED_AREA] = {DRAM_ADDR_AREA6, {0xFFFBFFFBU, 0x00000000U}}, /* Area6 phys:0x04_07E00000-0x04_07EFFFFF R:RGID2 W:RGID2 */ + [SDRAM_BLANK_AREA3] = {DRAM_ADDR_AREA7, {0xFF90FF90U, 0x00000000U}}, /* Area7 phys:0x04_07F00000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFB9FFB9U, 0x00000000U}}, /* Area8 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFB0FFB0U, 0x00000000U}}, /* Area9 phys:0x04_08000000-0x04_1DBFFFFF R:RGID0/1/2/3/6 W:RGID0/1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA11,{0xFFBDFFBDU, 0x00000000U}}, /* Area11 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA12,{0xFFDDFFDDU, 0x00000000U}}, /* Area12 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFB9FFB9U, 0x00000000U}}, /* Area13 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA14,{0xBF90BF90U, 0x00000000U}}, /* Area14 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA15,{0xFFFFFFFFU, 0x00000000U}}, /* Area15 phys:0x05_00000000-0x05_FFFFFFFF */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA16,{0xFFF9FFF9U, 0x00000000U}}, /* Area16 phys:0x06_00000000-0x06_FFFFFFFF R:RGID1/2 W:RGID1/2 */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + [17] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [18] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [19] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [20] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [21] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [22] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [23] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [24] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [25] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [26] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [27] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [28] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [29] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [30] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [31] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [32] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [33] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [34] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [35] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [36] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [37] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [38] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [39] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [40] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [41] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [42] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [43] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [44] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [45] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [46] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [47] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [48] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [49] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [50] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [51] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [52] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [53] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [54] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [55] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [56] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [57] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [58] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [59] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [60] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [61] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [62] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [63] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +const CONFIGURATION_SETTING_TABLE g_fdt_tbl[FDT_REG_MAX] = { + [0] = {0xFD480700U, 0x00000002U}, /*FDT_AXRT2APRT0*/ + [1] = {0xFDA00700U, 0x00000002U}, /*FDT_AXSC2APS0*/ + [2] = {0xFCB60700U, 0x00000004U}, /*FDT_AXSP02APSP3*/ + [3] = {0xFCB60704U, 0x00000004U}, /*FDT_AXSD02APSP3*/ + [4] = {0xFCB90700U, 0x00000004U}, /*FDT_AXSD02APSP4*/ + [5] = {0xFCB90704U, 0x00000004U}, /*FDT_AXSP02APSP4*/ + [6] = {0xFC070700U, 0x00000005U}, /*FDT_AXVC2APVC1*/ + [7] = {0xFC9D0700U, 0x00000006U}, /*FDT_AXVI12APVI4*/ + [8] = {0xFCF80700U, 0x00000008U}, /*FDT_PCI00*/ + [9] = {0xFCF80710U, 0x00000005U}, /*FDT_AVB0*/ + [10] = {0xFCF80714U, 0x00000005U}, /*FDT_AVB1*/ + [11] = {0xFCF80718U, 0x00000005U}, /*FDT_AVB2*/ + [12] = {0xFCF80720U, 0x00000008U}, /*FDT_PCI01*/ + [13] = {0xFCF80724U, 0x00000008U}, /*FDT_PCI10*/ + [14] = {0xFCF80728U, 0x00000008U}, /*FDT_AXSTM2AXHC0*/ + [15] = {0xFCF8072CU, 0x00000008U}, /*FDT_AXSTM2AXHC1*/ + [16] = {0xFCF80734U, 0x00000008U}, /*FDT_PCI11*/ + [17] = {0xFCF80740U, 0x00000005U}, /*FDT_TSN0*/ + [18] = {0xFF880704U, 0x0000000BU}, /*FDT_FBABUSIR0*/ + [19] = {0xFF880708U, 0x0000000BU}, /*FDT_FBABUSIR1*/ + [20] = {0xFF88070CU, 0x0000000BU}, /*FDT_FBABUSIR2*/ + [21] = {0xFF880710U, 0x0000000BU}, /*FDT_FBABUSIR3*/ + [22] = {0xFF880714U, 0x0000000BU}, /*FDT_FBABUSIR4*/ + [23] = {0xFF88071CU, 0x0000000BU}, /*FDT_IMP0*/ + [24] = {0xFF880720U, 0x0000000BU}, /*FDT_IMP1*/ + [25] = {0xFF880728U, 0x0000000BU}, /*FDT_DSPD*/ + [26] = {0xFF88072CU, 0x0000000BU}, /*FDT_DSPP*/ + [27] = {0xFC610714U, 0x00000008U}, /*FDT_RGX0*/ + [28] = {0xFDC20204U, 0x00000008U}, /*FDT_AXRT2AXRC*/ + [29] = {0xFDC2020CU, 0x00000008U}, /*FDT_DCLS_ICUMX*/ + [30] = {0xFDC20210U, 0x00000008U}, /*FDT_ICUMX*/ + [31] = {0xFDC20704U, 0x00000008U}, /*FDT_CR0*/ + [32] = {0xFD430700U, 0x00000008U}, /*FDT_PERI_RTDM0*/ + [33] = {0xFD430704U, 0x00000008U}, /*FDT_PERI_RTDM1*/ + [34] = {0xFD430708U, 0x00000008U}, /*FDT_PERI_RTDM2*/ + [35] = {0xFD43070CU, 0x00000008U}, /*FDT_PERI_RTDM3*/ + [36] = {0xFD440700U, 0x00000008U}, /*FDT_AXRC2AXRT*/ + [37] = {0xFD440708U, 0x00000008U}, /*FDT_BUS_RTDM0M*/ + [38] = {0xFD44070CU, 0x00000008U}, /*FDT_BUS_RTDM1M*/ + [39] = {0xFD440710U, 0x00000008U}, /*FDT_BUS_RTDM2M*/ + [40] = {0xFD440714U, 0x00000008U}, /*FDT_BUS_RTDM3M*/ + [41] = {0xFD440718U, 0x00000008U}, /*FDT_CR52SS0*/ + [42] = {0xFD44071CU, 0x00000008U}, /*FDT_CSD*/ + [43] = {0xFD440724U, 0x00000008U}, /*FDT_INTAP0*/ + [44] = {0xFD440728U, 0x00000008U}, /*FDT_MEM_RTDM0*/ + [45] = {0xFD44072CU, 0x00000008U}, /*FDT_MEM_RTDM1*/ + [46] = {0xFD440730U, 0x00000008U}, /*FDT_MEM_RTDM2*/ + [47] = {0xFD440734U, 0x00000008U}, /*FDT_MEM_RTDM3*/ + [48] = {0xFD44075CU, 0x00000008U}, /*FDT_CR52SS1*/ + [49] = {0xFD440760U, 0x00000008U}, /*FDT_CR52SS2*/ + [50] = {0xFF860704U, 0x00000008U}, /*FDT_AXRT2AXSC*/ + [51] = {0xFF860708U, 0x00000008U}, /*FDT_AXSM2AXSC*/ + [52] = {0xFF86070CU, 0x00000008U}, /*FDT_AXSN2AXSC*/ + [53] = {0xFF860714U, 0x00000008U}, /*FDT_CCI*/ + [54] = {0xFF860718U, 0x00000008U}, /*FDT_FBABUSTOP0*/ + [55] = {0xFF86071CU, 0x00000008U}, /*FDT_FBABUSTOP1*/ + [56] = {0xFCB80704U, 0x00000006U}, /*FDT_PERI_SYDM1*/ + [57] = {0xFCB80708U, 0x00000006U}, /*FDT_PERI_SYDM2*/ + [58] = {0xFDDC0700U, 0x00000008U}, /*FDT_AXMM2AXSN*/ + [59] = {0xFF800700U, 0x00000008U}, /*FDT_AXIMP02AXSN*/ + [60] = {0xFF800704U, 0x00000008U}, /*FDT_AXSC2AXSN*/ + [61] = {0xFF800708U, 0x00000008U}, /*FDT_AXSP02AXSN*/ + [62] = {0xFF80070CU, 0x00000008U}, /*FDT_AXHC2AXSN*/ + [63] = {0xFCB50708U, 0x00000006U}, /*FDT_BUS_SYDM1*/ + [64] = {0xFCB5070CU, 0x00000006U}, /*FDT_BUS_SYDM2*/ + [65] = {0xFCB50710U, 0x00000004U}, /*FDT_FRAY*/ + [66] = {0xFCB50714U, 0x00000006U}, /*FDT_IPC*/ + [67] = {0xFCB50718U, 0x00000006U}, /*FDT_MEM_SYDM1*/ + [68] = {0xFCB5071CU, 0x00000006U}, /*FDT_MEM_SYDM2*/ + [69] = {0xFCB50720U, 0x00000006U}, /*FDT_SDHI0*/ + [70] = {0xFF810700U, 0x00000008U}, /*FDT_AXMM2AXSTM*/ + [71] = {0xFF810704U, 0x00000008U}, /*FDT_CSDE0*/ + [72] = {0xFF810708U, 0x00000008U}, /*FDT_CSDE1*/ + [73] = {0xFC080704U, 0x00000006U}, /*FDT_FBABUSVC*/ + [74] = {0xFC080708U, 0x0000000AU}, /*FDT_FCPCS*/ + [75] = {0xFC08070CU, 0x0000000AU}, /*FDT_IMR20*/ + [76] = {0xFC080710U, 0x0000000AU}, /*FDT_IMR00*/ + [77] = {0xFC080714U, 0x0000000AU}, /*FDT_IMR01*/ + [78] = {0xFC080718U, 0x0000000AU}, /*FDT_IMR21*/ + [79] = {0xFC080724U, 0x0000000AU}, /*FDT_IMR10*/ + [80] = {0xFC080728U, 0x0000000AU}, /*FDT_IMR11*/ + [81] = {0xFC080740U, 0x0000000AU}, /*FDT_IMS0*/ + [82] = {0xFC080744U, 0x0000000AU}, /*FDT_IMS1*/ + [83] = {0xFC080748U, 0x0000000AU}, /*FDT_IV1ES*/ + [84] = {0xFC9E0700U, 0x00000005U}, /*FDT_DSITXLINK0*/ + [85] = {0xFC9E0704U, 0x00000005U}, /*FDT_DSITXLINK1*/ + [86] = {0xFC9E0708U, 0x00000008U}, /*FDT_FBABUSVIO*/ + [87] = {0xFC9E0714U, 0x00000008U}, /*FDT_FCPVD0*/ + [88] = {0xFC9E0718U, 0x00000008U}, /*FDT_FCPVD1*/ + [89] = {0xFC9E071CU, 0x00000008U}, /*FDT_FCPVX0*/ + [90] = {0xFC9E0720U, 0x00000008U}, /*FDT_FCPVX1*/ + [91] = {0xFC9F0210U, 0x00000008U}, /*FDT_AXVI12AXVI*/ + [92] = {0xFC9F0700U, 0x0000000EU}, /*FDT_ISP02*/ + [93] = {0xFC9F0704U, 0x0000000EU}, /*FDT_ISP03*/ + [94] = {0xFC9F0708U, 0x0000000EU}, /*FDT_ISP04*/ + [95] = {0xFC9F0710U, 0x0000000EU}, /*FDT_VIN0*/ + [96] = {0xFC9F0714U, 0x0000000EU}, /*FDT_VIN1*/ + [97] = {0xFC9F0720U, 0x0000000EU}, /*FDT_ISP00*/ + [98] = {0xFC9F0724U, 0x0000000EU}, /*FDT_ISP01*/ + [99] = {0xFC9F0728U, 0x0000000EU}, /*FDT_ISP10*/ + [100] = {0xFC9F072CU, 0x0000000EU}, /*FDT_ISP11*/ + [101] = {0xFC9F0744U, 0x0000000EU}, /*FDT_ISP12*/ + [102] = {0xFC9F074CU, 0x0000000EU}, /*FDT_ISP13*/ + [103] = {0xFC9F0750U, 0x0000000EU}, /*FDT_ISP14*/ + [104] = {0xFC310704U, 0x00000006U}, /*FDT_FBABUSVIP0*/ + [105] = {0xFC310710U, 0x0000000BU}, /*FDT_SMPO0*/ + [106] = {0xFC310718U, 0x0000000BU}, /*FDT_SMPS0*/ + [107] = {0xFC31071CU, 0x0000000BU}, /*FDT_UMFL0*/ + [108] = {0xFC340700U, 0x0000000BU}, /*FDT_AXVIP02AXVIP1*/ + [109] = {0xFC340718U, 0x0000000BU}, /*FDT_PAP*/ + [110] = {0xFC340728U, 0x00000006U}, /*FDT_FBABUSVIP1*/ + [111] = {0xFC400200U, 0x0000000BU}, /*FDT_AXIMP02AXDSP*/ + [112] = {0xFC400204U, 0x0000000BU}, /*FDT_DSP00*/ + [113] = {0xFC400208U, 0x0000000BU}, /*FDT_DSP01*/ + [114] = {0xFC40020CU, 0x0000000BU}, /*FDT_DSP10*/ + [115] = {0xFC400210U, 0x0000000BU}, /*FDT_DSP11*/ + [116] = {0xFC400214U, 0x0000000BU}, /*FDT_DSP20*/ + [117] = {0xFC400218U, 0x0000000BU}, /*FDT_DSP21*/ + [118] = {0xFC40021CU, 0x0000000BU}, /*FDT_DSP30*/ + [119] = {0xFC400220U, 0x0000000BU}, /*FDT_DSP31*/ +}; + +const CONFIGURATION_SETTING_TABLE g_inten_tbl[INTEN_REG_MAX] = { + [0] = {0xFF8403C0U, 0x00033E4CU}, /* FIXINTENTOP00 */ + [1] = {0xFDA723C0U, 0x00000003U}, /* FIXINTENTOP10 */ + [2] = {0xFF8483C0U, 0x00000007U}, /* FIXINTENTOP20 */ + [3] = {0xFF8443C0U, 0x000000FFU}, /* FIXINTENTOP30 */ + [4] = {0xFDDFC3C0U, 0x000000FAU}, /* FIXINTENMM0 */ + [5] = {0xFD8003C0U, 0x0DFFEFFFU}, /* FIXINTENRT00 */ + [6] = {0xFD8003C4U, 0x00042000U}, /* FIXINTENRT01 */ + [7] = {0xFD8043C0U, 0x000000FFU}, /* FIXINTENRT10 */ + [8] = {0xFD8083C0U, 0x000000FFU}, /* FIXINTENRT20 */ + [9] = {0xFD80C3C0U, 0x00000003U}, /* FIXINTENRT30 */ + [10] = {0xFCB303C0U, 0x001FDFC0U}, /* FIXINTENPER000 */ + [11] = {0xFCB343C0U, 0x0000000FU}, /* FIXINTENPER010 */ + [12] = {0xFCB383C0U, 0x0000000FU}, /* FIXINTENPER020 */ + [13] = {0xFCB3C3C0U, 0x0000000FU}, /* FIXINTENPER030 */ + [14] = {0xFCE903C0U, 0x638353FBU}, /* FIXINTENHSC0 */ + [15] = {0xFCE903C4U, 0x00000000U}, /* FIXINTENHSC1 */ + [16] = {0xFC8F83C0U, 0xB0006660U}, /* FIXINTENVIO00 */ + [17] = {0xFC8F83C4U, 0x00018001U}, /* FIXINTENVIO01 */ + [18] = {0xFC8F03C0U, 0xF980000FU}, /* FIXINTENVIO10 */ + [19] = {0xFC8F03C4U, 0x00000039U}, /* FIXINTENVIO11 */ + [20] = {0xFC8FC3C0U, 0x00000003U}, /* FIXINTENVIO20 */ + [21] = {0xFC0103C0U, 0x7AF6ABABU}, /* FIXINTENVC00 */ + [22] = {0xFC0183C0U, 0x00000003U}, /* FIXINTENVC10 */ + [23] = {0xFF8E03C0U, 0x03C3E00FU}, /* FIXINTENIR0 */ + [24] = {0xFC2F03C0U, 0x0000026FU}, /* FIXINTENVIP00 */ + [25] = {0xFC2F83C0U, 0x000010E1U}, /* FIXINTENVIP10 */ + [26] = {0xFC6403C0U, 0x00000007U}, /* FIXINTEN3DG0 */ + [27] = {0xFC4803C0U, 0x0003FFFFU}, /* FIXINTENDSP0 */ + [28] = {0xFF840440U, 0xC5400001U}, /* EDCINTENTOP00 */ + [29] = {0xFF840444U, 0x81FDBB0FU}, /* EDCINTENTOP01 */ + [30] = {0xFF840448U, 0x0000000FU}, /* EDCINTENTOP02 */ + [31] = {0xFDA72440U, 0xFFDFFFFFU}, /* EDCINTENTOP10 */ + [32] = {0xFDA72444U, 0x003FBFFFU}, /* EDCINTENTOP11 */ + [33] = {0xFF848440U, 0x00000003U}, /* EDCINTENTOP20 */ + [34] = {0xFF844440U, 0x0000003FU}, /* EDCINTENTOP30 */ + [35] = {0xFDDFC440U, 0xFFFFFFFFU}, /* EDCINTENMM0 */ + [36] = {0xFDDFC444U, 0xFFFFFFFFU}, /* EDCINTENMM1 */ + [37] = {0xFDDFC448U, 0xFFFFFFFFU}, /* EDCINTENMM2 */ + [38] = {0xFDDFC44CU, 0xFFFFFFFFU}, /* EDCINTENMM3 */ + [39] = {0xFDDFC450U, 0x03FFFFFFU}, /* EDCINTENMM4 */ + [40] = {0xFD800440U, 0x3F7F87FFU}, /* EDCINTENRT00 */ + [41] = {0xFD800444U, 0x001DF804U}, /* EDCINTENRT01 */ + [42] = {0xFD800448U, 0xFFFFFC2FU}, /* EDCINTENRT02 */ + [43] = {0xFD80044CU, 0xFEF3FFFFU}, /* EDCINTENRT03 */ + [44] = {0xFD800450U, 0x6DFDDFF7U}, /* EDCINTENRT04 */ + [45] = {0xFD800454U, 0xFFC001FFU}, /* EDCINTENRT05 */ + [46] = {0xFD808440U, 0x00007FFFU}, /* EDCINTENRT20 */ + [47] = {0xFD80C440U, 0xFFFFFFFFU}, /* EDCINTENRT30 */ + [48] = {0xFD80C444U, 0x00000003U}, /* EDCINTENRT31 */ + [49] = {0xFCB30440U, 0x80800000U}, /* EDCINTENPER000 */ + [50] = {0xFCB30444U, 0x0000000EU}, /* EDCINTENPER001 */ + [51] = {0xFCB30448U, 0xFFF81E80U}, /* EDCINTENPER002 */ + [52] = {0xFCB3044CU, 0xFFFF03FFU}, /* EDCINTENPER003 */ + [53] = {0xFCB30450U, 0x87F7BFFEU}, /* EDCINTENPER004 */ + [54] = {0xFCB30454U, 0xEC01003FU}, /* EDCINTENPER005 */ + [55] = {0xFCB30458U, 0x2007FFFFU}, /* EDCINTENPER006 */ + [56] = {0xFCB3045CU, 0x00000180U}, /* EDCINTENPER007 */ + [57] = {0xFCB34440U, 0xFFF7E7EAU}, /* EDCINTENPER010 */ + [58] = {0xFCB34444U, 0x0000000FU}, /* EDCINTENPER011 */ + [59] = {0xFCB38440U, 0xFFFFFFFFU}, /* EDCINTENPER020 */ + [60] = {0xFCB3C440U, 0xFFFFFFFFU}, /* EDCINTENPER030 */ + [61] = {0xFCB3C444U, 0xFFFFFFFFU}, /* EDCINTENPER031 */ + [62] = {0xFCB3C448U, 0x0000FFFFU}, /* EDCINTENPER032 */ + [63] = {0xFCE90440U, 0xFF9FFFFFU}, /* EDCINTENHSC0 */ + [64] = {0xFCE90444U, 0x19067733U}, /* EDCINTENHSC1 */ + [65] = {0xFCE90448U, 0xC190607CU}, /* EDCINTENHSC2 */ + [66] = {0xFCE9044CU, 0xA6F8C631U}, /* EDCINTENHSC3 */ + [67] = {0xFCE90450U, 0x11D31923U}, /* EDCINTENHSC4 */ + [68] = {0xFCE90454U, 0x00000001U}, /* EDCINTENHSC5 */ + [69] = {0xFC8F8440U, 0x00FEFFFFU}, /* EDCINTENVIO00 */ + [70] = {0xFC8F8444U, 0x0FFFFFFFU}, /* EDCINTENVIO01 */ + [71] = {0xFC8F8448U, 0x00000000U}, /* EDCINTENVIO02 */ + [72] = {0xFC8F844CU, 0xCCCCC000U}, /* EDCINTENVIO03 */ + [73] = {0xFC8F8450U, 0x070F0CF0U}, /* EDCINTENVIO04 */ + [74] = {0xFC8F8454U, 0xC0000000U}, /* EDCINTENVIO05 */ + [75] = {0xFC8F8458U, 0x007F2080U}, /* EDCINTENVIO06 */ + [76] = {0xFC8F0440U, 0xCF010300U}, /* EDCINTENVIO10 */ + [77] = {0xFC8F0444U, 0xFFFF0000U}, /* EDCINTENVIO11 */ + [78] = {0xFC8F0448U, 0xFFFF0000U}, /* EDCINTENVIO12 */ + [79] = {0xFC8F044CU, 0xE67CFFCCU}, /* EDCINTENVIO13 */ + [80] = {0xFC8F0450U, 0xC927CF3FU}, /* EDCINTENVIO14 */ + [81] = {0xFC8F0454U, 0x1DE3797FU}, /* EDCINTENVIO15 */ + [82] = {0xFC8F0458U, 0x1F800000U}, /* EDCINTENVIO16 */ + [83] = {0xFC8FC440U, 0x000FDFEFU}, /* EDCINTENVIO20 */ + [84] = {0xFC010440U, 0x0011EC01U}, /* EDCINTENVC00 */ + [85] = {0xFC010444U, 0xF3EFCE30U}, /* EDCINTENVC01 */ + [86] = {0xFC010448U, 0xFFFFFE5BU}, /* EDCINTENVC02 */ + [87] = {0xFC01044CU, 0xFFFFFFFFU}, /* EDCINTENVC03 */ + [88] = {0xFC010450U, 0x0000003FU}, /* EDCINTENVC04 */ + [89] = {0xFC018440U, 0x00000FFFU}, /* EDCINTENVC10 */ + [90] = {0xFF8E0440U, 0x00073FFFU}, /* EDCINTENIR0 */ + [91] = {0xFF8E0444U, 0xF983FFD8U}, /* EDCINTENIR1 */ + [92] = {0xFF8E0448U, 0xFFF3FFFFU}, /* EDCINTENIR2 */ + [93] = {0xFF8E044CU, 0x0F8000FFU}, /* EDCINTENIR3 */ + [94] = {0xFC2F0440U, 0x00000177U}, /* EDCINTENVIP00 */ + [95] = {0xFC2F0444U, 0xF3BE0000U}, /* EDCINTENVIP01 */ + [96] = {0xFC2F0448U, 0x001F7BF8U}, /* EDCINTENVIP02 */ + [97] = {0xFC2F044CU, 0x00000000U}, /* EDCINTENVIP03 */ + [98] = {0xFC2F0450U, 0x18000000U}, /* EDCINTENVIP04 */ + [99] = {0xFC2F0454U, 0x0000FBFBU}, /* EDCINTENVIP05 */ + [100] = {0xFC2F8440U, 0xFFE18430U}, /* EDCINTENVIP10 */ + [101] = {0xFC2F8444U, 0xF87C3FF0U}, /* EDCINTENVIP11 */ + [102] = {0xFC2F8448U, 0x00000007U}, /* EDCINTENVIP12 */ + [103] = {0xFC640440U, 0xFBFC07FFU}, /* EDCINTEN3DG0 */ + [104] = {0xFC640444U, 0x0081FC47U}, /* EDCINTEN3DG1 */ + [105] = {0xFC480440U, 0x03FFFFFFU}, /* EDCINTENDSP0 */ + [106] = {0xFF840680U, 0x000F3F82U}, /* ICISTPINTENTOP00 */ + [107] = {0xFDA72680U, 0x00000003U}, /* ICISTPINTENTOP10 */ + [108] = {0xFF848680U, 0x00000007U}, /* ICISTPINTENTOP20 */ + [109] = {0xFF844680U, 0x000000FFU}, /* ICISTPINTENTOP30 */ + [110] = {0xFDDFC680U, 0x000FFFFFU}, /* ICISTPINTENMM0 */ + [111] = {0xFD800680U, 0x0E007FFFU}, /* ICISTPINTENRT00 */ + [112] = {0xFD804680U, 0x000001FFU}, /* ICISTPINTENRT10 */ + [113] = {0xFD808680U, 0x00000007U}, /* ICISTPINTENRT20 */ + [114] = {0xFD80C680U, 0x00000003U}, /* ICISTPINTENRT30 */ + [115] = {0xFCB30680U, 0x00023FF0U}, /* ICISTPINTENPER000 */ + [116] = {0xFCB34680U, 0x0000000FU}, /* ICISTPINTENPER010 */ + [117] = {0xFCB38680U, 0x00000003U}, /* ICISTPINTENPER020 */ + [118] = {0xFCB3C680U, 0x00000003U}, /* ICISTPINTENPER030 */ + [119] = {0xFCE90680U, 0x000001E7U}, /* ICISTPINTENHSC0 */ + [120] = {0xFC8F8680U, 0x00000013U}, /* ICISTPINTENVIO00 */ + [121] = {0xFC8F0680U, 0x0000003FU}, /* ICISTPINTENVIO10 */ + [122] = {0xFC8FC680U, 0x00000003U}, /* ICISTPINTENVIO20 */ + [123] = {0xFC010680U, 0x0000003FU}, /* ICISTPINTENVC00 */ + [124] = {0xFC018680U, 0x00000003U}, /* ICISTPINTENVC10 */ + [125] = {0xFF8E0680U, 0x0000FFC3U}, /* ICISTPINTENIR0 */ + [126] = {0xFC2F0680U, 0x0000001FU}, /* ICISTPINTENVIP00 */ + [127] = {0xFC2F8680U, 0x0000003FU}, /* ICISTPINTENVIP10 */ + [128] = {0xFC640680U, 0x0000000FU}, /* ICISTPINTEN3DG0 */ + [129] = {0xFC480680U, 0x000000FFU}, /* ICISTPINTENDSP0 */ + [130] = {0xFF840580U, 0x0000003CU}, /* DCLSINTENTOP00 */ + [131] = {0xFDA72580U, 0x00000003U}, /* DCLSINTENTOP10 */ + [132] = {0xFF848580U, 0x00000003U}, /* DCLSINTENTOP20 */ + [133] = {0xFF844580U, 0x00000003U}, /* DCLSINTENTOP30 */ + [134] = {0xFDDFC580U, 0x3FFFFFF7U}, /* DCLSINTENMM0 */ + [135] = {0xFDDFC584U, 0x00000080U}, /* DCLSINTENMM1 */ + [136] = {0xFD800580U, 0x01FFFFFFU}, /* DCLSINTENRT00 */ + [137] = {0xFD800584U, 0x0000003EU}, /* DCLSINTENRT01 */ + [138] = {0xFD808580U, 0x0000003FU}, /* DCLSINTENRT20 */ + [139] = {0xFD80C580U, 0x00000003U}, /* DCLSINTENRT30 */ + [140] = {0xFCB30580U, 0x039FFFC0U}, /* DCLSINTENPER000 */ + [141] = {0xFCB34580U, 0x0000000AU}, /* DCLSINTENPER010 */ + [142] = {0xFCB38580U, 0x0000000FU}, /* DCLSINTENPER020 */ + [143] = {0xFCB3C580U, 0x000000FFU}, /* DCLSINTENPER030 */ + [144] = {0xFCE90580U, 0x1FFFC23FU}, /* DCLSINTENHSC0 */ + [145] = {0xFC8F8580U, 0x7207FF0CU}, /* DCLSINTENVIO00 */ + [146] = {0xFC8F0580U, 0x0DFBC03FU}, /* DCLSINTENVIO10 */ + [147] = {0xFC8FC580U, 0x00000003U}, /* DCLSINTENVIO20 */ + [148] = {0xFC010580U, 0x03FAF7E7U}, /* DCLSINTENVC00 */ + [149] = {0xFC018580U, 0x00000003U}, /* DCLSINTENVC10 */ + [150] = {0xFF8E0580U, 0x0FFF9F60U}, /* DCLSINTENIR0 */ + [151] = {0xFC2F0580U, 0xE00003E7U}, /* DCLSINTENVIP00 */ + [152] = {0xFC2F0584U, 0x0000003FU}, /* DCLSINTENVIP01 */ + [153] = {0xFC2F8580U, 0x00000C3FU}, /* DCLSINTENVIP10 */ + [154] = {0xFC480580U, 0x00000003U}, /* DCLSINTENDSP0 */ + [155] = {0xFF840480U, 0xF99F00F0U}, /* LSCHKINTENTOP00 */ + [156] = {0xFF840484U, 0x0003E67FU}, /* LSCHKINTENTOP01 */ + [157] = {0xFDA72480U, 0x00000003U}, /* LSCHKINTENTOP10 */ + [158] = {0xFF848480U, 0x0000001FU}, /* LSCHKINTENTOP20 */ + [159] = {0xFF844480U, 0x000FFFFFU}, /* LSCHKINTENTOP30 */ + [160] = {0xFDDFC480U, 0xFFFFFFFFU}, /* LSCHKINTENMM0 */ + [161] = {0xFDDFC484U, 0x000003FFU}, /* LSCHKINTENMM1 */ + [162] = {0xFD800480U, 0x7FFFFF7FU}, /* LSCHKINTENRT00 */ + [163] = {0xFD800484U, 0x001FFFFFU}, /* LSCHKINTENRT01 */ + [164] = {0xFD800488U, 0x04C4C000U}, /* LSCHKINTENRT02 */ + [165] = {0xFD804480U, 0x003FC7F8U}, /* LSCHKINTENRT10 */ + [166] = {0xFD808480U, 0x000003FFU}, /* LSCHKINTENRT20 */ + [167] = {0xFD80C480U, 0x00000003U}, /* LSCHKINTENRT30 */ + [168] = {0xFCB30480U, 0xDFFFDF00U}, /* LSCHKINTENPER000 */ + [169] = {0xFCB30484U, 0x00000CFFU}, /* LSCHKINTENPER001 */ + [170] = {0xFCB34480U, 0x000000FFU}, /* LSCHKINTENPER010 */ + [171] = {0xFCB38480U, 0x0000000FU}, /* LSCHKINTENPER020 */ + [172] = {0xFCB3C480U, 0x0000000FU}, /* LSCHKINTENPER030 */ + [173] = {0xFCE90480U, 0x1F863FFFU}, /* LSCHKINTENHSC0 */ + [174] = {0xFCE90484U, 0x00000C3CU}, /* LSCHKINTENHSC1 */ + [175] = {0xFC8F8480U, 0xF99F333FU}, /* LSCHKINTENVIO00 */ + [176] = {0xFC8F8484U, 0x000E0403U}, /* LSCHKINTENVIO01 */ + [177] = {0xFC8F0480U, 0xE0040003U}, /* LSCHKINTENVIO10 */ + [178] = {0xFC8F0484U, 0x0031F3FCU}, /* LSCHKINTENVIO11 */ + [179] = {0xFC8FC480U, 0x00000003U}, /* LSCHKINTENVIO20 */ + [180] = {0xFC010480U, 0x7EF0ABABU}, /* LSCHKINTENVC00 */ + [181] = {0xFC010484U, 0x00000FDFU}, /* LSCHKINTENVC01 */ + [182] = {0xFC018480U, 0x00000003U}, /* LSCHKINTENVC10 */ + [183] = {0xFF8E0480U, 0x403FF00FU}, /* LSCHKINTENIR0 */ + [184] = {0xFF8E0484U, 0x003F3FFFU}, /* LSCHKINTENIR1 */ + [185] = {0xFC2F0480U, 0x000176DFU}, /* LSCHKINTENVIP00 */ + [186] = {0xFC2F0484U, 0x00060000U}, /* LSCHKINTENVIP01 */ + [187] = {0xFC2F8480U, 0x001C3F87U}, /* LSCHKINTENVIP10 */ + [188] = {0xFC640480U, 0x0000063FU}, /* LSCHKINTEN3DG0 */ + [189] = {0xFC480480U, 0x3FFFFFFFU}, /* LSCHKINTENDSP0 */ + [190] = {0xFF840700U, 0x0000001EU}, /* OTHINTENTOP00 */ + [191] = {0xFDDFC700U, 0x008FCFFFU}, /* OTHINTENMM0 */ + [192] = {0xFD800700U, 0x00FFFFF0U}, /* OTHINTENRT00 */ + [193] = {0xFCB30700U, 0x0000003CU}, /* OTHINTENPER000 */ + [194] = {0xFCE90700U, 0x0000003CU}, /* OTHINTENHSC0 */ + [195] = {0xFC8F8700U, 0x00000000U}, /* OTHINTENVIO00 */ + [196] = {0xFC8F0700U, 0x0000007CU}, /* OTHINTENVIO10 */ + [197] = {0xFC010700U, 0x000000F0U}, /* OTHINTENVC00 */ + [198] = {0xFC018700U, 0x00000000U}, /* OTHINTENVC10 */ + [199] = {0xFF8E0700U, 0x000000F0U}, /* OTHINTENIR0 */ + [200] = {0xFC2F0700U, 0x00000FC0U}, /* OTHINTENVIP00 */ + [201] = {0xFC2F8700U, 0x00000000U}, /* OTHINTENVIP10 */ + [202] = {0xFC640700U, 0x00000024U}, /* OTHINTEN3DG0 */ + [203] = {0xFF840400U, 0xC5000071U}, /* ROUINTENTOP00 */ + [204] = {0xFF840404U, 0xC8FFE7CFU}, /* ROUINTENTOP01 */ + [205] = {0xFF840408U, 0x8000F3E7U}, /* ROUINTENTOP02 */ + [206] = {0xFDA72400U, 0xFFFFFFFFU}, /* ROUINTENTOP10 */ + [207] = {0xFDA72404U, 0x003FFFFFU}, /* ROUINTENTOP11 */ + [208] = {0xFF848400U, 0x00000007U}, /* ROUINTENTOP20 */ + [209] = {0xFF844400U, 0x003FFFFFU}, /* ROUINTENTOP30 */ + [210] = {0xFDDFC400U, 0xFFFFFFFFU}, /* ROUINTENMM0 */ + [211] = {0xFDDFC404U, 0xFFFFFFFFU}, /* ROUINTENMM1 */ + [212] = {0xFDDFC408U, 0xFFFFFFFFU}, /* ROUINTENMM2 */ + [213] = {0xFDDFC40CU, 0x01FFFFFFU}, /* ROUINTENMM3 */ + [214] = {0xFD800400U, 0x007F3FEFU}, /* ROUINTENRT00 */ + [215] = {0xFD800404U, 0x40000040U}, /* ROUINTENRT01 */ + [216] = {0xFD800408U, 0x7BFFFBFFU}, /* ROUINTENRT02 */ + [217] = {0xFD80040CU, 0xFFFFFFFFU}, /* ROUINTENRT03 */ + [218] = {0xFD800410U, 0x6C007F87U}, /* ROUINTENRT04 */ + [219] = {0xFD800414U, 0xFFFFFFFFU}, /* ROUINTENRT05 */ + [220] = {0xFD800418U, 0x05FFFFFFU}, /* ROUINTENRT06 */ + [221] = {0xFD804400U, 0x001FFFFFU}, /* ROUINTENRT10 */ + [222] = {0xFD808400U, 0x000003FFU}, /* ROUINTENRT20 */ + [223] = {0xFD80C400U, 0xFFFFFFFFU}, /* ROUINTENRT30 */ + [224] = {0xFD80C404U, 0x00000003U}, /* ROUINTENRT31 */ + [225] = {0xFCB30400U, 0x00800000U}, /* ROUINTENPER000 */ + [226] = {0xFCB30404U, 0x00000000U}, /* ROUINTENPER001 */ + [227] = {0xFCB30408U, 0xFFF81C80U}, /* ROUINTENPER002 */ + [228] = {0xFCB3040CU, 0xC7F1FFFFU}, /* ROUINTENPER003 */ + [229] = {0xFCB30410U, 0x020FFFFFU}, /* ROUINTENPER004 */ + [230] = {0xFCB30414U, 0xFFBDE010U}, /* ROUINTENPER005 */ + [231] = {0xFCB30418U, 0x01003FFFU}, /* ROUINTENPER006 */ + [232] = {0xFCB3041CU, 0x0000005EU}, /* ROUINTENPER007 */ + [233] = {0xFCB34400U, 0xFFF7FF7EU}, /* ROUINTENPER010 */ + [234] = {0xFCB34404U, 0x0000003FU}, /* ROUINTENPER011 */ + [235] = {0xFCB38400U, 0x0FFFFFFFU}, /* ROUINTENPER020 */ + [236] = {0xFCB3C400U, 0xFFFFFFFFU}, /* ROUINTENPER030 */ + [237] = {0xFCB3C404U, 0xFFFFFFFFU}, /* ROUINTENPER031 */ + [238] = {0xFCB3C408U, 0x000000FFU}, /* ROUINTENPER032 */ + [239] = {0xFCE90400U, 0xFFE1D3FFU}, /* ROUINTENHSC0 */ + [240] = {0xFCE90404U, 0x00106001U}, /* ROUINTENHSC1 */ + [241] = {0xFCE90408U, 0xFFFB9906U}, /* ROUINTENHSC2 */ + [242] = {0xFCE9040CU, 0x7C1F07F9U}, /* ROUINTENHSC3 */ + [243] = {0xFCE90410U, 0x00000CFFU}, /* ROUINTENHSC4 */ + [244] = {0xFC8F8400U, 0xDFFFE1FFU}, /* ROUINTENVIO00 */ + [245] = {0xFC8F8404U, 0x00001003U}, /* ROUINTENVIO01 */ + [246] = {0xFC8F8408U, 0xF8000000U}, /* ROUINTENVIO02 */ + [247] = {0xFC8F840CU, 0x1E18007FU}, /* ROUINTENVIO03 */ + [248] = {0xFC8F8410U, 0xE0786200U}, /* ROUINTENVIO04 */ + [249] = {0xFC8F8414U, 0x0000000FU}, /* ROUINTENVIO05 */ + [250] = {0xFC8F8418U, 0xFFFE0002U}, /* ROUINTENVIO06 */ + [251] = {0xFC8F0400U, 0x200007CFU}, /* ROUINTENVIO10 */ + [252] = {0xFC8F0404U, 0xCF3FE1CEU}, /* ROUINTENVIO11 */ + [253] = {0xFC8F0408U, 0x000079E7U}, /* ROUINTENVIO12 */ + [254] = {0xFC8F040CU, 0x00000000U}, /* ROUINTENVIO13 */ + [255] = {0xFC8F0410U, 0x3C000000U}, /* ROUINTENVIO14 */ + [256] = {0xFC8F0414U, 0x0F038000U}, /* ROUINTENVIO15 */ + [257] = {0xFC8F0418U, 0x0000001CU}, /* ROUINTENVIO16 */ + [258] = {0xFC8FC400U, 0x0003F7FBU}, /* ROUINTENVIO20 */ + [259] = {0xFC010400U, 0x40000000U}, /* ROUINTENVC00 */ + [260] = {0xFC010404U, 0x38001860U}, /* ROUINTENVC01 */ + [261] = {0xFC010408U, 0xF9C003BFU}, /* ROUINTENVC02 */ + [262] = {0xFC01040CU, 0xFFFFF3FFU}, /* ROUINTENVC03 */ + [263] = {0xFC010410U, 0x000001FFU}, /* ROUINTENVC04 */ + [264] = {0xFC018400U, 0x000003FFU}, /* ROUINTENVC10 */ + [265] = {0xFF8E0400U, 0x803F1FC1U}, /* ROUINTENIR0 */ + [266] = {0xFF8E0404U, 0x087E821FU}, /* ROUINTENIR1 */ + [267] = {0xFF8E0408U, 0xFFFF0FC2U}, /* ROUINTENIR2 */ + [268] = {0xFF8E040CU, 0x000001FFU}, /* ROUINTENIR3 */ + [269] = {0xFC2F0400U, 0xF00101E1U}, /* ROUINTENVIP00 */ + [270] = {0xFC2F0404U, 0xBC07C007U}, /* ROUINTENVIP01 */ + [271] = {0xFC2F0408U, 0x00EE97E1U}, /* ROUINTENVIP02 */ + [272] = {0xFC2F040CU, 0x00000000U}, /* ROUINTENVIP03 */ + [273] = {0xFC2F0410U, 0x00000000U}, /* ROUINTENVIP04 */ + [274] = {0xFC2F0414U, 0x01F80000U}, /* ROUINTENVIP05 */ + [275] = {0xFC2F8400U, 0x07FFFFFFU}, /* ROUINTENVIP10 */ + [276] = {0xFC2F8404U, 0x3FFFF03FU}, /* ROUINTENVIP11 */ + [277] = {0xFC640400U, 0x03FC03FFU}, /* ROUINTEN3DG0 */ + [278] = {0xFC640404U, 0x000007FFU}, /* ROUINTEN3DG1 */ + [279] = {0xFC480400U, 0xFFFFFFFFU}, /* ROUINTENDSP0 */ + [280] = {0xFF840500U, 0xC0FEEFFFU}, /* RSCHKINTENTOP00 */ + [281] = {0xFF840504U, 0x603F99FFU}, /* RSCHKINTENTOP01 */ + [282] = {0xFF840508U, 0x0001C000U}, /* RSCHKINTENTOP02 */ + [283] = {0xFDA72500U, 0x00000001U}, /* RSCHKINTENTOP10 */ + [284] = {0xFF848500U, 0x0000001FU}, /* RSCHKINTENTOP20 */ + [285] = {0xFF844500U, 0x00003FFFU}, /* RSCHKINTENTOP30 */ + [286] = {0xFDDFC500U, 0xFFFFFFFFU}, /* RSCHKINTENMM0 */ + [287] = {0xFDDFC504U, 0x00000007U}, /* RSCHKINTENMM1 */ + [288] = {0xFD800500U, 0xFFFFFFFFU}, /* RSCHKINTENRT00 */ + [289] = {0xFD800504U, 0xFFFF8001U}, /* RSCHKINTENRT01 */ + [290] = {0xFD800508U, 0x0000FFE3U}, /* RSCHKINTENRT02 */ + [291] = {0xFD804500U, 0x000007FFU}, /* RSCHKINTENRT10 */ + [292] = {0xFD808500U, 0x000000FFU}, /* RSCHKINTENRT20 */ + [293] = {0xFD80C500U, 0x00000001U}, /* RSCHKINTENRT30 */ + [294] = {0xFCB30500U, 0xFFF10F07U}, /* RSCHKINTENPER000 */ + [295] = {0xFCB30504U, 0x000FBCFFU}, /* RSCHKINTENPER001 */ + [296] = {0xFCB34500U, 0x000000FAU}, /* RSCHKINTENPER010 */ + [297] = {0xFCB38500U, 0x00000003U}, /* RSCHKINTENPER020 */ + [298] = {0xFCB3C500U, 0x0000003FU}, /* RSCHKINTENPER030 */ + [299] = {0xFCE90500U, 0xF3F3FFFFU}, /* RSCHKINTENHSC0 */ + [300] = {0xFCE90504U, 0x001FFFFFU}, /* RSCHKINTENHSC1 */ + [301] = {0xFC8F8500U, 0xFFFFC003U}, /* RSCHKINTENVIO00 */ + [302] = {0xFC8F8504U, 0x3801C03FU}, /* RSCHKINTENVIO01 */ + [303] = {0xFC8F0500U, 0xFF7F3FFFU}, /* RSCHKINTENVIO10 */ + [304] = {0xFC8F0504U, 0x041A001EU}, /* RSCHKINTENVIO11 */ + [305] = {0xFC8FC500U, 0x00000007U}, /* RSCHKINTENVIO20 */ + [306] = {0xFC010500U, 0xFEBB6627U}, /* RSCHKINTENVC00 */ + [307] = {0xFC010504U, 0x000007FFU}, /* RSCHKINTENVC01 */ + [308] = {0xFC018500U, 0x00000007U}, /* RSCHKINTENVC10 */ + [309] = {0xFF8E0500U, 0x3FFFFE00U}, /* RSCHKINTENIR0 */ + [310] = {0xFF8E0504U, 0x0000FFFFU}, /* RSCHKINTENIR1 */ + [311] = {0xFC2F0500U, 0x0000FFFFU}, /* RSCHKINTENVIP00 */ + [312] = {0xFC2F0504U, 0x000FF800U}, /* RSCHKINTENVIP01 */ + [313] = {0xFC2F8500U, 0x000FFFFFU}, /* RSCHKINTENVIP10 */ + [314] = {0xFC640500U, 0x000001C7U}, /* RSCHKINTEN3DG0 */ + [315] = {0xFC480500U, 0x0001FFFFU}, /* RSCHKINTENDSP0 */ + [316] = {0xFF840540U, 0x00000003U}, /* TIDINTENTOP00 */ + [317] = {0xFF848540U, 0x00000007U}, /* TIDINTENTOP20 */ + [318] = {0xFDDFC540U, 0x00003FFFU}, /* TIDINTENMM0 */ + [319] = {0xFD800540U, 0x007FFF7FU}, /* TIDINTENRT00 */ + [320] = {0xFD800544U, 0x00000020U}, /* TIDINTENRT01 */ + [321] = {0xFD804540U, 0x000000FFU}, /* TIDINTENRT10 */ + [322] = {0xFD808540U, 0x0000003FU}, /* TIDINTENRT20 */ + [323] = {0xFCB30540U, 0x0003FFF0U}, /* TIDINTENPER000 */ + [324] = {0xFCB34540U, 0x0000000FU}, /* TIDINTENPER010 */ + [325] = {0xFCE90540U, 0x0638367FU}, /* TIDINTENHSC0 */ + [326] = {0xFC8F8540U, 0xFFF0CFC3U}, /* TIDINTENVIO00 */ + [327] = {0xFC8F8544U, 0x00000003U}, /* TIDINTENVIO01 */ + [328] = {0xFC8F0540U, 0x3C000000U}, /* TIDINTENVIO10 */ + [329] = {0xFC8F0544U, 0x0000003FU}, /* TIDINTENVIO11 */ + [330] = {0xFC010540U, 0x3B77EFD0U}, /* TIDINTENVC00 */ + [331] = {0xFF8E0540U, 0x00FC1F60U}, /* TIDINTENIR0 */ + [332] = {0xFC2F0540U, 0x0000036DU}, /* TIDINTENVIP00 */ + [333] = {0xFC2F8540U, 0x00000610U}, /* TIDINTENVIP10 */ + [334] = {0xFC640540U, 0x00000003U}, /* TIDINTEN3DG0 */ + [335] = {0xFC480540U, 0x00000000U}, /* TIDINTENDSP0 */ + [336] = {0xFF840640U, 0x00000001U}, /* SAFERRINTENTOP00 */ + [337] = {0xFDA72640U, 0x00000001U}, /* SAFERRINTENTOP10 */ + [338] = {0xFF848640U, 0x00000000U}, /* SAFERRINTENTOP20 */ + [339] = {0xFF844640U, 0x00000001U}, /* SAFERRINTENTOP30 */ + [340] = {0xFDDFC640U, 0x00000007U}, /* SAFERRINTENMM0 */ + [341] = {0xFD800640U, 0x0000001DU}, /* SAFERRINTENRT00 */ + [342] = {0xFD804640U, 0x00000001U}, /* SAFERRINTENRT10 */ + [343] = {0xFD808640U, 0x00000001U}, /* SAFERRINTENRT20 */ + [344] = {0xFD80C640U, 0x00000001U}, /* SAFERRINTENRT30 */ + [345] = {0xFCB30640U, 0x00000004U}, /* SAFERRINTENPER000 */ + [346] = {0xFCB34640U, 0x00000001U}, /* SAFERRINTENPER010 */ + [347] = {0xFCB38640U, 0x00000001U}, /* SAFERRINTENPER020 */ + [348] = {0xFCB3C640U, 0x00000001U}, /* SAFERRINTENPER030 */ + [349] = {0xFCE90640U, 0x00000001U}, /* SAFERRINTENHSC0 */ + [350] = {0xFC8F8640U, 0x00000001U}, /* SAFERRINTENVIO00 */ + [351] = {0xFC8F0640U, 0x00000002U}, /* SAFERRINTENVIO10 */ + [352] = {0xFC8FC640U, 0x00000001U}, /* SAFERRINTENVIO20 */ + [353] = {0xFC010640U, 0x00000001U}, /* SAFERRINTENVC00 */ + [354] = {0xFC018640U, 0x00000001U}, /* SAFERRINTENVC10 */ + [355] = {0xFF8E0640U, 0x00000001U}, /* SAFERRINTENIR0 */ + [356] = {0xFC2F0640U, 0x00000001U}, /* SAFERRINTENVIP00 */ + [357] = {0xFC2F8640U, 0x00000001U}, /* SAFERRINTENVIP10 */ + [358] = {0xFC640640U, 0x00000001U}, /* SAFERRINTEN3DG0 */ + [359] = {0xFC480640U, 0x00000001U}, /* SAFERRINTENDSP0 */ + [360] = {0xFF8404C0U, 0x0000007BU}, /* WCRCINTENTOP00 */ + [361] = {0xFDDFC4C0U, 0x07FFFFFFU}, /* WCRCINTENMM0 */ + [362] = {0xFD8004C0U, 0x607FFFFBU}, /* WCRCINTENRT00 */ + [363] = {0xFD8004C4U, 0x0000001CU}, /* WCRCINTENRT01 */ + [364] = {0xFD8044C0U, 0x0000078FU}, /* WCRCINTENRT10 */ + [365] = {0xFD8084C0U, 0x00000001U}, /* WCRCINTENRT20 */ + [366] = {0xFCB304C0U, 0x000037FFU}, /* WCRCINTENPER000 */ + [367] = {0xFCB344C0U, 0x00000003U}, /* WCRCINTENPER010 */ + [368] = {0xFCE904C0U, 0x000FC1ECU}, /* WCRCINTENHSC0 */ + [369] = {0xFC8F84C0U, 0x0000FFC3U}, /* WCRCERRINTENVIO00 */ + [370] = {0xFC8F04C0U, 0x001FC40FU}, /* WCRCERRINTENVIO10 */ + [371] = {0xFC0104C0U, 0x00357D7DU}, /* WCRCERRINTENVC00 */ + [372] = {0xFF8E04C0U, 0x3FFF03F0U}, /* WCRCERRINTENIR0 */ + [373] = {0xFC2F04C0U, 0x070030F5U}, /* WCRCERRINTENVIP00 */ + [374] = {0xFC2F84C0U, 0x000000F0U}, /* WCRCERRINTENVIP10 */ + [375] = {0xFC6404C0U, 0x00000063U}, /* WCRCERRINTEN3DG0 */ + [376] = {0xFC4804C0U, 0x3FFF03F0U}, /* WCRCINTENDSP0 */ + [377] = {0xFF840600U, 0x00000001U}, /* SECERRINTENTOP00 */ + [378] = {0xFDA72600U, 0x00000001U}, /* SECERRINTENTOP10 */ + [379] = {0xFF848600U, 0x00000000U}, /* SECERRINTENTOP20 */ + [380] = {0xFF844600U, 0x00000001U}, /* SECERRINTENTOP30 */ + [381] = {0xFDDFC600U, 0x00000007U}, /* SECERRINTENMM0 */ + [382] = {0xFD800600U, 0x0000001DU}, /* SECERRINTENRT00 */ + [383] = {0xFD804600U, 0x00000001U}, /* SECERRINTENRT10 */ + [384] = {0xFD808600U, 0x00000001U}, /* SECERRINTENRT20 */ + [385] = {0xFD80C600U, 0x00000001U}, /* SECERRINTENRT30 */ + [386] = {0xFCB30600U, 0x00000004U}, /* SECERRINTENPER000 */ + [387] = {0xFCB34600U, 0x00000001U}, /* SECERRINTENPER010 */ + [388] = {0xFCB38600U, 0x00000001U}, /* SECERRINTENPER020 */ + [389] = {0xFCB3C600U, 0x00000001U}, /* SECERRINTENPER030 */ + [390] = {0xFCE90600U, 0x00000001U}, /* SECERRINTENHSC0 */ + [391] = {0xFC8F8600U, 0x00000001U}, /* SECERRINTENVIO00 */ + [392] = {0xFC8F0600U, 0x00000002U}, /* SECERRINTENVIO10 */ + [393] = {0xFC8FC600U, 0x00000001U}, /* SECERRINTENVIO20 */ + [394] = {0xFC010600U, 0x00000001U}, /* SECERRINTENVC00 */ + [395] = {0xFC018600U, 0x00000001U}, /* SECERRINTENVC10 */ + [396] = {0xFF8E0600U, 0x00007FFFU}, /* SECERRINTENIR0 */ + [397] = {0xFC2F0600U, 0x00000001U}, /* SECERRINTENVIP00 */ + [398] = {0xFC2F8600U, 0x00000001U}, /* SECERRINTENVIP10 */ + [399] = {0xFC640600U, 0x00000001U}, /* SECERRINTEN3DG0 */ + [400] = {0xFC480600U, 0x00000001U}, /* SECERRINTENDSP0 */ +}; + +const REGION_ID_SETTING_TABLE g_imp_rgid_m_tbl[IMP_MASTER_MAX] = { + [0] = {0xFFA8E270U, 0x00010202U}, /* SPMI BMATTR00 */ + [1] = {0xFFA8E274U, 0x00010202U}, /* SPMI BMATTR01 */ + [2] = {0xFFA8E278U, 0x00010202U}, /* SPMI BMATTR02 */ + [3] = {0xFFA8E27CU, 0x00010202U}, /* SPMI BMATTR03 */ + [4] = {0xFFA8E280U, 0x00010202U}, /* SPMI BMATTR04 */ + [5] = {0xFFA8E284U, 0x00010202U}, /* SPMI BMATTR05 */ + [6] = {0xFFA8E288U, 0x00010202U}, /* SPMI BMATTR06 */ + [7] = {0xFFA8E28CU, 0x00010202U}, /* SPMI BMATTR07 */ + [8] = {0xFFA8E290U, 0x00010202U}, /* SPMI BMATTR08 */ + [9] = {0xFFA8E294U, 0x00010202U}, /* SPMI BMATTR09 */ + [10] = {0xFFA8E298U, 0x00010202U}, /* SPMI BMATTR10 */ + [11] = {0xFFA8E29CU, 0x00010202U}, /* SPMI BMATTRSP0 */ + [12] = {0xFFAB2270U, 0x00010202U}, /* SPMC BMATTR00 */ + [13] = {0xFFAB2274U, 0x00010202U}, /* SPMC BMATTR01 */ + [14] = {0xFFAB2278U, 0x00010202U}, /* SPMC BMATTR02 */ + [15] = {0xFFAB227CU, 0x00010202U}, /* SPMC BMATTR03 */ + [16] = {0xFFAB2280U, 0x00010202U}, /* SPMC BMATTR04 */ + [17] = {0xFFAB2284U, 0x00010202U}, /* SPMC BMATTR05 */ + [18] = {0xFFAB2288U, 0x00010202U}, /* SPMC BMATTR06 */ +}; + +const REGION_ID_SETTING_TABLE g_imp_rgid_s_tbl[IMP_SLAVE_MAX] = { + [0] = {0xFF902100U, 0x004E004FU}, /* IMPSLV RCR0 */ + [1] = {0xFF902108U, 0x004E004FU}, /* IMPSLV RCR2 */ + [2] = {0xFFAB2100U, 0x004E004FU}, /* SPMC RCR0 */ + [3] = {0xFFAB2110U, 0x004E004FU}, /* SPMC RC00 */ + [4] = {0xFFAB2114U, 0x004E004FU}, /* SPMC RC01 */ + [5] = {0xFFAB2118U, 0x004E004FU}, /* SPMC RC02 */ + [6] = {0xFFAB2200U, 0x004E004FU}, /* SPMC RCB0 */ + [7] = {0xFFAB2204U, 0x004E004FU}, /* SPMC RCB1 */ + [8] = {0xFFAB2208U, 0x004E004FU}, /* SPMC RCB2 */ + [9] = {0xFFAB220CU, 0x004E004FU}, /* SPMC RCB3 */ + [10] = {0xFFAB2210U, 0x004E004FU}, /* SPMC RCB4 */ + [11] = {0xFFAB2104U, 0x004E004FU}, /* SPMC RCR1 */ + [12] = {0xFFA8E100U, 0x004E004FU}, /* SPMI RCR0 */ + [13] = {0xFFA8E110U, 0x004E004FU}, /* SPMI RC00 */ + [14] = {0xFFA8E114U, 0x004E004FU}, /* SPMI RC01 */ + [15] = {0xFFA8E118U, 0x004E004FU}, /* SPMI RC02 */ + [16] = {0xFFA8E11CU, 0x004E004FU}, /* SPMI RC03 */ + [17] = {0xFFA8E120U, 0x004E004FU}, /* SPMI RC04 */ + [18] = {0xFFA8E124U, 0x004E004FU}, /* SPMI RC05 */ + [19] = {0xFFA8E128U, 0x004E004FU}, /* SPMI RC06 */ + [20] = {0xFFA8E12CU, 0x004E004FU}, /* SPMI RC07 */ + [21] = {0xFFA8E130U, 0x004E004FU}, /* SPMI RC08 */ + [22] = {0xFFA8E134U, 0x004E004FU}, /* SPMI RC09 */ + [23] = {0xFFA8E138U, 0x004E004FU}, /* SPMI RC10 */ + [24] = {0xFFA8E13CU, 0x004E004FU}, /* SPMI RC11 */ + [25] = {0xFFA8E140U, 0x004E004FU}, /* SPMI RC12 */ + [26] = {0xFFA8E144U, 0x004E004FU}, /* SPMI RC13 */ + [27] = {0xFFA8E200U, 0x004E004FU}, /* SPMI RCB0 */ + [28] = {0xFFA8E204U, 0x004E004FU}, /* SPMI RCB1 */ + [29] = {0xFFA8E208U, 0x004E004FU}, /* SPMI RCB2 */ + [30] = {0xFFA8E20CU, 0x004E004FU}, /* SPMI RCB3 */ + [31] = {0xFFA8E210U, 0x004E004FU}, /* SPMI RCB4 */ + [32] = {0xFFA8E214U, 0x004E004FU}, /* SPMI RCB5 */ + [33] = {0xFFA8E218U, 0x004E004FU}, /* SPMI RCB6 */ + [34] = {0xFFA8E21CU, 0x004E004FU}, /* SPMI RCB7 */ + [35] = {0xFFA8E104U, 0x004E004FU}, /* SPMI RCR1 */ + [36] = {0xFF902110U, 0x004E004FU}, /* IMPSLV RC00 */ + [37] = {0xFF902104U, 0x004E004FU}, /* IMPSLV RCR1 */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX] = { + [0] = {0xFC480570U, 0x00000002U}, /* IMRGID_IPMMU_VI0 */ + [1] = {0xFC4C0570U, 0x00000002U}, /* IMRGID_IPMMU_VI1 */ + [2] = {0xFC3C0570U, 0x00000002U}, /* IMRGID_IPMMU_VC0 */ + [3] = {0xFC380570U, 0x00000002U}, /* IMRGID_IPMMU_IR */ + [4] = {0xFC080570U, 0x00000001U}, /* IMRGID_IPMMU_RT0 */ + [5] = {0xFC0C0570U, 0x00000001U}, /* IMRGID_IPMMU_RT1 */ + [6] = {0xFC300570U, 0x00000001U}, /* IMRGID_IPMMU_DS0 */ + [7] = {0xFC340570U, 0x00000001U}, /* IMRGID_IPMMU_HSC */ + [8] = {0xFC500570U, 0x00000002U}, /* IMRGID_IPMMU_VIP0 */ + [9] = {0xFC540570U, 0x00000002U}, /* IMRGID_IPMMU_VIP1 */ + [10] = {0xFC400570U, 0x00000002U}, /* IMRGID_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX] = { + [0] = {0xFC480578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI0 */ + [1] = {0xFC4C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI1 */ + [2] = {0xFC3C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VC0 */ + [3] = {0xFC380578U, 0x00000001U}, /* IMSECGRP_IPMMU_IR */ + [4] = {0xFC080578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT0 */ + [5] = {0xFC0C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT1 */ + [6] = {0xFC300578U, 0x00000001U}, /* IMSECGRP_IPMMU_DS0 */ + [7] = {0xFC340578U, 0x00000001U}, /* IMSECGRP_IPMMU_HSC */ + [8] = {0xFC500578U, 0x00000001U}, /* IMSECGRP_IPMMU_VIP0 */ + [9] = {0xFC540578U, 0x00000001U}, /* IMSECGRP_IPMMU_VIP1 */ + [10] = {0xFC400578U, 0x00000001U}, /* IMSECGRP_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX] = { + [0] = {0xFC480574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI0 */ + [1] = {0xFC4C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI1 */ + [2] = {0xFC3C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VC0 */ + [3] = {0xFC380574U, 0x00000002U}, /* IMRGIDEN_IPMMU_IR */ + [4] = {0xFC080574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT0 */ + [5] = {0xFC0C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT1 */ + [6] = {0xFC300574U, 0x00000002U}, /* IMRGIDEN_IPMMU_DS0 */ + [7] = {0xFC340574U, 0x00000002U}, /* IMRGIDEN_IPMMU_HSC */ + [8] = {0xFC500574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VIP0 */ + [9] = {0xFC540574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VIP1 */ + [10] = {0xFC400574U, 0x00000002U}, /* IMRGIDEN_IPMMU_3DG */ +}; + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4m.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4m.c new file mode 100644 index 0000000..87abef8 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cnf_tbl/cnf_tbl_v4m.c @@ -0,0 +1,3552 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table + ******************************************************************************/ +/****************************************************************************** + * @file cnf_tbl_v4m.c + * - Version : 0.12 + * @brief Configuration table for V4M. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + * : 19.09.2023 0.02 Update setting table according to + * HWUM Rev.0.50. + * : 10.10.2023 0.03 Removed unimplemented registers. + * : 13.11.2023 0.04 Added setting table for CCI MPU GID register. + * : 11.01.2024 0.05 Updated writing privilege to System RAM. + * Fixed setting value of read/write permissions + * for RT-VRAM1 area2. + * Update Region ID settings. + * The divided areas of SDRAM have been changed. + * : 17.07.2024 0.06 Removed FDT_PAP in g_fdt_tbl. + * : 11.10.2024 0.07 Updated Region ID and RAM protection setting + * for QNX. + * : 12.11.2024 0.08 Updated AXI timeout setting value. + * : 05.12.2024 0.09 Update RAM protection settings for ICCOM + * memory area (SDRAM Area5). + * Update Region ID settings for VSPD and VSPX. + * Update Region ID settings for IPMMU. + * : 16.12.2024 0.10 Updated Region ID setting. + * Updated Region ID setting and RAM protection + * setting for booting CR52 3 cores. + * Updated AXI timeout setting value. + * Update Region ID settings for ISP ch1. + * Update Region ID settings for PCI1. + * Added IPMMU Region ID table. + * : 17.03.2025 0.11 Updated AXI timeout setting value. + * : 26.05.2025 0.12 Updated RAM protection settings for + * protection area. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#define RTDMA_EN (0x00000002U) +#define SYSDMA_EN (0x00003FF4U) + +#pragma ghs section rodata=".qosbw_tbl" +/* not used for V4M */ +const QOS_SETTING_TABLE g_qosbw_tbl[] = {0}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".qoswt_tbl" +/* not used for V4M */ +const QOS_SETTING_TABLE g_qoswt_tbl[] = {0}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_m_tbl" +const REGION_ID_SETTING_TABLE g_rgid_m_tbl[] = { + [0] = {0xFCF81000U, 0x00000002U}, /* RGIDM_MODID[0]:PCI0 */ + [1] = {0xFCF81020U, 0x00000002U}, /* RGIDM_MODID[1]:PCI1 */ + [2] = {0xFCF81010U, 0x00000002U}, /* RGIDM_MODID[3]:AVB0 */ + [3] = {0xFCF81014U, 0x00000001U}, /* RGIDM_MODID[4]:AVB1 */ + [4] = {0xFCF81018U, 0x00000001U}, /* RGIDM_MODID[5]:AVB2 */ + [5] = {0xFDC2100CU, 0x00000000U}, /* RGIDM_MODID[6]:DCLS_ICUMX */ + [6] = {0xFDC21010U, 0x00000000U}, /* RGIDM_MODID[7]:ICUMX */ + [7] = {0xFDC21014U, 0x00000000U}, /* RGIDM_MODID[8]:SDMAC_ICUMX */ + [8] = {0xFD441018U, 0x00000001U}, /* RGIDM_MODID[9]:CR52SS0 */ + [9] = {0xFD44105CU, 0x00000001U}, /* RGIDM_MODID[10]:CR52SS1 */ + [10] = {0xFD441060U, 0x00000006U}, /* RGIDM_MODID[11]:CR52SS2 */ + [11] = {0xFD44101CU, 0x00000003U}, /* RGIDM_MODID[12]:CSD */ + [12] = {0xFD441024U, 0x00000002U}, /* RGIDM_MODID[13]:INTAP0 */ + [13] = {0xFC861018U, 0x00000002U}, /* RGIDM_MODID[14]:FBABUSTOP0 */ + [14] = {0xFCB51020U, 0x00000002U}, /* RGIDM_MODID[15]:SDHI0 */ + [15] = {0xFCB51010U, 0x00000001U}, /* RGIDM_MODID[16]:FRAY */ + [16] = {0xFC811000U, 0x00000002U}, /* RGIDM_MODID[17]:AXMM2AXSTM */ + [17] = {0xFC811004U, 0x00000003U}, /* RGIDM_MODID[18]:CSDE0 */ + [18] = {0xFC811008U, 0x00000003U}, /* RGIDM_MODID[19]:CSDE1 */ + [19] = {0xFD441020U, 0x00000003U}, /* RGIDM_MODID[20]:CSDE2 */ + [20] = {0xFC881004U, 0x00000002U}, /* RGIDM_MODID[21]:FBABUSIR0 */ + [21] = {0xFC881008U, 0x00000002U}, /* RGIDM_MODID[22]:FBABUSIR1 */ + [22] = {0xFC88100CU, 0x00000002U}, /* RGIDM_MODID[23]:FBABUSIR2 */ + [23] = {0xFC881010U, 0x00000002U}, /* RGIDM_MODID[24]:FBABUSIR3 */ + [24] = {0xFC011014U, 0x00000002U}, /* RGIDM_MODID[25]:RGX0 */ + [25] = {0xFC681004U, 0x00000002U}, /* RGIDM_MODID[26]:FBABUSVC */ + [26] = {0xFC681010U, 0x00000002U}, /* RGIDM_MODID[27]:IMR00 */ + [27] = {0xFC681014U, 0x00000002U}, /* RGIDM_MODID[28]:IMR01 */ + [28] = {0xFC681024U, 0x00000002U}, /* RGIDM_MODID[29]:IMR10 */ + [29] = {0xFC681028U, 0x00000002U}, /* RGIDM_MODID[30]:IMR11 */ + [30] = {0xFC681040U, 0x00000002U}, /* RGIDM_MODID[31]:IMS0 */ + [31] = {0xFC681044U, 0x00000002U}, /* RGIDM_MODID[32]:IMS1 */ + [32] = {0xFC681048U, 0x00000005U}, /* RGIDM_MODID[33]:IV1ES */ + [33] = {0xFEBE1000U, 0x00000002U}, /* RGIDM_MODID[34]:DSITLINK0 */ + [34] = {0xFEBE1008U, 0x00000002U}, /* RGIDM_MODID[36]:FBABUSVIO */ + [35] = {0xFEBE1014U, 0x00000002U}, /* RGIDM_MODID[37]:FCPVD0 */ + [36] = {0xFEBE101CU, 0x00000002U}, /* RGIDM_MODID[38]:FCPVX0 */ + [37] = {0xFEBF1020U, 0x00000002U}, /* RGIDM_MODID[39]:ISP00 */ + [38] = {0xFEBF1024U, 0x00000002U}, /* RGIDM_MODID[40]:ISP01 */ + [39] = {0xFEBF1000U, 0x00000002U}, /* RGIDM_MODID[41]:ISP02 */ + [40] = {0xFEBF1004U, 0x00000002U}, /* RGIDM_MODID[42]:ISP03 */ + [41] = {0xFEBF1008U, 0x00000002U}, /* RGIDM_MODID[43]:ISP04 */ + [42] = {0xFEBF1010U, 0x00000002U}, /* RGIDM_MODID[44]:VIN0 */ + [43] = {0xFEBF1014U, 0x00000002U}, /* RGIDM_MODID[45]:VIN1 */ + [44] = {0xFC311004U, 0x00000002U}, /* RGIDM_MODID[46]:FBABUSVIP0 */ + [45] = {0xFC311010U, 0x00000002U}, /* RGIDM_MODID[47]:SMPO */ + [46] = {0xFC311018U, 0x00000002U}, /* RGIDM_MODID[48]:SMPS */ + [47] = {0xFC31101CU, 0x00000002U}, /* RGIDM_MODID[49]:UMFL */ + [48] = {0xFC881018U, 0x00000002U}, /* RGIDM_MODID[50]:DSP00 */ + [49] = {0xFC881024U, 0x00000002U}, /* RGIDM_MODID[51]:DSP01 */ + [50] = {0xFC881038U, 0x00000002U}, /* RGIDM_MODID[52]:DSP10 */ + [51] = {0xFC881044U, 0x00000002U}, /* RGIDM_MODID[53]:DSP11 */ + [52] = {0xFC881048U, 0x00000002U}, /* RGIDM_MODID[54]:DSP20 */ + [53] = {0xFC88104CU, 0x00000002U}, /* RGIDM_MODID[55]:DSP21 */ + [54] = {0xFC881050U, 0x00000002U}, /* RGIDM_MODID[56]:DSP30 */ + [55] = {0xFC881054U, 0x00000002U}, /* RGIDM_MODID[57]:DSP31 */ + [56] = {0xFC881058U, 0x00000002U}, /* RGIDM_MODID[58]:IMP0R100 */ + [57] = {0xFC88105CU, 0x00000002U}, /* RGIDM_MODID[59]:IMP0R101 */ + [58] = {0xFC881060U, 0x00000002U}, /* RGIDM_MODID[60]:IMP0R102 */ + [59] = {0xFC881064U, 0x00000002U}, /* RGIDM_MODID[61]:IMP0R103 */ + [60] = {0xFC881068U, 0x00000002U}, /* RGIDM_MODID[62]:IMP0R104 */ + [61] = {0xFC88106CU, 0x00000002U}, /* RGIDM_MODID[63]:IMP0R105 */ + [62] = {0xFC881070U, 0x00000002U}, /* RGIDM_MODID[64]:IMP0R106 */ + [63] = {0xFC881074U, 0x00000002U}, /* RGIDM_MODID[65]:IMP0R107 */ + [64] = {0xFC881078U, 0x00000002U}, /* RGIDM_MODID[66]:IMP0R108 */ + [65] = {0xFC88107CU, 0x00000002U}, /* RGIDM_MODID[67]:IMP0R109 */ + [66] = {0xFC881080U, 0x00000002U}, /* RGIDM_MODID[68]:IMP0R200 */ + [67] = {0xFC881084U, 0x00000002U}, /* RGIDM_MODID[69]:IMP0R201 */ + [68] = {0xFC881088U, 0x00000002U}, /* RGIDM_MODID[70]:IMP0R202 */ + [69] = {0xFC88108CU, 0x00000002U}, /* RGIDM_MODID[71]:IMP0W100 */ + [70] = {0xFC881090U, 0x00000002U}, /* RGIDM_MODID[72]:IMP0W101 */ + [71] = {0xFC881094U, 0x00000002U}, /* RGIDM_MODID[73]:IMP0W102 */ + [72] = {0xFC881098U, 0x00000002U}, /* RGIDM_MODID[74]:IMP0W103 */ + [73] = {0xFC88109CU, 0x00000002U}, /* RGIDM_MODID[75]:IMP0W104 */ + [74] = {0xFC8810A0U, 0x00000002U}, /* RGIDM_MODID[76]:IMP0W105 */ + [75] = {0xFC8810A4U, 0x00000002U}, /* RGIDM_MODID[77]:IMP0W106 */ + [76] = {0xFC8810A8U, 0x00000002U}, /* RGIDM_MODID[78]:IMP0W107 */ + [77] = {0xFC8810ACU, 0x00000002U}, /* RGIDM_MODID[79]:IMP0W108 */ + [78] = {0xFC8810B0U, 0x00000002U}, /* RGIDM_MODID[80]:IMP0W109 */ + [79] = {0xFC8810B4U, 0x00000002U}, /* RGIDM_MODID[81]:IMP0W200 */ + [80] = {0xFC8810B8U, 0x00000002U}, /* RGIDM_MODID[82]:IMP0W201 */ + [81] = {0xFC8810BCU, 0x00000002U}, /* RGIDM_MODID[83]:IMP0W202 */ + [82] = {0xFDDBF500U, 0x0000000EU}, /* RGIDM_MODID[84]:VRAM_R */ + [83] = {0xFDDBF504U, 0x0000000EU}, /* RGIDM_MODID[85]:VRAM_W */ + [84] = {0xFC311008U, 0x00000002U}, /* RGIDM_MODID[86]:PAP */ +}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_r_tbl" +const REGION_ID_SETTING_TABLE g_rgid_r_tbl[] = { + [0] = {0xFD482000U, 0x0000000FU}, /* RGIDR_MODID[0]:ARMGC0*/ + [1] = {0xFD482004U, 0x0000000FU}, /* RGIDR_MODID[1]:ARMGC1*/ + [2] = {0xFD482008U, 0x00000000U}, /* RGIDR_MODID[2]:ARMGC2*/ + [3] = {0xFD48200CU, 0x0000000FU}, /* RGIDR_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDR_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDR_MODID[5]:ARRT02*/ + [4] = {0xFD482018U, 0x0000000FU}, /* RGIDR_MODID[6]:ARRT03*/ + [5] = {0xFD48201CU, 0x0000000FU}, /* RGIDR_MODID[7]:ARRT04*/ + [6] = {0xFD482020U, 0x0000000FU}, /* RGIDR_MODID[8]:ARRT05*/ + [7] = {0xFD482024U, 0x0000000FU}, /* RGIDR_MODID[9]:ARRT06*/ + [8] = {0xFD482028U, 0x0000000FU}, /* RGIDR_MODID[10]:ARRT07*/ + [9] = {0xFD48202CU, 0x00000000U}, /* RGIDR_MODID[11]:ARRT08*/ + [10] = {0xFD482030U, 0x00000001U}, /* RGIDR_MODID[12]:LIFEC0*/ + [11] = {0xFD482034U, 0x0000000EU}, /* RGIDR_MODID[13]:SWDT*/ + [12] = {0xFD482038U, 0x0000006EU}, /* RGIDR_MODID[14]:TMU0*/ + [13] = {0xFD48203CU, 0x0000000EU}, /* RGIDR_MODID[15]:WDT*/ + [14] = {0xFD482040U, 0x0000000EU}, /* RGIDR_MODID[16]:WWDT0*/ + [15] = {0xFD482044U, 0x0000000EU}, /* RGIDR_MODID[17]:WWDT1*/ + [16] = {0xFD482048U, 0x0000000EU}, /* RGIDR_MODID[18]:WWDT2*/ + [17] = {0xFD48204CU, 0x0000000EU}, /* RGIDR_MODID[19]:WWDT3*/ + [18] = {0xFD482050U, 0x0000000EU}, /* RGIDR_MODID[20]:WWDT4*/ + [19] = {0xFD482054U, 0x0000000EU}, /* RGIDR_MODID[21]:WWDT5*/ + [20] = {0xFD482058U, 0x0000000EU}, /* RGIDR_MODID[22]:WWDT6*/ + [21] = {0xFD482068U, 0x0000000FU}, /* RGIDR_MODID[23]:ECMRT3*/ + [22] = {0xFDA02004U, 0x0000000FU}, /* RGIDR_MODID[24]:APMU0*/ + [23] = {0xFDA02008U, 0x00000002U}, /* RGIDR_MODID[25]:APMU1*/ + [24] = {0xFDA0200CU, 0x00000000U}, /* RGIDR_MODID[26]:APMU10*/ + [25] = {0xFDA02010U, 0x00000000U}, /* RGIDR_MODID[27]:APMU11*/ + [26] = {0xFDA02014U, 0x00000000U}, /* RGIDR_MODID[28]:APMU12*/ + [27] = {0xFDA02018U, 0x00000000U}, /* RGIDR_MODID[29]:APMU13*/ + [28] = {0xFDA0201CU, 0x00000000U}, /* RGIDR_MODID[30]:APMU14*/ + [29] = {0xFDA02020U, 0x00000000U}, /* RGIDR_MODID[31]:APMU15*/ + [30] = {0xFDA02024U, 0x00000004U}, /* RGIDR_MODID[32]:APMU2*/ + [31] = {0xFDA02028U, 0x00000004U}, /* RGIDR_MODID[33]:APMU3*/ + [32] = {0xFDA0202CU, 0x00000000U}, /* RGIDR_MODID[34]:APMU4*/ + [33] = {0xFDA02030U, 0x00000000U}, /* RGIDR_MODID[35]:APMU5*/ + [34] = {0xFDA02034U, 0x00000000U}, /* RGIDR_MODID[36]:APMU6*/ + [35] = {0xFDA02038U, 0x00000000U}, /* RGIDR_MODID[37]:APMU7*/ + [36] = {0xFDA0203CU, 0x00000000U}, /* RGIDR_MODID[38]:APMU8*/ + [37] = {0xFDA02040U, 0x00000000U}, /* RGIDR_MODID[39]:APMU9*/ + [38] = {0xFDA02044U, 0x0000000FU}, /* RGIDR_MODID[40]:ARS00*/ + /* After setting */ /* RGIDR_MODID[41]:ARS01*/ + /* After setting */ /* RGIDR_MODID[42]:ARS02*/ + [39] = {0xFDA02050U, 0x0000000FU}, /* RGIDR_MODID[43]:ARS03*/ + [40] = {0xFDA02054U, 0x0000000FU}, /* RGIDR_MODID[44]:ARS04*/ + [41] = {0xFDA02058U, 0x0000000FU}, /* RGIDR_MODID[45]:ARS05*/ + [42] = {0xFDA0205CU, 0x0000000FU}, /* RGIDR_MODID[46]:ARS06*/ + [43] = {0xFDA02060U, 0x0000000FU}, /* RGIDR_MODID[47]:ARS07*/ + [44] = {0xFDA02064U, 0x00000000U}, /* RGIDR_MODID[48]:ARS08*/ + [45] = {0xFDA02068U, 0x0000000EU}, /* RGIDR_MODID[49]:CMT0*/ + [46] = {0xFDA0206CU, 0x0000000EU}, /* RGIDR_MODID[50]:CMT1*/ + [47] = {0xFDA02070U, 0x0000000EU}, /* RGIDR_MODID[51]:CMT2*/ + [48] = {0xFDA02074U, 0x0000000EU}, /* RGIDR_MODID[52]:CMT3*/ + [49] = {0xFDA02078U, 0x0000000AU}, /* RGIDR_MODID[53]:CKM*/ + [50] = {0xFDA0207CU, 0x0000000EU}, /* RGIDR_MODID[54]:DBE*/ + [51] = {0xFDA02080U, 0x0000000EU}, /* RGIDR_MODID[55]:IRQC*/ + [52] = {0xFDA02084U, 0x0000000FU}, /* RGIDR_MODID[56]:ECMPS0*/ + [53] = {0xFDA02088U, 0x0000000BU}, /* RGIDR_MODID[57]:OTP0*/ + [54] = {0xFDA0208CU, 0x0000000FU}, /* RGIDR_MODID[58]:OTP1*/ + [55] = {0xFDA0209CU, 0x0000000EU}, /* RGIDR_MODID[59]:SCMT*/ + [56] = {0xFDA020A8U, 0x0000004EU}, /* RGIDR_MODID[60]:TSC1*/ + [57] = {0xFDA020ACU, 0x0000004EU}, /* RGIDR_MODID[61]:TSC2*/ + [58] = {0xFDA020B8U, 0x00000006U}, /* RGIDR_MODID[62]:UCMT*/ + [59] = {0xFDA02100U, 0x0000006FU}, /* RGIDR_MODID[63]:CPG0*/ + [60] = {0xFDA02104U, 0x0000000AU}, /* RGIDR_MODID[64]:CPG1*/ + [61] = {0xFDA02108U, 0x0000004EU}, /* RGIDR_MODID[65]:CPG2*/ + [62] = {0xFDA0210CU, 0x00000028U}, /* RGIDR_MODID[66]:CPG3*/ + [63] = {0xFDA02110U, 0x0000006FU}, /* RGIDR_MODID[67]:PFC00*/ + [64] = {0xFDA02114U, 0x0000000AU}, /* RGIDR_MODID[68]:PFC01*/ + [65] = {0xFDA02118U, 0x0000004EU}, /* RGIDR_MODID[69]:PFC02*/ + [66] = {0xFDA0211CU, 0x00000028U}, /* RGIDR_MODID[70]:PFC03*/ + [67] = {0xFDA02120U, 0x0000006FU}, /* RGIDR_MODID[71]:PFC10*/ + [68] = {0xFDA02124U, 0x0000000AU}, /* RGIDR_MODID[72]:PFC11*/ + [69] = {0xFDA02128U, 0x0000004EU}, /* RGIDR_MODID[73]:PFC12*/ + [70] = {0xFDA0212CU, 0x00000028U}, /* RGIDR_MODID[74]:PFC13*/ + [71] = {0xFDA02130U, 0x0000006FU}, /* RGIDR_MODID[75]:PFC20*/ + [72] = {0xFDA02134U, 0x0000000AU}, /* RGIDR_MODID[76]:PFC21*/ + [73] = {0xFDA02138U, 0x0000004EU}, /* RGIDR_MODID[77]:PFC22*/ + [74] = {0xFDA0213CU, 0x00000028U}, /* RGIDR_MODID[78]:PFC23*/ + [75] = {0xFDA02150U, 0x0000006FU}, /* RGIDR_MODID[79]:PFCS0*/ + [76] = {0xFDA02154U, 0x0000000AU}, /* RGIDR_MODID[80]:PFCS1*/ + [77] = {0xFDA02158U, 0x0000004EU}, /* RGIDR_MODID[81]:PFCS2*/ + [78] = {0xFDA0215CU, 0x00000028U}, /* RGIDR_MODID[82]:PFCS3*/ + [79] = {0xFDA02160U, 0x0000006FU}, /* RGIDR_MODID[83]:RESET0*/ + [80] = {0xFDA02164U, 0x0000000AU}, /* RGIDR_MODID[84]:RESET1*/ + [81] = {0xFDA02168U, 0x0000004EU}, /* RGIDR_MODID[85]:RESET2*/ + [82] = {0xFDA0216CU, 0x00000028U}, /* RGIDR_MODID[86]:RESET3*/ + [83] = {0xFDA02170U, 0x0000006FU}, /* RGIDR_MODID[87]:SYS0*/ + [84] = {0xFDA02174U, 0x0000000AU}, /* RGIDR_MODID[88]:SYS1*/ + [85] = {0xFDA02178U, 0x0000004EU}, /* RGIDR_MODID[89]:SYS2*/ + [86] = {0xFDA0217CU, 0x00000028U}, /* RGIDR_MODID[90]:SYS3*/ + [87] = {0xFCB62000U, 0x0000000EU}, /* RGIDR_MODID[91]:DMAMSI0*/ + [88] = {0xFCB62004U, 0x0000000EU}, /* RGIDR_MODID[92]:DMAMSI1*/ + [89] = {0xFCB62008U, 0x0000000EU}, /* RGIDR_MODID[93]:DMAMSI2*/ + [90] = {0xFCB6200CU, 0x0000000EU}, /* RGIDR_MODID[94]:DMAMSI3*/ + [91] = {0xFCB62010U, 0x0000000EU}, /* RGIDR_MODID[95]:DMAMSI4*/ + [92] = {0xFCB62014U, 0x0000000EU}, /* RGIDR_MODID[96]:DMAMSI5*/ + [93] = {0xFCB62018U, 0x0000000FU}, /* RGIDR_MODID[97]:ECMSP3*/ + [94] = {0xFCB62024U, 0x0000000FU}, /* RGIDR_MODID[98]:ARSP30*/ + /* After setting */ /* RGIDR_MODID[99]:ARSP31*/ + /* After setting */ /* RGIDR_MODID[100]:ARSP32*/ + [95] = {0xFCB62030U, 0x0000000FU}, /* RGIDR_MODID[101]:ARSP33*/ + [96] = {0xFCB62034U, 0x0000000FU}, /* RGIDR_MODID[102]:ARSP34*/ + [97] = {0xFCB62038U, 0x0000000FU}, /* RGIDR_MODID[103]:ARSP35*/ + [98] = {0xFCB6203CU, 0x0000000FU}, /* RGIDR_MODID[104]:ARSP36*/ + [99] = {0xFCB62040U, 0x0000000FU}, /* RGIDR_MODID[105]:ARSP37*/ + [100] = {0xFCB62044U, 0x00000000U}, /* RGIDR_MODID[106]:ARSP38*/ + [101] = {0xFCB62048U, 0x0000000EU}, /* RGIDR_MODID[107]:MSI0*/ + [102] = {0xFCB6204CU, 0x0000000EU}, /* RGIDR_MODID[108]:MSI1*/ + [103] = {0xFCB62050U, 0x0000000EU}, /* RGIDR_MODID[109]:MSI2*/ + [104] = {0xFCB62054U, 0x0000000EU}, /* RGIDR_MODID[110]:MSI3*/ + [105] = {0xFCB62058U, 0x0000000EU}, /* RGIDR_MODID[111]:MSI4*/ + [106] = {0xFCB6205CU, 0x0000000EU}, /* RGIDR_MODID[112]:MSI5*/ + [107] = {0xFCB92000U, 0x0000000FU}, /* RGIDR_MODID[113]:ARSP40*/ + /* After setting */ /* RGIDR_MODID[114]:ARSP41*/ + /* After setting */ /* RGIDR_MODID[115]:ARSP42*/ + [108] = {0xFCB9200CU, 0x0000000FU}, /* RGIDR_MODID[116]:ARSP43*/ + [109] = {0xFCB92010U, 0x0000000FU}, /* RGIDR_MODID[117]:ARSP44*/ + [110] = {0xFCB92014U, 0x0000000FU}, /* RGIDR_MODID[118]:ARSP45*/ + [111] = {0xFCB92018U, 0x0000000FU}, /* RGIDR_MODID[119]:ARSP46*/ + [112] = {0xFCB9201CU, 0x0000000FU}, /* RGIDR_MODID[120]:ARSP47*/ + [113] = {0xFCB92020U, 0x00000000U}, /* RGIDR_MODID[121]:ARSP48*/ + [114] = {0xFCB92024U, 0x0000004FU}, /* RGIDR_MODID[122]:DMAHSCIF0*/ + [115] = {0xFCB92028U, 0x0000004FU}, /* RGIDR_MODID[123]:DMAHSCIF1*/ + [116] = {0xFCB9202CU, 0x0000004FU}, /* RGIDR_MODID[124]:DMAHSCIF2*/ + [117] = {0xFCB92030U, 0x0000004FU}, /* RGIDR_MODID[125]:DMAHSCIF3*/ + [118] = {0xFCB92034U, 0x0000004FU}, /* RGIDR_MODID[126]:DMASCIF0*/ + [119] = {0xFCB92038U, 0x0000004FU}, /* RGIDR_MODID[127]:DMASCIF1*/ + [120] = {0xFCB9203CU, 0x0000004FU}, /* RGIDR_MODID[128]:DMASCIF3*/ + [121] = {0xFCB92040U, 0x0000004FU}, /* RGIDR_MODID[129]:DMASCIF4*/ + [122] = {0xFCB92044U, 0x0000000FU}, /* RGIDR_MODID[130]:ECMSP4*/ + [123] = {0xFCB92048U, 0x0000004FU}, /* RGIDR_MODID[131]:HSCIF0*/ + [124] = {0xFCB9204CU, 0x0000004FU}, /* RGIDR_MODID[132]:HSCIF1*/ + [125] = {0xFCB92050U, 0x0000004FU}, /* RGIDR_MODID[133]:HSCIF2*/ + [126] = {0xFCB92054U, 0x0000004FU}, /* RGIDR_MODID[134]:HSCIF3*/ + [127] = {0xFCB92058U, 0x0000004FU}, /* RGIDR_MODID[135]:SCIF0*/ + [128] = {0xFCB9205CU, 0x0000004FU}, /* RGIDR_MODID[136]:SCIF1*/ + [129] = {0xFCB92060U, 0x0000004FU}, /* RGIDR_MODID[137]:SCIF3*/ + [130] = {0xFCB92064U, 0x0000004FU}, /* RGIDR_MODID[138]:SCIF4*/ + [131] = {0xFCB92068U, 0x0000006EU}, /* RGIDR_MODID[139]:TMU1*/ + [132] = {0xFCB9206CU, 0x0000006EU}, /* RGIDR_MODID[140]:TMU2*/ + [133] = {0xFCB92070U, 0x0000006EU}, /* RGIDR_MODID[141]:TMU3*/ + [134] = {0xFCB92074U, 0x0000006EU}, /* RGIDR_MODID[142]:TMU4*/ + [135] = {0xFCB92078U, 0x0000004AU}, /* RGIDR_MODID[143]:CANFD*/ + [136] = {0xFCB9207CU, 0x0000004AU}, /* RGIDR_MODID[144]:DMACANFD*/ + [137] = {0xFCB92080U, 0x00000002U}, /* RGIDR_MODID[145]:DMATPU0*/ + [138] = {0xFCB92084U, 0x00000002U}, /* RGIDR_MODID[146]:PWM0*/ + [139] = {0xFCB92088U, 0x00000002U}, /* RGIDR_MODID[147]:PWM1*/ + [140] = {0xFCB9208CU, 0x00000002U}, /* RGIDR_MODID[148]:PWM2*/ + [141] = {0xFCB92090U, 0x00000002U}, /* RGIDR_MODID[149]:PWM3*/ + [142] = {0xFCB92094U, 0x00000002U}, /* RGIDR_MODID[150]:PWM4*/ + [143] = {0xFCB920ACU, 0x00000002U}, /* RGIDR_MODID[151]:TPU0*/ + [144] = {0xFEBD2000U, 0x0000000FU}, /* RGIDR_MODID[152]:ARVI40*/ + /* After setting */ /* RGIDR_MODID[153]:ARVI41*/ + /* After setting */ /* RGIDR_MODID[154]:ARVI42*/ + [145] = {0xFEBD200CU, 0x0000000FU}, /* RGIDR_MODID[155]:ARVI43*/ + [146] = {0xFEBD2010U, 0x0000000FU}, /* RGIDR_MODID[156]:ARVI44*/ + [147] = {0xFEBD2014U, 0x0000000FU}, /* RGIDR_MODID[157]:ARVI45*/ + [148] = {0xFEBD2018U, 0x0000000FU}, /* RGIDR_MODID[158]:ARVI46*/ + [149] = {0xFEBD201CU, 0x0000000FU}, /* RGIDR_MODID[159]:ARVI47*/ + [150] = {0xFEBD2020U, 0x00000000U}, /* RGIDR_MODID[160]:ARVI48*/ + [151] = {0xFEBD2024U, 0x0000000FU}, /* RGIDR_MODID[161]:DIS0*/ + [152] = {0xFEBD2030U, 0x0000000FU}, /* RGIDR_MODID[162]:ECMVIO2*/ + [153] = {0xFEBD2034U, 0x0000000FU}, /* RGIDR_MODID[163]:FCPVD0*/ + [154] = {0xFEBD203CU, 0x0000004EU}, /* RGIDR_MODID[164]:VSPD0*/ + [155] = {0xFCF82000U, 0x0000000AU}, /* RGIDR_MODID[165]:CKMHSC*/ + [156] = {0xFCF82004U, 0x0000000CU}, /* RGIDR_MODID[166]:AXIPCI001*/ + [157] = {0xFCF82008U, 0x0000000CU}, /* RGIDR_MODID[167]:AXIPCI002*/ + [158] = {0xFCF8200CU, 0x0000000CU}, /* RGIDR_MODID[168]:AXIPCI003*/ + [159] = {0xFCF82014U, 0x0000000CU}, /* RGIDR_MODID[169]:AXIPCI005*/ + [160] = {0xFCF82018U, 0x0000000CU}, /* RGIDR_MODID[170]:AXIPCI006*/ + [161] = {0xFCF8201CU, 0x0000000CU}, /* RGIDR_MODID[171]:AXIPCI007*/ + [162] = {0xFCF82020U, 0x0000000CU}, /* RGIDR_MODID[172]:AXIPCI008*/ + [163] = {0xFCF82024U, 0x0000000CU}, /* RGIDR_MODID[173]:AXIPCI009*/ + [164] = {0xFCF82028U, 0x0000000CU}, /* RGIDR_MODID[174]:AXIPCI010*/ + [165] = {0xFCF8202CU, 0x0000000CU}, /* RGIDR_MODID[175]:AXIPCI011*/ + [166] = {0xFCF82030U, 0x0000000CU}, /* RGIDR_MODID[176]:AXIPCI012*/ + [167] = {0xFCF82034U, 0x0000000CU}, /* RGIDR_MODID[177]:AXIPCI013*/ + [168] = {0xFCF82038U, 0x0000000CU}, /* RGIDR_MODID[178]:AXIPCI014*/ + [169] = {0xFCF8203CU, 0x0000000CU}, /* RGIDR_MODID[179]:AXIPCI015*/ + [170] = {0xFCF82084U, 0x0000000EU}, /* RGIDR_MODID[180]:GPTP*/ + [171] = {0xFCF82088U, 0x0000004EU}, /* RGIDR_MODID[181]:IPMMUHC00*/ + [172] = {0xFCF820F4U, 0x0000000CU}, /* RGIDR_MODID[182]:AXIPCI000*/ + [173] = {0xFCF820F8U, 0x0000000CU}, /* RGIDR_MODID[183]:AXIPCI004*/ + [174] = {0xFCF820FCU, 0x0000004EU}, /* RGIDR_MODID[184]:IPMMUHC01*/ + [175] = {0xFCF82100U, 0x0000004EU}, /* RGIDR_MODID[185]:AVB0*/ + [176] = {0xFCF82104U, 0x0000004EU}, /* RGIDR_MODID[186]:AVB1*/ + [177] = {0xFCF82108U, 0x0000004EU}, /* RGIDR_MODID[187]:AVB2*/ + [178] = {0xFCF8210CU, 0x0000004EU}, /* RGIDR_MODID[188]:IPMMUHC10*/ + [179] = {0xFCF82110U, 0x0000004EU}, /* RGIDR_MODID[189]:IPMMUHC11*/ + [180] = {0xFCF82114U, 0x0000004EU}, /* RGIDR_MODID[190]:IPMMUHC12*/ + [181] = {0xFCF82118U, 0x0000004EU}, /* RGIDR_MODID[191]:IPMMUHC13*/ + [182] = {0xFCF8211CU, 0x0000000CU}, /* RGIDR_MODID[192]:PPHY0*/ + [183] = {0xFCF82124U, 0x0000004EU}, /* RGIDR_MODID[193]:IPMMUHC14*/ + [184] = {0xFCF82128U, 0x0000004EU}, /* RGIDR_MODID[194]:IPMMUHC15*/ + [185] = {0xFCF8212CU, 0x0000000EU}, /* RGIDR_MODID[195]:FBAHSC*/ + [186] = {0xFCF82130U, 0x0000004EU}, /* RGIDR_MODID[196]:IPMMUHC02*/ + [187] = {0xFCF82138U, 0x0000000FU}, /* RGIDR_MODID[197]:ECMHSC*/ + [188] = {0xFCF8213CU, 0x0000000FU}, /* RGIDR_MODID[198]:ARHC0*/ + /* After setting */ /* RGIDR_MODID[199]:ARHC1*/ + /* After setting */ /* RGIDR_MODID[200]:ARHC2*/ + [189] = {0xFCF82148U, 0x0000000FU}, /* RGIDR_MODID[201]:ARHC3*/ + [190] = {0xFCF8214CU, 0x0000000FU}, /* RGIDR_MODID[202]:ARHC4*/ + [191] = {0xFCF82150U, 0x0000000FU}, /* RGIDR_MODID[203]:ARHC5*/ + [192] = {0xFCF82154U, 0x0000000FU}, /* RGIDR_MODID[204]:ARHC6*/ + [193] = {0xFCF82158U, 0x0000000FU}, /* RGIDR_MODID[205]:ARHC7*/ + [194] = {0xFCF8215CU, 0x00000000U}, /* RGIDR_MODID[206]:ARHC8*/ + [195] = {0xFCF82160U, 0x0000004EU}, /* RGIDR_MODID[207]:IPMMUHC03*/ + [196] = {0xFCF82164U, 0x0000004EU}, /* RGIDR_MODID[208]:IPMMUHC04*/ + [197] = {0xFCF82168U, 0x0000004EU}, /* RGIDR_MODID[209]:IPMMUHC05*/ + [198] = {0xFCF8216CU, 0x0000004EU}, /* RGIDR_MODID[210]:IPMMUHC06*/ + [199] = {0xFCF82170U, 0x0000004EU}, /* RGIDR_MODID[211]:IPMMUHC07*/ + [200] = {0xFCF82174U, 0x0000004EU}, /* RGIDR_MODID[212]:IPMMUHC08*/ + [201] = {0xFCF82178U, 0x0000004EU}, /* RGIDR_MODID[213]:IPMMUHC09*/ + [202] = {0xFC882000U, 0x0000000FU}, /* RGIDR_MODID[214]:ARIMP00*/ + /* After setting */ /* RGIDR_MODID[215]:ARIMP01*/ + /* After setting */ /* RGIDR_MODID[216]:ARIMP02*/ + [203] = {0xFC88200CU, 0x0000000FU}, /* RGIDR_MODID[217]:ARIMP03*/ + [204] = {0xFC882010U, 0x0000000FU}, /* RGIDR_MODID[218]:ARIMP04*/ + [205] = {0xFC882014U, 0x0000004EU}, /* RGIDR_MODID[219]:AXIFBABUSIR0*/ + [206] = {0xFC882018U, 0x0000004EU}, /* RGIDR_MODID[220]:AXIFBABUSIR1*/ + [207] = {0xFC88201CU, 0x0000004EU}, /* RGIDR_MODID[221]:AXIFBABUSIR2*/ + [208] = {0xFC882020U, 0x0000004EU}, /* RGIDR_MODID[222]:AXIFBABUSIR3*/ + [209] = {0xFC882028U, 0x0000004EU}, /* RGIDR_MODID[223]:AXIIMP0*/ + [210] = {0xFC882034U, 0x0000000FU}, /* RGIDR_MODID[224]:ARIMP05*/ + [211] = {0xFC882038U, 0x0000000FU}, /* RGIDR_MODID[225]:ARIMP06*/ + [212] = {0xFC88203CU, 0x0000000FU}, /* RGIDR_MODID[226]:ARIMP07*/ + [213] = {0xFC882040U, 0x00000000U}, /* RGIDR_MODID[227]:ARIMP08*/ + [214] = {0xFC882048U, 0x0000000FU}, /* RGIDR_MODID[228]:ECMIR*/ + [215] = {0xFC88204CU, 0x0000000FU}, /* RGIDR_MODID[229]:DSPPS*/ + [216] = {0xFC882050U, 0x0000004EU}, /* RGIDR_MODID[230]:IPMMUIR1*/ + [217] = {0xFC882054U, 0x0000004EU}, /* RGIDR_MODID[231]:IPMMUIR0*/ + [218] = {0xFC882058U, 0x0000004EU}, /* RGIDR_MODID[232]:IPMMUIR10*/ + [219] = {0xFC88205CU, 0x0000004EU}, /* RGIDR_MODID[233]:IPMMUIR11*/ + [220] = {0xFC882060U, 0x0000004EU}, /* RGIDR_MODID[234]:IPMMUIR12*/ + [221] = {0xFC882064U, 0x0000004EU}, /* RGIDR_MODID[235]:IPMMUIR13*/ + [222] = {0xFC882068U, 0x0000004EU}, /* RGIDR_MODID[236]:IPMMUIR14*/ + [223] = {0xFC88206CU, 0x0000004EU}, /* RGIDR_MODID[237]:IPMMUIR15*/ + [224] = {0xFC882070U, 0x0000004EU}, /* RGIDR_MODID[238]:IPMMUIR2*/ + [225] = {0xFC882074U, 0x0000004EU}, /* RGIDR_MODID[239]:IPMMUIR3*/ + [226] = {0xFC882078U, 0x0000004EU}, /* RGIDR_MODID[240]:IPMMUIR4*/ + [227] = {0xFC88207CU, 0x0000004EU}, /* RGIDR_MODID[241]:IPMMUIR5*/ + [228] = {0xFC882080U, 0x0000004EU}, /* RGIDR_MODID[242]:IPMMUIR6*/ + [229] = {0xFC882084U, 0x0000004EU}, /* RGIDR_MODID[243]:IPMMUIR7*/ + [230] = {0xFC882088U, 0x0000004EU}, /* RGIDR_MODID[244]:IPMMUIR8*/ + [231] = {0xFC88208CU, 0x0000004EU}, /* RGIDR_MODID[245]:IPMMUIR9*/ + [232] = {0xFC012000U, 0x0000000FU}, /* RGIDR_MODID[246]:ARPV0*/ + /* After setting */ /* RGIDR_MODID[247]:ARPV1*/ + [233] = {0xFC012008U, 0x0000002CU}, /* RGIDR_MODID[248]:AXIRGXS*/ + /* After setting */ /* RGIDR_MODID[249]:ARPV2*/ + [234] = {0xFC012010U, 0x0000000FU}, /* RGIDR_MODID[250]:ARPV3*/ + [235] = {0xFC012014U, 0x0000000FU}, /* RGIDR_MODID[251]:ARPV4*/ + [236] = {0xFC012018U, 0x0000000FU}, /* RGIDR_MODID[252]:ARPV5*/ + [237] = {0xFC01201CU, 0x0000000FU}, /* RGIDR_MODID[253]:ARPV6*/ + [238] = {0xFC012020U, 0x0000000FU}, /* RGIDR_MODID[254]:ARPV7*/ + [239] = {0xFC012024U, 0x00000000U}, /* RGIDR_MODID[255]:ARPV8*/ + [240] = {0xFC01202CU, 0x0000000FU}, /* RGIDR_MODID[256]:ECM3DG*/ + [241] = {0xFC012030U, 0x0000000EU}, /* RGIDR_MODID[257]:FBAPVC*/ + [242] = {0xFC012034U, 0x0000000EU}, /* RGIDR_MODID[258]:FBAPVD0*/ + [243] = {0xFC012038U, 0x0000000EU}, /* RGIDR_MODID[259]:FBAPVD1*/ + [244] = {0xFC01203CU, 0x0000000EU}, /* RGIDR_MODID[260]:FBAPVD2*/ + [245] = {0xFC012040U, 0x0000000EU}, /* RGIDR_MODID[261]:FBAPVE*/ + [246] = {0xFC012044U, 0x0000004EU}, /* RGIDR_MODID[262]:IPMMUPV000*/ + [247] = {0xFC012048U, 0x0000004EU}, /* RGIDR_MODID[263]:IPMMUPV001*/ + [248] = {0xFC01204CU, 0x0000004EU}, /* RGIDR_MODID[264]:IPMMUPV010*/ + [249] = {0xFC012050U, 0x0000004EU}, /* RGIDR_MODID[265]:IPMMUPV011*/ + [250] = {0xFC012054U, 0x0000004EU}, /* RGIDR_MODID[266]:IPMMUPV012*/ + [251] = {0xFC012058U, 0x0000004EU}, /* RGIDR_MODID[267]:IPMMUPV013*/ + [252] = {0xFC01205CU, 0x0000004EU}, /* RGIDR_MODID[268]:IPMMUPV014*/ + [253] = {0xFC012060U, 0x0000004EU}, /* RGIDR_MODID[269]:IPMMUPV015*/ + [254] = {0xFC012064U, 0x0000004EU}, /* RGIDR_MODID[270]:IPMMUPV002*/ + [255] = {0xFC012068U, 0x0000004EU}, /* RGIDR_MODID[271]:IPMMUPV003*/ + [256] = {0xFC01206CU, 0x0000004EU}, /* RGIDR_MODID[272]:IPMMUPV004*/ + [257] = {0xFC012070U, 0x0000004EU}, /* RGIDR_MODID[273]:IPMMUPV005*/ + [258] = {0xFC012074U, 0x0000004EU}, /* RGIDR_MODID[274]:IPMMUPV006*/ + [259] = {0xFC012078U, 0x0000004EU}, /* RGIDR_MODID[275]:IPMMUPV007*/ + [260] = {0xFC01207CU, 0x0000004EU}, /* RGIDR_MODID[276]:IPMMUPV008*/ + [261] = {0xFC012080U, 0x0000004EU}, /* RGIDR_MODID[277]:IPMMUPV009*/ + [262] = {0xFDC22000U, 0x0000000FU}, /* RGIDR_MODID[278]:ARRC0*/ + /* After setting */ /* RGIDR_MODID[279]:ARRC1*/ + /* After setting */ /* RGIDR_MODID[280]:ARRC2*/ + [263] = {0xFDC2200CU, 0x0000000FU}, /* RGIDR_MODID[281]:ARRC3*/ + [264] = {0xFDC22010U, 0x0000000FU}, /* RGIDR_MODID[282]:ARRC4*/ + [265] = {0xFDC22014U, 0x0000000FU}, /* RGIDR_MODID[283]:ARRC5*/ + [266] = {0xFDC22018U, 0x0000000FU}, /* RGIDR_MODID[284]:ARRC6*/ + [267] = {0xFDC2201CU, 0x0000000FU}, /* RGIDR_MODID[285]:ARRC7*/ + [268] = {0xFDC22020U, 0x00000000U}, /* RGIDR_MODID[286]:ARRC8*/ + [269] = {0xFDC22028U, 0x0000004FU}, /* RGIDR_MODID[287]:ICUMX*/ + [270] = {0xFDC2202CU, 0x0000000FU}, /* RGIDR_MODID[288]:ECMRC*/ + [271] = {0xFD432000U, 0x0000004EU}, /* RGIDR_MODID[289]:DMAWCRC0*/ + [272] = {0xFD432004U, 0x0000004EU}, /* RGIDR_MODID[290]:DMAWCRC1*/ + [273] = {0xFD432008U, 0x0000004EU}, /* RGIDR_MODID[291]:DMAWCRC2*/ + [274] = {0xFD43200CU, 0x0000004EU}, /* RGIDR_MODID[292]:DMAWCRC3*/ + [275] = {0xFD442000U, 0x0000000FU}, /* RGIDR_MODID[293]:ARMREG00*/ + [276] = {0xFD442004U, 0x0000000DU}, /* RGIDR_MODID[294]:ARMREG01*/ + [277] = {0xFD442008U, 0x00000000U}, /* RGIDR_MODID[295]:ARMREG10*/ + [278] = {0xFD44200CU, 0x00000000U}, /* RGIDR_MODID[296]:ARMREG11*/ + [279] = {0xFD442010U, 0x0000000BU}, /* RGIDR_MODID[297]:ARMREG12*/ + [280] = {0xFD442014U, 0x0000000FU}, /* RGIDR_MODID[298]:ARMREG13*/ + [281] = {0xFD442018U, 0x0000000BU}, /* RGIDR_MODID[299]:ARMREG14*/ + [282] = {0xFD44201CU, 0x00000002U}, /* RGIDR_MODID[300]:AXICR52SS0*/ + [283] = {0xFD442020U, 0x0000000EU}, /* RGIDR_MODID[301]:AXICSD0*/ + [284] = {0xFD442024U, 0x0000000EU}, /* RGIDR_MODID[302]:AXIINTAP0*/ + [285] = {0xFD44202CU, 0x00000009U}, /* RGIDR_MODID[303]:AXISECROM*/ + [286] = {0xFD442030U, 0x0000000FU}, /* RGIDR_MODID[304]:AXISYSRAM0*/ + [287] = {0xFD442034U, 0x0000004FU}, /* RGIDR_MODID[305]:AXISYSRAM1*/ + [288] = {0xFD442038U, 0x00000000U}, /* RGIDR_MODID[306]:ARGREG15*/ + [289] = {0xFD44203CU, 0x00000000U}, /* RGIDR_MODID[307]:ARMREG2*/ + [290] = {0xFD442040U, 0x00000000U}, /* RGIDR_MODID[308]:ARMREG3*/ + [291] = {0xFD442044U, 0x00000000U}, /* RGIDR_MODID[309]:ARMREG4*/ + [292] = {0xFD442048U, 0x0000000FU}, /* RGIDR_MODID[310]:ARMREG5*/ + [293] = {0xFD44204CU, 0x0000000FU}, /* RGIDR_MODID[311]:ARMREG6*/ + [294] = {0xFD442050U, 0x00000000U}, /* RGIDR_MODID[312]:ARMREG7*/ + [295] = {0xFD442054U, 0x0000000DU}, /* RGIDR_MODID[313]:ARMREG8*/ + [296] = {0xFD442058U, 0x0000000DU}, /* RGIDR_MODID[314]:ARMREG9*/ + [297] = {0xFD44205CU, 0x0000000FU}, /* RGIDR_MODID[315]:ARRD0*/ + /* After setting */ /* RGIDR_MODID[316]:ARRD1*/ + /* After setting */ /* RGIDR_MODID[317]:ARRD2*/ + [298] = {0xFD442068U, 0x0000000FU}, /* RGIDR_MODID[318]:ARRD3*/ + [299] = {0xFD44206CU, 0x0000000FU}, /* RGIDR_MODID[319]:ARRD4*/ + [300] = {0xFD442070U, 0x0000000FU}, /* RGIDR_MODID[320]:ARRD5*/ + [301] = {0xFD442074U, 0x0000000FU}, /* RGIDR_MODID[321]:ARRD6*/ + [302] = {0xFD442078U, 0x0000000FU}, /* RGIDR_MODID[322]:ARRD7*/ + [303] = {0xFD44207CU, 0x00000000U}, /* RGIDR_MODID[323]:ARRD8*/ + [304] = {0xFD442080U, 0x0000000FU}, /* RGIDR_MODID[324]:ARRT0*/ + /* After setting */ /* RGIDR_MODID[325]:ARRT1*/ + /* After setting */ /* RGIDR_MODID[326]:ARRT2*/ + [305] = {0xFD44208CU, 0x0000000FU}, /* RGIDR_MODID[327]:ARRT3*/ + [306] = {0xFD442090U, 0x0000000FU}, /* RGIDR_MODID[328]:ARRT4*/ + [307] = {0xFD442094U, 0x0000000FU}, /* RGIDR_MODID[329]:ARRT5*/ + [308] = {0xFD442098U, 0x0000000FU}, /* RGIDR_MODID[330]:ARRT6*/ + [309] = {0xFD44209CU, 0x0000000FU}, /* RGIDR_MODID[331]:ARRT7*/ + [310] = {0xFD4420A0U, 0x00000000U}, /* RGIDR_MODID[332]:ARRT8*/ + [311] = {0xFD4420A4U, 0x0000000AU}, /* RGIDR_MODID[333]:CKMRT*/ + [312] = {0xFD4420A8U, 0x0000004EU}, /* RGIDR_MODID[334]:CRC0*/ + [313] = {0xFD4420ACU, 0x0000004EU}, /* RGIDR_MODID[335]:CRC1*/ + [314] = {0xFD4420B0U, 0x0000004EU}, /* RGIDR_MODID[336]:CRC2*/ + [315] = {0xFD4420B4U, 0x0000004EU}, /* RGIDR_MODID[337]:CRC3*/ + [316] = {0xFD4420B8U, 0x0000000EU}, /* RGIDR_MODID[338]:CSD*/ + [317] = {0xFD4420BCU, 0x0000000FU}, /* RGIDR_MODID[339]:ECM*/ + [318] = {0xFD4420C0U, 0x0000000FU}, /* RGIDR_MODID[340]:ECMRT*/ + [319] = {0xFD4420C4U, 0x0000000EU}, /* RGIDR_MODID[341]:FBACR52*/ + [320] = {0xFD4420C8U, 0x0000000EU}, /* RGIDR_MODID[342]:FBART*/ + [321] = {0xFD4420CCU, 0x0000000EU}, /* RGIDR_MODID[343]:INTTP*/ + [322] = {0xFD4420D0U, 0x0000004EU}, /* RGIDR_MODID[344]:IPMMURT000*/ + [323] = {0xFD4420D4U, 0x0000004EU}, /* RGIDR_MODID[345]:IPMMURT100*/ + [324] = {0xFD4420D8U, 0x0000004EU}, /* RGIDR_MODID[346]:KCRC4*/ + [325] = {0xFD4420DCU, 0x0000004EU}, /* RGIDR_MODID[347]:KCRC5*/ + [326] = {0xFD4420E0U, 0x0000004EU}, /* RGIDR_MODID[348]:KCRC6*/ + [327] = {0xFD4420E4U, 0x0000004EU}, /* RGIDR_MODID[349]:KCRC7*/ + [328] = {0xFD4420E8U, 0x0000004FU}, /* RGIDR_MODID[350]:MFI00*/ + [329] = {0xFD4420ECU, 0x0000004EU}, /* RGIDR_MODID[351]:MFI01*/ + [330] = {0xFD4420F0U, 0x0000004EU}, /* RGIDR_MODID[352]:MFI10*/ + [331] = {0xFD4420F4U, 0x0000004EU}, /* RGIDR_MODID[353]:MFI02*/ + [332] = {0xFD4420F8U, 0x0000004EU}, /* RGIDR_MODID[354]:MFI03*/ + [333] = {0xFD4420FCU, 0x0000004EU}, /* RGIDR_MODID[355]:MFI04*/ + [334] = {0xFD442100U, 0x00000000U}, /* RGIDR_MODID[356]:MFI05*/ + [335] = {0xFD442104U, 0x00000000U}, /* RGIDR_MODID[357]:MFI06*/ + [336] = {0xFD442108U, 0x00000000U}, /* RGIDR_MODID[358]:MFI07*/ + [337] = {0xFD44210CU, 0x00000000U}, /* RGIDR_MODID[359]:MFI08*/ + [338] = {0xFD442110U, 0x0000004EU}, /* RGIDR_MODID[360]:MFI09*/ + [339] = {0xFD442114U, 0x0000004FU}, /* RGIDR_MODID[361]:MFI15*/ + [340] = {0xFD442118U, 0x0000000AU}, /* RGIDR_MODID[362]:CKMCR52*/ + [341] = {0xFD44211CU, 0x0000004BU}, /* RGIDR_MODID[363]:RTDM0P*/ + [342] = {0xFD442120U, 0x0000000FU}, /* RGIDR_MODID[364]:ECMRD*/ + [343] = {0xFD442124U, 0x0000004BU}, /* RGIDR_MODID[365]:RTDM1P*/ + [344] = {0xFD442130U, 0x0000000BU}, /* RGIDR_MODID[366]:SYSRAM10*/ + [345] = {0xFD442138U, 0x00000003U}, /* RGIDR_MODID[367]:SYSRAM00*/ + [346] = {0xFD44213CU, 0x0000004EU}, /* RGIDR_MODID[368]:TSIPL0*/ + [347] = {0xFD442140U, 0x0000004EU}, /* RGIDR_MODID[369]:TSIPL1*/ + [348] = {0xFD442144U, 0x0000004EU}, /* RGIDR_MODID[370]:TSIPL2*/ + [349] = {0xFD442148U, 0x0000004EU}, /* RGIDR_MODID[371]:TSIPL3*/ + [350] = {0xFD44214CU, 0x0000004EU}, /* RGIDR_MODID[372]:TSIPL4*/ + [351] = {0xFD442150U, 0x0000004EU}, /* RGIDR_MODID[373]:TSIPL5*/ + [352] = {0xFD442154U, 0x0000004EU}, /* RGIDR_MODID[374]:TSIPL6*/ + [353] = {0xFD442158U, 0x0000004EU}, /* RGIDR_MODID[375]:TSIPL7*/ + [354] = {0xFD44215CU, 0x0000004EU}, /* RGIDR_MODID[376]:WCRC0*/ + [355] = {0xFD442160U, 0x0000004EU}, /* RGIDR_MODID[377]:WCRC1*/ + [356] = {0xFD442164U, 0x0000004EU}, /* RGIDR_MODID[378]:WCRC2*/ + [357] = {0xFD442168U, 0x0000004EU}, /* RGIDR_MODID[379]:WCRC3*/ + [358] = {0xFD442180U, 0x0000004EU}, /* RGIDR_MODID[380]:MFI11*/ + [359] = {0xFD442184U, 0x00000000U}, /* RGIDR_MODID[381]:MFI12*/ + [360] = {0xFD442188U, 0x00000000U}, /* RGIDR_MODID[382]:MFI13*/ + [361] = {0xFD44218CU, 0x00000000U}, /* RGIDR_MODID[383]:MFI14*/ + [362] = {0xFD442190U, 0x0000004EU}, /* RGIDR_MODID[384]:IPMMURT001*/ + [363] = {0xFD442194U, 0x0000004EU}, /* RGIDR_MODID[385]:IPMMURT010*/ + [364] = {0xFD442198U, 0x0000004EU}, /* RGIDR_MODID[386]:IPMMURT011*/ + [365] = {0xFD44219CU, 0x0000004EU}, /* RGIDR_MODID[387]:IPMMURT012*/ + [366] = {0xFD4421A0U, 0x0000004EU}, /* RGIDR_MODID[388]:IPMMURT013*/ + [367] = {0xFD4421A4U, 0x0000004EU}, /* RGIDR_MODID[389]:IPMMURT014*/ + [368] = {0xFD4421A8U, 0x0000004EU}, /* RGIDR_MODID[390]:IPMMURT015*/ + [369] = {0xFD4421ACU, 0x0000004EU}, /* RGIDR_MODID[391]:IPMMURT002*/ + [370] = {0xFD4421B0U, 0x0000004EU}, /* RGIDR_MODID[392]:IPMMURT003*/ + [371] = {0xFD4421B4U, 0x0000004EU}, /* RGIDR_MODID[393]:IPMMURT004*/ + [372] = {0xFD4421B8U, 0x0000004EU}, /* RGIDR_MODID[394]:IPMMURT005*/ + [373] = {0xFD4421BCU, 0x0000004EU}, /* RGIDR_MODID[395]:IPMMURT006*/ + [374] = {0xFD4421C0U, 0x0000004EU}, /* RGIDR_MODID[396]:IPMMURT007*/ + [375] = {0xFD4421C4U, 0x0000004EU}, /* RGIDR_MODID[397]:IPMMURT008*/ + [376] = {0xFD4421C8U, 0x0000004EU}, /* RGIDR_MODID[398]:IPMMURT009*/ + [377] = {0xFD4421CCU, 0x0000004EU}, /* RGIDR_MODID[399]:IPKMURT101*/ + [378] = {0xFD4421D0U, 0x0000004EU}, /* RGIDR_MODID[400]:IPMMURT110*/ + [379] = {0xFD4421D4U, 0x0000004EU}, /* RGIDR_MODID[401]:IPMMURT111*/ + [380] = {0xFD4421D8U, 0x0000004EU}, /* RGIDR_MODID[402]:IPMMURT112*/ + [381] = {0xFD4421DCU, 0x0000004EU}, /* RGIDR_MODID[403]:IPMMURT113*/ + [382] = {0xFD4421E0U, 0x0000004EU}, /* RGIDR_MODID[404]:IPMMURT114*/ + [383] = {0xFD4421E4U, 0x0000004EU}, /* RGIDR_MODID[405]:IPMMURT115*/ + [384] = {0xFD4421E8U, 0x0000004EU}, /* RGIDR_MODID[406]:IPMMURT102*/ + [385] = {0xFD4421ECU, 0x0000004EU}, /* RGIDR_MODID[407]:IPMMURT103*/ + [386] = {0xFD4421F0U, 0x0000004EU}, /* RGIDR_MODID[408]:IPMMURT104*/ + [387] = {0xFD4421F4U, 0x0000004EU}, /* RGIDR_MODID[409]:IPMMURT105*/ + [388] = {0xFD4421F8U, 0x0000004EU}, /* RGIDR_MODID[410]:IPMMURT106*/ + [389] = {0xFD4421FCU, 0x0000004EU}, /* RGIDR_MODID[411]:IPMMURT107*/ + [390] = {0xFD442200U, 0x0000004BU}, /* RGIDR_MODID[412]:RTDM000*/ + [391] = {0xFD442204U, 0x0000004BU}, /* RGIDR_MODID[413]:RTDM001*/ + [392] = {0xFD442208U, 0x0000004BU}, /* RGIDR_MODID[414]:RTDM010*/ + [393] = {0xFD44220CU, 0x0000004BU}, /* RGIDR_MODID[415]:RTDM011*/ + [394] = {0xFD442210U, 0x0000004BU}, /* RGIDR_MODID[416]:RTDM012*/ + [395] = {0xFD442214U, 0x0000004BU}, /* RGIDR_MODID[417]:RTDM013*/ + [396] = {0xFD442218U, 0x0000004BU}, /* RGIDR_MODID[418]:RTDM014*/ + [397] = {0xFD44221CU, 0x0000004BU}, /* RGIDR_MODID[419]:RTDM015*/ + [398] = {0xFD442220U, 0x0000004BU}, /* RGIDR_MODID[420]:RTDM002*/ + [399] = {0xFD442224U, 0x0000004BU}, /* RGIDR_MODID[421]:RTDM003*/ + [400] = {0xFD442228U, 0x0000004BU}, /* RGIDR_MODID[422]:RTDM004*/ + [401] = {0xFD44222CU, 0x0000004BU}, /* RGIDR_MODID[423]:RTDM005*/ + [402] = {0xFD442230U, 0x0000004BU}, /* RGIDR_MODID[424]:RTDM006*/ + [403] = {0xFD442234U, 0x0000004BU}, /* RGIDR_MODID[425]:RTDM007*/ + [404] = {0xFD442238U, 0x0000004BU}, /* RGIDR_MODID[426]:RTDM008*/ + [405] = {0xFD44223CU, 0x0000004BU}, /* RGIDR_MODID[427]:RTDM009*/ + [406] = {0xFD442240U, 0x0000004BU}, /* RGIDR_MODID[428]:RTDM100*/ + [407] = {0xFD442244U, 0x0000004BU}, /* RGIDR_MODID[429]:RTDM101*/ + [408] = {0xFD442248U, 0x0000004BU}, /* RGIDR_MODID[430]:RTDM110*/ + [409] = {0xFD44224CU, 0x0000004BU}, /* RGIDR_MODID[431]:RTDM111*/ + [410] = {0xFD442250U, 0x0000004BU}, /* RGIDR_MODID[432]:RTDM112*/ + [411] = {0xFD442254U, 0x0000004BU}, /* RGIDR_MODID[433]:RTDM113*/ + [412] = {0xFD442258U, 0x0000004BU}, /* RGIDR_MODID[434]:RTDM114*/ + [413] = {0xFD44225CU, 0x0000004BU}, /* RGIDR_MODID[435]:RTDM115*/ + [414] = {0xFD442260U, 0x0000004BU}, /* RGIDR_MODID[436]:RTDM102*/ + [415] = {0xFD442264U, 0x0000004BU}, /* RGIDR_MODID[437]:RTDM103*/ + [416] = {0xFD442268U, 0x0000004BU}, /* RGIDR_MODID[438]:RTDM104*/ + [417] = {0xFD44226CU, 0x0000004BU}, /* RGIDR_MODID[439]:RTDM105*/ + [418] = {0xFD442270U, 0x0000004BU}, /* RGIDR_MODID[440]:RTDM106*/ + [419] = {0xFD442274U, 0x0000004BU}, /* RGIDR_MODID[441]:RTDM107*/ + [420] = {0xFD442278U, 0x0000004BU}, /* RGIDR_MODID[442]:RTDM108*/ + [421] = {0xFD44227CU, 0x0000004BU}, /* RGIDR_MODID[443]:RTDM109*/ + [422] = {0xFD442300U, 0x0000004EU}, /* RGIDR_MODID[444]:IPMMURT108*/ + [423] = {0xFD442304U, 0x0000004EU}, /* RGIDR_MODID[445]:IPMMURT109*/ + [424] = {0xFD442308U, 0x00000001U}, /* RGIDR_MODID[446]:SYSRAM01*/ + [425] = {0xFD44230CU, 0x0000000BU}, /* RGIDR_MODID[447]:SYSRAM02*/ + [426] = {0xFD442310U, 0x00000001U}, /* RGIDR_MODID[448]:SYSRAM03*/ + [427] = {0xFD442314U, 0x00000001U}, /* RGIDR_MODID[449]:SYSRAM04*/ + [428] = {0xFD442318U, 0x00000001U}, /* RGIDR_MODID[450]:SYSRAM05*/ + [429] = {0xFD44231CU, 0x00000001U}, /* RGIDR_MODID[451]:SYSRAM06*/ + [430] = {0xFD442320U, 0x00000000U}, /* RGIDR_MODID[452]:SYSRAM07*/ + [431] = {0xFD442324U, 0x0000000BU}, /* RGIDR_MODID[453]:SYSRAM11*/ + [432] = {0xFD442328U, 0x0000000BU}, /* RGIDR_MODID[454]:SYSRAM12*/ + [433] = {0xFD44232CU, 0x0000000BU}, /* RGIDR_MODID[455]:SYSRAM13*/ + [434] = {0xFD442330U, 0x0000000BU}, /* RGIDR_MODID[456]:SYSRAM14*/ + [435] = {0xFD442334U, 0x0000000BU}, /* RGIDR_MODID[457]:SYSRAM15*/ + [436] = {0xFD442338U, 0x0000000BU}, /* RGIDR_MODID[458]:SYSRAM16*/ + [437] = {0xFD44233CU, 0x00000000U}, /* RGIDR_MODID[459]:SYSRAM17*/ + [438] = {0xFD442360U, 0x00000002U}, /* RGIDR_MODID[460]:BKBUF*/ + [439] = {0xFD442364U, 0x00000002U}, /* RGIDR_MODID[461]:AXICR52SS1*/ + [440] = {0xFD442368U, 0x00000002U}, /* RGIDR_MODID[462]:AXICR52SS2*/ + [441] = {0xFC862000U, 0x0000000FU}, /* RGIDR_MODID[463]:ARSC0*/ + /* After setting */ /* RGIDR_MODID[464]:ARSC1*/ + /* After setting */ /* RGIDR_MODID[465]:ARSC2*/ + [442] = {0xFC86200CU, 0x0000000FU}, /* RGIDR_MODID[466]:ARSC3*/ + [443] = {0xFC862010U, 0x0000000FU}, /* RGIDR_MODID[467]:ARSC4*/ + [444] = {0xFC862014U, 0x0000000FU}, /* RGIDR_MODID[468]:ARSC5*/ + [445] = {0xFC862018U, 0x0000000FU}, /* RGIDR_MODID[469]:ARSC6*/ + [446] = {0xFC86201CU, 0x0000000FU}, /* RGIDR_MODID[470]:ARSC7*/ + [447] = {0xFC862020U, 0x00000000U}, /* RGIDR_MODID[471]:ARSC8*/ + [448] = {0xFC862024U, 0x0000000FU}, /* RGIDR_MODID[472]:ARSTM0*/ + /* After setting */ /* RGIDR_MODID[473]:ARSTM1*/ + [449] = {0xFC86202CU, 0x0000000EU}, /* RGIDR_MODID[474]:CSD1S*/ + [450] = {0xFC862030U, 0x0000000EU}, /* RGIDR_MODID[475]:AXIFBABUSTOP0*/ + /* After setting */ /* RGIDR_MODID[476]:ARSTM2*/ + [451] = {0xFC86203CU, 0x0000000FU}, /* RGIDR_MODID[477]:ARSTM3*/ + [452] = {0xFC862040U, 0x0000000FU}, /* RGIDR_MODID[478]:ARSTM4*/ + [453] = {0xFC862044U, 0x0000000FU}, /* RGIDR_MODID[479]:ARSTM5*/ + [454] = {0xFC862048U, 0x0000000FU}, /* RGIDR_MODID[480]:ARSTM6*/ + [455] = {0xFC86204CU, 0x0000000FU}, /* RGIDR_MODID[481]:ARSTM7*/ + [456] = {0xFC862050U, 0x00000000U}, /* RGIDR_MODID[482]:ARSTM8*/ + [457] = {0xFC862054U, 0x0000000FU}, /* RGIDR_MODID[483]:ECMTOP*/ + [458] = {0xFC862058U, 0x0000000EU}, /* RGIDR_MODID[484]:FBA*/ + [459] = {0xFC86205CU, 0x0000000EU}, /* RGIDR_MODID[485]:FBC*/ + [460] = {0xFC862034U, 0x0000000CU}, /* RGIDR_MODID[486]:AXICCI00*/ + [461] = {0xFC862060U, 0x0000000CU}, /* RGIDR_MODID[487]:AXICCI01*/ + [462] = {0xFC862064U, 0x0000000CU}, /* RGIDR_MODID[488]:AXICCI10*/ + [463] = {0xFC862068U, 0x0000000CU}, /* RGIDR_MODID[489]:AXICCI11*/ + [464] = {0xFC86206CU, 0x0000000CU}, /* RGIDR_MODID[490]:AXICCI12*/ + [465] = {0xFC862070U, 0x0000000CU}, /* RGIDR_MODID[491]:AXICCI13*/ + [466] = {0xFC862074U, 0x0000000CU}, /* RGIDR_MODID[492]:AXICCI14*/ + [467] = {0xFC862078U, 0x0000000CU}, /* RGIDR_MODID[493]:AXICCI15*/ + [468] = {0xFC86207CU, 0x0000000CU}, /* RGIDR_MODID[494]:AXICCI2*/ + [469] = {0xFC862080U, 0x0000000CU}, /* RGIDR_MODID[495]:AXICCI3*/ + [470] = {0xFC862084U, 0x0000000CU}, /* RGIDR_MODID[496]:AXICCI4*/ + [471] = {0xFC862088U, 0x0000000CU}, /* RGIDR_MODID[497]:AXICCI5*/ + [472] = {0xFC86208CU, 0x0000000CU}, /* RGIDR_MODID[498]:AXICCI6*/ + [473] = {0xFC862090U, 0x0000000CU}, /* RGIDR_MODID[499]:AXICCI7*/ + [474] = {0xFC862094U, 0x0000000CU}, /* RGIDR_MODID[500]:AXICCI8*/ + [475] = {0xFC862098U, 0x0000000FU}, /* RGIDR_MODID[501]:AXICCI9*/ + [476] = {0xFC8620A0U, 0x0000000FU}, /* RGIDR_MODID[502]:ECMSTM*/ + [477] = {0xFCB82000U, 0x0000002CU}, /* RGIDR_MODID[503]:DMASSI00*/ + [478] = {0xFCB82004U, 0x0000002CU}, /* RGIDR_MODID[504]:DMASSI01*/ + [479] = {0xFCB82008U, 0x0000002CU}, /* RGIDR_MODID[505]:DMASSI02*/ + [480] = {0xFCB8200CU, 0x0000002CU}, /* RGIDR_MODID[506]:DMASSI03*/ + [481] = {0xFCB82010U, 0x0000002CU}, /* RGIDR_MODID[507]:DMASSI04*/ + [482] = {0xFCB82014U, 0x0000004EU}, /* RGIDR_MODID[508]:DMAI2C0*/ + [483] = {0xFCB82018U, 0x0000004EU}, /* RGIDR_MODID[509]:DMAI2C1*/ + [484] = {0xFCB8201CU, 0x0000004EU}, /* RGIDR_MODID[510]:DMAI2C2*/ + [485] = {0xFCB82020U, 0x0000004EU}, /* RGIDR_MODID[511]:DMAI2C3*/ + [486] = {0xFCB8202CU, 0x0000002CU}, /* RGIDR_MODID[512]:DMASSI05*/ + [487] = {0xFCB82030U, 0x0000002CU}, /* RGIDR_MODID[513]:DMASSI06*/ + [488] = {0xFCB82034U, 0x0000002CU}, /* RGIDR_MODID[514]:DMASSI07*/ + [489] = {0xFDDC2000U, 0x00000007U}, /* RGIDR_MODID[515]:ARMM*/ + /* After setting */ /* RGIDR_MODID[516]:AXIARNMM*/ + [490] = {0xFDDC2008U, 0x0000000FU}, /* RGIDR_MODID[517]:ARSM0*/ + /* After setting */ /* RGIDR_MODID[518]:ARSM1*/ + /* After setting */ /* RGIDR_MODID[519]:ARSM2*/ + [491] = {0xFDDC2014U, 0x0000000FU}, /* RGIDR_MODID[520]:AXIQOS0*/ + [492] = {0xFDDC2018U, 0x0000000FU}, /* RGIDR_MODID[521]:AXIQOS1*/ + [493] = {0xFDDC201CU, 0x0000000FU}, /* RGIDR_MODID[522]:AXIQOS2*/ + [494] = {0xFDDC2020U, 0x0000000FU}, /* RGIDR_MODID[523]:AXIQOS3*/ + [495] = {0xFDDC2024U, 0x0000000FU}, /* RGIDR_MODID[524]:AXIQOS4*/ + [496] = {0xFDDC2028U, 0x0000000FU}, /* RGIDR_MODID[525]:AXIQOS5*/ + [497] = {0xFDDC2034U, 0x0000000FU}, /* RGIDR_MODID[526]:ARSM3*/ + [498] = {0xFDDC2038U, 0x0000000FU}, /* RGIDR_MODID[527]:ARSM4*/ + [499] = {0xFDDC203CU, 0x0000000FU}, /* RGIDR_MODID[528]:ARSM5*/ + [500] = {0xFDDC2040U, 0x0000000FU}, /* RGIDR_MODID[529]:ARSM6*/ + [501] = {0xFDDC2044U, 0x0000000FU}, /* RGIDR_MODID[530]:ARSM7*/ + [502] = {0xFDDC2048U, 0x00000000U}, /* RGIDR_MODID[531]:ARSM8*/ + [503] = {0xFDDC204CU, 0x0000000BU}, /* RGIDR_MODID[532]:AXMM0*/ + [504] = {0xFDDC2050U, 0x0000000BU}, /* RGIDR_MODID[533]:AXMM1*/ + [505] = {0xFDDC2054U, 0x00000000U}, /* RGIDR_MODID[534]:AXMMPMON*/ + [506] = {0xFDDC2058U, 0x0000000AU}, /* RGIDR_MODID[535]:CKMMM*/ + [507] = {0xFDDC205CU, 0x0000000FU}, /* RGIDR_MODID[536]:ECMMM*/ + [508] = {0xFDDC2060U, 0x0000000EU}, /* RGIDR_MODID[537]:FBADBSC0*/ + [509] = {0xFDDC2068U, 0x0000000EU}, /* RGIDR_MODID[538]:FBAMM*/ + [510] = {0xFDDC206CU, 0x0000004EU}, /* RGIDR_MODID[539]:IPMMUMM00*/ + [511] = {0xFDDC2070U, 0x0000000FU}, /* RGIDR_MODID[540]:DBS0A0*/ + [512] = {0xFDDC2074U, 0x0000000AU}, /* RGIDR_MODID[541]:DBS0A1*/ + [513] = {0xFDDC2084U, 0x00000009U}, /* RGIDR_MODID[542]:FCPRC*/ + [514] = {0xFDDC2088U, 0x0000000FU}, /* RGIDR_MODID[543]:DBS0D0*/ + [515] = {0xFDDC208CU, 0x0000000AU}, /* RGIDR_MODID[544]:DBS0D1*/ + [516] = {0xFDDC2098U, 0x0000000EU}, /* RGIDR_MODID[545]:FBADDR*/ + [517] = {0xFDDC209CU, 0x0000004EU}, /* RGIDR_MODID[546]:IPMMUMM01*/ + [518] = {0xFDDC20A0U, 0x0000004EU}, /* RGIDR_MODID[547]:IPMMUMM10*/ + [519] = {0xFDDC20A4U, 0x0000004EU}, /* RGIDR_MODID[548]:IPMMUMM11*/ + [520] = {0xFDDC20A8U, 0x0000004EU}, /* RGIDR_MODID[549]:IPMMUMM12*/ + [521] = {0xFDDC20ACU, 0x0000004EU}, /* RGIDR_MODID[550]:IPMMUMM13*/ + [522] = {0xFDDC20B0U, 0x0000004EU}, /* RGIDR_MODID[551]:IPMMUMM14*/ + [523] = {0xFDDC20B4U, 0x0000004EU}, /* RGIDR_MODID[552]:IPMMUMM15*/ + [524] = {0xFDDC20B8U, 0x0000004EU}, /* RGIDR_MODID[553]:IPMMUMM02*/ + [525] = {0xFDDC20BCU, 0x0000004EU}, /* RGIDR_MODID[554]:IPMMUMM03*/ + [526] = {0xFDDC20C0U, 0x0000004EU}, /* RGIDR_MODID[555]:IPMMUMM04*/ + [527] = {0xFDDC20C4U, 0x0000004EU}, /* RGIDR_MODID[556]:IPMMUMM05*/ + [528] = {0xFDDC20C8U, 0x0000004EU}, /* RGIDR_MODID[557]:IPMMUMM06*/ + [529] = {0xFDDC20CCU, 0x0000004EU}, /* RGIDR_MODID[558]:IPMMUMM07*/ + [530] = {0xFDDC20D0U, 0x0000004EU}, /* RGIDR_MODID[559]:IPMMUMM08*/ + [531] = {0xFDDC20D4U, 0x0000004EU}, /* RGIDR_MODID[560]:IPMMUMM09*/ + [532] = {0xFC802000U, 0x0000000FU}, /* RGIDR_MODID[561]:ARSN0*/ + /* After setting */ /* RGIDR_MODID[562]:ARSN1*/ + /* After setting */ /* RGIDR_MODID[563]:ARSN2*/ + [533] = {0xFC80200CU, 0x0000000FU}, /* RGIDR_MODID[564]:ARSN3*/ + [534] = {0xFC802010U, 0x0000000FU}, /* RGIDR_MODID[565]:ARSN4*/ + [535] = {0xFC802014U, 0x0000000FU}, /* RGIDR_MODID[566]:ARSN5*/ + [536] = {0xFC802018U, 0x0000000FU}, /* RGIDR_MODID[567]:ARSN6*/ + [537] = {0xFC80201CU, 0x00000007U}, /* RGIDR_MODID[568]:ARSN7*/ + [538] = {0xFC802020U, 0x00000000U}, /* RGIDR_MODID[569]:ARSN8*/ + [539] = {0xFC802024U, 0x0000000FU}, /* RGIDR_MODID[570]:ECMTOP3*/ + [540] = {0xFCB52000U, 0x0000000FU}, /* RGIDR_MODID[571]:ARSD00*/ + /* After setting */ /* RGIDR_MODID[572]:ARSD01*/ + /* After setting */ /* RGIDR_MODID[573]:ARSD02*/ + [541] = {0xFCB5200CU, 0x0000000FU}, /* RGIDR_MODID[574]:ARSD03*/ + [542] = {0xFCB52010U, 0x0000000FU}, /* RGIDR_MODID[575]:ARSD04*/ + [543] = {0xFCB52014U, 0x0000000FU}, /* RGIDR_MODID[576]:ARSD05*/ + [544] = {0xFCB52018U, 0x0000000FU}, /* RGIDR_MODID[577]:ARSD06*/ + [545] = {0xFCB5201CU, 0x0000004AU}, /* RGIDR_MODID[578]:AXIFRAY*/ + [546] = {0xFCB52028U, 0x0000004FU}, /* RGIDR_MODID[579]:AXIRPC*/ + [547] = {0xFCB5202CU, 0x0000000FU}, /* RGIDR_MODID[580]:AXISDHI0*/ + [548] = {0xFCB52030U, 0x0000000FU}, /* RGIDR_MODID[581]:ARSD07*/ + [549] = {0xFCB52034U, 0x00000000U}, /* RGIDR_MODID[582]:ARSD08*/ + [550] = {0xFCB52038U, 0x0000000FU}, /* RGIDR_MODID[583]:ARSP00*/ + /* After setting */ /* RGIDR_MODID[584]:ARSP01*/ + /* After setting */ /* RGIDR_MODID[585]:ARSP02*/ + [551] = {0xFCB52044U, 0x0000000FU}, /* RGIDR_MODID[586]:ARSP03*/ + [552] = {0xFCB52048U, 0x0000000FU}, /* RGIDR_MODID[587]:ARSP04*/ + [553] = {0xFCB5204CU, 0x0000000FU}, /* RGIDR_MODID[588]:ARSP05*/ + [554] = {0xFCB52050U, 0x0000000FU}, /* RGIDR_MODID[589]:ARSP06*/ + [555] = {0xFCB52054U, 0x00000007U}, /* RGIDR_MODID[590]:ARSP07*/ + [556] = {0xFCB52058U, 0x00000000U}, /* RGIDR_MODID[591]:ARSP08*/ + [557] = {0xFCB5205CU, 0x0000004EU}, /* RGIDR_MODID[592]:IPMMUDS001*/ + [558] = {0xFCB52060U, 0x0000000AU}, /* RGIDR_MODID[593]:CKMPER0*/ + [559] = {0xFCB52064U, 0x0000000FU}, /* RGIDR_MODID[594]:ECMPER0*/ + [560] = {0xFCB52068U, 0x0000000EU}, /* RGIDR_MODID[595]:FBAPER0*/ + [561] = {0xFCB5206CU, 0x0000004EU}, /* RGIDR_MODID[596]:FSO0*/ + [562] = {0xFCB52070U, 0x0000004EU}, /* RGIDR_MODID[597]:FSO1*/ + [563] = {0xFCB52074U, 0x0000004EU}, /* RGIDR_MODID[598]:FSO10*/ + [564] = {0xFCB52078U, 0x0000004EU}, /* RGIDR_MODID[599]:FSO2*/ + [565] = {0xFCB5207CU, 0x0000004EU}, /* RGIDR_MODID[600]:FSO3*/ + [566] = {0xFCB52080U, 0x0000004EU}, /* RGIDR_MODID[601]:FSO4*/ + [567] = {0xFCB52084U, 0x0000004EU}, /* RGIDR_MODID[602]:FSO5*/ + [568] = {0xFCB52088U, 0x0000004EU}, /* RGIDR_MODID[603]:FSO6*/ + [569] = {0xFCB5208CU, 0x0000004EU}, /* RGIDR_MODID[604]:FSO7*/ + [570] = {0xFCB52090U, 0x0000004EU}, /* RGIDR_MODID[605]:FSO8*/ + [571] = {0xFCB52094U, 0x0000004EU}, /* RGIDR_MODID[606]:FSO9*/ + [572] = {0xFCB52098U, 0x0000002CU}, /* RGIDR_MODID[607]:ADG*/ + [573] = {0xFCB5209CU, 0x0000000FU}, /* RGIDR_MODID[608]:ECMSD0*/ + [574] = {0xFCB520A0U, 0x0000004EU}, /* RGIDR_MODID[609]:IPMMUDS010*/ + [575] = {0xFCB520A4U, 0x0000004EU}, /* RGIDR_MODID[610]:IPMMUDS011*/ + [576] = {0xFCB520A8U, 0x0000004EU}, /* RGIDR_MODID[611]:I2C0*/ + [577] = {0xFCB520ACU, 0x0000004EU}, /* RGIDR_MODID[612]:I2C1*/ + [578] = {0xFCB520B0U, 0x0000004EU}, /* RGIDR_MODID[613]:I2C2*/ + [579] = {0xFCB520B4U, 0x0000004EU}, /* RGIDR_MODID[614]:I2C3*/ + [580] = {0xFCB520C0U, 0x0000004EU}, /* RGIDR_MODID[615]:IPMMUDS012*/ + [581] = {0xFCB520C8U, 0x0000004EU}, /* RGIDR_MODID[616]:IPMMUDS000*/ + [582] = {0xFCB520CCU, 0x0000004EU}, /* RGIDR_MODID[617]:IPMMUDS013*/ + [583] = {0xFCB520D0U, 0x0000004EU}, /* RGIDR_MODID[618]:IPMMUDS014*/ + [584] = {0xFCB520D4U, 0x0000004EU}, /* RGIDR_MODID[619]:IPMMUDS015*/ + [585] = {0xFCB520D8U, 0x0000004EU}, /* RGIDR_MODID[620]:IPMMUDS002*/ + [586] = {0xFCB520DCU, 0x0000004EU}, /* RGIDR_MODID[621]:IPMMUDS003*/ + [587] = {0xFCB520E0U, 0x0000004EU}, /* RGIDR_MODID[622]:IPMMUDS004*/ + [588] = {0xFCB520E4U, 0x0000004EU}, /* RGIDR_MODID[623]:IPMMUDS005*/ + [589] = {0xFCB520E8U, 0x0000002CU}, /* RGIDR_MODID[624]:SSI*/ + [590] = {0xFCB520ECU, 0x0000004EU}, /* RGIDR_MODID[625]:IPMMUDS006*/ + [591] = {0xFCB520F0U, 0x0000004EU}, /* RGIDR_MODID[626]:IPMMUDS007*/ + [592] = {0xFCB520F4U, 0x0000000CU}, /* RGIDR_MODID[627]:SYDM1P*/ + [593] = {0xFCB520F8U, 0x0000004EU}, /* RGIDR_MODID[628]:IPMMUDS008*/ + [594] = {0xFCB520FCU, 0x0000000CU}, /* RGIDR_MODID[629]:SYDM2P*/ + [595] = {0xFCB52100U, 0x0000004EU}, /* RGIDR_MODID[630]:IPMMUDS009*/ + [596] = {0xFCB52240U, 0x0000000CU}, /* RGIDR_MODID[631]:SYDM100*/ + [597] = {0xFCB52244U, 0x0000000CU}, /* RGIDR_MODID[632]:SYDM101*/ + [598] = {0xFCB52248U, 0x0000000CU}, /* RGIDR_MODID[633]:SYDM110*/ + [599] = {0xFCB5224CU, 0x0000000CU}, /* RGIDR_MODID[634]:SYDM111*/ + [600] = {0xFCB52250U, 0x0000000CU}, /* RGIDR_MODID[635]:SYDM112*/ + [601] = {0xFCB52254U, 0x0000000CU}, /* RGIDR_MODID[636]:SYDM113*/ + [602] = {0xFCB52258U, 0x0000000CU}, /* RGIDR_MODID[637]:SYDM114*/ + [603] = {0xFCB5225CU, 0x0000000CU}, /* RGIDR_MODID[638]:SYDM115*/ + [604] = {0xFCB52260U, 0x0000000CU}, /* RGIDR_MODID[639]:SYDM102*/ + [605] = {0xFCB52264U, 0x0000000CU}, /* RGIDR_MODID[640]:SYDM103*/ + [606] = {0xFCB52268U, 0x0000000CU}, /* RGIDR_MODID[641]:SYDM104*/ + [607] = {0xFCB5226CU, 0x0000000CU}, /* RGIDR_MODID[642]:SYDM105*/ + [608] = {0xFCB52270U, 0x0000000CU}, /* RGIDR_MODID[643]:SYDM106*/ + [609] = {0xFCB52274U, 0x0000000CU}, /* RGIDR_MODID[644]:SYDM107*/ + [610] = {0xFCB52278U, 0x0000000CU}, /* RGIDR_MODID[645]:SYDM108*/ + [611] = {0xFCB5227CU, 0x0000000CU}, /* RGIDR_MODID[646]:SYDM109*/ + [612] = {0xFCB52280U, 0x0000000CU}, /* RGIDR_MODID[647]:SYDM200*/ + [613] = {0xFCB52284U, 0x0000000CU}, /* RGIDR_MODID[648]:SYDM201*/ + [614] = {0xFCB52288U, 0x0000000CU}, /* RGIDR_MODID[649]:SYDM210*/ + [615] = {0xFCB5228CU, 0x0000000CU}, /* RGIDR_MODID[650]:SYDM211*/ + [616] = {0xFCB52290U, 0x0000000CU}, /* RGIDR_MODID[651]:SYDM212*/ + [617] = {0xFCB52294U, 0x0000000CU}, /* RGIDR_MODID[652]:SYDM213*/ + [618] = {0xFCB52298U, 0x0000000CU}, /* RGIDR_MODID[653]:SYDM214*/ + [619] = {0xFCB5229CU, 0x0000000CU}, /* RGIDR_MODID[654]:SYDM215*/ + [620] = {0xFCB522A0U, 0x0000000CU}, /* RGIDR_MODID[655]:SYDM202*/ + [621] = {0xFCB522A4U, 0x0000000CU}, /* RGIDR_MODID[656]:SYDM203*/ + [622] = {0xFCB522A8U, 0x0000000CU}, /* RGIDR_MODID[657]:SYDM204*/ + [623] = {0xFCB522ACU, 0x0000000CU}, /* RGIDR_MODID[658]:SYDM205*/ + [624] = {0xFCB522B0U, 0x0000000CU}, /* RGIDR_MODID[659]:SYDM206*/ + [625] = {0xFCB522B4U, 0x0000000CU}, /* RGIDR_MODID[660]:SYDM207*/ + [626] = {0xFCB522B8U, 0x0000000CU}, /* RGIDR_MODID[661]:SYDM208*/ + [627] = {0xFCB522BCU, 0x0000000CU}, /* RGIDR_MODID[662]:SYDM209*/ + [628] = {0xFC682000U, 0x0000000FU}, /* RGIDR_MODID[663]:ARVC0*/ + /* After setting */ /* RGIDR_MODID[664]:ARVC1*/ + /* After setting */ /* RGIDR_MODID[665]:ARVC2*/ + [629] = {0xFC68200CU, 0x0000000FU}, /* RGIDR_MODID[666]:ARVC3*/ + [630] = {0xFC682010U, 0x0000000EU}, /* RGIDR_MODID[667]:AXIFBABUSVC*/ + [631] = {0xFC682014U, 0x0000000FU}, /* RGIDR_MODID[668]:ARVC4*/ + [632] = {0xFC682018U, 0x0000000FU}, /* RGIDR_MODID[669]:ARVC5*/ + [633] = {0xFC68201CU, 0x0000000FU}, /* RGIDR_MODID[670]:ARVC6*/ + [634] = {0xFC682020U, 0x0000000FU}, /* RGIDR_MODID[671]:ARVC7*/ + [635] = {0xFC682024U, 0x00000000U}, /* RGIDR_MODID[672]:ARVC8*/ + [636] = {0xFC68202CU, 0x0000000FU}, /* RGIDR_MODID[673]:ECMVC0*/ + [637] = {0xFC682034U, 0x0000004EU}, /* RGIDR_MODID[674]:IMR0*/ + [638] = {0xFC682038U, 0x0000004EU}, /* RGIDR_MODID[675]:IMR1*/ + [639] = {0xFC68203CU, 0x0000004EU}, /* RGIDR_MODID[676]:IPMMUVC01*/ + [640] = {0xFC682040U, 0x0000004EU}, /* RGIDR_MODID[677]:IPMMUVC10*/ + [641] = {0xFC682044U, 0x0000000CU}, /* RGIDR_MODID[678]:IMS0*/ + [642] = {0xFC682048U, 0x0000000CU}, /* RGIDR_MODID[679]:IMS1*/ + [643] = {0xFC68204CU, 0x0000004EU}, /* RGIDR_MODID[680]:IPMMUVC00*/ + [644] = {0xFC682050U, 0x0000004EU}, /* RGIDR_MODID[681]:IPMMUVC11*/ + [645] = {0xFC682054U, 0x0000004EU}, /* RGIDR_MODID[682]:IPMMUVC12*/ + [646] = {0xFC682058U, 0x0000004EU}, /* RGIDR_MODID[683]:IPMMUVC13*/ + [647] = {0xFC68205CU, 0x0000004EU}, /* RGIDR_MODID[684]:IPMMUVC14*/ + [648] = {0xFC682060U, 0x0000004EU}, /* RGIDR_MODID[685]:IPMMUVC15*/ + [649] = {0xFC682064U, 0x0000004EU}, /* RGIDR_MODID[686]:IPMMUVC02*/ + [650] = {0xFC682068U, 0x0000004EU}, /* RGIDR_MODID[687]:IPMMUVC03*/ + [651] = {0xFC68206CU, 0x0000004EU}, /* RGIDR_MODID[688]:IPMMUVC04*/ + [652] = {0xFC682070U, 0x0000004EU}, /* RGIDR_MODID[689]:IPMMUVC05*/ + [653] = {0xFC682074U, 0x0000004EU}, /* RGIDR_MODID[690]:IPMMUVC06*/ + [654] = {0xFC682078U, 0x0000004EU}, /* RGIDR_MODID[691]:IPMMUVC07*/ + [655] = {0xFC68207CU, 0x0000004EU}, /* RGIDR_MODID[692]:IPMMUVC08*/ + [656] = {0xFC682080U, 0x0000004EU}, /* RGIDR_MODID[693]:IPMMUVC09*/ + [657] = {0xFC682084U, 0x00000028U}, /* RGIDR_MODID[694]:IV1ES*/ + [658] = {0xFEBE2000U, 0x0000004EU}, /* RGIDR_MODID[695]:CSITOP0*/ + [659] = {0xFEBE2004U, 0x0000000FU}, /* RGIDR_MODID[696]:ARVI10*/ + /* After setting */ /* RGIDR_MODID[697]:ARVI11*/ + /* After setting */ /* RGIDR_MODID[698]:ARVI12*/ + [660] = {0xFEBE2010U, 0x0000000FU}, /* RGIDR_MODID[699]:ARVI13*/ + [661] = {0xFEBE2014U, 0x0000000FU}, /* RGIDR_MODID[700]:ARVI14*/ + [662] = {0xFEBE2018U, 0x0000000FU}, /* RGIDR_MODID[701]:ARVI15*/ + [663] = {0xFEBE201CU, 0x0000000FU}, /* RGIDR_MODID[702]:ARVI16*/ + [664] = {0xFEBE2020U, 0x0000000FU}, /* RGIDR_MODID[703]:ARVI17*/ + [665] = {0xFEBE2024U, 0x00000000U}, /* RGIDR_MODID[704]:ARVI18*/ + [666] = {0xFEBE202CU, 0x0000004EU}, /* RGIDR_MODID[705]:CSITOP1*/ + [667] = {0xFEBE2034U, 0x0000004EU}, /* RGIDR_MODID[706]:DSITLINK0*/ + [668] = {0xFEBE203CU, 0x0000000FU}, /* RGIDR_MODID[707]:ECMVIO1*/ + [669] = {0xFEBE2044U, 0x0000004EU}, /* RGIDR_MODID[708]:IPMMUVI001*/ + [670] = {0xFEBE2048U, 0x0000000CU}, /* RGIDR_MODID[709]:FCPVX0*/ + [671] = {0xFEBE2058U, 0x0000004EU}, /* RGIDR_MODID[710]:IPMMUVI000*/ + [672] = {0xFEBE205CU, 0x0000004EU}, /* RGIDR_MODID[711]:IPMMUVI100*/ + [673] = {0xFEBE2060U, 0x0000004EU}, /* RGIDR_MODID[712]:IPMMUVI010*/ + [674] = {0xFEBE2064U, 0x0000004EU}, /* RGIDR_MODID[713]:IPMMUVI011*/ + [675] = {0xFEBE2068U, 0x0000004EU}, /* RGIDR_MODID[714]:VSPX0*/ + [676] = {0xFEBE2078U, 0x0000004EU}, /* RGIDR_MODID[715]:IPMMUVI012*/ + [677] = {0xFEBE207CU, 0x0000004EU}, /* RGIDR_MODID[716]:IPMMUVI013*/ + [678] = {0xFEBE2080U, 0x0000004EU}, /* RGIDR_MODID[717]:IPMMUVI014*/ + [679] = {0xFEBE2084U, 0x0000004EU}, /* RGIDR_MODID[718]:IPMMUVI015*/ + [680] = {0xFEBE2088U, 0x0000004EU}, /* RGIDR_MODID[719]:IPMMUVI002*/ + [681] = {0xFEBE208CU, 0x0000004EU}, /* RGIDR_MODID[720]:IPMMUVI003*/ + [682] = {0xFEBE2090U, 0x0000004EU}, /* RGIDR_MODID[721]:IPMMUVI004*/ + [683] = {0xFEBE2094U, 0x0000004EU}, /* RGIDR_MODID[722]:IPMMUVI005*/ + [684] = {0xFEBE2098U, 0x0000004EU}, /* RGIDR_MODID[723]:IPMMUVI006*/ + [685] = {0xFEBE209CU, 0x0000004EU}, /* RGIDR_MODID[724]:IPMMUVI007*/ + [686] = {0xFEBE20A0U, 0x0000004EU}, /* RGIDR_MODID[725]:IPMMUVI008*/ + [687] = {0xFEBE20A4U, 0x0000004EU}, /* RGIDR_MODID[726]:IPMMUVI009*/ + [688] = {0xFEBE20A8U, 0x0000004EU}, /* RGIDR_MODID[727]:IPMMUVI101*/ + [689] = {0xFEBE20ACU, 0x0000004EU}, /* RGIDR_MODID[728]:IPMMUVI110*/ + [690] = {0xFEBE20B0U, 0x0000004EU}, /* RGIDR_MODID[729]:IPMMUVI111*/ + [691] = {0xFEBE20B4U, 0x0000004EU}, /* RGIDR_MODID[730]:IPMMUVI112*/ + [692] = {0xFEBE20B8U, 0x0000004EU}, /* RGIDR_MODID[731]:IPMMUVI113*/ + [693] = {0xFEBE20BCU, 0x0000004EU}, /* RGIDR_MODID[732]:IPMMUVI114*/ + [694] = {0xFEBE20C0U, 0x0000004EU}, /* RGIDR_MODID[733]:IPMMUVI115*/ + [695] = {0xFEBE20C4U, 0x0000004EU}, /* RGIDR_MODID[734]:IPMMUVI102*/ + [696] = {0xFEBE20C8U, 0x0000004EU}, /* RGIDR_MODID[735]:IPMMUVI103*/ + [697] = {0xFEBE20CCU, 0x0000004EU}, /* RGIDR_MODID[736]:IPMMUVI104*/ + [698] = {0xFEBE20D0U, 0x0000004EU}, /* RGIDR_MODID[737]:IPMMUVI105*/ + [699] = {0xFEBE20D4U, 0x0000004EU}, /* RGIDR_MODID[738]:IPMMUVI106*/ + [700] = {0xFEBE20D8U, 0x0000004EU}, /* RGIDR_MODID[739]:IPMMUVI107*/ + [701] = {0xFEBE20DCU, 0x0000004EU}, /* RGIDR_MODID[740]:IPMMUVI108*/ + [702] = {0xFEBE20E0U, 0x0000004EU}, /* RGIDR_MODID[741]:IPMMUVI109*/ + [703] = {0xFEBE2104U, 0x0000000EU}, /* RGIDR_MODID[742]:AXIFBABUSVIO*/ + [704] = {0xFEBF2000U, 0x0000000FU}, /* RGIDR_MODID[743]:ARVI0*/ + /* After setting */ /* RGIDR_MODID[744]:ARVI1*/ + /* After setting */ /* RGIDR_MODID[745]:ARVI2*/ + [705] = {0xFEBF200CU, 0x0000000FU}, /* RGIDR_MODID[746]:ARVI3*/ + [706] = {0xFEBF2010U, 0x0000000FU}, /* RGIDR_MODID[747]:ARVI4*/ + [707] = {0xFEBF2014U, 0x0000000FU}, /* RGIDR_MODID[748]:ARVI5*/ + [708] = {0xFEBF2018U, 0x0000000FU}, /* RGIDR_MODID[749]:ARVI6*/ + [709] = {0xFEBF201CU, 0x0000000FU}, /* RGIDR_MODID[750]:ARVI7*/ + [710] = {0xFEBF2020U, 0x00000000U}, /* RGIDR_MODID[751]:ARVI8*/ + [711] = {0xFEBF2024U, 0x0000000FU}, /* RGIDR_MODID[752]:ECMVIO0*/ + [712] = {0xFEBF2028U, 0x0000004EU}, /* RGIDR_MODID[753]:ISP0*/ + [713] = {0xFEBF202CU, 0x0000004EU}, /* RGIDR_MODID[754]:ISP0CORE*/ + [714] = {0xFEBF2030U, 0x0000004EU}, /* RGIDR_MODID[755]:ISP1*/ + [715] = {0xFEBF2054U, 0x0000004EU}, /* RGIDR_MODID[756]:VIN00*/ + [716] = {0xFEBF2058U, 0x0000004EU}, /* RGIDR_MODID[757]:VIN01*/ + [717] = {0xFEBF205CU, 0x0000004EU}, /* RGIDR_MODID[758]:VIN02*/ + [718] = {0xFEBF2060U, 0x0000004EU}, /* RGIDR_MODID[759]:VIN03*/ + [719] = {0xFEBF2064U, 0x0000004EU}, /* RGIDR_MODID[760]:VIN04*/ + [720] = {0xFEBF2068U, 0x0000004EU}, /* RGIDR_MODID[761]:VIN05*/ + [721] = {0xFEBF206CU, 0x0000004EU}, /* RGIDR_MODID[762]:VIN06*/ + [722] = {0xFEBF2070U, 0x0000004EU}, /* RGIDR_MODID[763]:VIN07*/ + [723] = {0xFEBF2074U, 0x0000004EU}, /* RGIDR_MODID[764]:VIN10*/ + [724] = {0xFEBF2078U, 0x0000004EU}, /* RGIDR_MODID[765]:VIN11*/ + [725] = {0xFEBF207CU, 0x0000004EU}, /* RGIDR_MODID[766]:VIN12*/ + [726] = {0xFEBF2080U, 0x0000004EU}, /* RGIDR_MODID[767]:VIN13*/ + [727] = {0xFEBF2084U, 0x0000004EU}, /* RGIDR_MODID[768]:VIN14*/ + [728] = {0xFEBF2088U, 0x0000004EU}, /* RGIDR_MODID[769]:VIN15*/ + [729] = {0xFEBF208CU, 0x0000004EU}, /* RGIDR_MODID[770]:VIN16*/ + [730] = {0xFEBF2090U, 0x0000004EU}, /* RGIDR_MODID[771]:VIN17*/ + [731] = {0xFC312000U, 0x0000000FU}, /* RGIDR_MODID[772]:ARVIP00*/ + /* After setting */ /* RGIDR_MODID[773]:ARVIP01*/ + /* After setting */ /* RGIDR_MODID[774]:ARVIP02*/ + [732] = {0xFC31200CU, 0x0000000FU}, /* RGIDR_MODID[775]:ARVIP03*/ + [733] = {0xFC312010U, 0x0000000EU}, /* RGIDR_MODID[776]:AXIFBABUSVIP0*/ + [734] = {0xFC312014U, 0x0000000FU}, /* RGIDR_MODID[777]:ARVIP04*/ + [735] = {0xFC312018U, 0x0000000FU}, /* RGIDR_MODID[778]:ARVIP05*/ + [736] = {0xFC31201CU, 0x0000000FU}, /* RGIDR_MODID[779]:ARVIP06*/ + [737] = {0xFC312020U, 0x00000007U}, /* RGIDR_MODID[780]:ARVIP07*/ + [738] = {0xFC312024U, 0x00000000U}, /* RGIDR_MODID[781]:ARVIP08*/ + [739] = {0xFC31202CU, 0x0000000FU}, /* RGIDR_MODID[782]:ECMVIP0*/ + [740] = {0xFC312030U, 0x0000004EU}, /* RGIDR_MODID[783]:IPMMUVIP000*/ + [741] = {0xFC312038U, 0x0000004EU}, /* RGIDR_MODID[784]:SMPO0*/ + [742] = {0xFC31203CU, 0x0000004EU}, /* RGIDR_MODID[785]:SMPS0*/ + [743] = {0xFC312040U, 0x0000004EU}, /* RGIDR_MODID[786]:UMFL0*/ + [744] = {0xFC312044U, 0x0000004EU}, /* RGIDR_MODID[787]:IPMMUVIP001*/ + [745] = {0xFC312048U, 0x0000004EU}, /* RGIDR_MODID[788]:IPMMUVIP010*/ + [746] = {0xFC31204CU, 0x0000004EU}, /* RGIDR_MODID[789]:IPMMUVIP011*/ + [747] = {0xFC312050U, 0x0000004EU}, /* RGIDR_MODID[790]:UMFL0M_W*/ + [748] = {0xFC312054U, 0x0000004EU}, /* RGIDR_MODID[791]:IPMMUVIP012*/ + [749] = {0xFC312058U, 0x0000004EU}, /* RGIDR_MODID[792]:IPMMUVIP013*/ + [750] = {0xFC31205CU, 0x0000004EU}, /* RGIDR_MODID[793]:IPMMUVIP014*/ + [751] = {0xFC312060U, 0x0000004EU}, /* RGIDR_MODID[794]:IPMMUVIP015*/ + [752] = {0xFC312064U, 0x0000004EU}, /* RGIDR_MODID[795]:IPMMUVIP002*/ + [753] = {0xFC312068U, 0x0000004EU}, /* RGIDR_MODID[796]:IPMMUVIP003*/ + [754] = {0xFC31206CU, 0x0000004EU}, /* RGIDR_MODID[797]:IPMMUVIP004*/ + [755] = {0xFC312070U, 0x0000004EU}, /* RGIDR_MODID[798]:IPMMUVIP005*/ + [756] = {0xFC312074U, 0x0000004EU}, /* RGIDR_MODID[799]:IPMMUVIP006*/ + [757] = {0xFC312078U, 0x0000004EU}, /* RGIDR_MODID[800]:IPMMUVIP007*/ + [758] = {0xFC31207CU, 0x0000004EU}, /* RGIDR_MODID[801]:IPMMUVIP008*/ + [759] = {0xFC312080U, 0x0000004EU}, /* RGIDR_MODID[802]:IPMMUVIP009*/ + [760] = {0xFC8820A0U, 0x0000000FU}, /* RGIDR_MODID[803]:ARDSP0*/ + /* After setting */ /* RGIDR_MODID[804]:ARDSP1*/ + /* After setting */ /* RGIDR_MODID[805]:ARDSP2*/ + [761] = {0xFC8820ACU, 0x0000000FU}, /* RGIDR_MODID[806]:ARDSP3*/ + [762] = {0xFC8820B0U, 0x0000000FU}, /* RGIDR_MODID[807]:ARDSP4*/ + [763] = {0xFC8820B4U, 0x0000000FU}, /* RGIDR_MODID[808]:ARDSP5*/ + [764] = {0xFC8820B8U, 0x0000000FU}, /* RGIDR_MODID[809]:ARDSP6*/ + [765] = {0xFC8820BCU, 0x0000000FU}, /* RGIDR_MODID[810]:ARDSP7*/ + [766] = {0xFC8820C0U, 0x0000000FU}, /* RGIDR_MODID[811]:ECMDSP*/ + [767] = {0xFC882090U, 0x0000000CU}, /* RGIDR_MODID[812]:AXIDSP0*/ + [768] = {0xFC882094U, 0x0000000CU}, /* RGIDR_MODID[813]:AXIDSP1*/ + [769] = {0xFC882098U, 0x0000000CU}, /* RGIDR_MODID[814]:AXIDSP2*/ + [770] = {0xFC88209CU, 0x0000000CU}, /* RGIDR_MODID[815]:AXIDSP3*/ + [771] = {0xFC8820C4U, 0x0000004EU}, /* RGIDR_MODID[816]:IMPM0100*/ + [772] = {0xFC8820C8U, 0x0000004EU}, /* RGIDR_MODID[817]:IMPM0101*/ + [773] = {0xFC8820CCU, 0x0000004EU}, /* RGIDR_MODID[818]:IMPM0102*/ + [774] = {0xFC8820D0U, 0x0000004EU}, /* RGIDR_MODID[819]:IMPM0103*/ + [775] = {0xFC8820D4U, 0x0000004EU}, /* RGIDR_MODID[820]:IMPM0104*/ + [776] = {0xFC8820D8U, 0x0000004EU}, /* RGIDR_MODID[821]:IMPM0105*/ + [777] = {0xFC8820DCU, 0x0000004EU}, /* RGIDR_MODID[822]:IMPM0106*/ + [778] = {0xFC8820E0U, 0x0000004EU}, /* RGIDR_MODID[823]:IMPM0107*/ + [779] = {0xFC8820E4U, 0x0000004EU}, /* RGIDR_MODID[824]:IMPM0200*/ + [780] = {0xFC8820E8U, 0x0000004EU}, /* RGIDR_MODID[825]:IMPM0201*/ + [781] = {0xFC8820ECU, 0x0000004EU}, /* RGIDR_MODID[826]:IMPS0000*/ + [782] = {0xFC8820F0U, 0x0000004EU}, /* RGIDR_MODID[827]:IMPS0001*/ + [783] = {0xFC8820F4U, 0x0000004EU}, /* RGIDR_MODID[828]:IMPS0002*/ + [784] = {0xFC8820F8U, 0x0000004EU}, /* RGIDR_MODID[829]:IMPS0003*/ + [785] = {0xFC8820FCU, 0x0000004EU}, /* RGIDR_MODID[830]:IMPS0100*/ + [786] = {0xFC882100U, 0x0000004EU}, /* RGIDR_MODID[831]:IMPS0101*/ + [787] = {0xFC882104U, 0x0000004EU}, /* RGIDR_MODID[832]:IMPS0102*/ + [788] = {0xFC882108U, 0x0000004EU}, /* RGIDR_MODID[833]:IMPS0103*/ + [789] = {0xFC88210CU, 0x0000004EU}, /* RGIDR_MODID[834]:IMPS0104*/ + [790] = {0xFC882110U, 0x0000004EU}, /* RGIDR_MODID[835]:IMPS0105*/ + [791] = {0xFC882114U, 0x0000004EU}, /* RGIDR_MODID[836]:IMPS0106*/ + [792] = {0xFC882118U, 0x0000004EU}, /* RGIDR_MODID[837]:IMPS0107*/ + [793] = {0xFC88211CU, 0x0000004EU}, /* RGIDR_MODID[838]:IMPS0108*/ + [794] = {0xFC882120U, 0x0000004EU}, /* RGIDR_MODID[839]:IMPS0109*/ + [795] = {0xFC882124U, 0x0000004EU}, /* RGIDR_MODID[840]:IMPS0110*/ + [796] = {0xFC882128U, 0x0000004EU}, /* RGIDR_MODID[841]:IMPS0111*/ + [797] = {0xFC88212CU, 0x0000004EU}, /* RGIDR_MODID[842]:IMPS0200*/ + [798] = {0xFC882130U, 0x0000004EU}, /* RGIDR_MODID[843]:IMPS0201*/ + [799] = {0xFC882134U, 0x0000004EU}, /* RGIDR_MODID[844]:IMPS0202*/ + [801] = {0xFDDB9660U, 0x0000000FU}, /* RGIDR_MODID[845]:ARCC*/ + [800] = {0xFDDB9674U, 0x0000000FU}, /* RGIDR_MODID[846]:ARRTRAM*/ + [802] = {0xFCB52024U, 0x00000000U}, /* RGIDR_MODID[847]:RSV0*/ + [803] = {0xFC31210CU, 0x00000004U}, /* RGIDR_MODID[848]:PAP*/ + [804] = {0xFEBD2028U, 0x0000000CU}, /* RGIDR_MODID[849]:DOC*/ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_w_tbl" +const REGION_ID_SETTING_TABLE g_rgid_w_tbl[] = { + [0] = {0xFD482400U, 0x0000000EU}, /* RGIDW_MODID[0]:ARMGC0*/ + [1] = {0xFD482404U, 0x0000000EU}, /* RGIDW_MODID[1]:ARMGC1*/ + [2] = {0xFD482408U, 0x00000000U}, /* RGIDW_MODID[2]:ARMGC2*/ + [3] = {0xFD48240CU, 0x00000002U}, /* RGIDW_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDW_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDW_MODID[5]:ARRT02*/ + [4] = {0xFD482418U, 0x00000001U}, /* RGIDW_MODID[6]:ARRT03*/ + [5] = {0xFD48241CU, 0x00000002U}, /* RGIDW_MODID[7]:ARRT04*/ + [6] = {0xFD482420U, 0x00000001U}, /* RGIDW_MODID[8]:ARRT05*/ + [7] = {0xFD482424U, 0x00000002U}, /* RGIDW_MODID[9]:ARRT06*/ + [8] = {0xFD482428U, 0x00000002U}, /* RGIDW_MODID[10]:ARRT07*/ + [9] = {0xFD48242CU, 0x00000000U}, /* RGIDW_MODID[11]:ARRT08*/ + [10] = {0xFD482430U, 0x00000001U}, /* RGIDW_MODID[12]:LIFEC0*/ + [11] = {0xFD482434U, 0x0000000EU}, /* RGIDW_MODID[13]:SWDT*/ + [12] = {0xFD482438U, 0x0000006EU}, /* RGIDW_MODID[14]:TMU0*/ + [13] = {0xFD48243CU, 0x0000000EU}, /* RGIDW_MODID[15]:WDT*/ + [14] = {0xFD482440U, 0x0000000EU}, /* RGIDW_MODID[16]:WWDT0*/ + [15] = {0xFD482444U, 0x0000000EU}, /* RGIDW_MODID[17]:WWDT1*/ + [16] = {0xFD482448U, 0x0000000EU}, /* RGIDW_MODID[18]:WWDT2*/ + [17] = {0xFD48244CU, 0x0000000EU}, /* RGIDW_MODID[19]:WWDT3*/ + [18] = {0xFD482450U, 0x0000000EU}, /* RGIDW_MODID[20]:WWDT4*/ + [19] = {0xFD482454U, 0x0000000EU}, /* RGIDW_MODID[21]:WWDT5*/ + [20] = {0xFD482458U, 0x0000000EU}, /* RGIDW_MODID[22]:WWDT6*/ + [21] = {0xFD482468U, 0x0000000AU}, /* RGIDW_MODID[23]:ECMRT3*/ + [22] = {0xFDA02404U, 0x0000000FU}, /* RGIDW_MODID[24]:APMU0*/ + [23] = {0xFDA02408U, 0x00000002U}, /* RGIDW_MODID[25]:APMU1*/ + [24] = {0xFDA0240CU, 0x00000000U}, /* RGIDW_MODID[26]:APMU10*/ + [25] = {0xFDA02410U, 0x00000000U}, /* RGIDW_MODID[27]:APMU11*/ + [26] = {0xFDA02414U, 0x00000000U}, /* RGIDW_MODID[28]:APMU12*/ + [27] = {0xFDA02418U, 0x00000000U}, /* RGIDW_MODID[29]:APMU13*/ + [28] = {0xFDA0241CU, 0x00000000U}, /* RGIDW_MODID[30]:APMU14*/ + [29] = {0xFDA02420U, 0x00000000U}, /* RGIDW_MODID[31]:APMU15*/ + [30] = {0xFDA02424U, 0x00000004U}, /* RGIDW_MODID[32]:APMU2*/ + [31] = {0xFDA02428U, 0x00000004U}, /* RGIDW_MODID[33]:APMU3*/ + [32] = {0xFDA0242CU, 0x00000000U}, /* RGIDW_MODID[34]:APMU4*/ + [33] = {0xFDA02430U, 0x00000000U}, /* RGIDW_MODID[35]:APMU5*/ + [34] = {0xFDA02434U, 0x00000000U}, /* RGIDW_MODID[36]:APMU6*/ + [35] = {0xFDA02438U, 0x00000000U}, /* RGIDW_MODID[37]:APMU7*/ + [36] = {0xFDA0243CU, 0x00000000U}, /* RGIDW_MODID[38]:APMU8*/ + [37] = {0xFDA02440U, 0x00000000U}, /* RGIDW_MODID[39]:APMU9*/ + [38] = {0xFDA02444U, 0x00000002U}, /* RGIDW_MODID[40]:ARS00*/ + /* After setting */ /* RGIDW_MODID[41]:ARS01*/ + /* After setting */ /* RGIDW_MODID[42]:ARS02*/ + [39] = {0xFDA02450U, 0x00000001U}, /* RGIDW_MODID[43]:ARS03*/ + [40] = {0xFDA02454U, 0x00000002U}, /* RGIDW_MODID[44]:ARS04*/ + [41] = {0xFDA02458U, 0x00000001U}, /* RGIDW_MODID[45]:ARS05*/ + [42] = {0xFDA0245CU, 0x00000002U}, /* RGIDW_MODID[46]:ARS06*/ + [43] = {0xFDA02460U, 0x00000002U}, /* RGIDW_MODID[47]:ARS07*/ + [44] = {0xFDA02464U, 0x00000000U}, /* RGIDW_MODID[48]:ARS08*/ + [45] = {0xFDA02468U, 0x0000000EU}, /* RGIDW_MODID[49]:CMT0*/ + [46] = {0xFDA0246CU, 0x0000000EU}, /* RGIDW_MODID[50]:CMT1*/ + [47] = {0xFDA02470U, 0x0000000EU}, /* RGIDW_MODID[51]:CMT2*/ + [48] = {0xFDA02474U, 0x0000000EU}, /* RGIDW_MODID[52]:CMT3*/ + [49] = {0xFDA02478U, 0x0000000AU}, /* RGIDW_MODID[53]:CKM*/ + [50] = {0xFDA0247CU, 0x0000000EU}, /* RGIDW_MODID[54]:DBE*/ + [51] = {0xFDA02480U, 0x0000000EU}, /* RGIDW_MODID[55]:IRQC*/ + [52] = {0xFDA02484U, 0x0000000AU}, /* RGIDW_MODID[56]:ECMPS0*/ + [53] = {0xFDA02488U, 0x0000000BU}, /* RGIDW_MODID[57]:OTP0*/ + [54] = {0xFDA0248CU, 0x0000000FU}, /* RGIDW_MODID[58]:OTP1*/ + [55] = {0xFDA0249CU, 0x0000000EU}, /* RGIDW_MODID[59]:SCMT*/ + [56] = {0xFDA024A8U, 0x0000004AU}, /* RGIDW_MODID[60]:TSC1*/ + [57] = {0xFDA024ACU, 0x0000004AU}, /* RGIDW_MODID[61]:TSC2*/ + [58] = {0xFDA024B8U, 0x00000006U}, /* RGIDW_MODID[62]:UCMT*/ + [59] = {0xFDA02500U, 0x0000006FU}, /* RGIDW_MODID[63]:CPG0*/ + [60] = {0xFDA02504U, 0x0000000AU}, /* RGIDW_MODID[64]:CPG1*/ + [61] = {0xFDA02508U, 0x0000004EU}, /* RGIDW_MODID[65]:CPG2*/ + [62] = {0xFDA0250CU, 0x00000028U}, /* RGIDW_MODID[66]:CPG3*/ + [63] = {0xFDA02510U, 0x0000006FU}, /* RGIDW_MODID[67]:PFC00*/ + [64] = {0xFDA02514U, 0x0000000AU}, /* RGIDW_MODID[68]:PFC01*/ + [65] = {0xFDA02518U, 0x0000004EU}, /* RGIDW_MODID[69]:PFC02*/ + [66] = {0xFDA0251CU, 0x00000028U}, /* RGIDW_MODID[70]:PFC03*/ + [67] = {0xFDA02520U, 0x0000006FU}, /* RGIDW_MODID[71]:PFC10*/ + [68] = {0xFDA02524U, 0x0000000AU}, /* RGIDW_MODID[72]:PFC11*/ + [69] = {0xFDA02528U, 0x0000004EU}, /* RGIDW_MODID[73]:PFC12*/ + [70] = {0xFDA0252CU, 0x00000028U}, /* RGIDW_MODID[74]:PFC13*/ + [71] = {0xFDA02530U, 0x0000006FU}, /* RGIDW_MODID[75]:PFC20*/ + [72] = {0xFDA02534U, 0x0000000AU}, /* RGIDW_MODID[76]:PFC21*/ + [73] = {0xFDA02538U, 0x0000004EU}, /* RGIDW_MODID[77]:PFC22*/ + [74] = {0xFDA0253CU, 0x00000028U}, /* RGIDW_MODID[78]:PFC23*/ + [75] = {0xFDA02550U, 0x0000006FU}, /* RGIDW_MODID[79]:PFCS0*/ + [76] = {0xFDA02554U, 0x0000000AU}, /* RGIDW_MODID[80]:PFCS1*/ + [77] = {0xFDA02558U, 0x0000004EU}, /* RGIDW_MODID[81]:PFCS2*/ + [78] = {0xFDA0255CU, 0x00000028U}, /* RGIDW_MODID[82]:PFCS3*/ + [79] = {0xFDA02560U, 0x0000006FU}, /* RGIDW_MODID[83]:RESET0*/ + [80] = {0xFDA02564U, 0x0000000AU}, /* RGIDW_MODID[84]:RESET1*/ + [81] = {0xFDA02568U, 0x0000004EU}, /* RGIDW_MODID[85]:RESET2*/ + [82] = {0xFDA0256CU, 0x00000028U}, /* RGIDW_MODID[86]:RESET3*/ + [83] = {0xFDA02570U, 0x0000006FU}, /* RGIDW_MODID[87]:SYS0*/ + [84] = {0xFDA02574U, 0x0000000AU}, /* RGIDW_MODID[88]:SYS1*/ + [85] = {0xFDA02578U, 0x0000004EU}, /* RGIDW_MODID[89]:SYS2*/ + [86] = {0xFDA0257CU, 0x00000028U}, /* RGIDW_MODID[90]:SYS3*/ + [87] = {0xFCB62400U, 0x0000000EU}, /* RGIDW_MODID[91]:DMAMSI0*/ + [88] = {0xFCB62404U, 0x0000000EU}, /* RGIDW_MODID[92]:DMAMSI1*/ + [89] = {0xFCB62408U, 0x0000000EU}, /* RGIDW_MODID[93]:DMAMSI2*/ + [90] = {0xFCB6240CU, 0x0000000EU}, /* RGIDW_MODID[94]:DMAMSI3*/ + [91] = {0xFCB62410U, 0x0000000EU}, /* RGIDW_MODID[95]:DMAMSI4*/ + [92] = {0xFCB62414U, 0x0000000EU}, /* RGIDW_MODID[96]:DMAMSI5*/ + [93] = {0xFCB62418U, 0x0000000AU}, /* RGIDW_MODID[97]:ECMSP3*/ + [94] = {0xFCB62424U, 0x00000002U}, /* RGIDW_MODID[98]:ARSP30*/ + /* After setting */ /* RGIDW_MODID[99]:ARSP31*/ + /* After setting */ /* RGIDW_MODID[100]:ARSP32*/ + [95] = {0xFCB62430U, 0x00000001U}, /* RGIDW_MODID[101]:ARSP33*/ + [96] = {0xFCB62434U, 0x00000002U}, /* RGIDW_MODID[102]:ARSP34*/ + [97] = {0xFCB62438U, 0x00000001U}, /* RGIDW_MODID[103]:ARSP35*/ + [98] = {0xFCB6243CU, 0x00000002U}, /* RGIDW_MODID[104]:ARSP36*/ + [99] = {0xFCB62440U, 0x00000002U}, /* RGIDW_MODID[105]:ARSP37*/ + [100] = {0xFCB62444U, 0x00000000U}, /* RGIDW_MODID[106]:ARSP38*/ + [101] = {0xFCB62448U, 0x0000000EU}, /* RGIDW_MODID[107]:MSI0*/ + [102] = {0xFCB6244CU, 0x0000000EU}, /* RGIDW_MODID[108]:MSI1*/ + [103] = {0xFCB62450U, 0x0000000EU}, /* RGIDW_MODID[109]:MSI2*/ + [104] = {0xFCB62454U, 0x0000000EU}, /* RGIDW_MODID[110]:MSI3*/ + [105] = {0xFCB62458U, 0x0000000EU}, /* RGIDW_MODID[111]:MSI4*/ + [106] = {0xFCB6245CU, 0x0000000EU}, /* RGIDW_MODID[112]:MSI5*/ + [107] = {0xFCB92400U, 0x00000002U}, /* RGIDW_MODID[113]:ARSP40*/ + /* After setting */ /* RGIDW_MODID[114]:ARSP41*/ + /* After setting */ /* RGIDW_MODID[115]:ARSP42*/ + [108] = {0xFCB9240CU, 0x00000001U}, /* RGIDW_MODID[116]:ARSP43*/ + [109] = {0xFCB92410U, 0x00000002U}, /* RGIDW_MODID[117]:ARSP44*/ + [110] = {0xFCB92414U, 0x00000001U}, /* RGIDW_MODID[118]:ARSP45*/ + [111] = {0xFCB92418U, 0x00000002U}, /* RGIDW_MODID[119]:ARSP46*/ + [112] = {0xFCB9241CU, 0x00000002U}, /* RGIDW_MODID[120]:ARSP47*/ + [113] = {0xFCB92420U, 0x00000000U}, /* RGIDW_MODID[121]:ARSP48*/ + [114] = {0xFCB92424U, 0x0000004FU}, /* RGIDW_MODID[122]:DMAHSCIF0*/ + [115] = {0xFCB92428U, 0x0000004FU}, /* RGIDW_MODID[123]:DMAHSCIF1*/ + [116] = {0xFCB9242CU, 0x0000004FU}, /* RGIDW_MODID[124]:DMAHSCIF2*/ + [117] = {0xFCB92430U, 0x0000004FU}, /* RGIDW_MODID[125]:DMAHSCIF3*/ + [118] = {0xFCB92434U, 0x0000004FU}, /* RGIDW_MODID[126]:DMASCIF0*/ + [119] = {0xFCB92438U, 0x0000004FU}, /* RGIDW_MODID[127]:DMASCIF1*/ + [120] = {0xFCB9243CU, 0x0000004FU}, /* RGIDW_MODID[128]:DMASCIF3*/ + [121] = {0xFCB92440U, 0x0000004FU}, /* RGIDW_MODID[129]:DMASCIF4*/ + [122] = {0xFCB92444U, 0x0000000AU}, /* RGIDW_MODID[130]:ECMSP4*/ + [123] = {0xFCB92448U, 0x0000004FU}, /* RGIDW_MODID[131]:HSCIF0*/ + [124] = {0xFCB9244CU, 0x0000004FU}, /* RGIDW_MODID[132]:HSCIF1*/ + [125] = {0xFCB92450U, 0x0000004FU}, /* RGIDW_MODID[133]:HSCIF2*/ + [126] = {0xFCB92454U, 0x0000004FU}, /* RGIDW_MODID[134]:HSCIF3*/ + [127] = {0xFCB92458U, 0x0000004FU}, /* RGIDW_MODID[135]:SCIF0*/ + [128] = {0xFCB9245CU, 0x0000004FU}, /* RGIDW_MODID[136]:SCIF1*/ + [129] = {0xFCB92460U, 0x0000004FU}, /* RGIDW_MODID[137]:SCIF3*/ + [130] = {0xFCB92464U, 0x0000004FU}, /* RGIDW_MODID[138]:SCIF4*/ + [131] = {0xFCB92468U, 0x0000006EU}, /* RGIDW_MODID[139]:TMU1*/ + [132] = {0xFCB9246CU, 0x0000006EU}, /* RGIDW_MODID[140]:TMU2*/ + [133] = {0xFCB92470U, 0x0000006EU}, /* RGIDW_MODID[141]:TMU3*/ + [134] = {0xFCB92474U, 0x0000006EU}, /* RGIDW_MODID[142]:TMU4*/ + [135] = {0xFCB92478U, 0x0000004AU}, /* RGIDW_MODID[143]:CANFD*/ + [136] = {0xFCB9247CU, 0x0000004AU}, /* RGIDW_MODID[144]:DMACANFD*/ + [137] = {0xFCB92480U, 0x00000002U}, /* RGIDW_MODID[145]:DMATPU0*/ + [138] = {0xFCB92484U, 0x00000002U}, /* RGIDW_MODID[146]:PWM0*/ + [139] = {0xFCB92488U, 0x00000002U}, /* RGIDW_MODID[147]:PWM1*/ + [140] = {0xFCB9248CU, 0x00000002U}, /* RGIDW_MODID[148]:PWM2*/ + [141] = {0xFCB92490U, 0x00000002U}, /* RGIDW_MODID[149]:PWM3*/ + [142] = {0xFCB92494U, 0x00000002U}, /* RGIDW_MODID[150]:PWM4*/ + [143] = {0xFCB924ACU, 0x00000002U}, /* RGIDW_MODID[151]:TPU0*/ + [144] = {0xFEBD2400U, 0x00000002U}, /* RGIDW_MODID[152]:ARVI40*/ + /* After setting */ /* RGIDW_MODID[153]:ARVI41*/ + /* After setting */ /* RGIDW_MODID[154]:ARVI42*/ + [145] = {0xFEBD240CU, 0x00000001U}, /* RGIDW_MODID[155]:ARVI43*/ + [146] = {0xFEBD2410U, 0x00000002U}, /* RGIDW_MODID[156]:ARVI44*/ + [147] = {0xFEBD2414U, 0x00000001U}, /* RGIDW_MODID[157]:ARVI45*/ + [148] = {0xFEBD2418U, 0x00000002U}, /* RGIDW_MODID[158]:ARVI46*/ + [149] = {0xFEBD241CU, 0x00000002U}, /* RGIDW_MODID[159]:ARVI47*/ + [150] = {0xFEBD2420U, 0x00000000U}, /* RGIDW_MODID[160]:ARVI48*/ + [151] = {0xFEBD2424U, 0x0000000FU}, /* RGIDW_MODID[161]:DIS0*/ + [152] = {0xFEBD2430U, 0x0000000EU}, /* RGIDW_MODID[162]:ECMVIO2*/ + [153] = {0xFEBD2434U, 0x0000000FU}, /* RGIDW_MODID[163]:FCPVD0*/ + [154] = {0xFEBD243CU, 0x0000004EU}, /* RGIDW_MODID[164]:VSPD0*/ + [155] = {0xFCF82400U, 0x0000000AU}, /* RGIDW_MODID[165]:CKMHSC*/ + [156] = {0xFCF82404U, 0x0000000CU}, /* RGIDW_MODID[166]:AXIPCI001*/ + [157] = {0xFCF82408U, 0x0000000CU}, /* RGIDW_MODID[167]:AXIPCI002*/ + [158] = {0xFCF8240CU, 0x0000000CU}, /* RGIDW_MODID[168]:AXIPCI003*/ + [159] = {0xFCF82414U, 0x0000000CU}, /* RGIDW_MODID[169]:AXIPCI005*/ + [160] = {0xFCF82418U, 0x0000000CU}, /* RGIDW_MODID[170]:AXIPCI006*/ + [161] = {0xFCF8241CU, 0x0000000CU}, /* RGIDW_MODID[171]:AXIPCI007*/ + [162] = {0xFCF82420U, 0x0000000CU}, /* RGIDW_MODID[172]:AXIPCI008*/ + [163] = {0xFCF82424U, 0x0000000CU}, /* RGIDW_MODID[173]:AXIPCI009*/ + [164] = {0xFCF82428U, 0x0000000CU}, /* RGIDW_MODID[174]:AXIPCI010*/ + [165] = {0xFCF8242CU, 0x0000000CU}, /* RGIDW_MODID[175]:AXIPCI011*/ + [166] = {0xFCF82430U, 0x0000000CU}, /* RGIDW_MODID[176]:AXIPCI012*/ + [167] = {0xFCF82434U, 0x0000000CU}, /* RGIDW_MODID[177]:AXIPCI013*/ + [168] = {0xFCF82438U, 0x0000000CU}, /* RGIDW_MODID[178]:AXIPCI014*/ + [169] = {0xFCF8243CU, 0x0000000CU}, /* RGIDW_MODID[179]:AXIPCI015*/ + [170] = {0xFCF82484U, 0x0000000EU}, /* RGIDW_MODID[180]:GPTP*/ + [171] = {0xFCF82488U, 0x0000004EU}, /* RGIDW_MODID[181]:IPMMUHC00*/ + [172] = {0xFCF824F4U, 0x0000000CU}, /* RGIDW_MODID[182]:AXIPCI000*/ + [173] = {0xFCF824F8U, 0x0000000CU}, /* RGIDW_MODID[183]:AXIPCI004*/ + [174] = {0xFCF824FCU, 0x0000004EU}, /* RGIDW_MODID[184]:IPMMUHC01*/ + [175] = {0xFCF82500U, 0x0000004EU}, /* RGIDW_MODID[185]:AVB0*/ + [176] = {0xFCF82504U, 0x0000004EU}, /* RGIDW_MODID[186]:AVB1*/ + [177] = {0xFCF82508U, 0x0000004EU}, /* RGIDW_MODID[187]:AVB2*/ + [178] = {0xFCF8250CU, 0x0000004EU}, /* RGIDW_MODID[188]:IPMMUHC10*/ + [179] = {0xFCF82510U, 0x0000004EU}, /* RGIDW_MODID[189]:IPMMUHC11*/ + [180] = {0xFCF82514U, 0x0000004EU}, /* RGIDW_MODID[190]:IPMMUHC12*/ + [181] = {0xFCF82518U, 0x0000004EU}, /* RGIDW_MODID[191]:IPMMUHC13*/ + [182] = {0xFCF8251CU, 0x0000000CU}, /* RGIDW_MODID[192]:PPHY0*/ + [183] = {0xFCF82524U, 0x0000004EU}, /* RGIDW_MODID[193]:IPMMUHC14*/ + [184] = {0xFCF82528U, 0x0000004EU}, /* RGIDW_MODID[194]:IPMMUHC15*/ + [185] = {0xFCF8252CU, 0x0000000EU}, /* RGIDW_MODID[195]:FBAHSC*/ + [186] = {0xFCF82530U, 0x0000004EU}, /* RGIDW_MODID[196]:IPMMUHC02*/ + [187] = {0xFCF82538U, 0x0000000AU}, /* RGIDW_MODID[197]:ECMHSC*/ + [188] = {0xFCF8253CU, 0x00000002U}, /* RGIDW_MODID[198]:ARHC0*/ + /* After setting */ /* RGIDW_MODID[199]:ARHC1*/ + /* After setting */ /* RGIDW_MODID[200]:ARHC2*/ + [189] = {0xFCF82548U, 0x00000001U}, /* RGIDW_MODID[201]:ARHC3*/ + [190] = {0xFCF8254CU, 0x00000002U}, /* RGIDW_MODID[202]:ARHC4*/ + [191] = {0xFCF82550U, 0x00000001U}, /* RGIDW_MODID[203]:ARHC5*/ + [192] = {0xFCF82554U, 0x00000002U}, /* RGIDW_MODID[204]:ARHC6*/ + [193] = {0xFCF82558U, 0x00000002U}, /* RGIDW_MODID[205]:ARHC7*/ + [194] = {0xFCF8255CU, 0x00000000U}, /* RGIDW_MODID[206]:ARHC8*/ + [195] = {0xFCF82560U, 0x0000004EU}, /* RGIDW_MODID[207]:IPMMUHC03*/ + [196] = {0xFCF82564U, 0x0000004EU}, /* RGIDW_MODID[208]:IPMMUHC04*/ + [197] = {0xFCF82568U, 0x0000004EU}, /* RGIDW_MODID[209]:IPMMUHC05*/ + [198] = {0xFCF8256CU, 0x0000004EU}, /* RGIDW_MODID[210]:IPMMUHC06*/ + [199] = {0xFCF82570U, 0x0000004EU}, /* RGIDW_MODID[211]:IPMMUHC07*/ + [200] = {0xFCF82574U, 0x0000004EU}, /* RGIDW_MODID[212]:IPMMUHC08*/ + [201] = {0xFCF82578U, 0x0000004EU}, /* RGIDW_MODID[213]:IPMMUHC09*/ + [202] = {0xFC882400U, 0x00000002U}, /* RGIDW_MODID[214]:ARIMP00*/ + /* After setting */ /* RGIDW_MODID[215]:ARIMP01*/ + /* After setting */ /* RGIDW_MODID[216]:ARIMP02*/ + [203] = {0xFC88240CU, 0x00000001U}, /* RGIDW_MODID[217]:ARIMP03*/ + [204] = {0xFC882410U, 0x00000002U}, /* RGIDW_MODID[218]:ARIMP04*/ + [205] = {0xFC882414U, 0x0000004EU}, /* RGIDW_MODID[219]:AXIFBABUSIR0*/ + [206] = {0xFC882418U, 0x0000004EU}, /* RGIDW_MODID[220]:AXIFBABUSIR1*/ + [207] = {0xFC88241CU, 0x0000004EU}, /* RGIDW_MODID[221]:AXIFBABUSIR2*/ + [208] = {0xFC882420U, 0x0000004EU}, /* RGIDW_MODID[222]:AXIFBABUSIR3*/ + [209] = {0xFC882428U, 0x0000004EU}, /* RGIDW_MODID[223]:AXIIMP0*/ + [210] = {0xFC882434U, 0x00000001U}, /* RGIDW_MODID[224]:ARIMP05*/ + [211] = {0xFC882438U, 0x00000002U}, /* RGIDW_MODID[225]:ARIMP06*/ + [212] = {0xFC88243CU, 0x00000002U}, /* RGIDW_MODID[226]:ARIMP07*/ + [213] = {0xFC882440U, 0x00000000U}, /* RGIDW_MODID[227]:ARIMP08*/ + [214] = {0xFC882448U, 0x0000000AU}, /* RGIDW_MODID[228]:ECMIR*/ + [215] = {0xFC88244CU, 0x0000000FU}, /* RGIDW_MODID[229]:DSPPS*/ + [216] = {0xFC882450U, 0x0000004EU}, /* RGIDW_MODID[230]:IPMMUIR1*/ + [217] = {0xFC882454U, 0x0000004EU}, /* RGIDW_MODID[231]:IPMMUIR0*/ + [218] = {0xFC882458U, 0x0000004EU}, /* RGIDW_MODID[232]:IPMMUIR10*/ + [219] = {0xFC88245CU, 0x0000004EU}, /* RGIDW_MODID[233]:IPMMUIR11*/ + [220] = {0xFC882460U, 0x0000004EU}, /* RGIDW_MODID[234]:IPMMUIR12*/ + [221] = {0xFC882464U, 0x0000004EU}, /* RGIDW_MODID[235]:IPMMUIR13*/ + [222] = {0xFC882468U, 0x0000004EU}, /* RGIDW_MODID[236]:IPMMUIR14*/ + [223] = {0xFC88246CU, 0x0000004EU}, /* RGIDW_MODID[237]:IPMMUIR15*/ + [224] = {0xFC882470U, 0x0000004EU}, /* RGIDW_MODID[238]:IPMMUIR2*/ + [225] = {0xFC882474U, 0x0000004EU}, /* RGIDW_MODID[239]:IPMMUIR3*/ + [226] = {0xFC882478U, 0x0000004EU}, /* RGIDW_MODID[240]:IPMMUIR4*/ + [227] = {0xFC88247CU, 0x0000004EU}, /* RGIDW_MODID[241]:IPMMUIR5*/ + [228] = {0xFC882480U, 0x0000004EU}, /* RGIDW_MODID[242]:IPMMUIR6*/ + [229] = {0xFC882484U, 0x0000004EU}, /* RGIDW_MODID[243]:IPMMUIR7*/ + [230] = {0xFC882488U, 0x0000004EU}, /* RGIDW_MODID[244]:IPMMUIR8*/ + [231] = {0xFC88248CU, 0x0000004EU}, /* RGIDW_MODID[245]:IPMMUIR9*/ + [232] = {0xFC012400U, 0x00000002U}, /* RGIDW_MODID[246]:ARPV0*/ + /* After setting */ /* RGIDW_MODID[247]:ARPV1*/ + [233] = {0xFC012408U, 0x0000002CU}, /* RGIDW_MODID[248]:AXIRGXS*/ + /* After setting */ /* RGIDW_MODID[249]:ARPV2*/ + [234] = {0xFC012410U, 0x00000001U}, /* RGIDW_MODID[250]:ARPV3*/ + [235] = {0xFC012414U, 0x00000002U}, /* RGIDW_MODID[251]:ARPV4*/ + [236] = {0xFC012418U, 0x00000001U}, /* RGIDW_MODID[252]:ARPV5*/ + [237] = {0xFC01241CU, 0x00000002U}, /* RGIDW_MODID[253]:ARPV6*/ + [238] = {0xFC012420U, 0x00000002U}, /* RGIDW_MODID[254]:ARPV7*/ + [239] = {0xFC012424U, 0x00000000U}, /* RGIDW_MODID[255]:ARPV8*/ + [240] = {0xFC01242CU, 0x0000000AU}, /* RGIDW_MODID[256]:ECM3DG*/ + [241] = {0xFC012430U, 0x0000000EU}, /* RGIDW_MODID[257]:FBAPVC*/ + [242] = {0xFC012434U, 0x0000000EU}, /* RGIDW_MODID[258]:FBAPVD0*/ + [243] = {0xFC012438U, 0x0000000EU}, /* RGIDW_MODID[259]:FBAPVD1*/ + [244] = {0xFC01243CU, 0x0000000EU}, /* RGIDW_MODID[260]:FBAPVD2*/ + [245] = {0xFC012440U, 0x0000000EU}, /* RGIDW_MODID[261]:FBAPVE*/ + [246] = {0xFC012444U, 0x0000004EU}, /* RGIDW_MODID[262]:IPMMUPV000*/ + [247] = {0xFC012448U, 0x0000004EU}, /* RGIDW_MODID[263]:IPMMUPV001*/ + [248] = {0xFC01244CU, 0x0000004EU}, /* RGIDW_MODID[264]:IPMMUPV010*/ + [249] = {0xFC012450U, 0x0000004EU}, /* RGIDW_MODID[265]:IPMMUPV011*/ + [250] = {0xFC012454U, 0x0000004EU}, /* RGIDW_MODID[266]:IPMMUPV012*/ + [251] = {0xFC012458U, 0x0000004EU}, /* RGIDW_MODID[267]:IPMMUPV013*/ + [252] = {0xFC01245CU, 0x0000004EU}, /* RGIDW_MODID[268]:IPMMUPV014*/ + [253] = {0xFC012460U, 0x0000004EU}, /* RGIDW_MODID[269]:IPMMUPV015*/ + [254] = {0xFC012464U, 0x0000004EU}, /* RGIDW_MODID[270]:IPMMUPV002*/ + [255] = {0xFC012468U, 0x0000004EU}, /* RGIDW_MODID[271]:IPMMUPV003*/ + [256] = {0xFC01246CU, 0x0000004EU}, /* RGIDW_MODID[272]:IPMMUPV004*/ + [257] = {0xFC012470U, 0x0000004EU}, /* RGIDW_MODID[273]:IPMMUPV005*/ + [258] = {0xFC012474U, 0x0000004EU}, /* RGIDW_MODID[274]:IPMMUPV006*/ + [259] = {0xFC012478U, 0x0000004EU}, /* RGIDW_MODID[275]:IPMMUPV007*/ + [260] = {0xFC01247CU, 0x0000004EU}, /* RGIDW_MODID[276]:IPMMUPV008*/ + [261] = {0xFC012480U, 0x0000004EU}, /* RGIDW_MODID[277]:IPMMUPV009*/ + [262] = {0xFDC22400U, 0x00000002U}, /* RGIDW_MODID[278]:ARRC0*/ + /* After setting */ /* RGIDW_MODID[279]:ARRC1*/ + /* After setting */ /* RGIDW_MODID[280]:ARRC2*/ + [263] = {0xFDC2240CU, 0x00000001U}, /* RGIDW_MODID[281]:ARRC3*/ + [264] = {0xFDC22410U, 0x00000002U}, /* RGIDW_MODID[282]:ARRC4*/ + [265] = {0xFDC22414U, 0x00000001U}, /* RGIDW_MODID[283]:ARRC5*/ + [266] = {0xFDC22418U, 0x00000002U}, /* RGIDW_MODID[284]:ARRC6*/ + [267] = {0xFDC2241CU, 0x00000002U}, /* RGIDW_MODID[285]:ARRC7*/ + [268] = {0xFDC22420U, 0x00000000U}, /* RGIDW_MODID[286]:ARRC8*/ + [269] = {0xFDC22428U, 0x0000004FU}, /* RGIDW_MODID[287]:ICUMX*/ + [270] = {0xFDC2242CU, 0x0000000AU}, /* RGIDW_MODID[288]:ECMRC*/ + [271] = {0xFD432400U, 0x0000004EU}, /* RGIDW_MODID[289]:DMAWCRC0*/ + [272] = {0xFD432404U, 0x0000004EU}, /* RGIDW_MODID[290]:DMAWCRC1*/ + [273] = {0xFD432408U, 0x0000004EU}, /* RGIDW_MODID[291]:DMAWCRC2*/ + [274] = {0xFD43240CU, 0x0000004EU}, /* RGIDW_MODID[292]:DMAWCRC3*/ + [275] = {0xFD442400U, 0x0000000FU}, /* RGIDW_MODID[293]:ARMREG00*/ + [276] = {0xFD442404U, 0x0000000CU}, /* RGIDW_MODID[294]:ARMREG01*/ + [277] = {0xFD442408U, 0x00000000U}, /* RGIDW_MODID[295]:ARMREG10*/ + [278] = {0xFD44240CU, 0x00000000U}, /* RGIDW_MODID[296]:ARMREG11*/ + [279] = {0xFD442410U, 0x0000000AU}, /* RGIDW_MODID[297]:ARMREG12*/ + [280] = {0xFD442414U, 0x0000000FU}, /* RGIDW_MODID[298]:ARMREG13*/ + [281] = {0xFD442418U, 0x0000000AU}, /* RGIDW_MODID[299]:ARMREG14*/ + [282] = {0xFD44241CU, 0x00000003U}, /* RGIDW_MODID[300]:AXICR52SS0*/ + [283] = {0xFD442420U, 0x0000000EU}, /* RGIDW_MODID[301]:AXICSD0*/ + [284] = {0xFD442424U, 0x0000000EU}, /* RGIDW_MODID[302]:AXIINTAP0*/ + [285] = {0xFD442430U, 0x0000000FU}, /* RGIDW_MODID[303]:AXISYSRAM0*/ + [286] = {0xFD442434U, 0x0000004FU}, /* RGIDW_MODID[304]:AXISYSRAM1*/ + [287] = {0xFD442438U, 0x00000000U}, /* RGIDW_MODID[305]:ARGREG15*/ + [288] = {0xFD44243CU, 0x00000000U}, /* RGIDW_MODID[306]:ARMREG2*/ + [289] = {0xFD442440U, 0x00000000U}, /* RGIDW_MODID[307]:ARMREG3*/ + [290] = {0xFD442444U, 0x00000000U}, /* RGIDW_MODID[308]:ARMREG4*/ + [291] = {0xFD442448U, 0x0000000FU}, /* RGIDW_MODID[309]:ARMREG5*/ + [292] = {0xFD44244CU, 0x0000000AU}, /* RGIDW_MODID[310]:ARMREG6*/ + [293] = {0xFD442450U, 0x00000000U}, /* RGIDW_MODID[311]:ARMREG7*/ + [294] = {0xFD442454U, 0x0000000CU}, /* RGIDW_MODID[312]:ARMREG8*/ + [295] = {0xFD442458U, 0x0000000CU}, /* RGIDW_MODID[313]:ARMREG9*/ + [296] = {0xFD44245CU, 0x00000002U}, /* RGIDW_MODID[314]:ARRD0*/ + /* After setting */ /* RGIDW_MODID[315]:ARRD1*/ + /* After setting */ /* RGIDW_MODID[316]:ARRD2*/ + [297] = {0xFD442468U, 0x00000001U}, /* RGIDW_MODID[317]:ARRD3*/ + [298] = {0xFD44246CU, 0x00000002U}, /* RGIDW_MODID[318]:ARRD4*/ + [299] = {0xFD442470U, 0x00000001U}, /* RGIDW_MODID[319]:ARRD5*/ + [300] = {0xFD442474U, 0x00000002U}, /* RGIDW_MODID[320]:ARRD6*/ + [301] = {0xFD442478U, 0x00000002U}, /* RGIDW_MODID[321]:ARRD7*/ + [302] = {0xFD44247CU, 0x00000000U}, /* RGIDW_MODID[322]:ARRD8*/ + [303] = {0xFD442480U, 0x00000002U}, /* RGIDW_MODID[323]:ARRT0*/ + /* After setting */ /* RGIDW_MODID[324]:ARRT1*/ + /* After setting */ /* RGIDW_MODID[325]:ARRT2*/ + [304] = {0xFD44248CU, 0x00000001U}, /* RGIDW_MODID[326]:ARRT3*/ + [305] = {0xFD442490U, 0x00000002U}, /* RGIDW_MODID[327]:ARRT4*/ + [306] = {0xFD442494U, 0x00000001U}, /* RGIDW_MODID[328]:ARRT5*/ + [307] = {0xFD442498U, 0x00000002U}, /* RGIDW_MODID[329]:ARRT6*/ + [308] = {0xFD44249CU, 0x00000002U}, /* RGIDW_MODID[330]:ARRT7*/ + [309] = {0xFD4424A0U, 0x00000000U}, /* RGIDW_MODID[331]:ARRT8*/ + [310] = {0xFD4424A4U, 0x0000000AU}, /* RGIDW_MODID[332]:CKMRT*/ + [311] = {0xFD4424A8U, 0x0000004EU}, /* RGIDW_MODID[333]:CRC0*/ + [312] = {0xFD4424ACU, 0x0000004EU}, /* RGIDW_MODID[334]:CRC1*/ + [313] = {0xFD4424B0U, 0x0000004EU}, /* RGIDW_MODID[335]:CRC2*/ + [314] = {0xFD4424B4U, 0x0000004EU}, /* RGIDW_MODID[336]:CRC3*/ + [315] = {0xFD4424B8U, 0x0000000EU}, /* RGIDW_MODID[337]:CSD*/ + [316] = {0xFD4424BCU, 0x0000000EU}, /* RGIDW_MODID[338]:ECM*/ + [317] = {0xFD4424C0U, 0x0000000AU}, /* RGIDW_MODID[339]:ECMRT*/ + [318] = {0xFD4424C4U, 0x0000000EU}, /* RGIDW_MODID[340]:FBACR52*/ + [319] = {0xFD4424C8U, 0x0000000EU}, /* RGIDW_MODID[341]:FBART*/ + [320] = {0xFD4424CCU, 0x0000000EU}, /* RGIDW_MODID[342]:INTTP*/ + [321] = {0xFD4424D0U, 0x0000004EU}, /* RGIDW_MODID[343]:IPMMURT000*/ + [322] = {0xFD4424D4U, 0x0000004EU}, /* RGIDW_MODID[344]:IPMMURT100*/ + [323] = {0xFD4424D8U, 0x0000004EU}, /* RGIDW_MODID[345]:KCRC4*/ + [324] = {0xFD4424DCU, 0x0000004EU}, /* RGIDW_MODID[346]:KCRC5*/ + [325] = {0xFD4424E0U, 0x0000004EU}, /* RGIDW_MODID[347]:KCRC6*/ + [326] = {0xFD4424E4U, 0x0000004EU}, /* RGIDW_MODID[348]:KCRC7*/ + [327] = {0xFD4424E8U, 0x0000004FU}, /* RGIDW_MODID[349]:MFI00*/ + [328] = {0xFD4424ECU, 0x0000004EU}, /* RGIDW_MODID[350]:MFI01*/ + [329] = {0xFD4424F0U, 0x0000004EU}, /* RGIDW_MODID[351]:MFI10*/ + [330] = {0xFD4424F4U, 0x0000004EU}, /* RGIDW_MODID[352]:MFI02*/ + [331] = {0xFD4424F8U, 0x0000004EU}, /* RGIDW_MODID[353]:MFI03*/ + [332] = {0xFD4424FCU, 0x0000004EU}, /* RGIDW_MODID[354]:MFI04*/ + [333] = {0xFD442500U, 0x00000000U}, /* RGIDW_MODID[355]:MFI05*/ + [334] = {0xFD442504U, 0x00000000U}, /* RGIDW_MODID[356]:MFI06*/ + [335] = {0xFD442508U, 0x00000000U}, /* RGIDW_MODID[357]:MFI07*/ + [336] = {0xFD44250CU, 0x00000000U}, /* RGIDW_MODID[358]:MFI08*/ + [337] = {0xFD442510U, 0x0000004EU}, /* RGIDW_MODID[359]:MFI09*/ + [338] = {0xFD442514U, 0x0000004FU}, /* RGIDW_MODID[360]:MFI15*/ + [339] = {0xFD442518U, 0x0000000AU}, /* RGIDW_MODID[361]:CKMCR52*/ + [340] = {0xFD44251CU, 0x0000004BU}, /* RGIDW_MODID[362]:RTDM0P*/ + [341] = {0xFD442520U, 0x0000000AU}, /* RGIDW_MODID[363]:ECMRD*/ + [342] = {0xFD442524U, 0x0000004BU}, /* RGIDW_MODID[364]:RTDM1P*/ + [343] = {0xFD442530U, 0x0000000BU}, /* RGIDW_MODID[365]:SYSRAM10*/ + [344] = {0xFD442538U, 0x00000001U}, /* RGIDW_MODID[366]:SYSRAM00*/ + [345] = {0xFD44253CU, 0x0000004EU}, /* RGIDW_MODID[367]:TSIPL0*/ + [346] = {0xFD442540U, 0x0000004EU}, /* RGIDW_MODID[368]:TSIPL1*/ + [347] = {0xFD442544U, 0x0000004EU}, /* RGIDW_MODID[369]:TSIPL2*/ + [348] = {0xFD442548U, 0x0000004EU}, /* RGIDW_MODID[370]:TSIPL3*/ + [349] = {0xFD44254CU, 0x0000004EU}, /* RGIDW_MODID[371]:TSIPL4*/ + [350] = {0xFD442550U, 0x0000004EU}, /* RGIDW_MODID[372]:TSIPL5*/ + [351] = {0xFD442554U, 0x0000004EU}, /* RGIDW_MODID[373]:TSIPL6*/ + [352] = {0xFD442558U, 0x0000004EU}, /* RGIDW_MODID[374]:TSIPL7*/ + [353] = {0xFD44255CU, 0x0000004EU}, /* RGIDW_MODID[375]:WCRC0*/ + [354] = {0xFD442560U, 0x0000004EU}, /* RGIDW_MODID[376]:WCRC1*/ + [355] = {0xFD442564U, 0x0000004EU}, /* RGIDW_MODID[377]:WCRC2*/ + [356] = {0xFD442568U, 0x0000004EU}, /* RGIDW_MODID[378]:WCRC3*/ + [357] = {0xFD442580U, 0x0000004EU}, /* RGIDW_MODID[379]:MFI11*/ + [358] = {0xFD442584U, 0x00000000U}, /* RGIDW_MODID[380]:MFI12*/ + [359] = {0xFD442588U, 0x00000000U}, /* RGIDW_MODID[381]:MFI13*/ + [360] = {0xFD44258CU, 0x00000000U}, /* RGIDW_MODID[382]:MFI14*/ + [361] = {0xFD442590U, 0x0000004EU}, /* RGIDW_MODID[383]:IPMMURT001*/ + [362] = {0xFD442594U, 0x0000004EU}, /* RGIDW_MODID[384]:IPMMURT010*/ + [363] = {0xFD442598U, 0x0000004EU}, /* RGIDW_MODID[385]:IPMMURT011*/ + [364] = {0xFD44259CU, 0x0000004EU}, /* RGIDW_MODID[386]:IPMMURT012*/ + [365] = {0xFD4425A0U, 0x0000004EU}, /* RGIDW_MODID[387]:IPMMURT013*/ + [366] = {0xFD4425A4U, 0x0000004EU}, /* RGIDW_MODID[388]:IPMMURT014*/ + [367] = {0xFD4425A8U, 0x0000004EU}, /* RGIDW_MODID[389]:IPMMURT015*/ + [368] = {0xFD4425ACU, 0x0000004EU}, /* RGIDW_MODID[390]:IPMMURT002*/ + [369] = {0xFD4425B0U, 0x0000004EU}, /* RGIDW_MODID[391]:IPMMURT003*/ + [370] = {0xFD4425B4U, 0x0000004EU}, /* RGIDW_MODID[392]:IPMMURT004*/ + [371] = {0xFD4425B8U, 0x0000004EU}, /* RGIDW_MODID[393]:IPMMURT005*/ + [372] = {0xFD4425BCU, 0x0000004EU}, /* RGIDW_MODID[394]:IPMMURT006*/ + [373] = {0xFD4425C0U, 0x0000004EU}, /* RGIDW_MODID[395]:IPMMURT007*/ + [374] = {0xFD4425C4U, 0x0000004EU}, /* RGIDW_MODID[396]:IPMMURT008*/ + [375] = {0xFD4425C8U, 0x0000004EU}, /* RGIDW_MODID[397]:IPMMURT009*/ + [376] = {0xFD4425CCU, 0x0000004EU}, /* RGIDW_MODID[398]:IPKMURT101*/ + [377] = {0xFD4425D0U, 0x0000004EU}, /* RGIDW_MODID[399]:IPMMURT110*/ + [378] = {0xFD4425D4U, 0x0000004EU}, /* RGIDW_MODID[400]:IPMMURT111*/ + [379] = {0xFD4425D8U, 0x0000004EU}, /* RGIDW_MODID[401]:IPMMURT112*/ + [380] = {0xFD4425DCU, 0x0000004EU}, /* RGIDW_MODID[402]:IPMMURT113*/ + [381] = {0xFD4425E0U, 0x0000004EU}, /* RGIDW_MODID[403]:IPMMURT114*/ + [382] = {0xFD4425E4U, 0x0000004EU}, /* RGIDW_MODID[404]:IPMMURT115*/ + [383] = {0xFD4425E8U, 0x0000004EU}, /* RGIDW_MODID[405]:IPMMURT102*/ + [384] = {0xFD4425ECU, 0x0000004EU}, /* RGIDW_MODID[406]:IPMMURT103*/ + [385] = {0xFD4425F0U, 0x0000004EU}, /* RGIDW_MODID[407]:IPMMURT104*/ + [386] = {0xFD4425F4U, 0x0000004EU}, /* RGIDW_MODID[408]:IPMMURT105*/ + [387] = {0xFD4425F8U, 0x0000004EU}, /* RGIDW_MODID[409]:IPMMURT106*/ + [388] = {0xFD4425FCU, 0x0000004EU}, /* RGIDW_MODID[410]:IPMMURT107*/ + [389] = {0xFD442600U, 0x0000004BU}, /* RGIDW_MODID[411]:RTDM000*/ + [390] = {0xFD442604U, 0x0000004BU}, /* RGIDW_MODID[412]:RTDM001*/ + [391] = {0xFD442608U, 0x0000004BU}, /* RGIDW_MODID[413]:RTDM010*/ + [392] = {0xFD44260CU, 0x0000004BU}, /* RGIDW_MODID[414]:RTDM011*/ + [393] = {0xFD442610U, 0x0000004BU}, /* RGIDW_MODID[415]:RTDM012*/ + [394] = {0xFD442614U, 0x0000004BU}, /* RGIDW_MODID[416]:RTDM013*/ + [395] = {0xFD442618U, 0x0000004BU}, /* RGIDW_MODID[417]:RTDM014*/ + [396] = {0xFD44261CU, 0x0000004BU}, /* RGIDW_MODID[418]:RTDM015*/ + [397] = {0xFD442620U, 0x0000004BU}, /* RGIDW_MODID[419]:RTDM002*/ + [398] = {0xFD442624U, 0x0000004BU}, /* RGIDW_MODID[420]:RTDM003*/ + [399] = {0xFD442628U, 0x0000004BU}, /* RGIDW_MODID[421]:RTDM004*/ + [400] = {0xFD44262CU, 0x0000004BU}, /* RGIDW_MODID[422]:RTDM005*/ + [401] = {0xFD442630U, 0x0000004BU}, /* RGIDW_MODID[423]:RTDM006*/ + [402] = {0xFD442634U, 0x0000004BU}, /* RGIDW_MODID[424]:RTDM007*/ + [403] = {0xFD442638U, 0x0000004BU}, /* RGIDW_MODID[425]:RTDM008*/ + [404] = {0xFD44263CU, 0x0000004BU}, /* RGIDW_MODID[426]:RTDM009*/ + [405] = {0xFD442640U, 0x0000004BU}, /* RGIDW_MODID[427]:RTDM100*/ + [406] = {0xFD442644U, 0x0000004BU}, /* RGIDW_MODID[428]:RTDM101*/ + [407] = {0xFD442648U, 0x0000004BU}, /* RGIDW_MODID[429]:RTDM110*/ + [408] = {0xFD44264CU, 0x0000004BU}, /* RGIDW_MODID[430]:RTDM111*/ + [409] = {0xFD442650U, 0x0000004BU}, /* RGIDW_MODID[431]:RTDM112*/ + [410] = {0xFD442654U, 0x0000004BU}, /* RGIDW_MODID[432]:RTDM113*/ + [411] = {0xFD442658U, 0x0000004BU}, /* RGIDW_MODID[433]:RTDM114*/ + [412] = {0xFD44265CU, 0x0000004BU}, /* RGIDW_MODID[434]:RTDM115*/ + [413] = {0xFD442660U, 0x0000004BU}, /* RGIDW_MODID[435]:RTDM102*/ + [414] = {0xFD442664U, 0x0000004BU}, /* RGIDW_MODID[436]:RTDM103*/ + [415] = {0xFD442668U, 0x0000004BU}, /* RGIDW_MODID[437]:RTDM104*/ + [416] = {0xFD44266CU, 0x0000004BU}, /* RGIDW_MODID[438]:RTDM105*/ + [417] = {0xFD442670U, 0x0000004BU}, /* RGIDW_MODID[439]:RTDM106*/ + [418] = {0xFD442674U, 0x0000004BU}, /* RGIDW_MODID[440]:RTDM107*/ + [419] = {0xFD442678U, 0x0000004BU}, /* RGIDW_MODID[441]:RTDM108*/ + [420] = {0xFD44267CU, 0x0000004BU}, /* RGIDW_MODID[442]:RTDM109*/ + [421] = {0xFD442700U, 0x0000004EU}, /* RGIDW_MODID[443]:IPMMURT108*/ + [422] = {0xFD442704U, 0x0000004EU}, /* RGIDW_MODID[444]:IPMMURT109*/ + [423] = {0xFD442708U, 0x00000001U}, /* RGIDW_MODID[445]:SYSRAM01*/ + [424] = {0xFD44270CU, 0x0000000BU}, /* RGIDW_MODID[446]:SYSRAM02*/ + [425] = {0xFD442710U, 0x00000001U}, /* RGIDW_MODID[447]:SYSRAM03*/ + [426] = {0xFD442714U, 0x00000001U}, /* RGIDW_MODID[448]:SYSRAM04*/ + [427] = {0xFD442718U, 0x00000001U}, /* RGIDW_MODID[449]:SYSRAM05*/ + [428] = {0xFD44271CU, 0x00000001U}, /* RGIDW_MODID[450]:SYSRAM06*/ + [429] = {0xFD442720U, 0x00000000U}, /* RGIDW_MODID[451]:SYSRAM07*/ + [430] = {0xFD442724U, 0x0000000BU}, /* RGIDW_MODID[452]:SYSRAM11*/ + [431] = {0xFD442728U, 0x0000000AU}, /* RGIDW_MODID[453]:SYSRAM12*/ + [432] = {0xFD44272CU, 0x0000000BU}, /* RGIDW_MODID[454]:SYSRAM13*/ + [433] = {0xFD442730U, 0x0000000BU}, /* RGIDW_MODID[455]:SYSRAM14*/ + [434] = {0xFD442734U, 0x0000000BU}, /* RGIDW_MODID[456]:SYSRAM15*/ + [435] = {0xFD442738U, 0x0000000BU}, /* RGIDW_MODID[457]:SYSRAM16*/ + [436] = {0xFD44273CU, 0x00000000U}, /* RGIDW_MODID[458]:SYSRAM17*/ + [437] = {0xFD442760U, 0x00000002U}, /* RGIDW_MODID[459]:BKBUF*/ + [438] = {0xFD442764U, 0x00000003U}, /* RGIDW_MODID[460]:AXICR52SS1*/ + [439] = {0xFD442768U, 0x00000003U}, /* RGIDW_MODID[461]:AXICR52SS2*/ + [440] = {0xFC862400U, 0x00000002U}, /* RGIDW_MODID[462]:ARSC0*/ + /* After setting */ /* RGIDW_MODID[463]:ARSC1*/ + /* After setting */ /* RGIDW_MODID[464]:ARSC2*/ + [441] = {0xFC86240CU, 0x00000001U}, /* RGIDW_MODID[465]:ARSC3*/ + [442] = {0xFC862410U, 0x00000002U}, /* RGIDW_MODID[466]:ARSC4*/ + [443] = {0xFC862414U, 0x00000001U}, /* RGIDW_MODID[467]:ARSC5*/ + [444] = {0xFC862418U, 0x00000002U}, /* RGIDW_MODID[468]:ARSC6*/ + [445] = {0xFC86241CU, 0x00000002U}, /* RGIDW_MODID[469]:ARSC7*/ + [446] = {0xFC862420U, 0x00000000U}, /* RGIDW_MODID[470]:ARSC8*/ + [447] = {0xFC862424U, 0x00000002U}, /* RGIDW_MODID[471]:ARSTM0*/ + /* After setting */ /* RGIDW_MODID[472]:ARSTM1*/ + [448] = {0xFC86242CU, 0x0000000EU}, /* RGIDW_MODID[473]:CSD1S*/ + [449] = {0xFC862430U, 0x0000000EU}, /* RGIDW_MODID[474]:AXIFBABUSTOP0*/ + /* After setting */ /* RGIDW_MODID[475]:ARSTM2*/ + [450] = {0xFC86243CU, 0x00000001U}, /* RGIDW_MODID[476]:ARSTM3*/ + [451] = {0xFC862440U, 0x00000002U}, /* RGIDW_MODID[477]:ARSTM4*/ + [452] = {0xFC862444U, 0x00000001U}, /* RGIDW_MODID[478]:ARSTM5*/ + [453] = {0xFC862448U, 0x00000002U}, /* RGIDW_MODID[479]:ARSTM6*/ + [454] = {0xFC86244CU, 0x00000002U}, /* RGIDW_MODID[480]:ARSTM7*/ + [455] = {0xFC862450U, 0x00000000U}, /* RGIDW_MODID[481]:ARSTM8*/ + [456] = {0xFC862454U, 0x0000000AU}, /* RGIDW_MODID[482]:ECMTOP*/ + [457] = {0xFC862458U, 0x0000000EU}, /* RGIDW_MODID[483]:FBA*/ + [458] = {0xFC86245CU, 0x0000000EU}, /* RGIDW_MODID[484]:FBC*/ + [459] = {0xFC862434U, 0x0000000CU}, /* RGIDW_MODID[485]:AXICCI00*/ + [460] = {0xFC862460U, 0x0000000EU}, /* RGIDW_MODID[486]:AXICCI01*/ + [461] = {0xFC862464U, 0x0000000CU}, /* RGIDW_MODID[487]:AXICCI10*/ + [462] = {0xFC862468U, 0x0000000CU}, /* RGIDW_MODID[488]:AXICCI11*/ + [463] = {0xFC86246CU, 0x0000000CU}, /* RGIDW_MODID[489]:AXICCI12*/ + [464] = {0xFC862470U, 0x0000000CU}, /* RGIDW_MODID[490]:AXICCI13*/ + [465] = {0xFC862474U, 0x0000000CU}, /* RGIDW_MODID[491]:AXICCI14*/ + [466] = {0xFC862478U, 0x0000000CU}, /* RGIDW_MODID[492]:AXICCI15*/ + [467] = {0xFC86247CU, 0x0000000EU}, /* RGIDW_MODID[493]:AXICCI2*/ + [468] = {0xFC862480U, 0x0000000CU}, /* RGIDW_MODID[494]:AXICCI3*/ + [469] = {0xFC862484U, 0x0000000CU}, /* RGIDW_MODID[495]:AXICCI4*/ + [470] = {0xFC862488U, 0x0000000CU}, /* RGIDW_MODID[496]:AXICCI5*/ + [471] = {0xFC86248CU, 0x0000000CU}, /* RGIDW_MODID[497]:AXICCI6*/ + [472] = {0xFC862490U, 0x0000000CU}, /* RGIDW_MODID[498]:AXICCI7*/ + [473] = {0xFC862494U, 0x0000000CU}, /* RGIDW_MODID[499]:AXICCI8*/ + [474] = {0xFC862498U, 0x00000009U}, /* RGIDW_MODID[500]:AXICCI9*/ + [475] = {0xFC8624A0U, 0x0000000AU}, /* RGIDW_MODID[501]:ECMSTM*/ + [476] = {0xFCB82400U, 0x0000002CU}, /* RGIDW_MODID[502]:DMASSI00*/ + [477] = {0xFCB82404U, 0x0000002CU}, /* RGIDW_MODID[503]:DMASSI01*/ + [478] = {0xFCB82408U, 0x0000002CU}, /* RGIDW_MODID[504]:DMASSI02*/ + [479] = {0xFCB8240CU, 0x0000002CU}, /* RGIDW_MODID[505]:DMASSI03*/ + [480] = {0xFCB82410U, 0x0000002CU}, /* RGIDW_MODID[506]:DMASSI04*/ + [481] = {0xFCB82414U, 0x0000004EU}, /* RGIDW_MODID[507]:DMAI2C0*/ + [482] = {0xFCB82418U, 0x0000004EU}, /* RGIDW_MODID[508]:DMAI2C1*/ + [483] = {0xFCB8241CU, 0x0000004EU}, /* RGIDW_MODID[509]:DMAI2C2*/ + [484] = {0xFCB82420U, 0x0000004EU}, /* RGIDW_MODID[510]:DMAI2C3*/ + [485] = {0xFCB8242CU, 0x0000002CU}, /* RGIDW_MODID[511]:DMASSI05*/ + [486] = {0xFCB82430U, 0x0000002CU}, /* RGIDW_MODID[512]:DMASSI06*/ + [487] = {0xFCB82434U, 0x0000002CU}, /* RGIDW_MODID[513]:DMASSI07*/ + [488] = {0xFDDC2400U, 0x00000002U}, /* RGIDW_MODID[514]:ARMM*/ + /* After setting */ /* RGIDW_MODID[515]:AXIARNMM*/ + [489] = {0xFDDC2408U, 0x00000002U}, /* RGIDW_MODID[516]:ARSM0*/ + /* After setting */ /* RGIDW_MODID[517]:ARSM1*/ + /* After setting */ /* RGIDW_MODID[518]:ARSM2*/ + [490] = {0xFDDC2414U, 0x0000000FU}, /* RGIDW_MODID[519]:AXIQOS0*/ + [491] = {0xFDDC2418U, 0x0000000FU}, /* RGIDW_MODID[520]:AXIQOS1*/ + [492] = {0xFDDC241CU, 0x0000000FU}, /* RGIDW_MODID[521]:AXIQOS2*/ + [493] = {0xFDDC2420U, 0x0000000FU}, /* RGIDW_MODID[522]:AXIQOS3*/ + [494] = {0xFDDC2424U, 0x0000000FU}, /* RGIDW_MODID[523]:AXIQOS4*/ + [495] = {0xFDDC2428U, 0x0000000FU}, /* RGIDW_MODID[524]:AXIQOS5*/ + [496] = {0xFDDC2434U, 0x00000001U}, /* RGIDW_MODID[525]:ARSM3*/ + [497] = {0xFDDC2438U, 0x00000002U}, /* RGIDW_MODID[526]:ARSM4*/ + [498] = {0xFDDC243CU, 0x00000001U}, /* RGIDW_MODID[527]:ARSM5*/ + [499] = {0xFDDC2440U, 0x00000002U}, /* RGIDW_MODID[528]:ARSM6*/ + [500] = {0xFDDC2444U, 0x00000002U}, /* RGIDW_MODID[529]:ARSM7*/ + [501] = {0xFDDC2448U, 0x00000000U}, /* RGIDW_MODID[530]:ARSM8*/ + [502] = {0xFDDC244CU, 0x0000000BU}, /* RGIDW_MODID[531]:AXMM0*/ + [503] = {0xFDDC2450U, 0x0000000BU}, /* RGIDW_MODID[532]:AXMM1*/ + [504] = {0xFDDC2454U, 0x00000000U}, /* RGIDW_MODID[533]:AXMMPMON*/ + [505] = {0xFDDC2458U, 0x0000000AU}, /* RGIDW_MODID[534]:CKMMM*/ + [506] = {0xFDDC245CU, 0x0000000AU}, /* RGIDW_MODID[535]:ECMMM*/ + [507] = {0xFDDC2460U, 0x0000000EU}, /* RGIDW_MODID[536]:FBADBSC0*/ + [508] = {0xFDDC2468U, 0x0000000EU}, /* RGIDW_MODID[537]:FBAMM*/ + [509] = {0xFDDC246CU, 0x0000004EU}, /* RGIDW_MODID[538]:IPMMUMM00*/ + [510] = {0xFDDC2470U, 0x0000000FU}, /* RGIDW_MODID[539]:DBS0A0*/ + [511] = {0xFDDC2474U, 0x0000000AU}, /* RGIDW_MODID[540]:DBS0A1*/ + [512] = {0xFDDC2484U, 0x00000009U}, /* RGIDW_MODID[541]:FCPRC*/ + [513] = {0xFDDC2488U, 0x0000000FU}, /* RGIDW_MODID[542]:DBS0D0*/ + [514] = {0xFDDC248CU, 0x0000000AU}, /* RGIDW_MODID[543]:DBS0D1*/ + [515] = {0xFDDC2498U, 0x0000000EU}, /* RGIDW_MODID[544]:FBADDR*/ + [516] = {0xFDDC249CU, 0x0000004EU}, /* RGIDW_MODID[545]:IPMMUMM01*/ + [517] = {0xFDDC24A0U, 0x0000004EU}, /* RGIDW_MODID[546]:IPMMUMM10*/ + [518] = {0xFDDC24A4U, 0x0000004EU}, /* RGIDW_MODID[547]:IPMMUMM11*/ + [519] = {0xFDDC24A8U, 0x0000004EU}, /* RGIDW_MODID[548]:IPMMUMM12*/ + [520] = {0xFDDC24ACU, 0x0000004EU}, /* RGIDW_MODID[549]:IPMMUMM13*/ + [521] = {0xFDDC24B0U, 0x0000004EU}, /* RGIDW_MODID[550]:IPMMUMM14*/ + [522] = {0xFDDC24B4U, 0x0000004EU}, /* RGIDW_MODID[551]:IPMMUMM15*/ + [523] = {0xFDDC24B8U, 0x0000004EU}, /* RGIDW_MODID[552]:IPMMUMM02*/ + [524] = {0xFDDC24BCU, 0x0000004EU}, /* RGIDW_MODID[553]:IPMMUMM03*/ + [525] = {0xFDDC24C0U, 0x0000004EU}, /* RGIDW_MODID[554]:IPMMUMM04*/ + [526] = {0xFDDC24C4U, 0x0000004EU}, /* RGIDW_MODID[555]:IPMMUMM05*/ + [527] = {0xFDDC24C8U, 0x0000004EU}, /* RGIDW_MODID[556]:IPMMUMM06*/ + [528] = {0xFDDC24CCU, 0x0000004EU}, /* RGIDW_MODID[557]:IPMMUMM07*/ + [529] = {0xFDDC24D0U, 0x0000004EU}, /* RGIDW_MODID[558]:IPMMUMM08*/ + [530] = {0xFDDC24D4U, 0x0000004EU}, /* RGIDW_MODID[559]:IPMMUMM09*/ + [531] = {0xFC802400U, 0x00000002U}, /* RGIDW_MODID[560]:ARSN0*/ + /* After setting */ /* RGIDW_MODID[561]:ARSN1*/ + /* After setting */ /* RGIDW_MODID[562]:ARSN2*/ + [532] = {0xFC80240CU, 0x00000001U}, /* RGIDW_MODID[563]:ARSN3*/ + [533] = {0xFC802410U, 0x00000002U}, /* RGIDW_MODID[564]:ARSN4*/ + [534] = {0xFC802414U, 0x00000001U}, /* RGIDW_MODID[565]:ARSN5*/ + [535] = {0xFC802418U, 0x00000002U}, /* RGIDW_MODID[566]:ARSN6*/ + [536] = {0xFC80241CU, 0x00000002U}, /* RGIDW_MODID[567]:ARSN7*/ + [537] = {0xFC802420U, 0x00000000U}, /* RGIDW_MODID[568]:ARSN8*/ + [538] = {0xFC802424U, 0x0000000AU}, /* RGIDW_MODID[569]:ECMTOP3*/ + [539] = {0xFCB52400U, 0x00000002U}, /* RGIDW_MODID[570]:ARSD00*/ + /* After setting */ /* RGIDW_MODID[571]:ARSD01*/ + /* After setting */ /* RGIDW_MODID[572]:ARSD02*/ + [540] = {0xFCB5240CU, 0x00000001U}, /* RGIDW_MODID[573]:ARSD03*/ + [541] = {0xFCB52410U, 0x00000002U}, /* RGIDW_MODID[574]:ARSD04*/ + [542] = {0xFCB52414U, 0x00000001U}, /* RGIDW_MODID[575]:ARSD05*/ + [543] = {0xFCB52418U, 0x00000002U}, /* RGIDW_MODID[576]:ARSD06*/ + [544] = {0xFCB5241CU, 0x0000004AU}, /* RGIDW_MODID[577]:AXIFRAY*/ + [545] = {0xFCB52428U, 0x0000004FU}, /* RGIDW_MODID[578]:AXIRPC*/ + [546] = {0xFCB5242CU, 0x0000000FU}, /* RGIDW_MODID[579]:AXISDHI0*/ + [547] = {0xFCB52430U, 0x00000002U}, /* RGIDW_MODID[580]:ARSD07*/ + [548] = {0xFCB52434U, 0x00000000U}, /* RGIDW_MODID[581]:ARSD08*/ + [549] = {0xFCB52438U, 0x00000002U}, /* RGIDW_MODID[582]:ARSP00*/ + /* After setting */ /* RGIDW_MODID[583]:ARSP01*/ + /* After setting */ /* RGIDW_MODID[584]:ARSP02*/ + [550] = {0xFCB52444U, 0x00000001U}, /* RGIDW_MODID[585]:ARSP03*/ + [551] = {0xFCB52448U, 0x00000002U}, /* RGIDW_MODID[586]:ARSP04*/ + [552] = {0xFCB5244CU, 0x00000001U}, /* RGIDW_MODID[587]:ARSP05*/ + [553] = {0xFCB52450U, 0x00000002U}, /* RGIDW_MODID[588]:ARSP06*/ + [554] = {0xFCB52454U, 0x00000002U}, /* RGIDW_MODID[589]:ARSP07*/ + [555] = {0xFCB52458U, 0x00000000U}, /* RGIDW_MODID[590]:ARSP08*/ + [556] = {0xFCB5245CU, 0x0000004EU}, /* RGIDW_MODID[591]:IPMMUDS001*/ + [557] = {0xFCB52460U, 0x0000000AU}, /* RGIDW_MODID[592]:CKMPER0*/ + [558] = {0xFCB52464U, 0x0000000AU}, /* RGIDW_MODID[593]:ECMPER0*/ + [559] = {0xFCB52468U, 0x0000000EU}, /* RGIDW_MODID[594]:FBAPER0*/ + [560] = {0xFCB5246CU, 0x0000004EU}, /* RGIDW_MODID[595]:FSO0*/ + [561] = {0xFCB52470U, 0x0000004EU}, /* RGIDW_MODID[596]:FSO1*/ + [562] = {0xFCB52474U, 0x0000004EU}, /* RGIDW_MODID[597]:FSO10*/ + [563] = {0xFCB52478U, 0x0000004EU}, /* RGIDW_MODID[598]:FSO2*/ + [564] = {0xFCB5247CU, 0x0000004EU}, /* RGIDW_MODID[599]:FSO3*/ + [565] = {0xFCB52480U, 0x0000004EU}, /* RGIDW_MODID[600]:FSO4*/ + [566] = {0xFCB52484U, 0x0000004EU}, /* RGIDW_MODID[601]:FSO5*/ + [567] = {0xFCB52488U, 0x0000004EU}, /* RGIDW_MODID[602]:FSO6*/ + [568] = {0xFCB5248CU, 0x0000004EU}, /* RGIDW_MODID[603]:FSO7*/ + [569] = {0xFCB52490U, 0x0000004EU}, /* RGIDW_MODID[604]:FSO8*/ + [570] = {0xFCB52494U, 0x0000004EU}, /* RGIDW_MODID[605]:FSO9*/ + [571] = {0xFCB52498U, 0x0000002CU}, /* RGIDW_MODID[606]:ADG*/ + [572] = {0xFCB5249CU, 0x0000000AU}, /* RGIDW_MODID[607]:ECMSD0*/ + [573] = {0xFCB524A0U, 0x0000004EU}, /* RGIDW_MODID[608]:IPMMUDS010*/ + [574] = {0xFCB524A4U, 0x0000004EU}, /* RGIDW_MODID[609]:IPMMUDS011*/ + [575] = {0xFCB524A8U, 0x0000004EU}, /* RGIDW_MODID[610]:I2C0*/ + [576] = {0xFCB524ACU, 0x0000004EU}, /* RGIDW_MODID[611]:I2C1*/ + [577] = {0xFCB524B0U, 0x0000004EU}, /* RGIDW_MODID[612]:I2C2*/ + [578] = {0xFCB524B4U, 0x0000004EU}, /* RGIDW_MODID[613]:I2C3*/ + [579] = {0xFCB524C0U, 0x0000004EU}, /* RGIDW_MODID[614]:IPMMUDS012*/ + [580] = {0xFCB524C8U, 0x0000004EU}, /* RGIDW_MODID[615]:IPMMUDS000*/ + [581] = {0xFCB524CCU, 0x0000004EU}, /* RGIDW_MODID[616]:IPMMUDS013*/ + [582] = {0xFCB524D0U, 0x0000004EU}, /* RGIDW_MODID[617]:IPMMUDS014*/ + [583] = {0xFCB524D4U, 0x0000004EU}, /* RGIDW_MODID[618]:IPMMUDS015*/ + [584] = {0xFCB524D8U, 0x0000004EU}, /* RGIDW_MODID[619]:IPMMUDS002*/ + [585] = {0xFCB524DCU, 0x0000004EU}, /* RGIDW_MODID[620]:IPMMUDS003*/ + [586] = {0xFCB524E0U, 0x0000004EU}, /* RGIDW_MODID[621]:IPMMUDS004*/ + [587] = {0xFCB524E4U, 0x0000004EU}, /* RGIDW_MODID[622]:IPMMUDS005*/ + [588] = {0xFCB524E8U, 0x0000002CU}, /* RGIDW_MODID[623]:SSI*/ + [589] = {0xFCB524ECU, 0x0000004EU}, /* RGIDW_MODID[624]:IPMMUDS006*/ + [590] = {0xFCB524F0U, 0x0000004EU}, /* RGIDW_MODID[625]:IPMMUDS007*/ + [591] = {0xFCB524F4U, 0x0000000CU}, /* RGIDW_MODID[626]:SYDM1P*/ + [592] = {0xFCB524F8U, 0x0000004EU}, /* RGIDW_MODID[627]:IPMMUDS008*/ + [593] = {0xFCB524FCU, 0x0000000CU}, /* RGIDW_MODID[628]:SYDM2P*/ + [594] = {0xFCB52500U, 0x0000004EU}, /* RGIDW_MODID[629]:IPMMUDS009*/ + [595] = {0xFCB52640U, 0x0000000CU}, /* RGIDW_MODID[630]:SYDM100*/ + [596] = {0xFCB52644U, 0x0000000CU}, /* RGIDW_MODID[631]:SYDM101*/ + [597] = {0xFCB52648U, 0x0000000CU}, /* RGIDW_MODID[632]:SYDM110*/ + [598] = {0xFCB5264CU, 0x0000000CU}, /* RGIDW_MODID[633]:SYDM111*/ + [599] = {0xFCB52650U, 0x0000000CU}, /* RGIDW_MODID[634]:SYDM112*/ + [600] = {0xFCB52654U, 0x0000000CU}, /* RGIDW_MODID[635]:SYDM113*/ + [601] = {0xFCB52658U, 0x0000000CU}, /* RGIDW_MODID[636]:SYDM114*/ + [602] = {0xFCB5265CU, 0x0000000CU}, /* RGIDW_MODID[637]:SYDM115*/ + [603] = {0xFCB52660U, 0x0000000CU}, /* RGIDW_MODID[638]:SYDM102*/ + [604] = {0xFCB52664U, 0x0000000CU}, /* RGIDW_MODID[639]:SYDM103*/ + [605] = {0xFCB52668U, 0x0000000CU}, /* RGIDW_MODID[640]:SYDM104*/ + [606] = {0xFCB5266CU, 0x0000000CU}, /* RGIDW_MODID[641]:SYDM105*/ + [607] = {0xFCB52670U, 0x0000000CU}, /* RGIDW_MODID[642]:SYDM106*/ + [608] = {0xFCB52674U, 0x0000000CU}, /* RGIDW_MODID[643]:SYDM107*/ + [609] = {0xFCB52678U, 0x0000000CU}, /* RGIDW_MODID[644]:SYDM108*/ + [610] = {0xFCB5267CU, 0x0000000CU}, /* RGIDW_MODID[645]:SYDM109*/ + [611] = {0xFCB52680U, 0x0000000CU}, /* RGIDW_MODID[646]:SYDM200*/ + [612] = {0xFCB52684U, 0x0000000CU}, /* RGIDW_MODID[647]:SYDM201*/ + [613] = {0xFCB52688U, 0x0000000CU}, /* RGIDW_MODID[648]:SYDM210*/ + [614] = {0xFCB5268CU, 0x0000000CU}, /* RGIDW_MODID[649]:SYDM211*/ + [615] = {0xFCB52690U, 0x0000000CU}, /* RGIDW_MODID[650]:SYDM212*/ + [616] = {0xFCB52694U, 0x0000000CU}, /* RGIDW_MODID[651]:SYDM213*/ + [617] = {0xFCB52698U, 0x0000000CU}, /* RGIDW_MODID[652]:SYDM214*/ + [618] = {0xFCB5269CU, 0x0000000CU}, /* RGIDW_MODID[653]:SYDM215*/ + [619] = {0xFCB526A0U, 0x0000000CU}, /* RGIDW_MODID[654]:SYDM202*/ + [620] = {0xFCB526A4U, 0x0000000CU}, /* RGIDW_MODID[655]:SYDM203*/ + [621] = {0xFCB526A8U, 0x0000000CU}, /* RGIDW_MODID[656]:SYDM204*/ + [622] = {0xFCB526ACU, 0x0000000CU}, /* RGIDW_MODID[657]:SYDM205*/ + [623] = {0xFCB526B0U, 0x0000000CU}, /* RGIDW_MODID[658]:SYDM206*/ + [624] = {0xFCB526B4U, 0x0000000CU}, /* RGIDW_MODID[659]:SYDM207*/ + [625] = {0xFCB526B8U, 0x0000000CU}, /* RGIDW_MODID[660]:SYDM208*/ + [626] = {0xFCB526BCU, 0x0000000CU}, /* RGIDW_MODID[661]:SYDM209*/ + [627] = {0xFC682400U, 0x00000002U}, /* RGIDW_MODID[662]:ARVC0*/ + /* After setting */ /* RGIDW_MODID[663]:ARVC1*/ + /* After setting */ /* RGIDW_MODID[664]:ARVC2*/ + [628] = {0xFC68240CU, 0x00000001U}, /* RGIDW_MODID[665]:ARVC3*/ + [629] = {0xFC682410U, 0x0000000EU}, /* RGIDW_MODID[666]:AXIFBABUSVC*/ + [630] = {0xFC682414U, 0x00000002U}, /* RGIDW_MODID[667]:ARVC4*/ + [631] = {0xFC682418U, 0x00000001U}, /* RGIDW_MODID[668]:ARVC5*/ + [632] = {0xFC68241CU, 0x00000002U}, /* RGIDW_MODID[669]:ARVC6*/ + [633] = {0xFC682420U, 0x00000002U}, /* RGIDW_MODID[670]:ARVC7*/ + [634] = {0xFC682424U, 0x00000000U}, /* RGIDW_MODID[671]:ARVC8*/ + [635] = {0xFC68242CU, 0x0000000AU}, /* RGIDW_MODID[672]:ECMVC0*/ + [636] = {0xFC682434U, 0x0000004EU}, /* RGIDW_MODID[673]:IMR0*/ + [637] = {0xFC682438U, 0x0000004EU}, /* RGIDW_MODID[674]:IMR1*/ + [638] = {0xFC68243CU, 0x0000004EU}, /* RGIDW_MODID[675]:IPMMUVC01*/ + [639] = {0xFC682440U, 0x0000004EU}, /* RGIDW_MODID[676]:IPMMUVC10*/ + [640] = {0xFC682444U, 0x0000000CU}, /* RGIDW_MODID[677]:IMS0*/ + [641] = {0xFC682448U, 0x0000000CU}, /* RGIDW_MODID[678]:IMS1*/ + [642] = {0xFC68244CU, 0x0000004EU}, /* RGIDW_MODID[679]:IPMMUVC00*/ + [643] = {0xFC682450U, 0x0000004EU}, /* RGIDW_MODID[680]:IPMMUVC11*/ + [644] = {0xFC682454U, 0x0000004EU}, /* RGIDW_MODID[681]:IPMMUVC12*/ + [645] = {0xFC682458U, 0x0000004EU}, /* RGIDW_MODID[682]:IPMMUVC13*/ + [646] = {0xFC68245CU, 0x0000004EU}, /* RGIDW_MODID[683]:IPMMUVC14*/ + [647] = {0xFC682460U, 0x0000004EU}, /* RGIDW_MODID[684]:IPMMUVC15*/ + [648] = {0xFC682464U, 0x0000004EU}, /* RGIDW_MODID[685]:IPMMUVC02*/ + [649] = {0xFC682468U, 0x0000004EU}, /* RGIDW_MODID[686]:IPMMUVC03*/ + [650] = {0xFC68246CU, 0x0000004EU}, /* RGIDW_MODID[687]:IPMMUVC04*/ + [651] = {0xFC682470U, 0x0000004EU}, /* RGIDW_MODID[688]:IPMMUVC05*/ + [652] = {0xFC682474U, 0x0000004EU}, /* RGIDW_MODID[689]:IPMMUVC06*/ + [653] = {0xFC682478U, 0x0000004EU}, /* RGIDW_MODID[690]:IPMMUVC07*/ + [654] = {0xFC68247CU, 0x0000004EU}, /* RGIDW_MODID[691]:IPMMUVC08*/ + [655] = {0xFC682480U, 0x0000004EU}, /* RGIDW_MODID[692]:IPMMUVC09*/ + [656] = {0xFC682484U, 0x00000028U}, /* RGIDW_MODID[693]:IV1ES*/ + [657] = {0xFEBE2400U, 0x0000004EU}, /* RGIDW_MODID[694]:CSITOP0*/ + [658] = {0xFEBE2404U, 0x00000002U}, /* RGIDW_MODID[695]:ARVI10*/ + /* After setting */ /* RGIDW_MODID[696]:ARVI11*/ + /* After setting */ /* RGIDW_MODID[697]:ARVI12*/ + [659] = {0xFEBE2410U, 0x00000001U}, /* RGIDW_MODID[698]:ARVI13*/ + [660] = {0xFEBE2414U, 0x00000002U}, /* RGIDW_MODID[699]:ARVI14*/ + [661] = {0xFEBE2418U, 0x00000001U}, /* RGIDW_MODID[700]:ARVI15*/ + [662] = {0xFEBE241CU, 0x00000002U}, /* RGIDW_MODID[701]:ARVI16*/ + [663] = {0xFEBE2420U, 0x00000002U}, /* RGIDW_MODID[702]:ARVI17*/ + [664] = {0xFEBE2424U, 0x00000000U}, /* RGIDW_MODID[703]:ARVI18*/ + [665] = {0xFEBE242CU, 0x0000004EU}, /* RGIDW_MODID[704]:CSITOP1*/ + [666] = {0xFEBE2434U, 0x0000004EU}, /* RGIDW_MODID[705]:DSITLINK0*/ + [667] = {0xFEBE243CU, 0x0000000AU}, /* RGIDW_MODID[706]:ECMVIO1*/ + [668] = {0xFEBE2444U, 0x0000004EU}, /* RGIDW_MODID[707]:IPMMUVI001*/ + [669] = {0xFEBE2448U, 0x0000000CU}, /* RGIDW_MODID[708]:FCPVX0*/ + [670] = {0xFEBE2458U, 0x0000004EU}, /* RGIDW_MODID[709]:IPMMUVI000*/ + [671] = {0xFEBE245CU, 0x0000004EU}, /* RGIDW_MODID[710]:IPMMUVI100*/ + [672] = {0xFEBE2460U, 0x0000004EU}, /* RGIDW_MODID[711]:IPMMUVI010*/ + [673] = {0xFEBE2464U, 0x0000004EU}, /* RGIDW_MODID[712]:IPMMUVI011*/ + [674] = {0xFEBE2468U, 0x0000004EU}, /* RGIDW_MODID[713]:VSPX0*/ + [675] = {0xFEBE2478U, 0x0000004EU}, /* RGIDW_MODID[714]:IPMMUVI012*/ + [676] = {0xFEBE247CU, 0x0000004EU}, /* RGIDW_MODID[715]:IPMMUVI013*/ + [677] = {0xFEBE2480U, 0x0000004EU}, /* RGIDW_MODID[716]:IPMMUVI014*/ + [678] = {0xFEBE2484U, 0x0000004EU}, /* RGIDW_MODID[717]:IPMMUVI015*/ + [679] = {0xFEBE2488U, 0x0000004EU}, /* RGIDW_MODID[718]:IPMMUVI002*/ + [680] = {0xFEBE248CU, 0x0000004EU}, /* RGIDW_MODID[719]:IPMMUVI003*/ + [681] = {0xFEBE2490U, 0x0000004EU}, /* RGIDW_MODID[720]:IPMMUVI004*/ + [682] = {0xFEBE2494U, 0x0000004EU}, /* RGIDW_MODID[721]:IPMMUVI005*/ + [683] = {0xFEBE2498U, 0x0000004EU}, /* RGIDW_MODID[722]:IPMMUVI006*/ + [684] = {0xFEBE249CU, 0x0000004EU}, /* RGIDW_MODID[723]:IPMMUVI007*/ + [685] = {0xFEBE24A0U, 0x0000004EU}, /* RGIDW_MODID[724]:IPMMUVI008*/ + [686] = {0xFEBE24A4U, 0x0000004EU}, /* RGIDW_MODID[725]:IPMMUVI009*/ + [687] = {0xFEBE24A8U, 0x0000004EU}, /* RGIDW_MODID[726]:IPMMUVI101*/ + [688] = {0xFEBE24ACU, 0x0000004EU}, /* RGIDW_MODID[727]:IPMMUVI110*/ + [689] = {0xFEBE24B0U, 0x0000004EU}, /* RGIDW_MODID[728]:IPMMUVI111*/ + [690] = {0xFEBE24B4U, 0x0000004EU}, /* RGIDW_MODID[729]:IPMMUVI112*/ + [691] = {0xFEBE24B8U, 0x0000004EU}, /* RGIDW_MODID[730]:IPMMUVI113*/ + [692] = {0xFEBE24BCU, 0x0000004EU}, /* RGIDW_MODID[731]:IPMMUVI114*/ + [693] = {0xFEBE24C0U, 0x0000004EU}, /* RGIDW_MODID[732]:IPMMUVI115*/ + [694] = {0xFEBE24C4U, 0x0000004EU}, /* RGIDW_MODID[733]:IPMMUVI102*/ + [695] = {0xFEBE24C8U, 0x0000004EU}, /* RGIDW_MODID[734]:IPMMUVI103*/ + [696] = {0xFEBE24CCU, 0x0000004EU}, /* RGIDW_MODID[735]:IPMMUVI104*/ + [697] = {0xFEBE24D0U, 0x0000004EU}, /* RGIDW_MODID[736]:IPMMUVI105*/ + [698] = {0xFEBE24D4U, 0x0000004EU}, /* RGIDW_MODID[737]:IPMMUVI106*/ + [699] = {0xFEBE24D8U, 0x0000004EU}, /* RGIDW_MODID[738]:IPMMUVI107*/ + [700] = {0xFEBE24DCU, 0x0000004EU}, /* RGIDW_MODID[739]:IPMMUVI108*/ + [701] = {0xFEBE24E0U, 0x0000004EU}, /* RGIDW_MODID[740]:IPMMUVI109*/ + [702] = {0xFEBE2504U, 0x0000000EU}, /* RGIDW_MODID[741]:AXIFBABUSVIO*/ + [703] = {0xFEBF2400U, 0x00000002U}, /* RGIDW_MODID[742]:ARVI0*/ + /* After setting */ /* RGIDW_MODID[743]:ARVI1*/ + /* After setting */ /* RGIDW_MODID[744]:ARVI2*/ + [704] = {0xFEBF240CU, 0x00000001U}, /* RGIDW_MODID[745]:ARVI3*/ + [705] = {0xFEBF2410U, 0x00000002U}, /* RGIDW_MODID[746]:ARVI4*/ + [706] = {0xFEBF2414U, 0x00000001U}, /* RGIDW_MODID[747]:ARVI5*/ + [707] = {0xFEBF2418U, 0x00000002U}, /* RGIDW_MODID[748]:ARVI6*/ + [708] = {0xFEBF241CU, 0x00000002U}, /* RGIDW_MODID[749]:ARVI7*/ + [709] = {0xFEBF2420U, 0x00000000U}, /* RGIDW_MODID[750]:ARVI8*/ + [710] = {0xFEBF2424U, 0x0000000AU}, /* RGIDW_MODID[751]:ECMVIO0*/ + [711] = {0xFEBF2428U, 0x0000004EU}, /* RGIDW_MODID[752]:ISP0*/ + [712] = {0xFEBF242CU, 0x0000004EU}, /* RGIDW_MODID[753]:ISP0CORE*/ + [713] = {0xFEBF2430U, 0x0000004EU}, /* RGIDW_MODID[754]:ISP1*/ + [714] = {0xFEBF2454U, 0x0000004EU}, /* RGIDW_MODID[755]:VIN00*/ + [715] = {0xFEBF2458U, 0x0000004EU}, /* RGIDW_MODID[756]:VIN01*/ + [716] = {0xFEBF245CU, 0x0000004EU}, /* RGIDW_MODID[757]:VIN02*/ + [717] = {0xFEBF2460U, 0x0000004EU}, /* RGIDW_MODID[758]:VIN03*/ + [718] = {0xFEBF2464U, 0x0000004EU}, /* RGIDW_MODID[759]:VIN04*/ + [719] = {0xFEBF2468U, 0x0000004EU}, /* RGIDW_MODID[760]:VIN05*/ + [720] = {0xFEBF246CU, 0x0000004EU}, /* RGIDW_MODID[761]:VIN06*/ + [721] = {0xFEBF2470U, 0x0000004EU}, /* RGIDW_MODID[762]:VIN07*/ + [722] = {0xFEBF2474U, 0x0000004EU}, /* RGIDW_MODID[763]:VIN10*/ + [723] = {0xFEBF2478U, 0x0000004EU}, /* RGIDW_MODID[764]:VIN11*/ + [724] = {0xFEBF247CU, 0x0000004EU}, /* RGIDW_MODID[765]:VIN12*/ + [725] = {0xFEBF2480U, 0x0000004EU}, /* RGIDW_MODID[766]:VIN13*/ + [726] = {0xFEBF2484U, 0x0000004EU}, /* RGIDW_MODID[767]:VIN14*/ + [727] = {0xFEBF2488U, 0x0000004EU}, /* RGIDW_MODID[768]:VIN15*/ + [728] = {0xFEBF248CU, 0x0000004EU}, /* RGIDW_MODID[769]:VIN16*/ + [729] = {0xFEBF2490U, 0x0000004EU}, /* RGIDW_MODID[770]:VIN17*/ + [730] = {0xFC312400U, 0x00000002U}, /* RGIDW_MODID[771]:ARVIP00*/ + /* After setting */ /* RGIDW_MODID[772]:ARVIP01*/ + /* After setting */ /* RGIDW_MODID[773]:ARVIP02*/ + [731] = {0xFC31240CU, 0x00000001U}, /* RGIDW_MODID[774]:ARVIP03*/ + [732] = {0xFC312410U, 0x0000000EU}, /* RGIDW_MODID[775]:AXIFBABUSVIP0*/ + [733] = {0xFC312414U, 0x00000002U}, /* RGIDW_MODID[776]:ARVIP04*/ + [734] = {0xFC312418U, 0x00000001U}, /* RGIDW_MODID[777]:ARVIP05*/ + [735] = {0xFC31241CU, 0x00000002U}, /* RGIDW_MODID[778]:ARVIP06*/ + [736] = {0xFC312420U, 0x00000002U}, /* RGIDW_MODID[779]:ARVIP07*/ + [737] = {0xFC312424U, 0x00000000U}, /* RGIDW_MODID[780]:ARVIP08*/ + [738] = {0xFC31242CU, 0x0000000AU}, /* RGIDW_MODID[781]:ECMVIP0*/ + [739] = {0xFC312430U, 0x0000004EU}, /* RGIDW_MODID[782]:IPMMUVIP000*/ + [740] = {0xFC312438U, 0x0000004EU}, /* RGIDW_MODID[783]:SMPO0*/ + [741] = {0xFC31243CU, 0x0000004EU}, /* RGIDW_MODID[784]:SMPS0*/ + [742] = {0xFC312440U, 0x0000004EU}, /* RGIDW_MODID[785]:UMFL0*/ + [743] = {0xFC312444U, 0x0000004EU}, /* RGIDW_MODID[786]:IPMMUVIP001*/ + [744] = {0xFC312448U, 0x0000004EU}, /* RGIDW_MODID[787]:IPMMUVIP010*/ + [745] = {0xFC31244CU, 0x0000004EU}, /* RGIDW_MODID[788]:IPMMUVIP011*/ + [746] = {0xFC312450U, 0x0000004EU}, /* RGIDW_MODID[789]:UMFL0M_W*/ + [747] = {0xFC312454U, 0x0000004EU}, /* RGIDW_MODID[790]:IPMMUVIP012*/ + [748] = {0xFC312458U, 0x0000004EU}, /* RGIDW_MODID[791]:IPMMUVIP013*/ + [749] = {0xFC31245CU, 0x0000004EU}, /* RGIDW_MODID[792]:IPMMUVIP014*/ + [750] = {0xFC312460U, 0x0000004EU}, /* RGIDW_MODID[793]:IPMMUVIP015*/ + [751] = {0xFC312464U, 0x0000004EU}, /* RGIDW_MODID[794]:IPMMUVIP002*/ + [752] = {0xFC312468U, 0x0000004EU}, /* RGIDW_MODID[795]:IPMMUVIP003*/ + [753] = {0xFC31246CU, 0x0000004EU}, /* RGIDW_MODID[796]:IPMMUVIP004*/ + [754] = {0xFC312470U, 0x0000004EU}, /* RGIDW_MODID[797]:IPMMUVIP005*/ + [755] = {0xFC312474U, 0x0000004EU}, /* RGIDW_MODID[798]:IPMMUVIP006*/ + [756] = {0xFC312478U, 0x0000004EU}, /* RGIDW_MODID[799]:IPMMUVIP007*/ + [757] = {0xFC31247CU, 0x0000004EU}, /* RGIDW_MODID[800]:IPMMUVIP008*/ + [758] = {0xFC312480U, 0x0000004EU}, /* RGIDW_MODID[801]:IPMMUVIP009*/ + [759] = {0xFC8824A0U, 0x00000002U}, /* RGIDW_MODID[802]:ARDSP0*/ + /* After setting */ /* RGIDW_MODID[803]:ARDSP1*/ + /* After setting */ /* RGIDW_MODID[804]:ARDSP2*/ + [760] = {0xFC8824ACU, 0x00000001U}, /* RGIDW_MODID[805]:ARDSP3*/ + [761] = {0xFC8824B0U, 0x00000002U}, /* RGIDW_MODID[806]:ARDSP4*/ + [762] = {0xFC8824B4U, 0x00000001U}, /* RGIDW_MODID[807]:ARDSP5*/ + [763] = {0xFC8824B8U, 0x00000002U}, /* RGIDW_MODID[808]:ARDSP6*/ + [764] = {0xFC8824BCU, 0x00000002U}, /* RGIDW_MODID[809]:ARDSP7*/ + [765] = {0xFC8824C0U, 0x0000000AU}, /* RGIDW_MODID[810]:ECMDSP*/ + [766] = {0xFC882490U, 0x0000000CU}, /* RGIDW_MODID[811]:AXIDSP0*/ + [767] = {0xFC882494U, 0x0000000CU}, /* RGIDW_MODID[812]:AXIDSP1*/ + [768] = {0xFC882498U, 0x0000000CU}, /* RGIDW_MODID[813]:AXIDSP2*/ + [769] = {0xFC88249CU, 0x0000000CU}, /* RGIDW_MODID[814]:AXIDSP3*/ + [771] = {0xFDDB969CU, 0x00000000U}, /* RGIDW_MODID[815]:ARCC*/ + [770] = {0xFDDB96B0U, 0x00000000U}, /* RGIDW_MODID[816]:ARRTRAM*/ + [772] = {0xFCB52424U, 0x00000000U}, /* RGIDW_MODID[817]:RSV0*/ + [773] = {0xFC31250CU, 0x00000004U}, /* RGIDW_MODID[818]:PAP*/ + [774] = {0xFC8824C4U, 0x0000004EU}, /* RGIDW_MODID[819]:IMPM0100*/ + [775] = {0xFC8824C8U, 0x0000004EU}, /* RGIDW_MODID[820]:IMPM0101*/ + [776] = {0xFC8824CCU, 0x0000004EU}, /* RGIDW_MODID[821]:IMPM0102*/ + [777] = {0xFC8824D0U, 0x0000004EU}, /* RGIDW_MODID[822]:IMPM0103*/ + [778] = {0xFC8824D4U, 0x0000004EU}, /* RGIDW_MODID[823]:IMPM0104*/ + [779] = {0xFC8824D8U, 0x0000004EU}, /* RGIDW_MODID[824]:IMPM0105*/ + [780] = {0xFC8824DCU, 0x0000004EU}, /* RGIDW_MODID[825]:IMPM0106*/ + [781] = {0xFC8824E0U, 0x0000004EU}, /* RGIDW_MODID[826]:IMPM0107*/ + [782] = {0xFC8824E4U, 0x0000004EU}, /* RGIDW_MODID[827]:IMPM0200*/ + [783] = {0xFC8824E8U, 0x0000004EU}, /* RGIDW_MODID[828]:IMPM0201*/ + [784] = {0xFC8824ECU, 0x0000004EU}, /* RGIDW_MODID[829]:IMPS0000*/ + [785] = {0xFC8824F0U, 0x0000004EU}, /* RGIDW_MODID[830]:IMPS0001*/ + [786] = {0xFC8824F4U, 0x0000004EU}, /* RGIDW_MODID[831]:IMPS0002*/ + [787] = {0xFC8824F8U, 0x0000004EU}, /* RGIDW_MODID[832]:IMPS0003*/ + [788] = {0xFC8824FCU, 0x0000004EU}, /* RGIDW_MODID[833]:IMPS0100*/ + [789] = {0xFC882500U, 0x0000004EU}, /* RGIDW_MODID[834]:IMPS0101*/ + [790] = {0xFC882504U, 0x0000004EU}, /* RGIDW_MODID[835]:IMPS0102*/ + [791] = {0xFC882508U, 0x0000004EU}, /* RGIDW_MODID[836]:IMPS0103*/ + [792] = {0xFC88250CU, 0x0000004EU}, /* RGIDW_MODID[837]:IMPS0104*/ + [793] = {0xFC882510U, 0x0000004EU}, /* RGIDW_MODID[838]:IMPS0105*/ + [794] = {0xFC882514U, 0x0000004EU}, /* RGIDW_MODID[839]:IMPS0106*/ + [795] = {0xFC882518U, 0x0000004EU}, /* RGIDW_MODID[840]:IMPS0107*/ + [796] = {0xFC88251CU, 0x0000004EU}, /* RGIDW_MODID[841]:IMPS0108*/ + [797] = {0xFC882520U, 0x0000004EU}, /* RGIDW_MODID[842]:IMPS0109*/ + [798] = {0xFC882524U, 0x0000004EU}, /* RGIDW_MODID[843]:IMPS0110*/ + [799] = {0xFC882528U, 0x0000004EU}, /* RGIDW_MODID[844]:IMPS0111*/ + [800] = {0xFC88252CU, 0x0000004EU}, /* RGIDW_MODID[845]:IMPS0200*/ + [801] = {0xFC882530U, 0x0000004EU}, /* RGIDW_MODID[846]:IMPS0201*/ + [802] = {0xFC882534U, 0x0000004EU}, /* RGIDW_MODID[847]:IMPS0202*/ + [803] = {0xFEBD2428U, 0x0000000CU}, /* RGIDW_MODID[848]:DOC*/ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_sec_tbl" +const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[] = { + [0] = {0xFD483400U, 0x00000000U}, /* SEC_MODID[0]:ARMGC0*/ + [1] = {0xFD483404U, 0x00000002U}, /* SEC_MODID[1]:ARMGC1*/ + [2] = {0xFD483408U, 0x00000002U}, /* SEC_MODID[2]:ARMGC2*/ + [3] = {0xFD48340CU, 0x00000002U}, /* SEC_MODID[3]:ARRT00*/ + [4] = {0xFD483410U, 0x00000002U}, /* SEC_MODID[4]:ARRT01*/ + [5] = {0xFD483414U, 0x00000002U}, /* SEC_MODID[5]:ARRT02*/ + [6] = {0xFD483418U, 0x00000002U}, /* SEC_MODID[6]:ARRT03*/ + [7] = {0xFD48341CU, 0x00000002U}, /* SEC_MODID[7]:ARRT04*/ + [8] = {0xFD483420U, 0x00000002U}, /* SEC_MODID[8]:ARRT05*/ + [9] = {0xFD483424U, 0x00000002U}, /* SEC_MODID[9]:ARRT06*/ + [10] = {0xFD483428U, 0x00000002U}, /* SEC_MODID[10]:ARRT07*/ + [11] = {0xFD48342CU, 0x00000002U}, /* SEC_MODID[11]:ARRT08*/ + [12] = {0xFD483430U, 0x00000000U}, /* SEC_MODID[12]:LIFEC0*/ + [13] = {0xFD483434U, 0x00000002U}, /* SEC_MODID[13]:SWDT*/ + [14] = {0xFD483438U, 0x00000002U}, /* SEC_MODID[14]:TMU0*/ + [15] = {0xFD48343CU, 0x00000002U}, /* SEC_MODID[15]:WDT*/ + [16] = {0xFD483440U, 0x00000002U}, /* SEC_MODID[16]:WWDT0*/ + [17] = {0xFD483444U, 0x00000002U}, /* SEC_MODID[17]:WWDT1*/ + [18] = {0xFD483448U, 0x00000002U}, /* SEC_MODID[18]:WWDT2*/ + [19] = {0xFD48344CU, 0x00000002U}, /* SEC_MODID[19]:WWDT3*/ + [20] = {0xFD483450U, 0x00000002U}, /* SEC_MODID[20]:WWDT4*/ + [21] = {0xFD483454U, 0x00000002U}, /* SEC_MODID[21]:WWDT5*/ + [22] = {0xFD483458U, 0x00000002U}, /* SEC_MODID[22]:WWDT6*/ + [23] = {0xFD483468U, 0x00000002U}, /* SEC_MODID[23]:ECMRT3*/ + [24] = {0xFDA03404U, 0x00000002U}, /* SEC_MODID[24]:APMU0*/ + [25] = {0xFDA03408U, 0x00000002U}, /* SEC_MODID[25]:APMU1*/ + [26] = {0xFDA0340CU, 0x00000002U}, /* SEC_MODID[26]:APMU10*/ + [27] = {0xFDA03410U, 0x00000002U}, /* SEC_MODID[27]:APMU11*/ + [28] = {0xFDA03414U, 0x00000002U}, /* SEC_MODID[28]:APMU12*/ + [29] = {0xFDA03418U, 0x00000002U}, /* SEC_MODID[29]:APMU13*/ + [30] = {0xFDA0341CU, 0x00000002U}, /* SEC_MODID[30]:APMU14*/ + [31] = {0xFDA03420U, 0x00000002U}, /* SEC_MODID[31]:APMU15*/ + [32] = {0xFDA03424U, 0x00000002U}, /* SEC_MODID[32]:APMU2*/ + [33] = {0xFDA03428U, 0x00000002U}, /* SEC_MODID[33]:APMU3*/ + [34] = {0xFDA0342CU, 0x00000002U}, /* SEC_MODID[34]:APMU4*/ + [35] = {0xFDA03430U, 0x00000002U}, /* SEC_MODID[35]:APMU5*/ + [36] = {0xFDA03434U, 0x00000002U}, /* SEC_MODID[36]:APMU6*/ + [37] = {0xFDA03438U, 0x00000002U}, /* SEC_MODID[37]:APMU7*/ + [38] = {0xFDA0343CU, 0x00000002U}, /* SEC_MODID[38]:APMU8*/ + [39] = {0xFDA03440U, 0x00000002U}, /* SEC_MODID[39]:APMU9*/ + [40] = {0xFDA03444U, 0x00000002U}, /* SEC_MODID[40]:ARS00*/ + [41] = {0xFDA03448U, 0x00000002U}, /* SEC_MODID[41]:ARS01*/ + [42] = {0xFDA0344CU, 0x00000002U}, /* SEC_MODID[42]:ARS02*/ + [43] = {0xFDA03450U, 0x00000002U}, /* SEC_MODID[43]:ARS03*/ + [44] = {0xFDA03454U, 0x00000002U}, /* SEC_MODID[44]:ARS04*/ + [45] = {0xFDA03458U, 0x00000002U}, /* SEC_MODID[45]:ARS05*/ + [46] = {0xFDA0345CU, 0x00000002U}, /* SEC_MODID[46]:ARS06*/ + [47] = {0xFDA03460U, 0x00000002U}, /* SEC_MODID[47]:ARS07*/ + [48] = {0xFDA03464U, 0x00000002U}, /* SEC_MODID[48]:ARS08*/ + [49] = {0xFDA03468U, 0x00000002U}, /* SEC_MODID[49]:CMT0*/ + [50] = {0xFDA0346CU, 0x00000002U}, /* SEC_MODID[50]:CMT1*/ + [51] = {0xFDA03470U, 0x00000002U}, /* SEC_MODID[51]:CMT2*/ + [52] = {0xFDA03474U, 0x00000002U}, /* SEC_MODID[52]:CMT3*/ + [53] = {0xFDA03478U, 0x00000002U}, /* SEC_MODID[53]:CKM*/ + [54] = {0xFDA0347CU, 0x00000002U}, /* SEC_MODID[54]:DBE*/ + [55] = {0xFDA03480U, 0x00000002U}, /* SEC_MODID[55]:IRQC*/ + [56] = {0xFDA03484U, 0x00000002U}, /* SEC_MODID[56]:ECMPS0*/ + [57] = {0xFDA03488U, 0x00000002U}, /* SEC_MODID[57]:OTP0*/ + [58] = {0xFDA0348CU, 0x00000002U}, /* SEC_MODID[58]:OTP1*/ + [59] = {0xFDA0349CU, 0x00000002U}, /* SEC_MODID[59]:SCMT*/ + [60] = {0xFDA034A8U, 0x00000002U}, /* SEC_MODID[60]:TSC1*/ + [61] = {0xFDA034ACU, 0x00000002U}, /* SEC_MODID[61]:TSC2*/ + [62] = {0xFDA034B8U, 0x00000002U}, /* SEC_MODID[62]:UCMT*/ + [63] = {0xFDA03500U, 0x00000002U}, /* SEC_MODID[63]:CPG0*/ + [64] = {0xFDA03504U, 0x00000002U}, /* SEC_MODID[64]:CPG1*/ + [65] = {0xFDA03508U, 0x00000002U}, /* SEC_MODID[65]:CPG2*/ + [66] = {0xFDA0350CU, 0x00000002U}, /* SEC_MODID[66]:CPG3*/ + [67] = {0xFDA03510U, 0x00000002U}, /* SEC_MODID[67]:PFC00*/ + [68] = {0xFDA03514U, 0x00000002U}, /* SEC_MODID[68]:PFC01*/ + [69] = {0xFDA03518U, 0x00000002U}, /* SEC_MODID[69]:PFC02*/ + [70] = {0xFDA0351CU, 0x00000002U}, /* SEC_MODID[70]:PFC03*/ + [71] = {0xFDA03520U, 0x00000002U}, /* SEC_MODID[71]:PFC10*/ + [72] = {0xFDA03524U, 0x00000002U}, /* SEC_MODID[72]:PFC11*/ + [73] = {0xFDA03528U, 0x00000002U}, /* SEC_MODID[73]:PFC12*/ + [74] = {0xFDA0352CU, 0x00000002U}, /* SEC_MODID[74]:PFC13*/ + [75] = {0xFDA03530U, 0x00000002U}, /* SEC_MODID[75]:PFC20*/ + [76] = {0xFDA03534U, 0x00000002U}, /* SEC_MODID[76]:PFC21*/ + [77] = {0xFDA03538U, 0x00000002U}, /* SEC_MODID[77]:PFC22*/ + [78] = {0xFDA0353CU, 0x00000002U}, /* SEC_MODID[78]:PFC23*/ + [79] = {0xFDA03550U, 0x00000002U}, /* SEC_MODID[79]:PFCS0*/ + [80] = {0xFDA03554U, 0x00000002U}, /* SEC_MODID[80]:PFCS1*/ + [81] = {0xFDA03558U, 0x00000002U}, /* SEC_MODID[81]:PFCS2*/ + [82] = {0xFDA0355CU, 0x00000002U}, /* SEC_MODID[82]:PFCS3*/ + [83] = {0xFDA03560U, 0x00000002U}, /* SEC_MODID[83]:RESET0*/ + [84] = {0xFDA03564U, 0x00000002U}, /* SEC_MODID[84]:RESET1*/ + [85] = {0xFDA03568U, 0x00000002U}, /* SEC_MODID[85]:RESET2*/ + [86] = {0xFDA0356CU, 0x00000002U}, /* SEC_MODID[86]:RESET3*/ + [87] = {0xFDA03570U, 0x00000002U}, /* SEC_MODID[87]:SYS0*/ + [88] = {0xFDA03574U, 0x00000002U}, /* SEC_MODID[88]:SYS1*/ + [89] = {0xFDA03578U, 0x00000002U}, /* SEC_MODID[89]:SYS2*/ + [90] = {0xFDA0357CU, 0x00000002U}, /* SEC_MODID[90]:SYS3*/ + [91] = {0xFCB63400U, 0x00000002U}, /* SEC_MODID[91]:DMAMSI0*/ + [92] = {0xFCB63404U, 0x00000002U}, /* SEC_MODID[92]:DMAMSI1*/ + [93] = {0xFCB63408U, 0x00000002U}, /* SEC_MODID[93]:DMAMSI2*/ + [94] = {0xFCB6340CU, 0x00000002U}, /* SEC_MODID[94]:DMAMSI3*/ + [95] = {0xFCB63410U, 0x00000002U}, /* SEC_MODID[95]:DMAMSI4*/ + [96] = {0xFCB63414U, 0x00000002U}, /* SEC_MODID[96]:DMAMSI5*/ + [97] = {0xFCB63418U, 0x00000002U}, /* SEC_MODID[97]:ECMSP3*/ + [98] = {0xFCB63424U, 0x00000002U}, /* SEC_MODID[98]:ARSP30*/ + [99] = {0xFCB63428U, 0x00000002U}, /* SEC_MODID[99]:ARSP31*/ + [100] = {0xFCB6342CU, 0x00000002U}, /* SEC_MODID[100]:ARSP32*/ + [101] = {0xFCB63430U, 0x00000002U}, /* SEC_MODID[101]:ARSP33*/ + [102] = {0xFCB63434U, 0x00000002U}, /* SEC_MODID[102]:ARSP34*/ + [103] = {0xFCB63438U, 0x00000002U}, /* SEC_MODID[103]:ARSP35*/ + [104] = {0xFCB6343CU, 0x00000002U}, /* SEC_MODID[104]:ARSP36*/ + [105] = {0xFCB63440U, 0x00000002U}, /* SEC_MODID[105]:ARSP37*/ + [106] = {0xFCB63444U, 0x00000002U}, /* SEC_MODID[106]:ARSP38*/ + [107] = {0xFCB63448U, 0x00000002U}, /* SEC_MODID[107]:MSI0*/ + [108] = {0xFCB6344CU, 0x00000002U}, /* SEC_MODID[108]:MSI1*/ + [109] = {0xFCB63450U, 0x00000002U}, /* SEC_MODID[109]:MSI2*/ + [110] = {0xFCB63454U, 0x00000002U}, /* SEC_MODID[110]:MSI3*/ + [111] = {0xFCB63458U, 0x00000002U}, /* SEC_MODID[111]:MSI4*/ + [112] = {0xFCB6345CU, 0x00000002U}, /* SEC_MODID[112]:MSI5*/ + [113] = {0xFCB93400U, 0x00000002U}, /* SEC_MODID[113]:ARSP40*/ + [114] = {0xFCB93404U, 0x00000002U}, /* SEC_MODID[114]:ARSP41*/ + [115] = {0xFCB93408U, 0x00000002U}, /* SEC_MODID[115]:ARSP42*/ + [116] = {0xFCB9340CU, 0x00000002U}, /* SEC_MODID[116]:ARSP43*/ + [117] = {0xFCB93410U, 0x00000002U}, /* SEC_MODID[117]:ARSP44*/ + [118] = {0xFCB93414U, 0x00000002U}, /* SEC_MODID[118]:ARSP45*/ + [119] = {0xFCB93418U, 0x00000002U}, /* SEC_MODID[119]:ARSP46*/ + [120] = {0xFCB9341CU, 0x00000002U}, /* SEC_MODID[120]:ARSP47*/ + [121] = {0xFCB93420U, 0x00000002U}, /* SEC_MODID[121]:ARSP48*/ + [122] = {0xFCB93424U, 0x00000002U}, /* SEC_MODID[122]:DMAHSCIF0*/ + [123] = {0xFCB93428U, 0x00000002U}, /* SEC_MODID[123]:DMAHSCIF1*/ + [124] = {0xFCB9342CU, 0x00000002U}, /* SEC_MODID[124]:DMAHSCIF2*/ + [125] = {0xFCB93430U, 0x00000002U}, /* SEC_MODID[125]:DMAHSCIF3*/ + [126] = {0xFCB93434U, 0x00000002U}, /* SEC_MODID[126]:DMASCIF0*/ + [127] = {0xFCB93438U, 0x00000002U}, /* SEC_MODID[127]:DMASCIF1*/ + [128] = {0xFCB9343CU, 0x00000002U}, /* SEC_MODID[128]:DMASCIF3*/ + [129] = {0xFCB93440U, 0x00000002U}, /* SEC_MODID[129]:DMASCIF4*/ + [130] = {0xFCB93444U, 0x00000002U}, /* SEC_MODID[130]:ECMSP4*/ + [131] = {0xFCB93448U, 0x00000002U}, /* SEC_MODID[131]:HSCIF0*/ + [132] = {0xFCB9344CU, 0x00000002U}, /* SEC_MODID[132]:HSCIF1*/ + [133] = {0xFCB93450U, 0x00000002U}, /* SEC_MODID[133]:HSCIF2*/ + [134] = {0xFCB93454U, 0x00000002U}, /* SEC_MODID[134]:HSCIF3*/ + [135] = {0xFCB93458U, 0x00000002U}, /* SEC_MODID[135]:SCIF0*/ + [136] = {0xFCB9345CU, 0x00000002U}, /* SEC_MODID[136]:SCIF1*/ + [137] = {0xFCB93460U, 0x00000002U}, /* SEC_MODID[137]:SCIF3*/ + [138] = {0xFCB93464U, 0x00000002U}, /* SEC_MODID[138]:SCIF4*/ + [139] = {0xFCB93468U, 0x00000002U}, /* SEC_MODID[139]:TMU1*/ + [140] = {0xFCB9346CU, 0x00000002U}, /* SEC_MODID[140]:TMU2*/ + [141] = {0xFCB93470U, 0x00000002U}, /* SEC_MODID[141]:TMU3*/ + [142] = {0xFCB93474U, 0x00000002U}, /* SEC_MODID[142]:TMU4*/ + [143] = {0xFCB93478U, 0x00000002U}, /* SEC_MODID[143]:CANFD*/ + [144] = {0xFCB9347CU, 0x00000002U}, /* SEC_MODID[144]:DMACANFD*/ + [145] = {0xFCB93480U, 0x00000002U}, /* SEC_MODID[145]:DMATPU0*/ + [146] = {0xFCB93484U, 0x00000002U}, /* SEC_MODID[146]:PWM0*/ + [147] = {0xFCB93488U, 0x00000002U}, /* SEC_MODID[147]:PWM1*/ + [148] = {0xFCB9348CU, 0x00000002U}, /* SEC_MODID[148]:PWM2*/ + [149] = {0xFCB93490U, 0x00000002U}, /* SEC_MODID[149]:PWM3*/ + [150] = {0xFCB93494U, 0x00000002U}, /* SEC_MODID[150]:PWM4*/ + [151] = {0xFCB934ACU, 0x00000002U}, /* SEC_MODID[151]:TPU0*/ + [152] = {0xFEBD3400U, 0x00000002U}, /* SEC_MODID[152]:ARVI40*/ + [153] = {0xFEBD3404U, 0x00000002U}, /* SEC_MODID[153]:ARVI41*/ + [154] = {0xFEBD3408U, 0x00000002U}, /* SEC_MODID[154]:ARVI42*/ + [155] = {0xFEBD340CU, 0x00000002U}, /* SEC_MODID[155]:ARVI43*/ + [156] = {0xFEBD3410U, 0x00000002U}, /* SEC_MODID[156]:ARVI44*/ + [157] = {0xFEBD3414U, 0x00000002U}, /* SEC_MODID[157]:ARVI45*/ + [158] = {0xFEBD3418U, 0x00000002U}, /* SEC_MODID[158]:ARVI46*/ + [159] = {0xFEBD341CU, 0x00000002U}, /* SEC_MODID[159]:ARVI47*/ + [160] = {0xFEBD3420U, 0x00000002U}, /* SEC_MODID[160]:ARVI48*/ + [161] = {0xFEBD3424U, 0x00000002U}, /* SEC_MODID[161]:DIS0*/ + [162] = {0xFEBD3430U, 0x00000002U}, /* SEC_MODID[162]:ECMVIO2*/ + [163] = {0xFEBD3434U, 0x00000002U}, /* SEC_MODID[163]:FCPVD0*/ + [164] = {0xFEBD343CU, 0x00000002U}, /* SEC_MODID[164]:VSPD0*/ + [165] = {0xFCF83400U, 0x00000002U}, /* SEC_MODID[165]:CKMHSC*/ + [166] = {0xFCF83404U, 0x00000002U}, /* SEC_MODID[166]:AXIPCI001*/ + [167] = {0xFCF83408U, 0x00000002U}, /* SEC_MODID[167]:AXIPCI002*/ + [168] = {0xFCF8340CU, 0x00000002U}, /* SEC_MODID[168]:AXIPCI003*/ + [169] = {0xFCF83414U, 0x00000002U}, /* SEC_MODID[169]:AXIPCI005*/ + [170] = {0xFCF83418U, 0x00000002U}, /* SEC_MODID[170]:AXIPCI006*/ + [171] = {0xFCF8341CU, 0x00000002U}, /* SEC_MODID[171]:AXIPCI007*/ + [172] = {0xFCF83420U, 0x00000002U}, /* SEC_MODID[172]:AXIPCI008*/ + [173] = {0xFCF83424U, 0x00000002U}, /* SEC_MODID[173]:AXIPCI009*/ + [174] = {0xFCF83428U, 0x00000002U}, /* SEC_MODID[174]:AXIPCI010*/ + [175] = {0xFCF8342CU, 0x00000002U}, /* SEC_MODID[175]:AXIPCI011*/ + [176] = {0xFCF83430U, 0x00000002U}, /* SEC_MODID[176]:AXIPCI012*/ + [177] = {0xFCF83434U, 0x00000002U}, /* SEC_MODID[177]:AXIPCI013*/ + [178] = {0xFCF83438U, 0x00000002U}, /* SEC_MODID[178]:AXIPCI014*/ + [179] = {0xFCF8343CU, 0x00000002U}, /* SEC_MODID[179]:AXIPCI015*/ + [180] = {0xFCF83484U, 0x00000002U}, /* SEC_MODID[180]:GPTP*/ + [181] = {0xFCF83488U, 0x00000002U}, /* SEC_MODID[181]:IPMMUHC00*/ + [182] = {0xFCF834F4U, 0x00000002U}, /* SEC_MODID[182]:AXIPCI000*/ + [183] = {0xFCF834F8U, 0x00000002U}, /* SEC_MODID[183]:AXIPCI004*/ + [184] = {0xFCF834FCU, 0x00000002U}, /* SEC_MODID[184]:IPMMUHC01*/ + [185] = {0xFCF83500U, 0x00000002U}, /* SEC_MODID[185]:AVB0*/ + [186] = {0xFCF83504U, 0x00000002U}, /* SEC_MODID[186]:AVB1*/ + [187] = {0xFCF83508U, 0x00000002U}, /* SEC_MODID[187]:AVB2*/ + [188] = {0xFCF8350CU, 0x00000002U}, /* SEC_MODID[188]:IPMMUHC10*/ + [189] = {0xFCF83510U, 0x00000002U}, /* SEC_MODID[189]:IPMMUHC11*/ + [190] = {0xFCF83514U, 0x00000002U}, /* SEC_MODID[190]:IPMMUHC12*/ + [191] = {0xFCF83518U, 0x00000002U}, /* SEC_MODID[191]:IPMMUHC13*/ + [192] = {0xFCF8351CU, 0x00000002U}, /* SEC_MODID[192]:PPHY0*/ + [193] = {0xFCF83524U, 0x00000002U}, /* SEC_MODID[193]:IPMMUHC14*/ + [194] = {0xFCF83528U, 0x00000002U}, /* SEC_MODID[194]:IPMMUHC15*/ + [195] = {0xFCF8352CU, 0x00000002U}, /* SEC_MODID[195]:FBAHSC*/ + [196] = {0xFCF83530U, 0x00000002U}, /* SEC_MODID[196]:IPMMUHC02*/ + [197] = {0xFCF83538U, 0x00000002U}, /* SEC_MODID[197]:ECMHSC*/ + [198] = {0xFCF8353CU, 0x00000002U}, /* SEC_MODID[198]:ARHC0*/ + [199] = {0xFCF83540U, 0x00000002U}, /* SEC_MODID[199]:ARHC1*/ + [200] = {0xFCF83544U, 0x00000002U}, /* SEC_MODID[200]:ARHC2*/ + [201] = {0xFCF83548U, 0x00000002U}, /* SEC_MODID[201]:ARHC3*/ + [202] = {0xFCF8354CU, 0x00000002U}, /* SEC_MODID[202]:ARHC4*/ + [203] = {0xFCF83550U, 0x00000002U}, /* SEC_MODID[203]:ARHC5*/ + [204] = {0xFCF83554U, 0x00000002U}, /* SEC_MODID[204]:ARHC6*/ + [205] = {0xFCF83558U, 0x00000002U}, /* SEC_MODID[205]:ARHC7*/ + [206] = {0xFCF8355CU, 0x00000002U}, /* SEC_MODID[206]:ARHC8*/ + [207] = {0xFCF83560U, 0x00000002U}, /* SEC_MODID[207]:IPMMUHC03*/ + [208] = {0xFCF83564U, 0x00000002U}, /* SEC_MODID[208]:IPMMUHC04*/ + [209] = {0xFCF83568U, 0x00000002U}, /* SEC_MODID[209]:IPMMUHC05*/ + [210] = {0xFCF8356CU, 0x00000002U}, /* SEC_MODID[210]:IPMMUHC06*/ + [211] = {0xFCF83570U, 0x00000002U}, /* SEC_MODID[211]:IPMMUHC07*/ + [212] = {0xFCF83574U, 0x00000002U}, /* SEC_MODID[212]:IPMMUHC08*/ + [213] = {0xFCF83578U, 0x00000002U}, /* SEC_MODID[213]:IPMMUHC09*/ + [214] = {0xFC883400U, 0x00000002U}, /* SEC_MODID[214]:ARIMP00*/ + [215] = {0xFC883404U, 0x00000002U}, /* SEC_MODID[215]:ARIMP01*/ + [216] = {0xFC883408U, 0x00000002U}, /* SEC_MODID[216]:ARIMP02*/ + [217] = {0xFC88340CU, 0x00000002U}, /* SEC_MODID[217]:ARIMP03*/ + [218] = {0xFC883410U, 0x00000002U}, /* SEC_MODID[218]:ARIMP04*/ + [219] = {0xFC883414U, 0x00000002U}, /* SEC_MODID[219]:AXIFBABUSIR0*/ + [220] = {0xFC883418U, 0x00000002U}, /* SEC_MODID[220]:AXIFBABUSIR1*/ + [221] = {0xFC88341CU, 0x00000002U}, /* SEC_MODID[221]:AXIFBABUSIR2*/ + [222] = {0xFC883420U, 0x00000002U}, /* SEC_MODID[222]:AXIFBABUSIR3*/ + [223] = {0xFC883428U, 0x00000002U}, /* SEC_MODID[223]:AXIIMP0*/ + [224] = {0xFC883434U, 0x00000002U}, /* SEC_MODID[224]:ARIMP05*/ + [225] = {0xFC883438U, 0x00000002U}, /* SEC_MODID[225]:ARIMP06*/ + [226] = {0xFC88343CU, 0x00000002U}, /* SEC_MODID[226]:ARIMP07*/ + [227] = {0xFC883440U, 0x00000002U}, /* SEC_MODID[227]:ARIMP08*/ + [228] = {0xFC883448U, 0x00000002U}, /* SEC_MODID[228]:ECMIR*/ + [229] = {0xFC88344CU, 0x00000002U}, /* SEC_MODID[229]:DSPPS*/ + [230] = {0xFC883450U, 0x00000002U}, /* SEC_MODID[230]:IPMMUIR1*/ + [231] = {0xFC883454U, 0x00000002U}, /* SEC_MODID[231]:IPMMUIR0*/ + [232] = {0xFC883458U, 0x00000002U}, /* SEC_MODID[232]:IPMMUIR10*/ + [233] = {0xFC88345CU, 0x00000002U}, /* SEC_MODID[233]:IPMMUIR11*/ + [234] = {0xFC883460U, 0x00000002U}, /* SEC_MODID[234]:IPMMUIR12*/ + [235] = {0xFC883464U, 0x00000002U}, /* SEC_MODID[235]:IPMMUIR13*/ + [236] = {0xFC883468U, 0x00000002U}, /* SEC_MODID[236]:IPMMUIR14*/ + [237] = {0xFC88346CU, 0x00000002U}, /* SEC_MODID[237]:IPMMUIR15*/ + [238] = {0xFC883470U, 0x00000002U}, /* SEC_MODID[238]:IPMMUIR2*/ + [239] = {0xFC883474U, 0x00000002U}, /* SEC_MODID[239]:IPMMUIR3*/ + [240] = {0xFC883478U, 0x00000002U}, /* SEC_MODID[240]:IPMMUIR4*/ + [241] = {0xFC88347CU, 0x00000002U}, /* SEC_MODID[241]:IPMMUIR5*/ + [242] = {0xFC883480U, 0x00000002U}, /* SEC_MODID[242]:IPMMUIR6*/ + [243] = {0xFC883484U, 0x00000002U}, /* SEC_MODID[243]:IPMMUIR7*/ + [244] = {0xFC883488U, 0x00000002U}, /* SEC_MODID[244]:IPMMUIR8*/ + [245] = {0xFC88348CU, 0x00000002U}, /* SEC_MODID[245]:IPMMUIR9*/ + [246] = {0xFC013400U, 0x00000002U}, /* SEC_MODID[246]:ARPV0*/ + [247] = {0xFC013404U, 0x00000002U}, /* SEC_MODID[247]:ARPV1*/ + [248] = {0xFC013408U, 0x00000002U}, /* SEC_MODID[248]:AXIRGXS*/ + [249] = {0xFC01340CU, 0x00000002U}, /* SEC_MODID[249]:ARPV2*/ + [250] = {0xFC013410U, 0x00000002U}, /* SEC_MODID[250]:ARPV3*/ + [251] = {0xFC013414U, 0x00000002U}, /* SEC_MODID[251]:ARPV4*/ + [252] = {0xFC013418U, 0x00000002U}, /* SEC_MODID[252]:ARPV5*/ + [253] = {0xFC01341CU, 0x00000002U}, /* SEC_MODID[253]:ARPV6*/ + [254] = {0xFC013420U, 0x00000002U}, /* SEC_MODID[254]:ARPV7*/ + [255] = {0xFC013424U, 0x00000002U}, /* SEC_MODID[255]:ARPV8*/ + [256] = {0xFC01342CU, 0x00000002U}, /* SEC_MODID[256]:ECM3DG*/ + [257] = {0xFC013430U, 0x00000002U}, /* SEC_MODID[257]:FBAPVC*/ + [258] = {0xFC013434U, 0x00000002U}, /* SEC_MODID[258]:FBAPVD0*/ + [259] = {0xFC013438U, 0x00000002U}, /* SEC_MODID[259]:FBAPVD1*/ + [260] = {0xFC01343CU, 0x00000002U}, /* SEC_MODID[260]:FBAPVD2*/ + [261] = {0xFC013440U, 0x00000002U}, /* SEC_MODID[261]:FBAPVE*/ + [262] = {0xFC013444U, 0x00000002U}, /* SEC_MODID[262]:IPMMUPV000*/ + [263] = {0xFC013448U, 0x00000002U}, /* SEC_MODID[263]:IPMMUPV001*/ + [264] = {0xFC01344CU, 0x00000002U}, /* SEC_MODID[264]:IPMMUPV010*/ + [265] = {0xFC013450U, 0x00000002U}, /* SEC_MODID[265]:IPMMUPV011*/ + [266] = {0xFC013454U, 0x00000002U}, /* SEC_MODID[266]:IPMMUPV012*/ + [267] = {0xFC013458U, 0x00000002U}, /* SEC_MODID[267]:IPMMUPV013*/ + [268] = {0xFC01345CU, 0x00000002U}, /* SEC_MODID[268]:IPMMUPV014*/ + [269] = {0xFC013460U, 0x00000002U}, /* SEC_MODID[269]:IPMMUPV015*/ + [270] = {0xFC013464U, 0x00000002U}, /* SEC_MODID[270]:IPMMUPV002*/ + [271] = {0xFC013468U, 0x00000002U}, /* SEC_MODID[271]:IPMMUPV003*/ + [272] = {0xFC01346CU, 0x00000002U}, /* SEC_MODID[272]:IPMMUPV004*/ + [273] = {0xFC013470U, 0x00000002U}, /* SEC_MODID[273]:IPMMUPV005*/ + [274] = {0xFC013474U, 0x00000002U}, /* SEC_MODID[274]:IPMMUPV006*/ + [275] = {0xFC013478U, 0x00000002U}, /* SEC_MODID[275]:IPMMUPV007*/ + [276] = {0xFC01347CU, 0x00000002U}, /* SEC_MODID[276]:IPMMUPV008*/ + [277] = {0xFC013480U, 0x00000002U}, /* SEC_MODID[277]:IPMMUPV009*/ + [278] = {0xFDC23400U, 0x00000002U}, /* SEC_MODID[278]:ARRC0*/ + [279] = {0xFDC23404U, 0x00000002U}, /* SEC_MODID[279]:ARRC1*/ + [280] = {0xFDC23408U, 0x00000002U}, /* SEC_MODID[280]:ARRC2*/ + [281] = {0xFDC2340CU, 0x00000002U}, /* SEC_MODID[281]:ARRC3*/ + [282] = {0xFDC23410U, 0x00000002U}, /* SEC_MODID[282]:ARRC4*/ + [283] = {0xFDC23414U, 0x00000002U}, /* SEC_MODID[283]:ARRC5*/ + [284] = {0xFDC23418U, 0x00000002U}, /* SEC_MODID[284]:ARRC6*/ + [285] = {0xFDC2341CU, 0x00000002U}, /* SEC_MODID[285]:ARRC7*/ + [286] = {0xFDC23420U, 0x00000002U}, /* SEC_MODID[286]:ARRC8*/ + [287] = {0xFDC23428U, 0x00000002U}, /* SEC_MODID[287]:ICUMX*/ + [288] = {0xFDC2342CU, 0x00000002U}, /* SEC_MODID[288]:ECMRC*/ + [289] = {0xFD433400U, 0x00000002U}, /* SEC_MODID[289]:DMAWCRC0*/ + [290] = {0xFD433404U, 0x00000002U}, /* SEC_MODID[290]:DMAWCRC1*/ + [291] = {0xFD433408U, 0x00000002U}, /* SEC_MODID[291]:DMAWCRC2*/ + [292] = {0xFD43340CU, 0x00000002U}, /* SEC_MODID[292]:DMAWCRC3*/ + [293] = {0xFD443400U, 0x00000002U}, /* SEC_MODID[293]:ARMREG00*/ + [294] = {0xFD443404U, 0x00000002U}, /* SEC_MODID[294]:ARMREG01*/ + [295] = {0xFD443408U, 0x00000002U}, /* SEC_MODID[295]:ARMREG10*/ + [296] = {0xFD44340CU, 0x00000002U}, /* SEC_MODID[296]:ARMREG11*/ + [297] = {0xFD443410U, 0x00000002U}, /* SEC_MODID[297]:ARMREG12*/ + [298] = {0xFD443414U, 0x00000000U}, /* SEC_MODID[298]:ARMREG13*/ + [299] = {0xFD443418U, 0x00000000U}, /* SEC_MODID[299]:ARMREG14*/ + [300] = {0xFD44341CU, 0x00000002U}, /* SEC_MODID[300]:AXICR52SS0*/ + [301] = {0xFD443420U, 0x00000002U}, /* SEC_MODID[301]:AXICSD0*/ + [302] = {0xFD443424U, 0x00000002U}, /* SEC_MODID[302]:AXIINTAP0*/ + [303] = {0xFD44342CU, 0x00000002U}, /* SEC_MODID[303]:AXISECROM*/ + [304] = {0xFD443430U, 0x00000002U}, /* SEC_MODID[304]:AXISYSRAM0*/ + [305] = {0xFD443434U, 0x00000002U}, /* SEC_MODID[305]:AXISYSRAM1*/ + [306] = {0xFD443438U, 0x00000002U}, /* SEC_MODID[306]:ARGREG15*/ + [307] = {0xFD44343CU, 0x00000002U}, /* SEC_MODID[307]:ARMREG2*/ + [308] = {0xFD443440U, 0x00000002U}, /* SEC_MODID[308]:ARMREG3*/ + [309] = {0xFD443444U, 0x00000002U}, /* SEC_MODID[309]:ARMREG4*/ + [310] = {0xFD443448U, 0x00000002U}, /* SEC_MODID[310]:ARMREG5*/ + [311] = {0xFD44344CU, 0x00000002U}, /* SEC_MODID[311]:ARMREG6*/ + [312] = {0xFD443450U, 0x00000002U}, /* SEC_MODID[312]:ARMREG7*/ + [313] = {0xFD443454U, 0x00000000U}, /* SEC_MODID[313]:ARMREG8*/ + [314] = {0xFD443458U, 0x00000000U}, /* SEC_MODID[314]:ARMREG9*/ + [315] = {0xFD44345CU, 0x00000002U}, /* SEC_MODID[315]:ARRD0*/ + [316] = {0xFD443460U, 0x00000002U}, /* SEC_MODID[316]:ARRD1*/ + [317] = {0xFD443464U, 0x00000002U}, /* SEC_MODID[317]:ARRD2*/ + [318] = {0xFD443468U, 0x00000002U}, /* SEC_MODID[318]:ARRD3*/ + [319] = {0xFD44346CU, 0x00000002U}, /* SEC_MODID[319]:ARRD4*/ + [320] = {0xFD443470U, 0x00000002U}, /* SEC_MODID[320]:ARRD5*/ + [321] = {0xFD443474U, 0x00000002U}, /* SEC_MODID[321]:ARRD6*/ + [322] = {0xFD443478U, 0x00000002U}, /* SEC_MODID[322]:ARRD7*/ + [323] = {0xFD44347CU, 0x00000002U}, /* SEC_MODID[323]:ARRD8*/ + [324] = {0xFD443480U, 0x00000002U}, /* SEC_MODID[324]:ARRT0*/ + [325] = {0xFD443484U, 0x00000002U}, /* SEC_MODID[325]:ARRT1*/ + [326] = {0xFD443488U, 0x00000002U}, /* SEC_MODID[326]:ARRT2*/ + [327] = {0xFD44348CU, 0x00000002U}, /* SEC_MODID[327]:ARRT3*/ + [328] = {0xFD443490U, 0x00000002U}, /* SEC_MODID[328]:ARRT4*/ + [329] = {0xFD443494U, 0x00000002U}, /* SEC_MODID[329]:ARRT5*/ + [330] = {0xFD443498U, 0x00000002U}, /* SEC_MODID[330]:ARRT6*/ + [331] = {0xFD44349CU, 0x00000002U}, /* SEC_MODID[331]:ARRT7*/ + [332] = {0xFD4434A0U, 0x00000002U}, /* SEC_MODID[332]:ARRT8*/ + [333] = {0xFD4434A4U, 0x00000002U}, /* SEC_MODID[333]:CKMRT*/ + [334] = {0xFD4434A8U, 0x00000002U}, /* SEC_MODID[334]:CRC0*/ + [335] = {0xFD4434ACU, 0x00000002U}, /* SEC_MODID[335]:CRC1*/ + [336] = {0xFD4434B0U, 0x00000002U}, /* SEC_MODID[336]:CRC2*/ + [337] = {0xFD4434B4U, 0x00000002U}, /* SEC_MODID[337]:CRC3*/ + [338] = {0xFD4434B8U, 0x00000002U}, /* SEC_MODID[338]:CSD*/ + [339] = {0xFD4434BCU, 0x00000002U}, /* SEC_MODID[339]:ECM*/ + [340] = {0xFD4434C0U, 0x00000002U}, /* SEC_MODID[340]:ECMRT*/ + [341] = {0xFD4434C4U, 0x00000002U}, /* SEC_MODID[341]:FBACR52*/ + [342] = {0xFD4434C8U, 0x00000002U}, /* SEC_MODID[342]:FBART*/ + [343] = {0xFD4434CCU, 0x00000002U}, /* SEC_MODID[343]:INTTP*/ + [344] = {0xFD4434D0U, 0x00000002U}, /* SEC_MODID[344]:IPMMURT000*/ + [345] = {0xFD4434D4U, 0x00000002U}, /* SEC_MODID[345]:IPMMURT100*/ + [346] = {0xFD4434D8U, 0x00000002U}, /* SEC_MODID[346]:KCRC4*/ + [347] = {0xFD4434DCU, 0x00000002U}, /* SEC_MODID[347]:KCRC5*/ + [348] = {0xFD4434E0U, 0x00000002U}, /* SEC_MODID[348]:KCRC6*/ + [349] = {0xFD4434E4U, 0x00000002U}, /* SEC_MODID[349]:KCRC7*/ + [350] = {0xFD4434E8U, 0x00000002U}, /* SEC_MODID[350]:MFI00*/ + [351] = {0xFD4434ECU, 0x00000002U}, /* SEC_MODID[351]:MFI01*/ + [352] = {0xFD4434F0U, 0x00000002U}, /* SEC_MODID[352]:MFI10*/ + [353] = {0xFD4434F4U, 0x00000002U}, /* SEC_MODID[353]:MFI02*/ + [354] = {0xFD4434F8U, 0x00000002U}, /* SEC_MODID[354]:MFI03*/ + [355] = {0xFD4434FCU, 0x00000002U}, /* SEC_MODID[355]:MFI04*/ + [356] = {0xFD443500U, 0x00000002U}, /* SEC_MODID[356]:MFI05*/ + [357] = {0xFD443504U, 0x00000002U}, /* SEC_MODID[357]:MFI06*/ + [358] = {0xFD443508U, 0x00000002U}, /* SEC_MODID[358]:MFI07*/ + [359] = {0xFD44350CU, 0x00000002U}, /* SEC_MODID[359]:MFI08*/ + [360] = {0xFD443510U, 0x00000002U}, /* SEC_MODID[360]:MFI09*/ + [361] = {0xFD443514U, 0x00000002U}, /* SEC_MODID[361]:MFI15*/ + [362] = {0xFD443518U, 0x00000002U}, /* SEC_MODID[362]:CKMCR52*/ + [363] = {0xFD44351CU, 0x00000002U}, /* SEC_MODID[363]:RTDM0P*/ + [364] = {0xFD443520U, 0x00000002U}, /* SEC_MODID[364]:ECMRD*/ + [365] = {0xFD443524U, 0x00000002U}, /* SEC_MODID[365]:RTDM1P*/ + [366] = {0xFD443530U, 0x00000002U}, /* SEC_MODID[366]:SYSRAM10*/ + [367] = {0xFD443538U, 0x00000000U}, /* SEC_MODID[367]:SYSRAM00*/ + [368] = {0xFD44353CU, 0x00000002U}, /* SEC_MODID[368]:TSIPL0*/ + [369] = {0xFD443540U, 0x00000002U}, /* SEC_MODID[369]:TSIPL1*/ + [370] = {0xFD443544U, 0x00000002U}, /* SEC_MODID[370]:TSIPL2*/ + [371] = {0xFD443548U, 0x00000002U}, /* SEC_MODID[371]:TSIPL3*/ + [372] = {0xFD44354CU, 0x00000002U}, /* SEC_MODID[372]:TSIPL4*/ + [373] = {0xFD443550U, 0x00000002U}, /* SEC_MODID[373]:TSIPL5*/ + [374] = {0xFD443554U, 0x00000002U}, /* SEC_MODID[374]:TSIPL6*/ + [375] = {0xFD443558U, 0x00000002U}, /* SEC_MODID[375]:TSIPL7*/ + [376] = {0xFD44355CU, 0x00000002U}, /* SEC_MODID[376]:WCRC0*/ + [377] = {0xFD443560U, 0x00000002U}, /* SEC_MODID[377]:WCRC1*/ + [378] = {0xFD443564U, 0x00000002U}, /* SEC_MODID[378]:WCRC2*/ + [379] = {0xFD443568U, 0x00000002U}, /* SEC_MODID[379]:WCRC3*/ + [380] = {0xFD443580U, 0x00000002U}, /* SEC_MODID[380]:MFI11*/ + [381] = {0xFD443584U, 0x00000002U}, /* SEC_MODID[381]:MFI12*/ + [382] = {0xFD443588U, 0x00000002U}, /* SEC_MODID[382]:MFI13*/ + [383] = {0xFD44358CU, 0x00000002U}, /* SEC_MODID[383]:MFI14*/ + [384] = {0xFD443590U, 0x00000002U}, /* SEC_MODID[384]:IPMMURT001*/ + [385] = {0xFD443594U, 0x00000002U}, /* SEC_MODID[385]:IPMMURT010*/ + [386] = {0xFD443598U, 0x00000002U}, /* SEC_MODID[386]:IPMMURT011*/ + [387] = {0xFD44359CU, 0x00000002U}, /* SEC_MODID[387]:IPMMURT012*/ + [388] = {0xFD4435A0U, 0x00000002U}, /* SEC_MODID[388]:IPMMURT013*/ + [389] = {0xFD4435A4U, 0x00000002U}, /* SEC_MODID[389]:IPMMURT014*/ + [390] = {0xFD4435A8U, 0x00000002U}, /* SEC_MODID[390]:IPMMURT015*/ + [391] = {0xFD4435ACU, 0x00000002U}, /* SEC_MODID[391]:IPMMURT002*/ + [392] = {0xFD4435B0U, 0x00000002U}, /* SEC_MODID[392]:IPMMURT003*/ + [393] = {0xFD4435B4U, 0x00000002U}, /* SEC_MODID[393]:IPMMURT004*/ + [394] = {0xFD4435B8U, 0x00000002U}, /* SEC_MODID[394]:IPMMURT005*/ + [395] = {0xFD4435BCU, 0x00000002U}, /* SEC_MODID[395]:IPMMURT006*/ + [396] = {0xFD4435C0U, 0x00000002U}, /* SEC_MODID[396]:IPMMURT007*/ + [397] = {0xFD4435C4U, 0x00000002U}, /* SEC_MODID[397]:IPMMURT008*/ + [398] = {0xFD4435C8U, 0x00000002U}, /* SEC_MODID[398]:IPMMURT009*/ + [399] = {0xFD4435CCU, 0x00000002U}, /* SEC_MODID[399]:IPKMURT101*/ + [400] = {0xFD4435D0U, 0x00000002U}, /* SEC_MODID[400]:IPMMURT110*/ + [401] = {0xFD4435D4U, 0x00000002U}, /* SEC_MODID[401]:IPMMURT111*/ + [402] = {0xFD4435D8U, 0x00000002U}, /* SEC_MODID[402]:IPMMURT112*/ + [403] = {0xFD4435DCU, 0x00000002U}, /* SEC_MODID[403]:IPMMURT113*/ + [404] = {0xFD4435E0U, 0x00000002U}, /* SEC_MODID[404]:IPMMURT114*/ + [405] = {0xFD4435E4U, 0x00000002U}, /* SEC_MODID[405]:IPMMURT115*/ + [406] = {0xFD4435E8U, 0x00000002U}, /* SEC_MODID[406]:IPMMURT102*/ + [407] = {0xFD4435ECU, 0x00000002U}, /* SEC_MODID[407]:IPMMURT103*/ + [408] = {0xFD4435F0U, 0x00000002U}, /* SEC_MODID[408]:IPMMURT104*/ + [409] = {0xFD4435F4U, 0x00000002U}, /* SEC_MODID[409]:IPMMURT105*/ + [410] = {0xFD4435F8U, 0x00000002U}, /* SEC_MODID[410]:IPMMURT106*/ + [411] = {0xFD4435FCU, 0x00000002U}, /* SEC_MODID[411]:IPMMURT107*/ + [412] = {0xFD443600U, 0x00000002U}, /* SEC_MODID[412]:RTDM000*/ + [413] = {0xFD443604U, 0x00000002U}, /* SEC_MODID[413]:RTDM001*/ + [414] = {0xFD443608U, 0x00000002U}, /* SEC_MODID[414]:RTDM010*/ + [415] = {0xFD44360CU, 0x00000002U}, /* SEC_MODID[415]:RTDM011*/ + [416] = {0xFD443610U, 0x00000002U}, /* SEC_MODID[416]:RTDM012*/ + [417] = {0xFD443614U, 0x00000002U}, /* SEC_MODID[417]:RTDM013*/ + [418] = {0xFD443618U, 0x00000002U}, /* SEC_MODID[418]:RTDM014*/ + [419] = {0xFD44361CU, 0x00000002U}, /* SEC_MODID[419]:RTDM015*/ + [420] = {0xFD443620U, 0x00000002U}, /* SEC_MODID[420]:RTDM002*/ + [421] = {0xFD443624U, 0x00000002U}, /* SEC_MODID[421]:RTDM003*/ + [422] = {0xFD443628U, 0x00000002U}, /* SEC_MODID[422]:RTDM004*/ + [423] = {0xFD44362CU, 0x00000002U}, /* SEC_MODID[423]:RTDM005*/ + [424] = {0xFD443630U, 0x00000002U}, /* SEC_MODID[424]:RTDM006*/ + [425] = {0xFD443634U, 0x00000002U}, /* SEC_MODID[425]:RTDM007*/ + [426] = {0xFD443638U, 0x00000002U}, /* SEC_MODID[426]:RTDM008*/ + [427] = {0xFD44363CU, 0x00000002U}, /* SEC_MODID[427]:RTDM009*/ + [428] = {0xFD443640U, 0x00000002U}, /* SEC_MODID[428]:RTDM100*/ + [429] = {0xFD443644U, 0x00000002U}, /* SEC_MODID[429]:RTDM101*/ + [430] = {0xFD443648U, 0x00000002U}, /* SEC_MODID[430]:RTDM110*/ + [431] = {0xFD44364CU, 0x00000002U}, /* SEC_MODID[431]:RTDM111*/ + [432] = {0xFD443650U, 0x00000002U}, /* SEC_MODID[432]:RTDM112*/ + [433] = {0xFD443654U, 0x00000002U}, /* SEC_MODID[433]:RTDM113*/ + [434] = {0xFD443658U, 0x00000002U}, /* SEC_MODID[434]:RTDM114*/ + [435] = {0xFD44365CU, 0x00000002U}, /* SEC_MODID[435]:RTDM115*/ + [436] = {0xFD443660U, 0x00000002U}, /* SEC_MODID[436]:RTDM102*/ + [437] = {0xFD443664U, 0x00000002U}, /* SEC_MODID[437]:RTDM103*/ + [438] = {0xFD443668U, 0x00000002U}, /* SEC_MODID[438]:RTDM104*/ + [439] = {0xFD44366CU, 0x00000002U}, /* SEC_MODID[439]:RTDM105*/ + [440] = {0xFD443670U, 0x00000002U}, /* SEC_MODID[440]:RTDM106*/ + [441] = {0xFD443674U, 0x00000002U}, /* SEC_MODID[441]:RTDM107*/ + [442] = {0xFD443678U, 0x00000002U}, /* SEC_MODID[442]:RTDM108*/ + [443] = {0xFD44367CU, 0x00000002U}, /* SEC_MODID[443]:RTDM109*/ + [444] = {0xFD443700U, 0x00000002U}, /* SEC_MODID[444]:IPMMURT108*/ + [445] = {0xFD443704U, 0x00000002U}, /* SEC_MODID[445]:IPMMURT109*/ + [446] = {0xFD443708U, 0x00000000U}, /* SEC_MODID[446]:SYSRAM01*/ + [447] = {0xFD44370CU, 0x00000002U}, /* SEC_MODID[447]:SYSRAM02*/ + [448] = {0xFD443710U, 0x00000000U}, /* SEC_MODID[448]:SYSRAM03*/ + [449] = {0xFD443714U, 0x00000000U}, /* SEC_MODID[449]:SYSRAM04*/ + [450] = {0xFD443718U, 0x00000000U}, /* SEC_MODID[450]:SYSRAM05*/ + [451] = {0xFD44371CU, 0x00000000U}, /* SEC_MODID[451]:SYSRAM06*/ + [452] = {0xFD443720U, 0x00000002U}, /* SEC_MODID[452]:SYSRAM07*/ + [453] = {0xFD443724U, 0x00000002U}, /* SEC_MODID[453]:SYSRAM11*/ + [454] = {0xFD443728U, 0x00000002U}, /* SEC_MODID[454]:SYSRAM12*/ + [455] = {0xFD44372CU, 0x00000002U}, /* SEC_MODID[455]:SYSRAM13*/ + [456] = {0xFD443730U, 0x00000002U}, /* SEC_MODID[456]:SYSRAM14*/ + [457] = {0xFD443734U, 0x00000002U}, /* SEC_MODID[457]:SYSRAM15*/ + [458] = {0xFD443738U, 0x00000002U}, /* SEC_MODID[458]:SYSRAM16*/ + [459] = {0xFD44373CU, 0x00000002U}, /* SEC_MODID[459]:SYSRAM17*/ + [460] = {0xFD443760U, 0x00000002U}, /* SEC_MODID[460]:BKBUF*/ + [461] = {0xFD443764U, 0x00000002U}, /* SEC_MODID[461]:AXICR52SS1*/ + [462] = {0xFD443768U, 0x00000002U}, /* SEC_MODID[462]:AXICR52SS2*/ + [463] = {0xFC863400U, 0x00000002U}, /* SEC_MODID[463]:ARSC0*/ + [464] = {0xFC863404U, 0x00000002U}, /* SEC_MODID[464]:ARSC1*/ + [465] = {0xFC863408U, 0x00000002U}, /* SEC_MODID[465]:ARSC2*/ + [466] = {0xFC86340CU, 0x00000002U}, /* SEC_MODID[466]:ARSC3*/ + [467] = {0xFC863410U, 0x00000002U}, /* SEC_MODID[467]:ARSC4*/ + [468] = {0xFC863414U, 0x00000002U}, /* SEC_MODID[468]:ARSC5*/ + [469] = {0xFC863418U, 0x00000002U}, /* SEC_MODID[469]:ARSC6*/ + [470] = {0xFC86341CU, 0x00000002U}, /* SEC_MODID[470]:ARSC7*/ + [471] = {0xFC863420U, 0x00000002U}, /* SEC_MODID[471]:ARSC8*/ + [472] = {0xFC863424U, 0x00000002U}, /* SEC_MODID[472]:ARSTM0*/ + [473] = {0xFC863428U, 0x00000002U}, /* SEC_MODID[473]:ARSTM1*/ + [474] = {0xFC86342CU, 0x00000002U}, /* SEC_MODID[474]:CSD1S*/ + [475] = {0xFC863430U, 0x00000002U}, /* SEC_MODID[475]:AXIFBABUSTOP0*/ + [476] = {0xFC863438U, 0x00000002U}, /* SEC_MODID[476]:ARSTM2*/ + [477] = {0xFC86343CU, 0x00000002U}, /* SEC_MODID[477]:ARSTM3*/ + [478] = {0xFC863440U, 0x00000002U}, /* SEC_MODID[478]:ARSTM4*/ + [479] = {0xFC863444U, 0x00000002U}, /* SEC_MODID[479]:ARSTM5*/ + [480] = {0xFC863448U, 0x00000002U}, /* SEC_MODID[480]:ARSTM6*/ + [481] = {0xFC86344CU, 0x00000002U}, /* SEC_MODID[481]:ARSTM7*/ + [482] = {0xFC863450U, 0x00000002U}, /* SEC_MODID[482]:ARSTM8*/ + [483] = {0xFC863454U, 0x00000002U}, /* SEC_MODID[483]:ECMTOP*/ + [484] = {0xFC863458U, 0x00000002U}, /* SEC_MODID[484]:FBA*/ + [485] = {0xFC86345CU, 0x00000002U}, /* SEC_MODID[485]:FBC*/ + [486] = {0xFC863434U, 0x00000002U}, /* SEC_MODID[486]:AXICCI00*/ + [487] = {0xFC863460U, 0x00000002U}, /* SEC_MODID[487]:AXICCI01*/ + [488] = {0xFC863464U, 0x00000002U}, /* SEC_MODID[488]:AXICCI10*/ + [489] = {0xFC863468U, 0x00000002U}, /* SEC_MODID[489]:AXICCI11*/ + [490] = {0xFC86346CU, 0x00000002U}, /* SEC_MODID[490]:AXICCI12*/ + [491] = {0xFC863470U, 0x00000002U}, /* SEC_MODID[491]:AXICCI13*/ + [492] = {0xFC863474U, 0x00000002U}, /* SEC_MODID[492]:AXICCI14*/ + [493] = {0xFC863478U, 0x00000002U}, /* SEC_MODID[493]:AXICCI15*/ + [494] = {0xFC86347CU, 0x00000002U}, /* SEC_MODID[494]:AXICCI2*/ + [495] = {0xFC863480U, 0x00000002U}, /* SEC_MODID[495]:AXICCI3*/ + [496] = {0xFC863484U, 0x00000002U}, /* SEC_MODID[496]:AXICCI4*/ + [497] = {0xFC863488U, 0x00000002U}, /* SEC_MODID[497]:AXICCI5*/ + [498] = {0xFC86348CU, 0x00000002U}, /* SEC_MODID[498]:AXICCI6*/ + [499] = {0xFC863490U, 0x00000002U}, /* SEC_MODID[499]:AXICCI7*/ + [500] = {0xFC863494U, 0x00000002U}, /* SEC_MODID[500]:AXICCI8*/ + [501] = {0xFC863498U, 0x00000002U}, /* SEC_MODID[501]:AXICCI9*/ + [502] = {0xFC8634A0U, 0x00000002U}, /* SEC_MODID[502]:ECMSTM*/ + [503] = {0xFCB83400U, 0x00000002U}, /* SEC_MODID[503]:DMASSI00*/ + [504] = {0xFCB83404U, 0x00000002U}, /* SEC_MODID[504]:DMASSI01*/ + [505] = {0xFCB83408U, 0x00000002U}, /* SEC_MODID[505]:DMASSI02*/ + [506] = {0xFCB8340CU, 0x00000002U}, /* SEC_MODID[506]:DMASSI03*/ + [507] = {0xFCB83410U, 0x00000002U}, /* SEC_MODID[507]:DMASSI04*/ + [508] = {0xFCB83414U, 0x00000002U}, /* SEC_MODID[508]:DMAI2C0*/ + [509] = {0xFCB83418U, 0x00000002U}, /* SEC_MODID[509]:DMAI2C1*/ + [510] = {0xFCB8341CU, 0x00000002U}, /* SEC_MODID[510]:DMAI2C2*/ + [511] = {0xFCB83420U, 0x00000002U}, /* SEC_MODID[511]:DMAI2C3*/ + [512] = {0xFCB8342CU, 0x00000002U}, /* SEC_MODID[512]:DMASSI05*/ + [513] = {0xFCB83430U, 0x00000002U}, /* SEC_MODID[513]:DMASSI06*/ + [514] = {0xFCB83434U, 0x00000002U}, /* SEC_MODID[514]:DMASSI07*/ + [515] = {0xFDDC3400U, 0x00000002U}, /* SEC_MODID[515]:ARMM*/ + [516] = {0xFDDC3404U, 0x00000002U}, /* SEC_MODID[516]:AXIARNMM*/ + [517] = {0xFDDC3408U, 0x00000002U}, /* SEC_MODID[517]:ARSM0*/ + [518] = {0xFDDC340CU, 0x00000002U}, /* SEC_MODID[518]:ARSM1*/ + [519] = {0xFDDC3410U, 0x00000002U}, /* SEC_MODID[519]:ARSM2*/ + [520] = {0xFDDC3414U, 0x00000002U}, /* SEC_MODID[520]:AXIQOS0*/ + [521] = {0xFDDC3418U, 0x00000002U}, /* SEC_MODID[521]:AXIQOS1*/ + [522] = {0xFDDC341CU, 0x00000002U}, /* SEC_MODID[522]:AXIQOS2*/ + [523] = {0xFDDC3420U, 0x00000002U}, /* SEC_MODID[523]:AXIQOS3*/ + [524] = {0xFDDC3424U, 0x00000002U}, /* SEC_MODID[524]:AXIQOS4*/ + [525] = {0xFDDC3428U, 0x00000002U}, /* SEC_MODID[525]:AXIQOS5*/ + [526] = {0xFDDC3434U, 0x00000002U}, /* SEC_MODID[526]:ARSM3*/ + [527] = {0xFDDC3438U, 0x00000002U}, /* SEC_MODID[527]:ARSM4*/ + [528] = {0xFDDC343CU, 0x00000002U}, /* SEC_MODID[528]:ARSM5*/ + [529] = {0xFDDC3440U, 0x00000002U}, /* SEC_MODID[529]:ARSM6*/ + [530] = {0xFDDC3444U, 0x00000002U}, /* SEC_MODID[530]:ARSM7*/ + [531] = {0xFDDC3448U, 0x00000002U}, /* SEC_MODID[531]:ARSM8*/ + [532] = {0xFDDC344CU, 0x00000000U}, /* SEC_MODID[532]:AXMM0*/ + [533] = {0xFDDC3450U, 0x00000000U}, /* SEC_MODID[533]:AXMM1*/ + [534] = {0xFDDC3454U, 0x00000002U}, /* SEC_MODID[534]:AXMMPMON*/ + [535] = {0xFDDC3458U, 0x00000002U}, /* SEC_MODID[535]:CKMMM*/ + [536] = {0xFDDC345CU, 0x00000002U}, /* SEC_MODID[536]:ECMMM*/ + [537] = {0xFDDC3460U, 0x00000002U}, /* SEC_MODID[537]:FBADBSC0*/ + [538] = {0xFDDC3468U, 0x00000002U}, /* SEC_MODID[538]:FBAMM*/ + [539] = {0xFDDC346CU, 0x00000002U}, /* SEC_MODID[539]:IPMMUMM00*/ + [540] = {0xFDDC3470U, 0x00000002U}, /* SEC_MODID[540]:DBS0A0*/ + [541] = {0xFDDC3474U, 0x00000002U}, /* SEC_MODID[541]:DBS0A1*/ + [542] = {0xFDDC3484U, 0x00000002U}, /* SEC_MODID[542]:FCPRC*/ + [543] = {0xFDDC3488U, 0x00000002U}, /* SEC_MODID[543]:DBS0D0*/ + [544] = {0xFDDC348CU, 0x00000002U}, /* SEC_MODID[544]:DBS0D1*/ + [545] = {0xFDDC3498U, 0x00000002U}, /* SEC_MODID[545]:FBADDR*/ + [546] = {0xFDDC349CU, 0x00000002U}, /* SEC_MODID[546]:IPMMUMM01*/ + [547] = {0xFDDC34A0U, 0x00000002U}, /* SEC_MODID[547]:IPMMUMM10*/ + [548] = {0xFDDC34A4U, 0x00000002U}, /* SEC_MODID[548]:IPMMUMM11*/ + [549] = {0xFDDC34A8U, 0x00000002U}, /* SEC_MODID[549]:IPMMUMM12*/ + [550] = {0xFDDC34ACU, 0x00000002U}, /* SEC_MODID[550]:IPMMUMM13*/ + [551] = {0xFDDC34B0U, 0x00000002U}, /* SEC_MODID[551]:IPMMUMM14*/ + [552] = {0xFDDC34B4U, 0x00000002U}, /* SEC_MODID[552]:IPMMUMM15*/ + [553] = {0xFDDC34B8U, 0x00000002U}, /* SEC_MODID[553]:IPMMUMM02*/ + [554] = {0xFDDC34BCU, 0x00000002U}, /* SEC_MODID[554]:IPMMUMM03*/ + [555] = {0xFDDC34C0U, 0x00000002U}, /* SEC_MODID[555]:IPMMUMM04*/ + [556] = {0xFDDC34C4U, 0x00000002U}, /* SEC_MODID[556]:IPMMUMM05*/ + [557] = {0xFDDC34C8U, 0x00000002U}, /* SEC_MODID[557]:IPMMUMM06*/ + [558] = {0xFDDC34CCU, 0x00000002U}, /* SEC_MODID[558]:IPMMUMM07*/ + [559] = {0xFDDC34D0U, 0x00000002U}, /* SEC_MODID[559]:IPMMUMM08*/ + [560] = {0xFDDC34D4U, 0x00000002U}, /* SEC_MODID[560]:IPMMUMM09*/ + [561] = {0xFC803400U, 0x00000002U}, /* SEC_MODID[561]:ARSN0*/ + [562] = {0xFC803404U, 0x00000002U}, /* SEC_MODID[562]:ARSN1*/ + [563] = {0xFC803408U, 0x00000002U}, /* SEC_MODID[563]:ARSN2*/ + [564] = {0xFC80340CU, 0x00000002U}, /* SEC_MODID[564]:ARSN3*/ + [565] = {0xFC803410U, 0x00000002U}, /* SEC_MODID[565]:ARSN4*/ + [566] = {0xFC803414U, 0x00000002U}, /* SEC_MODID[566]:ARSN5*/ + [567] = {0xFC803418U, 0x00000002U}, /* SEC_MODID[567]:ARSN6*/ + [568] = {0xFC80341CU, 0x00000002U}, /* SEC_MODID[568]:ARSN7*/ + [569] = {0xFC803420U, 0x00000002U}, /* SEC_MODID[569]:ARSN8*/ + [570] = {0xFC803424U, 0x00000002U}, /* SEC_MODID[570]:ECMTOP3*/ + [571] = {0xFCB53400U, 0x00000002U}, /* SEC_MODID[571]:ARSD00*/ + [572] = {0xFCB53404U, 0x00000002U}, /* SEC_MODID[572]:ARSD01*/ + [573] = {0xFCB53408U, 0x00000002U}, /* SEC_MODID[573]:ARSD02*/ + [574] = {0xFCB5340CU, 0x00000002U}, /* SEC_MODID[574]:ARSD03*/ + [575] = {0xFCB53410U, 0x00000002U}, /* SEC_MODID[575]:ARSD04*/ + [576] = {0xFCB53414U, 0x00000002U}, /* SEC_MODID[576]:ARSD05*/ + [577] = {0xFCB53418U, 0x00000002U}, /* SEC_MODID[577]:ARSD06*/ + [578] = {0xFCB5341CU, 0x00000002U}, /* SEC_MODID[578]:AXIFRAY*/ + [579] = {0xFCB53428U, 0x00000002U}, /* SEC_MODID[579]:AXIRPC*/ + [580] = {0xFCB5342CU, 0x00000002U}, /* SEC_MODID[580]:AXISDHI0*/ + [581] = {0xFCB53430U, 0x00000002U}, /* SEC_MODID[581]:ARSD07*/ + [582] = {0xFCB53434U, 0x00000002U}, /* SEC_MODID[582]:ARSD08*/ + [583] = {0xFCB53438U, 0x00000002U}, /* SEC_MODID[583]:ARSP00*/ + [584] = {0xFCB5343CU, 0x00000002U}, /* SEC_MODID[584]:ARSP01*/ + [585] = {0xFCB53440U, 0x00000002U}, /* SEC_MODID[585]:ARSP02*/ + [586] = {0xFCB53444U, 0x00000002U}, /* SEC_MODID[586]:ARSP03*/ + [587] = {0xFCB53448U, 0x00000002U}, /* SEC_MODID[587]:ARSP04*/ + [588] = {0xFCB5344CU, 0x00000002U}, /* SEC_MODID[588]:ARSP05*/ + [589] = {0xFCB53450U, 0x00000002U}, /* SEC_MODID[589]:ARSP06*/ + [590] = {0xFCB53454U, 0x00000002U}, /* SEC_MODID[590]:ARSP07*/ + [591] = {0xFCB53458U, 0x00000002U}, /* SEC_MODID[591]:ARSP08*/ + [592] = {0xFCB5345CU, 0x00000002U}, /* SEC_MODID[592]:IPMMUDS001*/ + [593] = {0xFCB53460U, 0x00000002U}, /* SEC_MODID[593]:CKMPER0*/ + [594] = {0xFCB53464U, 0x00000002U}, /* SEC_MODID[594]:ECMPER0*/ + [595] = {0xFCB53468U, 0x00000002U}, /* SEC_MODID[595]:FBAPER0*/ + [596] = {0xFCB5346CU, 0x00000002U}, /* SEC_MODID[596]:FSO0*/ + [597] = {0xFCB53470U, 0x00000002U}, /* SEC_MODID[597]:FSO1*/ + [598] = {0xFCB53474U, 0x00000002U}, /* SEC_MODID[598]:FSO10*/ + [599] = {0xFCB53478U, 0x00000002U}, /* SEC_MODID[599]:FSO2*/ + [600] = {0xFCB5347CU, 0x00000002U}, /* SEC_MODID[600]:FSO3*/ + [601] = {0xFCB53480U, 0x00000002U}, /* SEC_MODID[601]:FSO4*/ + [602] = {0xFCB53484U, 0x00000002U}, /* SEC_MODID[602]:FSO5*/ + [603] = {0xFCB53488U, 0x00000002U}, /* SEC_MODID[603]:FSO6*/ + [604] = {0xFCB5348CU, 0x00000002U}, /* SEC_MODID[604]:FSO7*/ + [605] = {0xFCB53490U, 0x00000002U}, /* SEC_MODID[605]:FSO8*/ + [606] = {0xFCB53494U, 0x00000002U}, /* SEC_MODID[606]:FSO9*/ + [607] = {0xFCB53498U, 0x00000002U}, /* SEC_MODID[607]:ADG*/ + [608] = {0xFCB5349CU, 0x00000002U}, /* SEC_MODID[608]:ECMSD0*/ + [609] = {0xFCB534A0U, 0x00000002U}, /* SEC_MODID[609]:IPMMUDS010*/ + [610] = {0xFCB534A4U, 0x00000002U}, /* SEC_MODID[610]:IPMMUDS011*/ + [611] = {0xFCB534A8U, 0x00000002U}, /* SEC_MODID[611]:I2C0*/ + [612] = {0xFCB534ACU, 0x00000002U}, /* SEC_MODID[612]:I2C1*/ + [613] = {0xFCB534B0U, 0x00000002U}, /* SEC_MODID[613]:I2C2*/ + [614] = {0xFCB534B4U, 0x00000002U}, /* SEC_MODID[614]:I2C3*/ + [615] = {0xFCB534C0U, 0x00000002U}, /* SEC_MODID[615]:IPMMUDS012*/ + [616] = {0xFCB534C8U, 0x00000002U}, /* SEC_MODID[616]:IPMMUDS000*/ + [617] = {0xFCB534CCU, 0x00000002U}, /* SEC_MODID[617]:IPMMUDS013*/ + [618] = {0xFCB534D0U, 0x00000002U}, /* SEC_MODID[618]:IPMMUDS014*/ + [619] = {0xFCB534D4U, 0x00000002U}, /* SEC_MODID[619]:IPMMUDS015*/ + [620] = {0xFCB534D8U, 0x00000002U}, /* SEC_MODID[620]:IPMMUDS002*/ + [621] = {0xFCB534DCU, 0x00000002U}, /* SEC_MODID[621]:IPMMUDS003*/ + [622] = {0xFCB534E0U, 0x00000002U}, /* SEC_MODID[622]:IPMMUDS004*/ + [623] = {0xFCB534E4U, 0x00000002U}, /* SEC_MODID[623]:IPMMUDS005*/ + [624] = {0xFCB534E8U, 0x00000002U}, /* SEC_MODID[624]:SSI*/ + [625] = {0xFCB534ECU, 0x00000002U}, /* SEC_MODID[625]:IPMMUDS006*/ + [626] = {0xFCB534F0U, 0x00000002U}, /* SEC_MODID[626]:IPMMUDS007*/ + [627] = {0xFCB534F4U, 0x00000002U}, /* SEC_MODID[627]:SYDM1P*/ + [628] = {0xFCB534F8U, 0x00000002U}, /* SEC_MODID[628]:IPMMUDS008*/ + [629] = {0xFCB534FCU, 0x00000002U}, /* SEC_MODID[629]:SYDM2P*/ + [630] = {0xFCB53500U, 0x00000002U}, /* SEC_MODID[630]:IPMMUDS009*/ + [631] = {0xFCB53640U, 0x00000002U}, /* SEC_MODID[631]:SYDM100*/ + [632] = {0xFCB53644U, 0x00000002U}, /* SEC_MODID[632]:SYDM101*/ + [633] = {0xFCB53648U, 0x00000002U}, /* SEC_MODID[633]:SYDM110*/ + [634] = {0xFCB5364CU, 0x00000002U}, /* SEC_MODID[634]:SYDM111*/ + [635] = {0xFCB53650U, 0x00000002U}, /* SEC_MODID[635]:SYDM112*/ + [636] = {0xFCB53654U, 0x00000002U}, /* SEC_MODID[636]:SYDM113*/ + [637] = {0xFCB53658U, 0x00000002U}, /* SEC_MODID[637]:SYDM114*/ + [638] = {0xFCB5365CU, 0x00000002U}, /* SEC_MODID[638]:SYDM115*/ + [639] = {0xFCB53660U, 0x00000002U}, /* SEC_MODID[639]:SYDM102*/ + [640] = {0xFCB53664U, 0x00000002U}, /* SEC_MODID[640]:SYDM103*/ + [641] = {0xFCB53668U, 0x00000002U}, /* SEC_MODID[641]:SYDM104*/ + [642] = {0xFCB5366CU, 0x00000002U}, /* SEC_MODID[642]:SYDM105*/ + [643] = {0xFCB53670U, 0x00000002U}, /* SEC_MODID[643]:SYDM106*/ + [644] = {0xFCB53674U, 0x00000002U}, /* SEC_MODID[644]:SYDM107*/ + [645] = {0xFCB53678U, 0x00000002U}, /* SEC_MODID[645]:SYDM108*/ + [646] = {0xFCB5367CU, 0x00000002U}, /* SEC_MODID[646]:SYDM109*/ + [647] = {0xFCB53680U, 0x00000002U}, /* SEC_MODID[647]:SYDM200*/ + [648] = {0xFCB53684U, 0x00000002U}, /* SEC_MODID[648]:SYDM201*/ + [649] = {0xFCB53688U, 0x00000002U}, /* SEC_MODID[649]:SYDM210*/ + [650] = {0xFCB5368CU, 0x00000002U}, /* SEC_MODID[650]:SYDM211*/ + [651] = {0xFCB53690U, 0x00000002U}, /* SEC_MODID[651]:SYDM212*/ + [652] = {0xFCB53694U, 0x00000002U}, /* SEC_MODID[652]:SYDM213*/ + [653] = {0xFCB53698U, 0x00000002U}, /* SEC_MODID[653]:SYDM214*/ + [654] = {0xFCB5369CU, 0x00000002U}, /* SEC_MODID[654]:SYDM215*/ + [655] = {0xFCB536A0U, 0x00000002U}, /* SEC_MODID[655]:SYDM202*/ + [656] = {0xFCB536A4U, 0x00000002U}, /* SEC_MODID[656]:SYDM203*/ + [657] = {0xFCB536A8U, 0x00000002U}, /* SEC_MODID[657]:SYDM204*/ + [658] = {0xFCB536ACU, 0x00000002U}, /* SEC_MODID[658]:SYDM205*/ + [659] = {0xFCB536B0U, 0x00000002U}, /* SEC_MODID[659]:SYDM206*/ + [660] = {0xFCB536B4U, 0x00000002U}, /* SEC_MODID[660]:SYDM207*/ + [661] = {0xFCB536B8U, 0x00000002U}, /* SEC_MODID[661]:SYDM208*/ + [662] = {0xFCB536BCU, 0x00000002U}, /* SEC_MODID[662]:SYDM209*/ + [663] = {0xFC683400U, 0x00000002U}, /* SEC_MODID[663]:ARVC0*/ + [664] = {0xFC683404U, 0x00000002U}, /* SEC_MODID[664]:ARVC1*/ + [665] = {0xFC683408U, 0x00000002U}, /* SEC_MODID[665]:ARVC2*/ + [666] = {0xFC68340CU, 0x00000002U}, /* SEC_MODID[666]:ARVC3*/ + [667] = {0xFC683410U, 0x00000002U}, /* SEC_MODID[667]:AXIFBABUSVC*/ + [668] = {0xFC683414U, 0x00000002U}, /* SEC_MODID[668]:ARVC4*/ + [669] = {0xFC683418U, 0x00000002U}, /* SEC_MODID[669]:ARVC5*/ + [670] = {0xFC68341CU, 0x00000002U}, /* SEC_MODID[670]:ARVC6*/ + [671] = {0xFC683420U, 0x00000002U}, /* SEC_MODID[671]:ARVC7*/ + [672] = {0xFC683424U, 0x00000002U}, /* SEC_MODID[672]:ARVC8*/ + [673] = {0xFC68342CU, 0x00000002U}, /* SEC_MODID[673]:ECMVC0*/ + [674] = {0xFC683434U, 0x00000002U}, /* SEC_MODID[674]:IMR0*/ + [675] = {0xFC683438U, 0x00000002U}, /* SEC_MODID[675]:IMR1*/ + [676] = {0xFC68343CU, 0x00000002U}, /* SEC_MODID[676]:IPMMUVC01*/ + [677] = {0xFC683440U, 0x00000002U}, /* SEC_MODID[677]:IPMMUVC10*/ + [678] = {0xFC683444U, 0x00000002U}, /* SEC_MODID[678]:IMS0*/ + [679] = {0xFC683448U, 0x00000002U}, /* SEC_MODID[679]:IMS1*/ + [680] = {0xFC68344CU, 0x00000002U}, /* SEC_MODID[680]:IPMMUVC00*/ + [681] = {0xFC683450U, 0x00000002U}, /* SEC_MODID[681]:IPMMUVC11*/ + [682] = {0xFC683454U, 0x00000002U}, /* SEC_MODID[682]:IPMMUVC12*/ + [683] = {0xFC683458U, 0x00000002U}, /* SEC_MODID[683]:IPMMUVC13*/ + [684] = {0xFC68345CU, 0x00000002U}, /* SEC_MODID[684]:IPMMUVC14*/ + [685] = {0xFC683460U, 0x00000002U}, /* SEC_MODID[685]:IPMMUVC15*/ + [686] = {0xFC683464U, 0x00000002U}, /* SEC_MODID[686]:IPMMUVC02*/ + [687] = {0xFC683468U, 0x00000002U}, /* SEC_MODID[687]:IPMMUVC03*/ + [688] = {0xFC68346CU, 0x00000002U}, /* SEC_MODID[688]:IPMMUVC04*/ + [689] = {0xFC683470U, 0x00000002U}, /* SEC_MODID[689]:IPMMUVC05*/ + [690] = {0xFC683474U, 0x00000002U}, /* SEC_MODID[690]:IPMMUVC06*/ + [691] = {0xFC683478U, 0x00000002U}, /* SEC_MODID[691]:IPMMUVC07*/ + [692] = {0xFC68347CU, 0x00000002U}, /* SEC_MODID[692]:IPMMUVC08*/ + [693] = {0xFC683480U, 0x00000002U}, /* SEC_MODID[693]:IPMMUVC09*/ + [694] = {0xFC683484U, 0x00000002U}, /* SEC_MODID[694]:IV1ES*/ + [695] = {0xFEBE3400U, 0x00000002U}, /* SEC_MODID[695]:CSITOP0*/ + [696] = {0xFEBE3404U, 0x00000002U}, /* SEC_MODID[696]:ARVI10*/ + [697] = {0xFEBE3408U, 0x00000002U}, /* SEC_MODID[697]:ARVI11*/ + [698] = {0xFEBE340CU, 0x00000002U}, /* SEC_MODID[698]:ARVI12*/ + [699] = {0xFEBE3410U, 0x00000002U}, /* SEC_MODID[699]:ARVI13*/ + [700] = {0xFEBE3414U, 0x00000002U}, /* SEC_MODID[700]:ARVI14*/ + [701] = {0xFEBE3418U, 0x00000002U}, /* SEC_MODID[701]:ARVI15*/ + [702] = {0xFEBE341CU, 0x00000002U}, /* SEC_MODID[702]:ARVI16*/ + [703] = {0xFEBE3420U, 0x00000002U}, /* SEC_MODID[703]:ARVI17*/ + [704] = {0xFEBE3424U, 0x00000002U}, /* SEC_MODID[704]:ARVI18*/ + [705] = {0xFEBE342CU, 0x00000002U}, /* SEC_MODID[705]:CSITOP1*/ + [706] = {0xFEBE3434U, 0x00000002U}, /* SEC_MODID[706]:DSITLINK0*/ + [707] = {0xFEBE343CU, 0x00000002U}, /* SEC_MODID[707]:ECMVIO1*/ + [708] = {0xFEBE3444U, 0x00000002U}, /* SEC_MODID[708]:IPMMUVI001*/ + [709] = {0xFEBE3448U, 0x00000002U}, /* SEC_MODID[709]:FCPVX0*/ + [710] = {0xFEBE3458U, 0x00000002U}, /* SEC_MODID[710]:IPMMUVI000*/ + [711] = {0xFEBE345CU, 0x00000002U}, /* SEC_MODID[711]:IPMMUVI100*/ + [712] = {0xFEBE3460U, 0x00000002U}, /* SEC_MODID[712]:IPMMUVI010*/ + [713] = {0xFEBE3464U, 0x00000002U}, /* SEC_MODID[713]:IPMMUVI011*/ + [714] = {0xFEBE3468U, 0x00000002U}, /* SEC_MODID[714]:VSPX0*/ + [715] = {0xFEBE3478U, 0x00000002U}, /* SEC_MODID[715]:IPMMUVI012*/ + [716] = {0xFEBE347CU, 0x00000002U}, /* SEC_MODID[716]:IPMMUVI013*/ + [717] = {0xFEBE3480U, 0x00000002U}, /* SEC_MODID[717]:IPMMUVI014*/ + [718] = {0xFEBE3484U, 0x00000002U}, /* SEC_MODID[718]:IPMMUVI015*/ + [719] = {0xFEBE3488U, 0x00000002U}, /* SEC_MODID[719]:IPMMUVI002*/ + [720] = {0xFEBE348CU, 0x00000002U}, /* SEC_MODID[720]:IPMMUVI003*/ + [721] = {0xFEBE3490U, 0x00000002U}, /* SEC_MODID[721]:IPMMUVI004*/ + [722] = {0xFEBE3494U, 0x00000002U}, /* SEC_MODID[722]:IPMMUVI005*/ + [723] = {0xFEBE3498U, 0x00000002U}, /* SEC_MODID[723]:IPMMUVI006*/ + [724] = {0xFEBE349CU, 0x00000002U}, /* SEC_MODID[724]:IPMMUVI007*/ + [725] = {0xFEBE34A0U, 0x00000002U}, /* SEC_MODID[725]:IPMMUVI008*/ + [726] = {0xFEBE34A4U, 0x00000002U}, /* SEC_MODID[726]:IPMMUVI009*/ + [727] = {0xFEBE34A8U, 0x00000002U}, /* SEC_MODID[727]:IPMMUVI101*/ + [728] = {0xFEBE34ACU, 0x00000002U}, /* SEC_MODID[728]:IPMMUVI110*/ + [729] = {0xFEBE34B0U, 0x00000002U}, /* SEC_MODID[729]:IPMMUVI111*/ + [730] = {0xFEBE34B4U, 0x00000002U}, /* SEC_MODID[730]:IPMMUVI112*/ + [731] = {0xFEBE34B8U, 0x00000002U}, /* SEC_MODID[731]:IPMMUVI113*/ + [732] = {0xFEBE34BCU, 0x00000002U}, /* SEC_MODID[732]:IPMMUVI114*/ + [733] = {0xFEBE34C0U, 0x00000002U}, /* SEC_MODID[733]:IPMMUVI115*/ + [734] = {0xFEBE34C4U, 0x00000002U}, /* SEC_MODID[734]:IPMMUVI102*/ + [735] = {0xFEBE34C8U, 0x00000002U}, /* SEC_MODID[735]:IPMMUVI103*/ + [736] = {0xFEBE34CCU, 0x00000002U}, /* SEC_MODID[736]:IPMMUVI104*/ + [737] = {0xFEBE34D0U, 0x00000002U}, /* SEC_MODID[737]:IPMMUVI105*/ + [738] = {0xFEBE34D4U, 0x00000002U}, /* SEC_MODID[738]:IPMMUVI106*/ + [739] = {0xFEBE34D8U, 0x00000002U}, /* SEC_MODID[739]:IPMMUVI107*/ + [740] = {0xFEBE34DCU, 0x00000002U}, /* SEC_MODID[740]:IPMMUVI108*/ + [741] = {0xFEBE34E0U, 0x00000002U}, /* SEC_MODID[741]:IPMMUVI109*/ + [742] = {0xFEBE3504U, 0x00000002U}, /* SEC_MODID[742]:AXIFBABUSVIO*/ + [743] = {0xFEBF3400U, 0x00000002U}, /* SEC_MODID[743]:ARVI0*/ + [744] = {0xFEBF3404U, 0x00000002U}, /* SEC_MODID[744]:ARVI1*/ + [745] = {0xFEBF3408U, 0x00000002U}, /* SEC_MODID[745]:ARVI2*/ + [746] = {0xFEBF340CU, 0x00000002U}, /* SEC_MODID[746]:ARVI3*/ + [747] = {0xFEBF3410U, 0x00000002U}, /* SEC_MODID[747]:ARVI4*/ + [748] = {0xFEBF3414U, 0x00000002U}, /* SEC_MODID[748]:ARVI5*/ + [749] = {0xFEBF3418U, 0x00000002U}, /* SEC_MODID[749]:ARVI6*/ + [750] = {0xFEBF341CU, 0x00000002U}, /* SEC_MODID[750]:ARVI7*/ + [751] = {0xFEBF3420U, 0x00000002U}, /* SEC_MODID[751]:ARVI8*/ + [752] = {0xFEBF3424U, 0x00000002U}, /* SEC_MODID[752]:ECMVIO0*/ + [753] = {0xFEBF3428U, 0x00000002U}, /* SEC_MODID[753]:ISP0*/ + [754] = {0xFEBF342CU, 0x00000002U}, /* SEC_MODID[754]:ISP0CORE*/ + [755] = {0xFEBF3430U, 0x00000002U}, /* SEC_MODID[755]:ISP1*/ + [756] = {0xFEBF3454U, 0x00000002U}, /* SEC_MODID[756]:VIN00*/ + [757] = {0xFEBF3458U, 0x00000002U}, /* SEC_MODID[757]:VIN01*/ + [758] = {0xFEBF345CU, 0x00000002U}, /* SEC_MODID[758]:VIN02*/ + [759] = {0xFEBF3460U, 0x00000002U}, /* SEC_MODID[759]:VIN03*/ + [760] = {0xFEBF3464U, 0x00000002U}, /* SEC_MODID[760]:VIN04*/ + [761] = {0xFEBF3468U, 0x00000002U}, /* SEC_MODID[761]:VIN05*/ + [762] = {0xFEBF346CU, 0x00000002U}, /* SEC_MODID[762]:VIN06*/ + [763] = {0xFEBF3470U, 0x00000002U}, /* SEC_MODID[763]:VIN07*/ + [764] = {0xFEBF3474U, 0x00000002U}, /* SEC_MODID[764]:VIN10*/ + [765] = {0xFEBF3478U, 0x00000002U}, /* SEC_MODID[765]:VIN11*/ + [766] = {0xFEBF347CU, 0x00000002U}, /* SEC_MODID[766]:VIN12*/ + [767] = {0xFEBF3480U, 0x00000002U}, /* SEC_MODID[767]:VIN13*/ + [768] = {0xFEBF3484U, 0x00000002U}, /* SEC_MODID[768]:VIN14*/ + [769] = {0xFEBF3488U, 0x00000002U}, /* SEC_MODID[769]:VIN15*/ + [770] = {0xFEBF348CU, 0x00000002U}, /* SEC_MODID[770]:VIN16*/ + [771] = {0xFEBF3490U, 0x00000002U}, /* SEC_MODID[771]:VIN17*/ + [772] = {0xFC313400U, 0x00000002U}, /* SEC_MODID[772]:ARVIP00*/ + [773] = {0xFC313404U, 0x00000002U}, /* SEC_MODID[773]:ARVIP01*/ + [774] = {0xFC313408U, 0x00000002U}, /* SEC_MODID[774]:ARVIP02*/ + [775] = {0xFC31340CU, 0x00000002U}, /* SEC_MODID[775]:ARVIP03*/ + [776] = {0xFC313410U, 0x00000002U}, /* SEC_MODID[776]:AXIFBABUSVIP0*/ + [777] = {0xFC313414U, 0x00000002U}, /* SEC_MODID[777]:ARVIP04*/ + [778] = {0xFC313418U, 0x00000002U}, /* SEC_MODID[778]:ARVIP05*/ + [779] = {0xFC31341CU, 0x00000002U}, /* SEC_MODID[779]:ARVIP06*/ + [780] = {0xFC313420U, 0x00000002U}, /* SEC_MODID[780]:ARVIP07*/ + [781] = {0xFC313424U, 0x00000002U}, /* SEC_MODID[781]:ARVIP08*/ + [782] = {0xFC31342CU, 0x00000002U}, /* SEC_MODID[782]:ECMVIP0*/ + [783] = {0xFC313430U, 0x00000002U}, /* SEC_MODID[783]:IPMMUVIP000*/ + [784] = {0xFC313438U, 0x00000002U}, /* SEC_MODID[784]:SMPO0*/ + [785] = {0xFC31343CU, 0x00000002U}, /* SEC_MODID[785]:SMPS0*/ + [786] = {0xFC313440U, 0x00000002U}, /* SEC_MODID[786]:UMFL0*/ + [787] = {0xFC313444U, 0x00000002U}, /* SEC_MODID[787]:IPMMUVIP001*/ + [788] = {0xFC313448U, 0x00000002U}, /* SEC_MODID[788]:IPMMUVIP010*/ + [789] = {0xFC31344CU, 0x00000002U}, /* SEC_MODID[789]:IPMMUVIP011*/ + [790] = {0xFC313450U, 0x00000002U}, /* SEC_MODID[790]:UMFL0M_W*/ + [791] = {0xFC313454U, 0x00000002U}, /* SEC_MODID[791]:IPMMUVIP012*/ + [792] = {0xFC313458U, 0x00000002U}, /* SEC_MODID[792]:IPMMUVIP013*/ + [793] = {0xFC31345CU, 0x00000002U}, /* SEC_MODID[793]:IPMMUVIP014*/ + [794] = {0xFC313460U, 0x00000002U}, /* SEC_MODID[794]:IPMMUVIP015*/ + [795] = {0xFC313464U, 0x00000002U}, /* SEC_MODID[795]:IPMMUVIP002*/ + [796] = {0xFC313468U, 0x00000002U}, /* SEC_MODID[796]:IPMMUVIP003*/ + [797] = {0xFC31346CU, 0x00000002U}, /* SEC_MODID[797]:IPMMUVIP004*/ + [798] = {0xFC313470U, 0x00000002U}, /* SEC_MODID[798]:IPMMUVIP005*/ + [799] = {0xFC313474U, 0x00000002U}, /* SEC_MODID[799]:IPMMUVIP006*/ + [800] = {0xFC313478U, 0x00000002U}, /* SEC_MODID[800]:IPMMUVIP007*/ + [801] = {0xFC31347CU, 0x00000002U}, /* SEC_MODID[801]:IPMMUVIP008*/ + [802] = {0xFC313480U, 0x00000002U}, /* SEC_MODID[802]:IPMMUVIP009*/ + [803] = {0xFC8834A0U, 0x00000002U}, /* SEC_MODID[803]:ARDSP0*/ + [804] = {0xFC8834A4U, 0x00000002U}, /* SEC_MODID[804]:ARDSP1*/ + [805] = {0xFC8834A8U, 0x00000002U}, /* SEC_MODID[805]:ARDSP2*/ + [806] = {0xFC8834ACU, 0x00000002U}, /* SEC_MODID[806]:ARDSP3*/ + [807] = {0xFC8834B0U, 0x00000002U}, /* SEC_MODID[807]:ARDSP4*/ + [808] = {0xFC8834B4U, 0x00000002U}, /* SEC_MODID[808]:ARDSP5*/ + [809] = {0xFC8834B8U, 0x00000002U}, /* SEC_MODID[809]:ARDSP6*/ + [810] = {0xFC8834BCU, 0x00000002U}, /* SEC_MODID[810]:ARDSP7*/ + [811] = {0xFC8834C0U, 0x00000002U}, /* SEC_MODID[811]:ECMDSP*/ + [812] = {0xFC883490U, 0x00000002U}, /* SEC_MODID[812]:AXIDSP0*/ + [813] = {0xFC883494U, 0x00000002U}, /* SEC_MODID[813]:AXIDSP1*/ + [814] = {0xFC883498U, 0x00000002U}, /* SEC_MODID[814]:AXIDSP2*/ + [815] = {0xFC88349CU, 0x00000002U}, /* SEC_MODID[815]:AXIDSP3*/ + [816] = {0xFCB53424U, 0x00000002U}, /* SEC_MODID[816]:RSV0*/ + [817] = {0xFC31350CU, 0x00000002U}, /* SEC_MODID[817]:PAP*/ + [818] = {0xFEBD3428U, 0x00000002U}, /* SEC_MODID[818]:DOC*/ +}; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_axi_tbl" +const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[] = { + [0] = {0xFD482010U, 0x0000000FU}, /* RGIDR_MODID[4]:ARRT01*/ + [1] = {0xFD482014U, 0x0000000FU}, /* RGIDR_MODID[5]:ARRT02*/ + [2] = {0xFDA02048U, 0x0000000FU}, /* RGIDR_MODID[41]:ARS01*/ + [3] = {0xFDA0204CU, 0x0000000FU}, /* RGIDR_MODID[42]:ARS02*/ + [4] = {0xFCB62028U, 0x0000000FU}, /* RGIDR_MODID[99]:ARSP31*/ + [5] = {0xFCB6202CU, 0x0000000FU}, /* RGIDR_MODID[100]:ARSP32*/ + [6] = {0xFCB92004U, 0x0000000FU}, /* RGIDR_MODID[114]:ARSP41*/ + [7] = {0xFCB92008U, 0x0000000FU}, /* RGIDR_MODID[115]:ARSP42*/ + [8] = {0xFEBD2004U, 0x0000000FU}, /* RGIDR_MODID[153]:ARVI41*/ + [9] = {0xFEBD2008U, 0x0000000FU}, /* RGIDR_MODID[154]:ARVI42*/ + [10] = {0xFCF82140U, 0x0000000FU}, /* RGIDR_MODID[199]:ARHC1*/ + [11] = {0xFCF82144U, 0x0000000FU}, /* RGIDR_MODID[200]:ARHC2*/ + [12] = {0xFC882004U, 0x0000000FU}, /* RGIDR_MODID[215]:ARIMP01*/ + [13] = {0xFC882008U, 0x0000000FU}, /* RGIDR_MODID[216]:ARIMP02*/ + [14] = {0xFC012004U, 0x0000000FU}, /* RGIDR_MODID[247]:ARPV1*/ + [15] = {0xFC01200CU, 0x0000000FU}, /* RGIDR_MODID[249]:ARPV2*/ + [16] = {0xFDC22004U, 0x0000000FU}, /* RGIDR_MODID[279]:ARRC1*/ + [17] = {0xFDC22008U, 0x0000000FU}, /* RGIDR_MODID[280]:ARRC2*/ + [18] = {0xFD442060U, 0x0000000FU}, /* RGIDR_MODID[316]:ARRD1*/ + [19] = {0xFD442064U, 0x0000000FU}, /* RGIDR_MODID[317]:ARRD2*/ + [20] = {0xFD442084U, 0x0000000FU}, /* RGIDR_MODID[325]:ARRT1*/ + [21] = {0xFD442088U, 0x0000000FU}, /* RGIDR_MODID[326]:ARRT2*/ + [24] = {0xFC862004U, 0x0000000FU}, /* RGIDR_MODID[464]:ARSC1*/ + [25] = {0xFC862008U, 0x0000000FU}, /* RGIDR_MODID[465]:ARSC2*/ + [22] = {0xFC862028U, 0x0000000FU}, /* RGIDR_MODID[473]:ARSTM1*/ + [23] = {0xFC862038U, 0x0000000FU}, /* RGIDR_MODID[476]:ARSTM2*/ + [26] = {0xFDDC2004U, 0x0000000FU}, /* RGIDR_MODID[516]:AXIARNMM*/ + [27] = {0xFDDC200CU, 0x0000000FU}, /* RGIDR_MODID[518]:ARSM1*/ + [28] = {0xFDDC2010U, 0x0000000FU}, /* RGIDR_MODID[519]:ARSM2*/ + [29] = {0xFC802004U, 0x0000000FU}, /* RGIDR_MODID[562]:ARSN1*/ + [30] = {0xFC802008U, 0x0000000FU}, /* RGIDR_MODID[563]:ARSN2*/ + [31] = {0xFCB52004U, 0x0000000FU}, /* RGIDR_MODID[572]:ARSD01*/ + [32] = {0xFCB52008U, 0x0000000FU}, /* RGIDR_MODID[573]:ARSD02*/ + [33] = {0xFCB5203CU, 0x0000000FU}, /* RGIDR_MODID[584]:ARSP01*/ + [34] = {0xFCB52040U, 0x0000000FU}, /* RGIDR_MODID[585]:ARSP02*/ + [35] = {0xFC682004U, 0x0000000FU}, /* RGIDR_MODID[664]:ARVC1*/ + [36] = {0xFC682008U, 0x0000000FU}, /* RGIDR_MODID[665]:ARVC2*/ + [37] = {0xFEBE2008U, 0x0000000FU}, /* RGIDR_MODID[697]:ARVI11*/ + [38] = {0xFEBE200CU, 0x0000000FU}, /* RGIDR_MODID[698]:ARVI12*/ + [39] = {0xFEBF2004U, 0x0000000FU}, /* RGIDR_MODID[744]:ARVI1*/ + [40] = {0xFEBF2008U, 0x0000000FU}, /* RGIDR_MODID[745]:ARVI2*/ + [41] = {0xFC312004U, 0x0000000FU}, /* RGIDR_MODID[772]:ARVIP01*/ + [42] = {0xFC312008U, 0x0000000FU}, /* RGIDR_MODID[773]:ARVIP02*/ + [43] = {0xFC8820A4U, 0x0000000FU}, /* RGIDR_MODID[803]:ARDSP1*/ + [44] = {0xFC8820A8U, 0x0000000FU}, /* RGIDR_MODID[804]:ARDSP2*/ + [45] = {0xFD482410U, 0x00000000U}, /* RGIDW_MODID[4]:ARRT01*/ + [46] = {0xFD482414U, 0x00000000U}, /* RGIDW_MODID[5]:ARRT02*/ + [47] = {0xFDA02448U, 0x00000000U}, /* RGIDW_MODID[41]:ARS01*/ + [48] = {0xFDA0244CU, 0x00000000U}, /* RGIDW_MODID[42]:ARS02*/ + [49] = {0xFCB62428U, 0x00000000U}, /* RGIDW_MODID[99]:ARSP31*/ + [50] = {0xFCB6242CU, 0x00000000U}, /* RGIDW_MODID[100]:ARSP32*/ + [51] = {0xFCB92404U, 0x00000000U}, /* RGIDW_MODID[114]:ARSP41*/ + [52] = {0xFCB92408U, 0x00000000U}, /* RGIDW_MODID[115]:ARSP42*/ + [53] = {0xFEBD2404U, 0x00000000U}, /* RGIDW_MODID[153]:ARVI41*/ + [54] = {0xFEBD2408U, 0x00000000U}, /* RGIDW_MODID[154]:ARVI42*/ + [55] = {0xFCF82540U, 0x00000000U}, /* RGIDW_MODID[199]:ARHC1*/ + [56] = {0xFCF82544U, 0x00000000U}, /* RGIDW_MODID[200]:ARHC2*/ + [57] = {0xFC8824A4U, 0x00000000U}, /* RGIDW_MODID[802]:ARDSP1*/ + [58] = {0xFC8824A8U, 0x00000000U}, /* RGIDW_MODID[803]:ARDSP2*/ + [59] = {0xFC882404U, 0x00000000U}, /* RGIDW_MODID[215]:ARIMP01*/ + [60] = {0xFC882408U, 0x00000000U}, /* RGIDW_MODID[216]:ARIMP02*/ + [61] = {0xFC012404U, 0x00000000U}, /* RGIDW_MODID[247]:ARPV1*/ + [62] = {0xFC01240CU, 0x00000000U}, /* RGIDW_MODID[249]:ARPV2*/ + [63] = {0xFDC22404U, 0x00000000U}, /* RGIDW_MODID[279]:ARRC1*/ + [64] = {0xFDC22408U, 0x00000000U}, /* RGIDW_MODID[280]:ARRC2*/ + [65] = {0xFD442460U, 0x00000000U}, /* RGIDW_MODID[315]:ARRD1*/ + [66] = {0xFD442464U, 0x00000000U}, /* RGIDW_MODID[316]:ARRD2*/ + [67] = {0xFD442484U, 0x00000000U}, /* RGIDW_MODID[324]:ARRT1*/ + [68] = {0xFD442488U, 0x00000000U}, /* RGIDW_MODID[325]:ARRT2*/ + [71] = {0xFC862404U, 0x00000000U}, /* RGIDW_MODID[463]:ARSC1*/ + [72] = {0xFC862408U, 0x00000000U}, /* RGIDW_MODID[464]:ARSC2*/ + [69] = {0xFC862428U, 0x00000000U}, /* RGIDW_MODID[472]:ARSTM1*/ + [70] = {0xFC862438U, 0x00000000U}, /* RGIDW_MODID[475]:ARSTM2*/ + [73] = {0xFDDC2404U, 0x00000000U}, /* RGIDW_MODID[515]:AXIARNMM*/ + [74] = {0xFDDC240CU, 0x00000000U}, /* RGIDW_MODID[517]:ARSM1*/ + [75] = {0xFDDC2410U, 0x00000000U}, /* RGIDW_MODID[518]:ARSM2*/ + [76] = {0xFC802404U, 0x00000000U}, /* RGIDW_MODID[561]:ARSN1*/ + [77] = {0xFC802408U, 0x00000000U}, /* RGIDW_MODID[562]:ARSN2*/ + [78] = {0xFCB52404U, 0x00000000U}, /* RGIDW_MODID[571]:ARSD01*/ + [79] = {0xFCB52408U, 0x00000000U}, /* RGIDW_MODID[572]:ARSD02*/ + [80] = {0xFCB5243CU, 0x00000000U}, /* RGIDW_MODID[583]:ARSP01*/ + [81] = {0xFCB52440U, 0x00000000U}, /* RGIDW_MODID[584]:ARSP02*/ + [82] = {0xFC682404U, 0x00000000U}, /* RGIDW_MODID[663]:ARVC1*/ + [83] = {0xFC682408U, 0x00000000U}, /* RGIDW_MODID[664]:ARVC2*/ + [84] = {0xFEBE2408U, 0x00000000U}, /* RGIDW_MODID[696]:ARVI11*/ + [85] = {0xFEBE240CU, 0x00000000U}, /* RGIDW_MODID[697]:ARVI12*/ + [86] = {0xFEBF2404U, 0x00000000U}, /* RGIDW_MODID[743]:ARVI1*/ + [87] = {0xFEBF2408U, 0x00000000U}, /* RGIDW_MODID[744]:ARVI2*/ + [88] = {0xFC312404U, 0x00000000U}, /* RGIDW_MODID[771]:ARVIP01*/ + [89] = {0xFC312408U, 0x00000000U}, /* RGIDW_MODID[772]:ARVIP02*/ +}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#pragma ghs section rodata=".rgid_gid_tbl" +const REGION_ID_SETTING_TABLE g_rgid_gid_tbl[] = { + [0] = {0xFC0F0000U, 0x000F0024U}, /* CCI MPU GID register 0 */ +}; +/* Now go back to default rules */ +#pragma ghs section rodata=default + +const uint32_t g_rgid_rtdma_setting_value[RTDMA_MODULE_MAX][RTDMA_CH_MAX][2U] = { + {/* Module0 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, + {/* Module1 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {RTDMA_EN, RGID_1}, /* CH0 */ + [1] = {RTDMA_EN, RGID_1}, /* CH1 */ + [2] = {RTDMA_EN, RGID_1}, /* CH2 */ + [3] = {RTDMA_EN, RGID_1}, /* CH3 */ + [4] = {RTDMA_EN, RGID_1}, /* CH4 */ + [5] = {RTDMA_EN, RGID_1}, /* CH5 */ + [6] = {RTDMA_EN, RGID_1}, /* CH6 */ + [7] = {RTDMA_EN, RGID_1}, /* CH7 */ + [8] = {RTDMA_EN, RGID_1}, /* CH8 */ + [9] = {RTDMA_EN, RGID_1}, /* CH9 */ + [10] = {RTDMA_EN, RGID_1}, /* CH10 */ + [11] = {RTDMA_EN, RGID_1}, /* CH11 */ + [12] = {RTDMA_EN, RGID_1}, /* CH12 */ + [13] = {RTDMA_EN, RGID_1}, /* CH13 */ + [14] = {RTDMA_EN, RGID_1}, /* CH14 */ + [15] = {RTDMA_EN, RGID_1} /* CH15 */ + }, +}; + +const uint32_t g_rgid_sysdma_setting_value[SYSDMA_MODULE_MAX][SYSDMA_CH_MAX][2U] = { + {/* Module0 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {SYSDMA_EN, RGID_2}, /* CH0 */ + [1] = {SYSDMA_EN, RGID_2}, /* CH1 */ + [2] = {SYSDMA_EN, RGID_2}, /* CH2 */ + [3] = {SYSDMA_EN, RGID_2}, /* CH3 */ + [4] = {SYSDMA_EN, RGID_2}, /* CH4 */ + [5] = {SYSDMA_EN, RGID_2}, /* CH5 */ + [6] = {SYSDMA_EN, RGID_2}, /* CH6 */ + [7] = {SYSDMA_EN, RGID_2}, /* CH7 */ + [8] = {SYSDMA_EN, RGID_2}, /* CH8 */ + [9] = {SYSDMA_EN, RGID_2}, /* CH9 */ + [10] = {SYSDMA_EN, RGID_2}, /* CH10 */ + [11] = {SYSDMA_EN, RGID_2}, /* CH11 */ + [12] = {SYSDMA_EN, RGID_2}, /* CH12 */ + [13] = {SYSDMA_EN, RGID_2}, /* CH13 */ + [14] = {SYSDMA_EN, RGID_2}, /* CH14 */ + [15] = {SYSDMA_EN, RGID_2} /* CH15 */ + }, + {/* Module1 */ + /* | RGIDMEN | RGID(Master) | */ + [0] = {SYSDMA_EN, RGID_2}, /* CH0 */ + [1] = {SYSDMA_EN, RGID_2}, /* CH1 */ + [2] = {SYSDMA_EN, RGID_2}, /* CH2 */ + [3] = {SYSDMA_EN, RGID_2}, /* CH3 */ + [4] = {SYSDMA_EN, RGID_2}, /* CH4 */ + [5] = {SYSDMA_EN, RGID_2}, /* CH5 */ + [6] = {SYSDMA_EN, RGID_2}, /* CH6 */ + [7] = {SYSDMA_EN, RGID_2}, /* CH7 */ + [8] = {SYSDMA_EN, RGID_INVALID}, /* reserved */ + [9] = {SYSDMA_EN, RGID_INVALID}, /* reserved */ + [10] = {SYSDMA_EN, RGID_INVALID}, /* reserved */ + [11] = {SYSDMA_EN, RGID_INVALID}, /* reserved */ + [12] = {SYSDMA_EN, RGID_INVALID}, /* reserved */ + [13] = {SYSDMA_EN, RGID_INVALID}, /* reserved */ + [14] = {SYSDMA_EN, RGID_INVALID}, /* reserved */ + [15] = {SYSDMA_EN, RGID_INVALID} /* reserved */ + }, +}; + +/* When V4H, this table is used as RT-VRAM0. */ +/* RAM protection setting for SECDIV[n]D_0 / SECCTRR[m]D_0 / SECCTRW[m]D_0 */ +const RTRAM_PROTECTION_STRUCTUR g_rtsram_protection_table[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTSRAM_ICUMX_IPL_AREA] = {NOT_USED_VALUE, {0x0000FFFCU, 0x0000FFFEU}}, /* not used for address value */ + /* Area0 phys:0xE0000000-0xE003FFFF R:RGID0/1 W:RGID0 */ + [RTSRAM_ICUMX_FW_AREA] = {RTSRAM_AREA1_TOP, {0x0004FFFEU, 0x0004FFFEU}}, /* Area1 phys:0xE0040000-0xE00FFFFF R:RGID0 W:RGID0 */ + [2] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [3] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTSRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* this table is finaly setting for RT-VRAM protection */ +/* RAM protection setting for SECDIV[n]D_1 / SECCTRR[m]D_1 / SECCTRW[m]D_1 */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table_1[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM_BLANK_AREA] = {NOT_USED_VALUE, {0x0000FFB6U, 0x0000FFB2U}}, /* not used for address value */ + /* Area0 phys:0xE2000000-0xE200FFFF R:RGID0/3/6 W:RGID0/2/3/6 */ + [RTVRAM_EXTEND_CACHE_AREA] = {RTVRAM_AREA1_TOP, {0x0000BFFFU, 0x0000BFFFU}}, /* Area1 phys:0xE2010000-0xE20FFFFF R:RGID14 W:RGID14 */ + [RTVRAM_RTOS_AREA] = {RTVRAM_AREA2_TOP, {0x0000FFF4U, 0x0000FFF0U}}, /* Area2 phys:0xE2100000-0xE3BFFFFF R:RGID0/1/3 W:RGID0/1/2/3 */ + [3] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for SPTDIVCR[n] / SPTRGNCR[n] / SPTSECCR[n] */ +const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX] = { + /* access Secure */ + /* address R | W R|W */ + [SYSTEM_RAM_CX_2ND_IPL] = {NOT_USED_VALUE, {0xFFD8FFD8U, 0x00000000U}}, /* not used for address value */ + /* Area0 phys:0xE6300000-0xE635DFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [SYSTEM_RAM_SHARED_MEM] = {SYSTEM_RAM_AREA1_TOP, {0xFFD8FFD8U, 0x00000000U}}, /* Area1 phys:0xE635E000-0xE635FFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [2] = {SYSTEM_RAM_AREA2_TOP, {0xFFDAFFDAU, 0x00000000U}}, /* Area2 phys:0xE6360000-0xE63FFFFF R:RGID0/2/5 W:RGID0/2/5 */ + [3] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for DPTDIVCR[n] / DPTRGNCR[n] / DPTSECCR[n] */ +const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX] = { + /* access secure */ + /* address R | W R|W */ + [RTVRAM_EXTEND_AREA] = {NOT_USED_VALUE, {0xBFFFBFFFU, 0x00000000U}}, /* not used for address value */ + /* Area0 phys:0x04_00000000-0x04_01BFFFFF R:RGID14 W:RGID14 */ + [CR_FW_SHARED_AREA] = {DRAM_ADDR_AREA1, {0xFFBCFFBCU, 0x00000000U}}, /* Area1 phys:0x04_01C00000-0x04_01CFFFFF R:RGID0/1/6 W:RGID0/1/6 */ + [SDRAM_BLANK_AREA] = {DRAM_ADDR_AREA2, {0xFF90FF90U, 0x00000000U}}, /* Area2:OPTEE_DISABLE phys:0x04_01D00000-0x04_063FFFFF + * Area2:OPTEE_ENABLE phys:0x04_01D00000-0x04_040FFFFF + * R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFAFFF8U, 0x00000000U}}, /* Area3 phys:0x04_06400000-0x04_0643FFFF R:RGID0/2 W:RGID0/1/2 */ + [SDRAM_PUBLIC_AREA] = {DRAM_ADDR_AREA4, {0xFF90FF90U, 0x00000000U}}, /* Area4 phys:0x04_06440000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA5, {0xFFB9FFB9U, 0x00000000U}}, /* Area5 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA6, {0xFFB0FFB0U, 0x00000000U}}, /* Area6 phys:0x04_08000000-0x04_1DBFFFFF R:RGID0/1/2/3/6 W:RGID0/1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA7, {0xFFB9FFB9U, 0x00000000U}}, /* Area7 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFBDFFBDU, 0x00000000U}}, /* Area8 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFDDFFDDU, 0x00000000U}}, /* Area9 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA11,{0xBF90BF90U, 0x00000000U}}, /* Area11 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA12,{0xFFF9FFF9U, 0x00000000U}}, /* Area12 phys:0x05_00000000-0x05_FFFFFFFF R:RGID1/2 W:RGID1/2 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA13,{0xFFFFFFFFU, 0x00000000U}}, /* Area13 phys:0x06_00000000-0x06_FFFFFFFF */ + [14] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [16] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +#else + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFAFFFAU, 0x00000000U}}, /* Area3 phys:0x04_04100000-0x04_063FFFFF R:RGID0/2 W:RGID0/2 */ + [SDRAM_PROTECT_AREA2]= {DRAM_ADDR_AREA4, {0xFFFAFFF8U, 0x00000000U}}, /* Area4 phys:0x04_06400000-0x04_0643FFFF R:RGID0/2 W:RGID0/1/2 */ + [SDRAM_BLANK_AREA2] = {DRAM_ADDR_AREA5, {0xFF90FF90U, 0x00000000U}}, /* Area5 phys:0x04_06440000-0x04_07DFFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [OPTEE_SHARED_AREA] = {DRAM_ADDR_AREA6, {0xFFFBFFFBU, 0x00000000U}}, /* Area6 phys:0x04_07E00000-0x04_07EFFFFF R:RGID2 W:RGID2 */ + [SDRAM_BLANK_AREA3] = {DRAM_ADDR_AREA7, {0xFF90FF90U, 0x00000000U}}, /* Area7 phys:0x04_07F00000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFB9FFB9U, 0x00000000U}}, /* Area8 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFB0FFB0U, 0x00000000U}}, /* Area9 phys:0x04_08000000-0x04_1DBFFFFF R:RGID0/1/2/3/6 W:RGID0/1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA11,{0xFFBDFFBDU, 0x00000000U}}, /* Area11 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA12,{0xFFDDFFDDU, 0x00000000U}}, /* Area12 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFB9FFB9U, 0x00000000U}}, /* Area13 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA14,{0xBF90BF90U, 0x00000000U}}, /* Area14 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA15,{0xFFF9FFF9U, 0x00000000U}}, /* Area15 phys:0x05_00000000-0x05_FFFFFFFF R:RGID1/2 W:RGID1/2 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA16,{0xFFFFFFFFU, 0x00000000U}}, /* Area16 phys:0x06_00000000-0x06_FFFFFFFF */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + [17] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [18] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [19] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [20] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [21] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [22] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [23] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [24] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [25] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [26] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [27] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [28] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [29] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [30] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [31] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [32] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [33] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [34] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [35] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [36] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [37] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [38] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [39] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [40] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [41] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [42] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [43] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [44] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [45] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [46] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [47] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [48] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [49] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [50] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [51] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [52] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [53] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [54] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [55] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [56] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [57] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [58] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [59] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [60] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [61] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [62] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [63] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +const CONFIGURATION_SETTING_TABLE g_fdt_tbl[FDT_REG_MAX] = { + [0] = {0xFCF80700U, 0x00000008U}, /*FDT_PCI00*/ + [1] = {0xFCF80710U, 0x00000005U}, /*FDT_AVB0*/ + [2] = {0xFCF80714U, 0x00000005U}, /*FDT_AVB1*/ + [3] = {0xFCF80718U, 0x00000005U}, /*FDT_AVB2*/ + [4] = {0xFF880704U, 0x0000000BU}, /*FDT_FBABUSIR0*/ + [5] = {0xFF880708U, 0x0000000BU}, /*FDT_FBABUSIR1*/ + [6] = {0xFF88070CU, 0x0000000BU}, /*FDT_FBABUSIR2*/ + [7] = {0xFF880710U, 0x0000000BU}, /*FDT_FBABUSIR3*/ + [8] = {0xFF88071CU, 0x0000000BU}, /*FDT_IMP0*/ + [9] = {0xFF880720U, 0x0000000BU}, /*FDT_IMP1*/ + [10] = {0xFF880728U, 0x0000000BU}, /*FDT_DSPD*/ + [11] = {0xFF88072CU, 0x0000000BU}, /*FDT_DSPP*/ + [12] = {0xFC610714U, 0x00000008U}, /*FDT_RGX0*/ + [13] = {0xFDC2070CU, 0x00000008U}, /*FDT_DCLS_ICUMX*/ + [14] = {0xFDC20710U, 0x00000008U}, /*FDT_ICUMX*/ + [15] = {0xFD430700U, 0x00000008U}, /*FDT_PERI_RTDM0*/ + [16] = {0xFD430704U, 0x00000008U}, /*FDT_PERI_RTDM1*/ + [17] = {0xFD440708U, 0x00000008U}, /*FDT_BUS_RTDM0M*/ + [18] = {0xFD44070CU, 0x00000008U}, /*FDT_BUS_RTDM1M*/ + [19] = {0xFD440718U, 0x00000008U}, /*FDT_CR52SS0*/ + [20] = {0xFD44071CU, 0x00000008U}, /*FDT_CSD*/ + [21] = {0xFD440724U, 0x00000008U}, /*FDT_INTAP0*/ + [22] = {0xFD440728U, 0x00000008U}, /*FDT_MEM_RTDM0*/ + [23] = {0xFD44072CU, 0x00000008U}, /*FDT_MEM_RTDM1*/ + [24] = {0xFD44075CU, 0x00000008U}, /*FDT_CR52SS1*/ + [25] = {0xFD440760U, 0x00000008U}, /*FDT_CR52SS2*/ + [26] = {0xFF860710U, 0x00000008U}, /*FDT_CCI*/ + [27] = {0xFF860718U, 0x00000008U}, /*FDT_FBABUSTOP0*/ + [28] = {0xFCB80704U, 0x00000006U}, /*FDT_PERI_SYDM1*/ + [29] = {0xFCB80708U, 0x00000006U}, /*FDT_PERI_SYDM2*/ + [30] = {0xFCB50708U, 0x00000006U}, /*FDT_BUS_SYDM1*/ + [31] = {0xFCB5070CU, 0x00000006U}, /*FDT_BUS_SYDM2*/ + [32] = {0xFCB50710U, 0x00000004U}, /*FDT_FRAY*/ + [33] = {0xFCB50718U, 0x00000006U}, /*FDT_MEM_SYDM1*/ + [34] = {0xFCB5071CU, 0x00000006U}, /*FDT_MEM_SYDM2*/ + [35] = {0xFCB50720U, 0x00000006U}, /*FDT_SDHI0*/ + [36] = {0xFF810700U, 0x00000008U}, /*FDT_AXMM2AXSTM*/ + [37] = {0xFF810704U, 0x00000008U}, /*FDT_CSDE0*/ + [38] = {0xFF810708U, 0x00000008U}, /*FDT_CSDE1*/ + [39] = {0xFC080704U, 0x00000006U}, /*FDT_FBABUSVC*/ + [40] = {0xFC080710U, 0x0000000AU}, /*FDT_IMR00*/ + [41] = {0xFC080714U, 0x0000000AU}, /*FDT_IMR01*/ + [42] = {0xFC080724U, 0x0000000AU}, /*FDT_IMR10*/ + [43] = {0xFC080728U, 0x0000000AU}, /*FDT_IMR11*/ + [44] = {0xFC080740U, 0x0000000AU}, /*FDT_IMS0*/ + [45] = {0xFC080744U, 0x0000000AU}, /*FDT_IMS1*/ + [46] = {0xFC080748U, 0x0000000AU}, /*FDT_IV1ES*/ + [47] = {0xFC9E0700U, 0x00000005U}, /*FDT_DSITXLINK0*/ + [48] = {0xFC9E0708U, 0x00000008U}, /*FDT_FBABUSVIO*/ + [49] = {0xFC9E0714U, 0x00000008U}, /*FDT_FCPVD0*/ + [50] = {0xFC9E071CU, 0x00000008U}, /*FDT_FCPVX0*/ + [51] = {0xFC9F0700U, 0x0000000EU}, /*FDT_ISP02*/ + [52] = {0xFC9F0704U, 0x0000000EU}, /*FDT_ISP03*/ + [53] = {0xFC9F0708U, 0x0000000EU}, /*FDT_ISP04*/ + [54] = {0xFC9F0710U, 0x0000000EU}, /*FDT_VIN0*/ + [55] = {0xFC9F0714U, 0x0000000EU}, /*FDT_VIN1*/ + [56] = {0xFC9F0720U, 0x0000000EU}, /*FDT_ISP00*/ + [57] = {0xFC9F0724U, 0x0000000EU}, /*FDT_ISP01*/ + [58] = {0xFC310704U, 0x00000006U}, /*FDT_FBABUSVIP0*/ + [59] = {0xFC310710U, 0x0000000BU}, /*FDT_SMPO0*/ + [60] = {0xFC310718U, 0x0000000BU}, /*FDT_SMPS0*/ + [61] = {0xFC31071CU, 0x0000000BU}, /*FDT_UMFL0*/ + [62] = {0xFC400204U, 0x0000000BU}, /*FDT_DSP00*/ + [63] = {0xFC400208U, 0x0000000BU}, /*FDT_DSP01*/ + [64] = {0xFC40020CU, 0x0000000BU}, /*FDT_DSP10*/ + [65] = {0xFC400210U, 0x0000000BU}, /*FDT_DSP11*/ + [66] = {0xFC400214U, 0x0000000BU}, /*FDT_DSP20*/ + [67] = {0xFC400218U, 0x0000000BU}, /*FDT_DSP21*/ + [68] = {0xFC40021CU, 0x0000000BU}, /*FDT_DSP30*/ + [69] = {0xFC400220U, 0x0000000BU}, /*FDT_DSP31*/ + [70] = {0xFC310708U, 0x0000000BU}, /*FDT_PAP*/ + [71] = {0xFD440720U, 0x00000008U}, /*FDT_CSDE2*/ +}; + +const CONFIGURATION_SETTING_TABLE g_inten_tbl[INTEN_REG_MAX] = { + [0] = {0xFF8403C0U, 0x00001003U}, /*FIXINTENTOP00*/ + [1] = {0xFDA723C0U, 0x00000000U}, /*FIXINTENTOP10*/ + [2] = {0xFF8483C0U, 0x00000007U}, /*FIXINTENTOP20*/ + [3] = {0xFDDFC3C0U, 0x000000F0U}, /*FIXINTENMM0*/ + [4] = {0xFD8003C0U, 0x099F1CF3U}, /*FIXINTENRT00*/ + [5] = {0xFD8003C4U, 0x00042000U}, /*FIXINTENRT01*/ + [6] = {0xFD8043C0U, 0x00000033U}, /*FIXINTENRT10*/ + [7] = {0xFD8083C0U, 0x000000CCU}, /*FIXINTENRT20*/ + [8] = {0xFD80C3C0U, 0x00000000U}, /*FIXINTENRT30*/ + [9] = {0xFCB303C0U, 0x001DDDC0U}, /*FIXINTENPER000*/ + [10] = {0xFCB343C0U, 0x0000000FU}, /*FIXINTENPER010*/ + [11] = {0xFCB383C0U, 0x00000000U}, /*FIXINTENPER020*/ + [12] = {0xFCB3C3C0U, 0x00000000U}, /*FIXINTENPER030*/ + [13] = {0xFCE903C0U, 0x210243F8U}, /*FIXINTENHSC0*/ + [14] = {0xFCE903C4U, 0x00000000U}, /*FIXINTENHSC1*/ + [15] = {0xFC8F83C0U, 0x30004460U}, /*FIXINTENVIO00*/ + [16] = {0xFC8F83C4U, 0x00000000U}, /*FIXINTENVIO01*/ + [17] = {0xFC8F03C0U, 0x5100000DU}, /*FIXINTENVIO10*/ + [18] = {0xFC8F03C4U, 0x00000029U}, /*FIXINTENVIO11*/ + [19] = {0xFC8FC3C0U, 0x00000000U}, /*FIXINTENVIO20*/ + [20] = {0xFC0103C0U, 0x3266A3A3U}, /*FIXINTENVC00*/ + [21] = {0xFF8E03C0U, 0x03C3C00FU}, /*FIXINTENIR0*/ + [22] = {0xFC2F03C0U, 0x0000037FU}, /*FIXINTENVIP00*/ + [23] = {0xFC6403C0U, 0x00000005U}, /*FIXINTEN3DG0*/ + [24] = {0xFC4803C0U, 0x0003FFFFU}, /*FIXINTENDSP0*/ + [25] = {0xFF840440U, 0xC5400003U}, /*EDCINTENTOP00*/ + [26] = {0xFF840444U, 0x81552A0AU}, /*EDCINTENTOP01*/ + [27] = {0xFF840448U, 0x0000000FU}, /*EDCINTENTOP02*/ + [28] = {0xFDA72440U, 0xFCDEFFFDU}, /*EDCINTENTOP10*/ + [29] = {0xFDA72444U, 0x0039BDFFU}, /*EDCINTENTOP11*/ + [30] = {0xFF848440U, 0x00000003U}, /*EDCINTENTOP20*/ + [31] = {0xFF844440U, 0x0000003FU}, /*EDCINTENTOP30*/ + [32] = {0xFDDFC440U, 0xFFFFFFFFU}, /*EDCINTENMM0*/ + [33] = {0xFDDFC444U, 0xFFFFFFFFU}, /*EDCINTENMM1*/ + [34] = {0xFDDFC448U, 0x0FFFFFFFU}, /*EDCINTENMM2*/ + [35] = {0xFDDFC44CU, 0xFFFFFEFFU}, /*EDCINTENMM3*/ + [36] = {0xFDDFC450U, 0x0FFFFFFFU}, /*EDCINTENMM4*/ + [37] = {0xFD800440U, 0x3F77BFFFU}, /*EDCINTENRT00*/ + [38] = {0xFD800444U, 0x001DF804U}, /*EDCINTENRT01*/ + [39] = {0xFD800448U, 0x81FFFFAFU}, /*EDCINTENRT02*/ + [40] = {0xFD80044CU, 0x3EF3FFFFU}, /*EDCINTENRT03*/ + [41] = {0xFD800450U, 0x6DFDDFF7U}, /*EDCINTENRT04*/ + [42] = {0xFD800454U, 0x9FC001FFU}, /*EDCINTENRT05*/ + [43] = {0xFD808440U, 0x00006B73U}, /*EDCINTENRT20*/ + [44] = {0xFD80C440U, 0x7FFC7FFDU}, /*EDCINTENRT30*/ + [45] = {0xFD80C444U, 0x00000000U}, /*EDCINTENRT31*/ + [46] = {0xFCB30440U, 0x80800003U}, /*EDCINTENPER000*/ + [47] = {0xFCB30444U, 0x0000000EU}, /*EDCINTENPER001*/ + [48] = {0xFCB30448U, 0xB7F81E80U}, /*EDCINTENPER002*/ + [49] = {0xFCB3044CU, 0xFF0F03FDU}, /*EDCINTENPER003*/ + [50] = {0xFCB30450U, 0x87E73B7CU}, /*EDCINTENPER004*/ + [51] = {0xFCB30454U, 0xEC010007U}, /*EDCINTENPER005*/ + [52] = {0xFCB30458U, 0x2000FFFFU}, /*EDCINTENPER006*/ + [53] = {0xFCB3045CU, 0x00000180U}, /*EDCINTENPER007*/ + [54] = {0xFCB34440U, 0xFFF1E1E7U}, /*EDCINTENPER010*/ + [55] = {0xFCB34444U, 0x0000000FU}, /*EDCINTENPER011*/ + [56] = {0xFCB38440U, 0xFFFFFFF3U}, /*EDCINTENPER020*/ + [57] = {0xFCB3C440U, 0xFFFFFF0FU}, /*EDCINTENPER030*/ + [58] = {0xFCB3C444U, 0x0FFFFFFFU}, /*EDCINTENPER031*/ + [59] = {0xFCB3C448U, 0x000083FEU}, /*EDCINTENPER032*/ + [60] = {0xFCE90440U, 0xDF7FBFFBU}, /*EDCINTENHSC0*/ + [61] = {0xFCE90444U, 0x10047627U}, /*EDCINTENHSC1*/ + [62] = {0xFCE90448U, 0x81004050U}, /*EDCINTENHSC2*/ + [63] = {0xFCE9044CU, 0xA6F84210U}, /*EDCINTENHSC3*/ + [64] = {0xFCE90450U, 0x00D30901U}, /*EDCINTENHSC4*/ + [65] = {0xFCE90454U, 0x00000001U}, /*EDCINTENHSC5*/ + [66] = {0xFC8F8440U, 0x37FFFFFFU}, /*EDCINTENVIO00*/ + [67] = {0xFC8F8444U, 0x0E3FFC7FU}, /*EDCINTENVIO01*/ + [68] = {0xFC8F8448U, 0x00000000U}, /*EDCINTENVIO02*/ + [69] = {0xFC8F844CU, 0xCCCCC000U}, /*EDCINTENVIO03*/ + [70] = {0xFC8F8450U, 0x070F0CF0U}, /*EDCINTENVIO04*/ + [71] = {0xFC8F8454U, 0xC0000000U}, /*EDCINTENVIO05*/ + [72] = {0xFC8F8458U, 0x001F2080U}, /*EDCINTENVIO06*/ + [73] = {0xFC8F0440U, 0x45010103U}, /*EDCINTENVIO10*/ + [74] = {0xFC8F0444U, 0xFFFF0000U}, /*EDCINTENVIO11*/ + [75] = {0xFC8F0448U, 0xFFFF0000U}, /*EDCINTENVIO12*/ + [76] = {0xFC8F044CU, 0xE234D7CCU}, /*EDCINTENVIO13*/ + [77] = {0xFC8F0450U, 0xC8234D16U}, /*EDCINTENVIO14*/ + [78] = {0xFC8F0454U, 0x1522511FU}, /*EDCINTENVIO15*/ + [79] = {0xFC8F0458U, 0x1F800000U}, /*EDCINTENVIO16*/ + [80] = {0xFC8FC440U, 0x00A68B45U}, /*EDCINTENVIO20*/ + [81] = {0xFC010440U, 0x0010CC07U}, /*EDCINTENVC00*/ + [82] = {0xFC010444U, 0xC3CF0E30U}, /*EDCINTENVC01*/ + [83] = {0xFC010448U, 0xFFFFFC53U}, /*EDCINTENVC02*/ + [84] = {0xFC01044CU, 0x9F773DCFU}, /*EDCINTENVC03*/ + [85] = {0xFC010450U, 0x0000003BU}, /*EDCINTENVC04*/ + [86] = {0xFF8E0440U, 0x0004D1FFU}, /*EDCINTENIR0*/ + [87] = {0xFF8E0444U, 0xC983DF98U}, /*EDCINTENIR1*/ + [88] = {0xFF8E0448U, 0x7BD3FFFFU}, /*EDCINTENIR2*/ + [89] = {0xFF8E044CU, 0x0F0000FFU}, /*EDCINTENIR3*/ + [90] = {0xFC2F0440U, 0x0007FF77U}, /*EDCINTENVIP00*/ + [91] = {0xFC2F0444U, 0xF3BA0000U}, /*EDCINTENVIP01*/ + [92] = {0xFC2F0448U, 0x001F7BE8U}, /*EDCINTENVIP02*/ + [93] = {0xFC2F044CU, 0x00000000U}, /*EDCINTENVIP03*/ + [94] = {0xFC2F0450U, 0x18000000U}, /*EDCINTENVIP04*/ + [95] = {0xFC2F0454U, 0x0000FAFAU}, /*EDCINTENVIP05*/ + [96] = {0xFC640440U, 0xF3FC3F7EU}, /*EDCINTEN3DG0*/ + [97] = {0xFC640444U, 0x0081FC47U}, /*EDCINTEN3DG1*/ + [98] = {0xFC480440U, 0x03FFFFFFU}, /*EDCINTENDSP0*/ + [99] = {0xFF840680U, 0x000F2D8FU}, /*ICISTPINTENTOP00*/ + [100] = {0xFDA72680U, 0x00000003U}, /*ICISTPINTENTOP10*/ + [101] = {0xFF848680U, 0x00000007U}, /*ICISTPINTENTOP20*/ + [102] = {0xFF844680U, 0x000000D7U}, /*ICISTPINTENTOP30*/ + [103] = {0xFDDFC680U, 0x0007EFFFU}, /*ICISTPINTENMM0*/ + [104] = {0xFD800680U, 0x0A007FFFU}, /*ICISTPINTENRT00*/ + [105] = {0xFD804680U, 0x000001E3U}, /*ICISTPINTENRT10*/ + [106] = {0xFD808680U, 0x00000007U}, /*ICISTPINTENRT20*/ + [107] = {0xFD80C680U, 0x00000003U}, /*ICISTPINTENRT30*/ + [108] = {0xFCB30680U, 0x000235F1U}, /*ICISTPINTENPER000*/ + [109] = {0xFCB34680U, 0x0000000FU}, /*ICISTPINTENPER010*/ + [110] = {0xFCB38680U, 0x00000003U}, /*ICISTPINTENPER020*/ + [111] = {0xFCB3C680U, 0x00000003U}, /*ICISTPINTENPER030*/ + [112] = {0xFCE90680U, 0x000000C7U}, /*ICISTPINTENHSC0*/ + [113] = {0xFC8F8680U, 0x00000013U}, /*ICISTPINTENVIO00*/ + [114] = {0xFC8F0680U, 0x0000003FU}, /*ICISTPINTENVIO10*/ + [115] = {0xFC8FC680U, 0x00000003U}, /*ICISTPINTENVIO20*/ + [116] = {0xFC010680U, 0x0000003FU}, /*ICISTPINTENVC00*/ + [117] = {0xFF8E0680U, 0x0000EF47U}, /*ICISTPINTENIR0*/ + [118] = {0xFC2F0680U, 0x00000037U}, /*ICISTPINTENVIP00*/ + [119] = {0xFC640680U, 0x0000000FU}, /*ICISTPINTEN3DG0*/ + [120] = {0xFC480680U, 0x000000FFU}, /*ICISTPINTENDSP0*/ + [121] = {0xFF840580U, 0x00000029U}, /*DCLSINTENTOP00*/ + [122] = {0xFDA72580U, 0x00000001U}, /*DCLSINTENTOP10*/ + [123] = {0xFF848580U, 0x00000003U}, /*DCLSINTENTOP20*/ + [124] = {0xFF844580U, 0x00000003U}, /*DCLSINTENTOP30*/ + [125] = {0xFDDFC580U, 0x3FFFFFF7U}, /*DCLSINTENMM0*/ + [126] = {0xFDDFC584U, 0x00000080U}, /*DCLSINTENMM1*/ + [127] = {0xFD800580U, 0x0FFFE7FFU}, /*DCLSINTENRT00*/ + [128] = {0xFD800584U, 0x00000036U}, /*DCLSINTENRT01*/ + [129] = {0xFD808580U, 0x00000033U}, /*DCLSINTENRT20*/ + [130] = {0xFD80C580U, 0x00000001U}, /*DCLSINTENRT30*/ + [131] = {0xFCB30580U, 0x039E1F43U}, /*DCLSINTENPER000*/ + [132] = {0xFCB34580U, 0x00000007U}, /*DCLSINTENPER010*/ + [133] = {0xFCB38580U, 0x00000003U}, /*DCLSINTENPER020*/ + [134] = {0xFCB3C580U, 0x0000000FU}, /*DCLSINTENPER030*/ + [135] = {0xFCE90580U, 0x0BFF01FAU}, /*DCLSINTENHSC0*/ + [136] = {0xFC8F8580U, 0x5000FC0FU}, /*DCLSINTENVIO00*/ + [137] = {0xFC8F0580U, 0x0C6A80FFU}, /*DCLSINTENVIO10*/ + [138] = {0xFC8FC580U, 0x00000001U}, /*DCLSINTENVIO20*/ + [139] = {0xFC010580U, 0x03F8E79FU}, /*DCLSINTENVC00*/ + [140] = {0xFF8E0580U, 0x0FFD9E63U}, /*DCLSINTENIR0*/ + [141] = {0xFC2F0580U, 0xE0000EF7U}, /*DCLSINTENVIP00*/ + [142] = {0xFC2F0584U, 0x0000003FU}, /*DCLSINTENVIP01*/ + [143] = {0xFC480580U, 0x00000003U}, /*DCLSINTENDSP0*/ + [144] = {0xFF840480U, 0xF986FFFFU}, /*LSCHKINTENTOP00*/ + [145] = {0xFF840484U, 0x0003E61CU}, /*LSCHKINTENTOP01*/ + [146] = {0xFDA72480U, 0x00000003U}, /*LSCHKINTENTOP10*/ + [147] = {0xFF848480U, 0x0000001FU}, /*LSCHKINTENTOP20*/ + [148] = {0xFF844480U, 0x0006B5ADU}, /*LSCHKINTENTOP30*/ + [149] = {0xFDDFC480U, 0xFEFFF7FFU}, /*LSCHKINTENMM0*/ + [150] = {0xFDDFC484U, 0x0000017FU}, /*LSCHKINTENMM1*/ + [151] = {0xFD800480U, 0x4FFF3F4FU}, /*LSCHKINTENRT00*/ + [152] = {0xFD800484U, 0x003FFE7FU}, /*LSCHKINTENRT01*/ + [153] = {0xFD800488U, 0x04C4C000U}, /*LSCHKINTENRT02*/ + [154] = {0xFD804480U, 0x000FC1F8U}, /*LSCHKINTENRT10*/ + [155] = {0xFD808480U, 0x0000037BU}, /*LSCHKINTENRT20*/ + [156] = {0xFD80C480U, 0x00000003U}, /*LSCHKINTENRT30*/ + [157] = {0xFCB30480U, 0x1FAF1F0FU}, /*LSCHKINTENPER000*/ + [158] = {0xFCB30484U, 0x00000CAFU}, /*LSCHKINTENPER001*/ + [159] = {0xFCB34480U, 0x000000FFU}, /*LSCHKINTENPER010*/ + [160] = {0xFCB38480U, 0x0000000FU}, /*LSCHKINTENPER020*/ + [161] = {0xFCB3C480U, 0x0000000FU}, /*LSCHKINTENPER030*/ + [162] = {0xFCE90480U, 0x1E043FCFU}, /*LSCHKINTENHSC0*/ + [163] = {0xFCE90484U, 0x00000418U}, /*LSCHKINTENHSC1*/ + [164] = {0xFC8F8480U, 0x711E2307U}, /*LSCHKINTENVIO00*/ + [165] = {0xFC8F8484U, 0x000E0400U}, /*LSCHKINTENVIO01*/ + [166] = {0xFC8F0480U, 0xA0040003U}, /*LSCHKINTENVIO10*/ + [167] = {0xFC8F0484U, 0x0031B368U}, /*LSCHKINTENVIO11*/ + [168] = {0xFC8FC480U, 0x00000003U}, /*LSCHKINTENVIO20*/ + [169] = {0xFC010480U, 0x7EF0A3A3U}, /*LSCHKINTENVC00*/ + [170] = {0xFC010484U, 0x00000D96U}, /*LSCHKINTENVC01*/ + [171] = {0xFF8E0480U, 0x4033D0FFU}, /*LSCHKINTENIR0*/ + [172] = {0xFF8E0484U, 0x003F33FCU}, /*LSCHKINTENIR1*/ + [173] = {0xFC2F0480U, 0x00057FFFU}, /*LSCHKINTENVIP00*/ + [174] = {0xFC2F0484U, 0x00000000U}, /*LSCHKINTENVIP01*/ + [175] = {0xFC640480U, 0x0000063FU}, /*LSCHKINTEN3DG0*/ + [176] = {0xFC480480U, 0x3FFFFFFFU}, /*LSCHKINTENDSP0*/ + [177] = {0xFF840700U, 0x0000001EU}, /*OTHINTENTOP00*/ + [178] = {0xFDDFC700U, 0x008FCFFFU}, /*OTHINTENMM0*/ + [179] = {0xFD800700U, 0x00FFFFF0U}, /*OTHINTENRT00*/ + [180] = {0xFCB30700U, 0x0000003CU}, /*OTHINTENPER000*/ + [181] = {0xFCE90700U, 0x0000003CU}, /*OTHINTENHSC0*/ + [182] = {0xFC8F8700U, 0x00000000U}, /*OTHINTENVIO00*/ + [183] = {0xFC8F0700U, 0x0000007CU}, /*OTHINTENVIO10*/ + [184] = {0xFC010700U, 0x000000F0U}, /*OTHINTENVC00*/ + [185] = {0xFF8E0700U, 0x000000F0U}, /*OTHINTENIR0*/ + [186] = {0xFC2F0700U, 0x00000FC0U}, /*OTHINTENVIP00*/ + [187] = {0xFC640700U, 0x00000024U}, /*OTHINTEN3DG0*/ + [188] = {0xFF840400U, 0xC5001FFFU}, /*ROUINTENTOP00*/ + [189] = {0xFF840404U, 0xC8B3458FU}, /*ROUINTENTOP01*/ + [190] = {0xFF840408U, 0x8000F3E7U}, /*ROUINTENTOP02*/ + [191] = {0xFDA72400U, 0xFE7F7FFFU}, /*ROUINTENTOP10*/ + [192] = {0xFDA72404U, 0x0039FDFFU}, /*ROUINTENTOP11*/ + [193] = {0xFF848400U, 0x0000007FU}, /*ROUINTENTOP20*/ + [194] = {0xFF844400U, 0x0035F5D7U}, /*ROUINTENTOP30*/ + [195] = {0xFDDFC400U, 0xFBFFFFADU}, /*ROUINTENMM0*/ + [196] = {0xFDDFC404U, 0xFFFFBFEFU}, /*ROUINTENMM1*/ + [197] = {0xFDDFC408U, 0xFFFFF7FEU}, /*ROUINTENMM2*/ + [198] = {0xFDDFC40CU, 0x01FFFFFFU}, /*ROUINTENMM3*/ + [199] = {0xFD800400U, 0x007F403FU}, /*ROUINTENRT00*/ + [200] = {0xFD800404U, 0x40000040U}, /*ROUINTENRT01*/ + [201] = {0xFD800408U, 0x7BFFFFFFU}, /*ROUINTENRT02*/ + [202] = {0xFD80040CU, 0xFFFFE387U}, /*ROUINTENRT03*/ + [203] = {0xFD800410U, 0x68006F87U}, /*ROUINTENRT04*/ + [204] = {0xFD800414U, 0xFFFFFFFEU}, /*ROUINTENRT05*/ + [205] = {0xFD800418U, 0x077E30FFU}, /*ROUINTENRT06*/ + [206] = {0xFD804400U, 0x001E3C78U}, /*ROUINTENRT10*/ + [207] = {0xFD808400U, 0x0000034DU}, /*ROUINTENRT20*/ + [208] = {0xFD80C400U, 0x7FFE3FFFU}, /*ROUINTENRT30*/ + [209] = {0xFD80C404U, 0x00000000U}, /*ROUINTENRT31*/ + [210] = {0xFCB30400U, 0x00800007U}, /*ROUINTENPER000*/ + [211] = {0xFCB30404U, 0x00000000U}, /*ROUINTENPER001*/ + [212] = {0xFCB30408U, 0xFDB01C80U}, /*ROUINTENPER002*/ + [213] = {0xFCB3040CU, 0xC771EFFFU}, /*ROUINTENPER003*/ + [214] = {0xFCB30410U, 0x020FDEE4U}, /*ROUINTENPER004*/ + [215] = {0xFCB30414U, 0xFFBDE010U}, /*ROUINTENPER005*/ + [216] = {0xFCB30418U, 0x010023FFU}, /*ROUINTENPER006*/ + [217] = {0xFCB3041CU, 0x0000005EU}, /*ROUINTENPER007*/ + [218] = {0xFCB34400U, 0xFFF1EF1EU}, /*ROUINTENPER010*/ + [219] = {0xFCB34404U, 0x0000003FU}, /*ROUINTENPER011*/ + [220] = {0xFCB38400U, 0x0FFFFFFFU}, /*ROUINTENPER020*/ + [221] = {0xFCB3C400U, 0xFFFFFFFFU}, /*ROUINTENPER030*/ + [222] = {0xFCB3C404U, 0xFE0FFFFFU}, /*ROUINTENPER031*/ + [223] = {0xFCB3C408U, 0x00000083U}, /*ROUINTENPER032*/ + [224] = {0xFCE90400U, 0xEFE1D3F3U}, /*ROUINTENHSC0*/ + [225] = {0xFCE90404U, 0x00004001U}, /*ROUINTENHSC1*/ + [226] = {0xFCE90408U, 0x0FFB1004U}, /*ROUINTENHSC2*/ + [227] = {0xFCE9040CU, 0x4C010049U}, /*ROUINTENHSC3*/ + [228] = {0xFCE90410U, 0x00000807U}, /*ROUINTENHSC4*/ + [229] = {0xFC8F8400U, 0x7FFFFBE1U}, /*ROUINTENVIO00*/ + [230] = {0xFC8F8404U, 0x00001000U}, /*ROUINTENVIO01*/ + [231] = {0xFC8F8408U, 0xF8000000U}, /*ROUINTENVIO02*/ + [232] = {0xFC8F840CU, 0x18000079U}, /*ROUINTENVIO03*/ + [233] = {0xFC8F8410U, 0x20600000U}, /*ROUINTENVIO04*/ + [234] = {0xFC8F8414U, 0x0000000CU}, /*ROUINTENVIO05*/ + [235] = {0xFC8F8418U, 0xFFFE0002U}, /*ROUINTENVIO06*/ + [236] = {0xFC8F0400U, 0x2000034DU}, /*ROUINTENVIO10*/ + [237] = {0xFC8F0404U, 0x4D15E1C6U}, /*ROUINTENVIO11*/ + [238] = {0xFC8F0408U, 0x000078E3U}, /*ROUINTENVIO12*/ + [239] = {0xFC8F040CU, 0x00000000U}, /*ROUINTENVIO13*/ + [240] = {0xFC8F0410U, 0x3C000000U}, /*ROUINTENVIO14*/ + [241] = {0xFC8F0414U, 0x0E028000U}, /*ROUINTENVIO15*/ + [242] = {0xFC8F0418U, 0x0000001CU}, /*ROUINTENVIO16*/ + [243] = {0xFC8FC400U, 0x002962B1U}, /*ROUINTENVIO20*/ + [244] = {0xFC010400U, 0x00000000U}, /*ROUINTENVC00*/ + [245] = {0xFC010404U, 0x38001860U}, /*ROUINTENVC01*/ + [246] = {0xFC010408U, 0xE1C0033CU}, /*ROUINTENVC02*/ + [247] = {0xFC01040CU, 0x7EFFF3FDU}, /*ROUINTENVC03*/ + [248] = {0xFC010410U, 0x000001F7U}, /*ROUINTENVC04*/ + [249] = {0xFF8E0400U, 0x883CEF3EU}, /*ROUINTENIR0*/ + [250] = {0xFF8E0404U, 0x087C821EU}, /*ROUINTENIR1*/ + [251] = {0xFF8E0408U, 0xFFFD0F42U}, /*ROUINTENIR2*/ + [252] = {0xFF8E040CU, 0x000001B6U}, /*ROUINTENIR3*/ + [253] = {0xFC2F0400U, 0x70010B6EU}, /*ROUINTENVIP00*/ + [254] = {0xFC2F0404U, 0x9C07C003U}, /*ROUINTENVIP01*/ + [255] = {0xFC2F0408U, 0x00EE96E1U}, /*ROUINTENVIP02*/ + [256] = {0xFC2F040CU, 0x00000000U}, /*ROUINTENVIP03*/ + [257] = {0xFC2F0410U, 0x00000000U}, /*ROUINTENVIP04*/ + [258] = {0xFC2F0414U, 0x01500000U}, /*ROUINTENVIP05*/ + [259] = {0xFC640400U, 0x03FC02FEU}, /*ROUINTEN3DG0*/ + [260] = {0xFC640404U, 0x000007FFU}, /*ROUINTEN3DG1*/ + [261] = {0xFC480400U, 0xFFFFFFFFU}, /*ROUINTENDSP0*/ + [262] = {0xFF840500U, 0x3F5FF3FFU}, /*RSCHKINTENTOP00*/ + [263] = {0xFF840504U, 0x603FFE73U}, /*RSCHKINTENTOP01*/ + [264] = {0xFF840508U, 0x0001C000U}, /*RSCHKINTENTOP02*/ + [265] = {0xFDA72500U, 0x00000001U}, /*RSCHKINTENTOP10*/ + [266] = {0xFF848500U, 0x0000001FU}, /*RSCHKINTENTOP20*/ + [267] = {0xFF844500U, 0x00001AD9U}, /*RSCHKINTENTOP30*/ + [268] = {0xFDDFC500U, 0xFFFFFFFFU}, /*RSCHKINTENMM0*/ + [269] = {0xFDDFC504U, 0x00000007U}, /*RSCHKINTENMM1*/ + [270] = {0xFD800500U, 0x7FFFF7FFU}, /*RSCHKINTENRT00*/ + [271] = {0xFD800504U, 0xFAB58006U}, /*RSCHKINTENRT01*/ + [272] = {0xFD800508U, 0x000013A1U}, /*RSCHKINTENRT02*/ + [273] = {0xFD804500U, 0x000007F8U}, /*RSCHKINTENRT10*/ + [274] = {0xFD808500U, 0x000000FDU}, /*RSCHKINTENRT20*/ + [275] = {0xFD80C500U, 0x00000001U}, /*RSCHKINTENRT30*/ + [276] = {0xFCB30500U, 0xF7F10F1FU}, /*RSCHKINTENPER000*/ + [277] = {0xFCB30504U, 0x000FBCFDU}, /*RSCHKINTENPER001*/ + [278] = {0xFCB34500U, 0x000000FAU}, /*RSCHKINTENPER010*/ + [279] = {0xFCB38500U, 0x00000003U}, /*RSCHKINTENPER020*/ + [280] = {0xFCB3C500U, 0x0000003FU}, /*RSCHKINTENPER030*/ + [281] = {0xFCE90500U, 0x93FF7F7FU}, /*RSCHKINTENHSC0*/ + [282] = {0xFCE90504U, 0x001FE067U}, /*RSCHKINTENHSC1*/ + [283] = {0xFC8F8500U, 0xFEFFC003U}, /*RSCHKINTENVIO00*/ + [284] = {0xFC8F8504U, 0x0801C03FU}, /*RSCHKINTENVIO01*/ + [285] = {0xFC8F0500U, 0xDF793FFFU}, /*RSCHKINTENVIO10*/ + [286] = {0xFC8F0504U, 0x041A001EU}, /*RSCHKINTENVIO11*/ + [287] = {0xFC8FC500U, 0x00000004U}, /*RSCHKINTENVIO20*/ + [288] = {0xFC010500U, 0xFEBB663FU}, /*RSCHKINTENVC00*/ + [289] = {0xFC010504U, 0x0000077FU}, /*RSCHKINTENVC01*/ + [290] = {0xFF8E0500U, 0x3E7FEE0FU}, /*RSCHKINTENIR0*/ + [291] = {0xFF8E0504U, 0x0000FFFFU}, /*RSCHKINTENIR1*/ + [292] = {0xFC2F0500U, 0x0003FDF8U}, /*RSCHKINTENVIP00*/ + [293] = {0xFC2F0504U, 0x000FF000U}, /*RSCHKINTENVIP01*/ + [294] = {0xFC640500U, 0x000001DFU}, /*RSCHKINTEN3DG0*/ + [295] = {0xFC480500U, 0x0001FFFFU}, /*RSCHKINTENDSP0*/ + [296] = {0xFF840540U, 0x0000000EU}, /*TIDINTENTOP00*/ + [297] = {0xFF848540U, 0x00000007U}, /*TIDINTENTOP20*/ + [298] = {0xFDDFC540U, 0x00003FFFU}, /*TIDINTENMM0*/ + [299] = {0xFD800540U, 0x0167CC7CU}, /*TIDINTENRT00*/ + [300] = {0xFD800544U, 0x00000020U}, /*TIDINTENRT01*/ + [301] = {0xFD804540U, 0x00000033U}, /*TIDINTENRT10*/ + [302] = {0xFD808540U, 0x00000036U}, /*TIDINTENRT20*/ + [303] = {0xFCB30540U, 0x0003BF70U}, /*TIDINTENPER000*/ + [304] = {0xFCB34540U, 0x0000000FU}, /*TIDINTENPER010*/ + [305] = {0xFCE90540U, 0x0210247BU}, /*TIDINTENHSC0*/ + [306] = {0xFC8F8540U, 0x1CC0C703U}, /*TIDINTENVIO00*/ + [307] = {0xFC8F8544U, 0x00000003U}, /*TIDINTENVIO01*/ + [308] = {0xFC8F0540U, 0x94000000U}, /*TIDINTENVIO10*/ + [309] = {0xFC8F0544U, 0x0000002AU}, /*TIDINTENVIO11*/ + [310] = {0xFC010540U, 0x3366CD90U}, /*TIDINTENVC00*/ + [311] = {0xFF8E0540U, 0x000C1E60U}, /*TIDINTENIR0*/ + [312] = {0xFC2F0540U, 0x000007EDU}, /*TIDINTENVIP00*/ + [313] = {0xFC640540U, 0x00000011U}, /*TIDINTEN3DG0*/ + [314] = {0xFC480540U, 0x00000000U}, /*TIDINTENDSP0*/ + [315] = {0xFF840640U, 0x00000002U}, /*SAFERRINTENTOP00*/ + [316] = {0xFDA72640U, 0x00000001U}, /*SAFERRINTENTOP10*/ + [317] = {0xFF848640U, 0x00000000U}, /*SAFERRINTENTOP20*/ + [318] = {0xFF844640U, 0x00000001U}, /*SAFERRINTENTOP30*/ + [319] = {0xFDDFC640U, 0x00000007U}, /*SAFERRINTENMM0*/ + [320] = {0xFD800640U, 0x0000001DU}, /*SAFERRINTENRT00*/ + [321] = {0xFD804640U, 0x00000001U}, /*SAFERRINTENRT10*/ + [322] = {0xFD808640U, 0x00000001U}, /*SAFERRINTENRT20*/ + [323] = {0xFD80C640U, 0x00000001U}, /*SAFERRINTENRT30*/ + [324] = {0xFCB30640U, 0x00000004U}, /*SAFERRINTENPER000*/ + [325] = {0xFCB34640U, 0x00000001U}, /*SAFERRINTENPER010*/ + [326] = {0xFCB38640U, 0x00000001U}, /*SAFERRINTENPER020*/ + [327] = {0xFCB3C640U, 0x00000001U}, /*SAFERRINTENPER030*/ + [328] = {0xFCE90640U, 0x00000001U}, /*SAFERRINTENHSC0*/ + [329] = {0xFC8F8640U, 0x00000001U}, /*SAFERRINTENVIO00*/ + [330] = {0xFC8F0640U, 0x00000002U}, /*SAFERRINTENVIO10*/ + [331] = {0xFC8FC640U, 0x00000001U}, /*SAFERRINTENVIO20*/ + [332] = {0xFC010640U, 0x00000001U}, /*SAFERRINTENVC00*/ + [333] = {0xFF8E0640U, 0x00000001U}, /*SAFERRINTENIR0*/ + [334] = {0xFC2F0640U, 0x00000001U}, /*SAFERRINTENVIP00*/ + [335] = {0xFC640640U, 0x00000001U}, /*SAFERRINTEN3DG0*/ + [336] = {0xFC480640U, 0x00000001U}, /*SAFERRINTENDSP0*/ + [337] = {0xFF8404C0U, 0x00000192U}, /*WCRCINTENTOP00*/ + [338] = {0xFDDFC4C0U, 0x07FFBDFFU}, /*WCRCINTENMM0*/ + [339] = {0xFD8004C0U, 0x207F3F3BU}, /*WCRCINTENRT00*/ + [340] = {0xFD8004C4U, 0x00000014U}, /*WCRCINTENRT01*/ + [341] = {0xFD8044C0U, 0x00000783U}, /*WCRCINTENRT10*/ + [342] = {0xFD8084C0U, 0x00000000U}, /*WCRCINTENRT20*/ + [343] = {0xFCB304C0U, 0x000027DFU}, /*WCRCINTENPER000*/ + [344] = {0xFCB344C0U, 0x00000003U}, /*WCRCINTENPER010*/ + [345] = {0xFCE904C0U, 0x000041BBU}, /*WCRCINTENHSC0*/ + [346] = {0xFC8F84C0U, 0x0000C703U}, /*WCRCERRINTENVIO00*/ + [347] = {0xFC8F04C0U, 0x0016840FU}, /*WCRCERRINTENVIO10*/ + [348] = {0xFC0104C0U, 0x00347D59U}, /*WCRCERRINTENVC00*/ + [349] = {0xFF8E04C0U, 0x3FFE03D0U}, /*WCRCERRINTENIR0*/ + [350] = {0xFC2F04C0U, 0x070031FDU}, /*WCRCERRINTENVIP00*/ + [351] = {0xFC6404C0U, 0x00000063U}, /*WCRCERRINTEN3DG0*/ + [352] = {0xFC4804C0U, 0x00007FFFU}, /*WCRCINTENDSP0*/ + [353] = {0xFF840600U, 0x00000002U}, /*SECERRINTENTOP00*/ + [354] = {0xFDA72600U, 0x00000001U}, /*SECERRINTENTOP10*/ + [355] = {0xFF848600U, 0x00000000U}, /*SECERRINTENTOP20*/ + [356] = {0xFF844600U, 0x00000001U}, /*SECERRINTENTOP30*/ + [357] = {0xFDDFC600U, 0x00000007U}, /*SECERRINTENMM0*/ + [358] = {0xFD800600U, 0x0000001DU}, /*SECERRINTENRT00*/ + [359] = {0xFD804600U, 0x00000001U}, /*SECERRINTENRT10*/ + [360] = {0xFD808600U, 0x00000001U}, /*SECERRINTENRT20*/ + [361] = {0xFD80C600U, 0x00000001U}, /*SECERRINTENRT30*/ + [362] = {0xFCB30600U, 0x00000004U}, /*SECERRINTENPER000*/ + [363] = {0xFCB34600U, 0x00000001U}, /*SECERRINTENPER010*/ + [364] = {0xFCB38600U, 0x00000001U}, /*SECERRINTENPER020*/ + [365] = {0xFCB3C600U, 0x00000001U}, /*SECERRINTENPER030*/ + [366] = {0xFCE90600U, 0x00000001U}, /*SECERRINTENHSC0*/ + [367] = {0xFC8F8600U, 0x00000001U}, /*SECERRINTENVIO00*/ + [368] = {0xFC8F0600U, 0x00000002U}, /*SECERRINTENVIO10*/ + [369] = {0xFC8FC600U, 0x00000001U}, /*SECERRINTENVIO20*/ + [370] = {0xFC010600U, 0x00000001U}, /*SECERRINTENVC00*/ + [371] = {0xFF8E0600U, 0x00000001U}, /*SECERRINTENIR0*/ + [372] = {0xFC2F0600U, 0x00000001U}, /*SECERRINTENVIP00*/ + [373] = {0xFC640600U, 0x00000001U}, /*SECERRINTEN3DG0*/ + [374] = {0xFC480600U, 0x00000001U}, /*SECERRINTENDSP0*/ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX] = { + [0] = {0xFC480570U, 0x00000002U}, /* IMRGID_IPMMU_VI0 */ + [1] = {0xFC4C0570U, 0x00000002U}, /* IMRGID_IPMMU_VI1 */ + [2] = {0xFC3C0570U, 0x00000002U}, /* IMRGID_IPMMU_VC0 */ + [3] = {0xFC380570U, 0x00000002U}, /* IMRGID_IPMMU_IR */ + [4] = {0xFC080570U, 0x00000001U}, /* IMRGID_IPMMU_RT0 */ + [5] = {0xFC0C0570U, 0x00000001U}, /* IMRGID_IPMMU_RT1 */ + [6] = {0xFC300570U, 0x00000001U}, /* IMRGID_IPMMU_DS0 */ + [7] = {0xFC340570U, 0x00000001U}, /* IMRGID_IPMMU_HSC */ + [8] = {0xFC500570U, 0x00000002U}, /* IMRGID_IPMMU_VIP0 */ + [9] = {0xFC400570U, 0x00000002U}, /* IMRGID_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX] = { + [0] = {0xFC480578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI0 */ + [1] = {0xFC4C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI1 */ + [2] = {0xFC3C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VC0 */ + [3] = {0xFC380578U, 0x00000001U}, /* IMSECGRP_IPMMU_IR */ + [4] = {0xFC080578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT0 */ + [5] = {0xFC0C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT1 */ + [6] = {0xFC300578U, 0x00000001U}, /* IMSECGRP_IPMMU_DS0 */ + [7] = {0xFC340578U, 0x00000001U}, /* IMSECGRP_IPMMU_HSC */ + [8] = {0xFC500578U, 0x00000001U}, /* IMSECGRP_IPMMU_VIP0 */ + [9] = {0xFC400578U, 0x00000001U}, /* IMSECGRP_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX] = { + [0] = {0xFC480574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI0 */ + [1] = {0xFC4C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI1 */ + [2] = {0xFC3C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VC0 */ + [3] = {0xFC380574U, 0x00000002U}, /* IMRGIDEN_IPMMU_IR */ + [4] = {0xFC080574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT0 */ + [5] = {0xFC0C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT1 */ + [6] = {0xFC300574U, 0x00000002U}, /* IMRGIDEN_IPMMU_DS0 */ + [7] = {0xFC340574U, 0x00000002U}, /* IMRGIDEN_IPMMU_HSC */ + [8] = {0xFC500574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VIP0 */ + [9] = {0xFC400574U, 0x00000002U}, /* IMRGIDEN_IPMMU_3DG */ +}; + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/common/log/log.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/common/log/log.c new file mode 100644 index 0000000..bf46cab --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/common/log/log.c @@ -0,0 +1,100 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Log driver + ******************************************************************************/ +/****************************************************************************** + * @file log.c + * - Version : 0.03 + * @brief Log driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 06.01.2022 0.02 Static analysis support + * : 04,04,2023 0.03 Fixed to not use the standard input/output + * library when LOG_LEVEL=0. + *****************************************************************************/ + +#include +#include +#include + +#if LOG_LEVEL >= LOG_ERROR +#include + +#define VSPRINTF_OK (0) + +void local_printf(const char *fmt, ...) +{ + va_list ap; + static char s_buffer[1024]; + int32_t num; + uint32_t loop; + + /* Convert all arguments to one string */ + va_start(ap, fmt); + num = vsprintf(s_buffer, fmt, ap); + va_end(ap); + + /* String output */ + if (VSPRINTF_OK <= num) + { + for (loop = 0U; loop < num; loop++) + { + (void)console_putc((uint8_t)s_buffer[loop]); + /* If the outputted character is LF, output CR */ + if (s_buffer[loop] == 0x0A) /* \n */ + { + (void)console_putc((uint8_t)'\r'); + } + } + } + else + { + while(1) + { + /* loop due to error detection. */ + } + } +} +/* End of function local_printf(const char *fmt, ...) */ +#endif + +void panic_printf(const char *str) +{ + const uint8_t *p = (const uint8_t *)str; + + /* Output one character at a time until the data in the argument is null-terminated string. */ + while(*p != (uint8_t)'\0') + { + (void)console_putc(*p); + p++; + } + /* output character is CR and LF */ + (void)console_putc((uint8_t)'\r'); + (void)console_putc((uint8_t)'\n'); +} +/* End of function panic_printf(const char *str) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/common/log/scif.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/common/log/scif.c new file mode 100644 index 0000000..72f497e --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/common/log/scif.c @@ -0,0 +1,618 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : SCIF driver + ******************************************************************************/ +/****************************************************************************** + * @file scif.c + * - Version : 0.08 + * @brief 1. Initial setting of SCIF. + * 2. Initial setting of HSCIF. + * 3. Log output function. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Modify the timing of MODEMR judgement. + * : 15.10.2021 0.03 Modify register access to read modify write. + * : 03.12.2021 0.04 Fix incorrect configuration process. + * : 06.01.2022 0.05 Static analysis support + * : 23.05.2022 0.06 Integration of S4 and V4H + * : 20.12.2022 0.07 Modify writing bit size to SCBRR register. + * : 21.08.2023 0.08 Add support for V4M. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Define */ +#define SCIF_SCSCR_TE_EN (uint16_t)((uint16_t)1U << 5U) +#define SCIF_SCSCR_RE_EN (uint16_t)((uint16_t)1U << 4U) +#define SCIF_SCSCR_CKE_EXT_CLK (uint16_t)((uint16_t)2U << 0U) +#define SCIF_SCSCR_INIT_DATA (uint16_t)(SCIF_SCSCR_TE_EN | SCIF_SCSCR_RE_EN) +#define SCIF_SCSCR_HW_INIT (uint16_t)(0x0000U) + +#define SCIF_SCFCR_TFRST_EN (uint16_t)((uint16_t)1U << 2U) +#define SCIF_SCFCR_RFRS_EN (uint16_t)((uint16_t)1U << 1U) +#define SCIF_SCFCR_RESET_FIFO (uint16_t)(SCIF_SCFCR_TFRST_EN | SCIF_SCFCR_RFRS_EN) + +#define SCIF_SCFSR_TEND (uint16_t)((uint16_t)1U << 6U) +#define SCIF_SCFSR_TDFE (uint16_t)((uint16_t)1U << 5U) +#define TRANS_END_CHECK (uint16_t)(SCIF_SCFSR_TEND | SCIF_SCFSR_TDFE) +#define SCIF_SCFSR_INIT_DATA (uint16_t)(0x0000U) + +#define SCIF_SCLSR_INIT_DATA (uint16_t)(0x0000U) + +#define SCIF_SCSMR_CHR (uint16_t)((uint16_t)1U << 6U) +#define SCIF_SCSMR_PE (uint16_t)((uint16_t)1U << 5U) +#define SCIF_SCSMR_STOP (uint16_t)((uint16_t)1U << 3U) +#define SCIF_SCSMR_CKS (uint16_t)((uint16_t)3U << 0U) +#define SCIF_SCSMR_INIT_DATA ~((uint16_t)(SCIF_SCSMR_CHR | SCIF_SCSMR_PE | SCIF_SCSMR_STOP | SCIF_SCSMR_CKS)) + +/* Pclk(66MHz)/1, 115.2kbps*/ +/* N = 66/(66/2*115200)*10^4-1 =17=> 0x11 */ +#define SCIF_SCBRR_115200BPS (uint8_t)(0x11U) +/* Pclk(266MHz)/1, 921.6kbps*/ +/* N = 266/(8*2*921600)*10^6-1 =17=> 0x11 */ +#define HSCIF_SCBRR_921600BPS (uint8_t)(0x11U) +/* Pclk(266MHz)/1, 1.8432Mbps*/ +/* N = 266/(8*2*1843200)*10^6-1 =8=> 0x08 */ +#define HSCIF_SCBRR_1843200BPS (uint8_t)(0x08U) + +#define HSCIF_HSSRR_SRE (uint16_t)(1U << 15U) +#define HSCIF_HSSRR_SRCYC (uint16_t)(0x1FU << 0U) +#define HSCIF_HSSRR_SRCYC8 (uint16_t)(7U << 0U) /* Sampling rate 8-1 */ +#define HSCIF_HSSRR_VAL (uint16_t)(HSCIF_HSSRR_SRE | HSCIF_HSSRR_SRCYC8) + +#define HSCIF_DL_DIV1 (uint16_t)(1U << 0U) +#define HSCIF_CKS_CKS (uint16_t)(1U << 15U) +#define HSCIF_CKS_XIN (uint16_t)(1U << 14U) +#define HSCIF_CKS_SC_CLK_EXT ~((uint16_t)(HSCIF_CKS_CKS | HSCIF_CKS_XIN)) + +/* module start setting value */ +#if (RCAR_LSI == RCAR_S4) +#define CPG_MSTPCR_HSCIF (((uint32_t)1U) << 14U) +#define CPG_MSTPCR_SCIF (((uint32_t)1U) << 4U) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define CPG_MSTPCR_HSCIF (((uint32_t)1U) << 14U) +#define CPG_MSTPCR_SCIF (((uint32_t)1U) << 2U) +#endif /* RCAR_LSI == RCAR_S4 */ + +/* Pin function setting value */ +#if (RCAR_LSI == RCAR_S4) +#define GPSR_TX ((uint32_t)1U << 3U) /* HTX0 / TX3 */ +#define GPSR_RX ((uint32_t)1U << 2U) /* HRX0 / RX3 */ +#define IPSR_RX_VAL ((uint32_t)1U << 8U) /* RX3 */ +#define IPSR_TX_VAL ((uint32_t)1U << 12U) /* TX3 */ +#define POC_TX_33V ((uint32_t)1U << 3U) /* HTX0 / TX3 3.3V setting value */ +#define POC_RX_33V ((uint32_t)1U << 2U) /* HRX0 / RX3 3.3V setting value */ +#define IPSR_RX_MASK ((uint32_t)0xFU << 8U) /* IPSR bit[11:8] */ +#define IPSR_TX_MASK ((uint32_t)0xFU << 12U) /* IPSR bit[15:12] */ +#define PFC_GPSR_SCIF_MASK (uint32_t)(0x0000000CU) /* SCIF3/HSCIF0 RX/TX */ +#define PFC_GPSR_SCIF_VAL (uint32_t)(GPSR_TX | GPSR_RX) /* SCIF3/HSCIF0 RX/TX */ +#define PFC_IPSR_SCIF_MASK (uint32_t)(IPSR_RX_MASK | IPSR_TX_MASK) /* Mask value of IPSR (SCIF3/HSCIF0 RX/TX) */ +#define PFC_IPSR_SCIF_VAL (uint32_t)(IPSR_RX_VAL | IPSR_TX_VAL) /* SCIF3 RX/TX */ +#define PFC_IPSR_HSCIF_VAL (uint32_t)(0x00000000U) /* HSCIF0 RX/TX */ +#define PFC_POC_SCIF_MASK (uint32_t)(0x0000000CU) /* SCIF3/HSCIF0 RX/TX */ +#define PFC_POC_SCIF_33V (uint32_t)(POC_TX_33V | POC_RX_33V) /* SCIF3/HSCIF0 RX/TX */ +#define PFC_IPSR_SCIF_EXTCLK_MASK (uint32_t)(0xFU << 0U) /* Mask value of IPSR (External Clock) */ +#define PFC_IPSR_SCIF_EXTCLK_VAL (uint32_t)(0x0U << 0U) /* IPSR (External Clock) */ +#define PFC_GPSR_SCIF_EXTCLK_MASK (uint32_t)(0x00000001U) /* Mask value of IPSR (External Clock) */ +#define PFC_GPSR_SCIF_EXTCLK_VAL (uint32_t)(1U << 0U) /* IPSR (External Clock) */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define GPSR_TX ((uint32_t)1U << 12U) /* HTX0 / TX0 */ +#define GPSR_RX ((uint32_t)1U << 16U) /* HRX0 / RX0 */ +#define IPSR_RX_VAL ((uint32_t)1U << 0U) /* RX0 */ +#define IPSR_TX_VAL ((uint32_t)1U << 16U) /* TX0 */ +#define POC_TX_33V ((uint32_t)1U << 12U) /* HTX0 / TX0 3.3V setting value */ +#define POC_RX_33V ((uint32_t)1U << 16U) /* HRX0 / RX0 3.3V setting value */ +#define POC_TX_18V ((uint32_t)0U << 12U) /* HTX0 / TX0 1.8V setting value */ +#define POC_RX_18V ((uint32_t)0U << 16U) /* HRX0 / RX0 1.8V setting value */ +#define IPSR_RX_MASK ((uint32_t)0xFU << 0U) /* IPSR bit[3:0] */ +#define IPSR_TX_MASK ((uint32_t)0xFU << 16U) /* IPSR bit[19:16] */ +#define PFC_GPSR_SCIF_MASK (uint32_t)(0x00011000U) /* SCIF0/HSCIF0 RX/TX */ +#define PFC_GPSR_SCIF_VAL (uint32_t)(GPSR_TX | GPSR_RX) /* SCIF0/HSCIF0 RX/TX */ +#define PFC_IPSR_SCIF_MASK1 (uint32_t)(IPSR_TX_MASK) /* Mask value of IPSR (SCIF0/HSCIF0 TX) */ +#define PFC_IPSR_SCIF_VAL1 (uint32_t)(IPSR_TX_VAL) /* SCIF0 TX */ +#define PFC_IPSR_SCIF_MASK2 (uint32_t)(IPSR_RX_MASK) /* Mask value of IPSR (SCIF3/HSCIF0 RX) */ +#define PFC_IPSR_SCIF_VAL2 (uint32_t)(IPSR_RX_VAL) /* SCIF0 RX */ +#define PFC_IPSR_HSCIF_VAL1 (uint32_t)(0x00000000U) /* HSCIF0 TX */ +#define PFC_IPSR_HSCIF_VAL2 (uint32_t)(0x00000000U) /* HSCIF0 RX */ +#define PFC_POC_SCIF_MASK (uint32_t)(0x00011000U) /* SCIF0/HSCIF0 RX/TX */ +#define PFC_POC_SCIF_33V (uint32_t)(POC_TX_33V | POC_RX_33V) /* SCIF0/HSCIF0 RX/TX */ +#define PFC_IPSR_SCIF_EXTCLK_MASK (uint32_t)(0xFU << 4U) /* Mask value of IPSR (External Clock) */ +#define PFC_IPSR_SCIF_EXTCLK_VAL (uint32_t)(0x0U << 4U) /* IPSR (External Clock) */ +#define PFC_GPSR_SCIF_EXTCLK_MASK (uint32_t)(0x00020000U) /* Mask value of IPSR (External Clock) */ +#endif /* RCAR_LSI == RCAR_S4 */ + +static void (*rcar_putc)(uint8_t outchar); + +static void scif_module_start(uint32_t modemr); +static void scif_pfc_init(uint32_t modemr); +static void scif_console_init(uint32_t modemr); +static void scif_console_putc(uint8_t outchar); +static void hscif_console_putc(uint8_t outchar); + + +static void scif_module_start(uint32_t modemr) +{ + uint32_t reg; + + if(modemr == MODEMR_SCIF_DLMODE) + { + reg = mem_read32(CPG_MSTPSR7D0); + /* If supply of clock to SCIF0 is stopped */ + if (FALSE != (CPG_MSTPCR_SCIF & reg)) + { + /* Supply of clock to SCIF0 is start */ + reg &= ~(CPG_MSTPCR_SCIF); + cpg_reg_write(CPG_MSTPCR7D0, CPG_MSTPSR7D0, reg); + } + } + else + { + reg = mem_read32(CPG_MSTPSR5D0); + /* If supply of clock to SCIF0 is stopped */ + if (FALSE != (CPG_MSTPCR_HSCIF & reg)) + { + /* Supply of clock to SCIF0 is start */ + reg &= ~(CPG_MSTPCR_HSCIF); + cpg_reg_write(CPG_MSTPCR5D0, CPG_MSTPSR5D0, reg); + } + } +} +/* End of function scif_module_start(void) */ + +static void scif_pfc_init(uint32_t modemr) +{ + uint32_t reg; + +#if (RCAR_LSI == RCAR_S4) + if(modemr == MODEMR_SCIF_DLMODE) + { + /* Set RX / TX of SCIF 0. */ + reg = mem_read32(PFC_IP0SR0_RW); + reg &= (~(PFC_IPSR_SCIF_MASK)); + reg |= PFC_IPSR_SCIF_VAL; + pfc_reg_write(PFC_IP0SR0_RW, reg); + + /* Set Voltage setting of 1.8V. */ + reg = mem_read32(PFC_POC0_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + pfc_reg_write(PFC_POC0_RW, reg); + } + else if(modemr == MODEMR_HSCIF_DLMODE_921600) + { + /* Set HRX / HTX of HSCIF 0. */ + reg = mem_read32(PFC_IP0SR0_RW); + reg &= (~(PFC_IPSR_SCIF_MASK)); + reg |= PFC_IPSR_HSCIF_VAL; + pfc_reg_write(PFC_IP0SR0_RW, reg); + + /* Set Voltage setting of 3.3V. */ + reg = mem_read32(PFC_POC0_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + reg |= PFC_POC_SCIF_33V; + pfc_reg_write(PFC_POC0_RW, reg); + } + else if(modemr == MODEMR_HSCIF_DLMODE_1843200) + { + /* Set HRX / HTX of HSCIF 0. */ + reg = mem_read32(PFC_IP0SR0_RW); + reg &= (~(PFC_IPSR_SCIF_MASK)); + reg |= PFC_IPSR_HSCIF_VAL; + pfc_reg_write(PFC_IP0SR0_RW, reg); + + /* Set Voltage setting of 1.8V. */ + reg = mem_read32(PFC_POC0_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + pfc_reg_write(PFC_POC0_RW, reg); + } + else if(modemr == MODEMR_HSCIF_DLMODE_3000000) + { + /* Set HRX / HTX of HSCIF 0. */ + reg = mem_read32(PFC_IP0SR0_RW); + reg &= (~(PFC_IPSR_SCIF_MASK)); + reg |= PFC_IPSR_HSCIF_VAL; + pfc_reg_write(PFC_IP0SR0_RW, reg); + + /* Set Voltage setting of 1.8V. */ + reg = mem_read32(PFC_POC0_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + pfc_reg_write(PFC_POC0_RW, reg); + + /* Set External Clock. */ + reg = mem_read32(PFC_IP0SR0_RW); + reg &= (~(PFC_IPSR_SCIF_EXTCLK_MASK)); + reg |= PFC_IPSR_SCIF_EXTCLK_VAL; + pfc_reg_write(PFC_IP0SR0_RW, reg); + + reg = mem_read32(PFC_GPSR0_RW); + reg &= (~(PFC_GPSR_SCIF_EXTCLK_MASK)); + reg |= PFC_GPSR_SCIF_EXTCLK_MASK; + pfc_reg_write(PFC_GPSR0_RW, reg); + } + else + { + /* no process */ + } + + reg = mem_read32(PFC_GPSR0_RW); + reg &= (~(PFC_GPSR_SCIF_MASK)); + reg |= PFC_GPSR_SCIF_VAL; + pfc_reg_write(PFC_GPSR0_RW, reg); + +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + if(modemr == MODEMR_SCIF_DLMODE) + { + /* Set TX of SCIF 0. */ + reg = mem_read32(PFC_IP1SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK1)); + reg |= PFC_IPSR_SCIF_VAL1; + pfc_reg_write(PFC_IP1SR1_RW, reg); + + /* Set RX of SCIF 0. */ + reg = mem_read32(PFC_IP2SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK2)); + reg |= PFC_IPSR_SCIF_VAL2; + pfc_reg_write(PFC_IP2SR1_RW, reg); + + /* Set Voltage setting of 1.8V. */ + reg = mem_read32(PFC_POC1_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + pfc_reg_write(PFC_POC1_RW, reg); + } + else if(modemr == MODEMR_HSCIF_DLMODE_921600) + { + /* Set HTX of HSCIF 0. */ + reg = mem_read32(PFC_IP1SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK1)); + reg |= PFC_IPSR_HSCIF_VAL1; + pfc_reg_write(PFC_IP1SR1_RW, reg); + + /* Set HRX of HSCIF 0. */ + reg = mem_read32(PFC_IP2SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK2)); + reg |= PFC_IPSR_HSCIF_VAL2; + pfc_reg_write(PFC_IP2SR1_RW, reg); + + /* Set Voltage setting of 3.3V. */ + reg = mem_read32(PFC_POC1_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + reg |= PFC_POC_SCIF_33V; + pfc_reg_write(PFC_POC1_RW, reg); + } + else if(modemr == MODEMR_HSCIF_DLMODE_1843200) + { + /* Set HTX of HSCIF 0. */ + reg = mem_read32(PFC_IP1SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK1)); + reg |= PFC_IPSR_HSCIF_VAL1; + pfc_reg_write(PFC_IP1SR1_RW, reg); + + /* Set HRX of HSCIF 0. */ + reg = mem_read32(PFC_IP2SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK2)); + reg |= PFC_IPSR_HSCIF_VAL2; + pfc_reg_write(PFC_IP2SR1_RW, reg); + + /* Set Voltage setting of 1.8V. */ + reg = mem_read32(PFC_POC1_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + pfc_reg_write(PFC_POC1_RW, reg); + } + else if(modemr == MODEMR_HSCIF_DLMODE_3000000) + { + /* Set HTX of HSCIF 0. */ + reg = mem_read32(PFC_IP1SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK1)); + reg |= PFC_IPSR_HSCIF_VAL1; + pfc_reg_write(PFC_IP1SR1_RW, reg); + + /* Set HRX of HSCIF 0. */ + reg = mem_read32(PFC_IP2SR1_RW); + reg &= (~(PFC_IPSR_SCIF_MASK2)); + reg |= PFC_IPSR_HSCIF_VAL2; + pfc_reg_write(PFC_IP2SR1_RW, reg); + + /* Set Voltage setting of 1.8V. */ + reg = mem_read32(PFC_POC1_RW); + reg &= (~(PFC_POC_SCIF_MASK)); + pfc_reg_write(PFC_POC1_RW, reg); + + /* Set External Clock. */ + reg = mem_read32(PFC_IP2SR1_RW); + reg &= (~(PFC_IPSR_SCIF_EXTCLK_MASK)); + reg |= PFC_IPSR_SCIF_EXTCLK_VAL; + pfc_reg_write(PFC_IP2SR1_RW, reg); + + reg = mem_read32(PFC_GPSR1_RW); + reg &= (~(PFC_GPSR_SCIF_EXTCLK_MASK)); + reg |= PFC_GPSR_SCIF_EXTCLK_MASK; + pfc_reg_write(PFC_GPSR1_RW, reg); + } + else + { + /* no process */ + } + + reg = mem_read32(PFC_GPSR1_RW); + reg &= (~(PFC_GPSR_SCIF_MASK)); + reg |= PFC_GPSR_SCIF_VAL; + pfc_reg_write(PFC_GPSR1_RW, reg); +#endif /* RCAR_LSI == RCAR_S4 */ +} +/* End of function scif_pfc_init(void) */ + +static void scif_console_init(uint32_t modemr) +{ + uint16_t reg; + switch(modemr) + { + case MODEMR_HSCIF_DLMODE_3000000: + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + reg = mem_read16(HSCIF_HSFCR); + reg |= SCIF_SCFCR_RESET_FIFO; + mem_write16(HSCIF_HSFCR, reg); + + /* clear ORER bit */ + mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA); + + /* external clock, SC_CLK pin used for output pin */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_CKE_EXT_CLK); + /* 8bit data, no-parity, 1 stop, Po/1 */ + reg = mem_read16(HSCIF_HSSMR); + reg &= SCIF_SCSMR_INIT_DATA; + mem_write16(HSCIF_HSSMR, reg); + + /* 24MHz / (3000000 * 8) = 1 */ + mem_write16(HSCIF_DL, HSCIF_DL_DIV1); + reg = mem_read16(HSCIF_CKS); + reg &= HSCIF_CKS_SC_CLK_EXT; + mem_write16(HSCIF_CKS, reg); + /* Sampling rate 8 */ + reg = mem_read16(HSCIF_HSSRR); + reg &= ~(HSCIF_HSSRR_SRE | HSCIF_HSSRR_SRCYC); + reg |= HSCIF_HSSRR_VAL; + mem_write16(HSCIF_HSSRR, reg); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + reg = mem_read16(HSCIF_HSFCR); + reg &= ~(SCIF_SCFCR_RESET_FIFO); + mem_write16(HSCIF_HSFCR, reg); + /* enable TE, RE; SC_CLK=external */ + reg = mem_read16(HSCIF_HSSCR); + reg |= SCIF_SCSCR_INIT_DATA; + mem_write16(HSCIF_HSSCR, reg); + + /* Set the pointer to a function that outputs one character. */ + rcar_putc = hscif_console_putc; + break; + } + case MODEMR_HSCIF_DLMODE_1843200: + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + reg = mem_read16(HSCIF_HSFCR); + reg |= SCIF_SCFCR_RESET_FIFO; + mem_write16(HSCIF_HSFCR, reg); + + /* clear ORER bit */ + mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA); + + /* internal clock, SC_CLK pin unused for output pin */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* 8bit data, no-parity, 1 stop, Po/1 */ + reg = mem_read16(HSCIF_HSSMR); + reg &= SCIF_SCSMR_INIT_DATA; + mem_write16(HSCIF_HSSMR, reg); + + /* Sampling rate 8 */ + mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL); + /* Baud rate 1843200bps*/ + mem_write8(HSCIF_HSBRR, HSCIF_SCBRR_1843200BPS); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + reg = mem_read16(HSCIF_HSFCR); + reg &= ~(SCIF_SCFCR_RESET_FIFO); + mem_write16(HSCIF_HSFCR, reg); + /* enable TE, RE; SC_CLK=external */ + reg = mem_read16(HSCIF_HSSCR); + reg |= SCIF_SCSCR_INIT_DATA; + mem_write16(HSCIF_HSSCR, reg); + + /* Set the pointer to a function that outputs one character. */ + rcar_putc = hscif_console_putc; + break; + } + case MODEMR_HSCIF_DLMODE_921600: + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + reg = mem_read16(HSCIF_HSFCR); + reg |= SCIF_SCFCR_RESET_FIFO; + mem_write16(HSCIF_HSFCR, reg); + + /* clear ORER bit */ + mem_write16(HSCIF_HSLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(HSCIF_HSFSR, SCIF_SCFSR_INIT_DATA); + + /* internal clock, SC_CLK pin unused for output pin */ + mem_write16(HSCIF_HSSCR, SCIF_SCSCR_HW_INIT); + /* 8bit data, no-parity, 1 stop, Po/1 */ + reg = mem_read16(HSCIF_HSSMR); + reg &= SCIF_SCSMR_INIT_DATA; + mem_write16(HSCIF_HSSMR, reg); + + /* Sampling rate 8 */ + mem_write16(HSCIF_HSSRR, HSCIF_HSSRR_VAL); + /* Baud rate 921600bps*/ + mem_write8(HSCIF_HSBRR, HSCIF_SCBRR_921600BPS); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + reg = mem_read16(HSCIF_HSFCR); + reg &= ~(SCIF_SCFCR_RESET_FIFO); + mem_write16(HSCIF_HSFCR, reg); + /* enable TE, RE; SC_CLK=external */ + reg = mem_read16(HSCIF_HSSCR); + reg |= SCIF_SCSCR_INIT_DATA; + mem_write16(HSCIF_HSSCR, reg); + + /* Set the pointer to a function that outputs one character. */ + rcar_putc = hscif_console_putc; + break; + } + case MODEMR_SCIF_DLMODE: + default: + { + /* clear SCR.TE & SCR.RE*/ + mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT); + /* reset tx-fifo, reset rx-fifo. */ + reg = mem_read16(SCIF_SCFCR); + reg |= SCIF_SCFCR_RESET_FIFO; + mem_write16(SCIF_SCFCR, reg); + + /* clear ORER bit */ + mem_write16(SCIF_SCLSR, SCIF_SCLSR_INIT_DATA); + /* clear all error bit */ + mem_write16(SCIF_SCFSR, SCIF_SCFSR_INIT_DATA); + + /* internal clock, SC_CLK pin unused for output pin */ + mem_write16(SCIF_SCSCR, SCIF_SCSCR_HW_INIT); + /* 8bit data, no-parity, 1 stop, Po/1 */ + reg = mem_read16(SCIF_SCSMR); + reg &= SCIF_SCSMR_INIT_DATA; + mem_write16(SCIF_SCSMR, reg); + + /* Baud rate 115200bps*/ + mem_write8(SCIF_SCBRR, SCIF_SCBRR_115200BPS); + + micro_wait(10U); /* 10us */ + + /* reset-off tx-fifo, rx-fifo. */ + reg = mem_read16(SCIF_SCFCR); + reg &= ~(SCIF_SCFCR_RESET_FIFO); + mem_write16(SCIF_SCFCR, reg); + /* enable TE, RE; SC_CLK=no output */ + reg = mem_read16(SCIF_SCSCR); + reg |= SCIF_SCSCR_INIT_DATA; + mem_write16(SCIF_SCSCR, reg); + + /* Set the pointer to a function that outputs one character. */ + rcar_putc = scif_console_putc; + break; + } + } +} +/* End of function scif_console_init(void) */ + +void scif_init(void) +{ + uint32_t modemr; + + modemr = ((mem_read32(RST_MODEMR0) & RST_MODEMR0_MD31) >> 31U); + modemr |= ((mem_read32(RST_MODEMR1) & RST_MODEMR1_MD32) << 1U); + + scif_module_start(modemr); + scif_pfc_init(modemr); + scif_console_init(modemr); +} +/* End of function scif_init(void) */ + +void console_putc(uint8_t outchar) +{ + rcar_putc(outchar); +} +/* End of function console_putc(void) */ + + +static void scif_console_putc(uint8_t outchar) +{ + uint16_t reg; + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK)) + { + ; + } + + mem_write8(SCIF_SCFTDR, outchar); /* Transfer one character */ + reg = mem_read16(SCIF_SCFSR); + reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */ + mem_write16(SCIF_SCFSR, reg); + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK)) + { + ; + } +} +/* End of function scif_console_putc(uint8_t outchar) */ + +static void hscif_console_putc(uint8_t outchar) +{ + uint16_t reg; + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK)) + { + ; + } + + mem_write8(HSCIF_HSFTDR, outchar); /* Transfer one character */ + reg = mem_read16(HSCIF_HSFSR); + reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */ + mem_write16(HSCIF_HSFSR, reg); + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK)) + { + ; + } +} +/* End of function hscif_console_putc(uint8_t outchar) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/common/timer/micro_wait.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/common/timer/micro_wait.c new file mode 100644 index 0000000..8aaaff5 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/common/timer/micro_wait.c @@ -0,0 +1,109 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Time wait driver + ******************************************************************************/ +/****************************************************************************** + * @file micro_wait.c + * - Version : 0.03 + * @brief Wait of micro second + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 15.10.2021 0.02 modify register access to read modify write. + * : 03.12.2021 0.03 fix incorrect configuration process. + *****************************************************************************/ + +#include +#include +#include + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + +#define INTICUOSTM0 (0xFFFEEA14U) +#define INTCR_RF ((uint16_t)1U << 12U) +#define INTCR_RF_NO_REQ ((uint16_t)0U << 12U) + +#define OSTM0_BASE (0xFFFEE000U) +#define OSTM0CMP (OSTM0_BASE) +#define OSTM0TS (OSTM0_BASE + 0x0014U) +#define OSTM0TT (OSTM0_BASE + 0x0018U) +#define OSTM0CTL (OSTM0_BASE + 0x0020U) + +#define OSTM0TS_TS (uint8_t)(0x01U) /* b0:1: Start */ +#define OSTM0TT_TT (uint8_t)(0x01U) /* b0:1: Stop */ +#define OSTM0CMP_MICRO_VALUE (0x00000190U) /* PCLK=400MHz(400=0x190 = 1us) */ + +#define OSTM0CTL_MD10 (uint8_t)(0x02U) /* b1:1: Free-run compare mode(Start:0 Counting Direction:up) */ + /* b0:0: Interrupts when counting starts are enabled */ + +#define MAX_MICRO_WAIT (10737418U) /* 0xFFFFFFFF / 400 */ + +void micro_wait(uint32_t count_us) +{ + uint32_t val; + uint16_t reg16; + uint8_t reg8; + + if (count_us != 0U) + { + /* When the timer count is an argument that exceeds 0xFFFFFFFF */ + if(MAX_MICRO_WAIT < count_us) + { + count_us = MAX_MICRO_WAIT; + } + val = count_us * OSTM0CMP_MICRO_VALUE; + /* timer start */ + reg8 = mem_read8(OSTM0TT); + reg8 |= OSTM0TT_TT; + mem_write8(OSTM0TT, reg8); + mem_write32(OSTM0CMP, val); + reg8 = mem_read8(OSTM0CTL); + reg8 |= OSTM0CTL_MD10; + mem_write8(OSTM0CTL, reg8); + reg8 = mem_read8(OSTM0TS); + reg8 |= OSTM0TS_TS; + mem_write8(OSTM0TS, reg8); + + while (1) + { + reg16 = mem_read16(INTICUOSTM0); + if ((reg16 & (INTCR_RF)) != INTCR_RF_NO_REQ) + { + /* timer stop */ + reg16 = (reg16 & (uint16_t)(~(INTCR_RF))); + mem_write16(INTICUOSTM0, reg16); + reg8 = mem_read8(OSTM0TT); + reg8 |= OSTM0TT_TT; + mem_write8(OSTM0TT, reg8); + break; + } + } + } +} +/* End of function micro_wait(uint32_t count_us) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cpu_on/cpu_on.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cpu_on/cpu_on.c new file mode 100644 index 0000000..203ed14 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/cpu_on/cpu_on.c @@ -0,0 +1,237 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Power management driver + ******************************************************************************/ + /****************************************************************************** + * @file cpu_on.c + * - Version : 0.09 + * @brief Boot process of ARM CPU core. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Modify macro definition name. + * : 08.09.2021 0.03 Removed the reset process of BOOT_CTRL and + * OPBT_CTRL register. + * : 06.01.2022 0.04 Static analysis support + * : 23.05.2022 0.05 Integration of S4 and V4H + * : 21.06.2022 0.06 Remove functions for MCU. + * : 21.08.2023 0.07 Add support for V4M. + * : 17.11.2023 0.08 Move a part of definitions to cpu_on.h. + * : 09.12.2024 0.09 Update OTP_MEM_OTPMONITOR60 register to + * OTP_MEM_OTPMONITOR17 register for V4M. + * And Improve the adj_cr_variant_freq function. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* ARM */ +#define CA_CORE0_WUP_REQ (0x00000001U) +#define CA_CORE0_VLD_RVBARP (0x00000001U) +#define CR_VLD_BARP (0x00000001U << 0U) +#define CR_BAREN_VALID (0x00000001U << 4U) +#define CRRST_BIT (0x00000001U) + +#if (RCAR_LSI == RCAR_V4H) +#define V4H_7_NI_CR (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */ +#define V4H_5_NI_CR (0x41U) /* 1100[MHz] = 50/3[MHz] x (0x41 + 0x1) */ +#define V4H_3_NI_CR (0x35U) /* 900[MHz] = 50/3[MHz] x (0x35 + 0x1) */ +#elif (RCAR_LSI == RCAR_V4M) +#define V4M_7_NI_CR (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */ +#define V4M_5_NI_CR (0x41U) /* 1100[MHz] = 50/3[MHz] x (0x41 + 0x1) */ +#define V4M_3_NI_CR (0x35U) /* 900[MHz] = 50/3[MHz] x (0x35 + 0x1) */ +#define V4M_2_NI_CR (0x35U) /* 900[MHz] = 50/3[MHz] x (0x35 + 0x1) */ +# endif /* RCAR_LSI == RCAR_V4H */ + +#define CPG_PLL6CR0_KICK_BIT (0x80000000U) +#define CPG_PLLECR_PLL6ST_BIT (0x00008000U) + +#define AP_CORE_APSREG_P_CCI500_AUX_ASPRTM (0x00000001U << 1U) + +static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr); + +static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr) +{ + if(RCAR_PWR_TARGET_CR == target) + { + /* CR Boot address set */ + mem_write32(APMU_CRBARP, (uint32_t)(boot_addr | CR_VLD_BARP)); + mem_write32(APMU_CRBARP, (uint32_t)(boot_addr | CR_VLD_BARP | CR_BAREN_VALID)); + } + else if(RCAR_PWR_TARGET_CA == target) + { + /* CA Boot address set */ + mem_write32(APMU_RVBARPLC0, boot_addr | CA_CORE0_VLD_RVBARP); + mem_write32(APMU_RVBARPHC0, 0x00000000U); + } + else + { + /* No Process */ + } +} +/* End of function arm_cpu_set_address(uint32_t target, uint32_t boot_addr) */ + +void arm_cpu_on(uint32_t target, uint32_t boot_addr) +{ + uint32_t res_data; + + if(RCAR_PWR_TARGET_CR == target) + { + /* CR Boot address set. */ + arm_cpu_set_address(target, boot_addr); + + synci(); + + /* CR reset. */ + res_data = mem_read32(APMU_CRRSTCTRL); + res_data &= ~(CRRST_BIT); + mem_write32(APMU_CRRSTCTRL, res_data); + } + else if(RCAR_PWR_TARGET_CA == target) + { + /* CA Boot address set. */ + arm_cpu_set_address(target, boot_addr); + + /* AP-System core initialize */ + res_data = mem_read32(ap_core_get_ap_cluster_n_aux0_addr(0U)); + res_data |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT; + mem_write32(ap_core_get_ap_cluster_n_aux0_addr(0U), res_data); + + res_data = mem_read32(AP_CORE_APSREG_CCI500_AUX); + res_data |= AP_CORE_APSREG_CCI500_AUX_ACTDIS; + mem_write32(AP_CORE_APSREG_CCI500_AUX, res_data); +#if (RCAR_LSI == RCAR_V4H) + res_data = mem_read32(AP_CORE_APSREG_P_CCI500_AUX); + res_data |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM; + mem_write32(AP_CORE_APSREG_P_CCI500_AUX, res_data); +#endif /* RCAR_LSI == RCAR_V4H */ + synci(); + + /* CA core0 wake up sequence. */ + res_data = mem_read32(APMU_PWRCTRLC0); + res_data |= CA_CORE0_WUP_REQ; + mem_write32(APMU_PWRCTRLC0, res_data); + /* Wait until CA core0 wake up sequence finished. */ + do + { + res_data = mem_read32(APMU_PWRCTRLC0); + }while(FALSE != (CA_CORE0_WUP_REQ & res_data)); + } + else + { + /* No Process */ + } +} +/* End of function arm_cpu_on(uint32_t target, uint32_t boot_addr) */ + + +void adj_cr_variant_freq(void) +{ + uint32_t product = mem_read32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK; + uint32_t pll6_freq = mem_read32(CPG_PLL6CR0); + +#if (RCAR_LSI == RCAR_V4H) + /* Set the CPU frequency division ratio according to the type of variant. */ + switch (product) + { + case VARIANT_V4H_7: + /* Default value, do nothing */; + break; + case VARIANT_V4H_5: + pll6_freq = (pll6_freq & ~(0xFFU << 20U)); + pll6_freq = (pll6_freq | (V4H_5_NI_CR << 20U)); + break; + case VARIANT_V4H_3: + pll6_freq = (pll6_freq & ~(0xFFU << 20U)); + pll6_freq = (pll6_freq | (V4H_3_NI_CR << 20U)); + break; + default: + ; /* Do nothing */ + break; + } + + if (VARIANT_V4H_5 == product || VARIANT_V4H_3 == product) + { + /* Write Division value to FRQCRC0 register */ + mem_write32(CPG_CPGWPR, ~(pll6_freq)); + mem_write32(CPG_PLL6CR0, pll6_freq); + + mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT)); + mem_write32(CPG_PLL6CR0, (mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT)); + + while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL6ST_BIT) != CPG_PLLECR_PLL6ST_BIT) + { + ; + } + } +#elif (RCAR_LSI == RCAR_V4M) + /* Set the CPU frequency division ratio according to the type of variant. */ + switch (product) + { + case VARIANT_V4M_7: + /* Default value, do nothing */; + break; + case VARIANT_V4M_5: + pll6_freq = (pll6_freq & ~(0xFFU << 20U)); + pll6_freq = (pll6_freq | (V4M_5_NI_CR << 20U)); + break; + case VARIANT_V4M_3: + pll6_freq = (pll6_freq & ~(0xFFU << 20U)); + pll6_freq = (pll6_freq | (V4M_3_NI_CR << 20U)); + break; + case VARIANT_V4M_2: + pll6_freq = (pll6_freq & ~(0xFFU << 20U)); + pll6_freq = (pll6_freq | (V4M_2_NI_CR << 20U)); + break; + default: + ; /* Do nothing */ + break; + } + + if (VARIANT_V4M_5 == product || VARIANT_V4M_3 == product || VARIANT_V4M_2 == product) + { + /* Write Division value to FRQCRC0 register */ + mem_write32(CPG_CPGWPR, ~(pll6_freq)); + mem_write32(CPG_PLL6CR0, pll6_freq); + + mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT)); + mem_write32(CPG_PLL6CR0, (mem_read32(CPG_PLL6CR0) | CPG_PLL6CR0_KICK_BIT)); + + while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL6ST_BIT) != CPG_PLLECR_PLL6ST_BIT) + { + ; + } + } +#endif /* RCAR_LSI == RCAR_V4H */ +} +/* End of function adj_cpu_variant_freq(void) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/image_load/image_load.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/image_load/image_load.c new file mode 100644 index 0000000..5ad2dd3 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/image_load/image_load.c @@ -0,0 +1,525 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file image_load.c + * - Version : 0.14 + * @brief Loading image driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Modify macro definition name. + * : 30.09.2021 0.03 Support of eMMC boot. + * : 15.10.2021 0.04 Fix a problem with overwriting the load area + * information in RTOS. + * modify Error log of check_load_area. + * Modify the process of outputting load + * information of Optionbyte to function. + * : 03.12.2021 0.05 Modify function "check_load_area" to check the + * boundary value of RT-VRAM(for virtual buffer). + * Fixed judgment of the top/end of the + * forwarding destination. + * : 06.01.2022 0.06 Support for two-stage boot of G4MH. + * : 23.05.2022 0.07 Support for updating the memory map. + * : 21.06.2022 0.08 Modify some function's arguments and add + * macros. + * : 05.08.2022 0.09 Add TFMV/NTFMV minimum version table + * information to load_init function. + * : 22.09.2022 0.10 Fix address range check for V4H. + * : 21.08.2023 0.11 Add support for V4M. + * : 15.01.2024 0.12 Add image_id initialization to load_init + * function. + * : 19.12.2024 0.13 Add RTOS#1, RTOS#2 image. + * : 26.05.2025 0.14 Change key cert address of [CA_OPTIONAL_ID+2]. + *****************************************************************************/ + +/* indelude */ +#include +#include +#include +#include +#include +#include +#include + +#if (RCAR_SA9_TYPE == FLASH_BOOT) +#include +#include +#elif (RCAR_SA9_TYPE == EMMC_BOOT) +#include +#include +#include +#endif + +#define KEY_SIZE_FLG_MSK (0x00000003U) +#define KEY_SIZE_4096 (0x00000002U) +#define KEY_SIZE_3072 (0x00000001U) +#define KEY_SIZE_2048 (0x00000000U) +#define WORD_TO_BYTE (4U) +#define ERROR_PARAM (0U) +#define NOT_OVERLAP_FLAG (0U) +#define OVERLAP_FLAG (1U) +#define RAM_RANGE_OK (0U) +#define RAM_RANGE_NG (1U) +#if (BOOT_MCU != 0U) +#define RAM_MAX (5U) +#else +#define RAM_MAX (4U) +#endif /* (BOOT_MCU != 0U) */ + +/* Load Parameter of Secure data */ +#define SRC_ADDR_OF_SECURE_DATA_FOR_ICUMXB (SRC_TOP + 0x00340000U) +#define DST_ADDR_OF_SECURE_DATA_FOR_ICUMXB (0xEB2E0000U) +#if (BOOT_MCU != 0U) +#define SRC_ADDR_OF_SECURE_DATA_FOR_ICUMH (SRC_TOP + 0x00440000U) +/* The destination address of Flash to RAM in the ICUMH Secure data is the top address of RT-VRAM. */ +#endif + +static void get_info_from_cert(uint32_t cert_addr, uint32_t *size, + uint32_t *dest_addr); +static void check_src_addr_range(uint32_t src, uint32_t len, uint32_t src_end); +static void check_dst_addr_range(uint32_t dst, uint32_t len, uint32_t dst_end); +static void check_overlap_images(uint32_t dst, uint32_t len, uint32_t dst_end); + +uint32_t load_content_cert(void) +{ + uint32_t load_num; +#if (RCAR_SA9_TYPE == FLASH_BOOT) + load_num = load_content_cert_for_flash(); +#elif (RCAR_SA9_TYPE == EMMC_BOOT) + load_num = load_content_cert_for_emmc(); +#else + /* NoProcess */ +#endif + return load_num; +} +/* End of function load_content_cert(void) */ + +void load_image(LOAD_INFO* li) +{ + /* log output of load image for information */ +#if (RCAR_SA9_TYPE == FLASH_BOOT) + load_image_info_print_for_flash(li); +#elif (RCAR_SA9_TYPE == EMMC_BOOT) + load_image_info_print_for_emmc(li); +#endif + /* Check transfer range of image. */ + check_load_area(li); + + /* Image load start. */ + load_start(li); +} +/* End of function load_image(LOAD_INFO* li) */ + +void load_init(LOAD_INFO* li) +{ + uint32_t loop; + uint32_t buf; + + const char *image_name[MAX_PLACED] = { + [SECURE_FW_ID] = "Secure FW", + [RTOS_ID] = "RTOS", + [CA_PROGRAM_ID] = "Cx IPL", + [ICUMH_PROGRAM_ID] = "ICUMH", + [G4MH_PROGRAM_ID] = "G4MH(1st)", + [G4MH_PROGRAM_ID + 1] = "G4MH(2nd)", + [CA_OPTIONAL_ID] = "CA Program #1", + [CA_OPTIONAL_ID + 1] = "CA Program #2", + [CA_OPTIONAL_ID + 2] = "CA Program #3", + [CA_OPTIONAL_ID + 3] = "CA Program #4", + [CA_OPTIONAL_ID + 4] = "CA Program #5", + [CA_OPTIONAL_ID + 5] = "CA Program #6", + [CA_OPTIONAL_ID + 6] = "CA Program #7", + [CA_OPTIONAL_ID + 7] = "CA Program #8", + [TFMV_MIN_VER_TBL_ID] = "TFMV minimum version table", + [NTFMV_MIN_VER_TBL_ID] = "NTFMV minimum version table", +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + [RTOS1_ID] = "RTOS#1", + [RTOS2_ID] = "RTOS#2" +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + }; + + const uint32_t key_cert[MAX_PLACED] = { + [SECURE_FW_ID] = TFMV_KEY_CERT_ADDR, + [RTOS_ID] = TFMV_KEY_CERT_ADDR, + [CA_PROGRAM_ID] = TFMV_KEY_CERT_ADDR, + [ICUMH_PROGRAM_ID] = TFMV_KEY_CERT_ADDR, + [G4MH_PROGRAM_ID] = TFMV_KEY_CERT_ADDR, + [G4MH_PROGRAM_ID + 1] = TFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID] = TFMV_KEY_CERT_ADDR, +#if (RCAR_LSI == RCAR_S4) + [CA_OPTIONAL_ID + 1] = TFMV_KEY_CERT_ADDR, +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + [CA_OPTIONAL_ID + 1] = NTFMV_KEY_CERT_ADDR, +#endif +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + [CA_OPTIONAL_ID + 2] = NTFMV_KEY_CERT_ADDR, +#else + [CA_OPTIONAL_ID + 2] = TFMV_KEY_CERT_ADDR, +#endif + [CA_OPTIONAL_ID + 3] = NTFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID + 4] = NTFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID + 5] = NTFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID + 6] = NTFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID + 7] = NTFMV_KEY_CERT_ADDR, + [TFMV_MIN_VER_TBL_ID] = TFMV_KEY_CERT_ADDR, + [NTFMV_MIN_VER_TBL_ID] = NTFMV_KEY_CERT_ADDR, +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + [RTOS1_ID] = TFMV_KEY_CERT_ADDR, + [RTOS2_ID] = TFMV_KEY_CERT_ADDR +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + }; + + /* Set Load info parameter */ + for (loop = 0; loop < MAX_PLACED; loop++) + { + li[loop].name = image_name[loop]; + li[loop].key_cert_addr = key_cert[loop]; + li[loop].cnt_cert_addr = get_logic_cont_cert_addr(loop); + get_info_from_cert(li[loop].cnt_cert_addr, &li[loop].image_size, &li[loop].boot_addr); + buf = get_src_addr_offset_in_cert(loop); + li[loop].src_addr = (SRC_TOP + mem_read32(buf)); + li[loop].image_id = loop; +#if (RCAR_SA9_TYPE == EMMC_BOOT) + buf = get_part_num_in_cert(loop); + li[loop].part_num = mem_read32(buf); +#endif + } +}/* End of function load_init(LOAD_INFO* li) */ + + +void check_load_area(const LOAD_INFO* li) +{ + uint32_t src; + uint32_t dst; + uint32_t len; + uint32_t src_end; + uint32_t dst_end; + + src = li->src_addr; + dst = li->boot_addr; + len = li->image_size; + + /* Check whether source is overflow. */ + check_overflow(src, len, &src_end, __func__); + + /* Check whether destination is overflow. */ + check_overflow(dst, len, &dst_end, __func__); + + /* Check source address range. */ + check_src_addr_range(src, len, src_end); + + /* Check destination address range. */ + check_dst_addr_range(dst, len, dst_end); + + /* Check whether overlap destination address and images that have been loaded. */ + check_overlap_images(dst, len, dst_end); +} +/* End of function check_load_area(const LOAD_INFO* li) */ + +static void get_info_from_cert(uint32_t cert_addr, uint32_t *size, + uint32_t *dest_addr) +{ + uint32_t val; + uint32_t certInfo1; + uint32_t pSize; + uint32_t pDestL; + + /* Get key length of content certificate. */ + val = mem_read32(cert_addr + CERT_INFO_FLG_OFFSET); + certInfo1 = (val >> KEY_SIZE_BIT_SHIFT) & KEY_SIZE_FLG_MSK; + + /* Get the transfer address and transfer size from + the certificate in accordance with the key length. */ + if (KEY_SIZE_4096 == certInfo1) /* key size = 4096 */ + { + pSize = cert_addr + CERT_INFO_SIZE_OFFSET2; + *size = mem_read32(pSize) * WORD_TO_BYTE; + pDestL = cert_addr + CERT_INFO_DST_OFFSET2; + *dest_addr = mem_read32(pDestL); + } + else if (KEY_SIZE_3072 == certInfo1) /* key size = 3072 */ + { + pSize = cert_addr + CERT_INFO_SIZE_OFFSET1; + *size = mem_read32(pSize) * WORD_TO_BYTE; + pDestL = cert_addr + CERT_INFO_DST_OFFSET1; + *dest_addr = mem_read32(pDestL); + } + else if (KEY_SIZE_2048 == certInfo1) /* key size = 2048 */ + { + pSize = cert_addr + CERT_INFO_SIZE_OFFSET; + *size = mem_read32(pSize) * WORD_TO_BYTE; + pDestL = cert_addr + CERT_INFO_DST_OFFSET; + *dest_addr = mem_read32(pDestL); + } + else + { + *size = ERROR_PARAM; + *dest_addr = ERROR_PARAM; + } +} +/* End of function get_info_from_cert(uint32_t cert_addr, uint32_t *size, uint32_t *dest_addr) */ + +void load_start(const LOAD_INFO* li) +{ +#if (RCAR_SA9_TYPE == FLASH_BOOT) + dma_trans_start(li->boot_addr, li->src_addr, li->image_size); +#elif (RCAR_SA9_TYPE == EMMC_BOOT) + uint32_t rtn_val; + uint32_t sector_count; + uint32_t fraction; + + /* Converted to number of sectors transferred. */ + sector_count = li->image_size >> EMMC_SECTOR_SIZE_SHIFT; + fraction = li->image_size % EMMC_SECTOR_SIZE; + /* Add 1 if there is a fraction */ + if(0U != fraction) + { + sector_count += 1U; + } + + rtn_val = emmc_trans_data(li->part_num, (li->src_addr >> EMMC_SECTOR_SIZE_SHIFT), + li->boot_addr, sector_count); + + if(EMMC_DEV_OK != rtn_val) + { + ERROR("load_start(emmc_trans_data error).\r\n"); + panic; + } +#else + /* NoProcess */ +#endif +}/* End of function load_start(LOAD_INFO* li) */ + +void load_end(void) +{ +#if (RCAR_SA9_TYPE == FLASH_BOOT) + dma_trans_end_check(); +#else + /* NoProcess */ +#endif +}/* End of function load_end(void) */ + +void load_securedata(uint32_t target_id) +{ + LOAD_INFO tmp_li; + + if(target_id == SECURE_FW_ID) /* When secure data transfer for ICUMXB FW. */ + { + tmp_li.image_size = SECUREDATA_SIZE; + tmp_li.src_addr = SRC_ADDR_OF_SECURE_DATA_FOR_ICUMXB; + tmp_li.boot_addr =DST_ADDR_OF_SECURE_DATA_FOR_ICUMXB; +#if (RCAR_SA9_TYPE == EMMC_BOOT) + tmp_li.part_num = EMMC_PARTITION_1; +#endif + } +#if (BOOT_MCU != 0U) + else if(target_id == ICUMH_PROGRAM_ID) /* When secure data transfer for ICUMH FW. */ + { + tmp_li.image_size = SECUREDATA_SIZE; + tmp_li.src_addr = SRC_ADDR_OF_SECURE_DATA_FOR_ICUMH; + tmp_li.boot_addr = RTVRAM_BASE; +#if (RCAR_SA9_TYPE == EMMC_BOOT) + tmp_li.part_num = EMMC_PARTITION_1; +#endif + } +#endif + else + { + ERROR("Failed input parameter.\n"); + panic; + } + + load_start(&tmp_li); +}/* End of function load_securedata(uint32_t target_id) */ + +void check_overflow(uint32_t addr, uint32_t len, uint32_t *end_addr, const char *func_name) +{ + /* Pre confirmation */ + if (addr > (UINT32_MAX - len)) + { + ERROR("1:overflow is occurred in %s.\n", func_name); + ERROR("1:address = 0x%x size = 0x%x\n", addr, len); + panic; + } + else + { + *end_addr = addr + len - 1U; + } + /* Post confirmation */ + if (*end_addr < addr) + { + ERROR("2:overflow is occurred in %s.\n", func_name); + ERROR("2:address = 0x%x size = 0x%x\n", addr, len); + panic; + } +} +/* End of function check_overflow(uint32_t addr, uint32_t len, uint32_t *end_addr, char *func_name) */ + +static void check_src_addr_range(uint32_t src, uint32_t len, uint32_t src_end) +{ + + /* Check image size */ + if (len == 0U) + { + ERROR("image size error\n"); + panic; + } + +#if (RCAR_SA9_TYPE == FLASH_BOOT) + if ((src < SRC_TOP) || (SRC_END < src_end)) +#elif (RCAR_SA9_TYPE == EMMC_BOOT) + if (SRC_END < src_end) +#endif + { + ERROR("check load area (source address)\n"); + ERROR("source address = 0x%x image size = 0x%x\n", src, len); + panic; + } +} +/* End of function check_src_addr_range(uint32_t src, uint32_t len, uint32_t src_end) */ + +static void check_dst_addr_range(uint32_t dst, uint32_t len, uint32_t dst_end) +{ + uint32_t rge_chk_flg; + uint32_t loop; + + /* The memory range of destination. */ + const ADDRESS_RANGE add_list[RAM_MAX] = { + [TARGET_MEM_DRAM] = {DRAM_BASE, DRAM_END}, + [TARGET_MEM_RTSRAM] = {RTSRAM_BASE, RTSRAM_END}, + [TARGET_MEM_RTVRAM] = {RTVRAM_VBUF_TOP, RTVRAM_VBUF_END}, + [TARGET_MEM_SYSRAM] = {SYSRAM_BASE, SYSRAM_END}, +#if (BOOT_MCU != 0U) + [TARGET_MEM_CODESRAM] = {CODESRAM_BASE, CODESRAM_END} +#endif /* (BOOT_MCU != 0U) */ + }; + + /* Check image size */ + if (len == 0U) + { + ERROR("image size error\n"); + panic; + } + + rge_chk_flg = RAM_RANGE_NG; + + for(loop = 0; loop < RAM_MAX; loop++) + { + if (add_list[loop].topadd <= dst) + { + if(dst_end <= add_list[loop].endadd) + { + rge_chk_flg = RAM_RANGE_OK; + break; + } + } + } + + if(rge_chk_flg != RAM_RANGE_OK) + { + ERROR("check load area (destination address)\n"); + ERROR("destination address = 0x%x image size = 0x%x\n", dst, len); + panic; + } +} +/* End of function check_dst_addr_range(uint32_t dst, uint32_t len, uint32_t dst_end) */ + +static void check_overlap_images(uint32_t dst, uint32_t len, uint32_t dst_end) +{ + uint32_t overlap; + uint32_t loop; + + static uint32_t s_num = 1U; + + static ADDRESS_RANGE s_placed_image[MAX_PLACED + 1] = { + [0] = {IPL_TOP, IPL_END}, + [1] = {0U,0U}, + [2] = {0U,0U}, + [3] = {0U,0U}, + [4] = {0U,0U}, + [5] = {0U,0U}, + [6] = {0U,0U}, + [7] = {0U,0U}, + [8] = {0U,0U}, + [9] = {0U,0U}, + [10] = {0U,0U}, + [11] = {0U,0U}, + [12] = {0U,0U}, + [13] = {0U,0U}, + [14] = {0U,0U}, + [15] = {0U,0U}, + [16] = {0U,0U} + }; + + overlap = NOT_OVERLAP_FLAG; + loop = 0U; + do + { + /* check overlap */ + if ((dst >= s_placed_image[loop].topadd) && (dst <= s_placed_image[loop].endadd)) + { + overlap = OVERLAP_FLAG; + } + else if ((dst_end >= s_placed_image[loop].topadd) && (dst_end <= s_placed_image[loop].endadd)) + { + overlap = OVERLAP_FLAG; + } + else if ((dst < s_placed_image[loop].topadd) && (s_placed_image[loop].endadd < dst_end)) + { + overlap = OVERLAP_FLAG; + } + else + { + loop++; + } + } while ((loop < s_num) && (overlap == NOT_OVERLAP_FLAG)); + + /* Check the overlap flag. * + * Parameters are error if overwrite occurred. * + * Otherwise, add parameters of the image to be loaded into Placed_image. */ + if (overlap == NOT_OVERLAP_FLAG) + { + s_placed_image[s_num].topadd = dst; + s_placed_image[s_num].endadd = dst_end; + INFO("[0x%x] topadd = 0x%x endadd = 0x%x\n", s_num, + s_placed_image[s_num].topadd, s_placed_image[s_num].endadd); + s_num++; + } + else + { + ERROR("check load area (overlap)\n"); + ERROR("destination address = 0x%x image size = 0x%x\n", dst, len); + ERROR("overlapped image is [%x]\n", loop); + ERROR("top address = 0x%x end address = 0x%x\n", + s_placed_image[loop].topadd, s_placed_image[loop].endadd); + panic; + } +} +/* End of function check_overlap_images(uint32_t dst, uint32_t len, uint32_t dst_end) */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/image_load/image_load_emmc.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/image_load/image_load_emmc.c new file mode 100644 index 0000000..45366b7 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/image_load/image_load_emmc.c @@ -0,0 +1,145 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load for emmc function + ******************************************************************************/ +/****************************************************************************** + * @file image_load_emmc.c + * - Version : 0.04 + * @brief Image load for emmc function. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 30.09.2021 0.01 First Release + * : 23.05.2022 0.02 Support for updating the memory map. + * : 05.08.2022 0.03 Add load_ver_tbl_cert_for_emmc function. + * : 30.09.2022 0.04 Modify size output in + * load_ver_tbl_cert_for_emmc function. + *****************************************************************************/ + +/* indelude */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void load_ver_tbl_cert_for_emmc(void); + +uint32_t load_content_cert_for_emmc(void) +{ + uint32_t load_num; + uint32_t phys_dst; + uint32_t phys_src; + uint32_t size; + uint32_t part; + + /* source address.(0x00240000/sector:0x1200) */ + phys_src = EMMC_CONTENT_CERT_SECTOR_NUMBER; + /* Get physical address of transfer destination. */ + phys_dst = remap_get_phys_addr(SA9_DEST_ADDR); + /* transfer size(number of secters) */ + size = CONTENT_CERT_INFO_SIZE >> EMMC_SECTOR_SIZE_SHIFT; + /* The partition that contains A. */ + part = (uint32_t)PARTITION_ID_BOOT_1; + + /* Load content cert header */ + (void)emmc_trans_data(part, phys_src, phys_dst, size); + + NOTICE( + "======== content cert info ========\n" + "destination address:0x%08x\n" + "physical destination address:0x%08x\n" + "source address:(p:%d)0x%08x\n" + "size:0x%08x\n", SA9_DEST_ADDR, phys_dst, + PARTITION_ID_BOOT_1, EMMC_CONTENT_CERT_ADDR, CONTENT_CERT_INFO_SIZE); + + load_num = mem_read32(SA9_DEST_ADDR); + + /* Check number of image load. + In case of number of image load is 0, error of transfer parameter. + In case of number of image loads is higher than 8, + the transfer parameter error. */ + if ((load_num == 0U) || (load_num > CA_MAX_IMAGE)) + { + ERROR("Content cert info 'load image num' fault.\n"); + ERROR("load image num = %d\n",load_num); + panic; + } + + /* Increase forwarding address by the size of cert header */ + phys_src += (CONTENT_CERT_INFO_SIZE >> EMMC_SECTOR_SIZE_SHIFT); + phys_dst += CONTENT_CERT_INFO_SIZE; + + /* Transfer size calculation for SA9 * + * TFMV key + NTFMV key + minimum version table + (content cert * number of loads) */ + size = ((KEY_CERT_SIZE * 2U) + MIN_VER_TBL_SIZE + + ((NUM_OF_ALWAYS_LOAD_CERT + load_num) * CONTENT_CERT_SIZE)); + + (void)emmc_trans_data(part, phys_src, phys_dst, size >> EMMC_SECTOR_SIZE_SHIFT); + + NOTICE( + "======== content cert ========\n" + "address:0x%08x size:0x%08x\n", phys_dst, size); + + /* Load content cert of Software minimum version table */ + load_ver_tbl_cert_for_emmc(); + + return load_num; +} +/* End of function load_content_cert_for_emmc(void) */ + +static void load_ver_tbl_cert_for_emmc(void) +{ +#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) + uint32_t phys_dst; + uint32_t phys_src; + uint32_t size; + uint32_t part; + + /* source address.(0x0024D000/sector:0x1268) */ + phys_src = EMMC_VER_TBL_CNT_CERT_SEC_NUM; + /* Get physical address of transfer destination. */ + phys_dst = remap_get_phys_addr(SA9_DEST_ADDR + EMMC_VER_TBL_OFFSET); + /* transfer size(number of secters) */ + size = (CONTENT_CERT_SIZE * 2U) >> EMMC_SECTOR_SIZE_SHIFT; + /* The partition that contains content cert of Software minimum version table. */ + part = (uint32_t)PARTITION_ID_BOOT_1; + + /* Load content cert of Software minimum version table */ + (void)emmc_trans_data(part, phys_src, phys_dst, size); + + NOTICE("======== content cert of SW version table ========\n" + "address:0x%08x size:0x%08x\n", phys_dst, (size << EMMC_SECTOR_SIZE_SHIFT)); + +#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */ +} +/* End of function load_ver_tbl_cert_for_emmc(void) */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/image_load/image_load_flash.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/image_load/image_load_flash.c new file mode 100644 index 0000000..ed3cc0d --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/image_load/image_load_flash.c @@ -0,0 +1,180 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load for Flash function + ******************************************************************************/ +/****************************************************************************** + * @file image_load_flash.c + * - Version : 0.04 + * @brief Image load for Flash function. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 30.09.2021 0.01 First Release + * : 23.05.2022 0.02 Support for updating the memory map. + * : 05.08.2022 0.03 Add load_ver_tbl_cert_for_flash function. + * : 20.12.2024 0.04 Add support for booting CR52 3 cores. + *****************************************************************************/ + +/* indelude */ +#include +#include +#include +#include +#include +#include +#include "image_load.h" + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +static void load_rtos12_cert_for_flash(void); +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +static void load_ver_tbl_cert_for_flash(void); + +uint32_t load_content_cert_for_flash(void) +{ + uint32_t load_num; + uint32_t phys_dst; + uint32_t phys_src; + uint32_t size; + + /* source address.(0x08240000) */ + phys_src = FLASH_CONTENT_CERT_ADDR; + /* Get physical address of transfer destination. */ + phys_dst = remap_get_phys_addr(SA9_DEST_ADDR); + /* transfer size */ + size = CONTENT_CERT_INFO_SIZE; + /* Load content cert header */ + dma_trans_start(phys_dst, phys_src, size); + + NOTICE( + "======== content cert info ========\n" + "destination address:0x%08x\n" + "physical destination address:0x%08x\n" + "source address:0x%08x\n" + "size:0x%08x\n", SA9_DEST_ADDR, phys_dst, phys_src, size); + + + /* End loading cert header */ + load_end(); + + load_num = mem_read32(SA9_DEST_ADDR); + + + /* Check number of image load. + In case of number of image load is 0, error of transfer parameter. + In case of number of image loads is higher than 8, + the transfer parameter error. */ + if ((load_num == 0U) || (load_num > CA_MAX_IMAGE)) + { + ERROR("Content cert info 'load image num' fault.\n"); + ERROR("load image num = %d\n",load_num); + panic; + } + + /* Increase forwarding address by the size of cert header */ + phys_src += CONTENT_CERT_INFO_SIZE; + phys_dst += CONTENT_CERT_INFO_SIZE; + + /* Transfer size calculation for SA9 * + * TFMV key + NTFMV key + TFMV/NTFMV minimum version table + (content cert * number of loads) */ + size = ((KEY_CERT_SIZE * 2U) + MIN_VER_TBL_SIZE + + ((NUM_OF_ALWAYS_LOAD_CERT + load_num) * CONTENT_CERT_SIZE)); + + /* Load SA9. */ + dma_trans_start(phys_dst, phys_src, size); + + /* End loading content cert */ + load_end(); + + NOTICE("======== content of SA9 ========\n" + "address:0x%08x size:0x%08x\n", phys_dst, size); + + /* Load content cert of Software minimum version table */ + load_ver_tbl_cert_for_flash(); + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + /* Load content cert of RTOS#1 and RTOS#2 */ + load_rtos12_cert_for_flash(); +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + + return load_num; +} +/* End of function load_content_cert_for_flash(void) */ + +static void load_ver_tbl_cert_for_flash(void) +{ +#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) + uint32_t phys_dst; + uint32_t phys_src; + uint32_t size; + + /* Source address.(0x0824D000) */ + phys_src = FLASH_VER_TBL_CNT_CERT_ADDR; + /* Get physical address of transfer destination. */ + phys_dst = remap_get_phys_addr(SA9_DEST_ADDR + VER_TBL_CNT_CERT_OFFSET); + /* transfer size */ + size = CONTENT_CERT_SIZE * 2U; + + /* Load content cert of Software minimum version table. */ + dma_trans_start(phys_dst, phys_src, size); + + /* End loading content cert */ + load_end(); + + NOTICE("======== content cert of SW version table ========\n" + "address:0x%08x size:0x%08x\n", phys_dst, size); + +#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */ +} +/* End of function load_ver_tbl_cert_for_flash(void) */ + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +static void load_rtos12_cert_for_flash(void) +{ + uint32_t phys_dst; + uint32_t phys_src; + uint32_t size; + + /* Source address.(0x0824E000) */ + phys_src = FLASH_RTOS12_CNT_CERT_ADDR; + /* Get physical address of transfer destination. */ + phys_dst = remap_get_phys_addr(SA9_DEST_ADDR + RTOS12_CNT_CERT_OFFSET); + /* transfer size */ + size = CONTENT_CERT_SIZE * 2U; /* RTOS#1 and RTOS#2 */ + + /* Load content cert of Software minimum version table. */ + dma_trans_start(phys_dst, phys_src, size); + + /* End loading content cert */ + load_end(); + + NOTICE("======== content cert of RTOS#1 and RTOS#2 ========\n" + "address:0x%08x size:0x%08x\n", phys_dst, size); + +} +/* End of function load_rtos12_cert_for_flash(void) */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/access_protection.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/access_protection.h new file mode 100644 index 0000000..9d5f08c --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/access_protection.h @@ -0,0 +1,53 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Access Protection function header + ******************************************************************************/ + +#include + +#ifndef ACCESS_PROTECTION_ID_H__ +#define ACCESS_PROTECTION_ID_H__ + +#define PROTECTION_DISABLE (0U) +#define PROTECTION_ENABLE (1U) + +#define RGID_0 (0U) +#define RGID_1 (1U) +#define RGID_2 (2U) +#define RGID_INVALID (0xFFFFFFFFU) + +#define CPG_PROTECTION (63U) +#define SYSC_PROTECTION (5U) +#define RESET_PROTECTION (29U) +#define WRITE_ENABLE (0xFFFFFFFFU) + +void rgid_protection(void); +void ram_protection(void); +void rgid_protection_final(void); +void ram_protection_final(void); +void set_master_rgid_4_tfr_mod(void); +void icu_remove_write_access(void); + +#endif /* ACCESS_PROTECTION_ID_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/ap_system_core_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/ap_system_core_register.h new file mode 100644 index 0000000..01fa5d5 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/ap_system_core_register.h @@ -0,0 +1,43 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : AP-System Core register header + ******************************************************************************/ + +#ifndef AP_SYSTEM_CORE_REGISTER_H_ +#define AP_SYSTEM_CORE_REGISTER_H_ + +#include + +#define AP_CORE_BASE (BASE_AP_CORE_ADDR) /* 0xE6280000 */ + +#define AP_CORE_APSREG_CCI500_AUX (AP_CORE_BASE + 0x00009010U) +#define AP_CORE_APSREG_P_CCI500_AUX (AP_CORE_BASE + 0x00029010U) + +static inline uint32_t ap_core_get_ap_cluster_n_aux0_addr(uint32_t num) +{ + return (AP_CORE_BASE + 0x00000010U + (num * 0x1000U)); +} + +#endif /* AP_SYSTEM_CORE_REGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/avs.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/avs.h new file mode 100644 index 0000000..cc5bfea --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/avs.h @@ -0,0 +1,34 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : AVS driver header + ******************************************************************************/ + +#ifndef AVS_DRIVER_H__ +#define AVS_DRIVER_H__ + +void avs_low_power_mode_setting(void); + +#endif /* AVS_DRIVER_H__ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/axmm_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/axmm_register.h new file mode 100644 index 0000000..8cc39fe --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/axmm_register.h @@ -0,0 +1,82 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : AXMM register header + ******************************************************************************/ + +#ifndef AXMM_REGISTER_H__ +#define AXMM_REGISTER_H__ + +#include +#include + +/* RT-SRAM register base address */ +#define AXMM_BASE (BASE_AXMM_ADDR) + +#define AXMM_DPTDIVCR (AXMM_BASE + 0x6000U) +#define AXMM_DPTRGNCR (AXMM_BASE + 0x6100U) +#define AXMM_DPTSECCR (AXMM_BASE + 0x6200U) +#define AXMM_SPTDIVCR (AXMM_BASE + 0x6300U) +#define AXMM_SPTRGNCR (AXMM_BASE + 0x6400U) +#define AXMM_SPTSECCR (AXMM_BASE + 0x6500U) + + +#define AXMM_DPTDIVCR_DIVADDR_MASK (0x003FFFFFU) +#define AXMM_DPTSECCR_SECGRP_MASK (0x00000F00U) +#define AXMM_DPTSECCR_SECGWP_MASK (0x0000000FU) +#define AXMM_SPTDIVCR_DIVADDR_MASK (0x000FFFFFU) +#define AXMM_SPTSECCR_SECGRP_MASK (0x00000F00U) +#define AXMM_SPTSECCR_SECGWP_MASK (0x0000000FU) + +static inline uint32_t get_dptdivcr_addr(uint32_t num) +{ + return ((AXMM_DPTDIVCR + (num * 4U))); +} + +static inline uint32_t get_dptrgncr_addr(uint32_t num) +{ + return ((AXMM_DPTRGNCR + (num * 4U))); +} + +static inline uint32_t get_dptseccr_addr(uint32_t num) +{ + return ((AXMM_DPTSECCR + (num * 4U))); +} + +static inline uint32_t get_sptdivcr_addr(uint32_t num) +{ + return ((AXMM_SPTDIVCR + (num * 4U))); +} + +static inline uint32_t get_sptrgncr_addr(uint32_t num) +{ + return ((AXMM_SPTRGNCR + (num * 4U))); +} + +static inline uint32_t get_sptseccr_addr(uint32_t num) +{ + return ((AXMM_SPTSECCR + (num * 4U))); +} + +#endif /* AXMM_REGISTER_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cnf_tbl.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cnf_tbl.h new file mode 100644 index 0000000..20cc4f8 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cnf_tbl.h @@ -0,0 +1,160 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table header + ******************************************************************************/ + +#ifndef CNF_TBL_H_ +#define CNF_TBL_H_ + +#include +#include + +typedef struct{ + uint32_t reg_addr; /* register address(for SIC remap) */ + uint32_t value; /* setting value */ +} CONFIGURATION_SETTING_TABLE; + +typedef struct{ + uint64_t fix; + uint64_t be; +} QOS_SETTING_TABLE; + +typedef struct{ + uint32_t addr; /* address of Region ID registers.(for SIC Remap) */ + uint32_t value; /* setting value of Region ID registers. */ +} REGION_ID_SETTING_TABLE; + +typedef struct { + uint32_t rw_val; + uint32_t sec_val; +}RAM_PROTECTION_VALUE_FORMAT; + +typedef struct { + uint32_t read_val; + uint32_t write_val; +}RTRAM_PROTECTION_VALUE_FORMAT; + +typedef struct { + uint32_t addr; + RTRAM_PROTECTION_VALUE_FORMAT setting_value; +}RTRAM_PROTECTION_STRUCTUR; + +typedef struct { + uint32_t addr; + RAM_PROTECTION_VALUE_FORMAT setting_value; +}SYSTEM_RAM_PROTECTION_STRUCTUR; + +typedef struct { + uint64_t addr; + RAM_PROTECTION_VALUE_FORMAT setting_value; +}DRAM_PROTECTION_STRUCTUR; + +#if (RCAR_LSI == RCAR_S4) +#define QOS_TBL_MAX (48U) /* Max setting number of QoS Bank registers. */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define QOS_TBL_MAX (125U) /* Max setting number of QoS Bank registers. */ +#endif /* RCAR_LSI == RCAR_S4 */ + +#if (RCAR_LSI == RCAR_S4) +#define RGID_M_MAX (44U) /* Max number of Region registers. (Master) */ +#define RGID_R_MAX (606U) /* Max number of Region registers. (Read) */ +#define RGID_W_MAX (606U) /* Max number of Region registers. (Write) */ +#define RGID_SEC_MAX (633U) /* Max number of Region registers. (Secure) */ +#define RGID_AXI_MAX (54U) /* Max number of Region registers. (Read/Write for AXI-bus) */ +#elif (RCAR_LSI == RCAR_V4H) +#define RGID_M_MAX (77U) /* Max number of Region registers. (Master) */ +#define RGID_R_MAX (908U) /* Max number of Region registers. (Read) */ +#define RGID_W_MAX (907U) /* Max number of Region registers. (Write) */ +#define RGID_SEC_MAX (957U) /* Max number of Region registers. (Secure) */ +#define RGID_AXI_MAX (98U) /* Max number of Region registers. (Read/Write for AXI-bus) */ +#define RGID_GID_MAX (2U) /* Max number of Region registers. (CCI MPU GID register) */ +#elif (RCAR_LSI == RCAR_V4M) +#define RGID_M_MAX (85U) /* Max number of Region registers. (Master) */ +#define RGID_R_MAX (805U) /* Max number of Region registers. (Read) */ +#define RGID_W_MAX (804U) /* Max number of Region registers. (Write) */ +#define RGID_SEC_MAX (819U) /* Max number of Region registers. (Secure) */ +#define RGID_AXI_MAX (90U) /* Max number of Region registers. (Read/Write for AXI-bus) */ +#define RGID_GID_MAX (1U) /* Max number of Region registers. (CCI MPU GID register) */ +#endif /* (RCAR_LSI == RCAR_S4) */ + +#define RAM_PROTECTION_MAX (16U) /* Max number of RAM Protection registers. (RT-SRAM/RT-VRAM/SystemRAM) */ +#define DRAM_PROTECTION_MAX (64U) /* Max number of RAM Protection registers. (SDRAM) */ + +#if (RCAR_LSI == RCAR_S4) +#define FDT_REG_MAX (102U) +#elif (RCAR_LSI == RCAR_V4H) +#define FDT_REG_MAX (120U) +#elif (RCAR_LSI == RCAR_V4M) +#define FDT_REG_MAX (72U) +#endif +#if (RCAR_LSI == RCAR_V4H) +#define INTEN_REG_MAX (401U) +#elif (RCAR_LSI == RCAR_V4M) +#define INTEN_REG_MAX (375U) +#endif /* (RCAR_LSI == RCAR_V4H) */ + +#if (RCAR_LSI == RCAR_V4H) +#define IMP_MASTER_MAX (19U) +#define IMP_SLAVE_MAX (38U) +#endif /* (RCAR_LSI == RCAR_V4H) */ + +#if (RCAR_LSI == RCAR_V4H) +#define IPMMU_RGID_MAX (11U) +#elif (RCAR_LSI == RCAR_V4M) +#define IPMMU_RGID_MAX (10U) +#endif /* (RCAR_LSI == RCAR_V4H) */ + +extern const QOS_SETTING_TABLE g_qosbw_tbl[QOS_TBL_MAX]; +extern const QOS_SETTING_TABLE g_qoswt_tbl[QOS_TBL_MAX]; + +extern const REGION_ID_SETTING_TABLE g_rgid_m_tbl[RGID_M_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_r_tbl[RGID_R_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_w_tbl[RGID_W_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[RGID_SEC_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[RGID_AXI_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_gid_tbl[RGID_GID_MAX]; +extern const uint32_t g_rgid_rtdma_setting_value[RTDMA_MODULE_MAX][RTDMA_CH_MAX][2U]; +extern const uint32_t g_rgid_sysdma_setting_value[SYSDMA_MODULE_MAX][SYSDMA_CH_MAX][2U]; +extern const RTRAM_PROTECTION_STRUCTUR g_rtsram_protection_table[RAM_PROTECTION_MAX]; +extern const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table_1[RAM_PROTECTION_MAX]; +#if (RCAR_LSI == RCAR_S4) +extern const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table_2[RAM_PROTECTION_MAX]; +#endif +extern const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX]; +extern const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX]; +extern const CONFIGURATION_SETTING_TABLE g_fdt_tbl[FDT_REG_MAX]; +extern const CONFIGURATION_SETTING_TABLE g_inten_tbl[INTEN_REG_MAX]; +#if (RCAR_LSI == RCAR_V4H) +extern const REGION_ID_SETTING_TABLE g_imp_rgid_m_tbl[IMP_MASTER_MAX]; +extern const REGION_ID_SETTING_TABLE g_imp_rgid_s_tbl[IMP_SLAVE_MAX]; +#endif /* (RCAR_LSI == RCAR_V4H) */ +extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX]; +extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX]; +extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX]; + +/* Now go back to default rules */ +#pragma ghs section rodata=default + +#endif /* CNF_TBL_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cpg.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cpg.h new file mode 100644 index 0000000..254f41d --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cpg.h @@ -0,0 +1,57 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : CPG driver header + ******************************************************************************/ +#ifndef CPG_H_ +#define CPG_H_ + +#include +#include +#include + +#define RPC_CLK_160MHZ (0x00000013U) /* RPCphi = 160MHz RPCD2phi = 80MHZ */ + +/* Prototype */ +void cpg_init(void); + +/* Inline function */ +static inline void cpg_reg_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t data) +{ + mem_write32(CPG_CPGWPR, ~data); + mem_write32(mstpcr, data); + while ((mem_read32(mstpsr) & ~(uint32_t)(data)) != 0U) + { + /* Loop to wait for confirmation that changes to "MSTPCRn" are reflected in "MSTPSRn". */ + } +} + +/* Inline function */ +static inline void apmu_reg_write(uint32_t reg, uint32_t data) +{ + mem_write32(APMU_WPR, ~data); + mem_write32(reg, data); +} + +#endif /* CPG_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cpg_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cpg_register.h new file mode 100644 index 0000000..c62bd22 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cpg_register.h @@ -0,0 +1,120 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : CPG register header + ******************************************************************************/ + +#ifndef CPG_REGISTER_H__ +#define CPG_REGISTER_H__ + +#include + +/* CPG base address */ +/* 0xE6150000 */ +#define CPG_BASE (BASE_CPG_ADDR) + +/* Domain Offset Addresses */ +#define D0 (0x4000U * 0U) +#define D1 (0x4000U * 1U) +#define D2 (0x4000U * 2U) +#define D3 (0x4000U * 3U) + +/* CPG write protect */ +#define CPG_CPGWPR (CPG_BASE + 0x0000U + D0) +/* CPG write protect control */ +#define CPG_CPGWPCR (CPG_BASE + 0x0004U + D0) + +/* Module Stop Control register */ +/* Registers of domain 0 */ +#define CPG_MSTPCR5D0 (CPG_BASE + 0x2D14U + D0) /* HSCIF0, I2C3 */ +#define CPG_MSTPCR7D0 (CPG_BASE + 0x2D1CU + D0) /* SCIF0 */ +#define CPG_MSTPCR28D0 (CPG_BASE + 0x2D70U + D0) /* FCPR */ + +/* Module Stop Status register */ +/* Registers of domain 0 */ +#define CPG_MSTPSR5D0 (CPG_BASE + 0x2E14U + D0) /* HSCIF0, I2C3 */ +#define CPG_MSTPSR7D0 (CPG_BASE + 0x2E1CU + D0) /* SCIF0 */ +#define CPG_MSTPSR28D0 (CPG_BASE + 0x2E70U + D0) /* FCPR */ + +/* Module standby , Software reset */ +#define CPG_SRCR11 (CPG_BASE + 0x2C2CU) +#define CPG_SRSTCLR11 (CPG_BASE + 0x2CACU) +#if (RCAR_LSI == RCAR_V4H) +#define CPG_SRCR28 (CPG_BASE + 0x2C70U) +#define CPG_SRCR29 (CPG_BASE + 0x2C74U) +#endif /* RCAR_LSI == RCAR_V4H */ + +#define CPGSRCR_PDR11 (0x00002000U) /* Bit13 */ +#if (RCAR_LSI == RCAR_V4H) +#define CPGSRCR28_VAL (0xCF600000U) +#define CPGSRCR29_VAL (0x007B3D9EU) +#endif /* RCAR_LSI == RCAR_V4H */ + +#define CPG_D1WACRA00 (CPG_BASE + 0x3900U) +#define CPG_D2WACRA00 (CPG_BASE + 0x3A00U) +#define CPG_D3WACRA00 (CPG_BASE + 0x3B00U) + +#define CPG_D1WACR_MSTPCR0 (CPG_BASE + 0x3100U) +#define CPG_D1WACR_RAHSR0 (CPG_BASE + 0x3180U) +#define CPG_D1WACR_SRCR0 (CPG_BASE + 0x3500U) +#define CPG_D1WACR_SRSTCLR0 (CPG_BASE + 0x3580U) + +#define CPG_D2WACR_MSTPCR0 (CPG_BASE + 0x3200U) +#define CPG_D2WACR_RAHSR0 (CPG_BASE + 0x3280U) +#define CPG_D2WACR_SRCR0 (CPG_BASE + 0x3600U) +#define CPG_D2WACR_SRSTCLR0 (CPG_BASE + 0x3680U) + +#define CPG_D3WACR_MSTPCR0 (CPG_BASE + 0x3300U) +#define CPG_D3WACR_RAHSR0 (CPG_BASE + 0x3380U) +#define CPG_D3WACR_SRCR0 (CPG_BASE + 0x3700U) +#define CPG_D3WACR_SRSTCLR0 (CPG_BASE + 0x3780U) + +/* APMU */ +#define APMU_BASE (BASE_APMU_ADDR) +#if (RCAR_LSI == RCAR_S4) +#define CORTEX_R_CORE (0U) /* Target Cortex R52 cores (0 only) */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define CORTEX_R_CORE (1U) /* Target Cortex R52 cores (0 to 2) */ +#endif /* RCAR_LSI == RCAR_S4 */ +#define APMU_WPR (APMU_BASE + 0x0004U) /* Write protection register */ +#define APMU_D0_ACCENR (APMU_BASE + 0x0010U) /* Domain0 Access enable register */ +#define APMU_D1_ACCENR (APMU_BASE + 0x0014U) /* Domain1 Access enable register */ +#define APMU_D2_ACCENR (APMU_BASE + 0x0018U) /* Domain2 Access enable register */ +#define APMU_D3_ACCENR (APMU_BASE + 0x001CU) /* Domain3 Access enable register */ +#define APMU_CRRSTCTRL (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x0304U) /* Cortex-R Reset Control Register */ +#define APMU_CRBAR (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x0334U) /* Cortex-R Boot Address Register */ +#define APMU_CRBARP (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x033CU) /* Cortex-R Boot Address Register Protected */ +#define APMU_PWRCTRLC0 (APMU_BASE + 0x0800U) /* Power Control Register for Core 0 */ +#define APMU_RVBARPLC0 (APMU_BASE + 0x0838U) /* Reset Vector Base Address Register Protected Low for Core 0 */ +#define APMU_RVBARPHC0 (APMU_BASE + 0x083CU) /* Reset Vector Base Address Register Protected High for Core 0 */ + +/* SD-IF */ +#define CPG_SD0CKCR0 (CPG_BASE + 0x0870U) + +/* RPC */ +#define CPG_RPCCKCR (CPG_BASE + 0x0874U) + +#define CPG_PLL6CR0 (CPG_BASE + 0x084CU) +#define CPG_PLLECR (CPG_BASE + 0x0820U) +#endif /* CPG_REGISTER_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cpu.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cpu.h new file mode 100644 index 0000000..51275cb --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cpu.h @@ -0,0 +1,103 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : CPU register access list header + ******************************************************************************/ + + +#ifndef CPU_H_ +#define CPU_H_ + +/* + * Groups + */ + +/* Name Reg, Group Comment */ +#define EIPC 0, 0 /* Status save registers when acknowledging EI level exception SV */ +#define EIPSW 1, 0 /* Status save registers when acknowledging EI level exception SV */ +#define FEPC 2, 0 /* Status save registers when acknowledging FE level exception SV */ +#define FEPSW 3, 0 /* Status save registers when acknowledging FE level exception SV */ +#define PSW 5, 0 /* Program status word Note 1 */ +#define EIIC 13, 0 /* EI level exception cause SV */ +#define FEIC 14, 0 /* FE level exception cause SV */ +#define CTPC 16, 0 /* CALLT execution status save register UM */ +#define CTPSW 17, 0 /* CALLT execution status save register UM */ +#define CTBP 20, 0 /* CALLT base pointer UM */ +#define EIWR 28, 0 /* EI level exception working register SV */ +#define FEWR 29, 0 /* FE level exception working register SV */ +#define BSEL 31, 0 /* (Reserved for backward compatibility with V850E2 series)Note 2 SV */ + +#define MCFG0 0, 1 /* Machine configuration SV */ +#define RBASE 2, 1 /* Reset vector base address SV */ +#define EBASE 3, 1 /* Exception handler vector address SV */ +#define INTBP 4, 1 /* Base address of the interrupt handler table SV */ +#define MCTL 5, 1 /* CPU control SV */ +#define PID 6, 1 /* Processor ID SV */ +#define SCCFG 11, 1 /* SYSCALL operation setting SV */ +#define SCBP 12, 1 /* SYSCALL base pointer SV */ + +#define HTCFG0 0, 2 /* Thread configuration SV */ +#define MEA 6, 2 /* Memory error address SV */ +#define ASID 7, 2 /* Address space ID SV */ +#define MEI 8, 2 /* Memory error information SV */ +#define ISPR 10, 2 /* Priority of interrupt being serviced SV */ +#define PMR 11, 2 /* Interrupt priority masking SV */ +#define ICSR 12, 2 /* Interrupt control status SV */ +#define INTCFG 13, 2 /* Interrupt function setting SV */ + +#define MPM 0, 5 /* Memory protection operation mode setting SV */ +#define MPRC 1, 5 /* MPU region control SV */ +#define MPBRGN 4, 5 /* MPU base region number SV */ +#define MPTRGN 5, 5 /* MPU end region number SV */ +#define MCA 8, 5 /* Memory protection setting check address SV */ +#define MCS 9, 5 /* Memory protection setting check size SV */ +#define MCC 10, 5 /* Memory protection setting check command SV */ +#define MCR 11, 5 /* Memory protection setting check result SV */ + +#define MPLA0 0, 6 /* Protection area minimum address SV */ +#define MPUA0 1, 6 /* Protection area maximum address SV */ +#define MPAT0 2, 6 /* Protection area attribute SV */ +#define MPLA1 4, 6 /* Protection area minimum address SV */ +#define MPUA1 5, 6 /* Protection area maximum address SV */ +#define MPAT1 6, 6 /* Protection area attribute SV */ +#define MPLA2 8, 6 /* Lower address of the protection area SV */ +#define MPUA2 9, 6 /* Protection area maximum address SV */ +#define MPAT2 10, 6 /* Protection area attribute SV */ +#define MPLA3 12, 6 /* Protection area minimum address SV */ +#define MPUA3 13, 6 /* Protection area maximum address SV */ +#define MPAT3 14, 6 /* Protection area attribute SV */ +#define MPLA4 16, 6 /* Protection area minimum address SV */ +#define MPUA4 17, 6 /* Protection area maximum address SV */ +#define MPAT4 18, 6 /* Protection area attribute SV */ +#define MPLA5 20, 6 /* Protection area minimum address SV */ +#define MPUA5 21, 6 /* Protection area maximum address SV */ +#define MPAT5 22, 6 /* Protection area attribute SV */ +#define MPLA6 24, 6 /* Protection area minimum address SV */ +#define MPUA6 25, 6 /* Protection area maximum address SV */ +#define MPAT6 26, 6 /* Protection area attribute SV */ +#define MLUA7 28, 6 /* Protection area minimum address SV */ +#define MPUA7 29, 6 /* Protection area maximum address SV */ +#define MPAT7 30, 6 /* Protection area attribute SV */ + +#endif /* CPU_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cpu_on.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cpu_on.h new file mode 100644 index 0000000..754113e --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/cpu_on.h @@ -0,0 +1,62 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Power management driver header + ******************************************************************************/ + +#ifndef CPU_ON_H__ +#define CPU_ON_H__ +#include "remap_register.h" + +#define RCAR_PWR_TARGET_CR (0U) +#define RCAR_PWR_TARGET_CA (1U) + +#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 (0x00000001U << 1U) +#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0 (0x00000001U << 0U) +#define AP_CORE_APSREG_CCI500_AUX_ACTDIS (0x00000001U << 0U) +#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT (AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 | AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0) + + +#define OTP_MEM_1_BASE (BASE_OTP_MEM_ADDR) +#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U) +#define OTP_MEM_PRODUCT_MASK (0x000000FFU) + +#if (RCAR_LSI == RCAR_V4H) +#define VARIANT_V4H_7 (0x00U) +#define VARIANT_V4H_5 (0x01U) +#define VARIANT_V4H_3 (0x02U) +#elif (RCAR_LSI == RCAR_V4M) +#define VARIANT_V4M_7 (0x00U) +#define VARIANT_V4M_5 (0x01U) +#define VARIANT_V4M_3 (0x02U) +#define VARIANT_V4M_2 (0x04U) +#endif /* RCAR_LSI == RCAR_V4H */ + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void arm_cpu_on(uint32_t target, uint32_t boot_addr); +void adj_cr_variant_freq(void); + +#endif /* CPU_ON_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/dma.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/dma.h new file mode 100644 index 0000000..3aee2fe --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/dma.h @@ -0,0 +1,56 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : DMA driver header + ******************************************************************************/ + +#ifndef DMA_DRIVER_H__ +#define DMA_DRIVER_H__ + +#include +#include +#include + +/* fraction mask for 64-byte units */ +#define FRACTION_MASK_64_BYTE (0x0000003FU) + +/* Prototype */ +void dma_init(void); +void dma_trans_start(uint32_t dst, uint32_t src, uint32_t len); +void dma_trans_end_check(void); +void dma_release(void); + +/* Inline function */ +/* Check address align when RT-DMAC/SDMAC transfer */ +static inline void dma_address_align_check(uint32_t dst_addr, uint32_t src_addr) +{ + if (((src_addr & FRACTION_MASK_64_BYTE) != 0U) || ((dst_addr & FRACTION_MASK_64_BYTE) != 0U)) + { + /* src_addr or dst_addr are not 64-byte alignment. */ + ERROR("Not 64-byte alignment in DMA transfer\n"); + panic; + } +} + +#endif /* DMA_DRIVER_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/dma_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/dma_register.h new file mode 100644 index 0000000..bd06423 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/dma_register.h @@ -0,0 +1,154 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : DMA register header + ******************************************************************************/ + +#ifndef DMA_REGISTER_H_ +#define DMA_REGISTER_H_ + +#include +#include + +#define DMACH (0U) /* The range of DMA ch is 0-15. */ + +#if ((RCAR_LSI == RCAR_S4) || (RCAR_LSI == RCAR_V4H)) +#define RTDMA_MODULE_MAX (4U) +#define RTDMA_CH_MAX (16U) +#define SYSDMA_MODULE_MAX (2U) +#define SYSDMA_CH_MAX (16U) +#elif (RCAR_LSI == RCAR_V4M) +#define RTDMA_MODULE_MAX (2U) +#define RTDMA_CH_MAX (16U) +#define SYSDMA_MODULE_MAX (2U) +#define SYSDMA_CH_MAX (16U) +#endif + +/* RT-DMA Control */ +#define RTDMACTL_BASE (BASE_RTDMACTL_ADDR) + +#define RTDMA_DMOR (RTDMACTL_BASE + 0x0060U) /* DMA operation register */ + +/* RT-DMAC0(for RPC) */ +#define RTDMA0_BASE (BASE_RTDMA0_ADDR) +#define RTDMA1_BASE (RTDMA0_BASE + 0x00010000U) +#define RTDMA2_BASE (RTDMA0_BASE + 0x00160000U) +#define RTDMA3_BASE (RTDMA0_BASE + 0x00170000U) +/* SYSDMAC */ +#define SYSDMA0_BASE (BASE_DMA_ADDR) +#define SYSDMA1_BASE (SYSDMA0_BASE + 0x00010000U) + +#define RTDMA_DMSEC (RTDMA0_BASE + 0x00B0U) + +#define DMA_REGIONID_MASK (0x0000000FU) + + +static inline uint32_t dma_get_rtdma_sar_addr(uint32_t num) +{ + return (RTDMA0_BASE + 0x0000U + (num * 0x1000U)); +} + +static inline uint32_t dma_get_rtdma_dar_addr(uint32_t num) +{ + return (RTDMA0_BASE + 0x0004U + (num * 0x1000U)); +} + +static inline uint32_t dma_get_rtdma_tcr_addr(uint32_t num) +{ + return (RTDMA0_BASE + 0x0008U + (num * 0x1000U)); +} + +static inline uint32_t dma_get_rtdma_chcr_addr(uint32_t num) +{ + return (RTDMA0_BASE + 0x000CU + (num * 0x1000U)); +} + +static inline uint32_t dma_get_rtdma_module_base_addr(uint32_t module) +{ + uint32_t ret; + + if(module == 0U) + { + ret = RTDMA0_BASE; + } + else if(module == 1U) + { + ret = RTDMA1_BASE; + } +#if ((RCAR_LSI == RCAR_S4) || (RCAR_LSI == RCAR_V4H)) + else if(module ==2U) + { + ret = RTDMA2_BASE; + } + else if(module == 3U) + { + ret = RTDMA3_BASE; + } +#endif /* ((RCAR_LSI == RCAR_S4) || (RCAR_LSI == RCAR_V4H)) */ + else + { + ERROR("Invalid DMA module value!\n"); + panic; + } + return ret; +} + +static inline uint32_t dma_get_rtdma_regionid_addr(uint32_t module, uint32_t ch) +{ + uint32_t base; + base = dma_get_rtdma_module_base_addr(module); + + return (base + 0x0078U + (ch * 0x1000U)); +} + +static inline uint32_t dma_get_sysdma_module_base_addr(uint32_t module) +{ + uint32_t ret; + + if(module == 0U) + { + ret = SYSDMA0_BASE; + } + else if(module == 1U) + { + ret = SYSDMA1_BASE; + } + else + { + ERROR("Invalid DMA module value!\n"); + panic; + } + + return ret; +} + +static inline uint32_t dma_get_sysdma_regionid_addr(uint32_t module, uint32_t ch) +{ + uint32_t base; + base = dma_get_sysdma_module_base_addr(module); + + return (base + 0x0078U + (ch * 0x1000U)); +} + +#endif /* DMAREGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_boot.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_boot.h new file mode 100644 index 0000000..437c50c --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_boot.h @@ -0,0 +1,41 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC boot header + ******************************************************************************/ + +#ifndef EMMC_BOOT_ +#define EMMC_BOOT_ + +#include + +#define FLASH_BOOT (0U) +#define EMMC_BOOT (1U) + +#define CA_IPL (0U) +#define BL31 (1U) + +void emmc_initialize( void ); + +#endif /* EMMC_BOOT_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_config.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_config.h new file mode 100644 index 0000000..847fe7e --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_config.h @@ -0,0 +1,82 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC Config header + ******************************************************************************/ + +#ifndef EMMC_CONFIG_H__ +#define EMMC_CONFIG_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "cpg_register.h" +#include "pfc_register.h" +#include "cpg.h" +#include "pfc.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* MMC driver config */ +#define EMMC_RCA (1U) /* RCA */ +#define EMMC_RW_DATA_TIMEOUT (0x40U) /* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */ +#define EMMC_CMD_MAX (60U) /* Don't change. */ + +/* etc */ +#define LOADIMAGE_FLAGS_DMA_ENABLE (0x00000001U) + +/* Module stop */ +#define CPG_MSTPCR_SDHI (1U << 6U) + +/* clock */ +#define CPG_SD0CKCR0_STP0HCK (1U << 9U) +#define CPG_SD0CKCR0_SDSRCFC_MASK (7U << 2U) +#define CPG_SD0CKCR0_SDSRCFC_000 (0U << 2U) +#define CPG_SD0CKCR0_SDSRCFC_010 (2U << 2U) +#define CPG_SD0CKCR0_SD0FC_MASK (3U << 0U) +#define CPG_SD0CKCR0_SD0FC_DIV2 (0U << 0U) +#define CPG_SD0CKCR0_SD0FC_DIV4 (1U << 0U) +#define CPG_SD0CKCR0_100MHZ (CPG_SD0CKCR0_STP0HCK | CPG_SD0CKCR0_SDSRCFC_010 | CPG_SD0CKCR0_SD0FC_DIV2) +#define CPG_SD0CKCR0_200MHZ (CPG_SD0CKCR0_STP0HCK | CPG_SD0CKCR0_SDSRCFC_000 | CPG_SD0CKCR0_SD0FC_DIV4) + +#if (RCAR_LSI == RCAR_S4) +#define PFC_POC_MMC_RW (PFC_POC1_RW) +#define PFC_POC_MMC_MASK (0x007FF000U) +#define PFC_POC_MMC_VAL (0x00000000U) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define PFC_POC_MMC_RW (PFC_POC3_RW) +#define PFC_POC_MMC_MASK (0x000007FFU) +#define PFC_POC_MMC_VAL (0x00000000U) +#endif /* RCAR_LSI == RCAR_S4 */ + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* #ifndef EMMC_CONFIG_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_def.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_def.h new file mode 100644 index 0000000..74b2222 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_def.h @@ -0,0 +1,74 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC Define header + ******************************************************************************/ + +#ifndef EMMC_DEF_H__ +#define EMMC_DEF_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_std.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +#define EMMC_DEV_OK (0x525F4F4BU) /* "R_OK" */ +#define EMMC_DEV_ERR (0xFFFFFFFFU) +#define EMMC_DEV_ERR_HW (0x00000004U) +#define EMMC_DEV_ERR_FAULT_INJECTION (0x00000005U) + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ +extern st_mmc_base mmc_drv_obj; + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* eMMC driver API */ +EMMC_ERROR_CODE emmc_init(void); +EMMC_ERROR_CODE emmc_terminate(void); +EMMC_ERROR_CODE emmc_memcard_power(uint32_t mode); +EMMC_ERROR_CODE emmc_mount(void); +EMMC_ERROR_CODE emmc_set_request_mmc_clock(const uint32_t *freq); +EMMC_ERROR_CODE emmc_send_idle_cmd (uint32_t arg); +EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id); +EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, uint32_t feature_flags); +uint32_t emmc_bit_field (const uint8_t *data, uint32_t top, uint32_t bottom); + + +/* interrupt service */ +uint32_t emmc_interrupt(void); + + +/* send command API */ +EMMC_ERROR_CODE emmc_exec_cmd (uint32_t error_mask, uint32_t *response); +void emmc_make_nontrans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg); +void emmc_make_trans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual, + uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode); +EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg); + +/* ********************************* CODE ********************************** */ + +#endif /* #define EMMC_DEF_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_hal.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_hal.h new file mode 100644 index 0000000..1db49a6 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_hal.h @@ -0,0 +1,162 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC HAL driverd header + ******************************************************************************/ + +#ifndef EMMC_HAL_H__ +#define EMMC_HAL_H__ +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +/* Memory card response types */ +#define HAL_MEMCARD_COMMAND_INDEX_MASK (0x0003fU) + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* memory access operation */ +typedef enum +{ + HAL_MEMCARD_READ = 0U, /**< read */ + HAL_MEMCARD_WRITE = 1U /**< write */ +} HAL_MEMCARD_OPERATION; + +/* Type of data width on memorycard bus */ +typedef enum +{ + HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U, + HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U, + HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U +} HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */ + +/* mode of data transfer */ +typedef enum +{ + HAL_MEMCARD_DMA = 0U, + HAL_MEMCARD_NOT_DMA = 1U +} HAL_MEMCARD_DATA_TRANSFER_MODE; + + +/* Memory card response types. */ +typedef enum hal_memcard_response_type +{ + HAL_MEMCARD_RESPONSE_NONE = 0x00000U, + HAL_MEMCARD_RESPONSE_R1 = 0x00100U, + HAL_MEMCARD_RESPONSE_R1b = 0x00200U, + HAL_MEMCARD_RESPONSE_R2 = 0x00300U, + HAL_MEMCARD_RESPONSE_R3 = 0x00400U, + HAL_MEMCARD_RESPONSE_R4 = 0x00500U, + HAL_MEMCARD_RESPONSE_R5 = 0x00600U, + HAL_MEMCARD_RESPONSE_R6 = 0x00700U, + HAL_MEMCARD_RESPONSE_R7 = 0x00800U, + HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U +} HAL_MEMCARD_RESPONSE_TYPE; + + +/* Memory card command types. */ +typedef enum hal_memcard_command_type +{ + HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U, + HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U, + HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U, + HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U, + HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U, + HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U +} HAL_MEMCARD_COMMAND_TYPE; + +/* Type of memory card */ +typedef enum hal_memcard_command_card_type +{ + HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U +} HAL_MEMCARD_COMMAND_CARD_TYPE; + +/* Memory card application command. */ +typedef enum hal_memcard_command_app_norm +{ + HAL_MEMCARD_COMMAND_NORMAL = 0x00000U, + HAL_MEMCARD_COMMAND_APP = 0x20000U, + HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U +} HAL_MEMCARD_COMMAND_APP_NORM; + + +/* Memory card command codes. */ +typedef enum +{ +/* class 0 and class 1 */ + CMD0_GO_IDLE_STATE = 0 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD0 */ + CMD1_SEND_OP_COND = 1 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD1 */ + CMD2_ALL_SEND_CID_MMC = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD2 */ + CMD2_ALL_SEND_CID_SD = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD3_SET_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD3 */ + CMD3_SEND_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R6 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD4_SET_DSR = 4 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD4 */ + CMD5_SLEEP_AWAKE = 5 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD5 */ + CMD6_SWITCH = 6 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD6 */ + CMD6_SWITCH_FUNC = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + ACMD6_SET_BUS_WIDTH = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + CMD7_SELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7 */ + CMD7_SELECT_CARD_PROG = 7 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7(from Disconnected State to Programming State) */ + CMD7_DESELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, + CMD8_SEND_EXT_CSD = 8 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD8 */ + CMD8_SEND_IF_COND = 8 | HAL_MEMCARD_RESPONSE_R7 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD9_SEND_CSD = 9 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD9 */ + CMD10_SEND_CID = 10 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD10 */ + CMD11_READ_DAT_UNTIL_STOP = 11 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD11 */ + CMD12_STOP_TRANSMISSION = 12 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 */ + CMD12_STOP_TRANSMISSION_WRITE = 12 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 R1b : write case */ + CMD13_SEND_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD13 */ + ACMD13_SD_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + CMD14_BUSTEST_R = 14 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD14 */ + CMD15_GO_INACTIVE_STATE = 15 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD15 */ + +/* class 2 */ + CMD16_SET_BLOCKLEN = 16 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD16 */ + CMD17_READ_SINGLE_BLOCK = 17 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD17 */ + CMD18_READ_MULTIPLE_BLOCK = 18 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD18 */ + CMD19_BUS_TEST_W = 19 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD19 */ +/* class 3 */ + CMD20_WRITE_DAT_UNTIL_STOP = 20 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD20 */ + CMD21 = 21, /* CMD21 */ + CMD22 = 22, /* CMD22 */ + ACMD22_SEND_NUM_WR_BLOCKS = 22 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + +/* class 4 */ + CMD23_SET_BLOCK_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL /* CMD23 */ + +} HAL_MEMCARD_COMMAND; + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* EMMC_HAL_H__ */ + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_multiboot.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_multiboot.h new file mode 100644 index 0000000..35f7680 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_multiboot.h @@ -0,0 +1,44 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC Multi boot header + ******************************************************************************/ + +#ifndef EMMC_MULTIBOOT_H_ +#define EMMC_MULTIBOOT_H_ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + + +/* ************************** FUNCTION PROTOTYPES ************************** */ +uint32_t emmc_trans_data(uint32_t next_bootPartition, uintptr_t sourceSct, uintptr_t targetAd, uint32_t sectorSize); +/* ******************************** END ************************************ */ +#endif /* #ifndef EMMC_MULTIBOOT_H_*/ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_registers.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_registers.h new file mode 100644 index 0000000..e81d9a4 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_registers.h @@ -0,0 +1,146 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC register header + ******************************************************************************/ + +#ifndef EMMC_REGISTERS_H__ +#define EMMC_REGISTERS_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +/* MMC0 channel */ +#define MMC0_SD_BASE (BASE_MMC0_ADDR) /* reg addr is 0xEE140000U */ + +#define SD_CMD (MMC0_SD_BASE + 0x0000U) +#define SD_ARG (MMC0_SD_BASE + 0x0010U) +#define SD_STOP (MMC0_SD_BASE + 0x0020U) +#define SD_SECCNT (MMC0_SD_BASE + 0x0028U) +#define SD_RSP10 (MMC0_SD_BASE + 0x0030U) +#define SD_RSP32 (MMC0_SD_BASE + 0x0040U) +#define SD_RSP54 (MMC0_SD_BASE + 0x0050U) +#define SD_RSP76 (MMC0_SD_BASE + 0x0060U) +#define SD_INFO1 (MMC0_SD_BASE + 0x0070U) +#define SD_INFO2 (MMC0_SD_BASE + 0x0078U) +#define SD_INFO1_MASK (MMC0_SD_BASE + 0x0080U) +#define SD_INFO2_MASK (MMC0_SD_BASE + 0x0088U) +#define SD_CLK_CTRL (MMC0_SD_BASE + 0x0090U) +#define SD_SIZE (MMC0_SD_BASE + 0x0098U) +#define SD_OPTION (MMC0_SD_BASE + 0x00A0U) +#define SD_ERR_STS1 (MMC0_SD_BASE + 0x00B0U) +#define SD_ERR_STS2 (MMC0_SD_BASE + 0x00B8U) +#define SD_BUF0 (MMC0_SD_BASE + 0x00C0U) +#define CC_EXT_MODE (MMC0_SD_BASE + 0x0360U) +#define SOFT_RST (MMC0_SD_BASE + 0x0380U) +#define HOST_MODE (MMC0_SD_BASE + 0x0390U) +#define DM_CM_DTRAN_MODE (MMC0_SD_BASE + 0x0820U) +#define DM_CM_DTRAN_CTRL (MMC0_SD_BASE + 0x0828U) +#define DM_CM_INFO1 (MMC0_SD_BASE + 0x0840U) +#define DM_CM_INFO1_MASK (MMC0_SD_BASE + 0x0848U) +#define DM_CM_INFO2 (MMC0_SD_BASE + 0x0850U) +#define DM_CM_INFO2_MASK (MMC0_SD_BASE + 0x0858U) +#define DM_DTRAN_ADDR (MMC0_SD_BASE + 0x0880U) + + + +/* SD_INFO1 Registers */ +#define SD_INFO1_INFO2 (0x00000004U) /* Access end */ +#define SD_INFO1_INFO0 (0x00000001U) /* Response end */ + +/* SD_INFO2 Registers */ +#define SD_INFO2_CBSY (0x00004000U) /* Command Type Register Busy */ +#define SD_INFO2_BWE (0x00000200U) /* SD_BUF Write Enable */ +#define SD_INFO2_BRE (0x00000100U) /* SD_BUF Read Enable */ +#define SD_INFO2_DAT0 (0x00000080U) /* SDDAT0 */ +#define SD_INFO2_ALL_ERR (0x0000807FU) +#define SD_INFO2_CLEAR (0x00000800U) /* BIT11 The write value should always be 1. HWM_0003 */ + +/* DM_INFO1 Registers */ +#define DM_CM_INFO_DTRANEND0 (0x00010000U) /* DMAC Channel 0 Transfer End */ +#define DM_CM_INFO_DTRANEND1 (0x00020000U) /* DMAC Channel 0 Transfer End */ + +/* SOFT_RST */ +#define SOFT_RST_SDRST (0x00000001U) + +/* SD_CLK_CTRL */ +#define SD_CLK_CTRL_CLKDIV_MASK (0x000000FFU) +#define SD_CLK_WRITE_MASK (0x000003FFU) + +/* SD_OPTION */ +#define SD_OPTION_WIDTH (0x00008000U) +#define SD_OPTION_WIDTH8 (0x00002000U) +#define SD_OPTION_TIMEOUT_CNT_MASK (0x000000F0U) + + +/* MMC Clock Frequency + * 200MHz * 1/x = output clock + */ +#define MMC_400KHZ (512U) /* 200MHz * 1/512 = 390 KHz */ +#define MMC_20MHZ (16U) /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */ +#define MMC_26MHZ (8U) /* 200MHz * 1/8 = 25 MHz High speed mode 26Mhz */ +#define MMC_52MHZ (4U) /* 200MHz * 1/4 = 50 MHz High speed mode 52Mhz */ + + +#define MMC_FREQ_52MHZ (52000000U) +#define MMC_FREQ_26MHZ (26000000U) +#define MMC_FREQ_20MHZ (20000000U) + + +/* MMC Clock DIV */ +#define MMC_SD_CLK_START (0x00000100U) /* CLOCK On */ +#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */ + +/* DM_CM_DTRAN_MODE */ +#define DM_CM_DTRAN_MODE_CH0 (0x00000000U) /* CH0 : downstream */ +#define DM_CM_DTRAN_MODE_CH1 (0x00010000U) /* CH1 : upstream */ +#define DM_CM_DTRAN_MODE_BIT_WIDTH (0x00000030U) + +/* CC_EXT_MODE */ +#define CC_EXT_MODE_DMASDRW_ENABLE (0x00000002U) /* SD_BUF Read/Write DMA Transfer */ +#define CC_EXT_MODE_CLEAR (0x00001010U) /* BIT 12 & 4 always 1. */ + +/* DM_CM_INFO_MASK */ +#define DM_CM_INFO_MASK_CLEAR (0xFFFCFFFEU) +#define DM_CM_INFO_CH0_ENABLE (0x00010001U) +#define DM_CM_INFO_CH1_ENABLE (0x00020001U) + +/* DM_DTRAN_ADDR */ +#define DM_DTRAN_ADDR_WRITE_MASK (0xFFFFFFF8U) + +/*DM_CM_DTRAN_CTRL */ +#define DM_CM_DTRAN_CTRL_START (0x00000001U) + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* EMMC_REGISTERS_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_std.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_std.h new file mode 100644 index 0000000..3057bf7 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/emmc_std.h @@ -0,0 +1,263 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC standard header + ******************************************************************************/ + +#ifndef EMMC_STD_H__ +#define EMMC_STD_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_hal.h" +#include "emmc_registers.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/*CSD register Macros */ +#define EMMC_CSD_SPEC_VARS() (emmc_bit_field(mmc_drv_obj.csd_data, 125,122)) +#define EMMC_CSD_TRAN_SPEED() (emmc_bit_field(mmc_drv_obj.csd_data, 103,96)) + +/* for sector access */ +#define EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */ +#define EMMC_SECTOR_PADD_MASK ((1U << EMMC_SECTOR_SIZE_SHIFT) - 1U) +#define EMMC_SECTOR_SIZE (512U) +#define EMMC_BLOCK_LENGTH (512U) +#define EMMC_BLOCK_LENGTH_DW (128U) + +/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */ +typedef enum +{ + EMMC_ERR = 0U, /**< unknown error */ + EMMC_SUCCESS , /**< OK */ + EMMC_ERR_FROM_DMAC , /**< DMAC allocation error */ + EMMC_ERR_FROM_DMAC_TRANSFER , /**< DMAC transfer error */ + EMMC_ERR_CARD_STATUS_BIT , /**< card status error. Non-masked error bit was set in the card status */ + EMMC_ERR_CMD_TIMEOUT , /**< command timeout error */ + EMMC_ERR_DATA_TIMEOUT , /**< data timeout error */ + EMMC_ERR_CMD_CRC , /**< command CRC error */ + EMMC_ERR_DATA_CRC , /**< data CRC error */ + EMMC_ERR_PARAM , /**< parameter error */ + EMMC_ERR_RESPONSE , /**< response error */ + EMMC_ERR_RESPONSE_BUSY , /**< response busy error */ + EMMC_ERR_TRANSFER , /**< data transfer error */ + EMMC_ERR_READ_SECTOR , /**< read sector error */ + EMMC_ERR_WRITE_SECTOR , /**< write sector error */ + EMMC_ERR_STATE , /**< state error */ + EMMC_ERR_TIMEOUT , /**< timeout error */ + EMMC_ERR_ILLEGAL_CARD , /**< illegal card */ + EMMC_ERR_CARD_BUSY , /**< Busy state */ + EMMC_ERR_CARD_STATE , /**< card state error */ + EMMC_ERR_SET_TRACE , /**< trace information error */ + EMMC_ERR_FROM_TIMER , /**< Timer error */ + EMMC_ERR_FORCE_TERMINATE , /**< Force terminate */ + EMMC_ERR_CARD_POWER , /**< card power fail */ + EMMC_ERR_ERASE_SECTOR , /**< erase sector error */ + EMMC_ERR_INFO2 /**< exec cmd error info2 */ +} EMMC_ERROR_CODE; + +/* Response */ +/** R1 */ +#define EMMC_R1_ERROR_MASK (0xFDBFE080U) /* Type 'E' bit and bit14(must be 0). ignore bit22 */ +#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) /* Ignore bit23 (Not check CRC error) */ +#define EMMC_R1_STATE_MASK (0x00001E00U) /* [12:9] */ +#define EMMC_R1_READY (0x00000100U) /* bit8 */ +#define EMMC_R1_STATE_SHIFT (9U) + +/** R4 */ +#define EMMC_R4_STATUS (0x00008000U) + +/** CSD */ +#define EMMC_TRANSPEED_FREQ_UNIT_MASK (0x07U) /* bit[2:0] */ +#define EMMC_TRANSPEED_MULT_MASK (0x78U) /* bit[6:3] */ +#define EMMC_TRANSPEED_MULT_SHIFT (3U) + +/** OCR */ +#define EMMC_HOST_OCR_VALUE (0x40FF8080U) +#define EMMC_OCR_STATUS_BIT (0x80000000U) /* Card power up status bit */ +#define EMMC_OCR_ACCESS_MODE_MASK (0x60000000U) /* bit[30:29] */ +#define EMMC_OCR_ACCESS_MODE_SECT (0x40000000U) + +/** EXT_CSD */ +#define EMMC_EXT_CSD_CARD_TYPE (196U) +#define EMMC_EXT_CSD_PARTITION_CONFIG (179U) + +#define EMMC_EXT_CSD_CARD_TYPE_26MHZ (0x01U) +#define EMMC_EXT_CSD_CARD_TYPE_52MHZ (0x02U) + +/** SWITCH (CMD6) argument */ +#define EXTCSD_ACCESS_BYTE (0x03000000U) + +#define HS_TIMING_ADD (185U<<16U) /* H'b9 */ +#define HS_TIMING_1 (1U<<8U) + +#define BUS_WIDTH_ADD (183U<<16U) /* H'b7 */ +#define BUS_WIDTH_1 (0U<<8U) + +#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1) /**< H'03b90100 */ + +#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1) /**< H'03b70000 */ +#define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL /**< Partition config = 0x00 */ + +/** for st_mmc_base */ +#define EMMC_MAX_RESPONSE_LENGTH (17U) +#define EMMC_MAX_CID_LENGTH (16U) +#define EMMC_MAX_CSD_LENGTH (16U) +#define EMMC_MAX_EXT_CSD_LENGTH (512U) + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* Partition id */ +typedef enum +{ + PARTITION_ID_USER = 0x0, /**< User Area */ + PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */ + PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */ + PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */ + PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */ + PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */ + PARTITION_ID_GP_3 = 0x6, /**< General Purpose partition 3 */ + PARTITION_ID_GP_4 = 0x7, /**< General Purpose partition 4 */ + PARTITION_ID_MASK = 0x7 /**< [2:0] */ +} EMMC_PARTITION_ID; + +/* card state in R1 response [12:9] */ +typedef enum +{ + EMMC_R1_STATE_IDLE = 0, + EMMC_R1_STATE_READY, + EMMC_R1_STATE_IDENT, + EMMC_R1_STATE_STBY, + EMMC_R1_STATE_TRAN, + EMMC_R1_STATE_DATA, + EMMC_R1_STATE_RCV, + EMMC_R1_STATE_PRG, + EMMC_R1_STATE_DIS, + EMMC_R1_STATE_BTST, + EMMC_R1_STATE_SLEP +} EMMC_R1_STATE; + +typedef enum{ + ESTATE_BEGIN = 0, + ESTATE_ISSUE_CMD, + ESTATE_NON_RESP_CMD, + ESTATE_RCV_RESP, + ESTATE_RCV_RESPONSE_BUSY, + ESTATE_CHECK_RESPONSE_COMPLETE, + ESTATE_DATA_TRANSFER, + ESTATE_DATA_TRANSFER_COMPLETE, + ESTATE_ACCESS_END, + ESTATE_TRANSFER_ERROR, + ESTATE_ERROR, + ESTATE_END +}EMMC_INT_STATE; + +/* eMMC boot driver error information */ +typedef struct +{ + volatile uint32_t info1; /**< SD_INFO1 register value. (hardware dependence) */ + volatile uint32_t info2; /**< SD_INFO2 register value. (hardware dependence) */ + volatile uint32_t status1; /**< SD_ERR_STS1 register value. (hardware dependence) */ + volatile uint32_t status2; /**< SD_ERR_STS2 register value. (hardware dependence) */ + volatile uint32_t dm_info1; /**< DM_CM_INFO1 register value. (hardware dependence) */ + volatile uint32_t dm_info2; /**< DM_CM_INFO2 register value. (hardware dependence) */ +} st_error_info; + + +/* Command information */ +typedef struct +{ + HAL_MEMCARD_COMMAND cmd; /**< Command information */ + uint32_t arg; /**< argument */ + HAL_MEMCARD_OPERATION dir; /**< direction */ + uint32_t hw; /**< H/W dependence. SD_CMD register value. */ +} st_command_info; + + +/* MMC driver base */ +typedef struct +{ + st_error_info error_info; /**< error information */ + st_command_info cmd_info; /**< command information */ + + /* for data transfer */ + uint32_t *buff_address_virtual; /**< Dest or Src buff */ + uint32_t *buff_address_physical; /**< Dest or Src buff */ + HAL_MEMCARD_DATA_WIDTH bus_width; /**< bus width */ + uint32_t trans_size; /**< transfer size for this command */ + uint32_t remain_size; /**< remain size for this command */ + uint32_t response_length; /**< response length for this command */ + + /* clock */ + uint32_t max_freq; /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */ + uint32_t current_freq; /**< current MMC clock[Hz] (the closest frequency supported by HW) */ + + /* state flag */ + uint32_t card_power_enable; /**< True : Power ON */ + uint32_t clock_enable; /**< True : Clock ON */ + uint32_t initialize; /**< True : initialize complete. */ + uint32_t mount; /**< True : mount complete. */ + uint32_t selected; /**< True : selected card. */ + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; /**< 0: DMA, 1:PIO */ + EMMC_R1_STATE current_state; /**< card state */ + volatile uint32_t during_transfer; /**< True : during transfer */ + volatile uint32_t during_dma_transfer; /**< True : during transfer (DMA)*/ + volatile uint32_t dma_error_flag; /**< True : occurred DMAC error */ + volatile uint32_t force_terminate; /**< force terminate flag */ + volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */ + + /* timeout */ + uint32_t data_timeout; /**< read and write data timeout.*/ + + /* interrupt */ + volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */ + volatile uint32_t int_event2; /**< interrupt SD_INFO2 Event */ + volatile uint32_t dm_event1; /**< interrupt DM_CM_INFO1 Event */ + volatile uint32_t dm_event2; /**< interrupt DM_CM_INFO2 Event */ + + /* response */ + uint32_t *response; /**< pointer to buffer for executing command. */ + uint32_t r1_card_status; /**< R1 response data */ + uint32_t r3_ocr; /**< R3 response data */ + uint32_t r4_resp; /**< R4 response data */ + uint32_t r5_resp; /**< R5 response data */ + + /* Card registers (4byte align) */ + uint8_t csd_data[EMMC_MAX_CSD_LENGTH]; /**< CSD */ + uint8_t cid_data[EMMC_MAX_CID_LENGTH]; /**< CID */ + uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH]; /**< EXT_CSD */ + uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH]; /**< other response */ + + /* SDHI base address */ + uintptr_t base_address; +} st_mmc_base; + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +/* ******************************** END ************************************ */ +#endif /* EMMC_STD_H__ */ + /* EMMC_STD_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/fcpr.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/fcpr.h new file mode 100644 index 0000000..0e85a3c --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/fcpr.h @@ -0,0 +1,45 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : FCPR driver header + ******************************************************************************/ + +#ifndef FCPR_H__ +#define FCPR_H__ + +#include + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ +#define FCPR_DISABLE (0U) +#define FCPR_ENABLE (1U) + +#define COMPRESSION_START_ADDR (0x80000000U) +#define COMPRESSION_END_ADDR (0xA2FFFFFFU) +#define COMPRESSION_ENABLE (0x00000001U) + +void fcpr_init(void); + +#endif /* FCPR_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/fcpr_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/fcpr_register.h new file mode 100644 index 0000000..dc2f5ca --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/fcpr_register.h @@ -0,0 +1,46 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : FCPR register header + ******************************************************************************/ + +#ifndef FCPR_REGISTER_H__ +#define FCPR_REGISTER_H__ + +#include + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ +/* CPG base address */ +/* 0xE6785700 */ +#define FCPR_BASE (BASE_FCPR_ADDR) + +/* FCPR */ +#define FCPR_CMP_CTRL (BASE_FCPR_ADDR + 0x0030U) +#define FCPR_CMP_SPACE (BASE_FCPR_ADDR + 0x0080U) +#define FCPR_CMP_STADR (BASE_FCPR_ADDR + 0x0084U) +#define FCPR_CMP_EDADR (BASE_FCPR_ADDR + 0x0088U) + +#endif /* FCPR_REGISTER_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/hscif_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/hscif_register.h new file mode 100644 index 0000000..7b33171 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/hscif_register.h @@ -0,0 +1,49 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : HSCIF register header + ******************************************************************************/ + + +#ifndef HSCIF_REGISTER_H_ +#define HSCIF_REGISTER_H_ + +#include + +/* HSCIF0 base address */ +/* 0xE6540000U */ +#define HSCIF0_BASE (BASE_HSCIF_ADDR) + +#define HSCIF_HSSMR (HSCIF0_BASE + 0x0000U) /* 16 Serial mode register */ +#define HSCIF_HSBRR (HSCIF0_BASE + 0x0004U) /* 8 Bit rate register */ +#define HSCIF_HSSCR (HSCIF0_BASE + 0x0008U) /* 16 Serial control register */ +#define HSCIF_HSFTDR (HSCIF0_BASE + 0x000CU) /* 8 Transmit FIFO data register */ +#define HSCIF_HSFSR (HSCIF0_BASE + 0x0010U) /* 16 Serial status register */ +#define HSCIF_HSFCR (HSCIF0_BASE + 0x0018U) /* 16 FIFO control register */ +#define HSCIF_HSLSR (HSCIF0_BASE + 0x0024U) /* 16 Line status register */ +#define HSCIF_DL (HSCIF0_BASE + 0x0030U) /* 16 Frequency division register */ +#define HSCIF_CKS (HSCIF0_BASE + 0x0034U) /* 16 Clock Select register */ +#define HSCIF_HSSRR (HSCIF0_BASE + 0x0040U) /* 16 Sampling rate register */ + +#endif /* HSCIF_REGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/i2c.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/i2c.h new file mode 100644 index 0000000..5c22af8 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/i2c.h @@ -0,0 +1,65 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : I2C driver header + ******************************************************************************/ + +#ifndef I2C_DRIVER_H__ +#define I2C_DRIVER_H__ + +#define FLG_RW (0x00000001U) + +#define I2C_OK (0x00000000U) +#define I2C_NG (0x00000001U) + +#define SET_SCGD (0x00000018U) +#define SET_CDF (0x00000007U) + +#define FLAG_MDBS (0x00000080U) +#define FLAG_FSCL (0x00000040U) +#define FLAG_FSDA (0x00000020U) +#define FLAG_MIE (0x00000008U) +#define FLAG_FSB (0x00000002U) +#define FLAG_ESG (0x00000001U) + +#define FLAG_MNR (0x00000040U) +#define FLAG_MAL (0x00000020U) +#define FLAG_MST (0x00000010U) +#define FLAG_MDE (0x00000008U) +#define FLAG_MDT (0x00000004U) +#define FLAG_MDR (0x00000002U) +#define FLAG_MAT (0x00000001U) + +#define FLAG_NONE (0U) + +#define ERR_MAX (1U) + +void i2c3_init(void); +void i2c3_write(uint32_t slaveAdd, uint32_t regAdd, uint32_t setData); +void i2c3_read(uint32_t slaveAdd, uint32_t regAdd, uint32_t *revData); +uint32_t i2c3_err_check(uint32_t first, uint32_t second, uint32_t error); +void i2c3_release(void); + +#endif /* I2C_DRIVER_H__ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/i2c_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/i2c_register.h new file mode 100644 index 0000000..1e78fe1 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/i2c_register.h @@ -0,0 +1,62 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : I2C register header + ******************************************************************************/ + +#ifndef I2C_REGISTER_H__ +#define I2C_REGISTER_H__ + +#include + +/* I2C ch6 base address */ +#define I2C3_BASE (BASE_I2C3_ADDR) /* Physical address:0xE66D0000, Logical address:0xFDCD0000 */ + +/* Slave control register */ +#define I2C3_ICSCR (I2C3_BASE + 0x0000U) +/* Master control register */ +#define I2C3_ICMCR (I2C3_BASE + 0x0004U) +/* Slave status register */ +#define I2C3_ICSSR (I2C3_BASE + 0x0008U) +/* Master status register */ +#define I2C3_ICMSR (I2C3_BASE + 0x000CU) +/* Slave interrupt enable register */ +#define I2C3_ICSIER (I2C3_BASE + 0x0010U) +/* Master interrupt enable register */ +#define I2C3_ICMIER (I2C3_BASE + 0x0014U) +/* Clock control register */ +#define I2C3_ICCCR (I2C3_BASE + 0x0018U) +/* Slave address register */ +#define I2C3_ICSAR (I2C3_BASE + 0x001CU) +/* Master address register */ +#define I2C3_ICMAR (I2C3_BASE + 0x0020U) +/* Recieve data register */ +#define I2C3_ICRXD (I2C3_BASE + 0x0024U) +/* Transmit data register */ +#define I2C3_ICTXD (I2C3_BASE + 0x0024U) +/* Clock control register 2 */ +#define I2C3_ICCCR2 (I2C3_BASE + 0x0028U) + +#endif /* I2C_REGISTER_H__ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/image_load.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/image_load.h new file mode 100644 index 0000000..1c1d633 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/image_load.h @@ -0,0 +1,150 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function header + ******************************************************************************/ + +#ifndef LOAD_IMAGE_H_ +#define LOAD_IMAGE_H_ + +/* define */ +/* For Build Option RTOS_LOAD_NUM */ +#define RTOS_LOAD_NUM_1 (1U) /* RTOS is RTOS#0 only. */ +#define RTOS_LOAD_NUM_3 (3U) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */ + +/* For Build Option OPTEE_LOAD_ENABLE */ +#define OPTEE_DISABLE (0U) /* Load OP-TEE image disable. */ +#define OPTEE_ENABLE (1U) /* Load OP-TEE image enable. */ + +/* ICUMX Loader */ +#define IPL_TOP (0xEB210000U) +#define IPL_SIZE (128U * 1024U) +#define IPL_END ((IPL_TOP +IPL_SIZE) - 1U) + +#define MCU_OFFSET (0x0200U) /* 512byte */ + +/* Certificate logical address */ +extern char __ghsbegin_sa9_load[]; +#define SA9_DEST_ADDR (uintptr_t)(&__ghsbegin_sa9_load[0]) +#define CONTENT_CERT_OFFSET (0x6000U) + +/* key cert address */ +#define TFMV_KEY_CERT_ADDR (SA9_DEST_ADDR + CONTENT_CERT_INFO_SIZE) /* 0xFDE31000 */ +#define NTFMV_KEY_CERT_ADDR (TFMV_KEY_CERT_ADDR + KEY_CERT_SIZE) /* 0xFDE33000 */ + +/* Size of each content contained in SA9. */ +#define KEY_CERT_SIZE (0x00002000U) /* Key cert size(8KiB) */ +#define CONTENT_CERT_INFO_SIZE (0x00001000U) /* Content cert header size(4KiB) */ +#define CONTENT_CERT_SIZE (0x00000800U) /* content cert src size(2KiB) */ +#define MIN_VER_TBL_SIZE (0x00001000U) /* Software minimum version table */ + +/* Load ID */ +#define SECURE_FW_ID (0U) /* 0:Secure Firmware */ +#define RTOS_ID (1U) /* 1:RTOS#0 */ +#define CA_PROGRAM_ID (2U) /* 2:CX 2nd IPL */ +#define ICUMH_PROGRAM_ID (3U) /* 3:ICUMH program */ +#define G4MH_PROGRAM_ID (4U) /* 4:G4MH program(1st) 5:G4MH program(2nd) */ +#define CA_OPTIONAL_ID (6U) /* 6:CA Program#1, 7:CA Program#2 ... 13:CA Program#8 */ +#define TFMV_MIN_VER_TBL_ID (14U) /* 14:TFMV Software minimum version table */ +#define NTFMV_MIN_VER_TBL_ID (15U) /* 15:NTFMV Software minimum version table */ +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RTOS1_ID (16U) /* 16:RTOS#1 */ +#define RTOS2_ID (17U) /* 17:RTOS#2 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* Number of Max loading image */ +#define NUM_OF_ALWAYS_LOAD_CERT (6U) /* Secure FW + RTOS + Cx IPL + ICUMH + (G4MH * 2) */ +#define CA_MAX_IMAGE (8U) /* CA program MAX image num */ + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1) +#define MAX_PLACED (16U) /* IPL (or minimum version table) + Secure FW + RTOS * + * + Cx IPL + (CA program * 8) + ICUMH + G4MH */ +#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define MAX_PLACED (18U) /* IPL (or minimum version table) + Secure FW + RTOS#0 * + * + Cx IPL + (CA program * 8) + ICUMH + G4MH + RTOS#1 + RTOS#2 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_1 */ + +#define TARGET_MEM_DRAM (0U) +#define TARGET_MEM_RTSRAM (1U) +#define TARGET_MEM_RTVRAM (2U) +#define TARGET_MEM_SYSRAM (3U) +#define TARGET_MEM_CODESRAM (4U) + +/* get info from cert address offset */ +#define CERT_INFO_SIZE_OFFSET (0x00000264U) /* Offset Type1 */ +#define CERT_INFO_DST_OFFSET (0x00000154U) /* Offset Type1 */ +#define CERT_INFO_SIZE_OFFSET1 (0x00000364U) /* Offset Type2 */ +#define CERT_INFO_DST_OFFSET1 (0x000001D4U) /* Offset Type2 */ +#define CERT_INFO_SIZE_OFFSET2 (0x00000464U) /* Offset Type2 */ +#define CERT_INFO_DST_OFFSET2 (0x00000254U) /* Offset Type2 */ + +#define FLASH_BOOT (0U) +#define EMMC_BOOT (1U) + +#define CERT_INFO_FLG_OFFSET (0x0000000CU) +#define KEY_SIZE_BIT_SHIFT (21U) + +/* Parameter info of secure data (for ICUM FW) */ +#define SECUREDATA_SIZE (112U * 1024U) /* 112KB */ + +/* struct */ +/* load address range */ +typedef struct { + uint32_t topadd; + uint32_t endadd; +} ADDRESS_RANGE; + +/* load info */ +typedef struct{ + const char *name; /* store load image name */ + uint32_t image_size; /* store image size */ + uint32_t boot_addr; /* store boot address of image */ + uint32_t key_cert_addr; /* store key cert address */ + uint32_t cnt_cert_addr; /* store content cert address */ + uint32_t src_addr; /* store source address */ + uint32_t part_num; /* store eMMC partition number */ + uint32_t image_id; /* store image ID */ +} LOAD_INFO; + +static inline uint32_t get_src_addr_offset_in_cert(uint32_t id) +{ + return (SA9_DEST_ADDR + ((id * 0x10U) + 0x8U)); +} + +static inline uint32_t get_logic_cont_cert_addr(uint32_t num) +{ + return (SA9_DEST_ADDR + CONTENT_CERT_OFFSET + (num * CONTENT_CERT_SIZE)); +} + +/* Prototype */ +uint32_t load_content_cert(void); +void load_image(LOAD_INFO* li); +void load_init(LOAD_INFO* li); +void check_load_area(const LOAD_INFO* li); +void load_start(const LOAD_INFO* li); +void load_end(void); +void check_overflow(uint32_t addr, uint32_t len, uint32_t *end_addr, const char *func_name); +void load_securedata(uint32_t target_id); +#endif /* LOAD_IMAGE_H_ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/image_load_emmc.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/image_load_emmc.h new file mode 100644 index 0000000..64831f2 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/image_load_emmc.h @@ -0,0 +1,73 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function for eMMC header + ******************************************************************************/ + +#ifndef LOAD_IMAGE_EMMC_H_ +#define LOAD_IMAGE_EMMC_H_ + +#include +#include +#include +#include + +/* define */ +/* eMMC */ +#define EMMC_TOP (0x00000000U) +#define EMMC_BOOT_PART_SIZE (31U * 1024U * 1024U) /* 31MB */ +#define EMMC_END ((EMMC_TOP + EMMC_BOOT_PART_SIZE) - 1U) +#define SRC_TOP (EMMC_TOP) +#define SRC_END (EMMC_END) + +/* For eMMC */ +#define EMMC_SECTOR_SIZE (512U) +#define EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */ +#define EMMC_CONTENT_CERT_ADDR (0x00240000U) +#define EMMC_CONTENT_CERT_SECTOR_NUMBER (EMMC_CONTENT_CERT_ADDR >> EMMC_SECTOR_SIZE_SHIFT) +#define EMMC_PARTITION_1 (1U) +#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) +#define EMMC_VER_TBL_OFFSET (0x0000D000U) +#define EMMC_VER_TBL_CNT_CERT_ADDR (EMMC_CONTENT_CERT_ADDR + EMMC_VER_TBL_OFFSET) +#define EMMC_VER_TBL_CNT_CERT_SEC_NUM (EMMC_VER_TBL_CNT_CERT_ADDR >> EMMC_SECTOR_SIZE_SHIFT) +#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */ + +static inline void load_image_info_print_for_emmc(const LOAD_INFO* li) +{ + NOTICE("======== %s image load info ========\n" + "load address \t= 0x%08x\n" "image size \t= 0x%08x\n" + "source address \t= (p:%d)0x%08x\n", + li->name, li->boot_addr, li->image_size, + li->part_num, li->src_addr); +} + +static inline uint32_t get_part_num_in_cert(uint32_t id) +{ + return (SA9_DEST_ADDR + ((id + 1U) * 0x10U)); +} + +/* Prototype */ +uint32_t load_content_cert_for_emmc(void); +#endif /* LOAD_IMAGE_EMMC_H_ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/image_load_flash.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/image_load_flash.h new file mode 100644 index 0000000..34674a6 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/image_load_flash.h @@ -0,0 +1,68 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function for eMMC header + ******************************************************************************/ + +#ifndef LOAD_IMAGE_FLASH_H_ +#define LOAD_IMAGE_FLASH_H_ + +#include +#include +#include +#include + +/* define */ +/* Flash address */ +#define FLASH_BASE (0x08000000U) +#define FLASH_SIZE (0x04000000U) +#define FLASH_END ((FLASH_BASE + FLASH_SIZE) - 1U) +#define SRC_TOP (FLASH_BASE) +#define SRC_END (FLASH_END) + +/* Flash address of content certificate */ +#define CONTENT_CERT_SA (9U) /* Content Cert SA9 */ +#define SA_SIZE (0x00040000U) +#define FLASH_CONTENT_CERT_ADDR (uint32_t)(FLASH_BASE + (SA_SIZE * CONTENT_CERT_SA)) /* FLASH Base + SA9 offset */ +#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) +#define VER_TBL_CNT_CERT_OFFSET (0x0000D000U) +#define FLASH_VER_TBL_CNT_CERT_ADDR (FLASH_CONTENT_CERT_ADDR + VER_TBL_CNT_CERT_OFFSET) /* SA9 top + offset */ +#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */ +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RTOS12_CNT_CERT_OFFSET (0x0000E000U) +#define FLASH_RTOS12_CNT_CERT_ADDR (FLASH_CONTENT_CERT_ADDR + RTOS12_CNT_CERT_OFFSET) /* SA9 top + offset */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +static inline void load_image_info_print_for_flash(const LOAD_INFO* li) +{ + NOTICE("======== %s image load info ========\n" + "load address \t= 0x%08x\n" "image size \t= 0x%08x\n" + "source address \t= 0x%08x\n", + li->name, li->boot_addr, li->image_size, li->src_addr); +} + +/* Prototype */ +uint32_t load_content_cert_for_flash(void); +#endif /* LOAD_IMAGE_FLASH_H_ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/inline_asm.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/inline_asm.h new file mode 100644 index 0000000..5f9f38f --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/inline_asm.h @@ -0,0 +1,41 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : inline asm func header + ******************************************************************************/ + +#ifndef INLINE_ASM_H__ +#define INLINE_ASM_H__ + +static inline void syncm(void) +{ + __asm__ __volatile__ ("SYNCM"); +} + +static inline void synci(void) +{ + __asm__ __volatile__ ("SYNCI"); +} + +#endif /* INLINE_ASM_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/intc.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/intc.h new file mode 100644 index 0000000..b783201 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/intc.h @@ -0,0 +1,58 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : window watchdog timer function header + ******************************************************************************/ + +#ifndef INTC_H__ +#define INTC_H__ + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + +#define INTC1_BASE (0xFFFEEA00UL) +#define INTC2_BASE (0xFFFEF000UL) + +typedef void (* INT_HANDLER)(uint32_t int_no, uint32_t arg); + +static inline uint32_t get_icumx_ic_addr(uint32_t id) +{ + uint32_t ret; + if(id < 32U) + { + ret = INTC1_BASE + (0x02U * (id % 32U)); + } + else + { + ret = (INTC2_BASE + 0x40U) + (0x02U * (id % 32U)); + } + return ret; +} + +void intc_set_interrupt(uint32_t int_no, uint32_t level, INT_HANDLER cb); +void intc_disable_interrupt(uint32_t int_no); +void intc_handler(void); + +#endif /* INTC_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/intc_id.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/intc_id.h new file mode 100644 index 0000000..764ab7a --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/intc_id.h @@ -0,0 +1,71 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Interrupt controler ID header + ******************************************************************************/ + +#ifndef INTC_ID_H_ +#define INTC_ID_H_ + +#define ECC_ERR_LRAM (0U) /* ECC Error Detection for Local RAM */ +#define ECC_ERR_CACHE (1U) /* ECC Error Detection for Cache RAM */ +#define EDC_ERR_INT_AXI (2U) /* EDC Error interrupt of AXI */ +#define ECC_ERR_INT_AXIAB (3U) /* ECC Error interrupt of AXIAB */ +#define ECC_ERR_INT_PKCC (4U) /* ECC Error interrupt of PKCC */ +#define CORTEX_INT_REQ_SINGLE_CORE (5U) /* Cortex-R/A interrupt request (single main core) */ +#define CORTEX_INT_REQ_SEL_SINGLE_CORE (6U) /* Cortex-R/A interrupt request (selected single main core) */ +#define COMPLETION_AES (7U) /* Completion of AES encryption or decryption */ + /* ID 8 Reserved */ +#define COMPLETION_RAND_NUMBER (9U) /* Random number generation complete */ +#define OSTIMER0_OVERFLOW (10U) /* OS Timer 0 overflow */ +#define OSTIMER1_OVERFLOW (11U) /* OS Timer 1 overflow */ +#define WDT0_INT (12U) /* Watchdog Timer 0 interrupt (at 75%) */ +#define COMPLETION_PKCC (13U) /* Completion of PKCC operation */ +#define COMPLETION_DMAC_CH5CH6 (14U) /* Interrupt request by transfer completion for channel-5/6 */ +#define INT_REQ_BRESP_RRESP_ERR_AXI (15U) /* Interrupt request by BRESP/RRESP-error for AXI */ + /* ID 16 Reserved */ +#define REQ_SHAA0 (17U) /* Input data request for SHAA0 */ +#define COMPLETION_SHAA0 (18U) /* Completion or suspension of SHAA0 data output */ +#define REQ_CHALLENGE_DATA_FOR_ARM_DEBUG (19U) /* Challenge data request for ARM Debugger */ +#define REQ_RES_COMP_FOR_ARM_DEBUG (20U) /* Response data compare request for ARM Debugger */ +#define REQ_CHALLENGE_DATA_FOR_RH850_DEBUG (21U) /* Challenge data request for RH850 Debugger */ +#define REQ_RES_COMP_FOR_RH850_DEBUG (22U) /* Response data compare request for RH850 Debugger */ +#define REQ_CHALLENGE_DATA_FOR_RH850_DEBUG_R (23U) /* Challenge data request for RH850 Debugger r */ + /* Reserved */ +#define ACC_ERR_MASKROM_RTSRAM (25U) /* Data access error detection of Mask ROM or RTSRAM area */ +#define ACC_ERR_EXCEPT_MASKROM_RTSRAM (26U) /* Data access error detection except Mask ROM and RT-SRAM area */ + /* ID 27 Reserved */ + /* ID 28 Reserved */ +#define RTSRAM_SAFETY_ERR (29U) /* RT-SRAM Error Safety Error Detection */ +#define RTSRAM_SECURE_ERR (30U) /* RT-SRAM Error Secure Error Detection */ +#define RTSRAM_EDC_ERR (31U) /* RT-SRAM Error EDC Error Detection */ +#define RTSRAM_DUPLEX_ERR (32U) /* RT-SRAM Error Duplex circuit Error Detection */ +#define RTSRAM_SYSRAM_2BIT_ERR (33U) /* RT-SRAM Error SYSRAM 2bit Error Detection */ +#define RTSRAM_SYSRAM_1BIT_ERR (34U) /* RT-SRAM Error SYSRAM 1bit Error Detection */ +#define SECROM_SYSRAM_2BIT_ERR (35U) /* Sec ROM Error SYSRAM 2bit Error Detection */ +#define SECROM_SYSRAM_1BIT_ERR (36U) /* Sec ROM Error SYSRAM 1bit Error Detection */ +#define COMPLETION_SECURE_BOOT_ENGINE_CALC (37U) /* Completion of secure boot engine calculation */ + /* ID 38 -- 63 Reserved */ + +#endif /* INTC_ID_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/ip_control.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/ip_control.h new file mode 100644 index 0000000..aefd1f4 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/ip_control.h @@ -0,0 +1,34 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : IP's control header + ******************************************************************************/ +#ifndef IP_CONTROL_H_ +#define IP_CONTROL_H_ + +/* Prototype */ +void ip_init(void); +void ip_release(void); + +#endif /* IP_CONTROL_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/loader_main.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/loader_main.h new file mode 100644 index 0000000..3a250e9 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/loader_main.h @@ -0,0 +1,36 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main header + ******************************************************************************/ + +#ifndef LOADER_MAIN_H_ +#define LOADER_MAIN_H_ + +/* prototype */ +uint32_t loader_main(void); +#if (RCAR_LSI == RCAR_V4H) +void clear_ecm_st_axi(void); +#endif +#endif /* LOAD_MAIN_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/loader_main_common.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/loader_main_common.h new file mode 100644 index 0000000..6b8d8bd --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/loader_main_common.h @@ -0,0 +1,44 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main common header + ******************************************************************************/ + +#ifndef LOADER_MAIN_COMMON_H_ +#define LOADER_MAIN_COMMON_H_ + + +/* define */ +#define IPL_VERSION "1.58.0" + +#define ADD_MAGIC_NUMBER (1U) + +/* Global */ +extern const char build_message[]; + +/* prototype */ +void print_boot_msg(void); +void wa_setting_apmu(void); + +#endif /* LOADER_MAIN_COMMON_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/log.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/log.h new file mode 100644 index 0000000..df767b8 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/log.h @@ -0,0 +1,86 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Log driver header + ******************************************************************************/ + +#ifndef LOG_H__ +#define LOG_H__ + +#include +#include + +#define LOG_NONE (0) +#define LOG_ERROR (1) +#define LOG_NOTICE (2) +#define LOG_WARNING (3) +#define LOG_INFO (4) +#define LOG_VERBOSE (5) + +#if LOG_LEVEL >= LOG_ERROR +#include +#endif + +#if LOG_LEVEL >= LOG_VERBOSE +# define VERBOSE(...) local_printf("V:" __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + +#if LOG_LEVEL >= LOG_INFO +# define INFO(...) local_printf("I:" __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_WARNING +# define WARN(...) local_printf("W:" __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_ERROR +# define ERROR(...) local_printf("E:" __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_NOTICE +# define NOTICE(...) local_printf("N:" __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#define panic \ + do { \ + panic_printf(__func__); \ + while(true){} \ + } while (false) + +#if LOG_LEVEL >= LOG_ERROR +void local_printf(const char *fmt, ...); +#endif +void panic_printf(const char *str); + +#endif /* LOG_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/mcu_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/mcu_register.h new file mode 100644 index 0000000..bd28444 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/mcu_register.h @@ -0,0 +1,125 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MCU register header + ******************************************************************************/ + +#ifndef MCU_REGISTER_H_ +#define MCU_REGISTER_H_ + +#include + +/* The Base is remapped in the IPL, and the address is calculated and accessed + * by adding the offset to the remapped address. */ +#define MCU_BASE (BASE_MCU_ADDR) + +/* SCDS0 (0xD8F00800) */ +#define MCU_ICUM_OPBT0 (MCU_BASE + 0x09C0U) +#define MCU_ICUM_OPBT1 (MCU_BASE + 0x09C4U) +#define MCU_ICUM_OPBT2 (MCU_BASE + 0x09C8U) +#define MCU_ICUM_OPBT4 (MCU_BASE + 0x09D0U) +#define MCU_ICUM_OPBT5 (MCU_BASE + 0x09D4U) +#define MCU_ICUM_OPBT6 (MCU_BASE + 0x09D8U) +#define MCU_ICUM_OPBT7 (MCU_BASE + 0x09DCU) +#define MCU_GREG120 (MCU_BASE + 0x09E0U) + +/* SCDS2 (0xD8F00C00) */ +#define MCU_RESET_VECTOR_PE0 (MCU_BASE + 0x0C00U) +#define MCU_RESET_VECTOR_PE1 (MCU_BASE + 0x0C04U) +#define MCU_OPBT0 (MCU_BASE + 0x0C20U) +#define MCU_OPBT1 (MCU_BASE + 0x0C24U) +#define MCU_OPBT2 (MCU_BASE + 0x0C28U) +#define MCU_OPBT3 (MCU_BASE + 0x0C2CU) +#define MCU_OPBT4 (MCU_BASE + 0x0C30U) +#define MCU_OPBT6 (MCU_BASE + 0x0C38U) +#define MCU_OPBT7 (MCU_BASE + 0x0C3CU) +#define MCU_OPBT8 (MCU_BASE + 0x0C40U) +#define MCU_OPBT9 (MCU_BASE + 0x0C44U) +#define MCU_OPBT96 (MCU_BASE + 0x0CA0U) + +/* MCCR_SELB0 (0xD8F01000) */ +#define MCU_OPBT_STAT (MCU_BASE + 0x1000U) +#define MCU_OPBT_CTRL (MCU_BASE + 0x1004U) +#define MCU_G4MH_BOOT_CTLR (MCU_BASE + 0x1008U) +#define MCU_ICUMH_BOOT_CTLR (MCU_BASE + 0x100CU) +#define MCU_BOOT_STAT (MCU_BASE + 0x1024U) + +/* MCCR_SELB1 (0xD8F02000) */ + +/* HBG (0xD8F12000) */ +#define MCU_HBG_CS0_HBGPROT0 (MCU_BASE + 0x00012000U) +#define MCU_HBG_CS1_HBGPROT0 (MCU_BASE + 0x00012100U) +#define MCU_HBG_CS2_HBGPROT0 (MCU_BASE + 0x00012200U) +#define MCU_HBG_CS3_HBGPROT0 (MCU_BASE + 0x00012300U) +#define MCU_HBG_CS4_HBGPROT0 (MCU_BASE + 0x00012400U) +#define MCU_HBG_CS5_HBGPROT0 (MCU_BASE + 0x00012500U) +#define MCU_HBG_DS_HBGPROT0 (MCU_BASE + 0x00012600U) +#define MCU_HBG_PFS_HBGPROT0 (MCU_BASE + 0x00012700U) +#define MCU_HBG_SOCM_HBGPROT0 (MCU_BASE + 0x00012800U) +#define MCU_HBG_SOCS_HBGPROT0 (MCU_BASE + 0x00012900U) + +/* HBGSLVER (0xD8F19000) */ +#define MCU_HBGSLVER_CS0_HBGKCPROT (MCU_BASE + 0x00019018U) +#define MCU_HBGSLVER_CS1_HBGKCPROT (MCU_BASE + 0x00019118U) +#define MCU_HBGSLVER_CS2_HBGKCPROT (MCU_BASE + 0x00019218U) +#define MCU_HBGSLVER_CS3_HBGKCPROT (MCU_BASE + 0x00019318U) +#define MCU_HBGSLVER_CS4_HBGKCPROT (MCU_BASE + 0x00019418U) +#define MCU_HBGSLVER_CS5_HBGKCPROT (MCU_BASE + 0x00019518U) +#define MCU_HBGSLVER_DS_HBGKCPROT (MCU_BASE + 0x00019618U) +#define MCU_HBGSLVER_PFS_HBGKCPROT (MCU_BASE + 0x00019718U) +#define MCU_HBGSLVER_SOCM_HBGKCPROT (MCU_BASE + 0x00019818U) +#define MCU_HBGSLVER_SOCS_HBGKCPROT (MCU_BASE + 0x00019918U) + +/* PBG (0xD8F01800) */ +#define MCUAXI_PBG_PBGPROT0_0 (MCU_BASE + 0x1800U) +#define MCUAXI_PBG_PBGPROT0_1 (MCU_BASE + 0x1808U) +#define MCUAXI_PBG_PBGPROT0_2 (MCU_BASE + 0x1810U) +#define MCUAXI_PBG_PBGPROT0_3 (MCU_BASE + 0x1818U) +#define MCUAXI_PBG_PBGPROT0_4 (MCU_BASE + 0x1820U) +#define MCUAXI_PBG_PBGPROT0_5 (MCU_BASE + 0x1828U) +#define MCUAXI_PBG_PBGPROT0_6 (MCU_BASE + 0x1830U) +#define MCUAXI_PBG_ERRSLV_PBGKCPROT (MCU_BASE + 0x00018118U) + + +/* CSRM (0xD8F10000) */ +#define MCU_CSRM0ECCCTL (MCU_BASE + 0x00010000U) +#define MCU_CSRM1ECCCTL (MCU_BASE + 0x00010100U) +#define MCU_CSRM2ECCCTL (MCU_BASE + 0x00010200U) +#define MCU_CSRM3ECCCTL (MCU_BASE + 0x00010300U) +#define MCU_CSRM4ECCCTL (MCU_BASE + 0x00010400U) +#define MCU_CSRM5ECCCTL (MCU_BASE + 0x00010500U) +#define MCU_CSRM0APCTL (MCU_BASE + 0x00010050U) +#define MCU_CSRM1APCTL (MCU_BASE + 0x00010150U) +#define MCU_CSRM2APCTL (MCU_BASE + 0x00010250U) +#define MCU_CSRM3APCTL (MCU_BASE + 0x00010350U) +#define MCU_CSRM4APCTL (MCU_BASE + 0x00010450U) +#define MCU_CSRM5APCTL (MCU_BASE + 0x00010550U) +#define MCU_CSRM0CSIFCODE (MCU_BASE + 0x00010080U) +#define MCU_CSRM1CSIFCODE (MCU_BASE + 0x00010180U) +#define MCU_CSRM2CSIFCODE (MCU_BASE + 0x00010280U) +#define MCU_CSRM3CSIFCODE (MCU_BASE + 0x00010380U) +#define MCU_CSRM4CSIFCODE (MCU_BASE + 0x00010480U) +#define MCU_CSRM5CSIFCODE (MCU_BASE + 0x00010580U) + +#endif /* MCU_REGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/mem_io.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/mem_io.h new file mode 100644 index 0000000..1ab5cbd --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/mem_io.h @@ -0,0 +1,84 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Memory access driver header + ******************************************************************************/ +#ifndef MEM_IO_H_ +#define MEM_IO_H_ + +#include + +static inline void mem_write8(uintptr_t addr, uint8_t data) +{ + *(volatile uint8_t*)addr = data; +} + +static inline uint8_t mem_read8(uintptr_t addr) +{ + return (*(volatile uint8_t*)addr); +} + +static inline void mem_write16(uintptr_t addr, uint16_t data) +{ + *(volatile uint16_t*)addr = data; +} + +static inline uint16_t mem_read16(uintptr_t addr) +{ + return (*(volatile uint16_t*)addr); +} + +static inline void mem_write32(uintptr_t addr, uint32_t data) +{ + *(volatile uint32_t*)addr = data; +} + +static inline uint32_t mem_read32(uintptr_t addr) +{ + return (*(volatile uint32_t*)addr); +} + +static inline void mem_write64(uintptr_t addr, uint64_t data) +{ + *(volatile uint64_t*)addr = data; +} + +static inline uint64_t mem_read64(uintptr_t addr) +{ + return (*(volatile uint64_t*)addr); +} + +static inline void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set) +{ + mem_write32(addr, (mem_read32(addr) & ~clr) | set); +} + +#if defined(__RH850G3K__) +#define mmio_write_32(a,b) mem_write32(a,b) +#define mmio_read_32(a) mem_read32(a) +#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c) +#endif + + +#endif /* MEM_IO_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/mfis.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/mfis.h new file mode 100644 index 0000000..52ed336 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/mfis.h @@ -0,0 +1,39 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MFIS driver header + ******************************************************************************/ + +#ifndef MFIS_H__ +#define MFIS_H__ + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + +void mfis_init(void); +void mfis_lock(void); +void mfis_unlock(void); + +#endif /* MFIS_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/mfis_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/mfis_register.h new file mode 100644 index 0000000..cd93e2f --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/mfis_register.h @@ -0,0 +1,45 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MFIS register header + ******************************************************************************/ + +#ifndef MFIS_REGISTER_H__ +#define MFIS_REGISTER_H__ + +#include + +/* The Base is remapped in the IPL, and the address is calculated and accessed + * by adding the offset to the remapped address. */ +#define MFIS_BASE (BASE_MFIS_ADDR) + +#define MFISLCKR_ADDRESS (0x0800U) /* MFISLCKR[j] Address 0x724 +(4U*(63U-8U)) */ + +/* Register Definition */ +#define MFIS_LCKR (MFIS_BASE + MFISLCKR_ADDRESS) /* MFIS Lock Register */ +#define MFIS_WPCNTR (MFIS_BASE + 0x0900U) /* Write Protection Control Register */ +#define MFIS_WACNTR (MFIS_BASE + 0x0904U) /* Write Access Control Register */ + + +#endif /* MFIS_REGISTER_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/micro_wait.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/micro_wait.h new file mode 100644 index 0000000..a16a913 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/micro_wait.h @@ -0,0 +1,39 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Time wait driver header + ******************************************************************************/ + +#ifndef MICRO_WAIT_H_ +#define MICRO_WAIT_H_ + +#include + +/* Define */ + +/* Prototype */ +void micro_wait(uint32_t count_us); + + +#endif /* MICRO_WAIT_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/pfc.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/pfc.h new file mode 100644 index 0000000..4c5b970 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/pfc.h @@ -0,0 +1,41 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : PFC driver header + ******************************************************************************/ + +#ifndef PFC_H__ +#define PFC_H__ + +#include +#include +#include + +static inline void pfc_reg_write(uint32_t addr, uint32_t data) +{ + mem_write32(get_pmmr_addr(addr), ~data); + mem_write32(addr, data); +} + +#endif /* PFC_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/pfc_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/pfc_register.h new file mode 100644 index 0000000..2de5ef5 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/pfc_register.h @@ -0,0 +1,135 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : PFC register header + ******************************************************************************/ + + +#ifndef PFC_REGISTER_H__ +#define PFC_REGISTER_H__ + +#include +#include + +/* PFC / GPIO base address */ +/* 0xE6050000 */ +#define PFC_BASE (BASE_PFC_ADDR) + +#define PFC_RW_OFFSET (0x0000U) +#define PFC_SET_OFFSET (0x0200U) +#define PFC_CLR_OFFSET (0x0400U) + +#if (RCAR_LSI == RCAR_S4) +#define PFC_MCU_BASE (BASE_PFCMCU_ADDR) + +#define PFC_PORT_GRP0 (0x00000000U) /* Port Group0/4 */ +#define PFC_PORT_GRP1 (0x00000800U) /* Port Group1/5 */ +#define PFC_PORT_GRP2 (0x00001000U) /* Port Group2/6 */ +#define PFC_PORT_GRP3 (0x00001800U) /* Port Group3/7 */ +#define PFC_SYS_GRP (0x00028000U) /* System Group0/1 */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define PFC_PORT_GRP0 (0x00000000U) /* Port Group0 */ +#define PFC_PORT_GRP1 (0x00000800U) /* Port Group1 */ +#define PFC_PORT_GRP2 (0x00008000U) /* Port Group2 */ +#define PFC_PORT_GRP3 (0x00008800U) /* Port Group3 */ +#define PFC_PORT_GRP4 (0x00010000U) /* Port Group4 */ +#define PFC_PORT_GRP5 (0x00010800U) /* Port Group5 */ +#define PFC_PORT_GRP6 (0x00011000U) /* Port Group6 */ +#define PFC_PORT_GRP7 (0x00011800U) /* Port Group7 */ +#if (RCAR_LSI == RCAR_V4H) +#define PFC_PORT_GRP8 (0x00018000U) /* Port Group8 */ +#endif +#define PFC_SYS_GRP (0x00028000U) /* System Group0 */ +#endif + +/* PFC / GPIO registers */ +/* Read/Write registers */ +#define PFC_PORT_GRP_MASK (0xFFFFF800U) + +/* Port Group0 */ +#define PFC_DM1PR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x002CU) +#define PFC_GPSR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0040U) +#define PFC_IP0SR0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x0060U) +#define PFC_POC0_RW (PFC_BASE + PFC_PORT_GRP0 + PFC_RW_OFFSET + 0x00A0U) +/* Port Group1 */ +#define PFC_DM1PR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x002CU) +#define PFC_GPSR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0040U) +#define PFC_IP1SR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0064U) +#define PFC_IP2SR1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x0068U) +#define PFC_POC1_RW (PFC_BASE + PFC_PORT_GRP1 + PFC_RW_OFFSET + 0x00A0U) +/* Port Group2 */ +#define PFC_DM1PR2_RW (PFC_BASE + PFC_PORT_GRP2 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR2_RW (PFC_BASE + PFC_PORT_GRP2 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR2_RW (PFC_BASE + PFC_PORT_GRP2 + PFC_RW_OFFSET + 0x002CU) +/* Port Group3 */ +#define PFC_DM1PR3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x002CU) +#define PFC_POC3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x00A0U) +#define PFC_PUEN3_RW (PFC_BASE + PFC_PORT_GRP3 + PFC_RW_OFFSET + 0x00C0U) +/* Port Group4 */ +#define PFC_DM1PR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x002CU) +/* Physical address:0xE6060040, Logical address:0x0xFDA60040 */ +#define PFC_GPSR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0040U) +/* Physical address:0xE6060060, Logical address:0x0xFDA60060 */ +#define PFC_IP0SR4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0060U) +/* Physical address:0xE60600C0, Logical address:0x0xFDA600C0 */ +#define PFC_PUEN4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x00C0U) +/* Physical address:0xE6060100, Logical address:0x0xFDA60100 */ +#define PFC_MODSEL4_RW (PFC_BASE + PFC_PORT_GRP4 + PFC_RW_OFFSET + 0x0100U) +/* Port Group5 */ +#define PFC_DM1PR5_RW (PFC_BASE + PFC_PORT_GRP5 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR5_RW (PFC_BASE + PFC_PORT_GRP5 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR5_RW (PFC_BASE + PFC_PORT_GRP5 + PFC_RW_OFFSET + 0x002CU) +/* Port Group6 */ +#define PFC_DM1PR6_RW (PFC_BASE + PFC_PORT_GRP6 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR6_RW (PFC_BASE + PFC_PORT_GRP6 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR6_RW (PFC_BASE + PFC_PORT_GRP6 + PFC_RW_OFFSET + 0x002CU) +/* Port Group7 */ +#define PFC_DM1PR7_RW (PFC_BASE + PFC_PORT_GRP7 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR7_RW (PFC_BASE + PFC_PORT_GRP7 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR7_RW (PFC_BASE + PFC_PORT_GRP7 + PFC_RW_OFFSET + 0x002CU) +#if (RCAR_LSI == RCAR_V4H) +/* Port Group8 */ +#define PFC_DM1PR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PR8_RW (PFC_BASE + PFC_PORT_GRP8 + PFC_RW_OFFSET + 0x002CU) +#endif +/* System Group */ +#define PFC_DM1PRSYS_RW (PFC_BASE + PFC_SYS_GRP + PFC_RW_OFFSET + 0x0024U) +#define PFC_DM2PRSYS_RW (PFC_BASE + PFC_SYS_GRP + PFC_RW_OFFSET + 0x0028U) +#define PFC_DM3PRSYS_RW (PFC_BASE + PFC_SYS_GRP + PFC_RW_OFFSET + 0x002CU) + +static inline uint32_t get_pmmr_addr(uint32_t addr) +{ + return (addr & PFC_PORT_GRP_MASK); +} + +#endif /* PFC_REGISTER_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/qos.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/qos.h new file mode 100644 index 0000000..2992d65 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/qos.h @@ -0,0 +1,33 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : QoS driver header + ******************************************************************************/ + +#ifndef QOS_INIT_H_ +#define QOS_INIT_H_ + +extern void qos_init(void); + +#endif /* QOS_INIT_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/ram_def.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/ram_def.h new file mode 100644 index 0000000..a0cb3a4 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/ram_def.h @@ -0,0 +1,80 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : R-Car RAM header + ******************************************************************************/ + +#ifndef RAM_DEF_H_ +#define RAM_DEF_H_ + +#include "remap_register.h" + +/* DRAM address */ +#define DRAM_BASE (0x40000000U) +#define DRAM_SIZE (0x80000000U) +#define DRAM_END ((DRAM_BASE + DRAM_SIZE) - 1U) +#define SDRAM_40BIT_ADDR_TOP (0x0400000000ULL) +/* RT-SRAM */ +#define RTSRAM_BASE (0xEB200000U) +#define RTSRAM_SIZE ((1024U - 16U) * 1024U) /* 1MB - 16KB(stack size) */ +#define RTSRAM_END ((RTSRAM_BASE + RTSRAM_SIZE) - 1U) +/* RT-VRAM */ +#define RTVRAM_BASE (0xE2000000U) +#define RTVRAM_SIZE (1024U * 1024U) /* 1MB */ +#define RTVRAM_END ((RTVRAM_BASE + RTVRAM_SIZE) - 1U) +/* RT-VRAM extend mode */ +#define RTVRAM_VBUF_TOP (RTVRAM_BASE + RTVRAM_SIZE) /* 0xE2100000 */ +#define RTVRAM_VBUF_4M (4U) /* 4MB */ +#define RTVRAM_VBUF_8M (8U) /* 8MB */ +#define RTVRAM_VBUF_12M (12U) /* 12MB */ +#define RTVRAM_VBUF_16M (16U) /* 16MB */ +#define RTVRAM_VBUF_20M (20U) /* 20MB */ +#define RTVRAM_VBUF_24M (24U) /* 24MB */ +#define RTVRAM_VBUF_28M (28U) /* 28MB */ +#define RTVRAM_VBUF_SIZE ((RTVRAM_VBUF_28M - 1U) * 1024U * 1024U) /* 3MB to 27MB (The first 1MB is actual RAM.) */ +#define RTVRAM_VBUF_AREA_SIZE (4U * 1024U * 1024U) /* 4MB */ +#define RTVRAM_VBUF_END ((RTVRAM_VBUF_TOP + RTVRAM_VBUF_SIZE) - 1U) + +/* Code SRAM */ +#if (BOOT_MCU != 0U) +#define CODESRAM_BASE (0x10000000U) +#define CODESRAM_SIZE (6U * 1024U * 1024U) /* 6MB */ +#define CODESRAM_END ((CODESRAM_BASE + CODESRAM_SIZE) - 1U) +#endif /* (BOOT_MCU != 0U) */ + +/* System RAM */ +#define SYSRAM_BASE (0xE6300000U) +#define SYSRAM_SIZE (384U * 1024U) /* 384KB */ +#define SYSRAM_END ((SYSRAM_BASE + SYSRAM_SIZE) - 1U) + +/* Local RAM */ +#define LOCAL_RAM_BASE (0xFEDE0000U) +#define LOCAL_RAM_SIZE (0x00020000U) /* 128KB */ +#define LOCAL_RAM_END ((LOCAL_RAM_BASE + LOCAL_RAM_SIZE) - 1U) + +/* Data-SRAM */ +#define DATA_SRAM_BASE (0xDF200000U) + +#endif /* RAM_DEF_H_ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/ram_protection.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/ram_protection.h new file mode 100644 index 0000000..287e9d4 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/ram_protection.h @@ -0,0 +1,162 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RAM protection driver header + ******************************************************************************/ +#ifndef RAM_PROTECTION_H_ +#define RAM_PROTECTION_H_ + +#include +#include + +#define RTSRAM_AREA1_TOP (0xE0040000U) +#define RTSRAM_ADDR_END (0xE0100000U) +#if (RCAR_LSI == RCAR_S4) +#define RTSRAM_ADDR_OFFSET_MASK (0x000FF000U) +#else +#define RTSRAM_ADDR_OFFSET_MASK (0xFFFFF000U) +#endif +#define RTVRAM_AREA1_TOP (0xE2010000U) +#define RTVRAM_AREA2_TOP (0xE2100000U) +#define RTVRAM_ADDR_END (0xE3C00000U) +#define RTVRAM_ADDR_MASK (0xFFFFF000U) +#if (RCAR_LSI == RCAR_S4) +#define SYSTEM_RAM_ADDR_END (0xE6360000U) +#else /* (RCAR_LSI == RCAR_S4) */ +/* For V4H/V4M */ +#define SYSTEM_RAM_AREA1_TOP (0xE635E000U) +#define SYSTEM_RAM_AREA2_TOP (0xE6360000U) +#define SYSTEM_RAM_ADDR_END (0xE6400000U) +#endif /* (RCAR_LSI == RCAR_S4) */ +#define SYSTEM_RAM_ADDR_MASK (0xFFFFF000U) +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define DRAM_ADDR_AREA1 (0x0401C00000ULL) +#define DRAM_ADDR_AREA2 (0x0401D00000ULL) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define DRAM_ADDR_AREA3 (0x0406400000ULL) +#define DRAM_ADDR_AREA4 (0x0406440000ULL) +#define DRAM_ADDR_AREA5 (0x0407FC0000ULL) +#define DRAM_ADDR_AREA6 (0x0408000000ULL) +#define DRAM_ADDR_AREA7 (0x041DC00000ULL) +#define DRAM_ADDR_AREA8 (0x0420000000ULL) +#define DRAM_ADDR_AREA9 (0x0440000000ULL) +#define DRAM_ADDR_AREA10 (0x0460000000ULL) +#define DRAM_ADDR_AREA11 (0x0480000000ULL) +#define DRAM_ADDR_AREA12 (0x0500000000ULL) +#define DRAM_ADDR_AREA13 (0x0600000000ULL) +#else +#define DRAM_ADDR_AREA3 (0x0404100000ULL) +#define DRAM_ADDR_AREA4 (0x0406400000ULL) +#define DRAM_ADDR_AREA5 (0x0406440000ULL) +#define DRAM_ADDR_AREA6 (0x0407E00000ULL) +#define DRAM_ADDR_AREA7 (0x0407F00000ULL) +#define DRAM_ADDR_AREA8 (0x0407FC0000ULL) +#define DRAM_ADDR_AREA9 (0x0408000000ULL) +#define DRAM_ADDR_AREA10 (0x041DC00000ULL) +#define DRAM_ADDR_AREA11 (0x0420000000ULL) +#define DRAM_ADDR_AREA12 (0x0440000000ULL) +#define DRAM_ADDR_AREA13 (0x0460000000ULL) +#define DRAM_ADDR_AREA14 (0x0480000000ULL) +#define DRAM_ADDR_AREA15 (0x0500000000ULL) +#define DRAM_ADDR_AREA16 (0x0600000000ULL) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#else +#define DRAM_ADDR_AREA1 (0x0401C00000ULL) +#define DRAM_ADDR_AREA2 (0x0406400000ULL) +#define DRAM_ADDR_AREA3 (0x0406440000ULL) +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ +#define DRAM_ADDR_END (0x0700000000ULL) +#define SDRAM_ADDR_MASK (0x3FFFFF0000ULL) + +#define NOT_USED_VALUE (0x00000000U) + +/* For System RAM protection setting */ +#define REGIONID0_WRITE_PRIVILEGE (0x00000001U) /* bit0 */ + +/* RAM DIVISION AREA ID */ +/* RT-SRAM */ +#define RTSRAM_ICUMX_IPL_AREA (0U) /* 0xE0000000 -- 0xE003FFFF */ +#define RTSRAM_ICUMX_FW_AREA (1U) /* 0xE0040000 -- 0xE00FFFFF */ +/* RT-VRAM */ +#define RTVRAM_BLANK_AREA (0U) /* 0xE2000000 -- 0xE200FFFF */ +#define RTVRAM_EXTEND_CACHE_AREA (1U) /* 0xE2010000 -- 0xE20FFFFF */ +#define RTVRAM_RTOS_AREA (2U) /* 0xE2100000 -- 0xE3BFFFFF */ +/* System RAM */ +#define SYSTEM_RAM_CX_2ND_IPL (0U) /* 0xE6300000 -- 0xE635DFFF */ +#define SYSTEM_RAM_SHARED_MEM (1U) /* 0xE635E000 -- 0xE635FFFF */ +/* SDRAM */ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define RTVRAM_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */ +#define CR_FW_SHARED_AREA (1U) /* 0x04_01C00000 -- 0x04_01CFFFFF */ +#define SDRAM_BLANK_AREA (2U) /* OPTEE_DISABLE:0x04_01D00000 -- 0x04_063FFFFF + * OPTEE_ENABLE :0x04_01D00000 -- 0x04_040FFFFF */ +#define SDRAM_PROTECT_AREA (3U) /* OPTEE_DISABLE:0x04_06400000 -- 0x04_0643FFFF + * OPTEE_ENABLE :0x04_04100000 -- 0x04_0643FFFF */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define SDRAM_PUBLIC_AREA (4U) /* 0x04_06440000 -- 0x04_07FBFFFF */ +#define ICCOM_USED_AREA (5U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */ +#define LINUX_USED_AREA (6U) /* 0x04_08000000 -- 0x04_1DBFFFFF */ +#define CAAREA2_USED_AREA (7U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */ +#define CR52_USED_AREA (8U) /* 0x04_20000000 -- 0x04_3FFFFFFF */ +#define CAAREA3_USED_AREA (9U) /* 0x04_40000000 -- 0x04_5FFFFFFF */ +#define CAAREA2_USED_AREA2 (10U) /* 0x04_60000000 -- 0x04_7FFFFFFF */ +#define CAAREA1_USED_AREA (11U) /* 0x04_80000000 -- 0x04_FFFFFFFF */ +#else +#define SDRAM_PROTECT_AREA2 (4U) /* 0x04_06400000 -- 0x04_0643FFFF */ +#define SDRAM_BLANK_AREA2 (5U) /* 0x04_06440000 -- 0x04_07DFFFFF */ +#define OPTEE_SHARED_AREA (6U) /* 0x04_07E00000 -- 0x04_07EFFFFF */ +#define SDRAM_BLANK_AREA3 (7U) /* 0x04_07F00000 -- 0x04_07FBFFFF */ +#define ICCOM_USED_AREA (8U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */ +#define LINUX_USED_AREA (9U) /* 0x04_08000000 -- 0x04_1DBFFFFF */ +#define CAAREA2_USED_AREA (10U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */ +#define CR52_USED_AREA (11U) /* 0x04_20000000 -- 0x04_3FFFFFFF */ +#define CAAREA3_USED_AREA (12U) /* 0x04_40000000 -- 0x04_5FFFFFFF */ +#define CAAREA2_USED_AREA2 (13U) /* 0x04_60000000 -- 0x04_7FFFFFFF */ +#define CAAREA1_USED_AREA (14U) /* 0x04_80000000 -- 0x04_FFFFFFFF */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#if (RCAR_LSI == RCAR_V4H) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define RESERVERD_AREA (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define CAAREA1_USED_AREA2 (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#else +#define RESERVERD_AREA (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define CAAREA1_USED_AREA2 (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#elif (RCAR_LSI == RCAR_V4M) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define CAAREA1_USED_AREA2 (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define RESERVERD_AREA (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#else +#define CAAREA1_USED_AREA2 (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define RESERVERD_AREA (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#endif /* RCAR_LSI == RCAR_V4H */ +#else +#define RTVRAM_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */ +#define SDRAM_BLANK_AREA (1U) /* 0x04_01C00000 -- 0x04_063FFFFF */ +#define SDRAM_PROTECT_AREA (2U) /* 0x04_06400000 -- 0x04_0643FFFF */ +#define SDRAM_PUBLIC_AREA (3U) /* 0x04_06440000 -- 0x06_FFFFFFFF */ +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +#endif /* RAM_PROTECTION_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rcar_def.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rcar_def.h new file mode 100644 index 0000000..ada224c --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rcar_def.h @@ -0,0 +1,51 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : R-Car common header + ******************************************************************************/ + +#ifndef RCAR_DEF_H_ +#define RCAR_DEF_H_ + +#include "remap_register.h" + +/* Product Register */ +#define PRR (0xFFF00044U) /* PRR register */ +#define PRR_CA_CL3_STATE_MASK (0x80000000U) /* Cortex-A Cluster 3 State */ +#define PRR_PRODUCT_MASK (0x00007F00U) /* Product mask */ +#define PRR_CUT_MASK (0x000000FFU) /* Cut Number bit mask */ +#define PRR_MAJOR_MASK (0x000000F0U) /* Major bit mask */ +#define PRR_MINOR_MASK (0x0000000FU) /* Minor bit mask */ +#define PRR_MAJOR_SHIFT (4U) /* Major bit shift */ +#define PRR_MAJOR_OFFSET (1U) + +#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */ +#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */ +#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */ + +#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */ +#define PRR_PRODUCT_11 (0x00000001U) /* ver 1.1 */ +#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */ +#endif /* RCAR_DEF_H_ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/remap.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/remap.h new file mode 100644 index 0000000..03fb5e6 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/remap.h @@ -0,0 +1,48 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : remap driver header + ******************************************************************************/ +#ifndef REMAP_H_ +#define REMAP_H_ + +#define ICUMX_CTLREG_BASE (0xFFFEE200U) +#define ICUMX_CFREMAP (ICUMX_CTLREG_BASE + 0x4CU) +#define CFREMAP_AREA_SIZE (0x02000000U) + +#include + +typedef struct{ + uint32_t base_addr; /* Base address of Region ID registers. */ + uint32_t rmp_addr; /* Stores the address converted from the Region ID base address to SICREMAP address. */ +} REMAP_TABLE; + +uint32_t remap_get_phys_addr(uint32_t remap_addr); +uint32_t get_cfremap_addr(uint32_t fetch_addr); +uint32_t remap_get_remap_addr(uint32_t phys_addr); +void remap_register(uint32_t addr, uint32_t *remap_addr); +void remap_unregister(uint32_t remap_addr); +void set_sicremap_s4v10(void); +void set_sicremap_fcpr(void); +#endif /* REMAP_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/remap_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/remap_register.h new file mode 100644 index 0000000..55eead2 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/remap_register.h @@ -0,0 +1,273 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : remap register header + ******************************************************************************/ + +#ifndef REMAP_REGISTER_H_ +#define REMAP_REGISTER_H_ + +#include + +#define REMAP_BASE (0xFF1FC400U) + +#define ICUMX_PROT0PCMD (0xFFFEE090U) +#define ICUMX_PROT0PS (0xFFFEE094U) +#define PROTCMD_START (0xA5U) +#define PROTS0ERR (0x01U) + +#define ICU_REMAP0 (0xFC000000U) + +/* REMAP setting */ +/* Remap ID(0 -- 15) */ +#define ICU_REMAP_NUM_RTRAM (15U) /* RTRAM */ +#define ICU_REMAP_NUM_CC (14U) /* CC63S,AXMM,QoS for S4 / V4H */ +#define ICU_REMAP_NUM_FCPR (14U) /* FCPR for V4M */ +#define ICU_REMAP_NUM_PFC (13U) /* PFC,GPIO,CPGA,RESET */ +#define ICU_REMAP_NUM_ECM (12U) /* ECM,AP-System Core */ +#define ICU_REMAP_NUM_RPC (11U) /* RPC */ +#define ICU_REMAP_NUM_RTDMAC (10U) /* RT-DMAC0,PFC(MCU) */ +#define ICU_REMAP_NUM_SCIF (9U) /* SCIF */ +#define ICU_REMAP_NUM_MMC (8U) /* MMC */ +#define ICU_REMAP_NUM_HSCIF (7U) /* HSCIF */ +#define ICU_REMAP_NUM_DMAC (6U) /* SYS-DMAC0 */ +#define ICU_REMAP_NUM_RGID (5U) /* Region ID */ +#if (RCAR_LSI == RCAR_S4) +#define ICU_REMAP_NUM_MCU (4U) /* MCU */ +#endif + +/* SICREMAP2M15 */ +#define ICU_REMAP_RTSRAM (0xEB200000U) /* RT-SRAM */ +/* SICREMAP2M14 */ +#define ICU_REMAP_CC (0xE6600000U) /* CC63S,AXMM,QoS,FCPR for S4 / V4H */ +/* SICREMAP2M14 */ +#define ICU_REMAP_FCPR (0xE6600000U) /* FCPR for V4M */ +/* SICREMAP2M13 */ +#define ICU_REMAP_PFC (0xE6000000U) /* PFC,GPIO,CPGA,RESET */ +/* SICREMAP2M12 */ +#define ICU_REMAP_ECM (0xE6200000U) /* ECM,AP-System Core */ +/* SICREMAP2M11 */ +#define ICU_REMAP_RPC (0xEE200000U) /* RPC */ +/* SICREMAP2M10 */ +#define ICU_REMAP_RTDMAC (0xFFC00000U) /* RT-DMAC0,PFC(MCU) */ +/* SICREMAP2M9 */ +#if (RCAR_LSI == RCAR_S4) +#define ICU_REMAP_SCIF (0xE6C00000U) /* SCIF3 */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define ICU_REMAP_SCIF (0xE6E00000U) /* SCIF0 */ +#endif /* RCAR_LSI == RCAR_S4 */ +/* SICREMAP2M8 */ +#define ICU_REMAP_MMC (0xEE000000U) /* MMC */ +/* SICREMAP2M7 */ +#define ICU_REMAP_HSCIF (0xE6400000U) /* HSCIF */ +/* SICREMAP2M6 */ +#define ICU_REMAP_DMAC (0xE7200000U) /* SYS-DMAC0 */ +/* SICREMAP2M5 */ +#define ICU_REMAP_RGID (0xE7600000U) /* Region ID */ +#if (RCAR_LSI == RCAR_S4) +/* SICREMAP2M4 */ +#define ICU_REMAP_MCU (0xD8E00000U) /* MCU */ +#endif + +#define ICU_REMAP15_BASE (ICU_REMAP_RTRAM) /* RTRAM */ +#define ICU_REMAP14_BASE (ICU_REMAP_CC) /* CC63S,AXMM,QoS,FCPR */ +#define ICU_REMAP13_BASE (ICU_REMAP_PFC) /* PFC,GPIO,CPGA,RESET */ +#define ICU_REMAP12_BASE (ICU_REMAP_ECM) /* ECM,AP-System Core */ +#define ICU_REMAP11_BASE (ICU_REMAP_RPC) /* RPC */ +#define ICU_REMAP10_BASE (ICU_REMAP_RTDMAC) /* RT-DMAC0 */ +#define ICU_REMAP9_BASE (ICU_REMAP_SCIF) /* SCIF */ +#define ICU_REMAP8_BASE (ICU_REMAP_MMC) /* MMC */ +#define ICU_REMAP7_BASE (ICU_REMAP_HSCIF) /* HSCIF */ +#define ICU_REMAP6_BASE (ICU_REMAP_DMAC) /* SYS-DMAC0 */ +#define ICU_REMAP5_BASE (ICU_REMAP_RGID) /* Region ID */ +#if (RCAR_LSI == RCAR_S4) +#define ICU_REMAP4_BASE (ICU_REMAP_MCU) /* MCU */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define ICU_REMAP4_BASE (0x00000000U) /* Reserved */ +#endif +#define ICU_REMAP3_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP2_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP1_BASE (0x00000000U) /* Reserved */ +#define ICU_REMAP0_BASE (0x00000000U) /* Reserved */ + +/* Base address offset of each register after remap */ +/* REMAP15(0xEB200000U) */ +/* RT-SRAM */ +#define ICU_REMAP_OFFSET_RTSRAM (0x00000000U) + +/* REMAP14(0xE6600000U) */ +#define ICU_REMAP_OFFSET_CC63S (0x00000000U) +#define ICU_REMAP_OFFSET_DBSC (0x00190000U) /* (0xE6790000U) */ +#define ICU_REMAP_OFFSET_AXMM (0x00180000U) /* (0xE6780000U) */ +#if (RCAR_LSI == RCAR_S4) +#define ICU_REMAP_OFFSET_CCI (0x001a0000U) /* (0xE67A0000U) */ +#define ICU_REMAP_OFFSET_QOS (0x001e0000U) /* (0xE67E0000U) */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define ICU_REMAP_OFFSET_FCPR (0x00185700U) /* (0xE6785700U) */ + #if (RCAR_LSI == RCAR_V4M) + #define ICU_REMAP_OFFSET_I2C3 (0x000D0000U) /* (0xE66D0000U) */ + #endif /* (RCAR_LSI == RCAR_V4M) */ +#endif /* (RCAR_LSI == RCAR_S4) */ + +/* REMAP13(0xE6000000U) */ +/* PFC */ +#define ICU_REMAP_OFFSET_PFC (0x00050000U) +/* EFUSE */ +#define ICU_REMAP_OFFSET_EFUSE (0x00078800U) +/* CPGA */ +#define ICU_REMAP_OFFSET_CPGA (0x00150000U) +/* RESET */ +#define ICU_REMAP_OFFSET_RESET (0x00160000U) +/* APMU */ +#define ICU_REMAP_OFFSET_APMU (0x00170000U) +/* SYSC */ +#define ICU_REMAP_OFFSET_SYSC (0x00180000U) +/* OTP */ +#define ICU_REMAP_OFFSET_OTP (0x001BF000U) +#if (RCAR_LSI == RCAR_V4M) +#define ICU_REMAP_OFFSET_AVS (0x000A0000U) /* (0xE60A0000U) */ +#endif /* (RCAR_LSI == RCAR_V4M) */ + +/* REMAP12(0xE6200000U) */ +/* ECM */ +#define ICU_REMAP_OFFSET_MFIS (0x00060000U) +#define ICU_REMAP_OFFSET_SDRAM_ECC (0x00050000U) +#define ICU_REMAP_OFFSET_AP_CORE (0x00080000U) + +/* REMAP11(0xEE200000U) */ +/*RPC*/ +#define ICU_REMAP_OFFSET_RPC (0x00000000U) + +/* REMAP10(0xFFC00000U) */ +/* RT-DMA */ +#define ICU_REMAP_OFFSET_RTDMA0 (0x00010000U) +#define ICU_REMAP_OFFSET_RTDMACTL (0x00160000U) +#define ICU_REMAP_OFFSET_PFCMCU (0x00190000U) + +#if (RCAR_LSI == RCAR_S4) +/* REMAP9(0xE6C00000U) */ +/*SCIF*/ +#define ICU_REMAP_OFFSET_SCIF3 (0x00050000U) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +/* REMAP9(0xE6E00000U) */ +/*SCIF*/ +#define ICU_REMAP_OFFSET_SCIF0 (0x00060000U) +#endif /* RCAR_LSI == RCAR_S4 */ + +/* REMAP8(0xEE000000U) */ +/* SDHI2/MMC0 */ +#define ICU_REMAP_OFFSET_SDHI (0x00140000U) + +/* REMAP7(0xE6400000U) */ +/* HSCIF */ +#define ICU_REMAP_OFFSET_HSCIF0 (0x00140000U) + +/* REMAP6(0xE7200000U) */ +/* SYS-DMAC */ +#define ICU_REMAP_OFFSET_SYSDMAC (0x00100000U) + +/* REMAP5(0xE7600000U) */ +/* Region ID */ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define ICU_REMAP_OFFSET_ICISTP (0x00100000U) +#endif +#define ICU_REMAP_OFFSET_RGID (0x00150000U) + +#if (RCAR_LSI == RCAR_S4) +/* REMAP4(0xD8E00000U) */ +/* MCU */ +#define ICU_REMAP_OFFSET_MCU (0x00100000U) +#endif + +/* REMAP15(0xEB200000U) */ +#define BASE_RTSRAM_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTRAM) + ICU_REMAP_OFFSET_RTSRAM) +/* REMAP14(0xE6600000U) */ +#define BASE_DBSC_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_DBSC) +#define BASE_AXMM_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_AXMM) +#if (RCAR_LSI == RCAR_S4) +#define BASE_CCI_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_CCI) +#define BASE_QOS_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_QOS) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define BASE_FCPR_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_FCPR) + #if (RCAR_LSI == RCAR_V4M) + #define BASE_I2C3_ADDR (icu_remap_calc(ICU_REMAP_NUM_CC) + ICU_REMAP_OFFSET_I2C3) + #endif /* (RCAR_LSI == RCAR_V4M) */ +#endif /* (RCAR_LSI == RCAR_S4) */ +/* REMAP13(0xE6000000U) */ +#define BASE_EFUSE_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_EFUSE) +#define BASE_PFC_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_PFC) +#define BASE_CPG_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_CPGA) +#define BASE_RESET_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_RESET) +#define BASE_APMU_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_APMU) +#define BASE_SYSC_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_SYSC) +#define BASE_OTP_MEM_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_OTP) +#if (RCAR_LSI == RCAR_V4M) +#define BASE_AVS_ADDR (icu_remap_calc(ICU_REMAP_NUM_PFC) + ICU_REMAP_OFFSET_AVS) +#endif /* (RCAR_LSI == RCAR_V4M) */ +/* REMAP12(0xE6200000U) */ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define BASE_ECM_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM)) +#endif +#define BASE_MFIS_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_MFIS) +#define BASE_ECC_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_SDRAM_ECC) +#define BASE_AP_CORE_ADDR (icu_remap_calc(ICU_REMAP_NUM_ECM) + ICU_REMAP_OFFSET_AP_CORE) +/* REMAP11(0xEE200000U) */ +#define BASE_RPC_ADDR (icu_remap_calc(ICU_REMAP_NUM_RPC) + ICU_REMAP_OFFSET_RPC) +/* REMAP10(0xFFC00000U) */ +#define BASE_RTDMA0_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMA0) +#define BASE_RTDMACTL_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_RTDMACTL) +#if (RCAR_LSI == RCAR_S4) +#define BASE_PFCMCU_ADDR (icu_remap_calc(ICU_REMAP_NUM_RTDMAC) + ICU_REMAP_OFFSET_PFCMCU) +#endif +#if (RCAR_LSI == RCAR_S4) +/* REMAP9(0xE6C00000U) */ +#define BASE_SCIF_ADDR (icu_remap_calc(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF3) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +/* REMAP9(0xE6E00000U) */ +#define BASE_SCIF_ADDR (icu_remap_calc(ICU_REMAP_NUM_SCIF) + ICU_REMAP_OFFSET_SCIF0) +#endif /* RCAR_LSI == RCAR_S4 */ +/* REMAP8(0xEE000000U) */ +#define BASE_MMC0_ADDR (icu_remap_calc(ICU_REMAP_NUM_MMC) + ICU_REMAP_OFFSET_SDHI) +/* REMAP7(0xE6400000U) */ +#define BASE_HSCIF_ADDR (icu_remap_calc(ICU_REMAP_NUM_HSCIF) + ICU_REMAP_OFFSET_HSCIF0) +/* REMAP6(0xE7200000U) */ +#define BASE_DMA_ADDR (icu_remap_calc(ICU_REMAP_NUM_DMAC) + ICU_REMAP_OFFSET_SYSDMAC) +/* REMAP5(0xE7600000U) */ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define BASE_ICISTP_ADDR (icu_remap_calc(ICU_REMAP_NUM_RGID) + ICU_REMAP_OFFSET_ICISTP) +#endif +#define BASE_RGID_ADDR (icu_remap_calc(ICU_REMAP_NUM_RGID) + ICU_REMAP_OFFSET_RGID) +#if (RCAR_LSI == RCAR_S4) +/* REMAP4(0xD8E00000U) */ +#define BASE_MCU_ADDR (icu_remap_calc(ICU_REMAP_NUM_MCU) + ICU_REMAP_OFFSET_MCU) +#endif + +/* Calculate the base address of each register after remapping */ +static inline uint32_t icu_remap_calc(uint32_t num) +{ + return (ICU_REMAP0 + (num * 0x00200000U)); +} +/* End of function icu_remap_calc(uint32_t num) */ + +#endif /* REMAP_REGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rom_api.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rom_api.h new file mode 100644 index 0000000..b87365e --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rom_api.h @@ -0,0 +1,73 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : boot ROM API header + ******************************************************************************/ +#ifndef ROM_API_H__ +#define ROM_API_H__ + +#include +#include + +#define SECURE_BOOT (0x0U) +#define NORMAL_BOOT (0x211883DFU) + +#define ROMAPI_OK (0x00000000U) +#define ROM_ERR_IMG_VERIFIER_NO_ENCRYPT_IMG (0xF100001DU) + +#define LCS_CM (0x00000000U) /* CM */ +#define LCS_DM (0x00000001U) /* DM */ +#define LCS_SD (0x00000003U) /* SD */ +#define LCS_SE (0x00000005U) /* SE */ +#define LCS_FA (0x00000007U) /* FA */ + +/* BOOTROM API address */ +#define ROM_GETLCS (0x01104418U) +#define ROM_SECUREBOOT_VERIFY (0x011044C8U) +#define ROM_SECUREBOOT_DECRYPT (0x011044D0U) +#define ROM_SECUREBOOT_COMPARE (0x011044D8U) + +/* For build option SW_VERSION_CHECK */ +#define OPT_VERSION_CHECK_ENABLE (1U) + +typedef uint32_t (*ROM_SECUREBOOT_VERIFY_API)(uint32_t *pKeyCert, uint32_t *pContentCert); +typedef uint32_t (*ROM_SECUREBOOT_DECRYPT_API)(uint32_t *pContentCert); +typedef uint32_t (*ROM_SECUREBOOT_COMPARE_API)(uint32_t *pContentCert, + uint32_t *hash, + uint32_t hash_size); +typedef uint32_t (*ROM_GETLCS_API)(uint32_t *pLcs, uint32_t lcs_size); + +static inline uint32_t get_load_info_id(const LOAD_INFO *li) +{ + return ((li->cnt_cert_addr - (SA9_DEST_ADDR + CONTENT_CERT_OFFSET)) / CONTENT_CERT_SIZE); +} +/* End of function get_load_info_id(LOAD_INFO *li) */ + +void rom_secureboot(LOAD_INFO* li); +uint32_t call_ROM_GetLcs(uint32_t *pLcs, uint32_t lcs_size); +void sw_version_check(const LOAD_INFO* li); +void auth_min_ver_tbl(LOAD_INFO* li); +void preload_verify_cntcert(const LOAD_INFO* li); + +#endif /* ROM_API_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rpc.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rpc.h new file mode 100644 index 0000000..6ff29b9 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rpc.h @@ -0,0 +1,87 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RPC driver header + ******************************************************************************/ + +#ifndef RPC_H__ +#define RPC_H__ + +#include +#include + +/* If user customizes for another vendor's QSPI Flash, set to 1. */ +#define USER_ADDED_QSPI (0U) /* 0:Disable 1:Enable */ + +/* The number of Flash vendor */ +#if USER_ADDED_QSPI == 0 +#define VENDOR_NUM (1U) +#endif /* USER_ADDED_QSPI == 0 */ +/* Command for S25FS512S */ +#define S25FS512S_READ_32BIT_ADDR (0x13U) /* read 32bit address */ +#define S25FS512S_DDR_QUAD_IO_READ_32BIT_ADDR (0xEEU) /* DDR quad I/O read 32bit address */ + +#if USER_ADDED_QSPI == 1 +/* User can customize for another vendor's QSPI Flash. */ +#define VENDOR_NUM (2U) +/* Command for XXXXXXXXX */ +#define XXXXXXXXX_READ_32BIT_ADDR (0x00U) /* read 32bit address */ +#define XXXXXXXXX_DDR_QUAD_IO_READ_32BIT_ADDR (0x00U) /* DDR quad I/O read 32bit address */ +#endif /* USER_ADDED_QSPI == 1 */ + + +typedef struct { + uint32_t read_32bit_addr; + uint32_t ddr_quad_io_read_32bit_addr; +} st_qspi_cmd_tbl_t; + +static const st_qspi_cmd_tbl_t qspi_cmd_tbls[VENDOR_NUM] = +{ + /* Command table for S25FS512S */ + { + S25FS512S_READ_32BIT_ADDR, /* read 32bit address */ + S25FS512S_DDR_QUAD_IO_READ_32BIT_ADDR /* DDR quad I/O read 32bit address */ + }, +#if USER_ADDED_QSPI == 1 + /* Command table for XXXXXXXXX */ + /* User can customize for another vendor's QSPI Flash. */ + { + XXXXXXXXX_READ_32BIT_ADDR, /* read 32bit address */ + XXXXXXXXX_DDR_QUAD_IO_READ_32BIT_ADDR /* DDR quad I/O read 32bit address */ + } +#endif /* USER_ADDED_QSPI == 1 */ +}; + + +void rpc_init(void); +void rpc_release(void); +void rpc_end_state_check(void); + +#if (QSPI_DDR_MODE==1) +void qspi_ddr_transfer_mode(uint32_t command); +#else +void qspi_sdr_transfer_mode(uint32_t command); +#endif + +#endif /* RPC_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rpc_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rpc_register.h new file mode 100644 index 0000000..42e85cb --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rpc_register.h @@ -0,0 +1,54 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RPC register header + ******************************************************************************/ + +#ifndef RPC_REGISTER_H_ +#define RPC_REGISTER_H_ + + +#include + +/* RPC base address */ +/* 0xEE200000 */ +#define RPC_BASE (BASE_RPC_ADDR) + +#define RPC_CMNCR (RPC_BASE + 0x0000U) /* Common control register */ +#define RPC_DRCR (RPC_BASE + 0x000CU) /* Data read control register */ +#define RPC_DRCMR (RPC_BASE + 0x0010U) /* Data read command setting register */ +#define RPC_DREAR (RPC_BASE + 0x0014U) /* Data read extended address register */ +#define RPC_DRENR (RPC_BASE + 0x001CU) /* Data read enable setting register */ +#define RPC_SMCR (RPC_BASE + 0x0020U) /* Manual mode control register */ +#define RPC_SMCMR (RPC_BASE + 0x0024U) /* Manual mode command setting register */ +#define RPC_SMENR (RPC_BASE + 0x0030U) /* Manual mode enable setting register */ +#define RPC_SMRDR0 (RPC_BASE + 0x0038U) /* Manual mode read data register 0 */ +#define RPC_CMNSR (RPC_BASE + 0x0048U) /* Common status register */ +#define RPC_DRDMCR (RPC_BASE + 0x0058U) /* Data read Dummy Cycle setting register */ +#define RPC_DRDRENR (RPC_BASE + 0x005CU) /* Data read DDR enable register */ +#define RPC_SMDRENR (RPC_BASE + 0x0064U) /* Manual mode DDR enable register */ +#define RPC_PHYCNT (RPC_BASE + 0x007CU) /* PHY control register */ +#define RPC_PHYOFFSET1 (RPC_BASE + 0x0080U) /* PHY Timing Offset Register 1 */ + +#endif /* RPC_REGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rst_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rst_register.h new file mode 100644 index 0000000..e644421 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rst_register.h @@ -0,0 +1,53 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RST register header + ******************************************************************************/ + +#ifndef RST_REGISTER_H_ +#define RST_REGISTER_H_ + +#include + +#define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */ + +#define RST_MODEMR0 (RST_BASE + 0x0000U) /* Mode pin register0 */ +#define RST_MODEMR1 (RST_BASE + 0x0004U) /* Mode pin register1 */ +#define RST_MODEMR0_MD31 (1U << 31U) +#define RST_MODEMR1_MD32 (1U << 0U) + +#define RST_MODEMR0_BOOT_DEV_MASK (0x0000001EU) +#define RST_MODEMR0_BOOT_DEV_HYPERFLASH160 (0x00000004U) +#define RST_MODEMR0_BOOT_DEV_HYPERFLASH80 (0x00000006U) +#define RST_MODEMR0_BOOT_DEV_QSPI_FLASH40 (0x00000008U) +#define RST_MODEMR0_BOOT_DEV_EMMC_50X8 (0x0000001AU) +#define RST_WDTRSTCR (RST_BASE + 0x0010U) + +/* SCIF / HSCIF clock speed */ +#define MODEMR_SCIF_DLMODE (0x00000000U) +#define MODEMR_HSCIF_DLMODE_921600 (0x00000001U) +#define MODEMR_HSCIF_DLMODE_1843200 (0x00000002U) +#define MODEMR_HSCIF_DLMODE_3000000 (0x00000003U) + +#endif /* RST_REGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rtsram_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rtsram_register.h new file mode 100644 index 0000000..5dc6825 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rtsram_register.h @@ -0,0 +1,65 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-SRAM register header + ******************************************************************************/ + +#ifndef RTSRAM_REGISTER_H__ +#define RTSRAM_REGISTER_H__ + +#include + +/* RT-SRAM register base address */ +#define RTSRAM_REG_BASE (0xFFE90000U) + +#define RTSRAM_SECDIVD (RTSRAM_REG_BASE + 0x0000U) +#define RTSRAM_SECCTRRD (RTSRAM_REG_BASE + 0x0040U) +#define RTSRAM_SECCTRWD (RTSRAM_REG_BASE + 0x0340U) + +#if (RCAR_LSI == RCAR_S4) +#define RTSRAM_SECDIVD_DIVADDR_MASK (0x000000FFU) +#else +#define RTSRAM_SECDIVD_DIVADDR_MASK (0x000FFFFFU) +#endif +#define RTSRAM_SECCTRRD_SECGRP_MASK (0x000F0000U) +#define RTSRAM_SECCTRRD_SAFGRP_MASK (0x0000FFFFU) +#define RTSRAM_SECCTRWD_SECGRP_MASK (0x000F0000U) +#define RTSRAM_SECCTRWD_SAFGRP_MASK (0x0000FFFFU) + +static inline uint32_t get_rtsram_secdivd_addr(uint32_t num) +{ + return ((RTSRAM_SECDIVD + (num * 4U))); +} + +static inline uint32_t get_rtsram_secctrrd_addr(uint32_t num) +{ + return ((RTSRAM_SECCTRRD + (num * 4U))); +} + +static inline uint32_t get_rtsram_secctrwd_addr(uint32_t num) +{ + return ((RTSRAM_SECCTRWD + (num * 4U))); +} + +#endif /* RTSRAM_REGISTER_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rtvram.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rtvram.h new file mode 100644 index 0000000..1ee2ecc --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rtvram.h @@ -0,0 +1,35 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-VRAM driver header + ******************************************************************************/ + +#ifndef RTVRAM_H_ +#define RTVRAM_H_ + +#include + +void rtvram_extendmode(void); + +#endif /* RTVRAM_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rtvram_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rtvram_register.h new file mode 100644 index 0000000..42d4a68 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/rtvram_register.h @@ -0,0 +1,70 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-VRAM register header + ******************************************************************************/ + +#ifndef RTVRAM_REGISTER_H__ +#define RTVRAM_REGISTER_H__ + +#include + +/* RT-VRAM register base address */ +#define RTVRAM_REG_BASE (0xFFEC0000U) + +#define RTVRAM_SECDIVD (RTVRAM_REG_BASE + 0x0000U) +#define RTVRAM_SECCTRRD (RTVRAM_REG_BASE + 0x0040U) +#define RTVRAM_SECCTRWD (RTVRAM_REG_BASE + 0x0340U) +#define RTVRAM_EXT_MODE (RTVRAM_REG_BASE + 0x8500U) +#define RTVRAM_VBUF_CFG (RTVRAM_REG_BASE + 0x6504U) +#define RTVRAM_CACHE_FLUSH (RTVRAM_REG_BASE + 0x4530U) +#define RTVRAM_VBUF_BADDR (RTVRAM_REG_BASE + 0xC580U) + +#define RTVRAM_SECDIVD_DIVADDR_MASK (0x000FFFFFU) +#define RTVRAM_SECCTRRD_SECGRP_MASK (0x000F0000U) +#define RTVRAM_SECCTRRD_SAFGRP_MASK (0x0000FFFFU) +#define RTVRAM_SECCTRWD_SECGRP_MASK (0x000F0000U) +#define RTVRAM_SECCTRWD_SAFGRP_MASK (0x0000FFFFU) + +static inline uint32_t get_rtvram_secdivd_addr(uint32_t num) +{ + return ((RTVRAM_SECDIVD + (num * 4U))); +} + +static inline uint32_t get_rtvram_secctrrd_addr(uint32_t num) +{ + return ((RTVRAM_SECCTRRD + (num * 4U))); +} + +static inline uint32_t get_rtvram_secctrwd_addr(uint32_t num) +{ + return ((RTVRAM_SECCTRWD + (num * 4U))); +} + +static inline uint32_t get_vbuf_baddr_addr(uint32_t num) +{ + return ((RTVRAM_VBUF_BADDR + (num * 4U))); +} + +#endif /* RTVRAM_REGISTER_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/scif.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/scif.h new file mode 100644 index 0000000..9aae4e9 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/scif.h @@ -0,0 +1,38 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : SCIF driver header + ******************************************************************************/ + +#ifndef SCIF_H_ +#define SCIF_H_ + +#include +#include + +/* Prototype */ +void scif_init(void); +void console_putc(uint8_t outchar); + +#endif /* SCIF_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/scif_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/scif_register.h new file mode 100644 index 0000000..f3278c6 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/scif_register.h @@ -0,0 +1,47 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : SCIF register header + ******************************************************************************/ + + +#ifndef SCIF_REGISTER_H_ +#define SCIF_REGISTER_H_ + +#include + +/* SCIF base address */ +/* S4:0xE6C50000(CH3), V4H:0xE6E60000(CH0) */ +#define SCIF_BASE (BASE_SCIF_ADDR) + +#define SCIF_SCSMR (SCIF_BASE + 0x0000U) /* 16 Serial mode register */ +#define SCIF_SCBRR (SCIF_BASE + 0x0004U) /* 8 Bit rate register */ +#define SCIF_SCSCR (SCIF_BASE + 0x0008U) /* 16 Serial control register */ +#define SCIF_SCFTDR (SCIF_BASE + 0x000CU) /* 8 Transmit FIFO data register */ +#define SCIF_SCFSR (SCIF_BASE + 0x0010U) /* 16 Serial status register */ +#define SCIF_SCFCR (SCIF_BASE + 0x0018U) /* 16 FIFO control register */ +#define SCIF_SCLSR (SCIF_BASE + 0x0024U) /* 16 Line status register */ +#define SCIF_CKS (SCIF_BASE + 0x0034U) /* 16 Clock Select register */ + +#endif /* SCIF_REGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/sysc.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/sysc.h new file mode 100644 index 0000000..4dcbd04 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/sysc.h @@ -0,0 +1,71 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : sysc header + ******************************************************************************/ +/****************************************************************************** + * @file sysc.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.09.2023 0.01 First Release + * : 08.01.2025 0.02 Add write protection register definition. + *****************************************************************************/ +#ifndef SYSC_H_ +#define SYSC_H_ + +#include +#include + +#define BASE_SYSC (BASE_SYSC_ADDR) /* SYSC logical address 0xFDB80000 */ + /* SYSC physical address 0xE6180000 */ +#if (RCAR_LSI == RCAR_V4M) +#define SYSC_SYSCSR (BASE_SYSC + 0x0000U) +#define SYSC_SYSCISCR0 (BASE_SYSC + 0x0810U) +#define SYSC_SYSCIER0 (BASE_SYSC + 0x0820U) +#define SYSC_SYSCIMR0 (BASE_SYSC + 0x0830U) +#define SYSC_PDRONCR31 (BASE_SYSC + 0x1004U + (31U * 64U)) /* Power Domain:C4 */ +#endif /* RCAR_LSI == RCAR_V4M */ +#define SYSC_SYSCD1WACR0 (BASE_SYSC + 0x3020U) +#define SYSC_SYSCD2WACR0 (BASE_SYSC + 0x3040U) +#define SYSC_SYSCD3WACR0 (BASE_SYSC + 0x3060U) + +#if (RCAR_LSI == RCAR_V4M) +#define SYSCIER0_PDR31 (0x80000000U) /* Bit31 */ +#define SYSCIMR0_PDR31 (0x80000000U) /* Bit31 */ +#define SYSCISCR0_PDR31 (0x80000000U) /* Bit31 */ +#define SYSCSR_BUSY1 (0x00000002U) /* Bit1 */ +#define PDRONCR31_PWRON (0x00000001U) /* Bit0 */ +#endif /* RCAR_LSI == RCAR_V4M */ + +/* Prototype */ +#if (RCAR_LSI == RCAR_V4M) +void sysc_c4_power_on(void); +#endif /* RCAR_LSI == RCAR_V4M */ +#endif /* SYSC_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/types.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/types.h new file mode 100644 index 0000000..8a34d4c --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/types.h @@ -0,0 +1,57 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Types Define header + ******************************************************************************/ + + +#ifndef TYPES_H +#define TYPES_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * File Name: types.h + * Contents : Types Define + ****************************************************************************/ +#include +#include + +#ifndef FALSE +#define FALSE (0U) +#endif + +#ifndef TRUE +#define TRUE (1U) +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/vect_set.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/vect_set.h new file mode 100644 index 0000000..b90dbc2 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/vect_set.h @@ -0,0 +1,35 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Set vector table function header + ******************************************************************************/ + +#ifndef VECT_SET_H__ +#define VECT_SET_H__ + +extern char __ghsbegin_EIINTTBL_ICU[]; + +void set_vect_table(void); + +#endif /* VECT_SET_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/wdt.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/wdt.h new file mode 100644 index 0000000..0207513 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/include/wdt.h @@ -0,0 +1,36 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : window watchdog timer function header + ******************************************************************************/ + +#ifndef WDT_H__ +#define WDT_H__ + +void wdt_init(void); +void wdt_restart(void); +void wdt_handler(void); + + +#endif /* WDT_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/intc/intc.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/intc/intc.c new file mode 100644 index 0000000..aca2576 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/intc/intc.c @@ -0,0 +1,155 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Interrupt controler driver + ******************************************************************************/ +/****************************************************************************** + * @file intc.c + * - Version : 0.02 + * @brief Interrupt controler driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 06.01.2022 0.01 First Release + * : 05,04.2023 0.02 Remove string.h + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +#define INTC_EI_MAX (64U) +#define INTC_EI_ID_MASK (0xFFU) + +#define ICUMX_IC_MK_BIT (0x0080U) /* Interrupt request mask */ +#define ICUMX_IC_TB_BIT (0x0040U) /* Vector table selection system */ +#define ICUMX_IC_PRIORITY_MASK (0x0007U) + +#define INT_FLG_ENABLE (0x10U) +#define INT_FLG_DISABLE (0x00U) + +#define EXCEPTION_SOURCE_CODE_BIT (0x1000U) + + +typedef struct { + INT_HANDLER handler; + uint32_t arg; + uint32_t flg; +} INTC_HDR_TBL; + +static INTC_HDR_TBL s_intc_tbl[INTC_EI_MAX]; + +void intc_set_interrupt(uint32_t int_no, uint32_t level, INT_HANDLER cb) +{ + uint16_t reg; + __DI(); + + /* check Exception Source code */ + if (INTC_EI_MAX <= int_no) + { + ERROR("Undefined Exception Source code error.(0x%x)\n", int_no); + panic; + } + + /* set interrupt handler */ + s_intc_tbl[int_no].handler = cb; + s_intc_tbl[int_no].flg = INT_FLG_ENABLE; + + /* the interrupt enable */ + reg = mem_read16(get_icumx_ic_addr(int_no)); + reg &= (~(ICUMX_IC_MK_BIT) | ICUMX_IC_PRIORITY_MASK); + reg |= (ICUMX_IC_TB_BIT | (level & ICUMX_IC_PRIORITY_MASK)); + mem_write16(get_icumx_ic_addr(int_no), reg); + + __EI(); +} +/* End of function intc_set_interrupt(uint32_t int_no, uint32_t level, INT_HANDLER cb) */ + + +void intc_disable_interrupt(uint32_t int_no) +{ + uint16_t reg; + __DI(); + + /* check Exception Source code */ + if (INTC_EI_MAX <= int_no) + { + ERROR("Undefined Exception Source code error.(0x%x)\n", int_no); + panic; + } + + /* check interrupt enable flag */ + if (INT_FLG_DISABLE == (s_intc_tbl[int_no].flg & INT_FLG_ENABLE)) + { + ERROR("Execption disabled.(0x%x)\n", int_no); + panic; + } + + /* the interrupt disable */ + s_intc_tbl[int_no].flg &= ~INT_FLG_ENABLE; + reg = mem_read16(get_icumx_ic_addr(int_no)); + reg &= ~(ICUMX_IC_TB_BIT); + reg |= ICUMX_IC_MK_BIT; + mem_write16(get_icumx_ic_addr(int_no), reg); + + __EI(); +} +/* End of function intc_disable_interrupt(uint32_t int_no) */ + +#pragma ghs interrupt(nonreentrant) +void intc_handler(void) +{ + uint32_t reg; + uint32_t int_no; + reg = __STSR(EIIC); + + /* check Exception Source code */ + if ((reg & EXCEPTION_SOURCE_CODE_BIT) == 0U) + { + ERROR("Undefined Exception Source code error.(0x%x)\n", reg); + panic; + } + int_no = reg & INTC_EI_ID_MASK; + if (INTC_EI_MAX <= int_no) + { + ERROR("Undefined Exception Source code error.(0x%x)\n", int_no); + panic; + } + + /* check interrupt enable flag */ + if (INT_FLG_DISABLE == (s_intc_tbl[int_no].flg & INT_FLG_ENABLE)) + { + ERROR("Execption disabled.(0x%x)\n", int_no); + panic; + } + + /* execute interrupt handler */ + s_intc_tbl[int_no].handler(int_no, s_intc_tbl[int_no].arg); +} +/* End of function intc_handler(void) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/intc/vect_set.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/intc/vect_set.c new file mode 100644 index 0000000..cb7b7ec --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/intc/vect_set.c @@ -0,0 +1,50 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Set vector table function + ******************************************************************************/ +/****************************************************************************** + * @file vect_set.c + * - Version : 0.01 + * @brief Set vector table function. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 06.01.2022 0.01 First Release + *****************************************************************************/ +#include +#include +#include "intc.h" +#include "vect_set.h" +#include "cpu.h" +#include "rst_register.h" +#include "mem_io.h" + +void set_vect_table(void) +{ + /* set interrupt table */ + __LDSR(INTBP, (uint32_t)&__ghsbegin_EIINTTBL_ICU[0]); +} +/* End of function set_vect_table(void) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/intc/vecttbl.S b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/intc/vecttbl.S new file mode 100644 index 0000000..4128399 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/intc/vecttbl.S @@ -0,0 +1,181 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader vector table + ******************************************************************************/ + + .global code_start + .global intc_handler + + .section ".reset" + .align 512 + .align 16 +_start: + jr32 code_start //RESET + .align 16 + jr32 _Dummy //SYSERR + .align 16 + jr32 _Dummy //HVTRAP + .align 16 + jr32 _Dummy //FETRAP + .align 16 + jr32 _Dummy //TRAP0 + .align 16 + jr32 _Dummy //TRAP1 + .align 16 + jr32 _Dummy //RIE + .align 16 + jr32 _Dummy //FPP/FPI + .align 16 + jr32 _Dummy //UCPOP + .align 16 + jr32 _Dummy //MIP/MDP + .align 16 + jr32 _Dummy //PIE + .align 16 + jr32 _Dummy //Debug + .align 16 + jr32 _Dummy //MAE + .align 16 + jr32 _Dummy //(R.F.U) + .align 16 + jr32 _Dummy //FENMI + .align 16 + jr32 _Dummy //FEINT + .align 16 + jr32 _Dummy //INTn(priority0) + .align 16 + jr32 _Dummy //INTn(priority1) + .align 16 + jr32 _Dummy //INTn(priority2) + .align 16 + jr32 _Dummy //INTn(priority3) + .align 16 + jr32 _Dummy //INTn(priority4) + .align 16 + jr32 _Dummy //INTn(priority5) + .align 16 + jr32 _Dummy //INTn(priority6) + .align 16 + jr32 _Dummy //INTn(priority7) + .align 16 + jr32 _Dummy //INTn(priority8) + .align 16 + jr32 _Dummy //INTn(priority9) + .align 16 + jr32 _Dummy //INTn(priority10) + .align 16 + jr32 _Dummy //INTn(priority11) + .align 16 + jr32 _Dummy //INTn(priority12) + .align 16 + jr32 _Dummy //INTn(priority13) + .align 16 + jr32 _Dummy //INTn(priority14) + .align 16 + jr32 _Dummy //INTn(priority15) + + .section ".EIINTTBL_ICU", const + .align 512 +.offset 0x0000 + .word _intc_handler /* 0 : INTICUECCLRAM */ +.offset 0x0004 + .word _intc_handler /* 1 : INTICUECCCRAM */ +.offset 0x0008 + .word _intc_handler /* 2 : INTICUEDCAXI */ +.offset 0x000C + .word _intc_handler /* 3 : INTICUECCAXIAB */ +.offset 0x0010 + .word _intc_handler /* 4 : INTICUECCPKRAM */ +.offset 0x0014 + .word _intc_handler /* 5 : INTPES */ +.offset 0x0018 + .word _intc_handler /* 6 : INTPE */ +.offset 0x001C + .word _intc_handler /* 7 : INTICUAESD0RD */ +.offset 0x0020 + .word _intc_handler /* 8 : Reserved */ +.offset 0x0024 + .word _intc_handler /* 9 : INTICUTRNGE0 */ +.offset 0x0028 + .word _intc_handler /* 10 : INTICUOSTM0 */ +.offset 0x002C + .word _intc_handler /* 11 : INTICUOSTM1 */ +.offset 0x0030 + .word _intc_handler /* 12 : INTICUWDTA0 */ +.offset 0x0034 + .word _intc_handler /* 13 : INTICUPKCCA0 */ +.offset 0x0038 + .word _intc_handler /* 14 : INTICUDMACA0 */ +.offset 0x003C + .word _intc_handler /* 15 : INTICUDMACA0AXI */ +.offset 0x0040 + .word _intc_handler /* 16 : Reserved */ +.offset 0x0044 + .word _intc_handler /* 17 : INTICUSHAA0IREQ */ +.offset 0x0048 + .word _intc_handler /* 18 : INTICUSHAA0OEND */ +.offset 0x004C + .word _intc_handler /* 19 : INTICUCRCDRQA */ +.offset 0x0050 + .word _intc_handler /* 20 : INTICUCRRDRQA */ +.offset 0x0054 + .word _intc_handler /* 21 : INTICUCRCDRQ1 */ +.offset 0x0058 + .word _intc_handler /* 22 : INTICUCRRDRQ */ +.offset 0x005C + .word _intc_handler /* 23 : INTICUCRCDRQ2 */ +.offset 0x0060 + .word _intc_handler /* 24 : Reserved */ +.offset 0x0064 + .word _intc_handler /* 25 : INTICUERRCFDA */ +.offset 0x0068 + .word _intc_handler /* 26 : INTICUERRDFDA */ +.offset 0x006C + .word _intc_handler /* 27 : Reserved */ +.offset 0x0070 + .word _intc_handler /* 28 : Reserved */ +.offset 0x0074 + .word _intc_handler /* 29 : INTSAFRTRAMERR */ +.offset 0x0078 + .word _intc_handler /* 30 : INTSECRTRAMERR */ +.offset 0x007C + .word _intc_handler /* 31 : INTEDCRTRAMERR */ +.offset 0x0080 + .word _intc_handler /* 32 : INTECCRTRAMCMPE */ +.offset 0x0084 + .word _intc_handler /* 33 : INTECCMRTRAMERR */ +.offset 0x0088 + .word _intc_handler /* 34 : INTECCSRTRAMERR */ +.offset 0x008C + .word _intc_handler /* 35 : INTEDCMSECROMER */ +.offset 0x0090 + .word _intc_handler /* 36 : INTEDCSSECROMER */ +.offset 0x0094 + .word _intc_handler /* 37 : INTSCEGCALEND */ + + .section ".text" + .align 2 +_Dummy: + br _Dummy diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/avs/avs.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/avs/avs.c new file mode 100644 index 0000000..69bc727 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/avs/avs.c @@ -0,0 +1,115 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : AVS driver + ******************************************************************************/ +/****************************************************************************** + * @file avs.c + * - Version : 0.01 + * @brief AVS driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 16.11.2023 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#define AVS_BASE (BASE_AVS_ADDR) /* Physical address:0xE60A0000, Logical address:0xFDAA0000 */ +#define AVS_ADVADJP (AVS_BASE + 0x0080U) +#define ADVADJP_VOLCOND_MASK (0x000001FFU) + +#define VOLCOND_NUM (5U) /* Array number */ +#define VOLCOND_FLAG_4 (4U) +#define VOLCOND_FLAG_2 (2U) + +/* I2C Slave Address */ +#define SLAVE_RW_ADDR (0x000000C8U) + +/* PMIC register Address */ +#define BUCK1_DVS0CFG1 (0x00000072U) +#define BUCK1_DVS0CFG0 (0x00000073U) +#define DVS_CFG_NUM (2U) /* Array number */ + +/* PMIC register setting value */ +#define BUCK1_DVS0CFG1_VOLCOND2 (0x0000009FU) /* Setting value for 0.7575[V] */ +#define BUCK1_DVS0CFG0_VOLCOND2 (0x000000C0U) /* Setting value for 0.7575[V] */ +#define BUCK1_DVS0CFG1_VOLCOND4 (0x0000009AU) /* Setting value for 0.7325[V] */ +#define BUCK1_DVS0CFG0_VOLCOND4 (0x00000080U) /* Setting value for 0.7325[V] */ + +void avs_low_power_mode_setting(void) +{ + uint32_t volcond; + + /* Initialize I2C ch3. */ + i2c3_init(); + + /* Confirm VOLCOND in ADVADJP register. */ + volcond = mem_read32(AVS_ADVADJP); + volcond &= ADVADJP_VOLCOND_MASK; + + NOTICE("Low Power Mode setting(AVS) VOLCOND=%d\n", volcond); + switch (volcond) + { + case VOLCOND_FLAG_2: + { + /* In case of VOLCOND=2, set supply voltage to 0.7575[V]. */ + i2c3_write(SLAVE_RW_ADDR, BUCK1_DVS0CFG1, BUCK1_DVS0CFG1_VOLCOND2); + i2c3_write(SLAVE_RW_ADDR, BUCK1_DVS0CFG0, BUCK1_DVS0CFG0_VOLCOND2); + INFO("VOLCOND=0x%x SET Slave=0x%x Register=0x%x Value=0x%x\n", + volcond, SLAVE_RW_ADDR, BUCK1_DVS0CFG1, BUCK1_DVS0CFG1_VOLCOND2); + INFO("VOLCOND=0x%x SET Slave=0x%x Register=0x%x Value=0x%x\n", + volcond, SLAVE_RW_ADDR, BUCK1_DVS0CFG0, BUCK1_DVS0CFG0_VOLCOND2); + break; + } + case VOLCOND_FLAG_4: + { + /* In case of VOLCOND=4, set supply voltage to 0.7325[V]. */ + i2c3_write(SLAVE_RW_ADDR, BUCK1_DVS0CFG1, BUCK1_DVS0CFG1_VOLCOND4); + i2c3_write(SLAVE_RW_ADDR, BUCK1_DVS0CFG0, BUCK1_DVS0CFG0_VOLCOND4); + INFO("VOLCOND=0x%x SET Slave=0x%x Register=0x%x Value=0x%x\n", + volcond, SLAVE_RW_ADDR, BUCK1_DVS0CFG1, BUCK1_DVS0CFG1_VOLCOND4); + INFO("VOLCOND=0x%x SET Slave=0x%x Register=0x%x Value=0x%x\n", + volcond, SLAVE_RW_ADDR, BUCK1_DVS0CFG0, BUCK1_DVS0CFG0_VOLCOND4); + break; + } + default: + { + /* Other than VOLCOND = 2 or 4, nothing to do. */ + break; + } + } + + /* Release I2C ch3 */ + i2c3_release(); +} +/* End of function avs_low_power_mode_setting(void) */ + + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/cpg/cpg.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/cpg/cpg.c new file mode 100644 index 0000000..0825aba --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/cpg/cpg.c @@ -0,0 +1,83 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : CPG initialize + ******************************************************************************/ + /****************************************************************************** + * @file cpg.c + * - Version : 0.03 + * @brief Initial setting process of CPG. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Move cpg_reg_write function to cpg.h. + * : 27.12.2024 0.03 Add set_srcr function. + *****************************************************************************/ + +#include +#include +#if (RCAR_LSI == RCAR_V4H) +#include +#endif /* RCAR_LSI == RCAR_V4H */ + +/* CPG write protect value */ +#define CPGWPCR_PASSWORD (0xA5A50000U) +#define CPGWPCR_WPE ((uint32_t)1U << 0U) +#define CPGWPCR_WPE_VALID (0U) + +#if (RCAR_LSI == RCAR_V4H) +static void set_srcr(void); +#endif /* RCAR_LSI == RCAR_V4H */ + +void cpg_init(void) +{ + /* Release CPG write protect */ + if((mem_read32(CPG_CPGWPCR) & CPGWPCR_WPE) != CPGWPCR_WPE_VALID) + { + mem_write32(CPG_CPGWPR, ~(uint32_t)(CPGWPCR_PASSWORD)); + mem_write32(CPG_CPGWPCR, CPGWPCR_PASSWORD); + + /* bit in WPE = 0? */ + while ((mem_read32(CPG_CPGWPCR) & CPGWPCR_WPE) != CPGWPCR_WPE_VALID) + { + ; + } + } + +#if (RCAR_LSI == RCAR_V4H) + set_srcr(); +#endif /* RCAR_LSI == RCAR_V4H */ +} +/* End of function cpg_init(void) */ + +#if (RCAR_LSI == RCAR_V4H) +static void set_srcr(void) +{ + mem_write32(CPG_SRCR28, CPGSRCR28_VAL); + mem_write32(CPG_SRCR29, CPGSRCR29_VAL); +} +/* End of function set_srcr(void) */ +#endif /* RCAR_LSI == RCAR_V4H */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/boot_init_dram.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/boot_init_dram.h new file mode 100644 index 0000000..1ab608d --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/boot_init_dram.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation All rights reserved. + */ + +#ifndef __BOOT_INIT_DRAM_ +#define __BOOT_INIT_DRAM_ + +extern int32_t InitDram(void); + +#define INITDRAM_OK (0) +#define INITDRAM_NG (0xffffffff) +#define INITDRAM_ERR_I (0xffffffff) +#define INITDRAM_ERR_O (0xfffffffe) +#define INITDRAM_ERR_T (0xfffffff0) + +#endif /* __BOOT_INIT_DRAM_*/ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/ddr.mk b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/ddr.mk new file mode 100644 index 0000000..b31c2ea --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/ddr.mk @@ -0,0 +1,6 @@ +# +# Copyright (c) 2015-2022, Renesas Electronics Corporation All rights reserved. +# + +OBJ_FILE += ip/ddr/s4/lpddr4x/boot_init_dram.o +OBJ_FILE += ip/ddr/dram_sub_func.o \ No newline at end of file diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.c new file mode 100644 index 0000000..8003434 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.c @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2015-2018, Renesas Electronics Corporation All rights reserved. + */ + +#include +#include "dram_sub_func.h" + +void dram_get_boot_status(uint32_t *status) +{ + *status = DRAM_BOOT_STATUS_COLD; +} + +int32_t dram_update_boot_status(uint32_t status) +{ + int32_t ret = 0; + return ret; +} diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.h new file mode 100644 index 0000000..0afbb35 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/dram_sub_func.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2015-2019, Renesas Electronics Corporation All rights reserved. + */ + +#ifndef DRAM_SUB_FUNC_H_ +#define DRAM_SUB_FUNC_H_ + +#define DRAM_BOOT_STATUS_COLD (0U) +#define DRAM_BOOT_STATUS_WARM (1U) + +#define DRAM_UPDATE_STATUS_ERR (-1) + +void dram_get_boot_status(uint32_t *status); +int32_t dram_update_boot_status(uint32_t status); + +#endif /* DRAM_SUB_FUNC_H_ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram.c new file mode 100644 index 0000000..f4137dc --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram.c @@ -0,0 +1,2243 @@ +/******************************************************************************* + * Copyright (c) 2021-2023 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#else +#include +#include +#endif +#include "ddr_regdef.h" +#include "init_dram_tbl_s4.h" +#include "boot_init_dram_regdef.h" +#include "boot_init_dram.h" +#include "dram_sub_func.h" + +#define DDR_BACKUPMODE +#define FATAL_MSG(x) NOTICE(x) + +/******************************************************************************* + * variables + ******************************************************************************/ +/* +static uint32_t Prr_Product; +static uint32_t Prr_Cut; +*/ +static uint32_t _cnf_BOARDTYPE; +static uint32_t brd_clk; +static uint32_t brd_clkdiv; +static uint32_t brd_clkdiva; +static uint32_t ddr_mbps; +static uint32_t ddr_mbpsdiv; +static uint32_t bus_mbps, bus_mbpsdiv; +static uint32_t ddr_tccd; +static const struct _boardcnf *Boardcnf; +static uint32_t ddr_phyvalid; +static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; +static uint32_t ch_have_this_cs[CS_CNT]; +static uint32_t max_density; +static uint32_t ddr_mul; +static uint32_t ddr_mul_nf; +static uint32_t ddr_mul_low; +static uint32_t ddrtbl_load_num; + +#define DDR_PHY_REGSET_MAX 143 +#define DDR_PI_REGSET_MAX 223 +static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX]; +#ifdef DDR_BACKUPMODE +static uint32_t ddrBackup; +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static uint32_t vch_nxt(uint32_t pos); +static void cpg_write_32(uint32_t a, uint32_t v); +static void pll3_control(uint32_t high); + +static void send_dbcmd(uint32_t cmd); +static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd); +static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata); +static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata); +static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, uint32_t val); +static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef); +static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val); +static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); +static void ddr_setval_ach(uint32_t regdef, uint32_t val); +static void ddr_setval_ach_as(uint32_t regdef, uint32_t val); +static uint32_t ddr_getval(uint32_t ch, uint32_t regdef); +static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size); +static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val); +static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef); +static uint16_t _f_scale(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint16_t cyc); +static void _f_scale_js2(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint16_t *f_js2); +static void ddrtbl_load(void); +static void ddrtbl_load_pi(void); +static void ddr_config(void); +static void dbsc_regset(void); +static void dbsc_regset_post(void); +static uint32_t dfi_init_start(void); +static void ddr_register_set(void); +static void wait_dbpdstat1(uint32_t status); +static uint32_t wait_freqchgreq(uint32_t req_assert); +static void set_freqchgack(uint32_t ack_assert); +static void set_dfifrequency(uint32_t freq); +static uint32_t pll3_freq(uint32_t fsel); +static uint32_t pi_training_go(void); +static void manual_frequency_change(void); +static uint32_t manual_training_wrlvl(void); +static uint32_t manual_training_rdgtlvl(void); +static uint32_t manual_training_rdlvl(void); +static uint32_t manual_training_wdqlvl(void); +static uint32_t ca_vref_training(void); +static uint32_t init_ddr(void); +static uint32_t boardcnf_get_brd_type(void); +static void dbsc_write_32(uintptr_t addr, uint32_t data); + +/******************************************************************************* + * load board configuration + ******************************************************************************/ +#include "boot_init_dram_config.c" + +/******************************************************************************* + * CA Vref Training setting + ******************************************************************************/ +#ifndef DDR_CAVREF_VAL +#define DDR_CAVREF_VAL 0x11 +#endif + +#ifndef DDR_CAVREF_DELTA +#define DDR_CAVREF_DELTA 3 +#endif + +/******************************************************************************* + * macro for channel selection loop + ******************************************************************************/ +static uint32_t vch_nxt(uint32_t pos) +{ + uint32_t posn; + + for (posn = pos; posn < DRAM_CH_CNT; posn++) { + if (ddr_phyvalid & (1U << posn)) { + break; + } + } + return posn; +} + +#define foreach_vch(ch) \ +for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1U)) + +#define foreach_ech(ch) \ +for (ch = 0U; ch < DRAM_CH_CNT; ch++) + +/******************************************************************************* + * Printing functions + ******************************************************************************/ +#define MSG_LF(...) + +/******************************************************************************* + * clock settings, reset control + ******************************************************************************/ +static void cpg_write_32(uint32_t a, uint32_t v) +{ + mmio_write_32(CPG_CPGWPR, ~v); + mmio_write_32(a, v); +} + +static void pll3_control(uint32_t high) +{ + uint32_t dataDIV, dataMUL; + uint32_t ssmode, dataNF; + + if (high) { + /* High frequency mode */ + dataMUL = ddr_mul - 1U; + dataDIV = 0x02U; + dataNF = ddr_mul_nf; + } else { + /* Low frequency mode (25MHz) */ + dataMUL = ddr_mul_low - 1U; /* PLL3VCO = 1600MHz */ + dataDIV = 0x0CU; /* div = 64 */ + dataNF = 0x00U; + } + + ssmode = 0x04U; + dataMUL = (dataMUL << 20) | (ssmode << 16); + dataNF = (dataNF << 20); + + /* PLL3 multiplie set */ + if (((mmio_read_32(CPG_PLL3CR0) & 0x3FFFFF7FU) != dataMUL) || (mmio_read_32(CPG_PLL3CR1) != dataNF) ) { + cpg_write_32(CPG_PLL3CR0, dataMUL); + cpg_write_32(CPG_PLL3CR1, dataNF); + cpg_write_32(CPG_PLL3CR0, mmio_read_32(CPG_PLL3CR0) | CPG_PLL3CR_KICK_BIT); + while ((mmio_read_32(CPG_PLLECR) & CPG_PLLECR_PLL3ST_BIT) != CPG_PLLECR_PLL3ST_BIT); + } + /* PLL3 DIV set(Target value) */ + while ((mmio_read_32(CPG_FRQCRD) & CPG_FRQCRD_KICK_BIT)); + cpg_write_32(CPG_FRQCRD, dataDIV | (mmio_read_32(CPG_FRQCRD) & 0xFFFFFF80U)); + cpg_write_32(CPG_FRQCRD, mmio_read_32(CPG_FRQCRD) | CPG_FRQCRD_KICK_BIT); + while ((mmio_read_32(CPG_FRQCRD) & CPG_FRQCRD_KICK_BIT)); + +} + +/******************************************************************************* + * DDR memory register access + ******************************************************************************/ +static void send_dbcmd(uint32_t cmd) +{ + /* dummy read */ + mmio_read_32(DBSC_DBCMD); + while ((mmio_read_32(DBSC_DBWAIT)) & 0x01U); + + dbsc_write_32((DBSC_DBCMD), cmd); +} + +/******************************************************************************* + * DDRPHY register access (raw) + ******************************************************************************/ +static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd) +{ + uint32_t val; + + val = 0U; + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00004000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x0000C000U)); + + val = mmio_read_32(DBSC_DBPDRGA(phyno)); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd); + + val = mmio_read_32(DBSC_DBPDRGD(phyno)); + (void)val; + + return val; +} + +static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) +{ + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd); + + mmio_write_32(DBSC_DBPDRGD(phyno), regdata); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x00008000U)); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); +} + +static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) +{ + uint32_t ch; + + foreach_vch(ch) { + reg_ddrphy_write(ch, regadd, regdata); + } +} + +/******************************************************************************* + * DDRPHY register access (field modify) + ******************************************************************************/ +static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + + adr = DDR_REGDEF_ADR(_regdef) + 0x100U * slice; + len = DDR_REGDEF_LEN(_regdef); + lsb = DDR_REGDEF_LSB(_regdef); + if (len == 0x20U) { + msk = 0xffffffffU; + } else { + msk = ((1U << len) - 1U) << lsb; + } + + tmp = reg_ddrphy_read(ch, adr); + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + reg_ddrphy_write(ch, adr, tmp); +} + +static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + + adr = DDR_REGDEF_ADR(_regdef) + 0x100U * slice; + len = DDR_REGDEF_LEN(_regdef); + lsb = DDR_REGDEF_LSB(_regdef); + if (len == 0x20U) { + msk = 0xffffffffU; + } else { + msk = ((1U << len) - 1U); + } + + tmp = reg_ddrphy_read(ch, adr); + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) +{ + ddr_setval_s(ch, 0U, regdef, val); +} + +static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val) +{ + uint32_t ch; + + foreach_vch(ch) { + ddr_setval_s(ch, slice, regdef, val); + } +} + +static void ddr_setval_ach(uint32_t regdef, uint32_t val) +{ + ddr_setval_ach_s(0U, regdef, val); +} + +static void ddr_setval_ach_as(uint32_t regdef, uint32_t val) +{ + uint32_t slice; + + for (slice = 0U; slice < SLICE_CNT; slice++) { + ddr_setval_ach_s(slice, regdef, val); + } +} + +static uint32_t ddr_getval(uint32_t ch, uint32_t regdef) +{ + return ddr_getval_s(ch, 0U, regdef); +} + +/******************************************************************************* + * DBSC register access + ******************************************************************************/ +static void dbsc_write_32(uintptr_t addr, uint32_t data) +{ + *((volatile uint32_t*)addr) = data; +} + +/******************************************************************************* + * handling functions for setteing ddrphy value table + ******************************************************************************/ +static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size) +{ + uint32_t i; + + for (i = 0U; i < size; i++) { + to[i] = from[i]; + } +} + +static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000000ffU; + + adr = DDR_REGDEF_ADR(_regdef); + len = DDR_REGDEF_LEN(_regdef); + lsb = DDR_REGDEF_LSB(_regdef); + if (len == 0x20U) { + msk = 0xffffffffU; + } else { + msk = ((1U << len) - 1U) << lsb; + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + tbl[adr & adrmsk] = tmp; +} + +static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000000ffU; + + adr = DDR_REGDEF_ADR(_regdef); + len = DDR_REGDEF_LEN(_regdef); + lsb = DDR_REGDEF_LSB(_regdef); + if (len == 0x20U) { + msk = 0xffffffffU; + } else { + msk = ((1U << len) - 1U); + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +/******************************************************************************* + * functions and parameters for timing setting + ******************************************************************************/ +struct _jedec_spec1 { + uint16_t fx3; + uint8_t RLwoDBI; + uint8_t RLwDBI; + uint8_t WL; + uint8_t nWR; + uint8_t nRTP; + uint8_t ODTLon; + uint8_t MR1; + uint8_t MR2; + uint16_t tRRD; + uint16_t tFAW; +}; + +#define JS1_USABLEC_SPEC_LO 2 +#define JS1_USABLEC_SPEC_HI 7 +#define JS1_FREQ_TBL_NUM 8 +#define JS1_MR1(f) (0x04 | ((f) << 4)) +#define JS1_MR2(f) (0x00 | ((f) << 3) | (f)) + +const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { + { 800, 6, 6, 4, 6 , 8, 0, JS1_MR1(0), JS1_MR2(0)|0x40,10000, 40000 }, /* 533.333Mbps*/ + { 1600, 10, 12, 8, 10 , 8, 0, JS1_MR1(1), JS1_MR2(1)|0x40,10000, 40000 }, /* 1066.666Mbps*/ + { 2400, 14, 16, 12, 16 , 8, 6, JS1_MR1(2), JS1_MR2(2)|0x40,10000, 40000 }, /* 1600.000Mbps*/ + { 3200, 20, 22, 10, 20 , 8, 4, JS1_MR1(3), JS1_MR2(3), 10000, 40000 }, /* 2133.333Mbps*/ + { 4000, 24, 28, 12, 24 ,10, 4, JS1_MR1(4), JS1_MR2(4), 10000, 40000 }, /* 2666.666Mbps*/ + { 4800, 28, 32, 14, 30 ,12, 6, JS1_MR1(5), JS1_MR2(5), 10000, 40000 }, /* 3200.000Mbps*/ + { 5600, 32, 36, 16, 34 ,14, 6, JS1_MR1(6), JS1_MR2(6), 10000, 40000 }, /* 3733.333Mbps*/ + { 6400, 36, 40, 18, 40 ,16, 8, JS1_MR1(7), JS1_MR2(7), 7500, 30000 } /* 4266.666Mbps*/ +}; + +struct _jedec_spec2 { + uint16_t ps; + uint16_t cyc; +}; + +#define JS2_tSR 0 +#define JS2_tXP 1 +#define JS2_tRTP 2 +#define JS2_tRCD 3 +#define JS2_tRPpb 4 +#define JS2_tRPab 5 +#define JS2_tRAS 6 +#define JS2_tWR 7 +#define JS2_tWTR 8 +#define JS2_tRRD 9 +#define JS2_tPPD 10 +#define JS2_tFAW 11 +#define JS2_tDQSCK 12 +#define JS2_tCKEHCMD 13 +#define JS2_tCKELCMD 14 +#define JS2_tCKELPD 15 +#define JS2_tMRR 16 +#define JS2_tMRW 17 +#define JS2_tMRD 18 +#define JS2_tZQCALns 19 +#define JS2_tZQLAT 20 +#define JS2_tIEdly 21 +#define JS2_tODTon_min 22 +#define JS2_TBLCNT 23 + +#define JS2_tRCpb (JS2_TBLCNT) +#define JS2_tRCab (JS2_TBLCNT + 1) +#define JS2_tRFCab (JS2_TBLCNT + 2) +#define JS2_CNT (JS2_TBLCNT + 3) + +#ifndef JS2_DERATE +#define JS2_DERATE 0 +#endif +const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { + { +/*tSR */ { 15000, 3 }, +/*tXP */ { 7500, 3 }, +/*tRTP */ { 7500, 8 }, +/*tRCD */ { 18000, 4 }, +/*tRPpb */ { 18000, 3 }, +/*tRPab */ { 21000, 3 }, +/*tRAS */ { 42000, 3 }, +/*tWR */ { 18000, 4 }, +/*tWTR */ { 10000, 8 }, +/*tRRD */ { 0, 0 }, +/*tPPD */ { 0, 0 }, +/*tFAW */ { 0, 0 }, +/*tDQSCK*/ { 3500, 0 }, +/*tCKEHCMD*/ { 7500, 3 }, +/*tCKELCMD*/ { 7500, 3 }, +/*tCKELPD*/ { 7500, 3 }, +/*tMRR*/ { 0, 8 }, +/*tMRW*/ { 10000, 10 }, +/*tMRD*/ { 14000, 10 }, +/*tZQCALns*/ { 1000, 0 }, +/*tZQLAT*/ { 30000, 10 }, +/*tIEdly*/ { 6000, 0 }, +/*tODTon_min*/ { 1500, 0 } + },{ +/*tSR */ { 15000, 3 }, +/*tXP */ { 7500, 3 }, +/*tRTP */ { 7500, 8 }, +/*tRCD */ { 19875, 4 }, +/*tRPpb */ { 19875, 3 }, +/*tRPab */ { 22875, 3 }, +/*tRAS */ { 43875, 3 }, +/*tWR */ { 18000, 4 }, +/*tWTR */ { 10000, 8 }, +/*tRRD */ { 1875, 0 }, +/*tPPD */ { 0, 0 }, +/*tFAW */ { 0, 0 }, +/*tDQSCK*/ { 3600, 0 }, +/*tCKEHCMD*/ { 7500, 3 }, +/*tCKELCMD*/ { 7500, 3 }, +/*tCKELPD*/ { 7500, 3 }, +/*tMRR*/ { 0, 8 }, +/*tMRW*/ { 10000, 10 }, +/*tMRD*/ { 14000, 10 }, +/*tZQCALns*/ { 1000, 0 }, +/*tZQLAT*/ { 30000, 10 }, +/*tIEdly*/ { 6000, 0 }, +/*tODTon_min*/ { 1500, 0 } + } +}; + +const uint16_t jedec_spec2_tRFC_ab[5] = { +/* 4Gb, 6Gb, 8Gb,12Gb,16Gb (24Gb/32Gb non) */ + 130, 180, 180, 280, 280 +}; + +static uint32_t js1_ind; +static uint16_t js2[JS2_CNT]; +static uint8_t RL; +static uint8_t WL; + +static uint16_t _f_scale(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint16_t cyc) +{ + uint32_t tmp; + uint32_t div; + + tmp = (((uint32_t)(ps) + 9U) / 10U) * f_ddr_mbps; + div = tmp / (200000U * f_ddr_mbpsdiv); + if (tmp != (div * 200000U * f_ddr_mbpsdiv)) { + div = div + 1U; + } + + if (div > cyc) { + cyc = (uint16_t)div; + } + + return cyc; +} + +static void _f_scale_js2(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint16_t *f_js2) +{ + uint32_t i; + + for (i = 0U; i < JS2_TBLCNT; i++) { + f_js2[i] = _f_scale(f_ddr_mbps, f_ddr_mbpsdiv, + (uint32_t)jedec_spec2[JS2_DERATE][i].ps, + jedec_spec2[JS2_DERATE][i].cyc); + } + + f_js2[JS2_tRRD] = _f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(js1[js1_ind].tRRD + jedec_spec2[JS2_DERATE][JS2_tPPD].ps), 4U); + f_js2[JS2_tFAW] = _f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(js1[js1_ind].tFAW + jedec_spec2[JS2_DERATE][JS2_tFAW].ps), 0U); + f_js2[JS2_tZQCALns] = _f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tZQCALns].ps) * 1000U, 0U); + f_js2[JS2_tRCpb] = f_js2[JS2_tRAS] + f_js2[JS2_tRPpb]; + f_js2[JS2_tRCab] = f_js2[JS2_tRAS] + f_js2[JS2_tRPab]; +} + +static const uint32_t _reg_PI_MR1_DATA_Fx_CSx[3][CS_CNT] = { + { + _reg_PI_MR1_DATA_F0_0, + _reg_PI_MR1_DATA_F0_1 + }, + { + _reg_PI_MR1_DATA_F1_0, + _reg_PI_MR1_DATA_F1_1 + }, + { + _reg_PI_MR1_DATA_F2_0, + _reg_PI_MR1_DATA_F2_1 + } +}; + +static const uint32_t _reg_PI_MR2_DATA_Fx_CSx[3][CS_CNT] = { + { + _reg_PI_MR2_DATA_F0_0, + _reg_PI_MR2_DATA_F0_1 + }, + { + _reg_PI_MR2_DATA_F1_0, + _reg_PI_MR2_DATA_F1_1 + }, + { + _reg_PI_MR2_DATA_F2_0, + _reg_PI_MR2_DATA_F2_1 + } +}; + +static const uint32_t _reg_PI_MR3_DATA_Fx_CSx[3][CS_CNT] = { + { + _reg_PI_MR3_DATA_F0_0, + _reg_PI_MR3_DATA_F0_1 + }, + { + _reg_PI_MR3_DATA_F1_0, + _reg_PI_MR3_DATA_F1_1 + }, + { + _reg_PI_MR3_DATA_F2_0, + _reg_PI_MR3_DATA_F2_1 + } +}; + +static const uint32_t _reg_PI_MR11_DATA_Fx_CSx[3][CS_CNT] = { + { + _reg_PI_MR11_DATA_F0_0, + _reg_PI_MR11_DATA_F0_1 + }, + { + _reg_PI_MR11_DATA_F1_0, + _reg_PI_MR11_DATA_F1_1 + }, + { + _reg_PI_MR11_DATA_F2_0, + _reg_PI_MR11_DATA_F2_1 + } +}; + +static const uint32_t _reg_PI_MR12_DATA_Fx_CSx[3][CS_CNT] = { + { + _reg_PI_MR12_DATA_F0_0, + _reg_PI_MR12_DATA_F0_1 + }, + { + _reg_PI_MR12_DATA_F1_0, + _reg_PI_MR12_DATA_F1_1 + }, + { + _reg_PI_MR12_DATA_F2_0, + _reg_PI_MR12_DATA_F2_1 + } +}; + +static const uint32_t _reg_PI_MR14_DATA_Fx_CSx[3][CS_CNT] = { + { + _reg_PI_MR14_DATA_F0_0, + _reg_PI_MR14_DATA_F0_1 + }, + { + _reg_PI_MR14_DATA_F1_0, + _reg_PI_MR14_DATA_F1_1 + }, + { + _reg_PI_MR14_DATA_F2_0, + _reg_PI_MR14_DATA_F2_1 + } +}; + +/******************************************************************************* + * load table data into DDR registers + ******************************************************************************/ +static void ddrtbl_load(void) +{ + uint32_t i; + uint32_t slice; + uint32_t cs; + uint32_t adr; + uint32_t dataL; + uint32_t tmp[2]; + + const uint32_t DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_S4; + const uint32_t DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_S4; + const uint32_t DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_S4; + const uint32_t DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_S4; + + const uint32_t DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_S4; + + const uint32_t DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_S4; + const uint32_t DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_S4; + const uint32_t DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_S4; + + /*********************************************************************** + * TIMING REGISTERS + ***********************************************************************/ + /* search jedec_spec1 index */ + for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1U; i++) { + if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) { + break; + } + } + if (JS1_USABLEC_SPEC_HI < i) { + js1_ind = JS1_USABLEC_SPEC_HI; + } else { + js1_ind = i; + } + + RL = js1[js1_ind].RLwDBI; + + WL = js1[js1_ind].WL; + + /* calculate jedec_spec2 */ + _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); + + /*********************************************************************** + * PREPARE TBL + ***********************************************************************/ + _tblcopy(_cnf_DDR_PHY_SLICE_REGSET, + DDR_PHY_SLICE_REGSET_S4, DDR_PHY_SLICE_REGSET_NUM_S4); + _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, + DDR_PHY_ADR_V_REGSET_S4, DDR_PHY_ADR_V_REGSET_NUM_S4); + _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, + DDR_PHY_ADR_G_REGSET_S4, DDR_PHY_ADR_G_REGSET_NUM_S4); + _tblcopy(_cnf_DDR_PI_REGSET, + DDR_PI_REGSET_S4, DDR_PI_REGSET_NUM_S4); + + /*********************************************************************** + * Adjust PI paramters + ***********************************************************************/ + if (js2[JS2_tIEdly] > RL) { + js2[JS2_tIEdly] = RL; + } + + if (js2[JS2_tIEdly] >= 0x0fU) { + dataL = 0x0fU; + } else { + dataL = js2[JS2_tIEdly]; + } + + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataL); + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY, (dataL - 2U)); + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_OE_DLY, dataL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataL - 1U); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, WL - 4U); + + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, WL); + + tmp[0] = js1[js1_ind].MR1; + tmp[1] = js1[js1_ind].MR2; + + for (cs = 0U; cs < CS_CNT; cs++) { + for (i = 1U; i < 3U; i++) { + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR1_DATA_Fx_CSx[i][cs], tmp[0]); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR2_DATA_Fx_CSx[i][cs], tmp[1]); + } + } + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) { + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_SET_DFI_INPUT_RST_PAD, 0x01U); + } +#endif /* DDR_BACKUPMODE */ + + /*********************************************************************** + * Read Vref (SoC side) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->vref_r); + if (dataL) { + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_VREF_INITIAL_START_POINT, dataL & 0x00ffU); + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_VREF_INITIAL_STOP_POINT, (dataL & 0xff00U) >> 8); + } + + /*********************************************************************** + * Write Vref (MR14) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->vref_w); + if (dataL) { + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WDQLVL_VREF_DELTA_F0, (((dataL & 0xff00U) >> 8) - (dataL & 0x00ffU) + 1) / 2); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WDQLVL_VREF_DELTA_F1, (((dataL & 0xff00U) >> 8) - (dataL & 0x00ffU) + 1) / 2); + for (cs = 0U; cs < CS_CNT; cs++) { + for (i = 0U; i < 3U; i++) { + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR14_DATA_Fx_CSx[i][cs], (((dataL & 0xff00U) >> 8) + (dataL & 0x00ffU)) / 2); + } + } + } + + /*********************************************************************** + * CA Vref (MR12) Default configuration + ***********************************************************************/ + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_1, DDR_CAVREF_VAL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F0_0, DDR_CAVREF_VAL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_1, DDR_CAVREF_VAL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_F1_0, DDR_CAVREF_VAL); + + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_CALVL_VREF_INITIAL_START_POINT_F0, DDR_CAVREF_VAL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F0, DDR_CAVREF_VAL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_CALVL_VREF_INITIAL_START_POINT_F1, DDR_CAVREF_VAL); + ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F1, DDR_CAVREF_VAL); + + /*********************************************************************** + * Low Freq setting + ***********************************************************************/ + if (3 * ddr_mbps < 4 * 1600 * ddr_mbpsdiv) { + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL, 0x1342); + } + + if (ddr_mbps < 4 * 640 * ddr_mbpsdiv) { + /* PCLK(10-100MHz) */ + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_PAD_DSLICE_IO_CFG, 0x05); + ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_PAD_ADR_IO_CFG_0, 0x05); + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PAD_ACS_IO_CFG, 0x05); + + /* CAL_CLK(10-20MHz) */ + ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DATA_DC_CAL_CLK_SEL, 0x04); + ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, _reg_PHY_ADR_DC_CAL_CLK_SEL_0, 0x04); + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_CLK_DC_CAL_CLK_SEL, 0x04); + ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_CAL_CLK_SELECT_0, 0x05); + } + + /*********************************************************************** + * FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) + ***********************************************************************/ + ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x01U); + ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01U); + + /*********************************************************************** + * SET DATA SLICE TABLE + ***********************************************************************/ + for (slice = 0U; slice < SLICE_CNT; slice++) { + adr = DDR_PHY_SLICE_REGSET_OFS + DDR_PHY_SLICE_REGSET_SIZE * slice; + for (i = 0U; i < DDR_PHY_SLICE_REGSET_NUM; i++) { + reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_SLICE_REGSET[i]); + } + } + + /*********************************************************************** + * SET ADR SLICE TABLE + ***********************************************************************/ + adr = DDR_PHY_ADR_V_REGSET_OFS; + for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++) { + reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]); + } + + /*********************************************************************** + * SET ADRCTRL SLICE TABLE + ***********************************************************************/ + adr = DDR_PHY_ADR_G_REGSET_OFS; + for (i = 0U; i < DDR_PHY_ADR_G_REGSET_NUM; i++) { + reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]); + } + + /*********************************************************************** + * SET PI REGISTERS + ***********************************************************************/ + adr = DDR_PI_REGSET_OFS; + ddrtbl_load_num = 83U; + for (i = 0U; i < ddrtbl_load_num; i++) { + reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]); + } +} + +static void ddrtbl_load_pi(void) +{ + uint32_t ch, dataL; + + const uint32_t DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_S4; + const uint32_t DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_S4; + + /*********************************************************************** + * SET PI REGISTERS + ***********************************************************************/ + dataL = ddrtbl_load_num; + while (dataL < DDR_PI_REGSET_NUM) { + reg_ddrphy_write_a(DDR_PI_REGSET_OFS + dataL, _cnf_DDR_PI_REGSET[dataL]); + ++dataL; + } + + foreach_vch(ch) { + /* --- DATA_BYTE_SWAP --- */ + dataL = (uint32_t)(Boardcnf->ch[ch].dqs_swap); + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01U); + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0, dataL & 0x0fU); + ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1, (dataL >> 4) & 0x0fU); + + if (!(ch_have_this_cs[1] & (1U << ch))) { + ddr_setval(ch, _reg_PI_CS_MAP, 0x01U); + } + } +} + +/******************************************************************************* + * CONFIGURE DDR REGISTERS + ******************************************************************************/ +static void ddr_config(void) +{ + uint32_t ch, slice; + uint32_t dataL; + uint8_t high_byte[SLICE_CNT]; + + const uint32_t _par_CALVL_DEVICE_MAP = 1U; + + foreach_vch(ch) { + /*********************************************************************** + * BOARD SETTINGS (DQ, DM, VREF_DRIVING) + ***********************************************************************/ + for (slice = 0U; slice < SLICE_CNT; slice++) { + high_byte[slice] = ((uint32_t)(Boardcnf->ch[ch].dqs_swap) >> (4U * slice)) % 2; + ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0, Boardcnf->ch[ch].dq_swap[slice]); + ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1, (uint32_t)(Boardcnf->ch[ch].dm_swap[slice])); + if (high_byte[slice]) { + /* HIGHER 16 BYTE */ + ddr_setval_s(ch, slice, _reg_PHY_CALVL_VREF_DRIVING_SLICE, 0x00U); + } else { + /* LOWER 16 BYTE */ + ddr_setval_s(ch, slice, _reg_PHY_CALVL_VREF_DRIVING_SLICE, 0x01U); + } + } + + /*********************************************************************** + * BOARD SETTINGS (CA, ADDR_SEL) + ***********************************************************************/ + dataL = (0x00ffffffU & (uint32_t)(Boardcnf->ch[ch].ca_swap)); + + /* --- ADR_ADDR_SEL --- */ + ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL_0, dataL); + + /* --- ADR_CALVL_SWIZZLE --- */ + if (high_byte[1]) { + dataL |= 0x00888888U; + } + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, dataL); + ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000U); + ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP, _par_CALVL_DEVICE_MAP); + + /*********************************************************************** + * mask CS_MAP if RANK1 is not found + ***********************************************************************/ + if (!(ch_have_this_cs[1] & (1U << ch))) { + ddr_setval(ch, _reg_PHY_ADR_CALVL_RANK_CTRL_0, 0x00U); + for (slice = 0U; slice < SLICE_CNT; slice++) { + ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00U); + } + } + } +} + +/******************************************************************************* + * DBSC register setting functions + ******************************************************************************/ +static void dbsc_regset_pre(void) +{ + uint32_t ch, cs; + + /*********************************************************************** + * PRIMARY SETTINGS + ***********************************************************************/ + /* LPDDR4, BL=16, DFI interface */ + dbsc_write_32(DBSC_DBKIND, 0x0000000aU); + dbsc_write_32(DBSC_DBKINDA, 0x0000000aU); + dbsc_write_32(DBSC_DBBL, 0x00000002U); + dbsc_write_32(DBSC_DBBLA, 0x00000002U); + dbsc_write_32(DBSC_DBPHYCONF0, 0x00000001U); + + dbsc_write_32(DBSC_DBSYSCONF0, 0x00000001U); + + /* FREQRATIO=2 */ + dbsc_write_32(DBSC_DBSYSCONF1, 0x00000002U); + dbsc_write_32(DBSC_DBSYSCONF1A, 0x00000002U); + + dbsc_write_32(DBSC_DBSYSCONF2, 0x00000001U); + dbsc_write_32(DBSC_DBSYSCONF2A, 0x00000061U); + + foreach_ech(ch) { + for (cs = 0U; cs < CS_CNT; cs++) { + if (ddr_density[ch][cs] == 0xffU) { + mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00U); + mmio_write_32(DBSC_DBMEMCONFA(ch, cs), 0x00U); + } else { + mmio_write_32(DBSC_DBMEMCONF(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs])); + mmio_write_32(DBSC_DBMEMCONFA(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs])); + } + } + } +} + +static void dbsc_regset(void) +{ + uint32_t dataL; + uint32_t tmp[4]; + + /* RFC */ + js2[JS2_tRFCab] = _f_scale(ddr_mbps, ddr_mbpsdiv, + 1UL * jedec_spec2_tRFC_ab[max_density] * 1000, 0); + + /* DBTR0.CL : RL */ + dbsc_write_32(DBSC_DBTR(0), RL); + + /* DBTR1.CWL : WL */ + dbsc_write_32(DBSC_DBTR(1), WL); + + /* DBTR2.AL : 0 */ + dbsc_write_32(DBSC_DBTR(2), 0U); + + /* DBTR3.TRCD: tRCD */ + dbsc_write_32(DBSC_DBTR(3), js2[JS2_tRCD]); + + /* DBTR4.TRPA,TRP: tRPab,tRPpb */ + dbsc_write_32(DBSC_DBTR(4), (js2[JS2_tRPab] << 16) | js2[JS2_tRPpb]); + + /* DBTR5.TRC : use tRCpb */ + dbsc_write_32(DBSC_DBTR(5), js2[JS2_tRCpb]); + + /* DBTR6.TRAS : tRAS */ + dbsc_write_32(DBSC_DBTR(6), js2[JS2_tRAS]); + + /* DBTR7.TRRD : tRRD */ + dbsc_write_32(DBSC_DBTR(7), (js2[JS2_tRRD] << 16) | js2[JS2_tRRD]); + + /* DBTR8.TFAW : tFAW */ + dbsc_write_32(DBSC_DBTR(8), js2[JS2_tFAW]); + + /* DBTR9.TRDPR : nRTP */ + dbsc_write_32(DBSC_DBTR(9), js1[js1_ind].nRTP); + + /* DBTR10.TWR : nWR */ + dbsc_write_32(DBSC_DBTR(10), js1[js1_ind].nWR); + + /* DBTR11.TRDWR : RL + BL / 2 + Rounddown(tRPST) + PHY_ODTLoff - ODTLon + tDQSCK - tODTon,min + PCB delay (out+in) + tPHY_ODToff */ + dbsc_write_32(DBSC_DBTR(11), + RL + (16 / 2) + 1 + 2 - js1[js1_ind].ODTLon + js2[JS2_tDQSCK] - js2[JS2_tODTon_min] + _f_scale(ddr_mbps, ddr_mbpsdiv, (1500 + 500 + 800), 0)); + + /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */ + dataL = WL + 1 + (16 / 2) + js2[JS2_tWTR]; + dbsc_write_32(DBSC_DBTR(12), (dataL << 16) | dataL); + + /* DBTR13.TRFCAB : tRFCab */ + dbsc_write_32(DBSC_DBTR(13), + (js2[JS2_tRFCab])); + + /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */ + dbsc_write_32(DBSC_DBTR(14), + ((js2[JS2_tCKEHCMD] + 3U) << 16) | (js2[JS2_tCKEHCMD] + 3U)); + + /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */ + dbsc_write_32(DBSC_DBTR(15), + (js2[JS2_tSR] << 16) | (js2[JS2_tCKELPD])); + + /* DBTR16 */ + tmp[0] = WL; + tmp[1] = WL - 4U; + tmp[2] = RL + 33U + 2U; + tmp[3] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1U; + dbsc_write_32(DBSC_DBTR(16), + (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR24 */ + /* WRCSLAT */ + tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1) - 5U; + /* WRCSGAP = 6 + 1 */ + tmp[1] = 7U; + /* RDCSLAT */ + tmp[2] = RL - 6U; + /* RDCSGAP */ + tmp[3] = 4U + 2U; + dbsc_write_32(DBSC_DBTR(24), + (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0)*/ + dbsc_write_32(DBSC_DBTR(17), (js2[JS2_tMRR] << 24) | (js2[JS2_tMRD] << 16)); + + /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */ + dbsc_write_32(DBSC_DBTR(18), 0U); + + /* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */ + dbsc_write_32(DBSC_DBTR(19), 0U); + + /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */ + dataL = js2[JS2_tRFCab] + js2[JS2_tCKEHCMD] + 3U; + dbsc_write_32(DBSC_DBTR(20), (dataL << 16) | dataL); + + /* DBTR21.TCCD */ + dbsc_write_32(DBSC_DBTR(21), (ddr_tccd << 16) | ddr_tccd); + + /* DBTR22.ZQLAT : */ + dbsc_write_32(DBSC_DBTR(22), (js2[JS2_tZQCALns] << 16) | js2[JS2_tZQLAT]); + + /* DBTR23.RRSPC */ + dbsc_write_32(DBSC_DBTR(23), 0x00000003U); + + /* DBTR25 : do not use in LPDDR4 */ + dbsc_write_32(DBSC_DBTR(25), 0U); + + /* DBRNK : */ + /* DBSC_DBRNK2 rkrr */ + dbsc_write_32(DBSC_DBRNK(2), 0x000000CC); + + /* DBSC_DBRNK3 rkrw */ + dbsc_write_32(DBSC_DBRNK(3), 0x00000066); + + /* DBSC_DBRNK4 rkwr */ + dbsc_write_32(DBSC_DBRNK(4), 0x00000066); + + /* DBSC_DBRNK5 rkww */ + dbsc_write_32(DBSC_DBRNK(5), 0x000000CC); + + /*********************************************************************** + * timing registers for Scheduler + ***********************************************************************/ + /* SCFCTST0 */ + /* SCFCTST0 ACT-ACT*/ + tmp[3] = 1UL * js2[JS2_tRCpb] * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + /* SCFCTST0 RDA-ACT*/ + tmp[2] = 1UL * ((16U / 2U) + js2[JS2_tRTP] - 8U + js2[JS2_tRPpb]) * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + /* SCFCTST0 WRA-ACT*/ + tmp[1] = 1UL * (WL + 1U + (16U / 2U) + js1[js1_ind].nWR) * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + /* SCFCTST0 PRE-ACT*/ + tmp[0] = 1UL * js2[JS2_tRPpb] * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + dbsc_write_32(DBSC_SCFCTST0, (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* SCFCTST1 */ + /* SCFCTST1 RD-WR*/ + tmp[3] = 1UL * (mmio_read_32(DBSC_DBTR(11)) & 0xffU) * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + /* SCFCTST1 WR-RD*/ + tmp[2] = 1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xffU) * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + /* SCFCTST1 ACT-RD/WR*/ + tmp[1] = 1UL * js2[JS2_tRCD] * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + /* SCFCTST1 ASYNCOFS*/ + tmp[0] = 12U; + dbsc_write_32(DBSC_SCFCTST1, (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBSCHRW1 */ + /* DBSCHRW1 SCTRFCAB*/ + tmp[0] = 1UL * js2[JS2_tRFCab] * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv; + dataL =(((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000U) >> 16) + + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFFU) + + (0x28U * 2U)) * bus_mbps * ddr_mbpsdiv / ddr_mbps / bus_mbpsdiv + 7U; + if (tmp[0] < dataL) { + tmp[0] = dataL; + } + dbsc_write_32(DBSC_DBSCHRW1, tmp[0] + + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF) + * bus_mbps * ddr_mbpsdiv + (ddr_mbps - 1U)) / ddr_mbps / bus_mbpsdiv); + + /*********************************************************************** + * QOS and CAM + ***********************************************************************/ + dbsc_write_32(DBSC_DBBCAMDIS, 0x00000001U); +} + +static void dbsc_regset_post(void) +{ + uint32_t dataL; + +#if RCAR_REWT_TRAINING != 0 + uint32_t ctrl_clk; + uint32_t clk_count; + uint32_t phymster_req_interval; +#endif /* RCAR_REWT_TRAINING */ + + /*set DBI */ + dbsc_write_32(DBSC_DBDBICNT, 0x00000003U); + + /*set REFCYCLE */ + dataL = DBSC_REFINT * ddr_mbps / 2000U / ddr_mbpsdiv; + dbsc_write_32(DBSC_DBRFCNF1, 0x00080000U | (dataL & 0x0000ffffU)); + dbsc_write_32(DBSC_DBRFCNF2, 0x00010000U | DBSC_REFINTS); + +#if RCAR_REWT_TRAINING != 0 + /* Periodic-WriteDQ Training seeting */ + dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000U); + + ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x03U); + ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00U); + ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01U); + + /* DFI_PHYMSTR_ACK , WTmode = b'01 */ + dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011U); +#endif /* RCAR_REWT_TRAINING */ + + /* PCLK */ + if (ddr_mbps < 4 * 640 * ddr_mbpsdiv) { + ddr_setval_ach(_reg_PHY_PAD_CAL_IO_CFG_0, 0x05U); + } else { + ddr_setval_ach(_reg_PHY_PAD_CAL_IO_CFG_0, 0x06U); + } + + /* periodic SoC zqcal enable */ + ddr_setval_ach(_reg_PHY_CAL_MODE_0, ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_CAL_MODE_0) | 0x02U); + + /* periodic dram zqcal enable */ + dbsc_write_32(DBSC_DBCALCNF, 0x01000010U); + + /* periodic phy ctrl update enable */ + dbsc_write_32(DBSC_DBDFICUPDCNF, 0x504C0001U); + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) { + /* SRX */ + send_dbcmd(0x0A840001U); + } +#endif /* DDR_BACKUPMODE */ + /* set Auto Refresh */ + dbsc_write_32(DBSC_DBRFEN, 0x00000001U); + +#if RCAR_REWT_TRAINING != 0 + /* Periodic WriteDQ Training */ + clk_count = 1024U - ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_LONG_COUNT_MASK) * 32U; + ctrl_clk = ddr_mbps / ddr_mbpsdiv / 4U; + dataL = clk_count * (1000U * 1000U * 1000U / (1000U * ctrl_clk)); + + phymster_req_interval = REWT_TRAINING_INTERVAL - 3000; + + ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, phymster_req_interval * 1000U * 100U / (dataL / 10U) ); +#endif /* RCAR_REWT_TRAINING */ + + /* dram access enable */ + dbsc_write_32(DBSC_DBACEN, 0x00000001U); + + /* MR13: vrcg(normal mode) */ + send_dbcmd(0x0e840dc0U); + + MSG_LF("dbsc_regset_post(done)\n"); +} + +/******************************************************************************* + * DFI_INIT_START + ******************************************************************************/ +static uint32_t dfi_init_start(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + const uint32_t RETRY_MAX = 0x10000U; + + /*********************************************************************** + * init start + ***********************************************************************/ + pll3_control(0U); /* Low frequency mode */ + /* dbdficnt0: + * dfi_dram_clk_disable=1 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start =0 + */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10U); + } + + /* dbdficnt0: + * dfi_dram_clk_disable=1 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start =1 + */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11U); + } + + wait_dbpdstat1(0x03U); + + /*********************************************************************** + * dll rst + ***********************************************************************/ + /* dll_rst negate */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01U); + } + + /*********************************************************************** + * wait init_complete + ***********************************************************************/ + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) { + foreach_vch(ch) { + dataL = mmio_read_32(DBSC_DBDFISTAT(ch)); + if (dataL & 0x00000001U) { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) { + break; + } + } + + /*********************************************************************** + * all ch ok? + ***********************************************************************/ + if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) { + return (phytrainingok); + } + /* dbdficnt0: + * dfi_dram_clk_disable=0 + * dfi_frequency = 0 + * freq_ratio = 01 (2:1) + * init_start =0 + */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010U); + } + + return (phytrainingok); +} + +/******************************************************************************* + * DDR mode register setting + ******************************************************************************/ +static void ddr_register_set(void) +{ + int32_t fspwp; + uint32_t tmp; + + for (fspwp = 0U; fspwp < 2U; fspwp++) { + /* MR13: fspop,fspwp */ + send_dbcmd(0x0e840d08U | ((2U - fspwp) << 6)); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR1_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840100U | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR2_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840200U | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840300U | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR11_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840b00U | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR12_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840c00U | tmp); + + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR14_DATA_Fx_CSx[fspwp][0]); + send_dbcmd(0x0e840e00U | tmp); + + /* MR22 */ + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR22_DATA_F0_0); + send_dbcmd(0x0e801600U | tmp); + + if (ch_have_this_cs[1]) { + tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR22_DATA_F0_1); + send_dbcmd(0x0e811600U | tmp); + } + + /* ZQCAL start */ + send_dbcmd(0x0d84004fU); + + /* ZQLAT */ + send_dbcmd(0x0d840051U); + } + + /* MR13, fspwp */ + send_dbcmd(0x0e840d08U); +} + +/******************************************************************************* + * Training handshake functions + ******************************************************************************/ +static void wait_dbpdstat1(uint32_t status) +{ + uint32_t i, ch, dataL; + + for (i = 0U; i < 2U; i++) { + do { + dataL = status; + foreach_vch(ch) { + dataL &= mmio_read_32(DBSC_DBPDSTAT1(ch)); + } + } while (dataL != status); + } +} + +static uint32_t wait_freqchgreq(uint32_t req_assert) +{ + uint32_t dataL; + uint32_t count; + uint32_t ch; + + count = 0xFFFFFFU; + + if (req_assert) { + do { + dataL = 1U; + foreach_vch(ch) { + dataL &= mmio_read_32(DBSC_DBPDSTAT(ch)); + } + count = count - 1U; + } while (((dataL & 0x01U) != 0x01U) & (count != 0U)); + } else { + do { + dataL = 0U; + foreach_vch(ch) { + dataL |= mmio_read_32(DBSC_DBPDSTAT(ch)); + } + count = count - 1U; + } while (((dataL & 0x01U) != 0x00U) & (count != 0U)); + } + + return (count == 0U); +} + +static void set_freqchgack(uint32_t ackassert) +{ + uint32_t ch; + uint32_t dataL; + + if (ackassert) { + dataL = 0x0000CF01U; + } else { + dataL = 0x00000000U; + } + + foreach_vch(ch) { + mmio_write_32(DBSC_DBPDCNT2(ch), dataL); + } +} + +static void set_dfifrequency(uint32_t freq) +{ + uint32_t ch; + + foreach_vch(ch) { + mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24, (freq << 24)); + } +} + +static uint32_t pll3_freq(uint32_t fsel) +{ + uint32_t timeout; + + wait_freqchgreq(1); + + if (fsel == 0U) { + pll3_control(0); /* Low frequency mode */ + } else { + pll3_control(1); /* High frequency mode */ + } + + set_dfifrequency(fsel); + set_freqchgack(1); + + timeout = wait_freqchgreq(0); + set_freqchgack(0); + + wait_dbpdstat1(0x03U); + + if (timeout) { + FATAL_MSG("BL2: Time out[2]\n"); + return (1); + } + return (0); +} + +/******************************************************************************* + * training by pi + ******************************************************************************/ +static uint32_t pi_training_go(void) +{ + uint32_t flag; + uint32_t dataL; + uint32_t retry; + const uint32_t RETRY_MAX = 4096 * 16; + uint32_t ch; + + uint32_t mst_ch; + uint32_t cur_frq; + uint32_t complete; + uint32_t frqchg_req; + + /*********************************************************************** + * pi_start + ***********************************************************************/ + foreach_vch(ch) { + while((ddr_getval(ch, _reg_PI_INT_STATUS)) != 0U); + } + + foreach_vch(ch) { + mmio_write_32(DBSC_DBPDRGA(ch), DDR_REGDEF_ADR(_reg_PI_START)); + mmio_write_32(DBSC_DBPDRGD(ch), 0x00000B01U); + } + + foreach_vch(ch) { + while((mmio_read_32(DBSC_DBPDRGA(ch)) & 0x00008000U) == 0U); + mmio_write_32(DBSC_DBPDRGA(ch), mmio_read_32(DBSC_DBPDRGA(ch))); + } + + /* set dfi_phymstr_ack = 1 */ + dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001U); + + /*********************************************************************** + * wait pi_int_status[0] + ***********************************************************************/ + flag = 0U; + complete = 0U; + cur_frq = 0U; + retry = RETRY_MAX; + + do { + for (frqchg_req = 0U, ch = 0U; ch < DRAM_CH_CNT; ch++) { + if (((~complete) & ddr_phyvalid) & (1U << ch)) { + if (mmio_read_32(DBSC_DBPDSTAT(ch)) & 0x01U) { + frqchg_req = 1U; + mst_ch = ch; + break; + } + } + } + + if (frqchg_req) { + cur_frq = (0x0300U & mmio_read_32(DBSC_DBPDSTAT(mst_ch))) >> 8; + flag = pll3_freq(cur_frq); + if (flag) { + break; + } + } else { + foreach_vch(ch) { + if (complete & (1U << ch)) { + continue; + } + mmio_write_32(DBSC_DBPDRGA(ch), DDR_REGDEF_ADR(_reg_PI_INT_STATUS) | 0x00004000U); + if (0x00008000U & mmio_read_32(DBSC_DBPDRGA(ch))) { + mmio_write_32(DBSC_DBPDRGA(ch), DDR_REGDEF_ADR(_reg_PI_INT_STATUS) | 0x00008000U); + dataL = mmio_read_32(DBSC_DBPDRGD(ch)); + mmio_write_32(DBSC_DBPDRGA(ch), DDR_REGDEF_ADR(_reg_PI_INT_STATUS) | 0x00000000U); + if (dataL & 0x01U) { + complete |= (1U << ch); + } + } + } + if (complete == ddr_phyvalid) { + break; + } + } + } while (--retry); + + foreach_vch(ch) { + /* dummy read */ + dataL = ddr_getval(ch, _reg_PI_START); + dataL = ddr_getval(ch, _reg_PI_INT_STATUS); + ddr_setval(ch, _reg_PI_INT_ACK, dataL); + } + + return complete; +} + +static void manual_frequency_change(void) +{ + uint32_t ch; + + /* FSP-OP:1 FSP-WR:1 VRCG:1 */ + send_dbcmd(0x0e840dc8U); + + /* PDE */ + send_dbcmd(0x08840000U); + + /* init start ass */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBDFICNT(ch), 0x01000011U); + } + + /* wait init comp neg */ + foreach_vch(ch) { + while((mmio_read_32(DBSC_DBDFISTAT(ch)) & 0x00000001U) != 0U); + } + + pll3_control(1); + + /* init start neg */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBDFICNT(ch), 0x01000010U); + } + + /* wait init comp ass */ + foreach_vch(ch) { + while((mmio_read_32(DBSC_DBDFISTAT(ch)) & 0x00000001U) != 1U); + } + + /* PDX */ + send_dbcmd(0x08840001U); + + /* set MR13 for FSP */ + ddr_setval_ach(_reg_PI_MR13_DATA_0, 0xc8U); + ddr_setval_ach(_reg_PI_MR13_DATA_1, 0xc8U); +} + +static uint32_t manual_training_wrlvl(void) +{ + uint32_t dataL; + uint32_t ch, cs, rank; + uint32_t wr_training_ng; + + if (ch_have_this_cs[1] != 0) { + rank = 2; + } else { + rank = 1; + } + + /* WR LVL */ + wr_training_ng = 0x00U; + + for(cs = 0; rank > cs; cs++) { + ddr_setval_ach(_reg_PI_WRLVL_CS, cs); + ddr_setval_ach(_reg_PI_WRLVL_REQ, 0x1U); + + foreach_vch(ch) { + while(1) { + dataL = ddr_getval(ch, _reg_PI_INT_STATUS); + if(dataL & 0x00001000U) break; + } + } + foreach_vch(ch) { + if (ddr_getval(ch, _reg_PHY_WRLVL_STATUS_OBS) & ( 1U << 12 )) { /* bit12 wrlvl_error */ + wr_training_ng |= 1U << ch; + } + } + ddr_setval_ach(_reg_PI_INT_ACK, 0x3FFFFFU); + } + return ~wr_training_ng; +} + +static uint32_t manual_training_rdgtlvl(void) +{ + uint32_t dataL; + uint32_t ch, cs, rank; + uint32_t gt_training_ng; + + if (ch_have_this_cs[1] != 0) { + rank = 2; + } else { + rank = 1; + } + + /* RD GATE LVL */ + gt_training_ng = 0x00U; + + for(cs = 0; rank > cs; cs++) { + ddr_setval_ach(_reg_PI_RDLVL_CS, cs); + ddr_setval_ach(_reg_PI_RDLVL_GATE_REQ, 0x1U); + + foreach_vch(ch) { + while(1) { + dataL = ddr_getval(ch, _reg_PI_INT_STATUS); + if(dataL & 0x00001000U) break; + } + } + foreach_vch(ch) { + if (ddr_getval(ch, _reg_PHY_GTLVL_STATUS_OBS) & ( 3U << 6 )) { /* bit6 Minimum delay setup error, bit7 Maximum delay setup error */ + gt_training_ng |= 1U << ch; + } + } + ddr_setval_ach(_reg_PI_INT_ACK, 0x3FFFFFU); + } + return ~gt_training_ng; +} + +static uint32_t manual_training_rdlvl(void) +{ + uint32_t dataL; + uint32_t ch, cs, rank; + uint32_t rd_training_ng; + + if (ch_have_this_cs[1] != 0) { + rank = 2; + } else { + rank = 1; + } + + /* RD LVL */ + rd_training_ng = 0x00U; + + for(cs = 0; rank > cs; cs++) { + ddr_setval_ach(_reg_PI_RDLVL_CS, cs); + ddr_setval_ach(_reg_PI_RDLVL_REQ, 0x1U); + + foreach_vch(ch) { + while(1) { + dataL = ddr_getval(ch, _reg_PI_INT_STATUS); + if(dataL & 0x00001000U) break; + } + } + foreach_vch(ch) { + if (ddr_getval(ch, _reg_PI_INT_STATUS) & ( 1U << 1 )) { /* bit1 PI_RDLVL_ERROR_BIT */ + rd_training_ng |= 1U << ch; + } + } + ddr_setval_ach(_reg_PI_INT_ACK, 0x3FFFFFU); + } + return ~rd_training_ng; +} + +static uint32_t manual_training_wdqlvl(void) +{ + uint32_t dataL; + uint32_t ch, cs, rank; + uint32_t wdq_training_ng; + + if (ch_have_this_cs[1] != 0) { + rank = 2; + } else { + rank = 1; + } + + /* WDQ LVL */ + wdq_training_ng = 0x00U; + + for(cs = 0; rank > cs; cs++) { + ddr_setval_ach(_reg_PI_WDQLVL_CS, cs); + ddr_setval_ach(_reg_PI_WDQLVL_REQ, 0x1U); + + foreach_vch(ch) { + while(1) { + dataL = ddr_getval(ch, _reg_PI_INT_STATUS); + if(dataL & 0x00001000U) break; + } + } + foreach_vch(ch) { + if (ddr_getval(ch, _reg_PI_INT_STATUS) & ( 1U << 5 )) { /* bit5 PI_WDQLVL_ERROR_BIT */ + wdq_training_ng |= 1U << ch; + } + } + ddr_setval_ach(_reg_PI_INT_ACK, 0x3FFFFFU); + } + return ~wdq_training_ng; +} + +/*********************************************************************** + * CA Vref Training + ***********************************************************************/ +static uint32_t ca_vref_training(void) +{ + uint32_t dvw, dvw_tmp[DRAM_CH_CNT][CS_CNT]; + uint32_t cavref, cavref_set_min[DRAM_CH_CNT][CS_CNT], cavref_set_max[DRAM_CH_CNT][CS_CNT]; + uint32_t ch, cs, rank; + uint32_t i, dataL, tmp; + uint32_t vref_start, vref_end; + uint32_t ca_training_ng; + + foreach_ech(ch) { + for (cs = 0; CS_CNT > cs; cs++) { + dvw_tmp[ch][cs] = 0x0000U; + cavref_set_min[ch][cs] = 0x0000U; + cavref_set_max[ch][cs] = 0x0000U; + } + } + + /*********************************************************************** + * CA Vref (MR12) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->vref_ca); + if (dataL) { + vref_start = dataL & 0x00ffU; + vref_end = (dataL & 0xff00U) >> 8; + } else { + vref_start = 0x000eU; + vref_end = 0x0014U; + } + + /*********************************************************************** + * CA training setting + ***********************************************************************/ + ddr_setval_ach(_reg_PI_MR13_DATA_0, 0xc8U); + ddr_setval_ach(_reg_PI_MR13_DATA_1, 0xc8U); + + ddr_setval_ach(_reg_PI_CA_TRAIN_VREF_EN, 0x0001U); + + if (ch_have_this_cs[1] != 0) { + rank = 2; + } else { + rank = 1; + } + + /*********************************************************************** + * Search Best CA VREF + ***********************************************************************/ + for(cs =0; rank > cs; cs++) { + for (cavref = vref_start; cavref <= vref_end; cavref += DDR_CAVREF_DELTA) { + ddr_setval_ach(_reg_PI_CALVL_CS, cs); + if (cs) { + ddr_setval_ach(_reg_PI_MR12_DATA_F1_1, cavref); + } else { + ddr_setval_ach(_reg_PI_MR12_DATA_F1_0, cavref); + } + ddr_setval_ach(_reg_PI_CALVL_REQ, 0x0001U); + + dataL = 0x00U; + while(dataL == 0x00U) { + dataL = 0x01U << 19; + foreach_vch(ch) { + dataL &= (ddr_getval(ch, _reg_PI_INT_STATUS)); + } + } + + foreach_vch(ch) { + if((0x00000010U & ddr_getval(ch, _reg_PI_INT_STATUS)) == 0x00000000U) { + dvw = 0x0000ffffU; + for (i = 0; i < 6; i++){ + ddr_setval(ch, _reg_PHY_ADR_CALVL_OBS_SELECT_0, i); + dataL = ddr_getval(ch, _reg_PHY_ADR_CALVL_CH0_OBS0_0); + tmp = (dataL & 0x000007ffU) - ((dataL >> 16) & 0x000007ffU); + if(dvw > tmp) { + dvw = tmp; + } + } + + if(dvw_tmp[ch][cs] < dvw) { + dvw_tmp[ch][cs] = dvw; + cavref_set_min[ch][cs] = cavref; + cavref_set_max[ch][cs] = cavref; + } else if (dvw_tmp[ch][cs] == dvw) { + cavref_set_max[ch][cs] = cavref; + } + } + ddr_setval(ch, _reg_PI_INT_ACK, ddr_getval(ch, _reg_PI_INT_STATUS)); + } + } + } + + /*********************************************************************** + * Use the Best CA VREF to do CA training + ***********************************************************************/ + if (rank == 2) { + ddr_setval_ach(_reg_PHY_ADR_CALVL_RANK_CTRL_0, 0x03U); + } + + foreach_vch(ch) { + ddr_setval(ch, _reg_PI_MR12_DATA_F1_0, (cavref_set_min[ch][0] + cavref_set_max[ch][0]) / 2); + ddr_setval(ch, _reg_PI_MR12_DATA_F1_1, (cavref_set_min[ch][rank - 1] + cavref_set_max[ch][rank - 1]) / 2); + } + + ca_training_ng = 0x00U; + for(cs = 0; rank > cs; cs++) { + ddr_setval_ach(_reg_PI_CALVL_CS, cs); + ddr_setval_ach(_reg_PI_CALVL_REQ, 0x0001U); + + dataL = 0x00U; + while(dataL == 0x00U) { + dataL = 0x01U << 19; + foreach_vch(ch) { + dataL &= (ddr_getval(ch, _reg_PI_INT_STATUS)); + } + } + + foreach_vch(ch) { + if (ddr_getval(ch, _reg_PHY_CSLVL_OBS1) & 0xF0000000U) { + ca_training_ng |= 1U << ch; + } + ddr_setval(ch, _reg_PI_INT_ACK, ddr_getval(ch, _reg_PI_INT_STATUS)); + } + } + + ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01U); + ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01U); + + return ~ca_training_ng; +} + +/******************************************************************************* + * DSKEWCALLOCK status check + ******************************************************************************/ +static uint32_t dskewcallock_chk(void) +{ + uint32_t ch; + uint32_t dataL; + uint32_t dskewcallock_ok; + + ddr_setval_ach(_reg_SC_PHY_PLL_SPO_CAL_SNAP_OBS, 0x01U); + + dskewcallock_ok = 0U; + foreach_ech(ch) { + dataL = 0x01U & (ddr_getval(ch, _reg_PHY_PLL_SPO_CAL_OBS_0) >> 16); + dataL &= 0x01U & (ddr_getval(ch, _reg_PHY_PLL_SPO_CAL_OBS_1) >> 16); + dskewcallock_ok |= dataL << ch; + } + + return dskewcallock_ok; +} + +/******************************************************************************* + * Initialize ddr + ******************************************************************************/ +static uint32_t init_ddr(void) +{ + uint32_t phytrainingok; + uint32_t ch; + uint32_t err; + + MSG_LF("init_ddr:0\n"); +#ifdef DDR_BACKUPMODE + dram_get_boot_status(&ddrBackup); +#endif + + /*********************************************************************** + * PLL3 initialization setting + ***********************************************************************/ + /* Reset Status Monitor clear */ + cpg_write_32(CPG_FSRCHKCLRR4, 0x00000200U); + /* Reset Status Monitor set */ + cpg_write_32(CPG_FSRCHKSETR4, 0x00000200U); + /* ddrphy soft reset assert */ + cpg_write_32(CPG_SRST4, mmio_read_32(CPG_SRST4) | 0x00000200U); + /* wait reset FB */ + while((mmio_read_32(CPG_FSRCHKRA4) & 0x00000200U) != 0U); + /* Reset Status Monitor clear */ + cpg_write_32(CPG_FSRCHKCLRR4, 0x00000200U); + + pll3_control(1); /* Initialize PLL3 setting */ + + /* ddrphy soft reset negate */ + cpg_write_32(CPG_SRSTCLR4, 0x00000200U); + while((mmio_read_32(CPG_SRST4) & 0x00000200U) != 0U); + + /*********************************************************************** + * unlock phy + ***********************************************************************/ + /* Unlock DDRPHY register */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU); + } + + /*********************************************************************** + * dbsc register pre-setting + ***********************************************************************/ + dbsc_regset_pre(); + + /*********************************************************************** + * load ddrphy registers + ***********************************************************************/ + ddrtbl_load(); + + /*********************************************************************** + * configure ddrphy registers + ***********************************************************************/ + ddr_config(); + + /*********************************************************************** + * ddr backupmode end + ***********************************************************************/ +#ifdef DDR_BACKUPMODE + if (ddrBackup) { + NOTICE("BL2: [WARM_BOOT]\n"); + } else { + NOTICE("BL2: [COLD_BOOT]\n"); + } + + err = dram_update_boot_status(ddrBackup); + if (err) { + NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); + return INITDRAM_ERR_I; + } +#endif + MSG_LF("init_ddr:1\n"); + + /*********************************************************************** + * dfi_init_start (start ddrphy) + ***********************************************************************/ + phytrainingok = dfi_init_start(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:1\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:2\n"); + + /*********************************************************************** + * load pi registers + ***********************************************************************/ + ddrtbl_load_pi(); + + /*********************************************************************** + * dbsc register set + ***********************************************************************/ + dbsc_regset(); + MSG_LF("init_ddr:3\n"); + + /*********************************************************************** + * setup DDR mode registers + ***********************************************************************/ + /* Dummy PDE */ + send_dbcmd(0x08840000U); + + /* PDX */ + send_dbcmd(0x08840001U); + + /* MRS */ + ddr_register_set(); + + MSG_LF("init_ddr:4\n"); + + /*********************************************************************** + * exec pi_training + ***********************************************************************/ + phytrainingok &= pi_training_go(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:2\n"); + return (phytrainingok); + } + + /*********************************************************************** + * exec frequency change + ***********************************************************************/ + manual_frequency_change(); + + /*********************************************************************** + * CA Vref Training + ***********************************************************************/ + phytrainingok &= ca_vref_training(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:3\n"); + return (phytrainingok); + } + + /*********************************************************************** + * exec wr_training + ***********************************************************************/ + phytrainingok &= manual_training_wrlvl(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:4\n"); + return (phytrainingok); + } + + /*********************************************************************** + * exec rdgt_training + ***********************************************************************/ + phytrainingok &= manual_training_rdgtlvl(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:5\n"); + return (phytrainingok); + } + + /*********************************************************************** + * exec rd_training + ***********************************************************************/ + phytrainingok &= manual_training_rdlvl(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:6\n"); + return (phytrainingok); + } + + /*********************************************************************** + * exec wdq_training + ***********************************************************************/ + phytrainingok &= manual_training_wdqlvl(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:7\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:5\n"); + + /*********************************************************************** + * FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (disable) + ***********************************************************************/ + ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U); + ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x00U); + + MSG_LF("init_ddr:6\n"); + + /*********************************************************************** + * DSKEWCALLOCK status check + ***********************************************************************/ + phytrainingok &= dskewcallock_chk(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:8\n"); + return (phytrainingok); + } + + /*********************************************************************** + * training complete, setup dbsc + ***********************************************************************/ + dbsc_regset_post(); + MSG_LF("init_ddr:7\n"); + + /*********************************************************************** + * lock phy + ***********************************************************************/ + /* Lock DDRPHY register */ + foreach_vch(ch) { + mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U); + } + + return phytrainingok; +} + +/******************************************************************************* + * DDR Initialize entry + ******************************************************************************/ +int32_t InitDram(void) +{ + uint32_t ch, cs; + uint32_t dataL; + uint32_t failcount; + + dbsc_write_32(DBSC_DBSYSCNT0, 0x00001234U); + dbsc_write_32(DBSC_DBSYSCNT0A, 0x00001234U); + + /*********************************************************************** + * Judge product and cut + ***********************************************************************/ +/* + Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; +*/ + /*********************************************************************** + * Judge board type + ***********************************************************************/ + _cnf_BOARDTYPE = boardcnf_get_brd_type(); + if (_cnf_BOARDTYPE >= BOARDNUM) { + FATAL_MSG("BL2: DDR:Unknown Board\n"); + return 0xffU; + } + Boardcnf = (const struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE]; + + ddr_phyvalid = (uint32_t)(Boardcnf->phyvalid); + + max_density = 0U; + + for (cs = 0U; cs < CS_CNT; cs++) { + ch_have_this_cs[cs] = 0U; + } + + foreach_ech(ch) { + for (cs = 0U; cs < CS_CNT; cs++) { + ddr_density[ch][cs] = 0xffU; + } + } + + foreach_vch(ch) { + for (cs = 0U; cs < CS_CNT; cs++) { + dataL = (uint32_t)(Boardcnf->ch[ch].ddr_density[cs]); + ddr_density[ch][cs] = dataL; + if (dataL == 0xffU) { + continue; + } + if (dataL > max_density) { + max_density = dataL; + } + ch_have_this_cs[cs] |= (1U << ch); + } + } + + /*********************************************************************** + * Judge board clock frequency (in MHz) + ***********************************************************************/ + boardcnf_get_brd_clk(_cnf_BOARDTYPE, &brd_clk, &brd_clkdiv); + if ((0x01U << 14) & mmio_read_32(RST_MODEMR0)) { + brd_clkdiva = 1U; + } else { + brd_clkdiva = 0U; + } + + /*********************************************************************** + * Judge ddr operating frequency clock(in Mbps) + ***********************************************************************/ + boardcnf_get_ddr_mbps(_cnf_BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv); + + ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv, brd_clk, brd_clkdiv * (brd_clkdiva + 1U)); + ddr_mul_nf = (16U * ddr_mbps * (brd_clkdiv * (brd_clkdiva + 1U))) / (ddr_mbpsdiv * brd_clk) - (16U * ddr_mul); + ddr_mul_low = CLK_DIV(1600U, 1U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U)); + if((ddr_mul_low * brd_clk / (brd_clkdiv * (brd_clkdiva + 1U))) != 1600U) { + ddr_mul_low += 1; + } + + dataL = 0x03U & (mmio_read_32(RST_MODEMR0) >> 13); + bus_mbps = 0U; + bus_mbpsdiv = 0U; + + switch (dataL) { + case 0U: + bus_mbps = brd_clk * 0x32U; + bus_mbpsdiv = brd_clkdiv; + break; + case 1U: + bus_mbps = brd_clk * 0x28U; + bus_mbpsdiv = brd_clkdiv; + break; + case 2U: + /* Not supported */ + bus_mbps = brd_clk * 0x40U; + bus_mbpsdiv = brd_clkdiv * 2U; + break; + case 3U: + bus_mbps = brd_clk * 0x28U; + bus_mbpsdiv = brd_clkdiv * 2U; + break; + default: + bus_mbps = brd_clk * 0x28U; + bus_mbpsdiv = brd_clkdiv * 2U; + break; + } + + /*********************************************************************** + * Adjust tccd + ***********************************************************************/ + ddr_tccd = 8U; + + NOTICE("BL2: DDR%d(%s)", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); + + MSG_LF("Start\n"); + + /*********************************************************************** + * initialize DDR + ***********************************************************************/ + dataL = init_ddr(); + if (dataL == ddr_phyvalid) { + failcount = 0U; + } else { + failcount = 1U; + } + + NOTICE("..%d\n", failcount); + + dbsc_write_32(DBSC_DBSYSCNT0, 0x00000000U); + dbsc_write_32(DBSC_DBSYSCNT0A, 0x00000000U); + + if (failcount == 0U) { + return INITDRAM_OK; + } else { + return INITDRAM_NG; + } +} + +/******************************************************************************* + * END + ******************************************************************************/ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.c new file mode 100644 index 0000000..b837191 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.c @@ -0,0 +1,254 @@ +/******************************************************************************* + * Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DRAM Param setting + ******************************************************************************/ +#define JS2_DERATE 0 +#define DBSC_REFINT 1920 /* Average periodic refresh interval/Average Refresh Interval [ns] */ +#define DBSC_REFINTS 0 /* 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. */ + +#define REWT_TRAINING_INTERVAL 20000 /* Periodic-WriteDQ Training Interval [us] */ + +/******************************************************************************* + * NUMBER OF BOARD CONFIGRATION + * PLEASE DEFINE + ******************************************************************************/ +#define BOARDNUM 3 /* Add User platform BOARD */ + +/******************************************************************************* + * PLEASE SET board number or board judge function + ******************************************************************************/ +#define BOARD_JUDGE_AUTO +#ifdef BOARD_JUDGE_AUTO +static uint32_t _board_judge(void); +static uint32_t boardcnf_get_brd_type(void) { + return _board_judge(); +} +#else /* BOARD_JUDGE_AUTO */ +static uint32_t boardcnf_get_brd_type(void) { + return (0); +} +#endif /* BOARD_JUDGE_AUTO */ + +/******************************************************************************* + * BOARD CONFIGRATION + * PLEASE DEFINE boardcnfs[] + ******************************************************************************/ +struct _boardcnf_ch { + /* + 0x00...0000B: 4Gb dual channel die / 2Gb single channel die + 0x01...0001B: 6Gb dual channel die / 3Gb single channel die + 0x02...0010B: 8Gb dual channel die / 4Gb single channel die + 0x03...0011B: 12Gb dual channel die / 6Gb single channel die + 0x04...0100B: 16Gb dual channel die / 8Gb single channel die + 0xff...NO_MEMORY + */ + uint8_t ddr_density[CS_CNT]; + /* SoC caX([5][4][3][2][1][0]) -> MEM caY: */ + uint32_t ca_swap; + /* SoC dqsX([3][2][1][0]) -> MEM dqsY: */ + uint16_t dqs_swap; + /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ + uint32_t dq_swap[SLICE_CNT]; + /* SoC dm -> MEM dqY/dm: (8 means DM) */ + uint8_t dm_swap[SLICE_CNT]; +}; + +struct _boardcnf { + /* ch in use */ + uint16_t phyvalid; + /* Read vref (SoC) training range : [15:8]stop / [7:0]start, 0x0000 = default val */ + uint16_t vref_r; + /* Write vref (MR14) training range : [15:8]stop / [7:0]start, 0x0000 = default val */ + uint16_t vref_w; + /* CA vref (MR12) training range : [15:8]stop / [7:0]start, 0x0000 = default val */ + uint16_t vref_ca; + + struct _boardcnf_ch ch[2]; +}; + +static const struct _boardcnf boardcnfs[BOARDNUM] = { +/* + * boardcnf[0] RENESAS S4 Spider (16Gbit 2rank) + */ +{ + 0x03, /* phyvalid */ + 0x0000, /* vref_r */ + 0x0000, /* vref_w */ + 0x0000, /* vref_ca */ + { +/* ch[0] */ { /* M0CAxB/M0DQ[23:16],M0DQ[31:24] */ +/* ddr_density[] */ { 0x04, 0x04 }, +/* ca_swap */ 0x243510U, +/* dqs_swap */ 0x10, +/* dq_swap[] */ { 0x21706345, 0x23510746 }, +/* dm_swap[] */ { 0x08, 0x08 } + }, +/* ch[1] */ { /* M0CAxA/M0DQ[15: 0] */ +/* ddr_density[] */ { 0x04, 0x04 }, +/* ca_swap */ 0x345210U, +/* dqs_swap */ 0x10, +/* dq_swap[] */ { 0x30124675, 0x53126047 }, +/* dm_swap[] */ { 0x08, 0x08 } + } + } +}, +/* + * boardcnf[1] RENESAS S4-N Spider (16Gbit 2rank) + */ +{ + 0x03, /* phyvalid */ + 0x0000, /* vref_r */ + 0x0000, /* vref_w */ + 0x0000, /* vref_ca */ + { +/* ch[0] */ { /* M0CAxB/M0DQ[23:16],M0DQ[31:24] */ +/* ddr_density[] */ { 0x04, 0x04 }, +/* ca_swap */ 0x243510U, +/* dqs_swap */ 0x10, +/* dq_swap[] */ { 0x21705634, 0x23516048 }, +/* dm_swap[] */ { 0x08, 0x07 } + }, +/* ch[1] */ { /* M0CAxA/M0DQ[15: 0] */ +/* ddr_density[] */ { 0x04, 0x04 }, +/* ca_swap */ 0x345201U, +/* dqs_swap */ 0x10, +/* dq_swap[] */ { 0x03124675, 0x35126047 }, +/* dm_swap[] */ { 0x08, 0x08 } + } + } +}, +/* + * boardcnf[2] RENESAS S4(2ch) + */ +{ + 0x03, /* phyvalid */ + 0x0000, /* vref_r */ + 0x0000, /* vref_w */ + 0x0000, /* vref_ca */ + { +/* ch[0] */ { +/* ddr_density[] */ { 0x04, 0x04 }, +/* ca_swap */ 0x00543210U, +/* dqs_swap */ 0x10, +/* dq_swap[] */ { 0x76543210, 0x76543210 }, +/* dm_swap[] */ { 0x08, 0x08 } + }, +/* ch[1] */ { +/* ddr_density[] */ { 0x04, 0x04 }, +/* ca_swap */ 0x00543210U, +/* dqs_swap */ 0x10, +/* dq_swap[] */ { 0x76543210, 0x76543210 }, +/* dm_swap[] */ { 0x08, 0x08 } + } + } +} +}; + +/******************************************************************************* + * EXTAL CLOCK DEFINITION + * PLEASE DEFINE HOW TO JUDGE BORAD CLK + ******************************************************************************/ +/* + * RENESAS SPIDER BOARD EXAMPLE + * judge by md14/md13 + * + * 16.00MHz CLK,DIV= 48,3 (md14,md13==0,0) + * 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1) + * 40.00MHz CLK,DIV=120,3 (md14,md13==1,1) +*/ +void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div) { + uint32_t md; + + md = (mmio_read_32(RST_MODEMR0) >> 13) & 0x3; + switch(md) { + case 0x0 : *clk = 48; *div = 3; break; /* 48 / 3 = 16.00MHz */ + case 0x1 : *clk = 60; *div = 3; break; /* 60 / 3 = 20.00MHz */ +/* case 0x2 : *clk = 75; *div = 3; break; */ /* Not supported */ + case 0x3 : *clk =120; *div = 3; break; /* 120 / 3 = 40.00MHz */ + } + (void)brd; +} + +/******************************************************************************* + * DDR MBPS TARGET + * PLEASE DEFINE HOW TO JUDGE DDR BPS + ******************************************************************************/ +/* + DDRxxxx (judge by md17) : Mbps + SSCG enable / disable for PLL1 (judge by md37/md36) +*/ +void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div) { + uint32_t md; + uint32_t sscg; + + md = (mmio_read_32(RST_MODEMR0) >> 17) & 0x01U; + sscg = (mmio_read_32(RST_MODEMR1) >> 4) & 0x03U; + + switch(sscg) { + case 0x0 : + switch(md) { + case 0x0 : *mbps = 3200; *div = 1; break; + case 0x1 : *mbps = 2120; *div = 1; break; + } + break; + case 0x1 : + switch(md) { + case 0x0 : *mbps = 3120; *div = 1; break; + case 0x1 : *mbps = 2120; *div = 1; break; + } + break; + case 0x2 : + switch(md) { + case 0x0 : *mbps = 3040; *div = 1; break; + case 0x1 : *mbps = 2120; *div = 1; break; + } + break; + case 0x3 : + switch(md) { + case 0x0 : *mbps = 3000; *div = 1; break; + case 0x1 : *mbps = 2120; *div = 1; break; + } + break; + } + (void)brd; +} + +#ifdef BOARD_JUDGE_AUTO +/******************************************************************************* + * SAMPLE board detect function + ******************************************************************************/ +static uint32_t _board_judge(void) { + uint32_t brd; + + brd = 0; /* spider (16Gbit 2rank)*/ + + return brd; +} +#endif diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.h new file mode 100644 index 0000000..4595f3b --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_config.h @@ -0,0 +1,73 @@ +/******************************************************************************* +* File Name : boot_init_dram_config.h +* Version : 1.0 +* Description : This file containing structure definitions for board settings +******************************************************************************/ + +/***************************************************************************** +* History : Please refer the readme.txt +* +******************************************************************************/ + +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* © 2020-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#ifndef BOOT_INIT_DRAM_CONFIG +#define BOOT_INIT_DRAM_CONFIG + +#include +#include "boot_init_dram_regdef.h" +/******************************************************************************* + * DRAM Param setting + * this parameter is depending on the user + ******************************************************************************/ +#define JS2_DERATE 0 +#define BOARDNUM 5 +#define USE_BOARD 0 + +/******************************************************************************* + * BOARD CONFIGRATION + * PLEASE DEFINE boardcnfs[] + ******************************************************************************/ + +struct board_cfg_t +{ + uint32_t phyvalid; + uint32_t vref_r; + uint32_t vref_w; + uint32_t vref_ca; + + + uint32_t ddr_density[CH_CNT][CS_CNT]; + uint32_t ca_swap[CH_CNT]; + uint32_t dqs_swap[CH_CNT]; + uint32_t dq_swap[CH_CNT][SLICE_CNT]; + uint32_t dm_swap[CH_CNT][SLICE_CNT]; +}; + +void judge_board_clk_freq(uint32_t* board_clk, uint32_t* board_clkdiv, uint32_t* board_clkdiva); +void judge_ddr_ope_freq(uint32_t* ddr_mbps, uint32_t* ddr_mbpsdiv); +void judge_bus_clk_freq(uint32_t* bus_mbps, uint32_t* bus_mbpsdiv, const uint32_t* board_clk, const uint32_t* board_clkdiv); +extern const struct board_cfg_t board_cfg[BOARDNUM]; + +#endif /* BOOT_INIT_DRAM_CONFIG */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_regdef.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_regdef.h new file mode 100644 index 0000000..705a895 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/boot_init_dram_regdef.h @@ -0,0 +1,260 @@ +/******************************************************************************* + * Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +#if defined(__RH850G3K__) +#include "remap_register.h" +#endif + +#define RCAR_DDR_VERSION "rev.0.30rc7" +#define DRAM_CH_CNT 0x02 +#define SLICE_CNT 0x02 +#define CS_CNT 0x02 + +/* for pll setting */ +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) +#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb))) + +/* for ddr density setting */ +#define DBMEMCONF_REG(d3, row, bank, col, dw) (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw)) +#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (28 - 3 - 10 - 1), 3, 10, 1)) /* 16bit */ +#define DBMEMCONF_VAL(ch,cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) + +/* system registers : CPG */ +#define CPG_FRQCRD_KICK_BIT (1U << 31) + +#define CPG_PLL3CR_KICK_BIT (1U << 31) + +#define CPG_PLLECR_PLL3E_BIT (1U << 3) +#define CPG_PLLECR_PLL3ST_BIT (1U << 11) + +#if defined(__RH850G3K__) +#define CPG_BASE (BASE_CPG_ADDR) +#else +#define CPG_BASE (0xE6150000U) +#endif +#define CPG_CPGWPR (CPG_BASE + 0x0000U) +#define CPG_CPGWPCR (CPG_BASE + 0x0004U) +#define CPG_FRQCRA (CPG_BASE + 0x0800U) +#define CPG_FRQCRB (CPG_BASE + 0x0804U) +#define CPG_FRQCRC (CPG_BASE + 0x0808U) +#define CPG_FRQCRD (CPG_BASE + 0x080CU) +#define CPG_PLLECR (CPG_BASE + 0x0820U) +#define CPG_PLL3CR0 (CPG_BASE + 0x083CU) +#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U) +#define CPG_Z0CKKSCR (CPG_BASE + 0x08A8U) +#define CPG_Z1CKKSCR (CPG_BASE + 0x08ACU) +#define CPG_SRST4 (CPG_BASE + 0x2C10U) +#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U) +#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U) +#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U) +#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U) + +#if defined(__RH850G3K__) +#define RST_BASE (BASE_RESET_ADDR) +#else +#define RST_BASE (0xE6160000U) +#endif +#define RST_MODEMR0 (RST_BASE + 0x0000U) +#define RST_MODEMR1 (RST_BASE + 0x0004U) + +/* Product Register */ +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) + +#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */ + +#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */ +#define PRR_PRODUCT_11 (0x00000001U) /* ver 1.1 */ +#define PRR_PRODUCT_12 (0x00000002U) /* ver 1.2 */ + +/* DBSC registers */ +#if defined(__RH850G3K__) +#define DBSC_BASE (BASE_DBSC_ADDR) +#else +#define DBSC_BASE (0xE6790000U) +#endif +#define DBSC_DBSYSCONF0 (DBSC_BASE + 0x0000U) +#define DBSC_DBSYSCONF1 (DBSC_BASE + 0x0004U) +#define DBSC_DBSYSCONF1A (DBSC_BASE + 0x0008U) +#define DBSC_DBSYSCONF2 (DBSC_BASE + 0x000CU) +#define DBSC_DBPHYCONF0 (DBSC_BASE + 0x0010U) +#define DBSC_DBSYSCONF2A (DBSC_BASE + 0x0014U) +#define DBSC_DBKIND (DBSC_BASE + 0x0020U) +#define DBSC_DBKINDA (DBSC_BASE + 0x0024U) + +#define DBSC_DBMEMCONF(ch, cs) (DBSC_BASE + 0x0030U + 0x2000U * (ch & 0x04U) + 0x10U * (ch & 0x03U) + 0x04U * cs) +#define DBSC_DBMEMCONF_0_0 (DBSC_BASE + 0x0030U) +#define DBSC_DBMEMCONF_0_1 (DBSC_BASE + 0x0034U) +#define DBSC_DBMEMCONF_0_2 (DBSC_BASE + 0x0038U) +#define DBSC_DBMEMCONF_0_3 (DBSC_BASE + 0x003CU) +#define DBSC_DBMEMCONF_1_0 (DBSC_BASE + 0x0040U) +#define DBSC_DBMEMCONF_1_1 (DBSC_BASE + 0x0044U) +#define DBSC_DBMEMCONF_1_2 (DBSC_BASE + 0x0048U) +#define DBSC_DBMEMCONF_1_3 (DBSC_BASE + 0x004CU) +#define DBSC_DBMEMCONF_2_0 (DBSC_BASE + 0x0050U) +#define DBSC_DBMEMCONF_2_1 (DBSC_BASE + 0x0054U) +#define DBSC_DBMEMCONF_2_2 (DBSC_BASE + 0x0058U) +#define DBSC_DBMEMCONF_2_3 (DBSC_BASE + 0x005CU) +#define DBSC_DBMEMCONF_3_0 (DBSC_BASE + 0x0060U) +#define DBSC_DBMEMCONF_3_1 (DBSC_BASE + 0x0064U) +#define DBSC_DBMEMCONF_3_2 (DBSC_BASE + 0x0068U) +#define DBSC_DBMEMCONF_3_3 (DBSC_BASE + 0x006CU) + +#define DBSC_DBMEMCONFA(ch, cs) (DBSC_BASE + 0x0070U + 0x2000U * (ch & 0x04U) + 0x10U * (ch & 0x03U) + 0x04U * cs) +#define DBSC_DBMEMCONF_0_0A (DBSC_BASE + 0x0070U) +#define DBSC_DBMEMCONF_0_1A (DBSC_BASE + 0x0074U) +#define DBSC_DBMEMCONF_0_2A (DBSC_BASE + 0x0078U) +#define DBSC_DBMEMCONF_0_3A (DBSC_BASE + 0x007CU) +#define DBSC_DBMEMCONF_1_0A (DBSC_BASE + 0x0080U) +#define DBSC_DBMEMCONF_1_1A (DBSC_BASE + 0x0084U) +#define DBSC_DBMEMCONF_1_2A (DBSC_BASE + 0x0088U) +#define DBSC_DBMEMCONF_1_3A (DBSC_BASE + 0x008CU) +#define DBSC_DBMEMCONF_2_0A (DBSC_BASE + 0x0090U) +#define DBSC_DBMEMCONF_2_1A (DBSC_BASE + 0x0094U) +#define DBSC_DBMEMCONF_2_2A (DBSC_BASE + 0x0098U) +#define DBSC_DBMEMCONF_2_3A (DBSC_BASE + 0x009CU) +#define DBSC_DBMEMCONF_3_0A (DBSC_BASE + 0x00A0U) +#define DBSC_DBMEMCONF_3_1A (DBSC_BASE + 0x00A4U) +#define DBSC_DBMEMCONF_3_2A (DBSC_BASE + 0x00A8U) +#define DBSC_DBMEMCONF_3_3A (DBSC_BASE + 0x00ACU) + +#define DBSC_DBSYSCNT0 (DBSC_BASE + 0x0100U) +#define DBSC_DBSYSCNT0A (DBSC_BASE + 0x0108U) + +#define DBSC_DBACEN (DBSC_BASE + 0x0200U) +#define DBSC_DBRFEN (DBSC_BASE + 0x0204U) +#define DBSC_DBCMD (DBSC_BASE + 0x0208U) +#define DBSC_DBWAIT (DBSC_BASE + 0x0210U) + +#define DBSC_DBTR(x) (DBSC_BASE + 0x0300U + 0x04U * (x)) +#define DBSC_DBTR0 (DBSC_BASE + 0x0300U) +#define DBSC_DBTR1 (DBSC_BASE + 0x0304U) +#define DBSC_DBTR3 (DBSC_BASE + 0x030CU) +#define DBSC_DBTR4 (DBSC_BASE + 0x0310U) +#define DBSC_DBTR5 (DBSC_BASE + 0x0314U) +#define DBSC_DBTR6 (DBSC_BASE + 0x0318U) +#define DBSC_DBTR7 (DBSC_BASE + 0x031CU) +#define DBSC_DBTR8 (DBSC_BASE + 0x0320U) +#define DBSC_DBTR9 (DBSC_BASE + 0x0324U) +#define DBSC_DBTR10 (DBSC_BASE + 0x0328U) +#define DBSC_DBTR11 (DBSC_BASE + 0x032CU) +#define DBSC_DBTR12 (DBSC_BASE + 0x0330U) +#define DBSC_DBTR13 (DBSC_BASE + 0x0334U) +#define DBSC_DBTR14 (DBSC_BASE + 0x0338U) +#define DBSC_DBTR15 (DBSC_BASE + 0x033CU) +#define DBSC_DBTR16 (DBSC_BASE + 0x0340U) +#define DBSC_DBTR17 (DBSC_BASE + 0x0344U) +#define DBSC_DBTR18 (DBSC_BASE + 0x0348U) +#define DBSC_DBTR19 (DBSC_BASE + 0x034CU) +#define DBSC_DBTR20 (DBSC_BASE + 0x0350U) +#define DBSC_DBTR21 (DBSC_BASE + 0x0354U) +#define DBSC_DBTR22 (DBSC_BASE + 0x0358U) +#define DBSC_DBTR23 (DBSC_BASE + 0x035CU) +#define DBSC_DBTR24 (DBSC_BASE + 0x0360U) +#define DBSC_DBTR25 (DBSC_BASE + 0x0364U) +#define DBSC_DBTR26 (DBSC_BASE + 0x0368U) + +#define DBSC_DBBL (DBSC_BASE + 0x0400U) +#define DBSC_DBBLA (DBSC_BASE + 0x0404U) + +#define DBSC_DBRFCNF1 (DBSC_BASE + 0x0414U) +#define DBSC_DBRFCNF2 (DBSC_BASE + 0x0418U) + +#define DBSC_DBCALCNF (DBSC_BASE + 0x0424U) + +#define DBSC_DBRNK(x) (DBSC_BASE + 0x0430U + 0x04U * (x)) +#define DBSC_DBRNK2 (DBSC_BASE + 0x0438U) +#define DBSC_DBRNK3 (DBSC_BASE + 0x043CU) +#define DBSC_DBRNK4 (DBSC_BASE + 0x0440U) +#define DBSC_DBRNK5 (DBSC_BASE + 0x0444U) + +#define DBSC_DBDBICNT (DBSC_BASE + 0x0518U) +#define DBSC_DBDFIPMSTRCNF (DBSC_BASE + 0x0520U) +#define DBSC_DBDFICUPDCNF (DBSC_BASE + 0x052CU) + +#define DBSC_DBDFISTAT(ch) (DBSC_BASE + 0x0600U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBDFISTAT_0 (DBSC_BASE + 0x0600U) +#define DBSC_DBDFISTAT_1 (DBSC_BASE + 0x0640U) +#define DBSC_DBDFISTAT_2 (DBSC_BASE + 0x0680U) +#define DBSC_DBDFISTAT_3 (DBSC_BASE + 0x06C0U) + +#define DBSC_DBDFICNT(ch) (DBSC_BASE + 0x0604U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBDFICNT_0 (DBSC_BASE + 0x0604U) +#define DBSC_DBDFICNT_1 (DBSC_BASE + 0x0644U) +#define DBSC_DBDFICNT_2 (DBSC_BASE + 0x0684U) +#define DBSC_DBDFICNT_3 (DBSC_BASE + 0x06C4U) + +#define DBSC_DBPDCNT2(ch) (DBSC_BASE + 0x0618U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBPDCNT2_0 (DBSC_BASE + 0x0618U) +#define DBSC_DBPDCNT2_1 (DBSC_BASE + 0x0658U) +#define DBSC_DBPDCNT2_2 (DBSC_BASE + 0x0698U) +#define DBSC_DBPDCNT2_3 (DBSC_BASE + 0x06D8U) + +#define DBSC_DBPDCNT3(ch) (DBSC_BASE + 0x061CU + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBPDCNT3_0 (DBSC_BASE + 0x061CU) +#define DBSC_DBPDCNT3_1 (DBSC_BASE + 0x065CU) +#define DBSC_DBPDCNT3_2 (DBSC_BASE + 0x069CU) +#define DBSC_DBPDCNT3_3 (DBSC_BASE + 0x06DCU) + +#define DBSC_DBPDLK(ch) (DBSC_BASE + 0x0620U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBPDLK_0 (DBSC_BASE + 0x0620U) +#define DBSC_DBPDLK_1 (DBSC_BASE + 0x0660U) +#define DBSC_DBPDLK_2 (DBSC_BASE + 0x06a0U) +#define DBSC_DBPDLK_3 (DBSC_BASE + 0x06e0U) + +#define DBSC_DBPDRGA(ch) (DBSC_BASE + 0x0624U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBPDRGA_0 (DBSC_BASE + 0x0624U) +#define DBSC_DBPDRGA_1 (DBSC_BASE + 0x0664U) +#define DBSC_DBPDRGA_2 (DBSC_BASE + 0x06A4U) +#define DBSC_DBPDRGA_3 (DBSC_BASE + 0x06E4U) + +#define DBSC_DBPDRGD(ch) (DBSC_BASE + 0x0628U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBPDRGD_0 (DBSC_BASE + 0x0628U) +#define DBSC_DBPDRGD_1 (DBSC_BASE + 0x0668U) +#define DBSC_DBPDRGD_2 (DBSC_BASE + 0x06A8U) +#define DBSC_DBPDRGD_3 (DBSC_BASE + 0x06E8U) + +#define DBSC_DBPDSTAT(ch) (DBSC_BASE + 0x0630U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) +#define DBSC_DBPDSTAT_0 (DBSC_BASE + 0x0630U) +#define DBSC_DBPDSTAT_1 (DBSC_BASE + 0x0670U) +#define DBSC_DBPDSTAT_2 (DBSC_BASE + 0x06B0U) +#define DBSC_DBPDSTAT_3 (DBSC_BASE + 0x06F0U) + +#define DBSC_DBPDSTAT1(ch) (DBSC_BASE + 0x0634U + 0x2000U * (ch & 0x04U) + 0x40U * (ch & 0x03U)) + +#define DBSC_DBBUS0CNF0 (DBSC_BASE + 0x0800U) +#define DBSC_DBBUS0CNF1 (DBSC_BASE + 0x0804U) + +#define DBSC_DBBCAMDIS (DBSC_BASE + 0x09FCU) + +#define DBSC_DBSCHRW1 (DBSC_BASE + 0x1024U) + +#define DBSC_SCFCTST0 (DBSC_BASE + 0x1700U) +#define DBSC_SCFCTST1 (DBSC_BASE + 0x1708U) + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ddr_regdef.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ddr_regdef.h new file mode 100644 index 0000000..44b1c25 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ddr_regdef.h @@ -0,0 +1,1320 @@ +/******************************************************************************* + * Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +#define _reg_PHY_CLK_WR_BYPASS_SLAVE_DELAY 0x000b1000U +#define _reg_PHY_IO_PAD_DELAY_TIMING_BYPASS 0x10041000U +#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS 0x000a1001U +#define _reg_PHY_WRITE_PATH_LAT_ADD_BYPASS 0x10031001U +#define _reg_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY 0x000a1002U +#define _reg_PHY_BYPASS_TWO_CYC_PREAMBLE 0x10021002U +#define _reg_PHY_CLK_BYPASS_OVERRIDE 0x18011002U +#define _reg_PHY_SW_WRDQ0_SHIFT 0x00061003U +#define _reg_PHY_SW_WRDQ1_SHIFT 0x08061003U +#define _reg_PHY_SW_WRDQ2_SHIFT 0x10061003U +#define _reg_PHY_SW_WRDQ3_SHIFT 0x18061003U +#define _reg_PHY_SW_WRDQ4_SHIFT 0x00061004U +#define _reg_PHY_SW_WRDQ5_SHIFT 0x08061004U +#define _reg_PHY_SW_WRDQ6_SHIFT 0x10061004U +#define _reg_PHY_SW_WRDQ7_SHIFT 0x18061004U +#define _reg_PHY_SW_WRDM_SHIFT 0x00061005U +#define _reg_PHY_SW_WRDQS_SHIFT 0x08041005U +#define _reg_PHY_PER_RANK_CS_MAP 0x10021005U +#define _reg_PHY_PER_CS_TRAINING_MULTICAST_EN 0x18011005U +#define _reg_PHY_PER_CS_TRAINING_INDEX 0x00011006U +#define _reg_PHY_LP4_BOOT_RDDATA_EN_IE_DLY 0x08021006U +#define _reg_PHY_LP4_BOOT_RDDATA_EN_DLY 0x10051006U +#define _reg_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY 0x18051006U +#define _reg_PHY_LP4_BOOT_RPTR_UPDATE 0x00041007U +#define _reg_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST 0x08041007U +#define _reg_PHY_LP4_BOOT_WRPATH_GATE_DISABLE 0x10021007U +#define _reg_PHY_LP4_BOOT_RDDATA_EN_OE_DLY 0x18051007U +#define _reg_PHY_CTRL_LPBK_EN 0x00021008U +#define _reg_PHY_LPBK_CONTROL 0x08091008U +#define _reg_PHY_LPBK_DFX_TIMEOUT_EN 0x18011008U +#define _reg_PHY_AUTO_TIMING_MARGIN_CONTROL 0x00201009U +#define _reg_PHY_AUTO_TIMING_MARGIN_OBS 0x001c100aU +#define _reg_PHY_PRBS_PATTERN_START 0x0007100bU +#define _reg_PHY_PRBS_PATTERN_MASK 0x0809100bU +#define _reg_PHY_RDLVL_MULTI_PATT_ENABLE 0x1801100bU +#define _reg_PHY_RDLVL_MULTI_PATT_RST_DISABLE 0x0001100cU +#define _reg_PHY_VREF_INITIAL_STEPSIZE 0x0806100cU +#define _reg_PHY_VREF_TRAIN_OBS 0x1007100cU +#define _reg_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY 0x000a100dU +#define _reg_PHY_GATE_ERROR_DELAY_SELECT 0x1004100dU +#define _reg_SC_PHY_SNAP_OBS_REGS 0x1801100dU +#define _reg_PHY_GATE_SMPL1_SLAVE_DELAY 0x0009100eU +#define _reg_PHY_LPDDR 0x1001100eU +#define _reg_PHY_MEM_CLASS 0x1803100eU +#define _reg_PHY_GATE_SMPL2_SLAVE_DELAY 0x0009100fU +#define _reg_ON_FLY_GATE_ADJUST_EN 0x1002100fU +#define _reg_PHY_GATE_TRACKING_OBS 0x00201010U +#define _reg_PHY_DFI40_POLARITY 0x00011011U +#define _reg_PHY_LP4_PST_AMBLE 0x08021011U +#define _reg_PHY_RDLVL_PATT8 0x00201012U +#define _reg_PHY_RDLVL_PATT9 0x00201013U +#define _reg_PHY_RDLVL_PATT10 0x00201014U +#define _reg_PHY_RDLVL_PATT11 0x00201015U +#define _reg_PHY_RDLVL_PATT12 0x00201016U +#define _reg_PHY_RDLVL_PATT13 0x00201017U +#define _reg_PHY_RDLVL_PATT14 0x00201018U +#define _reg_PHY_RDLVL_PATT15 0x00201019U +#define _reg_PHY_SLAVE_LOOP_CNT_UPDATE 0x0003101aU +#define _reg_PHY_SW_FIFO_PTR_RST_DISABLE 0x0801101aU +#define _reg_PHY_MASTER_DLY_LOCK_OBS_SELECT 0x1004101aU +#define _reg_PHY_RDDQ_ENC_OBS_SELECT 0x1803101aU +#define _reg_PHY_RDDQS_DQ_ENC_OBS_SELECT 0x0004101bU +#define _reg_PHY_WR_ENC_OBS_SELECT 0x0804101bU +#define _reg_PHY_WR_SHIFT_OBS_SELECT 0x1004101bU +#define _reg_PHY_FIFO_PTR_OBS_SELECT 0x1804101bU +#define _reg_PHY_LVL_DEBUG_MODE 0x0001101cU +#define _reg_SC_PHY_LVL_DEBUG_CONT 0x0801101cU +#define _reg_PHY_WRLVL_ALGO 0x1002101cU +#define _reg_PHY_WRLVL_PER_START 0x1808101cU +#define _reg_PHY_WRLVL_CAPTURE_CNT 0x0006101dU +#define _reg_PHY_WRLVL_UPDT_WAIT_CNT 0x0804101dU +#define _reg_PHY_DQ_MASK 0x1008101dU +#define _reg_PHY_GTLVL_PER_START 0x000a101eU +#define _reg_PHY_GTLVL_CAPTURE_CNT 0x1006101eU +#define _reg_PHY_GTLVL_UPDT_WAIT_CNT 0x1804101eU +#define _reg_PHY_RDLVL_CAPTURE_CNT 0x0006101fU +#define _reg_PHY_RDLVL_UPDT_WAIT_CNT 0x0804101fU +#define _reg_PHY_RDLVL_OP_MODE 0x1002101fU +#define _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x1805101fU +#define _reg_PHY_RDLVL_PERIODIC_OBS_SELECT 0x00081020U +#define _reg_PHY_RDLVL_DATA_MASK 0x08081020U +#define _reg_PHY_WDQLVL_CLK_JITTER_TOLERANCE 0x10081020U +#define _reg_PHY_WDQLVL_BURST_CNT 0x18061020U +#define _reg_PHY_WDQLVL_PATT 0x00031021U +#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET 0x080b1021U +#define _reg_PHY_WDQLVL_UPDT_WAIT_CNT 0x18041021U +#define _reg_PHY_WDQLVL_DQDM_OBS_SELECT 0x00041022U +#define _reg_PHY_WDQLVL_PERIODIC_OBS_SELECT 0x08081022U +#define _reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS 0x10011022U +#define _reg_PHY_WDQLVL_DATADM_MASK 0x00091023U +#define _reg_PHY_USER_PATT0 0x00201024U +#define _reg_PHY_USER_PATT1 0x00201025U +#define _reg_PHY_USER_PATT2 0x00201026U +#define _reg_PHY_USER_PATT3 0x00201027U +#define _reg_PHY_USER_PATT4 0x00101028U +#define _reg_PHY_NTP_MULT_TRAIN 0x10011028U +#define _reg_PHY_NTP_EARLY_THRESHOLD 0x000a1029U +#define _reg_PHY_NTP_PERIOD_THRESHOLD 0x100a1029U +#define _reg_PHY_NTP_PERIOD_THRESHOLD_MIN 0x000a102aU +#define _reg_PHY_NTP_PERIOD_THRESHOLD_MAX 0x100a102aU +#define _reg_PHY_CALVL_VREF_DRIVING_SLICE 0x0001102bU +#define _reg_SC_PHY_MANUAL_CLEAR 0x0806102bU +#define _reg_PHY_FIFO_PTR_OBS 0x1008102bU +#define _reg_PHY_LPBK_RESULT_OBS 0x0020102cU +#define _reg_PHY_LPBK_ERROR_COUNT_OBS 0x0010102dU +#define _reg_PHY_MASTER_DLY_LOCK_OBS 0x100b102dU +#define _reg_PHY_RDDQ_SLV_DLY_ENC_OBS 0x0007102eU +#define _reg_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS 0x0807102eU +#define _reg_PHY_MEAS_DLY_STEP_VALUE 0x1008102eU +#define _reg_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS 0x1808102eU +#define _reg_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS 0x0008102fU +#define _reg_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS 0x080b102fU +#define _reg_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS 0x1807102fU +#define _reg_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS 0x00081030U +#define _reg_PHY_WR_ADDER_SLV_DLY_ENC_OBS 0x08081030U +#define _reg_PHY_WR_SHIFT_OBS 0x10031030U +#define _reg_PHY_WRLVL_HARD0_DELAY_OBS 0x000a1031U +#define _reg_PHY_WRLVL_HARD1_DELAY_OBS 0x100a1031U +#define _reg_PHY_WRLVL_STATUS_OBS 0x00111032U +#define _reg_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS 0x000a1033U +#define _reg_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS 0x100a1033U +#define _reg_PHY_WRLVL_ERROR_OBS 0x00101034U +#define _reg_PHY_GTLVL_HARD0_DELAY_OBS 0x100e1034U +#define _reg_PHY_GTLVL_HARD1_DELAY_OBS 0x000e1035U +#define _reg_PHY_GTLVL_STATUS_OBS 0x00121036U +#define _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x000a1037U +#define _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x100a1037U +#define _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS 0x00021038U +#define _reg_PHY_RDLVL_STATUS_OBS 0x00201039U +#define _reg_PHY_RDLVL_PERIODIC_OBS 0x0020103aU +#define _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS 0x000b103bU +#define _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS 0x100b103bU +#define _reg_PHY_WDQLVL_STATUS_OBS 0x0020103cU +#define _reg_PHY_WDQLVL_PERIODIC_OBS 0x0020103dU +#define _reg_PHY_DDL_MODE 0x001f103eU +#define _reg_PHY_DDL_MASK 0x0006103fU +#define _reg_PHY_DDL_TEST_OBS 0x00201040U +#define _reg_PHY_DDL_TEST_MSTR_DLY_OBS 0x00201041U +#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD 0x00081042U +#define _reg_PHY_LP4_WDQS_OE_EXTEND 0x08011042U +#define _reg_SC_PHY_RX_CAL_START 0x10011042U +#define _reg_PHY_RX_CAL_OVERRIDE 0x18011042U +#define _reg_PHY_RX_CAL_SAMPLE_WAIT 0x00081043U +#define _reg_PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE 0x08011043U +#define _reg_PHY_RX_CAL_DQ0 0x10091043U +#define _reg_PHY_RX_CAL_DQ1 0x00091044U +#define _reg_PHY_RX_CAL_DQ2 0x10091044U +#define _reg_PHY_RX_CAL_DQ3 0x00091045U +#define _reg_PHY_RX_CAL_DQ4 0x10091045U +#define _reg_PHY_RX_CAL_DQ5 0x00091046U +#define _reg_PHY_RX_CAL_DQ6 0x10091046U +#define _reg_PHY_RX_CAL_DQ7 0x00091047U +#define _reg_PHY_RX_CAL_DM 0x00121048U +#define _reg_PHY_RX_CAL_DQS 0x00091049U +#define _reg_PHY_RX_CAL_FDBK 0x10091049U +#define _reg_PHY_RX_CAL_OBS 0x000b104aU +#define _reg_PHY_RX_CAL_LOCK_OBS 0x1009104aU +#define _reg_PHY_RX_CAL_DISABLE 0x0001104bU +#define _reg_PHY_RX_CAL_SE_ADJUST 0x0807104bU +#define _reg_PHY_RX_CAL_DIFF_ADJUST 0x1007104bU +#define _reg_PHY_RX_CAL_COMP_VAL 0x1801104bU +#define _reg_PHY_RX_CAL_INDEX_MASK 0x000c104cU +#define _reg_PHY_PAD_RX_BIAS_EN 0x100b104cU +#define _reg_PHY_STATIC_TOG_DISABLE 0x0005104dU +#define _reg_PHY_DATA_DC_CAL_SAMPLE_WAIT 0x0808104dU +#define _reg_PHY_DATA_DC_CAL_TIMEOUT 0x1008104dU +#define _reg_PHY_DATA_DC_WEIGHT 0x1802104dU +#define _reg_PHY_DATA_DC_ADJUST_START 0x0006104eU +#define _reg_PHY_DATA_DC_ADJUST_SAMPLE_CNT 0x0808104eU +#define _reg_PHY_DATA_DC_ADJUST_THRSHLD 0x1008104eU +#define _reg_PHY_DATA_DC_ADJUST_DIRECT 0x1801104eU +#define _reg_PHY_DATA_DC_CAL_POLARITY 0x0001104fU +#define _reg_PHY_DATA_DC_CAL_START 0x0801104fU +#define _reg_PHY_DATA_DC_SW_RANK 0x1002104fU +#define _reg_PHY_FDBK_PWR_CTRL 0x1803104fU +#define _reg_PHY_SLV_DLY_CTRL_GATE_DISABLE 0x00011050U +#define _reg_PHY_RDPATH_GATE_DISABLE 0x08011050U +#define _reg_PHY_DCC_RXCAL_CTRL_GATE_DISABLE 0x10011050U +#define _reg_PHY_SLICE_PWR_RDC_DISABLE 0x18011050U +#define _reg_PHY_PARITY_ERROR_REGIF 0x000b1051U +#define _reg_PHY_DS_FSM_ERROR_INFO 0x100e1051U +#define _reg_PHY_DS_FSM_ERROR_INFO_MASK 0x000e1052U +#define _reg_SC_PHY_DS_FSM_ERROR_INFO_WOCLR 0x100e1052U +#define _reg_PHY_DS_TRAIN_CALIB_ERROR_INFO 0x00051053U +#define _reg_PHY_DS_TRAIN_CALIB_ERROR_INFO_MASK 0x08051053U +#define _reg_SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR 0x10051053U +#define _reg_PHY_DQ_TSEL_ENABLE 0x00031054U +#define _reg_PHY_DQ_TSEL_SELECT 0x08101054U +#define _reg_PHY_DQS_TSEL_ENABLE 0x18031054U +#define _reg_PHY_DQS_TSEL_SELECT 0x00101055U +#define _reg_PHY_TWO_CYC_PREAMBLE 0x10021055U +#define _reg_PHY_VREF_INITIAL_START_POINT 0x18071055U +#define _reg_PHY_VREF_INITIAL_STOP_POINT 0x00071056U +#define _reg_PHY_VREF_TRAINING_CTRL 0x08021056U +#define _reg_PHY_NTP_TRAIN_EN 0x10011056U +#define _reg_PHY_NTP_WDQ_STEP_SIZE 0x18081056U +#define _reg_PHY_NTP_WDQ_START 0x000b1057U +#define _reg_PHY_NTP_WDQ_STOP 0x100b1057U +#define _reg_PHY_NTP_WDQ_BIT_EN 0x00081058U +#define _reg_PHY_WDQLVL_DVW_MIN 0x080a1058U +#define _reg_PHY_SW_WDQLVL_DVW_MIN_EN 0x18011058U +#define _reg_PHY_WDQLVL_PER_START_OFFSET 0x00061059U +#define _reg_PHY_FAST_LVL_EN 0x08041059U +#define _reg_PHY_PAD_TX_DCD 0x10051059U +#define _reg_PHY_PAD_RX_DCD_0 0x18051059U +#define _reg_PHY_PAD_RX_DCD_1 0x0005105aU +#define _reg_PHY_PAD_RX_DCD_2 0x0805105aU +#define _reg_PHY_PAD_RX_DCD_3 0x1005105aU +#define _reg_PHY_PAD_RX_DCD_4 0x1805105aU +#define _reg_PHY_PAD_RX_DCD_5 0x0005105bU +#define _reg_PHY_PAD_RX_DCD_6 0x0805105bU +#define _reg_PHY_PAD_RX_DCD_7 0x1005105bU +#define _reg_PHY_PAD_DM_RX_DCD 0x1805105bU +#define _reg_PHY_PAD_DQS_RX_DCD 0x0005105cU +#define _reg_PHY_PAD_FDBK_RX_DCD 0x0805105cU +#define _reg_PHY_PAD_DSLICE_IO_CFG 0x1006105cU +#define _reg_PHY_RDDQ0_SLAVE_DELAY 0x000a105dU +#define _reg_PHY_RDDQ1_SLAVE_DELAY 0x100a105dU +#define _reg_PHY_RDDQ2_SLAVE_DELAY 0x000a105eU +#define _reg_PHY_RDDQ3_SLAVE_DELAY 0x100a105eU +#define _reg_PHY_RDDQ4_SLAVE_DELAY 0x000a105fU +#define _reg_PHY_RDDQ5_SLAVE_DELAY 0x100a105fU +#define _reg_PHY_RDDQ6_SLAVE_DELAY 0x000a1060U +#define _reg_PHY_RDDQ7_SLAVE_DELAY 0x100a1060U +#define _reg_PHY_RDDM_SLAVE_DELAY 0x000a1061U +#define _reg_PHY_DATA_DC_CAL_CLK_SEL 0x10031061U +#define _reg_PHY_DQ_OE_TIMING 0x00081062U +#define _reg_PHY_DQ_TSEL_RD_TIMING 0x08081062U +#define _reg_PHY_DQ_TSEL_WR_TIMING 0x10081062U +#define _reg_PHY_DQS_OE_TIMING 0x18081062U +#define _reg_PHY_IO_PAD_DELAY_TIMING 0x00041063U +#define _reg_PHY_DQS_TSEL_RD_TIMING 0x08081063U +#define _reg_PHY_DQS_OE_RD_TIMING 0x10081063U +#define _reg_PHY_DQS_TSEL_WR_TIMING 0x18081063U +#define _reg_PHY_VREF_SETTING_TIME 0x00101064U +#define _reg_PHY_PAD_VREF_CTRL_DQ 0x100c1064U +#define _reg_PHY_PER_CS_TRAINING_EN 0x00011065U +#define _reg_PHY_DQ_IE_TIMING 0x08081065U +#define _reg_PHY_DQS_IE_TIMING 0x10081065U +#define _reg_PHY_RDDATA_EN_IE_DLY 0x18021065U +#define _reg_PHY_IE_MODE 0x00021066U +#define _reg_PHY_DBI_MODE 0x08011066U +#define _reg_PHY_RDDATA_EN_TSEL_DLY 0x10051066U +#define _reg_PHY_RDDATA_EN_OE_DLY 0x18051066U +#define _reg_PHY_SW_MASTER_MODE 0x00041067U +#define _reg_PHY_MASTER_DELAY_START 0x080b1067U +#define _reg_PHY_MASTER_DELAY_STEP 0x18061067U +#define _reg_PHY_MASTER_DELAY_WAIT 0x00081068U +#define _reg_PHY_MASTER_DELAY_HALF_MEASURE 0x08081068U +#define _reg_PHY_RPTR_UPDATE 0x10041068U +#define _reg_PHY_WRLVL_DLY_STEP 0x18081068U +#define _reg_PHY_WRLVL_DLY_FINE_STEP 0x00041069U +#define _reg_PHY_WRLVL_RESP_WAIT_CNT 0x08061069U +#define _reg_PHY_GTLVL_DLY_STEP 0x10041069U +#define _reg_PHY_GTLVL_RESP_WAIT_CNT 0x18051069U +#define _reg_PHY_GTLVL_BACK_STEP 0x000a106aU +#define _reg_PHY_GTLVL_FINAL_STEP 0x100a106aU +#define _reg_PHY_WDQLVL_DLY_STEP 0x0008106bU +#define _reg_PHY_WDQLVL_QTR_DLY_STEP 0x0804106bU +#define _reg_PHY_TOGGLE_PRE_SUPPORT 0x1001106bU +#define _reg_PHY_RDLVL_DLY_STEP 0x1804106bU +#define _reg_PHY_RDLVL_MAX_EDGE 0x000a106cU +#define _reg_PHY_RDLVL_DVW_MIN 0x000a106dU +#define _reg_PHY_SW_RDLVL_DVW_MIN_EN 0x1001106dU +#define _reg_PHY_RDLVL_PER_START_OFFSET 0x1806106dU +#define _reg_PHY_WRPATH_GATE_DISABLE 0x0002106eU +#define _reg_PHY_WRPATH_GATE_TIMING 0x0803106eU +#define _reg_PHY_DATA_DC_INIT_DISABLE 0x1002106eU +#define _reg_PHY_DATA_DC_DQS_INIT_SLV_DELAY 0x000a106fU +#define _reg_PHY_DATA_DC_DQ_INIT_SLV_DELAY 0x100b106fU +#define _reg_PHY_DATA_DC_WRLVL_ENABLE 0x00011070U +#define _reg_PHY_DATA_DC_WDQLVL_ENABLE 0x08011070U +#define _reg_PHY_DATA_DC_DM_CLK_SE_THRSHLD 0x10081070U +#define _reg_PHY_DATA_DC_DM_CLK_DIFF_THRSHLD 0x18081070U +#define _reg_PHY_WDQ_OSC_DELTA 0x00071071U +#define _reg_PHY_MEAS_DLY_STEP_ENABLE 0x08061071U +#define _reg_PHY_RDDATA_EN_DLY 0x10051071U +#define _reg_PHY_DQ_DM_SWIZZLE0 0x00201072U +#define _reg_PHY_DQ_DM_SWIZZLE1 0x00041073U +#define _reg_PHY_CLK_WRDQ0_SLAVE_DELAY 0x000b1074U +#define _reg_PHY_CLK_WRDQ1_SLAVE_DELAY 0x100b1074U +#define _reg_PHY_CLK_WRDQ2_SLAVE_DELAY 0x000b1075U +#define _reg_PHY_CLK_WRDQ3_SLAVE_DELAY 0x100b1075U +#define _reg_PHY_CLK_WRDQ4_SLAVE_DELAY 0x000b1076U +#define _reg_PHY_CLK_WRDQ5_SLAVE_DELAY 0x100b1076U +#define _reg_PHY_CLK_WRDQ6_SLAVE_DELAY 0x000b1077U +#define _reg_PHY_CLK_WRDQ7_SLAVE_DELAY 0x100b1077U +#define _reg_PHY_CLK_WRDM_SLAVE_DELAY 0x000b1078U +#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY 0x100a1078U +#define _reg_PHY_WRLVL_THRESHOLD_ADJUST 0x00021079U +#define _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY 0x080a1079U +#define _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY 0x000a107aU +#define _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY 0x100a107aU +#define _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY 0x000a107bU +#define _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY 0x100a107bU +#define _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY 0x000a107cU +#define _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY 0x100a107cU +#define _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY 0x000a107dU +#define _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY 0x100a107dU +#define _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY 0x000a107eU +#define _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY 0x100a107eU +#define _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY 0x000a107fU +#define _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY 0x100a107fU +#define _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY 0x000a1080U +#define _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY 0x100a1080U +#define _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY 0x000a1081U +#define _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY 0x100a1081U +#define _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY 0x000a1082U +#define _reg_PHY_RDDQS_GATE_SLAVE_DELAY 0x100a1082U +#define _reg_PHY_RDDQS_LATENCY_ADJUST 0x00041083U +#define _reg_PHY_WRITE_PATH_LAT_ADD 0x08031083U +#define _reg_PHY_WRLVL_DELAY_EARLY_THRESHOLD 0x100a1083U +#define _reg_PHY_WRLVL_DELAY_PERIOD_THRESHOLD 0x000a1084U +#define _reg_PHY_WRLVL_EARLY_FORCE_ZERO 0x10011084U +#define _reg_PHY_GTLVL_RDDQS_SLV_DLY_START 0x000a1085U +#define _reg_PHY_GTLVL_LAT_ADJ_START 0x10041085U +#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_START 0x000b1086U +#define _reg_PHY_NTP_WRLAT_START 0x10041086U +#define _reg_PHY_NTP_PASS 0x18011086U +#define _reg_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START 0x000a1087U +#define _reg_PHY_DATA_DC_DQS_CLK_ADJUST 0x00081088U +#define _reg_PHY_DATA_DC_DQ0_CLK_ADJUST 0x08081088U +#define _reg_PHY_DATA_DC_DQ1_CLK_ADJUST 0x10081088U +#define _reg_PHY_DATA_DC_DQ2_CLK_ADJUST 0x18081088U +#define _reg_PHY_DATA_DC_DQ3_CLK_ADJUST 0x00081089U +#define _reg_PHY_DATA_DC_DQ4_CLK_ADJUST 0x08081089U +#define _reg_PHY_DATA_DC_DQ5_CLK_ADJUST 0x10081089U +#define _reg_PHY_DATA_DC_DQ6_CLK_ADJUST 0x18081089U +#define _reg_PHY_DATA_DC_DQ7_CLK_ADJUST 0x0008108aU +#define _reg_PHY_DATA_DC_DM_CLK_ADJUST 0x0808108aU +#define _reg_PHY_DSLICE_PAD_BOOSTPN_SETTING 0x1010108aU +#define _reg_PHY_DSLICE_PAD_RX_CTLE_SETTING 0x0006108bU +#define _reg_PHY_DQ_FFE 0x0802108bU +#define _reg_PHY_DQS_FFE 0x1002108bU +#define _reg_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0 0x000b1200U +#define _reg_PHY_ADR_CLK_BYPASS_OVERRIDE_0 0x10011200U +#define _reg_SC_PHY_ADR_MANUAL_CLEAR_0 0x18031200U +#define _reg_PHY_ADR_LPBK_RESULT_OBS_0 0x00201201U +#define _reg_PHY_ADR_LPBK_ERROR_COUNT_OBS_0 0x00101202U +#define _reg_PHY_ADR_MEAS_DLY_STEP_VALUE_0 0x10081202U +#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0 0x18041202U +#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_0 0x000b1203U +#define _reg_PHY_ADR_BASE_SLV_DLY_ENC_OBS_0 0x10071203U +#define _reg_PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0 0x18081203U +#define _reg_PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0 0x00031204U +#define _reg_PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0 0x08031204U +#define _reg_SC_PHY_ADR_SNAP_OBS_REGS_0 0x10011204U +#define _reg_PHY_ADR_TSEL_ENABLE_0 0x18011204U +#define _reg_PHY_ADR_LPBK_CONTROL_0 0x00071205U +#define _reg_PHY_ADR_PRBS_PATTERN_START_0 0x08071205U +#define _reg_PHY_ADR_PRBS_PATTERN_MASK_0 0x10051205U +#define _reg_PHY_ADR_PWR_RDC_DISABLE_0 0x18011205U +#define _reg_PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0 0x00011206U +#define _reg_PHY_ADR_TYPE_0 0x08021206U +#define _reg_PHY_ADR_WRADDR_SHIFT_OBS_0 0x10031206U +#define _reg_PHY_ADR_IE_MODE_0 0x18011206U +#define _reg_PHY_ADR_DDL_MODE_0 0x001b1207U +#define _reg_PHY_ADR_DDL_MASK_0 0x00061208U +#define _reg_PHY_ADR_DDL_TEST_OBS_0 0x00201209U +#define _reg_PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0 0x0020120aU +#define _reg_PHY_ADR_CALVL_START_0 0x000b120bU +#define _reg_PHY_ADR_CALVL_COARSE_DLY_0 0x100b120bU +#define _reg_PHY_ADR_CALVL_QTR_0 0x000b120cU +#define _reg_PHY_ADR_CALVL_SWIZZLE0_0 0x0018120dU +#define _reg_PHY_ADR_CALVL_SWIZZLE1_0 0x0018120eU +#define _reg_PHY_ADR_CALVL_RANK_CTRL_0 0x1802120eU +#define _reg_PHY_ADR_CALVL_NUM_PATTERNS_0 0x0002120fU +#define _reg_PHY_ADR_CALVL_RESP_WAIT_CNT_0 0x0804120fU +#define _reg_PHY_ADR_CALVL_PERIODIC_START_OFFSET_0 0x1009120fU +#define _reg_PHY_ADR_CALVL_DEBUG_MODE_0 0x00011210U +#define _reg_SC_PHY_ADR_CALVL_DEBUG_CONT_0 0x08011210U +#define _reg_SC_PHY_ADR_CALVL_ERROR_CLR_0 0x10011210U +#define _reg_PHY_ADR_CALVL_OBS_SELECT_0 0x18031210U +#define _reg_PHY_ADR_CALVL_CH0_OBS0_0 0x00201211U +#define _reg_PHY_ADR_CALVL_CH1_OBS0_0 0x00201212U +#define _reg_PHY_ADR_CALVL_CH2_OBS0_0 0x00201213U +#define _reg_PHY_ADR_CALVL_CH3_OBS0_0 0x00201214U +#define _reg_PHY_ADR_CALVL_OBS1_0 0x00201215U +#define _reg_PHY_ADR_CALVL_OBS2_0 0x00201216U +#define _reg_PHY_ADR_CALVL_FG_0_0 0x00141217U +#define _reg_PHY_ADR_CALVL_BG_0_0 0x00141218U +#define _reg_PHY_ADR_CALVL_FG_1_0 0x00141219U +#define _reg_PHY_ADR_CALVL_BG_1_0 0x0014121aU +#define _reg_PHY_ADR_CALVL_FG_2_0 0x0014121bU +#define _reg_PHY_ADR_CALVL_BG_2_0 0x0014121cU +#define _reg_PHY_ADR_CALVL_FG_3_0 0x0014121dU +#define _reg_PHY_ADR_CALVL_BG_3_0 0x0014121eU +#define _reg_PHY_ADR_ADDR_SEL_0 0x0018121fU +#define _reg_PHY_ADR_LP4_BOOT_SLV_DELAY_0 0x000a1220U +#define _reg_PHY_ADR_BIT_MASK_0 0x10061220U +#define _reg_PHY_ADR_SEG_MASK_0 0x18061220U +#define _reg_PHY_ADR_CALVL_TRAIN_MASK_0 0x00061221U +#define _reg_PHY_ADR_CSLVL_TRAIN_MASK_0 0x08061221U +#define _reg_PHY_ADR_STATIC_TOG_DISABLE_0 0x10041221U +#define _reg_PHY_ADR_SW_TXIO_CTRL_0 0x18061221U +#define _reg_PHY_ADR_DC_INIT_DISABLE_0 0x00021222U +#define _reg_PHY_ADR_DC_ADR0_CLK_ADJUST_0 0x08081222U +#define _reg_PHY_ADR_DC_ADR1_CLK_ADJUST_0 0x10081222U +#define _reg_PHY_ADR_DC_ADR2_CLK_ADJUST_0 0x18081222U +#define _reg_PHY_ADR_DC_ADR3_CLK_ADJUST_0 0x00081223U +#define _reg_PHY_ADR_DC_ADR4_CLK_ADJUST_0 0x08081223U +#define _reg_PHY_ADR_DC_ADR5_CLK_ADJUST_0 0x10081223U +#define _reg_PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0 0x18011223U +#define _reg_PHY_ADR_DC_CAL_SAMPLE_WAIT_0 0x00081224U +#define _reg_PHY_ADR_DC_CAL_TIMEOUT_0 0x08081224U +#define _reg_PHY_ADR_DC_WEIGHT_0 0x10021224U +#define _reg_PHY_ADR_DC_ADJUST_START_0 0x18061224U +#define _reg_PHY_ADR_DC_ADJUST_SAMPLE_CNT_0 0x00081225U +#define _reg_PHY_ADR_DC_ADJUST_THRSHLD_0 0x08081225U +#define _reg_PHY_ADR_DC_ADJUST_DIRECT_0 0x10011225U +#define _reg_PHY_ADR_DC_CAL_POLARITY_0 0x18011225U +#define _reg_PHY_ADR_DC_CAL_START_0 0x00011226U +#define _reg_PHY_ADR_SW_TXPWR_CTRL_0 0x08061226U +#define _reg_PHY_PARITY_ERROR_REGIF_ADR_0 0x100b1226U +#define _reg_PHY_AS_FSM_ERROR_INFO_0 0x00091227U +#define _reg_PHY_AS_FSM_ERROR_INFO_MASK_0 0x10091227U +#define _reg_SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0 0x00091228U +#define _reg_PHY_AS_TRAIN_CALIB_ERROR_INFO_0 0x10011228U +#define _reg_PHY_AS_TRAIN_CALIB_ERROR_INFO_MASK_0 0x18011228U +#define _reg_SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0 0x00011229U +#define _reg_PHY_ADR_TSEL_SELECT_0 0x0008122aU +#define _reg_PHY_ADR_DC_CAL_CLK_SEL_0 0x0803122aU +#define _reg_PHY_PAD_ADR_IO_CFG_0 0x100b122aU +#define _reg_PHY_ADR0_SW_WRADDR_SHIFT_0 0x0005122bU +#define _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY_0 0x080b122bU +#define _reg_PHY_ADR1_SW_WRADDR_SHIFT_0 0x1805122bU +#define _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY_0 0x000b122cU +#define _reg_PHY_ADR2_SW_WRADDR_SHIFT_0 0x1005122cU +#define _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY_0 0x000b122dU +#define _reg_PHY_ADR3_SW_WRADDR_SHIFT_0 0x1005122dU +#define _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY_0 0x000b122eU +#define _reg_PHY_ADR4_SW_WRADDR_SHIFT_0 0x1005122eU +#define _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY_0 0x000b122fU +#define _reg_PHY_ADR5_SW_WRADDR_SHIFT_0 0x1005122fU +#define _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY_0 0x000b1230U +#define _reg_PHY_ADR_SW_MASTER_MODE_0 0x10041230U +#define _reg_PHY_ADR_MASTER_DELAY_START_0 0x000b1231U +#define _reg_PHY_ADR_MASTER_DELAY_STEP_0 0x10061231U +#define _reg_PHY_ADR_MASTER_DELAY_WAIT_0 0x18081231U +#define _reg_PHY_ADR_MASTER_DELAY_HALF_MEASURE_0 0x00081232U +#define _reg_PHY_ADR_SW_CALVL_DVW_MIN_0 0x080a1232U +#define _reg_PHY_ADR_SW_CALVL_DVW_MIN_EN_0 0x18011232U +#define _reg_PHY_ADR_CALVL_DLY_STEP_0 0x00041233U +#define _reg_PHY_ADR_CALVL_CAPTURE_CNT_0 0x00041234U +#define _reg_PHY_ADR_MEAS_DLY_STEP_ENABLE_0 0x08011234U +#define _reg_PHY_ADR_DC_INIT_SLV_DELAY_0 0x100a1234U +#define _reg_PHY_ADR_DC_CALVL_ENABLE_0 0x00011235U +#define _reg_PHY_ADR_DC_DM_CLK_THRSHLD_0 0x08081235U +#define _reg_PHY_FREQ_SEL 0x00031300U +#define _reg_PHY_FREQ_SEL_FROM_REGIF 0x00011301U +#define _reg_PHY_FREQ_SEL_MULTICAST_EN 0x08011301U +#define _reg_PHY_FREQ_SEL_INDEX 0x10021301U +#define _reg_PHY_SW_GRP0_SHIFT_0 0x18051301U +#define _reg_PHY_SW_GRP1_SHIFT_0 0x00051302U +#define _reg_PHY_SW_GRP2_SHIFT_0 0x08051302U +#define _reg_PHY_SW_GRP3_SHIFT_0 0x10051302U +#define _reg_PHY_SW_GRP0_SHIFT_1 0x18051302U +#define _reg_PHY_SW_GRP1_SHIFT_1 0x00051303U +#define _reg_PHY_SW_GRP2_SHIFT_1 0x08051303U +#define _reg_PHY_SW_GRP3_SHIFT_1 0x10051303U +#define _reg_PHY_GRP_BYPASS_SLAVE_DELAY 0x000b1304U +#define _reg_PHY_SW_GRP_BYPASS_SHIFT 0x10051304U +#define _reg_PHY_GRP_BYPASS_OVERRIDE 0x18011304U +#define _reg_SC_PHY_MANUAL_UPDATE 0x00011305U +#define _reg_PHY_MANUAL_UPDATE_PHYUPD_ENABLE 0x08011305U +#define _reg_PHY_CSLVL_START 0x100b1305U +#define _reg_PHY_CSLVL_COARSE_DLY 0x000b1306U +#define _reg_PHY_CSLVL_DEBUG_MODE 0x10011306U +#define _reg_SC_PHY_CSLVL_DEBUG_CONT 0x18011306U +#define _reg_SC_PHY_CSLVL_ERROR_CLR 0x00011307U +#define _reg_PHY_CSLVL_OBS0 0x00201308U +#define _reg_PHY_CSLVL_OBS1 0x00201309U +#define _reg_PHY_CSLVL_OBS2 0x0020130aU +#define _reg_PHY_CSLVL_ENABLE 0x0001130bU +#define _reg_PHY_CSLVL_PERIODIC_START_OFFSET 0x0809130bU +#define _reg_PHY_LP4_BOOT_DISABLE 0x1801130bU +#define _reg_PHY_CSLVL_CS_MAP 0x0002130cU +#define _reg_PHY_CSLVL_QTR 0x080b130cU +#define _reg_PHY_CSLVL_COARSE_CHK 0x000b130dU +#define _reg_PHY_CSLVL_COARSE_CAPTURE_CNT 0x1004130dU +#define _reg_PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE 0x1803130dU +#define _reg_PHY_ADRCTL_SNAP_OBS_REGS 0x0001130eU +#define _reg_PHY_DFI_PHYUPD_TYPE 0x0802130eU +#define _reg_PHY_ADRCTL_LPDDR 0x1001130eU +#define _reg_PHY_LP4_ACTIVE 0x1801130eU +#define _reg_PHY_LPDDR3_CS 0x0001130fU +#define _reg_PHY_CLK_DC_CAL_SAMPLE_WAIT 0x0808130fU +#define _reg_PHY_CLK_DC_CAL_TIMEOUT 0x1008130fU +#define _reg_PHY_CLK_DC_WEIGHT 0x1802130fU +#define _reg_PHY_CLK_DC_FREQ_CHG_ADJ 0x00011310U +#define _reg_PHY_CLK_DC_ADJUST_START 0x08061310U +#define _reg_PHY_CLK_DC_ADJUST_SAMPLE_CNT 0x10081310U +#define _reg_PHY_CLK_DC_ADJUST_THRSHLD 0x18081310U +#define _reg_PHY_CLK_DC_ADJUST_DIRECT 0x00011311U +#define _reg_PHY_CLK_DC_CAL_POLARITY 0x08011311U +#define _reg_PHY_CLK_DC_CAL_START 0x10011311U +#define _reg_SC_PHY_UPDATE_CLK_CAL_VALUES 0x18011311U +#define _reg_PHY_CONTINUOUS_CLK_CAL_UPDATE 0x00011312U +#define _reg_PHY_SW_TXIO_CTRL_0 0x08041312U +#define _reg_PHY_SW_TXIO_CTRL_1 0x10041312U +#define _reg_PHY_MEMCLK_SW_TXIO_CTRL 0x18011312U +#define _reg_PHY_ADRCTL_SW_TXPWR_CTRL_0 0x00041313U +#define _reg_PHY_ADRCTL_SW_TXPWR_CTRL_1 0x08041313U +#define _reg_PHY_MEMCLK_SW_TXPWR_CTRL 0x10011313U +#define _reg_PHY_USER_DEF_REG_AC_0 0x00201314U +#define _reg_PHY_USER_DEF_REG_AC_1 0x00201315U +#define _reg_PHY_USER_DEF_REG_AC_2 0x00201316U +#define _reg_PHY_USER_DEF_REG_AC_3 0x00201317U +#define _reg_PHY_TOP_STATIC_TOG_DISABLE 0x00011318U +#define _reg_PHY_BYTE_DISABLE_STATIC_TOG_DISABLE 0x08011318U +#define _reg_PHY_STATIC_TOG_CONTROL 0x10101318U +#define _reg_PHY_ADRCTL_STATIC_TOG_DISABLE 0x00041319U +#define _reg_PHY_MEMCLK_STATIC_TOG_DISABLE 0x08011319U +#define _reg_PHY_LP4_BOOT_PLL_BYPASS 0x10011319U +#define _reg_PHY_CLK_SWITCH_OBS 0x0020131aU +#define _reg_PHY_PLL_WAIT 0x0010131bU +#define _reg_PHY_SW_PLL_BYPASS 0x0001131cU +#define _reg_PHY_SET_DFI_INPUT_RST_PAD 0x0001131dU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT0_0 0x0802131dU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT1_0 0x1002131dU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT2_0 0x1802131dU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT3_0 0x0002131eU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT0_1 0x0802131eU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT1_1 0x1002131eU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT2_1 0x1802131eU +#define _reg_PHY_CS_ACS_ALLOCATION_BIT3_1 0x0002131fU +#define _reg_PHY_CLK_DC_ADJUST_0 0x0808131fU +#define _reg_PHY_CLK_DC_INIT_DISABLE 0x1001131fU +#define _reg_PHY_CLK_DC_DM_THRSHLD 0x1808131fU +#define _reg_PHY_LP4_BOOT_PLL_CTRL 0x000d1320U +#define _reg_PHY_PLL_CTRL_OVERRIDE 0x10101320U +#define _reg_PHY_USE_PLL_DSKEWCALLOCK 0x00011321U +#define _reg_PHY_PLL_SPO_CAL_CTRL 0x08131321U +#define _reg_SC_PHY_PLL_SPO_CAL_SNAP_OBS 0x00021322U +#define _reg_PHY_PLL_OBS_0 0x08101322U +#define _reg_PHY_PLL_SPO_CAL_OBS_0 0x00111323U +#define _reg_PHY_PLL_OBS_1 0x00101324U +#define _reg_PHY_PLL_SPO_CAL_OBS_1 0x00111325U +#define _reg_PHY_PLL_TESTOUT_SEL 0x18011325U +#define _reg_PHY_LP4_BOOT_LOW_FREQ_SEL 0x00011326U +#define _reg_PHY_TCKSRE_WAIT 0x08041326U +#define _reg_PHY_LP_WAKEUP 0x10081326U +#define _reg_PHY_LS_IDLE_EN 0x18011326U +#define _reg_PHY_LP_CTRLUPD_CNTR_CFG 0x000a1327U +#define _reg_PHY_TDFI_PHY_WRDELAY 0x10011327U +#define _reg_PHY_PAD_FDBK_TERM 0x00121328U +#define _reg_PHY_PAD_DATA_TERM 0x00111329U +#define _reg_PHY_PAD_DQS_TERM 0x0011132aU +#define _reg_PHY_PAD_ADDR_TERM 0x0012132bU +#define _reg_PHY_PAD_CLK_TERM 0x0012132cU +#define _reg_PHY_PAD_CKE_TERM 0x0012132dU +#define _reg_PHY_PAD_RST_TERM 0x0012132eU +#define _reg_PHY_PAD_CS_TERM 0x0012132fU +#define _reg_PHY_PAD_ODT_TERM 0x00121330U +#define _reg_PHY_ADRCTL_RX_CAL 0x000a1331U +#define _reg_PHY_ADRCTL_LP3_RX_CAL 0x100d1331U +#define _reg_PHY_TST_CLK_PAD_CTRL 0x00201332U +#define _reg_PHY_TST_CLK_PAD_CTRL2 0x00171333U +#define _reg_PHY_TST_CLK_PAD_CTRL3 0x00171334U +#define _reg_PHY_TST_CLK_PAD_CTRL4 0x001b1335U +#define _reg_PHY_CAL_MODE_0 0x000d1336U +#define _reg_PHY_CAL_CLEAR_0 0x10011336U +#define _reg_PHY_CAL_START_0 0x18011336U +#define _reg_PHY_CAL_INTERVAL_COUNT_0 0x00201337U +#define _reg_PHY_CAL_SAMPLE_WAIT_0 0x00081338U +#define _reg_PHY_LP4_BOOT_CAL_CLK_SELECT_0 0x08031338U +#define _reg_PHY_CAL_RESULT_OBS_0 0x00181339U +#define _reg_PHY_CAL_RESULT2_OBS_0 0x0018133aU +#define _reg_PHY_CAL_RESULT4_OBS_0 0x0018133bU +#define _reg_PHY_CAL_RESULT5_OBS_0 0x0018133cU +#define _reg_PHY_CAL_RESULT6_OBS_0 0x0018133dU +#define _reg_PHY_CAL_RESULT7_OBS_0 0x0018133eU +#define _reg_PHY_CAL_CPTR_CNT_0 0x1807133eU +#define _reg_PHY_CAL_PU_FINE_ADJ_0 0x0008133fU +#define _reg_PHY_CAL_PD_FINE_ADJ_0 0x0808133fU +#define _reg_PHY_CAL_RCV_FINE_ADJ_0 0x1008133fU +#define _reg_PHY_CAL_DBG_CFG_0 0x1801133fU +#define _reg_SC_PHY_PAD_DBG_CONT_0 0x00011340U +#define _reg_PHY_CAL_RESULT3_OBS_0 0x00201341U +#define _reg_PHY_ADRCTL_PVT_MAP_0 0x00071342U +#define _reg_PHY_CAL_SLOPE_ADJ_0 0x08141342U +#define _reg_PHY_CAL_SLOPE_ADJ_PASS2_0 0x00141343U +#define _reg_PHY_CAL_TWO_PASS_CFG_0 0x00191344U +#define _reg_PHY_CAL_SW_CAL_CFG_0 0x00171345U +#define _reg_PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0 0x18061345U +#define _reg_PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0 0x00061346U +#define _reg_PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0 0x08051346U +#define _reg_PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0 0x10061346U +#define _reg_PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0 0x18061346U +#define _reg_PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0 0x00051347U +#define _reg_PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0 0x08061347U +#define _reg_PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0 0x10061347U +#define _reg_PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0 0x18051347U +#define _reg_PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0 0x00061348U +#define _reg_PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0 0x08061348U +#define _reg_PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0 0x10051348U +#define _reg_PHY_PAD_ATB_CTRL 0x00101349U +#define _reg_PHY_PARITY_ERROR_REGIF_AC 0x100b1349U +#define _reg_PHY_ADRCTL_MANUAL_UPDATE 0x0001134aU +#define _reg_PHY_AC_LPBK_ERR_CLEAR 0x0801134aU +#define _reg_PHY_AC_LPBK_OBS_SELECT 0x1001134aU +#define _reg_PHY_AC_LPBK_ENABLE 0x1802134aU +#define _reg_PHY_AC_LPBK_CONTROL 0x0009134bU +#define _reg_PHY_AC_PRBS_PATTERN_START 0x1007134bU +#define _reg_PHY_AC_PRBS_PATTERN_MASK 0x1804134bU +#define _reg_PHY_AC_LPBK_RESULT_OBS 0x0020134cU +#define _reg_PHY_AC_CLK_LPBK_OBS_SELECT 0x0001134dU +#define _reg_PHY_AC_CLK_LPBK_ENABLE 0x0801134dU +#define _reg_PHY_AC_CLK_LPBK_CONTROL 0x1006134dU +#define _reg_PHY_AC_CLK_LPBK_RESULT_OBS 0x0010134eU +#define _reg_PHY_AC_PWR_RDC_DISABLE 0x1001134eU +#define _reg_PHY_TOP_PWR_RDC_DISABLE 0x1801134eU +#define _reg_PHY_AC_SLV_DLY_CTRL_GATE_DISABLE 0x0001134fU +#define _reg_PHY_CALVL_DEVICE_MAP 0x0805134fU +#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL_0 0x1002134fU +#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL_1 0x1802134fU +#define _reg_PHY_DDL_AC_ENABLE 0x00201350U +#define _reg_PHY_DDL_AC_MODE 0x001a1351U +#define _reg_PHY_DDL_AC_MASK 0x00061352U +#define _reg_PHY_INIT_UPDATE_CONFIG 0x08031352U +#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD_AC 0x10081352U +#define _reg_PHY_ERR_MASK_EN 0x18031352U +#define _reg_PHY_ERR_STATUS 0x00031353U +#define _reg_PHY_DS0_DQS_ERR_COUNTER 0x00201354U +#define _reg_PHY_DS1_DQS_ERR_COUNTER 0x00201355U +#define _reg_PHY_DLL_RST_EN 0x00021356U +#define _reg_PHY_AC_INIT_COMPLETE_OBS 0x080a1356U +#define _reg_PHY_DS_INIT_COMPLETE_OBS 0x18021356U +#define _reg_PHY_UPDATE_MASK 0x00011357U +#define _reg_PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE 0x08011357U +#define _reg_PHY_GRP_SLV_DLY_ENC_OBS_SELECT 0x10041357U +#define _reg_PHY_GRP_SHIFT_OBS_SELECT 0x18031357U +#define _reg_PHY_GRP_SLV_DLY_ENC_OBS 0x000b1358U +#define _reg_PHY_GRP_SHIFT_OBS 0x10031358U +#define _reg_PHY_PARITY_ERROR_INJECTION_ENABLE 0x00011359U +#define _reg_PHY_PARITY_ERROR_REGIF_PS 0x080b1359U +#define _reg_PHY_PLL_LOCK_DEASSERT_MASK 0x18031359U +#define _reg_PHY_PARITY_ERROR_INFO 0x0005135aU +#define _reg_PHY_PARITY_ERROR_INFO_MASK 0x0805135aU +#define _reg_SC_PHY_PARITY_ERROR_INFO_WOCLR 0x1005135aU +#define _reg_PHY_TIMEOUT_ERROR_INFO 0x000e135bU +#define _reg_PHY_TIMEOUT_ERROR_INFO_MASK 0x100e135bU +#define _reg_SC_PHY_TIMEOUT_ERROR_INFO_WOCLR 0x000e135cU +#define _reg_PHY_PLL_FREQUENCY_ERROR 0x1004135cU +#define _reg_PHY_PLL_FREQUENCY_ERROR_MASK 0x1806135cU +#define _reg_SC_PHY_PLL_FREQUENCY_ERROR_WOCLR 0x0006135dU +#define _reg_PHY_PLL_DSKEWCALOUT_MIN 0x080c135dU +#define _reg_PHY_PLL_DSKEWCALOUT_MAX 0x000c135eU +#define _reg_PHY_PLL_DSKEWCALOUT_ERROR_INFO 0x1002135eU +#define _reg_PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK 0x1802135eU +#define _reg_SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR 0x0002135fU +#define _reg_PHY_TOP_FSM_ERROR_INFO 0x0809135fU +#define _reg_PHY_TOP_FSM_ERROR_INFO_MASK 0x00091360U +#define _reg_SC_PHY_TOP_FSM_ERROR_INFO_WOCLR 0x10091360U +#define _reg_PHY_FSM_TRANSIENT_ERROR_INFO 0x00081361U +#define _reg_PHY_FSM_TRANSIENT_ERROR_INFO_MASK 0x08081361U +#define _reg_SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR 0x10081361U +#define _reg_PHY_TOP_TRAIN_CALIB_ERROR_INFO 0x18021361U +#define _reg_PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK 0x00021362U +#define _reg_SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR 0x08021362U +#define _reg_PHY_TRAIN_CALIB_ERROR_INFO 0x10051362U +#define _reg_PHY_TRAIN_CALIB_ERROR_INFO_MASK 0x18051362U +#define _reg_SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR 0x00051363U +#define _reg_PHY_GLOBAL_ERROR_INFO 0x08061363U +#define _reg_PHY_GLOBAL_ERROR_INFO_MASK 0x10061363U +#define _reg_PHY_TRAINING_TIMEOUT_VALUE 0x00141364U +#define _reg_PHY_INIT_TIMEOUT_VALUE 0x00141365U +#define _reg_PHY_LP_TIMEOUT_VALUE 0x00101366U +#define _reg_PHY_PHYUPD_TIMEOUT_VALUE 0x00201367U +#define _reg_PHY_PHYMSTR_TIMEOUT_VALUE 0x00141368U +#define _reg_PHY_PLL_LOCK_0_MIN_VALUE 0x18051368U +#define _reg_PHY_PLL_LOCK_TIMEOUT_VALUE 0x00101369U +#define _reg_PHY_RDDATA_VALID_TIMEOUT_VALUE 0x10081369U +#define _reg_PHY_PLL_FREQUENCY_DELTA 0x18041369U +#define _reg_PHY_PLL_FREQUENCY_COMPARE_INTERVAL 0x0010136aU +#define _reg_PHY_ADRCTL_FSM_ERROR_INFO_0 0x100e136aU +#define _reg_PHY_ADRCTL_FSM_ERROR_INFO_MASK_0 0x000e136bU +#define _reg_SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0 0x100e136bU +#define _reg_PHY_ADRCTL_FSM_ERROR_INFO_1 0x000e136cU +#define _reg_PHY_ADRCTL_FSM_ERROR_INFO_MASK_1 0x100e136cU +#define _reg_SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1 0x000e136dU +#define _reg_PHY_MEMCLK_FSM_ERROR_INFO_0 0x100e136dU +#define _reg_PHY_MEMCLK_FSM_ERROR_INFO_MASK_0 0x000e136eU +#define _reg_SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0 0x100e136eU +#define _reg_PHY_PAD_CAL_IO_CFG_0 0x0012136fU +#define _reg_PHY_PAD_ACS_IO_CFG 0x000d1370U +#define _reg_PHY_PLL_BYPASS 0x00011371U +#define _reg_PHY_PLL_CTRL 0x000d1372U +#define _reg_PHY_LOW_FREQ_SEL 0x10011372U +#define _reg_PHY_PAD_VREF_CTRL_AC 0x000c1373U +#define _reg_PHY_CSLVL_CAPTURE_CNT 0x10041373U +#define _reg_PHY_CSLVL_DLY_STEP 0x18041373U +#define _reg_PHY_SW_CSLVL_DVW_MIN 0x00091374U +#define _reg_PHY_SW_CSLVL_DVW_MIN_EN 0x10011374U +#define _reg_PHY_LVL_MEAS_DLY_STEP_ENABLE 0x18011374U +#define _reg_PHY_GRP0_SLAVE_DELAY_0 0x000b1375U +#define _reg_PHY_GRP1_SLAVE_DELAY_0 0x100b1375U +#define _reg_PHY_GRP2_SLAVE_DELAY_0 0x000b1376U +#define _reg_PHY_GRP3_SLAVE_DELAY_0 0x100b1376U +#define _reg_PHY_GRP0_SLAVE_DELAY_1 0x000b1377U +#define _reg_PHY_GRP1_SLAVE_DELAY_1 0x000b1378U +#define _reg_PHY_GRP2_SLAVE_DELAY_1 0x000b1379U +#define _reg_PHY_GRP3_SLAVE_DELAY_1 0x000b137aU +#define _reg_PHY_CLK_DC_CAL_CLK_SEL 0x0003137bU +#define _reg_PHY_PAD_FDBK_DRIVE 0x001e137cU +#define _reg_PHY_PAD_FDBK_DRIVE2 0x0013137dU +#define _reg_PHY_PAD_DATA_DRIVE 0x001f137eU +#define _reg_PHY_PAD_DATA_DRIVE2 0x0001137fU +#define _reg_PHY_PAD_DQS_DRIVE 0x00201380U +#define _reg_PHY_PAD_DQS_DRIVE2 0x00011381U +#define _reg_PHY_PAD_ADDR_DRIVE 0x001e1382U +#define _reg_PHY_PAD_ADDR_DRIVE2 0x001c1383U +#define _reg_PHY_PAD_CLK_DRIVE 0x00201384U +#define _reg_PHY_PAD_CLK_DRIVE2 0x00131385U +#define _reg_PHY_PAD_CKE_DRIVE 0x001e1386U +#define _reg_PHY_PAD_CKE_DRIVE2 0x001c1387U +#define _reg_PHY_PAD_RST_DRIVE 0x001e1388U +#define _reg_PHY_PAD_RST_DRIVE2 0x001c1389U +#define _reg_PHY_PAD_CS_DRIVE 0x001e138aU +#define _reg_PHY_PAD_CS_DRIVE2 0x001c138bU +#define _reg_PHY_PAD_ODT_DRIVE 0x001e138cU +#define _reg_PHY_PAD_ODT_DRIVE2 0x001c138dU +#define _reg_PHY_CAL_CLK_SELECT_0 0x0003138eU +#define _reg_PHY_CAL_VREF_SWITCH_TIMER_0 0x0810138eU +#define _reg_PHY_CAL_SETTLING_PRD_0 0x1807138eU +#define _reg_PI_START 0x00010800U +#define _reg_PI_DRAM_CLASS 0x08040800U +#define _reg_PI_VERSION 0x00200801U +#define _reg_PI_ID 0x00100802U +#define _reg_PI_NORMAL_LVL_SEQ 0x00010803U +#define _reg_PI_INIT_LVL_EN 0x08010803U +#define _reg_PI_NOTCARE_PHYUPD 0x10010803U +#define _reg_PI_TCMD_GAP 0x00100804U +#define _reg_RESERVED_R0 0x10080804U +#define _reg_PI_TRAIN_ALL_FREQ_REQ 0x18010804U +#define _reg_PI_DFI_VERSION 0x00010805U +#define _reg_PI_DFI_PHYMSTR_TYPE 0x08020805U +#define _reg_PI_DFI_PHYMSTR_CS_STATE_R 0x10010805U +#define _reg_PI_DFI_PHYMSTR_STATE_SEL_R 0x18010805U +#define _reg_PI_TDFI_PHYMSTR_MAX 0x00200806U +#define _reg_PI_TDFI_PHYMSTR_RESP 0x00140807U +#define _reg_PI_TDFI_PHYUPD_RESP 0x00140808U +#define _reg_PI_TDFI_PHYUPD_MAX 0x00200809U +#define _reg_PI_FREQ_MAP 0x0020080aU +#define _reg_PI_INIT_WORK_FREQ 0x0005080bU +#define _reg_PI_INIT_DFS_CALVL_ONLY 0x0801080bU +#define _reg_PI_SW_RST_N 0x1001080bU +#define _reg_RESERVED_V3U 0x1801080bU +#define _reg_PI_CS_MAP 0x0002080cU +#define _reg_PI_RANK_NUM_PER_CKE 0x0805080cU +#define _reg_PI_SRX_LVL_TARGET_CS_EN 0x1001080cU +#define _reg_PI_TMRR 0x1804080cU +#define _reg_PI_PREAMBLE_SUPPORT 0x0002080dU +#define _reg_PI_MCAREF_FORWARD_ONLY 0x0801080dU +#define _reg_PI_WRLVL_MRR_DQ_RETURN_HIZ 0x1001080dU +#define _reg_PI_ON_DFIBUS 0x1801080dU +#define _reg_PI_SWLVL_LOAD 0x0001080eU +#define _reg_PI_SWLVL_OP_DONE 0x0801080eU +#define _reg_PI_SW_WRLVL_RESP_0 0x1001080eU +#define _reg_PI_SW_WRLVL_RESP_1 0x1801080eU +#define _reg_PI_SW_RDLVL_RESP_0 0x0002080fU +#define _reg_PI_SW_RDLVL_RESP_1 0x0802080fU +#define _reg_PI_SW_CALVL_RESP_0 0x1002080fU +#define _reg_PI_SW_LEVELING_MODE 0x1803080fU +#define _reg_PI_SWLVL_START 0x00010810U +#define _reg_PI_SWLVL_EXIT 0x08010810U +#define _reg_PI_SWLVL_WR_SLICE_0 0x10010810U +#define _reg_PI_SWLVL_RD_SLICE_0 0x18010810U +#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_0 0x00010811U +#define _reg_PI_SW_WDQLVL_RESP_0 0x08020811U +#define _reg_PI_SWLVL_WR_SLICE_1 0x10010811U +#define _reg_PI_SWLVL_RD_SLICE_1 0x18010811U +#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_1 0x00010812U +#define _reg_PI_SW_WDQLVL_RESP_1 0x08020812U +#define _reg_PI_SWLVL_SM2_START 0x10010812U +#define _reg_PI_SWLVL_SM2_WR 0x18010812U +#define _reg_PI_SWLVL_SM2_RD 0x00010813U +#define _reg_PI_SEQUENTIAL_LVL_REQ 0x08010813U +#define _reg_PI_DFS_PERIOD_EN 0x10010813U +#define _reg_PI_SRE_PERIOD_EN 0x18010813U +#define _reg_PI_DFI40_POLARITY 0x00010814U +#define _reg_PI_WRLVL_REQ 0x08010814U +#define _reg_PI_WRLVL_CS 0x10010814U +#define _reg_PI_WLDQSEN 0x18060814U +#define _reg_PI_WLMRD 0x00060815U +#define _reg_PI_WRLVL_INTERVAL 0x08100815U +#define _reg_PI_WRLVL_PERIODIC 0x18010815U +#define _reg_PI_WRLVL_ON_SREF_EXIT 0x00010816U +#define _reg_PI_WRLVL_DISABLE_DFS 0x08010816U +#define _reg_PI_WRLVL_RESP_MASK 0x10020816U +#define _reg_PI_WRLVL_ROTATE 0x18010816U +#define _reg_PI_WRLVL_CS_MAP 0x00020817U +#define _reg_PI_WRLVL_ERROR_STATUS 0x08010817U +#define _reg_PI_TDFI_WRLVL_EN 0x10080817U +#define _reg_PI_TDFI_WRLVL_RESP 0x00200818U +#define _reg_PI_TDFI_WRLVL_MAX 0x00200819U +#define _reg_PI_WRLVL_STROBE_NUM 0x0005081aU +#define _reg_PI_TODTH_WR 0x0804081aU +#define _reg_PI_TODTH_RD 0x1004081aU +#define _reg_PI_ODT_VALUE 0x1802081aU +#define _reg_PI_RDLVL_REQ 0x0001081bU +#define _reg_PI_RDLVL_GATE_REQ 0x0801081bU +#define _reg_PI_RDLVL_CS 0x1001081bU +#define _reg_PI_RDLVL_PAT_0 0x0020081cU +#define _reg_PI_RDLVL_PAT_1 0x0020081dU +#define _reg_PI_RDLVL_PAT_2 0x0020081eU +#define _reg_PI_RDLVL_PAT_3 0x0020081fU +#define _reg_PI_RDLVL_PAT_4 0x00200820U +#define _reg_PI_RDLVL_PAT_5 0x00200821U +#define _reg_PI_RDLVL_PAT_6 0x00200822U +#define _reg_PI_RDLVL_PAT_7 0x00200823U +#define _reg_PI_RDLVL_SEQ_EN 0x00040824U +#define _reg_PI_RDLVL_PERIODIC 0x08010824U +#define _reg_PI_RDLVL_ON_SREF_EXIT 0x10010824U +#define _reg_PI_RDLVL_DISABLE_DFS 0x18010824U +#define _reg_PI_RDLVL_GATE_PERIODIC 0x00010825U +#define _reg_PI_RDLVL_GATE_ON_SREF_EXIT 0x08010825U +#define _reg_PI_RDLVL_GATE_DISABLE_DFS 0x10010825U +#define _reg_PI_RDLVL_ROTATE 0x18010825U +#define _reg_PI_RDLVL_GATE_ROTATE 0x00010826U +#define _reg_PI_RDLVL_CS_MAP 0x08020826U +#define _reg_PI_RDLVL_GATE_CS_MAP 0x10020826U +#define _reg_PI_TDFI_RDLVL_RR 0x000a0827U +#define _reg_PI_TDFI_RDLVL_RESP 0x00200828U +#define _reg_PI_RDLVL_RESP_MASK 0x00020829U +#define _reg_PI_TDFI_RDLVL_EN 0x08080829U +#define _reg_PI_TDFI_RDLVL_MAX 0x0020082aU +#define _reg_PI_RDLVL_ERROR_STATUS 0x0001082bU +#define _reg_PI_RDLVL_INTERVAL 0x0810082bU +#define _reg_PI_RDLVL_GATE_INTERVAL 0x0010082cU +#define _reg_PI_RDLVL_PATTERN_START 0x1004082cU +#define _reg_PI_RDLVL_PATTERN_NUM 0x1804082cU +#define _reg_PI_RDLVL_STROBE_NUM 0x0005082dU +#define _reg_PI_RDLVL_GATE_STROBE_NUM 0x0805082dU +#define _reg_PI_RD_PREAMBLE_TRAINING_EN 0x1001082dU +#define _reg_PI_REG_DIMM_ENABLE 0x1801082dU +#define _reg_PI_TDFI_RDDATA_EN 0x0007082eU +#define _reg_PI_TDFI_PHY_WRLAT 0x0807082eU +#define _reg_PI_CALVL_REQ 0x1001082eU +#define _reg_PI_CALVL_CS 0x1801082eU +#define _reg_PI_WRLVL_EN_DEASSERT_2_MRR 0x0001082fU +#define _reg_RESERVED_R1 0x0804082fU +#define _reg_PI_CALVL_SEQ_EN 0x1002082fU +#define _reg_PI_CALVL_PERIODIC 0x1801082fU +#define _reg_PI_CALVL_ON_SREF_EXIT 0x00010830U +#define _reg_PI_CALVL_DISABLE_DFS 0x08010830U +#define _reg_PI_CALVL_ROTATE 0x10010830U +#define _reg_PI_CALVL_CS_MAP 0x18020830U +#define _reg_PI_TDFI_CALVL_EN 0x00080831U +#define _reg_PI_TDFI_CALVL_RESP 0x00200832U +#define _reg_PI_TDFI_CALVL_MAX 0x00200833U +#define _reg_PI_CALVL_RESP_MASK 0x00010834U +#define _reg_PI_CALVL_ERROR_STATUS 0x08020834U +#define _reg_PI_CALVL_INTERVAL 0x10100834U +#define _reg_PI_TCACKEL 0x00050835U +#define _reg_PI_TCAMRD 0x08060835U +#define _reg_PI_TCACKEH 0x10050835U +#define _reg_PI_TCAEXT 0x18050835U +#define _reg_PI_CA_TRAIN_VREF_EN 0x00010836U +#define _reg_PI_CALVL_VREF_INITIAL_STEPSIZE 0x08040836U +#define _reg_PI_CALVL_VREF_NORMAL_STEPSIZE 0x10040836U +#define _reg_PI_TDFI_INIT_START_MIN 0x18080836U +#define _reg_PI_TDFI_INIT_COMPLETE_MIN 0x00080837U +#define _reg_PI_TCKCKEH 0x08040837U +#define _reg_PI_CALVL_STROBE_NUM 0x10050837U +#define _reg_PI_SW_CA_TRAIN_VREF 0x18070837U +#define _reg_PI_CLKDISABLE_2_INIT_START 0x00080838U +#define _reg_PI_INIT_STARTORCOMPLETE_2_CLKDISABLE 0x08080838U +#define _reg_PI_DRAM_CLK_DISABLE_DEASSERT_SEL 0x10010838U +#define _reg_PI_REFRESH_BETWEEN_SEGMENT_DISABLE 0x18010838U +#define _reg_PI_MC_DFS_PI_SET_VREF_ENABLE 0x00010839U +#define _reg_PI_FSM_ERROR_INFO_MASK 0x080d0839U +#define _reg_PI_SC_FSM_ERROR_INFO_WOCLR 0x000d083aU +#define _reg_PI_FSM_ERROR_INFO 0x100d083aU +#define _reg_PI_WDQLVL_VREF_EN 0x0001083bU +#define _reg_PI_WDQLVL_BST_NUM 0x0803083bU +#define _reg_PI_WDQLVL_RESP_MASK 0x1002083bU +#define _reg_PI_WDQLVL_ROTATE 0x1801083bU +#define _reg_PI_WDQLVL_CS_MAP 0x0002083cU +#define _reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE 0x0805083cU +#define _reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE 0x1005083cU +#define _reg_PI_WDQLVL_PERIODIC 0x1801083cU +#define _reg_PI_WDQLVL_REQ 0x0001083dU +#define _reg_PI_WDQLVL_CS 0x0801083dU +#define _reg_PI_TDFI_WDQLVL_EN 0x1008083dU +#define _reg_PI_TDFI_WDQLVL_RESP 0x0020083eU +#define _reg_PI_TDFI_WDQLVL_MAX 0x0020083fU +#define _reg_PI_WDQLVL_INTERVAL 0x00100840U +#define _reg_PI_WDQLVL_ON_SREF_EXIT 0x10010840U +#define _reg_PI_WDQLVL_DISABLE_DFS 0x18010840U +#define _reg_PI_WDQLVL_ERROR_STATUS 0x00020841U +#define _reg_PI_WDQLVL_OSC_EN 0x08010841U +#define _reg_PI_DQS_OSC_PERIOD_EN 0x10010841U +#define _reg_PI_BANK_DIFF 0x18020841U +#define _reg_PI_ROW_DIFF 0x00030842U +#define _reg_PI_TCCD 0x08050842U +#define _reg_RESERVED_R2 0x10040842U +#define _reg_RESERVED_R3 0x18040842U +#define _reg_RESERVED_R4 0x00040843U +#define _reg_RESERVED_R5 0x08040843U +#define _reg_RESERVED_R6 0x10040843U +#define _reg_RESERVED_R7 0x18040843U +#define _reg_RESERVED_R8 0x00040844U +#define _reg_RESERVED_R9 0x08040844U +#define _reg_RESERVED_R10 0x10040844U +#define _reg_RESERVED_R11 0x18040844U +#define _reg_RESERVED_R12 0x00040845U +#define _reg_RESERVED_R13 0x08040845U +#define _reg_RESERVED_R14 0x10040845U +#define _reg_RESERVED_R15 0x18040845U +#define _reg_RESERVED_R16 0x00040846U +#define _reg_RESERVED_R17 0x08040846U +#define _reg_RESERVED_R18 0x10040846U +#define _reg_RESERVED_R19 0x18040846U +#define _reg_RESERVED_R20 0x00040847U +#define _reg_RESERVED_R21 0x08040847U +#define _reg_PI_INT_STATUS 0x00170848U +#define _reg_PI_INT_ACK 0x00160849U +#define _reg_PI_INT_MASK 0x0017084aU +#define _reg_PI_BIST_EXP_DATA_P0 0x0020084bU +#define _reg_PI_BIST_EXP_DATA_P1 0x0020084cU +#define _reg_PI_BIST_FAIL_DATA_P0 0x0020084dU +#define _reg_PI_BIST_FAIL_DATA_P1 0x0020084eU +#define _reg_PI_BIST_FAIL_ADDR_P0 0x0020084fU +#define _reg_PI_BIST_FAIL_ADDR_P1 0x00010850U +#define _reg_PI_BSTLEN 0x08050850U +#define _reg_PI_LONG_COUNT_MASK 0x10050850U +#define _reg_PI_DATA_BYTE_SWAP_EN 0x18010850U +#define _reg_PI_DATA_BYTE_SWAP_SLICE0 0x00010851U +#define _reg_PI_DATA_BYTE_SWAP_SLICE1 0x08010851U +#define _reg_PI_CTRLUPD_REQ_PER_AREF_EN 0x10010851U +#define _reg_PI_TDFI_CTRLUPD_MIN 0x18080851U +#define _reg_PI_UPDATE_ERROR_STATUS 0x00020852U +#define _reg_PI_BIST_GO 0x08010852U +#define _reg_PI_BIST_RESULT 0x10020852U +#define _reg_PI_ADDR_SPACE 0x18060852U +#define _reg_PI_BIST_DATA_CHECK 0x00010853U +#define _reg_PI_BIST_ADDR_CHECK 0x08010853U +#define _reg_PI_BIST_START_ADDRESS_P0 0x00200854U +#define _reg_PI_BIST_START_ADDRESS_P1 0x00010855U +#define _reg_PI_MBIST_INIT_PATTERN 0x08080855U +#define _reg_PI_BIST_DATA_MASK 0x00200856U +#define _reg_PI_BIST_ERR_COUNT 0x000c0857U +#define _reg_PI_BIST_ERR_STOP 0x100c0857U +#define _reg_PI_BIST_ADDR_MASK_0_P0 0x00200858U +#define _reg_PI_BIST_ADDR_MASK_0_P1 0x00020859U +#define _reg_PI_BIST_ADDR_MASK_1_P0 0x0020085aU +#define _reg_PI_BIST_ADDR_MASK_1_P1 0x0002085bU +#define _reg_PI_BIST_ADDR_MASK_2_P0 0x0020085cU +#define _reg_PI_BIST_ADDR_MASK_2_P1 0x0002085dU +#define _reg_PI_BIST_ADDR_MASK_3_P0 0x0020085eU +#define _reg_PI_BIST_ADDR_MASK_3_P1 0x0002085fU +#define _reg_PI_BIST_ADDR_MASK_4_P0 0x00200860U +#define _reg_PI_BIST_ADDR_MASK_4_P1 0x00020861U +#define _reg_PI_BIST_ADDR_MASK_5_P0 0x00200862U +#define _reg_PI_BIST_ADDR_MASK_5_P1 0x00020863U +#define _reg_PI_BIST_ADDR_MASK_6_P0 0x00200864U +#define _reg_PI_BIST_ADDR_MASK_6_P1 0x00020865U +#define _reg_PI_BIST_ADDR_MASK_7_P0 0x00200866U +#define _reg_PI_BIST_ADDR_MASK_7_P1 0x00020867U +#define _reg_PI_BIST_ADDR_MASK_8_P0 0x00200868U +#define _reg_PI_BIST_ADDR_MASK_8_P1 0x00020869U +#define _reg_PI_BIST_ADDR_MASK_9_P0 0x0020086aU +#define _reg_PI_BIST_ADDR_MASK_9_P1 0x0002086bU +#define _reg_PI_BIST_MODE 0x0803086bU +#define _reg_PI_BIST_ADDR_MODE 0x1002086bU +#define _reg_PI_BIST_PAT_MODE 0x1802086bU +#define _reg_PI_BIST_USER_PAT_P0 0x0020086cU +#define _reg_PI_BIST_USER_PAT_P1 0x0020086dU +#define _reg_PI_BIST_PAT_NUM 0x0004086eU +#define _reg_PI_BIST_STAGE_0 0x001e086fU +#define _reg_PI_BIST_STAGE_1 0x001e0870U +#define _reg_PI_BIST_STAGE_2 0x001e0871U +#define _reg_PI_BIST_STAGE_3 0x001e0872U +#define _reg_PI_BIST_STAGE_4 0x001e0873U +#define _reg_PI_BIST_STAGE_5 0x001e0874U +#define _reg_PI_BIST_STAGE_6 0x001e0875U +#define _reg_PI_BIST_STAGE_7 0x001e0876U +#define _reg_PI_COL_DIFF 0x00040877U +#define _reg_PI_SELF_REFRESH_EN 0x08010877U +#define _reg_PI_PWRUP_SREFRESH_EXIT 0x10010877U +#define _reg_PI_MONITOR_SRC_SEL_0 0x18040877U +#define _reg_PI_MONITOR_CAP_SEL_0 0x00010878U +#define _reg_PI_MONITOR_0 0x08080878U +#define _reg_PI_MONITOR_SRC_SEL_1 0x10040878U +#define _reg_PI_MONITOR_CAP_SEL_1 0x18010878U +#define _reg_PI_MONITOR_1 0x00080879U +#define _reg_PI_MONITOR_SRC_SEL_2 0x08040879U +#define _reg_PI_MONITOR_CAP_SEL_2 0x10010879U +#define _reg_PI_MONITOR_2 0x18080879U +#define _reg_PI_MONITOR_SRC_SEL_3 0x0004087aU +#define _reg_PI_MONITOR_CAP_SEL_3 0x0801087aU +#define _reg_PI_MONITOR_3 0x1008087aU +#define _reg_PI_MONITOR_SRC_SEL_4 0x1804087aU +#define _reg_PI_MONITOR_CAP_SEL_4 0x0001087bU +#define _reg_PI_MONITOR_4 0x0808087bU +#define _reg_PI_MONITOR_SRC_SEL_5 0x1004087bU +#define _reg_PI_MONITOR_CAP_SEL_5 0x1801087bU +#define _reg_PI_MONITOR_5 0x0008087cU +#define _reg_PI_MONITOR_SRC_SEL_6 0x0804087cU +#define _reg_PI_MONITOR_CAP_SEL_6 0x1001087cU +#define _reg_PI_MONITOR_6 0x1808087cU +#define _reg_PI_MONITOR_SRC_SEL_7 0x0004087dU +#define _reg_PI_MONITOR_CAP_SEL_7 0x0801087dU +#define _reg_PI_MONITOR_7 0x1008087dU +#define _reg_PI_MONITOR_STROBE 0x0008087eU +#define _reg_PI_DLL_LOCK 0x0001087fU +#define _reg_PI_FREQ_NUMBER_STATUS 0x0805087fU +#define _reg_RESERVED_R22 0x1001087fU +#define _reg_PI_PHYMSTR_TYPE 0x1802087fU +#define _reg_RESERVED_R23 0x00010880U +#define _reg_PI_POWER_REDUC_EN 0x08010880U +#define _reg_RESERVED_R24 0x10010880U +#define _reg_RESERVED_R25 0x18010880U +#define _reg_RESERVED_R26 0x00010881U +#define _reg_RESERVED_R27 0x08010881U +#define _reg_RESERVED_R28 0x10010881U +#define _reg_RESERVED_R29 0x18010881U +#define _reg_RESERVED_R30 0x00010882U +#define _reg_RESERVED_R31 0x08010882U +#define _reg_RESERVED_R32 0x10010882U +#define _reg_RESERVED_R33 0x18010882U +#define _reg_RESERVED_R34 0x00010883U +#define _reg_RESERVED_R35 0x08010883U +#define _reg_RESERVED_R36 0x10010883U +#define _reg_RESERVED_R37 0x18010883U +#define _reg_RESERVED_R38 0x00010884U +#define _reg_PI_WRLVL_MAX_STROBE_PEND 0x08080884U +#define _reg_PI_TREFBW_THR 0x10090884U +#define _reg_PI_FREQ_CHANGE_REG_COPY 0x00050885U +#define _reg_PI_FREQ_SEL_FROM_REGIF 0x00010886U +#define _reg_RESERVED_R39 0x08050886U +#define _reg_PI_CATR 0x10020886U +#define _reg_PI_NO_CATR_READ 0x18010886U +#define _reg_PI_MASK_INIT_COMPLETE 0x00010887U +#define _reg_PI_DISCONNECT_MC 0x08010887U +#define _reg_PI_TRACE_MC_MR13 0x10010887U +#define _reg_PI_TSDO_F0 0x18080887U +#define _reg_PI_TSDO_F1 0x00080888U +#define _reg_PI_TSDO_F2 0x08080888U +#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F0 0x00080889U +#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F1 0x0008088aU +#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x0008088bU +#define _reg_PI_WRLAT_F0 0x0807088bU +#define _reg_PI_CASLAT_LIN_F0 0x1007088bU +#define _reg_PI_WRLAT_F1 0x1807088bU +#define _reg_PI_CASLAT_LIN_F1 0x0007088cU +#define _reg_PI_WRLAT_F2 0x0807088cU +#define _reg_PI_CASLAT_LIN_F2 0x1007088cU +#define _reg_PI_TRFC_F0 0x000a088dU +#define _reg_PI_TREF_F0 0x0014088eU +#define _reg_PI_TRFC_F1 0x000a088fU +#define _reg_PI_TREF_F1 0x00140890U +#define _reg_PI_TRFC_F2 0x000a0891U +#define _reg_PI_TREF_F2 0x00140892U +#define _reg_PI_TDFI_CTRL_DELAY_F0 0x18040892U +#define _reg_PI_TDFI_CTRL_DELAY_F1 0x00040893U +#define _reg_PI_TDFI_CTRL_DELAY_F2 0x08040893U +#define _reg_PI_WRLVL_EN_F0 0x10020893U +#define _reg_PI_WRLVL_EN_F1 0x18020893U +#define _reg_PI_WRLVL_EN_F2 0x00020894U +#define _reg_PI_TDFI_WRLVL_WW_F0 0x080a0894U +#define _reg_PI_TDFI_WRLVL_WW_F1 0x000a0895U +#define _reg_PI_TDFI_WRLVL_WW_F2 0x100a0895U +#define _reg_PI_TODTL_2CMD_F0 0x00080896U +#define _reg_PI_ODT_EN_F0 0x08010896U +#define _reg_PI_TODTL_2CMD_F1 0x10080896U +#define _reg_PI_ODT_EN_F1 0x18010896U +#define _reg_PI_TODTL_2CMD_F2 0x00080897U +#define _reg_PI_ODT_EN_F2 0x08010897U +#define _reg_PI_ODTLON_F0 0x10040897U +#define _reg_PI_TODTON_MIN_F0 0x18040897U +#define _reg_PI_ODTLON_F1 0x00040898U +#define _reg_PI_TODTON_MIN_F1 0x08040898U +#define _reg_PI_ODTLON_F2 0x10040898U +#define _reg_PI_TODTON_MIN_F2 0x18040898U +#define _reg_PI_RDLVL_EN_F0 0x00020899U +#define _reg_PI_RDLVL_GATE_EN_F0 0x08020899U +#define _reg_PI_RDLVL_EN_F1 0x10020899U +#define _reg_PI_RDLVL_GATE_EN_F1 0x18020899U +#define _reg_PI_RDLVL_EN_F2 0x0002089aU +#define _reg_PI_RDLVL_GATE_EN_F2 0x0802089aU +#define _reg_PI_RDLVL_PAT0_EN_F0 0x1002089aU +#define _reg_PI_RDLVL_RXCAL_EN_F0 0x1802089aU +#define _reg_PI_RDLVL_DFE_EN_F0 0x0002089bU +#define _reg_PI_RDLVL_MULTI_EN_F0 0x0802089bU +#define _reg_PI_RDLVL_PAT0_EN_F1 0x1002089bU +#define _reg_PI_RDLVL_RXCAL_EN_F1 0x1802089bU +#define _reg_PI_RDLVL_DFE_EN_F1 0x0002089cU +#define _reg_PI_RDLVL_MULTI_EN_F1 0x0802089cU +#define _reg_PI_RDLVL_PAT0_EN_F2 0x1002089cU +#define _reg_PI_RDLVL_RXCAL_EN_F2 0x1802089cU +#define _reg_PI_RDLVL_DFE_EN_F2 0x0002089dU +#define _reg_PI_RDLVL_MULTI_EN_F2 0x0802089dU +#define _reg_PI_RDLAT_ADJ_F0 0x1007089dU +#define _reg_PI_RDLAT_ADJ_F1 0x1807089dU +#define _reg_PI_RDLAT_ADJ_F2 0x0007089eU +#define _reg_PI_WRLAT_ADJ_F0 0x0807089eU +#define _reg_PI_WRLAT_ADJ_F1 0x1007089eU +#define _reg_PI_WRLAT_ADJ_F2 0x1807089eU +#define _reg_PI_TDFI_PHY_WRDATA_F0 0x0003089fU +#define _reg_PI_TDFI_PHY_WRDATA_F1 0x0803089fU +#define _reg_PI_TDFI_PHY_WRDATA_F2 0x1003089fU +#define _reg_PI_TDFI_CALVL_CC_F0 0x000a08a0U +#define _reg_PI_TDFI_CALVL_CAPTURE_F0 0x100a08a0U +#define _reg_PI_TDFI_CALVL_CC_F1 0x000a08a1U +#define _reg_PI_TDFI_CALVL_CAPTURE_F1 0x100a08a1U +#define _reg_PI_TDFI_CALVL_CC_F2 0x000a08a2U +#define _reg_PI_TDFI_CALVL_CAPTURE_F2 0x100a08a2U +#define _reg_PI_CALVL_EN_F0 0x000208a3U +#define _reg_PI_CALVL_EN_F1 0x080208a3U +#define _reg_PI_CALVL_EN_F2 0x100208a3U +#define _reg_PI_TMRZ_F0 0x180508a3U +#define _reg_PI_TCAENT_F0 0x000e08a4U +#define _reg_PI_TMRZ_F1 0x100508a4U +#define _reg_PI_TCAENT_F1 0x000e08a5U +#define _reg_PI_TMRZ_F2 0x100508a5U +#define _reg_PI_TCAENT_F2 0x000e08a6U +#define _reg_PI_TDFI_CACSCA_F0 0x100508a6U +#define _reg_PI_TDFI_CASEL_F0 0x180508a6U +#define _reg_PI_TVREF_SHORT_F0 0x000a08a7U +#define _reg_PI_TVREF_LONG_F0 0x100a08a7U +#define _reg_PI_TDFI_CACSCA_F1 0x000508a8U +#define _reg_PI_TDFI_CASEL_F1 0x080508a8U +#define _reg_PI_TVREF_SHORT_F1 0x100a08a8U +#define _reg_PI_TVREF_LONG_F1 0x000a08a9U +#define _reg_PI_TDFI_CACSCA_F2 0x100508a9U +#define _reg_PI_TDFI_CASEL_F2 0x180508a9U +#define _reg_PI_TVREF_SHORT_F2 0x000a08aaU +#define _reg_PI_TVREF_LONG_F2 0x100a08aaU +#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F0 0x000708abU +#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F0 0x080708abU +#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F1 0x100708abU +#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F1 0x180708abU +#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F2 0x000708acU +#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x080708acU +#define _reg_PI_CALVL_VREF_DELTA_F0 0x100408acU +#define _reg_PI_CALVL_VREF_DELTA_F1 0x180408acU +#define _reg_PI_CALVL_VREF_DELTA_F2 0x000408adU +#define _reg_PI_TDFI_CALVL_STROBE_F0 0x080408adU +#define _reg_PI_TXP_F0 0x100508adU +#define _reg_PI_TMRWCKEL_F0 0x180808adU +#define _reg_PI_TCKELCK_F0 0x000508aeU +#define _reg_PI_TDFI_CALVL_STROBE_F1 0x080408aeU +#define _reg_PI_TXP_F1 0x100508aeU +#define _reg_PI_TMRWCKEL_F1 0x180808aeU +#define _reg_PI_TCKELCK_F1 0x000508afU +#define _reg_PI_TDFI_CALVL_STROBE_F2 0x080408afU +#define _reg_PI_TXP_F2 0x100508afU +#define _reg_PI_TMRWCKEL_F2 0x180808afU +#define _reg_PI_TCKELCK_F2 0x000508b0U +#define _reg_PI_TDFI_INIT_START_F0 0x080a08b0U +#define _reg_PI_TDFI_INIT_COMPLETE_F0 0x001008b1U +#define _reg_PI_TDFI_INIT_START_F1 0x100a08b1U +#define _reg_PI_TDFI_INIT_COMPLETE_F1 0x001008b2U +#define _reg_PI_TDFI_INIT_START_F2 0x100a08b2U +#define _reg_PI_TDFI_INIT_COMPLETE_F2 0x001008b3U +#define _reg_PI_TCKEHDQS_F0 0x100608b3U +#define _reg_PI_TFC_F0 0x000a08b4U +#define _reg_PI_TCKEHDQS_F1 0x100608b4U +#define _reg_PI_TFC_F1 0x000a08b5U +#define _reg_PI_TCKEHDQS_F2 0x100608b5U +#define _reg_PI_TFC_F2 0x000a08b6U +#define _reg_PI_TDFI_WDQLVL_WR_F0 0x100a08b6U +#define _reg_PI_TDFI_WDQLVL_RW_F0 0x000a08b7U +#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x100708b7U +#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x180708b7U +#define _reg_PI_WDQLVL_VREF_DELTA_F0 0x000408b8U +#define _reg_PI_WDQLVL_EN_F0 0x080208b8U +#define _reg_PI_NTP_TRAIN_EN_F0 0x100208b8U +#define _reg_PI_TDFI_WDQLVL_WR_F1 0x000a08b9U +#define _reg_PI_TDFI_WDQLVL_RW_F1 0x100a08b9U +#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x000708baU +#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x080708baU +#define _reg_PI_WDQLVL_VREF_DELTA_F1 0x100408baU +#define _reg_PI_WDQLVL_EN_F1 0x180208baU +#define _reg_PI_NTP_TRAIN_EN_F1 0x000208bbU +#define _reg_PI_TDFI_WDQLVL_WR_F2 0x080a08bbU +#define _reg_PI_TDFI_WDQLVL_RW_F2 0x000a08bcU +#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x100708bcU +#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x180708bcU +#define _reg_PI_WDQLVL_VREF_DELTA_F2 0x000408bdU +#define _reg_PI_WDQLVL_EN_F2 0x080208bdU +#define _reg_PI_NTP_TRAIN_EN_F2 0x100208bdU +#define _reg_PI_TRTP_F0 0x180808bdU +#define _reg_PI_TRP_F0 0x000808beU +#define _reg_PI_TRCD_F0 0x080808beU +#define _reg_PI_TWTR_F0 0x100608beU +#define _reg_PI_TWR_F0 0x180808beU +#define _reg_PI_TRAS_MAX_F0 0x001008bfU +#define _reg_PI_TRAS_MIN_F0 0x100808bfU +#define _reg_PI_TDQSCK_MAX_F0 0x180408bfU +#define _reg_PI_TCCDMW_F0 0x000608c0U +#define _reg_PI_TSR_F0 0x080808c0U +#define _reg_PI_TMRD_F0 0x100808c0U +#define _reg_PI_TMRW_F0 0x180808c0U +#define _reg_PI_TRTP_F1 0x000808c1U +#define _reg_PI_TRP_F1 0x080808c1U +#define _reg_PI_TRCD_F1 0x100808c1U +#define _reg_PI_TWTR_F1 0x180608c1U +#define _reg_PI_TWR_F1 0x000808c2U +#define _reg_PI_TRAS_MAX_F1 0x081008c2U +#define _reg_PI_TRAS_MIN_F1 0x180808c2U +#define _reg_PI_TDQSCK_MAX_F1 0x000408c3U +#define _reg_PI_TCCDMW_F1 0x080608c3U +#define _reg_PI_TSR_F1 0x100808c3U +#define _reg_PI_TMRD_F1 0x180808c3U +#define _reg_PI_TMRW_F1 0x000808c4U +#define _reg_PI_TRTP_F2 0x080808c4U +#define _reg_PI_TRP_F2 0x100808c4U +#define _reg_PI_TRCD_F2 0x180808c4U +#define _reg_PI_TWTR_F2 0x000608c5U +#define _reg_PI_TWR_F2 0x080808c5U +#define _reg_PI_TRAS_MAX_F2 0x101008c5U +#define _reg_PI_TRAS_MIN_F2 0x000808c6U +#define _reg_PI_TDQSCK_MAX_F2 0x080408c6U +#define _reg_PI_TCCDMW_F2 0x100608c6U +#define _reg_PI_TSR_F2 0x180808c6U +#define _reg_PI_TMRD_F2 0x000808c7U +#define _reg_PI_TMRW_F2 0x080808c7U +#define _reg_PI_TDFI_CTRLUPD_MAX_F0 0x001508c8U +#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F0 0x002008c9U +#define _reg_PI_TDFI_CTRLUPD_MAX_F1 0x001508caU +#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F1 0x002008cbU +#define _reg_PI_TDFI_CTRLUPD_MAX_F2 0x001508ccU +#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F2 0x002008cdU +#define _reg_PI_TXSR_F0 0x001008ceU +#define _reg_PI_TXSR_F1 0x101008ceU +#define _reg_PI_TXSR_F2 0x001008cfU +#define _reg_PI_WDQ_OSC_DELTA_INDEX_F0 0x100408cfU +#define _reg_PI_WDQ_OSC_DELTA_INDEX_F1 0x180408cfU +#define _reg_PI_WDQ_OSC_DELTA_INDEX_F2 0x000408d0U +#define _reg_PI_MR13_DATA_0 0x080808d0U +#define _reg_PI_MR40_DATA_0 0x100808d0U +#define _reg_PI_MR13_DATA_1 0x180808d0U +#define _reg_PI_MR40_DATA_1 0x000808d1U +#define _reg_PI_DQS_OSC_BASE_VALUE_0_0 0x081008d1U +#define _reg_PI_DQS_OSC_BASE_VALUE_0_1 0x001008d2U +#define _reg_PI_MR1_DATA_F0_0 0x100808d2U +#define _reg_PI_MR2_DATA_F0_0 0x180808d2U +#define _reg_PI_MR3_DATA_F0_0 0x000808d3U +#define _reg_PI_MR11_DATA_F0_0 0x080808d3U +#define _reg_PI_MR12_DATA_F0_0 0x100808d3U +#define _reg_PI_MR14_DATA_F0_0 0x180808d3U +#define _reg_PI_MR22_DATA_F0_0 0x000808d4U +#define _reg_PI_MR23_DATA_F0_0 0x080808d4U +#define _reg_PI_MR1_DATA_F1_0 0x100808d4U +#define _reg_PI_MR2_DATA_F1_0 0x180808d4U +#define _reg_PI_MR3_DATA_F1_0 0x000808d5U +#define _reg_PI_MR11_DATA_F1_0 0x080808d5U +#define _reg_PI_MR12_DATA_F1_0 0x100808d5U +#define _reg_PI_MR14_DATA_F1_0 0x180808d5U +#define _reg_PI_MR22_DATA_F1_0 0x000808d6U +#define _reg_PI_MR23_DATA_F1_0 0x080808d6U +#define _reg_PI_MR1_DATA_F2_0 0x100808d6U +#define _reg_PI_MR2_DATA_F2_0 0x180808d6U +#define _reg_PI_MR3_DATA_F2_0 0x000808d7U +#define _reg_PI_MR11_DATA_F2_0 0x080808d7U +#define _reg_PI_MR12_DATA_F2_0 0x100808d7U +#define _reg_PI_MR14_DATA_F2_0 0x180808d7U +#define _reg_PI_MR22_DATA_F2_0 0x000808d8U +#define _reg_PI_MR23_DATA_F2_0 0x080808d8U +#define _reg_PI_MR1_DATA_F0_1 0x100808d8U +#define _reg_PI_MR2_DATA_F0_1 0x180808d8U +#define _reg_PI_MR3_DATA_F0_1 0x000808d9U +#define _reg_PI_MR11_DATA_F0_1 0x080808d9U +#define _reg_PI_MR12_DATA_F0_1 0x100808d9U +#define _reg_PI_MR14_DATA_F0_1 0x180808d9U +#define _reg_PI_MR22_DATA_F0_1 0x000808daU +#define _reg_PI_MR23_DATA_F0_1 0x080808daU +#define _reg_PI_MR1_DATA_F1_1 0x100808daU +#define _reg_PI_MR2_DATA_F1_1 0x180808daU +#define _reg_PI_MR3_DATA_F1_1 0x000808dbU +#define _reg_PI_MR11_DATA_F1_1 0x080808dbU +#define _reg_PI_MR12_DATA_F1_1 0x100808dbU +#define _reg_PI_MR14_DATA_F1_1 0x180808dbU +#define _reg_PI_MR22_DATA_F1_1 0x000808dcU +#define _reg_PI_MR23_DATA_F1_1 0x080808dcU +#define _reg_PI_MR1_DATA_F2_1 0x100808dcU +#define _reg_PI_MR2_DATA_F2_1 0x180808dcU +#define _reg_PI_MR3_DATA_F2_1 0x000808ddU +#define _reg_PI_MR11_DATA_F2_1 0x080808ddU +#define _reg_PI_MR12_DATA_F2_1 0x100808ddU +#define _reg_PI_MR14_DATA_F2_1 0x180808ddU +#define _reg_PI_MR22_DATA_F2_1 0x000808deU +#define _reg_PI_MR23_DATA_F2_1 0x080808deU +#define _reg_PI_PARITY_ERROR_REGIF 0x100b08deU + +#define DDR_REGDEF_ADR(regdef) ((regdef)&0xffff) +#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff) +#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff) + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.c new file mode 100644 index 0000000..055e568 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.c @@ -0,0 +1,354 @@ +/******************************************************************************* + * Copyright (c) 2022-2023 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC setting function + ******************************************************************************/ +/****************************************************************************** + * @file ecc_enable_s4.c + * - Version : 0.02 + * @brief Enable setting process of ECC for DRAM. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 09.08.2022 0.01 First Release + * : 04.04.2023 0.02 Removed stdio.h and string.h. + *****************************************************************************/ + + +#include + +static void ecm_unlock(void); +static void ecm_write(uint32_t adr, uint32_t val); +static void ecm_lock(void); + +#include "boot_init_dram_regdef.h" +#include "ecc_enable_s4.h" + +static void ecm_unlock(void) +{ + uint32_t tmp_adr; + tmp_adr = ((0xACCEU << 16U) | (ECMWPCNTR & 0xffffU)); + mem_write32(ECMWACNTR, tmp_adr); + mem_write32(ECMWPCNTR, 0xACCE0001); +} + +static void ecm_write(uint32_t adr, uint32_t val) +{ + mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU))); + mem_write32(adr, val); +} + +static void ecm_lock(void) +{ + mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (ECMWACNTR & 0xffffU))); + mem_write32(ECMWPCNTR, 0xACCE0000U); +} + +void enable_ecc(void) +{ + NOTICE("ECC for DRAM is enable.\n"); + uint32_t ecm_tmp; + + /* Unlock the access protect for DBSC registers */ + mem_write32(DBSC_DBSYSCNT0, 0x00001234U); + mem_write32(DBSC_DBSYSCNT0A, 0x00001234U); + + /* (A) Initialization for DRAM */ + mmio_write_32(DBSC_DBACEN, 0x00000000U); + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR and ECMERRFATALR registers to inform + the control domain of the fatal error. */ + ecm_tmp = mem_read32(ECMERRTGTR0); + ecm_tmp &= ~(0x3U); + ecm_write(ECMERRTGTR0, ecm_tmp); + + ecm_tmp = mem_read32(ECMERRCTLR0); + ecm_tmp |= 0x3U; + ecm_write(ECMERRCTLR0, ecm_tmp); + + ecm_tmp = mem_read32(ECMERRFATALR0); + ecm_tmp |= 0x3U; + ecm_write(ECMERRFATALR0, ecm_tmp); + + /* (B) Setting ECC protection area */ + /* Set the bottom row address of the ECC protection area */ + mem_write32(DBFSDRAMECCAREA00, ECC_PROT_SIZE0); + mem_write32(DBFSDRAMECCAREA01, ECC_PROT_SIZE1); + + /* (2) Initialization for DRAM connected to DBSCCORE */ + /* Specify RANK0 as the initialization target */ + ecm_tmp = mem_read32(DBFSCONF00A); + ecm_tmp = 0x0U; + mem_write32(DBFSCONF00A, ecm_tmp); + + /* Set the start and end row address of the initialization area */ + mem_write32(DBFSCONF01A, START_ECC_INIT_AREA0); + mem_write32(DBFSCONF05A, END_ECC_INIT_AREA0); + + /* Set 0x1 to start initialization */ + ecm_tmp = mem_read32(DBFSCTRL01A); + ecm_tmp |= 0x01U; + mem_write32(DBFSCTRL01A, ecm_tmp); + + /* Wait until to DRAM initialization is complete */ + NOTICE("DRAM rank 0 is initializing.......\n"); + do + { + ecm_tmp = mem_read32(DBFSSTAT01A); + } while ((ecm_tmp & 0x01U) != 0x01U); + + /* If DRAM is connected to RANK1, Initialize RANK1 */ + /* Specify RANK0 as the initialization target */ + ecm_tmp = mem_read32(DBFSCONF00A); + ecm_tmp |= 0x1U; + mem_write32(DBFSCONF00A, ecm_tmp); + + /* Set the start and end row address of the initialization area */ + mem_write32(DBFSCONF01A, START_ECC_INIT_AREA1); + mem_write32(DBFSCONF05A, END_ECC_INIT_AREA1); + + /* Set 0x1 to start initialization */ + ecm_tmp = mem_read32(DBFSCTRL01A); + ecm_tmp |= 0x01U; + mem_write32(DBFSCTRL01A, ecm_tmp); + + /* Wait until to DRAM initialization is complete */ + NOTICE("DRAM rank 1 is initializing.......\n"); + do + { + ecm_tmp = mem_read32(DBFSSTAT01A); + } while ((ecm_tmp & 0x01U) != 0x01U); + + /* (C) Setting ECC protection enable */ + ecm_tmp = mem_read32(DBFSCONFAXI0); + ecm_tmp |= (0x3 << 8U); + mem_write32(DBFSCONFAXI0, ecm_tmp); + + /* (D) System RAM initialization */ + /* Wait for initialization of System RAM */ + NOTICE("System RAM is initializing.......\n"); + do + { + ; + } while ((mem_read32(DBFSSTAT00A) & 0x1U) != 0x1U); + + /* (E) Setting for ECC error interrupt */ + /* (1) Set the ECC error interrupt for read data. */ + mem_write32(DBFSINTENB02A, 0xFF00U); + + /* (2) Set the ECC error interrupt during RMW operation for System RAM. */ + ecm_tmp = mem_read32(DBFSINTENB02A); + ecm_tmp |= (0xFFU << 24U); + mem_write32(DBFSINTENB02A, ecm_tmp); + + /* (3) Set the ECC error interrupt during RMW operation for DRAM. */ + mem_write32(DBFSINTENB04A, 0xFFFFU); + + /* Lock the ECM registers */ + ecm_lock(); + + /* Enable the write protect of ECM registers */ + mmio_write_32(DBSC_DBACEN, 0x00000001U); + + /* Enable the access protect for DBSC registers */ + mem_write32(DBSC_DBSYSCNT0, 0x00000000U); + mem_write32(DBSC_DBSYSCNT0A, 0x00000000U); +} + +void ecc_rtsram_enable(void) +{ + uint32_t ecc_tmp; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR and + ECMERRFATALR registers to inform the control domain of the fatal error. */ + + /* Set bit 29 of ECMERRTGTR7 to 0 and bit 29 of ECMERRCTLR7 to 1. + (RT-SRAM ecc 2-bit error) */ + ecc_tmp = mem_read32(ECMERRTGTR7); + ecc_tmp |= (1U << 29U) ; + ecm_write(ECMERRTGTR7, ecc_tmp); + + ecc_tmp = mem_read32(ECMERRCTLR7); + ecc_tmp |= (1U << 29U); + ecm_write(ECMERRCTLR7, ecc_tmp); + + /* Set bit 19 of ECMERRTGTR7 to 0 and bit 19 of ECMERRCTLR7 to 1. + (RT-SRAM ecc 2-bit error (for ICUMX)) */ + ecc_tmp = mem_read32(ECMERRTGTR7); + ecc_tmp |= (1U << 19U); + ecm_write(ECMERRTGTR7, ecc_tmp); + + ecc_tmp = mem_read32(ECMERRCTLR7); + ecc_tmp |= (1U << 19U); + ecm_write(ECMERRCTLR7, ecc_tmp); + + /* Set bit 29 and 19 of ECMERRFATALR7 to 1. (Notification of fatal error) */ + ecc_tmp = mem_read32(ECMERRFATALR7); + ecc_tmp |= ((1U << 29U) | (1U << 19U)); + ecm_write(ECMERRFATALR7, ecc_tmp); + + /* (2) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers to + notify the correctable error to software. */ + + /* Set bit 30 of ECMERRTGTR7 to 1 and bit 30 of ECMERRCTLR7 to 1. + (RT-SRAM ecc 1-bit error) */ + ecc_tmp = mem_read32(ECMERRTGTR7); + ecc_tmp |= (1U << 30U); + ecm_write(ECMERRTGTR7, ecc_tmp); + + ecc_tmp = mem_read32(ECMERRCTLR7); + ecc_tmp |= (1U << 30U); + ecm_write(ECMERRCTLR7, ecc_tmp); + + /* Set bit 20 of ECMERRTGTR7 to 1 and bit 20 of ECMERRCTLR7 to 1. + (RT-SRAM ecc 1-bit error (for ICUMX)) */ + ecc_tmp = mem_read32(ECMERRTGTR7); + ecc_tmp |= (1U << 20U); + ecm_write(ECMERRTGTR7, ecc_tmp); + + ecc_tmp = mem_read32(ECMERRCTLR7); + ecc_tmp |= (1U << 20U); + ecm_write(ECMERRCTLR7, ecc_tmp); + + /* Lock the ECM registers */ + ecm_lock(); +} + +void edc_axi_enable(void) +{ + uint32_t edc_tmp; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR + and ECMERRFATALR registers to inform the control domain of the fatal error. */ + + /* Set bit 10 - bit 6 of ECMERRTGTR7 to all 0 and bit 10 - bit 6 of + ECMERRCTLR7 to 1. (Error of AXI-Bus ECM of each hierarchy) */ + edc_tmp = mem_read32(ECMERRTGTR7); + edc_tmp &= ~(0x1fU << 6U); + ecm_write(ECMERRTGTR7, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR7); + edc_tmp |= (0x1fU << 6U); + ecm_write(ECMERRCTLR7, edc_tmp); + + /* Set bit 23 - bit 16 of ECMERRTGTR39 to all 0 and bit 23 - bit 16 of + ECMERRCTLR39 to 1. (Error of AXI-Bus ECM of each hierarchy) */ + edc_tmp = mem_read32(ECMERRTGTR39); + edc_tmp &= ~(0xffU << 16U); + ecm_write(ECMERRTGTR39, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR39); + edc_tmp |= (0xffU << 6U); + ecm_write(ECMERRCTLR39, edc_tmp); + + /* Set bit 26 of ECMERRTGTR1 to 0 and bit 26 of + ECMERRCTLR1 to 1. (CCI bus EDC error) */ + edc_tmp = mem_read32(ECMERRTGTR1); + edc_tmp &= ~(0x1U << 26U); + ecm_write(ECMERRTGTR1, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR1); + edc_tmp |= (0x1U << 26U); + ecm_write(ECMERRCTLR1, edc_tmp); + + /* Set bit 10 - bit 6 of ECMERRFATALR7 to 1. + (Notification of fatal error) */ + edc_tmp = mem_read32(ECMERRFATALR7); + edc_tmp |= (0x1fU << 6U); + ecm_write(ECMERRFATALR7, edc_tmp); + + /* Set bit 23 - bit 16 of ECMERRFATALR39 to 1. + (Notification of fatal error) */ + edc_tmp = mem_read32(ECMERRFATALR39); + edc_tmp |= (0xffU << 16U); + ecm_write(ECMERRFATALR39, edc_tmp); + + /* Set bit 26 of ECMERRFATALR1 to 1. + (Notification of fatal error) */ + edc_tmp = mem_read32(ECMERRFATALR1); + edc_tmp |= (0x1U << 26U); + ecm_write(ECMERRFATALR1, edc_tmp); + + /* Lock the ECM registers */ + ecm_lock(); +} + +void edc_vram_enable(void) +{ + uint32_t edc_tmp; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR, ECMERRCTLR and + ECMERRFATALR registers to inform the control domain of the fatal error. */ + + /* Set bit 19 of ECMERRTGTR17 to 0 and bit 19 of ECMERRCTLR17 to 1. + (RT-VRAM edc 1-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR17); + edc_tmp &= ~(0x1U << 19U); + ecm_write(ECMERRTGTR17, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR17); + edc_tmp |= (0x1U << 19U); + ecm_write(ECMERRCTLR17, edc_tmp); + + /* Set bit 18 of ECMERRTGTR17 to 0 and bit 18 of ECMERRCTLR17 to 1. + (RT-VRAM edc multi-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR17); + edc_tmp &= ~(0x1U << 18U); + ecm_write(ECMERRTGTR17, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR17); + edc_tmp |= (0x1U << 18U); + ecm_write(ECMERRCTLR17, edc_tmp); + + /* Set bit 19, 18 of ECMERRFATALR17 to 1. (Notification of fatal error) */ + edc_tmp = mem_read32(ECMERRFATALR17); + edc_tmp |= (0x3U << 18U); + ecm_write(ECMERRFATALR17, edc_tmp); + + /* Set bit 0 of EDC_CFG to 1. (EDC Error Control) */ + edc_tmp = mem_read32(EDC_CFG); + edc_tmp |= (0x1U << 0U); + ecm_write(EDC_CFG, edc_tmp); + + /* Lock the ECM registers */ + ecm_lock(); +} diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.h new file mode 100644 index 0000000..2bbf663 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/ecc_enable_s4.h @@ -0,0 +1,104 @@ +/******************************************************************************* + * Copyright (c) 2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC driver header + ******************************************************************************/ + +#ifndef ECC_PROTECT +#define ECC_PROTECT +#include "remap_register.h" +#if(__RH850__) + #include "mem_io.h" + #include "log.h" + #define ECM_BASE (BASE_ECC_ADDR) + #define DBSC_BASE (BASE_DBSC_ADDR) +#else + #include + #include + #define ECM_BASE (0xE6250000U) + #define DBSC_BASE (0xE6790000U) +#endif/* __RH850__ */ + +#define RTVRAM_REG_BASE (0xFFEC0000U) + +void enable_ecc(void); +void ecc_rtsram_enable(void); +void edc_axi_enable(void); +void edc_vram_enable(void); + +#define DBSC_DBACEN (DBSC_BASE + 0x0200U) + +#define ECMWACNTR (ECM_BASE + 0x0A04U) +#define ECMWPCNTR (ECM_BASE + 0x0A00U) +#define ECMERRTGTR0 (ECM_BASE + 0x0200U) +#define ECMERRCTLR0 (ECM_BASE + 0x0000U) +#define ECMERRTGTR1 (ECM_BASE + 0x0200U + 0x4U * 1U) +#define ECMERRCTLR1 (ECM_BASE + 0x0000U + 0x4U * 1U) +#define ECMERRTGTR7 (ECM_BASE + 0x0200U + 0x4U * 7U) +#define ECMERRCTLR7 (ECM_BASE + 0x0000U + 0x4U * 7U) +#define ECMERRTGTR17 (ECM_BASE + 0x0200U + 0x4U * 17U) +#define ECMERRCTLR17 (ECM_BASE + 0x0000U + 0x4U * 17U) +#define ECMERRTGTR39 (ECM_BASE + 0x0200U + 0x4U * 39U) +#define ECMERRCTLR39 (ECM_BASE + 0x0000U + 0x4U * 39U) +#define ECMERRFATALR0 (ECM_BASE + 0x0600U) +#define ECMERRFATALR1 (ECM_BASE + 0x0600U + 0x4U * 1U) +#define ECMERRFATALR7 (ECM_BASE + 0x0600U + 0x4U * 7U) +#define ECMERRFATALR17 (ECM_BASE + 0x0600U + 0x4U * 17U) +#define ECMERRFATALR39 (ECM_BASE + 0x0600U + 0x4U * 39U) + +#define DBFSCONF00A (DBSC_BASE + 0x7640U) +#define DBFSCONF01A (DBSC_BASE + 0x7644U) +#define DBFSCONF05A (DBSC_BASE + 0x7654U) +#define DBFSCTRL01A (DBSC_BASE + 0x7604U) +#define DBFSSTAT01A (DBSC_BASE + 0x7684U) +#define DBFSSTAT00A (DBSC_BASE + 0x7680U) +#define DBFSINTENB02A (DBSC_BASE + 0x7088U) +#define DBFSINTENB04A (DBSC_BASE + 0x7090U) + +#define DBFSDRAMECCAREA00 (DBSC_BASE + 0x7450U) +#define DBFSDRAMECCAREA01 (DBSC_BASE + 0x7454U) +#define DBFSCONFAXI0 (DBSC_BASE + 0x7400U) + +#define EDC_CFG (RTVRAM_REG_BASE + 0x4110U) + +/********************* Set by the user *********************/ +/* The row address of ECC Protection Area Size for memory rank 0/1 */ +#define ECC_PROT_SIZE0 (0x2000U) +#define ECC_PROT_SIZE1 (0x2000U) + +/* Start and End row address of ECC Protection area for rank0 */ +#define START_ECC_INIT_AREA0 (0x00000000U) +#define END_ECC_INIT_AREA0 (0x00001FFFU) + +/* Start and End row address of ECC Protection area for rank1 */ +#define START_ECC_INIT_AREA1 (0x00000000U) +#define END_ECC_INIT_AREA1 (0x00001FFFU) +/*********** Other settings cannot be changed ***************/ + +#endif/* ECC_PROTECT */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/init_dram_tbl_s4.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/init_dram_tbl_s4.h new file mode 100644 index 0000000..599ceed --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/s4/lpddr4x/init_dram_tbl_s4.h @@ -0,0 +1,615 @@ +/******************************************************************************* + * Copyright (c) 2021-2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +#define DDR_PHY_SLICE_REGSET_OFS_S4 0x1000 +#define DDR_PHY_ADR_V_REGSET_OFS_S4 0x1200 +#define DDR_PHY_ADR_G_REGSET_OFS_S4 0x1300 +#define DDR_PI_REGSET_OFS_S4 0x0800 + +#define DDR_PHY_SLICE_REGSET_SIZE_S4 0x100 +#define DDR_PHY_ADR_V_REGSET_SIZE_S4 0x80 +#define DDR_PHY_ADR_G_REGSET_SIZE_S4 0x100 +#define DDR_PI_REGSET_SIZE_S4 0x100 + +#define DDR_PHY_SLICE_REGSET_NUM_S4 140 +#define DDR_PHY_ADR_V_REGSET_NUM_S4 54 +#define DDR_PHY_ADR_G_REGSET_NUM_S4 143 +#define DDR_PI_REGSET_NUM_S4 223 + +static const uint32_t DDR_PHY_SLICE_REGSET_S4[DDR_PHY_SLICE_REGSET_NUM_S4] = { +/*1000*/ 0x000004F0, +/*1001*/ 0x00000000, +/*1002*/ 0x00030200, +/*1003*/ 0x00000000, +/*1004*/ 0x00000000, +/*1005*/ 0x01030000, +/*1006*/ 0x00010000, +/*1007*/ 0x01030004, +/*1008*/ 0x00000000, +/*1009*/ 0x00000000, +/*100a*/ 0x00000000, +/*100b*/ 0x01000001, +/*100c*/ 0x00000200, +/*100d*/ 0x000800C0, +/*100e*/ 0x06010190, +/*100f*/ 0x00030030, +/*1010*/ 0x00000000, +/*1011*/ 0x00000000, +/*1012*/ 0x55555A3C, +/*1013*/ 0x00005555, +/*1014*/ 0x0000B5B5, +/*1015*/ 0x00004A4A, +/*1016*/ 0x00005656, +/*1017*/ 0x0000A9A9, +/*1018*/ 0x0000A9A9, +/*1019*/ 0x0000B5B5, +/*101a*/ 0x00000000, +/*101b*/ 0x00000000, +/*101c*/ 0x2A000000, +/*101d*/ 0x00000808, +/*101e*/ 0x04000000, +/*101f*/ 0x00000408, +/*1020*/ 0x10600000, +/*1021*/ 0x0C008006, +/*1022*/ 0x00000000, +/*1023*/ 0x00000000, +/*1024*/ 0x55AA55AA, +/*1025*/ 0x33CC33CC, +/*1026*/ 0x0FF00FF0, +/*1027*/ 0x0F0FF0F0, +/*1028*/ 0x00008E38, +/*1029*/ 0x01000100, +/*102a*/ 0x00800180, +/*102b*/ 0x00000001, +/*102c*/ 0x00000000, +/*102d*/ 0x00000000, +/*102e*/ 0x00000000, +/*102f*/ 0x00000000, +/*1030*/ 0x00000000, +/*1031*/ 0x00000000, +/*1032*/ 0x00000000, +/*1033*/ 0x00000000, +/*1034*/ 0x00000000, +/*1035*/ 0x00000000, +/*1036*/ 0x00000000, +/*1037*/ 0x00000000, +/*1038*/ 0x00000000, +/*1039*/ 0x00000000, +/*103a*/ 0x00000000, +/*103b*/ 0x00000000, +/*103c*/ 0x00000000, +/*103d*/ 0x00000000, +/*103e*/ 0x00000000, +/*103f*/ 0x00000000, +/*1040*/ 0x00000000, +/*1041*/ 0x00000000, +/*1042*/ 0x00000104, +/*1043*/ 0x00000120, +/*1044*/ 0x00000000, +/*1045*/ 0x00000000, +/*1046*/ 0x00000000, +/*1047*/ 0x00000000, +/*1048*/ 0x00000000, +/*1049*/ 0x00000000, +/*104a*/ 0x00000000, +/*104b*/ 0x00000000, +/*104c*/ 0x07FF0000, +/*104d*/ 0x00800800, +/*104e*/ 0x00081020, +/*104f*/ 0x04010000, +/*1050*/ 0x00000000, +/*1051*/ 0x00000000, +/*1052*/ 0x00000000, +/*1053*/ 0x00000000, +/*1054*/ 0x01CC0C01, +/*1055*/ 0x2003CC0C, +/*1056*/ 0x20000139, +/*1057*/ 0x07FF0200, +/*1058*/ 0x0100DD01, +/*1059*/ 0x00000103, +/*105a*/ 0x00000000, +/*105b*/ 0x00000000, +/*105c*/ 0x00060000, +/*105d*/ 0x00A000A0, +/*105e*/ 0x00A000A0, +/*105f*/ 0x00A000A0, +/*1060*/ 0x00A000A0, +/*1061*/ 0x000500A0, +/*1062*/ 0x51517042, +/*1063*/ 0x31C08000, +/*1064*/ 0x09AD0064, +/*1065*/ 0x00C0C001, +/*1066*/ 0x0E0C0101, +/*1067*/ 0x10001000, +/*1068*/ 0x0C073E42, +/*1069*/ 0x0F0C3708, +/*106a*/ 0x01C00190, +/*106b*/ 0x04000420, +/*106c*/ 0x00000322, +/*106d*/ 0x0A0000D0, +/*106e*/ 0x00030200, +/*106f*/ 0x02800000, +/*1070*/ 0x80800000, +/*1071*/ 0x000E0010, +/*1072*/ 0x76543210, +/*1073*/ 0x00000008, +/*1074*/ 0x02800280, +/*1075*/ 0x02800280, +/*1076*/ 0x02800280, +/*1077*/ 0x02800280, +/*1078*/ 0x00000280, +/*1079*/ 0x0000A000, +/*107a*/ 0x00A000A0, +/*107b*/ 0x00A000A0, +/*107c*/ 0x00A000A0, +/*107d*/ 0x00A000A0, +/*107e*/ 0x00A000A0, +/*107f*/ 0x00A000A0, +/*1080*/ 0x00A000A0, +/*1081*/ 0x00A000A0, +/*1082*/ 0x01C200A0, +/*1083*/ 0x01A00005, +/*1084*/ 0x00000000, +/*1085*/ 0x00000000, +/*1086*/ 0x00080200, +/*1087*/ 0x00000000, +/*1088*/ 0x20202020, +/*1089*/ 0x20202020, +/*108a*/ 0x01012020, +/*108b*/ 0x00000000 +}; + +static const uint32_t DDR_PHY_ADR_V_REGSET_S4[DDR_PHY_ADR_V_REGSET_NUM_S4] = { +/*1200*/ 0x00000000, +/*1201*/ 0x00000000, +/*1202*/ 0x00000000, +/*1203*/ 0x00000000, +/*1204*/ 0x00000000, +/*1205*/ 0x00000100, +/*1206*/ 0x00000200, +/*1207*/ 0x00000000, +/*1208*/ 0x00000000, +/*1209*/ 0x00000000, +/*120a*/ 0x00000000, +/*120b*/ 0x00800200, +/*120c*/ 0x00000080, +/*120d*/ 0x00DCBA98, +/*120e*/ 0x01000000, +/*120f*/ 0x00200003, +/*1210*/ 0x00000000, +/*1211*/ 0x00000000, +/*1212*/ 0x00000000, +/*1213*/ 0x00000000, +/*1214*/ 0x00000000, +/*1215*/ 0x00000000, +/*1216*/ 0x00000000, +/*1217*/ 0x0000002A, +/*1218*/ 0x00000015, +/*1219*/ 0x00000015, +/*121a*/ 0x0000002A, +/*121b*/ 0x00000033, +/*121c*/ 0x0000000C, +/*121d*/ 0x0000000C, +/*121e*/ 0x00000033, +/*121f*/ 0x00543210, +/*1220*/ 0x003F0000, +/*1221*/ 0x0000013F, +/*1222*/ 0x20202003, +/*1223*/ 0x00202020, +/*1224*/ 0x20008008, +/*1225*/ 0x00000810, +/*1226*/ 0x00000F00, +/*1227*/ 0x00000000, +/*1228*/ 0x00000000, +/*1229*/ 0x00000000, +/*122a*/ 0x000605CC, +/*122b*/ 0x00030000, +/*122c*/ 0x00000300, +/*122d*/ 0x00000300, +/*122e*/ 0x00000300, +/*122f*/ 0x00000300, +/*1230*/ 0x00000300, +/*1231*/ 0x42080010, +/*1232*/ 0x0000803E, +/*1233*/ 0x00000008, +/*1234*/ 0x01000001, +/*1235*/ 0x00008000 +}; + +static const uint32_t DDR_PHY_ADR_G_REGSET_S4[DDR_PHY_ADR_G_REGSET_NUM_S4] = { +/*1300*/ 0x00000000, +/*1301*/ 0x00000100, +/*1302*/ 0x00000000, +/*1303*/ 0x00000000, +/*1304*/ 0x00050000, +/*1305*/ 0x04000000, +/*1306*/ 0x00000020, +/*1307*/ 0x00000000, +/*1308*/ 0x00000000, +/*1309*/ 0x00000000, +/*130a*/ 0x00000000, +/*130b*/ 0x00002001, +/*130c*/ 0x00004003, +/*130d*/ 0x00010028, +/*130e*/ 0x01010100, +/*130f*/ 0x00800800, +/*1310*/ 0x08102000, +/*1311*/ 0x00000000, +/*1312*/ 0x00000000, +/*1313*/ 0x00010E06, +/*1314*/ 0x00000000, +/*1315*/ 0x00000000, +/*1316*/ 0x00000000, +/*1317*/ 0x00000000, +/*1318*/ 0x00040000, +/*1319*/ 0x00000000, +/*131a*/ 0x00000000, +/*131b*/ 0x00000064, +/*131c*/ 0x00000000, +/*131d*/ 0x00000100, +/*131e*/ 0x00000200, +/*131f*/ 0x80012000, +/*1320*/ 0x00041B42, +/*1321*/ 0x05000000, +/*1322*/ 0x00000000, +/*1323*/ 0x00000000, +/*1324*/ 0x00000000, +/*1325*/ 0x01000000, +/*1326*/ 0x01070501, +/*1327*/ 0x00000054, +/*1328*/ 0x00004410, +/*1329*/ 0x00004410, +/*132a*/ 0x00004410, +/*132b*/ 0x00004410, +/*132c*/ 0x00004410, +/*132d*/ 0x00004410, +/*132e*/ 0x00004410, +/*132f*/ 0x00004410, +/*1330*/ 0x00004410, +/*1331*/ 0x00000000, +/*1332*/ 0x00000000, +/*1333*/ 0x00000000, +/*1334*/ 0x00060000, +/*1335*/ 0x00000000, +/*1336*/ 0x00000090, +/*1337*/ 0x0000A25A, +/*1338*/ 0x00000008, +/*1339*/ 0x00000000, +/*133a*/ 0x00000000, +/*133b*/ 0x00000000, +/*133c*/ 0x00000000, +/*133d*/ 0x00000000, +/*133e*/ 0x03000000, +/*133f*/ 0x00000000, +/*1340*/ 0x00000000, +/*1341*/ 0x00000000, +/*1342*/ 0x04102000, +/*1343*/ 0x00041020, +/*1344*/ 0x00C98C98, +/*1345*/ 0x3F400000, +/*1346*/ 0x3F3F1F3F, +/*1347*/ 0x0000001F, +/*1348*/ 0x00000000, +/*1349*/ 0x00000000, +/*134a*/ 0x00000000, +/*134b*/ 0x00010000, +/*134c*/ 0x00000000, +/*134d*/ 0x00000000, +/*134e*/ 0x00000000, +/*134f*/ 0x00000100, +/*1350*/ 0x00000000, +/*1351*/ 0x00000000, +/*1352*/ 0x00040700, +/*1353*/ 0x00000000, +/*1354*/ 0x00000000, +/*1355*/ 0x00000000, +/*1356*/ 0x00000002, +/*1357*/ 0x00000100, +/*1358*/ 0x00000000, +/*1359*/ 0x00000000, +/*135a*/ 0x00001F00, +/*135b*/ 0x00000000, +/*135c*/ 0x00000000, +/*135d*/ 0x00080000, +/*135e*/ 0x000007FF, +/*135f*/ 0x00000000, +/*1360*/ 0x00000000, +/*1361*/ 0x00000000, +/*1362*/ 0x00000000, +/*1363*/ 0x00000000, +/*1364*/ 0x000FFFFF, +/*1365*/ 0x000FFFFF, +/*1366*/ 0x0000FFFF, +/*1367*/ 0xFFFFFFF0, +/*1368*/ 0x030FFFFF, +/*1369*/ 0x01FFFFFF, +/*136a*/ 0x0000FFFF, +/*136b*/ 0x00000000, +/*136c*/ 0x00000000, +/*136d*/ 0x00000000, +/*136e*/ 0x00000000, +/*136f*/ 0x00000000, +/*1370*/ 0x00000006, +/*1371*/ 0x00000000, +/*1372*/ 0x00001142, +/*1373*/ 0x08010600, +/*1374*/ 0x00000080, +/*1375*/ 0x03000300, +/*1376*/ 0x03000300, +/*1377*/ 0x00000300, +/*1378*/ 0x00000300, +/*1379*/ 0x00000300, +/*137a*/ 0x00000300, +/*137b*/ 0x00000005, +/*137c*/ 0x0004BFCC, +/*137d*/ 0x0000010C, +/*137e*/ 0x0000027F, +/*137f*/ 0x00000000, +/*1380*/ 0x0000027F, +/*1381*/ 0x00000000, +/*1382*/ 0x00127F00, +/*1383*/ 0x0089FF00, +/*1384*/ 0x00827FCC, +/*1385*/ 0x00000000, +/*1386*/ 0x00127F80, +/*1387*/ 0x01980000, +/*1388*/ 0x00127F80, +/*1389*/ 0x01980000, +/*138a*/ 0x00127F00, +/*138b*/ 0x01980000, +/*138c*/ 0x00127F00, +/*138d*/ 0x01980000, +/*138e*/ 0x20040006 +}; + +static const uint32_t DDR_PI_REGSET_S4[DDR_PI_REGSET_NUM_S4] = { +/*0800*/ 0x00000B00, +/*0801*/ 0x00000000, +/*0802*/ 0x00000000, +/*0803*/ 0x00000101, +/*0804*/ 0x00640000, +/*0805*/ 0x00000001, +/*0806*/ 0x00000000, +/*0807*/ 0x00000000, +/*0808*/ 0x00000000, +/*0809*/ 0x00000000, +/*080a*/ 0x00000003, +/*080b*/ 0x00010100, +/*080c*/ 0x08000003, +/*080d*/ 0x00000103, +/*080e*/ 0x00000000, +/*080f*/ 0x00000000, +/*0810*/ 0x00000000, +/*0811*/ 0x00000000, +/*0812*/ 0x00000000, +/*0813*/ 0x00000000, +/*0814*/ 0x0A000000, +/*0815*/ 0x00000028, +/*0816*/ 0x00000100, +/*0817*/ 0x00320003, +/*0818*/ 0x00000000, +/*0819*/ 0x00000000, +/*081a*/ 0x01010102, +/*081b*/ 0x00000000, +/*081c*/ 0x55555A3C, +/*081d*/ 0x00000055, +/*081e*/ 0x000000B5, +/*081f*/ 0x0000004A, +/*0820*/ 0x00000056, +/*0821*/ 0x000000A9, +/*0822*/ 0x000000A9, +/*0823*/ 0x000000B5, +/*0824*/ 0x01000000, +/*0825*/ 0x00010000, +/*0826*/ 0x00030300, +/*0827*/ 0x0000001A, +/*0828*/ 0x000007D0, +/*0829*/ 0x00000300, +/*082a*/ 0x00000000, +/*082b*/ 0x00000000, +/*082c*/ 0x01080000, +/*082d*/ 0x00010101, +/*082e*/ 0x00000000, +/*082f*/ 0x00030000, +/*0830*/ 0x03000100, +/*0831*/ 0x00000017, +/*0832*/ 0x00000000, +/*0833*/ 0x00000000, +/*0834*/ 0x00000000, +/*0835*/ 0x0A0A140A, +/*0836*/ 0x10020300, +/*0837*/ 0x00020805, +/*0838*/ 0x00000404, +/*0839*/ 0x00000000, +/*083a*/ 0x00000000, +/*083b*/ 0x01000101, +/*083c*/ 0x00020203, +/*083d*/ 0x00340000, +/*083e*/ 0x00000000, +/*083f*/ 0x00000000, +/*0840*/ 0x01000000, +/*0841*/ 0x00000000, +/*0842*/ 0x00000800, +/*0843*/ 0x00020002, +/*0844*/ 0x00010001, +/*0845*/ 0x00010000, +/*0846*/ 0x00020002, +/*0847*/ 0x00000002, +/*0848*/ 0x00000000, +/*0849*/ 0x00000000, +/*084a*/ 0x00000000, +/*084b*/ 0x00000000, +/*084c*/ 0x00000000, +/*084d*/ 0x00000000, +/*084e*/ 0x00000000, +/*084f*/ 0x00000000, +/*0850*/ 0x00100400, +/*0851*/ 0x08010100, +/*0852*/ 0x08000000, +/*0853*/ 0x00000100, +/*0854*/ 0x00000000, +/*0855*/ 0x0000AA00, +/*0856*/ 0x00000000, +/*0857*/ 0x00010000, +/*0858*/ 0x00000000, +/*0859*/ 0x00000000, +/*085a*/ 0x00000000, +/*085b*/ 0x00000000, +/*085c*/ 0x00000000, +/*085d*/ 0x00000000, +/*085e*/ 0x00000000, +/*085f*/ 0x00000000, +/*0860*/ 0x00000000, +/*0861*/ 0x00000000, +/*0862*/ 0x00000000, +/*0863*/ 0x00000000, +/*0864*/ 0x00000000, +/*0865*/ 0x00000000, +/*0866*/ 0x00000000, +/*0867*/ 0x00000000, +/*0868*/ 0x00000000, +/*0869*/ 0x00000000, +/*086a*/ 0x00000000, +/*086b*/ 0x00000000, +/*086c*/ 0x00000000, +/*086d*/ 0x00000000, +/*086e*/ 0x00000000, +/*086f*/ 0x00000000, +/*0870*/ 0x00000000, +/*0871*/ 0x00000000, +/*0872*/ 0x00000000, +/*0873*/ 0x00000000, +/*0874*/ 0x00000000, +/*0875*/ 0x00000000, +/*0876*/ 0x00000000, +/*0877*/ 0x00000002, +/*0878*/ 0x01010001, +/*0879*/ 0x00010200, +/*087a*/ 0x04000103, +/*087b*/ 0x01050001, +/*087c*/ 0x00010600, +/*087d*/ 0x00000107, +/*087e*/ 0x00000000, +/*087f*/ 0x00000000, +/*0880*/ 0x00000100, +/*0881*/ 0x00000000, +/*0882*/ 0x00000000, +/*0883*/ 0x00000000, +/*0884*/ 0x00040100, +/*0885*/ 0x00000000, +/*0886*/ 0x00000000, +/*0887*/ 0x01000000, +/*0888*/ 0x00002B2B, +/*0889*/ 0x00000034, +/*088a*/ 0x0000006C, +/*088b*/ 0x120C046C, +/*088c*/ 0x00481248, +/*088d*/ 0x00000006, +/*088e*/ 0x00000046, +/*088f*/ 0x00000256, +/*0890*/ 0x00002073, +/*0891*/ 0x00000256, +/*0892*/ 0x04002073, +/*0893*/ 0x00000404, +/*0894*/ 0x00002A00, +/*0895*/ 0x002A002A, +/*0896*/ 0x01000100, +/*0897*/ 0x00000100, +/*0898*/ 0x00000000, +/*0899*/ 0x00000000, +/*089a*/ 0x00010000, +/*089b*/ 0x00010100, +/*089c*/ 0x00010100, +/*089d*/ 0x15040100, +/*089e*/ 0x0E0E0215, +/*089f*/ 0x00040402, +/*08a0*/ 0x000C0034, +/*08a1*/ 0x00210049, +/*08a2*/ 0x00210049, +/*08a3*/ 0x01000001, +/*08a4*/ 0x00040005, +/*08a5*/ 0x00040216, +/*08a6*/ 0x01000216, +/*08a7*/ 0x00060006, +/*08a8*/ 0x02170100, +/*08a9*/ 0x01000217, +/*08aa*/ 0x02170217, +/*08ab*/ 0x11111111, +/*08ac*/ 0x00001111, +/*08ad*/ 0x0A070600, +/*08ae*/ 0x1F130A0D, +/*08af*/ 0x1F130A14, +/*08b0*/ 0x0000C014, +/*08b1*/ 0x00C01000, +/*08b2*/ 0x00C01000, +/*08b3*/ 0x00021000, +/*08b4*/ 0x00240005, +/*08b5*/ 0x00240216, +/*08b6*/ 0x003E0216, +/*08b7*/ 0x1609003A, +/*08b8*/ 0x00000007, +/*08b9*/ 0x003A003E, +/*08ba*/ 0x00071609, +/*08bb*/ 0x00003E00, +/*08bc*/ 0x1609003A, +/*08bd*/ 0x08000007, +/*08be*/ 0x04010404, +/*08bf*/ 0x01030277, +/*08c0*/ 0x0A0A0320, +/*08c1*/ 0x18272D10, +/*08c2*/ 0x5A752F28, +/*08c3*/ 0x1E202008, +/*08c4*/ 0x272D1016, +/*08c5*/ 0x752F2818, +/*08c6*/ 0x2020085A, +/*08c7*/ 0x0000161E, +/*08c8*/ 0x0000008C, +/*08c9*/ 0x00000578, +/*08ca*/ 0x000040E6, +/*08cb*/ 0x000288FC, +/*08cc*/ 0x000040E6, +/*08cd*/ 0x000288FC, +/*08ce*/ 0x02660006, +/*08cf*/ 0x04040266, +/*08d0*/ 0xC83CC804, +/*08d1*/ 0x0000003C, +/*08d2*/ 0x00040000, +/*08d3*/ 0x0F1166F1, +/*08d4*/ 0x3F740006, +/*08d5*/ 0x0F1166F1, +/*08d6*/ 0x3F740006, +/*08d7*/ 0x0F1166F1, +/*08d8*/ 0x00040006, +/*08d9*/ 0x0F1166F1, +/*08da*/ 0x3F74002E, +/*08db*/ 0x0F1166F1, +/*08dc*/ 0x3F74002E, +/*08dd*/ 0x0F1166F1, +/*08de*/ 0x0000002E +}; + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h new file mode 100644 index 0000000..8cdb901 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h @@ -0,0 +1,302 @@ +/******************************************************************************* + * Copyright (c) 2015-2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +#if defined(__RH850G3K__) +#include "remap_register.h" +#endif + +#define RCAR_DDR_VERSION "rev.0.08rc7" +#define DRAM_CH_CNT 0x04 +#define SLICE_CNT 0x02 +#define CS_CNT 0x02 + +/* for pll setting */ +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) +#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb))) + +/* for ddr density setting */ +#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30) | ((row) << 24) | ((BG) << 20) | ((bank) << 16) | ((col) << 8) | (dw)) +#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (28 - 2 - 2 - 10 - 1), 2, 2, 10, 1)) /* 16bit */ +#define DBMEMCONF_VAL(ch,cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) + +/* system registers : CPG */ +#define CPG_FRQCRD_KICK_BIT (1U << 31) +#define CPG_PLL3CR0_KICK_BIT (1U << 31) + +#define CPG_PLLECR_PLL3E_BIT (1U << 3) +#define CPG_PLLECR_PLL3ST_BIT (1U << 11) + +#if defined(__RH850G3K__) +#define CPG_BASE (BASE_CPG_ADDR) +#else +#define CPG_BASE (0xE6150000U) +#endif +#define CPG_CPGWPR (CPG_BASE + 0x0000U) +#define CPG_CPGWPCR (CPG_BASE + 0x0004U) +#define CPG_FRQCRA (CPG_BASE + 0x0800U) +#define CPG_FRQCRB (CPG_BASE + 0x0804U) +#define CPG_FRQCRC (CPG_BASE + 0x0808U) +#define CPG_FRQCRD0 (CPG_BASE + 0x080CU) +#define CPG_PLLECR (CPG_BASE + 0x0820U) +#define CPG_PLL3CR0 (CPG_BASE + 0x083CU) +#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U) +#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U) +#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U) +#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U) +#define CPG_SRCR4 (CPG_BASE + 0x2C10U) +#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U) + +#define CPG_PLL3FBCKMCSR (CPG_BASE + 0x0C60U) +#define CPG_PLL3FBCKMECR (CPG_BASE + 0x0C64U) +#define CPG_PLL3FBCKMLCH (CPG_BASE + 0x0C68U) +#define CPG_PLL3FBCKMLCL (CPG_BASE + 0x0C6CU) +#define CPG_PLL3FBCKMCNT (CPG_BASE + 0x0C70U) +#define CPG_PLL3FBCKMCNTE (CPG_BASE + 0x0C74U) + +#if defined(__RH850G3K__) +#define RST_BASE (BASE_RESET_ADDR) +#else +#define RST_BASE (0xE6160000U) +#endif +#define RST_MODEMR0 (RST_BASE + 0x0000U) +#define RST_MODEMR1 (RST_BASE + 0x0004U) + +/* Product Register */ +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) + +#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */ + +#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */ +#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */ + +/* DBSC registers */ +#if defined(__RH850G3K__) +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#else +#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#endif + +#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U) +#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U) +#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U) +#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U) +#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U) +#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U) +#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U) +#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U) + +#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs)) +#define DBSC_DBMEMCONF_0_0 (DBSC_D_BASE + 0x0030U) +#define DBSC_DBMEMCONF_0_1 (DBSC_D_BASE + 0x0034U) +#define DBSC_DBMEMCONF_0_2 (DBSC_D_BASE + 0x0038U) +#define DBSC_DBMEMCONF_0_3 (DBSC_D_BASE + 0x003CU) +#define DBSC_DBMEMCONF_1_0 (DBSC_D_BASE + 0x0040U) +#define DBSC_DBMEMCONF_1_1 (DBSC_D_BASE + 0x0044U) +#define DBSC_DBMEMCONF_1_2 (DBSC_D_BASE + 0x0048U) +#define DBSC_DBMEMCONF_1_3 (DBSC_D_BASE + 0x004CU) +#define DBSC_DBMEMCONF_2_0 (DBSC_D_BASE + 0x0050U) +#define DBSC_DBMEMCONF_2_1 (DBSC_D_BASE + 0x0054U) +#define DBSC_DBMEMCONF_2_2 (DBSC_D_BASE + 0x0058U) +#define DBSC_DBMEMCONF_2_3 (DBSC_D_BASE + 0x005CU) +#define DBSC_DBMEMCONF_3_0 (DBSC_D_BASE + 0x0060U) +#define DBSC_DBMEMCONF_3_1 (DBSC_D_BASE + 0x0064U) +#define DBSC_DBMEMCONF_3_2 (DBSC_D_BASE + 0x0068U) +#define DBSC_DBMEMCONF_3_3 (DBSC_D_BASE + 0x006CU) + +#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs)) +#define DBSC_DBMEMCONF_0_0A (DBSC_A_BASE + 0x0030U) +#define DBSC_DBMEMCONF_0_1A (DBSC_A_BASE + 0x0034U) +#define DBSC_DBMEMCONF_0_2A (DBSC_A_BASE + 0x0038U) +#define DBSC_DBMEMCONF_0_3A (DBSC_A_BASE + 0x003CU) +#define DBSC_DBMEMCONF_1_0A (DBSC_A_BASE + 0x0040U) +#define DBSC_DBMEMCONF_1_1A (DBSC_A_BASE + 0x0044U) +#define DBSC_DBMEMCONF_1_2A (DBSC_A_BASE + 0x0048U) +#define DBSC_DBMEMCONF_1_3A (DBSC_A_BASE + 0x004CU) +#define DBSC_DBMEMCONF_2_0A (DBSC_A_BASE + 0x0050U) +#define DBSC_DBMEMCONF_2_1A (DBSC_A_BASE + 0x0054U) +#define DBSC_DBMEMCONF_2_2A (DBSC_A_BASE + 0x0058U) +#define DBSC_DBMEMCONF_2_3A (DBSC_A_BASE + 0x005CU) +#define DBSC_DBMEMCONF_3_0A (DBSC_A_BASE + 0x0060U) +#define DBSC_DBMEMCONF_3_1A (DBSC_A_BASE + 0x0064U) +#define DBSC_DBMEMCONF_3_2A (DBSC_A_BASE + 0x0068U) +#define DBSC_DBMEMCONF_3_3A (DBSC_A_BASE + 0x006CU) + +#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U) + +#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U) +#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U) +#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U) +#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U) + +#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + 0x04U * (x)) +#define DBSC_DBTR0 (DBSC_D_BASE + 0x0300U) +#define DBSC_DBTR1 (DBSC_D_BASE + 0x0304U) +#define DBSC_DBTR2 (DBSC_D_BASE + 0x0308U) +#define DBSC_DBTR3 (DBSC_D_BASE + 0x030CU) +#define DBSC_DBTR4 (DBSC_D_BASE + 0x0310U) +#define DBSC_DBTR5 (DBSC_D_BASE + 0x0314U) +#define DBSC_DBTR6 (DBSC_D_BASE + 0x0318U) +#define DBSC_DBTR7 (DBSC_D_BASE + 0x031CU) +#define DBSC_DBTR8 (DBSC_D_BASE + 0x0320U) +#define DBSC_DBTR9 (DBSC_D_BASE + 0x0324U) +#define DBSC_DBTR10 (DBSC_D_BASE + 0x0328U) +#define DBSC_DBTR11 (DBSC_D_BASE + 0x032CU) +#define DBSC_DBTR12 (DBSC_D_BASE + 0x0330U) +#define DBSC_DBTR13 (DBSC_D_BASE + 0x0334U) +#define DBSC_DBTR14 (DBSC_D_BASE + 0x0338U) +#define DBSC_DBTR15 (DBSC_D_BASE + 0x033CU) +#define DBSC_DBTR16 (DBSC_D_BASE + 0x0340U) +#define DBSC_DBTR17 (DBSC_D_BASE + 0x0344U) +#define DBSC_DBTR18 (DBSC_D_BASE + 0x0348U) +#define DBSC_DBTR19 (DBSC_D_BASE + 0x034CU) +#define DBSC_DBTR20 (DBSC_D_BASE + 0x0350U) +#define DBSC_DBTR21 (DBSC_D_BASE + 0x0354U) +#define DBSC_DBTR22 (DBSC_D_BASE + 0x0358U) +#define DBSC_DBTR23 (DBSC_D_BASE + 0x035CU) +#define DBSC_DBTR24 (DBSC_D_BASE + 0x0360U) +#define DBSC_DBTR25 (DBSC_D_BASE + 0x0364U) +#define DBSC_DBTR26 (DBSC_D_BASE + 0x0368U) +#define DBSC_DBTR27 (DBSC_D_BASE + 0x036CU) +#define DBSC_DBTR28 (DBSC_D_BASE + 0x0370U) +#define DBSC_DBTR29 (DBSC_D_BASE + 0x0374U) +#define DBSC_DBTR30 (DBSC_D_BASE + 0x0378U) +#define DBSC_DBTR31 (DBSC_D_BASE + 0x037CU) +#define DBSC_DBTR32 (DBSC_D_BASE + 0x0380U) +#define DBSC_DBTR33 (DBSC_D_BASE + 0x0384U) +#define DBSC_DBTR34 (DBSC_D_BASE + 0x0388U) +#define DBSC_DBTR35 (DBSC_D_BASE + 0x038CU) +#define DBSC_DBTR36 (DBSC_D_BASE + 0x0390U) +#define DBSC_DBTR37 (DBSC_D_BASE + 0x0394U) + +#define DBSC_DBBL (DBSC_D_BASE + 0x0400U) +#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U) + +#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U) +#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U) + +#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U) + +#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + 0x04U * (x)) +#define DBSC_DBRNK2 (DBSC_D_BASE + 0x0438U) +#define DBSC_DBRNK3 (DBSC_D_BASE + 0x043CU) +#define DBSC_DBRNK4 (DBSC_D_BASE + 0x0440U) +#define DBSC_DBRNK5 (DBSC_D_BASE + 0x0444U) + +#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U) +#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U) +#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U) + +#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBDFISTAT_0 (DBSC_D_BASE + 0x0600U) +#define DBSC_DBDFISTAT_1 (DBSC_D_BASE + 0x0640U) +#define DBSC_DBDFISTAT_2 (DBSC_D_BASE + 0x0680U) +#define DBSC_DBDFISTAT_3 (DBSC_D_BASE + 0x06C0U) + +#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBDFICNT_0 (DBSC_D_BASE + 0x0604U) +#define DBSC_DBDFICNT_1 (DBSC_D_BASE + 0x0644U) +#define DBSC_DBDFICNT_2 (DBSC_D_BASE + 0x0684U) +#define DBSC_DBDFICNT_3 (DBSC_D_BASE + 0x06C4U) + +#define DBSC_DBPDCNT0_0 (DBSC_D_BASE + 0x0610U) +#define DBSC_DBPDCNT0_1 (DBSC_D_BASE + 0x0614U) +#define DBSC_DBPDCNT0_2 (DBSC_D_BASE + 0x0618U) +#define DBSC_DBPDCNT0_3 (DBSC_D_BASE + 0x061CU) + +#define DBSC_DBPDCNT1_0 (DBSC_D_BASE + 0x0650U) +#define DBSC_DBPDCNT1_1 (DBSC_D_BASE + 0x0654U) +#define DBSC_DBPDCNT1_2 (DBSC_D_BASE + 0x0658U) +#define DBSC_DBPDCNT1_3 (DBSC_D_BASE + 0x065CU) + +#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDCNT2_0 (DBSC_D_BASE + 0x0690U) +#define DBSC_DBPDCNT2_1 (DBSC_D_BASE + 0x0694U) +#define DBSC_DBPDCNT2_2 (DBSC_D_BASE + 0x0698U) +#define DBSC_DBPDCNT2_3 (DBSC_D_BASE + 0x069CU) + +#define DBSC_DBPDCNT3_0 (DBSC_D_BASE + 0x06D0U) +#define DBSC_DBPDCNT3_1 (DBSC_D_BASE + 0x06D4U) +#define DBSC_DBPDCNT3_2 (DBSC_D_BASE + 0x06D8U) +#define DBSC_DBPDCNT3_3 (DBSC_D_BASE + 0x06DCU) + +#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDLK_0 (DBSC_D_BASE + 0x0620U) +#define DBSC_DBPDLK_1 (DBSC_D_BASE + 0x0660U) +#define DBSC_DBPDLK_2 (DBSC_D_BASE + 0x06a0U) +#define DBSC_DBPDLK_3 (DBSC_D_BASE + 0x06e0U) + +#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDRGA_0 (DBSC_D_BASE + 0x0624U) +#define DBSC_DBPDRGA_1 (DBSC_D_BASE + 0x0664U) +#define DBSC_DBPDRGA_2 (DBSC_D_BASE + 0x06A4U) +#define DBSC_DBPDRGA_3 (DBSC_D_BASE + 0x06E4U) + +#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDRGD_0 (DBSC_D_BASE + 0x0628U) +#define DBSC_DBPDRGD_1 (DBSC_D_BASE + 0x0668U) +#define DBSC_DBPDRGD_2 (DBSC_D_BASE + 0x06A8U) +#define DBSC_DBPDRGD_3 (DBSC_D_BASE + 0x06E8U) + +#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDSTAT0_0 (DBSC_D_BASE + 0x0630U) +#define DBSC_DBPDSTAT1_0 (DBSC_D_BASE + 0x0670U) + +#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDSTAT0_1 (DBSC_D_BASE + 0x0634U) +#define DBSC_DBPDSTA1T_1 (DBSC_D_BASE + 0x0674U) + +#define DBSC_DBCAM0CTRL0 (DBSC_A_BASE + 0x0940U) + +#define DBSC_DBCAMSTAT0(x) (DBSC_A_BASE + 0x0980U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U)) +#define DBSC_DBCAM0STAT0 (DBSC_A_BASE + 0x0980U) +#define DBSC_DBCAM1STAT0 (DBSC_A_BASE + 0x0990U) +#define DBSC_DBCAM2STAT0 (DBSC_A_BASE + 0x09A0U) +#define DBSC_DBCAM3STAT0 (DBSC_A_BASE + 0x09B0U) + +#define DBSC_DBCAMSTAT1(x) (DBSC_A_BASE + 0x0984U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U)) +#define DBSC_DBCAM0STAT1 (DBSC_A_BASE + 0x0984U) +#define DBSC_DBCAM1STAT1 (DBSC_A_BASE + 0x0994U) +#define DBSC_DBCAM2STAT1 (DBSC_A_BASE + 0x09A4U) +#define DBSC_DBCAM3STAT1 (DBSC_A_BASE + 0x09B4U) + +#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU) + +#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U) + +#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U) + +#define DBSC_DBSCHFCTST01(x) (DBSC_A_BASE + 0x1040U + 0x04U * (x)) +#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U) +#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U) + +#define DBSC_DBSCHQOS(x,y) (DBSC_A_BASE + 0x1100U + 0x10U * (x) + 0x04U * (y)) diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c new file mode 100644 index 0000000..badbd04 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c @@ -0,0 +1,220 @@ +/******************************************************************************* + * Copyright (c) 2022-2025 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC setting function + ******************************************************************************/ +/****************************************************************************** + * @file ecc_enable_v4h.c + * - Version : 0.06 + * @brief Enable setting process of ECC for DRAM. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 09.08.2022 0.01 First Release + * : 22.03.2023 0.02 Added AXI Timeout setting + * : 04.04.2023 0.03 Removed stdio.h and string.h. + * : 24.08.2023 0.04 Removed enable_ecc function. + * : 13.06.2024 0.05 Fix register setting for EDC_CFG, and revise + * : the ecm_lock()/ecm_unlock() process. + * : 07.04.2025 0.06 Remove unused functions. + *****************************************************************************/ + +#include +#include +#include +#include + +#if (ECM_ENABLE == 1) +#include "ecc_enable_v4h.h" +#include "v4h/lpddr5/boot_init_dram_regdef.h" +#include "ecm_enable_v4h.h" + +#define AXI_SICREMAP_NUM (5U) +#define RGID_BASE1 (0xFE600000U) +#define RGID_BASE2 (0xE7A00000U) +#define RGID_BASE3 (0xEB800000U) +#define RGID_BASE4 (0xFD800000U) +#define RGID_BASE5 (0xFEA00000U) + +#define FDT_COUNTER_MASK (0x0000FFFFU) + +static void axi_timeout_setting(void); + +void edc_axi_enable(void) +{ + uint32_t edc_tmp; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers + to inform the external device of the error via the ERROROUT# pin. */ + + /* Set bit 11 - bit 2 of ECMERRTGTR7 to all 0 and bit 11 - bit 2 of + ECMERRCTLR7 to 1. (Error of AXI-Bus ECM of each hierarchy) */ + edc_tmp = mem_read32(ECMERRTGTR7); + edc_tmp &= ~(0x3FFU << 2U); + ecm_write(ECMERRTGTR7, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR7); + edc_tmp |= (0x3FFU << 2U); + ecm_write(ECMERRCTLR7, edc_tmp); + + /* Set bit 28 - bit 16 of ECMERRTGTR39 to all 0 and bit 28 - bit 16 of + ECMERRCTLR39 to 1. (Error of AXI-Bus ECM of each hierarchy) */ + edc_tmp = mem_read32(ECMERRTGTR39); + edc_tmp &= ~(0x1FFFU << 16U); + ecm_write(ECMERRTGTR39, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR39); + edc_tmp |= (0x1FFFU << 16U); + ecm_write(ECMERRCTLR39, edc_tmp); + + /* Set bit 26 of ECMERRTGTR1 to 0 and bit 26 of + ECMERRCTLR1 to 1. (CCI bus EDC error) */ + edc_tmp = mem_read32(ECMERRTGTR1); + edc_tmp &= ~(0x1U << 26U); + ecm_write(ECMERRTGTR1, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR1); + edc_tmp |= (0x1U << 26U); + ecm_write(ECMERRCTLR1, edc_tmp); + + axi_timeout_setting(); + + /* Lock the ECM registers */ + ecm_lock(); +} + +void edc_vram_enable(void) +{ + uint32_t edc_tmp; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers + to inform the external device of the error via the ERROROUT# pin. */ + + /* Set bit 30 of ECMERRTGTR7 to 0 and bit 30 of ECMERRCTLR7 to 1. + (RT-VRAM edc 1-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR7); + edc_tmp &= ~(0x1U << 30U); + ecm_write(ECMERRTGTR7, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR7); + edc_tmp |= (0x1U << 30U); + ecm_write(ECMERRCTLR7, edc_tmp); + + /* Set bit 29 of ECMERRTGTR7 to 0 and bit 29 of ECMERRCTLR7 to 1. + (RT-VRAM edc multi-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR7); + edc_tmp &= ~(0x1U << 29U); + ecm_write(ECMERRTGTR7, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR7); + edc_tmp |= (0x1U << 29U); + ecm_write(ECMERRCTLR7, edc_tmp); + + /* Set bit 19 of ECMERRTGTR17 to 0 and bit 19 of ECMERRCTLR17 to 1. + (RT-VRAM edc 1-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR17); + edc_tmp &= ~(0x1U << 19U); + ecm_write(ECMERRTGTR17, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR17); + edc_tmp |= (0x1U << 19U); + ecm_write(ECMERRCTLR17, edc_tmp); + + /* Set bit 18 of ECMERRTGTR17 to 0 and bit 18 of ECMERRCTLR17 to 1. + (RT-VRAM edc multi-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR17); + edc_tmp &= ~(0x1U << 18U); + ecm_write(ECMERRTGTR17, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR17); + edc_tmp |= (0x1U << 18U); + ecm_write(ECMERRCTLR17, edc_tmp); + + /* Set bit 0 of EDC_CFG to 1. (EDC Error Control) */ + edc_tmp = mem_read32(EDC_CFG); + edc_tmp |= (0x1U << 0U); + mem_write32(EDC_CFG, edc_tmp); + + /* Lock the ECM registers */ + ecm_lock(); +} + +static void axi_timeout_setting(void) +{ + uint32_t reg; + uint32_t loop; + REMAP_TABLE axi_remap_tbl[AXI_SICREMAP_NUM] = { + {RGID_BASE1, 0U}, + {RGID_BASE2, 0U}, + {RGID_BASE3, 0U}, + {RGID_BASE4, 0U}, + {RGID_BASE5, 0U}, + }; + + /* Register of AXI Base */ + for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++) + { + remap_register(axi_remap_tbl[loop].base_addr, &axi_remap_tbl[loop].rmp_addr); + } + + /* Set the COUNTER bits of the FDT_* registers for all safety-related modules to minimum value with 1ms or more. */ + for (loop = 0U; loop < FDT_REG_MAX; loop++) + { + reg = mem_read32(g_fdt_tbl[loop].reg_addr); + reg &= ~(FDT_COUNTER_MASK); + reg |= g_fdt_tbl[loop].value; + mem_write32(g_fdt_tbl[loop].reg_addr, reg); + + INFO("FDT[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_fdt_tbl[loop].reg_addr), g_fdt_tbl[loop].value); + } + + for(loop = 0U; loop < INTEN_REG_MAX; loop++) + { + /* Set access protection setting value of Region ID (AXI bus of Region ID register) */ + mem_write32(g_inten_tbl[loop].reg_addr, g_inten_tbl[loop].value); + + INFO("INTEN[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_inten_tbl[loop].reg_addr), g_inten_tbl[loop].value); + } + + /* Unregister of AXI Base */ + for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++) + { + remap_unregister(axi_remap_tbl[loop].rmp_addr); + } + + wdt_restart(); +} +#endif /* ECM_ENABLE == 1 */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h new file mode 100644 index 0000000..8a04f4b --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h @@ -0,0 +1,123 @@ +/******************************************************************************* + * Copyright (c) 2022-2024 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC driver header + ******************************************************************************/ + +#ifndef ECC_PROTECT +#define ECC_PROTECT +#include "remap_register.h" +/* DBSC registers */ +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#define ECM_BASE (BASE_ECC_ADDR) +#else +#include +#include +#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#define ECM_BASE (0xE6250000U) +#endif/* defined(__RH850G3K__) */ + +#define RTVRAM_REG_BASE (0xFFEC0000U) + +void edc_axi_enable(void); +void edc_vram_enable(void); + +#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U) +#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U) +#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U) + +#define DBSC_DBACEN0 (DBSC_A_BASE + 0x0200U) +#define DBSC_DBACEN1 (DBSC_DBACEN0 + 0x8000U) + +#define ECMWACNTR (ECM_BASE + 0x0A04U) +#define ECMWPCNTR (ECM_BASE + 0x0A00U) +#define ECMERRTGTR0 (ECM_BASE + 0x0200U) +#define ECMERRCTLR0 (ECM_BASE + 0x0000U) +#define ECMERRTGTR1 (ECM_BASE + 0x0200U + 0x4U * 1U) +#define ECMERRCTLR1 (ECM_BASE + 0x0000U + 0x4U * 1U) +#define ECMERRTGTR7 (ECM_BASE + 0x0200U + 0x4U * 7U) +#define ECMERRCTLR7 (ECM_BASE + 0x0000U + 0x4U * 7U) +#define ECMERRTGTR17 (ECM_BASE + 0x0200U + 0x4U * 17U) +#define ECMERRCTLR17 (ECM_BASE + 0x0000U + 0x4U * 17U) +#define ECMERRTGTR39 (ECM_BASE + 0x0200U + 0x4U * 39U) +#define ECMERRCTLR39 (ECM_BASE + 0x0000U + 0x4U * 39U) +#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U) +#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U) +#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U) +#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U) +#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U) +#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U) +#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U) +#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U) +#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U) +#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U) +#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U) +#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U) +#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U) +#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U) +#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U) +#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U) + +#define DB0FSDRAMECCAREA0 (DBSC_A_BASE + 0x7450U) +#define DB0FSDRAMECCAREA1 (DBSC_A_BASE + 0x7454U) +#define DB1FSDRAMECCAREA0 (DB0FSDRAMECCAREA0 + 0x8000U) +#define DB1FSDRAMECCAREA1 (DB0FSDRAMECCAREA1 + 0x8000U) + +#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U) +#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U) + +#define EDC_CFG (RTVRAM_REG_BASE + 0x4110U) + +/********************* Set by the user *********************/ +/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */ +#define ECC_PROT_SIZE00 (0x1000U) +#define ECC_PROT_SIZE01 (0x1000U) +#define ECC_PROT_SIZE10 (0x1000U) +#define ECC_PROT_SIZE11 (0x1000U) + +/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */ +#define START_ECC_INIT_AREA00 (0x00000000U) +#define START_ECC_INIT_AREA10 (0x00000000U) +#define END_ECC_INIT_AREA00 (0x00000FFFU) +#define END_ECC_INIT_AREA10 (0x00000FFFU) + +/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */ +#define START_ECC_INIT_AREA01 (0x00000000U) +#define START_ECC_INIT_AREA11 (0x00000000U) +#define END_ECC_INIT_AREA01 (0x00000FFFU) +#define END_ECC_INIT_AREA11 (0x00000FFFU) +/*********** Other settings cannot be changed ***************/ + +#endif/* ECC_PROTECT */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c new file mode 100644 index 0000000..fe88dd5 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c @@ -0,0 +1,531 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM initialize function + ******************************************************************************/ +/****************************************************************************** + * @file ecm_enable_v4h.c + * - Version : 0.01 + * @brief ECM setting. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.01.2025 0.01 First Release + *****************************************************************************/ + +#include +#include "ecm_enable_v4h.h" + +#if (ECM_ERROR_ENABLE == 1) +#include "log.h" +#endif /* ECM_ERROR_ENABLE == 1 */ +#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1)) +#include "ecc_enable_v4h.h" +#include "mem_io.h" +#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +#define TYPE1_ECM_REG_MAX (13U) +#define TYPE2_ECM_REG_MAX (22U) +#define TYPE3_ECM_CTLREG_MAX (1U) +#define TYPE3_ECM_TGTREG_MAX (2U) + +typedef struct{ + uint32_t phys_addr; /* Physical address of ECM registers. */ + uint32_t value; /* Setting value of ECM registers. */ +} ECM_ERROR_TABLE; +#endif /* ECM_ERROR_ENABLE == 1 */ + +#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1)) +void ecm_unlock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0001U); +} + +void ecm_write(uint32_t adr, uint32_t val) +{ + mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU))); + mem_write32(adr, val); +} + +void ecm_lock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0000U); +} +#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_init_setting(void) +{ + uint32_t reg; + uint32_t loop; + + const ECM_ERROR_TABLE ecmerrctlr_type1_tbl[TYPE1_ECM_REG_MAX] = { + [0] = {0xFD850000U, 0x00381000U}, /* ECMERRCTLR0 */ + [1] = {0xFD850004U, 0xA400C000U}, /* ECMERRCTLR1 */ + /* Skip ECMERRCTLR2 setting */ + /* Skip ECMERRCTLR3 setting */ + /* Skip ECMERRCTLR4 setting */ + /* Skip ECMERRCTLR5 setting */ + [2] = {0xFD850018U, 0xCC000000U}, /* ECMERRCTLR6 */ + [3] = {0xFD85001CU, 0x0C000000U}, /* ECMERRCTLR7 */ + /* Skip ECMERRCTLR8 setting */ + /* Skip ECMERRCTLR9 setting */ + /* Skip ECMERRCTLR10 setting */ + /* Skip ECMERRCTLR11 setting */ + /* Skip ECMERRCTLR12 setting */ + /* Skip ECMERRCTLR13 setting */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + /* Skip ECMERRCTLR16 setting */ + [4] = {0xFD850044U, 0x2D000000U}, /* ECMERRCTLR17 */ + [5] = {0xFD850048U, 0x0EC0003FU}, /* ECMERRCTLR18 */ + [6] = {0xFD85004CU, 0x00FFFF08U}, /* ECMERRCTLR19 */ + [7] = {0xFD850050U, 0x0000001EU}, /* ECMERRCTLR20 */ + [8] = {0xFD850054U, 0x9F800000U}, /* ECMERRCTLR21 */ + /* Skip ECMERRCTLR22 setting */ + /* Skip ECMERRCTLR23 setting */ + /* Skip ECMERRCTLR24 setting */ + /* Skip ECMERRCTLR25 setting */ + /* Skip ECMERRCTLR26 setting */ + /* Skip ECMERRCTLR27 setting */ + /* Skip ECMERRCTLR28 setting */ + /* Skip ECMERRCTLR29 setting */ + /* Skip ECMERRCTLR30 setting */ + /* Skip ECMERRCTLR31 setting */ + /* Skip ECMERRCTLR32 setting */ + /* Skip ECMERRCTLR33 setting */ + /* Skip ECMERRCTLR34 setting */ + [9] = {0xFD85008CU, 0x300003C0U}, /* ECMERRCTLR35 */ + /* Skip ECMERRCTLR36 setting */ + /* Skip ECMERRCTLR37 setting */ + [10] = {0xFD850098U, 0x33300054U}, /* ECMERRCTLR38 */ + /* Skip ECMERRCTLR39 setting */ + /* Skip ECMERRCTLR40 setting */ + [11] = {0xFD8500A4U, 0x01000880U}, /* ECMERRCTLR41 */ + [12] = {0xFD8500A8U, 0x00040020U}, /* ECMERRCTLR42 */ + }; + + const ECM_ERROR_TABLE ecmerrtgtr_type1_tbl[TYPE1_ECM_REG_MAX] = { + [0] = {0xFD850200U, 0x00381000U}, /* ECMERRTGTR0 */ + [1] = {0xFD850204U, 0xA400C000U}, /* ECMERRTGTR1 */ + /* Skip ECMERRTGTR2 setting */ + /* Skip ECMERRTGTR3 setting */ + /* Skip ECMERRTGTR4 setting */ + /* Skip ECMERRTGTR5 setting */ + [2] = {0xFD850218U, 0xCC000000U}, /* ECMERRTGTR6 */ + [3] = {0xFD85021CU, 0x0C000000U}, /* ECMERRTGTR7 */ + /* Skip ECMERRTGTR8 setting */ + /* Skip ECMERRTGTR9 setting */ + /* Skip ECMERRTGTR10 setting */ + /* Skip ECMERRTGTR11 setting */ + /* Skip ECMERRTGTR12 setting */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + /* Skip ECMERRTGTR16 setting */ + [4] = {0xFD850244U, 0x2D000000U}, /* ECMERRTGTR17 */ + [5] = {0xFD850248U, 0x0EC0003FU}, /* ECMERRTGTR18 */ + [6] = {0xFD85024CU, 0x00FFFF08U}, /* ECMERRTGTR19 */ + [7] = {0xFD850250U, 0x0000001EU}, /* ECMERRTGTR20 */ + [8] = {0xFD850254U, 0x9F800000U}, /* ECMERRTGTR21 */ + /* Skip ECMERRTGTR22 setting */ + /* Skip ECMERRTGTR23 setting */ + /* Skip ECMERRTGTR24 setting */ + /* Skip ECMERRTGTR25 setting */ + /* Skip ECMERRTGTR26 setting */ + /* Skip ECMERRTGTR27 setting */ + /* Skip ECMERRTGTR28 setting */ + /* Skip ECMERRTGTR29 setting */ + /* Skip ECMERRTGTR30 setting */ + /* Skip ECMERRTGTR31 setting */ + /* Skip ECMERRTGTR32 setting */ + /* Skip ECMERRTGTR33 setting */ + /* Skip ECMERRTGTR34 setting */ + [9] = {0xFD85028CU, 0x300003C0U}, /* ECMERRTGTR35 */ + /* Skip ECMERRTGTR36 setting */ + /* Skip ECMERRTGTR37 setting */ + [10] = {0xFD850298U, 0x33300054U}, /* ECMERRTGTR38 */ + /* Skip ECMERRTGTR39 setting */ + /* Skip ECMERRTGTR40 setting */ + [11] = {0xFD8502A4U, 0x01000880U}, /* ECMERRTGTR41 */ + [12] = {0xFD8502A8U, 0x00040020U}, /* ECMERRTGTR42 */ + }; + + const ECM_ERROR_TABLE ecmerrctlr_type2_tbl[TYPE2_ECM_REG_MAX] = { + [0] = {0xFD850000U, 0x4000000FU}, /* ECMERRCTLR0 */ + [1] = {0xFD850004U, 0x1C004000U}, /* ECMERRCTLR1 */ + [2] = {0xFD850008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */ + [3] = {0xFD85000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */ + [4] = {0xFD850010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */ + [5] = {0xFD850014U, 0xC1FFFFFFU}, /* ECMERRCTLR5 */ + [6] = {0xFD850018U, 0x15000A80U}, /* ECMERRCTLR6 */ + [7] = {0xFD85001CU, 0x00803481U}, /* ECMERRCTLR7 */ + /* Skip ECMERRCTLR8 setting */ + /* Skip ECMERRCTLR9 setting */ + /* Skip ECMERRCTLR10 setting */ + /* Skip ECMERRCTLR11 setting */ + /* Skip ECMERRCTLR12 setting */ + /* Skip ECMERRCTLR13 setting */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + [8] = {0xFD850040U, 0x00003E9FU}, /* ECMERRCTLR16 */ + [9] = {0xFD850044U, 0x00938060U}, /* ECMERRCTLR17 */ + [10] = {0xFD850048U, 0x003C1FC0U}, /* ECMERRCTLR18 */ + [11] = {0xFD85004CU, 0xFF0000F0U}, /* ECMERRCTLR19 */ + [12] = {0xFD850050U, 0x02222220U}, /* ECMERRCTLR20 */ + [13] = {0xFD850054U, 0x0061BE0FU}, /* ECMERRCTLR21 */ + /* Skip ECMERRCTLR22 setting */ + /* Skip ECMERRCTLR23 setting */ + /* Skip ECMERRCTLR24 setting */ + /* Skip ECMERRCTLR25 setting */ + /* Skip ECMERRCTLR26 setting */ + /* Skip ECMERRCTLR27 setting */ + /* Skip ECMERRCTLR28 setting */ + /* Skip ECMERRCTLR29 setting */ + /* Skip ECMERRCTLR30 setting */ + /* Skip ECMERRCTLR31 setting */ + [14] = {0xFD850080U, 0x03E9043BU}, /* ECMERRCTLR32 */ + [15] = {0xFD850084U, 0x03E9043BU}, /* ECMERRCTLR33 */ + /* Skip ECMERRCTLR34 setting */ + [16] = {0xFD85008CU, 0xC3F00C00U}, /* ECMERRCTLR35 */ + [17] = {0xFD850090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */ + /* Skip ECMERRCTLR37 setting */ + [18] = {0xFD850098U, 0x00000002U}, /* ECMERRCTLR38 */ + /* Skip ECMERRCTLR39 setting */ + [19] = {0xFD8500A0U, 0x000067FEU}, /* ECMERRCTLR40 */ + [20] = {0xFD8500A4U, 0x20010000U}, /* ECMERRCTLR41 */ + [21] = {0xFD8500A8U, 0x00800400U}, /* ECMERRCTLR42 */ + }; + + const ECM_ERROR_TABLE ecmerrtgtr_type2_tbl[TYPE2_ECM_REG_MAX] = { + [0] = {0xFD850200U, 0x4000000FU}, /* ECMERRTGTR0 */ + [1] = {0xFD850204U, 0x1C004000U}, /* ECMERRTGTR1 */ + [2] = {0xFD850208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */ + [3] = {0xFD85020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */ + [4] = {0xFD850210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */ + [5] = {0xFD850214U, 0xC1FFFFFFU}, /* ECMERRTGTR5 */ + [6] = {0xFD850218U, 0x15000A80U}, /* ECMERRTGTR6 */ + [7] = {0xFD85021CU, 0x00803481U}, /* ECMERRTGTR7 */ + /* Skip ECMERRTGTR8 setting */ + /* Skip ECMERRTGTR9 setting */ + /* Skip ECMERRTGTR10 setting */ + /* Skip ECMERRTGTR11 setting */ + /* Skip ECMERRTGTR12 setting */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [8] = {0xFD850240U, 0x00003E9FU}, /* ECMERRTGTR16 */ + [9] = {0xFD850244U, 0x00938060U}, /* ECMERRTGTR17 */ + [10] = {0xFD850248U, 0x003C1FC0U}, /* ECMERRTGTR18 */ + [11] = {0xFD85024CU, 0xFF0000F0U}, /* ECMERRTGTR19 */ + [12] = {0xFD850250U, 0x02222220U}, /* ECMERRTGTR20 */ + [13] = {0xFD850254U, 0x0061BE0FU}, /* ECMERRTGTR21 */ + /* Skip ECMERRTGTR22 setting */ + /* Skip ECMERRTGTR23 setting */ + /* Skip ECMERRTGTR24 setting */ + /* Skip ECMERRTGTR25 setting */ + /* Skip ECMERRTGTR26 setting */ + /* Skip ECMERRTGTR27 setting */ + /* Skip ECMERRTGTR28 setting */ + /* Skip ECMERRTGTR29 setting */ + /* Skip ECMERRTGTR30 setting */ + /* Skip ECMERRTGTR31 setting */ + [14] = {0xFD850280U, 0x03E9043BU}, /* ECMERRTGTR32 */ + [15] = {0xFD850284U, 0x03E9043BU}, /* ECMERRTGTR33 */ + /* Skip ECMERRTGTR34 setting */ + [16] = {0xFD85028CU, 0xC3F00C00U}, /* ECMERRTGTR35 */ + [17] = {0xFD850290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */ + /* Skip ECMERRTGTR37 setting */ + [18] = {0xFD850298U, 0x00000002U}, /* ECMERRTGTR38 */ + /* Skip ECMERRTGTR39 setting */ + [19] = {0xFD8502A0U, 0x000067FEU}, /* ECMERRTGTR40 */ + [20] = {0xFD8502A4U, 0x20010000U}, /* ECMERRTGTR41 */ + [21] = {0xFD8502A8U, 0x00800400U}, /* ECMERRTGTR42 */ + }; + + const ECM_ERROR_TABLE ecmerrctlr_type3_tbl[TYPE3_ECM_CTLREG_MAX] = { + /* Skip ECMERRCTLR0 setting */ + /* Skip ECMERRCTLR1 setting */ + /* Skip ECMERRCTLR2 setting */ + /* Skip ECMERRCTLR3 setting */ + /* Skip ECMERRCTLR4 setting */ + /* Skip ECMERRCTLR5 setting */ + /* Skip ECMERRCTLR6 setting */ + /* Skip ECMERRCTLR7 setting */ + /* Skip ECMERRCTLR8 setting */ + /* Skip ECMERRCTLR9 setting */ + /* Skip ECMERRCTLR10 setting */ + /* Skip ECMERRCTLR11 setting */ + /* Skip ECMERRCTLR12 setting */ + /* Skip ECMERRCTLR13 setting */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + [0] = {0xFD850040U, 0x3FFFC000U}, /* ECMERRCTLR16 */ + /* Skip ECMERRCTLR17 setting */ + /* Skip ECMERRCTLR18 setting */ + /* Skip ECMERRCTLR19 setting */ + /* Skip ECMERRCTLR20 setting */ + /* Skip ECMERRCTLR21 setting */ + /* Skip ECMERRCTLR22 setting */ + /* Skip ECMERRCTLR23 setting */ + /* Skip ECMERRCTLR24 setting */ + /* Skip ECMERRCTLR25 setting */ + /* Skip ECMERRCTLR26 setting */ + /* Skip ECMERRCTLR27 setting */ + /* Skip ECMERRCTLR28 setting */ + /* Skip ECMERRCTLR29 setting */ + /* Skip ECMERRCTLR30 setting */ + /* Skip ECMERRCTLR31 setting */ + /* Skip ECMERRCTLR32 setting */ + /* Skip ECMERRCTLR33 setting */ + /* Skip ECMERRCTLR34 setting */ + /* Skip ECMERRCTLR35 setting */ + /* Skip ECMERRCTLR36 setting */ + /* Skip ECMERRCTLR37 setting */ + /* Skip ECMERRCTLR38 setting */ + /* Skip ECMERRCTLR39 setting */ + /* Skip ECMERRCTLR40 setting */ + /* Skip ECMERRCTLR41 setting */ + /* Skip ECMERRCTLR42 setting */ + }; + + const ECM_ERROR_TABLE ecmerrtgtr_type3_tbl[TYPE3_ECM_TGTREG_MAX] = { + [0] = {0xFD850200U, 0x80000000U}, /* ECMERRTGTR0 */ + /* Skip ECMERRTGTR1 setting */ + /* Skip ECMERRTGTR2 setting */ + /* Skip ECMERRTGTR3 setting */ + /* Skip ECMERRTGTR4 setting */ + /* Skip ECMERRTGTR5 setting */ + /* Skip ECMERRTGTR6 setting */ + /* Skip ECMERRTGTR7 setting */ + /* Skip ECMERRTGTR8 setting */ + /* Skip ECMERRTGTR9 setting */ + /* Skip ECMERRTGTR10 setting */ + /* Skip ECMERRTGTR11 setting */ + /* Skip ECMERRTGTR12 setting */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [1] = {0xFD850240U, 0x3FFFC000U}, /* ECMERRTGTR16 */ + /* Skip ECMERRTGTR17 setting */ + /* Skip ECMERRTGTR18 setting */ + /* Skip ECMERRTGTR19 setting */ + /* Skip ECMERRTGTR20 setting */ + /* Skip ECMERRTGTR21 setting */ + /* Skip ECMERRTGTR22 setting */ + /* Skip ECMERRTGTR23 setting */ + /* Skip ECMERRTGTR24 setting */ + /* Skip ECMERRTGTR25 setting */ + /* Skip ECMERRTGTR26 setting */ + /* Skip ECMERRTGTR27 setting */ + /* Skip ECMERRTGTR28 setting */ + /* Skip ECMERRTGTR29 setting */ + /* Skip ECMERRTGTR30 setting */ + /* Skip ECMERRTGTR31 setting */ + /* Skip ECMERRTGTR32 setting */ + /* Skip ECMERRTGTR33 setting */ + /* Skip ECMERRTGTR34 setting */ + /* Skip ECMERRTGTR35 setting */ + /* Skip ECMERRTGTR36 setting */ + /* Skip ECMERRTGTR37 setting */ + /* Skip ECMERRTGTR38 setting */ + /* Skip ECMERRTGTR39 setting */ + /* Skip ECMERRTGTR40 setting */ + /* Skip ECMERRTGTR41 setting */ + /* Skip ECMERRTGTR42 setting */ + }; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + NOTICE("ECMERRCTLR and ECMERRTGTR register initial setting.\n"); + /* For the initial setting flow for Type-1, please refer to the following + * section in the "SAN(Safety Application Note)." + * Section 4.1.2.5 : (1) + * Section 4.1.4.5 : (1) + * Section 4.12.1.5 : (1) + * Section 4.13.1.5 : (1) + * Section 4.14.5 : (1) + * Section 4.16.5 : (1) + * Section 4.18.5 : (1) + * Section 4.2.7.5 : (1) + * Section 4.2.9.5 : (1) + * Section 4.23.5 : (1) + * Section 4.3.11.5 : (1) + * Section 4.3.12.5 : (1) + * Section 4.3.14.5 : (1) + * Section 4.3.19.5 : (1) + * Section 4.3.21.5 : (1) + * Section 4.4.14.5 : (1) + * Section 4.4.16.5 : (3) + * Section 4.4.18.5 : (1) + * Section 4.4.20.5 : (1) + * Section 4.4.3.5 : (1) + * Section 4.4.4.5 : (1) + * Section 4.4.6.5 : (1) + * Section 4.4.7.5 : (1) + * Section 4.4.9.5 : (1) + * Section 4.5.1.5 : (1) + * Section 4.7.1.5 : (1) + * Section 4.7.10.5 : (1) + * Section 4.7.3.5 : (1) + * Section 4.7.4.5 : (1) + * Section 4.7.7.5 : (1) + * Section 4.7.8.5 : (1) + * Section 5.6.5 : (1) + * Section 5.8.1.5 : (1) + */ + for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++) + { + reg = mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr); + reg |= (ecmerrctlr_type1_tbl[loop].value); + ecm_write(ecmerrctlr_type1_tbl[loop].phys_addr, reg); + + INFO("[Type-1]ECMERRCTLR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", + loop, + ecmerrctlr_type1_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr), + ecmerrctlr_type1_tbl[loop].value); + } + + for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++) + { + reg = mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr); + reg &= ~(ecmerrtgtr_type1_tbl[loop].value); + ecm_write(ecmerrtgtr_type1_tbl[loop].phys_addr, reg); + + INFO("[Type-1]ECMERRTGTR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", + loop, + ecmerrtgtr_type1_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr), + ecmerrtgtr_type1_tbl[loop].value); + } + + /* For the initial setting flow for Type-2, please refer to the following + * section in the "SAN(Safety Application Note)." + * Section 4.1.1.5 : (1) + * Section 4.12.2.5 : (1) + * Section 4.12.3.5 : (1) + * Section 4.15.5 : (1) + * Section 4.16.5 : (1) + * Section 4.2.1.5 : (1) + * Section 4.2.10.5 : (1) + * Section 4.2.12.5 : (1) + * Section 4.2.2.5 : (1) + * Section 4.2.4.5 : (1) + * Section 4.2.8.5 : (1) + * Section 4.3.1.5 : (1) + * Section 4.3.10.5 : (1) + * Section 4.3.11.5 : (1) + * Section 4.3.12.5 : (1) + * Section 4.3.13.5 : (1) + * Section 4.3.15.5 : (1) + * Section 4.3.16.5 : (1) + * Section 4.3.2.5 : (1) + * Section 4.3.5.5 : (1) + * Section 4.3.7.5 : (1) + * Section 4.3.8.5 : (1) + * Section 4.4.10.5 : (1) + * Section 4.4.12.5 : (8) + * Section 4.4.13.5 : (1) + * Section 4.4.15.5 : (1) + * Section 4.4.2.5 : (1) + * Section 4.5.3.5 : (1) + * Section 4.6.5 : (1) + * Section 4.7.2.5 : (1) + * Section 5.11.5 : (1) + * Section 5.12.5 : (1) + * Section 5.13.5 : (1) + * Section 5.4.5 : (1) + * Section 5.8.2.5 : (1) + */ + for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++) + { + /* Initial Setting Type-2 for ECMERRCTLR registers */ + reg = mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr); + reg |= (ecmerrctlr_type2_tbl[loop].value); + ecm_write(ecmerrctlr_type2_tbl[loop].phys_addr, reg); + + INFO("[Type-2]ECMERRCTLR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", + loop, + ecmerrctlr_type2_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr), + ecmerrctlr_type2_tbl[loop].value); + } + + for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++) + { + /* Initial Setting Type-2 for ECMERRTGTR registers */ + reg = mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr); + reg &= ~(ecmerrtgtr_type2_tbl[loop].value); + ecm_write(ecmerrtgtr_type2_tbl[loop].phys_addr, reg); + + INFO("[Type-2]ECMERRTGTR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", + loop, + ecmerrtgtr_type2_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr), + ecmerrtgtr_type2_tbl[loop].value); + } + + /* For the initial setting flow for Type-3, please refer to the following + * section in the "SAN(Safety Application Note)." + * Section 4.19.1.5 : (3) + * Section 6.2.5 : (12) + */ + for (loop = 0U; loop < TYPE3_ECM_CTLREG_MAX; loop++) + { + /* Initial Setting Type-3 for ECMERRCTLR registers */ + reg = mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr); + reg |= (ecmerrctlr_type3_tbl[loop].value); + ecm_write(ecmerrctlr_type3_tbl[loop].phys_addr, reg); + + INFO("[Type-3]ECMERRCTLR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", + loop, + ecmerrctlr_type3_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr), + ecmerrctlr_type3_tbl[loop].value); + } + + for (loop = 0U; loop < TYPE3_ECM_TGTREG_MAX; loop++) + { + /* Initial Setting Type-3 for ECMERRTGTR registers */ + reg = mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr); + reg &= ~(ecmerrtgtr_type3_tbl[loop].value); + ecm_write(ecmerrtgtr_type3_tbl[loop].phys_addr, reg); + + INFO("[Type-3]ECMERRTGTR[\t%d]\t(0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", + loop, + ecmerrtgtr_type3_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr), + ecmerrtgtr_type3_tbl[loop].value); + } + + /* Lock the ECM registers */ + ecm_lock(); +} +/* End of function ecm_init_setting(void) */ +#endif /* ECM_ERROR_ENABLE == 1 */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h new file mode 100644 index 0000000..fa5a8a6 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM driver header + ******************************************************************************/ + +#ifndef ECM_ENABLE_V4H +#define ECM_ENABLE_V4H + +#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1)) +void ecm_unlock(void); +void ecm_write(uint32_t adr, uint32_t val); +void ecm_lock(void); +#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_init_setting(void); +#endif /* ECM_ERROR_ENABLE == 1 */ + +#endif/* ECM_ENABLE_V4H */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h new file mode 100644 index 0000000..8cdb901 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h @@ -0,0 +1,302 @@ +/******************************************************************************* + * Copyright (c) 2015-2022 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +#if defined(__RH850G3K__) +#include "remap_register.h" +#endif + +#define RCAR_DDR_VERSION "rev.0.08rc7" +#define DRAM_CH_CNT 0x04 +#define SLICE_CNT 0x02 +#define CS_CNT 0x02 + +/* for pll setting */ +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) +#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb))) + +/* for ddr density setting */ +#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30) | ((row) << 24) | ((BG) << 20) | ((bank) << 16) | ((col) << 8) | (dw)) +#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density) % 2, ((density) + 1) / 2 + (28 - 2 - 2 - 10 - 1), 2, 2, 10, 1)) /* 16bit */ +#define DBMEMCONF_VAL(ch,cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs))) + +/* system registers : CPG */ +#define CPG_FRQCRD_KICK_BIT (1U << 31) +#define CPG_PLL3CR0_KICK_BIT (1U << 31) + +#define CPG_PLLECR_PLL3E_BIT (1U << 3) +#define CPG_PLLECR_PLL3ST_BIT (1U << 11) + +#if defined(__RH850G3K__) +#define CPG_BASE (BASE_CPG_ADDR) +#else +#define CPG_BASE (0xE6150000U) +#endif +#define CPG_CPGWPR (CPG_BASE + 0x0000U) +#define CPG_CPGWPCR (CPG_BASE + 0x0004U) +#define CPG_FRQCRA (CPG_BASE + 0x0800U) +#define CPG_FRQCRB (CPG_BASE + 0x0804U) +#define CPG_FRQCRC (CPG_BASE + 0x0808U) +#define CPG_FRQCRD0 (CPG_BASE + 0x080CU) +#define CPG_PLLECR (CPG_BASE + 0x0820U) +#define CPG_PLL3CR0 (CPG_BASE + 0x083CU) +#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U) +#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U) +#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U) +#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U) +#define CPG_SRCR4 (CPG_BASE + 0x2C10U) +#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U) + +#define CPG_PLL3FBCKMCSR (CPG_BASE + 0x0C60U) +#define CPG_PLL3FBCKMECR (CPG_BASE + 0x0C64U) +#define CPG_PLL3FBCKMLCH (CPG_BASE + 0x0C68U) +#define CPG_PLL3FBCKMLCL (CPG_BASE + 0x0C6CU) +#define CPG_PLL3FBCKMCNT (CPG_BASE + 0x0C70U) +#define CPG_PLL3FBCKMCNTE (CPG_BASE + 0x0C74U) + +#if defined(__RH850G3K__) +#define RST_BASE (BASE_RESET_ADDR) +#else +#define RST_BASE (0xE6160000U) +#endif +#define RST_MODEMR0 (RST_BASE + 0x0000U) +#define RST_MODEMR1 (RST_BASE + 0x0004U) + +/* Product Register */ +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) + +#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */ + +#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */ +#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */ + +/* DBSC registers */ +#if defined(__RH850G3K__) +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#else +#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#endif + +#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U) +#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U) +#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U) +#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U) +#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U) +#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U) +#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U) +#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U) + +#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs)) +#define DBSC_DBMEMCONF_0_0 (DBSC_D_BASE + 0x0030U) +#define DBSC_DBMEMCONF_0_1 (DBSC_D_BASE + 0x0034U) +#define DBSC_DBMEMCONF_0_2 (DBSC_D_BASE + 0x0038U) +#define DBSC_DBMEMCONF_0_3 (DBSC_D_BASE + 0x003CU) +#define DBSC_DBMEMCONF_1_0 (DBSC_D_BASE + 0x0040U) +#define DBSC_DBMEMCONF_1_1 (DBSC_D_BASE + 0x0044U) +#define DBSC_DBMEMCONF_1_2 (DBSC_D_BASE + 0x0048U) +#define DBSC_DBMEMCONF_1_3 (DBSC_D_BASE + 0x004CU) +#define DBSC_DBMEMCONF_2_0 (DBSC_D_BASE + 0x0050U) +#define DBSC_DBMEMCONF_2_1 (DBSC_D_BASE + 0x0054U) +#define DBSC_DBMEMCONF_2_2 (DBSC_D_BASE + 0x0058U) +#define DBSC_DBMEMCONF_2_3 (DBSC_D_BASE + 0x005CU) +#define DBSC_DBMEMCONF_3_0 (DBSC_D_BASE + 0x0060U) +#define DBSC_DBMEMCONF_3_1 (DBSC_D_BASE + 0x0064U) +#define DBSC_DBMEMCONF_3_2 (DBSC_D_BASE + 0x0068U) +#define DBSC_DBMEMCONF_3_3 (DBSC_D_BASE + 0x006CU) + +#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + 0x10U * (ch) + 0x04U * (cs)) +#define DBSC_DBMEMCONF_0_0A (DBSC_A_BASE + 0x0030U) +#define DBSC_DBMEMCONF_0_1A (DBSC_A_BASE + 0x0034U) +#define DBSC_DBMEMCONF_0_2A (DBSC_A_BASE + 0x0038U) +#define DBSC_DBMEMCONF_0_3A (DBSC_A_BASE + 0x003CU) +#define DBSC_DBMEMCONF_1_0A (DBSC_A_BASE + 0x0040U) +#define DBSC_DBMEMCONF_1_1A (DBSC_A_BASE + 0x0044U) +#define DBSC_DBMEMCONF_1_2A (DBSC_A_BASE + 0x0048U) +#define DBSC_DBMEMCONF_1_3A (DBSC_A_BASE + 0x004CU) +#define DBSC_DBMEMCONF_2_0A (DBSC_A_BASE + 0x0050U) +#define DBSC_DBMEMCONF_2_1A (DBSC_A_BASE + 0x0054U) +#define DBSC_DBMEMCONF_2_2A (DBSC_A_BASE + 0x0058U) +#define DBSC_DBMEMCONF_2_3A (DBSC_A_BASE + 0x005CU) +#define DBSC_DBMEMCONF_3_0A (DBSC_A_BASE + 0x0060U) +#define DBSC_DBMEMCONF_3_1A (DBSC_A_BASE + 0x0064U) +#define DBSC_DBMEMCONF_3_2A (DBSC_A_BASE + 0x0068U) +#define DBSC_DBMEMCONF_3_3A (DBSC_A_BASE + 0x006CU) + +#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U) + +#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U) +#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U) +#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U) +#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U) + +#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + 0x04U * (x)) +#define DBSC_DBTR0 (DBSC_D_BASE + 0x0300U) +#define DBSC_DBTR1 (DBSC_D_BASE + 0x0304U) +#define DBSC_DBTR2 (DBSC_D_BASE + 0x0308U) +#define DBSC_DBTR3 (DBSC_D_BASE + 0x030CU) +#define DBSC_DBTR4 (DBSC_D_BASE + 0x0310U) +#define DBSC_DBTR5 (DBSC_D_BASE + 0x0314U) +#define DBSC_DBTR6 (DBSC_D_BASE + 0x0318U) +#define DBSC_DBTR7 (DBSC_D_BASE + 0x031CU) +#define DBSC_DBTR8 (DBSC_D_BASE + 0x0320U) +#define DBSC_DBTR9 (DBSC_D_BASE + 0x0324U) +#define DBSC_DBTR10 (DBSC_D_BASE + 0x0328U) +#define DBSC_DBTR11 (DBSC_D_BASE + 0x032CU) +#define DBSC_DBTR12 (DBSC_D_BASE + 0x0330U) +#define DBSC_DBTR13 (DBSC_D_BASE + 0x0334U) +#define DBSC_DBTR14 (DBSC_D_BASE + 0x0338U) +#define DBSC_DBTR15 (DBSC_D_BASE + 0x033CU) +#define DBSC_DBTR16 (DBSC_D_BASE + 0x0340U) +#define DBSC_DBTR17 (DBSC_D_BASE + 0x0344U) +#define DBSC_DBTR18 (DBSC_D_BASE + 0x0348U) +#define DBSC_DBTR19 (DBSC_D_BASE + 0x034CU) +#define DBSC_DBTR20 (DBSC_D_BASE + 0x0350U) +#define DBSC_DBTR21 (DBSC_D_BASE + 0x0354U) +#define DBSC_DBTR22 (DBSC_D_BASE + 0x0358U) +#define DBSC_DBTR23 (DBSC_D_BASE + 0x035CU) +#define DBSC_DBTR24 (DBSC_D_BASE + 0x0360U) +#define DBSC_DBTR25 (DBSC_D_BASE + 0x0364U) +#define DBSC_DBTR26 (DBSC_D_BASE + 0x0368U) +#define DBSC_DBTR27 (DBSC_D_BASE + 0x036CU) +#define DBSC_DBTR28 (DBSC_D_BASE + 0x0370U) +#define DBSC_DBTR29 (DBSC_D_BASE + 0x0374U) +#define DBSC_DBTR30 (DBSC_D_BASE + 0x0378U) +#define DBSC_DBTR31 (DBSC_D_BASE + 0x037CU) +#define DBSC_DBTR32 (DBSC_D_BASE + 0x0380U) +#define DBSC_DBTR33 (DBSC_D_BASE + 0x0384U) +#define DBSC_DBTR34 (DBSC_D_BASE + 0x0388U) +#define DBSC_DBTR35 (DBSC_D_BASE + 0x038CU) +#define DBSC_DBTR36 (DBSC_D_BASE + 0x0390U) +#define DBSC_DBTR37 (DBSC_D_BASE + 0x0394U) + +#define DBSC_DBBL (DBSC_D_BASE + 0x0400U) +#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U) + +#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U) +#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U) + +#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U) + +#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + 0x04U * (x)) +#define DBSC_DBRNK2 (DBSC_D_BASE + 0x0438U) +#define DBSC_DBRNK3 (DBSC_D_BASE + 0x043CU) +#define DBSC_DBRNK4 (DBSC_D_BASE + 0x0440U) +#define DBSC_DBRNK5 (DBSC_D_BASE + 0x0444U) + +#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U) +#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U) +#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U) + +#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBDFISTAT_0 (DBSC_D_BASE + 0x0600U) +#define DBSC_DBDFISTAT_1 (DBSC_D_BASE + 0x0640U) +#define DBSC_DBDFISTAT_2 (DBSC_D_BASE + 0x0680U) +#define DBSC_DBDFISTAT_3 (DBSC_D_BASE + 0x06C0U) + +#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBDFICNT_0 (DBSC_D_BASE + 0x0604U) +#define DBSC_DBDFICNT_1 (DBSC_D_BASE + 0x0644U) +#define DBSC_DBDFICNT_2 (DBSC_D_BASE + 0x0684U) +#define DBSC_DBDFICNT_3 (DBSC_D_BASE + 0x06C4U) + +#define DBSC_DBPDCNT0_0 (DBSC_D_BASE + 0x0610U) +#define DBSC_DBPDCNT0_1 (DBSC_D_BASE + 0x0614U) +#define DBSC_DBPDCNT0_2 (DBSC_D_BASE + 0x0618U) +#define DBSC_DBPDCNT0_3 (DBSC_D_BASE + 0x061CU) + +#define DBSC_DBPDCNT1_0 (DBSC_D_BASE + 0x0650U) +#define DBSC_DBPDCNT1_1 (DBSC_D_BASE + 0x0654U) +#define DBSC_DBPDCNT1_2 (DBSC_D_BASE + 0x0658U) +#define DBSC_DBPDCNT1_3 (DBSC_D_BASE + 0x065CU) + +#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDCNT2_0 (DBSC_D_BASE + 0x0690U) +#define DBSC_DBPDCNT2_1 (DBSC_D_BASE + 0x0694U) +#define DBSC_DBPDCNT2_2 (DBSC_D_BASE + 0x0698U) +#define DBSC_DBPDCNT2_3 (DBSC_D_BASE + 0x069CU) + +#define DBSC_DBPDCNT3_0 (DBSC_D_BASE + 0x06D0U) +#define DBSC_DBPDCNT3_1 (DBSC_D_BASE + 0x06D4U) +#define DBSC_DBPDCNT3_2 (DBSC_D_BASE + 0x06D8U) +#define DBSC_DBPDCNT3_3 (DBSC_D_BASE + 0x06DCU) + +#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDLK_0 (DBSC_D_BASE + 0x0620U) +#define DBSC_DBPDLK_1 (DBSC_D_BASE + 0x0660U) +#define DBSC_DBPDLK_2 (DBSC_D_BASE + 0x06a0U) +#define DBSC_DBPDLK_3 (DBSC_D_BASE + 0x06e0U) + +#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDRGA_0 (DBSC_D_BASE + 0x0624U) +#define DBSC_DBPDRGA_1 (DBSC_D_BASE + 0x0664U) +#define DBSC_DBPDRGA_2 (DBSC_D_BASE + 0x06A4U) +#define DBSC_DBPDRGA_3 (DBSC_D_BASE + 0x06E4U) + +#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDRGD_0 (DBSC_D_BASE + 0x0628U) +#define DBSC_DBPDRGD_1 (DBSC_D_BASE + 0x0668U) +#define DBSC_DBPDRGD_2 (DBSC_D_BASE + 0x06A8U) +#define DBSC_DBPDRGD_3 (DBSC_D_BASE + 0x06E8U) + +#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDSTAT0_0 (DBSC_D_BASE + 0x0630U) +#define DBSC_DBPDSTAT1_0 (DBSC_D_BASE + 0x0670U) + +#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + 0x2000U * (ch & 0x02U) + 0x40U * (ch & 0x01U)) +#define DBSC_DBPDSTAT0_1 (DBSC_D_BASE + 0x0634U) +#define DBSC_DBPDSTA1T_1 (DBSC_D_BASE + 0x0674U) + +#define DBSC_DBCAM0CTRL0 (DBSC_A_BASE + 0x0940U) + +#define DBSC_DBCAMSTAT0(x) (DBSC_A_BASE + 0x0980U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U)) +#define DBSC_DBCAM0STAT0 (DBSC_A_BASE + 0x0980U) +#define DBSC_DBCAM1STAT0 (DBSC_A_BASE + 0x0990U) +#define DBSC_DBCAM2STAT0 (DBSC_A_BASE + 0x09A0U) +#define DBSC_DBCAM3STAT0 (DBSC_A_BASE + 0x09B0U) + +#define DBSC_DBCAMSTAT1(x) (DBSC_A_BASE + 0x0984U + 0x4000U *(x & 0x02U) + 0x10U * (x & 0x01U)) +#define DBSC_DBCAM0STAT1 (DBSC_A_BASE + 0x0984U) +#define DBSC_DBCAM1STAT1 (DBSC_A_BASE + 0x0994U) +#define DBSC_DBCAM2STAT1 (DBSC_A_BASE + 0x09A4U) +#define DBSC_DBCAM3STAT1 (DBSC_A_BASE + 0x09B4U) + +#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU) + +#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U) + +#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U) + +#define DBSC_DBSCHFCTST01(x) (DBSC_A_BASE + 0x1040U + 0x04U * (x)) +#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U) +#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U) + +#define DBSC_DBSCHQOS(x,y) (DBSC_A_BASE + 0x1100U + 0x10U * (x) + 0x04U * (y)) diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c new file mode 100644 index 0000000..dcfb84b --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c @@ -0,0 +1,217 @@ +/******************************************************************************* + * Copyright (c) 2023-2024 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC setting function + ******************************************************************************/ +/****************************************************************************** + * @file ecc_enable_v4m.c + * - Version : 0.03 + * @brief Enable setting process of ECC for DRAM. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + * : 13.06.2024 0.02 Fix register setting for EDC_CFG, and revise + * : the ecm_lock()/ecm_unlock() process. + * : 07.04.2025 0.06 Remove unused functions. + *****************************************************************************/ + +#include +#include +#include +#include + +#if (ECM_ENABLE == 1) +#include "ecc_enable_v4m.h" +#include "v4m/lpddr5/boot_init_dram_regdef.h" +#include "ecm_enable_v4m.h" + +#define AXI_SICREMAP_NUM (5U) +#define RGID_BASE1 (0xFE600000U) +#define RGID_BASE2 (0xE7A00000U) +#define RGID_BASE3 (0xEB800000U) +#define RGID_BASE4 (0xFD800000U) +#define RGID_BASE5 (0xFEA00000U) + +#define FDT_COUNTER_MASK (0x0000FFFFU) + +static void axi_timeout_setting(void); + +void edc_axi_enable(void) +{ + uint32_t edc_tmp; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers + to inform the external device of the error via the ERROROUT# pin. */ + + /* Set bit 11 - bit 2 of ECMERRTGTR7 to all 0 and bit 11 - bit 2 of + ECMERRCTLR7 to 1. (Error of AXI-Bus ECM of each hierarchy) */ + edc_tmp = mem_read32(ECMERRTGTR7); + edc_tmp &= ~(0x3FFU << 2U); + ecm_write(ECMERRTGTR7, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR7); + edc_tmp |= (0x3FFU << 2U); + ecm_write(ECMERRCTLR7, edc_tmp); + + /* Set bit 28 - bit 16 of ECMERRTGTR39 to all 0 and bit 28 - bit 16 of + ECMERRCTLR39 to 1. (Error of AXI-Bus ECM of each hierarchy) */ + edc_tmp = mem_read32(ECMERRTGTR39); + edc_tmp &= ~(0x1FFFU << 16U); + ecm_write(ECMERRTGTR39, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR39); + edc_tmp |= (0x1FFFU << 16U); + ecm_write(ECMERRCTLR39, edc_tmp); + + /* Set bit 26 of ECMERRTGTR1 to 0 and bit 26 of + ECMERRCTLR1 to 1. (CCI bus EDC error) */ + edc_tmp = mem_read32(ECMERRTGTR1); + edc_tmp &= ~(0x1U << 26U); + ecm_write(ECMERRTGTR1, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR1); + edc_tmp |= (0x1U << 26U); + ecm_write(ECMERRCTLR1, edc_tmp); + + axi_timeout_setting(); + + /* Lock the ECM registers */ + ecm_lock(); +} + +void edc_vram_enable(void) +{ + uint32_t edc_tmp; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers + to inform the external device of the error via the ERROROUT# pin. */ + + /* Set bit 30 of ECMERRTGTR7 to 0 and bit 30 of ECMERRCTLR7 to 1. + (RT-VRAM edc 1-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR7); + edc_tmp &= ~(0x1U << 30U); + ecm_write(ECMERRTGTR7, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR7); + edc_tmp |= (0x1U << 30U); + ecm_write(ECMERRCTLR7, edc_tmp); + + /* Set bit 29 of ECMERRTGTR7 to 0 and bit 29 of ECMERRCTLR7 to 1. + (RT-VRAM edc multi-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR7); + edc_tmp &= ~(0x1U << 29U); + ecm_write(ECMERRTGTR7, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR7); + edc_tmp |= (0x1U << 29U); + ecm_write(ECMERRCTLR7, edc_tmp); + + /* Set bit 19 of ECMERRTGTR17 to 0 and bit 19 of ECMERRCTLR17 to 1. + (RT-VRAM edc 1-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR17); + edc_tmp &= ~(0x1U << 19U); + ecm_write(ECMERRTGTR17, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR17); + edc_tmp |= (0x1U << 19U); + ecm_write(ECMERRCTLR17, edc_tmp); + + /* Set bit 18 of ECMERRTGTR17 to 0 and bit 18 of ECMERRCTLR17 to 1. + (RT-VRAM edc multi-bit error) */ + edc_tmp = mem_read32(ECMERRTGTR17); + edc_tmp &= ~(0x1U << 18U); + ecm_write(ECMERRTGTR17, edc_tmp); + + edc_tmp = mem_read32(ECMERRCTLR17); + edc_tmp |= (0x1U << 18U); + ecm_write(ECMERRCTLR17, edc_tmp); + + /* Set bit 0 of EDC_CFG to 1. (EDC Error Control) */ + edc_tmp = mem_read32(EDC_CFG); + edc_tmp |= (0x1U << 0U); + mem_write32(EDC_CFG, edc_tmp); + + /* Lock the ECM registers */ + ecm_lock(); +} + +static void axi_timeout_setting(void) +{ + uint32_t reg; + uint32_t loop; + REMAP_TABLE axi_remap_tbl[AXI_SICREMAP_NUM] = { + {RGID_BASE1, 0U}, + {RGID_BASE2, 0U}, + {RGID_BASE3, 0U}, + {RGID_BASE4, 0U}, + {RGID_BASE5, 0U}, + }; + + /* Register of AXI Base */ + for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++) + { + remap_register(axi_remap_tbl[loop].base_addr, &axi_remap_tbl[loop].rmp_addr); + } + + /* Set the COUNTER bits of the FDT_* registers for all safety-related modules to minimum value with 1ms or more. */ + for (loop = 0U; loop < FDT_REG_MAX; loop++) + { + reg = mem_read32(g_fdt_tbl[loop].reg_addr); + reg &= ~(FDT_COUNTER_MASK); + reg |= g_fdt_tbl[loop].value; + mem_write32(g_fdt_tbl[loop].reg_addr, reg); + + INFO("FDT[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_fdt_tbl[loop].reg_addr), g_fdt_tbl[loop].value); + } + + for(loop = 0U; loop < INTEN_REG_MAX; loop++) + { + /* Set access protection setting value of Region ID (AXI bus of Region ID register) */ + mem_write32(g_inten_tbl[loop].reg_addr, g_inten_tbl[loop].value); + + INFO("INTEN[%d] =\t0x%08x \tsetting value = 0x%08x\n", loop, mem_read32(g_inten_tbl[loop].reg_addr), g_inten_tbl[loop].value); + } + + /* Unregister of AXI Base */ + for (loop = 0U; loop < AXI_SICREMAP_NUM; loop++) + { + remap_unregister(axi_remap_tbl[loop].rmp_addr); + } + + wdt_restart(); +} +#endif /* ECM_ENABLE == 1 */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h new file mode 100644 index 0000000..8a04f4b --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h @@ -0,0 +1,123 @@ +/******************************************************************************* + * Copyright (c) 2022-2024 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC driver header + ******************************************************************************/ + +#ifndef ECC_PROTECT +#define ECC_PROTECT +#include "remap_register.h" +/* DBSC registers */ +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#define ECM_BASE (BASE_ECC_ADDR) +#else +#include +#include +#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#define ECM_BASE (0xE6250000U) +#endif/* defined(__RH850G3K__) */ + +#define RTVRAM_REG_BASE (0xFFEC0000U) + +void edc_axi_enable(void); +void edc_vram_enable(void); + +#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U) +#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U) +#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U) + +#define DBSC_DBACEN0 (DBSC_A_BASE + 0x0200U) +#define DBSC_DBACEN1 (DBSC_DBACEN0 + 0x8000U) + +#define ECMWACNTR (ECM_BASE + 0x0A04U) +#define ECMWPCNTR (ECM_BASE + 0x0A00U) +#define ECMERRTGTR0 (ECM_BASE + 0x0200U) +#define ECMERRCTLR0 (ECM_BASE + 0x0000U) +#define ECMERRTGTR1 (ECM_BASE + 0x0200U + 0x4U * 1U) +#define ECMERRCTLR1 (ECM_BASE + 0x0000U + 0x4U * 1U) +#define ECMERRTGTR7 (ECM_BASE + 0x0200U + 0x4U * 7U) +#define ECMERRCTLR7 (ECM_BASE + 0x0000U + 0x4U * 7U) +#define ECMERRTGTR17 (ECM_BASE + 0x0200U + 0x4U * 17U) +#define ECMERRCTLR17 (ECM_BASE + 0x0000U + 0x4U * 17U) +#define ECMERRTGTR39 (ECM_BASE + 0x0200U + 0x4U * 39U) +#define ECMERRCTLR39 (ECM_BASE + 0x0000U + 0x4U * 39U) +#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U) +#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U) +#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U) +#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U) +#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U) +#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U) +#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U) +#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U) +#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U) +#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U) +#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U) +#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U) +#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U) +#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U) +#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U) +#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U) + +#define DB0FSDRAMECCAREA0 (DBSC_A_BASE + 0x7450U) +#define DB0FSDRAMECCAREA1 (DBSC_A_BASE + 0x7454U) +#define DB1FSDRAMECCAREA0 (DB0FSDRAMECCAREA0 + 0x8000U) +#define DB1FSDRAMECCAREA1 (DB0FSDRAMECCAREA1 + 0x8000U) + +#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U) +#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U) + +#define EDC_CFG (RTVRAM_REG_BASE + 0x4110U) + +/********************* Set by the user *********************/ +/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */ +#define ECC_PROT_SIZE00 (0x1000U) +#define ECC_PROT_SIZE01 (0x1000U) +#define ECC_PROT_SIZE10 (0x1000U) +#define ECC_PROT_SIZE11 (0x1000U) + +/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */ +#define START_ECC_INIT_AREA00 (0x00000000U) +#define START_ECC_INIT_AREA10 (0x00000000U) +#define END_ECC_INIT_AREA00 (0x00000FFFU) +#define END_ECC_INIT_AREA10 (0x00000FFFU) + +/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */ +#define START_ECC_INIT_AREA01 (0x00000000U) +#define START_ECC_INIT_AREA11 (0x00000000U) +#define END_ECC_INIT_AREA01 (0x00000FFFU) +#define END_ECC_INIT_AREA11 (0x00000FFFU) +/*********** Other settings cannot be changed ***************/ + +#endif/* ECC_PROTECT */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c new file mode 100644 index 0000000..4c615e4 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c @@ -0,0 +1,534 @@ +/******************************************************************************* + * Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM initialize function + ******************************************************************************/ +/****************************************************************************** + * @file ecm_enable_v4m.c + * - Version : 0.01 + * @brief ECM setting. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.01.2025 0.01 First Release + *****************************************************************************/ + +#include +#include "ecm_enable_v4m.h" + +#if (ECM_ERROR_ENABLE == 1) +#include "log.h" +#endif /* ECM_ERROR_ENABLE == 1 */ +#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1)) +#include "ecc_enable_v4m.h" +#include "mem_io.h" +#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +#define TYPE1_ECM_REG_MAX (14U) +#define TYPE2_ECM_REG_MAX (21U) +#define TYPE3_ECM_CTLREG_MAX (1U) +#define TYPE3_ECM_TGTREG_MAX (2U) + +typedef struct{ + uint32_t phys_addr; /* Physical address of ECM registers. */ + uint32_t value; /* Setting value of ECM registers. */ +} ECM_ERROR_TABLE; +#endif /* ECM_ERROR_ENABLE == 1 */ + +#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1)) +void ecm_unlock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0001U); +} + +void ecm_write(uint32_t adr, uint32_t val) +{ + mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU))); + mem_write32(adr, val); +} + +void ecm_lock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0000U); +} +#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_init_setting(void) +{ + uint32_t reg; + uint32_t loop; + + const ECM_ERROR_TABLE ecmerrctlr_type1_tbl[TYPE1_ECM_REG_MAX] = { + [0] = {0xFD850000U, 0x00381000U}, /* ECMERRCTLR0 */ + [1] = {0xFD850004U, 0xA400C000U}, /* ECMERRCTLR1 */ + /* Skip ECMERRCTLR2 setting */ + /* Skip ECMERRCTLR3 setting */ + /* Skip ECMERRCTLR4 setting */ + /* Skip ECMERRCTLR5 setting */ + [2] = {0xFD850018U, 0xCC000000U}, /* ECMERRCTLR6 */ + [3] = {0xFD85001CU, 0x08000000U}, /* ECMERRCTLR7 */ + /* Skip ECMERRCTLR8 setting */ + /* Skip ECMERRCTLR9 setting */ + /* Skip ECMERRCTLR10 setting */ + /* Skip ECMERRCTLR11 setting */ + /* Skip ECMERRCTLR12 setting */ + /* Skip ECMERRCTLR13 setting */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + /* Skip ECMERRCTLR16 setting */ + [4] = {0xFD850044U, 0x2D001000U}, /* ECMERRCTLR17 */ + [5] = {0xFD850048U, 0x0CC001FFU}, /* ECMERRCTLR18 */ + [6] = {0xFD85004CU, 0xFFF80000U}, /* ECMERRCTLR19 */ + [7] = {0xFD850050U, 0x0000001EU}, /* ECMERRCTLR20 */ + [8] = {0xFD850054U, 0x9F000000U}, /* ECMERRCTLR21 */ + /* Skip ECMERRCTLR22 setting */ + /* Skip ECMERRCTLR23 setting */ + /* Skip ECMERRCTLR24 setting */ + /* Skip ECMERRCTLR25 setting */ + /* Skip ECMERRCTLR26 setting */ + /* Skip ECMERRCTLR27 setting */ + /* Skip ECMERRCTLR28 setting */ + /* Skip ECMERRCTLR29 setting */ + /* Skip ECMERRCTLR30 setting */ + /* Skip ECMERRCTLR31 setting */ + [9] = {0xFD850080U, 0x10000000U}, /* ECMERRCTLR32 */ + [10] = {0xFD850084U, 0x10000000U}, /* ECMERRCTLR33 */ + /* Skip ECMERRCTLR34 setting */ + [11] = {0xFD85008CU, 0x20002280U}, /* ECMERRCTLR35 */ + /* Skip ECMERRCTLR36 setting */ + /* Skip ECMERRCTLR37 setting */ + [12] = {0xFD850098U, 0x33300054U}, /* ECMERRCTLR38 */ + /* Skip ECMERRCTLR39 setting */ + /* Skip ECMERRCTLR40 setting */ + [13] = {0xFD8500A4U, 0x01000880U}, /* ECMERRCTLR41 */ + /* Skip ECMERRCTLR42 setting */ + }; + + const ECM_ERROR_TABLE ecmerrtgtr_type1_tbl[TYPE1_ECM_REG_MAX] = { + [0] = {0xFD850200U, 0x00381000U}, /* ECMERRTGTR0 */ + [1] = {0xFD850204U, 0xA400C000U}, /* ECMERRTGTR1 */ + /* Skip ECMERRTGTR2 setting */ + /* Skip ECMERRTGTR3 setting */ + /* Skip ECMERRTGTR4 setting */ + /* Skip ECMERRTGTR5 setting */ + [2] = {0xFD850218U, 0xCC000000U}, /* ECMERRTGTR6 */ + [3] = {0xFD85021CU, 0x08000000U}, /* ECMERRTGTR7 */ + /* Skip ECMERRTGTR8 setting */ + /* Skip ECMERRTGTR9 setting */ + /* Skip ECMERRTGTR10 setting */ + /* Skip ECMERRTGTR11 setting */ + /* Skip ECMERRTGTR12 setting */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + /* Skip ECMERRTGTR16 setting */ + [4] = {0xFD850244U, 0x2D001000U}, /* ECMERRTGTR17 */ + [5] = {0xFD850248U, 0x0CC001FFU}, /* ECMERRTGTR18 */ + [6] = {0xFD85024CU, 0xFFF80000U}, /* ECMERRTGTR19 */ + [7] = {0xFD850250U, 0x0000001EU}, /* ECMERRTGTR20 */ + [8] = {0xFD850254U, 0x9F000000U}, /* ECMERRTGTR21 */ + /* Skip ECMERRTGTR22 setting */ + /* Skip ECMERRTGTR23 setting */ + /* Skip ECMERRTGTR24 setting */ + /* Skip ECMERRTGTR25 setting */ + /* Skip ECMERRTGTR26 setting */ + /* Skip ECMERRTGTR27 setting */ + /* Skip ECMERRTGTR28 setting */ + /* Skip ECMERRTGTR29 setting */ + /* Skip ECMERRTGTR30 setting */ + /* Skip ECMERRTGTR31 setting */ + [9] = {0xFD850280U, 0x10000000U}, /* ECMERRTGTR32 */ + [10] = {0xFD850284U, 0x10000000U}, /* ECMERRTGTR33 */ + /* Skip ECMERRTGTR34 setting */ + [11] = {0xFD85028CU, 0x20002280U}, /* ECMERRTGTR35 */ + /* Skip ECMERRTGTR36 setting */ + /* Skip ECMERRTGTR37 setting */ + [12] = {0xFD850298U, 0x33300054U}, /* ECMERRTGTR38 */ + /* Skip ECMERRTGTR39 setting */ + /* Skip ECMERRTGTR40 setting */ + [13] = {0xFD8502A4U, 0x01000880U}, /* ECMERRTGTR41 */ + /* Skip ECMERRTGTR42 setting */ + }; + + const ECM_ERROR_TABLE ecmerrctlr_type2_tbl[TYPE2_ECM_REG_MAX] = { + [0] = {0xFD850000U, 0x40000003U}, /* ECMERRCTLR0 */ + [1] = {0xFD850004U, 0x04004000U}, /* ECMERRCTLR1 */ + [2] = {0xFD850008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */ + [3] = {0xFD85000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */ + [4] = {0xFD850010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */ + [5] = {0xFD850014U, 0x81FFFFFFU}, /* ECMERRCTLR5 */ + [6] = {0xFD850018U, 0x15000A80U}, /* ECMERRCTLR6 */ + [7] = {0xFD85001CU, 0x00801481U}, /* ECMERRCTLR7 */ + /* Skip ECMERRCTLR8 setting */ + /* Skip ECMERRCTLR9 setting */ + /* Skip ECMERRCTLR10 setting */ + /* Skip ECMERRCTLR11 setting */ + /* Skip ECMERRCTLR12 setting */ + /* Skip ECMERRCTLR13 setting */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + [8] = {0xFD850040U, 0x00003E9FU}, /* ECMERRCTLR16 */ + [9] = {0xFD850044U, 0x00938060U}, /* ECMERRCTLR17 */ + [10] = {0xFD850048U, 0x00341600U}, /* ECMERRCTLR18 */ + [11] = {0xFD85004CU, 0x0007FF30U}, /* ECMERRCTLR19 */ + [12] = {0xFD850050U, 0x02200220U}, /* ECMERRCTLR20 */ + [13] = {0xFD850054U, 0x0061820FU}, /* ECMERRCTLR21 */ + /* Skip ECMERRCTLR22 setting */ + /* Skip ECMERRCTLR23 setting */ + /* Skip ECMERRCTLR24 setting */ + /* Skip ECMERRCTLR25 setting */ + /* Skip ECMERRCTLR26 setting */ + /* Skip ECMERRCTLR27 setting */ + /* Skip ECMERRCTLR28 setting */ + /* Skip ECMERRCTLR29 setting */ + /* Skip ECMERRCTLR30 setting */ + /* Skip ECMERRCTLR31 setting */ + [14] = {0xFD850080U, 0x03E9043BU}, /* ECMERRCTLR32 */ + [15] = {0xFD850084U, 0x03E9043BU}, /* ECMERRCTLR33 */ + /* Skip ECMERRCTLR34 setting */ + [16] = {0xFD85008CU, 0x83B00800U}, /* ECMERRCTLR35 */ + [17] = {0xFD850090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */ + /* Skip ECMERRCTLR37 setting */ + [18] = {0xFD850098U, 0x00000002U}, /* ECMERRCTLR38 */ + /* Skip ECMERRCTLR39 setting */ + [19] = {0xFD8500A0U, 0x0000601EU}, /* ECMERRCTLR40 */ + [20] = {0xFD8500A4U, 0x20010000U}, /* ECMERRCTLR41 */ + /* Skip ECMERRCTLR42 setting */ + }; + + const ECM_ERROR_TABLE ecmerrtgtr_type2_tbl[TYPE2_ECM_REG_MAX] = { + [0] = {0xFD850200U, 0x40000003U}, /* ECMERRTGTR0 */ + [1] = {0xFD850204U, 0x04004000U}, /* ECMERRTGTR1 */ + [2] = {0xFD850208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */ + [3] = {0xFD85020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */ + [4] = {0xFD850210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */ + [5] = {0xFD850214U, 0x81FFFFFFU}, /* ECMERRTGTR5 */ + [6] = {0xFD850218U, 0x15000A80U}, /* ECMERRTGTR6 */ + [7] = {0xFD85021CU, 0x00801481U}, /* ECMERRTGTR7 */ + /* Skip ECMERRTGTR8 setting */ + /* Skip ECMERRTGTR9 setting */ + /* Skip ECMERRTGTR10 setting */ + /* Skip ECMERRTGTR11 setting */ + /* Skip ECMERRTGTR12 setting */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [8] = {0xFD850240U, 0x00003E9FU}, /* ECMERRTGTR16 */ + [9] = {0xFD850244U, 0x00938060U}, /* ECMERRTGTR17 */ + [10] = {0xFD850248U, 0x00341600U}, /* ECMERRTGTR18 */ + [11] = {0xFD85024CU, 0x0007FF30U}, /* ECMERRTGTR19 */ + [12] = {0xFD850250U, 0x02200220U}, /* ECMERRTGTR20 */ + [13] = {0xFD850254U, 0x0061820FU}, /* ECMERRTGTR21 */ + /* Skip ECMERRTGTR22 setting */ + /* Skip ECMERRTGTR23 setting */ + /* Skip ECMERRTGTR24 setting */ + /* Skip ECMERRTGTR25 setting */ + /* Skip ECMERRTGTR26 setting */ + /* Skip ECMERRTGTR27 setting */ + /* Skip ECMERRTGTR28 setting */ + /* Skip ECMERRTGTR29 setting */ + /* Skip ECMERRTGTR30 setting */ + /* Skip ECMERRTGTR31 setting */ + [14] = {0xFD850280U, 0x03E9043BU}, /* ECMERRTGTR32 */ + [15] = {0xFD850284U, 0x03E9043BU}, /* ECMERRTGTR33 */ + /* Skip ECMERRTGTR34 setting */ + [16] = {0xFD85028CU, 0x83B00800U}, /* ECMERRTGTR35 */ + [17] = {0xFD850290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */ + /* Skip ECMERRTGTR37 setting */ + [18] = {0xFD850298U, 0x00000002U}, /* ECMERRTGTR38 */ + /* Skip ECMERRTGTR39 setting */ + [19] = {0xFD8502A0U, 0x0000601EU}, /* ECMERRTGTR40 */ + [20] = {0xFD8502A4U, 0x20010000U}, /* ECMERRTGTR41 */ + /* Skip ECMERRTGTR42 setting */ + }; + + const ECM_ERROR_TABLE ecmerrctlr_type3_tbl[TYPE3_ECM_CTLREG_MAX] = { + /* Skip ECMERRCTLR0 setting */ + /* Skip ECMERRCTLR1 setting */ + /* Skip ECMERRCTLR2 setting */ + /* Skip ECMERRCTLR3 setting */ + /* Skip ECMERRCTLR4 setting */ + /* Skip ECMERRCTLR5 setting */ + /* Skip ECMERRCTLR6 setting */ + /* Skip ECMERRCTLR7 setting */ + /* Skip ECMERRCTLR8 setting */ + /* Skip ECMERRCTLR9 setting */ + /* Skip ECMERRCTLR10 setting */ + /* Skip ECMERRCTLR11 setting */ + /* Skip ECMERRCTLR12 setting */ + /* Skip ECMERRCTLR13 setting */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + [0] = {0xFD850040U, 0x33F00000U}, /* ECMERRCTLR16 */ + /* Skip ECMERRCTLR17 setting */ + /* Skip ECMERRCTLR18 setting */ + /* Skip ECMERRCTLR19 setting */ + /* Skip ECMERRCTLR20 setting */ + /* Skip ECMERRCTLR21 setting */ + /* Skip ECMERRCTLR22 setting */ + /* Skip ECMERRCTLR23 setting */ + /* Skip ECMERRCTLR24 setting */ + /* Skip ECMERRCTLR25 setting */ + /* Skip ECMERRCTLR26 setting */ + /* Skip ECMERRCTLR27 setting */ + /* Skip ECMERRCTLR28 setting */ + /* Skip ECMERRCTLR29 setting */ + /* Skip ECMERRCTLR30 setting */ + /* Skip ECMERRCTLR31 setting */ + /* Skip ECMERRCTLR32 setting */ + /* Skip ECMERRCTLR33 setting */ + /* Skip ECMERRCTLR34 setting */ + /* Skip ECMERRCTLR35 setting */ + /* Skip ECMERRCTLR36 setting */ + /* Skip ECMERRCTLR37 setting */ + /* Skip ECMERRCTLR38 setting */ + /* Skip ECMERRCTLR39 setting */ + /* Skip ECMERRCTLR40 setting */ + /* Skip ECMERRCTLR41 setting */ + /* Skip ECMERRCTLR42 setting */ + }; + + const ECM_ERROR_TABLE ecmerrtgtr_type3_tbl[TYPE3_ECM_TGTREG_MAX] = { + [0] = {0xFD850200U, 0x80000000U}, /* ECMERRTGTR0 */ + /* Skip ECMERRTGTR1 setting */ + /* Skip ECMERRTGTR2 setting */ + /* Skip ECMERRTGTR3 setting */ + /* Skip ECMERRTGTR4 setting */ + /* Skip ECMERRTGTR5 setting */ + /* Skip ECMERRTGTR6 setting */ + /* Skip ECMERRTGTR7 setting */ + /* Skip ECMERRTGTR8 setting */ + /* Skip ECMERRTGTR9 setting */ + /* Skip ECMERRTGTR10 setting */ + /* Skip ECMERRTGTR11 setting */ + /* Skip ECMERRTGTR12 setting */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [1] = {0xFD850240U, 0x33F00000U}, /* ECMERRTGTR16 */ + /* Skip ECMERRTGTR17 setting */ + /* Skip ECMERRTGTR18 setting */ + /* Skip ECMERRTGTR19 setting */ + /* Skip ECMERRTGTR20 setting */ + /* Skip ECMERRTGTR21 setting */ + /* Skip ECMERRTGTR22 setting */ + /* Skip ECMERRTGTR23 setting */ + /* Skip ECMERRTGTR24 setting */ + /* Skip ECMERRTGTR25 setting */ + /* Skip ECMERRTGTR26 setting */ + /* Skip ECMERRTGTR27 setting */ + /* Skip ECMERRTGTR28 setting */ + /* Skip ECMERRTGTR29 setting */ + /* Skip ECMERRTGTR30 setting */ + /* Skip ECMERRTGTR31 setting */ + /* Skip ECMERRTGTR32 setting */ + /* Skip ECMERRTGTR33 setting */ + /* Skip ECMERRTGTR34 setting */ + /* Skip ECMERRTGTR35 setting */ + /* Skip ECMERRTGTR36 setting */ + /* Skip ECMERRTGTR37 setting */ + /* Skip ECMERRTGTR38 setting */ + /* Skip ECMERRTGTR39 setting */ + /* Skip ECMERRTGTR40 setting */ + /* Skip ECMERRTGTR41 setting */ + /* Skip ECMERRTGTR42 setting */ + }; + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + NOTICE("ECMERRCTLR and ECMERRTGTR register initial setting.\n"); + /* For the initial setting flow for Type-1, please refer to the following + * section in the "SAN(Safety Application Note)." + * Section 4.1.2.5 : (1) + * Section 4.1.4.5 : (1) + * Section 4.12.1.5 : (1) + * Section 4.14.5 : (1) + * Section 4.2.7.5 : (1) + * Section 4.2.9.5 : (1) + * Section 4.23.5 : (1) + * Section 4.25.5 : (1) + * Section 4.3.14.5 : (1) + * Section 4.3.19.5 : (1) + * Section 4.3.21.5 : (1) + * Section 4.4.16.5 : (1) + * Section 4.4.18.5 : (1) + * Section 4.4.20.5 : (1) + * Section 4.4.3.5 : (1) + * Section 4.4.4.5 : (1) + * Section 4.4.6.5 : (1) + * Section 4.4.7.5 : (1) + * Section 4.4.9.5 : (1) + * Section 4.5.1.5 : (1) + * Section 4.7.1.5 : (1) + * Section 4.7.10.5 : (1) + * Section 4.7.3.5 : (1) + * Section 4.7.4.5 : (1) + * Section 4.7.7.5 : (1) + * Section 4.7.8.5 : (1) + * Section 5.8.1.5 : (1) + */ + for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++) + { + /* Initial Setting Type-1 for ECMERRCTLR registers */ + reg = mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr); + reg |= (ecmerrctlr_type1_tbl[loop].value); + ecm_write(ecmerrctlr_type1_tbl[loop].phys_addr, reg); + + INFO("[Type-1]ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrctlr_type1_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_type1_tbl[loop].phys_addr), + ecmerrctlr_type1_tbl[loop].value); + } + + for (loop = 0U; loop < TYPE1_ECM_REG_MAX; loop++) + { + /* Initial Setting Type-1 for ECMERRTGTR registers */ + reg = mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr); + reg &= ~(ecmerrtgtr_type1_tbl[loop].value); + ecm_write(ecmerrtgtr_type1_tbl[loop].phys_addr, reg); + + INFO("[Type-1]ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrtgtr_type1_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_type1_tbl[loop].phys_addr), + ecmerrtgtr_type1_tbl[loop].value); + } + + /* For the initial setting flow for Type-2, please refer to the following + * section in the "SAN(Safety Application Note)." + * Section 4.1.1.5 : (1) + * Section 4.12.2.5 : (1) + * Section 4.12.3.5 : (1) + * Section 4.15.5 : (1) + * Section 4.16.5 : (1) + * Section 4.18.5 : (1) + * Section 4.2.1.5 : (1) + * Section 4.2.10.5 : (1) + * Section 4.2.12.5 : (1) + * Section 4.2.2.5 : (1) + * Section 4.2.4.5 : (1) + * Section 4.2.8.5 : (1) + * Section 4.3.1.5 : (1) + * Section 4.3.10.5 : (1) + * Section 4.3.11.5 : (1) + * Section 4.3.12.5 : (1) + * Section 4.3.13.5 : (1) + * Section 4.3.15.5 : (1) + * Section 4.3.16.5 : (1) + * Section 4.3.2.5 : (1) + * Section 4.3.5.5 : (1) + * Section 4.3.7.5 : (1) + * Section 4.3.8.5 : (1) + * Section 4.4.10.5 : (1) + * Section 4.4.12.5 : (6) + * Section 4.4.13.5 : (1) + * Section 4.4.14.5 : (1) + * Section 4.4.15.5 : (1) + * Section 4.4.2.5 : (1) + * Section 4.5.3.5 : (1) + * Section 4.6.5 : (1) + * Section 4.7.2.5 : (1) + * Section 5.11.5 : (1) + * Section 5.12.5 : (1) + * Section 5.13.5 : (1) + * Section 5.4.5 : (1) + * Section 5.6.5 : (1) + * Section 5.8.2.5 : (1) + */ + for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++) + { + /* Initial Setting Type-2 for ECMERRCTLR registers */ + reg = mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr); + reg |= (ecmerrctlr_type2_tbl[loop].value); + ecm_write(ecmerrctlr_type2_tbl[loop].phys_addr, reg); + + INFO("[Type-2]ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrctlr_type2_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_type2_tbl[loop].phys_addr), + ecmerrctlr_type2_tbl[loop].value); + } + + for (loop = 0U; loop < TYPE2_ECM_REG_MAX; loop++) + { + /* Initial Setting Type-2 for ECMERRTGTR registers */ + reg = mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr); + reg &= ~(ecmerrtgtr_type2_tbl[loop].value); + ecm_write(ecmerrtgtr_type2_tbl[loop].phys_addr, reg); + + INFO("[Type-2]ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrtgtr_type2_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_type2_tbl[loop].phys_addr), + ecmerrtgtr_type2_tbl[loop].value); + } + + /* For the initial setting flow for Type-3, please refer to the following + * section in the "SAN(Safety Application Note)." + * Section 4.19.1.5 : (3) + * Section 6.2.5 : (12) + */ + for (loop = 0U; loop < TYPE3_ECM_CTLREG_MAX; loop++) + { + /* Initial Setting Type-3 for ECMERRCTLR registers */ + reg = mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr); + reg |= (ecmerrctlr_type3_tbl[loop].value); + ecm_write(ecmerrctlr_type3_tbl[loop].phys_addr, reg); + + INFO("[Type-3]ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrctlr_type3_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_type3_tbl[loop].phys_addr), + ecmerrctlr_type3_tbl[loop].value); + } + + for (loop = 0U; loop < TYPE3_ECM_TGTREG_MAX; loop++) + { + /* Initial Setting Type-3 for ECMERRTGTR registers */ + reg = mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr); + reg &= ~(ecmerrtgtr_type3_tbl[loop].value); + ecm_write(ecmerrtgtr_type3_tbl[loop].phys_addr, reg); + + INFO("[Type-3]ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrtgtr_type3_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_type3_tbl[loop].phys_addr), + ecmerrtgtr_type3_tbl[loop].value); + } + + /* Lock the ECM registers */ + ecm_lock(); +} +/* End of function ecm_init_setting(void) */ +#endif /* ECM_ERROR_ENABLE == 1 */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h new file mode 100644 index 0000000..2c2f80b --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h @@ -0,0 +1,47 @@ +/******************************************************************************* + * Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM driver header + ******************************************************************************/ + +#ifndef ECM_ENABLE_V4M +#define ECM_ENABLE_V4M + +#if ((ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1)) +void ecm_unlock(void); +void ecm_write(uint32_t adr, uint32_t val); +void ecm_lock(void); +#endif /* (ECM_ERROR_ENABLE == 1) || (ECM_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_init_setting(void); +#endif /* ECM_ERROR_ENABLE == 1 */ + +#endif/* ECM_ENABLE_V4M */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/dma/dma.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/dma/dma.c new file mode 100644 index 0000000..a9d6e77 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/dma/dma.c @@ -0,0 +1,182 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : DMA driver + ******************************************************************************/ +/****************************************************************************** + * @file dma.c + * - Version : 0.07 + * @brief DMA driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 30.09.2021 0.02 Change function name load_start and + * load_end function. + * : 15.10.2021 0.03 modified to not use CHCLR. + * : 06.01.2022 0.04 Add exception handling for ICUMX_WDTA. + * : 02.02.2022 0.05 Add MFIS Lock/Unlock. + * : 22.06.2022 0.06 Replace address align check to function. + * : Remove some defines. + * : 20.12.2022 0.07 Add mask when writing to TCR register. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +#define DMOR_INIT (uint16_t)(0x0301U) +#define DMOR_HW_INIT (uint16_t)(0x0000U) +#define TCR_CNT_SHIFT (6U) +#define TCR_UPPER8BIT_MASK (0x00FFFFFFU) +#define CHCR_TRN_MODE (0x00105409U) +#define CHCR_TE_BIT (0x00000002U) +#define TE_FLAG (0x00000000U) +#define CHCR_CAE_BIT (0x80000000U) +#define CHCR_CAE_BIT_NOERROR (0x00000000U) +#define CHCR_CAIE_BIT (0x40000000U) +#define CHCR_DPM_BIT (0x30000000U) +#define CHCR_RPT_BIT (0x0F000000U) +#define CHCR_WAIT_BIT (0x00800000U) +#define CHCR_DPB_BIT (0x00400000U) +#define CHCR_DSE_BIT (0x00080000U) +#define CHCR_DSIE_BIT (0x00040000U) +#define CHCR_DM_BIT (0x0000C000U) +#define CHCR_SM_BIT (0x00003000U) +#define CHCR_RS_BIT (0x00000F00U) +#define CHCR_TS_BIT (0x00300018U) +#define CHCR_IE_BIT (0x00000004U) +#define CHCR_TE_BIT (0x00000002U) +#define CHCR_DE_BIT (0x00000001U) +#define CHCR_CONF_MASK (CHCR_TS_BIT | CHCR_DM_BIT | CHCR_SM_BIT | CHCR_RS_BIT | CHCR_DE_BIT) +#define CHCR_DESCRIPTOR_CONF_MASK (CHCR_DPM_BIT | CHCR_RPT_BIT | CHCR_WAIT_BIT | CHCR_DPB_BIT) +#define CHCR_INTERRUPT_MASK (CHCR_CAIE_BIT | CHCR_DSIE_BIT | CHCR_IE_BIT) +#define CHCR_FLAG_MASK (CHCR_CAE_BIT | CHCR_DSE_BIT | CHCR_TE_BIT) +#define CHCR_ALL_BIT_MASK (CHCR_CONF_MASK | CHCR_DESCRIPTOR_CONF_MASK | CHCR_INTERRUPT_MASK | CHCR_FLAG_MASK) +#define DAR_HW_INIT (0x00000000U) +#define SAR_HW_INIT (0x00000000U) +#define TCR_HW_INIT (0x00000000U) + +/* fraction mask for 256-byte units */ +#define FRACTION_MASK_256_BYTE (0x000000FFU) + +void dma_init(void) +{ + uint32_t reg; + + /* DMA operation */ + mem_write16(RTDMA_DMOR, DMOR_INIT); + /* DMA secure control register */ + reg = mem_read32(RTDMA_DMSEC); + reg |= ((uint32_t)1U << DMACH); + mem_write32(RTDMA_DMSEC, reg); + + reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH)); + reg &= ~(CHCR_ALL_BIT_MASK); + mem_write32(dma_get_rtdma_chcr_addr(DMACH), reg); +} +/* End of function dma_init(void) */ + +void dma_trans_start(uint32_t dst, uint32_t src, uint32_t len) +{ + uint32_t reg; + + /* dst and src must be 64-byte boundary. */ + dma_address_align_check(dst, src); + + /* round up 256 byte alignment */ + len += FRACTION_MASK_256_BYTE; + len &= (~(uint32_t)(FRACTION_MASK_256_BYTE)); + + /* DMA destination address */ + mem_write32(dma_get_rtdma_dar_addr(DMACH), dst); + /* DMA source address */ + mem_write32(dma_get_rtdma_sar_addr(DMACH), src); + /* DMA 64bytes-unit transfer count */ + mem_write32(dma_get_rtdma_tcr_addr(DMACH), ((len >> TCR_CNT_SHIFT) & TCR_UPPER8BIT_MASK)); + /* Lock to avoid conflict with RPC */ + mfis_lock(); + /* DMA channel control */ + reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH)); + reg |= CHCR_TRN_MODE; + mem_write32(dma_get_rtdma_chcr_addr(DMACH), reg); +} +/* End of function dma_trans_start(uint32_t dst, uint32_t src, uint32_t len) */ + +void dma_trans_end_check(void) +{ + uint32_t reg; + + /* Check end of DMA transfer. */ + do + { + wdt_restart(); + reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH)); + /* Check error of DMA transfer */ + if ((reg & CHCR_CAE_BIT) != CHCR_CAE_BIT_NOERROR) + { + ERROR("DMA - Channel Address Error\n"); + panic; + } + } while ((reg & CHCR_TE_BIT) == TE_FLAG); + + reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH)); + reg &= ~(CHCR_ALL_BIT_MASK); + mem_write32(dma_get_rtdma_chcr_addr(DMACH), reg); + + rpc_end_state_check(); + /* Unlock to avoid conflict with RPC */ + mfis_unlock(); +} +/* End of function dma_trans_end_check(void) */ + +void dma_release(void) +{ + uint32_t reg; + + /* DMA channel control */ + reg = mem_read32(dma_get_rtdma_chcr_addr(DMACH)); + reg &= ~(CHCR_ALL_BIT_MASK); + mem_write32(dma_get_rtdma_chcr_addr(DMACH), reg); + + /* DMA destination address */ + mem_write32(dma_get_rtdma_dar_addr(DMACH), DAR_HW_INIT); + /* DMA source address */ + mem_write32(dma_get_rtdma_sar_addr(DMACH), SAR_HW_INIT); + /* DMA 64bytes-unit transfer count */ + mem_write32(dma_get_rtdma_tcr_addr(DMACH), TCR_HW_INIT); + + reg = mem_read32(RTDMA_DMSEC); + reg &= (~((uint32_t)1U << DMACH)); + mem_write32(RTDMA_DMSEC, reg); + + /* DMA operation */ + mem_write16(RTDMA_DMOR, DMOR_HW_INIT); +} +/* End of function dma_release(void) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_boot.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_boot.c new file mode 100644 index 0000000..92e5d0a --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_boot.c @@ -0,0 +1,249 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC boot + ******************************************************************************/ +/****************************************************************************** + * @file emmc_boot.c + * - Version : 0.07 + * @brief eMMC initialze interface. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 30.09.2021 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Add WWDT timer reset function + * : 06.04.2022 0.05 Fix Set SDCLK to 200MHz + * : 23.05.2022 0.06 Integration of S4 and V4H + * : 24.06.2024 0.07 Add process that set SDHI_D1.8/3.3V to 1.8V. + *****************************************************************************/ + +#include "emmc_boot.h" +#include "mem_io.h" +#include "log.h" +#include "rom_api.h" +#include "image_load_emmc.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_multiboot.h" +#include "emmc_def.h" +#include "emmc_config.h" +#if (RCAR_LSI == RCAR_V4M) /* Gray Hawk */ +#include "i2c.h" +#include "remap.h" +#endif /* (RCAR_LSI == RCAR_V4M) */ + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Unions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Structs */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Globals */ +/************************************************************************************************/ + +/************************************************************************************************/ +/* Macros */ +/************************************************************************************************/ + +/************************************************************************************************/ +/* Prototypes */ +/************************************************************************************************/ +static void power_on_mmc(void); +static void set_sd_clock(void); +static void init_mmc_pin_function(void); +#if (RCAR_LSI == RCAR_V4M) /* Gray Hawk */ +static void sdhi_random_address_read_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *rd_buf); +static void sdhi_page_write_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *wr_buf); +static void pmic_set_sdhi_vdd18(void); +#endif /* (RCAR_LSI == RCAR_V4M) */ + +void emmc_initialize( void ) +{ +#if (RCAR_LSI == RCAR_V4M) /* Gray Hawk */ + /* Register I2C base address(physical:0xE6600000) to SIC REMAP14 for V4M. */ + set_sicremap_fcpr(); + pmic_set_sdhi_vdd18(); +#endif /* (RCAR_LSI == RCAR_V4M) */ + + /***************************************************************** + PFC setting + *****************************************************************/ + init_mmc_pin_function(); + + /***************************************************************** + CPG setting + *****************************************************************/ + power_on_mmc(); + set_sd_clock(); + +#if (RCAR_SA9_TYPE == EMMC_BOOT) + EMMC_ERROR_CODE result; + /* eMMC driver initialize */ + (void)emmc_init(); /* Normal clock mode */ + + /* Card power on */ + (void)emmc_memcard_power(TRUE); + + /* Card mount */ + result = emmc_mount(); + + if (result != EMMC_SUCCESS) + { + NOTICE("eMMC initialize error!!\n"); + panic; + } +#endif /* (RCAR_SA9_TYPE == EMMC_BOOT) */ +} /* End of function emmc_initialize( void ) */ + +/************************************************************************************************/ +/* Func power_on_mmc */ +/************************************************************************************************/ +static void power_on_mmc(void) +{ + uint32_t reg; + uint32_t tmp_val; + + tmp_val = CPG_MSTPCR_SDHI; + + reg = mem_read32(CPG_MSTPCR7D0); + if ((reg & tmp_val) != 0x0U) + { + reg &= ~(tmp_val); + cpg_reg_write(CPG_MSTPCR7D0, CPG_MSTPSR7D0, reg); + } + + do + { + reg = mem_read32(CPG_MSTPCR7D0); + } + while ((reg & tmp_val) != 0x0U); /* wait tmp_val=0 */ +} /* End of function power_on_mmc(void) */ + +/************************************************************************************************/ +/* Func set_sd_clock */ +/************************************************************************************************/ +static void set_sd_clock(void) +{ + uint32_t reg; + + reg = mem_read32(CPG_SD0CKCR0); + reg &= (~(CPG_SD0CKCR0_STP0HCK | CPG_SD0CKCR0_SDSRCFC_MASK | CPG_SD0CKCR0_SD0FC_MASK)); + reg |= CPG_SD0CKCR0_200MHZ; + cpg_reg_write(CPG_SD0CKCR0, CPG_SD0CKCR0, reg); /* Stop SDnH clock & SDn=200MHz */ +} /* End of function set_sd_clock(void) */ + +/************************************************************************************************/ +/* Func init_mmc_pin_function */ +/************************************************************************************************/ +static void init_mmc_pin_function(void) +{ + uint32_t reg; + + reg = mem_read32(PFC_POC_MMC_RW); + reg &= (~(PFC_POC_MMC_MASK)); + reg |= PFC_POC_MMC_VAL; + pfc_reg_write(PFC_POC_MMC_RW, reg); +} /* End of function init_mmc_pin_function(void) */ + +#if (RCAR_LSI == RCAR_V4M) /* Gray Hawk */ +static void sdhi_random_address_read_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *rd_buf) +{ + uint32_t data; + + /* for PMIC_RAA271005 */ + data = (access_add & 0x300U) >> 8U; + i2c3_write(sl_add, 0x00U, data); /* Bank Set */ + + i2c3_read(sl_add, (access_add & 0x0FFU), rd_buf); +} +/* End of function sdhi_random_address_read_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *rd_buf) */ + +static void sdhi_page_write_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *wr_buf) +{ + uint32_t data; + + /* for PMIC_RAA271005 */ + data = (access_add & 0x300U) >> 8U; + i2c3_write(sl_add, 0x00U, data); /* Bank Set */ + + i2c3_read(sl_add, (access_add & 0x0FFU), wr_buf); +} +/* End of function sdhi_page_write_pmic(uint32_t sl_add, uint32_t access_add, uint32_t *wr_buf) */ + +static void pmic_set_sdhi_vdd18(void) +{ + /* In case of Gray Hawk board, change SDHI_18/33 voltage. */ + uint32_t slv_addr = 0xA8U; /* for PMIC-RAA271005: "reg 0xA8 0xA9 prot 0xAA 0xAB" */ + uint32_t data; + + /* Init I2C */ + i2c3_init(); + + /* Setting 1.8V to SDHI_D1.8/3.3V(VDDQ18_33_SDHI) on PMIC-RAA271005 */ + data = 0x1U; + i2c3_write(slv_addr, 0x00U, data); /* Write IO_PAGE. Chenge BANK1 */ + + i2c3_read(slv_addr, 0x3BU, &data); + if ((data & 0x0CU) != 0x0U) + { + data &= ~(0x0CU); + i2c3_write(slv_addr, 0x3BU, data); + } + + sdhi_random_address_read_pmic(slv_addr, 0x02U, &data); + if ((data & 0xF0U) == 0xB0U) + { + // RAA271005 rev.B only + data = 0x1U; + sdhi_page_write_pmic(slv_addr, 0x00U, &data); /* Write IO_PAGE. Chenge BANK1 */ + + sdhi_random_address_read_pmic(slv_addr, 0x3BU, &data); /* Read FLT_CTRL1 */ + + data &= 0xF3U; /* LDO1 Fault remove */ + sdhi_page_write_pmic(slv_addr, 0x3BU, &data); /* Write FLT_CTRL1 */ + + data = 0x0U; + sdhi_page_write_pmic(slv_addr, 0x00U, &data); /* Write IO_PAGE. Chenge BANK0 */ + } + + data = 0x75U; /* LDO voltage 1.8V Value */ + i2c3_write(slv_addr, 0xBAU, data); + sdhi_random_address_read_pmic(slv_addr, 0xBAU, &data); +} +/* End of function pmic_set_sdhi_vdd18(void) */ +#endif /* (RCAR_LSI == RCAR_V4M) */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_cmd.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_cmd.c new file mode 100644 index 0000000..c2455b3 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_cmd.c @@ -0,0 +1,580 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC CMD driver + ******************************************************************************/ +/****************************************************************************** + * @file emmc_cmd.c + * - Version : 0.04 + * @brief control of CMD in SDHI. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.02.2022 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Modify SDHI access from DMA to PIO. + *****************************************************************************/ + +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "micro_wait.h" +#include "log.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static void emmc_read_response(uint32_t *response); +static void emmc_little_to_big(uint8_t *p, uint32_t value); +static void emmc_data_transfer_dma(void); +static EMMC_ERROR_CODE emmc_response_check(const uint32_t *response, uint32_t error_mask); +static void emmc_softreset(void); +static void emmc_WaitCmd2Cmd_8Cycle(void); + +/* ********************************* CODE ********************************** */ + +/* execute MMC command. + * + * - Pre-conditions:
+ * * Clock to memory card IF is enabled. + * - Post-conditions:
+ * Requested command is executed successfully + * + * param[in] error_mask Errors to be checked (error values; HAL_MEMCARD_ERRORS) + * param[in,out] *response Response from the card (virtual address) + * return eMMC error code. + */ +EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response) +{ + EMMC_ERROR_CODE rtn_code = EMMC_ERR; + HAL_MEMCARD_RESPONSE_TYPE response_type; + HAL_MEMCARD_COMMAND_TYPE cmd_type; + EMMC_INT_STATE state; + + /* parameter check */ + if (response == NULL) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.clock_enable != TRUE) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + if (mmc_drv_obj.state_machine_blocking == TRUE) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR); + return EMMC_ERR; + } + + state = ESTATE_BEGIN; + response_type = (HAL_MEMCARD_RESPONSE_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK); + cmd_type = (HAL_MEMCARD_COMMAND_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_COMMAND_TYPE_MASK); + + /* state machine */ + while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END)) { + /* The interrupt factor flag is observed. */ + (void)emmc_interrupt(); + + /* wait interrupt */ + if (mmc_drv_obj.state_machine_blocking == TRUE) { + continue; + } + + switch (state) { + case ESTATE_BEGIN: + /* Busy check */ + if ((mmc_drv_obj.error_info.info2 & SD_INFO2_CBSY) != 0U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR_CARD_BUSY; + } + + /* clear register */ + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, SD_INFO2_CLEAR); + mem_write32(SD_INFO1_MASK, SD_INFO1_INFO0); + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + + /* fallthrough */ + + case ESTATE_ISSUE_CMD: + /* ARG */ + mem_write32(SD_ARG, mmc_drv_obj.cmd_info.arg); + /* issue cmd */ + mem_write32(SD_CMD, mmc_drv_obj.cmd_info.hw); + /* Set driver flag */ + mmc_drv_obj.state_machine_blocking = TRUE; + + if (response_type == HAL_MEMCARD_RESPONSE_NONE) { + state = ESTATE_NON_RESP_CMD; + } else { + state = ESTATE_RCV_RESP; + } + + break; + + case ESTATE_NON_RESP_CMD: + /* interrupt disable */ + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); + + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 0U) { + /* not receive expected interrupt */ + rtn_code = EMMC_ERR_RESPONSE; + state = ESTATE_ERROR; + } else { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } + break; + + case ESTATE_RCV_RESP: + /* interrupt disable */ + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); + + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + break; + } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 0U) { + /* not receive expected interrupt */ + rtn_code = EMMC_ERR_RESPONSE; + state = ESTATE_ERROR; + break; + } else { + /* nop */ + } + + /* read response */ + emmc_read_response(response); + + /* check response */ + rtn_code = emmc_response_check(response, error_mask); + if (rtn_code != EMMC_SUCCESS) { + state = ESTATE_ERROR; + break; + } + + if (response_type == HAL_MEMCARD_RESPONSE_R1b) { + /* R1b */ + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + state = ESTATE_RCV_RESPONSE_BUSY; + } else { + state = ESTATE_CHECK_RESPONSE_COMPLETE; + } + break; + + case ESTATE_RCV_RESPONSE_BUSY: + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + break; + } + /* DAT0 not Busy */ + if ((SD_INFO2_DAT0 & mmc_drv_obj.error_info.info2) != 0U) { + state = ESTATE_CHECK_RESPONSE_COMPLETE; + break; + } + break; + + case ESTATE_CHECK_RESPONSE_COMPLETE: + if (cmd_type >= HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE) { + state = ESTATE_DATA_TRANSFER; + } else { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } + break; + + case ESTATE_DATA_TRANSFER: + /* ADTC command */ + mmc_drv_obj.during_transfer = TRUE; + mmc_drv_obj.state_machine_blocking = TRUE; + + if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) { + /* DMA */ + emmc_data_transfer_dma(); + } else { + /* PIO */ + /* interrupt enable (FIFO read/write enable) */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) { + mem_write32(SD_INFO2_MASK, ( SD_INFO2_BWE | SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + } else { + mem_write32(SD_INFO2_MASK, ( SD_INFO2_BRE | SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + } + } + state = ESTATE_DATA_TRANSFER_COMPLETE; + break; + + case ESTATE_DATA_TRANSFER_COMPLETE: + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_TRANSFER_ERROR; + break; + } else { + /* success. nothing to do. */ + } + + /* DMAC error ? */ + if (mmc_drv_obj.dma_error_flag == TRUE) { + /* Error occurred in DMAC driver. */ + rtn_code = EMMC_ERR_FROM_DMAC_TRANSFER; + state = ESTATE_TRANSFER_ERROR; + } else if (mmc_drv_obj.during_dma_transfer == TRUE) { + /* DMAC not finished. unknown error */ + rtn_code = EMMC_ERR; + state = ESTATE_TRANSFER_ERROR; + } else { + mem_write32(SD_INFO1_MASK, SD_INFO1_INFO2); + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + + mmc_drv_obj.state_machine_blocking = TRUE; + + state = ESTATE_ACCESS_END; + } + break; + + case ESTATE_ACCESS_END: + + /* clear flag */ + if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) { + mem_write32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ + mem_write32(SD_STOP, 0x00000000U); + mmc_drv_obj.during_dma_transfer = FALSE; + } + + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, SD_INFO2_CLEAR); + + if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO2) != 0U) { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } else { + state = ESTATE_ERROR; + } + break; + + case ESTATE_TRANSFER_ERROR: + /* The error occurred in the Data transfer. */ + if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) { + mem_write32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ + mem_write32(SD_STOP, 0x00000000U); + mmc_drv_obj.during_dma_transfer = FALSE; + } + /* fallthrough */ + + case ESTATE_ERROR: + emmc_softreset(); + ERROR("%s:0x%08x\n",__func__,rtn_code); + return rtn_code; + + default: + state = ESTATE_END; + break; + } /* switch (state) */ + } /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */ + + /* force terminate */ + if (mmc_drv_obj.force_terminate == TRUE) { + /* timeout timer is expired. Or, PIO data transfer error. */ + /* Timeout occurred in the DMA transfer. */ + if (mmc_drv_obj.during_dma_transfer == TRUE) { + mmc_drv_obj.during_dma_transfer = FALSE; + } + emmc_softreset(); + + return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */ + } + + /* success */ + mmc_drv_obj.during_transfer = FALSE; + + return EMMC_SUCCESS; +} + +/** host controller softrest. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param None. + * return None. + */ +static void emmc_softreset(void) +{ + int32_t loop = 10000; + int32_t retry = 1000; + + /* flag clear */ + mmc_drv_obj.during_transfer = FALSE; + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.state_machine_blocking = FALSE; + mmc_drv_obj.force_terminate = FALSE; + mmc_drv_obj.dma_error_flag = FALSE; + + /* during operation ? */ + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U) { + /* wait CMDSEQ = 0 */ + while (loop > 0) { + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) == 0U) { + break; /* ready */ + } + + loop--; + if ((loop == 0) && (retry > 0)) { + micro_wait(1000U); /* wait 1ms */ + loop = 10000; + retry--; + } + } + } + + /* reset */ + mem_write32(SOFT_RST, ( mem_read32(SOFT_RST) & (~SOFT_RST_SDRST) )); /* Soft reset */ + mem_write32(SOFT_RST, ( mem_read32(SOFT_RST) | SOFT_RST_SDRST )); /* Soft reset released */ + + /* initialize */ + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, SD_INFO2_CLEAR); + mem_write32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ + +} + +/** read response + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * param[in,out] *response Response from the card + * return None. + */ +static void emmc_read_response(uint32_t *response) +{ + + uint8_t *p = NULL; + + if (response == NULL) { + return; + } + + /* read response */ + if (mmc_drv_obj.response_length == EMMC_MAX_RESPONSE_LENGTH) { + /* CSD or CID */ + p = (uint8_t *)(response); + emmc_little_to_big(p, ((mem_read32(SD_RSP76) << 8U) | (mem_read32(SD_RSP54) >> 24U))); /* [127:96] */ + emmc_little_to_big(p + 4U, ((mem_read32(SD_RSP54) << 8U) | (mem_read32(SD_RSP32) >> 24U))); /* [95:64] */ + emmc_little_to_big(p + 8U, ((mem_read32(SD_RSP32) << 8U) | (mem_read32(SD_RSP10) >> 24U))); /* [63:32] */ + emmc_little_to_big(p + 12U, (mem_read32(SD_RSP10) << 8U)); /* [31:0] */ + } else { + *response = mem_read32(SD_RSP10); /* [39:8] */ + } +} + +/** response check + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * param[in] *response Response from the card + * param[in] error_mask Errors to be checked (for R1/R1b response) + * return error code. + */ +static EMMC_ERROR_CODE emmc_response_check(const uint32_t *response, uint32_t error_mask) +{ + + HAL_MEMCARD_RESPONSE_TYPE response_type = (HAL_MEMCARD_RESPONSE_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) + & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK); + + if (response == NULL) { + return EMMC_ERR_PARAM; + } + + if (response_type == HAL_MEMCARD_RESPONSE_NONE) { + return EMMC_SUCCESS; + } + + /* response check */ + if (response_type <= HAL_MEMCARD_RESPONSE_R1b) { + /* R1 or R1b */ + mmc_drv_obj.current_state = (EMMC_R1_STATE)((*response & EMMC_R1_STATE_MASK) >> EMMC_R1_STATE_SHIFT); + if ((*response & error_mask) != 0U) { + return EMMC_ERR_CARD_STATUS_BIT; + } + } else if (response_type == HAL_MEMCARD_RESPONSE_R4) { + /* R4 */ + if ((*response & EMMC_R4_STATUS) != 0U) { + return EMMC_ERR_CARD_STATUS_BIT; + } + } else { + ; /* nothing to do. other type does not have status bit */ + } + + return EMMC_SUCCESS; +} + +/** brief converts endian from little to big + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param[in,out] p destination buffer address. + * param[in] value convert data.(little) + * return None. + */ +static void emmc_little_to_big(uint8_t *p, uint32_t value) +{ + if (p == NULL) { + return; + } + + p[0] = (uint8_t)(value >> 24U); + p[1] = (uint8_t)(value >> 16U); + p[2] = (uint8_t)(value >> 8U); + p[3] = (uint8_t)value; +} + +/** data transfer with DMA. + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * return error code. + */ +static void emmc_data_transfer_dma(void) +{ + mmc_drv_obj.during_dma_transfer = TRUE; + mmc_drv_obj.dma_error_flag = FALSE; + + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + + /* DMAC setting */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) { + /* transfer complete interrupt enable */ + mem_write32(DM_CM_INFO1_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE )); + mem_write32(DM_CM_INFO2_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE )); + /* BUFF --> FIFO */ + mem_write32(DM_CM_DTRAN_MODE, ( DM_CM_DTRAN_MODE_CH0 | DM_CM_DTRAN_MODE_BIT_WIDTH )); /* CH0(downstream), 64-bit width */ + } else { + /* transfer complete interrupt enable */ + mem_write32(DM_CM_INFO1_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE )); + mem_write32(DM_CM_INFO2_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE )); + /* FIFO --> BUFF */ + mem_write32(DM_CM_DTRAN_MODE, ( DM_CM_DTRAN_MODE_CH1 | DM_CM_DTRAN_MODE_BIT_WIDTH )); /* CH0(downstream), 64-bit width */ + } + mem_write32(DM_DTRAN_ADDR, ( ( (uintptr_t)mmc_drv_obj.buff_address_virtual & DM_DTRAN_ADDR_WRITE_MASK ) )); /* Set address */ + + mem_write32(DM_CM_DTRAN_CTRL, DM_CM_DTRAN_CTRL_START); /* DMAC Start */ +} + +/** wait cmd-cmd 8cycle + * + * - Pre-conditions:
+ * + * - Post-conditions:
+ * . + * + * return None. + */ +static void emmc_WaitCmd2Cmd_8Cycle(void) +{ + uint32_t dataL, wait = 0U; + + dataL = mem_read32(SD_CLK_CTRL); + dataL &= 0x000000FFU; + + switch (dataL) { + case 0xFFU: /* 1/1 10 us wait ( 1/200MHz)*8= 0.04 us(min) */ + wait = 10U; + break; + case 0x00U: /* 1/2 10 us wait ( 2/200MHz)*8= 0.08 us(min) */ + wait = 10U; + break; + case 0x01U: /* 1/4 10 us wait ( 4/200MHz)*8= 0.16 us(min) */ + wait = 10U; + break; + case 0x02U: /* 1/8 10 us wait ( 8/200MHz)*8= 0.32 us(min) */ + wait = 10U; + break; + case 0x04U: /* 1/16 10 us wait ( 16/200MHz)*8= 0.64 us(min) */ + wait = 10U; + break; + case 0x08U: /* 1/32 10 us wait ( 32/200MHz)*8= 1.28 us(min) */ + wait = 10U; + break; + case 0x10U: /* 1/64 10 us wait ( 64/200MHz)*8= 2.56 us(min) */ + wait = 10U; + break; + case 0x20U: /* 1/128 10 us wait (128/200MHz)*8= 5.12 us(min) */ + wait = 10U; + break; + case 0x40U: /* 1/256 20 us wait (256/200MHz)*8= 10.24 us(min) */ + wait = 20U; + break; + case 0x80U: /* 1/512 30 us wait (512/200MHz)*8= 20.48 us(min) */ + wait = 30U; + break; + default: + /* nop */ + break; + } + micro_wait(wait); + +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_init.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_init.c new file mode 100644 index 0000000..46ed5ca --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_init.c @@ -0,0 +1,311 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC initialze + ******************************************************************************/ +/****************************************************************************** + * @file emmc_init.c + * - Version : 0.05 + * @brief initialize of SDHI driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.02.2022 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Modify SDHI access from DMA to PIO. + * : 06.04/2022 0.05 Del SDnH clock & SDn=200MHz(Duplicate settings) + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ +st_mmc_base mmc_drv_obj; + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static void emmc_drv_init(void); +static EMMC_ERROR_CODE emmc_dev_init(void); +static EMMC_ERROR_CODE emmc_dev_finalize(void); +static void emmc_memset(void *buff, uint8_t data, uint32_t cnt); +static EMMC_ERROR_CODE emmc_reset_controller(void); +static void emmc_driver_config(void); +static void emmc_set_data_timeout(uint32_t data_timeout); + +/* ********************************* CODE ********************************** */ + +/** brief eMMC initialize. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR error from interrupt API. + */ +EMMC_ERROR_CODE emmc_init(void) +{ + /* initialize H/W */ + (void)emmc_reset_controller(); + + /* Configuration */ + emmc_driver_config(); + + return EMMC_SUCCESS; +} + +/** terminate emmc driver + * + * EMMC H/W and S/W resource is released. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * return None. + */ +EMMC_ERROR_CODE emmc_terminate(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* H/W finalize */ + result = emmc_dev_finalize(); + + /* driver finalize */ + emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base)); /* clear global variable */ + + return result; +} + +/** Function executes full reset to MMC host controller without taking power out from the memory card. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * Reset MMC host controller without taking power out from the memory card. + * Memory card preserves its state. + * + * return None + */ +static EMMC_ERROR_CODE emmc_reset_controller(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* initialize mmc driver */ + emmc_drv_init(); + + mmc_drv_obj.base_address = MMC0_SD_BASE; + + /* initialize H/W */ + result = emmc_dev_init(); + + mmc_drv_obj.initialize = TRUE; + + return result; + +} + +/** Configuration eMMC driver + * + * - Pre-conditions:
+ * initialized eMMC driver. + * - Post-conditions:
+ * . + * + * return None + */ +static void emmc_driver_config(void) +{ + /* Read/Write data timeout */ + emmc_set_data_timeout(EMMC_RW_DATA_TIMEOUT); +} + +/** Sets data timeout + * + * Sets the data timeout value for read and write operations. + * + * - Pre-conditions:
+ * initialized eMMC driver. + * + * - Post-conditions:
+ * After this function is called, the timeout value is set according to argument. + * + * param[in] time_out The desired timeout value in milliseconds. + * return None + */ +static void emmc_set_data_timeout(uint32_t data_timeout) +{ + mmc_drv_obj.data_timeout = data_timeout; +} + +/** eMMC driver initialize. (software) + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * return None. + */ +static void emmc_drv_init(void) +{ + /* initialize */ + emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base)); + + mmc_drv_obj.data_timeout = EMMC_RW_DATA_TIMEOUT; + + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; +} + +/** eMMC driver initialize. (H/W) + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * return None. + */ +static EMMC_ERROR_CODE emmc_dev_init(void) +{ + + /* MMCIF initialize */ + mem_write32(SD_INFO1, 0x00000000U); /* all interrupt clear */ + mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* all interrupt clear */ + mem_write32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ + + mem_write32(HOST_MODE, 0x00000000U); /* SD_BUF access width = 64-bit */ + mem_write32(SD_OPTION, 0x0000C0EEU); /* Bus width = 1bit, timeout=MAX */ + mem_write32(SD_CLK_CTRL, 0x00000000U); /* Automatic Control=Disable, Clock Output=Disable */ + + return EMMC_SUCCESS; +} + +/** EMMC H/W finalize + * + * EMMC Host and Card hardware resource is released. + * + * - Pre-conditions:
+ * . + * + * - Post-conditions:
+ * . + * return None. + */ +static EMMC_ERROR_CODE emmc_dev_finalize(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* MMC power off + * the power supply of eMMC device is always turning on. + * RST_n : Hi --> Low level. + */ + result = emmc_memcard_power(FALSE); + + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, 0x00000800U); + mem_write32(DM_CM_INFO1, 0x00000000U); + mem_write32(DM_CM_INFO2, 0x00000000U); + + mem_write32(SD_CLK_CTRL, 0x00000020U); + mem_write32(CC_EXT_MODE, 0x00000000U); + mem_write32(SD_STOP, 0x00000000U); + mem_write32(SD_SECCNT, 0x00000000U); + mem_write32(DM_CM_DTRAN_MODE, 0x00000000U); + mem_write32(DM_DTRAN_ADDR, 0x00000000U); + mem_write32(SD_OPTION, 0x00000000U); + mem_write32(DM_CM_DTRAN_CTRL, 0x00000000U); + + return result; +} + +/** Set power to memory card IF. + * This function control Vcc and Vccq and RST_n. + * + * attention + * CPU cannot control Vcc&Vccq. + * The power supply of eMMC device is always turning on. + * + * param[in] mode TRUE = power on, FALSE = power off + * + * retval EMMC_SUCCESS powering succeeded + * retval EMMC_ERR_CARD_POWER powering failed + */ +EMMC_ERROR_CODE emmc_memcard_power(uint32_t mode) +{ + if (mode == TRUE) { + /* power on (Vcc&Vccq is always power on) */ + mmc_drv_obj.card_power_enable = TRUE; + } else { + /* power off (Vcc&Vccq is always power on) */ + mmc_drv_obj.card_power_enable = FALSE; + mmc_drv_obj.mount = FALSE; + mmc_drv_obj.selected = FALSE; + } + + return EMMC_SUCCESS; +} + +/** memset(). no use C standard library. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param[in,out] buff pointer to buffer (virtual) + * param[in] data fill data. + * param[in] cnt fill size (number of bytes) + * return None. + */ +static void emmc_memset(void *buff, uint8_t data, uint32_t cnt) +{ + uint8_t *tmp = NULL; + tmp = (uint8_t *)buff; + + if (buff == NULL) { + return; + } + + while (cnt > 0U) { + *tmp = data; + tmp++; + cnt--; + } +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_interrupt.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_interrupt.c new file mode 100644 index 0000000..e1d344d --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_interrupt.c @@ -0,0 +1,227 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC interrupt + ******************************************************************************/ +/****************************************************************************** + * @file emmc_interrupt.c + * - Version : 0.04 + * @brief state check of SDHI. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.02.2022 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Modify SDHI access from DMA to PIO. + *****************************************************************************/ + +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "log.h" +#include +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual); + + +/* ********************************* CODE ********************************** */ + + + +/** emmc driver interrupt service routine. + * + * - Pre-conditions:
+ * Must be block emmc driver state machine. + * - Post-conditions:
+ * unblocking emmc driver state machine. + * + * retval INT_SUCCESS + */ +uint32_t emmc_interrupt(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* SD_INFO */ + mmc_drv_obj.error_info.info1 = mem_read32(SD_INFO1); + mmc_drv_obj.error_info.info2 = mem_read32(SD_INFO2); + + /* SD_INFO EVENT */ + mmc_drv_obj.int_event1 = mmc_drv_obj.error_info.info1 & mem_read32(SD_INFO1_MASK); + mmc_drv_obj.int_event2 = mmc_drv_obj.error_info.info2 & mem_read32(SD_INFO2_MASK); + + /* ERR_STS */ + mmc_drv_obj.error_info.status1 = mem_read32(SD_ERR_STS1); + mmc_drv_obj.error_info.status2 = mem_read32(SD_ERR_STS2); + + /* DM_CM_INFO */ + mmc_drv_obj.error_info.dm_info1 = mem_read32(DM_CM_INFO1); + mmc_drv_obj.error_info.dm_info2 = mem_read32(DM_CM_INFO2); + + /* DM_CM_INFO EVENT */ + mmc_drv_obj.dm_event1 = mmc_drv_obj.error_info.dm_info1 & mem_read32(DM_CM_INFO1_MASK); + mmc_drv_obj.dm_event2 = mmc_drv_obj.error_info.dm_info2 & mem_read32(DM_CM_INFO2_MASK); + + /* ERR SD_INFO2 */ + if ((SD_INFO2_ALL_ERR & mmc_drv_obj.int_event2) != 0U) { + mem_write32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */ + mem_write32(SD_INFO1, 0x00000000U); /* interrupt clear */ + mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } + + /* PIO Transfer */ + /* BWE/BRE */ + else if ((( SD_INFO2_BWE | SD_INFO2_BRE) & mmc_drv_obj.int_event2) != 0U) { + /* BWE */ + if (( SD_INFO2_BWE & mmc_drv_obj.int_event2) != 0U) { + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BWE)); /* interrupt clear */ + } + /* BRE */ + else { + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BRE)); /* interrupt clear */ + } + + result = emmc_trans_sector((uint32_t *)mmc_drv_obj.buff_address_virtual); /* sector R/W */ + mmc_drv_obj.buff_address_virtual += EMMC_BLOCK_LENGTH; + mmc_drv_obj.remain_size -= EMMC_BLOCK_LENGTH; + + if (result != EMMC_SUCCESS) { + /* data transfer error */ + ERROR("%s:0x%08x\n",__func__, result); + + /* Panic */ + mem_write32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */ + mem_write32(SD_INFO1, 0x00000000U); /* interrupt clear */ + mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */ + mmc_drv_obj.force_terminate = TRUE; + } else { + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; + } + + /* DMA_TRANSFER */ + /* DM_CM_INFO1: DMA-ch0 transfer complete or error occured */ + else if ((DM_CM_INFO_DTRANEND0 & mmc_drv_obj.dm_event1) != 0U) { + mem_write32(DM_CM_INFO1, 0x00000000U); + mem_write32(DM_CM_INFO2, 0x00000000U); + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BWE)); /* interrupt clear */ + /* DM_CM_INFO2: DMA-ch0 error occured */ + if (( DM_CM_INFO_DTRANEND0 & mmc_drv_obj.dm_event2) != 0U) { + mmc_drv_obj.dma_error_flag = TRUE; + } else { + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; /* wait next interrupt */ + } + /* DM_CM_INFO1: DMA-ch1 transfer complete or error occured */ + else if ((DM_CM_INFO_DTRANEND1 & mmc_drv_obj.dm_event1) != 0U) { + mem_write32(DM_CM_INFO1, 0x00000000U); + mem_write32(DM_CM_INFO2, 0x00000000U); + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BRE)); /* interrupt clear */ + /* DM_CM_INFO2: DMA-ch1 error occured */ + if (( DM_CM_INFO_DTRANEND1 & mmc_drv_obj.dm_event2) != 0U) { + mmc_drv_obj.dma_error_flag = TRUE; + } else { + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; /* wait next interrupt */ + } + + /* Response end */ + else if ((SD_INFO1_INFO0 & mmc_drv_obj.int_event1) != 0U) { + mem_write32(SD_INFO1, (mem_read32(SD_INFO1) & ~SD_INFO1_INFO0)); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } + /* Access end */ + else if ((SD_INFO1_INFO2 & mmc_drv_obj.int_event1) != 0U) { + mem_write32(SD_INFO1, (mem_read32(SD_INFO1) & ~SD_INFO1_INFO2)); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } else { + /* nothing to do. */ + } + + return 0U; +} + +/** Data transfer function with PIO (Single sector). + * + * - Pre-conditions:
+ * Called from interrupt service. + * - Post-conditions:
+ * . + * + * param[in,out] buff_address_virtual Dest/Src buffer address(virtual). + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_PARAM parameter error. + * retval EMMC_ERR_STATE state error. + */ +static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual) +{ + uint32_t length, i; + uint64_t *bufPtrLL; + + if (buff_address_virtual == NULL) { + return EMMC_ERR_PARAM; + } + + if ((mmc_drv_obj.during_transfer != TRUE) || (mmc_drv_obj.remain_size == 0U)) { + return EMMC_ERR_STATE; + } + + bufPtrLL = (uint64_t*)buff_address_virtual; + length = mmc_drv_obj.remain_size; + + /* data transefer */ + for (i = 0U; i < (length >> 3U); i++) { + /* Write */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) { + mem_write64(SD_BUF0, *bufPtrLL); /* buffer --> FIFO */ + } + /* Read */ + else { + *bufPtrLL = mem_read64(SD_BUF0); /* FIFO --> buffer */ + } + bufPtrLL++; + } + + return EMMC_SUCCESS; +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_mount.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_mount.c new file mode 100644 index 0000000..ba0a0f9 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_mount.c @@ -0,0 +1,767 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC Mount + ******************************************************************************/ +/****************************************************************************** + * @file emmc_mount.c + * - Version : 0.04 + * @brief initialize of condition. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.02.2022 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Modify SDHI access from DMA to PIO. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include +#include "micro_wait.h" +#include "remap.h" +#include "log.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static EMMC_ERROR_CODE emmc_clock_ctrl(uint32_t mode); +static EMMC_ERROR_CODE emmc_card_init(void); +static EMMC_ERROR_CODE emmc_high_speed(void); +static EMMC_ERROR_CODE emmc_bus_width(uint32_t width); +static uint32_t emmc_set_timeout_register_value(uint32_t freq); +static void set_sd_clk(uint32_t clkDiv); +static uint32_t emmc_calc_tran_speed(uint32_t* freq); + +/* ********************************* CODE ********************************** */ + +/** eMMC mount operation. + * + * Sequence is the following. + * 1) Bus initialization (emmc_card_init()) + * 2) Switching to high speed mode. (emmc_high_speed()) + * 3) Changing the data bus width. (emmc_bus_width()) + * + * - Pre-conditions:
+ * eMMC driver is initialized. The power supply of MMC IF must be turning on. + * - Post-conditions:
+ * MMC card state changes to transfer state. + * + * return eMMC error code. + */ +EMMC_ERROR_CODE emmc_mount(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || (mmc_drv_obj.card_power_enable != TRUE) + || ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U)) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* initialize card (IDLE state --> Transfer state) */ + result = emmc_card_init(); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + (void)emmc_clock_ctrl(FALSE); + return result; + } + + /* Switching high speed mode */ + result = emmc_high_speed(); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + (void)emmc_clock_ctrl(FALSE); + return result; + } + + /* Changing the data bus width */ + result = emmc_bus_width(8U); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + (void)emmc_clock_ctrl(FALSE); + return result; + } + + /* mount complete */ + mmc_drv_obj.mount = TRUE; + + return EMMC_SUCCESS; +} + +/** Bus initialization function + * + * - Pre-conditions:
+ * eMMC driver is initialized. The power supply of MMC IF must be turning on. + * - Post-conditions:
+ * MMC card state changes to transfer state. + * + * retval EMMC_SUCCESS successful. + * return eMMC error code. + * attention upper layer must be check pre-conditions. + */ +static EMMC_ERROR_CODE emmc_card_init(void) +{ + int32_t retry; + uint32_t freq = MMC_400KHZ; /* 390KHz */ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t resultCalc = 0U; + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || (mmc_drv_obj.card_power_enable != TRUE) + || ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U)) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* clock on (force change) */ + mmc_drv_obj.current_freq = 0U; + mmc_drv_obj.max_freq = MMC_20MHZ; /* MMC_20MHZ = MMC_12MHZ = 12.187MHz */ + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return EMMC_ERR; + } + + micro_wait(1000U); /* wait 1ms */ + + /* CMD0, arg=0x00000000 */ + result = emmc_send_idle_cmd (0x00000000U); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + micro_wait(200U); /* wait 74clock 390kHz(189.74us)*/ + + /* CMD1 */ + emmc_make_nontrans_cmd(CMD1_SEND_OP_COND, EMMC_HOST_OCR_VALUE); + for (retry = 300; retry > 0; retry--) { + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + if ((mmc_drv_obj.r3_ocr & EMMC_OCR_STATUS_BIT) != 0U) { + break; /* card is ready. exit loop */ + } + micro_wait(1000U); /* wait 1ms */ + } + + if (retry == 0) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_TIMEOUT); + return EMMC_ERR_TIMEOUT; + } + + if ((mmc_drv_obj.r3_ocr & EMMC_OCR_ACCESS_MODE_MASK) != EMMC_OCR_ACCESS_MODE_SECT) { + /* unknown value */ + ERROR("%s:0x%08x\n",__func__,EMMC_ERR); + return EMMC_ERR; + } + + /* CMD2 */ + emmc_make_nontrans_cmd(CMD2_ALL_SEND_CID_MMC, 0x00000000U); + mmc_drv_obj.response = (uint32_t *)(&mmc_drv_obj.cid_data[0U]); /* use CID special buffer */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + /* CMD3 */ + emmc_make_nontrans_cmd(CMD3_SET_RELATIVE_ADDR, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + /* CMD9 : CSD */ + emmc_make_nontrans_cmd(CMD9_SEND_CSD, EMMC_RCA << 16U); + mmc_drv_obj.response = (uint32_t *)(&mmc_drv_obj.csd_data[0U]); /* use CSD special buffer */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + /* card version check */ + if (EMMC_CSD_SPEC_VARS() < 4U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_ILLEGAL_CARD); + return EMMC_ERR_ILLEGAL_CARD; + } + + /* CMD7 (select card) */ + emmc_make_nontrans_cmd(CMD7_SELECT_CARD, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + mmc_drv_obj.selected = TRUE; + + /* card speed check */ + resultCalc = emmc_calc_tran_speed(&freq); /* Card spec is calculated from TRAN_SPEED(CSD). */ + if (resultCalc == 0U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_ILLEGAL_CARD); + return EMMC_ERR_ILLEGAL_CARD; + } + mmc_drv_obj.max_freq = freq; /* max frequency (card spec) */ + + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return EMMC_ERR; + } + + /* set read/write timeout */ + mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(freq); + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) | mmc_drv_obj.data_timeout)); + + /* SET_BLOCKLEN:512byte */ + /* CMD16 */ + emmc_make_nontrans_cmd(CMD16_SET_BLOCKLEN, EMMC_BLOCK_LENGTH); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + /* Transfer Data Length */ + mem_write32(SD_SIZE, EMMC_BLOCK_LENGTH); + + /* CMD8 : EXT_CSD */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0U]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + /* CMD12 is not send. + * If BUS initialization is failed, user must be execute Bus initialization again. + * Bus initialization is start CMD0(soft reset command). + */ + ERROR("%s\n",__func__); + return result; + } + + return EMMC_SUCCESS; +} + +/** Switching to high-speed mode + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * EXT_CSD data must be stored in mmc_drv_obj.ext_csd_data[]. + * + * - Post-conditions:
+ * Change the clock frequency to 26MHz or 52MHz. + * + * retval EMMC_SUCCESS successful or aleady switching. + * retval EMMC_ERR_STATE state error. + * retval EMMC_ERR unknown error. + * return emmc error code. + */ +static EMMC_ERROR_CODE emmc_high_speed(void) +{ + uint32_t freq; /**< High speed mode clock frequency */ + EMMC_ERROR_CODE result = EMMC_ERR; + uint8_t cardType; + + /* state check */ + if (mmc_drv_obj.selected != TRUE) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* max frequency */ + cardType = (uint8_t)mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_CARD_TYPE]; + if ((cardType & EMMC_EXT_CSD_CARD_TYPE_52MHZ) != 0U) { + freq = MMC_52MHZ; + } else if ((cardType & EMMC_EXT_CSD_CARD_TYPE_26MHZ) != 0U) { + freq = MMC_26MHZ; + } else { + freq = MMC_20MHZ; + } + + /* Hi-Speed-mode selction */ + if (( MMC_52MHZ == freq) || ( MMC_26MHZ == freq)) { + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + } + + /* set mmc clock */ + mmc_drv_obj.max_freq = freq; + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return EMMC_ERR; + } + + /* set read/write timeout */ + mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(freq); + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) | mmc_drv_obj.data_timeout)); + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK_WITHOUT_CRC, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + ERROR("%s\n",__func__); + return result; + } + + return EMMC_SUCCESS; +} + +/** Changing the data bus width + * + * if chinging the data bus width failed, card is reset by CMD0. + * Please do Bus initialization over again. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * + * - Post-conditions:
+ * Change the data bus width to 8bit or 4bit. + * mmc_drv_obj.ext_csd_data is updated. + * + * param[in] width bus width (8 or 4) + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_PARAM parameter error + * retval EMMC_ERR_STATE state error. + * + */ +static EMMC_ERROR_CODE emmc_bus_width(uint32_t width) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* parameter check */ + if ((width != 8U) && (width != 4U) && (width != 1U)) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.selected != TRUE) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH)(width >> 2U); /* 2 = 8bit, 1 = 4bit, 0 =1bit */ + + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, ( EMMC_SWITCH_BUS_WIDTH_1 | ((uint32_t)(mmc_drv_obj.bus_width) << 8U))); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + /* occurred error */ + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; + goto EXIT; + } + + switch (mmc_drv_obj.bus_width) { + case HAL_MEMCARD_DATA_WIDTH_1_BIT: + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_WIDTH|SD_OPTION_WIDTH8)) | SD_OPTION_WIDTH )); + break; + case HAL_MEMCARD_DATA_WIDTH_4_BIT: + mem_write32(SD_OPTION, (mem_read32(SD_OPTION) & ~(SD_OPTION_WIDTH|SD_OPTION_WIDTH8))); + break; + case HAL_MEMCARD_DATA_WIDTH_8_BIT: + default: + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_WIDTH|SD_OPTION_WIDTH8)) | SD_OPTION_WIDTH8 )); + break; + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + goto EXIT; + } + + /* CMD8 : EXT_CSD */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0U]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + goto EXIT; + } + + return EMMC_SUCCESS; + +EXIT: + ERROR("%s:0x%08x\n",__func__,result); + return result; +} + +/** select access partition + * + * This function write the EXT_CSD register(PARTITION_ACCESS: PARTITION_CONFIG[2:0]). + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * selected partition can access. + * + * param[in] id user selects partitions to access. + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_STATE state error. + * retval EMMC_ERR_PARAM parameter error. + * return emmc error code. + */ +EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t partition; + uint32_t partition_config; + + /* state check */ + if (mmc_drv_obj.mount != TRUE) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* id has PARTITION_ACCESS(Bit[2:0]) */ + if ((uint32_t)((uint32_t)id & ~(uint32_t)PARTITION_ID_MASK) != 0U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* EXT_CSD[179] value */ + partition_config = (uint32_t)mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_PARTITION_CONFIG]; + if ((partition_config & (uint32_t)PARTITION_ID_MASK) == (uint32_t)id) { + result = EMMC_SUCCESS; + } else { + + partition_config = ((partition_config & (~(uint32_t)PARTITION_ID_MASK)) | (uint32_t)id); + partition = EMMC_SWITCH_PARTITION_CONFIG | (partition_config << 8U); + + result = emmc_set_ext_csd(partition); + } + + return result; +} + +/** set EXT CSD data + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * mmc_drv_obj.ext_csd_data[] is updated. + * + * param[in] arg argument of CMD6 + * return emmc error code. + */ +EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, arg); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + + /* CMD8 : EXT_CSD */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0U]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + return EMMC_SUCCESS; +} + +/** set request MMC clock frequency. + * + * Function returns EMMC_SUCCESS if clock is already running in the desired frequency. + * EMMC_ERR is returned if the HW doesn't support requested clock frequency. + * If matching frequence cannot be set the closest frequence below should be selected. + * For example if 50MHz is requested, but HW supports only 48MHz then 48MHz should be returned in the freq parameter. + * + * - Pre-conditions:
+ * initialized eMMC driver with emmc_init(). + * Memory card and MMCSDIO host controller needs to be powered up beforehand. + * + * - Post-conditions:
+ * Desired clock frequency is set to memory card IF. + * + * param[in] freq frequency [Hz] + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_STATE state error. + * retval EMMC_ERR busy + */ +EMMC_ERROR_CODE emmc_set_request_mmc_clock(const uint32_t *freq) +{ + /* parameter check */ + if (freq == NULL) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || (mmc_drv_obj.card_power_enable != TRUE)) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* clock is already running in the desired frequency. */ + if ((mmc_drv_obj.clock_enable == TRUE) && (mmc_drv_obj.current_freq == *freq)) { + return EMMC_SUCCESS; + } + + /* busy check */ + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR; + } + + set_sd_clk(*freq); + mmc_drv_obj.clock_enable = FALSE; + + return emmc_clock_ctrl(TRUE); /* clock on */ +} + +/** set sd clock. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * set mmc clock. + * + * param[in] clkDiv request freq + * return None. + */ +static void set_sd_clk(uint32_t clkDiv) +{ + uint32_t dataL; + + dataL = (mem_read32(SD_CLK_CTRL) & (~SD_CLK_CTRL_CLKDIV_MASK)); + + switch (clkDiv) { + case 1U: /* 1/1 */ + dataL |= 0x000000FFU; + break; + case 2U: /* 1/2 */ + dataL |= 0x00000000U; + break; + case 4U: /* 1/4 */ + dataL |= 0x00000001U; + break; + case 8U: /* 1/8 */ + dataL |= 0x00000002U; + break; + case 16U: /* 1/16 */ + dataL |= 0x00000004U; + break; + case 32U:/* 1/32 */ + dataL |= 0x00000008U; + break; + case 64U:/* 1/64 */ + dataL |= 0x00000010U; + break; + case 128U:/* 1/128 */ + dataL |= 0x00000020U; + break; + case 256U: /* 1/256 */ + dataL |= 0x00000040U; + break; + case 512U:/* 1/512 */ + dataL |= 0x00000080U; + break; + default: + /* nop */ + break; + } + + mem_write32(SD_CLK_CTRL, dataL); + mmc_drv_obj.current_freq = (uint32_t)clkDiv; +} + + +/** Enable/Disable MMC clock + * + * - Pre-conditions:
+ * Before enabling the clock for the first time the desired clock frequency must be set with + * emmc_set_clock_freq(). + * Berore setting mmc_drv_obj.data_timeout with emmc_set_data_timeout(). + * + * - Post-conditions:
+ * After this function is called, clock to memory card IF is on/off. + * + * param[in] mode TRUE = clock on, FALSE = clock off + * retval EMMC_SUCCESS succeeded + * retval EMMC_ERR Busy + */ +static EMMC_ERROR_CODE emmc_clock_ctrl(uint32_t mode) +{ + uint32_t value; + + /* busy check */ + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR; + } + + if (mode == TRUE) { + /* clock ON */ + value = ((mem_read32(SD_CLK_CTRL) | MMC_SD_CLK_START) & SD_CLK_WRITE_MASK); + mem_write32(SD_CLK_CTRL, value); /* on */ + mmc_drv_obj.clock_enable = TRUE; + } else { + /* clock OFF */ + value = ((mem_read32(SD_CLK_CTRL) & MMC_SD_CLK_STOP) & SD_CLK_WRITE_MASK); + mem_write32(SD_CLK_CTRL, value); /* off */ + mmc_drv_obj.clock_enable = FALSE; + } + + return EMMC_SUCCESS; +} + +/** Calculate Card support frequency. + * TRAN_SPEED defines the clock frequency when not in high speed mode. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * None. + * return Frquency[Hz] + */ +static uint32_t emmc_calc_tran_speed(uint32_t* freq) +{ + const uint32_t unit[8U] = {10000U, 100000U, 1000000U, 10000000U, 0U, 0U, 0U, 0U}; /**< frequency unit (1/10) */ + const uint32_t mult[16U] = {0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, 35U, 40U, 45U, 52U, 55U, 60U, 70U, 80U}; /**< multiple factor (x10) */ + uint32_t maxFreq = 0U; + uint32_t result = 0U; + uint32_t tran_speed = EMMC_CSD_TRAN_SPEED(); + + /* tran_speed = 0x32 + * unit[tran_speed&0x7] = uint[0x2] = 1000000 + * mult[(tran_speed&0x78)>>3] = mult[0x30>>3] = mult[6] = 26 + * 1000000 * 26 = 26000000 (26MHz) + */ + + maxFreq = unit[tran_speed & EMMC_TRANSPEED_FREQ_UNIT_MASK] + * mult[(tran_speed & EMMC_TRANSPEED_MULT_MASK) >> EMMC_TRANSPEED_MULT_SHIFT]; + + if (maxFreq == 0U) { + result = 0U; + } else if ( MMC_FREQ_52MHZ <= maxFreq) { + *freq = MMC_52MHZ; + result = 1U; + } else if ( MMC_FREQ_26MHZ <= maxFreq) { + *freq = MMC_26MHZ; + result = 1U; + } else if ( MMC_FREQ_20MHZ <= maxFreq) { + *freq = MMC_20MHZ; + result = 1U; + } else { + *freq = MMC_400KHZ; + result = 1U; + } + + return result; +} + +/** Calculate read/write timeout. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * set mmc clock. + * + * param[in] freq Base clock Div + * return SD_OPTION Timeout Counter + */ +static uint32_t emmc_set_timeout_register_value(uint32_t freq) +{ + uint32_t timeoutCnt = 0U; /* SD_OPTION - Timeout Counter */ + + switch (freq) { + case 1U:/* SDCLK * 2^27 */ + timeoutCnt = 0xE0U; + break; + case 2U:/* SDCLK * 2^27 */ + timeoutCnt = 0xE0U; + break; + case 4U:/* SDCLK * 2^26 */ + timeoutCnt = 0xD0U; + break; + case 8U:/* SDCLK * 2^25 */ + timeoutCnt = 0xC0U; + break; + case 16U:/* SDCLK * 2^24 */ + timeoutCnt = 0xB0U; + break; + case 32U:/* SDCLK * 2^23 */ + timeoutCnt = 0xA0U; + break; + case 64U:/* SDCLK * 2^22 */ + timeoutCnt = 0x90U; + break; + case 128U:/* SDCLK * 2^21 */ + timeoutCnt = 0x80U; + break; + case 256U:/* SDCLK * 2^20 */ + timeoutCnt = 0x70U; + break; + case 512U:/* SDCLK * 2^19 */ + timeoutCnt = 0x60U; + break; + default: + /* nop */ + break; + } + + return timeoutCnt; +} diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_multiboot.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_multiboot.c new file mode 100644 index 0000000..4f01c82 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_multiboot.c @@ -0,0 +1,95 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC multi boot + ******************************************************************************/ +/****************************************************************************** + * @file emmc_multiboot.c + * - Version : 0.04 + * @brief data access interface to emmc. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.02.2022 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Modify SDHI access from DMA to PIO. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_def.h" +#include "emmc_multiboot.h" +#include "rom_api.h" +#include "types.h" + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +uint32_t emmc_check_result(uint32_t result); + +/* ********************************* CODE ********************************** */ + + +#if defined(__RH850__) +uint32_t emmc_trans_data(uint32_t next_bootPartition, uintptr_t sourceSct, uintptr_t targetAd, uint32_t sectorSize) +{ + EMMC_ERROR_CODE result; + uint32_t rtn_val = EMMC_DEV_ERR; + + /* Partition select */ + result = emmc_select_partition((EMMC_PARTITION_ID)next_bootPartition); + + if (result == EMMC_SUCCESS) { + result = emmc_read_sector((uint32_t *)targetAd, sourceSct, sectorSize, LOADIMAGE_FLAGS_DMA_ENABLE); + } + + /* EMMC_ERROR_CODE -> ROM_XX */ + rtn_val = emmc_check_result((uint32_t)result); + + return rtn_val; +} +#endif /* #if defined(__RH850__) */ +uint32_t emmc_check_result(uint32_t result) +{ + uint32_t ret = EMMC_DEV_ERR_FAULT_INJECTION; + + if (result == EMMC_SUCCESS) { + ret = EMMC_DEV_OK; + } else if (result == EMMC_ERR) { + ret = EMMC_DEV_ERR; + } else { /* other */ + ret = EMMC_DEV_ERR_HW; + } + + return ret; +} +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_read.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_read.c new file mode 100644 index 0000000..0145bd7 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_read.c @@ -0,0 +1,204 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC Read data access driver + ******************************************************************************/ +/****************************************************************************** + * @file emmc_read.c + * - Version : 0.04 + * @brief read data access function to emmc. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.02.2022 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Modify SDHI access from DMA to PIO. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "log.h" +#include + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +#define EMMC_RW_SECTOR_COUNT_MAX 0x0000ffffUL + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +static EMMC_ERROR_CODE emmc_multiple_block_read (uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode); + +static inline uint32_t get_min_value(uint32_t a, uint32_t b) +{ + uint32_t ret = a; + + if(b < a) + { + ret = b; + } + + return ret; +} + +/* ********************************* CODE ********************************** */ + +/** function of read sector + * + * This function always use block read. + * Single block read is not used. + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * . + * + * param[in,out] buff_address_virtual virtual address of read data buffer. + * param[in] sector_number data address for MMC device (sector number). + * param[in] count number of sector. + * param[in] transfermode Mode of data transfer, DMA or not DMA. + */ +EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, + uint32_t feature_flags) +{ + uint32_t trans_count; + uint32_t remain; + EMMC_ERROR_CODE result = EMMC_ERR; + HAL_MEMCARD_DATA_TRANSFER_MODE transfermode; + + /* parameter check */ + if (count == 0U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.mount != TRUE) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* DMA? */ + if ((feature_flags & LOADIMAGE_FLAGS_DMA_ENABLE) != 0U) { + transfermode = HAL_MEMCARD_DMA; + } else { + transfermode = HAL_MEMCARD_NOT_DMA; + } + + remain = count; + while (remain != 0U) { + trans_count = get_min_value(remain, EMMC_RW_SECTOR_COUNT_MAX); + result = emmc_multiple_block_read(buff_address_virtual, sector_number, trans_count, transfermode); + if (result != EMMC_SUCCESS) { + return result; + } + + buff_address_virtual += (EMMC_BLOCK_LENGTH_DW * trans_count); + sector_number += trans_count; + remain -= trans_count; + wdt_restart(); + } + + return EMMC_SUCCESS; +} + +/** multiple block read + * + * Multiple block read with pre-defined block count. + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * . + * + * param[in,out] buff_address_virtual virtual address of read data buffer. + * param[in] sector_number data address for MMC device (sector number). + * param[in] count number of sector. (0x1 - 0xffff) + * param[in] transfer_mode Mode of data transfer, DMA or not DMA. + */ +static EMMC_ERROR_CODE emmc_multiple_block_read(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* parameter check */ + if ((count > EMMC_RW_SECTOR_COUNT_MAX) || (count == 0U) + || ((transfer_mode != HAL_MEMCARD_DMA) && (transfer_mode != HAL_MEMCARD_NOT_DMA))) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* CMD23 */ + emmc_make_nontrans_cmd(CMD23_SET_BLOCK_COUNT, count); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + mem_write32(SD_SECCNT, count); + mem_write32(SD_STOP, 0x00000100U); + mem_write32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE)); /* SD_BUF Read/Write DMA Transfer enable */ + + /* CMD18 */ + emmc_make_trans_cmd(CMD18_READ_MULTIPLE_BLOCK, sector_number, buff_address_virtual, count << EMMC_SECTOR_SIZE_SHIFT, + HAL_MEMCARD_READ, transfer_mode); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; /* CMD18 error code */ + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + + /* ready status check */ + if ((mmc_drv_obj.r1_card_status & EMMC_R1_READY) == 0U) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR_CARD_BUSY; + } + + /* state check */ + if (mmc_drv_obj.current_state != EMMC_R1_STATE_TRAN) { + ERROR("%s:0x%08x\n",__func__,EMMC_ERR_CARD_STATE); + return EMMC_ERR_CARD_STATE; + } + + return EMMC_SUCCESS; +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_utility.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_utility.c new file mode 100644 index 0000000..11a66fe --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/emmc/emmc_utility.c @@ -0,0 +1,301 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : eMMC Utility + ******************************************************************************/ +/****************************************************************************** + * @file emmc_utility.c + * - Version : 0.04 + * @brief Analysis of SDHI data. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.02.2022 0.01 First Release + * : 22.10.2021 0.02 Remove unnecessary code + * : 22.12.2021 0.03 Support static analysis + * : 06.01.2022 0.04 Modify SDHI access from DMA to PIO. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +#define BUSY_SIGNAL (1U << 10U) + +static const uint32_t cmd_reg_hw[EMMC_CMD_MAX + 1U] = { + 0x00000000U, /* CMD0 */ + 0x00000701U, /* CMD1 */ + 0x00000002U, /* CMD2 */ + 0x00000003U, /* CMD3 */ + 0x00000004U, /* CMD4 */ + 0x00000505U, /* CMD5 */ + 0x00000406U, /* CMD6 */ + 0x00000007U, /* CMD7 */ + 0x00001C08U, /* CMD8 */ + 0x00000009U, /* CMD9 */ + 0x0000000AU, /* CMD10 */ + 0x00000000U, /* reserved */ + 0x0000000CU, /* CMD12 */ + 0x0000000DU, /* CMD13 */ + 0x00001C0EU, /* CMD14 */ + 0x0000000FU, /* CMD15 */ + 0x00000010U, /* CMD16 */ + 0x00000011U, /* CMD17 */ + 0x00007C12U, /* CMD18 */ + 0x00000C13U, /* CMD19 */ + 0x00000000U, + 0x00001C15U, /* CMD21 */ + 0x00000000U, + 0x00000017U, /* CMD23 */ + 0x00000018U, /* CMD24 */ + 0x00006C19U, /* CMD25 */ + 0x00000C1AU, /* CMD26 */ + 0x0000001BU, /* CMD27 */ + 0x0000001CU, /* CMD28 */ + 0x0000001DU, /* CMD29 */ + 0x0000001EU, /* CMD30 */ + 0x00001C1FU, /* CMD31 */ + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000423U, /* CMD35 */ + 0x00000424U, /* CMD36 */ + 0x00000000U, + 0x00000026U, /* CMD38 */ + 0x00000427U, /* CMD39 */ + 0x00000428U, /* CMD40 : send cmd */ + 0x00000000U, + 0x0000002AU, /* CMD42 */ + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000C31U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00007C35U, + 0x00006C36U, + 0x00000037U, /* CMD55 */ + 0x00000038U, /* CMD56 : Read */ + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U +}; +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +/** make non-transfer command data + * + * Response data buffer is automatically selected. + * + * - Pre-conditions:
+ * Clock to memory card IF is enabled. + * + * - Post-conditions:
+ * After this function is called, command can be executed. + * + * param[in] cmd command information. + * param[in] arg command argument + * return None. + */ +void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg) +{ + /* command information */ + mmc_drv_obj.cmd_info.cmd = cmd; + mmc_drv_obj.cmd_info.arg = arg; + mmc_drv_obj.cmd_info.dir = HAL_MEMCARD_READ; + mmc_drv_obj.cmd_info.hw = cmd_reg_hw[(uint32_t)cmd & HAL_MEMCARD_COMMAND_INDEX_MASK]; + + /* clear data transfer information */ + mmc_drv_obj.trans_size = 0U; + mmc_drv_obj.remain_size = 0U; + mmc_drv_obj.buff_address_virtual = NULL; + mmc_drv_obj.buff_address_physical = NULL; + + /* response information */ + mmc_drv_obj.response_length = 6U; + + switch ((HAL_MEMCARD_RESPONSE_TYPE)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK)) { + case HAL_MEMCARD_RESPONSE_NONE: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + mmc_drv_obj.response_length = 0U; + break; + case HAL_MEMCARD_RESPONSE_R1: + mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; + break; + case HAL_MEMCARD_RESPONSE_R1b: + mmc_drv_obj.cmd_info.hw |= BUSY_SIGNAL; /* bit10 = R1 busy bit */ + mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; + break; + case HAL_MEMCARD_RESPONSE_R2: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + mmc_drv_obj.response_length = 17U; + break; + case HAL_MEMCARD_RESPONSE_R3: + mmc_drv_obj.response = &mmc_drv_obj.r3_ocr; + break; + case HAL_MEMCARD_RESPONSE_R4: + mmc_drv_obj.response = &mmc_drv_obj.r4_resp; + break; + case HAL_MEMCARD_RESPONSE_R5: + mmc_drv_obj.response = &mmc_drv_obj.r5_resp; + break; + default: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + break; + } +} + +/** Making command information for data transfer command. + * + * - Pre-conditions:
+ * None. + * + * - Post-conditions:
+ * After this function is called, command can be executed. + * + * param[in] cmd command + * param[in] arg command argument + * param[in] buff_address_virtual Pointer to buffer where data is/will be stored. (virtual address) + * Client is responsible of allocation and deallocation of the buffer. + * param[in] len transfer length in bytes + * param[in] dir direction + * param[in] transfer_mode Mode of data transfer, DMA or not DMA. + * return None. + */ +void emmc_make_trans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual, /* virtual address */ +uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode) +{ + emmc_make_nontrans_cmd(cmd, arg); /* update common information */ + + /* for data transfer command */ + mmc_drv_obj.cmd_info.dir = dir; + mmc_drv_obj.buff_address_virtual = buff_address_virtual; + mmc_drv_obj.buff_address_physical = buff_address_virtual; + mmc_drv_obj.trans_size = len; + mmc_drv_obj.remain_size = len; + mmc_drv_obj.transfer_mode = transfer_mode; +} + +/** Send idle command. + * Function execute CMD0. + * + * - Pre-conditions:
+ * Clock to MMC I/F enabled. + * + * - Post-conditions:
+ * Card reset to idle or pre-idle state. + * + * param[in] arg CMD0 argument. + * return error code + */ +EMMC_ERROR_CODE emmc_send_idle_cmd(uint32_t arg) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t freq; + + /* initialize state */ + mmc_drv_obj.mount = FALSE; + mmc_drv_obj.selected = FALSE; + mmc_drv_obj.during_transfer = FALSE; + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.dma_error_flag = FALSE; + mmc_drv_obj.force_terminate = FALSE; + mmc_drv_obj.state_machine_blocking = FALSE; + + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; + mmc_drv_obj.max_freq = MMC_20MHZ; /* 20MHz */ + mmc_drv_obj.current_state = EMMC_R1_STATE_IDLE; + + /* CMD0 (MMC clock is current frequency. if Data transfer mode, 20MHz or higher.) */ + emmc_make_nontrans_cmd(CMD0_GO_IDLE_STATE, arg); /* CMD0 */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) { + return result; + } + + /* change MMC clock(400KHz) */ + freq = MMC_400KHZ; + result = emmc_set_request_mmc_clock(&freq); + if (result != EMMC_SUCCESS) { + return result; + } + + return EMMC_SUCCESS; +} + +/** get bit field data for 16bytes data(CSD register). + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param[in] data 16bytes data. + * param[in] top bit number(top). 128>top + * param[in] bottom bit number(bottom). (0<=bottom<=top) + * return bit field. + */ +uint32_t emmc_bit_field(const uint8_t *data, uint32_t top, uint32_t bottom) +{ + uint32_t value; + + uint32_t index_top = (uint32_t)(15U - (top >> 3U)); + uint32_t index_bottom = (uint32_t)(15U - (bottom >> 3U)); + + if (index_top == index_bottom) { + value = data[index_top]; + } else if ((index_top + 1U) == index_bottom) { + value = (uint32_t)(((uint32_t)data[index_top] << 8U) | data[index_bottom]); + } else if ((index_top + 2U) == index_bottom) { + value = (uint32_t)( + ((uint32_t)data[index_top] << 16U) | ((uint32_t)data[index_top + 1U] << 8U) | data[index_top + 2U]); + } else { + value = (uint32_t)( + ((uint32_t)data[index_top] << 24U) | ((uint32_t)data[index_top + 1U] << 16U) + | ((uint32_t)data[index_top + 2U] << 8U) | data[index_top + 3U]); + } + + value = ((value >> (bottom & 0x07U)) & ((1U << ((top - bottom) + 1U)) - 1U)); + + return value; +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/fcpr/fcpr.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/fcpr/fcpr.c new file mode 100644 index 0000000..8c96010 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/fcpr/fcpr.c @@ -0,0 +1,79 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : FCPR initialize + ******************************************************************************/ + /****************************************************************************** + * @file fcpr.c + * - Version : 0.04 + * @brief Initial setting process of FCPR. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.10.2022 0.01 First Release + * : 22.11.2022 0.02 Defenition Remap address + * : 14.06.2023 0.03 Update the setting process for FCPR. + * : 21.08.2023 0.04 Add support for V4M. + *****************************************************************************/ + +#include +#include +#include +#include +#include + +#define CPG_MSTPCR_FCPR (((uint32_t)1U) << 17U) + +void fcpr_init(void) +{ + /* Register FPCR base address to SIC REMAP14 for V4M. */ + /* There are no problems for V4H because same value had set for V4H in BootROM. */ + set_sicremap_fcpr(); + +#if (SET_FCPR_PARAM == FCPR_ENABLE) + uint32_t reg; + + /* Enables supply of the clock signal */ + reg = mem_read32(CPG_MSTPCR28D0); + /* If supply of clock to FCPR is stopped */ + if (FALSE != (CPG_MSTPCR_FCPR & reg)) + { + /* Supply of clock to FCPR is start */ + reg &= ~(CPG_MSTPCR_FCPR); + mem_write32(CPG_MSTPCR28D0, reg); + } + + /* Set value to FCPR_CMP_CTRL */ + mem_write32(FCPR_CMP_CTRL, COMPRESSION_ENABLE); + /* Set value to FCPR_CMP_SPACE */ + mem_write32(FCPR_CMP_SPACE, 0x00000000U); + /* Set value to FCPR_CMP_STADR */ + mem_write32(FCPR_CMP_STADR, COMPRESSION_START_ADDR); + /* Set value to FCPR_CMP_EDADR */ + mem_write32(FCPR_CMP_EDADR, COMPRESSION_END_ADDR); + +#endif /* SET_FCPR_PARAM == FCPR_ENABLE */ +} +/* End of function fcpr_init(void) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/i2c/i2c.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/i2c/i2c.c new file mode 100644 index 0000000..005642a --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/i2c/i2c.c @@ -0,0 +1,408 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : I2C driver + ******************************************************************************/ +/****************************************************************************** + * @file i2c.c + * - Version : 0.02 + * @brief I2C driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 16.11.2023 0.01 First Release + * : 24.06.2024 0.02 Remove pre-process branch of i2c3_read(). + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Setting value for PFC */ +#define IP0SR4_SDA3 (0xF0000000U) /* bit[31:28] */ +#define IP0SR4_SCL3 (0x0F000000U) /* bit[27:24] */ +#define GPSR4_SDA3 (0x00000080U) /* bit7 */ +#define GPSR4_SCL3 (0x00000040U) /* bit6 */ +#define MODSEL4_SDA3 (0x00000080U) /* bit7 */ +#define MODSEL4_SCL3 (0x00000040U) /* bit6 */ +#define PUEN4_SDA3 (0x00000080U) /* bit7 */ +#define PUEN4_SCL3 (0x00000040U) /* bit6 */ + +static void i2c3_init_pin_function(void); + +void i2c3_init(void) +{ + /* + * Module Standby setting for I2C3 is not nessesary + * because H/W initial value is 'Enables supply of the clock signal'. + */ + + /* PFC setting for I2C3. */ + i2c3_init_pin_function(); + + /* CDFD=0, HLSE=0, SME=0 */ + mem_write32((uintptr_t)I2C3_ICCCR2, 0x00000000U); + /* SCGD=H'3, CDF=H'6 */ + mem_write32((uintptr_t)I2C3_ICCCR, (SET_SCGD | SET_CDF)); + + mem_write32((uintptr_t)I2C3_ICSCR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICSSR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICSIER, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICSAR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE)); + mem_write32((uintptr_t)I2C3_ICMSR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMIER, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMAR, 0x00000000U); +} +/* End of function i2c3_init(void) */ + +static void i2c3_init_pin_function(void) +{ + uint32_t data; + + /* SDA3, SCL3 -> 0 */ + data = mem_read32((uintptr_t)PFC_IP0SR4_RW); + data &= ~(IP0SR4_SDA3 | IP0SR4_SCL3); + pfc_reg_write(PFC_IP0SR4_RW, data); + + /* SDA3, SCL3 -> 1 */ + data = mem_read32((uintptr_t)PFC_GPSR4_RW); + data |= (GPSR4_SDA3 | GPSR4_SCL3); + pfc_reg_write(PFC_GPSR4_RW, data); + + /* Select SDA3 and SCL3 to I2C mode */ + data = mem_read32((uintptr_t)PFC_MODSEL4_RW); + data |= (MODSEL4_SDA3 | MODSEL4_SCL3); + pfc_reg_write(PFC_MODSEL4_RW, data); + + /* SDA3, SCL3 -> 0 */ + data = mem_read32((uintptr_t)PFC_PUEN4_RW); + data &= ~(PUEN4_SDA3 | PUEN4_SCL3); + pfc_reg_write(PFC_PUEN4_RW, data); +} +/* End of function i2c3_init_pin_function(void) */ + +void i2c3_write(uint32_t slaveAdd, uint32_t regAdd, uint32_t setData) +{ + uint32_t data; + uint32_t err_count = 0U; + uint32_t status; + + while(true) + { + data = mem_read32((uintptr_t)I2C3_ICMCR); + data &= (FLAG_FSCL | FLAG_FSDA); + if(data == FLAG_FSCL) + { + break; + } + } + + status = I2C_NG; + while(I2C_NG == status) + { + /* Set MDBS and MIE (initialize) */ + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE)); + /* Set slave address */ + slaveAdd &= ~FLG_RW; /* write mode */ + mem_write32((uintptr_t)I2C3_ICMAR, slaveAdd); + /* Set register address */ + mem_write32((uintptr_t)I2C3_ICTXD, regAdd); + + while(true) + { + data = mem_read32((uintptr_t)I2C3_ICMCR); + data &= (FLAG_FSCL | FLAG_FSDA); + if(data == FLAG_FSCL) + { + break; + } + } + + /* Set MDBS, MIE and ESG */ + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_ESG)); /* start condition */ + + /* MDE(master data empty) & MAT(master address transmitted */ + status = i2c3_err_check(FLAG_MDE, FLAG_MAT, (FLAG_MNR|FLAG_MAL)); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("1:I2C data write error\n"); + panic; + } + } + } + + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE)); + + status = I2C_NG; + while(I2C_NG == status) + { + /* MDE and MAT clear */ + data = mem_read32((uintptr_t)I2C3_ICMSR); + data &= (FLAG_MNR | FLAG_MAL | FLAG_MST | FLAG_MDT | FLAG_MDR); + mem_write32((uintptr_t)I2C3_ICMSR, data); + /* MDE(master data empty) & MDT(master data transmitted) */ + status = i2c3_err_check(FLAG_MDE, FLAG_MDT, FLAG_MNR); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("2:I2C data write error\n"); + panic; + } + } + } + + status = I2C_NG; + while(I2C_NG == status) + { + /* send voltage */ + mem_write32((uintptr_t)I2C3_ICTXD, setData); + /* MDE and MAT clear */ + data = mem_read32((uintptr_t)I2C3_ICMSR); + data &= (FLAG_MNR | FLAG_MAL | FLAG_MST | FLAG_MDR | FLAG_MAT); + mem_write32((uintptr_t)I2C3_ICMSR, data); + /* MDE(master data empty) & MDT(master data transmitted) */ + status = i2c3_err_check(FLAG_MDE, FLAG_MDT, FLAG_MNR); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("3:I2C data write error\n"); + panic; + } + } + } + + /* Set MDBS, MIE and FSB */ + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_FSB)); /* stop condition */ + mem_write32((uintptr_t)I2C3_ICMSR, 0x00000000U); /* MST(master stop transmitted) clear */ + + while(true) + { + data = mem_read32((uintptr_t)I2C3_ICMSR); + if((data & FLAG_MST) != 0U) /* MST(master stop transmitted) */ + { + break; + } + } + + mem_write32((uintptr_t)I2C3_ICMSR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE)); + +} +/* End of function i2c3_write(uint32_t slaveAdd, uint32_t regAdd, uint32_t setData) */ + +void i2c3_read(uint32_t slaveAdd, uint32_t regAdd, uint32_t *revData) +{ + uint32_t data; + uint32_t err_count = 0; + uint32_t status; + + while(true) + { + data = mem_read32((uintptr_t)I2C3_ICMCR); + data &= (FLAG_FSCL | FLAG_FSDA); + if(data == FLAG_FSCL) + { + break; + } + } + + status = I2C_NG; + while(I2C_NG == status) + { + /* Set MDBS and MIE (initialize) */ + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE)); + /* Set slave address */ + slaveAdd &= ~FLG_RW; /* write mode */ + mem_write32((uintptr_t)I2C3_ICMAR, slaveAdd); + /* Set register address */ + mem_write32((uintptr_t)I2C3_ICTXD, regAdd); + + while(true) + { + data = mem_read32((uintptr_t)I2C3_ICMCR); + data &= (FLAG_FSCL | FLAG_FSDA); + if(data == FLAG_FSCL) + { + break; + } + } + + /* Set MDBS, MIE and ESG */ + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_ESG)); /* start condition */ + + /* MDE(master data empty) & MAT(master address transmitted */ + status = i2c3_err_check(FLAG_MDE, FLAG_MAT, (FLAG_MNR|FLAG_MAL)); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("1:I2C data read error\n"); + panic; + } + } + } + + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE)); + + status = I2C_NG; + while(I2C_NG == status) + { + /* MDE and MAT clear */ + data = mem_read32((uintptr_t)I2C3_ICMSR); + data &= 0x000000F6U; + mem_write32((uintptr_t)I2C3_ICMSR, data); + /* MDE(master data empty) */ + status = i2c3_err_check(FLAG_MDE, FLAG_NONE, FLAG_MNR); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("2:I2C data read error\n"); + panic; + } + } + } + + status = I2C_NG; + while(I2C_NG == status) + { + /* Set slave address */ + slaveAdd |= FLG_RW; /* read mode */ + mem_write32((uintptr_t)I2C3_ICMAR, slaveAdd); + /* Set MDBS, MIE and ESG */ + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_ESG)); /* start condition */ + mem_write32((uintptr_t)I2C3_ICMSR, 0x00000000U); + + /* MDR(master data recieved) & MAT(master address transmitted) */ + status = i2c3_err_check(FLAG_MDR, FLAG_MAT, (FLAG_MNR|FLAG_MAL)); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("3:I2C data read error\n"); + panic; + } + } + } + + status = I2C_NG; + while(I2C_NG == status) + { + /* Set MDBS, MIE and FSB */ + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE | FLAG_FSB)); /* stop condition */ + /* MDE and MAT clear */ + data = mem_read32((uintptr_t)I2C3_ICMSR); + data &= 0x000000FCU; + mem_write32((uintptr_t)I2C3_ICMSR, data); + status = i2c3_err_check(FLAG_MDR, FLAG_NONE, FLAG_MNR); + if(I2C_NG == status) + { + err_count++; + if(err_count > ERR_MAX) + { + ERROR("4:I2C data read error\n"); + panic; + } + } + if(I2C_OK == status) + { + *revData = mem_read32((uintptr_t)I2C3_ICRXD) & 0x000000FFU; + } + mem_write32((uintptr_t)I2C3_ICMSR, 0x00000000U); /* MST(master stop transmitted) clear */ + } + + while(true) + { + data = mem_read32((uintptr_t)I2C3_ICMSR); + if((data & FLAG_MST) != 0U) + { + break; + } + } + + mem_write32((uintptr_t)I2C3_ICMSR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMCR, (FLAG_MDBS | FLAG_MIE)); +} +/* End of function i2c3_read(uint32_t slaveAdd, uint32_t regAdd, uint32_t *revData) */ + +uint32_t i2c3_err_check(uint32_t first, uint32_t second, uint32_t error) +{ + uint32_t data; + uint32_t status = I2C_OK; + + while(true) + { + data = mem_read32((uintptr_t)I2C3_ICMSR); + if((data & first) != 0U) + { + if((second == FLAG_NONE) || ((data & second) != 0U)) + { + status = I2C_OK; + break; + } + } + if((data & error) != 0U) + { + mem_write32((uintptr_t)I2C3_ICMSR, ~error); + status = I2C_NG; + break; + } + } + return status; +} +/* End of function i2c3_err_check(uint32_t first, uint32_t second, uint32_t error) */ + +void i2c3_release(void) +{ + mem_write32((uintptr_t)I2C3_ICCCR2, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICCCR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICSCR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICSSR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICSIER, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICSAR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMCR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMSR, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMIER, 0x00000000U); + mem_write32((uintptr_t)I2C3_ICMAR, 0x00000000U); +} +/* End of function i2c3_release(void) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ip_control.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ip_control.c new file mode 100644 index 0000000..9e20666 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/ip_control.c @@ -0,0 +1,115 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : IP's control function + ******************************************************************************/ +/****************************************************************************** + * @file ip_control.c + * - Version : 0.08 + * @brief Initial setting controller. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 30.09.2021 0.02 Support of eMMC boot. + * : 15.10.2021 0.03 modify include of flash /eMMC. + * : 03.12.2021 0.04 CA IPL boot support (workaround) + * : 06.01.2022 0.05 Add exception handling for ICUMX_WDTA. + * : 02.02.2022 0.06 Add MFIS Lock/Unlock. + * : 23.05.2022 0.07 Integration of S4 and V4H + * : 23.08.2023 0.08 Add support for V4M. + * : 13.10.2023 0.09 Add calling of sysc_c4_power_on function. + *****************************************************************************/ + +#include +#include +#include +#if (RCAR_SA9_TYPE == FLASH_BOOT) +#include +#include +#include +#elif (RCAR_SA9_TYPE == EMMC_BOOT) +#include +#else +/* no process */ +#endif +#include +#include +#include + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#include +#endif + +#if (RCAR_LSI == RCAR_V4M) +#include +#endif + +void ip_init(void) +{ + scif_init(); + set_vect_table(); + wdt_init(); + cpg_init(); +#if (RCAR_SA9_TYPE == FLASH_BOOT) + dma_init(); + rpc_init(); + mfis_init(); + #if (CA_LOAD_TYPE == CA_IPL) + emmc_initialize(); /* workaround */ + #endif /* (CA_LOAD_TYPE == CA_IPL) */ +#elif (RCAR_SA9_TYPE == EMMC_BOOT) /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + emmc_initialize(); +#else /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + /* No process */ +#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + fcpr_init(); +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +#if (RCAR_LSI == RCAR_V4M) + /* + * For accessing Region ID registers by ICUMX, + * and starting Cortex-A76 by CR52 2nd IPL. + */ + sysc_c4_power_on(); +#endif /* RCAR_LSI == RCAR_V4M */ +} +/* End of function ip_init(void) */ + +void ip_release(void) +{ +#if (RCAR_SA9_TYPE == FLASH_BOOT) + rpc_release(); + dma_release(); +#elif (RCAR_SA9_TYPE == EMMC_BOOT) + emmc_terminate(); +#else + /* No process */ +#endif + wdt_restart(); +} +/* End of function ip_release(void) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/mfis/mfis.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/mfis/mfis.c new file mode 100644 index 0000000..9f133cc --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/mfis/mfis.c @@ -0,0 +1,82 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MFIS driver + ******************************************************************************/ +/****************************************************************************** + * @file mfis.c + * - Version : 0.01 + * @brief Initial setting process of MFIS. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.04.2022 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include + +#define MFIS_CODE_VALID (0xACCE0000U) +#define MFISWPCNTR_ENABLE (0U) /* 1' b0: Enable write protection */ + +#define MFISLCKR_LCK_BIT ((uint32_t)1U << 0U) +#define MFISLCKR_UNLOCK (0U) + +void mfis_init(void) +{ + /* Write Protection Control Register */ + /* Enable write protection setting */ + mem_write32(MFIS_WPCNTR, (uint32_t)(MFIS_CODE_VALID + MFISWPCNTR_ENABLE)); + + /* IPL considers the situation that mutex of MFIS is not released, release it. */ + mfis_unlock(); +} +/* End of function mfis_init(void) */ + +void mfis_lock(void) +{ + /* MFIS Lock Register [j] (MFISLCKR[j]) */ + /* bit in LCK != 0? */ + while((mem_read32(MFIS_LCKR) & MFISLCKR_LCK_BIT) != MFISLCKR_UNLOCK) + { + micro_wait(10U); /* 10us */ + } + /* this bit is automatically set to "1" */ +} +/* End of function mfis_lock(void) */ + +void mfis_unlock(void) +{ + /* Write Access Control Register */ + /* MFISLCKR[j] Register address setting */ + mem_write32(MFIS_WACNTR, (uint32_t)(MFIS_CODE_VALID + MFISLCKR_ADDRESS)); + + /* MFIS Lock Register [j] (MFISLCKR[j]) */ + mem_write32(MFIS_LCKR, (uint32_t)MFISLCKR_UNLOCK); +} +/* End of function mfis_unlock(void) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/qos/qos.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/qos/qos.c new file mode 100644 index 0000000..fd0674d --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/qos/qos.c @@ -0,0 +1,413 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : QoS initialize function + ******************************************************************************/ +/****************************************************************************** + * @file qos.c + * - Version : 0.04 + * @brief Initial setting process of QoS. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 23.05.2022 0.02 Integration of S4 and V4H + * Update QoS setting rev.0.02 (for S4) + * Update QoS setting rev.0.03 (for V4H) + * : 20.01.2023 0.03 Add DBSC W/A 1,2,3 (OTLINT-5579) + * : 21.08.2023 0.04 Add support for V4M. + *****************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include +#include +#include +#else +#include +#endif +#include +#include +#include + +#if (RCAR_LSI == RCAR_S4) +#define RCAR_QOS_VERSION "base_v6.1" +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define RCAR_QOS_VERSION "base_v6.1" +#endif /* RCAR_LSI == RCAR_S4 */ + +#define RCAR_DRAM_SPLIT_DISABLE (0U) +#define RCAR_DRAM_SPLIT_ENABLE (1U) +#define RCAR_REWT_TRAINING_DISABLE (0U) +#define RCAR_REWT_TRAINING_ENABLE (1U) + +#if defined(__RH850G3K__) +#define AXMM_BASE (BASE_AXMM_ADDR) +#else +#define AXMM_BASE (0xE6780000U) +#endif +#define AXMM_MMCR (AXMM_BASE + 0x4300U) +#define AXMM_ADSPLCR0 (AXMM_BASE + 0x4008U) +#define AXMM_ADSPLCR1 (AXMM_BASE + 0x400CU) +#define AXMM_ADSPLCR2 (AXMM_BASE + 0x4010U) +#define AXMM_ADSPLCR3 (AXMM_BASE + 0x4014U) + + +#if (RCAR_LSI == RCAR_S4) +#if defined(__RH850G3K__) +#define DBSC_BASE (BASE_DBSC_ADDR) +#else +#define DBSC_BASE (0xE6790000U) +#endif + +#define DBSC_CH_NUM (1U) /* Number of DBSCx */ +#define DBSC_A_CH_OFFSET (0U) /* 1ch only (for S4)*/ +#define DBSC_D_CH_OFFSET (0U) /* 1ch only (for S4)*/ + +#define DBSC_SYSCNT0 (DBSC_BASE + 0x0100U) +#define DBSC_SYSCNT0A (DBSC_BASE + 0x0108U) +#define DBSC_DBBUS0CNF2 (DBSC_BASE + 0x0808U) +#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) +#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) +#define DBSC_DBCAMDIS (DBSC_BASE + 0x09FCU) +#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) +#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) +#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) +#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) +#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) +#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) +#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) +#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) +#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) +#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) +#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) +#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) +#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) +#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) +#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) +#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) +#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) +#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) +#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) +#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) +#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) +#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) +#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) +#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) +#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) +#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if defined(__RH850G3K__) +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) +#define DBSC_A_BASE (BASE_DBSC_ADDR) +#else +#define DBSC_D_BASE (0xE67A4000U) +#define DBSC_A_BASE (0xE6790000U) +#endif + +#define DBSC_CH_NUM (2U) /* ch number of DBSCx */ +#define DBSC_A_CH_OFFSET (0x8000U) +#define DBSC_D_CH_OFFSET (0x4000U) + +#define DBSC_SYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DBSC_SYSCNT0A (DBSC_A_BASE + 0x0100U) +#define DBSC_DBBUS0CNF2 (DBSC_A_BASE + 0x0808U) +#define DBSC_DBCAM0CNF1 (DBSC_A_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_A_BASE + 0x0908U) +#define DBSC_DBCAMDIS (DBSC_A_BASE + 0x09FCU) +#define DBSC_DBCAM0CNF3 (DBSC_A_BASE + 0x090CU) +#define DBSC_DBSCHCNT0 (DBSC_A_BASE + 0x1000U) +#define DBSC_DBSCHSZ0 (DBSC_A_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_A_BASE + 0x1020U) +#define DBSC_DBSCHQOS_0_0 (DBSC_A_BASE + 0x1100U) +#define DBSC_DBSCHQOS_0_1 (DBSC_A_BASE + 0x1104U) +#define DBSC_DBSCHQOS_0_2 (DBSC_A_BASE + 0x1108U) +#define DBSC_DBSCHQOS_0_3 (DBSC_A_BASE + 0x110CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_A_BASE + 0x1140U) +#define DBSC_DBSCHQOS_4_1 (DBSC_A_BASE + 0x1144U) +#define DBSC_DBSCHQOS_4_2 (DBSC_A_BASE + 0x1148U) +#define DBSC_DBSCHQOS_4_3 (DBSC_A_BASE + 0x114CU) +#define DBSC_DBSCHQOS_9_0 (DBSC_A_BASE + 0x1190U) +#define DBSC_DBSCHQOS_9_1 (DBSC_A_BASE + 0x1194U) +#define DBSC_DBSCHQOS_9_2 (DBSC_A_BASE + 0x1198U) +#define DBSC_DBSCHQOS_9_3 (DBSC_A_BASE + 0x119CU) +#define DBSC_DBSCHQOS_12_0 (DBSC_A_BASE + 0x11C0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_A_BASE + 0x11C4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_A_BASE + 0x11C8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_A_BASE + 0x11CCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_A_BASE + 0x11D0U) +#define DBSC_DBSCHQOS_13_1 (DBSC_A_BASE + 0x11D4U) +#define DBSC_DBSCHQOS_13_2 (DBSC_A_BASE + 0x11D8U) +#define DBSC_DBSCHQOS_13_3 (DBSC_A_BASE + 0x11DCU) +#define DBSC_DBSCHQOS_14_0 (DBSC_A_BASE + 0x11E0U) +#define DBSC_DBSCHQOS_14_1 (DBSC_A_BASE + 0x11E4U) +#define DBSC_DBSCHQOS_14_2 (DBSC_A_BASE + 0x11E8U) +#define DBSC_DBSCHQOS_14_3 (DBSC_A_BASE + 0x11ECU) +#define DBSC_DBSCHQOS_15_0 (DBSC_A_BASE + 0x11F0U) +#define DBSC_DBSCHQOS_15_1 (DBSC_A_BASE + 0x11F4U) +#define DBSC_DBSCHQOS_15_2 (DBSC_A_BASE + 0x11F8U) +#define DBSC_DBSCHQOS_15_3 (DBSC_A_BASE + 0x11FCU) +#define DBSC_SCFCTST2 (DBSC_A_BASE + 0x1048U) +#endif /* RCAR_LSI == RCAR_S4 */ + +#if defined(__RH850G3K__) +#define QOS_BASE (BASE_QOS_ADDR) +#else +#define QOS_BASE (0xE67E0000U) +#endif +#define QOS_FIX_QOS_BANK0 (QOS_BASE + 0x00000000U) +#define QOS_FIX_QOS_BANK1 (QOS_BASE + 0x00001000U) +#define QOS_BE_QOS_BANK0 (QOS_BASE + 0x00002000U) +#define QOS_BE_QOS_BANK1 (QOS_BASE + 0x00003000U) +#define QOS_SL_INIT (QOS_BASE + 0x00008000U) +#define QOS_REF_ARS (QOS_BASE + 0x00008004U) +#define QOS_STATQC (QOS_BASE + 0x00008008U) +#define QOS_REF_ENBL (QOS_BASE + 0x00008044U) +#define QOS_BWG (QOS_BASE + 0x0000804CU) +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE +#define QOSWT_FIX_QOS_BANK0 (QOS_BASE + 0x00000800U) +#define QOSWT_FIX_QOS_BANK1 (QOS_BASE + 0x00001800U) +#define QOSWT_BE_QOS_BANK0 (QOS_BASE + 0x00002800U) +#define QOSWT_BE_QOS_BANK1 (QOS_BASE + 0x00003800U) +#define QOSWT_WTEN (QOS_BASE + 0x00008030U) +#define QOSWT_WTREF (QOS_BASE + 0x00008034U) +#define QOSWT_WTSET0 (QOS_BASE + 0x00008038U) +#define QOSWT_WTSET1 (QOS_BASE + 0x0000803CU) +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + +#define QOS_RAS (QOS_BASE + 0x00010000U) +#define QOS_RAEN (QOS_BASE + 0x00010018U) +#define QOS_DANN_LOW (QOS_BASE + 0x00010030U) +#define QOS_DANN_HIGH (QOS_BASE + 0x00010034U) +#define QOS_DANT (QOS_BASE + 0x00010038U) +#define QOS_EMS_LOW (QOS_BASE + 0x00010040U) +#define QOS_EMS_HIGH (QOS_BASE + 0x00010044U) +#define QOS_FSS (QOS_BASE + 0x00010048U) +#define QOS_INSFC (QOS_BASE + 0x00010050U) +#define QOS_EARLYR (QOS_BASE + 0x00010060U) +#define QOS_RACNT0 (QOS_BASE + 0x00010080U) +#define QOS_STATGEN0 (QOS_BASE + 0x00010088U) + +#define CCI_BASE (BASE_CCI_ADDR) +#define CCIQOS00 (CCI_BASE + 0xC020U) +#define CCIQOS01 (CCI_BASE + 0xC024U) +#define CCIQOS10 (CCI_BASE + 0xD000U) +#define CCIQOS11 (CCI_BASE + 0xD004U) +#if (RCAR_LSI == RCAR_S4) +#define CCIQOS12 (CCI_BASE + 0xD008U) +#define CCIQOS13 (CCI_BASE + 0xD00CU) +#endif + +static void dbsc_setting(void) +{ + for(uint32_t loop = 0; loop < DBSC_CH_NUM; loop++) + { + /* DBSC CAM, Scheduling Setting */ + mem_write32((DBSC_SYSCNT0 + (DBSC_D_CH_OFFSET * loop)), 0x00001234U); + mem_write32((DBSC_SYSCNT0A + (DBSC_A_CH_OFFSET * loop)), 0x00001234U); + mem_write32((DBSC_DBCAM0CNF1 + (DBSC_A_CH_OFFSET * loop)), 0x00104214U); /* dbcam0cnf1 */ + mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U); /* dbcam0cnf2 */ + mem_write32((DBSC_DBCAM0CNF3 + (DBSC_A_CH_OFFSET * loop)), 0x00000003U); /* dbcam0cnf3 */ + +#if (RCAR_LSI == RCAR_S4) + #if (WA_OTLINT5579 == 1 && ECC_ENABLE == 1) + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000002U); /* OTLINT-5579: V4H DBSC W/A-1,2 */ + #else + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000000U); + #endif +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + #if (WA_OTLINT5579 == 1 && ECC_ENABLE == 1) + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000013U); /* OTLINT-5579: V4H DBSC W/A-1,2,3 */ + #elif (WA_OTLINT5579 == 1 && ECC_ENABLE == 0) + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000011U); /* OTLINT-5579: V4H DBSC W/A-3 */ + #else + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); + #endif +#endif + + mem_write32((DBSC_DBSCHCNT0 + (DBSC_A_CH_OFFSET * loop)), 0x000F0037U); /* dbschcnt0 */ + mem_write32((DBSC_DBSCHSZ0 + (DBSC_A_CH_OFFSET * loop)), 0x00000001U); /* dbschsz0 */ + mem_write32((DBSC_DBSCHRW0 + (DBSC_A_CH_OFFSET * loop)), 0xF7311111U); /* dbschrw0 */ + mem_write32((DBSC_SCFCTST2 + (DBSC_A_CH_OFFSET * loop)), 0x111F1FFFU); + +#if (((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) && WA_OTLINT5579 == 1) + mem_write32((DBSC_DBBUS0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x00000007U); /* OTLINT-5579: V4H DBSC WA3 */ +#else + mem_write32((DBSC_DBBUS0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x00000003U); /* S4, V4H w/o DBSC WA3 */ +#endif + + /* DBSC QoS Setting */ + mem_write32((DBSC_DBSCHQOS_0_0 + (DBSC_A_CH_OFFSET * loop)), 0x0000FFFFU); + mem_write32((DBSC_DBSCHQOS_0_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000480U); + mem_write32((DBSC_DBSCHQOS_0_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_0_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_4_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000600U); + mem_write32((DBSC_DBSCHQOS_4_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000480U); + mem_write32((DBSC_DBSCHQOS_4_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_4_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_9_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000400U); + mem_write32((DBSC_DBSCHQOS_9_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_9_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000200U); + mem_write32((DBSC_DBSCHQOS_9_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); + mem_write32((DBSC_DBSCHQOS_12_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000040U); + mem_write32((DBSC_DBSCHQOS_12_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000030U); + mem_write32((DBSC_DBSCHQOS_12_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000020U); + mem_write32((DBSC_DBSCHQOS_12_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); + mem_write32((DBSC_DBSCHQOS_13_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_13_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000240U); + mem_write32((DBSC_DBSCHQOS_13_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_13_3 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U); + mem_write32((DBSC_DBSCHQOS_14_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000200U); + mem_write32((DBSC_DBSCHQOS_14_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_14_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); + mem_write32((DBSC_DBSCHQOS_14_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000080U); + mem_write32((DBSC_DBSCHQOS_15_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); + mem_write32((DBSC_DBSCHQOS_15_1 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U); + mem_write32((DBSC_DBSCHQOS_15_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000080U); + mem_write32((DBSC_DBSCHQOS_15_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000040U); + + mem_write32((DBSC_SYSCNT0 + (DBSC_D_CH_OFFSET * loop)), 0x00000000U); + mem_write32((DBSC_SYSCNT0A + (DBSC_A_CH_OFFSET * loop)), 0x00000000U); + } +} +/* End of function dbsc_setting(void) */ + +void qos_init(void) +{ + uint32_t i; + + /* Setting the register of DBSC4 for QoS initialize */ + dbsc_setting(); + + NOTICE("QoS setting(%s)\n", RCAR_QOS_VERSION); + NOTICE("DRAM refresh interval 1.91 usec\n"); + +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE + NOTICE("Periodic Write DQ Training\n"); +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + +#if (RCAR_LSI == RCAR_S4) + /* Resource Alloc setting */ + mem_write32(QOS_RAS, 0x00000028U); + mem_write32(QOS_DANN_LOW, 0x02020201U); + mem_write32(QOS_DANN_HIGH, 0x04040200U); + mem_write32(QOS_DANT, 0x00181004U); + mem_write32(QOS_EMS_LOW, 0x00000000U); + mem_write32(QOS_EMS_HIGH, 0x00000000U); + mem_write32(QOS_FSS, 0x0000000AU); + mem_write32(QOS_INSFC, 0x030F0001U); + mem_write32(QOS_EARLYR, 0x00000000U); + mem_write32(QOS_RACNT0, 0x00050003U); + mem_write32(QOS_STATGEN0, 0x00000000U); + + /* QoS MSTAT setting */ + mem_write32(QOS_SL_INIT, 0x00050100U); + mem_write32(QOS_REF_ARS, 0x00FB0000U); + mem_write32(QOS_REF_ENBL, 0x00000012U); + mem_write32(QOS_BWG, 0x00000002U); + mem_write32(AXMM_MMCR, 0x00010000U); + + mem_write32(CCIQOS00, 0x08000000); + mem_write32(CCIQOS01, 0x08000000); + mem_write32(CCIQOS10, 0x00000001); + mem_write32(CCIQOS11, 0x00000001); + mem_write32(CCIQOS12, 0x00000001); + mem_write32(CCIQOS13, 0x00000001); +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_ENABLE) + /* Address Split 2ch */ + mem_write32(AXMM_ADSPLCR0, 0x00000000U); + mem_write32(AXMM_ADSPLCR1, 0x00FF1B0CU); + mem_write32(AXMM_ADSPLCR2, 0x00000000U); + mem_write32(AXMM_ADSPLCR3, 0x00000000U); +#endif + + mem_write32(CCIQOS00, 0x08000000); + mem_write32(CCIQOS01, 0x08000000); + mem_write32(CCIQOS10, 0x00000000); + mem_write32(CCIQOS11, 0x00000000); + + /* Resource Alloc setting */ + mem_write32(QOS_RAS, 0x00000040U); + mem_write32(QOS_DANN_LOW, 0x02020201U); + mem_write32(QOS_DANN_HIGH, 0x04040200U); + mem_write32(QOS_DANT, 0x00181008U); + mem_write32(QOS_EMS_LOW, 0x00000000U); + mem_write32(QOS_EMS_HIGH, 0x00000000U); + mem_write32(QOS_FSS, 0x0000000AU); + mem_write32(QOS_INSFC, 0x030F0001U); + mem_write32(QOS_EARLYR, 0x00000000U); + mem_write32(QOS_RACNT0, 0x00050003U); + mem_write32(QOS_STATGEN0, 0x00000000U); + + /* QoS MSTAT setting */ + mem_write32(QOS_SL_INIT, 0x00050100U); + mem_write32(QOS_REF_ARS, 0x00FB0000U); + mem_write32(QOS_REF_ENBL, 0x00000012U); + mem_write32(QOS_BWG, 0x00000004U); + #if (((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) && WA_OTLINT5579 == 1) + mem_write32(AXMM_MMCR, 0x00000000U); /* OTLINT-5579: V4H DBSC WA3 */ + #else + mem_write32(AXMM_MMCR, 0x00010000U); + #endif + +#endif /* RCAR_LSI == RCAR_S4 */ + + for (i = 0U; i < QOS_TBL_MAX; i++) + { + mem_write64((QOS_FIX_QOS_BANK0 + (i * 8U)), g_qosbw_tbl[i].fix); + mem_write64((QOS_FIX_QOS_BANK1 + (i * 8U)), g_qosbw_tbl[i].fix); + mem_write64((QOS_BE_QOS_BANK0 + (i * 8U)), g_qosbw_tbl[i].be); + mem_write64((QOS_BE_QOS_BANK1 + (i * 8U)), g_qosbw_tbl[i].be); + } + +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE + for (i = 0U; i < QOS_TBL_MAX; i++) + { + mem_write64((QOSWT_FIX_QOS_BANK0 + (i * 8U)), g_qoswt_tbl[i].fix); + mem_write64((QOSWT_FIX_QOS_BANK1 + (i * 8U)), g_qoswt_tbl[i].fix); + mem_write64((QOSWT_BE_QOS_BANK0 + (i * 8U)), g_qoswt_tbl[i].be); + mem_write64((QOSWT_BE_QOS_BANK1 + (i * 8U)), g_qoswt_tbl[i].be); + } +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + + /* QoS SRAM setting */ + mem_write32(QOS_RAEN, 0x00000001U); +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE + mem_write32(QOSWT_WTREF, 0x02080208U); + mem_write32(QOSWT_WTSET0, 0x14A6050BU); + mem_write32(QOSWT_WTSET1, 0x14A6050BU); + mem_write32(QOSWT_WTEN, 0x00000001U); +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + mem_write32(QOS_STATQC, 0x00000101U); +} +/* End of function qos_init(void) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/rpc/rpc.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/rpc/rpc.c new file mode 100644 index 0000000..a49ac40 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/rpc/rpc.c @@ -0,0 +1,603 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RPC driver + ******************************************************************************/ +/****************************************************************************** + * @file rpc.c + * - Version : 0.08 + * @brief Initial setting process of RPC. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Add rpc_release function. + * : 27.07.2022 0.03 Add QSPI Flash vendor ID check and QSPI Flash + * : command initialization. + * : 22.08.2022 0.04 Add DDR mode for QSPI Flash. + * : 21.09.2022 0.05 Fix comparison of test data + * : in adjust_strobe_timing function. + * : 12.01.2023 0.06 Add PFC setting to qspi_ddr_transfer_mode() + * : function. + * : 04.04.2023 0.07 Removed stdio.h. + * : 17.06.2024 0.08 Fix PUEN register setting when QSPI DDR mode. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RPC_PHYCNT_CAL ((uint32_t)1U << 31U) +#define RPC_PHYCNT_DDRCAL ((uint32_t)1U << 19U) +#define RPC_PHYCNT_PHYMEM_SPI_DDR ((uint32_t)1U << 0U) +#define RPC_PHYCNT_HS (0x00040000U) +#define RPC_PHYCNT_WBUF2 (0x00000010U) +#define RPC_PHYCNT_WBUF (0x00000004U) +#define RPC_PHYCNT_PHYMEM_MASK (0x00000003U) +#define RPC_DRCR_RCF ((uint32_t)1U << 9U) +#define RPC_DRCR_SSLN_NEGATE (0x01000000U) +#define RPC_DRCR_RBE_RBURST_MASK (0x001F0000U) +#define RPC_DRCR_RBE_RBURST_1DATA (0x00000000U) /* Smallest data unit (8byte) */ +#define RPC_DRCR_RBE_RBURST_32DATA (0x001F0000U) /* biggest data unit (256byte) */ +#define RPC_DRCR_RBE_ENABLE (0x00000100U) +#define RPC_DRCMR_CMD_SHIFT (16U) +#define RPC_DRCMR_CMD_MASK ((uint32_t)0xFFU << RPC_DRCMR_CMD_SHIFT) +#define RPC_DRCMR_OCMD_MASK ((uint32_t)0xFFU << 0U) +#define RPC_DRCMR_HW_INIT (0x00030000U) +#define RPC_DREAR_EAV_MASK ((uint32_t)0xFFU << 16U) +#define RPC_DREAR_EAC_MASK ((uint32_t)0x7U << 0U) +#define RPC_DREAR_EAC_EXT_ADDR_25BIT ((uint32_t)0x1U << 0U) +#define RPC_DREAR_HW_INIT (0x00000000U) +#define RPC_DRENR_CDB_MASK (0xC0000000U) +#define RPC_DRENR_CDB_1BIT (0x00000000U) +#define RPC_DRENR_ADB_MASK (0x03000000U) +#define RPC_DRENR_ADB_4BIT (0x02000000U) +#define RPC_DRENR_DRDB_MASK (0x00030000U) +#define RPC_DRENR_DRDB_4BIT (0x00020000U) +#define RPC_DRENR_DME_MASK (0x00008000U) +#define RPC_DRENR_DME_ENABLE (0x00008000U) +#define RPC_DRENR_CDE_ENABLE ((uint32_t)0x1U << 14U) +#define RPC_DRENR_ADE_MASK (0x00000F00U) +#define RPC_DRENR_ADE_32BIT_ADDR ((uint32_t)0xFU << 8U) +#define RPC_DRENR_HW_INIT (0x00004700U) +#define RPC_DRENR_TRANS_DISABLE (0x00000000U) +#define RPC_SMCMR_CMD_SHIFT (16U) +#define RPC_SMCMR_CMD_MASK (0x00FF0000U) +#define RPC_SMCMR_OCMD_MASK (0x000000FFU) +#define RPC_SMDRENR_HYPE_MASK (0x00007000U) +#define RPC_SMDRENR_ADDRE (0x00000100U) +#define RPC_SMDRENR_OPDRE (0x00000010U) +#define RPC_SMDRENR_SPIDRE (0x00000001U) +#define RPC_SMENR_CDB_MASK (0xC0000000U) +#define RPC_SMENR_OCDB_MASK (0x30000000U) +#define RPC_SMENR_ADB_MASK (0x03000000U) +#define RPC_SMENR_OPDB_MASK (0x00300000U) +#define RPC_SMENR_SPIDB_MASK (0x00030000U) +#define RPC_SMENR_DME_EN (0x00008000U) +#define RPC_SMENR_CDE_EN (0x00004000U) +#define RPC_SMENR_OCDE_EN (0x00001000U) +#define RPC_SMENR_ADE_MASK (0x00000F00U) +#define RPC_SMENR_OPDE_MASK (0x000000F0U) +#define RPC_SMENR_SPIDE_MASK (0x0000000FU) +#define RPC_SMENR_SPIDE_SPI_32 (0x0000000FU) +#define RPC_SMCR_SSLKP (0x00000100U) +#define RPC_SMCR_SPIRE (0x00000004U) +#define RPC_SMCR_SPIWE (0x00000002U) +#define RPC_SMCR_SPIE (0x00000001U) +#define RPC_CMNCR_MD (0x80000000U) /* bit[31]:Operating Mode Switch -> Manual mode */ +#define RPC_CMNCR_MOIIO_MASK (0x00FF0000U) +#define RPC_CMNCR_MOIIO3_HI_Z (0x00C00000U) +#define RPC_CMNCR_MOIIO2_HI_Z (0x00300000U) +#define RPC_CMNCR_MOIIO1_HI_Z (0x000C0000U) +#define RPC_CMNCR_MOIIO0_HI_Z (0x00030000U) +#define RPC_CMNCR_BSZ_MASK (0x00000003U) +#define RPC_DRDRENR_DRDRE (0x00000001U) +#define RPC_DRDRENR_ADDRE (0x00000100U) +#define RPC_PHYOFFSET1_DDRTMG_MSK (0x30000000U) +#define RPC_PHYOFFSET1_DDRTMG_DDR (0x20000000U) +#define CMNSR_TEND (0x00000001U) + +#define STRTIM_SMALLEST (0x0000000FU) +#define STRTIM_MASK_3 (0x00000008U) +#define STRTIM_MASK (0x00000007U) +#define STRTIM_MATCH_ERROR (0xFFFFFFFFU) + +#define RST_MODEMR0_BOOTMODE (0xFU << 1U) +#define BOOTMODE_QSPI_SINGLE_40MHZ (0x4U) + +/* QSPI Flash device ID */ +#define DEVID_S25FS512S (0x00200201U) /* S25FS512S */ +#if USER_ADDED_QSPI == 1 +#define DEVID_XXXXXXXXX (0xFFFFFFFFU) +#endif /* USER_ADDED_QSPI == 1 */ + +/* For return value */ +#define QSPI_CMD_INIT_SUCCESS (0x00000000U) +#define QSPI_CMD_INIT_ERROR (0xFFFFFFFFU) +/* Common command for QSPI Flash */ +#define FLASH_CMD_READ_ID (0x9FU) +/* Device ID mask for QSPI Flash */ +#define DEVICE_ID_MASK (0x00FFFFFFU) + +/* For PFC register */ +#define PFC_PUEN3_QSPI0_IO3 (0x00010000U) /* bit16 */ +#define PFC_PUEN3_QSPI0_IO2 (0x00020000U) /* bit17 */ + +typedef struct{ + uint32_t reg_addr; /* registers address. */ + uint32_t value; /* setting value. */ +} st_register_table_t; + + +#define RPC_TBL_MAX (13U) + +static st_register_table_t g_rpc_reg_hwinit_val_tbl[RPC_TBL_MAX]; + +static const uint32_t dev_id_index[VENDOR_NUM] = +{ + /* QSPI Flash device ID */ + DEVID_S25FS512S, /* S25FS512S */ +#if USER_ADDED_QSPI == 1 + /* User can customize for another vendor's QSPI Flash. */ + DEVID_XXXXXXXXX +#endif /* USER_ADDED_QSPI == 1 */ +}; + +static const st_qspi_cmd_tbl_t* gp_qspi_cmd_tbl; + + +/* verification data for strobe timing adjustment */ +#define QSPI_TESTDATA (0x5A5AA5A5U) +#define QSPI_TESTDATA_OFFSET (0x00000400U) +#define QSPI_TESTDATA_FLASH_ADDR (FLASH_CONTENT_CERT_ADDR + QSPI_TESTDATA_OFFSET) /* Offset 0x00240400 */ + +static void rpc_save_hw_init_val(void); +static uint32_t read_qspi_flash_id(void); +static uint32_t init_qspi_cmd(uint32_t device_id); +static inline void set_strtim(uint32_t strobe_timing); +#if (QSPI_DDR_MODE==1) +static void adjust_strobe_timing(void); +#endif + + +void rpc_init(void) +{ + uint32_t reg; + uint32_t qspi_flash_id; + uint32_t rtn_val; + + /* Save HW initial value of RPC registers */ + rpc_save_hw_init_val(); + + /* judge boot device */ + reg = (mem_read32(RST_MODEMR0) & RST_MODEMR0_BOOTMODE) >> 1U; + + if(reg == BOOTMODE_QSPI_SINGLE_40MHZ) + { + /* check the transfer end flag */ + rpc_end_state_check(); + + /* Initialize command for QSPI Flash. */ + rtn_val = read_qspi_flash_id(); + qspi_flash_id = (rtn_val & DEVICE_ID_MASK); + rtn_val = init_qspi_cmd(qspi_flash_id); + if(rtn_val != QSPI_CMD_INIT_SUCCESS) + { + /* unknown QSPI Flash ID */ + ERROR("QSPI Flash command initialization error!!\n"); + panic; + } + +#if (QSPI_DDR_MODE==1) + /* Initialize for QSPI DDR transfer mode */ + qspi_ddr_transfer_mode(gp_qspi_cmd_tbl->ddr_quad_io_read_32bit_addr); +#else + /* Initialize for QSPI SDR transfer mode */ + qspi_sdr_transfer_mode(gp_qspi_cmd_tbl->read_32bit_addr); +#endif + } +} +/* End of function rpc_init(void) */ + +void rpc_release(void) +{ + uint32_t loop; + + /* Set HW initial value to RPC registers */ + for(loop = 0; loop < RPC_TBL_MAX; loop++) + { + mem_write32(g_rpc_reg_hwinit_val_tbl[loop].reg_addr, g_rpc_reg_hwinit_val_tbl[loop].value); + } +} +/* End of function rpc_release(void) */ + +void rpc_end_state_check(void) +{ + /* Wait until RPC data transfer is completed */ + while ((mem_read32(RPC_CMNSR) & CMNSR_TEND) != 1U) + { + ; + } +} +/* End of function rpc_end_state_check(void) */ + + +static void rpc_save_hw_init_val(void) +{ + uint32_t loop; + + g_rpc_reg_hwinit_val_tbl[0].reg_addr = RPC_CMNCR; + g_rpc_reg_hwinit_val_tbl[1].reg_addr = RPC_DRCR; + g_rpc_reg_hwinit_val_tbl[2].reg_addr = RPC_DRCMR; + g_rpc_reg_hwinit_val_tbl[3].reg_addr = RPC_DREAR; + g_rpc_reg_hwinit_val_tbl[4].reg_addr = RPC_DRENR; + g_rpc_reg_hwinit_val_tbl[5].reg_addr = RPC_SMCR; + g_rpc_reg_hwinit_val_tbl[6].reg_addr = RPC_SMCMR; + g_rpc_reg_hwinit_val_tbl[7].reg_addr = RPC_SMENR; + /* RPC_SMRDR0 is Read only */ + /* RPC_CMNSR is Read only */ + g_rpc_reg_hwinit_val_tbl[8].reg_addr = RPC_DRDMCR; + g_rpc_reg_hwinit_val_tbl[9].reg_addr = RPC_DRDRENR; + g_rpc_reg_hwinit_val_tbl[10].reg_addr = RPC_SMDRENR; + g_rpc_reg_hwinit_val_tbl[11].reg_addr = RPC_PHYCNT; + g_rpc_reg_hwinit_val_tbl[12].reg_addr = RPC_PHYOFFSET1; + + /* Save RPC register initial value */ + for(loop = 0; loop < RPC_TBL_MAX; loop++) + { + g_rpc_reg_hwinit_val_tbl[loop].value = mem_read32(g_rpc_reg_hwinit_val_tbl[loop].reg_addr); + } +} + +#if (QSPI_DDR_MODE==0) +void qspi_sdr_transfer_mode(uint32_t command) +{ + uint32_t reg; + /* check the transfer end flag */ + rpc_end_state_check(); + + /* For the initial setting flow of RPC, see Figure 112.12 in */ + /* "R-Car Series, S4 Series User's Manual" and */ + /* "R-Car Series, V4H Series User's Manual". */ + /* This RPC setting is for S25FS512S device */ + /* A register that does not set a value expects */ + /* the initial value of HW. */ + + /* PHY calibration */ + set_strtim(STRTIM_SMALLEST); + reg = mem_read32(RPC_PHYCNT); + reg |= RPC_PHYCNT_CAL; + mem_write32(RPC_PHYCNT, reg); + /* External Address Space Read Mode */ + reg = mem_read32(RPC_CMNCR); + reg &= ~(RPC_CMNCR_MD); + mem_write32(RPC_CMNCR, reg); + /* Read cache Flash */ + reg = mem_read32(RPC_DRCR); + mem_write32(RPC_DRCR, (reg | RPC_DRCR_RCF)); + /* 32bit address read command*/ + reg = mem_read32(RPC_DRCMR); + reg &= ~(RPC_DRCMR_CMD_MASK | RPC_DRCMR_OCMD_MASK); + reg |= (command << RPC_SMCMR_CMD_SHIFT); + mem_write32(RPC_DRCMR, reg); + /* Extended external address valid range is [25:0]*/ + reg = mem_read32(RPC_DREAR); + reg &= ~(RPC_DREAR_EAV_MASK | RPC_DREAR_EAC_MASK); + reg |= RPC_DREAR_EAC_EXT_ADDR_25BIT; + mem_write32(RPC_DREAR, reg); + /* output command is 32bit width */ + reg = mem_read32(RPC_DRENR); + reg &= ~(RPC_DRENR_CDE_ENABLE | RPC_DRENR_ADE_MASK); + reg |= (RPC_DRENR_CDE_ENABLE | RPC_DRENR_ADE_32BIT_ADDR); + mem_write32(RPC_DRENR, reg); +} +/* End of function rpc_init(void) */ + +#else +void qspi_ddr_transfer_mode(uint32_t command) +{ + uint32_t reg; + + /* check the transfer end flag */ + rpc_end_state_check(); + + cpg_reg_write(CPG_RPCCKCR, CPG_RPCCKCR, RPC_CLK_160MHZ); /* RPCD2 = 80MHz */ + + /* Disable pull-up/down function of QSPI0_IO2/QSPI0_IO3 when QSPI DDR transfer mode. */ + reg = mem_read32(PFC_PUEN3_RW); + reg &= ~(PFC_PUEN3_QSPI0_IO3 | PFC_PUEN3_QSPI0_IO2); + pfc_reg_write(PFC_PUEN3_RW, reg); + + /* For the initial setting flow of RPC, see Figure 112.12 in */ + /* "R-Car Series, S4 Series User's Manual" and */ + /* "R-Car Series, V4H Series User's Manual". */ + /* This RPC setting is for S25FS512S device */ + /* A register that does not set a value expects */ + /* the initial value of HW. */ + + /* PHY calibration */ + set_strtim(STRTIM_SMALLEST); + reg = mem_read32(RPC_PHYCNT); + reg |= RPC_PHYCNT_DDRCAL; + reg |= RPC_PHYCNT_PHYMEM_SPI_DDR; + mem_write32(RPC_PHYCNT, reg); + /* External Address Space Read Mode */ + reg = mem_read32(RPC_CMNCR); + reg &= ~(RPC_CMNCR_MD | RPC_CMNCR_MOIIO_MASK | RPC_CMNCR_BSZ_MASK); + reg |= (RPC_CMNCR_MOIIO0_HI_Z | RPC_CMNCR_MOIIO1_HI_Z | RPC_CMNCR_MOIIO2_HI_Z | RPC_CMNCR_MOIIO3_HI_Z); + mem_write32(RPC_CMNCR, reg); + /* Read cache Flash */ + reg = mem_read32(RPC_DRCR); + reg &= ~(RPC_DRCR_RBE_RBURST_MASK); + reg |= (RPC_DRCR_SSLN_NEGATE | RPC_DRCR_RBE_RBURST_1DATA | RPC_DRCR_RCF | RPC_DRCR_RBE_ENABLE); + mem_write32(RPC_DRCR, (reg | RPC_DRCR_RCF)); + /* 32bit address read command*/ + reg = mem_read32(RPC_DRCMR); + reg &= ~(RPC_DRCMR_CMD_MASK | RPC_DRCMR_OCMD_MASK); + reg |= (command << RPC_SMCMR_CMD_SHIFT); + mem_write32(RPC_DRCMR, reg); + /* Extended external address valid range is [25:0]*/ + reg = mem_read32(RPC_DREAR); + reg &= ~(RPC_DREAR_EAV_MASK | RPC_DREAR_EAC_MASK); + reg |= RPC_DREAR_EAC_EXT_ADDR_25BIT; + mem_write32(RPC_DREAR, reg); + /* output command is 32bit width */ + reg = mem_read32(RPC_DRENR); + reg &= ~(RPC_DRENR_CDB_MASK | RPC_DRENR_ADB_MASK | RPC_DRENR_DRDB_MASK + | RPC_DRENR_DME_MASK | RPC_DRENR_CDE_ENABLE | RPC_DRENR_ADE_MASK); + reg |= (RPC_DRENR_CDB_1BIT | RPC_DRENR_ADB_4BIT | RPC_DRENR_DRDB_4BIT + | RPC_DRENR_DME_ENABLE | RPC_DRENR_CDE_ENABLE | RPC_DRENR_ADE_32BIT_ADDR); + mem_write32(RPC_DRENR, reg); + /* Set Dummy Cycle */ + mem_write32(RPC_DRDMCR, (uint32_t)RCAR_QSPI_DDR_DUMMY_CYCLE - 1U); + /* Specifies DDR transfer of the data read. */ + reg = mem_read32(RPC_DRDRENR); + reg |= RPC_DRDRENR_DRDRE | RPC_DRDRENR_ADDRE; + mem_write32(RPC_DRDRENR, reg); + /* timing adjustment in DDR read operation. */ + reg = mem_read32(RPC_PHYOFFSET1); + reg &= ~(RPC_PHYOFFSET1_DDRTMG_MSK); + reg |= RPC_PHYOFFSET1_DDRTMG_DDR; + mem_write32(RPC_PHYOFFSET1, reg); + + /* Change PHYCNT.DDRCAL */ + reg = mem_read32(RPC_PHYCNT); + reg |= RPC_PHYCNT_PHYMEM_SPI_DDR; + reg &= ~RPC_PHYCNT_CAL; + reg |= RPC_PHYCNT_DDRCAL; + mem_write32(RPC_PHYCNT, reg); + + adjust_strobe_timing(); + + /* Set data burst length to 256 byte */ + reg = mem_read32(RPC_DRCR); + reg |= RPC_DRCR_RBE_RBURST_32DATA; + mem_write32(RPC_DRCR, reg); +} + +static void adjust_strobe_timing(void) +{ + uint32_t reg; + uint32_t flash_data; + uint32_t remap_flash_addr; + uint32_t strobe_timing = STRTIM_SMALLEST; + uint32_t first_match = STRTIM_MATCH_ERROR; + uint32_t match_count = 0U; + uint32_t loop; + + /* Convert verification data to logical addresses. */ + remap_register(QSPI_TESTDATA_FLASH_ADDR, &remap_flash_addr); + + INFO("Adjust strobe timing\n"); + + INFO("QSPI_TESTDATA_FLASH_ADDR = 0x%08x\n",remap_flash_addr); + + for(loop = 0U; loop <= STRTIM_SMALLEST; loop++) + { + /* RPC Transfer Disable */ + mem_write32(RPC_DRENR, RPC_DRENR_TRANS_DISABLE); + + /* Read cache Flash */ + reg = mem_read32(RPC_DRCR); + mem_write32(RPC_DRCR, (reg | RPC_DRCR_RCF)); + + /* set strobe timing */ + set_strtim(strobe_timing); + + /* RPC Transfer Enable */ + reg = mem_read32(RPC_DRENR); + reg &= ~(RPC_DRENR_CDB_MASK | RPC_DRENR_ADB_MASK | RPC_DRENR_DRDB_MASK + | RPC_DRENR_DME_MASK | RPC_DRENR_CDE_ENABLE | RPC_DRENR_ADE_MASK); + reg |= (RPC_DRENR_CDB_1BIT | RPC_DRENR_ADB_4BIT | RPC_DRENR_DRDB_4BIT + | RPC_DRENR_DME_ENABLE | RPC_DRENR_CDE_ENABLE | RPC_DRENR_ADE_32BIT_ADDR); + mem_write32(RPC_DRENR, reg); + + /* Read verification Data on QSPIFlash */ + flash_data = mem_read32(remap_flash_addr); + + /* check the transfer end flag */ + rpc_end_state_check(); + + INFO("strobe timing:0x%x\tflash_data:0x%x\ttest_data:0x%x\n", strobe_timing, flash_data, QSPI_TESTDATA); + + /* Comparison of Verification Data */ + if(flash_data == QSPI_TESTDATA) + { + /* First match of validation data. */ + if(first_match == STRTIM_MATCH_ERROR) + { + first_match = strobe_timing; + } + match_count++; + } + else + { + /* If out of timing to match */ + if(first_match != STRTIM_MATCH_ERROR) + { + /* Terminate the exploration of Strobe timing. */ + break; + } + } + strobe_timing--; + } + + /* Verification Data is not matched */ + if(first_match == STRTIM_MATCH_ERROR) + { + ERROR("Failed Strobe timing adjustment of DDR transfer mode.\n"); + panic; + } + + INFO("first_match:0x%x\tmatch_count:0x%x\n", first_match, match_count); + remap_unregister(remap_flash_addr); + + /* strobe timing value adjustment */ + strobe_timing = first_match - (match_count / 2U); + + /* set strobe timing */ + set_strtim(strobe_timing); + INFO("RPC_PHYCNT\t = 0x%08x\n",mem_read32(RPC_PHYCNT)); +} +#endif + +static inline void set_strtim(uint32_t strobe_timing) +{ + uint32_t reg; + reg = mem_read32(RPC_PHYCNT); + reg &= ~((STRTIM_MASK_3 << 24U) | (STRTIM_MASK << 15U)); + reg |= ((strobe_timing & STRTIM_MASK_3) << 24U); /* bit[27] */ + reg |= ((strobe_timing & STRTIM_MASK) << 15U); /* bit[17:15] */ + mem_write32(RPC_PHYCNT, reg); +} + + +static uint32_t read_qspi_flash_id(void) +{ + uint32_t reg; + uint32_t device_id; + + reg = mem_read32(RPC_PHYCNT); + reg &= ~( RPC_PHYCNT_HS + | RPC_PHYCNT_WBUF2 + | RPC_PHYCNT_WBUF + | RPC_PHYCNT_PHYMEM_MASK); + mem_write32(RPC_PHYCNT, reg); + set_strtim(STRTIM_SMALLEST); + reg |= RPC_PHYCNT_CAL; + mem_write32(RPC_PHYCNT, reg); + /* bit31 CAL = 1 : PHY calibration */ + /* bit1-0 PHYMEM[1:0] = 00 : QSPI-SDR */ + + reg = mem_read32(RPC_CMNCR); + reg &= ~(RPC_CMNCR_BSZ_MASK); + reg |= (RPC_CMNCR_MD); + mem_write32(RPC_CMNCR, reg); + /* bit31 MD = 1 : Manual mode */ + /* bit1-0 BSZ[1:0] = 00 : QSPI Flash x 1 */ + + reg = mem_read32(RPC_SMCMR); + reg &= ~( RPC_SMCMR_CMD_MASK + | RPC_SMCMR_OCMD_MASK); + reg |= (FLASH_CMD_READ_ID << RPC_SMCMR_CMD_SHIFT); + mem_write32(RPC_SMCMR, reg); + /* bit23-16 CMD[7:0] = 0x9F : Read ID command (for Palladium QSPI model) */ + + reg = mem_read32(RPC_SMDRENR); + reg &= ~( RPC_SMDRENR_HYPE_MASK + | RPC_SMDRENR_ADDRE + | RPC_SMDRENR_OPDRE + | RPC_SMDRENR_SPIDRE); + mem_write32(RPC_SMDRENR, reg); + /* bit8 ADDRE = 0 : Address SDR transfer */ + /* bit0 SPIDRE = 0 : DATA SDR transfer */ + + reg = mem_read32(RPC_SMENR); + reg &= ~( RPC_SMENR_CDB_MASK + | RPC_SMENR_OCDB_MASK + | RPC_SMENR_ADB_MASK + | RPC_SMENR_OPDB_MASK + | RPC_SMENR_SPIDB_MASK + | RPC_SMENR_DME_EN + | RPC_SMENR_OCDE_EN + | RPC_SMENR_ADE_MASK + | RPC_SMENR_OPDE_MASK + | RPC_SMENR_SPIDE_MASK); + reg |= ( RPC_SMENR_CDE_EN + | RPC_SMENR_SPIDE_SPI_32); + mem_write32(RPC_SMENR, reg); + /* bit31-30 CDB[1:0] = 00 : 1bit width command (QSPI0_MOSI) */ + /* bit25-24 ADB[1:0] = 00 : 1bit width address (QSPI0_MOSI) */ + /* bit17-16 SPIDB[1:0] = 00 : 1bit width transfer data (QSPI0_MISO) */ + /* bit15 DME = 0 : No dummy cycle */ + /* bit14 CDE = 1 : Command enable */ + /* bit11-8 ADE[3:0] = 0000 : Address output disable */ + /* bit3-0 SPIDE[3:0] = 1111 : 32bit transfer */ + + reg = mem_read32(RPC_SMCR); + reg &= ~( RPC_SMCR_SSLKP + | RPC_SMCR_SPIWE); + reg |= ( RPC_SMCR_SPIRE + | RPC_SMCR_SPIE); + mem_write32(RPC_SMCR, reg); + /* bit2 SPIRE = 1 : Data read enable */ + /* bit1 SPIWE = 0 : Data write disable */ + /* bit0 SPIE = 1 : SPI transfer start */ + + rpc_end_state_check(); + + device_id = mem_read32(RPC_SMRDR0); + + return device_id; +} +/* End of function read_qspi_flash_id(void) */ + +static uint32_t init_qspi_cmd(uint32_t device_id) +{ + uint32_t i = 0U; + uint32_t rtn_val = QSPI_CMD_INIT_ERROR; + + gp_qspi_cmd_tbl = NULL; + + for (i = 0U; i < VENDOR_NUM; i++) + { + if (device_id == dev_id_index[i]) + { + gp_qspi_cmd_tbl = &qspi_cmd_tbls[i]; + rtn_val = QSPI_CMD_INIT_SUCCESS; + break; + } + } + return rtn_val; +} +/* End of function init_qspi_cmd(uint32_t device_id) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/rtvram/rtvram.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/rtvram/rtvram.c new file mode 100644 index 0000000..291d639 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/rtvram/rtvram.c @@ -0,0 +1,77 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-VRAM driver + ******************************************************************************/ +/****************************************************************************** + * @file RTVRAM.c + * - Version : 0.03 + * @brief RT-VRAM driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 17.11.2021 0.01 First Release + * : 03.12.2021 0.02 remove Cache flush. + * : 06.01.2022 0.03 Static analysis support + *****************************************************************************/ + +#include +#include +#include +#include +#include + +#define RTVRAM_VBUF_CFG_CACHE_MODE_8WAY (1U << 8U) +#define RTVRAM_VBUF_CFG_VBUF_SIZE_28M (6U << 0U) + +#define RTVRAM_EXT_MODE_EXT (1U << 0U) + +#define RTVRAM_VBUF_NUM (7U) + +#define RTVRAM_EXTEND_ENABLE (1U) + +void rtvram_extendmode(void) +{ +#if (RTVRAM_EXTEND == RTVRAM_EXTEND_ENABLE) + uint32_t reg; + uint32_t loop; + + /* Set each 4MB from the top of SDRAM as the buffer area of RT-VRAM. */ + for(loop = 0; loop < RTVRAM_VBUF_NUM; loop++) + { + mem_write32(get_vbuf_baddr_addr(loop), (uint32_t)((SDRAM_40BIT_ADDR_TOP + (RTVRAM_VBUF_AREA_SIZE * loop)) >> 16U)); + } + + reg = mem_read32(RTVRAM_VBUF_CFG); + reg |= (RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | RTVRAM_VBUF_CFG_VBUF_SIZE_28M); /* Cache Mode: 8-way, VBF size: 28M */ + mem_write32(RTVRAM_VBUF_CFG, reg); + + /* Set at the end */ + mem_write32(RTVRAM_EXT_MODE, RTVRAM_EXT_MODE_EXT); /* Change from Compatible Mode to Extended Mode */ + + syncm(); +#endif +} +/* End of function rtvram_extendmode(void) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/sysc/sysc.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/sysc/sysc.c new file mode 100644 index 0000000..29a3f1b --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/sysc/sysc.c @@ -0,0 +1,109 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : System Controller function + ******************************************************************************/ +/****************************************************************************** + * @file sysc.c + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.09.2023 0.01 First Release + * : 13.11.2023 0.02 Add software reset + * : 16.11.2023 0.03 Add APSREG initialization process. + * : 22.10.2024 0.04 Update the C4 power domain setting process. +*****************************************************************************/ +#include "mem_io.h" +#include "sysc.h" +#include "cpg_register.h" +#include "log.h" +#include "cpu_on.h" +#include "ap_system_core_register.h" + +/* + * V4M turns on C4 power before starting CA + * V4M HWM:SYSC:Operation:Power Control of Non Arm CPU Modules + */ +#if (RCAR_LSI == RCAR_V4M) +void sysc_c4_power_on(void) +{ + uint32_t reg; + + /* + * Need to execute APSREG initialization before C4 power on according to + * R-Car V4M Series User's Manual '5.4.3 Register Initialization Before C4 power on'. + */ + reg = mem_read32(ap_core_get_ap_cluster_n_aux0_addr(0U)); + reg |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT; + mem_write32(ap_core_get_ap_cluster_n_aux0_addr(0U), reg); + + reg = mem_read32(AP_CORE_APSREG_CCI500_AUX); + reg |= AP_CORE_APSREG_CCI500_AUX_ACTDIS; + mem_write32(AP_CORE_APSREG_CCI500_AUX, reg); + + /* 1.Write the set value in SYSCIER0 and SYSCIMR0 */ + reg = mem_read32(SYSC_SYSCIER0); + mem_write32(SYSC_SYSCIER0, reg | SYSCIER0_PDR31); + reg = mem_read32(SYSC_SYSCIMR0); + mem_write32(SYSC_SYSCIMR0, reg | SYSCIMR0_PDR31); + + /* 2.Confirm that SYSCSR.BUSY[1] becomes 1.*/ + while (true) + { + reg = mem_read32(SYSC_SYSCSR); + if (SYSCSR_BUSY1 == (reg & SYSCSR_BUSY1)) + { + break; + } + } + + /* 3.Write the reset value in SRCR11 and SESTCLR11 */ + reg = mem_read32(CPG_SRCR11); + mem_write32(CPG_SRCR11, reg | CPGSRCR_PDR11); + mem_write32(CPG_SRSTCLR11, CPGSRCR_PDR11); + + /* 4.Write the set value in PDRONCR31 */ + mem_write32(SYSC_PDRONCR31, PDRONCR31_PWRON); + + /* 5.Confirm that SYSCISCR0.PDR[31] becomes 1.*/ + while (true) + { + reg = mem_read32(SYSC_SYSCISCR0); + if (SYSCISCR0_PDR31 == (reg & SYSCISCR0_PDR31)) + { + break; + } + } + + /* 6.Clear the bit31(PDR[31]) in SYSCISCR0 to 0. */ + mem_write32(SYSC_SYSCISCR0, SYSCISCR0_PDR31); +} +/* End of function sysc_c4_power_on(void) */ +#endif /* RCAR_LSI == RCAR_V4M */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/wdt/wdt.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/wdt/wdt.c new file mode 100644 index 0000000..72933cd --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/ip/wdt/wdt.c @@ -0,0 +1,133 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : window watchdog timer driver + ******************************************************************************/ +/****************************************************************************** + * @file wdt.c + * - Version : 0.04 + * @brief Window Watchdog Timer driver + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 06.01.2022 0.02 Add exception handling for ICUMX_WDTA. + * : 20.01.2022 0.03 Add ICUMX name unification. + * : 11.01.2023 0.04 Modify activation code writing to + * : ICUMX_WDTA0EVAC register. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + + +#define ICUMX_WDTA0_BASE (0xFFFEE080U) /* Watchdog Timer base */ +#define ICUMX_WDTA0WDTE (ICUMX_WDTA0_BASE) +#define ICUMX_WDTA0EVAC (ICUMX_WDTA0_BASE+0x0004U) +#define ICUMX_WDTA0REF (ICUMX_WDTA0_BASE+0x0008U) +#define ICUMX_WDTA0MD (ICUMX_WDTA0_BASE+0x000CU) + + +#define WDTA0MD_WDTA0WIE (1U<<3) /* Enables the 75% interrupt request INTWDTA0 */ +#define WDTA0MD_WDTA0ERM (1U<<2) /* 0:NMI request mode 1:Reset mode */ +#define WDTA0MD_WDTA0WS10 (3U) /* 11B: window-open period is 100% */ + +/* overflow time setting */ +#define WDT_11MS (0x0U) +#define WDT_23MS (0x1U) +#define WDT_46MS (0x2U) +#define WDT_93MS (0x3U) +#define WDT_187MS (0x4U) +#define WDT_374MS (0x5U) +#define WDT_749MS (0x6U) +#define WDT_1498MS (0x7U) + +/* Activation code */ +#define WDT_ACT_CODE (0xACU) + +/* ICUMX Configuration Register */ +#define ICUMX_CFG4 (0xFFFEE270U) +/* Bit definition for Configuration Register */ +#define ICUMX_CFG4_ICUMOPWDVAC (0x00000020U) + +/* Initialization Window Watchdog Timer */ +void wdt_init(void) +{ + uint8_t wdta_val; + + /* This API is executed before copying a part of Loader to Local RAM. */ + /* Therefore, this API can not use the Memory mapped I/O API. */ + /* When reading or writing memory, execute the same processing as */ + /* Memory mapped I/O API in this function. */ + wdta_val = WDTA0MD_WDTA0ERM; /* NMI request mode */ + wdta_val |= WDTA0MD_WDTA0WIE; /* Enables the 75% interrupt request INTWDTA0 */ + wdta_val |= WDTA0MD_WDTA0WS10; + wdta_val |= (WDT_1498MS << 4U); /* overflow interval time */ + mem_write8(ICUMX_WDTA0MD, wdta_val); + + /* set watchdog timer handler */ + intc_set_interrupt(WDT0_INT, 7U, (INT_HANDLER)wdt_handler); + + /* watchdog timer restart */ + wdt_restart(); +} +/* End of function wdt_init(uint32_t overflow_time) */ + +void wdt_restart(void) +{ + uint8_t reg8; + uint32_t reg32; + + reg32 = mem_read32(ICUMX_CFG4); + + if((reg32 & ICUMX_CFG4_ICUMOPWDVAC) != 0U) + { + reg8 = mem_read8(ICUMX_WDTA0REF); + reg8 = WDT_ACT_CODE - reg8; + /* Watchdog Timer restart. */ + /* Subtract ICUMX_WDTA0REF from activation code when VAC(Variable Activation Code) is enabled. */ + mem_write8(ICUMX_WDTA0EVAC, reg8); + } + else + { + /* Watchdog Timer restart. */ + mem_write8(ICUMX_WDTA0EVAC, WDT_ACT_CODE); + } +} +/* End of function wdt_restart(void) */ + +/* Interrupt handling function */ +void wdt_handler(void) +{ + intc_disable_interrupt(WDT0_INT); + ERROR("\n"); + ERROR("ICUMX: System WDT overflow\n"); + panic; +} +/* End of function wdt_handler(void) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/icumx_loader.ld b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/icumx_loader.ld new file mode 100644 index 0000000..d8a22e5 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/icumx_loader.ld @@ -0,0 +1,192 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader linker directive + ******************************************************************************/ + +DEFAULTS { +//Memory + remap_addr = 0xFDE00000 //remap15 address(target address = 0xEB200000) + remap_size = 1M //RT-SRAM size + + rt_sram_addr = 0xEB200000 //RT-SRAM address + local_ram_addr = 0xfede0000 //LRAM address + local_ram_size = 128K //LRAM size + +// Size +//No override area + stack_size = 16K //ICUMX Loader stack size + sa9_size = 64K //content cert size(cert info 1K + content cert(14) * 2K) + bss_size = 16K +// Configuration Table + qosbw_table_size = 4K + qoswt_table_size = 4K + rgid_m_table_size = 1K + rgid_r_table_size = 8K + rgid_w_table_size = 8K + rgid_sec_table_size = 8K + rgid_axi_table_size = 1K + rgid_gid_table_size = 1K //include .data section + configuration_size = qosbw_table_size + qoswt_table_size + rgid_m_table_size + rgid_r_table_size + rgid_w_table_size + rgid_sec_table_size + rgid_axi_table_size + rgid_gid_table_size + +// ICUMX Loader + ipl_top_addr = 0xEB210000 + ipl_size = 128K //ICUMX Loader size + vector_table_size = 2K //vector table size + ipl_rom_size = ipl_size - (vector_table_size + configuration_size + bss_size) + +// Address +// ICUMX Loader + vector_table_address_offset = ipl_top_addr - rt_sram_addr + code_fetch_remap_vector_table = 0x1200000 + vector_table_address_offset // 0xEB200000 - 0xEA000000 + ipl start address offset + code_fetch_remap_ipl = code_fetch_remap_vector_table + (vector_table_size + configuration_size) + +// No override area + stack_addr_offset = remap_size - stack_size + sa9_addr_offset = 0x30000 + bss_addr_offset = sa9_addr_offset - bss_size + +// Configuration Table + configuration_table_address_offset = vector_table_address_offset + vector_table_size + configuration_table_address = code_fetch_remap_vector_table + vector_table_size + qosbw_table_address = configuration_table_address + qoswt_table_address = qosbw_table_address + qosbw_table_size + rgid_m_table_address = qoswt_table_address + qoswt_table_size + rgid_r_table_address = rgid_m_table_address + rgid_m_table_size + rgid_w_table_address = rgid_r_table_address + rgid_r_table_size + rgid_sec_table_address = rgid_w_table_address + rgid_w_table_size + rgid_axi_table_address = rgid_sec_table_address + rgid_sec_table_size + rgid_gid_table_address = rgid_axi_table_address + rgid_axi_table_size + +// Offset + qosbw_table_address_offset = vector_table_address_offset + vector_table_size + qoswt_table_address_offset = qosbw_table_address_offset + qosbw_table_size + rgid_m_table_address_offset = qoswt_table_address_offset + qoswt_table_size + rgid_r_table_address_offset = rgid_m_table_address_offset + rgid_m_table_size + rgid_w_table_address_offset = rgid_r_table_address_offset + rgid_r_table_size + rgid_sec_table_address_offset = rgid_w_table_address_offset + rgid_w_table_size + rgid_axi_table_address_offset = rgid_sec_table_address_offset + rgid_sec_table_size + rgid_gid_table_address_offset = rgid_axi_table_address_offset + rgid_axi_table_size + ipl_rom_address_offset = configuration_table_address_offset + configuration_size +} +MEMORY +{ + vector_table : ORIGIN = code_fetch_remap_vector_table , LENGTH = vector_table_size // ICUMX Loader (CFREMAP) + qosbw_table : ORIGIN = remap_addr + qosbw_table_address_offset , LENGTH = qosbw_table_size // configuration table (QOSBW) + qoswt_table : ORIGIN = remap_addr + qoswt_table_address_offset , LENGTH = qoswt_table_size // configuration table (QOSWT) + rgid_m_table : ORIGIN = remap_addr + rgid_m_table_address_offset , LENGTH = rgid_m_table_size // configuration table (Region ID(Master)) + rgid_r_table : ORIGIN = remap_addr + rgid_r_table_address_offset , LENGTH = rgid_r_table_size // configuration table (Region ID(Read)) + rgid_w_table : ORIGIN = remap_addr + rgid_w_table_address_offset , LENGTH = rgid_w_table_size // configuration table (Region ID(Write)) + rgid_sec_table : ORIGIN = remap_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure)) + rgid_axi_table : ORIGIN = remap_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (R/W for AXI) + rgid_gid_table : ORIGIN = remap_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (R/W for GID) + ipl_rom : ORIGIN = code_fetch_remap_ipl , LENGTH = ipl_rom_size + +// Physical address + phys_vector_table : ORIGIN = rt_sram_addr + vector_table_address_offset, LENGTH = vector_table_size //ICUMX Loader(RT-SRAM) + phys_qosbw_table : ORIGIN = rt_sram_addr + qosbw_table_address_offset, LENGTH = qosbw_table_size //configuration table (QOSBW) + phys_qoswt_table : ORIGIN = rt_sram_addr + qoswt_table_address_offset, LENGTH = qoswt_table_size //configuration table (QOSWT) + phys_rgid_m_table : ORIGIN = rt_sram_addr + rgid_m_table_address_offset, LENGTH = rgid_m_table_size // configuration table (Region ID(Master)) + phys_rgid_r_table : ORIGIN = rt_sram_addr + rgid_r_table_address_offset, LENGTH = rgid_r_table_size // configuration table (Region ID(Read)) + phys_rgid_w_table : ORIGIN = rt_sram_addr + rgid_w_table_address_offset, LENGTH = rgid_w_table_size // configuration table (Region ID(Write)) + phys_rgid_sec_table : ORIGIN = rt_sram_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure)) + phys_rgid_axi_table : ORIGIN = rt_sram_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (Region ID(R/W for AXI)) + phys_rgid_gid_table : ORIGIN = rt_sram_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (Region ID(R/W for GID)) + phys_ipl_rom : ORIGIN = rt_sram_addr + ipl_rom_address_offset, LENGTH = ipl_rom_size //ICUMX Loader(RT-SRAM) + +// No override area + sa9_load : ORIGIN = remap_addr + sa9_addr_offset, LENGTH = sa9_size // Content cert + stack : ORIGIN = remap_addr + stack_addr_offset, LENGTH = stack_size // ICUMX Loader stack + bss : ORIGIN = remap_addr + bss_addr_offset, LENGTH = bss_size // ICUMX Loader bss area + local_ram : ORIGIN = local_ram_addr, LENGTH = local_ram_size - stack_size // Local RAM +} + +// +// Program layout for starting in ROM, copying data to RAM, +// and continuing to execute out of ROM. +// +SECTIONS +{ +// +// ROM SECTIONS(Remap) +// +// Place .text into fast_memory. Fail if it does not fit. + .reset ALIGN(4) : > vector_table + .EIINTTBL_ICU ALIGN(512) : > . + .qosbw_tbl ALIGN(4) : > qosbw_table + .qoswt_tbl ALIGN(4) : > qoswt_table + .rgid_m_tbl ALIGN(4) : > rgid_m_table + .rgid_r_tbl ALIGN(4) : > rgid_r_table + .rgid_w_tbl ALIGN(4) : > rgid_w_table + .rgid_sec_tbl ALIGN(4) : > rgid_sec_table + .rgid_axi_tbl ALIGN(4) : > rgid_axi_table + .rgid_gid_tbl ALIGN(4) : > rgid_gid_table + .data ALIGN(4) : > . + .text ALIGN(4) : > ipl_rom + .RE_CR.text ALIGN(4) : > . + .rosdata ALIGN(4) : > . + .rodata ALIGN(4) : > . + .secinfo ALIGN(4) : > . + + .rom_end ALIGN(4) : > . + .canary ALIGN(4) : > bss + .bss ALIGN(4) : > . + +// ROM mirror SECTIONS(RT-SRAM) + _start = ipl_top_addr; + .ROM_NOCOPY.reset ROM_NOCOPY(.reset) ALIGN(4) : > phys_vector_table + .ROM_NOCOPY.EIINTTBL_ICU ROM_NOCOPY(.EIINTTBL_ICU) ALIGN(4) : > . + .ROM_NOCOPY.qosbw_tbl ROM_NOCOPY(.qosbw_tbl) ALIGN(4) : > phys_qosbw_table + .ROM_NOCOPY.qoswt_tbl ROM_NOCOPY(.qoswt_tbl) ALIGN(4) : > phys_qoswt_table + .ROM_NOCOPY.rgid_m_tbl ROM_NOCOPY(.rgid_m_tbl) ALIGN(4) : > phys_rgid_m_table + .ROM_NOCOPY.rgid_r_tbl ROM_NOCOPY(.rgid_r_tbl) ALIGN(4) : > phys_rgid_r_table + .ROM_NOCOPY.rgid_w_tbl ROM_NOCOPY(.rgid_w_tbl) ALIGN(4) : > phys_rgid_w_table + .ROM_NOCOPY.rgid_sec_tbl ROM_NOCOPY(.rgid_sec_tbl) ALIGN(4) : > phys_rgid_sec_table + .ROM_NOCOPY.rgid_axi_tbl ROM_NOCOPY(.rgid_axi_tbl) ALIGN(4) : > phys_rgid_axi_table + .ROM_NOCOPY.rgid_gid_tbl ROM_NOCOPY(.rgid_gid_tbl) ALIGN(4) : > phys_rgid_gid_table + .ROM_NOCOPY.data ROM_NOCOPY(.data) ALIGN(4) : > . + .ROM_NOCOPY.text ROM_NOCOPY(.text) ALIGN(4) : > phys_ipl_rom + .ROM_NOCOPY.RE_CR.text ROM_NOCOPY(.RE_CR.text) ALIGN(4) : > . + .ROM_NOCOPY.rosdata ROM_NOCOPY(.rosdata) ALIGN(4) : > . + .ROM_NOCOPY.rodata ROM_NOCOPY(.rodata) ALIGN(4) : > . + .ROM_NOCOPY.secinfo ROM_NOCOPY(.secinfo) ALIGN(4) : > . + .cr_hot_plug_magic ALIGN(16): > . // This section must be placed at the last of binary. + + + +// +// RAM SECTIONS +// + .top_stack : > stack + .RT.stack ALIGN(4) PAD(stack_size) ABS : > . + .end_stack : > . + + .top.local.ram : > local_ram + .sdata ALIGN(4) : > . + .tdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .end.local.ram : > . + + .sa9_load ALIGN(4) PAD(sa9_size) : > sa9_load +} diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/icumx_loader_v4m.ld b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/icumx_loader_v4m.ld new file mode 100644 index 0000000..6c6e4b9 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/icumx_loader_v4m.ld @@ -0,0 +1,194 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader linker directive + ******************************************************************************/ + +DEFAULTS { +//Memory + remap_addr = 0xFDE00000 //remap15 address(target address = 0xEB200000) + remap_size = 1M //RT-SRAM size + + rt_sram_addr = 0xEB200000 //RT-SRAM address + local_ram_addr = 0xfede0000 //LRAM address + local_ram_size = 128K //LRAM size + +// Size +//No override area + stack_size = 16K //ICUMX Loader stack size + bootrom_work_size = 2K + sa9_size = 64K //content cert size(cert info 1K + content cert(14) * 2K) + bss_size = 16K +// Configuration Table + qosbw_table_size = 4K + qoswt_table_size = 4K + rgid_m_table_size = 1K + rgid_r_table_size = 8K + rgid_w_table_size = 8K + rgid_sec_table_size = 8K + rgid_axi_table_size = 1K + rgid_gid_table_size = 1K //include .data section + configuration_size = qosbw_table_size + qoswt_table_size + rgid_m_table_size + rgid_r_table_size + rgid_w_table_size + rgid_sec_table_size + rgid_axi_table_size + rgid_gid_table_size + +// ICUMX Loader + ipl_top_addr = 0xEB210000 + ipl_size = 128K //ICUMX Loader size + vector_table_size = 2K //vector table size + ipl_rom_size = ipl_size - (vector_table_size + configuration_size + bss_size) + +// Address +// ICUMX Loader + vector_table_address_offset = ipl_top_addr - rt_sram_addr + code_fetch_remap_vector_table = 0x1200000 + vector_table_address_offset // 0xEB200000 - 0xEA000000 + ipl start address offset + code_fetch_remap_ipl = code_fetch_remap_vector_table + (vector_table_size + configuration_size) + +// No override area + stack_addr_offset = 110K // stack top address : 0xFEDFB800 (This is in Local RAM) + sa9_addr_offset = 0x30000 + bss_addr_offset = sa9_addr_offset - bss_size + +// Configuration Table + configuration_table_address_offset = vector_table_address_offset + vector_table_size + configuration_table_address = code_fetch_remap_vector_table + vector_table_size + qosbw_table_address = configuration_table_address + qoswt_table_address = qosbw_table_address + qosbw_table_size + rgid_m_table_address = qoswt_table_address + qoswt_table_size + rgid_r_table_address = rgid_m_table_address + rgid_m_table_size + rgid_w_table_address = rgid_r_table_address + rgid_r_table_size + rgid_sec_table_address = rgid_w_table_address + rgid_w_table_size + rgid_axi_table_address = rgid_sec_table_address + rgid_sec_table_size + rgid_gid_table_address = rgid_axi_table_address + rgid_axi_table_size + +// Offset + qosbw_table_address_offset = vector_table_address_offset + vector_table_size + qoswt_table_address_offset = qosbw_table_address_offset + qosbw_table_size + rgid_m_table_address_offset = qoswt_table_address_offset + qoswt_table_size + rgid_r_table_address_offset = rgid_m_table_address_offset + rgid_m_table_size + rgid_w_table_address_offset = rgid_r_table_address_offset + rgid_r_table_size + rgid_sec_table_address_offset = rgid_w_table_address_offset + rgid_w_table_size + rgid_axi_table_address_offset = rgid_sec_table_address_offset + rgid_sec_table_size + rgid_gid_table_address_offset = rgid_axi_table_address_offset + rgid_axi_table_size + ipl_rom_address_offset = configuration_table_address_offset + configuration_size +} +MEMORY +{ + vector_table : ORIGIN = code_fetch_remap_vector_table , LENGTH = vector_table_size // ICUMX Loader (CFREMAP) + qosbw_table : ORIGIN = remap_addr + qosbw_table_address_offset , LENGTH = qosbw_table_size // configuration table (QOSBW) + qoswt_table : ORIGIN = remap_addr + qoswt_table_address_offset , LENGTH = qoswt_table_size // configuration table (QOSWT) + rgid_m_table : ORIGIN = remap_addr + rgid_m_table_address_offset , LENGTH = rgid_m_table_size // configuration table (Region ID(Master)) + rgid_r_table : ORIGIN = remap_addr + rgid_r_table_address_offset , LENGTH = rgid_r_table_size // configuration table (Region ID(Read)) + rgid_w_table : ORIGIN = remap_addr + rgid_w_table_address_offset , LENGTH = rgid_w_table_size // configuration table (Region ID(Write)) + rgid_sec_table : ORIGIN = remap_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure)) + rgid_axi_table : ORIGIN = remap_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (R/W for AXI) + rgid_gid_table : ORIGIN = remap_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (R/W for GID) + ipl_rom : ORIGIN = code_fetch_remap_ipl , LENGTH = ipl_rom_size + +// Physical address + phys_vector_table : ORIGIN = rt_sram_addr + vector_table_address_offset, LENGTH = vector_table_size //ICUMX Loader(RT-SRAM) + phys_qosbw_table : ORIGIN = rt_sram_addr + qosbw_table_address_offset, LENGTH = qosbw_table_size //configuration table (QOSBW) + phys_qoswt_table : ORIGIN = rt_sram_addr + qoswt_table_address_offset, LENGTH = qoswt_table_size //configuration table (QOSWT) + phys_rgid_m_table : ORIGIN = rt_sram_addr + rgid_m_table_address_offset, LENGTH = rgid_m_table_size // configuration table (Region ID(Master)) + phys_rgid_r_table : ORIGIN = rt_sram_addr + rgid_r_table_address_offset, LENGTH = rgid_r_table_size // configuration table (Region ID(Read)) + phys_rgid_w_table : ORIGIN = rt_sram_addr + rgid_w_table_address_offset, LENGTH = rgid_w_table_size // configuration table (Region ID(Write)) + phys_rgid_sec_table : ORIGIN = rt_sram_addr + rgid_sec_table_address_offset, LENGTH = rgid_sec_table_size // configuration table (Region ID(Secure)) + phys_rgid_axi_table : ORIGIN = rt_sram_addr + rgid_axi_table_address_offset, LENGTH = rgid_axi_table_size // configuration table (Region ID(R/W for AXI)) + phys_rgid_gid_table : ORIGIN = rt_sram_addr + rgid_gid_table_address_offset, LENGTH = rgid_gid_table_size // configuration table (Region ID(R/W for GID)) + phys_ipl_rom : ORIGIN = rt_sram_addr + ipl_rom_address_offset, LENGTH = ipl_rom_size //ICUMX Loader(RT-SRAM) + +// No override area + sa9_load : ORIGIN = remap_addr + sa9_addr_offset, LENGTH = sa9_size // Content cert + stack : ORIGIN = local_ram_addr + stack_addr_offset, LENGTH = stack_size // ICUMX Loader stack (This is in Local RAM) + bss : ORIGIN = remap_addr + bss_addr_offset, LENGTH = bss_size // ICUMX Loader bss area + local_ram : ORIGIN = local_ram_addr, LENGTH = local_ram_size - stack_size - bootrom_work_size // Local RAM + bootrom_work : ORIGIN = local_ram_addr + stack_addr_offset + stack_size, LENGTH = bootrom_work_size // BootROM work area +} + +// +// Program layout for starting in ROM, copying data to RAM, +// and continuing to execute out of ROM. +// +SECTIONS +{ +// +// ROM SECTIONS(Remap) +// +// Place .text into fast_memory. Fail if it does not fit. + .reset ALIGN(4) : > vector_table + .EIINTTBL_ICU ALIGN(512) : > . + .qosbw_tbl ALIGN(4) : > qosbw_table + .qoswt_tbl ALIGN(4) : > qoswt_table + .rgid_m_tbl ALIGN(4) : > rgid_m_table + .rgid_r_tbl ALIGN(4) : > rgid_r_table + .rgid_w_tbl ALIGN(4) : > rgid_w_table + .rgid_sec_tbl ALIGN(4) : > rgid_sec_table + .rgid_axi_tbl ALIGN(4) : > rgid_axi_table + .rgid_gid_tbl ALIGN(4) : > rgid_gid_table + .data ALIGN(4) : > . + .text ALIGN(4) : > ipl_rom + .RE_CR.text ALIGN(4) : > . + .rosdata ALIGN(4) : > . + .rodata ALIGN(4) : > . + .secinfo ALIGN(4) : > . + + .rom_end ALIGN(4) : > . + .canary ALIGN(4) : > bss + .bss ALIGN(4) : > . + +// ROM mirror SECTIONS(RT-SRAM) + _start = ipl_top_addr; + .ROM_NOCOPY.reset ROM_NOCOPY(.reset) ALIGN(4) : > phys_vector_table + .ROM_NOCOPY.EIINTTBL_ICU ROM_NOCOPY(.EIINTTBL_ICU) ALIGN(4) : > . + .ROM_NOCOPY.qosbw_tbl ROM_NOCOPY(.qosbw_tbl) ALIGN(4) : > phys_qosbw_table + .ROM_NOCOPY.qoswt_tbl ROM_NOCOPY(.qoswt_tbl) ALIGN(4) : > phys_qoswt_table + .ROM_NOCOPY.rgid_m_tbl ROM_NOCOPY(.rgid_m_tbl) ALIGN(4) : > phys_rgid_m_table + .ROM_NOCOPY.rgid_r_tbl ROM_NOCOPY(.rgid_r_tbl) ALIGN(4) : > phys_rgid_r_table + .ROM_NOCOPY.rgid_w_tbl ROM_NOCOPY(.rgid_w_tbl) ALIGN(4) : > phys_rgid_w_table + .ROM_NOCOPY.rgid_sec_tbl ROM_NOCOPY(.rgid_sec_tbl) ALIGN(4) : > phys_rgid_sec_table + .ROM_NOCOPY.rgid_axi_tbl ROM_NOCOPY(.rgid_axi_tbl) ALIGN(4) : > phys_rgid_axi_table + .ROM_NOCOPY.rgid_gid_tbl ROM_NOCOPY(.rgid_gid_tbl) ALIGN(4) : > phys_rgid_gid_table + .ROM_NOCOPY.data ROM_NOCOPY(.data) ALIGN(4) : > . + .ROM_NOCOPY.text ROM_NOCOPY(.text) ALIGN(4) : > phys_ipl_rom + .ROM_NOCOPY.RE_CR.text ROM_NOCOPY(.RE_CR.text) ALIGN(4) : > . + .ROM_NOCOPY.rosdata ROM_NOCOPY(.rosdata) ALIGN(4) : > . + .ROM_NOCOPY.rodata ROM_NOCOPY(.rodata) ALIGN(4) : > . + .ROM_NOCOPY.secinfo ROM_NOCOPY(.secinfo) ALIGN(4) : > . + .cr_hot_plug_magic ALIGN(16): > . // This section must be placed at the last of binary. + + + +// +// RAM SECTIONS +// + .top.local.ram : > local_ram + .sdata ALIGN(4) : > . + .tdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .top_stack : > stack + .RT.stack ALIGN(4) PAD(stack_size) ABS : > . + .end_stack : > . + .used_by_bootrom ALIGN(4) PAD(bootrom_work_size) ABS : > bootrom_work // 0xFEDFF800 - 0xFEDFFFFF is prohibited writing + .end.local.ram : > . + + .sa9_load ALIGN(4) PAD(sa9_size) : > sa9_load +} diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader.S b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader.S new file mode 100644 index 0000000..e824f24 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader.S @@ -0,0 +1,168 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader start code + ******************************************************************************/ + + .global code_start + .global _loader_main + .global ___ghsend_RT_stack /* RT-SRAM stack Logical end address */ + .global ___ghs_set_stack_chk_guard + + BOOTROM_CODE_START_ADDRESS .set 0x01104000 /* Boot ROM start address */ + BOOTROM_CODE_END_ADDRESS .set 0x0112CFFC /* Boot ROM end address */ + SICREMAP_WINDOW_AREA_START_ADDRESS .set 0xFC000000 /* Remap 0 start address */ + SICREMAP_WINDOW_AREA_END_ADDRESS .set 0xFEBFFFFC /* SIC area end address */ + ICU_REGISTER_AREA_START_ADDRESS .set 0xFEDE0000 /* ICUMXB register area start address */ + ICU_REGISTER_AREA_END_ADDRESS .set 0xFFFEFFFC /* ICUMXB register area end address */ + + MPAT_SX_SR_ENABLE .set 0x000000E8 /* SV mode Read/Execution enable */ + MPAT_SW_SR_ENABLE .set 0x000000D8 /* SV mode Read/Writer enable */ + MPRC_E3_TO_E0_ENABLE .set 0x0000000F /* E0,E1,E2,E3 enable */ + MPM_SVP_MPE_ENABLE .set 0x00000003 /* SV mode protect enable, MPU enable */ + MPAT_ALL_DISABLE .set 0x00000040 + MPM_ALL_DISABLE .set 0x00000000 + + .section ".reset", "ax" + .align 2 + + +code_start: +/* ; initialize registers */ + mov r0, r1 + mov r0, r2 + mov r0, r3 + mov r0, r4 + mov r0, r5 + mov r0, r6 + mov r0, r7 + mov r0, r8 + mov r0, r9 + mov r0, r10 + mov r0, r11 + mov r0, r12 + mov r0, r13 + mov r0, r14 + mov r0, r15 + mov r0, r16 + mov r0, r17 + mov r0, r18 + mov r0, r19 + mov r0, r20 + mov r0, r21 + mov r0, r22 + mov r0, r23 + mov r0, r24 + mov r0, r25 + mov r0, r26 + mov r0, r27 + mov r0, r28 + mov r0, r29 + ldsr r0, 0, 0 + ldsr r0, 16, 0 + +/* set global pointer * + mov ___ghsbegin_sdabase, gp +/* set stack pointer */ + mov ___ghsend_RT_stack, sp + +/* MPU Disable */ + stsr 0, r6 ,5 + andi 0xFFFE, r6, r6 + ldsr r6, 0, 5 + SYNCM + +/* MPU setting */ + mov BOOTROM_CODE_START_ADDRESS, r12 /* MPLA0 */ + ldsr r12, 0, 6 + mov BOOTROM_CODE_END_ADDRESS, r12 /* MPUA0 */ + ldsr r12, 1, 6 + mov ___ghsbegin_reset, r12 /* MPLA1 */ + ldsr r12, 4, 6 + mov ___ghsend_rom_end, r12 /* MPUA1 */ + ldsr r12, 5, 6 + mov SICREMAP_WINDOW_AREA_START_ADDRESS, r12 /* MPLA2 */ + ldsr r12, 8, 6 + mov SICREMAP_WINDOW_AREA_END_ADDRESS, r12 /* MPUA2 */ + ldsr r12, 9, 6 + mov ICU_REGISTER_AREA_START_ADDRESS, r12 /* MPLA3 */ + ldsr r12, 12, 6 + mov ICU_REGISTER_AREA_END_ADDRESS, r12 /* MPUA3 */ + ldsr r12, 13, 6 + mov MPAT_SX_SR_ENABLE, r12 /* MPAT0 */ + ldsr r12, 2, 6 + mov MPAT_SX_SR_ENABLE, r12 /* MPAT1 */ + ldsr r12, 6, 6 + mov MPAT_SW_SR_ENABLE, r12 /* MPAT2 */ + ldsr r12, 10, 6 + mov MPAT_SW_SR_ENABLE, r12 /* MPAT3 */ + ldsr r12, 14, 6 + mov MPRC_E3_TO_E0_ENABLE, r12 /* MPRC */ + ldsr r12, 1, 5 + mov MPM_SVP_MPE_ENABLE, r12 /* MPM */ + ldsr r12, 0, 5 + SYNCM + +/* BSS clear */ + mov ___ghsbegin_bss, r6 + mov ___ghsend_bss, r7 + mov r0, r1 +loop_clear: + st.dw r0, 0[r6] + addi 8, r6, r6 + cmp r7, r6 + bl loop_clear + +/* Set canary before jump another function. */ +/* Don't call functions before calling __ghs_set_stack_chk_guard. */ + jarl ___ghs_set_stack_chk_guard, lp + + mov _loader_main, r2 + jarl [r2], lp + +/* Release MPU setting */ + mov MPM_ALL_DISABLE, r12 + ldsr r12, 0, 5 /* MPM */ + ldsr zero, 1, 5 /* MPRC */ + mov MPAT_ALL_DISABLE, r12 + ldsr r12, 2, 6 /* MPAT0 */ + ldsr r12, 6, 6 /* MPAT1 */ + ldsr r12, 10, 6 /* MPAT2 */ + ldsr r12, 14, 6 /* MPAT3 */ + ldsr zero, 0, 6 /* MPLA0 */ + ldsr zero, 1, 6 /* MPUA0 */ + ldsr zero, 4, 6 /* MPLA1 */ + ldsr zero, 5, 6 /* MPUA1 */ + ldsr zero, 8, 6 /* MPLA2 */ + ldsr zero, 9, 6 /* MPUA2 */ + ldsr zero, 12, 6 /* MPLA3 */ + ldsr zero, 13, 6 /* MPUA3 */ + SYNCM + + jmp [r10] + nop + halt + + .section ".padding" + .align 4 diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_common.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_common.c new file mode 100644 index 0000000..35b8412 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_common.c @@ -0,0 +1,265 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main common function + ******************************************************************************/ +/****************************************************************************** + * @file loader_main_common.c + * - Version : 0.04 + * @brief 1.Output boot message. + * 2.Judge boot mode. + * 3.Set BL31 parameter. + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.04.2022 0.01 First Release + * : 04.04.2023 0.02 Removed stdio.h. + * : 21.08.2023 0.03 Add support for V4M. + * : 19.09.2023 0.04 Add log output for build option LSI. + *****************************************************************************/ + +#include +#include /* NULL pointer */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RST_MODEMR0_MD5 (0x00000020U) + +/* Define for Work Around of APMU */ +#define CL0GRP3_BIT (1U << 3) +#define CL1GRP3_BIT (1U << 7) +#define RTGRP3_BIT (1U << 19) +#define APMU_ACC_ENB_FOR_ARM_CPU (CL0GRP3_BIT | CL1GRP3_BIT | RTGRP3_BIT) + +static void judge_bootmode(uint32_t lcs); + +/* global variable */ +uint32_t is_verify = SECURE_BOOT; + +static void judge_bootmode(uint32_t lcs) +{ + uint32_t md; + + /* LCS Status check */ + if((lcs != LCS_CM) + && (lcs != LCS_DM) + && (lcs != LCS_SD) + && (lcs != LCS_SE) + && (lcs != LCS_FA)) + { + ERROR("LCS state error." + "LCS = 0x%x", lcs); + panic; + } + + md = (mem_read32(RST_MODEMR0) & RST_MODEMR0_MD5) >> 5U; + if (lcs == LCS_SE) + { + /* LCS=SE => Secure boot */ + is_verify = SECURE_BOOT; + } + else if ((lcs != LCS_SD) && (md == 0U)) + { + /* LCS=CM/DM/FA and MD5=0 => Secure boot */ + is_verify = SECURE_BOOT; + } + else + { + /* LCS=SD or MD5=1 => Normal boot */ + is_verify = NORMAL_BOOT; + } + + if (NORMAL_BOOT != is_verify) + { + NOTICE("Secure boot(ICUMX)\n"); + } + else + { + NOTICE("Normal boot(ICUMX)\n"); + } +} +/* End of function judge_bootmode(uint32_t lcs) */ + +void print_boot_msg(void) +{ + uint32_t lcs = 0U; /* store LCS state */ + uint32_t lcs_size = sizeof(lcs); + uint32_t prr; + uint32_t reg; /* store register value */ + uint32_t ret; /* store return value */ + __attribute__((__unused__)) const char *str; + __attribute__((__unused__)) const char *product_s4 = "S4"; + __attribute__((__unused__)) const char *product_v4h = "V4H"; + __attribute__((__unused__)) const char *product_v4m = "V4M"; + __attribute__((__unused__)) const char *unknown = "unknown"; + __attribute__((__unused__)) const char *boot_hyper160 = "HyperFlash(160MHz)"; + __attribute__((__unused__)) const char *boot_hyper80 = "HyperFlash(80MHz)"; + __attribute__((__unused__)) const char *boot_qspi40 = "QSPI Flash(40MHz)"; + __attribute__((__unused__)) const char *boot_emmc50x8 = "eMMC(50MHz x8)"; + const char *lcs_name[8U] = { + [LCS_CM] = "CM", + [LCS_DM] = "DM", + [LCS_SD] = "SD", + [LCS_SE] = "SE", + [LCS_FA] = "FA", + }; + + NOTICE("ICUMX Loader Rev.%s\n", IPL_VERSION); + + NOTICE("LSI=%d (Build Option : S4=0, V4H=1, V4M=2)\n", RCAR_LSI); + + NOTICE("%s\n", build_message); + + /* Get PRR */ + prr = mem_read32(PRR); + prr &= (PRR_PRODUCT_MASK | PRR_MAJOR_MASK | PRR_MINOR_MASK); + switch (prr & PRR_PRODUCT_MASK) + { + case PRR_PRODUCT_S4: + { + str = product_s4; + break; + } + case PRR_PRODUCT_V4H: + { + str = product_v4h; + break; + } + case PRR_PRODUCT_V4M: + { + str = product_v4m; + break; + } + default: + { + str = unknown; + break; + } + } + NOTICE("PRR is R-Car %s Ver%d.%d\n", str, + ((prr & PRR_MAJOR_MASK) >> PRR_MAJOR_SHIFT) + PRR_MAJOR_OFFSET, + (prr & PRR_MINOR_MASK)); + + reg = mem_read32(RST_MODEMR0); + reg &= RST_MODEMR0_BOOT_DEV_MASK; + + switch (reg) + { + case RST_MODEMR0_BOOT_DEV_HYPERFLASH160: + { + str = boot_hyper160; + break; + } + case RST_MODEMR0_BOOT_DEV_HYPERFLASH80: + { + str = boot_hyper80; + break; + } + case RST_MODEMR0_BOOT_DEV_QSPI_FLASH40: + { + str = boot_qspi40; + break; + } + case RST_MODEMR0_BOOT_DEV_EMMC_50X8: + { + str = boot_emmc50x8; + break; + } + default: + { + str = unknown; + break; + } + } + NOTICE("Boot device is %s\n", str); +#if (QSPI_DDR_MODE==1) + NOTICE("Change QSPI DDR Transfer mode(Quad I/O 80MHz)\n"); +#endif + + /* Get LCS state */ + ret = call_ROM_GetLcs(&lcs, lcs_size); + str = unknown; + if (ret == ROMAPI_OK) + { + if (NULL != lcs_name[lcs]) + { + str = lcs_name[lcs]; + } + } + NOTICE("LCM state is %s\n", str); + + /* If PRR is S4 Ver.1.0 */ + if ((PRR_PRODUCT_S4 == (prr & PRR_PRODUCT_MASK)) && (0U == (prr & PRR_CUT_MASK))) + { + set_sicremap_s4v10(); /* downgrade SICREMAP setting. */ + is_verify = NORMAL_BOOT;/* S4 Ver.1.0 is Normal Boot only. */ + } + else + { + /* LCS judgement for secure boot */ + judge_bootmode(lcs); + } + +#if (SET_FCPR_PARAM == FCPR_ENABLE) + NOTICE("Data Compression Enable\n"); + NOTICE("Start address = 0x%08x End address = 0x%08x\n", COMPRESSION_START_ADDR, COMPRESSION_END_ADDR); +#endif + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + NOTICE("Access protection Enable\n"); +#endif +} +/* End of function print_boot_msg(void) */ + +/* Work Around setting for APMU */ +void wa_setting_apmu(void) +{ + uint32_t apmu_tmp; + + /* Work Around setting for D0_ACCENR-DOMAIN3_ACCENR */ + apmu_tmp = mem_read32(APMU_D0_ACCENR); + apmu_tmp |= APMU_ACC_ENB_FOR_ARM_CPU; + apmu_reg_write(APMU_D0_ACCENR, apmu_tmp); + + apmu_tmp = mem_read32(APMU_D1_ACCENR); + apmu_tmp |= APMU_ACC_ENB_FOR_ARM_CPU; + apmu_reg_write(APMU_D1_ACCENR, apmu_tmp); + + apmu_tmp = mem_read32(APMU_D2_ACCENR); + apmu_tmp |= APMU_ACC_ENB_FOR_ARM_CPU; + apmu_reg_write(APMU_D2_ACCENR, apmu_tmp); + + apmu_tmp = mem_read32(APMU_D3_ACCENR); + apmu_tmp |= APMU_ACC_ENB_FOR_ARM_CPU; + apmu_reg_write(APMU_D3_ACCENR, apmu_tmp); +} +/* End of function wa_setting_apmu(void) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_s4.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_s4.c new file mode 100644 index 0000000..2d556af --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_s4.c @@ -0,0 +1,490 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main function + ******************************************************************************/ +/****************************************************************************** + * @file loader_main.c + * - Version : 0.15 + * @brief 1. IP initialization. + * 2. DMA transfer the binary image from Flash to RAM. + * 3. Authentication of the transferred image. + * 4. Boot CR and CA core. + * 5. Release of used resources. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Modify macro definition name. + * Add process to call rpc_release function. + * : 30.09.2021 0.03 Support of eMMC boot. + * : 15.10.2021 0.04 Modified the MCU boot sequence. + * remove include of Flash/eMMC. + * : 03.12.2021 0.05 Add RT-VRAM extend mode. + * : CA IPL boot support + * : 06.01.2022 0.06 Support for two-stage boot of G4MH + * : Add the Reset mask release process for RWDT. + * : Add exception handling for ICUMX_WDTA. + * : 20.01.2022 0.07 Capture DDR rev.0.02rc11 + * Add ICUMX name unification. + * : 28.02.2022 0.08 Modify the process of setting the parameters + * used by BL31 in IPL. + * : 14.04.2022 0.09 Fixed Set SDCLK to 200MHz. + * : 23.05.2022 0.10 Integration of S4 and V4H + * Renamed from loader_main.c to loader_main_s4.c. + * : 04.07.2022 0.11 Change loading Control Domain process to + * calling load_main_for_mcu() function. + * : 05.08.2022 0.12 Add authentication of software minimum + * version table. + * : 30.09.2022 0.13 Modify pre-process pranch in load_main_for_mcu + * function. + * Modify authentication process of software + * minimum version. + * : 12.01.2023 0.14 Modified argument to fixed + * when calls smoni_set_param() function. + * Modified processing sequence for Access + * protection. + * : 04.04.2023 0.15 Removed stdio.h. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Provided code */ +#include "../ip/ddr/boot_init_dram.h" +# if (ECC_ENABLE == 1) + #include "../ip/ddr/s4/lpddr4x/ecc_enable_s4.h" +# endif + +#define CA_IPL (0U) +#define BL31 (1U) + +#define WDTRSTCR_RWDT_RSTMSK ((uint32_t)1U << 0U) +#define WDTRSTCR_PASSWORD (0xA55A0000U) + +/* flag of set BL31 parameter*/ +#define CA_APP_SET_PARAM_ENABLE (1U) +/* Calculation set address for BL31 parameter */ +#define SMONI_IPL_PARAM_OFFSET (0x00022200U) +#define SMONI_EP_INFO_OFFSET (SMONI_IPL_PARAM_OFFSET + 0x0030U) +#define OPTEE_EP_INFO_OFFSET (SMONI_IPL_PARAM_OFFSET + 0x0088U) +#define BL31_KIND_BOOT_ADDR (SMONI_IPL_PARAM_OFFSET + 0x0D00U) +/* KIND BOOT flag*/ +#define BL31_COLD_BOOT (0x0000000000000000U) +#define BL31_WARM_BOOT (0x0000000000000001U) +#define SMONI_KIND_BOOT_PARAM (0xFFFFFFFFFFFFFFFFU) +/* Program top address of Secure Monitor(BL31), OP-TEE and u-boot. */ +#define SMONI_PHYS_TOP_ADDR (0x46400000U) +#define OPTEE_PHYS_TOP_ADDR (0x44100000U) +#define UBOOT_PHYS_TOP_ADDR (0x50000000U) + +/* struct */ +typedef struct{ + uint8_t uctype; + uint8_t ucversion; + uint16_t ussize; + uint32_t uiattr; + uint32_t psecmonimageinfo_low; + uint32_t psecmonimageinfo_high; + uint32_t psecoptepinfo_low; + uint32_t psecoptepinfo_high; + uint32_t psecoptimageinfo_low; + uint32_t psecoptimageinfo_high; + uint32_t pnonsecepinfo_low; + uint32_t pnonsecepinfo_high; + uint32_t pnonsecimageinfo_low; + uint32_t pnonsecimageinfo_high; +}st_smoni_iplparams_t; + +typedef struct{ + uint8_t uctype; + uint8_t ucversion; + uint16_t ussize; + uint32_t uiattr; + uint32_t ulpc_low; + uint32_t ulpc_high; + uint32_t ulspsr_low; + uint32_t ulspsr_high; + uint32_t ularg0_low; + uint32_t ularg0_high; + uint32_t ularg1_low; + uint32_t ularg1_high; + uint32_t ularg2_low; + uint32_t ularg2_high; + uint32_t ularg3_low; + uint32_t ularg3_high; + uint32_t ularg4_low; + uint32_t ularg4_high; + uint32_t ularg5_low; + uint32_t ularg5_high; + uint32_t ularg6_low; + uint32_t ularg6_high; + uint32_t ularg7_low; + uint32_t ularg7_high; +}st_smoni_entrypointinfo_t; + +static void load_main_for_mcu(const LOAD_INFO *li, uint32_t is_verify); +static void smoni_set_param(uint32_t smoni_entry_point, + uint32_t tee_entry_point, + uint32_t uboot_entry_point); + +static void load_main_for_mcu(const LOAD_INFO *li); + +#if ((CR_SECURE_DEBUG == SECURE_DEBUG_ENABLE) || (ADD_HOTPLUG_MAGIC == ADD_MAGIC_NUMBER)) +#define HOTPLUG_MAGIC_NUM (0x853F912EU) +#else +#define HOTPLUG_MAGIC_NUM (0x00000000U) +#endif +__attribute__ ((section (".cr_hot_plug_magic"))) const uint32_t magic_num[4] = {0x00000000U, 0x00000000U, + 0x00000000U, HOTPLUG_MAGIC_NUM}; + +uint32_t loader_main(void) +{ + uint32_t reg; /* store register value */ + int32_t result; /* store result of ddr_init() */ + uint32_t is_verify = SECURE_BOOT; + uint32_t boot_ca_id; + uint32_t auth_count = 0U; + __attribute__((__unused__)) uint32_t loop = 0U; + __attribute__((__unused__)) uint32_t ca_load_num; /* number of load for Optional CA program */ + LOAD_INFO li[MAX_PLACED] = {0U}; + + +/***************************************************************************** + * Initialize Hardware + *****************************************************************************/ + /* IP initialize */ + ip_init(); + + /* Unmask the detection of RWDT overflow */ + reg = mem_read32(RST_WDTRSTCR); + reg &= ~WDTRSTCR_RWDT_RSTMSK; + reg |= WDTRSTCR_PASSWORD; + mem_write32(RST_WDTRSTCR, reg); + +# if (ECC_ENABLE == 1) +/***************************************************************************** + * ECC and EDC Initialize + *****************************************************************************/ + ecc_rtsram_enable(); + edc_axi_enable(); + edc_vram_enable(); +#endif + +/***************************************************************************** + * Work Around for APMU + *****************************************************************************/ + wa_setting_apmu(); + +/***************************************************************************** + * Output boot message + *****************************************************************************/ + is_verify =print_boot_msg(); + +/***************************************************************************** + * Setting Access protection + *****************************************************************************/ + /* Region ID access protection */ + rgid_protection(); + ram_protection(); + + /* Change the Region ID (Master) of the Module used for data transfer to a temporary setting. */ + set_master_rgid_4_tfr_mod(); + +/***************************************************************************** + * Load Certficate from QSPI + *****************************************************************************/ + /* Load content certificate */ + ca_load_num = load_content_cert(); + + /* Get load information */ + load_init(li); + +/***************************************************************************** + * Authenticate Software minimum version table + *****************************************************************************/ + auth_min_ver_tbl(is_verify, li); + +/***************************************************************************** + * Load Control Domain + *****************************************************************************/ + load_main_for_mcu(li, is_verify); + +/***************************************************************************** + * DDR Initialization + *****************************************************************************/ + + /* DDR initialize */ + result = InitDram(); + if (INITDRAM_OK != result) + { + ERROR("Failed to DRAM initialize (%d).\n", result); + panic; + } + +#if (ECC_ENABLE == 1) + /* ECC Protection */ + enable_ecc(); +#endif /* ECC_ENABLE */ + + /* QoS configuration */ + qos_init(); + + /* RT-VRAM Extend mode */ + rtvram_extendmode(); + +/***************************************************************************** + * Load RTOS from Flash + *****************************************************************************/ + /* Start loading RTOS image from Flash into SDRAM */ + load_image(&li[RTOS_ID]); + + /* finish loading RTOS */ + load_end(); + + +/***************************************************************************** + * Load Cx IPL from Flash + *****************************************************************************/ +#if (CA_LOAD_TYPE == CA_IPL) + /* Start loading Cx IPL image from Flash into SDRAM */ + load_image(&li[CA_PROGRAM_ID]); + + /* Authenticate of RTOS */ + rom_secureboot(is_verify, &li[RTOS_ID]); + + /* boot CR */ + arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr); + + /* The CA image to boot is CA IPL. */ + boot_ca_id = CA_PROGRAM_ID; + + /* finish loading Cx IPL */ + load_end(); +#elif (CA_LOAD_TYPE == BL31) + /* Authenticate of RTOS */ + rom_secureboot(is_verify, &li[RTOS_ID]); + + /* boot CR */ + arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr); + + /* The CA image to boot is CA prgram#1. */ + boot_ca_id = CA_OPTIONAL_ID; + +/***************************************************************************** + * Load CA Program#1--#8 from Flash + *****************************************************************************/ + /* Start loading CA Program#n image from Flash into SDRAM */ + for (loop = 0U; loop < ca_load_num; loop++) + { + /* Loading start */ + load_image(&li[boot_ca_id + loop]); + + /* Authenticate of CA Program#n-1 */ + if (loop != 0U) + { + rom_secureboot(is_verify, &li[boot_ca_id + loop - 1U]); + auth_count++; + } + + /* finish loading CA Program#n */ + load_end(); + } +#endif /* (CA_LOAD_TYPE == CA_IPL) */ +/***************************************************************************** + * Load Secure Firmware from Flash + *****************************************************************************/ + /* Start loading Secure FW image from Flash into SDRAM */ + load_image(&li[SECURE_FW_ID]); + + /* Authenticate of Cx IPL or CA Program#n */ + rom_secureboot(is_verify, &li[boot_ca_id + auth_count]); + + /* Set Secure Monitor parameter */ + smoni_set_param(SMONI_PHYS_TOP_ADDR, /* BL31 */ + OPTEE_PHYS_TOP_ADDR, /* OP-TEE */ + UBOOT_PHYS_TOP_ADDR); /* U-Boot */ + + /* boot CA */ + arm_cpu_on(RCAR_PWR_TARGET_CA, li[boot_ca_id].boot_addr); + + /* finish loading Secure Firmware */ + load_end(); + + /* load_secure data(for ICUMXB) */ + load_securedata(SECURE_FW_ID); + + /* Authenticate of Secure Firmware */ + rom_secureboot(is_verify, &li[SECURE_FW_ID]); + + /* finish loading secure data */ + load_end(); + + /* Finally Protection setting */ + ram_protection_final(); + rgid_protection_final(); + +#if (ECC_ENABLE == 1) + /* Notice the ecc enable */ + NOTICE("Enabled ECC and EDC for RT-SRAM, AXI, VRAM, SDRAM. \n"); +# endif + NOTICE("Load finish.\n"); + ip_release(); + + return remap_get_remap_addr(li[SECURE_FW_ID].boot_addr); +} +/* End of function loader_main(void) */ + +static void load_main_for_mcu(const LOAD_INFO *li, uint32_t is_verify) +{ +#if (BOOT_MCU != 0U) + mcu_load_main(li, is_verify); +#endif /* (BOOT_MCU != 0U) */ +} +/* End of function load_main_for_mcu(const LOAD_INFO *li, uint32_t is_verify) */ + +static void smoni_set_param(uint32_t smoni_entry_point, + uint32_t tee_entry_point, + uint32_t uboot_entry_point) +{ +#if (SET_CA_PARAM == CA_APP_SET_PARAM_ENABLE) + uint32_t mapped_addr; + st_smoni_iplparams_t *smoni_ipl_param; + st_smoni_entrypointinfo_t *smoni_ep_info; + st_smoni_entrypointinfo_t *optee_ep_info; + + remap_register(smoni_entry_point, &mapped_addr); + + /* set struct address */ + smoni_ipl_param = (st_smoni_iplparams_t *) + (mapped_addr + SMONI_IPL_PARAM_OFFSET); + smoni_ep_info = (st_smoni_entrypointinfo_t *) + (mapped_addr + SMONI_EP_INFO_OFFSET); + optee_ep_info = (st_smoni_entrypointinfo_t *) + (mapped_addr + OPTEE_EP_INFO_OFFSET); + + + + /* set parameter */ + smoni_ipl_param->uctype = 0x03U; + smoni_ipl_param->ucversion = 0x01U; + smoni_ipl_param->ussize = 0x0030U; + smoni_ipl_param->uiattr = 0x00000000U; + smoni_ipl_param->psecmonimageinfo_low = 0x00000000U; + smoni_ipl_param->psecmonimageinfo_high = 0x00000000U; + smoni_ipl_param->psecoptepinfo_low = 0x00000000U; + smoni_ipl_param->psecoptepinfo_high = 0x00000000U; + smoni_ipl_param->psecoptimageinfo_low = 0x00000000U; + smoni_ipl_param->psecoptimageinfo_high = 0x00000000U; + smoni_ipl_param->pnonsecepinfo_low = + remap_get_phys_addr((uint32_t)smoni_ep_info); + smoni_ipl_param->pnonsecepinfo_high = 0x00000000U; + smoni_ipl_param->pnonsecimageinfo_low = 0x00000000U; + smoni_ipl_param->pnonsecimageinfo_high = 0x00000000U; + + smoni_ep_info->uctype = 0x01U; + smoni_ep_info->ucversion = 0x01U; + smoni_ep_info->ussize = 0x0058U; /* structure size */ + smoni_ep_info->uiattr = 0x00000001U; /* SECURE */ + smoni_ep_info->ulpc_low = uboot_entry_point; + smoni_ep_info->ulpc_high = 0x00000000U; + /* SPSR_EL3.E[9] = b1 (BigEndian) * + * .A[8] = b1 (DataAbort MASK) * + * .I[7] = b1 (IRQ MASK) * + * .F[6] = b1 (FIQ MASK) * + * .M[4] = b0 (AArcch64) * + * .M[3:1] = b0101 (EL1h) */ + smoni_ep_info->ulspsr_low = 0x000003C5U; + smoni_ep_info->ulspsr_high = 0x00000000U; + smoni_ep_info->ularg0_low = 0x00000000U; + smoni_ep_info->ularg0_high = 0x00000000U; + smoni_ep_info->ularg1_low = 0x00000000U; + smoni_ep_info->ularg1_high = 0x00000000U; + smoni_ep_info->ularg2_low = 0x00000000U; + smoni_ep_info->ularg2_high = 0x00000000U; + smoni_ep_info->ularg3_low = 0x00000000U; + smoni_ep_info->ularg3_high = 0x00000000U; + smoni_ep_info->ularg4_low = 0x00000000U; + smoni_ep_info->ularg4_high = 0x00000000U; + smoni_ep_info->ularg5_low = 0x00000000U; + smoni_ep_info->ularg5_high = 0x00000000U; + smoni_ep_info->ularg6_low = 0x00000000U; + smoni_ep_info->ularg6_high = 0x00000000U; + smoni_ep_info->ularg7_low = 0x00000000U; + smoni_ep_info->ularg7_high = 0x00000000U; + + optee_ep_info->uctype = 0x01U; + optee_ep_info->ucversion = 0x02U; + optee_ep_info->ussize = 0x0058U; + optee_ep_info->uiattr = 0x00000008U; + optee_ep_info->ulpc_low = tee_entry_point; + optee_ep_info->ulpc_high = 0x00000000U; + optee_ep_info->ulspsr_low = 0x000003C5U; + optee_ep_info->ulspsr_high = 0x00000000U; + optee_ep_info->ularg0_low = 0x00000000U; + optee_ep_info->ularg0_high = 0x00000000U; + optee_ep_info->ularg1_low = 0x00000000U; + optee_ep_info->ularg1_high = 0x00000000U; + optee_ep_info->ularg2_low = 0x00000000U; + optee_ep_info->ularg2_high = 0x00000000U; + optee_ep_info->ularg3_low = 0x00000000U; + optee_ep_info->ularg3_high = 0x00000000U; + optee_ep_info->ularg4_low = 0x00000000U; + optee_ep_info->ularg4_high = 0x00000000U; + optee_ep_info->ularg5_low = 0x00000000U; + optee_ep_info->ularg5_high = 0x00000000U; + optee_ep_info->ularg6_low = 0x00000000U; + optee_ep_info->ularg6_high = 0x00000000U; + optee_ep_info->ularg7_low = 0x00000000U; + optee_ep_info->ularg7_high = 0x00000000U; + + mapped_addr += BL31_KIND_BOOT_ADDR; + mem_write32((mapped_addr), (uint32_t)((uint64_t)BL31_COLD_BOOT & 0xFFFFFFFFU)); + mem_write32(((mapped_addr) + 0x4U), + (uint32_t)(((uint64_t)BL31_COLD_BOOT >> 32U) & 0xFFFFFFFFU)); + + remap_unregister(mapped_addr); +#endif /* (SET_CA_PARAM == CA_APP_SET_PARAM_ENABLE) */ +} +/* End of function smoni_set_param(uint32_t smoni_entry_point) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_v4h.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_v4h.c new file mode 100644 index 0000000..60d24dc --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_v4h.c @@ -0,0 +1,460 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main function for V4H + ******************************************************************************/ +/****************************************************************************** + * @file loader_main.c + * - Version : 0.14 + * @brief 1. IP initialization. + * 2. DMA transfer the binary image from Flash to RAM. + * 3. Authentication of the transferred image. + * 4. Boot CR and CA core. + * 5. Release of used resources. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Modify macro definition name. + * Add process to call rpc_release function. + * : 30.09.2021 0.03 Support of eMMC boot. + * : (30.11.2021 0.04) Support boot sequence of V4H. + * : 03.12.2021 0.05 Add RT-VRAM extend mode. + * : 23.05.2022 0.06 Integration of S4 and V4H + * Renamed from loader_main.c to loader_main_v4h.c. + * : 05.08.2022 0.07 Add authentication of software minimum + * version table. + * : 30.09.2022 0.08 Modify authentication process of software + * minimum version. + * : 20.01.2023 0.09 Add W/A OTLINT-5556: increased latency + * : 17.04.2023 0.10 Add setting for V4H v2.x leak current reduce + * Removed stdio.h. + * Add certificate authentication functions to be + * execute before image transfer. + * : 15.05.2023 0.11 Change the jump address of secure firmware from + * on SIC remap area to CF remap area. + * : 13.06.2024 0.12 Updated ECM register setting in wa_for_v4h2 + * function. + * : 27.12.2024 0.13 Change the location of ECC and EDC + * initialization function. + * : 07.04.2025 0.14 Added ecm_init_setting function calling. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rcar_def.h" +#if (ECM_ERROR_ENABLE == 1) +#include "../ip/ddr/v4h/lpddr5/ecm_enable_v4h.h" +#endif /* ECM_ERROR_ENABLE == 1 */ + +/* Provided code */ +#include "../ip/ddr/boot_init_dram.h" +#include "../ip/ddr/v4h/lpddr5/ecc_enable_v4h.h" +#include + +#define ICISTP_BASE (BASE_ICISTP_ADDR) +#define ICISTPSTPER000 (ICISTP_BASE + 0x30300U) + +#define EDC_BASE (BASE_ECM_ADDR) +#define EDCSTRT20 (EDC_BASE + 0x80C0U) +#define TIDSTRT20 (EDC_BASE + 0x81C0U) + +/* SYSC register */ +#define SYSC_BASE (BASE_SYSC_ADDR) +#define SYSC_SYSCSR (SYSC_BASE + 0x0000U) /* SYSC Status Register */ +#define SYSC_SYSCISCR1 (SYSC_BASE + 0x0814U) /* Interrupt Status/Clear Register1 */ +#define SYSC_SYSCIER1 (SYSC_BASE + 0x0824U) /* Interrupt Enable Register1 */ +#define SYSC_SYSCIMR1 (SYSC_BASE + 0x0834U) /* Interrupt MASK Register1 */ + +/* Power Domain Register */ +#define SYSC_PDR41 (0x0A40U) /* A1CNN0 */ +#define SYSC_PDR42 (0x0A80U) /* A2CN0 */ +#define SYSC_PDR43 (0x0AC0U) /* A3IR */ +#define SYSC_PDRSR (SYSC_BASE + 0x1000U) /* Base address of Power Domain Status Register */ +#define SYSC_PDRSR41 (SYSC_PDRSR + (SYSC_PDR41)) +#define SYSC_PDRSR42 (SYSC_PDRSR + (SYSC_PDR42)) +#define SYSC_PDRSR43 (SYSC_PDRSR + (SYSC_PDR43)) +#define SYSC_PDRONCR (SYSC_BASE + 0x1004U) /* Base address of Power Domain Power-ON Control Register */ +#define SYSC_PDRONCR41 (SYSC_PDRONCR + (SYSC_PDR41)) +#define SYSC_PDRONCR42 (SYSC_PDRONCR + (SYSC_PDR42)) +#define SYSC_PDRONCR43 (SYSC_PDRONCR + (SYSC_PDR43)) + +#define PDR_MAX (3U) /* Number of PDR's to be set */ +#define SYSC_BIT_PDR41 (0x00000200U) /* SYSC register target PDR41 bit */ +#define SYSC_BIT_PDR42 (0x00000400U) /* SYSC register target PDR42 bit */ +#define SYSC_BIT_PDR43 (0x00000800U) /* SYSC register target PDR43 bit */ + +#define SYSCSR_BUSY_MASK (0x00000003U) /* SYSC Power On or Power Off seaquence status */ +#define SYSCSR_NOT_BUSY (0x00000003U) /* Not processing */ + +#define SYSC_PDRSR_PWR_MASK (0x00001111U) /* PDR Power On / Off Status MASK */ +#define SYSC_PDRSR_PWROFF (0x00000001U) /* PDR Power OFF Status */ +#define SYSC_PDRONCR_PWRON (0x00000001U) /* PDR Power On request */ +#define SYSC_PDR_PWR_PROC (0x00000000U) /* PDR Power On or Poweer off processing */ + +/* struct */ +typedef struct{ + uint8_t uctype; + uint8_t ucversion; + uint16_t ussize; + uint32_t uiattr; + uint32_t psecmonimageinfo_low; + uint32_t psecmonimageinfo_high; + uint32_t psecoptepinfo_low; + uint32_t psecoptepinfo_high; + uint32_t psecoptimageinfo_low; + uint32_t psecoptimageinfo_high; + uint32_t pnonsecepinfo_low; + uint32_t pnonsecepinfo_high; + uint32_t pnonsecimageinfo_low; + uint32_t pnonsecimageinfo_high; +}st_smoni_iplparams_t; + +typedef struct{ + uint8_t uctype; + uint8_t ucversion; + uint16_t ussize; + uint32_t uiattr; + uint32_t ulpc_low; + uint32_t ulpc_high; + uint32_t ulspsr_low; + uint32_t ulspsr_high; + uint32_t ularg0_low; + uint32_t ularg0_high; + uint32_t ularg1_low; + uint32_t ularg1_high; + uint32_t ularg2_low; + uint32_t ularg2_high; + uint32_t ularg3_low; + uint32_t ularg3_high; + uint32_t ularg4_low; + uint32_t ularg4_high; + uint32_t ularg5_low; + uint32_t ularg5_high; + uint32_t ularg6_low; + uint32_t ularg6_high; + uint32_t ularg7_low; + uint32_t ularg7_high; +}st_smoni_entrypointinfo_t; + +#define RGID_SET_RGID_FIN_FLG_ADDR (0xFD95EFFCU) /* 0xE635EFFC:Remap 12 */ +#define RGID_SET_RGID_FIN_FLG_VAL (0x64U) + + +#if (ADD_HOTPLUG_MAGIC == ADD_MAGIC_NUMBER) +#define HOTPLUG_MAGIC_NUM (0x853F912EU) +#else +#define HOTPLUG_MAGIC_NUM (0x00000000U) +#endif +__attribute__ ((section (".cr_hot_plug_magic"))) const uint32_t magic_num[4] = {0x00000000U, 0x00000000U, + 0x00000000U, HOTPLUG_MAGIC_NUM}; + +/* Prototype functions */ +static void wa_for_v4h2(void); +static void set_leak_current_reduce_for_v4h2x(void); + + +uint32_t loader_main(void) +{ + uint32_t boot_ca_id; + uint32_t auth_count = 0U; + uint32_t boot_cpu; + uint32_t tmp; + __attribute__((__unused__)) uint32_t loop = 0U; + __attribute__((__unused__)) uint32_t ca_load_num; /* number of load for Optional CA program */ + LOAD_INFO li[MAX_PLACED] = {0U}; + + +/***************************************************************************** + * Initialize Hardware + *****************************************************************************/ + /* IP initialize */ + ip_init(); + +#if (ECM_ERROR_ENABLE == 1) + ecm_init_setting(); +#endif /* ECM_ERROR_ENABLE == 1 */ +/***************************************************************************** + * Work Around for APMU + *****************************************************************************/ + wa_setting_apmu(); + +/***************************************************************************** + * Output boot message + *****************************************************************************/ + print_boot_msg(); + +/***************************************************************************** + * WA for V4H ver2.0 + *****************************************************************************/ + uint32_t Prr_Cut; + Prr_Cut = mem_read32(PRR) & PRR_CUT_MASK; + + if (Prr_Cut >= PRR_PRODUCT_20) + { + /* IPL setting for V4H v2.x leak current reduce */ + set_leak_current_reduce_for_v4h2x(); + + wa_for_v4h2(); + } + + /* WA OTLINT-5556 increased latency: APMU FRSTCTRL bit[29] disable */ + tmp = mem_read32(BASE_APMU_ADDR + 0x68U); + tmp = tmp & ~(1 << 29); + mem_write32((BASE_APMU_ADDR + 0x68U), tmp); + +#if (ECM_ENABLE == 1) +/***************************************************************************** + * ECC and EDC Initialize + *****************************************************************************/ + edc_axi_enable(); + edc_vram_enable(); +#endif + +/***************************************************************************** + * Setting Access protection + *****************************************************************************/ + /* Region ID access protection */ + rgid_protection(); + ram_protection(); + + /* Change the Region ID (Master) of the Module used for data transfer to a temporary setting. */ + set_master_rgid_4_tfr_mod(); + +/***************************************************************************** + * Clear ECM Status Bits + *****************************************************************************/ + /* Check the V4H is v1.0 */ + if(Prr_Cut == PRR_PRODUCT_10) + { + clear_ecm_st_axi(); + } + +/***************************************************************************** + * Load Certficate from QSPI + *****************************************************************************/ + /* Load content certificate */ + ca_load_num = load_content_cert(); + + /* Get load information */ + load_init(li); + + /* verify the each content certs before Image load */ + preload_verify_cntcert(li); + +/***************************************************************************** + * Authenticate Software minimum version table + *****************************************************************************/ + auth_min_ver_tbl(li); + +/***************************************************************************** + * Load Cx IPL from Flash + *****************************************************************************/ + /* Start loading Cx IPL image from Flash into SDRAM */ + load_image(&li[CA_PROGRAM_ID]); + + /* The CA image to boot is CA IPL. */ + boot_ca_id = CA_PROGRAM_ID; + + /* boot CPU is CR */ + boot_cpu = RCAR_PWR_TARGET_CR; + + /* finish loading Cx IPL */ + load_end(); +/***************************************************************************** + * Load Secure Firmware from Flash + *****************************************************************************/ + /* Start loading Secure FW image from Flash into SDRAM */ + load_image(&li[SECURE_FW_ID]); + + /* Authenticate of CA Program#n */ + rom_secureboot(&li[boot_ca_id + auth_count]); + + /* SystemRAM has an undefined initial value, clear the address of + * the SystemRAM that is going to store set finish flag of RGID. */ + mem_write8(RGID_SET_RGID_FIN_FLG_ADDR, 0xFFU); + + /* Before Boot CPU, Set the division ratio for CPU operating frequency */ + adj_cr_variant_freq(); + + /* boot CA */ + arm_cpu_on(boot_cpu, li[boot_ca_id].boot_addr); + + /* finish loading Secure Firmware */ + load_end(); + + /* load_secure data(for ICUMXB) */ + load_securedata(SECURE_FW_ID); + + /* Authenticate of Secure Firmware */ + rom_secureboot(&li[SECURE_FW_ID]); + + /* finish loading secure data */ + load_end(); + + /* Finally Protection setting */ + rgid_protection_final(); + + /* set RGID setting finish flag. + * because polling from CX 2nd IPL. */ + mem_write8(RGID_SET_RGID_FIN_FLG_ADDR, RGID_SET_RGID_FIN_FLG_VAL); + +#if (ECM_ENABLE == 1) + /* Notice the ecc enable */ + NOTICE("Enabled EDC for AXI-Bus, RT-VRAM. \n"); +#endif + NOTICE("Load finish.\n"); + ip_release(); + + return get_cfremap_addr(li[SECURE_FW_ID].boot_addr); +} +/* End of function loader_main(void) */ + +void clear_ecm_st_axi(void) +{ + mem_write32(ICISTPSTPER000,0x30U); + mem_write32(EDCSTRT20, 0x10U); + mem_write32(TIDSTRT20, 0x12U); +}/* End of function clear_ecm_st_axi(void) */ + +static void wa_for_v4h2(void) +{ + uint32_t tmp; + + /* 1. Release of pseudo power shutdown */ + /* Process moved to function set_leak_current_reduce_for_v4h2x(). */ + + /* 2. Reset ON for A2CN0 and Reset OFF for A2CN0 */ + tmp = mem_read32(BASE_CPG_ADDR + 0x2C00U); /* Software Reset Register 0 (SRCR0) */ + tmp = tmp | (0x1U << 23U); + mem_write32(CPG_CPGWPR, ~tmp); + mem_write32((BASE_CPG_ADDR + 0x2C00U),tmp); + + tmp = mem_read32(BASE_CPG_ADDR + 0x2C80U); /* Software Reset Clearing Register 0 (SRSTCLR0) */ + tmp = tmp | (0x1U << 23U); + mem_write32(CPG_CPGWPR, ~tmp); + mem_write32((BASE_CPG_ADDR + 0x2C80U),tmp); + + /* Unlock the ECM register protect. */ + mem_write32(ECMWPCNTR, 0xACCE0001); + + /* 3. ECM Enable */ + tmp = mem_read32(BASE_ECM_ADDR + 0x50018U); /* ECM Error Control Register 6 (ECMERRCTLR6) */ + tmp = tmp | (0xfU << 24U); + mem_write32((BASE_ECM_ADDR + 0x50018U),tmp); + + /* Lock the ECM register protect. */ + mem_write32(ECMWPCNTR, 0xACCE0000U); +}/* End of function wa_for_v4h2(void) */ + +static void set_leak_current_reduce_for_v4h2x(void) +{ + uint32_t reg; + const uint32_t pdrsr_tbl[PDR_MAX] = { /* SYSC PDRSR register table */ + SYSC_PDRSR43, /* A3IR */ + SYSC_PDRSR42, /* A2CN0 */ + SYSC_PDRSR41 /* A1CNN0 */ + }; + const uint32_t pdroncr_tbl[PDR_MAX] = { /* SYSC PDRONCR register table */ + SYSC_PDRONCR43, /* A3IR */ + SYSC_PDRONCR42, /* A2CN0 */ + SYSC_PDRONCR41 /* A1CNN0 */ + }; + + /* Power ON / OFF process complete interrupt enable for PDR41-PDR43 */ + reg = mem_read32(SYSC_SYSCIER1); + reg |= (SYSC_BIT_PDR41 | SYSC_BIT_PDR42 | SYSC_BIT_PDR43); + mem_write32(SYSC_SYSCIER1, reg); + INFO("SYSCIER1(0x%08x) = %08x\n",SYSC_SYSCIER1,mem_read32(SYSC_SYSCIER1)); + + /* MASK complete interrupt request to INTC for PDR41-PDR43 */ + reg = mem_read32(SYSC_SYSCIMR1); + reg |= (SYSC_BIT_PDR41 | SYSC_BIT_PDR42 | SYSC_BIT_PDR43); + mem_write32(SYSC_SYSCIMR1, reg); + INFO("SYSCIMR1(0x%08x) = %08x\n",SYSC_SYSCIMR1,mem_read32(SYSC_SYSCIMR1)); + + for(uint32_t loop = 0U; loop < PDR_MAX; loop++) + { + /* Check PDRn Power on state */ + reg = mem_read32(pdrsr_tbl[loop]); + INFO("PDRSR(0x%08x) = %08x\n",pdrsr_tbl[loop],reg); + reg &= SYSC_PDRSR_PWR_MASK; + /* Only when the Power state of PDRn is OFF, the Power On Request is processed */ + if((reg == SYSC_PDRSR_PWROFF) == true) + { + /* Wait until SYSC is in Not busy status */ + do{ + /* Get SYSC processing Power ON / OFF status */ + reg = mem_read32(SYSC_SYSCSR); + INFO("SYSCSR(0x%08x) = %08x\n", SYSC_SYSCSR, reg); + reg &= SYSCSR_BUSY_MASK; + } while((reg == SYSCSR_NOT_BUSY) != true); + + /* PDRn Power ON request */ + mem_write32(pdroncr_tbl[loop], SYSC_PDRONCR_PWRON); + INFO("PDRONCRn(0x%08x) = %08x\n",pdroncr_tbl[loop],mem_read32(pdroncr_tbl[loop])); + + /* Power ON process complete interrupt status for PDR41-PDR43 */ + do{ + reg = mem_read32(SYSC_SYSCISCR1); + INFO("SYSCISCR1(0x%08x) = %08x\n", SYSC_SYSCISCR1, reg); + reg &= (SYSC_BIT_PDR43 >> loop); /* loop = 0:PDR43 1:PDR42 2:PDR41 */ + } while((reg !=SYSC_PDR_PWR_PROC) != true); + + /* Clear Power ON process complete interrupt status for PDR41-PDR43 */ + mem_write32(SYSC_SYSCISCR1, reg); + INFO("SYSCISCR1(0x%08x) = %08x\n",SYSC_SYSCISCR1,mem_read32(SYSC_SYSCISCR1)); + } + } + + /* Power ON / OFF process complete interrupt disable for PDR41-PDR43 */ + reg = mem_read32(SYSC_SYSCIER1); + reg &= ~(SYSC_BIT_PDR41 | SYSC_BIT_PDR42 | SYSC_BIT_PDR43); + mem_write32(SYSC_SYSCIER1, reg); + INFO("SYSCIER1(0x%08x) = %08x\n",SYSC_SYSCIER1,mem_read32(SYSC_SYSCIER1)); + + /* MASK complete interrupt request to INTC for PDR41-PDR43 */ + reg = mem_read32(SYSC_SYSCIMR1); + reg &= ~(SYSC_BIT_PDR41 | SYSC_BIT_PDR42 | SYSC_BIT_PDR43); + mem_write32(SYSC_SYSCIMR1, reg); + INFO("SYSCIMR1(0x%08x) = %08x\n",SYSC_SYSCIMR1,mem_read32(SYSC_SYSCIMR1)); +} diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_v4m.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_v4m.c new file mode 100644 index 0000000..af1ac9c --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/loader/loader_main_v4m.c @@ -0,0 +1,269 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main function for V4M + ******************************************************************************/ +/****************************************************************************** + * @file loader_main_v4m.c + * - Version : 0.04 + * @brief 1. IP initialization. + * 2. DMA transfer the binary image from Flash to RAM. + * 3. Authentication of the transferred image. + * 4. Boot CR and CA core. + * 5. Release of used resources. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + * : 14.11.2023 0.02 Fixed file header path of ECC. + * : 16.11.2023 0.03 Added avs_low_power_mode_setting function + * calling. + * : 07.04.2025 0.04 Added ecm_init_setting function calling. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rcar_def.h" +#if (ECM_ERROR_ENABLE == 1) +#include "../ip/ddr/v4m/lpddr5/ecm_enable_v4m.h" +#endif /* ECM_ERROR_ENABLE == 1 */ + +/* Provided code */ +#include "../ip/ddr/boot_init_dram.h" +#include "../ip/ddr/v4m/lpddr5/ecc_enable_v4m.h" +#include + +#define ICISTP_BASE (BASE_ICISTP_ADDR) +#define ICISTPSTPER000 (ICISTP_BASE + 0x30300U) + +#define EDC_BASE (BASE_ECM_ADDR) +#define EDCSTRT20 (EDC_BASE + 0x80C0U) +#define TIDSTRT20 (EDC_BASE + 0x81C0U) + +/* SYSC register */ +#define SYSC_BASE (BASE_SYSC_ADDR) +#define SYSC_SYSCSR (SYSC_BASE + 0x0000U) /* SYSC Status Register */ +#define SYSC_SYSCISCR1 (SYSC_BASE + 0x0814U) /* Interrupt Status/Clear Register1 */ +#define SYSC_SYSCIER1 (SYSC_BASE + 0x0824U) /* Interrupt Enable Register1 */ +#define SYSC_SYSCIMR1 (SYSC_BASE + 0x0834U) /* Interrupt MASK Register1 */ + +/* Power Domain Register */ +#define SYSC_PDR41 (0x0A40U) /* A1CNN0 */ +#define SYSC_PDR42 (0x0A80U) /* A2CN0 */ +#define SYSC_PDR43 (0x0AC0U) /* A3IR */ +#define SYSC_PDRSR (SYSC_BASE + 0x1000U) /* Base address of Power Domain Status Register */ +#define SYSC_PDRSR41 (SYSC_PDRSR + (SYSC_PDR41)) +#define SYSC_PDRSR42 (SYSC_PDRSR + (SYSC_PDR42)) +#define SYSC_PDRSR43 (SYSC_PDRSR + (SYSC_PDR43)) +#define SYSC_PDRONCR (SYSC_BASE + 0x1004U) /* Base address of Power Domain Power-ON Control Register */ +#define SYSC_PDRONCR41 (SYSC_PDRONCR + (SYSC_PDR41)) +#define SYSC_PDRONCR42 (SYSC_PDRONCR + (SYSC_PDR42)) +#define SYSC_PDRONCR43 (SYSC_PDRONCR + (SYSC_PDR43)) + +#define PDR_MAX (3U) /* Number of PDR's to be set */ +#define SYSC_BIT_PDR41 (0x00000200U) /* SYSC register target PDR41 bit */ +#define SYSC_BIT_PDR42 (0x00000400U) /* SYSC register target PDR42 bit */ +#define SYSC_BIT_PDR43 (0x00000800U) /* SYSC register target PDR43 bit */ + +#define SYSCSR_BUSY_MASK (0x00000003U) /* SYSC Power On or Power Off seaquence status */ +#define SYSCSR_NOT_BUSY (0x00000003U) /* Not processing */ + +#define SYSC_PDRSR_PWR_MASK (0x00001111U) /* PDR Power On / Off Status MASK */ +#define SYSC_PDRSR_PWROFF (0x00000001U) /* PDR Power OFF Status */ +#define SYSC_PDRONCR_PWRON (0x00000001U) /* PDR Power On request */ +#define SYSC_PDR_PWR_PROC (0x00000000U) /* PDR Power On or Poweer off processing */ + +#define RGID_SET_RGID_FIN_FLG_ADDR (0xFD95EFFCU) /* 0xE635EFFC:Remap 12 */ +#define RGID_SET_RGID_FIN_FLG_VAL (0x64U) + + +#if (ADD_HOTPLUG_MAGIC == ADD_MAGIC_NUMBER) +#define HOTPLUG_MAGIC_NUM (0x853F912EU) +#else +#define HOTPLUG_MAGIC_NUM (0x00000000U) +#endif +__attribute__ ((section (".cr_hot_plug_magic"))) const uint32_t magic_num[4] = {0x00000000U, 0x00000000U, + 0x00000000U, HOTPLUG_MAGIC_NUM}; + +uint32_t loader_main(void) +{ + uint32_t boot_ca_id; + uint32_t auth_count = 0U; + uint32_t boot_cpu; + uint32_t tmp; + __attribute__((__unused__)) uint32_t loop = 0U; + __attribute__((__unused__)) uint32_t ca_load_num; /* number of load for Optional CA program */ + LOAD_INFO li[MAX_PLACED] = {0U}; + + +/***************************************************************************** + * Initialize Hardware + *****************************************************************************/ + /* IP initialize */ + ip_init(); + +#if (ECM_ERROR_ENABLE == 1) + ecm_init_setting(); +#endif /* ECM_ERROR_ENABLE == 1 */ + +#if (ECM_ENABLE == 1) +/***************************************************************************** + * ECC and EDC Initialize + *****************************************************************************/ + edc_axi_enable(); + edc_vram_enable(); +#endif + +/***************************************************************************** + * Work Around for APMU + *****************************************************************************/ + wa_setting_apmu(); + +/***************************************************************************** + * Output boot message + *****************************************************************************/ + print_boot_msg(); + +/***************************************************************************** + * Low Power Mode setting for V4M + *****************************************************************************/ + avs_low_power_mode_setting(); + +/***************************************************************************** + * WA for V4M + *****************************************************************************/ + /* WA OTLINT-5556 increased latency: APMU FRSTCTRL bit[29] disable */ + tmp = mem_read32(BASE_APMU_ADDR + 0x68U); + tmp = tmp & ~(1U << 29U); + mem_write32((BASE_APMU_ADDR + 0x68U), tmp); + +/***************************************************************************** + * Setting Access protection + *****************************************************************************/ + /* Region ID access protection */ + rgid_protection(); + ram_protection(); + + /* Change the Region ID (Master) of the Module used for data transfer to a temporary setting. */ + set_master_rgid_4_tfr_mod(); + +/***************************************************************************** + * Load Certficate from QSPI + *****************************************************************************/ + /* Load content certificate */ + ca_load_num = load_content_cert(); + + /* Get load information */ + load_init(li); + + /* verify the each content certs before Image load */ + preload_verify_cntcert(li); + +/***************************************************************************** + * Authenticate Software minimum version table + *****************************************************************************/ + auth_min_ver_tbl(li); + +/***************************************************************************** + * Load Cx IPL from Flash + *****************************************************************************/ + /* Start loading Cx IPL image from Flash into SDRAM */ + load_image(&li[CA_PROGRAM_ID]); + + /* The CA image to boot is CA IPL. */ + boot_ca_id = CA_PROGRAM_ID; + + /* boot CPU is CR */ + boot_cpu = RCAR_PWR_TARGET_CR; + + /* finish loading Cx IPL */ + load_end(); +/***************************************************************************** + * Load Secure Firmware from Flash + *****************************************************************************/ + /* Start loading Secure FW image from Flash into SDRAM */ + load_image(&li[SECURE_FW_ID]); + + /* Authenticate of CA Program#n */ + rom_secureboot(&li[boot_ca_id + auth_count]); + + /* SystemRAM has an undefined initial value, clear the address of + * the SystemRAM that is going to store set finish flag of RGID. */ + mem_write8(RGID_SET_RGID_FIN_FLG_ADDR, 0xFFU); + + /* Before Boot CPU, Set the division ratio for CPU operating frequency */ + adj_cr_variant_freq(); + + /* boot CA */ + arm_cpu_on(boot_cpu, li[boot_ca_id].boot_addr); + + /* finish loading Secure Firmware */ + load_end(); + + /* load_secure data(for ICUMXB) */ + load_securedata(SECURE_FW_ID); + + /* Authenticate of Secure Firmware */ + rom_secureboot(&li[SECURE_FW_ID]); + + /* finish loading secure data */ + load_end(); + + /* Finally Protection setting */ + rgid_protection_final(); + + /* set RGID setting finish flag. + * because polling from CX 2nd IPL. */ + mem_write8(RGID_SET_RGID_FIN_FLG_ADDR, RGID_SET_RGID_FIN_FLG_VAL); + +#if (ECM_ENABLE == 1) + /* Notice the ecc enable */ + NOTICE("Enabled EDC for AXI-Bus, RT-VRAM. \n"); +#endif + NOTICE("Load finish.\n"); + ip_release(); + + return get_cfremap_addr(li[SECURE_FW_ID].boot_addr); +} +/* End of function loader_main(void) */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/codesram_ecc.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/codesram_ecc.c new file mode 100644 index 0000000..bc3c0a2 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/codesram_ecc.c @@ -0,0 +1,228 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Control ECC and Address parity check for CodeSRAM + ******************************************************************************/ + /****************************************************************************** + * @file codesram_ecc.c + * - Version : 0.01 + * @brief 1. Enable / Disable ECC and Address parity check for CodeSRAM. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 19.01.2023 0.01 First Release + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#define CSRM_ECCCTL_EMCA_EN_MOD (0x00004000U) +#define CSRM_ECCCTL_APERR (0x00001000U) +#define CSRM_ECCCTL_ECERVF (0x00000040U) +#define CSRM_ECCCTL_EC1ECP (0x00000020U) +#define CSRM_ECCCTL_ECER2F (0x00000004U) +#define CSRM_ECCCTL_ECER1F (0x00000002U) + +#define CSRM_APCTL_APCEN (0x00000001U) +#define CSRM_NO_ERROR (0x00000000U) + +#define CODESRAM_BUS_NUM_SHIFT (20U) + +void disable_codesram_ecc_parity(uint32_t boot_addr, uint32_t size) +{ + uint32_t loop; + uint32_t bus_num; + uint32_t set_num; + uint32_t reg; + + /* Code-SRAMn ECC Control Register */ + const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL, + MCU_CSRM1ECCCTL, + MCU_CSRM2ECCCTL, + MCU_CSRM3ECCCTL, + MCU_CSRM4ECCCTL, + MCU_CSRM5ECCCTL}; + + /* Code-SRAMn Address Parity Control Register */ + const uint32_t apctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0APCTL, + MCU_CSRM1APCTL, + MCU_CSRM2APCTL, + MCU_CSRM3APCTL, + MCU_CSRM4APCTL, + MCU_CSRM5APCTL}; + + /* Calculate the area used by Code SRAM. */ + bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + + for (loop = 0U; loop < set_num; loop++) + { + /* Disable ECC error detection and error correction for CodeSRAM. */ + reg = mem_read32(eccctl_reg[bus_num + loop]); + reg &= ~(CSRM_ECCCTL_ECERVF); + reg |= CSRM_ECCCTL_EMCA_EN_MOD; + reg |= CSRM_ECCCTL_EC1ECP; + mem_write32(eccctl_reg[bus_num + loop], reg); + /* Disable Address parity check for CodeSRAM. */ + reg = mem_read32(apctl_reg[bus_num + loop]); + reg &= ~(CSRM_APCTL_APCEN); + mem_write32(apctl_reg[bus_num + loop], reg); + } +} +/* End of function disable_codesram_ecc_parity */ + +void enable_codesram_ecc_parity(uint32_t boot_addr, uint32_t size) +{ + uint32_t loop; + uint32_t bus_num; + uint32_t set_num; + uint32_t reg; + + /* Code-SRAMn ECC Control Register */ + const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL, + MCU_CSRM1ECCCTL, + MCU_CSRM2ECCCTL, + MCU_CSRM3ECCCTL, + MCU_CSRM4ECCCTL, + MCU_CSRM5ECCCTL}; + + /* Code-SRAMn Address Parity Control Register */ + const uint32_t apctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0APCTL, + MCU_CSRM1APCTL, + MCU_CSRM2APCTL, + MCU_CSRM3APCTL, + MCU_CSRM4APCTL, + MCU_CSRM5APCTL}; + + /* Calculate the area used by Code SRAM. */ + bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + + for (loop = 0U; loop < set_num; loop++) + { + /* Enable ECC error detection and error correction for CodeSRAM. */ + reg = mem_read32(eccctl_reg[bus_num + loop]); + reg &= ~(CSRM_ECCCTL_EC1ECP); + reg |= CSRM_ECCCTL_ECERVF; + reg |= CSRM_ECCCTL_EMCA_EN_MOD; + mem_write32(eccctl_reg[bus_num + loop], reg); + /* Enable Address parity check for CodeSRAM. */ + reg = mem_read32(apctl_reg[bus_num + loop]); + reg |= CSRM_APCTL_APCEN; + mem_write32(apctl_reg[bus_num + loop], reg); + } +} +/* End of function enable_codesram_ecc_parity */ + +void chk_codesram_ecc_parity(uint32_t boot_addr, uint32_t size) +{ + uint32_t loop; + uint32_t bus_num; + uint32_t set_num; + uint32_t reg; + uint32_t err_chk; + + /* Code-SRAMn ECC Control Register */ + const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL, + MCU_CSRM1ECCCTL, + MCU_CSRM2ECCCTL, + MCU_CSRM3ECCCTL, + MCU_CSRM4ECCCTL, + MCU_CSRM5ECCCTL}; + + /* Calculate the area used by Code SRAM. */ + bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + + /* Check ECC error and Address parity error for CodeSRAM. */ + for (loop = 0U; loop < set_num; loop++) + { + reg = mem_read32(eccctl_reg[bus_num + loop]); + err_chk = reg; + err_chk &= (CSRM_ECCCTL_ECER2F | CSRM_ECCCTL_ECER1F); + if(err_chk != CSRM_NO_ERROR) + { + /* ECC error occurred. */ + ERROR("CodeSRAM ECC error detected !!\n"); + panic; + } + err_chk = reg; + err_chk &= CSRM_ECCCTL_APERR; + if(err_chk != CSRM_NO_ERROR) + { + /* Address parity error occurred. */ + ERROR("CodeSRAM Address parity error detected !!\n"); + panic; + } + } +} +/* End of function chk_codesram_ecc_parity */ + +void initialize_codesram_ecc_parity(uint32_t boot_addr, uint32_t size) +{ + uint32_t loop; + uint32_t bus_num; + uint32_t set_num; + uint32_t reg; + + /* Code-SRAMn ECC Control Register */ + const uint32_t eccctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0ECCCTL, + MCU_CSRM1ECCCTL, + MCU_CSRM2ECCCTL, + MCU_CSRM3ECCCTL, + MCU_CSRM4ECCCTL, + MCU_CSRM5ECCCTL}; + + /* Code-SRAMn Address Parity Control Register */ + const uint32_t apctl_reg[MCU_CSRM_MAX] = { MCU_CSRM0APCTL, + MCU_CSRM1APCTL, + MCU_CSRM2APCTL, + MCU_CSRM3APCTL, + MCU_CSRM4APCTL, + MCU_CSRM5APCTL}; + + /* Calculate the area used by Code SRAM. */ + bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + set_num = ((size & CODESRAM_BUS_NUM_MASK) >> CODESRAM_BUS_NUM_SHIFT); + + for (loop = 0U; loop < set_num; loop++) + { + /* Initialize ECC error detection and error correction setting for CodeSRAM. */ + reg = mem_read32(eccctl_reg[bus_num + loop]); + reg &= ~(CSRM_ECCCTL_EC1ECP | CSRM_ECCCTL_ECERVF); + reg |= CSRM_ECCCTL_EMCA_EN_MOD; + mem_write32(eccctl_reg[bus_num + loop], reg); + /* Initialize Address parity check setting for CodeSRAM. */ + reg = mem_read32(apctl_reg[bus_num + loop]); + reg |= CSRM_APCTL_APCEN; + mem_write32(apctl_reg[bus_num + loop], reg); + } +} +/* End of function initialize_codesram_ecc_parity */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/codesram_ecc.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/codesram_ecc.h new file mode 100644 index 0000000..7cb662f --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/codesram_ecc.h @@ -0,0 +1,39 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC and Address parity check for CodeSRAM header + ******************************************************************************/ + +#ifndef CODESRAM_ECC_H__ +#define CODESRAM_ECC_H__ + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void disable_codesram_ecc_parity(uint32_t boot_addr, uint32_t size); +void enable_codesram_ecc_parity(uint32_t boot_addr, uint32_t size); +void chk_codesram_ecc_parity(uint32_t boot_addr, uint32_t size); +void initialize_codesram_ecc_parity(uint32_t boot_addr, uint32_t size); + +#endif /* CODESRAM_ECC_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.c new file mode 100644 index 0000000..93a5b56 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.c @@ -0,0 +1,300 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MCU power management driver + ******************************************************************************/ + /****************************************************************************** + * @file cpu_on.c + * - Version : 0.02 + * @brief 1. Boot process of MCU CPU core. + * 2. Set Option Byte to OPBT. + * 3. Disable the Bus Guard. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.06.2022 0.01 First Release + * : 02.02.2023 0.02 Moved definitions to header file. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +/* MCU */ +#define MCU_OPBT_MAX (12U) +#define MCU_ICUM_OPBT_MAX (7U) +#define MCU_PBG_MAX (7U) +#define MCU_HBG_MAX (9U) +#define LOCAL_FLASH_BUS_MODE (0x12B9B0A1U) + +#define MCU_RESET_READY (0x00000001U) +#define MCU_RCT_RUNNING (0x00000001U) + +#define CODESRAM_ROUND_MASK (0x000FFFFFU) + +#define OPBT_EMPTY_VALUE (0xFFFFFFFFU) + +static void csrm_n_csifcode_protect(uint32_t bit_shift); + +void mcu_cpu_on(uint32_t target) +{ + uint32_t boot_ctrl = 0U; + uint32_t ret; + + if(MCU_PWR_TARGET_G4MH == target) + { +#if ((BOOT_MCU & MCU_BOOT_G4MH) != 0U) + boot_ctrl = MCU_G4MH_BOOT_CTLR; +#endif /* ((BOOT_MCU & MCU_BOOT_G4MH) != 0U) */ + } + else if(MCU_PWR_TARGET_ICUMH == target) + { +#if ((BOOT_MCU & MCU_BOOT_ICUMH) != 0U) + boot_ctrl = MCU_ICUMH_BOOT_CTLR; +#endif /* ((BOOT_MCU & MCU_BOOT_ICUMH) != 0) */ + } + else + { + /* No Process */ + } + + /* Execute the reset process of MCU core. * + * If the register address is not set in "A", * + * exit the function without executing anything. */ + if(boot_ctrl != 0U) + { + /* Release write protection of SCDS0 */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_REL_CODE); + + /* MCU core reset */ + ret = mem_read32(boot_ctrl); + ret |= MCU_RESET_READY; + mem_write32(boot_ctrl, ret); + ret = mem_read32(MCU_OPBT_CTRL); + ret |= MCU_RESET_READY; + mem_write32(MCU_OPBT_CTRL, ret); + + /* Wait until the MCU status is set to start. */ + do + { + ret = mem_read32(MCU_OPBT_STAT); + ret &= MCU_RCT_RUNNING; + } while (ret != MCU_RCT_RUNNING); + + /* write protection of SCDS0 */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_PROT_CODE); + } +} +/* End of function mcu_cpu_on(uint32_t target) */ + +void mcu_set_opbt(void) +{ + uint32_t loop; + const uint32_t opbt_reg[MCU_OPBT_MAX] = + { MCU_RESET_VECTOR_PE0, + MCU_RESET_VECTOR_PE1, + MCU_OPBT0, + MCU_OPBT1, + MCU_OPBT2, + MCU_OPBT3, + MCU_OPBT4, + MCU_OPBT6, + MCU_OPBT7, + MCU_OPBT8, + MCU_OPBT9, + MCU_OPBT96 + }; + + uint32_t opbt_val[MCU_OPBT_MAX] = + { 0x00000400U, + 0x00000400U, + 0x3D810010U, + 0x00700000U, + 0x707FFFFFU, + 0x00000000U, + 0x0C0C0C0FU, + 0x00000F00U, + 0x00000FFFU, + 0x02000000U, + 0x03000300U, + 0x00000000U + }; + + for (loop = 0U; loop < MCU_OPBT_MAX; loop++) + { + mem_write32(opbt_reg[loop], opbt_val[loop]); + opbt_val[loop] = OPBT_EMPTY_VALUE; + } +} +/* End of function mcu_set_opbt(uint32_t g4mh_addr) */ + +void mcu_set_icum_opbt(void) +{ + uint32_t loop; + const uint32_t opbt_reg[MCU_ICUM_OPBT_MAX] = + { MCU_ICUM_OPBT0, + MCU_ICUM_OPBT1, + MCU_ICUM_OPBT2, + MCU_ICUM_OPBT4, + MCU_ICUM_OPBT5, + MCU_ICUM_OPBT6, + MCU_ICUM_OPBT7 + }; + +#if (BOOT_MCU == MCU_BOOT_G4MH_ICUMH) + uint32_t opbt_val[MCU_ICUM_OPBT_MAX] = + { 0x0FFFFFFFU, + 0x00500000U, + 0x00500000U, + 0xFFFFFFEFU, + 0x00600000U, + 0xFFFFFFFFU, + 0xFFFFFFFFU + }; +#else + uint32_t opbt_val[MCU_ICUM_OPBT_MAX] = + { OPBT_EMPTY_VALUE, + OPBT_EMPTY_VALUE, + OPBT_EMPTY_VALUE, + OPBT_EMPTY_VALUE, + OPBT_EMPTY_VALUE, + OPBT_EMPTY_VALUE, + OPBT_EMPTY_VALUE + }; +#endif + + for (loop = 0U; loop < MCU_ICUM_OPBT_MAX; loop++) + { + mem_write32(opbt_reg[loop], opbt_val[loop]); + opbt_val[loop] = OPBT_EMPTY_VALUE; + } +} +/* End of function mcu_set_icum_opbt(uint32_t icumh_addr) */ + +void mcu_set_hbg(void) +{ + uint32_t loop; + const uint32_t pbg_reg[MCU_PBG_MAX][2U] = + { /* register address setting value */ + {MCUAXI_PBG_PBGPROT0_0, 0x00000000U}, + {MCUAXI_PBG_PBGPROT0_1, 0x00000000U}, + {MCUAXI_PBG_PBGPROT0_2, 0x00000000U}, + {MCUAXI_PBG_PBGPROT0_3, 0x00000000U}, + {MCUAXI_PBG_PBGPROT0_4, 0x00000000U}, + {MCUAXI_PBG_PBGPROT0_5, 0x00000000U}, + {MCUAXI_PBG_PBGPROT0_6, 0x00000000U} + }; + + const uint32_t hbg_reg[MCU_HBG_MAX][2U] = + { /* register address setting value */ + {MCU_HBG_CS0_HBGPROT0, 0x00000000U}, + {MCU_HBG_CS1_HBGPROT0, 0x00000000U}, + {MCU_HBG_CS2_HBGPROT0, 0x00000000U}, + {MCU_HBG_CS3_HBGPROT0, 0x00000000U}, + {MCU_HBG_CS4_HBGPROT0, 0x00000000U}, + {MCU_HBG_CS5_HBGPROT0, 0x00000000U}, + {MCU_HBG_DS_HBGPROT0, 0x00000000U}, + {MCU_HBG_SOCM_HBGPROT0, 0x00000000U}, + {MCU_HBG_SOCS_HBGPROT0, 0x00000000U} + }; + + const uint32_t hbg_prot_reg[MCU_HBG_MAX] = + { + MCU_HBGSLVER_CS0_HBGKCPROT, + MCU_HBGSLVER_CS1_HBGKCPROT, + MCU_HBGSLVER_CS2_HBGKCPROT, + MCU_HBGSLVER_CS3_HBGKCPROT, + MCU_HBGSLVER_CS4_HBGKCPROT, + MCU_HBGSLVER_CS5_HBGKCPROT, + MCU_HBGSLVER_DS_HBGKCPROT, + MCU_HBGSLVER_SOCM_HBGKCPROT, + MCU_HBGSLVER_SOCS_HBGKCPROT + }; + + /* Release write protection of SCDS0 */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_REL_CODE); + + /* Set PBG register */ + for (loop = 0U; loop < MCU_PBG_MAX; loop++) + { + mem_write32(pbg_reg[loop][0U], pbg_reg[loop][1U]); + } + + /* write protection of SCDS0 */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_PROT_CODE); + + /* Set HBG register */ + for (loop = 0U; loop < MCU_HBG_MAX; loop++) + { + hbg_reg_write(hbg_prot_reg[loop], hbg_reg[loop][0U], hbg_reg[loop][1U]); + } +} +/* End of function mcu_set_hbg(void) */ + +void mcu_set_csrm(uint32_t boot_addr, uint32_t size) +{ + uint32_t loop; + uint32_t bus_num; + uint32_t set_num; + const uint32_t csrm_reg[MCU_CSRM_MAX] = + { MCU_CSRM0CSIFCODE, + MCU_CSRM1CSIFCODE, + MCU_CSRM2CSIFCODE, + MCU_CSRM3CSIFCODE, + MCU_CSRM4CSIFCODE, + MCU_CSRM5CSIFCODE, + }; + + /* Calculate the area used by Code SRAM. */ + bus_num = ((boot_addr & CODESRAM_BUS_NUM_MASK) >> 20U); + set_num = ((size & CODESRAM_BUS_NUM_MASK) >> 20U); + + /* Set CSRM register */ + for (loop = 0U; loop < set_num; loop++) + { + mem_write32(csrm_reg[bus_num + loop], LOCAL_FLASH_BUS_MODE); + + /* Write protection of CSRMnCSIFCODE registers */ + csrm_n_csifcode_protect((bus_num + loop)); + } +} +/* End of function mcu_set_csrm(void) */ + +void hbg_reg_write(uint32_t prot_reg_addr, uint32_t reg_addr, uint32_t val) +{ + mem_write32(prot_reg_addr, MCU_HBG_REL_CODE); + mem_write32(reg_addr, val); + mem_write32(prot_reg_addr, MCU_HBG_PROT_CODE); +} +/* End of function hbg_reg_write(uint32_t prot_reg_addr, uint32_t reg_addr, uint32_t val) */ + +static void csrm_n_csifcode_protect(uint32_t bit_shift) +{ + /* Control CSIFCODE_LOCK to protect writing to CSRMnCSIFCODE during product mass production. */ +} +/* End of function csrm_n_csifcode_protect(uint32_t bit_shift) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.h new file mode 100644 index 0000000..ac40f44 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/cpu_on_for_mcu.h @@ -0,0 +1,62 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MCU power management driver header + ******************************************************************************/ + +#ifndef CPU_ON_FOR_MCU_H__ +#define CPU_ON_FOR_MCU_H__ + +#define MCU_PWR_TARGET_G4MH (0U) +#define MCU_PWR_TARGET_ICUMH (1U) + +#define MCU_BOOT_NONE (0U) +#define MCU_BOOT_G4MH (1U) +#define MCU_BOOT_ICUMH (2U) +#define MCU_BOOT_G4MH_ICUMH (3U) + +#define MCU_HBG_REL_CODE (0xA5A5A501U) +#define MCU_HBG_PROT_CODE (0xA5A5A500U) + +#define G4MH_PRG_1_BOOT_ADDR (0x10000000U) +#define G4MH_PRG_1_SIZE (0x00100000U) +#define G4MH_PRG_2_BOOT_ADDR (0x10100000U) +#define G4MH_PRG_2_SIZE (0x00400000U) +#define ICUMH_PRG_BOOT_ADDR (0x10500000U) +#define ICUMH_PRG_SIZE (0x00100000U) + +#define MCU_CSRM_MAX (6U) +#define CODESRAM_BUS_NUM_MASK (0x00700000U) + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void mcu_cpu_on(uint32_t target); +void mcu_set_opbt(void); +void mcu_set_icum_opbt(void); +void mcu_set_hbg(void); +void mcu_set_csrm(uint32_t boot_addr, uint32_t size); +void hbg_reg_write(uint32_t prot_reg_addr, uint32_t reg_addr, uint32_t val); + +#endif /* CPU_ON_FOR_MCU_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.c new file mode 100644 index 0000000..5ea17a4 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.c @@ -0,0 +1,117 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function for MCU + ******************************************************************************/ +/****************************************************************************** + * @file image_load_for_mcu.c + * - Version : 0.01 + * @brief Loading image driver for MCU. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 04.07.2022 0.01 First Release + *****************************************************************************/ + +/* indelude */ +#include +#include +#include +#include +#include +#if (RCAR_SA9_TYPE == FLASH_BOOT) +#include +#elif (RCAR_SA9_TYPE == EMMC_BOOT) +#include +#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + +void image_load_for_mcu(const LOAD_INFO *li, uint32_t is_verify) +{ + uint32_t aes_flg = MCU_IMG_NOT_ENCRYPTED; + + if (is_verify != NORMAL_BOOT) + { + /* A flag whether MCU image is encrypted */ + aes_flg = get_aes_flg_in_cert(li -> cnt_cert_addr); + } + + if(aes_flg == MCU_IMG_NOT_ENCRYPTED) + { + /* Transfer by SDMAC on ICUMX */ + icu_sdmac_trans_start(li); + } + else + { + /* Transfer by AES driver on ICUMX */ + mcu_img_decrypt(li); + } +} +/* End of function image_load_for_mcu(const LOAD_INFO *li) */ + +void load_end_for_mcu(const LOAD_INFO *li, uint32_t is_verify) +{ + uint32_t aes_flg = MCU_IMG_NOT_ENCRYPTED; + + if (is_verify != NORMAL_BOOT) + { + /* A flag whether MCU image is encrypted */ + aes_flg = get_aes_flg_in_cert(li -> cnt_cert_addr); + } + + if(aes_flg == MCU_IMG_NOT_ENCRYPTED) + { + icu_sdmac_trans_end(); + } + else + { + mcu_img_decrypt_end(li); + } +} +/* End of function load_end_for_mcu(const LOAD_INFO *li) */ + +void load_image_info_print(const LOAD_INFO *li) +{ +#if (RCAR_SA9_TYPE == FLASH_BOOT) + load_image_info_print_for_flash(li); +#elif (RCAR_SA9_TYPE == EMMC_BOOT) + load_image_info_print_for_emmc(li); +#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */ +} +/* End of function load_image_info_print(const LOAD_INFO *li) */ + +void load_securedata_for_mcu(void) +{ + LOAD_INFO tmp_li; + + tmp_li.image_size = SECUREDATA_SIZE; + tmp_li.src_addr = RTVRAM_BASE; + tmp_li.boot_addr = DATA_SRAM_BASE; +#if (RCAR_SA9_TYPE == EMMC_BOOT) + tmp_li.part_num = EMMC_PARTITION_1; +#endif + /* */ + icu_sdmac_trans_start(&tmp_li); + icu_sdmac_trans_end(); +}/* End of function load_securedata(uint32_t target_id) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.h new file mode 100644 index 0000000..1511f64 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/image_load_for_mcu.h @@ -0,0 +1,67 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function for MCU header + ******************************************************************************/ + +#ifndef IMAGE_LOAD_FOR_MCU_H__ +#define IMAGE_LOAD_FOR_MCU_H__ + +#include +#include +#include +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) +#include +#include +#include +#include +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ + +void image_load_for_mcu(const LOAD_INFO *li, uint32_t is_verify); +void load_end_for_mcu(const LOAD_INFO *li, uint32_t is_verify); +void load_image_info_print(const LOAD_INFO *li); +void load_securedata_for_mcu(void); + +/* Inline function */ +static inline uint32_t get_aes_flg_in_cert(uint32_t cert_addr) +{ +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) + uint32_t aes_flg; + uint32_t val; + + val = mem_read32(cert_addr + CERT_INFO_FLG_OFFSET); + aes_flg = ((val >> CERT_FLAG_ENCRYPTION_USED_BIT_LOCATION) & 0x1U); + + return aes_flg; +#else + return MCU_IMG_NOT_ENCRYPTED; +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ +} +/* End of function get_aes_flg_in_cert(uint32_t cert_addr) */ + +#endif /* IMAGE_LOAD_FOR_MCU_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/loader_main_mcu.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/loader_main_mcu.c new file mode 100644 index 0000000..48dc21b --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/loader_main_mcu.c @@ -0,0 +1,456 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main for MCU + ******************************************************************************/ + /****************************************************************************** + * @file loader_main_mcu.c + * - Version : 0.03 + * @brief 1. Loading G4MH(1st) image including integrity check. + * 2. Loading ICUMH image including integrity check. + * 3. Loading G4MH(2nd) image including integrity check. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 22.06.2022 0.01 First Release + * : 05.08.2022 0.02 Add sw_version_check function call to + * : mcu_img_verify function. + * : 19.01.2023 0.03 Add ECC and Address parity check for CodeSRAM. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) +#include +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ +#include +#include +#include + +#define ICUMH_OPBT_OFFSET (0x200U) + +#define MCU_TRANSFER_UNIT (0x00040000U) /* 256KiB */ +#define RTVRAM_TMP_G4MH_TOP_A (0xE2080000U) +#define RTVRAM_TMP_G4MH_TOP_B (0xE20C0000U) + +#define GREG120_CODE (0x5AA5A55AU) +#define G4MH_LOAD_FIN_CODE (0x0000001EU) + +/* Prototype */ +static void load_g4mh_1st(const LOAD_INFO *li, uint32_t is_verify); +static void load_icumh(const LOAD_INFO *li, uint32_t is_verify); +static void load_g4mh_2nd(const LOAD_INFO *li, uint32_t is_verify); +static void w_load_even(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify); +static void w_load_odd(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify); +static void mcu_key_cert_check(LOAD_INFO *li, uint32_t is_verify); +static void mcu_cnt_cert_check(const LOAD_INFO *li, uint32_t is_verify); +static void mcu_img_verify(const LOAD_INFO *li, uint32_t is_verify); + + +static void load_g4mh_1st(const LOAD_INFO *li, uint32_t is_verify) +{ + LOAD_INFO tmp_li = {0U}; + + /* Copy li to tmporary structure. (Because original li members are required later.) */ + (void)memcpy((void *)&tmp_li, li, sizeof(LOAD_INFO)); + /* Change boot_addr to RTVRAM_BASE. */ + tmp_li.boot_addr = RTVRAM_BASE; + + /* Output image info. */ + load_image_info_print(li); + + /* Check load information. */ + check_load_area(li); + + /* Release write protection of SCDS0. */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_REL_CODE); + mem_write32(MCU_GREG120, 0x00000000U); + + /* Set G4MH Option Byte. */ + mcu_set_opbt(); + /* Set ICUMH Option Byte. */ + mcu_set_icum_opbt(); + + mem_write32(MCU_GREG120, GREG120_CODE); + micro_wait(10U); + + /* Write protection of SCDS0. */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_PROT_CODE); + + /* Load G4MH(1st) image from external flash to RT-VRAM. */ + load_start(&tmp_li); + + /* Verify Key Certificate. */ + mcu_key_cert_check(&tmp_li, is_verify); + + /* Disable bus guard of MCU. */ + mcu_set_hbg(); + + /* Finish loading G4MH(1st) image from external flash to RT-VRAM. */ + load_end(); + + /* Change src_addr from external flash to RT-VRAM. */ + tmp_li.src_addr = tmp_li.boot_addr; + /* Change boot_addr from RT-VRAM to CodeSRAM. */ + tmp_li.boot_addr = li->boot_addr; + + /* Disable ECC error and Address parity error check for CodeSRAM. */ + disable_codesram_ecc_parity(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE); + + /* Load G4MH(1st) image from RT-VRAM to CodeSRAM. */ + image_load_for_mcu(&tmp_li, is_verify); + + /* Verify Content Certificate */ + mcu_cnt_cert_check(&tmp_li, is_verify); + + /* Finish loading G4MH(1st) image from RT-VRAM to CodeSRAM. */ + load_end_for_mcu(&tmp_li, is_verify); + + /* Enable ECC error and Address parity error check for CodeSRAM. */ + enable_codesram_ecc_parity(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE); + + /* Verify G4MH(1st) image. */ + mcu_img_verify(&tmp_li, is_verify); + + /* Check ECC error and Address parity error detection for CodeSRAM. */ + chk_codesram_ecc_parity(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE); + + /* Reset CSRM registers that related CodeSRAM ECC to H/W initial value. */ + initialize_codesram_ecc_parity(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE); + + + /* Change Bus mode of CodeSRAM to the Local Flash Bus mode. */ + mcu_set_csrm(G4MH_PRG_1_BOOT_ADDR, G4MH_PRG_1_SIZE); + + /* Boot G4MH */ + mcu_cpu_on(MCU_PWR_TARGET_G4MH); +} +/* End of function load_g4mh_1st(const LOAD_INFO *li) */ + +static void load_icumh(const LOAD_INFO *li, uint32_t is_verify) +{ +#if (BOOT_MCU == MCU_BOOT_G4MH_ICUMH) + LOAD_INFO tmp_li = {0U}; + + /* Copy li to tmporary structure. (Because original li members are required later.) */ + (void)memcpy((void *)&tmp_li, li, sizeof(LOAD_INFO)); + /* Change boot_addr to RTVRAM_BASE. */ + tmp_li.boot_addr = RTVRAM_BASE; + + /* Output image info. */ + load_image_info_print(li); + + /* Check load information. */ + check_load_area(li); + + /* Load ICUMH image from external flash to RT-VRAM. */ + load_start(&tmp_li); + + /* Verify Key Certificate. */ + mcu_key_cert_check(&tmp_li, is_verify); + + /* Finish loading ICUMH image from external flash to RT-VRAM. */ + load_end(); + + /* Change src_addr from external flash to RT-VRAM. */ + tmp_li.src_addr = tmp_li.boot_addr; + /* Change boot_addr from RT-VRAM to CodeSRAM. */ + tmp_li.boot_addr = li->boot_addr; + + /* Disable ECC error and Address parity error check for CodeSRAM. */ + disable_codesram_ecc_parity(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE); + + /* Load ICUMH image from RT-VRAM to CodeSRAM. */ + image_load_for_mcu(&tmp_li, is_verify); + + /* Verify Content Certificate */ + mcu_cnt_cert_check(&tmp_li, is_verify); + + /* Finish loading ICUMH image from RT-VRAM to CodeSRAM. */ + load_end_for_mcu(&tmp_li, is_verify); + + /* Load Secure data from external flash to RT-VRAM */ + load_securedata(ICUMH_PROGRAM_ID); + + /* Enable ECC error and Address parity error check for CodeSRAM. */ + enable_codesram_ecc_parity(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE); + + /* Verify ICUMH image. */ + mcu_img_verify(&tmp_li, is_verify); + + /* Finish loading Secure data from external flash to RT-VRAM. */ + load_end(); + + /* Check ECC error and Address parity error detection for CodeSRAM. */ + chk_codesram_ecc_parity(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE); + + /* Reset CSRM registers that related CodeSRAM ECC to H/W initial value. */ + initialize_codesram_ecc_parity(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE); + + /* Load Secure data from RT-VRAM to Data-SRAM. */ + load_securedata_for_mcu(); + + /* Change Bus mode of CodeSRAM to the Local Flash Bus mode. */ + mcu_set_csrm(ICUMH_PRG_BOOT_ADDR, ICUMH_PRG_SIZE); + + /* Boot ICUMH */ + mcu_cpu_on(MCU_PWR_TARGET_ICUMH); +#endif /* (BOOT_MCU == MCU_BOOT_G4MH_ICUMH) */ +} +/* End of function load_icumh(const LOAD_INFO *li) */ + +static void load_g4mh_2nd(const LOAD_INFO *li, uint32_t is_verify) +{ + uint32_t count = 0U; + uint32_t dst_size = li->image_size; + uint32_t even_or_odd = 0U; + LOAD_INFO tmp_li = {0U}; + void (*p_w_load_func[])(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify) + = {w_load_even, w_load_odd}; + + /* Copy li to tmporary structure. (Because original li members are required later.) */ + (void)memcpy((void *)&tmp_li, li, sizeof(LOAD_INFO)); + + /* A transfer unit is 256KiB. */ + tmp_li.image_size = MCU_TRANSFER_UNIT; + /* Change boot_addr to 0xE2080000. */ + tmp_li.boot_addr = RTVRAM_TMP_G4MH_TOP_A; + + /* Output image info. */ + load_image_info_print(li); + + /* Check load information. */ + check_load_area(li); + + /* Load image from external flash to RT-VRAM. */ + load_start(&tmp_li); + + /* Verify Key Certificate. */ + mcu_key_cert_check(&tmp_li, is_verify); + + /* Finish loading image from external flash to RT-VRAM. */ + load_end(); + + /* Disable ECC error and Address parity error check for CodeSRAM. */ + disable_codesram_ecc_parity(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE); + + if (dst_size <= tmp_li.image_size) + { + /* If image size is less than 256KiB. */ + tmp_li.image_size = dst_size; + mcu_cnt_cert_check(li, is_verify); + } + else /* If image size is larger than 256KiB. */ + { + /* dst_size - 256KiB */ + dst_size -= tmp_li.image_size; + + if (dst_size < tmp_li.image_size) + { + /* If remaining image size is less than 256KiB. */ + count++; + even_or_odd = count; + tmp_li.image_size = dst_size; + dst_size = 0U; + } + else /* If remaining image size is still larger than 256KiB. */ + { + count++; + even_or_odd = count; + dst_size -= tmp_li.image_size; + } + /* Load image(#count) from external flash to RT-VRAM. * + * Load image(#count-1) from RT-VRAM to CodeSRAM. */ + p_w_load_func[even_or_odd](li, &tmp_li, count, is_verify); + + /* Verify Content Certificate */ + mcu_cnt_cert_check(&tmp_li, is_verify); + + /* Finish loading image(#count) from external flash to RT-VRAM. */ + load_end(); + /* Finish loading image(#count-1) from RT-VRAM to CodeSRAM. */ + load_end_for_mcu(&tmp_li, is_verify); + + /* Load remaining image. */ + while (dst_size != 0U) + { + if (dst_size < tmp_li.image_size) + { + /* If remaining image size is less than 256KiB. */ + count++; + even_or_odd = count % 2U; + tmp_li.image_size = dst_size; + dst_size = 0U; + } + else /* If remaining image size is still larger than 256KiB. */ + { + count++; + even_or_odd = count % 2U; + dst_size -= tmp_li.image_size; + } + /* Load image(#count) from external flash to RT-VRAM. * + * Load image(#count-1) from RT-VRAM to CodeSRAM. (with decryption) */ + p_w_load_func[even_or_odd](li, &tmp_li, count, is_verify); + /* Finish loading image(#count) from external flash to RT-VRAM. */ + load_end(); + /* Finish loading image(#count-1) from RT-VRAM to CodeSRAM. */ + load_end_for_mcu(&tmp_li, is_verify); + } + } + tmp_li.src_addr = (RTVRAM_TMP_G4MH_TOP_A + (even_or_odd * MCU_TRANSFER_UNIT)); + tmp_li.boot_addr = (li->boot_addr + (MCU_TRANSFER_UNIT * (count))); + + /* Load image from RT-VRAM to CodeSRAM (with decryption). */ + image_load_for_mcu(&tmp_li, is_verify); + + /* Finish loading image(bottom) from RT-VRAM to CodeSRAM. */ + load_end_for_mcu(&tmp_li); + + /* Enable ECC error and Address parity error check for CodeSRAM. */ + enable_codesram_ecc_parity(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE); + + /* Verify G4MH(2nd) image. */ + mcu_img_verify(li, is_verify); + + /* Check ECC error and Address parity error detection for CodeSRAM. */ + chk_codesram_ecc_parity(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE); + + /* Reset CSRM registers that related CodeSRAM ECC to H/W initial value. */ + initialize_codesram_ecc_parity(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE); + + /* Change Bus mode of CodeSRAM to the Local Flash Bus mode. */ + mcu_set_csrm(G4MH_PRG_2_BOOT_ADDR, G4MH_PRG_2_SIZE); + + /* Release write protection of SCDS0. */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_REL_CODE); + mem_write32(MCU_BOOT_STAT, G4MH_LOAD_FIN_CODE); + /* Write protection of SCDS0. */ + mem_write32(MCUAXI_PBG_ERRSLV_PBGKCPROT, MCU_HBG_PROT_CODE); + + hbg_reg_write(MCU_HBGSLVER_PFS_HBGKCPROT, MCU_HBG_PFS_HBGPROT0, 0x00000000U); +} +/* End of function load_g4mh_2nd(const LOAD_INFO *li) */ + +static void w_load_even(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify) +{ + tmp_li->src_addr = (li->src_addr + (MCU_TRANSFER_UNIT * count)); + tmp_li->boot_addr = RTVRAM_TMP_G4MH_TOP_A; + + /* Load image(#count) from external flash to RT-VRAM. */ + load_start(tmp_li); + + tmp_li->src_addr = RTVRAM_TMP_G4MH_TOP_B; + tmp_li->boot_addr = (li->boot_addr + (MCU_TRANSFER_UNIT * (count - 1U))); + + /* Load image(#count-1) from RT-VRAM to CodeSRAM. (with decryption) */ + image_load_for_mcu(tmp_li, is_verify); +} +/* End of function w_load_even(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count) */ + +static void w_load_odd(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count, uint32_t is_verify) +{ + tmp_li->src_addr = (li->src_addr + (MCU_TRANSFER_UNIT * count)); + tmp_li->boot_addr = RTVRAM_TMP_G4MH_TOP_B; + + /* Load image(#count) from external flash to RT-VRAM. */ + load_start(tmp_li); + + tmp_li->src_addr = RTVRAM_TMP_G4MH_TOP_A; + tmp_li->boot_addr = (li->boot_addr + (MCU_TRANSFER_UNIT * (count - 1U))); + + /* Load image(#count-1) from RT-VRAM to CodeSRAM. (with decryption) */ + image_load_for_mcu(tmp_li, is_verify); +} +/* End of function w_load_even(const LOAD_INFO *li, LOAD_INFO *tmp_li, uint32_t count) */ + +static void mcu_key_cert_check(LOAD_INFO *li, uint32_t is_verify) +{ +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) + if (is_verify != NORMAL_BOOT) + { + r_mcu_key_cert_check_api(li); + } +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ +} +/* End of function mcu_key_cert_check(LOAD_INFO *li, uint32_t is_verify). */ + +static void mcu_cnt_cert_check(const LOAD_INFO *li, uint32_t is_verify) +{ +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) + if (is_verify != NORMAL_BOOT) + { + r_mcu_cnt_cert_check_api(li); + } +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ +} +/* End of function mcu_key_cert_check(const LOAD_INFO *li, uint32_t is_verify) */ + +void mcu_img_decrypt(const LOAD_INFO *li) +{ +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) + r_mcu_img_decrypt_api(li); +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ +} +/* End of function mcu_img_decrypt(const LOAD_INFO *li, uint32_t is_verify) */ + +void mcu_img_decrypt_end(const LOAD_INFO *li) +{ + /* Argument li is not used but compliant to MISRA Rule 2.2. */ +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) + r_mcu_img_decrypt_end(); +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ +} +/* End of function mcu_img_decrypt_end(const LOAD_INFO *li) */ + +static void mcu_img_verify(const LOAD_INFO *li, uint32_t is_verify) +{ +#if (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) + if (is_verify != NORMAL_BOOT) + { + r_mcu_img_verify_api(li); + sw_version_check(li); + } +#endif /* (MCU_SECURE_BOOT == MCU_SEC_BOOT_ENABLE) */ +} +/* End of function mcu_img_verify(const LOAD_INFO *li, uint32_t is_verify) */ + +void mcu_load_main(const LOAD_INFO *li, uint32_t is_verify) +{ + load_g4mh_1st(&li[G4MH_PROGRAM_ID], is_verify); /* Load G4MH(1st) image. */ + load_icumh(&li[ICUMH_PROGRAM_ID], is_verify); /* Load ICUMH image. */ + load_g4mh_2nd(&li[G4MH_PROGRAM_ID + 1U], is_verify); /* Load G4MH(2nd) image. */ +} +/* End of function mcu_load_main(const LOAD_INFO *li, uint32_t is_verify) */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/loader_main_mcu.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/loader_main_mcu.h new file mode 100644 index 0000000..5cf989b --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/loader_main_mcu.h @@ -0,0 +1,45 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : MCU Secure Boot Main header + ******************************************************************************/ + +#ifndef LOADER_MAIN_MCU_H__ +#define LOADER_MAIN_MCU_H__ + +#include +#include + +#define MCU_SEC_BOOT_ENABLE (1U) +#define MCU_IMG_NOT_ENCRYPTED (0U) + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ + +void mcu_img_decrypt(const LOAD_INFO *li); +void mcu_img_decrypt_end(const LOAD_INFO *li); +void mcu_load_main(const LOAD_INFO *li, uint32_t is_verify); + +#endif /* LOADER_MAIN_MCU_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/sdmac.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/sdmac.c new file mode 100644 index 0000000..2ff451f --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/sdmac.c @@ -0,0 +1,110 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function by SDMAC on ICUMX + ******************************************************************************/ +/****************************************************************************** + * @file sdmac.c + * - Version : 0.01 + * @brief Driver of SCMAC on ICUMX. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.06.2022 0.01 First Release + *****************************************************************************/ + +/* indelude */ +#include +#include +#include +#include +#include +#include + +void icu_sdmac_trans_start(const LOAD_INFO *li) +{ + uint16_t reg; + uint32_t len = li->image_size; + + /* src_addr and boot_addr must be 64-byte boundary. */ + dma_address_align_check(li->boot_addr, li->src_addr); + + /* If len is not 64-byte boundary, */ + /* round up len to 64-byte boundary. */ + len += SDMAC_FRACTION_MASK_64_BYTE; + len &= ~(SDMAC_FRACTION_MASK_64_BYTE); + + /* Clear channel 0 registers */ + mem_write32(ICUMX_DMACHRST, ICUMX_DMACHRST_CLR_CH0); + /* Clear flags */ + mem_write32(ICUMX_DMACHFCR_0, ICUMX_DMACHFCR_INIT); + /* Round-robin mode / Enable DMA transfer */ + mem_write16(ICUMX_DMAOR, ICUMX_DMAOR_INIT); + + /* DMA Transfer mode * + * Slow speed mode : Normal mode * + * Priority setting : Disable * + * Transfer Request source : Auto Request * + * Destination Address mode : Fixed * + * Source address mode : Incremented * + * DMA destination transaction size : 64byte * + * DMA source transaction size : 64byte */ + mem_write32(ICUMX_DMATMR_0, ICUMX_DMATMR_0_INIT); + + /* Set destination address */ + mem_write32(ICUMX_DMADAR_0, li->boot_addr); + /* Set source address */ + mem_write32(ICUMX_DMASAR_0, li->src_addr); + /* Set transfer size */ + mem_write32(ICUMX_DMATSR_0, len); + reg = mem_read16(ICUMX_DMACHCR_0); + /* Enable channel address error notification / Enable DMA */ + reg |= ICUMX_DMACHCR_0_START; + mem_write16(ICUMX_DMACHCR_0, reg); +} +/* End of function icu_sdmac_trans_start(LOAD_INFO *li) */ + +void icu_sdmac_trans_end(void) +{ + uint32_t reg; + + wdt_restart(); + /* Check end of DMA transfer. */ + do + { + reg = mem_read32(ICUMX_DMACHSTA_0); + /* Check error of DMA transfer */ + if ((reg & ICUMX_DMACHSTA_CAE) != DMACHSTA_CAE_BIT_NOERROR) + { + ERROR("SDMAC on ICUMX - Channel Address Error\n"); + panic; + } + } while ((reg & ICUMX_DMACHSTA_TE) != DMACHSTA_TE_END_DMA); + + /* Clear flags */ + mem_write32(ICUMX_DMACHFCR_0, ICUMX_DMACHFCR_INIT); +} +/* End of function icu_sdmac_trans_end(void) */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/sdmac.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/sdmac.h new file mode 100644 index 0000000..0f241c4 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/sdmac.h @@ -0,0 +1,99 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Image load function by SDMAC on ICUMX header + ******************************************************************************/ + +#ifndef SDMAC_H__ +#define SDMAC_H__ + +#include +#include + +/* Prototype */ +void icu_sdmac_trans_start(const LOAD_INFO *li); +void icu_sdmac_trans_end(void); + +/* Definitions */ +#define ICUMX_DMACHRST_CLR_CH0 (0x00000001U) +#define ICUMX_DMACHRST_CLR_CH1 (0x00000002U) +#define ICUMX_DMACHRST_CLR_CH2 (0x00000004U) + +#define ICUMX_DMACHFCR_CAEC (0x00000008U) +#define ICUMX_DMACHFCR_TEC (0x00000002U) +#define ICUMX_DMACHFCR_DEC (0x00000001U) +#define ICUMX_DMACHFCR_INIT (ICUMX_DMACHFCR_CAEC | ICUMX_DMACHFCR_TEC | ICUMX_DMACHFCR_DEC) + +#define ICUMX_DMAOR_PR_ROUND_ROBIN (0x0300U) +#define ICUMX_DMAOR_DME_ENABLE (0x0001U) +#define ICUMX_DMAOR_INIT (ICUMX_DMAOR_PR_ROUND_ROBIN | ICUMX_DMAOR_DME_ENABLE) + +#define ICUMX_DMATMR_SLM_NORMAL (0x00000000U) +#define ICUMX_DMATMR_PRI_DISABLE (0x00000000U) +#define ICUMX_DMATMR_TRS_AT_REQ (0x00000000U) +#define ICUMX_DMATMR_TRS_HARD_REQ (0x00001000U) +#define ICUMX_DMATMR_DM_INC (0x00000400U) +#define ICUMX_DMATMR_SM_INC (0x00000100U) +#define ICUMX_DMATMR_DTS_64B (0x00000060U) +#define ICUMX_DMATMR_STS_64B (0x00000006U) +#define ICUMX_DMATMR_0_INIT (ICUMX_DMATMR_SLM_NORMAL | ICUMX_DMATMR_PRI_DISABLE | ICUMX_DMATMR_TRS_AT_REQ \ + | ICUMX_DMATMR_DM_INC | ICUMX_DMATMR_SM_INC | ICUMX_DMATMR_DTS_64B \ + | ICUMX_DMATMR_STS_64B) +#define ICUMX_DMATMR_1_INIT (ICUMX_DMATMR_SLM_NORMAL | ICUMX_DMATMR_PRI_DISABLE \ + | ICUMX_DMATMR_TRS_HARD_REQ | ICUMX_DMATMR_SM_INC | ICUMX_DMATMR_DTS_64B \ + | ICUMX_DMATMR_STS_64B) +#define ICUMX_DMATMR_2_INIT (ICUMX_DMATMR_SLM_NORMAL | ICUMX_DMATMR_PRI_DISABLE \ + | ICUMX_DMATMR_TRS_HARD_REQ | ICUMX_DMATMR_DM_INC | ICUMX_DMATMR_DTS_64B \ + | ICUMX_DMATMR_STS_64B) + +#define ICUMX_DMACHCR_CAEE_ENABLE (0x0010U) +#define ICUMX_DMACHCR_CAIE_ENABLE (0x0008U) +#define ICUMX_DMACHCR_IE_ENABLE (0x0002U) +#define ICUMX_DMACHCR_DE_ENABLE (0x0001U) +#define ICUMX_DMACHCR_0_START (ICUMX_DMACHCR_CAEE_ENABLE | ICUMX_DMACHCR_DE_ENABLE) +#define ICUMX_DMACHCR_1_START (ICUMX_DMACHCR_CAEE_ENABLE | ICUMX_DMACHCR_CAIE_ENABLE \ + | ICUMX_DMACHCR_DE_ENABLE) +#define ICUMX_DMACHCR_2_START (ICUMX_DMACHCR_CAEE_ENABLE | ICUMX_DMACHCR_CAIE_ENABLE \ + | ICUMX_DMACHCR_IE_ENABLE | ICUMX_DMACHCR_DE_ENABLE) + +#define ICUMX_DMACHSTA_CAE (0x00000008U) +#define ICUMX_DMACHSTA_TE (0x00000002U) +#define DMACHSTA_CAE_BIT_NOERROR (0x00000000U) +#define DMACHSTA_TE_END_DMA (0x00000002U) + +#define ICUMX_DMARS_TC_1 (0x00010000U) +#define ICUMX_DMARS_TL_TMR_DTS (0x00001000U) +#define ICUMX_DMARS_TL_TMR_STS (0x00000000U) +#define ICUMX_DMARS_FPT_DE_IS_1 (0x00000000U) +#define ICUMX_DMARS_PLE_ENABLE (0x00000400U) +#define ICUMX_DMARS_PLE_DISABLE (0x00000000U) +#define ICUMX_DMARS_RS_FOR_CH2 (0x00000001U) +#define ICUMX_DMARS_1_INIT (ICUMX_DMARS_TC_1 | ICUMX_DMARS_TL_TMR_DTS | ICUMX_DMARS_FPT_DE_IS_1 \ + | ICUMX_DMARS_PLE_ENABLE) +#define ICUMX_DMARS_2_INIT (ICUMX_DMARS_TC_1 | ICUMX_DMARS_TL_TMR_STS | ICUMX_DMARS_FPT_DE_IS_1 \ + | ICUMX_DMARS_PLE_DISABLE | ICUMX_DMARS_RS_FOR_CH2) + +#define SDMAC_FRACTION_MASK_64_BYTE (0x3FU) + +#endif /* SDMAC_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/sdmac_register.h b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/sdmac_register.h new file mode 100644 index 0000000..69be66a --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/mcu/sdmac_register.h @@ -0,0 +1,77 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Registers of SDMAC on ICUMX + ******************************************************************************/ + +#ifndef SDMAC_REGISTER_H__ +#define SDMAC_REGISTER_H__ + +/* SDMAC on ICUMX base address */ +#define ICUMX_SDMAC_BASE (0xFF600000U) + +/* Channel offset address */ +#define ICUMX_SDMAC_CH0 (0x80U * 0U) +#define ICUMX_SDMAC_CH1 (0x80U * 1U) +#define ICUMX_SDMAC_CH2 (0x80U * 2U) + +/* SDMAC Interrupt Status Register */ +#define ICUMX_DMAISTA (ICUMX_SDMAC_BASE + 0x0020U) +/* SDMAC Operation Register */ +#define ICUMX_DMAOR (ICUMX_SDMAC_BASE + 0x0060U) +/* SDMAC Channel Reset Register */ +#define ICUMX_DMACHRST (ICUMX_SDMAC_BASE + 0x0080U) +/* SDMAC Source Address Register */ +#define ICUMX_DMASAR_0 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH0) +#define ICUMX_DMASAR_1 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH1) +#define ICUMX_DMASAR_2 (ICUMX_SDMAC_BASE + 0x2000U + ICUMX_SDMAC_CH2) +/* SDMAC Destination Address Register */ +#define ICUMX_DMADAR_0 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH0) +#define ICUMX_DMADAR_1 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH1) +#define ICUMX_DMADAR_2 (ICUMX_SDMAC_BASE + 0x2004U + ICUMX_SDMAC_CH2) +/* SDMAC Transfer Size Register */ +#define ICUMX_DMATSR_0 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH0) +#define ICUMX_DMATSR_1 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH1) +#define ICUMX_DMATSR_2 (ICUMX_SDMAC_BASE + 0x2008U + ICUMX_SDMAC_CH2) +/* SDMAC Transfer Mode Register */ +#define ICUMX_DMATMR_0 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH0) +#define ICUMX_DMATMR_1 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH1) +#define ICUMX_DMATMR_2 (ICUMX_SDMAC_BASE + 0x2010U + ICUMX_SDMAC_CH2) +/* SDMAC Channel Control Register */ +#define ICUMX_DMACHCR_0 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH0) +#define ICUMX_DMACHCR_1 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH1) +#define ICUMX_DMACHCR_2 (ICUMX_SDMAC_BASE + 0x2014U + ICUMX_SDMAC_CH2) +/* SDMAC Channel Status Register */ +#define ICUMX_DMACHSTA_0 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH0) +#define ICUMX_DMACHSTA_1 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH1) +#define ICUMX_DMACHSTA_2 (ICUMX_SDMAC_BASE + 0x2018U + ICUMX_SDMAC_CH2) +/* SDMAC Channel Flag Clear Register */ +#define ICUMX_DMACHFCR_0 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH0) +#define ICUMX_DMACHFCR_1 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH1) +#define ICUMX_DMACHFCR_2 (ICUMX_SDMAC_BASE + 0x201CU + ICUMX_SDMAC_CH2) +/* SDMAC Resource Select Register */ +#define ICUMX_DMARS_1 (ICUMX_SDMAC_BASE + 0x2040U + ICUMX_SDMAC_CH1) +#define ICUMX_DMARS_2 (ICUMX_SDMAC_BASE + 0x2040U + ICUMX_SDMAC_CH2) + +#endif /* SDMAC_REGISTER_H__ */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/protect/ram_protection.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/protect/ram_protection.c new file mode 100644 index 0000000..1a4fec5 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/protect/ram_protection.c @@ -0,0 +1,271 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : memory protection function + ******************************************************************************/ + /****************************************************************************** + * @file ram_protection.c + * - Version : 0.03 + * @brief Access protection setting of memory. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 19.12.2022 0.01 First Release + * : 11.01.2024 0.02 Added icu_remove_write_access function. + * : 19.01.2024 0.03 Updated debug log. + * : 31.01.2024 0.04 Fixed the error in SECDIVn register + * setting value for ram_protect_init_4_rtsram() + * and ram_protect_init_4_rtvram. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Value for calculating the offset address to set in SECDIVD. */ +#define RTSRAM_SECDIVD_SUBVALUE (0xE0000000U) /* RT-VRAM0 Base address */ +#define RTVRAM_SECDIVD_SUBVALUE (0xE2000000U) /* RT-VRAM1 Base address */ + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +static void ram_protect_init_4_rtsram(void); +static void ram_protect_init_4_rtvram(const RTRAM_PROTECTION_STRUCTUR *cnf_tbl); +static void ram_protect_init_4_sysram(void); +static void ram_protect_init_4_dram(void); +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ + +void ram_protection(void) +{ +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + /* RT-SRAM */ + NOTICE("RT-SRAM Protection setting...\n"); + ram_protect_init_4_rtsram(); + NOTICE("finish!\n"); + + /* RT-VRAM */ + NOTICE("RT-VRAM Protection setting...\n"); + ram_protect_init_4_rtvram(g_rtvram1_protection_table_1); + NOTICE("finish!\n"); + + /* System RAM */ + NOTICE("System RAM Protection setting...\n"); + ram_protect_init_4_sysram(); + NOTICE("finish!\n"); + + /* DRAM */ + NOTICE("DRAM Protection setting...\n"); + ram_protect_init_4_dram(); + NOTICE("finish!\n"); +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ +} +/* End of function ram_protection(void) */ + +#if (RCAR_LSI == RCAR_S4) +void ram_protection_final(void) +{ +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + NOTICE("RT-VRAM Protection setting(finally)...\n"); + ram_protect_init_4_rtvram(g_rtvram1_protection_table_2); + NOTICE("finish!\n"); +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ +} +/* End of function ram_protection_final(void) */ +#endif /* #if (RCAR_LSI == RCAR_S4) */ + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +static void ram_protect_init_4_rtsram(void) +{ + uint32_t loop; + uint32_t val; + uint32_t set_val; + uint32_t addr; + + /* set division point for RT-SRAM */ + for (loop = 0U; loop < (RAM_PROTECTION_MAX - 1U); ++loop) + { + addr = get_rtsram_secdivd_addr(loop); + val = mem_read32(addr); + val &= ~(RTSRAM_SECDIVD_DIVADDR_MASK); + set_val = g_rtsram_protection_table[loop + 1U].addr - RTSRAM_SECDIVD_SUBVALUE; + val |= ((set_val & RTSRAM_ADDR_OFFSET_MASK) >> 12U); + mem_write32(addr, val); + INFO("SECDIVD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } + + /* Set division area protection register for RT-SRAM */ + for (loop = 0U; loop < RAM_PROTECTION_MAX; ++loop) + { + /* Read Access Configuration */ + addr = get_rtsram_secctrrd_addr(loop); + val = mem_read32(addr); + val &= ~(RTSRAM_SECCTRRD_SECGRP_MASK | RTSRAM_SECCTRRD_SAFGRP_MASK); + val |= g_rtsram_protection_table[loop].setting_value.read_val; + mem_write32(addr, val); + INFO("SECCTRRD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + /* Write Access Configuration */ + addr = get_rtsram_secctrwd_addr(loop); + val = mem_read32(addr); + val &= ~(RTSRAM_SECCTRWD_SECGRP_MASK | RTSRAM_SECCTRWD_SAFGRP_MASK); + val |= g_rtsram_protection_table[loop].setting_value.write_val; + mem_write32(addr, val); + INFO("SECCTRWD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } +} +/* End of function ram_protect_init_4_rtsram(void) */ + +static void ram_protect_init_4_rtvram(const RTRAM_PROTECTION_STRUCTUR *cnf_tbl) +{ + uint32_t loop; + uint32_t val; + uint32_t set_val; + uint32_t addr; + + /* set division point for RT-VRAM1 */ + for (loop = 0U; loop < (RAM_PROTECTION_MAX - 1U); ++loop) + { + addr = get_rtvram_secdivd_addr(loop); + val = mem_read32(addr); + val &= ~(RTVRAM_SECDIVD_DIVADDR_MASK); + set_val = cnf_tbl[loop + 1U].addr - RTVRAM_SECDIVD_SUBVALUE; + val |= ((set_val & RTVRAM_ADDR_MASK) >> 12U); + mem_write32(addr, val); + INFO("SECDIVD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } + + /* Set division area protection register for RT-VRAM1 */ + for (loop = 0U; loop < RAM_PROTECTION_MAX; ++loop) + { + /* Read Access Configuration */ + addr = get_rtvram_secctrrd_addr(loop); + val = mem_read32(addr); + val &= ~(RTVRAM_SECCTRRD_SECGRP_MASK | RTVRAM_SECCTRRD_SAFGRP_MASK); + val |= cnf_tbl[loop].setting_value.read_val; + mem_write32(addr, val); + INFO("SECCTRRD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + /* Write Access Configuration */ + addr = get_rtvram_secctrwd_addr(loop); + val = mem_read32(addr); + val &= ~(RTVRAM_SECCTRWD_SECGRP_MASK | RTVRAM_SECCTRWD_SAFGRP_MASK); + val |= cnf_tbl[loop].setting_value.write_val; + mem_write32(addr, val); + INFO("SECCTRWD[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } +} +/* End of function ram_protect_init_4_rtvram(const RTRAM_PROTECTION_STRUCTUR *cnf_tbl) */ + + +static void ram_protect_init_4_sysram(void) +{ + uint32_t loop; + uint32_t val; + uint32_t addr; + + /* set division point for SystemRAM */ + for (loop = 0U; loop < (RAM_PROTECTION_MAX - 1U); ++loop) + { + addr = get_sptdivcr_addr(loop); + val = mem_read32(addr); + val &= ~(AXMM_SPTDIVCR_DIVADDR_MASK); + val |= ((g_system_ram_protection_table[loop + 1U].addr & SYSTEM_RAM_ADDR_MASK) >> 12U); + mem_write32(addr, val); + INFO("SPTDIVCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } + + /* Set division area protection register for RT-VRAM */ + for (loop = 0U; loop < RAM_PROTECTION_MAX; ++loop) + { + /* Read / Write Access Configuration */ + addr = get_sptrgncr_addr(loop); + val = g_system_ram_protection_table[loop].setting_value.rw_val; + mem_write32(addr, val); + INFO("SPTRGNCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + /* Secure setting */ + addr = get_sptseccr_addr(loop); + val = mem_read32(addr); + val &= ~(AXMM_SPTSECCR_SECGRP_MASK | AXMM_SPTSECCR_SECGWP_MASK); + val |= g_system_ram_protection_table[loop].setting_value.sec_val; + mem_write32(addr, val); + INFO("SPTSECCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } +} +/* End of function ram_protect_init_4_sysram(void) */ + + +static void ram_protect_init_4_dram(void) +{ + uint32_t loop; + uint32_t val; + uint32_t addr; + + /* set division point for SDRAM */ + for (loop = 0U; loop < (DRAM_PROTECTION_MAX - 1U); ++loop) + { + addr = get_dptdivcr_addr(loop); + val = mem_read32(addr); + val &= ~(AXMM_DPTDIVCR_DIVADDR_MASK); + val |= ((g_dram_protection_table[loop + 1U].addr & SDRAM_ADDR_MASK) >> 16U); + mem_write32(addr, val); + INFO("DPTDIVCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } + + /* Set division area protection register for RT-VRAM */ + for (loop = 0U; loop < DRAM_PROTECTION_MAX; ++loop) + { + /* Read / Write Access Configuration */ + addr = get_dptrgncr_addr(loop); + val = g_dram_protection_table[loop].setting_value.rw_val; + mem_write32(addr, val); + INFO("DPTRGNCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + /* Secure setting */ + addr = get_dptseccr_addr(loop); + val = mem_read32(addr); + val &= ~(AXMM_DPTSECCR_SECGRP_MASK | AXMM_DPTSECCR_SECGWP_MASK); + val |= g_dram_protection_table[loop].setting_value.sec_val; + mem_write32(addr, val); + INFO("DPTSECCR[%d](0x%08x)\t = 0x%08x\n", loop, addr, mem_read32(addr)); + } +} +/* End of function ram_protect_init_4_dram(void) */ +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ + +void icu_remove_write_access(void) +{ +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + uint32_t reg; + uint32_t addr; + + addr = get_sptrgncr_addr(SYSTEM_RAM_CX_2ND_IPL); + reg = mem_read32(addr); + reg |= REGIONID0_WRITE_PRIVILEGE; /* Remove write privilege to System RAM Area0 from RGID0(ICUMX). */ + mem_write32(addr, reg); +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ +} +/* End of function icu_remove_write_access(void) */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/protect/region_id.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/protect/region_id.c new file mode 100644 index 0000000..51c8f16 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/protect/region_id.c @@ -0,0 +1,587 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Region ID protection function + ******************************************************************************/ + /****************************************************************************** + * @file region_id.c + * - Version : 0.08 + * @brief Each module to R/W access protection by Region ID. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.03.2022 0.01 First Release + * : 23.05.2022 0.02 Modify remap address + * : 21.10.2022 0.03 Supported for V4H + * : 23.01.2023 0.04 Remove pre-process branch for S4N. + * Added a process for judgement the number of + * Clusters to the rgid_gid_setting function. + * Changed to temporarily sweeten the protection + * setting only when the IPL is running. + * : 21.08.2023 0.05 Add support for V4M. + * : 13.11.2023 0.06 Changed to use CCI MPU GID register setting + * table in rgid_gid_setting function. + * : 13.09.2024 0.07 Change setting order of Region ID. + * (Swap Write and Secure.) + * : 06.01.2025 0.08 Added IMP Region ID setting process. + * Added Domain protection setting process. + * Added IPMMU Region ID setting process. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Unregistered base address of Region ID in SIC Remap. */ +#if (RCAR_LSI == RCAR_S4) +#define RGID_SICREMAP_NUM (1U) +#define RGID_BASE1 (0xFF800000U) + +#define GID_SETTING_VALUE (0x0002BFC4U) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define RGID_SICREMAP_NUM (5U) +#define RGID_BASE1 (0xFD800000U) +#define RGID_BASE2 (0xE7A00000U) +#define RGID_BASE3 (0xEB800000U) +#define RGID_BASE4 (0xFE600000U) +#define RGID_BASE5 (0xFF800000U) +/* For IPMMU Region ID setting */ +#define RGID_IPMMU_SICREMAP_NUM (3U) +#define RGID_IPMMU_BASE1 (0xEE400000U) +#define RGID_IPMMU_BASE2 (0xEEC00000U) +#define RGID_IPMMU_BASE3 (0xEEE00000U) +#endif + +#define RGID_M_SDHI (38U) + +#define RGIDMEN_RTDM_BASE (0xFD441800U) /* 0xFFC41800:Remap 10 */ +#define RGIDMEN_SYDM_BASE (0xFCB51800U) /* 0xE7751800:Remap 5 */ +#define RGIDMEN_RGIDEN_MASK (0x0000FFFFU) + +#define GID_BASE (0xF12F0000U) + +#if (RCAR_LSI == RCAR_V4H) +#define IMP_IMPSLV_PRESET (0xFF902000U) /* PRESET Register (IMPSLV) */ +#define IMPSLV_PRESET_INIT_SET_VAL (0x0000000AU) /* Initial set value */ +#define IMP_SPMI_PRESET (0xFFA8E000U) /* PRESET Register (SPMI) */ +#define SPMI_PRESET_INIT_SET_VAL (0x0000000AU) /* Initial set value */ +#define IMP_SPMI_MBCTRL120 (0xFFA8C868U) /* Master Bus ConTRoL120 (SPMI) */ +#define SPMI_MBCTRL120_INIT_SET_VAL (0x00030000U) /* Initial set value */ +#define IMP_SPMI_MBCTRL130 (0xFFA8D028U) /* Master Bus ConTRoL130 (SPMI) */ +#define SPMI_MBCTRL130_INIT_SET_VAL (0x00030000U) /* Initial set value */ +#define IMP_SPMC_PRESET (0xFFAB2000U) /* PRESET Register (SPMC) */ +#define SPMC_PRESET_INIT_SET_VAL (0x00000009U) /* Initial set value */ +#endif /* (RCAR_LSI == RCAR_V4H) */ + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +static void rgid_rtdma_master_setting(void); +static void rgid_sysdma_master_setting(void); +static uint32_t get_rgidmen_rtdm_addr(uint32_t module, uint32_t ch); +static uint32_t get_rgidmen_sydm_addr(uint32_t module, uint32_t ch); +static void rgid_gid_setting(void); +#if (RCAR_SA9_TYPE == FLASH_BOOT) +static void set_rgid_rtdma_master(uint32_t module, uint32_t ch, uint32_t rgid); +#else /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ +static void set_rgid_master(uint32_t id, uint32_t val); +#endif /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ +static void rgid_register_protection(void); +static void domain_protection_setting(void); +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ + +void rgid_protection(void) +{ +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + uint32_t loop; + + REMAP_TABLE rgid_remap_tbl[RGID_SICREMAP_NUM] = { + {RGID_BASE1, 0U}, +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + {RGID_BASE2, 0U}, + {RGID_BASE3, 0U}, + {RGID_BASE4, 0U}, + {RGID_BASE5, 0U}, +#endif +}; + + REMAP_TABLE ipmmu_rgid_remap_tbl[RGID_IPMMU_SICREMAP_NUM] = { + {RGID_IPMMU_BASE1, 0U}, + {RGID_IPMMU_BASE2, 0U}, + {RGID_IPMMU_BASE3, 0U}, + }; + + /* Set domain protection registers */ + domain_protection_setting(); + + /* Set RGID of DMA (Master) */ + rgid_rtdma_master_setting(); + rgid_sysdma_master_setting(); + + /* Set RGID of GID */ + rgid_gid_setting(); + + /* Register of IPMMU Region ID Base */ + for (loop = 0U; loop < RGID_IPMMU_SICREMAP_NUM; loop++) + { + remap_register(ipmmu_rgid_remap_tbl[loop].base_addr, &ipmmu_rgid_remap_tbl[loop].rmp_addr); + } + + /* IPMMU Region ID setting */ + for(loop = 0U; loop < IPMMU_RGID_MAX; loop++) + { + /* Set access protection setting value of IPMMU */ + mem_write32(g_ipmmu_rgid_tbl[loop].addr, g_ipmmu_rgid_tbl[loop].value); + + INFO("IMRGID_IPMMU[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_ipmmu_rgid_tbl[loop].addr, mem_read32(g_ipmmu_rgid_tbl[loop].addr), g_ipmmu_rgid_tbl[loop].value); + } + + for(loop = 0U; loop < IPMMU_RGID_MAX; loop++) + { + /* Set access protection setting value of IPMMU Secure */ + mem_write32(g_ipmmu_rgid_sec_tbl[loop].addr, g_ipmmu_rgid_sec_tbl[loop].value); + + INFO("IMSECGRP_IPMMU[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_ipmmu_rgid_sec_tbl[loop].addr, mem_read32(g_ipmmu_rgid_sec_tbl[loop].addr), g_ipmmu_rgid_sec_tbl[loop].value); + } + + for(loop = 0U; loop < IPMMU_RGID_MAX; loop++) + { + /* Set access protection setting value of IPMMU Region ID Enable */ + mem_write32(g_ipmmu_rgid_en_tbl[loop].addr, g_ipmmu_rgid_en_tbl[loop].value); + + INFO("IMRGIDEN_IPMMU[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_ipmmu_rgid_en_tbl[loop].addr, mem_read32(g_ipmmu_rgid_en_tbl[loop].addr), g_ipmmu_rgid_en_tbl[loop].value); + } + + /* Unregister of IPMMU Region ID Base */ + for (loop = 0U; loop < RGID_IPMMU_SICREMAP_NUM; loop++) + { + remap_unregister(ipmmu_rgid_remap_tbl[loop].rmp_addr); + } + + /* Register of Region ID Base */ + for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++) + { + remap_register(rgid_remap_tbl[loop].base_addr, &rgid_remap_tbl[loop].rmp_addr); + } + +#if (RCAR_LSI == RCAR_V4H) + /* For the IMP Region ID setting flow, see "Table U34.3" in */ + /* "R-Car Series, V4H Series User's Manual". */ + /* Following setting is described as step7 in "Table U34.3". */ + mem_write32(IMP_IMPSLV_PRESET, IMPSLV_PRESET_INIT_SET_VAL); + mem_write32(IMP_SPMI_PRESET, SPMI_PRESET_INIT_SET_VAL); + mem_write32(IMP_SPMI_MBCTRL120, SPMI_MBCTRL120_INIT_SET_VAL); + mem_write32(IMP_SPMI_MBCTRL130, SPMI_MBCTRL130_INIT_SET_VAL); + mem_write32(IMP_SPMC_PRESET, SPMC_PRESET_INIT_SET_VAL); + + /* IMP Region ID setting */ + for(loop = 0U; loop < IMP_MASTER_MAX; loop++) + { + /* Set access protection setting value of IMP (Master) */ + mem_write32(g_imp_rgid_m_tbl[loop].addr, g_imp_rgid_m_tbl[loop].value); + + INFO("IMP_Master[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_imp_rgid_m_tbl[loop].addr, mem_read32(g_imp_rgid_m_tbl[loop].addr), g_imp_rgid_m_tbl[loop].value); + } + + for(loop = 0U; loop < IMP_SLAVE_MAX; loop++) + { + /* Set access protection setting value of IMP (Slave) */ + mem_write32(g_imp_rgid_s_tbl[loop].addr, g_imp_rgid_s_tbl[loop].value); + + INFO("IMP_Slave[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_imp_rgid_s_tbl[loop].addr, mem_read32(g_imp_rgid_s_tbl[loop].addr), g_imp_rgid_s_tbl[loop].value); + } +#endif /* (RCAR_LSI == RCAR_V4H) */ + + for(loop = 0U; loop < RGID_M_MAX; loop++) + { + /* Set access protection setting value of Region ID (Master) */ + mem_write32(g_rgid_m_tbl[loop].addr, g_rgid_m_tbl[loop].value); + + INFO("RGIDM[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_m_tbl[loop].addr, mem_read32(g_rgid_m_tbl[loop].addr), g_rgid_m_tbl[loop].value); + } + + for(loop = 0U; loop < RGID_R_MAX; loop++) + { + /* Set access protection setting value of Region ID (READ) */ + mem_write32(g_rgid_r_tbl[loop].addr, g_rgid_r_tbl[loop].value); /* Read */ + + INFO("RGIDR[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_r_tbl[loop].addr, mem_read32(g_rgid_r_tbl[loop].addr), g_rgid_r_tbl[loop].value); + } + + wdt_restart(); + + for(loop = 0U; loop < RGID_SEC_MAX; loop++) + { + /* Set access protection setting value of Region ID (Secure) */ + mem_write32(g_rgid_sec_tbl[loop].addr, g_rgid_sec_tbl[loop].value); /* Secure */ + + INFO("SEC_MODID[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_sec_tbl[loop].addr, mem_read32(g_rgid_sec_tbl[loop].addr), g_rgid_sec_tbl[loop].value); + } + + wdt_restart(); + + for(loop = 0U; loop < RGID_W_MAX; loop++) + { + /* Set access protection setting value of Region ID (Write) */ + mem_write32(g_rgid_w_tbl[loop].addr, g_rgid_w_tbl[loop].value); /* Write */ + + INFO("RGIDW[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_w_tbl[loop].addr, mem_read32(g_rgid_w_tbl[loop].addr), g_rgid_w_tbl[loop].value); + } + + wdt_restart(); + + /* Unregister of Region ID Base */ + for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++) + { + remap_unregister(rgid_remap_tbl[loop].rmp_addr); + } +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ +} +/* End of function rgid_protection(void) */ + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +static void rgid_rtdma_master_setting(void) +{ + uint32_t addr; + uint32_t val; + + /* Region ID(Master) RT-DMAC set:Region ID (i = 0-3(S4/V4H) 0-1(V4M), j = 0-15) */ + for(uint32_t module = 0U; module < RTDMA_MODULE_MAX; module++) { + for(uint32_t ch = 0U; ch < RTDMA_CH_MAX; ch++) { + addr = get_rgidmen_rtdm_addr(module, ch); + val = mem_read32(addr); + val &= ~(RGIDMEN_RGIDEN_MASK); + val |= g_rgid_rtdma_setting_value[module][ch][0U]; + mem_write32(addr, val); + + INFO("RGIDMEN_RTDM[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val); + + addr = dma_get_rtdma_regionid_addr(module, ch); + val = mem_read32(addr); + val &= ~(DMA_REGIONID_MASK); + val |= g_rgid_rtdma_setting_value[module][ch][1U]; + mem_write32(addr, val); + + INFO("RDMREGIONID_[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val); + } + } +} +/* End of function rgid_rtdma_master_setting(void) */ + +static uint32_t get_rgidmen_rtdm_addr(uint32_t module, uint32_t ch) +{ + return (RGIDMEN_RTDM_BASE + (module * 0x40U) + (ch * 0x04U)); +} +/* End of function get_rgidmen_rtdm_addr(uint32_t module, uint32_t ch) */ + +static void rgid_sysdma_master_setting(void) +{ + uint32_t addr; + uint32_t val; + + + /* Region ID(Master) SYSDMAC set:Region ID (i = 0, j = 0-15)(i = 1, j = 0-15(S4/V4H) 0-7(V4M)) */ + for(uint32_t module = 0U; module < SYSDMA_MODULE_MAX; module++) { + for(uint32_t ch = 0U; ch < SYSDMA_CH_MAX; ch++) { + if (g_rgid_sysdma_setting_value[module][ch][1U] != RGID_INVALID) + { + addr = get_rgidmen_sydm_addr(module, ch); + val = mem_read32(addr); + val &= ~(RGIDMEN_RGIDEN_MASK); + val |= g_rgid_sysdma_setting_value[module][ch][0U]; + mem_write32(addr, val); + + INFO("RGIDMEN_SYDM[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val); + + addr = dma_get_sysdma_regionid_addr(module, ch); + val = mem_read32(addr); + val &= ~(DMA_REGIONID_MASK); + val |= g_rgid_sysdma_setting_value[module][ch][1U]; + mem_write32(addr, val); + + INFO("SDMREGIONID_[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val); + } + } + } +} +/* End of function rgid_sysdma_master_setting(void) */ + +static uint32_t get_rgidmen_sydm_addr(uint32_t module, uint32_t ch) +{ + return (RGIDMEN_SYDM_BASE + (module * 0x40U) + (ch * 0x04U)); +} +/* End of function get_rgidmen_sydm_addr(uint32_t module, uint32_t ch) */ + +static void rgid_gid_setting(void) +{ + uint32_t rmp_addr; + + /* Register of GID Base */ + remap_register(GID_BASE, &rmp_addr); + + for(uint32_t loop = 0U; loop < RGID_GID_MAX; loop++) + { + /* Set access protection setting value of CCI MPU GID register */ + mem_write32(g_rgid_gid_tbl[loop].addr, g_rgid_gid_tbl[loop].value); + + INFO("GID[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_gid_tbl[loop].addr, mem_read32(g_rgid_gid_tbl[loop].addr), g_rgid_gid_tbl[loop].value); + } + + /* Unregister of GID Base */ + remap_unregister(rmp_addr); +} +/* End of function rgid_gid_setting(void) */ +#endif /* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ + +/* Change the Region ID of the Master to be used for the transfer to the value of the argument. */ +void set_master_rgid_4_tfr_mod(void) +{ +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +#if (RCAR_SA9_TYPE == FLASH_BOOT) + uint32_t module; + uint32_t ch; + + module = 0U; + ch = 0U; + set_rgid_rtdma_master(module, ch, RGID_0); +#else/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ + set_rgid_master(RGID_M_SDHI, RGID_0); +#endif/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ +#endif/* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ +} +/* End of function set_master_rgid_4_tfr_mod(void) */ + +/* Set the final expected value of Region ID. */ +void rgid_protection_final(void) +{ +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +#if (RCAR_SA9_TYPE == FLASH_BOOT) + /* Updated Master authority for RT-DMA. */ + rgid_rtdma_master_setting(); +#else/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ + /* Updated Master authority for SDHI. */ + set_rgid_master(RGID_M_SDHI, RGID_2); +#endif/* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ + /* Access protection setting function for AXI bus of Region ID register */ + rgid_register_protection(); +#endif/* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ +} +/* End of function rgid_protection_final(void) */ + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +#if (RCAR_SA9_TYPE == FLASH_BOOT) +static void set_rgid_rtdma_master(uint32_t module, uint32_t ch, uint32_t rgid) +{ + uint32_t addr; + uint32_t val; + + /* Region ID(Master) RT-DMAC set:Region ID */ + addr = get_rgidmen_rtdm_addr(module, ch); + val = mem_read32(addr); + val |= (1UL << rgid); + mem_write32(addr, val); + + INFO("RGIDMEN_RTDM[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val); + + addr = dma_get_rtdma_regionid_addr(module, ch); + val = mem_read32(addr); + val &= ~(DMA_REGIONID_MASK); + val |= rgid; + mem_write32(addr, val); + + INFO("RDMREGIONID_[%d]_CH[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", module, ch, addr, mem_read32(addr), val); +} +/* End of function set_rgid_rtdma_master(uint32_t module, uint32_t ch, uint32_t rgid) */ +#else /* (RCAR_SA9_TYPE == FLASH_BOOT) */ +/* Individual setting function of RGIDM register */ +static void set_rgid_master(uint32_t id, uint32_t rgid) +{ +#if (RCAR_LSI == RCAR_S4) + uint32_t loop; + + REMAP_TABLE rgid_remap_tbl[RGID_SICREMAP_NUM] = { + {RGID_BASE1, 0U}, + }; + + /* Register of Region ID Base */ + for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++) + { + remap_register(rgid_remap_tbl[loop].base_addr, &rgid_remap_tbl[loop].rmp_addr); + } + + /* Set access protection setting value of Region ID (Master) */ + mem_write32(g_rgid_m_tbl[id].addr, rgid); + INFO("RGIDM[%d](0x%08x) =\t0x%08x\n", id, g_rgid_m_tbl[id].addr, mem_read32(g_rgid_m_tbl[id].addr)); + + /* Unregister of Region ID Base */ + for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++) + { + remap_unregister(rgid_remap_tbl[loop].rmp_addr); + } +#endif /* #if (RCAR_LSI == RCAR_S4) */ +} +/* End of function set_rgid_master(uint32_t id, uint32_t rgid) */ +#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + +/* Access protection setting function for AXI bus of Region ID register */ +static void rgid_register_protection(void) +{ + uint32_t loop; + + REMAP_TABLE rgid_remap_tbl[RGID_SICREMAP_NUM] = { + {RGID_BASE1, 0U}, +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + {RGID_BASE2, 0U}, + {RGID_BASE3, 0U}, + {RGID_BASE4, 0U}, + {RGID_BASE5, 0U}, +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + }; + + /* Register of Region ID Base */ + for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++) + { + remap_register(rgid_remap_tbl[loop].base_addr, &rgid_remap_tbl[loop].rmp_addr); + } + + for(loop = 0U; loop < RGID_AXI_MAX; loop++) + { + /* Set access protection setting value of Region ID (AXI bus of Region ID register) */ + mem_write32(g_rgid_axi_tbl[loop].addr, g_rgid_axi_tbl[loop].value); + + INFO("RGID_AXI[%d](0x%08x) =\t0x%08x \tsetting value = 0x%08x\n", loop, g_rgid_axi_tbl[loop].addr, mem_read32(g_rgid_axi_tbl[loop].addr), g_rgid_axi_tbl[loop].value); + } + + /* Unregister of Region ID Base */ + for (loop = 0U; loop < RGID_SICREMAP_NUM; loop++) + { + remap_unregister(rgid_remap_tbl[loop].rmp_addr); + } +} +/* End of function rgid_register_protection(void) */ + +static void domain_protection_setting(void) +{ + uint32_t loop; + + /* Set CPG domain write access control register */ + for(loop = 0U; loop <= CPG_PROTECTION; loop++) + { + cpg_reg_write((CPG_D1WACRA00 + (loop * 4U)), (CPG_D1WACRA00 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D2WACRA00 + (loop * 4U)), (CPG_D2WACRA00 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D3WACRA00 + (loop * 4U)), (CPG_D3WACRA00 + (loop * 4U)), WRITE_ENABLE); + } + + /* Set PFC domain write access control register */ + /* Port Group0 */ + pfc_reg_write(PFC_DM1PR0_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR0_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR0_RW, WRITE_ENABLE); + + /* Port Group1 */ + pfc_reg_write(PFC_DM1PR1_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR1_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR1_RW, WRITE_ENABLE); + + /* Port Group2 */ + pfc_reg_write(PFC_DM1PR2_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR2_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR2_RW, WRITE_ENABLE); + + /* Port Group3 */ + pfc_reg_write(PFC_DM1PR3_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR3_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR3_RW, WRITE_ENABLE); + + /* Port Group4 */ + pfc_reg_write(PFC_DM1PR4_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR4_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR4_RW, WRITE_ENABLE); + + /* Port Group5 */ + pfc_reg_write(PFC_DM1PR5_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR5_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR5_RW, WRITE_ENABLE); + + /* Port Group6 */ + pfc_reg_write(PFC_DM1PR6_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR6_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR6_RW, WRITE_ENABLE); + + /* Port Group7 */ + pfc_reg_write(PFC_DM1PR7_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR7_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR7_RW, WRITE_ENABLE); + +#if (RCAR_LSI == RCAR_V4H) + /* Port Group8 */ + pfc_reg_write(PFC_DM1PR8_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PR8_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PR8_RW, WRITE_ENABLE); +#endif/* #if (RCAR_LSI == RCAR_V4H) */ + + /* System Group */ + pfc_reg_write(PFC_DM1PRSYS_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM2PRSYS_RW, WRITE_ENABLE); + pfc_reg_write(PFC_DM3PRSYS_RW, WRITE_ENABLE); + + /* Set SYSC domain write access control register */ + for(loop = 0U; loop <= SYSC_PROTECTION; loop++) + { + mem_write32((SYSC_SYSCD1WACR0 + (loop * 4U)), WRITE_ENABLE); + mem_write32((SYSC_SYSCD2WACR0 + (loop * 4U)), WRITE_ENABLE); + mem_write32((SYSC_SYSCD3WACR0 + (loop * 4U)), WRITE_ENABLE); + } + + /* Set Reset domain write access control register */ + for(loop = 0U; loop <= RESET_PROTECTION; loop++) + { + cpg_reg_write((CPG_D1WACR_MSTPCR0 + (loop * 4U)), (CPG_D1WACR_MSTPCR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D1WACR_RAHSR0 + (loop * 4U)), (CPG_D1WACR_RAHSR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D1WACR_SRCR0 + (loop * 4U)), (CPG_D1WACR_SRCR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D1WACR_SRSTCLR0 + (loop * 4U)), (CPG_D1WACR_SRSTCLR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D2WACR_MSTPCR0 + (loop * 4U)), (CPG_D2WACR_MSTPCR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D2WACR_RAHSR0 + (loop * 4U)), (CPG_D2WACR_RAHSR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D2WACR_SRCR0 + (loop * 4U)), (CPG_D2WACR_SRCR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D2WACR_SRSTCLR0 + (loop * 4U)), (CPG_D2WACR_SRSTCLR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D3WACR_MSTPCR0 + (loop * 4U)), (CPG_D3WACR_MSTPCR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D3WACR_RAHSR0 + (loop * 4U)), (CPG_D3WACR_RAHSR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D3WACR_SRCR0 + (loop * 4U)), (CPG_D3WACR_SRCR0 + (loop * 4U)), WRITE_ENABLE); + cpg_reg_write((CPG_D3WACR_SRSTCLR0 + (loop * 4U)), (CPG_D3WACR_SRSTCLR0 + (loop * 4U)), WRITE_ENABLE); + } +} +/* End of function domain_protection_setting(void) */ +#endif/* #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/protect/stack_protect.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/protect/stack_protect.c new file mode 100644 index 0000000..21a6493 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/protect/stack_protect.c @@ -0,0 +1,86 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Stack protect function + ******************************************************************************/ + /****************************************************************************** + * @file stack_protect.c + * - Version : 0.01 + * @brief Check for Stack Smashing Attacks. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 31.01.2023 0.01 First Release + *****************************************************************************/ + +#include +#include + +/* Specify fixed canary value as reference implementation. */ +#define CANARY_VAL (0xB9DFF6A0U) + +#define STACK_PROTECT_ENABLE (1U) + +/* Save canary to __stack_chk_guard. */ +extern uintptr_t __stack_chk_guard; +__attribute__((section(".canary"))) uintptr_t __stack_chk_guard; + +/* Prototype */ +extern void __ghs_set_stack_chk_guard(void); +#if (STACK_PROTECT == STACK_PROTECT_ENABLE) +extern void __stack_chk_fail(void); +static inline uintptr_t *__ghs_get_stack_chk_guard_address(void); +#endif + +void __ghs_set_stack_chk_guard(void) +{ +#if (STACK_PROTECT == STACK_PROTECT_ENABLE) + /* Initialize the stack canary before any code that may require a stack canary. */ + /* So don't add valiables larger than 8-bytes to this function. */ + /* Don't call function that uses stack canaries from this function. */ + /* If customize CANARY_VAL to random value, don't allow the function */ + /* to be inlined or this function may require a canary. */ + + *__ghs_get_stack_chk_guard_address() = (uintptr_t)CANARY_VAL; + +#endif +} +/* End of function __ghs_set_stack_chk_guard(void) */ + +#if (STACK_PROTECT == STACK_PROTECT_ENABLE) +static inline uintptr_t *__ghs_get_stack_chk_guard_address(void) +{ + /* Don't modify this function. */ + return &__stack_chk_guard; +} +/* End of function __ghs_get_stack_chk_guard_address(void) */ + +void __stack_chk_fail(void) +{ + ERROR("Stack smashing detected\n"); + panic; +} +/* End of function __stack_chk_fail(void) */ +#endif /* (STACK_PROTECT == STACK_PROTECT_ENABLE) */ diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/remap/remap.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/remap/remap.c new file mode 100644 index 0000000..337748d --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/remap/remap.c @@ -0,0 +1,286 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : remap driver + ******************************************************************************/ +/****************************************************************************** + * @file remap.c + * - Version : 0.06 + * @brief 1. Setting of SIC REMAP AREA. + * 2. Release of SIC REMAP AREA. + * 3. Calculation of logical address. + * 4. Calculation of physical address. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Modify remap_reg_write function to inline. + * : 06.01.2022 0.03 Static analysis support + * : 23.05.2022 0.04 Supported SICREMAP address for S4 ver1.0 + * S4/V4H differences applied to s_remap_tbl. + * : 15.05.2023 0.05 Add get_cfremap_addr() function to jump + * the secure firmware on CF remap Area. + * : 21.08.2023 0.06 Add support for V4M. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +/* Range of SICREMAP2M register */ +#define REMAP_REG_MAX (16U) + +#define REMAP_2M_BITS (21U) +#define REMAP_2M_SIZE ((uint32_t)1U << REMAP_2M_BITS) +#define REMAP_2M_MASK (REMAP_2M_SIZE - 1U) +#define REMAP_TBL_MAX (sizeof(s_remap_tbl)/sizeof(s_remap_tbl[0])) +#define REMAP_UNUSED (0xFFFFFFFFU) + +typedef struct { + uint32_t number; + uint32_t address; +}st_remap_address_table_t; + +/* Remap management table */ +static st_remap_address_table_t s_remap_tbl[REMAP_REG_MAX] = { + [0] = {REMAP_UNUSED, 0x00000000U}, + [1] = {REMAP_UNUSED, 0x00000000U}, + [2] = {REMAP_UNUSED, 0x00000000U}, + [3] = {REMAP_UNUSED, 0x00000000U}, +#if (RCAR_LSI == RCAR_S4) + [4] = {4, 0xD8E00000}, /* MCU */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + [4] = {REMAP_UNUSED, 0x00000000U}, +#endif + [5] = {5, 0xE7600000U}, /* Region ID */ + [6] = {6, 0xE7200000U}, /* SYS-DMAC0 */ + [7] = {7, 0xE6400000U}, /* HSCIF */ + [8] = {8, 0xEE000000U}, /* MMC */ + [9] = {9, 0xE6E00000U}, /* SCIF */ + [10] = {10, 0xFFC00000U}, /* RT-DMAC0,PFC(MCU) */ + [11] = {11, 0xEE200000U}, /* RPC */ + [12] = {12, 0xE6200000U}, /* ECM,AP-System Core */ + [13] = {13, 0xE6000000U}, /* PFC,GPIO,CPGA,RESET */ + [14] = {14, 0xE6600000U}, /* CC63S,AXMM,QoS,FCPR */ + [15] = {15, 0xEB200000U}, /* RT-SRAM */ +}; + +static inline uint32_t get_sicremap2m_addr(uint32_t num) +{ + return (REMAP_BASE + (num * 0x0004U)); +} +/* End of function get_sicremap2m_addr(uint32_t num) */ + +static inline void remap_reg_write(uint32_t num, uint32_t value) +{ + /* Specific write Procedure for Write-Protected Register. */ + do + { + mem_write32(ICUMX_PROT0PCMD, PROTCMD_START); + mem_write32(get_sicremap2m_addr(num), value); + mem_write32(get_sicremap2m_addr(num), ~value); + mem_write32(get_sicremap2m_addr(num), value); + } while (mem_read32(ICUMX_PROT0PS) == PROTS0ERR); +} +/* End of function remap_reg_write(uint32_t num, uint32_t value) */ + +void remap_register(uint32_t addr, uint32_t *remap_addr) +{ + uint32_t loop; + uint32_t set_addr; + + /* Check unused area in order from the top of + the remap management table. */ + for (loop = 0U; loop < REMAP_TBL_MAX; ++loop) + { + if (REMAP_UNUSED == s_remap_tbl[loop].number) + { + break; + } + } + + /* When necessary area can not be secured */ + if (REMAP_TBL_MAX <= loop) + { + ERROR("There is no space in the logical address area.\n"); + panic; + } + + syncm(); + + /* Set remap area */ + set_addr = addr & ~REMAP_2M_MASK; + + /* Update the table managing the remap space */ + s_remap_tbl[loop].address = set_addr; + s_remap_tbl[loop].number = (uint8_t)loop; + /* Set SICREMAP register */ + remap_reg_write(loop, set_addr); + INFO("s_remap_tbl[%d].number = 0x%x\n",loop,s_remap_tbl[loop].number); + INFO("s_remap_tbl[%d].address = 0x%x\n",loop,s_remap_tbl[loop].address); + + syncm(); + + /* Calculating the logical address of the + address received as an argument */ + *remap_addr = icu_remap_calc(loop); + *remap_addr += addr & REMAP_2M_MASK; +} +/* End of function remap_register(uint32_t addr, uint32_t size, uint32_t *remap_addr) */ + +void remap_unregister(uint32_t remap_addr) +{ + uint32_t loop; + + /* Is the remap space where the address of the argument is used? */ + for (loop = 0U; loop < REMAP_TBL_MAX; ++loop) + { + INFO("s_remap_tbl[%d].number = 0x%x\n",loop,s_remap_tbl[loop].number); + if ((REMAP_UNUSED != s_remap_tbl[loop].number) + && ((icu_remap_calc(loop) <= remap_addr) + && (remap_addr < icu_remap_calc(loop + 1U)))) + { + break; + } + } + + /* When an area to release can not be found */ + if (REMAP_TBL_MAX <= loop) + { + ERROR("Not registered in the logical address.\n" + "remap address = 0x%x\n",remap_addr); + panic; + } + syncm(); + + /* release remap area */ + /* Update the table managing the remap space */ + s_remap_tbl[loop].address = 0U; + s_remap_tbl[loop].number = REMAP_UNUSED; + /* Release SICREMAP register */ + remap_reg_write(loop, icu_remap_calc(loop)); + + syncm(); +} +/* End of function remap_unregister(uint32_t remap_addr) */ + +uint32_t remap_get_phys_addr(uint32_t remap_addr) +{ + uint32_t phys_addr; + uint32_t reg; + + /* It checks whether the argument is within the range + of the logical address. */ + if ((ICU_REMAP0 > remap_addr) + || (icu_remap_calc(REMAP_REG_MAX) <= remap_addr)) + { + ERROR("Address convert error.\n" + "source address = 0x%x\n",remap_addr); + panic; + } + + /* Calculate the physical address of the argument */ + phys_addr = remap_addr - ICU_REMAP0; + phys_addr >>= REMAP_2M_BITS; + reg = get_sicremap2m_addr(phys_addr); + reg = mem_read32(reg); + phys_addr = reg + (remap_addr & REMAP_2M_MASK); + + return phys_addr; +} +/* End of function remap_get_phys_addr(uint32_t remap_addr) */ + +uint32_t remap_get_remap_addr(uint32_t phys_addr) +{ + uint32_t remap_addr; + uint32_t reg; + uint32_t loop; + + /* It checks whether the argument is within the range + of the physical address registered in SICREMAP. */ + for (loop = 0U; loop < REMAP_REG_MAX; loop++) + { + reg = mem_read32(get_sicremap2m_addr(loop)); + if ((reg <= phys_addr) + && (phys_addr <= (reg + REMAP_2M_MASK))) + { + break; + } + } + + /* argument value is not used in the remap area. */ + if (REMAP_REG_MAX <= loop) + { + ERROR("Address convert error.\n" + "source address = 0x%x\n",phys_addr); + panic; + } + + /* Calculate the logical address of the argument */ + remap_addr = icu_remap_calc(loop); + remap_addr += phys_addr - reg; + + return remap_addr; +} +/* End of function remap_get_remap_addr(uint32_t phys_addr) */ + +uint32_t get_cfremap_addr(uint32_t fetch_addr) +{ + uint32_t cf_remap_addr = 0x0U; + uint32_t cf_current_base = mem_read32(ICUMX_CFREMAP); + + /* Get current setting of "physical address for cf remap base", + and calculate cf remap address of target fetch */ + cf_remap_addr = fetch_addr - cf_current_base; + + /* Check whether the calculated address is outside of Code Fetch area */ + if ((CFREMAP_AREA_SIZE <= cf_remap_addr) || (fetch_addr < cf_current_base)) + { + ERROR("Target fetch address is invalid: 0x%08x\n", fetch_addr); + panic; + } + + return cf_remap_addr; +} + +void set_sicremap_s4v10(void) +{ +#if (RCAR_LSI == RCAR_S4) + /* Change the setting of SICREMAP for S4 Ver1.0 to be the setting of SICREMAP for S4 Ver1.1. */ + remap_reg_write(ICU_REMAP_NUM_RGID, ICU_REMAP_RGID); /* SIC REMAP5:Region ID */ + remap_reg_write(ICU_REMAP_NUM_MCU , ICU_REMAP_MCU); /* SIC REMAP4:MCU */ +#endif +} +/* End of function set_sicremap_s4v10(void) */ + +void set_sicremap_fcpr(void) +{ + remap_reg_write(ICU_REMAP_NUM_FCPR, ICU_REMAP_FCPR); /* SIC REMAP14:FCPR */ +} +/* End of function set_sicremap_fcpr(void) */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/rom_api/rom_api.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/rom_api/rom_api.c new file mode 100644 index 0000000..62a06ca --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/rom_api/rom_api.c @@ -0,0 +1,381 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : boot ROM API + ******************************************************************************/ +/****************************************************************************** + * @file rom_api.c + * - Version : 0.13 + * @brief 1.Call ROM_SecureBootAPI. + * 2.Call ROM_GetLcsAPI. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : (30.11.2021 0.02) Modify argument of ROM_GetLcs. + * : 23.05.2022 0.03 Supported Secure boot for ROM API. + * : 05.08.2022 0.04 Add sw_version_check function and macros. + * Add sw_version_check function call to + * rom_secureboot function. + * : 30.09.2022 0.05 Add auth_min_ver_tbl function. + * : 09.12.2022 0.06 Remove argument 'is_verify' used in + * auth_min_ver_tbl function. + * : 14.02.2023 0.07 Add Hash save process to rom_secureboot. + * : 14.04.2023 0.08 Add certificate authentication functions. + * : 21.08.2023 0.09 Add support for V4M. + * : 11.01.2024 0.10 Add process that change writing privilege + * to System RAM by ICUMX. + * : 08.02.2024 0.11 Update icu_remove_write_access calling + * condition to always calling. + * : 05.12.2024 0.12 Remove icu_remove_write_access function. + * : 26.05.2025 0.13 Add verification support for the OP-TEE + * content cert. + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* For software version check */ +#define TBL_VERSION_CHECK_DISABLE (0U) +#define TFMV_MIN_VER_TBL_TOP (0xFDE35000U) /* remapped address */ +#define NTFMV_MIN_VER_TBL_TOP (0xFDE35800U) /* remapped address */ +#define NTFMV_LD_ID_OFST (7U) +#define SW_MIN_VER_TBL_UNIT (0x10U) +#define TBL_VER_OFST (4U) +#define TBL_IMG_OFST (8U) + +/* Hash size definition */ +#define SECURE_BOOT_COMPARE_HASH_SIZE_BYTE (64U) /* SHA-256 * 2 */ +/* Definitions for get_hash_save_addr() */ +#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) +/* cnt=0: TFMV Software minimum version table */ +/* cnt=1: NTFMV Software minimum version table */ +/* cnt=2: CR52 2nd IPL */ +#define CR52_IPL_HASH_SAVE_CNT (0x2U) +/* cnt=3: Secure FW */ +#define SECURE_FW_HASH_SAVE_CNT (0x3U) +#else +#define CR52_IPL_HASH_SAVE_CNT (0x0U) +#define SECURE_FW_HASH_SAVE_CNT (0x1U) +#endif +#define CR52_IPL_HASH_SAVE_ADDR (0xE635FF40U) /* Physical address */ +#define SECURE_FW_HASH_SAVE_ADDR (0xE635FFC0U) /* Physical address */ +/* For TFMV/NTFMV Software minimum version table */ +#define OTHERS_HASH_SAVE_ADDR (0xE635FC00U) /* Physical address */ + +static uint32_t call_ROM_SecureBootVerify(uint32_t *pKeyCert, uint32_t *pContentCert); +static uint32_t call_ROM_SecureBootCompare(uint32_t *pContentCert, uint32_t *hash, uint32_t hash_size); +static uint32_t call_ROM_SecureBootDecrypt(uint32_t *pContentCert); +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +static uint32_t get_hash_save_addr(void); +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +extern uint32_t is_verify; + +void rom_secureboot(LOAD_INFO* li) +{ + uint32_t *keycert = (uint32_t*)li->key_cert_addr; + uint32_t *contentcert = (uint32_t*)li->cnt_cert_addr; +#if (RCAR_LSI == RCAR_S4) + uint32_t hash[16]; /* hash space is 64byte */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + uint32_t *hash; /* SystemRAM logical address */ +#endif /* (RCAR_LSI == RCAR_S4) */ + uint32_t ret; + + /* If boot mode is Secure BOOT, the ROM API is used to authenticate the image. */ + if (NORMAL_BOOT != is_verify) + { + /* Content cert certification */ + ret = call_ROM_SecureBootVerify(keycert, contentcert); + if (ROMAPI_OK != ret) + { + ERROR("%s Certificate Verification Failed!!!(0x%x)\n", li->name, ret); + panic; + } + + /* Decryption image */ + ret = call_ROM_SecureBootDecrypt(contentcert); + if ((ROMAPI_OK != ret) && (ROM_ERR_IMG_VERIFIER_NO_ENCRYPT_IMG != ret)) + { + ERROR("%s Decryption Failed!!!(0x%x)\n", li->name, ret); + panic; + } + } /* if (NORMAL_BOOT != is_verify) */ + + /* + * System RAM is divided two regions that Cx 2nd IPL and others by RAM protection. + * After loading and decrypting Cx 2nd IPL, writing privilege to Cx 2nd IPL region + * from RGID0(ICUMX) to be disabled and then comparing Hash. + * This implementation is according to operation in SAN (Application Domain Safety Application Note) + * chapter 6.23.5. + */ +/* Remove the following comment out if user want to enable protection of System Ram. */ +/* if(CA_PROGRAM_ID == (li->image_id)) */ +/* { */ +/* icu_remove_write_access(); */ +/* } */ + + if (NORMAL_BOOT != is_verify) + { + /* Hash save SystemRAM logical address calculation (V4H only) */ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + hash = (uint32_t *)get_hash_save_addr(); +#endif + /* Image certification */ + ret = call_ROM_SecureBootCompare(contentcert, hash, SECURE_BOOT_COMPARE_HASH_SIZE_BYTE); + if (ROMAPI_OK != ret) + { + ERROR("%s Image Verification Failed!!!(0x%x)\n", li->name, ret); + panic; + } + + /* Software version check */ + sw_version_check(li); + } /* if (NORMAL_BOOT != is_verify) */ +} +/* End of function rom_secureboot(LOAD_INFO* li) */ + +static uint32_t call_ROM_SecureBootVerify(uint32_t *pKeyCert, uint32_t *pContentCert) +{ + /* Secure Boot API address */ + static const uintptr_t s_rom_secureboot_verify_addr = ROM_SECUREBOOT_VERIFY; + ROM_SECUREBOOT_VERIFY_API func; + uint32_t ret; + + func = (ROM_SECUREBOOT_VERIFY_API)s_rom_secureboot_verify_addr; + + ret = func(pKeyCert, pContentCert); + return ret; +} +/* End of function call_ROM_SecureBootVerify(uint32_t *pKeyCert, uint32_t *pContentCert) */ + +static uint32_t call_ROM_SecureBootCompare(uint32_t *pContentCert, uint32_t *hash, uint32_t hash_size) +{ + /* Secure Boot API address */ + static const uintptr_t s_rom_secureboot_compare_addr = ROM_SECUREBOOT_COMPARE; + ROM_SECUREBOOT_COMPARE_API func; + uint32_t ret; + + func = (ROM_SECUREBOOT_COMPARE_API)s_rom_secureboot_compare_addr; + + ret = func(pContentCert, hash, hash_size); + return ret; +} +/* End of function call_ROM_SecureBootCompare(uint32_t *pContentCert, uint32_t *hash, uint32_t hash_size) */ + +static uint32_t call_ROM_SecureBootDecrypt(uint32_t *pContentCert) +{ + /* Secure Boot API address */ + static const uintptr_t s_rom_secureboot_decrypt_addr = ROM_SECUREBOOT_DECRYPT; + ROM_SECUREBOOT_DECRYPT_API func; + uint32_t ret; + + func = (ROM_SECUREBOOT_DECRYPT_API)s_rom_secureboot_decrypt_addr; + + ret = func(pContentCert); + return ret; +} +/* End of function call_ROM_SecureBootDecrypt(uint32_t *pContentCert) */ + +uint32_t call_ROM_GetLcs(uint32_t *pLcs, uint32_t lcs_size) +{ + /* Get LCS stete API address */ + static const uintptr_t s_rom_getlcs_addr = ROM_GETLCS; + ROM_GETLCS_API func; + uint32_t ret; + + func = (ROM_GETLCS_API)s_rom_getlcs_addr; + + ret = func(pLcs, lcs_size); + return ret; +} +/* End of function call_ROM_GetLcs(uint32_t *pLcs, uint32_t lcs_size) */ + +void sw_version_check(const LOAD_INFO* li) +{ +#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) + uint32_t ver_tbl_base; + uint32_t ver_tbl_addr; + uint32_t ver_tbl_version; + uint32_t ver_tbl_ofst; + uint32_t img_version; + uint32_t id_adj = 0U; + uint32_t val; + uint32_t rmp_addr; + uint32_t load_id; + + load_id = get_load_info_id(li); + + if (load_id < TFMV_MIN_VER_TBL_ID) + { + /* If image is other than Software minimum version table */ + if(li->key_cert_addr == TFMV_KEY_CERT_ADDR) + { + /* Refer to TFMV Software minimum version table */ + ver_tbl_base = TFMV_MIN_VER_TBL_TOP; /* 0xFDE35000 */ + } + else + { + /* Refer to NTFMV Software minimum version table */ + ver_tbl_base = NTFMV_MIN_VER_TBL_TOP; /* 0xFDE35800 */ + id_adj = NTFMV_LD_ID_OFST; + } + + /* Calculate Software minimum version address for Load ID */ + ver_tbl_addr = ver_tbl_base + (SW_MIN_VER_TBL_UNIT * (load_id - id_adj)); + + val = mem_read32(ver_tbl_addr); + if(val != TBL_VERSION_CHECK_DISABLE) + { + /* If a flag in Software minimum version is enable */ + ver_tbl_version = mem_read32(ver_tbl_addr + TBL_VER_OFST); + ver_tbl_ofst = mem_read32(ver_tbl_addr + TBL_IMG_OFST); + + /* Read image version in Load ID's image */ + remap_register(li->boot_addr + ver_tbl_ofst, &rmp_addr); + img_version = mem_read32(rmp_addr); + remap_unregister(rmp_addr); + + if(img_version < ver_tbl_version) + { + ERROR("%s Software version check result is failed.\n", li->name); + panic; + } + } + } +#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */ +} +/* End of function sw_version_check(const LOAD_INFO* li) */ + +void auth_min_ver_tbl(LOAD_INFO* li) +{ +#if (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) + rom_secureboot(&li[TFMV_MIN_VER_TBL_ID]); + rom_secureboot(&li[NTFMV_MIN_VER_TBL_ID]); +#endif /* (SW_VERSION_CHECK == OPT_VERSION_CHECK_ENABLE) */ +} +/* End of function auth_min_ver_tbl(LOAD_INFO* li) */ + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +static uint32_t get_hash_save_addr(void) +{ + uint32_t hash_addr; + static uint32_t cnt = 0U; + + if(cnt == CR52_IPL_HASH_SAVE_CNT) + { + /* When loading image is Cx 2nd IPL. */ + hash_addr = remap_get_remap_addr(CR52_IPL_HASH_SAVE_ADDR); + } + else if(cnt == SECURE_FW_HASH_SAVE_CNT) + { + /* When loading image is Secure FW. */ + hash_addr = remap_get_remap_addr(SECURE_FW_HASH_SAVE_ADDR); + } + else + { + /* When loading image is TFMV/NTFMV Software minimum version table. */ + hash_addr = remap_get_remap_addr(OTHERS_HASH_SAVE_ADDR); + } + /* Count how many times this function called. */ + cnt++; + + if(cnt > SECURE_FW_HASH_SAVE_CNT + 1U) + { + NOTICE("get_hash_save_addr: Unexpected cnt value.\n"); + } + + return hash_addr; +} +/* End of function get_hash_save_addr(void) */ + +void preload_verify_cntcert(const LOAD_INFO* li) +{ + if (NORMAL_BOOT != is_verify) + { + /* Set error code value as initial value */ + int32_t ret = -1; + + /* verify the content cert of RTOS */ + ret = call_ROM_SecureBootVerify((uint32_t *)li[RTOS_ID].key_cert_addr, (uint32_t *)li[RTOS_ID].cnt_cert_addr); + if (ROMAPI_OK != ret) + { + ERROR("%s Certificate Verification Failed!!!(0x%x)\n", li[RTOS_ID].name, ret); + panic; + } + + /* verify the content cert of Secure FW */ + ret = call_ROM_SecureBootVerify((uint32_t *)li[SECURE_FW_ID].key_cert_addr, (uint32_t *)li[SECURE_FW_ID].cnt_cert_addr); + if (ROMAPI_OK != ret) + { + ERROR("%s Certificate Verification Failed!!!(0x%x)\n", li[SECURE_FW_ID].name, ret); + panic; + } + + /* verify the content cert of CxIPL */ + ret = call_ROM_SecureBootVerify((uint32_t *)li[CA_PROGRAM_ID].key_cert_addr, (uint32_t *)li[CA_PROGRAM_ID].cnt_cert_addr); + if (ROMAPI_OK != ret) + { + ERROR("%s Certificate Verification Failed!!!(0x%x)\n", li[CA_PROGRAM_ID].name, ret); + panic; + } + + /* verify the content cert of Secure Monitor */ + ret = call_ROM_SecureBootVerify((uint32_t *)li[CA_OPTIONAL_ID].key_cert_addr, (uint32_t *)li[CA_OPTIONAL_ID].cnt_cert_addr); + if (ROMAPI_OK != ret) + { + ERROR("%s Certificate Verification Failed!!!(0x%x)\n", li[CA_OPTIONAL_ID].name, ret); + panic; + } + + /* verify the content cert of U-boot */ + ret = call_ROM_SecureBootVerify((uint32_t *)li[CA_OPTIONAL_ID + 1U].key_cert_addr, (uint32_t *)li[CA_OPTIONAL_ID + 1U].cnt_cert_addr); + if (ROMAPI_OK != ret) + { + ERROR("%s Certificate Verification Failed!!!(0x%x)\n", li[CA_OPTIONAL_ID + 1U].name, ret); + panic; + } + +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) + /* verify the content cert of OP-TEE */ + ret = call_ROM_SecureBootVerify((uint32_t *)li[CA_OPTIONAL_ID + 2U].key_cert_addr, (uint32_t *)li[CA_OPTIONAL_ID + 2U].cnt_cert_addr); + if (ROMAPI_OK != ret) + { + ERROR("%s Certificate Verification Failed!!!(0x%x)\n", li[CA_OPTIONAL_ID + 2U].name, ret); + panic; + } +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ + } +} + +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/s4/sa9.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/s4/sa9.c new file mode 100644 index 0000000..94e1618 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/s4/sa9.c @@ -0,0 +1,289 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 9(0x240000) + ******************************************************************************/ + +#include + +#define FLASH_BOOT (0U) +#define EMMC_BOOT (1U) +#define CA_IPL (0U) +#define BL31 (1U) + +/* CA program load num */ +#define CA_IMAGE_NUM (0x00000003U) +/* Source address on flash for Secure FW */ +#define SECURE_FW_SRC_ADDRESS (0x00280000U) +/* Source address on flash for RTOS */ +#define RTOS_SRC_ADDRESS (0x00500000U) +/* Source address on flash for ICUMH program */ +#define ICUMH_PROG_SRC_ADDRESS (0x00380000U) +/* Source address on flash for G4MH program (1st) */ +#define G4MH_PROG_SRC_ADDRESS (0x00900000U) +/* Source address on flash for G4MH program (2nd) */ +#define G4MH_PROG_02_SRC_ADDRESS (0x00A00000U) +#if (CA_LOAD_TYPE == CA_IPL) +/* Source address on flash for CX IPL */ +#define CX_IPL_SRC_ADDRESS (0x00480000U) +#else +/* Reserved */ +#define CX_IPL_SRC_ADDRESS (0x00000000U) +#endif +/* ----------- customized ----------- */ +/* Source address on flash for BL31 */ +#define CA_PROG_01_SRC_ADDRESS (0x00E00000U) +/* Source address on flash for OP-TEE */ +#define CA_PROG_02_SRC_ADDRESS (0x00E80000U) +/* Source address on flash for U-Boot */ +#define CA_PROG_03_SRC_ADDRESS (0x00F80000U) +/* Reserved */ +#define CA_PROG_04_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_05_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_06_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_07_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_08_SRC_ADDRESS (0x00000000U) +/* ----------- customized ----------- */ + +#if (RCAR_SA9_TYPE == FLASH_BOOT) +#define SECURE_FW_PARTITION (0x00000000U) +#define RTOS_PARTITION (0x00000000U) +#define ICUMH_PROG_PARTITION (0x00000000U) +#define G4MH_PROG_PARTITION (0x00000000U) +#define G4MH_PROG_02_PARTITION (0x00000000U) +#define CX_IPL_PARTITION (0x00000000U) + #if (CA_LOAD_TYPE == CA_IPL) +#define CA_PROG_01_PARTITION (0x00000001U) +#define CA_PROG_02_PARTITION (0x00000001U) +#define CA_PROG_03_PARTITION (0x00000001U) +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) + #else /* #if (CA_LOAD_TYPE == CA_IPL) */ +#define CA_PROG_01_PARTITION (0x00000000U) +#define CA_PROG_02_PARTITION (0x00000000U) +#define CA_PROG_03_PARTITION (0x00000000U) +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) + #endif /* #if (CA_LOAD_TYPE == CA_IPL) */ +#else /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ +#define SECURE_FW_PARTITION (0x00000001U) +#define RTOS_PARTITION (0x00000001U) +#define ICUMH_PROG_PARTITION (0x00000001U) +#define G4MH_PROG_PARTITION (0x00000001U) +#define G4MH_PROG_02_PARTITION (0x00000001U) +#define CX_IPL_PARTITION (0x00000001U) +#define CA_PROG_01_PARTITION (0x00000001U) +#define CA_PROG_02_PARTITION (0x00000001U) +#define CA_PROG_03_PARTITION (0x00000001U) +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) +#endif /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ + +#if (RCAR_SA9_TYPE != EMMC_BOOT) +/* Test data for QSPI DDR mode */ +#define QSPI_TESTDATA (0x5A5AA5A5U) +#else +#define QSPI_TESTDATA (0x00000000U) +#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + +/* Destination address for Secure FW */ +#define SECURE_FW_ADDRESS (0xEB240000U) +#define SECURE_FW_ADDRESSH (0x00000000U) +/* Destination size for Secure FW */ +#define SECURE_FW_DST_SIZE (0x00028000U) /* 640KiB / 4 */ +/* Destination address for RTOS */ +#define RTOS_ADDRESS (0xE2100000U) +#define RTOS_ADDRESSH (0x00000000U) +/* Destination size for RTOS */ +#define RTOS_DST_SIZE (0x00100000U) /* 4MiB / 4 */ +/* Destination address for ICUMH program */ +#define ICUMH_PROG_ADDRESS (0x10500000U) +#define ICUMH_PROG_ADDRESSH (0x00000000U) +/* Destination size for ICUMH program */ +#define ICUMH_PROG_DST_SIZE (0x00040000U) /* 1MiB / 4 */ +/* Destination address for G4MH program (1st) */ +#define G4MH_PROG_ADDRESS (0x10000000U) +#define G4MH_PROG_ADDRESSH (0x00000000U) +/* Destination size for G4MH program (1st) */ +#define G4MH_PROG_DST_SIZE (0x00040000U) /* 1MiB / 4 */ +/* Destination address for G4MH program (2nd) */ +#define G4MH_PROG_02_ADDRESS (0x10100000U) +#define G4MH_PROG_02_ADDRESSH (0x00000000U) +/* Destination size for G4MH program (2nd) */ +#define G4MH_PROG_02_DST_SIZE (0x00040000U) /* 1MiB / 4 */ +#if (CA_LOAD_TYPE == CA_IPL) +/* Destination address for CA Loader */ +#define CX_IPL_ADDRESS (0xE6300000U) +#define CX_UPL_ADDRESSH (0x00000000U) +/* Destination size for CA Loader */ +#define CX_IPL_SIZE (0x0000C000U) /* 192KiB / 4 */ +#else /* (CA_LOAD_TYPE == CA_IPL) */ +/* CX IPL Reserved */ +#define CX_IPL_ADDRESS (0x00000000U) +#define CX_UPL_ADDRESSH (0x00000000U) +#define CX_IPL_SIZE (0x00000000U) +#endif /* (CA_LOAD_TYPE == CA_IPL) */ +/* ----------- customized ----------- */ +/* Destination address for BL31 */ +#define CA_PROG_01_ADDRESS (0x46400000U) +#define CA_PROG_01_ADDRESSH (0x00000000U) +#define CA_PROG_01_SIZE (0x00008800U) /* 136KiB / 4 */ +/* Destination address for OP-TEE */ +#define CA_PROG_02_ADDRESS (0x44100000U) +#define CA_PROG_02_ADDRESSH (0x00000000U) +#define CA_PROG_02_SIZE (0x00040000U) /* 1MiB / 4 */ +/* Destination address for U-Boot */ +#define CA_PROG_03_ADDRESS (0x50000000U) +#define CA_PROG_03_ADDRESSH (0x00000000U) +#define CA_PROG_03_SIZE (0x00080000U) /* 2MiB / 4 */ +/* Reserved */ +#define CA_PROG_04_ADDRESS (0x00000000U) +#define CA_PROG_04_ADDRESSH (0x00000000U) +#define CA_PROG_04_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_05_ADDRESS (0x00000000U) +#define CA_PROG_05_ADDRESSH (0x00000000U) +#define CA_PROG_05_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_06_ADDRESS (0x00000000U) +#define CA_PROG_06_ADDRESSH (0x00000000U) +#define CA_PROG_06_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_07_ADDRESS (0x00000000U) +#define CA_PROG_07_ADDRESSH (0x00000000U) +#define CA_PROG_07_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_08_ADDRESS (0x00000000U) +#define CA_PROG_08_ADDRESSH (0x00000000U) +#define CA_PROG_08_SIZE (0x00000000U) +/* ----------- customized ----------- */ + +/* sa9 */ +__attribute__ ((section (".sa9_top"))) const uint32_t top_cert[1024 / 4] = { + [0x0000 / 4] = CA_IMAGE_NUM, + [0x0008 / 4] = SECURE_FW_SRC_ADDRESS, + [0x0010 / 4] = SECURE_FW_PARTITION, + [0x0018 / 4] = RTOS_SRC_ADDRESS, + [0x0020 / 4] = RTOS_PARTITION, + [0x0028 / 4] = CX_IPL_SRC_ADDRESS, + [0x0030 / 4] = CX_IPL_PARTITION, + [0x0038 / 4] = ICUMH_PROG_SRC_ADDRESS, + [0x0040 / 4] = ICUMH_PROG_PARTITION, + [0x0048 / 4] = G4MH_PROG_SRC_ADDRESS, + [0x0050 / 4] = G4MH_PROG_PARTITION, + [0x0058 / 4] = G4MH_PROG_02_SRC_ADDRESS, + [0x0060 / 4] = G4MH_PROG_02_PARTITION, + [0x0068 / 4] = CA_PROG_01_SRC_ADDRESS, + [0x0070 / 4] = CA_PROG_01_PARTITION, + [0x0078 / 4] = CA_PROG_02_SRC_ADDRESS, + [0x0080 / 4] = CA_PROG_02_PARTITION, + [0x0088 / 4] = CA_PROG_03_SRC_ADDRESS, + [0x0090 / 4] = CA_PROG_03_PARTITION, + [0x0098 / 4] = CA_PROG_04_SRC_ADDRESS, + [0x00A0 / 4] = CA_PROG_04_PARTITION, + [0x00A8 / 4] = CA_PROG_05_SRC_ADDRESS, + [0x00B0 / 4] = CA_PROG_05_PARTITION, + [0x00B8 / 4] = CA_PROG_06_SRC_ADDRESS, + [0x00C0 / 4] = CA_PROG_06_PARTITION, + [0x00C8 / 4] = CA_PROG_07_SRC_ADDRESS, + [0x00D0 / 4] = CA_PROG_07_PARTITION, + [0x00D8 / 4] = CA_PROG_08_SRC_ADDRESS, + [0x00E0 / 4] = CA_PROG_08_PARTITION, +}; +__attribute__ ((section (".qspi_test_data"))) const uint32_t test_data[1] = { + QSPI_TESTDATA +}; +__attribute__ ((section (".sa9_firm"))) const uint32_t firm_cert[2048 / 4] = { + [0x0154 / 4] = SECURE_FW_ADDRESS, + [0x0264 / 4] = SECURE_FW_DST_SIZE, +}; +__attribute__ ((section (".sa9_rtos"))) const uint32_t rtos_cert[2048 / 4] = { + [0x0154 / 4] = RTOS_ADDRESS, + [0x0264 / 4] = RTOS_DST_SIZE, +}; +__attribute__ ((section (".sa9_cx_ipl"))) const uint32_t cx_ipl_cert[2048 / 4] = { + [0x0154 / 4] = CX_IPL_ADDRESS, + [0x0264 / 4] = CX_IPL_SIZE, +}; +__attribute__ ((section (".sa9_ca_01"))) const uint32_t ca_01_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_01_ADDRESS, + [0x0264 / 4] = CA_PROG_01_SIZE, +}; + +__attribute__ ((section (".sa9_ca_02"))) const uint32_t ca_02_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_02_ADDRESS, + [0x0264 / 4] = CA_PROG_02_SIZE, +}; +__attribute__ ((section (".sa9_ca_03"))) const uint32_t ca_03_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_03_ADDRESS, + [0x0264 / 4] = CA_PROG_03_SIZE, +}; +__attribute__ ((section (".sa9_ca_04"))) const uint32_t ca_04_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_04_ADDRESS, + [0x0264 / 4] = CA_PROG_04_SIZE, +}; +__attribute__ ((section (".sa9_ca_05"))) const uint32_t ca_05_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_05_ADDRESS, + [0x0264 / 4] = CA_PROG_05_SIZE, +}; +__attribute__ ((section (".sa9_ca_06"))) const uint32_t ca_06_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_06_ADDRESS, + [0x0264 / 4] = CA_PROG_06_SIZE, +}; +__attribute__ ((section (".sa9_ca_07"))) const uint32_t ca_07_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_07_ADDRESS, + [0x0264 / 4] = CA_PROG_07_SIZE, +}; +__attribute__ ((section (".sa9_ca_08"))) const uint32_t ca_08_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_08_ADDRESS, + [0x0264 / 4] = CA_PROG_08_SIZE, +}; +__attribute__ ((section (".sa9_icumh"))) const uint32_t icumh_cert[2048 / 4] = { + [0x0154 / 4] = ICUMH_PROG_ADDRESS, + [0x0264 / 4] = ICUMH_PROG_DST_SIZE, +}; +__attribute__ ((section (".sa9_g4mh"))) const uint32_t g4mh_cert[2048 / 4] = { + [0x0154 / 4] = G4MH_PROG_ADDRESS, + [0x0264 / 4] = G4MH_PROG_DST_SIZE, +}; +__attribute__ ((section (".sa9_g4mh_02"))) const uint32_t g4mh_02_cert[2048 / 4] = { + [0x0154 / 4] = G4MH_PROG_02_ADDRESS, + [0x0264 / 4] = G4MH_PROG_02_DST_SIZE, +}; + +/* TFMV key(8KB) + NTFMV key(8KB) + minimum version table(4KB) */ +__attribute__ ((section (".reserved"))) const uint32_t reserved[20480 / 4] = {0}; diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/s4/sa9.ld b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/s4/sa9.ld new file mode 100644 index 0000000..ce24d18 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/s4/sa9.ld @@ -0,0 +1,66 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 9(0x240000) linker directive + ******************************************************************************/ +DEFAULTS { + dummy_addr = 0xEB230000 + + dummy_size = 64K +} +MEMORY +{ + rt_sram : ORIGIN = dummy_addr, LENGTH = dummy_size +} +SECTIONS +{ +// +// Dummy Certificate +// + _start = dummy_addr; + .sa9_top ALIGN(1024) : > rt_sram /* Offset 0x00240000 */ + .qspi_test_data ALIGN(1024) : > . /* Offset 0x00240400 */ + .reserved ALIGN(4096) : > . + .sa9_firm ALIGN(1024) : > . /* Offset 0x00246000 */ + .sa9_rtos ALIGN(1024) : > . /* Offset 0x00246800 */ + .sa9_cx_ipl ALIGN(1024) : > . /* Offset 0x00247000 */ + .sa9_icumh ALIGN(1024) : > . /* Offset 0x00247800 */ + .sa9_g4mh ALIGN(1024) : > . /* Offset 0x00248000 */ + .sa9_g4mh_02 ALIGN(1024) : > . /* Offset 0x00248800 */ + .sa9_ca_01 ALIGN(1024) : > . /* Offset 0x00249000 */ + .sa9_ca_02 ALIGN(1024) : > . /* Offset 0x00249800 */ + .sa9_ca_03 ALIGN(1024) : > . /* Offset 0x0024A000 */ + .sa9_ca_04 ALIGN(1024) : > . /* Offset 0x0024A800 */ + .sa9_ca_05 ALIGN(1024) : > . /* Offset 0x0024B000 */ + .sa9_ca_06 ALIGN(1024) : > . /* Offset 0x0024B800 */ + .sa9_ca_07 ALIGN(1024) : > . /* Offset 0x0024C000 */ + .sa9_ca_08 ALIGN(1024) : > . /* Offset 0x0024C800 */ + + + .sdata : > . + .tdata : > . + .rosdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +} diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/sa0.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/sa0.c new file mode 100644 index 0000000..6bf842a --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/sa0.c @@ -0,0 +1,49 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 0(0x00000) + ******************************************************************************/ + +#include + +#define BOOT_PARAM (0x00000000U) +#define CERT_MAGIC (0xE291F358U) +#define LOADER_ADDR (0xEB210000U) +#define LOADER_SIZE (128U * 1024U / 4U) + +/* SA0 */ +/* boot parameter */ +__attribute__ ((section(".sa0_boot"))) const uint32_t boot[] = { + [0] = BOOT_PARAM, + [1] = 0xFFFFFFFFU, +}; + + +/* A-side contents Key (0x3000) */ +__attribute__ ((section(".sa0_content_a"))) const uint32_t content_a[872 / 4] = { +// [0x000 / 4] = CERT_MAGIC, /* magic */ + [0x00C / 4] = 0x00000000U, /* magic */ + [0x154 / 4] = LOADER_ADDR, /* address */ + [0x264 / 4] = LOADER_SIZE, /* size */ +}; diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/sa0.ld b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/sa0.ld new file mode 100644 index 0000000..ed4039e --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/sa0.ld @@ -0,0 +1,53 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 0(0x00000) linker directive + ******************************************************************************/ +DEFAULTS { + dummy_addr = 0xEB200000 + dummy_size = 2M + +} +MEMORY +{ + dram : ORIGIN = dummy_addr, LENGTH = dummy_size +} +SECTIONS +{ +// +// Dummy Certificate +// + .sa0 ALIGN(16) : { + _start=0; + *(.sa0_boot) _boot=0; + .=0x3000; + *(.sa0_content_a) _content_a=.; + } > dram + + .sdata : > . + .tdata : > . + .rosdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +} \ No newline at end of file diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4h/sa9.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4h/sa9.c new file mode 100644 index 0000000..bcee271 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4h/sa9.c @@ -0,0 +1,316 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 9(0x240000) + ******************************************************************************/ + +#include +#include + +#define FLASH_BOOT (0U) +#define EMMC_BOOT (1U) +#define CA_IPL (0U) +#define BL31 (1U) + +#define RTOS_LOAD_NUM_1 (1U) +#define RTOS_LOAD_NUM_3 (3U) + +/* CA program load num */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define CA_IMAGE_NUM (0x00000002U) +#else +#define CA_IMAGE_NUM (0x00000003U) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +/* Source address on flash for Secure FW */ +#define SECURE_FW_SRC_ADDRESS (0x00280000U) +/* Source address on flash for RTOS#0 */ +#define RTOS_SRC_ADDRESS (0x00000000U) +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* Source address on eMMC for RTOS#1 */ +#define RTOS1_SRC_ADDRESS (0x01000000U) +/* Source address on eMMC for RTOS#2 */ +#define RTOS2_SRC_ADDRESS (0x01200000U) +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +#if (CA_LOAD_TYPE == CA_IPL) +/* Source address on flash for CX IPL */ +#define CX_IPL_SRC_ADDRESS (0x00480000U) +#else +/* Reserved */ +#define CX_IPL_SRC_ADDRESS (0x00000000U) +#endif +/* ----------- customized ----------- */ +/* Source address on flash for BL31 */ +#define CA_PROG_01_SRC_ADDRESS (0x01400000U) +/* Source address on flash for U-Boot */ +#define CA_PROG_02_SRC_ADDRESS (0x01580000U) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +/* Reserved */ +#define CA_PROG_03_SRC_ADDRESS (0x00000000U) +#else +/* Source address on flash for OP-TEE */ +#define CA_PROG_03_SRC_ADDRESS (0x01480000U) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +/* Reserved */ +#define CA_PROG_04_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_05_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_06_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_07_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_08_SRC_ADDRESS (0x00000000U) +/* ----------- customized ----------- */ + +#if (RCAR_SA9_TYPE == FLASH_BOOT) +#define SECURE_FW_PARTITION (0x00000000U) +#define CX_IPL_PARTITION (0x00000000U) + #if (CA_LOAD_TYPE == CA_IPL) +#define RTOS_PARTITION (0x00000001U) +#define CA_PROG_01_PARTITION (0x00000001U) +#define CA_PROG_02_PARTITION (0x00000001U) + #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define CA_PROG_03_PARTITION (0x00000000U) + #else +#define CA_PROG_03_PARTITION (0x00000001U) + #endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) + #if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RTOS1_PARTITION (0x00000001U) +#define RTOS2_PARTITION (0x00000001U) + #endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + #else /* #if (CA_LOAD_TYPE == CA_IPL) */ +#define RTOS_PARTITION (0x00000000U) +#define CA_PROG_01_PARTITION (0x00000000U) +#define CA_PROG_02_PARTITION (0x00000000U) +#define CA_PROG_03_PARTITION (0x00000000U) +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) + #endif /* #if (CA_LOAD_TYPE == CA_IPL) */ +#else /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ +#define SECURE_FW_PARTITION (0x00000001U) +#define RTOS_PARTITION (0x00000001U) +#define CX_IPL_PARTITION (0x00000001U) +#define CA_PROG_01_PARTITION (0x00000001U) +#define CA_PROG_02_PARTITION (0x00000001U) + #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define CA_PROG_03_PARTITION (0x00000000U) + #else +#define CA_PROG_03_PARTITION (0x00000001U) + #endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) +#endif + +#if (RCAR_SA9_TYPE != EMMC_BOOT) +/* Test data for QSPI DDR mode */ +#define QSPI_TESTDATA (0x5A5AA5A5U) +#else +#define QSPI_TESTDATA (0x00000000U) +#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + +/* Destination address for Secure FW */ +#define SECURE_FW_ADDRESS (0xEB240000U) +#define SECURE_FW_ADDRESSH (0x00000000U) +/* Destination size for Secure FW */ +#define SECURE_FW_DST_SIZE (0x00028000U) /* 640KiB / 4 */ +/* Destination address for RTOS#0 */ +#define RTOS_ADDRESS (0xE2100000U) +#define RTOS_ADDRESSH (0x00000000U) +/* Destination size for RTOS#0 */ +#define RTOS_DST_SIZE (0x00400000U) /* 16MiB / 4 */ +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* Destination address for RTOS#1 */ +#define RTOS1_ADDRESS (0xE3100000U) +#define RTOS1_ADDRESSH (0x00000000U) +/* Destination size for RTOS#1 */ +#define RTOS1_DST_SIZE (0x00080000U) /* 2MiB / 4 */ +/* Destination address for RTOS#2 */ +#define RTOS2_ADDRESS (0xE2000000U) +#define RTOS2_ADDRESSH (0x00000000U) +/* Destination size for RTOS#2 */ +#define RTOS2_DST_SIZE (0x00004000U) /* 64KiB / 4 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +#if (CA_LOAD_TYPE == CA_IPL) +/* Destination address for CA Loader */ +#define CX_IPL_ADDRESS (0xE6300000U) +#define CX_UPL_ADDRESSH (0x00000000U) +/* Destination size for CA Loader */ +#define CX_IPL_SIZE (0x0000C000U) /* 192KiB / 4 */ +#else +/* CX IPL Reserved */ +#define CX_IPL_ADDRESS (0x00000000U) +#define CX_UPL_ADDRESSH (0x00000000U) +#define CX_IPL_SIZE (0x00000000U) +#endif +/* ----------- customized ----------- */ +/* Destination address for BL31 */ +#define CA_PROG_01_ADDRESS (0x46400000U) +#define CA_PROG_01_ADDRESSH (0x00000000U) +#define CA_PROG_01_SIZE (0x00008800U) /* 136KiB / 4 */ +/* Destination address for U-Boot */ +#define CA_PROG_02_ADDRESS (0x50000000U) +#define CA_PROG_02_ADDRESSH (0x00000000U) +#define CA_PROG_02_SIZE (0x00080000U) /* 2MiB / 4 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +/* Reserved */ +#define CA_PROG_03_ADDRESS (0x00000000U) +#define CA_PROG_03_ADDRESSH (0x00000000U) +#define CA_PROG_03_SIZE (0x00000000U) +#else +/* Destination address for OP-TEE */ +#define CA_PROG_03_ADDRESS (0x44100000U) +#define CA_PROG_03_ADDRESSH (0x00000000U) +#define CA_PROG_03_SIZE (0x00040000U) /* 1MiB / 4 */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +/* Reserved */ +#define CA_PROG_04_ADDRESS (0x00000000U) +#define CA_PROG_04_ADDRESSH (0x00000000U) +#define CA_PROG_04_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_05_ADDRESS (0x00000000U) +#define CA_PROG_05_ADDRESSH (0x00000000U) +#define CA_PROG_05_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_06_ADDRESS (0x00000000U) +#define CA_PROG_06_ADDRESSH (0x00000000U) +#define CA_PROG_06_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_07_ADDRESS (0x00000000U) +#define CA_PROG_07_ADDRESSH (0x00000000U) +#define CA_PROG_07_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_08_ADDRESS (0x00000000U) +#define CA_PROG_08_ADDRESSH (0x00000000U) +#define CA_PROG_08_SIZE (0x00000000U) +/* ----------- customized ----------- */ + +/* sa9 */ +__attribute__ ((section (".sa9_top"))) const uint32_t top_cert[1024 / 4] = { + [0x0000 / 4] = CA_IMAGE_NUM, + [0x0008 / 4] = SECURE_FW_SRC_ADDRESS, + [0x0010 / 4] = SECURE_FW_PARTITION, + [0x0018 / 4] = RTOS_SRC_ADDRESS, + [0x0020 / 4] = RTOS_PARTITION, + [0x0028 / 4] = CX_IPL_SRC_ADDRESS, + [0x0030 / 4] = CX_IPL_PARTITION, + [0x0068 / 4] = CA_PROG_01_SRC_ADDRESS, + [0x0070 / 4] = CA_PROG_01_PARTITION, + [0x0078 / 4] = CA_PROG_02_SRC_ADDRESS, + [0x0080 / 4] = CA_PROG_02_PARTITION, + [0x0088 / 4] = CA_PROG_03_SRC_ADDRESS, + [0x0090 / 4] = CA_PROG_03_PARTITION, + [0x0098 / 4] = CA_PROG_04_SRC_ADDRESS, + [0x00A0 / 4] = CA_PROG_04_PARTITION, + [0x00A8 / 4] = CA_PROG_05_SRC_ADDRESS, + [0x00B0 / 4] = CA_PROG_05_PARTITION, + [0x00B8 / 4] = CA_PROG_06_SRC_ADDRESS, + [0x00C0 / 4] = CA_PROG_06_PARTITION, + [0x00C8 / 4] = CA_PROG_07_SRC_ADDRESS, + [0x00D0 / 4] = CA_PROG_07_PARTITION, + [0x00D8 / 4] = CA_PROG_08_SRC_ADDRESS, + [0x00E0 / 4] = CA_PROG_08_PARTITION, +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + [0x0108 / 4] = RTOS1_SRC_ADDRESS, + [0x0110 / 4] = RTOS1_PARTITION, + [0x0118 / 4] = RTOS2_SRC_ADDRESS, + [0x0120 / 4] = RTOS2_PARTITION, +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +}; +__attribute__ ((section (".qspi_test_data"))) const uint32_t test_data[1] = { + QSPI_TESTDATA +}; +__attribute__ ((section (".sa9_firm"))) const uint32_t firm_cert[2048 / 4] = { + [0x0154 / 4] = SECURE_FW_ADDRESS, + [0x0264 / 4] = SECURE_FW_DST_SIZE, +}; +__attribute__ ((section (".sa9_rtos"))) const uint32_t rtos_cert[2048 / 4] = { + [0x0154 / 4] = RTOS_ADDRESS, + [0x0264 / 4] = RTOS_DST_SIZE, +}; +__attribute__ ((section (".sa9_cx_ipl"))) const uint32_t cx_ipl_cert[2048 / 4] = { + [0x0154 / 4] = CX_IPL_ADDRESS, + [0x0264 / 4] = CX_IPL_SIZE, +}; +__attribute__ ((section (".sa9_ca_01"))) const uint32_t ca_01_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_01_ADDRESS, + [0x0264 / 4] = CA_PROG_01_SIZE, +}; + +__attribute__ ((section (".sa9_ca_02"))) const uint32_t ca_02_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_02_ADDRESS, + [0x0264 / 4] = CA_PROG_02_SIZE, +}; +__attribute__ ((section (".sa9_ca_03"))) const uint32_t ca_03_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_03_ADDRESS, + [0x0264 / 4] = CA_PROG_03_SIZE, +}; +__attribute__ ((section (".sa9_ca_04"))) const uint32_t ca_04_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_04_ADDRESS, + [0x0264 / 4] = CA_PROG_04_SIZE, +}; +__attribute__ ((section (".sa9_ca_05"))) const uint32_t ca_05_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_05_ADDRESS, + [0x0264 / 4] = CA_PROG_05_SIZE, +}; +__attribute__ ((section (".sa9_ca_06"))) const uint32_t ca_06_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_06_ADDRESS, + [0x0264 / 4] = CA_PROG_06_SIZE, +}; +__attribute__ ((section (".sa9_ca_07"))) const uint32_t ca_07_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_07_ADDRESS, + [0x0264 / 4] = CA_PROG_07_SIZE, +}; +__attribute__ ((section (".sa9_ca_08"))) const uint32_t ca_08_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_08_ADDRESS, + [0x0264 / 4] = CA_PROG_08_SIZE, +}; + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +__attribute__ ((section (".sa9_rtos_01"))) const uint32_t rtos1_cert[2048 / 4] = { + [0x0154 / 4] = RTOS1_ADDRESS, + [0x0264 / 4] = RTOS1_DST_SIZE, +}; +__attribute__ ((section (".sa9_rtos_02"))) const uint32_t rtos2_cert[2048 / 4] = { + [0x0154 / 4] = RTOS2_ADDRESS, + [0x0264 / 4] = RTOS2_DST_SIZE, +}; +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* TFMV key(8KB) + NTFMV key(8KB) + minimum version table(4KB) */ +__attribute__ ((section (".reserved"))) const uint32_t reserved[20480 / 4] = {0}; +/* G4MH cert * 2 + ICUMH Cert */ +__attribute__ ((section (".reserved2"))) const uint32_t reserved2[6144 / 4] = {0}; diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4h/sa9.ld b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4h/sa9.ld new file mode 100644 index 0000000..dbf3dc7 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4h/sa9.ld @@ -0,0 +1,67 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 9(0x240000) linker directive + ******************************************************************************/ +DEFAULTS { + dummy_addr = 0xEB230000 + + dummy_size = 64K + +} +MEMORY +{ + rt_sram : ORIGIN = dummy_addr, LENGTH = dummy_size +} +SECTIONS +{ +// +// Dummy Certificate +// + _start = dummy_addr; + .sa9_top ALIGN(1024) : > rt_sram /* Offset 0x00240000 */ + .qspi_test_data ALIGN(1024) : > . /* Offset 0x00240400 */ + .reserved ALIGN(4096) : > . + .sa9_firm ALIGN(1024) : > . /* Offset 0x00246000 */ + .sa9_rtos ALIGN(1024) : > . /* Offset 0x00246800 */ + .sa9_cx_ipl ALIGN(1024) : > . /* Offset 0x00247000 */ + .reserved2 ALIGN(1024) : > . + .sa9_ca_01 ALIGN(1024) : > . /* Offset 0x00249000 */ + .sa9_ca_02 ALIGN(1024) : > . /* Offset 0x00249800 */ + .sa9_ca_03 ALIGN(1024) : > . /* Offset 0x0024A000 */ + .sa9_ca_04 ALIGN(1024) : > . /* Offset 0x0024A800 */ + .sa9_ca_05 ALIGN(1024) : > . /* Offset 0x0024B000 */ + .sa9_ca_06 ALIGN(1024) : > . /* Offset 0x0024B800 */ + .sa9_ca_07 ALIGN(1024) : > . /* Offset 0x0024C000 */ + .sa9_ca_08 ALIGN(1024) : > . /* Offset 0x0024C800 */ + /* 0x0024D000 - 0x0024DFFF is area for TFMV/NTFMV minimum version table certificate */ + .sa9_rtos_01 ALIGN(1024) PAD(4096) : > . /* Offset 0x0024E000 */ + .sa9_rtos_02 ALIGN(1024) : > . /* Offset 0x0024E800 */ + + .sdata : > . + .tdata : > . + .rosdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +} diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4m/sa9.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4m/sa9.c new file mode 100644 index 0000000..2aa9e4e --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4m/sa9.c @@ -0,0 +1,316 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 9(0x240000) + ******************************************************************************/ + +#include +#include + +#define FLASH_BOOT (0U) +#define EMMC_BOOT (1U) +#define CA_IPL (0U) +#define BL31 (1U) + +#define RTOS_LOAD_NUM_1 (1U) +#define RTOS_LOAD_NUM_3 (3U) + +/* CA program load num */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define CA_IMAGE_NUM (0x00000002U) +#else +#define CA_IMAGE_NUM (0x00000003U) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +/* Source address on flash for Secure FW */ +#define SECURE_FW_SRC_ADDRESS (0x00280000U) +/* Source address on flash for RTOS#0 */ +#define RTOS_SRC_ADDRESS (0x00000000U) +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* Source address on eMMC for RTOS#1 */ +#define RTOS1_SRC_ADDRESS (0x01000000U) +/* Source address on eMMC for RTOS#2 */ +#define RTOS2_SRC_ADDRESS (0x01200000U) +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +#if (CA_LOAD_TYPE == CA_IPL) +/* Source address on flash for CX IPL */ +#define CX_IPL_SRC_ADDRESS (0x00480000U) +#else +/* Reserved */ +#define CX_IPL_SRC_ADDRESS (0x00000000U) +#endif +/* ----------- customized ----------- */ +/* Source address on flash for BL31 */ +#define CA_PROG_01_SRC_ADDRESS (0x01400000U) +/* Source address on flash for U-Boot */ +#define CA_PROG_02_SRC_ADDRESS (0x01580000U) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +/* Reserved */ +#define CA_PROG_03_SRC_ADDRESS (0x00000000U) +#else +/* Source address on flash for OP-TEE */ +#define CA_PROG_03_SRC_ADDRESS (0x01480000U) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +/* Reserved */ +#define CA_PROG_04_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_05_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_06_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_07_SRC_ADDRESS (0x00000000U) +/* Reserved */ +#define CA_PROG_08_SRC_ADDRESS (0x00000000U) +/* ----------- customized ----------- */ + +#if (RCAR_SA9_TYPE == FLASH_BOOT) +#define SECURE_FW_PARTITION (0x00000000U) +#define CX_IPL_PARTITION (0x00000000U) + #if (CA_LOAD_TYPE == CA_IPL) +#define RTOS_PARTITION (0x00000001U) +#define CA_PROG_01_PARTITION (0x00000001U) +#define CA_PROG_02_PARTITION (0x00000001U) + #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define CA_PROG_03_PARTITION (0x00000000U) + #else +#define CA_PROG_03_PARTITION (0x00000001U) + #endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) + #if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RTOS1_PARTITION (0x00000001U) +#define RTOS2_PARTITION (0x00000001U) + #endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + #else /* #if (CA_LOAD_TYPE == CA_IPL) */ +#define RTOS_PARTITION (0x00000000U) +#define CA_PROG_01_PARTITION (0x00000000U) +#define CA_PROG_02_PARTITION (0x00000000U) +#define CA_PROG_03_PARTITION (0x00000000U) +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) + #endif /* #if (CA_LOAD_TYPE == CA_IPL) */ +#else /* #if (RCAR_SA9_TYPE == FLASH_BOOT) */ +#define SECURE_FW_PARTITION (0x00000001U) +#define RTOS_PARTITION (0x00000001U) +#define CX_IPL_PARTITION (0x00000001U) +#define CA_PROG_01_PARTITION (0x00000001U) +#define CA_PROG_02_PARTITION (0x00000001U) + #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define CA_PROG_03_PARTITION (0x00000000U) + #else +#define CA_PROG_03_PARTITION (0x00000001U) + #endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#define CA_PROG_04_PARTITION (0x00000000U) +#define CA_PROG_05_PARTITION (0x00000000U) +#define CA_PROG_06_PARTITION (0x00000000U) +#define CA_PROG_07_PARTITION (0x00000000U) +#define CA_PROG_08_PARTITION (0x00000000U) +#endif + +#if (RCAR_SA9_TYPE != EMMC_BOOT) +/* Test data for QSPI DDR mode */ +#define QSPI_TESTDATA (0x5A5AA5A5U) +#else +#define QSPI_TESTDATA (0x00000000U) +#endif /* (RCAR_SA9_TYPE == FLASH_BOOT) */ + +/* Destination address for Secure FW */ +#define SECURE_FW_ADDRESS (0xEB240000U) +#define SECURE_FW_ADDRESSH (0x00000000U) +/* Destination size for Secure FW */ +#define SECURE_FW_DST_SIZE (0x00028000U) /* 640KiB / 4 */ +/* Destination address for RTOS#0 */ +#define RTOS_ADDRESS (0xE2100000U) +#define RTOS_ADDRESSH (0x00000000U) +/* Destination size for RTOS#0 */ +#define RTOS_DST_SIZE (0x00400000U) /* 16MiB / 4 */ +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* Destination address for RTOS#1 */ +#define RTOS1_ADDRESS (0xE3100000U) +#define RTOS1_ADDRESSH (0x00000000U) +/* Destination size for RTOS#1 */ +#define RTOS1_DST_SIZE (0x00080000U) /* 2MiB / 4 */ +/* Destination address for RTOS#2 */ +#define RTOS2_ADDRESS (0xE2000000U) +#define RTOS2_ADDRESSH (0x00000000U) +/* Destination size for RTOS#2 */ +#define RTOS2_DST_SIZE (0x00004000U) /* 64KiB / 4 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +#if (CA_LOAD_TYPE == CA_IPL) +/* Destination address for CA Loader */ +#define CX_IPL_ADDRESS (0xE6300000U) +#define CX_UPL_ADDRESSH (0x00000000U) +/* Destination size for CA Loader */ +#define CX_IPL_SIZE (0x0000C000U) /* 192KiB / 4 */ +#else +/* CX IPL Reserved */ +#define CX_IPL_ADDRESS (0x00000000U) +#define CX_UPL_ADDRESSH (0x00000000U) +#define CX_IPL_SIZE (0x00000000U) +#endif +/* ----------- customized ----------- */ +/* Destination address for BL31 */ +#define CA_PROG_01_ADDRESS (0x46400000U) +#define CA_PROG_01_ADDRESSH (0x00000000U) +#define CA_PROG_01_SIZE (0x00008800U) /* 136KiB / 4 */ +/* Destination address for U-Boot */ +#define CA_PROG_02_ADDRESS (0x50000000U) +#define CA_PROG_02_ADDRESSH (0x00000000U) +#define CA_PROG_02_SIZE (0x00080000U) /* 2MiB / 4 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +/* Reserved */ +#define CA_PROG_03_ADDRESS (0x00000000U) +#define CA_PROG_03_ADDRESSH (0x00000000U) +#define CA_PROG_03_SIZE (0x00000000U) +#else +/* Destination address for OP-TEE */ +#define CA_PROG_03_ADDRESS (0x44100000U) +#define CA_PROG_03_ADDRESSH (0x00000000U) +#define CA_PROG_03_SIZE (0x00040000U) /* 1MiB / 4 */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +/* Reserved */ +#define CA_PROG_04_ADDRESS (0x00000000U) +#define CA_PROG_04_ADDRESSH (0x00000000U) +#define CA_PROG_04_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_05_ADDRESS (0x00000000U) +#define CA_PROG_05_ADDRESSH (0x00000000U) +#define CA_PROG_05_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_06_ADDRESS (0x00000000U) +#define CA_PROG_06_ADDRESSH (0x00000000U) +#define CA_PROG_06_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_07_ADDRESS (0x00000000U) +#define CA_PROG_07_ADDRESSH (0x00000000U) +#define CA_PROG_07_SIZE (0x00000000U) +/* Reserved */ +#define CA_PROG_08_ADDRESS (0x00000000U) +#define CA_PROG_08_ADDRESSH (0x00000000U) +#define CA_PROG_08_SIZE (0x00000000U) +/* ----------- customized ----------- */ + +/* sa9 */ +__attribute__ ((section (".sa9_top"))) const uint32_t top_cert[1024 / 4] = { + [0x0000 / 4] = CA_IMAGE_NUM, + [0x0008 / 4] = SECURE_FW_SRC_ADDRESS, + [0x0010 / 4] = SECURE_FW_PARTITION, + [0x0018 / 4] = RTOS_SRC_ADDRESS, + [0x0020 / 4] = RTOS_PARTITION, + [0x0028 / 4] = CX_IPL_SRC_ADDRESS, + [0x0030 / 4] = CX_IPL_PARTITION, + [0x0068 / 4] = CA_PROG_01_SRC_ADDRESS, + [0x0070 / 4] = CA_PROG_01_PARTITION, + [0x0078 / 4] = CA_PROG_02_SRC_ADDRESS, + [0x0080 / 4] = CA_PROG_02_PARTITION, + [0x0088 / 4] = CA_PROG_03_SRC_ADDRESS, + [0x0090 / 4] = CA_PROG_03_PARTITION, + [0x0098 / 4] = CA_PROG_04_SRC_ADDRESS, + [0x00A0 / 4] = CA_PROG_04_PARTITION, + [0x00A8 / 4] = CA_PROG_05_SRC_ADDRESS, + [0x00B0 / 4] = CA_PROG_05_PARTITION, + [0x00B8 / 4] = CA_PROG_06_SRC_ADDRESS, + [0x00C0 / 4] = CA_PROG_06_PARTITION, + [0x00C8 / 4] = CA_PROG_07_SRC_ADDRESS, + [0x00D0 / 4] = CA_PROG_07_PARTITION, + [0x00D8 / 4] = CA_PROG_08_SRC_ADDRESS, + [0x00E0 / 4] = CA_PROG_08_PARTITION, +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + [0x0108 / 4] = RTOS1_SRC_ADDRESS, + [0x0110 / 4] = RTOS1_PARTITION, + [0x0118 / 4] = RTOS2_SRC_ADDRESS, + [0x0120 / 4] = RTOS2_PARTITION, +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +}; +__attribute__ ((section (".qspi_test_data"))) const uint32_t test_data[1] = { + QSPI_TESTDATA +}; +__attribute__ ((section (".sa9_firm"))) const uint32_t firm_cert[2048 / 4] = { + [0x0154 / 4] = SECURE_FW_ADDRESS, + [0x0264 / 4] = SECURE_FW_DST_SIZE, +}; +__attribute__ ((section (".sa9_rtos"))) const uint32_t rtos_cert[2048 / 4] = { + [0x0154 / 4] = RTOS_ADDRESS, + [0x0264 / 4] = RTOS_DST_SIZE, +}; +__attribute__ ((section (".sa9_cx_ipl"))) const uint32_t cx_ipl_cert[2048 / 4] = { + [0x0154 / 4] = CX_IPL_ADDRESS, + [0x0264 / 4] = CX_IPL_SIZE, +}; +__attribute__ ((section (".sa9_ca_01"))) const uint32_t ca_01_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_01_ADDRESS, + [0x0264 / 4] = CA_PROG_01_SIZE, +}; + +__attribute__ ((section (".sa9_ca_02"))) const uint32_t ca_02_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_02_ADDRESS, + [0x0264 / 4] = CA_PROG_02_SIZE, +}; +__attribute__ ((section (".sa9_ca_03"))) const uint32_t ca_03_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_03_ADDRESS, + [0x0264 / 4] = CA_PROG_03_SIZE, +}; +__attribute__ ((section (".sa9_ca_04"))) const uint32_t ca_04_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_04_ADDRESS, + [0x0264 / 4] = CA_PROG_04_SIZE, +}; +__attribute__ ((section (".sa9_ca_05"))) const uint32_t ca_05_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_05_ADDRESS, + [0x0264 / 4] = CA_PROG_05_SIZE, +}; +__attribute__ ((section (".sa9_ca_06"))) const uint32_t ca_06_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_06_ADDRESS, + [0x0264 / 4] = CA_PROG_06_SIZE, +}; +__attribute__ ((section (".sa9_ca_07"))) const uint32_t ca_07_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_07_ADDRESS, + [0x0264 / 4] = CA_PROG_07_SIZE, +}; +__attribute__ ((section (".sa9_ca_08"))) const uint32_t ca_08_cert[2048 / 4] = { + [0x0154 / 4] = CA_PROG_08_ADDRESS, + [0x0264 / 4] = CA_PROG_08_SIZE, +}; + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +__attribute__ ((section (".sa9_rtos_01"))) const uint32_t rtos1_cert[2048 / 4] = { + [0x0154 / 4] = RTOS1_ADDRESS, + [0x0264 / 4] = RTOS1_DST_SIZE, +}; +__attribute__ ((section (".sa9_rtos_02"))) const uint32_t rtos2_cert[2048 / 4] = { + [0x0154 / 4] = RTOS2_ADDRESS, + [0x0264 / 4] = RTOS2_DST_SIZE, +}; +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* TFMV key(8KB) + NTFMV key(8KB) + minimum version table(4KB) */ +__attribute__ ((section (".reserved"))) const uint32_t reserved[20480 / 4] = {0}; +/* G4MH cert * 2 + ICUMH Cert */ +__attribute__ ((section (".reserved2"))) const uint32_t reserved2[6144 / 4] = {0}; diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4m/sa9.ld b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4m/sa9.ld new file mode 100644 index 0000000..11c8421 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/dummy_create/v4m/sa9.ld @@ -0,0 +1,68 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : dummy flash data for sector 9(0x240000) linker directive + ******************************************************************************/ +DEFAULTS { + dummy_addr = 0xEB230000 + + dummy_size = 64K + +} +MEMORY +{ + rt_sram : ORIGIN = dummy_addr, LENGTH = dummy_size +} +SECTIONS +{ +// +// Dummy Certificate +// + _start = dummy_addr; + .sa9_top ALIGN(1024) : > rt_sram /* Offset 0x00240000 */ + .qspi_test_data ALIGN(1024) : > . /* Offset 0x00240400 */ + .reserved ALIGN(4096) : > . + .sa9_firm ALIGN(1024) : > . /* Offset 0x00246000 */ + .sa9_rtos ALIGN(1024) : > . /* Offset 0x00246800 */ + .sa9_cx_ipl ALIGN(1024) : > . /* Offset 0x00247000 */ + .reserved2 ALIGN(1024) : > . + .sa9_ca_01 ALIGN(1024) : > . /* Offset 0x00249000 */ + .sa9_ca_02 ALIGN(1024) : > . /* Offset 0x00249800 */ + .sa9_ca_03 ALIGN(1024) : > . /* Offset 0x0024A000 */ + .sa9_ca_04 ALIGN(1024) : > . /* Offset 0x0024A800 */ + .sa9_ca_05 ALIGN(1024) : > . /* Offset 0x0024B000 */ + .sa9_ca_06 ALIGN(1024) : > . /* Offset 0x0024B800 */ + .sa9_ca_07 ALIGN(1024) : > . /* Offset 0x0024C000 */ + .sa9_ca_08 ALIGN(1024) : > . /* Offset 0x0024C800 */ + /* 0x0024D000 - 0x0024DFFF is area for TFMV/NTFMV minimum version table certificate */ + .sa9_rtos_01 ALIGN(1024) PAD(4096) : > . /* Offset 0x0024E000 */ + .sa9_rtos_02 ALIGN(1024) : > . /* Offset 0x0024E800 */ + + + .sdata : > . + .tdata : > . + .rosdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +} diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/ntfmv_ver_tbl.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/ntfmv_ver_tbl.c new file mode 100644 index 0000000..4f50da6 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/ntfmv_ver_tbl.c @@ -0,0 +1,111 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2023 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : NTFMV Software minimum version table + ******************************************************************************/ +/****************************************************************************** + * @file ntfmv_ver_tbl.c + * - Version : 0.02 + * @brief NTFMV Software minimum version table. + * This is sample source code. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.08.2022 0.01 First Release + * : 21.08.2023 0.02 Add support for V4M. + *****************************************************************************/ + +#include + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +/* Minimum software version of U-Boot(V4H) */ +#define CA_PROG_02_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_02_SW_VERSION (0x00000000U) +#define CA_PROG_02_VER_OFFSET (0x00000000U) +#else /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ +/* Reserved */ +#define CA_PROG_02_CHECK_FLAG (0x00000000U) +#define CA_PROG_02_SW_VERSION (0x00000000U) +#define CA_PROG_02_VER_OFFSET (0x00000000U) +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +/* Minimum software version of U-Boot(S4) */ +#define CA_PROG_03_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_03_SW_VERSION (0x00000000U) +#define CA_PROG_03_VER_OFFSET (0x00000000U) + +/* Reserved */ +#define CA_PROG_04_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_04_SW_VERSION (0x00000000U) +#define CA_PROG_04_VER_OFFSET (0x00000000U) + +/* Reserved */ +#define CA_PROG_05_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_05_SW_VERSION (0x00000000U) +#define CA_PROG_05_VER_OFFSET (0x00000000U) + +/* Reserved */ +#define CA_PROG_06_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_06_SW_VERSION (0x00000000U) +#define CA_PROG_06_VER_OFFSET (0x00000000U) + +/* Reserved */ +#define CA_PROG_07_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_07_SW_VERSION (0x00000000U) +#define CA_PROG_07_VER_OFFSET (0x00000000U) + +/* Reserved */ +#define CA_PROG_08_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_08_SW_VERSION (0x00000000U) +#define CA_PROG_08_VER_OFFSET (0x00000000U) + +/* For 16-byte boundary */ +#define RESERVED_FOR_PADDING (0x00000000U) + +__attribute__ ((section (".ntfmv_tbl_top"))) const uint32_t ntfmv_ver_tbl[] = { + [0x0000 / 4] = CA_PROG_02_CHECK_FLAG, + [0x0004 / 4] = CA_PROG_02_SW_VERSION, + [0x0008 / 4] = CA_PROG_02_VER_OFFSET, + [0x0010 / 4] = CA_PROG_03_CHECK_FLAG, + [0x0014 / 4] = CA_PROG_03_SW_VERSION, + [0x0018 / 4] = CA_PROG_03_VER_OFFSET, + [0x0020 / 4] = CA_PROG_04_CHECK_FLAG, + [0x0024 / 4] = CA_PROG_04_SW_VERSION, + [0x0028 / 4] = CA_PROG_04_VER_OFFSET, + [0x0030 / 4] = CA_PROG_05_CHECK_FLAG, + [0x0034 / 4] = CA_PROG_05_SW_VERSION, + [0x0038 / 4] = CA_PROG_05_VER_OFFSET, + [0x0040 / 4] = CA_PROG_06_CHECK_FLAG, + [0x0044 / 4] = CA_PROG_06_SW_VERSION, + [0x0048 / 4] = CA_PROG_06_VER_OFFSET, + [0x0050 / 4] = CA_PROG_07_CHECK_FLAG, + [0x0054 / 4] = CA_PROG_07_SW_VERSION, + [0x0058 / 4] = CA_PROG_07_VER_OFFSET, + [0x0060 / 4] = CA_PROG_08_CHECK_FLAG, + [0x0064 / 4] = CA_PROG_08_SW_VERSION, + [0x0068 / 4] = CA_PROG_08_VER_OFFSET, + [0x006C / 4] = RESERVED_FOR_PADDING, /* Adjust to 16-byte boundary */ +}; + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/ntfmv_ver_tbl.ld b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/ntfmv_ver_tbl.ld new file mode 100644 index 0000000..b6b3d77 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/ntfmv_ver_tbl.ld @@ -0,0 +1,60 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : linker directive for NTFMV Software minimum version table + ******************************************************************************/ +/****************************************************************************** + * @file ntfmv_ver_tbl.ld + * - Version : 0.01 + * @brief linker directive for NTFMV Software minimum version table. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.08.2022 0.01 First Release + *****************************************************************************/ + +DEFAULTS { + tbl_base_addr = 0xEB235800 + + tbl_size = 2K +} +MEMORY +{ + rt_sram : ORIGIN = tbl_base_addr, LENGTH = tbl_size +} +SECTIONS +{ +// +// NTFMV Software minimum version table +// + _start = tbl_base_addr; + .ntfmv_tbl_top ALIGN(1024) : > rt_sram + + .sdata : > . + .tdata : > . + .rosdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +} diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/tfmv_ver_tbl.c b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/tfmv_ver_tbl.c new file mode 100644 index 0000000..699a004 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/tfmv_ver_tbl.c @@ -0,0 +1,141 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : TFMV Software minimum version table + ******************************************************************************/ +/****************************************************************************** + * @file tfmv_ver_tbl.c + * - Version : 0.01 + * @brief TFMV Software minimum version table. + * This is sample source code. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.08.2022 0.01 First Release + *****************************************************************************/ + +#include + +#define CA_IPL (0U) + +/* Minimum software version of Secure FW */ +#define SECURE_FW_CHECK_FLAG (0x00000001U) /* 0:disable other:enable */ +#define SECURE_FW_SW_VERSION (0x00000001U) +#define SECURE_FW_VER_OFFSET (0x00000400U) + +/* Minimum software version of RTOS */ +#define RTOS_SW_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define RTOS_SW_SW_VERSION (0x00000000U) +#define RTOS_SW_VER_OFFSET (0x00000000U) + +#if (CA_LOAD_TYPE == CA_IPL) +/* Minimum software version of CX 2nd IPL */ +#define CX_2ND_IPL_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CX_2ND_IPL_SW_VERSION (0x00000000U) +#define CX_2ND_IPL_VER_OFFSET (0x00000000U) +#else /* (CA_LOAD_TYPE == CA_IPL) */ +/* Reserved */ +#define CX_2ND_IPL_CHECK_FLAG (0x00000000U) +#define CX_2ND_IPL_SW_VERSION (0x00000000U) +#define CX_2ND_IPL_VER_OFFSET (0x00000000U) +#endif /* (CA_LOAD_TYPE == CA_IPL) */ + +#if (RCAR_LSI == RCAR_S4) +/* Minimum software version of ICUMH program */ +#define ICUMH_PROG_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define ICUMH_PROG_SW_VERSION (0x00000000U) +#define ICUMH_PROG_VER_OFFSET (0x00000000U) + +/* Minimum software version of G4MH program(1st) */ +#define G4MH_PROG_01_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define G4MH_PROG_01_SW_VERSION (0x00000000U) +#define G4MH_PROG_01_VER_OFFSET (0x00000000U) + +/* Minimum software version of G4MH program(2nd) */ +#define G4MH_PROG_02_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define G4MH_PROG_02_SW_VERSION (0x00000000U) +#define G4MH_PROG_02_VER_OFFSET (0x00000000U) + +#else /* (RCAR_LSI == RCAR_S4) */ +/* Reserved */ +#define ICUMH_PROG_CHECK_FLAG (0x00000000U) +#define ICUMH_PROG_SW_VERSION (0x00000000U) +#define ICUMH_PROG_VER_OFFSET (0x00000000U) +#define G4MH_PROG_01_CHECK_FLAG (0x00000000U) +#define G4MH_PROG_01_SW_VERSION (0x00000000U) +#define G4MH_PROG_01_VER_OFFSET (0x00000000U) +#define G4MH_PROG_02_CHECK_FLAG (0x00000000U) +#define G4MH_PROG_02_SW_VERSION (0x00000000U) +#define G4MH_PROG_02_VER_OFFSET (0x00000000U) +#endif /* (RCAR_LSI == RCAR_S4) */ + +/* Minimum software version of BL31 */ +#define CA_PROG_01_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_01_SW_VERSION (0x00000000U) +#define CA_PROG_01_VER_OFFSET (0x00000000U) + +#if (RCAR_LSI == RCAR_S4) +/* Minimum software version of OP-TEE */ +#define CA_PROG_02_CHECK_FLAG (0x00000000U) /* 0:disable other:enable */ +#define CA_PROG_02_SW_VERSION (0x00000000U) +#define CA_PROG_02_VER_OFFSET (0x00000000U) +#else /* (RCAR_LSI == RCAR_S4) */ +/* Reserved */ +#define CA_PROG_02_CHECK_FLAG (0x00000000U) +#define CA_PROG_02_SW_VERSION (0x00000000U) +#define CA_PROG_02_VER_OFFSET (0x00000000U) +#endif /* (RCAR_LSI == RCAR_S4) */ + +/* For 16-byte boundary */ +#define RESERVED_FOR_PADDING (0x00000000U) + +__attribute__ ((section (".tfmv_tbl_top"))) const uint32_t tfmv_ver_tbl[] = { + [0x0000 / 4] = SECURE_FW_CHECK_FLAG, + [0x0004 / 4] = SECURE_FW_SW_VERSION, + [0x0008 / 4] = SECURE_FW_VER_OFFSET, + [0x0010 / 4] = RTOS_SW_CHECK_FLAG, + [0x0014 / 4] = RTOS_SW_SW_VERSION, + [0x0018 / 4] = RTOS_SW_VER_OFFSET, + [0x0020 / 4] = CX_2ND_IPL_CHECK_FLAG, + [0x0024 / 4] = CX_2ND_IPL_SW_VERSION, + [0x0028 / 4] = CX_2ND_IPL_VER_OFFSET, + [0x0030 / 4] = ICUMH_PROG_CHECK_FLAG, + [0x0034 / 4] = ICUMH_PROG_SW_VERSION, + [0x0038 / 4] = ICUMH_PROG_VER_OFFSET, + [0x0040 / 4] = G4MH_PROG_01_CHECK_FLAG, + [0x0044 / 4] = G4MH_PROG_01_SW_VERSION, + [0x0048 / 4] = G4MH_PROG_01_VER_OFFSET, + [0x0050 / 4] = G4MH_PROG_02_CHECK_FLAG, + [0x0054 / 4] = G4MH_PROG_02_SW_VERSION, + [0x0058 / 4] = G4MH_PROG_02_VER_OFFSET, + [0x0060 / 4] = CA_PROG_01_CHECK_FLAG, + [0x0064 / 4] = CA_PROG_01_SW_VERSION, + [0x0068 / 4] = CA_PROG_01_VER_OFFSET, + [0x0070 / 4] = CA_PROG_02_CHECK_FLAG, + [0x0074 / 4] = CA_PROG_02_SW_VERSION, + [0x0078 / 4] = CA_PROG_02_VER_OFFSET, + [0x007C / 4] = RESERVED_FOR_PADDING, /* Adjust to 16-byte boundary */ +}; + diff --git a/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/tfmv_ver_tbl.ld b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/tfmv_ver_tbl.ld new file mode 100644 index 0000000..b371a60 --- /dev/null +++ b/IPL/SDK/v4h/src/Gen4_ICUMX_Loader/tools/sw_min_ver_tbl/tfmv_ver_tbl.ld @@ -0,0 +1,60 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : linker directive for TFMV Software minimum version table + ******************************************************************************/ +/****************************************************************************** + * @file tfmv_ver_tbl.ld + * - Version : 0.01 + * @brief linker directive for TFMV Software minimum version table. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.08.2022 0.01 First Release + *****************************************************************************/ + +DEFAULTS { + tbl_base_addr = 0xEB235000 + + tbl_size = 2K +} +MEMORY +{ + rt_sram : ORIGIN = tbl_base_addr, LENGTH = tbl_size +} +SECTIONS +{ +// +// TFMV Software minimum version table +// + _start = tbl_base_addr; + .tfmv_tbl_top ALIGN(1024) : > rt_sram + + .sdata : > . + .tdata : > . + .rosdata ALIGN(4) : > . + .sdabase ALIGN(4) : > . + .secinfo ALIGN(4) : > . +} diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/Makefile b/IPL/SDK/v4h/src/V4H_Cx_Loader/Makefile new file mode 100644 index 0000000..358e25d --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/Makefile @@ -0,0 +1,528 @@ +#******************************************************************************* +# DISCLAIMER +# This software is supplied by Renesas Electronics Corporation and is only +# intended for use with Renesas products. No other uses are authorized. This +# software is owned by Renesas Electronics Corporation and is protected under +# all applicable laws, including copyright laws. +# THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +# THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +# LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +# AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +# TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +# ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +# FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +# ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +# BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +# Renesas reserves the right, without notice, to make changes to this software +# and to discontinue the availability of this software. By using this software, +# you agree to the additional terms and conditions found by accessing the +# following link: +# http://www.renesas.com/disclaimer +# Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +#******************************************************************************/ + + + +# ****************************************************************************** +# * DESCRIPTION : makefile for Loader +# ****************************************************************************** +# ****************************************************************************** +# * @file Makefile +# * - Version : 0.14 +# * @brief +# * . +# ****************************************************************************** +# ****************************************************************************** +# * History : DD.MM.YYYY Version Description +# * : 02.02.2022 0.01 First Release +# * : 17.02.2022 0.02 Support AArch32 +# * : 23.03.2022 0.03 Removed unnecessary functions +# * : 09.05.2022 0.04 Used the standard library +# * Renamed the image +# * Added make option "LSI" +# * Removed make option "AArch" +# * Changed to make common things common in LSI +# * : 17.06.2022 0.05 Support secure boot for S4 +# * : 02.08.2022 0.06 Support WDT +# * : 07.11.2022 0.07 Support DDR initialization/QOS initialization processing +# * : 14.12.2022 0.08 Fixed make option "EMMC_TRANS_MODE" +# * Support MMU +# * : 15.12.2022 0.09 Support RegionID check +# * Fixed "LSI" default settings +# * : 04.04.2023 0.10 Fixed not used standerd library. +# * : 21.08.2023 0.11 Add support for V4M. +# * : 04.09.2023 0.12 Add C4 power domain setting. +# * : 19.12.2024 0.13 Add build option "RTOS_LOAD_NUM" +# * Add build option "ECM_ERROR_ENABLE" +# * and "ECMERRTGTR_INTC". +# * : 26.05.2025 0.14 Add build option "OPTEE_LOAD_ENABLE" +# ****************************************************************************** + +################################################### +# makefile +################################################### + +define add_define +DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),) +endef + +INCLUDE_DIR = -Iinclude + +OUTDIR := build + +# LSI setting common define +RCAR_S4:=0 +RCAR_V4H:=1 +RCAR_V4M:=2 +NORMAL:=0 +SECURE:=1 +HS400:=0 +HS200:=1 +HIGH_SPEED:=2 +NO_HIGH_SPEED:=3 +$(eval $(call add_define,RCAR_S4)) +$(eval $(call add_define,RCAR_V4H)) +$(eval $(call add_define,RCAR_V4M)) +$(eval $(call add_define,NORMAL)) +$(eval $(call add_define,SECURE)) +$(eval $(call add_define,HS400)) +$(eval $(call add_define,HS200)) +$(eval $(call add_define,HIGH_SPEED)) +$(eval $(call add_define,NO_HIGH_SPEED)) + +#/* Select LSI("S4" or "V4H" or "V4M")*********************** +ifeq ("$(LSI)", "") +LSI = S4 +endif + +ifeq (${LSI},S4) + RCAR_LSI:=${RCAR_S4} + #output file name + FILE_NAME = ca55_loader +else ifeq (${LSI},V4H) + RCAR_LSI:=${RCAR_V4H} + #output file name + FILE_NAME = cr52_loader +else ifeq (${LSI},V4M) + RCAR_LSI:=${RCAR_V4M} + #output file name + FILE_NAME = cr52_loader +else + $(error "Error: ${LSI} is not supported.") +endif +$(eval $(call add_define,RCAR_LSI)) + +ifndef BOOT_MODE + BOOT_MODE:=${NORMAL} +else + ifeq (${BOOT_MODE},NORMAL) + BOOT_MODE:=${NORMAL} + else ifeq (${BOOT_MODE},SECURE) + BOOT_MODE:=${SECURE} + ifeq (${LSI},S4) + $(eval $(call add_define,TARGET_CORTEX_A)) + $(eval $(call add_define,TARGET_DEVICE_S4X)) + $(eval $(call add_define,AARCH64)) + else ifeq (${LSI},V4H) + $(eval $(call add_define,TARGET_DEVICE_V4H)) + else ifeq (${LSI},V4M) + $(eval $(call add_define,TARGET_DEVICE_V4M)) + endif + else + $(error "Error: ${BOOT_MODE} is not supported.") + endif + $(eval $(call add_define,BOOT_MODE)) +endif + +ifndef EMMC_TRANS_MODE + EMMC_TRANS_MODE:=${HS400} +else + ifeq (${EMMC_TRANS_MODE},HS400) + EMMC_TRANS_MODE:=${HS400} + else ifeq (${EMMC_TRANS_MODE},HS200) + EMMC_TRANS_MODE:=${HS200} + else ifeq (${EMMC_TRANS_MODE},HIGH_SPEED) + EMMC_TRANS_MODE:=${HIGH_SPEED} + else ifeq (${EMMC_TRANS_MODE},NO_HIGH_SPEED) + EMMC_TRANS_MODE:=${NO_HIGH_SPEED} + else + $(error "Error: ${EMMC_TRANS_MODE} is not supported.") + endif + $(eval $(call add_define,EMMC_TRANS_MODE)) +endif + +# Process RCAR_DRAM_SPLIT flag (V4H only) +ifeq (${LSI},V4H) + ifndef RCAR_DRAM_SPLIT + RCAR_DRAM_SPLIT := 1 + $(eval $(call add_define,RCAR_DRAM_SPLIT)) + else + ifeq (${RCAR_DRAM_SPLIT},0) + $(eval $(call add_define,RCAR_DRAM_SPLIT)) + else ifeq (${RCAR_DRAM_SPLIT},1) + $(eval $(call add_define,RCAR_DRAM_SPLIT)) + else + $(error "Error:RCAR_DRAM_SPLIT=${RCAR_DRAM_SPLIT} is not supported.") + endif + endif +else ifeq (${LSI},V4M) + ifndef RCAR_DRAM_SPLIT + RCAR_DRAM_SPLIT := 0 + $(eval $(call add_define,RCAR_DRAM_SPLIT)) + else + ifneq (${RCAR_DRAM_SPLIT},0) + $(error "Error:RCAR_DRAM_SPLIT=${RCAR_DRAM_SPLIT} is not supported.") + endif + endif +endif + +# Process RCAR_PERIODIC_WRITE_TRAINING flag +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef RCAR_PERIODIC_WRITE_TRAINING + RCAR_PERIODIC_WRITE_TRAINING := 1 + $(eval $(call add_define,RCAR_PERIODIC_WRITE_TRAINING)) + else + ifeq (${RCAR_PERIODIC_WRITE_TRAINING},0) + $(eval $(call add_define,RCAR_PERIODIC_WRITE_TRAINING)) + else ifeq (${RCAR_PERIODIC_WRITE_TRAINING},1) + $(eval $(call add_define,RCAR_PERIODIC_WRITE_TRAINING)) + else + $(error "Error:RCAR_PERIODIC_WRITE_TRAINING=${RCAR_PERIODIC_WRITE_TRAINING} is not supported.") + endif + endif +endif + +# Process RCAR_PERIODIC_READ_TRAINING flag +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef RCAR_PERIODIC_READ_TRAINING + RCAR_PERIODIC_READ_TRAINING := 1 + $(eval $(call add_define,RCAR_PERIODIC_READ_TRAINING)) + else + ifeq (${RCAR_PERIODIC_READ_TRAINING},0) + $(eval $(call add_define,RCAR_PERIODIC_READ_TRAINING)) + else ifeq (${RCAR_PERIODIC_READ_TRAINING},1) + $(eval $(call add_define,RCAR_PERIODIC_READ_TRAINING)) + else + $(error "Error:RCAR_PERIODIC_READ_TRAINING=${RCAR_PERIODIC_READ_TRAINING} is not supported.") + endif + endif +endif + +# Process DBSC_REFINTS flag +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef DBSC_REFINTS + DBSC_REFINTS := 0 + $(eval $(call add_define,DBSC_REFINTS)) + else + ifeq (${DBSC_REFINTS},0) + $(eval $(call add_define,DBSC_REFINTS)) + else ifeq (${DBSC_REFINTS},1) + $(eval $(call add_define,DBSC_REFINTS)) + else + $(error "Error:DBSC_REFINTS=${DBSC_REFINTS} is not supported.") + endif + endif +endif + +# Process RTVRAM_EXTEND flag +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef RTVRAM_EXTEND + RTVRAM_EXTEND := 1 + $(eval $(call add_define,RTVRAM_EXTEND)) + else + ifeq (${RTVRAM_EXTEND},0) + $(eval $(call add_define,RTVRAM_EXTEND)) + else ifeq (${RTVRAM_EXTEND},1) + $(eval $(call add_define,RTVRAM_EXTEND)) + else + $(error "Error:RTVRAM_EXTEND=${RTVRAM_EXTEND} is not supported.") + endif + endif +endif + +# Process RTOS_LOAD_NUM flag +# 1:RTOS#0 only 3:RTOS#0,#1,#2 +ifndef RTOS_LOAD_NUM + RTOS_LOAD_NUM := 1 + $(eval $(call add_define,RTOS_LOAD_NUM)) +else + ifeq (${RTOS_LOAD_NUM},1) + $(eval $(call add_define,RTOS_LOAD_NUM)) + else ifeq (${RTOS_LOAD_NUM},3) + $(eval $(call add_define,RTOS_LOAD_NUM)) + else + $(error "Error:RTOS_LOAD_NUM=${RTOS_LOAD_NUM} is not supported.") + endif +endif + +# Process OPTEE_LOAD_ENABLE flag +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef OPTEE_LOAD_ENABLE + OPTEE_LOAD_ENABLE := 1 + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else + ifeq (${OPTEE_LOAD_ENABLE},0) + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else ifeq (${OPTEE_LOAD_ENABLE},1) + $(eval $(call add_define,OPTEE_LOAD_ENABLE)) + else + $(error "Error:OPTEE_LOAD_ENABLE=${OPTEE_LOAD_ENABLE} is not supported.") + endif + endif +endif + +OUTPUT_FILE = $(FILE_NAME).elf + +#object file name +OBJ_FILE = common/string.o \ + common/log/log.o \ + common/log/scif.o \ + common/timer/generic_timer.o \ + image_load/image_load.o \ + ip/ip_control.o \ + ip/emmc/emmc_boot.o \ + ip/emmc/emmc_cmd.o \ + ip/emmc/emmc_init.o \ + ip/emmc/emmc_interrupt.o \ + ip/emmc/emmc_mount.o \ + ip/emmc/emmc_multiboot.o \ + ip/emmc/emmc_read.o \ + ip/emmc/emmc_utility.o \ + loader/stack.o \ + loader/loader_main.o \ + ip/interrupt.o + +ifeq (${BOOT_MODE},SECURE) +OBJ_FILE += secure/secure_boot.o \ + secure/src/comm_drv/icum_d_comm_pe.o \ + secure/src/icumif_lib/r_icumif.o \ + secure/shared/src/mem_info_def.o \ + secure/user_api/user_icumif_api.o + +INCLUDE_DIR += -Isecure/src/comm_drv -Isecure/src/icumif_lib -Isecure/icumif -Isecure/include -Isecure/user_api -Isecure/shared/src + +endif + +ifeq (${LSI},S4) + OBJ_FILE += \ + loader/loader_s4.o \ + ip/swdt/swdt.o \ + loader/loader_mmu_table.o \ + loader/loader_exceptions.o + #linker script name + MEMORY_DEF = loader/loader_s4.ld +else ifeq (${LSI},V4H) + OBJ_FILE += \ + cpu_on/cpu_on.o \ + ip/qos/qos.o \ + cnf_tbl/cnf_tbl_v4h.o \ + ip/rtvram/rtvram.o \ + loader/loader_v4h.o \ + loader/loader_main_common.o \ + protect/region_id/region_id.o \ + cnf_tbl/rgidcnf_tbl_v4h.o \ + ip/ddr/v4h/lpddr5/ecc_enable_v4h.o \ + ip/ddr/v4h/lpddr5/ecm_enable_v4h.o + #linker script name + MEMORY_DEF = loader/loader_v4h.ld + + INCLUDE_DIR += -Iip/ddr +else ifeq (${LSI},V4M) + OBJ_FILE += \ + cpu_on/cpu_on.o \ + ip/qos/qos.o \ + cnf_tbl/cnf_tbl_v4m.o \ + ip/rtvram/rtvram.o \ + loader/loader_v4m.o \ + loader/loader_main_common.o \ + protect/region_id/region_id.o \ + cnf_tbl/rgidcnf_tbl_v4m.o \ + ip/ddr/v4m/lpddr5/ecc_enable_v4m.o \ + ip/ddr/v4m/lpddr5/ecm_enable_v4m.o + #linker script name + MEMORY_DEF = loader/loader_v4m.ld + + INCLUDE_DIR += -Iip/ddr + +endif + +################################################### +# Process access protection flag +# 0:Disable 1:Enable +ifndef ACC_PROT_ENABLE +ACC_PROT_ENABLE := 0 +$(eval $(call add_define,ACC_PROT_ENABLE)) +else + ifeq (${ACC_PROT_ENABLE},0) + $(eval $(call add_define,ACC_PROT_ENABLE)) + else ifeq (${ACC_PROT_ENABLE},1) + $(eval $(call add_define,ACC_PROT_ENABLE)) + else + $(error "Error:ACC_PROT_ENABLE=${ACC_PROT_ENABLE} is not supported.") + endif +endif + +# Debug build +DEBUG:=0 + +# Process DEBUG flag +$(eval $(call assert_boolean,DEBUG)) +$(eval $(call add_define,DEBUG)) +ifeq (${DEBUG},0) + $(eval $(call add_define,NDEBUG)) +else + CFLAGS += -g + ASFLAGS += -g -Wa,--gdwarf-2 +endif + +# Process LOG_LEVEL +ifndef LOG_LEVEL +LOG_LEVEL := 2 +endif +$(eval $(call add_define,LOG_LEVEL)) + +# Process ECC_ENABLE +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + ifndef ECC_ENABLE + ECC_ENABLE:= 0 + $(eval $(call add_define,ECC_ENABLE)) + else + ifeq (${ECC_ENABLE},0) + $(eval $(call add_define,ECC_ENABLE)) + else ifeq (${ECC_ENABLE},1) + $(eval $(call add_define,ECC_ENABLE)) + else + $(error "Error: ECC_ENABLE=${ECC_ENABLE} is not supported.") + endif + endif +endif + +# Process ECM_ERROR_ENABLE flag +ifndef ECM_ERROR_ENABLE + ECM_ERROR_ENABLE := 1 + $(eval $(call add_define,ECM_ERROR_ENABLE)) +else + ifeq (${ECM_ERROR_ENABLE},0) + $(eval $(call add_define,ECM_ERROR_ENABLE)) + else ifeq (${ECM_ERROR_ENABLE},1) + $(eval $(call add_define,ECM_ERROR_ENABLE)) + else + $(error "Error:ECM_ERROR_ENABLE=${ECM_ERROR_ENABLE} is not supported.") + endif +endif + +# Process ECMERRTGTR_INTC flag +ifndef ECMERRTGTR_INTC + ECMERRTGTR_INTC := 1 + $(eval $(call add_define,ECMERRTGTR_INTC)) +else + ifeq (${ECMERRTGTR_INTC},0) + $(eval $(call add_define,ECMERRTGTR_INTC)) + else ifeq (${ECMERRTGTR_INTC},1) + $(eval $(call add_define,ECMERRTGTR_INTC)) + else + $(error "Error:ECMERRTGTR_INTC=${ECMERRTGTR_INTC} is not supported.") + endif +endif + +ifeq ($(filter ${LSI},V4H V4M),${LSI}) + include ip/ddr/ddr.mk +endif + +# Process DBSC HUNGUP WA +ifndef WA_OTLINT5579 + WA_OTLINT5579:= 1 +endif +$(eval $(call add_define,WA_OTLINT5579)) + +# Private Option for QoS and DBSC +RCAR_PERIODIC_TRAINING_SEPARATE_MODE:= 0 +$(eval $(call add_define,RCAR_PERIODIC_TRAINING_SEPARATE_MODE)) + +################################################### + +OUTDIR_REL := $(OUTDIR)/release +OUTDIR_OBJ := $(OUTDIR)/obj + +OBJ_FILE := $(OBJ_FILE:%.o=$(OUTDIR_OBJ)/%.o) + +CC = $(CROSS_COMPILE)gcc +CPP = ${CROSS_COMPILE}cpp +AS = ${CROSS_COMPILE}gcc +AR = ${CROSS_COMPILE}ar +LD = $(CROSS_COMPILE)ld +OC = ${CROSS_COMPILE}objcopy +OD = ${CROSS_COMPILE}objdump + +ifeq (${LSI},S4) +ASFLAGS += -march=armv8.2-a +CFLAGS += -march=armv8.2-a \ + -O0 +else ifeq ($(filter ${LSI},V4H V4M),${LSI}) +ASFLAGS += -march=armv8-r +CFLAGS += -march=armv8-r \ + -O2 +endif + +ASFLAGS += -ffreestanding -Wa,--fatal-warnings \ + -Wmissing-include-dirs \ + -c -D__ASSEMBLY \ + $(INCLUDE_DIR) $(DEFINES) + +CFLAGS += -ffreestanding -Wall \ + -Wmissing-include-dirs \ + -std=c99 -c \ + $(INCLUDE_DIR) $(DEFINES) + +LDFLAGS = --fatal-warnings -O1 -nostdlib + +BUILD_MESSAGE_TIMESTAMP ?= __TIME__", "__DATE__ + +LIBS = -L$(subst libc.a, ,$(shell $(CC) -print-file-name=libc.a 2> /dev/null)) -lc +LIBS += -L$(subst libgcc.a, ,$(shell $(CC) -print-libgcc-file-name 2> /dev/null)) -lgcc + +################################################### +.SUFFIXES : .s .c .o + +################################################### +# command + +.PHONY: all +all: $(OUTPUT_FILE) + +################################################### +# Linker +################################################### +$(OUTPUT_FILE) : $(MEMORY_DEF) $(OBJ_FILE) + @echo 'const char build_message[] = "Built : "$(BUILD_MESSAGE_TIMESTAMP);' | \ + $(CC) $(CFLAGS) -xc - -o $(OUTDIR_OBJ)/build_message.o + + -mkdir "$(OUTDIR_REL)" + + $(LD) $(OBJ_FILE) $(OUTDIR_OBJ)/build_message.o \ + -T $(MEMORY_DEF) \ + -o $(OUTDIR_REL)/$(OUTPUT_FILE) \ + $(LDFLAGS) \ + -Map $(OUTDIR_REL)/$(FILE_NAME).map \ + $(LIBS) + + $(OC) -O srec --srec-forceS3 $(OUTDIR_REL)/$(OUTPUT_FILE) $(OUTDIR_REL)/$(FILE_NAME).srec + $(OC) -O binary $(OUTDIR_REL)/$(OUTPUT_FILE) $(OUTDIR_REL)/$(FILE_NAME).bin + $(OD) -dx $(OUTDIR_REL)/$(OUTPUT_FILE) > $(OUTDIR_REL)/$(FILE_NAME).dump + +################################################### +# Compile +################################################### + +$(OUTDIR_OBJ)/%.o:%.c + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + @$(CC) $(CFLAGS) -o $@ -c $< + +$(OUTDIR_OBJ)/%.o:%.S + @if [ ! -e `dirname $@` ]; then mkdir -p `dirname $@`; fi + @$(AS) $(ASFLAGS) -o $@ -c $< + + +.PHONY: clean +clean: + @rm -rf $(OUTDIR) diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4h.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4h.c new file mode 100644 index 0000000..18942e6 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4h.c @@ -0,0 +1,323 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2021-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table + ******************************************************************************/ +/****************************************************************************** + * @file cnf_tbl.c + * - Version : 0.04 + * @brief Configuration table for V4H. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 23.05.2022 0.02 Integration of S4 and V4H + * Renamed from conf_tbl.c to cnf_tbl_v4h.c. + * : 22.05.2023 0.03 Update the qos config table for response to past + * follow back. + * : 08.06.2023 0.04 Update the qos config table for ISP and VSPX. + *****************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include +#endif +#include + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".qosbw_tbl" +#else +__attribute__ ((section(".qoswt_tbl"))) +#endif +const QOS_SETTING_TABLE g_qosbw_tbl[] = { + [0] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [1] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [2] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [3] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [4] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [5] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [6] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [7] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [8] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [9] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [10] = {0x000C04010000FFFFULL, 0x0000000000000000ULL}, + [11] = {0x000C04080000FFFFULL, 0x00200030004FFC01ULL}, + [12] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [13] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [14] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [15] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [16] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [17] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [18] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [19] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [20] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [21] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [22] = {0x000C04100000FFFFULL, 0x0000000000000000ULL}, + [23] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL}, + [24] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL}, + [25] = {0x000000000000FFF0ULL, 0x0000000000000000ULL}, + [26] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [27] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [28] = {0x000C04100000FFFFULL, 0x0000000000000000ULL}, + [29] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [30] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL}, + [31] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [32] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [33] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [34] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [35] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [36] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [37] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [38] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [39] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [40] = {0x000C04010000FFFFULL, 0x001000F0004FFC01ULL}, + [41] = {0x000C04010000FFFFULL, 0x001000F0004FFC01ULL}, + [42] = {0x000C04010000FFFFULL, 0x002000F0004FFC01ULL}, + [43] = {0x000C04010000FFFFULL, 0x002000F0004FFC01ULL}, + [44] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [45] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [46] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [47] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [48] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [49] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [50] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [51] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [52] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [53] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [54] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [55] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [56] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [57] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [58] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [59] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [60] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [61] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [62] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [63] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [64] = {0x000C04200000FFFFULL, 0x00100030004FFC01ULL}, + [65] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [66] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [67] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [68] = {0x000C0C4F0000FFFFULL, 0x00100030004FFC01ULL}, + [69] = {0x000C0C4F0000FFFFULL, 0x00100030004FFC01ULL}, + [70] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [71] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [72] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [73] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [74] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL}, + [75] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL}, + [76] = {0x000C149E0000FFFFULL, 0x00100030004FFC01ULL}, + [77] = {0x000C149E0000FFFFULL, 0x00100030004FFC01ULL}, + [78] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [79] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [80] = {0x00140C050000FFFFULL, 0x00100030004FFC01ULL}, + [81] = {0x0014450E0000FFFFULL, 0x00100030004FFC01ULL}, + [82] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL}, + [83] = {0x0014289E0000FFFFULL, 0x00000000000FFC00ULL}, + [84] = {0x0014289E0000FFFFULL, 0x00000000000FFC00ULL}, + [85] = {0x0014149E0000FFFFULL, 0x0000000000000000ULL}, + [86] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [87] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [88] = {0x001004080000FFFFULL, 0x0000000000000000ULL}, + [89] = {0x001004080000FFFFULL, 0x0000000000000000ULL}, + [90] = {0x001004080000FFFFULL, 0x0000000000000000ULL}, + [91] = {0x000C00000000FFFFULL, 0x001000F0004FFC01ULL}, + [92] = {0x000C00000000FFFFULL, 0x001000F0004FFC01ULL}, + [93] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [94] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [95] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [96] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [97] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [98] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [99] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [100] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [101] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [102] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [103] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [104] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [105] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [106] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [107] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [108] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [109] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [110] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [111] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [112] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [113] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [114] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [115] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [116] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [117] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [118] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [119] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [120] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [121] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [122] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [123] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [124] = {0x001404010000FFFFULL, 0x00100030004FFC01ULL} +}; + + +/* Now go back to default rules */ +#if defined(__RH850G3K__) +#pragma ghs section rodata=default + +#pragma ghs section rodata=".qoswt_tbl" +#else +__attribute__ ((section(".qosbw_tbl"))) +#endif +const QOS_SETTING_TABLE g_qoswt_tbl[] = { + [0] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [1] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [2] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [3] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [4] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [5] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [6] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [7] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [8] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [9] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [10] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [11] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [12] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [13] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [14] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [15] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [16] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [17] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [18] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [19] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [20] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [21] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [22] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [23] = {0x000C04050000FFFFULL, 0x0000000000000000ULL}, + [24] = {0x000C080C0000FFFFULL, 0x0000000000000000ULL}, + [25] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [26] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [27] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [28] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [29] = {0x000C04050000C001ULL, 0x0000000000000000ULL}, + [30] = {0x000C080C0000C001ULL, 0x0000000000000000ULL}, + [31] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [32] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [33] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [34] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [35] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [36] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [37] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [38] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [39] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [40] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [41] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [42] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [43] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [44] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [45] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [46] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [47] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [48] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [49] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [50] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [51] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [52] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [53] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [54] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [55] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [56] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [57] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [58] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [59] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [60] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [61] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [62] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [63] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [64] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [65] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [66] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [67] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [68] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [69] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [70] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [71] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [72] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [73] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [74] = {0x001424870000C001ULL, 0x0000000000000000ULL}, + [75] = {0x001424870000C001ULL, 0x0000000000000000ULL}, + [76] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [77] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [78] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [79] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [80] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [81] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [82] = {0x001424870000FFFFULL, 0x0000000000000000ULL}, + [83] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [84] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [85] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [86] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [87] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [88] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [89] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [90] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [91] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [92] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [93] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [94] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [95] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [96] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [97] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [98] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [99] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [100] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [101] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [102] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [103] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [104] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [105] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [106] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [107] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [108] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [109] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [110] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [111] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [112] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [113] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [114] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [115] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [116] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [117] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [118] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [119] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [120] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [121] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [122] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [123] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [124] = {0x0000000000000000ULL, 0x0000000000000000ULL} +}; + + +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4m.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4m.c new file mode 100644 index 0000000..7a3e6cd --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/cnf_tbl_v4m.c @@ -0,0 +1,318 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table + ******************************************************************************/ +/****************************************************************************** + * @file cnf_tbl_v4m.c + * - Version : 0.01 + * @brief Configuration table for V4M. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + *****************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include +#endif +#include + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".qosbw_tbl" +#else +__attribute__ ((section(".qoswt_tbl"))) +#endif +const QOS_SETTING_TABLE g_qosbw_tbl[] = { + [0] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [1] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [2] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [3] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [4] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [5] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [6] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [7] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [8] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [9] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [10] = {0x000C04010000FFFFULL, 0x0000000000000000ULL}, + [11] = {0x000C04080000FFFFULL, 0x00200030004FFC01ULL}, + [12] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [13] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [14] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [15] = {0x000C04010000FFFFULL, 0x00200030004FFC01ULL}, + [16] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [17] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [18] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [19] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [20] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [21] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [22] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [23] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL}, + [24] = {0x0000000000000000ULL, 0x00100030004FFC01ULL}, + [25] = {0x000000000000FFF0ULL, 0x0000000000000000ULL}, + [26] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [27] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [28] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [29] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [30] = {0x000C08140000FFFFULL, 0x00100030004FFC01ULL}, + [31] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [32] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [33] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [34] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [35] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [36] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [37] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [38] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [39] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [40] = {0x000C04010000FFFFULL, 0x001000F0004FFC01ULL}, + [41] = {0x000C04010000FFFFULL, 0x001000F0004FFC01ULL}, + [42] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [43] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [44] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [45] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [46] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [47] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [48] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [49] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [50] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [51] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [52] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [53] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [54] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [55] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [56] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [57] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [58] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [59] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [60] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [61] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [62] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [63] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [64] = {0x000C04200000FFFFULL, 0x00100030004FFC01ULL}, + [65] = {0x000C04100000FFFFULL, 0x00100030004FFC01ULL}, + [66] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [67] = {0x000C144F0000FFFFULL, 0x00100030004FFC01ULL}, + [68] = {0x000C0C4F0000FFFFULL, 0x00100030004FFC01ULL}, + [69] = {0x000C0C4F0000FFFFULL, 0x00100030004FFC01ULL}, + [70] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [71] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [72] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [73] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [74] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL}, + [75] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL}, + [76] = {0x000C149E0000FFFFULL, 0x00100030004FFC01ULL}, + [77] = {0x000C149E0000FFFFULL, 0x00100030004FFC01ULL}, + [78] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [79] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [80] = {0x00140C050000FFFFULL, 0x00100030004FFC01ULL}, + [81] = {0x0014450E0000FFFFULL, 0x00100030004FFC01ULL}, + [82] = {0x001424870000FFFFULL, 0x00100030004FFC01ULL}, + [83] = {0x0014289E0000FFFFULL, 0x00000000000FFC00ULL}, + [84] = {0x0014289E0000FFFFULL, 0x00000000000FFC00ULL}, + [85] = {0x0014149E0000FFFFULL, 0x0000000000000000ULL}, + [86] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [87] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [88] = {0x001004080000FFFFULL, 0x0000000000000000ULL}, + [89] = {0x001004080000FFFFULL, 0x0000000000000000ULL}, + [90] = {0x001004080000FFFFULL, 0x0000000000000000ULL}, + [91] = {0x000C00000000FFFFULL, 0x001000F0004FFC01ULL}, + [92] = {0x000C00000000FFFFULL, 0x001000F0004FFC01ULL}, + [93] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [94] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [95] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [96] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [97] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [98] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [99] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [100] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [101] = {0x001404080000FFFFULL, 0x00100030004FFC01ULL}, + [102] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [103] = {0x000C04080000FFFFULL, 0x00100030004FFC01ULL}, + [104] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [105] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [106] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [107] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [108] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [109] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [110] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [111] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [112] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [113] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [114] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [115] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [116] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [117] = {0x000000000000FFFFULL, 0x0000000000000000ULL}, + [118] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [119] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [120] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [121] = {0x000C04010000FFFFULL, 0x001001D0004FFC01ULL}, + [122] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [123] = {0x000C04010000FFFFULL, 0x00100030004FFC01ULL}, + [124] = {0x001404010000FFFFULL, 0x00100030004FFC01ULL} +}; + + +/* Now go back to default rules */ +#if defined(__RH850G3K__) +#pragma ghs section rodata=default + +#pragma ghs section rodata=".qoswt_tbl" +#else +__attribute__ ((section(".qosbw_tbl"))) +#endif +const QOS_SETTING_TABLE g_qoswt_tbl[] = { + [0] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [1] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [2] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [3] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [4] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [5] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [6] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [7] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [8] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [9] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [10] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [11] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [12] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [13] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [14] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [15] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [16] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [17] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [18] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [19] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [20] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [21] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [22] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [23] = {0x000C04050000FFFFULL, 0x0000000000000000ULL}, + [24] = {0x000C080C0000FFFFULL, 0x0000000000000000ULL}, + [25] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [26] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [27] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [28] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [29] = {0x000C04050000C001ULL, 0x0000000000000000ULL}, + [30] = {0x000C080C0000C001ULL, 0x0000000000000000ULL}, + [31] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [32] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [33] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [34] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [35] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [36] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [37] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [38] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [39] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [40] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [41] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [42] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [43] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [44] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [45] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [46] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [47] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [48] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [49] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [50] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [51] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [52] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [53] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [54] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [55] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [56] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [57] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [58] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [59] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [60] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [61] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [62] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [63] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [64] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [65] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [66] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [67] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [68] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [69] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [70] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [71] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [72] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [73] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [74] = {0x001424870000C001ULL, 0x0000000000000000ULL}, + [75] = {0x001424870000C001ULL, 0x0000000000000000ULL}, + [76] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [77] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [78] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [79] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [80] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [81] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [82] = {0x001424870000FFFFULL, 0x0000000000000000ULL}, + [83] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [84] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [85] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [86] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [87] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [88] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [89] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [90] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [91] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [92] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [93] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [94] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [95] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [96] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [97] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [98] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [99] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [100] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [101] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [102] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [103] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [104] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [105] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [106] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [107] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [108] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [109] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [110] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [111] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [112] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [113] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [114] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [115] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [116] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [117] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [118] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [119] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [120] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [121] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [122] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [123] = {0x0000000000000000ULL, 0x0000000000000000ULL}, + [124] = {0x0000000000000000ULL, 0x0000000000000000ULL} +}; + + +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4h.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4h.c new file mode 100644 index 0000000..f0d1dee --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4h.c @@ -0,0 +1,3434 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table + ******************************************************************************/ +/****************************************************************************** + * @file rgidcnf_tbl_v4h.c + * - Version : 0.07 + * @brief Configuration table for V4H. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 16.12.2022 0.01 First Release + * : 23.01.2023 0.02 Added RAM protection table. + * Update Region ID settings. + * : 07.02.2024 0.03 Update System RAM protection setting Area0. + * : 30.08.2024 0.04 Updated Region ID and RAM protection setting + * for QNX. + * : 05.12.2024 0.05 Update RAM protection settings for ICCOM + * memory area (SDRAM Area5). + * Update Region ID settings for VSPD and VSPX. + * Update Region ID settings for IPMMU. + * Update RAM protection setting. + * : 16.12.2024 0.06 Updated Region ID setting. + * Updated Region ID setting and RAM protection + * setting for booting CR52 3 cores. + * Added IMP Region ID table. + * Added IPMMU Region ID table. + * : 26.05.2025 0.07 Updated RAM protection settings for + * protection area. + *****************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include +#endif +#include +#include +#include "ram_protection.h" + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_m_tbl" +#else +__attribute__ ((section(".rgid_m_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_master_tbl[] = { + [0] = {0xE6581000U, 0x00000002U}, /* RGIDM_MODID[0]:PCI0 */ + [1] = {0xE6581020U, 0x00000002U}, /* RGIDM_MODID[1]:PCI1 */ + [2] = {0xE6581024U, 0x00000002U}, /* RGIDM_MODID[2]:PCI2 */ + [3] = {0xE6581034U, 0x00000002U}, /* RGIDM_MODID[3]:PCI3 */ + [4] = {0xE6581010U, 0x00000002U}, /* RGIDM_MODID[4]:AVB0 */ + [5] = {0xE6581014U, 0x00000001U}, /* RGIDM_MODID[5]:AVB1 */ + [6] = {0xE6581018U, 0x00000001U}, /* RGIDM_MODID[6]:AVB2 */ + [7] = {0xE6581040U, 0x00000002U}, /* RGIDM_MODID[7]:TSN */ + [8] = {0xE6621004U, 0x00000000U}, /* RGIDM_MODID[8]:CR0 */ + [9] = {0xE662100CU, 0x00000000U}, /* RGIDM_MODID[9]:DCLS_ICUMX */ + [10] = {0xE6621010U, 0x00000000U}, /* RGIDM_MODID[10]:ICUMX */ + [11] = {0xE6621014U, 0x00000000U}, /* RGIDM_MODID[11]:SDMAC_ICUMX */ + [12] = {0xFFC41018U, 0x00000001U}, /* RGIDM_MODID[12]:CR52SS0 */ + [13] = {0xFFC4105CU, 0x00000001U}, /* RGIDM_MODID[13]:CR52SS1 */ + [14] = {0xFFC41060U, 0x00000006U}, /* RGIDM_MODID[14]:CR52SS2 */ + [15] = {0xFFC4101CU, 0x00000003U}, /* RGIDM_MODID[15]:CSD */ + [16] = {0xFFC41024U, 0x00000002U}, /* RGIDM_MODID[16]:INTAP0 */ + [17] = {0xFF861018U, 0x00000002U}, /* RGIDM_MODID[17]:FBABUSTOP0 */ + [18] = {0xFF86101CU, 0x00000002U}, /* RGIDM_MODID[18]:FBABUSTOP1 */ + [19] = {0xE7751020U, 0x00000002U}, /* RGIDM_MODID[19]:SDHI0 */ + [20] = {0xE7751010U, 0x00000001U}, /* RGIDM_MODID[20]:FRAY */ + [21] = {0xE7751014U, 0x00000002U}, /* RGIDM_MODID[21]:IPC */ + [22] = {0xFF811000U, 0x00000002U}, /* RGIDM_MODID[22]:AXMM2AXSTM */ + [23] = {0xFF811004U, 0x00000003U}, /* RGIDM_MODID[23]:CSDE0 */ + [24] = {0xFF811008U, 0x00000003U}, /* RGIDM_MODID[24]:CSDE1 */ + [25] = {0xFF881004U, 0x00000002U}, /* RGIDM_MODID[25]:FBABUSIR0 */ + [26] = {0xFF881008U, 0x00000002U}, /* RGIDM_MODID[26]:FBABUSIR1 */ + [27] = {0xFF88100CU, 0x00000002U}, /* RGIDM_MODID[27]:FBABUSIR2 */ + [28] = {0xFF881010U, 0x00000002U}, /* RGIDM_MODID[28]:FBABUSIR3 */ + [29] = {0xFF881014U, 0x00000002U}, /* RGIDM_MODID[29]:FBABUSIR4 */ + [30] = {0xFD811014U, 0x00000002U}, /* RGIDM_MODID[30]:RGX0 */ + [31] = {0xFE681004U, 0x00000002U}, /* RGIDM_MODID[31]:FBABUSVC */ + [32] = {0xFE681008U, 0x00000005U}, /* RGIDM_MODID[32]:FCPCS */ + [33] = {0xFE681010U, 0x00000002U}, /* RGIDM_MODID[33]:IMR00 */ + [34] = {0xFE681014U, 0x00000002U}, /* RGIDM_MODID[34]:IMR01 */ + [35] = {0xFE681024U, 0x00000002U}, /* RGIDM_MODID[35]:IMR10 */ + [36] = {0xFE681028U, 0x00000002U}, /* RGIDM_MODID[36]:IMR11 */ + [37] = {0xFE68100CU, 0x00000002U}, /* RGIDM_MODID[37]:IMR20 */ + [38] = {0xFE681018U, 0x00000002U}, /* RGIDM_MODID[38]:IMR21 */ + [39] = {0xFE681040U, 0x00000002U}, /* RGIDM_MODID[39]:IMS0 */ + [40] = {0xFE681044U, 0x00000002U}, /* RGIDM_MODID[40]:IMS1 */ + [41] = {0xFE681048U, 0x00000005U}, /* RGIDM_MODID[41]:IV1ES */ + [42] = {0xFEBE1000U, 0x00000002U}, /* RGIDM_MODID[42]:DSITLINK0 */ + [43] = {0xFEBE1004U, 0x00000002U}, /* RGIDM_MODID[43]:DSTLINK1 */ + [44] = {0xFEBE1008U, 0x00000002U}, /* RGIDM_MODID[44]:FBABUSVIO */ + [45] = {0xFEBE1014U, 0x00000002U}, /* RGIDM_MODID[45]:FCPVD0 */ + [46] = {0xFEBE1018U, 0x00000002U}, /* RGIDM_MODID[46]:FCPVD1 */ + [47] = {0xFEBE101CU, 0x00000002U}, /* RGIDM_MODID[47]:FCPVX0 */ + [48] = {0xFEBE1020U, 0x00000002U}, /* RGIDM_MODID[48]:FCPVX1 */ + [49] = {0xFEBF1020U, 0x00000002U}, /* RGIDM_MODID[49]:ISP00 */ + [50] = {0xFEBF1024U, 0x00000002U}, /* RGIDM_MODID[50]:ISP01 */ + [51] = {0xFEBF1000U, 0x00000002U}, /* RGIDM_MODID[51]:ISP02 */ + [52] = {0xFEBF1004U, 0x00000002U}, /* RGIDM_MODID[52]:ISP03 */ + [53] = {0xFEBF1008U, 0x00000002U}, /* RGIDM_MODID[53]:ISP04 */ + [54] = {0xFEBF1028U, 0x00000002U}, /* RGIDM_MODID[54]:ISP10 */ + [55] = {0xFEBF102CU, 0x00000002U}, /* RGIDM_MODID[55]:ISP11 */ + [56] = {0xFEBF1044U, 0x00000002U}, /* RGIDM_MODID[56]:ISP12 */ + [57] = {0xFEBF104CU, 0x00000002U}, /* RGIDM_MODID[57]:ISP13 */ + [58] = {0xFEBF1050U, 0x00000002U}, /* RGIDM_MODID[58]:ISP14 */ + [59] = {0xFEBF1010U, 0x00000002U}, /* RGIDM_MODID[59]:VIN0 */ + [60] = {0xFEBF1014U, 0x00000002U}, /* RGIDM_MODID[60]:VIN1 */ + [61] = {0xE7B11004U, 0x00000002U}, /* RGIDM_MODID[61]:FBABUSVIP0 */ + [62] = {0xE7B11010U, 0x00000002U}, /* RGIDM_MODID[62]:SMPO */ + [63] = {0xE7B11018U, 0x00000002U}, /* RGIDM_MODID[63]:SMPS */ + [64] = {0xE7B1101CU, 0x00000002U}, /* RGIDM_MODID[64]:UMFL */ + [65] = {0xE7B41018U, 0x00000002U}, /* RGIDM_MODID[65]:PAP */ + [66] = {0xE7B41028U, 0x00000002U}, /* RGIDM_MODID[66]:FBABUSVIP1 */ + [67] = {0xEB801000U, 0x00000002U}, /* RGIDM_MODID[67]:DSP00 */ + [68] = {0xEB801004U, 0x00000002U}, /* RGIDM_MODID[68]:DSP01 */ + [69] = {0xEB801008U, 0x00000002U}, /* RGIDM_MODID[69]:DSP10 */ + [70] = {0xEB80100CU, 0x00000002U}, /* RGIDM_MODID[70]:DSP11 */ + [71] = {0xEB801010U, 0x00000002U}, /* RGIDM_MODID[71]:DSP20 */ + [72] = {0xEB801014U, 0x00000002U}, /* RGIDM_MODID[72]:DSP21 */ + [73] = {0xEB801018U, 0x00000002U}, /* RGIDM_MODID[73]:DSP30 */ + [74] = {0xEB80101CU, 0x00000002U}, /* RGIDM_MODID[74]:DSP31 */ + [75] = {0xE67BF500U, 0x0000000EU}, /* RGIDM_MODID[75]:VRAM_R */ + [76] = {0xE67BF504U, 0x0000000EU}, /* RGIDM_MODID[76]:VRAM_W */ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_r_tbl" +#else +__attribute__ ((section(".rgid_r_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_read_tbl[] = { + [0] = {0xFFC82000U, 0x0000000FU}, /* RGIDR_MODID[0]:ARMGC0*/ + [1] = {0xFFC82004U, 0x0000000FU}, /* RGIDR_MODID[1]:ARMGC1*/ + [2] = {0xFFC82008U, 0x00000000U}, /* RGIDR_MODID[2]:ARMGC2*/ + [3] = {0xFFC8200CU, 0x0000000FU}, /* RGIDR_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDR_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDR_MODID[5]:ARRT02*/ + [4] = {0xFFC82018U, 0x0000000FU}, /* RGIDR_MODID[6]:ARRT03*/ + [5] = {0xFFC8201CU, 0x0000000FU}, /* RGIDR_MODID[7]:ARRT04*/ + [6] = {0xFFC82020U, 0x0000000FU}, /* RGIDR_MODID[8]:ARRT05*/ + [7] = {0xFFC82024U, 0x0000000FU}, /* RGIDR_MODID[9]:ARRT06*/ + [8] = {0xFFC82028U, 0x0000000FU}, /* RGIDR_MODID[10]:ARRT07*/ + [9] = {0xFFC8202CU, 0x00000000U}, /* RGIDR_MODID[11]:ARRT08*/ + [10] = {0xFFC82030U, 0x00000001U}, /* RGIDR_MODID[12]:LIFEC0*/ + [11] = {0xFFC82034U, 0x0000000EU}, /* RGIDR_MODID[13]:SWDT*/ + [12] = {0xFFC82038U, 0x0000006EU}, /* RGIDR_MODID[14]:TMU0*/ + [13] = {0xFFC8203CU, 0x0000000EU}, /* RGIDR_MODID[15]:WDT*/ + [14] = {0xFFC82040U, 0x0000000EU}, /* RGIDR_MODID[16]:WWDT0*/ + [15] = {0xFFC82044U, 0x0000000EU}, /* RGIDR_MODID[17]:WWDT1*/ + [16] = {0xFFC82048U, 0x0000000EU}, /* RGIDR_MODID[18]:WWDT2*/ + [17] = {0xFFC8204CU, 0x0000000EU}, /* RGIDR_MODID[19]:WWDT3*/ + [18] = {0xFFC82050U, 0x0000000EU}, /* RGIDR_MODID[20]:WWDT4*/ + [19] = {0xFFC82054U, 0x0000000EU}, /* RGIDR_MODID[21]:WWDT5*/ + [20] = {0xFFC82058U, 0x0000000EU}, /* RGIDR_MODID[22]:WWDT6*/ + [21] = {0xFFC82068U, 0x0000000FU}, /* RGIDR_MODID[23]:ECMRT3*/ + [22] = {0xE6002000U, 0x0000000EU}, /* RGIDR_MODID[24]:ADVFSC*/ + [23] = {0xE6002004U, 0x0000000FU}, /* RGIDR_MODID[25]:APMU0*/ + [24] = {0xE6002008U, 0x00000002U}, /* RGIDR_MODID[26]:APMU1*/ + [25] = {0xE600200CU, 0x00000000U}, /* RGIDR_MODID[27]:APMU10*/ + [26] = {0xE6002010U, 0x00000000U}, /* RGIDR_MODID[28]:APMU11*/ + [27] = {0xE6002014U, 0x00000000U}, /* RGIDR_MODID[29]:APMU12*/ + [28] = {0xE6002018U, 0x00000000U}, /* RGIDR_MODID[30]:APMU13*/ + [29] = {0xE600201CU, 0x00000000U}, /* RGIDR_MODID[31]:APMU14*/ + [30] = {0xE6002020U, 0x00000000U}, /* RGIDR_MODID[32]:APMU15*/ + [31] = {0xE6002024U, 0x00000004U}, /* RGIDR_MODID[33]:APMU2*/ + [32] = {0xE6002028U, 0x00000004U}, /* RGIDR_MODID[34]:APMU3*/ + [33] = {0xE600202CU, 0x00000000U}, /* RGIDR_MODID[35]:APMU4*/ + [34] = {0xE6002030U, 0x00000000U}, /* RGIDR_MODID[36]:APMU5*/ + [35] = {0xE6002034U, 0x00000000U}, /* RGIDR_MODID[37]:APMU6*/ + [36] = {0xE6002038U, 0x00000000U}, /* RGIDR_MODID[38]:APMU7*/ + [37] = {0xE600203CU, 0x00000000U}, /* RGIDR_MODID[39]:APMU8*/ + [38] = {0xE6002040U, 0x00000000U}, /* RGIDR_MODID[40]:APMU9*/ + [39] = {0xE6002044U, 0x0000000FU}, /* RGIDR_MODID[41]:ARS00*/ + /* After setting */ /* RGIDR_MODID[42]:ARS01*/ + /* After setting */ /* RGIDR_MODID[43]:ARS02*/ + [40] = {0xE6002050U, 0x0000000FU}, /* RGIDR_MODID[44]:ARS03*/ + [41] = {0xE6002054U, 0x0000000FU}, /* RGIDR_MODID[45]:ARS04*/ + [42] = {0xE6002058U, 0x0000000FU}, /* RGIDR_MODID[46]:ARS05*/ + [43] = {0xE600205CU, 0x0000000FU}, /* RGIDR_MODID[47]:ARS06*/ + [44] = {0xE6002060U, 0x0000000FU}, /* RGIDR_MODID[48]:ARS07*/ + [45] = {0xE6002064U, 0x00000000U}, /* RGIDR_MODID[49]:ARS08*/ + [46] = {0xE6002068U, 0x0000000EU}, /* RGIDR_MODID[50]:CMT0*/ + [47] = {0xE600206CU, 0x0000000EU}, /* RGIDR_MODID[51]:CMT1*/ + [48] = {0xE6002070U, 0x0000000EU}, /* RGIDR_MODID[52]:CMT2*/ + [49] = {0xE6002074U, 0x0000000EU}, /* RGIDR_MODID[53]:CMT3*/ + [50] = {0xE6002078U, 0x0000000AU}, /* RGIDR_MODID[54]:CKM*/ + [51] = {0xE600207CU, 0x0000000EU}, /* RGIDR_MODID[55]:DBE*/ + [52] = {0xE6002080U, 0x0000000EU}, /* RGIDR_MODID[56]:IRQC*/ + [53] = {0xE6002084U, 0x0000000FU}, /* RGIDR_MODID[57]:ECMPS0*/ + [54] = {0xE6002088U, 0x0000000BU}, /* RGIDR_MODID[58]:OTP0*/ + [55] = {0xE600208CU, 0x0000000FU}, /* RGIDR_MODID[59]:OTP1*/ + [56] = {0xE600209CU, 0x0000000EU}, /* RGIDR_MODID[60]:SCMT*/ + [57] = {0xE60020A8U, 0x0000004EU}, /* RGIDR_MODID[61]:TSC1*/ + [58] = {0xE60020ACU, 0x0000004EU}, /* RGIDR_MODID[62]:TSC2*/ + [59] = {0xE60020B0U, 0x0000004EU}, /* RGIDR_MODID[63]:TSC3*/ + [60] = {0xE60020B4U, 0x0000004EU}, /* RGIDR_MODID[64]:TSC4*/ + [61] = {0xE60020B8U, 0x00000006U}, /* RGIDR_MODID[65]:UCMT*/ + [62] = {0xE6002100U, 0x0000006FU}, /* RGIDR_MODID[66]:CPG0*/ + [63] = {0xE6002104U, 0x0000000AU}, /* RGIDR_MODID[67]:CPG1*/ + [64] = {0xE6002108U, 0x0000004EU}, /* RGIDR_MODID[68]:CPG2*/ + [65] = {0xE600210CU, 0x00000028U}, /* RGIDR_MODID[69]:CPG3*/ + [66] = {0xE6002110U, 0x0000006FU}, /* RGIDR_MODID[70]:PFC00*/ + [67] = {0xE6002114U, 0x0000000AU}, /* RGIDR_MODID[71]:PFC01*/ + [68] = {0xE6002118U, 0x0000004EU}, /* RGIDR_MODID[72]:PFC02*/ + [69] = {0xE600211CU, 0x00000028U}, /* RGIDR_MODID[73]:PFC03*/ + [70] = {0xE6002120U, 0x0000006FU}, /* RGIDR_MODID[74]:PFC10*/ + [71] = {0xE6002124U, 0x0000000AU}, /* RGIDR_MODID[75]:PFC11*/ + [72] = {0xE6002128U, 0x0000004EU}, /* RGIDR_MODID[76]:PFC12*/ + [73] = {0xE600212CU, 0x00000028U}, /* RGIDR_MODID[77]:PFC13*/ + [74] = {0xE6002130U, 0x0000006FU}, /* RGIDR_MODID[78]:PFC20*/ + [75] = {0xE6002134U, 0x0000000AU}, /* RGIDR_MODID[79]:PFC21*/ + [76] = {0xE6002138U, 0x0000004EU}, /* RGIDR_MODID[80]:PFC22*/ + [77] = {0xE600213CU, 0x00000028U}, /* RGIDR_MODID[81]:PFC23*/ + [78] = {0xE6002140U, 0x0000006FU}, /* RGIDR_MODID[82]:PFC30*/ + [79] = {0xE6002144U, 0x0000000AU}, /* RGIDR_MODID[83]:PFC31*/ + [80] = {0xE6002148U, 0x0000004EU}, /* RGIDR_MODID[84]:PFC32*/ + [81] = {0xE600214CU, 0x00000028U}, /* RGIDR_MODID[85]:PFC33*/ + [82] = {0xE6002150U, 0x0000006FU}, /* RGIDR_MODID[86]:PFCS0*/ + [83] = {0xE6002154U, 0x0000000AU}, /* RGIDR_MODID[87]:PFCS1*/ + [84] = {0xE6002158U, 0x0000004EU}, /* RGIDR_MODID[88]:PFCS2*/ + [85] = {0xE600215CU, 0x00000028U}, /* RGIDR_MODID[89]:PFCS3*/ + [86] = {0xE6002160U, 0x0000006FU}, /* RGIDR_MODID[90]:RESET0*/ + [87] = {0xE6002164U, 0x0000000AU}, /* RGIDR_MODID[91]:RESET1*/ + [88] = {0xE6002168U, 0x0000004EU}, /* RGIDR_MODID[92]:RESET2*/ + [89] = {0xE600216CU, 0x00000028U}, /* RGIDR_MODID[93]:RESET3*/ + [90] = {0xE6002170U, 0x0000006FU}, /* RGIDR_MODID[94]:SYS0*/ + [91] = {0xE6002174U, 0x0000000AU}, /* RGIDR_MODID[95]:SYS1*/ + [92] = {0xE6002178U, 0x0000004EU}, /* RGIDR_MODID[96]:SYS2*/ + [93] = {0xE600217CU, 0x00000028U}, /* RGIDR_MODID[97]:SYS3*/ + [94] = {0xE7762000U, 0x0000000EU}, /* RGIDR_MODID[98]:DMAMSI0*/ + [95] = {0xE7762004U, 0x0000000EU}, /* RGIDR_MODID[99]:DMAMSI1*/ + [96] = {0xE7762008U, 0x0000000EU}, /* RGIDR_MODID[100]:DMAMSI2*/ + [97] = {0xE776200CU, 0x0000000EU}, /* RGIDR_MODID[101]:DMAMSI3*/ + [98] = {0xE7762010U, 0x0000000EU}, /* RGIDR_MODID[102]:DMAMSI4*/ + [99] = {0xE7762014U, 0x0000000EU}, /* RGIDR_MODID[103]:DMAMSI5*/ + [100] = {0xE7762018U, 0x0000000FU}, /* RGIDR_MODID[104]:ECMSP3*/ + [101] = {0xE7762024U, 0x0000000FU}, /* RGIDR_MODID[105]:ARSP30*/ + /* After setting */ /* RGIDR_MODID[106]:ARSP31*/ + /* After setting */ /* RGIDR_MODID[107]:ARSP32*/ + [102] = {0xE7762030U, 0x0000000FU}, /* RGIDR_MODID[108]:ARSP33*/ + [103] = {0xE7762034U, 0x0000000FU}, /* RGIDR_MODID[109]:ARSP34*/ + [104] = {0xE7762038U, 0x0000000FU}, /* RGIDR_MODID[110]:ARSP35*/ + [105] = {0xE776203CU, 0x0000000FU}, /* RGIDR_MODID[111]:ARSP36*/ + [106] = {0xE7762040U, 0x0000000FU}, /* RGIDR_MODID[112]:ARSP37*/ + [107] = {0xE7762044U, 0x00000000U}, /* RGIDR_MODID[113]:ARSP38*/ + [108] = {0xE7762048U, 0x0000000EU}, /* RGIDR_MODID[114]:MSI0*/ + [109] = {0xE776204CU, 0x0000000EU}, /* RGIDR_MODID[115]:MSI1*/ + [110] = {0xE7762050U, 0x0000000EU}, /* RGIDR_MODID[116]:MSI2*/ + [111] = {0xE7762054U, 0x0000000EU}, /* RGIDR_MODID[117]:MSI3*/ + [112] = {0xE7762058U, 0x0000000EU}, /* RGIDR_MODID[118]:MSI4*/ + [113] = {0xE776205CU, 0x0000000EU}, /* RGIDR_MODID[119]:MSI5*/ + [114] = {0xE7792000U, 0x0000000FU}, /* RGIDR_MODID[120]:ARSP40*/ + /* After setting */ /* RGIDR_MODID[121]:ARSP41*/ + /* After setting */ /* RGIDR_MODID[122]:ARSP42*/ + [115] = {0xE779200CU, 0x0000000FU}, /* RGIDR_MODID[123]:ARSP43*/ + [116] = {0xE7792010U, 0x0000000FU}, /* RGIDR_MODID[124]:ARSP44*/ + [117] = {0xE7792014U, 0x0000000FU}, /* RGIDR_MODID[125]:ARSP45*/ + [118] = {0xE7792018U, 0x0000000FU}, /* RGIDR_MODID[126]:ARSP46*/ + [119] = {0xE779201CU, 0x0000000FU}, /* RGIDR_MODID[127]:ARSP47*/ + [120] = {0xE7792020U, 0x00000000U}, /* RGIDR_MODID[128]:ARSP48*/ + [121] = {0xE7792024U, 0x0000004FU}, /* RGIDR_MODID[129]:DMAHSCIF0*/ + [122] = {0xE7792028U, 0x0000004FU}, /* RGIDR_MODID[130]:DMAHSCIF1*/ + [123] = {0xE779202CU, 0x0000004FU}, /* RGIDR_MODID[131]:DMAHSCIF2*/ + [124] = {0xE7792030U, 0x0000004FU}, /* RGIDR_MODID[132]:DMAHSCIF3*/ + [125] = {0xE7792034U, 0x0000004FU}, /* RGIDR_MODID[133]:DMASCIF0*/ + [126] = {0xE7792038U, 0x0000004FU}, /* RGIDR_MODID[134]:DMASCIF1*/ + [127] = {0xE779203CU, 0x0000004FU}, /* RGIDR_MODID[135]:DMASCIF3*/ + [128] = {0xE7792040U, 0x0000004FU}, /* RGIDR_MODID[136]:DMASCIF4*/ + [129] = {0xE7792044U, 0x0000000FU}, /* RGIDR_MODID[137]:ECMSP4*/ + [130] = {0xE7792048U, 0x0000004FU}, /* RGIDR_MODID[138]:HSCIF0*/ + [131] = {0xE779204CU, 0x0000004FU}, /* RGIDR_MODID[139]:HSCIF1*/ + [132] = {0xE7792050U, 0x0000004FU}, /* RGIDR_MODID[140]:HSCIF2*/ + [133] = {0xE7792054U, 0x0000004FU}, /* RGIDR_MODID[141]:HSCIF3*/ + [134] = {0xE7792058U, 0x0000004FU}, /* RGIDR_MODID[142]:SCIF0*/ + [135] = {0xE779205CU, 0x0000004FU}, /* RGIDR_MODID[143]:SCIF1*/ + [136] = {0xE7792060U, 0x0000004FU}, /* RGIDR_MODID[144]:SCIF3*/ + [137] = {0xE7792064U, 0x0000004FU}, /* RGIDR_MODID[145]:SCIF4*/ + [138] = {0xE7792068U, 0x0000006EU}, /* RGIDR_MODID[146]:TMU1*/ + [139] = {0xE779206CU, 0x0000006EU}, /* RGIDR_MODID[147]:TMU2*/ + [140] = {0xE7792070U, 0x0000006EU}, /* RGIDR_MODID[148]:TMU3*/ + [141] = {0xE7792074U, 0x0000006EU}, /* RGIDR_MODID[149]:TMU4*/ + [142] = {0xE7792078U, 0x0000004AU}, /* RGIDR_MODID[150]:CANFD*/ + [143] = {0xE779207CU, 0x0000004AU}, /* RGIDR_MODID[151]:DMACANFD*/ + [144] = {0xE7792080U, 0x00000002U}, /* RGIDR_MODID[152]:DMATPU0*/ + [145] = {0xE7792084U, 0x00000002U}, /* RGIDR_MODID[153]:PWM0*/ + [146] = {0xE7792088U, 0x00000002U}, /* RGIDR_MODID[154]:PWM1*/ + [147] = {0xE779208CU, 0x00000002U}, /* RGIDR_MODID[155]:PWM2*/ + [148] = {0xE7792090U, 0x00000002U}, /* RGIDR_MODID[156]:PWM3*/ + [149] = {0xE7792094U, 0x00000002U}, /* RGIDR_MODID[157]:PWM4*/ + [150] = {0xE7792098U, 0x00000002U}, /* RGIDR_MODID[158]:PWM5*/ + [151] = {0xE779209CU, 0x00000002U}, /* RGIDR_MODID[159]:PWM6*/ + [152] = {0xE77920A0U, 0x00000002U}, /* RGIDR_MODID[160]:PWM7*/ + [153] = {0xE77920A4U, 0x00000002U}, /* RGIDR_MODID[161]:PWM8*/ + [154] = {0xE77920A8U, 0x00000002U}, /* RGIDR_MODID[162]:PWM9*/ + [155] = {0xE77920ACU, 0x00000002U}, /* RGIDR_MODID[163]:TPU0*/ + [156] = {0xFE672000U, 0x0000002FU}, /* RGIDR_MODID[164]:ARVC10*/ + /* After setting */ /* RGIDR_MODID[165]:ARVC11*/ + /* After setting */ /* RGIDR_MODID[166]:ARVC12*/ + [157] = {0xFE67200CU, 0x0000002FU}, /* RGIDR_MODID[167]:ARVC13*/ + [158] = {0xFE672010U, 0x0000002FU}, /* RGIDR_MODID[168]:ARVC14*/ + [159] = {0xFE672014U, 0x0000002FU}, /* RGIDR_MODID[169]:ARVC15*/ + [160] = {0xFE672018U, 0x0000002FU}, /* RGIDR_MODID[170]:ARVC16*/ + [161] = {0xFE67201CU, 0x0000002FU}, /* RGIDR_MODID[171]:ARVC17*/ + [162] = {0xFE672020U, 0x00000000U}, /* RGIDR_MODID[172]:ARVC18*/ + [163] = {0xFE672024U, 0x0000000FU}, /* RGIDR_MODID[173]:ECMVC1*/ + [164] = {0xFE672028U, 0x00000028U}, /* RGIDR_MODID[174]:FCPCS*/ + [165] = {0xFE67202CU, 0x00000028U}, /* RGIDR_MODID[175]:VCP4LC*/ + [166] = {0xFE672030U, 0x00000028U}, /* RGIDR_MODID[176]:VCP4LV*/ + [167] = {0xFEBD2000U, 0x0000000FU}, /* RGIDR_MODID[177]:ARVI40*/ + /* After setting */ /* RGIDR_MODID[178]:ARVI41*/ + /* After setting */ /* RGIDR_MODID[179]:ARVI42*/ + [168] = {0xFEBD200CU, 0x0000000FU}, /* RGIDR_MODID[180]:ARVI43*/ + [169] = {0xFEBD2010U, 0x0000000FU}, /* RGIDR_MODID[181]:ARVI44*/ + [170] = {0xFEBD2014U, 0x0000000FU}, /* RGIDR_MODID[182]:ARVI45*/ + [171] = {0xFEBD2018U, 0x0000000FU}, /* RGIDR_MODID[183]:ARVI46*/ + [172] = {0xFEBD201CU, 0x0000000FU}, /* RGIDR_MODID[184]:ARVI47*/ + [173] = {0xFEBD2020U, 0x00000000U}, /* RGIDR_MODID[185]:ARVI48*/ + [174] = {0xFEBD2024U, 0x0000000FU}, /* RGIDR_MODID[186]:DIS0*/ + [175] = {0xFEBD202CU, 0x0000000FU}, /* RGIDR_MODID[187]:DSC*/ + [176] = {0xFEBD2030U, 0x0000000FU}, /* RGIDR_MODID[188]:ECMVIO2*/ + [177] = {0xFEBD2034U, 0x0000000FU}, /* RGIDR_MODID[189]:FCPVD0*/ + [178] = {0xFEBD2038U, 0x0000000FU}, /* RGIDR_MODID[190]:FCPVD1*/ + [179] = {0xFEBD203CU, 0x0000004EU}, /* RGIDR_MODID[191]:VSPD0*/ + [180] = {0xFEBD2040U, 0x0000004EU}, /* RGIDR_MODID[192]:VSPD1*/ + [181] = {0xE6582000U, 0x0000000AU}, /* RGIDR_MODID[193]:CKMHSC*/ + [182] = {0xE6582004U, 0x0000000CU}, /* RGIDR_MODID[194]:AXIPCI001*/ + [183] = {0xE6582008U, 0x0000000CU}, /* RGIDR_MODID[195]:AXIPCI002*/ + [184] = {0xE658200CU, 0x0000000CU}, /* RGIDR_MODID[196]:AXIPCI003*/ + [185] = {0xE6582014U, 0x0000000CU}, /* RGIDR_MODID[197]:AXIPCI005*/ + [186] = {0xE6582018U, 0x0000000CU}, /* RGIDR_MODID[198]:AXIPCI006*/ + [187] = {0xE658201CU, 0x0000000CU}, /* RGIDR_MODID[199]:AXIPCI007*/ + [188] = {0xE6582020U, 0x0000000CU}, /* RGIDR_MODID[200]:AXIPCI008*/ + [189] = {0xE6582024U, 0x0000000CU}, /* RGIDR_MODID[201]:AXIPCI009*/ + [190] = {0xE6582028U, 0x0000000CU}, /* RGIDR_MODID[202]:AXIPCI010*/ + [191] = {0xE658202CU, 0x0000000CU}, /* RGIDR_MODID[203]:AXIPCI011*/ + [192] = {0xE6582030U, 0x0000000CU}, /* RGIDR_MODID[204]:AXIPCI012*/ + [193] = {0xE6582034U, 0x0000000CU}, /* RGIDR_MODID[205]:AXIPCI013*/ + [194] = {0xE6582038U, 0x0000000CU}, /* RGIDR_MODID[206]:AXIPCI014*/ + [195] = {0xE658203CU, 0x0000000CU}, /* RGIDR_MODID[207]:AXIPCI015*/ + [196] = {0xE6582040U, 0x0000000CU}, /* RGIDR_MODID[208]:AXIPCI100*/ + [197] = {0xE6582044U, 0x0000000CU}, /* RGIDR_MODID[209]:AXIPCI101*/ + [198] = {0xE6582048U, 0x0000000CU}, /* RGIDR_MODID[210]:AXIPCI102*/ + [199] = {0xE658204CU, 0x0000000CU}, /* RGIDR_MODID[211]:AXIPCI103*/ + [200] = {0xE6582050U, 0x0000000CU}, /* RGIDR_MODID[212]:AXIPCI104*/ + [201] = {0xE6582054U, 0x0000000CU}, /* RGIDR_MODID[213]:AXIPCI105*/ + [202] = {0xE6582058U, 0x0000000CU}, /* RGIDR_MODID[214]:AXIPCI106*/ + [203] = {0xE658205CU, 0x0000000CU}, /* RGIDR_MODID[215]:AXIPCI107*/ + [204] = {0xE6582060U, 0x0000000CU}, /* RGIDR_MODID[216]:AXIPCI108*/ + [205] = {0xE6582064U, 0x0000000CU}, /* RGIDR_MODID[217]:AXIPCI109*/ + [206] = {0xE6582068U, 0x0000000CU}, /* RGIDR_MODID[218]:AXIPCI110*/ + [207] = {0xE658206CU, 0x0000000CU}, /* RGIDR_MODID[219]:AXIPCI111*/ + [208] = {0xE6582070U, 0x0000000CU}, /* RGIDR_MODID[220]:AXIPCI112*/ + [209] = {0xE6582074U, 0x0000000CU}, /* RGIDR_MODID[221]:AXIPCI113*/ + [210] = {0xE6582078U, 0x0000000CU}, /* RGIDR_MODID[222]:AXIPCI114*/ + [211] = {0xE658207CU, 0x0000000CU}, /* RGIDR_MODID[223]:AXIPCI115*/ + [212] = {0xE6582084U, 0x0000000EU}, /* RGIDR_MODID[224]:GPTP*/ + [213] = {0xE6582088U, 0x0000004EU}, /* RGIDR_MODID[225]:IPMMUHC00*/ + [214] = {0xE65820F0U, 0x0000000EU}, /* RGIDR_MODID[226]:TSN0*/ + [215] = {0xE65820F4U, 0x0000000CU}, /* RGIDR_MODID[227]:AXIPCI000*/ + [216] = {0xE65820F8U, 0x0000000CU}, /* RGIDR_MODID[228]:AXIPCI004*/ + [217] = {0xE65820FCU, 0x0000004EU}, /* RGIDR_MODID[229]:IPMMUHC01*/ + [218] = {0xE6582100U, 0x0000004EU}, /* RGIDR_MODID[230]:AVB0*/ + [219] = {0xE6582104U, 0x0000004EU}, /* RGIDR_MODID[231]:AVB1*/ + [220] = {0xE6582108U, 0x0000004EU}, /* RGIDR_MODID[232]:AVB2*/ + [221] = {0xE658210CU, 0x0000004EU}, /* RGIDR_MODID[233]:IPMMUHC10*/ + [222] = {0xE6582110U, 0x0000004EU}, /* RGIDR_MODID[234]:IPMMUHC11*/ + [223] = {0xE6582114U, 0x0000004EU}, /* RGIDR_MODID[235]:IPMMUHC12*/ + [224] = {0xE6582118U, 0x0000004EU}, /* RGIDR_MODID[236]:IPMMUHC13*/ + [225] = {0xE658211CU, 0x0000000CU}, /* RGIDR_MODID[237]:PPHY0*/ + [226] = {0xE6582120U, 0x0000000CU}, /* RGIDR_MODID[238]:PPHY1*/ + [227] = {0xE6582124U, 0x0000004EU}, /* RGIDR_MODID[239]:IPMMUHC14*/ + [228] = {0xE6582128U, 0x0000004EU}, /* RGIDR_MODID[240]:IPMMUHC15*/ + [229] = {0xE658212CU, 0x0000000EU}, /* RGIDR_MODID[241]:FBAHSC*/ + [230] = {0xE6582130U, 0x0000004EU}, /* RGIDR_MODID[242]:IPMMUHC02*/ + [231] = {0xE6582138U, 0x0000000FU}, /* RGIDR_MODID[243]:ECMHSC*/ + [232] = {0xE658213CU, 0x0000000FU}, /* RGIDR_MODID[244]:ARHC0*/ + /* After setting */ /* RGIDR_MODID[245]:ARHC1*/ + /* After setting */ /* RGIDR_MODID[246]:ARHC2*/ + [233] = {0xE6582148U, 0x0000000FU}, /* RGIDR_MODID[247]:ARHC3*/ + [234] = {0xE658214CU, 0x0000000FU}, /* RGIDR_MODID[248]:ARHC4*/ + [235] = {0xE6582150U, 0x0000000FU}, /* RGIDR_MODID[249]:ARHC5*/ + [236] = {0xE6582154U, 0x0000000FU}, /* RGIDR_MODID[250]:ARHC6*/ + [237] = {0xE6582158U, 0x0000000FU}, /* RGIDR_MODID[251]:ARHC7*/ + [238] = {0xE658215CU, 0x00000000U}, /* RGIDR_MODID[252]:ARHC8*/ + [239] = {0xE6582160U, 0x0000004EU}, /* RGIDR_MODID[253]:IPMMUHC03*/ + [240] = {0xE6582164U, 0x0000004EU}, /* RGIDR_MODID[254]:IPMMUHC04*/ + [241] = {0xE6582168U, 0x0000004EU}, /* RGIDR_MODID[255]:IPMMUHC05*/ + [242] = {0xE658216CU, 0x0000004EU}, /* RGIDR_MODID[256]:IPMMUHC06*/ + [243] = {0xE6582170U, 0x0000004EU}, /* RGIDR_MODID[257]:IPMMUHC07*/ + [244] = {0xE6582174U, 0x0000004EU}, /* RGIDR_MODID[258]:IPMMUHC08*/ + [245] = {0xE6582178U, 0x0000004EU}, /* RGIDR_MODID[259]:IPMMUHC09*/ + [246] = {0xFF882000U, 0x0000000FU}, /* RGIDR_MODID[260]:ARIMP00*/ + /* After setting */ /* RGIDR_MODID[261]:ARIMP01*/ + /* After setting */ /* RGIDR_MODID[262]:ARIMP02*/ + [247] = {0xFF88200CU, 0x0000000FU}, /* RGIDR_MODID[263]:ARIMP03*/ + [248] = {0xFF882010U, 0x0000000FU}, /* RGIDR_MODID[264]:ARIMP04*/ + [249] = {0xFF882014U, 0x0000004EU}, /* RGIDR_MODID[265]:AXIFBABUSIR0*/ + [250] = {0xFF882018U, 0x0000004EU}, /* RGIDR_MODID[266]:AXIFBABUSIR1*/ + [251] = {0xFF88201CU, 0x0000004EU}, /* RGIDR_MODID[267]:AXIFBABUSIR2*/ + [252] = {0xFF882020U, 0x0000004EU}, /* RGIDR_MODID[268]:AXIFBABUSIR3*/ + [253] = {0xFF882024U, 0x0000004EU}, /* RGIDR_MODID[269]:AXIFBABUSIR4*/ + [254] = {0xFF882028U, 0x0000004EU}, /* RGIDR_MODID[270]:AXIIMP0*/ + [255] = {0xFF88202CU, 0x0000004EU}, /* RGIDR_MODID[271]:CKMCNR*/ + [256] = {0xFF882030U, 0x0000004EU}, /* RGIDR_MODID[272]:CKMDSP*/ + [257] = {0xFF882034U, 0x0000000FU}, /* RGIDR_MODID[273]:ARIMP05*/ + [258] = {0xFF882038U, 0x0000000FU}, /* RGIDR_MODID[274]:ARIMP06*/ + [259] = {0xFF88203CU, 0x0000000FU}, /* RGIDR_MODID[275]:ARIMP07*/ + [260] = {0xFF882040U, 0x00000000U}, /* RGIDR_MODID[276]:ARIMP08*/ + [261] = {0xFF882044U, 0x0000004EU}, /* RGIDR_MODID[277]:CKMIR*/ + [262] = {0xFF882048U, 0x0000000FU}, /* RGIDR_MODID[278]:ECMIR*/ + [263] = {0xFF88204CU, 0x0000000FU}, /* RGIDR_MODID[279]:DSPPS*/ + [264] = {0xFF882050U, 0x0000004EU}, /* RGIDR_MODID[280]:IPMMUIR1*/ + [265] = {0xFF882054U, 0x0000004EU}, /* RGIDR_MODID[281]:IPMMUIR0*/ + [266] = {0xFF882058U, 0x0000004EU}, /* RGIDR_MODID[282]:IPMMUIR10*/ + [267] = {0xFF88205CU, 0x0000004EU}, /* RGIDR_MODID[283]:IPMMUIR11*/ + [268] = {0xFF882060U, 0x0000004EU}, /* RGIDR_MODID[284]:IPMMUIR12*/ + [269] = {0xFF882064U, 0x0000004EU}, /* RGIDR_MODID[285]:IPMMUIR13*/ + [270] = {0xFF882068U, 0x0000004EU}, /* RGIDR_MODID[286]:IPMMUIR14*/ + [271] = {0xFF88206CU, 0x0000004EU}, /* RGIDR_MODID[287]:IPMMUIR15*/ + [272] = {0xFF882070U, 0x0000004EU}, /* RGIDR_MODID[288]:IPMMUIR2*/ + [273] = {0xFF882074U, 0x0000004EU}, /* RGIDR_MODID[289]:IPMMUIR3*/ + [274] = {0xFF882078U, 0x0000004EU}, /* RGIDR_MODID[290]:IPMMUIR4*/ + [275] = {0xFF88207CU, 0x0000004EU}, /* RGIDR_MODID[291]:IPMMUIR5*/ + [276] = {0xFF882080U, 0x0000004EU}, /* RGIDR_MODID[292]:IPMMUIR6*/ + [277] = {0xFF882084U, 0x0000004EU}, /* RGIDR_MODID[293]:IPMMUIR7*/ + [278] = {0xFF882088U, 0x0000004EU}, /* RGIDR_MODID[294]:IPMMUIR8*/ + [279] = {0xFF88208CU, 0x0000004EU}, /* RGIDR_MODID[295]:IPMMUIR9*/ + [280] = {0xFD812000U, 0x0000000FU}, /* RGIDR_MODID[296]:ARPV0*/ + /* After setting */ /* RGIDR_MODID[297]:ARPV1*/ + [281] = {0xFD812008U, 0x0000002CU}, /* RGIDR_MODID[298]:AXIRGXS*/ + /* After setting */ /* RGIDR_MODID[299]:ARPV2*/ + [282] = {0xFD812010U, 0x0000000FU}, /* RGIDR_MODID[300]:ARPV3*/ + [283] = {0xFD812014U, 0x0000000FU}, /* RGIDR_MODID[301]:ARPV4*/ + [284] = {0xFD812018U, 0x0000000FU}, /* RGIDR_MODID[302]:ARPV5*/ + [285] = {0xFD81201CU, 0x0000000FU}, /* RGIDR_MODID[303]:ARPV6*/ + [286] = {0xFD812020U, 0x0000000FU}, /* RGIDR_MODID[304]:ARPV7*/ + [287] = {0xFD812024U, 0x00000000U}, /* RGIDR_MODID[305]:ARPV8*/ + [288] = {0xFD812028U, 0x0000000AU}, /* RGIDR_MODID[306]:CKM3DG*/ + [289] = {0xFD81202CU, 0x0000000FU}, /* RGIDR_MODID[307]:ECM3DG*/ + [290] = {0xFD812030U, 0x0000000EU}, /* RGIDR_MODID[308]:FBAPVC*/ + [291] = {0xFD812034U, 0x0000000EU}, /* RGIDR_MODID[309]:FBAPVD0*/ + [292] = {0xFD812038U, 0x0000000EU}, /* RGIDR_MODID[310]:FBAPVD1*/ + [293] = {0xFD81203CU, 0x0000000EU}, /* RGIDR_MODID[311]:FBAPVD2*/ + [294] = {0xFD812040U, 0x0000000EU}, /* RGIDR_MODID[312]:FBAPVE*/ + [295] = {0xFD812044U, 0x0000004EU}, /* RGIDR_MODID[313]:IPMMUPV000*/ + [296] = {0xFD812048U, 0x0000004EU}, /* RGIDR_MODID[314]:IPMMUPV001*/ + [297] = {0xFD81204CU, 0x0000004EU}, /* RGIDR_MODID[315]:IPMMUPV010*/ + [298] = {0xFD812050U, 0x0000004EU}, /* RGIDR_MODID[316]:IPMMUPV011*/ + [299] = {0xFD812054U, 0x0000004EU}, /* RGIDR_MODID[317]:IPMMUPV012*/ + [300] = {0xFD812058U, 0x0000004EU}, /* RGIDR_MODID[318]:IPMMUPV013*/ + [301] = {0xFD81205CU, 0x0000004EU}, /* RGIDR_MODID[319]:IPMMUPV014*/ + [302] = {0xFD812060U, 0x0000004EU}, /* RGIDR_MODID[320]:IPMMUPV015*/ + [303] = {0xFD812064U, 0x0000004EU}, /* RGIDR_MODID[321]:IPMMUPV002*/ + [304] = {0xFD812068U, 0x0000004EU}, /* RGIDR_MODID[322]:IPMMUPV003*/ + [305] = {0xFD81206CU, 0x0000004EU}, /* RGIDR_MODID[323]:IPMMUPV004*/ + [306] = {0xFD812070U, 0x0000004EU}, /* RGIDR_MODID[324]:IPMMUPV005*/ + [307] = {0xFD812074U, 0x0000004EU}, /* RGIDR_MODID[325]:IPMMUPV006*/ + [308] = {0xFD812078U, 0x0000004EU}, /* RGIDR_MODID[326]:IPMMUPV007*/ + [309] = {0xFD81207CU, 0x0000004EU}, /* RGIDR_MODID[327]:IPMMUPV008*/ + [310] = {0xFD812080U, 0x0000004EU}, /* RGIDR_MODID[328]:IPMMUPV009*/ + [311] = {0xE6622000U, 0x0000000FU}, /* RGIDR_MODID[329]:ARRC0*/ + /* After setting */ /* RGIDR_MODID[330]:ARRC1*/ + /* After setting */ /* RGIDR_MODID[331]:ARRC2*/ + [312] = {0xE662200CU, 0x0000000FU}, /* RGIDR_MODID[332]:ARRC3*/ + [313] = {0xE6622010U, 0x0000000FU}, /* RGIDR_MODID[333]:ARRC4*/ + [314] = {0xE6622014U, 0x0000000FU}, /* RGIDR_MODID[334]:ARRC5*/ + [315] = {0xE6622018U, 0x0000000FU}, /* RGIDR_MODID[335]:ARRC6*/ + [316] = {0xE662201CU, 0x0000000FU}, /* RGIDR_MODID[336]:ARRC7*/ + [317] = {0xE6622020U, 0x00000000U}, /* RGIDR_MODID[337]:ARRC8*/ + [318] = {0xE6622024U, 0x00000009U}, /* RGIDR_MODID[338]:CR0*/ + [319] = {0xE6622028U, 0x0000004FU}, /* RGIDR_MODID[339]:ICUMX*/ + [320] = {0xE662202CU, 0x0000000FU}, /* RGIDR_MODID[340]:ECMRC*/ + [321] = {0xFFC32000U, 0x0000004EU}, /* RGIDR_MODID[341]:DMAWCRC0*/ + [322] = {0xFFC32004U, 0x0000004EU}, /* RGIDR_MODID[342]:DMAWCRC1*/ + [323] = {0xFFC32008U, 0x0000004EU}, /* RGIDR_MODID[343]:DMAWCRC2*/ + [324] = {0xFFC3200CU, 0x0000004EU}, /* RGIDR_MODID[344]:DMAWCRC3*/ + [325] = {0xFFC42000U, 0x0000000FU}, /* RGIDR_MODID[345]:ARMREG00*/ + [326] = {0xFFC42004U, 0x0000000DU}, /* RGIDR_MODID[346]:ARMREG01*/ + [327] = {0xFFC42008U, 0x00000000U}, /* RGIDR_MODID[347]:ARMREG10*/ + [328] = {0xFFC4200CU, 0x00000000U}, /* RGIDR_MODID[348]:ARMREG11*/ + [329] = {0xFFC42010U, 0x0000000BU}, /* RGIDR_MODID[349]:ARMREG12*/ + [330] = {0xFFC42014U, 0x0000000FU}, /* RGIDR_MODID[350]:ARMREG13*/ + [331] = {0xFFC42018U, 0x0000000BU}, /* RGIDR_MODID[351]:ARMREG14*/ + [332] = {0xFFC4201CU, 0x00000002U}, /* RGIDR_MODID[352]:AXICR52SS0*/ + [333] = {0xFFC42020U, 0x0000000EU}, /* RGIDR_MODID[353]:AXICSD0*/ + [334] = {0xFFC42024U, 0x0000000EU}, /* RGIDR_MODID[354]:AXIINTAP0*/ + [335] = {0xFFC42028U, 0x00000000U}, /* RGIDR_MODID[355]:AXIINTAP1*/ + [336] = {0xFFC4202CU, 0x00000009U}, /* RGIDR_MODID[356]:AXISECROM*/ + [337] = {0xFFC42030U, 0x0000000FU}, /* RGIDR_MODID[357]:AXISYSRAM0*/ + [338] = {0xFFC42034U, 0x0000004FU}, /* RGIDR_MODID[358]:AXISYSRAM1*/ + [339] = {0xFFC42038U, 0x00000000U}, /* RGIDR_MODID[359]:ARGREG15*/ + [340] = {0xFFC4203CU, 0x00000000U}, /* RGIDR_MODID[360]:ARMREG2*/ + [341] = {0xFFC42040U, 0x00000000U}, /* RGIDR_MODID[361]:ARMREG3*/ + [342] = {0xFFC42044U, 0x00000000U}, /* RGIDR_MODID[362]:ARMREG4*/ + [343] = {0xFFC42048U, 0x0000000FU}, /* RGIDR_MODID[363]:ARMREG5*/ + [344] = {0xFFC4204CU, 0x0000000FU}, /* RGIDR_MODID[364]:ARMREG6*/ + [345] = {0xFFC42050U, 0x00000000U}, /* RGIDR_MODID[365]:ARMREG7*/ + [346] = {0xFFC42054U, 0x0000000DU}, /* RGIDR_MODID[366]:ARMREG8*/ + [347] = {0xFFC42058U, 0x0000000DU}, /* RGIDR_MODID[367]:ARMREG9*/ + [348] = {0xFFC4205CU, 0x0000000FU}, /* RGIDR_MODID[368]:ARRD0*/ + /* After setting */ /* RGIDR_MODID[369]:ARRD1*/ + /* After setting */ /* RGIDR_MODID[370]:ARRD2*/ + [349] = {0xFFC42068U, 0x0000000FU}, /* RGIDR_MODID[371]:ARRD3*/ + [350] = {0xFFC4206CU, 0x0000000FU}, /* RGIDR_MODID[372]:ARRD4*/ + [351] = {0xFFC42070U, 0x0000000FU}, /* RGIDR_MODID[373]:ARRD5*/ + [352] = {0xFFC42074U, 0x0000000FU}, /* RGIDR_MODID[374]:ARRD6*/ + [353] = {0xFFC42078U, 0x0000000FU}, /* RGIDR_MODID[375]:ARRD7*/ + [354] = {0xFFC4207CU, 0x00000000U}, /* RGIDR_MODID[376]:ARRD8*/ + [355] = {0xFFC42080U, 0x0000000FU}, /* RGIDR_MODID[377]:ARRT0*/ + /* After setting */ /* RGIDR_MODID[378]:ARRT1*/ + /* After setting */ /* RGIDR_MODID[379]:ARRT2*/ + [356] = {0xFFC4208CU, 0x0000000FU}, /* RGIDR_MODID[380]:ARRT3*/ + [357] = {0xFFC42090U, 0x0000000FU}, /* RGIDR_MODID[381]:ARRT4*/ + [358] = {0xFFC42094U, 0x0000000FU}, /* RGIDR_MODID[382]:ARRT5*/ + [359] = {0xFFC42098U, 0x0000000FU}, /* RGIDR_MODID[383]:ARRT6*/ + [360] = {0xFFC4209CU, 0x0000000FU}, /* RGIDR_MODID[384]:ARRT7*/ + [361] = {0xFFC420A0U, 0x00000000U}, /* RGIDR_MODID[385]:ARRT8*/ + [362] = {0xFFC420A4U, 0x0000000AU}, /* RGIDR_MODID[386]:CKMRT*/ + [363] = {0xFFC420A8U, 0x0000004EU}, /* RGIDR_MODID[387]:CRC0*/ + [364] = {0xFFC420ACU, 0x0000004EU}, /* RGIDR_MODID[388]:CRC1*/ + [365] = {0xFFC420B0U, 0x0000004EU}, /* RGIDR_MODID[389]:CRC2*/ + [366] = {0xFFC420B4U, 0x0000004EU}, /* RGIDR_MODID[390]:CRC3*/ + [367] = {0xFFC420B8U, 0x0000000EU}, /* RGIDR_MODID[391]:CSD*/ + [368] = {0xFFC420BCU, 0x0000000FU}, /* RGIDR_MODID[392]:ECM*/ + [369] = {0xFFC420C0U, 0x0000000FU}, /* RGIDR_MODID[393]:ECMRT*/ + [370] = {0xFFC420C4U, 0x0000000EU}, /* RGIDR_MODID[394]:FBACR52*/ + [371] = {0xFFC420C8U, 0x0000000EU}, /* RGIDR_MODID[395]:FBART*/ + [372] = {0xFFC420CCU, 0x0000000EU}, /* RGIDR_MODID[396]:INTTP*/ + [373] = {0xFFC420D0U, 0x0000004EU}, /* RGIDR_MODID[397]:IPMMURT000*/ + [374] = {0xFFC420D4U, 0x0000004EU}, /* RGIDR_MODID[398]:IPMMURT100*/ + [375] = {0xFFC420D8U, 0x0000004EU}, /* RGIDR_MODID[399]:KCRC4*/ + [376] = {0xFFC420DCU, 0x0000004EU}, /* RGIDR_MODID[400]:KCRC5*/ + [377] = {0xFFC420E0U, 0x0000004EU}, /* RGIDR_MODID[401]:KCRC6*/ + [378] = {0xFFC420E4U, 0x0000004EU}, /* RGIDR_MODID[402]:KCRC7*/ + [379] = {0xFFC420E8U, 0x0000004FU}, /* RGIDR_MODID[403]:MFI00*/ + [380] = {0xFFC420ECU, 0x0000004EU}, /* RGIDR_MODID[404]:MFI01*/ + [381] = {0xFFC420F0U, 0x0000004EU}, /* RGIDR_MODID[405]:MFI10*/ + [382] = {0xFFC420F4U, 0x0000004EU}, /* RGIDR_MODID[406]:MFI02*/ + [383] = {0xFFC420F8U, 0x0000004EU}, /* RGIDR_MODID[407]:MFI03*/ + [384] = {0xFFC420FCU, 0x0000004EU}, /* RGIDR_MODID[408]:MFI04*/ + [385] = {0xFFC42100U, 0x00000000U}, /* RGIDR_MODID[409]:MFI05*/ + [386] = {0xFFC42104U, 0x00000000U}, /* RGIDR_MODID[410]:MFI06*/ + [387] = {0xFFC42108U, 0x00000000U}, /* RGIDR_MODID[411]:MFI07*/ + [388] = {0xFFC4210CU, 0x00000000U}, /* RGIDR_MODID[412]:MFI08*/ + [389] = {0xFFC42110U, 0x0000004EU}, /* RGIDR_MODID[413]:MFI09*/ + [390] = {0xFFC42114U, 0x0000004FU}, /* RGIDR_MODID[414]:MFI15*/ + [391] = {0xFFC42118U, 0x0000000AU}, /* RGIDR_MODID[415]:CKMCR52*/ + [392] = {0xFFC4211CU, 0x0000004BU}, /* RGIDR_MODID[416]:RTDM0P*/ + [393] = {0xFFC42120U, 0x0000000FU}, /* RGIDR_MODID[417]:ECMRD*/ + [394] = {0xFFC42124U, 0x0000004BU}, /* RGIDR_MODID[418]:RTDM1P*/ + [395] = {0xFFC4212CU, 0x0000004BU}, /* RGIDR_MODID[419]:RTDM2P*/ + [396] = {0xFFC42130U, 0x0000000BU}, /* RGIDR_MODID[420]:SYSRAM10*/ + [397] = {0xFFC42134U, 0x0000004BU}, /* RGIDR_MODID[421]:RTDM3P*/ + [398] = {0xFFC42138U, 0x00000003U}, /* RGIDR_MODID[422]:SYSRAM00*/ + [399] = {0xFFC4213CU, 0x0000004EU}, /* RGIDR_MODID[423]:TSIPL0*/ + [400] = {0xFFC42140U, 0x0000004EU}, /* RGIDR_MODID[424]:TSIPL1*/ + [401] = {0xFFC42144U, 0x0000004EU}, /* RGIDR_MODID[425]:TSIPL2*/ + [402] = {0xFFC42148U, 0x0000004EU}, /* RGIDR_MODID[426]:TSIPL3*/ + [403] = {0xFFC4214CU, 0x0000004EU}, /* RGIDR_MODID[427]:TSIPL4*/ + [404] = {0xFFC42150U, 0x0000004EU}, /* RGIDR_MODID[428]:TSIPL5*/ + [405] = {0xFFC42154U, 0x0000004EU}, /* RGIDR_MODID[429]:TSIPL6*/ + [406] = {0xFFC42158U, 0x0000004EU}, /* RGIDR_MODID[430]:TSIPL7*/ + [407] = {0xFFC4215CU, 0x0000004EU}, /* RGIDR_MODID[431]:WCRC0*/ + [408] = {0xFFC42160U, 0x0000004EU}, /* RGIDR_MODID[432]:WCRC1*/ + [409] = {0xFFC42164U, 0x0000004EU}, /* RGIDR_MODID[433]:WCRC2*/ + [410] = {0xFFC42168U, 0x0000004EU}, /* RGIDR_MODID[434]:WCRC3*/ + [411] = {0xFFC42180U, 0x0000004EU}, /* RGIDR_MODID[435]:MFI11*/ + [412] = {0xFFC42184U, 0x00000000U}, /* RGIDR_MODID[436]:MFI12*/ + [413] = {0xFFC42188U, 0x00000000U}, /* RGIDR_MODID[437]:MFI13*/ + [414] = {0xFFC4218CU, 0x00000000U}, /* RGIDR_MODID[438]:MFI14*/ + [415] = {0xFFC42190U, 0x0000004EU}, /* RGIDR_MODID[439]:IPMMURT001*/ + [416] = {0xFFC42194U, 0x0000004EU}, /* RGIDR_MODID[440]:IPMMURT010*/ + [417] = {0xFFC42198U, 0x0000004EU}, /* RGIDR_MODID[441]:IPMMURT011*/ + [418] = {0xFFC4219CU, 0x0000004EU}, /* RGIDR_MODID[442]:IPMMURT012*/ + [419] = {0xFFC421A0U, 0x0000004EU}, /* RGIDR_MODID[443]:IPMMURT013*/ + [420] = {0xFFC421A4U, 0x0000004EU}, /* RGIDR_MODID[444]:IPMMURT014*/ + [421] = {0xFFC421A8U, 0x0000004EU}, /* RGIDR_MODID[445]:IPMMURT015*/ + [422] = {0xFFC421ACU, 0x0000004EU}, /* RGIDR_MODID[446]:IPMMURT002*/ + [423] = {0xFFC421B0U, 0x0000004EU}, /* RGIDR_MODID[447]:IPMMURT003*/ + [424] = {0xFFC421B4U, 0x0000004EU}, /* RGIDR_MODID[448]:IPMMURT004*/ + [425] = {0xFFC421B8U, 0x0000004EU}, /* RGIDR_MODID[449]:IPMMURT005*/ + [426] = {0xFFC421BCU, 0x0000004EU}, /* RGIDR_MODID[450]:IPMMURT006*/ + [427] = {0xFFC421C0U, 0x0000004EU}, /* RGIDR_MODID[451]:IPMMURT007*/ + [428] = {0xFFC421C4U, 0x0000004EU}, /* RGIDR_MODID[452]:IPMMURT008*/ + [429] = {0xFFC421C8U, 0x0000004EU}, /* RGIDR_MODID[453]:IPMMURT009*/ + [430] = {0xFFC421CCU, 0x0000004EU}, /* RGIDR_MODID[454]:IPKMURT101*/ + [431] = {0xFFC421D0U, 0x0000004EU}, /* RGIDR_MODID[455]:IPMMURT110*/ + [432] = {0xFFC421D4U, 0x0000004EU}, /* RGIDR_MODID[456]:IPMMURT111*/ + [433] = {0xFFC421D8U, 0x0000004EU}, /* RGIDR_MODID[457]:IPMMURT112*/ + [434] = {0xFFC421DCU, 0x0000004EU}, /* RGIDR_MODID[458]:IPMMURT113*/ + [435] = {0xFFC421E0U, 0x0000004EU}, /* RGIDR_MODID[459]:IPMMURT114*/ + [436] = {0xFFC421E4U, 0x0000004EU}, /* RGIDR_MODID[460]:IPMMURT115*/ + [437] = {0xFFC421E8U, 0x0000004EU}, /* RGIDR_MODID[461]:IPMMURT102*/ + [438] = {0xFFC421ECU, 0x0000004EU}, /* RGIDR_MODID[462]:IPMMURT103*/ + [439] = {0xFFC421F0U, 0x0000004EU}, /* RGIDR_MODID[463]:IPMMURT104*/ + [440] = {0xFFC421F4U, 0x0000004EU}, /* RGIDR_MODID[464]:IPMMURT105*/ + [441] = {0xFFC421F8U, 0x0000004EU}, /* RGIDR_MODID[465]:IPMMURT106*/ + [442] = {0xFFC421FCU, 0x0000004EU}, /* RGIDR_MODID[466]:IPMMURT107*/ + [443] = {0xFFC42200U, 0x0000004BU}, /* RGIDR_MODID[467]:RTDM000*/ + [444] = {0xFFC42204U, 0x0000004BU}, /* RGIDR_MODID[468]:RTDM001*/ + [445] = {0xFFC42208U, 0x0000004BU}, /* RGIDR_MODID[469]:RTDM010*/ + [446] = {0xFFC4220CU, 0x0000004BU}, /* RGIDR_MODID[470]:RTDM011*/ + [447] = {0xFFC42210U, 0x0000004BU}, /* RGIDR_MODID[471]:RTDM012*/ + [448] = {0xFFC42214U, 0x0000004BU}, /* RGIDR_MODID[472]:RTDM013*/ + [449] = {0xFFC42218U, 0x0000004BU}, /* RGIDR_MODID[473]:RTDM014*/ + [450] = {0xFFC4221CU, 0x0000004BU}, /* RGIDR_MODID[474]:RTDM015*/ + [451] = {0xFFC42220U, 0x0000004BU}, /* RGIDR_MODID[475]:RTDM002*/ + [452] = {0xFFC42224U, 0x0000004BU}, /* RGIDR_MODID[476]:RTDM003*/ + [453] = {0xFFC42228U, 0x0000004BU}, /* RGIDR_MODID[477]:RTDM004*/ + [454] = {0xFFC4222CU, 0x0000004BU}, /* RGIDR_MODID[478]:RTDM005*/ + [455] = {0xFFC42230U, 0x0000004BU}, /* RGIDR_MODID[479]:RTDM006*/ + [456] = {0xFFC42234U, 0x0000004BU}, /* RGIDR_MODID[480]:RTDM007*/ + [457] = {0xFFC42238U, 0x0000004BU}, /* RGIDR_MODID[481]:RTDM008*/ + [458] = {0xFFC4223CU, 0x0000004BU}, /* RGIDR_MODID[482]:RTDM009*/ + [459] = {0xFFC42240U, 0x0000004BU}, /* RGIDR_MODID[483]:RTDM100*/ + [460] = {0xFFC42244U, 0x0000004BU}, /* RGIDR_MODID[484]:RTDM101*/ + [461] = {0xFFC42248U, 0x0000004BU}, /* RGIDR_MODID[485]:RTDM110*/ + [462] = {0xFFC4224CU, 0x0000004BU}, /* RGIDR_MODID[486]:RTDM111*/ + [463] = {0xFFC42250U, 0x0000004BU}, /* RGIDR_MODID[487]:RTDM112*/ + [464] = {0xFFC42254U, 0x0000004BU}, /* RGIDR_MODID[488]:RTDM113*/ + [465] = {0xFFC42258U, 0x0000004BU}, /* RGIDR_MODID[489]:RTDM114*/ + [466] = {0xFFC4225CU, 0x0000004BU}, /* RGIDR_MODID[490]:RTDM115*/ + [467] = {0xFFC42260U, 0x0000004BU}, /* RGIDR_MODID[491]:RTDM102*/ + [468] = {0xFFC42264U, 0x0000004BU}, /* RGIDR_MODID[492]:RTDM103*/ + [469] = {0xFFC42268U, 0x0000004BU}, /* RGIDR_MODID[493]:RTDM104*/ + [470] = {0xFFC4226CU, 0x0000004BU}, /* RGIDR_MODID[494]:RTDM105*/ + [471] = {0xFFC42270U, 0x0000004BU}, /* RGIDR_MODID[495]:RTDM106*/ + [472] = {0xFFC42274U, 0x0000004BU}, /* RGIDR_MODID[496]:RTDM107*/ + [473] = {0xFFC42278U, 0x0000004BU}, /* RGIDR_MODID[497]:RTDM108*/ + [474] = {0xFFC4227CU, 0x0000004BU}, /* RGIDR_MODID[498]:RTDM109*/ + [475] = {0xFFC42280U, 0x0000004BU}, /* RGIDR_MODID[499]:RTDM200*/ + [476] = {0xFFC42284U, 0x0000004BU}, /* RGIDR_MODID[500]:RTDM201*/ + [477] = {0xFFC42288U, 0x0000004BU}, /* RGIDR_MODID[501]:RTDM210*/ + [478] = {0xFFC4228CU, 0x0000004BU}, /* RGIDR_MODID[502]:RTDM211*/ + [479] = {0xFFC42290U, 0x0000004BU}, /* RGIDR_MODID[503]:RTDM212*/ + [480] = {0xFFC42294U, 0x0000004BU}, /* RGIDR_MODID[504]:RTDM213*/ + [481] = {0xFFC42298U, 0x0000004BU}, /* RGIDR_MODID[505]:RTDM214*/ + [482] = {0xFFC4229CU, 0x0000004BU}, /* RGIDR_MODID[506]:RTDM215*/ + [483] = {0xFFC422A0U, 0x0000004BU}, /* RGIDR_MODID[507]:RTDM202*/ + [484] = {0xFFC422A4U, 0x0000004BU}, /* RGIDR_MODID[508]:RTDM203*/ + [485] = {0xFFC422A8U, 0x0000004BU}, /* RGIDR_MODID[509]:RTDM204*/ + [486] = {0xFFC422ACU, 0x0000004BU}, /* RGIDR_MODID[510]:RTDM205*/ + [487] = {0xFFC422B0U, 0x0000004BU}, /* RGIDR_MODID[511]:RTDM206*/ + [488] = {0xFFC422B4U, 0x0000004BU}, /* RGIDR_MODID[512]:RTDM207*/ + [489] = {0xFFC422B8U, 0x0000004BU}, /* RGIDR_MODID[513]:RTDM208*/ + [490] = {0xFFC422BCU, 0x0000004BU}, /* RGIDR_MODID[514]:RTDM209*/ + [491] = {0xFFC422C0U, 0x0000004BU}, /* RGIDR_MODID[515]:RTDM300*/ + [492] = {0xFFC422C4U, 0x0000004BU}, /* RGIDR_MODID[516]:RTDM301*/ + [493] = {0xFFC422C8U, 0x0000004BU}, /* RGIDR_MODID[517]:RTDM310*/ + [494] = {0xFFC422CCU, 0x0000004BU}, /* RGIDR_MODID[518]:RTDM311*/ + [495] = {0xFFC422D0U, 0x0000004BU}, /* RGIDR_MODID[519]:RTDM312*/ + [496] = {0xFFC422D4U, 0x0000004BU}, /* RGIDR_MODID[520]:RTDM313*/ + [497] = {0xFFC422D8U, 0x0000004BU}, /* RGIDR_MODID[521]:RTDM314*/ + [498] = {0xFFC422DCU, 0x0000004BU}, /* RGIDR_MODID[522]:RTDM315*/ + [499] = {0xFFC422E0U, 0x0000004BU}, /* RGIDR_MODID[523]:RTDM302*/ + [500] = {0xFFC422E4U, 0x0000004BU}, /* RGIDR_MODID[524]:RTDM303*/ + [501] = {0xFFC422E8U, 0x0000004BU}, /* RGIDR_MODID[525]:RTDM304*/ + [502] = {0xFFC422ECU, 0x0000004BU}, /* RGIDR_MODID[526]:RTDM305*/ + [503] = {0xFFC422F0U, 0x0000004BU}, /* RGIDR_MODID[527]:RTDM306*/ + [504] = {0xFFC422F4U, 0x0000004BU}, /* RGIDR_MODID[528]:RTDM307*/ + [505] = {0xFFC422F8U, 0x0000004BU}, /* RGIDR_MODID[529]:RTDM308*/ + [506] = {0xFFC422FCU, 0x0000004BU}, /* RGIDR_MODID[530]:RTDM309*/ + [507] = {0xFFC42300U, 0x0000004EU}, /* RGIDR_MODID[531]:IPMMURT108*/ + [508] = {0xFFC42304U, 0x0000004EU}, /* RGIDR_MODID[532]:IPMMURT109*/ + [509] = {0xFFC42308U, 0x00000001U}, /* RGIDR_MODID[533]:SYSRAM01*/ + [510] = {0xFFC4230CU, 0x0000000BU}, /* RGIDR_MODID[534]:SYSRAM02*/ + [511] = {0xFFC42310U, 0x00000001U}, /* RGIDR_MODID[535]:SYSRAM03*/ + [512] = {0xFFC42314U, 0x00000001U}, /* RGIDR_MODID[536]:SYSRAM04*/ + [513] = {0xFFC42318U, 0x00000001U}, /* RGIDR_MODID[537]:SYSRAM05*/ + [514] = {0xFFC4231CU, 0x00000001U}, /* RGIDR_MODID[538]:SYSRAM06*/ + [515] = {0xFFC42320U, 0x00000000U}, /* RGIDR_MODID[539]:SYSRAM07*/ + [516] = {0xFFC42324U, 0x0000000BU}, /* RGIDR_MODID[540]:SYSRAM11*/ + [517] = {0xFFC42328U, 0x0000000BU}, /* RGIDR_MODID[541]:SYSRAM12*/ + [518] = {0xFFC4232CU, 0x0000000BU}, /* RGIDR_MODID[542]:SYSRAM13*/ + [519] = {0xFFC42330U, 0x0000000BU}, /* RGIDR_MODID[543]:SYSRAM14*/ + [520] = {0xFFC42334U, 0x0000000BU}, /* RGIDR_MODID[544]:SYSRAM15*/ + [521] = {0xFFC42338U, 0x0000000BU}, /* RGIDR_MODID[545]:SYSRAM16*/ + [522] = {0xFFC4233CU, 0x00000000U}, /* RGIDR_MODID[546]:SYSRAM17*/ + [523] = {0xFFC42360U, 0x00000002U}, /* RGIDR_MODID[547]:BKBUF*/ + [524] = {0xFFC42364U, 0x00000002U}, /* RGIDR_MODID[548]:AXICR52SS1*/ + [525] = {0xFFC42368U, 0x00000002U}, /* RGIDR_MODID[549]:AXICR52SS2*/ + [526] = {0xFF862000U, 0x0000000FU}, /* RGIDR_MODID[550]:ARSC0*/ + /* After setting */ /* RGIDR_MODID[551]:ARSC1*/ + /* After setting */ /* RGIDR_MODID[552]:ARSC2*/ + [527] = {0xFF86200CU, 0x0000000FU}, /* RGIDR_MODID[553]:ARSC3*/ + [528] = {0xFF862010U, 0x0000000FU}, /* RGIDR_MODID[554]:ARSC4*/ + [529] = {0xFF862014U, 0x0000000FU}, /* RGIDR_MODID[555]:ARSC5*/ + [530] = {0xFF862018U, 0x0000000FU}, /* RGIDR_MODID[556]:ARSC6*/ + [531] = {0xFF86201CU, 0x0000000FU}, /* RGIDR_MODID[557]:ARSC7*/ + [532] = {0xFF862020U, 0x00000000U}, /* RGIDR_MODID[558]:ARSC8*/ + [533] = {0xFF862024U, 0x0000000FU}, /* RGIDR_MODID[559]:ARSTM0*/ + /* After setting */ /* RGIDR_MODID[560]:ARSTM1*/ + [534] = {0xFF86202CU, 0x0000000EU}, /* RGIDR_MODID[561]:CSD1S*/ + [535] = {0xFF862030U, 0x0000000EU}, /* RGIDR_MODID[562]:AXIFBABUSTOP0*/ + [536] = {0xFF862034U, 0x0000000EU}, /* RGIDR_MODID[563]:AXIFBABUSTOP1*/ + /* After setting */ /* RGIDR_MODID[564]:ARSTM2*/ + [537] = {0xFF86203CU, 0x0000000FU}, /* RGIDR_MODID[565]:ARSTM3*/ + [538] = {0xFF862040U, 0x0000000FU}, /* RGIDR_MODID[566]:ARSTM4*/ + [539] = {0xFF862044U, 0x0000000FU}, /* RGIDR_MODID[567]:ARSTM5*/ + [540] = {0xFF862048U, 0x0000000FU}, /* RGIDR_MODID[568]:ARSTM6*/ + [541] = {0xFF86204CU, 0x0000000FU}, /* RGIDR_MODID[569]:ARSTM7*/ + [542] = {0xFF862050U, 0x00000000U}, /* RGIDR_MODID[570]:ARSTM8*/ + [543] = {0xFF862054U, 0x0000000FU}, /* RGIDR_MODID[571]:ECMTOP*/ + [544] = {0xFF862058U, 0x0000000EU}, /* RGIDR_MODID[572]:FBA*/ + [545] = {0xFF86205CU, 0x0000000EU}, /* RGIDR_MODID[573]:FBC*/ + [546] = {0xFF862060U, 0x0000000CU}, /* RGIDR_MODID[574]:AXICCI00*/ + [547] = {0xFF862064U, 0x0000000CU}, /* RGIDR_MODID[575]:AXICCI01*/ + [548] = {0xFF862068U, 0x0000000CU}, /* RGIDR_MODID[576]:AXICCI10*/ + [549] = {0xFF86206CU, 0x0000000CU}, /* RGIDR_MODID[577]:AXICCI11*/ + [550] = {0xFF862070U, 0x0000000CU}, /* RGIDR_MODID[578]:AXICCI12*/ + [551] = {0xFF862074U, 0x0000000CU}, /* RGIDR_MODID[579]:AXICCI13*/ + [552] = {0xFF862078U, 0x0000000CU}, /* RGIDR_MODID[580]:AXICCI14*/ + [553] = {0xFF86207CU, 0x0000000CU}, /* RGIDR_MODID[581]:AXICCI15*/ + [554] = {0xFF862080U, 0x0000000CU}, /* RGIDR_MODID[582]:AXICCI2*/ + [555] = {0xFF862084U, 0x0000000CU}, /* RGIDR_MODID[583]:AXICCI3*/ + [556] = {0xFF862088U, 0x0000000CU}, /* RGIDR_MODID[584]:AXICCI4*/ + [557] = {0xFF86208CU, 0x0000000CU}, /* RGIDR_MODID[585]:AXICCI5*/ + [558] = {0xFF862090U, 0x0000000CU}, /* RGIDR_MODID[586]:AXICCI6*/ + [559] = {0xFF862094U, 0x0000000CU}, /* RGIDR_MODID[587]:AXICCI7*/ + [560] = {0xFF862098U, 0x0000000CU}, /* RGIDR_MODID[588]:AXICCI8*/ + [561] = {0xFF86209CU, 0x0000000FU}, /* RGIDR_MODID[589]:AXICCI9*/ + [562] = {0xFF8620A0U, 0x0000000FU}, /* RGIDR_MODID[590]:ECMSTM*/ + [563] = {0xE7782000U, 0x0000002CU}, /* RGIDR_MODID[591]:DMASSI00*/ + [564] = {0xE7782004U, 0x0000002CU}, /* RGIDR_MODID[592]:DMASSI01*/ + [565] = {0xE7782008U, 0x0000002CU}, /* RGIDR_MODID[593]:DMASSI02*/ + [566] = {0xE778200CU, 0x0000002CU}, /* RGIDR_MODID[594]:DMASSI03*/ + [567] = {0xE7782010U, 0x0000002CU}, /* RGIDR_MODID[595]:DMASSI04*/ + [568] = {0xE7782014U, 0x0000004EU}, /* RGIDR_MODID[596]:DMAI2C0*/ + [569] = {0xE7782018U, 0x0000004EU}, /* RGIDR_MODID[597]:DMAI2C1*/ + [570] = {0xE778201CU, 0x0000004EU}, /* RGIDR_MODID[598]:DMAI2C2*/ + [571] = {0xE7782020U, 0x0000004EU}, /* RGIDR_MODID[599]:DMAI2C3*/ + [572] = {0xE7782024U, 0x0000004EU}, /* RGIDR_MODID[600]:DMAI2C4*/ + [573] = {0xE7782028U, 0x0000004EU}, /* RGIDR_MODID[601]:DMAI2C5*/ + [574] = {0xE778202CU, 0x0000002CU}, /* RGIDR_MODID[602]:DMASSI05*/ + [575] = {0xE7782030U, 0x0000002CU}, /* RGIDR_MODID[603]:DMASSI06*/ + [576] = {0xE7782034U, 0x0000002CU}, /* RGIDR_MODID[604]:DMASSI07*/ + [577] = {0xE67C2000U, 0x00000007U}, /* RGIDR_MODID[605]:ARMM*/ + /* After setting */ /* RGIDR_MODID[606]:AXIARNMM*/ + [578] = {0xE67C2008U, 0x0000000FU}, /* RGIDR_MODID[607]:ARSM0*/ + /* After setting */ /* RGIDR_MODID[608]:ARSM1*/ + /* After setting */ /* RGIDR_MODID[609]:ARSM2*/ + [579] = {0xE67C2014U, 0x0000000FU}, /* RGIDR_MODID[610]:AXIQOS0*/ + [580] = {0xE67C2018U, 0x0000000FU}, /* RGIDR_MODID[611]:AXIQOS1*/ + [581] = {0xE67C201CU, 0x0000000FU}, /* RGIDR_MODID[612]:AXIQOS2*/ + [582] = {0xE67C2020U, 0x0000000FU}, /* RGIDR_MODID[613]:AXIQOS3*/ + [583] = {0xE67C2024U, 0x0000000FU}, /* RGIDR_MODID[614]:AXIQOS4*/ + [584] = {0xE67C2028U, 0x0000000FU}, /* RGIDR_MODID[615]:AXIQOS5*/ + [585] = {0xE67C202CU, 0x0000000FU}, /* RGIDR_MODID[616]:AXIQOS6*/ + [586] = {0xE67C2030U, 0x0000000FU}, /* RGIDR_MODID[617]:AXIQOS7*/ + [587] = {0xE67C2034U, 0x0000000FU}, /* RGIDR_MODID[618]:ARSM3*/ + [588] = {0xE67C2038U, 0x0000000FU}, /* RGIDR_MODID[619]:ARSM4*/ + [589] = {0xE67C203CU, 0x0000000FU}, /* RGIDR_MODID[620]:ARSM5*/ + [590] = {0xE67C2040U, 0x0000000FU}, /* RGIDR_MODID[621]:ARSM6*/ + [591] = {0xE67C2044U, 0x0000000FU}, /* RGIDR_MODID[622]:ARSM7*/ + [592] = {0xE67C2048U, 0x00000000U}, /* RGIDR_MODID[623]:ARSM8*/ + [593] = {0xE67C204CU, 0x0000000BU}, /* RGIDR_MODID[624]:AXMM0*/ + [594] = {0xE67C2050U, 0x0000000BU}, /* RGIDR_MODID[625]:AXMM1*/ + [595] = {0xE67C2054U, 0x00000000U}, /* RGIDR_MODID[626]:AXMMPMON*/ + [596] = {0xE67C2058U, 0x0000000AU}, /* RGIDR_MODID[627]:CKMMM*/ + [597] = {0xE67C205CU, 0x0000000FU}, /* RGIDR_MODID[628]:ECMMM*/ + [598] = {0xE67C2060U, 0x0000000EU}, /* RGIDR_MODID[629]:FBADBSC0*/ + [599] = {0xE67C2064U, 0x0000000EU}, /* RGIDR_MODID[630]:FBADBSC1*/ + [600] = {0xE67C2068U, 0x0000000EU}, /* RGIDR_MODID[631]:FBAMM*/ + [601] = {0xE67C206CU, 0x0000004EU}, /* RGIDR_MODID[632]:IPMMUMM00*/ + [602] = {0xE67C2070U, 0x0000000FU}, /* RGIDR_MODID[633]:DBS0A0*/ + [603] = {0xE67C2074U, 0x0000000AU}, /* RGIDR_MODID[634]:DBS0A1*/ + [604] = {0xE67C2078U, 0x0000000FU}, /* RGIDR_MODID[635]:DBS1A0*/ + [605] = {0xE67C207CU, 0x0000000AU}, /* RGIDR_MODID[636]:DBS1A1*/ + [606] = {0xE67C2080U, 0x0000000FU}, /* RGIDR_MODID[637]:AXCIDBS*/ + [607] = {0xE67C2084U, 0x00000009U}, /* RGIDR_MODID[638]:FCPRC*/ + [608] = {0xE67C2088U, 0x0000000FU}, /* RGIDR_MODID[639]:DBS0D0*/ + [609] = {0xE67C208CU, 0x0000000AU}, /* RGIDR_MODID[640]:DBS0D1*/ + [610] = {0xE67C2090U, 0x0000000FU}, /* RGIDR_MODID[641]:DBS1D0*/ + [611] = {0xE67C2094U, 0x0000000AU}, /* RGIDR_MODID[642]:DBS1D1*/ + [612] = {0xE67C2098U, 0x0000000EU}, /* RGIDR_MODID[643]:FBADDR*/ + [613] = {0xE67C209CU, 0x0000004EU}, /* RGIDR_MODID[644]:IPMMUMM01*/ + [614] = {0xE67C20A0U, 0x0000004EU}, /* RGIDR_MODID[645]:IPMMUMM10*/ + [615] = {0xE67C20A4U, 0x0000004EU}, /* RGIDR_MODID[646]:IPMMUMM11*/ + [616] = {0xE67C20A8U, 0x0000004EU}, /* RGIDR_MODID[647]:IPMMUMM12*/ + [617] = {0xE67C20ACU, 0x0000004EU}, /* RGIDR_MODID[648]:IPMMUMM13*/ + [618] = {0xE67C20B0U, 0x0000004EU}, /* RGIDR_MODID[649]:IPMMUMM14*/ + [619] = {0xE67C20B4U, 0x0000004EU}, /* RGIDR_MODID[650]:IPMMUMM15*/ + [620] = {0xE67C20B8U, 0x0000004EU}, /* RGIDR_MODID[651]:IPMMUMM02*/ + [621] = {0xE67C20BCU, 0x0000004EU}, /* RGIDR_MODID[652]:IPMMUMM03*/ + [622] = {0xE67C20C0U, 0x0000004EU}, /* RGIDR_MODID[653]:IPMMUMM04*/ + [623] = {0xE67C20C4U, 0x0000004EU}, /* RGIDR_MODID[654]:IPMMUMM05*/ + [624] = {0xE67C20C8U, 0x0000004EU}, /* RGIDR_MODID[655]:IPMMUMM06*/ + [625] = {0xE67C20CCU, 0x0000004EU}, /* RGIDR_MODID[656]:IPMMUMM07*/ + [626] = {0xE67C20D0U, 0x0000004EU}, /* RGIDR_MODID[657]:IPMMUMM08*/ + [627] = {0xE67C20D4U, 0x0000004EU}, /* RGIDR_MODID[658]:IPMMUMM09*/ + [628] = {0xFF802000U, 0x0000000FU}, /* RGIDR_MODID[659]:ARSN0*/ + /* After setting */ /* RGIDR_MODID[660]:ARSN1*/ + /* After setting */ /* RGIDR_MODID[661]:ARSN2*/ + [629] = {0xFF80200CU, 0x0000000FU}, /* RGIDR_MODID[662]:ARSN3*/ + [630] = {0xFF802010U, 0x0000000FU}, /* RGIDR_MODID[663]:ARSN4*/ + [631] = {0xFF802014U, 0x0000000FU}, /* RGIDR_MODID[664]:ARSN5*/ + [632] = {0xFF802018U, 0x0000000FU}, /* RGIDR_MODID[665]:ARSN6*/ + [633] = {0xFF80201CU, 0x00000007U}, /* RGIDR_MODID[666]:ARSN7*/ + [634] = {0xFF802020U, 0x00000000U}, /* RGIDR_MODID[667]:ARSN8*/ + [635] = {0xFF802024U, 0x0000000FU}, /* RGIDR_MODID[668]:ECMTOP3*/ + [636] = {0xE7752000U, 0x0000000FU}, /* RGIDR_MODID[669]:ARSD00*/ + /* After setting */ /* RGIDR_MODID[670]:ARSD01*/ + /* After setting */ /* RGIDR_MODID[671]:ARSD02*/ + [637] = {0xE775200CU, 0x0000000FU}, /* RGIDR_MODID[672]:ARSD03*/ + [638] = {0xE7752010U, 0x0000000FU}, /* RGIDR_MODID[673]:ARSD04*/ + [639] = {0xE7752014U, 0x0000000FU}, /* RGIDR_MODID[674]:ARSD05*/ + [640] = {0xE7752018U, 0x0000000FU}, /* RGIDR_MODID[675]:ARSD06*/ + [641] = {0xE775201CU, 0x0000004AU}, /* RGIDR_MODID[676]:AXIFRAY*/ + [642] = {0xE7752020U, 0x0000000FU}, /* RGIDR_MODID[677]:AXIIPC*/ + [643] = {0xE7752028U, 0x0000004FU}, /* RGIDR_MODID[678]:AXIRPC*/ + [644] = {0xE775202CU, 0x0000000FU}, /* RGIDR_MODID[679]:AXISDHI0*/ + [645] = {0xE7752030U, 0x0000000FU}, /* RGIDR_MODID[680]:ARSD07*/ + [646] = {0xE7752034U, 0x00000000U}, /* RGIDR_MODID[681]:ARSD08*/ + [647] = {0xE7752038U, 0x0000000FU}, /* RGIDR_MODID[682]:ARSP00*/ + /* After setting */ /* RGIDR_MODID[683]:ARSP01*/ + /* After setting */ /* RGIDR_MODID[684]:ARSP02*/ + [648] = {0xE7752044U, 0x0000000FU}, /* RGIDR_MODID[685]:ARSP03*/ + [649] = {0xE7752048U, 0x0000000FU}, /* RGIDR_MODID[686]:ARSP04*/ + [650] = {0xE775204CU, 0x0000000FU}, /* RGIDR_MODID[687]:ARSP05*/ + [651] = {0xE7752050U, 0x0000000FU}, /* RGIDR_MODID[688]:ARSP06*/ + [652] = {0xE7752054U, 0x00000007U}, /* RGIDR_MODID[689]:ARSP07*/ + [653] = {0xE7752058U, 0x00000000U}, /* RGIDR_MODID[690]:ARSP08*/ + [654] = {0xE775205CU, 0x0000004EU}, /* RGIDR_MODID[691]:IPMMUDS001*/ + [655] = {0xE7752060U, 0x0000000AU}, /* RGIDR_MODID[692]:CKMPER0*/ + [656] = {0xE7752064U, 0x0000000FU}, /* RGIDR_MODID[693]:ECMPER0*/ + [657] = {0xE7752068U, 0x0000000EU}, /* RGIDR_MODID[694]:FBAPER0*/ + [658] = {0xE775206CU, 0x0000004EU}, /* RGIDR_MODID[695]:FSO0*/ + [659] = {0xE7752070U, 0x0000004EU}, /* RGIDR_MODID[696]:FSO1*/ + [660] = {0xE7752074U, 0x0000004EU}, /* RGIDR_MODID[697]:FSO10*/ + [661] = {0xE7752078U, 0x0000004EU}, /* RGIDR_MODID[698]:FSO2*/ + [662] = {0xE775207CU, 0x0000004EU}, /* RGIDR_MODID[699]:FSO3*/ + [663] = {0xE7752080U, 0x0000004EU}, /* RGIDR_MODID[700]:FSO4*/ + [664] = {0xE7752084U, 0x0000004EU}, /* RGIDR_MODID[701]:FSO5*/ + [665] = {0xE7752088U, 0x0000004EU}, /* RGIDR_MODID[702]:FSO6*/ + [666] = {0xE775208CU, 0x0000004EU}, /* RGIDR_MODID[703]:FSO7*/ + [667] = {0xE7752090U, 0x0000004EU}, /* RGIDR_MODID[704]:FSO8*/ + [668] = {0xE7752094U, 0x0000004EU}, /* RGIDR_MODID[705]:FSO9*/ + [669] = {0xE7752098U, 0x0000002CU}, /* RGIDR_MODID[706]:ADG*/ + [670] = {0xE775209CU, 0x0000000FU}, /* RGIDR_MODID[707]:ECMSD0*/ + [671] = {0xE77520A0U, 0x0000004EU}, /* RGIDR_MODID[708]:IPMMUDS010*/ + [672] = {0xE77520A4U, 0x0000004EU}, /* RGIDR_MODID[709]:IPMMUDS011*/ + [673] = {0xE77520A8U, 0x0000004EU}, /* RGIDR_MODID[710]:I2C0*/ + [674] = {0xE77520ACU, 0x0000004EU}, /* RGIDR_MODID[711]:I2C1*/ + [675] = {0xE77520B0U, 0x0000004EU}, /* RGIDR_MODID[712]:I2C2*/ + [676] = {0xE77520B4U, 0x0000004EU}, /* RGIDR_MODID[713]:I2C3*/ + [677] = {0xE77520B8U, 0x0000004EU}, /* RGIDR_MODID[714]:I2C4*/ + [678] = {0xE77520BCU, 0x0000004EU}, /* RGIDR_MODID[715]:I2C5*/ + [679] = {0xE77520C0U, 0x0000004EU}, /* RGIDR_MODID[716]:IPMMUDS012*/ + [680] = {0xE77520C4U, 0x0000000FU}, /* RGIDR_MODID[717]:IPC*/ + [681] = {0xE77520C8U, 0x0000004EU}, /* RGIDR_MODID[718]:IPMMUDS000*/ + [682] = {0xE77520CCU, 0x0000004EU}, /* RGIDR_MODID[719]:IPMMUDS013*/ + [683] = {0xE77520D0U, 0x0000004EU}, /* RGIDR_MODID[720]:IPMMUDS014*/ + [684] = {0xE77520D4U, 0x0000004EU}, /* RGIDR_MODID[721]:IPMMUDS015*/ + [685] = {0xE77520D8U, 0x0000004EU}, /* RGIDR_MODID[722]:IPMMUDS002*/ + [686] = {0xE77520DCU, 0x0000004EU}, /* RGIDR_MODID[723]:IPMMUDS003*/ + [687] = {0xE77520E0U, 0x0000004EU}, /* RGIDR_MODID[724]:IPMMUDS004*/ + [688] = {0xE77520E4U, 0x0000004EU}, /* RGIDR_MODID[725]:IPMMUDS005*/ + [689] = {0xE77520E8U, 0x0000002CU}, /* RGIDR_MODID[726]:SSI*/ + [690] = {0xE77520ECU, 0x0000004EU}, /* RGIDR_MODID[727]:IPMMUDS006*/ + [691] = {0xE77520F0U, 0x0000004EU}, /* RGIDR_MODID[728]:IPMMUDS007*/ + [692] = {0xE77520F4U, 0x0000000CU}, /* RGIDR_MODID[729]:SYDM1P*/ + [693] = {0xE77520F8U, 0x0000004EU}, /* RGIDR_MODID[730]:IPMMUDS008*/ + [694] = {0xE77520FCU, 0x0000000CU}, /* RGIDR_MODID[731]:SYDM2P*/ + [695] = {0xE7752100U, 0x0000004EU}, /* RGIDR_MODID[732]:IPMMUDS009*/ + [696] = {0xE7752240U, 0x0000000CU}, /* RGIDR_MODID[733]:SYDM100*/ + [697] = {0xE7752244U, 0x0000000CU}, /* RGIDR_MODID[734]:SYDM101*/ + [698] = {0xE7752248U, 0x0000000CU}, /* RGIDR_MODID[735]:SYDM110*/ + [699] = {0xE775224CU, 0x0000000CU}, /* RGIDR_MODID[736]:SYDM111*/ + [700] = {0xE7752250U, 0x0000000CU}, /* RGIDR_MODID[737]:SYDM112*/ + [701] = {0xE7752254U, 0x0000000CU}, /* RGIDR_MODID[738]:SYDM113*/ + [702] = {0xE7752258U, 0x0000000CU}, /* RGIDR_MODID[739]:SYDM114*/ + [703] = {0xE775225CU, 0x0000000CU}, /* RGIDR_MODID[740]:SYDM115*/ + [704] = {0xE7752260U, 0x0000000CU}, /* RGIDR_MODID[741]:SYDM102*/ + [705] = {0xE7752264U, 0x0000000CU}, /* RGIDR_MODID[742]:SYDM103*/ + [706] = {0xE7752268U, 0x0000000CU}, /* RGIDR_MODID[743]:SYDM104*/ + [707] = {0xE775226CU, 0x0000000CU}, /* RGIDR_MODID[744]:SYDM105*/ + [708] = {0xE7752270U, 0x0000000CU}, /* RGIDR_MODID[745]:SYDM106*/ + [709] = {0xE7752274U, 0x0000000CU}, /* RGIDR_MODID[746]:SYDM107*/ + [710] = {0xE7752278U, 0x0000000CU}, /* RGIDR_MODID[747]:SYDM108*/ + [711] = {0xE775227CU, 0x0000000CU}, /* RGIDR_MODID[748]:SYDM109*/ + [712] = {0xE7752280U, 0x0000000CU}, /* RGIDR_MODID[749]:SYDM200*/ + [713] = {0xE7752284U, 0x0000000CU}, /* RGIDR_MODID[750]:SYDM201*/ + [714] = {0xE7752288U, 0x0000000CU}, /* RGIDR_MODID[751]:SYDM210*/ + [715] = {0xE775228CU, 0x0000000CU}, /* RGIDR_MODID[752]:SYDM211*/ + [716] = {0xE7752290U, 0x0000000CU}, /* RGIDR_MODID[753]:SYDM212*/ + [717] = {0xE7752294U, 0x0000000CU}, /* RGIDR_MODID[754]:SYDM213*/ + [718] = {0xE7752298U, 0x0000000CU}, /* RGIDR_MODID[755]:SYDM214*/ + [719] = {0xE775229CU, 0x0000000CU}, /* RGIDR_MODID[756]:SYDM215*/ + [720] = {0xE77522A0U, 0x0000000CU}, /* RGIDR_MODID[757]:SYDM202*/ + [721] = {0xE77522A4U, 0x0000000CU}, /* RGIDR_MODID[758]:SYDM203*/ + [722] = {0xE77522A8U, 0x0000000CU}, /* RGIDR_MODID[759]:SYDM204*/ + [723] = {0xE77522ACU, 0x0000000CU}, /* RGIDR_MODID[760]:SYDM205*/ + [724] = {0xE77522B0U, 0x0000000CU}, /* RGIDR_MODID[761]:SYDM206*/ + [725] = {0xE77522B4U, 0x0000000CU}, /* RGIDR_MODID[762]:SYDM207*/ + [726] = {0xE77522B8U, 0x0000000CU}, /* RGIDR_MODID[763]:SYDM208*/ + [727] = {0xE77522BCU, 0x0000000CU}, /* RGIDR_MODID[764]:SYDM209*/ + [728] = {0xFE682000U, 0x0000000FU}, /* RGIDR_MODID[765]:ARVC0*/ + /* After setting */ /* RGIDR_MODID[766]:ARVC1*/ + /* After setting */ /* RGIDR_MODID[767]:ARVC2*/ + [729] = {0xFE68200CU, 0x0000000FU}, /* RGIDR_MODID[768]:ARVC3*/ + [730] = {0xFE682010U, 0x0000000EU}, /* RGIDR_MODID[769]:AXIFBABUSVC*/ + [731] = {0xFE682014U, 0x0000000FU}, /* RGIDR_MODID[770]:ARVC4*/ + [732] = {0xFE682018U, 0x0000000FU}, /* RGIDR_MODID[771]:ARVC5*/ + [733] = {0xFE68201CU, 0x0000000FU}, /* RGIDR_MODID[772]:ARVC6*/ + [734] = {0xFE682020U, 0x0000000FU}, /* RGIDR_MODID[773]:ARVC7*/ + [735] = {0xFE682024U, 0x00000000U}, /* RGIDR_MODID[774]:ARVC8*/ + [736] = {0xFE682028U, 0x0000000AU}, /* RGIDR_MODID[775]:CKMVC*/ + [737] = {0xFE68202CU, 0x0000000FU}, /* RGIDR_MODID[776]:ECMVC0*/ + [738] = {0xFE682030U, 0x0000004EU}, /* RGIDR_MODID[777]:IMR2*/ + [739] = {0xFE682034U, 0x0000004EU}, /* RGIDR_MODID[778]:IMR0*/ + [740] = {0xFE682038U, 0x0000004EU}, /* RGIDR_MODID[779]:IMR1*/ + [741] = {0xFE68203CU, 0x0000004EU}, /* RGIDR_MODID[780]:IPMMUVC01*/ + [742] = {0xFE682040U, 0x0000004EU}, /* RGIDR_MODID[781]:IPMMUVC10*/ + [743] = {0xFE682044U, 0x0000000CU}, /* RGIDR_MODID[782]:IMS0*/ + [744] = {0xFE682048U, 0x0000000CU}, /* RGIDR_MODID[783]:IMS1*/ + [745] = {0xFE68204CU, 0x0000004EU}, /* RGIDR_MODID[784]:IPMMUVC00*/ + [746] = {0xFE682050U, 0x0000004EU}, /* RGIDR_MODID[785]:IPMMUVC11*/ + [747] = {0xFE682054U, 0x0000004EU}, /* RGIDR_MODID[786]:IPMMUVC12*/ + [748] = {0xFE682058U, 0x0000004EU}, /* RGIDR_MODID[787]:IPMMUVC13*/ + [749] = {0xFE68205CU, 0x0000004EU}, /* RGIDR_MODID[788]:IPMMUVC14*/ + [750] = {0xFE682060U, 0x0000004EU}, /* RGIDR_MODID[789]:IPMMUVC15*/ + [751] = {0xFE682064U, 0x0000004EU}, /* RGIDR_MODID[790]:IPMMUVC02*/ + [752] = {0xFE682068U, 0x0000004EU}, /* RGIDR_MODID[791]:IPMMUVC03*/ + [753] = {0xFE68206CU, 0x0000004EU}, /* RGIDR_MODID[792]:IPMMUVC04*/ + [754] = {0xFE682070U, 0x0000004EU}, /* RGIDR_MODID[793]:IPMMUVC05*/ + [755] = {0xFE682074U, 0x0000004EU}, /* RGIDR_MODID[794]:IPMMUVC06*/ + [756] = {0xFE682078U, 0x0000004EU}, /* RGIDR_MODID[795]:IPMMUVC07*/ + [757] = {0xFE68207CU, 0x0000004EU}, /* RGIDR_MODID[796]:IPMMUVC08*/ + [758] = {0xFE682080U, 0x0000004EU}, /* RGIDR_MODID[797]:IPMMUVC09*/ + [759] = {0xFE682084U, 0x00000028U}, /* RGIDR_MODID[798]:IV1ES*/ + [760] = {0xFEBE2000U, 0x0000004EU}, /* RGIDR_MODID[799]:CSITOP0*/ + [761] = {0xFEBE2004U, 0x0000000FU}, /* RGIDR_MODID[800]:ARVI10*/ + /* After setting */ /* RGIDR_MODID[801]:ARVI11*/ + /* After setting */ /* RGIDR_MODID[802]:ARVI12*/ + [762] = {0xFEBE2010U, 0x0000000FU}, /* RGIDR_MODID[803]:ARVI13*/ + [763] = {0xFEBE2014U, 0x0000000FU}, /* RGIDR_MODID[804]:ARVI14*/ + [764] = {0xFEBE2018U, 0x0000000FU}, /* RGIDR_MODID[805]:ARVI15*/ + [765] = {0xFEBE201CU, 0x0000000FU}, /* RGIDR_MODID[806]:ARVI16*/ + [766] = {0xFEBE2020U, 0x0000000FU}, /* RGIDR_MODID[807]:ARVI17*/ + [767] = {0xFEBE2024U, 0x00000000U}, /* RGIDR_MODID[808]:ARVI18*/ + [768] = {0xFEBE2028U, 0x0000000AU}, /* RGIDR_MODID[809]:CKMVIO*/ + [769] = {0xFEBE202CU, 0x0000004EU}, /* RGIDR_MODID[810]:CSITOP1*/ + [770] = {0xFEBE2034U, 0x0000004EU}, /* RGIDR_MODID[811]:DSITLINK0*/ + [771] = {0xFEBE2038U, 0x0000004EU}, /* RGIDR_MODID[812]:DSITLINK1*/ + [772] = {0xFEBE203CU, 0x0000000FU}, /* RGIDR_MODID[813]:ECMVIO1*/ + [773] = {0xFEBE2044U, 0x0000004EU}, /* RGIDR_MODID[814]:IPMMUVI001*/ + [774] = {0xFEBE2048U, 0x0000000CU}, /* RGIDR_MODID[815]:FCPVX0*/ + [775] = {0xFEBE204CU, 0x0000000CU}, /* RGIDR_MODID[816]:FCPVX1*/ + [776] = {0xFEBE2058U, 0x0000004EU}, /* RGIDR_MODID[817]:IPMMUVI000*/ + [777] = {0xFEBE205CU, 0x0000004EU}, /* RGIDR_MODID[818]:IPMMUVI100*/ + [778] = {0xFEBE2060U, 0x0000004EU}, /* RGIDR_MODID[819]:IPMMUVI010*/ + [779] = {0xFEBE2064U, 0x0000004EU}, /* RGIDR_MODID[820]:IPMMUVI011*/ + [780] = {0xFEBE2068U, 0x0000004EU}, /* RGIDR_MODID[821]:VSPX0*/ + [781] = {0xFEBE206CU, 0x0000004EU}, /* RGIDR_MODID[822]:VSPX1*/ + [782] = {0xFEBE2078U, 0x0000004EU}, /* RGIDR_MODID[823]:IPMMUVI012*/ + [783] = {0xFEBE207CU, 0x0000004EU}, /* RGIDR_MODID[824]:IPMMUVI013*/ + [784] = {0xFEBE2080U, 0x0000004EU}, /* RGIDR_MODID[825]:IPMMUVI014*/ + [785] = {0xFEBE2084U, 0x0000004EU}, /* RGIDR_MODID[826]:IPMMUVI015*/ + [786] = {0xFEBE2088U, 0x0000004EU}, /* RGIDR_MODID[827]:IPMMUVI002*/ + [787] = {0xFEBE208CU, 0x0000004EU}, /* RGIDR_MODID[828]:IPMMUVI003*/ + [788] = {0xFEBE2090U, 0x0000004EU}, /* RGIDR_MODID[829]:IPMMUVI004*/ + [789] = {0xFEBE2094U, 0x0000004EU}, /* RGIDR_MODID[830]:IPMMUVI005*/ + [790] = {0xFEBE2098U, 0x0000004EU}, /* RGIDR_MODID[831]:IPMMUVI006*/ + [791] = {0xFEBE209CU, 0x0000004EU}, /* RGIDR_MODID[832]:IPMMUVI007*/ + [792] = {0xFEBE20A0U, 0x0000004EU}, /* RGIDR_MODID[833]:IPMMUVI008*/ + [793] = {0xFEBE20A4U, 0x0000004EU}, /* RGIDR_MODID[834]:IPMMUVI009*/ + [794] = {0xFEBE20A8U, 0x0000004EU}, /* RGIDR_MODID[835]:IPMMUVI101*/ + [795] = {0xFEBE20ACU, 0x0000004EU}, /* RGIDR_MODID[836]:IPMMUVI110*/ + [796] = {0xFEBE20B0U, 0x0000004EU}, /* RGIDR_MODID[837]:IPMMUVI111*/ + [797] = {0xFEBE20B4U, 0x0000004EU}, /* RGIDR_MODID[838]:IPMMUVI112*/ + [798] = {0xFEBE20B8U, 0x0000004EU}, /* RGIDR_MODID[839]:IPMMUVI113*/ + [799] = {0xFEBE20BCU, 0x0000004EU}, /* RGIDR_MODID[840]:IPMMUVI114*/ + [800] = {0xFEBE20C0U, 0x0000004EU}, /* RGIDR_MODID[841]:IPMMUVI115*/ + [801] = {0xFEBE20C4U, 0x0000004EU}, /* RGIDR_MODID[842]:IPMMUVI102*/ + [802] = {0xFEBE20C8U, 0x0000004EU}, /* RGIDR_MODID[843]:IPMMUVI103*/ + [803] = {0xFEBE20CCU, 0x0000004EU}, /* RGIDR_MODID[844]:IPMMUVI104*/ + [804] = {0xFEBE20D0U, 0x0000004EU}, /* RGIDR_MODID[845]:IPMMUVI105*/ + [805] = {0xFEBE20D4U, 0x0000004EU}, /* RGIDR_MODID[846]:IPMMUVI106*/ + [806] = {0xFEBE20D8U, 0x0000004EU}, /* RGIDR_MODID[847]:IPMMUVI107*/ + [807] = {0xFEBE20DCU, 0x0000004EU}, /* RGIDR_MODID[848]:IPMMUVI108*/ + [808] = {0xFEBE20E0U, 0x0000004EU}, /* RGIDR_MODID[849]:IPMMUVI109*/ + [809] = {0xFEBE2104U, 0x0000000EU}, /* RGIDR_MODID[850]:AXIFBABUSVIO*/ + [810] = {0xFEBF2000U, 0x0000000FU}, /* RGIDR_MODID[851]:ARVI0*/ + /* After setting */ /* RGIDR_MODID[852]:ARVI1*/ + /* After setting */ /* RGIDR_MODID[853]:ARVI2*/ + [811] = {0xFEBF200CU, 0x0000000FU}, /* RGIDR_MODID[854]:ARVI3*/ + [812] = {0xFEBF2010U, 0x0000000FU}, /* RGIDR_MODID[855]:ARVI4*/ + [813] = {0xFEBF2014U, 0x0000000FU}, /* RGIDR_MODID[856]:ARVI5*/ + [814] = {0xFEBF2018U, 0x0000000FU}, /* RGIDR_MODID[857]:ARVI6*/ + [815] = {0xFEBF201CU, 0x0000000FU}, /* RGIDR_MODID[858]:ARVI7*/ + [816] = {0xFEBF2020U, 0x00000000U}, /* RGIDR_MODID[859]:ARVI8*/ + [817] = {0xFEBF2024U, 0x0000000FU}, /* RGIDR_MODID[860]:ECMVIO0*/ + [818] = {0xFEBF2028U, 0x0000004EU}, /* RGIDR_MODID[861]:ISP0*/ + [819] = {0xFEBF202CU, 0x0000004EU}, /* RGIDR_MODID[862]:ISP0CORE*/ + [820] = {0xFEBF2030U, 0x0000004EU}, /* RGIDR_MODID[863]:ISP1*/ + [821] = {0xFEBF2034U, 0x0000004EU}, /* RGIDR_MODID[864]:ISP1CORE*/ + [822] = {0xFEBF2054U, 0x0000004EU}, /* RGIDR_MODID[865]:VIN00*/ + [823] = {0xFEBF2058U, 0x0000004EU}, /* RGIDR_MODID[866]:VIN01*/ + [824] = {0xFEBF205CU, 0x0000004EU}, /* RGIDR_MODID[867]:VIN02*/ + [825] = {0xFEBF2060U, 0x0000004EU}, /* RGIDR_MODID[868]:VIN03*/ + [826] = {0xFEBF2064U, 0x0000004EU}, /* RGIDR_MODID[869]:VIN04*/ + [827] = {0xFEBF2068U, 0x0000004EU}, /* RGIDR_MODID[870]:VIN05*/ + [828] = {0xFEBF206CU, 0x0000004EU}, /* RGIDR_MODID[871]:VIN06*/ + [829] = {0xFEBF2070U, 0x0000004EU}, /* RGIDR_MODID[872]:VIN07*/ + [830] = {0xFEBF2074U, 0x0000004EU}, /* RGIDR_MODID[873]:VIN10*/ + [831] = {0xFEBF2078U, 0x0000004EU}, /* RGIDR_MODID[874]:VIN11*/ + [832] = {0xFEBF207CU, 0x0000004EU}, /* RGIDR_MODID[875]:VIN12*/ + [833] = {0xFEBF2080U, 0x0000004EU}, /* RGIDR_MODID[876]:VIN13*/ + [834] = {0xFEBF2084U, 0x0000004EU}, /* RGIDR_MODID[877]:VIN14*/ + [835] = {0xFEBF2088U, 0x0000004EU}, /* RGIDR_MODID[878]:VIN15*/ + [836] = {0xFEBF208CU, 0x0000004EU}, /* RGIDR_MODID[879]:VIN16*/ + [837] = {0xFEBF2090U, 0x0000004EU}, /* RGIDR_MODID[880]:VIN17*/ + [838] = {0xE7B12000U, 0x0000000FU}, /* RGIDR_MODID[881]:ARVIP00*/ + /* After setting */ /* RGIDR_MODID[882]:ARVIP01*/ + /* After setting */ /* RGIDR_MODID[883]:ARVIP02*/ + [839] = {0xE7B1200CU, 0x0000000FU}, /* RGIDR_MODID[884]:ARVIP03*/ + [840] = {0xE7B12010U, 0x0000000EU}, /* RGIDR_MODID[885]:AXIFBABUSVIP0*/ + [841] = {0xE7B12014U, 0x0000000FU}, /* RGIDR_MODID[886]:ARVIP04*/ + [842] = {0xE7B12018U, 0x0000000FU}, /* RGIDR_MODID[887]:ARVIP05*/ + [843] = {0xE7B1201CU, 0x0000000FU}, /* RGIDR_MODID[888]:ARVIP06*/ + [844] = {0xE7B12020U, 0x00000007U}, /* RGIDR_MODID[889]:ARVIP07*/ + [845] = {0xE7B12024U, 0x00000000U}, /* RGIDR_MODID[890]:ARVIP08*/ + [846] = {0xE7B12028U, 0x0000000AU}, /* RGIDR_MODID[891]:CKMVIP*/ + [847] = {0xE7B1202CU, 0x0000000FU}, /* RGIDR_MODID[892]:ECMVIP0*/ + [848] = {0xE7B12030U, 0x0000004EU}, /* RGIDR_MODID[893]:IPMMUVIP000*/ + [849] = {0xE7B12038U, 0x0000004EU}, /* RGIDR_MODID[894]:SMPO0*/ + [850] = {0xE7B1203CU, 0x0000004EU}, /* RGIDR_MODID[895]:SMPS0*/ + [851] = {0xE7B12040U, 0x0000000CU}, /* RGIDR_MODID[896]:UMFL0*/ + [852] = {0xE7B12044U, 0x0000004EU}, /* RGIDR_MODID[897]:IPMMUVIP001*/ + [853] = {0xE7B12048U, 0x0000004EU}, /* RGIDR_MODID[898]:IPMMUVIP010*/ + [854] = {0xE7B1204CU, 0x0000004EU}, /* RGIDR_MODID[899]:IPMMUVIP011*/ + [855] = {0xE7B12050U, 0x0000004EU}, /* RGIDR_MODID[900]:UMFL0M_W*/ + [856] = {0xE7B12054U, 0x0000004EU}, /* RGIDR_MODID[901]:IPMMUVIP012*/ + [857] = {0xE7B12058U, 0x0000004EU}, /* RGIDR_MODID[902]:IPMMUVIP013*/ + [858] = {0xE7B1205CU, 0x0000004EU}, /* RGIDR_MODID[903]:IPMMUVIP014*/ + [859] = {0xE7B12060U, 0x0000004EU}, /* RGIDR_MODID[904]:IPMMUVIP015*/ + [860] = {0xE7B12064U, 0x0000004EU}, /* RGIDR_MODID[905]:IPMMUVIP002*/ + [861] = {0xE7B12068U, 0x0000004EU}, /* RGIDR_MODID[906]:IPMMUVIP003*/ + [862] = {0xE7B1206CU, 0x0000004EU}, /* RGIDR_MODID[907]:IPMMUVIP004*/ + [863] = {0xE7B12070U, 0x0000004EU}, /* RGIDR_MODID[908]:IPMMUVIP005*/ + [864] = {0xE7B12074U, 0x0000004EU}, /* RGIDR_MODID[909]:IPMMUVIP006*/ + [865] = {0xE7B12078U, 0x0000004EU}, /* RGIDR_MODID[910]:IPMMUVIP007*/ + [866] = {0xE7B1207CU, 0x0000004EU}, /* RGIDR_MODID[911]:IPMMUVIP008*/ + [867] = {0xE7B12080U, 0x0000004EU}, /* RGIDR_MODID[912]:IPMMUVIP009*/ + [868] = {0xE7B42000U, 0x0000000FU}, /* RGIDR_MODID[913]:ARVIP10*/ + /* After setting */ /* RGIDR_MODID[914]:ARVIP11*/ + /* After setting */ /* RGIDR_MODID[915]:ARVIP12*/ + [869] = {0xE7B4200CU, 0x0000000FU}, /* RGIDR_MODID[916]:ARVIP13*/ + [870] = {0xE7B42010U, 0x0000000EU}, /* RGIDR_MODID[917]:AXIFBABUSVIP1*/ + [871] = {0xE7B42014U, 0x0000000FU}, /* RGIDR_MODID[918]:ARVIIP14*/ + [872] = {0xE7B42018U, 0x0000000FU}, /* RGIDR_MODID[919]:ARVIIP15*/ + [873] = {0xE7B4201CU, 0x0000000FU}, /* RGIDR_MODID[920]:ARVIIP16*/ + [874] = {0xE7B42020U, 0x0000000FU}, /* RGIDR_MODID[921]:ARVIIP17*/ + [875] = {0xE7B42024U, 0x00000000U}, /* RGIDR_MODID[922]:ARVIIP18*/ + [876] = {0xE7B42038U, 0x0000000FU}, /* RGIDR_MODID[923]:ECMVIP1*/ + [877] = {0xE7B4203CU, 0x0000004EU}, /* RGIDR_MODID[924]:IPMMUVIP101*/ + [878] = {0xE7B42040U, 0x0000004EU}, /* RGIDR_MODID[925]:IPMMUVIP100*/ + [879] = {0xE7B42044U, 0x0000004EU}, /* RGIDR_MODID[926]:IPMMUVIP110*/ + [880] = {0xE7B42048U, 0x0000004EU}, /* RGIDR_MODID[927]:IPMMUVIP111*/ + [881] = {0xE7B4204CU, 0x0000004EU}, /* RGIDR_MODID[928]:IPMMUVIP112*/ + [882] = {0xE7B42050U, 0x0000004EU}, /* RGIDR_MODID[929]:IPMMUVIP113*/ + [883] = {0xE7B42054U, 0x0000004EU}, /* RGIDR_MODID[930]:IPMMUVIP114*/ + [884] = {0xE7B42058U, 0x0000004EU}, /* RGIDR_MODID[931]:IPMMUVIP115*/ + [885] = {0xE7B4205CU, 0x0000004EU}, /* RGIDR_MODID[932]:IPMMUVIP102*/ + [886] = {0xE7B42060U, 0x0000004EU}, /* RGIDR_MODID[933]:IPMMUVIP103*/ + [887] = {0xE7B42064U, 0x0000004EU}, /* RGIDR_MODID[934]:IPMMUVIP104*/ + [888] = {0xE7B42068U, 0x0000004EU}, /* RGIDR_MODID[935]:IPMMUVIP105*/ + [889] = {0xE7B4206CU, 0x0000004EU}, /* RGIDR_MODID[936]:IPMMUVIP106*/ + [890] = {0xE7B42070U, 0x0000004EU}, /* RGIDR_MODID[937]:IPMMUVIP107*/ + [891] = {0xE7B42074U, 0x0000004EU}, /* RGIDR_MODID[938]:IPMMUVIP108*/ + [892] = {0xE7B42078U, 0x0000004EU}, /* RGIDR_MODID[939]:IPMMUVIP109*/ + [893] = {0xE7B42118U, 0x00000004U}, /* RGIDR_MODID[940]:PAP*/ + [894] = {0xEB802000U, 0x0000000FU}, /* RGIDR_MODID[941]:ARDSP0*/ + /* After setting */ /* RGIDR_MODID[942]:ARDSP1*/ + /* After setting */ /* RGIDR_MODID[943]:ARDSP2*/ + [895] = {0xEB80200CU, 0x0000000FU}, /* RGIDR_MODID[944]:ARDSP3*/ + [896] = {0xEB802010U, 0x0000000FU}, /* RGIDR_MODID[945]:ARDSP4*/ + [897] = {0xEB802014U, 0x0000000FU}, /* RGIDR_MODID[946]:ARDSP5*/ + [898] = {0xEB802018U, 0x0000000FU}, /* RGIDR_MODID[947]:ARDSP6*/ + [899] = {0xEB80201CU, 0x0000000FU}, /* RGIDR_MODID[948]:ARDSP7*/ + [900] = {0xEB802020U, 0x0000000FU}, /* RGIDR_MODID[949]:ECMDSP*/ + [901] = {0xEB802024U, 0x0000000CU}, /* RGIDR_MODID[950]:AXIDSP0*/ + [902] = {0xEB802028U, 0x0000000CU}, /* RGIDR_MODID[951]:AXIDSP1*/ + [903] = {0xEB80202CU, 0x0000000CU}, /* RGIDR_MODID[952]:AXIDSP2*/ + [904] = {0xEB802030U, 0x0000000CU}, /* RGIDR_MODID[953]:AXIDSP3*/ + [906] = {0xE67B9660U, 0x0000000FU}, /* RGIDR_MODID[954]:ARCC*/ + [905] = {0xE67B9674U, 0x0000000FU}, /* RGIDR_MODID[955]:ARRTRAM*/ + [907] = {0xE7752024U, 0x00000000U}, /* RGIDR_MODID[956]:RSV0*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_w_tbl" +#else +__attribute__ ((section(".rgid_w_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_write_tbl[] = { + [0] = {0xFFC82400U, 0x0000000EU}, /* RGIDW_MODID[0]:ARMGC0*/ + [1] = {0xFFC82404U, 0x0000000EU}, /* RGIDW_MODID[1]:ARMGC1*/ + [2] = {0xFFC82408U, 0x00000000U}, /* RGIDW_MODID[2]:ARMGC2*/ + [3] = {0xFFC8240CU, 0x00000002U}, /* RGIDW_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDW_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDW_MODID[5]:ARRT02*/ + [4] = {0xFFC82418U, 0x00000001U}, /* RGIDW_MODID[6]:ARRT03*/ + [5] = {0xFFC8241CU, 0x00000002U}, /* RGIDW_MODID[7]:ARRT04*/ + [6] = {0xFFC82420U, 0x00000001U}, /* RGIDW_MODID[8]:ARRT05*/ + [7] = {0xFFC82424U, 0x00000002U}, /* RGIDW_MODID[9]:ARRT06*/ + [8] = {0xFFC82428U, 0x00000002U}, /* RGIDW_MODID[10]:ARRT07*/ + [9] = {0xFFC8242CU, 0x00000000U}, /* RGIDW_MODID[11]:ARRT08*/ + [10] = {0xFFC82430U, 0x00000001U}, /* RGIDW_MODID[12]:LIFEC0*/ + [11] = {0xFFC82434U, 0x0000000EU}, /* RGIDW_MODID[13]:SWDT*/ + [12] = {0xFFC82438U, 0x0000006EU}, /* RGIDW_MODID[14]:TMU0*/ + [13] = {0xFFC8243CU, 0x0000000EU}, /* RGIDW_MODID[15]:WDT*/ + [14] = {0xFFC82440U, 0x0000000EU}, /* RGIDW_MODID[16]:WWDT0*/ + [15] = {0xFFC82444U, 0x0000000EU}, /* RGIDW_MODID[17]:WWDT1*/ + [16] = {0xFFC82448U, 0x0000000EU}, /* RGIDW_MODID[18]:WWDT2*/ + [17] = {0xFFC8244CU, 0x0000000EU}, /* RGIDW_MODID[19]:WWDT3*/ + [18] = {0xFFC82450U, 0x0000000EU}, /* RGIDW_MODID[20]:WWDT4*/ + [19] = {0xFFC82454U, 0x0000000EU}, /* RGIDW_MODID[21]:WWDT5*/ + [20] = {0xFFC82458U, 0x0000000EU}, /* RGIDW_MODID[22]:WWDT6*/ + [21] = {0xFFC82468U, 0x0000000AU}, /* RGIDW_MODID[23]:ECMRT3*/ + [22] = {0xE6002400U, 0x00000006U}, /* RGIDW_MODID[24]:ADVFSC*/ + [23] = {0xE6002404U, 0x0000000FU}, /* RGIDW_MODID[25]:APMU0*/ + [24] = {0xE6002408U, 0x00000002U}, /* RGIDW_MODID[26]:APMU1*/ + [25] = {0xE600240CU, 0x00000000U}, /* RGIDW_MODID[27]:APMU10*/ + [26] = {0xE6002410U, 0x00000000U}, /* RGIDW_MODID[28]:APMU11*/ + [27] = {0xE6002414U, 0x00000000U}, /* RGIDW_MODID[29]:APMU12*/ + [28] = {0xE6002418U, 0x00000000U}, /* RGIDW_MODID[30]:APMU13*/ + [29] = {0xE600241CU, 0x00000000U}, /* RGIDW_MODID[31]:APMU14*/ + [30] = {0xE6002420U, 0x00000000U}, /* RGIDW_MODID[32]:APMU15*/ + [31] = {0xE6002424U, 0x00000004U}, /* RGIDW_MODID[33]:APMU2*/ + [32] = {0xE6002428U, 0x00000004U}, /* RGIDW_MODID[34]:APMU3*/ + [33] = {0xE600242CU, 0x00000000U}, /* RGIDW_MODID[35]:APMU4*/ + [34] = {0xE6002430U, 0x00000000U}, /* RGIDW_MODID[36]:APMU5*/ + [35] = {0xE6002434U, 0x00000000U}, /* RGIDW_MODID[37]:APMU6*/ + [36] = {0xE6002438U, 0x00000000U}, /* RGIDW_MODID[38]:APMU7*/ + [37] = {0xE600243CU, 0x00000000U}, /* RGIDW_MODID[39]:APMU8*/ + [38] = {0xE6002440U, 0x00000000U}, /* RGIDW_MODID[40]:APMU9*/ + [39] = {0xE6002444U, 0x00000002U}, /* RGIDW_MODID[41]:ARS00*/ + /* After setting */ /* RGIDW_MODID[42]:ARS01*/ + /* After setting */ /* RGIDW_MODID[43]:ARS02*/ + [40] = {0xE6002450U, 0x00000001U}, /* RGIDW_MODID[44]:ARS03*/ + [41] = {0xE6002454U, 0x00000002U}, /* RGIDW_MODID[45]:ARS04*/ + [42] = {0xE6002458U, 0x00000001U}, /* RGIDW_MODID[46]:ARS05*/ + [43] = {0xE600245CU, 0x00000002U}, /* RGIDW_MODID[47]:ARS06*/ + [44] = {0xE6002460U, 0x00000002U}, /* RGIDW_MODID[48]:ARS07*/ + [45] = {0xE6002464U, 0x00000000U}, /* RGIDW_MODID[49]:ARS08*/ + [46] = {0xE6002468U, 0x0000000EU}, /* RGIDW_MODID[50]:CMT0*/ + [47] = {0xE600246CU, 0x0000000EU}, /* RGIDW_MODID[51]:CMT1*/ + [48] = {0xE6002470U, 0x0000000EU}, /* RGIDW_MODID[52]:CMT2*/ + [49] = {0xE6002474U, 0x0000000EU}, /* RGIDW_MODID[53]:CMT3*/ + [50] = {0xE6002478U, 0x0000000AU}, /* RGIDW_MODID[54]:CKM*/ + [51] = {0xE600247CU, 0x0000000EU}, /* RGIDW_MODID[55]:DBE*/ + [52] = {0xE6002480U, 0x0000000EU}, /* RGIDW_MODID[56]:IRQC*/ + [53] = {0xE6002484U, 0x0000000AU}, /* RGIDW_MODID[57]:ECMPS0*/ + [54] = {0xE6002488U, 0x0000000BU}, /* RGIDW_MODID[58]:OTP0*/ + [55] = {0xE600248CU, 0x0000000FU}, /* RGIDW_MODID[59]:OTP1*/ + [56] = {0xE600249CU, 0x0000000EU}, /* RGIDW_MODID[60]:SCMT*/ + [57] = {0xE60024A8U, 0x0000004AU}, /* RGIDW_MODID[61]:TSC1*/ + [58] = {0xE60024ACU, 0x0000004AU}, /* RGIDW_MODID[62]:TSC2*/ + [59] = {0xE60024B0U, 0x0000004AU}, /* RGIDW_MODID[63]:TSC3*/ + [60] = {0xE60024B4U, 0x0000004AU}, /* RGIDW_MODID[64]:TSC4*/ + [61] = {0xE60024B8U, 0x00000006U}, /* RGIDW_MODID[65]:UCMT*/ + [62] = {0xE6002500U, 0x0000006FU}, /* RGIDW_MODID[66]:CPG0*/ + [63] = {0xE6002504U, 0x0000000AU}, /* RGIDW_MODID[67]:CPG1*/ + [64] = {0xE6002508U, 0x0000004EU}, /* RGIDW_MODID[68]:CPG2*/ + [65] = {0xE600250CU, 0x00000028U}, /* RGIDW_MODID[69]:CPG3*/ + [66] = {0xE6002510U, 0x0000006FU}, /* RGIDW_MODID[70]:PFC00*/ + [67] = {0xE6002514U, 0x0000000AU}, /* RGIDW_MODID[71]:PFC01*/ + [68] = {0xE6002518U, 0x0000004EU}, /* RGIDW_MODID[72]:PFC02*/ + [69] = {0xE600251CU, 0x00000028U}, /* RGIDW_MODID[73]:PFC03*/ + [70] = {0xE6002520U, 0x0000006FU}, /* RGIDW_MODID[74]:PFC10*/ + [71] = {0xE6002524U, 0x0000000AU}, /* RGIDW_MODID[75]:PFC11*/ + [72] = {0xE6002528U, 0x0000004EU}, /* RGIDW_MODID[76]:PFC12*/ + [73] = {0xE600252CU, 0x00000028U}, /* RGIDW_MODID[77]:PFC13*/ + [74] = {0xE6002530U, 0x0000006FU}, /* RGIDW_MODID[78]:PFC20*/ + [75] = {0xE6002534U, 0x0000000AU}, /* RGIDW_MODID[79]:PFC21*/ + [76] = {0xE6002538U, 0x0000004EU}, /* RGIDW_MODID[80]:PFC22*/ + [77] = {0xE600253CU, 0x00000028U}, /* RGIDW_MODID[81]:PFC23*/ + [78] = {0xE6002540U, 0x0000006FU}, /* RGIDW_MODID[82]:PFC30*/ + [79] = {0xE6002544U, 0x0000000AU}, /* RGIDW_MODID[83]:PFC31*/ + [80] = {0xE6002548U, 0x0000004EU}, /* RGIDW_MODID[84]:PFC32*/ + [81] = {0xE600254CU, 0x00000028U}, /* RGIDW_MODID[85]:PFC33*/ + [82] = {0xE6002550U, 0x0000006FU}, /* RGIDW_MODID[86]:PFCS0*/ + [83] = {0xE6002554U, 0x0000000AU}, /* RGIDW_MODID[87]:PFCS1*/ + [84] = {0xE6002558U, 0x0000004EU}, /* RGIDW_MODID[88]:PFCS2*/ + [85] = {0xE600255CU, 0x00000028U}, /* RGIDW_MODID[89]:PFCS3*/ + [86] = {0xE6002560U, 0x0000006FU}, /* RGIDW_MODID[90]:RESET0*/ + [87] = {0xE6002564U, 0x0000000AU}, /* RGIDW_MODID[91]:RESET1*/ + [88] = {0xE6002568U, 0x0000004EU}, /* RGIDW_MODID[92]:RESET2*/ + [89] = {0xE600256CU, 0x00000028U}, /* RGIDW_MODID[93]:RESET3*/ + [90] = {0xE6002570U, 0x0000006FU}, /* RGIDW_MODID[94]:SYS0*/ + [91] = {0xE6002574U, 0x0000000AU}, /* RGIDW_MODID[95]:SYS1*/ + [92] = {0xE6002578U, 0x0000004EU}, /* RGIDW_MODID[96]:SYS2*/ + [93] = {0xE600257CU, 0x00000028U}, /* RGIDW_MODID[97]:SYS3*/ + [94] = {0xE7762400U, 0x0000000EU}, /* RGIDW_MODID[98]:DMAMSI0*/ + [95] = {0xE7762404U, 0x0000000EU}, /* RGIDW_MODID[99]:DMAMSI1*/ + [96] = {0xE7762408U, 0x0000000EU}, /* RGIDW_MODID[100]:DMAMSI2*/ + [97] = {0xE776240CU, 0x0000000EU}, /* RGIDW_MODID[101]:DMAMSI3*/ + [98] = {0xE7762410U, 0x0000000EU}, /* RGIDW_MODID[102]:DMAMSI4*/ + [99] = {0xE7762414U, 0x0000000EU}, /* RGIDW_MODID[103]:DMAMSI5*/ + [100] = {0xE7762418U, 0x0000000AU}, /* RGIDW_MODID[104]:ECMSP3*/ + [101] = {0xE7762424U, 0x00000002U}, /* RGIDW_MODID[105]:ARSP30*/ + /* After setting */ /* RGIDW_MODID[106]:ARSP31*/ + /* After setting */ /* RGIDW_MODID[107]:ARSP32*/ + [102] = {0xE7762430U, 0x00000001U}, /* RGIDW_MODID[108]:ARSP33*/ + [103] = {0xE7762434U, 0x00000002U}, /* RGIDW_MODID[109]:ARSP34*/ + [104] = {0xE7762438U, 0x00000001U}, /* RGIDW_MODID[110]:ARSP35*/ + [105] = {0xE776243CU, 0x00000002U}, /* RGIDW_MODID[111]:ARSP36*/ + [106] = {0xE7762440U, 0x00000002U}, /* RGIDW_MODID[112]:ARSP37*/ + [107] = {0xE7762444U, 0x00000000U}, /* RGIDW_MODID[113]:ARSP38*/ + [108] = {0xE7762448U, 0x0000000EU}, /* RGIDW_MODID[114]:MSI0*/ + [109] = {0xE776244CU, 0x0000000EU}, /* RGIDW_MODID[115]:MSI1*/ + [110] = {0xE7762450U, 0x0000000EU}, /* RGIDW_MODID[116]:MSI2*/ + [111] = {0xE7762454U, 0x0000000EU}, /* RGIDW_MODID[117]:MSI3*/ + [112] = {0xE7762458U, 0x0000000EU}, /* RGIDW_MODID[118]:MSI4*/ + [113] = {0xE776245CU, 0x0000000EU}, /* RGIDW_MODID[119]:MSI5*/ + [114] = {0xE7792400U, 0x00000002U}, /* RGIDW_MODID[120]:ARSP40*/ + /* After setting */ /* RGIDW_MODID[121]:ARSP41*/ + /* After setting */ /* RGIDW_MODID[122]:ARSP42*/ + [115] = {0xE779240CU, 0x00000001U}, /* RGIDW_MODID[123]:ARSP43*/ + [116] = {0xE7792410U, 0x00000002U}, /* RGIDW_MODID[124]:ARSP44*/ + [117] = {0xE7792414U, 0x00000001U}, /* RGIDW_MODID[125]:ARSP45*/ + [118] = {0xE7792418U, 0x00000002U}, /* RGIDW_MODID[126]:ARSP46*/ + [119] = {0xE779241CU, 0x00000002U}, /* RGIDW_MODID[127]:ARSP47*/ + [120] = {0xE7792420U, 0x00000000U}, /* RGIDW_MODID[128]:ARSP48*/ + [121] = {0xE7792424U, 0x0000004FU}, /* RGIDW_MODID[129]:DMAHSCIF0*/ + [122] = {0xE7792428U, 0x0000004FU}, /* RGIDW_MODID[130]:DMAHSCIF1*/ + [123] = {0xE779242CU, 0x0000004FU}, /* RGIDW_MODID[131]:DMAHSCIF2*/ + [124] = {0xE7792430U, 0x0000004FU}, /* RGIDW_MODID[132]:DMAHSCIF3*/ + [125] = {0xE7792434U, 0x0000004FU}, /* RGIDW_MODID[133]:DMASCIF0*/ + [126] = {0xE7792438U, 0x0000004FU}, /* RGIDW_MODID[134]:DMASCIF1*/ + [127] = {0xE779243CU, 0x0000004FU}, /* RGIDW_MODID[135]:DMASCIF3*/ + [128] = {0xE7792440U, 0x0000004FU}, /* RGIDW_MODID[136]:DMASCIF4*/ + [129] = {0xE7792444U, 0x0000000AU}, /* RGIDW_MODID[137]:ECMSP4*/ + [130] = {0xE7792448U, 0x0000004FU}, /* RGIDW_MODID[138]:HSCIF0*/ + [131] = {0xE779244CU, 0x0000004FU}, /* RGIDW_MODID[139]:HSCIF1*/ + [132] = {0xE7792450U, 0x0000004FU}, /* RGIDW_MODID[140]:HSCIF2*/ + [133] = {0xE7792454U, 0x0000004FU}, /* RGIDW_MODID[141]:HSCIF3*/ + [134] = {0xE7792458U, 0x0000004FU}, /* RGIDW_MODID[142]:SCIF0*/ + [135] = {0xE779245CU, 0x0000004FU}, /* RGIDW_MODID[143]:SCIF1*/ + [136] = {0xE7792460U, 0x0000004FU}, /* RGIDW_MODID[144]:SCIF3*/ + [137] = {0xE7792464U, 0x0000004FU}, /* RGIDW_MODID[145]:SCIF4*/ + [138] = {0xE7792468U, 0x0000006EU}, /* RGIDW_MODID[146]:TMU1*/ + [139] = {0xE779246CU, 0x0000006EU}, /* RGIDW_MODID[147]:TMU2*/ + [140] = {0xE7792470U, 0x0000006EU}, /* RGIDW_MODID[148]:TMU3*/ + [141] = {0xE7792474U, 0x0000006EU}, /* RGIDW_MODID[149]:TMU4*/ + [142] = {0xE7792478U, 0x0000004AU}, /* RGIDW_MODID[150]:CANFD*/ + [143] = {0xE779247CU, 0x0000004AU}, /* RGIDW_MODID[151]:DMACANFD*/ + [144] = {0xE7792480U, 0x00000002U}, /* RGIDW_MODID[152]:DMATPU0*/ + [145] = {0xE7792484U, 0x00000002U}, /* RGIDW_MODID[153]:PWM0*/ + [146] = {0xE7792488U, 0x00000002U}, /* RGIDW_MODID[154]:PWM1*/ + [147] = {0xE779248CU, 0x00000002U}, /* RGIDW_MODID[155]:PWM2*/ + [148] = {0xE7792490U, 0x00000002U}, /* RGIDW_MODID[156]:PWM3*/ + [149] = {0xE7792494U, 0x00000002U}, /* RGIDW_MODID[157]:PWM4*/ + [150] = {0xE7792498U, 0x00000002U}, /* RGIDW_MODID[158]:PWM5*/ + [151] = {0xE779249CU, 0x00000002U}, /* RGIDW_MODID[159]:PWM6*/ + [152] = {0xE77924A0U, 0x00000002U}, /* RGIDW_MODID[160]:PWM7*/ + [153] = {0xE77924A4U, 0x00000002U}, /* RGIDW_MODID[161]:PWM8*/ + [154] = {0xE77924A8U, 0x00000002U}, /* RGIDW_MODID[162]:PWM9*/ + [155] = {0xE77924ACU, 0x00000002U}, /* RGIDW_MODID[163]:TPU0*/ + [156] = {0xFE672400U, 0x00000002U}, /* RGIDW_MODID[164]:ARVC10*/ + /* After setting */ /* RGIDW_MODID[165]:ARVC11*/ + /* After setting */ /* RGIDW_MODID[166]:ARVC12*/ + [157] = {0xFE67240CU, 0x00000001U}, /* RGIDW_MODID[167]:ARVC13*/ + [158] = {0xFE672410U, 0x00000002U}, /* RGIDW_MODID[168]:ARVC14*/ + [159] = {0xFE672414U, 0x00000001U}, /* RGIDW_MODID[169]:ARVC15*/ + [160] = {0xFE672418U, 0x00000002U}, /* RGIDW_MODID[170]:ARVC16*/ + [161] = {0xFE67241CU, 0x00000002U}, /* RGIDW_MODID[171]:ARVC17*/ + [162] = {0xFE672420U, 0x00000000U}, /* RGIDW_MODID[172]:ARVC18*/ + [163] = {0xFE672424U, 0x0000000AU}, /* RGIDW_MODID[173]:ECMVC1*/ + [164] = {0xFE672428U, 0x00000028U}, /* RGIDW_MODID[174]:FCPCS*/ + [165] = {0xFE67242CU, 0x00000028U}, /* RGIDW_MODID[175]:VCP4LC*/ + [166] = {0xFE672430U, 0x00000028U}, /* RGIDW_MODID[176]:VCP4LV*/ + [167] = {0xFEBD2400U, 0x00000002U}, /* RGIDW_MODID[177]:ARVI40*/ + /* After setting */ /* RGIDW_MODID[178]:ARVI41*/ + /* After setting */ /* RGIDW_MODID[179]:ARVI42*/ + [168] = {0xFEBD240CU, 0x00000001U}, /* RGIDW_MODID[180]:ARVI43*/ + [169] = {0xFEBD2410U, 0x00000002U}, /* RGIDW_MODID[181]:ARVI44*/ + [170] = {0xFEBD2414U, 0x00000001U}, /* RGIDW_MODID[182]:ARVI45*/ + [171] = {0xFEBD2418U, 0x00000002U}, /* RGIDW_MODID[183]:ARVI46*/ + [172] = {0xFEBD241CU, 0x00000002U}, /* RGIDW_MODID[184]:ARVI47*/ + [173] = {0xFEBD2420U, 0x00000000U}, /* RGIDW_MODID[185]:ARVI48*/ + [174] = {0xFEBD2424U, 0x0000000FU}, /* RGIDW_MODID[186]:DIS0*/ + [175] = {0xFEBD242CU, 0x0000000FU}, /* RGIDW_MODID[187]:DSC*/ + [176] = {0xFEBD2430U, 0x0000000EU}, /* RGIDW_MODID[188]:ECMVIO2*/ + [177] = {0xFEBD2434U, 0x0000000FU}, /* RGIDW_MODID[189]:FCPVD0*/ + [178] = {0xFEBD2438U, 0x0000000FU}, /* RGIDW_MODID[190]:FCPVD1*/ + [179] = {0xFEBD243CU, 0x0000004EU}, /* RGIDW_MODID[191]:VSPD0*/ + [180] = {0xFEBD2440U, 0x0000004EU}, /* RGIDW_MODID[192]:VSPD1*/ + [181] = {0xE6582400U, 0x0000000AU}, /* RGIDW_MODID[193]:CKMHSC*/ + [182] = {0xE6582404U, 0x0000000CU}, /* RGIDW_MODID[194]:AXIPCI001*/ + [183] = {0xE6582408U, 0x0000000CU}, /* RGIDW_MODID[195]:AXIPCI002*/ + [184] = {0xE658240CU, 0x0000000CU}, /* RGIDW_MODID[196]:AXIPCI003*/ + [185] = {0xE6582414U, 0x0000000CU}, /* RGIDW_MODID[197]:AXIPCI005*/ + [186] = {0xE6582418U, 0x0000000CU}, /* RGIDW_MODID[198]:AXIPCI006*/ + [187] = {0xE658241CU, 0x0000000CU}, /* RGIDW_MODID[199]:AXIPCI007*/ + [188] = {0xE6582420U, 0x0000000CU}, /* RGIDW_MODID[200]:AXIPCI008*/ + [189] = {0xE6582424U, 0x0000000CU}, /* RGIDW_MODID[201]:AXIPCI009*/ + [190] = {0xE6582428U, 0x0000000CU}, /* RGIDW_MODID[202]:AXIPCI010*/ + [191] = {0xE658242CU, 0x0000000CU}, /* RGIDW_MODID[203]:AXIPCI011*/ + [192] = {0xE6582430U, 0x0000000CU}, /* RGIDW_MODID[204]:AXIPCI012*/ + [193] = {0xE6582434U, 0x0000000CU}, /* RGIDW_MODID[205]:AXIPCI013*/ + [194] = {0xE6582438U, 0x0000000CU}, /* RGIDW_MODID[206]:AXIPCI014*/ + [195] = {0xE658243CU, 0x0000000CU}, /* RGIDW_MODID[207]:AXIPCI015*/ + [196] = {0xE6582440U, 0x0000000CU}, /* RGIDW_MODID[208]:AXIPCI100*/ + [197] = {0xE6582444U, 0x0000000CU}, /* RGIDW_MODID[209]:AXIPCI101*/ + [198] = {0xE6582448U, 0x0000000CU}, /* RGIDW_MODID[210]:AXIPCI102*/ + [199] = {0xE658244CU, 0x0000000CU}, /* RGIDW_MODID[211]:AXIPCI103*/ + [200] = {0xE6582450U, 0x0000000CU}, /* RGIDW_MODID[212]:AXIPCI104*/ + [201] = {0xE6582454U, 0x0000000CU}, /* RGIDW_MODID[213]:AXIPCI105*/ + [202] = {0xE6582458U, 0x0000000CU}, /* RGIDW_MODID[214]:AXIPCI106*/ + [203] = {0xE658245CU, 0x0000000CU}, /* RGIDW_MODID[215]:AXIPCI107*/ + [204] = {0xE6582460U, 0x0000000CU}, /* RGIDW_MODID[216]:AXIPCI108*/ + [205] = {0xE6582464U, 0x0000000CU}, /* RGIDW_MODID[217]:AXIPCI109*/ + [206] = {0xE6582468U, 0x0000000CU}, /* RGIDW_MODID[218]:AXIPCI110*/ + [207] = {0xE658246CU, 0x0000000CU}, /* RGIDW_MODID[219]:AXIPCI111*/ + [208] = {0xE6582470U, 0x0000000CU}, /* RGIDW_MODID[220]:AXIPCI112*/ + [209] = {0xE6582474U, 0x0000000CU}, /* RGIDW_MODID[221]:AXIPCI113*/ + [210] = {0xE6582478U, 0x0000000CU}, /* RGIDW_MODID[222]:AXIPCI114*/ + [211] = {0xE658247CU, 0x0000000CU}, /* RGIDW_MODID[223]:AXIPCI115*/ + [212] = {0xE6582484U, 0x0000000EU}, /* RGIDW_MODID[224]:GPTP*/ + [213] = {0xE6582488U, 0x0000004EU}, /* RGIDW_MODID[225]:IPMMUHC00*/ + [214] = {0xE65824F0U, 0x0000000EU}, /* RGIDW_MODID[226]:TSN0*/ + [215] = {0xE65824F4U, 0x0000000CU}, /* RGIDW_MODID[227]:AXIPCI000*/ + [216] = {0xE65824F8U, 0x0000000CU}, /* RGIDW_MODID[228]:AXIPCI004*/ + [217] = {0xE65824FCU, 0x0000004EU}, /* RGIDW_MODID[229]:IPMMUHC01*/ + [218] = {0xE6582500U, 0x0000004EU}, /* RGIDW_MODID[230]:AVB0*/ + [219] = {0xE6582504U, 0x0000004EU}, /* RGIDW_MODID[231]:AVB1*/ + [220] = {0xE6582508U, 0x0000004EU}, /* RGIDW_MODID[232]:AVB2*/ + [221] = {0xE658250CU, 0x0000004EU}, /* RGIDW_MODID[233]:IPMMUHC10*/ + [222] = {0xE6582510U, 0x0000004EU}, /* RGIDW_MODID[234]:IPMMUHC11*/ + [223] = {0xE6582514U, 0x0000004EU}, /* RGIDW_MODID[235]:IPMMUHC12*/ + [224] = {0xE6582518U, 0x0000004EU}, /* RGIDW_MODID[236]:IPMMUHC13*/ + [225] = {0xE658251CU, 0x0000000CU}, /* RGIDW_MODID[237]:PPHY0*/ + [226] = {0xE6582520U, 0x0000000CU}, /* RGIDW_MODID[238]:PPHY1*/ + [227] = {0xE6582524U, 0x0000004EU}, /* RGIDW_MODID[239]:IPMMUHC14*/ + [228] = {0xE6582528U, 0x0000004EU}, /* RGIDW_MODID[240]:IPMMUHC15*/ + [229] = {0xE658252CU, 0x0000000EU}, /* RGIDW_MODID[241]:FBAHSC*/ + [230] = {0xE6582530U, 0x0000004EU}, /* RGIDW_MODID[242]:IPMMUHC02*/ + [231] = {0xE6582538U, 0x0000000AU}, /* RGIDW_MODID[243]:ECMHSC*/ + [232] = {0xE658253CU, 0x00000002U}, /* RGIDW_MODID[244]:ARHC0*/ + /* After setting */ /* RGIDW_MODID[245]:ARHC1*/ + /* After setting */ /* RGIDW_MODID[246]:ARHC2*/ + [233] = {0xE6582548U, 0x00000001U}, /* RGIDW_MODID[247]:ARHC3*/ + [234] = {0xE658254CU, 0x00000002U}, /* RGIDW_MODID[248]:ARHC4*/ + [235] = {0xE6582550U, 0x00000001U}, /* RGIDW_MODID[249]:ARHC5*/ + [236] = {0xE6582554U, 0x00000002U}, /* RGIDW_MODID[250]:ARHC6*/ + [237] = {0xE6582558U, 0x00000002U}, /* RGIDW_MODID[251]:ARHC7*/ + [238] = {0xE658255CU, 0x00000000U}, /* RGIDW_MODID[252]:ARHC8*/ + [239] = {0xE6582560U, 0x0000004EU}, /* RGIDW_MODID[253]:IPMMUHC03*/ + [240] = {0xE6582564U, 0x0000004EU}, /* RGIDW_MODID[254]:IPMMUHC04*/ + [241] = {0xE6582568U, 0x0000004EU}, /* RGIDW_MODID[255]:IPMMUHC05*/ + [242] = {0xE658256CU, 0x0000004EU}, /* RGIDW_MODID[256]:IPMMUHC06*/ + [243] = {0xE6582570U, 0x0000004EU}, /* RGIDW_MODID[257]:IPMMUHC07*/ + [244] = {0xE6582574U, 0x0000004EU}, /* RGIDW_MODID[258]:IPMMUHC08*/ + [245] = {0xE6582578U, 0x0000004EU}, /* RGIDW_MODID[259]:IPMMUHC09*/ + [246] = {0xFF882400U, 0x00000002U}, /* RGIDW_MODID[260]:ARIMP00*/ + /* After setting */ /* RGIDW_MODID[261]:ARIMP01*/ + /* After setting */ /* RGIDW_MODID[262]:ARIMP02*/ + [247] = {0xFF88240CU, 0x00000001U}, /* RGIDW_MODID[263]:ARIMP03*/ + [248] = {0xFF882410U, 0x00000002U}, /* RGIDW_MODID[264]:ARIMP04*/ + [249] = {0xFF882414U, 0x0000004EU}, /* RGIDW_MODID[265]:AXIFBABUSIR0*/ + [250] = {0xFF882418U, 0x0000004EU}, /* RGIDW_MODID[266]:AXIFBABUSIR1*/ + [251] = {0xFF88241CU, 0x0000004EU}, /* RGIDW_MODID[267]:AXIFBABUSIR2*/ + [252] = {0xFF882420U, 0x0000004EU}, /* RGIDW_MODID[268]:AXIFBABUSIR3*/ + [253] = {0xFF882424U, 0x0000004EU}, /* RGIDW_MODID[269]:AXIFBABUSIR4*/ + [254] = {0xFF882428U, 0x0000004EU}, /* RGIDW_MODID[270]:AXIIMP0*/ + [255] = {0xFF88242CU, 0x0000004EU}, /* RGIDW_MODID[271]:CKMCNR*/ + [256] = {0xFF882430U, 0x0000004EU}, /* RGIDW_MODID[272]:CKMDSP*/ + [257] = {0xFF882434U, 0x00000001U}, /* RGIDW_MODID[273]:ARIMP05*/ + [258] = {0xFF882438U, 0x00000002U}, /* RGIDW_MODID[274]:ARIMP06*/ + [259] = {0xFF88243CU, 0x00000002U}, /* RGIDW_MODID[275]:ARIMP07*/ + [260] = {0xFF882440U, 0x00000000U}, /* RGIDW_MODID[276]:ARIMP08*/ + [261] = {0xFF882444U, 0x0000004EU}, /* RGIDW_MODID[277]:CKMIR*/ + [262] = {0xFF882448U, 0x0000000AU}, /* RGIDW_MODID[278]:ECMIR*/ + [263] = {0xFF88244CU, 0x0000000FU}, /* RGIDW_MODID[279]:DSPPS*/ + [264] = {0xFF882450U, 0x0000004EU}, /* RGIDW_MODID[280]:IPMMUIR1*/ + [265] = {0xFF882454U, 0x0000004EU}, /* RGIDW_MODID[281]:IPMMUIR0*/ + [266] = {0xFF882458U, 0x0000004EU}, /* RGIDW_MODID[282]:IPMMUIR10*/ + [267] = {0xFF88245CU, 0x0000004EU}, /* RGIDW_MODID[283]:IPMMUIR11*/ + [268] = {0xFF882460U, 0x0000004EU}, /* RGIDW_MODID[284]:IPMMUIR12*/ + [269] = {0xFF882464U, 0x0000004EU}, /* RGIDW_MODID[285]:IPMMUIR13*/ + [270] = {0xFF882468U, 0x0000004EU}, /* RGIDW_MODID[286]:IPMMUIR14*/ + [271] = {0xFF88246CU, 0x0000004EU}, /* RGIDW_MODID[287]:IPMMUIR15*/ + [272] = {0xFF882470U, 0x0000004EU}, /* RGIDW_MODID[288]:IPMMUIR2*/ + [273] = {0xFF882474U, 0x0000004EU}, /* RGIDW_MODID[289]:IPMMUIR3*/ + [274] = {0xFF882478U, 0x0000004EU}, /* RGIDW_MODID[290]:IPMMUIR4*/ + [275] = {0xFF88247CU, 0x0000004EU}, /* RGIDW_MODID[291]:IPMMUIR5*/ + [276] = {0xFF882480U, 0x0000004EU}, /* RGIDW_MODID[292]:IPMMUIR6*/ + [277] = {0xFF882484U, 0x0000004EU}, /* RGIDW_MODID[293]:IPMMUIR7*/ + [278] = {0xFF882488U, 0x0000004EU}, /* RGIDW_MODID[294]:IPMMUIR8*/ + [279] = {0xFF88248CU, 0x0000004EU}, /* RGIDW_MODID[295]:IPMMUIR9*/ + [280] = {0xFD812400U, 0x00000002U}, /* RGIDW_MODID[296]:ARPV0*/ + /* After setting */ /* RGIDW_MODID[297]:ARPV1*/ + [281] = {0xFD812408U, 0x0000002CU}, /* RGIDW_MODID[298]:AXIRGXS*/ + /* After setting */ /* RGIDW_MODID[299]:ARPV2*/ + [282] = {0xFD812410U, 0x00000001U}, /* RGIDW_MODID[300]:ARPV3*/ + [283] = {0xFD812414U, 0x00000002U}, /* RGIDW_MODID[301]:ARPV4*/ + [284] = {0xFD812418U, 0x00000001U}, /* RGIDW_MODID[302]:ARPV5*/ + [285] = {0xFD81241CU, 0x00000002U}, /* RGIDW_MODID[303]:ARPV6*/ + [286] = {0xFD812420U, 0x00000002U}, /* RGIDW_MODID[304]:ARPV7*/ + [287] = {0xFD812424U, 0x00000000U}, /* RGIDW_MODID[305]:ARPV8*/ + [288] = {0xFD812428U, 0x0000000AU}, /* RGIDW_MODID[306]:CKM3DG*/ + [289] = {0xFD81242CU, 0x0000000AU}, /* RGIDW_MODID[307]:ECM3DG*/ + [290] = {0xFD812430U, 0x0000000EU}, /* RGIDW_MODID[308]:FBAPVC*/ + [291] = {0xFD812434U, 0x0000000EU}, /* RGIDW_MODID[309]:FBAPVD0*/ + [292] = {0xFD812438U, 0x0000000EU}, /* RGIDW_MODID[310]:FBAPVD1*/ + [293] = {0xFD81243CU, 0x0000000EU}, /* RGIDW_MODID[311]:FBAPVD2*/ + [294] = {0xFD812440U, 0x0000000EU}, /* RGIDW_MODID[312]:FBAPVE*/ + [295] = {0xFD812444U, 0x0000004EU}, /* RGIDW_MODID[313]:IPMMUPV000*/ + [296] = {0xFD812448U, 0x0000004EU}, /* RGIDW_MODID[314]:IPMMUPV001*/ + [297] = {0xFD81244CU, 0x0000004EU}, /* RGIDW_MODID[315]:IPMMUPV010*/ + [298] = {0xFD812450U, 0x0000004EU}, /* RGIDW_MODID[316]:IPMMUPV011*/ + [299] = {0xFD812454U, 0x0000004EU}, /* RGIDW_MODID[317]:IPMMUPV012*/ + [300] = {0xFD812458U, 0x0000004EU}, /* RGIDW_MODID[318]:IPMMUPV013*/ + [301] = {0xFD81245CU, 0x0000004EU}, /* RGIDW_MODID[319]:IPMMUPV014*/ + [302] = {0xFD812460U, 0x0000004EU}, /* RGIDW_MODID[320]:IPMMUPV015*/ + [303] = {0xFD812464U, 0x0000004EU}, /* RGIDW_MODID[321]:IPMMUPV002*/ + [304] = {0xFD812468U, 0x0000004EU}, /* RGIDW_MODID[322]:IPMMUPV003*/ + [305] = {0xFD81246CU, 0x0000004EU}, /* RGIDW_MODID[323]:IPMMUPV004*/ + [306] = {0xFD812470U, 0x0000004EU}, /* RGIDW_MODID[324]:IPMMUPV005*/ + [307] = {0xFD812474U, 0x0000004EU}, /* RGIDW_MODID[325]:IPMMUPV006*/ + [308] = {0xFD812478U, 0x0000004EU}, /* RGIDW_MODID[326]:IPMMUPV007*/ + [309] = {0xFD81247CU, 0x0000004EU}, /* RGIDW_MODID[327]:IPMMUPV008*/ + [310] = {0xFD812480U, 0x0000004EU}, /* RGIDW_MODID[328]:IPMMUPV009*/ + [311] = {0xE6622400U, 0x00000002U}, /* RGIDW_MODID[329]:ARRC0*/ + /* After setting */ /* RGIDW_MODID[330]:ARRC1*/ + /* After setting */ /* RGIDW_MODID[331]:ARRC2*/ + [312] = {0xE662240CU, 0x00000001U}, /* RGIDW_MODID[332]:ARRC3*/ + [313] = {0xE6622410U, 0x00000002U}, /* RGIDW_MODID[333]:ARRC4*/ + [314] = {0xE6622414U, 0x00000001U}, /* RGIDW_MODID[334]:ARRC5*/ + [315] = {0xE6622418U, 0x00000002U}, /* RGIDW_MODID[335]:ARRC6*/ + [316] = {0xE662241CU, 0x00000002U}, /* RGIDW_MODID[336]:ARRC7*/ + [317] = {0xE6622420U, 0x00000000U}, /* RGIDW_MODID[337]:ARRC8*/ + [318] = {0xE6622424U, 0x00000009U}, /* RGIDW_MODID[338]:CR0*/ + [319] = {0xE6622428U, 0x0000004FU}, /* RGIDW_MODID[339]:ICUMX*/ + [320] = {0xE662242CU, 0x0000000AU}, /* RGIDW_MODID[340]:ECMRC*/ + [321] = {0xFFC32400U, 0x0000004EU}, /* RGIDW_MODID[341]:DMAWCRC0*/ + [322] = {0xFFC32404U, 0x0000004EU}, /* RGIDW_MODID[342]:DMAWCRC1*/ + [323] = {0xFFC32408U, 0x0000004EU}, /* RGIDW_MODID[343]:DMAWCRC2*/ + [324] = {0xFFC3240CU, 0x0000004EU}, /* RGIDW_MODID[344]:DMAWCRC3*/ + [325] = {0xFFC42400U, 0x0000000FU}, /* RGIDW_MODID[345]:ARMREG00*/ + [326] = {0xFFC42404U, 0x0000000CU}, /* RGIDW_MODID[346]:ARMREG01*/ + [327] = {0xFFC42408U, 0x00000000U}, /* RGIDW_MODID[347]:ARMREG10*/ + [328] = {0xFFC4240CU, 0x00000000U}, /* RGIDW_MODID[348]:ARMREG11*/ + [329] = {0xFFC42410U, 0x0000000AU}, /* RGIDW_MODID[349]:ARMREG12*/ + [330] = {0xFFC42414U, 0x0000000FU}, /* RGIDW_MODID[350]:ARMREG13*/ + [331] = {0xFFC42418U, 0x0000000AU}, /* RGIDW_MODID[351]:ARMREG14*/ + [332] = {0xFFC4241CU, 0x00000003U}, /* RGIDW_MODID[352]:AXICR52SS0*/ + [333] = {0xFFC42420U, 0x0000000EU}, /* RGIDW_MODID[353]:AXICSD0*/ + [334] = {0xFFC42424U, 0x0000000EU}, /* RGIDW_MODID[354]:AXIINTAP0*/ + [335] = {0xFFC42428U, 0x00000000U}, /* RGIDW_MODID[355]:AXIINTAP1*/ + [336] = {0xFFC42430U, 0x0000000FU}, /* RGIDW_MODID[356]:AXISYSRAM0*/ + [337] = {0xFFC42434U, 0x0000004FU}, /* RGIDW_MODID[357]:AXISYSRAM1*/ + [338] = {0xFFC42438U, 0x00000000U}, /* RGIDW_MODID[358]:ARGREG15*/ + [339] = {0xFFC4243CU, 0x00000000U}, /* RGIDW_MODID[359]:ARMREG2*/ + [340] = {0xFFC42440U, 0x00000000U}, /* RGIDW_MODID[360]:ARMREG3*/ + [341] = {0xFFC42444U, 0x00000000U}, /* RGIDW_MODID[361]:ARMREG4*/ + [342] = {0xFFC42448U, 0x0000000FU}, /* RGIDW_MODID[362]:ARMREG5*/ + [343] = {0xFFC4244CU, 0x0000000AU}, /* RGIDW_MODID[363]:ARMREG6*/ + [344] = {0xFFC42450U, 0x00000000U}, /* RGIDW_MODID[364]:ARMREG7*/ + [345] = {0xFFC42454U, 0x0000000CU}, /* RGIDW_MODID[365]:ARMREG8*/ + [346] = {0xFFC42458U, 0x0000000CU}, /* RGIDW_MODID[366]:ARMREG9*/ + [347] = {0xFFC4245CU, 0x00000002U}, /* RGIDW_MODID[367]:ARRD0*/ + /* After setting */ /* RGIDW_MODID[368]:ARRD1*/ + /* After setting */ /* RGIDW_MODID[369]:ARRD2*/ + [348] = {0xFFC42468U, 0x00000001U}, /* RGIDW_MODID[370]:ARRD3*/ + [349] = {0xFFC4246CU, 0x00000002U}, /* RGIDW_MODID[371]:ARRD4*/ + [350] = {0xFFC42470U, 0x00000001U}, /* RGIDW_MODID[372]:ARRD5*/ + [351] = {0xFFC42474U, 0x00000002U}, /* RGIDW_MODID[373]:ARRD6*/ + [352] = {0xFFC42478U, 0x00000002U}, /* RGIDW_MODID[374]:ARRD7*/ + [353] = {0xFFC4247CU, 0x00000000U}, /* RGIDW_MODID[375]:ARRD8*/ + [354] = {0xFFC42480U, 0x00000002U}, /* RGIDW_MODID[376]:ARRT0*/ + /* After setting */ /* RGIDW_MODID[377]:ARRT1*/ + /* After setting */ /* RGIDW_MODID[378]:ARRT2*/ + [355] = {0xFFC4248CU, 0x00000001U}, /* RGIDW_MODID[379]:ARRT3*/ + [356] = {0xFFC42490U, 0x00000002U}, /* RGIDW_MODID[380]:ARRT4*/ + [357] = {0xFFC42494U, 0x00000001U}, /* RGIDW_MODID[381]:ARRT5*/ + [358] = {0xFFC42498U, 0x00000002U}, /* RGIDW_MODID[382]:ARRT6*/ + [359] = {0xFFC4249CU, 0x00000002U}, /* RGIDW_MODID[383]:ARRT7*/ + [360] = {0xFFC424A0U, 0x00000000U}, /* RGIDW_MODID[384]:ARRT8*/ + [361] = {0xFFC424A4U, 0x0000000AU}, /* RGIDW_MODID[385]:CKMRT*/ + [362] = {0xFFC424A8U, 0x0000004EU}, /* RGIDW_MODID[386]:CRC0*/ + [363] = {0xFFC424ACU, 0x0000004EU}, /* RGIDW_MODID[387]:CRC1*/ + [364] = {0xFFC424B0U, 0x0000004EU}, /* RGIDW_MODID[388]:CRC2*/ + [365] = {0xFFC424B4U, 0x0000004EU}, /* RGIDW_MODID[389]:CRC3*/ + [366] = {0xFFC424B8U, 0x0000000EU}, /* RGIDW_MODID[390]:CSD*/ + [367] = {0xFFC424BCU, 0x0000000EU}, /* RGIDW_MODID[391]:ECM*/ + [368] = {0xFFC424C0U, 0x0000000AU}, /* RGIDW_MODID[392]:ECMRT*/ + [369] = {0xFFC424C4U, 0x0000000EU}, /* RGIDW_MODID[393]:FBACR52*/ + [370] = {0xFFC424C8U, 0x0000000EU}, /* RGIDW_MODID[394]:FBART*/ + [371] = {0xFFC424CCU, 0x0000000EU}, /* RGIDW_MODID[395]:INTTP*/ + [372] = {0xFFC424D0U, 0x0000004EU}, /* RGIDW_MODID[396]:IPMMURT000*/ + [373] = {0xFFC424D4U, 0x0000004EU}, /* RGIDW_MODID[397]:IPMMURT100*/ + [374] = {0xFFC424D8U, 0x0000004EU}, /* RGIDW_MODID[398]:KCRC4*/ + [375] = {0xFFC424DCU, 0x0000004EU}, /* RGIDW_MODID[399]:KCRC5*/ + [376] = {0xFFC424E0U, 0x0000004EU}, /* RGIDW_MODID[400]:KCRC6*/ + [377] = {0xFFC424E4U, 0x0000004EU}, /* RGIDW_MODID[401]:KCRC7*/ + [378] = {0xFFC424E8U, 0x0000004FU}, /* RGIDW_MODID[402]:MFI00*/ + [379] = {0xFFC424ECU, 0x0000004EU}, /* RGIDW_MODID[403]:MFI01*/ + [380] = {0xFFC424F0U, 0x0000004EU}, /* RGIDW_MODID[404]:MFI10*/ + [381] = {0xFFC424F4U, 0x0000004EU}, /* RGIDW_MODID[405]:MFI02*/ + [382] = {0xFFC424F8U, 0x0000004EU}, /* RGIDW_MODID[406]:MFI03*/ + [383] = {0xFFC424FCU, 0x0000004EU}, /* RGIDW_MODID[407]:MFI04*/ + [384] = {0xFFC42500U, 0x00000000U}, /* RGIDW_MODID[408]:MFI05*/ + [385] = {0xFFC42504U, 0x00000000U}, /* RGIDW_MODID[409]:MFI06*/ + [386] = {0xFFC42508U, 0x00000000U}, /* RGIDW_MODID[410]:MFI07*/ + [387] = {0xFFC4250CU, 0x00000000U}, /* RGIDW_MODID[411]:MFI08*/ + [388] = {0xFFC42510U, 0x0000004EU}, /* RGIDW_MODID[412]:MFI09*/ + [389] = {0xFFC42514U, 0x0000004FU}, /* RGIDW_MODID[413]:MFI15*/ + [390] = {0xFFC42518U, 0x0000000AU}, /* RGIDW_MODID[414]:CKMCR52*/ + [391] = {0xFFC4251CU, 0x0000004BU}, /* RGIDW_MODID[415]:RTDM0P*/ + [392] = {0xFFC42520U, 0x0000000AU}, /* RGIDW_MODID[416]:ECMRD*/ + [393] = {0xFFC42524U, 0x0000004BU}, /* RGIDW_MODID[417]:RTDM1P*/ + [394] = {0xFFC4252CU, 0x0000004BU}, /* RGIDW_MODID[418]:RTDM2P*/ + [395] = {0xFFC42530U, 0x0000000BU}, /* RGIDW_MODID[419]:SYSRAM10*/ + [396] = {0xFFC42534U, 0x0000004BU}, /* RGIDW_MODID[420]:RTDM3P*/ + [397] = {0xFFC42538U, 0x00000001U}, /* RGIDW_MODID[421]:SYSRAM00*/ + [398] = {0xFFC4253CU, 0x0000004EU}, /* RGIDW_MODID[422]:TSIPL0*/ + [399] = {0xFFC42540U, 0x0000004EU}, /* RGIDW_MODID[423]:TSIPL1*/ + [400] = {0xFFC42544U, 0x0000004EU}, /* RGIDW_MODID[424]:TSIPL2*/ + [401] = {0xFFC42548U, 0x0000004EU}, /* RGIDW_MODID[425]:TSIPL3*/ + [402] = {0xFFC4254CU, 0x0000004EU}, /* RGIDW_MODID[426]:TSIPL4*/ + [403] = {0xFFC42550U, 0x0000004EU}, /* RGIDW_MODID[427]:TSIPL5*/ + [404] = {0xFFC42554U, 0x0000004EU}, /* RGIDW_MODID[428]:TSIPL6*/ + [405] = {0xFFC42558U, 0x0000004EU}, /* RGIDW_MODID[429]:TSIPL7*/ + [406] = {0xFFC4255CU, 0x0000004EU}, /* RGIDW_MODID[430]:WCRC0*/ + [407] = {0xFFC42560U, 0x0000004EU}, /* RGIDW_MODID[431]:WCRC1*/ + [408] = {0xFFC42564U, 0x0000004EU}, /* RGIDW_MODID[432]:WCRC2*/ + [409] = {0xFFC42568U, 0x0000004EU}, /* RGIDW_MODID[433]:WCRC3*/ + [410] = {0xFFC42580U, 0x0000004EU}, /* RGIDW_MODID[434]:MFI11*/ + [411] = {0xFFC42584U, 0x00000000U}, /* RGIDW_MODID[435]:MFI12*/ + [412] = {0xFFC42588U, 0x00000000U}, /* RGIDW_MODID[436]:MFI13*/ + [413] = {0xFFC4258CU, 0x00000000U}, /* RGIDW_MODID[437]:MFI14*/ + [414] = {0xFFC42590U, 0x0000004EU}, /* RGIDW_MODID[438]:IPMMURT001*/ + [415] = {0xFFC42594U, 0x0000004EU}, /* RGIDW_MODID[439]:IPMMURT010*/ + [416] = {0xFFC42598U, 0x0000004EU}, /* RGIDW_MODID[440]:IPMMURT011*/ + [417] = {0xFFC4259CU, 0x0000004EU}, /* RGIDW_MODID[441]:IPMMURT012*/ + [418] = {0xFFC425A0U, 0x0000004EU}, /* RGIDW_MODID[442]:IPMMURT013*/ + [419] = {0xFFC425A4U, 0x0000004EU}, /* RGIDW_MODID[443]:IPMMURT014*/ + [420] = {0xFFC425A8U, 0x0000004EU}, /* RGIDW_MODID[444]:IPMMURT015*/ + [421] = {0xFFC425ACU, 0x0000004EU}, /* RGIDW_MODID[445]:IPMMURT002*/ + [422] = {0xFFC425B0U, 0x0000004EU}, /* RGIDW_MODID[446]:IPMMURT003*/ + [423] = {0xFFC425B4U, 0x0000004EU}, /* RGIDW_MODID[447]:IPMMURT004*/ + [424] = {0xFFC425B8U, 0x0000004EU}, /* RGIDW_MODID[448]:IPMMURT005*/ + [425] = {0xFFC425BCU, 0x0000004EU}, /* RGIDW_MODID[449]:IPMMURT006*/ + [426] = {0xFFC425C0U, 0x0000004EU}, /* RGIDW_MODID[450]:IPMMURT007*/ + [427] = {0xFFC425C4U, 0x0000004EU}, /* RGIDW_MODID[451]:IPMMURT008*/ + [428] = {0xFFC425C8U, 0x0000004EU}, /* RGIDW_MODID[452]:IPMMURT009*/ + [429] = {0xFFC425CCU, 0x0000004EU}, /* RGIDW_MODID[453]:IPKMURT101*/ + [430] = {0xFFC425D0U, 0x0000004EU}, /* RGIDW_MODID[454]:IPMMURT110*/ + [431] = {0xFFC425D4U, 0x0000004EU}, /* RGIDW_MODID[455]:IPMMURT111*/ + [432] = {0xFFC425D8U, 0x0000004EU}, /* RGIDW_MODID[456]:IPMMURT112*/ + [433] = {0xFFC425DCU, 0x0000004EU}, /* RGIDW_MODID[457]:IPMMURT113*/ + [434] = {0xFFC425E0U, 0x0000004EU}, /* RGIDW_MODID[458]:IPMMURT114*/ + [435] = {0xFFC425E4U, 0x0000004EU}, /* RGIDW_MODID[459]:IPMMURT115*/ + [436] = {0xFFC425E8U, 0x0000004EU}, /* RGIDW_MODID[460]:IPMMURT102*/ + [437] = {0xFFC425ECU, 0x0000004EU}, /* RGIDW_MODID[461]:IPMMURT103*/ + [438] = {0xFFC425F0U, 0x0000004EU}, /* RGIDW_MODID[462]:IPMMURT104*/ + [439] = {0xFFC425F4U, 0x0000004EU}, /* RGIDW_MODID[463]:IPMMURT105*/ + [440] = {0xFFC425F8U, 0x0000004EU}, /* RGIDW_MODID[464]:IPMMURT106*/ + [441] = {0xFFC425FCU, 0x0000004EU}, /* RGIDW_MODID[465]:IPMMURT107*/ + [442] = {0xFFC42600U, 0x0000004BU}, /* RGIDW_MODID[466]:RTDM000*/ + [443] = {0xFFC42604U, 0x0000004BU}, /* RGIDW_MODID[467]:RTDM001*/ + [444] = {0xFFC42608U, 0x0000004BU}, /* RGIDW_MODID[468]:RTDM010*/ + [445] = {0xFFC4260CU, 0x0000004BU}, /* RGIDW_MODID[469]:RTDM011*/ + [446] = {0xFFC42610U, 0x0000004BU}, /* RGIDW_MODID[470]:RTDM012*/ + [447] = {0xFFC42614U, 0x0000004BU}, /* RGIDW_MODID[471]:RTDM013*/ + [448] = {0xFFC42618U, 0x0000004BU}, /* RGIDW_MODID[472]:RTDM014*/ + [449] = {0xFFC4261CU, 0x0000004BU}, /* RGIDW_MODID[473]:RTDM015*/ + [450] = {0xFFC42620U, 0x0000004BU}, /* RGIDW_MODID[474]:RTDM002*/ + [451] = {0xFFC42624U, 0x0000004BU}, /* RGIDW_MODID[475]:RTDM003*/ + [452] = {0xFFC42628U, 0x0000004BU}, /* RGIDW_MODID[476]:RTDM004*/ + [453] = {0xFFC4262CU, 0x0000004BU}, /* RGIDW_MODID[477]:RTDM005*/ + [454] = {0xFFC42630U, 0x0000004BU}, /* RGIDW_MODID[478]:RTDM006*/ + [455] = {0xFFC42634U, 0x0000004BU}, /* RGIDW_MODID[479]:RTDM007*/ + [456] = {0xFFC42638U, 0x0000004BU}, /* RGIDW_MODID[480]:RTDM008*/ + [457] = {0xFFC4263CU, 0x0000004BU}, /* RGIDW_MODID[481]:RTDM009*/ + [458] = {0xFFC42640U, 0x0000004BU}, /* RGIDW_MODID[482]:RTDM100*/ + [459] = {0xFFC42644U, 0x0000004BU}, /* RGIDW_MODID[483]:RTDM101*/ + [460] = {0xFFC42648U, 0x0000004BU}, /* RGIDW_MODID[484]:RTDM110*/ + [461] = {0xFFC4264CU, 0x0000004BU}, /* RGIDW_MODID[485]:RTDM111*/ + [462] = {0xFFC42650U, 0x0000004BU}, /* RGIDW_MODID[486]:RTDM112*/ + [463] = {0xFFC42654U, 0x0000004BU}, /* RGIDW_MODID[487]:RTDM113*/ + [464] = {0xFFC42658U, 0x0000004BU}, /* RGIDW_MODID[488]:RTDM114*/ + [465] = {0xFFC4265CU, 0x0000004BU}, /* RGIDW_MODID[489]:RTDM115*/ + [466] = {0xFFC42660U, 0x0000004BU}, /* RGIDW_MODID[490]:RTDM102*/ + [467] = {0xFFC42664U, 0x0000004BU}, /* RGIDW_MODID[491]:RTDM103*/ + [468] = {0xFFC42668U, 0x0000004BU}, /* RGIDW_MODID[492]:RTDM104*/ + [469] = {0xFFC4266CU, 0x0000004BU}, /* RGIDW_MODID[493]:RTDM105*/ + [470] = {0xFFC42670U, 0x0000004BU}, /* RGIDW_MODID[494]:RTDM106*/ + [471] = {0xFFC42674U, 0x0000004BU}, /* RGIDW_MODID[495]:RTDM107*/ + [472] = {0xFFC42678U, 0x0000004BU}, /* RGIDW_MODID[496]:RTDM108*/ + [473] = {0xFFC4267CU, 0x0000004BU}, /* RGIDW_MODID[497]:RTDM109*/ + [474] = {0xFFC42680U, 0x0000004BU}, /* RGIDW_MODID[498]:RTDM200*/ + [475] = {0xFFC42684U, 0x0000004BU}, /* RGIDW_MODID[499]:RTDM201*/ + [476] = {0xFFC42688U, 0x0000004BU}, /* RGIDW_MODID[500]:RTDM210*/ + [477] = {0xFFC4268CU, 0x0000004BU}, /* RGIDW_MODID[501]:RTDM211*/ + [478] = {0xFFC42690U, 0x0000004BU}, /* RGIDW_MODID[502]:RTDM212*/ + [479] = {0xFFC42694U, 0x0000004BU}, /* RGIDW_MODID[503]:RTDM213*/ + [480] = {0xFFC42698U, 0x0000004BU}, /* RGIDW_MODID[504]:RTDM214*/ + [481] = {0xFFC4269CU, 0x0000004BU}, /* RGIDW_MODID[505]:RTDM215*/ + [482] = {0xFFC426A0U, 0x0000004BU}, /* RGIDW_MODID[506]:RTDM202*/ + [483] = {0xFFC426A4U, 0x0000004BU}, /* RGIDW_MODID[507]:RTDM203*/ + [484] = {0xFFC426A8U, 0x0000004BU}, /* RGIDW_MODID[508]:RTDM204*/ + [485] = {0xFFC426ACU, 0x0000004BU}, /* RGIDW_MODID[509]:RTDM205*/ + [486] = {0xFFC426B0U, 0x0000004BU}, /* RGIDW_MODID[510]:RTDM206*/ + [487] = {0xFFC426B4U, 0x0000004BU}, /* RGIDW_MODID[511]:RTDM207*/ + [488] = {0xFFC426B8U, 0x0000004BU}, /* RGIDW_MODID[512]:RTDM208*/ + [489] = {0xFFC426BCU, 0x0000004BU}, /* RGIDW_MODID[513]:RTDM209*/ + [490] = {0xFFC426C0U, 0x0000004BU}, /* RGIDW_MODID[514]:RTDM300*/ + [491] = {0xFFC426C4U, 0x0000004BU}, /* RGIDW_MODID[515]:RTDM301*/ + [492] = {0xFFC426C8U, 0x0000004BU}, /* RGIDW_MODID[516]:RTDM310*/ + [493] = {0xFFC426CCU, 0x0000004BU}, /* RGIDW_MODID[517]:RTDM311*/ + [494] = {0xFFC426D0U, 0x0000004BU}, /* RGIDW_MODID[518]:RTDM312*/ + [495] = {0xFFC426D4U, 0x0000004BU}, /* RGIDW_MODID[519]:RTDM313*/ + [496] = {0xFFC426D8U, 0x0000004BU}, /* RGIDW_MODID[520]:RTDM314*/ + [497] = {0xFFC426DCU, 0x0000004BU}, /* RGIDW_MODID[521]:RTDM315*/ + [498] = {0xFFC426E0U, 0x0000004BU}, /* RGIDW_MODID[522]:RTDM302*/ + [499] = {0xFFC426E4U, 0x0000004BU}, /* RGIDW_MODID[523]:RTDM303*/ + [500] = {0xFFC426E8U, 0x0000004BU}, /* RGIDW_MODID[524]:RTDM304*/ + [501] = {0xFFC426ECU, 0x0000004BU}, /* RGIDW_MODID[525]:RTDM305*/ + [502] = {0xFFC426F0U, 0x0000004BU}, /* RGIDW_MODID[526]:RTDM306*/ + [503] = {0xFFC426F4U, 0x0000004BU}, /* RGIDW_MODID[527]:RTDM307*/ + [504] = {0xFFC426F8U, 0x0000004BU}, /* RGIDW_MODID[528]:RTDM308*/ + [505] = {0xFFC426FCU, 0x0000004BU}, /* RGIDW_MODID[529]:RTDM309*/ + [506] = {0xFFC42700U, 0x0000004EU}, /* RGIDW_MODID[530]:IPMMURT108*/ + [507] = {0xFFC42704U, 0x0000004EU}, /* RGIDW_MODID[531]:IPMMURT109*/ + [508] = {0xFFC42708U, 0x00000001U}, /* RGIDW_MODID[532]:SYSRAM01*/ + [509] = {0xFFC4270CU, 0x0000000BU}, /* RGIDW_MODID[533]:SYSRAM02*/ + [510] = {0xFFC42710U, 0x00000001U}, /* RGIDW_MODID[534]:SYSRAM03*/ + [511] = {0xFFC42714U, 0x00000001U}, /* RGIDW_MODID[535]:SYSRAM04*/ + [512] = {0xFFC42718U, 0x00000001U}, /* RGIDW_MODID[536]:SYSRAM05*/ + [513] = {0xFFC4271CU, 0x00000001U}, /* RGIDW_MODID[537]:SYSRAM06*/ + [514] = {0xFFC42720U, 0x00000000U}, /* RGIDW_MODID[538]:SYSRAM07*/ + [515] = {0xFFC42724U, 0x0000000BU}, /* RGIDW_MODID[539]:SYSRAM11*/ + [516] = {0xFFC42728U, 0x0000000AU}, /* RGIDW_MODID[540]:SYSRAM12*/ + [517] = {0xFFC4272CU, 0x0000000BU}, /* RGIDW_MODID[541]:SYSRAM13*/ + [518] = {0xFFC42730U, 0x0000000BU}, /* RGIDW_MODID[542]:SYSRAM14*/ + [519] = {0xFFC42734U, 0x0000000BU}, /* RGIDW_MODID[543]:SYSRAM15*/ + [520] = {0xFFC42738U, 0x0000000BU}, /* RGIDW_MODID[544]:SYSRAM16*/ + [521] = {0xFFC4273CU, 0x00000000U}, /* RGIDW_MODID[545]:SYSRAM17*/ + [522] = {0xFFC42760U, 0x00000002U}, /* RGIDW_MODID[546]:BKBUF*/ + [523] = {0xFFC42764U, 0x00000003U}, /* RGIDW_MODID[547]:AXICR52SS1*/ + [524] = {0xFFC42768U, 0x00000003U}, /* RGIDW_MODID[548]:AXICR52SS2*/ + [525] = {0xFF862400U, 0x00000002U}, /* RGIDW_MODID[549]:ARSC0*/ + /* After setting */ /* RGIDW_MODID[550]:ARSC1*/ + /* After setting */ /* RGIDW_MODID[551]:ARSC2*/ + [526] = {0xFF86240CU, 0x00000001U}, /* RGIDW_MODID[552]:ARSC3*/ + [527] = {0xFF862410U, 0x00000002U}, /* RGIDW_MODID[553]:ARSC4*/ + [528] = {0xFF862414U, 0x00000001U}, /* RGIDW_MODID[554]:ARSC5*/ + [529] = {0xFF862418U, 0x00000002U}, /* RGIDW_MODID[555]:ARSC6*/ + [530] = {0xFF86241CU, 0x00000002U}, /* RGIDW_MODID[556]:ARSC7*/ + [531] = {0xFF862420U, 0x00000000U}, /* RGIDW_MODID[557]:ARSC8*/ + [532] = {0xFF862424U, 0x00000002U}, /* RGIDW_MODID[558]:ARSTM0*/ + /* After setting */ /* RGIDW_MODID[559]:ARSTM1*/ + [533] = {0xFF86242CU, 0x0000000EU}, /* RGIDW_MODID[560]:CSD1S*/ + [534] = {0xFF862430U, 0x0000000EU}, /* RGIDW_MODID[561]:AXIFBABUSTOP0*/ + [535] = {0xFF862434U, 0x0000000EU}, /* RGIDW_MODID[562]:AXIFBABUSTOP1*/ + /* After setting */ /* RGIDW_MODID[563]:ARSTM2*/ + [536] = {0xFF86243CU, 0x00000001U}, /* RGIDW_MODID[564]:ARSTM3*/ + [537] = {0xFF862440U, 0x00000002U}, /* RGIDW_MODID[565]:ARSTM4*/ + [538] = {0xFF862444U, 0x00000001U}, /* RGIDW_MODID[566]:ARSTM5*/ + [539] = {0xFF862448U, 0x00000002U}, /* RGIDW_MODID[567]:ARSTM6*/ + [540] = {0xFF86244CU, 0x00000002U}, /* RGIDW_MODID[568]:ARSTM7*/ + [541] = {0xFF862450U, 0x00000000U}, /* RGIDW_MODID[569]:ARSTM8*/ + [542] = {0xFF862454U, 0x0000000AU}, /* RGIDW_MODID[570]:ECMTOP*/ + [543] = {0xFF862458U, 0x0000000EU}, /* RGIDW_MODID[571]:FBA*/ + [544] = {0xFF86245CU, 0x0000000EU}, /* RGIDW_MODID[572]:FBC*/ + [545] = {0xFF862460U, 0x0000000CU}, /* RGIDW_MODID[573]:AXICCI00*/ + [546] = {0xFF862464U, 0x0000000EU}, /* RGIDW_MODID[574]:AXICCI01*/ + [547] = {0xFF862468U, 0x0000000CU}, /* RGIDW_MODID[575]:AXICCI10*/ + [548] = {0xFF86246CU, 0x0000000CU}, /* RGIDW_MODID[576]:AXICCI11*/ + [549] = {0xFF862470U, 0x0000000CU}, /* RGIDW_MODID[577]:AXICCI12*/ + [550] = {0xFF862474U, 0x0000000CU}, /* RGIDW_MODID[578]:AXICCI13*/ + [551] = {0xFF862478U, 0x0000000CU}, /* RGIDW_MODID[579]:AXICCI14*/ + [552] = {0xFF86247CU, 0x0000000CU}, /* RGIDW_MODID[580]:AXICCI15*/ + [553] = {0xFF862480U, 0x0000000EU}, /* RGIDW_MODID[581]:AXICCI2*/ + [554] = {0xFF862484U, 0x0000000CU}, /* RGIDW_MODID[582]:AXICCI3*/ + [555] = {0xFF862488U, 0x0000000CU}, /* RGIDW_MODID[583]:AXICCI4*/ + [556] = {0xFF86248CU, 0x0000000CU}, /* RGIDW_MODID[584]:AXICCI5*/ + [557] = {0xFF862490U, 0x0000000CU}, /* RGIDW_MODID[585]:AXICCI6*/ + [558] = {0xFF862494U, 0x0000000CU}, /* RGIDW_MODID[586]:AXICCI7*/ + [559] = {0xFF862498U, 0x0000000CU}, /* RGIDW_MODID[587]:AXICCI8*/ + [560] = {0xFF86249CU, 0x00000009U}, /* RGIDW_MODID[588]:AXICCI9*/ + [561] = {0xFF8624A0U, 0x0000000AU}, /* RGIDW_MODID[589]:ECMSTM*/ + [562] = {0xE7782400U, 0x0000002CU}, /* RGIDW_MODID[590]:DMASSI00*/ + [563] = {0xE7782404U, 0x0000002CU}, /* RGIDW_MODID[591]:DMASSI01*/ + [564] = {0xE7782408U, 0x0000002CU}, /* RGIDW_MODID[592]:DMASSI02*/ + [565] = {0xE778240CU, 0x0000002CU}, /* RGIDW_MODID[593]:DMASSI03*/ + [566] = {0xE7782410U, 0x0000002CU}, /* RGIDW_MODID[594]:DMASSI04*/ + [567] = {0xE7782414U, 0x0000004EU}, /* RGIDW_MODID[595]:DMAI2C0*/ + [568] = {0xE7782418U, 0x0000004EU}, /* RGIDW_MODID[596]:DMAI2C1*/ + [569] = {0xE778241CU, 0x0000004EU}, /* RGIDW_MODID[597]:DMAI2C2*/ + [570] = {0xE7782420U, 0x0000004EU}, /* RGIDW_MODID[598]:DMAI2C3*/ + [571] = {0xE7782424U, 0x0000004EU}, /* RGIDW_MODID[599]:DMAI2C4*/ + [572] = {0xE7782428U, 0x0000004EU}, /* RGIDW_MODID[600]:DMAI2C5*/ + [573] = {0xE778242CU, 0x0000002CU}, /* RGIDW_MODID[601]:DMASSI05*/ + [574] = {0xE7782430U, 0x0000002CU}, /* RGIDW_MODID[602]:DMASSI06*/ + [575] = {0xE7782434U, 0x0000002CU}, /* RGIDW_MODID[603]:DMASSI07*/ + [576] = {0xE67C2400U, 0x00000002U}, /* RGIDW_MODID[604]:ARMM*/ + /* After setting */ /* RGIDW_MODID[605]:AXIARNMM*/ + [577] = {0xE67C2408U, 0x00000002U}, /* RGIDW_MODID[606]:ARSM0*/ + /* After setting */ /* RGIDW_MODID[607]:ARSM1*/ + /* After setting */ /* RGIDW_MODID[608]:ARSM2*/ + [578] = {0xE67C2414U, 0x0000000FU}, /* RGIDW_MODID[609]:AXIQOS0*/ + [579] = {0xE67C2418U, 0x0000000FU}, /* RGIDW_MODID[610]:AXIQOS1*/ + [580] = {0xE67C241CU, 0x0000000FU}, /* RGIDW_MODID[611]:AXIQOS2*/ + [581] = {0xE67C2420U, 0x0000000FU}, /* RGIDW_MODID[612]:AXIQOS3*/ + [582] = {0xE67C2424U, 0x0000000FU}, /* RGIDW_MODID[613]:AXIQOS4*/ + [583] = {0xE67C2428U, 0x0000000FU}, /* RGIDW_MODID[614]:AXIQOS5*/ + [584] = {0xE67C242CU, 0x0000000FU}, /* RGIDW_MODID[615]:AXIQOS6*/ + [585] = {0xE67C2430U, 0x0000000FU}, /* RGIDW_MODID[616]:AXIQOS7*/ + [586] = {0xE67C2434U, 0x00000001U}, /* RGIDW_MODID[617]:ARSM3*/ + [587] = {0xE67C2438U, 0x00000002U}, /* RGIDW_MODID[618]:ARSM4*/ + [588] = {0xE67C243CU, 0x00000001U}, /* RGIDW_MODID[619]:ARSM5*/ + [589] = {0xE67C2440U, 0x00000002U}, /* RGIDW_MODID[620]:ARSM6*/ + [590] = {0xE67C2444U, 0x00000002U}, /* RGIDW_MODID[621]:ARSM7*/ + [591] = {0xE67C2448U, 0x00000000U}, /* RGIDW_MODID[622]:ARSM8*/ + [592] = {0xE67C244CU, 0x0000000BU}, /* RGIDW_MODID[623]:AXMM0*/ + [593] = {0xE67C2450U, 0x0000000BU}, /* RGIDW_MODID[624]:AXMM1*/ + [594] = {0xE67C2454U, 0x00000000U}, /* RGIDW_MODID[625]:AXMMPMON*/ + [595] = {0xE67C2458U, 0x0000000AU}, /* RGIDW_MODID[626]:CKMMM*/ + [596] = {0xE67C245CU, 0x0000000AU}, /* RGIDW_MODID[627]:ECMMM*/ + [597] = {0xE67C2460U, 0x0000000EU}, /* RGIDW_MODID[628]:FBADBSC0*/ + [598] = {0xE67C2464U, 0x0000000EU}, /* RGIDW_MODID[629]:FBADBSC1*/ + [599] = {0xE67C2468U, 0x0000000EU}, /* RGIDW_MODID[630]:FBAMM*/ + [600] = {0xE67C246CU, 0x0000004EU}, /* RGIDW_MODID[631]:IPMMUMM00*/ + [601] = {0xE67C2470U, 0x0000000FU}, /* RGIDW_MODID[632]:DBS0A0*/ + [602] = {0xE67C2474U, 0x0000000AU}, /* RGIDW_MODID[633]:DBS0A1*/ + [603] = {0xE67C2478U, 0x0000000FU}, /* RGIDW_MODID[634]:DBS1A0*/ + [604] = {0xE67C247CU, 0x0000000AU}, /* RGIDW_MODID[635]:DBS1A1*/ + [605] = {0xE67C2480U, 0x0000000FU}, /* RGIDW_MODID[636]:AXCIDBS*/ + [606] = {0xE67C2484U, 0x00000009U}, /* RGIDW_MODID[637]:FCPRC*/ + [607] = {0xE67C2488U, 0x0000000FU}, /* RGIDW_MODID[638]:DBS0D0*/ + [608] = {0xE67C248CU, 0x0000000AU}, /* RGIDW_MODID[639]:DBS0D1*/ + [609] = {0xE67C2490U, 0x0000000FU}, /* RGIDW_MODID[640]:DBS1D0*/ + [610] = {0xE67C2494U, 0x0000000AU}, /* RGIDW_MODID[641]:DBS1D1*/ + [611] = {0xE67C2498U, 0x0000000EU}, /* RGIDW_MODID[642]:FBADDR*/ + [612] = {0xE67C249CU, 0x0000004EU}, /* RGIDW_MODID[643]:IPMMUMM01*/ + [613] = {0xE67C24A0U, 0x0000004EU}, /* RGIDW_MODID[644]:IPMMUMM10*/ + [614] = {0xE67C24A4U, 0x0000004EU}, /* RGIDW_MODID[645]:IPMMUMM11*/ + [615] = {0xE67C24A8U, 0x0000004EU}, /* RGIDW_MODID[646]:IPMMUMM12*/ + [616] = {0xE67C24ACU, 0x0000004EU}, /* RGIDW_MODID[647]:IPMMUMM13*/ + [617] = {0xE67C24B0U, 0x0000004EU}, /* RGIDW_MODID[648]:IPMMUMM14*/ + [618] = {0xE67C24B4U, 0x0000004EU}, /* RGIDW_MODID[649]:IPMMUMM15*/ + [619] = {0xE67C24B8U, 0x0000004EU}, /* RGIDW_MODID[650]:IPMMUMM02*/ + [620] = {0xE67C24BCU, 0x0000004EU}, /* RGIDW_MODID[651]:IPMMUMM03*/ + [621] = {0xE67C24C0U, 0x0000004EU}, /* RGIDW_MODID[652]:IPMMUMM04*/ + [622] = {0xE67C24C4U, 0x0000004EU}, /* RGIDW_MODID[653]:IPMMUMM05*/ + [623] = {0xE67C24C8U, 0x0000004EU}, /* RGIDW_MODID[654]:IPMMUMM06*/ + [624] = {0xE67C24CCU, 0x0000004EU}, /* RGIDW_MODID[655]:IPMMUMM07*/ + [625] = {0xE67C24D0U, 0x0000004EU}, /* RGIDW_MODID[656]:IPMMUMM08*/ + [626] = {0xE67C24D4U, 0x0000004EU}, /* RGIDW_MODID[657]:IPMMUMM09*/ + [627] = {0xFF802400U, 0x00000002U}, /* RGIDW_MODID[658]:ARSN0*/ + /* After setting */ /* RGIDW_MODID[659]:ARSN1*/ + /* After setting */ /* RGIDW_MODID[660]:ARSN2*/ + [628] = {0xFF80240CU, 0x00000001U}, /* RGIDW_MODID[661]:ARSN3*/ + [629] = {0xFF802410U, 0x00000002U}, /* RGIDW_MODID[662]:ARSN4*/ + [630] = {0xFF802414U, 0x00000001U}, /* RGIDW_MODID[663]:ARSN5*/ + [631] = {0xFF802418U, 0x00000002U}, /* RGIDW_MODID[664]:ARSN6*/ + [632] = {0xFF80241CU, 0x00000002U}, /* RGIDW_MODID[665]:ARSN7*/ + [633] = {0xFF802420U, 0x00000000U}, /* RGIDW_MODID[666]:ARSN8*/ + [634] = {0xFF802424U, 0x0000000AU}, /* RGIDW_MODID[667]:ECMTOP3*/ + [635] = {0xE7752400U, 0x00000002U}, /* RGIDW_MODID[668]:ARSD00*/ + /* After setting */ /* RGIDW_MODID[669]:ARSD01*/ + /* After setting */ /* RGIDW_MODID[670]:ARSD02*/ + [636] = {0xE775240CU, 0x00000001U}, /* RGIDW_MODID[671]:ARSD03*/ + [637] = {0xE7752410U, 0x00000002U}, /* RGIDW_MODID[672]:ARSD04*/ + [638] = {0xE7752414U, 0x00000001U}, /* RGIDW_MODID[673]:ARSD05*/ + [639] = {0xE7752418U, 0x00000002U}, /* RGIDW_MODID[674]:ARSD06*/ + [640] = {0xE775241CU, 0x0000004AU}, /* RGIDW_MODID[675]:AXIFRAY*/ + [641] = {0xE7752420U, 0x0000000FU}, /* RGIDW_MODID[676]:AXIIPC*/ + [642] = {0xE7752428U, 0x0000004FU}, /* RGIDW_MODID[677]:AXIRPC*/ + [643] = {0xE775242CU, 0x0000000FU}, /* RGIDW_MODID[678]:AXISDHI0*/ + [644] = {0xE7752430U, 0x00000002U}, /* RGIDW_MODID[679]:ARSD07*/ + [645] = {0xE7752434U, 0x00000000U}, /* RGIDW_MODID[680]:ARSD08*/ + [646] = {0xE7752438U, 0x00000002U}, /* RGIDW_MODID[681]:ARSP00*/ + /* After setting */ /* RGIDW_MODID[682]:ARSP01*/ + /* After setting */ /* RGIDW_MODID[683]:ARSP02*/ + [647] = {0xE7752444U, 0x00000001U}, /* RGIDW_MODID[684]:ARSP03*/ + [648] = {0xE7752448U, 0x00000002U}, /* RGIDW_MODID[685]:ARSP04*/ + [649] = {0xE775244CU, 0x00000001U}, /* RGIDW_MODID[686]:ARSP05*/ + [650] = {0xE7752450U, 0x00000002U}, /* RGIDW_MODID[687]:ARSP06*/ + [651] = {0xE7752454U, 0x00000002U}, /* RGIDW_MODID[688]:ARSP07*/ + [652] = {0xE7752458U, 0x00000000U}, /* RGIDW_MODID[689]:ARSP08*/ + [653] = {0xE775245CU, 0x0000004EU}, /* RGIDW_MODID[690]:IPMMUDS001*/ + [654] = {0xE7752460U, 0x0000000AU}, /* RGIDW_MODID[691]:CKMPER0*/ + [655] = {0xE7752464U, 0x0000000AU}, /* RGIDW_MODID[692]:ECMPER0*/ + [656] = {0xE7752468U, 0x0000000EU}, /* RGIDW_MODID[693]:FBAPER0*/ + [657] = {0xE775246CU, 0x0000004EU}, /* RGIDW_MODID[694]:FSO0*/ + [658] = {0xE7752470U, 0x0000004EU}, /* RGIDW_MODID[695]:FSO1*/ + [659] = {0xE7752474U, 0x0000004EU}, /* RGIDW_MODID[696]:FSO10*/ + [660] = {0xE7752478U, 0x0000004EU}, /* RGIDW_MODID[697]:FSO2*/ + [661] = {0xE775247CU, 0x0000004EU}, /* RGIDW_MODID[698]:FSO3*/ + [662] = {0xE7752480U, 0x0000004EU}, /* RGIDW_MODID[699]:FSO4*/ + [663] = {0xE7752484U, 0x0000004EU}, /* RGIDW_MODID[700]:FSO5*/ + [664] = {0xE7752488U, 0x0000004EU}, /* RGIDW_MODID[701]:FSO6*/ + [665] = {0xE775248CU, 0x0000004EU}, /* RGIDW_MODID[702]:FSO7*/ + [666] = {0xE7752490U, 0x0000004EU}, /* RGIDW_MODID[703]:FSO8*/ + [667] = {0xE7752494U, 0x0000004EU}, /* RGIDW_MODID[704]:FSO9*/ + [668] = {0xE7752498U, 0x0000002CU}, /* RGIDW_MODID[705]:ADG*/ + [669] = {0xE775249CU, 0x0000000AU}, /* RGIDW_MODID[706]:ECMSD0*/ + [670] = {0xE77524A0U, 0x0000004EU}, /* RGIDW_MODID[707]:IPMMUDS010*/ + [671] = {0xE77524A4U, 0x0000004EU}, /* RGIDW_MODID[708]:IPMMUDS011*/ + [672] = {0xE77524A8U, 0x0000004EU}, /* RGIDW_MODID[709]:I2C0*/ + [673] = {0xE77524ACU, 0x0000004EU}, /* RGIDW_MODID[710]:I2C1*/ + [674] = {0xE77524B0U, 0x0000004EU}, /* RGIDW_MODID[711]:I2C2*/ + [675] = {0xE77524B4U, 0x0000004EU}, /* RGIDW_MODID[712]:I2C3*/ + [676] = {0xE77524B8U, 0x0000004EU}, /* RGIDW_MODID[713]:I2C4*/ + [677] = {0xE77524BCU, 0x0000004EU}, /* RGIDW_MODID[714]:I2C5*/ + [678] = {0xE77524C0U, 0x0000004EU}, /* RGIDW_MODID[715]:IPMMUDS012*/ + [679] = {0xE77524C4U, 0x0000000FU}, /* RGIDW_MODID[716]:IPC*/ + [680] = {0xE77524C8U, 0x0000004EU}, /* RGIDW_MODID[717]:IPMMUDS000*/ + [681] = {0xE77524CCU, 0x0000004EU}, /* RGIDW_MODID[718]:IPMMUDS013*/ + [682] = {0xE77524D0U, 0x0000004EU}, /* RGIDW_MODID[719]:IPMMUDS014*/ + [683] = {0xE77524D4U, 0x0000004EU}, /* RGIDW_MODID[720]:IPMMUDS015*/ + [684] = {0xE77524D8U, 0x0000004EU}, /* RGIDW_MODID[721]:IPMMUDS002*/ + [685] = {0xE77524DCU, 0x0000004EU}, /* RGIDW_MODID[722]:IPMMUDS003*/ + [686] = {0xE77524E0U, 0x0000004EU}, /* RGIDW_MODID[723]:IPMMUDS004*/ + [687] = {0xE77524E4U, 0x0000004EU}, /* RGIDW_MODID[724]:IPMMUDS005*/ + [688] = {0xE77524E8U, 0x0000002CU}, /* RGIDW_MODID[725]:SSI*/ + [689] = {0xE77524ECU, 0x0000004EU}, /* RGIDW_MODID[726]:IPMMUDS006*/ + [690] = {0xE77524F0U, 0x0000004EU}, /* RGIDW_MODID[727]:IPMMUDS007*/ + [691] = {0xE77524F4U, 0x0000000CU}, /* RGIDW_MODID[728]:SYDM1P*/ + [692] = {0xE77524F8U, 0x0000004EU}, /* RGIDW_MODID[729]:IPMMUDS008*/ + [693] = {0xE77524FCU, 0x0000000CU}, /* RGIDW_MODID[730]:SYDM2P*/ + [694] = {0xE7752500U, 0x0000004EU}, /* RGIDW_MODID[731]:IPMMUDS009*/ + [695] = {0xE7752640U, 0x0000000CU}, /* RGIDW_MODID[732]:SYDM100*/ + [696] = {0xE7752644U, 0x0000000CU}, /* RGIDW_MODID[733]:SYDM101*/ + [697] = {0xE7752648U, 0x0000000CU}, /* RGIDW_MODID[734]:SYDM110*/ + [698] = {0xE775264CU, 0x0000000CU}, /* RGIDW_MODID[735]:SYDM111*/ + [699] = {0xE7752650U, 0x0000000CU}, /* RGIDW_MODID[736]:SYDM112*/ + [700] = {0xE7752654U, 0x0000000CU}, /* RGIDW_MODID[737]:SYDM113*/ + [701] = {0xE7752658U, 0x0000000CU}, /* RGIDW_MODID[738]:SYDM114*/ + [702] = {0xE775265CU, 0x0000000CU}, /* RGIDW_MODID[739]:SYDM115*/ + [703] = {0xE7752660U, 0x0000000CU}, /* RGIDW_MODID[740]:SYDM102*/ + [704] = {0xE7752664U, 0x0000000CU}, /* RGIDW_MODID[741]:SYDM103*/ + [705] = {0xE7752668U, 0x0000000CU}, /* RGIDW_MODID[742]:SYDM104*/ + [706] = {0xE775266CU, 0x0000000CU}, /* RGIDW_MODID[743]:SYDM105*/ + [707] = {0xE7752670U, 0x0000000CU}, /* RGIDW_MODID[744]:SYDM106*/ + [708] = {0xE7752674U, 0x0000000CU}, /* RGIDW_MODID[745]:SYDM107*/ + [709] = {0xE7752678U, 0x0000000CU}, /* RGIDW_MODID[746]:SYDM108*/ + [710] = {0xE775267CU, 0x0000000CU}, /* RGIDW_MODID[747]:SYDM109*/ + [711] = {0xE7752680U, 0x0000000CU}, /* RGIDW_MODID[748]:SYDM200*/ + [712] = {0xE7752684U, 0x0000000CU}, /* RGIDW_MODID[749]:SYDM201*/ + [713] = {0xE7752688U, 0x0000000CU}, /* RGIDW_MODID[750]:SYDM210*/ + [714] = {0xE775268CU, 0x0000000CU}, /* RGIDW_MODID[751]:SYDM211*/ + [715] = {0xE7752690U, 0x0000000CU}, /* RGIDW_MODID[752]:SYDM212*/ + [716] = {0xE7752694U, 0x0000000CU}, /* RGIDW_MODID[753]:SYDM213*/ + [717] = {0xE7752698U, 0x0000000CU}, /* RGIDW_MODID[754]:SYDM214*/ + [718] = {0xE775269CU, 0x0000000CU}, /* RGIDW_MODID[755]:SYDM215*/ + [719] = {0xE77526A0U, 0x0000000CU}, /* RGIDW_MODID[756]:SYDM202*/ + [720] = {0xE77526A4U, 0x0000000CU}, /* RGIDW_MODID[757]:SYDM203*/ + [721] = {0xE77526A8U, 0x0000000CU}, /* RGIDW_MODID[758]:SYDM204*/ + [722] = {0xE77526ACU, 0x0000000CU}, /* RGIDW_MODID[759]:SYDM205*/ + [723] = {0xE77526B0U, 0x0000000CU}, /* RGIDW_MODID[760]:SYDM206*/ + [724] = {0xE77526B4U, 0x0000000CU}, /* RGIDW_MODID[761]:SYDM207*/ + [725] = {0xE77526B8U, 0x0000000CU}, /* RGIDW_MODID[762]:SYDM208*/ + [726] = {0xE77526BCU, 0x0000000CU}, /* RGIDW_MODID[763]:SYDM209*/ + [727] = {0xFE682400U, 0x00000002U}, /* RGIDW_MODID[764]:ARVC0*/ + /* After setting */ /* RGIDW_MODID[765]:ARVC1*/ + /* After setting */ /* RGIDW_MODID[766]:ARVC2*/ + [728] = {0xFE68240CU, 0x00000001U}, /* RGIDW_MODID[767]:ARVC3*/ + [729] = {0xFE682410U, 0x0000000EU}, /* RGIDW_MODID[768]:AXIFBABUSVC*/ + [730] = {0xFE682414U, 0x00000002U}, /* RGIDW_MODID[769]:ARVC4*/ + [731] = {0xFE682418U, 0x00000001U}, /* RGIDW_MODID[770]:ARVC5*/ + [732] = {0xFE68241CU, 0x00000002U}, /* RGIDW_MODID[771]:ARVC6*/ + [733] = {0xFE682420U, 0x00000002U}, /* RGIDW_MODID[772]:ARVC7*/ + [734] = {0xFE682424U, 0x00000000U}, /* RGIDW_MODID[773]:ARVC8*/ + [735] = {0xFE682428U, 0x0000000AU}, /* RGIDW_MODID[774]:CKMVC*/ + [736] = {0xFE68242CU, 0x0000000AU}, /* RGIDW_MODID[775]:ECMVC0*/ + [737] = {0xFE682430U, 0x0000004EU}, /* RGIDW_MODID[776]:IMR2*/ + [738] = {0xFE682434U, 0x0000004EU}, /* RGIDW_MODID[777]:IMR0*/ + [739] = {0xFE682438U, 0x0000004EU}, /* RGIDW_MODID[778]:IMR1*/ + [740] = {0xFE68243CU, 0x0000004EU}, /* RGIDW_MODID[779]:IPMMUVC01*/ + [741] = {0xFE682440U, 0x0000004EU}, /* RGIDW_MODID[780]:IPMMUVC10*/ + [742] = {0xFE682444U, 0x0000000CU}, /* RGIDW_MODID[781]:IMS0*/ + [743] = {0xFE682448U, 0x0000000CU}, /* RGIDW_MODID[782]:IMS1*/ + [744] = {0xFE68244CU, 0x0000004EU}, /* RGIDW_MODID[783]:IPMMUVC00*/ + [745] = {0xFE682450U, 0x0000004EU}, /* RGIDW_MODID[784]:IPMMUVC11*/ + [746] = {0xFE682454U, 0x0000004EU}, /* RGIDW_MODID[785]:IPMMUVC12*/ + [747] = {0xFE682458U, 0x0000004EU}, /* RGIDW_MODID[786]:IPMMUVC13*/ + [748] = {0xFE68245CU, 0x0000004EU}, /* RGIDW_MODID[787]:IPMMUVC14*/ + [749] = {0xFE682460U, 0x0000004EU}, /* RGIDW_MODID[788]:IPMMUVC15*/ + [750] = {0xFE682464U, 0x0000004EU}, /* RGIDW_MODID[789]:IPMMUVC02*/ + [751] = {0xFE682468U, 0x0000004EU}, /* RGIDW_MODID[790]:IPMMUVC03*/ + [752] = {0xFE68246CU, 0x0000004EU}, /* RGIDW_MODID[791]:IPMMUVC04*/ + [753] = {0xFE682470U, 0x0000004EU}, /* RGIDW_MODID[792]:IPMMUVC05*/ + [754] = {0xFE682474U, 0x0000004EU}, /* RGIDW_MODID[793]:IPMMUVC06*/ + [755] = {0xFE682478U, 0x0000004EU}, /* RGIDW_MODID[794]:IPMMUVC07*/ + [756] = {0xFE68247CU, 0x0000004EU}, /* RGIDW_MODID[795]:IPMMUVC08*/ + [757] = {0xFE682480U, 0x0000004EU}, /* RGIDW_MODID[796]:IPMMUVC09*/ + [758] = {0xFE682484U, 0x00000028U}, /* RGIDW_MODID[797]:IV1ES*/ + [759] = {0xFEBE2400U, 0x0000004EU}, /* RGIDW_MODID[798]:CSITOP0*/ + [760] = {0xFEBE2404U, 0x00000002U}, /* RGIDW_MODID[799]:ARVI10*/ + /* After setting */ /* RGIDW_MODID[800]:ARVI11*/ + /* After setting */ /* RGIDW_MODID[801]:ARVI12*/ + [761] = {0xFEBE2410U, 0x00000001U}, /* RGIDW_MODID[802]:ARVI13*/ + [762] = {0xFEBE2414U, 0x00000002U}, /* RGIDW_MODID[803]:ARVI14*/ + [763] = {0xFEBE2418U, 0x00000001U}, /* RGIDW_MODID[804]:ARVI15*/ + [764] = {0xFEBE241CU, 0x00000002U}, /* RGIDW_MODID[805]:ARVI16*/ + [765] = {0xFEBE2420U, 0x00000002U}, /* RGIDW_MODID[806]:ARVI17*/ + [766] = {0xFEBE2424U, 0x00000000U}, /* RGIDW_MODID[807]:ARVI18*/ + [767] = {0xFEBE2428U, 0x0000000AU}, /* RGIDW_MODID[808]:CKMVIO*/ + [768] = {0xFEBE242CU, 0x0000004EU}, /* RGIDW_MODID[809]:CSITOP1*/ + [769] = {0xFEBE2434U, 0x0000004EU}, /* RGIDW_MODID[810]:DSITLINK0*/ + [770] = {0xFEBE2438U, 0x0000004EU}, /* RGIDW_MODID[811]:DSITLINK1*/ + [771] = {0xFEBE243CU, 0x0000000AU}, /* RGIDW_MODID[812]:ECMVIO1*/ + [772] = {0xFEBE2444U, 0x0000004EU}, /* RGIDW_MODID[813]:IPMMUVI001*/ + [773] = {0xFEBE2448U, 0x0000000CU}, /* RGIDW_MODID[814]:FCPVX0*/ + [774] = {0xFEBE244CU, 0x0000000CU}, /* RGIDW_MODID[815]:FCPVX1*/ + [775] = {0xFEBE2458U, 0x0000004EU}, /* RGIDW_MODID[816]:IPMMUVI000*/ + [776] = {0xFEBE245CU, 0x0000004EU}, /* RGIDW_MODID[817]:IPMMUVI100*/ + [777] = {0xFEBE2460U, 0x0000004EU}, /* RGIDW_MODID[818]:IPMMUVI010*/ + [778] = {0xFEBE2464U, 0x0000004EU}, /* RGIDW_MODID[819]:IPMMUVI011*/ + [779] = {0xFEBE2468U, 0x0000004EU}, /* RGIDW_MODID[820]:VSPX0*/ + [780] = {0xFEBE246CU, 0x0000004EU}, /* RGIDW_MODID[821]:VSPX1*/ + [781] = {0xFEBE2478U, 0x0000004EU}, /* RGIDW_MODID[822]:IPMMUVI012*/ + [782] = {0xFEBE247CU, 0x0000004EU}, /* RGIDW_MODID[823]:IPMMUVI013*/ + [783] = {0xFEBE2480U, 0x0000004EU}, /* RGIDW_MODID[824]:IPMMUVI014*/ + [784] = {0xFEBE2484U, 0x0000004EU}, /* RGIDW_MODID[825]:IPMMUVI015*/ + [785] = {0xFEBE2488U, 0x0000004EU}, /* RGIDW_MODID[826]:IPMMUVI002*/ + [786] = {0xFEBE248CU, 0x0000004EU}, /* RGIDW_MODID[827]:IPMMUVI003*/ + [787] = {0xFEBE2490U, 0x0000004EU}, /* RGIDW_MODID[828]:IPMMUVI004*/ + [788] = {0xFEBE2494U, 0x0000004EU}, /* RGIDW_MODID[829]:IPMMUVI005*/ + [789] = {0xFEBE2498U, 0x0000004EU}, /* RGIDW_MODID[830]:IPMMUVI006*/ + [790] = {0xFEBE249CU, 0x0000004EU}, /* RGIDW_MODID[831]:IPMMUVI007*/ + [791] = {0xFEBE24A0U, 0x0000004EU}, /* RGIDW_MODID[832]:IPMMUVI008*/ + [792] = {0xFEBE24A4U, 0x0000004EU}, /* RGIDW_MODID[833]:IPMMUVI009*/ + [793] = {0xFEBE24A8U, 0x0000004EU}, /* RGIDW_MODID[834]:IPMMUVI101*/ + [794] = {0xFEBE24ACU, 0x0000004EU}, /* RGIDW_MODID[835]:IPMMUVI110*/ + [795] = {0xFEBE24B0U, 0x0000004EU}, /* RGIDW_MODID[836]:IPMMUVI111*/ + [796] = {0xFEBE24B4U, 0x0000004EU}, /* RGIDW_MODID[837]:IPMMUVI112*/ + [797] = {0xFEBE24B8U, 0x0000004EU}, /* RGIDW_MODID[838]:IPMMUVI113*/ + [798] = {0xFEBE24BCU, 0x0000004EU}, /* RGIDW_MODID[839]:IPMMUVI114*/ + [799] = {0xFEBE24C0U, 0x0000004EU}, /* RGIDW_MODID[840]:IPMMUVI115*/ + [800] = {0xFEBE24C4U, 0x0000004EU}, /* RGIDW_MODID[841]:IPMMUVI102*/ + [801] = {0xFEBE24C8U, 0x0000004EU}, /* RGIDW_MODID[842]:IPMMUVI103*/ + [802] = {0xFEBE24CCU, 0x0000004EU}, /* RGIDW_MODID[843]:IPMMUVI104*/ + [803] = {0xFEBE24D0U, 0x0000004EU}, /* RGIDW_MODID[844]:IPMMUVI105*/ + [804] = {0xFEBE24D4U, 0x0000004EU}, /* RGIDW_MODID[845]:IPMMUVI106*/ + [805] = {0xFEBE24D8U, 0x0000004EU}, /* RGIDW_MODID[846]:IPMMUVI107*/ + [806] = {0xFEBE24DCU, 0x0000004EU}, /* RGIDW_MODID[847]:IPMMUVI108*/ + [807] = {0xFEBE24E0U, 0x0000004EU}, /* RGIDW_MODID[848]:IPMMUVI109*/ + [808] = {0xFEBE2504U, 0x0000000EU}, /* RGIDW_MODID[849]:AXIFBABUSVIO*/ + [809] = {0xFEBF2400U, 0x00000002U}, /* RGIDW_MODID[850]:ARVI0*/ + /* After setting */ /* RGIDW_MODID[851]:ARVI1*/ + /* After setting */ /* RGIDW_MODID[852]:ARVI2*/ + [810] = {0xFEBF240CU, 0x00000001U}, /* RGIDW_MODID[853]:ARVI3*/ + [811] = {0xFEBF2410U, 0x00000002U}, /* RGIDW_MODID[854]:ARVI4*/ + [812] = {0xFEBF2414U, 0x00000001U}, /* RGIDW_MODID[855]:ARVI5*/ + [813] = {0xFEBF2418U, 0x00000002U}, /* RGIDW_MODID[856]:ARVI6*/ + [814] = {0xFEBF241CU, 0x00000002U}, /* RGIDW_MODID[857]:ARVI7*/ + [815] = {0xFEBF2420U, 0x00000000U}, /* RGIDW_MODID[858]:ARVI8*/ + [816] = {0xFEBF2424U, 0x0000000AU}, /* RGIDW_MODID[859]:ECMVIO0*/ + [817] = {0xFEBF2428U, 0x0000004EU}, /* RGIDW_MODID[860]:ISP0*/ + [818] = {0xFEBF242CU, 0x0000004EU}, /* RGIDW_MODID[861]:ISP0CORE*/ + [819] = {0xFEBF2430U, 0x0000004EU}, /* RGIDW_MODID[862]:ISP1*/ + [820] = {0xFEBF2434U, 0x0000004EU}, /* RGIDW_MODID[863]:ISP1CORE*/ + [821] = {0xFEBF2454U, 0x0000004EU}, /* RGIDW_MODID[864]:VIN00*/ + [822] = {0xFEBF2458U, 0x0000004EU}, /* RGIDW_MODID[865]:VIN01*/ + [823] = {0xFEBF245CU, 0x0000004EU}, /* RGIDW_MODID[866]:VIN02*/ + [824] = {0xFEBF2460U, 0x0000004EU}, /* RGIDW_MODID[867]:VIN03*/ + [825] = {0xFEBF2464U, 0x0000004EU}, /* RGIDW_MODID[868]:VIN04*/ + [826] = {0xFEBF2468U, 0x0000004EU}, /* RGIDW_MODID[869]:VIN05*/ + [827] = {0xFEBF246CU, 0x0000004EU}, /* RGIDW_MODID[870]:VIN06*/ + [828] = {0xFEBF2470U, 0x0000004EU}, /* RGIDW_MODID[871]:VIN07*/ + [829] = {0xFEBF2474U, 0x0000004EU}, /* RGIDW_MODID[872]:VIN10*/ + [830] = {0xFEBF2478U, 0x0000004EU}, /* RGIDW_MODID[873]:VIN11*/ + [831] = {0xFEBF247CU, 0x0000004EU}, /* RGIDW_MODID[874]:VIN12*/ + [832] = {0xFEBF2480U, 0x0000004EU}, /* RGIDW_MODID[875]:VIN13*/ + [833] = {0xFEBF2484U, 0x0000004EU}, /* RGIDW_MODID[876]:VIN14*/ + [834] = {0xFEBF2488U, 0x0000004EU}, /* RGIDW_MODID[877]:VIN15*/ + [835] = {0xFEBF248CU, 0x0000004EU}, /* RGIDW_MODID[878]:VIN16*/ + [836] = {0xFEBF2490U, 0x0000004EU}, /* RGIDW_MODID[879]:VIN17*/ + [837] = {0xE7B12400U, 0x00000002U}, /* RGIDW_MODID[880]:ARVIP00*/ + /* After setting */ /* RGIDW_MODID[881]:ARVIP01*/ + /* After setting */ /* RGIDW_MODID[882]:ARVIP02*/ + [838] = {0xE7B1240CU, 0x00000001U}, /* RGIDW_MODID[883]:ARVIP03*/ + [839] = {0xE7B12410U, 0x0000000EU}, /* RGIDW_MODID[884]:AXIFBABUSVIP0*/ + [840] = {0xE7B12414U, 0x00000002U}, /* RGIDW_MODID[885]:ARVIP04*/ + [841] = {0xE7B12418U, 0x00000001U}, /* RGIDW_MODID[886]:ARVIP05*/ + [842] = {0xE7B1241CU, 0x00000002U}, /* RGIDW_MODID[887]:ARVIP06*/ + [843] = {0xE7B12420U, 0x00000002U}, /* RGIDW_MODID[888]:ARVIP07*/ + [844] = {0xE7B12424U, 0x00000000U}, /* RGIDW_MODID[889]:ARVIP08*/ + [845] = {0xE7B12428U, 0x0000000AU}, /* RGIDW_MODID[890]:CKMVIP*/ + [846] = {0xE7B1242CU, 0x0000000AU}, /* RGIDW_MODID[891]:ECMVIP0*/ + [847] = {0xE7B12430U, 0x0000004EU}, /* RGIDW_MODID[892]:IPMMUVIP000*/ + [848] = {0xE7B12438U, 0x0000004EU}, /* RGIDW_MODID[893]:SMPO0*/ + [849] = {0xE7B1243CU, 0x0000004EU}, /* RGIDW_MODID[894]:SMPS0*/ + [850] = {0xE7B12440U, 0x0000000CU}, /* RGIDW_MODID[895]:UMFL0*/ + [851] = {0xE7B12444U, 0x0000004EU}, /* RGIDW_MODID[896]:IPMMUVIP001*/ + [852] = {0xE7B12448U, 0x0000004EU}, /* RGIDW_MODID[897]:IPMMUVIP010*/ + [853] = {0xE7B1244CU, 0x0000004EU}, /* RGIDW_MODID[898]:IPMMUVIP011*/ + [854] = {0xE7B12450U, 0x0000004EU}, /* RGIDW_MODID[899]:UMFL0M_W*/ + [855] = {0xE7B12454U, 0x0000004EU}, /* RGIDW_MODID[900]:IPMMUVIP012*/ + [856] = {0xE7B12458U, 0x0000004EU}, /* RGIDW_MODID[901]:IPMMUVIP013*/ + [857] = {0xE7B1245CU, 0x0000004EU}, /* RGIDW_MODID[902]:IPMMUVIP014*/ + [858] = {0xE7B12460U, 0x0000004EU}, /* RGIDW_MODID[903]:IPMMUVIP015*/ + [859] = {0xE7B12464U, 0x0000004EU}, /* RGIDW_MODID[904]:IPMMUVIP002*/ + [860] = {0xE7B12468U, 0x0000004EU}, /* RGIDW_MODID[905]:IPMMUVIP003*/ + [861] = {0xE7B1246CU, 0x0000004EU}, /* RGIDW_MODID[906]:IPMMUVIP004*/ + [862] = {0xE7B12470U, 0x0000004EU}, /* RGIDW_MODID[907]:IPMMUVIP005*/ + [863] = {0xE7B12474U, 0x0000004EU}, /* RGIDW_MODID[908]:IPMMUVIP006*/ + [864] = {0xE7B12478U, 0x0000004EU}, /* RGIDW_MODID[909]:IPMMUVIP007*/ + [865] = {0xE7B1247CU, 0x0000004EU}, /* RGIDW_MODID[910]:IPMMUVIP008*/ + [866] = {0xE7B12480U, 0x0000004EU}, /* RGIDW_MODID[911]:IPMMUVIP009*/ + [867] = {0xE7B42400U, 0x00000002U}, /* RGIDW_MODID[912]:ARVIP10*/ + /* After setting */ /* RGIDW_MODID[913]:ARVIP11*/ + /* After setting */ /* RGIDW_MODID[914]:ARVIP12*/ + [868] = {0xE7B4240CU, 0x00000001U}, /* RGIDW_MODID[915]:ARVIP13*/ + [869] = {0xE7B42410U, 0x0000000EU}, /* RGIDW_MODID[916]:AXIFBABUSVIP1*/ + [870] = {0xE7B42414U, 0x00000002U}, /* RGIDW_MODID[917]:ARVIIP14*/ + [871] = {0xE7B42418U, 0x00000001U}, /* RGIDW_MODID[918]:ARVIIP15*/ + [872] = {0xE7B4241CU, 0x00000002U}, /* RGIDW_MODID[919]:ARVIIP16*/ + [873] = {0xE7B42420U, 0x00000002U}, /* RGIDW_MODID[920]:ARVIIP17*/ + [874] = {0xE7B42424U, 0x00000000U}, /* RGIDW_MODID[921]:ARVIIP18*/ + [875] = {0xE7B42438U, 0x0000000AU}, /* RGIDW_MODID[922]:ECMVIP1*/ + [876] = {0xE7B4243CU, 0x0000004EU}, /* RGIDW_MODID[923]:IPMMUVIP101*/ + [877] = {0xE7B42440U, 0x0000004EU}, /* RGIDW_MODID[924]:IPMMUVIP100*/ + [878] = {0xE7B42444U, 0x0000004EU}, /* RGIDW_MODID[925]:IPMMUVIP110*/ + [879] = {0xE7B42448U, 0x0000004EU}, /* RGIDW_MODID[926]:IPMMUVIP111*/ + [880] = {0xE7B4244CU, 0x0000004EU}, /* RGIDW_MODID[927]:IPMMUVIP112*/ + [881] = {0xE7B42450U, 0x0000004EU}, /* RGIDW_MODID[928]:IPMMUVIP113*/ + [882] = {0xE7B42454U, 0x0000004EU}, /* RGIDW_MODID[929]:IPMMUVIP114*/ + [883] = {0xE7B42458U, 0x0000004EU}, /* RGIDW_MODID[930]:IPMMUVIP115*/ + [884] = {0xE7B4245CU, 0x0000004EU}, /* RGIDW_MODID[931]:IPMMUVIP102*/ + [885] = {0xE7B42460U, 0x0000004EU}, /* RGIDW_MODID[932]:IPMMUVIP103*/ + [886] = {0xE7B42464U, 0x0000004EU}, /* RGIDW_MODID[933]:IPMMUVIP104*/ + [887] = {0xE7B42468U, 0x0000004EU}, /* RGIDW_MODID[934]:IPMMUVIP105*/ + [888] = {0xE7B4246CU, 0x0000004EU}, /* RGIDW_MODID[935]:IPMMUVIP106*/ + [889] = {0xE7B42470U, 0x0000004EU}, /* RGIDW_MODID[936]:IPMMUVIP107*/ + [890] = {0xE7B42474U, 0x0000004EU}, /* RGIDW_MODID[937]:IPMMUVIP108*/ + [891] = {0xE7B42478U, 0x0000004EU}, /* RGIDW_MODID[938]:IPMMUVIP109*/ + [892] = {0xE7B42518U, 0x00000004U}, /* RGIDW_MODID[939]:PAP*/ + [893] = {0xEB802400U, 0x00000002U}, /* RGIDW_MODID[940]:ARDSP0*/ + /* After setting */ /* RGIDW_MODID[941]:ARDSP1*/ + /* After setting */ /* RGIDW_MODID[942]:ARDSP2*/ + [894] = {0xEB80240CU, 0x00000001U}, /* RGIDW_MODID[943]:ARDSP3*/ + [895] = {0xEB802410U, 0x00000002U}, /* RGIDW_MODID[944]:ARDSP4*/ + [896] = {0xEB802414U, 0x00000001U}, /* RGIDW_MODID[945]:ARDSP5*/ + [897] = {0xEB802418U, 0x00000002U}, /* RGIDW_MODID[946]:ARDSP6*/ + [898] = {0xEB80241CU, 0x00000002U}, /* RGIDW_MODID[947]:ARDSP7*/ + [899] = {0xEB802420U, 0x0000000AU}, /* RGIDW_MODID[948]:ECMDSP*/ + [900] = {0xEB802424U, 0x0000000CU}, /* RGIDW_MODID[949]:AXIDSP0*/ + [901] = {0xEB802428U, 0x0000000CU}, /* RGIDW_MODID[950]:AXIDSP1*/ + [902] = {0xEB80242CU, 0x0000000CU}, /* RGIDW_MODID[951]:AXIDSP2*/ + [903] = {0xEB802430U, 0x0000000CU}, /* RGIDW_MODID[952]:AXIDSP3*/ + [905] = {0xE67B969CU, 0x00000000U}, /* RGIDW_MODID[953]:ARCC*/ + [904] = {0xE67B96B0U, 0x00000000U}, /* RGIDW_MODID[954]:ARRTRAM*/ + [906] = {0xE7752424U, 0x00000000U}, /* RGIDW_MODID[955]:RSV0*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_sec_tbl" +#else +__attribute__ ((section(".rgid_sec_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[] = { + [0] = {0xFFC83400U, 0x00000000U}, /* SEC_MODID[0]:ARMGC0*/ + [1] = {0xFFC83404U, 0x00000002U}, /* SEC_MODID[1]:ARMGC1*/ + [2] = {0xFFC83408U, 0x00000002U}, /* SEC_MODID[2]:ARMGC2*/ + [3] = {0xFFC8340CU, 0x00000002U}, /* SEC_MODID[3]:ARRT00*/ + [4] = {0xFFC83410U, 0x00000002U}, /* SEC_MODID[4]:ARRT01*/ + [5] = {0xFFC83414U, 0x00000002U}, /* SEC_MODID[5]:ARRT02*/ + [6] = {0xFFC83418U, 0x00000002U}, /* SEC_MODID[6]:ARRT03*/ + [7] = {0xFFC8341CU, 0x00000002U}, /* SEC_MODID[7]:ARRT04*/ + [8] = {0xFFC83420U, 0x00000002U}, /* SEC_MODID[8]:ARRT05*/ + [9] = {0xFFC83424U, 0x00000002U}, /* SEC_MODID[9]:ARRT06*/ + [10] = {0xFFC83428U, 0x00000002U}, /* SEC_MODID[10]:ARRT07*/ + [11] = {0xFFC8342CU, 0x00000002U}, /* SEC_MODID[11]:ARRT08*/ + [12] = {0xFFC83430U, 0x00000000U}, /* SEC_MODID[12]:LIFEC0*/ + [13] = {0xFFC83434U, 0x00000002U}, /* SEC_MODID[13]:SWDT*/ + [14] = {0xFFC83438U, 0x00000002U}, /* SEC_MODID[14]:TMU0*/ + [15] = {0xFFC8343CU, 0x00000002U}, /* SEC_MODID[15]:WDT*/ + [16] = {0xFFC83440U, 0x00000002U}, /* SEC_MODID[16]:WWDT0*/ + [17] = {0xFFC83444U, 0x00000002U}, /* SEC_MODID[17]:WWDT1*/ + [18] = {0xFFC83448U, 0x00000002U}, /* SEC_MODID[18]:WWDT2*/ + [19] = {0xFFC8344CU, 0x00000002U}, /* SEC_MODID[19]:WWDT3*/ + [20] = {0xFFC83450U, 0x00000002U}, /* SEC_MODID[20]:WWDT4*/ + [21] = {0xFFC83454U, 0x00000002U}, /* SEC_MODID[21]:WWDT5*/ + [22] = {0xFFC83458U, 0x00000002U}, /* SEC_MODID[22]:WWDT6*/ + [23] = {0xFFC83468U, 0x00000002U}, /* SEC_MODID[23]:ECMRT3*/ + [24] = {0xE6003400U, 0x00000002U}, /* SEC_MODID[24]:ADVFSC*/ + [25] = {0xE6003404U, 0x00000002U}, /* SEC_MODID[25]:APMU0*/ + [26] = {0xE6003408U, 0x00000002U}, /* SEC_MODID[26]:APMU1*/ + [27] = {0xE600340CU, 0x00000002U}, /* SEC_MODID[27]:APMU10*/ + [28] = {0xE6003410U, 0x00000002U}, /* SEC_MODID[28]:APMU11*/ + [29] = {0xE6003414U, 0x00000002U}, /* SEC_MODID[29]:APMU12*/ + [30] = {0xE6003418U, 0x00000002U}, /* SEC_MODID[30]:APMU13*/ + [31] = {0xE600341CU, 0x00000002U}, /* SEC_MODID[31]:APMU14*/ + [32] = {0xE6003420U, 0x00000002U}, /* SEC_MODID[32]:APMU15*/ + [33] = {0xE6003424U, 0x00000002U}, /* SEC_MODID[33]:APMU2*/ + [34] = {0xE6003428U, 0x00000002U}, /* SEC_MODID[34]:APMU3*/ + [35] = {0xE600342CU, 0x00000002U}, /* SEC_MODID[35]:APMU4*/ + [36] = {0xE6003430U, 0x00000002U}, /* SEC_MODID[36]:APMU5*/ + [37] = {0xE6003434U, 0x00000002U}, /* SEC_MODID[37]:APMU6*/ + [38] = {0xE6003438U, 0x00000002U}, /* SEC_MODID[38]:APMU7*/ + [39] = {0xE600343CU, 0x00000002U}, /* SEC_MODID[39]:APMU8*/ + [40] = {0xE6003440U, 0x00000002U}, /* SEC_MODID[40]:APMU9*/ + [41] = {0xE6003444U, 0x00000002U}, /* SEC_MODID[41]:ARS00*/ + [42] = {0xE6003448U, 0x00000002U}, /* SEC_MODID[42]:ARS01*/ + [43] = {0xE600344CU, 0x00000002U}, /* SEC_MODID[43]:ARS02*/ + [44] = {0xE6003450U, 0x00000002U}, /* SEC_MODID[44]:ARS03*/ + [45] = {0xE6003454U, 0x00000002U}, /* SEC_MODID[45]:ARS04*/ + [46] = {0xE6003458U, 0x00000002U}, /* SEC_MODID[46]:ARS05*/ + [47] = {0xE600345CU, 0x00000002U}, /* SEC_MODID[47]:ARS06*/ + [48] = {0xE6003460U, 0x00000002U}, /* SEC_MODID[48]:ARS07*/ + [49] = {0xE6003464U, 0x00000002U}, /* SEC_MODID[49]:ARS08*/ + [50] = {0xE6003468U, 0x00000002U}, /* SEC_MODID[50]:CMT0*/ + [51] = {0xE600346CU, 0x00000002U}, /* SEC_MODID[51]:CMT1*/ + [52] = {0xE6003470U, 0x00000002U}, /* SEC_MODID[52]:CMT2*/ + [53] = {0xE6003474U, 0x00000002U}, /* SEC_MODID[53]:CMT3*/ + [54] = {0xE6003478U, 0x00000002U}, /* SEC_MODID[54]:CKM*/ + [55] = {0xE600347CU, 0x00000002U}, /* SEC_MODID[55]:DBE*/ + [56] = {0xE6003480U, 0x00000002U}, /* SEC_MODID[56]:IRQC*/ + [57] = {0xE6003484U, 0x00000002U}, /* SEC_MODID[57]:ECMPS0*/ + [58] = {0xE6003488U, 0x00000002U}, /* SEC_MODID[58]:OTP0*/ + [59] = {0xE600348CU, 0x00000002U}, /* SEC_MODID[59]:OTP1*/ + [60] = {0xE600349CU, 0x00000002U}, /* SEC_MODID[60]:SCMT*/ + [61] = {0xE60034A8U, 0x00000002U}, /* SEC_MODID[61]:TSC1*/ + [62] = {0xE60034ACU, 0x00000002U}, /* SEC_MODID[62]:TSC2*/ + [63] = {0xE60034B0U, 0x00000002U}, /* SEC_MODID[63]:TSC3*/ + [64] = {0xE60034B4U, 0x00000002U}, /* SEC_MODID[64]:TSC4*/ + [65] = {0xE60034B8U, 0x00000002U}, /* SEC_MODID[65]:UCMT*/ + [66] = {0xE6003500U, 0x00000002U}, /* SEC_MODID[66]:CPG0*/ + [67] = {0xE6003504U, 0x00000002U}, /* SEC_MODID[67]:CPG1*/ + [68] = {0xE6003508U, 0x00000002U}, /* SEC_MODID[68]:CPG2*/ + [69] = {0xE600350CU, 0x00000002U}, /* SEC_MODID[69]:CPG3*/ + [70] = {0xE6003510U, 0x00000002U}, /* SEC_MODID[70]:PFC00*/ + [71] = {0xE6003514U, 0x00000002U}, /* SEC_MODID[71]:PFC01*/ + [72] = {0xE6003518U, 0x00000002U}, /* SEC_MODID[72]:PFC02*/ + [73] = {0xE600351CU, 0x00000002U}, /* SEC_MODID[73]:PFC03*/ + [74] = {0xE6003520U, 0x00000002U}, /* SEC_MODID[74]:PFC10*/ + [75] = {0xE6003524U, 0x00000002U}, /* SEC_MODID[75]:PFC11*/ + [76] = {0xE6003528U, 0x00000002U}, /* SEC_MODID[76]:PFC12*/ + [77] = {0xE600352CU, 0x00000002U}, /* SEC_MODID[77]:PFC13*/ + [78] = {0xE6003530U, 0x00000002U}, /* SEC_MODID[78]:PFC20*/ + [79] = {0xE6003534U, 0x00000002U}, /* SEC_MODID[79]:PFC21*/ + [80] = {0xE6003538U, 0x00000002U}, /* SEC_MODID[80]:PFC22*/ + [81] = {0xE600353CU, 0x00000002U}, /* SEC_MODID[81]:PFC23*/ + [82] = {0xE6003540U, 0x00000002U}, /* SEC_MODID[82]:PFC30*/ + [83] = {0xE6003544U, 0x00000002U}, /* SEC_MODID[83]:PFC31*/ + [84] = {0xE6003548U, 0x00000002U}, /* SEC_MODID[84]:PFC32*/ + [85] = {0xE600354CU, 0x00000002U}, /* SEC_MODID[85]:PFC33*/ + [86] = {0xE6003550U, 0x00000002U}, /* SEC_MODID[86]:PFCS0*/ + [87] = {0xE6003554U, 0x00000002U}, /* SEC_MODID[87]:PFCS1*/ + [88] = {0xE6003558U, 0x00000002U}, /* SEC_MODID[88]:PFCS2*/ + [89] = {0xE600355CU, 0x00000002U}, /* SEC_MODID[89]:PFCS3*/ + [90] = {0xE6003560U, 0x00000002U}, /* SEC_MODID[90]:RESET0*/ + [91] = {0xE6003564U, 0x00000002U}, /* SEC_MODID[91]:RESET1*/ + [92] = {0xE6003568U, 0x00000002U}, /* SEC_MODID[92]:RESET2*/ + [93] = {0xE600356CU, 0x00000002U}, /* SEC_MODID[93]:RESET3*/ + [94] = {0xE6003570U, 0x00000002U}, /* SEC_MODID[94]:SYS0*/ + [95] = {0xE6003574U, 0x00000002U}, /* SEC_MODID[95]:SYS1*/ + [96] = {0xE6003578U, 0x00000002U}, /* SEC_MODID[96]:SYS2*/ + [97] = {0xE600357CU, 0x00000002U}, /* SEC_MODID[97]:SYS3*/ + [98] = {0xE7763400U, 0x00000002U}, /* SEC_MODID[98]:DMAMSI0*/ + [99] = {0xE7763404U, 0x00000002U}, /* SEC_MODID[99]:DMAMSI1*/ + [100] = {0xE7763408U, 0x00000002U}, /* SEC_MODID[100]:DMAMSI2*/ + [101] = {0xE776340CU, 0x00000002U}, /* SEC_MODID[101]:DMAMSI3*/ + [102] = {0xE7763410U, 0x00000002U}, /* SEC_MODID[102]:DMAMSI4*/ + [103] = {0xE7763414U, 0x00000002U}, /* SEC_MODID[103]:DMAMSI5*/ + [104] = {0xE7763418U, 0x00000002U}, /* SEC_MODID[104]:ECMSP3*/ + [105] = {0xE7763424U, 0x00000002U}, /* SEC_MODID[105]:ARSP30*/ + [106] = {0xE7763428U, 0x00000002U}, /* SEC_MODID[106]:ARSP31*/ + [107] = {0xE776342CU, 0x00000002U}, /* SEC_MODID[107]:ARSP32*/ + [108] = {0xE7763430U, 0x00000002U}, /* SEC_MODID[108]:ARSP33*/ + [109] = {0xE7763434U, 0x00000002U}, /* SEC_MODID[109]:ARSP34*/ + [110] = {0xE7763438U, 0x00000002U}, /* SEC_MODID[110]:ARSP35*/ + [111] = {0xE776343CU, 0x00000002U}, /* SEC_MODID[111]:ARSP36*/ + [112] = {0xE7763440U, 0x00000002U}, /* SEC_MODID[112]:ARSP37*/ + [113] = {0xE7763444U, 0x00000002U}, /* SEC_MODID[113]:ARSP38*/ + [114] = {0xE7763448U, 0x00000002U}, /* SEC_MODID[114]:MSI0*/ + [115] = {0xE776344CU, 0x00000002U}, /* SEC_MODID[115]:MSI1*/ + [116] = {0xE7763450U, 0x00000002U}, /* SEC_MODID[116]:MSI2*/ + [117] = {0xE7763454U, 0x00000002U}, /* SEC_MODID[117]:MSI3*/ + [118] = {0xE7763458U, 0x00000002U}, /* SEC_MODID[118]:MSI4*/ + [119] = {0xE776345CU, 0x00000002U}, /* SEC_MODID[119]:MSI5*/ + [120] = {0xE7793400U, 0x00000002U}, /* SEC_MODID[120]:ARSP40*/ + [121] = {0xE7793404U, 0x00000002U}, /* SEC_MODID[121]:ARSP41*/ + [122] = {0xE7793408U, 0x00000002U}, /* SEC_MODID[122]:ARSP42*/ + [123] = {0xE779340CU, 0x00000002U}, /* SEC_MODID[123]:ARSP43*/ + [124] = {0xE7793410U, 0x00000002U}, /* SEC_MODID[124]:ARSP44*/ + [125] = {0xE7793414U, 0x00000002U}, /* SEC_MODID[125]:ARSP45*/ + [126] = {0xE7793418U, 0x00000002U}, /* SEC_MODID[126]:ARSP46*/ + [127] = {0xE779341CU, 0x00000002U}, /* SEC_MODID[127]:ARSP47*/ + [128] = {0xE7793420U, 0x00000002U}, /* SEC_MODID[128]:ARSP48*/ + [129] = {0xE7793424U, 0x00000002U}, /* SEC_MODID[129]:DMAHSCIF0*/ + [130] = {0xE7793428U, 0x00000002U}, /* SEC_MODID[130]:DMAHSCIF1*/ + [131] = {0xE779342CU, 0x00000002U}, /* SEC_MODID[131]:DMAHSCIF2*/ + [132] = {0xE7793430U, 0x00000002U}, /* SEC_MODID[132]:DMAHSCIF3*/ + [133] = {0xE7793434U, 0x00000002U}, /* SEC_MODID[133]:DMASCIF0*/ + [134] = {0xE7793438U, 0x00000002U}, /* SEC_MODID[134]:DMASCIF1*/ + [135] = {0xE779343CU, 0x00000002U}, /* SEC_MODID[135]:DMASCIF3*/ + [136] = {0xE7793440U, 0x00000002U}, /* SEC_MODID[136]:DMASCIF4*/ + [137] = {0xE7793444U, 0x00000002U}, /* SEC_MODID[137]:ECMSP4*/ + [138] = {0xE7793448U, 0x00000002U}, /* SEC_MODID[138]:HSCIF0*/ + [139] = {0xE779344CU, 0x00000002U}, /* SEC_MODID[139]:HSCIF1*/ + [140] = {0xE7793450U, 0x00000002U}, /* SEC_MODID[140]:HSCIF2*/ + [141] = {0xE7793454U, 0x00000002U}, /* SEC_MODID[141]:HSCIF3*/ + [142] = {0xE7793458U, 0x00000002U}, /* SEC_MODID[142]:SCIF0*/ + [143] = {0xE779345CU, 0x00000002U}, /* SEC_MODID[143]:SCIF1*/ + [144] = {0xE7793460U, 0x00000002U}, /* SEC_MODID[144]:SCIF3*/ + [145] = {0xE7793464U, 0x00000002U}, /* SEC_MODID[145]:SCIF4*/ + [146] = {0xE7793468U, 0x00000002U}, /* SEC_MODID[146]:TMU1*/ + [147] = {0xE779346CU, 0x00000002U}, /* SEC_MODID[147]:TMU2*/ + [148] = {0xE7793470U, 0x00000002U}, /* SEC_MODID[148]:TMU3*/ + [149] = {0xE7793474U, 0x00000002U}, /* SEC_MODID[149]:TMU4*/ + [150] = {0xE7793478U, 0x00000002U}, /* SEC_MODID[150]:CANFD*/ + [151] = {0xE779347CU, 0x00000002U}, /* SEC_MODID[151]:DMACANFD*/ + [152] = {0xE7793480U, 0x00000002U}, /* SEC_MODID[152]:DMATPU0*/ + [153] = {0xE7793484U, 0x00000002U}, /* SEC_MODID[153]:PWM0*/ + [154] = {0xE7793488U, 0x00000002U}, /* SEC_MODID[154]:PWM1*/ + [155] = {0xE779348CU, 0x00000002U}, /* SEC_MODID[155]:PWM2*/ + [156] = {0xE7793490U, 0x00000002U}, /* SEC_MODID[156]:PWM3*/ + [157] = {0xE7793494U, 0x00000002U}, /* SEC_MODID[157]:PWM4*/ + [158] = {0xE7793498U, 0x00000002U}, /* SEC_MODID[158]:PWM5*/ + [159] = {0xE779349CU, 0x00000002U}, /* SEC_MODID[159]:PWM6*/ + [160] = {0xE77934A0U, 0x00000002U}, /* SEC_MODID[160]:PWM7*/ + [161] = {0xE77934A4U, 0x00000002U}, /* SEC_MODID[161]:PWM8*/ + [162] = {0xE77934A8U, 0x00000002U}, /* SEC_MODID[162]:PWM9*/ + [163] = {0xE77934ACU, 0x00000002U}, /* SEC_MODID[163]:TPU0*/ + [164] = {0xFE673400U, 0x00000002U}, /* SEC_MODID[164]:ARVC10*/ + [165] = {0xFE673404U, 0x00000002U}, /* SEC_MODID[165]:ARVC11*/ + [166] = {0xFE673408U, 0x00000002U}, /* SEC_MODID[166]:ARVC12*/ + [167] = {0xFE67340CU, 0x00000002U}, /* SEC_MODID[167]:ARVC13*/ + [168] = {0xFE673410U, 0x00000002U}, /* SEC_MODID[168]:ARVC14*/ + [169] = {0xFE673414U, 0x00000002U}, /* SEC_MODID[169]:ARVC15*/ + [170] = {0xFE673418U, 0x00000002U}, /* SEC_MODID[170]:ARVC16*/ + [171] = {0xFE67341CU, 0x00000002U}, /* SEC_MODID[171]:ARVC17*/ + [172] = {0xFE673420U, 0x00000002U}, /* SEC_MODID[172]:ARVC18*/ + [173] = {0xFE673424U, 0x00000002U}, /* SEC_MODID[173]:ECMVC1*/ + [174] = {0xFE673428U, 0x00000002U}, /* SEC_MODID[174]:FCPCS*/ + [175] = {0xFE67342CU, 0x00000002U}, /* SEC_MODID[175]:VCP4LC*/ + [176] = {0xFE673430U, 0x00000002U}, /* SEC_MODID[176]:VCP4LV*/ + [177] = {0xFEBD3400U, 0x00000002U}, /* SEC_MODID[177]:ARVI40*/ + [178] = {0xFEBD3404U, 0x00000002U}, /* SEC_MODID[178]:ARVI41*/ + [179] = {0xFEBD3408U, 0x00000002U}, /* SEC_MODID[179]:ARVI42*/ + [180] = {0xFEBD340CU, 0x00000002U}, /* SEC_MODID[180]:ARVI43*/ + [181] = {0xFEBD3410U, 0x00000002U}, /* SEC_MODID[181]:ARVI44*/ + [182] = {0xFEBD3414U, 0x00000002U}, /* SEC_MODID[182]:ARVI45*/ + [183] = {0xFEBD3418U, 0x00000002U}, /* SEC_MODID[183]:ARVI46*/ + [184] = {0xFEBD341CU, 0x00000002U}, /* SEC_MODID[184]:ARVI47*/ + [185] = {0xFEBD3420U, 0x00000002U}, /* SEC_MODID[185]:ARVI48*/ + [186] = {0xFEBD3424U, 0x00000002U}, /* SEC_MODID[186]:DIS0*/ + [187] = {0xFEBD342CU, 0x00000002U}, /* SEC_MODID[187]:DSC*/ + [188] = {0xFEBD3430U, 0x00000002U}, /* SEC_MODID[188]:ECMVIO2*/ + [189] = {0xFEBD3434U, 0x00000002U}, /* SEC_MODID[189]:FCPVD0*/ + [190] = {0xFEBD3438U, 0x00000002U}, /* SEC_MODID[190]:FCPVD1*/ + [191] = {0xFEBD343CU, 0x00000002U}, /* SEC_MODID[191]:VSPD0*/ + [192] = {0xFEBD3440U, 0x00000002U}, /* SEC_MODID[192]:VSPD1*/ + [193] = {0xE6583400U, 0x00000002U}, /* SEC_MODID[193]:CKMHSC*/ + [194] = {0xE6583404U, 0x00000002U}, /* SEC_MODID[194]:AXIPCI001*/ + [195] = {0xE6583408U, 0x00000002U}, /* SEC_MODID[195]:AXIPCI002*/ + [196] = {0xE658340CU, 0x00000002U}, /* SEC_MODID[196]:AXIPCI003*/ + [197] = {0xE6583414U, 0x00000002U}, /* SEC_MODID[197]:AXIPCI005*/ + [198] = {0xE6583418U, 0x00000002U}, /* SEC_MODID[198]:AXIPCI006*/ + [199] = {0xE658341CU, 0x00000002U}, /* SEC_MODID[199]:AXIPCI007*/ + [200] = {0xE6583420U, 0x00000002U}, /* SEC_MODID[200]:AXIPCI008*/ + [201] = {0xE6583424U, 0x00000002U}, /* SEC_MODID[201]:AXIPCI009*/ + [202] = {0xE6583428U, 0x00000002U}, /* SEC_MODID[202]:AXIPCI010*/ + [203] = {0xE658342CU, 0x00000002U}, /* SEC_MODID[203]:AXIPCI011*/ + [204] = {0xE6583430U, 0x00000002U}, /* SEC_MODID[204]:AXIPCI012*/ + [205] = {0xE6583434U, 0x00000002U}, /* SEC_MODID[205]:AXIPCI013*/ + [206] = {0xE6583438U, 0x00000002U}, /* SEC_MODID[206]:AXIPCI014*/ + [207] = {0xE658343CU, 0x00000002U}, /* SEC_MODID[207]:AXIPCI015*/ + [208] = {0xE6583440U, 0x00000002U}, /* SEC_MODID[208]:AXIPCI100*/ + [209] = {0xE6583444U, 0x00000002U}, /* SEC_MODID[209]:AXIPCI101*/ + [210] = {0xE6583448U, 0x00000002U}, /* SEC_MODID[210]:AXIPCI102*/ + [211] = {0xE658344CU, 0x00000002U}, /* SEC_MODID[211]:AXIPCI103*/ + [212] = {0xE6583450U, 0x00000002U}, /* SEC_MODID[212]:AXIPCI104*/ + [213] = {0xE6583454U, 0x00000002U}, /* SEC_MODID[213]:AXIPCI105*/ + [214] = {0xE6583458U, 0x00000002U}, /* SEC_MODID[214]:AXIPCI106*/ + [215] = {0xE658345CU, 0x00000002U}, /* SEC_MODID[215]:AXIPCI107*/ + [216] = {0xE6583460U, 0x00000002U}, /* SEC_MODID[216]:AXIPCI108*/ + [217] = {0xE6583464U, 0x00000002U}, /* SEC_MODID[217]:AXIPCI109*/ + [218] = {0xE6583468U, 0x00000002U}, /* SEC_MODID[218]:AXIPCI110*/ + [219] = {0xE658346CU, 0x00000002U}, /* SEC_MODID[219]:AXIPCI111*/ + [220] = {0xE6583470U, 0x00000002U}, /* SEC_MODID[220]:AXIPCI112*/ + [221] = {0xE6583474U, 0x00000002U}, /* SEC_MODID[221]:AXIPCI113*/ + [222] = {0xE6583478U, 0x00000002U}, /* SEC_MODID[222]:AXIPCI114*/ + [223] = {0xE658347CU, 0x00000002U}, /* SEC_MODID[223]:AXIPCI115*/ + [224] = {0xE6583484U, 0x00000002U}, /* SEC_MODID[224]:GPTP*/ + [225] = {0xE6583488U, 0x00000002U}, /* SEC_MODID[225]:IPMMUHC00*/ + [226] = {0xE65834F0U, 0x00000002U}, /* SEC_MODID[226]:TSN0*/ + [227] = {0xE65834F4U, 0x00000002U}, /* SEC_MODID[227]:AXIPCI000*/ + [228] = {0xE65834F8U, 0x00000002U}, /* SEC_MODID[228]:AXIPCI004*/ + [229] = {0xE65834FCU, 0x00000002U}, /* SEC_MODID[229]:IPMMUHC01*/ + [230] = {0xE6583500U, 0x00000002U}, /* SEC_MODID[230]:AVB0*/ + [231] = {0xE6583504U, 0x00000002U}, /* SEC_MODID[231]:AVB1*/ + [232] = {0xE6583508U, 0x00000002U}, /* SEC_MODID[232]:AVB2*/ + [233] = {0xE658350CU, 0x00000002U}, /* SEC_MODID[233]:IPMMUHC10*/ + [234] = {0xE6583510U, 0x00000002U}, /* SEC_MODID[234]:IPMMUHC11*/ + [235] = {0xE6583514U, 0x00000002U}, /* SEC_MODID[235]:IPMMUHC12*/ + [236] = {0xE6583518U, 0x00000002U}, /* SEC_MODID[236]:IPMMUHC13*/ + [237] = {0xE658351CU, 0x00000002U}, /* SEC_MODID[237]:PPHY0*/ + [238] = {0xE6583520U, 0x00000002U}, /* SEC_MODID[238]:PPHY1*/ + [239] = {0xE6583524U, 0x00000002U}, /* SEC_MODID[239]:IPMMUHC14*/ + [240] = {0xE6583528U, 0x00000002U}, /* SEC_MODID[240]:IPMMUHC15*/ + [241] = {0xE658352CU, 0x00000002U}, /* SEC_MODID[241]:FBAHSC*/ + [242] = {0xE6583530U, 0x00000002U}, /* SEC_MODID[242]:IPMMUHC02*/ + [243] = {0xE6583538U, 0x00000002U}, /* SEC_MODID[243]:ECMHSC*/ + [244] = {0xE658353CU, 0x00000002U}, /* SEC_MODID[244]:ARHC0*/ + [245] = {0xE6583540U, 0x00000002U}, /* SEC_MODID[245]:ARHC1*/ + [246] = {0xE6583544U, 0x00000002U}, /* SEC_MODID[246]:ARHC2*/ + [247] = {0xE6583548U, 0x00000002U}, /* SEC_MODID[247]:ARHC3*/ + [248] = {0xE658354CU, 0x00000002U}, /* SEC_MODID[248]:ARHC4*/ + [249] = {0xE6583550U, 0x00000002U}, /* SEC_MODID[249]:ARHC5*/ + [250] = {0xE6583554U, 0x00000002U}, /* SEC_MODID[250]:ARHC6*/ + [251] = {0xE6583558U, 0x00000002U}, /* SEC_MODID[251]:ARHC7*/ + [252] = {0xE658355CU, 0x00000002U}, /* SEC_MODID[252]:ARHC8*/ + [253] = {0xE6583560U, 0x00000002U}, /* SEC_MODID[253]:IPMMUHC03*/ + [254] = {0xE6583564U, 0x00000002U}, /* SEC_MODID[254]:IPMMUHC04*/ + [255] = {0xE6583568U, 0x00000002U}, /* SEC_MODID[255]:IPMMUHC05*/ + [256] = {0xE658356CU, 0x00000002U}, /* SEC_MODID[256]:IPMMUHC06*/ + [257] = {0xE6583570U, 0x00000002U}, /* SEC_MODID[257]:IPMMUHC07*/ + [258] = {0xE6583574U, 0x00000002U}, /* SEC_MODID[258]:IPMMUHC08*/ + [259] = {0xE6583578U, 0x00000002U}, /* SEC_MODID[259]:IPMMUHC09*/ + [260] = {0xFF883400U, 0x00000002U}, /* SEC_MODID[260]:ARIMP00*/ + [261] = {0xFF883404U, 0x00000002U}, /* SEC_MODID[261]:ARIMP01*/ + [262] = {0xFF883408U, 0x00000002U}, /* SEC_MODID[262]:ARIMP02*/ + [263] = {0xFF88340CU, 0x00000002U}, /* SEC_MODID[263]:ARIMP03*/ + [264] = {0xFF883410U, 0x00000002U}, /* SEC_MODID[264]:ARIMP04*/ + [265] = {0xFF883414U, 0x00000002U}, /* SEC_MODID[265]:AXIFBABUSIR0*/ + [266] = {0xFF883418U, 0x00000002U}, /* SEC_MODID[266]:AXIFBABUSIR1*/ + [267] = {0xFF88341CU, 0x00000002U}, /* SEC_MODID[267]:AXIFBABUSIR2*/ + [268] = {0xFF883420U, 0x00000002U}, /* SEC_MODID[268]:AXIFBABUSIR3*/ + [269] = {0xFF883424U, 0x00000002U}, /* SEC_MODID[269]:AXIFBABUSIR4*/ + [270] = {0xFF883428U, 0x00000002U}, /* SEC_MODID[270]:AXIIMP0*/ + [271] = {0xFF88342CU, 0x00000002U}, /* SEC_MODID[271]:CKMCNR*/ + [272] = {0xFF883430U, 0x00000002U}, /* SEC_MODID[272]:CKMDSP*/ + [273] = {0xFF883434U, 0x00000002U}, /* SEC_MODID[273]:ARIMP05*/ + [274] = {0xFF883438U, 0x00000002U}, /* SEC_MODID[274]:ARIMP06*/ + [275] = {0xFF88343CU, 0x00000002U}, /* SEC_MODID[275]:ARIMP07*/ + [276] = {0xFF883440U, 0x00000002U}, /* SEC_MODID[276]:ARIMP08*/ + [277] = {0xFF883444U, 0x00000002U}, /* SEC_MODID[277]:CKMIR*/ + [278] = {0xFF883448U, 0x00000002U}, /* SEC_MODID[278]:ECMIR*/ + [279] = {0xFF88344CU, 0x00000002U}, /* SEC_MODID[279]:DSPPS*/ + [280] = {0xFF883450U, 0x00000002U}, /* SEC_MODID[280]:IPMMUIR1*/ + [281] = {0xFF883454U, 0x00000002U}, /* SEC_MODID[281]:IPMMUIR0*/ + [282] = {0xFF883458U, 0x00000002U}, /* SEC_MODID[282]:IPMMUIR10*/ + [283] = {0xFF88345CU, 0x00000002U}, /* SEC_MODID[283]:IPMMUIR11*/ + [284] = {0xFF883460U, 0x00000002U}, /* SEC_MODID[284]:IPMMUIR12*/ + [285] = {0xFF883464U, 0x00000002U}, /* SEC_MODID[285]:IPMMUIR13*/ + [286] = {0xFF883468U, 0x00000002U}, /* SEC_MODID[286]:IPMMUIR14*/ + [287] = {0xFF88346CU, 0x00000002U}, /* SEC_MODID[287]:IPMMUIR15*/ + [288] = {0xFF883470U, 0x00000002U}, /* SEC_MODID[288]:IPMMUIR2*/ + [289] = {0xFF883474U, 0x00000002U}, /* SEC_MODID[289]:IPMMUIR3*/ + [290] = {0xFF883478U, 0x00000002U}, /* SEC_MODID[290]:IPMMUIR4*/ + [291] = {0xFF88347CU, 0x00000002U}, /* SEC_MODID[291]:IPMMUIR5*/ + [292] = {0xFF883480U, 0x00000002U}, /* SEC_MODID[292]:IPMMUIR6*/ + [293] = {0xFF883484U, 0x00000002U}, /* SEC_MODID[293]:IPMMUIR7*/ + [294] = {0xFF883488U, 0x00000002U}, /* SEC_MODID[294]:IPMMUIR8*/ + [295] = {0xFF88348CU, 0x00000002U}, /* SEC_MODID[295]:IPMMUIR9*/ + [296] = {0xFD813400U, 0x00000002U}, /* SEC_MODID[296]:ARPV0*/ + [297] = {0xFD813404U, 0x00000002U}, /* SEC_MODID[297]:ARPV1*/ + [298] = {0xFD813408U, 0x00000002U}, /* SEC_MODID[298]:AXIRGXS*/ + [299] = {0xFD81340CU, 0x00000002U}, /* SEC_MODID[299]:ARPV2*/ + [300] = {0xFD813410U, 0x00000002U}, /* SEC_MODID[300]:ARPV3*/ + [301] = {0xFD813414U, 0x00000002U}, /* SEC_MODID[301]:ARPV4*/ + [302] = {0xFD813418U, 0x00000002U}, /* SEC_MODID[302]:ARPV5*/ + [303] = {0xFD81341CU, 0x00000002U}, /* SEC_MODID[303]:ARPV6*/ + [304] = {0xFD813420U, 0x00000002U}, /* SEC_MODID[304]:ARPV7*/ + [305] = {0xFD813424U, 0x00000002U}, /* SEC_MODID[305]:ARPV8*/ + [306] = {0xFD813428U, 0x00000002U}, /* SEC_MODID[306]:CKM3DG*/ + [307] = {0xFD81342CU, 0x00000002U}, /* SEC_MODID[307]:ECM3DG*/ + [308] = {0xFD813430U, 0x00000002U}, /* SEC_MODID[308]:FBAPVC*/ + [309] = {0xFD813434U, 0x00000002U}, /* SEC_MODID[309]:FBAPVD0*/ + [310] = {0xFD813438U, 0x00000002U}, /* SEC_MODID[310]:FBAPVD1*/ + [311] = {0xFD81343CU, 0x00000002U}, /* SEC_MODID[311]:FBAPVD2*/ + [312] = {0xFD813440U, 0x00000002U}, /* SEC_MODID[312]:FBAPVE*/ + [313] = {0xFD813444U, 0x00000002U}, /* SEC_MODID[313]:IPMMUPV000*/ + [314] = {0xFD813448U, 0x00000002U}, /* SEC_MODID[314]:IPMMUPV001*/ + [315] = {0xFD81344CU, 0x00000002U}, /* SEC_MODID[315]:IPMMUPV010*/ + [316] = {0xFD813450U, 0x00000002U}, /* SEC_MODID[316]:IPMMUPV011*/ + [317] = {0xFD813454U, 0x00000002U}, /* SEC_MODID[317]:IPMMUPV012*/ + [318] = {0xFD813458U, 0x00000002U}, /* SEC_MODID[318]:IPMMUPV013*/ + [319] = {0xFD81345CU, 0x00000002U}, /* SEC_MODID[319]:IPMMUPV014*/ + [320] = {0xFD813460U, 0x00000002U}, /* SEC_MODID[320]:IPMMUPV015*/ + [321] = {0xFD813464U, 0x00000002U}, /* SEC_MODID[321]:IPMMUPV002*/ + [322] = {0xFD813468U, 0x00000002U}, /* SEC_MODID[322]:IPMMUPV003*/ + [323] = {0xFD81346CU, 0x00000002U}, /* SEC_MODID[323]:IPMMUPV004*/ + [324] = {0xFD813470U, 0x00000002U}, /* SEC_MODID[324]:IPMMUPV005*/ + [325] = {0xFD813474U, 0x00000002U}, /* SEC_MODID[325]:IPMMUPV006*/ + [326] = {0xFD813478U, 0x00000002U}, /* SEC_MODID[326]:IPMMUPV007*/ + [327] = {0xFD81347CU, 0x00000002U}, /* SEC_MODID[327]:IPMMUPV008*/ + [328] = {0xFD813480U, 0x00000002U}, /* SEC_MODID[328]:IPMMUPV009*/ + [329] = {0xE6623400U, 0x00000002U}, /* SEC_MODID[329]:ARRC0*/ + [330] = {0xE6623404U, 0x00000002U}, /* SEC_MODID[330]:ARRC1*/ + [331] = {0xE6623408U, 0x00000002U}, /* SEC_MODID[331]:ARRC2*/ + [332] = {0xE662340CU, 0x00000002U}, /* SEC_MODID[332]:ARRC3*/ + [333] = {0xE6623410U, 0x00000002U}, /* SEC_MODID[333]:ARRC4*/ + [334] = {0xE6623414U, 0x00000002U}, /* SEC_MODID[334]:ARRC5*/ + [335] = {0xE6623418U, 0x00000002U}, /* SEC_MODID[335]:ARRC6*/ + [336] = {0xE662341CU, 0x00000002U}, /* SEC_MODID[336]:ARRC7*/ + [337] = {0xE6623420U, 0x00000002U}, /* SEC_MODID[337]:ARRC8*/ + [338] = {0xE6623424U, 0x00000000U}, /* SEC_MODID[338]:CR0*/ + [339] = {0xE6623428U, 0x00000002U}, /* SEC_MODID[339]:ICUMX*/ + [340] = {0xE662342CU, 0x00000002U}, /* SEC_MODID[340]:ECMRC*/ + [341] = {0xFFC33400U, 0x00000002U}, /* SEC_MODID[341]:DMAWCRC0*/ + [342] = {0xFFC33404U, 0x00000002U}, /* SEC_MODID[342]:DMAWCRC1*/ + [343] = {0xFFC33408U, 0x00000002U}, /* SEC_MODID[343]:DMAWCRC2*/ + [344] = {0xFFC3340CU, 0x00000002U}, /* SEC_MODID[344]:DMAWCRC3*/ + [345] = {0xFFC43400U, 0x00000002U}, /* SEC_MODID[345]:ARMREG00*/ + [346] = {0xFFC43404U, 0x00000002U}, /* SEC_MODID[346]:ARMREG01*/ + [347] = {0xFFC43408U, 0x00000002U}, /* SEC_MODID[347]:ARMREG10*/ + [348] = {0xFFC4340CU, 0x00000002U}, /* SEC_MODID[348]:ARMREG11*/ + [349] = {0xFFC43410U, 0x00000002U}, /* SEC_MODID[349]:ARMREG12*/ + [350] = {0xFFC43414U, 0x00000000U}, /* SEC_MODID[350]:ARMREG13*/ + [351] = {0xFFC43418U, 0x00000000U}, /* SEC_MODID[351]:ARMREG14*/ + [352] = {0xFFC4341CU, 0x00000002U}, /* SEC_MODID[352]:AXICR52SS0*/ + [353] = {0xFFC43420U, 0x00000002U}, /* SEC_MODID[353]:AXICSD0*/ + [354] = {0xFFC43424U, 0x00000002U}, /* SEC_MODID[354]:AXIINTAP0*/ + [355] = {0xFFC43428U, 0x00000002U}, /* SEC_MODID[355]:AXIINTAP1*/ + [356] = {0xFFC4342CU, 0x00000002U}, /* SEC_MODID[356]:AXISECROM*/ + [357] = {0xFFC43430U, 0x00000002U}, /* SEC_MODID[357]:AXISYSRAM0*/ + [358] = {0xFFC43434U, 0x00000002U}, /* SEC_MODID[358]:AXISYSRAM1*/ + [359] = {0xFFC43438U, 0x00000002U}, /* SEC_MODID[359]:ARGREG15*/ + [360] = {0xFFC4343CU, 0x00000002U}, /* SEC_MODID[360]:ARMREG2*/ + [361] = {0xFFC43440U, 0x00000002U}, /* SEC_MODID[361]:ARMREG3*/ + [362] = {0xFFC43444U, 0x00000002U}, /* SEC_MODID[362]:ARMREG4*/ + [363] = {0xFFC43448U, 0x00000002U}, /* SEC_MODID[363]:ARMREG5*/ + [364] = {0xFFC4344CU, 0x00000002U}, /* SEC_MODID[364]:ARMREG6*/ + [365] = {0xFFC43450U, 0x00000002U}, /* SEC_MODID[365]:ARMREG7*/ + [366] = {0xFFC43454U, 0x00000000U}, /* SEC_MODID[366]:ARMREG8*/ + [367] = {0xFFC43458U, 0x00000000U}, /* SEC_MODID[367]:ARMREG9*/ + [368] = {0xFFC4345CU, 0x00000002U}, /* SEC_MODID[368]:ARRD0*/ + [369] = {0xFFC43460U, 0x00000002U}, /* SEC_MODID[369]:ARRD1*/ + [370] = {0xFFC43464U, 0x00000002U}, /* SEC_MODID[370]:ARRD2*/ + [371] = {0xFFC43468U, 0x00000002U}, /* SEC_MODID[371]:ARRD3*/ + [372] = {0xFFC4346CU, 0x00000002U}, /* SEC_MODID[372]:ARRD4*/ + [373] = {0xFFC43470U, 0x00000002U}, /* SEC_MODID[373]:ARRD5*/ + [374] = {0xFFC43474U, 0x00000002U}, /* SEC_MODID[374]:ARRD6*/ + [375] = {0xFFC43478U, 0x00000002U}, /* SEC_MODID[375]:ARRD7*/ + [376] = {0xFFC4347CU, 0x00000002U}, /* SEC_MODID[376]:ARRD8*/ + [377] = {0xFFC43480U, 0x00000002U}, /* SEC_MODID[377]:ARRT0*/ + [378] = {0xFFC43484U, 0x00000002U}, /* SEC_MODID[378]:ARRT1*/ + [379] = {0xFFC43488U, 0x00000002U}, /* SEC_MODID[379]:ARRT2*/ + [380] = {0xFFC4348CU, 0x00000002U}, /* SEC_MODID[380]:ARRT3*/ + [381] = {0xFFC43490U, 0x00000002U}, /* SEC_MODID[381]:ARRT4*/ + [382] = {0xFFC43494U, 0x00000002U}, /* SEC_MODID[382]:ARRT5*/ + [383] = {0xFFC43498U, 0x00000002U}, /* SEC_MODID[383]:ARRT6*/ + [384] = {0xFFC4349CU, 0x00000002U}, /* SEC_MODID[384]:ARRT7*/ + [385] = {0xFFC434A0U, 0x00000002U}, /* SEC_MODID[385]:ARRT8*/ + [386] = {0xFFC434A4U, 0x00000002U}, /* SEC_MODID[386]:CKMRT*/ + [387] = {0xFFC434A8U, 0x00000002U}, /* SEC_MODID[387]:CRC0*/ + [388] = {0xFFC434ACU, 0x00000002U}, /* SEC_MODID[388]:CRC1*/ + [389] = {0xFFC434B0U, 0x00000002U}, /* SEC_MODID[389]:CRC2*/ + [390] = {0xFFC434B4U, 0x00000002U}, /* SEC_MODID[390]:CRC3*/ + [391] = {0xFFC434B8U, 0x00000002U}, /* SEC_MODID[391]:CSD*/ + [392] = {0xFFC434BCU, 0x00000002U}, /* SEC_MODID[392]:ECM*/ + [393] = {0xFFC434C0U, 0x00000002U}, /* SEC_MODID[393]:ECMRT*/ + [394] = {0xFFC434C4U, 0x00000002U}, /* SEC_MODID[394]:FBACR52*/ + [395] = {0xFFC434C8U, 0x00000002U}, /* SEC_MODID[395]:FBART*/ + [396] = {0xFFC434CCU, 0x00000002U}, /* SEC_MODID[396]:INTTP*/ + [397] = {0xFFC434D0U, 0x00000002U}, /* SEC_MODID[397]:IPMMURT000*/ + [398] = {0xFFC434D4U, 0x00000002U}, /* SEC_MODID[398]:IPMMURT100*/ + [399] = {0xFFC434D8U, 0x00000002U}, /* SEC_MODID[399]:KCRC4*/ + [400] = {0xFFC434DCU, 0x00000002U}, /* SEC_MODID[400]:KCRC5*/ + [401] = {0xFFC434E0U, 0x00000002U}, /* SEC_MODID[401]:KCRC6*/ + [402] = {0xFFC434E4U, 0x00000002U}, /* SEC_MODID[402]:KCRC7*/ + [403] = {0xFFC434E8U, 0x00000002U}, /* SEC_MODID[403]:MFI00*/ + [404] = {0xFFC434ECU, 0x00000002U}, /* SEC_MODID[404]:MFI01*/ + [405] = {0xFFC434F0U, 0x00000002U}, /* SEC_MODID[405]:MFI10*/ + [406] = {0xFFC434F4U, 0x00000002U}, /* SEC_MODID[406]:MFI02*/ + [407] = {0xFFC434F8U, 0x00000002U}, /* SEC_MODID[407]:MFI03*/ + [408] = {0xFFC434FCU, 0x00000002U}, /* SEC_MODID[408]:MFI04*/ + [409] = {0xFFC43500U, 0x00000002U}, /* SEC_MODID[409]:MFI05*/ + [410] = {0xFFC43504U, 0x00000002U}, /* SEC_MODID[410]:MFI06*/ + [411] = {0xFFC43508U, 0x00000002U}, /* SEC_MODID[411]:MFI07*/ + [412] = {0xFFC4350CU, 0x00000002U}, /* SEC_MODID[412]:MFI08*/ + [413] = {0xFFC43510U, 0x00000002U}, /* SEC_MODID[413]:MFI09*/ + [414] = {0xFFC43514U, 0x00000002U}, /* SEC_MODID[414]:MFI15*/ + [415] = {0xFFC43518U, 0x00000002U}, /* SEC_MODID[415]:CKMCR52*/ + [416] = {0xFFC4351CU, 0x00000002U}, /* SEC_MODID[416]:RTDM0P*/ + [417] = {0xFFC43520U, 0x00000002U}, /* SEC_MODID[417]:ECMRD*/ + [418] = {0xFFC43524U, 0x00000002U}, /* SEC_MODID[418]:RTDM1P*/ + [419] = {0xFFC4352CU, 0x00000002U}, /* SEC_MODID[419]:RTDM2P*/ + [420] = {0xFFC43530U, 0x00000002U}, /* SEC_MODID[420]:SYSRAM10*/ + [421] = {0xFFC43534U, 0x00000002U}, /* SEC_MODID[421]:RTDM3P*/ + [422] = {0xFFC43538U, 0x00000000U}, /* SEC_MODID[422]:SYSRAM00*/ + [423] = {0xFFC4353CU, 0x00000002U}, /* SEC_MODID[423]:TSIPL0*/ + [424] = {0xFFC43540U, 0x00000002U}, /* SEC_MODID[424]:TSIPL1*/ + [425] = {0xFFC43544U, 0x00000002U}, /* SEC_MODID[425]:TSIPL2*/ + [426] = {0xFFC43548U, 0x00000002U}, /* SEC_MODID[426]:TSIPL3*/ + [427] = {0xFFC4354CU, 0x00000002U}, /* SEC_MODID[427]:TSIPL4*/ + [428] = {0xFFC43550U, 0x00000002U}, /* SEC_MODID[428]:TSIPL5*/ + [429] = {0xFFC43554U, 0x00000002U}, /* SEC_MODID[429]:TSIPL6*/ + [430] = {0xFFC43558U, 0x00000002U}, /* SEC_MODID[430]:TSIPL7*/ + [431] = {0xFFC4355CU, 0x00000002U}, /* SEC_MODID[431]:WCRC0*/ + [432] = {0xFFC43560U, 0x00000002U}, /* SEC_MODID[432]:WCRC1*/ + [433] = {0xFFC43564U, 0x00000002U}, /* SEC_MODID[433]:WCRC2*/ + [434] = {0xFFC43568U, 0x00000002U}, /* SEC_MODID[434]:WCRC3*/ + [435] = {0xFFC43580U, 0x00000002U}, /* SEC_MODID[435]:MFI11*/ + [436] = {0xFFC43584U, 0x00000002U}, /* SEC_MODID[436]:MFI12*/ + [437] = {0xFFC43588U, 0x00000002U}, /* SEC_MODID[437]:MFI13*/ + [438] = {0xFFC4358CU, 0x00000002U}, /* SEC_MODID[438]:MFI14*/ + [439] = {0xFFC43590U, 0x00000002U}, /* SEC_MODID[439]:IPMMURT001*/ + [440] = {0xFFC43594U, 0x00000002U}, /* SEC_MODID[440]:IPMMURT010*/ + [441] = {0xFFC43598U, 0x00000002U}, /* SEC_MODID[441]:IPMMURT011*/ + [442] = {0xFFC4359CU, 0x00000002U}, /* SEC_MODID[442]:IPMMURT012*/ + [443] = {0xFFC435A0U, 0x00000002U}, /* SEC_MODID[443]:IPMMURT013*/ + [444] = {0xFFC435A4U, 0x00000002U}, /* SEC_MODID[444]:IPMMURT014*/ + [445] = {0xFFC435A8U, 0x00000002U}, /* SEC_MODID[445]:IPMMURT015*/ + [446] = {0xFFC435ACU, 0x00000002U}, /* SEC_MODID[446]:IPMMURT002*/ + [447] = {0xFFC435B0U, 0x00000002U}, /* SEC_MODID[447]:IPMMURT003*/ + [448] = {0xFFC435B4U, 0x00000002U}, /* SEC_MODID[448]:IPMMURT004*/ + [449] = {0xFFC435B8U, 0x00000002U}, /* SEC_MODID[449]:IPMMURT005*/ + [450] = {0xFFC435BCU, 0x00000002U}, /* SEC_MODID[450]:IPMMURT006*/ + [451] = {0xFFC435C0U, 0x00000002U}, /* SEC_MODID[451]:IPMMURT007*/ + [452] = {0xFFC435C4U, 0x00000002U}, /* SEC_MODID[452]:IPMMURT008*/ + [453] = {0xFFC435C8U, 0x00000002U}, /* SEC_MODID[453]:IPMMURT009*/ + [454] = {0xFFC435CCU, 0x00000002U}, /* SEC_MODID[454]:IPKMURT101*/ + [455] = {0xFFC435D0U, 0x00000002U}, /* SEC_MODID[455]:IPMMURT110*/ + [456] = {0xFFC435D4U, 0x00000002U}, /* SEC_MODID[456]:IPMMURT111*/ + [457] = {0xFFC435D8U, 0x00000002U}, /* SEC_MODID[457]:IPMMURT112*/ + [458] = {0xFFC435DCU, 0x00000002U}, /* SEC_MODID[458]:IPMMURT113*/ + [459] = {0xFFC435E0U, 0x00000002U}, /* SEC_MODID[459]:IPMMURT114*/ + [460] = {0xFFC435E4U, 0x00000002U}, /* SEC_MODID[460]:IPMMURT115*/ + [461] = {0xFFC435E8U, 0x00000002U}, /* SEC_MODID[461]:IPMMURT102*/ + [462] = {0xFFC435ECU, 0x00000002U}, /* SEC_MODID[462]:IPMMURT103*/ + [463] = {0xFFC435F0U, 0x00000002U}, /* SEC_MODID[463]:IPMMURT104*/ + [464] = {0xFFC435F4U, 0x00000002U}, /* SEC_MODID[464]:IPMMURT105*/ + [465] = {0xFFC435F8U, 0x00000002U}, /* SEC_MODID[465]:IPMMURT106*/ + [466] = {0xFFC435FCU, 0x00000002U}, /* SEC_MODID[466]:IPMMURT107*/ + [467] = {0xFFC43600U, 0x00000002U}, /* SEC_MODID[467]:RTDM000*/ + [468] = {0xFFC43604U, 0x00000002U}, /* SEC_MODID[468]:RTDM001*/ + [469] = {0xFFC43608U, 0x00000002U}, /* SEC_MODID[469]:RTDM010*/ + [470] = {0xFFC4360CU, 0x00000002U}, /* SEC_MODID[470]:RTDM011*/ + [471] = {0xFFC43610U, 0x00000002U}, /* SEC_MODID[471]:RTDM012*/ + [472] = {0xFFC43614U, 0x00000002U}, /* SEC_MODID[472]:RTDM013*/ + [473] = {0xFFC43618U, 0x00000002U}, /* SEC_MODID[473]:RTDM014*/ + [474] = {0xFFC4361CU, 0x00000002U}, /* SEC_MODID[474]:RTDM015*/ + [475] = {0xFFC43620U, 0x00000002U}, /* SEC_MODID[475]:RTDM002*/ + [476] = {0xFFC43624U, 0x00000002U}, /* SEC_MODID[476]:RTDM003*/ + [477] = {0xFFC43628U, 0x00000002U}, /* SEC_MODID[477]:RTDM004*/ + [478] = {0xFFC4362CU, 0x00000002U}, /* SEC_MODID[478]:RTDM005*/ + [479] = {0xFFC43630U, 0x00000002U}, /* SEC_MODID[479]:RTDM006*/ + [480] = {0xFFC43634U, 0x00000002U}, /* SEC_MODID[480]:RTDM007*/ + [481] = {0xFFC43638U, 0x00000002U}, /* SEC_MODID[481]:RTDM008*/ + [482] = {0xFFC4363CU, 0x00000002U}, /* SEC_MODID[482]:RTDM009*/ + [483] = {0xFFC43640U, 0x00000002U}, /* SEC_MODID[483]:RTDM100*/ + [484] = {0xFFC43644U, 0x00000002U}, /* SEC_MODID[484]:RTDM101*/ + [485] = {0xFFC43648U, 0x00000002U}, /* SEC_MODID[485]:RTDM110*/ + [486] = {0xFFC4364CU, 0x00000002U}, /* SEC_MODID[486]:RTDM111*/ + [487] = {0xFFC43650U, 0x00000002U}, /* SEC_MODID[487]:RTDM112*/ + [488] = {0xFFC43654U, 0x00000002U}, /* SEC_MODID[488]:RTDM113*/ + [489] = {0xFFC43658U, 0x00000002U}, /* SEC_MODID[489]:RTDM114*/ + [490] = {0xFFC4365CU, 0x00000002U}, /* SEC_MODID[490]:RTDM115*/ + [491] = {0xFFC43660U, 0x00000002U}, /* SEC_MODID[491]:RTDM102*/ + [492] = {0xFFC43664U, 0x00000002U}, /* SEC_MODID[492]:RTDM103*/ + [493] = {0xFFC43668U, 0x00000002U}, /* SEC_MODID[493]:RTDM104*/ + [494] = {0xFFC4366CU, 0x00000002U}, /* SEC_MODID[494]:RTDM105*/ + [495] = {0xFFC43670U, 0x00000002U}, /* SEC_MODID[495]:RTDM106*/ + [496] = {0xFFC43674U, 0x00000002U}, /* SEC_MODID[496]:RTDM107*/ + [497] = {0xFFC43678U, 0x00000002U}, /* SEC_MODID[497]:RTDM108*/ + [498] = {0xFFC4367CU, 0x00000002U}, /* SEC_MODID[498]:RTDM109*/ + [499] = {0xFFC43680U, 0x00000002U}, /* SEC_MODID[499]:RTDM200*/ + [500] = {0xFFC43684U, 0x00000002U}, /* SEC_MODID[500]:RTDM201*/ + [501] = {0xFFC43688U, 0x00000002U}, /* SEC_MODID[501]:RTDM210*/ + [502] = {0xFFC4368CU, 0x00000002U}, /* SEC_MODID[502]:RTDM211*/ + [503] = {0xFFC43690U, 0x00000002U}, /* SEC_MODID[503]:RTDM212*/ + [504] = {0xFFC43694U, 0x00000002U}, /* SEC_MODID[504]:RTDM213*/ + [505] = {0xFFC43698U, 0x00000002U}, /* SEC_MODID[505]:RTDM214*/ + [506] = {0xFFC4369CU, 0x00000002U}, /* SEC_MODID[506]:RTDM215*/ + [507] = {0xFFC436A0U, 0x00000002U}, /* SEC_MODID[507]:RTDM202*/ + [508] = {0xFFC436A4U, 0x00000002U}, /* SEC_MODID[508]:RTDM203*/ + [509] = {0xFFC436A8U, 0x00000002U}, /* SEC_MODID[509]:RTDM204*/ + [510] = {0xFFC436ACU, 0x00000002U}, /* SEC_MODID[510]:RTDM205*/ + [511] = {0xFFC436B0U, 0x00000002U}, /* SEC_MODID[511]:RTDM206*/ + [512] = {0xFFC436B4U, 0x00000002U}, /* SEC_MODID[512]:RTDM207*/ + [513] = {0xFFC436B8U, 0x00000002U}, /* SEC_MODID[513]:RTDM208*/ + [514] = {0xFFC436BCU, 0x00000002U}, /* SEC_MODID[514]:RTDM209*/ + [515] = {0xFFC436C0U, 0x00000002U}, /* SEC_MODID[515]:RTDM300*/ + [516] = {0xFFC436C4U, 0x00000002U}, /* SEC_MODID[516]:RTDM301*/ + [517] = {0xFFC436C8U, 0x00000002U}, /* SEC_MODID[517]:RTDM310*/ + [518] = {0xFFC436CCU, 0x00000002U}, /* SEC_MODID[518]:RTDM311*/ + [519] = {0xFFC436D0U, 0x00000002U}, /* SEC_MODID[519]:RTDM312*/ + [520] = {0xFFC436D4U, 0x00000002U}, /* SEC_MODID[520]:RTDM313*/ + [521] = {0xFFC436D8U, 0x00000002U}, /* SEC_MODID[521]:RTDM314*/ + [522] = {0xFFC436DCU, 0x00000002U}, /* SEC_MODID[522]:RTDM315*/ + [523] = {0xFFC436E0U, 0x00000002U}, /* SEC_MODID[523]:RTDM302*/ + [524] = {0xFFC436E4U, 0x00000002U}, /* SEC_MODID[524]:RTDM303*/ + [525] = {0xFFC436E8U, 0x00000002U}, /* SEC_MODID[525]:RTDM304*/ + [526] = {0xFFC436ECU, 0x00000002U}, /* SEC_MODID[526]:RTDM305*/ + [527] = {0xFFC436F0U, 0x00000002U}, /* SEC_MODID[527]:RTDM306*/ + [528] = {0xFFC436F4U, 0x00000002U}, /* SEC_MODID[528]:RTDM307*/ + [529] = {0xFFC436F8U, 0x00000002U}, /* SEC_MODID[529]:RTDM308*/ + [530] = {0xFFC436FCU, 0x00000002U}, /* SEC_MODID[530]:RTDM309*/ + [531] = {0xFFC43700U, 0x00000002U}, /* SEC_MODID[531]:IPMMURT108*/ + [532] = {0xFFC43704U, 0x00000002U}, /* SEC_MODID[532]:IPMMURT109*/ + [533] = {0xFFC43708U, 0x00000000U}, /* SEC_MODID[533]:SYSRAM01*/ + [534] = {0xFFC4370CU, 0x00000002U}, /* SEC_MODID[534]:SYSRAM02*/ + [535] = {0xFFC43710U, 0x00000000U}, /* SEC_MODID[535]:SYSRAM03*/ + [536] = {0xFFC43714U, 0x00000000U}, /* SEC_MODID[536]:SYSRAM04*/ + [537] = {0xFFC43718U, 0x00000000U}, /* SEC_MODID[537]:SYSRAM05*/ + [538] = {0xFFC4371CU, 0x00000000U}, /* SEC_MODID[538]:SYSRAM06*/ + [539] = {0xFFC43720U, 0x00000002U}, /* SEC_MODID[539]:SYSRAM07*/ + [540] = {0xFFC43724U, 0x00000002U}, /* SEC_MODID[540]:SYSRAM11*/ + [541] = {0xFFC43728U, 0x00000002U}, /* SEC_MODID[541]:SYSRAM12*/ + [542] = {0xFFC4372CU, 0x00000002U}, /* SEC_MODID[542]:SYSRAM13*/ + [543] = {0xFFC43730U, 0x00000002U}, /* SEC_MODID[543]:SYSRAM14*/ + [544] = {0xFFC43734U, 0x00000002U}, /* SEC_MODID[544]:SYSRAM15*/ + [545] = {0xFFC43738U, 0x00000002U}, /* SEC_MODID[545]:SYSRAM16*/ + [546] = {0xFFC4373CU, 0x00000002U}, /* SEC_MODID[546]:SYSRAM17*/ + [547] = {0xFFC43760U, 0x00000002U}, /* SEC_MODID[547]:BKBUF*/ + [548] = {0xFFC43764U, 0x00000002U}, /* SEC_MODID[548]:AXICR52SS1*/ + [549] = {0xFFC43768U, 0x00000002U}, /* SEC_MODID[549]:AXICR52SS2*/ + [550] = {0xFF863400U, 0x00000002U}, /* SEC_MODID[550]:ARSC0*/ + [551] = {0xFF863404U, 0x00000002U}, /* SEC_MODID[551]:ARSC1*/ + [552] = {0xFF863408U, 0x00000002U}, /* SEC_MODID[552]:ARSC2*/ + [553] = {0xFF86340CU, 0x00000002U}, /* SEC_MODID[553]:ARSC3*/ + [554] = {0xFF863410U, 0x00000002U}, /* SEC_MODID[554]:ARSC4*/ + [555] = {0xFF863414U, 0x00000002U}, /* SEC_MODID[555]:ARSC5*/ + [556] = {0xFF863418U, 0x00000002U}, /* SEC_MODID[556]:ARSC6*/ + [557] = {0xFF86341CU, 0x00000002U}, /* SEC_MODID[557]:ARSC7*/ + [558] = {0xFF863420U, 0x00000002U}, /* SEC_MODID[558]:ARSC8*/ + [559] = {0xFF863424U, 0x00000002U}, /* SEC_MODID[559]:ARSTM0*/ + [560] = {0xFF863428U, 0x00000002U}, /* SEC_MODID[560]:ARSTM1*/ + [561] = {0xFF86342CU, 0x00000002U}, /* SEC_MODID[561]:CSD1S*/ + [562] = {0xFF863430U, 0x00000002U}, /* SEC_MODID[562]:AXIFBABUSTOP0*/ + [563] = {0xFF863434U, 0x00000002U}, /* SEC_MODID[563]:AXIFBABUSTOP1*/ + [564] = {0xFF863438U, 0x00000002U}, /* SEC_MODID[564]:ARSTM2*/ + [565] = {0xFF86343CU, 0x00000002U}, /* SEC_MODID[565]:ARSTM3*/ + [566] = {0xFF863440U, 0x00000002U}, /* SEC_MODID[566]:ARSTM4*/ + [567] = {0xFF863444U, 0x00000002U}, /* SEC_MODID[567]:ARSTM5*/ + [568] = {0xFF863448U, 0x00000002U}, /* SEC_MODID[568]:ARSTM6*/ + [569] = {0xFF86344CU, 0x00000002U}, /* SEC_MODID[569]:ARSTM7*/ + [570] = {0xFF863450U, 0x00000002U}, /* SEC_MODID[570]:ARSTM8*/ + [571] = {0xFF863454U, 0x00000002U}, /* SEC_MODID[571]:ECMTOP*/ + [572] = {0xFF863458U, 0x00000002U}, /* SEC_MODID[572]:FBA*/ + [573] = {0xFF86345CU, 0x00000002U}, /* SEC_MODID[573]:FBC*/ + [574] = {0xFF863460U, 0x00000002U}, /* SEC_MODID[574]:AXICCI00*/ + [575] = {0xFF863464U, 0x00000002U}, /* SEC_MODID[575]:AXICCI01*/ + [576] = {0xFF863468U, 0x00000002U}, /* SEC_MODID[576]:AXICCI10*/ + [577] = {0xFF86346CU, 0x00000002U}, /* SEC_MODID[577]:AXICCI11*/ + [578] = {0xFF863470U, 0x00000002U}, /* SEC_MODID[578]:AXICCI12*/ + [579] = {0xFF863474U, 0x00000002U}, /* SEC_MODID[579]:AXICCI13*/ + [580] = {0xFF863478U, 0x00000002U}, /* SEC_MODID[580]:AXICCI14*/ + [581] = {0xFF86347CU, 0x00000002U}, /* SEC_MODID[581]:AXICCI15*/ + [582] = {0xFF863480U, 0x00000002U}, /* SEC_MODID[582]:AXICCI2*/ + [583] = {0xFF863484U, 0x00000002U}, /* SEC_MODID[583]:AXICCI3*/ + [584] = {0xFF863488U, 0x00000002U}, /* SEC_MODID[584]:AXICCI4*/ + [585] = {0xFF86348CU, 0x00000002U}, /* SEC_MODID[585]:AXICCI5*/ + [586] = {0xFF863490U, 0x00000002U}, /* SEC_MODID[586]:AXICCI6*/ + [587] = {0xFF863494U, 0x00000002U}, /* SEC_MODID[587]:AXICCI7*/ + [588] = {0xFF863498U, 0x00000002U}, /* SEC_MODID[588]:AXICCI8*/ + [589] = {0xFF86349CU, 0x00000002U}, /* SEC_MODID[589]:AXICCI9*/ + [590] = {0xFF8634A0U, 0x00000002U}, /* SEC_MODID[590]:ECMSTM*/ + [591] = {0xE7783400U, 0x00000002U}, /* SEC_MODID[591]:DMASSI00*/ + [592] = {0xE7783404U, 0x00000002U}, /* SEC_MODID[592]:DMASSI01*/ + [593] = {0xE7783408U, 0x00000002U}, /* SEC_MODID[593]:DMASSI02*/ + [594] = {0xE778340CU, 0x00000002U}, /* SEC_MODID[594]:DMASSI03*/ + [595] = {0xE7783410U, 0x00000002U}, /* SEC_MODID[595]:DMASSI04*/ + [596] = {0xE7783414U, 0x00000002U}, /* SEC_MODID[596]:DMAI2C0*/ + [597] = {0xE7783418U, 0x00000002U}, /* SEC_MODID[597]:DMAI2C1*/ + [598] = {0xE778341CU, 0x00000002U}, /* SEC_MODID[598]:DMAI2C2*/ + [599] = {0xE7783420U, 0x00000002U}, /* SEC_MODID[599]:DMAI2C3*/ + [600] = {0xE7783424U, 0x00000002U}, /* SEC_MODID[600]:DMAI2C4*/ + [601] = {0xE7783428U, 0x00000002U}, /* SEC_MODID[601]:DMAI2C5*/ + [602] = {0xE778342CU, 0x00000002U}, /* SEC_MODID[602]:DMASSI05*/ + [603] = {0xE7783430U, 0x00000002U}, /* SEC_MODID[603]:DMASSI06*/ + [604] = {0xE7783434U, 0x00000002U}, /* SEC_MODID[604]:DMASSI07*/ + [605] = {0xE67C3400U, 0x00000002U}, /* SEC_MODID[605]:ARMM*/ + [606] = {0xE67C3404U, 0x00000002U}, /* SEC_MODID[606]:AXIARNMM*/ + [607] = {0xE67C3408U, 0x00000002U}, /* SEC_MODID[607]:ARSM0*/ + [608] = {0xE67C340CU, 0x00000002U}, /* SEC_MODID[608]:ARSM1*/ + [609] = {0xE67C3410U, 0x00000002U}, /* SEC_MODID[609]:ARSM2*/ + [610] = {0xE67C3414U, 0x00000002U}, /* SEC_MODID[610]:AXIQOS0*/ + [611] = {0xE67C3418U, 0x00000002U}, /* SEC_MODID[611]:AXIQOS1*/ + [612] = {0xE67C341CU, 0x00000002U}, /* SEC_MODID[612]:AXIQOS2*/ + [613] = {0xE67C3420U, 0x00000002U}, /* SEC_MODID[613]:AXIQOS3*/ + [614] = {0xE67C3424U, 0x00000002U}, /* SEC_MODID[614]:AXIQOS4*/ + [615] = {0xE67C3428U, 0x00000002U}, /* SEC_MODID[615]:AXIQOS5*/ + [616] = {0xE67C342CU, 0x00000002U}, /* SEC_MODID[616]:AXIQOS6*/ + [617] = {0xE67C3430U, 0x00000002U}, /* SEC_MODID[617]:AXIQOS7*/ + [618] = {0xE67C3434U, 0x00000002U}, /* SEC_MODID[618]:ARSM3*/ + [619] = {0xE67C3438U, 0x00000002U}, /* SEC_MODID[619]:ARSM4*/ + [620] = {0xE67C343CU, 0x00000002U}, /* SEC_MODID[620]:ARSM5*/ + [621] = {0xE67C3440U, 0x00000002U}, /* SEC_MODID[621]:ARSM6*/ + [622] = {0xE67C3444U, 0x00000002U}, /* SEC_MODID[622]:ARSM7*/ + [623] = {0xE67C3448U, 0x00000002U}, /* SEC_MODID[623]:ARSM8*/ + [624] = {0xE67C344CU, 0x00000000U}, /* SEC_MODID[624]:AXMM0*/ + [625] = {0xE67C3450U, 0x00000000U}, /* SEC_MODID[625]:AXMM1*/ + [626] = {0xE67C3454U, 0x00000002U}, /* SEC_MODID[626]:AXMMPMON*/ + [627] = {0xE67C3458U, 0x00000002U}, /* SEC_MODID[627]:CKMMM*/ + [628] = {0xE67C345CU, 0x00000002U}, /* SEC_MODID[628]:ECMMM*/ + [629] = {0xE67C3460U, 0x00000002U}, /* SEC_MODID[629]:FBADBSC0*/ + [630] = {0xE67C3464U, 0x00000002U}, /* SEC_MODID[630]:FBADBSC1*/ + [631] = {0xE67C3468U, 0x00000002U}, /* SEC_MODID[631]:FBAMM*/ + [632] = {0xE67C346CU, 0x00000002U}, /* SEC_MODID[632]:IPMMUMM00*/ + [633] = {0xE67C3470U, 0x00000002U}, /* SEC_MODID[633]:DBS0A0*/ + [634] = {0xE67C3474U, 0x00000002U}, /* SEC_MODID[634]:DBS0A1*/ + [635] = {0xE67C3478U, 0x00000002U}, /* SEC_MODID[635]:DBS1A0*/ + [636] = {0xE67C347CU, 0x00000002U}, /* SEC_MODID[636]:DBS1A1*/ + [637] = {0xE67C3480U, 0x00000002U}, /* SEC_MODID[637]:AXCIDBS*/ + [638] = {0xE67C3484U, 0x00000002U}, /* SEC_MODID[638]:FCPRC*/ + [639] = {0xE67C3488U, 0x00000002U}, /* SEC_MODID[639]:DBS0D0*/ + [640] = {0xE67C348CU, 0x00000002U}, /* SEC_MODID[640]:DBS0D1*/ + [641] = {0xE67C3490U, 0x00000002U}, /* SEC_MODID[641]:DBS1D0*/ + [642] = {0xE67C3494U, 0x00000002U}, /* SEC_MODID[642]:DBS1D1*/ + [643] = {0xE67C3498U, 0x00000002U}, /* SEC_MODID[643]:FBADDR*/ + [644] = {0xE67C349CU, 0x00000002U}, /* SEC_MODID[644]:IPMMUMM01*/ + [645] = {0xE67C34A0U, 0x00000002U}, /* SEC_MODID[645]:IPMMUMM10*/ + [646] = {0xE67C34A4U, 0x00000002U}, /* SEC_MODID[646]:IPMMUMM11*/ + [647] = {0xE67C34A8U, 0x00000002U}, /* SEC_MODID[647]:IPMMUMM12*/ + [648] = {0xE67C34ACU, 0x00000002U}, /* SEC_MODID[648]:IPMMUMM13*/ + [649] = {0xE67C34B0U, 0x00000002U}, /* SEC_MODID[649]:IPMMUMM14*/ + [650] = {0xE67C34B4U, 0x00000002U}, /* SEC_MODID[650]:IPMMUMM15*/ + [651] = {0xE67C34B8U, 0x00000002U}, /* SEC_MODID[651]:IPMMUMM02*/ + [652] = {0xE67C34BCU, 0x00000002U}, /* SEC_MODID[652]:IPMMUMM03*/ + [653] = {0xE67C34C0U, 0x00000002U}, /* SEC_MODID[653]:IPMMUMM04*/ + [654] = {0xE67C34C4U, 0x00000002U}, /* SEC_MODID[654]:IPMMUMM05*/ + [655] = {0xE67C34C8U, 0x00000002U}, /* SEC_MODID[655]:IPMMUMM06*/ + [656] = {0xE67C34CCU, 0x00000002U}, /* SEC_MODID[656]:IPMMUMM07*/ + [657] = {0xE67C34D0U, 0x00000002U}, /* SEC_MODID[657]:IPMMUMM08*/ + [658] = {0xE67C34D4U, 0x00000002U}, /* SEC_MODID[658]:IPMMUMM09*/ + [659] = {0xFF803400U, 0x00000002U}, /* SEC_MODID[659]:ARSN0*/ + [660] = {0xFF803404U, 0x00000002U}, /* SEC_MODID[660]:ARSN1*/ + [661] = {0xFF803408U, 0x00000002U}, /* SEC_MODID[661]:ARSN2*/ + [662] = {0xFF80340CU, 0x00000002U}, /* SEC_MODID[662]:ARSN3*/ + [663] = {0xFF803410U, 0x00000002U}, /* SEC_MODID[663]:ARSN4*/ + [664] = {0xFF803414U, 0x00000002U}, /* SEC_MODID[664]:ARSN5*/ + [665] = {0xFF803418U, 0x00000002U}, /* SEC_MODID[665]:ARSN6*/ + [666] = {0xFF80341CU, 0x00000002U}, /* SEC_MODID[666]:ARSN7*/ + [667] = {0xFF803420U, 0x00000002U}, /* SEC_MODID[667]:ARSN8*/ + [668] = {0xFF803424U, 0x00000002U}, /* SEC_MODID[668]:ECMTOP3*/ + [669] = {0xE7753400U, 0x00000002U}, /* SEC_MODID[669]:ARSD00*/ + [670] = {0xE7753404U, 0x00000002U}, /* SEC_MODID[670]:ARSD01*/ + [671] = {0xE7753408U, 0x00000002U}, /* SEC_MODID[671]:ARSD02*/ + [672] = {0xE775340CU, 0x00000002U}, /* SEC_MODID[672]:ARSD03*/ + [673] = {0xE7753410U, 0x00000002U}, /* SEC_MODID[673]:ARSD04*/ + [674] = {0xE7753414U, 0x00000002U}, /* SEC_MODID[674]:ARSD05*/ + [675] = {0xE7753418U, 0x00000002U}, /* SEC_MODID[675]:ARSD06*/ + [676] = {0xE775341CU, 0x00000002U}, /* SEC_MODID[676]:AXIFRAY*/ + [677] = {0xE7753420U, 0x00000002U}, /* SEC_MODID[677]:AXIIPC*/ + [678] = {0xE7753428U, 0x00000002U}, /* SEC_MODID[678]:AXIRPC*/ + [679] = {0xE775342CU, 0x00000002U}, /* SEC_MODID[679]:AXISDHI0*/ + [680] = {0xE7753430U, 0x00000002U}, /* SEC_MODID[680]:ARSD07*/ + [681] = {0xE7753434U, 0x00000002U}, /* SEC_MODID[681]:ARSD08*/ + [682] = {0xE7753438U, 0x00000002U}, /* SEC_MODID[682]:ARSP00*/ + [683] = {0xE775343CU, 0x00000002U}, /* SEC_MODID[683]:ARSP01*/ + [684] = {0xE7753440U, 0x00000002U}, /* SEC_MODID[684]:ARSP02*/ + [685] = {0xE7753444U, 0x00000002U}, /* SEC_MODID[685]:ARSP03*/ + [686] = {0xE7753448U, 0x00000002U}, /* SEC_MODID[686]:ARSP04*/ + [687] = {0xE775344CU, 0x00000002U}, /* SEC_MODID[687]:ARSP05*/ + [688] = {0xE7753450U, 0x00000002U}, /* SEC_MODID[688]:ARSP06*/ + [689] = {0xE7753454U, 0x00000002U}, /* SEC_MODID[689]:ARSP07*/ + [690] = {0xE7753458U, 0x00000002U}, /* SEC_MODID[690]:ARSP08*/ + [691] = {0xE775345CU, 0x00000002U}, /* SEC_MODID[691]:IPMMUDS001*/ + [692] = {0xE7753460U, 0x00000002U}, /* SEC_MODID[692]:CKMPER0*/ + [693] = {0xE7753464U, 0x00000002U}, /* SEC_MODID[693]:ECMPER0*/ + [694] = {0xE7753468U, 0x00000002U}, /* SEC_MODID[694]:FBAPER0*/ + [695] = {0xE775346CU, 0x00000002U}, /* SEC_MODID[695]:FSO0*/ + [696] = {0xE7753470U, 0x00000002U}, /* SEC_MODID[696]:FSO1*/ + [697] = {0xE7753474U, 0x00000002U}, /* SEC_MODID[697]:FSO10*/ + [698] = {0xE7753478U, 0x00000002U}, /* SEC_MODID[698]:FSO2*/ + [699] = {0xE775347CU, 0x00000002U}, /* SEC_MODID[699]:FSO3*/ + [700] = {0xE7753480U, 0x00000002U}, /* SEC_MODID[700]:FSO4*/ + [701] = {0xE7753484U, 0x00000002U}, /* SEC_MODID[701]:FSO5*/ + [702] = {0xE7753488U, 0x00000002U}, /* SEC_MODID[702]:FSO6*/ + [703] = {0xE775348CU, 0x00000002U}, /* SEC_MODID[703]:FSO7*/ + [704] = {0xE7753490U, 0x00000002U}, /* SEC_MODID[704]:FSO8*/ + [705] = {0xE7753494U, 0x00000002U}, /* SEC_MODID[705]:FSO9*/ + [706] = {0xE7753498U, 0x00000002U}, /* SEC_MODID[706]:ADG*/ + [707] = {0xE775349CU, 0x00000002U}, /* SEC_MODID[707]:ECMSD0*/ + [708] = {0xE77534A0U, 0x00000002U}, /* SEC_MODID[708]:IPMMUDS010*/ + [709] = {0xE77534A4U, 0x00000002U}, /* SEC_MODID[709]:IPMMUDS011*/ + [710] = {0xE77534A8U, 0x00000002U}, /* SEC_MODID[710]:I2C0*/ + [711] = {0xE77534ACU, 0x00000002U}, /* SEC_MODID[711]:I2C1*/ + [712] = {0xE77534B0U, 0x00000002U}, /* SEC_MODID[712]:I2C2*/ + [713] = {0xE77534B4U, 0x00000002U}, /* SEC_MODID[713]:I2C3*/ + [714] = {0xE77534B8U, 0x00000002U}, /* SEC_MODID[714]:I2C4*/ + [715] = {0xE77534BCU, 0x00000002U}, /* SEC_MODID[715]:I2C5*/ + [716] = {0xE77534C0U, 0x00000002U}, /* SEC_MODID[716]:IPMMUDS012*/ + [717] = {0xE77534C4U, 0x00000002U}, /* SEC_MODID[717]:IPC*/ + [718] = {0xE77534C8U, 0x00000002U}, /* SEC_MODID[718]:IPMMUDS000*/ + [719] = {0xE77534CCU, 0x00000002U}, /* SEC_MODID[719]:IPMMUDS013*/ + [720] = {0xE77534D0U, 0x00000002U}, /* SEC_MODID[720]:IPMMUDS014*/ + [721] = {0xE77534D4U, 0x00000002U}, /* SEC_MODID[721]:IPMMUDS015*/ + [722] = {0xE77534D8U, 0x00000002U}, /* SEC_MODID[722]:IPMMUDS002*/ + [723] = {0xE77534DCU, 0x00000002U}, /* SEC_MODID[723]:IPMMUDS003*/ + [724] = {0xE77534E0U, 0x00000002U}, /* SEC_MODID[724]:IPMMUDS004*/ + [725] = {0xE77534E4U, 0x00000002U}, /* SEC_MODID[725]:IPMMUDS005*/ + [726] = {0xE77534E8U, 0x00000002U}, /* SEC_MODID[726]:SSI*/ + [727] = {0xE77534ECU, 0x00000002U}, /* SEC_MODID[727]:IPMMUDS006*/ + [728] = {0xE77534F0U, 0x00000002U}, /* SEC_MODID[728]:IPMMUDS007*/ + [729] = {0xE77534F4U, 0x00000002U}, /* SEC_MODID[729]:SYDM1P*/ + [730] = {0xE77534F8U, 0x00000002U}, /* SEC_MODID[730]:IPMMUDS008*/ + [731] = {0xE77534FCU, 0x00000002U}, /* SEC_MODID[731]:SYDM2P*/ + [732] = {0xE7753500U, 0x00000002U}, /* SEC_MODID[732]:IPMMUDS009*/ + [733] = {0xE7753640U, 0x00000002U}, /* SEC_MODID[733]:SYDM100*/ + [734] = {0xE7753644U, 0x00000002U}, /* SEC_MODID[734]:SYDM101*/ + [735] = {0xE7753648U, 0x00000002U}, /* SEC_MODID[735]:SYDM110*/ + [736] = {0xE775364CU, 0x00000002U}, /* SEC_MODID[736]:SYDM111*/ + [737] = {0xE7753650U, 0x00000002U}, /* SEC_MODID[737]:SYDM112*/ + [738] = {0xE7753654U, 0x00000002U}, /* SEC_MODID[738]:SYDM113*/ + [739] = {0xE7753658U, 0x00000002U}, /* SEC_MODID[739]:SYDM114*/ + [740] = {0xE775365CU, 0x00000002U}, /* SEC_MODID[740]:SYDM115*/ + [741] = {0xE7753660U, 0x00000002U}, /* SEC_MODID[741]:SYDM102*/ + [742] = {0xE7753664U, 0x00000002U}, /* SEC_MODID[742]:SYDM103*/ + [743] = {0xE7753668U, 0x00000002U}, /* SEC_MODID[743]:SYDM104*/ + [744] = {0xE775366CU, 0x00000002U}, /* SEC_MODID[744]:SYDM105*/ + [745] = {0xE7753670U, 0x00000002U}, /* SEC_MODID[745]:SYDM106*/ + [746] = {0xE7753674U, 0x00000002U}, /* SEC_MODID[746]:SYDM107*/ + [747] = {0xE7753678U, 0x00000002U}, /* SEC_MODID[747]:SYDM108*/ + [748] = {0xE775367CU, 0x00000002U}, /* SEC_MODID[748]:SYDM109*/ + [749] = {0xE7753680U, 0x00000002U}, /* SEC_MODID[749]:SYDM200*/ + [750] = {0xE7753684U, 0x00000002U}, /* SEC_MODID[750]:SYDM201*/ + [751] = {0xE7753688U, 0x00000002U}, /* SEC_MODID[751]:SYDM210*/ + [752] = {0xE775368CU, 0x00000002U}, /* SEC_MODID[752]:SYDM211*/ + [753] = {0xE7753690U, 0x00000002U}, /* SEC_MODID[753]:SYDM212*/ + [754] = {0xE7753694U, 0x00000002U}, /* SEC_MODID[754]:SYDM213*/ + [755] = {0xE7753698U, 0x00000002U}, /* SEC_MODID[755]:SYDM214*/ + [756] = {0xE775369CU, 0x00000002U}, /* SEC_MODID[756]:SYDM215*/ + [757] = {0xE77536A0U, 0x00000002U}, /* SEC_MODID[757]:SYDM202*/ + [758] = {0xE77536A4U, 0x00000002U}, /* SEC_MODID[758]:SYDM203*/ + [759] = {0xE77536A8U, 0x00000002U}, /* SEC_MODID[759]:SYDM204*/ + [760] = {0xE77536ACU, 0x00000002U}, /* SEC_MODID[760]:SYDM205*/ + [761] = {0xE77536B0U, 0x00000002U}, /* SEC_MODID[761]:SYDM206*/ + [762] = {0xE77536B4U, 0x00000002U}, /* SEC_MODID[762]:SYDM207*/ + [763] = {0xE77536B8U, 0x00000002U}, /* SEC_MODID[763]:SYDM208*/ + [764] = {0xE77536BCU, 0x00000002U}, /* SEC_MODID[764]:SYDM209*/ + [765] = {0xFE683400U, 0x00000002U}, /* SEC_MODID[765]:ARVC0*/ + [766] = {0xFE683404U, 0x00000002U}, /* SEC_MODID[766]:ARVC1*/ + [767] = {0xFE683408U, 0x00000002U}, /* SEC_MODID[767]:ARVC2*/ + [768] = {0xFE68340CU, 0x00000002U}, /* SEC_MODID[768]:ARVC3*/ + [769] = {0xFE683410U, 0x00000002U}, /* SEC_MODID[769]:AXIFBABUSVC*/ + [770] = {0xFE683414U, 0x00000002U}, /* SEC_MODID[770]:ARVC4*/ + [771] = {0xFE683418U, 0x00000002U}, /* SEC_MODID[771]:ARVC5*/ + [772] = {0xFE68341CU, 0x00000002U}, /* SEC_MODID[772]:ARVC6*/ + [773] = {0xFE683420U, 0x00000002U}, /* SEC_MODID[773]:ARVC7*/ + [774] = {0xFE683424U, 0x00000002U}, /* SEC_MODID[774]:ARVC8*/ + [775] = {0xFE683428U, 0x00000002U}, /* SEC_MODID[775]:CKMVC*/ + [776] = {0xFE68342CU, 0x00000002U}, /* SEC_MODID[776]:ECMVC0*/ + [777] = {0xFE683430U, 0x00000002U}, /* SEC_MODID[777]:IMR2*/ + [778] = {0xFE683434U, 0x00000002U}, /* SEC_MODID[778]:IMR0*/ + [779] = {0xFE683438U, 0x00000002U}, /* SEC_MODID[779]:IMR1*/ + [780] = {0xFE68343CU, 0x00000002U}, /* SEC_MODID[780]:IPMMUVC01*/ + [781] = {0xFE683440U, 0x00000002U}, /* SEC_MODID[781]:IPMMUVC10*/ + [782] = {0xFE683444U, 0x00000002U}, /* SEC_MODID[782]:IMS0*/ + [783] = {0xFE683448U, 0x00000002U}, /* SEC_MODID[783]:IMS1*/ + [784] = {0xFE68344CU, 0x00000002U}, /* SEC_MODID[784]:IPMMUVC00*/ + [785] = {0xFE683450U, 0x00000002U}, /* SEC_MODID[785]:IPMMUVC11*/ + [786] = {0xFE683454U, 0x00000002U}, /* SEC_MODID[786]:IPMMUVC12*/ + [787] = {0xFE683458U, 0x00000002U}, /* SEC_MODID[787]:IPMMUVC13*/ + [788] = {0xFE68345CU, 0x00000002U}, /* SEC_MODID[788]:IPMMUVC14*/ + [789] = {0xFE683460U, 0x00000002U}, /* SEC_MODID[789]:IPMMUVC15*/ + [790] = {0xFE683464U, 0x00000002U}, /* SEC_MODID[790]:IPMMUVC02*/ + [791] = {0xFE683468U, 0x00000002U}, /* SEC_MODID[791]:IPMMUVC03*/ + [792] = {0xFE68346CU, 0x00000002U}, /* SEC_MODID[792]:IPMMUVC04*/ + [793] = {0xFE683470U, 0x00000002U}, /* SEC_MODID[793]:IPMMUVC05*/ + [794] = {0xFE683474U, 0x00000002U}, /* SEC_MODID[794]:IPMMUVC06*/ + [795] = {0xFE683478U, 0x00000002U}, /* SEC_MODID[795]:IPMMUVC07*/ + [796] = {0xFE68347CU, 0x00000002U}, /* SEC_MODID[796]:IPMMUVC08*/ + [797] = {0xFE683480U, 0x00000002U}, /* SEC_MODID[797]:IPMMUVC09*/ + [798] = {0xFE683484U, 0x00000002U}, /* SEC_MODID[798]:IV1ES*/ + [799] = {0xFEBE3400U, 0x00000002U}, /* SEC_MODID[799]:CSITOP0*/ + [800] = {0xFEBE3404U, 0x00000002U}, /* SEC_MODID[800]:ARVI10*/ + [801] = {0xFEBE3408U, 0x00000002U}, /* SEC_MODID[801]:ARVI11*/ + [802] = {0xFEBE340CU, 0x00000002U}, /* SEC_MODID[802]:ARVI12*/ + [803] = {0xFEBE3410U, 0x00000002U}, /* SEC_MODID[803]:ARVI13*/ + [804] = {0xFEBE3414U, 0x00000002U}, /* SEC_MODID[804]:ARVI14*/ + [805] = {0xFEBE3418U, 0x00000002U}, /* SEC_MODID[805]:ARVI15*/ + [806] = {0xFEBE341CU, 0x00000002U}, /* SEC_MODID[806]:ARVI16*/ + [807] = {0xFEBE3420U, 0x00000002U}, /* SEC_MODID[807]:ARVI17*/ + [808] = {0xFEBE3424U, 0x00000002U}, /* SEC_MODID[808]:ARVI18*/ + [809] = {0xFEBE3428U, 0x00000002U}, /* SEC_MODID[809]:CKMVIO*/ + [810] = {0xFEBE342CU, 0x00000002U}, /* SEC_MODID[810]:CSITOP1*/ + [811] = {0xFEBE3434U, 0x00000002U}, /* SEC_MODID[811]:DSITLINK0*/ + [812] = {0xFEBE3438U, 0x00000002U}, /* SEC_MODID[812]:DSITLINK1*/ + [813] = {0xFEBE343CU, 0x00000002U}, /* SEC_MODID[813]:ECMVIO1*/ + [814] = {0xFEBE3444U, 0x00000002U}, /* SEC_MODID[814]:IPMMUVI001*/ + [815] = {0xFEBE3448U, 0x00000002U}, /* SEC_MODID[815]:FCPVX0*/ + [816] = {0xFEBE344CU, 0x00000002U}, /* SEC_MODID[816]:FCPVX1*/ + [817] = {0xFEBE3458U, 0x00000002U}, /* SEC_MODID[817]:IPMMUVI000*/ + [818] = {0xFEBE345CU, 0x00000002U}, /* SEC_MODID[818]:IPMMUVI100*/ + [819] = {0xFEBE3460U, 0x00000002U}, /* SEC_MODID[819]:IPMMUVI010*/ + [820] = {0xFEBE3464U, 0x00000002U}, /* SEC_MODID[820]:IPMMUVI011*/ + [821] = {0xFEBE3468U, 0x00000002U}, /* SEC_MODID[821]:VSPX0*/ + [822] = {0xFEBE346CU, 0x00000002U}, /* SEC_MODID[822]:VSPX1*/ + [823] = {0xFEBE3478U, 0x00000002U}, /* SEC_MODID[823]:IPMMUVI012*/ + [824] = {0xFEBE347CU, 0x00000002U}, /* SEC_MODID[824]:IPMMUVI013*/ + [825] = {0xFEBE3480U, 0x00000002U}, /* SEC_MODID[825]:IPMMUVI014*/ + [826] = {0xFEBE3484U, 0x00000002U}, /* SEC_MODID[826]:IPMMUVI015*/ + [827] = {0xFEBE3488U, 0x00000002U}, /* SEC_MODID[827]:IPMMUVI002*/ + [828] = {0xFEBE348CU, 0x00000002U}, /* SEC_MODID[828]:IPMMUVI003*/ + [829] = {0xFEBE3490U, 0x00000002U}, /* SEC_MODID[829]:IPMMUVI004*/ + [830] = {0xFEBE3494U, 0x00000002U}, /* SEC_MODID[830]:IPMMUVI005*/ + [831] = {0xFEBE3498U, 0x00000002U}, /* SEC_MODID[831]:IPMMUVI006*/ + [832] = {0xFEBE349CU, 0x00000002U}, /* SEC_MODID[832]:IPMMUVI007*/ + [833] = {0xFEBE34A0U, 0x00000002U}, /* SEC_MODID[833]:IPMMUVI008*/ + [834] = {0xFEBE34A4U, 0x00000002U}, /* SEC_MODID[834]:IPMMUVI009*/ + [835] = {0xFEBE34A8U, 0x00000002U}, /* SEC_MODID[835]:IPMMUVI101*/ + [836] = {0xFEBE34ACU, 0x00000002U}, /* SEC_MODID[836]:IPMMUVI110*/ + [837] = {0xFEBE34B0U, 0x00000002U}, /* SEC_MODID[837]:IPMMUVI111*/ + [838] = {0xFEBE34B4U, 0x00000002U}, /* SEC_MODID[838]:IPMMUVI112*/ + [839] = {0xFEBE34B8U, 0x00000002U}, /* SEC_MODID[839]:IPMMUVI113*/ + [840] = {0xFEBE34BCU, 0x00000002U}, /* SEC_MODID[840]:IPMMUVI114*/ + [841] = {0xFEBE34C0U, 0x00000002U}, /* SEC_MODID[841]:IPMMUVI115*/ + [842] = {0xFEBE34C4U, 0x00000002U}, /* SEC_MODID[842]:IPMMUVI102*/ + [843] = {0xFEBE34C8U, 0x00000002U}, /* SEC_MODID[843]:IPMMUVI103*/ + [844] = {0xFEBE34CCU, 0x00000002U}, /* SEC_MODID[844]:IPMMUVI104*/ + [845] = {0xFEBE34D0U, 0x00000002U}, /* SEC_MODID[845]:IPMMUVI105*/ + [846] = {0xFEBE34D4U, 0x00000002U}, /* SEC_MODID[846]:IPMMUVI106*/ + [847] = {0xFEBE34D8U, 0x00000002U}, /* SEC_MODID[847]:IPMMUVI107*/ + [848] = {0xFEBE34DCU, 0x00000002U}, /* SEC_MODID[848]:IPMMUVI108*/ + [849] = {0xFEBE34E0U, 0x00000002U}, /* SEC_MODID[849]:IPMMUVI109*/ + [850] = {0xFEBE3504U, 0x00000002U}, /* SEC_MODID[850]:AXIFBABUSVIO*/ + [851] = {0xFEBF3400U, 0x00000002U}, /* SEC_MODID[851]:ARVI0*/ + [852] = {0xFEBF3404U, 0x00000002U}, /* SEC_MODID[852]:ARVI1*/ + [853] = {0xFEBF3408U, 0x00000002U}, /* SEC_MODID[853]:ARVI2*/ + [854] = {0xFEBF340CU, 0x00000002U}, /* SEC_MODID[854]:ARVI3*/ + [855] = {0xFEBF3410U, 0x00000002U}, /* SEC_MODID[855]:ARVI4*/ + [856] = {0xFEBF3414U, 0x00000002U}, /* SEC_MODID[856]:ARVI5*/ + [857] = {0xFEBF3418U, 0x00000002U}, /* SEC_MODID[857]:ARVI6*/ + [858] = {0xFEBF341CU, 0x00000002U}, /* SEC_MODID[858]:ARVI7*/ + [859] = {0xFEBF3420U, 0x00000002U}, /* SEC_MODID[859]:ARVI8*/ + [860] = {0xFEBF3424U, 0x00000002U}, /* SEC_MODID[860]:ECMVIO0*/ + [861] = {0xFEBF3428U, 0x00000002U}, /* SEC_MODID[861]:ISP0*/ + [862] = {0xFEBF342CU, 0x00000002U}, /* SEC_MODID[862]:ISP0CORE*/ + [863] = {0xFEBF3430U, 0x00000002U}, /* SEC_MODID[863]:ISP1*/ + [864] = {0xFEBF3434U, 0x00000002U}, /* SEC_MODID[864]:ISP1CORE*/ + [865] = {0xFEBF3454U, 0x00000002U}, /* SEC_MODID[865]:VIN00*/ + [866] = {0xFEBF3458U, 0x00000002U}, /* SEC_MODID[866]:VIN01*/ + [867] = {0xFEBF345CU, 0x00000002U}, /* SEC_MODID[867]:VIN02*/ + [868] = {0xFEBF3460U, 0x00000002U}, /* SEC_MODID[868]:VIN03*/ + [869] = {0xFEBF3464U, 0x00000002U}, /* SEC_MODID[869]:VIN04*/ + [870] = {0xFEBF3468U, 0x00000002U}, /* SEC_MODID[870]:VIN05*/ + [871] = {0xFEBF346CU, 0x00000002U}, /* SEC_MODID[871]:VIN06*/ + [872] = {0xFEBF3470U, 0x00000002U}, /* SEC_MODID[872]:VIN07*/ + [873] = {0xFEBF3474U, 0x00000002U}, /* SEC_MODID[873]:VIN10*/ + [874] = {0xFEBF3478U, 0x00000002U}, /* SEC_MODID[874]:VIN11*/ + [875] = {0xFEBF347CU, 0x00000002U}, /* SEC_MODID[875]:VIN12*/ + [876] = {0xFEBF3480U, 0x00000002U}, /* SEC_MODID[876]:VIN13*/ + [877] = {0xFEBF3484U, 0x00000002U}, /* SEC_MODID[877]:VIN14*/ + [878] = {0xFEBF3488U, 0x00000002U}, /* SEC_MODID[878]:VIN15*/ + [879] = {0xFEBF348CU, 0x00000002U}, /* SEC_MODID[879]:VIN16*/ + [880] = {0xFEBF3490U, 0x00000002U}, /* SEC_MODID[880]:VIN17*/ + [881] = {0xE7B13400U, 0x00000002U}, /* SEC_MODID[881]:ARVIP00*/ + [882] = {0xE7B13404U, 0x00000002U}, /* SEC_MODID[882]:ARVIP01*/ + [883] = {0xE7B13408U, 0x00000002U}, /* SEC_MODID[883]:ARVIP02*/ + [884] = {0xE7B1340CU, 0x00000002U}, /* SEC_MODID[884]:ARVIP03*/ + [885] = {0xE7B13410U, 0x00000002U}, /* SEC_MODID[885]:AXIFBABUSVIP0*/ + [886] = {0xE7B13414U, 0x00000002U}, /* SEC_MODID[886]:ARVIP04*/ + [887] = {0xE7B13418U, 0x00000002U}, /* SEC_MODID[887]:ARVIP05*/ + [888] = {0xE7B1341CU, 0x00000002U}, /* SEC_MODID[888]:ARVIP06*/ + [889] = {0xE7B13420U, 0x00000002U}, /* SEC_MODID[889]:ARVIP07*/ + [890] = {0xE7B13424U, 0x00000002U}, /* SEC_MODID[890]:ARVIP08*/ + [891] = {0xE7B13428U, 0x00000002U}, /* SEC_MODID[891]:CKMVIP*/ + [892] = {0xE7B1342CU, 0x00000002U}, /* SEC_MODID[892]:ECMVIP0*/ + [893] = {0xE7B13430U, 0x00000002U}, /* SEC_MODID[893]:IPMMUVIP000*/ + [894] = {0xE7B13438U, 0x00000002U}, /* SEC_MODID[894]:SMPO0*/ + [895] = {0xE7B1343CU, 0x00000002U}, /* SEC_MODID[895]:SMPS0*/ + [896] = {0xE7B13440U, 0x00000002U}, /* SEC_MODID[896]:UMFL0*/ + [897] = {0xE7B13444U, 0x00000002U}, /* SEC_MODID[897]:IPMMUVIP001*/ + [898] = {0xE7B13448U, 0x00000002U}, /* SEC_MODID[898]:IPMMUVIP010*/ + [899] = {0xE7B1344CU, 0x00000002U}, /* SEC_MODID[899]:IPMMUVIP011*/ + [900] = {0xE7B13450U, 0x00000002U}, /* SEC_MODID[900]:UMFL0M_W*/ + [901] = {0xE7B13454U, 0x00000002U}, /* SEC_MODID[901]:IPMMUVIP012*/ + [902] = {0xE7B13458U, 0x00000002U}, /* SEC_MODID[902]:IPMMUVIP013*/ + [903] = {0xE7B1345CU, 0x00000002U}, /* SEC_MODID[903]:IPMMUVIP014*/ + [904] = {0xE7B13460U, 0x00000002U}, /* SEC_MODID[904]:IPMMUVIP015*/ + [905] = {0xE7B13464U, 0x00000002U}, /* SEC_MODID[905]:IPMMUVIP002*/ + [906] = {0xE7B13468U, 0x00000002U}, /* SEC_MODID[906]:IPMMUVIP003*/ + [907] = {0xE7B1346CU, 0x00000002U}, /* SEC_MODID[907]:IPMMUVIP004*/ + [908] = {0xE7B13470U, 0x00000002U}, /* SEC_MODID[908]:IPMMUVIP005*/ + [909] = {0xE7B13474U, 0x00000002U}, /* SEC_MODID[909]:IPMMUVIP006*/ + [910] = {0xE7B13478U, 0x00000002U}, /* SEC_MODID[910]:IPMMUVIP007*/ + [911] = {0xE7B1347CU, 0x00000002U}, /* SEC_MODID[911]:IPMMUVIP008*/ + [912] = {0xE7B13480U, 0x00000002U}, /* SEC_MODID[912]:IPMMUVIP009*/ + [913] = {0xE7B43400U, 0x00000002U}, /* SEC_MODID[913]:ARVIP10*/ + [914] = {0xE7B43404U, 0x00000002U}, /* SEC_MODID[914]:ARVIP11*/ + [915] = {0xE7B43408U, 0x00000002U}, /* SEC_MODID[915]:ARVIP12*/ + [916] = {0xE7B4340CU, 0x00000002U}, /* SEC_MODID[916]:ARVIP13*/ + [917] = {0xE7B43410U, 0x00000002U}, /* SEC_MODID[917]:AXIFBABUSVIP1*/ + [918] = {0xE7B43414U, 0x00000002U}, /* SEC_MODID[918]:ARVIIP14*/ + [919] = {0xE7B43418U, 0x00000002U}, /* SEC_MODID[919]:ARVIIP15*/ + [920] = {0xE7B4341CU, 0x00000002U}, /* SEC_MODID[920]:ARVIIP16*/ + [921] = {0xE7B43420U, 0x00000002U}, /* SEC_MODID[921]:ARVIIP17*/ + [922] = {0xE7B43424U, 0x00000002U}, /* SEC_MODID[922]:ARVIIP18*/ + [923] = {0xE7B43438U, 0x00000002U}, /* SEC_MODID[923]:ECMVIP1*/ + [924] = {0xE7B4343CU, 0x00000002U}, /* SEC_MODID[924]:IPMMUVIP101*/ + [925] = {0xE7B43440U, 0x00000002U}, /* SEC_MODID[925]:IPMMUVIP100*/ + [926] = {0xE7B43444U, 0x00000002U}, /* SEC_MODID[926]:IPMMUVIP110*/ + [927] = {0xE7B43448U, 0x00000002U}, /* SEC_MODID[927]:IPMMUVIP111*/ + [928] = {0xE7B4344CU, 0x00000002U}, /* SEC_MODID[928]:IPMMUVIP112*/ + [929] = {0xE7B43450U, 0x00000002U}, /* SEC_MODID[929]:IPMMUVIP113*/ + [930] = {0xE7B43454U, 0x00000002U}, /* SEC_MODID[930]:IPMMUVIP114*/ + [931] = {0xE7B43458U, 0x00000002U}, /* SEC_MODID[931]:IPMMUVIP115*/ + [932] = {0xE7B4345CU, 0x00000002U}, /* SEC_MODID[932]:IPMMUVIP102*/ + [933] = {0xE7B43460U, 0x00000002U}, /* SEC_MODID[933]:IPMMUVIP103*/ + [934] = {0xE7B43464U, 0x00000002U}, /* SEC_MODID[934]:IPMMUVIP104*/ + [935] = {0xE7B43468U, 0x00000002U}, /* SEC_MODID[935]:IPMMUVIP105*/ + [936] = {0xE7B4346CU, 0x00000002U}, /* SEC_MODID[936]:IPMMUVIP106*/ + [937] = {0xE7B43470U, 0x00000002U}, /* SEC_MODID[937]:IPMMUVIP107*/ + [938] = {0xE7B43474U, 0x00000002U}, /* SEC_MODID[938]:IPMMUVIP108*/ + [939] = {0xE7B43478U, 0x00000002U}, /* SEC_MODID[939]:IPMMUVIP109*/ + [940] = {0xE7B43518U, 0x00000002U}, /* SEC_MODID[940]:PAP*/ + [941] = {0xEB803400U, 0x00000002U}, /* SEC_MODID[941]:ARDSP0*/ + [942] = {0xEB803404U, 0x00000002U}, /* SEC_MODID[942]:ARDSP1*/ + [943] = {0xEB803408U, 0x00000002U}, /* SEC_MODID[943]:ARDSP2*/ + [944] = {0xEB80340CU, 0x00000002U}, /* SEC_MODID[944]:ARDSP3*/ + [945] = {0xEB803410U, 0x00000002U}, /* SEC_MODID[945]:ARDSP4*/ + [946] = {0xEB803414U, 0x00000002U}, /* SEC_MODID[946]:ARDSP5*/ + [947] = {0xEB803418U, 0x00000002U}, /* SEC_MODID[947]:ARDSP6*/ + [948] = {0xEB80341CU, 0x00000002U}, /* SEC_MODID[948]:ARDSP7*/ + [949] = {0xEB803420U, 0x00000002U}, /* SEC_MODID[949]:ECMDSP*/ + [950] = {0xEB803424U, 0x00000002U}, /* SEC_MODID[950]:AXIDSP0*/ + [951] = {0xEB803428U, 0x00000002U}, /* SEC_MODID[951]:AXIDSP1*/ + [952] = {0xEB80342CU, 0x00000002U}, /* SEC_MODID[952]:AXIDSP2*/ + [953] = {0xEB803430U, 0x00000002U}, /* SEC_MODID[953]:AXIDSP3*/ + [955] = {0xE67B9624U, 0x00000001U}, /* SEC_MODID[954]:ARCC*/ + [954] = {0xE67B9638U, 0x00000001U}, /* SEC_MODID[955]:ARRTRAM*/ + [956] = {0xE7753424U, 0x00000002U}, /* SEC_MODID[956]:RSV0*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_axi_tbl" +#else +__attribute__ ((section(".rgid_axi_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[] = { + [0] = {0xFFC82010U, 0x0000000FU}, /* RGIDR_MODID[4]:ARRT01*/ + [1] = {0xFFC82014U, 0x0000000FU}, /* RGIDR_MODID[5]:ARRT02*/ + [2] = {0xE6002048U, 0x0000000FU}, /* RGIDR_MODID[42]:ARS01*/ + [3] = {0xE600204CU, 0x0000000FU}, /* RGIDR_MODID[43]:ARS02*/ + [4] = {0xE7762028U, 0x0000000FU}, /* RGIDR_MODID[106]:ARSP31*/ + [5] = {0xE776202CU, 0x0000000FU}, /* RGIDR_MODID[107]:ARSP32*/ + [6] = {0xE7792004U, 0x0000000FU}, /* RGIDR_MODID[121]:ARSP41*/ + [7] = {0xE7792008U, 0x0000000FU}, /* RGIDR_MODID[122]:ARSP42*/ + [8] = {0xFE672004U, 0x0000002FU}, /* RGIDR_MODID[165]:ARVC11*/ + [9] = {0xFE672008U, 0x0000002FU}, /* RGIDR_MODID[166]:ARVC12*/ + [10] = {0xFEBD2004U, 0x0000000FU}, /* RGIDR_MODID[178]:ARVI41*/ + [11] = {0xFEBD2008U, 0x0000000FU}, /* RGIDR_MODID[179]:ARVI42*/ + [12] = {0xE6582140U, 0x0000000FU}, /* RGIDR_MODID[245]:ARHC1*/ + [13] = {0xE6582144U, 0x0000000FU}, /* RGIDR_MODID[246]:ARHC2*/ + [14] = {0xFF882004U, 0x0000000FU}, /* RGIDR_MODID[261]:ARIMP01*/ + [15] = {0xFF882008U, 0x0000000FU}, /* RGIDR_MODID[262]:ARIMP02*/ + [16] = {0xFD812004U, 0x0000000FU}, /* RGIDR_MODID[297]:ARPV1*/ + [17] = {0xFD81200CU, 0x0000000FU}, /* RGIDR_MODID[299]:ARPV2*/ + [18] = {0xE6622004U, 0x0000000FU}, /* RGIDR_MODID[330]:ARRC1*/ + [19] = {0xE6622008U, 0x0000000FU}, /* RGIDR_MODID[331]:ARRC2*/ + [20] = {0xFFC42060U, 0x0000000FU}, /* RGIDR_MODID[369]:ARRD1*/ + [21] = {0xFFC42064U, 0x0000000FU}, /* RGIDR_MODID[370]:ARRD2*/ + [22] = {0xFFC42084U, 0x0000000FU}, /* RGIDR_MODID[378]:ARRT1*/ + [23] = {0xFFC42088U, 0x0000000FU}, /* RGIDR_MODID[379]:ARRT2*/ + [26] = {0xFF862004U, 0x0000000FU}, /* RGIDR_MODID[551]:ARSC1*/ + [27] = {0xFF862008U, 0x0000000FU}, /* RGIDR_MODID[552]:ARSC2*/ + [24] = {0xFF862028U, 0x0000000FU}, /* RGIDR_MODID[560]:ARSTM1*/ + [25] = {0xFF862038U, 0x0000000FU}, /* RGIDR_MODID[564]:ARSTM2*/ + [28] = {0xE67C2004U, 0x0000000FU}, /* RGIDR_MODID[606]:AXIARNMM*/ + [29] = {0xE67C200CU, 0x0000000FU}, /* RGIDR_MODID[608]:ARSM1*/ + [30] = {0xE67C2010U, 0x0000000FU}, /* RGIDR_MODID[609]:ARSM2*/ + [31] = {0xFF802004U, 0x0000000FU}, /* RGIDR_MODID[660]:ARSN1*/ + [32] = {0xFF802008U, 0x0000000FU}, /* RGIDR_MODID[661]:ARSN2*/ + [33] = {0xE7752004U, 0x0000000FU}, /* RGIDR_MODID[670]:ARSD01*/ + [34] = {0xE7752008U, 0x0000000FU}, /* RGIDR_MODID[671]:ARSD02*/ + [35] = {0xE775203CU, 0x0000000FU}, /* RGIDR_MODID[683]:ARSP01*/ + [36] = {0xE7752040U, 0x0000000FU}, /* RGIDR_MODID[684]:ARSP02*/ + [37] = {0xFE682004U, 0x0000000FU}, /* RGIDR_MODID[766]:ARVC1*/ + [38] = {0xFE682008U, 0x0000000FU}, /* RGIDR_MODID[767]:ARVC2*/ + [39] = {0xFEBE2008U, 0x0000000FU}, /* RGIDR_MODID[801]:ARVI11*/ + [40] = {0xFEBE200CU, 0x0000000FU}, /* RGIDR_MODID[802]:ARVI12*/ + [41] = {0xFEBF2004U, 0x0000000FU}, /* RGIDR_MODID[852]:ARVI1*/ + [42] = {0xFEBF2008U, 0x0000000FU}, /* RGIDR_MODID[853]:ARVI2*/ + [43] = {0xE7B12004U, 0x0000000FU}, /* RGIDR_MODID[882]:ARVIP01*/ + [44] = {0xE7B12008U, 0x0000000FU}, /* RGIDR_MODID[883]:ARVIP02*/ + [45] = {0xE7B42004U, 0x0000000FU}, /* RGIDR_MODID[914]:ARVIP11*/ + [46] = {0xE7B42008U, 0x0000000FU}, /* RGIDR_MODID[915]:ARVIP12*/ + [47] = {0xEB802004U, 0x0000000FU}, /* RGIDR_MODID[942]:ARDSP1*/ + [48] = {0xEB802008U, 0x0000000FU}, /* RGIDR_MODID[943]:ARDSP2*/ + [49] = {0xFFC82410U, 0x00000000U}, /* RGIDW_MODID[4]:ARRT01*/ + [50] = {0xFFC82414U, 0x00000000U}, /* RGIDW_MODID[5]:ARRT02*/ + [51] = {0xE6002448U, 0x00000000U}, /* RGIDW_MODID[42]:ARS01*/ + [52] = {0xE600244CU, 0x00000000U}, /* RGIDW_MODID[43]:ARS02*/ + [53] = {0xE7762428U, 0x00000000U}, /* RGIDW_MODID[106]:ARSP31*/ + [54] = {0xE776242CU, 0x00000000U}, /* RGIDW_MODID[107]:ARSP32*/ + [55] = {0xE7792404U, 0x00000000U}, /* RGIDW_MODID[121]:ARSP41*/ + [56] = {0xE7792408U, 0x00000000U}, /* RGIDW_MODID[122]:ARSP42*/ + [57] = {0xFE672404U, 0x00000000U}, /* RGIDW_MODID[165]:ARVC11*/ + [58] = {0xFE672408U, 0x00000000U}, /* RGIDW_MODID[166]:ARVC12*/ + [59] = {0xFEBD2404U, 0x00000000U}, /* RGIDW_MODID[178]:ARVI41*/ + [60] = {0xFEBD2408U, 0x00000000U}, /* RGIDW_MODID[179]:ARVI42*/ + [61] = {0xE6582540U, 0x00000000U}, /* RGIDW_MODID[245]:ARHC1*/ + [62] = {0xE6582544U, 0x00000000U}, /* RGIDW_MODID[246]:ARHC2*/ + [63] = {0xFF882404U, 0x00000000U}, /* RGIDW_MODID[261]:ARIMP01*/ + [64] = {0xFF882408U, 0x00000000U}, /* RGIDW_MODID[262]:ARIMP02*/ + [65] = {0xFD812404U, 0x00000000U}, /* RGIDW_MODID[297]:ARPV1*/ + [66] = {0xFD81240CU, 0x00000000U}, /* RGIDW_MODID[299]:ARPV2*/ + [67] = {0xE6622404U, 0x00000000U}, /* RGIDW_MODID[330]:ARRC1*/ + [68] = {0xE6622408U, 0x00000000U}, /* RGIDW_MODID[331]:ARRC2*/ + [69] = {0xFFC42460U, 0x00000000U}, /* RGIDW_MODID[368]:ARRD1*/ + [70] = {0xFFC42464U, 0x00000000U}, /* RGIDW_MODID[369]:ARRD2*/ + [71] = {0xFFC42484U, 0x00000000U}, /* RGIDW_MODID[377]:ARRT1*/ + [72] = {0xFFC42488U, 0x00000000U}, /* RGIDW_MODID[378]:ARRT2*/ + [75] = {0xFF862404U, 0x00000000U}, /* RGIDW_MODID[550]:ARSC1*/ + [76] = {0xFF862408U, 0x00000000U}, /* RGIDW_MODID[551]:ARSC2*/ + [73] = {0xFF862428U, 0x00000000U}, /* RGIDW_MODID[559]:ARSTM1*/ + [74] = {0xFF862438U, 0x00000000U}, /* RGIDW_MODID[563]:ARSTM2*/ + [77] = {0xE67C2404U, 0x00000000U}, /* RGIDW_MODID[605]:AXIARNMM*/ + [78] = {0xE67C240CU, 0x00000000U}, /* RGIDW_MODID[607]:ARSM1*/ + [79] = {0xE67C2410U, 0x00000000U}, /* RGIDW_MODID[608]:ARSM2*/ + [80] = {0xFF802404U, 0x00000000U}, /* RGIDW_MODID[659]:ARSN1*/ + [81] = {0xFF802408U, 0x00000000U}, /* RGIDW_MODID[660]:ARSN2*/ + [82] = {0xE7752404U, 0x00000000U}, /* RGIDW_MODID[669]:ARSD01*/ + [83] = {0xE7752408U, 0x00000000U}, /* RGIDW_MODID[670]:ARSD02*/ + [84] = {0xE775243CU, 0x00000000U}, /* RGIDW_MODID[682]:ARSP01*/ + [85] = {0xE7752440U, 0x00000000U}, /* RGIDW_MODID[683]:ARSP02*/ + [86] = {0xFE682404U, 0x00000000U}, /* RGIDW_MODID[765]:ARVC1*/ + [87] = {0xFE682408U, 0x00000000U}, /* RGIDW_MODID[766]:ARVC2*/ + [88] = {0xFEBE2408U, 0x00000000U}, /* RGIDW_MODID[800]:ARVI11*/ + [89] = {0xFEBE240CU, 0x00000000U}, /* RGIDW_MODID[801]:ARVI12*/ + [90] = {0xFEBF2404U, 0x00000000U}, /* RGIDW_MODID[851]:ARVI1*/ + [91] = {0xFEBF2408U, 0x00000000U}, /* RGIDW_MODID[852]:ARVI2*/ + [92] = {0xE7B12404U, 0x00000000U}, /* RGIDW_MODID[881]:ARVIP01*/ + [93] = {0xE7B12408U, 0x00000000U}, /* RGIDW_MODID[882]:ARVIP02*/ + [94] = {0xE7B42404U, 0x00000000U}, /* RGIDW_MODID[913]:ARVIP11*/ + [95] = {0xE7B42408U, 0x00000000U}, /* RGIDW_MODID[914]:ARVIP12*/ + [96] = {0xEB802404U, 0x00000000U}, /* RGIDW_MODID[941]:ARDSP1*/ + [97] = {0xEB802408U, 0x00000000U}, /* RGIDW_MODID[942]:ARDSP2*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +/* RAM protection setting for SECDIV[n]D_0 / SECCTRR[m]D_0 / SECCTRW[m]D_0 */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram0_protection_table[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM0_ICUMX_IPL_AREA] = {NOT_USED_VALUE, {0x0000FFFCU, 0x0000FFFEU}}, /* not used for address value */ + /* Area0 phys:0xE0000000-0xE003FFFF R:RGID0/1 W:RGID0 */ + [RTVRAM0_ICUMX_FW_AREA] = {RTVRAM0_AREA1_TOP, {0x0004FFFEU, 0x0004FFFEU}}, /* Area1 phys:0xE0040000-0xE00FFFFF R:RGID0 W:RGID0 */ + [2] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [3] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for SECDIV[n]D_1 / SECCTRR[m]D_1 / SECCTRW[m]D_1 */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM1_BLANK_AREA] = {NOT_USED_VALUE, {0x0000FFB6U, 0x0000FFB7U}}, /* not used for address value */ + /* Area0 phys:0xE2000000-0xE200FFFF R:RGID0/3/6 W:RGID3/6 */ + [RTVRAM1_EXTEND_CACHE_AREA] = {RTVRAM1_AREA1_TOP, {0x0000BFFFU, 0x0000BFFFU}}, /* Area1 phys:0xE2010000-0xE20FFFFF R:RGID14 W:RGID14 */ + [RTVRAM1_RTOS_AREA] = {RTVRAM1_AREA2_TOP, {0x0000FFF4U, 0x0000FFF5U}}, /* Area2 phys:0xE2100000-0xE3BFFFFF R:RGID0/1/3 W:RGID1/3 */ + [3] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for SPTDIVCR[n] / SPTRGNCR[n] / SPTSECCR[n] */ +const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX] = { + /* access Secure */ + /* address R | W R|W */ + [SYSTEM_RAM_CX_2ND_IPL] = {NOT_USED_VALUE, {0xFFD8FFD8U, 0x00000000U}}, /* not used for address value */ + /* + * Change the access permission from 0xFFCCFFCC to 0xFFCCFFCD + * if user want to enable protection of System Ram Area0. + */ + /* Area0 phys:0xE6300000-0xE635DFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [SYSTEM_RAM_SHARED_MEM] = {SYSTEM_RAM_AREA1_TOP, {0xFFD8FFD8U, 0x00000000U}}, /* Area1 phys:0xE635E000-0xE635FFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [2] = {SYSTEM_RAM_AREA2_TOP, {0xFFDAFFDAU, 0x00000000U}}, /* Area2 phys:0xE6360000-0xE63FFFFF R:RGID0/2/5 W:RGID0/2/5 */ + [3] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for DPTDIVCR[n] / DPTRGNCR[n] / DPTSECCR[n] */ +const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX] = { + /* access secure */ + /* address R | W R|W */ + [RTVRAM1_EXTEND_AREA] = {NOT_USED_VALUE, {0xBFFFBFFFU, 0x00000000U}}, /* not used for address value */ + /* Area0 phys:0x04_00000000-0x04_01BFFFFF R:RGID14 W:RGID14 */ + [CR_FW_SHARED_AREA] = {DRAM_ADDR_AREA1, {0xFFBCFFBCU, 0x00000000U}}, /* Area1 phys:0x04_01C00000-0x04_01CFFFFF R:RGID0/1/6 W:RGID0/1/6 */ + /* This secure setting is added by sdram_protection() in loader_main function. */ + [SDRAM_BLANK_AREA] = {DRAM_ADDR_AREA2, {0xFF90FF90U, 0x00000000U}}, /* Area2:OPTEE_DISABLE phys:0x04_01D00000-0x04_063FFFFF + * Area2:OPTEE_ENABLE phys:0x04_01D00000-0x04_040FFFFF + * R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFBFFF9U, 0x00000404U}}, /* Area3 phys:0x04_06400000-0x04_0643FFFF R:RGID2 W:RGID1/2 */ + [SDRAM_PUBLIC_AREA] = {DRAM_ADDR_AREA4, {0xFF90FF90U, 0x00000000U}}, /* Area4 phys:0x04_06440000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA5, {0xFFB9FFB9U, 0x00000000U}}, /* Area5 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA6, {0xFFB1FFB1U, 0x00000000U}}, /* Area6 phys:0x04_08000000-0x04_1DBFFFFF R:RGID1/2/3/6 W:RGID1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA7, {0xFFB9FFB9U, 0x00000000U}}, /* Area7 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFBDFFBDU, 0x00000000U}}, /* Area8 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFDDFFDDU, 0x00000000U}}, /* Area9 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA11,{0xBF90BF90U, 0x00000000U}}, /* Area11 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA12,{0xFFFFFFFFU, 0x00000000U}}, /* Area12 phys:0x05_00000000-0x05_FFFFFFFF */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFF9FFF9U, 0x00000000U}}, /* Area13 phys:0x06_00000000-0x06_FFFFFFFF R:RGID1/2 W:RGID1/2 */ + [14] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [16] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +#else + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFAFFFAU, 0x00000404U}}, /* Area3 phys:0x04_04100000-0x04_063FFFFF R:RGID0/2 W:RGID0/2 */ + [SDRAM_PROTECT_AREA2] = {DRAM_ADDR_AREA4, {0xFFFBFFF9U, 0x00000404U}}, /* Area4 phys:0x04_06400000-0x04_0643FFFF R:RGID2 W:RGID1/2 */ + [SDRAM_BLANK_AREA2] = {DRAM_ADDR_AREA5, {0xFF90FF90U, 0x00000000U}}, /* Area5 phys:0x04_06440000-0x04_07DFFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [OPTEE_SHARED_AREA] = {DRAM_ADDR_AREA6, {0xFFFBFFFBU, 0x00000000U}}, /* Area6 phys:0x04_07E00000-0x04_07EFFFFF R:RGID2 W:RGID2 */ + [SDRAM_BLANK_AREA3] = {DRAM_ADDR_AREA7, {0xFF90FF90U, 0x00000000U}}, /* Area7 phys:0x04_07F00000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFB9FFB9U, 0x00000000U}}, /* Area8 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFB1FFB1U, 0x00000000U}}, /* Area9 phys:0x04_08000000-0x04_1DBFFFFF R:RGID1/2/3/6 W:RGID1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA11,{0xFFBDFFBDU, 0x00000000U}}, /* Area11 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA12,{0xFFDDFFDDU, 0x00000000U}}, /* Area12 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFB9FFB9U, 0x00000000U}}, /* Area13 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA14,{0xBF90BF90U, 0x00000000U}}, /* Area14 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA15,{0xFFFFFFFFU, 0x00000000U}}, /* Area15 phys:0x05_00000000-0x05_FFFFFFFF */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA16,{0xFFF9FFF9U, 0x00000000U}}, /* Area16 phys:0x06_00000000-0x06_FFFFFFFF R:RGID1/2 W:RGID1/2 */ +#endif /*OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + [17] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [18] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [19] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [20] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [21] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [22] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [23] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [24] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [25] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [26] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [27] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [28] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [29] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [30] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [31] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [32] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [33] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [34] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [35] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [36] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [37] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [38] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [39] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [40] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [41] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [42] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [43] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [44] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [45] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [46] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [47] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [48] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [49] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [50] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [51] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [52] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [53] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [54] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [55] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [56] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [57] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [58] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [59] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [60] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [61] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [62] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [63] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +const REGION_ID_SETTING_TABLE g_imp_rgid_m_tbl[IMP_MASTER_MAX] = { + [0] = {0xFFA8E270U, 0x00010202U}, /* SPMI BMATTR00 */ + [1] = {0xFFA8E274U, 0x00010202U}, /* SPMI BMATTR01 */ + [2] = {0xFFA8E278U, 0x00010202U}, /* SPMI BMATTR02 */ + [3] = {0xFFA8E27CU, 0x00010202U}, /* SPMI BMATTR03 */ + [4] = {0xFFA8E280U, 0x00010202U}, /* SPMI BMATTR04 */ + [5] = {0xFFA8E284U, 0x00010202U}, /* SPMI BMATTR05 */ + [6] = {0xFFA8E288U, 0x00010202U}, /* SPMI BMATTR06 */ + [7] = {0xFFA8E28CU, 0x00010202U}, /* SPMI BMATTR07 */ + [8] = {0xFFA8E290U, 0x00010202U}, /* SPMI BMATTR08 */ + [9] = {0xFFA8E294U, 0x00010202U}, /* SPMI BMATTR09 */ + [10] = {0xFFA8E298U, 0x00010202U}, /* SPMI BMATTR10 */ + [11] = {0xFFA8E29CU, 0x00010202U}, /* SPMI BMATTRSP0 */ + [12] = {0xFFAB2270U, 0x00010202U}, /* SPMC BMATTR00 */ + [13] = {0xFFAB2274U, 0x00010202U}, /* SPMC BMATTR01 */ + [14] = {0xFFAB2278U, 0x00010202U}, /* SPMC BMATTR02 */ + [15] = {0xFFAB227CU, 0x00010202U}, /* SPMC BMATTR03 */ + [16] = {0xFFAB2280U, 0x00010202U}, /* SPMC BMATTR04 */ + [17] = {0xFFAB2284U, 0x00010202U}, /* SPMC BMATTR05 */ + [18] = {0xFFAB2288U, 0x00010202U}, /* SPMC BMATTR06 */ +}; + +const REGION_ID_SETTING_TABLE g_imp_rgid_s_tbl[IMP_SLAVE_MAX] = { + [0] = {0xFF902100U, 0x004E004FU}, /* IMPSLV RCR0 */ + [1] = {0xFF902108U, 0x004E004FU}, /* IMPSLV RCR2 */ + [2] = {0xFFAB2100U, 0x004E004FU}, /* SPMC RCR0 */ + [3] = {0xFFAB2110U, 0x004E004FU}, /* SPMC RC00 */ + [4] = {0xFFAB2114U, 0x004E004FU}, /* SPMC RC01 */ + [5] = {0xFFAB2118U, 0x004E004FU}, /* SPMC RC02 */ + [6] = {0xFFAB2200U, 0x004E004FU}, /* SPMC RCB0 */ + [7] = {0xFFAB2204U, 0x004E004FU}, /* SPMC RCB1 */ + [8] = {0xFFAB2208U, 0x004E004FU}, /* SPMC RCB2 */ + [9] = {0xFFAB220CU, 0x004E004FU}, /* SPMC RCB3 */ + [10] = {0xFFAB2210U, 0x004E004FU}, /* SPMC RCB4 */ + [11] = {0xFFAB2104U, 0x004E004FU}, /* SPMC RCR1 */ + [12] = {0xFFA8E100U, 0x004E004FU}, /* SPMI RCR0 */ + [13] = {0xFFA8E110U, 0x004E004FU}, /* SPMI RC00 */ + [14] = {0xFFA8E114U, 0x004E004FU}, /* SPMI RC01 */ + [15] = {0xFFA8E118U, 0x004E004FU}, /* SPMI RC02 */ + [16] = {0xFFA8E11CU, 0x004E004FU}, /* SPMI RC03 */ + [17] = {0xFFA8E120U, 0x004E004FU}, /* SPMI RC04 */ + [18] = {0xFFA8E124U, 0x004E004FU}, /* SPMI RC05 */ + [19] = {0xFFA8E128U, 0x004E004FU}, /* SPMI RC06 */ + [20] = {0xFFA8E12CU, 0x004E004FU}, /* SPMI RC07 */ + [21] = {0xFFA8E130U, 0x004E004FU}, /* SPMI RC08 */ + [22] = {0xFFA8E134U, 0x004E004FU}, /* SPMI RC09 */ + [23] = {0xFFA8E138U, 0x004E004FU}, /* SPMI RC10 */ + [24] = {0xFFA8E13CU, 0x004E004FU}, /* SPMI RC11 */ + [25] = {0xFFA8E140U, 0x004E004FU}, /* SPMI RC12 */ + [26] = {0xFFA8E144U, 0x004E004FU}, /* SPMI RC13 */ + [27] = {0xFFA8E200U, 0x004E004FU}, /* SPMI RCB0 */ + [28] = {0xFFA8E204U, 0x004E004FU}, /* SPMI RCB1 */ + [29] = {0xFFA8E208U, 0x004E004FU}, /* SPMI RCB2 */ + [30] = {0xFFA8E20CU, 0x004E004FU}, /* SPMI RCB3 */ + [31] = {0xFFA8E210U, 0x004E004FU}, /* SPMI RCB4 */ + [32] = {0xFFA8E214U, 0x004E004FU}, /* SPMI RCB5 */ + [33] = {0xFFA8E218U, 0x004E004FU}, /* SPMI RCB6 */ + [34] = {0xFFA8E21CU, 0x004E004FU}, /* SPMI RCB7 */ + [35] = {0xFFA8E104U, 0x004E004FU}, /* SPMI RCR1 */ + [36] = {0xFF902110U, 0x004E004FU}, /* IMPSLV RC00 */ + [37] = {0xFF902104U, 0x004E004FU}, /* IMPSLV RCR1 */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX] = { + [0] = {0xEEE80570U, 0x00000002U}, /* IMRGID_IPMMU_VI0 */ + [1] = {0xEEEC0570U, 0x00000002U}, /* IMRGID_IPMMU_VI1 */ + [2] = {0xEEDC0570U, 0x00000002U}, /* IMRGID_IPMMU_VC0 */ + [3] = {0xEED80570U, 0x00000002U}, /* IMRGID_IPMMU_IR */ + [4] = {0xEE480570U, 0x00000001U}, /* IMRGID_IPMMU_RT0 */ + [5] = {0xEE4C0570U, 0x00000001U}, /* IMRGID_IPMMU_RT1 */ + [6] = {0xEED00570U, 0x00000001U}, /* IMRGID_IPMMU_DS0 */ + [7] = {0xEED40570U, 0x00000001U}, /* IMRGID_IPMMU_HSC */ + [8] = {0xEEF00570U, 0x00000002U}, /* IMRGID_IPMMU_VIP0 */ + [9] = {0xEEF40570U, 0x00000002U}, /* IMRGID_IPMMU_VIP1 */ + [10] = {0xEEE00570U, 0x00000002U}, /* IMRGID_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX] = { + [0] = {0xEEE80578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI0 */ + [1] = {0xEEEC0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI1 */ + [2] = {0xEEDC0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VC0 */ + [3] = {0xEED80578U, 0x00000001U}, /* IMSECGRP_IPMMU_IR */ + [4] = {0xEE480578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT0 */ + [5] = {0xEE4C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT1 */ + [6] = {0xEED00578U, 0x00000001U}, /* IMSECGRP_IPMMU_DS0 */ + [7] = {0xEED40578U, 0x00000001U}, /* IMSECGRP_IPMMU_HSC */ + [8] = {0xEEF00578U, 0x00000001U}, /* IMSECGRP_IPMMU_VIP0 */ + [9] = {0xEEF40578U, 0x00000001U}, /* IMSECGRP_IPMMU_VIP1 */ + [10] = {0xEEE00578U, 0x00000001U}, /* IMSECGRP_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX] = { + [0] = {0xEEE80574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI0 */ + [1] = {0xEEEC0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI1 */ + [2] = {0xEEDC0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VC0 */ + [3] = {0xEED80574U, 0x00000002U}, /* IMRGIDEN_IPMMU_IR */ + [4] = {0xEE480574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT0 */ + [5] = {0xEE4C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT1 */ + [6] = {0xEED00574U, 0x00000002U}, /* IMRGIDEN_IPMMU_DS0 */ + [7] = {0xEED40574U, 0x00000002U}, /* IMRGIDEN_IPMMU_HSC */ + [8] = {0xEEF00574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VIP0 */ + [9] = {0xEEF40574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VIP1 */ + [10] = {0xEEE00574U, 0x00000002U}, /* IMRGIDEN_IPMMU_3DG */ +}; + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4m.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4m.c new file mode 100644 index 0000000..501ef62 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/cnf_tbl/rgidcnf_tbl_v4m.c @@ -0,0 +1,3020 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table + ******************************************************************************/ +/****************************************************************************** + * @file rgidcnf_tbl_v4m.c + * - Version : 0.09 + * @brief Configuration table for V4M. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + * : 15.09.2023 0.02 Update setting table according to + * HWUM Rev.0.50. + * : 10.10.2023 0.03 Removed unimplemented registers. + * : 23.01.2024 0.04 Added RAM protection table. + * Update Region ID settings. + * : 07.02.2024 0.05 Update System RAM protection setting Area0. + * : 11.10.2024 0.06 Updated Region ID and RAM protection setting + * for QNX. + * : 05.12.2024 0.07 Update RAM protection settings for ICCOM + * memory area (SDRAM Area5). + * Update Region ID settings for VSPD and VSPX. + * Update Region ID settings for IPMMU. + * Update RAM protection setting. + * : 16.12.2024 0.08 Updated Region ID setting. + * Updated Region ID setting and RAM protection + * setting for booting CR52 3 cores. + * Update Region ID settings for ISP ch1. + * Update Region ID settings for PCI1. + * Added IPMMU Region ID table. + * : 26.05.2025 0.09 Updated RAM protection settings for + * protection area. + *****************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include +#endif +#include +#include +#include "ram_protection.h" + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_m_tbl" +#else +__attribute__ ((section(".rgid_m_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_master_tbl[] = { + [0] = {0xE6581000U, 0x00000002U}, /* RGIDM_MODID[0]:PCI0 */ + [1] = {0xE6581020U, 0x00000002U}, /* RGIDM_MODID[1]:PCI1 */ + [2] = {0xE6581010U, 0x00000002U}, /* RGIDM_MODID[3]:AVB0 */ + [3] = {0xE6581014U, 0x00000001U}, /* RGIDM_MODID[4]:AVB1 */ + [4] = {0xE6581018U, 0x00000001U}, /* RGIDM_MODID[5]:AVB2 */ + [5] = {0xE662100CU, 0x00000000U}, /* RGIDM_MODID[6]:DCLS_ICUMX */ + [6] = {0xE6621010U, 0x00000000U}, /* RGIDM_MODID[7]:ICUMX */ + [7] = {0xE6621014U, 0x00000000U}, /* RGIDM_MODID[8]:SDMAC_ICUMX */ + [8] = {0xFFC41018U, 0x00000001U}, /* RGIDM_MODID[9]:CR52SS0 */ + [9] = {0xFFC4105CU, 0x00000001U}, /* RGIDM_MODID[10]:CR52SS1 */ + [10] = {0xFFC41060U, 0x00000006U}, /* RGIDM_MODID[11]:CR52SS2 */ + [11] = {0xFFC4101CU, 0x00000003U}, /* RGIDM_MODID[12]:CSD */ + [12] = {0xFFC41024U, 0x00000002U}, /* RGIDM_MODID[13]:INTAP0 */ + [13] = {0xFF861018U, 0x00000002U}, /* RGIDM_MODID[14]:FBABUSTOP0 */ + [14] = {0xE7751020U, 0x00000002U}, /* RGIDM_MODID[15]:SDHI0 */ + [15] = {0xE7751010U, 0x00000001U}, /* RGIDM_MODID[16]:FRAY */ + [16] = {0xFF811000U, 0x00000002U}, /* RGIDM_MODID[17]:AXMM2AXSTM */ + [17] = {0xFF811004U, 0x00000003U}, /* RGIDM_MODID[18]:CSDE0 */ + [18] = {0xFF811008U, 0x00000003U}, /* RGIDM_MODID[19]:CSDE1 */ + [19] = {0xFFC41020U, 0x00000003U}, /* RGIDM_MODID[20]:CSDE2 */ + [20] = {0xFF881004U, 0x00000002U}, /* RGIDM_MODID[21]:FBABUSIR0 */ + [21] = {0xFF881008U, 0x00000002U}, /* RGIDM_MODID[22]:FBABUSIR1 */ + [22] = {0xFF88100CU, 0x00000002U}, /* RGIDM_MODID[23]:FBABUSIR2 */ + [23] = {0xFF881010U, 0x00000002U}, /* RGIDM_MODID[24]:FBABUSIR3 */ + [24] = {0xFD811014U, 0x00000002U}, /* RGIDM_MODID[25]:RGX0 */ + [25] = {0xFE681004U, 0x00000002U}, /* RGIDM_MODID[26]:FBABUSVC */ + [26] = {0xFE681010U, 0x00000002U}, /* RGIDM_MODID[27]:IMR00 */ + [27] = {0xFE681014U, 0x00000002U}, /* RGIDM_MODID[28]:IMR01 */ + [28] = {0xFE681024U, 0x00000002U}, /* RGIDM_MODID[29]:IMR10 */ + [29] = {0xFE681028U, 0x00000002U}, /* RGIDM_MODID[30]:IMR11 */ + [30] = {0xFE681040U, 0x00000002U}, /* RGIDM_MODID[31]:IMS0 */ + [31] = {0xFE681044U, 0x00000002U}, /* RGIDM_MODID[32]:IMS1 */ + [32] = {0xFE681048U, 0x00000005U}, /* RGIDM_MODID[33]:IV1ES */ + [33] = {0xFEBE1000U, 0x00000002U}, /* RGIDM_MODID[34]:DSITLINK0 */ + [34] = {0xFEBE1008U, 0x00000002U}, /* RGIDM_MODID[36]:FBABUSVIO */ + [35] = {0xFEBE1014U, 0x00000002U}, /* RGIDM_MODID[37]:FCPVD0 */ + [36] = {0xFEBE101CU, 0x00000002U}, /* RGIDM_MODID[38]:FCPVX0 */ + [37] = {0xFEBF1020U, 0x00000002U}, /* RGIDM_MODID[39]:ISP00 */ + [38] = {0xFEBF1024U, 0x00000002U}, /* RGIDM_MODID[40]:ISP01 */ + [39] = {0xFEBF1000U, 0x00000002U}, /* RGIDM_MODID[41]:ISP02 */ + [40] = {0xFEBF1004U, 0x00000002U}, /* RGIDM_MODID[42]:ISP03 */ + [41] = {0xFEBF1008U, 0x00000002U}, /* RGIDM_MODID[43]:ISP04 */ + [42] = {0xFEBF1010U, 0x00000002U}, /* RGIDM_MODID[44]:VIN0 */ + [43] = {0xFEBF1014U, 0x00000002U}, /* RGIDM_MODID[45]:VIN1 */ + [44] = {0xE7B11004U, 0x00000002U}, /* RGIDM_MODID[46]:FBABUSVIP0 */ + [45] = {0xE7B11010U, 0x00000002U}, /* RGIDM_MODID[47]:SMPO */ + [46] = {0xE7B11018U, 0x00000002U}, /* RGIDM_MODID[48]:SMPS */ + [47] = {0xE7B1101CU, 0x00000002U}, /* RGIDM_MODID[49]:UMFL */ + [48] = {0xFF881018U, 0x00000002U}, /* RGIDM_MODID[50]:DSP00 */ + [49] = {0xFF881024U, 0x00000002U}, /* RGIDM_MODID[51]:DSP01 */ + [50] = {0xFF881038U, 0x00000002U}, /* RGIDM_MODID[52]:DSP10 */ + [51] = {0xFF881044U, 0x00000002U}, /* RGIDM_MODID[53]:DSP11 */ + [52] = {0xFF881048U, 0x00000002U}, /* RGIDM_MODID[54]:DSP20 */ + [53] = {0xFF88104CU, 0x00000002U}, /* RGIDM_MODID[55]:DSP21 */ + [54] = {0xFF881050U, 0x00000002U}, /* RGIDM_MODID[56]:DSP30 */ + [55] = {0xFF881054U, 0x00000002U}, /* RGIDM_MODID[57]:DSP31 */ + [56] = {0xFF881058U, 0x00000002U}, /* RGIDM_MODID[58]:IMP0R100 */ + [57] = {0xFF88105CU, 0x00000002U}, /* RGIDM_MODID[59]:IMP0R101 */ + [58] = {0xFF881060U, 0x00000002U}, /* RGIDM_MODID[60]:IMP0R102 */ + [59] = {0xFF881064U, 0x00000002U}, /* RGIDM_MODID[61]:IMP0R103 */ + [60] = {0xFF881068U, 0x00000002U}, /* RGIDM_MODID[62]:IMP0R104 */ + [61] = {0xFF88106CU, 0x00000002U}, /* RGIDM_MODID[63]:IMP0R105 */ + [62] = {0xFF881070U, 0x00000002U}, /* RGIDM_MODID[64]:IMP0R106 */ + [63] = {0xFF881074U, 0x00000002U}, /* RGIDM_MODID[65]:IMP0R107 */ + [64] = {0xFF881078U, 0x00000002U}, /* RGIDM_MODID[66]:IMP0R108 */ + [65] = {0xFF88107CU, 0x00000002U}, /* RGIDM_MODID[67]:IMP0R109 */ + [66] = {0xFF881080U, 0x00000002U}, /* RGIDM_MODID[68]:IMP0R200 */ + [67] = {0xFF881084U, 0x00000002U}, /* RGIDM_MODID[69]:IMP0R201 */ + [68] = {0xFF881088U, 0x00000002U}, /* RGIDM_MODID[70]:IMP0R202 */ + [69] = {0xFF88108CU, 0x00000002U}, /* RGIDM_MODID[71]:IMP0W100 */ + [70] = {0xFF881090U, 0x00000002U}, /* RGIDM_MODID[72]:IMP0W101 */ + [71] = {0xFF881094U, 0x00000002U}, /* RGIDM_MODID[73]:IMP0W102 */ + [72] = {0xFF881098U, 0x00000002U}, /* RGIDM_MODID[74]:IMP0W103 */ + [73] = {0xFF88109CU, 0x00000002U}, /* RGIDM_MODID[75]:IMP0W104 */ + [74] = {0xFF8810A0U, 0x00000002U}, /* RGIDM_MODID[76]:IMP0W105 */ + [75] = {0xFF8810A4U, 0x00000002U}, /* RGIDM_MODID[77]:IMP0W106 */ + [76] = {0xFF8810A8U, 0x00000002U}, /* RGIDM_MODID[78]:IMP0W107 */ + [77] = {0xFF8810ACU, 0x00000002U}, /* RGIDM_MODID[79]:IMP0W108 */ + [78] = {0xFF8810B0U, 0x00000002U}, /* RGIDM_MODID[80]:IMP0W109 */ + [79] = {0xFF8810B4U, 0x00000002U}, /* RGIDM_MODID[81]:IMP0W200 */ + [80] = {0xFF8810B8U, 0x00000002U}, /* RGIDM_MODID[82]:IMP0W201 */ + [81] = {0xFF8810BCU, 0x00000002U}, /* RGIDM_MODID[83]:IMP0W202 */ + [82] = {0xE67BF500U, 0x0000000EU}, /* RGIDM_MODID[84]:VRAM_R */ + [83] = {0xE67BF504U, 0x0000000EU}, /* RGIDM_MODID[85]:VRAM_W */ + [84] = {0xE7B11008U, 0x00000002U}, /* RGIDM_MODID[86]:PAP */ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_r_tbl" +#else +__attribute__ ((section(".rgid_r_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_read_tbl[] = { + [0] = {0xFFC82000U, 0x0000000FU}, /* RGIDR_MODID[0]:ARMGC0*/ + [1] = {0xFFC82004U, 0x0000000FU}, /* RGIDR_MODID[1]:ARMGC1*/ + [2] = {0xFFC82008U, 0x00000000U}, /* RGIDR_MODID[2]:ARMGC2*/ + [3] = {0xFFC8200CU, 0x0000000FU}, /* RGIDR_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDR_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDR_MODID[5]:ARRT02*/ + [4] = {0xFFC82018U, 0x0000000FU}, /* RGIDR_MODID[6]:ARRT03*/ + [5] = {0xFFC8201CU, 0x0000000FU}, /* RGIDR_MODID[7]:ARRT04*/ + [6] = {0xFFC82020U, 0x0000000FU}, /* RGIDR_MODID[8]:ARRT05*/ + [7] = {0xFFC82024U, 0x0000000FU}, /* RGIDR_MODID[9]:ARRT06*/ + [8] = {0xFFC82028U, 0x0000000FU}, /* RGIDR_MODID[10]:ARRT07*/ + [9] = {0xFFC8202CU, 0x00000000U}, /* RGIDR_MODID[11]:ARRT08*/ + [10] = {0xFFC82030U, 0x00000001U}, /* RGIDR_MODID[12]:LIFEC0*/ + [11] = {0xFFC82034U, 0x0000000EU}, /* RGIDR_MODID[13]:SWDT*/ + [12] = {0xFFC82038U, 0x0000006EU}, /* RGIDR_MODID[14]:TMU0*/ + [13] = {0xFFC8203CU, 0x0000000EU}, /* RGIDR_MODID[15]:WDT*/ + [14] = {0xFFC82040U, 0x0000000EU}, /* RGIDR_MODID[16]:WWDT0*/ + [15] = {0xFFC82044U, 0x0000000EU}, /* RGIDR_MODID[17]:WWDT1*/ + [16] = {0xFFC82048U, 0x0000000EU}, /* RGIDR_MODID[18]:WWDT2*/ + [17] = {0xFFC8204CU, 0x0000000EU}, /* RGIDR_MODID[19]:WWDT3*/ + [18] = {0xFFC82050U, 0x0000000EU}, /* RGIDR_MODID[20]:WWDT4*/ + [19] = {0xFFC82054U, 0x0000000EU}, /* RGIDR_MODID[21]:WWDT5*/ + [20] = {0xFFC82058U, 0x0000000EU}, /* RGIDR_MODID[22]:WWDT6*/ + [21] = {0xFFC82068U, 0x0000000FU}, /* RGIDR_MODID[23]:ECMRT3*/ + [22] = {0xE6002004U, 0x0000000FU}, /* RGIDR_MODID[24]:APMU0*/ + [23] = {0xE6002008U, 0x00000002U}, /* RGIDR_MODID[25]:APMU1*/ + [24] = {0xE600200CU, 0x00000000U}, /* RGIDR_MODID[26]:APMU10*/ + [25] = {0xE6002010U, 0x00000000U}, /* RGIDR_MODID[27]:APMU11*/ + [26] = {0xE6002014U, 0x00000000U}, /* RGIDR_MODID[28]:APMU12*/ + [27] = {0xE6002018U, 0x00000000U}, /* RGIDR_MODID[29]:APMU13*/ + [28] = {0xE600201CU, 0x00000000U}, /* RGIDR_MODID[30]:APMU14*/ + [29] = {0xE6002020U, 0x00000000U}, /* RGIDR_MODID[31]:APMU15*/ + [30] = {0xE6002024U, 0x00000004U}, /* RGIDR_MODID[32]:APMU2*/ + [31] = {0xE6002028U, 0x00000004U}, /* RGIDR_MODID[33]:APMU3*/ + [32] = {0xE600202CU, 0x00000000U}, /* RGIDR_MODID[34]:APMU4*/ + [33] = {0xE6002030U, 0x00000000U}, /* RGIDR_MODID[35]:APMU5*/ + [34] = {0xE6002034U, 0x00000000U}, /* RGIDR_MODID[36]:APMU6*/ + [35] = {0xE6002038U, 0x00000000U}, /* RGIDR_MODID[37]:APMU7*/ + [36] = {0xE600203CU, 0x00000000U}, /* RGIDR_MODID[38]:APMU8*/ + [37] = {0xE6002040U, 0x00000000U}, /* RGIDR_MODID[39]:APMU9*/ + [38] = {0xE6002044U, 0x0000000FU}, /* RGIDR_MODID[40]:ARS00*/ + /* After setting */ /* RGIDR_MODID[41]:ARS01*/ + /* After setting */ /* RGIDR_MODID[42]:ARS02*/ + [39] = {0xE6002050U, 0x0000000FU}, /* RGIDR_MODID[43]:ARS03*/ + [40] = {0xE6002054U, 0x0000000FU}, /* RGIDR_MODID[44]:ARS04*/ + [41] = {0xE6002058U, 0x0000000FU}, /* RGIDR_MODID[45]:ARS05*/ + [42] = {0xE600205CU, 0x0000000FU}, /* RGIDR_MODID[46]:ARS06*/ + [43] = {0xE6002060U, 0x0000000FU}, /* RGIDR_MODID[47]:ARS07*/ + [44] = {0xE6002064U, 0x00000000U}, /* RGIDR_MODID[48]:ARS08*/ + [45] = {0xE6002068U, 0x0000000EU}, /* RGIDR_MODID[49]:CMT0*/ + [46] = {0xE600206CU, 0x0000000EU}, /* RGIDR_MODID[50]:CMT1*/ + [47] = {0xE6002070U, 0x0000000EU}, /* RGIDR_MODID[51]:CMT2*/ + [48] = {0xE6002074U, 0x0000000EU}, /* RGIDR_MODID[52]:CMT3*/ + [49] = {0xE6002078U, 0x0000000AU}, /* RGIDR_MODID[53]:CKM*/ + [50] = {0xE600207CU, 0x0000000EU}, /* RGIDR_MODID[54]:DBE*/ + [51] = {0xE6002080U, 0x0000000EU}, /* RGIDR_MODID[55]:IRQC*/ + [52] = {0xE6002084U, 0x0000000FU}, /* RGIDR_MODID[56]:ECMPS0*/ + [53] = {0xE6002088U, 0x0000000BU}, /* RGIDR_MODID[57]:OTP0*/ + [54] = {0xE600208CU, 0x0000000FU}, /* RGIDR_MODID[58]:OTP1*/ + [55] = {0xE600209CU, 0x0000000EU}, /* RGIDR_MODID[59]:SCMT*/ + [56] = {0xE60020A8U, 0x0000004EU}, /* RGIDR_MODID[60]:TSC1*/ + [57] = {0xE60020ACU, 0x0000004EU}, /* RGIDR_MODID[61]:TSC2*/ + [58] = {0xE60020B8U, 0x00000006U}, /* RGIDR_MODID[62]:UCMT*/ + [59] = {0xE6002100U, 0x0000006FU}, /* RGIDR_MODID[63]:CPG0*/ + [60] = {0xE6002104U, 0x0000000AU}, /* RGIDR_MODID[64]:CPG1*/ + [61] = {0xE6002108U, 0x0000004EU}, /* RGIDR_MODID[65]:CPG2*/ + [62] = {0xE600210CU, 0x00000028U}, /* RGIDR_MODID[66]:CPG3*/ + [63] = {0xE6002110U, 0x0000006FU}, /* RGIDR_MODID[67]:PFC00*/ + [64] = {0xE6002114U, 0x0000000AU}, /* RGIDR_MODID[68]:PFC01*/ + [65] = {0xE6002118U, 0x0000004EU}, /* RGIDR_MODID[69]:PFC02*/ + [66] = {0xE600211CU, 0x00000028U}, /* RGIDR_MODID[70]:PFC03*/ + [67] = {0xE6002120U, 0x0000006FU}, /* RGIDR_MODID[71]:PFC10*/ + [68] = {0xE6002124U, 0x0000000AU}, /* RGIDR_MODID[72]:PFC11*/ + [69] = {0xE6002128U, 0x0000004EU}, /* RGIDR_MODID[73]:PFC12*/ + [70] = {0xE600212CU, 0x00000028U}, /* RGIDR_MODID[74]:PFC13*/ + [71] = {0xE6002130U, 0x0000006FU}, /* RGIDR_MODID[75]:PFC20*/ + [72] = {0xE6002134U, 0x0000000AU}, /* RGIDR_MODID[76]:PFC21*/ + [73] = {0xE6002138U, 0x0000004EU}, /* RGIDR_MODID[77]:PFC22*/ + [74] = {0xE600213CU, 0x00000028U}, /* RGIDR_MODID[78]:PFC23*/ + [75] = {0xE6002150U, 0x0000006FU}, /* RGIDR_MODID[79]:PFCS0*/ + [76] = {0xE6002154U, 0x0000000AU}, /* RGIDR_MODID[80]:PFCS1*/ + [77] = {0xE6002158U, 0x0000004EU}, /* RGIDR_MODID[81]:PFCS2*/ + [78] = {0xE600215CU, 0x00000028U}, /* RGIDR_MODID[82]:PFCS3*/ + [79] = {0xE6002160U, 0x0000006FU}, /* RGIDR_MODID[83]:RESET0*/ + [80] = {0xE6002164U, 0x0000000AU}, /* RGIDR_MODID[84]:RESET1*/ + [81] = {0xE6002168U, 0x0000004EU}, /* RGIDR_MODID[85]:RESET2*/ + [82] = {0xE600216CU, 0x00000028U}, /* RGIDR_MODID[86]:RESET3*/ + [83] = {0xE6002170U, 0x0000006FU}, /* RGIDR_MODID[87]:SYS0*/ + [84] = {0xE6002174U, 0x0000000AU}, /* RGIDR_MODID[88]:SYS1*/ + [85] = {0xE6002178U, 0x0000004EU}, /* RGIDR_MODID[89]:SYS2*/ + [86] = {0xE600217CU, 0x00000028U}, /* RGIDR_MODID[90]:SYS3*/ + [87] = {0xE7762000U, 0x0000000EU}, /* RGIDR_MODID[91]:DMAMSI0*/ + [88] = {0xE7762004U, 0x0000000EU}, /* RGIDR_MODID[92]:DMAMSI1*/ + [89] = {0xE7762008U, 0x0000000EU}, /* RGIDR_MODID[93]:DMAMSI2*/ + [90] = {0xE776200CU, 0x0000000EU}, /* RGIDR_MODID[94]:DMAMSI3*/ + [91] = {0xE7762010U, 0x0000000EU}, /* RGIDR_MODID[95]:DMAMSI4*/ + [92] = {0xE7762014U, 0x0000000EU}, /* RGIDR_MODID[96]:DMAMSI5*/ + [93] = {0xE7762018U, 0x0000000FU}, /* RGIDR_MODID[97]:ECMSP3*/ + [94] = {0xE7762024U, 0x0000000FU}, /* RGIDR_MODID[98]:ARSP30*/ + /* After setting */ /* RGIDR_MODID[99]:ARSP31*/ + /* After setting */ /* RGIDR_MODID[100]:ARSP32*/ + [95] = {0xE7762030U, 0x0000000FU}, /* RGIDR_MODID[101]:ARSP33*/ + [96] = {0xE7762034U, 0x0000000FU}, /* RGIDR_MODID[102]:ARSP34*/ + [97] = {0xE7762038U, 0x0000000FU}, /* RGIDR_MODID[103]:ARSP35*/ + [98] = {0xE776203CU, 0x0000000FU}, /* RGIDR_MODID[104]:ARSP36*/ + [99] = {0xE7762040U, 0x0000000FU}, /* RGIDR_MODID[105]:ARSP37*/ + [100] = {0xE7762044U, 0x00000000U}, /* RGIDR_MODID[106]:ARSP38*/ + [101] = {0xE7762048U, 0x0000000EU}, /* RGIDR_MODID[107]:MSI0*/ + [102] = {0xE776204CU, 0x0000000EU}, /* RGIDR_MODID[108]:MSI1*/ + [103] = {0xE7762050U, 0x0000000EU}, /* RGIDR_MODID[109]:MSI2*/ + [104] = {0xE7762054U, 0x0000000EU}, /* RGIDR_MODID[110]:MSI3*/ + [105] = {0xE7762058U, 0x0000000EU}, /* RGIDR_MODID[111]:MSI4*/ + [106] = {0xE776205CU, 0x0000000EU}, /* RGIDR_MODID[112]:MSI5*/ + [107] = {0xE7792000U, 0x0000000FU}, /* RGIDR_MODID[113]:ARSP40*/ + /* After setting */ /* RGIDR_MODID[114]:ARSP41*/ + /* After setting */ /* RGIDR_MODID[115]:ARSP42*/ + [108] = {0xE779200CU, 0x0000000FU}, /* RGIDR_MODID[116]:ARSP43*/ + [109] = {0xE7792010U, 0x0000000FU}, /* RGIDR_MODID[117]:ARSP44*/ + [110] = {0xE7792014U, 0x0000000FU}, /* RGIDR_MODID[118]:ARSP45*/ + [111] = {0xE7792018U, 0x0000000FU}, /* RGIDR_MODID[119]:ARSP46*/ + [112] = {0xE779201CU, 0x0000000FU}, /* RGIDR_MODID[120]:ARSP47*/ + [113] = {0xE7792020U, 0x00000000U}, /* RGIDR_MODID[121]:ARSP48*/ + [114] = {0xE7792024U, 0x0000004FU}, /* RGIDR_MODID[122]:DMAHSCIF0*/ + [115] = {0xE7792028U, 0x0000004FU}, /* RGIDR_MODID[123]:DMAHSCIF1*/ + [116] = {0xE779202CU, 0x0000004FU}, /* RGIDR_MODID[124]:DMAHSCIF2*/ + [117] = {0xE7792030U, 0x0000004FU}, /* RGIDR_MODID[125]:DMAHSCIF3*/ + [118] = {0xE7792034U, 0x0000004FU}, /* RGIDR_MODID[126]:DMASCIF0*/ + [119] = {0xE7792038U, 0x0000004FU}, /* RGIDR_MODID[127]:DMASCIF1*/ + [120] = {0xE779203CU, 0x0000004FU}, /* RGIDR_MODID[128]:DMASCIF3*/ + [121] = {0xE7792040U, 0x0000004FU}, /* RGIDR_MODID[129]:DMASCIF4*/ + [122] = {0xE7792044U, 0x0000000FU}, /* RGIDR_MODID[130]:ECMSP4*/ + [123] = {0xE7792048U, 0x0000004FU}, /* RGIDR_MODID[131]:HSCIF0*/ + [124] = {0xE779204CU, 0x0000004FU}, /* RGIDR_MODID[132]:HSCIF1*/ + [125] = {0xE7792050U, 0x0000004FU}, /* RGIDR_MODID[133]:HSCIF2*/ + [126] = {0xE7792054U, 0x0000004FU}, /* RGIDR_MODID[134]:HSCIF3*/ + [127] = {0xE7792058U, 0x0000004FU}, /* RGIDR_MODID[135]:SCIF0*/ + [128] = {0xE779205CU, 0x0000004FU}, /* RGIDR_MODID[136]:SCIF1*/ + [129] = {0xE7792060U, 0x0000004FU}, /* RGIDR_MODID[137]:SCIF3*/ + [130] = {0xE7792064U, 0x0000004FU}, /* RGIDR_MODID[138]:SCIF4*/ + [131] = {0xE7792068U, 0x0000006EU}, /* RGIDR_MODID[139]:TMU1*/ + [132] = {0xE779206CU, 0x0000006EU}, /* RGIDR_MODID[140]:TMU2*/ + [133] = {0xE7792070U, 0x0000006EU}, /* RGIDR_MODID[141]:TMU3*/ + [134] = {0xE7792074U, 0x0000006EU}, /* RGIDR_MODID[142]:TMU4*/ + [135] = {0xE7792078U, 0x0000004AU}, /* RGIDR_MODID[143]:CANFD*/ + [136] = {0xE779207CU, 0x0000004AU}, /* RGIDR_MODID[144]:DMACANFD*/ + [137] = {0xE7792080U, 0x00000002U}, /* RGIDR_MODID[145]:DMATPU0*/ + [138] = {0xE7792084U, 0x00000002U}, /* RGIDR_MODID[146]:PWM0*/ + [139] = {0xE7792088U, 0x00000002U}, /* RGIDR_MODID[147]:PWM1*/ + [140] = {0xE779208CU, 0x00000002U}, /* RGIDR_MODID[148]:PWM2*/ + [141] = {0xE7792090U, 0x00000002U}, /* RGIDR_MODID[149]:PWM3*/ + [142] = {0xE7792094U, 0x00000002U}, /* RGIDR_MODID[150]:PWM4*/ + [143] = {0xE77920ACU, 0x00000002U}, /* RGIDR_MODID[151]:TPU0*/ + [144] = {0xFEBD2000U, 0x0000000FU}, /* RGIDR_MODID[152]:ARVI40*/ + /* After setting */ /* RGIDR_MODID[153]:ARVI41*/ + /* After setting */ /* RGIDR_MODID[154]:ARVI42*/ + [145] = {0xFEBD200CU, 0x0000000FU}, /* RGIDR_MODID[155]:ARVI43*/ + [146] = {0xFEBD2010U, 0x0000000FU}, /* RGIDR_MODID[156]:ARVI44*/ + [147] = {0xFEBD2014U, 0x0000000FU}, /* RGIDR_MODID[157]:ARVI45*/ + [148] = {0xFEBD2018U, 0x0000000FU}, /* RGIDR_MODID[158]:ARVI46*/ + [149] = {0xFEBD201CU, 0x0000000FU}, /* RGIDR_MODID[159]:ARVI47*/ + [150] = {0xFEBD2020U, 0x00000000U}, /* RGIDR_MODID[160]:ARVI48*/ + [151] = {0xFEBD2024U, 0x0000000FU}, /* RGIDR_MODID[161]:DIS0*/ + [152] = {0xFEBD2030U, 0x0000000FU}, /* RGIDR_MODID[162]:ECMVIO2*/ + [153] = {0xFEBD2034U, 0x0000000FU}, /* RGIDR_MODID[163]:FCPVD0*/ + [154] = {0xFEBD203CU, 0x0000004EU}, /* RGIDR_MODID[164]:VSPD0*/ + [155] = {0xE6582000U, 0x0000000AU}, /* RGIDR_MODID[165]:CKMHSC*/ + [156] = {0xE6582004U, 0x0000000CU}, /* RGIDR_MODID[166]:AXIPCI001*/ + [157] = {0xE6582008U, 0x0000000CU}, /* RGIDR_MODID[167]:AXIPCI002*/ + [158] = {0xE658200CU, 0x0000000CU}, /* RGIDR_MODID[168]:AXIPCI003*/ + [159] = {0xE6582014U, 0x0000000CU}, /* RGIDR_MODID[169]:AXIPCI005*/ + [160] = {0xE6582018U, 0x0000000CU}, /* RGIDR_MODID[170]:AXIPCI006*/ + [161] = {0xE658201CU, 0x0000000CU}, /* RGIDR_MODID[171]:AXIPCI007*/ + [162] = {0xE6582020U, 0x0000000CU}, /* RGIDR_MODID[172]:AXIPCI008*/ + [163] = {0xE6582024U, 0x0000000CU}, /* RGIDR_MODID[173]:AXIPCI009*/ + [164] = {0xE6582028U, 0x0000000CU}, /* RGIDR_MODID[174]:AXIPCI010*/ + [165] = {0xE658202CU, 0x0000000CU}, /* RGIDR_MODID[175]:AXIPCI011*/ + [166] = {0xE6582030U, 0x0000000CU}, /* RGIDR_MODID[176]:AXIPCI012*/ + [167] = {0xE6582034U, 0x0000000CU}, /* RGIDR_MODID[177]:AXIPCI013*/ + [168] = {0xE6582038U, 0x0000000CU}, /* RGIDR_MODID[178]:AXIPCI014*/ + [169] = {0xE658203CU, 0x0000000CU}, /* RGIDR_MODID[179]:AXIPCI015*/ + [170] = {0xE6582084U, 0x0000000EU}, /* RGIDR_MODID[180]:GPTP*/ + [171] = {0xE6582088U, 0x0000004EU}, /* RGIDR_MODID[181]:IPMMUHC00*/ + [172] = {0xE65820F4U, 0x0000000CU}, /* RGIDR_MODID[182]:AXIPCI000*/ + [173] = {0xE65820F8U, 0x0000000CU}, /* RGIDR_MODID[183]:AXIPCI004*/ + [174] = {0xE65820FCU, 0x0000004EU}, /* RGIDR_MODID[184]:IPMMUHC01*/ + [175] = {0xE6582100U, 0x0000004EU}, /* RGIDR_MODID[185]:AVB0*/ + [176] = {0xE6582104U, 0x0000004EU}, /* RGIDR_MODID[186]:AVB1*/ + [177] = {0xE6582108U, 0x0000004EU}, /* RGIDR_MODID[187]:AVB2*/ + [178] = {0xE658210CU, 0x0000004EU}, /* RGIDR_MODID[188]:IPMMUHC10*/ + [179] = {0xE6582110U, 0x0000004EU}, /* RGIDR_MODID[189]:IPMMUHC11*/ + [180] = {0xE6582114U, 0x0000004EU}, /* RGIDR_MODID[190]:IPMMUHC12*/ + [181] = {0xE6582118U, 0x0000004EU}, /* RGIDR_MODID[191]:IPMMUHC13*/ + [182] = {0xE658211CU, 0x0000000CU}, /* RGIDR_MODID[192]:PPHY0*/ + [183] = {0xE6582124U, 0x0000004EU}, /* RGIDR_MODID[193]:IPMMUHC14*/ + [184] = {0xE6582128U, 0x0000004EU}, /* RGIDR_MODID[194]:IPMMUHC15*/ + [185] = {0xE658212CU, 0x0000000EU}, /* RGIDR_MODID[195]:FBAHSC*/ + [186] = {0xE6582130U, 0x0000004EU}, /* RGIDR_MODID[196]:IPMMUHC02*/ + [187] = {0xE6582138U, 0x0000000FU}, /* RGIDR_MODID[197]:ECMHSC*/ + [188] = {0xE658213CU, 0x0000000FU}, /* RGIDR_MODID[198]:ARHC0*/ + /* After setting */ /* RGIDR_MODID[199]:ARHC1*/ + /* After setting */ /* RGIDR_MODID[200]:ARHC2*/ + [189] = {0xE6582148U, 0x0000000FU}, /* RGIDR_MODID[201]:ARHC3*/ + [190] = {0xE658214CU, 0x0000000FU}, /* RGIDR_MODID[202]:ARHC4*/ + [191] = {0xE6582150U, 0x0000000FU}, /* RGIDR_MODID[203]:ARHC5*/ + [192] = {0xE6582154U, 0x0000000FU}, /* RGIDR_MODID[204]:ARHC6*/ + [193] = {0xE6582158U, 0x0000000FU}, /* RGIDR_MODID[205]:ARHC7*/ + [194] = {0xE658215CU, 0x00000000U}, /* RGIDR_MODID[206]:ARHC8*/ + [195] = {0xE6582160U, 0x0000004EU}, /* RGIDR_MODID[207]:IPMMUHC03*/ + [196] = {0xE6582164U, 0x0000004EU}, /* RGIDR_MODID[208]:IPMMUHC04*/ + [197] = {0xE6582168U, 0x0000004EU}, /* RGIDR_MODID[209]:IPMMUHC05*/ + [198] = {0xE658216CU, 0x0000004EU}, /* RGIDR_MODID[210]:IPMMUHC06*/ + [199] = {0xE6582170U, 0x0000004EU}, /* RGIDR_MODID[211]:IPMMUHC07*/ + [200] = {0xE6582174U, 0x0000004EU}, /* RGIDR_MODID[212]:IPMMUHC08*/ + [201] = {0xE6582178U, 0x0000004EU}, /* RGIDR_MODID[213]:IPMMUHC09*/ + [202] = {0xFF882000U, 0x0000000FU}, /* RGIDR_MODID[214]:ARIMP00*/ + /* After setting */ /* RGIDR_MODID[215]:ARIMP01*/ + /* After setting */ /* RGIDR_MODID[216]:ARIMP02*/ + [203] = {0xFF88200CU, 0x0000000FU}, /* RGIDR_MODID[217]:ARIMP03*/ + [204] = {0xFF882010U, 0x0000000FU}, /* RGIDR_MODID[218]:ARIMP04*/ + [205] = {0xFF882014U, 0x0000004EU}, /* RGIDR_MODID[219]:AXIFBABUSIR0*/ + [206] = {0xFF882018U, 0x0000004EU}, /* RGIDR_MODID[220]:AXIFBABUSIR1*/ + [207] = {0xFF88201CU, 0x0000004EU}, /* RGIDR_MODID[221]:AXIFBABUSIR2*/ + [208] = {0xFF882020U, 0x0000004EU}, /* RGIDR_MODID[222]:AXIFBABUSIR3*/ + [209] = {0xFF882028U, 0x0000004EU}, /* RGIDR_MODID[223]:AXIIMP0*/ + [210] = {0xFF882034U, 0x0000000FU}, /* RGIDR_MODID[224]:ARIMP05*/ + [211] = {0xFF882038U, 0x0000000FU}, /* RGIDR_MODID[225]:ARIMP06*/ + [212] = {0xFF88203CU, 0x0000000FU}, /* RGIDR_MODID[226]:ARIMP07*/ + [213] = {0xFF882040U, 0x00000000U}, /* RGIDR_MODID[227]:ARIMP08*/ + [214] = {0xFF882048U, 0x0000000FU}, /* RGIDR_MODID[228]:ECMIR*/ + [215] = {0xFF88204CU, 0x0000000FU}, /* RGIDR_MODID[229]:DSPPS*/ + [216] = {0xFF882050U, 0x0000004EU}, /* RGIDR_MODID[230]:IPMMUIR1*/ + [217] = {0xFF882054U, 0x0000004EU}, /* RGIDR_MODID[231]:IPMMUIR0*/ + [218] = {0xFF882058U, 0x0000004EU}, /* RGIDR_MODID[232]:IPMMUIR10*/ + [219] = {0xFF88205CU, 0x0000004EU}, /* RGIDR_MODID[233]:IPMMUIR11*/ + [220] = {0xFF882060U, 0x0000004EU}, /* RGIDR_MODID[234]:IPMMUIR12*/ + [221] = {0xFF882064U, 0x0000004EU}, /* RGIDR_MODID[235]:IPMMUIR13*/ + [222] = {0xFF882068U, 0x0000004EU}, /* RGIDR_MODID[236]:IPMMUIR14*/ + [223] = {0xFF88206CU, 0x0000004EU}, /* RGIDR_MODID[237]:IPMMUIR15*/ + [224] = {0xFF882070U, 0x0000004EU}, /* RGIDR_MODID[238]:IPMMUIR2*/ + [225] = {0xFF882074U, 0x0000004EU}, /* RGIDR_MODID[239]:IPMMUIR3*/ + [226] = {0xFF882078U, 0x0000004EU}, /* RGIDR_MODID[240]:IPMMUIR4*/ + [227] = {0xFF88207CU, 0x0000004EU}, /* RGIDR_MODID[241]:IPMMUIR5*/ + [228] = {0xFF882080U, 0x0000004EU}, /* RGIDR_MODID[242]:IPMMUIR6*/ + [229] = {0xFF882084U, 0x0000004EU}, /* RGIDR_MODID[243]:IPMMUIR7*/ + [230] = {0xFF882088U, 0x0000004EU}, /* RGIDR_MODID[244]:IPMMUIR8*/ + [231] = {0xFF88208CU, 0x0000004EU}, /* RGIDR_MODID[245]:IPMMUIR9*/ + [232] = {0xFD812000U, 0x0000000FU}, /* RGIDR_MODID[246]:ARPV0*/ + /* After setting */ /* RGIDR_MODID[247]:ARPV1*/ + [233] = {0xFD812008U, 0x0000002CU}, /* RGIDR_MODID[248]:AXIRGXS*/ + /* After setting */ /* RGIDR_MODID[249]:ARPV2*/ + [234] = {0xFD812010U, 0x0000000FU}, /* RGIDR_MODID[250]:ARPV3*/ + [235] = {0xFD812014U, 0x0000000FU}, /* RGIDR_MODID[251]:ARPV4*/ + [236] = {0xFD812018U, 0x0000000FU}, /* RGIDR_MODID[252]:ARPV5*/ + [237] = {0xFD81201CU, 0x0000000FU}, /* RGIDR_MODID[253]:ARPV6*/ + [238] = {0xFD812020U, 0x0000000FU}, /* RGIDR_MODID[254]:ARPV7*/ + [239] = {0xFD812024U, 0x00000000U}, /* RGIDR_MODID[255]:ARPV8*/ + [240] = {0xFD81202CU, 0x0000000FU}, /* RGIDR_MODID[256]:ECM3DG*/ + [241] = {0xFD812030U, 0x0000000EU}, /* RGIDR_MODID[257]:FBAPVC*/ + [242] = {0xFD812034U, 0x0000000EU}, /* RGIDR_MODID[258]:FBAPVD0*/ + [243] = {0xFD812038U, 0x0000000EU}, /* RGIDR_MODID[259]:FBAPVD1*/ + [244] = {0xFD81203CU, 0x0000000EU}, /* RGIDR_MODID[260]:FBAPVD2*/ + [245] = {0xFD812040U, 0x0000000EU}, /* RGIDR_MODID[261]:FBAPVE*/ + [246] = {0xFD812044U, 0x0000004EU}, /* RGIDR_MODID[262]:IPMMUPV000*/ + [247] = {0xFD812048U, 0x0000004EU}, /* RGIDR_MODID[263]:IPMMUPV001*/ + [248] = {0xFD81204CU, 0x0000004EU}, /* RGIDR_MODID[264]:IPMMUPV010*/ + [249] = {0xFD812050U, 0x0000004EU}, /* RGIDR_MODID[265]:IPMMUPV011*/ + [250] = {0xFD812054U, 0x0000004EU}, /* RGIDR_MODID[266]:IPMMUPV012*/ + [251] = {0xFD812058U, 0x0000004EU}, /* RGIDR_MODID[267]:IPMMUPV013*/ + [252] = {0xFD81205CU, 0x0000004EU}, /* RGIDR_MODID[268]:IPMMUPV014*/ + [253] = {0xFD812060U, 0x0000004EU}, /* RGIDR_MODID[269]:IPMMUPV015*/ + [254] = {0xFD812064U, 0x0000004EU}, /* RGIDR_MODID[270]:IPMMUPV002*/ + [255] = {0xFD812068U, 0x0000004EU}, /* RGIDR_MODID[271]:IPMMUPV003*/ + [256] = {0xFD81206CU, 0x0000004EU}, /* RGIDR_MODID[272]:IPMMUPV004*/ + [257] = {0xFD812070U, 0x0000004EU}, /* RGIDR_MODID[273]:IPMMUPV005*/ + [258] = {0xFD812074U, 0x0000004EU}, /* RGIDR_MODID[274]:IPMMUPV006*/ + [259] = {0xFD812078U, 0x0000004EU}, /* RGIDR_MODID[275]:IPMMUPV007*/ + [260] = {0xFD81207CU, 0x0000004EU}, /* RGIDR_MODID[276]:IPMMUPV008*/ + [261] = {0xFD812080U, 0x0000004EU}, /* RGIDR_MODID[277]:IPMMUPV009*/ + [262] = {0xE6622000U, 0x0000000FU}, /* RGIDR_MODID[278]:ARRC0*/ + /* After setting */ /* RGIDR_MODID[279]:ARRC1*/ + /* After setting */ /* RGIDR_MODID[280]:ARRC2*/ + [263] = {0xE662200CU, 0x0000000FU}, /* RGIDR_MODID[281]:ARRC3*/ + [264] = {0xE6622010U, 0x0000000FU}, /* RGIDR_MODID[282]:ARRC4*/ + [265] = {0xE6622014U, 0x0000000FU}, /* RGIDR_MODID[283]:ARRC5*/ + [266] = {0xE6622018U, 0x0000000FU}, /* RGIDR_MODID[284]:ARRC6*/ + [267] = {0xE662201CU, 0x0000000FU}, /* RGIDR_MODID[285]:ARRC7*/ + [268] = {0xE6622020U, 0x00000000U}, /* RGIDR_MODID[286]:ARRC8*/ + [269] = {0xE6622028U, 0x0000004FU}, /* RGIDR_MODID[287]:ICUMX*/ + [270] = {0xE662202CU, 0x0000000FU}, /* RGIDR_MODID[288]:ECMRC*/ + [271] = {0xFFC32000U, 0x0000004EU}, /* RGIDR_MODID[289]:DMAWCRC0*/ + [272] = {0xFFC32004U, 0x0000004EU}, /* RGIDR_MODID[290]:DMAWCRC1*/ + [273] = {0xFFC32008U, 0x0000004EU}, /* RGIDR_MODID[291]:DMAWCRC2*/ + [274] = {0xFFC3200CU, 0x0000004EU}, /* RGIDR_MODID[292]:DMAWCRC3*/ + [275] = {0xFFC42000U, 0x0000000FU}, /* RGIDR_MODID[293]:ARMREG00*/ + [276] = {0xFFC42004U, 0x0000000DU}, /* RGIDR_MODID[294]:ARMREG01*/ + [277] = {0xFFC42008U, 0x00000000U}, /* RGIDR_MODID[295]:ARMREG10*/ + [278] = {0xFFC4200CU, 0x00000000U}, /* RGIDR_MODID[296]:ARMREG11*/ + [279] = {0xFFC42010U, 0x0000000BU}, /* RGIDR_MODID[297]:ARMREG12*/ + [280] = {0xFFC42014U, 0x0000000FU}, /* RGIDR_MODID[298]:ARMREG13*/ + [281] = {0xFFC42018U, 0x0000000BU}, /* RGIDR_MODID[299]:ARMREG14*/ + [282] = {0xFFC4201CU, 0x00000002U}, /* RGIDR_MODID[300]:AXICR52SS0*/ + [283] = {0xFFC42020U, 0x0000000EU}, /* RGIDR_MODID[301]:AXICSD0*/ + [284] = {0xFFC42024U, 0x0000000EU}, /* RGIDR_MODID[302]:AXIINTAP0*/ + [285] = {0xFFC4202CU, 0x00000009U}, /* RGIDR_MODID[303]:AXISECROM*/ + [286] = {0xFFC42030U, 0x0000000FU}, /* RGIDR_MODID[304]:AXISYSRAM0*/ + [287] = {0xFFC42034U, 0x0000004FU}, /* RGIDR_MODID[305]:AXISYSRAM1*/ + [288] = {0xFFC42038U, 0x00000000U}, /* RGIDR_MODID[306]:ARGREG15*/ + [289] = {0xFFC4203CU, 0x00000000U}, /* RGIDR_MODID[307]:ARMREG2*/ + [290] = {0xFFC42040U, 0x00000000U}, /* RGIDR_MODID[308]:ARMREG3*/ + [291] = {0xFFC42044U, 0x00000000U}, /* RGIDR_MODID[309]:ARMREG4*/ + [292] = {0xFFC42048U, 0x0000000FU}, /* RGIDR_MODID[310]:ARMREG5*/ + [293] = {0xFFC4204CU, 0x0000000FU}, /* RGIDR_MODID[311]:ARMREG6*/ + [294] = {0xFFC42050U, 0x00000000U}, /* RGIDR_MODID[312]:ARMREG7*/ + [295] = {0xFFC42054U, 0x0000000DU}, /* RGIDR_MODID[313]:ARMREG8*/ + [296] = {0xFFC42058U, 0x0000000DU}, /* RGIDR_MODID[314]:ARMREG9*/ + [297] = {0xFFC4205CU, 0x0000000FU}, /* RGIDR_MODID[315]:ARRD0*/ + /* After setting */ /* RGIDR_MODID[316]:ARRD1*/ + /* After setting */ /* RGIDR_MODID[317]:ARRD2*/ + [298] = {0xFFC42068U, 0x0000000FU}, /* RGIDR_MODID[318]:ARRD3*/ + [299] = {0xFFC4206CU, 0x0000000FU}, /* RGIDR_MODID[319]:ARRD4*/ + [300] = {0xFFC42070U, 0x0000000FU}, /* RGIDR_MODID[320]:ARRD5*/ + [301] = {0xFFC42074U, 0x0000000FU}, /* RGIDR_MODID[321]:ARRD6*/ + [302] = {0xFFC42078U, 0x0000000FU}, /* RGIDR_MODID[322]:ARRD7*/ + [303] = {0xFFC4207CU, 0x00000000U}, /* RGIDR_MODID[323]:ARRD8*/ + [304] = {0xFFC42080U, 0x0000000FU}, /* RGIDR_MODID[324]:ARRT0*/ + /* After setting */ /* RGIDR_MODID[325]:ARRT1*/ + /* After setting */ /* RGIDR_MODID[326]:ARRT2*/ + [305] = {0xFFC4208CU, 0x0000000FU}, /* RGIDR_MODID[327]:ARRT3*/ + [306] = {0xFFC42090U, 0x0000000FU}, /* RGIDR_MODID[328]:ARRT4*/ + [307] = {0xFFC42094U, 0x0000000FU}, /* RGIDR_MODID[329]:ARRT5*/ + [308] = {0xFFC42098U, 0x0000000FU}, /* RGIDR_MODID[330]:ARRT6*/ + [309] = {0xFFC4209CU, 0x0000000FU}, /* RGIDR_MODID[331]:ARRT7*/ + [310] = {0xFFC420A0U, 0x00000000U}, /* RGIDR_MODID[332]:ARRT8*/ + [311] = {0xFFC420A4U, 0x0000000AU}, /* RGIDR_MODID[333]:CKMRT*/ + [312] = {0xFFC420A8U, 0x0000004EU}, /* RGIDR_MODID[334]:CRC0*/ + [313] = {0xFFC420ACU, 0x0000004EU}, /* RGIDR_MODID[335]:CRC1*/ + [314] = {0xFFC420B0U, 0x0000004EU}, /* RGIDR_MODID[336]:CRC2*/ + [315] = {0xFFC420B4U, 0x0000004EU}, /* RGIDR_MODID[337]:CRC3*/ + [316] = {0xFFC420B8U, 0x0000000EU}, /* RGIDR_MODID[338]:CSD*/ + [317] = {0xFFC420BCU, 0x0000000FU}, /* RGIDR_MODID[339]:ECM*/ + [318] = {0xFFC420C0U, 0x0000000FU}, /* RGIDR_MODID[340]:ECMRT*/ + [319] = {0xFFC420C4U, 0x0000000EU}, /* RGIDR_MODID[341]:FBACR52*/ + [320] = {0xFFC420C8U, 0x0000000EU}, /* RGIDR_MODID[342]:FBART*/ + [321] = {0xFFC420CCU, 0x0000000EU}, /* RGIDR_MODID[343]:INTTP*/ + [322] = {0xFFC420D0U, 0x0000004EU}, /* RGIDR_MODID[344]:IPMMURT000*/ + [323] = {0xFFC420D4U, 0x0000004EU}, /* RGIDR_MODID[345]:IPMMURT100*/ + [324] = {0xFFC420D8U, 0x0000004EU}, /* RGIDR_MODID[346]:KCRC4*/ + [325] = {0xFFC420DCU, 0x0000004EU}, /* RGIDR_MODID[347]:KCRC5*/ + [326] = {0xFFC420E0U, 0x0000004EU}, /* RGIDR_MODID[348]:KCRC6*/ + [327] = {0xFFC420E4U, 0x0000004EU}, /* RGIDR_MODID[349]:KCRC7*/ + [328] = {0xFFC420E8U, 0x0000004FU}, /* RGIDR_MODID[350]:MFI00*/ + [329] = {0xFFC420ECU, 0x0000004EU}, /* RGIDR_MODID[351]:MFI01*/ + [330] = {0xFFC420F0U, 0x0000004EU}, /* RGIDR_MODID[352]:MFI10*/ + [331] = {0xFFC420F4U, 0x0000004EU}, /* RGIDR_MODID[353]:MFI02*/ + [332] = {0xFFC420F8U, 0x0000004EU}, /* RGIDR_MODID[354]:MFI03*/ + [333] = {0xFFC420FCU, 0x0000004EU}, /* RGIDR_MODID[355]:MFI04*/ + [334] = {0xFFC42100U, 0x00000000U}, /* RGIDR_MODID[356]:MFI05*/ + [335] = {0xFFC42104U, 0x00000000U}, /* RGIDR_MODID[357]:MFI06*/ + [336] = {0xFFC42108U, 0x00000000U}, /* RGIDR_MODID[358]:MFI07*/ + [337] = {0xFFC4210CU, 0x00000000U}, /* RGIDR_MODID[359]:MFI08*/ + [338] = {0xFFC42110U, 0x0000004EU}, /* RGIDR_MODID[360]:MFI09*/ + [339] = {0xFFC42114U, 0x0000004FU}, /* RGIDR_MODID[361]:MFI15*/ + [340] = {0xFFC42118U, 0x0000000AU}, /* RGIDR_MODID[362]:CKMCR52*/ + [341] = {0xFFC4211CU, 0x0000004BU}, /* RGIDR_MODID[363]:RTDM0P*/ + [342] = {0xFFC42120U, 0x0000000FU}, /* RGIDR_MODID[364]:ECMRD*/ + [343] = {0xFFC42124U, 0x0000004BU}, /* RGIDR_MODID[365]:RTDM1P*/ + [344] = {0xFFC42130U, 0x0000000BU}, /* RGIDR_MODID[366]:SYSRAM10*/ + [345] = {0xFFC42138U, 0x00000003U}, /* RGIDR_MODID[367]:SYSRAM00*/ + [346] = {0xFFC4213CU, 0x0000004EU}, /* RGIDR_MODID[368]:TSIPL0*/ + [347] = {0xFFC42140U, 0x0000004EU}, /* RGIDR_MODID[369]:TSIPL1*/ + [348] = {0xFFC42144U, 0x0000004EU}, /* RGIDR_MODID[370]:TSIPL2*/ + [349] = {0xFFC42148U, 0x0000004EU}, /* RGIDR_MODID[371]:TSIPL3*/ + [350] = {0xFFC4214CU, 0x0000004EU}, /* RGIDR_MODID[372]:TSIPL4*/ + [351] = {0xFFC42150U, 0x0000004EU}, /* RGIDR_MODID[373]:TSIPL5*/ + [352] = {0xFFC42154U, 0x0000004EU}, /* RGIDR_MODID[374]:TSIPL6*/ + [353] = {0xFFC42158U, 0x0000004EU}, /* RGIDR_MODID[375]:TSIPL7*/ + [354] = {0xFFC4215CU, 0x0000004EU}, /* RGIDR_MODID[376]:WCRC0*/ + [355] = {0xFFC42160U, 0x0000004EU}, /* RGIDR_MODID[377]:WCRC1*/ + [356] = {0xFFC42164U, 0x0000004EU}, /* RGIDR_MODID[378]:WCRC2*/ + [357] = {0xFFC42168U, 0x0000004EU}, /* RGIDR_MODID[379]:WCRC3*/ + [358] = {0xFFC42180U, 0x0000004EU}, /* RGIDR_MODID[380]:MFI11*/ + [359] = {0xFFC42184U, 0x00000000U}, /* RGIDR_MODID[381]:MFI12*/ + [360] = {0xFFC42188U, 0x00000000U}, /* RGIDR_MODID[382]:MFI13*/ + [361] = {0xFFC4218CU, 0x00000000U}, /* RGIDR_MODID[383]:MFI14*/ + [362] = {0xFFC42190U, 0x0000004EU}, /* RGIDR_MODID[384]:IPMMURT001*/ + [363] = {0xFFC42194U, 0x0000004EU}, /* RGIDR_MODID[385]:IPMMURT010*/ + [364] = {0xFFC42198U, 0x0000004EU}, /* RGIDR_MODID[386]:IPMMURT011*/ + [365] = {0xFFC4219CU, 0x0000004EU}, /* RGIDR_MODID[387]:IPMMURT012*/ + [366] = {0xFFC421A0U, 0x0000004EU}, /* RGIDR_MODID[388]:IPMMURT013*/ + [367] = {0xFFC421A4U, 0x0000004EU}, /* RGIDR_MODID[389]:IPMMURT014*/ + [368] = {0xFFC421A8U, 0x0000004EU}, /* RGIDR_MODID[390]:IPMMURT015*/ + [369] = {0xFFC421ACU, 0x0000004EU}, /* RGIDR_MODID[391]:IPMMURT002*/ + [370] = {0xFFC421B0U, 0x0000004EU}, /* RGIDR_MODID[392]:IPMMURT003*/ + [371] = {0xFFC421B4U, 0x0000004EU}, /* RGIDR_MODID[393]:IPMMURT004*/ + [372] = {0xFFC421B8U, 0x0000004EU}, /* RGIDR_MODID[394]:IPMMURT005*/ + [373] = {0xFFC421BCU, 0x0000004EU}, /* RGIDR_MODID[395]:IPMMURT006*/ + [374] = {0xFFC421C0U, 0x0000004EU}, /* RGIDR_MODID[396]:IPMMURT007*/ + [375] = {0xFFC421C4U, 0x0000004EU}, /* RGIDR_MODID[397]:IPMMURT008*/ + [376] = {0xFFC421C8U, 0x0000004EU}, /* RGIDR_MODID[398]:IPMMURT009*/ + [377] = {0xFFC421CCU, 0x0000004EU}, /* RGIDR_MODID[399]:IPKMURT101*/ + [378] = {0xFFC421D0U, 0x0000004EU}, /* RGIDR_MODID[400]:IPMMURT110*/ + [379] = {0xFFC421D4U, 0x0000004EU}, /* RGIDR_MODID[401]:IPMMURT111*/ + [380] = {0xFFC421D8U, 0x0000004EU}, /* RGIDR_MODID[402]:IPMMURT112*/ + [381] = {0xFFC421DCU, 0x0000004EU}, /* RGIDR_MODID[403]:IPMMURT113*/ + [382] = {0xFFC421E0U, 0x0000004EU}, /* RGIDR_MODID[404]:IPMMURT114*/ + [383] = {0xFFC421E4U, 0x0000004EU}, /* RGIDR_MODID[405]:IPMMURT115*/ + [384] = {0xFFC421E8U, 0x0000004EU}, /* RGIDR_MODID[406]:IPMMURT102*/ + [385] = {0xFFC421ECU, 0x0000004EU}, /* RGIDR_MODID[407]:IPMMURT103*/ + [386] = {0xFFC421F0U, 0x0000004EU}, /* RGIDR_MODID[408]:IPMMURT104*/ + [387] = {0xFFC421F4U, 0x0000004EU}, /* RGIDR_MODID[409]:IPMMURT105*/ + [388] = {0xFFC421F8U, 0x0000004EU}, /* RGIDR_MODID[410]:IPMMURT106*/ + [389] = {0xFFC421FCU, 0x0000004EU}, /* RGIDR_MODID[411]:IPMMURT107*/ + [390] = {0xFFC42200U, 0x0000004BU}, /* RGIDR_MODID[412]:RTDM000*/ + [391] = {0xFFC42204U, 0x0000004BU}, /* RGIDR_MODID[413]:RTDM001*/ + [392] = {0xFFC42208U, 0x0000004BU}, /* RGIDR_MODID[414]:RTDM010*/ + [393] = {0xFFC4220CU, 0x0000004BU}, /* RGIDR_MODID[415]:RTDM011*/ + [394] = {0xFFC42210U, 0x0000004BU}, /* RGIDR_MODID[416]:RTDM012*/ + [395] = {0xFFC42214U, 0x0000004BU}, /* RGIDR_MODID[417]:RTDM013*/ + [396] = {0xFFC42218U, 0x0000004BU}, /* RGIDR_MODID[418]:RTDM014*/ + [397] = {0xFFC4221CU, 0x0000004BU}, /* RGIDR_MODID[419]:RTDM015*/ + [398] = {0xFFC42220U, 0x0000004BU}, /* RGIDR_MODID[420]:RTDM002*/ + [399] = {0xFFC42224U, 0x0000004BU}, /* RGIDR_MODID[421]:RTDM003*/ + [400] = {0xFFC42228U, 0x0000004BU}, /* RGIDR_MODID[422]:RTDM004*/ + [401] = {0xFFC4222CU, 0x0000004BU}, /* RGIDR_MODID[423]:RTDM005*/ + [402] = {0xFFC42230U, 0x0000004BU}, /* RGIDR_MODID[424]:RTDM006*/ + [403] = {0xFFC42234U, 0x0000004BU}, /* RGIDR_MODID[425]:RTDM007*/ + [404] = {0xFFC42238U, 0x0000004BU}, /* RGIDR_MODID[426]:RTDM008*/ + [405] = {0xFFC4223CU, 0x0000004BU}, /* RGIDR_MODID[427]:RTDM009*/ + [406] = {0xFFC42240U, 0x0000004BU}, /* RGIDR_MODID[428]:RTDM100*/ + [407] = {0xFFC42244U, 0x0000004BU}, /* RGIDR_MODID[429]:RTDM101*/ + [408] = {0xFFC42248U, 0x0000004BU}, /* RGIDR_MODID[430]:RTDM110*/ + [409] = {0xFFC4224CU, 0x0000004BU}, /* RGIDR_MODID[431]:RTDM111*/ + [410] = {0xFFC42250U, 0x0000004BU}, /* RGIDR_MODID[432]:RTDM112*/ + [411] = {0xFFC42254U, 0x0000004BU}, /* RGIDR_MODID[433]:RTDM113*/ + [412] = {0xFFC42258U, 0x0000004BU}, /* RGIDR_MODID[434]:RTDM114*/ + [413] = {0xFFC4225CU, 0x0000004BU}, /* RGIDR_MODID[435]:RTDM115*/ + [414] = {0xFFC42260U, 0x0000004BU}, /* RGIDR_MODID[436]:RTDM102*/ + [415] = {0xFFC42264U, 0x0000004BU}, /* RGIDR_MODID[437]:RTDM103*/ + [416] = {0xFFC42268U, 0x0000004BU}, /* RGIDR_MODID[438]:RTDM104*/ + [417] = {0xFFC4226CU, 0x0000004BU}, /* RGIDR_MODID[439]:RTDM105*/ + [418] = {0xFFC42270U, 0x0000004BU}, /* RGIDR_MODID[440]:RTDM106*/ + [419] = {0xFFC42274U, 0x0000004BU}, /* RGIDR_MODID[441]:RTDM107*/ + [420] = {0xFFC42278U, 0x0000004BU}, /* RGIDR_MODID[442]:RTDM108*/ + [421] = {0xFFC4227CU, 0x0000004BU}, /* RGIDR_MODID[443]:RTDM109*/ + [422] = {0xFFC42300U, 0x0000004EU}, /* RGIDR_MODID[444]:IPMMURT108*/ + [423] = {0xFFC42304U, 0x0000004EU}, /* RGIDR_MODID[445]:IPMMURT109*/ + [424] = {0xFFC42308U, 0x00000001U}, /* RGIDR_MODID[446]:SYSRAM01*/ + [425] = {0xFFC4230CU, 0x0000000BU}, /* RGIDR_MODID[447]:SYSRAM02*/ + [426] = {0xFFC42310U, 0x00000001U}, /* RGIDR_MODID[448]:SYSRAM03*/ + [427] = {0xFFC42314U, 0x00000001U}, /* RGIDR_MODID[449]:SYSRAM04*/ + [428] = {0xFFC42318U, 0x00000001U}, /* RGIDR_MODID[450]:SYSRAM05*/ + [429] = {0xFFC4231CU, 0x00000001U}, /* RGIDR_MODID[451]:SYSRAM06*/ + [430] = {0xFFC42320U, 0x00000000U}, /* RGIDR_MODID[452]:SYSRAM07*/ + [431] = {0xFFC42324U, 0x0000000BU}, /* RGIDR_MODID[453]:SYSRAM11*/ + [432] = {0xFFC42328U, 0x0000000BU}, /* RGIDR_MODID[454]:SYSRAM12*/ + [433] = {0xFFC4232CU, 0x0000000BU}, /* RGIDR_MODID[455]:SYSRAM13*/ + [434] = {0xFFC42330U, 0x0000000BU}, /* RGIDR_MODID[456]:SYSRAM14*/ + [435] = {0xFFC42334U, 0x0000000BU}, /* RGIDR_MODID[457]:SYSRAM15*/ + [436] = {0xFFC42338U, 0x0000000BU}, /* RGIDR_MODID[458]:SYSRAM16*/ + [437] = {0xFFC4233CU, 0x00000000U}, /* RGIDR_MODID[459]:SYSRAM17*/ + [438] = {0xFFC42360U, 0x00000002U}, /* RGIDR_MODID[460]:BKBUF*/ + [439] = {0xFFC42364U, 0x00000002U}, /* RGIDR_MODID[461]:AXICR52SS1*/ + [440] = {0xFFC42368U, 0x00000002U}, /* RGIDR_MODID[462]:AXICR52SS2*/ + [441] = {0xFF862000U, 0x0000000FU}, /* RGIDR_MODID[463]:ARSC0*/ + /* After setting */ /* RGIDR_MODID[464]:ARSC1*/ + /* After setting */ /* RGIDR_MODID[465]:ARSC2*/ + [442] = {0xFF86200CU, 0x0000000FU}, /* RGIDR_MODID[466]:ARSC3*/ + [443] = {0xFF862010U, 0x0000000FU}, /* RGIDR_MODID[467]:ARSC4*/ + [444] = {0xFF862014U, 0x0000000FU}, /* RGIDR_MODID[468]:ARSC5*/ + [445] = {0xFF862018U, 0x0000000FU}, /* RGIDR_MODID[469]:ARSC6*/ + [446] = {0xFF86201CU, 0x0000000FU}, /* RGIDR_MODID[470]:ARSC7*/ + [447] = {0xFF862020U, 0x00000000U}, /* RGIDR_MODID[471]:ARSC8*/ + [448] = {0xFF862024U, 0x0000000FU}, /* RGIDR_MODID[472]:ARSTM0*/ + /* After setting */ /* RGIDR_MODID[473]:ARSTM1*/ + [449] = {0xFF86202CU, 0x0000000EU}, /* RGIDR_MODID[474]:CSD1S*/ + [450] = {0xFF862030U, 0x0000000EU}, /* RGIDR_MODID[475]:AXIFBABUSTOP0*/ + /* After setting */ /* RGIDR_MODID[476]:ARSTM2*/ + [451] = {0xFF86203CU, 0x0000000FU}, /* RGIDR_MODID[477]:ARSTM3*/ + [452] = {0xFF862040U, 0x0000000FU}, /* RGIDR_MODID[478]:ARSTM4*/ + [453] = {0xFF862044U, 0x0000000FU}, /* RGIDR_MODID[479]:ARSTM5*/ + [454] = {0xFF862048U, 0x0000000FU}, /* RGIDR_MODID[480]:ARSTM6*/ + [455] = {0xFF86204CU, 0x0000000FU}, /* RGIDR_MODID[481]:ARSTM7*/ + [456] = {0xFF862050U, 0x00000000U}, /* RGIDR_MODID[482]:ARSTM8*/ + [457] = {0xFF862054U, 0x0000000FU}, /* RGIDR_MODID[483]:ECMTOP*/ + [458] = {0xFF862058U, 0x0000000EU}, /* RGIDR_MODID[484]:FBA*/ + [459] = {0xFF86205CU, 0x0000000EU}, /* RGIDR_MODID[485]:FBC*/ + [460] = {0xFF862034U, 0x0000000CU}, /* RGIDR_MODID[486]:AXICCI00*/ + [461] = {0xFF862060U, 0x0000000CU}, /* RGIDR_MODID[487]:AXICCI01*/ + [462] = {0xFF862064U, 0x0000000CU}, /* RGIDR_MODID[488]:AXICCI10*/ + [463] = {0xFF862068U, 0x0000000CU}, /* RGIDR_MODID[489]:AXICCI11*/ + [464] = {0xFF86206CU, 0x0000000CU}, /* RGIDR_MODID[490]:AXICCI12*/ + [465] = {0xFF862070U, 0x0000000CU}, /* RGIDR_MODID[491]:AXICCI13*/ + [466] = {0xFF862074U, 0x0000000CU}, /* RGIDR_MODID[492]:AXICCI14*/ + [467] = {0xFF862078U, 0x0000000CU}, /* RGIDR_MODID[493]:AXICCI15*/ + [468] = {0xFF86207CU, 0x0000000CU}, /* RGIDR_MODID[494]:AXICCI2*/ + [469] = {0xFF862080U, 0x0000000CU}, /* RGIDR_MODID[495]:AXICCI3*/ + [470] = {0xFF862084U, 0x0000000CU}, /* RGIDR_MODID[496]:AXICCI4*/ + [471] = {0xFF862088U, 0x0000000CU}, /* RGIDR_MODID[497]:AXICCI5*/ + [472] = {0xFF86208CU, 0x0000000CU}, /* RGIDR_MODID[498]:AXICCI6*/ + [473] = {0xFF862090U, 0x0000000CU}, /* RGIDR_MODID[499]:AXICCI7*/ + [474] = {0xFF862094U, 0x0000000CU}, /* RGIDR_MODID[500]:AXICCI8*/ + [475] = {0xFF862098U, 0x0000000FU}, /* RGIDR_MODID[501]:AXICCI9*/ + [476] = {0xFF8620A0U, 0x0000000FU}, /* RGIDR_MODID[502]:ECMSTM*/ + [477] = {0xE7782000U, 0x0000002CU}, /* RGIDR_MODID[503]:DMASSI00*/ + [478] = {0xE7782004U, 0x0000002CU}, /* RGIDR_MODID[504]:DMASSI01*/ + [479] = {0xE7782008U, 0x0000002CU}, /* RGIDR_MODID[505]:DMASSI02*/ + [480] = {0xE778200CU, 0x0000002CU}, /* RGIDR_MODID[506]:DMASSI03*/ + [481] = {0xE7782010U, 0x0000002CU}, /* RGIDR_MODID[507]:DMASSI04*/ + [482] = {0xE7782014U, 0x0000004EU}, /* RGIDR_MODID[508]:DMAI2C0*/ + [483] = {0xE7782018U, 0x0000004EU}, /* RGIDR_MODID[509]:DMAI2C1*/ + [484] = {0xE778201CU, 0x0000004EU}, /* RGIDR_MODID[510]:DMAI2C2*/ + [485] = {0xE7782020U, 0x0000004EU}, /* RGIDR_MODID[511]:DMAI2C3*/ + [486] = {0xE778202CU, 0x0000002CU}, /* RGIDR_MODID[512]:DMASSI05*/ + [487] = {0xE7782030U, 0x0000002CU}, /* RGIDR_MODID[513]:DMASSI06*/ + [488] = {0xE7782034U, 0x0000002CU}, /* RGIDR_MODID[514]:DMASSI07*/ + [489] = {0xE67C2000U, 0x00000007U}, /* RGIDR_MODID[515]:ARMM*/ + /* After setting */ /* RGIDR_MODID[516]:AXIARNMM*/ + [490] = {0xE67C2008U, 0x0000000FU}, /* RGIDR_MODID[517]:ARSM0*/ + /* After setting */ /* RGIDR_MODID[518]:ARSM1*/ + /* After setting */ /* RGIDR_MODID[519]:ARSM2*/ + [491] = {0xE67C2014U, 0x0000000FU}, /* RGIDR_MODID[520]:AXIQOS0*/ + [492] = {0xE67C2018U, 0x0000000FU}, /* RGIDR_MODID[521]:AXIQOS1*/ + [493] = {0xE67C201CU, 0x0000000FU}, /* RGIDR_MODID[522]:AXIQOS2*/ + [494] = {0xE67C2020U, 0x0000000FU}, /* RGIDR_MODID[523]:AXIQOS3*/ + [495] = {0xE67C2024U, 0x0000000FU}, /* RGIDR_MODID[524]:AXIQOS4*/ + [496] = {0xE67C2028U, 0x0000000FU}, /* RGIDR_MODID[525]:AXIQOS5*/ + [497] = {0xE67C2034U, 0x0000000FU}, /* RGIDR_MODID[526]:ARSM3*/ + [498] = {0xE67C2038U, 0x0000000FU}, /* RGIDR_MODID[527]:ARSM4*/ + [499] = {0xE67C203CU, 0x0000000FU}, /* RGIDR_MODID[528]:ARSM5*/ + [500] = {0xE67C2040U, 0x0000000FU}, /* RGIDR_MODID[529]:ARSM6*/ + [501] = {0xE67C2044U, 0x0000000FU}, /* RGIDR_MODID[530]:ARSM7*/ + [502] = {0xE67C2048U, 0x00000000U}, /* RGIDR_MODID[531]:ARSM8*/ + [503] = {0xE67C204CU, 0x0000000BU}, /* RGIDR_MODID[532]:AXMM0*/ + [504] = {0xE67C2050U, 0x0000000BU}, /* RGIDR_MODID[533]:AXMM1*/ + [505] = {0xE67C2054U, 0x00000000U}, /* RGIDR_MODID[534]:AXMMPMON*/ + [506] = {0xE67C2058U, 0x0000000AU}, /* RGIDR_MODID[535]:CKMMM*/ + [507] = {0xE67C205CU, 0x0000000FU}, /* RGIDR_MODID[536]:ECMMM*/ + [508] = {0xE67C2060U, 0x0000000EU}, /* RGIDR_MODID[537]:FBADBSC0*/ + [509] = {0xE67C2068U, 0x0000000EU}, /* RGIDR_MODID[538]:FBAMM*/ + [510] = {0xE67C206CU, 0x0000004EU}, /* RGIDR_MODID[539]:IPMMUMM00*/ + [511] = {0xE67C2070U, 0x0000000FU}, /* RGIDR_MODID[540]:DBS0A0*/ + [512] = {0xE67C2074U, 0x0000000AU}, /* RGIDR_MODID[541]:DBS0A1*/ + [513] = {0xE67C2084U, 0x00000009U}, /* RGIDR_MODID[542]:FCPRC*/ + [514] = {0xE67C2088U, 0x0000000FU}, /* RGIDR_MODID[543]:DBS0D0*/ + [515] = {0xE67C208CU, 0x0000000AU}, /* RGIDR_MODID[544]:DBS0D1*/ + [516] = {0xE67C2098U, 0x0000000EU}, /* RGIDR_MODID[545]:FBADDR*/ + [517] = {0xE67C209CU, 0x0000004EU}, /* RGIDR_MODID[546]:IPMMUMM01*/ + [518] = {0xE67C20A0U, 0x0000004EU}, /* RGIDR_MODID[547]:IPMMUMM10*/ + [519] = {0xE67C20A4U, 0x0000004EU}, /* RGIDR_MODID[548]:IPMMUMM11*/ + [520] = {0xE67C20A8U, 0x0000004EU}, /* RGIDR_MODID[549]:IPMMUMM12*/ + [521] = {0xE67C20ACU, 0x0000004EU}, /* RGIDR_MODID[550]:IPMMUMM13*/ + [522] = {0xE67C20B0U, 0x0000004EU}, /* RGIDR_MODID[551]:IPMMUMM14*/ + [523] = {0xE67C20B4U, 0x0000004EU}, /* RGIDR_MODID[552]:IPMMUMM15*/ + [524] = {0xE67C20B8U, 0x0000004EU}, /* RGIDR_MODID[553]:IPMMUMM02*/ + [525] = {0xE67C20BCU, 0x0000004EU}, /* RGIDR_MODID[554]:IPMMUMM03*/ + [526] = {0xE67C20C0U, 0x0000004EU}, /* RGIDR_MODID[555]:IPMMUMM04*/ + [527] = {0xE67C20C4U, 0x0000004EU}, /* RGIDR_MODID[556]:IPMMUMM05*/ + [528] = {0xE67C20C8U, 0x0000004EU}, /* RGIDR_MODID[557]:IPMMUMM06*/ + [529] = {0xE67C20CCU, 0x0000004EU}, /* RGIDR_MODID[558]:IPMMUMM07*/ + [530] = {0xE67C20D0U, 0x0000004EU}, /* RGIDR_MODID[559]:IPMMUMM08*/ + [531] = {0xE67C20D4U, 0x0000004EU}, /* RGIDR_MODID[560]:IPMMUMM09*/ + [532] = {0xFF802000U, 0x0000000FU}, /* RGIDR_MODID[561]:ARSN0*/ + /* After setting */ /* RGIDR_MODID[562]:ARSN1*/ + /* After setting */ /* RGIDR_MODID[563]:ARSN2*/ + [533] = {0xFF80200CU, 0x0000000FU}, /* RGIDR_MODID[564]:ARSN3*/ + [534] = {0xFF802010U, 0x0000000FU}, /* RGIDR_MODID[565]:ARSN4*/ + [535] = {0xFF802014U, 0x0000000FU}, /* RGIDR_MODID[566]:ARSN5*/ + [536] = {0xFF802018U, 0x0000000FU}, /* RGIDR_MODID[567]:ARSN6*/ + [537] = {0xFF80201CU, 0x00000007U}, /* RGIDR_MODID[568]:ARSN7*/ + [538] = {0xFF802020U, 0x00000000U}, /* RGIDR_MODID[569]:ARSN8*/ + [539] = {0xFF802024U, 0x0000000FU}, /* RGIDR_MODID[570]:ECMTOP3*/ + [540] = {0xE7752000U, 0x0000000FU}, /* RGIDR_MODID[571]:ARSD00*/ + /* After setting */ /* RGIDR_MODID[572]:ARSD01*/ + /* After setting */ /* RGIDR_MODID[573]:ARSD02*/ + [541] = {0xE775200CU, 0x0000000FU}, /* RGIDR_MODID[574]:ARSD03*/ + [542] = {0xE7752010U, 0x0000000FU}, /* RGIDR_MODID[575]:ARSD04*/ + [543] = {0xE7752014U, 0x0000000FU}, /* RGIDR_MODID[576]:ARSD05*/ + [544] = {0xE7752018U, 0x0000000FU}, /* RGIDR_MODID[577]:ARSD06*/ + [545] = {0xE775201CU, 0x0000004AU}, /* RGIDR_MODID[578]:AXIFRAY*/ + [546] = {0xE7752028U, 0x0000004FU}, /* RGIDR_MODID[579]:AXIRPC*/ + [547] = {0xE775202CU, 0x0000000FU}, /* RGIDR_MODID[580]:AXISDHI0*/ + [548] = {0xE7752030U, 0x0000000FU}, /* RGIDR_MODID[581]:ARSD07*/ + [549] = {0xE7752034U, 0x00000000U}, /* RGIDR_MODID[582]:ARSD08*/ + [550] = {0xE7752038U, 0x0000000FU}, /* RGIDR_MODID[583]:ARSP00*/ + /* After setting */ /* RGIDR_MODID[584]:ARSP01*/ + /* After setting */ /* RGIDR_MODID[585]:ARSP02*/ + [551] = {0xE7752044U, 0x0000000FU}, /* RGIDR_MODID[586]:ARSP03*/ + [552] = {0xE7752048U, 0x0000000FU}, /* RGIDR_MODID[587]:ARSP04*/ + [553] = {0xE775204CU, 0x0000000FU}, /* RGIDR_MODID[588]:ARSP05*/ + [554] = {0xE7752050U, 0x0000000FU}, /* RGIDR_MODID[589]:ARSP06*/ + [555] = {0xE7752054U, 0x00000007U}, /* RGIDR_MODID[590]:ARSP07*/ + [556] = {0xE7752058U, 0x00000000U}, /* RGIDR_MODID[591]:ARSP08*/ + [557] = {0xE775205CU, 0x0000004EU}, /* RGIDR_MODID[592]:IPMMUDS001*/ + [558] = {0xE7752060U, 0x0000000AU}, /* RGIDR_MODID[593]:CKMPER0*/ + [559] = {0xE7752064U, 0x0000000FU}, /* RGIDR_MODID[594]:ECMPER0*/ + [560] = {0xE7752068U, 0x0000000EU}, /* RGIDR_MODID[595]:FBAPER0*/ + [561] = {0xE775206CU, 0x0000004EU}, /* RGIDR_MODID[596]:FSO0*/ + [562] = {0xE7752070U, 0x0000004EU}, /* RGIDR_MODID[597]:FSO1*/ + [563] = {0xE7752074U, 0x0000004EU}, /* RGIDR_MODID[598]:FSO10*/ + [564] = {0xE7752078U, 0x0000004EU}, /* RGIDR_MODID[599]:FSO2*/ + [565] = {0xE775207CU, 0x0000004EU}, /* RGIDR_MODID[600]:FSO3*/ + [566] = {0xE7752080U, 0x0000004EU}, /* RGIDR_MODID[601]:FSO4*/ + [567] = {0xE7752084U, 0x0000004EU}, /* RGIDR_MODID[602]:FSO5*/ + [568] = {0xE7752088U, 0x0000004EU}, /* RGIDR_MODID[603]:FSO6*/ + [569] = {0xE775208CU, 0x0000004EU}, /* RGIDR_MODID[604]:FSO7*/ + [570] = {0xE7752090U, 0x0000004EU}, /* RGIDR_MODID[605]:FSO8*/ + [571] = {0xE7752094U, 0x0000004EU}, /* RGIDR_MODID[606]:FSO9*/ + [572] = {0xE7752098U, 0x0000002CU}, /* RGIDR_MODID[607]:ADG*/ + [573] = {0xE775209CU, 0x0000000FU}, /* RGIDR_MODID[608]:ECMSD0*/ + [574] = {0xE77520A0U, 0x0000004EU}, /* RGIDR_MODID[609]:IPMMUDS010*/ + [575] = {0xE77520A4U, 0x0000004EU}, /* RGIDR_MODID[610]:IPMMUDS011*/ + [576] = {0xE77520A8U, 0x0000004EU}, /* RGIDR_MODID[611]:I2C0*/ + [577] = {0xE77520ACU, 0x0000004EU}, /* RGIDR_MODID[612]:I2C1*/ + [578] = {0xE77520B0U, 0x0000004EU}, /* RGIDR_MODID[613]:I2C2*/ + [579] = {0xE77520B4U, 0x0000004EU}, /* RGIDR_MODID[614]:I2C3*/ + [580] = {0xE77520C0U, 0x0000004EU}, /* RGIDR_MODID[615]:IPMMUDS012*/ + [581] = {0xE77520C8U, 0x0000004EU}, /* RGIDR_MODID[616]:IPMMUDS000*/ + [582] = {0xE77520CCU, 0x0000004EU}, /* RGIDR_MODID[617]:IPMMUDS013*/ + [583] = {0xE77520D0U, 0x0000004EU}, /* RGIDR_MODID[618]:IPMMUDS014*/ + [584] = {0xE77520D4U, 0x0000004EU}, /* RGIDR_MODID[619]:IPMMUDS015*/ + [585] = {0xE77520D8U, 0x0000004EU}, /* RGIDR_MODID[620]:IPMMUDS002*/ + [586] = {0xE77520DCU, 0x0000004EU}, /* RGIDR_MODID[621]:IPMMUDS003*/ + [587] = {0xE77520E0U, 0x0000004EU}, /* RGIDR_MODID[622]:IPMMUDS004*/ + [588] = {0xE77520E4U, 0x0000004EU}, /* RGIDR_MODID[623]:IPMMUDS005*/ + [589] = {0xE77520E8U, 0x0000002CU}, /* RGIDR_MODID[624]:SSI*/ + [590] = {0xE77520ECU, 0x0000004EU}, /* RGIDR_MODID[625]:IPMMUDS006*/ + [591] = {0xE77520F0U, 0x0000004EU}, /* RGIDR_MODID[626]:IPMMUDS007*/ + [592] = {0xE77520F4U, 0x0000000CU}, /* RGIDR_MODID[627]:SYDM1P*/ + [593] = {0xE77520F8U, 0x0000004EU}, /* RGIDR_MODID[628]:IPMMUDS008*/ + [594] = {0xE77520FCU, 0x0000000CU}, /* RGIDR_MODID[629]:SYDM2P*/ + [595] = {0xE7752100U, 0x0000004EU}, /* RGIDR_MODID[630]:IPMMUDS009*/ + [596] = {0xE7752240U, 0x0000000CU}, /* RGIDR_MODID[631]:SYDM100*/ + [597] = {0xE7752244U, 0x0000000CU}, /* RGIDR_MODID[632]:SYDM101*/ + [598] = {0xE7752248U, 0x0000000CU}, /* RGIDR_MODID[633]:SYDM110*/ + [599] = {0xE775224CU, 0x0000000CU}, /* RGIDR_MODID[634]:SYDM111*/ + [600] = {0xE7752250U, 0x0000000CU}, /* RGIDR_MODID[635]:SYDM112*/ + [601] = {0xE7752254U, 0x0000000CU}, /* RGIDR_MODID[636]:SYDM113*/ + [602] = {0xE7752258U, 0x0000000CU}, /* RGIDR_MODID[637]:SYDM114*/ + [603] = {0xE775225CU, 0x0000000CU}, /* RGIDR_MODID[638]:SYDM115*/ + [604] = {0xE7752260U, 0x0000000CU}, /* RGIDR_MODID[639]:SYDM102*/ + [605] = {0xE7752264U, 0x0000000CU}, /* RGIDR_MODID[640]:SYDM103*/ + [606] = {0xE7752268U, 0x0000000CU}, /* RGIDR_MODID[641]:SYDM104*/ + [607] = {0xE775226CU, 0x0000000CU}, /* RGIDR_MODID[642]:SYDM105*/ + [608] = {0xE7752270U, 0x0000000CU}, /* RGIDR_MODID[643]:SYDM106*/ + [609] = {0xE7752274U, 0x0000000CU}, /* RGIDR_MODID[644]:SYDM107*/ + [610] = {0xE7752278U, 0x0000000CU}, /* RGIDR_MODID[645]:SYDM108*/ + [611] = {0xE775227CU, 0x0000000CU}, /* RGIDR_MODID[646]:SYDM109*/ + [612] = {0xE7752280U, 0x0000000CU}, /* RGIDR_MODID[647]:SYDM200*/ + [613] = {0xE7752284U, 0x0000000CU}, /* RGIDR_MODID[648]:SYDM201*/ + [614] = {0xE7752288U, 0x0000000CU}, /* RGIDR_MODID[649]:SYDM210*/ + [615] = {0xE775228CU, 0x0000000CU}, /* RGIDR_MODID[650]:SYDM211*/ + [616] = {0xE7752290U, 0x0000000CU}, /* RGIDR_MODID[651]:SYDM212*/ + [617] = {0xE7752294U, 0x0000000CU}, /* RGIDR_MODID[652]:SYDM213*/ + [618] = {0xE7752298U, 0x0000000CU}, /* RGIDR_MODID[653]:SYDM214*/ + [619] = {0xE775229CU, 0x0000000CU}, /* RGIDR_MODID[654]:SYDM215*/ + [620] = {0xE77522A0U, 0x0000000CU}, /* RGIDR_MODID[655]:SYDM202*/ + [621] = {0xE77522A4U, 0x0000000CU}, /* RGIDR_MODID[656]:SYDM203*/ + [622] = {0xE77522A8U, 0x0000000CU}, /* RGIDR_MODID[657]:SYDM204*/ + [623] = {0xE77522ACU, 0x0000000CU}, /* RGIDR_MODID[658]:SYDM205*/ + [624] = {0xE77522B0U, 0x0000000CU}, /* RGIDR_MODID[659]:SYDM206*/ + [625] = {0xE77522B4U, 0x0000000CU}, /* RGIDR_MODID[660]:SYDM207*/ + [626] = {0xE77522B8U, 0x0000000CU}, /* RGIDR_MODID[661]:SYDM208*/ + [627] = {0xE77522BCU, 0x0000000CU}, /* RGIDR_MODID[662]:SYDM209*/ + [628] = {0xFE682000U, 0x0000000FU}, /* RGIDR_MODID[663]:ARVC0*/ + /* After setting */ /* RGIDR_MODID[664]:ARVC1*/ + /* After setting */ /* RGIDR_MODID[665]:ARVC2*/ + [629] = {0xFE68200CU, 0x0000000FU}, /* RGIDR_MODID[666]:ARVC3*/ + [630] = {0xFE682010U, 0x0000000EU}, /* RGIDR_MODID[667]:AXIFBABUSVC*/ + [631] = {0xFE682014U, 0x0000000FU}, /* RGIDR_MODID[668]:ARVC4*/ + [632] = {0xFE682018U, 0x0000000FU}, /* RGIDR_MODID[669]:ARVC5*/ + [633] = {0xFE68201CU, 0x0000000FU}, /* RGIDR_MODID[670]:ARVC6*/ + [634] = {0xFE682020U, 0x0000000FU}, /* RGIDR_MODID[671]:ARVC7*/ + [635] = {0xFE682024U, 0x00000000U}, /* RGIDR_MODID[672]:ARVC8*/ + [636] = {0xFE68202CU, 0x0000000FU}, /* RGIDR_MODID[673]:ECMVC0*/ + [637] = {0xFE682034U, 0x0000004EU}, /* RGIDR_MODID[674]:IMR0*/ + [638] = {0xFE682038U, 0x0000004EU}, /* RGIDR_MODID[675]:IMR1*/ + [639] = {0xFE68203CU, 0x0000004EU}, /* RGIDR_MODID[676]:IPMMUVC01*/ + [640] = {0xFE682040U, 0x0000004EU}, /* RGIDR_MODID[677]:IPMMUVC10*/ + [641] = {0xFE682044U, 0x0000000CU}, /* RGIDR_MODID[678]:IMS0*/ + [642] = {0xFE682048U, 0x0000000CU}, /* RGIDR_MODID[679]:IMS1*/ + [643] = {0xFE68204CU, 0x0000004EU}, /* RGIDR_MODID[680]:IPMMUVC00*/ + [644] = {0xFE682050U, 0x0000004EU}, /* RGIDR_MODID[681]:IPMMUVC11*/ + [645] = {0xFE682054U, 0x0000004EU}, /* RGIDR_MODID[682]:IPMMUVC12*/ + [646] = {0xFE682058U, 0x0000004EU}, /* RGIDR_MODID[683]:IPMMUVC13*/ + [647] = {0xFE68205CU, 0x0000004EU}, /* RGIDR_MODID[684]:IPMMUVC14*/ + [648] = {0xFE682060U, 0x0000004EU}, /* RGIDR_MODID[685]:IPMMUVC15*/ + [649] = {0xFE682064U, 0x0000004EU}, /* RGIDR_MODID[686]:IPMMUVC02*/ + [650] = {0xFE682068U, 0x0000004EU}, /* RGIDR_MODID[687]:IPMMUVC03*/ + [651] = {0xFE68206CU, 0x0000004EU}, /* RGIDR_MODID[688]:IPMMUVC04*/ + [652] = {0xFE682070U, 0x0000004EU}, /* RGIDR_MODID[689]:IPMMUVC05*/ + [653] = {0xFE682074U, 0x0000004EU}, /* RGIDR_MODID[690]:IPMMUVC06*/ + [654] = {0xFE682078U, 0x0000004EU}, /* RGIDR_MODID[691]:IPMMUVC07*/ + [655] = {0xFE68207CU, 0x0000004EU}, /* RGIDR_MODID[692]:IPMMUVC08*/ + [656] = {0xFE682080U, 0x0000004EU}, /* RGIDR_MODID[693]:IPMMUVC09*/ + [657] = {0xFE682084U, 0x00000028U}, /* RGIDR_MODID[694]:IV1ES*/ + [658] = {0xFEBE2000U, 0x0000004EU}, /* RGIDR_MODID[695]:CSITOP0*/ + [659] = {0xFEBE2004U, 0x0000000FU}, /* RGIDR_MODID[696]:ARVI10*/ + /* After setting */ /* RGIDR_MODID[697]:ARVI11*/ + /* After setting */ /* RGIDR_MODID[698]:ARVI12*/ + [660] = {0xFEBE2010U, 0x0000000FU}, /* RGIDR_MODID[699]:ARVI13*/ + [661] = {0xFEBE2014U, 0x0000000FU}, /* RGIDR_MODID[700]:ARVI14*/ + [662] = {0xFEBE2018U, 0x0000000FU}, /* RGIDR_MODID[701]:ARVI15*/ + [663] = {0xFEBE201CU, 0x0000000FU}, /* RGIDR_MODID[702]:ARVI16*/ + [664] = {0xFEBE2020U, 0x0000000FU}, /* RGIDR_MODID[703]:ARVI17*/ + [665] = {0xFEBE2024U, 0x00000000U}, /* RGIDR_MODID[704]:ARVI18*/ + [666] = {0xFEBE202CU, 0x0000004EU}, /* RGIDR_MODID[705]:CSITOP1*/ + [667] = {0xFEBE2034U, 0x0000004EU}, /* RGIDR_MODID[706]:DSITLINK0*/ + [668] = {0xFEBE203CU, 0x0000000FU}, /* RGIDR_MODID[707]:ECMVIO1*/ + [669] = {0xFEBE2044U, 0x0000004EU}, /* RGIDR_MODID[708]:IPMMUVI001*/ + [670] = {0xFEBE2048U, 0x0000000CU}, /* RGIDR_MODID[709]:FCPVX0*/ + [671] = {0xFEBE2058U, 0x0000004EU}, /* RGIDR_MODID[710]:IPMMUVI000*/ + [672] = {0xFEBE205CU, 0x0000004EU}, /* RGIDR_MODID[711]:IPMMUVI100*/ + [673] = {0xFEBE2060U, 0x0000004EU}, /* RGIDR_MODID[712]:IPMMUVI010*/ + [674] = {0xFEBE2064U, 0x0000004EU}, /* RGIDR_MODID[713]:IPMMUVI011*/ + [675] = {0xFEBE2068U, 0x0000004EU}, /* RGIDR_MODID[714]:VSPX0*/ + [676] = {0xFEBE2078U, 0x0000004EU}, /* RGIDR_MODID[715]:IPMMUVI012*/ + [677] = {0xFEBE207CU, 0x0000004EU}, /* RGIDR_MODID[716]:IPMMUVI013*/ + [678] = {0xFEBE2080U, 0x0000004EU}, /* RGIDR_MODID[717]:IPMMUVI014*/ + [679] = {0xFEBE2084U, 0x0000004EU}, /* RGIDR_MODID[718]:IPMMUVI015*/ + [680] = {0xFEBE2088U, 0x0000004EU}, /* RGIDR_MODID[719]:IPMMUVI002*/ + [681] = {0xFEBE208CU, 0x0000004EU}, /* RGIDR_MODID[720]:IPMMUVI003*/ + [682] = {0xFEBE2090U, 0x0000004EU}, /* RGIDR_MODID[721]:IPMMUVI004*/ + [683] = {0xFEBE2094U, 0x0000004EU}, /* RGIDR_MODID[722]:IPMMUVI005*/ + [684] = {0xFEBE2098U, 0x0000004EU}, /* RGIDR_MODID[723]:IPMMUVI006*/ + [685] = {0xFEBE209CU, 0x0000004EU}, /* RGIDR_MODID[724]:IPMMUVI007*/ + [686] = {0xFEBE20A0U, 0x0000004EU}, /* RGIDR_MODID[725]:IPMMUVI008*/ + [687] = {0xFEBE20A4U, 0x0000004EU}, /* RGIDR_MODID[726]:IPMMUVI009*/ + [688] = {0xFEBE20A8U, 0x0000004EU}, /* RGIDR_MODID[727]:IPMMUVI101*/ + [689] = {0xFEBE20ACU, 0x0000004EU}, /* RGIDR_MODID[728]:IPMMUVI110*/ + [690] = {0xFEBE20B0U, 0x0000004EU}, /* RGIDR_MODID[729]:IPMMUVI111*/ + [691] = {0xFEBE20B4U, 0x0000004EU}, /* RGIDR_MODID[730]:IPMMUVI112*/ + [692] = {0xFEBE20B8U, 0x0000004EU}, /* RGIDR_MODID[731]:IPMMUVI113*/ + [693] = {0xFEBE20BCU, 0x0000004EU}, /* RGIDR_MODID[732]:IPMMUVI114*/ + [694] = {0xFEBE20C0U, 0x0000004EU}, /* RGIDR_MODID[733]:IPMMUVI115*/ + [695] = {0xFEBE20C4U, 0x0000004EU}, /* RGIDR_MODID[734]:IPMMUVI102*/ + [696] = {0xFEBE20C8U, 0x0000004EU}, /* RGIDR_MODID[735]:IPMMUVI103*/ + [697] = {0xFEBE20CCU, 0x0000004EU}, /* RGIDR_MODID[736]:IPMMUVI104*/ + [698] = {0xFEBE20D0U, 0x0000004EU}, /* RGIDR_MODID[737]:IPMMUVI105*/ + [699] = {0xFEBE20D4U, 0x0000004EU}, /* RGIDR_MODID[738]:IPMMUVI106*/ + [700] = {0xFEBE20D8U, 0x0000004EU}, /* RGIDR_MODID[739]:IPMMUVI107*/ + [701] = {0xFEBE20DCU, 0x0000004EU}, /* RGIDR_MODID[740]:IPMMUVI108*/ + [702] = {0xFEBE20E0U, 0x0000004EU}, /* RGIDR_MODID[741]:IPMMUVI109*/ + [703] = {0xFEBE2104U, 0x0000000EU}, /* RGIDR_MODID[742]:AXIFBABUSVIO*/ + [704] = {0xFEBF2000U, 0x0000000FU}, /* RGIDR_MODID[743]:ARVI0*/ + /* After setting */ /* RGIDR_MODID[744]:ARVI1*/ + /* After setting */ /* RGIDR_MODID[745]:ARVI2*/ + [705] = {0xFEBF200CU, 0x0000000FU}, /* RGIDR_MODID[746]:ARVI3*/ + [706] = {0xFEBF2010U, 0x0000000FU}, /* RGIDR_MODID[747]:ARVI4*/ + [707] = {0xFEBF2014U, 0x0000000FU}, /* RGIDR_MODID[748]:ARVI5*/ + [708] = {0xFEBF2018U, 0x0000000FU}, /* RGIDR_MODID[749]:ARVI6*/ + [709] = {0xFEBF201CU, 0x0000000FU}, /* RGIDR_MODID[750]:ARVI7*/ + [710] = {0xFEBF2020U, 0x00000000U}, /* RGIDR_MODID[751]:ARVI8*/ + [711] = {0xFEBF2024U, 0x0000000FU}, /* RGIDR_MODID[752]:ECMVIO0*/ + [712] = {0xFEBF2028U, 0x0000004EU}, /* RGIDR_MODID[753]:ISP0*/ + [713] = {0xFEBF202CU, 0x0000004EU}, /* RGIDR_MODID[754]:ISP0CORE*/ + [714] = {0xFEBF2030U, 0x0000004EU}, /* RGIDR_MODID[755]:ISP1*/ + [715] = {0xFEBF2054U, 0x0000004EU}, /* RGIDR_MODID[756]:VIN00*/ + [716] = {0xFEBF2058U, 0x0000004EU}, /* RGIDR_MODID[757]:VIN01*/ + [717] = {0xFEBF205CU, 0x0000004EU}, /* RGIDR_MODID[758]:VIN02*/ + [718] = {0xFEBF2060U, 0x0000004EU}, /* RGIDR_MODID[759]:VIN03*/ + [719] = {0xFEBF2064U, 0x0000004EU}, /* RGIDR_MODID[760]:VIN04*/ + [720] = {0xFEBF2068U, 0x0000004EU}, /* RGIDR_MODID[761]:VIN05*/ + [721] = {0xFEBF206CU, 0x0000004EU}, /* RGIDR_MODID[762]:VIN06*/ + [722] = {0xFEBF2070U, 0x0000004EU}, /* RGIDR_MODID[763]:VIN07*/ + [723] = {0xFEBF2074U, 0x0000004EU}, /* RGIDR_MODID[764]:VIN10*/ + [724] = {0xFEBF2078U, 0x0000004EU}, /* RGIDR_MODID[765]:VIN11*/ + [725] = {0xFEBF207CU, 0x0000004EU}, /* RGIDR_MODID[766]:VIN12*/ + [726] = {0xFEBF2080U, 0x0000004EU}, /* RGIDR_MODID[767]:VIN13*/ + [727] = {0xFEBF2084U, 0x0000004EU}, /* RGIDR_MODID[768]:VIN14*/ + [728] = {0xFEBF2088U, 0x0000004EU}, /* RGIDR_MODID[769]:VIN15*/ + [729] = {0xFEBF208CU, 0x0000004EU}, /* RGIDR_MODID[770]:VIN16*/ + [730] = {0xFEBF2090U, 0x0000004EU}, /* RGIDR_MODID[771]:VIN17*/ + [731] = {0xE7B12000U, 0x0000000FU}, /* RGIDR_MODID[772]:ARVIP00*/ + /* After setting */ /* RGIDR_MODID[773]:ARVIP01*/ + /* After setting */ /* RGIDR_MODID[774]:ARVIP02*/ + [732] = {0xE7B1200CU, 0x0000000FU}, /* RGIDR_MODID[775]:ARVIP03*/ + [733] = {0xE7B12010U, 0x0000000EU}, /* RGIDR_MODID[776]:AXIFBABUSVIP0*/ + [734] = {0xE7B12014U, 0x0000000FU}, /* RGIDR_MODID[777]:ARVIP04*/ + [735] = {0xE7B12018U, 0x0000000FU}, /* RGIDR_MODID[778]:ARVIP05*/ + [736] = {0xE7B1201CU, 0x0000000FU}, /* RGIDR_MODID[779]:ARVIP06*/ + [737] = {0xE7B12020U, 0x00000007U}, /* RGIDR_MODID[780]:ARVIP07*/ + [738] = {0xE7B12024U, 0x00000000U}, /* RGIDR_MODID[781]:ARVIP08*/ + [739] = {0xE7B1202CU, 0x0000000FU}, /* RGIDR_MODID[782]:ECMVIP0*/ + [740] = {0xE7B12030U, 0x0000004EU}, /* RGIDR_MODID[783]:IPMMUVIP000*/ + [741] = {0xE7B12038U, 0x0000004EU}, /* RGIDR_MODID[784]:SMPO0*/ + [742] = {0xE7B1203CU, 0x0000004EU}, /* RGIDR_MODID[785]:SMPS0*/ + [743] = {0xE7B12040U, 0x0000004EU}, /* RGIDR_MODID[786]:UMFL0*/ + [744] = {0xE7B12044U, 0x0000004EU}, /* RGIDR_MODID[787]:IPMMUVIP001*/ + [745] = {0xE7B12048U, 0x0000004EU}, /* RGIDR_MODID[788]:IPMMUVIP010*/ + [746] = {0xE7B1204CU, 0x0000004EU}, /* RGIDR_MODID[789]:IPMMUVIP011*/ + [747] = {0xE7B12050U, 0x0000004EU}, /* RGIDR_MODID[790]:UMFL0M_W*/ + [748] = {0xE7B12054U, 0x0000004EU}, /* RGIDR_MODID[791]:IPMMUVIP012*/ + [749] = {0xE7B12058U, 0x0000004EU}, /* RGIDR_MODID[792]:IPMMUVIP013*/ + [750] = {0xE7B1205CU, 0x0000004EU}, /* RGIDR_MODID[793]:IPMMUVIP014*/ + [751] = {0xE7B12060U, 0x0000004EU}, /* RGIDR_MODID[794]:IPMMUVIP015*/ + [752] = {0xE7B12064U, 0x0000004EU}, /* RGIDR_MODID[795]:IPMMUVIP002*/ + [753] = {0xE7B12068U, 0x0000004EU}, /* RGIDR_MODID[796]:IPMMUVIP003*/ + [754] = {0xE7B1206CU, 0x0000004EU}, /* RGIDR_MODID[797]:IPMMUVIP004*/ + [755] = {0xE7B12070U, 0x0000004EU}, /* RGIDR_MODID[798]:IPMMUVIP005*/ + [756] = {0xE7B12074U, 0x0000004EU}, /* RGIDR_MODID[799]:IPMMUVIP006*/ + [757] = {0xE7B12078U, 0x0000004EU}, /* RGIDR_MODID[800]:IPMMUVIP007*/ + [758] = {0xE7B1207CU, 0x0000004EU}, /* RGIDR_MODID[801]:IPMMUVIP008*/ + [759] = {0xE7B12080U, 0x0000004EU}, /* RGIDR_MODID[802]:IPMMUVIP009*/ + [760] = {0xFF8820A0U, 0x0000000FU}, /* RGIDR_MODID[803]:ARDSP0*/ + /* After setting */ /* RGIDR_MODID[804]:ARDSP1*/ + /* After setting */ /* RGIDR_MODID[805]:ARDSP2*/ + [761] = {0xFF8820ACU, 0x0000000FU}, /* RGIDR_MODID[806]:ARDSP3*/ + [762] = {0xFF8820B0U, 0x0000000FU}, /* RGIDR_MODID[807]:ARDSP4*/ + [763] = {0xFF8820B4U, 0x0000000FU}, /* RGIDR_MODID[808]:ARDSP5*/ + [764] = {0xFF8820B8U, 0x0000000FU}, /* RGIDR_MODID[809]:ARDSP6*/ + [765] = {0xFF8820BCU, 0x0000000FU}, /* RGIDR_MODID[810]:ARDSP7*/ + [766] = {0xFF8820C0U, 0x0000000FU}, /* RGIDR_MODID[811]:ECMDSP*/ + [767] = {0xFF882090U, 0x0000000CU}, /* RGIDR_MODID[812]:AXIDSP0*/ + [768] = {0xFF882094U, 0x0000000CU}, /* RGIDR_MODID[813]:AXIDSP1*/ + [769] = {0xFF882098U, 0x0000000CU}, /* RGIDR_MODID[814]:AXIDSP2*/ + [770] = {0xFF88209CU, 0x0000000CU}, /* RGIDR_MODID[815]:AXIDSP3*/ + [771] = {0xFF8820C4U, 0x0000004EU}, /* RGIDR_MODID[816]:IMPM0100*/ + [772] = {0xFF8820C8U, 0x0000004EU}, /* RGIDR_MODID[817]:IMPM0101*/ + [773] = {0xFF8820CCU, 0x0000004EU}, /* RGIDR_MODID[818]:IMPM0102*/ + [774] = {0xFF8820D0U, 0x0000004EU}, /* RGIDR_MODID[819]:IMPM0103*/ + [775] = {0xFF8820D4U, 0x0000004EU}, /* RGIDR_MODID[820]:IMPM0104*/ + [776] = {0xFF8820D8U, 0x0000004EU}, /* RGIDR_MODID[821]:IMPM0105*/ + [777] = {0xFF8820DCU, 0x0000004EU}, /* RGIDR_MODID[822]:IMPM0106*/ + [778] = {0xFF8820E0U, 0x0000004EU}, /* RGIDR_MODID[823]:IMPM0107*/ + [779] = {0xFF8820E4U, 0x0000004EU}, /* RGIDR_MODID[824]:IMPM0200*/ + [780] = {0xFF8820E8U, 0x0000004EU}, /* RGIDR_MODID[825]:IMPM0201*/ + [781] = {0xFF8820ECU, 0x0000004EU}, /* RGIDR_MODID[826]:IMPS0000*/ + [782] = {0xFF8820F0U, 0x0000004EU}, /* RGIDR_MODID[827]:IMPS0001*/ + [783] = {0xFF8820F4U, 0x0000004EU}, /* RGIDR_MODID[828]:IMPS0002*/ + [784] = {0xFF8820F8U, 0x0000004EU}, /* RGIDR_MODID[829]:IMPS0003*/ + [785] = {0xFF8820FCU, 0x0000004EU}, /* RGIDR_MODID[830]:IMPS0100*/ + [786] = {0xFF882100U, 0x0000004EU}, /* RGIDR_MODID[831]:IMPS0101*/ + [787] = {0xFF882104U, 0x0000004EU}, /* RGIDR_MODID[832]:IMPS0102*/ + [788] = {0xFF882108U, 0x0000004EU}, /* RGIDR_MODID[833]:IMPS0103*/ + [789] = {0xFF88210CU, 0x0000004EU}, /* RGIDR_MODID[834]:IMPS0104*/ + [790] = {0xFF882110U, 0x0000004EU}, /* RGIDR_MODID[835]:IMPS0105*/ + [791] = {0xFF882114U, 0x0000004EU}, /* RGIDR_MODID[836]:IMPS0106*/ + [792] = {0xFF882118U, 0x0000004EU}, /* RGIDR_MODID[837]:IMPS0107*/ + [793] = {0xFF88211CU, 0x0000004EU}, /* RGIDR_MODID[838]:IMPS0108*/ + [794] = {0xFF882120U, 0x0000004EU}, /* RGIDR_MODID[839]:IMPS0109*/ + [795] = {0xFF882124U, 0x0000004EU}, /* RGIDR_MODID[840]:IMPS0110*/ + [796] = {0xFF882128U, 0x0000004EU}, /* RGIDR_MODID[841]:IMPS0111*/ + [797] = {0xFF88212CU, 0x0000004EU}, /* RGIDR_MODID[842]:IMPS0200*/ + [798] = {0xFF882130U, 0x0000004EU}, /* RGIDR_MODID[843]:IMPS0201*/ + [799] = {0xFF882134U, 0x0000004EU}, /* RGIDR_MODID[844]:IMPS0202*/ + [801] = {0xE67B9660U, 0x0000000FU}, /* RGIDR_MODID[845]:ARCC*/ + [800] = {0xE67B9674U, 0x0000000FU}, /* RGIDR_MODID[846]:ARRTRAM*/ + [802] = {0xE7752024U, 0x00000000U}, /* RGIDR_MODID[847]:RSV0*/ + [803] = {0xE7B1210CU, 0x00000004U}, /* RGIDR_MODID[848]:PAP*/ + [804] = {0xFEBD2028U, 0x0000000CU}, /* RGIDR_MODID[849]:DOC*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_w_tbl" +#else +__attribute__ ((section(".rgid_w_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_write_tbl[] = { + [0] = {0xFFC82400U, 0x0000000EU}, /* RGIDW_MODID[0]:ARMGC0*/ + [1] = {0xFFC82404U, 0x0000000EU}, /* RGIDW_MODID[1]:ARMGC1*/ + [2] = {0xFFC82408U, 0x00000000U}, /* RGIDW_MODID[2]:ARMGC2*/ + [3] = {0xFFC8240CU, 0x00000002U}, /* RGIDW_MODID[3]:ARRT00*/ + /* After setting */ /* RGIDW_MODID[4]:ARRT01*/ + /* After setting */ /* RGIDW_MODID[5]:ARRT02*/ + [4] = {0xFFC82418U, 0x00000001U}, /* RGIDW_MODID[6]:ARRT03*/ + [5] = {0xFFC8241CU, 0x00000002U}, /* RGIDW_MODID[7]:ARRT04*/ + [6] = {0xFFC82420U, 0x00000001U}, /* RGIDW_MODID[8]:ARRT05*/ + [7] = {0xFFC82424U, 0x00000002U}, /* RGIDW_MODID[9]:ARRT06*/ + [8] = {0xFFC82428U, 0x00000002U}, /* RGIDW_MODID[10]:ARRT07*/ + [9] = {0xFFC8242CU, 0x00000000U}, /* RGIDW_MODID[11]:ARRT08*/ + [10] = {0xFFC82430U, 0x00000001U}, /* RGIDW_MODID[12]:LIFEC0*/ + [11] = {0xFFC82434U, 0x0000000EU}, /* RGIDW_MODID[13]:SWDT*/ + [12] = {0xFFC82438U, 0x0000006EU}, /* RGIDW_MODID[14]:TMU0*/ + [13] = {0xFFC8243CU, 0x0000000EU}, /* RGIDW_MODID[15]:WDT*/ + [14] = {0xFFC82440U, 0x0000000EU}, /* RGIDW_MODID[16]:WWDT0*/ + [15] = {0xFFC82444U, 0x0000000EU}, /* RGIDW_MODID[17]:WWDT1*/ + [16] = {0xFFC82448U, 0x0000000EU}, /* RGIDW_MODID[18]:WWDT2*/ + [17] = {0xFFC8244CU, 0x0000000EU}, /* RGIDW_MODID[19]:WWDT3*/ + [18] = {0xFFC82450U, 0x0000000EU}, /* RGIDW_MODID[20]:WWDT4*/ + [19] = {0xFFC82454U, 0x0000000EU}, /* RGIDW_MODID[21]:WWDT5*/ + [20] = {0xFFC82458U, 0x0000000EU}, /* RGIDW_MODID[22]:WWDT6*/ + [21] = {0xFFC82468U, 0x0000000AU}, /* RGIDW_MODID[23]:ECMRT3*/ + [22] = {0xE6002404U, 0x0000000FU}, /* RGIDW_MODID[24]:APMU0*/ + [23] = {0xE6002408U, 0x00000002U}, /* RGIDW_MODID[25]:APMU1*/ + [24] = {0xE600240CU, 0x00000000U}, /* RGIDW_MODID[26]:APMU10*/ + [25] = {0xE6002410U, 0x00000000U}, /* RGIDW_MODID[27]:APMU11*/ + [26] = {0xE6002414U, 0x00000000U}, /* RGIDW_MODID[28]:APMU12*/ + [27] = {0xE6002418U, 0x00000000U}, /* RGIDW_MODID[29]:APMU13*/ + [28] = {0xE600241CU, 0x00000000U}, /* RGIDW_MODID[30]:APMU14*/ + [29] = {0xE6002420U, 0x00000000U}, /* RGIDW_MODID[31]:APMU15*/ + [30] = {0xE6002424U, 0x00000004U}, /* RGIDW_MODID[32]:APMU2*/ + [31] = {0xE6002428U, 0x00000004U}, /* RGIDW_MODID[33]:APMU3*/ + [32] = {0xE600242CU, 0x00000000U}, /* RGIDW_MODID[34]:APMU4*/ + [33] = {0xE6002430U, 0x00000000U}, /* RGIDW_MODID[35]:APMU5*/ + [34] = {0xE6002434U, 0x00000000U}, /* RGIDW_MODID[36]:APMU6*/ + [35] = {0xE6002438U, 0x00000000U}, /* RGIDW_MODID[37]:APMU7*/ + [36] = {0xE600243CU, 0x00000000U}, /* RGIDW_MODID[38]:APMU8*/ + [37] = {0xE6002440U, 0x00000000U}, /* RGIDW_MODID[39]:APMU9*/ + [38] = {0xE6002444U, 0x00000002U}, /* RGIDW_MODID[40]:ARS00*/ + /* After setting */ /* RGIDW_MODID[41]:ARS01*/ + /* After setting */ /* RGIDW_MODID[42]:ARS02*/ + [39] = {0xE6002450U, 0x00000001U}, /* RGIDW_MODID[43]:ARS03*/ + [40] = {0xE6002454U, 0x00000002U}, /* RGIDW_MODID[44]:ARS04*/ + [41] = {0xE6002458U, 0x00000001U}, /* RGIDW_MODID[45]:ARS05*/ + [42] = {0xE600245CU, 0x00000002U}, /* RGIDW_MODID[46]:ARS06*/ + [43] = {0xE6002460U, 0x00000002U}, /* RGIDW_MODID[47]:ARS07*/ + [44] = {0xE6002464U, 0x00000000U}, /* RGIDW_MODID[48]:ARS08*/ + [45] = {0xE6002468U, 0x0000000EU}, /* RGIDW_MODID[49]:CMT0*/ + [46] = {0xE600246CU, 0x0000000EU}, /* RGIDW_MODID[50]:CMT1*/ + [47] = {0xE6002470U, 0x0000000EU}, /* RGIDW_MODID[51]:CMT2*/ + [48] = {0xE6002474U, 0x0000000EU}, /* RGIDW_MODID[52]:CMT3*/ + [49] = {0xE6002478U, 0x0000000AU}, /* RGIDW_MODID[53]:CKM*/ + [50] = {0xE600247CU, 0x0000000EU}, /* RGIDW_MODID[54]:DBE*/ + [51] = {0xE6002480U, 0x0000000EU}, /* RGIDW_MODID[55]:IRQC*/ + [52] = {0xE6002484U, 0x0000000AU}, /* RGIDW_MODID[56]:ECMPS0*/ + [53] = {0xE6002488U, 0x0000000BU}, /* RGIDW_MODID[57]:OTP0*/ + [54] = {0xE600248CU, 0x0000000FU}, /* RGIDW_MODID[58]:OTP1*/ + [55] = {0xE600249CU, 0x0000000EU}, /* RGIDW_MODID[59]:SCMT*/ + [56] = {0xE60024A8U, 0x0000004AU}, /* RGIDW_MODID[60]:TSC1*/ + [57] = {0xE60024ACU, 0x0000004AU}, /* RGIDW_MODID[61]:TSC2*/ + [58] = {0xE60024B8U, 0x00000006U}, /* RGIDW_MODID[62]:UCMT*/ + [59] = {0xE6002500U, 0x0000006FU}, /* RGIDW_MODID[63]:CPG0*/ + [60] = {0xE6002504U, 0x0000000AU}, /* RGIDW_MODID[64]:CPG1*/ + [61] = {0xE6002508U, 0x0000004EU}, /* RGIDW_MODID[65]:CPG2*/ + [62] = {0xE600250CU, 0x00000028U}, /* RGIDW_MODID[66]:CPG3*/ + [63] = {0xE6002510U, 0x0000006FU}, /* RGIDW_MODID[67]:PFC00*/ + [64] = {0xE6002514U, 0x0000000AU}, /* RGIDW_MODID[68]:PFC01*/ + [65] = {0xE6002518U, 0x0000004EU}, /* RGIDW_MODID[69]:PFC02*/ + [66] = {0xE600251CU, 0x00000028U}, /* RGIDW_MODID[70]:PFC03*/ + [67] = {0xE6002520U, 0x0000006FU}, /* RGIDW_MODID[71]:PFC10*/ + [68] = {0xE6002524U, 0x0000000AU}, /* RGIDW_MODID[72]:PFC11*/ + [69] = {0xE6002528U, 0x0000004EU}, /* RGIDW_MODID[73]:PFC12*/ + [70] = {0xE600252CU, 0x00000028U}, /* RGIDW_MODID[74]:PFC13*/ + [71] = {0xE6002530U, 0x0000006FU}, /* RGIDW_MODID[75]:PFC20*/ + [72] = {0xE6002534U, 0x0000000AU}, /* RGIDW_MODID[76]:PFC21*/ + [73] = {0xE6002538U, 0x0000004EU}, /* RGIDW_MODID[77]:PFC22*/ + [74] = {0xE600253CU, 0x00000028U}, /* RGIDW_MODID[78]:PFC23*/ + [75] = {0xE6002550U, 0x0000006FU}, /* RGIDW_MODID[79]:PFCS0*/ + [76] = {0xE6002554U, 0x0000000AU}, /* RGIDW_MODID[80]:PFCS1*/ + [77] = {0xE6002558U, 0x0000004EU}, /* RGIDW_MODID[81]:PFCS2*/ + [78] = {0xE600255CU, 0x00000028U}, /* RGIDW_MODID[82]:PFCS3*/ + [79] = {0xE6002560U, 0x0000006FU}, /* RGIDW_MODID[83]:RESET0*/ + [80] = {0xE6002564U, 0x0000000AU}, /* RGIDW_MODID[84]:RESET1*/ + [81] = {0xE6002568U, 0x0000004EU}, /* RGIDW_MODID[85]:RESET2*/ + [82] = {0xE600256CU, 0x00000028U}, /* RGIDW_MODID[86]:RESET3*/ + [83] = {0xE6002570U, 0x0000006FU}, /* RGIDW_MODID[87]:SYS0*/ + [84] = {0xE6002574U, 0x0000000AU}, /* RGIDW_MODID[88]:SYS1*/ + [85] = {0xE6002578U, 0x0000004EU}, /* RGIDW_MODID[89]:SYS2*/ + [86] = {0xE600257CU, 0x00000028U}, /* RGIDW_MODID[90]:SYS3*/ + [87] = {0xE7762400U, 0x0000000EU}, /* RGIDW_MODID[91]:DMAMSI0*/ + [88] = {0xE7762404U, 0x0000000EU}, /* RGIDW_MODID[92]:DMAMSI1*/ + [89] = {0xE7762408U, 0x0000000EU}, /* RGIDW_MODID[93]:DMAMSI2*/ + [90] = {0xE776240CU, 0x0000000EU}, /* RGIDW_MODID[94]:DMAMSI3*/ + [91] = {0xE7762410U, 0x0000000EU}, /* RGIDW_MODID[95]:DMAMSI4*/ + [92] = {0xE7762414U, 0x0000000EU}, /* RGIDW_MODID[96]:DMAMSI5*/ + [93] = {0xE7762418U, 0x0000000AU}, /* RGIDW_MODID[97]:ECMSP3*/ + [94] = {0xE7762424U, 0x00000002U}, /* RGIDW_MODID[98]:ARSP30*/ + /* After setting */ /* RGIDW_MODID[99]:ARSP31*/ + /* After setting */ /* RGIDW_MODID[100]:ARSP32*/ + [95] = {0xE7762430U, 0x00000001U}, /* RGIDW_MODID[101]:ARSP33*/ + [96] = {0xE7762434U, 0x00000002U}, /* RGIDW_MODID[102]:ARSP34*/ + [97] = {0xE7762438U, 0x00000001U}, /* RGIDW_MODID[103]:ARSP35*/ + [98] = {0xE776243CU, 0x00000002U}, /* RGIDW_MODID[104]:ARSP36*/ + [99] = {0xE7762440U, 0x00000002U}, /* RGIDW_MODID[105]:ARSP37*/ + [100] = {0xE7762444U, 0x00000000U}, /* RGIDW_MODID[106]:ARSP38*/ + [101] = {0xE7762448U, 0x0000000EU}, /* RGIDW_MODID[107]:MSI0*/ + [102] = {0xE776244CU, 0x0000000EU}, /* RGIDW_MODID[108]:MSI1*/ + [103] = {0xE7762450U, 0x0000000EU}, /* RGIDW_MODID[109]:MSI2*/ + [104] = {0xE7762454U, 0x0000000EU}, /* RGIDW_MODID[110]:MSI3*/ + [105] = {0xE7762458U, 0x0000000EU}, /* RGIDW_MODID[111]:MSI4*/ + [106] = {0xE776245CU, 0x0000000EU}, /* RGIDW_MODID[112]:MSI5*/ + [107] = {0xE7792400U, 0x00000002U}, /* RGIDW_MODID[113]:ARSP40*/ + /* After setting */ /* RGIDW_MODID[114]:ARSP41*/ + /* After setting */ /* RGIDW_MODID[115]:ARSP42*/ + [108] = {0xE779240CU, 0x00000001U}, /* RGIDW_MODID[116]:ARSP43*/ + [109] = {0xE7792410U, 0x00000002U}, /* RGIDW_MODID[117]:ARSP44*/ + [110] = {0xE7792414U, 0x00000001U}, /* RGIDW_MODID[118]:ARSP45*/ + [111] = {0xE7792418U, 0x00000002U}, /* RGIDW_MODID[119]:ARSP46*/ + [112] = {0xE779241CU, 0x00000002U}, /* RGIDW_MODID[120]:ARSP47*/ + [113] = {0xE7792420U, 0x00000000U}, /* RGIDW_MODID[121]:ARSP48*/ + [114] = {0xE7792424U, 0x0000004FU}, /* RGIDW_MODID[122]:DMAHSCIF0*/ + [115] = {0xE7792428U, 0x0000004FU}, /* RGIDW_MODID[123]:DMAHSCIF1*/ + [116] = {0xE779242CU, 0x0000004FU}, /* RGIDW_MODID[124]:DMAHSCIF2*/ + [117] = {0xE7792430U, 0x0000004FU}, /* RGIDW_MODID[125]:DMAHSCIF3*/ + [118] = {0xE7792434U, 0x0000004FU}, /* RGIDW_MODID[126]:DMASCIF0*/ + [119] = {0xE7792438U, 0x0000004FU}, /* RGIDW_MODID[127]:DMASCIF1*/ + [120] = {0xE779243CU, 0x0000004FU}, /* RGIDW_MODID[128]:DMASCIF3*/ + [121] = {0xE7792440U, 0x0000004FU}, /* RGIDW_MODID[129]:DMASCIF4*/ + [122] = {0xE7792444U, 0x0000000AU}, /* RGIDW_MODID[130]:ECMSP4*/ + [123] = {0xE7792448U, 0x0000004FU}, /* RGIDW_MODID[131]:HSCIF0*/ + [124] = {0xE779244CU, 0x0000004FU}, /* RGIDW_MODID[132]:HSCIF1*/ + [125] = {0xE7792450U, 0x0000004FU}, /* RGIDW_MODID[133]:HSCIF2*/ + [126] = {0xE7792454U, 0x0000004FU}, /* RGIDW_MODID[134]:HSCIF3*/ + [127] = {0xE7792458U, 0x0000004FU}, /* RGIDW_MODID[135]:SCIF0*/ + [128] = {0xE779245CU, 0x0000004FU}, /* RGIDW_MODID[136]:SCIF1*/ + [129] = {0xE7792460U, 0x0000004FU}, /* RGIDW_MODID[137]:SCIF3*/ + [130] = {0xE7792464U, 0x0000004FU}, /* RGIDW_MODID[138]:SCIF4*/ + [131] = {0xE7792468U, 0x0000006EU}, /* RGIDW_MODID[139]:TMU1*/ + [132] = {0xE779246CU, 0x0000006EU}, /* RGIDW_MODID[140]:TMU2*/ + [133] = {0xE7792470U, 0x0000006EU}, /* RGIDW_MODID[141]:TMU3*/ + [134] = {0xE7792474U, 0x0000006EU}, /* RGIDW_MODID[142]:TMU4*/ + [135] = {0xE7792478U, 0x0000004AU}, /* RGIDW_MODID[143]:CANFD*/ + [136] = {0xE779247CU, 0x0000004AU}, /* RGIDW_MODID[144]:DMACANFD*/ + [137] = {0xE7792480U, 0x00000002U}, /* RGIDW_MODID[145]:DMATPU0*/ + [138] = {0xE7792484U, 0x00000002U}, /* RGIDW_MODID[146]:PWM0*/ + [139] = {0xE7792488U, 0x00000002U}, /* RGIDW_MODID[147]:PWM1*/ + [140] = {0xE779248CU, 0x00000002U}, /* RGIDW_MODID[148]:PWM2*/ + [141] = {0xE7792490U, 0x00000002U}, /* RGIDW_MODID[149]:PWM3*/ + [142] = {0xE7792494U, 0x00000002U}, /* RGIDW_MODID[150]:PWM4*/ + [143] = {0xE77924ACU, 0x00000002U}, /* RGIDW_MODID[151]:TPU0*/ + [144] = {0xFEBD2400U, 0x00000002U}, /* RGIDW_MODID[152]:ARVI40*/ + /* After setting */ /* RGIDW_MODID[153]:ARVI41*/ + /* After setting */ /* RGIDW_MODID[154]:ARVI42*/ + [145] = {0xFEBD240CU, 0x00000001U}, /* RGIDW_MODID[155]:ARVI43*/ + [146] = {0xFEBD2410U, 0x00000002U}, /* RGIDW_MODID[156]:ARVI44*/ + [147] = {0xFEBD2414U, 0x00000001U}, /* RGIDW_MODID[157]:ARVI45*/ + [148] = {0xFEBD2418U, 0x00000002U}, /* RGIDW_MODID[158]:ARVI46*/ + [149] = {0xFEBD241CU, 0x00000002U}, /* RGIDW_MODID[159]:ARVI47*/ + [150] = {0xFEBD2420U, 0x00000000U}, /* RGIDW_MODID[160]:ARVI48*/ + [151] = {0xFEBD2424U, 0x0000000FU}, /* RGIDW_MODID[161]:DIS0*/ + [152] = {0xFEBD2430U, 0x0000000EU}, /* RGIDW_MODID[162]:ECMVIO2*/ + [153] = {0xFEBD2434U, 0x0000000FU}, /* RGIDW_MODID[163]:FCPVD0*/ + [154] = {0xFEBD243CU, 0x0000004EU}, /* RGIDW_MODID[164]:VSPD0*/ + [155] = {0xE6582400U, 0x0000000AU}, /* RGIDW_MODID[165]:CKMHSC*/ + [156] = {0xE6582404U, 0x0000000CU}, /* RGIDW_MODID[166]:AXIPCI001*/ + [157] = {0xE6582408U, 0x0000000CU}, /* RGIDW_MODID[167]:AXIPCI002*/ + [158] = {0xE658240CU, 0x0000000CU}, /* RGIDW_MODID[168]:AXIPCI003*/ + [159] = {0xE6582414U, 0x0000000CU}, /* RGIDW_MODID[169]:AXIPCI005*/ + [160] = {0xE6582418U, 0x0000000CU}, /* RGIDW_MODID[170]:AXIPCI006*/ + [161] = {0xE658241CU, 0x0000000CU}, /* RGIDW_MODID[171]:AXIPCI007*/ + [162] = {0xE6582420U, 0x0000000CU}, /* RGIDW_MODID[172]:AXIPCI008*/ + [163] = {0xE6582424U, 0x0000000CU}, /* RGIDW_MODID[173]:AXIPCI009*/ + [164] = {0xE6582428U, 0x0000000CU}, /* RGIDW_MODID[174]:AXIPCI010*/ + [165] = {0xE658242CU, 0x0000000CU}, /* RGIDW_MODID[175]:AXIPCI011*/ + [166] = {0xE6582430U, 0x0000000CU}, /* RGIDW_MODID[176]:AXIPCI012*/ + [167] = {0xE6582434U, 0x0000000CU}, /* RGIDW_MODID[177]:AXIPCI013*/ + [168] = {0xE6582438U, 0x0000000CU}, /* RGIDW_MODID[178]:AXIPCI014*/ + [169] = {0xE658243CU, 0x0000000CU}, /* RGIDW_MODID[179]:AXIPCI015*/ + [170] = {0xE6582484U, 0x0000000EU}, /* RGIDW_MODID[180]:GPTP*/ + [171] = {0xE6582488U, 0x0000004EU}, /* RGIDW_MODID[181]:IPMMUHC00*/ + [172] = {0xE65824F4U, 0x0000000CU}, /* RGIDW_MODID[182]:AXIPCI000*/ + [173] = {0xE65824F8U, 0x0000000CU}, /* RGIDW_MODID[183]:AXIPCI004*/ + [174] = {0xE65824FCU, 0x0000004EU}, /* RGIDW_MODID[184]:IPMMUHC01*/ + [175] = {0xE6582500U, 0x0000004EU}, /* RGIDW_MODID[185]:AVB0*/ + [176] = {0xE6582504U, 0x0000004EU}, /* RGIDW_MODID[186]:AVB1*/ + [177] = {0xE6582508U, 0x0000004EU}, /* RGIDW_MODID[187]:AVB2*/ + [178] = {0xE658250CU, 0x0000004EU}, /* RGIDW_MODID[188]:IPMMUHC10*/ + [179] = {0xE6582510U, 0x0000004EU}, /* RGIDW_MODID[189]:IPMMUHC11*/ + [180] = {0xE6582514U, 0x0000004EU}, /* RGIDW_MODID[190]:IPMMUHC12*/ + [181] = {0xE6582518U, 0x0000004EU}, /* RGIDW_MODID[191]:IPMMUHC13*/ + [182] = {0xE658251CU, 0x0000000CU}, /* RGIDW_MODID[192]:PPHY0*/ + [183] = {0xE6582524U, 0x0000004EU}, /* RGIDW_MODID[193]:IPMMUHC14*/ + [184] = {0xE6582528U, 0x0000004EU}, /* RGIDW_MODID[194]:IPMMUHC15*/ + [185] = {0xE658252CU, 0x0000000EU}, /* RGIDW_MODID[195]:FBAHSC*/ + [186] = {0xE6582530U, 0x0000004EU}, /* RGIDW_MODID[196]:IPMMUHC02*/ + [187] = {0xE6582538U, 0x0000000AU}, /* RGIDW_MODID[197]:ECMHSC*/ + [188] = {0xE658253CU, 0x00000002U}, /* RGIDW_MODID[198]:ARHC0*/ + /* After setting */ /* RGIDW_MODID[199]:ARHC1*/ + /* After setting */ /* RGIDW_MODID[200]:ARHC2*/ + [189] = {0xE6582548U, 0x00000001U}, /* RGIDW_MODID[201]:ARHC3*/ + [190] = {0xE658254CU, 0x00000002U}, /* RGIDW_MODID[202]:ARHC4*/ + [191] = {0xE6582550U, 0x00000001U}, /* RGIDW_MODID[203]:ARHC5*/ + [192] = {0xE6582554U, 0x00000002U}, /* RGIDW_MODID[204]:ARHC6*/ + [193] = {0xE6582558U, 0x00000002U}, /* RGIDW_MODID[205]:ARHC7*/ + [194] = {0xE658255CU, 0x00000000U}, /* RGIDW_MODID[206]:ARHC8*/ + [195] = {0xE6582560U, 0x0000004EU}, /* RGIDW_MODID[207]:IPMMUHC03*/ + [196] = {0xE6582564U, 0x0000004EU}, /* RGIDW_MODID[208]:IPMMUHC04*/ + [197] = {0xE6582568U, 0x0000004EU}, /* RGIDW_MODID[209]:IPMMUHC05*/ + [198] = {0xE658256CU, 0x0000004EU}, /* RGIDW_MODID[210]:IPMMUHC06*/ + [199] = {0xE6582570U, 0x0000004EU}, /* RGIDW_MODID[211]:IPMMUHC07*/ + [200] = {0xE6582574U, 0x0000004EU}, /* RGIDW_MODID[212]:IPMMUHC08*/ + [201] = {0xE6582578U, 0x0000004EU}, /* RGIDW_MODID[213]:IPMMUHC09*/ + [202] = {0xFF882400U, 0x00000002U}, /* RGIDW_MODID[214]:ARIMP00*/ + /* After setting */ /* RGIDW_MODID[215]:ARIMP01*/ + /* After setting */ /* RGIDW_MODID[216]:ARIMP02*/ + [203] = {0xFF88240CU, 0x00000001U}, /* RGIDW_MODID[217]:ARIMP03*/ + [204] = {0xFF882410U, 0x00000002U}, /* RGIDW_MODID[218]:ARIMP04*/ + [205] = {0xFF882414U, 0x0000004EU}, /* RGIDW_MODID[219]:AXIFBABUSIR0*/ + [206] = {0xFF882418U, 0x0000004EU}, /* RGIDW_MODID[220]:AXIFBABUSIR1*/ + [207] = {0xFF88241CU, 0x0000004EU}, /* RGIDW_MODID[221]:AXIFBABUSIR2*/ + [208] = {0xFF882420U, 0x0000004EU}, /* RGIDW_MODID[222]:AXIFBABUSIR3*/ + [209] = {0xFF882428U, 0x0000004EU}, /* RGIDW_MODID[223]:AXIIMP0*/ + [210] = {0xFF882434U, 0x00000001U}, /* RGIDW_MODID[224]:ARIMP05*/ + [211] = {0xFF882438U, 0x00000002U}, /* RGIDW_MODID[225]:ARIMP06*/ + [212] = {0xFF88243CU, 0x00000002U}, /* RGIDW_MODID[226]:ARIMP07*/ + [213] = {0xFF882440U, 0x00000000U}, /* RGIDW_MODID[227]:ARIMP08*/ + [214] = {0xFF882448U, 0x0000000AU}, /* RGIDW_MODID[228]:ECMIR*/ + [215] = {0xFF88244CU, 0x0000000FU}, /* RGIDW_MODID[229]:DSPPS*/ + [216] = {0xFF882450U, 0x0000004EU}, /* RGIDW_MODID[230]:IPMMUIR1*/ + [217] = {0xFF882454U, 0x0000004EU}, /* RGIDW_MODID[231]:IPMMUIR0*/ + [218] = {0xFF882458U, 0x0000004EU}, /* RGIDW_MODID[232]:IPMMUIR10*/ + [219] = {0xFF88245CU, 0x0000004EU}, /* RGIDW_MODID[233]:IPMMUIR11*/ + [220] = {0xFF882460U, 0x0000004EU}, /* RGIDW_MODID[234]:IPMMUIR12*/ + [221] = {0xFF882464U, 0x0000004EU}, /* RGIDW_MODID[235]:IPMMUIR13*/ + [222] = {0xFF882468U, 0x0000004EU}, /* RGIDW_MODID[236]:IPMMUIR14*/ + [223] = {0xFF88246CU, 0x0000004EU}, /* RGIDW_MODID[237]:IPMMUIR15*/ + [224] = {0xFF882470U, 0x0000004EU}, /* RGIDW_MODID[238]:IPMMUIR2*/ + [225] = {0xFF882474U, 0x0000004EU}, /* RGIDW_MODID[239]:IPMMUIR3*/ + [226] = {0xFF882478U, 0x0000004EU}, /* RGIDW_MODID[240]:IPMMUIR4*/ + [227] = {0xFF88247CU, 0x0000004EU}, /* RGIDW_MODID[241]:IPMMUIR5*/ + [228] = {0xFF882480U, 0x0000004EU}, /* RGIDW_MODID[242]:IPMMUIR6*/ + [229] = {0xFF882484U, 0x0000004EU}, /* RGIDW_MODID[243]:IPMMUIR7*/ + [230] = {0xFF882488U, 0x0000004EU}, /* RGIDW_MODID[244]:IPMMUIR8*/ + [231] = {0xFF88248CU, 0x0000004EU}, /* RGIDW_MODID[245]:IPMMUIR9*/ + [232] = {0xFD812400U, 0x00000002U}, /* RGIDW_MODID[246]:ARPV0*/ + /* After setting */ /* RGIDW_MODID[247]:ARPV1*/ + [233] = {0xFD812408U, 0x0000002CU}, /* RGIDW_MODID[248]:AXIRGXS*/ + /* After setting */ /* RGIDW_MODID[249]:ARPV2*/ + [234] = {0xFD812410U, 0x00000001U}, /* RGIDW_MODID[250]:ARPV3*/ + [235] = {0xFD812414U, 0x00000002U}, /* RGIDW_MODID[251]:ARPV4*/ + [236] = {0xFD812418U, 0x00000001U}, /* RGIDW_MODID[252]:ARPV5*/ + [237] = {0xFD81241CU, 0x00000002U}, /* RGIDW_MODID[253]:ARPV6*/ + [238] = {0xFD812420U, 0x00000002U}, /* RGIDW_MODID[254]:ARPV7*/ + [239] = {0xFD812424U, 0x00000000U}, /* RGIDW_MODID[255]:ARPV8*/ + [240] = {0xFD81242CU, 0x0000000AU}, /* RGIDW_MODID[256]:ECM3DG*/ + [241] = {0xFD812430U, 0x0000000EU}, /* RGIDW_MODID[257]:FBAPVC*/ + [242] = {0xFD812434U, 0x0000000EU}, /* RGIDW_MODID[258]:FBAPVD0*/ + [243] = {0xFD812438U, 0x0000000EU}, /* RGIDW_MODID[259]:FBAPVD1*/ + [244] = {0xFD81243CU, 0x0000000EU}, /* RGIDW_MODID[260]:FBAPVD2*/ + [245] = {0xFD812440U, 0x0000000EU}, /* RGIDW_MODID[261]:FBAPVE*/ + [246] = {0xFD812444U, 0x0000004EU}, /* RGIDW_MODID[262]:IPMMUPV000*/ + [247] = {0xFD812448U, 0x0000004EU}, /* RGIDW_MODID[263]:IPMMUPV001*/ + [248] = {0xFD81244CU, 0x0000004EU}, /* RGIDW_MODID[264]:IPMMUPV010*/ + [249] = {0xFD812450U, 0x0000004EU}, /* RGIDW_MODID[265]:IPMMUPV011*/ + [250] = {0xFD812454U, 0x0000004EU}, /* RGIDW_MODID[266]:IPMMUPV012*/ + [251] = {0xFD812458U, 0x0000004EU}, /* RGIDW_MODID[267]:IPMMUPV013*/ + [252] = {0xFD81245CU, 0x0000004EU}, /* RGIDW_MODID[268]:IPMMUPV014*/ + [253] = {0xFD812460U, 0x0000004EU}, /* RGIDW_MODID[269]:IPMMUPV015*/ + [254] = {0xFD812464U, 0x0000004EU}, /* RGIDW_MODID[270]:IPMMUPV002*/ + [255] = {0xFD812468U, 0x0000004EU}, /* RGIDW_MODID[271]:IPMMUPV003*/ + [256] = {0xFD81246CU, 0x0000004EU}, /* RGIDW_MODID[272]:IPMMUPV004*/ + [257] = {0xFD812470U, 0x0000004EU}, /* RGIDW_MODID[273]:IPMMUPV005*/ + [258] = {0xFD812474U, 0x0000004EU}, /* RGIDW_MODID[274]:IPMMUPV006*/ + [259] = {0xFD812478U, 0x0000004EU}, /* RGIDW_MODID[275]:IPMMUPV007*/ + [260] = {0xFD81247CU, 0x0000004EU}, /* RGIDW_MODID[276]:IPMMUPV008*/ + [261] = {0xFD812480U, 0x0000004EU}, /* RGIDW_MODID[277]:IPMMUPV009*/ + [262] = {0xE6622400U, 0x00000002U}, /* RGIDW_MODID[278]:ARRC0*/ + /* After setting */ /* RGIDW_MODID[279]:ARRC1*/ + /* After setting */ /* RGIDW_MODID[280]:ARRC2*/ + [263] = {0xE662240CU, 0x00000001U}, /* RGIDW_MODID[281]:ARRC3*/ + [264] = {0xE6622410U, 0x00000002U}, /* RGIDW_MODID[282]:ARRC4*/ + [265] = {0xE6622414U, 0x00000001U}, /* RGIDW_MODID[283]:ARRC5*/ + [266] = {0xE6622418U, 0x00000002U}, /* RGIDW_MODID[284]:ARRC6*/ + [267] = {0xE662241CU, 0x00000002U}, /* RGIDW_MODID[285]:ARRC7*/ + [268] = {0xE6622420U, 0x00000000U}, /* RGIDW_MODID[286]:ARRC8*/ + [269] = {0xE6622428U, 0x0000004FU}, /* RGIDW_MODID[287]:ICUMX*/ + [270] = {0xE662242CU, 0x0000000AU}, /* RGIDW_MODID[288]:ECMRC*/ + [271] = {0xFFC32400U, 0x0000004EU}, /* RGIDW_MODID[289]:DMAWCRC0*/ + [272] = {0xFFC32404U, 0x0000004EU}, /* RGIDW_MODID[290]:DMAWCRC1*/ + [273] = {0xFFC32408U, 0x0000004EU}, /* RGIDW_MODID[291]:DMAWCRC2*/ + [274] = {0xFFC3240CU, 0x0000004EU}, /* RGIDW_MODID[292]:DMAWCRC3*/ + [275] = {0xFFC42400U, 0x0000000FU}, /* RGIDW_MODID[293]:ARMREG00*/ + [276] = {0xFFC42404U, 0x0000000CU}, /* RGIDW_MODID[294]:ARMREG01*/ + [277] = {0xFFC42408U, 0x00000000U}, /* RGIDW_MODID[295]:ARMREG10*/ + [278] = {0xFFC4240CU, 0x00000000U}, /* RGIDW_MODID[296]:ARMREG11*/ + [279] = {0xFFC42410U, 0x0000000AU}, /* RGIDW_MODID[297]:ARMREG12*/ + [280] = {0xFFC42414U, 0x0000000FU}, /* RGIDW_MODID[298]:ARMREG13*/ + [281] = {0xFFC42418U, 0x0000000AU}, /* RGIDW_MODID[299]:ARMREG14*/ + [282] = {0xFFC4241CU, 0x00000003U}, /* RGIDW_MODID[300]:AXICR52SS0*/ + [283] = {0xFFC42420U, 0x0000000EU}, /* RGIDW_MODID[301]:AXICSD0*/ + [284] = {0xFFC42424U, 0x0000000EU}, /* RGIDW_MODID[302]:AXIINTAP0*/ + [285] = {0xFFC42430U, 0x0000000FU}, /* RGIDW_MODID[303]:AXISYSRAM0*/ + [286] = {0xFFC42434U, 0x0000004FU}, /* RGIDW_MODID[304]:AXISYSRAM1*/ + [287] = {0xFFC42438U, 0x00000000U}, /* RGIDW_MODID[305]:ARGREG15*/ + [288] = {0xFFC4243CU, 0x00000000U}, /* RGIDW_MODID[306]:ARMREG2*/ + [289] = {0xFFC42440U, 0x00000000U}, /* RGIDW_MODID[307]:ARMREG3*/ + [290] = {0xFFC42444U, 0x00000000U}, /* RGIDW_MODID[308]:ARMREG4*/ + [291] = {0xFFC42448U, 0x0000000FU}, /* RGIDW_MODID[309]:ARMREG5*/ + [292] = {0xFFC4244CU, 0x0000000AU}, /* RGIDW_MODID[310]:ARMREG6*/ + [293] = {0xFFC42450U, 0x00000000U}, /* RGIDW_MODID[311]:ARMREG7*/ + [294] = {0xFFC42454U, 0x0000000CU}, /* RGIDW_MODID[312]:ARMREG8*/ + [295] = {0xFFC42458U, 0x0000000CU}, /* RGIDW_MODID[313]:ARMREG9*/ + [296] = {0xFFC4245CU, 0x00000002U}, /* RGIDW_MODID[314]:ARRD0*/ + /* After setting */ /* RGIDW_MODID[315]:ARRD1*/ + /* After setting */ /* RGIDW_MODID[316]:ARRD2*/ + [297] = {0xFFC42468U, 0x00000001U}, /* RGIDW_MODID[317]:ARRD3*/ + [298] = {0xFFC4246CU, 0x00000002U}, /* RGIDW_MODID[318]:ARRD4*/ + [299] = {0xFFC42470U, 0x00000001U}, /* RGIDW_MODID[319]:ARRD5*/ + [300] = {0xFFC42474U, 0x00000002U}, /* RGIDW_MODID[320]:ARRD6*/ + [301] = {0xFFC42478U, 0x00000002U}, /* RGIDW_MODID[321]:ARRD7*/ + [302] = {0xFFC4247CU, 0x00000000U}, /* RGIDW_MODID[322]:ARRD8*/ + [303] = {0xFFC42480U, 0x00000002U}, /* RGIDW_MODID[323]:ARRT0*/ + /* After setting */ /* RGIDW_MODID[324]:ARRT1*/ + /* After setting */ /* RGIDW_MODID[325]:ARRT2*/ + [304] = {0xFFC4248CU, 0x00000001U}, /* RGIDW_MODID[326]:ARRT3*/ + [305] = {0xFFC42490U, 0x00000002U}, /* RGIDW_MODID[327]:ARRT4*/ + [306] = {0xFFC42494U, 0x00000001U}, /* RGIDW_MODID[328]:ARRT5*/ + [307] = {0xFFC42498U, 0x00000002U}, /* RGIDW_MODID[329]:ARRT6*/ + [308] = {0xFFC4249CU, 0x00000002U}, /* RGIDW_MODID[330]:ARRT7*/ + [309] = {0xFFC424A0U, 0x00000000U}, /* RGIDW_MODID[331]:ARRT8*/ + [310] = {0xFFC424A4U, 0x0000000AU}, /* RGIDW_MODID[332]:CKMRT*/ + [311] = {0xFFC424A8U, 0x0000004EU}, /* RGIDW_MODID[333]:CRC0*/ + [312] = {0xFFC424ACU, 0x0000004EU}, /* RGIDW_MODID[334]:CRC1*/ + [313] = {0xFFC424B0U, 0x0000004EU}, /* RGIDW_MODID[335]:CRC2*/ + [314] = {0xFFC424B4U, 0x0000004EU}, /* RGIDW_MODID[336]:CRC3*/ + [315] = {0xFFC424B8U, 0x0000000EU}, /* RGIDW_MODID[337]:CSD*/ + [316] = {0xFFC424BCU, 0x0000000EU}, /* RGIDW_MODID[338]:ECM*/ + [317] = {0xFFC424C0U, 0x0000000AU}, /* RGIDW_MODID[339]:ECMRT*/ + [318] = {0xFFC424C4U, 0x0000000EU}, /* RGIDW_MODID[340]:FBACR52*/ + [319] = {0xFFC424C8U, 0x0000000EU}, /* RGIDW_MODID[341]:FBART*/ + [320] = {0xFFC424CCU, 0x0000000EU}, /* RGIDW_MODID[342]:INTTP*/ + [321] = {0xFFC424D0U, 0x0000004EU}, /* RGIDW_MODID[343]:IPMMURT000*/ + [322] = {0xFFC424D4U, 0x0000004EU}, /* RGIDW_MODID[344]:IPMMURT100*/ + [323] = {0xFFC424D8U, 0x0000004EU}, /* RGIDW_MODID[345]:KCRC4*/ + [324] = {0xFFC424DCU, 0x0000004EU}, /* RGIDW_MODID[346]:KCRC5*/ + [325] = {0xFFC424E0U, 0x0000004EU}, /* RGIDW_MODID[347]:KCRC6*/ + [326] = {0xFFC424E4U, 0x0000004EU}, /* RGIDW_MODID[348]:KCRC7*/ + [327] = {0xFFC424E8U, 0x0000004FU}, /* RGIDW_MODID[349]:MFI00*/ + [328] = {0xFFC424ECU, 0x0000004EU}, /* RGIDW_MODID[350]:MFI01*/ + [329] = {0xFFC424F0U, 0x0000004EU}, /* RGIDW_MODID[351]:MFI10*/ + [330] = {0xFFC424F4U, 0x0000004EU}, /* RGIDW_MODID[352]:MFI02*/ + [331] = {0xFFC424F8U, 0x0000004EU}, /* RGIDW_MODID[353]:MFI03*/ + [332] = {0xFFC424FCU, 0x0000004EU}, /* RGIDW_MODID[354]:MFI04*/ + [333] = {0xFFC42500U, 0x00000000U}, /* RGIDW_MODID[355]:MFI05*/ + [334] = {0xFFC42504U, 0x00000000U}, /* RGIDW_MODID[356]:MFI06*/ + [335] = {0xFFC42508U, 0x00000000U}, /* RGIDW_MODID[357]:MFI07*/ + [336] = {0xFFC4250CU, 0x00000000U}, /* RGIDW_MODID[358]:MFI08*/ + [337] = {0xFFC42510U, 0x0000004EU}, /* RGIDW_MODID[359]:MFI09*/ + [338] = {0xFFC42514U, 0x0000004FU}, /* RGIDW_MODID[360]:MFI15*/ + [339] = {0xFFC42518U, 0x0000000AU}, /* RGIDW_MODID[361]:CKMCR52*/ + [340] = {0xFFC4251CU, 0x0000004BU}, /* RGIDW_MODID[362]:RTDM0P*/ + [341] = {0xFFC42520U, 0x0000000AU}, /* RGIDW_MODID[363]:ECMRD*/ + [342] = {0xFFC42524U, 0x0000004BU}, /* RGIDW_MODID[364]:RTDM1P*/ + [343] = {0xFFC42530U, 0x0000000BU}, /* RGIDW_MODID[365]:SYSRAM10*/ + [344] = {0xFFC42538U, 0x00000001U}, /* RGIDW_MODID[366]:SYSRAM00*/ + [345] = {0xFFC4253CU, 0x0000004EU}, /* RGIDW_MODID[367]:TSIPL0*/ + [346] = {0xFFC42540U, 0x0000004EU}, /* RGIDW_MODID[368]:TSIPL1*/ + [347] = {0xFFC42544U, 0x0000004EU}, /* RGIDW_MODID[369]:TSIPL2*/ + [348] = {0xFFC42548U, 0x0000004EU}, /* RGIDW_MODID[370]:TSIPL3*/ + [349] = {0xFFC4254CU, 0x0000004EU}, /* RGIDW_MODID[371]:TSIPL4*/ + [350] = {0xFFC42550U, 0x0000004EU}, /* RGIDW_MODID[372]:TSIPL5*/ + [351] = {0xFFC42554U, 0x0000004EU}, /* RGIDW_MODID[373]:TSIPL6*/ + [352] = {0xFFC42558U, 0x0000004EU}, /* RGIDW_MODID[374]:TSIPL7*/ + [353] = {0xFFC4255CU, 0x0000004EU}, /* RGIDW_MODID[375]:WCRC0*/ + [354] = {0xFFC42560U, 0x0000004EU}, /* RGIDW_MODID[376]:WCRC1*/ + [355] = {0xFFC42564U, 0x0000004EU}, /* RGIDW_MODID[377]:WCRC2*/ + [356] = {0xFFC42568U, 0x0000004EU}, /* RGIDW_MODID[378]:WCRC3*/ + [357] = {0xFFC42580U, 0x0000004EU}, /* RGIDW_MODID[379]:MFI11*/ + [358] = {0xFFC42584U, 0x00000000U}, /* RGIDW_MODID[380]:MFI12*/ + [359] = {0xFFC42588U, 0x00000000U}, /* RGIDW_MODID[381]:MFI13*/ + [360] = {0xFFC4258CU, 0x00000000U}, /* RGIDW_MODID[382]:MFI14*/ + [361] = {0xFFC42590U, 0x0000004EU}, /* RGIDW_MODID[383]:IPMMURT001*/ + [362] = {0xFFC42594U, 0x0000004EU}, /* RGIDW_MODID[384]:IPMMURT010*/ + [363] = {0xFFC42598U, 0x0000004EU}, /* RGIDW_MODID[385]:IPMMURT011*/ + [364] = {0xFFC4259CU, 0x0000004EU}, /* RGIDW_MODID[386]:IPMMURT012*/ + [365] = {0xFFC425A0U, 0x0000004EU}, /* RGIDW_MODID[387]:IPMMURT013*/ + [366] = {0xFFC425A4U, 0x0000004EU}, /* RGIDW_MODID[388]:IPMMURT014*/ + [367] = {0xFFC425A8U, 0x0000004EU}, /* RGIDW_MODID[389]:IPMMURT015*/ + [368] = {0xFFC425ACU, 0x0000004EU}, /* RGIDW_MODID[390]:IPMMURT002*/ + [369] = {0xFFC425B0U, 0x0000004EU}, /* RGIDW_MODID[391]:IPMMURT003*/ + [370] = {0xFFC425B4U, 0x0000004EU}, /* RGIDW_MODID[392]:IPMMURT004*/ + [371] = {0xFFC425B8U, 0x0000004EU}, /* RGIDW_MODID[393]:IPMMURT005*/ + [372] = {0xFFC425BCU, 0x0000004EU}, /* RGIDW_MODID[394]:IPMMURT006*/ + [373] = {0xFFC425C0U, 0x0000004EU}, /* RGIDW_MODID[395]:IPMMURT007*/ + [374] = {0xFFC425C4U, 0x0000004EU}, /* RGIDW_MODID[396]:IPMMURT008*/ + [375] = {0xFFC425C8U, 0x0000004EU}, /* RGIDW_MODID[397]:IPMMURT009*/ + [376] = {0xFFC425CCU, 0x0000004EU}, /* RGIDW_MODID[398]:IPKMURT101*/ + [377] = {0xFFC425D0U, 0x0000004EU}, /* RGIDW_MODID[399]:IPMMURT110*/ + [378] = {0xFFC425D4U, 0x0000004EU}, /* RGIDW_MODID[400]:IPMMURT111*/ + [379] = {0xFFC425D8U, 0x0000004EU}, /* RGIDW_MODID[401]:IPMMURT112*/ + [380] = {0xFFC425DCU, 0x0000004EU}, /* RGIDW_MODID[402]:IPMMURT113*/ + [381] = {0xFFC425E0U, 0x0000004EU}, /* RGIDW_MODID[403]:IPMMURT114*/ + [382] = {0xFFC425E4U, 0x0000004EU}, /* RGIDW_MODID[404]:IPMMURT115*/ + [383] = {0xFFC425E8U, 0x0000004EU}, /* RGIDW_MODID[405]:IPMMURT102*/ + [384] = {0xFFC425ECU, 0x0000004EU}, /* RGIDW_MODID[406]:IPMMURT103*/ + [385] = {0xFFC425F0U, 0x0000004EU}, /* RGIDW_MODID[407]:IPMMURT104*/ + [386] = {0xFFC425F4U, 0x0000004EU}, /* RGIDW_MODID[408]:IPMMURT105*/ + [387] = {0xFFC425F8U, 0x0000004EU}, /* RGIDW_MODID[409]:IPMMURT106*/ + [388] = {0xFFC425FCU, 0x0000004EU}, /* RGIDW_MODID[410]:IPMMURT107*/ + [389] = {0xFFC42600U, 0x0000004BU}, /* RGIDW_MODID[411]:RTDM000*/ + [390] = {0xFFC42604U, 0x0000004BU}, /* RGIDW_MODID[412]:RTDM001*/ + [391] = {0xFFC42608U, 0x0000004BU}, /* RGIDW_MODID[413]:RTDM010*/ + [392] = {0xFFC4260CU, 0x0000004BU}, /* RGIDW_MODID[414]:RTDM011*/ + [393] = {0xFFC42610U, 0x0000004BU}, /* RGIDW_MODID[415]:RTDM012*/ + [394] = {0xFFC42614U, 0x0000004BU}, /* RGIDW_MODID[416]:RTDM013*/ + [395] = {0xFFC42618U, 0x0000004BU}, /* RGIDW_MODID[417]:RTDM014*/ + [396] = {0xFFC4261CU, 0x0000004BU}, /* RGIDW_MODID[418]:RTDM015*/ + [397] = {0xFFC42620U, 0x0000004BU}, /* RGIDW_MODID[419]:RTDM002*/ + [398] = {0xFFC42624U, 0x0000004BU}, /* RGIDW_MODID[420]:RTDM003*/ + [399] = {0xFFC42628U, 0x0000004BU}, /* RGIDW_MODID[421]:RTDM004*/ + [400] = {0xFFC4262CU, 0x0000004BU}, /* RGIDW_MODID[422]:RTDM005*/ + [401] = {0xFFC42630U, 0x0000004BU}, /* RGIDW_MODID[423]:RTDM006*/ + [402] = {0xFFC42634U, 0x0000004BU}, /* RGIDW_MODID[424]:RTDM007*/ + [403] = {0xFFC42638U, 0x0000004BU}, /* RGIDW_MODID[425]:RTDM008*/ + [404] = {0xFFC4263CU, 0x0000004BU}, /* RGIDW_MODID[426]:RTDM009*/ + [405] = {0xFFC42640U, 0x0000004BU}, /* RGIDW_MODID[427]:RTDM100*/ + [406] = {0xFFC42644U, 0x0000004BU}, /* RGIDW_MODID[428]:RTDM101*/ + [407] = {0xFFC42648U, 0x0000004BU}, /* RGIDW_MODID[429]:RTDM110*/ + [408] = {0xFFC4264CU, 0x0000004BU}, /* RGIDW_MODID[430]:RTDM111*/ + [409] = {0xFFC42650U, 0x0000004BU}, /* RGIDW_MODID[431]:RTDM112*/ + [410] = {0xFFC42654U, 0x0000004BU}, /* RGIDW_MODID[432]:RTDM113*/ + [411] = {0xFFC42658U, 0x0000004BU}, /* RGIDW_MODID[433]:RTDM114*/ + [412] = {0xFFC4265CU, 0x0000004BU}, /* RGIDW_MODID[434]:RTDM115*/ + [413] = {0xFFC42660U, 0x0000004BU}, /* RGIDW_MODID[435]:RTDM102*/ + [414] = {0xFFC42664U, 0x0000004BU}, /* RGIDW_MODID[436]:RTDM103*/ + [415] = {0xFFC42668U, 0x0000004BU}, /* RGIDW_MODID[437]:RTDM104*/ + [416] = {0xFFC4266CU, 0x0000004BU}, /* RGIDW_MODID[438]:RTDM105*/ + [417] = {0xFFC42670U, 0x0000004BU}, /* RGIDW_MODID[439]:RTDM106*/ + [418] = {0xFFC42674U, 0x0000004BU}, /* RGIDW_MODID[440]:RTDM107*/ + [419] = {0xFFC42678U, 0x0000004BU}, /* RGIDW_MODID[441]:RTDM108*/ + [420] = {0xFFC4267CU, 0x0000004BU}, /* RGIDW_MODID[442]:RTDM109*/ + [421] = {0xFFC42700U, 0x0000004EU}, /* RGIDW_MODID[443]:IPMMURT108*/ + [422] = {0xFFC42704U, 0x0000004EU}, /* RGIDW_MODID[444]:IPMMURT109*/ + [423] = {0xFFC42708U, 0x00000001U}, /* RGIDW_MODID[445]:SYSRAM01*/ + [424] = {0xFFC4270CU, 0x0000000BU}, /* RGIDW_MODID[446]:SYSRAM02*/ + [425] = {0xFFC42710U, 0x00000001U}, /* RGIDW_MODID[447]:SYSRAM03*/ + [426] = {0xFFC42714U, 0x00000001U}, /* RGIDW_MODID[448]:SYSRAM04*/ + [427] = {0xFFC42718U, 0x00000001U}, /* RGIDW_MODID[449]:SYSRAM05*/ + [428] = {0xFFC4271CU, 0x00000001U}, /* RGIDW_MODID[450]:SYSRAM06*/ + [429] = {0xFFC42720U, 0x00000000U}, /* RGIDW_MODID[451]:SYSRAM07*/ + [430] = {0xFFC42724U, 0x0000000BU}, /* RGIDW_MODID[452]:SYSRAM11*/ + [431] = {0xFFC42728U, 0x0000000AU}, /* RGIDW_MODID[453]:SYSRAM12*/ + [432] = {0xFFC4272CU, 0x0000000BU}, /* RGIDW_MODID[454]:SYSRAM13*/ + [433] = {0xFFC42730U, 0x0000000BU}, /* RGIDW_MODID[455]:SYSRAM14*/ + [434] = {0xFFC42734U, 0x0000000BU}, /* RGIDW_MODID[456]:SYSRAM15*/ + [435] = {0xFFC42738U, 0x0000000BU}, /* RGIDW_MODID[457]:SYSRAM16*/ + [436] = {0xFFC4273CU, 0x00000000U}, /* RGIDW_MODID[458]:SYSRAM17*/ + [437] = {0xFFC42760U, 0x00000002U}, /* RGIDW_MODID[459]:BKBUF*/ + [438] = {0xFFC42764U, 0x00000003U}, /* RGIDW_MODID[460]:AXICR52SS1*/ + [439] = {0xFFC42768U, 0x00000003U}, /* RGIDW_MODID[461]:AXICR52SS2*/ + [440] = {0xFF862400U, 0x00000002U}, /* RGIDW_MODID[462]:ARSC0*/ + /* After setting */ /* RGIDW_MODID[463]:ARSC1*/ + /* After setting */ /* RGIDW_MODID[464]:ARSC2*/ + [441] = {0xFF86240CU, 0x00000001U}, /* RGIDW_MODID[465]:ARSC3*/ + [442] = {0xFF862410U, 0x00000002U}, /* RGIDW_MODID[466]:ARSC4*/ + [443] = {0xFF862414U, 0x00000001U}, /* RGIDW_MODID[467]:ARSC5*/ + [444] = {0xFF862418U, 0x00000002U}, /* RGIDW_MODID[468]:ARSC6*/ + [445] = {0xFF86241CU, 0x00000002U}, /* RGIDW_MODID[469]:ARSC7*/ + [446] = {0xFF862420U, 0x00000000U}, /* RGIDW_MODID[470]:ARSC8*/ + [447] = {0xFF862424U, 0x00000002U}, /* RGIDW_MODID[471]:ARSTM0*/ + /* After setting */ /* RGIDW_MODID[472]:ARSTM1*/ + [448] = {0xFF86242CU, 0x0000000EU}, /* RGIDW_MODID[473]:CSD1S*/ + [449] = {0xFF862430U, 0x0000000EU}, /* RGIDW_MODID[474]:AXIFBABUSTOP0*/ + /* After setting */ /* RGIDW_MODID[475]:ARSTM2*/ + [450] = {0xFF86243CU, 0x00000001U}, /* RGIDW_MODID[476]:ARSTM3*/ + [451] = {0xFF862440U, 0x00000002U}, /* RGIDW_MODID[477]:ARSTM4*/ + [452] = {0xFF862444U, 0x00000001U}, /* RGIDW_MODID[478]:ARSTM5*/ + [453] = {0xFF862448U, 0x00000002U}, /* RGIDW_MODID[479]:ARSTM6*/ + [454] = {0xFF86244CU, 0x00000002U}, /* RGIDW_MODID[480]:ARSTM7*/ + [455] = {0xFF862450U, 0x00000000U}, /* RGIDW_MODID[481]:ARSTM8*/ + [456] = {0xFF862454U, 0x0000000AU}, /* RGIDW_MODID[482]:ECMTOP*/ + [457] = {0xFF862458U, 0x0000000EU}, /* RGIDW_MODID[483]:FBA*/ + [458] = {0xFF86245CU, 0x0000000EU}, /* RGIDW_MODID[484]:FBC*/ + [459] = {0xFF862434U, 0x0000000CU}, /* RGIDW_MODID[485]:AXICCI00*/ + [460] = {0xFF862460U, 0x0000000EU}, /* RGIDW_MODID[486]:AXICCI01*/ + [461] = {0xFF862464U, 0x0000000CU}, /* RGIDW_MODID[487]:AXICCI10*/ + [462] = {0xFF862468U, 0x0000000CU}, /* RGIDW_MODID[488]:AXICCI11*/ + [463] = {0xFF86246CU, 0x0000000CU}, /* RGIDW_MODID[489]:AXICCI12*/ + [464] = {0xFF862470U, 0x0000000CU}, /* RGIDW_MODID[490]:AXICCI13*/ + [465] = {0xFF862474U, 0x0000000CU}, /* RGIDW_MODID[491]:AXICCI14*/ + [466] = {0xFF862478U, 0x0000000CU}, /* RGIDW_MODID[492]:AXICCI15*/ + [467] = {0xFF86247CU, 0x0000000EU}, /* RGIDW_MODID[493]:AXICCI2*/ + [468] = {0xFF862480U, 0x0000000CU}, /* RGIDW_MODID[494]:AXICCI3*/ + [469] = {0xFF862484U, 0x0000000CU}, /* RGIDW_MODID[495]:AXICCI4*/ + [470] = {0xFF862488U, 0x0000000CU}, /* RGIDW_MODID[496]:AXICCI5*/ + [471] = {0xFF86248CU, 0x0000000CU}, /* RGIDW_MODID[497]:AXICCI6*/ + [472] = {0xFF862490U, 0x0000000CU}, /* RGIDW_MODID[498]:AXICCI7*/ + [473] = {0xFF862494U, 0x0000000CU}, /* RGIDW_MODID[499]:AXICCI8*/ + [474] = {0xFF862498U, 0x00000009U}, /* RGIDW_MODID[500]:AXICCI9*/ + [475] = {0xFF8624A0U, 0x0000000AU}, /* RGIDW_MODID[501]:ECMSTM*/ + [476] = {0xE7782400U, 0x0000002CU}, /* RGIDW_MODID[502]:DMASSI00*/ + [477] = {0xE7782404U, 0x0000002CU}, /* RGIDW_MODID[503]:DMASSI01*/ + [478] = {0xE7782408U, 0x0000002CU}, /* RGIDW_MODID[504]:DMASSI02*/ + [479] = {0xE778240CU, 0x0000002CU}, /* RGIDW_MODID[505]:DMASSI03*/ + [480] = {0xE7782410U, 0x0000002CU}, /* RGIDW_MODID[506]:DMASSI04*/ + [481] = {0xE7782414U, 0x0000004EU}, /* RGIDW_MODID[507]:DMAI2C0*/ + [482] = {0xE7782418U, 0x0000004EU}, /* RGIDW_MODID[508]:DMAI2C1*/ + [483] = {0xE778241CU, 0x0000004EU}, /* RGIDW_MODID[509]:DMAI2C2*/ + [484] = {0xE7782420U, 0x0000004EU}, /* RGIDW_MODID[510]:DMAI2C3*/ + [485] = {0xE778242CU, 0x0000002CU}, /* RGIDW_MODID[511]:DMASSI05*/ + [486] = {0xE7782430U, 0x0000002CU}, /* RGIDW_MODID[512]:DMASSI06*/ + [487] = {0xE7782434U, 0x0000002CU}, /* RGIDW_MODID[513]:DMASSI07*/ + [488] = {0xE67C2400U, 0x00000002U}, /* RGIDW_MODID[514]:ARMM*/ + /* After setting */ /* RGIDW_MODID[515]:AXIARNMM*/ + [489] = {0xE67C2408U, 0x00000002U}, /* RGIDW_MODID[516]:ARSM0*/ + /* After setting */ /* RGIDW_MODID[517]:ARSM1*/ + /* After setting */ /* RGIDW_MODID[518]:ARSM2*/ + [490] = {0xE67C2414U, 0x0000000FU}, /* RGIDW_MODID[519]:AXIQOS0*/ + [491] = {0xE67C2418U, 0x0000000FU}, /* RGIDW_MODID[520]:AXIQOS1*/ + [492] = {0xE67C241CU, 0x0000000FU}, /* RGIDW_MODID[521]:AXIQOS2*/ + [493] = {0xE67C2420U, 0x0000000FU}, /* RGIDW_MODID[522]:AXIQOS3*/ + [494] = {0xE67C2424U, 0x0000000FU}, /* RGIDW_MODID[523]:AXIQOS4*/ + [495] = {0xE67C2428U, 0x0000000FU}, /* RGIDW_MODID[524]:AXIQOS5*/ + [496] = {0xE67C2434U, 0x00000001U}, /* RGIDW_MODID[525]:ARSM3*/ + [497] = {0xE67C2438U, 0x00000002U}, /* RGIDW_MODID[526]:ARSM4*/ + [498] = {0xE67C243CU, 0x00000001U}, /* RGIDW_MODID[527]:ARSM5*/ + [499] = {0xE67C2440U, 0x00000002U}, /* RGIDW_MODID[528]:ARSM6*/ + [500] = {0xE67C2444U, 0x00000002U}, /* RGIDW_MODID[529]:ARSM7*/ + [501] = {0xE67C2448U, 0x00000000U}, /* RGIDW_MODID[530]:ARSM8*/ + [502] = {0xE67C244CU, 0x0000000BU}, /* RGIDW_MODID[531]:AXMM0*/ + [503] = {0xE67C2450U, 0x0000000BU}, /* RGIDW_MODID[532]:AXMM1*/ + [504] = {0xE67C2454U, 0x00000000U}, /* RGIDW_MODID[533]:AXMMPMON*/ + [505] = {0xE67C2458U, 0x0000000AU}, /* RGIDW_MODID[534]:CKMMM*/ + [506] = {0xE67C245CU, 0x0000000AU}, /* RGIDW_MODID[535]:ECMMM*/ + [507] = {0xE67C2460U, 0x0000000EU}, /* RGIDW_MODID[536]:FBADBSC0*/ + [508] = {0xE67C2468U, 0x0000000EU}, /* RGIDW_MODID[537]:FBAMM*/ + [509] = {0xE67C246CU, 0x0000004EU}, /* RGIDW_MODID[538]:IPMMUMM00*/ + [510] = {0xE67C2470U, 0x0000000FU}, /* RGIDW_MODID[539]:DBS0A0*/ + [511] = {0xE67C2474U, 0x0000000AU}, /* RGIDW_MODID[540]:DBS0A1*/ + [512] = {0xE67C2484U, 0x00000009U}, /* RGIDW_MODID[541]:FCPRC*/ + [513] = {0xE67C2488U, 0x0000000FU}, /* RGIDW_MODID[542]:DBS0D0*/ + [514] = {0xE67C248CU, 0x0000000AU}, /* RGIDW_MODID[543]:DBS0D1*/ + [515] = {0xE67C2498U, 0x0000000EU}, /* RGIDW_MODID[544]:FBADDR*/ + [516] = {0xE67C249CU, 0x0000004EU}, /* RGIDW_MODID[545]:IPMMUMM01*/ + [517] = {0xE67C24A0U, 0x0000004EU}, /* RGIDW_MODID[546]:IPMMUMM10*/ + [518] = {0xE67C24A4U, 0x0000004EU}, /* RGIDW_MODID[547]:IPMMUMM11*/ + [519] = {0xE67C24A8U, 0x0000004EU}, /* RGIDW_MODID[548]:IPMMUMM12*/ + [520] = {0xE67C24ACU, 0x0000004EU}, /* RGIDW_MODID[549]:IPMMUMM13*/ + [521] = {0xE67C24B0U, 0x0000004EU}, /* RGIDW_MODID[550]:IPMMUMM14*/ + [522] = {0xE67C24B4U, 0x0000004EU}, /* RGIDW_MODID[551]:IPMMUMM15*/ + [523] = {0xE67C24B8U, 0x0000004EU}, /* RGIDW_MODID[552]:IPMMUMM02*/ + [524] = {0xE67C24BCU, 0x0000004EU}, /* RGIDW_MODID[553]:IPMMUMM03*/ + [525] = {0xE67C24C0U, 0x0000004EU}, /* RGIDW_MODID[554]:IPMMUMM04*/ + [526] = {0xE67C24C4U, 0x0000004EU}, /* RGIDW_MODID[555]:IPMMUMM05*/ + [527] = {0xE67C24C8U, 0x0000004EU}, /* RGIDW_MODID[556]:IPMMUMM06*/ + [528] = {0xE67C24CCU, 0x0000004EU}, /* RGIDW_MODID[557]:IPMMUMM07*/ + [529] = {0xE67C24D0U, 0x0000004EU}, /* RGIDW_MODID[558]:IPMMUMM08*/ + [530] = {0xE67C24D4U, 0x0000004EU}, /* RGIDW_MODID[559]:IPMMUMM09*/ + [531] = {0xFF802400U, 0x00000002U}, /* RGIDW_MODID[560]:ARSN0*/ + /* After setting */ /* RGIDW_MODID[561]:ARSN1*/ + /* After setting */ /* RGIDW_MODID[562]:ARSN2*/ + [532] = {0xFF80240CU, 0x00000001U}, /* RGIDW_MODID[563]:ARSN3*/ + [533] = {0xFF802410U, 0x00000002U}, /* RGIDW_MODID[564]:ARSN4*/ + [534] = {0xFF802414U, 0x00000001U}, /* RGIDW_MODID[565]:ARSN5*/ + [535] = {0xFF802418U, 0x00000002U}, /* RGIDW_MODID[566]:ARSN6*/ + [536] = {0xFF80241CU, 0x00000002U}, /* RGIDW_MODID[567]:ARSN7*/ + [537] = {0xFF802420U, 0x00000000U}, /* RGIDW_MODID[568]:ARSN8*/ + [538] = {0xFF802424U, 0x0000000AU}, /* RGIDW_MODID[569]:ECMTOP3*/ + [539] = {0xE7752400U, 0x00000002U}, /* RGIDW_MODID[570]:ARSD00*/ + /* After setting */ /* RGIDW_MODID[571]:ARSD01*/ + /* After setting */ /* RGIDW_MODID[572]:ARSD02*/ + [540] = {0xE775240CU, 0x00000001U}, /* RGIDW_MODID[573]:ARSD03*/ + [541] = {0xE7752410U, 0x00000002U}, /* RGIDW_MODID[574]:ARSD04*/ + [542] = {0xE7752414U, 0x00000001U}, /* RGIDW_MODID[575]:ARSD05*/ + [543] = {0xE7752418U, 0x00000002U}, /* RGIDW_MODID[576]:ARSD06*/ + [544] = {0xE775241CU, 0x0000004AU}, /* RGIDW_MODID[577]:AXIFRAY*/ + [545] = {0xE7752428U, 0x0000004FU}, /* RGIDW_MODID[578]:AXIRPC*/ + [546] = {0xE775242CU, 0x0000000FU}, /* RGIDW_MODID[579]:AXISDHI0*/ + [547] = {0xE7752430U, 0x00000002U}, /* RGIDW_MODID[580]:ARSD07*/ + [548] = {0xE7752434U, 0x00000000U}, /* RGIDW_MODID[581]:ARSD08*/ + [549] = {0xE7752438U, 0x00000002U}, /* RGIDW_MODID[582]:ARSP00*/ + /* After setting */ /* RGIDW_MODID[583]:ARSP01*/ + /* After setting */ /* RGIDW_MODID[584]:ARSP02*/ + [550] = {0xE7752444U, 0x00000001U}, /* RGIDW_MODID[585]:ARSP03*/ + [551] = {0xE7752448U, 0x00000002U}, /* RGIDW_MODID[586]:ARSP04*/ + [552] = {0xE775244CU, 0x00000001U}, /* RGIDW_MODID[587]:ARSP05*/ + [553] = {0xE7752450U, 0x00000002U}, /* RGIDW_MODID[588]:ARSP06*/ + [554] = {0xE7752454U, 0x00000002U}, /* RGIDW_MODID[589]:ARSP07*/ + [555] = {0xE7752458U, 0x00000000U}, /* RGIDW_MODID[590]:ARSP08*/ + [556] = {0xE775245CU, 0x0000004EU}, /* RGIDW_MODID[591]:IPMMUDS001*/ + [557] = {0xE7752460U, 0x0000000AU}, /* RGIDW_MODID[592]:CKMPER0*/ + [558] = {0xE7752464U, 0x0000000AU}, /* RGIDW_MODID[593]:ECMPER0*/ + [559] = {0xE7752468U, 0x0000000EU}, /* RGIDW_MODID[594]:FBAPER0*/ + [560] = {0xE775246CU, 0x0000004EU}, /* RGIDW_MODID[595]:FSO0*/ + [561] = {0xE7752470U, 0x0000004EU}, /* RGIDW_MODID[596]:FSO1*/ + [562] = {0xE7752474U, 0x0000004EU}, /* RGIDW_MODID[597]:FSO10*/ + [563] = {0xE7752478U, 0x0000004EU}, /* RGIDW_MODID[598]:FSO2*/ + [564] = {0xE775247CU, 0x0000004EU}, /* RGIDW_MODID[599]:FSO3*/ + [565] = {0xE7752480U, 0x0000004EU}, /* RGIDW_MODID[600]:FSO4*/ + [566] = {0xE7752484U, 0x0000004EU}, /* RGIDW_MODID[601]:FSO5*/ + [567] = {0xE7752488U, 0x0000004EU}, /* RGIDW_MODID[602]:FSO6*/ + [568] = {0xE775248CU, 0x0000004EU}, /* RGIDW_MODID[603]:FSO7*/ + [569] = {0xE7752490U, 0x0000004EU}, /* RGIDW_MODID[604]:FSO8*/ + [570] = {0xE7752494U, 0x0000004EU}, /* RGIDW_MODID[605]:FSO9*/ + [571] = {0xE7752498U, 0x0000002CU}, /* RGIDW_MODID[606]:ADG*/ + [572] = {0xE775249CU, 0x0000000AU}, /* RGIDW_MODID[607]:ECMSD0*/ + [573] = {0xE77524A0U, 0x0000004EU}, /* RGIDW_MODID[608]:IPMMUDS010*/ + [574] = {0xE77524A4U, 0x0000004EU}, /* RGIDW_MODID[609]:IPMMUDS011*/ + [575] = {0xE77524A8U, 0x0000004EU}, /* RGIDW_MODID[610]:I2C0*/ + [576] = {0xE77524ACU, 0x0000004EU}, /* RGIDW_MODID[611]:I2C1*/ + [577] = {0xE77524B0U, 0x0000004EU}, /* RGIDW_MODID[612]:I2C2*/ + [578] = {0xE77524B4U, 0x0000004EU}, /* RGIDW_MODID[613]:I2C3*/ + [579] = {0xE77524C0U, 0x0000004EU}, /* RGIDW_MODID[614]:IPMMUDS012*/ + [580] = {0xE77524C8U, 0x0000004EU}, /* RGIDW_MODID[615]:IPMMUDS000*/ + [581] = {0xE77524CCU, 0x0000004EU}, /* RGIDW_MODID[616]:IPMMUDS013*/ + [582] = {0xE77524D0U, 0x0000004EU}, /* RGIDW_MODID[617]:IPMMUDS014*/ + [583] = {0xE77524D4U, 0x0000004EU}, /* RGIDW_MODID[618]:IPMMUDS015*/ + [584] = {0xE77524D8U, 0x0000004EU}, /* RGIDW_MODID[619]:IPMMUDS002*/ + [585] = {0xE77524DCU, 0x0000004EU}, /* RGIDW_MODID[620]:IPMMUDS003*/ + [586] = {0xE77524E0U, 0x0000004EU}, /* RGIDW_MODID[621]:IPMMUDS004*/ + [587] = {0xE77524E4U, 0x0000004EU}, /* RGIDW_MODID[622]:IPMMUDS005*/ + [588] = {0xE77524E8U, 0x0000002CU}, /* RGIDW_MODID[623]:SSI*/ + [589] = {0xE77524ECU, 0x0000004EU}, /* RGIDW_MODID[624]:IPMMUDS006*/ + [590] = {0xE77524F0U, 0x0000004EU}, /* RGIDW_MODID[625]:IPMMUDS007*/ + [591] = {0xE77524F4U, 0x0000000CU}, /* RGIDW_MODID[626]:SYDM1P*/ + [592] = {0xE77524F8U, 0x0000004EU}, /* RGIDW_MODID[627]:IPMMUDS008*/ + [593] = {0xE77524FCU, 0x0000000CU}, /* RGIDW_MODID[628]:SYDM2P*/ + [594] = {0xE7752500U, 0x0000004EU}, /* RGIDW_MODID[629]:IPMMUDS009*/ + [595] = {0xE7752640U, 0x0000000CU}, /* RGIDW_MODID[630]:SYDM100*/ + [596] = {0xE7752644U, 0x0000000CU}, /* RGIDW_MODID[631]:SYDM101*/ + [597] = {0xE7752648U, 0x0000000CU}, /* RGIDW_MODID[632]:SYDM110*/ + [598] = {0xE775264CU, 0x0000000CU}, /* RGIDW_MODID[633]:SYDM111*/ + [599] = {0xE7752650U, 0x0000000CU}, /* RGIDW_MODID[634]:SYDM112*/ + [600] = {0xE7752654U, 0x0000000CU}, /* RGIDW_MODID[635]:SYDM113*/ + [601] = {0xE7752658U, 0x0000000CU}, /* RGIDW_MODID[636]:SYDM114*/ + [602] = {0xE775265CU, 0x0000000CU}, /* RGIDW_MODID[637]:SYDM115*/ + [603] = {0xE7752660U, 0x0000000CU}, /* RGIDW_MODID[638]:SYDM102*/ + [604] = {0xE7752664U, 0x0000000CU}, /* RGIDW_MODID[639]:SYDM103*/ + [605] = {0xE7752668U, 0x0000000CU}, /* RGIDW_MODID[640]:SYDM104*/ + [606] = {0xE775266CU, 0x0000000CU}, /* RGIDW_MODID[641]:SYDM105*/ + [607] = {0xE7752670U, 0x0000000CU}, /* RGIDW_MODID[642]:SYDM106*/ + [608] = {0xE7752674U, 0x0000000CU}, /* RGIDW_MODID[643]:SYDM107*/ + [609] = {0xE7752678U, 0x0000000CU}, /* RGIDW_MODID[644]:SYDM108*/ + [610] = {0xE775267CU, 0x0000000CU}, /* RGIDW_MODID[645]:SYDM109*/ + [611] = {0xE7752680U, 0x0000000CU}, /* RGIDW_MODID[646]:SYDM200*/ + [612] = {0xE7752684U, 0x0000000CU}, /* RGIDW_MODID[647]:SYDM201*/ + [613] = {0xE7752688U, 0x0000000CU}, /* RGIDW_MODID[648]:SYDM210*/ + [614] = {0xE775268CU, 0x0000000CU}, /* RGIDW_MODID[649]:SYDM211*/ + [615] = {0xE7752690U, 0x0000000CU}, /* RGIDW_MODID[650]:SYDM212*/ + [616] = {0xE7752694U, 0x0000000CU}, /* RGIDW_MODID[651]:SYDM213*/ + [617] = {0xE7752698U, 0x0000000CU}, /* RGIDW_MODID[652]:SYDM214*/ + [618] = {0xE775269CU, 0x0000000CU}, /* RGIDW_MODID[653]:SYDM215*/ + [619] = {0xE77526A0U, 0x0000000CU}, /* RGIDW_MODID[654]:SYDM202*/ + [620] = {0xE77526A4U, 0x0000000CU}, /* RGIDW_MODID[655]:SYDM203*/ + [621] = {0xE77526A8U, 0x0000000CU}, /* RGIDW_MODID[656]:SYDM204*/ + [622] = {0xE77526ACU, 0x0000000CU}, /* RGIDW_MODID[657]:SYDM205*/ + [623] = {0xE77526B0U, 0x0000000CU}, /* RGIDW_MODID[658]:SYDM206*/ + [624] = {0xE77526B4U, 0x0000000CU}, /* RGIDW_MODID[659]:SYDM207*/ + [625] = {0xE77526B8U, 0x0000000CU}, /* RGIDW_MODID[660]:SYDM208*/ + [626] = {0xE77526BCU, 0x0000000CU}, /* RGIDW_MODID[661]:SYDM209*/ + [627] = {0xFE682400U, 0x00000002U}, /* RGIDW_MODID[662]:ARVC0*/ + /* After setting */ /* RGIDW_MODID[663]:ARVC1*/ + /* After setting */ /* RGIDW_MODID[664]:ARVC2*/ + [628] = {0xFE68240CU, 0x00000001U}, /* RGIDW_MODID[665]:ARVC3*/ + [629] = {0xFE682410U, 0x0000000EU}, /* RGIDW_MODID[666]:AXIFBABUSVC*/ + [630] = {0xFE682414U, 0x00000002U}, /* RGIDW_MODID[667]:ARVC4*/ + [631] = {0xFE682418U, 0x00000001U}, /* RGIDW_MODID[668]:ARVC5*/ + [632] = {0xFE68241CU, 0x00000002U}, /* RGIDW_MODID[669]:ARVC6*/ + [633] = {0xFE682420U, 0x00000002U}, /* RGIDW_MODID[670]:ARVC7*/ + [634] = {0xFE682424U, 0x00000000U}, /* RGIDW_MODID[671]:ARVC8*/ + [635] = {0xFE68242CU, 0x0000000AU}, /* RGIDW_MODID[672]:ECMVC0*/ + [636] = {0xFE682434U, 0x0000004EU}, /* RGIDW_MODID[673]:IMR0*/ + [637] = {0xFE682438U, 0x0000004EU}, /* RGIDW_MODID[674]:IMR1*/ + [638] = {0xFE68243CU, 0x0000004EU}, /* RGIDW_MODID[675]:IPMMUVC01*/ + [639] = {0xFE682440U, 0x0000004EU}, /* RGIDW_MODID[676]:IPMMUVC10*/ + [640] = {0xFE682444U, 0x0000000CU}, /* RGIDW_MODID[677]:IMS0*/ + [641] = {0xFE682448U, 0x0000000CU}, /* RGIDW_MODID[678]:IMS1*/ + [642] = {0xFE68244CU, 0x0000004EU}, /* RGIDW_MODID[679]:IPMMUVC00*/ + [643] = {0xFE682450U, 0x0000004EU}, /* RGIDW_MODID[680]:IPMMUVC11*/ + [644] = {0xFE682454U, 0x0000004EU}, /* RGIDW_MODID[681]:IPMMUVC12*/ + [645] = {0xFE682458U, 0x0000004EU}, /* RGIDW_MODID[682]:IPMMUVC13*/ + [646] = {0xFE68245CU, 0x0000004EU}, /* RGIDW_MODID[683]:IPMMUVC14*/ + [647] = {0xFE682460U, 0x0000004EU}, /* RGIDW_MODID[684]:IPMMUVC15*/ + [648] = {0xFE682464U, 0x0000004EU}, /* RGIDW_MODID[685]:IPMMUVC02*/ + [649] = {0xFE682468U, 0x0000004EU}, /* RGIDW_MODID[686]:IPMMUVC03*/ + [650] = {0xFE68246CU, 0x0000004EU}, /* RGIDW_MODID[687]:IPMMUVC04*/ + [651] = {0xFE682470U, 0x0000004EU}, /* RGIDW_MODID[688]:IPMMUVC05*/ + [652] = {0xFE682474U, 0x0000004EU}, /* RGIDW_MODID[689]:IPMMUVC06*/ + [653] = {0xFE682478U, 0x0000004EU}, /* RGIDW_MODID[690]:IPMMUVC07*/ + [654] = {0xFE68247CU, 0x0000004EU}, /* RGIDW_MODID[691]:IPMMUVC08*/ + [655] = {0xFE682480U, 0x0000004EU}, /* RGIDW_MODID[692]:IPMMUVC09*/ + [656] = {0xFE682484U, 0x00000028U}, /* RGIDW_MODID[693]:IV1ES*/ + [657] = {0xFEBE2400U, 0x0000004EU}, /* RGIDW_MODID[694]:CSITOP0*/ + [658] = {0xFEBE2404U, 0x00000002U}, /* RGIDW_MODID[695]:ARVI10*/ + /* After setting */ /* RGIDW_MODID[696]:ARVI11*/ + /* After setting */ /* RGIDW_MODID[697]:ARVI12*/ + [659] = {0xFEBE2410U, 0x00000001U}, /* RGIDW_MODID[698]:ARVI13*/ + [660] = {0xFEBE2414U, 0x00000002U}, /* RGIDW_MODID[699]:ARVI14*/ + [661] = {0xFEBE2418U, 0x00000001U}, /* RGIDW_MODID[700]:ARVI15*/ + [662] = {0xFEBE241CU, 0x00000002U}, /* RGIDW_MODID[701]:ARVI16*/ + [663] = {0xFEBE2420U, 0x00000002U}, /* RGIDW_MODID[702]:ARVI17*/ + [664] = {0xFEBE2424U, 0x00000000U}, /* RGIDW_MODID[703]:ARVI18*/ + [665] = {0xFEBE242CU, 0x0000004EU}, /* RGIDW_MODID[704]:CSITOP1*/ + [666] = {0xFEBE2434U, 0x0000004EU}, /* RGIDW_MODID[705]:DSITLINK0*/ + [667] = {0xFEBE243CU, 0x0000000AU}, /* RGIDW_MODID[706]:ECMVIO1*/ + [668] = {0xFEBE2444U, 0x0000004EU}, /* RGIDW_MODID[707]:IPMMUVI001*/ + [669] = {0xFEBE2448U, 0x0000000CU}, /* RGIDW_MODID[708]:FCPVX0*/ + [670] = {0xFEBE2458U, 0x0000004EU}, /* RGIDW_MODID[709]:IPMMUVI000*/ + [671] = {0xFEBE245CU, 0x0000004EU}, /* RGIDW_MODID[710]:IPMMUVI100*/ + [672] = {0xFEBE2460U, 0x0000004EU}, /* RGIDW_MODID[711]:IPMMUVI010*/ + [673] = {0xFEBE2464U, 0x0000004EU}, /* RGIDW_MODID[712]:IPMMUVI011*/ + [674] = {0xFEBE2468U, 0x0000004EU}, /* RGIDW_MODID[713]:VSPX0*/ + [675] = {0xFEBE2478U, 0x0000004EU}, /* RGIDW_MODID[714]:IPMMUVI012*/ + [676] = {0xFEBE247CU, 0x0000004EU}, /* RGIDW_MODID[715]:IPMMUVI013*/ + [677] = {0xFEBE2480U, 0x0000004EU}, /* RGIDW_MODID[716]:IPMMUVI014*/ + [678] = {0xFEBE2484U, 0x0000004EU}, /* RGIDW_MODID[717]:IPMMUVI015*/ + [679] = {0xFEBE2488U, 0x0000004EU}, /* RGIDW_MODID[718]:IPMMUVI002*/ + [680] = {0xFEBE248CU, 0x0000004EU}, /* RGIDW_MODID[719]:IPMMUVI003*/ + [681] = {0xFEBE2490U, 0x0000004EU}, /* RGIDW_MODID[720]:IPMMUVI004*/ + [682] = {0xFEBE2494U, 0x0000004EU}, /* RGIDW_MODID[721]:IPMMUVI005*/ + [683] = {0xFEBE2498U, 0x0000004EU}, /* RGIDW_MODID[722]:IPMMUVI006*/ + [684] = {0xFEBE249CU, 0x0000004EU}, /* RGIDW_MODID[723]:IPMMUVI007*/ + [685] = {0xFEBE24A0U, 0x0000004EU}, /* RGIDW_MODID[724]:IPMMUVI008*/ + [686] = {0xFEBE24A4U, 0x0000004EU}, /* RGIDW_MODID[725]:IPMMUVI009*/ + [687] = {0xFEBE24A8U, 0x0000004EU}, /* RGIDW_MODID[726]:IPMMUVI101*/ + [688] = {0xFEBE24ACU, 0x0000004EU}, /* RGIDW_MODID[727]:IPMMUVI110*/ + [689] = {0xFEBE24B0U, 0x0000004EU}, /* RGIDW_MODID[728]:IPMMUVI111*/ + [690] = {0xFEBE24B4U, 0x0000004EU}, /* RGIDW_MODID[729]:IPMMUVI112*/ + [691] = {0xFEBE24B8U, 0x0000004EU}, /* RGIDW_MODID[730]:IPMMUVI113*/ + [692] = {0xFEBE24BCU, 0x0000004EU}, /* RGIDW_MODID[731]:IPMMUVI114*/ + [693] = {0xFEBE24C0U, 0x0000004EU}, /* RGIDW_MODID[732]:IPMMUVI115*/ + [694] = {0xFEBE24C4U, 0x0000004EU}, /* RGIDW_MODID[733]:IPMMUVI102*/ + [695] = {0xFEBE24C8U, 0x0000004EU}, /* RGIDW_MODID[734]:IPMMUVI103*/ + [696] = {0xFEBE24CCU, 0x0000004EU}, /* RGIDW_MODID[735]:IPMMUVI104*/ + [697] = {0xFEBE24D0U, 0x0000004EU}, /* RGIDW_MODID[736]:IPMMUVI105*/ + [698] = {0xFEBE24D4U, 0x0000004EU}, /* RGIDW_MODID[737]:IPMMUVI106*/ + [699] = {0xFEBE24D8U, 0x0000004EU}, /* RGIDW_MODID[738]:IPMMUVI107*/ + [700] = {0xFEBE24DCU, 0x0000004EU}, /* RGIDW_MODID[739]:IPMMUVI108*/ + [701] = {0xFEBE24E0U, 0x0000004EU}, /* RGIDW_MODID[740]:IPMMUVI109*/ + [702] = {0xFEBE2504U, 0x0000000EU}, /* RGIDW_MODID[741]:AXIFBABUSVIO*/ + [703] = {0xFEBF2400U, 0x00000002U}, /* RGIDW_MODID[742]:ARVI0*/ + /* After setting */ /* RGIDW_MODID[743]:ARVI1*/ + /* After setting */ /* RGIDW_MODID[744]:ARVI2*/ + [704] = {0xFEBF240CU, 0x00000001U}, /* RGIDW_MODID[745]:ARVI3*/ + [705] = {0xFEBF2410U, 0x00000002U}, /* RGIDW_MODID[746]:ARVI4*/ + [706] = {0xFEBF2414U, 0x00000001U}, /* RGIDW_MODID[747]:ARVI5*/ + [707] = {0xFEBF2418U, 0x00000002U}, /* RGIDW_MODID[748]:ARVI6*/ + [708] = {0xFEBF241CU, 0x00000002U}, /* RGIDW_MODID[749]:ARVI7*/ + [709] = {0xFEBF2420U, 0x00000000U}, /* RGIDW_MODID[750]:ARVI8*/ + [710] = {0xFEBF2424U, 0x0000000AU}, /* RGIDW_MODID[751]:ECMVIO0*/ + [711] = {0xFEBF2428U, 0x0000004EU}, /* RGIDW_MODID[752]:ISP0*/ + [712] = {0xFEBF242CU, 0x0000004EU}, /* RGIDW_MODID[753]:ISP0CORE*/ + [713] = {0xFEBF2430U, 0x0000004EU}, /* RGIDW_MODID[754]:ISP1*/ + [714] = {0xFEBF2454U, 0x0000004EU}, /* RGIDW_MODID[755]:VIN00*/ + [715] = {0xFEBF2458U, 0x0000004EU}, /* RGIDW_MODID[756]:VIN01*/ + [716] = {0xFEBF245CU, 0x0000004EU}, /* RGIDW_MODID[757]:VIN02*/ + [717] = {0xFEBF2460U, 0x0000004EU}, /* RGIDW_MODID[758]:VIN03*/ + [718] = {0xFEBF2464U, 0x0000004EU}, /* RGIDW_MODID[759]:VIN04*/ + [719] = {0xFEBF2468U, 0x0000004EU}, /* RGIDW_MODID[760]:VIN05*/ + [720] = {0xFEBF246CU, 0x0000004EU}, /* RGIDW_MODID[761]:VIN06*/ + [721] = {0xFEBF2470U, 0x0000004EU}, /* RGIDW_MODID[762]:VIN07*/ + [722] = {0xFEBF2474U, 0x0000004EU}, /* RGIDW_MODID[763]:VIN10*/ + [723] = {0xFEBF2478U, 0x0000004EU}, /* RGIDW_MODID[764]:VIN11*/ + [724] = {0xFEBF247CU, 0x0000004EU}, /* RGIDW_MODID[765]:VIN12*/ + [725] = {0xFEBF2480U, 0x0000004EU}, /* RGIDW_MODID[766]:VIN13*/ + [726] = {0xFEBF2484U, 0x0000004EU}, /* RGIDW_MODID[767]:VIN14*/ + [727] = {0xFEBF2488U, 0x0000004EU}, /* RGIDW_MODID[768]:VIN15*/ + [728] = {0xFEBF248CU, 0x0000004EU}, /* RGIDW_MODID[769]:VIN16*/ + [729] = {0xFEBF2490U, 0x0000004EU}, /* RGIDW_MODID[770]:VIN17*/ + [730] = {0xE7B12400U, 0x00000002U}, /* RGIDW_MODID[771]:ARVIP00*/ + /* After setting */ /* RGIDW_MODID[772]:ARVIP01*/ + /* After setting */ /* RGIDW_MODID[773]:ARVIP02*/ + [731] = {0xE7B1240CU, 0x00000001U}, /* RGIDW_MODID[774]:ARVIP03*/ + [732] = {0xE7B12410U, 0x0000000EU}, /* RGIDW_MODID[775]:AXIFBABUSVIP0*/ + [733] = {0xE7B12414U, 0x00000002U}, /* RGIDW_MODID[776]:ARVIP04*/ + [734] = {0xE7B12418U, 0x00000001U}, /* RGIDW_MODID[777]:ARVIP05*/ + [735] = {0xE7B1241CU, 0x00000002U}, /* RGIDW_MODID[778]:ARVIP06*/ + [736] = {0xE7B12420U, 0x00000002U}, /* RGIDW_MODID[779]:ARVIP07*/ + [737] = {0xE7B12424U, 0x00000000U}, /* RGIDW_MODID[780]:ARVIP08*/ + [738] = {0xE7B1242CU, 0x0000000AU}, /* RGIDW_MODID[781]:ECMVIP0*/ + [739] = {0xE7B12430U, 0x0000004EU}, /* RGIDW_MODID[782]:IPMMUVIP000*/ + [740] = {0xE7B12438U, 0x0000004EU}, /* RGIDW_MODID[783]:SMPO0*/ + [741] = {0xE7B1243CU, 0x0000004EU}, /* RGIDW_MODID[784]:SMPS0*/ + [742] = {0xE7B12440U, 0x0000004EU}, /* RGIDW_MODID[785]:UMFL0*/ + [743] = {0xE7B12444U, 0x0000004EU}, /* RGIDW_MODID[786]:IPMMUVIP001*/ + [744] = {0xE7B12448U, 0x0000004EU}, /* RGIDW_MODID[787]:IPMMUVIP010*/ + [745] = {0xE7B1244CU, 0x0000004EU}, /* RGIDW_MODID[788]:IPMMUVIP011*/ + [746] = {0xE7B12450U, 0x0000004EU}, /* RGIDW_MODID[789]:UMFL0M_W*/ + [747] = {0xE7B12454U, 0x0000004EU}, /* RGIDW_MODID[790]:IPMMUVIP012*/ + [748] = {0xE7B12458U, 0x0000004EU}, /* RGIDW_MODID[791]:IPMMUVIP013*/ + [749] = {0xE7B1245CU, 0x0000004EU}, /* RGIDW_MODID[792]:IPMMUVIP014*/ + [750] = {0xE7B12460U, 0x0000004EU}, /* RGIDW_MODID[793]:IPMMUVIP015*/ + [751] = {0xE7B12464U, 0x0000004EU}, /* RGIDW_MODID[794]:IPMMUVIP002*/ + [752] = {0xE7B12468U, 0x0000004EU}, /* RGIDW_MODID[795]:IPMMUVIP003*/ + [753] = {0xE7B1246CU, 0x0000004EU}, /* RGIDW_MODID[796]:IPMMUVIP004*/ + [754] = {0xE7B12470U, 0x0000004EU}, /* RGIDW_MODID[797]:IPMMUVIP005*/ + [755] = {0xE7B12474U, 0x0000004EU}, /* RGIDW_MODID[798]:IPMMUVIP006*/ + [756] = {0xE7B12478U, 0x0000004EU}, /* RGIDW_MODID[799]:IPMMUVIP007*/ + [757] = {0xE7B1247CU, 0x0000004EU}, /* RGIDW_MODID[800]:IPMMUVIP008*/ + [758] = {0xE7B12480U, 0x0000004EU}, /* RGIDW_MODID[801]:IPMMUVIP009*/ + [759] = {0xFF8824A0U, 0x00000002U}, /* RGIDW_MODID[802]:ARDSP0*/ + /* After setting */ /* RGIDW_MODID[803]:ARDSP1*/ + /* After setting */ /* RGIDW_MODID[804]:ARDSP2*/ + [760] = {0xFF8824ACU, 0x00000001U}, /* RGIDW_MODID[805]:ARDSP3*/ + [761] = {0xFF8824B0U, 0x00000002U}, /* RGIDW_MODID[806]:ARDSP4*/ + [762] = {0xFF8824B4U, 0x00000001U}, /* RGIDW_MODID[807]:ARDSP5*/ + [763] = {0xFF8824B8U, 0x00000002U}, /* RGIDW_MODID[808]:ARDSP6*/ + [764] = {0xFF8824BCU, 0x00000002U}, /* RGIDW_MODID[809]:ARDSP7*/ + [765] = {0xFF8824C0U, 0x0000000AU}, /* RGIDW_MODID[810]:ECMDSP*/ + [766] = {0xFF882490U, 0x0000000CU}, /* RGIDW_MODID[811]:AXIDSP0*/ + [767] = {0xFF882494U, 0x0000000CU}, /* RGIDW_MODID[812]:AXIDSP1*/ + [768] = {0xFF882498U, 0x0000000CU}, /* RGIDW_MODID[813]:AXIDSP2*/ + [769] = {0xFF88249CU, 0x0000000CU}, /* RGIDW_MODID[814]:AXIDSP3*/ + [771] = {0xE67B969CU, 0x00000000U}, /* RGIDW_MODID[815]:ARCC*/ + [770] = {0xE67B96B0U, 0x00000000U}, /* RGIDW_MODID[816]:ARRTRAM*/ + [772] = {0xE7752424U, 0x00000000U}, /* RGIDW_MODID[817]:RSV0*/ + [773] = {0xE7B1250CU, 0x00000004U}, /* RGIDW_MODID[818]:PAP*/ + [774] = {0xFF8824C4U, 0x0000004EU}, /* RGIDW_MODID[819]:IMPM0100*/ + [775] = {0xFF8824C8U, 0x0000004EU}, /* RGIDW_MODID[820]:IMPM0101*/ + [776] = {0xFF8824CCU, 0x0000004EU}, /* RGIDW_MODID[821]:IMPM0102*/ + [777] = {0xFF8824D0U, 0x0000004EU}, /* RGIDW_MODID[822]:IMPM0103*/ + [778] = {0xFF8824D4U, 0x0000004EU}, /* RGIDW_MODID[823]:IMPM0104*/ + [779] = {0xFF8824D8U, 0x0000004EU}, /* RGIDW_MODID[824]:IMPM0105*/ + [780] = {0xFF8824DCU, 0x0000004EU}, /* RGIDW_MODID[825]:IMPM0106*/ + [781] = {0xFF8824E0U, 0x0000004EU}, /* RGIDW_MODID[826]:IMPM0107*/ + [782] = {0xFF8824E4U, 0x0000004EU}, /* RGIDW_MODID[827]:IMPM0200*/ + [783] = {0xFF8824E8U, 0x0000004EU}, /* RGIDW_MODID[828]:IMPM0201*/ + [784] = {0xFF8824ECU, 0x0000004EU}, /* RGIDW_MODID[829]:IMPS0000*/ + [785] = {0xFF8824F0U, 0x0000004EU}, /* RGIDW_MODID[830]:IMPS0001*/ + [786] = {0xFF8824F4U, 0x0000004EU}, /* RGIDW_MODID[831]:IMPS0002*/ + [787] = {0xFF8824F8U, 0x0000004EU}, /* RGIDW_MODID[832]:IMPS0003*/ + [788] = {0xFF8824FCU, 0x0000004EU}, /* RGIDW_MODID[833]:IMPS0100*/ + [789] = {0xFF882500U, 0x0000004EU}, /* RGIDW_MODID[834]:IMPS0101*/ + [790] = {0xFF882504U, 0x0000004EU}, /* RGIDW_MODID[835]:IMPS0102*/ + [791] = {0xFF882508U, 0x0000004EU}, /* RGIDW_MODID[836]:IMPS0103*/ + [792] = {0xFF88250CU, 0x0000004EU}, /* RGIDW_MODID[837]:IMPS0104*/ + [793] = {0xFF882510U, 0x0000004EU}, /* RGIDW_MODID[838]:IMPS0105*/ + [794] = {0xFF882514U, 0x0000004EU}, /* RGIDW_MODID[839]:IMPS0106*/ + [795] = {0xFF882518U, 0x0000004EU}, /* RGIDW_MODID[840]:IMPS0107*/ + [796] = {0xFF88251CU, 0x0000004EU}, /* RGIDW_MODID[841]:IMPS0108*/ + [797] = {0xFF882520U, 0x0000004EU}, /* RGIDW_MODID[842]:IMPS0109*/ + [798] = {0xFF882524U, 0x0000004EU}, /* RGIDW_MODID[843]:IMPS0110*/ + [799] = {0xFF882528U, 0x0000004EU}, /* RGIDW_MODID[844]:IMPS0111*/ + [800] = {0xFF88252CU, 0x0000004EU}, /* RGIDW_MODID[845]:IMPS0200*/ + [801] = {0xFF882530U, 0x0000004EU}, /* RGIDW_MODID[846]:IMPS0201*/ + [802] = {0xFF882534U, 0x0000004EU}, /* RGIDW_MODID[847]:IMPS0202*/ + [803] = {0xFEBD2428U, 0x0000000CU}, /* RGIDW_MODID[848]:DOC*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_sec_tbl" +#else +__attribute__ ((section(".rgid_sec_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[] = { + [0] = {0xFFC83400U, 0x00000000U}, /* SEC_MODID[0]:ARMGC0*/ + [1] = {0xFFC83404U, 0x00000002U}, /* SEC_MODID[1]:ARMGC1*/ + [2] = {0xFFC83408U, 0x00000002U}, /* SEC_MODID[2]:ARMGC2*/ + [3] = {0xFFC8340CU, 0x00000002U}, /* SEC_MODID[3]:ARRT00*/ + [4] = {0xFFC83410U, 0x00000002U}, /* SEC_MODID[4]:ARRT01*/ + [5] = {0xFFC83414U, 0x00000002U}, /* SEC_MODID[5]:ARRT02*/ + [6] = {0xFFC83418U, 0x00000002U}, /* SEC_MODID[6]:ARRT03*/ + [7] = {0xFFC8341CU, 0x00000002U}, /* SEC_MODID[7]:ARRT04*/ + [8] = {0xFFC83420U, 0x00000002U}, /* SEC_MODID[8]:ARRT05*/ + [9] = {0xFFC83424U, 0x00000002U}, /* SEC_MODID[9]:ARRT06*/ + [10] = {0xFFC83428U, 0x00000002U}, /* SEC_MODID[10]:ARRT07*/ + [11] = {0xFFC8342CU, 0x00000002U}, /* SEC_MODID[11]:ARRT08*/ + [12] = {0xFFC83430U, 0x00000000U}, /* SEC_MODID[12]:LIFEC0*/ + [13] = {0xFFC83434U, 0x00000002U}, /* SEC_MODID[13]:SWDT*/ + [14] = {0xFFC83438U, 0x00000002U}, /* SEC_MODID[14]:TMU0*/ + [15] = {0xFFC8343CU, 0x00000002U}, /* SEC_MODID[15]:WDT*/ + [16] = {0xFFC83440U, 0x00000002U}, /* SEC_MODID[16]:WWDT0*/ + [17] = {0xFFC83444U, 0x00000002U}, /* SEC_MODID[17]:WWDT1*/ + [18] = {0xFFC83448U, 0x00000002U}, /* SEC_MODID[18]:WWDT2*/ + [19] = {0xFFC8344CU, 0x00000002U}, /* SEC_MODID[19]:WWDT3*/ + [20] = {0xFFC83450U, 0x00000002U}, /* SEC_MODID[20]:WWDT4*/ + [21] = {0xFFC83454U, 0x00000002U}, /* SEC_MODID[21]:WWDT5*/ + [22] = {0xFFC83458U, 0x00000002U}, /* SEC_MODID[22]:WWDT6*/ + [23] = {0xFFC83468U, 0x00000002U}, /* SEC_MODID[23]:ECMRT3*/ + [24] = {0xE6003404U, 0x00000002U}, /* SEC_MODID[24]:APMU0*/ + [25] = {0xE6003408U, 0x00000002U}, /* SEC_MODID[25]:APMU1*/ + [26] = {0xE600340CU, 0x00000002U}, /* SEC_MODID[26]:APMU10*/ + [27] = {0xE6003410U, 0x00000002U}, /* SEC_MODID[27]:APMU11*/ + [28] = {0xE6003414U, 0x00000002U}, /* SEC_MODID[28]:APMU12*/ + [29] = {0xE6003418U, 0x00000002U}, /* SEC_MODID[29]:APMU13*/ + [30] = {0xE600341CU, 0x00000002U}, /* SEC_MODID[30]:APMU14*/ + [31] = {0xE6003420U, 0x00000002U}, /* SEC_MODID[31]:APMU15*/ + [32] = {0xE6003424U, 0x00000002U}, /* SEC_MODID[32]:APMU2*/ + [33] = {0xE6003428U, 0x00000002U}, /* SEC_MODID[33]:APMU3*/ + [34] = {0xE600342CU, 0x00000002U}, /* SEC_MODID[34]:APMU4*/ + [35] = {0xE6003430U, 0x00000002U}, /* SEC_MODID[35]:APMU5*/ + [36] = {0xE6003434U, 0x00000002U}, /* SEC_MODID[36]:APMU6*/ + [37] = {0xE6003438U, 0x00000002U}, /* SEC_MODID[37]:APMU7*/ + [38] = {0xE600343CU, 0x00000002U}, /* SEC_MODID[38]:APMU8*/ + [39] = {0xE6003440U, 0x00000002U}, /* SEC_MODID[39]:APMU9*/ + [40] = {0xE6003444U, 0x00000002U}, /* SEC_MODID[40]:ARS00*/ + [41] = {0xE6003448U, 0x00000002U}, /* SEC_MODID[41]:ARS01*/ + [42] = {0xE600344CU, 0x00000002U}, /* SEC_MODID[42]:ARS02*/ + [43] = {0xE6003450U, 0x00000002U}, /* SEC_MODID[43]:ARS03*/ + [44] = {0xE6003454U, 0x00000002U}, /* SEC_MODID[44]:ARS04*/ + [45] = {0xE6003458U, 0x00000002U}, /* SEC_MODID[45]:ARS05*/ + [46] = {0xE600345CU, 0x00000002U}, /* SEC_MODID[46]:ARS06*/ + [47] = {0xE6003460U, 0x00000002U}, /* SEC_MODID[47]:ARS07*/ + [48] = {0xE6003464U, 0x00000002U}, /* SEC_MODID[48]:ARS08*/ + [49] = {0xE6003468U, 0x00000002U}, /* SEC_MODID[49]:CMT0*/ + [50] = {0xE600346CU, 0x00000002U}, /* SEC_MODID[50]:CMT1*/ + [51] = {0xE6003470U, 0x00000002U}, /* SEC_MODID[51]:CMT2*/ + [52] = {0xE6003474U, 0x00000002U}, /* SEC_MODID[52]:CMT3*/ + [53] = {0xE6003478U, 0x00000002U}, /* SEC_MODID[53]:CKM*/ + [54] = {0xE600347CU, 0x00000002U}, /* SEC_MODID[54]:DBE*/ + [55] = {0xE6003480U, 0x00000002U}, /* SEC_MODID[55]:IRQC*/ + [56] = {0xE6003484U, 0x00000002U}, /* SEC_MODID[56]:ECMPS0*/ + [57] = {0xE6003488U, 0x00000002U}, /* SEC_MODID[57]:OTP0*/ + [58] = {0xE600348CU, 0x00000002U}, /* SEC_MODID[58]:OTP1*/ + [59] = {0xE600349CU, 0x00000002U}, /* SEC_MODID[59]:SCMT*/ + [60] = {0xE60034A8U, 0x00000002U}, /* SEC_MODID[60]:TSC1*/ + [61] = {0xE60034ACU, 0x00000002U}, /* SEC_MODID[61]:TSC2*/ + [62] = {0xE60034B8U, 0x00000002U}, /* SEC_MODID[62]:UCMT*/ + [63] = {0xE6003500U, 0x00000002U}, /* SEC_MODID[63]:CPG0*/ + [64] = {0xE6003504U, 0x00000002U}, /* SEC_MODID[64]:CPG1*/ + [65] = {0xE6003508U, 0x00000002U}, /* SEC_MODID[65]:CPG2*/ + [66] = {0xE600350CU, 0x00000002U}, /* SEC_MODID[66]:CPG3*/ + [67] = {0xE6003510U, 0x00000002U}, /* SEC_MODID[67]:PFC00*/ + [68] = {0xE6003514U, 0x00000002U}, /* SEC_MODID[68]:PFC01*/ + [69] = {0xE6003518U, 0x00000002U}, /* SEC_MODID[69]:PFC02*/ + [70] = {0xE600351CU, 0x00000002U}, /* SEC_MODID[70]:PFC03*/ + [71] = {0xE6003520U, 0x00000002U}, /* SEC_MODID[71]:PFC10*/ + [72] = {0xE6003524U, 0x00000002U}, /* SEC_MODID[72]:PFC11*/ + [73] = {0xE6003528U, 0x00000002U}, /* SEC_MODID[73]:PFC12*/ + [74] = {0xE600352CU, 0x00000002U}, /* SEC_MODID[74]:PFC13*/ + [75] = {0xE6003530U, 0x00000002U}, /* SEC_MODID[75]:PFC20*/ + [76] = {0xE6003534U, 0x00000002U}, /* SEC_MODID[76]:PFC21*/ + [77] = {0xE6003538U, 0x00000002U}, /* SEC_MODID[77]:PFC22*/ + [78] = {0xE600353CU, 0x00000002U}, /* SEC_MODID[78]:PFC23*/ + [79] = {0xE6003550U, 0x00000002U}, /* SEC_MODID[79]:PFCS0*/ + [80] = {0xE6003554U, 0x00000002U}, /* SEC_MODID[80]:PFCS1*/ + [81] = {0xE6003558U, 0x00000002U}, /* SEC_MODID[81]:PFCS2*/ + [82] = {0xE600355CU, 0x00000002U}, /* SEC_MODID[82]:PFCS3*/ + [83] = {0xE6003560U, 0x00000002U}, /* SEC_MODID[83]:RESET0*/ + [84] = {0xE6003564U, 0x00000002U}, /* SEC_MODID[84]:RESET1*/ + [85] = {0xE6003568U, 0x00000002U}, /* SEC_MODID[85]:RESET2*/ + [86] = {0xE600356CU, 0x00000002U}, /* SEC_MODID[86]:RESET3*/ + [87] = {0xE6003570U, 0x00000002U}, /* SEC_MODID[87]:SYS0*/ + [88] = {0xE6003574U, 0x00000002U}, /* SEC_MODID[88]:SYS1*/ + [89] = {0xE6003578U, 0x00000002U}, /* SEC_MODID[89]:SYS2*/ + [90] = {0xE600357CU, 0x00000002U}, /* SEC_MODID[90]:SYS3*/ + [91] = {0xE7763400U, 0x00000002U}, /* SEC_MODID[91]:DMAMSI0*/ + [92] = {0xE7763404U, 0x00000002U}, /* SEC_MODID[92]:DMAMSI1*/ + [93] = {0xE7763408U, 0x00000002U}, /* SEC_MODID[93]:DMAMSI2*/ + [94] = {0xE776340CU, 0x00000002U}, /* SEC_MODID[94]:DMAMSI3*/ + [95] = {0xE7763410U, 0x00000002U}, /* SEC_MODID[95]:DMAMSI4*/ + [96] = {0xE7763414U, 0x00000002U}, /* SEC_MODID[96]:DMAMSI5*/ + [97] = {0xE7763418U, 0x00000002U}, /* SEC_MODID[97]:ECMSP3*/ + [98] = {0xE7763424U, 0x00000002U}, /* SEC_MODID[98]:ARSP30*/ + [99] = {0xE7763428U, 0x00000002U}, /* SEC_MODID[99]:ARSP31*/ + [100] = {0xE776342CU, 0x00000002U}, /* SEC_MODID[100]:ARSP32*/ + [101] = {0xE7763430U, 0x00000002U}, /* SEC_MODID[101]:ARSP33*/ + [102] = {0xE7763434U, 0x00000002U}, /* SEC_MODID[102]:ARSP34*/ + [103] = {0xE7763438U, 0x00000002U}, /* SEC_MODID[103]:ARSP35*/ + [104] = {0xE776343CU, 0x00000002U}, /* SEC_MODID[104]:ARSP36*/ + [105] = {0xE7763440U, 0x00000002U}, /* SEC_MODID[105]:ARSP37*/ + [106] = {0xE7763444U, 0x00000002U}, /* SEC_MODID[106]:ARSP38*/ + [107] = {0xE7763448U, 0x00000002U}, /* SEC_MODID[107]:MSI0*/ + [108] = {0xE776344CU, 0x00000002U}, /* SEC_MODID[108]:MSI1*/ + [109] = {0xE7763450U, 0x00000002U}, /* SEC_MODID[109]:MSI2*/ + [110] = {0xE7763454U, 0x00000002U}, /* SEC_MODID[110]:MSI3*/ + [111] = {0xE7763458U, 0x00000002U}, /* SEC_MODID[111]:MSI4*/ + [112] = {0xE776345CU, 0x00000002U}, /* SEC_MODID[112]:MSI5*/ + [113] = {0xE7793400U, 0x00000002U}, /* SEC_MODID[113]:ARSP40*/ + [114] = {0xE7793404U, 0x00000002U}, /* SEC_MODID[114]:ARSP41*/ + [115] = {0xE7793408U, 0x00000002U}, /* SEC_MODID[115]:ARSP42*/ + [116] = {0xE779340CU, 0x00000002U}, /* SEC_MODID[116]:ARSP43*/ + [117] = {0xE7793410U, 0x00000002U}, /* SEC_MODID[117]:ARSP44*/ + [118] = {0xE7793414U, 0x00000002U}, /* SEC_MODID[118]:ARSP45*/ + [119] = {0xE7793418U, 0x00000002U}, /* SEC_MODID[119]:ARSP46*/ + [120] = {0xE779341CU, 0x00000002U}, /* SEC_MODID[120]:ARSP47*/ + [121] = {0xE7793420U, 0x00000002U}, /* SEC_MODID[121]:ARSP48*/ + [122] = {0xE7793424U, 0x00000002U}, /* SEC_MODID[122]:DMAHSCIF0*/ + [123] = {0xE7793428U, 0x00000002U}, /* SEC_MODID[123]:DMAHSCIF1*/ + [124] = {0xE779342CU, 0x00000002U}, /* SEC_MODID[124]:DMAHSCIF2*/ + [125] = {0xE7793430U, 0x00000002U}, /* SEC_MODID[125]:DMAHSCIF3*/ + [126] = {0xE7793434U, 0x00000002U}, /* SEC_MODID[126]:DMASCIF0*/ + [127] = {0xE7793438U, 0x00000002U}, /* SEC_MODID[127]:DMASCIF1*/ + [128] = {0xE779343CU, 0x00000002U}, /* SEC_MODID[128]:DMASCIF3*/ + [129] = {0xE7793440U, 0x00000002U}, /* SEC_MODID[129]:DMASCIF4*/ + [130] = {0xE7793444U, 0x00000002U}, /* SEC_MODID[130]:ECMSP4*/ + [131] = {0xE7793448U, 0x00000002U}, /* SEC_MODID[131]:HSCIF0*/ + [132] = {0xE779344CU, 0x00000002U}, /* SEC_MODID[132]:HSCIF1*/ + [133] = {0xE7793450U, 0x00000002U}, /* SEC_MODID[133]:HSCIF2*/ + [134] = {0xE7793454U, 0x00000002U}, /* SEC_MODID[134]:HSCIF3*/ + [135] = {0xE7793458U, 0x00000002U}, /* SEC_MODID[135]:SCIF0*/ + [136] = {0xE779345CU, 0x00000002U}, /* SEC_MODID[136]:SCIF1*/ + [137] = {0xE7793460U, 0x00000002U}, /* SEC_MODID[137]:SCIF3*/ + [138] = {0xE7793464U, 0x00000002U}, /* SEC_MODID[138]:SCIF4*/ + [139] = {0xE7793468U, 0x00000002U}, /* SEC_MODID[139]:TMU1*/ + [140] = {0xE779346CU, 0x00000002U}, /* SEC_MODID[140]:TMU2*/ + [141] = {0xE7793470U, 0x00000002U}, /* SEC_MODID[141]:TMU3*/ + [142] = {0xE7793474U, 0x00000002U}, /* SEC_MODID[142]:TMU4*/ + [143] = {0xE7793478U, 0x00000002U}, /* SEC_MODID[143]:CANFD*/ + [144] = {0xE779347CU, 0x00000002U}, /* SEC_MODID[144]:DMACANFD*/ + [145] = {0xE7793480U, 0x00000002U}, /* SEC_MODID[145]:DMATPU0*/ + [146] = {0xE7793484U, 0x00000002U}, /* SEC_MODID[146]:PWM0*/ + [147] = {0xE7793488U, 0x00000002U}, /* SEC_MODID[147]:PWM1*/ + [148] = {0xE779348CU, 0x00000002U}, /* SEC_MODID[148]:PWM2*/ + [149] = {0xE7793490U, 0x00000002U}, /* SEC_MODID[149]:PWM3*/ + [150] = {0xE7793494U, 0x00000002U}, /* SEC_MODID[150]:PWM4*/ + [151] = {0xE77934ACU, 0x00000002U}, /* SEC_MODID[151]:TPU0*/ + [152] = {0xFEBD3400U, 0x00000002U}, /* SEC_MODID[152]:ARVI40*/ + [153] = {0xFEBD3404U, 0x00000002U}, /* SEC_MODID[153]:ARVI41*/ + [154] = {0xFEBD3408U, 0x00000002U}, /* SEC_MODID[154]:ARVI42*/ + [155] = {0xFEBD340CU, 0x00000002U}, /* SEC_MODID[155]:ARVI43*/ + [156] = {0xFEBD3410U, 0x00000002U}, /* SEC_MODID[156]:ARVI44*/ + [157] = {0xFEBD3414U, 0x00000002U}, /* SEC_MODID[157]:ARVI45*/ + [158] = {0xFEBD3418U, 0x00000002U}, /* SEC_MODID[158]:ARVI46*/ + [159] = {0xFEBD341CU, 0x00000002U}, /* SEC_MODID[159]:ARVI47*/ + [160] = {0xFEBD3420U, 0x00000002U}, /* SEC_MODID[160]:ARVI48*/ + [161] = {0xFEBD3424U, 0x00000002U}, /* SEC_MODID[161]:DIS0*/ + [162] = {0xFEBD3430U, 0x00000002U}, /* SEC_MODID[162]:ECMVIO2*/ + [163] = {0xFEBD3434U, 0x00000002U}, /* SEC_MODID[163]:FCPVD0*/ + [164] = {0xFEBD343CU, 0x00000002U}, /* SEC_MODID[164]:VSPD0*/ + [165] = {0xE6583400U, 0x00000002U}, /* SEC_MODID[165]:CKMHSC*/ + [166] = {0xE6583404U, 0x00000002U}, /* SEC_MODID[166]:AXIPCI001*/ + [167] = {0xE6583408U, 0x00000002U}, /* SEC_MODID[167]:AXIPCI002*/ + [168] = {0xE658340CU, 0x00000002U}, /* SEC_MODID[168]:AXIPCI003*/ + [169] = {0xE6583414U, 0x00000002U}, /* SEC_MODID[169]:AXIPCI005*/ + [170] = {0xE6583418U, 0x00000002U}, /* SEC_MODID[170]:AXIPCI006*/ + [171] = {0xE658341CU, 0x00000002U}, /* SEC_MODID[171]:AXIPCI007*/ + [172] = {0xE6583420U, 0x00000002U}, /* SEC_MODID[172]:AXIPCI008*/ + [173] = {0xE6583424U, 0x00000002U}, /* SEC_MODID[173]:AXIPCI009*/ + [174] = {0xE6583428U, 0x00000002U}, /* SEC_MODID[174]:AXIPCI010*/ + [175] = {0xE658342CU, 0x00000002U}, /* SEC_MODID[175]:AXIPCI011*/ + [176] = {0xE6583430U, 0x00000002U}, /* SEC_MODID[176]:AXIPCI012*/ + [177] = {0xE6583434U, 0x00000002U}, /* SEC_MODID[177]:AXIPCI013*/ + [178] = {0xE6583438U, 0x00000002U}, /* SEC_MODID[178]:AXIPCI014*/ + [179] = {0xE658343CU, 0x00000002U}, /* SEC_MODID[179]:AXIPCI015*/ + [180] = {0xE6583484U, 0x00000002U}, /* SEC_MODID[180]:GPTP*/ + [181] = {0xE6583488U, 0x00000002U}, /* SEC_MODID[181]:IPMMUHC00*/ + [182] = {0xE65834F4U, 0x00000002U}, /* SEC_MODID[182]:AXIPCI000*/ + [183] = {0xE65834F8U, 0x00000002U}, /* SEC_MODID[183]:AXIPCI004*/ + [184] = {0xE65834FCU, 0x00000002U}, /* SEC_MODID[184]:IPMMUHC01*/ + [185] = {0xE6583500U, 0x00000002U}, /* SEC_MODID[185]:AVB0*/ + [186] = {0xE6583504U, 0x00000002U}, /* SEC_MODID[186]:AVB1*/ + [187] = {0xE6583508U, 0x00000002U}, /* SEC_MODID[187]:AVB2*/ + [188] = {0xE658350CU, 0x00000002U}, /* SEC_MODID[188]:IPMMUHC10*/ + [189] = {0xE6583510U, 0x00000002U}, /* SEC_MODID[189]:IPMMUHC11*/ + [190] = {0xE6583514U, 0x00000002U}, /* SEC_MODID[190]:IPMMUHC12*/ + [191] = {0xE6583518U, 0x00000002U}, /* SEC_MODID[191]:IPMMUHC13*/ + [192] = {0xE658351CU, 0x00000002U}, /* SEC_MODID[192]:PPHY0*/ + [193] = {0xE6583524U, 0x00000002U}, /* SEC_MODID[193]:IPMMUHC14*/ + [194] = {0xE6583528U, 0x00000002U}, /* SEC_MODID[194]:IPMMUHC15*/ + [195] = {0xE658352CU, 0x00000002U}, /* SEC_MODID[195]:FBAHSC*/ + [196] = {0xE6583530U, 0x00000002U}, /* SEC_MODID[196]:IPMMUHC02*/ + [197] = {0xE6583538U, 0x00000002U}, /* SEC_MODID[197]:ECMHSC*/ + [198] = {0xE658353CU, 0x00000002U}, /* SEC_MODID[198]:ARHC0*/ + [199] = {0xE6583540U, 0x00000002U}, /* SEC_MODID[199]:ARHC1*/ + [200] = {0xE6583544U, 0x00000002U}, /* SEC_MODID[200]:ARHC2*/ + [201] = {0xE6583548U, 0x00000002U}, /* SEC_MODID[201]:ARHC3*/ + [202] = {0xE658354CU, 0x00000002U}, /* SEC_MODID[202]:ARHC4*/ + [203] = {0xE6583550U, 0x00000002U}, /* SEC_MODID[203]:ARHC5*/ + [204] = {0xE6583554U, 0x00000002U}, /* SEC_MODID[204]:ARHC6*/ + [205] = {0xE6583558U, 0x00000002U}, /* SEC_MODID[205]:ARHC7*/ + [206] = {0xE658355CU, 0x00000002U}, /* SEC_MODID[206]:ARHC8*/ + [207] = {0xE6583560U, 0x00000002U}, /* SEC_MODID[207]:IPMMUHC03*/ + [208] = {0xE6583564U, 0x00000002U}, /* SEC_MODID[208]:IPMMUHC04*/ + [209] = {0xE6583568U, 0x00000002U}, /* SEC_MODID[209]:IPMMUHC05*/ + [210] = {0xE658356CU, 0x00000002U}, /* SEC_MODID[210]:IPMMUHC06*/ + [211] = {0xE6583570U, 0x00000002U}, /* SEC_MODID[211]:IPMMUHC07*/ + [212] = {0xE6583574U, 0x00000002U}, /* SEC_MODID[212]:IPMMUHC08*/ + [213] = {0xE6583578U, 0x00000002U}, /* SEC_MODID[213]:IPMMUHC09*/ + [214] = {0xFF883400U, 0x00000002U}, /* SEC_MODID[214]:ARIMP00*/ + [215] = {0xFF883404U, 0x00000002U}, /* SEC_MODID[215]:ARIMP01*/ + [216] = {0xFF883408U, 0x00000002U}, /* SEC_MODID[216]:ARIMP02*/ + [217] = {0xFF88340CU, 0x00000002U}, /* SEC_MODID[217]:ARIMP03*/ + [218] = {0xFF883410U, 0x00000002U}, /* SEC_MODID[218]:ARIMP04*/ + [219] = {0xFF883414U, 0x00000002U}, /* SEC_MODID[219]:AXIFBABUSIR0*/ + [220] = {0xFF883418U, 0x00000002U}, /* SEC_MODID[220]:AXIFBABUSIR1*/ + [221] = {0xFF88341CU, 0x00000002U}, /* SEC_MODID[221]:AXIFBABUSIR2*/ + [222] = {0xFF883420U, 0x00000002U}, /* SEC_MODID[222]:AXIFBABUSIR3*/ + [223] = {0xFF883428U, 0x00000002U}, /* SEC_MODID[223]:AXIIMP0*/ + [224] = {0xFF883434U, 0x00000002U}, /* SEC_MODID[224]:ARIMP05*/ + [225] = {0xFF883438U, 0x00000002U}, /* SEC_MODID[225]:ARIMP06*/ + [226] = {0xFF88343CU, 0x00000002U}, /* SEC_MODID[226]:ARIMP07*/ + [227] = {0xFF883440U, 0x00000002U}, /* SEC_MODID[227]:ARIMP08*/ + [228] = {0xFF883448U, 0x00000002U}, /* SEC_MODID[228]:ECMIR*/ + [229] = {0xFF88344CU, 0x00000002U}, /* SEC_MODID[229]:DSPPS*/ + [230] = {0xFF883450U, 0x00000002U}, /* SEC_MODID[230]:IPMMUIR1*/ + [231] = {0xFF883454U, 0x00000002U}, /* SEC_MODID[231]:IPMMUIR0*/ + [232] = {0xFF883458U, 0x00000002U}, /* SEC_MODID[232]:IPMMUIR10*/ + [233] = {0xFF88345CU, 0x00000002U}, /* SEC_MODID[233]:IPMMUIR11*/ + [234] = {0xFF883460U, 0x00000002U}, /* SEC_MODID[234]:IPMMUIR12*/ + [235] = {0xFF883464U, 0x00000002U}, /* SEC_MODID[235]:IPMMUIR13*/ + [236] = {0xFF883468U, 0x00000002U}, /* SEC_MODID[236]:IPMMUIR14*/ + [237] = {0xFF88346CU, 0x00000002U}, /* SEC_MODID[237]:IPMMUIR15*/ + [238] = {0xFF883470U, 0x00000002U}, /* SEC_MODID[238]:IPMMUIR2*/ + [239] = {0xFF883474U, 0x00000002U}, /* SEC_MODID[239]:IPMMUIR3*/ + [240] = {0xFF883478U, 0x00000002U}, /* SEC_MODID[240]:IPMMUIR4*/ + [241] = {0xFF88347CU, 0x00000002U}, /* SEC_MODID[241]:IPMMUIR5*/ + [242] = {0xFF883480U, 0x00000002U}, /* SEC_MODID[242]:IPMMUIR6*/ + [243] = {0xFF883484U, 0x00000002U}, /* SEC_MODID[243]:IPMMUIR7*/ + [244] = {0xFF883488U, 0x00000002U}, /* SEC_MODID[244]:IPMMUIR8*/ + [245] = {0xFF88348CU, 0x00000002U}, /* SEC_MODID[245]:IPMMUIR9*/ + [246] = {0xFD813400U, 0x00000002U}, /* SEC_MODID[246]:ARPV0*/ + [247] = {0xFD813404U, 0x00000002U}, /* SEC_MODID[247]:ARPV1*/ + [248] = {0xFD813408U, 0x00000002U}, /* SEC_MODID[248]:AXIRGXS*/ + [249] = {0xFD81340CU, 0x00000002U}, /* SEC_MODID[249]:ARPV2*/ + [250] = {0xFD813410U, 0x00000002U}, /* SEC_MODID[250]:ARPV3*/ + [251] = {0xFD813414U, 0x00000002U}, /* SEC_MODID[251]:ARPV4*/ + [252] = {0xFD813418U, 0x00000002U}, /* SEC_MODID[252]:ARPV5*/ + [253] = {0xFD81341CU, 0x00000002U}, /* SEC_MODID[253]:ARPV6*/ + [254] = {0xFD813420U, 0x00000002U}, /* SEC_MODID[254]:ARPV7*/ + [255] = {0xFD813424U, 0x00000002U}, /* SEC_MODID[255]:ARPV8*/ + [256] = {0xFD81342CU, 0x00000002U}, /* SEC_MODID[256]:ECM3DG*/ + [257] = {0xFD813430U, 0x00000002U}, /* SEC_MODID[257]:FBAPVC*/ + [258] = {0xFD813434U, 0x00000002U}, /* SEC_MODID[258]:FBAPVD0*/ + [259] = {0xFD813438U, 0x00000002U}, /* SEC_MODID[259]:FBAPVD1*/ + [260] = {0xFD81343CU, 0x00000002U}, /* SEC_MODID[260]:FBAPVD2*/ + [261] = {0xFD813440U, 0x00000002U}, /* SEC_MODID[261]:FBAPVE*/ + [262] = {0xFD813444U, 0x00000002U}, /* SEC_MODID[262]:IPMMUPV000*/ + [263] = {0xFD813448U, 0x00000002U}, /* SEC_MODID[263]:IPMMUPV001*/ + [264] = {0xFD81344CU, 0x00000002U}, /* SEC_MODID[264]:IPMMUPV010*/ + [265] = {0xFD813450U, 0x00000002U}, /* SEC_MODID[265]:IPMMUPV011*/ + [266] = {0xFD813454U, 0x00000002U}, /* SEC_MODID[266]:IPMMUPV012*/ + [267] = {0xFD813458U, 0x00000002U}, /* SEC_MODID[267]:IPMMUPV013*/ + [268] = {0xFD81345CU, 0x00000002U}, /* SEC_MODID[268]:IPMMUPV014*/ + [269] = {0xFD813460U, 0x00000002U}, /* SEC_MODID[269]:IPMMUPV015*/ + [270] = {0xFD813464U, 0x00000002U}, /* SEC_MODID[270]:IPMMUPV002*/ + [271] = {0xFD813468U, 0x00000002U}, /* SEC_MODID[271]:IPMMUPV003*/ + [272] = {0xFD81346CU, 0x00000002U}, /* SEC_MODID[272]:IPMMUPV004*/ + [273] = {0xFD813470U, 0x00000002U}, /* SEC_MODID[273]:IPMMUPV005*/ + [274] = {0xFD813474U, 0x00000002U}, /* SEC_MODID[274]:IPMMUPV006*/ + [275] = {0xFD813478U, 0x00000002U}, /* SEC_MODID[275]:IPMMUPV007*/ + [276] = {0xFD81347CU, 0x00000002U}, /* SEC_MODID[276]:IPMMUPV008*/ + [277] = {0xFD813480U, 0x00000002U}, /* SEC_MODID[277]:IPMMUPV009*/ + [278] = {0xE6623400U, 0x00000002U}, /* SEC_MODID[278]:ARRC0*/ + [279] = {0xE6623404U, 0x00000002U}, /* SEC_MODID[279]:ARRC1*/ + [280] = {0xE6623408U, 0x00000002U}, /* SEC_MODID[280]:ARRC2*/ + [281] = {0xE662340CU, 0x00000002U}, /* SEC_MODID[281]:ARRC3*/ + [282] = {0xE6623410U, 0x00000002U}, /* SEC_MODID[282]:ARRC4*/ + [283] = {0xE6623414U, 0x00000002U}, /* SEC_MODID[283]:ARRC5*/ + [284] = {0xE6623418U, 0x00000002U}, /* SEC_MODID[284]:ARRC6*/ + [285] = {0xE662341CU, 0x00000002U}, /* SEC_MODID[285]:ARRC7*/ + [286] = {0xE6623420U, 0x00000002U}, /* SEC_MODID[286]:ARRC8*/ + [287] = {0xE6623428U, 0x00000002U}, /* SEC_MODID[287]:ICUMX*/ + [288] = {0xE662342CU, 0x00000002U}, /* SEC_MODID[288]:ECMRC*/ + [289] = {0xFFC33400U, 0x00000002U}, /* SEC_MODID[289]:DMAWCRC0*/ + [290] = {0xFFC33404U, 0x00000002U}, /* SEC_MODID[290]:DMAWCRC1*/ + [291] = {0xFFC33408U, 0x00000002U}, /* SEC_MODID[291]:DMAWCRC2*/ + [292] = {0xFFC3340CU, 0x00000002U}, /* SEC_MODID[292]:DMAWCRC3*/ + [293] = {0xFFC43400U, 0x00000002U}, /* SEC_MODID[293]:ARMREG00*/ + [294] = {0xFFC43404U, 0x00000002U}, /* SEC_MODID[294]:ARMREG01*/ + [295] = {0xFFC43408U, 0x00000002U}, /* SEC_MODID[295]:ARMREG10*/ + [296] = {0xFFC4340CU, 0x00000002U}, /* SEC_MODID[296]:ARMREG11*/ + [297] = {0xFFC43410U, 0x00000002U}, /* SEC_MODID[297]:ARMREG12*/ + [298] = {0xFFC43414U, 0x00000000U}, /* SEC_MODID[298]:ARMREG13*/ + [299] = {0xFFC43418U, 0x00000000U}, /* SEC_MODID[299]:ARMREG14*/ + [300] = {0xFFC4341CU, 0x00000002U}, /* SEC_MODID[300]:AXICR52SS0*/ + [301] = {0xFFC43420U, 0x00000002U}, /* SEC_MODID[301]:AXICSD0*/ + [302] = {0xFFC43424U, 0x00000002U}, /* SEC_MODID[302]:AXIINTAP0*/ + [303] = {0xFFC4342CU, 0x00000002U}, /* SEC_MODID[303]:AXISECROM*/ + [304] = {0xFFC43430U, 0x00000002U}, /* SEC_MODID[304]:AXISYSRAM0*/ + [305] = {0xFFC43434U, 0x00000002U}, /* SEC_MODID[305]:AXISYSRAM1*/ + [306] = {0xFFC43438U, 0x00000002U}, /* SEC_MODID[306]:ARGREG15*/ + [307] = {0xFFC4343CU, 0x00000002U}, /* SEC_MODID[307]:ARMREG2*/ + [308] = {0xFFC43440U, 0x00000002U}, /* SEC_MODID[308]:ARMREG3*/ + [309] = {0xFFC43444U, 0x00000002U}, /* SEC_MODID[309]:ARMREG4*/ + [310] = {0xFFC43448U, 0x00000002U}, /* SEC_MODID[310]:ARMREG5*/ + [311] = {0xFFC4344CU, 0x00000002U}, /* SEC_MODID[311]:ARMREG6*/ + [312] = {0xFFC43450U, 0x00000002U}, /* SEC_MODID[312]:ARMREG7*/ + [313] = {0xFFC43454U, 0x00000000U}, /* SEC_MODID[313]:ARMREG8*/ + [314] = {0xFFC43458U, 0x00000000U}, /* SEC_MODID[314]:ARMREG9*/ + [315] = {0xFFC4345CU, 0x00000002U}, /* SEC_MODID[315]:ARRD0*/ + [316] = {0xFFC43460U, 0x00000002U}, /* SEC_MODID[316]:ARRD1*/ + [317] = {0xFFC43464U, 0x00000002U}, /* SEC_MODID[317]:ARRD2*/ + [318] = {0xFFC43468U, 0x00000002U}, /* SEC_MODID[318]:ARRD3*/ + [319] = {0xFFC4346CU, 0x00000002U}, /* SEC_MODID[319]:ARRD4*/ + [320] = {0xFFC43470U, 0x00000002U}, /* SEC_MODID[320]:ARRD5*/ + [321] = {0xFFC43474U, 0x00000002U}, /* SEC_MODID[321]:ARRD6*/ + [322] = {0xFFC43478U, 0x00000002U}, /* SEC_MODID[322]:ARRD7*/ + [323] = {0xFFC4347CU, 0x00000002U}, /* SEC_MODID[323]:ARRD8*/ + [324] = {0xFFC43480U, 0x00000002U}, /* SEC_MODID[324]:ARRT0*/ + [325] = {0xFFC43484U, 0x00000002U}, /* SEC_MODID[325]:ARRT1*/ + [326] = {0xFFC43488U, 0x00000002U}, /* SEC_MODID[326]:ARRT2*/ + [327] = {0xFFC4348CU, 0x00000002U}, /* SEC_MODID[327]:ARRT3*/ + [328] = {0xFFC43490U, 0x00000002U}, /* SEC_MODID[328]:ARRT4*/ + [329] = {0xFFC43494U, 0x00000002U}, /* SEC_MODID[329]:ARRT5*/ + [330] = {0xFFC43498U, 0x00000002U}, /* SEC_MODID[330]:ARRT6*/ + [331] = {0xFFC4349CU, 0x00000002U}, /* SEC_MODID[331]:ARRT7*/ + [332] = {0xFFC434A0U, 0x00000002U}, /* SEC_MODID[332]:ARRT8*/ + [333] = {0xFFC434A4U, 0x00000002U}, /* SEC_MODID[333]:CKMRT*/ + [334] = {0xFFC434A8U, 0x00000002U}, /* SEC_MODID[334]:CRC0*/ + [335] = {0xFFC434ACU, 0x00000002U}, /* SEC_MODID[335]:CRC1*/ + [336] = {0xFFC434B0U, 0x00000002U}, /* SEC_MODID[336]:CRC2*/ + [337] = {0xFFC434B4U, 0x00000002U}, /* SEC_MODID[337]:CRC3*/ + [338] = {0xFFC434B8U, 0x00000002U}, /* SEC_MODID[338]:CSD*/ + [339] = {0xFFC434BCU, 0x00000002U}, /* SEC_MODID[339]:ECM*/ + [340] = {0xFFC434C0U, 0x00000002U}, /* SEC_MODID[340]:ECMRT*/ + [341] = {0xFFC434C4U, 0x00000002U}, /* SEC_MODID[341]:FBACR52*/ + [342] = {0xFFC434C8U, 0x00000002U}, /* SEC_MODID[342]:FBART*/ + [343] = {0xFFC434CCU, 0x00000002U}, /* SEC_MODID[343]:INTTP*/ + [344] = {0xFFC434D0U, 0x00000002U}, /* SEC_MODID[344]:IPMMURT000*/ + [345] = {0xFFC434D4U, 0x00000002U}, /* SEC_MODID[345]:IPMMURT100*/ + [346] = {0xFFC434D8U, 0x00000002U}, /* SEC_MODID[346]:KCRC4*/ + [347] = {0xFFC434DCU, 0x00000002U}, /* SEC_MODID[347]:KCRC5*/ + [348] = {0xFFC434E0U, 0x00000002U}, /* SEC_MODID[348]:KCRC6*/ + [349] = {0xFFC434E4U, 0x00000002U}, /* SEC_MODID[349]:KCRC7*/ + [350] = {0xFFC434E8U, 0x00000002U}, /* SEC_MODID[350]:MFI00*/ + [351] = {0xFFC434ECU, 0x00000002U}, /* SEC_MODID[351]:MFI01*/ + [352] = {0xFFC434F0U, 0x00000002U}, /* SEC_MODID[352]:MFI10*/ + [353] = {0xFFC434F4U, 0x00000002U}, /* SEC_MODID[353]:MFI02*/ + [354] = {0xFFC434F8U, 0x00000002U}, /* SEC_MODID[354]:MFI03*/ + [355] = {0xFFC434FCU, 0x00000002U}, /* SEC_MODID[355]:MFI04*/ + [356] = {0xFFC43500U, 0x00000002U}, /* SEC_MODID[356]:MFI05*/ + [357] = {0xFFC43504U, 0x00000002U}, /* SEC_MODID[357]:MFI06*/ + [358] = {0xFFC43508U, 0x00000002U}, /* SEC_MODID[358]:MFI07*/ + [359] = {0xFFC4350CU, 0x00000002U}, /* SEC_MODID[359]:MFI08*/ + [360] = {0xFFC43510U, 0x00000002U}, /* SEC_MODID[360]:MFI09*/ + [361] = {0xFFC43514U, 0x00000002U}, /* SEC_MODID[361]:MFI15*/ + [362] = {0xFFC43518U, 0x00000002U}, /* SEC_MODID[362]:CKMCR52*/ + [363] = {0xFFC4351CU, 0x00000002U}, /* SEC_MODID[363]:RTDM0P*/ + [364] = {0xFFC43520U, 0x00000002U}, /* SEC_MODID[364]:ECMRD*/ + [365] = {0xFFC43524U, 0x00000002U}, /* SEC_MODID[365]:RTDM1P*/ + [366] = {0xFFC43530U, 0x00000002U}, /* SEC_MODID[366]:SYSRAM10*/ + [367] = {0xFFC43538U, 0x00000000U}, /* SEC_MODID[367]:SYSRAM00*/ + [368] = {0xFFC4353CU, 0x00000002U}, /* SEC_MODID[368]:TSIPL0*/ + [369] = {0xFFC43540U, 0x00000002U}, /* SEC_MODID[369]:TSIPL1*/ + [370] = {0xFFC43544U, 0x00000002U}, /* SEC_MODID[370]:TSIPL2*/ + [371] = {0xFFC43548U, 0x00000002U}, /* SEC_MODID[371]:TSIPL3*/ + [372] = {0xFFC4354CU, 0x00000002U}, /* SEC_MODID[372]:TSIPL4*/ + [373] = {0xFFC43550U, 0x00000002U}, /* SEC_MODID[373]:TSIPL5*/ + [374] = {0xFFC43554U, 0x00000002U}, /* SEC_MODID[374]:TSIPL6*/ + [375] = {0xFFC43558U, 0x00000002U}, /* SEC_MODID[375]:TSIPL7*/ + [376] = {0xFFC4355CU, 0x00000002U}, /* SEC_MODID[376]:WCRC0*/ + [377] = {0xFFC43560U, 0x00000002U}, /* SEC_MODID[377]:WCRC1*/ + [378] = {0xFFC43564U, 0x00000002U}, /* SEC_MODID[378]:WCRC2*/ + [379] = {0xFFC43568U, 0x00000002U}, /* SEC_MODID[379]:WCRC3*/ + [380] = {0xFFC43580U, 0x00000002U}, /* SEC_MODID[380]:MFI11*/ + [381] = {0xFFC43584U, 0x00000002U}, /* SEC_MODID[381]:MFI12*/ + [382] = {0xFFC43588U, 0x00000002U}, /* SEC_MODID[382]:MFI13*/ + [383] = {0xFFC4358CU, 0x00000002U}, /* SEC_MODID[383]:MFI14*/ + [384] = {0xFFC43590U, 0x00000002U}, /* SEC_MODID[384]:IPMMURT001*/ + [385] = {0xFFC43594U, 0x00000002U}, /* SEC_MODID[385]:IPMMURT010*/ + [386] = {0xFFC43598U, 0x00000002U}, /* SEC_MODID[386]:IPMMURT011*/ + [387] = {0xFFC4359CU, 0x00000002U}, /* SEC_MODID[387]:IPMMURT012*/ + [388] = {0xFFC435A0U, 0x00000002U}, /* SEC_MODID[388]:IPMMURT013*/ + [389] = {0xFFC435A4U, 0x00000002U}, /* SEC_MODID[389]:IPMMURT014*/ + [390] = {0xFFC435A8U, 0x00000002U}, /* SEC_MODID[390]:IPMMURT015*/ + [391] = {0xFFC435ACU, 0x00000002U}, /* SEC_MODID[391]:IPMMURT002*/ + [392] = {0xFFC435B0U, 0x00000002U}, /* SEC_MODID[392]:IPMMURT003*/ + [393] = {0xFFC435B4U, 0x00000002U}, /* SEC_MODID[393]:IPMMURT004*/ + [394] = {0xFFC435B8U, 0x00000002U}, /* SEC_MODID[394]:IPMMURT005*/ + [395] = {0xFFC435BCU, 0x00000002U}, /* SEC_MODID[395]:IPMMURT006*/ + [396] = {0xFFC435C0U, 0x00000002U}, /* SEC_MODID[396]:IPMMURT007*/ + [397] = {0xFFC435C4U, 0x00000002U}, /* SEC_MODID[397]:IPMMURT008*/ + [398] = {0xFFC435C8U, 0x00000002U}, /* SEC_MODID[398]:IPMMURT009*/ + [399] = {0xFFC435CCU, 0x00000002U}, /* SEC_MODID[399]:IPKMURT101*/ + [400] = {0xFFC435D0U, 0x00000002U}, /* SEC_MODID[400]:IPMMURT110*/ + [401] = {0xFFC435D4U, 0x00000002U}, /* SEC_MODID[401]:IPMMURT111*/ + [402] = {0xFFC435D8U, 0x00000002U}, /* SEC_MODID[402]:IPMMURT112*/ + [403] = {0xFFC435DCU, 0x00000002U}, /* SEC_MODID[403]:IPMMURT113*/ + [404] = {0xFFC435E0U, 0x00000002U}, /* SEC_MODID[404]:IPMMURT114*/ + [405] = {0xFFC435E4U, 0x00000002U}, /* SEC_MODID[405]:IPMMURT115*/ + [406] = {0xFFC435E8U, 0x00000002U}, /* SEC_MODID[406]:IPMMURT102*/ + [407] = {0xFFC435ECU, 0x00000002U}, /* SEC_MODID[407]:IPMMURT103*/ + [408] = {0xFFC435F0U, 0x00000002U}, /* SEC_MODID[408]:IPMMURT104*/ + [409] = {0xFFC435F4U, 0x00000002U}, /* SEC_MODID[409]:IPMMURT105*/ + [410] = {0xFFC435F8U, 0x00000002U}, /* SEC_MODID[410]:IPMMURT106*/ + [411] = {0xFFC435FCU, 0x00000002U}, /* SEC_MODID[411]:IPMMURT107*/ + [412] = {0xFFC43600U, 0x00000002U}, /* SEC_MODID[412]:RTDM000*/ + [413] = {0xFFC43604U, 0x00000002U}, /* SEC_MODID[413]:RTDM001*/ + [414] = {0xFFC43608U, 0x00000002U}, /* SEC_MODID[414]:RTDM010*/ + [415] = {0xFFC4360CU, 0x00000002U}, /* SEC_MODID[415]:RTDM011*/ + [416] = {0xFFC43610U, 0x00000002U}, /* SEC_MODID[416]:RTDM012*/ + [417] = {0xFFC43614U, 0x00000002U}, /* SEC_MODID[417]:RTDM013*/ + [418] = {0xFFC43618U, 0x00000002U}, /* SEC_MODID[418]:RTDM014*/ + [419] = {0xFFC4361CU, 0x00000002U}, /* SEC_MODID[419]:RTDM015*/ + [420] = {0xFFC43620U, 0x00000002U}, /* SEC_MODID[420]:RTDM002*/ + [421] = {0xFFC43624U, 0x00000002U}, /* SEC_MODID[421]:RTDM003*/ + [422] = {0xFFC43628U, 0x00000002U}, /* SEC_MODID[422]:RTDM004*/ + [423] = {0xFFC4362CU, 0x00000002U}, /* SEC_MODID[423]:RTDM005*/ + [424] = {0xFFC43630U, 0x00000002U}, /* SEC_MODID[424]:RTDM006*/ + [425] = {0xFFC43634U, 0x00000002U}, /* SEC_MODID[425]:RTDM007*/ + [426] = {0xFFC43638U, 0x00000002U}, /* SEC_MODID[426]:RTDM008*/ + [427] = {0xFFC4363CU, 0x00000002U}, /* SEC_MODID[427]:RTDM009*/ + [428] = {0xFFC43640U, 0x00000002U}, /* SEC_MODID[428]:RTDM100*/ + [429] = {0xFFC43644U, 0x00000002U}, /* SEC_MODID[429]:RTDM101*/ + [430] = {0xFFC43648U, 0x00000002U}, /* SEC_MODID[430]:RTDM110*/ + [431] = {0xFFC4364CU, 0x00000002U}, /* SEC_MODID[431]:RTDM111*/ + [432] = {0xFFC43650U, 0x00000002U}, /* SEC_MODID[432]:RTDM112*/ + [433] = {0xFFC43654U, 0x00000002U}, /* SEC_MODID[433]:RTDM113*/ + [434] = {0xFFC43658U, 0x00000002U}, /* SEC_MODID[434]:RTDM114*/ + [435] = {0xFFC4365CU, 0x00000002U}, /* SEC_MODID[435]:RTDM115*/ + [436] = {0xFFC43660U, 0x00000002U}, /* SEC_MODID[436]:RTDM102*/ + [437] = {0xFFC43664U, 0x00000002U}, /* SEC_MODID[437]:RTDM103*/ + [438] = {0xFFC43668U, 0x00000002U}, /* SEC_MODID[438]:RTDM104*/ + [439] = {0xFFC4366CU, 0x00000002U}, /* SEC_MODID[439]:RTDM105*/ + [440] = {0xFFC43670U, 0x00000002U}, /* SEC_MODID[440]:RTDM106*/ + [441] = {0xFFC43674U, 0x00000002U}, /* SEC_MODID[441]:RTDM107*/ + [442] = {0xFFC43678U, 0x00000002U}, /* SEC_MODID[442]:RTDM108*/ + [443] = {0xFFC4367CU, 0x00000002U}, /* SEC_MODID[443]:RTDM109*/ + [444] = {0xFFC43700U, 0x00000002U}, /* SEC_MODID[444]:IPMMURT108*/ + [445] = {0xFFC43704U, 0x00000002U}, /* SEC_MODID[445]:IPMMURT109*/ + [446] = {0xFFC43708U, 0x00000000U}, /* SEC_MODID[446]:SYSRAM01*/ + [447] = {0xFFC4370CU, 0x00000002U}, /* SEC_MODID[447]:SYSRAM02*/ + [448] = {0xFFC43710U, 0x00000000U}, /* SEC_MODID[448]:SYSRAM03*/ + [449] = {0xFFC43714U, 0x00000000U}, /* SEC_MODID[449]:SYSRAM04*/ + [450] = {0xFFC43718U, 0x00000000U}, /* SEC_MODID[450]:SYSRAM05*/ + [451] = {0xFFC4371CU, 0x00000000U}, /* SEC_MODID[451]:SYSRAM06*/ + [452] = {0xFFC43720U, 0x00000002U}, /* SEC_MODID[452]:SYSRAM07*/ + [453] = {0xFFC43724U, 0x00000002U}, /* SEC_MODID[453]:SYSRAM11*/ + [454] = {0xFFC43728U, 0x00000002U}, /* SEC_MODID[454]:SYSRAM12*/ + [455] = {0xFFC4372CU, 0x00000002U}, /* SEC_MODID[455]:SYSRAM13*/ + [456] = {0xFFC43730U, 0x00000002U}, /* SEC_MODID[456]:SYSRAM14*/ + [457] = {0xFFC43734U, 0x00000002U}, /* SEC_MODID[457]:SYSRAM15*/ + [458] = {0xFFC43738U, 0x00000002U}, /* SEC_MODID[458]:SYSRAM16*/ + [459] = {0xFFC4373CU, 0x00000002U}, /* SEC_MODID[459]:SYSRAM17*/ + [460] = {0xFFC43760U, 0x00000002U}, /* SEC_MODID[460]:BKBUF*/ + [461] = {0xFFC43764U, 0x00000002U}, /* SEC_MODID[461]:AXICR52SS1*/ + [462] = {0xFFC43768U, 0x00000002U}, /* SEC_MODID[462]:AXICR52SS2*/ + [463] = {0xFF863400U, 0x00000002U}, /* SEC_MODID[463]:ARSC0*/ + [464] = {0xFF863404U, 0x00000002U}, /* SEC_MODID[464]:ARSC1*/ + [465] = {0xFF863408U, 0x00000002U}, /* SEC_MODID[465]:ARSC2*/ + [466] = {0xFF86340CU, 0x00000002U}, /* SEC_MODID[466]:ARSC3*/ + [467] = {0xFF863410U, 0x00000002U}, /* SEC_MODID[467]:ARSC4*/ + [468] = {0xFF863414U, 0x00000002U}, /* SEC_MODID[468]:ARSC5*/ + [469] = {0xFF863418U, 0x00000002U}, /* SEC_MODID[469]:ARSC6*/ + [470] = {0xFF86341CU, 0x00000002U}, /* SEC_MODID[470]:ARSC7*/ + [471] = {0xFF863420U, 0x00000002U}, /* SEC_MODID[471]:ARSC8*/ + [472] = {0xFF863424U, 0x00000002U}, /* SEC_MODID[472]:ARSTM0*/ + [473] = {0xFF863428U, 0x00000002U}, /* SEC_MODID[473]:ARSTM1*/ + [474] = {0xFF86342CU, 0x00000002U}, /* SEC_MODID[474]:CSD1S*/ + [475] = {0xFF863430U, 0x00000002U}, /* SEC_MODID[475]:AXIFBABUSTOP0*/ + [476] = {0xFF863438U, 0x00000002U}, /* SEC_MODID[476]:ARSTM2*/ + [477] = {0xFF86343CU, 0x00000002U}, /* SEC_MODID[477]:ARSTM3*/ + [478] = {0xFF863440U, 0x00000002U}, /* SEC_MODID[478]:ARSTM4*/ + [479] = {0xFF863444U, 0x00000002U}, /* SEC_MODID[479]:ARSTM5*/ + [480] = {0xFF863448U, 0x00000002U}, /* SEC_MODID[480]:ARSTM6*/ + [481] = {0xFF86344CU, 0x00000002U}, /* SEC_MODID[481]:ARSTM7*/ + [482] = {0xFF863450U, 0x00000002U}, /* SEC_MODID[482]:ARSTM8*/ + [483] = {0xFF863454U, 0x00000002U}, /* SEC_MODID[483]:ECMTOP*/ + [484] = {0xFF863458U, 0x00000002U}, /* SEC_MODID[484]:FBA*/ + [485] = {0xFF86345CU, 0x00000002U}, /* SEC_MODID[485]:FBC*/ + [486] = {0xFF863434U, 0x00000002U}, /* SEC_MODID[486]:AXICCI00*/ + [487] = {0xFF863460U, 0x00000002U}, /* SEC_MODID[487]:AXICCI01*/ + [488] = {0xFF863464U, 0x00000002U}, /* SEC_MODID[488]:AXICCI10*/ + [489] = {0xFF863468U, 0x00000002U}, /* SEC_MODID[489]:AXICCI11*/ + [490] = {0xFF86346CU, 0x00000002U}, /* SEC_MODID[490]:AXICCI12*/ + [491] = {0xFF863470U, 0x00000002U}, /* SEC_MODID[491]:AXICCI13*/ + [492] = {0xFF863474U, 0x00000002U}, /* SEC_MODID[492]:AXICCI14*/ + [493] = {0xFF863478U, 0x00000002U}, /* SEC_MODID[493]:AXICCI15*/ + [494] = {0xFF86347CU, 0x00000002U}, /* SEC_MODID[494]:AXICCI2*/ + [495] = {0xFF863480U, 0x00000002U}, /* SEC_MODID[495]:AXICCI3*/ + [496] = {0xFF863484U, 0x00000002U}, /* SEC_MODID[496]:AXICCI4*/ + [497] = {0xFF863488U, 0x00000002U}, /* SEC_MODID[497]:AXICCI5*/ + [498] = {0xFF86348CU, 0x00000002U}, /* SEC_MODID[498]:AXICCI6*/ + [499] = {0xFF863490U, 0x00000002U}, /* SEC_MODID[499]:AXICCI7*/ + [500] = {0xFF863494U, 0x00000002U}, /* SEC_MODID[500]:AXICCI8*/ + [501] = {0xFF863498U, 0x00000002U}, /* SEC_MODID[501]:AXICCI9*/ + [502] = {0xFF8634A0U, 0x00000002U}, /* SEC_MODID[502]:ECMSTM*/ + [503] = {0xE7783400U, 0x00000002U}, /* SEC_MODID[503]:DMASSI00*/ + [504] = {0xE7783404U, 0x00000002U}, /* SEC_MODID[504]:DMASSI01*/ + [505] = {0xE7783408U, 0x00000002U}, /* SEC_MODID[505]:DMASSI02*/ + [506] = {0xE778340CU, 0x00000002U}, /* SEC_MODID[506]:DMASSI03*/ + [507] = {0xE7783410U, 0x00000002U}, /* SEC_MODID[507]:DMASSI04*/ + [508] = {0xE7783414U, 0x00000002U}, /* SEC_MODID[508]:DMAI2C0*/ + [509] = {0xE7783418U, 0x00000002U}, /* SEC_MODID[509]:DMAI2C1*/ + [510] = {0xE778341CU, 0x00000002U}, /* SEC_MODID[510]:DMAI2C2*/ + [511] = {0xE7783420U, 0x00000002U}, /* SEC_MODID[511]:DMAI2C3*/ + [512] = {0xE778342CU, 0x00000002U}, /* SEC_MODID[512]:DMASSI05*/ + [513] = {0xE7783430U, 0x00000002U}, /* SEC_MODID[513]:DMASSI06*/ + [514] = {0xE7783434U, 0x00000002U}, /* SEC_MODID[514]:DMASSI07*/ + [515] = {0xE67C3400U, 0x00000002U}, /* SEC_MODID[515]:ARMM*/ + [516] = {0xE67C3404U, 0x00000002U}, /* SEC_MODID[516]:AXIARNMM*/ + [517] = {0xE67C3408U, 0x00000002U}, /* SEC_MODID[517]:ARSM0*/ + [518] = {0xE67C340CU, 0x00000002U}, /* SEC_MODID[518]:ARSM1*/ + [519] = {0xE67C3410U, 0x00000002U}, /* SEC_MODID[519]:ARSM2*/ + [520] = {0xE67C3414U, 0x00000002U}, /* SEC_MODID[520]:AXIQOS0*/ + [521] = {0xE67C3418U, 0x00000002U}, /* SEC_MODID[521]:AXIQOS1*/ + [522] = {0xE67C341CU, 0x00000002U}, /* SEC_MODID[522]:AXIQOS2*/ + [523] = {0xE67C3420U, 0x00000002U}, /* SEC_MODID[523]:AXIQOS3*/ + [524] = {0xE67C3424U, 0x00000002U}, /* SEC_MODID[524]:AXIQOS4*/ + [525] = {0xE67C3428U, 0x00000002U}, /* SEC_MODID[525]:AXIQOS5*/ + [526] = {0xE67C3434U, 0x00000002U}, /* SEC_MODID[526]:ARSM3*/ + [527] = {0xE67C3438U, 0x00000002U}, /* SEC_MODID[527]:ARSM4*/ + [528] = {0xE67C343CU, 0x00000002U}, /* SEC_MODID[528]:ARSM5*/ + [529] = {0xE67C3440U, 0x00000002U}, /* SEC_MODID[529]:ARSM6*/ + [530] = {0xE67C3444U, 0x00000002U}, /* SEC_MODID[530]:ARSM7*/ + [531] = {0xE67C3448U, 0x00000002U}, /* SEC_MODID[531]:ARSM8*/ + [532] = {0xE67C344CU, 0x00000000U}, /* SEC_MODID[532]:AXMM0*/ + [533] = {0xE67C3450U, 0x00000000U}, /* SEC_MODID[533]:AXMM1*/ + [534] = {0xE67C3454U, 0x00000002U}, /* SEC_MODID[534]:AXMMPMON*/ + [535] = {0xE67C3458U, 0x00000002U}, /* SEC_MODID[535]:CKMMM*/ + [536] = {0xE67C345CU, 0x00000002U}, /* SEC_MODID[536]:ECMMM*/ + [537] = {0xE67C3460U, 0x00000002U}, /* SEC_MODID[537]:FBADBSC0*/ + [538] = {0xE67C3468U, 0x00000002U}, /* SEC_MODID[538]:FBAMM*/ + [539] = {0xE67C346CU, 0x00000002U}, /* SEC_MODID[539]:IPMMUMM00*/ + [540] = {0xE67C3470U, 0x00000002U}, /* SEC_MODID[540]:DBS0A0*/ + [541] = {0xE67C3474U, 0x00000002U}, /* SEC_MODID[541]:DBS0A1*/ + [542] = {0xE67C3484U, 0x00000002U}, /* SEC_MODID[542]:FCPRC*/ + [543] = {0xE67C3488U, 0x00000002U}, /* SEC_MODID[543]:DBS0D0*/ + [544] = {0xE67C348CU, 0x00000002U}, /* SEC_MODID[544]:DBS0D1*/ + [545] = {0xE67C3498U, 0x00000002U}, /* SEC_MODID[545]:FBADDR*/ + [546] = {0xE67C349CU, 0x00000002U}, /* SEC_MODID[546]:IPMMUMM01*/ + [547] = {0xE67C34A0U, 0x00000002U}, /* SEC_MODID[547]:IPMMUMM10*/ + [548] = {0xE67C34A4U, 0x00000002U}, /* SEC_MODID[548]:IPMMUMM11*/ + [549] = {0xE67C34A8U, 0x00000002U}, /* SEC_MODID[549]:IPMMUMM12*/ + [550] = {0xE67C34ACU, 0x00000002U}, /* SEC_MODID[550]:IPMMUMM13*/ + [551] = {0xE67C34B0U, 0x00000002U}, /* SEC_MODID[551]:IPMMUMM14*/ + [552] = {0xE67C34B4U, 0x00000002U}, /* SEC_MODID[552]:IPMMUMM15*/ + [553] = {0xE67C34B8U, 0x00000002U}, /* SEC_MODID[553]:IPMMUMM02*/ + [554] = {0xE67C34BCU, 0x00000002U}, /* SEC_MODID[554]:IPMMUMM03*/ + [555] = {0xE67C34C0U, 0x00000002U}, /* SEC_MODID[555]:IPMMUMM04*/ + [556] = {0xE67C34C4U, 0x00000002U}, /* SEC_MODID[556]:IPMMUMM05*/ + [557] = {0xE67C34C8U, 0x00000002U}, /* SEC_MODID[557]:IPMMUMM06*/ + [558] = {0xE67C34CCU, 0x00000002U}, /* SEC_MODID[558]:IPMMUMM07*/ + [559] = {0xE67C34D0U, 0x00000002U}, /* SEC_MODID[559]:IPMMUMM08*/ + [560] = {0xE67C34D4U, 0x00000002U}, /* SEC_MODID[560]:IPMMUMM09*/ + [561] = {0xFF803400U, 0x00000002U}, /* SEC_MODID[561]:ARSN0*/ + [562] = {0xFF803404U, 0x00000002U}, /* SEC_MODID[562]:ARSN1*/ + [563] = {0xFF803408U, 0x00000002U}, /* SEC_MODID[563]:ARSN2*/ + [564] = {0xFF80340CU, 0x00000002U}, /* SEC_MODID[564]:ARSN3*/ + [565] = {0xFF803410U, 0x00000002U}, /* SEC_MODID[565]:ARSN4*/ + [566] = {0xFF803414U, 0x00000002U}, /* SEC_MODID[566]:ARSN5*/ + [567] = {0xFF803418U, 0x00000002U}, /* SEC_MODID[567]:ARSN6*/ + [568] = {0xFF80341CU, 0x00000002U}, /* SEC_MODID[568]:ARSN7*/ + [569] = {0xFF803420U, 0x00000002U}, /* SEC_MODID[569]:ARSN8*/ + [570] = {0xFF803424U, 0x00000002U}, /* SEC_MODID[570]:ECMTOP3*/ + [571] = {0xE7753400U, 0x00000002U}, /* SEC_MODID[571]:ARSD00*/ + [572] = {0xE7753404U, 0x00000002U}, /* SEC_MODID[572]:ARSD01*/ + [573] = {0xE7753408U, 0x00000002U}, /* SEC_MODID[573]:ARSD02*/ + [574] = {0xE775340CU, 0x00000002U}, /* SEC_MODID[574]:ARSD03*/ + [575] = {0xE7753410U, 0x00000002U}, /* SEC_MODID[575]:ARSD04*/ + [576] = {0xE7753414U, 0x00000002U}, /* SEC_MODID[576]:ARSD05*/ + [577] = {0xE7753418U, 0x00000002U}, /* SEC_MODID[577]:ARSD06*/ + [578] = {0xE775341CU, 0x00000002U}, /* SEC_MODID[578]:AXIFRAY*/ + [579] = {0xE7753428U, 0x00000002U}, /* SEC_MODID[579]:AXIRPC*/ + [580] = {0xE775342CU, 0x00000002U}, /* SEC_MODID[580]:AXISDHI0*/ + [581] = {0xE7753430U, 0x00000002U}, /* SEC_MODID[581]:ARSD07*/ + [582] = {0xE7753434U, 0x00000002U}, /* SEC_MODID[582]:ARSD08*/ + [583] = {0xE7753438U, 0x00000002U}, /* SEC_MODID[583]:ARSP00*/ + [584] = {0xE775343CU, 0x00000002U}, /* SEC_MODID[584]:ARSP01*/ + [585] = {0xE7753440U, 0x00000002U}, /* SEC_MODID[585]:ARSP02*/ + [586] = {0xE7753444U, 0x00000002U}, /* SEC_MODID[586]:ARSP03*/ + [587] = {0xE7753448U, 0x00000002U}, /* SEC_MODID[587]:ARSP04*/ + [588] = {0xE775344CU, 0x00000002U}, /* SEC_MODID[588]:ARSP05*/ + [589] = {0xE7753450U, 0x00000002U}, /* SEC_MODID[589]:ARSP06*/ + [590] = {0xE7753454U, 0x00000002U}, /* SEC_MODID[590]:ARSP07*/ + [591] = {0xE7753458U, 0x00000002U}, /* SEC_MODID[591]:ARSP08*/ + [592] = {0xE775345CU, 0x00000002U}, /* SEC_MODID[592]:IPMMUDS001*/ + [593] = {0xE7753460U, 0x00000002U}, /* SEC_MODID[593]:CKMPER0*/ + [594] = {0xE7753464U, 0x00000002U}, /* SEC_MODID[594]:ECMPER0*/ + [595] = {0xE7753468U, 0x00000002U}, /* SEC_MODID[595]:FBAPER0*/ + [596] = {0xE775346CU, 0x00000002U}, /* SEC_MODID[596]:FSO0*/ + [597] = {0xE7753470U, 0x00000002U}, /* SEC_MODID[597]:FSO1*/ + [598] = {0xE7753474U, 0x00000002U}, /* SEC_MODID[598]:FSO10*/ + [599] = {0xE7753478U, 0x00000002U}, /* SEC_MODID[599]:FSO2*/ + [600] = {0xE775347CU, 0x00000002U}, /* SEC_MODID[600]:FSO3*/ + [601] = {0xE7753480U, 0x00000002U}, /* SEC_MODID[601]:FSO4*/ + [602] = {0xE7753484U, 0x00000002U}, /* SEC_MODID[602]:FSO5*/ + [603] = {0xE7753488U, 0x00000002U}, /* SEC_MODID[603]:FSO6*/ + [604] = {0xE775348CU, 0x00000002U}, /* SEC_MODID[604]:FSO7*/ + [605] = {0xE7753490U, 0x00000002U}, /* SEC_MODID[605]:FSO8*/ + [606] = {0xE7753494U, 0x00000002U}, /* SEC_MODID[606]:FSO9*/ + [607] = {0xE7753498U, 0x00000002U}, /* SEC_MODID[607]:ADG*/ + [608] = {0xE775349CU, 0x00000002U}, /* SEC_MODID[608]:ECMSD0*/ + [609] = {0xE77534A0U, 0x00000002U}, /* SEC_MODID[609]:IPMMUDS010*/ + [610] = {0xE77534A4U, 0x00000002U}, /* SEC_MODID[610]:IPMMUDS011*/ + [611] = {0xE77534A8U, 0x00000002U}, /* SEC_MODID[611]:I2C0*/ + [612] = {0xE77534ACU, 0x00000002U}, /* SEC_MODID[612]:I2C1*/ + [613] = {0xE77534B0U, 0x00000002U}, /* SEC_MODID[613]:I2C2*/ + [614] = {0xE77534B4U, 0x00000002U}, /* SEC_MODID[614]:I2C3*/ + [615] = {0xE77534C0U, 0x00000002U}, /* SEC_MODID[615]:IPMMUDS012*/ + [616] = {0xE77534C8U, 0x00000002U}, /* SEC_MODID[616]:IPMMUDS000*/ + [617] = {0xE77534CCU, 0x00000002U}, /* SEC_MODID[617]:IPMMUDS013*/ + [618] = {0xE77534D0U, 0x00000002U}, /* SEC_MODID[618]:IPMMUDS014*/ + [619] = {0xE77534D4U, 0x00000002U}, /* SEC_MODID[619]:IPMMUDS015*/ + [620] = {0xE77534D8U, 0x00000002U}, /* SEC_MODID[620]:IPMMUDS002*/ + [621] = {0xE77534DCU, 0x00000002U}, /* SEC_MODID[621]:IPMMUDS003*/ + [622] = {0xE77534E0U, 0x00000002U}, /* SEC_MODID[622]:IPMMUDS004*/ + [623] = {0xE77534E4U, 0x00000002U}, /* SEC_MODID[623]:IPMMUDS005*/ + [624] = {0xE77534E8U, 0x00000002U}, /* SEC_MODID[624]:SSI*/ + [625] = {0xE77534ECU, 0x00000002U}, /* SEC_MODID[625]:IPMMUDS006*/ + [626] = {0xE77534F0U, 0x00000002U}, /* SEC_MODID[626]:IPMMUDS007*/ + [627] = {0xE77534F4U, 0x00000002U}, /* SEC_MODID[627]:SYDM1P*/ + [628] = {0xE77534F8U, 0x00000002U}, /* SEC_MODID[628]:IPMMUDS008*/ + [629] = {0xE77534FCU, 0x00000002U}, /* SEC_MODID[629]:SYDM2P*/ + [630] = {0xE7753500U, 0x00000002U}, /* SEC_MODID[630]:IPMMUDS009*/ + [631] = {0xE7753640U, 0x00000002U}, /* SEC_MODID[631]:SYDM100*/ + [632] = {0xE7753644U, 0x00000002U}, /* SEC_MODID[632]:SYDM101*/ + [633] = {0xE7753648U, 0x00000002U}, /* SEC_MODID[633]:SYDM110*/ + [634] = {0xE775364CU, 0x00000002U}, /* SEC_MODID[634]:SYDM111*/ + [635] = {0xE7753650U, 0x00000002U}, /* SEC_MODID[635]:SYDM112*/ + [636] = {0xE7753654U, 0x00000002U}, /* SEC_MODID[636]:SYDM113*/ + [637] = {0xE7753658U, 0x00000002U}, /* SEC_MODID[637]:SYDM114*/ + [638] = {0xE775365CU, 0x00000002U}, /* SEC_MODID[638]:SYDM115*/ + [639] = {0xE7753660U, 0x00000002U}, /* SEC_MODID[639]:SYDM102*/ + [640] = {0xE7753664U, 0x00000002U}, /* SEC_MODID[640]:SYDM103*/ + [641] = {0xE7753668U, 0x00000002U}, /* SEC_MODID[641]:SYDM104*/ + [642] = {0xE775366CU, 0x00000002U}, /* SEC_MODID[642]:SYDM105*/ + [643] = {0xE7753670U, 0x00000002U}, /* SEC_MODID[643]:SYDM106*/ + [644] = {0xE7753674U, 0x00000002U}, /* SEC_MODID[644]:SYDM107*/ + [645] = {0xE7753678U, 0x00000002U}, /* SEC_MODID[645]:SYDM108*/ + [646] = {0xE775367CU, 0x00000002U}, /* SEC_MODID[646]:SYDM109*/ + [647] = {0xE7753680U, 0x00000002U}, /* SEC_MODID[647]:SYDM200*/ + [648] = {0xE7753684U, 0x00000002U}, /* SEC_MODID[648]:SYDM201*/ + [649] = {0xE7753688U, 0x00000002U}, /* SEC_MODID[649]:SYDM210*/ + [650] = {0xE775368CU, 0x00000002U}, /* SEC_MODID[650]:SYDM211*/ + [651] = {0xE7753690U, 0x00000002U}, /* SEC_MODID[651]:SYDM212*/ + [652] = {0xE7753694U, 0x00000002U}, /* SEC_MODID[652]:SYDM213*/ + [653] = {0xE7753698U, 0x00000002U}, /* SEC_MODID[653]:SYDM214*/ + [654] = {0xE775369CU, 0x00000002U}, /* SEC_MODID[654]:SYDM215*/ + [655] = {0xE77536A0U, 0x00000002U}, /* SEC_MODID[655]:SYDM202*/ + [656] = {0xE77536A4U, 0x00000002U}, /* SEC_MODID[656]:SYDM203*/ + [657] = {0xE77536A8U, 0x00000002U}, /* SEC_MODID[657]:SYDM204*/ + [658] = {0xE77536ACU, 0x00000002U}, /* SEC_MODID[658]:SYDM205*/ + [659] = {0xE77536B0U, 0x00000002U}, /* SEC_MODID[659]:SYDM206*/ + [660] = {0xE77536B4U, 0x00000002U}, /* SEC_MODID[660]:SYDM207*/ + [661] = {0xE77536B8U, 0x00000002U}, /* SEC_MODID[661]:SYDM208*/ + [662] = {0xE77536BCU, 0x00000002U}, /* SEC_MODID[662]:SYDM209*/ + [663] = {0xFE683400U, 0x00000002U}, /* SEC_MODID[663]:ARVC0*/ + [664] = {0xFE683404U, 0x00000002U}, /* SEC_MODID[664]:ARVC1*/ + [665] = {0xFE683408U, 0x00000002U}, /* SEC_MODID[665]:ARVC2*/ + [666] = {0xFE68340CU, 0x00000002U}, /* SEC_MODID[666]:ARVC3*/ + [667] = {0xFE683410U, 0x00000002U}, /* SEC_MODID[667]:AXIFBABUSVC*/ + [668] = {0xFE683414U, 0x00000002U}, /* SEC_MODID[668]:ARVC4*/ + [669] = {0xFE683418U, 0x00000002U}, /* SEC_MODID[669]:ARVC5*/ + [670] = {0xFE68341CU, 0x00000002U}, /* SEC_MODID[670]:ARVC6*/ + [671] = {0xFE683420U, 0x00000002U}, /* SEC_MODID[671]:ARVC7*/ + [672] = {0xFE683424U, 0x00000002U}, /* SEC_MODID[672]:ARVC8*/ + [673] = {0xFE68342CU, 0x00000002U}, /* SEC_MODID[673]:ECMVC0*/ + [674] = {0xFE683434U, 0x00000002U}, /* SEC_MODID[674]:IMR0*/ + [675] = {0xFE683438U, 0x00000002U}, /* SEC_MODID[675]:IMR1*/ + [676] = {0xFE68343CU, 0x00000002U}, /* SEC_MODID[676]:IPMMUVC01*/ + [677] = {0xFE683440U, 0x00000002U}, /* SEC_MODID[677]:IPMMUVC10*/ + [678] = {0xFE683444U, 0x00000002U}, /* SEC_MODID[678]:IMS0*/ + [679] = {0xFE683448U, 0x00000002U}, /* SEC_MODID[679]:IMS1*/ + [680] = {0xFE68344CU, 0x00000002U}, /* SEC_MODID[680]:IPMMUVC00*/ + [681] = {0xFE683450U, 0x00000002U}, /* SEC_MODID[681]:IPMMUVC11*/ + [682] = {0xFE683454U, 0x00000002U}, /* SEC_MODID[682]:IPMMUVC12*/ + [683] = {0xFE683458U, 0x00000002U}, /* SEC_MODID[683]:IPMMUVC13*/ + [684] = {0xFE68345CU, 0x00000002U}, /* SEC_MODID[684]:IPMMUVC14*/ + [685] = {0xFE683460U, 0x00000002U}, /* SEC_MODID[685]:IPMMUVC15*/ + [686] = {0xFE683464U, 0x00000002U}, /* SEC_MODID[686]:IPMMUVC02*/ + [687] = {0xFE683468U, 0x00000002U}, /* SEC_MODID[687]:IPMMUVC03*/ + [688] = {0xFE68346CU, 0x00000002U}, /* SEC_MODID[688]:IPMMUVC04*/ + [689] = {0xFE683470U, 0x00000002U}, /* SEC_MODID[689]:IPMMUVC05*/ + [690] = {0xFE683474U, 0x00000002U}, /* SEC_MODID[690]:IPMMUVC06*/ + [691] = {0xFE683478U, 0x00000002U}, /* SEC_MODID[691]:IPMMUVC07*/ + [692] = {0xFE68347CU, 0x00000002U}, /* SEC_MODID[692]:IPMMUVC08*/ + [693] = {0xFE683480U, 0x00000002U}, /* SEC_MODID[693]:IPMMUVC09*/ + [694] = {0xFE683484U, 0x00000002U}, /* SEC_MODID[694]:IV1ES*/ + [695] = {0xFEBE3400U, 0x00000002U}, /* SEC_MODID[695]:CSITOP0*/ + [696] = {0xFEBE3404U, 0x00000002U}, /* SEC_MODID[696]:ARVI10*/ + [697] = {0xFEBE3408U, 0x00000002U}, /* SEC_MODID[697]:ARVI11*/ + [698] = {0xFEBE340CU, 0x00000002U}, /* SEC_MODID[698]:ARVI12*/ + [699] = {0xFEBE3410U, 0x00000002U}, /* SEC_MODID[699]:ARVI13*/ + [700] = {0xFEBE3414U, 0x00000002U}, /* SEC_MODID[700]:ARVI14*/ + [701] = {0xFEBE3418U, 0x00000002U}, /* SEC_MODID[701]:ARVI15*/ + [702] = {0xFEBE341CU, 0x00000002U}, /* SEC_MODID[702]:ARVI16*/ + [703] = {0xFEBE3420U, 0x00000002U}, /* SEC_MODID[703]:ARVI17*/ + [704] = {0xFEBE3424U, 0x00000002U}, /* SEC_MODID[704]:ARVI18*/ + [705] = {0xFEBE342CU, 0x00000002U}, /* SEC_MODID[705]:CSITOP1*/ + [706] = {0xFEBE3434U, 0x00000002U}, /* SEC_MODID[706]:DSITLINK0*/ + [707] = {0xFEBE343CU, 0x00000002U}, /* SEC_MODID[707]:ECMVIO1*/ + [708] = {0xFEBE3444U, 0x00000002U}, /* SEC_MODID[708]:IPMMUVI001*/ + [709] = {0xFEBE3448U, 0x00000002U}, /* SEC_MODID[709]:FCPVX0*/ + [710] = {0xFEBE3458U, 0x00000002U}, /* SEC_MODID[710]:IPMMUVI000*/ + [711] = {0xFEBE345CU, 0x00000002U}, /* SEC_MODID[711]:IPMMUVI100*/ + [712] = {0xFEBE3460U, 0x00000002U}, /* SEC_MODID[712]:IPMMUVI010*/ + [713] = {0xFEBE3464U, 0x00000002U}, /* SEC_MODID[713]:IPMMUVI011*/ + [714] = {0xFEBE3468U, 0x00000002U}, /* SEC_MODID[714]:VSPX0*/ + [715] = {0xFEBE3478U, 0x00000002U}, /* SEC_MODID[715]:IPMMUVI012*/ + [716] = {0xFEBE347CU, 0x00000002U}, /* SEC_MODID[716]:IPMMUVI013*/ + [717] = {0xFEBE3480U, 0x00000002U}, /* SEC_MODID[717]:IPMMUVI014*/ + [718] = {0xFEBE3484U, 0x00000002U}, /* SEC_MODID[718]:IPMMUVI015*/ + [719] = {0xFEBE3488U, 0x00000002U}, /* SEC_MODID[719]:IPMMUVI002*/ + [720] = {0xFEBE348CU, 0x00000002U}, /* SEC_MODID[720]:IPMMUVI003*/ + [721] = {0xFEBE3490U, 0x00000002U}, /* SEC_MODID[721]:IPMMUVI004*/ + [722] = {0xFEBE3494U, 0x00000002U}, /* SEC_MODID[722]:IPMMUVI005*/ + [723] = {0xFEBE3498U, 0x00000002U}, /* SEC_MODID[723]:IPMMUVI006*/ + [724] = {0xFEBE349CU, 0x00000002U}, /* SEC_MODID[724]:IPMMUVI007*/ + [725] = {0xFEBE34A0U, 0x00000002U}, /* SEC_MODID[725]:IPMMUVI008*/ + [726] = {0xFEBE34A4U, 0x00000002U}, /* SEC_MODID[726]:IPMMUVI009*/ + [727] = {0xFEBE34A8U, 0x00000002U}, /* SEC_MODID[727]:IPMMUVI101*/ + [728] = {0xFEBE34ACU, 0x00000002U}, /* SEC_MODID[728]:IPMMUVI110*/ + [729] = {0xFEBE34B0U, 0x00000002U}, /* SEC_MODID[729]:IPMMUVI111*/ + [730] = {0xFEBE34B4U, 0x00000002U}, /* SEC_MODID[730]:IPMMUVI112*/ + [731] = {0xFEBE34B8U, 0x00000002U}, /* SEC_MODID[731]:IPMMUVI113*/ + [732] = {0xFEBE34BCU, 0x00000002U}, /* SEC_MODID[732]:IPMMUVI114*/ + [733] = {0xFEBE34C0U, 0x00000002U}, /* SEC_MODID[733]:IPMMUVI115*/ + [734] = {0xFEBE34C4U, 0x00000002U}, /* SEC_MODID[734]:IPMMUVI102*/ + [735] = {0xFEBE34C8U, 0x00000002U}, /* SEC_MODID[735]:IPMMUVI103*/ + [736] = {0xFEBE34CCU, 0x00000002U}, /* SEC_MODID[736]:IPMMUVI104*/ + [737] = {0xFEBE34D0U, 0x00000002U}, /* SEC_MODID[737]:IPMMUVI105*/ + [738] = {0xFEBE34D4U, 0x00000002U}, /* SEC_MODID[738]:IPMMUVI106*/ + [739] = {0xFEBE34D8U, 0x00000002U}, /* SEC_MODID[739]:IPMMUVI107*/ + [740] = {0xFEBE34DCU, 0x00000002U}, /* SEC_MODID[740]:IPMMUVI108*/ + [741] = {0xFEBE34E0U, 0x00000002U}, /* SEC_MODID[741]:IPMMUVI109*/ + [742] = {0xFEBE3504U, 0x00000002U}, /* SEC_MODID[742]:AXIFBABUSVIO*/ + [743] = {0xFEBF3400U, 0x00000002U}, /* SEC_MODID[743]:ARVI0*/ + [744] = {0xFEBF3404U, 0x00000002U}, /* SEC_MODID[744]:ARVI1*/ + [745] = {0xFEBF3408U, 0x00000002U}, /* SEC_MODID[745]:ARVI2*/ + [746] = {0xFEBF340CU, 0x00000002U}, /* SEC_MODID[746]:ARVI3*/ + [747] = {0xFEBF3410U, 0x00000002U}, /* SEC_MODID[747]:ARVI4*/ + [748] = {0xFEBF3414U, 0x00000002U}, /* SEC_MODID[748]:ARVI5*/ + [749] = {0xFEBF3418U, 0x00000002U}, /* SEC_MODID[749]:ARVI6*/ + [750] = {0xFEBF341CU, 0x00000002U}, /* SEC_MODID[750]:ARVI7*/ + [751] = {0xFEBF3420U, 0x00000002U}, /* SEC_MODID[751]:ARVI8*/ + [752] = {0xFEBF3424U, 0x00000002U}, /* SEC_MODID[752]:ECMVIO0*/ + [753] = {0xFEBF3428U, 0x00000002U}, /* SEC_MODID[753]:ISP0*/ + [754] = {0xFEBF342CU, 0x00000002U}, /* SEC_MODID[754]:ISP0CORE*/ + [755] = {0xFEBF3430U, 0x00000002U}, /* SEC_MODID[755]:ISP1*/ + [756] = {0xFEBF3454U, 0x00000002U}, /* SEC_MODID[756]:VIN00*/ + [757] = {0xFEBF3458U, 0x00000002U}, /* SEC_MODID[757]:VIN01*/ + [758] = {0xFEBF345CU, 0x00000002U}, /* SEC_MODID[758]:VIN02*/ + [759] = {0xFEBF3460U, 0x00000002U}, /* SEC_MODID[759]:VIN03*/ + [760] = {0xFEBF3464U, 0x00000002U}, /* SEC_MODID[760]:VIN04*/ + [761] = {0xFEBF3468U, 0x00000002U}, /* SEC_MODID[761]:VIN05*/ + [762] = {0xFEBF346CU, 0x00000002U}, /* SEC_MODID[762]:VIN06*/ + [763] = {0xFEBF3470U, 0x00000002U}, /* SEC_MODID[763]:VIN07*/ + [764] = {0xFEBF3474U, 0x00000002U}, /* SEC_MODID[764]:VIN10*/ + [765] = {0xFEBF3478U, 0x00000002U}, /* SEC_MODID[765]:VIN11*/ + [766] = {0xFEBF347CU, 0x00000002U}, /* SEC_MODID[766]:VIN12*/ + [767] = {0xFEBF3480U, 0x00000002U}, /* SEC_MODID[767]:VIN13*/ + [768] = {0xFEBF3484U, 0x00000002U}, /* SEC_MODID[768]:VIN14*/ + [769] = {0xFEBF3488U, 0x00000002U}, /* SEC_MODID[769]:VIN15*/ + [770] = {0xFEBF348CU, 0x00000002U}, /* SEC_MODID[770]:VIN16*/ + [771] = {0xFEBF3490U, 0x00000002U}, /* SEC_MODID[771]:VIN17*/ + [772] = {0xE7B13400U, 0x00000002U}, /* SEC_MODID[772]:ARVIP00*/ + [773] = {0xE7B13404U, 0x00000002U}, /* SEC_MODID[773]:ARVIP01*/ + [774] = {0xE7B13408U, 0x00000002U}, /* SEC_MODID[774]:ARVIP02*/ + [775] = {0xE7B1340CU, 0x00000002U}, /* SEC_MODID[775]:ARVIP03*/ + [776] = {0xE7B13410U, 0x00000002U}, /* SEC_MODID[776]:AXIFBABUSVIP0*/ + [777] = {0xE7B13414U, 0x00000002U}, /* SEC_MODID[777]:ARVIP04*/ + [778] = {0xE7B13418U, 0x00000002U}, /* SEC_MODID[778]:ARVIP05*/ + [779] = {0xE7B1341CU, 0x00000002U}, /* SEC_MODID[779]:ARVIP06*/ + [780] = {0xE7B13420U, 0x00000002U}, /* SEC_MODID[780]:ARVIP07*/ + [781] = {0xE7B13424U, 0x00000002U}, /* SEC_MODID[781]:ARVIP08*/ + [782] = {0xE7B1342CU, 0x00000002U}, /* SEC_MODID[782]:ECMVIP0*/ + [783] = {0xE7B13430U, 0x00000002U}, /* SEC_MODID[783]:IPMMUVIP000*/ + [784] = {0xE7B13438U, 0x00000002U}, /* SEC_MODID[784]:SMPO0*/ + [785] = {0xE7B1343CU, 0x00000002U}, /* SEC_MODID[785]:SMPS0*/ + [786] = {0xE7B13440U, 0x00000002U}, /* SEC_MODID[786]:UMFL0*/ + [787] = {0xE7B13444U, 0x00000002U}, /* SEC_MODID[787]:IPMMUVIP001*/ + [788] = {0xE7B13448U, 0x00000002U}, /* SEC_MODID[788]:IPMMUVIP010*/ + [789] = {0xE7B1344CU, 0x00000002U}, /* SEC_MODID[789]:IPMMUVIP011*/ + [790] = {0xE7B13450U, 0x00000002U}, /* SEC_MODID[790]:UMFL0M_W*/ + [791] = {0xE7B13454U, 0x00000002U}, /* SEC_MODID[791]:IPMMUVIP012*/ + [792] = {0xE7B13458U, 0x00000002U}, /* SEC_MODID[792]:IPMMUVIP013*/ + [793] = {0xE7B1345CU, 0x00000002U}, /* SEC_MODID[793]:IPMMUVIP014*/ + [794] = {0xE7B13460U, 0x00000002U}, /* SEC_MODID[794]:IPMMUVIP015*/ + [795] = {0xE7B13464U, 0x00000002U}, /* SEC_MODID[795]:IPMMUVIP002*/ + [796] = {0xE7B13468U, 0x00000002U}, /* SEC_MODID[796]:IPMMUVIP003*/ + [797] = {0xE7B1346CU, 0x00000002U}, /* SEC_MODID[797]:IPMMUVIP004*/ + [798] = {0xE7B13470U, 0x00000002U}, /* SEC_MODID[798]:IPMMUVIP005*/ + [799] = {0xE7B13474U, 0x00000002U}, /* SEC_MODID[799]:IPMMUVIP006*/ + [800] = {0xE7B13478U, 0x00000002U}, /* SEC_MODID[800]:IPMMUVIP007*/ + [801] = {0xE7B1347CU, 0x00000002U}, /* SEC_MODID[801]:IPMMUVIP008*/ + [802] = {0xE7B13480U, 0x00000002U}, /* SEC_MODID[802]:IPMMUVIP009*/ + [803] = {0xFF8834A0U, 0x00000002U}, /* SEC_MODID[803]:ARDSP0*/ + [804] = {0xFF8834A4U, 0x00000002U}, /* SEC_MODID[804]:ARDSP1*/ + [805] = {0xFF8834A8U, 0x00000002U}, /* SEC_MODID[805]:ARDSP2*/ + [806] = {0xFF8834ACU, 0x00000002U}, /* SEC_MODID[806]:ARDSP3*/ + [807] = {0xFF8834B0U, 0x00000002U}, /* SEC_MODID[807]:ARDSP4*/ + [808] = {0xFF8834B4U, 0x00000002U}, /* SEC_MODID[808]:ARDSP5*/ + [809] = {0xFF8834B8U, 0x00000002U}, /* SEC_MODID[809]:ARDSP6*/ + [810] = {0xFF8834BCU, 0x00000002U}, /* SEC_MODID[810]:ARDSP7*/ + [811] = {0xFF8834C0U, 0x00000002U}, /* SEC_MODID[811]:ECMDSP*/ + [812] = {0xFF883490U, 0x00000002U}, /* SEC_MODID[812]:AXIDSP0*/ + [813] = {0xFF883494U, 0x00000002U}, /* SEC_MODID[813]:AXIDSP1*/ + [814] = {0xFF883498U, 0x00000002U}, /* SEC_MODID[814]:AXIDSP2*/ + [815] = {0xFF88349CU, 0x00000002U}, /* SEC_MODID[815]:AXIDSP3*/ + [816] = {0xE7753424U, 0x00000002U}, /* SEC_MODID[816]:RSV0*/ + [817] = {0xE7B1350CU, 0x00000002U}, /* SEC_MODID[817]:PAP*/ + [818] = {0xFEBD3428U, 0x00000002U}, /* SEC_MODID[818]:DOC*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +#if defined(__RH850G3K__) +#pragma ghs section rodata=".rgid_axi_tbl" +#else +__attribute__ ((section(".rgid_axi_tbl"))) +#endif +const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[] = { + [0] = {0xFFC82010U, 0x0000000FU}, /* RGIDR_MODID[4]:ARRT01*/ + [1] = {0xFFC82014U, 0x0000000FU}, /* RGIDR_MODID[5]:ARRT02*/ + [2] = {0xE6002048U, 0x0000000FU}, /* RGIDR_MODID[41]:ARS01*/ + [3] = {0xE600204CU, 0x0000000FU}, /* RGIDR_MODID[42]:ARS02*/ + [4] = {0xE7762028U, 0x0000000FU}, /* RGIDR_MODID[99]:ARSP31*/ + [5] = {0xE776202CU, 0x0000000FU}, /* RGIDR_MODID[100]:ARSP32*/ + [6] = {0xE7792004U, 0x0000000FU}, /* RGIDR_MODID[114]:ARSP41*/ + [7] = {0xE7792008U, 0x0000000FU}, /* RGIDR_MODID[115]:ARSP42*/ + [8] = {0xFEBD2004U, 0x0000000FU}, /* RGIDR_MODID[153]:ARVI41*/ + [9] = {0xFEBD2008U, 0x0000000FU}, /* RGIDR_MODID[154]:ARVI42*/ + [10] = {0xE6582140U, 0x0000000FU}, /* RGIDR_MODID[199]:ARHC1*/ + [11] = {0xE6582144U, 0x0000000FU}, /* RGIDR_MODID[200]:ARHC2*/ + [12] = {0xFF882004U, 0x0000000FU}, /* RGIDR_MODID[215]:ARIMP01*/ + [13] = {0xFF882008U, 0x0000000FU}, /* RGIDR_MODID[216]:ARIMP02*/ + [14] = {0xFD812004U, 0x0000000FU}, /* RGIDR_MODID[247]:ARPV1*/ + [15] = {0xFD81200CU, 0x0000000FU}, /* RGIDR_MODID[249]:ARPV2*/ + [16] = {0xE6622004U, 0x0000000FU}, /* RGIDR_MODID[279]:ARRC1*/ + [17] = {0xE6622008U, 0x0000000FU}, /* RGIDR_MODID[280]:ARRC2*/ + [18] = {0xFFC42060U, 0x0000000FU}, /* RGIDR_MODID[316]:ARRD1*/ + [19] = {0xFFC42064U, 0x0000000FU}, /* RGIDR_MODID[317]:ARRD2*/ + [20] = {0xFFC42084U, 0x0000000FU}, /* RGIDR_MODID[325]:ARRT1*/ + [21] = {0xFFC42088U, 0x0000000FU}, /* RGIDR_MODID[326]:ARRT2*/ + [24] = {0xFF862004U, 0x0000000FU}, /* RGIDR_MODID[464]:ARSC1*/ + [25] = {0xFF862008U, 0x0000000FU}, /* RGIDR_MODID[465]:ARSC2*/ + [22] = {0xFF862028U, 0x0000000FU}, /* RGIDR_MODID[473]:ARSTM1*/ + [23] = {0xFF862038U, 0x0000000FU}, /* RGIDR_MODID[476]:ARSTM2*/ + [26] = {0xE67C2004U, 0x0000000FU}, /* RGIDR_MODID[516]:AXIARNMM*/ + [27] = {0xE67C200CU, 0x0000000FU}, /* RGIDR_MODID[518]:ARSM1*/ + [28] = {0xE67C2010U, 0x0000000FU}, /* RGIDR_MODID[519]:ARSM2*/ + [29] = {0xFF802004U, 0x0000000FU}, /* RGIDR_MODID[562]:ARSN1*/ + [30] = {0xFF802008U, 0x0000000FU}, /* RGIDR_MODID[563]:ARSN2*/ + [31] = {0xE7752004U, 0x0000000FU}, /* RGIDR_MODID[572]:ARSD01*/ + [32] = {0xE7752008U, 0x0000000FU}, /* RGIDR_MODID[573]:ARSD02*/ + [33] = {0xE775203CU, 0x0000000FU}, /* RGIDR_MODID[584]:ARSP01*/ + [34] = {0xE7752040U, 0x0000000FU}, /* RGIDR_MODID[585]:ARSP02*/ + [35] = {0xFE682004U, 0x0000000FU}, /* RGIDR_MODID[664]:ARVC1*/ + [36] = {0xFE682008U, 0x0000000FU}, /* RGIDR_MODID[665]:ARVC2*/ + [37] = {0xFEBE2008U, 0x0000000FU}, /* RGIDR_MODID[697]:ARVI11*/ + [38] = {0xFEBE200CU, 0x0000000FU}, /* RGIDR_MODID[698]:ARVI12*/ + [39] = {0xFEBF2004U, 0x0000000FU}, /* RGIDR_MODID[744]:ARVI1*/ + [40] = {0xFEBF2008U, 0x0000000FU}, /* RGIDR_MODID[745]:ARVI2*/ + [41] = {0xE7B12004U, 0x0000000FU}, /* RGIDR_MODID[772]:ARVIP01*/ + [42] = {0xE7B12008U, 0x0000000FU}, /* RGIDR_MODID[773]:ARVIP02*/ + [43] = {0xFF8820A4U, 0x0000000FU}, /* RGIDR_MODID[803]:ARDSP1*/ + [44] = {0xFF8820A8U, 0x0000000FU}, /* RGIDR_MODID[804]:ARDSP2*/ + [45] = {0xFFC82410U, 0x00000000U}, /* RGIDW_MODID[4]:ARRT01*/ + [46] = {0xFFC82414U, 0x00000000U}, /* RGIDW_MODID[5]:ARRT02*/ + [47] = {0xE6002448U, 0x00000000U}, /* RGIDW_MODID[41]:ARS01*/ + [48] = {0xE600244CU, 0x00000000U}, /* RGIDW_MODID[42]:ARS02*/ + [49] = {0xE7762428U, 0x00000000U}, /* RGIDW_MODID[99]:ARSP31*/ + [50] = {0xE776242CU, 0x00000000U}, /* RGIDW_MODID[100]:ARSP32*/ + [51] = {0xE7792404U, 0x00000000U}, /* RGIDW_MODID[114]:ARSP41*/ + [52] = {0xE7792408U, 0x00000000U}, /* RGIDW_MODID[115]:ARSP42*/ + [53] = {0xFEBD2404U, 0x00000000U}, /* RGIDW_MODID[153]:ARVI41*/ + [54] = {0xFEBD2408U, 0x00000000U}, /* RGIDW_MODID[154]:ARVI42*/ + [55] = {0xE6582540U, 0x00000000U}, /* RGIDW_MODID[199]:ARHC1*/ + [56] = {0xE6582544U, 0x00000000U}, /* RGIDW_MODID[200]:ARHC2*/ + [57] = {0xFF8824A4U, 0x00000000U}, /* RGIDW_MODID[802]:ARDSP1*/ + [58] = {0xFF8824A8U, 0x00000000U}, /* RGIDW_MODID[803]:ARDSP2*/ + [59] = {0xFF882404U, 0x00000000U}, /* RGIDW_MODID[215]:ARIMP01*/ + [60] = {0xFF882408U, 0x00000000U}, /* RGIDW_MODID[216]:ARIMP02*/ + [61] = {0xFD812404U, 0x00000000U}, /* RGIDW_MODID[247]:ARPV1*/ + [62] = {0xFD81240CU, 0x00000000U}, /* RGIDW_MODID[249]:ARPV2*/ + [63] = {0xE6622404U, 0x00000000U}, /* RGIDW_MODID[279]:ARRC1*/ + [64] = {0xE6622408U, 0x00000000U}, /* RGIDW_MODID[280]:ARRC2*/ + [65] = {0xFFC42460U, 0x00000000U}, /* RGIDW_MODID[315]:ARRD1*/ + [66] = {0xFFC42464U, 0x00000000U}, /* RGIDW_MODID[316]:ARRD2*/ + [67] = {0xFFC42484U, 0x00000000U}, /* RGIDW_MODID[324]:ARRT1*/ + [68] = {0xFFC42488U, 0x00000000U}, /* RGIDW_MODID[325]:ARRT2*/ + [71] = {0xFF862404U, 0x00000000U}, /* RGIDW_MODID[463]:ARSC1*/ + [72] = {0xFF862408U, 0x00000000U}, /* RGIDW_MODID[464]:ARSC2*/ + [69] = {0xFF862428U, 0x00000000U}, /* RGIDW_MODID[472]:ARSTM1*/ + [70] = {0xFF862438U, 0x00000000U}, /* RGIDW_MODID[475]:ARSTM2*/ + [73] = {0xE67C2404U, 0x00000000U}, /* RGIDW_MODID[515]:AXIARNMM*/ + [74] = {0xE67C240CU, 0x00000000U}, /* RGIDW_MODID[517]:ARSM1*/ + [75] = {0xE67C2410U, 0x00000000U}, /* RGIDW_MODID[518]:ARSM2*/ + [76] = {0xFF802404U, 0x00000000U}, /* RGIDW_MODID[561]:ARSN1*/ + [77] = {0xFF802408U, 0x00000000U}, /* RGIDW_MODID[562]:ARSN2*/ + [78] = {0xE7752404U, 0x00000000U}, /* RGIDW_MODID[571]:ARSD01*/ + [79] = {0xE7752408U, 0x00000000U}, /* RGIDW_MODID[572]:ARSD02*/ + [80] = {0xE775243CU, 0x00000000U}, /* RGIDW_MODID[583]:ARSP01*/ + [81] = {0xE7752440U, 0x00000000U}, /* RGIDW_MODID[584]:ARSP02*/ + [82] = {0xFE682404U, 0x00000000U}, /* RGIDW_MODID[663]:ARVC1*/ + [83] = {0xFE682408U, 0x00000000U}, /* RGIDW_MODID[664]:ARVC2*/ + [84] = {0xFEBE2408U, 0x00000000U}, /* RGIDW_MODID[696]:ARVI11*/ + [85] = {0xFEBE240CU, 0x00000000U}, /* RGIDW_MODID[697]:ARVI12*/ + [86] = {0xFEBF2404U, 0x00000000U}, /* RGIDW_MODID[743]:ARVI1*/ + [87] = {0xFEBF2408U, 0x00000000U}, /* RGIDW_MODID[744]:ARVI2*/ + [88] = {0xE7B12404U, 0x00000000U}, /* RGIDW_MODID[771]:ARVIP01*/ + [89] = {0xE7B12408U, 0x00000000U}, /* RGIDW_MODID[772]:ARVIP02*/ +}; +#if defined(__RH850G3K__) +/* Now go back to default rules */ +#pragma ghs section rodata=default +#endif + +/* RAM protection setting for SECDIV[n]D_0 / SECCTRR[m]D_0 / SECCTRW[m]D_0 */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram0_protection_table[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM0_ICUMX_IPL_AREA] = {NOT_USED_VALUE, {0x0000FFFCU, 0x0000FFFEU}}, /* not used for address value */ + /* Area0 phys:0xE0000000-0xE003FFFF R:RGID0/1 W:RGID0 */ + [RTVRAM0_ICUMX_FW_AREA] = {RTVRAM0_AREA1_TOP, {0x0004FFFEU, 0x0004FFFEU}}, /* Area1 phys:0xE0040000-0xE00FFFFF R:RGID0 W:RGID0 */ + [2] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [3] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM0_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for SECDIV[n]D_1 / SECCTRR[m]D_1 / SECCTRW[m]D_1 */ +const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table[RAM_PROTECTION_MAX] = { + /* address READ Write */ + [RTVRAM1_BLANK_AREA] = {NOT_USED_VALUE, {0x0000FFB6U, 0x0000FFB7U}}, /* not used for address value */ + /* Area0 phys:0xE2000000-0xE200FFFF R:RGID0/3/6 W:RGID3/6 */ + [RTVRAM1_EXTEND_CACHE_AREA] = {RTVRAM1_AREA1_TOP, {0x0000BFFFU, 0x0000BFFFU}}, /* Area1 phys:0xE2010000-0xE20FFFFF R:RGID14 W:RGID14 */ + [RTVRAM1_RTOS_AREA] = {RTVRAM1_AREA2_TOP, {0x0000FFF4U, 0x0000FFF5U}}, /* Area2 phys:0xE2100000-0xE3BFFFFF R:RGID0/1/3 W:RGID1/3 */ + [3] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {RTVRAM1_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for SPTDIVCR[n] / SPTRGNCR[n] / SPTSECCR[n] */ +const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX] = { + /* access Secure */ + /* address R | W R|W */ + [SYSTEM_RAM_CX_2ND_IPL] = {NOT_USED_VALUE, {0xFFD8FFD8U, 0x00000000U}}, /* not used for address value */ + /* + * Change the access permission from 0xFFD8FFD8 to 0xFFD8FFD9 + * if user want to enable protection of System Ram Area0. + */ + /* Area0 phys:0xE6300000-0xE635DFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [SYSTEM_RAM_SHARED_MEM] = {SYSTEM_RAM_AREA1_TOP, {0xFFD8FFD8U, 0x00000000U}}, /* Area1 phys:0xE635E000-0xE635FFFF R:RGID0/1/2/5 W:RGID0/1/2/5 */ + [2] = {SYSTEM_RAM_AREA2_TOP, {0xFFDAFFDAU, 0x00000000U}}, /* Area2 phys:0xE6360000-0xE63FFFFF R:RGID0/2/5 W:RGID0/2/5 */ + [3] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [4] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [5] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [6] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [7] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [8] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [9] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [10] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [11] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [12] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [13] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [14] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {SYSTEM_RAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +/* RAM protection setting for DPTDIVCR[n] / DPTRGNCR[n] / DPTSECCR[n] */ +const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX] = { + /* access secure */ + /* address R | W R|W */ + [RTVRAM1_EXTEND_AREA] = {NOT_USED_VALUE, {0xBFFFBFFFU, 0x00000000U}}, /* not used for address value */ + /* Area0 phys:0x04_00000000-0x04_01BFFFFF R:RGID14 W:RGID14 */ + [CR_FW_SHARED_AREA] = {DRAM_ADDR_AREA1, {0xFFBCFFBCU, 0x00000000U}}, /* Area1 phys:0x04_01C00000-0x04_01CFFFFF R:RGID0/1/6 W:RGID0/1/6 */ + /* This secure setting is added by sdram_protection() in loader_main function. */ + [SDRAM_BLANK_AREA] = {DRAM_ADDR_AREA2, {0xFF90FF90U, 0x00000000U}}, /* Area2:OPTEE_DISABLE phys:0x04_01D00000-0x04_063FFFFF + * Area2:OPTEE_ENABLE phys:0x04_01D00000-0x04_040FFFFF + * R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFBFFF9U, 0x00000404U}}, /* Area3 phys:0x04_06400000-0x04_0643FFFF R:RGID2 W:RGID1/2 */ + [SDRAM_PUBLIC_AREA] = {DRAM_ADDR_AREA4, {0xFF90FF90U, 0x00000000U}}, /* Area4 phys:0x04_06440000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA5, {0xFFB9FFB9U, 0x00000000U}}, /* Area5 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA6, {0xFFB1FFB1U, 0x00000000U}}, /* Area6 phys:0x04_08000000-0x04_1DBFFFFF R:RGID1/2/3/6 W:RGID1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA7, {0xFFB9FFB9U, 0x00000000U}}, /* Area7 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFBDFFBDU, 0x00000000U}}, /* Area8 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFDDFFDDU, 0x00000000U}}, /* Area9 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA11,{0xBF90BF90U, 0x00000000U}}, /* Area11 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA12,{0xFFF9FFF9U, 0x00000000U}}, /* Area12 phys:0x05_00000000-0x05_FFFFFFFF R:RGID1/2 W:RGID1/2 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA13,{0xFFFFFFFFU, 0x00000000U}}, /* Area13 phys:0x06_00000000-0x06_FFFFFFFF */ + [14] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [15] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [16] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +#else + [SDRAM_PROTECT_AREA] = {DRAM_ADDR_AREA3, {0xFFFAFFFAU, 0x00000404U}}, /* Area3 phys:0x04_04100000-0x04_063FFFFF R:RGID0/2 W:RGID0/2 */ + [SDRAM_PROTECT_AREA2] = {DRAM_ADDR_AREA4, {0xFFFBFFF9U, 0x00000404U}}, /* Area4 phys:0x04_06400000-0x04_0643FFFF R:RGID2 W:RGID1/2 */ + [SDRAM_BLANK_AREA2] = {DRAM_ADDR_AREA5, {0xFF90FF90U, 0x00000000U}}, /* Area5 phys:0x04_06440000-0x04_07DFFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [OPTEE_SHARED_AREA] = {DRAM_ADDR_AREA6, {0xFFFBFFFBU, 0x00000000U}}, /* Area6 phys:0x04_07E00000-0x04_07EFFFFF R:RGID2 W:RGID2 */ + [SDRAM_BLANK_AREA3] = {DRAM_ADDR_AREA7, {0xFF90FF90U, 0x00000000U}}, /* Area7 phys:0x04_07F00000-0x04_07FBFFFF R:RGID0/1/2/3/5/6 W:RGID0/1/2/3/5/6 */ + [ICCOM_USED_AREA] = {DRAM_ADDR_AREA8, {0xFFB9FFB9U, 0x00000000U}}, /* Area8 phys:0x04_07FC0000-0x04_07FFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [LINUX_USED_AREA] = {DRAM_ADDR_AREA9, {0xFFB1FFB1U, 0x00000000U}}, /* Area9 phys:0x04_08000000-0x04_1DBFFFFF R:RGID1/2/3/6 W:RGID1/2/3/6 */ + [CAAREA2_USED_AREA] = {DRAM_ADDR_AREA10,{0xFFB9FFB9U, 0x00000000U}}, /* Area10 phys:0x04_1DC00000-0x04_1FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CR52_USED_AREA] = {DRAM_ADDR_AREA11,{0xFFBDFFBDU, 0x00000000U}}, /* Area11 phys:0x04_20000000-0x04_3FFFFFFF R:RGID1/6 W:RGID1/6 */ + [CAAREA3_USED_AREA] = {DRAM_ADDR_AREA12,{0xFFDDFFDDU, 0x00000000U}}, /* Area12 phys:0x04_40000000-0x04_5FFFFFFF R:RGID1/5 W:RGID1/5 */ + [CAAREA2_USED_AREA2] = {DRAM_ADDR_AREA13,{0xFFB9FFB9U, 0x00000000U}}, /* Area13 phys:0x04_60000000-0x04_7FFFFFFF R:RGID1/2/6 W:RGID1/2/6 */ + [CAAREA1_USED_AREA] = {DRAM_ADDR_AREA14,{0xBF90BF90U, 0x00000000U}}, /* Area14 phys:0x04_80000000-0x04_FFFFFFFF R:RGID0/1/2/3/5/6/14 W:RGID0/1/2/3/5/6/14 */ + [CAAREA1_USED_AREA2] = {DRAM_ADDR_AREA15,{0xFFF9FFF9U, 0x00000000U}}, /* Area15 phys:0x05_00000000-0x05_FFFFFFFF R:RGID1/2 W:RGID1/2 */ + [RESERVERD_AREA] = {DRAM_ADDR_AREA16,{0xFFFFFFFFU, 0x00000000U}}, /* Area16 phys:0x06_00000000-0x06_FFFFFFFF */ +#endif /*OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + [17] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [18] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [19] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [20] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [21] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [22] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [23] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [24] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [25] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [26] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [27] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [28] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [29] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [30] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [31] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [32] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [33] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [34] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [35] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [36] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [37] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [38] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [39] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [40] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [41] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [42] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [43] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [44] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [45] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [46] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [47] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [48] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [49] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [50] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [51] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [52] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [53] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [54] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [55] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [56] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [57] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [58] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [59] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [60] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [61] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [62] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, + [63] = {DRAM_ADDR_END, {0x00000000U, 0x00000000U}}, +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX] = { + [0] = {0xEEE80570U, 0x00000002U}, /* IMRGID_IPMMU_VI0 */ + [1] = {0xEEEC0570U, 0x00000002U}, /* IMRGID_IPMMU_VI1 */ + [2] = {0xEEDC0570U, 0x00000002U}, /* IMRGID_IPMMU_VC0 */ + [3] = {0xEED80570U, 0x00000002U}, /* IMRGID_IPMMU_IR */ + [4] = {0xEE480570U, 0x00000001U}, /* IMRGID_IPMMU_RT0 */ + [5] = {0xEE4C0570U, 0x00000001U}, /* IMRGID_IPMMU_RT1 */ + [6] = {0xEED00570U, 0x00000001U}, /* IMRGID_IPMMU_DS0 */ + [7] = {0xEED40570U, 0x00000001U}, /* IMRGID_IPMMU_HSC */ + [8] = {0xEEF00570U, 0x00000002U}, /* IMRGID_IPMMU_VIP0 */ + [9] = {0xEEE00570U, 0x00000002U}, /* IMRGID_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX] = { + [0] = {0xEEE80578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI0 */ + [1] = {0xEEEC0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VI1 */ + [2] = {0xEEDC0578U, 0x00000001U}, /* IMSECGRP_IPMMU_VC0 */ + [3] = {0xEED80578U, 0x00000001U}, /* IMSECGRP_IPMMU_IR */ + [4] = {0xEE480578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT0 */ + [5] = {0xEE4C0578U, 0x00000001U}, /* IMSECGRP_IPMMU_RT1 */ + [6] = {0xEED00578U, 0x00000001U}, /* IMSECGRP_IPMMU_DS0 */ + [7] = {0xEED40578U, 0x00000001U}, /* IMSECGRP_IPMMU_HSC */ + [8] = {0xEEF00578U, 0x00000001U}, /* IMSECGRP_IPMMU_VIP0 */ + [9] = {0xEEE00578U, 0x00000001U}, /* IMSECGRP_IPMMU_3DG */ +}; + +const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX] = { + [0] = {0xEEE80574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI0 */ + [1] = {0xEEEC0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VI1 */ + [2] = {0xEEDC0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VC0 */ + [3] = {0xEED80574U, 0x00000002U}, /* IMRGIDEN_IPMMU_IR */ + [4] = {0xEE480574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT0 */ + [5] = {0xEE4C0574U, 0x00000002U}, /* IMRGIDEN_IPMMU_RT1 */ + [6] = {0xEED00574U, 0x00000002U}, /* IMRGIDEN_IPMMU_DS0 */ + [7] = {0xEED40574U, 0x00000002U}, /* IMRGIDEN_IPMMU_HSC */ + [8] = {0xEEF00574U, 0x00000002U}, /* IMRGIDEN_IPMMU_VIP0 */ + [9] = {0xEEE00574U, 0x00000002U}, /* IMRGIDEN_IPMMU_3DG */ +}; + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/common/log/log.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/common/log/log.c new file mode 100644 index 0000000..315efe0 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/common/log/log.c @@ -0,0 +1,180 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + +/******************************************************************************* + * DESCRIPTION : log + ******************************************************************************/ +/****************************************************************************** + * @file log.c + * - Version : 0.04 + * @brief Access protection setting driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 03.07.2020 0.01 First Release + * : 16.06.2022 0.02 Change log output + * : 31.10.2022 0.03 License notation change. + * : 04.04.2023 0.04 Removed sprintf. + *****************************************************************************/ + +#include "stdarg.h" +#include "stdint.h" +#include "log.h" +#include "scif.h" + +#define NULL_CHAR '\0' + +/*********************************************************** + * log_printf + ***********************************************************/ + +static uint32_t uint32_print(uint32_t num) +{ + uint8_t num_buf[10]; + uint32_t count = 0U; + uint32_t i = 0U; + uint32_t rem; + uint32_t unum = num; + + while (1) { + rem = unum % 10U; + num_buf[i] = (uint8_t)('0' + rem); + + i++; + unum = unum / 10U; + if (unum < 1U) { + break; + } + } + + while (i != 0U) { + i--; + (void)console_putc(num_buf[i]); + count++; + }; + + return count; +} + + +static uint32_t int32_print(int32_t num) +{ + uint32_t unum; + uint32_t count = 0U; + + if (num < 0) { + (void)console_putc((uint8_t)'-'); + count = 1U; + unum = (uint32_t)-num; + } else { + unum = (uint32_t)num; + } + + count += uint32_print(unum); + + return count; +} + + +static uint32_t uint32_hex_print(uint32_t num) +{ + uint32_t i; + uint32_t count = 0U; + uint8_t c; + + for (i = 0U; i < 8U; i++) { + /* 0-F */ + c = (uint8_t)((num >> ((7U - i) * 4U)) & 0x0FU); + if (c >= 0x0AU) { + /* A-F */ + c += (uint8_t)('a' - 0x0AU); + } else { + /* 0-9 */ + c += (uint8_t)'0'; + } + (void)console_putc(c); + count++; + } + + return count; +} + + +static uint32_t str_print(const char *str) +{ + uint32_t count = 0; + + while (*str != NULL_CHAR) { + (void)console_putc((uint8_t)*str); + str++; + count++; + } + + return count; +} + + +void log_printf(const char *fmt, ...) +{ + va_list args; + int32_t num; + uint32_t unum; + char *str; + uint32_t count = 0U; + + va_start(args, fmt); + while (*fmt != NULL_CHAR) { + if (*fmt == '%') { + fmt++; + switch (*fmt) { + case 'i': + /* No break */ + case 'd': + num = va_arg(args, int32_t); + count += int32_print(num); + break; + case 's': + str = va_arg(args, char *); + count += str_print(str); + break; + case 'x': + unum = va_arg(args, uint32_t); + count += uint32_hex_print(unum); + break; + case 'u': + unum = va_arg(args, uint32_t); + count += uint32_print(unum); + break; + default: + break; + } + } else { + (void)console_putc((uint8_t)*fmt); + count++; + } + fmt++; + } + va_end(args); +} diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/common/log/scif.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/common/log/scif.c new file mode 100644 index 0000000..df48279 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/common/log/scif.c @@ -0,0 +1,163 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ +/******************************************************************************* + * DESCRIPTION : SCIF driver + ******************************************************************************/ +/****************************************************************************** + * @file scif.c + * - Version : 0.07 + * @brief 1. Initial setting of SCIF. + * 2. Initial setting of HSCIF. + * 3. Log output function. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 03.09.2021 0.02 Modify the timing of MODEMR judgement. + * : 15.10.2021 0.03 Modify register access to read modify write. + * : 03.12.2021 0.04 Fix incorrect configuration process. + * : 06.01.2022 0.05 Static analysis support + * : 16.06.2022 0.06 Change line feed code + * : 31.10.2022 0.07 License notation change. + *****************************************************************************/ + +#include +#include +#include +#include +#include + +/* Define */ +#define SCIF_SCFSR_TEND (uint16_t)((uint16_t)1U << 6U) +#define SCIF_SCFSR_TDFE (uint16_t)((uint16_t)1U << 5U) +#define TRANS_END_CHECK (uint16_t)(SCIF_SCFSR_TEND | SCIF_SCFSR_TDFE) + + +static void (*rcar_putc)(uint8_t outchar); + +static void scif_console_init(uint32_t modemr); +static void scif_console_putc(uint8_t outchar); +static void hscif_console_putc(uint8_t outchar); + + +static void scif_console_init(uint32_t modemr) +{ + switch(modemr) + { + case MODEMR_HSCIF_DLMODE_3000000: + { + /* Set the pointer to a function that outputs one character. */ + rcar_putc = hscif_console_putc; + break; + } + case MODEMR_HSCIF_DLMODE_1843200: + { + /* Set the pointer to a function that outputs one character. */ + rcar_putc = hscif_console_putc; + break; + } + case MODEMR_HSCIF_DLMODE_921600: + { + /* Set the pointer to a function that outputs one character. */ + rcar_putc = hscif_console_putc; + break; + } + case MODEMR_SCIF_DLMODE: + default: + { + /* Set the pointer to a function that outputs one character. */ + rcar_putc = scif_console_putc; + break; + } + } +} +/* End of function scif_console_init(void) */ + +void scif_init(void) +{ + uint32_t modemr; + + modemr = ((mem_read32(RST_MODEMR0) & RST_MODEMR0_MD31) >> 31U); + modemr |= ((mem_read32(RST_MODEMR1) & RST_MODEMR1_MD32) << 1U); + + scif_console_init(modemr); +} +/* End of function scif_init(void) */ + +void console_putc(uint8_t outchar) +{ + if (outchar == 0x0A) /* \n */ + { + rcar_putc( 0x0D ); /* \r */ + } + rcar_putc(outchar); +} +/* End of function console_putc(void) */ + + +static void scif_console_putc(uint8_t outchar) +{ + uint16_t reg; + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK)) + { + ; + } + + mem_write8(SCIF_SCFTDR, outchar); /* Transfer one character */ + reg = mem_read16(SCIF_SCFSR); + reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */ + mem_write16(SCIF_SCFSR, reg); + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(SCIF_SCFSR)) == TRANS_END_CHECK)) + { + ; + } +} +/* End of function scif_console_putc(uint8_t outchar) */ + +static void hscif_console_putc(uint8_t outchar) +{ + uint16_t reg; + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK)) + { + ; + } + + mem_write8(HSCIF_HSFTDR, outchar); /* Transfer one character */ + reg = mem_read16(HSCIF_HSFSR); + reg &= (uint16_t)(~(TRANS_END_CHECK)); /* TEND,TDFE clear */ + mem_write16(HSCIF_HSFSR, reg); + + /* Check that transfer of SCIF0 is completed */ + while (!((TRANS_END_CHECK & mem_read16(HSCIF_HSFSR)) == TRANS_END_CHECK)) + { + ; + } +} +/* End of function hscif_console_putc(uint8_t outchar) */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/common/string.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/common/string.c new file mode 100644 index 0000000..a44ea10 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/common/string.c @@ -0,0 +1,67 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Standard library + ******************************************************************************/ +/****************************************************************************** + * @file string.c + * - Version : 0.01 + * @brief standard library. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 04.04.2023 0.01 First Release + *****************************************************************************/ + +#include +#include +#include + +void *memcpy(void *dst, const void *src, size_t len) +{ + uint8_t *p1 = (uint8_t *)dst; + const uint8_t *p2 = (const uint8_t *)src; + while(len > 0U) + { + *(p1++) = *(p2++); + len--; + } + return dst; +} +/* End of function memcpy( void* dst, const void* src, size_t n ) */ + +void *memset(void *dst, int val, size_t len) +{ + uint8_t *p = (uint8_t *)dst; + const uint8_t uc = (uint8_t)val; + + while (len > 0U) + { + *p++ = uc; + len--; + } + return (dst); +} +/* End of function memset(void *dst, int val, size_t len) */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/common/timer/generic_timer.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/common/timer/generic_timer.c new file mode 100644 index 0000000..6075807 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/common/timer/generic_timer.c @@ -0,0 +1,177 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + +/******************************************************************************* + * DESCRIPTION : generic timer + ******************************************************************************/ +/****************************************************************************** + * @file generic_timer.c + * - Version : 0.08 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 19.01.2022 0.01 First Release + * : 17.02.2022 0.02 Support AArch32 + * : 09.05.2022 0.03 Supports argument check of micro_wait() + * Moved the definition of the define value + * Removed __ARM_ARCH_8R__ and __ARM_ARCH_8A__ + * Change macro to inline function + * Added initial settings + * Remove unnecessary casts + * Change the value of RCAR_CNTC_EXTAL + * : 16.06.2022 0.04 Change the value of RCAR_CNTC_EXTAL + * : 16.06.2022 0.05 Change log output + * : 31.10.2022 0.06 License notation change. + * : 04.04.2023 0.07 Removed stdio.h. + * : 21.08.2023 0.08 Add support for V4M. + *****************************************************************************/ + +#include +#include +#include +#include + +#if (RCAR_LSI == RCAR_S4) +#define RCAR_CNTC_EXTAL (16666666U) /* 16.666666MHz */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define RCAR_CNTC_EXTAL (16666600U) /* 16.666600MHz */ +#endif /* RCAR_LSI == RCAR_S4 */ +#define CNTFID_OFF (0x0020U) +#define CNTCR_OFF (0x0000U) +#define CNTCR_EN ((1U) << 0U) +#define RCAR_CNTC_BASE (0xE6080000U) +#define RCAR_CONV_MICROSEC (1000000U) +#define RCAR_MAX_WAITTIME (10000000U) +#define RCAR_MIN_WAITTIME (0U) + +#ifdef __aarch64__ +static inline uint64_t get_cntfrq(void) +{ + uint64_t freq; + __asm__ volatile ("mrs %0, cntfrq_el0" : "=r" (freq)); + + return(freq); +} + +static inline void set_cntfrq(uint64_t reg_cntfid) +{ + __asm__ volatile ("msr cntfrq_el0, %0" :: "r" (reg_cntfid)); +} + +static inline uint64_t get_cntpct(void) +{ + uint64_t base_count; + __asm__ volatile ("mrs %0, cntpct_el0" : "=r" (base_count)); + + return(base_count); +} + +#elif __arm__ +static inline uint32_t get_cntfrq(void) +{ + uint32_t freq; + __asm__ volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq)); + + return(freq); +} + +static inline void set_cntfrq(uint32_t reg_cntfid) +{ + __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (reg_cntfid)); +} + +static inline uint64_t get_cntpct(void) +{ + uint64_t base_count; + __asm__ volatile ("mrrc p15, 0, %Q0, %R0, c14" : "=r" (base_count)); + + return(base_count); +} +#endif /* __aarch64__ */ + +void generic_timer_init(void) +{ + /* Update memory mapped and register based freqency */ + /* AArch64:cntfrq_el0 */ + /* AArch32:cntfrq */ + set_cntfrq(RCAR_CNTC_EXTAL); + + mem_write32(RCAR_CNTC_BASE + CNTFID_OFF, RCAR_CNTC_EXTAL); + + /* Enable counter */ + mem_bitset32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_EN); +} +/* End of function generic_timer_init(void) */ + +void micro_wait(uint64_t micro_sec) +{ + uint64_t base_count = 0U; + uint64_t get_count = 0U; + uint64_t wait_time = 0U; +#ifdef __aarch64__ + uint64_t freq = 0U; +#elif __arm__ + uint32_t freq = 0U; +#endif /* __aarch64__ */ + + + if((micro_sec > RCAR_MIN_WAITTIME) && (micro_sec <= RCAR_MAX_WAITTIME)) + { + /* AArch64:cntfrq_el0 */ + /* AArch32:cntfrq */ + freq = get_cntfrq(); + /* AArch64:cntpct_el0 */ + /* AArch32:cntpct */ + base_count = get_cntpct(); + + micro_sec *= freq; + while (micro_sec > wait_time) + { + /* cntpct */ + get_count = get_cntpct(); + + /* INT30-C Pre confirmation */ + if (get_count < base_count) + { + ERROR("micro_wait(Timer value error!!).\n"); + panic; + } + else + { + wait_time = ((get_count - base_count) * RCAR_CONV_MICROSEC); + } + } + } + else + { + ERROR("micro_wait(wait time)\n"); + ERROR("wait time = 0x%x\n", (unsigned int)micro_sec); + panic; + } + +} +/* End of function micro_wait(uint64_t micro_sec) */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/cpu_on/cpu_on.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/cpu_on/cpu_on.c new file mode 100644 index 0000000..b55c36e --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/cpu_on/cpu_on.c @@ -0,0 +1,323 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Power management driver + ******************************************************************************/ +/****************************************************************************** + * @file cpu_on.c + * - Version : 0.12 + * @brief 1. Boot process of ARM CPU core. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 17.02.2022 0.01 First Release + * : 25.02.2022 0.02 Changed to boot Cortex-R on Core 0. + * : 23.03.2022 0.03 Removed unnecessary header file inclusions + * : 09.05.2022 0.04 Removed unnecessary processing + * Removed unnecessary cast + * : 31.10.2022 0.05 License notation change. + * : 21.08.2023 0.06 Add support for V4M. + * : 16.11.2023 0.07 Changed not to execute ASPREG setting + * in case of V4M. + * : 10.09.2024 0.08 Updated Region ID and RAM protection setting + * for QNX. + * : 11.10.2024 0.09 Updated Region ID and RAM protection setting + * for QNX for V4M. + * : 09.12.2024 0.10 Updated OTP_MEM_OTPMONITOR60 register to + * OTP_MEM_OTPMONITOR17 register for V4M. + * And Improve the adj_ca_variant_freq function. + * : 19.12.2024 0.11 Add support for booting CR52 core2. + * : 18.03.2025 0.12 Add INTC initialization process. + *****************************************************************************/ + +#include +#include +#include +#include +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#include "access_protection.h" +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +/* ARM */ +#define CA_CORE0_WUP_REQ (0x00000001U) +#define CA_CORE0_VLD_RVBARP (0x00000001U) +#define CR_BTMD_RBAR (0x00000000U) +#define CR_VLD_BARP (0x00000001U << 0U) +#define CR_BAREN_VALID (0x00000001U << 4U) +#define CRRST (0x00000000U) + +#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 (0x00000001U << 1U) +#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0 (0x00000001U << 0U) +#define AP_CORE_APSREG_CCI500_AUX_ACTDIS (0x00000001U << 0U) +#define AP_CORE_APSREG_P_CCI500_AUX_ASPRTM (0x00000001U << 1U) + +/* APMU */ +#define APMU_BASE (BASE_APMU_ADDR) +#define CORTEX_R_CORE (0U) /* Target is Cortex R52 core0 */ +#define APMU_CRRSTCTRL (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x0304U) /* Cortex-R Reset Control Register0 */ +#define APMU_CRBARP (APMU_BASE + (CORTEX_R_CORE * 0x40U) + 0x033CU) /* Cortex-R Reset Control Register0 */ +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define CORTEX_R_CORE2 (2U) /* Target is Cortex R52 core2 */ +#define APMU_CRRSTCTRL2 (APMU_BASE + (CORTEX_R_CORE2 * 0x40U) + 0x0304U) /* Cortex-R Reset Control Register2 */ +#define APMU_CRBARP2 (APMU_BASE + (CORTEX_R_CORE2 * 0x40U) + 0x033CU) /* Cortex-R Reset Control Register2 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +#define APMU_PWRCTRLC0 (APMU_BASE + 0x0800U) /* Power Control Register for Core 0 */ +#define APMU_RVBARPLC0 (APMU_BASE + 0x0838U) /* Reset Vector Base Address Register Protected Low for Core 0 */ +#define APMU_RVBARPHC0 (APMU_BASE + 0x083CU) /* Reset Vector Base Address Register Protected High for Core 0 */ + +#define AP_CORE_BASE (BASE_AP_CORE_ADDR) /* 0xE6280000 */ + +#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0(x) (AP_CORE_BASE + 0x00000010U + ((uint8_t)(x) * 0x1000U)) +#define AP_CORE_APSREG_CCI500_AUX (AP_CORE_BASE + 0x00009010U) +#define AP_CORE_APSREG_P_CCI500_AUX (AP_CORE_BASE + 0x00029010U) + +#define AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT (AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS1 | AP_CORE_APSREG_AP_CLUSTER_N_AUX0_ACTDIS0) + +#if (RCAR_LSI == RCAR_V4H) +#define V4H_5_NI_CA (0x53U) /* 1400[MHz] = 50/3[MHz] x (0x53 + 0x1) */ +#define V4H_3_NI_CA (0x5FU) /* 1600[MHz] = 50/3[MHz] x (0x5F + 0x1) */ +#elif (RCAR_LSI == RCAR_V4M) +#define V4M_5_NI_CA (0x5FU) /* 3200/4[MHz] = 50/3[MHz] x (0x5F + 0x1) */ +#define V4M_3_NI_CA (0x6FU) /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */ +#define V4M_2_NI_CA (0x6FU) /* 3732/4[MHz] = 50/3[MHz] x (0x6F + 0x1) */ +#endif /* RCAR_LSI == RCAR_V4H */ + +#define CPG_PLL2CR0_KICK_BIT (0x80000000U) +#define CPG_PLLECR_PLL2ST_BIT (0x00000200U) + +#if (RCAR_LSI == RCAR_V4M) +#define CPG_BASE (BASE_CPG_ADDR) +#define CPG_SRSTCLR5 (CPG_BASE + 0x2C94U) +#define CPG_SRSTCLR11 (CPG_BASE + 0x2CACU) +#define CPG_MSTPCR5 (CPG_BASE + 0x2D14U) +#define CPG_SRSTCLR5_VAL (0x80000000U) +#define CPG_SRSTCLR11_VAL (0x00080000U) +#define CPG_MSTPCR5_VAL (0x80000000U) +#endif /* RCAR_LSI == RCAR_V4M */ + +static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr); +#if (RCAR_LSI == RCAR_V4M) +static void intc_init(void); +#endif /* RCAR_LSI == RCAR_V4M */ + +static void arm_cpu_set_address(uint32_t target, uint32_t boot_addr) +{ + if(RCAR_PWR_TARGET_CR == target) + { + /* CR52 core0 Boot address set */ + mem_write32(APMU_CRBARP, (boot_addr | CR_VLD_BARP)); + mem_write32(APMU_CRBARP, (boot_addr | CR_VLD_BARP | CR_BAREN_VALID)); + } +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + else if(RCAR_PWR_TARGET_CR2 == target) + { + /* CR52 core2 Boot address set */ + mem_write32(APMU_CRBARP2, (boot_addr | CR_VLD_BARP)); + mem_write32(APMU_CRBARP2, (boot_addr | CR_VLD_BARP | CR_BAREN_VALID)); + } +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + else + { + /* CA Boot address set */ + mem_write32(APMU_RVBARPLC0, boot_addr | CA_CORE0_VLD_RVBARP); +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + mem_write32(APMU_RVBARPHC0, 0x00000020U); /* CA boot address 0x20_XXXXXXXX */ +#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE) + mem_write32(APMU_RVBARPHC0, 0x00000000U); +#endif +#else + mem_write32(APMU_RVBARPHC0, 0x00000000U); +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + } +} +/* End of function arm_cpu_set_address(uint32_t target, uint32_t boot_addr) */ + +void arm_cpu_on(uint32_t target, uint32_t boot_addr) +{ + uint32_t res_data; + + if(RCAR_PWR_TARGET_CR == target) + { + /* CR Boot address set. */ + arm_cpu_set_address(target, boot_addr); + + /* CR reset. */ + mem_write32(APMU_CRRSTCTRL, CRRST); + } +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + else if(RCAR_PWR_TARGET_CR2 == target) + { + /* CR Boot address set. */ + arm_cpu_set_address(target, boot_addr); + + /* CR reset. */ + mem_write32(APMU_CRRSTCTRL2, CRRST); + } +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + else + { +#if (RCAR_LSI == RCAR_V4M) + /* For the initial setting flow of INTC, see Section 15.4.5 in + * "R-Car Series, V4M Series User's Manual". + */ + /* INTC initialize */ + intc_init(); +#endif /* RCAR_LSI == RCAR_V4M */ + + /* CA Boot address set. */ + arm_cpu_set_address(target, boot_addr); + +#if (RCAR_LSI == RCAR_V4H) + /* + * In case of V4M, doesn't execute following process at Cx 2nd IPL. + * Because following register setting is needed to execute before C4 power on. + */ + /* AP-System core initialize */ + res_data = mem_read32(AP_CORE_APSREG_AP_CLUSTER_N_AUX0(0U)); + res_data |= AP_CORE_APSREG_AP_CLUSTER_N_AUX0_INIT; + mem_write32(AP_CORE_APSREG_AP_CLUSTER_N_AUX0(0U), res_data); + + res_data = mem_read32(AP_CORE_APSREG_CCI500_AUX); + res_data |= AP_CORE_APSREG_CCI500_AUX_ACTDIS; + mem_write32(AP_CORE_APSREG_CCI500_AUX, res_data); + /* AP_CORE_APSREG_P_CCI500_AUX setting is only for V4H. */ + res_data = mem_read32(AP_CORE_APSREG_P_CCI500_AUX); + res_data |= AP_CORE_APSREG_P_CCI500_AUX_ASPRTM; + mem_write32(AP_CORE_APSREG_P_CCI500_AUX, res_data); +#endif /* RCAR_LSI == RCAR_V4H */ + /* CA core0 wake up sequence. */ + mem_write32(APMU_PWRCTRLC0, CA_CORE0_WUP_REQ); + /* Wait until CA core0 wake up sequence finished. */ + do + { + res_data = mem_read32(APMU_PWRCTRLC0); + }while(CA_CORE0_WUP_REQ & res_data); + } +} +/* End of function arm_cpu_on(uint32_t target, uint32_t boot_addr) */ + +void adj_ca_variant_freq(void) +{ + uint32_t product = mem_read32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK; + uint32_t pll2_freq = mem_read32(CPG_PLL2CR0); + +#if (RCAR_LSI == RCAR_V4H) + /* Set the CPU frequency division ratio according to the type of variant. */ + switch (product) + { + case VARIANT_V4H_7: + /* Default value, do nothing */; + break; + case VARIANT_V4H_5: + pll2_freq = (pll2_freq & ~(0xFFU << 20U)); + pll2_freq = (pll2_freq | (V4H_5_NI_CA << 20U)); + break; + case VARIANT_V4H_3: + pll2_freq = (pll2_freq & ~(0xFFU << 20U)); + pll2_freq = (pll2_freq | (V4H_3_NI_CA << 20U)); + break; + default: + ; /* Do nothing */ + break; + } + + if (VARIANT_V4H_5 == product || VARIANT_V4H_3 == product) + { + /* Write Division value to FRQCRC0 register */ + mem_write32(CPG_CPGWPR, ~(pll2_freq)); + mem_write32(CPG_PLL2CR0, pll2_freq); + + mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT)); + mem_write32(CPG_PLL2CR0, (mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT)); + + while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL2ST_BIT) != CPG_PLLECR_PLL2ST_BIT) + { + ; + } + } +#elif (RCAR_LSI == RCAR_V4M) + /* Set the CPU frequency division ratio according to the type of variant. */ + switch (product) + { + case VARIANT_V4M_7: + /* Default value, do nothing */; + break; + case VARIANT_V4M_5: + pll2_freq = (pll2_freq & ~(0xFFU << 20U)); + pll2_freq = (pll2_freq | (V4M_5_NI_CA << 20U)); + break; + case VARIANT_V4M_3: + pll2_freq = (pll2_freq & ~(0xFFU << 20U)); + pll2_freq = (pll2_freq | (V4M_3_NI_CA << 20U)); + break; + case VARIANT_V4M_2: + pll2_freq = (pll2_freq & ~(0xFFU << 20U)); + pll2_freq = (pll2_freq | (V4M_2_NI_CA << 20U)); + break; + default: + ; /* Do nothing */ + break; + } + + if (VARIANT_V4M_5 == product || VARIANT_V4M_3 == product || VARIANT_V4M_2 == product) + { + /* Write Division value to FRQCRC0 register */ + mem_write32(CPG_CPGWPR, ~(pll2_freq)); + mem_write32(CPG_PLL2CR0, pll2_freq); + + mem_write32(CPG_CPGWPR, ~(mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT)); + mem_write32(CPG_PLL2CR0, (mem_read32(CPG_PLL2CR0) | CPG_PLL2CR0_KICK_BIT)); + + while ((mem_read32(CPG_PLLECR) & CPG_PLLECR_PLL2ST_BIT) != CPG_PLLECR_PLL2ST_BIT) + { + ; + } + } +#endif /* RCAR_LSI == RCAR_V4H */ +} +/* End of function adj_cpu_variant_freq(void) */ + +#if (RCAR_LSI == RCAR_V4M) +static void intc_init(void) +{ + uint32_t reg; + + mem_write32(CPG_CPGWPR, ~(CPG_SRSTCLR5_VAL)); + mem_write32(CPG_SRSTCLR5, CPG_SRSTCLR5_VAL); + + mem_write32(CPG_CPGWPR, ~(CPG_SRSTCLR11_VAL)); + mem_write32(CPG_SRSTCLR11, CPG_SRSTCLR11_VAL); + + mem_write32(CPG_CPGWPR, ~(CPG_MSTPCR5_VAL)); + reg = mem_read32(CPG_MSTPCR5); + reg |= CPG_MSTPCR5_VAL; + mem_write32(CPG_MSTPCR5, reg); +} +/* End of function intc_init(void) */ +#endif /* RCAR_LSI == RCAR_V4M */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/image_load/image_load.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/image_load/image_load.c new file mode 100644 index 0000000..04f4b9c --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/image_load/image_load.c @@ -0,0 +1,465 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file image_load.c + * - Version : 0.11 + * @brief Access protection setting driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.11.2021 0.01 First Release + * : 10.02.2022 0.02 Updated eMMC driver + * Removed the comment + * Change the line feed code of log output + * Change the number of CA programs + * : 17.02.2022 0.03 Support AArch32 + * : 22.03.2022 0.04 Support for GSCE[3.3b] + * : 11.05.2022 0.05 Used the standard library + * Integrated LOAD_INFO + * Changed image_name table + * Changed check_load_area + * - Change RAM check process + * - Change address check process + * - Add Image check process + * - Processing integration + * Changed to processing for each device + * Change structure member name + * Added function return value judgment + * Changed LOGICAL_CONTENT_CERT_ADDR to + * get_logic_cont_cert_addr + * Changed uint32_t to uintptr_t + * Change log output + * Add argument of load_init() + * Change to error when key information is invalid + * Remove unnecessary type conversion + * : 11.07.2022 0.06 Change log output + * Support secure boot for S4 + * Change load start processing other than 512byte align + * : 02.09.2022 0.07 Added 512byte boundary check + * : 31.10.2022 0.08 License notation change. + * : 21.08.2023 0.09 Add support for V4M. + * : 19.12.2024 0.10 Add support for RTOS#1 and RTOS#2. + * : 26.05.2025 0.11 Change key cert address of [CA_OPTIONAL_ID+2]. +*****************************************************************************/ +/* indelude */ +#include +#include +#include +#include + +#include +#include + +#define KEY_SIZE_FLG_MSK (0x00000003U) +#define KEY_SIZE_BIT_SHIFT (21U) +#define CERT_INFO_FLG_OFFSET (0x0000000CU) +#define KEY_SIZE_4096 (0x00000002U) +#define KEY_SIZE_3072 (0x00000001U) +#define KEY_SIZE_2048 (0x00000000U) +#define WORD_TO_BYTE (4U) +#define NOT_OVERLAP_FLAG (0U) +#define OVERLAP_FLAG (1U) +#define RAM_RANGE_OK (0U) +#define RAM_RANGE_NG (1U) +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1) +#define RAM_MAX (4U) +#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RAM_MAX (5U) /* ++ SRAM in RT-VRAM (0xE2000000 - 0xE200FFFF) */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +#define ADDRESS_RANGE_512 (512U) + +static void check_load_area(LOAD_INFO* li); +static void get_info_from_cert(uint32_t cert_addr, uint32_t *size, + uint32_t *dest_addr); + +void load_image(LOAD_INFO* li) +{ + /* log output of load image for information */ + load_image_info_print_for_emmc(li); + + /* Check transfer range of image. */ + check_load_area(li); + + /* Image load start. */ + load_start(li); +} +/* End of function load_image(LOAD_INFO* li) */ + +void load_init(LOAD_INFO* li, uint32_t num) +{ + uint32_t loop; + uintptr_t buf; + + const char *image_name[MAX_PLACED] = { +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + [RTOS_ID] = "RTOS", +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + [CA_OPTIONAL_ID] = "CA Program #1", + [CA_OPTIONAL_ID + 1] = "CA Program #2", + [CA_OPTIONAL_ID + 2] = "CA Program #3", + [CA_OPTIONAL_ID + 3] = "CA Program #4", + [CA_OPTIONAL_ID + 4] = "CA Program #5", + [CA_OPTIONAL_ID + 5] = "CA Program #6", + [CA_OPTIONAL_ID + 6] = "CA Program #7", + [CA_OPTIONAL_ID + 7] = "CA Program #8", +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + [RTOS1_ID] = "RTOS#1", + [RTOS2_ID] = "RTOS#2", +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + }; + + const uint32_t key_cert[MAX_PLACED] = { +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + [RTOS_ID] = TFMV_KEY_CERT_ADDR, +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + [CA_OPTIONAL_ID] = TFMV_KEY_CERT_ADDR, +#if (RCAR_LSI == RCAR_S4) + [CA_OPTIONAL_ID + 1] = TFMV_KEY_CERT_ADDR, +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + [CA_OPTIONAL_ID + 1] = NTFMV_KEY_CERT_ADDR, +#endif +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + [CA_OPTIONAL_ID + 2] = NTFMV_KEY_CERT_ADDR, +#else + [CA_OPTIONAL_ID + 2] = TFMV_KEY_CERT_ADDR, +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + [CA_OPTIONAL_ID + 3] = NTFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID + 4] = NTFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID + 5] = NTFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID + 6] = NTFMV_KEY_CERT_ADDR, + [CA_OPTIONAL_ID + 7] = NTFMV_KEY_CERT_ADDR, +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + [RTOS1_ID] = TFMV_KEY_CERT_ADDR, + [RTOS2_ID] = TFMV_KEY_CERT_ADDR, +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + }; + + + if (num >= 1U && num <= 8U) + { + /* Set Load info parameter */ + for (loop = CA_OPTIONAL_ID; loop < CA_OPTIONAL_ID + num; loop++) + { + li[loop].name = image_name[loop]; + li[loop].key_cert_addr = key_cert[loop]; + li[loop].cnt_cert_addr = get_logic_cont_cert_addr(loop); + get_info_from_cert(li[loop].cnt_cert_addr, &li[loop].image_size, &li[loop].boot_addr); + buf = get_src_addr_offset_in_cert(loop); + li[loop].src_addr = (SRC_TOP + mem_read32(buf)); + buf = get_part_num_in_cert(loop); + li[loop].part_num = mem_read32(buf); + li[loop].load_id = loop; + } + } + else + { + ERROR("load_init(CA program num error).\n"); + panic; + } + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + li[RTOS_ID].name = image_name[RTOS_ID]; + li[RTOS_ID].key_cert_addr = key_cert[RTOS_ID]; + li[RTOS_ID].cnt_cert_addr = get_logic_cont_cert_addr(RTOS_ID); + get_info_from_cert(li[RTOS_ID].cnt_cert_addr, &li[RTOS_ID].image_size, &li[RTOS_ID].boot_addr); + buf = get_src_addr_offset_in_cert(RTOS_ID); + li[RTOS_ID].src_addr = (SRC_TOP + mem_read32(buf)); + buf = get_part_num_in_cert(RTOS_ID); + li[RTOS_ID].part_num = mem_read32(buf); + li[RTOS_ID].load_id = RTOS_ID; + + #if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + /* Set Load info parameter for RTOS#1 and RTOS#2 */ + for (loop = RTOS1_ID; loop <= RTOS2_ID; loop++) + { + li[loop].name = image_name[loop]; + li[loop].key_cert_addr = key_cert[loop]; + li[loop].cnt_cert_addr = get_logic_cont_cert_addr(loop); + get_info_from_cert(li[loop].cnt_cert_addr, &li[loop].image_size, &li[loop].boot_addr); + buf = get_src_addr_offset_in_cert(loop); + li[loop].src_addr = (SRC_TOP + mem_read32(buf)); + buf = get_part_num_in_cert(loop); + li[loop].part_num = mem_read32(buf); + li[loop].load_id = loop; + } + #endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + +}/* End of function load_init(LOAD_INFO* li) */ + + +static void check_load_area(LOAD_INFO* li) +{ + uint32_t src; + uint32_t dst; + uint32_t len; + uint32_t dst_end; + uint32_t overlap; + uint32_t loop; + uint32_t rge_chk_flg; + static uint32_t s_num = 1U; + + /* The memory range of destination. */ + const ADDRESS_RANGE add_list[RAM_MAX] = { + [TARGET_MEM_DRAM] = {DRAM_BASE, DRAM_END}, + [TARGET_MEM_RTSRAM] = {RTSRAM_BASE, RTSRAM_END}, + [TARGET_MEM_RTVRAM] = {RTVRAM_VBUF_TOP, RTVRAM_VBUF_END}, + [TARGET_MEM_SYSRAM] = {SYSRAM_BASE, SYSRAM_END}, +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + [TARGET_MEM_SRAM_IN_RTVRAM] = {RTVRAM_SRAM_TOP, RTVRAM_SRAM_END}, +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + }; + + /* The image range check */ + const IMAGE_RANGE size_list[CA_IMAGESIZECHK_DEF] = { + { CA_PROGRAM1_ID, CA_PROGRAM1_ADR, CA_PROGRAM1_SIZE}, + { CA_PROGRAM2_ID, CA_PROGRAM2_ADR, CA_PROGRAM2_SIZE}, +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) + { CA_PROGRAM3_ID, CA_PROGRAM3_ADR, CA_PROGRAM3_SIZE}, +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ + }; + + static ADDRESS_RANGE s_placed_image[MAX_PLACED] = { + [0] = {IPL_TOP, IPL_END} + }; + + + src = li->src_addr; + dst = li->boot_addr; + len = li->image_size; + + /* Check image size */ + if (len == 0U) + { + ERROR("image size error\n"); + panic; + } + + /* Check whether source is overflow */ + /* INT30-C Pre confirmation */ + if (src > (UINT32_MAX - len)) + { + ERROR("1:overflow is occurred at source\n"); + ERROR("1:source address = 0x%x image size = 0x%x\n", (unsigned int)src, (unsigned int)len); + panic; + } + + /* Check whether destination is overflow */ + /* INT30-C Pre confirmation */ + if (dst > (UINT32_MAX - len)) + { + ERROR("1:overflow is occurred at destination\n"); + ERROR("1:destination address = 0x%x image size = 0x%x\n", (unsigned int)dst, + (unsigned int)len); + panic; + } + else + { + dst_end = dst + len - 1U; + } + + /* Check source address range. */ + /* No error check is performed because it is detected by the eMMC device */ + + /* Check destination address range. */ + + /* 512byte boundary check */ + if (0U != (dst % ADDRESS_RANGE_512)) + { + ERROR("check_load_area (destination address)\n"); + ERROR("destination address = 0x%x \n", (unsigned int)dst); + panic; + } + + /* range check */ + rge_chk_flg = RAM_RANGE_NG; + + for(loop = 0U; loop < RAM_MAX; loop++) + { + if (add_list[loop].cx_topadd <= dst) + { + if(dst_end <= add_list[loop].cx_endadd) + { + rge_chk_flg = RAM_RANGE_OK; + break; + } + } + } + + if(rge_chk_flg != RAM_RANGE_OK) + { + ERROR("check_load_area (destination address)\n"); + ERROR("destination address = 0x%x image size = 0x%x\n", (unsigned int)dst, + (unsigned int)len); + panic; + } + + /* Check whether destination is overflow */ + for (loop = 0U; loop < CA_IMAGESIZECHK_DEF; loop++) + { + if (li->load_id == size_list[loop].load_id) + { + if ((size_list[loop].image_adr != 0U) && (dst != size_list[loop].image_adr)) + { + ERROR("check load area.(outside secure area)\n"); + ERROR("destination address = 0x%x image size = 0x%x\n", (unsigned int)dst, + (unsigned int)len); + panic; + } + if ((size_list[loop].image_size != 0U) && (len > size_list[loop].image_size)) + { + ERROR("check load area.(outside secure area)\n"); + ERROR("destination address = 0x%x image size = 0x%x\n", (unsigned int)dst, + (unsigned int)len); + panic; + } + } + } + + /* Check there are no overlaps the image that will be loaded and + the images that have already loaded. */ + overlap = NOT_OVERLAP_FLAG; + loop = 0U; + do + { + /* check overlap */ + if ((dst >= s_placed_image[loop].cx_topadd) + && (dst <= s_placed_image[loop].cx_endadd)) + { + overlap = OVERLAP_FLAG; + } + else if ((dst_end >= s_placed_image[loop].cx_topadd) + && (dst_end <= s_placed_image[loop].cx_endadd)) + { + overlap = OVERLAP_FLAG; + } + else if ((dst < s_placed_image[loop].cx_topadd) + && (s_placed_image[loop].cx_endadd < dst_end)) + { + overlap = OVERLAP_FLAG; + } + else + { + loop++; + } + } while ((loop < s_num) && (overlap == NOT_OVERLAP_FLAG)); + + /* Check the overlap flag. + Parameter error if overwrite occurred. + Otherwise, add parameters of the image to be loaded into + Placed_image. */ + if (overlap == NOT_OVERLAP_FLAG) + { + s_placed_image[s_num].cx_topadd = dst; + s_placed_image[s_num].cx_endadd = dst_end; + s_num++; + } + else + { + ERROR("check load area (overlap)\n"); + ERROR("destination address = 0x%x image size = 0x%x\n", (unsigned int)dst, (unsigned int)len); + ERROR("overlapped image is [%u]\n", (unsigned int)loop); + ERROR("top address = 0x%x end address = 0x%x\n", + (unsigned int)s_placed_image[loop].cx_topadd, (unsigned int)s_placed_image[loop].cx_endadd); + panic; + } +} +/* End of function check_load_area(uint32_t dst, uint32_t src, uint32_t len) */ + +static void get_info_from_cert(uint32_t cert_addr, uint32_t *size, + uint32_t *dest_addr) +{ + uint32_t val; + uint32_t certInfo1; + uintptr_t pSize; + uintptr_t pDestL; + + /* Get key length of content certificate. */ + val = mem_read32((uintptr_t)cert_addr + CERT_INFO_FLG_OFFSET); + certInfo1 = (val >> KEY_SIZE_BIT_SHIFT) & KEY_SIZE_FLG_MSK; + + /* Get the transfer address and transfer size from + the certificate in accordance with the key length. */ + if (KEY_SIZE_4096 == certInfo1) /* key size = 4096 */ + { + pSize = cert_addr + CERT_INFO_SIZE_OFFSET2; + *size = mem_read32(pSize) * WORD_TO_BYTE; + pDestL = cert_addr + CERT_INFO_DST_OFFSET2; + *dest_addr = mem_read32(pDestL); + } + else if (KEY_SIZE_3072 == certInfo1) /* key size = 3072 */ + { + pSize = cert_addr + CERT_INFO_SIZE_OFFSET1; + *size = mem_read32(pSize) * WORD_TO_BYTE; + pDestL = cert_addr + CERT_INFO_DST_OFFSET1; + *dest_addr = mem_read32(pDestL); + } + else if (KEY_SIZE_2048 == certInfo1) /* key size = 2048 */ + { + pSize = cert_addr + CERT_INFO_SIZE_OFFSET; + *size = mem_read32(pSize) * WORD_TO_BYTE; + pDestL = cert_addr + CERT_INFO_DST_OFFSET; + *dest_addr = mem_read32(pDestL); + } + else + { + ERROR("get_info_from_cert key size error.\n"); + panic; + } +} +/* End of function get_info_from_cert(uint32_t cert_addr, uint32_t *size, uint32_t *dest_addr) */ + +void load_start(LOAD_INFO* li) +{ + uint32_t rtn_val = EMMC_DEV_ERR; + uint32_t sector_count; + uint32_t fraction; + + /* Converted to number of sectors transferred. */ + sector_count = li->image_size >> CX_EMMC_SECTOR_SIZE_SHIFT; + + fraction = li->image_size % CX_EMMC_SECTOR_SIZE; + /* Add 1 if there is a fraction */ + if(0U != fraction) + { + sector_count += 1U; + } + + rtn_val = emmc_trans_data(li->part_num, (uintptr_t)(li->src_addr >> CX_EMMC_SECTOR_SIZE_SHIFT), + (uintptr_t)li->boot_addr, sector_count); + + if(EMMC_DEV_OK != rtn_val) + { + ERROR("load_start(emmc_trans_data error).\n"); + panic; + } +} +/* End of function load_start(LOAD_INFO* li) */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/access_protection.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/access_protection.h new file mode 100644 index 0000000..222ccf9 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/access_protection.h @@ -0,0 +1,37 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2022-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Region ID function header + ******************************************************************************/ + +#ifndef REGION_ID_H__ +#define REGION_ID_H__ + +#define PROTECTION_DISABLE (0U) +#define PROTECTION_ENABLE (1U) + +void rgid_protection_check(void); +void ram_protection_check(void); + +#endif /* REGION_ID_H__ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/axmm_register.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/axmm_register.h new file mode 100644 index 0000000..b3a6c8a --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/axmm_register.h @@ -0,0 +1,73 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : AXMM register header + ******************************************************************************/ + +#ifndef AXMM_REGISTER_H__ +#define AXMM_REGISTER_H__ + +#include + +/* System RAM / SDRAM register base address */ +#define AXMM_BASE (0xE6780000U) + +#define AXMM_DPTDIVCR (AXMM_BASE + 0x6000U) +#define AXMM_DPTRGNCR (AXMM_BASE + 0x6100U) +#define AXMM_DPTSECCR (AXMM_BASE + 0x6200U) +#define AXMM_SPTDIVCR (AXMM_BASE + 0x6300U) +#define AXMM_SPTRGNCR (AXMM_BASE + 0x6400U) +#define AXMM_SPTSECCR (AXMM_BASE + 0x6500U) + +static inline uint32_t get_dptdivcr_addr(uint32_t num) +{ + return ((AXMM_DPTDIVCR + (num * 4U))); +} + +static inline uint32_t get_dptrgncr_addr(uint32_t num) +{ + return ((AXMM_DPTRGNCR + (num * 4U))); +} + +static inline uint32_t get_dptseccr_addr(uint32_t num) +{ + return ((AXMM_DPTSECCR + (num * 4U))); +} + +static inline uint32_t get_sptdivcr_addr(uint32_t num) +{ + return ((AXMM_SPTDIVCR + (num * 4U))); +} + +static inline uint32_t get_sptrgncr_addr(uint32_t num) +{ + return ((AXMM_SPTRGNCR + (num * 4U))); +} + +static inline uint32_t get_sptseccr_addr(uint32_t num) +{ + return ((AXMM_SPTSECCR + (num * 4U))); +} + +#endif /* AXMM_REGISTER_H__ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/cnf_tbl.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/cnf_tbl.h new file mode 100644 index 0000000..9691245 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/cnf_tbl.h @@ -0,0 +1,126 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2021-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Configuration table header + ******************************************************************************/ + +#ifndef CNF_TBL_H_ +#define CNF_TBL_H_ + +#include + +typedef struct{ + uint64_t fix; + uint64_t be; +} QOS_SETTING_TABLE; + +typedef struct{ + uint32_t phys_addr; /* Physical address of Region ID registers. */ + uint32_t value; /* setting value of Region ID registers. */ +} REGION_ID_SETTING_TABLE; + +/* For RAM protection table */ +typedef struct { + uint32_t rw_val; + uint32_t sec_val; +}RAM_PROTECTION_VALUE_FORMAT; + +typedef struct { + uint32_t read_val; + uint32_t write_val; +}RTRAM_PROTECTION_VALUE_FORMAT; + +typedef struct { + uint32_t addr; + RTRAM_PROTECTION_VALUE_FORMAT setting_value; +}RTRAM_PROTECTION_STRUCTUR; + +typedef struct { + uint32_t addr; + RAM_PROTECTION_VALUE_FORMAT setting_value; +}SYSTEM_RAM_PROTECTION_STRUCTUR; + +typedef struct { + uint64_t addr; + RAM_PROTECTION_VALUE_FORMAT setting_value; +}DRAM_PROTECTION_STRUCTUR; + + +#if (RCAR_LSI == RCAR_S4) +#define QOS_TBL_MAX (48U) /* Max setting number of QoS Bank registers. */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define QOS_TBL_MAX (125U) /* Max setting number of QoS Bank registers. */ +#endif /* RCAR_LSI == RCAR_S4 */ + +#if (RCAR_LSI == RCAR_V4H) +#define RGID_MASTER_MAX (77U) /* Max number of Region registers. (Master) */ +#define RGID_READ_MAX (908U) /* Max number of Region registers. (Read) */ +#define RGID_WRITE_MAX (907U) /* Max number of Region registers. (Write) */ +#define RGID_SEC_MAX (957U) /* Max number of Region registers. (Secure) */ +#define RGID_AXI_MAX (98U) /* Max number of Region registers. (Read/Write for AXI-bus) */ +#elif (RCAR_LSI == RCAR_V4M) +#define RGID_MASTER_MAX (85U) /* Max number of Region registers. (Master) */ +#define RGID_READ_MAX (805U) /* Max number of Region registers. (Read) */ +#define RGID_WRITE_MAX (804U) /* Max number of Region registers. (Write) */ +#define RGID_SEC_MAX (819U) /* Max number of Region registers. (Secure) */ +#define RGID_AXI_MAX (90U) /* Max number of Region registers. (Read/Write for AXI-bus) */ +#endif /* RCAR_LSI == RCAR_V4H */ + +#define RAM_PROTECTION_MAX (16U) /* Max number of RAM Protection registers. (RT-VRAM0/RT-VRAM1/SystemRAM) */ +#define DRAM_PROTECTION_MAX (64U) /* Max number of RAM Protection registers. (SDRAM) */ + +#if (RCAR_LSI == RCAR_V4H) +#define IMP_MASTER_MAX (19U) +#define IMP_SLAVE_MAX (38U) +#endif /* (RCAR_LSI == RCAR_V4H) */ + +#if (RCAR_LSI == RCAR_V4H) +#define IPMMU_RGID_MAX (11U) +#elif (RCAR_LSI == RCAR_V4M) +#define IPMMU_RGID_MAX (10U) +#endif /* (RCAR_LSI == RCAR_V4H) */ + +extern const QOS_SETTING_TABLE g_qosbw_tbl[QOS_TBL_MAX]; +extern const QOS_SETTING_TABLE g_qoswt_tbl[QOS_TBL_MAX]; + +extern const REGION_ID_SETTING_TABLE g_rgid_master_tbl[RGID_MASTER_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_read_tbl[RGID_READ_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_write_tbl[RGID_WRITE_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_sec_tbl[RGID_SEC_MAX]; +extern const REGION_ID_SETTING_TABLE g_rgid_axi_tbl[RGID_AXI_MAX]; +#if (RCAR_LSI == RCAR_V4H) +extern const REGION_ID_SETTING_TABLE g_imp_rgid_m_tbl[IMP_MASTER_MAX]; +extern const REGION_ID_SETTING_TABLE g_imp_rgid_s_tbl[IMP_SLAVE_MAX]; +#endif /* (RCAR_LSI == RCAR_V4H) */ +extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_tbl[IPMMU_RGID_MAX]; +extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_sec_tbl[IPMMU_RGID_MAX]; +extern const REGION_ID_SETTING_TABLE g_ipmmu_rgid_en_tbl[IPMMU_RGID_MAX]; + +/* For RAM protection */ +extern const RTRAM_PROTECTION_STRUCTUR g_rtvram0_protection_table[RAM_PROTECTION_MAX]; +extern const RTRAM_PROTECTION_STRUCTUR g_rtvram1_protection_table[RAM_PROTECTION_MAX]; +extern const SYSTEM_RAM_PROTECTION_STRUCTUR g_system_ram_protection_table[RAM_PROTECTION_MAX]; +extern const DRAM_PROTECTION_STRUCTUR g_dram_protection_table[DRAM_PROTECTION_MAX]; + +#endif /* CNF_TBL_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/cpu_on.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/cpu_on.h new file mode 100644 index 0000000..ded7680 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/cpu_on.h @@ -0,0 +1,75 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : cpu on function header + ******************************************************************************/ +/****************************************************************************** + * @file cpu_on.h + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 17.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + * : 09.12.2024 0.03 Remove OTP_MEM_OTPMONITOR60 register. + * : 19.12.2024 0.04 Add definition for booting CR52 core 2. +*****************************************************************************/ + +#ifndef CPU_ON_H__ +#define CPU_ON_H__ + +#include "image_load.h" + +#define RCAR_PWR_TARGET_CR (0U) +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RCAR_PWR_TARGET_CR2 (2U) +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +#define RCAR_PWR_TARGET_CA (1U) + + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void arm_cpu_on(uint32_t target, uint32_t boot_addr); +void adj_ca_variant_freq(void); + +#define OTP_MEM_1_BASE (0xE61BF000U) +#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U) +#define OTP_MEM_PRODUCT_MASK (0x000000FFU) +#if (RCAR_LSI == RCAR_V4H) +#define VARIANT_V4H_7 (0x00U) +#define VARIANT_V4H_5 (0x01U) +#define VARIANT_V4H_3 (0x02U) +#elif (RCAR_LSI == RCAR_V4M) +#define VARIANT_V4M_7 (0x00U) +#define VARIANT_V4M_5 (0x01U) +#define VARIANT_V4M_3 (0x02U) +#define VARIANT_V4M_2 (0x04U) +#endif /* RCAR_LSI == RCAR_V4H */ + +#endif /* CPU_ON_H__ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_boot.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_boot.h new file mode 100644 index 0000000..94cb5ef --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_boot.h @@ -0,0 +1,46 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc boot header + ******************************************************************************/ +/****************************************************************************** + * @file emmc_boot.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +#ifndef EMMC_BOOT_ +#define EMMC_BOOT_ + +void emmc_initialize( void ); + +#endif /* EMMC_BOOT_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_config.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_config.h new file mode 100644 index 0000000..88305b6 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_config.h @@ -0,0 +1,68 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc config header + ******************************************************************************/ +/****************************************************************************** + * @file emmc_config.h + * - Version : 0.03 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 18.03.2022 0.02 Delete unnecessary define + * Delete unnecessary include file + * : 31.10.2022 0.03 License notation change. + *****************************************************************************/ + +#ifndef EMMC_CONFIG_H__ +#define EMMC_CONFIG_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* MMC driver config */ +#define EMMC_RCA (1U) /* RCA */ +#define EMMC_RW_DATA_TIMEOUT (0x40U) /* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */ +#define EMMC_CMD_MAX (60U) /* Don't change. */ + +/* etc */ +#define LOADIMAGE_FLAGS_DMA_ENABLE (0x00000001U) + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* #ifndef EMMC_CONFIG_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_def.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_def.h new file mode 100644 index 0000000..59aadd2 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_def.h @@ -0,0 +1,84 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc def header + ******************************************************************************/ +/****************************************************************************** + * @file emmc_def.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +#ifndef EMMC_DEF_H__ +#define EMMC_DEF_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_std.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ +extern st_mmc_base mmc_drv_obj; + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* eMMC driver API */ +EMMC_ERROR_CODE emmc_init(void); +EMMC_ERROR_CODE emmc_terminate(void); +EMMC_ERROR_CODE emmc_memcard_power(uint32_t mode); +EMMC_ERROR_CODE emmc_mount(void); +EMMC_ERROR_CODE emmc_set_request_mmc_clock(const uint32_t *freq); +EMMC_ERROR_CODE emmc_send_idle_cmd (uint32_t arg); +EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id); +EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, uint32_t feature_flags); +uint32_t emmc_bit_field (const uint8_t *data, uint32_t top, uint32_t bottom); + + +/* interrupt service */ +uint32_t emmc_interrupt(void); + + +/* send command API */ +EMMC_ERROR_CODE emmc_exec_cmd (uint32_t error_mask, uint32_t *response); +void emmc_make_nontrans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg); +void emmc_make_trans_cmd (HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual, + uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode); +EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg); + +/* ********************************* CODE ********************************** */ + +#endif /* #define EMMC_DEF_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_hal.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_hal.h new file mode 100644 index 0000000..9c87276 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_hal.h @@ -0,0 +1,175 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc HW Layer header + ******************************************************************************/ +/****************************************************************************** + * @file emmc_hal.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +#ifndef EMMC_HAL_H__ +#define EMMC_HAL_H__ +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +/* Memory card response types */ +#define HAL_MEMCARD_COMMAND_INDEX_MASK (0x0003fU) + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* memory access operation */ +typedef enum +{ + HAL_MEMCARD_READ = 0U, /**< read */ + HAL_MEMCARD_WRITE = 1U /**< write */ +} HAL_MEMCARD_OPERATION; + +/* Type of data width on memorycard bus */ +typedef enum +{ + HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U, + HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U, + HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U +} HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */ + +/* mode of data transfer */ +typedef enum +{ + HAL_MEMCARD_DMA = 0U, + HAL_MEMCARD_NOT_DMA = 1U +} HAL_MEMCARD_DATA_TRANSFER_MODE; + + +/* Memory card response types. */ +typedef enum hal_memcard_response_type +{ + HAL_MEMCARD_RESPONSE_NONE = 0x00000U, + HAL_MEMCARD_RESPONSE_R1 = 0x00100U, + HAL_MEMCARD_RESPONSE_R1b = 0x00200U, + HAL_MEMCARD_RESPONSE_R2 = 0x00300U, + HAL_MEMCARD_RESPONSE_R3 = 0x00400U, + HAL_MEMCARD_RESPONSE_R4 = 0x00500U, + HAL_MEMCARD_RESPONSE_R5 = 0x00600U, + HAL_MEMCARD_RESPONSE_R6 = 0x00700U, + HAL_MEMCARD_RESPONSE_R7 = 0x00800U, + HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U +} HAL_MEMCARD_RESPONSE_TYPE; + + +/* Memory card command types. */ +typedef enum hal_memcard_command_type +{ + HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U, + HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U, + HAL_MEMCARD_COMMAND_TYPE_AC = 0x02000U, + HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE = 0x03000U, + HAL_MEMCARD_COMMAND_TYPE_ADTC_READ = 0x04000U, + HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U +} HAL_MEMCARD_COMMAND_TYPE; + +/* Type of memory card */ +typedef enum hal_memcard_command_card_type +{ + HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_SD = 0x10000U, + HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U +} HAL_MEMCARD_COMMAND_CARD_TYPE; + +/* Memory card application command. */ +typedef enum hal_memcard_command_app_norm +{ +HAL_MEMCARD_COMMAND_NORMAL = 0x00000U, +HAL_MEMCARD_COMMAND_APP = 0x20000U, +HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U +} HAL_MEMCARD_COMMAND_APP_NORM; + + +/* Memory card command codes. */ +typedef enum +{ +/* class 0 and class 1 */ + CMD0_GO_IDLE_STATE = 0 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD0 */ + CMD1_SEND_OP_COND = 1 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD1 */ + CMD2_ALL_SEND_CID_MMC = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD2 */ + CMD2_ALL_SEND_CID_SD = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD3_SET_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD3 */ + CMD3_SEND_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R6 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD4_SET_DSR = 4 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD4 */ + CMD5_SLEEP_AWAKE = 5 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD5 */ + CMD6_SWITCH = 6 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD6 */ + CMD6_SWITCH_FUNC = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + ACMD6_SET_BUS_WIDTH = 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + CMD7_SELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7 */ + CMD7_SELECT_CARD_PROG = 7 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7(from Disconnected State to Programming State) */ + CMD7_DESELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, + CMD8_SEND_EXT_CSD = 8 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD8 */ + CMD8_SEND_IF_COND = 8 | HAL_MEMCARD_RESPONSE_R7 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, + CMD9_SEND_CSD = 9 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD9 */ + CMD10_SEND_CID = 10 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD10 */ + CMD11_READ_DAT_UNTIL_STOP = 11 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD11 */ + CMD12_STOP_TRANSMISSION = 12 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 */ + CMD12_STOP_TRANSMISSION_WRITE = 12 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 R1b : write case */ + CMD13_SEND_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD13 */ + ACMD13_SD_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + CMD14_BUSTEST_R = 14 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD14 */ + CMD15_GO_INACTIVE_STATE = 15 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD15 */ + +/* class 2 */ + CMD16_SET_BLOCKLEN = 16 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD16 */ + CMD17_READ_SINGLE_BLOCK = 17 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD17 */ + CMD18_READ_MULTIPLE_BLOCK = 18 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD18 */ + CMD19_BUS_TEST_W = 19 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD19 */ +/* class 3 */ + CMD20_WRITE_DAT_UNTIL_STOP = 20 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD20 */ + CMD21 = 21, /* CMD21 */ + CMD22 = 22, /* CMD22 */ + ACMD22_SEND_NUM_WR_BLOCKS = 22 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP, + +/* class 4 */ + CMD23_SET_BLOCK_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL /* CMD23 */ + +} HAL_MEMCARD_COMMAND; + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* EMMC_HAL_H__ */ + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_multiboot.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_multiboot.h new file mode 100644 index 0000000..336b40a --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_multiboot.h @@ -0,0 +1,62 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc multi boot header + ******************************************************************************/ +/****************************************************************************** + * @file emmc_multiboot.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +#ifndef EMMC_MULTIBOOT_H_ +#define EMMC_MULTIBOOT_H_ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ +/* EMMC */ +#define EMMC_DEV_OK (0x525F4F4BU) /* "R_OK" */ +#define EMMC_DEV_ERR (0xFFFFFFFFU) +#define EMMC_DEV_ERR_HW (0x00000004U) +#define EMMC_DEV_ERR_FAULT_INJECTION (0x00000005U) + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + + +/* ************************** FUNCTION PROTOTYPES ************************** */ +uint32_t emmc_trans_data(uint32_t next_bootPartition, uintptr_t sourceSct, uintptr_t targetAd, uint32_t sectorSize); +/* ******************************** END ************************************ */ +#endif /* #ifndef EMMC_MULTIBOOT_H_*/ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_registers.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_registers.h new file mode 100644 index 0000000..3b1fd16 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_registers.h @@ -0,0 +1,174 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc register header + ******************************************************************************/ +/****************************************************************************** + * @file emmc_register.h + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 24.10.2022 0.02 SDIF_MODE register to support HS200/400 + * : 31.10.2022 0.03 License notation change. + * : 07.06.2024 0.04 Modify the transfer end bit of DMAC channel. + *****************************************************************************/ + +#ifndef EMMC_REGISTERS_H__ +#define EMMC_REGISTERS_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ +/* MMC0 channel */ +#define MMC0_SD_BASE (BASE_MMC0_ADDR) /* reg addr is 0xEE140000U */ + +#define SD_CMD (MMC0_SD_BASE + 0x0000U) +#define SD_ARG (MMC0_SD_BASE + 0x0010U) +#define SD_STOP (MMC0_SD_BASE + 0x0020U) +#define SD_SECCNT (MMC0_SD_BASE + 0x0028U) +#define SD_RSP10 (MMC0_SD_BASE + 0x0030U) +#define SD_RSP32 (MMC0_SD_BASE + 0x0040U) +#define SD_RSP54 (MMC0_SD_BASE + 0x0050U) +#define SD_RSP76 (MMC0_SD_BASE + 0x0060U) +#define SD_INFO1 (MMC0_SD_BASE + 0x0070U) +#define SD_INFO2 (MMC0_SD_BASE + 0x0078U) +#define SD_INFO1_MASK (MMC0_SD_BASE + 0x0080U) +#define SD_INFO2_MASK (MMC0_SD_BASE + 0x0088U) +#define SD_CLK_CTRL (MMC0_SD_BASE + 0x0090U) +#define SD_SIZE (MMC0_SD_BASE + 0x0098U) +#define SD_OPTION (MMC0_SD_BASE + 0x00A0U) +#define SD_ERR_STS1 (MMC0_SD_BASE + 0x00B0U) +#define SD_ERR_STS2 (MMC0_SD_BASE + 0x00B8U) +#define SD_BUF0 (MMC0_SD_BASE + 0x00C0U) +#define CC_EXT_MODE (MMC0_SD_BASE + 0x0360U) +#define SOFT_RST (MMC0_SD_BASE + 0x0380U) +#define HOST_MODE (MMC0_SD_BASE + 0x0390U) +#define SDIF_MODE (MMC0_SD_BASE + 0x0398U) +#define DM_CM_DTRAN_MODE (MMC0_SD_BASE + 0x0820U) +#define DM_CM_DTRAN_CTRL (MMC0_SD_BASE + 0x0828U) +#define DM_CM_INFO1 (MMC0_SD_BASE + 0x0840U) +#define DM_CM_INFO1_MASK (MMC0_SD_BASE + 0x0848U) +#define DM_CM_INFO2 (MMC0_SD_BASE + 0x0850U) +#define DM_CM_INFO2_MASK (MMC0_SD_BASE + 0x0858U) +#define DM_DTRAN_ADDR (MMC0_SD_BASE + 0x0880U) +#define SCC_DTCNTL (MMC0_SD_BASE + 0x1000U) +#define SCC_TAPSET (MMC0_SD_BASE + 0x1008U) +#define SCC_DT2FF (MMC0_SD_BASE + 0x1010U) +#define SCC_CKSEL (MMC0_SD_BASE + 0x1018U) +#define SCC_SMPCMP (MMC0_SD_BASE + 0x1030U) +#define SCC_TMPPORT2 (MMC0_SD_BASE + 0x1038U) + +/* SD_INFO1 Registers */ +#define SD_INFO1_INFO2 (0x00000004U) /* Access end*/ +#define SD_INFO1_INFO0 (0x00000001U) /* Response end*/ + +/* SD_INFO2 Registers */ +#define SD_INFO2_CBSY (0x00004000U) /* Command Type Register Busy*/ +#define SD_INFO2_BWE (0x00000200U) /* SD_BUF Write Enable*/ +#define SD_INFO2_BRE (0x00000100U) /* SD_BUF Read Enable*/ +#define SD_INFO2_DAT0 (0x00000080U) /* SDDAT0*/ +#define SD_INFO2_ALL_ERR (0x0000807FU) +#define SD_INFO2_CLEAR (0x00000800U) /* BIT11 The write value should always be 1. HWM_0003 */ + +/* DM_INFO1 Registers */ +#define DM_CM_INFO_DTRANEND0 (0x00010000U) /* DMAC Channel 0 Transfer End */ +#define DM_CM_INFO_DTRANEND1 (0x00100000U) /* DMAC Channel 1 Transfer End */ + +/* DM_INFO2 Registers */ +#define DM_CM_INFO2_DTRANEND0 (0x00010000U) /* DMAC Channel 0 Error */ +#define DM_CM_INFO2_DTRANEND1 (0x00020000U) /* DMAC Channel 1 Error */ + +/* SOFT_RST */ +#define SOFT_RST_SDRST (0x00000001U) + +/* SD_CLK_CTRL */ +#define SD_CLK_CTRL_CLKDIV_MASK (0x000000FFU) +#define SD_CLK_WRITE_MASK (0x000003FFU) + +/* SD_OPTION */ +#define SD_OPTION_WIDTH (0x00008000U) +#define SD_OPTION_WIDTH8 (0x00002000U) +#define SD_OPTION_TIMEOUT_CNT_MASK (0x000000F0U) + + +/* MMC Clock Frequency +* 200MHz * 1/x = output clock +*/ +#define MMC_400KHZ (512U) /* 200MHz * 1/512 = 390 KHz */ +#define MMC_20MHZ (16U) /* 200MHz * 1/16 = 12.5 MHz Normal speed mode*/ +#define MMC_26MHZ (8U) /* 200MHz * 1/8 = 25 MHz High speed mode 26Mhz*/ +#define MMC_52MHZ (4U) /* 200MHz * 1/4 = 50 MHz High speed mode 52Mhz*/ +#define MMC_200MHZ (1U) /* 200MHz * 1/1 = 200 MHz HS200/HS400 mode 200Mhz*/ + +#define MMC_FREQ_52MHZ (52000000U) +#define MMC_FREQ_26MHZ (26000000U) +#define MMC_FREQ_20MHZ (20000000U) + +/* MMC Clock DIV */ +#define MMC_SD_CLK_START (0x00000100U) /* CLOCK On */ +#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */ + +/* DM_CM_DTRAN_MODE */ +#define DM_CM_DTRAN_MODE_CH0 (0x00000000U) /* CH0 : downstream*/ +#define DM_CM_DTRAN_MODE_CH1 (0x00010000U) /* CH1 : upstream*/ +#define DM_CM_DTRAN_MODE_BIT_WIDTH (0x00000030U) + +/* CC_EXT_MODE */ +#define CC_EXT_MODE_DMASDRW_ENABLE (0x00000002U) /* SD_BUF Read/Write DMA Transfer */ +#define CC_EXT_MODE_CLEAR (0x00001010U) /* BIT 12 & 4 always 1. */ + +/* DM_CM_INFO_MASK */ +#define DM_CM_INFO_MASK_CLEAR (0xFFEEFEFEU) +#define DM_CM_INFO_CH0_ENABLE (0x00010001U) +#define DM_CM_INFO_CH1_ENABLE (0x00100001U) + +/* DM_CM_INFO2_MASK */ +#define DM_CM_INFO2_MASK_CLEAR (0xFFFCFFFEU) +#define DM_CM_INFO2_CH0_ENABLE (0x00010001U) +#define DM_CM_INFO2_CH1_ENABLE (0x00020001U) + +/* DM_DTRAN_ADDR */ +#define DM_DTRAN_ADDR_WRITE_MASK (0xFFFFFFF8U) + +/*DM_CM_DTRAN_CTRL */ +#define DM_CM_DTRAN_CTRL_START (0x00000001U) + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +#endif /* EMMC_REGISTERS_H__ */ +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_std.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_std.h new file mode 100644 index 0000000..25c3f18 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/emmc_std.h @@ -0,0 +1,312 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc std header + ******************************************************************************/ +/****************************************************************************** + * @file emmc_std.h + * - Version : 0.03 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 24.10.2022 0.02 Add supports for HS200/400 + * : 31.10.2022 0.03 License notation change. + *****************************************************************************/ + +#ifndef EMMC_STD_H__ +#define EMMC_STD_H__ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_hal.h" +#include "emmc_registers.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/*CSD register Macros */ +#define EMMC_CSD_SPEC_VARS() (emmc_bit_field(mmc_drv_obj.csd_data, 125,122)) +#define EMMC_CSD_TRAN_SPEED() (emmc_bit_field(mmc_drv_obj.csd_data, 103,96)) + +/* for sector access */ +#define EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */ +#define EMMC_SECTOR_PADD_MASK ((1U << EMMC_SECTOR_SIZE_SHIFT) - 1U) +#define EMMC_SECTOR_SIZE (512U) +#define EMMC_BLOCK_LENGTH (512U) +#define EMMC_BLOCK_LENGTH_DW (128U) + +/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */ +typedef enum +{ + EMMC_ERR = 0U, /**< unknown error */ + EMMC_SUCCESS , /**< OK */ + EMMC_ERR_FROM_DMAC , /**< DMAC allocation error */ + EMMC_ERR_FROM_DMAC_TRANSFER , /**< DMAC transfer error */ + EMMC_ERR_CARD_STATUS_BIT , /**< card status error. Non-masked error bit was set in the card status */ + EMMC_ERR_CMD_TIMEOUT , /**< command timeout error */ + EMMC_ERR_DATA_TIMEOUT , /**< data timeout error */ + EMMC_ERR_CMD_CRC , /**< command CRC error */ + EMMC_ERR_DATA_CRC , /**< data CRC error */ + EMMC_ERR_PARAM , /**< parameter error */ + EMMC_ERR_RESPONSE , /**< response error */ + EMMC_ERR_RESPONSE_BUSY , /**< response busy error */ + EMMC_ERR_TRANSFER , /**< data transfer error */ + EMMC_ERR_READ_SECTOR , /**< read sector error */ + EMMC_ERR_WRITE_SECTOR , /**< write sector error */ + EMMC_ERR_STATE , /**< state error */ + EMMC_ERR_TIMEOUT , /**< timeout error */ + EMMC_ERR_ILLEGAL_CARD , /**< illegal card */ + EMMC_ERR_CARD_BUSY , /**< Busy state */ + EMMC_ERR_CARD_STATE , /**< card state error */ + EMMC_ERR_SET_TRACE , /**< trace information error */ + EMMC_ERR_FROM_TIMER , /**< Timer error */ + EMMC_ERR_FORCE_TERMINATE , /**< Force terminate */ + EMMC_ERR_CARD_POWER , /**< card power fail */ + EMMC_ERR_ERASE_SECTOR , /**< erase sector error */ + EMMC_ERR_INFO2 , /**< exec cmd error info2 */ + RCAR_ERR /**< Error judged by R-Car register */ + +} EMMC_ERROR_CODE; + +/* Error code judged by R-car register or eMMC return*/ +#define EMMC_TUNING_FAIL (0U) /* Fail judged by eMMC return*/ +#define TUNING_SUCCESS (1U) /* Tuning success */ +#define RCAR_TUNING_FAIL (2U) /* Fail judged by R-car register*/ + +/* Response */ +/** R1 */ +#define EMMC_R1_ERROR_MASK (0xFDBFE080U) /* Type 'E' bit and bit14(must be 0). ignore bit22 */ +#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) /* Ignore bit23 (Not check CRC error) */ +#define EMMC_R1_STATE_MASK (0x00001E00U) /* [12:9] */ +#define EMMC_R1_READY (0x00000100U) /* bit8 */ +#define EMMC_R1_STATE_SHIFT (9U) + +/** R4 */ +#define EMMC_R4_STATUS (0x00008000U) + +/** CSD */ +#define EMMC_TRANSPEED_FREQ_UNIT_MASK (0x07U) /* bit[2:0] */ +#define EMMC_TRANSPEED_MULT_MASK (0x78U) /* bit[6:3] */ +#define EMMC_TRANSPEED_MULT_SHIFT (3U) + +/** OCR */ +#define EMMC_HOST_OCR_VALUE (0x40FF8080U) +#define EMMC_OCR_STATUS_BIT (0x80000000U) /* Card power up status bit */ +#define EMMC_OCR_ACCESS_MODE_MASK (0x60000000U) /* bit[30:29] */ +#define EMMC_OCR_ACCESS_MODE_SECT (0x40000000U) + +/** EXT_CSD */ +#define EMMC_EXT_CSD_CARD_TYPE (196U) +#define EMMC_EXT_CSD_PARTITION_CONFIG (179U) +#define EMMC_EXT_CSD_PWR_CL_DDR_200_360 (253U) /* Power class for 200MHz, DDR at VCC= 3.6V */ +#define EMMC_EXT_CSD_PWR_CL_200_195 (237U) /* Power class for 200MHz, at VCCQ =1.95V, VCC = 3.6V */ +#define EMMC_EXT_CSD_PWR_CL_26_195 (201U) /* Power class for 26MHz at 1.95V 1 R */ +#define EMMC_EXT_CSD_PWR_CL_52_195 (200U) /* Power class for 52MHz at 1.95V 1 R */ + +#define EMMC_EXT_CSD_CARD_TYPE_26MHZ (0x01U) +#define EMMC_EXT_CSD_CARD_TYPE_52MHZ (0x02U) +#define EMMC_EXT_CSD_CARD_TYPE_200MHZ (0x10U) +#define EMMC_EXT_CSD_CARD_TYPE_400MHZ (0x40U) + +/** SWITCH (CMD6) argument */ +#define EXTCSD_ACCESS_BYTE (0x03000000U) /* H'03000000 */ + +#define BUS_WIDTH_ADD (183U<<16U) /* H'00b70000 */ +#define HS_TIMING_ADD (185U<<16U) /* H'00b90000 */ +#define POW_CLASS_ADD (187U<<16U) /* H'00bb0000 */ + +#define BUS_WIDTH_1 (0U<<8U) /* H'00000000 */ +#define BUS_WIDTH_8 (2U<<8U) /* H'00000200 */ +#define BUS_WIDTH_8_DDR (6U<<8U) /* H'00000400 */ + +#define HS_TIMING_1 (1U<<8U) /* H'00000100 */ +#define HS_TIMING_HS200 (2U<<8U) /* H'00000200 */ +#define HS_TIMING_HS400 (3U<<8U) /* H'00000300 */ + +#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1) /**< H'03b90100 */ +#define EMMC_SWITCH_HS200 (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_HS200) /**< H'03b90200 */ +#define EMMC_SWITCH_HS400 (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_HS400) /**< H'03b90300 */ + +#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1) /**< H'03b70000 */ +#define EMMC_SWITCH_BUS_WIDTH_8_DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8_DDR) /**< H'03b70600 */ + + +#define EMMC_SWITCH_PARTITION_CONFIG (0x03B30000UL) /**< Partition config = 0x00 */ + +/** for st_mmc_base */ +#define EMMC_MAX_RESPONSE_LENGTH (17U) +#define EMMC_MAX_CID_LENGTH (16U) +#define EMMC_MAX_CSD_LENGTH (16U) +#define EMMC_MAX_EXT_CSD_LENGTH (512U) + +/* speed mode */ +#define TIMING_HIGH_SPEED_OFF (0U) +#define TIMING_HIGH_SPEED (1U) +#define TIMING_HS200 (2U) +#define TIMING_HS400 (3U) + +/* MMC Clock Frequency */ +/* 200MHz * 1/x = output clock */ +#define HS400_50MHZ (8U) /* 400MHz * 1/8 = 50MHz */ +#define HS400_200MHZ (2U) /* 400MHz * 1/2 = 200MHz */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* Partition id */ +typedef enum +{ + PARTITION_ID_USER = 0x0, /**< User Area */ + PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */ + PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */ + PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */ + PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */ + PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */ + PARTITION_ID_GP_3 = 0x6, /**< General Purpose partition 3 */ + PARTITION_ID_GP_4 = 0x7, /**< General Purpose partition 4 */ + PARTITION_ID_MASK = 0x7 /**< [2:0] */ +} EMMC_PARTITION_ID; + +/* card state in R1 response [12:9] */ +typedef enum +{ + EMMC_R1_STATE_IDLE = 0, + EMMC_R1_STATE_READY, + EMMC_R1_STATE_IDENT, + EMMC_R1_STATE_STBY, + EMMC_R1_STATE_TRAN, + EMMC_R1_STATE_DATA, + EMMC_R1_STATE_RCV, + EMMC_R1_STATE_PRG, + EMMC_R1_STATE_DIS, + EMMC_R1_STATE_BTST, + EMMC_R1_STATE_SLEP +} EMMC_R1_STATE; + +typedef enum{ + ESTATE_BEGIN = 0, + ESTATE_ISSUE_CMD, + ESTATE_NON_RESP_CMD, + ESTATE_RCV_RESP, + ESTATE_RCV_RESPONSE_BUSY, + ESTATE_CHECK_RESPONSE_COMPLETE, + ESTATE_DATA_TRANSFER, + ESTATE_DATA_TRANSFER_COMPLETE, + ESTATE_ACCESS_END, + ESTATE_TRANSFER_ERROR, + ESTATE_ERROR, + ESTATE_END +}EMMC_INT_STATE; + +/* eMMC boot driver error information */ +typedef struct +{ + volatile uint32_t info1; /**< SD_INFO1 register value. (hardware dependence) */ + volatile uint32_t info2; /**< SD_INFO2 register value. (hardware dependence) */ + volatile uint32_t status1; /**< SD_ERR_STS1 register value. (hardware dependence) */ + volatile uint32_t status2; /**< SD_ERR_STS2 register value. (hardware dependence) */ + volatile uint32_t dm_info1; /**< DM_CM_INFO1 register value. (hardware dependence) */ + volatile uint32_t dm_info2; /**< DM_CM_INFO2 register value. (hardware dependence) */ +} st_error_info; + + +/* Command information */ +typedef struct +{ + HAL_MEMCARD_COMMAND cmd; /**< Command information */ + uint32_t arg; /**< argument */ + HAL_MEMCARD_OPERATION dir; /**< direction */ + uint32_t hw; /**< H/W dependence. SD_CMD register value. */ +} st_command_info; + + +/* MMC driver base */ +typedef struct +{ + st_error_info error_info; /**< error information */ + st_command_info cmd_info; /**< command information */ + + /* for data transfer */ + uint32_t *buff_address_virtual; /**< Dest or Src buff */ + uint32_t *buff_address_physical; /**< Dest or Src buff */ + HAL_MEMCARD_DATA_WIDTH bus_width; /**< bus width */ + uint32_t trans_size; /**< transfer size for this command */ + uint32_t remain_size; /**< remain size for this command */ + uint32_t response_length; /**< response length for this command */ + + /* clock */ + uint32_t max_freq; /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */ + uint32_t current_freq; /**< current MMC clock[Hz] (the closest frequency supported by HW) */ + uint32_t set_freq; /**< Frequency to be set. */ + + /* state flag */ + uint32_t card_power_enable; /**< True : Power ON */ + uint32_t clock_enable; /**< True : Clock ON */ + uint32_t initialize; /**< True : initialize complete. */ + uint32_t mount; /**< True : mount complete. */ + uint32_t selected; /**< True : selected card. */ + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode; /**< 0: DMA, 1:PIO */ + EMMC_R1_STATE current_state; /**< card state */ + volatile uint32_t during_transfer; /**< True : during transfer */ + volatile uint32_t during_dma_transfer; /**< True : during transfer (DMA)*/ + volatile uint32_t dma_error_flag; /**< True : occurred DMAC error */ + volatile uint32_t force_terminate; /**< force terminate flag */ + volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */ + + /* timeout */ + uint32_t data_timeout; /**< read and write data timeout.*/ + + /* interrupt */ + volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */ + volatile uint32_t int_event2; /**< interrupt SD_INFO2 Event */ + volatile uint32_t dm_event1; /**< interrupt DM_CM_INFO1 Event */ + volatile uint32_t dm_event2; /**< interrupt DM_CM_INFO2 Event */ + + /* response */ + uint32_t *response; /**< pointer to buffer for executing command. */ + uint32_t r1_card_status; /**< R1 response data */ + uint32_t r3_ocr; /**< R3 response data */ + uint32_t r4_resp; /**< R4 response data */ + uint32_t r5_resp; /**< R5 response data */ + + /* Card registers (4byte align) */ + uint8_t csd_data[EMMC_MAX_CSD_LENGTH]; /**< CSD */ + uint8_t cid_data[EMMC_MAX_CID_LENGTH]; /**< CID */ + uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH]; /**< EXT_CSD */ + uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH]; /**< other response */ + + /* SDHI base address */ + uintptr_t base_address; +} st_mmc_base; + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +/* ******************************** END ************************************ */ +#endif /* EMMC_STD_H__ */ +/* EMMC_STD_H__ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/gic.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/gic.h new file mode 100644 index 0000000..08d6f8a --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/gic.h @@ -0,0 +1,417 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : GIC Control Function + ******************************************************************************/ +/****************************************************************************** + * @file gic.h + * - Version : 0.04 + * @brief Controls GIC-600 registers and interrupts. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.08.2022 0.01 First Release + * : 20.09.2022 0.02 Set ChildrenAsleep of GICR_WAKER to 1 and end processing + * : 31.10.2022 0.03 License notation change. + * : 04.04.2023 0.04 Removed stdio.h. + *****************************************************************************/ + +#ifndef GIC_H +#define GIC_H + +/******************************************************************************* +** Include Section ** +*******************************************************************************/ +#include + +/******************************************************************************* +** Version Information ** +*******************************************************************************/ + +/******************************************************************************* +** Global Symbols ** +*******************************************************************************/ +/* GIC base */ +#define GICD_BASE (0xF1000000UL) +#define GICR_BASE (GICD_BASE + 0x60000U) + +/* Generic Interrupt Controller Distributor (GICD) */ +#define GICD_CTLR *((volatile uint32_t *)(GICD_BASE + 0x000U)) +#define GICD_IGROUPR(n) *((volatile uint32_t *)(GICD_BASE + 0x080U + 4U*(n))) +#define GICD_ISENABLER(n) *((volatile uint32_t *)(GICD_BASE + 0x100U + 4U*(n))) +#define GICD_ICENABLER(n) *((volatile uint32_t *)(GICD_BASE + 0x180U + 4U*(n))) +#define GICD_ISPENDR(n) *((volatile uint32_t *)(GICD_BASE + 0x200U + 4U*(n))) +#define GICD_ICPENDR(n) *((volatile uint32_t *)(GICD_BASE + 0x280U + 4U*(n))) +#define GICD_IPRIORITYR(n) *((volatile uint32_t *)(GICD_BASE + 0x400U + 4U*(n))) +#define GICD_ICFGR(n) *((volatile uint32_t *)(GICD_BASE + 0xC00U + 4U*(n))) +#define GICD_IGRPMODR(n) *((volatile uint32_t *)(GICD_BASE + 0xD00U + 4U*(n))) +#define GICD_IROUTER(n) *((volatile uint64_t *)(GICD_BASE + 0x6000U + 8U*(n))) + +/* Generic Interrupt Controller Redistributor (GICR) */ +#define GICR_CTLR *((volatile uint32_t *)(GICR_BASE + 0x0000U)) +#define GICR_WAKER *((volatile uint32_t *)(GICR_BASE + 0x0014U)) +#define GICR_PWRR *((volatile uint32_t *)(GICR_BASE + 0x0024U)) + +#define CHILDREN_ASLEEP (1U << 2U) +#define PROCESSOR_SLEEP (1U << 1U) +#define RDPOWER_DOWN (1U << 0U) + +/******************************************************************************* +** Global Data Types ** +*******************************************************************************/ + +/******************************************************************************* +** Function Prototypes ** +*******************************************************************************/ + +/******************************************************************************* +** Macro ** +*******************************************************************************/ + +/******************************************************************************* + * Definitions for CPU system register interface to GICv3 + ******************************************************************************/ +/* ICC_SRE_EL3 */ +#define ICC_SRE_EN_BIT (8U) +#define ICC_SRE_DIB_BIT (4U) +#define ICC_SRE_DFB_BIT (2U) +#define ICC_SRE_SRE_BIT (1U) + +/* SCR_EL3 */ +#define SCR_NS_BIT (1U) + +/* Affinity Leve mask value */ +#define AFFINITY0_MASK (0xFFU) +#define AFFINITY1_MASK (0xFF00U) +#define AFFINITY2_MASK (0xFF0000U) +#define AFFINITY3_MASK (0xFF00000000U) +#define IRM_OFF (0x80000000U) + +/* Get ICC_IAR0 */ +static inline uint64_t get_ICC_IAR0(void) +{ + uint64_t value = 0U; + __asm__ volatile("mrs %0, S3_0_c12_c8_0" : "=r" (value)); + return value; +} + +/* Set ICC_PMR */ +static inline void set_ICC_PMR(uint64_t value) +{ + __asm__ volatile ("msr S3_0_C4_C6_0, %0" :: "r" (value)); +} + +/* Set ICC_IGRPEN0 */ +static inline void set_ICC_IGRPEN0(uint64_t value) +{ + __asm__ volatile ("msr S3_0_c12_c12_6, %0" :: "r" (value)); +} + +/* Set ICC_SRE_EL1 */ +static inline void set_ICC_SRE_EL1(uint64_t value) +{ + __asm__ volatile ("msr S3_0_C12_C12_5, %0" :: "r" (value)); +} + +/* Get ICC_SRE_EL3 */ +static inline uint64_t get_ICC_SRE_EL3(void) +{ + uint64_t value = 0U; + __asm__ volatile("mrs %0, S3_6_C12_C12_5" : "=r" (value)); + return value; +} + +/* Set ICC_SRE_EL3 */ +static inline void set_ICC_SRE_EL3(uint64_t value) +{ + __asm__ volatile ("msr S3_6_C12_C12_5, %0" :: "r" (value)); +} + +/* Get MPIDR_EL1 */ +static inline uint64_t get_MPIDR_EL1(void) +{ + uint64_t value = 0U; + __asm__ volatile("mrs %0, mpidr_el1" : "=r" (value)); + return value; +} + +/* ISB */ +static inline void GIC_isb(void) +{ + __asm__ volatile ("isb"); +} + +/* Enable the interrupt distributor using the GIC's CTLR register */ +static inline void GIC_EnableDistributor(void) +{ + GICD_CTLR |= 0x31U; +} + +/* Disable the interrupt distributor using the GIC's CTLR register */ +static inline void GIC_DisableDistributor(void) +{ + GICD_CTLR &= 0xFFFFFFFEU; +} + +/* Set the interrupt enable from the GIC's ISENABLER register */ +static inline void GIC_SetEnable(uint32_t intid, uint32_t value) +{ + uint32_t reg = GICD_ISENABLER(intid / 32U); + uint32_t shift = (intid % 32U); + + reg &= (~(1U << shift)); + reg |= ( (value & 1U) << shift); + + GICD_ISENABLER(intid / 32U) = reg; +} + +/* Set the interrupt disable from the GIC's ICENABLER register */ +static inline void GIC_SetClearEnable(uint32_t intid, uint32_t value) +{ + uint32_t reg = GICD_ICENABLER(intid / 32U); + uint32_t shift = (intid % 32U); + + reg &= (~(1U << shift)); + reg |= ( (value & 1U) << shift); + + GICD_ICENABLER(intid / 32U) = reg; +} + +/* Sets the interrupt configuration using GIC's ICFGR register */ +static inline void GIC_SetConfiguration(uint32_t intid, uint32_t int_config) +{ + uint32_t icfgr = GICD_ICFGR(intid / 16U); + uint32_t shift = (intid % 16U) << 1U; + + icfgr &= (~(3U << shift)); + icfgr |= ( int_config << shift); + + GICD_ICFGR(intid / 16U) = icfgr; +} + +/* Set the priority for the given interrupt in the GIC's IPRIORITYR register */ +static inline void GIC_SetPriority(uint32_t intid, uint32_t priority) +{ + uint32_t mask = GICD_IPRIORITYR(intid / 4U); + uint32_t shift = ((intid % 4U) * 8U); + + mask &= (~(0xFFU << shift)); + mask |= ( (priority & 0xFFU) << shift); + + GICD_IPRIORITYR(intid / 4U) = mask; +} + +/* Set the interrupt group from the GIC's IGROUPR register */ +static inline void GIC_SetGroup(uint32_t intid, uint32_t group) +{ + uint32_t igroupr = GICD_IGROUPR(intid / 32U); + uint32_t shift = (intid % 32U); + + igroupr &= (~(1U << shift)); + igroupr |= ( (group & 1U) << shift); + + GICD_IGROUPR(intid / 32U) = igroupr; +} + +/* Set the interrupt group from the GIC's IGRPMODR register */ +static inline void GIC_SetGrpMode(uint32_t intid, uint32_t mode) +{ + uint32_t imode = GICD_IGRPMODR(intid / 32U); + uint32_t shift = (intid % 32U); + + imode &= (~(1U << shift)); + imode |= ( (mode & 1U) << shift); + + GICD_IGRPMODR(intid / 32U) = imode; +} + +/* Set the interrupt routing from the GIC's IROUTER register */ +static inline void GIC_SetRouter(uint32_t intid) +{ + uint64_t affinity = 0U; + + /* Get Affinity level */ + affinity = get_MPIDR_EL1(); + affinity &= (AFFINITY0_MASK | AFFINITY1_MASK | AFFINITY2_MASK | AFFINITY3_MASK); + /* Interrupt routing mode bit OFF */ + affinity &= (~(IRM_OFF)); + + GICD_IROUTER(intid) = affinity; +} + +/* Get power register value from the GIC's GICR_PWRR register */ +static inline uint32_t GIC_Getpwwr(void) +{ + return (GICR_PWRR); +} + +/* Set power register value from the GIC's GICR_PWRR register */ +static inline void GIC_Setpwwr(uint32_t set_value) +{ + GICR_PWRR = set_value; +} + +/* Get power management cotrol register from the GIC's GICR_WAKER register */ +static inline uint32_t GIC_Getwaker(void) +{ + return (GICR_WAKER); +} + +/* Set power management cotrol register from the GIC's GICR_WAKER register */ +static inline void GIC_Setwaker(uint32_t set_value) +{ + GICR_WAKER = set_value; +} + +/* Enables the given interrupt using GIC's ISENABLER register */ +static inline void GIC_EnableFIQ(uint32_t intid) +{ + + /* Disable interrupt forwarding */ + GIC_DisableDistributor(); + + /* Set level-sensitive */ + GIC_SetConfiguration(intid, 0U); + + /* Set priority */ + GIC_SetPriority(intid, 0U); + + /* Set group 0 (secure) */ + GIC_SetGroup(intid, 0U); + + /* Set group 0 (secure) */ + GIC_SetGrpMode(intid, 0U); + + /* Enable distributor */ + GIC_EnableDistributor(); + + /* Enable the SPI interrupt */ + GIC_SetEnable(intid, 1U); + + /* Set the interrupt routing */ + GIC_SetRouter(intid); +} + +/* Enable the interrupt redistributor wakeup */ +static inline void GIC_WakeupRedistributor(void) +{ + uint32_t get_value = 0U; + uint32_t set_value = 0U; + + get_value = GIC_Getpwwr(); + set_value = get_value & ~(RDPOWER_DOWN); + GIC_Setpwwr(set_value); + + get_value = GIC_Getwaker(); + set_value = get_value & ~(PROCESSOR_SLEEP); + GIC_Setwaker(set_value); + + do + { + get_value = GIC_Getwaker(); + }while((get_value & CHILDREN_ASLEEP) == CHILDREN_ASLEEP); +} + +/* Enable the CPU's interrupt interface */ +static inline void GIC_EnableInterface(void) +{ + uint64_t reg = 0U; + uint64_t icc_sre_el3 = 0U; + + /* Disable the legacy interrupt bypass */ + icc_sre_el3 = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT | ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT; + + reg = get_ICC_SRE_EL3(); + set_ICC_SRE_EL3(reg | icc_sre_el3); + + set_ICC_SRE_EL1(ICC_SRE_SRE_BIT); + GIC_isb(); + + set_ICC_IGRPEN0(1U); /* enable interface grp0 */ + GIC_isb(); +} + +/* Disable the CPU's interrupt interface */ +static inline void GIC_DisableInterface(uint32_t intid) +{ + uint32_t get_value = 0U; + uint32_t set_value = 0U; + + /* Clear Enable the SPI interrupt */ + GIC_SetClearEnable(intid, 1U); + + /* Set ChildrenAsleep of GICR_WAKER to 1 and end processing */ + get_value = GIC_Getwaker(); + set_value = get_value | PROCESSOR_SLEEP; + GIC_Setwaker(set_value); + + do + { + get_value = GIC_Getwaker(); + }while((get_value & CHILDREN_ASLEEP) != CHILDREN_ASLEEP); + +} + +/* Read the CPU's IAR register */ +static inline uint32_t GIC_AcknowledgePending(void) +{ + return (uint32_t)(get_ICC_IAR0()); +} + +/* Set the interrupt priority mask using CPU's PMR register */ +static inline void GIC_SetInterfacePriorityMask(uint64_t priority) +{ + /* Specify F8. 32 priority levels are bit0-2 invalid */ + set_ICC_PMR(priority << 3U); +} + +/* Initialize and enable the GIC */ +static inline void GIC_Enable(void) +{ + GIC_WakeupRedistributor(); + /* Enable interface */ + GIC_EnableInterface(); + /* Set priority mask */ + GIC_SetInterfacePriorityMask(0xFFUL); +} + +/******************************************************************************* +** Function ** +*******************************************************************************/ +/* Interrupt configuration */ +#define Interrupt_Config(void) GIC_Enable(void) + +/* Enable */ +#define Interrupt_Enable(intid) GIC_EnableFIQ((uint32_t)intid) + +/* Disable */ +#define Interrupt_Disable(intid) GIC_DisableInterface((uint32_t)intid) + +#endif /* GIC_H */ +/******************************************************************************* +** End of File ** +*******************************************************************************/ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/hscif_register.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/hscif_register.h new file mode 100644 index 0000000..1eb9ae9 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/hscif_register.h @@ -0,0 +1,61 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : HSCIF register header + ******************************************************************************/ +/****************************************************************************** + * @file hscif_register.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +#ifndef HSCIF_REGISTER_H_ +#define HSCIF_REGISTER_H_ + +#include + +/* HSCIF0 base address */ +/* 0xE6540000U */ +#define HSCIF0_BASE (BASE_HSCIF_ADDR) + +#define HSCIF_HSSMR (HSCIF0_BASE + 0x0000U) /* 16 Serial mode register */ +#define HSCIF_HSBRR (HSCIF0_BASE + 0x0004U) /* 8 Bit rate register */ +#define HSCIF_HSSCR (HSCIF0_BASE + 0x0008U) /* 16 Serial control register */ +#define HSCIF_HSFTDR (HSCIF0_BASE + 0x000CU) /* 8 Transmit FIFO data register */ +#define HSCIF_HSFSR (HSCIF0_BASE + 0x0010U) /* 16 Serial status register */ +#define HSCIF_HSFCR (HSCIF0_BASE + 0x0018U) /* 16 FIFO control register */ +#define HSCIF_HSLSR (HSCIF0_BASE + 0x0024U) /* 16 Line status register */ +#define HSCIF_DL (HSCIF0_BASE + 0x0030U) /* 16 Frequency division register */ +#define HSCIF_CKS (HSCIF0_BASE + 0x0034U) /* 16 Clock Select register */ +#define HSCIF_HSSRR (HSCIF0_BASE + 0x0040U) /* 16 Sampling rate register */ + +#endif /* HSCIF_REGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/image_load.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/image_load.h new file mode 100644 index 0000000..70b9144 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/image_load.h @@ -0,0 +1,243 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file image_load.h + * - Version : 0.09 + * @brief Access protection setting driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 10.02.2022 0.02 Change the number of CA programs + * : 17.02.2022 0.03 Support AArch32 + * : 18.05.2022 0.04 Integrated LOAD_INFO + * Defined value integration + * Remove unused define values + * Changed to processing for each device + * Change structure member name + * Remove LOGICAL_CONTENT_CERT_ADDR + * Add get_logic_cont_cert_addr + * Change the argument type of get_src_addr_offset_in_cert + * Added argument check + * Remove unnecessary macros + * Add argument of load_init() + * Change for memory map update + * : 16.06.2022 0.05 Change log output + * Support secure boot for S4 + * : 31.10.2022 0.06 License notation change. + * : 21.08.2023 0.07 Add support for V4M. + * : 19.12.2024 0.08 Add definitions for RTOS#1 and RTOS#2. + * : 26.05.2025 0.09 Change address and size of CA program2. + *****************************************************************************/ + +#ifndef LOAD_IMAGE_H_ +#define LOAD_IMAGE_H_ + +#include "log.h" + +/* define */ +/* For Build Option RTOS_LOAD_NUM */ +#define RTOS_LOAD_NUM_1 (1U) /* RTOS is RTOS#0 only. */ +#define RTOS_LOAD_NUM_3 (3U) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */ + +/* For Build Option OPTEE_LOAD_ENABLE */ +#define OPTEE_DISABLE (0U) /* Load OP-TEE image disable. */ +#define OPTEE_ENABLE (1U) /* Load OP-TEE image enable. */ + +/* DRAM address */ +#define DRAM_BASE (0x40000000U) +#define DRAM_SIZE (0x80000000U) +#define DRAM_END ((DRAM_BASE + DRAM_SIZE) - 1U) + +/* RT-SRAM */ +/* S4:RT-SRAM V4H/V4M:RT-VRAM0 Mirror */ +#define RTSRAM_BASE (0xEB200000U) +#define RTSRAM_SIZE ((1024U - 16U) * 1024U) /* 1MB - 16KB(stack size) */ +#define RTSRAM_END ((RTSRAM_BASE + RTSRAM_SIZE) - 1U) + +/* RT-VRAM */ +/* S4:RT-VRAM V4H/V4M:RT-VRAM1 */ +#define RTVRAM_BASE (0xE2000000U) +#define RTVRAM_SIZE (1024U * 1024U) /* 1MB */ +#define RTVRAM_VBUF_28M (28U) /* 28MB */ +#define RTVRAM_VBUF_SIZE ((RTVRAM_VBUF_28M - 1U) * 1024U * 1024U) /* 3MB to 27MB (The first 1MB is actual RAM.) */ +#define RTVRAM_VBUF_TOP (RTVRAM_BASE + RTVRAM_SIZE) /* 0xE2100000 */ +#define RTVRAM_VBUF_END ((RTVRAM_VBUF_TOP + RTVRAM_VBUF_SIZE) - 1U) +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RTVRAM_8WAY_28M_SRAM_SIZE (0x00010000U) /* 64KiB */ +#define RTVRAM_SRAM_TOP (RTVRAM_BASE) +#define RTVRAM_SRAM_END (RTVRAM_SRAM_TOP + RTVRAM_8WAY_28M_SRAM_SIZE - 1U) /* 0xE2000000 - 0xE200FFFF */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* System RAM */ +#define SYSRAM_BASE (0xE6300000U) +#if (RCAR_LSI == RCAR_S4) +#define SYSRAM_SIZE (384U * 1024U) /* 384KB */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define SYSRAM_SIZE (1024U * 1024U) /* 1MB */ +#endif /* RCAR_LSI == RCAR_S4 */ +#define SYSRAM_END ((SYSRAM_BASE + SYSRAM_SIZE) - 1U) + +/* Cx Loader */ +#define IPL_TOP (0xE6300000U) +#define IPL_SIZE (0x00030000U) /* 192KiB */ +#define IPL_END ((IPL_TOP +IPL_SIZE) - 1U) + +/* Certificate size */ +#define CONTENT_CERT_OFFSET (0x00006000U) /* certificate top offset */ +#define CONTENT_CERT_INFO_SIZE (0x00001000U) /* Content cert header area size(4KiB) */ +#define CONTENT_CERT_DST_SIZE (0x00000800U) /* content cert dst size */ +#define KEY_CERT_SIZE (0x00002000U) /* Key cert area size(8KiB) */ + +/* Load ID */ +#define RTOS_ID (1U) +#define CA_PROGRAM_ID (2U) +#define CA_OPTIONAL_ID (6U) +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define RTOS1_ID (16U) /* 16:RTOS#1 */ +#define RTOS2_ID (17U) /* 17:RTOS#2 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* Number of Max loading image */ +#define CA_MAX_IMAGE (8U) /* CA Load program MAX image num */ +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1) +#define MAX_PLACED (16U) /* Load program MAX image num */ +#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define MAX_PLACED (18U) /* Load program MAX image num */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_1 */ + +#define TARGET_MEM_DRAM (0U) +#define TARGET_MEM_RTSRAM (1U) +#define TARGET_MEM_RTVRAM (2U) +#define TARGET_MEM_SYSRAM (3U) +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +#define TARGET_MEM_SRAM_IN_RTVRAM (4U) +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* get info from cert address offset */ +#define CERT_INFO_SIZE_OFFSET (0x00000264U) /* Offset Type1 */ +#define CERT_INFO_DST_OFFSET (0x00000154U) /* Offset Type1 */ +#define CERT_INFO_SIZE_OFFSET1 (0x00000364U) /* Offset Type2 */ +#define CERT_INFO_DST_OFFSET1 (0x000001D4U) /* Offset Type2 */ +#define CERT_INFO_SIZE_OFFSET2 (0x00000464U) /* Offset Type2 */ +#define CERT_INFO_DST_OFFSET2 (0x00000254U) /* Offset Type2 */ + +/* Certificate logical address */ +#define CONTENT_CERT_DEST_ADDR (0xEB230000U) + +/* BL31/BL32 check */ +/* check image num */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define CA_IMAGESIZECHK_DEF (2U) +#else +#define CA_IMAGESIZECHK_DEF (3U) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +/* load_id */ +#define CA_PROGRAM1_ID (6U) +#define CA_PROGRAM2_ID (7U) +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) +#define CA_PROGRAM3_ID (8U) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ + +#define CA_PROGRAM1_ADR (0x46400000U) +#define CA_PROGRAM1_SIZE (0x00022000U) +#if (RCAR_LSI == RCAR_S4) +#define CA_PROGRAM2_ADR (0x44100000U) +#define CA_PROGRAM2_SIZE (0x00100000U) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define CA_PROGRAM2_ADR (0x00000000U) +#define CA_PROGRAM2_SIZE (0x00000000U) +#endif /* RCAR_LSI == RCAR_S4 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) +#define CA_PROGRAM3_ADR (0x44100000U) +#define CA_PROGRAM3_SIZE (0x00100000U) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ + +/* key cert address */ +#define TFMV_KEY_CERT_ADDR (CONTENT_CERT_DEST_ADDR + CONTENT_CERT_INFO_SIZE) /* 0xEB231000 */ +#define NTFMV_KEY_CERT_ADDR (TFMV_KEY_CERT_ADDR + KEY_CERT_SIZE) /* 0xEB233000 */ + +/* struct */ +/* load image range */ +typedef struct { + uint32_t load_id; + uint32_t image_adr; + uint32_t image_size; +} IMAGE_RANGE; + +/* load address range */ +typedef struct { + uint32_t cx_topadd; + uint32_t cx_endadd; +} ADDRESS_RANGE; + +/* load info */ +typedef struct{ + const char *name; /* store load image name */ + uint32_t image_size; /* store image size */ + uint32_t boot_addr; /* store boot address of image */ + uint32_t key_cert_addr; /* store key cert address */ + uint32_t cnt_cert_addr; /* store content cert address */ + uint32_t src_addr; /* store source address */ + uint32_t part_num; /* store eMMC partition number */ + uint32_t load_id; /* store Load ID */ + uint32_t cmac[4U]; /* store cmac */ + +} LOAD_INFO; + +static inline uint32_t get_src_addr_offset_in_cert(uint32_t id) +{ + /* INT30-C Pre confirmation */ + if (id > UINT32_MAX / 0x10U) + { + ERROR("get_src_addr_offset_in_cert id error.\n"); + panic; + } + + return (CONTENT_CERT_DEST_ADDR + ((id * 0x10U) + 0x8U)); +} + +static inline uint32_t get_logic_cont_cert_addr(uint32_t num) +{ + /* INT30-C Pre confirmation */ + if (num > UINT32_MAX / 0x10U) + { + ERROR("get_logic_cont_cert_addr num error.\n"); + panic; + } + return (CONTENT_CERT_DEST_ADDR + CONTENT_CERT_OFFSET + (num * CONTENT_CERT_DST_SIZE)); +} + +/* Prototype */ +void load_image(LOAD_INFO* li); +void load_init(LOAD_INFO* li, uint32_t num); +void load_start(LOAD_INFO* li); +#endif /* LOAD_IMAGE_H_ */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/image_load_emmc.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/image_load_emmc.h new file mode 100644 index 0000000..45aae02 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/image_load_emmc.h @@ -0,0 +1,113 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Image load function for eMMC header + ******************************************************************************/ +/****************************************************************************** + * @file image_load_emmc.h + * - Version : 0.05 + * @brief Access protection setting driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 17.02.2022 0.02 Support AArch32 + * : 10.05.2022 0.03 Defined value integration + * Change the argument type of get_part_num_in_cert + * Added argument check + * Changed define name + * Change log output + * Change the direct value reference + * Remove Prototype + * : 08.07.2022 0.04 Change log output + * Adds the defined used in the emmc_trans_data argument + * : 31.10.2022 0.05 License notation change. + *****************************************************************************/ + +#ifndef LOAD_IMAGE_EMMC_H_ +#define LOAD_IMAGE_EMMC_H_ + +#include +#include + +/* define */ +/* eMMC */ +#define CX_EMMC_TOP (0x00000000U) +#define CX_EMMC_BOOT_PART_SIZE (31U * 1024U * 1024U) /* 31MB */ +#define CX_EMMC_END ((CX_EMMC_TOP + CX_EMMC_BOOT_PART_SIZE) - 1U) +#define SRC_TOP (CX_EMMC_TOP) + +/* For eMMC */ +#define CX_EMMC_SECTOR_SIZE_SHIFT (9U) /* 512 = 2^9 */ +#define CX_EMMC_SECTOR_SIZE (512U) +#define CX_EMMC_CONTENT_CERT_ADDR (0x00240000U) +#define CX_EMMC_CONTENT_CERT_SECTOR_NUMBER (CX_EMMC_CONTENT_CERT_ADDR >> CX_EMMC_SECTOR_SIZE_SHIFT) + +/* A side certificate setting */ +/* RT-SRAM Offset */ +#define SEC_BOOT_KEY_CERT_OFFSET (0x00001000U) +#define SEC_DEBUG_SEC_CERT_OFFSET (0x00006000U) + +/* A side RT-SRAM physical address */ +/* RT-SRAM(0xEB200000) + CERT_OFFSET */ +#define SEC_BOOT_KEY_CERT_ADDR (ADDR_RT_SRAM_TOP + SEC_BOOT_KEY_CERT_OFFSET) + +/* A/B side certificate setting */ +/* Boot side Offset */ +#define CERT_OFFSET_2ND (0x8000U) + +/* A/B side RT-SRAM physical address */ +/* RT-SRAM(0xEB200000) + CERT_OFFSET (+ 2nd OFFSET)*/ +#define GET_SEC_BOOT_KEY_CERT_ADDR(a) ((SEC_BOOT_KEY_CERT_ADDR) + ((CERT_OFFSET_2ND) * (a))) + +#define SEC_DEBUG_CERT_SIZE (6396U) + + +static inline void load_image_info_print_for_emmc(LOAD_INFO* li) +{ + + NOTICE("======== %s image load info ========\n", li->name); + NOTICE("load address \t= 0x%x\n" "image size \t= 0x%x\n" + "source address \t= (p:%u)0x%x\n", + (unsigned int)li->boot_addr, (unsigned int)(li->image_size), + (unsigned int)li->part_num, (unsigned int)li->src_addr ); +} + +static inline uint32_t get_part_num_in_cert(uint32_t id) +{ + /* INT30-C Pre confirmation */ + if (UINT32_MAX - id < 1U) + { + ERROR("get_part_num_in_cert id error.\n"); + panic; + } + + return (CONTENT_CERT_DEST_ADDR + ((id + 1U) * 0x10U)); +} + +#endif /* LOAD_IMAGE_EMMC_H_ */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/inline_asm.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/inline_asm.h new file mode 100644 index 0000000..d74e80d --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/inline_asm.h @@ -0,0 +1,55 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : inline asm func header + ******************************************************************************/ + +#ifndef INLINE_ASM_H__ +#define INLINE_ASM_H__ + +#if defined(__RH850G3K__) +static inline void syncm(void) +{ + __asm__ __volatile__ ("SYNCM"); +} + +static inline void synci(void) +{ + __asm__ __volatile__ ("SYNCI"); +} +#else +static inline void syncm(void) +{ + __asm__ volatile ("dsb"); +} + +static inline void synci(void) +{ + __asm__ volatile ("dsb"); + __asm__ volatile ("isb"); +} + +#endif + +#endif /* INLINE_ASM_H__ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/interrupt.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/interrupt.h new file mode 100644 index 0000000..e950bad --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/interrupt.h @@ -0,0 +1,56 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : INTC header + ******************************************************************************/ +/****************************************************************************** + * @file interrupt.h + * - Version : 0.05 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + * : 15.12.2022 0.03 V4H interrupt support. + * : 27.12.2022 0.04 Change argument of pabort_error. + * : 21.08.2023 0.05 Add support for V4M. + *****************************************************************************/ +#ifndef INTERRUPT_H_ +#define INTERRUPT_H_ + +/* Prototype */ +#if (RCAR_LSI == RCAR_S4) +extern void handler_fiq(void); +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +void dabort_error(uint32_t occ_add, uint32_t dfsr, uint32_t dfar); +void pabort_error(uint32_t ifsr, uint32_t ifar); +void Undefined_error(uint32_t occ_add); +#endif /* RCAR_LSI == RCAR_S4 */ +extern void handler_error(uint32_t ex_type); + +#endif /* INTERRUPT_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/ip_control.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/ip_control.h new file mode 100644 index 0000000..99472bb --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/ip_control.h @@ -0,0 +1,51 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : IP's control header + ******************************************************************************/ +/****************************************************************************** + * @file ip_control.h + * - Version : 0.03 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 02.08.2022 0.02 Added define value + * : 31.10.2022 0.03 License notation change. + *****************************************************************************/ + +#ifndef IP_CONTROL_H_ +#define IP_CONTROL_H_ + +#define INTC_SPI_SWDT (548U) + +/* Prototype */ +void ip_init(void); +void ip_release(void); + +#endif /* IP_CONTROL_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/loader_main.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/loader_main.h new file mode 100644 index 0000000..03fb61a --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/loader_main.h @@ -0,0 +1,85 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Loader main header + ******************************************************************************/ +/****************************************************************************** + * @file loader_main.h + * - Version : 0.34 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 18.02.2022 0.02 Updated IPL_VERSION 0.7.0 + * : 22.03.2022 0.03 Updated IPL_VERSION 0.8.0 + * : 20.05.2022 0.04 Updated IPL_VERSION 0.9.0 + * : 12.07.2022 0.05 Updated IPL_VERSION 0.11.0 + * : 22.08.2022 0.06 Updated IPL_VERSION 0.12.0 + * : 03.10.2022 0.07 Updated IPL_VERSION 0.13.0 + * : 27.10.2022 0.08 Updated IPL_VERSION 0.14.0 + * : 31.10.2022 0.09 License notation change. + * : 07.11.2022 0.10 Removed unnecessary define values. + * : 14.12.2022 0.11 Updated IPL_VERSION 0.15.0 + * : 08.02.2023 0.12 Updated IPL_VERSION 0.17.0 + * : 17.02.2023 0.13 Updated IPL_VERSION 0.17.1 + * : 24.04.2023 0.14 Updated IPL_VERSION 0.18.0 + * : 22.05.2023 0.15 Updated IPL_VERSION 0.19.0 + * : 19.06.2023 0.16 Updated IPL_VERSION 0.21.0 + * : 22.08.2023 0.17 Updated IPL_VERSION 1.25.0 + * : 19.09.2023 0.18 Updated IPL_VERSION 1.30.0 + * : 23.10.2023 0.19 Updated IPL_VERSION 1.31.0 + * : 17.11.2023 0.20 Updated IPL_VERSION 1.41.0 + * : 26.01.2024 0.21 Updated IPL_VERSION 1.42.0 + * : 07.02.2024 0.22 Updated IPL_VERSION 1.44.0 + * : 05.04.2024 0.23 Updated IPL_VERSION 1.45.0 + * : 11.06.2024 0.24 Updated IPL_VERSION 1.48.0 + * : 19.08.2024 0.25 Updated IPL_VERSION 1.50.0 + * : 19.09.2024 0.26 Updated IPL_VERSION 1.51.2 + * : 22.10.2024 0.27 Updated IPL_VERSION 1.52.0 + * : 23.10.2024 0.28 Updated IPL_VERSION 1.53.0 + * : 28.10.2024 0.29 Updated IPL_VERSION 1.53.1 + * : 28.10.2024 0.30 Updated IPL_VERSION 1.54.0 + * : 05.12.2024 0.31 Updated IPL_VERSION 1.55.0 + * : 08.01.2025 0.32 Updated IPL_VERSION 1.56.0 + * : 09.04.2025 0.33 Updated IPL_VERSION 1.57.0 + * : 26.05.2025 0.34 Updated IPL_VERSION 1.58.0 + *****************************************************************************/ + +#ifndef LOADER_MAIN_H_ +#define LOADER_MAIN_H_ + +/* define */ +#define IPL_VERSION "1.58.0" + +/* Global */ +extern const char build_message[]; + +/* prototype */ +uint32_t loader_main(void); + +#endif /* LOAD_MAIN_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/loader_main_common.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/loader_main_common.h new file mode 100644 index 0000000..da3d539 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/loader_main_common.h @@ -0,0 +1,43 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main common header + ******************************************************************************/ + +#ifndef LOADER_MAIN_COMMON_H_ +#define LOADER_MAIN_COMMON_H_ + +#include + +/* prototype */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +void smoni_set_param(uint32_t smoni_entry_point, + uint32_t uboot_entry_point); +#else +void smoni_set_param(uint32_t smoni_entry_point, + uint32_t uboot_entry_point, + uint32_t tee_entry_point); +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + +#endif /* LOADER_MAIN_COMMON_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/loader_mmu_table.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/loader_mmu_table.h new file mode 100644 index 0000000..27e3f99 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/loader_mmu_table.h @@ -0,0 +1,80 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + +/******************************************************************************* + * DESCRIPTION : Definitions used by the MMU. + ******************************************************************************/ +/****************************************************************************** + * @file loader_mmu_table.h + * - Version : 0.01 + * @brief MMU define. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 14.12.2022 0.01 First Release +*****************************************************************************/ + +#ifndef MMU_TABLE_H_ +#define MMU_TABLE_H_ + +#include /* for uint32_t */ + +/* b[1:0] Block and Table descriptors */ +#define MMU_TBL_TYPE_TABLE (3UL << 0) +#define MMU_TBL_TYPE_BLOCK (1UL << 0) +#define MMU_TBL_TYPE_PAGE (3UL << 0) + +/* Lower attributes:SH[1:0] unused */ +#define MMU_TBL_BLOCK_OUTER_SHARE (2ULL << 8) +#define MMU_TBL_BLOCK_INNER_SHARE (3ULL << 8) + +/* Lower attributes:AF[10] */ +#define MMU_TBL_BLOCK_AF (1UL << 10) + +/* Lower attributes:AP[2:1] access permissions model */ +#define MMU_TBL_AP_APP_RW (1UL << 6) +#define MMU_TBL_AP_APP_R (3UL << 6) + +/* Lower attributes:AttrIndx[2:0] */ +#define MMU_TBL_ATTRINDX0 (0UL << 2) /* Device-nGnRnE memory */ +#define MMU_TBL_ATTRINDX1 (1UL << 2) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */ +#define MMU_TBL_ATTRINDX2 (2UL << 2) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */ + +/* Upper attributes:Block descriptors */ +#define MMU_TBL_BLOCK_XN (1UL << 54) + +#define MMU_TBL_BLOCK_NOEXEC_DEVICE (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX0 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK) +#define MMU_TBL_BLOCK_EXECREAD_MEMORY ( MMU_TBL_AP_APP_R | MMU_TBL_ATTRINDX1 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK) +#define MMU_TBL_BLOCK_NOEXEC_MEMORY (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX2 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_BLOCK) +/* Level 3 */ +#define MMU_TBL_PAGE_NOEXEC_DEVICE (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX0 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE) +#define MMU_TBL_PAGE_EXECREAD_MEMORY ( MMU_TBL_AP_APP_R | MMU_TBL_ATTRINDX1 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE) +#define MMU_TBL_PAGE_NOEXEC_MEMORY (MMU_TBL_BLOCK_XN | MMU_TBL_AP_APP_RW | MMU_TBL_ATTRINDX2 | MMU_TBL_BLOCK_AF | MMU_TBL_TYPE_PAGE) + +extern const uint64_t g_loader_level1_table[]; +extern const uint64_t g_loader_level2_table[]; +extern const uint64_t g_loader_level3_table[]; + +#endif /* MMU_TABLE_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/log.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/log.h new file mode 100644 index 0000000..56c1bbb --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/log.h @@ -0,0 +1,98 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : log header file + ******************************************************************************/ +/****************************************************************************** + * @file log.h + * - Version : 0.06 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 12.05.2022 0.02 Changed __LOG_H__ to LOG_H_ + * Changed panic (Static analysis) + * : 16.06.2022 0.03 Change log output + * : 31.10.2022 0.04 License notation change. + * : 07.11.2022 0.05 Change log macro. + * : 04.04.2023 0.06 Removed stdio.h. + *****************************************************************************/ +#ifndef LOG_H_ +#define LOG_H_ + +#include + +#define LOG_NONE (0) +#define LOG_ERROR (1) +#define LOG_NOTICE (2) +#define LOG_WARNING (3) +#define LOG_INFO (4) +#define LOG_VERBOSE (5) + + +#if LOG_LEVEL >= LOG_NOTICE +# define NOTICE(...) log_printf("N:" __VA_ARGS__) +#else +# define NOTICE(...) +#endif + +#if LOG_LEVEL >= LOG_ERROR +# define ERROR(...) log_printf("E:" __VA_ARGS__) +#else +# define ERROR(...) +#endif + +#if LOG_LEVEL >= LOG_WARNING +# define WARN(...) log_printf("W:" __VA_ARGS__) +#else +# define WARN(...) +#endif + +#if LOG_LEVEL >= LOG_INFO +# define INFO(...) log_printf("I:" __VA_ARGS__) +#else +# define INFO(...) +#endif + +#if LOG_LEVEL >= LOG_VERBOSE +# define VERBOSE(...) log_printf("V:" __VA_ARGS__) +#else +# define VERBOSE(...) +#endif + + +#define panic \ + do { \ + log_printf("P:%s\n", __func__); \ + while(true){} \ + } while (false) + + +void log_printf(const char *fmt, ...); + +#endif /* LOG_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/mem_io.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/mem_io.h new file mode 100644 index 0000000..922e7d3 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/mem_io.h @@ -0,0 +1,104 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Memory access driver header + ******************************************************************************/ +/****************************************************************************** + * @file mem_io.h + * - Version : 0.05 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 17.02.2022 0.02 Change the return type of mem_read64 + * : 31.10.2022 0.03 License notation change. + * : 07.11.2022 0.04 Added to convert mmio. + * : 21.08.2023 0.05 Add support for V4M. + *****************************************************************************/ +#ifndef MEM_IO_H_ +#define MEM_IO_H_ + +#include + +static inline void mem_write8(uintptr_t addr, uint8_t data) +{ + *(volatile uint8_t*)addr = data; +} + +static inline uint8_t mem_read8(uintptr_t addr) +{ + return (*(volatile uint8_t*)addr); +} + +static inline void mem_write16(uintptr_t addr, uint16_t data) +{ + *(volatile uint16_t*)addr = data; +} + +static inline uint16_t mem_read16(uintptr_t addr) +{ + return (*(volatile uint16_t*)addr); +} + +static inline void mem_write32(uintptr_t addr, uint32_t data) +{ + *(volatile uint32_t*)addr = data; +} + +static inline uint32_t mem_read32(uintptr_t addr) +{ + return (*(volatile uint32_t*)addr); +} + +static inline void mem_write64(uintptr_t addr, uint64_t data) +{ + *(volatile uint64_t*)addr = data; +} + +static inline uint64_t mem_read64(uintptr_t addr) +{ + return (*(volatile uint64_t*)addr); +} + +static inline void mem_bitclrset32(uintptr_t addr, uint32_t clr, uint32_t set) +{ + mem_write32(addr, (mem_read32(addr) & ~clr) | set); +} + +static inline void mem_bitset32(uintptr_t addr, uint32_t set) +{ + mem_write32(addr, (mem_read32(addr) | set) ); +} + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define mmio_write_32(a,b) mem_write32(a,b) +#define mmio_read_32(a) mem_read32(a) +#define mmio_clrsetbits_32(a,b,c) mem_bitclrset32(a,b,c) +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + +#endif /* MEM_IO_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/qos.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/qos.h new file mode 100644 index 0000000..057fcee --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/qos.h @@ -0,0 +1,33 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : QoS driver header + ******************************************************************************/ + +#ifndef QOS_INIT_H_ +#define QOS_INIT_H_ + +extern void qos_init(void); + +#endif /* QOS_INIT_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/ram_protection.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/ram_protection.h new file mode 100644 index 0000000..3568486 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/ram_protection.h @@ -0,0 +1,150 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2024-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RAM protection driver header + ******************************************************************************/ +#ifndef RAM_PROTECTION_H_ +#define RAM_PROTECTION_H_ + +#include +#include + +#define RTVRAM0_AREA1_TOP (0xE0040000U) +#define RTVRAM0_ADDR_END (0xE0100000U) + +#define RTVRAM1_AREA1_TOP (0xE2010000U) +#define RTVRAM1_AREA2_TOP (0xE2100000U) +#define RTVRAM1_ADDR_END (0xE3C00000U) + +#define SYSTEM_RAM_AREA1_TOP (0xE635E000U) +#define SYSTEM_RAM_AREA2_TOP (0xE6360000U) +#define SYSTEM_RAM_ADDR_END (0xE6400000U) + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define DRAM_ADDR_AREA1 (0x0401C00000ULL) +#define DRAM_ADDR_AREA2 (0x0401D00000ULL) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define DRAM_ADDR_AREA3 (0x0406400000ULL) +#define DRAM_ADDR_AREA4 (0x0406440000ULL) +#define DRAM_ADDR_AREA5 (0x0407FC0000ULL) +#define DRAM_ADDR_AREA6 (0x0408000000ULL) +#define DRAM_ADDR_AREA7 (0x041DC00000ULL) +#define DRAM_ADDR_AREA8 (0x0420000000ULL) +#define DRAM_ADDR_AREA9 (0x0440000000ULL) +#define DRAM_ADDR_AREA10 (0x0460000000ULL) +#define DRAM_ADDR_AREA11 (0x0480000000ULL) +#define DRAM_ADDR_AREA12 (0x0500000000ULL) +#define DRAM_ADDR_AREA13 (0x0600000000ULL) +#else +#define DRAM_ADDR_AREA3 (0x0404100000ULL) +#define DRAM_ADDR_AREA4 (0x0406400000ULL) +#define DRAM_ADDR_AREA5 (0x0406440000ULL) +#define DRAM_ADDR_AREA6 (0x0407E00000ULL) +#define DRAM_ADDR_AREA7 (0x0407F00000ULL) +#define DRAM_ADDR_AREA8 (0x0407FC0000ULL) +#define DRAM_ADDR_AREA9 (0x0408000000ULL) +#define DRAM_ADDR_AREA10 (0x041DC00000ULL) +#define DRAM_ADDR_AREA11 (0x0420000000ULL) +#define DRAM_ADDR_AREA12 (0x0440000000ULL) +#define DRAM_ADDR_AREA13 (0x0460000000ULL) +#define DRAM_ADDR_AREA14 (0x0480000000ULL) +#define DRAM_ADDR_AREA15 (0x0500000000ULL) +#define DRAM_ADDR_AREA16 (0x0600000000ULL) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + +#else +#define DRAM_ADDR_AREA1 (0x0401C00000ULL) +#define DRAM_ADDR_AREA2 (0x0406400000ULL) +#define DRAM_ADDR_AREA3 (0x0406440000ULL) +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ +#define DRAM_ADDR_END (0x0700000000ULL) + +#define NOT_USED_VALUE (0x00000000U) + +/* RAM DIVISION AREA ID */ +/* RT-SRAM */ +#define RTVRAM0_ICUMX_IPL_AREA (0U) /* 0xEB200000 -- 0xEB23FFFF */ +#define RTVRAM0_ICUMX_FW_AREA (1U) /* 0xEB240000 -- 0xEB2FFFFF */ +/* RT-VRAM */ +#define RTVRAM1_BLANK_AREA (0U) /* 0xE2000000 -- 0xE200FFFF */ +#define RTVRAM1_EXTEND_CACHE_AREA (1U) /* 0xE2010000 -- 0xE20FFFFF */ +#define RTVRAM1_RTOS_AREA (2U) /* 0xE2100000 -- 0xE3BFFFFF */ +/* System RAM */ +#define SYSTEM_RAM_CX_2ND_IPL (0U) /* 0xE6300000 -- 0xE635DFFF */ +#define SYSTEM_RAM_SHARED_MEM (1U) /* 0xE635E000 -- 0xE635FFFF */ +/* SDRAM */ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define RTVRAM1_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */ +#define CR_FW_SHARED_AREA (1U) /* 0x04_01C00000 -- 0x04_01CFFFFF */ +#define SDRAM_BLANK_AREA (2U) /* OPTEE_DISABLE:0x04_01D00000 -- 0x04_063FFFFF + * OPTEE_ENABLE :0x04_01D00000 -- 0x04_040FFFFF */ +#define SDRAM_PROTECT_AREA (3U) /* OPTEE_DISABLE:0x04_06400000 -- 0x04_0643FFFF + * OPTEE_ENABLE :0x04_04100000 -- 0x04_0643FFFF */ +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define SDRAM_PUBLIC_AREA (4U) /* 0x04_06440000 -- 0x04_07FBFFFF */ +#define ICCOM_USED_AREA (5U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */ +#define LINUX_USED_AREA (6U) /* 0x04_08000000 -- 0x04_1DBFFFFF */ +#define CAAREA2_USED_AREA (7U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */ +#define CR52_USED_AREA (8U) /* 0x04_20000000 -- 0x04_3FFFFFFF */ +#define CAAREA3_USED_AREA (9U) /* 0x04_40000000 -- 0x04_5FFFFFFF */ +#define CAAREA2_USED_AREA2 (10U) /* 0x04_60000000 -- 0x04_7FFFFFFF */ +#define CAAREA1_USED_AREA (11U) /* 0x04_80000000 -- 0x04_FFFFFFFF */ +#else +#define SDRAM_PROTECT_AREA2 (4U) /* 0x04_06400000 -- 0x04_0643FFFF */ +#define SDRAM_BLANK_AREA2 (5U) /* 0x04_06440000 -- 0x04_07DFFFFF */ +#define OPTEE_SHARED_AREA (6U) /* 0x04_07E00000 -- 0x04_07EFFFFF */ +#define SDRAM_BLANK_AREA3 (7U) /* 0x04_07F00000 -- 0x04_07FBFFFF */ +#define ICCOM_USED_AREA (8U) /* 0x04_07FC0000 -- 0x04_07FFFFFF */ +#define LINUX_USED_AREA (9U) /* 0x04_08000000 -- 0x04_1DBFFFFF */ +#define CAAREA2_USED_AREA (10U) /* 0x04_1DC00000 -- 0x04_1FFFFFFF */ +#define CR52_USED_AREA (11U) /* 0x04_20000000 -- 0x04_3FFFFFFF */ +#define CAAREA3_USED_AREA (12U) /* 0x04_40000000 -- 0x04_5FFFFFFF */ +#define CAAREA2_USED_AREA2 (13U) /* 0x04_60000000 -- 0x04_7FFFFFFF */ +#define CAAREA1_USED_AREA (14U) /* 0x04_80000000 -- 0x04_FFFFFFFF */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#if (RCAR_LSI == RCAR_V4H) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define RESERVERD_AREA (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define CAAREA1_USED_AREA2 (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#else +#define RESERVERD_AREA (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define CAAREA1_USED_AREA2 (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#elif (RCAR_LSI == RCAR_V4M) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define CAAREA1_USED_AREA2 (12U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define RESERVERD_AREA (13U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#else +#define CAAREA1_USED_AREA2 (15U) /* 0x05_00000000 -- 0x05_FFFFFFFF */ +#define RESERVERD_AREA (16U) /* 0x06_00000000 -- 0x06_FFFFFFFF */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#endif /* RCAR_LSI == RCAR_V4H */ +#else +#define RTVRAM1_EXTEND_AREA (0U) /* 0x04_00000000 -- 0x04_01BFFFFF */ +#define SDRAM_BLANK_AREA (1U) /* 0x04_01C00000 -- 0x04_063FFFFF */ +#define SDRAM_PROTECT_AREA (2U) /* 0x04_06400000 -- 0x04_0643FFFF */ +#define SDRAM_PUBLIC_AREA (3U) /* 0x04_06440000 -- 0x06_FFFFFFFF */ +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +#endif /* RAM_PROTECTION_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rcar_def.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rcar_def.h new file mode 100644 index 0000000..8ddcbfa --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rcar_def.h @@ -0,0 +1,66 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : R-Car common header + ******************************************************************************/ +/****************************************************************************** + * @file rcar_def.h + * - Version : 0.05 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 17.02.2022 0.02 Support V4H + * : 31.10.2022 0.03 License notation change. + * : 23.05.2023 0.04 Add the define "PRR_PRODUCT_21" for V4H v2.1. + * : 21.08.2023 0.05 Add support for V4M. + *****************************************************************************/ + +#ifndef RCAR_DEF_H_ +#define RCAR_DEF_H_ + +/* Product Register */ +#define PRR (0xFFF00044U) /* PRR register */ +#define PRR_PRODUCT_MASK (0x00007F00U) /* Product mask */ +#define PRR_CUT_MASK (0x000000FFU) /* Cut Number bit mask */ +#define PRR_MAJOR_MASK (0x000000F0U) /* Major bit mask */ +#define PRR_MINOR_MASK (0x0000000FU) /* Minor bit mask */ +#define PRR_MAJOR_SHIFT (4U) /* Major bit shift */ +#define PRR_MAJOR_OFFSET (1U) + +#define PRR_PRODUCT_S4 (0x00005A00U) /* R-Car S4 */ +#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */ +#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */ + +#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */ +#define PRR_PRODUCT_11 (0x00000001U) /* ver 1.1 */ +#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */ +#define PRR_PRODUCT_21 (0x00000011U) /* ver 2.1 */ +#define PRR_PRODUCT_22 (0x00000012U) /* ver 2.2 */ +#endif /* RCAR_DEF_H_ */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rcar_register.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rcar_register.h new file mode 100644 index 0000000..9b5fa33 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rcar_register.h @@ -0,0 +1,157 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : rcar register header + ******************************************************************************/ +/****************************************************************************** + * @file rcar_register.h + * - Version : 0.07 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 17.02.2022 0.02 Add APMU + * Support AArch32 + * : 09.05.2022 0.03 Changed to processing for each device + * : 24.10.2022 0.04 Add supports for HS200/400 + * : 31.10.2022 0.05 License notation change. + * : 07.11.2022 0.06 Added QOS and RTVRAM related registers. + * : 21.08.2023 0.07 Add support for V4M. + *****************************************************************************/ + +#ifndef RCAR_REGISTER_H_ +#define RCAR_REGISTER_H_ + +#include + +#define BASE_ADDR_PFC (0xE6000000U) /* PFC,GPIO,LIFC,CPGA,RESET */ +#define BASE_ADDR_RPC (0xEE200000U) /* RPC */ +#if (RCAR_LSI == RCAR_S4) +#define BASE_ADDR_SCIF (0xE6C00000U) /* SCIF */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define BASE_ADDR_SCIF (0xE6E00000U) /* SCIF */ +#endif /* RCAR_LSI == RCAR_S4 */ +#define BASE_ADDR_MMC (0xEE000000U) /* MMC */ +#define BASE_ADDR_HSCIF (0xE6400000U) /* HSCIF */ +#define BASE_AP_CORE_ADDR (0xE6280000U) /* ECM */ + +/* Base address offset of each register */ +/* CPGA */ +#define OFFSET_CPGA (0x00150000U) +/* RESET */ +#define OFFSET_RESET (0x00160000U) +/* APMU */ +#define OFFSET_APMU (0x00170000U) + +/*RPC*/ +#define OFFSET_RPC (0x00000000U) + +/*SCIF*/ +#if (RCAR_LSI == RCAR_S4) +#define OFFSET_SCIF3 (0x00050000U) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define OFFSET_SCIF0 (0x00060000U) +#endif /* RCAR_LSI == RCAR_S4 */ + +/* SDHI2/MMC0 */ +#define OFFSET_SDHI (0x00140000U) + +/* HSCIF */ +#define OFFSET_HSCIF0 (0x00140000U) + +/* PFC0 */ +#define OFFSET_PFC0 (0x00050000U) + +/* PFC1 */ +#if (RCAR_LSI == RCAR_S4) +#define OFFSET_PFC1 (0x00051000U) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define OFFSET_PFC1 (0x00058000U) +#endif /* RCAR_LSI == RCAR_S4 */ + +/* Port Group */ +#define OFFSET_PORTGR (0x00000800U) + +/* CPGWPR */ +#define OFFSET_CPG_CPGWPR (0x00000000U) + +/* SD0CKCR */ +#define OFFSET_CPG_SD0CKCR (0x00000870U) + +/* PLL2CR0 */ +#define OFFSET_CPG_PLL2CR0 (0x00000834U) + +/* PLLECR */ +#define OFFSET_CPG_PLLECR (0x00000820U) + +/* QOS */ +#define ICU_CC (0xE6600000U) /* CC63S,I2C,AXMM,QoS */ +#define ICU_OFFSET_CCI (0x001a0000U) /* (0xE67A0000U) */ +#define BASE_CCI_ADDR (ICU_CC + ICU_OFFSET_CCI) + +/* RTVRAM */ +#define SDRAM_40BIT_ADDR_TOP (0x0400000000ULL) +#define RTVRAM_VBUF_AREA_SIZE (4U * 1024U * 1024U) /* 4MB */ + +#define BASE_CPG_ADDR (BASE_ADDR_PFC + OFFSET_CPGA) +#define BASE_RESET_ADDR (BASE_ADDR_PFC + OFFSET_RESET) +#define BASE_APMU_ADDR (BASE_ADDR_PFC + OFFSET_APMU) +#define BASE_RPC_ADDR (BASE_ADDR_RPC + OFFSET_RPC) +#if (RCAR_LSI == RCAR_S4) +#define BASE_SCIF_ADDR (BASE_ADDR_SCIF + OFFSET_SCIF3) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define BASE_SCIF_ADDR (BASE_ADDR_SCIF + OFFSET_SCIF0) +#endif /* RCAR_LSI == RCAR_S4 */ +#define BASE_MMC0_ADDR (BASE_ADDR_MMC + OFFSET_SDHI) +#define BASE_HSCIF_ADDR (BASE_ADDR_HSCIF + OFFSET_HSCIF0) +#define BASE_PFC0_ADDR (BASE_ADDR_PFC + OFFSET_PFC0) +#define BASE_PFC1_ADDR (BASE_ADDR_PFC + OFFSET_PFC1) +#define BASE_CPG_ADDR (BASE_ADDR_PFC + OFFSET_CPGA) +#define PFC_GP1_BASE (BASE_PFC0_ADDR + OFFSET_PORTGR) +#define PFC_GP3_BASE (BASE_PFC1_ADDR + OFFSET_PORTGR) +#define CPG_CPGWPR (BASE_CPG_ADDR + OFFSET_CPG_CPGWPR) +#define CPG_PLL2CR0 (BASE_CPG_ADDR + OFFSET_CPG_PLL2CR0) +#define CPG_PLLECR (BASE_CPG_ADDR + OFFSET_CPG_PLLECR) +#define CPG_SD0CKCR (BASE_CPG_ADDR + OFFSET_CPG_SD0CKCR) +#define CPG_FRQCRC0 (BASE_CPG_ADDR + OFFSET_CPG_FRQCRC0 0x0808U) + +#define OFFSET_PFC_DRV0CTRL (0x00000080U) +#define OFFSET_PFC_DRV1CTRL (0x00000084U) +#define OFFSET_PFC_DRV2CTRL (0x00000088U) + +#if (RCAR_LSI == RCAR_S4) +#define PFC_DRVCTRL1_GP1_DM0 (PFC_GP1_BASE + OFFSET_PFC_DRV1CTRL) // R/W 32 POC control register0 PortGroup 3 +#define PFC_DRVCTRL2_GP1_DM0 (PFC_GP1_BASE + OFFSET_PFC_DRV2CTRL) // R/W 32 POC control register1 PortGroup 3 +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define PFC_DRVCTRL0_GP3_DM0 (PFC_GP3_BASE + OFFSET_PFC_DRV0CTRL) // R/W 32 POC control register0 PortGroup 3 +#define PFC_DRVCTRL1_GP3_DM0 (PFC_GP3_BASE + OFFSET_PFC_DRV1CTRL) // R/W 32 POC control register1 PortGroup 3 +#endif /* RCAR_LSI == RCAR_S4 */ + +#define PFC_PMMR(addr) ((addr) & (uintptr_t)0xFFFFF800U) // R/W 32 LSI Multiplexed Pin Setting Mask Register + +#endif /* RCAR_REGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rst_register.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rst_register.h new file mode 100644 index 0000000..52ad7ec --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rst_register.h @@ -0,0 +1,65 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : RST register header + ******************************************************************************/ +/****************************************************************************** + * @file rst_register.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +#ifndef RST_REGISTER_H_ +#define RST_REGISTER_H_ + +#include + +#define RST_BASE (BASE_RESET_ADDR) /* 0xE6160000 */ + +#define RST_MODEMR0 (RST_BASE + 0x0000U) /* Mode pin register0 */ +#define RST_MODEMR1 (RST_BASE + 0x0004U) /* Mode pin register1 */ +#define RST_MODEMR0_MD31 (1U << 31U) +#define RST_MODEMR1_MD32 (1U << 0U) + +#define RST_MODEMR0_BOOT_DEV_MASK (0x0000001EU) +#define RST_MODEMR0_BOOT_DEV_HYPERFLASH160 (0x00000004U) +#define RST_MODEMR0_BOOT_DEV_HYPERFLASH80 (0x00000006U) +#define RST_MODEMR0_BOOT_DEV_QSPI_FLASH40 (0x00000008U) +#define RST_MODEMR0_BOOT_DEV_EMMC_50X8 (0x0000001AU) + +/* SCIF / HSCIF clock speed */ +#define MODEMR_SCIF_DLMODE (0x00000000U) +#define MODEMR_HSCIF_DLMODE_921600 (0x00000001U) +#define MODEMR_HSCIF_DLMODE_1843200 (0x00000002U) +#define MODEMR_HSCIF_DLMODE_3000000 (0x00000003U) + +#endif /* RST_REGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rtvram.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rtvram.h new file mode 100644 index 0000000..ae0c5f3 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rtvram.h @@ -0,0 +1,35 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2021-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-VRAM driver header + ******************************************************************************/ + +#ifndef RTVRAM_H_ +#define RTVRAM_H_ + +#include + +void rtvram_extendmode(void); + +#endif /* RTVRAM_H__ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rtvram_register.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rtvram_register.h new file mode 100644 index 0000000..4b27268 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/rtvram_register.h @@ -0,0 +1,92 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-VRAM register header + ******************************************************************************/ + +#ifndef RTVRAM_REGISTER_H__ +#define RTVRAM_REGISTER_H__ + +#include + +/* RT-VRAM register base address */ +#define RTVRAM_REG_BASE (0xFFEC0000U) + +#define RTVRAM_SECDIVD (RTVRAM_REG_BASE + 0x0000U) +#define RTVRAM_SECCTRRD (RTVRAM_REG_BASE + 0x0040U) +#define RTVRAM_SECCTRWD (RTVRAM_REG_BASE + 0x0340U) +#define RTVRAM_EXT_MODE (RTVRAM_REG_BASE + 0x8500U) +#define RTVRAM_VBUF_CFG (RTVRAM_REG_BASE + 0x6504U) +#define RTVRAM_CACHE_FLUSH (RTVRAM_REG_BASE + 0x4530U) +#define RTVRAM_VBUF_BADDR (RTVRAM_REG_BASE + 0xC580U) + +/* RT-VRAM0 register base address */ +#define RTVRAM0_REG_BASE (0xFFE90000U) +/* RT-VRAM1 register base address */ +#define RTVRAM1_REG_BASE (0xFFEC0000U) + +#define RTVRAM0_SECDIVD (RTVRAM0_REG_BASE + 0x0000U) +#define RTVRAM0_SECCTRRD (RTVRAM0_REG_BASE + 0x0040U) +#define RTVRAM0_SECCTRWD (RTVRAM0_REG_BASE + 0x0340U) + +#define RTVRAM1_SECDIVD (RTVRAM1_REG_BASE + 0x0000U) +#define RTVRAM1_SECCTRRD (RTVRAM1_REG_BASE + 0x0040U) +#define RTVRAM1_SECCTRWD (RTVRAM1_REG_BASE + 0x0340U) + +static inline uint32_t get_rtvram0_secdivd_addr(uint32_t num) +{ + return ((RTVRAM0_SECDIVD + (num * 4U))); +} + +static inline uint32_t get_rtvram0_secctrrd_addr(uint32_t num) +{ + return ((RTVRAM0_SECCTRRD + (num * 4U))); +} + +static inline uint32_t get_rtvram0_secctrwd_addr(uint32_t num) +{ + return ((RTVRAM0_SECCTRWD + (num * 4U))); +} + +static inline uint32_t get_rtvram1_secdivd_addr(uint32_t num) +{ + return ((RTVRAM1_SECDIVD + (num * 4U))); +} + +static inline uint32_t get_rtvram1_secctrrd_addr(uint32_t num) +{ + return ((RTVRAM1_SECCTRRD + (num * 4U))); +} + +static inline uint32_t get_rtvram1_secctrwd_addr(uint32_t num) +{ + return ((RTVRAM1_SECCTRWD + (num * 4U))); +} + +static inline uint32_t get_vbuf_baddr_addr(uint32_t num) +{ + return ((RTVRAM_VBUF_BADDR + (num * 4U))); +} + +#endif /* RTVRAM_REGISTER_H__ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/scif.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/scif.h new file mode 100644 index 0000000..80d8a6e --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/scif.h @@ -0,0 +1,51 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : SCIF driver header + ******************************************************************************/ +/****************************************************************************** + * @file scif.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +#ifndef SCIF_H_ +#define SCIF_H_ + +#include +#include + +/* Prototype */ +void scif_init(void); +void console_putc(uint8_t outchar); + +#endif /* SCIF_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/scif_register.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/scif_register.h new file mode 100644 index 0000000..d26b6c6 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/scif_register.h @@ -0,0 +1,60 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : SCIF register header + ******************************************************************************/ +/****************************************************************************** + * @file scif_register.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + + +#ifndef SCIF_REGISTER_H_ +#define SCIF_REGISTER_H_ + +#include + +/* SCIF3 base address */ +/* 0xE6C50000 */ +#define SCIF_BASE (BASE_SCIF_ADDR) + +#define SCIF_SCSMR (SCIF_BASE + 0x0000U) /* 16 Serial mode register */ +#define SCIF_SCBRR (SCIF_BASE + 0x0004U) /* 8 Bit rate register */ +#define SCIF_SCSCR (SCIF_BASE + 0x0008U) /* 16 Serial control register */ +#define SCIF_SCFTDR (SCIF_BASE + 0x000CU) /* 8 Transmit FIFO data register */ +#define SCIF_SCFSR (SCIF_BASE + 0x0010U) /* 16 Serial status register */ +#define SCIF_SCFCR (SCIF_BASE + 0x0018U) /* 16 FIFO control register */ +#define SCIF_SCLSR (SCIF_BASE + 0x0024U) /* 16 Line status register */ +#define SCIF_CKS (SCIF_BASE + 0x0034U) /* 16 Clock Select register */ + +#endif /* SCIF_REGISTER_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/secure_boot.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/secure_boot.h new file mode 100644 index 0000000..71116ba --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/secure_boot.h @@ -0,0 +1,60 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + +/******************************************************************************* + * DESCRIPTION : ICUMIF control function header + ******************************************************************************/ +/****************************************************************************** + * @file secure_boot.h + * - Version : 0.03 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 17.06.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + * : 16.02.2023 0.03 Added prototype declaration of final_hash_cmp. + *****************************************************************************/ + +#ifndef SECURE_BOOT_H_ +#define SECURE_BOOT_H_ + +#define SECURE_BOOT (0x0U) +#define NORMAL_BOOT (0x211883DFU) + +#define ROMAPI_OK (0x00000000U) +#define ROM_ERR_IMG_VERIFIER_NO_ENCRYPT_IMG (0xF100001DU) + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void secureboot_init(void); +uint32_t judge_bootmode(void); +void secureboot_verify(LOAD_INFO* li, uint32_t num); +void secureboot_image(LOAD_INFO* li); +void final_hash_cmp(void); + +#endif /* SECURE_BOOT_H_ */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/string.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/string.h new file mode 100644 index 0000000..70d71f4 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/string.h @@ -0,0 +1,51 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : string function header + ******************************************************************************/ +/****************************************************************************** + * @file string.h + * - Version : 0.01 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 06.04.2023 0.01 First Release +*****************************************************************************/ + +#ifndef STRING_H__ +#define STRING_H__ + +#include + +/******************************************************************************* + * Function & variable prototypes + ******************************************************************************/ +void *memcpy(void *dst, const void *src, size_t len); +void *memset(void *dst, int val, size_t len); + +#endif /* STRING_H__ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/swdt.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/swdt.h new file mode 100644 index 0000000..5e8e663 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/swdt.h @@ -0,0 +1,105 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : swdt header + ******************************************************************************/ +/****************************************************************************** + * @file swdt.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 12.08.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ +#ifndef SWDT_H_ +#define SWDT_H_ + +#include +#include "mem_io.h" +#include "rst_register.h" + +#define SWDT_BASE (0xE6030000U) +#define SWDT_WTCNT (SWDT_BASE + 0x0000U) +#define SWDT_WTCSRA (SWDT_BASE + 0x0004U) +#define SWDT_WTCSRB (SWDT_BASE + 0x0008U) + +#define WTCNT_UPPER_BYTE (0x5A5A0000U) +#define WTCSRA_UPPER_BYTE (0xA5A5A500U) +#define WTCSRB_UPPER_BYTE (0xA5A5A500U) +#define WTCNT_RESET_VALUE (0xF488U) +#define WTCSRA_BIT_CKS (0x0007U) +#define WTCSRB_BIT_CKS (0x003FU) +#define SWDT_RSTMSK (0U << 1U) +#define WTCSRA_WOVFE (1U << 3U) +#define WTCSRA_WRFLG (1U << 5U) +#define WTCSRA_TME (1U << 7U) + +#define WDTRSTCR_MASK_ALL (0x0000FFFFU) +#define WTCSRA_MASK_ALL (0x000000FFU) +#define WTCNT_INIT_DATA (WTCNT_UPPER_BYTE + WTCNT_RESET_VALUE) +#define WTCSRA_INIT_DATA (WTCSRA_UPPER_BYTE + 0x0FU) +#define WTCSRB_INIT_DATA (WTCSRB_UPPER_BYTE + 0x21U) + +/* CKS0 setting */ +#define OSCCLK_32 (32U) /* 011:OSCCLK/32 */ +#define WTCSRA_CKS0_OSCCLK (0x00000003U) + +/* WDT Timeout Setting */ +/* OSCCLK */ +#define OSCCLK_133330HZ (133330U) /* MD13=0 MD14=0*/ +#define OSCCLK_131570HZ (131570U) /* MD13=H MD14=L*/ + +/* clock */ +/* (micro sec / (Hz / RPhi) */ +#define CLK_133330HZ ((uint32_t)((1U * 1000U * 1000U) \ + / (OSCCLK_133330HZ / OSCCLK_32))) +#define CLK_131570HZ ((uint32_t)((1U * 1000U * 1000U) \ + / (OSCCLK_131570HZ / OSCCLK_32))) + +#define SWDT_COUNT_SEC (10U) /* set param(1--10sec) */ + +/* SWDT over flow sec need count*/ +#define SWDT_COUNT_133330HZ ((uint32_t)((SWDT_COUNT_SEC * 1000U * 1000U) \ + / CLK_133330HZ)) +#define SWDT_COUNT_131570HZ ((uint32_t)((SWDT_COUNT_SEC * 1000U * 1000U) \ + / CLK_131570HZ)) + +#define SWDTCNT_133330HZ (0x10000U - SWDT_COUNT_133330HZ) +#define SWDTCNT_131570HZ (0x10000U - SWDT_COUNT_131570HZ) + +#define MD14_MD13_TYPE_0 (0x00000000U) /* MD14=0 MD13=0 */ +#define MD14_MD13_TYPE_1 (0x00002000U) /* MD14=0 MD13=1 */ +#define MD14_MD13_TYPE_3 (0x00006000U) /* MD14=1 MD13=1 */ +#define CHECK_MD13_MD14 (0x00006000U) + +/* Prototype */ +void swdt_init(void); +void swdt_exec(void); +void swdt_release(void); +#endif /* SWDT_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/timer.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/timer.h new file mode 100644 index 0000000..207c84a --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/timer.h @@ -0,0 +1,51 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : timer header + ******************************************************************************/ +/****************************************************************************** + * @file timer.h + * - Version : 0.03 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 09.05.2022 0.02 Moved the definition of the define value + * : 31.10.2022 0.03 License notation change. + *****************************************************************************/ +#ifndef TIMER_H_ +#define TIMER_H_ + +#include +#include + +/* Prototype */ +void generic_timer_init(void); +void micro_wait(uint64_t micro_sec); + +#endif /* TIMER_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/include/types.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/types.h new file mode 100644 index 0000000..b4860d2 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/include/types.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Type header + ******************************************************************************/ +/****************************************************************************** + * @file types.h + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + + +#ifndef TYPES_H +#define TYPES_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * File Name: types.h + * Contents : Types Define + ****************************************************************************/ +#include +#include + +#ifndef FALSE +#define FALSE (0U) +#endif + +#ifndef TRUE +#define TRUE (1U) +#endif + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/boot_init_dram.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/boot_init_dram.h new file mode 100644 index 0000000..c6b8b47 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/boot_init_dram.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#ifndef BOOT_INIT_DRAM +#define BOOT_INIT_DRAM + +extern uint32_t R_DRAM_Init(void); +#if (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) +void r_set_pi_rdlvl_interval(void); +#endif + +#define INITDRAM_OK (0) +#define INITDRAM_NG (0xFFFFFFFFU) +#define INITDRAM_ERR_I (0xFFFFFFFFU) + +#endif /* BOOT_INIT_DRAM */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/ddr.mk b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/ddr.mk new file mode 100644 index 0000000..a245832 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/ddr.mk @@ -0,0 +1,12 @@ +# +# Copyright (c) 2015-2023, Renesas Electronics Corporation All rights reserved. +# + +ifeq (${LSI},V4H) + OBJ_FILE += ip/ddr/v4h/lpddr5/boot_init_dram.o + OBJ_FILE += ip/ddr/v4h/lpddr5/boot_init_dram_config.o +else ifeq (${LSI},V4M) + OBJ_FILE += ip/ddr/v4m/lpddr5/boot_init_dram.o + OBJ_FILE += ip/ddr/v4m/lpddr5/boot_init_dram_config.o +endif +OBJ_FILE += ip/ddr/dram_sub_func.o \ No newline at end of file diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/dram_sub_func.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/dram_sub_func.c new file mode 100644 index 0000000..9d3b535 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/dram_sub_func.c @@ -0,0 +1,36 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#include +#include "dram_sub_func.h" + +void R_DRAM_Get_Boot_Status(uint32_t *status) +{ + *status = DRAM_BOOT_STATUS_COLD; +} + +uint32_t R_DRAM_Update_Boot_Status(uint32_t status) +{ + uint32_t ret = 0U; + return ret; +} diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/dram_sub_func.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/dram_sub_func.h new file mode 100644 index 0000000..ac9493b --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/dram_sub_func.h @@ -0,0 +1,33 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#ifndef DRAM_SUB_FUNC +#define DRAM_SUB_FUNC + +#define DRAM_BOOT_STATUS_COLD (0U) +#define DRAM_BOOT_STATUS_WARM (1U) + +void R_DRAM_Get_Boot_Status(uint32_t *status); +uint32_t R_DRAM_Update_Boot_Status(uint32_t status); + +#endif /* DRAM_SUB_FUNC_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram.c new file mode 100644 index 0000000..1fc3ebb --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram.c @@ -0,0 +1,4613 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#else +#include "mem_io.h" +#include "log.h" +#endif +#include "ddr_regdef.h" +#include "init_dram_tbl_v4h_lp5.h" +#include "boot_init_dram_regdef.h" +#include "boot_init_dram.h" +#include "dram_sub_func.h" + +/******************************************************************************* + * load board configuration + ******************************************************************************/ +#include "boot_init_dram_config.h" + +//! @details Implement for suspend to Ram. +#define DDR_BACKUPMODE + +//! @details Define the function of log output. +#define FATAL_MSG(x) NOTICE(x) + +/******************************************************************************* + * variables + ******************************************************************************/ +static uint32_t Prr_Product; +static uint32_t Prr_Cut; +//! @details The board parameter index which you use. +static uint32_t BOARDTYPE; +//! @details The board clock frequency +static uint32_t brd_clk; +//! @details The board clock frequency division +static uint32_t brd_clkdiv; +//! @details The board clock frequency division A +static uint32_t brd_clkdiva; +//! @details The Mbps of DDR +static uint32_t ddr_mbps; +//! @details The Mbps division of DDR +static uint32_t ddr_mbpsdiv; +//! @details Decimal multiplication setting value +static uint32_t sscg; +//! @details The Mbps of Bus, The Mbps division of Bus +static uint32_t bus_clk, bus_clkdiv; +//! @details The tccd value of DDR +static uint32_t ddr_tccd; +//! @details The parameter structure of the board you use +static const st_boardcnf_t *Boardcnf; +//! @details Value indicating the enabled channel +static uint32_t ddr_phyvalid; +//! @details Memory capacity in each channel and each CS +static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; +//! @details Indicates channels used for each memory rank +static uint32_t ch_have_this_cs[CS_CNT]; +//! @details The maximum memory capacity +static uint32_t max_density; +//! @details One of the DDR memory multiplier setting value +static uint32_t ddr_mul; +//! @details One of the DDR memory multiplier setting value +static uint32_t ddr_mul_nf; +//! @details One of the DDR memory multiplier setting value +static uint32_t ddr_mul_low; +//! @details One of the DDR memory multiplier setting value +static uint32_t ddr_mul_reg; + +//! @details Number of elements in DDRPHY register setting array +#define DDR_PHY_REGSET_MAX 153 +//! @details Number of elements in PI register setting array +#define DDR_PI_REGSET_MAX 1381 + +//! @details Array for DDRPHY Slice settings +static uint32_t DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX]; +//! @details Array for DDRPHY ADRRESS VALUE Slice settings +static uint32_t DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; +//! @details Array for DDRPHY ADRRESS CONTROL Slice settings +static uint32_t DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; +//! @details Array for DDR PI Slice settings +static uint32_t DDR_PI_REGSET[DDR_PI_REGSET_MAX]; +#ifdef DDR_BACKUPMODE +//! @details Boot mode of ICUMX Loader +static uint32_t ddrBackup; +#endif + +#ifndef RCAR_PLL3_FRAC_MODE +//! @details SS Mode for PLL3 +#define RCAR_PLL3_FRAC_MODE (1U) +#endif + +#ifndef RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE +//! @details Fast loading mode of DDRPHY register +#define RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE (1U) +#endif + +//! @details PLL3 configuration value of low frequency mode +#define PLL3_LOW_FREQUENCY_MODE (0U) +//! @details PLL3 configuration value of high frequency mode +#define PLL3_HIGH_FREQUENCY_MODE (2U) +//! @details PLL3 configuration value of high frequency mode load register +#define PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER (3U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static uint32_t r_vch_nxt(uint32_t pos); +static void r_cpg_write_32(uint32_t a, uint32_t v); +static void r_pll3_control(uint32_t mode); +static void r_send_dbcmd2(uint32_t cmd); +static uint32_t r_reg_ddrphy_read(uint32_t phyno, uint32_t regadd); +static void r_reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata); +static void r_reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata); +static void r_reg_ddrphy_masked_write(uint32_t phyno, uint32_t regadd, uint32_t regdata, uint32_t msk); +static void r_ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t regdef, uint32_t val); +static uint32_t r_ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t regdef); +static void r_ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val); +static void r_ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); +static void r_ddr_setval_ach(uint32_t regdef, uint32_t val); +static void r_ddr_setval_ach_as(uint32_t regdef, uint32_t val); +static uint32_t r_ddr_getval(uint32_t ch, uint32_t regdef); +static void r_tbl_copy(uint32_t *to, const uint32_t *from, uint32_t size); +static void r_ddrtbl_setval(uint32_t *tbl, uint32_t regdef, uint32_t val); +static void r_ddrtbl_setval_pi(uint32_t *tbl, uint32_t regdef, uint32_t val); +static uint32_t r_ddrtbl_getval(const uint32_t *tbl, uint32_t regdef); +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) +static uint32_t r_ddrtbl_getval_pi(const uint32_t *tbl, uint32_t regdef); +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ +static uint16_t r_f_scale(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint16_t cyc); +static uint32_t r_f_scale_l(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint32_t cyc); +static void r_f_scale_js2(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t *f_js2); +static void r_ddrtbl_load(void); +static void r_ddr_config(void); +static void r_dbsc_regset(void); +static void r_dbsc_regset_post(void); +static void r_ddr_register_set(void); +static void r_ddr_register_read(void); +static uint32_t r_wait_freqchgreq(uint32_t req_assert); +static void r_set_freqchgack(uint32_t ack_assert); +static uint32_t r_pi_training(void); +static void r_write_leveling_adjust(void); +static uint32_t r_wl_gt_training(void); +static void r_write_dca(void); +static uint32_t r_dramdca_training(void); +static uint32_t r_write_leveling(void); +static void r_manual_write_dca(void); +static uint32_t r_read_gate_training(void); +static uint32_t r_read_vref_training(void); +static uint32_t r_read_write_training(void); +static uint32_t r_read_training(void); +static uint32_t r_pll3_freq(void); +static uint32_t r_init_ddr(void); +static void r_dbsc_write_32(uintptr_t addr, uint32_t data); +static uint32_t r_pi_int_ack_0_assert(uint32_t bit); + +/** +* Macro for channel selection loop +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-01:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] pos Start channel of validity check +* @return uint32_t Effective channel +* @details Returns the ID of the channel to be used.\n +* -# Check for valid channels between the value of posn and the maximum number of CHs.\n +* -# If a valid channel is found, returns the value of that channel. +*/ +static uint32_t r_vch_nxt(uint32_t pos) +{ + uint32_t posn; + + for (posn = pos; posn < DRAM_CH_CNT; posn++) + { + if ((ddr_phyvalid & (1U << posn)) != 0x0U) + { + break; + } + } + return posn; +} + +//! @details Select only valid channels in all channels from CH0. +#define r_foreach_vch(ch) \ +for (ch = r_vch_nxt(0); ch < DRAM_CH_CNT; ch = r_vch_nxt(ch + 1U)) + +//! @details All channels are selected. +#define r_foreach_ech(ch) \ +for (ch = 0U; ch < DRAM_CH_CNT; ch++) + +//! @details Printing functions +#define MSG_LF(...) + +/** +* Clock settings and reset control +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-02:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] a Destination address +* @param[in] v Setting value +* @details +* -# Write the complement value of setting value to the CPG_CPGWPR register\n +* for releaseing the protect.\n +* -# Write setting value to destination address. +*/ +static void r_cpg_write_32(uint32_t a, uint32_t v) +{ + mmio_write_32(CPG_CPGWPR, ~v); + mmio_write_32(a, v); +} + +/** +* Setting PLL3 +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-01:V4H-LPDDR5-DDR-HW-DD-10-02-02 +* @param[in] mode Selection of frequency +* @details +*-# Determine the set value according to the frequency mode of the argument.\n +*-# Write the set value to CPG_FRQCRD0 register and CPG_FRQCRD0 one.\n +*-# Reflect settings +*/ +static void r_pll3_control(uint32_t mode) +{ + uint32_t dataDIV, ssmode_high, dataMUL; + uint32_t ssmode, dataNF; + /* PLL3VCO = EXTAL * ddr_mul * 1/2 */ + /* clk_ctlr_sync = PLL3VCO * pll3_div */ + /* ddr_mul = (NI[7:0] + 1) * 2 + NF[24:0] / 2^24 */ + +#if RCAR_PLL3_FRAC_MODE == 1U + ssmode_high = 0x4U; +#else + ssmode_high = 0x0U; +#endif + + switch (mode) + { + case PLL3_LOW_FREQUENCY_MODE: + /* Low frequency mode (50MHz) */ + dataMUL = (ddr_mul_low / 2U) - 1U; /* PLL3VCO = 1600MHz */ + dataDIV = 0x9U; /* div = 32 */ + dataNF = 0x00U; + ssmode = 0x0U; + break; + case PLL3_HIGH_FREQUENCY_MODE: + /* High frequency mode */ + dataMUL = (ddr_mul / 2U) - 1U; + dataDIV = 0x0U; /* div = 2 */ + dataNF = ddr_mul_nf; + ssmode = ssmode_high; + break; + case PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER: + /* High frequency mode for loading to DDRPHY registers */ + dataMUL = (ddr_mul_reg / 2U) - 1U; + dataDIV = 0x0U; /* div = 2 */ + dataNF = 0x00U; + ssmode = ssmode_high; + break; + default: + /* High frequency mode */ + dataMUL = (ddr_mul / 2U) - 1U; + dataDIV = 0x0U; /* div = 2 */ + dataNF = ddr_mul_nf; + ssmode = ssmode_high; + break; + }/* mode */ + + dataMUL = (dataMUL << 20) | (ssmode << 16); + dataNF = (dataNF << 21); + + if (((mmio_read_32(CPG_PLL3CR0) & 0x3FFFFF7FU) != dataMUL) || (mmio_read_32(CPG_PLL3CR1) != dataNF)) + { + /* PLL3CR0 multiplie set */ + r_cpg_write_32(CPG_PLL3CR0, dataMUL); + /* PLL3CR1 multiplie set */ + r_cpg_write_32(CPG_PLL3CR1, dataNF); + r_cpg_write_32(CPG_PLL3CR0, mmio_read_32(CPG_PLL3CR0) | CPG_PLL3CR0_KICK_BIT); + while ((mmio_read_32(CPG_PLLECR) & CPG_PLLECR_PLL3ST_BIT) != CPG_PLLECR_PLL3ST_BIT) + { + ; /* Nothing */ + } + } + + /* PLL3 DIV set(Target value) */ + while (((mmio_read_32(CPG_FRQCRD0) & CPG_FRQCRD_KICK_BIT)) != 0x0U) + { + ; /* Nothing */ + } + r_cpg_write_32(CPG_FRQCRD0, dataDIV | (mmio_read_32(CPG_FRQCRD0) & 0xFFFFFFF0U)); + r_cpg_write_32(CPG_FRQCRD0, mmio_read_32(CPG_FRQCRD0) | CPG_FRQCRD_KICK_BIT); + while (((mmio_read_32(CPG_FRQCRD0) & CPG_FRQCRD_KICK_BIT)) != 0x0U) + { + ; /* Nothing */ + } +} + +/** +* DRAM Command Write Access +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-03:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] cmd DRAM command. +* @details +* -# First, execute the dummy read to DBSC_DBCMD.\n +* -# Confirm that no DBSC command operation is in progress 0.\n +* -# Write the contents of the command to be sent to DRAM.. +*/ +static void r_send_dbcmd2(uint32_t cmd) +{ + /* dummy read */ + mmio_read_32(DBSC_DBCMD); + + while (((mmio_read_32(DBSC_DBWAIT)) & 0x01U) != 0x0U) + { + ; /* Nothing */ + } + while (((mmio_read_32(DBSC_DBWAIT + 0x00004000U)) & 0x01U) != 0x0U) + { + ; /* Nothing */ + } + + r_dbsc_write_32((DBSC_DBCMD), cmd); +} + +/** +* DDRPHY register read +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-04:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] phyno Target channel +* @param[in] regadd Destination address of target ddrphy register +* @return uint32_t Result of read access +* @details +* -# Write the destination address of ddrphy to DBSC_DBPDRGA(ch) register.\n +* -# Wait until the status bit in the DBSC_DBPDRGD register indicates completion. +* -# Read the value of the DDRPHY register from DBSC_DBPDRGD. +* -# Clear the status bit of DBSC_DBPDRGD register twice. +* -# Read the value of the DDRPHY register from DBSC_DBPDRGD. +* -# Dummy reads the variable val. +*/ +static uint32_t r_reg_ddrphy_read(uint32_t phyno, uint32_t regadd) +{ + uint32_t val; + + val = 0U; + mmio_write_32(DBSC_DBPDRGA(phyno), (regadd | 0x00004000U)); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x0000C000U)) + { + ; /* Nothing */ + } + + val = mmio_read_32(DBSC_DBPDRGA(phyno)); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + val = mmio_read_32(DBSC_DBPDRGD(phyno)); + (void)val; + + return val; +} + +/** +* DDRPHY register write +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-05:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] phyno Target channel +* @param[in] regadd Destination address of target ddrphy register +* @param[in] regdata Setting value to be written +* @details +* -# Write the destination address of ddrphy to DBSC_DBPDRGA(ch) register.\n +* -# Write setting value to be written to target address. +* -# Clear the status bit of DBSC_DBPDRGD register twice. +* -# Write the destination address of ddrphy to DBSC_DBPDRGA(ch) register.\n +*/ +static void r_reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) +{ + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGD(phyno), regdata); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x00008000U)) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), (regadd | 0x00008000U)); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); +} + +/** +* DDRPHY register write for valid channels +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-06:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] regadd Destination address +* @param[in] regdata Setting value to be written +* @details +* -# Call the "r_reg_ddrphy_write" func for only valid channels. +*/ +static void r_reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) +{ + uint32_t ch; + + r_foreach_vch((ch)) + { + r_reg_ddrphy_write(ch, regadd, regdata); + } +} + +/** +* Write the value to the register of ddrphy. +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-23:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] phyno The channel of DBSC +* @param[in] regadd Destination address +* @param[in] regdata Setting value to be written +* @param[in] msk The value of Mask +* @details +* -# Write the value of the argument msk to DBSC_DBPDRGM. Wait until the write process completed.\n +* -# Write the value of the argument regadd to DBSC_DBPDRGA. Wait until the write process completed.\n +* -# Write the value of the argument regdate to DBSC_DBPDRGD. Wait until the write process completed.\n +* -# Write the value of the argument regadd to DBSC_DBPDRGA. Wait until the write process completed.\n +* -# Write the value of the argument regadd to DBSC_DBPDRGA.\n +* -# Write the value of the argument msk to DBSC_DBPDRGM. Wait until the write process completed.\n +*/ +static void r_reg_ddrphy_masked_write(uint32_t phyno, uint32_t regadd, uint32_t regdata, uint32_t msk) +{ + mmio_write_32(DBSC_DBPDRGM(phyno), msk); + while (mmio_read_32(DBSC_DBPDRGM(phyno)) != msk) + { + ; /* do nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* do nothing */ + } + + mmio_write_32(DBSC_DBPDRGD(phyno), regdata); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x00008000U)) + { + ; /* do nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* do nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + + mmio_write_32(DBSC_DBPDRGM(phyno), 0x00U); + while (mmio_read_32(DBSC_DBPDRGM(phyno)) != 0x00U) + { + ; /* do nothing */ + } +} + +/** +* DDRPHY register access write (field modify) +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-07:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] ch Target ch +* @param[in] slice Target slice +* @param[in] regdef Information of destination bit field +* @param[in] val Setting value to be written +* @details +* -# Calculate the bit field in which to write the setting value\n +* from "regdef" value. +* -# Call r_reg_ddrphy_write() to write the setting value.\n +*/ +static void r_ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + + adr = DDR_REGDEF_ADR(regdef) + (0x100U * slice); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + tmp = 0xFFFFFFFFU; + } + else + { + tmp = ((1U << len) - 1U) << lsb; + } + + msk = (~(((tmp >> 21) & 0x08U) | ((tmp >> 14) & 0x04U) | ((tmp >> 7) & 0x02U) | (tmp & 0x01U))) & 0x0FU; + + r_reg_ddrphy_masked_write(ch, adr, (val << lsb), msk); +} + +/** +* DDRPHY register access read (field modify) +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-08:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] ch Target ch +* @param[in] slice Target slice +* @param[in] regdef Information of destination bit field +* @details +* -# Calculate the address and the bit-field from "regdef" value.\n +* -# Call r_reg_ddrphy_read() to read value from the target address. +*/ +static uint32_t r_ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + + adr = DDR_REGDEF_ADR(regdef) + (0x100U * slice); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U); + } + + tmp = r_reg_ddrphy_read(ch, adr); + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +/** +* DDRPHY register access write for slice0 (field modify) +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-09:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] ch Target ch +* @param[in] regdef Information of destination bit field +* @param[in] val Setting value to be written +* @details +* -# Call the "r_ddr_setval_s" func. In this case, the argument slice is 0. +*/ +static void r_ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) +{ + r_ddr_setval_s(ch, 0U, regdef, val); +} + +/** +* DDRPHY register access write for all channel/slice (field modify) +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-10:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] slice Target slice +* @param[in] regdef Information of destination bit field +* @param[in] val Setting value to be written +* @details +* -# Call the "r_ddr_setval_s" func for valid channels. +*/ +static void r_ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val) +{ + uint32_t ch; + + r_foreach_vch((ch)) + { + r_ddr_setval_s(ch, slice, regdef, val); + } +} + +/** +* DDRPHY register access write for all channel and slice0 (field modify) +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-11:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] regdef Information of destination bit field +* @param[in] val Setting value to be written +* @details Call the "r_ddr_setval_ach_s" func. In this case, the argument slice is 0. +*/ +static void r_ddr_setval_ach(uint32_t regdef, uint32_t val) +{ + r_ddr_setval_ach_s(0U, regdef, val); +} + +/** +* DDRPHY register access write for all channels and all slices (field modify) +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-12:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] regdef Information of destination bit field +* @param[in] val Setting value to be written +* @details +* -# Call the "r_ddr_setval_ach_s" func for all sleces. +*/ +static void r_ddr_setval_ach_as(uint32_t regdef, uint32_t val) +{ + uint32_t slice; + + for (slice = 0U; slice < SLICE_CNT; slice++) + { + r_ddr_setval_ach_s(slice, regdef, val); + } +} + +/** +* DDRPHY register access read to slices0 (field modify) +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-13:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] ch Target channel +* @param[in] regdef Information of destination bit field +* @details +* -# Call the "r_ddr_getval_s" func to slece0. +*/ +static uint32_t r_ddr_getval(uint32_t ch, uint32_t regdef) +{ + return r_ddr_getval_s(ch, 0U, regdef); +} + +/** +* DBSC register access +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-14:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] addr Destination address +* @param[in] data Setting value to be written +* @details +* -# Stores "data" in the pointer indicated by the argument "addr". +*/ +static void r_dbsc_write_32(uintptr_t addr, uint32_t data) +{ + *((volatile uint32_t*)addr) = data; + if ((addr & 0x000A0000U) == 0x000A0000U) + { + *((volatile uint32_t*)(addr + 0x00004000U)) = data; + } + else + { + *((volatile uint32_t*)(addr + 0x00008000U)) = data; + } +} + +/** +* handling functions for setteing ddrphy value table +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-15:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] to First pointer of the static array where the setting value is stored +* @param[in] from First pointer of the source static array +* @param[in] size The size of the source static array +* @details +* -# Copy all the elements of the array specified by "from" pointer to by "to" pointer. +*/ +static void r_tbl_copy(uint32_t *to, const uint32_t *from, uint32_t size) +{ + uint32_t i; + + for (i = 0U; i < size; i++) + { + to[i] = from[i]; + } +} + +/** +* Edit the setting table to the PHY register. +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-16:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] tbl The pointer of target configuration table +* @param[in] regdef Information of destination bit field +* @param[in] val Setting value to be written +* @details +* -# Calculate the target index of *tbl and the bit-field to write the setting value\n +* from "regdef" value.\n +* -# Write the setting value to the target bit-field in the index. +*/ +static void r_ddrtbl_setval(uint32_t *tbl, uint32_t regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000000FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U) << lsb; + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + tbl[adr & adrmsk] = tmp; +} + +/** +* Edit the setting table to the PI register. +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-17:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] tbl The pointer of target configuration table +* @param[in] regdef Information of destination bit field +* @param[in] val Setting value to be written +* @details +* -# Calculate the target index of *tbl and the bit-field to write the setting value\n +* from "regdef" value.\n +* -# Write the setting value to the target bit-field in the index. +*/ +static void r_ddrtbl_setval_pi(uint32_t *tbl, uint32_t regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000007FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U) << lsb; + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + tbl[adr & adrmsk] = tmp; +} + +/** +* Reads the setting values from the setting table to the PHY registers +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-18:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] tbl The pointer of target configuration table +* @param[in] regdef Information of destination bit field +* @details +* -# Calculate the target index of *tbl and the bit-field to read the setting value.\n +* -# Read the setting value from the target bit-field in the index. +*/ +static uint32_t r_ddrtbl_getval(const uint32_t *tbl, uint32_t regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000000FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U); + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) +/** +* Reads the setting values from the setting table to the PI registers +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-19:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] tbl The pointer of target configuration table +* @param[in] regdef Information of destination bit field +* @details +* -# Calculate the target index of *tbl and the bit-field to read the setting value.\n +* -# Read the setting value from the target bit-field in the index. +*/ +static uint32_t r_ddrtbl_getval_pi(const uint32_t *tbl, uint32_t regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000007FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U); + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp >> lsb) & msk; + + return tmp; +} +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + +//! @details functions and parameters for timing setting +typedef struct +{ + //! @details Frequency + uint32_t fx3; + //! @details setting value of Read Latency + uint8_t RLset1; + //! @details setting value of Read Latency + uint8_t RLset2; + //! @details setting value of Write Latency + uint8_t WLsetA; + //! @details setting value of Write Latency + uint8_t WLsetB; + //! @details Write-Recovery for Auto-Precharge commands + uint32_t nWR; + //! @details the minimum interval from a READ command to a PRE command + uint32_t nRBTP; + //! @details On Die Termination + uint32_t ODTLon; + //! @details Mode Register 1 + uint8_t MR1; + //! @details Mode Register 2 + uint8_t MR2; + //! @details The setting time from CAS command to the Start-up of WCK in READ operation + uint32_t WCKENLR; + //! @details The setting time from CAS command to the Start-up of WCK in WRITE operation + uint32_t WCKENLW; + //! @details The setting time from CAS command to the Start-up of WCK in FAST-sync operation + uint32_t WCKENLF; + //! @details The setting time from the Start-up of WCK to WCK Clocling Start + uint32_t WCKPRESTA; + //! @details The setting time from WCK Clocling Start to Reflecting frequency of WCK + uint32_t WCKPRETGLR; +} jedec_spec1_t; + +//! @details Minimum value table for JS1 configuration table that can be taken +#define JS1_USABLEC_SPEC_LO 5U +//! @details Maximum value table for JS1 configuration table that can be taken +#define JS1_USABLEC_SPEC_HI 11U +//! @details The number of JS1 setting table +#define JS1_FREQ_TBL_NUM 12U +//! @details Macro to set the value of MR1 +#define JS1_MR1(f) (0x00U | ((f) << 4)) /* CK mode = 0B */ +//! @details Macro to set the value of MR2 +#define JS1_MR2(f) (((f) << 4) | (f)) +//! @details Declaration of setting table of jedec spec1 +static const jedec_spec1_t js1[JS1_FREQ_TBL_NUM] = +{ + /* fx3, RL1, RL2, WLA.WLB.nWR.nRBTP, ODTLon */ + { 800, 3, 3, 2, 2, 3, 0, 1, JS1_MR1(0), JS1_MR2(0), 0, 0, 0, 1, 3 }, /* 533.333Mbps*/ + { 1600, 4, 4, 2, 3, 5, 0, 1, JS1_MR1(1), JS1_MR2(1), 0, 0, 0, 1, 4 }, /* 1066.666Mbps*/ + { 2400, 5, 6, 3, 4, 7, 0, 2, JS1_MR1(2), JS1_MR2(2), 1, 1, 1, 1, 4 }, /* 1600.000Mbps*/ + { 3200, 7, 7, 4, 5, 10, 0, 2, JS1_MR1(3), JS1_MR2(3), 2, 1, 1, 2, 4 }, /* 2133.333Mbps*/ + { 4000, 8, 9, 4, 7, 12, 1, 2, JS1_MR1(4), JS1_MR2(4), 2, 1, 1, 2, 5 }, /* 2666.666Mbps*/ + { 4800, 10, 10, 5, 8, 14, 1, 3, JS1_MR1(5), JS1_MR2(5), 4, 2, 1, 2, 5 }, /* 3200.000Mbps*/ + { 5600, 11, 12, 6, 9, 16, 2, 4, JS1_MR1(6), JS1_MR2(6), 4, 2, 1, 3, 5 }, /* 3733.333Mbps*/ + { 6400, 13, 14, 6, 11, 19, 2, 3, JS1_MR1(7), JS1_MR2(7), 5, 2, 1, 3, 6 }, /* 4266.666Mbps*/ + { 7200, 14, 15, 7, 12, 21, 3, 4, JS1_MR1(8), JS1_MR2(8), 6, 3, 2, 3, 6 }, /* 4800.000Mbps*/ + { 8250, 16, 17, 8, 14, 24, 4, 5, JS1_MR1(9), JS1_MR2(9), 7, 3, 2, 4, 6 }, /* 5500.000Mbps*/ + { 9000, 17, 19, 9, 15, 26, 4, 6, JS1_MR1(10), JS1_MR2(10), 7, 4, 2, 4, 7 }, /* 6000.000Mbps*/ + { 9600, 18, 20, 9, 16, 28, 4, 6, JS1_MR1(11), JS1_MR2(11), 8, 4, 2, 4, 7 } /* 6400.000Mbps*/ +}; + +//! @details Define of structure of jedec spec2 +typedef struct +{ + //! @details Value in pico seconds + uint16_t ps; + //! @details Value in cycle count + uint16_t cyc; +} jedec_spec2_t; + +//! @details Element for self refresh +#define JS2_tSR 0U +//! @details Exit power-down mode to first valid command +#define JS2_tXP 1U +//! @details Active to read or write delay +#define JS2_tRCD 2U +//! @details Minimum Row Precharge Delay Time +#define JS2_tRPpb 3U +//! @details Minimum Row Precharge Delay Time +#define JS2_tRPab 4U +//! @details ACTIVE-to-PRECHARGE command +#define JS2_tRAS 5U +//! @details Internal WRITE-to-READ command delay +#define JS2_tWTR_S 6U +//! @details Internal WRITE-to-READ command delay +#define JS2_tWTR_L 7U +//! @details Active bank a to active bank b command +#define JS2_tRRD 8U +//! @details Precharge Power Down +#define JS2_tPPD 9U +//! @details Four bank ACT window +#define JS2_tFAW 10U +//! @details Mode Register Read +#define JS2_tMRR 11U +//! @details Mode Register Write +#define JS2_tMRW 12U +//! @details LOAD MODE REGISTER command cycle time +#define JS2_tMRD 13U +//! @details ZQ Calibration +#define JS2_tZQCALns 14U +//! @details ZQ Latency +#define JS2_tZQLAT 15U +//! @details Minimum time on die termination +#define JS2_tODTon_min 16U +//! @details recommended minimum time for Deep Sleep Mode duration +#define JS2_tPDN_DSM 17U +//! @details Required time to be fully re-powered up from Deep Sleep Mode +#define JS2_tXSR_DSM 18U +//! @details Delay from Deep Sleep Mode Exit to Power-Down Exit +#define JS2_tXDSM_XP 19U +//! @details Setting value of DQ to WCK input offset +#define JS2_tWCK2DQI_HF 20U +//! @details Setting value of WCK to DQ output offset +#define JS2_tWCK2DQO_HF 21U +//! @details Setting value of DQ to WCK input offset +#define JS2_tWCK2DQI_LF 22U +//! @details Setting value of WCK to DQ output offset +#define JS2_tWCK2DQO_LF 23U +//! @details Delay time from Stop WCK2DQI Interval Oscillator command to Mode Register Readout +#define JS2_tOSCODQI 24U +//! @details Reception time to change the value fof REF(CA) for Command Bus Training Mode2 +#define JS2_tDQ72DQns 25U +//! @details Reception time to change the value fof REF(CA) for Command Bus Training Mode1 +#define JS2_tCAENTns 26U +//! @details Minimum CA Low Duration time +#define JS2_tCSCAL 27U +//! @details The number of table +#define JS2_TBLCNT 28U +//! @details ACTIVATE-to-ACTIVATE command period with per bank precharge +#define JS2_tRCpb (JS2_TBLCNT) +//! @details ACTIVATE-to-ACTIVATE command period with all bank precharge +#define JS2_tRCab (JS2_TBLCNT + 1U) +//! @details Refresh Cycle Time with All Banks +#define JS2_tRFCab (JS2_TBLCNT + 2U) +//! @details READ Burst end to PRECHARGE command delay +#define JS2_tRBTP (JS2_TBLCNT + 3U) +//! @details Exit Self Refresh to Valid commands +#define JS2_tXSR (JS2_TBLCNT + 4U) + +#define JS2_tPDN (JS2_TBLCNT + 5U) +#define JS2_tWLWCKOFF (JS2_TBLCNT + 6U) +#define JS2_CNT (JS2_TBLCNT + 7U) + +#ifndef JS2_DERATE +#define JS2_DERATE 0 +#endif + +//! @details Declaration of setting table of jedec spec2 +static const jedec_spec2_t jedec_spec2[2][JS2_TBLCNT] = +{ + { +/*tSR */ { 15000, 2 }, +/*tXP */ { 7000, 3 }, +/*tRCD */ { 18000, 2 }, +/*tRPpb */ { 18000, 2 }, +/*tRPab */ { 21000, 2 }, +/*tRAS */ { 42000, 3 }, +/*tWTR_S */ { 6250, 4 }, +/*tWTR_L */ { 12000, 4 }, +/*tRRD */ { 5000, 2 }, +/*tPPD */ { 0, 2 }, +/*tFAW */ { 20000, 0 }, +/*tMRR*/ { 0, 4 }, +/*tMRW*/ { 10000, 5 }, +/*tMRD*/ { 14000, 5 }, +/*tZQCALns*/ { 1500, 0 }, +/*tZQLAT*/ { 30000, 4 }, +/*tODTon_min*/ { 1500, 0 }, +/*tPDN_DSMus*/ { 4000, 0 }, +/*tXSR_DSMus*/ { 200, 0 }, +/*tXDSM_XPus*/ { 190, 0 }, +/*tWCK2DQI_HF*/ { 700, 0 }, +/*tWCK2DQO_HF*/ { 1600, 0 }, +/*tWCK2DQI_LF*/ { 900, 0 }, +/*tWCK2DQO_LF*/ { 1900, 0 }, +/*tOSCODQI*/ { 40000, 8 }, +/*tDQ72DQns*/ { 125, 0 }, +/*tCAENTns*/ { 250, 0 }, +/*tCSCAL*/ { 1750, 0 } + },{ +/*tSR */ { 15000, 2 }, +/*tXP */ { 7000, 3 }, +/*tRCD */ { 19875, 2 }, +/*tRPpb */ { 19875, 2 }, +/*tRPab */ { 22875, 2 }, +/*tRAS */ { 43875, 3 }, +/*tWTR_S */ { 6250, 4 }, +/*tWTR_L */ { 12000, 4 }, +/*tRRD */ { 5000, 2 }, +/*tPPD */ { 0, 2 }, +/*tFAW */ { 20000, 0 }, +/*tMRR*/ { 0, 4 }, +/*tMRW*/ { 10000, 5 }, +/*tMRD*/ { 14000, 5 }, +/*tZQCALns*/ { 1500, 0 }, +/*tZQLAT*/ { 30000, 4 }, +/*tODTon_min*/ { 1500, 0 }, +/*tPDN_DSMus*/ { 4000, 0 }, +/*tXSR_DSMus*/ { 200, 0 }, +/*tXDSM_XPus*/ { 190, 0 }, +/*tWCK2DQI_HF*/ { 715, 0 }, +/*tWCK2DQO_HF*/ { 1635, 0 }, +/*tWCK2DQI_LF*/ { 920, 0 }, +/*tWCK2DQO_LF*/ { 1940, 0 }, +/*tOSCODQI*/ { 40000, 8 }, +/*tDQ72DQns*/ { 125, 0 }, +/*tCAENTns*/ { 250, 0 }, +/*tCSCAL*/ { 1750, 0 } + } +}; + +//! @details 4Gb, 6Gb, 8Gb,12Gb,16Gb (24Gb/32Gb non) +static const uint16_t jedec_spec2_tRFC_ab[9] = +{ +/* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 130, 180, 180, 210, 210, 280, 280, 380, 380 +}; + +//! @details Index of jedec spec1 setting table you use +static uint32_t js1_ind; +//! @details Static global array of jedec spec2 setting table +static uint32_t js2[JS2_CNT]; +//! @details Read latency +static uint32_t RL; +//! @details Write latency +static uint32_t WL; + +/** +* Selection the best value for the setting value among the two elements of structure jedec_spec2 +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-20:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] f_ddr_mbps DDR transmission frequency +* @param[in] f_ddr_mbpsdiv Division DDR transmission frequency +* @param[in] ps Optimal setting value in pico second +* @param[in] cyc Optimal setting value in cycle count +* @return uint32_t Selected the best value for DBSC timing setting +* @details +* -# Convert the optimal value in pico second to in cycle count.\n +* -# Compare the value of the result of the conversion with the value of the argument cyc.\n +* -# Returns the larger value. +*/ +static uint16_t r_f_scale(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint16_t cyc) +{ + uint32_t tmp; + uint32_t f_scale_div; + + tmp = (((uint32_t)(ps) + 9U) / 10U) * f_ddr_mbps; + f_scale_div = tmp / (800000U * f_ddr_mbpsdiv); + if (tmp != (f_scale_div * 800000U * f_ddr_mbpsdiv)) + { + f_scale_div = f_scale_div + 1U; + } + + if (f_scale_div > cyc) + { + cyc = (uint16_t)f_scale_div; + } + + return cyc; +} + +/** +* Selection the best value for the setting value among the two elements of structure jedec_spec2 +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-21:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] f_ddr_mbps DDR transmission frequency +* @param[in] f_ddr_mbpsdiv Division DDR transmission frequency +* @param[in] ps Optimal setting value in pico second +* @param[in] cyc Optimal setting value in cycle count +* @return uint32_t Selected the best value for DBSC timing setting +* @details +* -# Convert the optimal value in pico second to in cycle count. Perform fractional rounding.\n +* -# Compare the value of the result of the conversion with the value of the argument cyc.\n +* -# Returns the larger value. +*/ +static uint32_t r_f_scale_l(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint32_t cyc) +{ + uint32_t tmp; + uint32_t f_scale_div; + + tmp = (((uint32_t)(ps) + 9U) / 10U) * f_ddr_mbps; + f_scale_div = tmp / (8U * f_ddr_mbpsdiv); + if (tmp != (f_scale_div * 8U * f_ddr_mbpsdiv)) + { + f_scale_div = f_scale_div + 1U; + } + + if (f_scale_div > cyc) + { + cyc = (uint32_t)f_scale_div; + } + + return cyc; +} + +/** +* Selection the best value for the setting value among the two elements of structure jedec_spec2 +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-13-22:V4H-LPDDR5-DDR-HW-DD-13 +* @param[in] f_ddr_mbps DDR transmission frequency +* @param[in] f_ddr_mbpsdiv Division DDR transmission frequency +* @param[out] f_js2 Table to store optimized setting value +* @details +* -# Calculate and assign each setting value of jecec_spec2 by "r_f_scale" func with the following arguments.\n +* -# f_ddr_mbps/f_ddr_mbpsdiv/jedec_spec2[JS2_DERATE][i].ps/jedec_spec2[JS2_DERATE][i].cyc\n +* -# Only the following array elements are calculated using different formulas from those described above.\n +* -# JS2_tRRD/JS2_tFAW/JS2_tZQCALns/JS2_tRCpb/JS2_tRCab +*/ +static void r_f_scale_js2(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t *f_js2) +{ + uint32_t i; + + for (i = 0U; i < JS2_TBLCNT; i++) + { + f_js2[i] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, + (uint32_t)jedec_spec2[JS2_DERATE][i].ps, + jedec_spec2[JS2_DERATE][i].cyc); + } + + f_js2[JS2_tZQCALns] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tZQCALns].ps) * 1000U, 0U); + f_js2[JS2_tDQ72DQns] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tDQ72DQns].ps) * 1000U, 0U); + f_js2[JS2_tCAENTns] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tCAENTns].ps) * 1000U, 0U); + f_js2[JS2_tRCpb] = f_js2[JS2_tRAS] + f_js2[JS2_tRPpb]; + f_js2[JS2_tRCab] = f_js2[JS2_tRAS] + f_js2[JS2_tRPab]; + f_js2[JS2_tRFCab] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 1UL * jedec_spec2_tRFC_ab[max_density] * 1000U, 0U); + + f_js2[JS2_tRBTP] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 7500U, 2U) - 2U; + f_js2[JS2_tXSR] = f_js2[JS2_tRFCab] + r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 7500U, 2U); + f_js2[JS2_tPDN] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 10000U, 0U) + 1U; + f_js2[JS2_tPDN_DSM] = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tPDN_DSM].ps) * 10U, 0U); + f_js2[JS2_tXSR_DSM] = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tXSR_DSM].ps) * 10U, 0U); + f_js2[JS2_tXDSM_XP] = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tXDSM_XP].ps) * 10U, 0U); + f_js2[JS2_tWLWCKOFF] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 14000U, 5U); + +} + +//! @details Array of addresses for setting PI_DARRAY3_0 in each CS and frequency-set +static const uint32_t PI_DARRAY3_0_CSx_Fx[CS_CNT][3] = +{ + { + PI_DARRAY3_0_CS0_F0, + PI_DARRAY3_0_CS0_F1, + PI_DARRAY3_0_CS0_F2 + }, + { + PI_DARRAY3_0_CS1_F0, + PI_DARRAY3_0_CS1_F1, + PI_DARRAY3_0_CS1_F2 + } +}; + +//! @details Array of addresses for setting PI_DARRAY3_1 in each CS and frequency-set +static const uint32_t PI_DARRAY3_1_CSx_Fx[CS_CNT][3] = +{ + { + PI_DARRAY3_1_CS0_F0, + PI_DARRAY3_1_CS0_F1, + PI_DARRAY3_1_CS0_F2 + }, + { + PI_DARRAY3_1_CS1_F0, + PI_DARRAY3_1_CS1_F1, + PI_DARRAY3_1_CS1_F2 + } +}; + +/** +* Load table data into DDR registers +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-08:V4H-LPDDR5-DDR-HW-DD-04-01 +* V4H-LPDDR5-DDR-SW-UD-08:V4H-LPDDR5-DDR-HW-DD-10-01-02 +* @details Execute the following processes in order.\n +* -# Determine Jedec_spec1 configuration table based on ddr_mbps and ddr_mbpsdiv.\n +* -# Calculate the value of the Jedec_Spec2 configuration table from ddr_mbps and ddr_mbpsdiv.\n +* -# Copy the configuration table described in init_dram_tbl_v4h_lp5.h to a local array.\n +* -# Change PI register table settings to match ddr_mbps and ddr_mbpsdiv.\n +* -# Set PHY_SET_DFI_INPUT_RST_PAD to High only if WARM_BOOT.\n +* -# If the set value vref_r is not 0, change the "Read Vref (SoC side) Training range" setting\n +* in the configuration table.\n +* -# If the set value vref_w is not 0, change the "Write Vref (MR14, MR15) Training range" setting\n +* in the configuration table.\n +* -# If the set value vref_ca is not 0, change the "CA Vref (MR12) Training range" setting\n +* in the configuration table.\n +* -# If ddr_mbps/ddr_mbpsdiv is less than 5120, change the contents of the PHY register setting table.\n +* -# If ddr_mbps/ddr_mbpsdiv is less than 4576, change the contents of the PHY register setting table.\n +* -# Reflect the contents of the configuration table in the register.\n +*/ +static void r_ddrtbl_load(void) +{ + uint32_t i; + uint32_t slice; + uint32_t cs; + uint32_t adr; + uint32_t dataL; + uint32_t tmp[2]; + + const uint32_t DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_V4H; + const uint32_t DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_V4H; + const uint32_t DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_V4H; + const uint32_t DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_V4H; + + const uint32_t DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_V4H; + + const uint32_t DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_V4H; + const uint32_t DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_V4H; + const uint32_t DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_V4H; + const uint32_t DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_V4H; + + /*********************************************************************** + * TIMING REGISTERS + ***********************************************************************/ + /* search jedec_spec1 index */ + for (i = JS1_USABLEC_SPEC_LO; i < (JS1_FREQ_TBL_NUM - 1U); i++) + { + if ((js1[i].fx3 * 2U * ddr_mbpsdiv) >= (ddr_mbps * 3U)) + { + break; + } + } + + if (JS1_USABLEC_SPEC_HI < i) + { + js1_ind = JS1_USABLEC_SPEC_HI; + } + else + { + js1_ind = i; + } + + RL = js1[js1_ind].RLset1; + + WL = js1[js1_ind].WLsetA; + + /* calculate jedec_spec2 */ + r_f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); + + /*********************************************************************** + * PREPARE TBL + ***********************************************************************/ + r_tbl_copy(DDR_PHY_SLICE_REGSET, + DDR_PHY_SLICE_REGSET_V4H, DDR_PHY_SLICE_REGSET_NUM_V4H); + r_tbl_copy(DDR_PHY_ADR_V_REGSET, + DDR_PHY_ADR_V_REGSET_V4H, DDR_PHY_ADR_V_REGSET_NUM_V4H); + r_tbl_copy(DDR_PHY_ADR_G_REGSET, + DDR_PHY_ADR_G_REGSET_V4H, DDR_PHY_ADR_G_REGSET_NUM_V4H); + r_tbl_copy(DDR_PI_REGSET, + DDR_PI_REGSET_V4H, DDR_PI_REGSET_NUM_V4H); + + /*********************************************************************** + * Adjust PI paramters + ***********************************************************************/ + + dataL = 10000U * ddr_mbps / ddr_mbpsdiv / 8U / 256U; + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_CAL_INTERVAL_COUNT_0, dataL); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_F2, WL); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_WR_ADJ_F2, (js1[js1_ind].WCKENLW * 4U) + 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_RD_ADJ_F2, (js1[js1_ind].WCKENLR * 4U) + 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_STATIC_F2, (js1[js1_ind].WCKPRESTA * 4U)); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_TOGGLE_RD_F2, (js1[js1_ind].WCKPRETGLR) * 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CASLAT_F2, RL); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_FS_ADJ_F2, (js1[js1_ind].WCKENLF * 4U) + 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRFC_F2, js2[JS2_tRFCab]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLVL_WCKOFF_F2, (js2[JS2_tWLWCKOFF]) + 3U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_ADJ_F2, (WL * 4U) + 2U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCAENT_F2, js2[JS2_tCAENTns]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVREF_LONG_F2, (js2[JS2_tCAENTns]) + 1U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVREF_SHORT_F2, (js2[JS2_tCAENTns]) + 1U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRCD_F2, js2[JS2_tRCD]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRP_F2, js2[JS2_tRPab]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRTP_F2, js1[js1_ind].nRBTP); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MIN_F2, js2[JS2_tRAS]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRD_F2, (js2[JS2_tMRD]) + 1U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TSR_F2, js2[JS2_tSR]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQCAL_F2, js2[JS2_tZQCALns]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQLAT_F2, js2[JS2_tZQLAT]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQ72DQ_F2, js2[JS2_tDQ72DQns]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MC_TRFC_F2, js2[JS2_tRFCab]); + + if (ddr_mbps < (3201U * ddr_mbpsdiv)) + { + /* 2751-3200 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x10U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x07U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x0BU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x07U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x25U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x012DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x0BU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x04U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_GATE_SLAVE_DELAY, 0x05U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x03U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x57U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x613U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F0, 0x2BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x2BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x2BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x22U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x1DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x43U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x51U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x29U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_STROBE_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x64U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x12U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x10U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_TWCKENL_RD_ADJ_F2, 0x10U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_RDLAT_ADJ_F2, 0x1EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x0EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQSCK_MAX_F2, 0x01U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x0C26U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x797CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x9BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0014U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x04U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000064U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x000320U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x00000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000029U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x000051U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x000003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_30_F2, 0x00002BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRDCM_LVL_EN_F1, 0x00U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRDCM_LVL_EN_F2, 0x00U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DRAMDCA_LVL_EN_F1, 0x00U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DRAMDCA_LVL_EN_F2, 0x00U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x013880U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x013880U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x0C3500U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000014U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x000320U); + } + else if (ddr_mbps < (3734U * ddr_mbpsdiv)) + { + /* 3201-3733 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x13U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x0AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x0DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x2AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x0149U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x0DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x04U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_GATE_SLAVE_DELAY, 0x9CU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x04U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x5BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x717U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F0, 0x2CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x2CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x2CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x24U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x1FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x45U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x5FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x30U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_STROBE_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x75U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x13U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x12U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_TWCKENL_RD_ADJ_F2, 0x10U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_RDLAT_ADJ_F2, 0x20U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x10U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x0E2EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x8DCCU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0xB5U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0018U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000075U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x0003A6U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000030U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x00005FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x000005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_30_F2, 0x00002DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x016C90U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x016C90U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x0E3D98U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000018U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x0003A6U); + } + else if (ddr_mbps < (4268U * ddr_mbpsdiv)) + { + /* 3734-4267 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x16U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x09U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x0BU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x0EU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x2EU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x0164U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x0EU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x05U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_GATE_SLAVE_DELAY, 0x30U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x04U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x64U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x81CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F0, 0x2DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x2DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x2DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x2BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x20U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x46U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x6CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x37U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x86U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x14U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x13U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_TWCKENL_RD_ADJ_F2, 0x14U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_RDLAT_ADJ_F2, 0x27U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x13U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x1038U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0xA230U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0xCFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x001BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000086U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x00042BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000037U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x00006CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x000006U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_30_F2, 0x000032U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x01A0ABU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x01A0ABU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x1046ABU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x00001BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x00042BU); + } + else if (ddr_mbps < (4801U * ddr_mbpsdiv)) + { + /* 4269-4800 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x18U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x0AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x0DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x10U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x31U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x017FU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x10U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x05U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_GATE_SLAVE_DELAY, 0xC6U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x05U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x68U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x2DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x920U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F0, 0x2EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x2EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x2EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x21U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x47U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x3DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x79U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x14U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x96U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x15U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_TWCKENL_RD_ADJ_F2, 0x18U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_RDLAT_ADJ_F2, 0x29U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x15U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x1240U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0xB680U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x0E9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x001EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000096U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000008U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x0004B0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000015U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x00003DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x000079U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x000008U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_30_F2, 0x000034U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x01D4A9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x01D4A9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x124E91U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x00001EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x0004B0U); + } + else if (ddr_mbps < (5501U * ddr_mbpsdiv)) + { + /* 4801 - 5500 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x1CU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x0CU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x10U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x13U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x37U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x01A3U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x13U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x06U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_GATE_SLAVE_DELAY, 0x8FU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x06U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x71U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x32U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0xA79U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F0, 0x30U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x30U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x30U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x23U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x49U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x46U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x8BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x15U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0xADU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x17U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_TWCKENL_RD_ADJ_F2, 0x1CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_RDLAT_ADJ_F2, 0x2EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x18U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x14F2U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0xD174U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x10BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x0000ADU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x000561U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000019U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000046U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x00008BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x00000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_30_F2, 0x000038U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x0219AFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x0219AFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x1500CFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x000561U); + } + else if (ddr_mbps < (6001U * ddr_mbpsdiv)) + { + /* 5501 - 6000 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x1FU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x12U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x15U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x3AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x01BDU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x15U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x07U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_GATE_SLAVE_DELAY, 0x1BU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x06U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x75U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x34U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0xB6BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F0, 0x31U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x31U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x31U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x4DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x98U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0xBCU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_TWCKENL_RD_ADJ_F2, 0x1CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MBIST_RDLAT_ADJ_F2, 0x30U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x1AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x16D6U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0xE45CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x123U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x0000BCU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x0005DDU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x00001BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x00004DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x000098U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_30_F2, 0x00003AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x024A16U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x024A16U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x16E4D8U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x0005DDU); + } + else + { + ; /* Nothing */ + } /* (ddr_mbps < (3201U * ddr_mbpsdiv) */ + + tmp[0] = js1[js1_ind].MR1; + tmp[1] = js1[js1_ind].MR2; + + for (cs = 0U; cs < CS_CNT; cs++) + { + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CSx_Fx[cs][2], tmp[0]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CSx_Fx[cs][2], tmp[1]); + } + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) + { + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_SET_DFI_INPUT_RST_PAD, 0x01U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_PWRUP_SREFRESH_EXIT, 0x01U); + } +#endif /* DDR_BACKUPMODE */ + + /*********************************************************************** + * Read Vref (SoC side) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->bdcfg_vref_r); + if (dataL != 0x0U) + { + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_START_POINT, dataL & 0x000000FFU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_STOP_POINT, (dataL & 0x0000FF00U) >> 8); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_STEPSIZE, (dataL & 0x00FF0000U) >> 16); + } + + /*********************************************************************** + * Write Vref (MR14, MR15) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->bdcfg_vref_w); + if (dataL != 0x0U) + { + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F0, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F1, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F2, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0, (dataL & 0xFF00U) >> 8); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, (dataL & 0xFF00U) >> 8); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2, (dataL & 0xFF00U) >> 8); + } + + /*********************************************************************** + * CA Vref (MR12) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->bdcfg_vref_ca); + if (dataL != 0x0U) + { + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_START_POINT_F0, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_START_POINT_F1, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_START_POINT_F2, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_STOP_POINT_F0, (dataL & 0xFF00U) >> 8); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_STOP_POINT_F1, (dataL & 0xFF00U) >> 8); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_STOP_POINT_F2, (dataL & 0xFF00U) >> 8); + } + + /*********************************************************************** + * Low Freq setting + ***********************************************************************/ + if (ddr_mbps < (8U * 640U * ddr_mbpsdiv)) + { + /* CAL_CLK(10-20MHz) */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_DATA_DC_CAL_CLK_SEL, 0x05U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_CLK_DC_CAL_CLK_SEL, 0x04U); + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_CAL_CLK_SELECT_0, 0x05U); + } + + if (ddr_mbps < (8U * 572U * ddr_mbpsdiv)) + { + /* CAL_CLK(10-20MHz) */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_PCLK_CLK_SEL, 0x03U); + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x02U); + } + + if (ddr_mbps < (8U * 401U * ddr_mbpsdiv)) + { + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PLL_CTRL, 0x1542U); + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PLL_CTRL_8X, 0x3342U); + } + + /*********************************************************************** + * SET DATA SLICE TABLE + ***********************************************************************/ + for (slice = 0U; slice < SLICE_CNT; slice++) + { + adr = DDR_PHY_SLICE_REGSET_OFS + (DDR_PHY_SLICE_REGSET_SIZE * slice); + for (i = 0U; i < DDR_PHY_SLICE_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PHY_SLICE_REGSET[i]); + } + } + + /*********************************************************************** + * SET ADR SLICE TABLE + ***********************************************************************/ + adr = DDR_PHY_ADR_V_REGSET_OFS; + for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PHY_ADR_V_REGSET[i]); + } + + /*********************************************************************** + * SET ADRCTRL SLICE TABLE + ***********************************************************************/ + adr = DDR_PHY_ADR_G_REGSET_OFS; + for (i = 0U; i < DDR_PHY_ADR_G_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PHY_ADR_G_REGSET[i]); + } + + /*********************************************************************** + * SET PI REGISTERS + ***********************************************************************/ + adr = DDR_PI_REGSET_OFS; + for (i = 0U; i < DDR_PI_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PI_REGSET[i]); + } +} + +/** +* CONFIGURE DDR REGISTERS +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-09:V4H-LPDDR5-DDR-HW-DD-10-01-03 +* @details +* -# Set up wiring for DQ and DM pins and VREF_DRIVING.\n +* -# Set the CA pin wiring and ADR_CALVL_SWIZZLE settings.\n +* -# Make wiring settings for the CS pin.\n +* -# When memory rank is 1, set RANK setting to 1 to disable CS training.\n +* -# Configure the DATA_BYTE_SWAP setting.\n +*/ +static void r_ddr_config(void) +{ + uint32_t ch, slice; + uint32_t dataL; + uint8_t high_byte[SLICE_CNT]; + + r_foreach_vch((ch)) + { + /*********************************************************************** + * BOARD SETTINGS (DQ, DM, VREF_DRIVING) + ***********************************************************************/ + for (slice = 0U; slice < SLICE_CNT; slice++) + { + high_byte[slice] = ((uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap) >> (4U * slice)) % 2U; + r_ddr_setval_s(ch, slice, PHY_DQ_DM_SWIZZLE0, Boardcnf->ch[ch].bdcfg_dq_swap[slice]); + r_ddr_setval_s(ch, slice, PHY_DQ_DM_SWIZZLE1, (uint32_t)(Boardcnf->ch[ch].bdcfg_dm_swap[slice])); + if (high_byte[slice] != 0U) + { + /* HIGHER 16 BYTE */ + r_ddr_setval_s(ch, slice, PHY_CALVL_VREF_DRIVING_SLICE, 0x00U); + } + else + { + /* LOWER 16 BYTE */ + r_ddr_setval_s(ch, slice, PHY_CALVL_VREF_DRIVING_SLICE, 0x01U); + } + } + dataL = (0x000000FFU & (uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap)); + r_ddr_setval(ch, PHY_DATA_BYTE_ORDER_SEL, (0x76543200U | dataL)); + + /*********************************************************************** + * BOARD SETTINGS (CA, ADDR_MUX) + ***********************************************************************/ + dataL = (0x0FFFFFFFU & (uint32_t)(Boardcnf->ch[ch].bdcfg_ca_swap)); + + /* --- ADDR_MUX --- */ + r_ddr_setval(ch, PI_ADDR_MUX_0, (0x000000FU & dataL)); + r_ddr_setval(ch, PI_ADDR_MUX_1, (0x000000FU & (dataL >> 4))); + r_ddr_setval(ch, PI_ADDR_MUX_2, (0x000000FU & (dataL >> 8))); + r_ddr_setval(ch, PI_ADDR_MUX_3, (0x000000FU & (dataL >> 12))); + r_ddr_setval(ch, PI_ADDR_MUX_4, (0x000000FU & (dataL >> 16))); + r_ddr_setval(ch, PI_ADDR_MUX_5, (0x000000FU & (dataL >> 20))); + r_ddr_setval(ch, PI_ADDR_MUX_6, (0x000000FU & (dataL >> 24))); + + /* --- ADR_CALVL_SWIZZLE --- */ + r_ddr_setval(ch, PHY_ADR_CALVL_SWIZZLE0, dataL); + + /*********************************************************************** + * BOARD SETTINGS (CS) + ***********************************************************************/ + /* --- CKE_MUX --- */ + /* SoC CKE -> DRAM CS */ + dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_cs_swap); + r_ddr_setval(ch, PI_CKE_MUX_0, ((0x0FU & dataL) + 2U)); + r_ddr_setval(ch, PI_CKE_MUX_1, ((0x0FU & (dataL >> 4)) + 2U)); + r_ddr_setval(ch, PHY_CS_ACS_ALLOCATION_BIT2_2, ((0x0FU & (dataL)) + 1U)); + r_ddr_setval(ch, PHY_CS_ACS_ALLOCATION_BIT3_2, ((0x0FU & (dataL >> 4)) + 1U)); + + /*********************************************************************** + * mask CS_MAP if RANK1 is not found + ***********************************************************************/ + if ((ch_have_this_cs[1] & (1U << ch)) == 0x0U) + { + r_ddr_setval(ch, PHY_ADR_CALVL_RANK_CTRL, 0x00U); + for (slice = 0U; slice < SLICE_CNT; slice++) + { + r_ddr_setval_s(ch, slice, PHY_PER_CS_TRAINING_EN, 0x00U); + } + } + } + + r_foreach_vch((ch)) + { + /* --- DATA_BYTE_SWAP --- */ + dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap); + r_ddr_setval(ch, PI_DATA_BYTE_SWAP_EN, 0x01U); + r_ddr_setval(ch, PI_DATA_BYTE_SWAP_SLICE0, dataL & 0x0FU); + r_ddr_setval(ch, PI_DATA_BYTE_SWAP_SLICE1, (dataL >> 4) & 0x0FU); + + if ((ch_have_this_cs[1] & (1U << ch)) == 0x0U) + { + r_ddr_setval(ch, PI_CS_MAP, 0x01U); + } + } +} + +/** +* DBSC register setting functions +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-03:V4H-LPDDR5-DDR-HW-DD-10-04-02 +* @details +* -# Set SDRAM type, Burst length, and PHY type.\n +* -# Frequency mode setting.\n +* -# Write SDRAM configuration contents to registers.\n +*/ +static void r_dbsc_regset_pre(void) +{ + uint32_t ch, cs; + + /*********************************************************************** + * PRIMARY SETTINGS + ***********************************************************************/ + /* LPDDR5, BL=16, DFI interface */ + r_dbsc_write_32(DBSC_DBMEMKIND, 0x0000000CU); + r_dbsc_write_32(DBSC_DBMEMKINDA, 0x0000000CU); + r_dbsc_write_32(DBSC_DBBL, 0x00000002U); + r_dbsc_write_32(DBSC_DBBLA, 0x00000002U); + r_dbsc_write_32(DBSC_DBPHYCONF0, 0x00000001U); + + r_dbsc_write_32(DBSC_DBSYSCONF0, 0x00000001U); + + /* FREQRATIO=2 */ + r_dbsc_write_32(DBSC_DBSYSCONF1, 0x00020000U); + r_dbsc_write_32(DBSC_DBSYSCONF1A, 0x00000000U); + + r_dbsc_write_32(DBSC_DBSYSCONF2, 0x00000001U); + r_dbsc_write_32(DBSC_DBSYSCONF2A, 0x00000241U); + + r_foreach_ech((ch)) + { + for (cs = 0U; cs < CS_CNT; cs++) + { + if (ddr_density[ch][cs] == 0xFFU) + { + mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00U); + mmio_write_32(DBSC_DBMEMCONFA(ch, cs), 0x00U); + } + else + { + mmio_write_32(DBSC_DBMEMCONF(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs])); + mmio_write_32(DBSC_DBMEMCONFA(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs])); + } + } + } +} + +/** +* Set DBSC timing parameters. +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-04:V4H-LPDDR5-DDR-HW-DD-10-04-03 +* @details +* -# Set the timing registers of the DBSC.\n +* -# Configure Scheduler settings.\n +*/ +static void r_dbsc_regset(void) +{ + uint32_t tmp[4]; + + /* DBTR0.CL : RL */ + r_dbsc_write_32(DBSC_DBTR(0U), RL); + + /* DBTR1.CWL : WL */ + r_dbsc_write_32(DBSC_DBTR(1U), WL); + + /* DBTR2.AL = 0 */ + r_dbsc_write_32(DBSC_DBTR(2U), 0x00000000U); + + /* DBTR3.TRCD: tRCD */ + r_dbsc_write_32(DBSC_DBTR(3U), js2[JS2_tRCD]); + + /* DBTR4.TRPA,TRP: tRPab,tRPpb */ + r_dbsc_write_32(DBSC_DBTR(4U), ((js2[JS2_tRPab] << 16) | js2[JS2_tRPpb])); + + /* DBTR5.TRC : tRCpb */ + r_dbsc_write_32(DBSC_DBTR(5U), js2[JS2_tRCpb]); + + /* DBTR6.TRAS : tRAS */ + r_dbsc_write_32(DBSC_DBTR(6U), js2[JS2_tRAS]); + + /* DBTR7.TRRD : tRRD */ + r_dbsc_write_32(DBSC_DBTR(7U), ((js2[JS2_tRRD] - 1U) << 16) | (js2[JS2_tRRD] - 1U)); + + /* DBTR8.TFAW : tFAW */ + r_dbsc_write_32(DBSC_DBTR(8U), (js2[JS2_tFAW] - 1U)); + + /* DBTR9.TRDPR: nRBTP */ + r_dbsc_write_32(DBSC_DBTR(9U), (js1[js1_ind].nRBTP)); + + /* DBTR10.TWR : nWR */ + r_dbsc_write_32(DBSC_DBTR(10U), js1[js1_ind].nWR); + + /* DBTR11.TRDWR : RL + BL/n_max + RU(tWCK2DQO(max)/tCK) + RD(tRPST/tCK) - ODTLon - RD(tODTon(min)/tCK) + 1 + feature */ + r_dbsc_write_32(DBSC_DBTR(11U), (RL + 4U + js2[JS2_tWCK2DQO_HF] + 0U - js1[js1_ind].ODTLon - (js2[JS2_tODTon_min] - 1U) + 1U + 0U)); + + /* DBTR12.TWRRD_S : WL + BL/2 + tWTR_S, TWRRD_L : WL + BL + tWTR_L */ + r_dbsc_write_32(DBSC_DBTR(12U), (((WL + 2U + js2[JS2_tWTR_S]) << 16) | (WL + 4U + js2[JS2_tWTR_L]))); + + /* DBTR13.TRFCAB : tRFCab */ + r_dbsc_write_32(DBSC_DBTR(13U), (js2[JS2_tRFCab])); + + /* DBTR14.TCSCAL,TCKEHDLL,tCKEH : tCSCAL,tXP,tXP */ + r_dbsc_write_32(DBSC_DBTR(14U), ((js2[JS2_tCSCAL] << 24) | (js2[JS2_tXP] << 16) | js2[JS2_tXP])); + + /* DBTR15.TESPD,TCKESR,TCKEL : tESPD = 2,tSR,tSR */ + r_dbsc_write_32(DBSC_DBTR(15U), ((0x02U << 24) | (js2[JS2_tSR] << 16) | js2[JS2_tSR])); + + /* DBTR16 */ + /* wdql(tphy_wrlat + tphy_wrdata) */ + tmp[0] = (WL * 4U) - 1U + 5U; + /* dqenltcy(tphy_wrlat) */ + tmp[1] = (WL * 4U) - 2U - 2U + 5U; + /* dql(tphy_rdlat + trddata_en) RL * 4 + phy_rptr_update + phy_rddqs_latency_adjust + 39 */ + tmp[2] = (RL * 4U) + r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE) + r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST) + 39U; + /* dqienltncy(trddata_en) RL * 4 - phy_rddata_en_dly_X + 4 * phy_wck_freq_ratio_X */ + tmp[3] = (RL * 4U) + 4U - r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY); + r_dbsc_write_32(DBSC_DBTR(16U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR17.TMODRD,TMOD: tMRR,tMRW */ + r_dbsc_write_32(DBSC_DBTR(17U), ((js2[JS2_tMRR] << 24) | (js2[JS2_tMRW] << 16))); + + /* DBTR18. RODTL, RODTA = 0 */ + r_dbsc_write_32(DBSC_DBTR(18U), 0x00000000U); + + /* DBTR19. TZQCL, TZQCS = 0 */ + r_dbsc_write_32(DBSC_DBTR(19U), 0x00000000U); + + /* DBTR20.TXSDLL, TXS : tXSR,tXSR */ + r_dbsc_write_32(DBSC_DBTR(20U), ((js2[JS2_tXSR]) << 16) | (js2[JS2_tXSR])); + + /* DBTR21.TCCD */ + r_dbsc_write_32(DBSC_DBTR(21U), ((ddr_tccd << 16) | (ddr_tccd * 2U))); + + /* DBTR22.TZQCAL,TZQLAT : tZQCAL,tZQLAT */ + r_dbsc_write_32(DBSC_DBTR(22U), ((js2[JS2_tZQCALns] << 16) | js2[JS2_tZQLAT])); + + /* DBTR23. RRSPC = 0 */ + r_dbsc_write_32(DBSC_DBTR(23U), 0x00000000U); + + /* DBTR24 */ + /* WRCSLAT(tphy_wrcslat) */ + tmp[0] = (WL * 4U) - 2U; + /* WRCSGAP(tphy_wrcsgap) */ + tmp[1] = 0x0CU; + /* RDCSLAT(tphy_rdcslat) */ + tmp[2] = RL * 4U; + /* RDCSGAP(tphy_rdcsgap) */ + tmp[3] = 0x0CU; + r_dbsc_write_32(DBSC_DBTR(24U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR25. TWDQLVLDIS = 0 */ + r_dbsc_write_32(DBSC_DBTR(25U), 0x00000000U); + + /* DBTR26. TWCK2DQOOSC,TDQSOSC : WCK2DQI interval timer run time, WCK2DQO interval timer run time */ + r_dbsc_write_32(DBSC_DBTR(26U), 0x00000000U); + + /* DBTR27.TPDN : tPDN */ + r_dbsc_write_32(DBSC_DBTR(27U), js2[JS2_tPDN]); + + /* DBTR28.txsrdsm : tXSR_DSM */ + r_dbsc_write_32(DBSC_DBTR(28U), js2[JS2_tXSR_DSM]); + + /* DBTR29.tdsmxp : tXDSM_XP */ + r_dbsc_write_32(DBSC_DBTR(29U), js2[JS2_tXDSM_XP]); + + /* DBTR30.TCMDPD : tCMDPD = 3 */ + r_dbsc_write_32(DBSC_DBTR(30U), 0x00000003U); + + /* DBTR31.TWCK2DQOMAX,TWCK2DQIMAX : tWCK2DQI/O_HF/LF */ + r_dbsc_write_32(DBSC_DBTR(31U), ((js2[JS2_tWCK2DQO_HF] << 4) | js2[JS2_tWCK2DQI_HF])); + + /* DBTR32 */ + /* twckenr */ + tmp[0] = (js1[js1_ind].WCKENLR * 4U) + 4U - 1U; + /* twckenw */ + tmp[1] = (js1[js1_ind].WCKENLW * 4U) + 4U - 1U; + /* twckenlf */ + tmp[2] = (js1[js1_ind].WCKENLF * 4U) + 4U; + /* twckpresta */ + tmp[3] = js1[js1_ind].WCKPRESTA * 4U; + r_dbsc_write_32(DBSC_DBTR(32U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR33 */ + /* TWCKTGL */ + tmp[0] = 4U; + /* TWCKDIS (RL+ bl/n_max) * 4 + RU(tWCKPST/tWCK) : tWCKPST = 2.5(MR10[3:2]) */ + tmp[1] = ((RL + 4U) * 4U) + 3U; + r_dbsc_write_32(DBSC_DBTR(33U), ((tmp[1] << 8) | tmp[0])); + + /* DBTR34 */ + /* TWCKSUS = 4 */ + tmp[0] = 4U; + /* TWCKPST RU(tWCKPST/tCK) : tWCKPST=2.5(MR10[3:2]) */ + tmp[1] = 1U; + r_dbsc_write_32(DBSC_DBTR(34U), ((tmp[1] << 8) | tmp[0])); + + /* DBTR35 */ + /* TRD2WCKOFF RL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[0] = RL + 4U + 0U +1U; + /* TWR2WCKOFF WL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[1] = WL + 4U + 0U +1U; + r_dbsc_write_32(DBSC_DBTR(35U), ((tmp[1] << 16) | tmp[0])); + + /* DBTR36 */ + /* TWSSUSWRX : CAS(WCKSUS)WRX */ + tmp[0] = 3U; + /* TWSOFFWRX : CAS(WS_OFF)WRX */ + tmp[1] = 3U; + /* TWSFSWRX : CAS(WS_FS)WRX */ + tmp[2] = 2U; + r_dbsc_write_32(DBSC_DBTR(36U), ((tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR37 */ + /* tOSCO */ + r_dbsc_write_32(DBSC_DBTR(37U), js2[JS2_tOSCODQI]); + + /* DBRNK2 */ + /* RNKRR = 12 */ + r_dbsc_write_32(DBSC_DBRNK(2U), 0x000000CCU); + + /* DBRNK3 */ + /* RNKRW = 6 */ + r_dbsc_write_32(DBSC_DBRNK(3U), 0x00000066U); + + /* DBRNK4 */ + /* RNKWR = 6 */ + r_dbsc_write_32(DBSC_DBRNK(4U), 0x00000066U); + + /* DBRNK5 */ + /* RNKWW = 14 */ + r_dbsc_write_32(DBSC_DBRNK(5U), 0x000000EEU); + + /*********************************************************************** + * timing registers for Scheduler + ***********************************************************************/ + /* SCFCTST0 */ + /* SCPREACT */ + tmp[0] = 1UL * js2[JS2_tRPpb] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* SCACTRDWR */ + tmp[1] = 1UL * (WL + 2U + 1U + js1[js1_ind].nWR + js2[JS2_tRPpb]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* SCRDACRT */ + tmp[2] = 1UL * ((js1[js1_ind].nRBTP + 2U) + js2[JS2_tRPpb]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* SCACTACT */ + tmp[3] = 1UL * js2[JS2_tRCpb] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + r_dbsc_write_32(DBSC_DBSCHFCTST0, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* SCFCTST1 */ + /* SCASYNCOFS */ + tmp[0] = 12; + /* SCACTRDWR */ + tmp[1] = 1UL * js2[JS2_tRCD] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* SCWRRD */ + tmp[2] = 1UL * (mmio_read_32(DBSC_DBTR(12U)) & 0xFFU) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* SCRDWR */ + tmp[3] = 1UL * (mmio_read_32(DBSC_DBTR(11U)) & 0xFFU) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + r_dbsc_write_32(DBSC_DBSCHFCTST1, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBSCHRW1 */ + /* SCTRFCAB */ + tmp[0] = 1UL * (js2[JS2_tRFCab] + js2[JS2_tZQLAT]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + r_dbsc_write_32(DBSC_DBSCHRW1, tmp[0]); + + /* DBSCHTR0 */ + /* SCDT0 */ + tmp[0] = (1UL * 4U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + /* SCDT1 */ + tmp[1] = (1UL * 8U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + /* SCDT2 */ + tmp[2] = (1UL * 12U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + /* SCDT3 */ + tmp[3] = (1UL * 16U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + r_dbsc_write_32(DBSC_DBSCHTR0, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /*********************************************************************** + * QOS and CAM + ***********************************************************************/ + r_dbsc_write_32(DBSC_DBBCAMDIS, 0x00000001U); +} + +/** +* DBSC Register Setting +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-05:V4H-LPDDR5-DDR-HW-DD-01-05 +* V4H-LPDDR5-DDR-SW-UD-05:V4H-LPDDR5-DDR-HW-DD-02-01 +* V4H-LPDDR5-DDR-SW-UD-05:V4H-LPDDR5-DDR-HW-DD-04-02 +* V4H-LPDDR5-DDR-SW-UD-05:V4H-LPDDR5-DDR-HW-DD-10-04-04 +* @details Execute following flow. +* -# If memory rank is 2, CS_TRAINING_EN is set to the other side.\n +* -# Configure DBI read/write settings.\n +* -# Execute DRAM refresh settings.\n +* -# Set WTmode of DFI PHY to OFF.\n +* -# Set up PHY Periodic Write DQ training.\n +* -# Set WTmode of DFI PHY to ON.\n +* -# Calibration settings for PHY PAD.\n +* -# Set SDRAM calibration.\n +* -# Make DFI Control Update Setting settings..\n +* -# In the case of WARM_BOOT, cancel the self-refresh setting.\n +* -# Enable SDRAM auto refresh.\n +* -# Set up PHY Periodic Write DQ training.\n +* -# Enable access to SDRAM.\n +*/ +static void r_dbsc_regset_post(void) +{ + uint32_t ch, slice; + uint32_t dataL; + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + uint32_t ctrl_clk; + uint32_t clk_count; + uint32_t phymster_req_interval; +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + + if (Prr_Cut < PRR_PRODUCT_30) + { + if (ch_have_this_cs[1] != 0x0U) + { + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + r_ddr_setval_s(ch, slice, PHY_PER_CS_TRAINING_EN, 0x00U); + } + } + } + } + + r_dbsc_write_32(DBSC_DBDBICNT, 0x00000003U); + + /* set REFCYCLE */ + dataL = DBSC_REFINT * ddr_mbps / 8000U / ddr_mbpsdiv; + /* refpmax=8 */ + r_dbsc_write_32(DBSC_DBRFCNF1, 0x00080000U | (dataL & 0x0000FFFFU)); + /* refpmin=1 */ + r_dbsc_write_32(DBSC_DBRFCNF2, 0x00010000U | DBSC_REFINTS); + + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000U); +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + +#if (RCAR_PERIODIC_WRITE_TRAINING != 0U) + /* Periodic-WriteDQ Training setting */ + r_ddr_setval_ach(PI_WDQLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_WDQLVL_VREF_EN, 0x00U); + r_ddr_setval_ach_as(PHY_DATA_DC_WDQLVL_ENABLE, 0x00U); + r_ddr_setval_ach(PI_WDQLVL_PERIODIC, 0x01U); +#endif /* (RCAR_PERIODIC_WRITE_TRAINING != 0U) */ + +#if (RCAR_PERIODIC_READ_TRAINING != 0U) + /* Periodic-ReadDQ Training setting */ + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F2, 0x00U); + r_ddr_setval_ach_as(PHY_RDLVL_DLY_STEP, 0x04U); + r_ddr_setval_ach(PI_RDLVL_PERIODIC, 0x01U); +#endif /* (RCAR_PERIODIC_READ_TRAINING != 0) */ + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + /* DFI_PHYMSTR_ACK , WTmode = b'01 */ + r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011U); +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + + /* periodic SoC zqcal enable */ + r_ddr_setval_ach(PHY_CAL_MODE_0, r_ddrtbl_getval(DDR_PHY_ADR_G_REGSET, PHY_CAL_MODE_0) | 0x02U); + + /* periodic dram zqcal enable */ + r_dbsc_write_32(DBSC_DBCALCNF, 0x01000010U); + + /* periodic phy ctrl update enable */ + r_dbsc_write_32(DBSC_DBDFICUPDCNF, 0x504C0001U); + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) + { + /* SRX */ + r_send_dbcmd2(0x0A840001U); + } +#endif /* DDR_BACKUPMODE */ + /* set Auto Refresh */ + r_dbsc_write_32(DBSC_DBRFEN, 0x00000001U); + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + /* Periodic-WriteDQ/ReadDQ Training Interval setting */ + phymster_req_interval = PERIODIC_TRAINING_INTERVAL - 3000U; + clk_count = 1024U - (r_ddrtbl_getval_pi(DDR_PI_REGSET, PI_LONG_COUNT_MASK) * 32U); + ctrl_clk = ddr_mbps / ddr_mbpsdiv / 8U; + dataL = phymster_req_interval * ctrl_clk / clk_count; +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + +#if (RCAR_PERIODIC_WRITE_TRAINING != 0U) + r_ddr_setval_ach(PI_WDQLVL_INTERVAL, dataL); +#endif /* RCAR_PERIODIC_WRITE_TRAINING */ + +#if ((RCAR_PERIODIC_READ_TRAINING != 0U) && (RCAR_PERIODIC_TRAINING_SEPARATE_MODE == 0U)) + r_ddr_setval_ach(PI_RDLVL_INTERVAL, dataL); +#endif /* ((RCAR_PERIODIC_READ_TRAINING != 0U) && (RCAR_PERIODIC_TRAINING_SEPARATE_MODE == 0U)) */ + + /* dram access enable */ + r_dbsc_write_32(DBSC_DBACEN, 0x00000001U); + + MSG_LF("dbsc_regset_post(done)\n"); +} + +/** +* training by PI +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-02:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Enable WCK signal training and read gate training.\n +* -# Start PI training.\n +* -# After DFI initialization for all channels is once turned off, turned on all chennels of it.\n +* -# Power down the DRAM device once and then release the power down mode.\n +* -# Perform training in low frequency mode and training in high frequency mode.\n +* -# Wait for the DFI training completion status bit to stand until the time limit.\n +* -# Turn off DFI initialization for all channels.\n +* -# Turn off WTMODE of DFI PHY.\n +* -# Check if CA/CS Training has failed.\n +* -# Checking if Wrlvl training is in error.\n +* -# If an error can be confirmed from the check result, the result is returned as a return value.\n +* -# Clear the status register for PI training.\n +*/ +static uint32_t r_pi_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + uint32_t frqchg_req; + uint32_t flag; + + uint32_t complete_ng; + uint32_t ca_training_ng; + uint32_t wr_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + /*********************************************************************** + * init start + ***********************************************************************/ + + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WRDCM_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WDQLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_DFS_INITIALIZATION_SEQ_9, 0x00000000U); + r_ddr_setval_ach(PI_DFS_INITIALIZATION_SEQ_10, 0x00000000U); + + /* PI_START */ + r_ddr_setval_ach(PI_START, 0x01U); + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) + { + r_ddr_setval_ach(PI_DLL_RST, 0x01U); + r_ddr_setval_ach(PI_PWRUP_SREFRESH_EXIT, 0x00U); + } +#endif /* DDR_BACKUPMODE */ + + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000020U); + } + + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000021U); + } + + /* Dummy PDE */ + r_send_dbcmd2(0x08840000U); + + /* PDX */ + r_send_dbcmd2(0x08840001U); + + /*********************************************************************** + * wait init_complete + ***********************************************************************/ + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + frqchg_req = 0U; + for (ch = 0U; ch < DRAM_CH_CNT; ch++) + { + if ((((~phytrainingok) & ddr_phyvalid) & (1U << ch)) != 0x0U) + { + if ((mmio_read_32(DBSC_DBPDSTAT0(ch)) & 0x01U) != 0x0U) + { + frqchg_req = 1U; + break; + } + } + } + + if (frqchg_req != 0x0U) + { + flag = r_pll3_freq(); + if (flag != 0x0U) + { + break; + } + } + else + { + r_foreach_vch((ch)) + { + dataL = mmio_read_32(DBSC_DBDFISTAT(ch)); + if ((dataL & 0x00000001U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + }/* (frqchg_req != 0x0U) */ + } + + /* dbdficnt0: + * dfi_dram_clk_disable=0 + * dfi_frequency = 0 + * freq_ratio = 10 (4:1) + * init_start =0 + */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000020U); + } + + /* DFI_PHYMSTR_ACK */ + r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001U); + + complete_ng = 0x0U; + ca_training_ng = 0x0U; + wr_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* CA/CS Training Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 4 )); /* PI_CALVL_ERROR_BIT */ + dataL |= (r_ddr_getval(ch, PHY_ADR_CALVL_OBS1) & (0x3U << 30 )); /* error on decrement/increment pass */ + dataL |= (r_ddr_getval(ch, PHY_ADR_CALVL_OBS2) & (0x3U << 24 )); /* start outside of initial search range */ + dataL |= (r_ddr_getval(ch, PHY_CSLVL_OBS1) & (0xFU << 28 )); /* CSlvl error */ + if (dataL != 0x0U) + { + ca_training_ng |= 1U << ch; + MSG_LF("pi_training_error:1\n"); + } + + /* Wrlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3 )); /* PI_WRLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12 )); /* SLICE0 wrlvl error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12 )); /* SLICE1 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS); /* SLICE0 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS); /* SLICE1 wrlvl error */ + if (dataL != 0x0U) + { + wr_training_ng |= 1U << ch; + MSG_LF("pi_training_error:2\n"); + } + } + + complete_ng = (wr_training_ng | ca_training_ng); + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x07U); + } + + return phytrainingok; +} + +/** +* Write Leveling Cycle Adjust +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-05:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Get delay value from the result write leveling of slice 0.\n +* -# Calculate latency of dfi_wrdata_en / dfi_wrdata / dfi_wrdata_mask signals based on delay values.\n +* -# Get delay value from the result write leveling of slice 1.\n +* -# Calculate latency of dfi_wrdata_en / dfi_wrdata / dfi_wrdata_mask signals based on delay values.\n +*/ +static void r_write_leveling_adjust(void) +{ + uint32_t ch; + uint32_t result_hard0; + uint32_t result_hard1; + uint32_t avg; + uint32_t avg_frac; + uint32_t avg_cycle; + + r_foreach_vch((ch)) + { + /* SLICE0 */ + result_hard0 = r_ddr_getval_s(ch, 0U, PHY_WRLVL_HARD0_DELAY_OBS); + result_hard1 = r_ddr_getval_s(ch, 0U, PHY_WRLVL_HARD1_DELAY_OBS); + + if (result_hard0 <= result_hard1) + { + avg = (result_hard0 + result_hard1) / 2U; + } + else + { + avg = (result_hard0 + result_hard1 + 0x400U) / 2U; + } + avg_frac = avg & 0xFFU; + avg_cycle = (avg >> 8) & 0x3U; + + if (avg_cycle == 0x3U) + { + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_DEC, 0x1U); + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_ADD, 0x0U); + } + else + { + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_DEC, 0x0U); + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_ADD, avg_cycle); + } + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_FRAC, avg_frac); + + /* SLICE1 */ + result_hard0 = r_ddr_getval_s(ch, 1U, PHY_WRLVL_HARD0_DELAY_OBS); + result_hard1 = r_ddr_getval_s(ch, 1U, PHY_WRLVL_HARD1_DELAY_OBS); + + if (result_hard0 <= result_hard1) + { + avg = (result_hard0 + result_hard1) / 2U; + } + else + { + avg = (result_hard0 + result_hard1 + 0x400U) / 2U; + } + avg_frac = avg & 0xFFU; + avg_cycle = (avg >> 8) & 0x3U; + + if (avg_cycle == 0x3U) + { + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_DEC, 0x1U); + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_ADD, 0x0U); + } + else + { + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_DEC, 0x0U); + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_ADD, avg_cycle); + } + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_FRAC, avg_frac); + } + + r_ddr_setval_ach_as(SC_PHY_WCK_CALC, 0x01U); + +} + +/** +* Re-run Write Leveling & Read Gate Training +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-06:V4H-LPDDR5-DDR-HW-FD-10-0 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Set CA leveling OFF, read gate leveling ON, write gate leveling ON, PI dram wck training ON.\n +* -# Perform PI_DFS configuration.\n +* -# Start PI frequency training in manual mode.\n +* -# Perform training in high-frequency mode.\n +* -# Check for Write leveling Error and Gate leveling Error.\n +* -# If an error is identified, the resulting value is inverted and returned.\n +* -# Clear the PI status register.\n +*/ +static uint32_t r_wl_gt_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + + uint32_t complete_ng; + uint32_t wr_training_ng; + uint32_t gt_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + r_ddr_setval_ach(PI_CALVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x01U); + + r_ddr_setval_ach(PI_DFS_ENTRY_SEQ_0, 0x181F0000U); + r_ddr_setval_ach(PI_DFS_INITIALIZATION_SEQ_1, 0x00000000U); + r_ddr_setval_ach(PI_TRAIN_ALL_FREQ_REQ, 0x01U); + + /* Freq Change High to High*/ + dataL = r_pll3_freq(); + if (dataL != 0x0U) + { + return (1); + } + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if ((dataL & 0x1U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + wr_training_ng = 0x0U; + gt_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Wrlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3 )); /* PI_WRLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12 )); /* SLICE0 wrlvl error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12 )); /* SLICE1 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS); /* SLICE0 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS); /* SLICE1 wrlvl error */ + if (dataL != 0x0U) + { + wr_training_ng |= 1U << ch; + MSG_LF("wl_gt_training_error:1\n"); + } + /* Gtlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 2 )); /* PI_RDLVL_GATE_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7 )); /* SLICE0 delay setup error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7 )); /* SLICE1 delay setup error */ + if (dataL != 0x0U) + { + gt_training_ng |= 1U << ch; + MSG_LF("wl_gt_training_error:2\n"); + } + } + + complete_ng = (wr_training_ng | gt_training_ng); + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x07U); + } + + return phytrainingok; +} + +/** +* Write DCA Training +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-07:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Get DCA Training CS0 Flip-0 training results for RANK0.\n +* -# Get DCA Training CS1 Flip-0 training results for RANK0.\n +* -# Calculate DRAMDCA settings from training results and write them to registers.\n +* -# Set DRAM DCA in MR30.\n +* -# Ensure that the training has been successfully completed..\n +* -# Clear CA status to 0.\n +*/ +static void r_write_dca(void) +{ + uint32_t ch; + uint32_t dataL; + uint32_t phytrainingok; + uint32_t retry; + const uint32_t RETRY_MAX = 0x10000U; + + r_ddr_setval_ach_as(PHY_DATA_DC_CAL_START, 0x01U); + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = (r_ddr_getval_s(ch, 0U, PHY_DATA_DC_CAL_START)) | (r_ddr_getval_s(ch, 1U, PHY_DATA_DC_CAL_START)); + if (dataL == 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } +} + +/** +* DRAM DCA Training and Calculations +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-07:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Get DCA Training CS0 Flip-0 training results for RANK0.\n +* -# Get DCA Training CS1 Flip-0 training results for RANK0.\n +* -# Calculate DRAMDCA settings from training results and write them to registers.\n +* -# Set DRAM DCA in MR30.\n +* -# Ensure that the training has been successfully completed..\n +* -# Clear CA status to 0.\n +*/ +static uint32_t r_dramdca_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t dataL; + uint32_t rank; + uint32_t dca_result_l_0[DRAM_CH_CNT][CS_CNT]; /* DCA_result_lower_flip0_[ch][cs] */ + uint32_t dca_result_u_0[DRAM_CH_CNT][CS_CNT]; /* DCA_result_upper_flip0_[ch][cs] */ + uint32_t dca_result_l_1[DRAM_CH_CNT][CS_CNT]; /* DCA_result_lower_flip1_[ch][cs] */ + uint32_t dca_result_u_1[DRAM_CH_CNT][CS_CNT]; /* DCA_result_upper_flip1_[ch][cs] */ + uint32_t tempu; + uint32_t templ; + + const uint32_t mr30_conv[16] = + { + 0x08U, 0x07U, 0x06U, 0x05U, 0x04U, 0x03U, 0x02U, 0x01U, + 0x00U, 0x09U, 0x0AU, 0x0BU, 0x0CU, 0x0DU, 0x0EU, 0x0FU + }; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + /*********************************************************************** + * Run DRAM DCA Training for Flip-0 + ***********************************************************************/ + r_ddr_setval_ach(PI_DCMLVL_CS_SW, rank); + + /* DRAMDCA go */ + r_ddr_setval_ach(PI_DRAMDCA_LVL_REQ, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = r_pi_int_ack_0_assert(28U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + /* result for DRAMDCA flip-0 */ + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS0_F2); + dca_result_u_0[ch][0] = mr30_conv[dataL >> 4]; + dca_result_l_0[ch][0] = mr30_conv[dataL & 0x0FU]; + if ((rank & 0x02U) != 0x0U) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS1_F2); + dca_result_u_0[ch][1] = mr30_conv[dataL >> 4]; + dca_result_l_0[ch][1] = mr30_conv[dataL & 0x0FU]; + } + } + + /*********************************************************************** + * Run DRAM DCA Training for Flip-1 + ***********************************************************************/ + r_ddr_setval_ach(PI_DRAMDCA_FLIP_MASK, 0x01U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_ACTIVE_SEQ_2, 0x00000000U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_ACTIVE_SEQ_3, 0x00000000U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_ACTIVE_SEQ_4, 0x00000000U); + + /* DRAMDCA go */ + r_ddr_setval_ach(PI_DRAMDCA_LVL_REQ, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = r_pi_int_ack_0_assert(28U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + /* result for DRAMDCA flip-1 */ + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS0_F2); + dca_result_u_1[ch][0] = mr30_conv[dataL >> 4]; + dca_result_l_1[ch][0] = mr30_conv[dataL & 0x0FU]; + if ((rank & 0x02U) != 0x0U) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS1_F2); + dca_result_u_1[ch][1] = mr30_conv[dataL >> 4]; + dca_result_l_1[ch][1] = mr30_conv[dataL & 0x0FU]; + } + } + + /*********************************************************************** + * Calculate and set DRAMDCA value + ***********************************************************************/ + r_foreach_vch((ch)) + { + /* CS0 */ + tempu = (dca_result_u_0[ch][0] + dca_result_u_1[ch][0]) / 2U; + templ = (dca_result_l_0[ch][0] + dca_result_l_1[ch][0]) / 2U; + dataL = (mr30_conv[tempu] << 4) | (mr30_conv[templ]); + r_ddr_setval(ch, PI_DARRAY3_20_CS0_F2, dataL); + if ((rank & 0x02U) != 0x0U) + { + /* CS1 */ + tempu = (dca_result_u_0[ch][1] + dca_result_u_1[ch][1]) / 2U; + templ = (dca_result_l_0[ch][1] + dca_result_l_1[ch][1]) / 2U; + dataL = (mr30_conv[tempu] << 4) | (mr30_conv[templ]); + r_ddr_setval(ch, PI_DARRAY3_20_CS1_F2, dataL); + } + } + + /* set DRAMDCA value in MR30 */ + r_ddr_setval_ach(PI_SW_SEQ_0, 0x01A11E14U); + r_ddr_setval_ach(PI_SW_SEQ_1, 0x001F0000U); + r_ddr_setval_ach(PI_SEQ_DEC_SW_CS, rank); + r_ddr_setval_ach(PI_SW_SEQ_START, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = r_pi_int_ack_0_assert(19U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + r_ddr_setval_ach(PI_SEQ_DEC_SW_CS, 0x00U); + r_ddr_setval_ach(PI_DRAMDCA_FLIP_MASK, 0x02U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_ACTIVE_SEQ_2, 0x001101FCU); + r_ddr_setval_ach(PI_DRAMDCA_LVL_ACTIVE_SEQ_3, 0x00211A00U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_ACTIVE_SEQ_4, 0x00051500U); + + return phytrainingok; +} + +/** +* Re-run Write Leveling +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-09:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# CALVL training is set to OFF, WRDCM training is set to OFF, and DRAMDCA training is set to OFF.\n +* -# Set the memory rank for the Write leveling target and start leveling.\n +* -# Wait until leveling is complete.\n +* -# Check for Write leveling errors.\n +* -# If an error is confirmed to have occurred, the result is returned as a return value.\n +* -# Clear the PI status bit.\n +*/ +static uint32_t r_write_leveling(void) +{ + uint32_t ch; + uint32_t rank; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + uint32_t complete_ng; + uint32_t wr_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + r_ddr_setval_ach(PI_CALVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WRDCM_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WRLVL_CS_SW, rank); + r_ddr_setval_ach(PI_WRLVL_REQ, 0x01U); + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = ((r_ddr_getval(ch, PI_INT_STATUS)) >> 29); + if ((dataL & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + wr_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Wrlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3 )); /* PI_WRLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12 )); /* SLICE0 wrlvl error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12 )); /* SLICE1 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS); /* SLICE0 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS); /* SLICE1 wrlvl error */ + if (dataL != 0x0U) + { + wr_training_ng |= 1U << ch; + MSG_LF("write_leveling_error:1\n"); + } + } + + complete_ng = wr_training_ng; + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x07U); + } + + return phytrainingok; +} + +/** +* Manual Write DCA Training +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-xx:V4H-LPDDR5-DDR-HW-FD-xx +* @details Execute following processes.\n +* -# Execute following processes.\n +* -# Write DCA training according to memory rank.\n +*/ +static void r_manual_write_dca(void) +{ + uint32_t ch; + uint32_t slice; + uint32_t rank; + uint32_t cs; + uint32_t i; + uint32_t phy_slv_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; + uint32_t phy_slv_dly_avg[DRAM_CH_CNT][SLICE_CNT]; + uint32_t slv_dly_min[DRAM_CH_CNT][SLICE_CNT]; + uint32_t slv_dly_max[DRAM_CH_CNT][SLICE_CNT]; + uint32_t phy_dcc_code_min[DRAM_CH_CNT][SLICE_CNT]; + uint32_t phy_dcc_code_max[DRAM_CH_CNT][SLICE_CNT]; + uint32_t phy_dcc_code_mid; + uint32_t tmp; + uint32_t complete; + uint32_t retry; + const uint32_t RETRY_MAX = 0x10000U; + + const uint8_t ratio_min = 0x06U; + const uint8_t ratio_max = 0x03U; + const uint8_t ratio_min_div = 0x0AU; + const uint8_t ratio_max_div = 0x02U; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x02U; + } + else + { + rank = 0x01U; + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + phy_dcc_code_min[ch][slice] = 0x7FU; + phy_dcc_code_max[ch][slice] = 0x00U; + } + } + + for (cs = 0U; cs < rank; cs++) + { + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_INDEX, cs); + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + phy_slv_dly[ch][cs][slice] = r_ddr_getval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY); + } + } + }/* for (cs = 0U; cs < rank; cs++ */ + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if (rank == 0x02U) + { + /* Calculate average between ranks */ + phy_slv_dly_avg[ch][slice] = (phy_slv_dly[ch][0][slice] + phy_slv_dly[ch][1][slice]) / 2U; + } + else + { + phy_slv_dly_avg[ch][slice] = phy_slv_dly[ch][0][slice]; + } + /* Determine the search range */ + slv_dly_min[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07FU) * ratio_min / ratio_min_div; + slv_dly_max[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07FU) * ratio_max / ratio_max_div; + if (slv_dly_max[ch][slice] > 0x7FU) + { + slv_dly_max[ch][slice] = 0x7FU; + } + } + } + + complete = 0x00U; + + r_ddr_setval_ach_as(PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x01U); + + for (i = 0U; i <= 0x7FU; i++) + { + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if (slv_dly_max[ch][slice] < (slv_dly_min[ch][slice] + i)) + { + complete |= ((0x01U << ch) << (8U * slice)); + } + else + { + /* CS0/1 same setting, Need masked write */ + r_ddr_setval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY, (slv_dly_min[ch][slice] + i)); + r_ddr_setval_s(ch, slice, SC_PHY_WCK_CALC, 0x01U); + r_ddr_setval(ch, SC_PHY_MANUAL_UPDATE, 0x01U); + } + } + } + + if (complete == (ddr_phyvalid | (ddr_phyvalid << 8))) + { + break; + } + + /* Exec write dca */ + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if ((((complete >> (8U * slice)) >> ch) & 0x01U) != 0x01U) + { + r_ddr_setval_s(ch, slice, PHY_DATA_DC_CAL_START, 0x01U); + } + } + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if ((((complete >> (8U * slice)) >> ch) & 0x01U) != 0x01U) + { + retry = 0U; + while (retry++ < RETRY_MAX) + { + tmp = r_ddr_getval_s(ch, slice,PHY_DATA_DC_CAL_START); + if (tmp == 0x00U) + { + break; + } + } + } + } + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if ((slv_dly_min[ch][slice] + i) <= slv_dly_max[ch][slice]) + { + tmp = (r_ddr_getval_s(ch, slice, PHY_DATA_DC_DQS_CLK_ADJUST)); + if ((tmp >> 6) == 0x01U) + { + tmp = 0x00U; + } + else if ((tmp >> 6) == 0x02U) + { + tmp = 0x3FU; + } + else + { + ; /* nop */ + } + + if (tmp < phy_dcc_code_min[ch][slice]) + { + phy_dcc_code_min[ch][slice] = tmp; + } + + if (phy_dcc_code_max[ch][slice] < tmp) + { + phy_dcc_code_max[ch][slice] = tmp; + } + } + } + } + }/* for (i = 0U; i <= 0x7FU; i++) */ + + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U); + for (cs = 0U; cs < rank; cs++) + { + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_INDEX, cs); + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + r_ddr_setval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY, phy_slv_dly[ch][cs][slice]); + r_ddr_setval_s(ch, slice, SC_PHY_WCK_CALC, 0x01U); + r_ddr_setval(ch, SC_PHY_MANUAL_UPDATE, 0x01U); + } + } + } + + r_ddr_setval_ach_as(PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x00U); + + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01U); + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + phy_dcc_code_mid = (phy_dcc_code_min[ch][slice] + phy_dcc_code_max[ch][slice]) / 2U; + r_ddr_setval_s(ch, slice, PHY_DATA_DC_DQS_CLK_ADJUST, phy_dcc_code_mid); + } + } +} + +/** +* Re-run read gate training by pi +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-11:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Write leveling set to OFF, read gate leveling set to ON.\n +* -# Set memory rank for leveling target, turn on read gate leveling.\n +* -# Waiting for leveling to be completed until the time limit.\n +* -# Check for errors during gate leveling.\n +* -# If an error is confirmed to have occurred, the result is returned as a return value.\n +* -# Clear the PI status register.\n +*/ +static uint32_t r_read_gate_training(void) +{ + uint32_t ch; + uint32_t rank; + uint32_t dataL; + uint32_t phytrainingok; + uint32_t retry; + uint32_t complete_ng; + uint32_t gt_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + r_ddr_setval_ach(PI_WRLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x01U); + r_ddr_setval_ach(PI_RDLVL_CS_SW, rank); + r_ddr_setval_ach(PI_RDLVL_GATE_REQ, 0x01U); + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = ((r_ddr_getval(ch, PI_INT_STATUS)) >> 24); + if ((dataL & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + gt_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Gtlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 2 )); /* PI_RDLVL_GATE_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7 )); /* SLICE0 delay setup error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7 )); /* SLICE1 delay setup error */ + if (dataL != 0x0U) + { + gt_training_ng |= 1U << ch; + MSG_LF("read_gate_training_error\n"); + } + } + + complete_ng = gt_training_ng; + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x07U); + } + + return phytrainingok; +} + +/** +* Read Data Training with VREF Training +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-12:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Set reading leveling to ON and Vref leveling of reading to OFF.\n +* -# Set Vref reading training to OFF.\n +* -# Get start value, end value and number of steps for Vref training.\n +* -# Determine the optimal VREFSEL value while increasing the Vref training setpoint by the starting value+step value.\n +*/ +static uint32_t r_read_vref_training(void) +{ + uint32_t ch; + uint32_t phytrainingok = 0U; + uint32_t retry; + uint32_t dataL; + uint32_t rank; + uint32_t curr_rank; + uint32_t vref_start, vref_stop, vref_step; + uint32_t vref_stop_index; + uint32_t dvw_min_byte0[DRAM_CH_CNT], dvw_min_byte1[DRAM_CH_CNT]; + uint32_t obs_sel; + uint32_t win_byte0, win_byte1; + uint32_t best_vref_byte0, best_vref_byte1; + uint32_t best_vref_byte0_index = 0U; + uint32_t best_vref_byte1_index = 0U; + uint32_t best_dvw_min_byte0, best_dvw_min_byte1; + uint32_t best_thrshld; + uint32_t vref_outlier; + uint32_t best_lower_vref, best_upper_vref; + uint32_t outlier_cnt; + uint32_t tempLE, tempTE; + uint32_t dvw_min_byte0_table[DRAM_CH_CNT][128]; + uint32_t dvw_min_byte1_table[DRAM_CH_CNT][128]; + int32_t i; + + for (ch = 0U; ch < DRAM_CH_CNT; ch++) + { + dvw_min_byte0[ch] = 0x0U; + dvw_min_byte1[ch] = 0x0U; + } + + const uint32_t RETRY_MAX = 0x10000U; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x02U; + } + else + { + rank = 0x01U; + } + + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F0, 0x00U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F1, 0x00U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F2, 0x00U); + r_ddr_setval_ach_as(PHY_VREF_TRAINING_CTRL, 0x00U); + + /* ch0 vref_point */ + vref_start = r_ddr_getval(0U, PHY_VREF_INITIAL_START_POINT); + vref_stop = r_ddr_getval(0U, PHY_VREF_INITIAL_STOP_POINT); + vref_step = r_ddr_getval(0U, PHY_VREF_INITIAL_STEPSIZE); + vref_stop_index = (vref_stop - vref_start) / vref_step; + + if (vref_stop_index > 0x80U) + { + return phytrainingok; + } + + for (i = 0; i <= vref_stop_index; i++) + { + r_foreach_vch((ch)) + { + dataL = (r_ddr_getval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | (vref_start + (vref_step * i)))); + dataL = (r_ddr_getval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | (vref_start + (vref_step * i)))); + } + + for (curr_rank = 0U; curr_rank < rank; curr_rank++) + { + /* All ch Read Training Start */ + r_ddr_setval_ach(PI_RDLVL_CS_SW, (1U << curr_rank)); + r_ddr_setval_ach(PI_RDLVL_REQ, 0x01U); + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if (((dataL >> 25) & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + /* Read Training End */ + r_ddr_setval_ach(PI_INT_ACK_0, (0x1U << 25)); + + r_foreach_vch((ch)) + { + /* minimum Data Valie Window for each VREF */ + dvw_min_byte0[ch] = 0xFFFFFFFFU; + dvw_min_byte1[ch] = 0xFFFFFFFFU; + for (obs_sel = 0x00U; obs_sel < 0x19U; obs_sel++) + { + if ((obs_sel < 0x11U) || (obs_sel == 0x18U)) + { + r_ddr_setval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_OBS_SELECT, obs_sel); + r_ddr_setval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_OBS_SELECT, obs_sel); + + tempLE = r_ddr_getval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + tempTE = r_ddr_getval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + if (tempTE > tempLE) + { + win_byte0 = tempTE - tempLE; + } + else + { + win_byte0 = 0U; + } + tempLE = r_ddr_getval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + tempTE = r_ddr_getval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + if (tempTE > tempLE) + { + win_byte1 = tempTE - tempLE; + } + else + { + win_byte1 = 0U; + } + + if (dvw_min_byte0[ch] > win_byte0) + { + dvw_min_byte0[ch] = win_byte0; + } + if (dvw_min_byte1[ch] > win_byte1) + { + dvw_min_byte1[ch] = win_byte1; + } + } + } + } + }/* For all memory rank */ + r_foreach_vch((ch)) + { + dvw_min_byte0_table[ch][i] = dvw_min_byte0[ch]; + dvw_min_byte1_table[ch][i] = dvw_min_byte1[ch]; + } + }/* For all vref_stop_index steps */ + + r_foreach_vch((ch)) + { + /* Search best VREF byte0 */ + best_vref_byte0 = vref_start; + best_vref_byte0_index = 0U; + best_dvw_min_byte0 = dvw_min_byte0_table[ch][0U]; + for (i = 0U; i <= vref_stop_index; i++) + { + if (best_dvw_min_byte0 < dvw_min_byte0_table[ch][i]) + { + best_vref_byte0 = vref_start + (vref_step * i); + best_vref_byte0_index = i; + best_dvw_min_byte0 = dvw_min_byte0_table[ch][i]; + } + } + + /* Search best_lower VREF byte0 */ + dataL = r_ddr_getval_s(ch, 0U, PHY_RDLVL_DLY_STEP); + if (dataL == 0U) + { + best_thrshld = r_ddr_getval_s(ch, 0U, PHY_RDLVL_BEST_THRSHLD); + } + else + { + best_thrshld = r_ddr_getval_s(ch, 0U, PHY_RDLVL_BEST_THRSHLD) * dataL; + } + vref_outlier = r_ddr_getval_s(ch, 0U, PHY_RDLVL_VREF_OUTLIER); + best_lower_vref = best_vref_byte0; + outlier_cnt = vref_outlier; + for (i = best_vref_byte0_index; i >= 0; i--) + { + if (dvw_min_byte0_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) + { + best_lower_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + if (i == 0) + { + break; + } + } + + /* Search best_upper VREF byte0 */ + vref_outlier = r_ddr_getval_s(ch, 0U, PHY_RDLVL_VREF_OUTLIER); + best_upper_vref = best_vref_byte0; + outlier_cnt = vref_outlier; + for (i = best_vref_byte0_index; i <= vref_stop_index; i++) + { + if (dvw_min_byte0_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) + { + best_upper_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + } + + /* Calculate center of best vref range byte0 */ + best_vref_byte0 = (best_lower_vref + best_upper_vref) / 2U; + + /* Search best VREF byte1 */ + best_vref_byte1 = vref_start; + best_vref_byte1_index = 0U; + best_dvw_min_byte1 = dvw_min_byte1_table[ch][0U]; + for (i = 0U; i <= vref_stop_index; i++) + { + if (best_dvw_min_byte1 < dvw_min_byte1_table[ch][i]) + { + best_vref_byte1 = vref_start + (vref_step * i); + best_vref_byte1_index = i; + best_dvw_min_byte1 = dvw_min_byte1_table[ch][i]; + } + } + + /* Search best_lower VREF byte1 */ + dataL = r_ddr_getval_s(ch, 1U, PHY_RDLVL_DLY_STEP); + if (dataL == 0U) + { + best_thrshld = r_ddr_getval_s(ch, 1U, PHY_RDLVL_BEST_THRSHLD); + } + else + { + best_thrshld = r_ddr_getval_s(ch, 1U, PHY_RDLVL_BEST_THRSHLD) * dataL; + } + + vref_outlier = r_ddr_getval_s(ch, 1U, PHY_RDLVL_VREF_OUTLIER); + best_lower_vref = best_vref_byte1; + outlier_cnt = vref_outlier; + for (i = best_vref_byte1_index; i >= 0; i--) + { + if (dvw_min_byte1_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) + { + best_lower_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + if (i == 0) + { + break; + } + } + + /* Search best_upper VREF byte1 */ + vref_outlier = r_ddr_getval_s(ch, 1U, PHY_RDLVL_VREF_OUTLIER); + best_upper_vref = best_vref_byte1; + outlier_cnt = vref_outlier; + for (i = best_vref_byte1_index; i <= vref_stop_index; i++) + { + if (dvw_min_byte1_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) + { + best_upper_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + } + + /* Calculate center of best vref range byte1 */ + best_vref_byte1 = (best_lower_vref + best_upper_vref) / 2U; + + dataL = (r_ddr_getval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | best_vref_byte0)); + dataL = (r_ddr_getval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | best_vref_byte1)); + } + + return phytrainingok; +} + +/** +* Read Data & RDDQ Training with best VREF & Write DQ VREF Training +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-13:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Set read DQS/RDQS slave delay setting to 0.\n +* -# Write leveling set to OFF, read gate leveling set to OFF.\n +* -# Turn on read and write leveling.\n +* -# Start frequency training.\n +* -# Training in high-frequency mode.\n +* -# Wait until training is complete.\n +* -# Check for errors in write dq leveling and read leveling.\n +* -# If an error is confirmed to have occurred, return the inverted result value.\n +* -# Clear the PI status register.\n +*/ +static uint32_t r_read_write_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + uint32_t complete_ng; + uint32_t rd_training_ng; + uint32_t wdq_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + /* RDDQ_SLAVE_DELAY Set 0x0050 -> 0x0000 */ + r_ddr_setval_ach_as(PHY_RDDQ0_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ1_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ2_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ3_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ4_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ5_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ6_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ7_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDM_SLAVE_DELAY, 0x0000U); + + r_ddr_setval_ach(PI_WRLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_WDQLVL_EN_F2, 0x03U); + + r_ddr_setval_ach(PI_TRAIN_ALL_FREQ_REQ, 0x01U); + + /* Freq Change High to High*/ + dataL = r_pll3_freq(); + if (dataL != 0x0U) + { + return (1); + } + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if ((dataL & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + rd_training_ng = 0x0U; + wdq_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Rdlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 1 )); /* PI_RDLVL_ERROR_BIT */ + if (dataL != 0x0U) + { + rd_training_ng |= 1U << ch; + MSG_LF("read_write_training_error:1\n"); + } + + /* Wdqlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 5 )); /* PI_WDQLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18 )); /* SLICE0 wdqlvl_fail_dqZ */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18 )); /* SLICE1 wdqlvl_fail_dqZ */ + if (dataL != 0x0U) + { + wdq_training_ng |= 1U << ch; + MSG_LF("read_write_training_error:2\n"); + } + } + + complete_ng = (wdq_training_ng | rd_training_ng); + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x07U); + } + + return phytrainingok; +} + +/** +* Correct RDDQ Training result & Re-Run Read Data Training +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-15:V4H-LPDDR5-DDR-HW-FD-10-03 +* @details Execute following processes.\n +* -# Set the Read DQ correction value and its upper limit from the board settings\n +* -# Check DDR memory ranks.\n +* -# Add the offset value to the current Read DQ value and write it to the register.\n +* -# Write the setting value to PI_RDLVL_TRAIN_SEQ_x.\n +* -# Start the Read training.\n +* -# PI_INT_ACK assert.\n +* -# Execute the Rdlvl Err Check.\n +* -# Confirmation that training has been successfully completed.\n +* -# Return the result of the confirmation as the return value.\n +*/ +static uint32_t r_read_training(void) +{ + uint32_t ch; + uint32_t slice; + uint32_t rank; + uint32_t i; + uint32_t phytrainingok; + uint32_t dataL; + uint32_t complete_ng; + uint32_t rd_training_ng; + uint32_t rddq_delay_offset; + uint32_t rddq_delay_max; + + const uint32_t rddq_delay_addr[9] = + { + PHY_RDDQ0_SLAVE_DELAY, PHY_RDDQ1_SLAVE_DELAY, PHY_RDDQ2_SLAVE_DELAY, + PHY_RDDQ3_SLAVE_DELAY, PHY_RDDQ4_SLAVE_DELAY, PHY_RDDQ5_SLAVE_DELAY, + PHY_RDDQ6_SLAVE_DELAY, PHY_RDDQ7_SLAVE_DELAY, PHY_RDDM_SLAVE_DELAY + }; + + const uint32_t rddq_delay_offset_ps = 0x19U; + const uint32_t rddq_delay_max_ps = 0x67U; + + rddq_delay_offset = rddq_delay_offset_ps * ddr_mbps * 256U / (ddr_mbpsdiv * 2U * 1000000U); + rddq_delay_max = rddq_delay_max_ps * ddr_mbps * 256U / (ddr_mbpsdiv * 2U * 1000000U); + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + for (i = 0U; i < 9U; i++) + { + dataL = r_ddr_getval_s(ch, slice, rddq_delay_addr[i]) + rddq_delay_offset; + if (dataL > rddq_delay_max) + { + dataL = rddq_delay_max; + } + r_ddr_setval_s(ch, slice, rddq_delay_addr[i], dataL); + } + } + } + + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_1, 0x00089080U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_2, 0x000811C0U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_3, 0x040811C0U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_4, 0x02000000U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_5, 0x00000000U); + r_ddr_setval_ach(PI_RDLVL_CS_SW, rank); + + /* Read training go */ + r_ddr_setval_ach(PI_RDLVL_REQ, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = 0x0U; + phytrainingok = r_pi_int_ack_0_assert(25U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + complete_ng = 0x0U; + rd_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Rdlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 1)); /* PI_RDLVL_ERROR_BIT */ + if (dataL != 0x0U) + { + rd_training_ng |= 1U << ch; + MSG_LF("read_training_error\n"); + } + } + + complete_ng = rd_training_ng; + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + return phytrainingok; +} + +/** +* DDR mode register setting +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-06:V4H-LPDDR5-DDR-HW-FD-10-05 +* @details Execute following processes.\n +* -# Set the mode register 28 of the SDRAM.\n +*/ +static void r_ddr_register_set(void) +{ + /* MR28 ZQ Mode: Command-Based ZQ Calibration, ZQ interval: Background Cal Interval < 64ms */ + r_send_dbcmd2(0x0E841C24U); +} + +/** +* DDR mode register read +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-14:V4H-LPDDR5-DDR-HW-FD-02-05 +* @details Execute following processes.\n +* -# Execute following processes.\n +* -# Set the mode register 27 and 57 of the SDRAM.\n +*/ +static void r_ddr_register_read(void) +{ + uint32_t dataL; + + dataL = (uint32_t)(Boardcnf->bdcfg_rfm_chk); + if (dataL != 0x0U) + { + /* MR27 rank0 */ + r_send_dbcmd2(0x0F801B00U); + /* MR57 rank0 */ + r_send_dbcmd2(0x0F803900U); + + if (ch_have_this_cs[1] != 0x0U) + { + /* MR27 rank1 */ + r_send_dbcmd2(0x0F811B00U); + /* MR57 rank1 */ + r_send_dbcmd2(0x0F813900U); + } + } +} + +/** +* Training handshake functions +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-08:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t The result of check that initialize valid channels is completed successfully +* @details Execute following processes.\n +* -# Wait for the status bit specified in the argument to become 1 until the time limit.\n +* -# After checking status bits on all channels, clear the target status bits\n +and returns the result of the check as the return value. +*/ +static uint32_t r_pi_int_ack_0_assert(uint32_t bit) +{ + uint32_t dataL; + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + const uint32_t RETRY_MAX = 0x10000U; + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if (((dataL >> bit) & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, (0x1U << bit)); + } + return phytrainingok; +} + +/** +* Wait for status register update +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-xx:V4H-LPDDR5-DDR-HW-FD-xx +* @details Execute following processes.\n +* -# Read value the DBSC_DBPDSTAT1(ch) register\n +* -# Wait until the contents of the status register are the same as status\n +*/ +static void r_wait_dbpdstat1(uint32_t status) +{ + uint32_t i, ch, dataL; + uint32_t freqchg_req_chk; + + for (i = 0U; i < 2U; i++) + { + do + { + dataL = status; + freqchg_req_chk = 0U; + r_foreach_vch((ch)) + { + dataL &= mmio_read_32(DBSC_DBPDSTAT1(ch)); + freqchg_req_chk |= mmio_read_32(DBSC_DBPDSTAT0(ch)); + } + } while ((dataL != status) && ((freqchg_req_chk & 0x1U) == 0x0U)); + } +} + +/** +* Training handshake functions +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-07-14:V4H-LPDDR5-DDR-HW-FD-10-03 +* @return uint32_t Check to see if time is running out +* @details Execute following processes.\n +* -# Check the value of the argument req_assert.\n +* -# If req_assert is 1, wait until FREQCHGREQ of all channels is 1 before time expires.\n +* -# If req_assert is 0, wait until FREQCHGREQ of all channels is 0 before time expires.\n +* -# Returns the result of whether time has expired or not as a return value.\n +*/ +static uint32_t r_wait_freqchgreq(uint32_t req_assert) +{ + uint32_t dataL; + uint32_t count; + uint32_t ch; + + count = 0xFFFFFFU; + + if (req_assert != 0x0U) + { + do + { + dataL = 1U; + r_foreach_vch((ch)) + { + dataL &= mmio_read_32(DBSC_DBPDSTAT0(ch)); + } + count = count - 1U; + } + while (((dataL & 0x1U) != 0x1U) && (count != 0U)); + } + else + { + do + { + dataL = 0U; + r_foreach_vch((ch)) + { + dataL |= mmio_read_32(DBSC_DBPDSTAT0(ch)); + } + count = count - 1U; + } + while (((dataL & 0x1U) != 0x0U) && (count != 0U)); + }/* (req_assert != 0x0U) */ + + return (count == 0x0U); +} + +/** +* Training handshake functions +* @par TraceID Cover_SW_UD:Cover_HW_DD +* :V4H-LPDDR5-DDR-SW-UD-07-04:V4H-LPDDR5-DDR-HW-FD-10-03 +* @details Execute following processes.\n +* -# Check the value of the argument ackassert..\n +* -# If the value of ackassert is greater than or equal to 0, write 0x0000CF01U to DBSC_DBPDCNT2.\n +* -# If the value of ackassert is 0, write 0x00000000U to DBSC_DBPDCNT2.\n +*/ +static void r_set_freqchgack(uint32_t ack_assert) +{ + uint32_t ch; + uint32_t dataL; + + if (ack_assert != 0x0U) + { + dataL = 0x0000CF01U; + } + else + { + dataL = 0x00000000U; + } + + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDCNT2(ch), dataL); + } +} + +/** +* Set up the pll3 frequency +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-xx:V4H-LPDDR5-DDR-HW-FD-xx +* @details Execute following processes.\n +* -# Wait for frequency change request.\n +* -# DBSC_DBPDSTAT0 value determines whether r_pll3_control is called\n +* in low frequency mode or high frequency mode.\n +* -# Call r_set_freqchgack(1U) function.\n +* -# Check update completion until timeout.\n +* -# Call r_set_freqchgack(0U) function.\n +* -# If timed out, return with error log\n +* -# Wait for status register update\n +*/ +static uint32_t r_pll3_freq(void) +{ + uint32_t timeout; + uint32_t fsel; + + r_wait_freqchgreq(1); + + fsel = (0x0300U & mmio_read_32(DBSC_DBPDSTAT0(0U))) >> 8; + if (fsel == 0U) + { + r_pll3_control(PLL3_LOW_FREQUENCY_MODE); /* Low frequency mode */ + } + else + { + r_pll3_control(PLL3_HIGH_FREQUENCY_MODE); /* High frequency mode */ + } + + r_set_freqchgack(1U); + + timeout = r_wait_freqchgreq(0); + r_set_freqchgack(0U); + + if (timeout != 0x0U) + { + FATAL_MSG("Time out\n"); + return (1); + } + + r_wait_dbpdstat1(0x07U); + + return (0); +} + +/** +* Initialize ddr +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-02:V4H-LPDDR5-DDR-HW-DD-10-02-02 +* @details Execute following processes.\n +* -# Status monitor and perform reset and software reset for DDR.\n +* -# Disable DDRPHY software reset.\n +* -# Unprotect the DDRPHY register.\n +* -# Perform pre-setting of DBSC registers.\n +* -# Configure the ddrphy registers.\n +* -# Process ddr backup.\n +* -# Set DBSC registers.\n +* -# Initialize DFI and perform PI training.\n +* -# Setup DDR mode registers pre-traning.\n +* -# Adjustment of number of write leveling cycles.\n +* -# Perform PI training in manual mode.\n +* -# Perform DRAM DCA training.\n +* -# Perform write leveling.\n +* -# Exec phydca training.\n +* -# Execute read gate training.\n +* -# Perform Vref training on read gate.\n +* -# Read DQ Write DQ Execute.\n +* -# frequency selection change (F1->F2).\n +* -# Disable the FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST.\n +* -# Start setting DDR mode registers.\n +* -# Set DBSC registers after training is completed.\n +* -# Set write protection for PHY registers.\n +*/ +static uint32_t r_init_ddr(void) +{ + uint32_t phytrainingok; + uint32_t ch; + uint32_t err; + + MSG_LF("init_ddr:0\n"); +#ifdef DDR_BACKUPMODE + R_DRAM_Get_Boot_Status(&ddrBackup); +#endif + + /*********************************************************************** + * PLL3 initialization setting + ***********************************************************************/ + /* Reset Status Monitor clear */ + r_cpg_write_32(CPG_FSRCHKCLRR4, 0x00000600U); + /* Reset Status Monitor set */ + r_cpg_write_32(CPG_FSRCHKSETR4, 0x00000600U); + /* ddrphy soft reset assert */ + r_cpg_write_32(CPG_SRCR4, mmio_read_32(CPG_SRCR4) | 0x00000600U); + /* wait reset FB */ + while ((mmio_read_32(CPG_FSRCHKRA4) & 0x00000600U) != 0U) + { + ; /* Nothing */ + } + /* Reset Status Monitor clear */ + r_cpg_write_32(CPG_FSRCHKCLRR4, 0x00000600U); + +#if (RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE == 1U) + r_pll3_control(PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER); /* Initialize PLL3 setting */ +#else + r_pll3_control(PLL3_HIGH_FREQUENCY_MODE); /* Initialize PLL3 setting */ +#endif /* (RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE == 1U) */ + + /* ddrphy soft reset negate */ + r_cpg_write_32(CPG_SRSTCLR4, 0x00000600U); + while ((mmio_read_32(CPG_SRCR4) & 0x00000600U) != 0U) + { + ; /* Nothing */ + } + + /*********************************************************************** + * unlock phy + ***********************************************************************/ + /* Unlock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU); + } + + /*********************************************************************** + * dbsc register pre-setting + ***********************************************************************/ + r_dbsc_regset_pre(); + + /*********************************************************************** + * load ddrphy registers + ***********************************************************************/ + r_ddrtbl_load(); + + /*********************************************************************** + * configure ddrphy registers + ***********************************************************************/ + r_ddr_config(); + + /*********************************************************************** + * ddr backupmode end + ***********************************************************************/ +#ifdef DDR_BACKUPMODE + if (ddrBackup != 0x0U) + { + NOTICE("[WARM_BOOT]\n"); + } + else + { + NOTICE("[COLD_BOOT]\n"); + } + + err = R_DRAM_Update_Boot_Status(ddrBackup); + if (err != 0x0U) + { + NOTICE("[BOOT_STATUS_UPDATE_ERROR]\n"); + return INITDRAM_ERR_I; + } +#endif + MSG_LF("init_ddr:1\n"); + + /*********************************************************************** + * dbsc register set + ***********************************************************************/ + r_dbsc_regset(); + MSG_LF("init_ddr:2\n"); + + /*********************************************************************** + * frequency selection change (F1->F2) + ***********************************************************************/ + r_ddr_setval_ach(PHY_FREQ_SEL_INDEX, 0x01U); + r_ddr_setval_ach(PHY_FREQ_SEL_MULTICAST_EN, 0x00U); + + /*********************************************************************** + * dfi_init_start (start ddrphy) & exec pi_training + ***********************************************************************/ + phytrainingok = r_pi_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:1\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:3\n"); + + /*********************************************************************** + * write leveling cycle adjust + ***********************************************************************/ + r_write_leveling_adjust(); + MSG_LF("init_ddr:4\n"); + + /*********************************************************************** + * exec write leveling & read gate training + ***********************************************************************/ + phytrainingok = r_wl_gt_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:2\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:5\n"); + + /*********************************************************************** + * exec write dca training + ***********************************************************************/ + r_write_dca(); + + MSG_LF("init_ddr:6\n"); + + /*********************************************************************** + * exec dram dca training + ***********************************************************************/ + phytrainingok = r_dramdca_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:3\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:7\n"); + + /*********************************************************************** + * exec write leveling + ***********************************************************************/ + phytrainingok = r_write_leveling(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:4\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:8\n"); + + /*********************************************************************** + * exec manual write dca training + ***********************************************************************/ + r_manual_write_dca(); + + MSG_LF("init_ddr:9\n"); + + /*********************************************************************** + * exec read gate training + ***********************************************************************/ + phytrainingok = r_read_gate_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:5\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:10\n"); + + /*********************************************************************** + * exec read vref training + ***********************************************************************/ + phytrainingok = r_read_vref_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:6\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:11\n"); + + /*********************************************************************** + * exec read dq & write dq training with best vref + ***********************************************************************/ + phytrainingok = r_read_write_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:7\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:12\n"); + + /*********************************************************************** + * correct rddq training result & exec read dq training + ***********************************************************************/ + phytrainingok = r_read_training(); + + if (ddr_phyvalid != phytrainingok) { + MSG_LF("init_ddr_error:8\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:13\n"); + + /*********************************************************************** + * PER_CS_TRAINING_MULTICAST SET (disable) + ***********************************************************************/ + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U); + + MSG_LF("init_ddr:14\n"); + + /*********************************************************************** + * setup DDR mode registers + ***********************************************************************/ + /* MRS */ + r_ddr_register_set(); + + /* MRR */ + r_ddr_register_read(); + + MSG_LF("init_ddr:15\n"); + + /*********************************************************************** + * training complete, setup dbsc + ***********************************************************************/ + r_dbsc_regset_post(); + + MSG_LF("init_ddr:16\n"); + + /*********************************************************************** + * lock phy + ***********************************************************************/ + /* Lock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U); + } + + return phytrainingok; +} + +/** +* DDR Initialize entry +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-01:V4H-LPDDR5-DDR-HW-FD-01-01 +* V4H-LPDDR5-DDR-SW-UD-01:V4H-LPDDR5-DDR-HW-DD-01-04-01 +* V4H-LPDDR5-DDR-SW-UD-01:V4H-LPDDR5-DDR-HW-DD-01-04-02 +* V4H-LPDDR5-DDR-SW-UD-01:V4H-LPDDR5-DDR-HW-DD-01-04-03 +* V4H-LPDDR5-DDR-SW-UD-01:V4H-LPDDR5-DDR-HW-DD-01-03-02 +* V4H-LPDDR5-DDR-SW-UD-01:V4H-LPDDR5-DDR-HW-DD-10-01-01 +* V4H-LPDDR5-DDR-SW-UD-01:V4H-LPDDR5-DDR-HW-DD-10-04-01 +* @details Execute following processes.\n +* -# Remove write protection on DBSC register.\n +* -# Reads the ID and version of the SoC used.\n +* -# Read DDR configuration information from a config file.\n +* -# Calculate board clock frequency and operating frequency from DDR configuration information.\n +* -# Call the main function of DDR initialization.\n +* -# Perform DBSC write protection after initialization is complete.\n +*/ +uint32_t R_DRAM_Init(void) +{ + uint32_t ch, cs; + uint32_t dataL; + uint32_t failcount; + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00001234U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00001234U); + + /*********************************************************************** + * Judge product and cut + ***********************************************************************/ + Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; + + if (Prr_Product != PRR_PRODUCT_V4H) + { + FATAL_MSG("DDR:Unknown Product\n"); + return 0xFFU; + } + else if (Prr_Cut > 0xFFU) + { + FATAL_MSG("DDR:Unknown Product Version\n"); + return 0xFFU; + } + else + { + ; /* Nothing */ + } + + /*********************************************************************** + * Judge board type + ***********************************************************************/ + BOARDTYPE = r_boardcnf_get_brd_type(); + if (BOARDTYPE >= BOARDNUM) + { + FATAL_MSG("DDR:Unknown Board\n"); + return 0xFFU; + } + + Boardcnf = (const st_boardcnf_t *)&boardcnfs[BOARDTYPE]; + + ddr_phyvalid = (uint32_t)(Boardcnf->bdcfg_phyvalid); + + max_density = 0U; + + for (cs = 0U; cs < CS_CNT; cs++) + { + ch_have_this_cs[cs] = 0U; + } + + r_foreach_ech((ch)) + { + for (cs = 0U; cs < CS_CNT; cs++) + { + ddr_density[ch][cs] = 0xFFU; + } + } + + r_foreach_vch((ch)) + { + for (cs = 0U; cs < CS_CNT; cs++) + { + dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_ddr_density[cs]); + ddr_density[ch][cs] = dataL; + if (dataL == 0xFFU) + { + continue; + } + if (dataL > max_density) + { + max_density = dataL; + } + ch_have_this_cs[cs] |= (1U << ch); + } + } + + /*********************************************************************** + * Judge board clock frequency (in MHz) + ***********************************************************************/ + r_boardcnf_get_brd_clk(BOARDTYPE, &brd_clk, &brd_clkdiv); + if (((0x01U << 14) & mmio_read_32(RST_MODEMR0)) != 0x0U) + { + brd_clkdiva = 1U; + } + else + { + brd_clkdiva = 0U; + } + + /*********************************************************************** + * Judge ddr operating frequency clock(in Mbps) + ***********************************************************************/ + r_boardcnf_get_ddr_mbps(BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv, &sscg); + + ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U)); + ddr_mul_low = CLK_DIV(6400U, 1U * 2U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U)); + + if (sscg != 0x0U) + { + ddr_mul_reg = ddr_mul_low - 2U; + } + else + { + ddr_mul_reg = ddr_mul_low; + } + +#if RCAR_PLL3_FRAC_MODE == 1U + ddr_mul_nf = ((8U * ddr_mbps * brd_clkdiv * (brd_clkdiva + 1U)) / (ddr_mbpsdiv * brd_clk * 2U)) - (8U * (ddr_mul / 2U) * 2U); +#else + ddr_mul_nf = 0x00U; +#endif + + dataL = 0x03U & (mmio_read_32(RST_MODEMR0) >> 13); + bus_clk = 0U; + bus_clkdiv = 0U; + + switch (dataL) + { + case 0U: + bus_clk = brd_clk * 0x18U; + bus_clkdiv = brd_clkdiv; + break; + case 1U: + bus_clk = brd_clk * 0x14U; + bus_clkdiv = brd_clkdiv; + break; + case 2U: + /* Not supported */ + bus_clk = brd_clk * 0x20U; + bus_clkdiv = brd_clkdiv * 2U; + break; + case 3U: + bus_clk = brd_clk * 0x18U; + bus_clkdiv = brd_clkdiv * 2U; + break; + default: + bus_clk = brd_clk * 0x18U; + bus_clkdiv = brd_clkdiv * 2U; + break; + } + + /*********************************************************************** + * Adjust tccd + ***********************************************************************/ + ddr_tccd = 2U; + + NOTICE("DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); + + MSG_LF("Start\n"); + + /*********************************************************************** + * initialize DDR + ***********************************************************************/ + dataL = r_init_ddr(); + if (dataL == ddr_phyvalid) + { + failcount = 0U; + } + else + { + failcount = 1U; + } + + NOTICE("..%d\n", failcount); + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00000000U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00000000U); + + if (failcount == 0U) + { + return INITDRAM_OK; + } + else + { + return INITDRAM_NG; + } +} + +#if (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) +/** +* DDR Initialize entry +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-16:V4H-LPDDR5-DDR-HW-FD-10-03 +* @details Set PI READ Leveling interval.\n +* -# First, unlock DDRPHY register.\n +* -# Clear PI_INT_STATUS register.\n +* -# Wait for wdq training to be done.\n +* -# Set PI read leveling interval.\n +* -# Last, lock DDRPHY register.\n +*/ +void r_set_pi_rdlvl_interval(void) +{ + uint32_t ch; + uint32_t dataL; + uint32_t ctrl_clk; + uint32_t clk_count; + uint32_t phymster_req_interval; + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00001234U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00001234U); + + /* Unlock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU); + } + + /* PI_INT_STATUS clear */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x07U); + } + + /* wait wdq training done */ + (void)r_pi_int_ack_0_assert(31U); + + /* set pi_rdlvl_interval */ + phymster_req_interval = PERIODIC_TRAINING_INTERVAL - 3000U; + clk_count = 1024U - (r_ddrtbl_getval_pi(DDR_PI_REGSET, PI_LONG_COUNT_MASK) * 32U); + ctrl_clk = ddr_mbps / ddr_mbpsdiv / 8U; + dataL = phymster_req_interval * ctrl_clk / clk_count; + r_ddr_setval_ach(PI_RDLVL_INTERVAL, dataL); + + /* Lock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U); + } + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00000000U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00000000U); + +} +#endif /* (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) */ + +/******************************************************************************* + * END + ******************************************************************************/ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.c new file mode 100644 index 0000000..282b056 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.c @@ -0,0 +1,194 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#else +#include "mem_io.h" +#include "log.h" +#endif +#include "boot_init_dram_config.h" +#include "boot_init_dram_regdef.h" + +/******************************************************************************* + * PLEASE SET board number or board judge function + ******************************************************************************/ +#define BOARD_JUDGE_AUTO +#ifdef BOARD_JUDGE_AUTO +static uint32_t r_board_judge(void); +uint32_t r_boardcnf_get_brd_type(void) +{ + return r_board_judge(); +} +#else /* BOARD_JUDGE_AUTO */ +uint32_t r_boardcnf_get_brd_type(void) +{ + return (0); +} +#endif /* BOARD_JUDGE_AUTO */ + +/** +* RENESAS WHITE HAWK BOARD EXAMPLE +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-01-02:V4H-LPDDR5-DDR-HW-DD-01-04-01 +* @param[in] brd Argument for dummy read +* @param[in] clk The pointer which indicate the clock frequency +* @param[in] div The pointer which indicate the clock frequency division +* @details judged by md14/md13\n +* 16.66MHz CLK,DIV= 50,3 (md14,md13==0,0) +* 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1) +* 33.33MHz CLK,DIV=100,3 (md14,md13==1,1) +*/ +void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div) +{ + uint32_t md; + + md = (mmio_read_32(RST_MODEMR0) >> 13) & 0x3U; + switch (md) + { + case 0x0U : *clk = 50U; *clk_div = 3U; break; /* 50 / 3 = 16.66MHz */ + case 0x1U : *clk = 60U; *clk_div = 3U; break; /* 60 / 3 = 20.00MHz */ + case 0x2U : NOTICE("MD14/MD13 is invalid!!\n"); panic; /* Not supported */ + case 0x3U : *clk = 100U; *clk_div = 3U; break; /* 100 / 3 = 33.33MHz */ + default : /* nop */ break; + } + (void)brd; +} + +/******************************************************************************* + * DDR MBPS TARGET + * PLEASE DEFINE HOW TO JUDGE DDR BPS + ******************************************************************************/ +/** +* DDRxxxx (judge by md19, md17) : Mbps +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-01-03:V4H-LPDDR5-DDR-HW-DD-01-04-02 +* @param[in] brd Argument for dummy read +* @param[in] mbps The pointer which indicate the ddr frequency +* @param[in] div The pointer which indicate the ddr frequency division +* @details SSCG enable / disable for PLL1 (judge by md37/md36) +* According to Bit[17] of RST_MODEMR0 and Bit[5:4] of RST_MODEMR1, +* determine the value of ddr mbps and mbps division. +*/ +void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg) +{ + uint32_t md; + uint32_t product; + + md = (mmio_read_32(RST_MODEMR0) >> 17) & 0x05U; + md = (md | (md >> 1)) & 0x03U; + *sscg = (mmio_read_32(RST_MODEMR1) >> 4) & 0x03U; + product = mmio_read_32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK; + + if (product == 0x01U) + { + /* V4H-5 */ + switch (md) + { + case 0x0U : *mbps = 5000U; *mbps_div = 1U; break; /* 5000Mbps */ + case 0x1U : *mbps = 5000U; *mbps_div = 1U; break; /* 5000Mbps */ + case 0x2U : *mbps = 5000U; *mbps_div = 1U; break; /* 5000Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + } + else if (product == 0x02U) + { + /* V4H-3 */ + switch (md) + { + case 0x0U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + case 0x1U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + case 0x2U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + } + else + { + /* V4H-7 */ + switch (*sscg) + { + case 0x0U : + switch (md) + { + case 0x0U : *mbps = 6400U; *mbps_div = 1U; break; /* 6400Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + default : /* nop */ break; + } + break; + case 0x1U : + switch (md) + { + case 0x0U : *mbps = 19000U; *mbps_div = 3U; break; /* 6333Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + default : /* nop */ break; + } + break; + case 0x2U : /* Not supported */ + NOTICE("This MD37/MD36 value is invalid!!\n");panic; + case 0x3U : + switch (md) + { + case 0x0U : *mbps = 19000U; *mbps_div = 3U; break; /* 6333Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; break; /* 4800Mbps */ + default : /* nop */ break; + } + break; + default : + /* nop */ + break; + } + } + (void)brd; +} + +#ifdef BOARD_JUDGE_AUTO +/******************************************************************************* + * SAMPLE board detect function + ******************************************************************************/ +/** +* Select the setting parameters about the Spieder board you use. +* @par TraceID Cover_SW_UD:Cover_HW_DD +* V4H-LPDDR5-DDR-SW-UD-10:V4H-LPDDR5-DDR-HW-DD-01-03-02 +* @return uint32_t Selected table index, this is sample value 0. +* @details Pass the return value from the r_board_judge function. +* In case that "BOARD_JUDGE_AUTO" is not defined, Another process will be called.\n\n +*/ +static uint32_t r_board_judge(void) +{ + uint32_t brd; + + brd = 0U; /* white hawk (64Gbit 1rank)*/ + + return brd; +} +#endif diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.h new file mode 100644 index 0000000..d3c36bf --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_config.h @@ -0,0 +1,236 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#ifndef BOOT_INIT_DRAM_CONFIG +#define BOOT_INIT_DRAM_CONFIG + +#include "boot_init_dram_regdef.h" + +//! @details DRAM Param setting +#define JS2_DERATE 0U +//! @details Average periodic refresh interval/Average Refresh Interval [ns] +#define DBSC_REFINT 1920U +#ifndef DBSC_REFINTS +//! 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. +#define DBSC_REFINTS 0U +#endif +//! @details Periodic-WriteDQ/ReadDQ Training Interval [us] +#define PERIODIC_TRAINING_INTERVAL 20000U + +/******************************************************************************* + * NUMBER OF BOARD CONFIGRATION + * PLEASE DEFINE + ******************************************************************************/ +//! @details Add User platform BOARD +#define BOARDNUM 3U + +/******************************************************************************* + * BOARD CONFIGRATION + * PLEASE DEFINE boardcnfs[] + ******************************************************************************/ +uint32_t r_boardcnf_get_brd_type(void); +void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div); +void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg); + +/******************************************************************************* + * BOARD CONFIGRATION + * PLEASE DEFINE boardcnfs[] + ******************************************************************************/ +typedef struct{ + /* + 0x00...0000B: 4Gb dual channel die / 2Gb single channel die + 0x01...0001B: 6Gb dual channel die / 3Gb single channel die + 0x02...0010B: 8Gb dual channel die / 4Gb single channel die + 0x03...0011B: 12Gb dual channel die / 6Gb single channel die + 0x04...0100B: 16Gb dual channel die / 8Gb single channel die + 0x05...0101B: 24Gb dual channel die / 12Gb single channel die + 0x06...0110B: 32Gb dual channel die / 16Gb single channel die + 0x07...0111B: 24Gb single channel die + 0x08...1000B: 32Gb single channel die + 0xFF...NO_MEMORY + */ + uint8_t bdcfg_ddr_density[CS_CNT]; + /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */ + uint32_t bdcfg_ca_swap; + /* SoC dqsX([1][0]) -> MEM dqsY: */ + uint8_t bdcfg_dqs_swap; + /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ + uint32_t bdcfg_dq_swap[SLICE_CNT]; + /* SoC dm -> MEM dqY/dm: (8 means DM) */ + uint8_t bdcfg_dm_swap[SLICE_CNT]; + /* SoC ckeX([1][0]) -> MEM csY */ + uint8_t bdcfg_cs_swap; +}st_boardcnf_ch_t; + +typedef struct { + + /* ch in use */ + uint8_t bdcfg_phyvalid; + /* Read vref (SoC) training range : [23:16]step / [15:8]stop / [7:0]start, 0x00000000 = default val */ + uint32_t bdcfg_vref_r; + /* Write vref (MR14, MR15) training range : [15:8]stop / [7:0]start, 0x0000 = default val */ + uint16_t bdcfg_vref_w; + /* CA vref (MR12) training range : [15:8]stop / [7:0]start, 0x0000 = default val */ + uint16_t bdcfg_vref_ca; + /* RFM required check : 0x01 = check enable, 0x00 = check disable */ + uint8_t bdcfg_rfm_chk; + //! @details Board parameter about channels + st_boardcnf_ch_t ch[4]; +}st_boardcnf_t; + +static const st_boardcnf_t boardcnfs[BOARDNUM] = { +/* + * boardcnf[0] RENESAS V4H White Hawk (64Gbit 1rank) + */ +{ + 0x0FU, /* bdcfg_phyvalid */ + 0x00000000U, /* bdcfg_vref_r */ + 0x0000U, /* bdcfg_vref_w */ + 0x0000U, /* bdcfg_vref_ca */ + 0x01U, /* bdcfg_rfm_chk */ + { +/* ch[0] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x04506132U, +/* bdcfg_dqs_swap */ 0x01U, +/* bdcfg_dq_swap[] */ { 0x26147085U, 0x12306845U }, +/* bdcfg_dm_swap[] */ { 0x03U, 0x07U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[1] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x02341065U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x56782314U, 0x71048365U }, +/* bdcfg_dm_swap[] */ { 0x00U, 0x02U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[2] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x02150643U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x58264071U, 0x41207536U }, +/* bdcfg_dm_swap[] */ { 0x03U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[3] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x01546230U, +/* bdcfg_dqs_swap */ 0x01U, +/* bdcfg_dq_swap[] */ { 0x45761328U, 0x62801745U }, +/* bdcfg_dm_swap[] */ { 0x00U, 0x03U }, +/* bdcfg_cs_swap */ 0x10U + } + } +}, +/* + * boardcnf[1] RENESAS V4H White Hawk (64Gbit 2rank) + */ +{ + 0x0FU, /* bdcfg_phyvalid */ + 0x00000000U, /* bdcfg_vref_r */ + 0x0000U, /* bdcfg_vref_w */ + 0x0000U, /* bdcfg_vref_ca */ + 0x01U, /* bdcfg_rfm_chk */ + { +/* ch[0] */ { +/* bdcfg_ddr_density[] */ { 0x04U, 0x04U }, +/* bdcfg_ca_swap */ 0x04506132U, +/* bdcfg_dqs_swap */ 0x01U, +/* bdcfg_dq_swap[] */ { 0x26147085U, 0x12306845U }, +/* bdcfg_dm_swap[] */ { 0x03U, 0x07U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[1] */ { +/* bdcfg_ddr_density[] */ { 0x04U, 0x04U }, +/* bdcfg_ca_swap */ 0x02341065U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x56782314U, 0x71048365U }, +/* bdcfg_dm_swap[] */ { 0x00U, 0x02U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[2] */ { +/* bdcfg_ddr_density[] */ { 0x04U, 0x04U }, +/* bdcfg_ca_swap */ 0x02150643U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x58264071U, 0x41207536U }, +/* bdcfg_dm_swap[] */ { 0x03U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[3] */ { +/* bdcfg_ddr_density[] */ { 0x04U, 0x04U }, +/* bdcfg_ca_swap */ 0x01546230U, +/* bdcfg_dqs_swap */ 0x01U, +/* bdcfg_dq_swap[] */ { 0x45761328U, 0x62801745U }, +/* bdcfg_dm_swap[] */ { 0x00U, 0x03U }, +/* bdcfg_cs_swap */ 0x10U + } + } +}, +/* + * boardcnf[2] RENESAS V4H (4ch) + */ +{ + 0x0FU, /* bdcfg_phyvalid */ + 0x00000000U, /* bdcfg_vref_r */ + 0x0000U, /* bdcfg_vref_w */ + 0x0000U, /* bdcfg_vref_ca */ + 0x01U, /* bdcfg_rfm_chk */ + { +/* ch[0] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x06543210U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U }, +/* bdcfg_dm_swap[] */ { 0x08U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[1] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x06543210U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U }, +/* bdcfg_dm_swap[] */ { 0x08U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[2] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x06543210U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U }, +/* bdcfg_dm_swap[] */ { 0x08U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[3] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0xFFU }, +/* bdcfg_ca_swap */ 0x06543210U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U }, +/* bdcfg_dm_swap[] */ { 0x08U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + } + } +} + +}; +#endif /* BOOT_INIT_DRAM_CONFIG */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h new file mode 100644 index 0000000..a31f1f0 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/boot_init_dram_regdef.h @@ -0,0 +1,203 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#ifndef BOOT_INIT_DRAM_REGDEF +#define BOOT_INIT_DRAM_REGDEF + +#if defined(__RH850G3K__) +#include "remap_register.h" +#endif + +//! @details The version of DDR code +#define RCAR_DDR_VERSION "rev.1.10" +//! @details The number of channels V4H has +#define DRAM_CH_CNT 0x04U +//! @details The number of slices V4H has +#define SLICE_CNT 0x02U +//! @details The number of chip select V4H has +#define CS_CNT 0x02U + +//! @details for pll setting +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) + +//! @details for ddr density setting +#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30U) | ((row) << 24U) | ((BG) << 20U) | ((bank) << 16U) | ((col) << 8U) | (dw)) +//! @details for 16bit value +#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density % 2U), (((density+ 1U) / 2U) + (28U - 2U - 2U - 10U - 1U)), 2U, 2U, 10U, 1U)) /* 16bit */ + +//! @details Kick bit setting CPG PLL3 division +#define CPG_FRQCRD_KICK_BIT (1U << 31) +//! @details Kick bit to reflect setting CPG PLL3 value +#define CPG_PLL3CR0_KICK_BIT (1U << 31) +//! @details Status bit to check CPG PLL3 works normally +#define CPG_PLLECR_PLL3ST_BIT (1U << 11) + +#if defined(__RH850G3K__) +//! @details If this bin is processed by RH850G3K, address will be remapped. +#define CPG_BASE (BASE_CPG_ADDR) +#else +//! @details If this bin is processed by Arm core, address will be "0xE6150000U". +#define CPG_BASE (0xE6150000U) +#endif +//! @details 32-bit readable/writable register +#define CPG_CPGWPR (CPG_BASE + 0x0000U) +//! @details The register specifies the DDR and DBSC clock (ZB3, ZB3D2,ZB3D4) frequency +#define CPG_FRQCRD0 (CPG_BASE + 0x080CU) +//! @details PLL Enable Control Register +#define CPG_PLLECR (CPG_BASE + 0x0820U) +//! @details The register specifies the integer multiplication ratio +#define CPG_PLL3CR0 (CPG_BASE + 0x083CU) +//! @details The register specifies the fractional multiplication +#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U) +//! @details Functional Safety Reset Check Clear Register +#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U) +//! @details Functional Safety Reset Check Set Register +#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U) +//! @details Functional Safety Reset Check Register A +#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U) +//! @details Software Reset Status Register +#define CPG_SRCR4 (CPG_BASE + 0x2C10U) +//! @details Software Reset Clearing Register +#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U) + +#if defined(__RH850G3K__) +//! @details If this bin is processed by RH850G3K, address will be remapped. +#define RST_BASE (BASE_RESET_ADDR) +#else +//! @details If this bin is processed by Arm core, address will be 0xE6160000U. +#define RST_BASE (0xE6160000U) +#endif +//! @details 32-bit read-only register, which is initialized only by POR. +#define RST_MODEMR0 (RST_BASE + 0x0000U) +//! @details 32-bit read-only register, which is initialized only by POR. +#define RST_MODEMR1 (RST_BASE + 0x0004U) + +#if defined(__RH850G3K__) +#define OTP_MEM_1_BASE (BASE_OTP_MEM_ADDR) +#else +#define OTP_MEM_1_BASE (0xE61BF000U) +#endif +#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U) +#define OTP_MEM_PRODUCT_MASK (0x000000FFU) + +/* Product Register */ +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) + +#define PRR_PRODUCT_V4H (0x00005C00U) /* R-Car V4H */ + +#define PRR_PRODUCT_30 (0x00000020U) /* ver 3.0 */ + +/* DBSC registers */ +#if defined(__RH850G3K__) +//! @details If this bin is processed by RH850G3K, address will be remapped. +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#else +//! @details If this bin is processed by RH850G3K, address will be remapped. +#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#endif +//! @details DBSC4 System Configuration Register 0 +#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U) +//! @details DBSC4 System Configuration Register 1(for DFI domain) +#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U) +//! @details DBSC4 System Configuration Register 1(for AXI domain) +#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U) +//! @details DBSC4 System Configuration Register 2 +#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U) +//! @details PHY type Configuration Register +#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U) +//! @details PHY type Configuration Register 2A +#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U) +//! @details Memory Type register (for DFI domain) +#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U) +//! @details Memory Type register (for AXI domain) +#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U) +//! @details SDRAM Configuration setting Register (for DFI domain) +#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + (0x2000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs))) +//! @details SDRAM Configuration setting Register (for AXI domain) +#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + (0x4000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs))) +//! @details DBSC System Register 0(For DFI Domain) +#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U) +//! @details DBSC System Register 0(For AXI Domain) +#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U) +//! @details SDRAM Access Enable Register +#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U) +//! @details Auto-Refresh Enable Register +#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U) +//! @details Manual Command-Issuing Register +#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U) +//! @details Operation Complition Waiting Register +#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U) +//! @details SDRAM Operation Setting Register(for DFI domain) +#define DBSC_DBBL (DBSC_D_BASE + 0x0400U) +//! @details SDRAM Operation Setting Register(for AXI domain) +#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U) +//! @details Refresh Configuration Register 1 +#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U) +//! @details Refresh Configuration Register 2 +#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U) +//! @details SDRAM Callibration Configuration Register +#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U) +//! @details DBI Configuration Register +#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U) +//! @details DFI PHY Master Control Register +#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U) +//! @details DFI Control Update Configuration Register +#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U) +//! @details CAM Unit Operation Setting Register +#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU) +//! @details Read/Write Scheduling Setting Register 1 +#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U) +//! @details Data Transfer Cycle Setting +#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U) +//! @details SDRAM Timing Register X +#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + (0x04U * (x))) +//! @details Multirank Operation Setting Register x +#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + (0x04U * (x))) +//! @details DFI Status Interface Input Regiser +#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details DFI Status Interface Output Regiser +#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details PHY Unit Control Register 02 +#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details PHY Unit Lock register +#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details PHY Unit register address +#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details PHY Unit register access +#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details PHY Unit Registers Mask for channel +#define DBSC_DBPDRGM(ch) (DBSC_D_BASE + 0x062CU + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details PHY Status Register0 ch +#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details PHY Status Register1 ch +#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) +//! @details Interval Setting for scheduler +#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U) +//! @details Interval Setting for scheduler +#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U) + +#endif /* BOOT_INIT_DRAM_REGDEF */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ddr_regdef.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ddr_regdef.h new file mode 100644 index 0000000..f566504 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ddr_regdef.h @@ -0,0 +1,269 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#ifndef DDR_REGDEF +#define DDR_REGDEF + +#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL 0x10031000U +#define PHY_PER_CS_TRAINING_MULTICAST_EN 0x10011006U +#define PHY_VREF_INITIAL_STEPSIZE 0x1808100DU +#define PHY_RDLVL_BEST_THRSHLD 0x0004100EU +#define PHY_RDLVL_VREF_OUTLIER 0x1003100EU +#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x1005102CU +#define PHY_CALVL_VREF_DRIVING_SLICE 0x18011030U +#define PHY_WRLVL_HARD0_DELAY_OBS 0x000A1038U +#define PHY_WRLVL_HARD1_DELAY_OBS 0x100A1038U +#define PHY_WRLVL_STATUS_OBS 0x001C1039U +#define PHY_WRLVL_ERROR_OBS 0x0010103BU +#define PHY_GTLVL_STATUS_OBS 0x0012103DU +#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x1009103EU +#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x0009103FU +#define PHY_WDQLVL_STATUS_OBS 0x00201043U +#define PHY_DATA_DC_CAL_START 0x1801104DU +#define PHY_SLV_DLY_CTRL_GATE_DISABLE 0x1001104EU +#define PHY_REGULATOR_EN_CNT 0x18061050U +#define PHY_VREF_INITIAL_START_POINT 0x00091055U +#define PHY_VREF_INITIAL_STOP_POINT 0x10091055U +#define PHY_VREF_TRAINING_CTRL 0x00021056U +#define PHY_RDDQ0_SLAVE_DELAY 0x0009105DU +#define PHY_RDDQ1_SLAVE_DELAY 0x1009105DU +#define PHY_RDDQ2_SLAVE_DELAY 0x0009105EU +#define PHY_RDDQ3_SLAVE_DELAY 0x1009105EU +#define PHY_RDDQ4_SLAVE_DELAY 0x0009105FU +#define PHY_RDDQ5_SLAVE_DELAY 0x1009105FU +#define PHY_RDDQ6_SLAVE_DELAY 0x00091060U +#define PHY_RDDQ7_SLAVE_DELAY 0x10091060U +#define PHY_RDDM_SLAVE_DELAY 0x00091061U +#define PHY_RX_CAL_ALL_DLY 0x18061061U +#define PHY_RX_PCLK_CLK_SEL 0x00031062U +#define PHY_DATA_DC_CAL_CLK_SEL 0x18031063U +#define PHY_PAD_VREF_CTRL_DQ 0x000E1067U +#define PHY_PER_CS_TRAINING_EN 0x00011068U +#define PHY_RDDATA_EN_TSEL_DLY 0x18051069U +#define PHY_RDDATA_EN_OE_DLY 0x0005106AU +#define PHY_RPTR_UPDATE 0x1004106CU +#define PHY_WRLVL_RESP_WAIT_CNT 0x0806106DU +#define PHY_RDLVL_DLY_STEP 0x08041070U +#define PHY_RDLVL_MAX_EDGE 0x00091071U +#define PHY_RDDATA_EN_DLY 0x10051076U +#define PHY_DQ_DM_SWIZZLE0 0x00201077U +#define PHY_DQ_DM_SWIZZLE1 0x00041078U +#define PHY_CLK_WRDQS_SLAVE_DELAY 0x0009107EU +#define PHY_WRITE_PATH_LAT_DEC 0x1001107EU +#define PHY_RDDQS_GATE_SLAVE_DELAY 0x00091088U +#define PHY_RDDQS_LATENCY_ADJUST 0x10051088U +#define PHY_WRITE_PATH_LAT_ADD 0x18031088U +#define PHY_WRITE_PATH_LAT_FRAC 0x00081089U +#define PHY_GTLVL_LAT_ADJ_START 0x0005108AU +#define PHY_ADR_CALVL_SWIZZLE0 0x00201202U +#define PHY_ADR_MEAS_DLY_STEP_ENABLE 0x10011203U +#define PHY_ADR_CALVL_RANK_CTRL 0x18021205U +#define PHY_ADR_CALVL_OBS1 0x0020120AU +#define PHY_ADR_CALVL_OBS2 0x0020120BU +#define PHY_ADR_CALVL_DLY_STEP 0x00041210U +#define PHY_CS_ACS_ALLOCATION_BIT2_2 0x08021215U +#define PHY_CS_ACS_ALLOCATION_BIT3_2 0x10021215U +#define PHY_CSLVL_OBS1 0x00201221U +#define PHY_CLK_DC_CAL_CLK_SEL 0x0803123AU +#define PHY_FREQ_SEL_MULTICAST_EN 0x08011301U +#define PHY_FREQ_SEL_INDEX 0x10021301U +#define SC_PHY_MANUAL_UPDATE 0x18011304U +#define PHY_SET_DFI_INPUT_RST_PAD 0x18011311U +#define PHY_CAL_MODE_0 0x000D132CU +#define PHY_CAL_INTERVAL_COUNT_0 0x0020132DU +#define PHY_DATA_BYTE_ORDER_SEL 0x0020133EU +#define PHY_PAD_ACS_RX_PCLK_CLK_SEL 0x10031348U +#define PHY_PLL_CTRL 0x000E134BU +#define PHY_PLL_CTRL_8X 0x100E134BU +#define PHY_CAL_CLK_SELECT_0 0x00031360U +#define SC_PHY_WCK_CALC 0x1801101AU +#define PI_START 0x00010800U +#define PI_TRAIN_ALL_FREQ_REQ 0x18010802U +#define PI_CS_MAP 0x08020813U +#define PI_WRLVL_REQ 0x1001081CU +#define PI_WRLVL_CS_SW 0x1802081CU +#define PI_RDLVL_REQ 0x18010824U +#define PI_RDLVL_GATE_REQ 0x00010825U +#define PI_RDLVL_CS_SW 0x08020825U +#define PI_DRAMDCA_FLIP_MASK 0x0802083BU +#define PI_DRAMDCA_LVL_REQ 0x1001083DU +#define PI_DCMLVL_CS_SW 0x1802083DU +#define PI_WRDCM_LVL_EN_F1 0x0002083FU +#define PI_DRAMDCA_LVL_EN_F1 0x0802083FU +#define PI_WRDCM_LVL_EN_F2 0x1802083FU +#define PI_DRAMDCA_LVL_EN_F2 0x00020840U +#define PI_TCKCKEL_F2 0x1804089DU +#define PI_INT_STATUS 0x00200900U +#define PI_INT_ACK_0 0x00200902U +#define PI_INT_ACK_1 0x00030903U +#define PI_ADDR_MUX_0 0x00030910U +#define PI_ADDR_MUX_1 0x08030910U +#define PI_ADDR_MUX_2 0x10030910U +#define PI_ADDR_MUX_3 0x18030910U +#define PI_ADDR_MUX_4 0x00030911U +#define PI_ADDR_MUX_5 0x08030911U +#define PI_ADDR_MUX_6 0x10030911U +#define PI_DATA_BYTE_SWAP_EN 0x18010911U +#define PI_DATA_BYTE_SWAP_SLICE0 0x00010912U +#define PI_DATA_BYTE_SWAP_SLICE1 0x08010912U +#define PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x00080964U +#define PI_WRLAT_F2 0x1007096AU +#define PI_TWCKENL_WR_ADJ_F2 0x1806096AU +#define PI_TWCKENL_RD_ADJ_F2 0x0006096BU +#define PI_TWCKPRE_STATIC_F2 0x0806096BU +#define PI_TWCKPRE_TOGGLE_RD_F2 0x1806096BU +#define PI_TWCKENL_FS_ADJ_F2 0x0006096CU +#define PI_CASLAT_F2 0x0807096CU +#define PI_TRFC_F2 0x000A0971U +#define PI_TREF_F2 0x00140972U +#define PI_TDFI_WRLVL_WW_F0 0x000A0974U +#define PI_TDFI_WRLVL_WW_F1 0x000A0975U +#define PI_WRLVL_EN_F2 0x18020975U +#define PI_TDFI_WRLVL_WW_F2 0x000A0976U +#define PI_WRLVL_WCKOFF_F2 0x10080976U +#define PI_RDLVL_EN_F2 0x1802097AU +#define PI_RDLVL_GATE_EN_F2 0x0002097BU +#define PI_RDLVL_VREF_EN_F0 0x1004097BU +#define PI_RDLVL_VREF_EN_F1 0x0004097DU +#define PI_RDLVL_VREF_EN_F2 0x1004097EU +#define PI_RDLAT_ADJ_F2 0x00090981U +#define PI_WRLAT_ADJ_F2 0x00070982U +#define PI_TDFI_CALVL_CC_F2 0x000A0985U +#define PI_TDFI_CALVL_CAPTURE_F2 0x100A0985U +#define PI_CALVL_EN_F2 0x10020986U +#define PI_TCAENT_F2 0x000E0989U +#define PI_TVREF_SHORT_F2 0x000A098FU +#define PI_TVREF_LONG_F2 0x100A098FU +#define PI_TVRCG_ENABLE_F2 0x000A0990U +#define PI_TVRCG_DISABLE_F2 0x100A0990U +#define PI_CALVL_VREF_INITIAL_START_POINT_F0 0x00070991U +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F0 0x08070991U +#define PI_CALVL_VREF_INITIAL_START_POINT_F1 0x18070991U +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F1 0x00070992U +#define PI_CALVL_VREF_INITIAL_START_POINT_F2 0x10070992U +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x18070992U +#define PI_TDFI_CALVL_STROBE_F2 0x08040995U +#define PI_TXP_F2 0x10050995U +#define PI_TMRWCKEL_F2 0x18080995U +#define PI_TCKEHDQS_F2 0x1006099DU +#define PI_TFC_F2 0x000A099EU +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x100709A0U +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x180709A0U +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x000709A4U +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x080709A4U +#define PI_TDFI_WDQLVL_WR_F2 0x000A09A6U +#define PI_TDFI_WDQLVL_RW_F2 0x100A09A6U +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x000709A7U +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x080709A7U +#define PI_WDQLVL_EN_F2 0x180209A7U +#define PI_MBIST_RDLAT_ADJ_F2 0x080909A8U +#define PI_MBIST_TWCKENL_RD_ADJ_F2 0x180609A8U +#define PI_TRTP_F2 0x180809B3U +#define PI_TRP_F2 0x000809B4U +#define PI_TRCD_F2 0x080809B4U +#define PI_TWTR_S_F2 0x180609B4U +#define PI_TWTR_L_F2 0x000609B5U +#define PI_TWTR_F2 0x100609B5U +#define PI_TWR_F2 0x180809B5U +#define PI_TRAS_MIN_F2 0x100909B6U +#define PI_TDQSCK_MAX_F2 0x000409B7U +#define PI_TSR_F2 0x100809B7U +#define PI_TMRD_F2 0x180809B7U +#define PI_TDFI_CTRLUPD_MAX_F2 0x001509BCU +#define PI_TDFI_CTRLUPD_INTERVAL_F2 0x002009BDU +#define PI_TINIT_F2 0x001809CCU +#define PI_TINIT1_F2 0x001809CDU +#define PI_TINIT3_F2 0x001809CEU +#define PI_TINIT4_F2 0x001809CFU +#define PI_TINIT5_F2 0x001809D0U +#define PI_TXSNR_F2 0x001009D1U +#define PI_TZQCAL_F2 0x100C09D6U +#define PI_TZQLAT_F2 0x000709D7U +#define PI_ZQRESET_F2 0x100C09D8U +#define PI_TDQ72DQ_F2 0x100A09DDU +#define PI_TCBTRTW_F2 0x000609DEU +#define PI_MC_TRFC_F2 0x000A09E1U +#define PI_CKE_MUX_0 0x000309E6U +#define PI_CKE_MUX_1 0x080309E6U +#define PI_SEQ_DEC_SW_CS 0x00020A4EU +#define PI_SW_SEQ_START 0x10010A4EU +#define PI_SW_SEQ_0 0x001B0BF1U +#define PI_SW_SEQ_1 0x001B0BF2U +#define PI_DFS_ENTRY_SEQ_0 0x001D0BFBU +#define PI_DFS_INITIALIZATION_SEQ_1 0x001D0C24U +#define PI_DFS_INITIALIZATION_SEQ_9 0x001D0C2CU +#define PI_DFS_INITIALIZATION_SEQ_10 0x001D0C2DU +#define PI_SEQ_WAIT_16_F2 0x00180C77U +#define PI_SEQ_WAIT_17_F2 0x00180C7AU +#define PI_SEQ_WAIT_18_F2 0x00180C7DU +#define PI_SEQ_WAIT_19_F2 0x00180C80U +#define PI_SEQ_WAIT_20_F2 0x00180C83U +#define PI_SEQ_WAIT_21_F2 0x00180C86U +#define PI_SEQ_WAIT_22_F2 0x00180C89U +#define PI_SEQ_WAIT_23_F2 0x00180C8CU +#define PI_SEQ_WAIT_24_F2 0x00180C8FU +#define PI_SEQ_WAIT_25_F2 0x00180C92U +#define PI_SEQ_WAIT_26_F2 0x00180C95U +#define PI_SEQ_WAIT_30_F2 0x00180CA1U +#define PI_DARRAY3_0_CS0_F0 0x00080D0BU +#define PI_DARRAY3_1_CS0_F0 0x08080D0BU +#define PI_DARRAY3_0_CS0_F1 0x00080D15U +#define PI_DARRAY3_1_CS0_F1 0x08080D15U +#define PI_DARRAY3_0_CS0_F2 0x00080D1FU +#define PI_DARRAY3_1_CS0_F2 0x08080D1FU +#define PI_DARRAY3_4_CS0_F2 0x00080D20U +#define PI_DARRAY3_20_CS0_F2 0x00080D24U +#define PI_DARRAY3_0_CS1_F0 0x00080D29U +#define PI_DARRAY3_1_CS1_F0 0x08080D29U +#define PI_DARRAY3_0_CS1_F1 0x00080D33U +#define PI_DARRAY3_1_CS1_F1 0x08080D33U +#define PI_DARRAY3_0_CS1_F2 0x00080D3DU +#define PI_DARRAY3_1_CS1_F2 0x08080D3DU +#define PI_DARRAY3_4_CS1_F2 0x00080D3EU +#define PI_DARRAY3_20_CS1_F2 0x00080D42U +#define PI_DLL_RST 0x00010941U +#define PI_PWRUP_SREFRESH_EXIT 0x1801093DU +#define PI_PWRUP_SREFRESH_EXIT 0x1801093DU +#define PI_RDLVL_TRAIN_SEQ_1 0x001B0C42U +#define PI_RDLVL_TRAIN_SEQ_2 0x001B0C43U +#define PI_RDLVL_TRAIN_SEQ_3 0x001B0C44U +#define PI_RDLVL_TRAIN_SEQ_4 0x001B0C45U +#define PI_RDLVL_TRAIN_SEQ_5 0x001B0C46U +#define PI_WDQLVL_VREF_EN 0x0804089EU +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_2 0x001B0868U +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_3 0x001B0869U +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_4 0x001B086AU +#define PHY_PER_CS_TRAINING_INDEX 0x18011006U +#define PHY_DATA_DC_DQS_CLK_ADJUST 0x0008108CU +#define PHY_DATA_DC_WDQLVL_ENABLE 0x08021075U +#define PI_WDQLVL_PERIODIC 0x000108A0U +#define PHY_MEAS_DLY_STEP_ENABLE 0x08061076U +#define PI_RDLVL_PERIODIC 0x0801082EU +#define PI_LONG_COUNT_MASK 0x1005090FU +#define PI_WDQLVL_INTERVAL 0x001008A4U +#define PI_RDLVL_INTERVAL 0x08100835U +#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xFFFFU) +#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xFFU) +#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xFFU) + +#endif /* DDR_REGDEF */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c new file mode 100644 index 0000000..4245fdc --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.c @@ -0,0 +1,183 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC initialize function + ******************************************************************************/ +/****************************************************************************** + * @file ecc_enable_v4h.c + * - Version : 0.06 + * @brief Enable setting process of ECC for DRAM. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 09.08.2022 0.01 First Release + * : 16.11.2022 0.02 Change ecc_enable to ecc_sdram_enable + * : 04.04.2023 0.03 Removed stdio.h and string.h. + * : 20.09.2023 0.04 Update the ecc_sdram_enable function according to HWSAN rev0.82. + * : 13.06.2024 0.05 Fix register setting for EDC_CFG, and revise + * : the ecm_lock()/ecm_unlock() process. + * : 27.01.2025 0.06 Remove unused functions. + *****************************************************************************/ + +#include + +#if (ECC_ENABLE == 1) +#include "ecc_enable_v4h.h" +#include "ecm_enable_v4h.h" +#include "mem_io.h" +#include "v4h/lpddr5/boot_init_dram_regdef.h" + +/* Reference:"ECC for DRAM and System RAM" in R19AN0083EJ0082_R-CarV4H_SAN_for_Customer.pdf*/ +void ecc_sdram_enable(void) +{ + NOTICE("ECC for DRAM is enable.\n"); + + uint32_t ecm_tmp; + + /* Before writing to DBSC register, it shall be set to "0x00001234" for the following registers. + After writing to DBSC register, it shall be set to a value other than "0x00001234" for the following registers. */ + mem_write32(DB0SYSCNT0, 0x00001234U); + mem_write32(DB1SYSCNT0, 0x00001234U); + mem_write32(DB0SYSCNT0A, 0x00001234U); + mem_write32(DB1SYSCNT0A, 0x00001234U); + + /* (A) Setting ECM */ + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + /* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers + to inform the external device of the error via the ERROROUT# pin. */ + /* Set bit 3, 1 of ECMERRTGTR0 to 0 and bit 3, 1 of ECMERRCTLR0 to 1. */ + ecm_tmp = mem_read32(ECMERRTGTR0); + ecm_tmp &= ~(0xAU); + ecm_write(ECMERRTGTR0, ecm_tmp); + + ecm_tmp = mem_read32(ECMERRCTLR0); + ecm_tmp |= (0xAU); + ecm_write(ECMERRCTLR0, ecm_tmp); + + /* (B) Setting ECC protection area */ + /* Set the bottom row address of the ECC protection area */ + mem_write32(DB0FSDRAMECCAREA00, ECC_PROT_SIZE00); + mem_write32(DB1FSDRAMECCAREA00, ECC_PROT_SIZE10); + + /* (C) Initialization for DRAM */ + mem_write32(DBSC_DB0ACEN, 0x00000000U); + mem_write32(DBSC_DB1ACEN, 0x00000000U); + + /*** Initialization for DRAM connected to DBS0 Initialize RANK0 in according with the following procedure.***/ + /* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB0FSCONF00A[1:0]. */ + mem_write32(DB0FSCONF00A, 0x0U); + + /* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */ + mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA00); + + /* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */ + mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA00); + + /* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */ + mem_write32(DB0FSCTRL01A, 0x01U); + + /*** Initialization for DRAM connected to DBS1 Initialize RANK0 in according with the following procedure.***/ + /* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB1FSCONF00A[1:0]. */ + mem_write32(DB1FSCONF00A, 0x0U); + + /* [Step2] Set the start row address of the initialization area in DB1FSCONF01A[31:0]. */ + mem_write32(DB1FSCONF01A, START_ECC_INIT_AREA10); + + /* [Step3] Set the end row address of the initialization area in DB1FSCONF02A[31:0]. */ + mem_write32(DB1FSCONF02A, END_ECC_INIT_AREA10); + + /* [Step4] Set 0x1 to DB1FSCTRL01A[0] to start initialization. */ + mem_write32(DB1FSCTRL01A, 0x01U); + + /* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */ + /* [Step5] When DB1FSSTAT01A[0] is set to 0x1, DBS1/RANK0 initialization is complete.*/ + NOTICE("DRAM rank 0 of DBSC0/1 is initializing.......\n"); + do + { + ecm_tmp = 0x01U; + ecm_tmp &= mem_read32(DB0FSSTAT01A); + ecm_tmp &= mem_read32(DB1FSSTAT01A); + } while ((ecm_tmp & 0x01U) != 0x01U); + + /* (D) Setting ECC protection enable */ + /* Enable ECC protection for dbs0/rank0 by setting 0x1 in DB0FSCONFAXI0[8]. */ + ecm_tmp = mem_read32(DB0FSCONFAXI0); + ecm_tmp |= (0x1U << 8U); + mem_write32(DB0FSCONFAXI0, ecm_tmp); + + /* Enable ECC protection for dbs1/rank0 by setting 0x1 in DB1FSCONFAXI0[8]. */ + ecm_tmp = mem_read32(DB1FSCONFAXI0); + ecm_tmp |= (0x1U << 8U); + mem_write32(DB1FSCONFAXI0, ecm_tmp); + + /* (E) System RAM initialization */ + NOTICE("System RAM of DBSC0 is initializing.......\n"); + do + { + ecm_tmp = 0x01U; + ecm_tmp &= mem_read32(DB0FSSTAT00A); + } while (ecm_tmp != 0x1U); + + NOTICE("System RAM of DBSC1 is initializing.......\n"); + do + { + ecm_tmp = 0x01U; + ecm_tmp &= mem_read32(DB1FSSTAT00A); + } while (ecm_tmp != 0x1U); + + /* (F) Setting for ECC error interrupt */ + /* (1) Set the ECC error interrupt for read data. */ + mem_write32(DB0FSINTENB02A, 0xFF00U); + mem_write32(DB1FSINTENB02A, 0xFF00U); + + /* (2) Set the ECC error interrupt during RMW operation for System RAM. */ + ecm_tmp = mem_read32(DB0FSINTENB02A); + ecm_tmp |= 0xFF000000U; + mem_write32(DB0FSINTENB02A, ecm_tmp); + ecm_tmp = mem_read32(DB1FSINTENB02A); + ecm_tmp |= 0xFF000000U; + mem_write32(DB1FSINTENB02A, ecm_tmp); + + /* (3) Set the ECC error interrupt during RMW operation for DRAM. */ + mem_write32(DB0FSINTENB04A, 0xFFFFFFFFU); + mem_write32(DB1FSINTENB04A, 0xFFFFFFFFU); + + /* Lock the ECM registers */ + ecm_lock(); + + /* Enable the write protect of ECM registers */ + mem_write32(DBSC_DB0ACEN, 0x00000001U); + mem_write32(DBSC_DB1ACEN, 0x00000001U); + + /* Enable the access protect for DBSC registers */ + mem_write32(DB0SYSCNT0, 0x00000000U); + mem_write32(DB1SYSCNT0, 0x00000000U); + mem_write32(DB0SYSCNT0A, 0x00000000U); + mem_write32(DB1SYSCNT0A, 0x00000000U); +} +#endif /* ECC_ENABLE == 1 */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h new file mode 100644 index 0000000..4798011 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecc_enable_v4h.h @@ -0,0 +1,111 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC driver header + ******************************************************************************/ + +#ifndef ECC_PROTECT +#define ECC_PROTECT +/* DBSC registers */ +#if defined(__RH850G3K__) +#include "remap_register.h" +#include "mem_io.h" +#include "log.h" +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#define ECM_BASE (BASE_ECC_ADDR) +#else +#if (ECC_ENABLE == 1) +#include "mem_io.h" +#include "log.h" +#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#endif /* ECC_ENABLE == 1 */ +#define ECM_BASE (0xE6250000U) +#endif/* defined(__RH850G3K__) */ + +#if (ECC_ENABLE == 1) +void ecc_sdram_enable(void); + +#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U) +#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U) +#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U) + +#define DBSC_DB0ACEN (DBSC_A_BASE + 0x0200U) +#define DBSC_DB1ACEN (DBSC_DB0ACEN + 0x8000U) +#endif /* ECC_ENABLE == 1 */ + +#define ECMWACNTR (ECM_BASE + 0x0A04U) +#define ECMWPCNTR (ECM_BASE + 0x0A00U) +#if (ECC_ENABLE == 1) +#define ECMERRTGTR0 (ECM_BASE + 0x0200U) +#define ECMERRCTLR0 (ECM_BASE + 0x0000U) +#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U) +#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U) +#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U) +#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U) +#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U) +#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U) +#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U) +#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U) +#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U) +#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U) +#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U) +#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U) +#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U) +#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U) +#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U) +#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U) + +#define DB0FSDRAMECCAREA00 (DBSC_A_BASE + 0x7450U) +#define DB0FSDRAMECCAREA01 (DBSC_A_BASE + 0x7454U) +#define DB1FSDRAMECCAREA00 (DB0FSDRAMECCAREA00 + 0x8000U) +#define DB1FSDRAMECCAREA01 (DB0FSDRAMECCAREA01 + 0x8000U) + +#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U) +#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U) + +/********************* Set by the user *********************/ +/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */ +#define ECC_PROT_SIZE00 (0xCCCCU) +#define ECC_PROT_SIZE01 (0xCCCCU) +#define ECC_PROT_SIZE10 (0xCCCCU) +#define ECC_PROT_SIZE11 (0xCCCCU) + +/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */ +#define START_ECC_INIT_AREA00 (0x00000000U) +#define START_ECC_INIT_AREA10 (0x00000000U) +#define END_ECC_INIT_AREA00 (0x0000CCCBU) +#define END_ECC_INIT_AREA10 (0x0000CCCBU) + +/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */ +#define START_ECC_INIT_AREA01 (0x00000000U) +#define START_ECC_INIT_AREA11 (0x00000000U) +#define END_ECC_INIT_AREA01 (0x0000CCCBU) +#define END_ECC_INIT_AREA11 (0x0000CCCBU) +/*********** Other settings cannot be changed ***************/ +#endif /* ECC_ENABLE == 1 */ + +#endif/* ECC_PROTECT */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c new file mode 100644 index 0000000..cdcdef6 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.c @@ -0,0 +1,260 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM initialize function + ******************************************************************************/ +/****************************************************************************** + * @file ecm_enable_v4h.c + * - Version : 0.01 + * @brief ECM setting. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.01.2025 0.01 First Release + *****************************************************************************/ + +#include +#include "ecm_enable_v4h.h" + +#if (ECM_ERROR_ENABLE == 1) +#include "log.h" +#endif /* ECM_ERROR_ENABLE == 1 */ +#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1)) +#include "ecc_enable_v4h.h" +#include "mem_io.h" +#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +#define ECM_ERR_REG_MAX (40U) + +typedef struct{ + uint32_t phys_addr; /* Physical address of ECM registers. */ + uint32_t value; /* Setting value of ECM registers. */ +} ECM_ERROR_TABLE; +#endif /* ECM_ERROR_ENABLE == 1 */ + +#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1)) +void ecm_unlock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0001U); +} + +void ecm_write(uint32_t adr, uint32_t val) +{ + mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU))); + mem_write32(adr, val); +} + +void ecm_lock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0000U); +} +#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_error_enable(void) +{ + uint32_t reg; + uint32_t loop; + + const ECM_ERROR_TABLE ecmerrctlr_tbl[ECM_ERR_REG_MAX] = { + [0] = {0xE6250000U, 0xFFFFF00FU}, /* ECMERRCTLR0 */ + [1] = {0xE6250004U, 0xFFF8C000U}, /* ECMERRCTLR1 */ + [2] = {0xE6250008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */ + [3] = {0xE625000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */ + [4] = {0xE6250010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */ + [5] = {0xE6250014U, 0xFFFFFFFFU}, /* ECMERRCTLR5 */ + [6] = {0xE6250018U, 0xFF000A80U}, /* ECMERRCTLR6 */ + [7] = {0xE625001CU, 0x6F980FFFU}, /* ECMERRCTLR7 */ + [8] = {0xE6250020U, 0xFFF00000U}, /* ECMERRCTLR8 */ + [9] = {0xE6250024U, 0xFF000000U}, /* ECMERRCTLR9 */ + [10] = {0xE6250028U, 0x557D554FU}, /* ECMERRCTLR10 */ + [11] = {0xE625002CU, 0xFFFC1555U}, /* ECMERRCTLR11 */ + [12] = {0xE6250030U, 0x5557FFFFU}, /* ECMERRCTLR12 */ + [13] = {0xE6250034U, 0x00000055U}, /* ECMERRCTLR13 */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + [14] = {0xE6250040U, 0x3FFFFFFFU}, /* ECMERRCTLR16 */ + [15] = {0xE6250044U, 0x2FFF8CE0U}, /* ECMERRCTLR17 */ + [16] = {0xE6250048U, 0x0EC03FFFU}, /* ECMERRCTLR18 */ + [17] = {0xE625004CU, 0xFFFFFFF9U}, /* ECMERRCTLR19 */ + [18] = {0xE6250050U, 0xFE66667EU}, /* ECMERRCTLR20 */ + [19] = {0xE6250054U, 0xBFE3BE0FU}, /* ECMERRCTLR21 */ + [20] = {0xE6250058U, 0x10000000U}, /* ECMERRCTLR22 */ + [21] = {0xE625005CU, 0x7EF3C008U}, /* ECMERRCTLR23 */ + [22] = {0xE6250060U, 0x7FFE8ADBU}, /* ECMERRCTLR24 */ + [23] = {0xE6250064U, 0xCF807FFFU}, /* ECMERRCTLR25 */ + [24] = {0xE6250068U, 0x7EF3C008U}, /* ECMERRCTLR26 */ + [25] = {0xE625006CU, 0x7FFE8ADBU}, /* ECMERRCTLR27 */ + [26] = {0xE6250070U, 0xCF807FFFU}, /* ECMERRCTLR28 */ + [27] = {0xE6250074U, 0x0073C008U}, /* ECMERRCTLR29 */ + [28] = {0xE6250078U, 0x7FE68A9BU}, /* ECMERRCTLR30 */ + [29] = {0xE625007CU, 0x8C007E00U}, /* ECMERRCTLR31 */ + [30] = {0xE6250080U, 0xCFFFFFFFU}, /* ECMERRCTLR32 */ + [31] = {0xE6250084U, 0x0FFFFFFFU}, /* ECMERRCTLR33 */ + [32] = {0xE6250088U, 0x000003FFU}, /* ECMERRCTLR34 */ + [33] = {0xE625008CU, 0xFFFFFFC0U}, /* ECMERRCTLR35 */ + [34] = {0xE6250090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */ + /* Skip ECMERRCTLR37 setting */ + [35] = {0xE6250098U, 0xFFF000FFU}, /* ECMERRCTLR38 */ + [36] = {0xE625009CU, 0x1FFF0000U}, /* ECMERRCTLR39 */ + [37] = {0xE62500A0U, 0x1FFC7FFFU}, /* ECMERRCTLR40 */ + [38] = {0xE62500A4U, 0xEFFF7FFBU}, /* ECMERRCTLR41 */ + [39] = {0xE62500A8U, 0x3FBFFDFFU}, /* ECMERRCTLR42 */ + }; + +#if (ECMERRTGTR_INTC == 1) + const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = { + [0] = {0xE6250200U, 0xFFFFF00FU}, /* ECMERRTGTR0 */ + [1] = {0xE6250204U, 0xFFF8C000U}, /* ECMERRTGTR1 */ + [2] = {0xE6250208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */ + [3] = {0xE625020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */ + [4] = {0xE6250210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */ + [5] = {0xE6250214U, 0xFFFFFFFFU}, /* ECMERRTGTR5 */ + [6] = {0xE6250218U, 0xFF000A80U}, /* ECMERRTGTR6 */ + [7] = {0xE625021CU, 0x6F980FFFU}, /* ECMERRTGTR7 */ + [8] = {0xE6250220U, 0xFFF00000U}, /* ECMERRTGTR8 */ + [9] = {0xE6250224U, 0xFF000000U}, /* ECMERRTGTR9 */ + [10] = {0xE6250228U, 0x557D554FU}, /* ECMERRTGTR10 */ + [11] = {0xE625022CU, 0xFFFC1555U}, /* ECMERRTGTR11 */ + [12] = {0xE6250230U, 0x5557FFFFU}, /* ECMERRTGTR12 */ + [13] = {0xE6250234U, 0x00000055U}, /* ECMERRTGTR13 */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [14] = {0xE6250240U, 0x3FFFFFFFU}, /* ECMERRTGTR16 */ + [15] = {0xE6250244U, 0x2FFF8CE0U}, /* ECMERRTGTR17 */ + [16] = {0xE6250248U, 0x0EC03FFFU}, /* ECMERRTGTR18 */ + [17] = {0xE625024CU, 0xFFFFFFF9U}, /* ECMERRTGTR19 */ + [18] = {0xE6250250U, 0xFE66667EU}, /* ECMERRTGTR20 */ + [19] = {0xE6250254U, 0xBFE3BE0FU}, /* ECMERRTGTR21 */ + [20] = {0xE6250258U, 0x10000000U}, /* ECMERRTGTR22 */ + [21] = {0xE625025CU, 0x7EF3C008U}, /* ECMERRTGTR23 */ + [22] = {0xE6250260U, 0x7FFE8ADBU}, /* ECMERRTGTR24 */ + [23] = {0xE6250264U, 0xCF807FFFU}, /* ECMERRTGTR25 */ + [24] = {0xE6250268U, 0x7EF3C008U}, /* ECMERRTGTR26 */ + [25] = {0xE625026CU, 0x7FFE8ADBU}, /* ECMERRTGTR27 */ + [26] = {0xE6250270U, 0xCF807FFFU}, /* ECMERRTGTR28 */ + [27] = {0xE6250274U, 0x0073C008U}, /* ECMERRTGTR29 */ + [28] = {0xE6250278U, 0x7FE68A9BU}, /* ECMERRTGTR30 */ + [29] = {0xE625027CU, 0x8C007E00U}, /* ECMERRTGTR31 */ + [30] = {0xE6250280U, 0xCFFFFFFFU}, /* ECMERRTGTR32 */ + [31] = {0xE6250284U, 0x0FFFFFFFU}, /* ECMERRTGTR33 */ + [32] = {0xE6250288U, 0x000003FFU}, /* ECMERRTGTR34 */ + [33] = {0xE625028CU, 0xFFFFFFC0U}, /* ECMERRTGTR35 */ + [34] = {0xE6250290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */ + /* Skip ECMERRTGTR37 setting */ + [35] = {0xE6250298U, 0xFFF000FFU}, /* ECMERRTGTR38 */ + [36] = {0xE625029CU, 0x1FFF0000U}, /* ECMERRTGTR39 */ + [37] = {0xE62502A0U, 0x1FFC7FFFU}, /* ECMERRTGTR40 */ + [38] = {0xE62502A4U, 0xEFFF7FFBU}, /* ECMERRTGTR41 */ + [39] = {0xE62502A8U, 0x3FBFFDFFU}, /* ECMERRTGTR42 */ + }; +#elif (ECMERRTGTR_INTC == 0) + const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = { + [0] = {0xE6250200U, 0x00000000U}, /* ECMERRTGTR0 */ + [1] = {0xE6250204U, 0x00000000U}, /* ECMERRTGTR1 */ + [2] = {0xE6250208U, 0x00000000U}, /* ECMERRTGTR2 */ + [3] = {0xE625020CU, 0x00000000U}, /* ECMERRTGTR3 */ + [4] = {0xE6250210U, 0x00000000U}, /* ECMERRTGTR4 */ + [5] = {0xE6250214U, 0x00000000U}, /* ECMERRTGTR5 */ + [6] = {0xE6250218U, 0x00000000U}, /* ECMERRTGTR6 */ + [7] = {0xE625021CU, 0x00000000U}, /* ECMERRTGTR7 */ + [8] = {0xE6250220U, 0x00000000U}, /* ECMERRTGTR8 */ + [9] = {0xE6250224U, 0x00000000U}, /* ECMERRTGTR9 */ + [10] = {0xE6250228U, 0x00000000U}, /* ECMERRTGTR10 */ + [11] = {0xE625022CU, 0x00000000U}, /* ECMERRTGTR11 */ + [12] = {0xE6250230U, 0x00000000U}, /* ECMERRTGTR12 */ + [13] = {0xE6250234U, 0x00000000U}, /* ECMERRTGTR13 */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [14] = {0xE6250240U, 0x00000000U}, /* ECMERRTGTR16 */ + [15] = {0xE6250244U, 0x00000000U}, /* ECMERRTGTR17 */ + [16] = {0xE6250248U, 0x00000000U}, /* ECMERRTGTR18 */ + [17] = {0xE625024CU, 0x00000000U}, /* ECMERRTGTR19 */ + [18] = {0xE6250250U, 0x00000000U}, /* ECMERRTGTR20 */ + [19] = {0xE6250254U, 0x00000000U}, /* ECMERRTGTR21 */ + [20] = {0xE6250258U, 0x00000000U}, /* ECMERRTGTR22 */ + [21] = {0xE625025CU, 0x00000000U}, /* ECMERRTGTR23 */ + [22] = {0xE6250260U, 0x00000000U}, /* ECMERRTGTR24 */ + [23] = {0xE6250264U, 0x00000000U}, /* ECMERRTGTR25 */ + [24] = {0xE6250268U, 0x00000000U}, /* ECMERRTGTR26 */ + [25] = {0xE625026CU, 0x00000000U}, /* ECMERRTGTR27 */ + [26] = {0xE6250270U, 0x00000000U}, /* ECMERRTGTR28 */ + [27] = {0xE6250274U, 0x00000000U}, /* ECMERRTGTR29 */ + [28] = {0xE6250278U, 0x00000000U}, /* ECMERRTGTR30 */ + [29] = {0xE625027CU, 0x00000000U}, /* ECMERRTGTR31 */ + [30] = {0xE6250280U, 0x00000000U}, /* ECMERRTGTR32 */ + [31] = {0xE6250284U, 0x00000000U}, /* ECMERRTGTR33 */ + [32] = {0xE6250288U, 0x00000000U}, /* ECMERRTGTR34 */ + [33] = {0xE625028CU, 0x00000000U}, /* ECMERRTGTR35 */ + [34] = {0xE6250290U, 0x00000000U}, /* ECMERRTGTR36 */ + /* Skip ECMERRTGTR37 setting */ + [35] = {0xE6250298U, 0x00000000U}, /* ECMERRTGTR38 */ + [36] = {0xE625029CU, 0x00000000U}, /* ECMERRTGTR39 */ + [37] = {0xE62502A0U, 0x00000000U}, /* ECMERRTGTR40 */ + [38] = {0xE62502A4U, 0x00000000U}, /* ECMERRTGTR41 */ + [39] = {0xE62502A8U, 0x00000000U}, /* ECMERRTGTR42 */ + }; +#endif /* ECMERRTGTR_INTC == 1 */ + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + NOTICE("ECMERRCTLR register setting.\n"); + for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++) + { + /* Set ECMERRCTLR registers. */ + reg = mem_read32(ecmerrctlr_tbl[loop].phys_addr); + reg |= ecmerrctlr_tbl[loop].value; + ecm_write(ecmerrctlr_tbl[loop].phys_addr, reg); + + INFO("ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrctlr_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_tbl[loop].phys_addr), + ecmerrctlr_tbl[loop].value); + } + + NOTICE("ECMERRTGTR register setting.\n"); + for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++) + { + /* Set ECMERRTGTR registers. */ + reg = mem_read32(ecmerrtgtr_tbl[loop].phys_addr); + reg |= ecmerrtgtr_tbl[loop].value; + ecm_write(ecmerrtgtr_tbl[loop].phys_addr, reg); + + INFO("ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrtgtr_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_tbl[loop].phys_addr), + ecmerrtgtr_tbl[loop].value); + } + + /* Lock the ECM registers */ + ecm_lock(); +} +/* End of function ecm_error_enable(void) */ +#endif /* ECM_ERROR_ENABLE == 1 */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h new file mode 100644 index 0000000..980b294 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/ecm_enable_v4h.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM driver header + ******************************************************************************/ + +#ifndef ECM_ENABLE +#define ECM_ENABLE + +#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1)) +void ecm_unlock(void); +void ecm_write(uint32_t adr, uint32_t val); +void ecm_lock(void); +#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_error_enable(void); +#endif /* ECM_ERROR_ENABLE == 1 */ + +#endif/* ECM_ENABLE */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/init_dram_tbl_v4h_lp5.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/init_dram_tbl_v4h_lp5.h new file mode 100644 index 0000000..81e90ee --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4h/lpddr5/init_dram_tbl_v4h_lp5.h @@ -0,0 +1,1753 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +#ifndef INIT_DRAM_TBL_V4H_LP5 +#define INIT_DRAM_TBL_V4H_LP5 + +//! @details The address offsets of Data Slice +#define DDR_PHY_SLICE_REGSET_OFS_V4H 0x1000 +//! @details The address offsets of Address Slice +#define DDR_PHY_ADR_V_REGSET_OFS_V4H 0x1200 +//! @details The address offsets of Address Control Slice +#define DDR_PHY_ADR_G_REGSET_OFS_V4H 0x1300 +//! @details The address offsets of PI Register +#define DDR_PI_REGSET_OFS_V4H 0x0800 + +//! @details Number of array elements in Data Slice +#define DDR_PHY_SLICE_REGSET_SIZE_V4H 0x100 +//! @details Number of array elements in Data Slice +#define DDR_PHY_SLICE_REGSET_NUM_V4H 153 +//! @details Number of array elements in Address Slice +#define DDR_PHY_ADR_V_REGSET_NUM_V4H 61 +//! @details Number of array elements in Address Control Slice +#define DDR_PHY_ADR_G_REGSET_NUM_V4H 97 +//! @details Number of array elements in PI Registe +#define DDR_PI_REGSET_NUM_V4H 1381 + +//! @details The setting table of Data Slice for V4H +static const uint32_t DDR_PHY_SLICE_REGSET_V4H[DDR_PHY_SLICE_REGSET_NUM_V4H] = { +/*1000*/ 0x30020370, +/*1001*/ 0x00000000, +/*1002*/ 0x01000002, +/*1003*/ 0x00000000, +/*1004*/ 0x00000000, +/*1005*/ 0x00000000, +/*1006*/ 0x00010300, +/*1007*/ 0x04000100, +/*1008*/ 0x00010000, +/*1009*/ 0x01000000, +/*100A*/ 0x00000000, +/*100B*/ 0x00000000, +/*100C*/ 0x00010000, +/*100D*/ 0x08010000, +/*100E*/ 0x00022003, +/*100F*/ 0x00000000, +/*1010*/ 0x040F0100, +/*1011*/ 0x1404034F, +/*1012*/ 0x04040102, +/*1013*/ 0x04040404, +/*1014*/ 0x00000100, +/*1015*/ 0x00000000, +/*1016*/ 0x00000000, +/*1017*/ 0x000800C0, +/*1018*/ 0x000F18FF, +/*1019*/ 0x00000000, +/*101A*/ 0x00000001, +/*101B*/ 0x00070000, +/*101C*/ 0x0000AAAA, +/*101D*/ 0x00005555, +/*101E*/ 0x0000B5B5, +/*101F*/ 0x00004A4A, +/*1020*/ 0x00005656, +/*1021*/ 0x0000A9A9, +/*1022*/ 0x0000A9A9, +/*1023*/ 0x0000B5B5, +/*1024*/ 0x00000000, +/*1025*/ 0xBFBF0000, +/*1026*/ 0xCCCCF7F7, +/*1027*/ 0x00000000, +/*1028*/ 0x00000000, +/*1029*/ 0x00000000, +/*102A*/ 0x00080815, +/*102B*/ 0x08040000, +/*102C*/ 0x00000004, +/*102D*/ 0x00103000, +/*102E*/ 0x000C0040, +/*102F*/ 0x00200200, +/*1030*/ 0x01010000, +/*1031*/ 0x00000000, +/*1032*/ 0x00000000, +/*1033*/ 0x00000000, +/*1034*/ 0x00000000, +/*1035*/ 0x00000000, +/*1036*/ 0x00000000, +/*1037*/ 0x00000000, +/*1038*/ 0x00000000, +/*1039*/ 0x00000000, +/*103A*/ 0x00000000, +/*103B*/ 0x00000000, +/*103C*/ 0x00000000, +/*103D*/ 0x00000000, +/*103E*/ 0x00000020, +/*103F*/ 0x00000000, +/*1040*/ 0x00000000, +/*1041*/ 0x00000000, +/*1042*/ 0x00000000, +/*1043*/ 0x00000000, +/*1044*/ 0x00000000, +/*1045*/ 0x00000000, +/*1046*/ 0x00000000, +/*1047*/ 0x00000000, +/*1048*/ 0x00000000, +/*1049*/ 0x00000004, +/*104A*/ 0x001F07FF, +/*104B*/ 0x08000303, +/*104C*/ 0x10200080, +/*104D*/ 0x00000006, +/*104E*/ 0x00000401, +/*104F*/ 0x00000000, +/*1050*/ 0x20CEC201, +/*1051*/ 0x00000001, +/*1052*/ 0x00017706, +/*1053*/ 0x01007706, +/*1054*/ 0x00000000, +/*1055*/ 0x008D006D, +/*1056*/ 0x00100001, +/*1057*/ 0x03FF0100, +/*1058*/ 0x00006E01, +/*1059*/ 0x00000301, +/*105A*/ 0x00000000, +/*105B*/ 0x00000000, +/*105C*/ 0x00000000, +/*105D*/ 0x00500050, +/*105E*/ 0x00500050, +/*105F*/ 0x00500050, +/*1060*/ 0x00500050, +/*1061*/ 0x0D000050, +/*1062*/ 0x10100004, +/*1063*/ 0x06102010, +/*1064*/ 0x61619041, +/*1065*/ 0x07097000, +/*1066*/ 0x00644180, +/*1067*/ 0x00803280, +/*1068*/ 0x00808001, +/*1069*/ 0x13010101, +/*106A*/ 0x02000016, +/*106B*/ 0x10001003, +/*106C*/ 0x06093E42, +/*106D*/ 0x0F063D01, +/*106E*/ 0x011700C8, +/*106F*/ 0x04100140, +/*1070*/ 0x00000100, +/*1071*/ 0x000001D1, +/*1072*/ 0x05000068, +/*1073*/ 0x00030402, +/*1074*/ 0x01400000, +/*1075*/ 0x80800300, +/*1076*/ 0x00160010, +/*1077*/ 0x76543210, +/*1078*/ 0x00000008, +/*1079*/ 0x03010301, +/*107A*/ 0x03010301, +/*107B*/ 0x03010301, +/*107C*/ 0x03010301, +/*107D*/ 0x03010301, +/*107E*/ 0x00000000, +/*107F*/ 0x00500050, +/*1080*/ 0x00500050, +/*1081*/ 0x00500050, +/*1082*/ 0x00500050, +/*1083*/ 0x00500050, +/*1084*/ 0x00500050, +/*1085*/ 0x00500050, +/*1086*/ 0x00500050, +/*1087*/ 0x00500050, +/*1088*/ 0x00070087, +/*1089*/ 0x00000000, +/*108A*/ 0x08010007, +/*108B*/ 0x00000000, +/*108C*/ 0x20202020, +/*108D*/ 0x20202020, +/*108E*/ 0x20202020, +/*108F*/ 0x00000000, +/*1090*/ 0x00000000, +/*1091*/ 0x00000000, +/*1092*/ 0x00000000, +/*1093*/ 0x00000000, +/*1094*/ 0x00000000, +/*1095*/ 0x00000000, +/*1096*/ 0x00000000, +/*1097*/ 0x00000000, +/*1098*/ 0x00000000 +}; + +//! @details The setting table of Address Slice for V4H +static const uint32_t DDR_PHY_ADR_V_REGSET_V4H[DDR_PHY_ADR_V_REGSET_NUM_V4H] = { +/*1200*/ 0x00200030, +/*1201*/ 0x00200002, +/*1202*/ 0x76543210, +/*1203*/ 0x00010001, +/*1204*/ 0x06543210, +/*1205*/ 0x03070000, +/*1206*/ 0x00001000, +/*1207*/ 0x00000000, +/*1208*/ 0x00000000, +/*1209*/ 0x00000000, +/*120A*/ 0x00000000, +/*120B*/ 0x00000000, +/*120C*/ 0x00000000, +/*120D*/ 0x00000000, +/*120E*/ 0x00000000, +/*120F*/ 0x0000807F, +/*1210*/ 0x00000001, +/*1211*/ 0x00000003, +/*1212*/ 0x00000000, +/*1213*/ 0x000F0000, +/*1214*/ 0x030C000F, +/*1215*/ 0x00020103, +/*1216*/ 0x0000000F, +/*1217*/ 0x00000100, +/*1218*/ 0x00000000, +/*1219*/ 0x00000000, +/*121A*/ 0x00000000, +/*121B*/ 0x00000000, +/*121C*/ 0x00000000, +/*121D*/ 0x02000400, +/*121E*/ 0x0000002A, +/*121F*/ 0x00000000, +/*1220*/ 0x00000000, +/*1221*/ 0x00000000, +/*1222*/ 0x00000000, +/*1223*/ 0x00200101, +/*1224*/ 0x10002C03, +/*1225*/ 0x00000003, +/*1226*/ 0x00030240, +/*1227*/ 0x00008008, +/*1228*/ 0x00081020, +/*1229*/ 0x01200000, +/*122A*/ 0x00010001, +/*122B*/ 0x00000000, +/*122C*/ 0x00100302, +/*122D*/ 0x003E4208, +/*122E*/ 0x01400140, +/*122F*/ 0x01400140, +/*1230*/ 0x01400140, +/*1231*/ 0x01400140, +/*1232*/ 0x00000100, +/*1233*/ 0x00000100, +/*1234*/ 0x00000100, +/*1235*/ 0x00000100, +/*1236*/ 0x00000000, +/*1237*/ 0x00000000, +/*1238*/ 0x00000000, +/*1239*/ 0x00000000, +/*123A*/ 0x00020580, +/*123B*/ 0x03000040, +/*123C*/ 0x00000000 +}; +//! @details The setting table of Address Control Slice for V4H +static const uint32_t DDR_PHY_ADR_G_REGSET_V4H[DDR_PHY_ADR_G_REGSET_NUM_V4H] = { +/*1300*/ 0x00000000, +/*1301*/ 0x00000100, +/*1302*/ 0x00000001, +/*1303*/ 0x23800000, +/*1304*/ 0x00000000, +/*1305*/ 0x01000101, +/*1306*/ 0x00000000, +/*1307*/ 0x00000001, +/*1308*/ 0x00000000, +/*1309*/ 0x00000000, +/*130A*/ 0x00000000, +/*130B*/ 0x00000000, +/*130C*/ 0x00040101, +/*130D*/ 0x00000000, +/*130E*/ 0x00000000, +/*130F*/ 0x00000064, +/*1310*/ 0x00000000, +/*1311*/ 0x00000000, +/*1312*/ 0x39421B42, +/*1313*/ 0x00010124, +/*1314*/ 0x00520052, +/*1315*/ 0x00000052, +/*1316*/ 0x00000000, +/*1317*/ 0x00000000, +/*1318*/ 0x00010001, +/*1319*/ 0x00000000, +/*131A*/ 0x00000000, +/*131B*/ 0x00010001, +/*131C*/ 0x00000000, +/*131D*/ 0x00000000, +/*131E*/ 0x00010001, +/*131F*/ 0x07030102, +/*1320*/ 0x01030307, +/*1321*/ 0x00000054, +/*1322*/ 0x00004096, +/*1323*/ 0x08200820, +/*1324*/ 0x08200820, +/*1325*/ 0x08200820, +/*1326*/ 0x08200820, +/*1327*/ 0x00000820, +/*1328*/ 0x004103B8, +/*1329*/ 0x0000003F, +/*132A*/ 0x000C0006, +/*132B*/ 0x00000000, +/*132C*/ 0x000004C0, +/*132D*/ 0x00007A12, +/*132E*/ 0x00000208, +/*132F*/ 0x00000000, +/*1330*/ 0x00000000, +/*1331*/ 0x00000000, +/*1332*/ 0x00000000, +/*1333*/ 0x00000000, +/*1334*/ 0x03000000, +/*1335*/ 0x00000000, +/*1336*/ 0x00000000, +/*1337*/ 0x04102002, +/*1338*/ 0x00041020, +/*1339*/ 0x01C98C98, +/*133A*/ 0x3F400000, +/*133B*/ 0x003F3F3F, +/*133C*/ 0x00000000, +/*133D*/ 0x00000000, +/*133E*/ 0x76543210, +/*133F*/ 0x00010198, +/*1340*/ 0x00000007, +/*1341*/ 0x00000000, +/*1342*/ 0x00000000, +/*1343*/ 0x00000000, +/*1344*/ 0x00000002, +/*1345*/ 0x00000000, +/*1346*/ 0x00000000, +/*1347*/ 0x00000000, +/*1348*/ 0x01032380, +/*1349*/ 0x00000100, +/*134A*/ 0x00000000, +/*134B*/ 0x31421342, +/*134C*/ 0x00308000, +/*134D*/ 0x00000080, +/*134E*/ 0x00063F77, +/*134F*/ 0x00000006, +/*1350*/ 0x0000033F, +/*1351*/ 0x00000000, +/*1352*/ 0x0000033F, +/*1353*/ 0x00000000, +/*1354*/ 0x0000033F, +/*1355*/ 0x00000000, +/*1356*/ 0x00033F00, +/*1357*/ 0x00CC0000, +/*1358*/ 0x00033F77, +/*1359*/ 0x00000000, +/*135A*/ 0x00033F00, +/*135B*/ 0x00EE0000, +/*135C*/ 0x00033F00, +/*135D*/ 0x00EE0000, +/*135E*/ 0x00033F00, +/*135F*/ 0x00EE0000, +/*1360*/ 0x00200106 +}; +//! @details The setting table of PI Register for V4H +static const uint32_t DDR_PI_REGSET_V4H[DDR_PI_REGSET_NUM_V4H] = { +/*0800*/ 0x00000D00, +/*0801*/ 0x00010100, +/*0802*/ 0x00640004, +/*0803*/ 0x00000001, +/*0804*/ 0x00000000, +/*0805*/ 0x00000000, +/*0806*/ 0x00000000, +/*0807*/ 0x00000000, +/*0808*/ 0xFFFFFFFF, +/*0809*/ 0x02010000, +/*080A*/ 0x00000003, +/*080B*/ 0x00000005, +/*080C*/ 0x00000002, +/*080D*/ 0x00000000, +/*080E*/ 0x00000101, +/*080F*/ 0x0012080E, +/*0810*/ 0x00000000, +/*0811*/ 0x001E2C0E, +/*0812*/ 0x00000000, +/*0813*/ 0x00030300, +/*0814*/ 0x01010700, +/*0815*/ 0x00000001, +/*0816*/ 0x00000000, +/*0817*/ 0x00000000, +/*0818*/ 0x00000000, +/*0819*/ 0x00000000, +/*081A*/ 0x00000000, +/*081B*/ 0x00000000, +/*081C*/ 0x01000000, +/*081D*/ 0x00002807, +/*081E*/ 0x00000000, +/*081F*/ 0x32000300, +/*0820*/ 0x00000000, +/*0821*/ 0x00000000, +/*0822*/ 0x04022004, +/*0823*/ 0x01040100, +/*0824*/ 0x00010000, +/*0825*/ 0x00000100, +/*0826*/ 0x000000AA, +/*0827*/ 0x00000055, +/*0828*/ 0x000000B5, +/*0829*/ 0x0000004A, +/*082A*/ 0x00000056, +/*082B*/ 0x000000A9, +/*082C*/ 0x000000A9, +/*082D*/ 0x000000B5, +/*082E*/ 0x00000000, +/*082F*/ 0x01000000, +/*0830*/ 0x00030300, +/*0831*/ 0x0000001A, +/*0832*/ 0x000007D0, +/*0833*/ 0x00000300, +/*0834*/ 0x00000000, +/*0835*/ 0x00000000, +/*0836*/ 0x01000000, +/*0837*/ 0x00000101, +/*0838*/ 0x00000000, +/*0839*/ 0x00000000, +/*083A*/ 0x00000000, +/*083B*/ 0x00000200, +/*083C*/ 0x03030300, +/*083D*/ 0x01000000, +/*083E*/ 0x00000000, +/*083F*/ 0x00000100, +/*0840*/ 0x00000003, +/*0841*/ 0x001100EF, +/*0842*/ 0x01A1120B, +/*0843*/ 0x00051400, +/*0844*/ 0x001A0700, +/*0845*/ 0x001101FC, +/*0846*/ 0x00011A00, +/*0847*/ 0x00000000, +/*0848*/ 0x001F0000, +/*0849*/ 0x00000000, +/*084A*/ 0x00000000, +/*084B*/ 0x00051500, +/*084C*/ 0x001103FC, +/*084D*/ 0x00011A00, +/*084E*/ 0x00051500, +/*084F*/ 0x001102FC, +/*0850*/ 0x00011A00, +/*0851*/ 0x00001A00, +/*0852*/ 0x00000000, +/*0853*/ 0x001F0000, +/*0854*/ 0x001100FC, +/*0855*/ 0x00011A00, +/*0856*/ 0x01A1120B, +/*0857*/ 0x001A0701, +/*0858*/ 0x00000000, +/*0859*/ 0x001F0000, +/*085A*/ 0x00000000, +/*085B*/ 0x00000000, +/*085C*/ 0x001100EF, +/*085D*/ 0x01A1120B, +/*085E*/ 0x00051400, +/*085F*/ 0x01910480, +/*0860*/ 0x01821009, +/*0861*/ 0x001F0000, +/*0862*/ 0x00000000, +/*0863*/ 0x00000000, +/*0864*/ 0x00000000, +/*0865*/ 0x00000000, +/*0866*/ 0x001A0700, +/*0867*/ 0x01A11E14, +/*0868*/ 0x001101FC, +/*0869*/ 0x00211A00, +/*086A*/ 0x00051500, +/*086B*/ 0x001103FC, +/*086C*/ 0x00011A00, +/*086D*/ 0x00051500, +/*086E*/ 0x001102FC, +/*086F*/ 0x00011A00, +/*0870*/ 0x00031A00, +/*0871*/ 0x001A0701, +/*0872*/ 0x00000000, +/*0873*/ 0x001F0000, +/*0874*/ 0x00000000, +/*0875*/ 0x00000000, +/*0876*/ 0x01A11E14, +/*0877*/ 0x01A1120B, +/*0878*/ 0x00000000, +/*0879*/ 0x001F0000, +/*087A*/ 0x00000000, +/*087B*/ 0x00000000, +/*087C*/ 0x00000000, +/*087D*/ 0x00000000, +/*087E*/ 0x001100FD, +/*087F*/ 0x00012E00, +/*0880*/ 0x00051700, +/*0881*/ 0x01A1120B, +/*0882*/ 0x001A0701, +/*0883*/ 0x001F0000, +/*0884*/ 0x00000000, +/*0885*/ 0x00000000, +/*0886*/ 0x001100EF, +/*0887*/ 0x01A1120B, +/*0888*/ 0x00051400, +/*0889*/ 0x001A0700, +/*088A*/ 0x001102FD, +/*088B*/ 0x00012E00, +/*088C*/ 0x00000000, +/*088D*/ 0x001F0000, +/*088E*/ 0x00000000, +/*088F*/ 0x00000000, +/*0890*/ 0x00070700, +/*0891*/ 0x00000000, +/*0892*/ 0x01000000, +/*0893*/ 0x00000300, +/*0894*/ 0x17030000, +/*0895*/ 0x00000000, +/*0896*/ 0x00000000, +/*0897*/ 0x00000000, +/*0898*/ 0x0A0A140A, +/*0899*/ 0x10020201, +/*089A*/ 0x332A0002, +/*089B*/ 0x01010000, +/*089C*/ 0x0B000404, +/*089D*/ 0x04030308, +/*089E*/ 0x00010100, +/*089F*/ 0x02020301, +/*08A0*/ 0x01001000, +/*08A1*/ 0x00000034, +/*08A2*/ 0x00000000, +/*08A3*/ 0x00000000, +/*08A4*/ 0x00000000, +/*08A5*/ 0x00000000, +/*08A6*/ 0x55AA55AA, +/*08A7*/ 0x33CC33CC, +/*08A8*/ 0x0FF00FF0, +/*08A9*/ 0x0F0FF0F0, +/*08AA*/ 0x00008E38, +/*08AB*/ 0x00000001, +/*08AC*/ 0x00000002, +/*08AD*/ 0x00020001, +/*08AE*/ 0x00020001, +/*08AF*/ 0x02010201, +/*08B0*/ 0x0000000F, +/*08B1*/ 0x00000000, +/*08B2*/ 0x00000000, +/*08B3*/ 0x00000000, +/*08B4*/ 0x00000000, +/*08B5*/ 0x00000000, +/*08B6*/ 0x00000000, +/*08B7*/ 0x00000000, +/*08B8*/ 0x00000000, +/*08B9*/ 0x00000000, +/*08BA*/ 0x00000000, +/*08BB*/ 0xAAAAA593, +/*08BC*/ 0xA5939999, +/*08BD*/ 0x00000000, +/*08BE*/ 0x00005555, +/*08BF*/ 0x00003333, +/*08C0*/ 0x0000CCCC, +/*08C1*/ 0x00000000, +/*08C2*/ 0x0003FFFF, +/*08C3*/ 0x00003333, +/*08C4*/ 0x0000CCCC, +/*08C5*/ 0x00000000, +/*08C6*/ 0x036DB6DB, +/*08C7*/ 0x00249249, +/*08C8*/ 0x05B6DB6D, +/*08C9*/ 0x00000000, +/*08CA*/ 0x00000000, +/*08CB*/ 0x00000000, +/*08CC*/ 0x00000000, +/*08CD*/ 0x00000000, +/*08CE*/ 0x036DB6DB, +/*08CF*/ 0x00249249, +/*08D0*/ 0x05B6DB6D, +/*08D1*/ 0x00000000, +/*08D2*/ 0x00000000, +/*08D3*/ 0x00000000, +/*08D4*/ 0x00000000, +/*08D5*/ 0x00000000, +/*08D6*/ 0x01000000, +/*08D7*/ 0x00000100, +/*08D8*/ 0x00000000, +/*08D9*/ 0x00000000, +/*08DA*/ 0x00000000, +/*08DB*/ 0x00000000, +/*08DC*/ 0x00000000, +/*08DD*/ 0x00000000, +/*08DE*/ 0x00000000, +/*08DF*/ 0x00000000, +/*08E0*/ 0x00010000, +/*08E1*/ 0x00000000, +/*08E2*/ 0x00000000, +/*08E3*/ 0x00000000, +/*08E4*/ 0x00000000, +/*08E5*/ 0x00000000, +/*08E6*/ 0x00000000, +/*08E7*/ 0x00000000, +/*08E8*/ 0x00000000, +/*08E9*/ 0x00000000, +/*08EA*/ 0x00000000, +/*08EB*/ 0x00000000, +/*08EC*/ 0x00000000, +/*08ED*/ 0x00010000, +/*08EE*/ 0x00000000, +/*08EF*/ 0x00000000, +/*08F0*/ 0x00000000, +/*08F1*/ 0x00000000, +/*08F2*/ 0x00000000, +/*08F3*/ 0x00000000, +/*08F4*/ 0x00000000, +/*08F5*/ 0x00000000, +/*08F6*/ 0x00000000, +/*08F7*/ 0x00000000, +/*08F8*/ 0x00000000, +/*08F9*/ 0x00000000, +/*08FA*/ 0x00080000, +/*08FB*/ 0x00000000, +/*08FC*/ 0x00000000, +/*08FD*/ 0x00000000, +/*08FE*/ 0x00000000, +/*08FF*/ 0x00000000, +/*0900*/ 0x00000000, +/*0901*/ 0x00000000, +/*0902*/ 0x00000000, +/*0903*/ 0x00000000, +/*0904*/ 0x00000000, +/*0905*/ 0x00000000, +/*0906*/ 0x00000000, +/*0907*/ 0x00000000, +/*0908*/ 0x00000000, +/*0909*/ 0x00000000, +/*090A*/ 0x00000000, +/*090B*/ 0x00000000, +/*090C*/ 0x00000000, +/*090D*/ 0x00000000, +/*090E*/ 0x00000000, +/*090F*/ 0x01180400, +/*0910*/ 0x03020100, +/*0911*/ 0x00060504, +/*0912*/ 0x00010100, +/*0913*/ 0x00000008, +/*0914*/ 0x00080000, +/*0915*/ 0x00000001, +/*0916*/ 0x00000000, +/*0917*/ 0x0001AA00, +/*0918*/ 0x00000100, +/*0919*/ 0x00000000, +/*091A*/ 0x00010000, +/*091B*/ 0x00000000, +/*091C*/ 0x00000000, +/*091D*/ 0x00000000, +/*091E*/ 0x00000000, +/*091F*/ 0x00000000, +/*0920*/ 0x00000000, +/*0921*/ 0x00000000, +/*0922*/ 0x00000000, +/*0923*/ 0x00000000, +/*0924*/ 0x00000000, +/*0925*/ 0x00000000, +/*0926*/ 0x00000000, +/*0927*/ 0x00000000, +/*0928*/ 0x00000000, +/*0929*/ 0x00000000, +/*092A*/ 0x00000000, +/*092B*/ 0x00000000, +/*092C*/ 0x00000000, +/*092D*/ 0x00000000, +/*092E*/ 0x00000000, +/*092F*/ 0x00000000, +/*0930*/ 0x00000000, +/*0931*/ 0x00000000, +/*0932*/ 0x00000000, +/*0933*/ 0x00000000, +/*0934*/ 0x00000000, +/*0935*/ 0x00000000, +/*0936*/ 0x00000000, +/*0937*/ 0x00000000, +/*0938*/ 0x00000000, +/*0939*/ 0x00000000, +/*093A*/ 0x00000000, +/*093B*/ 0x00000000, +/*093C*/ 0x00020000, +/*093D*/ 0x00000100, +/*093E*/ 0x00010000, +/*093F*/ 0x0000000B, +/*0940*/ 0x0000001C, +/*0941*/ 0x00000100, +/*0942*/ 0x00000000, +/*0943*/ 0x00000000, +/*0944*/ 0x00000000, +/*0945*/ 0x00000000, +/*0946*/ 0x03010000, +/*0947*/ 0x01000100, +/*0948*/ 0x01020001, +/*0949*/ 0x00010300, +/*094A*/ 0x05000104, +/*094B*/ 0x01060001, +/*094C*/ 0x00010700, +/*094D*/ 0x00000000, +/*094E*/ 0x00000000, +/*094F*/ 0x00010000, +/*0950*/ 0x00000000, +/*0951*/ 0x00000000, +/*0952*/ 0x00000000, +/*0953*/ 0x00000000, +/*0954*/ 0x00000301, +/*0955*/ 0x00000000, +/*0956*/ 0x00000000, +/*0957*/ 0x01010000, +/*0958*/ 0x00000000, +/*0959*/ 0x00000200, +/*095A*/ 0x00000000, +/*095B*/ 0xB8000000, +/*095C*/ 0x010000FF, +/*095D*/ 0x0000FFE8, +/*095E*/ 0x00FFA801, +/*095F*/ 0xFFD80100, +/*0960*/ 0x00007F10, +/*0961*/ 0x00000000, +/*0962*/ 0x00000034, +/*0963*/ 0x0000003D, +/*0964*/ 0x00020079, +/*0965*/ 0x02000200, +/*0966*/ 0x02000204, +/*0967*/ 0x06000C06, +/*0968*/ 0x04040200, +/*0969*/ 0x04100804, +/*096A*/ 0x14090004, +/*096B*/ 0x1C081024, +/*096C*/ 0x0000120C, +/*096D*/ 0x00000015, +/*096E*/ 0x000000CF, +/*096F*/ 0x00000026, +/*0970*/ 0x0000017F, +/*0971*/ 0x00000130, +/*0972*/ 0x04000C2E, +/*0973*/ 0x00000404, +/*0974*/ 0x01080032, +/*0975*/ 0x01080032, +/*0976*/ 0x000F0032, +/*0977*/ 0x00000000, +/*0978*/ 0x00000000, +/*0979*/ 0x00000000, +/*097A*/ 0x00010300, +/*097B*/ 0x00010301, +/*097C*/ 0x03030000, +/*097D*/ 0x00000001, +/*097E*/ 0x00010303, +/*097F*/ 0x00030000, +/*0980*/ 0x0013000C, +/*0981*/ 0x0A060037, +/*0982*/ 0x03030526, +/*0983*/ 0x000C0032, +/*0984*/ 0x0017003D, +/*0985*/ 0x0025004B, +/*0986*/ 0x00010101, +/*0987*/ 0x0000000E, +/*0988*/ 0x00000019, +/*0989*/ 0x010000C8, +/*098A*/ 0x000F000F, +/*098B*/ 0x0007000C, +/*098C*/ 0x001A0100, +/*098D*/ 0x0015001A, +/*098E*/ 0x0100000B, +/*098F*/ 0x00C900C9, +/*0990*/ 0x005100A1, +/*0991*/ 0x29003329, +/*0992*/ 0x33290033, +/*0993*/ 0x0A070600, +/*0994*/ 0x0A07060D, +/*0995*/ 0x0D09070D, +/*0996*/ 0x000C000D, +/*0997*/ 0x00001000, +/*0998*/ 0x00000C00, +/*0999*/ 0x00001000, +/*099A*/ 0x00000C00, +/*099B*/ 0x02001000, +/*099C*/ 0x0002000E, +/*099D*/ 0x00160019, +/*099E*/ 0x1E1A00C8, +/*099F*/ 0x00100004, +/*09A0*/ 0x361C0008, +/*09A1*/ 0x00000000, +/*09A2*/ 0x0000000C, +/*09A3*/ 0x0006000C, +/*09A4*/ 0x0300361C, +/*09A5*/ 0x04001300, +/*09A6*/ 0x000D0019, +/*09A7*/ 0x0000361C, +/*09A8*/ 0x20003300, +/*09A9*/ 0x00000000, +/*09AA*/ 0x02000000, +/*09AB*/ 0x04040802, +/*09AC*/ 0x00060404, +/*09AD*/ 0x0003C34F, +/*09AE*/ 0x05022001, +/*09AF*/ 0x0203000A, +/*09B0*/ 0x04040408, +/*09B1*/ 0xC34F0604, +/*09B2*/ 0x10010005, +/*09B3*/ 0x040A0502, +/*09B4*/ 0x0A080F11, +/*09B5*/ 0x1C0A040A, +/*09B6*/ 0x0022C34F, +/*09B7*/ 0x0C0C1002, +/*09B8*/ 0x00019E0A, +/*09B9*/ 0x0000102C, +/*09BA*/ 0x000002FE, +/*09BB*/ 0x00001DEC, +/*09BC*/ 0x0000185C, +/*09BD*/ 0x0000F398, +/*09BE*/ 0x04000400, +/*09BF*/ 0x03030400, +/*09C0*/ 0x002AF803, +/*09C1*/ 0x00002AF8, +/*09C2*/ 0x0000D6D7, +/*09C3*/ 0x00000003, +/*09C4*/ 0x0000006E, +/*09C5*/ 0x00000016, +/*09C6*/ 0x00004E20, +/*09C7*/ 0x00004E20, +/*09C8*/ 0x00030D40, +/*09C9*/ 0x00000005, +/*09CA*/ 0x000000C8, +/*09CB*/ 0x00000027, +/*09CC*/ 0x00027100, +/*09CD*/ 0x00027100, +/*09CE*/ 0x00186A00, +/*09CF*/ 0x00000028, +/*09D0*/ 0x00000640, +/*09D1*/ 0x01000136, +/*09D2*/ 0x00530040, +/*09D3*/ 0x00010004, +/*09D4*/ 0x00960040, +/*09D5*/ 0x00010004, +/*09D6*/ 0x04B00040, +/*09D7*/ 0x00000318, +/*09D8*/ 0x00280005, +/*09D9*/ 0x05040404, +/*09DA*/ 0x00070603, +/*09DB*/ 0x06030503, +/*09DC*/ 0x0503000D, +/*09DD*/ 0x00640603, +/*09DE*/ 0x06040608, +/*09DF*/ 0x00040604, +/*09E0*/ 0x00260015, +/*09E1*/ 0x01050130, +/*09E2*/ 0x01000100, +/*09E3*/ 0x00020201, +/*09E4*/ 0x04040000, +/*09E5*/ 0x01010104, +/*09E6*/ 0x03020302, +/*09E7*/ 0x00000100, +/*09E8*/ 0x02020101, +/*09E9*/ 0x00000000, +/*09EA*/ 0x09910260, +/*09EB*/ 0x11911600, +/*09EC*/ 0x19A21009, +/*09ED*/ 0x19A10100, +/*09EE*/ 0x19A10201, +/*09EF*/ 0x19A10302, +/*09F0*/ 0x19A10A03, +/*09F1*/ 0x19A10B04, +/*09F2*/ 0x19A10C05, +/*09F3*/ 0x19A10E07, +/*09F4*/ 0x19A10F08, +/*09F5*/ 0x19A1110A, +/*09F6*/ 0x19A1120B, +/*09F7*/ 0x19A1130C, +/*09F8*/ 0x19A1140D, +/*09F9*/ 0x19A00C00, +/*09FA*/ 0x199F0000, +/*09FB*/ 0x199F0000, +/*09FC*/ 0x199F0000, +/*09FD*/ 0x199F0000, +/*09FE*/ 0x01910300, +/*09FF*/ 0x01A21009, +/*0A00*/ 0x019F0000, +/*0A01*/ 0x019F0000, +/*0A02*/ 0x019F0000, +/*0A03*/ 0x019F0000, +/*0A04*/ 0x001140BF, +/*0A05*/ 0x01811009, +/*0A06*/ 0x01850400, +/*0A07*/ 0x01A10C05, +/*0A08*/ 0x01850300, +/*0A09*/ 0x01A10C11, +/*0A0A*/ 0x01850300, +/*0A0B*/ 0x001100BF, +/*0A0C*/ 0x01811009, +/*0A0D*/ 0x01850500, +/*0A0E*/ 0x019F0000, +/*0A0F*/ 0x019F0000, +/*0A10*/ 0x01510001, +/*0A11*/ 0x01D102A0, +/*0A12*/ 0x01E21009, +/*0A13*/ 0x00051900, +/*0A14*/ 0x019F0000, +/*0A15*/ 0x019F0000, +/*0A16*/ 0x019F0000, +/*0A17*/ 0x019F0000, +/*0A18*/ 0x019F0000, +/*0A19*/ 0x019F0000, +/*0A1A*/ 0x019F0000, +/*0A1B*/ 0x019F0000, +/*0A1C*/ 0x019F0000, +/*0A1D*/ 0x019F0000, +/*0A1E*/ 0x019F0000, +/*0A1F*/ 0x01510001, +/*0A20*/ 0x01D10290, +/*0A21*/ 0x01E21009, +/*0A22*/ 0x01510001, +/*0A23*/ 0x01D10000, +/*0A24*/ 0x01E21009, +/*0A25*/ 0x00051800, +/*0A26*/ 0x019F0000, +/*0A27*/ 0x019F0000, +/*0A28*/ 0x019F0000, +/*0A29*/ 0x019F0000, +/*0A2A*/ 0x019F0000, +/*0A2B*/ 0x019F0000, +/*0A2C*/ 0x019F0000, +/*0A2D*/ 0x019F0000, +/*0A2E*/ 0x0011008F, +/*0A2F*/ 0x00910000, +/*0A30*/ 0x01811009, +/*0A31*/ 0x01910040, +/*0A32*/ 0x01A21009, +/*0A33*/ 0x019F0000, +/*0A34*/ 0x01911000, +/*0A35*/ 0x01A21009, +/*0A36*/ 0x01A10100, +/*0A37*/ 0x01A10201, +/*0A38*/ 0x01A10302, +/*0A39*/ 0x01A10A03, +/*0A3A*/ 0x01A10B04, +/*0A3B*/ 0x01A10C05, +/*0A3C*/ 0x01A10E07, +/*0A3D*/ 0x01A10F08, +/*0A3E*/ 0x01A1110A, +/*0A3F*/ 0x01A1120B, +/*0A40*/ 0x01A1130C, +/*0A41*/ 0x01A1140D, +/*0A42*/ 0x01A00C00, +/*0A43*/ 0x01910800, +/*0A44*/ 0x01A21009, +/*0A45*/ 0x019F0000, +/*0A46*/ 0x019F0000, +/*0A47*/ 0x019F0000, +/*0A48*/ 0x0101017F, +/*0A49*/ 0x00010101, +/*0A4A*/ 0x00000000, +/*0A4B*/ 0x00000000, +/*0A4C*/ 0x00000000, +/*0A4D*/ 0x00000000, +/*0A4E*/ 0x01000000, +/*0A4F*/ 0x01000101, +/*0A50*/ 0x00000000, +/*0A51*/ 0x00000000, +/*0A52*/ 0x00050000, +/*0A53*/ 0x00070100, +/*0A54*/ 0x000F0200, +/*0A55*/ 0x00000000, +/*0A56*/ 0x01A10100, +/*0A57*/ 0x01A10201, +/*0A58*/ 0x01A10302, +/*0A59*/ 0x01A00B04, +/*0A5A*/ 0x00210D06, +/*0A5B*/ 0x01A1110A, +/*0A5C*/ 0x01A1140D, +/*0A5D*/ 0x00098000, +/*0A5E*/ 0x019F0000, +/*0A5F*/ 0x019F0000, +/*0A60*/ 0x019F0000, +/*0A61*/ 0x019F0000, +/*0A62*/ 0x019F0000, +/*0A63*/ 0x019F0000, +/*0A64*/ 0x019F0000, +/*0A65*/ 0x019F0000, +/*0A66*/ 0x019F0000, +/*0A67*/ 0x019F0000, +/*0A68*/ 0x019F0000, +/*0A69*/ 0x019F0000, +/*0A6A*/ 0x019F0000, +/*0A6B*/ 0x019F0000, +/*0A6C*/ 0x019F0000, +/*0A6D*/ 0x019F0000, +/*0A6E*/ 0x019F0000, +/*0A6F*/ 0x019F0000, +/*0A70*/ 0x019F0000, +/*0A71*/ 0x019F0000, +/*0A72*/ 0x019F0000, +/*0A73*/ 0x019F0000, +/*0A74*/ 0x019F0000, +/*0A75*/ 0x019F0000, +/*0A76*/ 0x019F0000, +/*0A77*/ 0x019F0000, +/*0A78*/ 0x019F0000, +/*0A79*/ 0x019F0000, +/*0A7A*/ 0x019F0000, +/*0A7B*/ 0x019F0000, +/*0A7C*/ 0x019F0000, +/*0A7D*/ 0x019F0000, +/*0A7E*/ 0x019F0000, +/*0A7F*/ 0x019F0000, +/*0A80*/ 0x019F0000, +/*0A81*/ 0x019F0000, +/*0A82*/ 0x019F0000, +/*0A83*/ 0x019F0000, +/*0A84*/ 0x019F0000, +/*0A85*/ 0x019F0000, +/*0A86*/ 0x019F0000, +/*0A87*/ 0x019F0000, +/*0A88*/ 0x019F0000, +/*0A89*/ 0x019F0000, +/*0A8A*/ 0x019F0000, +/*0A8B*/ 0x019F0000, +/*0A8C*/ 0x019F0000, +/*0A8D*/ 0x019F0000, +/*0A8E*/ 0x019F0000, +/*0A8F*/ 0x019F0000, +/*0A90*/ 0x019F0000, +/*0A91*/ 0x019F0000, +/*0A92*/ 0x01A10100, +/*0A93*/ 0x01A10201, +/*0A94*/ 0x01A10302, +/*0A95*/ 0x01A10A03, +/*0A96*/ 0x01A10B04, +/*0A97*/ 0x00210D06, +/*0A98*/ 0x01A1110A, +/*0A99*/ 0x00000000, +/*0A9A*/ 0x01A1140D, +/*0A9B*/ 0x00000000, +/*0A9C*/ 0x00000000, +/*0A9D*/ 0x00000000, +/*0A9E*/ 0x01A1120B, +/*0A9F*/ 0x000A0000, +/*0AA0*/ 0x001F0000, +/*0AA1*/ 0x001F0000, +/*0AA2*/ 0x001F0000, +/*0AA3*/ 0x001F0000, +/*0AA4*/ 0x001F0000, +/*0AA5*/ 0x001F0000, +/*0AA6*/ 0x000A0000, +/*0AA7*/ 0x01061300, +/*0AA8*/ 0x00000000, +/*0AA9*/ 0x00000000, +/*0AAA*/ 0x00061180, +/*0AAB*/ 0x000612C0, +/*0AAC*/ 0x00000000, +/*0AAD*/ 0x00000000, +/*0AAE*/ 0x001F0000, +/*0AAF*/ 0x00000000, +/*0AB0*/ 0x00000000, +/*0AB1*/ 0x00000000, +/*0AB2*/ 0x00000000, +/*0AB3*/ 0x00000000, +/*0AB4*/ 0x00000000, +/*0AB5*/ 0x00000000, +/*0AB6*/ 0x00000000, +/*0AB7*/ 0x00000000, +/*0AB8*/ 0x00000000, +/*0AB9*/ 0x00000000, +/*0ABA*/ 0x01811009, +/*0ABB*/ 0x0011EFAF, +/*0ABC*/ 0x01A1120B, +/*0ABD*/ 0x001F0000, +/*0ABE*/ 0x001F0000, +/*0ABF*/ 0x001F0000, +/*0AC0*/ 0x001F0000, +/*0AC1*/ 0x001F0000, +/*0AC2*/ 0x001F0000, +/*0AC3*/ 0x001100BF, +/*0AC4*/ 0x01A1120B, +/*0AC5*/ 0x080D0000, +/*0AC6*/ 0x001F0000, +/*0AC7*/ 0x001F0000, +/*0AC8*/ 0x001F0000, +/*0AC9*/ 0x080C0000, +/*0ACA*/ 0x001F0000, +/*0ACB*/ 0x001F0000, +/*0ACC*/ 0x001F0000, +/*0ACD*/ 0x001F0000, +/*0ACE*/ 0x001F0000, +/*0ACF*/ 0x001F0000, +/*0AD0*/ 0x001F0000, +/*0AD1*/ 0x001F0000, +/*0AD2*/ 0x001F0200, +/*0AD3*/ 0x001F0200, +/*0AD4*/ 0x001F0200, +/*0AD5*/ 0x001F0200, +/*0AD6*/ 0x001F0200, +/*0AD7*/ 0x001F0200, +/*0AD8*/ 0x001F0200, +/*0AD9*/ 0x001F0200, +/*0ADA*/ 0x001F0200, +/*0ADB*/ 0x001F0200, +/*0ADC*/ 0x001F0200, +/*0ADD*/ 0x001F0200, +/*0ADE*/ 0x001100EF, +/*0ADF*/ 0x01A1120B, +/*0AE0*/ 0x001F0000, +/*0AE1*/ 0x00000000, +/*0AE2*/ 0x00000000, +/*0AE3*/ 0x00000000, +/*0AE4*/ 0x00000000, +/*0AE5*/ 0x00000000, +/*0AE6*/ 0x00000000, +/*0AE7*/ 0x00000000, +/*0AE8*/ 0x00000000, +/*0AE9*/ 0x00000000, +/*0AEA*/ 0x00000000, +/*0AEB*/ 0x00000000, +/*0AEC*/ 0x00000000, +/*0AED*/ 0x00000000, +/*0AEE*/ 0x01A1120B, +/*0AEF*/ 0x001F0000, +/*0AF0*/ 0x00000000, +/*0AF1*/ 0x00000000, +/*0AF2*/ 0x00000000, +/*0AF3*/ 0x00000000, +/*0AF4*/ 0x00000000, +/*0AF5*/ 0x00000000, +/*0AF6*/ 0x00000000, +/*0AF7*/ 0x00000000, +/*0AF8*/ 0x00000000, +/*0AF9*/ 0x00000000, +/*0AFA*/ 0x00000000, +/*0AFB*/ 0x00000000, +/*0AFC*/ 0x00000000, +/*0AFD*/ 0x00000000, +/*0AFE*/ 0x001100EF, +/*0AFF*/ 0x01A1120B, +/*0B00*/ 0x001F0000, +/*0B01*/ 0x00000000, +/*0B02*/ 0x00000000, +/*0B03*/ 0x00000000, +/*0B04*/ 0x00000000, +/*0B05*/ 0x00000000, +/*0B06*/ 0x00000000, +/*0B07*/ 0x00000000, +/*0B08*/ 0x00000000, +/*0B09*/ 0x00000000, +/*0B0A*/ 0x00000000, +/*0B0B*/ 0x00000000, +/*0B0C*/ 0x00000000, +/*0B0D*/ 0x00000000, +/*0B0E*/ 0x00211F14, +/*0B0F*/ 0x00212014, +/*0B10*/ 0x00212116, +/*0B11*/ 0x00212217, +/*0B12*/ 0x001F0000, +/*0B13*/ 0x00000000, +/*0B14*/ 0x00000000, +/*0B15*/ 0x00000000, +/*0B16*/ 0x00000000, +/*0B17*/ 0x00000000, +/*0B18*/ 0x001A85FF, +/*0B19*/ 0x00051E00, +/*0B1A*/ 0x001F0000, +/*0B1B*/ 0x00000000, +/*0B1C*/ 0x00211F14, +/*0B1D*/ 0x00212015, +/*0B1E*/ 0x00212116, +/*0B1F*/ 0x00212217, +/*0B20*/ 0x01A1120B, +/*0B21*/ 0x001F0000, +/*0B22*/ 0x00000000, +/*0B23*/ 0x00000000, +/*0B24*/ 0x00000000, +/*0B25*/ 0x00000000, +/*0B26*/ 0x0031FFBF, +/*0B27*/ 0x01A11009, +/*0B28*/ 0x01A10E07, +/*0B29*/ 0x01A10F08, +/*0B2A*/ 0x003100BF, +/*0B2B*/ 0x01A11009, +/*0B2C*/ 0x00051800, +/*0B2D*/ 0x003F0000, +/*0B2E*/ 0x003F0000, +/*0B2F*/ 0x003F0000, +/*0B30*/ 0x003F0000, +/*0B31*/ 0x003F0000, +/*0B32*/ 0x003F0000, +/*0B33*/ 0x003F0000, +/*0B34*/ 0x003F0000, +/*0B35*/ 0x003F0000, +/*0B36*/ 0x0031FFBF, +/*0B37*/ 0x01A11009, +/*0B38*/ 0x01A10E07, +/*0B39*/ 0x01A10F08, +/*0B3A*/ 0x003100BF, +/*0B3B*/ 0x01A11009, +/*0B3C*/ 0x00051800, +/*0B3D*/ 0x003F0000, +/*0B3E*/ 0x003F0000, +/*0B3F*/ 0x003F0000, +/*0B40*/ 0x003F0000, +/*0B41*/ 0x003F0000, +/*0B42*/ 0x003F0000, +/*0B43*/ 0x003F0000, +/*0B44*/ 0x003F0000, +/*0B45*/ 0x003F0000, +/*0B46*/ 0x08084340, +/*0B47*/ 0x0011FFFF, +/*0B48*/ 0x2011FFFB, +/*0B49*/ 0x00012E00, +/*0B4A*/ 0x001100EF, +/*0B4B*/ 0x01A1120B, +/*0B4C*/ 0x001F0000, +/*0B4D*/ 0x001F0000, +/*0B4E*/ 0x001F0000, +/*0B4F*/ 0x001F0000, +/*0B50*/ 0x001F0000, +/*0B51*/ 0x001F0000, +/*0B52*/ 0x001F0000, +/*0B53*/ 0x001F0000, +/*0B54*/ 0x001F0000, +/*0B55*/ 0x001F0000, +/*0B56*/ 0x001F0000, +/*0B57*/ 0x001F0000, +/*0B58*/ 0x001F0000, +/*0B59*/ 0x001F0000, +/*0B5A*/ 0x001F0000, +/*0B5B*/ 0x001F0000, +/*0B5C*/ 0x001F0000, +/*0B5D*/ 0x001F0000, +/*0B5E*/ 0x083E4340, +/*0B5F*/ 0x00212E00, +/*0B60*/ 0x01A1120B, +/*0B61*/ 0x003F0000, +/*0B62*/ 0x003F0000, +/*0B63*/ 0x003F0000, +/*0B64*/ 0x003F0000, +/*0B65*/ 0x003F0000, +/*0B66*/ 0x003F0000, +/*0B67*/ 0x08201020, +/*0B68*/ 0x28100020, +/*0B69*/ 0x08083020, +/*0B6A*/ 0x08400020, +/*0B6B*/ 0x08402020, +/*0B6C*/ 0x08483020, +/*0B6D*/ 0x10083020, +/*0B6E*/ 0x20180020, +/*0B6F*/ 0x30480020, +/*0B70*/ 0x78880020, +/*0B71*/ 0x488010E0, +/*0B72*/ 0x494B0000, +/*0B73*/ 0x49089080, +/*0B74*/ 0x49080000, +/*0B75*/ 0x490011C0, +/*0B76*/ 0x0A000020, +/*0B77*/ 0x08000020, +/*0B78*/ 0x08000020, +/*0B79*/ 0x08000020, +/*0B7A*/ 0x08000020, +/*0B7B*/ 0x08000020, +/*0B7C*/ 0x08000020, +/*0B7D*/ 0x08000020, +/*0B7E*/ 0x08000020, +/*0B7F*/ 0x08000020, +/*0B80*/ 0x08000020, +/*0B81*/ 0x08000020, +/*0B82*/ 0x08000020, +/*0B83*/ 0x08000020, +/*0B84*/ 0x08000020, +/*0B85*/ 0x08000020, +/*0B86*/ 0x08000020, +/*0B87*/ 0x08000020, +/*0B88*/ 0x08000020, +/*0B89*/ 0x08000020, +/*0B8A*/ 0x08000020, +/*0B8B*/ 0x08000020, +/*0B8C*/ 0x08000020, +/*0B8D*/ 0x08000020, +/*0B8E*/ 0x08000020, +/*0B8F*/ 0x08000020, +/*0B90*/ 0x08000020, +/*0B91*/ 0x08000020, +/*0B92*/ 0x08000020, +/*0B93*/ 0x08000020, +/*0B94*/ 0x001100FF, +/*0B95*/ 0x01810302, +/*0B96*/ 0x001100DF, +/*0B97*/ 0x00010D06, +/*0B98*/ 0x001100EF, +/*0B99*/ 0x01A1120B, +/*0B9A*/ 0x001F0000, +/*0B9B*/ 0x001F0000, +/*0B9C*/ 0x001F0000, +/*0B9D*/ 0x001F0000, +/*0B9E*/ 0x001F0000, +/*0B9F*/ 0x001F0000, +/*0BA0*/ 0x001F0000, +/*0BA1*/ 0x001F0000, +/*0BA2*/ 0x001F0000, +/*0BA3*/ 0x001F0000, +/*0BA4*/ 0x00010D06, +/*0BA5*/ 0x01810302, +/*0BA6*/ 0x0181160E, +/*0BA7*/ 0x001F0000, +/*0BA8*/ 0x001F0000, +/*0BA9*/ 0x001F0000, +/*0BAA*/ 0x001F0000, +/*0BAB*/ 0x001F0000, +/*0BAC*/ 0x081A52FD, +/*0BAD*/ 0x001A12FF, +/*0BAE*/ 0x00051A00, +/*0BAF*/ 0x001A13FF, +/*0BB0*/ 0x00051B00, +/*0BB1*/ 0x001F13FF, +/*0BB2*/ 0x081A52FD, +/*0BB3*/ 0x001A12FF, +/*0BB4*/ 0x00051A00, +/*0BB5*/ 0x001A13FF, +/*0BB6*/ 0x00051B00, +/*0BB7*/ 0x001F13FF, +/*0BB8*/ 0x081A52FD, +/*0BB9*/ 0x001A12FF, +/*0BBA*/ 0x00051A00, +/*0BBB*/ 0x001A13FF, +/*0BBC*/ 0x00051B00, +/*0BBD*/ 0x001F13FF, +/*0BBE*/ 0x00032300, +/*0BBF*/ 0x00032400, +/*0BC0*/ 0x001F0000, +/*0BC1*/ 0x001F0000, +/*0BC2*/ 0x00800000, +/*0BC3*/ 0x0031FFBF, +/*0BC4*/ 0x01A11009, +/*0BC5*/ 0x01A10E07, +/*0BC6*/ 0x01A10F08, +/*0BC7*/ 0x003100BF, +/*0BC8*/ 0x01A11009, +/*0BC9*/ 0x00051800, +/*0BCA*/ 0x003F0000, +/*0BCB*/ 0x003F0000, +/*0BCC*/ 0x003F0000, +/*0BCD*/ 0x003F0000, +/*0BCE*/ 0x003F0000, +/*0BCF*/ 0x003F0000, +/*0BD0*/ 0x003F0000, +/*0BD1*/ 0x003F0000, +/*0BD2*/ 0x00800000, +/*0BD3*/ 0x0031FFBF, +/*0BD4*/ 0x01A11009, +/*0BD5*/ 0x01A10E07, +/*0BD6*/ 0x01A10F08, +/*0BD7*/ 0x003100BF, +/*0BD8*/ 0x01A11009, +/*0BD9*/ 0x00051800, +/*0BDA*/ 0x003F0000, +/*0BDB*/ 0x003F0000, +/*0BDC*/ 0x003F0000, +/*0BDD*/ 0x003F0000, +/*0BDE*/ 0x003F0000, +/*0BDF*/ 0x003F0000, +/*0BE0*/ 0x003F0000, +/*0BE1*/ 0x003F0000, +/*0BE2*/ 0x081100DF, +/*0BE3*/ 0x08010D06, +/*0BE4*/ 0x0011000F, +/*0BE5*/ 0x0181160E, +/*0BE6*/ 0x001100EF, +/*0BE7*/ 0x01A1120B, +/*0BE8*/ 0x001F0000, +/*0BE9*/ 0x001F0000, +/*0BEA*/ 0x001F0000, +/*0BEB*/ 0x009C0000, +/*0BEC*/ 0x08010D06, +/*0BED*/ 0x0181160E, +/*0BEE*/ 0x01A1120B, +/*0BEF*/ 0x001F0000, +/*0BF0*/ 0x001F0000, +/*0BF1*/ 0x001F0000, +/*0BF2*/ 0x00000000, +/*0BF3*/ 0x00000000, +/*0BF4*/ 0x00000000, +/*0BF5*/ 0x00000000, +/*0BF6*/ 0x00000000, +/*0BF7*/ 0x00000000, +/*0BF8*/ 0x00000000, +/*0BF9*/ 0x00000000, +/*0BFA*/ 0x00000000, +/*0BFB*/ 0x11910048, +/*0BFC*/ 0x09910060, +/*0BFD*/ 0x19A21009, +/*0BFE*/ 0x19A10100, +/*0BFF*/ 0x19A10201, +/*0C00*/ 0x19A10302, +/*0C01*/ 0x19A10A03, +/*0C02*/ 0x19A10B04, +/*0C03*/ 0x18051C00, +/*0C04*/ 0x19A1110A, +/*0C05*/ 0x19A1120B, +/*0C06*/ 0x19A1130C, +/*0C07*/ 0x19A1140D, +/*0C08*/ 0x19A1160E, +/*0C09*/ 0x181140BF, +/*0C0A*/ 0x19A11009, +/*0C0B*/ 0x19A10C05, +/*0C0C*/ 0x19A00C00, +/*0C0D*/ 0x19A10E07, +/*0C0E*/ 0x19A10F08, +/*0C0F*/ 0x19910280, +/*0C10*/ 0x19A21009, +/*0C11*/ 0x18051000, +/*0C12*/ 0x18861101, +/*0C13*/ 0x181F0000, +/*0C14*/ 0x18000000, +/*0C15*/ 0x18000000, +/*0C16*/ 0x18000000, +/*0C17*/ 0x18000000, +/*0C18*/ 0x18000000, +/*0C19*/ 0x18000000, +/*0C1A*/ 0x18000000, +/*0C1B*/ 0x18000000, +/*0C1C*/ 0x18000000, +/*0C1D*/ 0x18000000, +/*0C1E*/ 0x18000000, +/*0C1F*/ 0x18000000, +/*0C20*/ 0x18000000, +/*0C21*/ 0x18000000, +/*0C22*/ 0x18000000, +/*0C23*/ 0x18861100, +/*0C24*/ 0x19A11009, +/*0C25*/ 0x101B0001, +/*0C26*/ 0x181B0100, +/*0C27*/ 0x18000500, +/*0C28*/ 0x181B0200, +/*0C29*/ 0x00000000, +/*0C2A*/ 0x181B0600, +/*0C2B*/ 0x181B0C00, +/*0C2C*/ 0x181B0100, +/*0C2D*/ 0x181B0200, +/*0C2E*/ 0x181B0300, +/*0C2F*/ 0x181B0400, +/*0C30*/ 0x181F0000, +/*0C31*/ 0x18000000, +/*0C32*/ 0x18000000, +/*0C33*/ 0x18000000, +/*0C34*/ 0x18000000, +/*0C35*/ 0x18000000, +/*0C36*/ 0x18000000, +/*0C37*/ 0x18000000, +/*0C38*/ 0x18000000, +/*0C39*/ 0x18000000, +/*0C3A*/ 0x18000000, +/*0C3B*/ 0x18000000, +/*0C3C*/ 0x18000000, +/*0C3D*/ 0x18000000, +/*0C3E*/ 0x18000000, +/*0C3F*/ 0x18000000, +/*0C40*/ 0x18000000, +/*0C41*/ 0x004B1040, +/*0C42*/ 0x001011C0, +/*0C43*/ 0x00089080, +/*0C44*/ 0x000811C0, +/*0C45*/ 0x040811C0, +/*0C46*/ 0x02000000, +/*0C47*/ 0x00000000, +/*0C48*/ 0x00000000, +/*0C49*/ 0x00000000, +/*0C4A*/ 0x00000000, +/*0C4B*/ 0x00000000, +/*0C4C*/ 0x00000000, +/*0C4D*/ 0x00000000, +/*0C4E*/ 0x00000000, +/*0C4F*/ 0x00000000, +/*0C50*/ 0x00000000, +/*0C51*/ 0x00000000, +/*0C52*/ 0x00000000, +/*0C53*/ 0x00000000, +/*0C54*/ 0x00000000, +/*0C55*/ 0x00000000, +/*0C56*/ 0x00000000, +/*0C57*/ 0x5F407FAA, +/*0C58*/ 0x007B776F, +/*0C59*/ 0x4AB555AA, +/*0C5A*/ 0xB5A9A956, +/*0C5B*/ 0x9F80BFAA, +/*0C5C*/ 0x00BBB7AF, +/*0C5D*/ 0x00000000, +/*0C5E*/ 0x00000000, +/*0C5F*/ 0x00000000, +/*0C60*/ 0x00000000, +/*0C61*/ 0x00000000, +/*0C62*/ 0x00000000, +/*0C63*/ 0x00000000, +/*0C64*/ 0x00000000, +/*0C65*/ 0x00002AF8, +/*0C66*/ 0x0000D6D7, +/*0C67*/ 0x0000006E, +/*0C68*/ 0x00000000, +/*0C69*/ 0x00000000, +/*0C6A*/ 0x00000000, +/*0C6B*/ 0x00000000, +/*0C6C*/ 0x00000000, +/*0C6D*/ 0x00000000, +/*0C6E*/ 0x00000000, +/*0C6F*/ 0x00000000, +/*0C70*/ 0x00000000, +/*0C71*/ 0x00000000, +/*0C72*/ 0x00000000, +/*0C73*/ 0x00000000, +/*0C74*/ 0x00000000, +/*0C75*/ 0x0000000E, +/*0C76*/ 0x00000019, +/*0C77*/ 0x000000C8, +/*0C78*/ 0x00000001, +/*0C79*/ 0x00000001, +/*0C7A*/ 0x00000003, +/*0C7B*/ 0x00000007, +/*0C7C*/ 0x00000007, +/*0C7D*/ 0x00000009, +/*0C7E*/ 0x00000001, +/*0C7F*/ 0x00000001, +/*0C80*/ 0x00000003, +/*0C81*/ 0x00000001, +/*0C82*/ 0x00000001, +/*0C83*/ 0x00000003, +/*0C84*/ 0x0000006E, +/*0C85*/ 0x000000C8, +/*0C86*/ 0x00000640, +/*0C87*/ 0x00000001, +/*0C88*/ 0x00000001, +/*0C89*/ 0x00000003, +/*0C8A*/ 0x00000002, +/*0C8B*/ 0x00000004, +/*0C8C*/ 0x0000001C, +/*0C8D*/ 0x00000007, +/*0C8E*/ 0x0000000B, +/*0C8F*/ 0x00000051, +/*0C90*/ 0x0000000C, +/*0C91*/ 0x00000015, +/*0C92*/ 0x000000A1, +/*0C93*/ 0x00000003, +/*0C94*/ 0x00000000, +/*0C95*/ 0x0000000C, +/*0C96*/ 0x00000000, +/*0C97*/ 0x00000000, +/*0C98*/ 0x00000000, +/*0C99*/ 0x0000000F, +/*0C9A*/ 0x0000000F, +/*0C9B*/ 0x0000000F, +/*0C9C*/ 0x00002AF9, +/*0C9D*/ 0x00002AF9, +/*0C9E*/ 0x00002AF9, +/*0C9F*/ 0x00000034, +/*0CA0*/ 0x0000001E, +/*0CA1*/ 0x0000003C, +/*0CA2*/ 0x00000000, +/*0CA3*/ 0x00000000, +/*0CA4*/ 0x00000000, +/*0CA5*/ 0x00000000, +/*0CA6*/ 0x00000000, +/*0CA7*/ 0x00000000, +/*0CA8*/ 0x00000000, +/*0CA9*/ 0x00000000, +/*0CAA*/ 0x00000000, +/*0CAB*/ 0x00000000, +/*0CAC*/ 0x00000000, +/*0CAD*/ 0x00000000, +/*0CAE*/ 0x00000000, +/*0CAF*/ 0x00000000, +/*0CB0*/ 0x00000000, +/*0CB1*/ 0x00000000, +/*0CB2*/ 0x00000000, +/*0CB3*/ 0x00000000, +/*0CB4*/ 0x00000000, +/*0CB5*/ 0x00000000, +/*0CB6*/ 0x00000000, +/*0CB7*/ 0x00000000, +/*0CB8*/ 0x00000000, +/*0CB9*/ 0x00000000, +/*0CBA*/ 0x00000000, +/*0CBB*/ 0x00000000, +/*0CBC*/ 0x00000000, +/*0CBD*/ 0x00000000, +/*0CBE*/ 0x00000000, +/*0CBF*/ 0x00000000, +/*0CC0*/ 0x00000000, +/*0CC1*/ 0x00000000, +/*0CC2*/ 0x00000000, +/*0CC3*/ 0x00000000, +/*0CC4*/ 0x00000000, +/*0CC5*/ 0x00000000, +/*0CC6*/ 0x00000000, +/*0CC7*/ 0x00000000, +/*0CC8*/ 0x00000000, +/*0CC9*/ 0x00000000, +/*0CCA*/ 0x00000000, +/*0CCB*/ 0x00000000, +/*0CCC*/ 0x00000000, +/*0CCD*/ 0x00000000, +/*0CCE*/ 0x00000000, +/*0CCF*/ 0x00000000, +/*0CD0*/ 0x00000000, +/*0CD1*/ 0x00000000, +/*0CD2*/ 0x00000000, +/*0CD3*/ 0x00000000, +/*0CD4*/ 0x000000C0, +/*0CD5*/ 0x00000000, +/*0CD6*/ 0x00000000, +/*0CD7*/ 0x55550000, +/*0CD8*/ 0x00003C5A, +/*0CD9*/ 0x00000000, +/*0CDA*/ 0x00000000, +/*0CDB*/ 0x00000000, +/*0CDC*/ 0x00000000, +/*0CDD*/ 0x00000000, +/*0CDE*/ 0x00000000, +/*0CDF*/ 0x00000000, +/*0CE0*/ 0x00000000, +/*0CE1*/ 0x00000000, +/*0CE2*/ 0x00000000, +/*0CE3*/ 0x00000000, +/*0CE4*/ 0x00000000, +/*0CE5*/ 0x00000000, +/*0CE6*/ 0x00000000, +/*0CE7*/ 0x00000000, +/*0CE8*/ 0x00000000, +/*0CE9*/ 0x00000000, +/*0CEA*/ 0x00000000, +/*0CEB*/ 0x00000000, +/*0CEC*/ 0x00000000, +/*0CED*/ 0x00000000, +/*0CEE*/ 0x00000000, +/*0CEF*/ 0x00000000, +/*0CF0*/ 0x00000000, +/*0CF1*/ 0x00000000, +/*0CF2*/ 0x00000000, +/*0CF3*/ 0x00000000, +/*0CF4*/ 0x00000000, +/*0CF5*/ 0x00000000, +/*0CF6*/ 0x00000000, +/*0CF7*/ 0x00000000, +/*0CF8*/ 0x00000000, +/*0CF9*/ 0x00000000, +/*0CFA*/ 0x00000000, +/*0CFB*/ 0x00000000, +/*0CFC*/ 0x00000000, +/*0CFD*/ 0x00000000, +/*0CFE*/ 0x00000000, +/*0CFF*/ 0x00000000, +/*0D00*/ 0x00000000, +/*0D01*/ 0x00000000, +/*0D02*/ 0x00000000, +/*0D03*/ 0x00000000, +/*0D04*/ 0x00000000, +/*0D05*/ 0x00000000, +/*0D06*/ 0x00000000, +/*0D07*/ 0x00000000, +/*0D08*/ 0x00000000, +/*0D09*/ 0x00000000, +/*0D0A*/ 0x00000000, +/*0D0B*/ 0x00D60000, +/*0D0C*/ 0x50005000, +/*0D0D*/ 0x803E0050, +/*0D0E*/ 0x00000200, +/*0D0F*/ 0x00000000, +/*0D10*/ 0x00000000, +/*0D11*/ 0x00007800, +/*0D12*/ 0x00000000, +/*0D13*/ 0x00000000, +/*0D14*/ 0x00000000, +/*0D15*/ 0x00C61110, +/*0D16*/ 0x2C002834, +/*0D17*/ 0x0C06002C, +/*0D18*/ 0x00000200, +/*0D19*/ 0x00000000, +/*0D1A*/ 0x00000000, +/*0D1B*/ 0x00007800, +/*0D1C*/ 0x00000000, +/*0D1D*/ 0x00000000, +/*0D1E*/ 0x00000000, +/*0D1F*/ 0x00C6BBB0, +/*0D20*/ 0x2C002834, +/*0D21*/ 0x0C06002C, +/*0D22*/ 0x00000200, +/*0D23*/ 0x00000000, +/*0D24*/ 0x00000000, +/*0D25*/ 0x00007800, +/*0D26*/ 0x00000000, +/*0D27*/ 0x00000000, +/*0D28*/ 0x00000000, +/*0D29*/ 0x00D60000, +/*0D2A*/ 0x50005000, +/*0D2B*/ 0x803E0050, +/*0D2C*/ 0x00000200, +/*0D2D*/ 0x00000000, +/*0D2E*/ 0x00000000, +/*0D2F*/ 0x00007800, +/*0D30*/ 0x00000000, +/*0D31*/ 0x00000000, +/*0D32*/ 0x00000000, +/*0D33*/ 0x00C61110, +/*0D34*/ 0x2C002834, +/*0D35*/ 0x082E002C, +/*0D36*/ 0x00000200, +/*0D37*/ 0x00000000, +/*0D38*/ 0x00000000, +/*0D39*/ 0x00007800, +/*0D3A*/ 0x00000000, +/*0D3B*/ 0x00000000, +/*0D3C*/ 0x00000000, +/*0D3D*/ 0x00C6BBB0, +/*0D3E*/ 0x2C002834, +/*0D3F*/ 0x082E002C, +/*0D40*/ 0x00000200, +/*0D41*/ 0x00000000, +/*0D42*/ 0x00000000, +/*0D43*/ 0x00007800, +/*0D44*/ 0x00000000, +/*0D45*/ 0x00000000, +/*0D46*/ 0x00000000, +/*0D47*/ 0x80808080, +/*0D48*/ 0x800D8080, +/*0D49*/ 0x80808080, +/*0D4A*/ 0x17808080, +/*0D4B*/ 0x80808025, +/*0D4C*/ 0x2221201F, +/*0D4D*/ 0x80808080, +/*0D4E*/ 0x80808080, +/*0D4F*/ 0x80808080, +/*0D50*/ 0x80808080, +/*0D51*/ 0x80808080, +/*0D52*/ 0x80808080, +/*0D53*/ 0x80808080, +/*0D54*/ 0x80808080, +/*0D55*/ 0x80808080, +/*0D56*/ 0x80808080, +/*0D57*/ 0x80808080, +/*0D58*/ 0x80808080, +/*0D59*/ 0x80808080, +/*0D5A*/ 0x80808080, +/*0D5B*/ 0x0A030201, +/*0D5C*/ 0x0E800C0B, +/*0D5D*/ 0x1211100F, +/*0D5E*/ 0x80161413, +/*0D5F*/ 0x08004C80, +/*0D60*/ 0x8080801E, +/*0D61*/ 0x80804E80, +/*0D62*/ 0x80808080, +/*0D63*/ 0x80808080, +/*0D64*/ 0x80808080 +}; + +#endif /* INIT_DRAM_TBL_V4H_LP5 */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram.c new file mode 100644 index 0000000..10d1d0f --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram.c @@ -0,0 +1,4542 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#else +#include "mem_io.h" +#include "log.h" +#endif +#include "ddr_regdef.h" +#include "init_dram_tbl_v4m_lp5.h" +#include "boot_init_dram_regdef.h" +#include "boot_init_dram.h" +#include "dram_sub_func.h" + +/******************************************************************************* + * load board configuration + ******************************************************************************/ +#include "boot_init_dram_config.h" + +#define DDR_BACKUPMODE +#define FATAL_MSG(x) NOTICE(x) + +/******************************************************************************* + * variables + ******************************************************************************/ +static uint32_t Prr_Product; +static uint32_t Prr_Cut; +static uint32_t BOARDTYPE; +static uint32_t brd_clk; +static uint32_t brd_clkdiv; +static uint32_t brd_clkdiva; +static uint32_t ddr_mbps; +static uint32_t ddr_mbpsdiv; +static uint32_t sscg; +static uint32_t med_freq_en; +static uint32_t bus_clk, bus_clkdiv; +static uint32_t ddr_tccd; +static const st_boardcnf_t *Boardcnf; +static uint32_t ddr_phyvalid; +static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT]; +static uint32_t ch_have_this_cs[CS_CNT]; +static uint32_t max_density; +static uint32_t ddr_mul; +static uint32_t ddr_medium_div; +static uint32_t ddr_mul_nf; +static uint32_t ddr_mul_low; +static uint32_t ddr_mul_reg; + +#define DDR_PHY_REGSET_MAX 140 +#define DDR_PI_REGSET_MAX 1301 + +static uint32_t DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX]; +static uint32_t DDR_PI_REGSET[DDR_PI_REGSET_MAX]; +#ifdef DDR_BACKUPMODE +static uint32_t ddrBackup; +#endif /* DDR_BACKUPMODE */ +#ifndef RCAR_PLL3_FRAC_MODE +#define RCAR_PLL3_FRAC_MODE (1U) +#endif +#ifndef RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE +#define RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE (1U) +#endif +#ifndef RCAR_MEDIUM_FREQUENCY_TRAINING_MODE +#define RCAR_MEDIUM_FREQUENCY_TRAINING_MODE (1U) +#endif +#define PLL3_LOW_FREQUENCY_MODE (0U) +#define PLL3_MEDIUM_FREQUENCY_MODE (1U) +#define PLL3_HIGH_FREQUENCY_MODE (2U) +#define PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER (3U) +#define PLL3_MEDIUM_FREQUENCY_THRESHOLD (1550U) + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static uint32_t r_vch_nxt(uint32_t pos); +static void r_cpg_write_32(uint32_t a, uint32_t v); +static void r_pll3_control(uint32_t mode); +static void r_send_dbcmd(uint32_t cmd); +static uint32_t r_reg_ddrphy_read(uint32_t phyno, uint32_t regadd); +static void r_reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata); +static void r_reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata); +static void r_reg_ddrphy_masked_write(uint32_t phyno, uint32_t regadd, uint32_t regdata, uint32_t msk); +static void r_ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t regdef, uint32_t val); +static uint32_t r_ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t regdef); +static void r_ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val); +static void r_ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val); +static void r_ddr_setval_ach(uint32_t regdef, uint32_t val); +static void r_ddr_setval_ach_as(uint32_t regdef, uint32_t val); +static uint32_t r_ddr_getval(uint32_t ch, uint32_t regdef); +static void r_dbsc_write_32(uintptr_t addr, uint32_t data); +static void r_tbl_copy(uint32_t *to, const uint32_t *from, uint32_t size); +static void r_ddrtbl_setval(uint32_t *tbl, uint32_t regdef, uint32_t val); +static void r_ddrtbl_setval_pi(uint32_t *tbl, uint32_t regdef, uint32_t val); +static uint32_t r_ddrtbl_getval(const uint32_t *tbl, uint32_t regdef); +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) +static uint32_t r_ddrtbl_getval_pi(const uint32_t *tbl, uint32_t regdef); +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ +static uint16_t r_f_scale(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint16_t cyc); +static uint32_t r_f_scale_l(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint32_t cyc); +static void r_f_scale_js2(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t *f_js2); +static void r_ddrtbl_load(void); +static void r_ddr_config(void); +static void r_dbsc_regset_pre(void); +static void r_dbsc_regset(void); +static void r_dbsc_regset_post(void); +static uint32_t r_pi_training(void); +static void r_write_leveling_adjust(void); +static uint32_t r_wl_gt_training(void); +static void r_write_dca(void); +static uint32_t r_dramdca_training(void); +static uint32_t r_write_leveling(void); +static void r_manual_write_dca(void); +static uint32_t r_read_gate_training(void); +static uint32_t r_read_vref_training(void); +static uint32_t r_read_write_training(void); +static uint32_t r_read_training(void); +static void r_ddr_register_set(void); +static void r_ddr_register_read(void); +static uint32_t r_pi_int_ack_0_assert(uint32_t bit); +static void r_wait_dbpdstat1(uint32_t status); +static uint32_t r_wait_freqchgreq(uint32_t req_assert); +static void r_set_freqchgack(uint32_t ack_assert); +static uint32_t r_pll3_freq(void); +static uint32_t r_init_ddr(void); +#if (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) +void r_set_pi_rdlvl_interval(void); +#endif /* (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) */ + +/******************************************************************************* + * macro for channel selection loop + ******************************************************************************/ +static uint32_t r_vch_nxt(uint32_t pos) +{ + uint32_t posn; + + for (posn = pos; posn < DRAM_CH_CNT; posn++) + { + if ((ddr_phyvalid & (1U << posn)) != 0x0U) + { + break; + } + } + return posn; +} + +#define r_foreach_vch(ch) \ +for (ch = r_vch_nxt(0); ch < DRAM_CH_CNT; ch = r_vch_nxt(ch + 1U)) + +#define r_foreach_ech(ch) \ +for (ch = 0U; ch < DRAM_CH_CNT; ch++) + +/******************************************************************************* + * Printing functions + ******************************************************************************/ +#define MSG_LF(...) + +/******************************************************************************* + * clock settings, reset control + ******************************************************************************/ +static void r_cpg_write_32(uint32_t a, uint32_t v) +{ + mmio_write_32(CPG_CPGWPR, ~v); + mmio_write_32(a, v); +} + +static void r_pll3_control(uint32_t mode) +{ + uint32_t dataDIV, dataMUL; + uint32_t ssmode, ssmode_high, dataNF; + /* PLL3VCO = EXTAL * ddr_mul * 1/2 */ + /* clk_ctlr_sync = PLL3VCO * pll3_div */ + /* ddr_mul = (NI[7:0] + 1) * 2 + NF[24:0] / 2^24 */ + +#if (RCAR_PLL3_FRAC_MODE == 1U) + ssmode_high = 0x4U; +#else + ssmode_high = 0x0U; +#endif /* (RCAR_PLL3_FRAC_MODE == 1U) */ + + switch (mode) + { + case PLL3_LOW_FREQUENCY_MODE: + /* Low frequency mode (50MHz) */ + dataMUL = (ddr_mul_low / 2U) - 1U; /* PLL3VCO = 1600MHz */ + dataDIV = 0x9U; /* div = 32 */ + dataNF = 0x00U; + ssmode = 0x0U; + break; + case PLL3_MEDIUM_FREQUENCY_MODE: + /* Medium frequency mode */ + dataMUL = (ddr_mul / 2U) - 1U; + dataDIV = ddr_medium_div; + dataNF = ddr_mul_nf; + ssmode = ssmode_high; + break; + case PLL3_HIGH_FREQUENCY_MODE: + /* High frequency mode */ + dataMUL = (ddr_mul / 2U) - 1U; + dataDIV = 0x0U; /* div = 2 */ + dataNF = ddr_mul_nf; + ssmode = ssmode_high; + break; + case PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER: + /* High frequency mode for loading to DDRPHY registers */ + dataMUL = (ddr_mul_reg / 2U) - 1U; + dataDIV = 0x0U; /* div = 2 */ + dataNF = 0x00U; + ssmode = ssmode_high; + break; + default: + /* High frequency mode */ + dataMUL = (ddr_mul / 2U) - 1U; + dataDIV = 0x0U; /* div = 2 */ + dataNF = ddr_mul_nf; + ssmode = ssmode_high; + break; + }/* mode setting */ + + dataMUL = (dataMUL << 20) | (ssmode << 16); + dataNF = (dataNF << 21); + + if (((mmio_read_32(CPG_PLL3CR0) & 0x3FFFFF7FU) != dataMUL) || (mmio_read_32(CPG_PLL3CR1) != dataNF)) + { + /* PLL3CR0 multiplie set */ + r_cpg_write_32(CPG_PLL3CR0, dataMUL); + /* PLL3CR1 multiplie set */ + r_cpg_write_32(CPG_PLL3CR1, dataNF); + r_cpg_write_32(CPG_PLL3CR0, mmio_read_32(CPG_PLL3CR0) | CPG_PLL3CR0_KICK_BIT); + while ((mmio_read_32(CPG_PLLECR) & CPG_PLLECR_PLL3ST_BIT) != CPG_PLLECR_PLL3ST_BIT) + { + ; /* Nothing */ + } + } + + /* PLL3 DIV set(Target value) */ + while (((mmio_read_32(CPG_FRQCRD0) & CPG_FRQCRD_KICK_BIT)) != 0x0U) + { + ; /* Nothing */ + } + r_cpg_write_32(CPG_FRQCRD0, dataDIV | (mmio_read_32(CPG_FRQCRD0) & 0xFFFFFFF0U)); + r_cpg_write_32(CPG_FRQCRD0, mmio_read_32(CPG_FRQCRD0) | CPG_FRQCRD_KICK_BIT); + while (((mmio_read_32(CPG_FRQCRD0) & CPG_FRQCRD_KICK_BIT)) != 0x0U) + { + ; /* Nothing */ + } +} + +/******************************************************************************* + * DDR memory register access + ******************************************************************************/ +static void r_send_dbcmd(uint32_t cmd) +{ + /* dummy read */ + (void)mmio_read_32(DBSC_DBCMD); + + while (((mmio_read_32(DBSC_DBWAIT)) & 0x01U) != 0x0U) + { + ; /* Nothing */ + } + + r_dbsc_write_32((DBSC_DBCMD), cmd); +} + +/******************************************************************************* + * DDRPHY register access (raw) + ******************************************************************************/ +static uint32_t r_reg_ddrphy_read(uint32_t phyno, uint32_t regadd) +{ + uint32_t val; + + val = 0U; + mmio_write_32(DBSC_DBPDRGA(phyno), (regadd | 0x00004000U)); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x0000C000U)) + { + ; /* Nothing */ + } + + val = mmio_read_32(DBSC_DBPDRGA(phyno)); + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + val = mmio_read_32(DBSC_DBPDRGD(phyno)); + (void)val; + + return val; +} + +static void r_reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata) +{ + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGD(phyno), regdata); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x00008000U)) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), (regadd | 0x00008000U)); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); +} + +static void r_reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata) +{ + uint32_t ch; + + r_foreach_vch((ch)) + { + r_reg_ddrphy_write(ch, regadd, regdata); + } +} + +static void r_reg_ddrphy_masked_write(uint32_t phyno, uint32_t regadd, uint32_t regdata, uint32_t msk) +{ + mmio_write_32(DBSC_DBPDRGM(phyno), msk); + while (mmio_read_32(DBSC_DBPDRGM(phyno)) != msk) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGD(phyno), regdata); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != (regadd | 0x00008000U)) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000U); + while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) + { + ; /* Nothing */ + } + + mmio_write_32(DBSC_DBPDRGA(phyno), regadd); + + mmio_write_32(DBSC_DBPDRGM(phyno), 0x00U); + while (mmio_read_32(DBSC_DBPDRGM(phyno)) != 0x00U) + { + ; /* Nothing */ + } +} + +/******************************************************************************* + * DDRPHY register access (field modify) + ******************************************************************************/ +static void r_ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + + adr = DDR_REGDEF_ADR(regdef) + (0x100U * slice); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + tmp = 0xFFFFFFFFU; + } + else + { + tmp = ((1U << len) - 1U) << lsb; + } + + msk = (~(((tmp >> 21) & 0x08U) | ((tmp >> 14) & 0x04U) | ((tmp >> 7) & 0x02U) | (tmp & 0x01U))) & 0x0FU; + + r_reg_ddrphy_masked_write(ch, adr, (val << lsb), msk); +} + +static uint32_t r_ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + + adr = DDR_REGDEF_ADR(regdef) + (0x100U * slice); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U); + } + + tmp = r_reg_ddrphy_read(ch, adr); + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +static void r_ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val) +{ + r_ddr_setval_s(ch, 0U, regdef, val); +} + +static void r_ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val) +{ + uint32_t ch; + + r_foreach_vch((ch)) + { + r_ddr_setval_s(ch, slice, regdef, val); + } +} + +static void r_ddr_setval_ach(uint32_t regdef, uint32_t val) +{ + r_ddr_setval_ach_s(0U, regdef, val); +} + +static void r_ddr_setval_ach_as(uint32_t regdef, uint32_t val) +{ + uint32_t slice; + + for (slice = 0U; slice < SLICE_CNT; slice++) + { + r_ddr_setval_ach_s(slice, regdef, val); + } +} + +static uint32_t r_ddr_getval(uint32_t ch, uint32_t regdef) +{ + return r_ddr_getval_s(ch, 0U, regdef); +} + +/******************************************************************************* + * DBSC0 register access + ******************************************************************************/ +static void r_dbsc_write_32(uintptr_t addr, uint32_t data) +{ + *((volatile uint32_t*)addr) = data; +} + +/******************************************************************************* + * handling functions for setteing ddrphy value table + ******************************************************************************/ +static void r_tbl_copy(uint32_t *to, const uint32_t *from, uint32_t size) +{ + uint32_t i; + + for (i = 0U; i < size; i++) + { + to[i] = from[i]; + } +} + +static void r_ddrtbl_setval(uint32_t *tbl, uint32_t regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000000FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U) << lsb; + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + tbl[adr & adrmsk] = tmp; +} + +static void r_ddrtbl_setval_pi(uint32_t *tbl, uint32_t regdef, uint32_t val) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000007FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U) << lsb; + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp & (~msk)) | ((val << lsb) & msk); + tbl[adr & adrmsk] = tmp; +} + +static uint32_t r_ddrtbl_getval(const uint32_t *tbl, uint32_t regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000000FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U); + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp >> lsb) & msk; + + return tmp; +} + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) +static uint32_t r_ddrtbl_getval_pi(const uint32_t *tbl, uint32_t regdef) +{ + uint32_t adr; + uint32_t lsb; + uint32_t len; + uint32_t msk; + uint32_t tmp; + const uint32_t adrmsk = 0x000007FFU; + + adr = DDR_REGDEF_ADR(regdef); + len = DDR_REGDEF_LEN(regdef); + lsb = DDR_REGDEF_LSB(regdef); + if (len == 0x20U) + { + msk = 0xFFFFFFFFU; + } + else + { + msk = ((1U << len) - 1U); + } + + tmp = tbl[adr & adrmsk]; + tmp = (tmp >> lsb) & msk; + + return tmp; +} +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + +/******************************************************************************* + * functions and parameters for timing setting + ******************************************************************************/ +typedef struct +{ + uint32_t fx3; + uint8_t RLset1; + uint8_t RLset2; + uint8_t WLsetA; + uint8_t WLsetB; + uint32_t nWR; + uint32_t nRBTP; + uint32_t ODTLon; + uint8_t MR1; + uint8_t MR2; + uint32_t WCKENLR; + uint32_t WCKENLW; + uint32_t WCKENLF; + uint32_t WCKPRESTA; + uint32_t WCKPRETGLR; +} jedec_spec1_t; + +#define JS1_USABLEC_SPEC_LO 5U +#define JS1_USABLEC_SPEC_HI 11U +#define JS1_FREQ_TBL_NUM 12U +#define JS1_MR1(f) (0x00U | ((f) << 4)) /* CK mode = 0B */ +#define JS1_MR2(f) (((f) << 4) | (f)) + +static const jedec_spec1_t js1[JS1_FREQ_TBL_NUM] = +{ + /* fx3,RL1,RL2,WLA.WLB.nWR.nRBTP,ODTLon */ + { 800, 3, 3, 2, 2, 3, 0, 1, JS1_MR1(0), JS1_MR2(0), 0, 0, 0, 1, 3 }, /* 533.333Mbps */ + { 1600, 4, 4, 2, 3, 5, 0, 1, JS1_MR1(1), JS1_MR2(1), 0, 0, 0, 1, 4 }, /* 1066.666Mbps */ + { 2400, 5, 6, 3, 4, 7, 0, 2, JS1_MR1(2), JS1_MR2(2), 1, 1, 1, 1, 4 }, /* 1600.000Mbps */ + { 3200, 7, 7, 4, 5, 10, 0, 2, JS1_MR1(3), JS1_MR2(3), 2, 1, 1, 2, 4 }, /* 2133.333Mbps */ + { 4000, 8, 9, 4, 7, 12, 1, 2, JS1_MR1(4), JS1_MR2(4), 2, 1, 1, 2, 5 }, /* 2666.666Mbps */ + { 4800, 10, 10, 5, 8, 14, 1, 3, JS1_MR1(5), JS1_MR2(5), 4, 2, 1, 2, 5 }, /* 3200.000Mbps */ + { 5600, 11, 12, 6, 9, 16, 2, 4, JS1_MR1(6), JS1_MR2(6), 4, 2, 1, 3, 5 }, /* 3733.333Mbps */ + { 6400, 13, 14, 6, 11, 19, 2, 3, JS1_MR1(7), JS1_MR2(7), 5, 2, 1, 3, 6 }, /* 4266.666Mbps */ + { 7200, 14, 15, 7, 12, 21, 3, 4, JS1_MR1(8), JS1_MR2(8), 6, 3, 2, 3, 6 }, /* 4800.000Mbps */ + { 8250, 16, 17, 8, 14, 24, 4, 5, JS1_MR1(9), JS1_MR2(9), 7, 3, 2, 4, 6 }, /* 5500.000Mbps */ + { 9000, 17, 19, 9, 15, 26, 4, 6, JS1_MR1(10), JS1_MR2(10), 7, 4, 2, 4, 7 }, /* 6000.000Mbps */ + { 9600, 18, 20, 9, 16, 28, 4, 6, JS1_MR1(11), JS1_MR2(11), 8, 4, 2, 4, 7 } /* 6400.000Mbps */ +}; + +typedef struct +{ + uint16_t ps; + uint16_t cyc; +} jedec_spec2_t; + +#define JS2_tSR 0U +#define JS2_tXP 1U +#define JS2_tRCD 2U +#define JS2_tRPpb 3U +#define JS2_tRPab 4U +#define JS2_tRAS 5U +#define JS2_tWTR_S 6U +#define JS2_tWTR_L 7U +#define JS2_tRRD 8U +#define JS2_tPPD 9U +#define JS2_tFAW 10U +#define JS2_tMRR 11U +#define JS2_tMRW 12U +#define JS2_tMRD 13U +#define JS2_tZQCALns 14U +#define JS2_tZQLAT 15U +#define JS2_tODTon_min 16U +#define JS2_tPDN_DSM 17U +#define JS2_tXSR_DSM 18U +#define JS2_tXDSM_XP 19U +#define JS2_tWCK2DQI_HF 20U +#define JS2_tWCK2DQO_HF 21U +#define JS2_tWCK2DQI_LF 22U +#define JS2_tWCK2DQO_LF 23U +#define JS2_tOSCODQI 24U +#define JS2_tDQ72DQns 25U +#define JS2_tCAENTns 26U +#define JS2_tCSCAL 27U +#define JS2_tWCKSTOP 28U +#define JS2_TBLCNT 29U + +#define JS2_tRCpb (JS2_TBLCNT) +#define JS2_tRCab (JS2_TBLCNT + 1U) +#define JS2_tRFCab (JS2_TBLCNT + 2U) +#define JS2_tRBTP (JS2_TBLCNT + 3U) +#define JS2_tXSR (JS2_TBLCNT + 4U) +#define JS2_tPDN (JS2_TBLCNT + 5U) +#define JS2_tWLWCKOFF (JS2_TBLCNT + 6U) +#define JS2_CNT (JS2_TBLCNT + 7U) + +#ifndef JS2_DERATE +#define JS2_DERATE 0 +#endif + +static const jedec_spec2_t jedec_spec2[2][JS2_TBLCNT] = +{ + { +/* tSR */ { 15000, 2 }, +/* tXP */ { 7000, 3 }, +/* tRCD */ { 18000, 2 }, +/* tRPpb */ { 18000, 2 }, +/* tRPab */ { 21000, 2 }, +/* tRAS */ { 42000, 3 }, +/* tWTR_S */ { 6250, 4 }, +/* tWTR_L */ { 12000, 4 }, +/* tRRD */ { 5000, 2 }, +/* tPPD */ { 0, 2 }, +/* tFAW */ { 20000, 0 }, +/* tMRR */ { 0, 4 }, +/* tMRW */ { 10000, 5 }, +/* tMRD */ { 14000, 5 }, +/* tZQCALns */ { 1500, 0 }, +/* tZQLAT */ { 30000, 4 }, +/* tODTon_min */ { 1500, 0 }, +/* tPDN_DSMus */ { 4000, 0 }, +/* tXSR_DSMus */ { 200, 0 }, +/* tXDSM_XPus */ { 190, 0 }, +/* tWCK2DQI_HF */ { 700, 0 }, +/* tWCK2DQO_HF */ { 1600, 0 }, +/* tWCK2DQI_LF */ { 900, 0 }, +/* tWCK2DQO_LF */ { 1900, 0 }, +/* tOSCODQI */ { 40000, 8 }, +/* tDQ72DQns */ { 125, 0 }, +/* tCAENTns */ { 250, 0 }, +/* tCSCAL */ { 1750, 0 }, +/* tWCKSTOP */ { 6000, 2 } + },{ +/* tSR */ { 15000, 2 }, +/* tXP */ { 7000, 3 }, +/* tRCD */ { 19875, 2 }, +/* tRPpb */ { 19875, 2 }, +/* tRPab */ { 22875, 2 }, +/* tRAS */ { 43875, 3 }, +/* tWTR_S */ { 6250, 4 }, +/* tWTR_L */ { 12000, 4 }, +/* tRRD */ { 5000, 2 }, +/* tPPD */ { 0, 2 }, +/* tFAW */ { 20000, 0 }, +/* tMRR */ { 0, 4 }, +/* tMRW */ { 10000, 5 }, +/* tMRD */ { 14000, 5 }, +/* tZQCALns */ { 1500, 0 }, +/* tZQLAT */ { 30000, 4 }, +/* tODTon_min */ { 1500, 0 }, +/* tPDN_DSMus */ { 4000, 0 }, +/* tXSR_DSMus */ { 200, 0 }, +/* tXDSM_XPus */ { 190, 0 }, +/* tWCK2DQI_HF */ { 715, 0 }, +/* tWCK2DQO_HF */ { 1635, 0 }, +/* tWCK2DQI_LF */ { 920, 0 }, +/* tWCK2DQO_LF */ { 1940, 0 }, +/* tOSCODQI */ { 40000, 8 }, +/* tDQ72DQns */ { 125, 0 }, +/* tCAENTns */ { 250, 0 }, +/* tCSCAL */ { 1750, 0 }, +/* tWCKSTOP */ { 6000, 2 } + } +}; + +static const uint16_t jedec_spec2_tRFC_ab[9] = +{ +/* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 130, 180, 180, 210, 210, 280, 280, 380, 380 +}; + +static uint32_t js1_ind; +static uint32_t js2[JS2_CNT]; +static uint32_t RL; +static uint32_t WL; + +static uint16_t r_f_scale(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint16_t cyc) +{ + uint32_t tmp; + uint32_t f_scale_div; + + tmp = (((uint32_t)(ps) + 9U) / 10U) * f_ddr_mbps; + f_scale_div = tmp / (800000U * f_ddr_mbpsdiv); + if (tmp != (f_scale_div * 800000U * f_ddr_mbpsdiv)) + { + f_scale_div = f_scale_div + 1U; + } + + if (f_scale_div > cyc) + { + cyc = (uint16_t)f_scale_div; + } + + return cyc; +} + +static uint32_t r_f_scale_l(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t ps, uint32_t cyc) +{ + uint32_t tmp; + uint32_t f_scale_div; + + tmp = (((uint32_t)(ps) + 9U) / 10U) * f_ddr_mbps; + f_scale_div = tmp / (8U * f_ddr_mbpsdiv); + if (tmp != (f_scale_div * 8U * f_ddr_mbpsdiv)) + { + f_scale_div = f_scale_div + 1U; + } + + if (f_scale_div > cyc) + { + cyc = (uint32_t)f_scale_div; + } + + return cyc; +} + +static void r_f_scale_js2(uint32_t f_ddr_mbps, uint32_t f_ddr_mbpsdiv, uint32_t *f_js2) +{ + uint32_t i; + + for (i = 0U; i < JS2_TBLCNT; i++) + { + f_js2[i] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, + (uint32_t)jedec_spec2[JS2_DERATE][i].ps, + jedec_spec2[JS2_DERATE][i].cyc); + } + + f_js2[JS2_tZQCALns] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tZQCALns].ps) * 1000U, 0U); + f_js2[JS2_tDQ72DQns] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tDQ72DQns].ps) * 1000U, 0U); + f_js2[JS2_tCAENTns] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tCAENTns].ps) * 1000U, 0U); + f_js2[JS2_tRCpb] = f_js2[JS2_tRAS] + f_js2[JS2_tRPpb]; + f_js2[JS2_tRCab] = f_js2[JS2_tRAS] + f_js2[JS2_tRPab]; + f_js2[JS2_tRFCab] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 1UL * jedec_spec2_tRFC_ab[max_density] * 1000U, 0U); + + f_js2[JS2_tRBTP] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 7500U, 2U) - 2U; + f_js2[JS2_tXSR] = f_js2[JS2_tRFCab] + r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 7500U, 2U); + f_js2[JS2_tPDN] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 10000U, 0U) + 1U; + f_js2[JS2_tPDN_DSM] = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tPDN_DSM].ps) * 10U, 0U); + f_js2[JS2_tXSR_DSM] = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tXSR_DSM].ps) * 10U, 0U); + f_js2[JS2_tXDSM_XP] = r_f_scale_l(f_ddr_mbps, f_ddr_mbpsdiv, (uint32_t)(jedec_spec2[JS2_DERATE][JS2_tXDSM_XP].ps) * 10U, 0U); + f_js2[JS2_tWLWCKOFF] = r_f_scale(f_ddr_mbps, f_ddr_mbpsdiv, 14000U, 5U); +} + +static const uint32_t PI_DARRAY3_0_CSx_Fx[CS_CNT][3] = +{ + { + PI_DARRAY3_0_CS0_F0, + PI_DARRAY3_0_CS0_F1, + PI_DARRAY3_0_CS0_F2 + }, + { + PI_DARRAY3_0_CS1_F0, + PI_DARRAY3_0_CS1_F1, + PI_DARRAY3_0_CS1_F2 + } +}; + +static const uint32_t PI_DARRAY3_1_CSx_Fx[CS_CNT][3] = +{ + { + PI_DARRAY3_1_CS0_F0, + PI_DARRAY3_1_CS0_F1, + PI_DARRAY3_1_CS0_F2 + }, + { + PI_DARRAY3_1_CS1_F0, + PI_DARRAY3_1_CS1_F1, + PI_DARRAY3_1_CS1_F2 + } +}; + +/******************************************************************************* + * load table data into DDR registers + ******************************************************************************/ +static void r_ddrtbl_load(void) +{ + uint32_t i; + uint32_t slice; + uint32_t cs; + uint32_t adr; + uint32_t dataL; + uint32_t tmp[2]; + + /* Setting RDDQ delay = 103ps */ + const uint32_t rddq_delay = 103U; + + const uint32_t DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_V4M; + const uint32_t DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_V4M; + const uint32_t DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_V4M; + const uint32_t DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_V4M; + + const uint32_t DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_V4M; + + const uint32_t DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_V4M; + const uint32_t DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_V4M; + const uint32_t DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_V4M; + const uint32_t DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_V4M; + + /*********************************************************************** + * TIMING REGISTERS + ***********************************************************************/ + /* search jedec_spec1 index */ + for (i = JS1_USABLEC_SPEC_LO; i < (JS1_FREQ_TBL_NUM - 1U); i++) + { + if ((js1[i].fx3 * 2U * ddr_mbpsdiv) >= (ddr_mbps * 3U)) + { + break; + } + } + + if (JS1_USABLEC_SPEC_HI < i) + { + js1_ind = JS1_USABLEC_SPEC_HI; + } + else + { + js1_ind = i; + } + + RL = js1[js1_ind].RLset1; + + WL = js1[js1_ind].WLsetA; + + /* calculate jedec_spec2 */ + r_f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2); + + /*********************************************************************** + * PREPARE TBL + ***********************************************************************/ + r_tbl_copy(DDR_PHY_SLICE_REGSET, + DDR_PHY_SLICE_REGSET_V4M, DDR_PHY_SLICE_REGSET_NUM_V4M); + r_tbl_copy(DDR_PHY_ADR_V_REGSET, + DDR_PHY_ADR_V_REGSET_V4M, DDR_PHY_ADR_V_REGSET_NUM_V4M); + r_tbl_copy(DDR_PHY_ADR_G_REGSET, + DDR_PHY_ADR_G_REGSET_V4M, DDR_PHY_ADR_G_REGSET_NUM_V4M); + r_tbl_copy(DDR_PI_REGSET, + DDR_PI_REGSET_V4M, DDR_PI_REGSET_NUM_V4M); + + /*********************************************************************** + * Adjust PI paramters + ***********************************************************************/ + dataL = 10000U * ddr_mbps / ddr_mbpsdiv / 8U / 256U; + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_CAL_INTERVAL_COUNT_0, dataL); + + dataL = rddq_delay * ddr_mbps * 256U / (ddr_mbpsdiv * 2U * 1000000U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ0_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ1_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ2_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ3_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ4_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ5_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ6_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQ7_SLAVE_DELAY, dataL); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDM_SLAVE_DELAY, dataL); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_F2, WL); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_WR_ADJ_F2, (js1[js1_ind].WCKENLW * 4U) + 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_RD_ADJ_F2, (js1[js1_ind].WCKENLR * 4U) + 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_STATIC_F2, (js1[js1_ind].WCKPRESTA * 4U)); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_TOGGLE_RD_F2, (js1[js1_ind].WCKPRETGLR * 4U)); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CASLAT_F2, RL); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_FS_ADJ_F2, (js1[js1_ind].WCKENLF * 4U) + 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRFC_F2, js2[JS2_tRFCab]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLVL_WCKOFF_F2, (js2[JS2_tWLWCKOFF]) + 3U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_ADJ_F2, (WL * 4U) + 2U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCAENT_F2, js2[JS2_tCAENTns]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVREF_LONG_F2, (js2[JS2_tCAENTns]) + 1U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRCD_F2, js2[JS2_tRCD]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRP_F2, js2[JS2_tRPab]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRTP_F2, js1[js1_ind].nRBTP); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MIN_F2, js2[JS2_tRAS]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRD_F2, (js2[JS2_tMRD]) + 1U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TSR_F2, js2[JS2_tSR]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQCAL_F2, js2[JS2_tZQCALns]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQLAT_F2, js2[JS2_tZQLAT]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQ72DQ_F2, js2[JS2_tDQ72DQns]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MC_TRFC_F2, js2[JS2_tRFCab]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_WRLAT_ADJ_F2, (WL * 4U) - 2U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_TWCKENL_RD_ADJ_F2, (js1[js1_ind].WCKENLR * 4U) + 4U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WCK_STOP_F2, (js2[JS2_tWCKSTOP]) + 2U); + + if (ddr_mbps < (3201U * ddr_mbpsdiv)) + { + /* 2751 - 3200 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_PER_START, 0x40U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x05U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x07U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x0BU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x07U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x25U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x012DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x0BU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x04U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x03U); + + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_TCKSRE_WAIT, 0x01U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x57U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2, 0x0DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x000613U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x002BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x0022U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x0043U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x001DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x0065U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x0029U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_STROBE_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x12U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x0064U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x0012U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0010U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2, 0x0022U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x0EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2, 0x62B8U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQSCK_MAX_F2, 0x01U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x000C26U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x0000797CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2, 0x009BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x013880U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x013880U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x0C3500U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000014U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x000320U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x009BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0014U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x04U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000064U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x000320U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x00000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000029U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x000065U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x000005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2, 0x000000U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2, 0x000065U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2, 0x0016U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F2, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2, 0x0007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2, 0x0016U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F2, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2, 0x0007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2, 0x0016U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F2, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2, 0x0007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2, 0x0016U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F2, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2, 0x0007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_2_CS0_F2, 0xD6U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_2_CS1_F2, 0xD6U); + } + else if (ddr_mbps < (3734U * ddr_mbpsdiv)) + { + /* 3201 - 3733 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_PER_START, 0x40U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x06U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x0AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x0DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x2AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x0149U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x0DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x04U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x04U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x5BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2, 0x10U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x000717U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x002CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x0024U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x0045U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x001FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x0076U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x0030U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_STROBE_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x13U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x0075U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x0014U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2, 0x0024U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x10U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2, 0x7329U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQSCK_MAX_F2, 0x01U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x000E2EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x00008DCCU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2, 0x00B6U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x016C90U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x016C90U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x0E3D98U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000018U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x0003A6U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x00B5U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0018U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000075U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x0003A6U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000030U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x000076U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x000007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2, 0x000000U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2, 0x000076U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2, 0x0019U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2, 0x000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2, 0x0007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2, 0x0019U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2, 0x000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2, 0x0007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2, 0x0019U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2, 0x000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2, 0x0007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2, 0x0019U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2, 0x000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2, 0x0007U); + } + else if (ddr_mbps < (4268U * ddr_mbpsdiv)) + { + /* 3734 - 4267 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_PER_START, 0x40U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x07U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x09U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x0BU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x0EU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x2EU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x0164U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x0EU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x05U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x04U); + + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x64U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2, 0x12U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x00081CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x002DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x002BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x0046U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x0020U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x0087U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x0037U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x14U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x0086U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x0015U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2, 0x002BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x13U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2, 0x83A0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x001038U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x0000A230U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2, 0x00CFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x01A0ABU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x01A0ABU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x1046ABU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x00001BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x00042BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x00CFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x001BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000086U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000007U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x00042BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000037U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x000087U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x000008U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2, 0x000000U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2, 0x000087U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2, 0x0009U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2, 0x0009U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2, 0x0009U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F2, 0x0004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2, 0x0009U); + } + else if (ddr_mbps < (4801U * ddr_mbpsdiv)) + { + /* 4268 - 4800 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_PER_START, 0x40U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x0AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x0DU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x10U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, 0x08U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x31U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x017FU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x10U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x05U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x05U); + + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKCKEL_F2, 0x03U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x68U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2, 0x13U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x000920U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x002EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x002DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x0047U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x0021U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x0097U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x003DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXP_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x14U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x0096U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x0017U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0014U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2, 0x002DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x15U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2, 0x940BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x001240U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x0000B680U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2, 0x00E9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x01D4A9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x01D4A9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x124E91U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x00001EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x0004B0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x00E9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x001EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x000096U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_18_F2, 0x000008U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x0004B0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F2, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000015U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x00003DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x000097U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x00000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2, 0x000001U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2, 0x000097U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2, 0x001FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F2, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2, 0x000DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2, 0x0009U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2, 0x001FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F2, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2, 0x000DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2, 0x0009U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2, 0x001FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F2, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2, 0x000DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2, 0x0009U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2, 0x001FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F2, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2, 0x000DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2, 0x0009U); + } + else if (ddr_mbps < (5501U * ddr_mbpsdiv)) + { + /* 4801 - 5500 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_REGULATOR_EN_CNT, 0x09U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_CAL_ALL_DLY, 0x0CU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x10U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x13U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x37U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x01A3U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x13U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, 0x06U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x06U); + + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x71U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F2, 0x0DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2, 0x15U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x000A79U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x0030U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x0032U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F2, 0x0049U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F2, 0x0023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x00AEU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x0046U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F2, 0x15U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x00ADU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F2, 0x0019U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0016U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2, 0x0032U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F2, 0x09U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x18U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2, 0xA9D9U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x0014F2U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x0000D174U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2, 0x010CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x0219AFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x0219AFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x1500CFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x000561U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x010BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F2, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x0000ADU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x000561U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x000019U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x000046U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x0000AEU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F2, 0x00000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2, 0x000003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2, 0x0000AEU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2, 0x0023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F2, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2, 0x0023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F2, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2, 0x0023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F2, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2, 0x0023U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F2, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F2, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2, 0x000AU); + } + else if (ddr_mbps < (6001U * ddr_mbpsdiv)) + { + /* 5501 - 6000 */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_TSEL_DLY, 0x12U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_OE_DLY, 0x15U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_WRLVL_RESP_WAIT_CNT, 0x3AU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDLVL_MAX_EDGE, 0x01BDU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, 0x15U); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_GTLVL_LAT_ADJ_START, 0x06U); + + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_ADR_CALVL_DLY_STEP, 0x02U); + + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x75U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F2, 0x16U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F2, 0x000B6BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F2, 0x0031U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F2, 0x0034U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F2, 0x00BDU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F2, 0x004DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TMRWCKEL_F2, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F2, 0x00BCU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F2, 0x0017U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F2, 0x0034U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F2, 0x1AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F2, 0xB924U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F2, 0x0016D6U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F2, 0x0000E45CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F2, 0x0124U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F2, 0x024A16U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F2, 0x024A16U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F2, 0x16E4D8U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F2, 0x000026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F2, 0x0005DDU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F2, 0x0123U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F2, 0x0026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F2, 0x0000BCU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F2, 0x0005DDU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F2, 0x00001BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F2, 0x00004DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F2, 0x0000BDU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_27_F2, 0x000004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F2, 0x0000BDU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F2, 0x0026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F2, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F2, 0x0026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F2, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F2, 0x0026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F2, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F2, 0x0026U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F2, 0x000AU); + } + else + { + ; /* Nothing */ + } /* (ddr_mbps < (3201U * ddr_mbpsdiv)) */ + +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + if (med_freq_en == 0x01U) + { + if (ddr_mbps < (1601U * ddr_mbpsdiv * ddr_medium_div)) + { + /* 1068 - 1600 */ + /* default */ + ; + } + else if (ddr_mbps < (2134U * ddr_mbpsdiv * ddr_medium_div)) + { + /* 1601 - 2133 */ + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F1, 0x4AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_F1, 0x04U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_RD_ADJ_F1, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_STATIC_F1, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F1, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F1, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CASLAT_F1, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRFC_F1, 0x0066U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F1, 0x00040AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x0028U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F1, 0x001AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_ADJ_F1, 0x12U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F1, 0x0041U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F1, 0x001BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCAENT_F1, 0x0043U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVREF_LONG_F1, 0x0044U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F1, 0x0044U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F1, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F1, 0x11U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F1, 0x0043U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F1, 0x0010U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F1, 0x000DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F1, 0x001AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_TWCKENL_RD_ADJ_F1, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRP_F1, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRCD_F1, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F1, 0x0AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F1, 0x41D0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MIN_F1, 0x000CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TSR_F1, 0x04U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F1, 0x000814U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F1, 0x000050C8U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F1, 0x0068U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F1, 0x00D056U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F1, 0x00D056U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F1, 0x082356U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F1, 0x00000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F1, 0x000216U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F1, 0x0068U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F1, 0x000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQCAL_F1, 0x0190U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQLAT_F1, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQ72DQ_F1, 0x0022U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MC_TRFC_F1, 0x0066U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F1, 0x000043U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F1, 0x000216U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F1, 0x00000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F1, 0x00001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F1, 0x000044U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F1, 0x000003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F1, 0x000044U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F1, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F1, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F1, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F1, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F1, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F1, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F1, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F1, 0x000AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F1, 0x0005U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CS0_F1, 0x30U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CS0_F1, 0x33U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CS1_F1, 0x30U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CS1_F1, 0x33U); + } + else + { + /* 2134 - 2750 */ + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDELAY_RDWR_2_BUS_IDLE_F1, 0x4FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_F1, 0x04U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKENL_RD_ADJ_F1, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_STATIC_F1, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWCKPRE_TOGGLE_RD_F1, 0x14U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_WR_F1, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WCK_ACTIVE_RD_F1, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CASLAT_F1, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRFC_F1, 0x0083U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TREF_F1, 0x000538U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WRLVL_WW_F1, 0x002AU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RDLAT_ADJ_F1, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WRLAT_ADJ_F1, 0x12U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CC_F1, 0x0042U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CALVL_CAPTURE_F1, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCAENT_F1, 0x0056U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVREF_LONG_F1, 0x0057U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_ENABLE_F1, 0x0057U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TVRCG_DISABLE_F1, 0x0024U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCKEHDQS_F1, 0x12U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TFC_F1, 0x0056U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_WR_F1, 0x0011U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WDQLVL_RW_F1, 0x000EU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_RDLAT_ADJ_F1, 0x001CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_WRLAT_ADJ_F1, 0x0012U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_TWCKENL_RD_ADJ_F1, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRTP_F1, 0x01U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRP_F1, 0x08U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRCD_F1, 0x07U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_S_F1, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_L_F1, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWTR_F1, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TWR_F1, 0x0CU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MAX_F1, 0x54E5U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TRAS_MIN_F1, 0x000FU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TSR_F1, 0x06U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_MAX_F1, 0x000A70U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_CTRLUPD_INTERVAL_F1, 0x00006860U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSR_F1, 0x0086U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT_F1, 0x010CC0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT1_F1, 0x010CC0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT3_F1, 0x0A7F7BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT4_F1, 0x000012U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TINIT5_F1, 0x0002B0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TXSNR_F1, 0x0086U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_ZQRESET_F1, 0x0012U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQCAL_F1, 0x0204U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TZQLAT_F1, 0x0BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDQ72DQ_F1, 0x002BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TCBTRTW_F1, 0x04U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_MC_TRFC_F1, 0x0083U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_TDFI_WCK_STOP_F1, 0x05U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_16_F1, 0x000056U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_17_F1, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_19_F1, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_20_F1, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_21_F1, 0x0002B0U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_22_F1, 0x000002U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_23_F1, 0x00000DU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_24_F1, 0x000024U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_25_F1, 0x000057U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_26_F1, 0x000004U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_SEQ_WAIT_31_F1, 0x000057U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_0_F1, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_0_F1, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_0_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_0_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_0_F1, 0x0006U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_1_F1, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_1_F1, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_1_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_1_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_1_F1, 0x0006U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_2_F1, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_2_F1, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_2_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_2_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_2_F1, 0x0006U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WP_GAP_3_F1, 0x0013U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RP_GAP_3_F1, 0x0003U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_S_3_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WR_GAP_L_3_F1, 0x000BU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_RW_GAP_3_F1, 0x0006U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CS0_F1, 0x40U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CS0_F1, 0x44U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CS1_F1, 0x40U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CS1_F1, 0x44U); + } /* (ddr_mbps < (1601U * ddr_mbpsdiv * ddr_medium_div)) */ + } /* (med_freq_en == 0x01U) */ +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ + + tmp[0] = js1[js1_ind].MR1; + tmp[1] = js1[js1_ind].MR2; + + for (cs = 0U; cs < CS_CNT; cs++) + { + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_0_CSx_Fx[cs][2], tmp[0]); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_DARRAY3_1_CSx_Fx[cs][2], tmp[1]); + } + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) + { + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_SET_DFI_INPUT_RST_PAD, 0x01U); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_PWRUP_SREFRESH_EXIT, 0x01U); + } +#endif /* DDR_BACKUPMODE */ + + /*********************************************************************** + * Read Vref (SoC side) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->bdcfg_vref_r); + if (dataL != 0x0U) + { + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_START_POINT, dataL & 0x000000FFU); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_STOP_POINT, (dataL & 0x0000FF00U) >> 8); + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_VREF_INITIAL_STEPSIZE, (dataL & 0x00FF0000U) >> 16); + } + + /*********************************************************************** + * Write Vref (MR14, MR15) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->bdcfg_vref_w); + if (dataL != 0x0U) + { + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F0, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F1, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_START_POINT_F2, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0, (dataL & 0xFF00U) >> 8); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, (dataL & 0xFF00U) >> 8); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2, (dataL & 0xFF00U) >> 8); + } + + /*********************************************************************** + * CA Vref (MR12) Training range + ***********************************************************************/ + dataL = (uint32_t)(Boardcnf->bdcfg_vref_ca); + if (dataL != 0x0U) + { + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_START_POINT_F2, dataL & 0x00FFU); + r_ddrtbl_setval_pi(DDR_PI_REGSET, PI_CALVL_VREF_INITIAL_STOP_POINT_F2, (dataL & 0xFF00U) >> 8); + } + + /*********************************************************************** + * Low Freq setting + ***********************************************************************/ + if (ddr_mbps < (8U * 640U * ddr_mbpsdiv)) + { + /* CAL_CLK(10-20MHz) */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_DATA_DC_CAL_CLK_SEL, 0x05U); + r_ddrtbl_setval(DDR_PHY_ADR_V_REGSET, PHY_CLK_DC_CAL_CLK_SEL, 0x04U); + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_CAL_CLK_SELECT_0, 0x05U); + } + + if (ddr_mbps < (8U * 572U * ddr_mbpsdiv)) + { + /* CAL_CLK(10-20MHz) */ + r_ddrtbl_setval(DDR_PHY_SLICE_REGSET, PHY_RX_PCLK_CLK_SEL, 0x03U); + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x02U); + } + + if (ddr_mbps < (8U * 401U * ddr_mbpsdiv)) + { + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PLL_CTRL, 0x1542U); + r_ddrtbl_setval(DDR_PHY_ADR_G_REGSET, PHY_PLL_CTRL_8X, 0x3342U); + } + + /*********************************************************************** + * SET DATA SLICE TABLE + ***********************************************************************/ + for (slice = 0U; slice < SLICE_CNT; slice++) + { + adr = DDR_PHY_SLICE_REGSET_OFS + (DDR_PHY_SLICE_REGSET_SIZE * slice); + for (i = 0U; i < DDR_PHY_SLICE_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PHY_SLICE_REGSET[i]); + } + } + + /*********************************************************************** + * SET ADR SLICE TABLE + ***********************************************************************/ + adr = DDR_PHY_ADR_V_REGSET_OFS; + for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PHY_ADR_V_REGSET[i]); + } + + /*********************************************************************** + * SET ADRCTRL SLICE TABLE + ***********************************************************************/ + adr = DDR_PHY_ADR_G_REGSET_OFS; + for (i = 0U; i < DDR_PHY_ADR_G_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PHY_ADR_G_REGSET[i]); + } + + /*********************************************************************** + * SET PI REGISTERS + ***********************************************************************/ + adr = DDR_PI_REGSET_OFS; + for (i = 0U; i < DDR_PI_REGSET_NUM; i++) + { + r_reg_ddrphy_write_a(adr + i, DDR_PI_REGSET[i]); + } + +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + /*********************************************************************** + * SET MEDIUM FREQ SETTING + ************************************************************************/ + if (med_freq_en == 0x01U) + { + r_ddr_setval_ach(PHY_FREQ_SEL_MULTICAST_EN, 0x00U); + r_ddr_setval_ach(PHY_FREQ_SEL_INDEX, 0x00U); + + dataL = rddq_delay * ddr_mbps * 256U / (ddr_mbpsdiv * ddr_medium_div * 2U * 1000000U); + r_ddr_setval_ach_as(PHY_RDDQ0_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDQ1_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDQ2_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDQ3_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDQ4_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDQ5_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDQ6_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDQ7_SLAVE_DELAY, dataL); + r_ddr_setval_ach_as(PHY_RDDM_SLAVE_DELAY, dataL); + + if (ddr_mbps < (1601U * ddr_mbpsdiv * ddr_medium_div)) + { + /* 1068 - 1600 */ + r_ddr_setval_ach_as(PHY_REGULATOR_EN_CNT, 0x03U); + r_ddr_setval_ach_as(PHY_RX_CAL_ALL_DLY, 0x04U); + r_ddr_setval_ach_as(PHY_RX_PCLK_CLK_SEL, 0x02U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_TSEL_DLY, 0x02U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_OE_DLY, 0x05U); + r_ddr_setval_ach_as(PHY_RPTR_UPDATE, 0x06U); + r_ddr_setval_ach_as(PHY_WRLVL_RESP_WAIT_CNT, 0x19U); + r_ddr_setval_ach_as(PHY_RDLVL_MAX_EDGE, 0x00DBU); + r_ddr_setval_ach_as(PHY_RDDATA_EN_DLY, 0x05U); + r_ddr_setval_ach_as(PHY_RDDQS_LATENCY_ADJUST, 0x02U); + r_ddr_setval_ach_as(PHY_GTLVL_LAT_ADJ_START, 0x01U); + r_ddr_setval_ach_as(PHY_DATA_DC_WDQLVL_ENABLE, 0x00U); + r_ddr_setval_ach(PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddr_setval_ach(PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddr_setval_ach(PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE, 0x32U); + r_ddr_setval_ach(PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x01U); + r_ddr_setval_ach(PHY_PLL_CTRL, 0x1742U); + r_ddr_setval_ach(PHY_PLL_CTRL_8X, 0x3542U); + } + else if (ddr_mbps < (2134U * ddr_mbpsdiv * ddr_medium_div)) + { + /* 1601 - 2133 */ + r_ddr_setval_ach_as(PHY_REGULATOR_EN_CNT, 0x04U); + r_ddr_setval_ach_as(PHY_RX_CAL_ALL_DLY, 0x05U); + r_ddr_setval_ach_as(PHY_RX_PCLK_CLK_SEL, 0x02U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_TSEL_DLY, 0x04U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_OE_DLY, 0x07U); + r_ddr_setval_ach_as(PHY_RPTR_UPDATE, 0x07U); + r_ddr_setval_ach_as(PHY_WRLVL_RESP_WAIT_CNT, 0x1EU); + r_ddr_setval_ach_as(PHY_RDLVL_MAX_EDGE, 0x00F7U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_DLY, 0x07U); + r_ddr_setval_ach_as(PHY_RDDQS_LATENCY_ADJUST, 0x02U); + r_ddr_setval_ach_as(PHY_GTLVL_LAT_ADJ_START, 0x02U); + r_ddr_setval_ach_as(PHY_DATA_DC_WDQLVL_ENABLE, 0x00U); + r_ddr_setval_ach(PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddr_setval_ach(PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddr_setval_ach(PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE, 0x32U); + r_ddr_setval_ach(PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x01U); + r_ddr_setval_ach(PHY_PLL_CTRL, 0x1542U); + r_ddr_setval_ach(PHY_PLL_CTRL_8X, 0x3342U); + } + else + { + /* 2134 - 2750 */ + r_ddr_setval_ach_as(PHY_REGULATOR_EN_CNT, 0x05U); + r_ddr_setval_ach_as(PHY_RX_CAL_ALL_DLY, 0x06U); + r_ddr_setval_ach_as(PHY_RX_PCLK_CLK_SEL, 0x03U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_TSEL_DLY, 0x06U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_OE_DLY, 0x09U); + r_ddr_setval_ach_as(PHY_RPTR_UPDATE, 0x07U); + r_ddr_setval_ach_as(PHY_WRLVL_RESP_WAIT_CNT, 0x22U); + r_ddr_setval_ach_as(PHY_RDLVL_MAX_EDGE, 0x0116U); + r_ddr_setval_ach_as(PHY_RDDATA_EN_DLY, 0x09U); + r_ddr_setval_ach_as(PHY_RDDQS_LATENCY_ADJUST, 0x03U); + r_ddr_setval_ach_as(PHY_GTLVL_LAT_ADJ_START, 0x03U); + r_ddr_setval_ach_as(PHY_DATA_DC_WDQLVL_ENABLE, 0x00U); + r_ddr_setval_ach(PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00U); + r_ddr_setval_ach(PHY_ADR_CALVL_DLY_STEP, 0x02U); + r_ddr_setval_ach(PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE, 0x32U); + r_ddr_setval_ach(PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x02U); + r_ddr_setval_ach(PHY_PLL_CTRL, 0x1542U); + r_ddr_setval_ach(PHY_PLL_CTRL_8X, 0x3342U); + } /* (ddr_mbps < (1601U * ddr_mbpsdiv * ddr_medium_div)) */ + + if (ddr_mbps < (8U * 160U * ddr_mbpsdiv * ddr_medium_div)) + { + /* CAL_CLK(10-20MHz) */ + r_ddr_setval_ach_as(PHY_DATA_DC_CAL_CLK_SEL, 0x03U); + r_ddr_setval_ach(PHY_CLK_DC_CAL_CLK_SEL, 0x02U); + r_ddr_setval_ach(PHY_CAL_CLK_SELECT_0, 0x03U); + } + else if (ddr_mbps < (8U * 320U * ddr_mbpsdiv * ddr_medium_div)) + { + /* CAL_CLK(10-20MHz) */ + r_ddr_setval_ach_as(PHY_DATA_DC_CAL_CLK_SEL, 0x04U); + r_ddr_setval_ach(PHY_CLK_DC_CAL_CLK_SEL, 0x03U); + r_ddr_setval_ach(PHY_CAL_CLK_SELECT_0, 0x04U); + } + else + { + /* CAL_CLK(10-20MHz) */ + r_ddr_setval_ach_as(PHY_DATA_DC_CAL_CLK_SEL, 0x05U); + r_ddr_setval_ach(PHY_CLK_DC_CAL_CLK_SEL, 0x04U); + r_ddr_setval_ach(PHY_CAL_CLK_SELECT_0, 0x05U); + } /* (ddr_mbps < (8U * 160U * ddr_mbpsdiv * ddr_medium_div)) */ + + r_ddr_setval_ach(PHY_FREQ_SEL_MULTICAST_EN, 0x01U); + } /* (med_freq_en == 0x01U) */ +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ +} + +/******************************************************************************* + * CONFIGURE DDR REGISTERS + ******************************************************************************/ +static void r_ddr_config(void) +{ + uint32_t ch, slice; + uint32_t dataL; + uint8_t high_byte[SLICE_CNT]; + + r_foreach_vch((ch)) + { + /*********************************************************************** + * BOARD SETTINGS (DQ, DM, VREF_DRIVING) + ***********************************************************************/ + for (slice = 0U; slice < SLICE_CNT; slice++) + { + high_byte[slice] = ((uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap) >> (4U * slice)) % 2U; + r_ddr_setval_s(ch, slice, PHY_DQ_DM_SWIZZLE0, Boardcnf->ch[ch].bdcfg_dq_swap[slice]); + r_ddr_setval_s(ch, slice, PHY_DQ_DM_SWIZZLE1, (uint32_t)(Boardcnf->ch[ch].bdcfg_dm_swap[slice])); + if (high_byte[slice] != 0U) + { + /* HIGHER 16 BYTE */ + r_ddr_setval_s(ch, slice, PHY_CALVL_VREF_DRIVING_SLICE, 0x00U); + } + else + { + /* LOWER 16 BYTE */ + r_ddr_setval_s(ch, slice, PHY_CALVL_VREF_DRIVING_SLICE, 0x01U); + } + } + dataL = (0x000000FFU & (uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap)); + r_ddr_setval(ch, PHY_DATA_BYTE_ORDER_SEL, (0x76543200U | dataL)); + + /*********************************************************************** + * BOARD SETTINGS (CA, ADDR_MUX) + ***********************************************************************/ + dataL = (0x0FFFFFFFU & (uint32_t)(Boardcnf->ch[ch].bdcfg_ca_swap)); + + /* --- ADDR_MUX --- */ + r_ddr_setval(ch, PI_ADDRESS_MUX_0, (0x000000FU & dataL)); + r_ddr_setval(ch, PI_ADDRESS_MUX_1, (0x000000FU & (dataL >> 4))); + r_ddr_setval(ch, PI_ADDRESS_MUX_2, (0x000000FU & (dataL >> 8))); + r_ddr_setval(ch, PI_ADDRESS_MUX_3, (0x000000FU & (dataL >> 12))); + r_ddr_setval(ch, PI_ADDRESS_MUX_4, (0x000000FU & (dataL >> 16))); + r_ddr_setval(ch, PI_ADDRESS_MUX_5, (0x000000FU & (dataL >> 20))); + r_ddr_setval(ch, PI_ADDRESS_MUX_6, (0x000000FU & (dataL >> 24))); + + /* --- ADR_CALVL_SWIZZLE --- */ + r_ddr_setval(ch, PHY_ADR_CALVL_SWIZZLE0, dataL); + + /*********************************************************************** + * BOARD SETTINGS (CS) + ***********************************************************************/ + /* --- CKE_MUX --- */ + /* SoC CKE -> DRAM CS */ + dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_cs_swap); + r_ddr_setval(ch, PI_CKE_MUX_0, (0x0FU & dataL)); + r_ddr_setval(ch, PI_CKE_MUX_1, (0x0FU & (dataL >> 4))); + r_ddr_setval(ch, PHY_CS_ACS_ALLOCATION_BIT2_2, ((0x0FU & (dataL)) + 1U)); + r_ddr_setval(ch, PHY_CS_ACS_ALLOCATION_BIT3_2, ((0x0FU & (dataL >> 4)) + 1U)); + + /*********************************************************************** + * mask CS_MAP if RANK1 is not found + ***********************************************************************/ + if ((ch_have_this_cs[1] & (1U << ch)) == 0x0U) + { + r_ddr_setval(ch, PHY_ADR_CALVL_RANK_CTRL, 0x00U); + for (slice = 0U; slice < SLICE_CNT; slice++) + { + r_ddr_setval_s(ch, slice, PHY_PER_CS_TRAINING_EN, 0x00U); + } + } + } + + r_foreach_vch((ch)) + { + /* --- DATA_BYTE_SWAP --- */ + dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_dqs_swap); + r_ddr_setval(ch, PI_DATA_BYTE_SWAP_EN, 0x01U); + r_ddr_setval(ch, PI_DATA_BYTE_SWAP_SLICE0, dataL & 0x0FU); + r_ddr_setval(ch, PI_DATA_BYTE_SWAP_SLICE1, (dataL >> 4) & 0x0FU); + + if ((ch_have_this_cs[1] & (1U << ch)) == 0x0U) + { + r_ddr_setval(ch, PI_CS_MAP, 0x01U); + } + } +} + +/******************************************************************************* + * DBSC register setting functions + ******************************************************************************/ +static void r_dbsc_regset_pre(void) +{ + uint32_t ch, cs; + + /*********************************************************************** + * PRIMARY SETTINGS + ***********************************************************************/ + /* LPDDR5, BL=16, DFI interface */ + r_dbsc_write_32(DBSC_DBMEMKIND, 0x0000000CU); + r_dbsc_write_32(DBSC_DBMEMKINDA, 0x0000000CU); + r_dbsc_write_32(DBSC_DBBL, 0x00000002U); + r_dbsc_write_32(DBSC_DBBLA, 0x00000002U); + r_dbsc_write_32(DBSC_DBPHYCONF0, 0x00000001U); + + r_dbsc_write_32(DBSC_DBSYSCONF0, 0x00000001U); + + /* FREQRATIO=2 */ + r_dbsc_write_32(DBSC_DBSYSCONF1, 0x00020000U); + r_dbsc_write_32(DBSC_DBSYSCONF1A, 0x00000000U); + + r_dbsc_write_32(DBSC_DBSYSCONF2, 0x00000001U); + r_dbsc_write_32(DBSC_DBSYSCONF2A, 0x00000241U); + + r_foreach_ech((ch)) + { + for (cs = 0U; cs < CS_CNT; cs++) + { + if (ddr_density[ch][cs] == 0xFFU) + { + mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00U); + mmio_write_32(DBSC_DBMEMCONFA(ch, cs), 0x00U); + } + else + { + mmio_write_32(DBSC_DBMEMCONF(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs])); + mmio_write_32(DBSC_DBMEMCONFA(ch, cs), DBMEMCONF_REGD(ddr_density[ch][cs])); + } + } + } +} + +static void r_dbsc_regset(void) +{ + uint32_t tmp[4]; + + /* DBTR0.cl : RL */ + r_dbsc_write_32(DBSC_DBTR(0U), RL); + + /* DBTR1.cwl : WL */ + r_dbsc_write_32(DBSC_DBTR(1U), WL); + + /* DBTR2.al = 0 */ + r_dbsc_write_32(DBSC_DBTR(2U), 0x00000000U); + + /* DBTR3.trcd : tRCD */ + r_dbsc_write_32(DBSC_DBTR(3U), js2[JS2_tRCD]); + + /* DBTR4.trpa,trp : tRPab,tRPpb */ + r_dbsc_write_32(DBSC_DBTR(4U), ((js2[JS2_tRPab] << 16) | js2[JS2_tRPpb])); + + /* DBTR5.trc : tRCpb */ + r_dbsc_write_32(DBSC_DBTR(5U), js2[JS2_tRCpb]); + + /* DBTR6.tras : tRAS */ + r_dbsc_write_32(DBSC_DBTR(6U), js2[JS2_tRAS]); + + /* DBTR7.trrd : tRRD */ + r_dbsc_write_32(DBSC_DBTR(7U), (((js2[JS2_tRRD] - 1U) << 16) | (js2[JS2_tRRD] - 1U))); + + /* DBTR8.tfaw : tFAW */ + r_dbsc_write_32(DBSC_DBTR(8U), (js2[JS2_tFAW] - 1U)); + + /* DBTR9.trdpr : nRBTP */ + r_dbsc_write_32(DBSC_DBTR(9U), js1[js1_ind].nRBTP); + + /* DBTR10.twr : nWR */ + r_dbsc_write_32(DBSC_DBTR(10U), js1[js1_ind].nWR); + + /* DBTR11.trdwr : RL + BL/n_max + RU(tWCK2DQO(max)/tCK) + RD(tRPST/tCK) - ODTLon - RD(tODTon(min)/tCK) + 1 + feature */ + r_dbsc_write_32(DBSC_DBTR(11U), (RL + 4U + js2[JS2_tWCK2DQO_HF] + 0U - js1[js1_ind].ODTLon - (js2[JS2_tODTon_min] - 1U) + 1U + 0U)); + + /* DBTR12.twrrd_s,twrrd : WL + BL/2 + tWTR_S,WL + BL + tWTR_L */ + r_dbsc_write_32(DBSC_DBTR(12U), (((WL + 2U + js2[JS2_tWTR_S]) << 16) | (WL + 4U + js2[JS2_tWTR_L]))); + + /* DBTR13.trfcab : tRFCab */ + r_dbsc_write_32(DBSC_DBTR(13U), js2[JS2_tRFCab]); + + /* DBTR14.tcscal,tckehdll,tckeh : tCSCAL,tXP,tXP */ + r_dbsc_write_32(DBSC_DBTR(14U), ((js2[JS2_tCSCAL] << 24) | (js2[JS2_tXP] << 16) | js2[JS2_tXP])); + + /* DBTR15.tespd,tckesr,tckel : tESPD = 2,tSR,tSR */ + r_dbsc_write_32(DBSC_DBTR(15U), ((0x02U << 24) | (js2[JS2_tSR] << 16) | js2[JS2_tSR])); + + /* DBTR16 */ + /* wdql(tphy_wrlat + tphy_wrdata) */ + tmp[0] = (WL * 4U) - 1U + 5U; + /* dqenltcy(tphy_wrlat) */ + tmp[1] = (WL * 4U) - 2U - 2U + 5U; + /* dql(tphy_rdlat + trddata_en) : RL * 4 + phy_rptr_update + phy_rddqs_latency_adjust + 39 */ + tmp[2] = (RL * 4U) + r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE) + r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST) + 39U; + /* dqienltncy(trddata_en) : RL * 4 - phy_rddata_en_dly_X + 4 * phy_wck_freq_ratio_X */ + tmp[3] = (RL * 4U) + 4U - r_ddrtbl_getval(DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY); + r_dbsc_write_32(DBSC_DBTR(16U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR17.tmodrd,tmod : tMRR,tMRW */ + r_dbsc_write_32(DBSC_DBTR(17U), ((js2[JS2_tMRR] << 24) | (js2[JS2_tMRW] << 16))); + + /* DBTR18.rodtl,rodta = 0 */ + r_dbsc_write_32(DBSC_DBTR(18U), 0x00000000U); + + /* DBTR19.tzqcl,tzqcs = 0 */ + r_dbsc_write_32(DBSC_DBTR(19U), 0x00000000U); + + /* DBTR20.txsdll,txs : tXSR,tXSR */ + r_dbsc_write_32(DBSC_DBTR(20U), ((js2[JS2_tXSR] << 16) | js2[JS2_tXSR])); + + /* DBTR21.tccd */ + r_dbsc_write_32(DBSC_DBTR(21U), ((ddr_tccd << 16) | (ddr_tccd * 2U))); + + /* DBTR22.tzqcal,tzqlat : tZQCAL,tZQLAT */ + r_dbsc_write_32(DBSC_DBTR(22U), ((js2[JS2_tZQCALns] << 16) | js2[JS2_tZQLAT])); + + /* DBTR23.rrspc = 0 */ + r_dbsc_write_32(DBSC_DBTR(23U), 0x00000000U); + + /* DBTR24 */ + /* wrcslat(tphy_wrcslat) */ + tmp[0] = (WL * 4U) - 2U; + /* wrcsgap(tphy_wrcsgap) */ + tmp[1] = 0x0CU; + /* rdcslat(tphy_rdcslat) */ + tmp[2] = RL * 4U; + /* rdcsgap(tphy_rdcsgap) */ + tmp[3] = 0x0CU; + r_dbsc_write_32(DBSC_DBTR(24U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR25 */ + r_dbsc_write_32(DBSC_DBTR(25U), 0x00000000U); + + /* DBTR26 */ + r_dbsc_write_32(DBSC_DBTR(26U), 0x00000000U); + + /* DBTR27.tpdn : tPDN */ + r_dbsc_write_32(DBSC_DBTR(27U), js2[JS2_tPDN]); + + /* DBTR28.txsrdsm : tXSR_DSM */ + r_dbsc_write_32(DBSC_DBTR(28U), js2[JS2_tXSR_DSM]); + + /* DBTR29.tdsmxp : tXDSM_XP */ + r_dbsc_write_32(DBSC_DBTR(29U), js2[JS2_tXDSM_XP]); + + /* DBTR30.tcmdpd : tCMDPD = 3 */ + r_dbsc_write_32(DBSC_DBTR(30U), 0x00000003U); + + /* DBTR31.twck2dqomax,twck2dqimax : tWCK2DQO_HF/LF,tWCK2DQI_HF/LF */ + r_dbsc_write_32(DBSC_DBTR(31U), ((js2[JS2_tWCK2DQO_HF] << 4) | js2[JS2_tWCK2DQI_HF])); + + /* DBTR32 */ + /* twckenr */ + tmp[0] = (js1[js1_ind].WCKENLR * 4U) + 4U - 1U; + /* twckenw */ + tmp[1] = (js1[js1_ind].WCKENLW * 4U) + 4U - 1U; + /* twckenlf */ + tmp[2] = (js1[js1_ind].WCKENLF * 4U) + 4U; + /* twckpresta */ + tmp[3] = js1[js1_ind].WCKPRESTA * 4U; + r_dbsc_write_32(DBSC_DBTR(32U), ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR33 */ + /* twcktgl */ + tmp[0] = 4U; + /* twckdis : (RL+ bl/n_max) * 4 + RU(tWCKPST/tWCK),tWCKPST = MR10[3:2] = 2.5 */ + tmp[1] = ((RL + 4U) * 4U) + 3U; + r_dbsc_write_32(DBSC_DBTR(33U), ((tmp[1] << 8) | tmp[0])); + + /* DBTR34 */ + /* twcksus = 4 */ + tmp[0] = 4U; + /* twckpst : RU(tWCKPST/tCK),tWCKPST = MR10[3:2] = 2.5 */ + tmp[1] = 1U; + r_dbsc_write_32(DBSC_DBTR(34U), ((tmp[1] << 8) | tmp[0])); + + /* DBTR35 */ + /* trd2wckoff : RL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[0] = RL + 4U + 0U +1U; + /* twr2wckoff : WL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[1] = WL + 4U + 0U +1U; + r_dbsc_write_32(DBSC_DBTR(35U), ((tmp[1] << 16) | tmp[0])); + + /* DBTR36 */ + /* twssuswrx : CAS(WCKSUS)WRX */ + tmp[0] = 3U; + /* twsoffwrx : CAS(WS_OFF)WRX */ + tmp[1] = 3U; + /* twsfswrx : CAS(WS_FS)WRX */ + tmp[2] = 2U; + r_dbsc_write_32(DBSC_DBTR(36U), ((tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBTR37.tosco : tOSCODQI */ + r_dbsc_write_32(DBSC_DBTR(37U), js2[JS2_tOSCODQI]); + + /* DBRNK2 */ + /* rnkrr = 12 */ + r_dbsc_write_32(DBSC_DBRNK(2U), 0x000000CCU); + + /* DBRNK3 */ + /* rnkrw = 6 */ + r_dbsc_write_32(DBSC_DBRNK(3U), 0x00000066U); + + /* DBRNK4 */ + /* rnkwr = 6 */ + r_dbsc_write_32(DBSC_DBRNK(4U), 0x00000066U); + + /* DBRNK5 */ + /* rnkww = 14 */ + r_dbsc_write_32(DBSC_DBRNK(5U), 0x000000EEU); + + /* DBBUS0CNF1 */ + /* BGADM */ + r_dbsc_write_32(DBSC_DBBUS0CNF1, 0x00010000U); + + /*********************************************************************** + * timing registers for Scheduler + ***********************************************************************/ + /* SCFCTST0 */ + /* scpreact */ + tmp[0] = 1UL * js2[JS2_tRPpb] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* scactrdwr */ + tmp[1] = 1UL * (WL + 2U + 1U + js1[js1_ind].nWR + js2[JS2_tRPpb]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* scrdacrt */ + tmp[2] = 1UL * ((js1[js1_ind].nRBTP + 2U) + js2[JS2_tRPpb]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* scactact */ + tmp[3] = 1UL * js2[JS2_tRCpb] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + r_dbsc_write_32(DBSC_DBSCHFCTST0, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* SCFCTST1 */ + /* scasyncofs */ + tmp[0] = 12U; + /* scactrdwr */ + tmp[1] = 1UL * js2[JS2_tRCD] * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* scwrrd */ + tmp[2] = 1UL * (mmio_read_32(DBSC_DBTR(12U)) & 0xFFU) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + /* scrdwr */ + tmp[3] = 1UL * (mmio_read_32(DBSC_DBTR(11U)) & 0xFFU) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + r_dbsc_write_32(DBSC_DBSCHFCTST1, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /* DBSCHRW1 */ + /* sctrfcab */ + tmp[0] = 1UL * (js2[JS2_tRFCab] + js2[JS2_tZQLAT]) * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv; + r_dbsc_write_32(DBSC_DBSCHRW1, tmp[0]); + + /* DBSCHTR0 */ + /* scdt0 */ + tmp[0] = (1UL * 4U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + /* scdt1 */ + tmp[1] = (1UL * 8U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + /* scdt2 */ + tmp[2] = (1UL * 12U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + /* scdt3 */ + tmp[3] = (1UL * 16U * bus_clk * ddr_mbpsdiv * 8U / ddr_mbps / bus_clkdiv) - 1U; + r_dbsc_write_32(DBSC_DBSCHTR0, ((tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0])); + + /*********************************************************************** + * QOS and CAM + ***********************************************************************/ + r_dbsc_write_32(DBSC_DBBCAMDIS, 0x00000001U); +} + +static void r_dbsc_regset_post(void) +{ + uint32_t dataL; + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + uint32_t ctrl_clk; + uint32_t clk_count; + uint32_t phymster_req_interval; +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + + r_dbsc_write_32(DBSC_DBDBICNT, 0x00000003U); + + /* set REFCYCLE */ + dataL = DBSC_REFINT * ddr_mbps / 8000U / ddr_mbpsdiv; + /* refpmax=8 */ + r_dbsc_write_32(DBSC_DBRFCNF1, 0x00080000U | (dataL & 0x0000FFFFU)); + /* refpmin=1 */ + r_dbsc_write_32(DBSC_DBRFCNF2, 0x00010000U | DBSC_REFINTS); + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000U); +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + +#if (RCAR_PERIODIC_WRITE_TRAINING != 0U) + /* Periodic-WriteDQ Training setting */ + r_ddr_setval_ach(PI_WDQLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_WDQLVL_VREF_EN, 0x00U); + r_ddr_setval_ach_as(PHY_DATA_DC_WDQLVL_ENABLE, 0x00U); + r_ddr_setval_ach(PI_WDQLVL_PERIODIC, 0x01U); +#endif /* (RCAR_PERIODIC_WRITE_TRAINING != 0U) */ + +#if (RCAR_PERIODIC_READ_TRAINING != 0U) + /* Periodic-ReadDQ Training setting */ + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F2, 0x00U); + r_ddr_setval_ach_as(PHY_RDLVL_DLY_STEP, 0x04U); + r_ddr_setval_ach(PI_RDLVL_PERIODIC, 0x01U); +#endif /* (RCAR_PERIODIC_READ_TRAINING != 0U) */ + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + /* DFI_PHYMSTR_ACK , WTmode = b'01 */ + r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011U); +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + + /* periodic SoC zqcal enable */ + r_ddr_setval_ach(PHY_CAL_MODE_0, r_ddrtbl_getval(DDR_PHY_ADR_G_REGSET, PHY_CAL_MODE_0) | 0x02U); + +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + if (med_freq_en == 0x01U) + { + /* Prepare DFS after initialization */ + /* Medium frequency mode (F1) */ + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F1, 0x03U); + r_ddr_setval_ach(PI_RDLVL_EN_F1, 0x01U); + r_ddr_setval_ach(PI_WDQLVL_EN_F1, 0x03U); + /* High frequency mode (F2) */ + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x03U); + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_WDQLVL_EN_F2, 0x03U); + } +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ + + /* periodic dram zqcal enable */ + r_dbsc_write_32(DBSC_DBCALCNF, 0x01000010U); + + /* periodic phy ctrl update enable */ + r_dbsc_write_32(DBSC_DBDFICUPDCNF, 0x504C0001U); + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) + { + /* SRX */ + r_send_dbcmd(0x0A840001U); + } +#endif /* DDR_BACKUPMODE */ + /* set Auto Refresh */ + r_dbsc_write_32(DBSC_DBRFEN, 0x00000001U); + +#if ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) + /* Periodic-WriteDQ/ReadDQ Training Interval setting */ + phymster_req_interval = PERIODIC_TRAINING_INTERVAL - 3000U; + clk_count = 1024U - (r_ddrtbl_getval_pi(DDR_PI_REGSET, PI_LONG_COUNT_MASK) * 32U); + ctrl_clk = ddr_mbps / ddr_mbpsdiv / 8U; + dataL = phymster_req_interval * ctrl_clk / clk_count; +#endif /* ((RCAR_PERIODIC_WRITE_TRAINING != 0U) || (RCAR_PERIODIC_READ_TRAINING != 0U)) */ + +#if (RCAR_PERIODIC_WRITE_TRAINING != 0U) + r_ddr_setval_ach(PI_WDQLVL_INTERVAL, dataL); +#endif /* (RCAR_PERIODIC_WRITE_TRAINING != 0U) */ + +#if ((RCAR_PERIODIC_READ_TRAINING != 0U) && (RCAR_PERIODIC_TRAINING_SEPARATE_MODE == 0U)) + r_ddr_setval_ach(PI_RDLVL_INTERVAL, dataL); +#endif /* ((RCAR_PERIODIC_READ_TRAINING != 0U) && (RCAR_PERIODIC_TRAINING_SEPARATE_MODE == 0U)) */ + + /* dram access enable */ + r_dbsc_write_32(DBSC_DBACEN, 0x00000001U); + + MSG_LF("dbsc_regset_post(done)\n"); +} + +/******************************************************************************* + * DFI_INIT_START and PI_TRAINING + ******************************************************************************/ +static uint32_t r_pi_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + uint32_t frqchg_req; + uint32_t flag; + uint32_t complete_ng; + uint32_t ca_training_ng; + uint32_t wr_training_ng; + uint32_t gt_training_ng; + uint32_t rd_training_ng; + uint32_t wdq_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + /*********************************************************************** + * init start + **********************************************************************/ +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + if (med_freq_en == 0x01U) + { + r_ddr_setval_ach(PI_FREQ_MAP, 0x07U); + r_ddr_setval_ach(PI_INIT_WORK_FREQ, 0x02U); + r_ddr_setval_ach(PI_CALVL_EN_F1, 0x01U); + r_ddr_setval_ach(PI_WRLVL_EN_F1, 0x01U); + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F1, 0x01U); + r_ddr_setval_ach(PI_WRDCM_LVL_EN_F1, 0x00U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_EN_F1, 0x00U); + r_ddr_setval_ach(PI_RDLVL_EN_F1, 0x01U); + r_ddr_setval_ach(PI_WDQLVL_EN_F1, 0x01U); + r_ddr_setval_ach(PI_RDLVL_RDDQ_EN_F1, 0x00U); + + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F1, 0x00U); + r_ddr_setval_ach_as(PHY_VREF_TRAINING_CTRL, 0x00U); + r_ddr_setval_ach(PI_WDQLVL_VREF_EN, 0x00U); + } +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ + + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WRDCM_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WDQLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_SEQ_ARRAY_81, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_82, 0x00000000U); + + /* PI_START */ + r_ddr_setval_ach(PI_START, 0x01U); + +#ifdef DDR_BACKUPMODE + if (ddrBackup == DRAM_BOOT_STATUS_WARM) + { + r_ddr_setval_ach(PI_DLL_RST, 0x01U); + r_ddr_setval_ach(PI_PWRUP_SREFRESH_EXIT, 0x00U); + } +#endif /* DDR_BACKUPMODE */ + + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000020U); + } + + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000021U); + } + + /* Dummy PDE */ + r_send_dbcmd(0x08840000U); + + /* PDX */ + r_send_dbcmd(0x08840001U); + + /*********************************************************************** + * wait init_complete + ***********************************************************************/ + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + frqchg_req = 0U; + for (ch = 0U; ch < DRAM_CH_CNT; ch++) + { + if ((((~phytrainingok) & ddr_phyvalid) & (1U << ch)) != 0x0U) + { + if ((mmio_read_32(DBSC_DBPDSTAT0(ch)) & 0x01U) != 0x0U) + { + frqchg_req = 1U; + break; + } + } + } + + if (frqchg_req != 0x0U) + { + flag = r_pll3_freq(); + if (flag != 0x0U) + { + break; + } + } + else + { + r_foreach_vch((ch)) + { + dataL = mmio_read_32(DBSC_DBDFISTAT(ch)); + if ((dataL & 0x00000001U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + }/* frqchg_req != 0x0U */ + } + + /* dbdficnt0: + * dfi_dram_clk_disable=0 + * dfi_frequency = 0 + * freq_ratio = 10 (4:1) + * init_start =0 + */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBDFICNT(ch), 0x00000020U); + } + + /* DFI_PHYMSTR_ACK */ + r_dbsc_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001U); + + complete_ng = 0x0U; + ca_training_ng = 0x0U; + wr_training_ng = 0x0U; + gt_training_ng = 0x0U; + rd_training_ng = 0x0U; + wdq_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* CA/CS Training Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 4)); /* PI_CALVL_ERROR_BIT */ + dataL |= (r_ddr_getval(ch, PHY_ADR_CALVL_OBS1) & (0x3U << 30)); /* error on decrement/increment pass */ + dataL |= (r_ddr_getval(ch, PHY_ADR_CALVL_OBS2) & (0x3U << 24)); /* start outside of initial search range */ + dataL |= (r_ddr_getval(ch, PHY_CSLVL_OBS1) & (0xFU << 28)); /* CSlvl error */ + if (dataL != 0x0U) + { + ca_training_ng |= 1U << ch; + MSG_LF("pi_training_error:1\n"); + } + + /* Wrlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3)); /* PI_WRLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12)); /* SLICE0 wrlvl error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12)); /* SLICE1 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS); /* SLICE0 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS); /* SLICE1 wrlvl error */ + if (dataL != 0x0U) + { + wr_training_ng |= 1U << ch; + MSG_LF("pi_training_error:2\n"); + } + +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + if (med_freq_en == 0x01U) + { + /* Gtlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 2)); /* PI_RDLVL_GATE_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7)); /* SLICE0 delay setup error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7)); /* SLICE1 delay setup error */ + if (dataL != 0x0U) + { + gt_training_ng |= 1U << ch; + MSG_LF("pi_training_error:3\n"); + } + + /* Rdlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 1)); /* PI_RDLVL_ERROR_BIT */ + if (dataL != 0x0U) + { + rd_training_ng |= 1U << ch; + MSG_LF("pi_training_error:4\n"); + } + + /* Wdqlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 5)); /* PI_WDQLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18)); /* SLICE0 wdqlvl_fail_dqZ */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18)); /* SLICE1 wdqlvl_fail_dqZ */ + if (dataL != 0x0U) + { + wdq_training_ng |= 1U << ch; + MSG_LF("pi_training_error:5\n"); + } + } +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ + } + + complete_ng = (wdq_training_ng | rd_training_ng | gt_training_ng | wr_training_ng | ca_training_ng); + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x01U); + } + + return phytrainingok; +} + +/******************************************************************************* + * Write Leveling Cycle Adjust + ******************************************************************************/ +static void r_write_leveling_adjust(void) +{ + uint32_t ch; + uint32_t result_hard0; + uint32_t result_hard1; + uint32_t avg; + uint32_t avg_frac; + uint32_t avg_cycle; + + r_foreach_vch((ch)) + { + /* SLICE0 */ + result_hard0 = r_ddr_getval_s(ch, 0U, PHY_WRLVL_HARD0_DELAY_OBS); + result_hard1 = r_ddr_getval_s(ch, 0U, PHY_WRLVL_HARD1_DELAY_OBS); + + if (result_hard0 <= result_hard1) + { + avg = (result_hard0 + result_hard1) / 2U; + } + else + { + avg = (result_hard0 + result_hard1 + 0x400U) / 2U; + } + avg_frac = avg & 0xFFU; + avg_cycle = (avg >> 8) & 0x3U; + + if (avg_cycle == 0x3U) + { + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_DEC, 0x1U); + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_ADD, 0x0U); + } + else + { + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_DEC, 0x0U); + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_ADD, avg_cycle); + } + r_ddr_setval_s(ch, 0U, PHY_WRITE_PATH_LAT_FRAC, avg_frac); + + /* SLICE1 */ + result_hard0 = r_ddr_getval_s(ch, 1U, PHY_WRLVL_HARD0_DELAY_OBS); + result_hard1 = r_ddr_getval_s(ch, 1U, PHY_WRLVL_HARD1_DELAY_OBS); + + if (result_hard0 <= result_hard1) + { + avg = (result_hard0 + result_hard1) / 2U; + } + else + { + avg = (result_hard0 + result_hard1 + 0x400U) / 2U; + } + avg_frac = avg & 0xFFU; + avg_cycle = (avg >> 8) & 0x3U; + + if (avg_cycle == 0x3U) + { + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_DEC, 0x1U); + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_ADD, 0x0U); + } + else + { + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_DEC, 0x0U); + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_ADD, avg_cycle); + } + r_ddr_setval_s(ch, 1U, PHY_WRITE_PATH_LAT_FRAC, avg_frac); + } + + r_ddr_setval_ach_as(SC_PHY_WCK_CALC, 0x01U); +} + +/******************************************************************************* + * Re-run Write Leveling & Read Gate Training + ******************************************************************************/ +static uint32_t r_wl_gt_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + + uint32_t complete_ng; + uint32_t wr_training_ng; + uint32_t gt_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + r_ddr_setval_ach(PI_CALVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x01U); + r_ddr_setval_ach(PI_SEQ_ARRAY_29, 0x181F0000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_64, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_65, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_66, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_67, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_68, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_69, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_70, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_71, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_72, 0x00000000U); + r_ddr_setval_ach(PI_TRAIN_ALL_FREQ_REQ, 0x01U); + + /* Freq Change High to High */ + dataL = r_pll3_freq(); + if (dataL != 0x0U) + { + return (1); + } + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if ((dataL & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + wr_training_ng = 0x0U; + gt_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Wrlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3)); /* PI_WRLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12)); /* SLICE0 wrlvl error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12)); /* SLICE1 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS); /* SLICE0 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS); /* SLICE1 wrlvl error */ + if (dataL != 0x0U) + { + wr_training_ng |= 1U << ch; + MSG_LF("wl_gt_training_error:1\n"); + } + /* Gtlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 2)); /* PI_RDLVL_GATE_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7)); /* SLICE0 delay setup error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7)); /* SLICE1 delay setup error */ + if (dataL != 0x0U) + { + gt_training_ng |= 1U << ch; + MSG_LF("wl_gt_training_error:2\n"); + } + } + + complete_ng = (wr_training_ng | gt_training_ng); + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x01U); + } + + return phytrainingok; +} + +/******************************************************************************* + * Write DCA Training + ******************************************************************************/ +static void r_write_dca(void) +{ + uint32_t ch; + uint32_t dataL; + uint32_t phytrainingok; + uint32_t retry; + const uint32_t RETRY_MAX = 0x10000U; + + r_ddr_setval_ach_as(PHY_DATA_DC_CAL_START, 0x01U); + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = (r_ddr_getval_s(ch, 0U, PHY_DATA_DC_CAL_START)) | (r_ddr_getval_s(ch, 1U, PHY_DATA_DC_CAL_START)); + if (dataL == 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } +} + +/******************************************************************************* + * DRAM DCA Training and Calculations + ******************************************************************************/ +static uint32_t r_dramdca_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t dataL; + uint32_t rank; + uint32_t dca_result_l_0[DRAM_CH_CNT][CS_CNT]; /* DCA_result_lower_flip0_[ch][cs] */ + uint32_t dca_result_u_0[DRAM_CH_CNT][CS_CNT]; /* DCA_result_upper_flip0_[ch][cs] */ + uint32_t dca_result_l_1[DRAM_CH_CNT][CS_CNT]; /* DCA_result_lower_flip1_[ch][cs] */ + uint32_t dca_result_u_1[DRAM_CH_CNT][CS_CNT]; /* DCA_result_upper_flip1_[ch][cs] */ + uint32_t tempu; + uint32_t templ; + + const uint32_t mr30_conv[16] = + { + 0x08U, 0x07U, 0x06U, 0x05U, 0x04U, 0x03U, 0x02U, 0x01U, + 0x00U, 0x09U, 0x0AU, 0x0BU, 0x0CU, 0x0DU, 0x0EU, 0x0FU + }; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + /*********************************************************************** + * Run DRAM DCA Training for Flip-0 + ***********************************************************************/ + r_ddr_setval_ach(PI_DCMLVL_CS_SW, rank); + + /* DRAMDCA go */ + r_ddr_setval_ach(PI_DRAMDCA_LVL_REQ, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = r_pi_int_ack_0_assert(26U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + /* result for DRAMDCA flip-0 */ + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS0_F2); + dca_result_u_0[ch][0] = mr30_conv[dataL >> 4]; + dca_result_l_0[ch][0] = mr30_conv[dataL & 0x0FU]; + if ((rank & 0x02U) != 0x0U) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS1_F2); + dca_result_u_0[ch][1] = mr30_conv[dataL >> 4]; + dca_result_l_0[ch][1] = mr30_conv[dataL & 0x0FU]; + } + } + + /*********************************************************************** + * Run DRAM DCA Training for Flip-1 + ***********************************************************************/ + r_ddr_setval_ach(PI_DRAMDCA_FLIP_MASK, 0x01U); + r_ddr_setval_ach(PI_SEQ_ARRAY_333, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_334, 0x00000000U); + r_ddr_setval_ach(PI_SEQ_ARRAY_335, 0x00000000U); + + /* DRAMDCA go */ + r_ddr_setval_ach(PI_DRAMDCA_LVL_REQ, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = r_pi_int_ack_0_assert(26U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + /* result for DRAMDCA flip-1 */ + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS0_F2); + dca_result_u_1[ch][0] = mr30_conv[dataL >> 4]; + dca_result_l_1[ch][0] = mr30_conv[dataL & 0x0FU]; + if ((rank & 0x02U) != 0x0U) + { + dataL = r_ddr_getval(ch, PI_DARRAY3_20_CS1_F2); + dca_result_u_1[ch][1] = mr30_conv[dataL >> 4]; + dca_result_l_1[ch][1] = mr30_conv[dataL & 0x0FU]; + } + } + + /*********************************************************************** + * Calculate and set DRAMDCA value + ***********************************************************************/ + r_foreach_vch((ch)) + { + /* CS0 */ + tempu = (dca_result_u_0[ch][0] + dca_result_u_1[ch][0]) / 2U; + templ = (dca_result_l_0[ch][0] + dca_result_l_1[ch][0]) / 2U; + dataL = (mr30_conv[tempu] << 4) | (mr30_conv[templ]); + r_ddr_setval(ch, PI_DARRAY3_20_CS0_F2, dataL); + if ((rank & 0x02U) != 0x0U) + { + /* CS1 */ + tempu = (dca_result_u_0[ch][1] + dca_result_u_1[ch][1]) / 2U; + templ = (dca_result_l_0[ch][1] + dca_result_l_1[ch][1]) / 2U; + dataL = (mr30_conv[tempu] << 4) | (mr30_conv[templ]); + r_ddr_setval(ch, PI_DARRAY3_20_CS1_F2, dataL); + } + } + + /* set DRAMDCA value in MR30 */ + r_ddr_setval_ach(PI_SEQ_ARRAY_349, 0x01A11E14U); + r_ddr_setval_ach(PI_SEQ_ARRAY_350, 0x001F0000U); + r_ddr_setval_ach(PI_SEQ_DEC_SW_CS, rank); + r_ddr_setval_ach(PI_SW_SEQ_START, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = r_pi_int_ack_0_assert(18U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + r_ddr_setval_ach(PI_SEQ_DEC_SW_CS, 0x00U); + r_ddr_setval_ach(PI_DRAMDCA_FLIP_MASK, 0x02U); + r_ddr_setval_ach(PI_SEQ_ARRAY_333, 0x001101FCU); + r_ddr_setval_ach(PI_SEQ_ARRAY_334, 0x00211A00U); + r_ddr_setval_ach(PI_SEQ_ARRAY_335, 0x00051500U); + + return phytrainingok; +} + +/******************************************************************************* + * Re-run Write Leveling + ******************************************************************************/ +static uint32_t r_write_leveling(void) +{ + uint32_t ch; + uint32_t rank; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + uint32_t complete_ng; + uint32_t wr_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + r_ddr_setval_ach(PI_CALVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WRDCM_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_DRAMDCA_LVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_WRLVL_CS_SW, rank); + r_ddr_setval_ach(PI_WRLVL_REQ, 0x01U); + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = ((r_ddr_getval(ch, PI_INT_STATUS)) >> 27); + if ((dataL & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + wr_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Wrlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 3)); /* PI_WRLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12)); /* SLICE0 wrlvl error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WRLVL_STATUS_OBS) & (0x1U << 12)); /* SLICE1 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 0U, PHY_WRLVL_ERROR_OBS); /* SLICE0 wrlvl error */ + dataL |= r_ddr_getval_s(ch, 1U, PHY_WRLVL_ERROR_OBS); /* SLICE1 wrlvl error */ + if (dataL != 0x0U) + { + wr_training_ng |= 1U << ch; + MSG_LF("write_leveling_error:1\n"); + } + } + + complete_ng = wr_training_ng; + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x01U); + } + + return phytrainingok; +} + +/******************************************************************************* + * Manual Write DCA Training + ******************************************************************************/ +static void r_manual_write_dca(void) +{ + uint32_t ch; + uint32_t slice; + uint32_t rank; + uint32_t cs; + uint32_t i; + uint32_t phy_slv_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; + uint32_t phy_slv_dly_avg[DRAM_CH_CNT][SLICE_CNT]; + uint32_t slv_dly_min[DRAM_CH_CNT][SLICE_CNT]; + uint32_t slv_dly_max[DRAM_CH_CNT][SLICE_CNT]; + uint32_t phy_dcc_code_min[DRAM_CH_CNT][SLICE_CNT]; + uint32_t phy_dcc_code_max[DRAM_CH_CNT][SLICE_CNT]; + uint32_t phy_dcc_code_mid; + uint32_t tmp; + uint32_t complete; + uint32_t retry; + const uint32_t RETRY_MAX = 0x10000U; + const uint8_t ratio_min = 0x06U; + const uint8_t ratio_max = 0x03U; + const uint8_t ratio_min_div = 0x0AU; + const uint8_t ratio_max_div = 0x02U; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x02U; + } + else + { + rank = 0x01U; + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + phy_dcc_code_min[ch][slice] = 0x7FU; + phy_dcc_code_max[ch][slice] = 0x00U; + } + } + + for (cs = 0U; cs < rank; cs++) + { + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_INDEX, cs); + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + phy_slv_dly[ch][cs][slice] = r_ddr_getval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY); + } + } + } /* for (cs = 0U; cs < rank; cs++ */ + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if (rank == 0x02U) + { + /* Calculate average between ranks */ + phy_slv_dly_avg[ch][slice] = (phy_slv_dly[ch][0][slice] + phy_slv_dly[ch][1][slice]) / 2U; + } + else + { + phy_slv_dly_avg[ch][slice] = phy_slv_dly[ch][0][slice]; + } + + /* Determine the search range */ + slv_dly_min[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07FU) * ratio_min / ratio_min_div; + slv_dly_max[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07FU) * ratio_max / ratio_max_div; + + if (slv_dly_max[ch][slice] > 0x7FU) + { + slv_dly_max[ch][slice] = 0x7FU; + } + } + } + + complete = 0x00U; + + r_ddr_setval_ach_as(PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x01U); + + for (i = 0U; i <= 0x7FU; i++) + { + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if (slv_dly_max[ch][slice] < (slv_dly_min[ch][slice] + i)) + { + complete |= ((0x01U << ch) << (8U * slice)); + } + else + { + /* CS0/1 same setting, Need masked write */ + r_ddr_setval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY, (slv_dly_min[ch][slice] + i)); + r_ddr_setval_s(ch, slice, SC_PHY_WCK_CALC, 0x01U); + r_ddr_setval(ch, SC_PHY_MANUAL_UPDATE, 0x01U); + } + } + } + + if (complete == (ddr_phyvalid | (ddr_phyvalid << 8))) + { + break; + } + + /* Exec write dca */ + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if ((((complete >> (8U * slice)) >> ch) & 0x01U) != 0x01U) + { + r_ddr_setval_s(ch, slice, PHY_DATA_DC_CAL_START, 0x01U); + } + } + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if ((((complete >> (8U * slice)) >> ch) & 0x01U) != 0x01U) + { + retry = 0U; + while (retry++ < RETRY_MAX) + { + tmp = r_ddr_getval_s(ch, slice, PHY_DATA_DC_CAL_START); + if (tmp == 0x00U) + { + break; + } + } + } + } + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + if ((slv_dly_min[ch][slice] + i) <= slv_dly_max[ch][slice]) + { + tmp = (r_ddr_getval_s(ch, slice, PHY_DATA_DC_DQS_CLK_ADJUST)); + if ((tmp >> 6) == 0x01U) + { + tmp = 0x00U; + } + else if ((tmp >> 6) == 0x02U) + { + tmp = 0x3FU; + } + else + { + ; /* Nothing */ + } + + if (tmp < phy_dcc_code_min[ch][slice]) + { + phy_dcc_code_min[ch][slice] = tmp; + } + + if (phy_dcc_code_max[ch][slice] < tmp) + { + phy_dcc_code_max[ch][slice] = tmp; + } + } + } + } + } /* for (i = 0U; i <= 0x7FU; i++) */ + + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U); + + for (cs = 0U; cs < rank; cs++) + { + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_INDEX, cs); + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + r_ddr_setval_s(ch, slice, PHY_CLK_WRDQS_SLAVE_DELAY, phy_slv_dly[ch][cs][slice]); + r_ddr_setval_s(ch, slice, SC_PHY_WCK_CALC, 0x01U); + r_ddr_setval(ch, SC_PHY_MANUAL_UPDATE, 0x01U); + } + } + } + + r_ddr_setval_ach_as(PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x00U); + + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01U); + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + phy_dcc_code_mid = (phy_dcc_code_min[ch][slice] + phy_dcc_code_max[ch][slice]) / 2U; + r_ddr_setval_s(ch, slice, PHY_DATA_DC_DQS_CLK_ADJUST, phy_dcc_code_mid); + } + } +} + +/******************************************************************************* + * Re-run Read Gate Training + ******************************************************************************/ +static uint32_t r_read_gate_training(void) +{ + uint32_t ch; + uint32_t rank; + uint32_t dataL; + uint32_t phytrainingok; + uint32_t retry; + uint32_t complete_ng; + uint32_t gt_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + r_ddr_setval_ach(PI_WRLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x01U); + r_ddr_setval_ach(PI_RDLVL_CS_SW, rank); + r_ddr_setval_ach(PI_RDLVL_GATE_REQ, 0x01U); + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = ((r_ddr_getval(ch, PI_INT_STATUS)) >> 22); + if ((dataL & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + gt_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Gtlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 2)); /* PI_RDLVL_GATE_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7)); /* SLICE0 delay setup error */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_GTLVL_STATUS_OBS) & (0x3U << 7)); /* SLICE1 delay setup error */ + if (dataL != 0x0U) + { + gt_training_ng |= 1U << ch; + MSG_LF("read_gate_training_error\n"); + } + } + + complete_ng = gt_training_ng; + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x01U); + } + + return phytrainingok; +} + +/*********************************************************************** + * Read Data Training with VREF Training + ***********************************************************************/ +static uint32_t r_read_vref_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + uint32_t rank; + uint32_t curr_rank; + uint32_t vref_start, vref_stop, vref_step; + uint32_t vref_stop_index; + uint32_t dvw_min_byte0[DRAM_CH_CNT], dvw_min_byte1[DRAM_CH_CNT]; + uint32_t obs_sel; + uint32_t win_byte0, win_byte1; + uint32_t best_vref_byte0, best_vref_byte1; + uint32_t best_vref_byte0_index, best_vref_byte1_index; + uint32_t best_dvw_min_byte0, best_dvw_min_byte1; + uint32_t best_thrshld; + uint32_t vref_outlier; + uint32_t best_lower_vref, best_upper_vref; + uint32_t outlier_cnt; + uint32_t tempLE, tempTE; + uint32_t dvw_min_byte0_table[DRAM_CH_CNT][128]; + uint32_t dvw_min_byte1_table[DRAM_CH_CNT][128]; + int32_t i; + + const uint32_t RETRY_MAX = 0x10000U; + + best_vref_byte0_index = 0U; + best_vref_byte1_index = 0U; + phytrainingok = 0U; + + for (ch = 0U; ch < DRAM_CH_CNT; ch++) + { + dvw_min_byte0[ch] = 0x0U; + dvw_min_byte1[ch] = 0x0U; + } + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x02U; + } + else + { + rank = 0x01U; + } + + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F0, 0x00U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F1, 0x00U); + r_ddr_setval_ach(PI_RDLVL_VREF_EN_F2, 0x00U); + r_ddr_setval_ach_as(PHY_VREF_TRAINING_CTRL, 0x00U); + + /* ch0 vref_point */ + vref_start = r_ddr_getval(0U, PHY_VREF_INITIAL_START_POINT); + vref_stop = r_ddr_getval(0U, PHY_VREF_INITIAL_STOP_POINT); + vref_step = r_ddr_getval(0U, PHY_VREF_INITIAL_STEPSIZE); + vref_stop_index = (vref_stop - vref_start) / vref_step; + + if (vref_stop_index > 0x80U) + { + return phytrainingok; + } + + for (i = 0; i <= vref_stop_index; i++) + { + r_foreach_vch((ch)) + { + dataL = (r_ddr_getval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | (vref_start + (vref_step * i)))); + dataL = (r_ddr_getval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | (vref_start + (vref_step * i)))); + } + + for (curr_rank = 0U; curr_rank < rank; curr_rank++) + { + /* All ch Read Training Start */ + r_ddr_setval_ach(PI_RDLVL_CS_SW, (0x1U << curr_rank)); + r_ddr_setval_ach(PI_RDLVL_REQ, 0x01U); + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if (((dataL >> 23) & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + /* Read Training End */ + r_ddr_setval_ach(PI_INT_ACK_0, (0x1U << 23)); + + r_foreach_vch((ch)) + { + /* minimum Data Valie Window for each VREF */ + dvw_min_byte0[ch] = 0xFFFFFFFFU; + dvw_min_byte1[ch] = 0xFFFFFFFFU; + for (obs_sel = 0x00U; obs_sel < 0x19U; obs_sel++) + { + if ((obs_sel < 0x11U) || (obs_sel == 0x18U)) + { + r_ddr_setval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_OBS_SELECT, obs_sel); + r_ddr_setval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_OBS_SELECT, obs_sel); + + tempLE = r_ddr_getval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + tempTE = r_ddr_getval_s(ch, 0U, PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + if (tempTE > tempLE) + { + win_byte0 = tempTE - tempLE; + } + else + { + win_byte0 = 0U; + } + tempLE = r_ddr_getval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + tempTE = r_ddr_getval_s(ch, 1U, PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + if (tempTE > tempLE) + { + win_byte1 = tempTE - tempLE; + } + else + { + win_byte1 = 0U; + } + + if (dvw_min_byte0[ch] > win_byte0) + { + dvw_min_byte0[ch] = win_byte0; + } + if (dvw_min_byte1[ch] > win_byte1) + { + dvw_min_byte1[ch] = win_byte1; + } + } + } + } + } /* For all memory rank */ + r_foreach_vch((ch)) + { + dvw_min_byte0_table[ch][i] = dvw_min_byte0[ch]; + dvw_min_byte1_table[ch][i] = dvw_min_byte1[ch]; + } + } /* For all vref_stop_index steps */ + + r_foreach_vch((ch)) + { + /* Search best VREF byte0 */ + best_vref_byte0 = vref_start; + best_vref_byte0_index = 0U; + best_dvw_min_byte0 = dvw_min_byte0_table[ch][0U]; + for (i = 0; i <= vref_stop_index; i++) + { + if (best_dvw_min_byte0 < dvw_min_byte0_table[ch][i]) + { + best_vref_byte0 = vref_start + (vref_step * i); + best_vref_byte0_index = i; + best_dvw_min_byte0 = dvw_min_byte0_table[ch][i]; + } + } + + /* Search best_lower VREF byte0 */ + dataL = r_ddr_getval_s(ch, 0U, PHY_RDLVL_DLY_STEP); + if (dataL == 0U) + { + best_thrshld = r_ddr_getval_s(ch, 0U, PHY_RDLVL_BEST_THRSHLD); + } + else + { + best_thrshld = r_ddr_getval_s(ch, 0U, PHY_RDLVL_BEST_THRSHLD) * dataL; + } + + vref_outlier = r_ddr_getval_s(ch, 0U, PHY_RDLVL_VREF_OUTLIER); + best_lower_vref = best_vref_byte0; + outlier_cnt = vref_outlier; + for (i = best_vref_byte0_index; i >= 0; i--) + { + if (dvw_min_byte0_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) + { + best_lower_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + if (i == 0) + { + break; + } + } + + /* Search best_upper VREF byte0 */ + vref_outlier = r_ddr_getval_s(ch, 0U, PHY_RDLVL_VREF_OUTLIER); + best_upper_vref = best_vref_byte0; + outlier_cnt = vref_outlier; + for (i = best_vref_byte0_index; i <= vref_stop_index; i++) + { + if (dvw_min_byte0_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) + { + best_upper_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + } + + /* Calculate center of best vref range byte0 */ + best_vref_byte0 = (best_lower_vref + best_upper_vref) / 2U; + + /* Search best VREF byte1 */ + best_vref_byte1 = vref_start; + best_vref_byte1_index = 0U; + best_dvw_min_byte1 = dvw_min_byte1_table[ch][0U]; + for (i = 0; i <= vref_stop_index; i++) + { + if (best_dvw_min_byte1 < dvw_min_byte1_table[ch][i]) + { + best_vref_byte1 = vref_start + (vref_step * i); + best_vref_byte1_index = i; + best_dvw_min_byte1 = dvw_min_byte1_table[ch][i]; + } + } + + /* Search best_lower VREF byte1 */ + dataL = r_ddr_getval_s(ch, 1U, PHY_RDLVL_DLY_STEP); + if (dataL == 0U) + { + best_thrshld = r_ddr_getval_s(ch, 1U, PHY_RDLVL_BEST_THRSHLD); + } + else + { + best_thrshld = r_ddr_getval_s(ch, 1U, PHY_RDLVL_BEST_THRSHLD) * dataL; + } + + vref_outlier = r_ddr_getval_s(ch, 1U, PHY_RDLVL_VREF_OUTLIER); + best_lower_vref = best_vref_byte1; + outlier_cnt = vref_outlier; + for (i = best_vref_byte1_index; i >= 0; i--) + { + if (dvw_min_byte1_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) + { + best_lower_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + if (i == 0) + { + break; + } + } + + /* Search best_upper VREF byte1 */ + vref_outlier = r_ddr_getval_s(ch, 1U, PHY_RDLVL_VREF_OUTLIER); + best_upper_vref = best_vref_byte1; + outlier_cnt = vref_outlier; + for (i = best_vref_byte1_index; i <= vref_stop_index; i++) + { + if (dvw_min_byte1_table[ch][i] <= 0U) + { + break; + } + if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) + { + best_upper_vref = vref_start + (vref_step * i); + } + else + { + if (outlier_cnt > 0U) + { + outlier_cnt--; + } + else + { + break; + } + } + } + + /* Calculate center of best vref range byte1 */ + best_vref_byte1 = (best_lower_vref + best_upper_vref) / 2U; + + dataL = (r_ddr_getval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 0U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | best_vref_byte0)); + dataL = (r_ddr_getval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ)) & (0xFU << 10); + r_ddr_setval_s(ch, 1U, PHY_PAD_VREF_CTRL_DQ, (dataL | (0x1U << 9) | best_vref_byte1)); + } + + return phytrainingok; +} + +/******************************************************************************* + * Read Data & RDDQ Training with best VREF & Write DQ VREF Training + ******************************************************************************/ +static uint32_t r_read_write_training(void) +{ + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + uint32_t dataL; + uint32_t complete_ng; + uint32_t rd_training_ng; + uint32_t wdq_training_ng; + + const uint32_t RETRY_MAX = 0x10000U; + + /* RDDQ_SLAVE_DELAY Set 0x0000 */ + r_ddr_setval_ach_as(PHY_RDDQ0_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ1_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ2_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ3_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ4_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ5_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ6_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDQ7_SLAVE_DELAY, 0x0000U); + r_ddr_setval_ach_as(PHY_RDDM_SLAVE_DELAY, 0x0000U); + + r_ddr_setval_ach(PI_WRLVL_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_GATE_EN_F2, 0x00U); + r_ddr_setval_ach(PI_RDLVL_EN_F2, 0x03U); + r_ddr_setval_ach(PI_WDQLVL_EN_F2, 0x03U); + + r_ddr_setval_ach(PI_TRAIN_ALL_FREQ_REQ, 0x01U); + + /* Freq Change High to High */ + dataL = r_pll3_freq(); + if (dataL != 0x0U) + { + return (1); + } + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if ((dataL & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + + complete_ng = 0x0U; + rd_training_ng = 0x0U; + wdq_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Rdlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 1)); /* PI_RDLVL_ERROR_BIT */ + if (dataL != 0x0U) + { + rd_training_ng |= 1U << ch; + MSG_LF("read_write_training_error:1\n"); + } + + /* Wdqlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 5)); /* PI_WDQLVL_ERROR_BIT */ + dataL |= (r_ddr_getval_s(ch, 0U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18)); /* SLICE0 wdqlvl_fail_dqZ */ + dataL |= (r_ddr_getval_s(ch, 1U, PHY_WDQLVL_STATUS_OBS) & (0x1FFU << 18)); /* SLICE1 wdqlvl_fail_dqZ */ + if (dataL != 0x0U) + { + wdq_training_ng |= 1U << ch; + MSG_LF("read_write_training_error:2\n"); + } + } + + complete_ng = (wdq_training_ng | rd_training_ng); + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + /* PI_INT_ACK assert */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x01U); + } + + return phytrainingok; +} + +/*********************************************************************** + * Correct RDDQ Training result & Re-Run Read Data Training + ***********************************************************************/ +static uint32_t r_read_training(void) +{ + uint32_t ch; + uint32_t slice; + uint32_t rank; + uint32_t i; + uint32_t phytrainingok; + uint32_t dataL; + uint32_t complete_ng; + uint32_t rd_training_ng; + uint32_t rddq_delay_offset; + uint32_t rddq_delay_max; + + const uint32_t rddq_delay_addr[9] = + { + PHY_RDDQ0_SLAVE_DELAY, PHY_RDDQ1_SLAVE_DELAY, PHY_RDDQ2_SLAVE_DELAY, + PHY_RDDQ3_SLAVE_DELAY, PHY_RDDQ4_SLAVE_DELAY, PHY_RDDQ5_SLAVE_DELAY, + PHY_RDDQ6_SLAVE_DELAY, PHY_RDDQ7_SLAVE_DELAY, PHY_RDDM_SLAVE_DELAY + }; + + const uint32_t rddq_delay_offset_ps = 0x19U; + const uint32_t rddq_delay_max_ps = 0x67U; + + rddq_delay_offset = rddq_delay_offset_ps * ddr_mbps * 256U / (ddr_mbpsdiv * 2U * 1000000U); + rddq_delay_max = rddq_delay_max_ps * ddr_mbps * 256U / (ddr_mbpsdiv * 2U * 1000000U); + + if (ch_have_this_cs[1] != 0x0U) + { + rank = 0x03U; + } + else + { + rank = 0x01U; + } + + r_foreach_vch((ch)) + { + for (slice = 0U; slice < SLICE_CNT; slice++) + { + for (i = 0U; i < 9U; i++) + { + dataL = r_ddr_getval_s(ch, slice, rddq_delay_addr[i]) + rddq_delay_offset; + if (dataL > rddq_delay_max) + { + dataL = rddq_delay_max; + } + r_ddr_setval_s(ch, slice, rddq_delay_addr[i], dataL); + } + } + } + + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_1, 0x00089080U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_2, 0x000811C0U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_3, 0x040811C0U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_4, 0x02000000U); + r_ddr_setval_ach(PI_RDLVL_TRAIN_SEQ_5, 0x00000000U); + r_ddr_setval_ach(PI_RDLVL_CS_SW, rank); + + /* Read training go */ + r_ddr_setval_ach(PI_RDLVL_REQ, 0x01U); + + /* PI_INT_ACK assert */ + phytrainingok = 0x0U; + phytrainingok = r_pi_int_ack_0_assert(23U); + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + + complete_ng = 0x0U; + rd_training_ng = 0x0U; + + /* Err Check */ + r_foreach_vch((ch)) + { + /* Rdlvl Err Check */ + dataL = 0x0U; + dataL = (r_ddr_getval(ch, PI_INT_STATUS) & (0x1U << 1)); /* PI_RDLVL_ERROR_BIT */ + if (dataL != 0x0U) + { + rd_training_ng |= 1U << ch; + MSG_LF("read_training_error\n"); + } + } + + complete_ng = rd_training_ng; + if (complete_ng != 0x0U) + { + return ~complete_ng; + } + + return phytrainingok; +} + +/******************************************************************************* + * DDR mode register setting + ******************************************************************************/ +static void r_ddr_register_set(void) +{ + /* MR28 ZQ Mode: Command-Based ZQ Calibration, ZQ interval: Background Cal Interval < 64ms */ + r_send_dbcmd(0x0E841C24U); +} + +/******************************************************************************* + * DDR mode register read + ******************************************************************************/ +static void r_ddr_register_read(void) +{ + uint32_t dataL; + + dataL = (uint32_t)(Boardcnf->bdcfg_rfm_chk); + if (dataL != 0x0U) + { + /* MR27 rank0 */ + r_send_dbcmd(0x0F801B00U); + /* MR57 rank0 */ + r_send_dbcmd(0x0F803900U); + + if (ch_have_this_cs[1] != 0x0U) + { + /* MR27 rank1 */ + r_send_dbcmd(0x0F811B00U); + /* MR57 rank1 */ + r_send_dbcmd(0x0F813900U); + } + } +} + +/******************************************************************************* + * Training handshake functions + ******************************************************************************/ +static uint32_t r_pi_int_ack_0_assert(uint32_t bit) +{ + uint32_t dataL; + uint32_t ch; + uint32_t phytrainingok; + uint32_t retry; + const uint32_t RETRY_MAX = 0x10000U; + + phytrainingok = 0U; + retry = 0U; + while (retry++ < RETRY_MAX) + { + r_foreach_vch((ch)) + { + dataL = r_ddr_getval(ch, PI_INT_STATUS); + if (((dataL >> bit) & 0x01U) != 0x0U) + { + phytrainingok |= (1U << ch); + } + } + if (phytrainingok == ddr_phyvalid) + { + break; + } + } + if (phytrainingok != ddr_phyvalid) + { + return phytrainingok; + } + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, (0x1U << bit)); + } + return phytrainingok; +} + +static void r_wait_dbpdstat1(uint32_t status) +{ + uint32_t i, ch, dataL; + uint32_t freqchg_req_chk; + + for (i = 0U; i < 2U; i++) + { + do + { + dataL = status; + freqchg_req_chk = 0U; + r_foreach_vch((ch)) + { + dataL &= mmio_read_32(DBSC_DBPDSTAT1(ch)); + freqchg_req_chk |= mmio_read_32(DBSC_DBPDSTAT0(ch)); + } + } while ((dataL != status) && ((freqchg_req_chk & 0x1U) == 0x0U)); + } +} + +static uint32_t r_wait_freqchgreq(uint32_t req_assert) +{ + uint32_t dataL; + uint32_t count; + uint32_t ch; + + count = 0xFFFFFFU; + + if (req_assert != 0x0U) + { + do + { + dataL = 1U; + r_foreach_vch((ch)) + { + dataL &= mmio_read_32(DBSC_DBPDSTAT0(ch)); + } + count = count - 1U; + } while (((dataL & 0x1U) != 0x1U) && (count != 0U)); + } + else + { + do + { + dataL = 0U; + r_foreach_vch((ch)) + { + dataL |= mmio_read_32(DBSC_DBPDSTAT0(ch)); + } + count = count - 1U; + } while (((dataL & 0x1U) != 0x0U) && (count != 0U)); + } /* (req_assert != 0x0U) */ + + return (count == 0U); +} + +static void r_set_freqchgack(uint32_t ack_assert) +{ + uint32_t ch; + uint32_t dataL; + + if (ack_assert != 0x0U) + { + dataL = 0x0000CF01U; + } + else + { + dataL = 0x00000000U; + } + + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDCNT2(ch), dataL); + } +} + +static uint32_t r_pll3_freq(void) +{ + uint32_t timeout; + uint32_t fsel; + + (void)r_wait_freqchgreq(1); + + fsel = (0x0300U & mmio_read_32(DBSC_DBPDSTAT0(0U))) >> 8; + if (fsel == 0U) + { + r_pll3_control(PLL3_LOW_FREQUENCY_MODE); /* Low frequency mode */ + } + else if (fsel == 1U) + { + r_pll3_control(PLL3_MEDIUM_FREQUENCY_MODE); /* Medium frequency mode */ + } + else + { + r_pll3_control(PLL3_HIGH_FREQUENCY_MODE); /* High frequency mode */ + } + + r_set_freqchgack(1U); + + timeout = r_wait_freqchgreq(0); + r_set_freqchgack(0U); + + if (timeout != 0x0U) + { + FATAL_MSG("Time out\n"); + return (1); + } + + r_wait_dbpdstat1(0x07U); + + return (0); +} + +/******************************************************************************* + * Initialize ddr + ******************************************************************************/ +static uint32_t r_init_ddr(void) +{ + uint32_t phytrainingok; + uint32_t ch; + uint32_t err; + + MSG_LF("init_ddr:0\n"); +#ifdef DDR_BACKUPMODE + R_DRAM_Get_Boot_Status(&ddrBackup); +#endif /* DDR_BACKUPMODE */ + + /*********************************************************************** + * PLL3 initialization setting + **********************************************************************/ + /* Reset Status Monitor clear */ + r_cpg_write_32(CPG_FSRCHKCLRR4, 0x00000200U); + /* Reset Status Monitor set */ + r_cpg_write_32(CPG_FSRCHKSETR4, 0x00000200U); + /* ddrphy soft reset assert */ + r_cpg_write_32(CPG_SRCR4, mmio_read_32(CPG_SRCR4) | 0x00000200U); + /* wait reset FB */ + while ((mmio_read_32(CPG_FSRCHKRA4) & 0x00000200U) != 0U) + { + ; /* Nothing */ + } + /* Reset Status Monitor clear */ + r_cpg_write_32(CPG_FSRCHKCLRR4, 0x00000200U); + +#if (RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE == 1U) + r_pll3_control(PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER); /* Initialize PLL3 setting */ +#else + r_pll3_control(PLL3_HIGH_FREQUENCY_MODE); /* Initialize PLL3 setting */ +#endif /* (RCAR_DDRPHY_REGISTER_FAST_LOAD_MODE == 1U) */ + + /* ddrphy soft reset negate */ + r_cpg_write_32(CPG_SRSTCLR4, 0x00000200U); + while ((mmio_read_32(CPG_SRCR4) & 0x00000200U) != 0U) + { + ; /* Nothing */ + } + + /*********************************************************************** + * unlock phy + **********************************************************************/ + /* Unlock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU); + } + + /*********************************************************************** + * dbsc register pre-setting + ***********************************************************************/ + r_dbsc_regset_pre(); + + /*********************************************************************** + * load ddrphy registers + ***********************************************************************/ + r_ddrtbl_load(); + + /*********************************************************************** + * configure ddrphy registers + ***********************************************************************/ + r_ddr_config(); + + /*********************************************************************** + * ddr backupmode end + ***********************************************************************/ +#ifdef DDR_BACKUPMODE + if (ddrBackup != 0x0U) + { + NOTICE("[WARM_BOOT]\n"); + } + else + { + NOTICE("[COLD_BOOT]\n"); + } + + err = R_DRAM_Update_Boot_Status(ddrBackup); + if (err != 0x0U) + { + NOTICE("[BOOT_STATUS_UPDATE_ERROR]\n"); + return INITDRAM_ERR_I; + } +#endif /* DDR_BACKUPMODE */ + MSG_LF("init_ddr:1\n"); + + /*********************************************************************** + * dbsc register set + ***********************************************************************/ + r_dbsc_regset(); + + MSG_LF("init_ddr:2\n"); + + /*********************************************************************** + * dfi_init_start (start ddrphy) & exec pi_training + ***********************************************************************/ + phytrainingok = r_pi_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:1\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:3\n"); + + /*********************************************************************** + * frequency selection change (F1->F2) + ***********************************************************************/ + r_ddr_setval_ach(PHY_FREQ_SEL_INDEX, 0x01U); + r_ddr_setval_ach(PHY_FREQ_SEL_MULTICAST_EN, 0x00U); +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + if (med_freq_en == 0x01U) + { + r_ddr_setval_ach(PI_WDQLVL_VREF_EN, 0x01U); + r_ddr_setval_ach(PI_FREQ_MAP, 0x04U); + r_ddr_setval_ach(PI_INIT_WORK_FREQ, 0x02U); + } +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ + + /*********************************************************************** + * write leveling cycle adjust + ***********************************************************************/ + r_write_leveling_adjust(); + + MSG_LF("init_ddr:4\n"); + + /*********************************************************************** + * exec write leveling & read gate training + ***********************************************************************/ + phytrainingok = r_wl_gt_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:2\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:5\n"); + + /*********************************************************************** + * exec write dca training + ***********************************************************************/ + r_write_dca(); + + MSG_LF("init_ddr:6\n"); + + /*********************************************************************** + * exec dram dca training + ***********************************************************************/ + phytrainingok = r_dramdca_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:3\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:7\n"); + + /*********************************************************************** + * exec write leveling + ***********************************************************************/ + phytrainingok = r_write_leveling(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:4\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:8\n"); + + /*********************************************************************** + * exec manual write dca training + ***********************************************************************/ + r_manual_write_dca(); + + MSG_LF("init_ddr:9\n"); + + /*********************************************************************** + * exec read gate training + ***********************************************************************/ + phytrainingok = r_read_gate_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:5\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:10\n"); + + /*********************************************************************** + * exec read vref training + ***********************************************************************/ + phytrainingok = r_read_vref_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:6\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:11\n"); + + /*********************************************************************** + * exec read dq & write dq training with best vref + ***********************************************************************/ + phytrainingok = r_read_write_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:7\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:12\n"); + + /*********************************************************************** + * correct rddq training result & exec read dq training + ***********************************************************************/ + phytrainingok = r_read_training(); + + if (ddr_phyvalid != phytrainingok) + { + MSG_LF("init_ddr_error:8\n"); + return (phytrainingok); + } + + MSG_LF("init_ddr:13\n"); + + /*********************************************************************** + * PER_CS_TRAINING_MULTICAST SET (disable) + ***********************************************************************/ + r_ddr_setval_ach_as(PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U); + + /*********************************************************************** + * Restore PI_SEQ_ARRAY for DFS + ***********************************************************************/ +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + if (med_freq_en == 0x01U) + { + r_ddr_setval_ach(PI_SEQ_ARRAY_29, 0x11910048U); + r_ddr_setval_ach(PI_SEQ_ARRAY_64, 0x1810214AU); + r_ddr_setval_ach(PI_SEQ_ARRAY_65, 0x1810314BU); + r_ddr_setval_ach(PI_SEQ_ARRAY_66, 0x18101149U); + r_ddr_setval_ach(PI_SEQ_ARRAY_67, 0x18061180U); + r_ddr_setval_ach(PI_SEQ_ARRAY_68, 0x18067FC0U); + r_ddr_setval_ach(PI_SEQ_ARRAY_69, 0x18101149U); + r_ddr_setval_ach(PI_SEQ_ARRAY_70, 0x18051200U); + r_ddr_setval_ach(PI_SEQ_ARRAY_71, 0x19A11C15U); + r_ddr_setval_ach(PI_SEQ_ARRAY_72, 0x19A11009U); + r_ddr_setval_ach(PI_FREQ_MAP, 0x07U); + } +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ + MSG_LF("init_ddr:14\n"); + + /*********************************************************************** + * setup DDR mode registers + ***********************************************************************/ + /* MRS */ + r_ddr_register_set(); + + /* MRR */ + r_ddr_register_read(); + + MSG_LF("init_ddr:15\n"); + + /*********************************************************************** + * training complete, setup dbsc + ***********************************************************************/ + r_dbsc_regset_post(); + + MSG_LF("init_ddr:16\n"); + + /*********************************************************************** + * lock phy + ***********************************************************************/ + /* Lock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U); + } + + return phytrainingok; +} + +/******************************************************************************* + * DDR Initialize entry + ******************************************************************************/ +uint32_t R_DRAM_Init(void) +{ + uint32_t ch, cs; + uint32_t dataL; + uint32_t failcount; + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00001234U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00001234U); + + /*********************************************************************** + * Judge product and cut + ***********************************************************************/ + Prr_Product = mmio_read_32(PRR) & PRR_PRODUCT_MASK; + Prr_Cut = mmio_read_32(PRR) & PRR_CUT_MASK; + + if (Prr_Product != PRR_PRODUCT_V4M) + { + FATAL_MSG("DDR:Unknown Product\n"); + return 0xFFU; + } + else if (Prr_Cut > 0xFFU) + { + FATAL_MSG("DDR:Unknown Product Version\n"); + return 0xFFU; + } + else + { + ; /* Nothing */ + } + + /*********************************************************************** + * Judge board type + ***********************************************************************/ + BOARDTYPE = r_boardcnf_get_brd_type(); + if (BOARDTYPE >= BOARDNUM) + { + FATAL_MSG("DDR:Unknown Board\n"); + return 0xFFU; + } + + Boardcnf = (const st_boardcnf_t *)&boardcnfs[BOARDTYPE]; + + ddr_phyvalid = (uint32_t)(Boardcnf->bdcfg_phyvalid); + + max_density = 0U; + + for (cs = 0U; cs < CS_CNT; cs++) + { + ch_have_this_cs[cs] = 0U; + } + + r_foreach_ech((ch)) + { + for (cs = 0U; cs < CS_CNT; cs++) + { + ddr_density[ch][cs] = 0xFFU; + } + } + + r_foreach_vch((ch)) + { + for (cs = 0U; cs < CS_CNT; cs++) + { + dataL = (uint32_t)(Boardcnf->ch[ch].bdcfg_ddr_density[cs]); + ddr_density[ch][cs] = dataL; + if (dataL == 0xFFU) + { + continue; + } + if (dataL > max_density) + { + max_density = dataL; + } + ch_have_this_cs[cs] |= (1U << ch); + } + } + + /*********************************************************************** + * Judge board clock frequency (in MHz) + ***********************************************************************/ + r_boardcnf_get_brd_clk(BOARDTYPE, &brd_clk, &brd_clkdiv); + if (((0x01U << 14) & mmio_read_32(RST_MODEMR0)) != 0x0U) + { + brd_clkdiva = 1U; + } + else + { + brd_clkdiva = 0U; + } + + /*********************************************************************** + * Judge ddr operating frequency clock(in Mbps) + ***********************************************************************/ + r_boardcnf_get_ddr_mbps(BOARDTYPE, &ddr_mbps, &ddr_mbpsdiv, &sscg, &med_freq_en); + + ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U)); + ddr_mul_low = CLK_DIV(6400U, 1U * 2U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U)); + + if (ddr_mbps >= (PLL3_MEDIUM_FREQUENCY_THRESHOLD * ddr_mbpsdiv * 4U)) + { + /* divider N = 8 */ + ddr_medium_div = 0x04U; + } + else if (ddr_mbps >= (PLL3_MEDIUM_FREQUENCY_THRESHOLD * ddr_mbpsdiv * 3U)) + { + /* divider N = 6 */ + ddr_medium_div = 0x03U; + } + else + { + /* divider N = 4 */ + ddr_medium_div = 0x02U; + } + + if ((sscg == 0x1U) || (sscg == 0x3U)) + { + ddr_mul_reg = ddr_mul_low - 2U; + } + else + { + ddr_mul_reg = ddr_mul_low; + } + +#if (RCAR_PLL3_FRAC_MODE == 1U) + ddr_mul_nf = ((8U * ddr_mbps * brd_clkdiv * (brd_clkdiva + 1U)) / (ddr_mbpsdiv * brd_clk * 2U)) - (8U * (ddr_mul / 2U) * 2U); +#else + ddr_mul_nf = 0x00U; +#endif /* (RCAR_PLL3_FRAC_MODE == 1U) */ + + dataL = 0x03U & (mmio_read_32(RST_MODEMR0) >> 13); + bus_clk = 0U; + bus_clkdiv = 0U; + + switch (dataL) + { + case 0U: + bus_clk = brd_clk * 0x18U; + bus_clkdiv = brd_clkdiv; + break; + case 1U: + bus_clk = brd_clk * 0x14U; + bus_clkdiv = brd_clkdiv; + break; + case 2U: + /* Not supported */ + bus_clk = brd_clk * 0x20U; + bus_clkdiv = brd_clkdiv * 2U; + break; + case 3U: + bus_clk = brd_clk * 0x18U; + bus_clkdiv = brd_clkdiv * 2U; + break; + default: + bus_clk = brd_clk * 0x18U; + bus_clkdiv = brd_clkdiv * 2U; + break; + } + + /*********************************************************************** + * Adjust tccd + ***********************************************************************/ + ddr_tccd = 2U; + +#if (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) + if (med_freq_en == 0x01U) + { + NOTICE("DDR%d/%d(%s)\n", ddr_mbps / ddr_mbpsdiv, ddr_mbps / ddr_mbpsdiv / ddr_medium_div, RCAR_DDR_VERSION); + } + else + { + NOTICE("DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); + } +#else + NOTICE("DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION); +#endif /* (RCAR_MEDIUM_FREQUENCY_TRAINING_MODE == 1U) */ + + MSG_LF("Start\n"); + + /*********************************************************************** + * initialize DDR + ***********************************************************************/ + dataL = r_init_ddr(); + if (dataL == ddr_phyvalid) + { + failcount = 0U; + } + else + { + failcount = 1U; + } + + NOTICE("..%d\n", failcount); + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00000000U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00000000U); + + if (failcount == 0U) + { + return INITDRAM_OK; + } + else + { + return INITDRAM_NG; + } +} + +#if (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) +void r_set_pi_rdlvl_interval(void) +{ + uint32_t ch; + uint32_t dataL; + uint32_t ctrl_clk; + uint32_t clk_count; + uint32_t phymster_req_interval; + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00001234U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00001234U); + + /* Unlock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU); + } + + /* PI_INT_STATUS clear */ + r_foreach_vch((ch)) + { + r_ddr_setval(ch, PI_INT_ACK_0, 0xFFFFFFFFU); + r_ddr_setval(ch, PI_INT_ACK_1, 0x01U); + } + + /* wait wdq training done */ + (void)r_pi_int_ack_0_assert(29U); + + /* set pi_rdlvl_interval */ + phymster_req_interval = PERIODIC_TRAINING_INTERVAL - 3000U; + clk_count = 1024U - (r_ddrtbl_getval_pi(DDR_PI_REGSET, PI_LONG_COUNT_MASK) * 32U); + ctrl_clk = ddr_mbps / ddr_mbpsdiv / 8U; + dataL = phymster_req_interval * ctrl_clk / clk_count; + r_ddr_setval_ach(PI_RDLVL_INTERVAL, dataL); + + /* Lock DDRPHY register */ + r_foreach_vch((ch)) + { + mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U); + } + + r_dbsc_write_32(DBSC_DBSYSCNT0, 0x00000000U); + r_dbsc_write_32(DBSC_DBSYSCNT0A, 0x00000000U); +} +#endif /* (RCAR_PERIODIC_TRAINING_SEPARATE_MODE != 0U) */ + +/******************************************************************************* + * END + ******************************************************************************/ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.c new file mode 100644 index 0000000..be344b9 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.c @@ -0,0 +1,240 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include "mem_io.h" +#include "log.h" +#else +#include "mem_io.h" +#include "log.h" +#endif +#include "boot_init_dram_regdef.h" +#include "boot_init_dram_config.h" + +/******************************************************************************* + * PLEASE SET board number or board judge function + ******************************************************************************/ +#define BOARD_JUDGE_AUTO +#ifdef BOARD_JUDGE_AUTO +static uint32_t r_board_judge(void); +uint32_t r_boardcnf_get_brd_type(void) +{ + return r_board_judge(); +} +#else /* BOARD_JUDGE_AUTO */ +uint32_t r_boardcnf_get_brd_type(void) +{ + return (0); +} +#endif /* BOARD_JUDGE_AUTO */ + +/******************************************************************************* + * EXTAL CLOCK DEFINITION + * PLEASE DEFINE HOW TO JUDGE BORAD CLK + ******************************************************************************/ +/* + * RENESAS GRAY HAWK BOARD EXAMPLE + * judge by md14/md13 + * + * 16.66MHz CLK,DIV= 50,3 (md14,md13==0,0) + * 20.00MHz CLK,DIV= 60,3 (md14,md13==0,1) + * 33.33MHz CLK,DIV=100,3 (md14,md13==1,1) +*/ +void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div) +{ + uint32_t md; + + md = (mmio_read_32(RST_MODEMR0) >> 13) & 0x3U; + switch (md) + { + case 0x0U : *clk = 50U; *clk_div = 3U; break; /* 50 / 3 = 16.66MHz */ + case 0x1U : *clk = 60U; *clk_div = 3U; break; /* 60 / 3 = 20.00MHz */ + case 0x2U : NOTICE("MD14/MD13 is invalid!!\n"); panic; /* Not supported */ + case 0x3U : *clk =100U; *clk_div = 3U; break; /* 100 / 3 = 33.33MHz */ + default : /* Nothing */ break; + } + (void)brd; +} + +/******************************************************************************* + * DDR MBPS TARGET + * PLEASE DEFINE HOW TO JUDGE DDR BPS + ******************************************************************************/ +/* + DDRxxxx (judge by md19,17) : Mbps + SSCG enable / disable for PLL1 (judge by md18/md37/md36) +*/ +void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg, uint32_t *med_freq_en) +{ + uint32_t md; + uint32_t product; + + md = (mmio_read_32(RST_MODEMR0) >> 17) & 0x05U; + md = (md | (md >> 1)) & 0x03U; + *sscg = ((mmio_read_32(RST_MODEMR0) >> 16) & 0x04U) | ((mmio_read_32(RST_MODEMR1) >> 4) & 0x03U); + product = mmio_read_32(OTP_MEM_OTPMONITOR17) & OTP_MEM_PRODUCT_MASK; + + if (product == 0x01U) + { + /* V4M-5 */ + switch (md) + { + case 0x0U : *mbps = 5000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5000Mbps */ + case 0x1U : *mbps = 5000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5000Mbps */ + case 0x2U : *mbps = 5000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5000Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + } + else if (product == 0x02U) + { + /* V4M-3 */ + switch (md) + { + case 0x0U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + case 0x1U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + case 0x2U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + } + else if (product == 0x04U) + { + /* V4M-2 */ + switch (md) + { + case 0x0U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + case 0x1U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + case 0x2U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + } + else + { + /* V4M-7 */ + switch (*sscg) + { + case 0x0U : + switch (md) + { + case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + case 0x1U : + switch (md) + { + case 0x0U : *mbps = 19000U; *mbps_div = 3U; *med_freq_en = 1U; break; /* 6333Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + case 0x2U : + switch (md) + { + case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + case 0x3U : + switch (md) + { + case 0x0U : *mbps = 19000U; *mbps_div = 3U; *med_freq_en = 1U; break; /* 6333Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + case 0x4U : + switch (md) + { + case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + case 0x5U : + switch (md) + { + case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + case 0x6U : + switch (md) + { + case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + case 0x7U : + switch (md) + { + case 0x0U : *mbps = 6400U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6400Mbps */ + case 0x1U : *mbps = 6000U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 6000Mbps */ + case 0x2U : *mbps = 5500U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 5500Mbps */ + case 0x3U : *mbps = 4800U; *mbps_div = 1U; *med_freq_en = 1U; break; /* 4800Mbps */ + default : /* Nothing */ break; + } + break; + default : + /* Nothing */ + break; + }/* Setting of SSCG */ + } /* (product == 0x01U) */ + + (void)brd; +} + +#ifdef BOARD_JUDGE_AUTO +/******************************************************************************* + * SAMPLE board detect function + ******************************************************************************/ +static uint32_t r_board_judge(void) +{ + uint32_t brd; + + brd = 0U; /* gray hawk (64Gbit 2rank) */ + + return brd; +} +#endif diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.h new file mode 100644 index 0000000..b8ada4d --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_config.h @@ -0,0 +1,156 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +#ifndef BOOT_INIT_DRAM_CONFIG_H_ +#define BOOT_INIT_DRAM_CONFIG_H_ + +/******************************************************************************* + * DRAM Param setting + ******************************************************************************/ +#define JS2_DERATE 0U +#define DBSC_REFINT 1920U /* Average periodic refresh interval/Average Refresh Interval [ns] */ +#ifndef DBSC_REFINTS +#define DBSC_REFINTS 0U /* 0: Average interval is REFINT. / 1: Average interval is 1/2 REFINT. */ +#endif +#define PERIODIC_TRAINING_INTERVAL 20000U /* Periodic-WriteDQ/ReadDQ Training Interval [us] */ + +/******************************************************************************* + * NUMBER OF BOARD CONFIGURATION + * PLEASE DEFINE + ******************************************************************************/ +#define BOARDNUM 2U /* Add User platform BOARD */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +uint32_t r_boardcnf_get_brd_type(void); +void r_boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *clk_div); +void r_boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *mbps_div, uint32_t *sscg, uint32_t *med_freq_en); + +/******************************************************************************* + * BOARD CONFIGURATION + * PLEASE DEFINE boardcnfs[] + ******************************************************************************/ +typedef struct +{ + /* + 0x00...0000B: 4Gb dual channel die / 2Gb single channel die + 0x01...0001B: 6Gb dual channel die / 3Gb single channel die + 0x02...0010B: 8Gb dual channel die / 4Gb single channel die + 0x03...0011B: 12Gb dual channel die / 6Gb single channel die + 0x04...0100B: 16Gb dual channel die / 8Gb single channel die + 0x05...0101B: 24Gb dual channel die / 12Gb single channel die + 0x06...0110B: 32Gb dual channel die / 16Gb single channel die + 0x07...0111B: 24Gb single channel die + 0x08...1000B: 32Gb single channel die + 0xFF...NO_MEMORY + */ + uint8_t bdcfg_ddr_density[CS_CNT]; + /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */ + uint32_t bdcfg_ca_swap; + /* SoC dqsX([1][0]) -> MEM dqsY: */ + uint8_t bdcfg_dqs_swap; + /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ + uint32_t bdcfg_dq_swap[SLICE_CNT]; + /* SoC dm -> MEM dqY/dm: (8 means DM) */ + uint8_t bdcfg_dm_swap[SLICE_CNT]; + /* SoC ckeX([1][0]) -> MEM csY */ + uint8_t bdcfg_cs_swap; +} st_boardcnf_ch_t; + +typedef struct +{ + /* ch in use */ + uint8_t bdcfg_phyvalid; + /* Read vref (SoC) training range : [23:16]step / [15:8]stop / [7:0]start, 0x00000000 = default val */ + uint32_t bdcfg_vref_r; + /* Write vref (MR14, MR15) training range : [15:8]stop / [7:0]start, 0x0000 = default val */ + uint16_t bdcfg_vref_w; + /* CA vref (MR12) training range : [15:8]stop / [7:0]start, 0x0000 = default val */ + uint16_t bdcfg_vref_ca; + /* RFM required check : 0x01 = check enable, 0x00 = check disable */ + uint8_t bdcfg_rfm_chk; + + st_boardcnf_ch_t ch[2]; +} st_boardcnf_t; + +static const st_boardcnf_t boardcnfs[BOARDNUM] = { +/* + * boardcnf[0] RENESAS V4M Gray Hawk (64Gbit 2rank) + */ +{ + 0x03U, /* bdcfg_phyvalid */ + 0x00000000U, /* bdcfg_vref_r */ + 0x0000U, /* bdcfg_vref_w */ + 0x0000U, /* bdcfg_vref_ca */ + 0x01U, /* bdcfg_rfm_chk */ + { +/* ch[0] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0x06U }, +/* bdcfg_ca_swap */ 0x06235104U, +/* bdcfg_dqs_swap */ 0x01U, +/* bdcfg_dq_swap[] */ { 0x43061257U, 0x30721685U }, +/* bdcfg_dm_swap[] */ { 0x08U, 0x04U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[1] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0x06U }, +/* bdcfg_ca_swap */ 0x04012653U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x58147026U, 0x70132685U }, +/* bdcfg_dm_swap[] */ { 0x03U, 0x04U }, +/* bdcfg_cs_swap */ 0x10U + } + } +}, +/* + * boardcnf[1] RENESAS V4M (2ch) + */ +{ + 0x03U, /* bdcfg_phyvalid */ + 0x00000000U, /* bdcfg_vref_r */ + 0x0000U, /* bdcfg_vref_w */ + 0x0000U, /* bdcfg_vref_ca */ + 0x01U, /* bdcfg_rfm_chk */ + { +/* ch[0] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0x06U }, +/* bdcfg_ca_swap */ 0x06543210U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U }, +/* bdcfg_dm_swap[] */ { 0x08U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + }, +/* ch[1] */ { +/* bdcfg_ddr_density[] */ { 0x06U, 0x06U }, +/* bdcfg_ca_swap */ 0x06543210U, +/* bdcfg_dqs_swap */ 0x10U, +/* bdcfg_dq_swap[] */ { 0x76543210U, 0x76543210U }, +/* bdcfg_dm_swap[] */ { 0x08U, 0x08U }, +/* bdcfg_cs_swap */ 0x10U + } + } +} +}; + +#endif /* BOOT_INIT_DRAM_CONFIG_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h new file mode 100644 index 0000000..67bfc20 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/boot_init_dram_regdef.h @@ -0,0 +1,165 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +#ifndef BOOT_INIT_DRAM_REGDEF_H_ +#define BOOT_INIT_DRAM_REGDEF_H_ + +#if defined(__RH850G3K__) +#include "remap_register.h" +#endif + +#define RCAR_DDR_VERSION "rev.1.00" +#define DRAM_CH_CNT 0x02U +#define SLICE_CNT 0x02U +#define CS_CNT 0x02U + +/* for pll setting */ +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) + +/* for ddr density setting */ +#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) (((d3) << 30U) | ((row) << 24U) | ((BG) << 20U) | ((bank) << 16U) | ((col) << 8U) | (dw)) +#define DBMEMCONF_REGD(density) (DBMEMCONF_REG((density % 2U), (((density + 1U) / 2U) + (28U - 2U - 2U - 10U - 1U)), 2U, 2U, 10U, 1U)) /* 16bit */ + +/* system registers : CPG */ +#define CPG_FRQCRD_KICK_BIT (1U << 31) +#define CPG_PLL3CR0_KICK_BIT (1U << 31) +#define CPG_PLLECR_PLL3ST_BIT (1U << 11) + +#if defined(__RH850G3K__) +#define CPG_BASE (BASE_CPG_ADDR) +#else +#define CPG_BASE (0xE6150000U) +#endif +#define CPG_CPGWPR (CPG_BASE + 0x0000U) +#define CPG_FRQCRD0 (CPG_BASE + 0x080CU) +#define CPG_PLLECR (CPG_BASE + 0x0820U) +#define CPG_PLL3CR0 (CPG_BASE + 0x083CU) +#define CPG_PLL3CR1 (CPG_BASE + 0x08C0U) +#define CPG_FSRCHKCLRR4 (CPG_BASE + 0x0590U) +#define CPG_FSRCHKSETR4 (CPG_BASE + 0x0510U) +#define CPG_FSRCHKRA4 (CPG_BASE + 0x0410U) +#define CPG_SRCR4 (CPG_BASE + 0x2C10U) +#define CPG_SRSTCLR4 (CPG_BASE + 0x2C90U) + +#if defined(__RH850G3K__) +#define RST_BASE (BASE_RESET_ADDR) +#else +#define RST_BASE (0xE6160000U) +#endif +#define RST_MODEMR0 (RST_BASE + 0x0000U) +#define RST_MODEMR1 (RST_BASE + 0x0004U) + +#if defined(__RH850G3K__) +#define OTP_MEM_1_BASE (BASE_OTP_MEM_ADDR) +#else +#define OTP_MEM_1_BASE (0xE61BF000U) +#endif +#define OTP_MEM_OTPMONITOR17 (OTP_MEM_1_BASE + 0x0144U) +#define OTP_MEM_PRODUCT_MASK (0x000000FFU) + +/* Product Register */ +#define PRR (0xFFF00044U) +#define PRR_PRODUCT_MASK (0x00007F00U) +#define PRR_CUT_MASK (0x000000FFU) + +#define PRR_PRODUCT_V4M (0x00005D00U) /* R-Car V4M */ + +#define PRR_PRODUCT_10 (0x00000000U) /* ver 1.0 */ +#define PRR_PRODUCT_20 (0x00000010U) /* ver 2.0 */ + +/* DBSC registers */ +#if defined(__RH850G3K__) +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4M DBSC0 clk_dbsc region */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4M DBSC0 clk_axim region */ +#else +#define DBSC_D_BASE (0xE67A4000U) /* forV4M DBSC0 clk_dbsc region */ +#define DBSC_A_BASE (0xE6790000U) /* forV4M DBSC0 clk_axim region */ +#endif + +#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0000U) +#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0000U) +#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x0004U) +#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x0004U) +#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x0008U) +#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x0008U) +#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x0020U) +#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x0020U) + +#define DBSC_DBMEMCONF(ch,cs) (DBSC_D_BASE + 0x0030U + (0x2000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs))) + +#define DBSC_DBMEMCONFA(ch,cs) (DBSC_A_BASE + 0x0030U + (0x4000U * (ch & 0x02U)) + (0x10U * (ch & 0x01U)) + (0x04U * (cs))) + +#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x0100U) + +#define DBSC_DBACEN (DBSC_A_BASE + 0x0200U) +#define DBSC_DBRFEN (DBSC_D_BASE + 0x0204U) +#define DBSC_DBCMD (DBSC_D_BASE + 0x0208U) +#define DBSC_DBWAIT (DBSC_D_BASE + 0x0210U) + +#define DBSC_DBTR(x) (DBSC_D_BASE + 0x0300U + (0x04U * (x))) + +#define DBSC_DBBL (DBSC_D_BASE + 0x0400U) +#define DBSC_DBBLA (DBSC_A_BASE + 0x0400U) + +#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x0414U) +#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x0418U) + +#define DBSC_DBCALCNF (DBSC_D_BASE + 0x0424U) + +#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x0430U + (0x04U * (x))) + +#define DBSC_DBDBICNT (DBSC_D_BASE + 0x0518U) +#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x0520U) +#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x0540U) + +#define DBSC_DBDFISTAT(ch) (DBSC_D_BASE + 0x0600U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBDFICNT(ch) (DBSC_D_BASE + 0x0604U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBPDCNT2(ch) (DBSC_D_BASE + 0x0618U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBPDLK(ch) (DBSC_D_BASE + 0x0620U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBPDRGA(ch) (DBSC_D_BASE + 0x0624U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBPDRGD(ch) (DBSC_D_BASE + 0x0628U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBPDRGM(ch) (DBSC_D_BASE + 0x062CU + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBPDSTAT0(ch) (DBSC_D_BASE + 0x0630U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBPDSTAT1(ch) (DBSC_D_BASE + 0x0634U + (0x2000U * (ch & 0x02U)) + (0x40U * (ch & 0x01U))) + +#define DBSC_DBBUS0CNF1 (DBSC_A_BASE + 0x0804U) + +#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x09FCU) + +#define DBSC_DBSCHRW1 (DBSC_A_BASE + 0x1024U) + +#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030U) + +#define DBSC_DBSCHFCTST0 (DBSC_A_BASE + 0x1040U) +#define DBSC_DBSCHFCTST1 (DBSC_A_BASE + 0x1044U) + +#endif /* BOOT_INIT_DRAM_REGDEF_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ddr_regdef.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ddr_regdef.h new file mode 100644 index 0000000..88b6c08 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ddr_regdef.h @@ -0,0 +1,390 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +#ifndef DDR_REGDEF_H_ +#define DDR_REGDEF_H_ + +#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL 0x10031000U +#define PHY_PER_CS_TRAINING_MULTICAST_EN 0x18011006U +#define PHY_PER_CS_TRAINING_INDEX 0x00011007U +#define PHY_VREF_INITIAL_STEPSIZE 0x1808100EU +#define PHY_RDLVL_BEST_THRSHLD 0x0004100FU +#define PHY_RDLVL_VREF_OUTLIER 0x1003100FU +#define SC_PHY_WCK_CALC 0x1801101BU +#define PHY_WRLVL_PER_START 0x00071020U +#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x08051022U +#define PHY_CALVL_VREF_DRIVING_SLICE 0x08011026U +#define PHY_WRLVL_HARD0_DELAY_OBS 0x000A102DU +#define PHY_WRLVL_HARD1_DELAY_OBS 0x100A102DU +#define PHY_WRLVL_STATUS_OBS 0x001C102EU +#define PHY_WRLVL_ERROR_OBS 0x00021030U +#define PHY_GTLVL_STATUS_OBS 0x00121032U +#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x10091033U +#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x00091034U +#define PHY_WDQLVL_STATUS_OBS 0x00201038U +#define PHY_DATA_DC_CAL_START 0x08011041U +#define PHY_SLV_DLY_CTRL_GATE_DISABLE 0x00011042U +#define PHY_REGULATOR_EN_CNT 0x00061044U +#define PHY_VREF_INITIAL_START_POINT 0x00091048U +#define PHY_VREF_INITIAL_STOP_POINT 0x10091048U +#define PHY_VREF_TRAINING_CTRL 0x00021049U +#define PHY_RDDQ0_SLAVE_DELAY 0x00091050U +#define PHY_RDDQ1_SLAVE_DELAY 0x10091050U +#define PHY_RDDQ2_SLAVE_DELAY 0x00091051U +#define PHY_RDDQ3_SLAVE_DELAY 0x10091051U +#define PHY_RDDQ4_SLAVE_DELAY 0x00091052U +#define PHY_RDDQ5_SLAVE_DELAY 0x10091052U +#define PHY_RDDQ6_SLAVE_DELAY 0x00091053U +#define PHY_RDDQ7_SLAVE_DELAY 0x10091053U +#define PHY_RDDM_SLAVE_DELAY 0x00091054U +#define PHY_RX_CAL_ALL_DLY 0x18061054U +#define PHY_RX_PCLK_CLK_SEL 0x00031055U +#define PHY_DATA_DC_CAL_CLK_SEL 0x08031055U +#define PHY_PAD_VREF_CTRL_DQ 0x100E1058U +#define PHY_PER_CS_TRAINING_EN 0x10011059U +#define PHY_RDDATA_EN_TSEL_DLY 0x0805105BU +#define PHY_RDDATA_EN_OE_DLY 0x1005105BU +#define PHY_RPTR_UPDATE 0x0804105EU +#define PHY_WRLVL_RESP_WAIT_CNT 0x0006105FU +#define PHY_RDLVL_DLY_STEP 0x08041062U +#define PHY_RDLVL_MAX_EDGE 0x00091063U +#define PHY_DATA_DC_WDQLVL_ENABLE 0x08021068U +#define PHY_RDDATA_EN_DLY 0x10051069U +#define PHY_DQ_DM_SWIZZLE0 0x0020106AU +#define PHY_DQ_DM_SWIZZLE1 0x0004106BU +#define PHY_CLK_WRDQS_SLAVE_DELAY 0x00091071U +#define PHY_WRITE_PATH_LAT_DEC 0x10011071U +#define PHY_RDDQS_LATENCY_ADJUST 0x1005107BU +#define PHY_WRITE_PATH_LAT_ADD 0x1803107BU +#define PHY_WRITE_PATH_LAT_FRAC 0x0008107CU +#define PHY_GTLVL_LAT_ADJ_START 0x0005107DU +#define PHY_DATA_DC_DQS_CLK_ADJUST 0x0008107FU +#define PHY_ADR_CALVL_SWIZZLE0 0x00201202U +#define PHY_ADR_MEAS_DLY_STEP_ENABLE 0x10011203U +#define PHY_ADR_CALVL_RANK_CTRL 0x18021205U +#define PHY_ADR_CALVL_OBS1 0x0020120AU +#define PHY_ADR_CALVL_OBS2 0x0020120BU +#define PHY_ADR_CALVL_DLY_STEP 0x00041210U +#define PHY_CS_ACS_ALLOCATION_BIT2_2 0x08021215U +#define PHY_CS_ACS_ALLOCATION_BIT3_2 0x10021215U +#define PHY_CSLVL_OBS1 0x00201221U +#define PHY_ADRCTL_MASTER_DELAY_HALF_MEASURE 0x1008122DU +#define PHY_CLK_DC_CAL_CLK_SEL 0x0803123AU +#define PHY_FREQ_SEL_MULTICAST_EN 0x08011301U +#define PHY_FREQ_SEL_INDEX 0x10021301U +#define SC_PHY_MANUAL_UPDATE 0x18011304U +#define PHY_SET_DFI_INPUT_RST_PAD 0x18011311U +#define PHY_TCKSRE_WAIT 0x1004131FU +#define PHY_CAL_MODE_0 0x000D132CU +#define PHY_CAL_INTERVAL_COUNT_0 0x0020132DU +#define PHY_DATA_BYTE_ORDER_SEL 0x0020133FU +#define PHY_PAD_ACS_RX_PCLK_CLK_SEL 0x1003134AU +#define PHY_PLL_CTRL 0x000E134DU +#define PHY_PLL_CTRL_8X 0x100E134DU +#define PHY_CAL_CLK_SELECT_0 0x00031361U + +#define PI_START 0x00010800U +#define PI_TRAIN_ALL_FREQ_REQ 0x18010804U +#define PI_FREQ_MAP 0x0020080DU +#define PI_INIT_WORK_FREQ 0x0005080EU +#define PI_CS_MAP 0x08020815U +#define PI_WRLVL_REQ 0x0801081FU +#define PI_WRLVL_CS_SW 0x1002081FU +#define PI_RDLVL_REQ 0x10010827U +#define PI_RDLVL_GATE_REQ 0x18010827U +#define PI_RDLVL_CS_SW 0x00020828U +#define PI_RDLVL_PERIODIC 0x08010831U +#define PI_RDLVL_INTERVAL 0x08100838U +#define PI_DRAMDCA_FLIP_MASK 0x0802083EU +#define PI_DRAMDCA_LVL_REQ 0x10010840U +#define PI_DCMLVL_CS_SW 0x18020840U +#define PI_WRDCM_LVL_EN_F1 0x00020842U +#define PI_DRAMDCA_LVL_EN_F1 0x08020842U +#define PI_WRDCM_LVL_EN_F2 0x18020842U +#define PI_DRAMDCA_LVL_EN_F2 0x00020843U +#define PI_TCKCKEL_F2 0x18040851U +#define PI_WDQLVL_VREF_EN 0x08040852U +#define PI_WDQLVL_PERIODIC 0x00010854U +#define PI_WDQLVL_INTERVAL 0x00100858U +#define PI_INT_STATUS 0x002008B7U +#define PI_INT_ACK_0 0x002008B9U +#define PI_INT_ACK_1 0x000108BAU +#define PI_LONG_COUNT_MASK 0x100508BCU +#define PI_ADDRESS_MUX_0 0x000308BDU +#define PI_ADDRESS_MUX_1 0x080308BDU +#define PI_ADDRESS_MUX_2 0x100308BDU +#define PI_ADDRESS_MUX_3 0x180308BDU +#define PI_ADDRESS_MUX_4 0x000308BEU +#define PI_ADDRESS_MUX_5 0x080308BEU +#define PI_ADDRESS_MUX_6 0x100308BEU +#define PI_DATA_BYTE_SWAP_EN 0x180108BEU +#define PI_DATA_BYTE_SWAP_SLICE0 0x000108BFU +#define PI_DATA_BYTE_SWAP_SLICE1 0x080108BFU +#define PI_PWRUP_SREFRESH_EXIT 0x100108C2U +#define PI_DLL_RST 0x000108C6U +#define PI_TDELAY_RDWR_2_BUS_IDLE_F1 0x000808E8U +#define PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x000808E9U +#define PI_WRLAT_F1 0x100708EDU +#define PI_TWCKENL_RD_ADJ_F1 0x000608EEU +#define PI_TWCKPRE_STATIC_F1 0x080608EEU +#define PI_TWCKPRE_TOGGLE_RD_F1 0x180608EEU +#define PI_WCK_ACTIVE_WR_F1 0x000708EFU +#define PI_WCK_ACTIVE_RD_F1 0x080708EFU +#define PI_CASLAT_F1 0x180708EFU +#define PI_WRLAT_F2 0x000708F0U +#define PI_TWCKENL_WR_ADJ_F2 0x080608F0U +#define PI_TWCKENL_RD_ADJ_F2 0x100608F0U +#define PI_TWCKPRE_STATIC_F2 0x180608F0U +#define PI_TWCKPRE_TOGGLE_RD_F2 0x080608F1U +#define PI_WCK_ACTIVE_WR_F2 0x100708F1U +#define PI_WCK_ACTIVE_RD_F2 0x180708F1U +#define PI_TWCKENL_FS_ADJ_F2 0x000608F2U +#define PI_CASLAT_F2 0x080708F2U +#define PI_TRFC_F1 0x000A08F4U +#define PI_TREF_F1 0x001408F5U +#define PI_TRFC_F2 0x000A08F6U +#define PI_TREF_F2 0x001408F7U +#define PI_WRLVL_EN_F1 0x000208FAU +#define PI_TDFI_WRLVL_WW_F1 0x080A08FAU +#define PI_WRLVL_EN_F2 0x000208FBU +#define PI_TDFI_WRLVL_WW_F2 0x080A08FBU +#define PI_WRLVL_WCKOFF_F2 0x180808FBU +#define PI_RDLVL_EN_F1 0x100208FFU +#define PI_RDLVL_GATE_EN_F1 0x180208FFU +#define PI_RDLVL_EN_F2 0x00020900U +#define PI_RDLVL_GATE_EN_F2 0x08020900U +#define PI_RDLVL_VREF_EN_F0 0x18040900U +#define PI_RDLVL_RDDQ_EN_F1 0x00040902U +#define PI_RDLVL_VREF_EN_F1 0x08040902U +#define PI_RDLVL_VREF_EN_F2 0x18040903U +#define PI_RDLAT_ADJ_F1 0x10090905U +#define PI_RDLAT_ADJ_F2 0x00090906U +#define PI_WRLAT_ADJ_F1 0x18070906U +#define PI_WRLAT_ADJ_F2 0x00070907U +#define PI_TDFI_CALVL_CC_F1 0x000A0909U +#define PI_TDFI_CALVL_CAPTURE_F1 0x100A0909U +#define PI_TDFI_CALVL_CC_F2 0x000A090AU +#define PI_TDFI_CALVL_CAPTURE_F2 0x100A090AU +#define PI_CALVL_EN_F1 0x0802090BU +#define PI_CALVL_EN_F2 0x1002090BU +#define PI_TCAENT_F1 0x000E090DU +#define PI_TCAENT_F2 0x000E090EU +#define PI_TVREF_LONG_F1 0x000A0912U +#define PI_TVRCG_ENABLE_F1 0x100A0912U +#define PI_TVRCG_DISABLE_F1 0x000A0913U +#define PI_TVREF_LONG_F2 0x100A0914U +#define PI_TVRCG_ENABLE_F2 0x000A0915U +#define PI_TVRCG_DISABLE_F2 0x100A0915U +#define PI_CALVL_VREF_INITIAL_START_POINT_F2 0x10070917U +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x18070917U +#define PI_TDFI_CALVL_STROBE_F2 0x0804091AU +#define PI_TXP_F2 0x1005091AU +#define PI_TMRWCKEL_F2 0x1808091AU +#define PI_TCKEHDQS_F1 0x10060921U +#define PI_TFC_F1 0x000A0922U +#define PI_TCKEHDQS_F2 0x10060922U +#define PI_TFC_F2 0x000A0923U +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x10070925U +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x18070925U +#define PI_TDFI_WDQLVL_WR_F1 0x080A0928U +#define PI_TDFI_WDQLVL_RW_F1 0x000A0929U +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x10070929U +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x18070929U +#define PI_WDQLVL_EN_F1 0x0802092AU +#define PI_WDQLVL_RDLAT_ADJ_F1 0x0009092BU +#define PI_WDQLVL_WRLAT_ADJ_F1 0x1009092BU +#define PI_WDQLVL_TWCKENL_RD_ADJ_F1 0x0006092CU +#define PI_TDFI_WDQLVL_WR_F2 0x080A092CU +#define PI_TDFI_WDQLVL_RW_F2 0x000A092DU +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x1007092DU +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x1807092DU +#define PI_WDQLVL_EN_F2 0x0802092EU +#define PI_WDQLVL_RDLAT_ADJ_F2 0x0009092FU +#define PI_WDQLVL_WRLAT_ADJ_F2 0x1009092FU +#define PI_WDQLVL_TWCKENL_RD_ADJ_F2 0x00060930U +#define PI_TRTP_F1 0x18080936U +#define PI_TRP_F1 0x00080937U +#define PI_TRCD_F1 0x08080937U +#define PI_TWTR_S_F1 0x18060937U +#define PI_TWTR_L_F1 0x00060938U +#define PI_TWTR_F1 0x10060938U +#define PI_TWR_F1 0x18080938U +#define PI_TRAS_MAX_F1 0x00100939U +#define PI_TRAS_MIN_F1 0x10090939U +#define PI_TSR_F1 0x1008093AU +#define PI_TRTP_F2 0x0808093BU +#define PI_TRP_F2 0x1008093BU +#define PI_TRCD_F2 0x1808093BU +#define PI_TWTR_S_F2 0x0806093CU +#define PI_TWTR_L_F2 0x1006093CU +#define PI_TWTR_F2 0x0006093DU +#define PI_TWR_F2 0x0808093DU +#define PI_TRAS_MAX_F2 0x1010093DU +#define PI_TRAS_MIN_F2 0x0009093EU +#define PI_TDQSCK_MAX_F2 0x1004093EU +#define PI_TSR_F2 0x0008093FU +#define PI_TMRD_F2 0x0808093FU +#define PI_TDFI_CTRLUPD_MAX_F1 0x00150942U +#define PI_TDFI_CTRLUPD_INTERVAL_F1 0x00200943U +#define PI_TDFI_CTRLUPD_MAX_F2 0x00150944U +#define PI_TDFI_CTRLUPD_INTERVAL_F2 0x00200945U +#define PI_TXSR_F1 0x10100946U +#define PI_TXSR_F2 0x00100947U +#define PI_TINIT_F1 0x0018094EU +#define PI_TINIT1_F1 0x0018094FU +#define PI_TINIT3_F1 0x00180950U +#define PI_TINIT4_F1 0x00180951U +#define PI_TINIT5_F1 0x00180952U +#define PI_TXSNR_F1 0x00100953U +#define PI_TINIT_F2 0x00180954U +#define PI_TINIT1_F2 0x00180955U +#define PI_TINIT3_F2 0x00180956U +#define PI_TINIT4_F2 0x00180957U +#define PI_TINIT5_F2 0x00180958U +#define PI_TXSNR_F2 0x00100959U +#define PI_TZQCAL_F1 0x100C095CU +#define PI_TZQLAT_F1 0x0007095DU +#define PI_TZQCAL_F2 0x100C095EU +#define PI_TZQLAT_F2 0x0007095FU +#define PI_ZQRESET_F1 0x000C0960U +#define PI_ZQRESET_F2 0x100C0960U +#define PI_TDQ72DQ_F1 0x000A0964U +#define PI_TCBTRTW_F1 0x10060964U +#define PI_TDQ72DQ_F2 0x100A0965U +#define PI_TCBTRTW_F2 0x00060966U +#define PI_MC_TRFC_F1 0x100A0968U +#define PI_MC_TRFC_F2 0x000A0969U +#define PI_TDFI_WCK_STOP_F1 0x0808096EU +#define PI_TDFI_WCK_STOP_F2 0x1808096EU +#define PI_CKE_MUX_0 0x1802096FU +#define PI_CKE_MUX_1 0x00020970U +#define PI_SEQ_DEC_SW_CS 0x0002097BU +#define PI_SW_SEQ_START 0x1001097BU +#define PI_SEQ_ARRAY_29 0x001D09C9U +#define PI_SEQ_ARRAY_64 0x001D09ECU +#define PI_SEQ_ARRAY_65 0x001D09EDU +#define PI_SEQ_ARRAY_66 0x001D09EEU +#define PI_SEQ_ARRAY_67 0x001D09EFU +#define PI_SEQ_ARRAY_68 0x001D09F0U +#define PI_SEQ_ARRAY_69 0x001D09F1U +#define PI_SEQ_ARRAY_70 0x001D09F2U +#define PI_SEQ_ARRAY_71 0x001D09F3U +#define PI_SEQ_ARRAY_72 0x001D09F4U +#define PI_SEQ_ARRAY_81 0x001D09FDU +#define PI_SEQ_ARRAY_82 0x001D09FEU +#define PI_SEQ_ARRAY_333 0x001B0AF9U +#define PI_SEQ_ARRAY_334 0x001B0AFAU +#define PI_SEQ_ARRAY_335 0x001B0AFBU +#define PI_SEQ_ARRAY_349 0x001B0B09U +#define PI_SEQ_ARRAY_350 0x001B0B0AU +#define PI_RDLVL_TRAIN_SEQ_1 0x001B0B9EU +#define PI_RDLVL_TRAIN_SEQ_2 0x001B0B9FU +#define PI_RDLVL_TRAIN_SEQ_3 0x001B0BA0U +#define PI_RDLVL_TRAIN_SEQ_4 0x001B0BA1U +#define PI_RDLVL_TRAIN_SEQ_5 0x001B0BA2U +#define PI_SEQ_WAIT_16_F1 0x00180BD2U +#define PI_SEQ_WAIT_16_F2 0x00180BD3U +#define PI_SEQ_WAIT_17_F1 0x00180BD5U +#define PI_SEQ_WAIT_17_F2 0x00180BD6U +#define PI_SEQ_WAIT_18_F2 0x00180BD9U +#define PI_SEQ_WAIT_19_F1 0x00180BDBU +#define PI_SEQ_WAIT_19_F2 0x00180BDCU +#define PI_SEQ_WAIT_20_F1 0x00180BDEU +#define PI_SEQ_WAIT_20_F2 0x00180BDFU +#define PI_SEQ_WAIT_21_F1 0x00180BE1U +#define PI_SEQ_WAIT_21_F2 0x00180BE2U +#define PI_SEQ_WAIT_22_F1 0x00180BE4U +#define PI_SEQ_WAIT_22_F2 0x00180BE5U +#define PI_SEQ_WAIT_23_F1 0x00180BE7U +#define PI_SEQ_WAIT_23_F2 0x00180BE8U +#define PI_SEQ_WAIT_24_F1 0x00180BEAU +#define PI_SEQ_WAIT_24_F2 0x00180BEBU +#define PI_SEQ_WAIT_25_F1 0x00180BEDU +#define PI_SEQ_WAIT_25_F2 0x00180BEEU +#define PI_SEQ_WAIT_26_F1 0x00180BF0U +#define PI_SEQ_WAIT_26_F2 0x00180BF1U +#define PI_SEQ_WAIT_27_F2 0x00180BF4U +#define PI_SEQ_WAIT_31_F1 0x00180BFFU +#define PI_SEQ_WAIT_31_F2 0x00180C00U +#define PI_WP_GAP_0_F1 0x100F0C0DU +#define PI_WP_GAP_0_F2 0x000F0C0EU +#define PI_RP_GAP_0_F1 0x000F0C0FU +#define PI_RP_GAP_0_F2 0x100F0C0FU +#define PI_WR_GAP_S_0_F1 0x100F0C10U +#define PI_WR_GAP_S_0_F2 0x000F0C11U +#define PI_WR_GAP_L_0_F1 0x000F0C12U +#define PI_WR_GAP_L_0_F2 0x100F0C12U +#define PI_RW_GAP_0_F1 0x100F0C13U +#define PI_RW_GAP_0_F2 0x000F0C14U +#define PI_WP_GAP_1_F1 0x000F0C1BU +#define PI_WP_GAP_1_F2 0x100F0C1BU +#define PI_RP_GAP_1_F1 0x100F0C1CU +#define PI_RP_GAP_1_F2 0x000F0C1DU +#define PI_WR_GAP_S_1_F1 0x000F0C1EU +#define PI_WR_GAP_S_1_F2 0x100F0C1EU +#define PI_WR_GAP_L_1_F1 0x100F0C1FU +#define PI_WR_GAP_L_1_F2 0x000F0C20U +#define PI_RW_GAP_1_F1 0x000F0C21U +#define PI_RW_GAP_1_F2 0x100F0C21U +#define PI_WP_GAP_2_F1 0x100F0C28U +#define PI_WP_GAP_2_F2 0x000F0C29U +#define PI_RP_GAP_2_F1 0x000F0C2AU +#define PI_RP_GAP_2_F2 0x100F0C2AU +#define PI_WR_GAP_S_2_F1 0x100F0C2BU +#define PI_WR_GAP_S_2_F2 0x000F0C2CU +#define PI_WR_GAP_L_2_F1 0x000F0C2DU +#define PI_WR_GAP_L_2_F2 0x100F0C2DU +#define PI_RW_GAP_2_F1 0x100F0C2EU +#define PI_RW_GAP_2_F2 0x000F0C2FU +#define PI_WP_GAP_3_F1 0x000F0C36U +#define PI_WP_GAP_3_F2 0x100F0C36U +#define PI_RP_GAP_3_F1 0x100F0C37U +#define PI_RP_GAP_3_F2 0x000F0C38U +#define PI_WR_GAP_S_3_F1 0x000F0C39U +#define PI_WR_GAP_S_3_F2 0x100F0C39U +#define PI_WR_GAP_L_3_F1 0x100F0C3AU +#define PI_WR_GAP_L_3_F2 0x000F0C3BU +#define PI_RW_GAP_3_F1 0x000F0C3CU +#define PI_RW_GAP_3_F2 0x100F0C3CU +#define PI_DARRAY3_0_CS0_F0 0x00080C9DU +#define PI_DARRAY3_1_CS0_F0 0x08080C9DU +#define PI_DARRAY3_0_CS0_F1 0x00080CA7U +#define PI_DARRAY3_1_CS0_F1 0x08080CA7U +#define PI_DARRAY3_0_CS0_F2 0x00080CB1U +#define PI_DARRAY3_1_CS0_F2 0x08080CB1U +#define PI_DARRAY3_2_CS0_F2 0x10080CB1U +#define PI_DARRAY3_20_CS0_F2 0x00080CB6U +#define PI_DARRAY3_0_CS1_F0 0x00080CBBU +#define PI_DARRAY3_1_CS1_F0 0x08080CBBU +#define PI_DARRAY3_0_CS1_F1 0x00080CC5U +#define PI_DARRAY3_1_CS1_F1 0x08080CC5U +#define PI_DARRAY3_0_CS1_F2 0x00080CCFU +#define PI_DARRAY3_1_CS1_F2 0x08080CCFU +#define PI_DARRAY3_2_CS1_F2 0x10080CCFU +#define PI_DARRAY3_20_CS1_F2 0x00080CD4U + +#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xFFFFU) +#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xFFU) +#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xFFU) + +#endif /* DDR_REGDEF_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c new file mode 100644 index 0000000..380bb5a --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.c @@ -0,0 +1,171 @@ +/******************************************************************************* + * Copyright (c) 2023-2025 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC initialize function + ******************************************************************************/ +/****************************************************************************** + * @file ecc_enable_v4m.c + * - Version : 0.05 + * @brief Enable setting process of ECC for DRAM. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + * : 21.08.2023 0.02 Update the ecc setting according to HW SAN rev0.82. + * : 08.04.2024 0.03 Update the ecc register setting. + * : 13.06.2024 0.04 Fix register setting for EDC_CFG, and revise + * : the ecm_lock()/ecm_unlock() process. + * : 27.01.2025 0.05 Add ECM setting process. + * Remove unused functions. + *****************************************************************************/ + +#include + +#if (ECC_ENABLE == 1) +#include "ecc_enable_v4m.h" +#include "ecm_enable_v4m.h" +#include "mem_io.h" +#include "v4m/lpddr5/boot_init_dram_regdef.h" + +/* Reference:"ECC for DRAM and System RAM" in R19AN0083EJ0082_R-CarV4H_SAN_for_Customer.pdf*/ +void ecc_sdram_enable(void) +{ + NOTICE("ECC for DRAM is enable.\n"); + + uint32_t ecm_tmp; + + /* Before writing to DBSC register, it shall be set to "0x00001234" for the following registers. + After writing to DBSC register, it shall be set to a value other than "0x00001234" for the following registers. */ + mem_write32(DB0SYSCNT0, 0x00001234U); + mem_write32(DB0SYSCNT0A, 0x00001234U); + + /* (A) Setting ECM */ + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + /* (1) Set the corresponding bits of the ECMERRTGTR and ECMERRCTLR registers + to inform the external device of the error via the ERROROUT# pin. */ + /* Set bit 1 of ECMERRTGTR0 to 0 and bit 1 of ECMERRCTLR0 to 1. */ + ecm_tmp = mem_read32(ECMERRTGTR0); + ecm_tmp &= ~(0x2U); + ecm_write(ECMERRTGTR0, ecm_tmp); + + ecm_tmp = mem_read32(ECMERRCTLR0); + ecm_tmp |= (0x2U); + ecm_write(ECMERRCTLR0, ecm_tmp); + + /* (B) Setting ECC protection area */ + /* Set the bottom row address of the ECC protection area */ + mem_write32(DB0FSDRAMECCAREA00, ECC_PROT_SIZE00); + mem_write32(DB0FSDRAMECCAREA01, ECC_PROT_SIZE01); + + /* (C) Initialization for DRAM */ + mem_write32(DBSC_DB0ACEN, 0x00000000U); + + /*** Initialization for DRAM connected to DBS0 Initialize RANK0 in according with the following procedure.***/ + /* [Step1] Specify RANK0 as the initialization target. Set 0x0 to DB0FSCONF00A[1:0]. */ + mem_write32(DB0FSCONF00A, 0x0U); + + /* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */ + mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA00); + + /* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */ + mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA00); + + /* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */ + mem_write32(DB0FSCTRL01A, 0x01U); + + /* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */ + NOTICE("DRAM rank 0 of DBSC0 is initializing.......\n"); + do + { + ecm_tmp = 0x01U; + ecm_tmp &= mem_read32(DB0FSSTAT01A); + } while ((ecm_tmp & 0x01U) != 0x01U); + + /*** If DRAM is connected to RANK1, Initialize RANK1 by the following procedure ***/ + /* [Step1] Specify RANK1 as the initialization target. Set 0x1 to DB0FSCONF00A[1:0]. */ + mem_write32(DB0FSCONF00A, 0x1U); + + /* [Step2] Set the start row address of the initialization area in DB0FSCONF01A[31:0]. */ + mem_write32(DB0FSCONF01A, START_ECC_INIT_AREA01); + + /* [Step3] Set the end row address of the initialization area in DB0FSCONF02A[31:0]. */ + mem_write32(DB0FSCONF02A, END_ECC_INIT_AREA01); + + /* [Step4] Set 0x1 to DB0FSCTRL01A[0] to start initialization. */ + mem_write32(DB0FSCTRL01A, 0x01U); + + /* [Step5] When DB0FSSTAT01A[0] is set to 0x1, DBS0/RANK1 initialization is complete. */ + NOTICE("DRAM rank 1 of DBSC0 is initializing.......\n"); + do + { + ecm_tmp = 0x01U; + ecm_tmp &= mem_read32(DB0FSSTAT01A); + } while ((ecm_tmp & 0x01U) != 0x01U); + + /* (D) Setting ECC protection enable */ + ecm_tmp = mem_read32(DB0FSCONFAXI0); + ecm_tmp |= (0x3U << 8U); + mem_write32(DB0FSCONFAXI0, ecm_tmp); + + /* (E) System RAM initialization */ + /* Read DB0FSSTAT00A and wait until its value changes to 0x1. */ + /* When DB0FSSTAT00A changes to 0x1, the System RAM area initialization is complete of dbs0 */ + NOTICE("System RAM is initializing.......\n"); + do + { + ecm_tmp = 0x01U; + ecm_tmp &= mem_read32(DB0FSSTAT00A); + } while (ecm_tmp != 0x1U); + + /* (F) Setting for ECC error interrupt */ + /* (1) Set the ECC error interrupt for read data */ + mem_write32(DB0FSINTENB02A, 0xFF00U); + + /* (2) Set the ECC error interrupt during RMW operation for System RAM. */ + ecm_tmp = mem_read32(DB0FSINTENB02A); + ecm_tmp |= 0xFF000000U; + mem_write32(DB0FSINTENB02A, ecm_tmp); + + /* (3) Set the ECC error interrupt during RMW operation for DRAM. */ + mem_write32(DB0FSINTENB04A, 0xFFFFFFFFU); + + /* Lock the ECM registers */ + ecm_lock(); + + /* Enable the write protect of ECM registers */ + mem_write32(DBSC_DB0ACEN, 0x00000001U); + + /* Enable the access protect for DBSC registers */ + mem_write32(DB0SYSCNT0, 0x00000000U); + mem_write32(DB0SYSCNT0A, 0x00000000U); +} +#endif /* ECC_ENABLE == 1 */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h new file mode 100644 index 0000000..9c007b7 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecc_enable_v4m.h @@ -0,0 +1,116 @@ +/******************************************************************************* + * Copyright (c) 2023-2025 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECC driver header + ******************************************************************************/ + +#ifndef ECC_PROTECT +#define ECC_PROTECT +/* DBSC registers */ +#if defined(__RH850G3K__) +#include "remap_register.h" +#include "mem_io.h" +#include "log.h" +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (BASE_DBSC_ADDR) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#define ECM_BASE (BASE_ECC_ADDR) +#else +#if (ECC_ENABLE == 1) +#include "mem_io.h" +#include "log.h" +#define DBSC_D_BASE (0xE67A4000U) /* forV4H DBSC0 clk_dbsc region DBSC1_D_BASE = 0xE67A8000U */ +#define DBSC_A_BASE (0xE6790000U) /* forV4H DBSC0 clk_axim region DBSC1_A_BASE = 0xE6798000U */ +#endif /* ECC_ENABLE == 1 */ +#define ECM_BASE (0xE6250000U) +#endif/* defined(__RH850G3K__) */ + +#if (ECC_ENABLE == 1) +void ecc_sdram_enable(void); + +#define DB0SYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DB0SYSCNT0A (DBSC_A_BASE + 0x0100U) +#define DB1SYSCNT0 (DB0SYSCNT0 + 0x4000U) +#define DB1SYSCNT0A (DB0SYSCNT0A + 0x8000U) + +#define DBSC_DB0ACEN (DBSC_A_BASE + 0x0200U) +#define DBSC_DB1ACEN (DBSC_DB0ACEN + 0x8000U) +#endif /* ECC_ENABLE == 1 */ + +#define ECMWACNTR (ECM_BASE + 0x0A04U) +#define ECMWPCNTR (ECM_BASE + 0x0A00U) +#if (ECC_ENABLE == 1) +#define ECMERRTGTR0 (ECM_BASE + 0x0200U) +#define ECMERRCTLR0 (ECM_BASE + 0x0000U) +#define DB0FSCONF00A (DBSC_A_BASE + 0x7640U) +#define DB1FSCONF00A (DB0FSCONF00A + 0x8000U) +#define DB0FSCONF01A (DBSC_A_BASE + 0x7644U) +#define DB1FSCONF01A (DB0FSCONF01A + 0x8000U) +#define DB0FSCONF02A (DBSC_A_BASE + 0x7648U) +#define DB1FSCONF02A (DB0FSCONF02A + 0x8000U) +#define DB0FSCTRL01A (DBSC_A_BASE + 0x7604U) +#define DB1FSCTRL01A (DB0FSCTRL01A + 0x8000U) +#define DB0FSSTAT01A (DBSC_A_BASE + 0x7684U) +#define DB1FSSTAT01A (DB0FSSTAT01A + 0x8000U) +#define DB0FSSTAT00A (DBSC_A_BASE + 0x7680U) +#define DB1FSSTAT00A (DB0FSSTAT00A + 0x8000U) +#define DB0FSINTENB02A (DBSC_A_BASE + 0x7088U) +#define DB1FSINTENB02A (DB0FSINTENB02A + 0x8000U) +#define DB0FSINTENB04A (DBSC_A_BASE + 0x7090U) +#define DB1FSINTENB04A (DB0FSINTENB04A + 0x8000U) + +#define DB0FSDRAMECCAREA00 (DBSC_A_BASE + 0x7450U) +#define DB0FSDRAMECCAREA01 (DBSC_A_BASE + 0x7454U) +#define DB1FSDRAMECCAREA00 (DB0FSDRAMECCAREA00 + 0x8000U) +#define DB1FSDRAMECCAREA01 (DB0FSDRAMECCAREA01 + 0x8000U) + +#define DB0FSCONFAXI0 (DBSC_A_BASE + 0x7400U) +#define DB1FSCONFAXI0 (DB0FSCONFAXI0 + 0x8000U) + +/********************* Set by the user *********************/ +/* The row address of ECC Protection Area Size for memory rank 0/1 of DBSC0/1 */ +#define ECC_PROT_SIZE00 (0xCCCCU) +#define ECC_PROT_SIZE01 (0xCCCCU) +#define ECC_PROT_SIZE10 (0xCCCCU) +#define ECC_PROT_SIZE11 (0xCCCCU) + +/* Start and End row address of ECC Protection area for rank0 of DBSC0/1 */ +#define START_ECC_INIT_AREA00 (0x00000000U) +#define START_ECC_INIT_AREA10 (0x00000000U) +#define END_ECC_INIT_AREA00 (0x0000CCCBU) +#define END_ECC_INIT_AREA10 (0x0000CCCBU) + +/* Start and End row address of ECC Protection area for rank1 of DBSC0/1 */ +#define START_ECC_INIT_AREA01 (0x00000000U) +#define START_ECC_INIT_AREA11 (0x00000000U) +#define END_ECC_INIT_AREA01 (0x0000CCCBU) +#define END_ECC_INIT_AREA11 (0x0000CCCBU) +/*********** Other settings cannot be changed ***************/ +#endif /* ECC_ENABLE == 1 */ + +#endif/* ECC_PROTECT */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c new file mode 100644 index 0000000..5d78cc9 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.c @@ -0,0 +1,265 @@ +/******************************************************************************* + * Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM initialize function + ******************************************************************************/ +/****************************************************************************** + * @file ecm_enable_v4m.c + * - Version : 0.01 + * @brief ECM setting. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 29.01.2025 0.01 First Release + *****************************************************************************/ + +#include +#include "ecm_enable_v4m.h" + +#if (ECM_ERROR_ENABLE == 1) +#include "log.h" +#endif /* ECM_ERROR_ENABLE == 1 */ +#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1)) +#include "ecc_enable_v4m.h" +#include "mem_io.h" +#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +#define ECM_ERR_REG_MAX (39U) + +typedef struct{ + uint32_t phys_addr; /* Physical address of ECM registers. */ + uint32_t value; /* Setting value of ECM registers. */ +} ECM_ERROR_TABLE; +#endif /* ECM_ERROR_ENABLE == 1 */ + +#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1)) +void ecm_unlock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0001U); +} + +void ecm_write(uint32_t adr, uint32_t val) +{ + mem_write32(ECMWACNTR, ((0xACCEU << 16U) | (adr & 0xffffU))); + mem_write32(adr, val); +} + +void ecm_lock(void) +{ + mem_write32(ECMWPCNTR, 0xACCE0000U); +} +#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_error_enable(void) +{ + uint32_t reg; + uint32_t loop; + + const ECM_ERROR_TABLE ecmerrctlr_tbl[ECM_ERR_REG_MAX] = { + [0] = {0xE6250000U, 0xFFFFF003U}, /* ECMERRCTLR0 */ + [1] = {0xE6250004U, 0xA7F8C000U}, /* ECMERRCTLR1 */ + [2] = {0xE6250008U, 0xFFFFFFFFU}, /* ECMERRCTLR2 */ + [3] = {0xE625000CU, 0xFFFFFFFFU}, /* ECMERRCTLR3 */ + [4] = {0xE6250010U, 0xFFFFFFFFU}, /* ECMERRCTLR4 */ + [5] = {0xE6250014U, 0x8FFFFFFFU}, /* ECMERRCTLR5 */ + [6] = {0xE6250018U, 0xFF000A80U}, /* ECMERRCTLR6 */ + [7] = {0xE625001CU, 0x68980FFFU}, /* ECMERRCTLR7 */ + [8] = {0xE6250020U, 0x60A00000U}, /* ECMERRCTLR8 */ + [9] = {0xE6250024U, 0xFF000000U}, /* ECMERRCTLR9 */ + [10] = {0xE6250028U, 0x557D554CU}, /* ECMERRCTLR10 */ + [11] = {0xE625002CU, 0xFF3C1555U}, /* ECMERRCTLR11 */ + [12] = {0xE6250030U, 0x0003FFFFU}, /* ECMERRCTLR12 */ + /* Skip ECMERRCTLR13 setting */ + /* Skip ECMERRCTLR14 setting */ + /* Skip ECMERRCTLR15 setting */ + [13] = {0xE6250040U, 0x33F03FFFU}, /* ECMERRCTLR16 */ + [14] = {0xE6250044U, 0x2DFF9CE0U}, /* ECMERRCTLR17 */ + [15] = {0xE6250048U, 0x0CC037FFU}, /* ECMERRCTLR18 */ + [16] = {0xE625004CU, 0xFFFFFF31U}, /* ECMERRCTLR19 */ + [17] = {0xE6250050U, 0xFE60067EU}, /* ECMERRCTLR20 */ + [18] = {0xE6250054U, 0xBF61820FU}, /* ECMERRCTLR21 */ + [19] = {0xE6250058U, 0x10000000U}, /* ECMERRCTLR22 */ + [20] = {0xE625005CU, 0x7E90C008U}, /* ECMERRCTLR23 */ + [21] = {0xE6250060U, 0x7E788AD9U}, /* ECMERRCTLR24 */ + [22] = {0xE6250064U, 0xC7807AB7U}, /* ECMERRCTLR25 */ + [23] = {0xE6250068U, 0x7E90C008U}, /* ECMERRCTLR26 */ + [24] = {0xE625006CU, 0x7E788AD9U}, /* ECMERRCTLR27 */ + [25] = {0xE6250070U, 0xC7807AB7U}, /* ECMERRCTLR28 */ + [26] = {0xE6250074U, 0x0010C008U}, /* ECMERRCTLR29 */ + [27] = {0xE6250078U, 0x7E608A99U}, /* ECMERRCTLR30 */ + [28] = {0xE625007CU, 0x84007A00U}, /* ECMERRCTLR31 */ + [29] = {0xE6250080U, 0xDFFFFFFFU}, /* ECMERRCTLR32 */ + [30] = {0xE6250084U, 0x1FFFFFFFU}, /* ECMERRCTLR33 */ + [31] = {0xE6250088U, 0x0000001FU}, /* ECMERRCTLR34 */ + [32] = {0xE625008CU, 0xA3BEEA80U}, /* ECMERRCTLR35 */ + [33] = {0xE6250090U, 0xFFFFFFFFU}, /* ECMERRCTLR36 */ + /* Skip ECMERRCTLR37 setting */ + [34] = {0xE6250098U, 0xFFF000FFU}, /* ECMERRCTLR38 */ + [35] = {0xE625009CU, 0x19FF0000U}, /* ECMERRCTLR39 */ + [36] = {0xE62500A0U, 0x0000601EU}, /* ECMERRCTLR40 */ + [37] = {0xE62500A4U, 0xEFFF7FFBU}, /* ECMERRCTLR41 */ + [38] = {0xE62500A8U, 0x0000000FU}, /* ECMERRCTLR42 */ + }; + +#if (ECMERRTGTR_INTC == 1) + const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = { + [0] = {0xE6250200U, 0xFFFFF003U}, /* ECMERRTGTR0 */ + [1] = {0xE6250204U, 0xA7F8C000U}, /* ECMERRTGTR1 */ + [2] = {0xE6250208U, 0xFFFFFFFFU}, /* ECMERRTGTR2 */ + [3] = {0xE625020CU, 0xFFFFFFFFU}, /* ECMERRTGTR3 */ + [4] = {0xE6250210U, 0xFFFFFFFFU}, /* ECMERRTGTR4 */ + [5] = {0xE6250214U, 0x8FFFFFFFU}, /* ECMERRTGTR5 */ + [6] = {0xE6250218U, 0xFF000A80U}, /* ECMERRTGTR6 */ + [7] = {0xE625021CU, 0x68980FFFU}, /* ECMERRTGTR7 */ + [8] = {0xE6250220U, 0x60A00000U}, /* ECMERRTGTR8 */ + [9] = {0xE6250224U, 0xFF000000U}, /* ECMERRTGTR9 */ + [10] = {0xE6250228U, 0x557D554CU}, /* ECMERRTGTR10 */ + [11] = {0xE625022CU, 0xFF3C1555U}, /* ECMERRTGTR11 */ + [12] = {0xE6250230U, 0x0003FFFFU}, /* ECMERRTGTR12 */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [13] = {0xE6250240U, 0x33F03FFFU}, /* ECMERRTGTR16 */ + [14] = {0xE6250244U, 0x2DFF9CE0U}, /* ECMERRTGTR17 */ + [15] = {0xE6250248U, 0x0CC037FFU}, /* ECMERRTGTR18 */ + [16] = {0xE625024CU, 0xFFFFFF31U}, /* ECMERRTGTR19 */ + [17] = {0xE6250250U, 0xFE60067EU}, /* ECMERRTGTR20 */ + [18] = {0xE6250254U, 0xBF61820FU}, /* ECMERRTGTR21 */ + [19] = {0xE6250258U, 0x10000000U}, /* ECMERRTGTR22 */ + [20] = {0xE625025CU, 0x7E90C008U}, /* ECMERRTGTR23 */ + [21] = {0xE6250260U, 0x7E788AD9U}, /* ECMERRTGTR24 */ + [22] = {0xE6250264U, 0xC7807AB7U}, /* ECMERRTGTR25 */ + [23] = {0xE6250268U, 0x7E90C008U}, /* ECMERRTGTR26 */ + [24] = {0xE625026CU, 0x7E788AD9U}, /* ECMERRTGTR27 */ + [25] = {0xE6250270U, 0xC7807AB7U}, /* ECMERRTGTR28 */ + [26] = {0xE6250274U, 0x0010C008U}, /* ECMERRTGTR29 */ + [27] = {0xE6250278U, 0x7E608A99U}, /* ECMERRTGTR30 */ + [28] = {0xE625027CU, 0x84007A00U}, /* ECMERRTGTR31 */ + [29] = {0xE6250280U, 0xDFFFFFFFU}, /* ECMERRTGTR32 */ + [30] = {0xE6250284U, 0x1FFFFFFFU}, /* ECMERRTGTR33 */ + [31] = {0xE6250288U, 0x0000001FU}, /* ECMERRTGTR34 */ + [32] = {0xE625028CU, 0xA3BEEA80U}, /* ECMERRTGTR35 */ + [33] = {0xE6250290U, 0xFFFFFFFFU}, /* ECMERRTGTR36 */ + /* Skip ECMERRTGTR37 setting */ + [34] = {0xE6250298U, 0xFFF000FFU}, /* ECMERRTGTR38 */ + [35] = {0xE625029CU, 0x19FF0000U}, /* ECMERRTGTR39 */ + [36] = {0xE62502A0U, 0x0000601EU}, /* ECMERRTGTR40 */ + [37] = {0xE62502A4U, 0xEFFF7FFBU}, /* ECMERRTGTR41 */ + [38] = {0xE62502A8U, 0x0000000FU}, /* ECMERRTGTR42 */ + }; +#elif (ECMERRTGTR_INTC == 0) + const ECM_ERROR_TABLE ecmerrtgtr_tbl[ECM_ERR_REG_MAX] = { + [0] = {0xE6250200U, 0x00000000U}, /* ECMERRTGTR0 */ + [1] = {0xE6250204U, 0x00000000U}, /* ECMERRTGTR1 */ + [2] = {0xE6250208U, 0x00000000U}, /* ECMERRTGTR2 */ + [3] = {0xE625020CU, 0x00000000U}, /* ECMERRTGTR3 */ + [4] = {0xE6250210U, 0x00000000U}, /* ECMERRTGTR4 */ + [5] = {0xE6250214U, 0x00000000U}, /* ECMERRTGTR5 */ + [6] = {0xE6250218U, 0x00000000U}, /* ECMERRTGTR6 */ + [7] = {0xE625021CU, 0x00000000U}, /* ECMERRTGTR7 */ + [8] = {0xE6250220U, 0x00000000U}, /* ECMERRTGTR8 */ + [9] = {0xE6250224U, 0x00000000U}, /* ECMERRTGTR9 */ + [10] = {0xE6250228U, 0x00000000U}, /* ECMERRTGTR10 */ + [11] = {0xE625022CU, 0x00000000U}, /* ECMERRTGTR11 */ + [12] = {0xE6250230U, 0x00000000U}, /* ECMERRTGTR12 */ + /* Skip ECMERRTGTR13 setting */ + /* Skip ECMERRTGTR14 setting */ + /* Skip ECMERRTGTR15 setting */ + [13] = {0xE6250240U, 0x00000000U}, /* ECMERRTGTR16 */ + [14] = {0xE6250244U, 0x00000000U}, /* ECMERRTGTR17 */ + [15] = {0xE6250248U, 0x00000000U}, /* ECMERRTGTR18 */ + [16] = {0xE625024CU, 0x00000000U}, /* ECMERRTGTR19 */ + [17] = {0xE6250250U, 0x00000000U}, /* ECMERRTGTR20 */ + [18] = {0xE6250254U, 0x00000000U}, /* ECMERRTGTR21 */ + [19] = {0xE6250258U, 0x00000000U}, /* ECMERRTGTR22 */ + [20] = {0xE625025CU, 0x00000000U}, /* ECMERRTGTR23 */ + [21] = {0xE6250260U, 0x00000000U}, /* ECMERRTGTR24 */ + [22] = {0xE6250264U, 0x00000000U}, /* ECMERRTGTR25 */ + [23] = {0xE6250268U, 0x00000000U}, /* ECMERRTGTR26 */ + [24] = {0xE625026CU, 0x00000000U}, /* ECMERRTGTR27 */ + [25] = {0xE6250270U, 0x00000000U}, /* ECMERRTGTR28 */ + [26] = {0xE6250274U, 0x00000000U}, /* ECMERRTGTR29 */ + [27] = {0xE6250278U, 0x00000000U}, /* ECMERRTGTR30 */ + [28] = {0xE625027CU, 0x00000000U}, /* ECMERRTGTR31 */ + [29] = {0xE6250280U, 0x00000000U}, /* ECMERRTGTR32 */ + [30] = {0xE6250284U, 0x00000000U}, /* ECMERRTGTR33 */ + [31] = {0xE6250288U, 0x00000000U}, /* ECMERRTGTR34 */ + [32] = {0xE625028CU, 0x00000000U}, /* ECMERRTGTR35 */ + [33] = {0xE6250290U, 0x00000000U}, /* ECMERRTGTR36 */ + /* Skip ECMERRTGTR37 setting */ + [34] = {0xE6250298U, 0x00000000U}, /* ECMERRTGTR38 */ + [35] = {0xE625029CU, 0x00000000U}, /* ECMERRTGTR39 */ + [36] = {0xE62502A0U, 0x00000000U}, /* ECMERRTGTR40 */ + [37] = {0xE62502A4U, 0x00000000U}, /* ECMERRTGTR41 */ + [38] = {0xE62502A8U, 0x00000000U}, /* ECMERRTGTR42 */ + }; +#endif /* ECMERRTGTR_INTC == 1 */ + + /* Unlock the write protect of ECM registers */ + ecm_unlock(); + + NOTICE("ECMERRCTLR register setting.\n"); + for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++) + { + /* Set ECMERRCTLR registers. */ + reg = mem_read32(ecmerrctlr_tbl[loop].phys_addr); + reg |= ecmerrctlr_tbl[loop].value; + ecm_write(ecmerrctlr_tbl[loop].phys_addr, reg); + + INFO("ECMERRCTLR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrctlr_tbl[loop].phys_addr, + mem_read32(ecmerrctlr_tbl[loop].phys_addr), + ecmerrctlr_tbl[loop].value); + } + + NOTICE("ECMERRTGTR register setting.\n"); + for (loop = 0U; loop < ECM_ERR_REG_MAX; loop++) + { + /* Set ECMERRTGTR registers. */ + reg = mem_read32(ecmerrtgtr_tbl[loop].phys_addr); + reg |= ecmerrtgtr_tbl[loop].value; + ecm_write(ecmerrtgtr_tbl[loop].phys_addr, reg); + + INFO("ECMERRTGTR[\t%d]\t(0x%x) =\t0x%x \tsetting value = 0x%x\n", + loop, + ecmerrtgtr_tbl[loop].phys_addr, + mem_read32(ecmerrtgtr_tbl[loop].phys_addr), + ecmerrtgtr_tbl[loop].value); + } + + /* Lock the ECM registers */ + ecm_lock(); +} +/* End of function ecm_error_enable(void) */ +#endif /* ECM_ERROR_ENABLE == 1 */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h new file mode 100644 index 0000000..88c3ea2 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/ecm_enable_v4m.h @@ -0,0 +1,47 @@ +/******************************************************************************* + * Copyright (c) 2025 Renesas Electronics Corporation. All rights reserved. + * + * RENESAS ELECTRONICS CONFIDENTIAL AND PROPRIETARY + * + * This software is provided as reference/sample code under the license + * agreement between Renesas Electronics Corporation and licensee (the + * "License Agreement") and shall be treated as specified in the License + * Agreement. + * These instructions, statements, and software are the confidential + * information of Renesas Electronics Corporation. They must be used and + * modified solely for the purpose for which it was furnished by Renesas + * Electronics Corporation. All or part of these instructions, statements and + * software must not be reproduced nor disclosed to any third party in any + * form, unless permitted by the License Agreement. + * + * THIS SOFTWARE IS PROVIDED BY RENESAS ELEOCTRONICS CORPORATION "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, + * SATISFACTORY QUALITY, ACCURACY, TITLE AND NON-INFRINGEMENT ARE DISCLAIMED. + * IN NO EVENT SHALL RENESAS ELECTRONICS CORPORATION BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, PUNITIVE, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + ******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : ECM driver header + ******************************************************************************/ + +#ifndef ECM_ENABLE +#define ECM_ENABLE + +#if ((ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1)) +void ecm_unlock(void); +void ecm_write(uint32_t adr, uint32_t val); +void ecm_lock(void); +#endif /* (ECM_ERROR_ENABLE == 1) || (ECC_ENABLE == 1) */ + +#if (ECM_ERROR_ENABLE == 1) +void ecm_error_enable(void); +#endif /* ECM_ERROR_ENABLE == 1 */ + +#endif/* ECM_ENABLE */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/init_dram_tbl_v4m_lp5.h b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/init_dram_tbl_v4m_lp5.h new file mode 100644 index 0000000..2dad73a --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ddr/v4m/lpddr5/init_dram_tbl_v4m_lp5.h @@ -0,0 +1,1654 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +#ifndef INIT_DRAM_TBL_V4M_LP5_H_ +#define INIT_DRAM_TBL_V4M_LP5_H_ + +#define DDR_PHY_SLICE_REGSET_OFS_V4M 0x1000 +#define DDR_PHY_ADR_V_REGSET_OFS_V4M 0x1200 +#define DDR_PHY_ADR_G_REGSET_OFS_V4M 0x1300 +#define DDR_PI_REGSET_OFS_V4M 0x0800 + +#define DDR_PHY_SLICE_REGSET_SIZE_V4M 0x100 +#define DDR_PHY_ADR_V_REGSET_SIZE_V4M 0x100 +#define DDR_PHY_ADR_G_REGSET_SIZE_V4M 0x100 +#define DDR_PI_REGSET_SIZE_V4M 0x600 + +#define DDR_PHY_SLICE_REGSET_NUM_V4M 140 +#define DDR_PHY_ADR_V_REGSET_NUM_V4M 61 +#define DDR_PHY_ADR_G_REGSET_NUM_V4M 98 +#define DDR_PI_REGSET_NUM_V4M 1301 + +static const uint32_t DDR_PHY_SLICE_REGSET_V4M[DDR_PHY_SLICE_REGSET_NUM_V4M] = { +/*1000*/ 0x30020370, +/*1001*/ 0x00000000, +/*1002*/ 0x01000002, +/*1003*/ 0x00010000, +/*1004*/ 0x00000000, +/*1005*/ 0x00000000, +/*1006*/ 0x01030000, +/*1007*/ 0x00010000, +/*1008*/ 0x01000004, +/*1009*/ 0x00000000, +/*100A*/ 0x00000001, +/*100B*/ 0x00000000, +/*100C*/ 0x00000000, +/*100D*/ 0x00010000, +/*100E*/ 0x08010000, +/*100F*/ 0x00022003, +/*1010*/ 0x00000000, +/*1011*/ 0x040F0100, +/*1012*/ 0x1404034F, +/*1013*/ 0x04020102, +/*1014*/ 0x10040404, +/*1015*/ 0x00000100, +/*1016*/ 0x00000000, +/*1017*/ 0x00FF0000, +/*1018*/ 0x18FF0008, +/*1019*/ 0x0000000F, +/*101A*/ 0x00000000, +/*101B*/ 0x00000001, +/*101C*/ 0x00070000, +/*101D*/ 0x00000000, +/*101E*/ 0x00000000, +/*101F*/ 0x00000000, +/*1020*/ 0x0008087F, +/*1021*/ 0x08040000, +/*1022*/ 0x00000004, +/*1023*/ 0x00401030, +/*1024*/ 0x0200000C, +/*1025*/ 0x00000020, +/*1026*/ 0x00000101, +/*1027*/ 0x00000000, +/*1028*/ 0x00000000, +/*1029*/ 0x00000000, +/*102A*/ 0x00000000, +/*102B*/ 0x00000000, +/*102C*/ 0x00000000, +/*102D*/ 0x00000000, +/*102E*/ 0x00000000, +/*102F*/ 0x00000000, +/*1030*/ 0x00000000, +/*1031*/ 0x00000000, +/*1032*/ 0x00000000, +/*1033*/ 0x00000020, +/*1034*/ 0x00000000, +/*1035*/ 0x00000000, +/*1036*/ 0x00000000, +/*1037*/ 0x00000000, +/*1038*/ 0x00000000, +/*1039*/ 0x00000000, +/*103A*/ 0x00000000, +/*103B*/ 0x00000000, +/*103C*/ 0x00000000, +/*103D*/ 0x00000004, +/*103E*/ 0x001F07FF, +/*103F*/ 0x00800800, +/*1040*/ 0x00061020, +/*1041*/ 0x04010000, +/*1042*/ 0x00000000, +/*1043*/ 0xCEC20101, +/*1044*/ 0x0000000A, +/*1045*/ 0x00017706, +/*1046*/ 0x01007706, +/*1047*/ 0x00000000, +/*1048*/ 0x008D006D, +/*1049*/ 0x00100001, +/*104A*/ 0x03FF0100, +/*104B*/ 0x00006E01, +/*104C*/ 0x00000301, +/*104D*/ 0x00000000, +/*104E*/ 0x00000000, +/*104F*/ 0x00000000, +/*1050*/ 0x00540054, +/*1051*/ 0x00540054, +/*1052*/ 0x00540054, +/*1053*/ 0x00540054, +/*1054*/ 0x0D000054, +/*1055*/ 0x90510604, +/*1056*/ 0x70006161, +/*1057*/ 0x41800531, +/*1058*/ 0x32800064, +/*1059*/ 0x80010080, +/*105A*/ 0x01010080, +/*105B*/ 0x00161301, +/*105C*/ 0x00030200, +/*105D*/ 0x42100010, +/*105E*/ 0x0106093E, +/*105F*/ 0x000F063D, +/*1060*/ 0x011700C8, +/*1061*/ 0x04100140, +/*1062*/ 0x00000100, +/*1063*/ 0x000001D1, +/*1064*/ 0x00000000, +/*1065*/ 0x05000068, +/*1066*/ 0x00030400, +/*1067*/ 0x01400000, +/*1068*/ 0x80800300, +/*1069*/ 0x00160010, +/*106A*/ 0x76543210, +/*106B*/ 0x00000008, +/*106C*/ 0x03010301, +/*106D*/ 0x03010301, +/*106E*/ 0x03010301, +/*106F*/ 0x03010301, +/*1070*/ 0x03010301, +/*1071*/ 0x00000000, +/*1072*/ 0x00500050, +/*1073*/ 0x00500050, +/*1074*/ 0x00500050, +/*1075*/ 0x00500050, +/*1076*/ 0x00500050, +/*1077*/ 0x00500050, +/*1078*/ 0x00500050, +/*1079*/ 0x00500050, +/*107A*/ 0x00500050, +/*107B*/ 0x00070087, +/*107C*/ 0x00000000, +/*107D*/ 0x08010007, +/*107E*/ 0x00000000, +/*107F*/ 0x20202020, +/*1080*/ 0x20202020, +/*1081*/ 0x20202020, +/*1082*/ 0x00000000, +/*1083*/ 0x00000000, +/*1084*/ 0x00000000, +/*1085*/ 0x00000000, +/*1086*/ 0x00000000, +/*1087*/ 0x00000000, +/*1088*/ 0x00000000, +/*1089*/ 0x00000000, +/*108A*/ 0x00000000, +/*108B*/ 0x00000000 +}; + +static const uint32_t DDR_PHY_ADR_V_REGSET_V4M[DDR_PHY_ADR_V_REGSET_NUM_V4M] = { +/*1200*/ 0x00200030, +/*1201*/ 0x00202002, +/*1202*/ 0x76543210, +/*1203*/ 0x00010001, +/*1204*/ 0x06543210, +/*1205*/ 0x03070000, +/*1206*/ 0x00001000, +/*1207*/ 0x00000000, +/*1208*/ 0x00000000, +/*1209*/ 0x00000000, +/*120A*/ 0x00000000, +/*120B*/ 0x00000000, +/*120C*/ 0x00000000, +/*120D*/ 0x00000000, +/*120E*/ 0x00000000, +/*120F*/ 0x0000807F, +/*1210*/ 0x00000001, +/*1211*/ 0x00000003, +/*1212*/ 0x00000000, +/*1213*/ 0x000F0000, +/*1214*/ 0x030C000F, +/*1215*/ 0x00020103, +/*1216*/ 0x0000000F, +/*1217*/ 0x00000100, +/*1218*/ 0x00000000, +/*1219*/ 0x00000000, +/*121A*/ 0x00000000, +/*121B*/ 0x00000000, +/*121C*/ 0x00000000, +/*121D*/ 0x00040000, +/*121E*/ 0x002A0200, +/*121F*/ 0x00000000, +/*1220*/ 0x00000000, +/*1221*/ 0x00000000, +/*1222*/ 0x00000000, +/*1223*/ 0x00200101, +/*1224*/ 0x10002C03, +/*1225*/ 0x00000003, +/*1226*/ 0x00030240, +/*1227*/ 0x00008008, +/*1228*/ 0x00081020, +/*1229*/ 0x01200000, +/*122A*/ 0x00010001, +/*122B*/ 0x00000000, +/*122C*/ 0x00100302, +/*122D*/ 0x003E4208, +/*122E*/ 0x01400140, +/*122F*/ 0x01400140, +/*1230*/ 0x01400140, +/*1231*/ 0x01400140, +/*1232*/ 0x00000100, +/*1233*/ 0x00000100, +/*1234*/ 0x00000100, +/*1235*/ 0x00000100, +/*1236*/ 0x00000000, +/*1237*/ 0x00000000, +/*1238*/ 0x00000000, +/*1239*/ 0x00000000, +/*123A*/ 0x00020580, +/*123B*/ 0x03000040, +/*123C*/ 0x00000000 +}; + +static const uint32_t DDR_PHY_ADR_G_REGSET_V4M[DDR_PHY_ADR_G_REGSET_NUM_V4M] = { +/*1300*/ 0x00000000, +/*1301*/ 0x00000100, +/*1302*/ 0x00000001, +/*1303*/ 0x23800000, +/*1304*/ 0x00000000, +/*1305*/ 0x01000101, +/*1306*/ 0x01000000, +/*1307*/ 0x00000000, +/*1308*/ 0x00000000, +/*1309*/ 0x00000000, +/*130A*/ 0x00000000, +/*130B*/ 0x00000000, +/*130C*/ 0x00040101, +/*130D*/ 0x00000000, +/*130E*/ 0x00000000, +/*130F*/ 0x00000064, +/*1310*/ 0x00000000, +/*1311*/ 0x00000000, +/*1312*/ 0x39421B42, +/*1313*/ 0x00010124, +/*1314*/ 0x00520052, +/*1315*/ 0x00000052, +/*1316*/ 0x00000000, +/*1317*/ 0x00000000, +/*1318*/ 0x00010001, +/*1319*/ 0x00000000, +/*131A*/ 0x00000000, +/*131B*/ 0x00010001, +/*131C*/ 0x00000000, +/*131D*/ 0x00000000, +/*131E*/ 0x00010001, +/*131F*/ 0x07030102, +/*1320*/ 0x01030307, +/*1321*/ 0x00000094, +/*1322*/ 0x00004096, +/*1323*/ 0x08200820, +/*1324*/ 0x08200820, +/*1325*/ 0x08200820, +/*1326*/ 0x08200820, +/*1327*/ 0x08200820, +/*1328*/ 0x004103B8, +/*1329*/ 0x0000003F, +/*132A*/ 0x000C0006, +/*132B*/ 0x00000000, +/*132C*/ 0x000004C0, +/*132D*/ 0x00000000, +/*132E*/ 0x00000208, +/*132F*/ 0x00000000, +/*1330*/ 0x00000000, +/*1331*/ 0x00000000, +/*1332*/ 0x00000000, +/*1333*/ 0x00000000, +/*1334*/ 0x03000000, +/*1335*/ 0x00000000, +/*1336*/ 0x00000000, +/*1337*/ 0x00000002, +/*1338*/ 0x00041020, +/*1339*/ 0x00041020, +/*133A*/ 0x01C98C98, +/*133B*/ 0x3F400000, +/*133C*/ 0x003F3F3F, +/*133D*/ 0x00000000, +/*133E*/ 0x00000000, +/*133F*/ 0x76543210, +/*1340*/ 0x01010098, +/*1341*/ 0x00000007, +/*1342*/ 0x00000000, +/*1343*/ 0x00000000, +/*1344*/ 0x00000000, +/*1345*/ 0x00000002, +/*1346*/ 0x00000000, +/*1347*/ 0x00000000, +/*1348*/ 0x0000017F, +/*1349*/ 0x00000000, +/*134A*/ 0x01032380, +/*134B*/ 0x00000100, +/*134C*/ 0x00000000, +/*134D*/ 0x31421342, +/*134E*/ 0x00308000, +/*134F*/ 0x00000080, +/*1350*/ 0x00063F77, +/*1351*/ 0x00000006, +/*1352*/ 0x0000033F, +/*1353*/ 0x0000033F, +/*1354*/ 0x0000033F, +/*1355*/ 0x00033F00, +/*1356*/ 0x00CC0000, +/*1357*/ 0x00033F00, +/*1358*/ 0x00CC0000, +/*1359*/ 0x00033F77, +/*135A*/ 0x00000000, +/*135B*/ 0x00033F00, +/*135C*/ 0x00EE0000, +/*135D*/ 0x00033F00, +/*135E*/ 0x00EE0000, +/*135F*/ 0x00033F00, +/*1360*/ 0x00EE0000, +/*1361*/ 0x00200106 +}; + +static const uint32_t DDR_PI_REGSET_V4M[DDR_PI_REGSET_NUM_V4M] = { +/*0800*/ 0x00000D00, +/*0801*/ 0x00000000, +/*0802*/ 0x00000000, +/*0803*/ 0x00010100, +/*0804*/ 0x00640004, +/*0805*/ 0x00000001, +/*0806*/ 0x00000000, +/*0807*/ 0x00000000, +/*0808*/ 0x00000000, +/*0809*/ 0x00000000, +/*080A*/ 0xFFFFFFFF, +/*080B*/ 0x02010000, +/*080C*/ 0x00000003, +/*080D*/ 0x00000005, +/*080E*/ 0x00000002, +/*080F*/ 0x00000000, +/*0810*/ 0x00000101, +/*0811*/ 0x0012080E, +/*0812*/ 0x00000000, +/*0813*/ 0x001E2C0E, +/*0814*/ 0x00000000, +/*0815*/ 0x00030300, +/*0816*/ 0x01010700, +/*0817*/ 0x00000001, +/*0818*/ 0x00000001, +/*0819*/ 0x00000000, +/*081A*/ 0x00000000, +/*081B*/ 0x00000000, +/*081C*/ 0x00000000, +/*081D*/ 0x00000000, +/*081E*/ 0x00000000, +/*081F*/ 0x07010000, +/*0820*/ 0x00000028, +/*0821*/ 0x00000000, +/*0822*/ 0x00320003, +/*0823*/ 0x00000000, +/*0824*/ 0x00000000, +/*0825*/ 0x04022004, +/*0826*/ 0x01040100, +/*0827*/ 0x00000000, +/*0828*/ 0x00000001, +/*0829*/ 0x000000AA, +/*082A*/ 0x00000055, +/*082B*/ 0x000000B5, +/*082C*/ 0x0000004A, +/*082D*/ 0x00000056, +/*082E*/ 0x000000A9, +/*082F*/ 0x000000A9, +/*0830*/ 0x000000B5, +/*0831*/ 0x00000000, +/*0832*/ 0x01000000, +/*0833*/ 0x00030300, +/*0834*/ 0x0000001A, +/*0835*/ 0x000007D0, +/*0836*/ 0x00000300, +/*0837*/ 0x00000000, +/*0838*/ 0x00000000, +/*0839*/ 0x01000000, +/*083A*/ 0x00000101, +/*083B*/ 0x00000000, +/*083C*/ 0x00000000, +/*083D*/ 0x00000000, +/*083E*/ 0x00000200, +/*083F*/ 0x03030300, +/*0840*/ 0x01000000, +/*0841*/ 0x00000000, +/*0842*/ 0x01000000, +/*0843*/ 0x07010001, +/*0844*/ 0x00000007, +/*0845*/ 0x00000000, +/*0846*/ 0x03000100, +/*0847*/ 0x00000000, +/*0848*/ 0x00001703, +/*0849*/ 0x00000000, +/*084A*/ 0x00000000, +/*084B*/ 0x00000000, +/*084C*/ 0x0A0A140A, +/*084D*/ 0x10020201, +/*084E*/ 0x332A0002, +/*084F*/ 0x01010000, +/*0850*/ 0x0B000404, +/*0851*/ 0x04030308, +/*0852*/ 0x00010100, +/*0853*/ 0x02020301, +/*0854*/ 0x01001000, +/*0855*/ 0x00000034, +/*0856*/ 0x00000000, +/*0857*/ 0x00000000, +/*0858*/ 0x00000000, +/*0859*/ 0x00000000, +/*085A*/ 0x00000000, +/*085B*/ 0x00080000, +/*085C*/ 0x00000000, +/*085D*/ 0x55AA55AA, +/*085E*/ 0x33CC33CC, +/*085F*/ 0x0FF00FF0, +/*0860*/ 0x0F0FF0F0, +/*0861*/ 0x00008E38, +/*0862*/ 0x00000001, +/*0863*/ 0x00000002, +/*0864*/ 0x00020001, +/*0865*/ 0x00020001, +/*0866*/ 0x02010201, +/*0867*/ 0x0000000F, +/*0868*/ 0x00000000, +/*0869*/ 0x00000000, +/*086A*/ 0x00000000, +/*086B*/ 0x00000000, +/*086C*/ 0x00000000, +/*086D*/ 0x00000000, +/*086E*/ 0x00000000, +/*086F*/ 0x00000000, +/*0870*/ 0x00000000, +/*0871*/ 0x00000000, +/*0872*/ 0xAAAAA593, +/*0873*/ 0xA5939999, +/*0874*/ 0x00000000, +/*0875*/ 0x0000AA55, +/*0876*/ 0x00006633, +/*0877*/ 0x000198CC, +/*0878*/ 0x00000000, +/*0879*/ 0x0003FFFF, +/*087A*/ 0x00006633, +/*087B*/ 0x000198CC, +/*087C*/ 0x00000000, +/*087D*/ 0x036DB6DB, +/*087E*/ 0x00249249, +/*087F*/ 0x05B6DB6D, +/*0880*/ 0x00000000, +/*0881*/ 0x00000000, +/*0882*/ 0x00000000, +/*0883*/ 0x00000000, +/*0884*/ 0x00000000, +/*0885*/ 0x036DB6DB, +/*0886*/ 0x00249249, +/*0887*/ 0x05B6DB6D, +/*0888*/ 0x00000000, +/*0889*/ 0x00000000, +/*088A*/ 0x00000000, +/*088B*/ 0x00000000, +/*088C*/ 0x00000000, +/*088D*/ 0x01000000, +/*088E*/ 0x00000100, +/*088F*/ 0x00000000, +/*0890*/ 0x00000000, +/*0891*/ 0x00000000, +/*0892*/ 0x00000000, +/*0893*/ 0x00000000, +/*0894*/ 0x00000000, +/*0895*/ 0x00000000, +/*0896*/ 0x00000000, +/*0897*/ 0x00010000, +/*0898*/ 0x00000000, +/*0899*/ 0x00000000, +/*089A*/ 0x00000000, +/*089B*/ 0x00000000, +/*089C*/ 0x00000000, +/*089D*/ 0x00000000, +/*089E*/ 0x00000000, +/*089F*/ 0x00000000, +/*08A0*/ 0x00000000, +/*08A1*/ 0x00000000, +/*08A2*/ 0x00000000, +/*08A3*/ 0x00000000, +/*08A4*/ 0x00010000, +/*08A5*/ 0x00000000, +/*08A6*/ 0x00000000, +/*08A7*/ 0x00000000, +/*08A8*/ 0x00000000, +/*08A9*/ 0x00000000, +/*08AA*/ 0x00000000, +/*08AB*/ 0x00000000, +/*08AC*/ 0x00000000, +/*08AD*/ 0x00000000, +/*08AE*/ 0x00000000, +/*08AF*/ 0x00000000, +/*08B0*/ 0x00000000, +/*08B1*/ 0x00080000, +/*08B2*/ 0x00000000, +/*08B3*/ 0x00000000, +/*08B4*/ 0x00000000, +/*08B5*/ 0x00000000, +/*08B6*/ 0x00000000, +/*08B7*/ 0x00000000, +/*08B8*/ 0x00000000, +/*08B9*/ 0x00000000, +/*08BA*/ 0x00000000, +/*08BB*/ 0x00000000, +/*08BC*/ 0x01000400, +/*08BD*/ 0x03020100, +/*08BE*/ 0x00060504, +/*08BF*/ 0x00010000, +/*08C0*/ 0x02000008, +/*08C1*/ 0x00000000, +/*08C2*/ 0x01000001, +/*08C3*/ 0x00010000, +/*08C4*/ 0x00000006, +/*08C5*/ 0x0000000E, +/*08C6*/ 0x00000100, +/*08C7*/ 0x00000000, +/*08C8*/ 0x00000000, +/*08C9*/ 0x00000000, +/*08CA*/ 0x00000000, +/*08CB*/ 0x03010000, +/*08CC*/ 0x01000100, +/*08CD*/ 0x01020001, +/*08CE*/ 0x00010300, +/*08CF*/ 0x05000104, +/*08D0*/ 0x01060001, +/*08D1*/ 0x00010700, +/*08D2*/ 0x00000000, +/*08D3*/ 0x00000000, +/*08D4*/ 0x00010000, +/*08D5*/ 0x00000000, +/*08D6*/ 0x00000000, +/*08D7*/ 0x00000000, +/*08D8*/ 0x00000000, +/*08D9*/ 0x01000000, +/*08DA*/ 0x00000008, +/*08DB*/ 0x00000000, +/*08DC*/ 0x01010000, +/*08DD*/ 0x00000000, +/*08DE*/ 0x00000200, +/*08DF*/ 0x00000001, +/*08E0*/ 0xB8000000, +/*08E1*/ 0x010000FF, +/*08E2*/ 0x0000FFE8, +/*08E3*/ 0x00FFA801, +/*08E4*/ 0xFFD80100, +/*08E5*/ 0x00007F10, +/*08E6*/ 0x00000000, +/*08E7*/ 0x00000034, +/*08E8*/ 0x00000042, +/*08E9*/ 0x00020079, +/*08EA*/ 0x02000200, +/*08EB*/ 0x02000204, +/*08EC*/ 0x0F0D0C06, +/*08ED*/ 0x08030600, +/*08EE*/ 0x10080408, +/*08EF*/ 0x05080806, +/*08F0*/ 0x10241409, +/*08F1*/ 0x170E1C08, +/*08F2*/ 0x000B120C, +/*08F3*/ 0x00000063, +/*08F4*/ 0x0000004C, +/*08F5*/ 0x00000305, +/*08F6*/ 0x00000130, +/*08F7*/ 0x10000C2E, +/*08F8*/ 0x00040404, +/*08F9*/ 0x08003200, +/*08FA*/ 0x08002701, +/*08FB*/ 0x0F003201, +/*08FC*/ 0x00000000, +/*08FD*/ 0x00000000, +/*08FE*/ 0x00000000, +/*08FF*/ 0x01030000, +/*0900*/ 0x01030103, +/*0901*/ 0x03000000, +/*0902*/ 0x00000103, +/*0903*/ 0x01030300, +/*0904*/ 0x03000000, +/*0905*/ 0x0014000C, +/*0906*/ 0x0E060037, +/*0907*/ 0x03030526, +/*0908*/ 0x000C0032, +/*0909*/ 0x0019003F, +/*090A*/ 0x0025004B, +/*090B*/ 0x00010101, +/*090C*/ 0x00000007, +/*090D*/ 0x00000032, +/*090E*/ 0x010000C8, +/*090F*/ 0x00080000, +/*0910*/ 0x00040008, +/*0911*/ 0x00000100, +/*0912*/ 0x00330033, +/*0913*/ 0x01000015, +/*0914*/ 0x00C90000, +/*0915*/ 0x005100C9, +/*0916*/ 0x2E002E2E, +/*0917*/ 0x3329002E, +/*0918*/ 0x0A070600, +/*0919*/ 0x0A07060D, +/*091A*/ 0x0D09070D, +/*091B*/ 0x000C000D, +/*091C*/ 0x00001000, +/*091D*/ 0x00000C00, +/*091E*/ 0x00001000, +/*091F*/ 0x00000C00, +/*0920*/ 0x02001000, +/*0921*/ 0x00100007, +/*0922*/ 0x00160032, +/*0923*/ 0x1E1A00C8, +/*0924*/ 0x00140004, +/*0925*/ 0x361C0010, +/*0926*/ 0x00000000, +/*0927*/ 0x0006000C, +/*0928*/ 0x00000F00, +/*0929*/ 0x361C000B, +/*092A*/ 0x00000300, +/*092B*/ 0x000E0014, +/*092C*/ 0x00001B08, +/*092D*/ 0x361C0018, +/*092E*/ 0x00000300, +/*092F*/ 0x00220037, +/*0930*/ 0x00000024, +/*0931*/ 0x00000003, +/*0932*/ 0x08020200, +/*0933*/ 0x04040404, +/*0934*/ 0x0006C906, +/*0935*/ 0x20010003, +/*0936*/ 0x000A0602, +/*0937*/ 0x04040405, +/*0938*/ 0x07040404, +/*0939*/ 0x0009315C, +/*093A*/ 0x06031001, +/*093B*/ 0x0F11040A, +/*093C*/ 0x040A0A04, +/*093D*/ 0xC5701C0A, +/*093E*/ 0x10020022, +/*093F*/ 0x000A0D0C, +/*0940*/ 0x000000C6, +/*0941*/ 0x000007BC, +/*0942*/ 0x0000060A, +/*0943*/ 0x00003C64, +/*0944*/ 0x0000185C, +/*0945*/ 0x0000F398, +/*0946*/ 0x004E000D, +/*0947*/ 0x03030136, +/*0948*/ 0x00157C03, +/*0949*/ 0x0000157C, +/*094A*/ 0x0000D6D8, +/*094B*/ 0x00000002, +/*094C*/ 0x00000037, +/*094D*/ 0x0000000B, +/*094E*/ 0x00009C40, +/*094F*/ 0x00009C40, +/*0950*/ 0x00061A80, +/*0951*/ 0x0000000A, +/*0952*/ 0x00000190, +/*0953*/ 0x0000004E, +/*0954*/ 0x00027100, +/*0955*/ 0x00027100, +/*0956*/ 0x00186A00, +/*0957*/ 0x00000028, +/*0958*/ 0x00000640, +/*0959*/ 0x01000136, +/*095A*/ 0x002A0040, +/*095B*/ 0x00010004, +/*095C*/ 0x012C0040, +/*095D*/ 0x00010006, +/*095E*/ 0x04B00040, +/*095F*/ 0x00000318, +/*0960*/ 0x0028000A, +/*0961*/ 0x05040404, +/*0962*/ 0x00040603, +/*0963*/ 0x06030503, +/*0964*/ 0x05030019, +/*0965*/ 0x00640603, +/*0966*/ 0x06040608, +/*0967*/ 0x00040604, +/*0968*/ 0x004C000B, +/*0969*/ 0x01050130, +/*096A*/ 0x01000100, +/*096B*/ 0x02020100, +/*096C*/ 0x04000000, +/*096D*/ 0x06010404, +/*096E*/ 0x07010401, +/*096F*/ 0x00000001, +/*0970*/ 0x00030201, +/*0971*/ 0x02010100, +/*0972*/ 0x00000002, +/*0973*/ 0x00000000, +/*0974*/ 0x017F0000, +/*0975*/ 0x01010101, +/*0976*/ 0x00000001, +/*0977*/ 0x00000000, +/*0978*/ 0x00000000, +/*0979*/ 0x00000000, +/*097A*/ 0x00000000, +/*097B*/ 0x01000000, +/*097C*/ 0x01000101, +/*097D*/ 0x00000000, +/*097E*/ 0x00000000, +/*097F*/ 0x08201020, +/*0980*/ 0x28100020, +/*0981*/ 0x08083020, +/*0982*/ 0x08400020, +/*0983*/ 0x08402020, +/*0984*/ 0x08483020, +/*0985*/ 0x10083020, +/*0986*/ 0x20180020, +/*0987*/ 0x30480020, +/*0988*/ 0x78880020, +/*0989*/ 0x488010E0, +/*098A*/ 0x494B0000, +/*098B*/ 0x49089080, +/*098C*/ 0x49080000, +/*098D*/ 0x490011C0, +/*098E*/ 0x0A000020, +/*098F*/ 0x08000020, +/*0990*/ 0x08000020, +/*0991*/ 0x08000020, +/*0992*/ 0x08000020, +/*0993*/ 0x08000020, +/*0994*/ 0x08000020, +/*0995*/ 0x08000020, +/*0996*/ 0x08000020, +/*0997*/ 0x08000020, +/*0998*/ 0x08000020, +/*0999*/ 0x08000020, +/*099A*/ 0x08000020, +/*099B*/ 0x08000020, +/*099C*/ 0x08000020, +/*099D*/ 0x08000020, +/*099E*/ 0x08000020, +/*099F*/ 0x08000020, +/*09A0*/ 0x08000020, +/*09A1*/ 0x08000020, +/*09A2*/ 0x08000020, +/*09A3*/ 0x08000020, +/*09A4*/ 0x08000020, +/*09A5*/ 0x08000020, +/*09A6*/ 0x08000020, +/*09A7*/ 0x08000020, +/*09A8*/ 0x08000020, +/*09A9*/ 0x08000020, +/*09AA*/ 0x08000020, +/*09AB*/ 0x08000020, +/*09AC*/ 0x08084340, +/*09AD*/ 0x0011FFFF, +/*09AE*/ 0x2011FFFB, +/*09AF*/ 0x00012E00, +/*09B0*/ 0x001100EF, +/*09B1*/ 0x01A1120B, +/*09B2*/ 0x001F0000, +/*09B3*/ 0x081E4340, +/*09B4*/ 0x00212E00, +/*09B5*/ 0x01A1120B, +/*09B6*/ 0x003F0000, +/*09B7*/ 0x001A12FF, +/*09B8*/ 0x00051A00, +/*09B9*/ 0x001A13FF, +/*09BA*/ 0x00051B00, +/*09BB*/ 0x001F13FF, +/*09BC*/ 0x001F13FF, +/*09BD*/ 0x001A12FF, +/*09BE*/ 0x00051A00, +/*09BF*/ 0x001A13FF, +/*09C0*/ 0x00051B00, +/*09C1*/ 0x001F13FF, +/*09C2*/ 0x001F13FF, +/*09C3*/ 0x001A12FF, +/*09C4*/ 0x00051A00, +/*09C5*/ 0x001A13FF, +/*09C6*/ 0x00051B00, +/*09C7*/ 0x001F13FF, +/*09C8*/ 0x001F13FF, +/*09C9*/ 0x11910048, +/*09CA*/ 0x09910060, +/*09CB*/ 0x19A21009, +/*09CC*/ 0x19A10100, +/*09CD*/ 0x19A10201, +/*09CE*/ 0x19A10302, +/*09CF*/ 0x19A10A03, +/*09D0*/ 0x19A10B04, +/*09D1*/ 0x18051C00, +/*09D2*/ 0x19A1110A, +/*09D3*/ 0x19A1120B, +/*09D4*/ 0x19A1130C, +/*09D5*/ 0x19A1140D, +/*09D6*/ 0x19A1160E, +/*09D7*/ 0x181140BF, +/*09D8*/ 0x19A11009, +/*09D9*/ 0x18051900, +/*09DA*/ 0x19A10C05, +/*09DB*/ 0x10051F00, +/*09DC*/ 0x19A00C00, +/*09DD*/ 0x10001F00, +/*09DE*/ 0x19A10E07, +/*09DF*/ 0x10051F00, +/*09E0*/ 0x19A10F08, +/*09E1*/ 0x10051F00, +/*09E2*/ 0x181102FD, +/*09E3*/ 0x19A11C15, +/*09E4*/ 0x18051F00, +/*09E5*/ 0x19910280, +/*09E6*/ 0x19A21009, +/*09E7*/ 0x18051000, +/*09E8*/ 0x180E1200, +/*09E9*/ 0x18861101, +/*09EA*/ 0x181F0000, +/*09EB*/ 0x18861100, +/*09EC*/ 0x1810214A, +/*09ED*/ 0x1810314B, +/*09EE*/ 0x18101149, +/*09EF*/ 0x18061180, +/*09F0*/ 0x18067FC0, +/*09F1*/ 0x18101149, +/*09F2*/ 0x18051200, +/*09F3*/ 0x19A11C15, +/*09F4*/ 0x19A11009, +/*09F5*/ 0x18051800, +/*09F6*/ 0x101B0001, +/*09F7*/ 0x181B0100, +/*09F8*/ 0x18000500, +/*09F9*/ 0x181B0200, +/*09FA*/ 0x00000000, +/*09FB*/ 0x181B0600, +/*09FC*/ 0x181B0C00, +/*09FD*/ 0x181B0100, +/*09FE*/ 0x181B0200, +/*09FF*/ 0x181B0300, +/*0A00*/ 0x181B0400, +/*0A01*/ 0x1C440316, +/*0A02*/ 0x100D0000, +/*0A03*/ 0x101C0000, +/*0A04*/ 0x181F0000, +/*0A05*/ 0x09910260, +/*0A06*/ 0x11911600, +/*0A07*/ 0x19A21009, +/*0A08*/ 0x18051900, +/*0A09*/ 0x19A10100, +/*0A0A*/ 0x19A10201, +/*0A0B*/ 0x19A10302, +/*0A0C*/ 0x19A10A03, +/*0A0D*/ 0x19A10B04, +/*0A0E*/ 0x19A10C05, +/*0A0F*/ 0x19A10E07, +/*0A10*/ 0x19A10F08, +/*0A11*/ 0x19A1110A, +/*0A12*/ 0x19A1120B, +/*0A13*/ 0x19A1130C, +/*0A14*/ 0x19A1140D, +/*0A15*/ 0x19A00C00, +/*0A16*/ 0x199F0000, +/*0A17*/ 0x199F0000, +/*0A18*/ 0x001100BF, +/*0A19*/ 0x01A1120B, +/*0A1A*/ 0x080D0000, +/*0A1B*/ 0x001F0000, +/*0A1C*/ 0x001F0000, +/*0A1D*/ 0x001F0000, +/*0A1E*/ 0x080C0000, +/*0A1F*/ 0x001F0000, +/*0A20*/ 0x001F0000, +/*0A21*/ 0x001F0000, +/*0A22*/ 0x001F0000, +/*0A23*/ 0x001F0000, +/*0A24*/ 0x001F0200, +/*0A25*/ 0x00050000, +/*0A26*/ 0x00070100, +/*0A27*/ 0x000F0200, +/*0A28*/ 0x00000000, +/*0A29*/ 0x01A10100, +/*0A2A*/ 0x01A10201, +/*0A2B*/ 0x01A10302, +/*0A2C*/ 0x01A00B04, +/*0A2D*/ 0x00210D06, +/*0A2E*/ 0x01A1110A, +/*0A2F*/ 0x01A1140D, +/*0A30*/ 0x00098000, +/*0A31*/ 0x019F0000, +/*0A32*/ 0x01A10100, +/*0A33*/ 0x01A10201, +/*0A34*/ 0x01A10302, +/*0A35*/ 0x01A10A03, +/*0A36*/ 0x01A10B04, +/*0A37*/ 0x00210D06, +/*0A38*/ 0x01A1110A, +/*0A39*/ 0x00000000, +/*0A3A*/ 0x01A1140D, +/*0A3B*/ 0x00000000, +/*0A3C*/ 0x00000000, +/*0A3D*/ 0x01A11C15, +/*0A3E*/ 0x01A1120B, +/*0A3F*/ 0x01A0190F, +/*0A40*/ 0x000A0000, +/*0A41*/ 0x001F0000, +/*0A42*/ 0x000A0000, +/*0A43*/ 0x01061300, +/*0A44*/ 0x00000000, +/*0A45*/ 0x00000000, +/*0A46*/ 0x00061180, +/*0A47*/ 0x000612C0, +/*0A48*/ 0x00000000, +/*0A49*/ 0x00000000, +/*0A4A*/ 0x001F0000, +/*0A4B*/ 0x01910300, +/*0A4C*/ 0x01A21009, +/*0A4D*/ 0x019F0000, +/*0A4E*/ 0x001140BF, +/*0A4F*/ 0x01811009, +/*0A50*/ 0x00051900, +/*0A51*/ 0x01A10C05, +/*0A52*/ 0x00051F00, +/*0A53*/ 0x01A10C11, +/*0A54*/ 0x00051F00, +/*0A55*/ 0x001100BF, +/*0A56*/ 0x01811009, +/*0A57*/ 0x00051800, +/*0A58*/ 0x019F0000, +/*0A59*/ 0x019F0000, +/*0A5A*/ 0x019F0000, +/*0A5B*/ 0x019F0000, +/*0A5C*/ 0x019F0000, +/*0A5D*/ 0x01510001, +/*0A5E*/ 0x01D102A0, +/*0A5F*/ 0x01E21009, +/*0A60*/ 0x00051900, +/*0A61*/ 0x019F0000, +/*0A62*/ 0x01510001, +/*0A63*/ 0x01D10290, +/*0A64*/ 0x01E21009, +/*0A65*/ 0x00051900, +/*0A66*/ 0x01510001, +/*0A67*/ 0x01D10000, +/*0A68*/ 0x01E21009, +/*0A69*/ 0x00051800, +/*0A6A*/ 0x019F0000, +/*0A6B*/ 0x0011008F, +/*0A6C*/ 0x01811009, +/*0A6D*/ 0x00051800, +/*0A6E*/ 0x01910040, +/*0A6F*/ 0x01A21009, +/*0A70*/ 0x019F0000, +/*0A71*/ 0x01911000, +/*0A72*/ 0x01A21009, +/*0A73*/ 0x00051800, +/*0A74*/ 0x01A10100, +/*0A75*/ 0x01A10201, +/*0A76*/ 0x01A10302, +/*0A77*/ 0x01A10A03, +/*0A78*/ 0x01A10B04, +/*0A79*/ 0x01A10C05, +/*0A7A*/ 0x01A10E07, +/*0A7B*/ 0x01A10F08, +/*0A7C*/ 0x01A1110A, +/*0A7D*/ 0x01A1120B, +/*0A7E*/ 0x01A1130C, +/*0A7F*/ 0x01A1140D, +/*0A80*/ 0x01A00C00, +/*0A81*/ 0x01910800, +/*0A82*/ 0x01A21009, +/*0A83*/ 0x019F0000, +/*0A84*/ 0x01811009, +/*0A85*/ 0x0011EFAF, +/*0A86*/ 0x01A1120B, +/*0A87*/ 0x001F0000, +/*0A88*/ 0x001F0200, +/*0A89*/ 0x001100EF, +/*0A8A*/ 0x01A1120B, +/*0A8B*/ 0x001F0000, +/*0A8C*/ 0x01A1120B, +/*0A8D*/ 0x001F0000, +/*0A8E*/ 0x001F0000, +/*0A8F*/ 0x001100EF, +/*0A90*/ 0x01A1120B, +/*0A91*/ 0x001F0000, +/*0A92*/ 0x00211F14, +/*0A93*/ 0x00212015, +/*0A94*/ 0x00212116, +/*0A95*/ 0x00212217, +/*0A96*/ 0x01A1120B, +/*0A97*/ 0x001F0000, +/*0A98*/ 0x00211F14, +/*0A99*/ 0x00212015, +/*0A9A*/ 0x00212116, +/*0A9B*/ 0x00212217, +/*0A9C*/ 0x001F0000, +/*0A9D*/ 0x001A85FF, +/*0A9E*/ 0x001F0000, +/*0A9F*/ 0x001100FF, +/*0AA0*/ 0x01810302, +/*0AA1*/ 0x001100DF, +/*0AA2*/ 0x00010D06, +/*0AA3*/ 0x001100EF, +/*0AA4*/ 0x01A1120B, +/*0AA5*/ 0x001F0000, +/*0AA6*/ 0x00010D06, +/*0AA7*/ 0x01810302, +/*0AA8*/ 0x0181160E, +/*0AA9*/ 0x01A1120B, +/*0AAA*/ 0x001F0000, +/*0AAB*/ 0x00032300, +/*0AAC*/ 0x00032400, +/*0AAD*/ 0x001F0000, +/*0AAE*/ 0x0031FFBF, +/*0AAF*/ 0x01A11009, +/*0AB0*/ 0x00051900, +/*0AB1*/ 0x01A10E07, +/*0AB2*/ 0x00051F00, +/*0AB3*/ 0x01A10F08, +/*0AB4*/ 0x00051F00, +/*0AB5*/ 0x003100BF, +/*0AB6*/ 0x01A11009, +/*0AB7*/ 0x00051800, +/*0AB8*/ 0x003F0000, +/*0AB9*/ 0x003F0000, +/*0ABA*/ 0x003F0000, +/*0ABB*/ 0x003F0000, +/*0ABC*/ 0x003F0000, +/*0ABD*/ 0x0031FFBF, +/*0ABE*/ 0x01A11009, +/*0ABF*/ 0x00051900, +/*0AC0*/ 0x01A10E07, +/*0AC1*/ 0x00051F00, +/*0AC2*/ 0x01A10F08, +/*0AC3*/ 0x00051F00, +/*0AC4*/ 0x003100BF, +/*0AC5*/ 0x01A11009, +/*0AC6*/ 0x00051800, +/*0AC7*/ 0x003F0000, +/*0AC8*/ 0x003F0000, +/*0AC9*/ 0x003F0000, +/*0ACA*/ 0x003F0000, +/*0ACB*/ 0x003F0000, +/*0ACC*/ 0x001100EF, +/*0ACD*/ 0x01A1120B, +/*0ACE*/ 0x00051400, +/*0ACF*/ 0x001A0800, +/*0AD0*/ 0x001102FD, +/*0AD1*/ 0x00012E00, +/*0AD2*/ 0x00000000, +/*0AD3*/ 0x001F0000, +/*0AD4*/ 0x001100FD, +/*0AD5*/ 0x00012E00, +/*0AD6*/ 0x00051700, +/*0AD7*/ 0x001A0801, +/*0AD8*/ 0x01A1120B, +/*0AD9*/ 0x001F0000, +/*0ADA*/ 0x001100EF, +/*0ADB*/ 0x01A1120B, +/*0ADC*/ 0x00051400, +/*0ADD*/ 0x001A0800, +/*0ADE*/ 0x001101FC, +/*0ADF*/ 0x00011A00, +/*0AE0*/ 0x00000000, +/*0AE1*/ 0x001F0000, +/*0AE2*/ 0x00051500, +/*0AE3*/ 0x001103FC, +/*0AE4*/ 0x00011A00, +/*0AE5*/ 0x00051500, +/*0AE6*/ 0x001102FC, +/*0AE7*/ 0x00011A00, +/*0AE8*/ 0x00001A00, +/*0AE9*/ 0x00000000, +/*0AEA*/ 0x001F0000, +/*0AEB*/ 0x001100FC, +/*0AEC*/ 0x00011A00, +/*0AED*/ 0x001A0801, +/*0AEE*/ 0x01A1120B, +/*0AEF*/ 0x00000000, +/*0AF0*/ 0x001F0000, +/*0AF1*/ 0x001108E7, +/*0AF2*/ 0x01A1120B, +/*0AF3*/ 0x00051400, +/*0AF4*/ 0x01910480, +/*0AF5*/ 0x01821009, +/*0AF6*/ 0x001F0000, +/*0AF7*/ 0x001A0800, +/*0AF8*/ 0x01A11E14, +/*0AF9*/ 0x001101FC, +/*0AFA*/ 0x00211A00, +/*0AFB*/ 0x00051500, +/*0AFC*/ 0x001103FC, +/*0AFD*/ 0x00011A00, +/*0AFE*/ 0x00051500, +/*0AFF*/ 0x001102FC, +/*0B00*/ 0x00011A00, +/*0B01*/ 0x00031A00, +/*0B02*/ 0x001A0801, +/*0B03*/ 0x00000000, +/*0B04*/ 0x001F0000, +/*0B05*/ 0x01A11E14, +/*0B06*/ 0x001108F7, +/*0B07*/ 0x01A1120B, +/*0B08*/ 0x001F0000, +/*0B09*/ 0x00000000, +/*0B0A*/ 0x00000000, +/*0B0B*/ 0x00000000, +/*0B0C*/ 0x00000000, +/*0B0D*/ 0x00000000, +/*0B0E*/ 0x00000000, +/*0B0F*/ 0x00000000, +/*0B10*/ 0x00000000, +/*0B11*/ 0x00000000, +/*0B12*/ 0x001F0000, +/*0B13*/ 0x0404FF7F, +/*0B14*/ 0x0404FF7F, +/*0B15*/ 0x0404FF7F, +/*0B16*/ 0x0404FF7F, +/*0B17*/ 0x0404FF7F, +/*0B18*/ 0x0404FF7F, +/*0B19*/ 0x0404FF7F, +/*0B1A*/ 0x0404FF7F, +/*0B1B*/ 0x00000000, +/*0B1C*/ 0x00000000, +/*0B1D*/ 0x00000000, +/*0B1E*/ 0x00000000, +/*0B1F*/ 0x00000000, +/*0B20*/ 0x00000000, +/*0B21*/ 0x00000000, +/*0B22*/ 0x00000000, +/*0B23*/ 0x00000000, +/*0B24*/ 0x00000000, +/*0B25*/ 0x00000000, +/*0B26*/ 0x00000000, +/*0B27*/ 0x00000000, +/*0B28*/ 0x00000000, +/*0B29*/ 0x00000000, +/*0B2A*/ 0x00000000, +/*0B2B*/ 0x00000000, +/*0B2C*/ 0x00000000, +/*0B2D*/ 0x00000000, +/*0B2E*/ 0x00000000, +/*0B2F*/ 0x00000000, +/*0B30*/ 0x00000000, +/*0B31*/ 0x00000000, +/*0B32*/ 0x00000000, +/*0B33*/ 0x00000000, +/*0B34*/ 0x00000000, +/*0B35*/ 0x00000000, +/*0B36*/ 0x00000000, +/*0B37*/ 0x00000000, +/*0B38*/ 0x00000000, +/*0B39*/ 0x00000000, +/*0B3A*/ 0x00000000, +/*0B3B*/ 0x00000000, +/*0B3C*/ 0x00000000, +/*0B3D*/ 0x00000000, +/*0B3E*/ 0x00000000, +/*0B3F*/ 0x00000000, +/*0B40*/ 0x00000000, +/*0B41*/ 0x00000000, +/*0B42*/ 0x00000000, +/*0B43*/ 0x00000000, +/*0B44*/ 0x00000000, +/*0B45*/ 0x00000000, +/*0B46*/ 0x00000000, +/*0B47*/ 0x00000000, +/*0B48*/ 0x00000000, +/*0B49*/ 0x00000000, +/*0B4A*/ 0x00000000, +/*0B4B*/ 0x00000000, +/*0B4C*/ 0x00000000, +/*0B4D*/ 0x00000000, +/*0B4E*/ 0x00000000, +/*0B4F*/ 0x00000000, +/*0B50*/ 0x00000000, +/*0B51*/ 0x00000000, +/*0B52*/ 0x00000000, +/*0B53*/ 0x00000000, +/*0B54*/ 0x00000000, +/*0B55*/ 0x00000000, +/*0B56*/ 0x00000000, +/*0B57*/ 0x00000000, +/*0B58*/ 0x00000000, +/*0B59*/ 0x00000000, +/*0B5A*/ 0x00000000, +/*0B5B*/ 0x00000000, +/*0B5C*/ 0x00000000, +/*0B5D*/ 0x00000000, +/*0B5E*/ 0x00000000, +/*0B5F*/ 0x00000000, +/*0B60*/ 0x00000000, +/*0B61*/ 0x00000000, +/*0B62*/ 0x00000000, +/*0B63*/ 0x00000000, +/*0B64*/ 0x00000000, +/*0B65*/ 0x00000000, +/*0B66*/ 0x00000000, +/*0B67*/ 0x00000000, +/*0B68*/ 0x00000000, +/*0B69*/ 0x00000000, +/*0B6A*/ 0x00000000, +/*0B6B*/ 0x00000000, +/*0B6C*/ 0x00000000, +/*0B6D*/ 0x00000000, +/*0B6E*/ 0x00000000, +/*0B6F*/ 0x00000000, +/*0B70*/ 0x00000000, +/*0B71*/ 0x00000000, +/*0B72*/ 0x00000000, +/*0B73*/ 0x00000000, +/*0B74*/ 0x00000000, +/*0B75*/ 0x00000000, +/*0B76*/ 0x00000000, +/*0B77*/ 0x00000000, +/*0B78*/ 0x00000000, +/*0B79*/ 0x00000000, +/*0B7A*/ 0x00000000, +/*0B7B*/ 0x00000000, +/*0B7C*/ 0x00000000, +/*0B7D*/ 0x00000000, +/*0B7E*/ 0x00000000, +/*0B7F*/ 0x00000000, +/*0B80*/ 0x00000000, +/*0B81*/ 0x00000000, +/*0B82*/ 0x00070000, +/*0B83*/ 0x0011000B, +/*0B84*/ 0x001D0017, +/*0B85*/ 0x0059003F, +/*0B86*/ 0x0072006C, +/*0B87*/ 0x00790078, +/*0B88*/ 0x00960086, +/*0B89*/ 0x00A2009F, +/*0B8A*/ 0x00B600B1, +/*0B8B*/ 0x00C500BF, +/*0B8C*/ 0x00DC00D8, +/*0B8D*/ 0x00E000DD, +/*0B8E*/ 0x00E600E3, +/*0B8F*/ 0x00F100EC, +/*0B90*/ 0x00FA00F3, +/*0B91*/ 0x010200FF, +/*0B92*/ 0x01200111, +/*0B93*/ 0x012E0128, +/*0B94*/ 0x013F0136, +/*0B95*/ 0x014B0145, +/*0B96*/ 0x015D0159, +/*0B97*/ 0x01680167, +/*0B98*/ 0x016A0169, +/*0B99*/ 0x016C016B, +/*0B9A*/ 0x016E016D, +/*0B9B*/ 0x00000000, +/*0B9C*/ 0x00000000, +/*0B9D*/ 0x004B1040, +/*0B9E*/ 0x001011C0, +/*0B9F*/ 0x00089080, +/*0BA0*/ 0x000811C0, +/*0BA1*/ 0x040811C0, +/*0BA2*/ 0x02000000, +/*0BA3*/ 0x00000000, +/*0BA4*/ 0x00000000, +/*0BA5*/ 0x00000000, +/*0BA6*/ 0x00000000, +/*0BA7*/ 0x00000000, +/*0BA8*/ 0x00000000, +/*0BA9*/ 0x00000000, +/*0BAA*/ 0x00000000, +/*0BAB*/ 0x00000000, +/*0BAC*/ 0x00000000, +/*0BAD*/ 0x00000000, +/*0BAE*/ 0x00000000, +/*0BAF*/ 0x00000000, +/*0BB0*/ 0x00000000, +/*0BB1*/ 0x00000000, +/*0BB2*/ 0x00000000, +/*0BB3*/ 0x5F407FAA, +/*0BB4*/ 0x007B776F, +/*0BB5*/ 0x4AB555AA, +/*0BB6*/ 0xB5A9A956, +/*0BB7*/ 0x9F80BFAA, +/*0BB8*/ 0x00BBB7AF, +/*0BB9*/ 0x00000000, +/*0BBA*/ 0x00000000, +/*0BBB*/ 0x00000000, +/*0BBC*/ 0x00000000, +/*0BBD*/ 0x00000000, +/*0BBE*/ 0x00000000, +/*0BBF*/ 0x00000000, +/*0BC0*/ 0x00000000, +/*0BC1*/ 0x0000157C, +/*0BC2*/ 0x0000D6D8, +/*0BC3*/ 0x00000037, +/*0BC4*/ 0x00000000, +/*0BC5*/ 0x00000000, +/*0BC6*/ 0x00000000, +/*0BC7*/ 0x00000000, +/*0BC8*/ 0x00000000, +/*0BC9*/ 0x00000000, +/*0BCA*/ 0x00000000, +/*0BCB*/ 0x00000000, +/*0BCC*/ 0x00000000, +/*0BCD*/ 0x00000000, +/*0BCE*/ 0x00000000, +/*0BCF*/ 0x00000000, +/*0BD0*/ 0x00000000, +/*0BD1*/ 0x00000007, +/*0BD2*/ 0x00000032, +/*0BD3*/ 0x000000C8, +/*0BD4*/ 0x00000001, +/*0BD5*/ 0x00000001, +/*0BD6*/ 0x00000003, +/*0BD7*/ 0x00000007, +/*0BD8*/ 0x00000007, +/*0BD9*/ 0x00000009, +/*0BDA*/ 0x00000001, +/*0BDB*/ 0x00000001, +/*0BDC*/ 0x00000003, +/*0BDD*/ 0x00000001, +/*0BDE*/ 0x00000001, +/*0BDF*/ 0x00000003, +/*0BE0*/ 0x00000037, +/*0BE1*/ 0x00000190, +/*0BE2*/ 0x00000640, +/*0BE3*/ 0x00000001, +/*0BE4*/ 0x00000001, +/*0BE5*/ 0x00000003, +/*0BE6*/ 0x00000001, +/*0BE7*/ 0x00000007, +/*0BE8*/ 0x0000001C, +/*0BE9*/ 0x00000004, +/*0BEA*/ 0x00000015, +/*0BEB*/ 0x00000051, +/*0BEC*/ 0x00000008, +/*0BED*/ 0x00000033, +/*0BEE*/ 0x000000C9, +/*0BEF*/ 0x00000007, +/*0BF0*/ 0x00000002, +/*0BF1*/ 0x0000000E, +/*0BF2*/ 0x00000000, +/*0BF3*/ 0x00000000, +/*0BF4*/ 0x00000005, +/*0BF5*/ 0x00000008, +/*0BF6*/ 0x00000008, +/*0BF7*/ 0x00000008, +/*0BF8*/ 0x00000000, +/*0BF9*/ 0x00000000, +/*0BFA*/ 0x00000000, +/*0BFB*/ 0x0000157D, +/*0BFC*/ 0x0000157D, +/*0BFD*/ 0x0000157D, +/*0BFE*/ 0x00000008, +/*0BFF*/ 0x00000033, +/*0C00*/ 0x000000C9, +/*0C01*/ 0x00000000, +/*0C02*/ 0x00000000, +/*0C03*/ 0x00000000, +/*0C04*/ 0x00000000, +/*0C05*/ 0x00000000, +/*0C06*/ 0x00000000, +/*0C07*/ 0x00000000, +/*0C08*/ 0x00000000, +/*0C09*/ 0x00000000, +/*0C0A*/ 0x00000000, +/*0C0B*/ 0x00000000, +/*0C0C*/ 0x00000000, +/*0C0D*/ 0x000D000F, +/*0C0E*/ 0x00040028, +/*0C0F*/ 0x00060002, +/*0C10*/ 0x0009000C, +/*0C11*/ 0x000C0010, +/*0C12*/ 0x00150009, +/*0C13*/ 0x00040006, +/*0C14*/ 0x0004000B, +/*0C15*/ 0x00020002, +/*0C16*/ 0x00020004, +/*0C17*/ 0x00040002, +/*0C18*/ 0x00020002, +/*0C19*/ 0x00020004, +/*0C1A*/ 0x000F0002, +/*0C1B*/ 0x0028000D, +/*0C1C*/ 0x00020004, +/*0C1D*/ 0x000C0006, +/*0C1E*/ 0x00100009, +/*0C1F*/ 0x0009000C, +/*0C20*/ 0x00060015, +/*0C21*/ 0x000B0004, +/*0C22*/ 0x00020004, +/*0C23*/ 0x00040002, +/*0C24*/ 0x00020002, +/*0C25*/ 0x00020004, +/*0C26*/ 0x00040002, +/*0C27*/ 0x00020002, +/*0C28*/ 0x000D000F, +/*0C29*/ 0x00040028, +/*0C2A*/ 0x00060002, +/*0C2B*/ 0x0009000C, +/*0C2C*/ 0x000C0010, +/*0C2D*/ 0x00150009, +/*0C2E*/ 0x00040006, +/*0C2F*/ 0x0004000B, +/*0C30*/ 0x00020002, +/*0C31*/ 0x00020004, +/*0C32*/ 0x00040002, +/*0C33*/ 0x00020002, +/*0C34*/ 0x00020004, +/*0C35*/ 0x000F0002, +/*0C36*/ 0x0028000D, +/*0C37*/ 0x00020004, +/*0C38*/ 0x000C0006, +/*0C39*/ 0x00100009, +/*0C3A*/ 0x0009000C, +/*0C3B*/ 0x00060015, +/*0C3C*/ 0x000B0004, +/*0C3D*/ 0x00020004, +/*0C3E*/ 0x00040002, +/*0C3F*/ 0x00020002, +/*0C40*/ 0x00020004, +/*0C41*/ 0x00040002, +/*0C42*/ 0x00020002, +/*0C43*/ 0x00000000, +/*0C44*/ 0x00000000, +/*0C45*/ 0x00000000, +/*0C46*/ 0x00000000, +/*0C47*/ 0x00000000, +/*0C48*/ 0x00000000, +/*0C49*/ 0x00000000, +/*0C4A*/ 0x00000000, +/*0C4B*/ 0x00000000, +/*0C4C*/ 0x00000000, +/*0C4D*/ 0x00000000, +/*0C4E*/ 0x00000000, +/*0C4F*/ 0x00000000, +/*0C50*/ 0x00000000, +/*0C51*/ 0x00000000, +/*0C52*/ 0x00000000, +/*0C53*/ 0x00000000, +/*0C54*/ 0x00000000, +/*0C55*/ 0x00000000, +/*0C56*/ 0x00000000, +/*0C57*/ 0x00000000, +/*0C58*/ 0x00000000, +/*0C59*/ 0x00000000, +/*0C5A*/ 0x00000000, +/*0C5B*/ 0x00000000, +/*0C5C*/ 0x00000000, +/*0C5D*/ 0x00000000, +/*0C5E*/ 0x00000000, +/*0C5F*/ 0x00000000, +/*0C60*/ 0x00000000, +/*0C61*/ 0x00000000, +/*0C62*/ 0x00000000, +/*0C63*/ 0x00000000, +/*0C64*/ 0x00000000, +/*0C65*/ 0x00000000, +/*0C66*/ 0x000000C0, +/*0C67*/ 0x00000000, +/*0C68*/ 0x00000000, +/*0C69*/ 0x55550000, +/*0C6A*/ 0x00003C5A, +/*0C6B*/ 0x00000000, +/*0C6C*/ 0x00000000, +/*0C6D*/ 0x00000000, +/*0C6E*/ 0x00000000, +/*0C6F*/ 0x00000000, +/*0C70*/ 0x00000000, +/*0C71*/ 0x00000000, +/*0C72*/ 0x00000000, +/*0C73*/ 0x00000000, +/*0C74*/ 0x00000000, +/*0C75*/ 0x00000000, +/*0C76*/ 0x00000000, +/*0C77*/ 0x00000000, +/*0C78*/ 0x00000000, +/*0C79*/ 0x00000000, +/*0C7A*/ 0x00000000, +/*0C7B*/ 0x00000000, +/*0C7C*/ 0x00000000, +/*0C7D*/ 0x00000000, +/*0C7E*/ 0x00000000, +/*0C7F*/ 0x00000000, +/*0C80*/ 0x00000000, +/*0C81*/ 0x00000000, +/*0C82*/ 0x00000000, +/*0C83*/ 0x00000000, +/*0C84*/ 0x00000000, +/*0C85*/ 0x00000000, +/*0C86*/ 0x00000000, +/*0C87*/ 0x00000000, +/*0C88*/ 0x00000000, +/*0C89*/ 0x00000000, +/*0C8A*/ 0x00000000, +/*0C8B*/ 0x00000000, +/*0C8C*/ 0x00000000, +/*0C8D*/ 0x00000000, +/*0C8E*/ 0x00000000, +/*0C8F*/ 0x00000000, +/*0C90*/ 0x00000000, +/*0C91*/ 0x00000000, +/*0C92*/ 0x00000000, +/*0C93*/ 0x00000000, +/*0C94*/ 0x00000000, +/*0C95*/ 0x00000000, +/*0C96*/ 0x00000000, +/*0C97*/ 0x00000000, +/*0C98*/ 0x00000000, +/*0C99*/ 0x00000000, +/*0C9A*/ 0x00000000, +/*0C9B*/ 0x00000000, +/*0C9C*/ 0x00000000, +/*0C9D*/ 0x00D60000, +/*0C9E*/ 0x50005000, +/*0C9F*/ 0x803E0050, +/*0CA0*/ 0x80000200, +/*0CA1*/ 0x00000000, +/*0CA2*/ 0x00002000, +/*0CA3*/ 0x00000000, +/*0CA4*/ 0x00000000, +/*0CA5*/ 0x00000000, +/*0CA6*/ 0x00000000, +/*0CA7*/ 0x00D62220, +/*0CA8*/ 0x2C002834, +/*0CA9*/ 0x0406002C, +/*0CAA*/ 0x80000200, +/*0CAB*/ 0x00000000, +/*0CAC*/ 0x00002000, +/*0CAD*/ 0x00000000, +/*0CAE*/ 0x00000000, +/*0CAF*/ 0x00000000, +/*0CB0*/ 0x00000000, +/*0CB1*/ 0x00C6BBB0, +/*0CB2*/ 0x2C002834, +/*0CB3*/ 0x0C06002C, +/*0CB4*/ 0x80000200, +/*0CB5*/ 0x00000000, +/*0CB6*/ 0x00002000, +/*0CB7*/ 0x00000000, +/*0CB8*/ 0x00000000, +/*0CB9*/ 0x00000000, +/*0CBA*/ 0x00000000, +/*0CBB*/ 0x00D60000, +/*0CBC*/ 0x50005000, +/*0CBD*/ 0x803E0050, +/*0CBE*/ 0x80000200, +/*0CBF*/ 0x00000000, +/*0CC0*/ 0x00002000, +/*0CC1*/ 0x00000000, +/*0CC2*/ 0x00000000, +/*0CC3*/ 0x00000000, +/*0CC4*/ 0x00000000, +/*0CC5*/ 0x00D62220, +/*0CC6*/ 0x2C002834, +/*0CC7*/ 0x002E002C, +/*0CC8*/ 0x80000200, +/*0CC9*/ 0x00000000, +/*0CCA*/ 0x00002000, +/*0CCB*/ 0x00000000, +/*0CCC*/ 0x00000000, +/*0CCD*/ 0x00000000, +/*0CCE*/ 0x00000000, +/*0CCF*/ 0x00C6BBB0, +/*0CD0*/ 0x2C002834, +/*0CD1*/ 0x082E002C, +/*0CD2*/ 0x80000200, +/*0CD3*/ 0x00000000, +/*0CD4*/ 0x00002000, +/*0CD5*/ 0x00000000, +/*0CD6*/ 0x00000000, +/*0CD7*/ 0x00000000, +/*0CD8*/ 0x00000000, +/*0CD9*/ 0x20002000, +/*0CDA*/ 0x20002000, +/*0CDB*/ 0x20002000, +/*0CDC*/ 0x2000000D, +/*0CDD*/ 0x20002000, +/*0CDE*/ 0x20002000, +/*0CDF*/ 0x20002000, +/*0CE0*/ 0x00172000, +/*0CE1*/ 0x20000025, +/*0CE2*/ 0x20002000, +/*0CE3*/ 0x0020001F, +/*0CE4*/ 0x00220021, +/*0CE5*/ 0x20002000, +/*0CE6*/ 0x20002000, +/*0CE7*/ 0x20002000, +/*0CE8*/ 0x20002000, +/*0CE9*/ 0x20002000, +/*0CEA*/ 0x20002000, +/*0CEB*/ 0x20002000, +/*0CEC*/ 0x20002000, +/*0CED*/ 0x20002000, +/*0CEE*/ 0x20002000, +/*0CEF*/ 0x20002000, +/*0CF0*/ 0x20002000, +/*0CF1*/ 0x20002000, +/*0CF2*/ 0x20002000, +/*0CF3*/ 0x20002000, +/*0CF4*/ 0x20002000, +/*0CF5*/ 0x20002000, +/*0CF6*/ 0x20002000, +/*0CF7*/ 0x20002000, +/*0CF8*/ 0x20002000, +/*0CF9*/ 0x20002000, +/*0CFA*/ 0x20002000, +/*0CFB*/ 0x20002000, +/*0CFC*/ 0x20002000, +/*0CFD*/ 0x20002000, +/*0CFE*/ 0x20002000, +/*0CFF*/ 0x20002000, +/*0D00*/ 0x20002000, +/*0D01*/ 0x00020001, +/*0D02*/ 0x000A0003, +/*0D03*/ 0x000C000B, +/*0D04*/ 0x000E2000, +/*0D05*/ 0x0010000F, +/*0D06*/ 0x00120011, +/*0D07*/ 0x00140013, +/*0D08*/ 0x00190016, +/*0D09*/ 0x100C2000, +/*0D0A*/ 0x00080000, +/*0D0B*/ 0x001C001E, +/*0D0C*/ 0x20002000, +/*0D0D*/ 0x20002000, +/*0D0E*/ 0x20002000, +/*0D0F*/ 0x20002000, +/*0D10*/ 0x20002000, +/*0D11*/ 0x20002000, +/*0D12*/ 0x20002000, +/*0D13*/ 0x20002000, +/*0D14*/ 0x20002000 +}; + +#endif /* INIT_DRAM_TBL_V4M_LP5_H_ */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_boot.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_boot.c new file mode 100644 index 0000000..1a53474 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_boot.c @@ -0,0 +1,95 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc boot + ******************************************************************************/ +/****************************************************************************** + * @file emmc_boot.c + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 18.03.2022 0.02 Removed unnecessary functions + * Removed unnecessary header file inclusions + * : 16.06.2022 0.03 Change log output + * : 31.10.2022 0.04 License notation change. + *****************************************************************************/ + +#include "emmc_boot.h" +#include "log.h" +#include "emmc_std.h" +#include "emmc_def.h" + + +/************************************************************************************************/ +/* Definitions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Unions */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Structs */ +/************************************************************************************************/ + + +/************************************************************************************************/ +/* Globals */ +/************************************************************************************************/ + +/************************************************************************************************/ +/* Macros */ +/************************************************************************************************/ + +/************************************************************************************************/ +/* Prototypes */ +/************************************************************************************************/ + +void emmc_initialize( void ) +{ + EMMC_ERROR_CODE result; + + /* eMMC driver initialize */ + (void)emmc_init(); /* Normal clock mode */ + + /* Card power on */ + (void)emmc_memcard_power(TRUE); + + /* Card mount */ + result = emmc_mount(); + + if (result != EMMC_SUCCESS) + { + NOTICE("eMMC initialize error!!\n"); + panic; + } +} diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_cmd.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_cmd.c new file mode 100644 index 0000000..29c83d9 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_cmd.c @@ -0,0 +1,622 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc command + ******************************************************************************/ +/****************************************************************************** + * @file emmc_cmd.c + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 16.06.2022 0.02 Change log output + * : 31.10.2022 0.03 License notation change. + * : 07.06.2024 0.04 Modify the transfer end bit of DMAC channel. + *****************************************************************************/ + +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "timer.h" +#include "log.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static void emmc_read_response(uint32_t *response); +static void emmc_little_to_big(uint8_t *p, uint32_t value); +static void emmc_data_transfer_dma(void); +static EMMC_ERROR_CODE emmc_response_check(const uint32_t *response, uint32_t error_mask); +static void emmc_softreset(void); +static void emmc_WaitCmd2Cmd_8Cycle(void); + +/* ********************************* CODE ********************************** */ + +/* execute MMC command. + * + * - Pre-conditions:
+ * * Clock to memory card IF is enabled. + * - Post-conditions:
+ * Requested command is executed successfully + * + * param[in] error_mask Errors to be checked (error values; HAL_MEMCARD_ERRORS) + * param[in,out] *response Response from the card (virtual address) + * return eMMC error code. + */ +EMMC_ERROR_CODE emmc_exec_cmd(uint32_t error_mask, uint32_t *response) +{ + EMMC_ERROR_CODE rtn_code = EMMC_ERR; + HAL_MEMCARD_RESPONSE_TYPE response_type; + HAL_MEMCARD_COMMAND_TYPE cmd_type; + EMMC_INT_STATE state; + + /* parameter check */ + if (response == NULL) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.clock_enable != TRUE) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + if (mmc_drv_obj.state_machine_blocking == TRUE) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR); + return EMMC_ERR; + } + + state = ESTATE_BEGIN; + response_type = (HAL_MEMCARD_RESPONSE_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK); + cmd_type = (HAL_MEMCARD_COMMAND_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_COMMAND_TYPE_MASK); + + /* state machine */ + while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END)) + { + /* The interrupt factor flag is observed. */ + (void)emmc_interrupt(); + + /* wait interrupt */ + if (mmc_drv_obj.state_machine_blocking == TRUE) + { + continue; + } + + switch (state) + { + case ESTATE_BEGIN: + /* Busy check */ + if ((mmc_drv_obj.error_info.info2 & SD_INFO2_CBSY) != 0U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR_CARD_BUSY; + } + + /* clear register */ + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, SD_INFO2_CLEAR); + mem_write32(SD_INFO1_MASK, SD_INFO1_INFO0); + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + + /* fallthrough */ + + case ESTATE_ISSUE_CMD: + /* ARG */ + mem_write32(SD_ARG, mmc_drv_obj.cmd_info.arg); + /* issue cmd */ + mem_write32(SD_CMD, mmc_drv_obj.cmd_info.hw); + /* Set driver flag */ + mmc_drv_obj.state_machine_blocking = TRUE; + + if (response_type == HAL_MEMCARD_RESPONSE_NONE) + { + state = ESTATE_NON_RESP_CMD; + } else { + state = ESTATE_RCV_RESP; + } + + break; + + case ESTATE_NON_RESP_CMD: + /* interrupt disable */ + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); + + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) + { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 0U) { + /* not receive expected interrupt */ + rtn_code = EMMC_ERR_RESPONSE; + state = ESTATE_ERROR; + } else { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } + break; + + case ESTATE_RCV_RESP: + /* interrupt disable */ + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); + + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) + { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + break; + } else if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO0) == 0U) { + /* not receive expected interrupt */ + rtn_code = EMMC_ERR_RESPONSE; + state = ESTATE_ERROR; + break; + } else { + /* nop */ + } + + /* read response */ + emmc_read_response(response); + + /* check response */ + rtn_code = emmc_response_check(response, error_mask); + if (rtn_code != EMMC_SUCCESS) + { + state = ESTATE_ERROR; + break; + } + + if (response_type == HAL_MEMCARD_RESPONSE_R1b) + { + /* R1b */ + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + state = ESTATE_RCV_RESPONSE_BUSY; + } else { + state = ESTATE_CHECK_RESPONSE_COMPLETE; + } + break; + + case ESTATE_RCV_RESPONSE_BUSY: + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) + { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_ERROR; + break; + } + /* DAT0 not Busy */ + if ((SD_INFO2_DAT0 & mmc_drv_obj.error_info.info2) != 0U) + { + state = ESTATE_CHECK_RESPONSE_COMPLETE; + break; + } + break; + + case ESTATE_CHECK_RESPONSE_COMPLETE: + if (cmd_type >= HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE) + { + state = ESTATE_DATA_TRANSFER; + } else { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } + break; + + case ESTATE_DATA_TRANSFER: + /* ADTC command */ + mmc_drv_obj.during_transfer = TRUE; + mmc_drv_obj.state_machine_blocking = TRUE; + + if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) + { + /* DMA */ + emmc_data_transfer_dma(); + } else { + /* PIO */ + /* interrupt enable (FIFO read/write enable) */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) + { + mem_write32(SD_INFO2_MASK, ( SD_INFO2_BWE | SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + } else { + mem_write32(SD_INFO2_MASK, ( SD_INFO2_BRE | SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + } + } + state = ESTATE_DATA_TRANSFER_COMPLETE; + break; + + case ESTATE_DATA_TRANSFER_COMPLETE: + /* check interrupt */ + if ((mmc_drv_obj.int_event2 & SD_INFO2_ALL_ERR) != 0U) + { + /* error interrupt */ + rtn_code = EMMC_ERR_INFO2; + state = ESTATE_TRANSFER_ERROR; + break; + } else { + /* success. nothing to do. */ + } + + /* DMAC error ? */ + if (mmc_drv_obj.dma_error_flag == TRUE) + { + /* Error occurred in DMAC driver. */ + rtn_code = EMMC_ERR_FROM_DMAC_TRANSFER; + state = ESTATE_TRANSFER_ERROR; + } else if (mmc_drv_obj.during_dma_transfer == TRUE) { + /* DMAC not finished. unknown error */ + rtn_code = EMMC_ERR; + state = ESTATE_TRANSFER_ERROR; + } else { + mem_write32(SD_INFO1_MASK, SD_INFO1_INFO2); + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + + mmc_drv_obj.state_machine_blocking = TRUE; + + state = ESTATE_ACCESS_END; + } + break; + + case ESTATE_ACCESS_END: + + /* clear flag */ + if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) + { + mem_write32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ + mem_write32(SD_STOP, 0x00000000U); + mmc_drv_obj.during_dma_transfer = FALSE; + } + + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, SD_INFO2_CLEAR); + + if ((mmc_drv_obj.int_event1 & SD_INFO1_INFO2) != 0U) + { + emmc_WaitCmd2Cmd_8Cycle(); + state = ESTATE_END; + } else { + state = ESTATE_ERROR; + } + break; + + case ESTATE_TRANSFER_ERROR: + /* The error occurred in the Data transfer. */ + if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) + { + mem_write32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */ + mem_write32(SD_STOP, 0x00000000U); + mmc_drv_obj.during_dma_transfer = FALSE; + } + /* fallthrough */ + + case ESTATE_ERROR: + emmc_softreset(); + ERROR("%s:0x%x\n",__func__,rtn_code); + return rtn_code; + + default: + state = ESTATE_END; + break; + } /* switch (state) */ + } /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */ + + /* force terminate */ + if (mmc_drv_obj.force_terminate == TRUE) + { + /* timeout timer is expired. Or, PIO data transfer error. */ + /* Timeout occurred in the DMA transfer. */ + if (mmc_drv_obj.during_dma_transfer == TRUE) + { + mmc_drv_obj.during_dma_transfer = FALSE; + } + emmc_softreset(); + + return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */ + } + + /* success */ + mmc_drv_obj.during_transfer = FALSE; + + return EMMC_SUCCESS; +} + +/** host controller softrest. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param None. + * return None. + */ +static void emmc_softreset(void) +{ + int32_t loop = 10000; + int32_t retry = 1000; + + /* flag clear */ + mmc_drv_obj.during_transfer = FALSE; + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.state_machine_blocking = FALSE; + mmc_drv_obj.force_terminate = FALSE; + mmc_drv_obj.dma_error_flag = FALSE; + + /* during operation ? */ + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U) + { + /* wait CMDSEQ = 0 */ + while (loop > 0) + { + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) == 0U) + { + break; /* ready */ + } + + loop--; + if ((loop == 0) && (retry > 0)) + { + micro_wait(1000U); /* wait 1ms */ + loop = 10000; + retry--; + } + } + } + + /* reset */ + mem_write32(SOFT_RST, ( mem_read32(SOFT_RST) & (~SOFT_RST_SDRST) )); /* Soft reset */ + mem_write32(SOFT_RST, ( mem_read32(SOFT_RST) | SOFT_RST_SDRST )); /* Soft reset released */ + + /* initialize */ + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, SD_INFO2_CLEAR); + mem_write32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ + +} + +/** read response + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * param[in,out] *response Response from the card + * return None. + */ +static void emmc_read_response(uint32_t *response) +{ + + uint8_t *p = NULL; + + if (response == NULL) + { + return; + } + + /* read response */ + if (mmc_drv_obj.response_length == EMMC_MAX_RESPONSE_LENGTH) + { + /* CSD or CID */ + p = (uint8_t *)(response); + emmc_little_to_big(p, ((mem_read32(SD_RSP76) << 8U) | (mem_read32(SD_RSP54) >> 24U))); /* [127:96] */ + emmc_little_to_big(p + 4U, ((mem_read32(SD_RSP54) << 8U) | (mem_read32(SD_RSP32) >> 24U))); /* [95:64] */ + emmc_little_to_big(p + 8U, ((mem_read32(SD_RSP32) << 8U) | (mem_read32(SD_RSP10) >> 24U))); /* [63:32] */ + emmc_little_to_big(p + 12U, (mem_read32(SD_RSP10) << 8U)); /* [31:0] */ + } else { + *response = mem_read32(SD_RSP10); /* [39:8] */ + } +} + +/** response check + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * param[in] *response Response from the card + * param[in] error_mask Errors to be checked (for R1/R1b response) + * return error code. + */ +static EMMC_ERROR_CODE emmc_response_check(const uint32_t *response, uint32_t error_mask) +{ + + HAL_MEMCARD_RESPONSE_TYPE response_type = (HAL_MEMCARD_RESPONSE_TYPE)(uintptr_t)((uint32_t)(mmc_drv_obj.cmd_info.cmd) + & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK); + + if (response == NULL) + { + return EMMC_ERR_PARAM; + } + + if (response_type == HAL_MEMCARD_RESPONSE_NONE) + { + return EMMC_SUCCESS; + } + + /* response check */ + if (response_type <= HAL_MEMCARD_RESPONSE_R1b) + { + /* R1 or R1b */ + mmc_drv_obj.current_state = (EMMC_R1_STATE)((*response & EMMC_R1_STATE_MASK) >> EMMC_R1_STATE_SHIFT); + if ((*response & error_mask) != 0U) + { + return EMMC_ERR_CARD_STATUS_BIT; + } + } else if (response_type == HAL_MEMCARD_RESPONSE_R4) { + /* R4 */ + if ((*response & EMMC_R4_STATUS) != 0U) + { + return EMMC_ERR_CARD_STATUS_BIT; + } + } else { + ; /* nothing to do. other type does not have status bit */ + } + + return EMMC_SUCCESS; +} + +/** brief converts endian from little to big + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param[in,out] p destination buffer address. + * param[in] value convert data.(little) + * return None. + */ +static void emmc_little_to_big(uint8_t *p, uint32_t value) +{ + if (p == NULL) + { + return; + } + + p[0] = (uint8_t)(value >> 24U); + p[1] = (uint8_t)(value >> 16U); + p[2] = (uint8_t)(value >> 8U); + p[3] = (uint8_t)value; +} + +/** data transfer with DMA. + * + * - Pre-conditions:
+ * Called from emmc_exec_cmd(). + * - Post-conditions:
+ * . + * + * return error code. + */ +static void emmc_data_transfer_dma(void) +{ + mmc_drv_obj.during_dma_transfer = TRUE; + mmc_drv_obj.dma_error_flag = FALSE; + + mem_write32(SD_INFO1_MASK, 0x00000000U); + mem_write32(SD_INFO2_MASK, ( SD_INFO2_ALL_ERR | SD_INFO2_CLEAR )); + + /* DMAC setting */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) + { + /* transfer complete interrupt enable when write to eMMC */ + mem_write32(DM_CM_INFO1_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH0_ENABLE )); + /* When writing to eMMC, set only bit 17 to "0". */ + mem_write32(DM_CM_INFO2_MASK, ( DM_CM_INFO2_MASK_CLEAR | DM_CM_INFO2_CH0_ENABLE )); + /* BUFF --> FIFO */ + mem_write32(DM_CM_DTRAN_MODE, ( DM_CM_DTRAN_MODE_CH0 | DM_CM_DTRAN_MODE_BIT_WIDTH )); /* CH0(downstream), 64-bit width */ + } else { + /* transfer complete interrupt enable when read from eMMC */ + mem_write32(DM_CM_INFO1_MASK, ( DM_CM_INFO_MASK_CLEAR | DM_CM_INFO_CH1_ENABLE )); + /* When reading from eMMC, set only bit 16 to "0". */ + mem_write32(DM_CM_INFO2_MASK, ( DM_CM_INFO2_MASK_CLEAR | DM_CM_INFO2_CH1_ENABLE )); + /* FIFO --> BUFF */ + mem_write32(DM_CM_DTRAN_MODE, ( DM_CM_DTRAN_MODE_CH1 | DM_CM_DTRAN_MODE_BIT_WIDTH )); /* CH1(upstream), 64-bit width */ + } + mem_write32(DM_DTRAN_ADDR, ( ( (uintptr_t)mmc_drv_obj.buff_address_virtual & DM_DTRAN_ADDR_WRITE_MASK ) )); /* Set address */ + + mem_write32(DM_CM_DTRAN_CTRL, DM_CM_DTRAN_CTRL_START); /* DMAC Start */ +} + +/** wait cmd-cmd 8cycle + * + * - Pre-conditions:
+ * + * - Post-conditions:
+ * . + * + * return None. + */ +static void emmc_WaitCmd2Cmd_8Cycle(void) +{ + uint32_t dataL, wait = 0U; + + dataL = mem_read32(SD_CLK_CTRL); + dataL &= 0x000000FFU; + + switch (dataL) + { + case 0xFFU: /* 1/1 10 us wait ( 1/200MHz)*8= 0.04 us(min) */ + wait = 10U; + break; + case 0x00U: /* 1/2 10 us wait ( 2/200MHz)*8= 0.08 us(min) */ + wait = 10U; + break; + case 0x01U: /* 1/4 10 us wait ( 4/200MHz)*8= 0.16 us(min) */ + wait = 10U; + break; + case 0x02U: /* 1/8 10 us wait ( 8/200MHz)*8= 0.32 us(min) */ + wait = 10U; + break; + case 0x04U: /* 1/16 10 us wait ( 16/200MHz)*8= 0.64 us(min) */ + wait = 10U; + break; + case 0x08U: /* 1/32 10 us wait ( 32/200MHz)*8= 1.28 us(min) */ + wait = 10U; + break; + case 0x10U: /* 1/64 10 us wait ( 64/200MHz)*8= 2.56 us(min) */ + wait = 10U; + break; + case 0x20U: /* 1/128 10 us wait (128/200MHz)*8= 5.12 us(min) */ + wait = 10U; + break; + case 0x40U: /* 1/256 20 us wait (256/200MHz)*8= 10.24 us(min) */ + wait = 20U; + break; + case 0x80U: /* 1/512 30 us wait (512/200MHz)*8= 20.48 us(min) */ + wait = 30U; + break; + default: + /* nop */ + break; + } + micro_wait(wait); + +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_init.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_init.c new file mode 100644 index 0000000..55fad8a --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_init.c @@ -0,0 +1,320 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc initialize + ******************************************************************************/ +/****************************************************************************** + * @file emmc_init.c + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 22.03.2022 0.02 Removed CPG setting + * Added Function End comment + * Added header file inclusion + * : 24.10.2022 0.03 Add CPG setting to support HS200/400 + * : 31.10.2022 0.04 License notation change. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "mem_io.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ +st_mmc_base mmc_drv_obj; + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static void emmc_drv_init(void); +static EMMC_ERROR_CODE emmc_dev_init(void); +static EMMC_ERROR_CODE emmc_dev_finalize(void); +static void emmc_memset(void *buff, uint8_t data, uint32_t cnt); +static EMMC_ERROR_CODE emmc_reset_controller(void); +static void emmc_driver_config(void); +static void emmc_set_data_timeout(uint32_t data_timeout); + +/* ********************************* CODE ********************************** */ + +/** brief eMMC initialize. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR error from interrupt API. + */ +EMMC_ERROR_CODE emmc_init(void) +{ + /* initialize H/W */ + (void)emmc_reset_controller(); + + /* Configuration */ + emmc_driver_config(); + + return EMMC_SUCCESS; +} + +/** terminate emmc driver + * + * EMMC H/W and S/W resource is released. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * return None. + */ +EMMC_ERROR_CODE emmc_terminate(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* H/W finalize */ + result = emmc_dev_finalize(); + + /* driver finalize */ + emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base)); /* clear global variable */ + + return result; +} + +/** Function executes full reset to MMC host controller without taking power out from the memory card. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * Reset MMC host controller without taking power out from the memory card. + * Memory card preserves its state. + * + * return None + */ +static EMMC_ERROR_CODE emmc_reset_controller(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* initialize mmc driver */ + emmc_drv_init(); + + mmc_drv_obj.base_address = MMC0_SD_BASE; + + /* initialize H/W */ + result = emmc_dev_init(); + + mmc_drv_obj.initialize = TRUE; + + return result; + +} + +/** Configuration eMMC driver + * + * - Pre-conditions:
+ * initialized eMMC driver. + * - Post-conditions:
+ * . + * + * return None + */ +static void emmc_driver_config(void) +{ + /* Read/Write data timeout */ + emmc_set_data_timeout(EMMC_RW_DATA_TIMEOUT); +} + +/** Sets data timeout + * + * Sets the data timeout value for read and write operations. + * + * - Pre-conditions:
+ * initialized eMMC driver. + * + * - Post-conditions:
+ * After this function is called, the timeout value is set according to argument. + * + * param[in] time_out The desired timeout value in milliseconds. + * return None + */ +static void emmc_set_data_timeout(uint32_t data_timeout) +{ + mmc_drv_obj.data_timeout = data_timeout; +} + +/** eMMC driver initialize. (software) + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * return None. + */ +static void emmc_drv_init(void) +{ + /* initialize */ + emmc_memset((uint8_t *)(&mmc_drv_obj), 0U, sizeof(st_mmc_base)); + + mmc_drv_obj.data_timeout = EMMC_RW_DATA_TIMEOUT; + + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; +} + +/** eMMC driver initialize. (H/W) + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * return None. + */ +static EMMC_ERROR_CODE emmc_dev_init(void) +{ + /* InitSdCkcr */ + mem_write32(CPG_CPGWPR, ~(0x00000001U)); + mem_write32(CPG_SD0CKCR, 0x00000001U); /* SD0H-Clock=800MHz(Supply), SD0=200MHz(Supply) */ + + /* MMCIF initialize */ + mem_write32(SD_INFO1, 0x00000000U); /* all interrupt clear */ + mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* all interrupt clear */ + mem_write32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */ + + mem_write32(HOST_MODE, 0x00000000U); /* SD_BUF access width = 64-bit */ + mem_write32(SD_OPTION, 0x0000C0EEU); /* Bus width = 1bit, timeout=MAX */ + mem_write32(SD_CLK_CTRL, 0x00000000U); /* Automatic Control=Disable, Clock Output=Disable */ + + return EMMC_SUCCESS; +} + +/** EMMC H/W finalize + * + * EMMC Host and Card hardware resource is released. + * + * - Pre-conditions:
+ * . + * + * - Post-conditions:
+ * . + * return None. + */ +static EMMC_ERROR_CODE emmc_dev_finalize(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* MMC power off + * the power supply of eMMC device is always turning on. + * RST_n : Hi --> Low level. + */ + result = emmc_memcard_power(FALSE); + + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, 0x00000800U); + mem_write32(DM_CM_INFO1, 0x00000000U); + mem_write32(DM_CM_INFO2, 0x00000000U); + + mem_write32(SD_CLK_CTRL, 0x00000020U); + mem_write32(CC_EXT_MODE, 0x00000000U); + mem_write32(SD_STOP, 0x00000000U); + mem_write32(SD_SECCNT, 0x00000000U); + mem_write32(DM_CM_DTRAN_MODE, 0x00000000U); + mem_write32(DM_DTRAN_ADDR, 0x00000000U); + mem_write32(SD_OPTION, 0x00000000U); + mem_write32(DM_CM_DTRAN_CTRL, 0x00000000U); + + return result; +} + +/** Set power to memory card IF. + * This function control Vcc and Vccq and RST_n. + * + * attention + * CPU cannot control Vcc&Vccq. + * The power supply of eMMC device is always turning on. + * + * param[in] mode TRUE = power on, FALSE = power off + * + * retval EMMC_SUCCESS powering succeeded + * retval EMMC_ERR_CARD_POWER powering failed + */ +EMMC_ERROR_CODE emmc_memcard_power(uint32_t mode) +{ + if (mode == TRUE) + { + /* power on (Vcc&Vccq is always power on) */ + mmc_drv_obj.card_power_enable = TRUE; + } else { + /* power off (Vcc&Vccq is always power on) */ + mmc_drv_obj.card_power_enable = FALSE; + mmc_drv_obj.mount = FALSE; + mmc_drv_obj.selected = FALSE; + } + + return EMMC_SUCCESS; +} + +/** memset(). no use C standard library. + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param[in,out] buff pointer to buffer (virtual) + * param[in] data fill data. + * param[in] cnt fill size (number of bytes) + * return None. + */ +static void emmc_memset(void *buff, uint8_t data, uint32_t cnt) +{ + uint8_t *tmp = NULL; + tmp = (uint8_t *)buff; + + if (buff == NULL) + { + return; + } + + while (cnt > 0U) + { + *tmp = data; + tmp++; + cnt--; + } +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_interrupt.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_interrupt.c new file mode 100644 index 0000000..48e3beb --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_interrupt.c @@ -0,0 +1,239 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc interrupt + ******************************************************************************/ +/****************************************************************************** + * @file emmc_interrupt.c + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 16.06.2022 0.02 Change log output + * : 31.10.2022 0.03 License notation change. + * : 07.06.2024 0.04 Modify the transfer end bit of DMAC channel. + *****************************************************************************/ + +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "log.h" +#include "mem_io.h" +#include +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual); + + +/* ********************************* CODE ********************************** */ + + + +/** emmc driver interrupt service routine. + * + * - Pre-conditions:
+ * Must be block emmc driver state machine. + * - Post-conditions:
+ * unblocking emmc driver state machine. + * + * retval INT_SUCCESS + */ +uint32_t emmc_interrupt(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* SD_INFO */ + mmc_drv_obj.error_info.info1 = mem_read32(SD_INFO1); + mmc_drv_obj.error_info.info2 = mem_read32(SD_INFO2); + + /* SD_INFO EVENT */ + mmc_drv_obj.int_event1 = mmc_drv_obj.error_info.info1 & mem_read32(SD_INFO1_MASK); + mmc_drv_obj.int_event2 = mmc_drv_obj.error_info.info2 & mem_read32(SD_INFO2_MASK); + + /* ERR_STS */ + mmc_drv_obj.error_info.status1 = mem_read32(SD_ERR_STS1); + mmc_drv_obj.error_info.status2 = mem_read32(SD_ERR_STS2); + + /* DM_CM_INFO */ + mmc_drv_obj.error_info.dm_info1 = mem_read32(DM_CM_INFO1); + mmc_drv_obj.error_info.dm_info2 = mem_read32(DM_CM_INFO2); + + /* DM_CM_INFO EVENT */ + mmc_drv_obj.dm_event1 = mmc_drv_obj.error_info.dm_info1 & mem_read32(DM_CM_INFO1_MASK); + mmc_drv_obj.dm_event2 = mmc_drv_obj.error_info.dm_info2 & mem_read32(DM_CM_INFO2_MASK); + + /* ERR SD_INFO2 */ + if ((SD_INFO2_ALL_ERR & mmc_drv_obj.int_event2) != 0U) + { + mem_write32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */ + mem_write32(SD_INFO1, 0x00000000U); /* interrupt clear */ + mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } + + /* PIO Transfer */ + /* BWE/BRE */ + else if ((( SD_INFO2_BWE | SD_INFO2_BRE) & mmc_drv_obj.int_event2) != 0U) { + /* BWE */ + if (( SD_INFO2_BWE & mmc_drv_obj.int_event2) != 0U) + { + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BWE)); /* interrupt clear */ + } + /* BRE */ + else { + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BRE)); /* interrupt clear */ + } + + result = emmc_trans_sector((uint32_t *)mmc_drv_obj.buff_address_virtual); /* sector R/W */ + mmc_drv_obj.buff_address_virtual += EMMC_BLOCK_LENGTH; + mmc_drv_obj.remain_size -= EMMC_BLOCK_LENGTH; + + if (result != EMMC_SUCCESS) + { + /* data transfer error */ + ERROR("%s:0x%x\n",__func__, result); + + /* Panic */ + mem_write32(SD_INFO1_MASK, 0x00000000U); /* interrupt disable */ + mem_write32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* interrupt disable */ + mem_write32(SD_INFO1, 0x00000000U); /* interrupt clear */ + mem_write32(SD_INFO2, SD_INFO2_CLEAR); /* interrupt clear */ + mmc_drv_obj.force_terminate = TRUE; + } else { + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; + } + + /* DMA_TRANSFER */ + /* DM_CM_INFO1: DMA-ch0 transfer complete or error occured */ + else if ((DM_CM_INFO_DTRANEND0 & mmc_drv_obj.dm_event1) != 0U) { + mem_write32(DM_CM_INFO1, 0x00000000U); + mem_write32(DM_CM_INFO2, 0x00000000U); + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BWE)); /* interrupt clear */ + /* DM_CM_INFO2: DMA-ch0 error occured */ + if (( DM_CM_INFO2_DTRANEND0 & mmc_drv_obj.dm_event2) != 0U) + { + mmc_drv_obj.dma_error_flag = TRUE; + } else { + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; /* wait next interrupt */ + } + /* DM_CM_INFO1: DMA-ch1 transfer complete or error occured */ + else if ((DM_CM_INFO_DTRANEND1 & mmc_drv_obj.dm_event1) != 0U) { + mem_write32(DM_CM_INFO1, 0x00000000U); + mem_write32(DM_CM_INFO2, 0x00000000U); + mem_write32(SD_INFO2, (mem_read32(SD_INFO2) & ~SD_INFO2_BRE)); /* interrupt clear */ + /* DM_CM_INFO2: DMA-ch1 error occured */ + if (( DM_CM_INFO2_DTRANEND1 & mmc_drv_obj.dm_event2) != 0U) + { + mmc_drv_obj.dma_error_flag = TRUE; + } else { + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.during_transfer = FALSE; + } + mmc_drv_obj.state_machine_blocking = FALSE; /* wait next interrupt */ + } + + /* Response end */ + else if ((SD_INFO1_INFO0 & mmc_drv_obj.int_event1) != 0U) { + mem_write32(SD_INFO1, (mem_read32(SD_INFO1) & ~SD_INFO1_INFO0)); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } + /* Access end */ + else if ((SD_INFO1_INFO2 & mmc_drv_obj.int_event1) != 0U) { + mem_write32(SD_INFO1, (mem_read32(SD_INFO1) & ~SD_INFO1_INFO2)); /* interrupt clear */ + mmc_drv_obj.state_machine_blocking = FALSE; + } else { + /* nothing to do. */ + } + + return 0U; +} + +/** Data transfer function with PIO (Single sector). + * + * - Pre-conditions:
+ * Called from interrupt service. + * - Post-conditions:
+ * . + * + * param[in,out] buff_address_virtual Dest/Src buffer address(virtual). + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_PARAM parameter error. + * retval EMMC_ERR_STATE state error. + */ +static EMMC_ERROR_CODE emmc_trans_sector(uint32_t *buff_address_virtual) +{ + uint32_t length, i; + uint64_t *bufPtrLL; + + if (buff_address_virtual == NULL) + { + return EMMC_ERR_PARAM; + } + + if ((mmc_drv_obj.during_transfer != TRUE) || (mmc_drv_obj.remain_size == 0U)) + { + return EMMC_ERR_STATE; + } + + bufPtrLL = (uint64_t*)buff_address_virtual; + length = mmc_drv_obj.remain_size; + + /* data transefer */ + for (i = 0U; i < (length >> 3U); i++) + { + /* Write */ + if (mmc_drv_obj.cmd_info.dir == HAL_MEMCARD_WRITE) + { + mem_write64(SD_BUF0, *bufPtrLL); /* buffer --> FIFO */ + } + /* Read */ + else { + *bufPtrLL = mem_read64(SD_BUF0); /* FIFO --> buffer */ + } + bufPtrLL++; + } + + return EMMC_SUCCESS; +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_mount.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_mount.c new file mode 100644 index 0000000..3784b82 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_mount.c @@ -0,0 +1,1592 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc mount + ******************************************************************************/ +/****************************************************************************** + * @file emmc_mount.c + * - Version : 0.08 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 17.02.2022 0.02 V4H software restrictions + * : 18.03.2022 0.03 Unrestricted V4H software + * : 16.06.2022 0.04 Change log output + * : 24.10.2022 0.05 Support HS200/400 + * : 31.10.2022 0.06 License notation change. + * : 08.12.2022 0.07 Support build option of EMMC_TRANS_MODE + * and add cmd21 function + * : 21.08.2023 0.08 Add support for V4M. +*****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include +#include "timer.h" +#include "log.h" + +#define BIT0 (0x0000000000000001U) +#define BIT1 (0x0000000000000002U) +#define BIT2 (0x0000000000000004U) +#define BIT3 (0x0000000000000008U) +#define BIT4 (0x0000000000000010U) +#define BIT5 (0x0000000000000020U) +#define BIT6 (0x0000000000000040U) +#define BIT8 (0x0000000000000100U) +#define BIT2_0 (BIT2|BIT1|BIT0) +#define BIT3_0 (BIT3|BIT2|BIT1|BIT0) +#define BIT6_0 (BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0) +#define BIT23_16 (0x0000000000FF0000U) + +#define SMPCMP_SUCCESS (0x0U) +#define FAIL (0x0U) +#define SUCCESS (0x1U) +#define FIRST (0x1U) + +#define MMC_CMD21 (0x00001C15U) + +/* for S4 */ +#define PFC_DRVCTRL1_GP1_DM0_MMC_MASK (0x77770000U) +#define PFC_DRVCTRL1_GP1_DM0_MMC_VALUE (0x66660000U) +#define PFC_DRVCTRL2_GP1_DM0_MMC_MASK (0x07777777U) +#define PFC_DRVCTRL2_GP1_DM0_MMC_VALUE (0x06666666U) + +/* for V4H */ +#define PFC_DRVCTRL0_GP3_DM0_MMC_MASK (0x77777777U) +#define PFC_DRVCTRL0_GP3_DM0_MMC_VALUE (0x66666666U) +#define PFC_DRVCTRL1_GP3_DM0_MMC_MASK (0x00000777U) +#define PFC_DRVCTRL1_GP3_DM0_MMC_VALUE (0x00000666U) + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +static EMMC_ERROR_CODE emmc_clock_ctrl(uint32_t mode); +static EMMC_ERROR_CODE emmc_card_init(void); +static EMMC_ERROR_CODE emmc_mode_select(uint32_t *speed_mode); +static EMMC_ERROR_CODE emmc_bus_width(uint32_t width); +static EMMC_ERROR_CODE emmc_power_select(void); +static uint32_t emmc_set_timeout_register_value(uint32_t freq); +static void set_sd_clk(uint32_t clkDiv); +static uint32_t emmc_calc_tran_speed(void); +static EMMC_ERROR_CODE emmc_scc_tuning(void); +static uint8_t emmc_scc_tuningmain(uint32_t tapset); +static EMMC_ERROR_CODE emmc_exec_cmd21(void); +static EMMC_ERROR_CODE emmc_tapset_position_find(uint32_t tapsetNum, const uint8_t result_tuning[], uint32_t *tapset); +static EMMC_ERROR_CODE emmc_data_read(void *buf); +static EMMC_ERROR_CODE emmc_wait_readbuf_enable(void); +static EMMC_ERROR_CODE emmc_wait_readbuf_end(void); +static void pfc_reg_modify_write(uintptr_t addr, uint32_t mask, uint32_t data); +/* ********************************* CODE ********************************** */ + +/** eMMC mount operation. + * + * Sequence is the following. + * 1) Bus initialization (emmc_card_init()) + * 2) Changing the data bus width. (emmc_bus_width()) + * 3) Selecting high speed or HS200 or HS400 mode refering to CARD_TYPE[196]. (emmc_mode_select()) + * 4) Selecting power class. (emmc_power_select()) + * 5) If selected mode is HS200 or HS400, perform timing tuning. (emmc_scc_tuning()) + * 6) If selected mode is HS400, switching to HS400 mode. + * + * - Pre-conditions:
+ * eMMC driver is initialized. The power supply of MMC IF must be turning on. + * - Post-conditions:
+ * MMC card state changes to transfer state. + * + * return eMMC error code. + */ +EMMC_ERROR_CODE emmc_mount(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t speed_mode; + + /* Frequency initialization setting */ + mmc_drv_obj.set_freq = MMC_400KHZ; + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || (mmc_drv_obj.card_power_enable != TRUE) + || ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U)) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* initialize card (IDLE state --> Transfer state) */ + result = emmc_card_init(); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + (void)emmc_clock_ctrl(FALSE); + return result; + } + + /* Changing the data bus width */ + result = emmc_bus_width(8U); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + (void)emmc_clock_ctrl(FALSE); + return result; + } + + /* Selecting Power class */ + result = emmc_power_select(); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + (void)emmc_clock_ctrl(FALSE); + return result; + } + + /* Switching HS400 or HS200 or High speed mode */ + result = emmc_mode_select(&speed_mode); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + (void)emmc_clock_ctrl(FALSE); + return result; + } + + switch (speed_mode) + { + case TIMING_HS400: + NOTICE("eMMC Transfer mode: HS400\n"); + break; + case TIMING_HS200: + NOTICE("eMMC Transfer mode: HS200\n"); + break; + case TIMING_HIGH_SPEED: + NOTICE("eMMC Transfer mode: High Speed\n"); + break; + default: + NOTICE("eMMC Transfer mode: No High Speed\n"); + break; + } + + /* Tuning for HS200 and HS400 */ + if ((speed_mode==TIMING_HS200) || (speed_mode==TIMING_HS400)) + { + /* EnableSccHs200Mmc */ + mem_write32(SCC_DTCNTL, 0x00080001U); /* TAPNUM=8, TAPEN=1 */ + mem_write32(SCC_CKSEL, 0x00000001U); /* DTSEL=1 */ + mem_write32(SCC_TMPPORT2, 0x00000000U); + + /* Timing Tuning for HS200/HS400 */ + result = emmc_scc_tuning(); + if(result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + } else { + /* DisableSccMmc */ + mem_write32(SCC_DTCNTL, 0x00080000U); /* TAPNUM=8, TAPEN=0 */ + mem_write32(SCC_CKSEL, 0x00000000U); /* DTSEL=0 */ + mem_write32(SCC_TMPPORT2, 0x00000000U); + } + + /* Setting for HS400 */ + if (speed_mode==TIMING_HS400) + { + /*Set the SoC's driver strength for HS400 mode */ +#if (RCAR_LSI == RCAR_S4) + /* DRVCTRL1_1[30:28][26:24][22:20][18:16]/ = D2, D1, D0, CLK */ + pfc_reg_modify_write(PFC_DRVCTRL1_GP1_DM0, PFC_DRVCTRL1_GP1_DM0_MMC_MASK, PFC_DRVCTRL1_GP1_DM0_MMC_VALUE); + /* DRVCTRL2_1[26:24][22:20][18:16][14:12][10:8][6:4][2:1]/ = CMD, D7, DS, D6, D4, D5, D3 */ + pfc_reg_modify_write(PFC_DRVCTRL2_GP1_DM0, PFC_DRVCTRL2_GP1_DM0_MMC_MASK, PFC_DRVCTRL2_GP1_DM0_MMC_VALUE); +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + /* DRVCTRL0_3[30:28][26:24][22:20][18:16][14:12][10:8][6:4][2:1]/ = D4, D5, D3, DS, CLK, D2, D0, D1 */ + pfc_reg_modify_write(PFC_DRVCTRL0_GP3_DM0, PFC_DRVCTRL0_GP3_DM0_MMC_MASK, PFC_DRVCTRL0_GP3_DM0_MMC_VALUE); + /* DRVCTRL1_3[10:8][6:4][2:0] = CMD, D6, D7 */ + pfc_reg_modify_write(PFC_DRVCTRL1_GP3_DM0, PFC_DRVCTRL1_GP3_DM0_MMC_MASK, PFC_DRVCTRL1_GP3_DM0_MMC_VALUE); +#endif + + /* EnableHs400Mmc*/ + mem_write32(SDIF_MODE, 0x00000001U); + + /* Set HS_TIMING to 0x01 (High Speed) */ + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* Host changes frequency to <= 52MHz */ + mmc_drv_obj.set_freq = MMC_52MHZ; + result = emmc_set_request_mmc_clock(&mmc_drv_obj.set_freq); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* Set the bus width to DDR 8bit (CMD6) */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_BUS_WIDTH_8_DDR); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* Set the bus width to 8bit for SD card access control option register */ + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_WIDTH|SD_OPTION_WIDTH8)) | SD_OPTION_WIDTH8 )); + + /* Set HS_TIMING to 0x03 (HS400) */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS400); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK_WITHOUT_CRC, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n", __func__); + panic; + } + + /* InitSdCkcrForHS400 */ + mem_write32(CPG_CPGWPR, ~(0x00000001U)); + mem_write32(CPG_SD0CKCR, 0x00000001U); /* SD0H-Clock=800MHz(Supply), SD0=200MHz(Supply) */ + + /* Host changes frequency to 200MHz */ + mmc_drv_obj.max_freq = HS400_200MHZ; + mmc_drv_obj.set_freq = mmc_drv_obj.max_freq; + result = emmc_set_request_mmc_clock(&mmc_drv_obj.set_freq); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* EnableSccHs400Mmc */ + mem_write32(SCC_DTCNTL, 0x00040001U); /* TAPNUM=4, TAPEN=1 */ + mem_write32(SCC_CKSEL, 0x00000001U); /* DTSEL=1 */ + mem_write32(SCC_TMPPORT2, 0x80000010U); /* HS400EN=1, HS400OSEL=1 (use SDxH clock) */ + } + + /* mount complete */ + mmc_drv_obj.mount = TRUE; + + return EMMC_SUCCESS; +} + +/** Bus initialization function + * + * - Pre-conditions:
+ * eMMC driver is initialized. The power supply of MMC IF must be turning on. + * - Post-conditions:
+ * MMC card state changes to transfer state. + * + * retval EMMC_SUCCESS successful. + * return eMMC error code. + * attention upper layer must be check pre-conditions. + */ +static EMMC_ERROR_CODE emmc_card_init(void) +{ + int32_t retry; + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t resultCalc = 0U; + mmc_drv_obj.set_freq = MMC_400KHZ; /* 390KHz */ + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || (mmc_drv_obj.card_power_enable != TRUE) + || ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U)) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* clock on (force change) */ + mmc_drv_obj.current_freq = 0U; + mmc_drv_obj.max_freq = MMC_20MHZ; /* MMC_20MHZ = MMC_12MHZ = 12.187MHz */ + result = emmc_set_request_mmc_clock(&mmc_drv_obj.set_freq); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return EMMC_ERR; + } + + micro_wait(1000U); /* wait 1ms */ + + /* CMD0, arg=0x00000000 */ + result = emmc_send_idle_cmd (0x00000000U); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + micro_wait(200U); /* wait 74clock 390kHz(189.74us)*/ + + /* CMD1 */ + emmc_make_nontrans_cmd(CMD1_SEND_OP_COND, EMMC_HOST_OCR_VALUE); + for (retry = 300; retry > 0; retry--) + { + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + if ((mmc_drv_obj.r3_ocr & EMMC_OCR_STATUS_BIT) != 0U) + { + break; /* card is ready. exit loop */ + } + micro_wait(1000U); /* wait 1ms */ + } + + if (retry == 0) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_TIMEOUT); + return EMMC_ERR_TIMEOUT; + } + + if ((mmc_drv_obj.r3_ocr & EMMC_OCR_ACCESS_MODE_MASK) != EMMC_OCR_ACCESS_MODE_SECT) + { + /* unknown value */ + ERROR("%s:0x%x\n",__func__,EMMC_ERR); + return EMMC_ERR; + } + + /* CMD2 */ + emmc_make_nontrans_cmd(CMD2_ALL_SEND_CID_MMC, 0x00000000U); + mmc_drv_obj.response = (uint32_t *)(&mmc_drv_obj.cid_data[0U]); /* use CID special buffer */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* CMD3 */ + emmc_make_nontrans_cmd(CMD3_SET_RELATIVE_ADDR, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* CMD9 : CSD */ + emmc_make_nontrans_cmd(CMD9_SEND_CSD, EMMC_RCA << 16U); + mmc_drv_obj.response = (uint32_t *)(&mmc_drv_obj.csd_data[0U]); /* use CSD special buffer */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* card version check */ + if (EMMC_CSD_SPEC_VARS() < 4U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_ILLEGAL_CARD); + return EMMC_ERR_ILLEGAL_CARD; + } + + /* CMD7 (select card) */ + emmc_make_nontrans_cmd(CMD7_SELECT_CARD, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + mmc_drv_obj.selected = TRUE; + + /* card speed check */ + resultCalc = emmc_calc_tran_speed(); /* Card spec is calculated from TRAN_SPEED(CSD). */ + if (resultCalc == 0U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_ILLEGAL_CARD); + return EMMC_ERR_ILLEGAL_CARD; + } + mmc_drv_obj.max_freq = mmc_drv_obj.set_freq; /* max frequency (card spec) */ + + result = emmc_set_request_mmc_clock(&mmc_drv_obj.set_freq); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return EMMC_ERR; + } + + /* set read/write timeout */ + mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(mmc_drv_obj.set_freq); + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) | mmc_drv_obj.data_timeout)); + + /* SET_BLOCKLEN:512byte */ + /* CMD16 */ + emmc_make_nontrans_cmd(CMD16_SET_BLOCKLEN, EMMC_BLOCK_LENGTH); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + return result; + } + + /* Transfer Data Length */ + mem_write32(SD_SIZE, EMMC_BLOCK_LENGTH); + + /* CMD8 : EXT_CSD */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0U]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + /* CMD12 is not send. + * If BUS initialization is failed, user must be execute Bus initialization again. + * Bus initialization is start CMD0(soft reset command). + */ + ERROR("%s\n",__func__); + return result; + } + + return EMMC_SUCCESS; +} + +/** Switching to high-speed or HS200/HS400 mode + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * EXT_CSD data must be stored in mmc_drv_obj.ext_csd_data[]. + * + * - Post-conditions:
+ * Change the clock frequency to 26MHz or 52MHz or 200MHz. + * + * retval EMMC_SUCCESS successful or aleady switching. + * retval EMMC_ERR_STATE state error. + * retval EMMC_ERR unknown error. + * return emmc error code. + */ +static EMMC_ERROR_CODE emmc_mode_select(uint32_t *speed_mode) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + +#if ((EMMC_TRANS_MODE == HS400) || (EMMC_TRANS_MODE == HS200) || (EMMC_TRANS_MODE == HIGH_SPEED)) + uint8_t cardType; + cardType = (uint8_t)mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_CARD_TYPE]; +#endif + + /* state check */ + if (mmc_drv_obj.selected != TRUE) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + panic; + } + + #if (EMMC_TRANS_MODE == HS400) + if ((cardType & EMMC_EXT_CSD_CARD_TYPE_400MHZ) != 0U) + { + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS200); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + panic; + } + + *speed_mode = TIMING_HS400; + mmc_drv_obj.max_freq = MMC_200MHZ; + } else { + ERROR("HS400 is not supported."); + panic; + } + #elif (EMMC_TRANS_MODE == HS200) + if ((cardType & EMMC_EXT_CSD_CARD_TYPE_200MHZ) != 0U) + { + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS200); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + panic; + } + + *speed_mode = TIMING_HS200; + mmc_drv_obj.max_freq = MMC_200MHZ; + } else { + ERROR("HS200 is not supported."); + panic; + } + #elif (EMMC_TRANS_MODE == HIGH_SPEED) + if ((cardType & EMMC_EXT_CSD_CARD_TYPE_52MHZ) != 0U) + { + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + panic; + } + + *speed_mode = TIMING_HIGH_SPEED; + mmc_drv_obj.max_freq = MMC_52MHZ; + } else if ((cardType & EMMC_EXT_CSD_CARD_TYPE_26MHZ) != 0U) { + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + panic; + } + + *speed_mode = TIMING_HIGH_SPEED; + mmc_drv_obj.max_freq = MMC_26MHZ; + } else { + ERROR("High Speed is not supported."); + panic; + } + #elif (EMMC_TRANS_MODE == NO_HIGH_SPEED) + *speed_mode = TIMING_HIGH_SPEED_OFF; + mmc_drv_obj.max_freq = MMC_20MHZ; + #endif /* EMMC_TRANS_MODE == HS400 */ + +#if ((EMMC_TRANS_MODE == HS400) || (EMMC_TRANS_MODE == HS200)) + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK_WITHOUT_CRC, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + panic; + } +#endif /* ((EMMC_TRANS_MODE == HS400) || (EMMC_TRANS_MODE == HS200)) */ + + /* set mmc clock */ + mmc_drv_obj.set_freq = mmc_drv_obj.max_freq; + result = emmc_set_request_mmc_clock(&mmc_drv_obj.set_freq); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + panic; + } + + /* set read/write timeout */ + mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(mmc_drv_obj.set_freq); + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_TIMEOUT_CNT_MASK)) | mmc_drv_obj.data_timeout)); + + return result; +} + +/** Changing the data bus width + * + * if chinging the data bus width failed, card is reset by CMD0. + * Please do Bus initialization over again. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * + * - Post-conditions:
+ * Change the data bus width to 8bit or 4bit. + * mmc_drv_obj.ext_csd_data is updated. + * + * param[in] width bus width (8 or 4) + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_PARAM parameter error + * retval EMMC_ERR_STATE state error. + * + */ +static EMMC_ERROR_CODE emmc_bus_width(uint32_t width) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* parameter check */ + if ((width != 8U) && (width != 4U) && (width != 1U)) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.selected != TRUE) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH)(width >> 2U); /* 2 = 8bit, 1 = 4bit, 0 =1bit */ + + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, ( EMMC_SWITCH_BUS_WIDTH_1 | ((uint32_t)(mmc_drv_obj.bus_width) << 8U))); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + /* occurred error */ + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; + goto EXIT; + } + + switch (mmc_drv_obj.bus_width) + { + case HAL_MEMCARD_DATA_WIDTH_1_BIT: + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_WIDTH|SD_OPTION_WIDTH8)) | SD_OPTION_WIDTH )); + break; + case HAL_MEMCARD_DATA_WIDTH_4_BIT: + mem_write32(SD_OPTION, (mem_read32(SD_OPTION) & ~(SD_OPTION_WIDTH|SD_OPTION_WIDTH8))); + break; + case HAL_MEMCARD_DATA_WIDTH_8_BIT: + default: + mem_write32(SD_OPTION, ((mem_read32(SD_OPTION) & ~(SD_OPTION_WIDTH|SD_OPTION_WIDTH8)) | SD_OPTION_WIDTH8 )); + break; + } + + /* CMD8 : EXT_CSD */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0U]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + goto EXIT; + } + + return EMMC_SUCCESS; + +EXIT: + ERROR("%s:0x%x\n",__func__,result); + return result; +} + +/** Switching to power class according to speed mode + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * EXT_CSD data must be stored in mmc_drv_obj.ext_csd_data[]. + * + * - Post-conditions:
+ * Change the power class according to each speed mode. + * + * param[in] speed mode (TIMING_HIGH_SPEED_MODE(0x0) or TIMING_HIGH_SPEED(0x1) or TIMING_HS200(0x2) or TIMING_HS400(0x3)) + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_PARAM parameter error + * retval EMMC_ERR_STATE state error. + * + */ +static EMMC_ERROR_CODE emmc_power_select(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t powerClass; + + powerClass = (uint8_t)mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_PWR_CL_DDR_200_360]; /* 200MHz, DDR, VCC=3.6V */ + + /* read value [7:4]=8bit bus, [3:0]=4bit bus */ + powerClass = (powerClass & 0xF0U) >> 4U; /* 8bit */ + powerClass = (EXTCSD_ACCESS_BYTE|POW_CLASS_ADD|(powerClass << 8U)); + + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, powerClass); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + } + + return result; +} + +/** select access partition + * + * This function write the EXT_CSD register(PARTITION_ACCESS: PARTITION_CONFIG[2:0]). + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * selected partition can access. + * + * param[in] id user selects partitions to access. + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_STATE state error. + * retval EMMC_ERR_PARAM parameter error. + * return emmc error code. + */ +EMMC_ERROR_CODE emmc_select_partition(EMMC_PARTITION_ID id) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t partition; + uint32_t partition_config; + + /* state check */ + if (mmc_drv_obj.mount != TRUE) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* id has PARTITION_ACCESS(Bit[2:0]) */ + if ((uint32_t)((uint32_t)id & ~(uint32_t)PARTITION_ID_MASK) != 0U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* EXT_CSD[179] value */ + partition_config = (uint32_t)mmc_drv_obj.ext_csd_data[EMMC_EXT_CSD_PARTITION_CONFIG]; + if ((partition_config & (uint32_t)PARTITION_ID_MASK) == (uint32_t)id) + { + result = EMMC_SUCCESS; + } else { + + partition_config = ((partition_config & (~(uint32_t)PARTITION_ID_MASK)) | (uint32_t)id); + partition = EMMC_SWITCH_PARTITION_CONFIG | (partition_config << 8U); + + result = emmc_set_ext_csd(partition); + } + + return result; +} + +/** set EXT CSD data + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * mmc_drv_obj.ext_csd_data[] is updated. + * + * param[in] arg argument of CMD6 + * return emmc error code. + */ +EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* CMD6 */ + emmc_make_nontrans_cmd(CMD6_SWITCH, arg); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + + /* CMD8 : EXT_CSD */ + emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000, (uint32_t *)(&mmc_drv_obj.ext_csd_data[0U]), + EMMC_MAX_EXT_CSD_LENGTH, HAL_MEMCARD_READ, HAL_MEMCARD_NOT_DMA); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + return EMMC_SUCCESS; +} + +/** set request MMC clock frequency. + * + * Function returns EMMC_SUCCESS if clock is already running in the desired frequency. + * EMMC_ERR is returned if the HW doesn't support requested clock frequency. + * If matching frequence cannot be set the closest frequence below should be selected. + * For example if 50MHz is requested, but HW supports only 48MHz then 48MHz should be returned in the freq parameter. + * + * - Pre-conditions:
+ * initialized eMMC driver with emmc_init(). + * Memory card and MMCSDIO host controller needs to be powered up beforehand. + * + * - Post-conditions:
+ * Desired clock frequency is set to memory card IF. + * + * param[in] freq frequency [Hz] + * retval EMMC_SUCCESS successful. + * retval EMMC_ERR_STATE state error. + * retval EMMC_ERR busy + */ +EMMC_ERROR_CODE emmc_set_request_mmc_clock(const uint32_t *freq) +{ + /* parameter check */ + if (freq == NULL) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if ((mmc_drv_obj.initialize != TRUE) || (mmc_drv_obj.card_power_enable != TRUE)) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* clock is already running in the desired frequency. */ + if ((mmc_drv_obj.clock_enable == TRUE) && (mmc_drv_obj.current_freq == *freq)) + { + return EMMC_SUCCESS; + } + + /* busy check */ + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR; + } + + set_sd_clk(*freq); + mmc_drv_obj.clock_enable = FALSE; + + return emmc_clock_ctrl(TRUE); /* clock on */ +} + +/** set sd clock. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * set mmc clock. + * + * param[in] clkDiv request freq + * return None. + */ +static void set_sd_clk(uint32_t clkDiv) +{ + uint32_t dataL; + + dataL = (mem_read32(SD_CLK_CTRL) & (~SD_CLK_CTRL_CLKDIV_MASK)); + + switch (clkDiv) + { + case 1U: /* 1/1 */ + dataL |= 0x000000FFU; + break; + case 2U: /* 1/2 */ + dataL |= 0x00000000U; + break; + case 4U: /* 1/4 */ + dataL |= 0x00000001U; + break; + case 8U: /* 1/8 */ + dataL |= 0x00000002U; + break; + case 16U: /* 1/16 */ + dataL |= 0x00000004U; + break; + case 32U:/* 1/32 */ + dataL |= 0x00000008U; + break; + case 64U:/* 1/64 */ + dataL |= 0x00000010U; + break; + case 128U:/* 1/128 */ + dataL |= 0x00000020U; + break; + case 256U: /* 1/256 */ + dataL |= 0x00000040U; + break; + case 512U:/* 1/512 */ + dataL |= 0x00000080U; + break; + default: + /* nop */ + break; + } + + mem_write32(SD_CLK_CTRL, dataL); + mmc_drv_obj.current_freq = (uint32_t)clkDiv; +} + + +/** Enable/Disable MMC clock + * + * - Pre-conditions:
+ * Before enabling the clock for the first time the desired clock frequency must be set with + * emmc_set_clock_freq(). + * Berore setting mmc_drv_obj.data_timeout with emmc_set_data_timeout(). + * + * - Post-conditions:
+ * After this function is called, clock to memory card IF is on/off. + * + * param[in] mode TRUE = clock on, FALSE = clock off + * retval EMMC_SUCCESS succeeded + * retval EMMC_ERR Busy + */ +static EMMC_ERROR_CODE emmc_clock_ctrl(uint32_t mode) +{ + uint32_t value; + + /* busy check */ + if ((mem_read32(SD_INFO2) & SD_INFO2_CBSY) != 0U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR; + } + + if (mode == TRUE) + { + /* clock ON */ + value = ((mem_read32(SD_CLK_CTRL) | MMC_SD_CLK_START) & SD_CLK_WRITE_MASK); + mem_write32(SD_CLK_CTRL, value); /* on */ + mmc_drv_obj.clock_enable = TRUE; + } else { + /* clock OFF */ + value = ((mem_read32(SD_CLK_CTRL) & MMC_SD_CLK_STOP) & SD_CLK_WRITE_MASK); + mem_write32(SD_CLK_CTRL, value); /* off */ + mmc_drv_obj.clock_enable = FALSE; + } + + return EMMC_SUCCESS; +} + +/** Calculate Card support frequency. + * TRAN_SPEED defines the clock frequency when not in high speed mode. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * None. + * return Frquency[Hz] + */ +static uint32_t emmc_calc_tran_speed(void) +{ + const uint32_t unit[8U] = {10000U, 100000U, 1000000U, 10000000U, 0U, 0U, 0U, 0U}; /**< frequency unit (1/10) */ + const uint32_t mult[16U] = {0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, 35U, 40U, 45U, 52U, 55U, 60U, 70U, 80U}; /**< multiple factor (x10) */ + uint32_t maxFreq = 0U; + uint32_t result = 0U; + uint32_t tran_speed = EMMC_CSD_TRAN_SPEED(); + + /* tran_speed = 0x32 + * unit[tran_speed&0x7] = uint[0x2] = 1000000 + * mult[(tran_speed&0x78)>>3] = mult[0x30>>3] = mult[6] = 26 + * 1000000 * 26 = 26000000 (26MHz) + */ + + maxFreq = unit[tran_speed & EMMC_TRANSPEED_FREQ_UNIT_MASK] + * mult[(tran_speed & EMMC_TRANSPEED_MULT_MASK) >> EMMC_TRANSPEED_MULT_SHIFT]; + + if (maxFreq == 0U) + { + result = 0U; + } else if ( MMC_FREQ_52MHZ <= maxFreq) { + mmc_drv_obj.set_freq = MMC_52MHZ; + result = 1U; + } else if ( MMC_FREQ_26MHZ <= maxFreq) { + mmc_drv_obj.set_freq = MMC_26MHZ; + result = 1U; + } else if ( MMC_FREQ_20MHZ <= maxFreq) { + mmc_drv_obj.set_freq = MMC_20MHZ; + result = 1U; + } else { + mmc_drv_obj.set_freq = MMC_400KHZ; + result = 1U; + } + + return result; +} + +/** Calculate read/write timeout. + * + * - Pre-conditions:
+ * CSD data must be stored in mmc_drv_obj.csd_data[]. + * + * - Post-conditions:
+ * set mmc clock. + * + * param[in] freq Base clock Div + * return SD_OPTION Timeout Counter + */ +static uint32_t emmc_set_timeout_register_value(uint32_t freq) +{ + uint32_t timeoutCnt = 0U; /* SD_OPTION - Timeout Counter */ + + switch (freq) + { + case 1U:/* SDCLK * 2^27 */ + timeoutCnt = 0xE0U; + break; + case 2U:/* SDCLK * 2^27 */ + timeoutCnt = 0xE0U; + break; + case 4U:/* SDCLK * 2^26 */ + timeoutCnt = 0xD0U; + break; + case 8U:/* SDCLK * 2^25 */ + timeoutCnt = 0xC0U; + break; + case 16U:/* SDCLK * 2^24 */ + timeoutCnt = 0xB0U; + break; + case 32U:/* SDCLK * 2^23 */ + timeoutCnt = 0xA0U; + break; + case 64U:/* SDCLK * 2^22 */ + timeoutCnt = 0x90U; + break; + case 128U:/* SDCLK * 2^21 */ + timeoutCnt = 0x80U; + break; + case 256U:/* SDCLK * 2^20 */ + timeoutCnt = 0x70U; + break; + case 512U:/* SDCLK * 2^19 */ + timeoutCnt = 0x60U; + break; + default: + /* nop */ + break; + } + + return timeoutCnt; +} + +/** Excecute tuning process and find optimal sampling clock position. + * + * Excecute tuning process in emmc_scc_tuningmain() and + * find optimal sampling clock position in emmc_tapset_position_find. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * None. + * + * return emmc error code. + */ +static EMMC_ERROR_CODE emmc_scc_tuning(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t i; + uint8_t result_tuning[8]; + uint32_t smpcmp[8]; + uint32_t dataL; + uint32_t tapset; + uint32_t allPass; + uint32_t tapsetNum; + + /* Hardware Adjustment Register */ + mem_write32(SCC_DT2FF, 0x00000300U); /* fixed value */ + + dataL = mem_read32(SCC_DTCNTL); + tapsetNum = (dataL & BIT23_16) >> 16U; + + /* CRC16(for Data) Disable */ + mem_write32(SDIF_MODE, (mem_read32(SDIF_MODE) | BIT8)); + + allPass = TRUE; /* allPass flag */ + for (i = 0; i < tapsetNum; i++) + { + result_tuning[i] = emmc_scc_tuningmain(i); + smpcmp[i] = mem_read32(SCC_SMPCMP); + + if( result_tuning[i] != TUNING_SUCCESS ) + { + result_tuning[i] = FAIL; + allPass = FALSE; /* if fail : clear allPass flag */ + } + } + + /* Detecting a change point of the input data + SCC_SMPCMP[24:16] : CMPNGU = There is a change point of data just before TAP-CLK. + SCC_SMPCMP[8:0] : CMPNGD = There is a change point of data just after TAP-CLK. + If "result_tuning[i]" is all pass, confirm SCC_SMPCMP and avoid setting value close to change point */ + if (allPass == TRUE) + { + for (i = 0; i < tapsetNum; i++) + { + if(smpcmp[i] == SMPCMP_SUCCESS) + { + result_tuning[i] = SUCCESS; /* result=Pass */ + } else { + result_tuning[i] = FAIL; /* result=Fail */ + } + } + } + + /* CRC16(for Data) Enable */ + mem_write32(SDIF_MODE, (mem_read32(SDIF_MODE) & ~BIT8)); + + /* Int flag clear */ + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, 0x00000000U); + + result = emmc_tapset_position_find(tapsetNum, result_tuning, &tapset); + if (result != EMMC_SUCCESS) + { + ERROR("%s:0x%x\n",__func__,RCAR_ERR); + panic; + } + + mem_write32(SCC_TAPSET, tapset); + + /* SET_BLOCKLEN */ + /* CMD16 */ + emmc_make_nontrans_cmd(CMD16_SET_BLOCKLEN, 512); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + ERROR("%s\n",__func__); + panic; + } + + /* Transfer Data Length */ + mem_write32(SD_SIZE, 512U); + + return result; +} + +/** Excecute tuning process. + * + * Set sampling clock position 'tapset'(0-7) and + * Excecute tuninng process by CMD21. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * None. + * + * param[in] tapset number 0-7 + * retval TUNING_SUCCESS successful + * retval EMMC_TUNING_FAIL error from eMMC + * retval RCAR_TUNING_FAIL error from R-car + * return result of tuning + */ +static uint8_t emmc_scc_tuningmain(uint32_t tapset) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint8_t result_tuning = TUNING_SUCCESS; + uint64_t i; + uint32_t dataL; + uint32_t sd_info2; + uint8_t tuningBuf[128] __attribute__ ((aligned (8))); /* 1024bit (64bit alignment) */ + + const uint32_t eMmcTuningBlockPattern[32]={ + 0xFF00FFFFU, 0x0000FFFFU, 0xCCCCFFFFU, 0xCCCC33CCU, + 0xCC3333CCU, 0xFFFFCCCCU, 0xFFFFEEFFU, 0xFFEEEEFFU, + 0xFFDDFFFFU, 0xDDDDFFFFU, 0xBBFFFFFFU, 0xBBFFFFFFU, + 0xFFFFFFBBU, 0xFFFFFF77U, 0x77FF7777U, 0xFFEEDDBBU, + 0x00FFFFFFU, 0x00FFFFFFU, 0xCCFFFF00U, 0xCC33CCCCU, + 0x3333CCCCU, 0xFFCCCCCCU, 0xFFEEFFFFU, 0xEEEEFFFFU, + 0xDDFFFFFFU, 0xDDFFFFFFU, 0xFFFFFFDDU, 0xFFFFFFBBU, + 0xFFFFBBBBU, 0xFFFF77FFU, 0xFF7777FFU, 0xEEDDBB77U, + }; + + /* SCC_TAPSET : Sampling Clock Position */ + mem_write32(SCC_TAPSET, tapset); + + /* Clear flags */ + mem_write32(SD_INFO1, 0x00000000U); + mem_write32(SD_INFO2, 0x00000000U); + + /* The data length of the tuning block is fixed. The BLOCKLEN command is unnecessary */ + + /* Transfer Data Length */ + mem_write32(SD_SIZE, 128); + + /* Block Count Disable */ + mem_write32(SD_STOP, 0x00000000U); + + /* MMC_CMD21:SEND_TUNING_BLOCK */ + /* CMD21 */ + result = emmc_exec_cmd21(); + if (result != EMMC_SUCCESS) + { + result_tuning = EMMC_TUNING_FAIL; + goto EXIT; + } + + /* Check Error */ + /* BIT2: END error (Communications Errors) */ + /* BIT1: CRC error (Communications Errors) */ + /* BIT0: CMD error (Communications Errors) */ + sd_info2 = mem_read32(SD_INFO2); + if ((BIT2_0 & sd_info2) != 0U) + { + result_tuning = RCAR_TUNING_FAIL; + goto EXIT; + } + + result = emmc_data_read((void*)tuningBuf); + if (result != EMMC_SUCCESS) + { + result_tuning = RCAR_TUNING_FAIL; + goto EXIT; + } + + /* Check Error */ + /* BIT3: Data timeout(other than response timeout) (Timeouts) */ + /* BIT2: END error (Communications Errors) */ + /* BIT1: CRC error (Communications Errors) */ + /* BIT0: CMD error (Communications Errors) */ + sd_info2 = mem_read32(SD_INFO2); + if ((BIT3_0 & sd_info2) != 0U) + { + result_tuning = RCAR_TUNING_FAIL; + goto EXIT; + } else { + /* Tuning Data Verify */ + for (i = 0; i < (128U>>2U); i++) + { + dataL = mem_read32((uintptr_t)tuningBuf + (uintptr_t)(i<<2U)); + if(dataL != eMmcTuningBlockPattern[i]) + { + result_tuning = RCAR_TUNING_FAIL; + goto EXIT; + } + } + } + + goto EXIT; + +EXIT: + return result_tuning; +} + +/** Send CMD21(SEND_TUNING_BLOCK) to eMMC. + * + * Send CMD21 to eMMC and check error using SD_INFO1,2. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * None. + * + * return result(EMMC_SUCCESS or RCAR_ERR). + */ +static EMMC_ERROR_CODE emmc_exec_cmd21(void) +{ + EMMC_ERROR_CODE result = RCAR_ERR; + uint32_t loop = 1U; + uint32_t sd_info1; + uint32_t sd_info2; + + mem_write32(SD_ARG, 0); + mem_write32(SD_CMD, MMC_CMD21); + + while(loop == 1U) + { + sd_info1 = mem_read32(SD_INFO1); + if(((sd_info1 & BIT0)) == 1U) /* INFO0 = 1 (Response End) */ + { + mem_write32(SD_INFO1, 0x0000FFFE); /* clear BIT0 */ + result = EMMC_SUCCESS; + loop = 0U; + } + + sd_info2 = mem_read32(SD_INFO2); + if ((BIT6_0 & sd_info2) != 0U) + { + result = RCAR_ERR; + break; + } + } + + return result; +} + +/** Find optimal sampling clock position. + * + * Based on the 'tapsetNum' number of result_tuning, + * Choose optimal sampling clock position and store it in tapset. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * None. + * + * param[in] total number of tapset: 0-7 + * result[] of tuning: 0 or 1 + * pointer to tapset + * retval EMMC_SUCCESS successful + * retval RCAR_ERR the number of tuning failure is smaller than 3 + * return emmc error code. + */ +static EMMC_ERROR_CODE emmc_tapset_position_find(uint32_t tapsetNum, const uint8_t result_tuning[], uint32_t *tapset) +{ + EMMC_ERROR_CODE result = EMMC_SUCCESS; + uint8_t tbl[8*2U] = {}; + uint32_t i; + uint32_t maxCount; + uint32_t maxPassPos; + uint32_t nowCount; + uint32_t passPos; + + /* tbl <- result_tuning */ + if ((tapsetNum >= 1U) && (tapsetNum <= 8U)) + { + for (i = 0; i < tapsetNum; i++) + { + tbl[i] = result_tuning[i]; + tbl[i+tapsetNum] = result_tuning[i]; + } + } else { + ERROR("invalid tapsetNum\n"); + panic; + } + + /* Search */ + maxCount = 0; + maxPassPos = 0; + nowCount = 0; + passPos = 0; + for (i = 0; i < (tapsetNum*2U); i++) + { + if (tbl[i] == SUCCESS) + { + nowCount++; + if (nowCount == FIRST) + { + passPos = i; + } + if (nowCount >= tapsetNum) + { + maxCount = tapsetNum; + maxPassPos = 0; + break; + } + } else { + if (nowCount != 0U) + { + if (maxCount < nowCount) + { + maxCount = nowCount; + maxPassPos = passPos; + } + } + nowCount = 0; + passPos = 0; + } + } + + /* Check 3 or more */ + if (maxCount < 3U) + { + *tapset = 0; + result = RCAR_ERR; /* Error End */ + } + + /* Set value select */ + if (maxCount == tapsetNum) + { + *tapset = 0; /* All pass : Default value = 0 */ + } else { + *tapset = maxPassPos+(maxCount>>1); + } + if (*tapset > 7U) + { + *tapset -= 8U; + } + + return result; /* Normal End */ +} + +/** Read emmc SD_BUF data. + * + * Read 128byte data and write the data to *buf. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * Completing writing emmc data to *buf. + * + * param[in] pointer to buffer in which read data is stored + * retval EMMC_SUCCESS successful + * retval RCAR_ERR SD_INFO2 error + * return emmc error code. + */ +static EMMC_ERROR_CODE emmc_data_read(void *buf) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t i; + uint64_t *bufPtrLL; + + bufPtrLL = (uint64_t*)buf; + mem_write32(SD_INFO1, 0x0000FFFEU); /* clear BIT0 */ + + result = emmc_wait_readbuf_enable(); + if (result != EMMC_SUCCESS) + { + ERROR("%s:0x%x\n",__func__,RCAR_ERR); + panic; + } + + for (i = 0; i < (128U>>3U); i++) /* 64-bit access */ + { + *bufPtrLL = mem_read64(SD_BUF0); + bufPtrLL++; + } + + result = emmc_wait_readbuf_end(); + if (result != EMMC_SUCCESS) + { + ERROR("%s:0x%x\n",__func__,RCAR_ERR); + } + + return result; +} + +/** Check if emmc read operation has enabled and error occured. + * + * Check BIT8 of SD_INFO2. If the bit is set, + * emmc read operation has enabled and EMMC_SUCCESS is returned. + * Check BIT0-6 of SD_INFO2. If their bit is set, + * some errors has occured and RCAR_ERR is returned. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * None. + * + * retval EMMC_SUCCESS successful + * retval RCAR_ERR SD_INFO2 error + * return emmc error code. + */ +static EMMC_ERROR_CODE emmc_wait_readbuf_enable(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t dataL; + + while(true) + { + dataL = mem_read32(SD_INFO2); + if((dataL & BIT8) != 0U) /* SD_BUF Read Enable = 1 */ + { + mem_write32(SD_INFO2, 0x0000FEFFU); /* clear BIT8 */ + result = EMMC_SUCCESS; + break; + } + + /* Check Error */ + /* BIT6: Response timeout (Timeouts) */ + /* BIT5: SD_BUF Illegal Read Access */ + /* BIT4: SD_BUF Illegal Write Access */ + /* BIT3: Data timeout(other than response timeout) (Timeouts) */ + /* BIT2: END error (Communications Errors) */ + /* BIT1: CRC error (Communications Errors) */ + /* BIT0: CMD error (Communications Errors) */ + if ((BIT6_0 & dataL) != 0U) + { + result = RCAR_ERR; + break; + } + } + + return result; +} + +/** Check if emmc read operation has completed and some error occured. + * + * Check BIT2 of SD_INFO1. If the bit is set, + * emmc read operation has completed and EMMC_SUCCESS is returned. + * Check BIT0-6 of SD_INFO2. If their bit is set, + * some errors occured and RCAR_ERR is returned. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * None. + * + * retval EMMC_SUCCESS successful + * retval RCAR_ERR SD_INFO2 error + * return emmc error code. + */ +static EMMC_ERROR_CODE emmc_wait_readbuf_end(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + uint32_t dataL; + + while(true) + { + dataL = mem_read32(SD_INFO1); + if((dataL & BIT2) != 0U) /* Access End = 1 */ + { + mem_write32(SD_INFO1, 0x0000FFFBU); /* clear BIT2 */ + result = EMMC_SUCCESS; + break; + } + + dataL = mem_read32(SD_INFO2); + + /* Check Error */ + /* BIT6: Response timeout (Timeouts) */ + /* BIT5: SD_BUF Illegal Read Access */ + /* BIT4: SD_BUF Illegal Write Access */ + /* BIT3: Data timeout(other than response timeout) (Timeouts) */ + /* BIT2: END error (Communications Errors) */ + /* BIT1: CRC error (Communications Errors) */ + /* BIT0: CMD error (Communications Errors) */ + if ((BIT6_0 & dataL) != 0U) + { + result = RCAR_ERR; + break; + } + } + + return result; +} + +/** PFC register write operation. + * + * Write data masked with mask to addr after writing PMMR register. + * + * - Pre-conditions:
+ * Executing Bus initializatin by emmc_card_init(). + * - Post-conditions:
+ * Update PFC register + * + * param[in] register address + * mask value + * data to write + * return None. + */ +static void pfc_reg_modify_write(uintptr_t addr, uint32_t mask, uint32_t data) +{ + uint32_t localdata; + + localdata = mem_read32(addr); + localdata &= ~(mask); + localdata |= data; + mem_write32(PFC_PMMR(addr), ~(localdata)); + mem_write32(addr, localdata); +} diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_multiboot.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_multiboot.c new file mode 100644 index 0000000..74bd2fb --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_multiboot.c @@ -0,0 +1,94 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc multi boot + ******************************************************************************/ +/****************************************************************************** + * @file emmc multiboot.c + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_def.h" +#include "emmc_multiboot.h" +#include "types.h" + + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ +uint32_t emmc_check_result(uint32_t result); + +/* ********************************* CODE ********************************** */ + + +uint32_t emmc_trans_data(uint32_t next_bootPartition, uintptr_t sourceSct, uintptr_t targetAd, uint32_t sectorSize) +{ + EMMC_ERROR_CODE result; + uint32_t rtn_val = EMMC_DEV_ERR; + + /* Partition select */ + result = emmc_select_partition((EMMC_PARTITION_ID)next_bootPartition); + + if (result == EMMC_SUCCESS) + { + result = emmc_read_sector((uint32_t *)targetAd, sourceSct, sectorSize, LOADIMAGE_FLAGS_DMA_ENABLE); + } + + /* EMMC_ERROR_CODE -> ROM_XX */ + rtn_val = emmc_check_result((uint32_t)result); + + return rtn_val; +} +uint32_t emmc_check_result(uint32_t result) +{ + uint32_t ret = EMMC_DEV_ERR_FAULT_INJECTION; + + if (result == EMMC_SUCCESS) + { + ret = EMMC_DEV_OK; + } else if (result == EMMC_ERR) { + ret = EMMC_DEV_ERR; + } else { /* other */ + ret = EMMC_DEV_ERR_HW; + } + + return ret; +} +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_read.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_read.c new file mode 100644 index 0000000..f1f00c4 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_read.c @@ -0,0 +1,216 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc read + ******************************************************************************/ +/****************************************************************************** + * @file emmc_read.c + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 23.03.2022 0.02 Added header file inclusion + * : 16.06.2022 0.03 Change log output + * : 31.10.2022 0.04 License notation change. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +#include "log.h" +#include "mem_io.h" + +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +#define EMMC_RW_SECTOR_COUNT_MAX 0x0000ffffUL + +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +static EMMC_ERROR_CODE emmc_multiple_block_read (uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode); + +static inline uint32_t get_min_value(uint32_t a, uint32_t b) +{ + uint32_t ret = a; + + if(b < a) + { + ret = b; + } + + return ret; +} + +/* ********************************* CODE ********************************** */ + +/** function of read sector + * + * This function always use block read. + * Single block read is not used. + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * . + * + * param[in,out] buff_address_virtual virtual address of read data buffer. + * param[in] sector_number data address for MMC device (sector number). + * param[in] count number of sector. + * param[in] transfermode Mode of data transfer, DMA or not DMA. + */ +EMMC_ERROR_CODE emmc_read_sector(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, + uint32_t feature_flags) +{ + uint32_t trans_count; + uint32_t remain; + EMMC_ERROR_CODE result = EMMC_ERR; + HAL_MEMCARD_DATA_TRANSFER_MODE transfermode; + + /* parameter check */ + if (count == 0U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* state check */ + if (mmc_drv_obj.mount != TRUE) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_STATE); + return EMMC_ERR_STATE; + } + + /* DMA? */ + if ((feature_flags & LOADIMAGE_FLAGS_DMA_ENABLE) != 0U) + { + transfermode = HAL_MEMCARD_DMA; + } else { + transfermode = HAL_MEMCARD_NOT_DMA; + } + + remain = count; + while (remain != 0U) + { + trans_count = get_min_value(remain, EMMC_RW_SECTOR_COUNT_MAX); + result = emmc_multiple_block_read(buff_address_virtual, sector_number, trans_count, transfermode); + if (result != EMMC_SUCCESS) + { + return result; + } + + buff_address_virtual += (EMMC_BLOCK_LENGTH_DW * trans_count); + sector_number += trans_count; + remain -= trans_count; + } + + return EMMC_SUCCESS; +} + +/** multiple block read + * + * Multiple block read with pre-defined block count. + * + * - Pre-conditions:
+ * MMC card is mounted. + * + * - Post-conditions:
+ * . + * + * param[in,out] buff_address_virtual virtual address of read data buffer. + * param[in] sector_number data address for MMC device (sector number). + * param[in] count number of sector. (0x1 - 0xffff) + * param[in] transfer_mode Mode of data transfer, DMA or not DMA. + */ +static EMMC_ERROR_CODE emmc_multiple_block_read(uint32_t *buff_address_virtual, uint32_t sector_number, uint32_t count, + HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* parameter check */ + if ((count > EMMC_RW_SECTOR_COUNT_MAX) || (count == 0U) + || ((transfer_mode != HAL_MEMCARD_DMA) && (transfer_mode != HAL_MEMCARD_NOT_DMA))) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_PARAM); + return EMMC_ERR_PARAM; + } + + /* CMD23 */ + emmc_make_nontrans_cmd(CMD23_SET_BLOCK_COUNT, count); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + mem_write32(SD_SECCNT, count); + mem_write32(SD_STOP, 0x00000100U); + mem_write32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE)); /* SD_BUF Read/Write DMA Transfer enable */ + + /* CMD18 */ + emmc_make_trans_cmd(CMD18_READ_MULTIPLE_BLOCK, sector_number, buff_address_virtual, count << EMMC_SECTOR_SIZE_SHIFT, + HAL_MEMCARD_READ, transfer_mode); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; /* CMD18 error code */ + } + + /* CMD13 */ + emmc_make_nontrans_cmd(CMD13_SEND_STATUS, EMMC_RCA << 16U); + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + + /* ready status check */ + if ((mmc_drv_obj.r1_card_status & EMMC_R1_READY) == 0U) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_BUSY); + return EMMC_ERR_CARD_BUSY; + } + + /* state check */ + if (mmc_drv_obj.current_state != EMMC_R1_STATE_TRAN) + { + ERROR("%s:0x%x\n",__func__,EMMC_ERR_CARD_STATE); + return EMMC_ERR_CARD_STATE; + } + + return EMMC_SUCCESS; +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_utility.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_utility.c new file mode 100644 index 0000000..6112b5e --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/emmc/emmc_utility.c @@ -0,0 +1,305 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : emmc utility + ******************************************************************************/ +/****************************************************************************** + * @file emmc_utility + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ + +/* ************************ HEADER (INCLUDE) SECTION *********************** */ + +#include "emmc_config.h" +#include "emmc_hal.h" +#include "emmc_std.h" +#include "emmc_registers.h" +#include "emmc_def.h" +/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */ + +#define BUSY_SIGNAL (1U << 10U) + +static const uint32_t cmd_reg_hw[EMMC_CMD_MAX + 1U] = +{ + 0x00000000U, /* CMD0 */ + 0x00000701U, /* CMD1 */ + 0x00000002U, /* CMD2 */ + 0x00000003U, /* CMD3 */ + 0x00000004U, /* CMD4 */ + 0x00000505U, /* CMD5 */ + 0x00000406U, /* CMD6 */ + 0x00000007U, /* CMD7 */ + 0x00001C08U, /* CMD8 */ + 0x00000009U, /* CMD9 */ + 0x0000000AU, /* CMD10 */ + 0x00000000U, /* reserved */ + 0x0000000CU, /* CMD12 */ + 0x0000000DU, /* CMD13 */ + 0x00001C0EU, /* CMD14 */ + 0x0000000FU, /* CMD15 */ + 0x00000010U, /* CMD16 */ + 0x00000011U, /* CMD17 */ + 0x00007C12U, /* CMD18 */ + 0x00000C13U, /* CMD19 */ + 0x00000000U, + 0x00001C15U, /* CMD21 */ + 0x00000000U, + 0x00000017U, /* CMD23 */ + 0x00000018U, /* CMD24 */ + 0x00006C19U, /* CMD25 */ + 0x00000C1AU, /* CMD26 */ + 0x0000001BU, /* CMD27 */ + 0x0000001CU, /* CMD28 */ + 0x0000001DU, /* CMD29 */ + 0x0000001EU, /* CMD30 */ + 0x00001C1FU, /* CMD31 */ + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000423U, /* CMD35 */ + 0x00000424U, /* CMD36 */ + 0x00000000U, + 0x00000026U, /* CMD38 */ + 0x00000427U, /* CMD39 */ + 0x00000428U, /* CMD40 : send cmd */ + 0x00000000U, + 0x0000002AU, /* CMD42 */ + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000C31U, + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00007C35U, + 0x00006C36U, + 0x00000037U, /* CMD55 */ + 0x00000038U, /* CMD56 : Read */ + 0x00000000U, + 0x00000000U, + 0x00000000U, + 0x00000000U +}; +/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */ + +/* ********************** DECLARATION OF EXTERNAL DATA ********************* */ + +/* ************************** FUNCTION PROTOTYPES ************************** */ + +/* ********************************* CODE ********************************** */ + +/** make non-transfer command data + * + * Response data buffer is automatically selected. + * + * - Pre-conditions:
+ * Clock to memory card IF is enabled. + * + * - Post-conditions:
+ * After this function is called, command can be executed. + * + * param[in] cmd command information. + * param[in] arg command argument + * return None. + */ +void emmc_make_nontrans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg) +{ + /* command information */ + mmc_drv_obj.cmd_info.cmd = cmd; + mmc_drv_obj.cmd_info.arg = arg; + mmc_drv_obj.cmd_info.dir = HAL_MEMCARD_READ; + mmc_drv_obj.cmd_info.hw = cmd_reg_hw[(uint32_t)cmd & HAL_MEMCARD_COMMAND_INDEX_MASK]; + + /* clear data transfer information */ + mmc_drv_obj.trans_size = 0U; + mmc_drv_obj.remain_size = 0U; + mmc_drv_obj.buff_address_virtual = NULL; + mmc_drv_obj.buff_address_physical = NULL; + + /* response information */ + mmc_drv_obj.response_length = 6U; + + switch ((HAL_MEMCARD_RESPONSE_TYPE)((uint32_t)(mmc_drv_obj.cmd_info.cmd) & (uint32_t)HAL_MEMCARD_RESPONSE_TYPE_MASK)) + { + case HAL_MEMCARD_RESPONSE_NONE: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + mmc_drv_obj.response_length = 0U; + break; + case HAL_MEMCARD_RESPONSE_R1: + mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; + break; + case HAL_MEMCARD_RESPONSE_R1b: + mmc_drv_obj.cmd_info.hw |= BUSY_SIGNAL; /* bit10 = R1 busy bit */ + mmc_drv_obj.response = &mmc_drv_obj.r1_card_status; + break; + case HAL_MEMCARD_RESPONSE_R2: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + mmc_drv_obj.response_length = 17U; + break; + case HAL_MEMCARD_RESPONSE_R3: + mmc_drv_obj.response = &mmc_drv_obj.r3_ocr; + break; + case HAL_MEMCARD_RESPONSE_R4: + mmc_drv_obj.response = &mmc_drv_obj.r4_resp; + break; + case HAL_MEMCARD_RESPONSE_R5: + mmc_drv_obj.response = &mmc_drv_obj.r5_resp; + break; + default: + mmc_drv_obj.response = (uint32_t *)mmc_drv_obj.response_data; + break; + } +} + +/** Making command information for data transfer command. + * + * - Pre-conditions:
+ * None. + * + * - Post-conditions:
+ * After this function is called, command can be executed. + * + * param[in] cmd command + * param[in] arg command argument + * param[in] buff_address_virtual Pointer to buffer where data is/will be stored. (virtual address) + * Client is responsible of allocation and deallocation of the buffer. + * param[in] len transfer length in bytes + * param[in] dir direction + * param[in] transfer_mode Mode of data transfer, DMA or not DMA. + * return None. + */ +void emmc_make_trans_cmd(HAL_MEMCARD_COMMAND cmd, uint32_t arg, uint32_t *buff_address_virtual, /* virtual address */ +uint32_t len, HAL_MEMCARD_OPERATION dir, HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode) +{ + emmc_make_nontrans_cmd(cmd, arg); /* update common information */ + + /* for data transfer command */ + mmc_drv_obj.cmd_info.dir = dir; + mmc_drv_obj.buff_address_virtual = buff_address_virtual; + mmc_drv_obj.buff_address_physical = buff_address_virtual; + mmc_drv_obj.trans_size = len; + mmc_drv_obj.remain_size = len; + mmc_drv_obj.transfer_mode = transfer_mode; +} + +/** Send idle command. + * Function execute CMD0. + * + * - Pre-conditions:
+ * Clock to MMC I/F enabled. + * + * - Post-conditions:
+ * Card reset to idle or pre-idle state. + * + * param[in] arg CMD0 argument. + * return error code + */ +EMMC_ERROR_CODE emmc_send_idle_cmd(uint32_t arg) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + /* initialize state */ + mmc_drv_obj.mount = FALSE; + mmc_drv_obj.selected = FALSE; + mmc_drv_obj.during_transfer = FALSE; + mmc_drv_obj.during_dma_transfer = FALSE; + mmc_drv_obj.dma_error_flag = FALSE; + mmc_drv_obj.force_terminate = FALSE; + mmc_drv_obj.state_machine_blocking = FALSE; + + mmc_drv_obj.bus_width = HAL_MEMCARD_DATA_WIDTH_1_BIT; + mmc_drv_obj.max_freq = MMC_20MHZ; /* 20MHz */ + mmc_drv_obj.current_state = EMMC_R1_STATE_IDLE; + + /* CMD0 (MMC clock is current frequency. if Data transfer mode, 20MHz or higher.) */ + emmc_make_nontrans_cmd(CMD0_GO_IDLE_STATE, arg); /* CMD0 */ + result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response); + if (result != EMMC_SUCCESS) + { + return result; + } + + /* change MMC clock(400KHz) */ + mmc_drv_obj.set_freq = MMC_400KHZ; + result = emmc_set_request_mmc_clock(&mmc_drv_obj.set_freq); + if (result != EMMC_SUCCESS) + { + return result; + } + + return EMMC_SUCCESS; +} + +/** get bit field data for 16bytes data(CSD register). + * + * - Pre-conditions:
+ * . + * - Post-conditions:
+ * . + * + * param[in] data 16bytes data. + * param[in] top bit number(top). 128>top + * param[in] bottom bit number(bottom). (0<=bottom<=top) + * return bit field. + */ +uint32_t emmc_bit_field(const uint8_t *data, uint32_t top, uint32_t bottom) +{ + uint32_t value; + + uint32_t index_top = (uint32_t)(15U - (top >> 3U)); + uint32_t index_bottom = (uint32_t)(15U - (bottom >> 3U)); + + if (index_top == index_bottom) + { + value = data[index_top]; + } else if ((index_top + 1U) == index_bottom) { + value = (uint32_t)(((uint32_t)data[index_top] << 8U) | data[index_bottom]); + } else if ((index_top + 2U) == index_bottom) { + value = (uint32_t)( + ((uint32_t)data[index_top] << 16U) | ((uint32_t)data[index_top + 1U] << 8U) | data[index_top + 2U]); + } else { + value = (uint32_t)( + ((uint32_t)data[index_top] << 24U) | ((uint32_t)data[index_top + 1U] << 16U) + | ((uint32_t)data[index_top + 2U] << 8U) | data[index_top + 3U]); + } + + value = ((value >> (bottom & 0x07U)) & ((1U << ((top - bottom) + 1U)) - 1U)); + + return value; +} + +/* ******************************** END ************************************ */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/interrupt.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/interrupt.c new file mode 100644 index 0000000..951705e --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/interrupt.c @@ -0,0 +1,102 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : INTC handler function + ******************************************************************************/ +/****************************************************************************** + * @file interrupt.c + * - Version : 0.05 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.08.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + * : 15.12.2022 0.03 V4H interrupt support. + * : 27.12.2022 0.04 Change argument of pabort_error. + * : 21.08.2023 0.05 Add support for V4M. + *****************************************************************************/ +#include "ip_control.h" +#include "log.h" +#include "gic.h" +#include "swdt.h" +#include "interrupt.h" + +#if (RCAR_LSI == RCAR_S4) +void handler_fiq(void) +{ + uint32_t intid = GIC_AcknowledgePending(); + if (intid == INTC_SPI_SWDT) + { + swdt_exec(); + } + else + { + ERROR("Invalid interrupt occurred.(%d)\n",intid); + panic; + } +} +/* End of function handler_fiq(void) */ +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +void dabort_error(uint32_t occ_add, uint32_t dfsr, uint32_t dfar) +{ + + ERROR("Data abort.\n"); + ERROR(" Data abort occurrred address : 0x%x\n", occ_add); + ERROR(" DFSR:0x%x DFAR:0x%x\n", dfsr, dfar); + panic; + +} +/* End of function dabort_error(uint32_t occ_add, uint32_t dfsr, uint32_t dfare) */ + +void pabort_error(uint32_t ifsr, uint32_t ifar) +{ + + ERROR("Prefetch abort.\n"); + ERROR(" IFSR:0x%x IFAR:0x%x\n", ifsr, ifar); + panic; +} +/* End of function pabort_error(uint32_t ifsr, uint32_t ifar) */ + +void Undefined_error(uint32_t occ_add) +{ + + ERROR("Undefined Instruction.\n"); + ERROR(" Undefined Instruction occurrred address : 0x%x\n", occ_add); + panic; +} +/* End of function Undefined_error(uint32_t occ_add) */ +#endif /* RCAR_LSI == RCAR_S4 */ + +void handler_error(uint32_t ex_type) +{ + + ERROR("Unhandled exception occurred.\n"); + ERROR(" Exception type = 0x%x.\n", ex_type); + panic; +} +/* End of function handler_error(uint32_t ex_type) */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ip_control.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ip_control.c new file mode 100644 index 0000000..7eab178 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/ip_control.c @@ -0,0 +1,89 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : IP's control function + ******************************************************************************/ +/****************************************************************************** + * @file ip_control.c + * - Version : 0.08 + * @brief Initial setting controller. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 30.11.2021 0.01 First Release + * : 18.01.2022 0.02 Changed log output + * Supported Generic Timer + * : 22.03.2022 0.03 Removed unnecessary header file inclusions + * Removed unnecessary functions + * : 10.05.2022 0.04 Added function return value judgment + * : 16.06.2022 0.05 Change log output + * : 02.08.2022 0.06 Added SWDT and GIC + * : 31.10.2022 0.07 License notation change. + * : 04.09.2023 0.08 Add C4 power domain setting. + * : 13.10.2023 0.09 Moved C4 power domain setting to ICUMX IPL. + *****************************************************************************/ +#include +#include +#include +#include +#include +#include +#include "gic.h" +#include "swdt.h" + +void ip_init(void) +{ + scif_init(); + generic_timer_init(); + +#if (RCAR_LSI == RCAR_S4) + Interrupt_Config(); + Interrupt_Enable(INTC_SPI_SWDT); + swdt_init(); +#endif /* RCAR_LSI == RCAR_S4 */ + + emmc_initialize(); +} +/* End of function ip_init(void) */ + +void ip_release(void) +{ + EMMC_ERROR_CODE result = EMMC_ERR; + + result = emmc_terminate(); + if(EMMC_SUCCESS != result) + { + ERROR("ip_release error (emmc_terminate).\n"); + panic; + } + +#if (RCAR_LSI == RCAR_S4) + swdt_release(); + Interrupt_Disable(INTC_SPI_SWDT); +#endif /* RCAR_LSI == RCAR_S4 */ +} +/* End of function ip_release(void) */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/qos/qos.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/qos/qos.c new file mode 100644 index 0000000..f1a22cd --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/qos/qos.c @@ -0,0 +1,553 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2021-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : QoS initialize function + ******************************************************************************/ +/****************************************************************************** + * @file qos.c + * - Version : 0.14 + * @brief Initial setting process of QoS. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 28.07.2021 0.01 First Release + * : 23.05.2022 0.02 Integration of S4 and V4H + * Update QoS setting rev.0.02 (for S4) + * Update QoS setting rev.0.03 (for V4H) + * : 20.01.2023 0.03 Add DBSC W/A 1,2,3 (OTLINT-5579) + * : 19.04.2023 0.04 Update the setting version from v6.1 to v7.0(for V4H). + * : 22.05.2023 0.05 Update the setting version from v7.0 to v7.1.1(for V4H). + * : 22.05.2023 0.06 Update the setting version from v7.1.1 to v8.0.0(for V4H). + * : 08.06.2023 0.07 Update the setting version from v8.0.0 to v8.0.1(for V4H). + * : 15.06.2023 0.08 Update the setting version from v8.0.1 to v8.0.2(for V4H). + * : 21.08.2023 0.09 Add support for V4M. + * : 20.09.2023 0.10 Update the setting version from v9.0.1 to v10.0.0(for V4M). + * : 20.09.2023 0.11 Update the setting version from v10.0.0 to v10.1.0(for V4H). + * : 11.10.2023 0.12 Update the setting version from v10.1.0 to v10.2.1(for V4H/V4M). + * : 17.01.2024 0.13 Update the setting version from v10.1.0 to v11.0.0(for V4H/V4M). + * : 05.04.2024 0.14 Update the setting version from v11.0.0 to v12.0.0(for V4H/V4M). + *****************************************************************************/ + +#include +#if defined(__RH850G3K__) +#include +#include +#include +#else +#include +#include +#endif +#include +#include +#include +#include + +#if (RCAR_LSI == RCAR_S4) +#define RCAR_QOS_VERSION "base_v6.1" +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#define RCAR_QOS_VERSION "v12.0.0" +#endif /* RCAR_LSI == RCAR_S4 */ + +#define RCAR_DRAM_SPLIT_DISABLE (0U) +#define RCAR_DRAM_SPLIT_ENABLE (1U) +#define RCAR_REWT_TRAINING_DISABLE (0U) +#define RCAR_REWT_TRAINING_ENABLE (1U) + +#if defined(__RH850G3K__) +#define AXMM_BASE (BASE_AXMM_ADDR) +#else +#define AXMM_BASE (0xE6780000U) +#endif +#define AXMM_MMCR (AXMM_BASE + 0x4300U) +#define AXMM_ADSPLCR0 (AXMM_BASE + 0x4008U) +#define AXMM_ADSPLCR1 (AXMM_BASE + 0x400CU) +#define AXMM_ADSPLCR2 (AXMM_BASE + 0x4010U) +#define AXMM_ADSPLCR3 (AXMM_BASE + 0x4014U) +#define AXMM_TR3CR (AXMM_BASE + 0x5100CU) + +#if (RCAR_LSI == RCAR_S4) +#if defined(__RH850G3K__) +#define DBSC_BASE (BASE_DBSC_ADDR) +#else +#define DBSC_BASE (0xE6790000U) +#endif + +#define DBSC_CH_NUM (1U) /* Number of DBSCx */ +#define DBSC_A_CH_OFFSET (0U) /* 1ch only (for S4)*/ +#define DBSC_D_CH_OFFSET (0U) /* 1ch only (for S4)*/ + +#define DBSC_SYSCNT0 (DBSC_BASE + 0x0100U) +#define DBSC_SYSCNT0A (DBSC_BASE + 0x0108U) +#define DBSC_DBBUS0CNF2 (DBSC_BASE + 0x0808U) +#define DBSC_DBCAM0CNF1 (DBSC_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_BASE + 0x0908U) +#define DBSC_DBCAM0CNF3 (DBSC_BASE + 0x090CU) +#define DBSC_DBCAMDIS (DBSC_BASE + 0x09FCU) +#define DBSC_DBSCHCNT0 (DBSC_BASE + 0x1000U) +#define DBSC_DBSCHSZ0 (DBSC_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_BASE + 0x1020U) +#define DBSC_DBSCHQOS_0_0 (DBSC_BASE + 0x1030U) +#define DBSC_DBSCHQOS_0_1 (DBSC_BASE + 0x1034U) +#define DBSC_DBSCHQOS_0_2 (DBSC_BASE + 0x1038U) +#define DBSC_DBSCHQOS_0_3 (DBSC_BASE + 0x103CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_BASE + 0x1070U) +#define DBSC_DBSCHQOS_4_1 (DBSC_BASE + 0x1074U) +#define DBSC_DBSCHQOS_4_2 (DBSC_BASE + 0x1078U) +#define DBSC_DBSCHQOS_4_3 (DBSC_BASE + 0x107CU) +#define DBSC_DBSCHQOS_9_0 (DBSC_BASE + 0x10C0U) +#define DBSC_DBSCHQOS_9_1 (DBSC_BASE + 0x10C4U) +#define DBSC_DBSCHQOS_9_2 (DBSC_BASE + 0x10C8U) +#define DBSC_DBSCHQOS_9_3 (DBSC_BASE + 0x10CCU) +#define DBSC_DBSCHQOS_12_0 (DBSC_BASE + 0x10F0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_BASE + 0x10F4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_BASE + 0x10F8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_BASE + 0x10FCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_BASE + 0x1100U) +#define DBSC_DBSCHQOS_13_1 (DBSC_BASE + 0x1104U) +#define DBSC_DBSCHQOS_13_2 (DBSC_BASE + 0x1108U) +#define DBSC_DBSCHQOS_13_3 (DBSC_BASE + 0x110CU) +#define DBSC_DBSCHQOS_14_0 (DBSC_BASE + 0x1110U) +#define DBSC_DBSCHQOS_14_1 (DBSC_BASE + 0x1114U) +#define DBSC_DBSCHQOS_14_2 (DBSC_BASE + 0x1118U) +#define DBSC_DBSCHQOS_14_3 (DBSC_BASE + 0x111CU) +#define DBSC_DBSCHQOS_15_0 (DBSC_BASE + 0x1120U) +#define DBSC_DBSCHQOS_15_1 (DBSC_BASE + 0x1124U) +#define DBSC_DBSCHQOS_15_2 (DBSC_BASE + 0x1128U) +#define DBSC_DBSCHQOS_15_3 (DBSC_BASE + 0x112CU) +#define DBSC_SCFCTST2 (DBSC_BASE + 0x170CU) +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if defined(__RH850G3K__) +#define DBSC_D_BASE (BASE_DBSC_ADDR + 0x14000U) +#define DBSC_A_BASE (BASE_DBSC_ADDR) +#else +#define DBSC_D_BASE (0xE67A4000U) +#define DBSC_A_BASE (0xE6790000U) +#endif + +#if (RCAR_LSI == RCAR_V4H) +#define DBSC_CH_NUM (2U) /* ch number of DBSCx */ +#elif (RCAR_LSI == RCAR_V4M) +#define DBSC_CH_NUM (1U) /* ch number of DBSCx */ +#endif + +#define DBSC_A_CH_OFFSET (0x8000U) +#define DBSC_D_CH_OFFSET (0x4000U) + +#define DBSC_SYSCNT0 (DBSC_D_BASE + 0x0100U) +#define DBSC_SYSCNT1 (DBSC_A_BASE + 0x0104U) +#define DBSC_SYSCNT0A (DBSC_A_BASE + 0x0100U) +#define DBSC_DBBUS0CNF2 (DBSC_A_BASE + 0x0808U) +#define DBSC_DBCAM0CNF1 (DBSC_A_BASE + 0x0904U) +#define DBSC_DBCAM0CNF2 (DBSC_A_BASE + 0x0908U) +#define DBSC_DBCAMDIS (DBSC_A_BASE + 0x09FCU) +#define DBSC_DBCAM0CNF3 (DBSC_A_BASE + 0x090CU) +#define DBSC_DBSCHCNT0 (DBSC_A_BASE + 0x1000U) +#define DBSC_DBSCHSZ0 (DBSC_A_BASE + 0x1010U) +#define DBSC_DBSCHRW0 (DBSC_A_BASE + 0x1020U) +#define DBSC_DBSCHQOS_0_0 (DBSC_A_BASE + 0x1100U) +#define DBSC_DBSCHQOS_0_1 (DBSC_A_BASE + 0x1104U) +#define DBSC_DBSCHQOS_0_2 (DBSC_A_BASE + 0x1108U) +#define DBSC_DBSCHQOS_0_3 (DBSC_A_BASE + 0x110CU) +#define DBSC_DBSCHQOS_4_0 (DBSC_A_BASE + 0x1140U) +#define DBSC_DBSCHQOS_4_1 (DBSC_A_BASE + 0x1144U) +#define DBSC_DBSCHQOS_4_2 (DBSC_A_BASE + 0x1148U) +#define DBSC_DBSCHQOS_4_3 (DBSC_A_BASE + 0x114CU) +#define DBSC_DBSCHQOS_9_0 (DBSC_A_BASE + 0x1190U) +#define DBSC_DBSCHQOS_9_1 (DBSC_A_BASE + 0x1194U) +#define DBSC_DBSCHQOS_9_2 (DBSC_A_BASE + 0x1198U) +#define DBSC_DBSCHQOS_9_3 (DBSC_A_BASE + 0x119CU) +#define DBSC_DBSCHQOS_12_0 (DBSC_A_BASE + 0x11C0U) +#define DBSC_DBSCHQOS_12_1 (DBSC_A_BASE + 0x11C4U) +#define DBSC_DBSCHQOS_12_2 (DBSC_A_BASE + 0x11C8U) +#define DBSC_DBSCHQOS_12_3 (DBSC_A_BASE + 0x11CCU) +#define DBSC_DBSCHQOS_13_0 (DBSC_A_BASE + 0x11D0U) +#define DBSC_DBSCHQOS_13_1 (DBSC_A_BASE + 0x11D4U) +#define DBSC_DBSCHQOS_13_2 (DBSC_A_BASE + 0x11D8U) +#define DBSC_DBSCHQOS_13_3 (DBSC_A_BASE + 0x11DCU) +#define DBSC_DBSCHQOS_14_0 (DBSC_A_BASE + 0x11E0U) +#define DBSC_DBSCHQOS_14_1 (DBSC_A_BASE + 0x11E4U) +#define DBSC_DBSCHQOS_14_2 (DBSC_A_BASE + 0x11E8U) +#define DBSC_DBSCHQOS_14_3 (DBSC_A_BASE + 0x11ECU) +#define DBSC_DBSCHQOS_15_0 (DBSC_A_BASE + 0x11F0U) +#define DBSC_DBSCHQOS_15_1 (DBSC_A_BASE + 0x11F4U) +#define DBSC_DBSCHQOS_15_2 (DBSC_A_BASE + 0x11F8U) +#define DBSC_DBSCHQOS_15_3 (DBSC_A_BASE + 0x11FCU) +#define DBSC_SCFCTST2 (DBSC_A_BASE + 0x1048U) + +#define AXMM_TR0CR0 (AXMM_BASE + 0x51000U) +#define AXMM_TR1CR0 (AXMM_BASE + 0x51004U) +#define AXMM_TR2CR0 (AXMM_BASE + 0x51008U) +#define AXMM_TR3CR0 (AXMM_BASE + 0x5100CU) +#define AXMM_TR0CR1 (AXMM_BASE + 0x51100U) +#define AXMM_TR1CR1 (AXMM_BASE + 0x51104U) +#define AXMM_TR2CR1 (AXMM_BASE + 0x51108U) +#define AXMM_TR3CR1 (AXMM_BASE + 0x5110CU) +#define AXMM_TR0CR2 (AXMM_BASE + 0x51200U) +#define AXMM_TR1CR2 (AXMM_BASE + 0x51204U) +#define AXMM_TR2CR2 (AXMM_BASE + 0x51208U) +#define AXMM_TR3CR2 (AXMM_BASE + 0x5120CU) +#define DBSC_FCPRSCTRL (DBSC_A_BASE + 0x0110U) +#define ACTEXT_RT0_R (0xFFC50800U) +#define ACTEXT_RT0_W (0xFFC51800U) +#define ACTEXT_IR0_R (0xFF890800U) +#define ACTEXT_IR0_W (0xFF891800U) +#define ACTEXT_IR1_R (0xFF892800U) +#define ACTEXT_IR1_W (0xFF893800U) +#define SI0_RW_MAX (0xF1201110U) +#define SI1_RW_MAX (0xF1202110U) +#endif /* RCAR_LSI == RCAR_S4 */ + +#if defined(__RH850G3K__) +#define QOS_BASE (BASE_QOS_ADDR) +#else +#define QOS_BASE (0xE67E0000U) +#endif +#define QOS_FIX_QOS_BANK0 (QOS_BASE + 0x00000000U) +#define QOS_FIX_QOS_BANK1 (QOS_BASE + 0x00001000U) +#define QOS_BE_QOS_BANK0 (QOS_BASE + 0x00002000U) +#define QOS_BE_QOS_BANK1 (QOS_BASE + 0x00003000U) +#define QOS_SL_INIT (QOS_BASE + 0x00008000U) +#define QOS_REF_ARS (QOS_BASE + 0x00008004U) +#define QOS_STATQC (QOS_BASE + 0x00008008U) +#define QOS_REF_ENBL (QOS_BASE + 0x00008044U) +#define QOS_BWG (QOS_BASE + 0x0000804CU) +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE +#define QOSWT_FIX_QOS_BANK0 (QOS_BASE + 0x00000800U) +#define QOSWT_FIX_QOS_BANK1 (QOS_BASE + 0x00001800U) +#define QOSWT_BE_QOS_BANK0 (QOS_BASE + 0x00002800U) +#define QOSWT_BE_QOS_BANK1 (QOS_BASE + 0x00003800U) +#define QOSWT_WTEN (QOS_BASE + 0x00008030U) +#define QOSWT_WTREF (QOS_BASE + 0x00008034U) +#define QOSWT_WTSET0 (QOS_BASE + 0x00008038U) +#define QOSWT_WTSET1 (QOS_BASE + 0x0000803CU) +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + +#define QOS_RAS (QOS_BASE + 0x00010000U) +#define QOS_RAEN (QOS_BASE + 0x00010018U) +#define QOS_DANN_LOW (QOS_BASE + 0x00010030U) +#define QOS_DANN_HIGH (QOS_BASE + 0x00010034U) +#define QOS_DANT (QOS_BASE + 0x00010038U) +#define QOS_EMS_LOW (QOS_BASE + 0x00010040U) +#define QOS_EMS_HIGH (QOS_BASE + 0x00010044U) +#define QOS_FSS (QOS_BASE + 0x00010048U) +#define QOS_INSFC (QOS_BASE + 0x00010050U) +#define QOS_EARLYR (QOS_BASE + 0x00010060U) +#define QOS_RACNT0 (QOS_BASE + 0x00010080U) +#define QOS_STATGEN0 (QOS_BASE + 0x00010088U) + +#define CCI_BASE (BASE_CCI_ADDR) +#define CCIQOS00 (CCI_BASE + 0xC020U) +#define CCIQOS01 (CCI_BASE + 0xC024U) +#define CCIQOS10 (CCI_BASE + 0xD000U) +#define CCIQOS11 (CCI_BASE + 0xD004U) +#if (RCAR_LSI == RCAR_S4) +#define CCIQOS12 (CCI_BASE + 0xD008U) +#define CCIQOS13 (CCI_BASE + 0xD00CU) +#endif + +static void dbsc_setting(void) +{ + for(uint32_t loop = 0; loop < DBSC_CH_NUM; loop++) + { + /* DBSC CAM, Scheduling Setting */ + mem_write32((DBSC_SYSCNT0 + (DBSC_D_CH_OFFSET * loop)), 0x00001234U); + mem_write32((DBSC_SYSCNT0A + (DBSC_A_CH_OFFSET * loop)), 0x00001234U); + mem_write32((DBSC_DBCAM0CNF1 + (DBSC_A_CH_OFFSET * loop)), 0x00048218U); /* dbcam0cnf1 */ +#if ((ECC_ENABLE == 1) && (RCAR_LSI == RCAR_V4H)) + /* For WA for DBSC5 Hang5 issue. */ + if ((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21) + { + mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000002C4U); /* dbcam0cnf2 */ + } + else + { + mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U); /* dbcam0cnf2 */ + } +#elif (RCAR_LSI == RCAR_V4M) + mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U); /* dbcam0cnf2 */ +#else + mem_write32((DBSC_DBCAM0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x000001C4U); /* dbcam0cnf2 */ +#endif + mem_write32((DBSC_DBCAM0CNF3 + (DBSC_A_CH_OFFSET * loop)), 0x00000003U); /* dbcam0cnf3 */ + +#if (RCAR_LSI == RCAR_S4) + #if ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 1)) + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000002U); /* OTLINT-5579: V4H DBSC W/A-1,2 */ + #else + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000000U); + #endif +#elif (RCAR_LSI == RCAR_V4H) + #if ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 1)) + if((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21) + { + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000013U); /* OTLINT-5579: V4H DBSC W/A-1,2,3 */ + } + else if((mem_read32(PRR) & PRR_CUT_MASK) == PRR_PRODUCT_22) + { + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000012U); + } + else + { + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); + } + #elif ((WA_OTLINT5579 == 1) && (ECC_ENABLE == 0)) + if((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21) + { + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000011U); /* OTLINT-5579: V4H DBSC W/A-3 */ + } + else + { + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); + } + #else + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); + #endif +#elif (RCAR_LSI == RCAR_V4M) + # if (ECC_ENABLE == 1) + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000012U); + #else + mem_write32((DBSC_DBCAMDIS + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); + # endif +#endif + + mem_write32((DBSC_DBSCHCNT0 + (DBSC_A_CH_OFFSET * loop)), 0x000F0037U); /* dbschcnt0 */ + mem_write32((DBSC_DBSCHSZ0 + (DBSC_A_CH_OFFSET * loop)), 0x00000001U); /* dbschsz0 */ + mem_write32((DBSC_DBSCHRW0 + (DBSC_A_CH_OFFSET * loop)), 0xF7311111U); /* dbschrw0 */ + mem_write32((DBSC_SCFCTST2 + (DBSC_A_CH_OFFSET * loop)), 0x111F1FFFU); + +#if (((RCAR_LSI == RCAR_V4H) && (WA_OTLINT5579 == 1)) || (RCAR_LSI == RCAR_V4M)) + mem_write32((DBSC_DBBUS0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x00000007U); /* OTLINT-5579: V4H DBSC WA3 */ +#else + mem_write32((DBSC_DBBUS0CNF2 + (DBSC_A_CH_OFFSET * loop)), 0x00000003U); /* S4, V4H w/o DBSC WA3 */ +#endif + + /* DBSC QoS Setting */ + mem_write32((DBSC_DBSCHQOS_0_0 + (DBSC_A_CH_OFFSET * loop)), 0x0000FFFFU); + mem_write32((DBSC_DBSCHQOS_0_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000480U); + mem_write32((DBSC_DBSCHQOS_0_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_0_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_4_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000400U); + mem_write32((DBSC_DBSCHQOS_4_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_4_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000200U); + mem_write32((DBSC_DBSCHQOS_4_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); + mem_write32((DBSC_DBSCHQOS_9_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_9_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000240U); + mem_write32((DBSC_DBSCHQOS_9_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_9_3 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U); + mem_write32((DBSC_DBSCHQOS_12_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000040U); + mem_write32((DBSC_DBSCHQOS_12_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000030U); + mem_write32((DBSC_DBSCHQOS_12_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000020U); + mem_write32((DBSC_DBSCHQOS_12_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000010U); + mem_write32((DBSC_DBSCHQOS_13_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000300U); + mem_write32((DBSC_DBSCHQOS_13_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000240U); + mem_write32((DBSC_DBSCHQOS_13_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_13_3 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U); + mem_write32((DBSC_DBSCHQOS_14_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000200U); + mem_write32((DBSC_DBSCHQOS_14_1 + (DBSC_A_CH_OFFSET * loop)), 0x00000180U); + mem_write32((DBSC_DBSCHQOS_14_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); + mem_write32((DBSC_DBSCHQOS_14_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000080U); + mem_write32((DBSC_DBSCHQOS_15_0 + (DBSC_A_CH_OFFSET * loop)), 0x00000100U); + mem_write32((DBSC_DBSCHQOS_15_1 + (DBSC_A_CH_OFFSET * loop)), 0x000000C0U); + mem_write32((DBSC_DBSCHQOS_15_2 + (DBSC_A_CH_OFFSET * loop)), 0x00000080U); + mem_write32((DBSC_DBSCHQOS_15_3 + (DBSC_A_CH_OFFSET * loop)), 0x00000040U); + if (loop == 0) /* Target register is only DBSC0 side. */ + { + mem_write32(DBSC_FCPRSCTRL, 0x00000001U); + } + mem_write32((DBSC_SYSCNT1 + (DBSC_A_CH_OFFSET * loop)), 0x00000001U); + mem_write32((DBSC_SYSCNT0 + (DBSC_D_CH_OFFSET * loop)), 0x00000000U); + mem_write32((DBSC_SYSCNT0A + (DBSC_A_CH_OFFSET * loop)), 0x00000000U); + } +} +/* End of function dbsc_setting(void) */ + +void qos_init(void) +{ + uint32_t i; + + /* Setting the register of DBSC4 for QoS initialize */ + dbsc_setting(); + + NOTICE("QoS setting(%s)\n", RCAR_QOS_VERSION); + NOTICE("DRAM refresh interval 1.91 usec\n"); + +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE + NOTICE("Periodic Write DQ Training\n"); +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + +#if (RCAR_LSI == RCAR_S4) + /* Resource Alloc setting */ + mem_write32(QOS_RAS, 0x00000028U); + mem_write32(QOS_DANN_LOW, 0x02020201U); + mem_write32(QOS_DANN_HIGH, 0x04040200U); + mem_write32(QOS_DANT, 0x00181004U); + mem_write32(QOS_EMS_LOW, 0x00000000U); + mem_write32(QOS_EMS_HIGH, 0x00000000U); + mem_write32(QOS_FSS, 0x0000000AU); + mem_write32(QOS_INSFC, 0x030F0001U); + mem_write32(QOS_EARLYR, 0x00000000U); + mem_write32(QOS_RACNT0, 0x00050003U); + mem_write32(QOS_STATGEN0, 0x00000000U); + + /* QoS MSTAT setting */ + mem_write32(QOS_SL_INIT, 0x00050100U); + mem_write32(QOS_REF_ARS, 0x00FB0000U); + mem_write32(QOS_REF_ENBL, 0x00000012U); + mem_write32(QOS_BWG, 0x00000002U); + mem_write32(AXMM_MMCR, 0x00010000U); + + mem_write32(CCIQOS00, 0x08000000); + mem_write32(CCIQOS01, 0x08000000); + mem_write32(CCIQOS10, 0x00000001); + mem_write32(CCIQOS11, 0x00000001); + mem_write32(CCIQOS12, 0x00000001); + mem_write32(CCIQOS13, 0x00000001); +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + #if (RCAR_LSI == RCAR_V4H) + #if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_ENABLE) + /* Address Split 2ch */ + mem_write32(AXMM_ADSPLCR0, 0x00000000U); + mem_write32(AXMM_ADSPLCR1, 0x00FF1B0CU); + mem_write32(AXMM_ADSPLCR2, 0x00000000U); + mem_write32(AXMM_ADSPLCR3, 0x00000000U); + #endif +#endif + +#if (RCAR_LSI == RCAR_V4H) + mem_write32(CCIQOS00, 0x08000000); + mem_write32(CCIQOS01, 0x08000000); + if ((mem_read32(PRR) & PRR_CUT_MASK) >= PRR_PRODUCT_20) + { + mem_write32(CCIQOS10, 0x00000001U); + mem_write32(CCIQOS11, 0x00000001U); + } + else + { + mem_write32(CCIQOS10, 0x00000000U); + mem_write32(CCIQOS11, 0x00000000U); + } + #endif + /* Resource Alloc setting */ +#if (RCAR_LSI == RCAR_V4H) + mem_write32(QOS_RAS, 0x00000048U); +#elif (RCAR_LSI == RCAR_V4M) + mem_write32(QOS_RAS, 0x00000030U); +#endif + mem_write32(QOS_DANN_LOW, 0x02020201U); + mem_write32(QOS_DANN_HIGH, 0x04040200U); + mem_write32(QOS_DANT, 0x00181008U); + mem_write32(QOS_EMS_LOW, 0x00000000U); + mem_write32(QOS_EMS_HIGH, 0x00000000U); + mem_write32(QOS_FSS, 0x0000000AU); + mem_write32(QOS_INSFC, 0x030F0001U); + mem_write32(QOS_EARLYR, 0x00000000U); + mem_write32(QOS_RACNT0, 0x00050003U); + mem_write32(QOS_STATGEN0, 0x00000000U); + + /* QoS MSTAT setting */ + mem_write32(QOS_SL_INIT, 0x00070120U); + mem_write32(QOS_REF_ARS, 0x011B0000U); + mem_write32(QOS_REF_ENBL, 0x00000012U); + mem_write32(QOS_BWG, 0x00000004U); + #if ((RCAR_LSI == RCAR_V4H) && (WA_OTLINT5579 == 1)) + if ((mem_read32(PRR) & PRR_CUT_MASK) <= PRR_PRODUCT_21) + { + mem_write32(AXMM_MMCR, 0x00000000U); /* OTLINT-5579: V4H DBSC WA3 */ + } + else + { + mem_write32(AXMM_MMCR, 0x00010000U); /* OTLINT-5579: V4H DBSC WA3 */ + } + #elif (RCAR_LSI == RCAR_V4M) + mem_write32(AXMM_MMCR, 0x00010000U); + #else + mem_write32(AXMM_MMCR, 0x00010000U); + #endif + mem_write32(ACTEXT_RT0_R, 0x00000003U); + mem_write32(ACTEXT_RT0_W, 0x00000003U); + mem_write32(ACTEXT_IR0_R, 0x00000003U); + mem_write32(ACTEXT_IR0_W, 0x00000003U); + mem_write32(ACTEXT_IR1_R, 0x00000003U); + mem_write32(ACTEXT_IR1_W, 0x00000003U); +#if (RCAR_LSI == RCAR_V4H) + mem_write32(AXMM_TR3CR, 0x00010000U); +#endif + +#if (RCAR_LSI == RCAR_V4M) + mem_write32(AXMM_TR0CR0, 0x00000000U); + mem_write32(AXMM_TR1CR0, 0x00000000U); + mem_write32(AXMM_TR2CR0, 0x00000000U); + mem_write32(AXMM_TR3CR0, 0x00000000U); + mem_write32(AXMM_TR0CR1, 0x70707070U); + mem_write32(AXMM_TR1CR1, 0x70707070U); + mem_write32(AXMM_TR2CR1, 0x70707070U); + mem_write32(AXMM_TR3CR1, 0x70707070U); + mem_write32(AXMM_TR0CR2, 0x70707070U); + mem_write32(AXMM_TR1CR2, 0x70707070U); + mem_write32(AXMM_TR2CR2, 0x70707070U); + mem_write32(AXMM_TR3CR2, 0x70707070U); +#endif + + +#if (RCAR_LSI == RCAR_V4H) + if ((mem_read32(PRR) & PRR_CUT_MASK) >= PRR_PRODUCT_20) + { + /* WA1 patch for IPL CA76 hang-up issue, REL_TRI_DN-7592 */ + mem_write32(SI0_RW_MAX, 0x00000038U); + mem_write32(SI1_RW_MAX, 0x00000038U); + } +#endif + +#endif /* RCAR_LSI == RCAR_S4 */ + + for (i = 0U; i < QOS_TBL_MAX; i++) + { + mem_write64((QOS_FIX_QOS_BANK0 + (i * 8U)), g_qosbw_tbl[i].fix); + mem_write64((QOS_FIX_QOS_BANK1 + (i * 8U)), g_qosbw_tbl[i].fix); + mem_write64((QOS_BE_QOS_BANK0 + (i * 8U)), g_qosbw_tbl[i].be); + mem_write64((QOS_BE_QOS_BANK1 + (i * 8U)), g_qosbw_tbl[i].be); + } + +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE + for (i = 0U; i < QOS_TBL_MAX; i++) + { + mem_write64((QOSWT_FIX_QOS_BANK0 + (i * 8U)), g_qoswt_tbl[i].fix); + mem_write64((QOSWT_FIX_QOS_BANK1 + (i * 8U)), g_qoswt_tbl[i].fix); + mem_write64((QOSWT_BE_QOS_BANK0 + (i * 8U)), g_qoswt_tbl[i].be); + mem_write64((QOSWT_BE_QOS_BANK1 + (i * 8U)), g_qoswt_tbl[i].be); + } +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + + /* QoS SRAM setting */ + mem_write32(QOS_RAEN, 0x00000001U); +#if RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE + mem_write32(QOSWT_WTREF, 0x02080208U); + mem_write32(QOSWT_WTSET0, 0x0D90050FU); + mem_write32(QOSWT_WTSET1, 0x0D90050FU); + mem_write32(QOSWT_WTEN, 0x00000001U); +#endif /* RCAR_PERIODIC_WRITE_TRAINING != RCAR_REWT_TRAINING_DISABLE */ + mem_write32(QOS_STATQC, 0x00000101U); +} +/* End of function qos_init(void) */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/rtvram/rtvram.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/rtvram/rtvram.c new file mode 100644 index 0000000..ae64c17 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/rtvram/rtvram.c @@ -0,0 +1,81 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : RT-VRAM driver + ******************************************************************************/ +/****************************************************************************** + * @file RTVRAM.c + * - Version : 0.03 + * @brief RT-VRAM driver. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 17.11.2021 0.01 First Release + * : 03.12.2021 0.02 remove Cache flush. + * : 06.01.2022 0.03 Static analysis support + *****************************************************************************/ + +#if defined(__RH850G3K__) +#include +#else +#include +#endif +#include +#include +#include +#include + +#define RTVRAM_VBUF_CFG_CACHE_MODE_8WAY (1U << 8U) +#define RTVRAM_VBUF_CFG_VBUF_SIZE_28M (6U << 0U) + +#define RTVRAM_EXT_MODE_EXT (1U << 0U) + +#define RTVRAM_VBUF_NUM (7U) + +#define RTVRAM_EXTEND_ENABLE (1U) + +void rtvram_extendmode(void) +{ +#if (RTVRAM_EXTEND == RTVRAM_EXTEND_ENABLE) + uint32_t reg; + uint32_t loop; + + /* Set each 4MB from the top of SDRAM as the buffer area of RT-VRAM. */ + for(loop = 0; loop < RTVRAM_VBUF_NUM; loop++) + { + mem_write32(get_vbuf_baddr_addr(loop), (uint32_t)((SDRAM_40BIT_ADDR_TOP + (RTVRAM_VBUF_AREA_SIZE * loop)) >> 16U)); + } + + reg = mem_read32(RTVRAM_VBUF_CFG); + reg |= (RTVRAM_VBUF_CFG_CACHE_MODE_8WAY | RTVRAM_VBUF_CFG_VBUF_SIZE_28M); /* Cache Mode: 8-way, VBF size: 28M */ + mem_write32(RTVRAM_VBUF_CFG, reg); + + /* Set at the end */ + mem_write32(RTVRAM_EXT_MODE, RTVRAM_EXT_MODE_EXT); /* Change from Compatible Mode to Extended Mode */ + + syncm(); +#endif +} +/* End of function rtvram_extendmode(void) */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/swdt/swdt.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/swdt/swdt.c new file mode 100644 index 0000000..c2f776c --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/ip/swdt/swdt.c @@ -0,0 +1,123 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Watchdog Timer function + ******************************************************************************/ +/****************************************************************************** + * @file swdt.c + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 12.08.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. +*****************************************************************************/ +#include "mem_io.h" +#include "rcar_def.h" +#include "rcar_register.h" +#include "swdt.h" +#include "gic.h" +#include "log.h" +#include "ip_control.h" + +void swdt_init(void) +{ + uint32_t sr; + uint32_t reg; + uint32_t val; + uint32_t chk_data; + + /* 1. Clear the TME bit in SWTCSRA to 0 to temporarily stop counting. */ + reg = mem_read32(SWDT_WTCSRA) & WTCSRA_TME; + if (WTCSRA_TME == reg) + { + mem_write32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE); + } + + /* 2.Write the set value in SWTCNT */ + /* OSCCLK check */ + reg = mem_read32(RST_MODEMR0); + chk_data = reg & CHECK_MD13_MD14; + + val = WTCNT_UPPER_BYTE; + + if (MD14_MD13_TYPE_0 == chk_data) + { + val |= SWDTCNT_133330HZ; + } + else if(MD14_MD13_TYPE_1 == chk_data) + { + val |= SWDTCNT_131570HZ; + } + else if(MD14_MD13_TYPE_3 == chk_data) + { + val |= SWDTCNT_131570HZ; + } + else + { + ERROR("MODEMR ERROR value = 0x%x\n", chk_data); + panic; + } + + mem_write32(SWDT_WTCNT, val); + + /* 3. Clear the bit4(WOVF) in SWTCSRA to 0. */ + mem_write32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE | WTCSRA_WOVFE | WTCSRA_CKS0_OSCCLK); + + /* 5.Confirm that SWTCSRA.WRFLG becomes 0.*/ + while (true) + { + if ((mem_read32(SWDT_WTCSRA) & WTCSRA_WRFLG) == 0U) + { + break; + } + } + + /* 6. Start the counting by setting the TME bit in SWTCSRA to 1. */ + sr = mem_read32(SWDT_WTCSRA) & WTCSRA_MASK_ALL; + + mem_write32(SWDT_WTCSRA, (WTCSRA_UPPER_BYTE | sr | WTCSRA_TME)); + +} +/* End of function swdt_init(void) */ + +void swdt_release(void) +{ + + mem_write32(SWDT_WTCSRA, WTCSRA_INIT_DATA); + mem_write32(SWDT_WTCNT, WTCNT_INIT_DATA); +} +/* End of function swdt_release(void) */ + +void swdt_exec(void) +{ + ERROR("System Watchdog Timer overflow.\n"); + panic; +} +/* End of function swdt_exec(void) */ + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/asm_macros.S b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/asm_macros.S new file mode 100644 index 0000000..952a364 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/asm_macros.S @@ -0,0 +1,55 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : macro + ******************************************************************************/ +/****************************************************************************** + * @file asm_macros.S + * - Version : 0.03 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 07.02.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + * : 17.02.2023 0.03 Modified instruction to lower case. + *****************************************************************************/ +#ifndef ASM_MACROS_S +#define ASM_MACROS_S + + .macro mov_imm _reg, _val + .if (\_val) > 65535 + mov \_reg, (\_val >> 0) & 0xffff + movk \_reg, (\_val >> 16) & 0xffff, lsl #16 + movk \_reg, (\_val >> 32) & 0xffff, lsl #32 + movk \_reg, (\_val >> 48) & 0xffff, lsl #48 + .else + mov \_reg, (\_val) + .endif + .endm + +#endif /* ASM_MACROS_S */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_exceptions.S b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_exceptions.S new file mode 100644 index 0000000..025bb8f --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_exceptions.S @@ -0,0 +1,207 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file loader_exceptions.S + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.08.2022 0.01 First Release + * : 31.10.2022 0.02 License notation change. + *****************************************************************************/ +#define SYNC_SP_EL0 (0x0U) +#define IRQ_SP_EL0 (0x1U) +#define FIQ_SP_EL0 (0x2U) +#define SERROR_SP_EL0 (0x3U) +#define SYNC_SP_ELX (0x4U) +#define IRQ_SP_ELX (0x5U) +#define FIQ_SP_ELX (0x6U) +#define SERROR_SP_ELX (0x7U) +#define SYNC_AARCH64 (0x8U) +#define IRQ_AARCH64 (0x9U) +#define FIQ_AARCH64 (0xAU) +#define SERROR_AARCH64 (0xBU) +#define SYNC_AARCH32 (0xCU) +#define IRQ_AARCH32 (0xDU) +#define FIQ_AARCH32 (0xEU) +#define SERROR_AARCH32 (0xFU) + + .global loader_exceptions + .global SyncSP0 + .global IrqSP0 + .global FiqSP0 + .global SErrorSP0 + .global SyncSPx + .global IrqSPx + .global FiqSPx + .global SErrorSPx + .global SyncA64 + .global IrqA64 + .global FiqA64 + .global SErrorA64 + .global SyncA32 + .global IrqA32 + .global FiqA32 + .global SErrorA32 + + /* Pre macro for a vector */ + .macro bigin_vector label, section_name=.vectors + .cfi_sections .debug_frame + .section \section_name, "ax" + .align 7, 0 + .type \label, %function + .cfi_startproc + \label: + .endm + + /* Post macro for a vector */ + .macro end_vector label + .cfi_endproc + .fill \label + (32 * 4) - . + .endm + + +/*****************************************************************************/ +/* Exception Vector Table */ +/*****************************************************************************/ + .section .vectors, "ax" + .align 11, 0 + +loader_exceptions: + + /***********************/ + /* Current EL with SP0 */ + /***********************/ +bigin_vector SyncSP0 + mov x0, #SYNC_SP_EL0 + msr spsel, #0 + bl handler_error +end_vector SyncSP0 + +bigin_vector IrqSP0 + mov x0, #IRQ_SP_EL0 + msr spsel, #0 + bl handler_error +end_vector IrqSP0 + +bigin_vector FiqSP0 + mov x0, #FIQ_SP_EL0 + msr spsel, #0 + b handler_fiq +end_vector FiqSP0 + +bigin_vector SErrorSP0 + mov x0, #SERROR_SP_EL0 + msr spsel, #0 + bl handler_error +end_vector SErrorSP0 + + /***********************/ + /* Current EL with SPx */ + /***********************/ +bigin_vector SyncSPx + mov x0, #SYNC_SP_ELX + msr spsel, #0 + bl handler_error +end_vector SyncSPx + +bigin_vector IrqSPx + mov x0, #IRQ_SP_ELX + msr spsel, #0 + bl handler_error +end_vector IrqSPx + +bigin_vector FiqSPx + mov x0, #FIQ_SP_ELX + msr spsel, #0 + bl handler_error +end_vector FiqSPx + +bigin_vector SErrorSPx + mov x0, #SERROR_SP_ELX + msr spsel, #0 + bl handler_error +end_vector SErrorSPx + + /**************************/ + /* Lower EL using AArch64 */ + /**************************/ +bigin_vector SyncA64 + mov x0, #SYNC_AARCH64 + msr spsel, #0 + bl handler_error +end_vector SyncA64 + +bigin_vector IrqA64 + mov x0, #IRQ_AARCH64 + msr spsel, #0 + bl handler_error +end_vector IrqA64 + +bigin_vector FiqA64 + mov x0, #FIQ_AARCH64 + msr spsel, #0 + bl handler_error +end_vector FiqA64 + +bigin_vector SErrorA64 + mov x0, #SERROR_AARCH64 + msr spsel, #0 + bl handler_error +end_vector SErrorA64 + + /**************************/ + /* Lower EL using AArch32 */ + /**************************/ +bigin_vector SyncA32 + mov x0, #SYNC_AARCH32 + msr spsel, #0 + bl handler_error +end_vector SyncA32 + +bigin_vector IrqA32 + mov x0, #IRQ_AARCH32 + msr spsel, #0 + bl handler_error +end_vector IrqA32 + +bigin_vector FiqA32 + mov x0, #FIQ_AARCH32 + msr spsel, #0 + bl handler_error +end_vector FiqA32 + +bigin_vector SErrorA32 + mov x0, #SERROR_AARCH32 + msr spsel, #0 + bl handler_error +end_vector SErrorA32 + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_main.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_main.c new file mode 100644 index 0000000..a02d3d1 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_main.c @@ -0,0 +1,479 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Loader main function + ******************************************************************************/ +/****************************************************************************** + * @file loader_main.c + * - Version : 0.17 + * @brief 1. IP initialization. + * 2. Transfer image. + * 3. Release of used resources. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 30.11.2021 0.01 First Release + * : 14.02.2022 0.02 Changed log output + * Added device version log output + * Removed Include in micro_wait.h + * Removed the parameter setting process to BL31 + * Removed LCS judgement + * Memory map change + * : 17.02.2022 0.03 Support AArch32 + * : 22.03.2022 0.04 Support for GSCE[5.4a, 5.4b],[10.3b] + * Support for coverity + * cid:3430806, 3307617, 3430797 + * Changed comment + * : 10.05.2022 0.05 Integrated processing + * Changed to processing for each device + * Change log output + * Add argument of load_init() + * : 16.06.2022 0.06 Change log output + * Support secure boot for S4 + * : 31.10.2022 0.07 License notation change. + * : 07.11.2022 0.08 Added the parameter setting process to BL31 + * Added DDR initialization/QOS initialization + * : 07.12.2022 0.09 Warning support when log output is disabled + * : 15.12.2022 0.10 Support RegionID check + * : 04.04.2023 0.11 Removed stdio.h. + * : 21.08.2023 0.12 Add support for V4M. + * : 23.01.2024 0.13 Add calling of ram_protection_check function. + * Move calling of final_hash_cmp function. + * : 10.09.2024 0.14 Updated Region ID and RAM protection setting + * for QNX. + * : 11.10.2024 0.15 Updated Region ID and RAM protection setting + * for QNX for V4M. + * : 19.12.2024 0.16 Add loading RTOS#1 and RTOS#2 process. + * Add calling ecm_error_enable() function. + * : 26.05.2025 0.17 Add argument of OP-TEE boot address to + * smoni_set_param function. +*****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#include "cpu_on.h" +#include "qos.h" +#include "rtvram.h" +#include "loader_main_common.h" +#include "../ip/ddr/boot_init_dram.h" +#include "access_protection.h" +#if (ECC_ENABLE == 1) +#if (RCAR_LSI == RCAR_V4H) +#include "../ip/ddr/v4h/lpddr5/ecc_enable_v4h.h" +#elif (RCAR_LSI == RCAR_V4M) +#include "../ip/ddr/v4m/lpddr5/ecc_enable_v4m.h" +#endif /* RCAR_LSI == RCAR_V4H */ +#endif /* ECC_ENABLE == 1 */ +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ +#if (BOOT_MODE == SECURE) +#include "secure_boot.h" +#endif /* BOOT_MODE == SECURE */ +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +#include "axmm_register.h" +#include "ram_protection.h" +#endif +#if (ECM_ERROR_ENABLE == 1) +#if (RCAR_LSI == RCAR_V4H) +#include "../ip/ddr/v4h/lpddr5/ecm_enable_v4h.h" +#elif (RCAR_LSI == RCAR_V4M) +#include "../ip/ddr/v4m/lpddr5/ecm_enable_v4m.h" +#endif /* RCAR_LSI == RCAR_V4H */ +#endif /* ECM_ERROR_ENABLE == 1 */ + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +#define AXMM_DPTSECCR_NUM (SDRAM_PROTECT_AREA) /* set 0 to 15 */ +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) +#define AXMM_DPTSECCR_NUM2 (SDRAM_PROTECT_AREA2) /* set 0 to 15 */ +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ + +#define AXMM_DPTSECCR_SECGRP_MASK (0x00000F00U) +#define AXMM_DPTSECCR_SECGRP_SEC (0x00000400U) +#define AXMM_DPTSECCR_SECGWP_MASK (0x0000000FU) +#define AXMM_DPTSECCR_SECGWP_SEC (0x00000004U) + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +#define DPTRGNCR_PROTECT_AREA (3U) +#define DPTRGNCR_LINUX_AREA (6U) +#else +#define DPTRGNCR_PROTECT_AREA (4U) +#define DPTRGNCR_LINUX_AREA (9U) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#define SECCTRWD_AREA0 (0U) +#define SECCTRWD_AREA2 (2U) + +#define AXMM_DPTRGNCR_RGN0RP_MASK (0x00010000U) +#define AXMM_DPTRGNCR_RGN0RP (0x00010000U) +#define AXMM_DPTRGNCR_RGN0WP_MASK (0x00000001U) +#define AXMM_DPTRGNCR_RGN0WP (0x00000001U) +#define SECCTRWD_SAFG15WP_MASK (0x00000005U) +#define SECCTRWD_SAFG15WP (0x00000005U) + +static void remove_rgid0_previlege(void); +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +static void sdram_protection(uint32_t num); +#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ + +uint32_t loader_main(void) +{ + uint32_t ca_load_num; /* number of load for CA program */ + uint32_t loop; + uint32_t reg; /* store register value */ + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + int32_t result; /* store result of ddr_init() */ +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + + __attribute__((unused))const char *str; +#if (RCAR_LSI == RCAR_S4) + const char *product_s4 = "S4"; +#elif (RCAR_LSI == RCAR_V4H) + const char *product_v4h = "V4H"; +#elif (RCAR_LSI == RCAR_V4M) + const char *product_v4m = "V4M"; +#endif /* RCAR_LSI == RCAR_S4 */ + const char *unknown = "unknown"; +#if (BOOT_MODE == SECURE) + uint32_t bootmode; /* store boot mode */ +#endif /* BOOT_MODE == SECURE */ + + LOAD_INFO li[MAX_PLACED]; + +/***************************************************************************** + * Initialize Hardware + *****************************************************************************/ + /* IP initialize */ + ip_init(); + +/***************************************************************************** + * Output boot message + *****************************************************************************/ +#if (RCAR_LSI == RCAR_S4) + NOTICE("CA55 Loader Program Rev.%s\n", IPL_VERSION); +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + NOTICE("CR52 Loader Program Rev.%s\n", IPL_VERSION); +#endif /* RCAR_LSI == RCAR_S4 */ + + NOTICE("%s\n", build_message); + + /* Get PRR */ + reg = mem_read32(PRR); + switch (reg & PRR_PRODUCT_MASK) + { + #if (RCAR_LSI == RCAR_S4) + case PRR_PRODUCT_S4: + { + str = product_s4; + break; + } + #elif (RCAR_LSI == RCAR_V4H) + case PRR_PRODUCT_V4H: + { + str = product_v4h; + break; + } + #elif (RCAR_LSI == RCAR_V4M) + case PRR_PRODUCT_V4M: + { + str = product_v4m; + break; + } + #endif /* RCAR_LSI == RCAR_S4 */ + default: + { + str = unknown; + break; + } + } + NOTICE("PRR is R-Car %s Ver.%d.%d\n", str, + ((int)(reg & PRR_MAJOR_MASK) >> PRR_MAJOR_SHIFT) + + PRR_MAJOR_OFFSET, (int)(reg & PRR_MINOR_MASK)); + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + /* Notice the ecc enable */ + NOTICE("Access Protection Enable\n"); + #endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + +/***************************************************************************** + * Load Certficate + *****************************************************************************/ + + /* Load content certificate */ + ca_load_num = mem_read32(CONTENT_CERT_DEST_ADDR); + + /* Get load information */ + load_init(li, ca_load_num); + +/***************************************************************************** + * DDR Initialization + *****************************************************************************/ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + + /* DDR initialize */ + result = R_DRAM_Init(); + if (INITDRAM_OK != result) + { + ERROR("Failed to DRAM initialize (%d).\n", (int)result); + panic; + } + +#if (ECM_ERROR_ENABLE == 1) + ecm_error_enable(); +#endif /* ECM_ERROR_ENABLE == 1 */ + +#if (ECC_ENABLE == 1) + /* ECC Protection */ + ecc_sdram_enable(); +#endif /* ECC_ENABLE == 1 */ + + /* QoS configuration */ + qos_init(); + + /* RT-VRAM Extend mode */ + rtvram_extendmode(); +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + +#if (BOOT_MODE == SECURE) + secureboot_init(); + + /* LCS judgement for secure boot */ + bootmode = judge_bootmode(); + + if (NORMAL_BOOT != bootmode) + { + /* Content cert certification */ + secureboot_verify(li, ca_load_num); + } +#endif /* BOOT_MODE == SECURE */ + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/***************************************************************************** + * Load RTOS#2 + *****************************************************************************/ + /* Start loading RTOS#2 image */ + load_image(&li[RTOS2_ID]); + + #if (BOOT_MODE == SECURE) + /* Decryption image and Image cerfification */ + if (NORMAL_BOOT != bootmode) + { + secureboot_image(&li[RTOS2_ID]); + } + #endif /* BOOT_MODE == SECURE */ + + /* boot CR core2 */ + arm_cpu_on(RCAR_PWR_TARGET_CR2, li[RTOS2_ID].boot_addr); +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +/***************************************************************************** + * Load RTOS#0 + *****************************************************************************/ + /* Start loading RTOS#0 image */ + load_image(&li[RTOS_ID]); + + #if (BOOT_MODE == SECURE) + /* Decryption image and Image cerfification */ + if (NORMAL_BOOT != bootmode) + { + secureboot_image(&li[RTOS_ID]); + } + #endif /* BOOT_MODE == SECURE */ + + /* boot CR core0 */ + arm_cpu_on(RCAR_PWR_TARGET_CR, li[RTOS_ID].boot_addr); + +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + +/***************************************************************************** + * Load CA Program#2--#8 + *****************************************************************************/ + /* Start loading CA Program#n image */ + for (loop = 0U; loop < ca_load_num; loop++) + { + /* Loading start */ + load_image(&li[CA_OPTIONAL_ID + loop]); + +#if (BOOT_MODE == SECURE) + /* Decryption image and Image certification */ + if (NORMAL_BOOT != bootmode) + { + secureboot_image(&li[CA_OPTIONAL_ID + loop]); + } +#endif /* BOOT_MODE == SECURE */ + } + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + /* Set Secure Monitor parameter */ + #if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + smoni_set_param(li[CA_OPTIONAL_ID].boot_addr, /* BL31 */ + li[CA_OPTIONAL_ID + 1U].boot_addr); /* U-Boot */ + #else + smoni_set_param(li[CA_OPTIONAL_ID].boot_addr, /* BL31 */ + li[CA_OPTIONAL_ID + 1U].boot_addr, /* U-Boot */ + li[CA_OPTIONAL_ID + 2U].boot_addr); /* OP-TEE */ + #endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ + + /* Before Boot CPU, Set the division ratio for CPU operating frequency */ + adj_ca_variant_freq(); + +/* boot CA */ + arm_cpu_on(RCAR_PWR_TARGET_CA, li[CA_OPTIONAL_ID].boot_addr); + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/***************************************************************************** + * Load RTOS#1 + *****************************************************************************/ + /* Start loading RTOS#1 image */ + load_image(&li[RTOS1_ID]); + + #if (BOOT_MODE == SECURE) + /* Decryption image and Image cerfification */ + if (NORMAL_BOOT != bootmode) + { + secureboot_image(&li[RTOS1_ID]); + } + #endif /* BOOT_MODE == SECURE */ + +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + + #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + sdram_protection(AXMM_DPTSECCR_NUM); + #if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) + sdram_protection(AXMM_DPTSECCR_NUM2); + #endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ + remove_rgid0_previlege(); + /* + * SAN(Safety Application Note) 6.23.5 Operation + * Checker processor : + * Check RegionID/LifeC & memory area protection settings (including order & content of intermediate updates) + * done by ICUMX. + */ + rgid_protection_check(); + ram_protection_check(); + #endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ + + #if (BOOT_MODE == SECURE) + if (NORMAL_BOOT != bootmode) + { + /* Compare Hash verified at ICUMX IPL (V4H only). (Target images are Secure FW and Cx 2nd IPL.) */ + /* + * SAN(Safety Application Note) 6.23.5 Operation + * Checker processor : + * Re-do comparison of hash in Flash vs hash generated by ICUMX to confirm proper comparison. + */ + final_hash_cmp(); + } + #endif /* BOOT_MODE == SECURE */ + + NOTICE("Load finish.(CR52 Loader)\n"); + +#elif (RCAR_LSI == RCAR_S4) + #if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + sdram_protection(AXMM_DPTSECCR_NUM); + #endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ + NOTICE("Load finish.(CA55 Loader)\n"); +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + ip_release(); + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1) + return li[CA_OPTIONAL_ID].boot_addr; +#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + return li[RTOS1_ID].boot_addr; +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +} +/* End of function loader_main(void) */ + + +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) +static void sdram_protection(uint32_t num) +{ + uint32_t val; + uint32_t addr; + + /* Calculation of the address of the DPTSECCR register. */ + addr = (AXMM_DPTSECCR + (num * 4U)); + + val = mem_read32(addr); + val &= ~(AXMM_DPTSECCR_SECGRP_MASK | AXMM_DPTSECCR_SECGWP_MASK); + val |= (AXMM_DPTSECCR_SECGRP_SEC | AXMM_DPTSECCR_SECGWP_SEC); + mem_write32(addr, val); +}/* End of function void sdram_protection(void) */ + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +static void remove_rgid0_previlege(void) +{ + uint32_t val; + uint32_t addr; + + /* Calculation of the address of the DPTRGNCR register. */ + addr = get_dptrgncr_addr(DPTRGNCR_PROTECT_AREA); + + val = mem_read32(addr); + val &= ~(AXMM_DPTRGNCR_RGN0RP_MASK | AXMM_DPTRGNCR_RGN0WP_MASK); + val |= (AXMM_DPTRGNCR_RGN0RP| AXMM_DPTRGNCR_RGN0WP); /* Remove RGID0 read/write previlege on SDRAM Area. */ + mem_write32(addr, val); + + /* Calculation of the address of the DPTRGNCR register. */ + addr = get_dptrgncr_addr(DPTRGNCR_LINUX_AREA); + + val = mem_read32(addr); + val &= ~(AXMM_DPTRGNCR_RGN0RP_MASK | AXMM_DPTRGNCR_RGN0WP_MASK); + val |= (AXMM_DPTRGNCR_RGN0RP| AXMM_DPTRGNCR_RGN0WP); /* Remove RGID0 read/write previlege on SDRAM Area. */ + mem_write32(addr, val); + + /* Calculation of the address of the SECCTRW0D_1 register. */ + addr = get_rtvram1_secctrwd_addr(SECCTRWD_AREA0); + + val = mem_read32(addr); + val &= ~(SECCTRWD_SAFG15WP_MASK); + val |= SECCTRWD_SAFG15WP; /* Remove RGID0/2 write previlege on RT-VRAM1 Area0. */ + mem_write32(addr, val); + + /* Calculation of the address of the SECCTRW2D_1 register. */ + addr = get_rtvram1_secctrwd_addr(SECCTRWD_AREA2); + + val = mem_read32(addr); + val &= ~(SECCTRWD_SAFG15WP_MASK); + val |= SECCTRWD_SAFG15WP; /* Remove RGID0/2 write previlege on RT-VRAM1 Area2. */ + mem_write32(addr, val); +} +/* End of function void remove_rgid0_previlege(void) */ +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_main_common.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_main_common.c new file mode 100644 index 0000000..4b2e097 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_main_common.c @@ -0,0 +1,244 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2022-2025 Renesas Electronics Corporation All rights reserved. + *******************************************************************************/ + +/******************************************************************************* + * DESCRIPTION : Loader main common function + ******************************************************************************/ +/****************************************************************************** + * @file loader_main_common.c + * - Version : 0.05 + * @brief 1.Set BL31 parameter. + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 15.11.2022 0.01 First Release + * : 04.04.2023 0.02 Removed stdio.h. + * : 13.09.2024 0.03 Updated smoni_ep_info->ulpc_high to 0x20, + * smoni_ipl_param->pnonsecepinfo_high to 0x20. + * : 11.10.2024 0.04 Updated Region ID and RAM protection setting + * for QNX for V4M. + * : 26.05.2025 0.05 Added optee_ep_info parameter. + *****************************************************************************/ + +#include +#include +#include +#include +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#include "access_protection.h" +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + +#define SMONI_IPL_PARAM_OFFSET (0x00022200U) +#define SMONI_EP_INFO_OFFSET (SMONI_IPL_PARAM_OFFSET + 0x0030U) +#define OPTEE_EP_INFO_OFFSET (SMONI_IPL_PARAM_OFFSET + 0x0088U) +#define BL31_KIND_BOOT_ADDR (SMONI_IPL_PARAM_OFFSET + 0x0D00U) +#define BL31_COLD_BOOT (0x0000000000000000U) +#define BL31_WARM_BOOT (0x0000000000000001U) +#define SMONI_KIND_BOOT_PARAM (0xFFFFFFFFFFFFFFFFU) + +/* struct */ +typedef struct{ + uint8_t uctype; + uint8_t ucversion; + uint16_t ussize; + uint32_t uiattr; + uint32_t psecmonimageinfo_low; + uint32_t psecmonimageinfo_high; + uint32_t psecoptepinfo_low; + uint32_t psecoptepinfo_high; + uint32_t psecoptimageinfo_low; + uint32_t psecoptimageinfo_high; + uint32_t pnonsecepinfo_low; + uint32_t pnonsecepinfo_high; + uint32_t pnonsecimageinfo_low; + uint32_t pnonsecimageinfo_high; +}st_smoni_iplparams_t; + +typedef struct{ + uint8_t uctype; + uint8_t ucversion; + uint16_t ussize; + uint32_t uiattr; + uint32_t ulpc_low; + uint32_t ulpc_high; + uint32_t ulspsr_low; + uint32_t ulspsr_high; + uint32_t ularg0_low; + uint32_t ularg0_high; + uint32_t ularg1_low; + uint32_t ularg1_high; + uint32_t ularg2_low; + uint32_t ularg2_high; + uint32_t ularg3_low; + uint32_t ularg3_high; + uint32_t ularg4_low; + uint32_t ularg4_high; + uint32_t ularg5_low; + uint32_t ularg5_high; + uint32_t ularg6_low; + uint32_t ularg6_high; + uint32_t ularg7_low; + uint32_t ularg7_high; +}st_smoni_entrypointinfo_t; + +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) +void smoni_set_param(uint32_t smoni_entry_point, + uint32_t uboot_entry_point) +#else +void smoni_set_param(uint32_t smoni_entry_point, + uint32_t uboot_entry_point, + uint32_t tee_entry_point) +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +{ + st_smoni_iplparams_t *smoni_ipl_param; + st_smoni_entrypointinfo_t *smoni_ep_info; +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) + st_smoni_entrypointinfo_t *optee_ep_info; +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ + + /* set struct address */ + smoni_ipl_param = (st_smoni_iplparams_t *) + (smoni_entry_point + SMONI_IPL_PARAM_OFFSET); + smoni_ep_info = (st_smoni_entrypointinfo_t *) + (smoni_entry_point + SMONI_EP_INFO_OFFSET); +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) + optee_ep_info = (st_smoni_entrypointinfo_t *) + (smoni_entry_point + OPTEE_EP_INFO_OFFSET); +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ + + /* set parameter */ + smoni_ipl_param->uctype = 0x03U; + smoni_ipl_param->ucversion = 0x01U; + smoni_ipl_param->ussize = 0x0030U; + smoni_ipl_param->uiattr = 0x00000000U; + smoni_ipl_param->psecmonimageinfo_low = 0x00000000U; + smoni_ipl_param->psecmonimageinfo_high = 0x00000000U; +#if (OPTEE_LOAD_ENABLE == OPTEE_DISABLE) + smoni_ipl_param->psecoptepinfo_low = 0x00000000U; +#else + smoni_ipl_param->psecoptepinfo_low = (uint32_t)optee_ep_info; +#endif /* OPTEE_LOAD_ENABLE == OPTEE_DISABLE */ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + smoni_ipl_param->psecoptepinfo_high = 0x00000020U; /* OP-TEE entry point information 0x20_46422288 */ +#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE) + smoni_ipl_param->psecoptepinfo_high = 0x00000000U; +#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ +#else + smoni_ipl_param->psecoptepinfo_high = 0x00000000U; +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + smoni_ipl_param->psecoptimageinfo_low = 0x00000000U; + smoni_ipl_param->psecoptimageinfo_high = 0x00000000U; + smoni_ipl_param->pnonsecepinfo_low = (uint32_t)smoni_ep_info; +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + smoni_ipl_param->pnonsecepinfo_high = 0x00000020U; /* Secure monitor entry point 0x20_46400000 */ +#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE) + smoni_ipl_param->pnonsecepinfo_high = 0x00000000U; +#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ +#else + smoni_ipl_param->pnonsecepinfo_high = 0x00000000U; +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + smoni_ipl_param->pnonsecimageinfo_low = 0x00000000U; + smoni_ipl_param->pnonsecimageinfo_high = 0x00000000U; + + smoni_ep_info->uctype = 0x01U; + smoni_ep_info->ucversion = 0x01U; + smoni_ep_info->ussize = 0x0058U; /* structure size */ + smoni_ep_info->uiattr = 0x00000001U; /* SECURE */ + smoni_ep_info->ulpc_low = uboot_entry_point; +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + smoni_ep_info->ulpc_high = 0x00000020U; /* U-boot entry point 0x20_50000000 */ +#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE) + smoni_ep_info->ulpc_high = 0x00000000U; +#endif +#else + smoni_ep_info->ulpc_high = 0x00000000U; +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + /* SPSR_EL3.E[9] = b1 (BigEndian) * + * .A[8] = b1 (DataAbort MASK) * + * .I[7] = b1 (IRQ MASK) * + * .F[6] = b1 (FIQ MASK) * + * .M[4] = b0 (AArcch64) * + * .M[3:1] = b0101 (EL1h) */ + smoni_ep_info->ulspsr_low = 0x000003C5U; + smoni_ep_info->ulspsr_high = 0x00000000U; + smoni_ep_info->ularg0_low = 0x00000000U; + smoni_ep_info->ularg0_high = 0x00000000U; + smoni_ep_info->ularg1_low = 0x00000000U; + smoni_ep_info->ularg1_high = 0x00000000U; + smoni_ep_info->ularg2_low = 0x00000000U; + smoni_ep_info->ularg2_high = 0x00000000U; + smoni_ep_info->ularg3_low = 0x00000000U; + smoni_ep_info->ularg3_high = 0x00000000U; + smoni_ep_info->ularg4_low = 0x00000000U; + smoni_ep_info->ularg4_high = 0x00000000U; + smoni_ep_info->ularg5_low = 0x00000000U; + smoni_ep_info->ularg5_high = 0x00000000U; + smoni_ep_info->ularg6_low = 0x00000000U; + smoni_ep_info->ularg6_high = 0x00000000U; + smoni_ep_info->ularg7_low = 0x00000000U; + smoni_ep_info->ularg7_high = 0x00000000U; + +#if (OPTEE_LOAD_ENABLE == OPTEE_ENABLE) + optee_ep_info->uctype = 0x01U; + optee_ep_info->ucversion = 0x02U; + optee_ep_info->ussize = 0x0058U; + optee_ep_info->uiattr = 0x00000008U; + optee_ep_info->ulpc_low = tee_entry_point; +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) +#if (ACC_PROT_ENABLE == PROTECTION_ENABLE) + optee_ep_info->ulpc_high = 0x00000020U; /* OP-TEE entry point 0x20_44100000 */ +#elif (ACC_PROT_ENABLE == PROTECTION_DISABLE) + optee_ep_info->ulpc_high = 0x00000000U; +#endif /* ACC_PROT_ENABLE == PROTECTION_ENABLE */ +#else + optee_ep_info->ulpc_high = 0x00000000U; +#endif /* ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) */ + optee_ep_info->ulspsr_low = 0x000003C5U; + optee_ep_info->ulspsr_high = 0x00000000U; + optee_ep_info->ularg0_low = 0x00000000U; + optee_ep_info->ularg0_high = 0x00000000U; + optee_ep_info->ularg1_low = 0x00000000U; + optee_ep_info->ularg1_high = 0x00000000U; + optee_ep_info->ularg2_low = 0x00000000U; + optee_ep_info->ularg2_high = 0x00000000U; + optee_ep_info->ularg3_low = 0x00000000U; + optee_ep_info->ularg3_high = 0x00000000U; + optee_ep_info->ularg4_low = 0x00000000U; + optee_ep_info->ularg4_high = 0x00000000U; + optee_ep_info->ularg5_low = 0x00000000U; + optee_ep_info->ularg5_high = 0x00000000U; + optee_ep_info->ularg6_low = 0x00000000U; + optee_ep_info->ularg6_high = 0x00000000U; + optee_ep_info->ularg7_low = 0x00000000U; + optee_ep_info->ularg7_high = 0x00000000U; +#endif /* OPTEE_LOAD_ENABLE == OPTEE_ENABLE */ + + smoni_entry_point += BL31_KIND_BOOT_ADDR; + mem_write32((smoni_entry_point), (uint32_t)((uint64_t)BL31_COLD_BOOT & 0xFFFFFFFFU)); + mem_write32(((smoni_entry_point) + 0x4U), + (uint32_t)(((uint64_t)BL31_COLD_BOOT >> 32U) & 0xFFFFFFFFU)); +} +/* End of function smoni_set_param(uint32_t smoni_entry_point) */ diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_mmu_table.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_mmu_table.c new file mode 100644 index 0000000..156212f --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_mmu_table.c @@ -0,0 +1,1086 @@ +/******************************************************************************* + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only + * intended for use with Renesas products. No other uses are authorized. This + * software is owned by Renesas Electronics Corporation and is protected under + * all applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT + * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE + * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. + * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS + * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE + * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR + * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software + * and to discontinue the availability of this software. By using this software, + * you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + +/******************************************************************************* + * DESCRIPTION : MMU Setting table level1 + ******************************************************************************/ +/****************************************************************************** + * @file loader_mmu_table1.c + * - Version : 0.02 + * @brief MMU setting table No.1. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 14.12.2022 0.01 First Release + * : 13.02.2023 0.02 Modify each table to be fixed address. + *****************************************************************************/ +#include /* for uint32_t */ +#include +#include "loader_mmu_table.h" + +/* Must match with MMU_LV2_STAT defined in loader_s4.ld. */ +#define MMU_TBL_ADDR (0xE6311000U) +/* Must match with MMU_LV3_STAT defined in loader_s4.ld. */ +#define MMU_TBL_SYSRAM_ADDR (0xE6310000U) + +const uint64_t g_loader_level3_table[] __attribute__ ((aligned (4096))) __attribute__ ((section(".lv3_tbl"))) = +{ + 0x00000000E6200000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6201000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6202000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6203000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6204000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6205000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6206000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6207000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6208000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6209000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E620A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E620B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E620C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E620D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E620E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E620F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6210000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6211000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6212000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6213000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6214000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6215000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6216000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6217000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6218000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6219000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E621A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E621B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E621C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E621D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E621E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E621F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6220000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6221000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6222000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6223000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6224000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6225000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6226000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6227000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6228000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6229000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E622A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E622B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E622C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E622D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E622E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E622F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6230000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6231000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6232000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6233000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6234000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6235000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6236000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6237000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6238000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6239000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E623A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E623B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E623C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E623D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E623E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E623F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6240000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6241000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6242000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6243000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6244000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6245000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6246000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6247000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6248000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6249000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E624A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E624B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E624C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E624D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E624E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E624F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6250000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6251000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6252000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6253000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6254000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6255000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6256000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6257000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6258000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6259000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E625A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E625B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E625C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E625D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E625E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E625F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6260000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6261000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6262000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6263000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6264000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6265000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6266000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6267000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6268000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6269000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E626A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E626B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E626C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E626D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E626E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E626F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6270000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6271000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6272000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6273000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6274000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6275000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6276000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6277000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6278000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6279000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E627A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E627B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E627C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E627D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E627E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E627F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6280000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6281000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6282000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6283000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6284000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6285000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6286000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6287000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6288000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6289000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E628A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E628B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E628C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E628D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E628E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E628F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6290000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6291000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6292000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6293000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6294000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6295000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6296000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6297000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6298000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6299000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E629A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E629B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E629C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E629D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E629E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E629F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62A9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62AA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62AB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62AC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62AD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62AE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62AF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62B9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62BA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62BB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62BC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62BD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62BE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62BF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62C9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62CA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62CB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62CC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62CD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62CE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62CF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62D9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62DA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62DB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62DC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62DD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62DE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62DF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62E9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62EA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62EB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62EC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62ED000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62EE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62EF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62F9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62FA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62FB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62FC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62FD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62FE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E62FF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6300000U | MMU_TBL_PAGE_EXECREAD_MEMORY, /* SystemRAM Start */ + 0x00000000E6301000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6302000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6303000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6304000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6305000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6306000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6307000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6308000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6309000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E630A000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E630B000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E630C000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E630D000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E630E000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E630F000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6310000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6311000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6312000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6313000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6314000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6315000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6316000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6317000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6318000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6319000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E631A000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E631B000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E631C000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E631D000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E631E000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E631F000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6320000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6321000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6322000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6323000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6324000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6325000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6326000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6327000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6328000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6329000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E632A000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E632B000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E632C000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E632D000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E632E000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E632F000U | MMU_TBL_PAGE_EXECREAD_MEMORY, + 0x00000000E6330000U | MMU_TBL_PAGE_NOEXEC_MEMORY, /* SystemRAM (.bss) */ + 0x00000000E6331000U | MMU_TBL_PAGE_NOEXEC_MEMORY, /* SystemRAM (.stack) */ + 0x00000000E6332000U | MMU_TBL_PAGE_NOEXEC_MEMORY, /* SystemRAM (.stack) */ + 0x00000000E6333000U | MMU_TBL_PAGE_NOEXEC_MEMORY, /* SystemRAM (Reserved) Start */ + 0x00000000E6334000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6335000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6336000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6337000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6338000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6339000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E633A000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E633B000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E633C000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E633D000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E633E000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E633F000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6340000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6341000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6342000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6343000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6344000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6345000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6346000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6347000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6348000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6349000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E634A000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E634B000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E634C000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E634D000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E634E000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E634F000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6350000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6351000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6352000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6353000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6354000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6355000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6356000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6357000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6358000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E6359000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E635A000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E635B000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E635C000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E635D000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E635E000U | MMU_TBL_PAGE_NOEXEC_MEMORY, + 0x00000000E635F000U | MMU_TBL_PAGE_NOEXEC_MEMORY, /* SystemRAM (Reserved) End */ + 0x00000000E6360000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6361000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6362000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6363000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6364000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6365000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6366000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6367000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6368000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6369000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E636A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E636B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E636C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E636D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E636E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E636F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6370000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6371000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6372000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6373000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6374000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6375000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6376000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6377000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6378000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6379000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E637A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E637B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E637C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E637D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E637E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E637F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6380000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6381000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6382000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6383000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6384000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6385000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6386000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6387000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6388000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6389000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E638A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E638B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E638C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E638D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E638E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E638F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6390000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6391000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6392000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6393000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6394000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6395000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6396000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6397000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6398000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E6399000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E639A000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E639B000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E639C000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E639D000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E639E000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E639F000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63A9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63AA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63AB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63AC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63AD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63AE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63AF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63B9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63BA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63BB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63BC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63BD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63BE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63BF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63C9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63CA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63CB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63CC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63CD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63CE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63CF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63D9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63DA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63DB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63DC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63DD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63DE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63DF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63EA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63EB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63EC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63ED000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63EE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63EF000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F0000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F1000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F2000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F3000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F4000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63E5000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F6000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F7000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F8000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63F9000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63FA000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63FB000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63FC000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63FD000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63FE000U | MMU_TBL_PAGE_NOEXEC_DEVICE, + 0x00000000E63FF000U | MMU_TBL_PAGE_NOEXEC_DEVICE +}; + +const uint64_t g_loader_level2_table[] __attribute__ ((aligned (4096))) __attribute__ ((section(".lv2_tbl"))) = +{ + 0x00000000C0000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C0200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C0400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C0600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C0800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C0A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C0C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C0E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C1E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C2E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C3E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C4E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C5E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C6E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C7E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C8E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000C9E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CA000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CA200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CA400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CA600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CA800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CAA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CAC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CAE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CB000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CB200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CB400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CB600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CB800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CBA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CBC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CBE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CC000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CC200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CC400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CC600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CC800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CCA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CCC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CCE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CD000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CD200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CD400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CD600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CD800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CDA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CDC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CDE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CE000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CE200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CE400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CE600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CE800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CEA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CEC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CEE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CF000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CF200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CF400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CF600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CF800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CFA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CFC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000CFE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D0E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D1E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D2E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D3E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D4E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D5E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D6E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D7E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D8E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000D9E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DA000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DA200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DA400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DA600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DA800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DAA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DAC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DAE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DB000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DB200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DB400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DB600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DB800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DBA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DBC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DBE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DC000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DC200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DC400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DC600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DC800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DCA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DCC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DCE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DD000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DD200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DD400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DD600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DD800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DDA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DDC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DDE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DE000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DE200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DE400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DE600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DE800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DEA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DEC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DEE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DF000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DF200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DF400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DF600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DF800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DFA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DFC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000DFE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E0E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E1E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E2000000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, /* RT-VRAM Start */ + 0x00000000E2200000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E2400000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E2600000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E2800000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E2A00000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E2C00000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E2E00000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E3000000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E3200000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E3400000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E3600000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E3800000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x00000000E3A00000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, /* RT-VRAM End */ + 0x00000000E3C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E3E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E4E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E5E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E6000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + MMU_TBL_SYSRAM_ADDR | MMU_TBL_TYPE_TABLE, + 0x00000000E6400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E6600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E6800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E6A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E6C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E6E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E7E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E8E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000E9E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EA000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EA200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EA400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EA600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EA800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EAA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EAC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EAE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EB000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EB200000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, /* RT-SRAM Start-End (H'00 EB2FFFFF) */ + 0x00000000EB400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EB600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EB800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EBA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EBC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EBE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EC000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EC200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EC400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EC600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EC800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ECA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ECC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ECE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ED000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ED200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ED400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ED600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000ED800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EDA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EDC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EDE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EE000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EE200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EE400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EE600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EE800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EEA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EEC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EEE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EF000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EF200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EF400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EF600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EF800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EFA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EFC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000EFE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F0E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F1E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F2E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F3E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F4E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F5E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F6E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F7E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F8E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9A00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9C00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000F9E00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FA000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FA200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FA400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FA600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FA800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FAA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FAC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FAE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FB000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FB200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FB400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FB600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FB800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FBA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FBC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FBE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FC000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FC200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FC400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FC600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FC800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FCA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FCC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FCE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FD000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FD200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FD400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FD600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FD800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FDA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FDC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FDE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FE000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FE200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FE400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FE600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FE800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FEA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FEC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FEE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FF000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FF200000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FF400000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FF600000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FF800000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FFA00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FFC00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x00000000FFE00000U | MMU_TBL_BLOCK_NOEXEC_DEVICE +}; + +const uint64_t g_loader_level1_table[] __attribute__ ((aligned (32))) __attribute__ ((section(".lv1_tbl"))) = +{ + 0x0000000000000000U | MMU_TBL_BLOCK_NOEXEC_DEVICE, + 0x0000000040000000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + 0x0000000080000000U | MMU_TBL_BLOCK_NOEXEC_MEMORY, + MMU_TBL_ADDR | MMU_TBL_TYPE_TABLE +}; diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_s4.S b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_s4.S new file mode 100644 index 0000000..45c0ab3 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_s4.S @@ -0,0 +1,336 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file loader_s4.S + * - Version : 0.06 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 27.06.2022 0.02 Remove unused definitions + * : 02.08.2022 0.03 Support WDT + * : 31.10.2022 0.04 License notation change. + * : 14.12.2022 0.05 Support MMU + * : 17.02.2023 0.06 Modified instruction and General purpose + * register to lower case. + *****************************************************************************/ + +#include "asm_macros.S" + +/* SCTLR definitions */ +#define SCTLR_M_BIT (1 << 0) +#define SCTLR_A_BIT (1 << 1) +#define SCTLR_SA_BIT (1 << 3) +#define SCTLR_I_BIT (1 << 12) +#define SCTLR_WXN_BIT (1 << 19) +#define SCTLR_EE_BIT (1 << 25) +#define SCTLR_RESET_VAL (SCTLR_SA_BIT) +#define SCTLR_MMU_ON (SCTLR_M_BIT) +#define SCTLR_OFF ~(SCTLR_M_BIT | SCTLR_I_BIT | SCTLR_A_BIT) + +/* SCR definitions */ +#define SCR_RES1_BITS ((1 << 4) | (1 << 5)) +#define SCR_TWEDEL_SHIFT (30) +#define SCR_TWEDEL_MASK (0xf) +#define SCR_AMVOFFEN_BIT (1 << 35) +#define SCR_TWEDEn_BIT (1 << 29) +#define SCR_ECVEN_BIT (1 << 28) +#define SCR_FGTEN_BIT (1 << 27) +#define SCR_ATA_BIT (1 << 26) +#define SCR_FIEN_BIT (1 << 21) +#define SCR_EEL2_BIT (1 << 18) +#define SCR_API_BIT (1 << 17) +#define SCR_APK_BIT (1 << 16) +#define SCR_TERR_BIT (1 << 15) +#define SCR_TWE_BIT (1 << 13) +#define SCR_TWI_BIT (1 << 12) +#define SCR_ST_BIT (1 << 11) +#define SCR_RW_BIT (1 << 10) +#define SCR_SIF_BIT (1 << 9) +#define SCR_HCE_BIT (1 << 8) +#define SCR_SMD_BIT (1 << 7) +#define SCR_EA_BIT (1 << 3) +#define SCR_FIQ_BIT (1 << 2) +#define SCR_IRQ_BIT (1 << 1) +#define SCR_NS_BIT (1 << 0) +#define SCR_VALID_BIT_MASK (0x2f8f) +#define SCR_RESET_VAL SCR_RES1_BITS + +/* CPSR/SPSR definitions */ +#define DAIF_FIQ_BIT (1 << 0) +#define DAIF_IRQ_BIT (1 << 1) +#define DAIF_ABT_BIT (1 << 2) +#define DAIF_DBG_BIT (1 << 3) +#define SPSR_DAIF_SHIFT (6) +#define SPSR_DAIF_MASK (0xf) + +#define SPSR_AIF_SHIFT (6) +#define SPSR_AIF_MASK (0x7) + +#define SPSR_E_SHIFT (9) +#define SPSR_E_MASK (0x1) +#define SPSR_E_LITTLE (0x0) +#define SPSR_E_BIG (0x1) + +#define SPSR_T_SHIFT (5) +#define SPSR_T_MASK (0x1) +#define SPSR_T_ARM (0x0) +#define SPSR_T_THUMB (0x1) + +#define SPSR_M_SHIFT (4) +#define SPSR_M_MASK (0x1) +#define SPSR_M_AARCH64 (0x0) +#define SPSR_M_AARCH32 (0x1) + +#define SPSR_EL_SHIFT (2) +#define SPSR_EL_WIDTH (2) + +/* TCR definitions */ +#define TCR_BIT31_RES1 (1 << 31) +#define TCR_BIT23_RES1 (1 << 23) +#define TCR_PS (0 << 16) +#define TCR_TG0 (0 << 14) +#define TCR_SH0 (3 << 12) +#define TCR_ORGN0 (3 << 10) +#define TCR_IRGN0 (3 << 8) +#define TCR_T0SZ (32 << 0) + +#define TCR_VAL \ + (TCR_BIT31_RES1 | TCR_BIT23_RES1 | TCR_PS | TCR_TG0 | TCR_SH0 | TCR_ORGN0 | TCR_IRGN0 | TCR_T0SZ) + +/* MAIR definitions */ +#define MAIR_ATTR0 (0x00 << 0) /* Device-nGnRnE memory */ +#define MAIR_ATTR1 (0x4A << 8) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */ +#define MAIR_ATTR2 (0x44 << 16) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */ +#define MAIR_ATTR3 (0x00 << 24) +#define MAIR_ATTR4 (0x00 << 32) +#define MAIR_ATTR5 (0x00 << 40) +#define MAIR_ATTR6 (0x00 << 48) +#define MAIR_ATTR7 (0x00 << 56) + +#define MAIR_VAL \ + (MAIR_ATTR7 | MAIR_ATTR6 | MAIR_ATTR5 | MAIR_ATTR4 | MAIR_ATTR3 | MAIR_ATTR2 | MAIR_ATTR1 | MAIR_ATTR0) +#define MAIR_INIT_VAL (0x44E048E000098AA4) + +#define BIT_64Cx(nr) (1 << (nr)) +#define SPSR_SSBS_BIT_AARCH64 BIT_64Cx(12) +#define SPSR_SSBS_BIT_AARCH32 BIT_64Cx(23) + +#define DISABLE_ALL_EXCEPTIONS \ + (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) + +#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) +#define MODE_RW_SHIFT (0x4) +#define MODE_SP_MASK (0x1) +#define MODE_SP_SHIFT (0x0) +#define MODE_EL_MASK (0x3) +#define MODE_EL_SHIFT (0x2) +#define MODE_EL3 (0x3) + +#define MODE_RW_64 (0x0) +#define MODE_SP_ELX (0x1) + +#define SPSR_64 (((MODE_RW_64 << MODE_RW_SHIFT) | \ +((MODE_EL3 & MODE_EL_MASK) << MODE_EL_SHIFT) | \ +((MODE_SP_ELX & MODE_SP_MASK) << MODE_SP_SHIFT) | \ +((DISABLE_ALL_EXCEPTIONS & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ +(~(SPSR_SSBS_BIT_AARCH64))) + + + .global Startup + +/***************************************************************************** + * Reset Hander + *****************************************************************************/ +Startup: + /* initialize registers*/ + ldr x0, =0 + ldr x1, =0 + ldr x2, =0 + ldr x3, =0 + ldr x4, =0 + ldr x5, =0 + ldr x6, =0 + ldr x7, =0 + ldr x8, =0 + ldr x9, =0 + ldr x10, =0 + ldr x11, =0 + ldr x12, =0 + ldr x13, =0 + ldr x14, =0 + ldr x15, =0 + ldr x16, =0 + ldr x17, =0 + ldr x18, =0 + ldr x19, =0 + ldr x20, =0 + ldr x21, =0 + ldr x22, =0 + ldr x23, =0 + ldr x24, =0 + ldr x25, =0 + ldr x26, =0 + ldr x27, =0 + ldr x28, =0 + ldr x29, =0 + ldr x30, =0 + + ldr x0, =__STACKS_END__ + + mrs x1, sctlr_el3 + mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \ + | SCTLR_SA_BIT | SCTLR_A_BIT)) + orr x0, x0, x1 + msr sctlr_el3, x0 + isb + + mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) + mrs x0, sctlr_el3 + orr x0, x0, x1 + msr sctlr_el3, x0 + isb + + mrs x1, scr_el3 + mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT | SCR_FIQ_BIT ) \ + & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT)) + orr x0, x0, x1 + msr scr_el3, x0 + + /* --------------------------------------------------------------------- + * Set the exception vectors. + * --------------------------------------------------------------------- + */ + adr x0, loader_exceptions + msr vbar_el3, x0 + isb + + msr daifclr, #(DAIF_ABT_BIT | DAIF_FIQ_BIT) + + /* --------------------------------------------------------------------- + * Set the MMU table. + * --------------------------------------------------------------------- + */ + ldr x0 ,=TCR_VAL + msr tcr_el3, x0 + + ldr x0, =MAIR_VAL + msr mair_el3, x0 + + ldr x0, =g_loader_level1_table + msr ttbr0_el3, x0 + + /* --------------------------------------------------------------------- + * Enable MMU. + * --------------------------------------------------------------------- + */ + + isb + tlbi alle3 + isb + + mrs x0, sctlr_el3 + ldr x1 ,=SCTLR_MMU_ON + orr x0, x0, x1 + msr sctlr_el3, x0 + + dsb sy + isb + tlbi alle3 + isb + + /* clear bss section */ + mov x0, #0x0 + ldr x1, =__BSS_START__ + ldr x2, =__BSS_SIZE__ +bss_loop: + subs x2, x2, #4 + bcc bss_end + str w0, [x1, x2] + b bss_loop +bss_end: + + /* copy data section */ + ldr x0, =__DATA_COPY_START__ + ldr x1, =__DATA_START__ + ldr x2, =__DATA_SIZE__ +data_loop: + subs x2, x2, #4 + bcc data_end + ldr w3, [x0, x2] + str w3, [x1, x2] + b data_loop +data_end: + + msr spsel, #0 + + ldr x0, =__STACKS_END__ + mov sp, x0 + + bl loader_main + + msr elr_el3, x0 + + mov x0, #SPSR_64 + msr spsr_el3, x0 + + /* --------------------------------------------------------------------- + * Disable MMU. + * --------------------------------------------------------------------- + */ + mrs x0, sctlr_el3 + ldr x1 ,=SCTLR_OFF + and x0, x0, x1 + msr sctlr_el3, x0 + + dsb sy + isb + tlbi alle3 + ic iallu + + /* --------------------------------------------------------------------- + * Set initial value. + * --------------------------------------------------------------------- + */ + msr ttbr0_el3, xzr + + ldr x0, =MAIR_INIT_VAL + msr mair_el3, x0 + + msr tcr_el3, xzr + + msr vbar_el3, xzr + isb + + eret + + + .end \ No newline at end of file diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_s4.ld b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_s4.ld new file mode 100644 index 0000000..3e0d894 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_s4.ld @@ -0,0 +1,140 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Loader linker directive + ******************************************************************************/ +/****************************************************************************** + * @file loader,ld + * - Version : 0.07 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 21.02.2022 0.02 Changed section name + * : 10.05.2022 0.03 Changed section name + * Added memory + * Change binary size to multiples of 16 + * : 20.06.2022 0.04 Support secure boot for S4 + * : 02.08.2022 0.05 Support WDT + * : 31.10.2022 0.06 License notation change. + * : 13.02.2023 0.07 Added sections for MMU table. + *****************************************************************************/ + +OUTPUT_FORMAT("elf64-littleaarch64") +OUTPUT_ARCH(aarch64) +ENTRY(Startup) + +MEMORY { + SYSRAM (rwxa): ORIGIN = 0xE6300000, LENGTH = 0x00030000 + + /* Must match with MMU_TBL_SYSRAM_ADDR defined in loader_mmu_table.c. */ + MMU_LV3_STAT (rwa): ORIGIN = 0xE6310000, LENGTH = 0x00001000 /* level3:4KiB */ + /* Must match with MMU_TBL_ADDR defined in loader_mmu_table.c. */ + MMU_LV2_STAT (rwa): ORIGIN = 0xE6311000, LENGTH = 0x00001000 /* level2:4KiB */ + MMU_LV1_STAT (rwa): ORIGIN = 0xE6312000, LENGTH = 0x00000100 /* level1:32byte */ + CXIPLDATA (rwa): ORIGIN = 0xE6330000, LENGTH = 0x00001000 + CXIPLSTACK (rwa): ORIGIN = 0xE6331000, LENGTH = 0x00002000 + SHARED_RAM (rwa): ORIGIN = 0x41C00000, LENGTH = 0x0000C000 + SHARED_SDRAM (rwa): ORIGIN = 0x41E00000, LENGTH = 0x00200000 +} + +SECTIONS +{ + .loader_start : { + __RO_START__ = .; + build/obj/loader/loader_s4.o(.text*) + . = NEXT(2048); + *(.vectors) + . = ALIGN(4096); + } > SYSRAM + + .loader_ro : { + *(.text*) + *(.rodata*) + . = ALIGN(8); + __CONST_START__ = .; + *(.constdata.CONFIG_DATA) + __RO_END_UNALIGNED__ = .; + . = NEXT(4096); + __RO_END__ = .; + __DATA_COPY_START__ = .; + } > SYSRAM + + .lv3_tbl : { + build/obj/loader/loader_mmu_table.o(.rodata) + } > MMU_LV3_STAT + + .lv2_tbl : { + build/obj/loader/loader_mmu_table.o(.rodata) + } > MMU_LV2_STAT + + .lv1_tbl : { + build/obj/loader/loader_mmu_table.o(.rodata) + } > MMU_LV1_STAT + + .data : { + __DATA_START__ = .; + *(.data*) + . = NEXT(16); + __DATA_END__ = .; + } > CXIPLDATA AT > SYSRAM + + __DATA_SIZE__ = SIZEOF(.data); + + stacks (NOLOAD) : ALIGN(16) { + __STACKS_START__ = .; + KEEP(*(Cx_loader_stack)) + __STACKS_END__ = .; + } > CXIPLSTACK + + .bss.SHARED_TOP : { + __SHARED_TOP_START__ = .; + *(.bss.SHARED_TOP) + *(.bss.SHARED_LCS) + *(.bss.SHARED_CMAC) + *(.bss.SHARED_HASH) + . = NEXT(0x00200000); + __SHARED__END__ = .; + } > SHARED_SDRAM + + .SHARED_RAM : { + __FWRAM_START__ = .; + . += 0; + . = NEXT(0x0000C000); + __FWRAM_END__ = .; + } > SHARED_RAM + + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } > CXIPLDATA + + __BSS_SIZE__ = SIZEOF(.bss); +} diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4h.S b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4h.S new file mode 100644 index 0000000..381b6e6 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4h.S @@ -0,0 +1,381 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file loader_v4h.S + * - Version : 0.07 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 17.02.2022 0.01 First Release + * : 09.05.2022 0.02 Removed the last nop instruction + * : 31.10.2022 0.03 License notation change. + * : 15.12.2022 0.04 V4H interrupt support. + * : 28.12.2022 0.05 MPU support. + * Address acquisition changes in interrupt handlers + * : 16.02.2023 0.06 Modified instruction to lower case. + * : 19.12.2024 0.07 Added the process that jump to RTOS#1. + *****************************************************************************/ + +/* SCTLR definitions */ +#define SCTLR_I (1 << 12) +#define SCTLR_M (1 << 0) + +/* MAIR definitions */ +#define MAIR_ATTR0 (0x00 << 0) /* Device-nGnRnE memory */ +#define MAIR_ATTR1 (0x4A << 8) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */ +#define MAIR_ATTR2 (0x44 << 16) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */ +#define MAIR_VAL (MAIR_ATTR2 | MAIR_ATTR1 | MAIR_ATTR0) + +#define SUP_EXCEPTION (0x2U) +#define HYP_EXCEPTION (0x5U) +#define IRQ_EXCEPTION (0x6U) +#define FIQ_EXCEPTION (0x7U) + +#define RTOS_LOAD_NUM_1 (1) /* RTOS is RTOS#0 only. */ +#define RTOS_LOAD_NUM_3 (3) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */ + + .global Startup + .global Vector + .global dabt_report_exception + .global pabt_report_exception + + .extern dabort_error + .extern pabort_error + .extern Undefined_error + .extern handler_error + + .align 5 + +Vector: + b Startup /* Reset */ + b Undefined_Handler /* Undefined Instruction */ + b Supervisor_Handler /* Supervisor Call */ + b Prefetch_Handler /* Prefetch Abort */ + b Abort_Handler /* Data Abort */ + b HypTrap_Handler /* Hyp Trap */ + b IRQ_Handler /* IRQ interrupt */ + b FIQ_Handler /* FIQ interrupt */ + +/***************************************************************************** + * Reset Hander + *****************************************************************************/ +Startup: +/* initialize registers*/ + /* initialize registers*/ + mov r0, #0 + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 + mov r8, #0 + mov r9, #0 + mov r10, #0 + mov r11, #0 + mov r12, #0 + mov lr, #0 + + ldr r13, =__STACKS_END__ + +/* Instruction cache enable */ + mrc p15, 4, r0, c1, c0, 0 /* HSCTLR */ + mrc p15, 0, r1, c1, c0, 0 /* SCTLR */ + bic r0, r0, #SCTLR_M /* M=0 */ + bic r1, r1, #SCTLR_M /* M=0 */ + orr r0, r0, #SCTLR_I /* I=1 */ + orr r1, r1, #SCTLR_I /* I=1 */ + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + mcr p15, 4, r0, c1, c0, 0 /* HSCTLR */ + mcr p15, 0, r1, c1, c0, 0 /* SCTLR */ + isb + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + isb + +/* CR52_CONFIGURE_MPU */ + mrc p15, 0, r0, c10, c2, 0 /* Read MAIR0 into R0 */ + mrc p15, 4, r1, c10, c2, 0 /* Read HMAIR0 into R1 */ + ldr r0, =MAIR_VAL /* Set MAIR */ + ldr r1, =MAIR_VAL /* Set MAIR */ + mcr p15, 0, r0, c10, c2, 0 /* Write R0 to MAIR0 */ + mcr p15, 4, r1, c10, c2, 0 /* Write R1 to HMAIR0 */ + +/* region 0: 0x00000000~0x3FFFFFFF */ + ldr r0, =0x00000006 /* SH=b'00/AP=b'11/XN=b'0 */ + ldr r1, =0x3FFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 0 /* Write R0 into PRBAR0 */ + mcr p15, 0, r1, c6, c8, 1 /* Write R1 into PRLAR0 */ + mcr p15, 4, r0, c6, c8, 0 /* Write R0 into HPRBAR0 */ + mcr p15, 4, r1, c6, c8, 1 /* Write R1 into HPRLAR0 */ +/* region 1: 0x40000000~0xBFFFFFFF */ + ldr r0, =0x40000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xBFFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 4 /* Write R0 into PRBAR1 */ + mcr p15, 0, r1, c6, c8, 5 /* Write R1 into PRLAR1 */ + mcr p15, 4, r0, c6, c8, 4 /* Write R0 into HPRBAR1 */ + mcr p15, 4, r1, c6, c8, 5 /* Write R1 into HPRLAR1 */ +/* region 2: 0xC0000000~0xE3FFFFFF */ + ldr r0, =0xC0000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE3FFFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c9, 0 /* Write R0 into PRBAR2 */ + mcr p15, 0, r1, c6, c9, 1 /* Write R1 into PRLAR2 */ + mcr p15, 4, r0, c6, c9, 0 /* Write R0 into HPRBAR2 */ + mcr p15, 4, r1, c6, c9, 1 /* Write R1 into HPRLAR2 */ +/* region 3: 0xE4000000~0xE4FFFFFF */ + ldr r0, =0xE4000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE4FFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c9, 4 /* Write R0 into PRBAR3 */ + mcr p15, 0, r1, c6, c9, 5 /* Write R1 into PRLAR3 */ + mcr p15, 4, r0, c6, c9, 4 /* Write R0 into HPRBAR3 */ + mcr p15, 4, r1, c6, c9, 5 /* Write R1 into HPRLAR3 */ +/* region 4: 0xE5000000~0xE62FFFFF */ + ldr r0, =0xE5000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE62FFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c10, 0 /* Write R0 into PRBAR4 */ + mcr p15, 0, r1, c6, c10, 1 /* Write R1 into PRLAR4 */ + mcr p15, 4, r0, c6, c10, 0 /* Write R0 into HPRBAR4 */ + mcr p15, 4, r1, c6, c10, 1 /* Write R1 into HPRLAR4 */ +/* region 5: 0xE6300000~0xE632FFFF */ + ldr r0, =0xE6300006 /* SH=b'00/AP=b'11/XN=b'0 */ + ldr r1, =0xE632FFC3 /* AttrIndx=1(Write-Through) */ + mcr p15, 0, r0, c6, c10, 4 /* Write R0 into PRBAR5 */ + mcr p15, 0, r1, c6, c10, 5 /* Write R1 into PRLAR5 */ + mcr p15, 4, r0, c6, c10, 4 /* Write R0 into HPRBAR5 */ + mcr p15, 4, r1, c6, c10, 5 /* Write R1 into HPRLAR5 */ +/* region 6: 0xE6330000~0xE635FFFF */ + ldr r0, =0xE6330003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE635FFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c11, 0 /* Write R0 into PRBAR6 */ + mcr p15, 0, r1, c6, c11, 1 /* Write R1 into PRLAR6 */ + mcr p15, 4, r0, c6, c11, 0 /* Write R0 into HPRBAR6 */ + mcr p15, 4, r1, c6, c11, 1 /* Write R1 into HPRLAR6 */ +/* region 7: 0xE6360000~0xEB1FFFFF */ + ldr r0, =0xE6360003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xEB1FFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c11, 4 /* Write R0 into PRBAR7 */ + mcr p15, 0, r1, c6, c11, 5 /* Write R1 into PRLAR7 */ + mcr p15, 4, r0, c6, c11, 4 /* Write R0 into HPRBAR7 */ + mcr p15, 4, r1, c6, c11, 5 /* Write R1 into HPRLAR7 */ +/* region 8: 0xEB200000~0xEB3FFFFF */ + ldr r0, =0xEB200003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xEB3FFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c12, 0 /* Write R0 into PRBAR8 */ + mcr p15, 0, r1, c6, c12, 1 /* Write R1 into PRLAR8 */ + mcr p15, 4, r0, c6, c12, 0 /* Write R0 into HPRBAR8 */ + mcr p15, 4, r1, c6, c12, 1 /* Write R1 into HPRLAR8 */ +/* region 9: 0xEB400000~0xFFFFFFFF */ + ldr r0, =0xEB400003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xFFFFFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c12, 4 /* Write R0 into PRBAR9 */ + mcr p15, 0, r1, c6, c12, 5 /* Write R1 into PRLAR9 */ + mcr p15, 4, r0, c6, c12, 4 /* Write R0 into HPRBAR9 */ + mcr p15, 4, r1, c6, c12, 5 /* Write R1 into HPRLAR9 */ + +/* CR52_SET_MPU_ON */ + mrc p15, 4, r0, c1, c0, 0 /* Read HSCTLR */ + mrc p15, 0, r1, c1, c0, 0 /* Read SCTLR */ + orr r0, r0, #SCTLR_M /* MPU enable */ + orr r1, r1, #SCTLR_M /* MPU enable */ + mcr p15, 4, r0, c1, c0, 0 /* Write HSCTLR */ + mcr p15, 0, r1, c1, c0, 0 /* Write SCTLR */ + isb + + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + isb + +/* Jump to physical address from mirror address */ + ldr r0, =JUMP_MAIN + bx r0 + +JUMP_MAIN: + ldr r0, =Vector + mcr p15, 4, r0, c12, c0, 0 /* HVBAR */ + +/* clear bss section */ + mov r0, #0x0 + ldr r1, =__BSS_START__ + ldr r2, =__BSS_SIZE__ +bss_loop: + subs r2, r2, #4 + bcc bss_end + str r0, [r1, +r2] + b bss_loop +bss_end: + +/* copy data section */ + ldr r0, =__DATA_COPY_START__ + ldr r1, =__DATA_START__ + ldr r2, =__DATA_SIZE__ +data_loop: + subs r2, r2, #4 + bcc data_end + ldr r3, [r0, +r2] + str r3, [r1, +r2] + b data_loop +data_end: + +/* Loader Main */ + bl loader_main + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* Keep return value from loader_main function (Boot address of RTOS#1) */ + mov r11, r0 +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* region 0: 0x00000000~0x3FFFFFFF */ + ldr r0, =0x00000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0x3FFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 0 /* Write R0 into PRBAR0 */ + mcr p15, 0, r1, c6, c8, 1 /* Write R1 into PRLAR0 */ + mcr p15, 4, r0, c6, c8, 0 /* Write R0 into HPRBAR0 */ + mcr p15, 4, r1, c6, c8, 1 /* Write R1 into HPRLAR0 */ +/* region 1: 0x40000000~0xBFFFFFFF */ + ldr r0, =0x40000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xBFFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 4 /* Write R0 into PRBAR1 */ + mcr p15, 0, r1, c6, c8, 5 /* Write R1 into PRLAR1 */ + mcr p15, 4, r0, c6, c8, 4 /* Write R0 into HPRBAR1 */ + mcr p15, 4, r1, c6, c8, 5 /* Write R1 into HPRLAR1 */ +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* region 2: 0xC0000000~0xE3FFFFFF */ +/* Change MPU setting for RTOS#1. */ + ldr r0, =0xC0000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE3FFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c9, 0 /* Write R0 into PRBAR2 */ + mcr p15, 0, r1, c6, c9, 1 /* Write R1 into PRLAR2 */ + mcr p15, 4, r0, c6, c9, 0 /* Write R0 into HPRBAR2 */ + mcr p15, 4, r1, c6, c9, 1 /* Write R1 into HPRLAR2 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +/* region 3: 0xE4000000~0xE4FFFFFF */ + ldr r0, =0xE4000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE4FFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c9, 4 /* Write R0 into PRBAR3 */ + mcr p15, 0, r1, c6, c9, 5 /* Write R1 into PRLAR3 */ + mcr p15, 4, r0, c6, c9, 4 /* Write R0 into HPRBAR3 */ + mcr p15, 4, r1, c6, c9, 5 /* Write R1 into HPRLAR3 */ +/* region 5: 0xE6300000~0xE632FFFF */ + ldr r0, =0xE6300002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE632FFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c10, 4 /* Write R0 into PRBAR5 */ + mcr p15, 0, r1, c6, c10, 5 /* Write R1 into PRLAR5 */ + mcr p15, 4, r0, c6, c10, 4 /* Write R0 into HPRBAR5 */ + mcr p15, 4, r1, c6, c10, 5 /* Write R0 into HPRLAR5 */ +/* region 6: 0xE6330000~0xE635FFFF */ + ldr r0, =0xE6330002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE635FFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c11, 0 /* Write R0 into PRBAR6 */ + mcr p15, 0, r1, c6, c11, 1 /* Write R1 into PRLAR6 */ + mcr p15, 4, r0, c6, c11, 0 /* Write R0 into HPRBAR6 */ + mcr p15, 4, r1, c6, c11, 1 /* Write R1 into HPRLAR6 */ +/* region 8: 0xEB200000~0xEB3FFFFF */ + ldr r0, =0xEB200002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xEB3FFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c12, 0 /* Write R0 into PRBAR8 */ + mcr p15, 0, r1, c6, c12, 1 /* Write R1 into PRLAR8 */ + mcr p15, 4, r0, c6, c12, 0 /* Write R0 into HPRBAR8 */ + mcr p15, 4, r1, c6, c12, 1 /* Write R1 into HPRLAR8 */ + + isb + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + isb + +/* Instruction cache disable */ + mrc p15, 4, r0, c1, c0, 0 /* Read HSCTLR */ + mrc p15, 0, r1, c1, c0, 0 /* Read SCTLR */ + bic r0, r0, #SCTLR_I /* I=0 */ + bic r1, r1, #SCTLR_I /* I=0 */ + mcr p15, 4, r0, c1, c0, 0 /* Write HSCTLR */ + mcr p15, 0, r1, c1, c0, 0 /* Write SCTLR */ + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + isb + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* Jump to RTOS#1 */ + bx r11 +#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1) +loader_end: + wfi + b loader_end +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +anker: + wfi + b anker + +/* Undefined Instruction */ +Undefined_Handler: + mrs r0, ELR_hyp + b Undefined_error + +/* Supervisor Call */ +Supervisor_Handler: + mov r0, #SUP_EXCEPTION + b handler_error + +/* Prefetch Abort */ +Prefetch_Handler: + b pabt_report_exception + +/* Data Abort */ +Abort_Handler: + mrs r0, ELR_hyp + b dabt_report_exception + +/* Hyp Trap */ +HypTrap_Handler: + mov r0, #HYP_EXCEPTION + b handler_error + +/*IRQ interrupt */ +IRQ_Handler: + mov r0, #IRQ_EXCEPTION + b handler_error + +/* FIQ interrupt */ +FIQ_Handler: + mov r0, #FIQ_EXCEPTION + b handler_error + +/******************************************************** + * abort exception + ********************************************************/ +dabt_report_exception: + mrc p15, 0, r1, c5, c0, 0 /* Read DFSR */ + mrc p15, 0, r2, c6, c0, 0 /* Read DFAR */ + b dabort_error + +pabt_report_exception: + mrc p15, 0, r0, c5, c0, 1 /* Read IFSR */ + mrc p15, 0, r1, c6, c0, 2 /* Read IFAR */ + b pabort_error + + .end diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4h.ld b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4h.ld new file mode 100644 index 0000000..d0f3c36 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4h.ld @@ -0,0 +1,137 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Loader linker directive + ******************************************************************************/ +/****************************************************************************** + * @file AArch32_loader,ld + * - Version : 0.05 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 17.02.2022 0.01 First Release + * : 21.02.2022 0.02 Changed section name + * : 10.05.2022 0.03 Changed section name + * Added memory + * Change binary size to multiples of 16 + * : 31.10.2022 0.04 License notation change. + * : 07.11.2022 0.05 Changed the size of CXIPLDATA. + * Added Qos settings assignment. + * : 15.12.2022 0.10 Support RegionID check + *****************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(Startup) + +MEMORY { + SYSRAM (rwxa): ORIGIN = 0xE6300000, LENGTH = 0x00030000 + CXIPLDATA (rwa): ORIGIN = 0xE6330000, LENGTH = 0x00003000 + CXIPLSTACK (rwa): ORIGIN = 0xE6333000, LENGTH = 0x00002000 + SHARED_RAM (rwa): ORIGIN = 0x41C00000, LENGTH = 0x0000C000 + SHARED_SDRAM (rwa): ORIGIN = 0x41E00000, LENGTH = 0x00200000 +} + +SECTIONS +{ + .loader_start : { + __RO_START__ = .; + build/obj/loader/loader_v4h.o(.text*) + . = NEXT(1024); + *(.vectors) + . = ALIGN(4096); + } > SYSRAM + + .loader_ro : { + *(.text*) + *(.rodata*) + . = ALIGN(8); + __CONST_START__ = .; + . = ALIGN(16); + *(.qoswt_tbl) + . = ALIGN(8); + *(.qosbw_tbl) + . = ALIGN(8); + *(.constdata.CONFIG_DATA) + . = ALIGN(8); + *(.rgid_w_tbl) + . = ALIGN(8); + *(.rgid_r_tbl) + . = ALIGN(8); + *(.rgid_m_tbl) + . = ALIGN(8); + *(.rgid_sec_tbl) + . = ALIGN(8); + *(.rgid_axi_tbl) + __RO_END_UNALIGNED__ = .; + . = NEXT(4096); + __RO_END__ = .; + __DATA_COPY_START__ = .; + } > SYSRAM + + .data : { + __DATA_START__ = .; + *(.data*) + . = NEXT(16); + __DATA_END__ = .; + } > CXIPLDATA AT > SYSRAM + + __DATA_SIZE__ = SIZEOF(.data); + + stacks (NOLOAD) : ALIGN(16) { + __STACKS_START__ = .; + KEEP(*(Cx_loader_stack)) + __STACKS_END__ = .; + } > CXIPLSTACK + + .bss.SHARED_TOP : { + __SHARED_TOP_START__ = .; + *(.bss.SHARED_TOP) + *(.bss.SHARED_LCS) + *(.bss.SHARED_CMAC) + *(.bss.SHARED_HASH) + . = NEXT(0x00200000); + __SHARED__END__ = .; + } > SHARED_SDRAM + + .SHARED_RAM : { + __FWRAM_START__ = .; + . += 0; + . = NEXT(0x0000C000); + __FWRAM_END__ = .; + } > SHARED_RAM + + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } > CXIPLDATA + + __BSS_SIZE__ = SIZEOF(.bss); +} diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4m.S b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4m.S new file mode 100644 index 0000000..5106219 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4m.S @@ -0,0 +1,375 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023-2024 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Image load function + ******************************************************************************/ +/****************************************************************************** + * @file loader_v4m.S + * - Version : 0.02 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + * : 19.12.2024 0.02 Added the process that jump to RTOS#1. + *****************************************************************************/ + +/* SCTLR definitions */ +#define SCTLR_I (1 << 12) +#define SCTLR_M (1 << 0) + +/* MAIR definitions */ +#define MAIR_ATTR0 (0x00 << 0) /* Device-nGnRnE memory */ +#define MAIR_ATTR1 (0x4A << 8) /* Normal memory, Outer Non-cacheable, Inner Write-Through Non-transient */ +#define MAIR_ATTR2 (0x44 << 16) /* Normal memory, Outer Non-cacheable, Inner Non-cacheable */ +#define MAIR_VAL (MAIR_ATTR2 | MAIR_ATTR1 | MAIR_ATTR0) + +#define SUP_EXCEPTION (0x2U) +#define HYP_EXCEPTION (0x5U) +#define IRQ_EXCEPTION (0x6U) +#define FIQ_EXCEPTION (0x7U) + +#define RTOS_LOAD_NUM_1 (1) /* RTOS is RTOS#0 only. */ +#define RTOS_LOAD_NUM_3 (3) /* RTOS are RTOS#0, RTOS#1, and RTOS#2. */ + + .global Startup + .global Vector + .global dabt_report_exception + .global pabt_report_exception + + .extern dabort_error + .extern pabort_error + .extern Undefined_error + .extern handler_error + + .align 5 + +Vector: + b Startup /* Reset */ + b Undefined_Handler /* Undefined Instruction */ + b Supervisor_Handler /* Supervisor Call */ + b Prefetch_Handler /* Prefetch Abort */ + b Abort_Handler /* Data Abort */ + b HypTrap_Handler /* Hyp Trap */ + b IRQ_Handler /* IRQ interrupt */ + b FIQ_Handler /* FIQ interrupt */ + +/***************************************************************************** + * Reset Hander + *****************************************************************************/ +Startup: +/* initialize registers*/ + /* initialize registers*/ + mov r0, #0 + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 + mov r8, #0 + mov r9, #0 + mov r10, #0 + mov r11, #0 + mov r12, #0 + mov lr, #0 + + ldr r13, =__STACKS_END__ + +/* Instruction cache enable */ + mrc p15, 4, r0, c1, c0, 0 /* HSCTLR */ + mrc p15, 0, r1, c1, c0, 0 /* SCTLR */ + bic r0, r0, #SCTLR_M /* M=0 */ + bic r1, r1, #SCTLR_M /* M=0 */ + orr r0, r0, #SCTLR_I /* I=1 */ + orr r1, r1, #SCTLR_I /* I=1 */ + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + mcr p15, 4, r0, c1, c0, 0 /* HSCTLR */ + mcr p15, 0, r1, c1, c0, 0 /* SCTLR */ + isb + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + isb + +/* CR52_CONFIGURE_MPU */ + mrc p15, 0, r0, c10, c2, 0 /* Read MAIR0 into R0 */ + mrc p15, 4, r1, c10, c2, 0 /* Read HMAIR0 into R1 */ + ldr r0, =MAIR_VAL /* Set MAIR */ + ldr r1, =MAIR_VAL /* Set MAIR */ + mcr p15, 0, r0, c10, c2, 0 /* Write R0 to MAIR0 */ + mcr p15, 4, r1, c10, c2, 0 /* Write R1 to HMAIR0 */ + +/* region 0: 0x00000000~0x3FFFFFFF */ + ldr r0, =0x00000006 /* SH=b'00/AP=b'11/XN=b'0 */ + ldr r1, =0x3FFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 0 /* Write R0 into PRBAR0 */ + mcr p15, 0, r1, c6, c8, 1 /* Write R1 into PRLAR0 */ + mcr p15, 4, r0, c6, c8, 0 /* Write R0 into HPRBAR0 */ + mcr p15, 4, r1, c6, c8, 1 /* Write R1 into HPRLAR0 */ +/* region 1: 0x40000000~0xBFFFFFFF */ + ldr r0, =0x40000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xBFFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 4 /* Write R0 into PRBAR1 */ + mcr p15, 0, r1, c6, c8, 5 /* Write R1 into PRLAR1 */ + mcr p15, 4, r0, c6, c8, 4 /* Write R0 into HPRBAR1 */ + mcr p15, 4, r1, c6, c8, 5 /* Write R1 into HPRLAR1 */ +/* region 2: 0xC0000000~0xE3FFFFFF */ + ldr r0, =0xC0000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE3FFFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c9, 0 /* Write R0 into PRBAR2 */ + mcr p15, 0, r1, c6, c9, 1 /* Write R1 into PRLAR2 */ + mcr p15, 4, r0, c6, c9, 0 /* Write R0 into HPRBAR2 */ + mcr p15, 4, r1, c6, c9, 1 /* Write R1 into HPRLAR2 */ +/* region 3: 0xE4000000~0xE4FFFFFF */ + ldr r0, =0xE4000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE4FFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c9, 4 /* Write R0 into PRBAR3 */ + mcr p15, 0, r1, c6, c9, 5 /* Write R1 into PRLAR3 */ + mcr p15, 4, r0, c6, c9, 4 /* Write R0 into HPRBAR3 */ + mcr p15, 4, r1, c6, c9, 5 /* Write R1 into HPRLAR3 */ +/* region 4: 0xE5000000~0xE62FFFFF */ + ldr r0, =0xE5000003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE62FFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c10, 0 /* Write R0 into PRBAR4 */ + mcr p15, 0, r1, c6, c10, 1 /* Write R1 into PRLAR4 */ + mcr p15, 4, r0, c6, c10, 0 /* Write R0 into HPRBAR4 */ + mcr p15, 4, r1, c6, c10, 1 /* Write R1 into HPRLAR4 */ +/* region 5: 0xE6300000~0xE632FFFF */ + ldr r0, =0xE6300006 /* SH=b'00/AP=b'11/XN=b'0 */ + ldr r1, =0xE632FFC3 /* AttrIndx=1(Write-Through) */ + mcr p15, 0, r0, c6, c10, 4 /* Write R0 into PRBAR5 */ + mcr p15, 0, r1, c6, c10, 5 /* Write R1 into PRLAR5 */ + mcr p15, 4, r0, c6, c10, 4 /* Write R0 into HPRBAR5 */ + mcr p15, 4, r1, c6, c10, 5 /* Write R1 into HPRLAR5 */ +/* region 6: 0xE6330000~0xE635FFFF */ + ldr r0, =0xE6330003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xE635FFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c11, 0 /* Write R0 into PRBAR6 */ + mcr p15, 0, r1, c6, c11, 1 /* Write R1 into PRLAR6 */ + mcr p15, 4, r0, c6, c11, 0 /* Write R0 into HPRBAR6 */ + mcr p15, 4, r1, c6, c11, 1 /* Write R1 into HPRLAR6 */ +/* region 7: 0xE6360000~0xEB1FFFFF */ + ldr r0, =0xE6360003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xEB1FFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c11, 4 /* Write R0 into PRBAR7 */ + mcr p15, 0, r1, c6, c11, 5 /* Write R1 into PRLAR7 */ + mcr p15, 4, r0, c6, c11, 4 /* Write R0 into HPRBAR7 */ + mcr p15, 4, r1, c6, c11, 5 /* Write R1 into HPRLAR7 */ +/* region 8: 0xEB200000~0xEB3FFFFF */ + ldr r0, =0xEB200003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xEB3FFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c12, 0 /* Write R0 into PRBAR8 */ + mcr p15, 0, r1, c6, c12, 1 /* Write R1 into PRLAR8 */ + mcr p15, 4, r0, c6, c12, 0 /* Write R0 into HPRBAR8 */ + mcr p15, 4, r1, c6, c12, 1 /* Write R1 into HPRLAR8 */ +/* region 9: 0xEB400000~0xFFFFFFFF */ + ldr r0, =0xEB400003 /* SH=b'00/AP=b'01/XN=b'1 */ + ldr r1, =0xFFFFFFC1 /* AttrIndx=0(Device) */ + mcr p15, 0, r0, c6, c12, 4 /* Write R0 into PRBAR9 */ + mcr p15, 0, r1, c6, c12, 5 /* Write R1 into PRLAR9 */ + mcr p15, 4, r0, c6, c12, 4 /* Write R0 into HPRBAR9 */ + mcr p15, 4, r1, c6, c12, 5 /* Write R1 into HPRLAR9 */ + +/* CR52_SET_MPU_ON */ + mrc p15, 4, r0, c1, c0, 0 /* Read HSCTLR */ + mrc p15, 0, r1, c1, c0, 0 /* Read SCTLR */ + orr r0, r0, #SCTLR_M /* MPU enable */ + orr r1, r1, #SCTLR_M /* MPU enable */ + mcr p15, 4, r0, c1, c0, 0 /* Write HSCTLR */ + mcr p15, 0, r1, c1, c0, 0 /* Write SCTLR */ + isb + + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + isb + +/* Jump to physical address from mirror address */ + ldr r0, =JUMP_MAIN + bx r0 + +JUMP_MAIN: + ldr r0, =Vector + mcr p15, 4, r0, c12, c0, 0 /* HVBAR */ + +/* clear bss section */ + mov r0, #0x0 + ldr r1, =__BSS_START__ + ldr r2, =__BSS_SIZE__ +bss_loop: + subs r2, r2, #4 + bcc bss_end + str r0, [r1, +r2] + b bss_loop +bss_end: + +/* copy data section */ + ldr r0, =__DATA_COPY_START__ + ldr r1, =__DATA_START__ + ldr r2, =__DATA_SIZE__ +data_loop: + subs r2, r2, #4 + bcc data_end + ldr r3, [r0, +r2] + str r3, [r1, +r2] + b data_loop +data_end: + +/* Loader Main */ + bl loader_main + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* Keep return value from loader_main function (Boot address of RTOS#1) */ + mov r11, r0 +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +/* region 0: 0x00000000~0x3FFFFFFF */ + ldr r0, =0x00000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0x3FFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 0 /* Write R0 into PRBAR0 */ + mcr p15, 0, r1, c6, c8, 1 /* Write R1 into PRLAR0 */ + mcr p15, 4, r0, c6, c8, 0 /* Write R0 into HPRBAR0 */ + mcr p15, 4, r1, c6, c8, 1 /* Write R1 into HPRLAR0 */ +/* region 1: 0x40000000~0xBFFFFFFF */ + ldr r0, =0x40000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xBFFFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c8, 4 /* Write R0 into PRBAR1 */ + mcr p15, 0, r1, c6, c8, 5 /* Write R1 into PRLAR1 */ + mcr p15, 4, r0, c6, c8, 4 /* Write R0 into HPRBAR1 */ + mcr p15, 4, r1, c6, c8, 5 /* Write R1 into HPRLAR1 */ +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* region 2: 0xC0000000~0xE3FFFFFF */ +/* Change MPU setting for RTOS#1. */ + ldr r0, =0xC0000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE3FFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c9, 0 /* Write R0 into PRBAR2 */ + mcr p15, 0, r1, c6, c9, 1 /* Write R1 into PRLAR2 */ + mcr p15, 4, r0, c6, c9, 0 /* Write R0 into HPRBAR2 */ + mcr p15, 4, r1, c6, c9, 1 /* Write R1 into HPRLAR2 */ +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +/* region 3: 0xE4000000~0xE4FFFFFF */ + ldr r0, =0xE4000002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE4FFFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c9, 4 /* Write R0 into PRBAR3 */ + mcr p15, 0, r1, c6, c9, 5 /* Write R1 into PRLAR3 */ + mcr p15, 4, r0, c6, c9, 4 /* Write R0 into HPRBAR3 */ + mcr p15, 4, r1, c6, c9, 5 /* Write R1 into HPRLAR3 */ +/* region 5: 0xE6300000~0xE632FFFF */ + ldr r0, =0xE6300002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE632FFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c10, 4 /* Write R0 into PRBAR5 */ + mcr p15, 0, r1, c6, c10, 5 /* Write R1 into PRLAR5 */ + mcr p15, 4, r0, c6, c10, 4 /* Write R0 into HPRBAR5 */ + mcr p15, 4, r1, c6, c10, 5 /* Write R0 into HPRLAR5 */ +/* region 6: 0xE6330000~0xE635FFFF */ + ldr r0, =0xE6330002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xE635FFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c11, 0 /* Write R0 into PRBAR6 */ + mcr p15, 0, r1, c6, c11, 1 /* Write R1 into PRLAR6 */ + mcr p15, 4, r0, c6, c11, 0 /* Write R0 into HPRBAR6 */ + mcr p15, 4, r1, c6, c11, 1 /* Write R1 into HPRLAR6 */ +/* region 8: 0xEB200000~0xEB3FFFFF */ + ldr r0, =0xEB200002 /* SH=b'00/AP=b'01/XN=b'0 */ + ldr r1, =0xEB3FFFC5 /* AttrIndx=2(Non-Cacheable) */ + mcr p15, 0, r0, c6, c12, 0 /* Write R0 into PRBAR8 */ + mcr p15, 0, r1, c6, c12, 1 /* Write R1 into PRLAR8 */ + mcr p15, 4, r0, c6, c12, 0 /* Write R0 into HPRBAR8 */ + mcr p15, 4, r1, c6, c12, 1 /* Write R1 into HPRLAR8 */ + + isb + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */ + isb + +/* Instruction cache disable */ + mrc p15, 4, r0, c1, c0, 0 /* Read HSCTLR */ + mrc p15, 0, r1, c1, c0, 0 /* Read SCTLR */ + bic r0, r0, #SCTLR_I /* I=0 */ + bic r1, r1, #SCTLR_I /* I=0 */ + mcr p15, 4, r0, c1, c0, 0 /* Write HSCTLR */ + mcr p15, 0, r1, c1, c0, 0 /* Write SCTLR */ + mcr p15, 0, r0, c7, c5, 0 /* ICIALLU */ + isb + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) +/* Jump to RTOS#1 */ + bx r11 +#elif (RTOS_LOAD_NUM == RTOS_LOAD_NUM_1) +loader_end: + wfi + b loader_end +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ + +anker: + wfi + b anker + +/* Undefined Instruction */ +Undefined_Handler: + mrs r0, ELR_hyp + b Undefined_error + +/* Supervisor Call */ +Supervisor_Handler: + mov r0, #SUP_EXCEPTION + b handler_error + +/* Prefetch Abort */ +Prefetch_Handler: + b pabt_report_exception + +/* Data Abort */ +Abort_Handler: + mrs r0, ELR_hyp + b dabt_report_exception + +/* Hyp Trap */ +HypTrap_Handler: + mov r0, #HYP_EXCEPTION + b handler_error + +/*IRQ interrupt */ +IRQ_Handler: + mov r0, #IRQ_EXCEPTION + b handler_error + +/* FIQ interrupt */ +FIQ_Handler: + mov r0, #FIQ_EXCEPTION + b handler_error + +/******************************************************** + * abort exception + ********************************************************/ +dabt_report_exception: + mrc p15, 0, r1, c5, c0, 0 /* Read DFSR */ + mrc p15, 0, r2, c6, c0, 0 /* Read DFAR */ + b dabort_error + +pabt_report_exception: + mrc p15, 0, r0, c5, c0, 1 /* Read IFSR */ + mrc p15, 0, r1, c6, c0, 2 /* Read IFAR */ + b pabort_error + + .end diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4m.ld b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4m.ld new file mode 100644 index 0000000..bd7f0a2 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/loader_v4m.ld @@ -0,0 +1,129 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2023 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Loader linker directive + ******************************************************************************/ +/****************************************************************************** + * @file loader_v4m.ld + * - Version : 0.01 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 21.08.2023 0.01 First Release + *****************************************************************************/ + +OUTPUT_FORMAT("elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(Startup) + +MEMORY { + SYSRAM (rwxa): ORIGIN = 0xE6300000, LENGTH = 0x00030000 + CXIPLDATA (rwa): ORIGIN = 0xE6330000, LENGTH = 0x00003000 + CXIPLSTACK (rwa): ORIGIN = 0xE6333000, LENGTH = 0x00002000 + SHARED_RAM (rwa): ORIGIN = 0x41C00000, LENGTH = 0x0000C000 + SHARED_SDRAM (rwa): ORIGIN = 0x41E00000, LENGTH = 0x00200000 +} + +SECTIONS +{ + .loader_start : { + __RO_START__ = .; + build/obj/loader/loader_v4m.o(.text*) + . = NEXT(1024); + *(.vectors) + . = ALIGN(4096); + } > SYSRAM + + .loader_ro : { + *(.text*) + *(.rodata*) + . = ALIGN(8); + __CONST_START__ = .; + . = ALIGN(16); + *(.qoswt_tbl) + . = ALIGN(8); + *(.qosbw_tbl) + . = ALIGN(8); + *(.constdata.CONFIG_DATA) + . = ALIGN(8); + *(.rgid_w_tbl) + . = ALIGN(8); + *(.rgid_r_tbl) + . = ALIGN(8); + *(.rgid_m_tbl) + . = ALIGN(8); + *(.rgid_sec_tbl) + . = ALIGN(8); + *(.rgid_axi_tbl) + __RO_END_UNALIGNED__ = .; + . = NEXT(4096); + __RO_END__ = .; + __DATA_COPY_START__ = .; + } > SYSRAM + + .data : { + __DATA_START__ = .; + *(.data*) + . = NEXT(16); + __DATA_END__ = .; + } > CXIPLDATA AT > SYSRAM + + __DATA_SIZE__ = SIZEOF(.data); + + stacks (NOLOAD) : ALIGN(16) { + __STACKS_START__ = .; + KEEP(*(Cx_loader_stack)) + __STACKS_END__ = .; + } > CXIPLSTACK + + .bss.SHARED_TOP : { + __SHARED_TOP_START__ = .; + *(.bss.SHARED_TOP) + *(.bss.SHARED_LCS) + *(.bss.SHARED_CMAC) + *(.bss.SHARED_HASH) + . = NEXT(0x00200000); + __SHARED__END__ = .; + } > SHARED_SDRAM + + .SHARED_RAM : { + __FWRAM_START__ = .; + . += 0; + . = NEXT(0x0000C000); + __FWRAM_END__ = .; + } > SHARED_RAM + + .bss : ALIGN(16) { + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + __BSS_END__ = .; + } > CXIPLDATA + + __BSS_SIZE__ = SIZEOF(.bss); +} diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/stack.S b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/stack.S new file mode 100644 index 0000000..7fe0238 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/loader/stack.S @@ -0,0 +1,48 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2022 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Make up stack space + ******************************************************************************/ +/****************************************************************************** + * @file stack.S + * - Version : 0.04 + * @brief + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 02.02.2022 0.01 First Release + * : 21.02.2022 0.02 Changed stacks name + * : 09.05.2022 0.03 Changed stacks name + * : 31.10.2022 0.04 License notation change. + *****************************************************************************/ + + .section Cx_loader_stack, "aw", %nobits + .align 5 +stacks: + .space (8*1024), 0 + + .end diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/protect/region_id/region_id.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/protect/region_id/region_id.c new file mode 100644 index 0000000..0db7396 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/protect/region_id/region_id.c @@ -0,0 +1,439 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : Access protection Function function + ******************************************************************************/ + /****************************************************************************** + * @file region_id.c + * - Version : 0.05 + * @brief Each module to R/W access protection by Region ID. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 15.12.2022 0.01 First Release + * : 24.02.2023 0.02 Polling the RGID setting process finish + * : 23.01.2024 0.03 Added ram_protection_check function. + * : 31.01.2024 0.04 Fixed the error in SECDIVn register + * calculating value. + * : 06.01.2025 0.05 Added reading back IMP Region ID register + * value. + * Added reading back IPMMU Region ID register + * value. + *****************************************************************************/ + +#include +#include "access_protection.h" +#include "axmm_register.h" +#include "cnf_tbl.h" +#include "mem_io.h" +#include "log.h" +#include "rtvram_register.h" + +#define RGID_SET_RGID_FIN_FLG_ADDR (0xE635EFFCU) +#define RGID_SET_RGID_FIN_FLG_VAL (0x64U) + +/* RAM protection for RT-VRAM0/RT-VRAM1 */ +#define SHIFT_FOR_SECDIVD (12U) +/* RAM protection for System RAM */ +#define SHIFT_FOR_SPTDIVCR (12U) +/* RAM protection for SDRAM */ +#define SHIFT_FOR_DPTDIVCR (16U) + +/* Value for calculating the offset address to set in SECDIVD. */ +#define RTSRAM_SECDIVD_SUBVALUE (0xE0000000U) /* RT-VRAM0 Base address */ +#define RTVRAM_SECDIVD_SUBVALUE (0xE2000000U) /* RT-VRAM1 Base address */ + +#define RTSRAM_ADDR_OFFSET_MASK (0xFFFFF000U) +#define RTVRAM_ADDR_MASK (0xFFFFF000U) + +void rgid_protection_check(void) +{ + uint32_t loop; + uint32_t reg; + + /* Polling until RGID setting completion flag is set by ICUMX IPL. */ + do{ + reg = mem_read8(RGID_SET_RGID_FIN_FLG_ADDR); + } while(reg != RGID_SET_RGID_FIN_FLG_VAL); + + for(loop = 0U; loop < RGID_MASTER_MAX; loop++) + { + /* Get RGIDM_MODID value */ + reg = mem_read32((uintptr_t)g_rgid_master_tbl[loop].phys_addr); /* Read */ + if (reg != g_rgid_master_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("RGIDM_MODID:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_rgid_master_tbl[loop].phys_addr, reg, g_rgid_master_tbl[loop].value); + panic; + } + } + + for(loop = 0U; loop < RGID_READ_MAX; loop++) + { + /* Get RGIDR_MODID value */ + reg = mem_read32((uintptr_t)g_rgid_read_tbl[loop].phys_addr); /* Read */ + if (reg != g_rgid_read_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("RGIDR_MODID:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_rgid_read_tbl[loop].phys_addr, reg, g_rgid_read_tbl[loop].value); + panic; + } + } + + for(loop = 0U; loop < RGID_WRITE_MAX; loop++) + { + /* Get RGIDW_MODID value */ + reg = mem_read32((uintptr_t)g_rgid_write_tbl[loop].phys_addr); /* Read */ + if (reg != g_rgid_write_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("RGIDW_MODID:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_rgid_write_tbl[loop].phys_addr, reg, g_rgid_write_tbl[loop].value); + panic; + } + } + + for(loop = 0U; loop < RGID_SEC_MAX; loop++) + { + /* Get SEC_MODID value */ + reg = mem_read32((uintptr_t)g_rgid_sec_tbl[loop].phys_addr); /* Read */ + if (reg != g_rgid_sec_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("SEC_MODID:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_rgid_sec_tbl[loop].phys_addr, reg, g_rgid_sec_tbl[loop].value); + panic; + } + } + + for(loop = 0U; loop < RGID_AXI_MAX; loop++) + { + /* Get AXI_MODID value */ + reg = mem_read32((uintptr_t)g_rgid_axi_tbl[loop].phys_addr); /* Read */ + if (reg != g_rgid_axi_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("AXI_MODID:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_rgid_axi_tbl[loop].phys_addr, reg, g_rgid_axi_tbl[loop].value); + panic; + } + } + +#if (RCAR_LSI == RCAR_V4H) + for(loop = 0U; loop < IMP_MASTER_MAX; loop++) + { + /* Get IMP Region ID Master value */ + reg = mem_read32((uintptr_t)g_imp_rgid_m_tbl[loop].phys_addr); /* Read */ + if (reg != g_imp_rgid_m_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("IMP_RGID_MASTER:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_imp_rgid_m_tbl[loop].phys_addr, reg, g_imp_rgid_m_tbl[loop].value); + panic; + } + } + + for(loop = 0U; loop < IMP_SLAVE_MAX; loop++) + { + /* Get IMP Region ID Slave value */ + reg = mem_read32((uintptr_t)g_imp_rgid_s_tbl[loop].phys_addr); /* Read */ + if (reg != g_imp_rgid_s_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("IMP_RGID_SLAVE:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_imp_rgid_s_tbl[loop].phys_addr, reg, g_imp_rgid_s_tbl[loop].value); + panic; + } + } +#endif /* (RCAR_LSI == RCAR_V4H) */ + + for(loop = 0U; loop < IPMMU_RGID_MAX; loop++) + { + /* Get IPMMU Region ID */ + reg = mem_read32((uintptr_t)g_ipmmu_rgid_tbl[loop].phys_addr); /* Read */ + if (reg != g_ipmmu_rgid_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("IMRGID_IPMMU:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_ipmmu_rgid_tbl[loop].phys_addr, reg, g_ipmmu_rgid_tbl[loop].value); + panic; + } + } + + for(loop = 0U; loop < IPMMU_RGID_MAX; loop++) + { + /* Get IPMMU Region ID Secure */ + reg = mem_read32((uintptr_t)g_ipmmu_rgid_sec_tbl[loop].phys_addr); /* Read */ + if (reg != g_ipmmu_rgid_sec_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("IMSECGRP_IPMMU:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_ipmmu_rgid_sec_tbl[loop].phys_addr, reg, g_ipmmu_rgid_sec_tbl[loop].value); + panic; + } + } + + for(loop = 0U; loop < IPMMU_RGID_MAX; loop++) + { + /* Get IPMMU Region ID Enable */ + reg = mem_read32((uintptr_t)g_ipmmu_rgid_en_tbl[loop].phys_addr); /* Read */ + if (reg != g_ipmmu_rgid_en_tbl[loop].value) + { + ERROR("Region ID check error.\n"); + ERROR("IMRGIDEN_IPMMU:%d 0x%x value = 0x%x expected value = 0x%x.\n", loop, + g_ipmmu_rgid_en_tbl[loop].phys_addr, reg, g_ipmmu_rgid_en_tbl[loop].value); + panic; + } + } + +} +/* End of function rgid_protection_check(void) */ + +void ram_protection_check(void) +{ + uint32_t loop; + uint32_t expect_val; + uint32_t area_addr; + uint32_t area_reg_val; + /* For RT-VRAM0 / RT-VRAM1 */ + uint32_t read_addr; + uint32_t read_reg_val; + uint32_t write_addr; + uint32_t write_reg_val; + /* For System RAM / SDRAM */ + uint32_t rw_addr; + uint32_t rw_reg_val; + uint32_t sec_addr; + uint32_t sec_reg_val; + + /* Check RAM protection for RT-VRAM0 */ + /* Check SECDIV[n]D_0 register */ + for (loop = 0; loop < RAM_PROTECTION_MAX - 1U; loop++) + { + area_addr = get_rtvram0_secdivd_addr(loop); + area_reg_val = mem_read32((uintptr_t)area_addr); + expect_val = g_rtvram0_protection_table[loop + 1U].addr - RTSRAM_SECDIVD_SUBVALUE; + expect_val = ((expect_val & RTSRAM_ADDR_OFFSET_MASK) >> 12U); + + if (area_reg_val != expect_val) + { + ERROR("RAM protection check error\n"); + ERROR("SECDIVnD_0:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , area_addr + , area_reg_val + , expect_val); + panic; + } + } + + + /* Check SECCTRR[m]D_0 / SECCTRW[m]D_0 register */ + for (loop = 0; loop < RAM_PROTECTION_MAX; loop++) + { + read_addr = get_rtvram0_secctrrd_addr(loop); + read_reg_val = mem_read32((uintptr_t)read_addr); + write_addr = get_rtvram0_secctrwd_addr(loop); + write_reg_val = mem_read32((uintptr_t)write_addr); + + if (read_reg_val != g_rtvram0_protection_table[loop].setting_value.read_val) + { + ERROR("RAM protection check error\n"); + ERROR("SECCTRRmD_0:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , read_addr + , read_reg_val + , g_rtvram0_protection_table[loop].setting_value.read_val); + panic; + } + if (write_reg_val != g_rtvram0_protection_table[loop].setting_value.write_val) + { + ERROR("RAM protection check error\n"); + ERROR("SECCTRWmD_0:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , write_addr + , write_reg_val + , g_rtvram0_protection_table[loop].setting_value.write_val); + panic; + } + } + + /* Check RAM protection for RT-VRAM1 */ + /* Check SECDIV[n]D_1 register */ + for (loop = 0; loop < RAM_PROTECTION_MAX - 1U; loop++) + { + area_addr = get_rtvram1_secdivd_addr(loop); + area_reg_val = mem_read32((uintptr_t)area_addr); + expect_val = g_rtvram1_protection_table[loop + 1U].addr - RTVRAM_SECDIVD_SUBVALUE; + expect_val = ((expect_val & RTVRAM_ADDR_MASK) >> 12U); + + if (area_reg_val != expect_val) + { + ERROR("RAM protection check error\n"); + ERROR("SECDIVnD_1:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , area_addr + , area_reg_val + , expect_val); + panic; + } + } + + /* Check SECCTRR[m]D_1 / SECCTRW[m]D_1 register */ + for (loop = 0; loop < RAM_PROTECTION_MAX; loop++) + { + read_addr = get_rtvram1_secctrrd_addr(loop); + read_reg_val = mem_read32((uintptr_t)read_addr); + write_addr = get_rtvram1_secctrwd_addr(loop); + write_reg_val = mem_read32((uintptr_t)write_addr); + + if (read_reg_val != g_rtvram1_protection_table[loop].setting_value.read_val) + { + ERROR("RAM protection check error\n"); + ERROR("SECCTRRmD_1:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , read_addr + , read_reg_val + , g_rtvram1_protection_table[loop].setting_value.read_val); + panic; + } + if (write_reg_val != g_rtvram1_protection_table[loop].setting_value.write_val) + { + ERROR("RAM protection check error\n"); + ERROR("SECCTRWmD_1:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , write_addr + , write_reg_val + , g_rtvram1_protection_table[loop].setting_value.write_val); + panic; + } + } + + /* Check RAM protection for System RAM */ + /* Check SPTDIVCR[n] register */ + for (loop = 0; loop < RAM_PROTECTION_MAX - 1U; loop++) + { + area_addr = get_sptdivcr_addr(loop); + area_reg_val = mem_read32((uintptr_t)area_addr); + + if (area_reg_val != (g_system_ram_protection_table[loop + 1U].addr >> SHIFT_FOR_SPTDIVCR)) + { + ERROR("RAM protection check error\n"); + ERROR("SPTDIVCR:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , area_addr + , area_reg_val + , (g_system_ram_protection_table[loop + 1U].addr >> SHIFT_FOR_SPTDIVCR)); + panic; + } + } + + /* Check SPTRGNCR[n] / SPTSECCR[n] register */ + for (loop = 0; loop < RAM_PROTECTION_MAX; loop++) + { + rw_addr = get_sptrgncr_addr(loop); + rw_reg_val = mem_read32((uintptr_t)rw_addr); + sec_addr = get_sptseccr_addr(loop); + sec_reg_val = mem_read32((uintptr_t)sec_addr); + + if (rw_reg_val != g_system_ram_protection_table[loop].setting_value.rw_val) + { + ERROR("RAM protection check error\n"); + ERROR("SPTRGNCR:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , rw_addr + , rw_reg_val + , g_system_ram_protection_table[loop].setting_value.rw_val); + panic; + } + if (sec_reg_val != g_system_ram_protection_table[loop].setting_value.sec_val) + { + ERROR("RAM protection check error\n"); + ERROR("SPTSECCR:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , sec_addr + , sec_reg_val + , g_system_ram_protection_table[loop].setting_value.sec_val); + panic; + } + } + + /* Check RAM protection for SDRAM */ + /* Check DPTDIVCR[n] register */ + for (loop = 0; loop < DRAM_PROTECTION_MAX - 1U; loop++) + { + area_addr = get_dptdivcr_addr(loop); + area_reg_val = mem_read32((uintptr_t)area_addr); + + if (area_reg_val != (g_dram_protection_table[loop + 1U].addr >> SHIFT_FOR_DPTDIVCR)) + { + ERROR("RAM protection check error\n"); + ERROR("DPTDIVCR:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , area_addr + , area_reg_val + , (g_dram_protection_table[loop + 1U].addr >> SHIFT_FOR_DPTDIVCR)); + panic; + } + } + + /* Check DPTRGNCR[n] / DPTSECCR[n] register */ + for (loop = 0; loop < DRAM_PROTECTION_MAX; loop++) + { + rw_addr = get_dptrgncr_addr(loop); + rw_reg_val = mem_read32((uintptr_t)rw_addr); + sec_addr = get_dptseccr_addr(loop); + sec_reg_val = mem_read32((uintptr_t)sec_addr); + + if (rw_reg_val != g_dram_protection_table[loop].setting_value.rw_val) + { + ERROR("RAM protection check error\n"); + ERROR("DPTRGNCR:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , rw_addr + , rw_reg_val + , g_dram_protection_table[loop].setting_value.rw_val); + panic; + } + if (sec_reg_val != g_dram_protection_table[loop].setting_value.sec_val) + { + ERROR("RAM protection check error\n"); + ERROR("DPTSECCR:%d 0x%x value=0x%x expected value=0x%x\n" + , loop + , sec_addr + , sec_reg_val + , g_dram_protection_table[loop].setting_value.sec_val); + panic; + } + } + +} +/* End of function ram_protection_check(void) */ + + diff --git a/IPL/SDK/v4h/src/V4H_Cx_Loader/secure/secure_boot.c b/IPL/SDK/v4h/src/V4H_Cx_Loader/secure/secure_boot.c new file mode 100644 index 0000000..a6e8921 --- /dev/null +++ b/IPL/SDK/v4h/src/V4H_Cx_Loader/secure/secure_boot.c @@ -0,0 +1,507 @@ +/******************************************************************************* +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only +* intended for use with Renesas products. No other uses are authorized. This +* software is owned by Renesas Electronics Corporation and is protected under +* all applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT +* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE +* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. +* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS +* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE +* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR +* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE +* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software +* and to discontinue the availability of this software. By using this software, +* you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* Copyright 2018-2025 Renesas Electronics Corporation All rights reserved. +*******************************************************************************/ + + + +/******************************************************************************* + * DESCRIPTION : ICUMIF control function + ******************************************************************************/ +/****************************************************************************** + * @file secure_boot.c + * - Version : 0.08 + * @brief ICUMIF controller. + * . + *****************************************************************************/ +/****************************************************************************** + * History : DD.MM.YYYY Version Description + * : 16.06.2022 0.01 First Release + * : 22.07.2022 0.02 Change CMAC address settings + * Added include file + * Changed for Warning measures + * : 31.10.2022 0.03 License notation change. + * : 07.12.2022 0.04 Warning support when log output is disabled + * : 15.02.2023 0.05 Added final_hash_cmp function. + * : 04.04.2023 0.06 Removed stdio.h. + * : 21.08.2023 0.07 Add support for V4M. + * : 14.01.2024 0.08 Add parameter setting process for RTOS#1/#2. + *****************************************************************************/ +#include "log.h" +#include "timer.h" +#include "r_icumif_api.h" +#include "r_icumif_pub.h" +#include "icum_d_comm_pe_pub.h" +#include "shared.h" +#include "image_load.h" +#include "secure_boot.h" +#include "rst_register.h" + +#define LCS_CM (0x00000000U) /* CM */ +#define LCS_DM (0x00000001U) /* DM */ +#define LCS_SD (0x00000003U) /* SD */ +#define LCS_SE (0x00000005U) /* SE */ +#define LCS_FA (0x00000007U) /* FA */ + +#define RST_MODEMR0_MD5 (0x00000020U) + +#define CX_CMAC_COPY (4U) +#define CX_ICUMIF_STATUS (0x1000F800UL) +#define CX_SIZEOF_CNT (4U) +#define CX_CMAC_SIZE (16U) + +/* Definitions for hash_cmp */ +#define HASH_CMP_NUM (0x2U) /* The number of hash check images */ +#define HASH_SIZE (32U) /* Hash size (32-bytes) */ +#define CR52_IPL_HASH_SAVE_ADDR (0xE635FF40U) /* Hash save address for CR52 IPL */ +#define SECURE_FW_HASH_SAVE_ADDR (0xE635FFC0U) /* Hash save address for Secure FW */ + +static void secureboot_memset(void *buff, uint32_t data, uint32_t cnt); +static void secureboot_service(r_icumif_isd_t *p_ISD); + +void secureboot_init(void) +{ + int32_t r_errno; + volatile uint32_t *status; + + status = (volatile uint32_t *)R_ICUMIF_GetStatus(); + + /* Wait until the ICU-M system intialization is complete */ + while(true) + { + if((*status & CX_ICUMIF_STATUS) != 0UL) + { + break; + } + else + { + micro_wait(100U); /* 100 micro sec */ + } + } + + r_errno = R_ICUMIF_Init((uint32_t *)((uintptr_t)MEM_INFO_SERVICEQUE_1_ADDR)); + if(r_errno != R_ICUMIF_ER_OK) + { + ERROR("R_ICUMIF_Init:Error code = (0x%x).\n", (unsigned int)r_errno); + panic; + } + +} +/* End of function secureboot_init(void) */ + +uint32_t judge_bootmode(void) +{ + uint32_t *p_lcs; + r_icumif_isd_t *p_ISD; + uint32_t md; + uint32_t is_verify = SECURE_BOOT; + + __attribute__((unused))const char *lcs_name[8U] = { + [LCS_CM] = "CM", + [LCS_DM] = "DM", + [LCS_SD] = "SD", + [LCS_SE] = "SE", + [LCS_FA] = "FA", + }; + + secureboot_memset(ISD_BUFFER, 0U, SIZE_OF_ISD_BUFFER); + secureboot_memset(LCS_BUFFER, 0U, SIZE_OF_LCS_BUFFER); + + /* initialize the global icum service header */ + p_ISD = (r_icumif_isd_t *)ISD_BUFFER; + p_lcs = (uint32_t *)LCS_BUFFER; + + p_ISD->service_id = SERVICE_00_SECURE_BOOT_API; + p_ISD->ptr.p_callbackfunc = NULL; + p_ISD->job_id = 0U; + p_ISD->res_nointerrupt = R_ICUMIF_REQRES_NOINTERRPUT; + + p_ISD->prm.SECURE_BOOT_API.boot_api_id = ROM_GET_LCS; + p_ISD->prm.SECURE_BOOT_API.api.get_lcs.ptr.p_lcs = p_lcs; + p_ISD->prm.SECURE_BOOT_API.api.get_lcs.lcs_size_in_bytes = SIZE_OF_LCS_BUFFER; + + /* trigger the service request */ + secureboot_service(p_ISD); + + if(ROMAPI_OK != p_ISD->prm.SECURE_BOOT_API.api_return_value) + { + ERROR("SECURE_BOOT_API:Error code = (0x%x).\n", + (unsigned int)p_ISD->prm.SECURE_BOOT_API.api_return_value); + panic; + } + else + { + /* LCM Status check */ + if(( LCS_CM != *p_lcs) + && ( LCS_DM != *p_lcs) + && ( LCS_SD != *p_lcs) + && ( LCS_SE != *p_lcs) + && ( LCS_FA != *p_lcs)) + { + ERROR("LCM state error. LCS = 0x%x\n", (unsigned int)*p_lcs ); + panic; + } + else + { + NOTICE("LCM state is %s\n",lcs_name[*p_lcs]); + } + } + + md = (mem_read32(RST_MODEMR0) & RST_MODEMR0_MD5) >> 5U; + + if (LCS_SD == *p_lcs) + { + /* LCS=SD => Normal boot */ + is_verify = NORMAL_BOOT; + } + else if ((LCS_SE != *p_lcs) && ( 1U == md)) + { + /* LCS=CM/DM/FA and MD5=1 => Normal boot */ + is_verify = NORMAL_BOOT; + } + else + { + /* LCS=SE => Secure boot */ + /* LCS=CM/DM/FA and MD5=0 => Secure boot */ + is_verify = SECURE_BOOT; + } + + if (NORMAL_BOOT != is_verify) + { +#if (RCAR_LSI == RCAR_S4) + NOTICE("Secure boot(CA55 Loader)\n"); +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + NOTICE("Secure boot(CR52 Loader)\n"); +#endif /* RCAR_LSI == RCAR_S4 */ + } + else + { +#if (RCAR_LSI == RCAR_S4) + NOTICE("Normal boot(CA55 Loader)\n"); +#elif ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + NOTICE("Normal boot(CR52 Loader)\n"); +#endif /* RCAR_LSI == RCAR_S4 */ + } + + return is_verify; + +} +/* End of function judge_bootmode(void) */ + +void secureboot_verify(LOAD_INFO* li, uint32_t num) +{ + uint32_t *p_cmac; + r_icumif_isd_t *p_ISD; + uint32_t loop; + uint32_t i; + volatile uintptr_t p_content_cert; + volatile uintptr_t p_key_cert; + + secureboot_memset(ISD_BUFFER, 0U, SIZE_OF_ISD_BUFFER); + + p_ISD = (r_icumif_isd_t *)ISD_BUFFER; + + /* Set Load info parameter */ + for (loop = CA_OPTIONAL_ID; loop < CA_OPTIONAL_ID + num; loop++) + { + secureboot_memset(CMAC_BUFFER, 0U, SIZE_OF_CMAC_BUFFER); + p_cmac = (uint32_t *)CMAC_BUFFER; + p_ISD->service_id = SERVICE_00_SECURE_BOOT_API; + p_ISD->ptr.p_callbackfunc = NULL; + p_ISD->job_id = 0U; + p_ISD->res_nointerrupt = R_ICUMIF_REQRES_NOINTERRPUT; + + p_ISD->prm.SECURE_BOOT_API.boot_api_id + = ROM_SECURE_BOOT_VERIFY; + p_key_cert = li[loop].key_cert_addr; + p_content_cert = li[loop].cnt_cert_addr; + + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr1.p_key_cert = (uint32_t*)p_key_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr2.p_content_cert = (uint32_t*)p_content_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr3.p_cmac = p_cmac; + + /* trigger the service request */ + secureboot_service(p_ISD); + if(ROMAPI_OK != p_ISD->prm.SECURE_BOOT_API.api_return_value) + { + ERROR("SECURE_BOOT_API:Error code = (0x%x).\n", + (unsigned int)p_ISD->prm.SECURE_BOOT_API.api_return_value); + panic; + } + else + { + for (i = 0U; i < CX_CMAC_COPY; i++) + { + li[loop].cmac[i] = *(p_cmac++); + } + } + } + +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + /* Set Load info parameter */ + /* For RTOS#0 */ + secureboot_memset(CMAC_BUFFER, 0U, CX_CMAC_SIZE); + p_cmac = (uint32_t *)CMAC_BUFFER; + p_ISD->service_id = SERVICE_00_SECURE_BOOT_API; + p_ISD->ptr.p_callbackfunc = NULL; + p_ISD->job_id = 0U; + p_ISD->res_nointerrupt = R_ICUMIF_REQRES_NOINTERRPUT; + + p_ISD->prm.SECURE_BOOT_API.boot_api_id + = ROM_SECURE_BOOT_VERIFY; + p_key_cert = li[RTOS_ID].key_cert_addr; + p_content_cert = li[RTOS_ID].cnt_cert_addr; + + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr1.p_key_cert = (uint32_t*)p_key_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr2.p_content_cert = (uint32_t*)p_content_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr3.p_cmac = p_cmac; + + /* trigger the service request */ + secureboot_service(p_ISD); + if(ROMAPI_OK != p_ISD->prm.SECURE_BOOT_API.api_return_value) + { + ERROR("SECURE_BOOT_API:Error code = (0x%x).\n", + (unsigned int)p_ISD->prm.SECURE_BOOT_API.api_return_value); + panic; + } + else + { + for (i = 0U; i < CX_CMAC_COPY; i++) + { + li[RTOS_ID].cmac[i] = *(p_cmac++); + } + } + +#if (RTOS_LOAD_NUM == RTOS_LOAD_NUM_3) + /* For RTOS#1,RTOS#2 */ + for (loop = RTOS1_ID; loop <= RTOS2_ID; loop++) + { + secureboot_memset(CMAC_BUFFER, 0U, CX_CMAC_SIZE); + p_cmac = (uint32_t *)CMAC_BUFFER; + p_ISD->service_id = SERVICE_00_SECURE_BOOT_API; + p_ISD->ptr.p_callbackfunc = NULL; + p_ISD->job_id = 0U; + p_ISD->res_nointerrupt = R_ICUMIF_REQRES_NOINTERRPUT; + + p_ISD->prm.SECURE_BOOT_API.boot_api_id + = ROM_SECURE_BOOT_VERIFY; + p_key_cert = li[loop].key_cert_addr; + p_content_cert = li[loop].cnt_cert_addr; + + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr1.p_key_cert = (uint32_t*)p_key_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr2.p_content_cert = (uint32_t*)p_content_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_verify.ptr3.p_cmac = p_cmac; + + /* trigger the service request */ + secureboot_service(p_ISD); + if(ROMAPI_OK != p_ISD->prm.SECURE_BOOT_API.api_return_value) + { + ERROR("SECURE_BOOT_API:Error code = (0x%x).\n", + (unsigned int)p_ISD->prm.SECURE_BOOT_API.api_return_value); + panic; + } + else + { + for (i = 0U; i < CX_CMAC_COPY; i++) + { + li[loop].cmac[i] = *(p_cmac++); + } + } + } +#endif /* RTOS_LOAD_NUM == RTOS_LOAD_NUM_3 */ +#endif /* RCAR_LSI == RCAR_V4H || RCAR_LSI == RCAR_V4M */ + +} +/* End of function secureboot_verify(void) */ + +void secureboot_image(LOAD_INFO* li) +{ + uint32_t *p_cmac; + uint32_t *p_hash; + r_icumif_isd_t *p_ISD; + uint32_t i; + volatile uintptr_t p_content_cert; + + secureboot_memset(ISD_BUFFER, 0U, SIZE_OF_ISD_BUFFER); + secureboot_memset(CMAC_BUFFER, 0U, SIZE_OF_CMAC_BUFFER); + secureboot_memset(HASH_BUFFER, 0U, SIZE_OF_HASH_BUFFER); + + /* initialize the global icum service header */ + p_ISD = (r_icumif_isd_t *)ISD_BUFFER; + p_cmac = (uint32_t *)CMAC_BUFFER; + p_hash = (uint32_t *)HASH_BUFFER; + + for (i = 0U; i < CX_CMAC_COPY; i++) + { + *(p_cmac++) = li->cmac[i]; + } + + p_ISD->service_id = SERVICE_00_SECURE_BOOT_API; + p_ISD->ptr.p_callbackfunc = NULL; + p_ISD->job_id = 0U; + p_ISD->res_nointerrupt = R_ICUMIF_REQRES_NOINTERRPUT; + + p_ISD->prm.SECURE_BOOT_API.boot_api_id = ROM_SECURE_BOOT_DECRYPT; + + p_content_cert = li->cnt_cert_addr; + + p_ISD->prm.SECURE_BOOT_API.api. + boot_decrypt.ptr1.p_content_cert = (uint32_t*)p_content_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_decrypt.ptr2.p_cmac = (uint32_t *)CMAC_BUFFER; + + /* trigger the service request */ + secureboot_service(p_ISD); + if(( ROMAPI_OK != p_ISD->prm.SECURE_BOOT_API.api_return_value) && + (ROM_ERR_IMG_VERIFIER_NO_ENCRYPT_IMG != p_ISD->prm.SECURE_BOOT_API.api_return_value)) + { + ERROR("SECURE_BOOT_API:Error code = (0x%x).\n", + (unsigned int)p_ISD->prm.SECURE_BOOT_API.api_return_value); + panic; + } + + p_ISD->service_id = SERVICE_00_SECURE_BOOT_API; + p_ISD->ptr.p_callbackfunc = NULL; + p_ISD->job_id = 0U; + p_ISD->res_nointerrupt = R_ICUMIF_REQRES_NOINTERRPUT; + + p_ISD->prm.SECURE_BOOT_API.boot_api_id = ROM_SECURE_BOOT_COMPARE; + + p_ISD->prm.SECURE_BOOT_API.api. + boot_compare.ptr1.p_content_cert = (uint32_t*)p_content_cert; + p_ISD->prm.SECURE_BOOT_API.api. + boot_compare.ptr2.p_hash = p_hash; + p_ISD->prm.SECURE_BOOT_API.api. + boot_compare.hash_size_in_bytes = SIZE_OF_HASH_BUFFER; + p_ISD->prm.SECURE_BOOT_API.api. + boot_compare.ptr3.p_cmac = (uint32_t *)CMAC_BUFFER; + + /* trigger the service request */ + secureboot_service(p_ISD); + if(ROMAPI_OK != p_ISD->prm.SECURE_BOOT_API.api_return_value) + { + ERROR("SECURE_BOOT_API:Error code = (0x%x).\n", + (unsigned int)p_ISD->prm.SECURE_BOOT_API.api_return_value); + panic; + } + +} +/* End of function secureboot_image(LOAD_INFO* li) */ + + +static void secureboot_memset(void *buff, uint32_t data, uint32_t cnt) +{ + uint32_t *tmp = NULL; + uint32_t loop = cnt / CX_SIZEOF_CNT; /* Copy 4 bytes at a time */ + tmp = (uint32_t *)buff; + + if (buff == NULL) + { + return; + } + + while (loop > 0U) + { + *tmp = data; + tmp++; + loop--; + } +}/* End of function secureboot_memset(void *buff, uint32_t data, uint32_t cnt) */ + +static void secureboot_service(r_icumif_isd_t *p_ISD) +{ + int32_t r_errno; + + /* trigger the service request */ + r_errno = R_ICUMIF_ServiceRequest(p_ISD); + if(R_ICUMIF_ER_OK != r_errno) + { + ERROR("R_ICUMIF_ServiceRequest:Error code = (0x%x).\n", (unsigned int)r_errno); + panic; + } + + /* wait for response */ + while(true) + { + r_errno = R_ICUMIF_IsServiceCompleted(p_ISD); + if(r_errno != R_ICUMIF_RTN_SERV_RUNNING) + { + break; + } + } + + if(SERV_OK != p_ISD->service_result) + { + ERROR("R_ICUMIF_IsServiceCompleted:Error code = (0x%x).\n", p_ISD->service_result); + panic; + } + + r_errno = R_ICUMIF_ServiceResponse(); + if(R_ICUMIF_ER_OK != r_errno) + { + ERROR("R_ICUMIF_ServiceResponse:Error code = (0x%x).\n", (unsigned int)r_errno); + panic; + } + +} +/* End of function secureboot_service(r_icumif_isd_t *p_ISD) */ + +void final_hash_cmp(void) +{ +#if ((RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M)) + uint32_t i; + uint32_t j; + uint8_t *hash1; + uint8_t *hash2; + uint32_t hash_addr[HASH_CMP_NUM] = {SECURE_FW_HASH_SAVE_ADDR, CR52_IPL_HASH_SAVE_ADDR}; + + for(i = 0U; i < HASH_CMP_NUM; i++) + { + /* Hash is placed SystemRAM by ICUMX IPL. */ + hash1 = (uint8_t *)(hash_addr[i]); + hash2 = (uint8_t *)(hash_addr[i] + HASH_SIZE); + + for(j = 0U; j < HASH_SIZE; j++) + { + /* Compare Hash */ + if(*hash1 != *hash2) + { + /* Hash unmatch. */ + ERROR("Final Hash compare error!!\n"); + panic; + } + hash1++; + hash2++; + } + } +#endif /* (RCAR_LSI == RCAR_V4H) || (RCAR_LSI == RCAR_V4M) */ +} +/* End of function final_hash_cmp(void) */ +